From a501e632867b65bbae7b668f98956672294bdcba Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 7 Jun 2022 01:18:02 -0700 Subject: [PATCH 001/286] init --- .gitignore | 2 + .gitmodules | 3 + build.zig | 51 + microzig | 1 + rp2040.ld | 58 + src/hal.zig | 20 + src/hal/clocks.zig | 438 + src/hal/gpio.zig | 153 + src/hal/pll.zig | 97 + src/raspberry_pi_pico.zig | 38 + src/rp2040.zig | 29422 ++++++++++++++++++++++++++++++++++++ 11 files changed, 30283 insertions(+) create mode 100644 .gitignore create mode 100644 .gitmodules create mode 100644 build.zig create mode 160000 microzig create mode 100644 rp2040.ld create mode 100644 src/hal.zig create mode 100644 src/hal/clocks.zig create mode 100644 src/hal/gpio.zig create mode 100644 src/hal/pll.zig create mode 100644 src/raspberry_pi_pico.zig create mode 100644 src/rp2040.zig diff --git a/.gitignore b/.gitignore new file mode 100644 index 000000000..4c82b07c0 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +zig-cache +zig-out diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 000000000..fdd0dab01 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "microzig"] + path = microzig + url = git@github.com:ZigEmbeddedGroup/microzig.git diff --git a/build.zig b/build.zig new file mode 100644 index 000000000..7bf7beaf8 --- /dev/null +++ b/build.zig @@ -0,0 +1,51 @@ +const std = @import("std"); + +const Builder = std.build.Builder; +const Pkg = std.build.Pkg; + +pub const BuildOptions = struct { + packages: ?[]const Pkg = null, +}; + +pub fn addPiPicoExecutable( + comptime microzig: type, + builder: *Builder, + name: []const u8, + source: []const u8, + options: BuildOptions, +) *std.build.LibExeObjStep { + const rp2040 = microzig.Chip{ + .name = "RP2040", + .path = root() ++ "src/rp2040.zig", + .cpu = microzig.cpus.cortex_m0plus, + .memory_regions = &.{ + .{ .kind = .flash, .offset = 0x10000100, .length = (2048 * 1024) - 256 }, + .{ .kind = .flash, .offset = 0x10000000, .length = 256 }, + .{ .kind = .ram, .offset = 0x20000000, .length = 256 * 1024 }, + }, + }; + + const raspberry_pi_pico = microzig.Board{ + .name = "Raspberry Pi Pico", + .path = root() ++ "src/raspberry_pi_pico.zig", + .chip = rp2040, + }; + + const ret = microzig.addEmbeddedExecutable( + builder, + name, + source, + .{ .board = raspberry_pi_pico }, + .{ + .packages = options.packages, + .hal_package_path = .{ .path = root() ++ "src/hal.zig" }, + }, + ) catch @panic("failed to create embedded executable"); + ret.setLinkerScriptPath(.{ .path = root() ++ "rp2040.ld" }); + + return ret; +} + +fn root() []const u8 { + return (std.fs.path.dirname(@src().file) orelse unreachable) ++ "/"; +} diff --git a/microzig b/microzig new file mode 160000 index 000000000..ac19b7de8 --- /dev/null +++ b/microzig @@ -0,0 +1 @@ +Subproject commit ac19b7de8eb1551e603b3ce23a4aab69c71d1216 diff --git a/rp2040.ld b/rp2040.ld new file mode 100644 index 000000000..f293543dc --- /dev/null +++ b/rp2040.ld @@ -0,0 +1,58 @@ +/* + * This file was auto-generated by microzig + * + * Target CPU: ARM Cortex-M0+ + * Target Chip: RP2040 + */ + +ENTRY(microzig_main); + +MEMORY +{ + flash0 (rx!w) : ORIGIN = 0x10000000, LENGTH = 0x00200000 + ram0 (rw!x) : ORIGIN = 0x20000000, LENGTH = 0x00040000 +} + +SECTIONS +{ + .boot2 : { + __boot2_start__ = .; + KEEP (*(.boot2)) + __boot2_end__ = .; + } > flash0 + + ASSERT(__boot2_end__ - __boot2_start__ == 256, + "ERROR: Pico second stage bootloader must be 256 bytes in size") + + .text : + { + KEEP(*(microzig_flash_start)) + *(.text*) + *(.rodata*) + } > flash0 + + .ARM.exidx : { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >flash0 + + .flash1 : + { + *(.flash1) + } > flash1 + + .data : + { + microzig_data_start = .; + *(.data*) + microzig_data_end = .; + } > ram0 AT> flash0 + + .bss (NOLOAD) : + { + microzig_bss_start = .; + *(.bss*) + microzig_bss_end = .; + } > ram0 + + microzig_data_load_start = LOADADDR(.data); +} diff --git a/src/hal.zig b/src/hal.zig new file mode 100644 index 000000000..41f474420 --- /dev/null +++ b/src/hal.zig @@ -0,0 +1,20 @@ +const microzig = @import("microzig"); +const regs = microzig.chip.regsisters; +pub const gpio = @import("hal/gpio.zig"); +pub const clocks = @import("hal/clocks.zig"); + +pub const default_clock_config = clocks.GlobalConfiguration.init(.{ + //.ref = .{ .source = .src_xosc }, + .sys = .{ + .source = .pll_sys, + .freq = 125_000_000, + }, + .usb = .{ .source = .pll_usb }, + //.adc = .{ .source = .pll_usb }, + //.rtc = .{ .source = .pll_usb }, + .peri = .{ .source = .clk_sys }, +}); + +pub fn getCpuId() u32 { + return regs.SIO.CPUID.*; +} diff --git a/src/hal/clocks.zig b/src/hal/clocks.zig new file mode 100644 index 000000000..7f266e299 --- /dev/null +++ b/src/hal/clocks.zig @@ -0,0 +1,438 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const pll = @import("pll.zig"); +const assert = std.debug.assert; + +const regs = microzig.chip.registers; +const xosc_freq = microzig.board.xosc_freq; +// TODO: move to board file +/// this is only nominal, very imprecise and prone to drift over time +const rosc_freq = 6_500_000; + +comptime { + assert(xosc_freq <= 15_000_000 and xosc_freq >= 1_000_000); // xosc limits +} + +pub const xosc = struct { + const startup_delay_ms = 1; + const startup_delay_value = xosc_freq * startup_delay_ms / 1000 / 256; + + pub fn init() void { + regs.XOSC.STARTUP.modify(.{ .DELAY = startup_delay_value }); + regs.XOSC.CTRL.modify(.{ .ENABLE = 4011 }); + + // wait for xosc startup to complete: + while (regs.XOSC.STATUS.read().STABLE == 0) {} + } + + pub fn waitCycles(value: u8) void { + assert(is_enabled: { + const status = regs.XOSC.STATUS.read(); + break :is_enabled status.STABLE != 0 and status.ENABLED != 0; + }); + + regs.XOSC.COUNT.modify(value); + while (regs.XOSC.COUNT.read() != 0) {} + } +}; + +fn formatUppercase( + bytes: []const u8, + comptime fmt: []const u8, + options: std.fmt.FormatOptions, + writer: anytype, +) !void { + _ = fmt; + _ = options; + for (bytes) |c| + try writer.writeByte(std.ascii.toUpper(c)); +} + +fn uppercase(bytes: []const u8) std.fmt.Formatter(formatUppercase) { + return .{ .data = bytes }; +} + +pub const Generator = enum { + gpout0, + gpout1, + gpout2, + gpout3, + ref, + sys, + peri, + usb, + adc, + rtc, + + // source directly from register definitions + const Source = enum { + rosc_clksrc_ph, + clksrc_clk_ref_aux, + xosc_clksrc, + clk_ref, + clksrc_clk_sys_aux, + }; + + // aux sources directly from register definitions + const AuxilarySource = enum { + clksrc_pll_sys, + clksrc_gpin0, + clksrc_gpin1, + clksrc_pll_usb, + rosc_clksrc, + xosc_clksrc, + clk_sys, + clk_usb, + clk_adc, + clk_rtc, + clk_ref, + rosc_clksrc_ph, + }; + + const source_map = struct { + const ref = [_]Generator.Source{ .rosc_clksrc_ph, .clksrc_clk_ref, .xosc_clksrc }; + const sys = [_]Generator.Source{ .clk_ref, .clksrc_clk_sys_aux }; + }; + + const aux_map = struct {}; + + pub fn hasGlitchlessMux(generator: Generator) bool { + return switch (generator) { + .sys, .ref => true, + else => false, + }; + } + + pub fn enable(generator: Generator) void { + inline for (std.meta.fields(Generator)) |field| { + if (generator == @field(Generator, field.name)) { + const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_CTRL", .{ + uppercase(field.name), + }); + + if (@hasField(@TypeOf(@field(regs.CLOCKS, reg_name).*).underlying_type, "ENABLE")) + @field(regs.CLOCKS, reg_name).modify(.{ .ENABLE = 1 }); + } + } + } + + pub fn setDiv(generator: Generator, div: u32) void { + inline for (std.meta.fields(Generator)) |field| { + if (generator == @field(Generator, field.name)) { + const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_DIV", .{ + uppercase(field.name), + }); + + if (@hasDecl(regs.CLOCKS, reg_name)) + @field(regs.CLOCKS, reg_name).raw = div + else + assert(false); // doesn't have a divider + } + } + } + + pub fn getDiv(generator: Generator) u32 { + return inline for (std.meta.fields(Generator)) |field| { + if (generator == @field(Generator, field.name)) { + const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_DIV", .{ + uppercase(field.name), + }); + + break if (@hasDecl(regs.CLOCKS, reg_name)) + @field(regs.CLOCKS, reg_name).raw + else + 1; + } + } else unreachable; + } + + // The bitfields for the *_SELECTED registers are actually a mask of which + // source is selected. While switching sources it may read as 0, and that's + // what this function is indended for: checking if the new source has + // switched over yet. + // + // Some mention that this is only for the glitchless mux, so if it is non-glitchless then return true + pub fn selected(generator: Generator) bool { + inline for (std.meta.fields(Generator)) |field| { + if (generator == @field(Generator, field.name)) { + return if (@field(Generator, field.name).hasGlitchlessMux()) ret: { + const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_SELECTED", .{ + uppercase(field.name), + }); + + break :ret @field(regs.CLOCKS, reg_name).* != 0; + } else true; + } + } else unreachable; + } +}; + +pub const Source = enum { + src_rosc, + src_xosc, + src_aux, + pll_sys, + pll_usb, + clk_sys, +}; + +pub const GlobalConfiguration = struct { + xosc_configured: bool, + sys: ?Configuration, + ref: ?Configuration, + usb: ?Configuration, + adc: ?Configuration, + rtc: ?Configuration, + peri: ?Configuration, + + pll_sys: ?pll.Configuration, + pll_usb: ?pll.Configuration, + + pub const Option = struct { + source: Source, + freq: ?u32 = null, + }; + + pub const Options = struct { + sys: ?Option = null, + ref: ?Option = null, + usb: ?Option = null, + adc: ?Option = null, + rtc: ?Option = null, + peri: ?Option = null, + // TODO: allow user to configure PLLs to optimize for low-jitter, low-power, or manually specify + }; + + /// this function reasons about how to configure the clock system. It will + /// assert if the configuration is invalid + pub fn init(comptime opts: Options) GlobalConfiguration { + var xosc_configured = false; + var pll_sys: ?pll.Configuration = null; + var pll_usb: ?pll.Configuration = null; + + return GlobalConfiguration{ + // the system clock can either use rosc, xosc, or the sys PLL + .sys = if (opts.sys) |sys_opts| sys_config: { + var output_freq: ?u32 = null; + break :sys_config .{ + .generator = .sys, + .input = switch (sys_opts.source) { + .src_rosc => input: { + output_freq = sys_opts.freq orelse rosc_freq; + assert(output_freq.? <= rosc_freq); + break :input .{ + .source = .rosc, + .freq = rosc_freq, + }; + }, + .src_xosc => input: { + xosc_configured = true; + output_freq = sys_opts.freq orelse xosc_freq; + assert(output_freq.? <= xosc_freq); + break :input .{ + .source = .xosc, + .freq = xosc_freq, + }; + }, + .pll_sys => input: { + xosc_configured = true; + output_freq = sys_opts.freq orelse 125_000_000; + assert(output_freq.? <= 125_000_000); + + // TODO: proper values for 125MHz + pll_sys = .{ + .refdiv = 2, + .vco_freq = 1_440_000_000, + .postdiv1 = 6, + .postdiv2 = 5, + }; + + break :input .{ + .source = .pll_sys, + // TODO: not really sure what frequency to + // drive pll at yet, but this is an okay start + .freq = 125_000_000, + }; + }, + + else => unreachable, // not an available input + }, + .output_freq = output_freq.?, + }; + } else null, + + // to keep things simple for now, we'll make it so that the usb + // generator can only be hooked up to the usb PLL, and only have + // one configuration for the usb PLL + .usb = if (opts.usb) |usb_opts| usb_config: { + assert(pll_usb == null); + assert(usb_opts.source == .pll_usb); + + xosc_configured = true; + pll_usb = .{ + .refdiv = 1, + .vco_freq = 1_440_000_000, + .postdiv1 = 6, + .postdiv2 = 5, + }; + + break :usb_config .{ + .generator = .usb, + .input = .{ + .source = .pll_usb, + .freq = 48_000_000, + }, + .output_freq = 48_000_000, + }; + } else null, + + // I THINK that if either pll is configured here, then that means + // that the ref clock generator MUST use xosc to feed the PLLs? + .ref = if (opts.ref) |_| + unreachable // don't explicitly configure for now + else if (pll_sys != null or pll_usb != null) ref_config: { + xosc_configured = true; + break :ref_config .{ + .generator = .ref, + .input = .{ + .source = .src_xosc, + .freq = xosc_freq, + }, + .output_freq = xosc_freq, + }; + } else null, + + // for the rest of the generators we'll make it so that they can + // either use the ROSC, XOSC, or sys PLL, with whatever dividing + // they need + + .adc = if (opts.adc) |_| + unreachable // TODO + else + null, + + .rtc = if (opts.rtc) |_| + unreachable // TODO + else + null, + + .peri = if (opts.peri) |peri_opts| peri_config: { + if (peri_opts.source == .src_xosc) + xosc_configured = true; + + // TODO + break :peri_config .{ + .generator = .peri, + .input = .{ + .source = peri_opts.source, + .freq = xosc_freq, + }, + .output_freq = xosc_freq, + }; + } else null, + + .xosc_configured = xosc_configured, + .pll_sys = pll_sys, + .pll_usb = pll_usb, + }; + } + + /// this is explicitly comptime to encourage the user to have separate + /// clock configuration declarations instead of mutating them at runtime + pub fn apply(comptime config: GlobalConfiguration) !void { + + // disable resus if it has been turned on elsewhere + regs.CLOCKS.CLK_SYS_RESUS_CTRL.raw = 0; + + if (config.xosc_configured) { + regs.WATCHDOG.TICK.modify(.{ + .CYCLES = xosc_freq / 1_000_000, + .ENABLE = 1, + }); + xosc.init(); + } + + // switch sys and ref cleanly away from aux sources if they're + // configured to use/be used from PLLs + if (config.sys) |sys| switch (sys.input.source) { + .pll_usb, .pll_sys => { + regs.CLOCKS.CLK_SYS_CTRL.modify(.{ .SRC = 0 }); + while (regs.CLOCKS.CLK_SYS_SELECTED.* != 1) {} + }, + else => {}, + }; + + if (config.ref) |ref| switch (ref.input.source) { + .pll_usb, .pll_sys => { + regs.CLOCKS.CLK_REF_CTRL.modify(.{ .SRC = 0 }); + while (regs.CLOCKS.CLK_REF_SELECTED.* != 1) {} + }, + else => {}, + }; + + // initialize PLLs + if (config.pll_sys) |pll_sys_config| pll.sys.apply(pll_sys_config); + if (config.pll_usb) |pll_usb_config| pll.usb.apply(pll_usb_config); + + // initialize clock generators + if (config.ref) |ref| try ref.apply(); + if (config.usb) |usb| try usb.apply(); + if (config.adc) |adc| try adc.apply(); + if (config.rtc) |rtc| try rtc.apply(); + if (config.peri) |peri| try peri.apply(); + } + + /// returns frequency of a clock or pll, if unconfigured it returns null + pub fn getFrequency(config: GlobalConfiguration) ?u32 { + _ = config; + return null; + } +}; + +pub const Configuration = struct { + generator: Generator, + input: struct { + source: Source, + freq: u32, + }, + output_freq: u32, + + pub fn apply(config: Configuration) !void { + const generator = config.generator; + const input = config.input; + const output_freq = config.output_freq; + + // source frequency has to be faster because dividing will always reduce. + assert(input.freq >= output_freq); + if (output_freq < input.freq) + return error.InvalidArgs; + + const div = @intCast(u32, (@intCast(u64, input.freq) << 8) / 8); + + // check divisor + if (div > generator.getDiv()) + generator.setDiv(div); + + if (generator.hasGlitchlessMux() and input.source == .src_aux) { + // TODO: clear bits + while (!generator.selected()) { + // TODO: is leaving this empty good enough? pico sdk has `tight_loop_contents()` + } + } else { + // uh stuff + } + + // set aux mux first and then glitchless mex if this clock has one + if (generator.hasGlitchlessMux()) { + // write to clock ctrl + while (!generator.selected()) {} + } + + generator.enable(); + generator.setDiv(div); + // should we store global state on configured clocks? + } +}; + +//pub fn countFrequencyKhz(source: Source) u32 {} + diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig new file mode 100644 index 000000000..ab0f66696 --- /dev/null +++ b/src/hal/gpio.zig @@ -0,0 +1,153 @@ +//! ### Function Select Table +//! +//! GPIO | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 +//! -------|----------|-----------|----------|--------|-----|------|------|---------------|---- +//! 0 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB OVCUR DET +//! 1 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS DET +//! 2 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB VBUS EN +//! 3 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB OVCUR DET +//! 4 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | | USB VBUS DET +//! 5 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | | USB VBUS EN +//! 6 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | | USB OVCUR DET +//! 7 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | | USB VBUS DET +//! 8 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | | USB VBUS EN +//! 9 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | | USB OVCUR DET +//! 10 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS DET +//! 11 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB VBUS EN +//! 12 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB OVCUR DET +//! 13 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS DET +//! 14 | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | | USB VBUS EN +//! 15 | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | | USB OVCUR DET +//! 16 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB VBUS DET +//! 17 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS EN +//! 18 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB OVCUR DET +//! 19 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB VBUS DET +//! 20 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | CLOCK GPIN0 | USB VBUS EN +//! 21 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | CLOCK GPOUT0 | USB OVCUR DET +//! 22 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | CLOCK GPIN1 | USB VBUS DET +//! 23 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | CLOCK GPOUT1 | USB VBUS EN +//! 24 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | CLOCK GPOUT2 | USB OVCUR DET +//! 25 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | CLOCK GPOUT3 | USB VBUS DET +//! 26 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS EN +//! 27 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB OVCUR DET +//! 28 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB VBUS DET +//! 29 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS EN + +const std = @import("std"); +const microzig = @import("microzig"); +const regs = microzig.chip.registers; +const assert = std.debug.assert; + +pub const Function = enum(u5) { + xip, + spi, + uart, + i2c, + pwm, + sio, + pio0, + pio1, + gpck, + usb, + @"null" = 0x1f, +}; + +pub const Direction = enum(u1) { + in, + out, +}; + +pub const IrqLevel = enum(u2) { + low, + high, + fall, + rise, +}; + +pub const IrqCallback = fn (gpio: u32, events: u32) callconv(.C) void; + +pub const Override = enum { + normal, + invert, + low, + high, +}; + +pub const SlewRate = enum { + slow, + fast, +}; + +pub const DriveStrength = enum { + ma_2, + ma_4, + ma_8, + ma_12, +}; + +pub const Enabled = enum { + disabled, + enabled, +}; + +//const gpio_num = gpio_num: { +// // calculate max gpios using comptime parsing +//}; + +/// Initialize a GPIO, set func to SIO +pub inline fn init(comptime gpio: u32) void { + regs.SIO.GPIO_OE_CLR.raw = 1 << gpio; + regs.SIO.GPIO_OUT_CLR.raw = 1 << gpio; + setFunction(gpio, .sio); +} + +/// Reset GPIO back to null function (disables it) +pub inline fn deinit(comptime gpio: u32) void { + setFunction(gpio, .@"null"); +} + +pub inline fn setDir(comptime gpio: u32, direction: Direction) void { + switch (direction) { + .in => regs.SIO.GPIO_OE_CLR.raw |= (1 << gpio), + .out => regs.SIO.GPIO_OE_SET.raw &= (1 << gpio), + } +} + +/// Drive a single GPIO high/low +pub inline fn put(comptime gpio: u32, value: u1) void { + switch (value) { + 0 => regs.SIO.GPIO_OUT.raw &= ~@as(u32, 1 << gpio), + 1 => regs.SIO.GPIO_OUT.raw |= (1 << gpio), + } +} + +pub inline fn setFunction(comptime gpio: u32, function: Function) void { + const reg_name = comptime std.fmt.comptimePrint("GPIO{}_CTRL", .{gpio}); + @field(regs.IO_BANK0, reg_name).write(.{ + .FUNCSEL = @enumToInt(function), + .OUTOVER = 0, + .INOVER = 0, + .IRQOVER = 0, + .OEOVER = 0, + }); +} + +// setting both uplls enables a "bus keep" function, a weak pull to whatever +// is current high/low state of GPIO +//pub fn setPulls(gpio: u32, up: bool, down: bool) void {} +// +//pub fn pullUp(gpio: u32) void {} +// +//pub fn pullDown(gpio: u32) void {} +//pub fn disablePulls(gpio: u32) void {} +//pub fn setIrqOver(gpio: u32, value: u32) void {} +//pub fn setOutOver(gpio: u32, value: u32) void {} +//pub fn setInOver(gpio: u32, value: u32) void {} +//pub fn setOeOver(gpio: u32, value: u32) void {} +//pub fn setInputEnabled(gpio: u32, enabled: Enabled) void {} +//pub fn setinputHysteresisEnabled(gpio: u32, enabled: Enabled) void {} +//pub fn setSlewRate(gpio: u32, slew_rate: SlewRate) void {} +//pub fn setDriveStrength(gpio: u32, drive: DriveStrength) void {} +//pub fn setIrqEnabled(gpio: u32, events: IrqEvents) void {} +//pub fn acknowledgeIrq(gpio: u32, events: IrqEvents) void {} + diff --git a/src/hal/pll.zig b/src/hal/pll.zig new file mode 100644 index 000000000..16fb3086d --- /dev/null +++ b/src/hal/pll.zig @@ -0,0 +1,97 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const assert = std.debug.assert; + +const regs = microzig.chip.registers; +const xosc_freq = microzig.board.xosc_freq; + +pub const Configuration = struct { + refdiv: u6, + vco_freq: u32, + postdiv1: u3, + postdiv2: u3, +}; + +pub const sys = @intToPtr(*volatile PLL, regs.PLL_SYS.base_address); +pub const usb = @intToPtr(*volatile PLL, regs.PLL_USB.base_address); + +pub const PLL = packed struct { + cs: @TypeOf(regs.PLL_SYS.CS), + pwr: @TypeOf(regs.PLL_SYS.PWR), + fbdiv_int: @TypeOf(regs.PLL_SYS.FBDIV_INT), + prim: @TypeOf(regs.PLL_SYS.PRIM), + + comptime { + // bunch of comptime checks in here to validate the layout + assert(0 == @bitOffsetOf(PLL, "cs")); + assert(32 == @bitOffsetOf(PLL, "pwr")); + assert(64 == @bitOffsetOf(PLL, "fbdiv_int")); + assert(96 == @bitOffsetOf(PLL, "prim")); + } + + pub fn isLocked(pll: *const volatile PLL) bool { + return pll.cs.read().LOCK == 1; + } + + pub fn reset(pll: *const volatile PLL) void { + switch (pll) { + sys => { + regs.RESETS.RESET.modify(.{ .pll_sys = 1 }); + regs.RESETS.RESET.modify(.{ .pll_sys = 0 }); + while (regs.RESETS.RESET_DONE.read().pll_sys == 1) {} + }, + usb => { + regs.RESETS.RESET.modify(.{ .pll_usb = 1 }); + regs.RESETS.RESET.modify(.{ .pll_usb = 0 }); + while (regs.RESETS.RESET_DONE.read().pll_usb == 1) {} + }, + else => unreachable, + } + } + + pub fn apply(pll: *volatile PLL, comptime config: Configuration) void { + const ref_freq = xosc_freq / @as(u32, config.refdiv); + const fbdiv = @intCast(u12, config.vco_freq / ref_freq); + + assert(fbdiv >= 16 and fbdiv <= 320); + assert(config.postdiv1 >= 1 and config.postdiv1 <= 7); + assert(config.postdiv2 >= 1 and config.postdiv2 <= 7); + assert(config.postdiv2 <= config.postdiv1); + assert(ref_freq <= config.vco_freq / 16); + + // 1. program reference clock divider + // 2. program feedback divider + // 3. turn on the main power and vco + // 4. wait for vco to lock + // 5. set up post dividers and turn them on + + // do not bother a PLL which is already configured + if (pll.isLocked() and + config.refdiv == pll.cs.read().REFDIV and + fbdiv == pll.fbdiv_int.read() and + config.postdiv1 == pll.prim.read().POSTDIV1 and + config.postdiv2 == pll.prim.read().POSTDIV2) + { + return; + } + + pll.reset(); + + // load vco related dividers + pll.cs.modify(.{ .REFDIV = config.refdiv }); + pll.fbdiv_int.modify(fbdiv); + + // turn on PLL + pll.pwr.modify(.{ .PD = 0, .VCOPD = 0 }); + + // wait for PLL to lock + while (!pll.isLocked()) {} + + pll.prim.modify(.{ + .POSTDIV1 = config.postdiv1, + .POSTDIV2 = config.postdiv2, + }); + + pll.pwr.modify(.{ .POSTDIVPD = 0 }); + } +}; diff --git a/src/raspberry_pi_pico.zig b/src/raspberry_pi_pico.zig new file mode 100644 index 000000000..ca1a9014d --- /dev/null +++ b/src/raspberry_pi_pico.zig @@ -0,0 +1,38 @@ +pub const xosc_freq = 12_000_000; + +// TODO: improve interface so that user can use a custom implementation and +// automatically checksum it. +pub export const _BOOT2: [256]u8 linksection(".boot2") = [_]u8{ + 0x00, 0xb5, 0x32, 0x4b, 0x21, 0x20, 0x58, 0x60, + 0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60, + 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2e, 0x4b, + 0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61, + 0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2b, 0x49, + 0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20, + 0x00, 0xf0, 0x44, 0xf8, 0x02, 0x22, 0x90, 0x42, + 0x14, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0, + 0x34, 0xf8, 0x19, 0x6e, 0x01, 0x21, 0x19, 0x66, + 0x00, 0x20, 0x18, 0x66, 0x1a, 0x66, 0x00, 0xf0, + 0x2c, 0xf8, 0x19, 0x6e, 0x19, 0x6e, 0x19, 0x6e, + 0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21, + 0x08, 0x42, 0xf9, 0xd1, 0x00, 0x21, 0x99, 0x60, + 0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60, + 0x1a, 0x49, 0x1b, 0x48, 0x01, 0x60, 0x01, 0x21, + 0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0xa0, 0x21, + 0x19, 0x66, 0x00, 0xf0, 0x12, 0xf8, 0x00, 0x21, + 0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60, + 0x01, 0x21, 0x99, 0x60, 0x01, 0xbc, 0x00, 0x28, + 0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49, + 0x08, 0x60, 0x03, 0xc8, 0x80, 0xf3, 0x08, 0x88, + 0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20, + 0x01, 0x42, 0xfb, 0xd0, 0x01, 0x20, 0x01, 0x42, + 0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66, + 0x18, 0x66, 0xff, 0xf7, 0xf2, 0xff, 0x18, 0x6e, + 0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40, + 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00, + 0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00, + 0xf4, 0x00, 0x00, 0x18, 0x22, 0x20, 0x00, 0xa0, + 0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x74, 0xb2, 0x4e, 0x7a, +}; diff --git a/src/rp2040.zig b/src/rp2040.zig new file mode 100644 index 000000000..e96b90134 --- /dev/null +++ b/src/rp2040.zig @@ -0,0 +1,29422 @@ +// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz +// commit: 09c331e02d8037bf2e5133eaa40b1d762637b441 +// +// vendor: Raspberry Pi +// device: RP2040 +// cpu: CM0PLUS + +pub const VectorTable = extern struct { + initial_stack_pointer: u32, + Reset: InterruptVector = unhandled, + NMI: InterruptVector = unhandled, + HardFault: InterruptVector = unhandled, + reserved0: [7]u32 = undefined, + SVCall: InterruptVector = unhandled, + reserved1: [2]u32 = undefined, + PendSV: InterruptVector = unhandled, + SysTick: InterruptVector = unhandled, + TIMER_IRQ_0: InterruptVector = unhandled, + TIMER_IRQ_1: InterruptVector = unhandled, + TIMER_IRQ_2: InterruptVector = unhandled, + TIMER_IRQ_3: InterruptVector = unhandled, + PWM_IRQ_WRAP: InterruptVector = unhandled, + USBCTRL_IRQ: InterruptVector = unhandled, + XIP_IRQ: InterruptVector = unhandled, + PIO0_IRQ_0: InterruptVector = unhandled, + PIO0_IRQ_1: InterruptVector = unhandled, + PIO1_IRQ_0: InterruptVector = unhandled, + PIO1_IRQ_1: InterruptVector = unhandled, + DMA_IRQ_0: InterruptVector = unhandled, + DMA_IRQ_1: InterruptVector = unhandled, + IO_IRQ_BANK0: InterruptVector = unhandled, + IO_IRQ_QSPI: InterruptVector = unhandled, + SIO_IRQ_PROC0: InterruptVector = unhandled, + SIO_IRQ_PROC1: InterruptVector = unhandled, + CLOCKS_IRQ: InterruptVector = unhandled, + SPI0_IRQ: InterruptVector = unhandled, + SPI1_IRQ: InterruptVector = unhandled, + UART0_IRQ: InterruptVector = unhandled, + UART1_IRQ: InterruptVector = unhandled, + ADC_IRQ_FIFO: InterruptVector = unhandled, + I2C0_IRQ: InterruptVector = unhandled, + I2C1_IRQ: InterruptVector = unhandled, + RTC_IRQ: InterruptVector = unhandled, +}; + +pub const registers = struct { + + /// System Control Space + pub const SCS = struct { + pub const base_address = 0xe000e000; + + /// System Tick Timer + pub const SysTick = struct { + + /// address: 0xe000e010 + /// SysTick Control and Status Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + ENABLE: u1, + TICKINT: u1, + CLKSOURCE: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + COUNTFLAG: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + }), base_address + 0x10); + + /// address: 0xe000e014 + /// SysTick Reload Value Register + pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct { + RELOAD: u24, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x14); + + /// address: 0xe000e018 + /// SysTick Current Value Register + pub const VAL = @intToPtr(*volatile Mmio(32, packed struct { + CURRENT: u24, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x18); + + /// address: 0xe000e01c + /// SysTick Calibration Register + pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct { + TENMS: u24, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + SKEW: u1, + NOREF: u1, + }), base_address + 0x1c); + }; + + /// Nested Vectored Interrupt Controller + pub const NVIC = struct { + + /// address: 0xe000e100 + /// Interrupt Set Enable Register + pub const ISER = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0xe000e180 + /// Interrupt Clear Enable Register + pub const ICER = @intToPtr(*volatile u32, base_address + 0x180); + + /// address: 0xe000e200 + /// Interrupt Set Pending Register + pub const ISPR = @intToPtr(*volatile u32, base_address + 0x200); + + /// address: 0xe000e280 + /// Interrupt Clear Pending Register + pub const ICPR = @intToPtr(*volatile u32, base_address + 0x280); + + /// address: 0xe000e400 + /// Interrupt Priority Register + pub const IP = @intToPtr(*volatile u32, base_address + 0x400); + }; + + /// System Control Block + pub const SCB = struct { + + /// address: 0xe000ed00 + pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { + REVISION: u4, + PARTNO: u12, + ARCHITECTURE: u4, + VARIANT: u4, + IMPLEMENTER: u8, + }), base_address + 0xd00); + + /// address: 0xe000ed04 + /// Interrupt Control and State Register + pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { + VECTACTIVE: u9, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + VECTPENDING: u9, + reserved3: u1 = 0, + ISRPENDING: u1, + ISRPREEMPT: u1, + reserved4: u1 = 0, + PENDSTCLR: u1, + PENDSTSET: u1, + PENDSVCLR: u1, + PENDSVSET: u1, + reserved5: u1 = 0, + reserved6: u1 = 0, + NMIPENDSET: u1, + }), base_address + 0xd04); + + /// address: 0xe000ed0c + /// Application Interrupt and Reset Control Register + pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + VECTCLRACTIVE: u1, + SYSRESETREQ: u1, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + ENDIANESS: u1, + VECTKEY: u16, + }), base_address + 0xd0c); + + /// address: 0xe000ed10 + /// System Control Register + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + SLEEPONEXIT: u1, + SLEEPDEEP: u1, + reserved1: u1 = 0, + SEVONPEND: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + }), base_address + 0xd10); + + /// address: 0xe000ed14 + /// Configuration Control Register + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + UNALIGN_TRP: u1, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + STKALIGN: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + }), base_address + 0xd14); + + /// address: 0xe000ed1c + /// System Handlers Priority Registers. [0] is RESERVED + pub const SHP = @intToPtr(*volatile u32, base_address + 0xd1c); + + /// address: 0xe000ed24 + /// System Handler Control and State Register + pub const SHCSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + SVCALLPENDED: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0xd24); + + /// address: 0xe000ed08 + /// Vector Table Offset Register + pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + TBLOFF: u24, + }), base_address + 0xd08); + }; + + /// Memory Protection Unit + pub const MPU = struct { + + /// address: 0xe000ed90 + /// MPU Type Register + pub const TYPE = @intToPtr(*volatile Mmio(32, packed struct { + SEPARATE: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + DREGION: u8, + IREGION: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0xd90); + + /// address: 0xe000ed94 + /// MPU Control Register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + ENABLE: u1, + HFNMIENA: u1, + PRIVDEFENA: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + }), base_address + 0xd94); + + /// address: 0xe000ed98 + /// MPU Region RNRber Register + pub const RNR = @intToPtr(*volatile Mmio(32, packed struct { + REGION: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xd98); + + /// address: 0xe000ed9c + /// MPU Region Base Address Register + pub const RBAR = @intToPtr(*volatile Mmio(32, packed struct { + REGION: u4, + VALID: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + ADDR: u24, + }), base_address + 0xd9c); + + /// address: 0xe000eda0 + /// MPU Region Attribute and Size Register + pub const RASR = @intToPtr(*volatile Mmio(32, packed struct { + ENABLE: u1, + SIZE: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + SRD: u8, + B: u1, + C: u1, + S: u1, + TEX: u3, + reserved2: u1 = 0, + reserved3: u1 = 0, + AP: u3, + reserved4: u1 = 0, + XN: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + }), base_address + 0xda0); + }; + }; + + /// QSPI flash execute-in-place block + pub const XIP_CTRL = struct { + pub const base_address = 0x14000000; + pub const version = "1"; + + /// address: 0x14000000 + /// Cache control + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// When 1, enable the cache. When the cache is disabled, all XIP accesses\n + /// will go straight to the flash, without querying the cache. When enabled,\n + /// cacheable XIP accesses will query the cache, and the flash will\n + /// not be accessed if the tag matches and the valid bit is set.\n\n + /// If the cache is enabled, cache-as-SRAM accesses have no effect on the\n + /// cache data RAM, and will produce a bus error response. + EN: u1, + /// When 1, writes to any alias other than 0x0 (caching, allocating)\n + /// will produce a bus fault. When 0, these writes are silently ignored.\n + /// In either case, writes to the 0x0 alias will deallocate on tag match,\n + /// as usual. + ERR_BADWRITE: u1, + reserved0: u1 = 0, + /// When 1, the cache memories are powered down. They retain state,\n + /// but can not be accessed. This reduces static power dissipation.\n + /// Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n + /// be enabled when powered down.\n + /// Cache-as-SRAM accesses will produce a bus error response when\n + /// the cache is powered down. + POWER_DOWN: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x0); + + /// address: 0x14000004 + /// Cache Flush control + pub const FLUSH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4); + + /// address: 0x14000008 + /// Cache Status + pub const STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Reads as 0 while a cache flush is in progress, and 1 otherwise.\n + /// The cache is flushed whenever the XIP block is reset, and also\n + /// when requested via the FLUSH register. + FLUSH_READY: u1, + /// When 1, indicates the XIP streaming FIFO is completely empty. + FIFO_EMPTY: u1, + /// When 1, indicates the XIP streaming FIFO is completely full.\n + /// The streaming FIFO is 2 entries deep, so the full and empty\n + /// flag allow its level to be ascertained. + FIFO_FULL: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + }), base_address + 0x8); + + /// address: 0x1400000c + /// Cache Hit counter\n + /// A 32 bit saturating counter that increments upon each cache hit,\n + /// i.e. when an XIP access is serviced directly from cached data.\n + /// Write any value to clear. + pub const CTR_HIT = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x14000010 + /// Cache Access counter\n + /// A 32 bit saturating counter that increments upon each XIP access,\n + /// whether the cache is hit or not. This includes noncacheable accesses.\n + /// Write any value to clear. + pub const CTR_ACC = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x14000014 + /// FIFO stream address + pub const STREAM_ADDR = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x14); + + /// address: 0x14000018 + /// FIFO stream control + pub const STREAM_CTR = @intToPtr(*volatile MmioInt(32, u22), base_address + 0x18); + + /// address: 0x1400001c + /// FIFO stream data\n + /// Streamed data is buffered here, for retrieval by the system DMA.\n + /// This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n + /// the DMA to bus stalls caused by other XIP traffic. + pub const STREAM_FIFO = @intToPtr(*volatile u32, base_address + 0x1c); + }; + + /// DW_apb_ssi has the following features:\n + /// * APB interface – Allows for easy integration into a DesignWare Synthesizable + /// Components for AMBA 2 implementation.\n + /// * APB3 and APB4 protocol support.\n + /// * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 + /// bits.\n + /// * Serial-master or serial-slave operation – Enables serial communication with + /// serial-master or serial-slave peripheral devices.\n + /// * Programmable Dual/Quad/Octal SPI support in Master Mode.\n + /// * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the + /// DW_apb_ssi master to perform operations with the device in DDR and RDS modes + /// when working in Dual/Quad/Octal mode of operation.\n + /// * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in + /// the device. This feature is applicable only in enhanced SPI modes.\n + /// * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a + /// memory mapped I/O and fetches the data from the device based on the APB read + /// request. This feature is applicable only in enhanced SPI modes.\n + /// * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA + /// controller over the bus using a handshaking interface for transfer requests.\n + /// * Independent masking of interrupts – Master collision, transmit FIFO + /// overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and + /// receive FIFO overflow interrupts can all be masked independently.\n + /// * Multi-master contention detection – Informs the processor of multiple + /// serial-master accesses on the serial bus.\n + /// * Bypass of meta-stability flip-flops for synchronous clocks – When the APB + /// clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, + /// meta-stable flip-flops are not used when transferring control signals across + /// these clock domains.\n + /// * Programmable delay on the sample time of the received serial data bit (rxd); + /// enables programmable control of routing delays resulting in higher serial + /// data-bit rates.\n + /// * Programmable features:\n + /// - Serial interface operation – Choice of Motorola SPI, Texas Instruments + /// Synchronous Serial Protocol or National Semiconductor Microwire.\n + /// - Clock bit-rate – Dynamic control of the serial bit rate of the data + /// transfer; used in only serial-master mode of operation.\n + /// - Data Item size (4 to 32 bits) – Item size of each data transfer under the + /// control of the programmer.\n + /// * Configured features:\n + /// - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n + /// - 1 slave select output.\n + /// - Hardware slave-select – Dedicated hardware slave-select line.\n + /// - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to + /// the interrupt controller.\n + /// - Interrupt polarity – active high interrupt lines.\n + /// - Serial clock polarity – low serial-clock polarity directly after reset.\n + /// - Serial clock phase – capture on first edge of serial-clock directly after + /// reset. + pub const XIP_SSI = struct { + pub const base_address = 0x18000000; + pub const version = "1"; + + /// address: 0x18000000 + /// Control register 0 + pub const CTRLR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data frame size + DFS: u4, + /// Frame format + FRF: u2, + /// Serial clock phase + SCPH: u1, + /// Serial clock polarity + SCPOL: u1, + /// Transfer mode + TMOD: u2, + /// Slave output enable + SLV_OE: u1, + /// Shift register loop (test mode) + SRL: u1, + /// Control frame size\n + /// Value of n -> n+1 clocks per frame. + CFS: u4, + /// Data frame size in 32b transfer mode\n + /// Value of n -> n+1 clocks per frame. + DFS_32: u5, + /// SPI frame format + SPI_FRF: u2, + reserved0: u1 = 0, + /// Slave select toggle enable + SSTE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + }), base_address + 0x0); + + /// address: 0x18000004 + /// Master Control register 1 + pub const CTRLR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Number of data frames + NDF: u16, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x4); + + /// address: 0x18000008 + /// SSI Enable + pub const SSIENR = @intToPtr(*volatile Mmio(32, packed struct { + /// SSI enable + SSI_EN: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x8); + + /// address: 0x1800000c + /// Microwire Control + pub const MWCR = @intToPtr(*volatile Mmio(32, packed struct { + /// Microwire transfer mode + MWMOD: u1, + /// Microwire control + MDD: u1, + /// Microwire handshaking + MHS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + }), base_address + 0xc); + + /// address: 0x18000010 + /// Slave enable + pub const SER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x10); + + /// address: 0x18000014 + /// Baud rate + pub const BAUDR = @intToPtr(*volatile Mmio(32, packed struct { + /// SSI clock divider + SCKDV: u16, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x14); + + /// address: 0x18000018 + /// TX FIFO threshold level + pub const TXFTLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO threshold + TFT: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x18); + + /// address: 0x1800001c + /// RX FIFO threshold level + pub const RXFTLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive FIFO threshold + RFT: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x1c); + + /// address: 0x18000020 + /// TX FIFO level + pub const TXFLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO level + TFTFL: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x20); + + /// address: 0x18000024 + /// RX FIFO level + pub const RXFLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive FIFO level + RXTFL: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x24); + + /// address: 0x18000028 + /// Status register + pub const SR = @intToPtr(*volatile Mmio(32, packed struct { + /// SSI busy flag + BUSY: u1, + /// Transmit FIFO not full + TFNF: u1, + /// Transmit FIFO empty + TFE: u1, + /// Receive FIFO not empty + RFNE: u1, + /// Receive FIFO full + RFF: u1, + /// Transmission error + TXE: u1, + /// Data collision error + DCOL: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + }), base_address + 0x28); + + /// address: 0x1800002c + /// Interrupt mask + pub const IMR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO empty interrupt mask + TXEIM: u1, + /// Transmit FIFO overflow interrupt mask + TXOIM: u1, + /// Receive FIFO underflow interrupt mask + RXUIM: u1, + /// Receive FIFO overflow interrupt mask + RXOIM: u1, + /// Receive FIFO full interrupt mask + RXFIM: u1, + /// Multi-master contention interrupt mask + MSTIM: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + }), base_address + 0x2c); + + /// address: 0x18000030 + /// Interrupt status + pub const ISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO empty interrupt status + TXEIS: u1, + /// Transmit FIFO overflow interrupt status + TXOIS: u1, + /// Receive FIFO underflow interrupt status + RXUIS: u1, + /// Receive FIFO overflow interrupt status + RXOIS: u1, + /// Receive FIFO full interrupt status + RXFIS: u1, + /// Multi-master contention interrupt status + MSTIS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + }), base_address + 0x30); + + /// address: 0x18000034 + /// Raw interrupt status + pub const RISR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO empty raw interrupt status + TXEIR: u1, + /// Transmit FIFO overflow raw interrupt status + TXOIR: u1, + /// Receive FIFO underflow raw interrupt status + RXUIR: u1, + /// Receive FIFO overflow raw interrupt status + RXOIR: u1, + /// Receive FIFO full raw interrupt status + RXFIR: u1, + /// Multi-master contention raw interrupt status + MSTIR: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + }), base_address + 0x34); + + /// address: 0x18000038 + /// TX FIFO overflow interrupt clear + pub const TXOICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x38); + + /// address: 0x1800003c + /// RX FIFO overflow interrupt clear + pub const RXOICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x3c); + + /// address: 0x18000040 + /// RX FIFO underflow interrupt clear + pub const RXUICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x40); + + /// address: 0x18000044 + /// Multi-master interrupt clear + pub const MSTICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x44); + + /// address: 0x18000048 + /// Interrupt clear + pub const ICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x48); + + /// address: 0x1800004c + /// DMA control + pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive DMA enable + RDMAE: u1, + /// Transmit DMA enable + TDMAE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x4c); + + /// address: 0x18000050 + /// DMA TX data level + pub const DMATDLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit data watermark level + DMATDL: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x50); + + /// address: 0x18000054 + /// DMA RX data level + pub const DMARDLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive data watermark level (DMARDLR+1) + DMARDL: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x54); + + /// address: 0x18000058 + /// Identification register + pub const IDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Peripheral dentification code + IDCODE: u32, + }), base_address + 0x58); + + /// address: 0x1800005c + /// Version ID + pub const SSI_VERSION_ID = @intToPtr(*volatile Mmio(32, packed struct { + /// SNPS component version (format X.YY) + SSI_COMP_VERSION: u32, + }), base_address + 0x5c); + + /// address: 0x18000060 + /// Data Register 0 (of 36) + pub const DR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// First data register of 36 + DR: u32, + }), base_address + 0x60); + + /// address: 0x180000f0 + /// RX sample delay + pub const RX_SAMPLE_DLY = @intToPtr(*volatile Mmio(32, packed struct { + /// RXD sample delay (in SCLK cycles) + RSD: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xf0); + + /// address: 0x180000f4 + /// SPI control + pub const SPI_CTRLR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Address and instruction transfer format + TRANS_TYPE: u2, + /// Address length (0b-60b in 4b increments) + ADDR_L: u4, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// Instruction length (0/4/8/16b) + INST_L: u2, + reserved2: u1 = 0, + /// Wait cycles between control frame transmit and data reception (in SCLK cycles) + WAIT_CYCLES: u5, + /// SPI DDR transfer enable + SPI_DDR_EN: u1, + /// Instruction DDR transfer enable + INST_DDR_EN: u1, + /// Read data strobe enable + SPI_RXDS_EN: u1, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L + /// = 0-bit) + XIP_CMD: u8, + }), base_address + 0xf4); + + /// address: 0x180000f8 + /// TX drive edge + pub const TXD_DRIVE_EDGE = @intToPtr(*volatile Mmio(32, packed struct { + /// TXD drive edge + TDE: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xf8); + }; + pub const SYSINFO = struct { + pub const base_address = 0x40000000; + pub const version = "1"; + + /// address: 0x40000000 + /// JEDEC JEP-106 compliant chip identifier. + pub const CHIP_ID = @intToPtr(*volatile Mmio(32, packed struct { + MANUFACTURER: u12, + PART: u16, + REVISION: u4, + }), base_address + 0x0); + + /// address: 0x40000004 + /// Platform register. Allows software to know what environment it is running in. + pub const PLATFORM = @intToPtr(*volatile Mmio(32, packed struct { + FPGA: u1, + ASIC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40000040 + /// Git hash of the chip source. Used to identify chip version. + pub const GITREF_RP2040 = @intToPtr(*volatile u32, base_address + 0x40); + }; + + /// Register block for various chip control signals + pub const SYSCFG = struct { + pub const base_address = 0x40004000; + pub const version = "1"; + + /// address: 0x40004000 + /// Processor core 0 NMI source mask\n + /// Set a bit high to enable NMI from that IRQ + pub const PROC0_NMI_MASK = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40004004 + /// Processor core 1 NMI source mask\n + /// Set a bit high to enable NMI from that IRQ + pub const PROC1_NMI_MASK = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40004008 + /// Configuration for processors + pub const PROC_CONFIG = @intToPtr(*volatile Mmio(32, packed struct { + /// Indication that proc0 has halted + PROC0_HALTED: u1, + /// Indication that proc1 has halted + PROC1_HALTED: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + /// Configure proc0 DAP instance ID.\n + /// Recommend that this is NOT changed until you require debug access in multi-chip + /// environment\n + /// WARNING: do not set to 15 as this is reserved for RescueDP + PROC0_DAP_INSTID: u4, + /// Configure proc1 DAP instance ID.\n + /// Recommend that this is NOT changed until you require debug access in multi-chip + /// environment\n + /// WARNING: do not set to 15 as this is reserved for RescueDP + PROC1_DAP_INSTID: u4, + }), base_address + 0x8); + + /// address: 0x4000400c + /// For each bit, if 1, bypass the input synchronizer between that GPIO\n + /// and the GPIO input register in the SIO. The input synchronizers should\n + /// generally be unbypassed, to avoid injecting metastabilities into processors.\n + /// If you're feeling brave, you can bypass to save two cycles of input\n + /// latency. This register applies to GPIO 0...29. + pub const PROC_IN_SYNC_BYPASS = @intToPtr(*volatile MmioInt(32, u30), base_address + 0xc); + + /// address: 0x40004010 + /// For each bit, if 1, bypass the input synchronizer between that GPIO\n + /// and the GPIO input register in the SIO. The input synchronizers should\n + /// generally be unbypassed, to avoid injecting metastabilities into processors.\n + /// If you're feeling brave, you can bypass to save two cycles of input\n + /// latency. This register applies to GPIO 30...35 (the QSPI IOs). + pub const PROC_IN_SYNC_BYPASS_HI = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x10); + + /// address: 0x40004014 + /// Directly control the SWD debug port of either processor + pub const DBGFORCE = @intToPtr(*volatile Mmio(32, packed struct { + /// Observe the value of processor 0 SWDIO output. + PROC0_SWDO: u1, + /// Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set + PROC0_SWDI: u1, + /// Directly drive processor 0 SWCLK, if PROC0_ATTACH is set + PROC0_SWCLK: u1, + /// Attach processor 0 debug port to syscfg controls, and disconnect it from + /// external SWD pads. + PROC0_ATTACH: u1, + /// Observe the value of processor 1 SWDIO output. + PROC1_SWDO: u1, + /// Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set + PROC1_SWDI: u1, + /// Directly drive processor 1 SWCLK, if PROC1_ATTACH is set + PROC1_SWCLK: u1, + /// Attach processor 1 debug port to syscfg controls, and disconnect it from + /// external SWD pads. + PROC1_ATTACH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x14); + + /// address: 0x40004018 + /// Control power downs to memories. Set high to power down memories.\n + /// Use with extreme caution + pub const MEMPOWERDOWN = @intToPtr(*volatile Mmio(32, packed struct { + SRAM0: u1, + SRAM1: u1, + SRAM2: u1, + SRAM3: u1, + SRAM4: u1, + SRAM5: u1, + USB: u1, + ROM: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x18); + }; + pub const CLOCKS = struct { + pub const base_address = 0x40008000; + pub const version = "1"; + + /// address: 0x40008000 + /// Clock control, can be changed on-the-fly (except for auxsrc) + pub const CLK_GPOUT0_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + /// Selects the auxiliary clock source, will glitch when switching + AUXSRC: u4, + reserved5: u1 = 0, + /// Asynchronously kills the clock generator + KILL: u1, + /// Starts and stops the clock generator cleanly + ENABLE: u1, + /// Enables duty cycle correction for odd divisors + DC50: u1, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// This delays the enable signal by up to 3 cycles of the input clock\n + /// This must be set before the clock is enabled to have any effect + PHASE: u2, + reserved9: u1 = 0, + reserved10: u1 = 0, + /// An edge on this signal shifts the phase of the output by 1 cycle of the input + /// clock\n + /// This can be done at any time + NUDGE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40008004 + /// Clock divisor, can be changed on-the-fly + pub const CLK_GPOUT0_DIV = @intToPtr(*volatile Mmio(32, packed struct { + /// Fractional component of the divisor + FRAC: u8, + /// Integer component of the divisor, 0 -> divide by 2^16 + INT: u24, + }), base_address + 0x4); + + /// address: 0x40008008 + /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + /// This slice does not have a glitchless mux (only the AUX_SRC field is present, + /// not SRC) so this register is hardwired to 0x1. + pub const CLK_GPOUT0_SELECTED = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4000800c + /// Clock control, can be changed on-the-fly (except for auxsrc) + pub const CLK_GPOUT1_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + /// Selects the auxiliary clock source, will glitch when switching + AUXSRC: u4, + reserved5: u1 = 0, + /// Asynchronously kills the clock generator + KILL: u1, + /// Starts and stops the clock generator cleanly + ENABLE: u1, + /// Enables duty cycle correction for odd divisors + DC50: u1, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// This delays the enable signal by up to 3 cycles of the input clock\n + /// This must be set before the clock is enabled to have any effect + PHASE: u2, + reserved9: u1 = 0, + reserved10: u1 = 0, + /// An edge on this signal shifts the phase of the output by 1 cycle of the input + /// clock\n + /// This can be done at any time + NUDGE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + }), base_address + 0xc); + + /// address: 0x40008010 + /// Clock divisor, can be changed on-the-fly + pub const CLK_GPOUT1_DIV = @intToPtr(*volatile Mmio(32, packed struct { + /// Fractional component of the divisor + FRAC: u8, + /// Integer component of the divisor, 0 -> divide by 2^16 + INT: u24, + }), base_address + 0x10); + + /// address: 0x40008014 + /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + /// This slice does not have a glitchless mux (only the AUX_SRC field is present, + /// not SRC) so this register is hardwired to 0x1. + pub const CLK_GPOUT1_SELECTED = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x40008018 + /// Clock control, can be changed on-the-fly (except for auxsrc) + pub const CLK_GPOUT2_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + /// Selects the auxiliary clock source, will glitch when switching + AUXSRC: u4, + reserved5: u1 = 0, + /// Asynchronously kills the clock generator + KILL: u1, + /// Starts and stops the clock generator cleanly + ENABLE: u1, + /// Enables duty cycle correction for odd divisors + DC50: u1, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// This delays the enable signal by up to 3 cycles of the input clock\n + /// This must be set before the clock is enabled to have any effect + PHASE: u2, + reserved9: u1 = 0, + reserved10: u1 = 0, + /// An edge on this signal shifts the phase of the output by 1 cycle of the input + /// clock\n + /// This can be done at any time + NUDGE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + }), base_address + 0x18); + + /// address: 0x4000801c + /// Clock divisor, can be changed on-the-fly + pub const CLK_GPOUT2_DIV = @intToPtr(*volatile Mmio(32, packed struct { + /// Fractional component of the divisor + FRAC: u8, + /// Integer component of the divisor, 0 -> divide by 2^16 + INT: u24, + }), base_address + 0x1c); + + /// address: 0x40008020 + /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + /// This slice does not have a glitchless mux (only the AUX_SRC field is present, + /// not SRC) so this register is hardwired to 0x1. + pub const CLK_GPOUT2_SELECTED = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40008024 + /// Clock control, can be changed on-the-fly (except for auxsrc) + pub const CLK_GPOUT3_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + /// Selects the auxiliary clock source, will glitch when switching + AUXSRC: u4, + reserved5: u1 = 0, + /// Asynchronously kills the clock generator + KILL: u1, + /// Starts and stops the clock generator cleanly + ENABLE: u1, + /// Enables duty cycle correction for odd divisors + DC50: u1, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// This delays the enable signal by up to 3 cycles of the input clock\n + /// This must be set before the clock is enabled to have any effect + PHASE: u2, + reserved9: u1 = 0, + reserved10: u1 = 0, + /// An edge on this signal shifts the phase of the output by 1 cycle of the input + /// clock\n + /// This can be done at any time + NUDGE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + }), base_address + 0x24); + + /// address: 0x40008028 + /// Clock divisor, can be changed on-the-fly + pub const CLK_GPOUT3_DIV = @intToPtr(*volatile Mmio(32, packed struct { + /// Fractional component of the divisor + FRAC: u8, + /// Integer component of the divisor, 0 -> divide by 2^16 + INT: u24, + }), base_address + 0x28); + + /// address: 0x4000802c + /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + /// This slice does not have a glitchless mux (only the AUX_SRC field is present, + /// not SRC) so this register is hardwired to 0x1. + pub const CLK_GPOUT3_SELECTED = @intToPtr(*volatile u32, base_address + 0x2c); + + /// address: 0x40008030 + /// Clock control, can be changed on-the-fly (except for auxsrc) + pub const CLK_REF_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the clock source glitchlessly, can be changed on-the-fly + SRC: u2, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// Selects the auxiliary clock source, will glitch when switching + AUXSRC: u2, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + }), base_address + 0x30); + + /// address: 0x40008034 + /// Clock divisor, can be changed on-the-fly + pub const CLK_REF_DIV = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Integer component of the divisor, 0 -> divide by 2^16 + INT: u2, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + }), base_address + 0x34); + + /// address: 0x40008038 + /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + /// The glitchless multiplexer does not switch instantaneously (to avoid glitches), + /// so software should poll this register to wait for the switch to complete. This + /// register contains one decoded bit for each of the clock sources enumerated in + /// the CTRL SRC field. At most one of these bits will be set at any time, + /// indicating that clock is currently present at the output of the glitchless mux. + /// Whilst switching is in progress, this register may briefly show all-0s. + pub const CLK_REF_SELECTED = @intToPtr(*volatile u32, base_address + 0x38); + + /// address: 0x4000803c + /// Clock control, can be changed on-the-fly (except for auxsrc) + pub const CLK_SYS_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Selects the clock source glitchlessly, can be changed on-the-fly + SRC: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// Selects the auxiliary clock source, will glitch when switching + AUXSRC: u3, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x3c); + + /// address: 0x40008040 + /// Clock divisor, can be changed on-the-fly + pub const CLK_SYS_DIV = @intToPtr(*volatile Mmio(32, packed struct { + /// Fractional component of the divisor + FRAC: u8, + /// Integer component of the divisor, 0 -> divide by 2^16 + INT: u24, + }), base_address + 0x40); + + /// address: 0x40008044 + /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + /// The glitchless multiplexer does not switch instantaneously (to avoid glitches), + /// so software should poll this register to wait for the switch to complete. This + /// register contains one decoded bit for each of the clock sources enumerated in + /// the CTRL SRC field. At most one of these bits will be set at any time, + /// indicating that clock is currently present at the output of the glitchless mux. + /// Whilst switching is in progress, this register may briefly show all-0s. + pub const CLK_SYS_SELECTED = @intToPtr(*volatile u32, base_address + 0x44); + + /// address: 0x40008048 + /// Clock control, can be changed on-the-fly (except for auxsrc) + pub const CLK_PERI_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + /// Selects the auxiliary clock source, will glitch when switching + AUXSRC: u3, + reserved5: u1 = 0, + reserved6: u1 = 0, + /// Asynchronously kills the clock generator + KILL: u1, + /// Starts and stops the clock generator cleanly + ENABLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x48); + + /// address: 0x40008050 + /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + /// This slice does not have a glitchless mux (only the AUX_SRC field is present, + /// not SRC) so this register is hardwired to 0x1. + pub const CLK_PERI_SELECTED = @intToPtr(*volatile u32, base_address + 0x50); + + /// address: 0x40008054 + /// Clock control, can be changed on-the-fly (except for auxsrc) + pub const CLK_USB_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + /// Selects the auxiliary clock source, will glitch when switching + AUXSRC: u3, + reserved5: u1 = 0, + reserved6: u1 = 0, + /// Asynchronously kills the clock generator + KILL: u1, + /// Starts and stops the clock generator cleanly + ENABLE: u1, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + /// This delays the enable signal by up to 3 cycles of the input clock\n + /// This must be set before the clock is enabled to have any effect + PHASE: u2, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// An edge on this signal shifts the phase of the output by 1 cycle of the input + /// clock\n + /// This can be done at any time + NUDGE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + }), base_address + 0x54); + + /// address: 0x40008058 + /// Clock divisor, can be changed on-the-fly + pub const CLK_USB_DIV = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Integer component of the divisor, 0 -> divide by 2^16 + INT: u2, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + }), base_address + 0x58); + + /// address: 0x4000805c + /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + /// This slice does not have a glitchless mux (only the AUX_SRC field is present, + /// not SRC) so this register is hardwired to 0x1. + pub const CLK_USB_SELECTED = @intToPtr(*volatile u32, base_address + 0x5c); + + /// address: 0x40008060 + /// Clock control, can be changed on-the-fly (except for auxsrc) + pub const CLK_ADC_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + /// Selects the auxiliary clock source, will glitch when switching + AUXSRC: u3, + reserved5: u1 = 0, + reserved6: u1 = 0, + /// Asynchronously kills the clock generator + KILL: u1, + /// Starts and stops the clock generator cleanly + ENABLE: u1, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + /// This delays the enable signal by up to 3 cycles of the input clock\n + /// This must be set before the clock is enabled to have any effect + PHASE: u2, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// An edge on this signal shifts the phase of the output by 1 cycle of the input + /// clock\n + /// This can be done at any time + NUDGE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + }), base_address + 0x60); + + /// address: 0x40008064 + /// Clock divisor, can be changed on-the-fly + pub const CLK_ADC_DIV = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Integer component of the divisor, 0 -> divide by 2^16 + INT: u2, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + }), base_address + 0x64); + + /// address: 0x40008068 + /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + /// This slice does not have a glitchless mux (only the AUX_SRC field is present, + /// not SRC) so this register is hardwired to 0x1. + pub const CLK_ADC_SELECTED = @intToPtr(*volatile u32, base_address + 0x68); + + /// address: 0x4000806c + /// Clock control, can be changed on-the-fly (except for auxsrc) + pub const CLK_RTC_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + /// Selects the auxiliary clock source, will glitch when switching + AUXSRC: u3, + reserved5: u1 = 0, + reserved6: u1 = 0, + /// Asynchronously kills the clock generator + KILL: u1, + /// Starts and stops the clock generator cleanly + ENABLE: u1, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + /// This delays the enable signal by up to 3 cycles of the input clock\n + /// This must be set before the clock is enabled to have any effect + PHASE: u2, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// An edge on this signal shifts the phase of the output by 1 cycle of the input + /// clock\n + /// This can be done at any time + NUDGE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + }), base_address + 0x6c); + + /// address: 0x40008070 + /// Clock divisor, can be changed on-the-fly + pub const CLK_RTC_DIV = @intToPtr(*volatile Mmio(32, packed struct { + /// Fractional component of the divisor + FRAC: u8, + /// Integer component of the divisor, 0 -> divide by 2^16 + INT: u24, + }), base_address + 0x70); + + /// address: 0x40008074 + /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n + /// This slice does not have a glitchless mux (only the AUX_SRC field is present, + /// not SRC) so this register is hardwired to 0x1. + pub const CLK_RTC_SELECTED = @intToPtr(*volatile u32, base_address + 0x74); + + /// address: 0x40008078 + pub const CLK_SYS_RESUS_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// This is expressed as a number of clk_ref cycles\n + /// and must be >= 2x clk_ref_freq/min_clk_tst_freq + TIMEOUT: u8, + /// Enable resus + ENABLE: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// Force a resus, for test purposes only + FRCE: u1, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// For clearing the resus after the fault that triggered it has been corrected + CLEAR: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + }), base_address + 0x78); + + /// address: 0x4000807c + pub const CLK_SYS_RESUS_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock has been resuscitated, correct the error then send ctrl_clear=1 + RESUSSED: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x7c); + + /// address: 0x40008080 + /// Reference clock frequency in kHz + pub const FC0_REF_KHZ = @intToPtr(*volatile MmioInt(32, u20), base_address + 0x80); + + /// address: 0x40008084 + /// Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using + /// the pass/fail flags + pub const FC0_MIN_KHZ = @intToPtr(*volatile MmioInt(32, u25), base_address + 0x84); + + /// address: 0x40008088 + /// Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not + /// using the pass/fail flags + pub const FC0_MAX_KHZ = @intToPtr(*volatile MmioInt(32, u25), base_address + 0x88); + + /// address: 0x4000808c + /// Delays the start of frequency counting to allow the mux to settle\n + /// Delay is measured in multiples of the reference clock period + pub const FC0_DELAY = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x8c); + + /// address: 0x40008090 + /// The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n + /// The default gives a test interval of 250us + pub const FC0_INTERVAL = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x90); + + /// address: 0x40008094 + /// Clock sent to frequency counter, set to 0 when not required\n + /// Writing to this register initiates the frequency count + pub const FC0_SRC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x94); + + /// address: 0x40008098 + /// Frequency counter status + pub const FC0_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Test passed + PASS: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// Test complete + DONE: u1, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// Test running + RUNNING: u1, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Waiting for test clock to start + WAITING: u1, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// Test failed + FAIL: u1, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + /// Test clock slower than expected, only valid when status_done=1 + SLOW: u1, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// Test clock faster than expected, only valid when status_done=1 + FAST: u1, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + /// Test clock stopped during test + DIED: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + }), base_address + 0x98); + + /// address: 0x4000809c + /// Result of frequency measurement, only valid when status_done=1 + pub const FC0_RESULT = @intToPtr(*volatile Mmio(32, packed struct { + FRAC: u5, + KHZ: u25, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x9c); + + /// address: 0x400080a0 + /// enable clock in wake mode + pub const WAKE_EN0 = @intToPtr(*volatile Mmio(32, packed struct { + clk_sys_clocks: u1, + clk_adc_adc: u1, + clk_sys_adc: u1, + clk_sys_busctrl: u1, + clk_sys_busfabric: u1, + clk_sys_dma: u1, + clk_sys_i2c0: u1, + clk_sys_i2c1: u1, + clk_sys_io: u1, + clk_sys_jtag: u1, + clk_sys_vreg_and_chip_reset: u1, + clk_sys_pads: u1, + clk_sys_pio0: u1, + clk_sys_pio1: u1, + clk_sys_pll_sys: u1, + clk_sys_pll_usb: u1, + clk_sys_psm: u1, + clk_sys_pwm: u1, + clk_sys_resets: u1, + clk_sys_rom: u1, + clk_sys_rosc: u1, + clk_rtc_rtc: u1, + clk_sys_rtc: u1, + clk_sys_sio: u1, + clk_peri_spi0: u1, + clk_sys_spi0: u1, + clk_peri_spi1: u1, + clk_sys_spi1: u1, + clk_sys_sram0: u1, + clk_sys_sram1: u1, + clk_sys_sram2: u1, + clk_sys_sram3: u1, + }), base_address + 0xa0); + + /// address: 0x400080a4 + /// enable clock in wake mode + pub const WAKE_EN1 = @intToPtr(*volatile Mmio(32, packed struct { + clk_sys_sram4: u1, + clk_sys_sram5: u1, + clk_sys_syscfg: u1, + clk_sys_sysinfo: u1, + clk_sys_tbman: u1, + clk_sys_timer: u1, + clk_peri_uart0: u1, + clk_sys_uart0: u1, + clk_peri_uart1: u1, + clk_sys_uart1: u1, + clk_sys_usbctrl: u1, + clk_usb_usbctrl: u1, + clk_sys_watchdog: u1, + clk_sys_xip: u1, + clk_sys_xosc: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + }), base_address + 0xa4); + + /// address: 0x400080a8 + /// enable clock in sleep mode + pub const SLEEP_EN0 = @intToPtr(*volatile Mmio(32, packed struct { + clk_sys_clocks: u1, + clk_adc_adc: u1, + clk_sys_adc: u1, + clk_sys_busctrl: u1, + clk_sys_busfabric: u1, + clk_sys_dma: u1, + clk_sys_i2c0: u1, + clk_sys_i2c1: u1, + clk_sys_io: u1, + clk_sys_jtag: u1, + clk_sys_vreg_and_chip_reset: u1, + clk_sys_pads: u1, + clk_sys_pio0: u1, + clk_sys_pio1: u1, + clk_sys_pll_sys: u1, + clk_sys_pll_usb: u1, + clk_sys_psm: u1, + clk_sys_pwm: u1, + clk_sys_resets: u1, + clk_sys_rom: u1, + clk_sys_rosc: u1, + clk_rtc_rtc: u1, + clk_sys_rtc: u1, + clk_sys_sio: u1, + clk_peri_spi0: u1, + clk_sys_spi0: u1, + clk_peri_spi1: u1, + clk_sys_spi1: u1, + clk_sys_sram0: u1, + clk_sys_sram1: u1, + clk_sys_sram2: u1, + clk_sys_sram3: u1, + }), base_address + 0xa8); + + /// address: 0x400080ac + /// enable clock in sleep mode + pub const SLEEP_EN1 = @intToPtr(*volatile Mmio(32, packed struct { + clk_sys_sram4: u1, + clk_sys_sram5: u1, + clk_sys_syscfg: u1, + clk_sys_sysinfo: u1, + clk_sys_tbman: u1, + clk_sys_timer: u1, + clk_peri_uart0: u1, + clk_sys_uart0: u1, + clk_peri_uart1: u1, + clk_sys_uart1: u1, + clk_sys_usbctrl: u1, + clk_usb_usbctrl: u1, + clk_sys_watchdog: u1, + clk_sys_xip: u1, + clk_sys_xosc: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + }), base_address + 0xac); + + /// address: 0x400080b0 + /// indicates the state of the clock enable + pub const ENABLED0 = @intToPtr(*volatile Mmio(32, packed struct { + clk_sys_clocks: u1, + clk_adc_adc: u1, + clk_sys_adc: u1, + clk_sys_busctrl: u1, + clk_sys_busfabric: u1, + clk_sys_dma: u1, + clk_sys_i2c0: u1, + clk_sys_i2c1: u1, + clk_sys_io: u1, + clk_sys_jtag: u1, + clk_sys_vreg_and_chip_reset: u1, + clk_sys_pads: u1, + clk_sys_pio0: u1, + clk_sys_pio1: u1, + clk_sys_pll_sys: u1, + clk_sys_pll_usb: u1, + clk_sys_psm: u1, + clk_sys_pwm: u1, + clk_sys_resets: u1, + clk_sys_rom: u1, + clk_sys_rosc: u1, + clk_rtc_rtc: u1, + clk_sys_rtc: u1, + clk_sys_sio: u1, + clk_peri_spi0: u1, + clk_sys_spi0: u1, + clk_peri_spi1: u1, + clk_sys_spi1: u1, + clk_sys_sram0: u1, + clk_sys_sram1: u1, + clk_sys_sram2: u1, + clk_sys_sram3: u1, + }), base_address + 0xb0); + + /// address: 0x400080b4 + /// indicates the state of the clock enable + pub const ENABLED1 = @intToPtr(*volatile Mmio(32, packed struct { + clk_sys_sram4: u1, + clk_sys_sram5: u1, + clk_sys_syscfg: u1, + clk_sys_sysinfo: u1, + clk_sys_tbman: u1, + clk_sys_timer: u1, + clk_peri_uart0: u1, + clk_sys_uart0: u1, + clk_peri_uart1: u1, + clk_sys_uart1: u1, + clk_sys_usbctrl: u1, + clk_usb_usbctrl: u1, + clk_sys_watchdog: u1, + clk_sys_xip: u1, + clk_sys_xosc: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + }), base_address + 0xb4); + + /// address: 0x400080b8 + /// Raw Interrupts + pub const INTR = @intToPtr(*volatile Mmio(32, packed struct { + CLK_SYS_RESUS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0xb8); + + /// address: 0x400080bc + /// Interrupt Enable + pub const INTE = @intToPtr(*volatile Mmio(32, packed struct { + CLK_SYS_RESUS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0xbc); + + /// address: 0x400080c0 + /// Interrupt Force + pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { + CLK_SYS_RESUS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0xc0); + + /// address: 0x400080c4 + /// Interrupt status after masking & forcing + pub const INTS = @intToPtr(*volatile Mmio(32, packed struct { + CLK_SYS_RESUS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0xc4); + }; + pub const RESETS = struct { + pub const base_address = 0x4000c000; + pub const version = "1"; + + /// address: 0x4000c000 + /// Reset control. If a bit is set it means the peripheral is in reset. 0 means the + /// peripheral's reset is deasserted. + pub const RESET = @intToPtr(*volatile Mmio(32, packed struct { + adc: u1, + busctrl: u1, + dma: u1, + i2c0: u1, + i2c1: u1, + io_bank0: u1, + io_qspi: u1, + jtag: u1, + pads_bank0: u1, + pads_qspi: u1, + pio0: u1, + pio1: u1, + pll_sys: u1, + pll_usb: u1, + pwm: u1, + rtc: u1, + spi0: u1, + spi1: u1, + syscfg: u1, + sysinfo: u1, + tbman: u1, + timer: u1, + uart0: u1, + uart1: u1, + usbctrl: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + }), base_address + 0x0); + + /// address: 0x4000c004 + /// Watchdog select. If a bit is set then the watchdog will reset this peripheral + /// when the watchdog fires. + pub const WDSEL = @intToPtr(*volatile Mmio(32, packed struct { + adc: u1, + busctrl: u1, + dma: u1, + i2c0: u1, + i2c1: u1, + io_bank0: u1, + io_qspi: u1, + jtag: u1, + pads_bank0: u1, + pads_qspi: u1, + pio0: u1, + pio1: u1, + pll_sys: u1, + pll_usb: u1, + pwm: u1, + rtc: u1, + spi0: u1, + spi1: u1, + syscfg: u1, + sysinfo: u1, + tbman: u1, + timer: u1, + uart0: u1, + uart1: u1, + usbctrl: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + }), base_address + 0x4); + + /// address: 0x4000c008 + /// Reset done. If a bit is set then a reset done signal has been returned by the + /// peripheral. This indicates that the peripheral's registers are ready to be + /// accessed. + pub const RESET_DONE = @intToPtr(*volatile Mmio(32, packed struct { + adc: u1, + busctrl: u1, + dma: u1, + i2c0: u1, + i2c1: u1, + io_bank0: u1, + io_qspi: u1, + jtag: u1, + pads_bank0: u1, + pads_qspi: u1, + pio0: u1, + pio1: u1, + pll_sys: u1, + pll_usb: u1, + pwm: u1, + rtc: u1, + spi0: u1, + spi1: u1, + syscfg: u1, + sysinfo: u1, + tbman: u1, + timer: u1, + uart0: u1, + uart1: u1, + usbctrl: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + }), base_address + 0x8); + }; + pub const PSM = struct { + pub const base_address = 0x40010000; + pub const version = "1"; + + /// address: 0x40010000 + /// Force block out of reset (i.e. power it on) + pub const FRCE_ON = @intToPtr(*volatile Mmio(32, packed struct { + rosc: u1, + xosc: u1, + clocks: u1, + resets: u1, + busfabric: u1, + rom: u1, + sram0: u1, + sram1: u1, + sram2: u1, + sram3: u1, + sram4: u1, + sram5: u1, + xip: u1, + vreg_and_chip_reset: u1, + sio: u1, + proc0: u1, + proc1: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40010004 + /// Force into reset (i.e. power it off) + pub const FRCE_OFF = @intToPtr(*volatile Mmio(32, packed struct { + rosc: u1, + xosc: u1, + clocks: u1, + resets: u1, + busfabric: u1, + rom: u1, + sram0: u1, + sram1: u1, + sram2: u1, + sram3: u1, + sram4: u1, + sram5: u1, + xip: u1, + vreg_and_chip_reset: u1, + sio: u1, + proc0: u1, + proc1: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40010008 + /// Set to 1 if this peripheral should be reset when the watchdog fires. + pub const WDSEL = @intToPtr(*volatile Mmio(32, packed struct { + rosc: u1, + xosc: u1, + clocks: u1, + resets: u1, + busfabric: u1, + rom: u1, + sram0: u1, + sram1: u1, + sram2: u1, + sram3: u1, + sram4: u1, + sram5: u1, + xip: u1, + vreg_and_chip_reset: u1, + sio: u1, + proc0: u1, + proc1: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + }), base_address + 0x8); + + /// address: 0x4001000c + /// Indicates the peripheral's registers are ready to access. + pub const DONE = @intToPtr(*volatile Mmio(32, packed struct { + rosc: u1, + xosc: u1, + clocks: u1, + resets: u1, + busfabric: u1, + rom: u1, + sram0: u1, + sram1: u1, + sram2: u1, + sram3: u1, + sram4: u1, + sram5: u1, + xip: u1, + vreg_and_chip_reset: u1, + sio: u1, + proc0: u1, + proc1: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + }), base_address + 0xc); + }; + pub const IO_BANK0 = struct { + pub const base_address = 0x40014000; + pub const version = "1"; + + /// address: 0x40014000 + /// GPIO status + pub const GPIO0_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40014004 + /// GPIO control including function select and overrides. + pub const GPIO0_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40014008 + /// GPIO status + pub const GPIO1_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x8); + + /// address: 0x4001400c + /// GPIO control including function select and overrides. + pub const GPIO1_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xc); + + /// address: 0x40014010 + /// GPIO status + pub const GPIO2_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x10); + + /// address: 0x40014014 + /// GPIO control including function select and overrides. + pub const GPIO2_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x14); + + /// address: 0x40014018 + /// GPIO status + pub const GPIO3_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x18); + + /// address: 0x4001401c + /// GPIO control including function select and overrides. + pub const GPIO3_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x1c); + + /// address: 0x40014020 + /// GPIO status + pub const GPIO4_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x20); + + /// address: 0x40014024 + /// GPIO control including function select and overrides. + pub const GPIO4_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x24); + + /// address: 0x40014028 + /// GPIO status + pub const GPIO5_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x28); + + /// address: 0x4001402c + /// GPIO control including function select and overrides. + pub const GPIO5_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x2c); + + /// address: 0x40014030 + /// GPIO status + pub const GPIO6_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x30); + + /// address: 0x40014034 + /// GPIO control including function select and overrides. + pub const GPIO6_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x34); + + /// address: 0x40014038 + /// GPIO status + pub const GPIO7_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x38); + + /// address: 0x4001403c + /// GPIO control including function select and overrides. + pub const GPIO7_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x3c); + + /// address: 0x40014040 + /// GPIO status + pub const GPIO8_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x40); + + /// address: 0x40014044 + /// GPIO control including function select and overrides. + pub const GPIO8_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x44); + + /// address: 0x40014048 + /// GPIO status + pub const GPIO9_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x48); + + /// address: 0x4001404c + /// GPIO control including function select and overrides. + pub const GPIO9_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x4c); + + /// address: 0x40014050 + /// GPIO status + pub const GPIO10_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x50); + + /// address: 0x40014054 + /// GPIO control including function select and overrides. + pub const GPIO10_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x54); + + /// address: 0x40014058 + /// GPIO status + pub const GPIO11_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x58); + + /// address: 0x4001405c + /// GPIO control including function select and overrides. + pub const GPIO11_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x5c); + + /// address: 0x40014060 + /// GPIO status + pub const GPIO12_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x60); + + /// address: 0x40014064 + /// GPIO control including function select and overrides. + pub const GPIO12_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x64); + + /// address: 0x40014068 + /// GPIO status + pub const GPIO13_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x68); + + /// address: 0x4001406c + /// GPIO control including function select and overrides. + pub const GPIO13_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x6c); + + /// address: 0x40014070 + /// GPIO status + pub const GPIO14_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x70); + + /// address: 0x40014074 + /// GPIO control including function select and overrides. + pub const GPIO14_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x74); + + /// address: 0x40014078 + /// GPIO status + pub const GPIO15_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x78); + + /// address: 0x4001407c + /// GPIO control including function select and overrides. + pub const GPIO15_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x7c); + + /// address: 0x40014080 + /// GPIO status + pub const GPIO16_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x80); + + /// address: 0x40014084 + /// GPIO control including function select and overrides. + pub const GPIO16_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x84); + + /// address: 0x40014088 + /// GPIO status + pub const GPIO17_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x88); + + /// address: 0x4001408c + /// GPIO control including function select and overrides. + pub const GPIO17_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x8c); + + /// address: 0x40014090 + /// GPIO status + pub const GPIO18_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x90); + + /// address: 0x40014094 + /// GPIO control including function select and overrides. + pub const GPIO18_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x94); + + /// address: 0x40014098 + /// GPIO status + pub const GPIO19_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x98); + + /// address: 0x4001409c + /// GPIO control including function select and overrides. + pub const GPIO19_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x9c); + + /// address: 0x400140a0 + /// GPIO status + pub const GPIO20_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0xa0); + + /// address: 0x400140a4 + /// GPIO control including function select and overrides. + pub const GPIO20_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xa4); + + /// address: 0x400140a8 + /// GPIO status + pub const GPIO21_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0xa8); + + /// address: 0x400140ac + /// GPIO control including function select and overrides. + pub const GPIO21_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xac); + + /// address: 0x400140b0 + /// GPIO status + pub const GPIO22_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0xb0); + + /// address: 0x400140b4 + /// GPIO control including function select and overrides. + pub const GPIO22_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xb4); + + /// address: 0x400140b8 + /// GPIO status + pub const GPIO23_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0xb8); + + /// address: 0x400140bc + /// GPIO control including function select and overrides. + pub const GPIO23_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xbc); + + /// address: 0x400140c0 + /// GPIO status + pub const GPIO24_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0xc0); + + /// address: 0x400140c4 + /// GPIO control including function select and overrides. + pub const GPIO24_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xc4); + + /// address: 0x400140c8 + /// GPIO status + pub const GPIO25_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0xc8); + + /// address: 0x400140cc + /// GPIO control including function select and overrides. + pub const GPIO25_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xcc); + + /// address: 0x400140d0 + /// GPIO status + pub const GPIO26_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0xd0); + + /// address: 0x400140d4 + /// GPIO control including function select and overrides. + pub const GPIO26_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xd4); + + /// address: 0x400140d8 + /// GPIO status + pub const GPIO27_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0xd8); + + /// address: 0x400140dc + /// GPIO control including function select and overrides. + pub const GPIO27_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xdc); + + /// address: 0x400140e0 + /// GPIO status + pub const GPIO28_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0xe0); + + /// address: 0x400140e4 + /// GPIO control including function select and overrides. + pub const GPIO28_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xe4); + + /// address: 0x400140e8 + /// GPIO status + pub const GPIO29_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0xe8); + + /// address: 0x400140ec + /// GPIO control including function select and overrides. + pub const GPIO29_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xec); + + /// address: 0x400140f0 + /// Raw Interrupts + pub const INTR0 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO0_LEVEL_LOW: u1, + GPIO0_LEVEL_HIGH: u1, + GPIO0_EDGE_LOW: u1, + GPIO0_EDGE_HIGH: u1, + GPIO1_LEVEL_LOW: u1, + GPIO1_LEVEL_HIGH: u1, + GPIO1_EDGE_LOW: u1, + GPIO1_EDGE_HIGH: u1, + GPIO2_LEVEL_LOW: u1, + GPIO2_LEVEL_HIGH: u1, + GPIO2_EDGE_LOW: u1, + GPIO2_EDGE_HIGH: u1, + GPIO3_LEVEL_LOW: u1, + GPIO3_LEVEL_HIGH: u1, + GPIO3_EDGE_LOW: u1, + GPIO3_EDGE_HIGH: u1, + GPIO4_LEVEL_LOW: u1, + GPIO4_LEVEL_HIGH: u1, + GPIO4_EDGE_LOW: u1, + GPIO4_EDGE_HIGH: u1, + GPIO5_LEVEL_LOW: u1, + GPIO5_LEVEL_HIGH: u1, + GPIO5_EDGE_LOW: u1, + GPIO5_EDGE_HIGH: u1, + GPIO6_LEVEL_LOW: u1, + GPIO6_LEVEL_HIGH: u1, + GPIO6_EDGE_LOW: u1, + GPIO6_EDGE_HIGH: u1, + GPIO7_LEVEL_LOW: u1, + GPIO7_LEVEL_HIGH: u1, + GPIO7_EDGE_LOW: u1, + GPIO7_EDGE_HIGH: u1, + }), base_address + 0xf0); + + /// address: 0x400140f4 + /// Raw Interrupts + pub const INTR1 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO8_LEVEL_LOW: u1, + GPIO8_LEVEL_HIGH: u1, + GPIO8_EDGE_LOW: u1, + GPIO8_EDGE_HIGH: u1, + GPIO9_LEVEL_LOW: u1, + GPIO9_LEVEL_HIGH: u1, + GPIO9_EDGE_LOW: u1, + GPIO9_EDGE_HIGH: u1, + GPIO10_LEVEL_LOW: u1, + GPIO10_LEVEL_HIGH: u1, + GPIO10_EDGE_LOW: u1, + GPIO10_EDGE_HIGH: u1, + GPIO11_LEVEL_LOW: u1, + GPIO11_LEVEL_HIGH: u1, + GPIO11_EDGE_LOW: u1, + GPIO11_EDGE_HIGH: u1, + GPIO12_LEVEL_LOW: u1, + GPIO12_LEVEL_HIGH: u1, + GPIO12_EDGE_LOW: u1, + GPIO12_EDGE_HIGH: u1, + GPIO13_LEVEL_LOW: u1, + GPIO13_LEVEL_HIGH: u1, + GPIO13_EDGE_LOW: u1, + GPIO13_EDGE_HIGH: u1, + GPIO14_LEVEL_LOW: u1, + GPIO14_LEVEL_HIGH: u1, + GPIO14_EDGE_LOW: u1, + GPIO14_EDGE_HIGH: u1, + GPIO15_LEVEL_LOW: u1, + GPIO15_LEVEL_HIGH: u1, + GPIO15_EDGE_LOW: u1, + GPIO15_EDGE_HIGH: u1, + }), base_address + 0xf4); + + /// address: 0x400140f8 + /// Raw Interrupts + pub const INTR2 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO16_LEVEL_LOW: u1, + GPIO16_LEVEL_HIGH: u1, + GPIO16_EDGE_LOW: u1, + GPIO16_EDGE_HIGH: u1, + GPIO17_LEVEL_LOW: u1, + GPIO17_LEVEL_HIGH: u1, + GPIO17_EDGE_LOW: u1, + GPIO17_EDGE_HIGH: u1, + GPIO18_LEVEL_LOW: u1, + GPIO18_LEVEL_HIGH: u1, + GPIO18_EDGE_LOW: u1, + GPIO18_EDGE_HIGH: u1, + GPIO19_LEVEL_LOW: u1, + GPIO19_LEVEL_HIGH: u1, + GPIO19_EDGE_LOW: u1, + GPIO19_EDGE_HIGH: u1, + GPIO20_LEVEL_LOW: u1, + GPIO20_LEVEL_HIGH: u1, + GPIO20_EDGE_LOW: u1, + GPIO20_EDGE_HIGH: u1, + GPIO21_LEVEL_LOW: u1, + GPIO21_LEVEL_HIGH: u1, + GPIO21_EDGE_LOW: u1, + GPIO21_EDGE_HIGH: u1, + GPIO22_LEVEL_LOW: u1, + GPIO22_LEVEL_HIGH: u1, + GPIO22_EDGE_LOW: u1, + GPIO22_EDGE_HIGH: u1, + GPIO23_LEVEL_LOW: u1, + GPIO23_LEVEL_HIGH: u1, + GPIO23_EDGE_LOW: u1, + GPIO23_EDGE_HIGH: u1, + }), base_address + 0xf8); + + /// address: 0x400140fc + /// Raw Interrupts + pub const INTR3 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO24_LEVEL_LOW: u1, + GPIO24_LEVEL_HIGH: u1, + GPIO24_EDGE_LOW: u1, + GPIO24_EDGE_HIGH: u1, + GPIO25_LEVEL_LOW: u1, + GPIO25_LEVEL_HIGH: u1, + GPIO25_EDGE_LOW: u1, + GPIO25_EDGE_HIGH: u1, + GPIO26_LEVEL_LOW: u1, + GPIO26_LEVEL_HIGH: u1, + GPIO26_EDGE_LOW: u1, + GPIO26_EDGE_HIGH: u1, + GPIO27_LEVEL_LOW: u1, + GPIO27_LEVEL_HIGH: u1, + GPIO27_EDGE_LOW: u1, + GPIO27_EDGE_HIGH: u1, + GPIO28_LEVEL_LOW: u1, + GPIO28_LEVEL_HIGH: u1, + GPIO28_EDGE_LOW: u1, + GPIO28_EDGE_HIGH: u1, + GPIO29_LEVEL_LOW: u1, + GPIO29_LEVEL_HIGH: u1, + GPIO29_EDGE_LOW: u1, + GPIO29_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0xfc); + + /// address: 0x40014100 + /// Interrupt Enable for proc0 + pub const PROC0_INTE0 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO0_LEVEL_LOW: u1, + GPIO0_LEVEL_HIGH: u1, + GPIO0_EDGE_LOW: u1, + GPIO0_EDGE_HIGH: u1, + GPIO1_LEVEL_LOW: u1, + GPIO1_LEVEL_HIGH: u1, + GPIO1_EDGE_LOW: u1, + GPIO1_EDGE_HIGH: u1, + GPIO2_LEVEL_LOW: u1, + GPIO2_LEVEL_HIGH: u1, + GPIO2_EDGE_LOW: u1, + GPIO2_EDGE_HIGH: u1, + GPIO3_LEVEL_LOW: u1, + GPIO3_LEVEL_HIGH: u1, + GPIO3_EDGE_LOW: u1, + GPIO3_EDGE_HIGH: u1, + GPIO4_LEVEL_LOW: u1, + GPIO4_LEVEL_HIGH: u1, + GPIO4_EDGE_LOW: u1, + GPIO4_EDGE_HIGH: u1, + GPIO5_LEVEL_LOW: u1, + GPIO5_LEVEL_HIGH: u1, + GPIO5_EDGE_LOW: u1, + GPIO5_EDGE_HIGH: u1, + GPIO6_LEVEL_LOW: u1, + GPIO6_LEVEL_HIGH: u1, + GPIO6_EDGE_LOW: u1, + GPIO6_EDGE_HIGH: u1, + GPIO7_LEVEL_LOW: u1, + GPIO7_LEVEL_HIGH: u1, + GPIO7_EDGE_LOW: u1, + GPIO7_EDGE_HIGH: u1, + }), base_address + 0x100); + + /// address: 0x40014104 + /// Interrupt Enable for proc0 + pub const PROC0_INTE1 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO8_LEVEL_LOW: u1, + GPIO8_LEVEL_HIGH: u1, + GPIO8_EDGE_LOW: u1, + GPIO8_EDGE_HIGH: u1, + GPIO9_LEVEL_LOW: u1, + GPIO9_LEVEL_HIGH: u1, + GPIO9_EDGE_LOW: u1, + GPIO9_EDGE_HIGH: u1, + GPIO10_LEVEL_LOW: u1, + GPIO10_LEVEL_HIGH: u1, + GPIO10_EDGE_LOW: u1, + GPIO10_EDGE_HIGH: u1, + GPIO11_LEVEL_LOW: u1, + GPIO11_LEVEL_HIGH: u1, + GPIO11_EDGE_LOW: u1, + GPIO11_EDGE_HIGH: u1, + GPIO12_LEVEL_LOW: u1, + GPIO12_LEVEL_HIGH: u1, + GPIO12_EDGE_LOW: u1, + GPIO12_EDGE_HIGH: u1, + GPIO13_LEVEL_LOW: u1, + GPIO13_LEVEL_HIGH: u1, + GPIO13_EDGE_LOW: u1, + GPIO13_EDGE_HIGH: u1, + GPIO14_LEVEL_LOW: u1, + GPIO14_LEVEL_HIGH: u1, + GPIO14_EDGE_LOW: u1, + GPIO14_EDGE_HIGH: u1, + GPIO15_LEVEL_LOW: u1, + GPIO15_LEVEL_HIGH: u1, + GPIO15_EDGE_LOW: u1, + GPIO15_EDGE_HIGH: u1, + }), base_address + 0x104); + + /// address: 0x40014108 + /// Interrupt Enable for proc0 + pub const PROC0_INTE2 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO16_LEVEL_LOW: u1, + GPIO16_LEVEL_HIGH: u1, + GPIO16_EDGE_LOW: u1, + GPIO16_EDGE_HIGH: u1, + GPIO17_LEVEL_LOW: u1, + GPIO17_LEVEL_HIGH: u1, + GPIO17_EDGE_LOW: u1, + GPIO17_EDGE_HIGH: u1, + GPIO18_LEVEL_LOW: u1, + GPIO18_LEVEL_HIGH: u1, + GPIO18_EDGE_LOW: u1, + GPIO18_EDGE_HIGH: u1, + GPIO19_LEVEL_LOW: u1, + GPIO19_LEVEL_HIGH: u1, + GPIO19_EDGE_LOW: u1, + GPIO19_EDGE_HIGH: u1, + GPIO20_LEVEL_LOW: u1, + GPIO20_LEVEL_HIGH: u1, + GPIO20_EDGE_LOW: u1, + GPIO20_EDGE_HIGH: u1, + GPIO21_LEVEL_LOW: u1, + GPIO21_LEVEL_HIGH: u1, + GPIO21_EDGE_LOW: u1, + GPIO21_EDGE_HIGH: u1, + GPIO22_LEVEL_LOW: u1, + GPIO22_LEVEL_HIGH: u1, + GPIO22_EDGE_LOW: u1, + GPIO22_EDGE_HIGH: u1, + GPIO23_LEVEL_LOW: u1, + GPIO23_LEVEL_HIGH: u1, + GPIO23_EDGE_LOW: u1, + GPIO23_EDGE_HIGH: u1, + }), base_address + 0x108); + + /// address: 0x4001410c + /// Interrupt Enable for proc0 + pub const PROC0_INTE3 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO24_LEVEL_LOW: u1, + GPIO24_LEVEL_HIGH: u1, + GPIO24_EDGE_LOW: u1, + GPIO24_EDGE_HIGH: u1, + GPIO25_LEVEL_LOW: u1, + GPIO25_LEVEL_HIGH: u1, + GPIO25_EDGE_LOW: u1, + GPIO25_EDGE_HIGH: u1, + GPIO26_LEVEL_LOW: u1, + GPIO26_LEVEL_HIGH: u1, + GPIO26_EDGE_LOW: u1, + GPIO26_EDGE_HIGH: u1, + GPIO27_LEVEL_LOW: u1, + GPIO27_LEVEL_HIGH: u1, + GPIO27_EDGE_LOW: u1, + GPIO27_EDGE_HIGH: u1, + GPIO28_LEVEL_LOW: u1, + GPIO28_LEVEL_HIGH: u1, + GPIO28_EDGE_LOW: u1, + GPIO28_EDGE_HIGH: u1, + GPIO29_LEVEL_LOW: u1, + GPIO29_LEVEL_HIGH: u1, + GPIO29_EDGE_LOW: u1, + GPIO29_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x10c); + + /// address: 0x40014110 + /// Interrupt Force for proc0 + pub const PROC0_INTF0 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO0_LEVEL_LOW: u1, + GPIO0_LEVEL_HIGH: u1, + GPIO0_EDGE_LOW: u1, + GPIO0_EDGE_HIGH: u1, + GPIO1_LEVEL_LOW: u1, + GPIO1_LEVEL_HIGH: u1, + GPIO1_EDGE_LOW: u1, + GPIO1_EDGE_HIGH: u1, + GPIO2_LEVEL_LOW: u1, + GPIO2_LEVEL_HIGH: u1, + GPIO2_EDGE_LOW: u1, + GPIO2_EDGE_HIGH: u1, + GPIO3_LEVEL_LOW: u1, + GPIO3_LEVEL_HIGH: u1, + GPIO3_EDGE_LOW: u1, + GPIO3_EDGE_HIGH: u1, + GPIO4_LEVEL_LOW: u1, + GPIO4_LEVEL_HIGH: u1, + GPIO4_EDGE_LOW: u1, + GPIO4_EDGE_HIGH: u1, + GPIO5_LEVEL_LOW: u1, + GPIO5_LEVEL_HIGH: u1, + GPIO5_EDGE_LOW: u1, + GPIO5_EDGE_HIGH: u1, + GPIO6_LEVEL_LOW: u1, + GPIO6_LEVEL_HIGH: u1, + GPIO6_EDGE_LOW: u1, + GPIO6_EDGE_HIGH: u1, + GPIO7_LEVEL_LOW: u1, + GPIO7_LEVEL_HIGH: u1, + GPIO7_EDGE_LOW: u1, + GPIO7_EDGE_HIGH: u1, + }), base_address + 0x110); + + /// address: 0x40014114 + /// Interrupt Force for proc0 + pub const PROC0_INTF1 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO8_LEVEL_LOW: u1, + GPIO8_LEVEL_HIGH: u1, + GPIO8_EDGE_LOW: u1, + GPIO8_EDGE_HIGH: u1, + GPIO9_LEVEL_LOW: u1, + GPIO9_LEVEL_HIGH: u1, + GPIO9_EDGE_LOW: u1, + GPIO9_EDGE_HIGH: u1, + GPIO10_LEVEL_LOW: u1, + GPIO10_LEVEL_HIGH: u1, + GPIO10_EDGE_LOW: u1, + GPIO10_EDGE_HIGH: u1, + GPIO11_LEVEL_LOW: u1, + GPIO11_LEVEL_HIGH: u1, + GPIO11_EDGE_LOW: u1, + GPIO11_EDGE_HIGH: u1, + GPIO12_LEVEL_LOW: u1, + GPIO12_LEVEL_HIGH: u1, + GPIO12_EDGE_LOW: u1, + GPIO12_EDGE_HIGH: u1, + GPIO13_LEVEL_LOW: u1, + GPIO13_LEVEL_HIGH: u1, + GPIO13_EDGE_LOW: u1, + GPIO13_EDGE_HIGH: u1, + GPIO14_LEVEL_LOW: u1, + GPIO14_LEVEL_HIGH: u1, + GPIO14_EDGE_LOW: u1, + GPIO14_EDGE_HIGH: u1, + GPIO15_LEVEL_LOW: u1, + GPIO15_LEVEL_HIGH: u1, + GPIO15_EDGE_LOW: u1, + GPIO15_EDGE_HIGH: u1, + }), base_address + 0x114); + + /// address: 0x40014118 + /// Interrupt Force for proc0 + pub const PROC0_INTF2 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO16_LEVEL_LOW: u1, + GPIO16_LEVEL_HIGH: u1, + GPIO16_EDGE_LOW: u1, + GPIO16_EDGE_HIGH: u1, + GPIO17_LEVEL_LOW: u1, + GPIO17_LEVEL_HIGH: u1, + GPIO17_EDGE_LOW: u1, + GPIO17_EDGE_HIGH: u1, + GPIO18_LEVEL_LOW: u1, + GPIO18_LEVEL_HIGH: u1, + GPIO18_EDGE_LOW: u1, + GPIO18_EDGE_HIGH: u1, + GPIO19_LEVEL_LOW: u1, + GPIO19_LEVEL_HIGH: u1, + GPIO19_EDGE_LOW: u1, + GPIO19_EDGE_HIGH: u1, + GPIO20_LEVEL_LOW: u1, + GPIO20_LEVEL_HIGH: u1, + GPIO20_EDGE_LOW: u1, + GPIO20_EDGE_HIGH: u1, + GPIO21_LEVEL_LOW: u1, + GPIO21_LEVEL_HIGH: u1, + GPIO21_EDGE_LOW: u1, + GPIO21_EDGE_HIGH: u1, + GPIO22_LEVEL_LOW: u1, + GPIO22_LEVEL_HIGH: u1, + GPIO22_EDGE_LOW: u1, + GPIO22_EDGE_HIGH: u1, + GPIO23_LEVEL_LOW: u1, + GPIO23_LEVEL_HIGH: u1, + GPIO23_EDGE_LOW: u1, + GPIO23_EDGE_HIGH: u1, + }), base_address + 0x118); + + /// address: 0x4001411c + /// Interrupt Force for proc0 + pub const PROC0_INTF3 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO24_LEVEL_LOW: u1, + GPIO24_LEVEL_HIGH: u1, + GPIO24_EDGE_LOW: u1, + GPIO24_EDGE_HIGH: u1, + GPIO25_LEVEL_LOW: u1, + GPIO25_LEVEL_HIGH: u1, + GPIO25_EDGE_LOW: u1, + GPIO25_EDGE_HIGH: u1, + GPIO26_LEVEL_LOW: u1, + GPIO26_LEVEL_HIGH: u1, + GPIO26_EDGE_LOW: u1, + GPIO26_EDGE_HIGH: u1, + GPIO27_LEVEL_LOW: u1, + GPIO27_LEVEL_HIGH: u1, + GPIO27_EDGE_LOW: u1, + GPIO27_EDGE_HIGH: u1, + GPIO28_LEVEL_LOW: u1, + GPIO28_LEVEL_HIGH: u1, + GPIO28_EDGE_LOW: u1, + GPIO28_EDGE_HIGH: u1, + GPIO29_LEVEL_LOW: u1, + GPIO29_LEVEL_HIGH: u1, + GPIO29_EDGE_LOW: u1, + GPIO29_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x11c); + + /// address: 0x40014120 + /// Interrupt status after masking & forcing for proc0 + pub const PROC0_INTS0 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO0_LEVEL_LOW: u1, + GPIO0_LEVEL_HIGH: u1, + GPIO0_EDGE_LOW: u1, + GPIO0_EDGE_HIGH: u1, + GPIO1_LEVEL_LOW: u1, + GPIO1_LEVEL_HIGH: u1, + GPIO1_EDGE_LOW: u1, + GPIO1_EDGE_HIGH: u1, + GPIO2_LEVEL_LOW: u1, + GPIO2_LEVEL_HIGH: u1, + GPIO2_EDGE_LOW: u1, + GPIO2_EDGE_HIGH: u1, + GPIO3_LEVEL_LOW: u1, + GPIO3_LEVEL_HIGH: u1, + GPIO3_EDGE_LOW: u1, + GPIO3_EDGE_HIGH: u1, + GPIO4_LEVEL_LOW: u1, + GPIO4_LEVEL_HIGH: u1, + GPIO4_EDGE_LOW: u1, + GPIO4_EDGE_HIGH: u1, + GPIO5_LEVEL_LOW: u1, + GPIO5_LEVEL_HIGH: u1, + GPIO5_EDGE_LOW: u1, + GPIO5_EDGE_HIGH: u1, + GPIO6_LEVEL_LOW: u1, + GPIO6_LEVEL_HIGH: u1, + GPIO6_EDGE_LOW: u1, + GPIO6_EDGE_HIGH: u1, + GPIO7_LEVEL_LOW: u1, + GPIO7_LEVEL_HIGH: u1, + GPIO7_EDGE_LOW: u1, + GPIO7_EDGE_HIGH: u1, + }), base_address + 0x120); + + /// address: 0x40014124 + /// Interrupt status after masking & forcing for proc0 + pub const PROC0_INTS1 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO8_LEVEL_LOW: u1, + GPIO8_LEVEL_HIGH: u1, + GPIO8_EDGE_LOW: u1, + GPIO8_EDGE_HIGH: u1, + GPIO9_LEVEL_LOW: u1, + GPIO9_LEVEL_HIGH: u1, + GPIO9_EDGE_LOW: u1, + GPIO9_EDGE_HIGH: u1, + GPIO10_LEVEL_LOW: u1, + GPIO10_LEVEL_HIGH: u1, + GPIO10_EDGE_LOW: u1, + GPIO10_EDGE_HIGH: u1, + GPIO11_LEVEL_LOW: u1, + GPIO11_LEVEL_HIGH: u1, + GPIO11_EDGE_LOW: u1, + GPIO11_EDGE_HIGH: u1, + GPIO12_LEVEL_LOW: u1, + GPIO12_LEVEL_HIGH: u1, + GPIO12_EDGE_LOW: u1, + GPIO12_EDGE_HIGH: u1, + GPIO13_LEVEL_LOW: u1, + GPIO13_LEVEL_HIGH: u1, + GPIO13_EDGE_LOW: u1, + GPIO13_EDGE_HIGH: u1, + GPIO14_LEVEL_LOW: u1, + GPIO14_LEVEL_HIGH: u1, + GPIO14_EDGE_LOW: u1, + GPIO14_EDGE_HIGH: u1, + GPIO15_LEVEL_LOW: u1, + GPIO15_LEVEL_HIGH: u1, + GPIO15_EDGE_LOW: u1, + GPIO15_EDGE_HIGH: u1, + }), base_address + 0x124); + + /// address: 0x40014128 + /// Interrupt status after masking & forcing for proc0 + pub const PROC0_INTS2 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO16_LEVEL_LOW: u1, + GPIO16_LEVEL_HIGH: u1, + GPIO16_EDGE_LOW: u1, + GPIO16_EDGE_HIGH: u1, + GPIO17_LEVEL_LOW: u1, + GPIO17_LEVEL_HIGH: u1, + GPIO17_EDGE_LOW: u1, + GPIO17_EDGE_HIGH: u1, + GPIO18_LEVEL_LOW: u1, + GPIO18_LEVEL_HIGH: u1, + GPIO18_EDGE_LOW: u1, + GPIO18_EDGE_HIGH: u1, + GPIO19_LEVEL_LOW: u1, + GPIO19_LEVEL_HIGH: u1, + GPIO19_EDGE_LOW: u1, + GPIO19_EDGE_HIGH: u1, + GPIO20_LEVEL_LOW: u1, + GPIO20_LEVEL_HIGH: u1, + GPIO20_EDGE_LOW: u1, + GPIO20_EDGE_HIGH: u1, + GPIO21_LEVEL_LOW: u1, + GPIO21_LEVEL_HIGH: u1, + GPIO21_EDGE_LOW: u1, + GPIO21_EDGE_HIGH: u1, + GPIO22_LEVEL_LOW: u1, + GPIO22_LEVEL_HIGH: u1, + GPIO22_EDGE_LOW: u1, + GPIO22_EDGE_HIGH: u1, + GPIO23_LEVEL_LOW: u1, + GPIO23_LEVEL_HIGH: u1, + GPIO23_EDGE_LOW: u1, + GPIO23_EDGE_HIGH: u1, + }), base_address + 0x128); + + /// address: 0x4001412c + /// Interrupt status after masking & forcing for proc0 + pub const PROC0_INTS3 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO24_LEVEL_LOW: u1, + GPIO24_LEVEL_HIGH: u1, + GPIO24_EDGE_LOW: u1, + GPIO24_EDGE_HIGH: u1, + GPIO25_LEVEL_LOW: u1, + GPIO25_LEVEL_HIGH: u1, + GPIO25_EDGE_LOW: u1, + GPIO25_EDGE_HIGH: u1, + GPIO26_LEVEL_LOW: u1, + GPIO26_LEVEL_HIGH: u1, + GPIO26_EDGE_LOW: u1, + GPIO26_EDGE_HIGH: u1, + GPIO27_LEVEL_LOW: u1, + GPIO27_LEVEL_HIGH: u1, + GPIO27_EDGE_LOW: u1, + GPIO27_EDGE_HIGH: u1, + GPIO28_LEVEL_LOW: u1, + GPIO28_LEVEL_HIGH: u1, + GPIO28_EDGE_LOW: u1, + GPIO28_EDGE_HIGH: u1, + GPIO29_LEVEL_LOW: u1, + GPIO29_LEVEL_HIGH: u1, + GPIO29_EDGE_LOW: u1, + GPIO29_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x12c); + + /// address: 0x40014130 + /// Interrupt Enable for proc1 + pub const PROC1_INTE0 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO0_LEVEL_LOW: u1, + GPIO0_LEVEL_HIGH: u1, + GPIO0_EDGE_LOW: u1, + GPIO0_EDGE_HIGH: u1, + GPIO1_LEVEL_LOW: u1, + GPIO1_LEVEL_HIGH: u1, + GPIO1_EDGE_LOW: u1, + GPIO1_EDGE_HIGH: u1, + GPIO2_LEVEL_LOW: u1, + GPIO2_LEVEL_HIGH: u1, + GPIO2_EDGE_LOW: u1, + GPIO2_EDGE_HIGH: u1, + GPIO3_LEVEL_LOW: u1, + GPIO3_LEVEL_HIGH: u1, + GPIO3_EDGE_LOW: u1, + GPIO3_EDGE_HIGH: u1, + GPIO4_LEVEL_LOW: u1, + GPIO4_LEVEL_HIGH: u1, + GPIO4_EDGE_LOW: u1, + GPIO4_EDGE_HIGH: u1, + GPIO5_LEVEL_LOW: u1, + GPIO5_LEVEL_HIGH: u1, + GPIO5_EDGE_LOW: u1, + GPIO5_EDGE_HIGH: u1, + GPIO6_LEVEL_LOW: u1, + GPIO6_LEVEL_HIGH: u1, + GPIO6_EDGE_LOW: u1, + GPIO6_EDGE_HIGH: u1, + GPIO7_LEVEL_LOW: u1, + GPIO7_LEVEL_HIGH: u1, + GPIO7_EDGE_LOW: u1, + GPIO7_EDGE_HIGH: u1, + }), base_address + 0x130); + + /// address: 0x40014134 + /// Interrupt Enable for proc1 + pub const PROC1_INTE1 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO8_LEVEL_LOW: u1, + GPIO8_LEVEL_HIGH: u1, + GPIO8_EDGE_LOW: u1, + GPIO8_EDGE_HIGH: u1, + GPIO9_LEVEL_LOW: u1, + GPIO9_LEVEL_HIGH: u1, + GPIO9_EDGE_LOW: u1, + GPIO9_EDGE_HIGH: u1, + GPIO10_LEVEL_LOW: u1, + GPIO10_LEVEL_HIGH: u1, + GPIO10_EDGE_LOW: u1, + GPIO10_EDGE_HIGH: u1, + GPIO11_LEVEL_LOW: u1, + GPIO11_LEVEL_HIGH: u1, + GPIO11_EDGE_LOW: u1, + GPIO11_EDGE_HIGH: u1, + GPIO12_LEVEL_LOW: u1, + GPIO12_LEVEL_HIGH: u1, + GPIO12_EDGE_LOW: u1, + GPIO12_EDGE_HIGH: u1, + GPIO13_LEVEL_LOW: u1, + GPIO13_LEVEL_HIGH: u1, + GPIO13_EDGE_LOW: u1, + GPIO13_EDGE_HIGH: u1, + GPIO14_LEVEL_LOW: u1, + GPIO14_LEVEL_HIGH: u1, + GPIO14_EDGE_LOW: u1, + GPIO14_EDGE_HIGH: u1, + GPIO15_LEVEL_LOW: u1, + GPIO15_LEVEL_HIGH: u1, + GPIO15_EDGE_LOW: u1, + GPIO15_EDGE_HIGH: u1, + }), base_address + 0x134); + + /// address: 0x40014138 + /// Interrupt Enable for proc1 + pub const PROC1_INTE2 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO16_LEVEL_LOW: u1, + GPIO16_LEVEL_HIGH: u1, + GPIO16_EDGE_LOW: u1, + GPIO16_EDGE_HIGH: u1, + GPIO17_LEVEL_LOW: u1, + GPIO17_LEVEL_HIGH: u1, + GPIO17_EDGE_LOW: u1, + GPIO17_EDGE_HIGH: u1, + GPIO18_LEVEL_LOW: u1, + GPIO18_LEVEL_HIGH: u1, + GPIO18_EDGE_LOW: u1, + GPIO18_EDGE_HIGH: u1, + GPIO19_LEVEL_LOW: u1, + GPIO19_LEVEL_HIGH: u1, + GPIO19_EDGE_LOW: u1, + GPIO19_EDGE_HIGH: u1, + GPIO20_LEVEL_LOW: u1, + GPIO20_LEVEL_HIGH: u1, + GPIO20_EDGE_LOW: u1, + GPIO20_EDGE_HIGH: u1, + GPIO21_LEVEL_LOW: u1, + GPIO21_LEVEL_HIGH: u1, + GPIO21_EDGE_LOW: u1, + GPIO21_EDGE_HIGH: u1, + GPIO22_LEVEL_LOW: u1, + GPIO22_LEVEL_HIGH: u1, + GPIO22_EDGE_LOW: u1, + GPIO22_EDGE_HIGH: u1, + GPIO23_LEVEL_LOW: u1, + GPIO23_LEVEL_HIGH: u1, + GPIO23_EDGE_LOW: u1, + GPIO23_EDGE_HIGH: u1, + }), base_address + 0x138); + + /// address: 0x4001413c + /// Interrupt Enable for proc1 + pub const PROC1_INTE3 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO24_LEVEL_LOW: u1, + GPIO24_LEVEL_HIGH: u1, + GPIO24_EDGE_LOW: u1, + GPIO24_EDGE_HIGH: u1, + GPIO25_LEVEL_LOW: u1, + GPIO25_LEVEL_HIGH: u1, + GPIO25_EDGE_LOW: u1, + GPIO25_EDGE_HIGH: u1, + GPIO26_LEVEL_LOW: u1, + GPIO26_LEVEL_HIGH: u1, + GPIO26_EDGE_LOW: u1, + GPIO26_EDGE_HIGH: u1, + GPIO27_LEVEL_LOW: u1, + GPIO27_LEVEL_HIGH: u1, + GPIO27_EDGE_LOW: u1, + GPIO27_EDGE_HIGH: u1, + GPIO28_LEVEL_LOW: u1, + GPIO28_LEVEL_HIGH: u1, + GPIO28_EDGE_LOW: u1, + GPIO28_EDGE_HIGH: u1, + GPIO29_LEVEL_LOW: u1, + GPIO29_LEVEL_HIGH: u1, + GPIO29_EDGE_LOW: u1, + GPIO29_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x13c); + + /// address: 0x40014140 + /// Interrupt Force for proc1 + pub const PROC1_INTF0 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO0_LEVEL_LOW: u1, + GPIO0_LEVEL_HIGH: u1, + GPIO0_EDGE_LOW: u1, + GPIO0_EDGE_HIGH: u1, + GPIO1_LEVEL_LOW: u1, + GPIO1_LEVEL_HIGH: u1, + GPIO1_EDGE_LOW: u1, + GPIO1_EDGE_HIGH: u1, + GPIO2_LEVEL_LOW: u1, + GPIO2_LEVEL_HIGH: u1, + GPIO2_EDGE_LOW: u1, + GPIO2_EDGE_HIGH: u1, + GPIO3_LEVEL_LOW: u1, + GPIO3_LEVEL_HIGH: u1, + GPIO3_EDGE_LOW: u1, + GPIO3_EDGE_HIGH: u1, + GPIO4_LEVEL_LOW: u1, + GPIO4_LEVEL_HIGH: u1, + GPIO4_EDGE_LOW: u1, + GPIO4_EDGE_HIGH: u1, + GPIO5_LEVEL_LOW: u1, + GPIO5_LEVEL_HIGH: u1, + GPIO5_EDGE_LOW: u1, + GPIO5_EDGE_HIGH: u1, + GPIO6_LEVEL_LOW: u1, + GPIO6_LEVEL_HIGH: u1, + GPIO6_EDGE_LOW: u1, + GPIO6_EDGE_HIGH: u1, + GPIO7_LEVEL_LOW: u1, + GPIO7_LEVEL_HIGH: u1, + GPIO7_EDGE_LOW: u1, + GPIO7_EDGE_HIGH: u1, + }), base_address + 0x140); + + /// address: 0x40014144 + /// Interrupt Force for proc1 + pub const PROC1_INTF1 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO8_LEVEL_LOW: u1, + GPIO8_LEVEL_HIGH: u1, + GPIO8_EDGE_LOW: u1, + GPIO8_EDGE_HIGH: u1, + GPIO9_LEVEL_LOW: u1, + GPIO9_LEVEL_HIGH: u1, + GPIO9_EDGE_LOW: u1, + GPIO9_EDGE_HIGH: u1, + GPIO10_LEVEL_LOW: u1, + GPIO10_LEVEL_HIGH: u1, + GPIO10_EDGE_LOW: u1, + GPIO10_EDGE_HIGH: u1, + GPIO11_LEVEL_LOW: u1, + GPIO11_LEVEL_HIGH: u1, + GPIO11_EDGE_LOW: u1, + GPIO11_EDGE_HIGH: u1, + GPIO12_LEVEL_LOW: u1, + GPIO12_LEVEL_HIGH: u1, + GPIO12_EDGE_LOW: u1, + GPIO12_EDGE_HIGH: u1, + GPIO13_LEVEL_LOW: u1, + GPIO13_LEVEL_HIGH: u1, + GPIO13_EDGE_LOW: u1, + GPIO13_EDGE_HIGH: u1, + GPIO14_LEVEL_LOW: u1, + GPIO14_LEVEL_HIGH: u1, + GPIO14_EDGE_LOW: u1, + GPIO14_EDGE_HIGH: u1, + GPIO15_LEVEL_LOW: u1, + GPIO15_LEVEL_HIGH: u1, + GPIO15_EDGE_LOW: u1, + GPIO15_EDGE_HIGH: u1, + }), base_address + 0x144); + + /// address: 0x40014148 + /// Interrupt Force for proc1 + pub const PROC1_INTF2 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO16_LEVEL_LOW: u1, + GPIO16_LEVEL_HIGH: u1, + GPIO16_EDGE_LOW: u1, + GPIO16_EDGE_HIGH: u1, + GPIO17_LEVEL_LOW: u1, + GPIO17_LEVEL_HIGH: u1, + GPIO17_EDGE_LOW: u1, + GPIO17_EDGE_HIGH: u1, + GPIO18_LEVEL_LOW: u1, + GPIO18_LEVEL_HIGH: u1, + GPIO18_EDGE_LOW: u1, + GPIO18_EDGE_HIGH: u1, + GPIO19_LEVEL_LOW: u1, + GPIO19_LEVEL_HIGH: u1, + GPIO19_EDGE_LOW: u1, + GPIO19_EDGE_HIGH: u1, + GPIO20_LEVEL_LOW: u1, + GPIO20_LEVEL_HIGH: u1, + GPIO20_EDGE_LOW: u1, + GPIO20_EDGE_HIGH: u1, + GPIO21_LEVEL_LOW: u1, + GPIO21_LEVEL_HIGH: u1, + GPIO21_EDGE_LOW: u1, + GPIO21_EDGE_HIGH: u1, + GPIO22_LEVEL_LOW: u1, + GPIO22_LEVEL_HIGH: u1, + GPIO22_EDGE_LOW: u1, + GPIO22_EDGE_HIGH: u1, + GPIO23_LEVEL_LOW: u1, + GPIO23_LEVEL_HIGH: u1, + GPIO23_EDGE_LOW: u1, + GPIO23_EDGE_HIGH: u1, + }), base_address + 0x148); + + /// address: 0x4001414c + /// Interrupt Force for proc1 + pub const PROC1_INTF3 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO24_LEVEL_LOW: u1, + GPIO24_LEVEL_HIGH: u1, + GPIO24_EDGE_LOW: u1, + GPIO24_EDGE_HIGH: u1, + GPIO25_LEVEL_LOW: u1, + GPIO25_LEVEL_HIGH: u1, + GPIO25_EDGE_LOW: u1, + GPIO25_EDGE_HIGH: u1, + GPIO26_LEVEL_LOW: u1, + GPIO26_LEVEL_HIGH: u1, + GPIO26_EDGE_LOW: u1, + GPIO26_EDGE_HIGH: u1, + GPIO27_LEVEL_LOW: u1, + GPIO27_LEVEL_HIGH: u1, + GPIO27_EDGE_LOW: u1, + GPIO27_EDGE_HIGH: u1, + GPIO28_LEVEL_LOW: u1, + GPIO28_LEVEL_HIGH: u1, + GPIO28_EDGE_LOW: u1, + GPIO28_EDGE_HIGH: u1, + GPIO29_LEVEL_LOW: u1, + GPIO29_LEVEL_HIGH: u1, + GPIO29_EDGE_LOW: u1, + GPIO29_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x14c); + + /// address: 0x40014150 + /// Interrupt status after masking & forcing for proc1 + pub const PROC1_INTS0 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO0_LEVEL_LOW: u1, + GPIO0_LEVEL_HIGH: u1, + GPIO0_EDGE_LOW: u1, + GPIO0_EDGE_HIGH: u1, + GPIO1_LEVEL_LOW: u1, + GPIO1_LEVEL_HIGH: u1, + GPIO1_EDGE_LOW: u1, + GPIO1_EDGE_HIGH: u1, + GPIO2_LEVEL_LOW: u1, + GPIO2_LEVEL_HIGH: u1, + GPIO2_EDGE_LOW: u1, + GPIO2_EDGE_HIGH: u1, + GPIO3_LEVEL_LOW: u1, + GPIO3_LEVEL_HIGH: u1, + GPIO3_EDGE_LOW: u1, + GPIO3_EDGE_HIGH: u1, + GPIO4_LEVEL_LOW: u1, + GPIO4_LEVEL_HIGH: u1, + GPIO4_EDGE_LOW: u1, + GPIO4_EDGE_HIGH: u1, + GPIO5_LEVEL_LOW: u1, + GPIO5_LEVEL_HIGH: u1, + GPIO5_EDGE_LOW: u1, + GPIO5_EDGE_HIGH: u1, + GPIO6_LEVEL_LOW: u1, + GPIO6_LEVEL_HIGH: u1, + GPIO6_EDGE_LOW: u1, + GPIO6_EDGE_HIGH: u1, + GPIO7_LEVEL_LOW: u1, + GPIO7_LEVEL_HIGH: u1, + GPIO7_EDGE_LOW: u1, + GPIO7_EDGE_HIGH: u1, + }), base_address + 0x150); + + /// address: 0x40014154 + /// Interrupt status after masking & forcing for proc1 + pub const PROC1_INTS1 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO8_LEVEL_LOW: u1, + GPIO8_LEVEL_HIGH: u1, + GPIO8_EDGE_LOW: u1, + GPIO8_EDGE_HIGH: u1, + GPIO9_LEVEL_LOW: u1, + GPIO9_LEVEL_HIGH: u1, + GPIO9_EDGE_LOW: u1, + GPIO9_EDGE_HIGH: u1, + GPIO10_LEVEL_LOW: u1, + GPIO10_LEVEL_HIGH: u1, + GPIO10_EDGE_LOW: u1, + GPIO10_EDGE_HIGH: u1, + GPIO11_LEVEL_LOW: u1, + GPIO11_LEVEL_HIGH: u1, + GPIO11_EDGE_LOW: u1, + GPIO11_EDGE_HIGH: u1, + GPIO12_LEVEL_LOW: u1, + GPIO12_LEVEL_HIGH: u1, + GPIO12_EDGE_LOW: u1, + GPIO12_EDGE_HIGH: u1, + GPIO13_LEVEL_LOW: u1, + GPIO13_LEVEL_HIGH: u1, + GPIO13_EDGE_LOW: u1, + GPIO13_EDGE_HIGH: u1, + GPIO14_LEVEL_LOW: u1, + GPIO14_LEVEL_HIGH: u1, + GPIO14_EDGE_LOW: u1, + GPIO14_EDGE_HIGH: u1, + GPIO15_LEVEL_LOW: u1, + GPIO15_LEVEL_HIGH: u1, + GPIO15_EDGE_LOW: u1, + GPIO15_EDGE_HIGH: u1, + }), base_address + 0x154); + + /// address: 0x40014158 + /// Interrupt status after masking & forcing for proc1 + pub const PROC1_INTS2 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO16_LEVEL_LOW: u1, + GPIO16_LEVEL_HIGH: u1, + GPIO16_EDGE_LOW: u1, + GPIO16_EDGE_HIGH: u1, + GPIO17_LEVEL_LOW: u1, + GPIO17_LEVEL_HIGH: u1, + GPIO17_EDGE_LOW: u1, + GPIO17_EDGE_HIGH: u1, + GPIO18_LEVEL_LOW: u1, + GPIO18_LEVEL_HIGH: u1, + GPIO18_EDGE_LOW: u1, + GPIO18_EDGE_HIGH: u1, + GPIO19_LEVEL_LOW: u1, + GPIO19_LEVEL_HIGH: u1, + GPIO19_EDGE_LOW: u1, + GPIO19_EDGE_HIGH: u1, + GPIO20_LEVEL_LOW: u1, + GPIO20_LEVEL_HIGH: u1, + GPIO20_EDGE_LOW: u1, + GPIO20_EDGE_HIGH: u1, + GPIO21_LEVEL_LOW: u1, + GPIO21_LEVEL_HIGH: u1, + GPIO21_EDGE_LOW: u1, + GPIO21_EDGE_HIGH: u1, + GPIO22_LEVEL_LOW: u1, + GPIO22_LEVEL_HIGH: u1, + GPIO22_EDGE_LOW: u1, + GPIO22_EDGE_HIGH: u1, + GPIO23_LEVEL_LOW: u1, + GPIO23_LEVEL_HIGH: u1, + GPIO23_EDGE_LOW: u1, + GPIO23_EDGE_HIGH: u1, + }), base_address + 0x158); + + /// address: 0x4001415c + /// Interrupt status after masking & forcing for proc1 + pub const PROC1_INTS3 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO24_LEVEL_LOW: u1, + GPIO24_LEVEL_HIGH: u1, + GPIO24_EDGE_LOW: u1, + GPIO24_EDGE_HIGH: u1, + GPIO25_LEVEL_LOW: u1, + GPIO25_LEVEL_HIGH: u1, + GPIO25_EDGE_LOW: u1, + GPIO25_EDGE_HIGH: u1, + GPIO26_LEVEL_LOW: u1, + GPIO26_LEVEL_HIGH: u1, + GPIO26_EDGE_LOW: u1, + GPIO26_EDGE_HIGH: u1, + GPIO27_LEVEL_LOW: u1, + GPIO27_LEVEL_HIGH: u1, + GPIO27_EDGE_LOW: u1, + GPIO27_EDGE_HIGH: u1, + GPIO28_LEVEL_LOW: u1, + GPIO28_LEVEL_HIGH: u1, + GPIO28_EDGE_LOW: u1, + GPIO28_EDGE_HIGH: u1, + GPIO29_LEVEL_LOW: u1, + GPIO29_LEVEL_HIGH: u1, + GPIO29_EDGE_LOW: u1, + GPIO29_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x15c); + + /// address: 0x40014160 + /// Interrupt Enable for dormant_wake + pub const DORMANT_WAKE_INTE0 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO0_LEVEL_LOW: u1, + GPIO0_LEVEL_HIGH: u1, + GPIO0_EDGE_LOW: u1, + GPIO0_EDGE_HIGH: u1, + GPIO1_LEVEL_LOW: u1, + GPIO1_LEVEL_HIGH: u1, + GPIO1_EDGE_LOW: u1, + GPIO1_EDGE_HIGH: u1, + GPIO2_LEVEL_LOW: u1, + GPIO2_LEVEL_HIGH: u1, + GPIO2_EDGE_LOW: u1, + GPIO2_EDGE_HIGH: u1, + GPIO3_LEVEL_LOW: u1, + GPIO3_LEVEL_HIGH: u1, + GPIO3_EDGE_LOW: u1, + GPIO3_EDGE_HIGH: u1, + GPIO4_LEVEL_LOW: u1, + GPIO4_LEVEL_HIGH: u1, + GPIO4_EDGE_LOW: u1, + GPIO4_EDGE_HIGH: u1, + GPIO5_LEVEL_LOW: u1, + GPIO5_LEVEL_HIGH: u1, + GPIO5_EDGE_LOW: u1, + GPIO5_EDGE_HIGH: u1, + GPIO6_LEVEL_LOW: u1, + GPIO6_LEVEL_HIGH: u1, + GPIO6_EDGE_LOW: u1, + GPIO6_EDGE_HIGH: u1, + GPIO7_LEVEL_LOW: u1, + GPIO7_LEVEL_HIGH: u1, + GPIO7_EDGE_LOW: u1, + GPIO7_EDGE_HIGH: u1, + }), base_address + 0x160); + + /// address: 0x40014164 + /// Interrupt Enable for dormant_wake + pub const DORMANT_WAKE_INTE1 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO8_LEVEL_LOW: u1, + GPIO8_LEVEL_HIGH: u1, + GPIO8_EDGE_LOW: u1, + GPIO8_EDGE_HIGH: u1, + GPIO9_LEVEL_LOW: u1, + GPIO9_LEVEL_HIGH: u1, + GPIO9_EDGE_LOW: u1, + GPIO9_EDGE_HIGH: u1, + GPIO10_LEVEL_LOW: u1, + GPIO10_LEVEL_HIGH: u1, + GPIO10_EDGE_LOW: u1, + GPIO10_EDGE_HIGH: u1, + GPIO11_LEVEL_LOW: u1, + GPIO11_LEVEL_HIGH: u1, + GPIO11_EDGE_LOW: u1, + GPIO11_EDGE_HIGH: u1, + GPIO12_LEVEL_LOW: u1, + GPIO12_LEVEL_HIGH: u1, + GPIO12_EDGE_LOW: u1, + GPIO12_EDGE_HIGH: u1, + GPIO13_LEVEL_LOW: u1, + GPIO13_LEVEL_HIGH: u1, + GPIO13_EDGE_LOW: u1, + GPIO13_EDGE_HIGH: u1, + GPIO14_LEVEL_LOW: u1, + GPIO14_LEVEL_HIGH: u1, + GPIO14_EDGE_LOW: u1, + GPIO14_EDGE_HIGH: u1, + GPIO15_LEVEL_LOW: u1, + GPIO15_LEVEL_HIGH: u1, + GPIO15_EDGE_LOW: u1, + GPIO15_EDGE_HIGH: u1, + }), base_address + 0x164); + + /// address: 0x40014168 + /// Interrupt Enable for dormant_wake + pub const DORMANT_WAKE_INTE2 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO16_LEVEL_LOW: u1, + GPIO16_LEVEL_HIGH: u1, + GPIO16_EDGE_LOW: u1, + GPIO16_EDGE_HIGH: u1, + GPIO17_LEVEL_LOW: u1, + GPIO17_LEVEL_HIGH: u1, + GPIO17_EDGE_LOW: u1, + GPIO17_EDGE_HIGH: u1, + GPIO18_LEVEL_LOW: u1, + GPIO18_LEVEL_HIGH: u1, + GPIO18_EDGE_LOW: u1, + GPIO18_EDGE_HIGH: u1, + GPIO19_LEVEL_LOW: u1, + GPIO19_LEVEL_HIGH: u1, + GPIO19_EDGE_LOW: u1, + GPIO19_EDGE_HIGH: u1, + GPIO20_LEVEL_LOW: u1, + GPIO20_LEVEL_HIGH: u1, + GPIO20_EDGE_LOW: u1, + GPIO20_EDGE_HIGH: u1, + GPIO21_LEVEL_LOW: u1, + GPIO21_LEVEL_HIGH: u1, + GPIO21_EDGE_LOW: u1, + GPIO21_EDGE_HIGH: u1, + GPIO22_LEVEL_LOW: u1, + GPIO22_LEVEL_HIGH: u1, + GPIO22_EDGE_LOW: u1, + GPIO22_EDGE_HIGH: u1, + GPIO23_LEVEL_LOW: u1, + GPIO23_LEVEL_HIGH: u1, + GPIO23_EDGE_LOW: u1, + GPIO23_EDGE_HIGH: u1, + }), base_address + 0x168); + + /// address: 0x4001416c + /// Interrupt Enable for dormant_wake + pub const DORMANT_WAKE_INTE3 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO24_LEVEL_LOW: u1, + GPIO24_LEVEL_HIGH: u1, + GPIO24_EDGE_LOW: u1, + GPIO24_EDGE_HIGH: u1, + GPIO25_LEVEL_LOW: u1, + GPIO25_LEVEL_HIGH: u1, + GPIO25_EDGE_LOW: u1, + GPIO25_EDGE_HIGH: u1, + GPIO26_LEVEL_LOW: u1, + GPIO26_LEVEL_HIGH: u1, + GPIO26_EDGE_LOW: u1, + GPIO26_EDGE_HIGH: u1, + GPIO27_LEVEL_LOW: u1, + GPIO27_LEVEL_HIGH: u1, + GPIO27_EDGE_LOW: u1, + GPIO27_EDGE_HIGH: u1, + GPIO28_LEVEL_LOW: u1, + GPIO28_LEVEL_HIGH: u1, + GPIO28_EDGE_LOW: u1, + GPIO28_EDGE_HIGH: u1, + GPIO29_LEVEL_LOW: u1, + GPIO29_LEVEL_HIGH: u1, + GPIO29_EDGE_LOW: u1, + GPIO29_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x16c); + + /// address: 0x40014170 + /// Interrupt Force for dormant_wake + pub const DORMANT_WAKE_INTF0 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO0_LEVEL_LOW: u1, + GPIO0_LEVEL_HIGH: u1, + GPIO0_EDGE_LOW: u1, + GPIO0_EDGE_HIGH: u1, + GPIO1_LEVEL_LOW: u1, + GPIO1_LEVEL_HIGH: u1, + GPIO1_EDGE_LOW: u1, + GPIO1_EDGE_HIGH: u1, + GPIO2_LEVEL_LOW: u1, + GPIO2_LEVEL_HIGH: u1, + GPIO2_EDGE_LOW: u1, + GPIO2_EDGE_HIGH: u1, + GPIO3_LEVEL_LOW: u1, + GPIO3_LEVEL_HIGH: u1, + GPIO3_EDGE_LOW: u1, + GPIO3_EDGE_HIGH: u1, + GPIO4_LEVEL_LOW: u1, + GPIO4_LEVEL_HIGH: u1, + GPIO4_EDGE_LOW: u1, + GPIO4_EDGE_HIGH: u1, + GPIO5_LEVEL_LOW: u1, + GPIO5_LEVEL_HIGH: u1, + GPIO5_EDGE_LOW: u1, + GPIO5_EDGE_HIGH: u1, + GPIO6_LEVEL_LOW: u1, + GPIO6_LEVEL_HIGH: u1, + GPIO6_EDGE_LOW: u1, + GPIO6_EDGE_HIGH: u1, + GPIO7_LEVEL_LOW: u1, + GPIO7_LEVEL_HIGH: u1, + GPIO7_EDGE_LOW: u1, + GPIO7_EDGE_HIGH: u1, + }), base_address + 0x170); + + /// address: 0x40014174 + /// Interrupt Force for dormant_wake + pub const DORMANT_WAKE_INTF1 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO8_LEVEL_LOW: u1, + GPIO8_LEVEL_HIGH: u1, + GPIO8_EDGE_LOW: u1, + GPIO8_EDGE_HIGH: u1, + GPIO9_LEVEL_LOW: u1, + GPIO9_LEVEL_HIGH: u1, + GPIO9_EDGE_LOW: u1, + GPIO9_EDGE_HIGH: u1, + GPIO10_LEVEL_LOW: u1, + GPIO10_LEVEL_HIGH: u1, + GPIO10_EDGE_LOW: u1, + GPIO10_EDGE_HIGH: u1, + GPIO11_LEVEL_LOW: u1, + GPIO11_LEVEL_HIGH: u1, + GPIO11_EDGE_LOW: u1, + GPIO11_EDGE_HIGH: u1, + GPIO12_LEVEL_LOW: u1, + GPIO12_LEVEL_HIGH: u1, + GPIO12_EDGE_LOW: u1, + GPIO12_EDGE_HIGH: u1, + GPIO13_LEVEL_LOW: u1, + GPIO13_LEVEL_HIGH: u1, + GPIO13_EDGE_LOW: u1, + GPIO13_EDGE_HIGH: u1, + GPIO14_LEVEL_LOW: u1, + GPIO14_LEVEL_HIGH: u1, + GPIO14_EDGE_LOW: u1, + GPIO14_EDGE_HIGH: u1, + GPIO15_LEVEL_LOW: u1, + GPIO15_LEVEL_HIGH: u1, + GPIO15_EDGE_LOW: u1, + GPIO15_EDGE_HIGH: u1, + }), base_address + 0x174); + + /// address: 0x40014178 + /// Interrupt Force for dormant_wake + pub const DORMANT_WAKE_INTF2 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO16_LEVEL_LOW: u1, + GPIO16_LEVEL_HIGH: u1, + GPIO16_EDGE_LOW: u1, + GPIO16_EDGE_HIGH: u1, + GPIO17_LEVEL_LOW: u1, + GPIO17_LEVEL_HIGH: u1, + GPIO17_EDGE_LOW: u1, + GPIO17_EDGE_HIGH: u1, + GPIO18_LEVEL_LOW: u1, + GPIO18_LEVEL_HIGH: u1, + GPIO18_EDGE_LOW: u1, + GPIO18_EDGE_HIGH: u1, + GPIO19_LEVEL_LOW: u1, + GPIO19_LEVEL_HIGH: u1, + GPIO19_EDGE_LOW: u1, + GPIO19_EDGE_HIGH: u1, + GPIO20_LEVEL_LOW: u1, + GPIO20_LEVEL_HIGH: u1, + GPIO20_EDGE_LOW: u1, + GPIO20_EDGE_HIGH: u1, + GPIO21_LEVEL_LOW: u1, + GPIO21_LEVEL_HIGH: u1, + GPIO21_EDGE_LOW: u1, + GPIO21_EDGE_HIGH: u1, + GPIO22_LEVEL_LOW: u1, + GPIO22_LEVEL_HIGH: u1, + GPIO22_EDGE_LOW: u1, + GPIO22_EDGE_HIGH: u1, + GPIO23_LEVEL_LOW: u1, + GPIO23_LEVEL_HIGH: u1, + GPIO23_EDGE_LOW: u1, + GPIO23_EDGE_HIGH: u1, + }), base_address + 0x178); + + /// address: 0x4001417c + /// Interrupt Force for dormant_wake + pub const DORMANT_WAKE_INTF3 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO24_LEVEL_LOW: u1, + GPIO24_LEVEL_HIGH: u1, + GPIO24_EDGE_LOW: u1, + GPIO24_EDGE_HIGH: u1, + GPIO25_LEVEL_LOW: u1, + GPIO25_LEVEL_HIGH: u1, + GPIO25_EDGE_LOW: u1, + GPIO25_EDGE_HIGH: u1, + GPIO26_LEVEL_LOW: u1, + GPIO26_LEVEL_HIGH: u1, + GPIO26_EDGE_LOW: u1, + GPIO26_EDGE_HIGH: u1, + GPIO27_LEVEL_LOW: u1, + GPIO27_LEVEL_HIGH: u1, + GPIO27_EDGE_LOW: u1, + GPIO27_EDGE_HIGH: u1, + GPIO28_LEVEL_LOW: u1, + GPIO28_LEVEL_HIGH: u1, + GPIO28_EDGE_LOW: u1, + GPIO28_EDGE_HIGH: u1, + GPIO29_LEVEL_LOW: u1, + GPIO29_LEVEL_HIGH: u1, + GPIO29_EDGE_LOW: u1, + GPIO29_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x17c); + + /// address: 0x40014180 + /// Interrupt status after masking & forcing for dormant_wake + pub const DORMANT_WAKE_INTS0 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO0_LEVEL_LOW: u1, + GPIO0_LEVEL_HIGH: u1, + GPIO0_EDGE_LOW: u1, + GPIO0_EDGE_HIGH: u1, + GPIO1_LEVEL_LOW: u1, + GPIO1_LEVEL_HIGH: u1, + GPIO1_EDGE_LOW: u1, + GPIO1_EDGE_HIGH: u1, + GPIO2_LEVEL_LOW: u1, + GPIO2_LEVEL_HIGH: u1, + GPIO2_EDGE_LOW: u1, + GPIO2_EDGE_HIGH: u1, + GPIO3_LEVEL_LOW: u1, + GPIO3_LEVEL_HIGH: u1, + GPIO3_EDGE_LOW: u1, + GPIO3_EDGE_HIGH: u1, + GPIO4_LEVEL_LOW: u1, + GPIO4_LEVEL_HIGH: u1, + GPIO4_EDGE_LOW: u1, + GPIO4_EDGE_HIGH: u1, + GPIO5_LEVEL_LOW: u1, + GPIO5_LEVEL_HIGH: u1, + GPIO5_EDGE_LOW: u1, + GPIO5_EDGE_HIGH: u1, + GPIO6_LEVEL_LOW: u1, + GPIO6_LEVEL_HIGH: u1, + GPIO6_EDGE_LOW: u1, + GPIO6_EDGE_HIGH: u1, + GPIO7_LEVEL_LOW: u1, + GPIO7_LEVEL_HIGH: u1, + GPIO7_EDGE_LOW: u1, + GPIO7_EDGE_HIGH: u1, + }), base_address + 0x180); + + /// address: 0x40014184 + /// Interrupt status after masking & forcing for dormant_wake + pub const DORMANT_WAKE_INTS1 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO8_LEVEL_LOW: u1, + GPIO8_LEVEL_HIGH: u1, + GPIO8_EDGE_LOW: u1, + GPIO8_EDGE_HIGH: u1, + GPIO9_LEVEL_LOW: u1, + GPIO9_LEVEL_HIGH: u1, + GPIO9_EDGE_LOW: u1, + GPIO9_EDGE_HIGH: u1, + GPIO10_LEVEL_LOW: u1, + GPIO10_LEVEL_HIGH: u1, + GPIO10_EDGE_LOW: u1, + GPIO10_EDGE_HIGH: u1, + GPIO11_LEVEL_LOW: u1, + GPIO11_LEVEL_HIGH: u1, + GPIO11_EDGE_LOW: u1, + GPIO11_EDGE_HIGH: u1, + GPIO12_LEVEL_LOW: u1, + GPIO12_LEVEL_HIGH: u1, + GPIO12_EDGE_LOW: u1, + GPIO12_EDGE_HIGH: u1, + GPIO13_LEVEL_LOW: u1, + GPIO13_LEVEL_HIGH: u1, + GPIO13_EDGE_LOW: u1, + GPIO13_EDGE_HIGH: u1, + GPIO14_LEVEL_LOW: u1, + GPIO14_LEVEL_HIGH: u1, + GPIO14_EDGE_LOW: u1, + GPIO14_EDGE_HIGH: u1, + GPIO15_LEVEL_LOW: u1, + GPIO15_LEVEL_HIGH: u1, + GPIO15_EDGE_LOW: u1, + GPIO15_EDGE_HIGH: u1, + }), base_address + 0x184); + + /// address: 0x40014188 + /// Interrupt status after masking & forcing for dormant_wake + pub const DORMANT_WAKE_INTS2 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO16_LEVEL_LOW: u1, + GPIO16_LEVEL_HIGH: u1, + GPIO16_EDGE_LOW: u1, + GPIO16_EDGE_HIGH: u1, + GPIO17_LEVEL_LOW: u1, + GPIO17_LEVEL_HIGH: u1, + GPIO17_EDGE_LOW: u1, + GPIO17_EDGE_HIGH: u1, + GPIO18_LEVEL_LOW: u1, + GPIO18_LEVEL_HIGH: u1, + GPIO18_EDGE_LOW: u1, + GPIO18_EDGE_HIGH: u1, + GPIO19_LEVEL_LOW: u1, + GPIO19_LEVEL_HIGH: u1, + GPIO19_EDGE_LOW: u1, + GPIO19_EDGE_HIGH: u1, + GPIO20_LEVEL_LOW: u1, + GPIO20_LEVEL_HIGH: u1, + GPIO20_EDGE_LOW: u1, + GPIO20_EDGE_HIGH: u1, + GPIO21_LEVEL_LOW: u1, + GPIO21_LEVEL_HIGH: u1, + GPIO21_EDGE_LOW: u1, + GPIO21_EDGE_HIGH: u1, + GPIO22_LEVEL_LOW: u1, + GPIO22_LEVEL_HIGH: u1, + GPIO22_EDGE_LOW: u1, + GPIO22_EDGE_HIGH: u1, + GPIO23_LEVEL_LOW: u1, + GPIO23_LEVEL_HIGH: u1, + GPIO23_EDGE_LOW: u1, + GPIO23_EDGE_HIGH: u1, + }), base_address + 0x188); + + /// address: 0x4001418c + /// Interrupt status after masking & forcing for dormant_wake + pub const DORMANT_WAKE_INTS3 = @intToPtr(*volatile Mmio(32, packed struct { + GPIO24_LEVEL_LOW: u1, + GPIO24_LEVEL_HIGH: u1, + GPIO24_EDGE_LOW: u1, + GPIO24_EDGE_HIGH: u1, + GPIO25_LEVEL_LOW: u1, + GPIO25_LEVEL_HIGH: u1, + GPIO25_EDGE_LOW: u1, + GPIO25_EDGE_HIGH: u1, + GPIO26_LEVEL_LOW: u1, + GPIO26_LEVEL_HIGH: u1, + GPIO26_EDGE_LOW: u1, + GPIO26_EDGE_HIGH: u1, + GPIO27_LEVEL_LOW: u1, + GPIO27_LEVEL_HIGH: u1, + GPIO27_EDGE_LOW: u1, + GPIO27_EDGE_HIGH: u1, + GPIO28_LEVEL_LOW: u1, + GPIO28_LEVEL_HIGH: u1, + GPIO28_EDGE_LOW: u1, + GPIO28_EDGE_HIGH: u1, + GPIO29_LEVEL_LOW: u1, + GPIO29_LEVEL_HIGH: u1, + GPIO29_EDGE_LOW: u1, + GPIO29_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x18c); + }; + pub const IO_QSPI = struct { + pub const base_address = 0x40018000; + pub const version = "1"; + + /// address: 0x40018000 + /// GPIO status + pub const GPIO_QSPI_SCLK_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40018004 + /// GPIO control including function select and overrides. + pub const GPIO_QSPI_SCLK_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40018008 + /// GPIO status + pub const GPIO_QSPI_SS_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x8); + + /// address: 0x4001800c + /// GPIO control including function select and overrides. + pub const GPIO_QSPI_SS_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0xc); + + /// address: 0x40018010 + /// GPIO status + pub const GPIO_QSPI_SD0_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x10); + + /// address: 0x40018014 + /// GPIO control including function select and overrides. + pub const GPIO_QSPI_SD0_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x14); + + /// address: 0x40018018 + /// GPIO status + pub const GPIO_QSPI_SD1_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x18); + + /// address: 0x4001801c + /// GPIO control including function select and overrides. + pub const GPIO_QSPI_SD1_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x1c); + + /// address: 0x40018020 + /// GPIO status + pub const GPIO_QSPI_SD2_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x20); + + /// address: 0x40018024 + /// GPIO control including function select and overrides. + pub const GPIO_QSPI_SD2_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x24); + + /// address: 0x40018028 + /// GPIO status + pub const GPIO_QSPI_SD3_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// output signal from selected peripheral, before register override is applied + OUTFROMPERI: u1, + /// output signal to pad after register override is applied + OUTTOPAD: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// output enable from selected peripheral, before register override is applied + OEFROMPERI: u1, + /// output enable to pad after register override is applied + OETOPAD: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// input signal from pad, before override is applied + INFROMPAD: u1, + reserved13: u1 = 0, + /// input signal to peripheral, after override is applied + INTOPERI: u1, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// interrupt from pad before override is applied + IRQFROMPAD: u1, + reserved18: u1 = 0, + /// interrupt to processors, after override is applied + IRQTOPROC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x28); + + /// address: 0x4001802c + /// GPIO control including function select and overrides. + pub const GPIO_QSPI_SD3_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// 0-31 -> selects pin function according to the gpio table\n + /// 31 == NULL + FUNCSEL: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + OUTOVER: u2, + reserved3: u1 = 0, + reserved4: u1 = 0, + OEOVER: u2, + reserved5: u1 = 0, + reserved6: u1 = 0, + INOVER: u2, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + IRQOVER: u2, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x2c); + + /// address: 0x40018030 + /// Raw Interrupts + pub const INTR = @intToPtr(*volatile Mmio(32, packed struct { + GPIO_QSPI_SCLK_LEVEL_LOW: u1, + GPIO_QSPI_SCLK_LEVEL_HIGH: u1, + GPIO_QSPI_SCLK_EDGE_LOW: u1, + GPIO_QSPI_SCLK_EDGE_HIGH: u1, + GPIO_QSPI_SS_LEVEL_LOW: u1, + GPIO_QSPI_SS_LEVEL_HIGH: u1, + GPIO_QSPI_SS_EDGE_LOW: u1, + GPIO_QSPI_SS_EDGE_HIGH: u1, + GPIO_QSPI_SD0_LEVEL_LOW: u1, + GPIO_QSPI_SD0_LEVEL_HIGH: u1, + GPIO_QSPI_SD0_EDGE_LOW: u1, + GPIO_QSPI_SD0_EDGE_HIGH: u1, + GPIO_QSPI_SD1_LEVEL_LOW: u1, + GPIO_QSPI_SD1_LEVEL_HIGH: u1, + GPIO_QSPI_SD1_EDGE_LOW: u1, + GPIO_QSPI_SD1_EDGE_HIGH: u1, + GPIO_QSPI_SD2_LEVEL_LOW: u1, + GPIO_QSPI_SD2_LEVEL_HIGH: u1, + GPIO_QSPI_SD2_EDGE_LOW: u1, + GPIO_QSPI_SD2_EDGE_HIGH: u1, + GPIO_QSPI_SD3_LEVEL_LOW: u1, + GPIO_QSPI_SD3_LEVEL_HIGH: u1, + GPIO_QSPI_SD3_EDGE_LOW: u1, + GPIO_QSPI_SD3_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x30); + + /// address: 0x40018034 + /// Interrupt Enable for proc0 + pub const PROC0_INTE = @intToPtr(*volatile Mmio(32, packed struct { + GPIO_QSPI_SCLK_LEVEL_LOW: u1, + GPIO_QSPI_SCLK_LEVEL_HIGH: u1, + GPIO_QSPI_SCLK_EDGE_LOW: u1, + GPIO_QSPI_SCLK_EDGE_HIGH: u1, + GPIO_QSPI_SS_LEVEL_LOW: u1, + GPIO_QSPI_SS_LEVEL_HIGH: u1, + GPIO_QSPI_SS_EDGE_LOW: u1, + GPIO_QSPI_SS_EDGE_HIGH: u1, + GPIO_QSPI_SD0_LEVEL_LOW: u1, + GPIO_QSPI_SD0_LEVEL_HIGH: u1, + GPIO_QSPI_SD0_EDGE_LOW: u1, + GPIO_QSPI_SD0_EDGE_HIGH: u1, + GPIO_QSPI_SD1_LEVEL_LOW: u1, + GPIO_QSPI_SD1_LEVEL_HIGH: u1, + GPIO_QSPI_SD1_EDGE_LOW: u1, + GPIO_QSPI_SD1_EDGE_HIGH: u1, + GPIO_QSPI_SD2_LEVEL_LOW: u1, + GPIO_QSPI_SD2_LEVEL_HIGH: u1, + GPIO_QSPI_SD2_EDGE_LOW: u1, + GPIO_QSPI_SD2_EDGE_HIGH: u1, + GPIO_QSPI_SD3_LEVEL_LOW: u1, + GPIO_QSPI_SD3_LEVEL_HIGH: u1, + GPIO_QSPI_SD3_EDGE_LOW: u1, + GPIO_QSPI_SD3_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x34); + + /// address: 0x40018038 + /// Interrupt Force for proc0 + pub const PROC0_INTF = @intToPtr(*volatile Mmio(32, packed struct { + GPIO_QSPI_SCLK_LEVEL_LOW: u1, + GPIO_QSPI_SCLK_LEVEL_HIGH: u1, + GPIO_QSPI_SCLK_EDGE_LOW: u1, + GPIO_QSPI_SCLK_EDGE_HIGH: u1, + GPIO_QSPI_SS_LEVEL_LOW: u1, + GPIO_QSPI_SS_LEVEL_HIGH: u1, + GPIO_QSPI_SS_EDGE_LOW: u1, + GPIO_QSPI_SS_EDGE_HIGH: u1, + GPIO_QSPI_SD0_LEVEL_LOW: u1, + GPIO_QSPI_SD0_LEVEL_HIGH: u1, + GPIO_QSPI_SD0_EDGE_LOW: u1, + GPIO_QSPI_SD0_EDGE_HIGH: u1, + GPIO_QSPI_SD1_LEVEL_LOW: u1, + GPIO_QSPI_SD1_LEVEL_HIGH: u1, + GPIO_QSPI_SD1_EDGE_LOW: u1, + GPIO_QSPI_SD1_EDGE_HIGH: u1, + GPIO_QSPI_SD2_LEVEL_LOW: u1, + GPIO_QSPI_SD2_LEVEL_HIGH: u1, + GPIO_QSPI_SD2_EDGE_LOW: u1, + GPIO_QSPI_SD2_EDGE_HIGH: u1, + GPIO_QSPI_SD3_LEVEL_LOW: u1, + GPIO_QSPI_SD3_LEVEL_HIGH: u1, + GPIO_QSPI_SD3_EDGE_LOW: u1, + GPIO_QSPI_SD3_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x38); + + /// address: 0x4001803c + /// Interrupt status after masking & forcing for proc0 + pub const PROC0_INTS = @intToPtr(*volatile Mmio(32, packed struct { + GPIO_QSPI_SCLK_LEVEL_LOW: u1, + GPIO_QSPI_SCLK_LEVEL_HIGH: u1, + GPIO_QSPI_SCLK_EDGE_LOW: u1, + GPIO_QSPI_SCLK_EDGE_HIGH: u1, + GPIO_QSPI_SS_LEVEL_LOW: u1, + GPIO_QSPI_SS_LEVEL_HIGH: u1, + GPIO_QSPI_SS_EDGE_LOW: u1, + GPIO_QSPI_SS_EDGE_HIGH: u1, + GPIO_QSPI_SD0_LEVEL_LOW: u1, + GPIO_QSPI_SD0_LEVEL_HIGH: u1, + GPIO_QSPI_SD0_EDGE_LOW: u1, + GPIO_QSPI_SD0_EDGE_HIGH: u1, + GPIO_QSPI_SD1_LEVEL_LOW: u1, + GPIO_QSPI_SD1_LEVEL_HIGH: u1, + GPIO_QSPI_SD1_EDGE_LOW: u1, + GPIO_QSPI_SD1_EDGE_HIGH: u1, + GPIO_QSPI_SD2_LEVEL_LOW: u1, + GPIO_QSPI_SD2_LEVEL_HIGH: u1, + GPIO_QSPI_SD2_EDGE_LOW: u1, + GPIO_QSPI_SD2_EDGE_HIGH: u1, + GPIO_QSPI_SD3_LEVEL_LOW: u1, + GPIO_QSPI_SD3_LEVEL_HIGH: u1, + GPIO_QSPI_SD3_EDGE_LOW: u1, + GPIO_QSPI_SD3_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x3c); + + /// address: 0x40018040 + /// Interrupt Enable for proc1 + pub const PROC1_INTE = @intToPtr(*volatile Mmio(32, packed struct { + GPIO_QSPI_SCLK_LEVEL_LOW: u1, + GPIO_QSPI_SCLK_LEVEL_HIGH: u1, + GPIO_QSPI_SCLK_EDGE_LOW: u1, + GPIO_QSPI_SCLK_EDGE_HIGH: u1, + GPIO_QSPI_SS_LEVEL_LOW: u1, + GPIO_QSPI_SS_LEVEL_HIGH: u1, + GPIO_QSPI_SS_EDGE_LOW: u1, + GPIO_QSPI_SS_EDGE_HIGH: u1, + GPIO_QSPI_SD0_LEVEL_LOW: u1, + GPIO_QSPI_SD0_LEVEL_HIGH: u1, + GPIO_QSPI_SD0_EDGE_LOW: u1, + GPIO_QSPI_SD0_EDGE_HIGH: u1, + GPIO_QSPI_SD1_LEVEL_LOW: u1, + GPIO_QSPI_SD1_LEVEL_HIGH: u1, + GPIO_QSPI_SD1_EDGE_LOW: u1, + GPIO_QSPI_SD1_EDGE_HIGH: u1, + GPIO_QSPI_SD2_LEVEL_LOW: u1, + GPIO_QSPI_SD2_LEVEL_HIGH: u1, + GPIO_QSPI_SD2_EDGE_LOW: u1, + GPIO_QSPI_SD2_EDGE_HIGH: u1, + GPIO_QSPI_SD3_LEVEL_LOW: u1, + GPIO_QSPI_SD3_LEVEL_HIGH: u1, + GPIO_QSPI_SD3_EDGE_LOW: u1, + GPIO_QSPI_SD3_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x40); + + /// address: 0x40018044 + /// Interrupt Force for proc1 + pub const PROC1_INTF = @intToPtr(*volatile Mmio(32, packed struct { + GPIO_QSPI_SCLK_LEVEL_LOW: u1, + GPIO_QSPI_SCLK_LEVEL_HIGH: u1, + GPIO_QSPI_SCLK_EDGE_LOW: u1, + GPIO_QSPI_SCLK_EDGE_HIGH: u1, + GPIO_QSPI_SS_LEVEL_LOW: u1, + GPIO_QSPI_SS_LEVEL_HIGH: u1, + GPIO_QSPI_SS_EDGE_LOW: u1, + GPIO_QSPI_SS_EDGE_HIGH: u1, + GPIO_QSPI_SD0_LEVEL_LOW: u1, + GPIO_QSPI_SD0_LEVEL_HIGH: u1, + GPIO_QSPI_SD0_EDGE_LOW: u1, + GPIO_QSPI_SD0_EDGE_HIGH: u1, + GPIO_QSPI_SD1_LEVEL_LOW: u1, + GPIO_QSPI_SD1_LEVEL_HIGH: u1, + GPIO_QSPI_SD1_EDGE_LOW: u1, + GPIO_QSPI_SD1_EDGE_HIGH: u1, + GPIO_QSPI_SD2_LEVEL_LOW: u1, + GPIO_QSPI_SD2_LEVEL_HIGH: u1, + GPIO_QSPI_SD2_EDGE_LOW: u1, + GPIO_QSPI_SD2_EDGE_HIGH: u1, + GPIO_QSPI_SD3_LEVEL_LOW: u1, + GPIO_QSPI_SD3_LEVEL_HIGH: u1, + GPIO_QSPI_SD3_EDGE_LOW: u1, + GPIO_QSPI_SD3_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x44); + + /// address: 0x40018048 + /// Interrupt status after masking & forcing for proc1 + pub const PROC1_INTS = @intToPtr(*volatile Mmio(32, packed struct { + GPIO_QSPI_SCLK_LEVEL_LOW: u1, + GPIO_QSPI_SCLK_LEVEL_HIGH: u1, + GPIO_QSPI_SCLK_EDGE_LOW: u1, + GPIO_QSPI_SCLK_EDGE_HIGH: u1, + GPIO_QSPI_SS_LEVEL_LOW: u1, + GPIO_QSPI_SS_LEVEL_HIGH: u1, + GPIO_QSPI_SS_EDGE_LOW: u1, + GPIO_QSPI_SS_EDGE_HIGH: u1, + GPIO_QSPI_SD0_LEVEL_LOW: u1, + GPIO_QSPI_SD0_LEVEL_HIGH: u1, + GPIO_QSPI_SD0_EDGE_LOW: u1, + GPIO_QSPI_SD0_EDGE_HIGH: u1, + GPIO_QSPI_SD1_LEVEL_LOW: u1, + GPIO_QSPI_SD1_LEVEL_HIGH: u1, + GPIO_QSPI_SD1_EDGE_LOW: u1, + GPIO_QSPI_SD1_EDGE_HIGH: u1, + GPIO_QSPI_SD2_LEVEL_LOW: u1, + GPIO_QSPI_SD2_LEVEL_HIGH: u1, + GPIO_QSPI_SD2_EDGE_LOW: u1, + GPIO_QSPI_SD2_EDGE_HIGH: u1, + GPIO_QSPI_SD3_LEVEL_LOW: u1, + GPIO_QSPI_SD3_LEVEL_HIGH: u1, + GPIO_QSPI_SD3_EDGE_LOW: u1, + GPIO_QSPI_SD3_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x48); + + /// address: 0x4001804c + /// Interrupt Enable for dormant_wake + pub const DORMANT_WAKE_INTE = @intToPtr(*volatile Mmio(32, packed struct { + GPIO_QSPI_SCLK_LEVEL_LOW: u1, + GPIO_QSPI_SCLK_LEVEL_HIGH: u1, + GPIO_QSPI_SCLK_EDGE_LOW: u1, + GPIO_QSPI_SCLK_EDGE_HIGH: u1, + GPIO_QSPI_SS_LEVEL_LOW: u1, + GPIO_QSPI_SS_LEVEL_HIGH: u1, + GPIO_QSPI_SS_EDGE_LOW: u1, + GPIO_QSPI_SS_EDGE_HIGH: u1, + GPIO_QSPI_SD0_LEVEL_LOW: u1, + GPIO_QSPI_SD0_LEVEL_HIGH: u1, + GPIO_QSPI_SD0_EDGE_LOW: u1, + GPIO_QSPI_SD0_EDGE_HIGH: u1, + GPIO_QSPI_SD1_LEVEL_LOW: u1, + GPIO_QSPI_SD1_LEVEL_HIGH: u1, + GPIO_QSPI_SD1_EDGE_LOW: u1, + GPIO_QSPI_SD1_EDGE_HIGH: u1, + GPIO_QSPI_SD2_LEVEL_LOW: u1, + GPIO_QSPI_SD2_LEVEL_HIGH: u1, + GPIO_QSPI_SD2_EDGE_LOW: u1, + GPIO_QSPI_SD2_EDGE_HIGH: u1, + GPIO_QSPI_SD3_LEVEL_LOW: u1, + GPIO_QSPI_SD3_LEVEL_HIGH: u1, + GPIO_QSPI_SD3_EDGE_LOW: u1, + GPIO_QSPI_SD3_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x4c); + + /// address: 0x40018050 + /// Interrupt Force for dormant_wake + pub const DORMANT_WAKE_INTF = @intToPtr(*volatile Mmio(32, packed struct { + GPIO_QSPI_SCLK_LEVEL_LOW: u1, + GPIO_QSPI_SCLK_LEVEL_HIGH: u1, + GPIO_QSPI_SCLK_EDGE_LOW: u1, + GPIO_QSPI_SCLK_EDGE_HIGH: u1, + GPIO_QSPI_SS_LEVEL_LOW: u1, + GPIO_QSPI_SS_LEVEL_HIGH: u1, + GPIO_QSPI_SS_EDGE_LOW: u1, + GPIO_QSPI_SS_EDGE_HIGH: u1, + GPIO_QSPI_SD0_LEVEL_LOW: u1, + GPIO_QSPI_SD0_LEVEL_HIGH: u1, + GPIO_QSPI_SD0_EDGE_LOW: u1, + GPIO_QSPI_SD0_EDGE_HIGH: u1, + GPIO_QSPI_SD1_LEVEL_LOW: u1, + GPIO_QSPI_SD1_LEVEL_HIGH: u1, + GPIO_QSPI_SD1_EDGE_LOW: u1, + GPIO_QSPI_SD1_EDGE_HIGH: u1, + GPIO_QSPI_SD2_LEVEL_LOW: u1, + GPIO_QSPI_SD2_LEVEL_HIGH: u1, + GPIO_QSPI_SD2_EDGE_LOW: u1, + GPIO_QSPI_SD2_EDGE_HIGH: u1, + GPIO_QSPI_SD3_LEVEL_LOW: u1, + GPIO_QSPI_SD3_LEVEL_HIGH: u1, + GPIO_QSPI_SD3_EDGE_LOW: u1, + GPIO_QSPI_SD3_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x50); + + /// address: 0x40018054 + /// Interrupt status after masking & forcing for dormant_wake + pub const DORMANT_WAKE_INTS = @intToPtr(*volatile Mmio(32, packed struct { + GPIO_QSPI_SCLK_LEVEL_LOW: u1, + GPIO_QSPI_SCLK_LEVEL_HIGH: u1, + GPIO_QSPI_SCLK_EDGE_LOW: u1, + GPIO_QSPI_SCLK_EDGE_HIGH: u1, + GPIO_QSPI_SS_LEVEL_LOW: u1, + GPIO_QSPI_SS_LEVEL_HIGH: u1, + GPIO_QSPI_SS_EDGE_LOW: u1, + GPIO_QSPI_SS_EDGE_HIGH: u1, + GPIO_QSPI_SD0_LEVEL_LOW: u1, + GPIO_QSPI_SD0_LEVEL_HIGH: u1, + GPIO_QSPI_SD0_EDGE_LOW: u1, + GPIO_QSPI_SD0_EDGE_HIGH: u1, + GPIO_QSPI_SD1_LEVEL_LOW: u1, + GPIO_QSPI_SD1_LEVEL_HIGH: u1, + GPIO_QSPI_SD1_EDGE_LOW: u1, + GPIO_QSPI_SD1_EDGE_HIGH: u1, + GPIO_QSPI_SD2_LEVEL_LOW: u1, + GPIO_QSPI_SD2_LEVEL_HIGH: u1, + GPIO_QSPI_SD2_EDGE_LOW: u1, + GPIO_QSPI_SD2_EDGE_HIGH: u1, + GPIO_QSPI_SD3_LEVEL_LOW: u1, + GPIO_QSPI_SD3_LEVEL_HIGH: u1, + GPIO_QSPI_SD3_EDGE_LOW: u1, + GPIO_QSPI_SD3_EDGE_HIGH: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x54); + }; + pub const PADS_BANK0 = struct { + pub const base_address = 0x4001c000; + pub const version = "1"; + + /// address: 0x4001c000 + /// Voltage select. Per bank control + pub const VOLTAGE_SELECT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0); + + /// address: 0x4001c004 + /// Pad control register + pub const GPIO0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x4); + + /// address: 0x4001c008 + /// Pad control register + pub const GPIO1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x8); + + /// address: 0x4001c00c + /// Pad control register + pub const GPIO2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xc); + + /// address: 0x4001c010 + /// Pad control register + pub const GPIO3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x10); + + /// address: 0x4001c014 + /// Pad control register + pub const GPIO4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x14); + + /// address: 0x4001c018 + /// Pad control register + pub const GPIO5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x18); + + /// address: 0x4001c01c + /// Pad control register + pub const GPIO6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x1c); + + /// address: 0x4001c020 + /// Pad control register + pub const GPIO7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x20); + + /// address: 0x4001c024 + /// Pad control register + pub const GPIO8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x24); + + /// address: 0x4001c028 + /// Pad control register + pub const GPIO9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x28); + + /// address: 0x4001c02c + /// Pad control register + pub const GPIO10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x2c); + + /// address: 0x4001c030 + /// Pad control register + pub const GPIO11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x30); + + /// address: 0x4001c034 + /// Pad control register + pub const GPIO12 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x34); + + /// address: 0x4001c038 + /// Pad control register + pub const GPIO13 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x38); + + /// address: 0x4001c03c + /// Pad control register + pub const GPIO14 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x3c); + + /// address: 0x4001c040 + /// Pad control register + pub const GPIO15 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x40); + + /// address: 0x4001c044 + /// Pad control register + pub const GPIO16 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x44); + + /// address: 0x4001c048 + /// Pad control register + pub const GPIO17 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x48); + + /// address: 0x4001c04c + /// Pad control register + pub const GPIO18 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x4c); + + /// address: 0x4001c050 + /// Pad control register + pub const GPIO19 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x50); + + /// address: 0x4001c054 + /// Pad control register + pub const GPIO20 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x54); + + /// address: 0x4001c058 + /// Pad control register + pub const GPIO21 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x58); + + /// address: 0x4001c05c + /// Pad control register + pub const GPIO22 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x5c); + + /// address: 0x4001c060 + /// Pad control register + pub const GPIO23 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x60); + + /// address: 0x4001c064 + /// Pad control register + pub const GPIO24 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x64); + + /// address: 0x4001c068 + /// Pad control register + pub const GPIO25 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x68); + + /// address: 0x4001c06c + /// Pad control register + pub const GPIO26 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x6c); + + /// address: 0x4001c070 + /// Pad control register + pub const GPIO27 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x70); + + /// address: 0x4001c074 + /// Pad control register + pub const GPIO28 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x74); + + /// address: 0x4001c078 + /// Pad control register + pub const GPIO29 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x78); + + /// address: 0x4001c07c + /// Pad control register + pub const SWCLK = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x7c); + + /// address: 0x4001c080 + /// Pad control register + pub const SWD = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x80); + }; + pub const PADS_QSPI = struct { + pub const base_address = 0x40020000; + pub const version = "1"; + + /// address: 0x40020000 + /// Voltage select. Per bank control + pub const VOLTAGE_SELECT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0); + + /// address: 0x40020004 + /// Pad control register + pub const GPIO_QSPI_SCLK = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40020008 + /// Pad control register + pub const GPIO_QSPI_SD0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x8); + + /// address: 0x4002000c + /// Pad control register + pub const GPIO_QSPI_SD1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xc); + + /// address: 0x40020010 + /// Pad control register + pub const GPIO_QSPI_SD2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x10); + + /// address: 0x40020014 + /// Pad control register + pub const GPIO_QSPI_SD3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x14); + + /// address: 0x40020018 + /// Pad control register + pub const GPIO_QSPI_SS = @intToPtr(*volatile Mmio(32, packed struct { + /// Slew rate control. 1 = Fast, 0 = Slow + SLEWFAST: u1, + /// Enable schmitt trigger + SCHMITT: u1, + /// Pull down enable + PDE: u1, + /// Pull up enable + PUE: u1, + /// Drive strength. + DRIVE: u2, + /// Input enable + IE: u1, + /// Output disable. Has priority over output enable from peripherals + OD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x18); + }; + + /// Controls the crystal oscillator + pub const XOSC = struct { + pub const base_address = 0x40024000; + pub const version = "1"; + + /// address: 0x40024000 + /// Crystal Oscillator Control + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Frequency range. This resets to 0xAA0 and cannot be changed. + FREQ_RANGE: u12, + /// On power-up this field is initialised to DISABLE and the chip runs from the + /// ROSC.\n + /// If the chip has subsequently been programmed to run from the XOSC then setting + /// this field to DISABLE may lock-up the chip. If this is a concern then run the + /// clk_ref from the ROSC and enable the clk_sys RESUS feature.\n + /// The 12-bit code is intended to give some protection against accidental writes. + /// An invalid setting will enable the oscillator. + ENABLE: u12, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40024004 + /// Crystal Oscillator Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// The current frequency range setting, always reads 0 + FREQ_RANGE: u2, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + /// Oscillator is enabled but not necessarily running and stable, resets to 0 + ENABLED: u1, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + /// An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT + BADWRITE: u1, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + reserved24: u1 = 0, + reserved25: u1 = 0, + reserved26: u1 = 0, + /// Oscillator is running and stable + STABLE: u1, + }), base_address + 0x4); + + /// address: 0x40024008 + /// Crystal Oscillator pause control\n + /// This is used to save power by pausing the XOSC\n + /// On power-up this field is initialised to WAKE\n + /// An invalid write will also select WAKE\n + /// WARNING: stop the PLLs before selecting dormant mode\n + /// WARNING: setup the irq before selecting dormant mode + pub const DORMANT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4002400c + /// Controls the startup delay + pub const STARTUP = @intToPtr(*volatile Mmio(32, packed struct { + /// in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx + /// 50 000 cycles. + DELAY: u14, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// Multiplies the startup_delay by 4. This is of little value to the user given + /// that the delay can be programmed directly. + X4: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + }), base_address + 0xc); + + /// address: 0x4002401c + /// A down counter running at the xosc frequency which counts to zero and stops.\n + /// To start the counter write a non-zero value.\n + /// Can be used for short software pauses when setting up time sensitive hardware. + pub const COUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x1c); + }; + pub const PLL_SYS = struct { + pub const base_address = 0x40028000; + pub const version = "1"; + + /// address: 0x40028000 + /// Control and Status\n + /// GENERAL CONSTRAINTS:\n + /// Reference clock frequency min=5MHz, max=800MHz\n + /// Feedback divider min=16, max=320\n + /// VCO frequency min=400MHz, max=1600MHz + pub const CS = @intToPtr(*volatile Mmio(32, packed struct { + /// Divides the PLL input reference clock.\n + /// Behaviour is undefined for div=0.\n + /// PLL output will be unpredictable during refdiv changes, wait for lock=1 before + /// using it. + REFDIV: u6, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// Passes the reference clock to the output instead of the divided VCO. The VCO + /// continues to run so the user can switch between the reference clock and the + /// divided VCO but the output will glitch when doing so. + BYPASS: u1, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + /// PLL is locked + LOCK: u1, + }), base_address + 0x0); + + /// address: 0x40028004 + /// Controls the PLL power modes. + pub const PWR = @intToPtr(*volatile Mmio(32, packed struct { + /// PLL powerdown\n + /// To save power set high when PLL output not required. + PD: u1, + reserved0: u1 = 0, + /// PLL DSM powerdown\n + /// Nothing is achieved by setting this low. + DSMPD: u1, + /// PLL post divider powerdown\n + /// To save power set high when PLL output not required or bypass=1. + POSTDIVPD: u1, + reserved1: u1 = 0, + /// PLL VCO powerdown\n + /// To save power set high when PLL output not required or bypass=1. + VCOPD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40028008 + /// Feedback divisor\n + /// (note: this PLL does not support fractional division) + pub const FBDIV_INT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x8); + + /// address: 0x4002800c + /// Controls the PLL post dividers for the primary output\n + /// (note: this PLL does not have a secondary output)\n + /// the primary output is driven from VCO divided by postdiv1*postdiv2 + pub const PRIM = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// divide by 1-7 + POSTDIV2: u3, + reserved12: u1 = 0, + /// divide by 1-7 + POSTDIV1: u3, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + }), base_address + 0xc); + }; + pub const PLL_USB = struct { + pub const base_address = 0x4002c000; + + /// address: 0x4002c000 + /// Control and Status\n + /// GENERAL CONSTRAINTS:\n + /// Reference clock frequency min=5MHz, max=800MHz\n + /// Feedback divider min=16, max=320\n + /// VCO frequency min=400MHz, max=1600MHz + pub const CS = @intToPtr(*volatile Mmio(32, packed struct { + /// Divides the PLL input reference clock.\n + /// Behaviour is undefined for div=0.\n + /// PLL output will be unpredictable during refdiv changes, wait for lock=1 before + /// using it. + REFDIV: u6, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// Passes the reference clock to the output instead of the divided VCO. The VCO + /// continues to run so the user can switch between the reference clock and the + /// divided VCO but the output will glitch when doing so. + BYPASS: u1, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + /// PLL is locked + LOCK: u1, + }), base_address + 0x0); + + /// address: 0x4002c004 + /// Controls the PLL power modes. + pub const PWR = @intToPtr(*volatile Mmio(32, packed struct { + /// PLL powerdown\n + /// To save power set high when PLL output not required. + PD: u1, + reserved0: u1 = 0, + /// PLL DSM powerdown\n + /// Nothing is achieved by setting this low. + DSMPD: u1, + /// PLL post divider powerdown\n + /// To save power set high when PLL output not required or bypass=1. + POSTDIVPD: u1, + reserved1: u1 = 0, + /// PLL VCO powerdown\n + /// To save power set high when PLL output not required or bypass=1. + VCOPD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + }), base_address + 0x4); + + /// address: 0x4002c008 + /// Feedback divisor\n + /// (note: this PLL does not support fractional division) + pub const FBDIV_INT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x8); + + /// address: 0x4002c00c + /// Controls the PLL post dividers for the primary output\n + /// (note: this PLL does not have a secondary output)\n + /// the primary output is driven from VCO divided by postdiv1*postdiv2 + pub const PRIM = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// divide by 1-7 + POSTDIV2: u3, + reserved12: u1 = 0, + /// divide by 1-7 + POSTDIV1: u3, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + }), base_address + 0xc); + }; + + /// Register block for busfabric control signals and performance counters + pub const BUSCTRL = struct { + pub const base_address = 0x40030000; + pub const version = "1"; + + /// address: 0x40030000 + /// Set the priority of each master for bus arbitration. + pub const BUS_PRIORITY = @intToPtr(*volatile Mmio(32, packed struct { + /// 0 - low priority, 1 - high priority + PROC0: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// 0 - low priority, 1 - high priority + PROC1: u1, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// 0 - low priority, 1 - high priority + DMA_R: u1, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// 0 - low priority, 1 - high priority + DMA_W: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40030004 + /// Bus priority acknowledge + pub const BUS_PRIORITY_ACK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4); + + /// address: 0x40030008 + /// Bus fabric performance counter 0 + pub const PERFCTR0 = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x8); + + /// address: 0x4003000c + /// Bus fabric performance event select for PERFCTR0 + pub const PERFSEL0 = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc); + + /// address: 0x40030010 + /// Bus fabric performance counter 1 + pub const PERFCTR1 = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x10); + + /// address: 0x40030014 + /// Bus fabric performance event select for PERFCTR1 + pub const PERFSEL1 = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x14); + + /// address: 0x40030018 + /// Bus fabric performance counter 2 + pub const PERFCTR2 = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x18); + + /// address: 0x4003001c + /// Bus fabric performance event select for PERFCTR2 + pub const PERFSEL2 = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x1c); + + /// address: 0x40030020 + /// Bus fabric performance counter 3 + pub const PERFCTR3 = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x20); + + /// address: 0x40030024 + /// Bus fabric performance event select for PERFCTR3 + pub const PERFSEL3 = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x24); + }; + pub const UART0 = struct { + pub const base_address = 0x40034000; + pub const version = "1"; + + /// address: 0x40034000 + /// Data Register, UARTDR + pub const UARTDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive (read) data character. Transmit (write) data character. + DATA: u8, + /// Framing error. When set to 1, it indicates that the received character did not + /// have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is + /// associated with the character at the top of the FIFO. + FE: u1, + /// Parity error. When set to 1, it indicates that the parity of the received data + /// character does not match the parity that the EPS and SPS bits in the Line + /// Control Register, UARTLCR_H. In FIFO mode, this error is associated with the + /// character at the top of the FIFO. + PE: u1, + /// Break error. This bit is set to 1 if a break condition was detected, indicating + /// that the received data input was held LOW for longer than a full-word + /// transmission time (defined as start, data, parity and stop bits). In FIFO mode, + /// this error is associated with the character at the top of the FIFO. When a break + /// occurs, only one 0 character is loaded into the FIFO. The next character is only + /// enabled after the receive data input goes to a 1 (marking state), and the next + /// valid start bit is received. + BE: u1, + /// Overrun error. This bit is set to 1 if data is received and the receive FIFO is + /// already full. This is cleared to 0 once there is an empty space in the FIFO and + /// a new character can be written to it. + OE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40034004 + /// Receive Status Register/Error Clear Register, UARTRSR/UARTECR + pub const UARTRSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Framing error. When set to 1, it indicates that the received character did not + /// have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a + /// write to UARTECR. In FIFO mode, this error is associated with the character at + /// the top of the FIFO. + FE: u1, + /// Parity error. When set to 1, it indicates that the parity of the received data + /// character does not match the parity that the EPS and SPS bits in the Line + /// Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In + /// FIFO mode, this error is associated with the character at the top of the FIFO. + PE: u1, + /// Break error. This bit is set to 1 if a break condition was detected, indicating + /// that the received data input was held LOW for longer than a full-word + /// transmission time (defined as start, data, parity, and stop bits). This bit is + /// cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated + /// with the character at the top of the FIFO. When a break occurs, only one 0 + /// character is loaded into the FIFO. The next character is only enabled after the + /// receive data input goes to a 1 (marking state) and the next valid start bit is + /// received. + BE: u1, + /// Overrun error. This bit is set to 1 if data is received and the FIFO is already + /// full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain + /// valid because no more data is written when the FIFO is full, only the contents + /// of the shift register are overwritten. The CPU must now read the data, to empty + /// the FIFO. + OE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40034018 + /// Flag Register, UARTFR + pub const UARTFR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, + /// modem status input. That is, the bit is 1 when nUARTCTS is LOW. + CTS: u1, + /// Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, + /// modem status input. That is, the bit is 1 when nUARTDSR is LOW. + DSR: u1, + /// Data carrier detect. This bit is the complement of the UART data carrier detect, + /// nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. + DCD: u1, + /// UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit + /// remains set until the complete byte, including all the stop bits, has been sent + /// from the shift register. This bit is set as soon as the transmit FIFO becomes + /// non-empty, regardless of whether the UART is enabled or not. + BUSY: u1, + /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit + /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the + /// receive holding register is empty. If the FIFO is enabled, the RXFE bit is set + /// when the receive FIFO is empty. + RXFE: u1, + /// Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit + /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the + /// transmit holding register is full. If the FIFO is enabled, the TXFF bit is set + /// when the transmit FIFO is full. + TXFF: u1, + /// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit + /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the + /// receive holding register is full. If the FIFO is enabled, the RXFF bit is set + /// when the receive FIFO is full. + RXFF: u1, + /// Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit + /// in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is + /// set when the transmit holding register is empty. If the FIFO is enabled, the + /// TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if + /// there is data in the transmit shift register. + TXFE: u1, + /// Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, + /// modem status input. That is, the bit is 1 when nUARTRI is LOW. + RI: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + }), base_address + 0x18); + + /// address: 0x40034020 + /// IrDA Low-Power Counter Register, UARTILPR + pub const UARTILPR = @intToPtr(*volatile Mmio(32, packed struct { + /// 8-bit low-power divisor value. These bits are cleared to 0 at reset. + ILPDVSR: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x20); + + /// address: 0x40034024 + /// Integer Baud Rate Register, UARTIBRD + pub const UARTIBRD = @intToPtr(*volatile Mmio(32, packed struct { + /// The integer baud rate divisor. These bits are cleared to 0 on reset. + BAUD_DIVINT: u16, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x24); + + /// address: 0x40034028 + /// Fractional Baud Rate Register, UARTFBRD + pub const UARTFBRD = @intToPtr(*volatile Mmio(32, packed struct { + /// The fractional baud rate divisor. These bits are cleared to 0 on reset. + BAUD_DIVFRAC: u6, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + }), base_address + 0x28); + + /// address: 0x4003402c + /// Line Control Register, UARTLCR_H + pub const UARTLCR_H = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break. If this bit is set to 1, a low-level is continually output on the + /// UARTTXD output, after completing transmission of the current character. For the + /// proper execution of the break command, the software must set this bit for at + /// least two complete frames. For normal use, this bit must be cleared to 0. + BRK: u1, + /// Parity enable: 0 = parity is disabled and no parity bit added to the data frame + /// 1 = parity checking and generation is enabled. + PEN: u1, + /// Even parity select. Controls the type of parity the UART uses during + /// transmission and reception: 0 = odd parity. The UART generates or checks for an + /// odd number of 1s in the data and parity bits. 1 = even parity. The UART + /// generates or checks for an even number of 1s in the data and parity bits. This + /// bit has no effect when the PEN bit disables parity checking and generation. + EPS: u1, + /// Two stop bits select. If this bit is set to 1, two stop bits are transmitted at + /// the end of the frame. The receive logic does not check for two stop bits being + /// received. + STP2: u1, + /// Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become + /// 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled + /// (FIFO mode). + FEN: u1, + /// Word length. These bits indicate the number of data bits transmitted or received + /// in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. + WLEN: u2, + /// Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit + /// is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 + /// then the parity bit is transmitted and checked as a 0. This bit has no effect + /// when the PEN bit disables parity checking and generation. + SPS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x2c); + + /// address: 0x40034030 + /// Control Register, UARTCR + pub const UARTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// UART enable: 0 = UART is disabled. If the UART is disabled in the middle of + /// transmission or reception, it completes the current character before stopping. 1 + /// = the UART is enabled. Data transmission and reception occurs for either UART + /// signals or SIR signals depending on the setting of the SIREN bit. + UARTEN: u1, + /// SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse + /// generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC + /// is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD + /// remains HIGH, in the marking state. Signal transitions on UARTRXD or modem + /// status inputs have no effect. This bit has no effect if the UARTEN bit disables + /// the UART. + SIREN: u1, + /// SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is + /// cleared to 0, low-level bits are transmitted as an active high pulse with a + /// width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are + /// transmitted with a pulse width that is 3 times the period of the IrLPBaud16 + /// input signal, regardless of the selected bit rate. Setting this bit uses less + /// power, but might reduce transmission distances. + SIRLP: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the + /// SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT + /// path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test + /// register must be set to 1 to override the normal half-duplex SIR operation. This + /// must be the requirement for accessing the test registers during normal + /// operation, and SIRTEST must be cleared to 0 when loopback testing is finished. + /// This feature reduces the amount of external coupling required during system + /// test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path + /// is fed through to the UARTRXD path. In either SIR mode or UART mode, when this + /// bit is set, the modem outputs are also fed through to the modem inputs. This bit + /// is cleared to 0 on reset, to disable loopback. + LBE: u1, + /// Transmit enable. If this bit is set to 1, the transmit section of the UART is + /// enabled. Data transmission occurs for either UART signals, or SIR signals + /// depending on the setting of the SIREN bit. When the UART is disabled in the + /// middle of transmission, it completes the current character before stopping. + TXE: u1, + /// Receive enable. If this bit is set to 1, the receive section of the UART is + /// enabled. Data reception occurs for either UART signals or SIR signals depending + /// on the setting of the SIREN bit. When the UART is disabled in the middle of + /// reception, it completes the current character before stopping. + RXE: u1, + /// Data transmit ready. This bit is the complement of the UART data transmit ready, + /// nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then + /// nUARTDTR is LOW. + DTR: u1, + /// Request to send. This bit is the complement of the UART request to send, + /// nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then + /// nUARTRTS is LOW. + RTS: u1, + /// This bit is the complement of the UART Out1 (nUARTOut1) modem status output. + /// That is, when the bit is programmed to a 1 the output is 0. For DTE this can be + /// used as Data Carrier Detect (DCD). + OUT1: u1, + /// This bit is the complement of the UART Out2 (nUARTOut2) modem status output. + /// That is, when the bit is programmed to a 1, the output is 0. For DTE this can be + /// used as Ring Indicator (RI). + OUT2: u1, + /// RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow + /// control is enabled. Data is only requested when there is space in the receive + /// FIFO for it to be received. + RTSEN: u1, + /// CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow + /// control is enabled. Data is only transmitted when the nUARTCTS signal is + /// asserted. + CTSEN: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x30); + + /// address: 0x40034034 + /// Interrupt FIFO Level Select Register, UARTIFLS + pub const UARTIFLS = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit interrupt FIFO level select. The trigger points for the transmit + /// interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = + /// Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full + /// b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 + /// full b101-b111 = reserved. + TXIFLSEL: u3, + /// Receive interrupt FIFO level select. The trigger points for the receive + /// interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = + /// Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full + /// b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 + /// full b101-b111 = reserved. + RXIFLSEL: u3, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + }), base_address + 0x34); + + /// address: 0x40034038 + /// Interrupt Mask Set/Clear Register, UARTIMSC + pub const UARTIMSC = @intToPtr(*volatile Mmio(32, packed struct { + /// nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR + /// interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write + /// of 0 clears the mask. + RIMIM: u1, + /// nUARTCTS modem interrupt mask. A read returns the current mask for the + /// UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is + /// set. A write of 0 clears the mask. + CTSMIM: u1, + /// nUARTDCD modem interrupt mask. A read returns the current mask for the + /// UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is + /// set. A write of 0 clears the mask. + DCDMIM: u1, + /// nUARTDSR modem interrupt mask. A read returns the current mask for the + /// UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is + /// set. A write of 0 clears the mask. + DSRMIM: u1, + /// Receive interrupt mask. A read returns the current mask for the UARTRXINTR + /// interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write + /// of 0 clears the mask. + RXIM: u1, + /// Transmit interrupt mask. A read returns the current mask for the UARTTXINTR + /// interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write + /// of 0 clears the mask. + TXIM: u1, + /// Receive timeout interrupt mask. A read returns the current mask for the + /// UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is + /// set. A write of 0 clears the mask. + RTIM: u1, + /// Framing error interrupt mask. A read returns the current mask for the UARTFEINTR + /// interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write + /// of 0 clears the mask. + FEIM: u1, + /// Parity error interrupt mask. A read returns the current mask for the UARTPEINTR + /// interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write + /// of 0 clears the mask. + PEIM: u1, + /// Break error interrupt mask. A read returns the current mask for the UARTBEINTR + /// interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write + /// of 0 clears the mask. + BEIM: u1, + /// Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR + /// interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write + /// of 0 clears the mask. + OEIM: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x38); + + /// address: 0x4003403c + /// Raw Interrupt Status Register, UARTRIS + pub const UARTRIS = @intToPtr(*volatile Mmio(32, packed struct { + /// nUARTRI modem interrupt status. Returns the raw interrupt state of the + /// UARTRIINTR interrupt. + RIRMIS: u1, + /// nUARTCTS modem interrupt status. Returns the raw interrupt state of the + /// UARTCTSINTR interrupt. + CTSRMIS: u1, + /// nUARTDCD modem interrupt status. Returns the raw interrupt state of the + /// UARTDCDINTR interrupt. + DCDRMIS: u1, + /// nUARTDSR modem interrupt status. Returns the raw interrupt state of the + /// UARTDSRINTR interrupt. + DSRRMIS: u1, + /// Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR + /// interrupt. + RXRIS: u1, + /// Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR + /// interrupt. + TXRIS: u1, + /// Receive timeout interrupt status. Returns the raw interrupt state of the + /// UARTRTINTR interrupt. a + RTRIS: u1, + /// Framing error interrupt status. Returns the raw interrupt state of the + /// UARTFEINTR interrupt. + FERIS: u1, + /// Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR + /// interrupt. + PERIS: u1, + /// Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR + /// interrupt. + BERIS: u1, + /// Overrun error interrupt status. Returns the raw interrupt state of the + /// UARTOEINTR interrupt. + OERIS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x3c); + + /// address: 0x40034040 + /// Masked Interrupt Status Register, UARTMIS + pub const UARTMIS = @intToPtr(*volatile Mmio(32, packed struct { + /// nUARTRI modem masked interrupt status. Returns the masked interrupt state of the + /// UARTRIINTR interrupt. + RIMMIS: u1, + /// nUARTCTS modem masked interrupt status. Returns the masked interrupt state of + /// the UARTCTSINTR interrupt. + CTSMMIS: u1, + /// nUARTDCD modem masked interrupt status. Returns the masked interrupt state of + /// the UARTDCDINTR interrupt. + DCDMMIS: u1, + /// nUARTDSR modem masked interrupt status. Returns the masked interrupt state of + /// the UARTDSRINTR interrupt. + DSRMMIS: u1, + /// Receive masked interrupt status. Returns the masked interrupt state of the + /// UARTRXINTR interrupt. + RXMIS: u1, + /// Transmit masked interrupt status. Returns the masked interrupt state of the + /// UARTTXINTR interrupt. + TXMIS: u1, + /// Receive timeout masked interrupt status. Returns the masked interrupt state of + /// the UARTRTINTR interrupt. + RTMIS: u1, + /// Framing error masked interrupt status. Returns the masked interrupt state of the + /// UARTFEINTR interrupt. + FEMIS: u1, + /// Parity error masked interrupt status. Returns the masked interrupt state of the + /// UARTPEINTR interrupt. + PEMIS: u1, + /// Break error masked interrupt status. Returns the masked interrupt state of the + /// UARTBEINTR interrupt. + BEMIS: u1, + /// Overrun error masked interrupt status. Returns the masked interrupt state of the + /// UARTOEINTR interrupt. + OEMIS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x40); + + /// address: 0x40034044 + /// Interrupt Clear Register, UARTICR + pub const UARTICR = @intToPtr(*volatile Mmio(32, packed struct { + /// nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. + RIMIC: u1, + /// nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. + CTSMIC: u1, + /// nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. + DCDMIC: u1, + /// nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. + DSRMIC: u1, + /// Receive interrupt clear. Clears the UARTRXINTR interrupt. + RXIC: u1, + /// Transmit interrupt clear. Clears the UARTTXINTR interrupt. + TXIC: u1, + /// Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. + RTIC: u1, + /// Framing error interrupt clear. Clears the UARTFEINTR interrupt. + FEIC: u1, + /// Parity error interrupt clear. Clears the UARTPEINTR interrupt. + PEIC: u1, + /// Break error interrupt clear. Clears the UARTBEINTR interrupt. + BEIC: u1, + /// Overrun error interrupt clear. Clears the UARTOEINTR interrupt. + OEIC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x44); + + /// address: 0x40034048 + /// DMA Control Register, UARTDMACR + pub const UARTDMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is + /// enabled. + RXDMAE: u1, + /// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is + /// enabled. + TXDMAE: u1, + /// DMA on error. If this bit is set to 1, the DMA receive request outputs, + /// UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is + /// asserted. + DMAONERR: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + }), base_address + 0x48); + + /// address: 0x40034fe0 + /// UARTPeriphID0 Register + pub const UARTPERIPHID0 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x11 + PARTNUMBER0: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe0); + + /// address: 0x40034fe4 + /// UARTPeriphID1 Register + pub const UARTPERIPHID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x0 + PARTNUMBER1: u4, + /// These bits read back as 0x1 + DESIGNER0: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe4); + + /// address: 0x40034fe8 + /// UARTPeriphID2 Register + pub const UARTPERIPHID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x4 + DESIGNER1: u4, + /// This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 + /// 0x2 r1p5 0x3 + REVISION: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe8); + + /// address: 0x40034fec + /// UARTPeriphID3 Register + pub const UARTPERIPHID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x00 + CONFIGURATION: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfec); + + /// address: 0x40034ff0 + /// UARTPCellID0 Register + pub const UARTPCELLID0 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff0); + + /// address: 0x40034ff4 + /// UARTPCellID1 Register + pub const UARTPCELLID1 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff4); + + /// address: 0x40034ff8 + /// UARTPCellID2 Register + pub const UARTPCELLID2 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff8); + + /// address: 0x40034ffc + /// UARTPCellID3 Register + pub const UARTPCELLID3 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xffc); + }; + pub const UART1 = struct { + pub const base_address = 0x40038000; + + /// address: 0x40038000 + /// Data Register, UARTDR + pub const UARTDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive (read) data character. Transmit (write) data character. + DATA: u8, + /// Framing error. When set to 1, it indicates that the received character did not + /// have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is + /// associated with the character at the top of the FIFO. + FE: u1, + /// Parity error. When set to 1, it indicates that the parity of the received data + /// character does not match the parity that the EPS and SPS bits in the Line + /// Control Register, UARTLCR_H. In FIFO mode, this error is associated with the + /// character at the top of the FIFO. + PE: u1, + /// Break error. This bit is set to 1 if a break condition was detected, indicating + /// that the received data input was held LOW for longer than a full-word + /// transmission time (defined as start, data, parity and stop bits). In FIFO mode, + /// this error is associated with the character at the top of the FIFO. When a break + /// occurs, only one 0 character is loaded into the FIFO. The next character is only + /// enabled after the receive data input goes to a 1 (marking state), and the next + /// valid start bit is received. + BE: u1, + /// Overrun error. This bit is set to 1 if data is received and the receive FIFO is + /// already full. This is cleared to 0 once there is an empty space in the FIFO and + /// a new character can be written to it. + OE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40038004 + /// Receive Status Register/Error Clear Register, UARTRSR/UARTECR + pub const UARTRSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Framing error. When set to 1, it indicates that the received character did not + /// have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a + /// write to UARTECR. In FIFO mode, this error is associated with the character at + /// the top of the FIFO. + FE: u1, + /// Parity error. When set to 1, it indicates that the parity of the received data + /// character does not match the parity that the EPS and SPS bits in the Line + /// Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In + /// FIFO mode, this error is associated with the character at the top of the FIFO. + PE: u1, + /// Break error. This bit is set to 1 if a break condition was detected, indicating + /// that the received data input was held LOW for longer than a full-word + /// transmission time (defined as start, data, parity, and stop bits). This bit is + /// cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated + /// with the character at the top of the FIFO. When a break occurs, only one 0 + /// character is loaded into the FIFO. The next character is only enabled after the + /// receive data input goes to a 1 (marking state) and the next valid start bit is + /// received. + BE: u1, + /// Overrun error. This bit is set to 1 if data is received and the FIFO is already + /// full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain + /// valid because no more data is written when the FIFO is full, only the contents + /// of the shift register are overwritten. The CPU must now read the data, to empty + /// the FIFO. + OE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40038018 + /// Flag Register, UARTFR + pub const UARTFR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, + /// modem status input. That is, the bit is 1 when nUARTCTS is LOW. + CTS: u1, + /// Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, + /// modem status input. That is, the bit is 1 when nUARTDSR is LOW. + DSR: u1, + /// Data carrier detect. This bit is the complement of the UART data carrier detect, + /// nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW. + DCD: u1, + /// UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit + /// remains set until the complete byte, including all the stop bits, has been sent + /// from the shift register. This bit is set as soon as the transmit FIFO becomes + /// non-empty, regardless of whether the UART is enabled or not. + BUSY: u1, + /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit + /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the + /// receive holding register is empty. If the FIFO is enabled, the RXFE bit is set + /// when the receive FIFO is empty. + RXFE: u1, + /// Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit + /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the + /// transmit holding register is full. If the FIFO is enabled, the TXFF bit is set + /// when the transmit FIFO is full. + TXFF: u1, + /// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit + /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the + /// receive holding register is full. If the FIFO is enabled, the RXFF bit is set + /// when the receive FIFO is full. + RXFF: u1, + /// Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit + /// in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is + /// set when the transmit holding register is empty. If the FIFO is enabled, the + /// TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if + /// there is data in the transmit shift register. + TXFE: u1, + /// Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, + /// modem status input. That is, the bit is 1 when nUARTRI is LOW. + RI: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + }), base_address + 0x18); + + /// address: 0x40038020 + /// IrDA Low-Power Counter Register, UARTILPR + pub const UARTILPR = @intToPtr(*volatile Mmio(32, packed struct { + /// 8-bit low-power divisor value. These bits are cleared to 0 at reset. + ILPDVSR: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x20); + + /// address: 0x40038024 + /// Integer Baud Rate Register, UARTIBRD + pub const UARTIBRD = @intToPtr(*volatile Mmio(32, packed struct { + /// The integer baud rate divisor. These bits are cleared to 0 on reset. + BAUD_DIVINT: u16, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x24); + + /// address: 0x40038028 + /// Fractional Baud Rate Register, UARTFBRD + pub const UARTFBRD = @intToPtr(*volatile Mmio(32, packed struct { + /// The fractional baud rate divisor. These bits are cleared to 0 on reset. + BAUD_DIVFRAC: u6, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + }), base_address + 0x28); + + /// address: 0x4003802c + /// Line Control Register, UARTLCR_H + pub const UARTLCR_H = @intToPtr(*volatile Mmio(32, packed struct { + /// Send break. If this bit is set to 1, a low-level is continually output on the + /// UARTTXD output, after completing transmission of the current character. For the + /// proper execution of the break command, the software must set this bit for at + /// least two complete frames. For normal use, this bit must be cleared to 0. + BRK: u1, + /// Parity enable: 0 = parity is disabled and no parity bit added to the data frame + /// 1 = parity checking and generation is enabled. + PEN: u1, + /// Even parity select. Controls the type of parity the UART uses during + /// transmission and reception: 0 = odd parity. The UART generates or checks for an + /// odd number of 1s in the data and parity bits. 1 = even parity. The UART + /// generates or checks for an even number of 1s in the data and parity bits. This + /// bit has no effect when the PEN bit disables parity checking and generation. + EPS: u1, + /// Two stop bits select. If this bit is set to 1, two stop bits are transmitted at + /// the end of the frame. The receive logic does not check for two stop bits being + /// received. + STP2: u1, + /// Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become + /// 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled + /// (FIFO mode). + FEN: u1, + /// Word length. These bits indicate the number of data bits transmitted or received + /// in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits. + WLEN: u2, + /// Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit + /// is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 + /// then the parity bit is transmitted and checked as a 0. This bit has no effect + /// when the PEN bit disables parity checking and generation. + SPS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x2c); + + /// address: 0x40038030 + /// Control Register, UARTCR + pub const UARTCR = @intToPtr(*volatile Mmio(32, packed struct { + /// UART enable: 0 = UART is disabled. If the UART is disabled in the middle of + /// transmission or reception, it completes the current character before stopping. 1 + /// = the UART is enabled. Data transmission and reception occurs for either UART + /// signals or SIR signals depending on the setting of the SIREN bit. + UARTEN: u1, + /// SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse + /// generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC + /// is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD + /// remains HIGH, in the marking state. Signal transitions on UARTRXD or modem + /// status inputs have no effect. This bit has no effect if the UARTEN bit disables + /// the UART. + SIREN: u1, + /// SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is + /// cleared to 0, low-level bits are transmitted as an active high pulse with a + /// width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are + /// transmitted with a pulse width that is 3 times the period of the IrLPBaud16 + /// input signal, regardless of the selected bit rate. Setting this bit uses less + /// power, but might reduce transmission distances. + SIRLP: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the + /// SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT + /// path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test + /// register must be set to 1 to override the normal half-duplex SIR operation. This + /// must be the requirement for accessing the test registers during normal + /// operation, and SIRTEST must be cleared to 0 when loopback testing is finished. + /// This feature reduces the amount of external coupling required during system + /// test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path + /// is fed through to the UARTRXD path. In either SIR mode or UART mode, when this + /// bit is set, the modem outputs are also fed through to the modem inputs. This bit + /// is cleared to 0 on reset, to disable loopback. + LBE: u1, + /// Transmit enable. If this bit is set to 1, the transmit section of the UART is + /// enabled. Data transmission occurs for either UART signals, or SIR signals + /// depending on the setting of the SIREN bit. When the UART is disabled in the + /// middle of transmission, it completes the current character before stopping. + TXE: u1, + /// Receive enable. If this bit is set to 1, the receive section of the UART is + /// enabled. Data reception occurs for either UART signals or SIR signals depending + /// on the setting of the SIREN bit. When the UART is disabled in the middle of + /// reception, it completes the current character before stopping. + RXE: u1, + /// Data transmit ready. This bit is the complement of the UART data transmit ready, + /// nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then + /// nUARTDTR is LOW. + DTR: u1, + /// Request to send. This bit is the complement of the UART request to send, + /// nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then + /// nUARTRTS is LOW. + RTS: u1, + /// This bit is the complement of the UART Out1 (nUARTOut1) modem status output. + /// That is, when the bit is programmed to a 1 the output is 0. For DTE this can be + /// used as Data Carrier Detect (DCD). + OUT1: u1, + /// This bit is the complement of the UART Out2 (nUARTOut2) modem status output. + /// That is, when the bit is programmed to a 1, the output is 0. For DTE this can be + /// used as Ring Indicator (RI). + OUT2: u1, + /// RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow + /// control is enabled. Data is only requested when there is space in the receive + /// FIFO for it to be received. + RTSEN: u1, + /// CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow + /// control is enabled. Data is only transmitted when the nUARTCTS signal is + /// asserted. + CTSEN: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x30); + + /// address: 0x40038034 + /// Interrupt FIFO Level Select Register, UARTIFLS + pub const UARTIFLS = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit interrupt FIFO level select. The trigger points for the transmit + /// interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = + /// Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full + /// b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 + /// full b101-b111 = reserved. + TXIFLSEL: u3, + /// Receive interrupt FIFO level select. The trigger points for the receive + /// interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = + /// Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full + /// b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 + /// full b101-b111 = reserved. + RXIFLSEL: u3, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + }), base_address + 0x34); + + /// address: 0x40038038 + /// Interrupt Mask Set/Clear Register, UARTIMSC + pub const UARTIMSC = @intToPtr(*volatile Mmio(32, packed struct { + /// nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR + /// interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write + /// of 0 clears the mask. + RIMIM: u1, + /// nUARTCTS modem interrupt mask. A read returns the current mask for the + /// UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is + /// set. A write of 0 clears the mask. + CTSMIM: u1, + /// nUARTDCD modem interrupt mask. A read returns the current mask for the + /// UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is + /// set. A write of 0 clears the mask. + DCDMIM: u1, + /// nUARTDSR modem interrupt mask. A read returns the current mask for the + /// UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is + /// set. A write of 0 clears the mask. + DSRMIM: u1, + /// Receive interrupt mask. A read returns the current mask for the UARTRXINTR + /// interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write + /// of 0 clears the mask. + RXIM: u1, + /// Transmit interrupt mask. A read returns the current mask for the UARTTXINTR + /// interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write + /// of 0 clears the mask. + TXIM: u1, + /// Receive timeout interrupt mask. A read returns the current mask for the + /// UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is + /// set. A write of 0 clears the mask. + RTIM: u1, + /// Framing error interrupt mask. A read returns the current mask for the UARTFEINTR + /// interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write + /// of 0 clears the mask. + FEIM: u1, + /// Parity error interrupt mask. A read returns the current mask for the UARTPEINTR + /// interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write + /// of 0 clears the mask. + PEIM: u1, + /// Break error interrupt mask. A read returns the current mask for the UARTBEINTR + /// interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write + /// of 0 clears the mask. + BEIM: u1, + /// Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR + /// interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write + /// of 0 clears the mask. + OEIM: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x38); + + /// address: 0x4003803c + /// Raw Interrupt Status Register, UARTRIS + pub const UARTRIS = @intToPtr(*volatile Mmio(32, packed struct { + /// nUARTRI modem interrupt status. Returns the raw interrupt state of the + /// UARTRIINTR interrupt. + RIRMIS: u1, + /// nUARTCTS modem interrupt status. Returns the raw interrupt state of the + /// UARTCTSINTR interrupt. + CTSRMIS: u1, + /// nUARTDCD modem interrupt status. Returns the raw interrupt state of the + /// UARTDCDINTR interrupt. + DCDRMIS: u1, + /// nUARTDSR modem interrupt status. Returns the raw interrupt state of the + /// UARTDSRINTR interrupt. + DSRRMIS: u1, + /// Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR + /// interrupt. + RXRIS: u1, + /// Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR + /// interrupt. + TXRIS: u1, + /// Receive timeout interrupt status. Returns the raw interrupt state of the + /// UARTRTINTR interrupt. a + RTRIS: u1, + /// Framing error interrupt status. Returns the raw interrupt state of the + /// UARTFEINTR interrupt. + FERIS: u1, + /// Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR + /// interrupt. + PERIS: u1, + /// Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR + /// interrupt. + BERIS: u1, + /// Overrun error interrupt status. Returns the raw interrupt state of the + /// UARTOEINTR interrupt. + OERIS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x3c); + + /// address: 0x40038040 + /// Masked Interrupt Status Register, UARTMIS + pub const UARTMIS = @intToPtr(*volatile Mmio(32, packed struct { + /// nUARTRI modem masked interrupt status. Returns the masked interrupt state of the + /// UARTRIINTR interrupt. + RIMMIS: u1, + /// nUARTCTS modem masked interrupt status. Returns the masked interrupt state of + /// the UARTCTSINTR interrupt. + CTSMMIS: u1, + /// nUARTDCD modem masked interrupt status. Returns the masked interrupt state of + /// the UARTDCDINTR interrupt. + DCDMMIS: u1, + /// nUARTDSR modem masked interrupt status. Returns the masked interrupt state of + /// the UARTDSRINTR interrupt. + DSRMMIS: u1, + /// Receive masked interrupt status. Returns the masked interrupt state of the + /// UARTRXINTR interrupt. + RXMIS: u1, + /// Transmit masked interrupt status. Returns the masked interrupt state of the + /// UARTTXINTR interrupt. + TXMIS: u1, + /// Receive timeout masked interrupt status. Returns the masked interrupt state of + /// the UARTRTINTR interrupt. + RTMIS: u1, + /// Framing error masked interrupt status. Returns the masked interrupt state of the + /// UARTFEINTR interrupt. + FEMIS: u1, + /// Parity error masked interrupt status. Returns the masked interrupt state of the + /// UARTPEINTR interrupt. + PEMIS: u1, + /// Break error masked interrupt status. Returns the masked interrupt state of the + /// UARTBEINTR interrupt. + BEMIS: u1, + /// Overrun error masked interrupt status. Returns the masked interrupt state of the + /// UARTOEINTR interrupt. + OEMIS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x40); + + /// address: 0x40038044 + /// Interrupt Clear Register, UARTICR + pub const UARTICR = @intToPtr(*volatile Mmio(32, packed struct { + /// nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt. + RIMIC: u1, + /// nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt. + CTSMIC: u1, + /// nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt. + DCDMIC: u1, + /// nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt. + DSRMIC: u1, + /// Receive interrupt clear. Clears the UARTRXINTR interrupt. + RXIC: u1, + /// Transmit interrupt clear. Clears the UARTTXINTR interrupt. + TXIC: u1, + /// Receive timeout interrupt clear. Clears the UARTRTINTR interrupt. + RTIC: u1, + /// Framing error interrupt clear. Clears the UARTFEINTR interrupt. + FEIC: u1, + /// Parity error interrupt clear. Clears the UARTPEINTR interrupt. + PEIC: u1, + /// Break error interrupt clear. Clears the UARTBEINTR interrupt. + BEIC: u1, + /// Overrun error interrupt clear. Clears the UARTOEINTR interrupt. + OEIC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x44); + + /// address: 0x40038048 + /// DMA Control Register, UARTDMACR + pub const UARTDMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is + /// enabled. + RXDMAE: u1, + /// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is + /// enabled. + TXDMAE: u1, + /// DMA on error. If this bit is set to 1, the DMA receive request outputs, + /// UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is + /// asserted. + DMAONERR: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + }), base_address + 0x48); + + /// address: 0x40038fe0 + /// UARTPeriphID0 Register + pub const UARTPERIPHID0 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x11 + PARTNUMBER0: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe0); + + /// address: 0x40038fe4 + /// UARTPeriphID1 Register + pub const UARTPERIPHID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x0 + PARTNUMBER1: u4, + /// These bits read back as 0x1 + DESIGNER0: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe4); + + /// address: 0x40038fe8 + /// UARTPeriphID2 Register + pub const UARTPERIPHID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x4 + DESIGNER1: u4, + /// This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 + /// 0x2 r1p5 0x3 + REVISION: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe8); + + /// address: 0x40038fec + /// UARTPeriphID3 Register + pub const UARTPERIPHID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x00 + CONFIGURATION: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfec); + + /// address: 0x40038ff0 + /// UARTPCellID0 Register + pub const UARTPCELLID0 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff0); + + /// address: 0x40038ff4 + /// UARTPCellID1 Register + pub const UARTPCELLID1 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff4); + + /// address: 0x40038ff8 + /// UARTPCellID2 Register + pub const UARTPCELLID2 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff8); + + /// address: 0x40038ffc + /// UARTPCellID3 Register + pub const UARTPCELLID3 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xffc); + }; + pub const SPI0 = struct { + pub const base_address = 0x4003c000; + pub const version = "1"; + + /// address: 0x4003c000 + /// Control register 0, SSPCR0 on page 3-4 + pub const SSPCR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined + /// operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. + /// 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit + /// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. + /// 1110 15-bit data. 1111 16-bit data. + DSS: u4, + /// Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame + /// format. 10 National Microwire frame format. 11 Reserved, undefined operation. + FRF: u2, + /// SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola + /// SPI frame format on page 2-10. + SPO: u1, + /// SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI + /// frame format on page 2-10. + SPH: u1, + /// Serial clock rate. The value SCR is used to generate the transmit and receive + /// bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where + /// CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and + /// SCR is a value from 0-255. + SCR: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x0); + + /// address: 0x4003c004 + /// Control register 1, SSPCR1 on page 3-5 + pub const SSPCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit + /// serial shifter is connected to input of receive serial shifter internally. + LBM: u1, + /// Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation + /// enabled. + SSE: u1, + /// Master or slave mode select. This bit can be modified only when the PrimeCell + /// SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device + /// configured as slave. + MS: u1, + /// Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In + /// multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast + /// a message to all slaves in the system while ensuring that only one slave drives + /// data onto its serial output line. In such systems the RXD lines from multiple + /// slaves could be tied together. To operate in such systems, the SOD bit can be + /// set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP + /// can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD + /// output in slave mode. + SOD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x4); + + /// address: 0x4003c008 + /// Data register, SSPDR on page 3-6 + pub const SSPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must + /// right-justify data when the PrimeCell SSP is programmed for a data size that is + /// less than 16 bits. Unused bits at the top are ignored by transmit logic. The + /// receive logic automatically right-justifies. + DATA: u16, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x8); + + /// address: 0x4003c00c + /// Status register, SSPSR on page 3-7 + pub const SSPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. + TFE: u1, + /// Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not + /// full. + TNF: u1, + /// Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not + /// empty. + RNE: u1, + /// Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. + RFF: u1, + /// PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting + /// and/or receiving a frame or the transmit FIFO is not empty. + BSY: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + }), base_address + 0xc); + + /// address: 0x4003c010 + /// Clock prescale register, SSPCPSR on page 3-8 + pub const SSPCPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock prescale divisor. Must be an even number from 2-254, depending on the + /// frequency of SSPCLK. The least significant bit always returns zero on reads. + CPSDVSR: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x10); + + /// address: 0x4003c014 + /// Interrupt mask set or clear register, SSPIMSC on page 3-9 + pub const SSPIMSC = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive overrun interrupt mask: 0 Receive FIFO written to while full condition + /// interrupt is masked. 1 Receive FIFO written to while full condition interrupt is + /// not masked. + RORIM: u1, + /// Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to + /// timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior + /// to timeout period interrupt is not masked. + RTIM: u1, + /// Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition + /// interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not + /// masked. + RXIM: u1, + /// Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition + /// interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is + /// not masked. + TXIM: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x14); + + /// address: 0x4003c018 + /// Raw interrupt status register, SSPRIS on page 3-10 + pub const SSPRIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + RORRIS: u1, + /// Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + RTRIS: u1, + /// Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + RXRIS: u1, + /// Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + TXRIS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x18); + + /// address: 0x4003c01c + /// Masked interrupt status register, SSPMIS on page 3-11 + pub const SSPMIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Gives the receive over run masked interrupt status, after masking, of the + /// SSPRORINTR interrupt + RORMIS: u1, + /// Gives the receive timeout masked interrupt state, after masking, of the + /// SSPRTINTR interrupt + RTMIS: u1, + /// Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR + /// interrupt + RXMIS: u1, + /// Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR + /// interrupt + TXMIS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x1c); + + /// address: 0x4003c020 + /// Interrupt clear register, SSPICR on page 3-11 + pub const SSPICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clears the SSPRORINTR interrupt + RORIC: u1, + /// Clears the SSPRTINTR interrupt + RTIC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x20); + + /// address: 0x4003c024 + /// DMA control register, SSPDMACR on page 3-12 + pub const SSPDMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is + /// enabled. + RXDMAE: u1, + /// Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is + /// enabled. + TXDMAE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x24); + + /// address: 0x4003cfe0 + /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + pub const SSPPERIPHID0 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x22 + PARTNUMBER0: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe0); + + /// address: 0x4003cfe4 + /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + pub const SSPPERIPHID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x0 + PARTNUMBER1: u4, + /// These bits read back as 0x1 + DESIGNER0: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe4); + + /// address: 0x4003cfe8 + /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + pub const SSPPERIPHID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x4 + DESIGNER1: u4, + /// These bits return the peripheral revision + REVISION: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe8); + + /// address: 0x4003cfec + /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + pub const SSPPERIPHID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x00 + CONFIGURATION: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfec); + + /// address: 0x4003cff0 + /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + pub const SSPPCELLID0 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff0); + + /// address: 0x4003cff4 + /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + pub const SSPPCELLID1 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff4); + + /// address: 0x4003cff8 + /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + pub const SSPPCELLID2 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff8); + + /// address: 0x4003cffc + /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + pub const SSPPCELLID3 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xffc); + }; + pub const SPI1 = struct { + pub const base_address = 0x40040000; + + /// address: 0x40040000 + /// Control register 0, SSPCR0 on page 3-4 + pub const SSPCR0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined + /// operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. + /// 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit + /// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. + /// 1110 15-bit data. 1111 16-bit data. + DSS: u4, + /// Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame + /// format. 10 National Microwire frame format. 11 Reserved, undefined operation. + FRF: u2, + /// SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola + /// SPI frame format on page 2-10. + SPO: u1, + /// SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI + /// frame format on page 2-10. + SPH: u1, + /// Serial clock rate. The value SCR is used to generate the transmit and receive + /// bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where + /// CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and + /// SCR is a value from 0-255. + SCR: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40040004 + /// Control register 1, SSPCR1 on page 3-5 + pub const SSPCR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit + /// serial shifter is connected to input of receive serial shifter internally. + LBM: u1, + /// Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation + /// enabled. + SSE: u1, + /// Master or slave mode select. This bit can be modified only when the PrimeCell + /// SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device + /// configured as slave. + MS: u1, + /// Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In + /// multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast + /// a message to all slaves in the system while ensuring that only one slave drives + /// data onto its serial output line. In such systems the RXD lines from multiple + /// slaves could be tied together. To operate in such systems, the SOD bit can be + /// set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP + /// can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD + /// output in slave mode. + SOD: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40040008 + /// Data register, SSPDR on page 3-6 + pub const SSPDR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must + /// right-justify data when the PrimeCell SSP is programmed for a data size that is + /// less than 16 bits. Unused bits at the top are ignored by transmit logic. The + /// receive logic automatically right-justifies. + DATA: u16, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x8); + + /// address: 0x4004000c + /// Status register, SSPSR on page 3-7 + pub const SSPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty. + TFE: u1, + /// Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not + /// full. + TNF: u1, + /// Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not + /// empty. + RNE: u1, + /// Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full. + RFF: u1, + /// PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting + /// and/or receiving a frame or the transmit FIFO is not empty. + BSY: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + }), base_address + 0xc); + + /// address: 0x40040010 + /// Clock prescale register, SSPCPSR on page 3-8 + pub const SSPCPSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clock prescale divisor. Must be an even number from 2-254, depending on the + /// frequency of SSPCLK. The least significant bit always returns zero on reads. + CPSDVSR: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x10); + + /// address: 0x40040014 + /// Interrupt mask set or clear register, SSPIMSC on page 3-9 + pub const SSPIMSC = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive overrun interrupt mask: 0 Receive FIFO written to while full condition + /// interrupt is masked. 1 Receive FIFO written to while full condition interrupt is + /// not masked. + RORIM: u1, + /// Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to + /// timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior + /// to timeout period interrupt is not masked. + RTIM: u1, + /// Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition + /// interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not + /// masked. + RXIM: u1, + /// Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition + /// interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is + /// not masked. + TXIM: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x14); + + /// address: 0x40040018 + /// Raw interrupt status register, SSPRIS on page 3-10 + pub const SSPRIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt + RORRIS: u1, + /// Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt + RTRIS: u1, + /// Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt + RXRIS: u1, + /// Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt + TXRIS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x18); + + /// address: 0x4004001c + /// Masked interrupt status register, SSPMIS on page 3-11 + pub const SSPMIS = @intToPtr(*volatile Mmio(32, packed struct { + /// Gives the receive over run masked interrupt status, after masking, of the + /// SSPRORINTR interrupt + RORMIS: u1, + /// Gives the receive timeout masked interrupt state, after masking, of the + /// SSPRTINTR interrupt + RTMIS: u1, + /// Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR + /// interrupt + RXMIS: u1, + /// Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR + /// interrupt + TXMIS: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x1c); + + /// address: 0x40040020 + /// Interrupt clear register, SSPICR on page 3-11 + pub const SSPICR = @intToPtr(*volatile Mmio(32, packed struct { + /// Clears the SSPRORINTR interrupt + RORIC: u1, + /// Clears the SSPRTINTR interrupt + RTIC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x20); + + /// address: 0x40040024 + /// DMA control register, SSPDMACR on page 3-12 + pub const SSPDMACR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is + /// enabled. + RXDMAE: u1, + /// Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is + /// enabled. + TXDMAE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x24); + + /// address: 0x40040fe0 + /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + pub const SSPPERIPHID0 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x22 + PARTNUMBER0: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe0); + + /// address: 0x40040fe4 + /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + pub const SSPPERIPHID1 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x0 + PARTNUMBER1: u4, + /// These bits read back as 0x1 + DESIGNER0: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe4); + + /// address: 0x40040fe8 + /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + pub const SSPPERIPHID2 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x4 + DESIGNER1: u4, + /// These bits return the peripheral revision + REVISION: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfe8); + + /// address: 0x40040fec + /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13 + pub const SSPPERIPHID3 = @intToPtr(*volatile Mmio(32, packed struct { + /// These bits read back as 0x00 + CONFIGURATION: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xfec); + + /// address: 0x40040ff0 + /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + pub const SSPPCELLID0 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff0); + + /// address: 0x40040ff4 + /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + pub const SSPPCELLID1 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff4); + + /// address: 0x40040ff8 + /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + pub const SSPPCELLID2 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff8); + + /// address: 0x40040ffc + /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16 + pub const SSPPCELLID3 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xffc); + }; + + /// DW_apb_i2c address block\n\n + /// List of configuration constants for the Synopsys I2C hardware (you may see + /// references to these in I2C register header; these are *fixed* values, set at + /// hardware design time):\n\n + /// IC_ULTRA_FAST_MODE ................ 0x0\n + /// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n + /// IC_UFM_SCL_LOW_COUNT .............. 0x0008\n + /// IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n + /// IC_TX_TL .......................... 0x0\n + /// IC_TX_CMD_BLOCK ................... 0x1\n + /// IC_HAS_DMA ........................ 0x1\n + /// IC_HAS_ASYNC_FIFO ................. 0x0\n + /// IC_SMBUS_ARP ...................... 0x0\n + /// IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n + /// IC_INTR_IO ........................ 0x1\n + /// IC_MASTER_MODE .................... 0x1\n + /// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n + /// IC_INTR_POL ....................... 0x1\n + /// IC_OPTIONAL_SAR ................... 0x0\n + /// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n + /// IC_DEFAULT_SLAVE_ADDR ............. 0x055\n + /// IC_DEFAULT_HS_SPKLEN .............. 0x1\n + /// IC_FS_SCL_HIGH_COUNT .............. 0x0006\n + /// IC_HS_SCL_LOW_COUNT ............... 0x0008\n + /// IC_DEVICE_ID_VALUE ................ 0x0\n + /// IC_10BITADDR_MASTER ............... 0x0\n + /// IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n + /// IC_DEFAULT_FS_SPKLEN .............. 0x7\n + /// IC_ADD_ENCODED_PARAMS ............. 0x0\n + /// IC_DEFAULT_SDA_HOLD ............... 0x000001\n + /// IC_DEFAULT_SDA_SETUP .............. 0x64\n + /// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n + /// IC_CLOCK_PERIOD ................... 100\n + /// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n + /// IC_RESTART_EN ..................... 0x1\n + /// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n + /// IC_BUS_CLEAR_FEATURE .............. 0x0\n + /// IC_CAP_LOADING .................... 100\n + /// IC_FS_SCL_LOW_COUNT ............... 0x000d\n + /// APB_DATA_WIDTH .................... 32\n + /// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n + /// IC_SLV_DATA_NACK_ONLY ............. 0x1\n + /// IC_10BITADDR_SLAVE ................ 0x0\n + /// IC_CLK_TYPE ....................... 0x0\n + /// IC_SMBUS_UDID_MSB ................. 0x0\n + /// IC_SMBUS_SUSPEND_ALERT ............ 0x0\n + /// IC_HS_SCL_HIGH_COUNT .............. 0x0006\n + /// IC_SLV_RESTART_DET_EN ............. 0x1\n + /// IC_SMBUS .......................... 0x0\n + /// IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n + /// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n + /// IC_USE_COUNTS ..................... 0x0\n + /// IC_RX_BUFFER_DEPTH ................ 16\n + /// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n + /// IC_RX_FULL_HLD_BUS_EN ............. 0x1\n + /// IC_SLAVE_DISABLE .................. 0x1\n + /// IC_RX_TL .......................... 0x0\n + /// IC_DEVICE_ID ...................... 0x0\n + /// IC_HC_COUNT_VALUES ................ 0x0\n + /// I2C_DYNAMIC_TAR_UPDATE ............ 0\n + /// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n + /// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n + /// IC_HS_MASTER_CODE ................. 0x1\n + /// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n + /// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n + /// IC_SS_SCL_HIGH_COUNT .............. 0x0028\n + /// IC_SS_SCL_LOW_COUNT ............... 0x002f\n + /// IC_MAX_SPEED_MODE ................. 0x2\n + /// IC_STAT_FOR_CLK_STRETCH ........... 0x0\n + /// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n + /// IC_DEFAULT_UFM_SPKLEN ............. 0x1\n + /// IC_TX_BUFFER_DEPTH ................ 16 + pub const I2C0 = struct { + pub const base_address = 0x40044000; + pub const version = "1"; + + /// address: 0x40044000 + /// I2C Control Register. This register can be written only when the DW_apb_i2c is + /// disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes + /// at other times have no effect.\n\n + /// Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read + /// only - bit 17 is read only - bits 18 and 19 are read only. + pub const IC_CON = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit controls whether the DW_apb_i2c master is enabled.\n\n + /// NOTE: Software should ensure that if this bit is written with '1' then bit 6 + /// should also be written with a '1'. + MASTER_MODE: u1, + /// These bits control at which speed the DW_apb_i2c operates; its setting is + /// relevant only if one is operating the DW_apb_i2c in master mode. Hardware + /// protects against illegal values being programmed by software. These bits must be + /// programmed appropriately for slave mode also, as it is used to capture correct + /// value of spike filter as per the speed mode.\n\n + /// This register should be programmed only with a value in the range of 1 to + /// IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of + /// IC_MAX_SPEED_MODE.\n\n + /// 1: standard mode (100 kbit/s)\n\n + /// 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n + /// 3: high speed mode (3.4 Mbit/s)\n\n + /// Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + SPEED: u2, + /// When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- + /// or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions + /// that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of + /// the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c + /// responds to only 10-bit addressing transfers that match the full 10 bits of the + /// IC_SAR register. + IC_10BITADDR_SLAVE: u1, + /// Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing + /// mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + IC_10BITADDR_MASTER: u1, + /// Determines whether RESTART conditions may be sent when acting as a master. Some + /// older slaves do not support handling RESTART conditions; however, RESTART + /// conditions are used in several DW_apb_i2c operations. When RESTART is disabled, + /// the master is prohibited from performing the following functions: - Sending a + /// START BYTE - Performing any high-speed mode operation - High-speed mode + /// operation - Performing direction changes in combined format mode - Performing a + /// read operation with a 10-bit address By replacing RESTART condition followed by + /// a STOP and a subsequent START condition, split operations are broken down into + /// multiple DW_apb_i2c transfers. If the above operations are performed, it will + /// result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n + /// Reset value: ENABLED + IC_RESTART_EN: u1, + /// This bit controls whether I2C has its slave disabled, which means once the + /// presetn signal is applied, then this bit is set and the slave is disabled.\n\n + /// If this bit is set (slave is disabled), DW_apb_i2c functions only as a master + /// and does not perform any action that requires a slave.\n\n + /// NOTE: Software should ensure that if this bit is written with 0, then bit 0 + /// should also be written with a 0. + IC_SLAVE_DISABLE: u1, + /// In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. + /// - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset + /// value: 0x0\n\n + /// NOTE: During a general call address, this slave does not issue the STOP_DET + /// interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the + /// general call address by generating ACK. The STOP_DET interrupt is generated only + /// when the transmitted address matches the slave address (SAR). + STOP_DET_IFADDRESSED: u1, + /// This bit controls the generation of the TX_EMPTY interrupt, as described in the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0. + TX_EMPTY_CTRL: u1, + /// This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is + /// physically full to its RX_BUFFER_DEPTH, as described in the + /// IC_RX_FULL_HLD_BUS_EN parameter.\n\n + /// Reset value: 0x0. + RX_FIFO_FULL_HLD_CTRL: u1, + /// Master issues the STOP_DET interrupt irrespective of whether master is active or + /// not + STOP_DET_IF_MASTER_ACTIVE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40044004 + /// I2C Target Address Register\n\n + /// This register is 12 bits wide, and bits 31:12 are reserved. This register can be + /// written to only when IC_ENABLE[0] is set to 0.\n\n + /// Note: If the software or application is aware that the DW_apb_i2c is not using + /// the TAR address for the pending commands in the Tx FIFO, then it is possible to + /// update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - + /// It is not necessary to perform any write to this register if DW_apb_i2c is + /// enabled as an I2C slave only. + pub const IC_TAR = @intToPtr(*volatile Mmio(32, packed struct { + /// This is the target address for any master transaction. When transmitting a + /// General Call, these bits are ignored. To generate a START BYTE, the CPU needs to + /// write only once into these bits.\n\n + /// If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared + /// between master and slave, so full loopback is not feasible. Only one direction + /// loopback mode is supported (simplex), not duplex. A master cannot transmit to + /// itself; it can transmit to only a slave. + IC_TAR: u10, + /// If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit + /// indicates whether a General Call or START byte command is to be performed by the + /// DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only + /// writes may be performed. Attempting to issue a read command results in setting + /// bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in + /// General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START + /// BYTE Reset value: 0x0 + GC_OR_START: u1, + /// This bit indicates whether software performs a Device-ID or General Call or + /// START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: + /// perform special I2C command as specified in Device_ID or GC_OR_START bit Reset + /// value: 0x0 + SPECIAL: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40044008 + /// I2C Slave Address Register + pub const IC_SAR = @intToPtr(*volatile MmioInt(32, u10), base_address + 0x8); + + /// address: 0x40044010 + /// I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes + /// to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX + /// FIFO.\n\n + /// The size of the register changes as follows:\n\n + /// Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when + /// IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 + /// - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to + /// continue acknowledging reads, a read command should be written for every byte + /// that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + pub const IC_DATA_CMD = @intToPtr(*volatile Mmio(32, packed struct { + /// This register contains the data to be transmitted or received on the I2C bus. If + /// you are writing to this register and want to perform a read, bits 7:0 (DAT) are + /// ignored by the DW_apb_i2c. However, when you read this register, these bits + /// return the value of data received on the DW_apb_i2c interface.\n\n + /// Reset value: 0x0 + DAT: u8, + /// This bit controls whether a read or a write is performed. This bit does not + /// control the direction when the DW_apb_i2con acts as a slave. It controls only + /// the direction when it acts as a master.\n\n + /// When a command is entered in the TX FIFO, this bit distinguishes the write and + /// read commands. In slave-receiver mode, this bit is a 'don't care' because writes + /// to this register are not required. In slave-transmitter mode, a '0' indicates + /// that the data in IC_DATA_CMD is to be transmitted.\n\n + /// When programming this bit, you should remember the following: attempting to + /// perform a read operation after a General Call command has been sent results in a + /// TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 + /// (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this + /// bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n + /// Reset value: 0x0 + CMD: u1, + /// This bit controls whether a STOP is issued after the byte is sent or + /// received.\n\n + /// - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO + /// is empty. If the Tx FIFO is not empty, the master immediately tries to start a + /// new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not + /// issued after this byte, regardless of whether or not the Tx FIFO is empty. If + /// the Tx FIFO is not empty, the master continues the current transfer by + /// sending/receiving data bytes according to the value of the CMD bit. If the Tx + /// FIFO is empty, the master holds the SCL line low and stalls the bus until a new + /// command is available in the Tx FIFO. Reset value: 0x0 + STOP: u1, + /// This bit controls whether a RESTART is issued before the byte is sent or + /// received.\n\n + /// 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received + /// (according to the value of CMD), regardless of whether or not the transfer + /// direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP + /// followed by a START is issued instead.\n\n + /// 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is + /// changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a + /// START is issued instead.\n\n + /// Reset value: 0x0 + RESTART: u1, + /// Indicates the first data byte received after the address phase for receive + /// transfer in Master receiver or Slave receiver mode.\n\n + /// Reset value : 0x0\n\n + /// NOTE: In case of APB_DATA_WIDTH=8,\n\n + /// 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status + /// on 11 bit.\n\n + /// 2. In order to read the 11 bit, the user has to perform the first data byte read + /// [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in + /// order to know the status of 11 bit (whether the data received in previous read + /// is a first data byte or not).\n\n + /// 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] + /// (offset 0x11) if not interested in FIRST_DATA_BYTE status. + FIRST_DATA_BYTE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x10); + + /// address: 0x40044014 + /// Standard Speed I2C Clock SCL High Count Register + pub const IC_SS_SCL_HCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14); + + /// address: 0x40044018 + /// Standard Speed I2C Clock SCL Low Count Register + pub const IC_SS_SCL_LCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x18); + + /// address: 0x4004401c + /// Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + pub const IC_FS_SCL_HCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c); + + /// address: 0x40044020 + /// Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + pub const IC_FS_SCL_LCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x20); + + /// address: 0x4004402c + /// I2C Interrupt Status Register\n\n + /// Each bit in this register has a corresponding mask bit in the IC_INTR_MASK + /// register. These bits are cleared by reading the matching interrupt clear + /// register. The unmasked raw versions of these bits are available in the + /// IC_RAW_INTR_STAT register. + pub const IC_INTR_STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n + /// Reset value: 0x0 + R_RX_UNDER: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n + /// Reset value: 0x0 + R_RX_OVER: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n + /// Reset value: 0x0 + R_RX_FULL: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n + /// Reset value: 0x0 + R_TX_OVER: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n + /// Reset value: 0x0 + R_TX_EMPTY: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n + /// Reset value: 0x0 + R_RD_REQ: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n + /// Reset value: 0x0 + R_TX_ABRT: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n + /// Reset value: 0x0 + R_RX_DONE: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n + /// Reset value: 0x0 + R_ACTIVITY: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n + /// Reset value: 0x0 + R_STOP_DET: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n + /// Reset value: 0x0 + R_START_DET: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n + /// Reset value: 0x0 + R_GEN_CALL: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n + /// Reset value: 0x0 + R_RESTART_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + }), base_address + 0x2c); + + /// address: 0x40044030 + /// I2C Interrupt Mask Register.\n\n + /// These bits mask their corresponding interrupt status bits. This register is + /// active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the + /// interrupt. + pub const IC_INTR_MASK = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_RX_UNDER: u1, + /// This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_RX_OVER: u1, + /// This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_RX_FULL: u1, + /// This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_TX_OVER: u1, + /// This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_TX_EMPTY: u1, + /// This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_RD_REQ: u1, + /// This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_TX_ABRT: u1, + /// This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_RX_DONE: u1, + /// This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x0 + M_ACTIVITY: u1, + /// This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x0 + M_STOP_DET: u1, + /// This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x0 + M_START_DET: u1, + /// This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_GEN_CALL: u1, + /// This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x0 + M_RESTART_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + }), base_address + 0x30); + + /// address: 0x40044034 + /// I2C Raw Interrupt Status Register\n\n + /// Unlike the IC_INTR_STAT register, these bits are not masked so they always show + /// the true status of the DW_apb_i2c. + pub const IC_RAW_INTR_STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Set if the processor attempts to read the receive buffer when it is empty by + /// reading from the IC_DATA_CMD register. If the module is disabled + /// (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state + /// machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n + /// Reset value: 0x0 + RX_UNDER: u1, + /// Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an + /// additional byte is received from an external I2C device. The DW_apb_i2c + /// acknowledges this, but any data bytes received after the FIFO is full are lost. + /// If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the + /// master or slave state machines go into idle, and when ic_en goes to 0, this + /// interrupt is cleared.\n\n + /// Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to + /// HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never + /// overflows.\n\n + /// Reset value: 0x0 + RX_OVER: u1, + /// Set when the receive buffer reaches or goes above the RX_TL threshold in the + /// IC_RX_TL register. It is automatically cleared by hardware when buffer level + /// goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX + /// FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this + /// bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of + /// the activity that continues.\n\n + /// Reset value: 0x0 + RX_FULL: u1, + /// Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and + /// the processor attempts to issue another I2C command by writing to the + /// IC_DATA_CMD register. When the module is disabled, this bit keeps its level + /// until the master or slave state machines go into idle, and when ic_en goes to 0, + /// this interrupt is cleared.\n\n + /// Reset value: 0x0 + TX_OVER: u1, + /// The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL + /// selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 + /// when the transmit buffer is at or below the threshold value set in the IC_TX_TL + /// register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit + /// buffer is at or below the threshold value set in the IC_TX_TL register and the + /// transmission of the address/data from the internal shift register for the most + /// recently popped command is completed. It is automatically cleared by hardware + /// when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, + /// the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no + /// data within it, so this bit is set to 1, provided there is activity in the + /// master or slave state machines. When there is no longer any activity, then with + /// ic_en=0, this bit is set to 0.\n\n + /// Reset value: 0x0. + TX_EMPTY: u1, + /// This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master + /// is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in + /// a wait state (SCL=0) until this interrupt is serviced, which means that the + /// slave has been addressed by a remote master that is asking for data to be + /// transferred. The processor must respond to this interrupt and then write the + /// requested data to the IC_DATA_CMD register. This bit is set to 0 just after the + /// processor reads the IC_CLR_RD_REQ register.\n\n + /// Reset value: 0x0 + RD_REQ: u1, + /// This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete + /// the intended actions on the contents of the transmit FIFO. This situation can + /// occur both as an I2C master or an I2C slave, and is referred to as a 'transmit + /// abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the + /// reason why the transmit abort takes places.\n\n + /// Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever + /// there is a transmit abort caused by any of the events tracked by the + /// IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the + /// register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is + /// then ready to accept more data bytes from the APB interface.\n\n + /// Reset value: 0x0 + TX_ABRT: u1, + /// When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if + /// the master does not acknowledge a transmitted byte. This occurs on the last byte + /// of the transmission, indicating that the transmission is done.\n\n + /// Reset value: 0x0 + RX_DONE: u1, + /// This bit captures DW_apb_i2c activity and stays set until it is cleared. There + /// are four ways to clear it: - Disabling the DW_apb_i2c - Reading the + /// IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once + /// this bit is set, it stays set unless one of the four methods is used to clear + /// it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, + /// indicating that there was activity on the bus.\n\n + /// Reset value: 0x0 + ACTIVITY: u1, + /// Indicates whether a STOP condition has occurred on the I2C interface regardless + /// of whether DW_apb_i2c is operating in slave or master mode.\n\n + /// In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET + /// interrupt will be issued only if slave is addressed. Note: During a general call + /// address, this slave does not issue a STOP_DET interrupt if + /// STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call + /// address by generating ACK. The STOP_DET interrupt is generated only when the + /// transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 + /// (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether + /// it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 + /// (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master + /// is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt + /// will be issued irrespective of whether master is active or not. Reset value: 0x0 + STOP_DET: u1, + /// Indicates whether a START or RESTART condition has occurred on the I2C interface + /// regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n + /// Reset value: 0x0 + START_DET: u1, + /// Set only when a General Call address is received and it is acknowledged. It + /// stays set until it is cleared either by disabling DW_apb_i2c or when the CPU + /// reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data + /// in the Rx buffer.\n\n + /// Reset value: 0x0 + GEN_CALL: u1, + /// Indicates whether a RESTART condition has occurred on the I2C interface when + /// DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled + /// only when IC_SLV_RESTART_DET_EN=1.\n\n + /// Note: However, in high-speed mode or during a START BYTE transfer, the RESTART + /// comes before the address field as per the I2C protocol. In this case, the slave + /// is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does + /// not generate the RESTART_DET interrupt.\n\n + /// Reset value: 0x0 + RESTART_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + }), base_address + 0x34); + + /// address: 0x40044038 + /// I2C Receive FIFO Threshold Register + pub const IC_RX_TL = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive FIFO Threshold Level.\n\n + /// Controls the level of entries (or above) that triggers the RX_FULL interrupt + /// (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the + /// additional restriction that hardware does not allow this value to be set to a + /// value larger than the depth of the buffer. If an attempt is made to do that, the + /// actual value set will be the maximum depth of the buffer. A value of 0 sets the + /// threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + RX_TL: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x38); + + /// address: 0x4004403c + /// I2C Transmit FIFO Threshold Register + pub const IC_TX_TL = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO Threshold Level.\n\n + /// Controls the level of entries (or below) that trigger the TX_EMPTY interrupt + /// (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the + /// additional restriction that it may not be set to value larger than the depth of + /// the buffer. If an attempt is made to do that, the actual value set will be the + /// maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and + /// a value of 255 sets the threshold for 255 entries. + TX_TL: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x3c); + + /// address: 0x40044040 + /// Clear Combined and Individual Interrupt Register + pub const IC_CLR_INTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the combined interrupt, all individual interrupts, + /// and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable + /// interrupts but software clearable interrupts. Refer to Bit 9 of the + /// IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n + /// Reset value: 0x0 + CLR_INTR: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x40); + + /// address: 0x40044044 + /// Clear RX_UNDER Interrupt Register + pub const IC_CLR_RX_UNDER = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the RX_UNDER interrupt (bit 0) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_RX_UNDER: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x44); + + /// address: 0x40044048 + /// Clear RX_OVER Interrupt Register + pub const IC_CLR_RX_OVER = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the RX_OVER interrupt (bit 1) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_RX_OVER: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x48); + + /// address: 0x4004404c + /// Clear TX_OVER Interrupt Register + pub const IC_CLR_TX_OVER = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the TX_OVER interrupt (bit 3) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_TX_OVER: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x4c); + + /// address: 0x40044050 + /// Clear RD_REQ Interrupt Register + pub const IC_CLR_RD_REQ = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT + /// register.\n\n + /// Reset value: 0x0 + CLR_RD_REQ: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x50); + + /// address: 0x40044054 + /// Clear TX_ABRT Interrupt Register + pub const IC_CLR_TX_ABRT = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the TX_ABRT interrupt (bit 6) of the + /// IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also + /// releases the TX FIFO from the flushed/reset state, allowing more writes to the + /// TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to + /// clearing IC_TX_ABRT_SOURCE.\n\n + /// Reset value: 0x0 + CLR_TX_ABRT: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x54); + + /// address: 0x40044058 + /// Clear RX_DONE Interrupt Register + pub const IC_CLR_RX_DONE = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the RX_DONE interrupt (bit 7) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_RX_DONE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x58); + + /// address: 0x4004405c + /// Clear ACTIVITY Interrupt Register + pub const IC_CLR_ACTIVITY = @intToPtr(*volatile Mmio(32, packed struct { + /// Reading this register clears the ACTIVITY interrupt if the I2C is not active + /// anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt + /// bit continues to be set. It is automatically cleared by hardware if the module + /// is disabled and if there is no further activity on the bus. The value read from + /// this register to get status of the ACTIVITY interrupt (bit 8) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_ACTIVITY: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x5c); + + /// address: 0x40044060 + /// Clear STOP_DET Interrupt Register + pub const IC_CLR_STOP_DET = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the STOP_DET interrupt (bit 9) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_STOP_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x60); + + /// address: 0x40044064 + /// Clear START_DET Interrupt Register + pub const IC_CLR_START_DET = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the START_DET interrupt (bit 10) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_START_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x64); + + /// address: 0x40044068 + /// Clear GEN_CALL Interrupt Register + pub const IC_CLR_GEN_CALL = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT + /// register.\n\n + /// Reset value: 0x0 + CLR_GEN_CALL: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x68); + + /// address: 0x4004406c + /// I2C Enable Register + pub const IC_ENABLE = @intToPtr(*volatile Mmio(32, packed struct { + /// Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX + /// FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable + /// DW_apb_i2c while it is active. However, it is important that care be taken to + /// ensure that DW_apb_i2c is disabled properly. A recommended procedure is + /// described in 'Disabling DW_apb_i2c'.\n\n + /// When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get + /// flushed. - Status bits in the IC_INTR_STAT register are still active until + /// DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well + /// as deletes the contents of the transmit buffer after the current transfer is + /// complete. If the module is receiving, the DW_apb_i2c stops the current transfer + /// at the end of the current byte and does not acknowledge the transfer.\n\n + /// In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to + /// asynchronous (1), there is a two ic_clk delay when enabling or disabling the + /// DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to + /// 'Disabling DW_apb_i2c'\n\n + /// Reset value: 0x0 + ENABLE: u1, + /// When set, the controller initiates the transfer abort. - 0: ABORT not initiated + /// or ABORT done - 1: ABORT operation in progress The software can abort the I2C + /// transfer in master mode by setting this bit. The software can set this bit only + /// when ENABLE is already set; otherwise, the controller ignores any write to ABORT + /// bit. The software cannot clear the ABORT bit once set. In response to an ABORT, + /// the controller issues a STOP and flushes the Tx FIFO after completing the + /// current transfer, then sets the TX_ABORT interrupt after the abort operation. + /// The ABORT bit is cleared automatically after the abort operation.\n\n + /// For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C + /// Transfers'.\n\n + /// Reset value: 0x0 + ABORT: u1, + /// In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx + /// FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus + /// automatically, as soon as the first data is available in the Tx FIFO. Note: To + /// block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx + /// FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). + /// Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit + /// is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + TX_CMD_BLOCK: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + }), base_address + 0x6c); + + /// address: 0x40044070 + /// I2C Status Register\n\n + /// This is a read-only register used to indicate the current transfer status and + /// FIFO status. The status register may be read at any time. None of the bits in + /// this register request an interrupt.\n\n + /// When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits + /// 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state + /// machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + pub const IC_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// I2C Activity Status. Reset value: 0x0 + ACTIVITY: u1, + /// Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty + /// locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: + /// Transmit FIFO is not full Reset value: 0x1 + TFNF: u1, + /// Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this + /// bit is set. When it contains one or more valid entries, this bit is cleared. + /// This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - + /// 1: Transmit FIFO is empty Reset value: 0x1 + TFE: u1, + /// Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or + /// more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is + /// empty - 1: Receive FIFO is not empty Reset value: 0x0 + RFNE: u1, + /// Receive FIFO Completely Full. When the receive FIFO is completely full, this bit + /// is set. When the receive FIFO contains one or more empty location, this bit is + /// cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: + /// 0x0 + RFF: u1, + /// Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in + /// the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master + /// part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the + /// Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is + /// the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n + /// Reset value: 0x0 + MST_ACTIVITY: u1, + /// Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in + /// the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave + /// part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the + /// Slave part of DW_apb_i2c is Active Reset value: 0x0 + SLV_ACTIVITY: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + }), base_address + 0x70); + + /// address: 0x40044074 + /// I2C Transmit FIFO Level Register This register contains the number of valid data + /// entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is + /// disabled - There is a transmit abort - that is, TX_ABRT bit is set in the + /// IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register + /// increments whenever data is placed into the transmit FIFO and decrements when + /// data is taken from the transmit FIFO. + pub const IC_TXFLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO Level. Contains the number of valid data entries in the transmit + /// FIFO.\n\n + /// Reset value: 0x0 + TXFLR: u5, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + }), base_address + 0x74); + + /// address: 0x40044078 + /// I2C Receive FIFO Level Register This register contains the number of valid data + /// entries in the receive FIFO buffer. It is cleared whenever: - The I2C is + /// disabled - Whenever there is a transmit abort caused by any of the events + /// tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed + /// into the receive FIFO and decrements when data is taken from the receive FIFO. + pub const IC_RXFLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive FIFO Level. Contains the number of valid data entries in the receive + /// FIFO.\n\n + /// Reset value: 0x0 + RXFLR: u5, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + }), base_address + 0x78); + + /// address: 0x4004407c + /// I2C SDA Hold Time Length Register\n\n + /// The bits [15:0] of this register are used to control the hold time of SDA during + /// transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n + /// The bits [23:16] of this register are used to extend the SDA transition (if any) + /// whenever SCL is HIGH in the receiver in either master or slave mode.\n\n + /// Writes to this register succeed only when IC_ENABLE[0]=0.\n\n + /// The values in this register are in units of ic_clk period. The value programmed + /// in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one + /// cycle in master mode, seven cycles in slave mode) for the value to be + /// implemented.\n\n + /// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at + /// any time the duration of the low part of scl. Therefore the programmed value + /// cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low + /// part of the scl period measured in ic_clk cycles. + pub const IC_SDA_HOLD = @intToPtr(*volatile Mmio(32, packed struct { + /// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts + /// as a transmitter.\n\n + /// Reset value: IC_DEFAULT_SDA_HOLD[15:0]. + IC_SDA_TX_HOLD: u16, + /// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts + /// as a receiver.\n\n + /// Reset value: IC_DEFAULT_SDA_HOLD[23:16]. + IC_SDA_RX_HOLD: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x7c); + + /// address: 0x40044080 + /// I2C Transmit Abort Source Register\n\n + /// This register has 32 bits that indicate the source of the TX_ABRT bit. Except + /// for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the + /// IC_CLR_INTR register is read. To clear Bit 9, the source of the + /// ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), + /// the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be + /// cleared (IC_TAR[10]).\n\n + /// Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared + /// in the same manner as other bits in this register. If the source of the + /// ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 + /// clears for one cycle and is then re-asserted. + pub const IC_TX_ABRT_SOURCE = @intToPtr(*volatile Mmio(32, packed struct { + /// This field indicates that the Master is in 7-bit addressing mode and the address + /// sent was not acknowledged by any slave.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + ABRT_7B_ADDR_NOACK: u1, + /// This field indicates that the Master is in 10-bit address mode and the first + /// 10-bit address byte was not acknowledged by any slave.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + ABRT_10ADDR1_NOACK: u1, + /// This field indicates that the Master is in 10-bit address mode and that the + /// second address byte of the 10-bit address was not acknowledged by any slave.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + ABRT_10ADDR2_NOACK: u1, + /// This field indicates the master-mode only bit. When the master receives an + /// acknowledgement for the address, but when it sends data byte(s) following the + /// address, it did not receive an acknowledge from the remote slave(s).\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter + ABRT_TXDATA_NOACK: u1, + /// This field indicates that DW_apb_i2c in master mode has sent a General Call and + /// no slave on the bus acknowledged the General Call.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter + ABRT_GCALL_NOACK: u1, + /// This field indicates that DW_apb_i2c in the master mode has sent a General Call + /// but the user programmed the byte following the General Call to be a read from + /// the bus (IC_DATA_CMD[9] is set to 1).\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter + ABRT_GCALL_READ: u1, + /// This field indicates that the Master is in High Speed mode and the High Speed + /// Master code was acknowledged (wrong behavior).\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master + ABRT_HS_ACKDET: u1, + /// This field indicates that the Master has sent a START Byte and the START Byte + /// was acknowledged (wrong behavior).\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master + ABRT_SBYTE_ACKDET: u1, + /// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) + /// =0) and the user is trying to use the master to transfer data in High Speed + /// mode.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + ABRT_HS_NORSTRT: u1, + /// To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; + /// restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared + /// (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the + /// source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the + /// same manner as other bits in this register. If the source of the + /// ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 + /// clears for one cycle and then gets reasserted. When this field is set to 1, the + /// restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to + /// send a START Byte.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master + ABRT_SBYTE_NORSTRT: u1, + /// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) + /// =0) and the master sends a read command in 10-bit addressing mode.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Receiver + ABRT_10B_RD_NORSTRT: u1, + /// This field indicates that the User tries to initiate a Master operation with the + /// Master mode disabled.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + ABRT_MASTER_DIS: u1, + /// This field specifies that the Master has lost arbitration, or if + /// IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost + /// arbitration.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + ARB_LOST: u1, + /// This field specifies that the Slave has received a read command and some data + /// exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data + /// in TX FIFO.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Slave-Transmitter + ABRT_SLVFLUSH_TXFIFO: u1, + /// This field indicates that a Slave has lost the bus while transmitting data to a + /// remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though + /// the slave never 'owns' the bus, something could go wrong on the bus. This is a + /// fail safe check. For instance, during a data transmission at the low-to-high + /// transition of SCL, if what is on the data bus is not what is supposed to be + /// transmitted, then DW_apb_i2c no longer own the bus.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Slave-Transmitter + ABRT_SLV_ARBLOST: u1, + /// 1: When the processor side responds to a slave mode request for data to be + /// transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD + /// register.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Slave-Transmitter + ABRT_SLVRD_INTX: u1, + /// This is a master-mode-only bit. Master has detected the transfer abort + /// (IC_ENABLE[1])\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter + ABRT_USER_ABRT: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// This field indicates the number of Tx FIFO Data Commands which are flushed due + /// to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + TX_FLUSH_CNT: u9, + }), base_address + 0x80); + + /// address: 0x40044084 + /// Generate Slave Data NACK Register\n\n + /// The register is used to generate a NACK for the data part of a transfer when + /// DW_apb_i2c is acting as a slave-receiver. This register only exists when the + /// IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this + /// register does not exist and writing to the register's address has no effect.\n\n + /// A write can occur on this register if both of the following conditions are met: + /// - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive + /// (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for + /// the internal slv_activity signal; the user should poll this before writing the + /// ic_slv_data_nack_only bit. + pub const IC_SLV_DATA_NACK_ONLY = @intToPtr(*volatile Mmio(32, packed struct { + /// Generate NACK. This NACK generation only occurs when DW_apb_i2c is a + /// slave-receiver. If this register is set to a value of 1, it can only generate a + /// NACK after a data byte is received; hence, the data transfer is aborted and the + /// data received is not pushed to the receive buffer.\n\n + /// When the register is set to a value of 0, it generates NACK/ACK, depending on + /// normal criteria. - 1: generate NACK after data byte received - 0: generate + /// NACK/ACK normally Reset value: 0x0 + NACK: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x84); + + /// address: 0x40044088 + /// DMA Control Register\n\n + /// The register is used to enable the DMA Controller interface operation. There is + /// a separate bit for transmit and receive. This can be programmed regardless of + /// the state of IC_ENABLE. + pub const IC_DMA_CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. + /// Reset value: 0x0 + RDMAE: u1, + /// Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. + /// Reset value: 0x0 + TDMAE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x88); + + /// address: 0x4004408c + /// DMA Transmit Data Level Register + pub const IC_DMA_TDLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Data Level. This bit field controls the level at which a DMA request is + /// made by the transmit logic. It is equal to the watermark level; that is, the + /// dma_tx_req signal is generated when the number of valid data entries in the + /// transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n + /// Reset value: 0x0 + DMATDL: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x8c); + + /// address: 0x40044090 + /// I2C Receive Data Level Register + pub const IC_DMA_RDLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Data Level. This bit field controls the level at which a DMA request is + /// made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req + /// is generated when the number of valid data entries in the receive FIFO is equal + /// to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is + /// 0, then dma_rx_req is asserted when 1 or more data entries are present in the + /// receive FIFO.\n\n + /// Reset value: 0x0 + DMARDL: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x90); + + /// address: 0x40044094 + /// I2C SDA Setup Register\n\n + /// This register controls the amount of time delay (in terms of number of ic_clk + /// clock periods) introduced in the rising edge of SCL - relative to SDA changing - + /// when DW_apb_i2c services a read request in a slave-transmitter operation. The + /// relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus + /// Specification. This register must be programmed with a value equal to or greater + /// than 2.\n\n + /// Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n + /// Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * + /// (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they + /// should program a value of 11. The IC_SDA_SETUP register is only used by the + /// DW_apb_i2c when operating as a slave transmitter. + pub const IC_SDA_SETUP = @intToPtr(*volatile Mmio(32, packed struct { + /// SDA Setup. It is recommended that if the required delay is 1000ns, then for an + /// ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. + /// IC_SDA_SETUP must be programmed with a minimum value of 2. + SDA_SETUP: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x94); + + /// address: 0x40044098 + /// I2C ACK General Call Register\n\n + /// The register controls whether DW_apb_i2c responds with a ACK or NACK when it + /// receives an I2C General Call address.\n\n + /// This register is applicable only when the DW_apb_i2c is in slave mode. + pub const IC_ACK_GENERAL_CALL = @intToPtr(*volatile Mmio(32, packed struct { + /// ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting + /// ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with + /// a NACK (by negating ic_data_oe). + ACK_GEN_CALL: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x98); + + /// address: 0x4004409c + /// I2C Enable Status Register\n\n + /// The register is used to report the DW_apb_i2c hardware status when the + /// IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is + /// disabled.\n\n + /// If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced + /// to 1.\n\n + /// If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is + /// read as '0'.\n\n + /// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read + /// as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + pub const IC_ENABLE_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// ic_en Status. This bit always reflects the value driven on the output port + /// ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When + /// read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely + /// read this bit anytime. When this bit is read as 0, the CPU can safely read + /// SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n + /// Reset value: 0x0 + IC_EN: u1, + /// Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential + /// or active Slave operation has been aborted due to the setting bit 0 of the + /// IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the + /// IC_ENABLE register while:\n\n + /// (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation + /// from a remote master;\n\n + /// OR,\n\n + /// (b) address and data bytes of the Slave-Receiver operation from a remote + /// master.\n\n + /// When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an + /// I2C transfer, irrespective of whether the I2C address matches the slave address + /// set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before + /// IC_ENABLE is set to 0 but has not taken effect.\n\n + /// Note: If the remote I2C master terminates the transfer with a STOP condition + /// before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been + /// set to 0, then this bit will also be set to 1.\n\n + /// When read as 0, DW_apb_i2c is deemed to have been disabled when there is master + /// activity, or when the I2C bus is idle.\n\n + /// Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n + /// Reset value: 0x0 + SLV_DISABLED_WHILE_BUSY: u1, + /// Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has + /// been aborted with at least one data byte received from an I2C transfer due to + /// the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed + /// to have been actively engaged in an aborted I2C transfer (with matching address) + /// and the data phase of the I2C transfer has been entered, even though a data byte + /// has been responded with a NACK.\n\n + /// Note: If the remote I2C master terminates the transfer with a STOP condition + /// before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been + /// set to 0, then this bit is also set to 1.\n\n + /// When read as 0, DW_apb_i2c is deemed to have been disabled without being + /// actively involved in the data phase of a Slave-Receiver transfer.\n\n + /// Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n + /// Reset value: 0x0 + SLV_RX_DATA_LOST: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + }), base_address + 0x9c); + + /// address: 0x400440a0 + /// I2C SS, FS or FM+ spike suppression limit\n\n + /// This register is used to store the duration, measured in ic_clk cycles, of the + /// longest spike that is filtered out by the spike suppression logic when the + /// component is operating in SS, FS or FM+ modes. The relevant I2C requirement is + /// tSP (table 4) as detailed in the I2C Bus Specification. This register must be + /// programmed with a minimum value of 1. + pub const IC_FS_SPKLEN = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xa0); + + /// address: 0x400440a8 + /// Clear RESTART_DET Interrupt Register + pub const IC_CLR_RESTART_DET = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the RESTART_DET interrupt (bit 12) of + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_RESTART_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0xa8); + + /// address: 0x400440f4 + /// Component Parameter Register 1\n\n + /// Note This register is not implemented and therefore reads as 0. If it was + /// implemented it would be a constant read-only register that contains encoded + /// information about the component's parameter settings. Fields shown below are the + /// settings for those parameters + pub const IC_COMP_PARAM_1 = @intToPtr(*volatile Mmio(32, packed struct { + /// APB data bus width is 32 bits + APB_DATA_WIDTH: u2, + /// MAX SPEED MODE = FAST MODE + MAX_SPEED_MODE: u2, + /// Programmable count values for each mode. + HC_COUNT_VALUES: u1, + /// COMBINED Interrupt outputs + INTR_IO: u1, + /// DMA handshaking signals are enabled + HAS_DMA: u1, + /// Encoded parameters not visible + ADD_ENCODED_PARAMS: u1, + /// RX Buffer Depth = 16 + RX_BUFFER_DEPTH: u8, + /// TX Buffer Depth = 16 + TX_BUFFER_DEPTH: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0xf4); + + /// address: 0x400440f8 + /// I2C Component Version Register + pub const IC_COMP_VERSION = @intToPtr(*volatile u32, base_address + 0xf8); + + /// address: 0x400440fc + /// I2C Component Type Register + pub const IC_COMP_TYPE = @intToPtr(*volatile u32, base_address + 0xfc); + }; + pub const I2C1 = struct { + pub const base_address = 0x40048000; + + /// address: 0x40048000 + /// I2C Control Register. This register can be written only when the DW_apb_i2c is + /// disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes + /// at other times have no effect.\n\n + /// Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read + /// only - bit 17 is read only - bits 18 and 19 are read only. + pub const IC_CON = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit controls whether the DW_apb_i2c master is enabled.\n\n + /// NOTE: Software should ensure that if this bit is written with '1' then bit 6 + /// should also be written with a '1'. + MASTER_MODE: u1, + /// These bits control at which speed the DW_apb_i2c operates; its setting is + /// relevant only if one is operating the DW_apb_i2c in master mode. Hardware + /// protects against illegal values being programmed by software. These bits must be + /// programmed appropriately for slave mode also, as it is used to capture correct + /// value of spike filter as per the speed mode.\n\n + /// This register should be programmed only with a value in the range of 1 to + /// IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of + /// IC_MAX_SPEED_MODE.\n\n + /// 1: standard mode (100 kbit/s)\n\n + /// 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n + /// 3: high speed mode (3.4 Mbit/s)\n\n + /// Note: This field is not applicable when IC_ULTRA_FAST_MODE=1 + SPEED: u2, + /// When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- + /// or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions + /// that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of + /// the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c + /// responds to only 10-bit addressing transfers that match the full 10 bits of the + /// IC_SAR register. + IC_10BITADDR_SLAVE: u1, + /// Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing + /// mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing + IC_10BITADDR_MASTER: u1, + /// Determines whether RESTART conditions may be sent when acting as a master. Some + /// older slaves do not support handling RESTART conditions; however, RESTART + /// conditions are used in several DW_apb_i2c operations. When RESTART is disabled, + /// the master is prohibited from performing the following functions: - Sending a + /// START BYTE - Performing any high-speed mode operation - High-speed mode + /// operation - Performing direction changes in combined format mode - Performing a + /// read operation with a 10-bit address By replacing RESTART condition followed by + /// a STOP and a subsequent START condition, split operations are broken down into + /// multiple DW_apb_i2c transfers. If the above operations are performed, it will + /// result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n + /// Reset value: ENABLED + IC_RESTART_EN: u1, + /// This bit controls whether I2C has its slave disabled, which means once the + /// presetn signal is applied, then this bit is set and the slave is disabled.\n\n + /// If this bit is set (slave is disabled), DW_apb_i2c functions only as a master + /// and does not perform any action that requires a slave.\n\n + /// NOTE: Software should ensure that if this bit is written with 0, then bit 0 + /// should also be written with a 0. + IC_SLAVE_DISABLE: u1, + /// In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. + /// - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset + /// value: 0x0\n\n + /// NOTE: During a general call address, this slave does not issue the STOP_DET + /// interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the + /// general call address by generating ACK. The STOP_DET interrupt is generated only + /// when the transmitted address matches the slave address (SAR). + STOP_DET_IFADDRESSED: u1, + /// This bit controls the generation of the TX_EMPTY interrupt, as described in the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0. + TX_EMPTY_CTRL: u1, + /// This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is + /// physically full to its RX_BUFFER_DEPTH, as described in the + /// IC_RX_FULL_HLD_BUS_EN parameter.\n\n + /// Reset value: 0x0. + RX_FIFO_FULL_HLD_CTRL: u1, + /// Master issues the STOP_DET interrupt irrespective of whether master is active or + /// not + STOP_DET_IF_MASTER_ACTIVE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40048004 + /// I2C Target Address Register\n\n + /// This register is 12 bits wide, and bits 31:12 are reserved. This register can be + /// written to only when IC_ENABLE[0] is set to 0.\n\n + /// Note: If the software or application is aware that the DW_apb_i2c is not using + /// the TAR address for the pending commands in the Tx FIFO, then it is possible to + /// update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - + /// It is not necessary to perform any write to this register if DW_apb_i2c is + /// enabled as an I2C slave only. + pub const IC_TAR = @intToPtr(*volatile Mmio(32, packed struct { + /// This is the target address for any master transaction. When transmitting a + /// General Call, these bits are ignored. To generate a START BYTE, the CPU needs to + /// write only once into these bits.\n\n + /// If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared + /// between master and slave, so full loopback is not feasible. Only one direction + /// loopback mode is supported (simplex), not duplex. A master cannot transmit to + /// itself; it can transmit to only a slave. + IC_TAR: u10, + /// If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit + /// indicates whether a General Call or START byte command is to be performed by the + /// DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only + /// writes may be performed. Attempting to issue a read command results in setting + /// bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in + /// General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START + /// BYTE Reset value: 0x0 + GC_OR_START: u1, + /// This bit indicates whether software performs a Device-ID or General Call or + /// START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: + /// perform special I2C command as specified in Device_ID or GC_OR_START bit Reset + /// value: 0x0 + SPECIAL: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40048008 + /// I2C Slave Address Register + pub const IC_SAR = @intToPtr(*volatile MmioInt(32, u10), base_address + 0x8); + + /// address: 0x40048010 + /// I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes + /// to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX + /// FIFO.\n\n + /// The size of the register changes as follows:\n\n + /// Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when + /// IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 + /// - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to + /// continue acknowledging reads, a read command should be written for every byte + /// that is to be received; otherwise the DW_apb_i2c will stop acknowledging. + pub const IC_DATA_CMD = @intToPtr(*volatile Mmio(32, packed struct { + /// This register contains the data to be transmitted or received on the I2C bus. If + /// you are writing to this register and want to perform a read, bits 7:0 (DAT) are + /// ignored by the DW_apb_i2c. However, when you read this register, these bits + /// return the value of data received on the DW_apb_i2c interface.\n\n + /// Reset value: 0x0 + DAT: u8, + /// This bit controls whether a read or a write is performed. This bit does not + /// control the direction when the DW_apb_i2con acts as a slave. It controls only + /// the direction when it acts as a master.\n\n + /// When a command is entered in the TX FIFO, this bit distinguishes the write and + /// read commands. In slave-receiver mode, this bit is a 'don't care' because writes + /// to this register are not required. In slave-transmitter mode, a '0' indicates + /// that the data in IC_DATA_CMD is to be transmitted.\n\n + /// When programming this bit, you should remember the following: attempting to + /// perform a read operation after a General Call command has been sent results in a + /// TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 + /// (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this + /// bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n + /// Reset value: 0x0 + CMD: u1, + /// This bit controls whether a STOP is issued after the byte is sent or + /// received.\n\n + /// - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO + /// is empty. If the Tx FIFO is not empty, the master immediately tries to start a + /// new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not + /// issued after this byte, regardless of whether or not the Tx FIFO is empty. If + /// the Tx FIFO is not empty, the master continues the current transfer by + /// sending/receiving data bytes according to the value of the CMD bit. If the Tx + /// FIFO is empty, the master holds the SCL line low and stalls the bus until a new + /// command is available in the Tx FIFO. Reset value: 0x0 + STOP: u1, + /// This bit controls whether a RESTART is issued before the byte is sent or + /// received.\n\n + /// 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received + /// (according to the value of CMD), regardless of whether or not the transfer + /// direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP + /// followed by a START is issued instead.\n\n + /// 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is + /// changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a + /// START is issued instead.\n\n + /// Reset value: 0x0 + RESTART: u1, + /// Indicates the first data byte received after the address phase for receive + /// transfer in Master receiver or Slave receiver mode.\n\n + /// Reset value : 0x0\n\n + /// NOTE: In case of APB_DATA_WIDTH=8,\n\n + /// 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status + /// on 11 bit.\n\n + /// 2. In order to read the 11 bit, the user has to perform the first data byte read + /// [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in + /// order to know the status of 11 bit (whether the data received in previous read + /// is a first data byte or not).\n\n + /// 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] + /// (offset 0x11) if not interested in FIRST_DATA_BYTE status. + FIRST_DATA_BYTE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x10); + + /// address: 0x40048014 + /// Standard Speed I2C Clock SCL High Count Register + pub const IC_SS_SCL_HCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14); + + /// address: 0x40048018 + /// Standard Speed I2C Clock SCL Low Count Register + pub const IC_SS_SCL_LCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x18); + + /// address: 0x4004801c + /// Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register + pub const IC_FS_SCL_HCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c); + + /// address: 0x40048020 + /// Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register + pub const IC_FS_SCL_LCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x20); + + /// address: 0x4004802c + /// I2C Interrupt Status Register\n\n + /// Each bit in this register has a corresponding mask bit in the IC_INTR_MASK + /// register. These bits are cleared by reading the matching interrupt clear + /// register. The unmasked raw versions of these bits are available in the + /// IC_RAW_INTR_STAT register. + pub const IC_INTR_STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n + /// Reset value: 0x0 + R_RX_UNDER: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n + /// Reset value: 0x0 + R_RX_OVER: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n + /// Reset value: 0x0 + R_RX_FULL: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n + /// Reset value: 0x0 + R_TX_OVER: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n + /// Reset value: 0x0 + R_TX_EMPTY: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n + /// Reset value: 0x0 + R_RD_REQ: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n + /// Reset value: 0x0 + R_TX_ABRT: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n + /// Reset value: 0x0 + R_RX_DONE: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n + /// Reset value: 0x0 + R_ACTIVITY: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n + /// Reset value: 0x0 + R_STOP_DET: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n + /// Reset value: 0x0 + R_START_DET: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n + /// Reset value: 0x0 + R_GEN_CALL: u1, + /// See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n + /// Reset value: 0x0 + R_RESTART_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + }), base_address + 0x2c); + + /// address: 0x40048030 + /// I2C Interrupt Mask Register.\n\n + /// These bits mask their corresponding interrupt status bits. This register is + /// active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the + /// interrupt. + pub const IC_INTR_MASK = @intToPtr(*volatile Mmio(32, packed struct { + /// This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_RX_UNDER: u1, + /// This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_RX_OVER: u1, + /// This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_RX_FULL: u1, + /// This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_TX_OVER: u1, + /// This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_TX_EMPTY: u1, + /// This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_RD_REQ: u1, + /// This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_TX_ABRT: u1, + /// This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_RX_DONE: u1, + /// This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x0 + M_ACTIVITY: u1, + /// This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x0 + M_STOP_DET: u1, + /// This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x0 + M_START_DET: u1, + /// This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x1 + M_GEN_CALL: u1, + /// This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n + /// Reset value: 0x0 + M_RESTART_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + }), base_address + 0x30); + + /// address: 0x40048034 + /// I2C Raw Interrupt Status Register\n\n + /// Unlike the IC_INTR_STAT register, these bits are not masked so they always show + /// the true status of the DW_apb_i2c. + pub const IC_RAW_INTR_STAT = @intToPtr(*volatile Mmio(32, packed struct { + /// Set if the processor attempts to read the receive buffer when it is empty by + /// reading from the IC_DATA_CMD register. If the module is disabled + /// (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state + /// machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n + /// Reset value: 0x0 + RX_UNDER: u1, + /// Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an + /// additional byte is received from an external I2C device. The DW_apb_i2c + /// acknowledges this, but any data bytes received after the FIFO is full are lost. + /// If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the + /// master or slave state machines go into idle, and when ic_en goes to 0, this + /// interrupt is cleared.\n\n + /// Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to + /// HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never + /// overflows.\n\n + /// Reset value: 0x0 + RX_OVER: u1, + /// Set when the receive buffer reaches or goes above the RX_TL threshold in the + /// IC_RX_TL register. It is automatically cleared by hardware when buffer level + /// goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX + /// FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this + /// bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of + /// the activity that continues.\n\n + /// Reset value: 0x0 + RX_FULL: u1, + /// Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and + /// the processor attempts to issue another I2C command by writing to the + /// IC_DATA_CMD register. When the module is disabled, this bit keeps its level + /// until the master or slave state machines go into idle, and when ic_en goes to 0, + /// this interrupt is cleared.\n\n + /// Reset value: 0x0 + TX_OVER: u1, + /// The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL + /// selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 + /// when the transmit buffer is at or below the threshold value set in the IC_TX_TL + /// register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit + /// buffer is at or below the threshold value set in the IC_TX_TL register and the + /// transmission of the address/data from the internal shift register for the most + /// recently popped command is completed. It is automatically cleared by hardware + /// when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, + /// the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no + /// data within it, so this bit is set to 1, provided there is activity in the + /// master or slave state machines. When there is no longer any activity, then with + /// ic_en=0, this bit is set to 0.\n\n + /// Reset value: 0x0. + TX_EMPTY: u1, + /// This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master + /// is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in + /// a wait state (SCL=0) until this interrupt is serviced, which means that the + /// slave has been addressed by a remote master that is asking for data to be + /// transferred. The processor must respond to this interrupt and then write the + /// requested data to the IC_DATA_CMD register. This bit is set to 0 just after the + /// processor reads the IC_CLR_RD_REQ register.\n\n + /// Reset value: 0x0 + RD_REQ: u1, + /// This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete + /// the intended actions on the contents of the transmit FIFO. This situation can + /// occur both as an I2C master or an I2C slave, and is referred to as a 'transmit + /// abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the + /// reason why the transmit abort takes places.\n\n + /// Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever + /// there is a transmit abort caused by any of the events tracked by the + /// IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the + /// register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is + /// then ready to accept more data bytes from the APB interface.\n\n + /// Reset value: 0x0 + TX_ABRT: u1, + /// When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if + /// the master does not acknowledge a transmitted byte. This occurs on the last byte + /// of the transmission, indicating that the transmission is done.\n\n + /// Reset value: 0x0 + RX_DONE: u1, + /// This bit captures DW_apb_i2c activity and stays set until it is cleared. There + /// are four ways to clear it: - Disabling the DW_apb_i2c - Reading the + /// IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once + /// this bit is set, it stays set unless one of the four methods is used to clear + /// it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, + /// indicating that there was activity on the bus.\n\n + /// Reset value: 0x0 + ACTIVITY: u1, + /// Indicates whether a STOP condition has occurred on the I2C interface regardless + /// of whether DW_apb_i2c is operating in slave or master mode.\n\n + /// In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET + /// interrupt will be issued only if slave is addressed. Note: During a general call + /// address, this slave does not issue a STOP_DET interrupt if + /// STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call + /// address by generating ACK. The STOP_DET interrupt is generated only when the + /// transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 + /// (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether + /// it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 + /// (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master + /// is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt + /// will be issued irrespective of whether master is active or not. Reset value: 0x0 + STOP_DET: u1, + /// Indicates whether a START or RESTART condition has occurred on the I2C interface + /// regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n + /// Reset value: 0x0 + START_DET: u1, + /// Set only when a General Call address is received and it is acknowledged. It + /// stays set until it is cleared either by disabling DW_apb_i2c or when the CPU + /// reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data + /// in the Rx buffer.\n\n + /// Reset value: 0x0 + GEN_CALL: u1, + /// Indicates whether a RESTART condition has occurred on the I2C interface when + /// DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled + /// only when IC_SLV_RESTART_DET_EN=1.\n\n + /// Note: However, in high-speed mode or during a START BYTE transfer, the RESTART + /// comes before the address field as per the I2C protocol. In this case, the slave + /// is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does + /// not generate the RESTART_DET interrupt.\n\n + /// Reset value: 0x0 + RESTART_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + }), base_address + 0x34); + + /// address: 0x40048038 + /// I2C Receive FIFO Threshold Register + pub const IC_RX_TL = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive FIFO Threshold Level.\n\n + /// Controls the level of entries (or above) that triggers the RX_FULL interrupt + /// (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the + /// additional restriction that hardware does not allow this value to be set to a + /// value larger than the depth of the buffer. If an attempt is made to do that, the + /// actual value set will be the maximum depth of the buffer. A value of 0 sets the + /// threshold for 1 entry, and a value of 255 sets the threshold for 256 entries. + RX_TL: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x38); + + /// address: 0x4004803c + /// I2C Transmit FIFO Threshold Register + pub const IC_TX_TL = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO Threshold Level.\n\n + /// Controls the level of entries (or below) that trigger the TX_EMPTY interrupt + /// (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the + /// additional restriction that it may not be set to value larger than the depth of + /// the buffer. If an attempt is made to do that, the actual value set will be the + /// maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and + /// a value of 255 sets the threshold for 255 entries. + TX_TL: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x3c); + + /// address: 0x40048040 + /// Clear Combined and Individual Interrupt Register + pub const IC_CLR_INTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the combined interrupt, all individual interrupts, + /// and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable + /// interrupts but software clearable interrupts. Refer to Bit 9 of the + /// IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n + /// Reset value: 0x0 + CLR_INTR: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x40); + + /// address: 0x40048044 + /// Clear RX_UNDER Interrupt Register + pub const IC_CLR_RX_UNDER = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the RX_UNDER interrupt (bit 0) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_RX_UNDER: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x44); + + /// address: 0x40048048 + /// Clear RX_OVER Interrupt Register + pub const IC_CLR_RX_OVER = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the RX_OVER interrupt (bit 1) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_RX_OVER: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x48); + + /// address: 0x4004804c + /// Clear TX_OVER Interrupt Register + pub const IC_CLR_TX_OVER = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the TX_OVER interrupt (bit 3) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_TX_OVER: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x4c); + + /// address: 0x40048050 + /// Clear RD_REQ Interrupt Register + pub const IC_CLR_RD_REQ = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT + /// register.\n\n + /// Reset value: 0x0 + CLR_RD_REQ: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x50); + + /// address: 0x40048054 + /// Clear TX_ABRT Interrupt Register + pub const IC_CLR_TX_ABRT = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the TX_ABRT interrupt (bit 6) of the + /// IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also + /// releases the TX FIFO from the flushed/reset state, allowing more writes to the + /// TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to + /// clearing IC_TX_ABRT_SOURCE.\n\n + /// Reset value: 0x0 + CLR_TX_ABRT: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x54); + + /// address: 0x40048058 + /// Clear RX_DONE Interrupt Register + pub const IC_CLR_RX_DONE = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the RX_DONE interrupt (bit 7) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_RX_DONE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x58); + + /// address: 0x4004805c + /// Clear ACTIVITY Interrupt Register + pub const IC_CLR_ACTIVITY = @intToPtr(*volatile Mmio(32, packed struct { + /// Reading this register clears the ACTIVITY interrupt if the I2C is not active + /// anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt + /// bit continues to be set. It is automatically cleared by hardware if the module + /// is disabled and if there is no further activity on the bus. The value read from + /// this register to get status of the ACTIVITY interrupt (bit 8) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_ACTIVITY: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x5c); + + /// address: 0x40048060 + /// Clear STOP_DET Interrupt Register + pub const IC_CLR_STOP_DET = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the STOP_DET interrupt (bit 9) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_STOP_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x60); + + /// address: 0x40048064 + /// Clear START_DET Interrupt Register + pub const IC_CLR_START_DET = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the START_DET interrupt (bit 10) of the + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_START_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x64); + + /// address: 0x40048068 + /// Clear GEN_CALL Interrupt Register + pub const IC_CLR_GEN_CALL = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT + /// register.\n\n + /// Reset value: 0x0 + CLR_GEN_CALL: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x68); + + /// address: 0x4004806c + /// I2C Enable Register + pub const IC_ENABLE = @intToPtr(*volatile Mmio(32, packed struct { + /// Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX + /// FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable + /// DW_apb_i2c while it is active. However, it is important that care be taken to + /// ensure that DW_apb_i2c is disabled properly. A recommended procedure is + /// described in 'Disabling DW_apb_i2c'.\n\n + /// When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get + /// flushed. - Status bits in the IC_INTR_STAT register are still active until + /// DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well + /// as deletes the contents of the transmit buffer after the current transfer is + /// complete. If the module is receiving, the DW_apb_i2c stops the current transfer + /// at the end of the current byte and does not acknowledge the transfer.\n\n + /// In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to + /// asynchronous (1), there is a two ic_clk delay when enabling or disabling the + /// DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to + /// 'Disabling DW_apb_i2c'\n\n + /// Reset value: 0x0 + ENABLE: u1, + /// When set, the controller initiates the transfer abort. - 0: ABORT not initiated + /// or ABORT done - 1: ABORT operation in progress The software can abort the I2C + /// transfer in master mode by setting this bit. The software can set this bit only + /// when ENABLE is already set; otherwise, the controller ignores any write to ABORT + /// bit. The software cannot clear the ABORT bit once set. In response to an ABORT, + /// the controller issues a STOP and flushes the Tx FIFO after completing the + /// current transfer, then sets the TX_ABORT interrupt after the abort operation. + /// The ABORT bit is cleared automatically after the abort operation.\n\n + /// For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C + /// Transfers'.\n\n + /// Reset value: 0x0 + ABORT: u1, + /// In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx + /// FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus + /// automatically, as soon as the first data is available in the Tx FIFO. Note: To + /// block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx + /// FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). + /// Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit + /// is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT + TX_CMD_BLOCK: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + }), base_address + 0x6c); + + /// address: 0x40048070 + /// I2C Status Register\n\n + /// This is a read-only register used to indicate the current transfer status and + /// FIFO status. The status register may be read at any time. None of the bits in + /// this register request an interrupt.\n\n + /// When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits + /// 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state + /// machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0 + pub const IC_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// I2C Activity Status. Reset value: 0x0 + ACTIVITY: u1, + /// Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty + /// locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: + /// Transmit FIFO is not full Reset value: 0x1 + TFNF: u1, + /// Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this + /// bit is set. When it contains one or more valid entries, this bit is cleared. + /// This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - + /// 1: Transmit FIFO is empty Reset value: 0x1 + TFE: u1, + /// Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or + /// more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is + /// empty - 1: Receive FIFO is not empty Reset value: 0x0 + RFNE: u1, + /// Receive FIFO Completely Full. When the receive FIFO is completely full, this bit + /// is set. When the receive FIFO contains one or more empty location, this bit is + /// cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: + /// 0x0 + RFF: u1, + /// Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in + /// the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master + /// part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the + /// Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is + /// the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n + /// Reset value: 0x0 + MST_ACTIVITY: u1, + /// Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in + /// the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave + /// part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the + /// Slave part of DW_apb_i2c is Active Reset value: 0x0 + SLV_ACTIVITY: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + }), base_address + 0x70); + + /// address: 0x40048074 + /// I2C Transmit FIFO Level Register This register contains the number of valid data + /// entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is + /// disabled - There is a transmit abort - that is, TX_ABRT bit is set in the + /// IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register + /// increments whenever data is placed into the transmit FIFO and decrements when + /// data is taken from the transmit FIFO. + pub const IC_TXFLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit FIFO Level. Contains the number of valid data entries in the transmit + /// FIFO.\n\n + /// Reset value: 0x0 + TXFLR: u5, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + }), base_address + 0x74); + + /// address: 0x40048078 + /// I2C Receive FIFO Level Register This register contains the number of valid data + /// entries in the receive FIFO buffer. It is cleared whenever: - The I2C is + /// disabled - Whenever there is a transmit abort caused by any of the events + /// tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed + /// into the receive FIFO and decrements when data is taken from the receive FIFO. + pub const IC_RXFLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive FIFO Level. Contains the number of valid data entries in the receive + /// FIFO.\n\n + /// Reset value: 0x0 + RXFLR: u5, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + }), base_address + 0x78); + + /// address: 0x4004807c + /// I2C SDA Hold Time Length Register\n\n + /// The bits [15:0] of this register are used to control the hold time of SDA during + /// transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n + /// The bits [23:16] of this register are used to extend the SDA transition (if any) + /// whenever SCL is HIGH in the receiver in either master or slave mode.\n\n + /// Writes to this register succeed only when IC_ENABLE[0]=0.\n\n + /// The values in this register are in units of ic_clk period. The value programmed + /// in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one + /// cycle in master mode, seven cycles in slave mode) for the value to be + /// implemented.\n\n + /// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at + /// any time the duration of the low part of scl. Therefore the programmed value + /// cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low + /// part of the scl period measured in ic_clk cycles. + pub const IC_SDA_HOLD = @intToPtr(*volatile Mmio(32, packed struct { + /// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts + /// as a transmitter.\n\n + /// Reset value: IC_DEFAULT_SDA_HOLD[15:0]. + IC_SDA_TX_HOLD: u16, + /// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts + /// as a receiver.\n\n + /// Reset value: IC_DEFAULT_SDA_HOLD[23:16]. + IC_SDA_RX_HOLD: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x7c); + + /// address: 0x40048080 + /// I2C Transmit Abort Source Register\n\n + /// This register has 32 bits that indicate the source of the TX_ABRT bit. Except + /// for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the + /// IC_CLR_INTR register is read. To clear Bit 9, the source of the + /// ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), + /// the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be + /// cleared (IC_TAR[10]).\n\n + /// Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared + /// in the same manner as other bits in this register. If the source of the + /// ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 + /// clears for one cycle and is then re-asserted. + pub const IC_TX_ABRT_SOURCE = @intToPtr(*volatile Mmio(32, packed struct { + /// This field indicates that the Master is in 7-bit addressing mode and the address + /// sent was not acknowledged by any slave.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + ABRT_7B_ADDR_NOACK: u1, + /// This field indicates that the Master is in 10-bit address mode and the first + /// 10-bit address byte was not acknowledged by any slave.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + ABRT_10ADDR1_NOACK: u1, + /// This field indicates that the Master is in 10-bit address mode and that the + /// second address byte of the 10-bit address was not acknowledged by any slave.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + ABRT_10ADDR2_NOACK: u1, + /// This field indicates the master-mode only bit. When the master receives an + /// acknowledgement for the address, but when it sends data byte(s) following the + /// address, it did not receive an acknowledge from the remote slave(s).\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter + ABRT_TXDATA_NOACK: u1, + /// This field indicates that DW_apb_i2c in master mode has sent a General Call and + /// no slave on the bus acknowledged the General Call.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter + ABRT_GCALL_NOACK: u1, + /// This field indicates that DW_apb_i2c in the master mode has sent a General Call + /// but the user programmed the byte following the General Call to be a read from + /// the bus (IC_DATA_CMD[9] is set to 1).\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter + ABRT_GCALL_READ: u1, + /// This field indicates that the Master is in High Speed mode and the High Speed + /// Master code was acknowledged (wrong behavior).\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master + ABRT_HS_ACKDET: u1, + /// This field indicates that the Master has sent a START Byte and the START Byte + /// was acknowledged (wrong behavior).\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master + ABRT_SBYTE_ACKDET: u1, + /// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) + /// =0) and the user is trying to use the master to transfer data in High Speed + /// mode.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + ABRT_HS_NORSTRT: u1, + /// To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; + /// restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared + /// (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the + /// source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the + /// same manner as other bits in this register. If the source of the + /// ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 + /// clears for one cycle and then gets reasserted. When this field is set to 1, the + /// restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to + /// send a START Byte.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master + ABRT_SBYTE_NORSTRT: u1, + /// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) + /// =0) and the master sends a read command in 10-bit addressing mode.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Receiver + ABRT_10B_RD_NORSTRT: u1, + /// This field indicates that the User tries to initiate a Master operation with the + /// Master mode disabled.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver + ABRT_MASTER_DIS: u1, + /// This field specifies that the Master has lost arbitration, or if + /// IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost + /// arbitration.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + ARB_LOST: u1, + /// This field specifies that the Slave has received a read command and some data + /// exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data + /// in TX FIFO.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Slave-Transmitter + ABRT_SLVFLUSH_TXFIFO: u1, + /// This field indicates that a Slave has lost the bus while transmitting data to a + /// remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though + /// the slave never 'owns' the bus, something could go wrong on the bus. This is a + /// fail safe check. For instance, during a data transmission at the low-to-high + /// transition of SCL, if what is on the data bus is not what is supposed to be + /// transmitted, then DW_apb_i2c no longer own the bus.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Slave-Transmitter + ABRT_SLV_ARBLOST: u1, + /// 1: When the processor side responds to a slave mode request for data to be + /// transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD + /// register.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Slave-Transmitter + ABRT_SLVRD_INTX: u1, + /// This is a master-mode-only bit. Master has detected the transfer abort + /// (IC_ENABLE[1])\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter + ABRT_USER_ABRT: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// This field indicates the number of Tx FIFO Data Commands which are flushed due + /// to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n + /// Reset value: 0x0\n\n + /// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter + TX_FLUSH_CNT: u9, + }), base_address + 0x80); + + /// address: 0x40048084 + /// Generate Slave Data NACK Register\n\n + /// The register is used to generate a NACK for the data part of a transfer when + /// DW_apb_i2c is acting as a slave-receiver. This register only exists when the + /// IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this + /// register does not exist and writing to the register's address has no effect.\n\n + /// A write can occur on this register if both of the following conditions are met: + /// - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive + /// (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for + /// the internal slv_activity signal; the user should poll this before writing the + /// ic_slv_data_nack_only bit. + pub const IC_SLV_DATA_NACK_ONLY = @intToPtr(*volatile Mmio(32, packed struct { + /// Generate NACK. This NACK generation only occurs when DW_apb_i2c is a + /// slave-receiver. If this register is set to a value of 1, it can only generate a + /// NACK after a data byte is received; hence, the data transfer is aborted and the + /// data received is not pushed to the receive buffer.\n\n + /// When the register is set to a value of 0, it generates NACK/ACK, depending on + /// normal criteria. - 1: generate NACK after data byte received - 0: generate + /// NACK/ACK normally Reset value: 0x0 + NACK: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x84); + + /// address: 0x40048088 + /// DMA Control Register\n\n + /// The register is used to enable the DMA Controller interface operation. There is + /// a separate bit for transmit and receive. This can be programmed regardless of + /// the state of IC_ENABLE. + pub const IC_DMA_CR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. + /// Reset value: 0x0 + RDMAE: u1, + /// Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. + /// Reset value: 0x0 + TDMAE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x88); + + /// address: 0x4004808c + /// DMA Transmit Data Level Register + pub const IC_DMA_TDLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Transmit Data Level. This bit field controls the level at which a DMA request is + /// made by the transmit logic. It is equal to the watermark level; that is, the + /// dma_tx_req signal is generated when the number of valid data entries in the + /// transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n + /// Reset value: 0x0 + DMATDL: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x8c); + + /// address: 0x40048090 + /// I2C Receive Data Level Register + pub const IC_DMA_RDLR = @intToPtr(*volatile Mmio(32, packed struct { + /// Receive Data Level. This bit field controls the level at which a DMA request is + /// made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req + /// is generated when the number of valid data entries in the receive FIFO is equal + /// to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is + /// 0, then dma_rx_req is asserted when 1 or more data entries are present in the + /// receive FIFO.\n\n + /// Reset value: 0x0 + DMARDL: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x90); + + /// address: 0x40048094 + /// I2C SDA Setup Register\n\n + /// This register controls the amount of time delay (in terms of number of ic_clk + /// clock periods) introduced in the rising edge of SCL - relative to SDA changing - + /// when DW_apb_i2c services a read request in a slave-transmitter operation. The + /// relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus + /// Specification. This register must be programmed with a value equal to or greater + /// than 2.\n\n + /// Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n + /// Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * + /// (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they + /// should program a value of 11. The IC_SDA_SETUP register is only used by the + /// DW_apb_i2c when operating as a slave transmitter. + pub const IC_SDA_SETUP = @intToPtr(*volatile Mmio(32, packed struct { + /// SDA Setup. It is recommended that if the required delay is 1000ns, then for an + /// ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. + /// IC_SDA_SETUP must be programmed with a minimum value of 2. + SDA_SETUP: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x94); + + /// address: 0x40048098 + /// I2C ACK General Call Register\n\n + /// The register controls whether DW_apb_i2c responds with a ACK or NACK when it + /// receives an I2C General Call address.\n\n + /// This register is applicable only when the DW_apb_i2c is in slave mode. + pub const IC_ACK_GENERAL_CALL = @intToPtr(*volatile Mmio(32, packed struct { + /// ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting + /// ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with + /// a NACK (by negating ic_data_oe). + ACK_GEN_CALL: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x98); + + /// address: 0x4004809c + /// I2C Enable Status Register\n\n + /// The register is used to report the DW_apb_i2c hardware status when the + /// IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is + /// disabled.\n\n + /// If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced + /// to 1.\n\n + /// If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is + /// read as '0'.\n\n + /// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read + /// as 0 because disabling the DW_apb_i2c depends on I2C bus activities. + pub const IC_ENABLE_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// ic_en Status. This bit always reflects the value driven on the output port + /// ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When + /// read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely + /// read this bit anytime. When this bit is read as 0, the CPU can safely read + /// SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n + /// Reset value: 0x0 + IC_EN: u1, + /// Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential + /// or active Slave operation has been aborted due to the setting bit 0 of the + /// IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the + /// IC_ENABLE register while:\n\n + /// (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation + /// from a remote master;\n\n + /// OR,\n\n + /// (b) address and data bytes of the Slave-Receiver operation from a remote + /// master.\n\n + /// When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an + /// I2C transfer, irrespective of whether the I2C address matches the slave address + /// set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before + /// IC_ENABLE is set to 0 but has not taken effect.\n\n + /// Note: If the remote I2C master terminates the transfer with a STOP condition + /// before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been + /// set to 0, then this bit will also be set to 1.\n\n + /// When read as 0, DW_apb_i2c is deemed to have been disabled when there is master + /// activity, or when the I2C bus is idle.\n\n + /// Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n + /// Reset value: 0x0 + SLV_DISABLED_WHILE_BUSY: u1, + /// Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has + /// been aborted with at least one data byte received from an I2C transfer due to + /// the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed + /// to have been actively engaged in an aborted I2C transfer (with matching address) + /// and the data phase of the I2C transfer has been entered, even though a data byte + /// has been responded with a NACK.\n\n + /// Note: If the remote I2C master terminates the transfer with a STOP condition + /// before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been + /// set to 0, then this bit is also set to 1.\n\n + /// When read as 0, DW_apb_i2c is deemed to have been disabled without being + /// actively involved in the data phase of a Slave-Receiver transfer.\n\n + /// Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n + /// Reset value: 0x0 + SLV_RX_DATA_LOST: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + }), base_address + 0x9c); + + /// address: 0x400480a0 + /// I2C SS, FS or FM+ spike suppression limit\n\n + /// This register is used to store the duration, measured in ic_clk cycles, of the + /// longest spike that is filtered out by the spike suppression logic when the + /// component is operating in SS, FS or FM+ modes. The relevant I2C requirement is + /// tSP (table 4) as detailed in the I2C Bus Specification. This register must be + /// programmed with a minimum value of 1. + pub const IC_FS_SPKLEN = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xa0); + + /// address: 0x400480a8 + /// Clear RESTART_DET Interrupt Register + pub const IC_CLR_RESTART_DET = @intToPtr(*volatile Mmio(32, packed struct { + /// Read this register to clear the RESTART_DET interrupt (bit 12) of + /// IC_RAW_INTR_STAT register.\n\n + /// Reset value: 0x0 + CLR_RESTART_DET: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0xa8); + + /// address: 0x400480f4 + /// Component Parameter Register 1\n\n + /// Note This register is not implemented and therefore reads as 0. If it was + /// implemented it would be a constant read-only register that contains encoded + /// information about the component's parameter settings. Fields shown below are the + /// settings for those parameters + pub const IC_COMP_PARAM_1 = @intToPtr(*volatile Mmio(32, packed struct { + /// APB data bus width is 32 bits + APB_DATA_WIDTH: u2, + /// MAX SPEED MODE = FAST MODE + MAX_SPEED_MODE: u2, + /// Programmable count values for each mode. + HC_COUNT_VALUES: u1, + /// COMBINED Interrupt outputs + INTR_IO: u1, + /// DMA handshaking signals are enabled + HAS_DMA: u1, + /// Encoded parameters not visible + ADD_ENCODED_PARAMS: u1, + /// RX Buffer Depth = 16 + RX_BUFFER_DEPTH: u8, + /// TX Buffer Depth = 16 + TX_BUFFER_DEPTH: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0xf4); + + /// address: 0x400480f8 + /// I2C Component Version Register + pub const IC_COMP_VERSION = @intToPtr(*volatile u32, base_address + 0xf8); + + /// address: 0x400480fc + /// I2C Component Type Register + pub const IC_COMP_TYPE = @intToPtr(*volatile u32, base_address + 0xfc); + }; + + /// Control and data interface to SAR ADC + pub const ADC = struct { + pub const base_address = 0x4004c000; + pub const version = "2"; + + /// address: 0x4004c000 + /// ADC Control and Status + pub const CS = @intToPtr(*volatile Mmio(32, packed struct { + /// Power on ADC and enable its clock.\n + /// 1 - enabled. 0 - disabled. + EN: u1, + /// Power on temperature sensor. 1 - enabled. 0 - disabled. + TS_EN: u1, + /// Start a single conversion. Self-clearing. Ignored if start_many is asserted. + START_ONCE: u1, + /// Continuously perform conversions whilst this bit is 1. A new conversion will + /// start immediately after the previous finishes. + START_MANY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// 1 if the ADC is ready to start a new conversion. Implies any previous conversion + /// has completed.\n + /// 0 whilst conversion in progress. + READY: u1, + /// The most recent ADC conversion encountered an error; result is undefined or + /// noisy. + ERR: u1, + /// Some past ADC conversion encountered an error. Write 1 to clear. + ERR_STICKY: u1, + reserved4: u1 = 0, + /// Select analog mux input. Updated automatically in round-robin mode. + AINSEL: u3, + reserved5: u1 = 0, + /// Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n + /// Otherwise, the ADC will cycle through each enabled channel in a round-robin + /// fashion.\n + /// The first channel to be sampled will be the one currently indicated by AINSEL.\n + /// AINSEL will be updated after each conversion with the newly-selected channel. + RROBIN: u5, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + }), base_address + 0x0); + + /// address: 0x4004c004 + /// Result of most recent ADC conversion + pub const RESULT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x4); + + /// address: 0x4004c008 + /// FIFO control and status + pub const FCS = @intToPtr(*volatile Mmio(32, packed struct { + /// If 1: write result to the FIFO after each conversion. + EN: u1, + /// If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte + /// buffers. + SHIFT: u1, + /// If 1: conversion error bit appears in the FIFO alongside the result + ERR: u1, + /// If 1: assert DMA requests when FIFO contains data + DREQ_EN: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + EMPTY: u1, + FULL: u1, + /// 1 if the FIFO has been underflowed. Write 1 to clear. + UNDER: u1, + /// 1 if the FIFO has been overflowed. Write 1 to clear. + OVER: u1, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// The number of conversion results currently waiting in the FIFO + LEVEL: u4, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// DREQ/IRQ asserted when level >= threshold + THRESH: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + }), base_address + 0x8); + + /// address: 0x4004c00c + /// Conversion result FIFO + pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct { + VAL: u12, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// 1 if this particular sample experienced a conversion error. Remains in the same + /// location if the sample is shifted. + ERR: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0xc); + + /// address: 0x4004c010 + /// Clock divider. If non-zero, CS_START_MANY will start conversions\n + /// at regular intervals rather than back-to-back.\n + /// The divider is reset when either of these fields are written.\n + /// Total period is 1 + INT + FRAC / 256 + pub const DIV = @intToPtr(*volatile Mmio(32, packed struct { + /// Fractional part of clock divisor. First-order delta-sigma. + FRAC: u8, + /// Integer part of clock divisor. + INT: u16, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x10); + + /// address: 0x4004c014 + /// Raw Interrupts + pub const INTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Triggered when the sample FIFO reaches a certain level.\n + /// This level can be programmed via the FCS_THRESH field. + FIFO: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x14); + + /// address: 0x4004c018 + /// Interrupt Enable + pub const INTE = @intToPtr(*volatile Mmio(32, packed struct { + /// Triggered when the sample FIFO reaches a certain level.\n + /// This level can be programmed via the FCS_THRESH field. + FIFO: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x18); + + /// address: 0x4004c01c + /// Interrupt Force + pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Triggered when the sample FIFO reaches a certain level.\n + /// This level can be programmed via the FCS_THRESH field. + FIFO: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x1c); + + /// address: 0x4004c020 + /// Interrupt status after masking & forcing + pub const INTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Triggered when the sample FIFO reaches a certain level.\n + /// This level can be programmed via the FCS_THRESH field. + FIFO: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x20); + }; + + /// Simple PWM + pub const PWM = struct { + pub const base_address = 0x40050000; + pub const version = "1"; + + /// address: 0x40050000 + /// Control and status register + pub const CH0_CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable the PWM channel. + EN: u1, + /// 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT: u1, + /// Invert output A + A_INV: u1, + /// Invert output B + B_INV: u1, + DIVMODE: u2, + /// Retard the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running. + PH_RET: u1, + /// Advance the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running\n + /// at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40050004 + /// INT and FRAC form a fixed-point fractional number.\n + /// Counting rate is system clock frequency divided by this number.\n + /// Fractional division uses simple 1st-order sigma-delta. + pub const CH0_DIV = @intToPtr(*volatile Mmio(32, packed struct { + FRAC: u4, + INT: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40050008 + /// Direct access to the PWM counter + pub const CH0_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x8); + + /// address: 0x4005000c + /// Counter compare values + pub const CH0_CC = @intToPtr(*volatile Mmio(32, packed struct { + A: u16, + B: u16, + }), base_address + 0xc); + + /// address: 0x40050010 + /// Counter wrap value + pub const CH0_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x10); + + /// address: 0x40050014 + /// Control and status register + pub const CH1_CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable the PWM channel. + EN: u1, + /// 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT: u1, + /// Invert output A + A_INV: u1, + /// Invert output B + B_INV: u1, + DIVMODE: u2, + /// Retard the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running. + PH_RET: u1, + /// Advance the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running\n + /// at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x14); + + /// address: 0x40050018 + /// INT and FRAC form a fixed-point fractional number.\n + /// Counting rate is system clock frequency divided by this number.\n + /// Fractional division uses simple 1st-order sigma-delta. + pub const CH1_DIV = @intToPtr(*volatile Mmio(32, packed struct { + FRAC: u4, + INT: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x18); + + /// address: 0x4005001c + /// Direct access to the PWM counter + pub const CH1_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c); + + /// address: 0x40050020 + /// Counter compare values + pub const CH1_CC = @intToPtr(*volatile Mmio(32, packed struct { + A: u16, + B: u16, + }), base_address + 0x20); + + /// address: 0x40050024 + /// Counter wrap value + pub const CH1_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24); + + /// address: 0x40050028 + /// Control and status register + pub const CH2_CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable the PWM channel. + EN: u1, + /// 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT: u1, + /// Invert output A + A_INV: u1, + /// Invert output B + B_INV: u1, + DIVMODE: u2, + /// Retard the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running. + PH_RET: u1, + /// Advance the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running\n + /// at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x28); + + /// address: 0x4005002c + /// INT and FRAC form a fixed-point fractional number.\n + /// Counting rate is system clock frequency divided by this number.\n + /// Fractional division uses simple 1st-order sigma-delta. + pub const CH2_DIV = @intToPtr(*volatile Mmio(32, packed struct { + FRAC: u4, + INT: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x2c); + + /// address: 0x40050030 + /// Direct access to the PWM counter + pub const CH2_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x30); + + /// address: 0x40050034 + /// Counter compare values + pub const CH2_CC = @intToPtr(*volatile Mmio(32, packed struct { + A: u16, + B: u16, + }), base_address + 0x34); + + /// address: 0x40050038 + /// Counter wrap value + pub const CH2_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38); + + /// address: 0x4005003c + /// Control and status register + pub const CH3_CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable the PWM channel. + EN: u1, + /// 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT: u1, + /// Invert output A + A_INV: u1, + /// Invert output B + B_INV: u1, + DIVMODE: u2, + /// Retard the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running. + PH_RET: u1, + /// Advance the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running\n + /// at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x3c); + + /// address: 0x40050040 + /// INT and FRAC form a fixed-point fractional number.\n + /// Counting rate is system clock frequency divided by this number.\n + /// Fractional division uses simple 1st-order sigma-delta. + pub const CH3_DIV = @intToPtr(*volatile Mmio(32, packed struct { + FRAC: u4, + INT: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x40); + + /// address: 0x40050044 + /// Direct access to the PWM counter + pub const CH3_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x44); + + /// address: 0x40050048 + /// Counter compare values + pub const CH3_CC = @intToPtr(*volatile Mmio(32, packed struct { + A: u16, + B: u16, + }), base_address + 0x48); + + /// address: 0x4005004c + /// Counter wrap value + pub const CH3_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x4c); + + /// address: 0x40050050 + /// Control and status register + pub const CH4_CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable the PWM channel. + EN: u1, + /// 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT: u1, + /// Invert output A + A_INV: u1, + /// Invert output B + B_INV: u1, + DIVMODE: u2, + /// Retard the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running. + PH_RET: u1, + /// Advance the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running\n + /// at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x50); + + /// address: 0x40050054 + /// INT and FRAC form a fixed-point fractional number.\n + /// Counting rate is system clock frequency divided by this number.\n + /// Fractional division uses simple 1st-order sigma-delta. + pub const CH4_DIV = @intToPtr(*volatile Mmio(32, packed struct { + FRAC: u4, + INT: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x54); + + /// address: 0x40050058 + /// Direct access to the PWM counter + pub const CH4_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x58); + + /// address: 0x4005005c + /// Counter compare values + pub const CH4_CC = @intToPtr(*volatile Mmio(32, packed struct { + A: u16, + B: u16, + }), base_address + 0x5c); + + /// address: 0x40050060 + /// Counter wrap value + pub const CH4_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x60); + + /// address: 0x40050064 + /// Control and status register + pub const CH5_CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable the PWM channel. + EN: u1, + /// 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT: u1, + /// Invert output A + A_INV: u1, + /// Invert output B + B_INV: u1, + DIVMODE: u2, + /// Retard the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running. + PH_RET: u1, + /// Advance the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running\n + /// at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x64); + + /// address: 0x40050068 + /// INT and FRAC form a fixed-point fractional number.\n + /// Counting rate is system clock frequency divided by this number.\n + /// Fractional division uses simple 1st-order sigma-delta. + pub const CH5_DIV = @intToPtr(*volatile Mmio(32, packed struct { + FRAC: u4, + INT: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x68); + + /// address: 0x4005006c + /// Direct access to the PWM counter + pub const CH5_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x6c); + + /// address: 0x40050070 + /// Counter compare values + pub const CH5_CC = @intToPtr(*volatile Mmio(32, packed struct { + A: u16, + B: u16, + }), base_address + 0x70); + + /// address: 0x40050074 + /// Counter wrap value + pub const CH5_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x74); + + /// address: 0x40050078 + /// Control and status register + pub const CH6_CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable the PWM channel. + EN: u1, + /// 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT: u1, + /// Invert output A + A_INV: u1, + /// Invert output B + B_INV: u1, + DIVMODE: u2, + /// Retard the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running. + PH_RET: u1, + /// Advance the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running\n + /// at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x78); + + /// address: 0x4005007c + /// INT and FRAC form a fixed-point fractional number.\n + /// Counting rate is system clock frequency divided by this number.\n + /// Fractional division uses simple 1st-order sigma-delta. + pub const CH6_DIV = @intToPtr(*volatile Mmio(32, packed struct { + FRAC: u4, + INT: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x7c); + + /// address: 0x40050080 + /// Direct access to the PWM counter + pub const CH6_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x80); + + /// address: 0x40050084 + /// Counter compare values + pub const CH6_CC = @intToPtr(*volatile Mmio(32, packed struct { + A: u16, + B: u16, + }), base_address + 0x84); + + /// address: 0x40050088 + /// Counter wrap value + pub const CH6_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x88); + + /// address: 0x4005008c + /// Control and status register + pub const CH7_CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable the PWM channel. + EN: u1, + /// 1: Enable phase-correct modulation. 0: Trailing-edge + PH_CORRECT: u1, + /// Invert output A + A_INV: u1, + /// Invert output B + B_INV: u1, + DIVMODE: u2, + /// Retard the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running. + PH_RET: u1, + /// Advance the phase of the counter by 1 count, while it is running.\n + /// Self-clearing. Write a 1, and poll until low. Counter must be running\n + /// at less than full speed (div_int + div_frac / 16 > 1) + PH_ADV: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x8c); + + /// address: 0x40050090 + /// INT and FRAC form a fixed-point fractional number.\n + /// Counting rate is system clock frequency divided by this number.\n + /// Fractional division uses simple 1st-order sigma-delta. + pub const CH7_DIV = @intToPtr(*volatile Mmio(32, packed struct { + FRAC: u4, + INT: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x90); + + /// address: 0x40050094 + /// Direct access to the PWM counter + pub const CH7_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x94); + + /// address: 0x40050098 + /// Counter compare values + pub const CH7_CC = @intToPtr(*volatile Mmio(32, packed struct { + A: u16, + B: u16, + }), base_address + 0x98); + + /// address: 0x4005009c + /// Counter wrap value + pub const CH7_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x9c); + + /// address: 0x400500a0 + /// This register aliases the CSR_EN bits for all channels.\n + /// Writing to this register allows multiple channels to be enabled\n + /// or disabled simultaneously, so they can run in perfect sync.\n + /// For each channel, there is only one physical EN register bit,\n + /// which can be accessed through here or CHx_CSR. + pub const EN = @intToPtr(*volatile Mmio(32, packed struct { + CH0: u1, + CH1: u1, + CH2: u1, + CH3: u1, + CH4: u1, + CH5: u1, + CH6: u1, + CH7: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xa0); + + /// address: 0x400500a4 + /// Raw Interrupts + pub const INTR = @intToPtr(*volatile Mmio(32, packed struct { + CH0: u1, + CH1: u1, + CH2: u1, + CH3: u1, + CH4: u1, + CH5: u1, + CH6: u1, + CH7: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xa4); + + /// address: 0x400500a8 + /// Interrupt Enable + pub const INTE = @intToPtr(*volatile Mmio(32, packed struct { + CH0: u1, + CH1: u1, + CH2: u1, + CH3: u1, + CH4: u1, + CH5: u1, + CH6: u1, + CH7: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xa8); + + /// address: 0x400500ac + /// Interrupt Force + pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { + CH0: u1, + CH1: u1, + CH2: u1, + CH3: u1, + CH4: u1, + CH5: u1, + CH6: u1, + CH7: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xac); + + /// address: 0x400500b0 + /// Interrupt status after masking & forcing + pub const INTS = @intToPtr(*volatile Mmio(32, packed struct { + CH0: u1, + CH1: u1, + CH2: u1, + CH3: u1, + CH4: u1, + CH5: u1, + CH6: u1, + CH7: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0xb0); + }; + + /// Controls time and alarms\n + /// time is a 64 bit value indicating the time in usec since power-on\n + /// timeh is the top 32 bits of time & timel is the bottom 32 bits\n + /// to change time write to timelw before timehw\n + /// to read time read from timelr before timehr\n + /// An alarm is set by setting alarm_enable and writing to the corresponding alarm + /// register\n + /// When an alarm is pending, the corresponding alarm_running signal will be high\n + /// An alarm can be cancelled before it has finished by clearing the alarm_enable\n + /// When an alarm fires, the corresponding alarm_irq is set and alarm_running is + /// cleared\n + /// To clear the interrupt write a 1 to the corresponding alarm_irq + pub const TIMER = struct { + pub const base_address = 0x40054000; + pub const version = "1"; + + /// address: 0x40054000 + /// Write to bits 63:32 of time\n + /// always write timelw before timehw + pub const TIMEHW = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x40054004 + /// Write to bits 31:0 of time\n + /// writes do not get copied to time until timehw is written + pub const TIMELW = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x40054008 + /// Read from bits 63:32 of time\n + /// always read timelr before timehr + pub const TIMEHR = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x4005400c + /// Read from bits 31:0 of time + pub const TIMELR = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40054010 + /// Arm alarm 0, and configure the time it will fire.\n + /// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n + /// The alarm will disarm itself once it fires, and can\n + /// be disarmed early using the ARMED status register. + pub const ALARM0 = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40054014 + /// Arm alarm 1, and configure the time it will fire.\n + /// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n + /// The alarm will disarm itself once it fires, and can\n + /// be disarmed early using the ARMED status register. + pub const ALARM1 = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x40054018 + /// Arm alarm 2, and configure the time it will fire.\n + /// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n + /// The alarm will disarm itself once it fires, and can\n + /// be disarmed early using the ARMED status register. + pub const ALARM2 = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x4005401c + /// Arm alarm 3, and configure the time it will fire.\n + /// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n + /// The alarm will disarm itself once it fires, and can\n + /// be disarmed early using the ARMED status register. + pub const ALARM3 = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40054020 + /// Indicates the armed/disarmed status of each alarm.\n + /// A write to the corresponding ALARMx register arms the alarm.\n + /// Alarms automatically disarm upon firing, but writing ones here\n + /// will disarm immediately without waiting to fire. + pub const ARMED = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x20); + + /// address: 0x40054024 + /// Raw read from bits 63:32 of time (no side effects) + pub const TIMERAWH = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x40054028 + /// Raw read from bits 31:0 of time (no side effects) + pub const TIMERAWL = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x4005402c + /// Set bits high to enable pause when the corresponding debug ports are active + pub const DBGPAUSE = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + /// Pause when processor 0 is in debug mode + DBG0: u1, + /// Pause when processor 1 is in debug mode + DBG1: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + }), base_address + 0x2c); + + /// address: 0x40054030 + /// Set high to pause the timer + pub const PAUSE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x30); + + /// address: 0x40054034 + /// Raw Interrupts + pub const INTR = @intToPtr(*volatile Mmio(32, packed struct { + ALARM_0: u1, + ALARM_1: u1, + ALARM_2: u1, + ALARM_3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x34); + + /// address: 0x40054038 + /// Interrupt Enable + pub const INTE = @intToPtr(*volatile Mmio(32, packed struct { + ALARM_0: u1, + ALARM_1: u1, + ALARM_2: u1, + ALARM_3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x38); + + /// address: 0x4005403c + /// Interrupt Force + pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { + ALARM_0: u1, + ALARM_1: u1, + ALARM_2: u1, + ALARM_3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x3c); + + /// address: 0x40054040 + /// Interrupt status after masking & forcing + pub const INTS = @intToPtr(*volatile Mmio(32, packed struct { + ALARM_0: u1, + ALARM_1: u1, + ALARM_2: u1, + ALARM_3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x40); + }; + pub const WATCHDOG = struct { + pub const base_address = 0x40058000; + pub const version = "1"; + + /// address: 0x40058000 + /// Watchdog control\n + /// The rst_wdsel register determines which subsystems are reset when the watchdog + /// is triggered.\n + /// The watchdog can be triggered in software. + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset + /// will be triggered + TIME: u24, + /// Pause the watchdog timer when JTAG is accessing the bus fabric + PAUSE_JTAG: u1, + /// Pause the watchdog timer when processor 0 is in debug mode + PAUSE_DBG0: u1, + /// Pause the watchdog timer when processor 1 is in debug mode + PAUSE_DBG1: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// When not enabled the watchdog timer is paused + ENABLE: u1, + /// Trigger a watchdog reset + TRIGGER: u1, + }), base_address + 0x0); + + /// address: 0x40058004 + /// Load the watchdog timer. The maximum setting is 0xffffff which corresponds to + /// 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1). + pub const LOAD = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x4); + + /// address: 0x40058008 + /// Logs the reason for the last reset. Both bits are zero for the case of a + /// hardware reset. + pub const REASON = @intToPtr(*volatile Mmio(32, packed struct { + TIMER: u1, + FORCE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x8); + + /// address: 0x4005800c + /// Scratch register. Information persists through soft reset of the chip. + pub const SCRATCH0 = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40058010 + /// Scratch register. Information persists through soft reset of the chip. + pub const SCRATCH1 = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x40058014 + /// Scratch register. Information persists through soft reset of the chip. + pub const SCRATCH2 = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x40058018 + /// Scratch register. Information persists through soft reset of the chip. + pub const SCRATCH3 = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x4005801c + /// Scratch register. Information persists through soft reset of the chip. + pub const SCRATCH4 = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x40058020 + /// Scratch register. Information persists through soft reset of the chip. + pub const SCRATCH5 = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x40058024 + /// Scratch register. Information persists through soft reset of the chip. + pub const SCRATCH6 = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x40058028 + /// Scratch register. Information persists through soft reset of the chip. + pub const SCRATCH7 = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x4005802c + /// Controls the tick generator + pub const TICK = @intToPtr(*volatile Mmio(32, packed struct { + /// Total number of clk_tick cycles before the next tick. + CYCLES: u9, + /// start / stop tick generation + ENABLE: u1, + /// Is the tick generator running? + RUNNING: u1, + /// Count down timer: the remaining number clk_tick cycles before the next tick is + /// generated. + COUNT: u9, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + }), base_address + 0x2c); + }; + + /// Register block to control RTC + pub const RTC = struct { + pub const base_address = 0x4005c000; + pub const version = "1"; + + /// address: 0x4005c000 + /// Divider minus 1 for the 1 second counter. Safe to change the value when RTC is + /// not enabled. + pub const CLKDIV_M1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x0); + + /// address: 0x4005c004 + /// RTC setup register 0 + pub const SETUP_0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of the month (1..31) + DAY: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// Month (1..12) + MONTH: u4, + /// Year + YEAR: u12, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x4); + + /// address: 0x4005c008 + /// RTC setup register 1 + pub const SETUP_1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Seconds + SEC: u6, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// Minutes + MIN: u6, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// Hours + HOUR: u5, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + /// Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7 + DOTW: u3, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x8); + + /// address: 0x4005c00c + /// RTC Control and status + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable RTC + RTC_ENABLE: u1, + /// RTC enabled (running) + RTC_ACTIVE: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// Load RTC + LOAD: u1, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + /// If set, leapyear is forced off.\n + /// Useful for years divisible by 100 but not by 400 + FORCE_NOTLEAPYEAR: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + }), base_address + 0xc); + + /// address: 0x4005c010 + /// Interrupt setup register 0 + pub const IRQ_SETUP_0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of the month (1..31) + DAY: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// Month (1..12) + MONTH: u4, + /// Year + YEAR: u12, + /// Enable day matching + DAY_ENA: u1, + /// Enable month matching + MONTH_ENA: u1, + /// Enable year matching + YEAR_ENA: u1, + reserved3: u1 = 0, + /// Global match enable. Don't change any other value while this one is enabled + MATCH_ENA: u1, + MATCH_ACTIVE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + }), base_address + 0x10); + + /// address: 0x4005c014 + /// Interrupt setup register 1 + pub const IRQ_SETUP_1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Seconds + SEC: u6, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// Minutes + MIN: u6, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// Hours + HOUR: u5, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + /// Day of the week + DOTW: u3, + reserved7: u1 = 0, + /// Enable second matching + SEC_ENA: u1, + /// Enable minute matching + MIN_ENA: u1, + /// Enable hour matching + HOUR_ENA: u1, + /// Enable day of the week matching + DOTW_ENA: u1, + }), base_address + 0x14); + + /// address: 0x4005c018 + /// RTC register 1. + pub const RTC_1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Day of the month (1..31) + DAY: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// Month (1..12) + MONTH: u4, + /// Year + YEAR: u12, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x18); + + /// address: 0x4005c01c + /// RTC register 0\n + /// Read this before RTC 1! + pub const RTC_0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Seconds + SEC: u6, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// Minutes + MIN: u6, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// Hours + HOUR: u5, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + /// Day of the week + DOTW: u3, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x1c); + + /// address: 0x4005c020 + /// Raw Interrupts + pub const INTR = @intToPtr(*volatile Mmio(32, packed struct { + RTC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x20); + + /// address: 0x4005c024 + /// Interrupt Enable + pub const INTE = @intToPtr(*volatile Mmio(32, packed struct { + RTC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x24); + + /// address: 0x4005c028 + /// Interrupt Force + pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { + RTC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x28); + + /// address: 0x4005c02c + /// Interrupt status after masking & forcing + pub const INTS = @intToPtr(*volatile Mmio(32, packed struct { + RTC: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + padding30: u1 = 0, + }), base_address + 0x2c); + }; + pub const ROSC = struct { + pub const base_address = 0x40060000; + pub const version = "1"; + + /// address: 0x40060000 + /// Ring Oscillator control + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Controls the number of delay stages in the ROSC ring\n + /// LOW uses stages 0 to 7\n + /// MEDIUM uses stages 0 to 5\n + /// HIGH uses stages 0 to 3\n + /// TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds + /// design specifications\n + /// The clock output will not glitch when changing the range up one step at a time\n + /// The clock output will glitch when changing the range down\n + /// Note: the values here are gray coded which is why HIGH comes before TOOHIGH + FREQ_RANGE: u12, + /// On power-up this field is initialised to ENABLE\n + /// The system clock must be switched to another source before setting this field to + /// DISABLE otherwise the chip will lock up\n + /// The 12-bit code is intended to give some protection against accidental writes. + /// An invalid setting will enable the oscillator. + ENABLE: u12, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40060004 + /// The FREQA & FREQB registers control the frequency by controlling the drive + /// strength of each stage\n + /// The drive strength has 4 levels determined by the number of bits set\n + /// Increasing the number of bits set increases the drive strength and increases the + /// oscillation frequency\n + /// 0 bits set is the default drive strength\n + /// 1 bit set doubles the drive strength\n + /// 2 bits set triples drive strength\n + /// 3 bits set quadruples drive strength + pub const FREQA = @intToPtr(*volatile Mmio(32, packed struct { + /// Stage 0 drive strength + DS0: u3, + reserved0: u1 = 0, + /// Stage 1 drive strength + DS1: u3, + reserved1: u1 = 0, + /// Stage 2 drive strength + DS2: u3, + reserved2: u1 = 0, + /// Stage 3 drive strength + DS3: u3, + reserved3: u1 = 0, + /// Set to 0x9696 to apply the settings\n + /// Any other value in this field will set all drive strengths to 0 + PASSWD: u16, + }), base_address + 0x4); + + /// address: 0x40060008 + /// For a detailed description see freqa register + pub const FREQB = @intToPtr(*volatile Mmio(32, packed struct { + /// Stage 4 drive strength + DS4: u3, + reserved0: u1 = 0, + /// Stage 5 drive strength + DS5: u3, + reserved1: u1 = 0, + /// Stage 6 drive strength + DS6: u3, + reserved2: u1 = 0, + /// Stage 7 drive strength + DS7: u3, + reserved3: u1 = 0, + /// Set to 0x9696 to apply the settings\n + /// Any other value in this field will set all drive strengths to 0 + PASSWD: u16, + }), base_address + 0x8); + + /// address: 0x4006000c + /// Ring Oscillator pause control\n + /// This is used to save power by pausing the ROSC\n + /// On power-up this field is initialised to WAKE\n + /// An invalid write will also select WAKE\n + /// Warning: setup the irq before selecting dormant mode + pub const DORMANT = @intToPtr(*volatile u32, base_address + 0xc); + + /// address: 0x40060010 + /// Controls the output divider + pub const DIV = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x10); + + /// address: 0x40060014 + /// Controls the phase shifted output + pub const PHASE = @intToPtr(*volatile Mmio(32, packed struct { + /// phase shift the phase-shifted output by SHIFT input clocks\n + /// this can be changed on-the-fly\n + /// must be set to 0 before setting div=1 + SHIFT: u2, + /// invert the phase-shifted output\n + /// this is ignored when div=1 + FLIP: u1, + /// enable the phase-shifted output\n + /// this can be changed on-the-fly + ENABLE: u1, + /// set to 0xaa\n + /// any other value enables the output with shift=0 + PASSWD: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x14); + + /// address: 0x40060018 + /// Ring Oscillator Status + pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// Oscillator is enabled but not necessarily running and stable\n + /// this resets to 0 but transitions to 1 during chip startup + ENABLED: u1, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + /// post-divider is running\n + /// this resets to 0 but transitions to 1 during chip startup + DIV_RUNNING: u1, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + /// An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or + /// FREQB or DIV or PHASE or DORMANT + BADWRITE: u1, + reserved22: u1 = 0, + reserved23: u1 = 0, + reserved24: u1 = 0, + reserved25: u1 = 0, + reserved26: u1 = 0, + reserved27: u1 = 0, + /// Oscillator is running and stable + STABLE: u1, + }), base_address + 0x18); + + /// address: 0x4006001c + /// This just reads the state of the oscillator output so randomness is compromised + /// if the ring oscillator is stopped or run at a harmonic of the bus frequency + pub const RANDOMBIT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x1c); + + /// address: 0x40060020 + /// A down counter running at the ROSC frequency which counts to zero and stops.\n + /// To start the counter write a non-zero value.\n + /// Can be used for short software pauses when setting up time sensitive hardware. + pub const COUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x20); + }; + + /// control and status for on-chip voltage regulator and chip level reset subsystem + pub const VREG_AND_CHIP_RESET = struct { + pub const base_address = 0x40064000; + pub const version = "1"; + + /// address: 0x40064000 + /// Voltage regulator control and status + pub const VREG = @intToPtr(*volatile Mmio(32, packed struct { + /// enable\n + /// 0=not enabled, 1=enabled + EN: u1, + /// high impedance mode select\n + /// 0=not in high impedance mode, 1=in high impedance mode + HIZ: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// output voltage select\n + /// 0000 to 0101 - 0.80V\n + /// 0110 - 0.85V\n + /// 0111 - 0.90V\n + /// 1000 - 0.95V\n + /// 1001 - 1.00V\n + /// 1010 - 1.05V\n + /// 1011 - 1.10V (default)\n + /// 1100 - 1.15V\n + /// 1101 - 1.20V\n + /// 1110 - 1.25V\n + /// 1111 - 1.30V + VSEL: u4, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// regulation status\n + /// 0=not in regulation, 1=in regulation + ROK: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + }), base_address + 0x0); + + /// address: 0x40064004 + /// brown-out detection control + pub const BOD = @intToPtr(*volatile Mmio(32, packed struct { + /// enable\n + /// 0=not enabled, 1=enabled + EN: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// threshold select\n + /// 0000 - 0.473V\n + /// 0001 - 0.516V\n + /// 0010 - 0.559V\n + /// 0011 - 0.602V\n + /// 0100 - 0.645V\n + /// 0101 - 0.688V\n + /// 0110 - 0.731V\n + /// 0111 - 0.774V\n + /// 1000 - 0.817V\n + /// 1001 - 0.860V (default)\n + /// 1010 - 0.903V\n + /// 1011 - 0.946V\n + /// 1100 - 0.989V\n + /// 1101 - 1.032V\n + /// 1110 - 1.075V\n + /// 1111 - 1.118V + VSEL: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + }), base_address + 0x4); + + /// address: 0x40064008 + /// Chip reset control and status + pub const CHIP_RESET = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Last reset was from the power-on reset or brown-out detection blocks + HAD_POR: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + /// Last reset was from the RUN pin + HAD_RUN: u1, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// Last reset was from the debug port + HAD_PSM_RESTART: u1, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + /// This is set by psm_restart from the debugger.\n + /// Its purpose is to branch bootcode to a safe mode when the debugger has issued a + /// psm_restart in order to recover from a boot lock-up.\n + /// In the safe mode the debugger can repair the boot code, clear this flag then + /// reboot the processor. + PSM_RESTART_FLAG: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + }), base_address + 0x8); + }; + + /// Testbench manager. Allows the programmer to know what platform their software is + /// running on. + pub const TBMAN = struct { + pub const base_address = 0x4006c000; + pub const version = "1"; + + /// address: 0x4006c000 + /// Indicates the type of platform in use + pub const PLATFORM = @intToPtr(*volatile Mmio(32, packed struct { + /// Indicates the platform is an ASIC + ASIC: u1, + /// Indicates the platform is an FPGA + FPGA: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x0); + }; + + /// DMA with separate read and write masters + pub const DMA = struct { + pub const base_address = 0x50000000; + pub const version = "1"; + + /// address: 0x50000000 + /// DMA Channel 0 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH0_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0x50000004 + /// DMA Channel 0 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH0_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x4); + + /// address: 0x50000008 + /// DMA Channel 0 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH0_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x8); + + /// address: 0x5000000c + /// DMA Channel 0 Control and Status + pub const CH0_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (0). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0xc); + + /// address: 0x50000010 + /// Alias for channel 0 CTRL register + pub const CH0_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x50000014 + /// Alias for channel 0 READ_ADDR register + pub const CH0_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x50000018 + /// Alias for channel 0 WRITE_ADDR register + pub const CH0_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x5000001c + /// Alias for channel 0 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH0_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x50000020 + /// Alias for channel 0 CTRL register + pub const CH0_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x50000024 + /// Alias for channel 0 TRANS_COUNT register + pub const CH0_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x50000028 + /// Alias for channel 0 READ_ADDR register + pub const CH0_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x5000002c + /// Alias for channel 0 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH0_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x2c); + + /// address: 0x50000030 + /// Alias for channel 0 CTRL register + pub const CH0_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x30); + + /// address: 0x50000034 + /// Alias for channel 0 WRITE_ADDR register + pub const CH0_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x34); + + /// address: 0x50000038 + /// Alias for channel 0 TRANS_COUNT register + pub const CH0_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x38); + + /// address: 0x5000003c + /// Alias for channel 0 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH0_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x3c); + + /// address: 0x50000040 + /// DMA Channel 1 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x40); + + /// address: 0x50000044 + /// DMA Channel 1 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x44); + + /// address: 0x50000048 + /// DMA Channel 1 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH1_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x48); + + /// address: 0x5000004c + /// DMA Channel 1 Control and Status + pub const CH1_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (1). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0x4c); + + /// address: 0x50000050 + /// Alias for channel 1 CTRL register + pub const CH1_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x50); + + /// address: 0x50000054 + /// Alias for channel 1 READ_ADDR register + pub const CH1_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x54); + + /// address: 0x50000058 + /// Alias for channel 1 WRITE_ADDR register + pub const CH1_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x58); + + /// address: 0x5000005c + /// Alias for channel 1 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH1_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x5c); + + /// address: 0x50000060 + /// Alias for channel 1 CTRL register + pub const CH1_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x60); + + /// address: 0x50000064 + /// Alias for channel 1 TRANS_COUNT register + pub const CH1_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x64); + + /// address: 0x50000068 + /// Alias for channel 1 READ_ADDR register + pub const CH1_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x68); + + /// address: 0x5000006c + /// Alias for channel 1 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH1_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x6c); + + /// address: 0x50000070 + /// Alias for channel 1 CTRL register + pub const CH1_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x70); + + /// address: 0x50000074 + /// Alias for channel 1 WRITE_ADDR register + pub const CH1_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x74); + + /// address: 0x50000078 + /// Alias for channel 1 TRANS_COUNT register + pub const CH1_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x78); + + /// address: 0x5000007c + /// Alias for channel 1 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH1_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x7c); + + /// address: 0x50000080 + /// DMA Channel 2 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x80); + + /// address: 0x50000084 + /// DMA Channel 2 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH2_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x84); + + /// address: 0x50000088 + /// DMA Channel 2 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x88); + + /// address: 0x5000008c + /// DMA Channel 2 Control and Status + pub const CH2_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (2). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0x8c); + + /// address: 0x50000090 + /// Alias for channel 2 CTRL register + pub const CH2_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x90); + + /// address: 0x50000094 + /// Alias for channel 2 READ_ADDR register + pub const CH2_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x94); + + /// address: 0x50000098 + /// Alias for channel 2 WRITE_ADDR register + pub const CH2_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x98); + + /// address: 0x5000009c + /// Alias for channel 2 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH2_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x9c); + + /// address: 0x500000a0 + /// Alias for channel 2 CTRL register + pub const CH2_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0xa0); + + /// address: 0x500000a4 + /// Alias for channel 2 TRANS_COUNT register + pub const CH2_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0xa4); + + /// address: 0x500000a8 + /// Alias for channel 2 READ_ADDR register + pub const CH2_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0xa8); + + /// address: 0x500000ac + /// Alias for channel 2 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH2_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0xac); + + /// address: 0x500000b0 + /// Alias for channel 2 CTRL register + pub const CH2_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0xb0); + + /// address: 0x500000b4 + /// Alias for channel 2 WRITE_ADDR register + pub const CH2_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0xb4); + + /// address: 0x500000b8 + /// Alias for channel 2 TRANS_COUNT register + pub const CH2_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0xb8); + + /// address: 0x500000bc + /// Alias for channel 2 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH2_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0xbc); + + /// address: 0x500000c0 + /// DMA Channel 3 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH3_READ_ADDR = @intToPtr(*volatile u32, base_address + 0xc0); + + /// address: 0x500000c4 + /// DMA Channel 3 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0xc4); + + /// address: 0x500000c8 + /// DMA Channel 3 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0xc8); + + /// address: 0x500000cc + /// DMA Channel 3 Control and Status + pub const CH3_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (3). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0xcc); + + /// address: 0x500000d0 + /// Alias for channel 3 CTRL register + pub const CH3_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0xd0); + + /// address: 0x500000d4 + /// Alias for channel 3 READ_ADDR register + pub const CH3_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0xd4); + + /// address: 0x500000d8 + /// Alias for channel 3 WRITE_ADDR register + pub const CH3_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0xd8); + + /// address: 0x500000dc + /// Alias for channel 3 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH3_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0xdc); + + /// address: 0x500000e0 + /// Alias for channel 3 CTRL register + pub const CH3_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0xe0); + + /// address: 0x500000e4 + /// Alias for channel 3 TRANS_COUNT register + pub const CH3_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0xe4); + + /// address: 0x500000e8 + /// Alias for channel 3 READ_ADDR register + pub const CH3_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0xe8); + + /// address: 0x500000ec + /// Alias for channel 3 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH3_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0xec); + + /// address: 0x500000f0 + /// Alias for channel 3 CTRL register + pub const CH3_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0xf0); + + /// address: 0x500000f4 + /// Alias for channel 3 WRITE_ADDR register + pub const CH3_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0xf4); + + /// address: 0x500000f8 + /// Alias for channel 3 TRANS_COUNT register + pub const CH3_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0xf8); + + /// address: 0x500000fc + /// Alias for channel 3 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH3_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0xfc); + + /// address: 0x50000100 + /// DMA Channel 4 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH4_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0x50000104 + /// DMA Channel 4 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH4_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0x50000108 + /// DMA Channel 4 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH4_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0x5000010c + /// DMA Channel 4 Control and Status + pub const CH4_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (4). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0x10c); + + /// address: 0x50000110 + /// Alias for channel 4 CTRL register + pub const CH4_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0x50000114 + /// Alias for channel 4 READ_ADDR register + pub const CH4_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0x50000118 + /// Alias for channel 4 WRITE_ADDR register + pub const CH4_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0x5000011c + /// Alias for channel 4 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH4_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0x50000120 + /// Alias for channel 4 CTRL register + pub const CH4_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0x50000124 + /// Alias for channel 4 TRANS_COUNT register + pub const CH4_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0x50000128 + /// Alias for channel 4 READ_ADDR register + pub const CH4_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0x5000012c + /// Alias for channel 4 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH4_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x12c); + + /// address: 0x50000130 + /// Alias for channel 4 CTRL register + pub const CH4_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x130); + + /// address: 0x50000134 + /// Alias for channel 4 WRITE_ADDR register + pub const CH4_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x134); + + /// address: 0x50000138 + /// Alias for channel 4 TRANS_COUNT register + pub const CH4_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x138); + + /// address: 0x5000013c + /// Alias for channel 4 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH4_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x13c); + + /// address: 0x50000140 + /// DMA Channel 5 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH5_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x140); + + /// address: 0x50000144 + /// DMA Channel 5 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH5_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x144); + + /// address: 0x50000148 + /// DMA Channel 5 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH5_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0x5000014c + /// DMA Channel 5 Control and Status + pub const CH5_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (5). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0x14c); + + /// address: 0x50000150 + /// Alias for channel 5 CTRL register + pub const CH5_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0x50000154 + /// Alias for channel 5 READ_ADDR register + pub const CH5_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x154); + + /// address: 0x50000158 + /// Alias for channel 5 WRITE_ADDR register + pub const CH5_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x158); + + /// address: 0x5000015c + /// Alias for channel 5 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH5_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x15c); + + /// address: 0x50000160 + /// Alias for channel 5 CTRL register + pub const CH5_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x160); + + /// address: 0x50000164 + /// Alias for channel 5 TRANS_COUNT register + pub const CH5_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x164); + + /// address: 0x50000168 + /// Alias for channel 5 READ_ADDR register + pub const CH5_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x168); + + /// address: 0x5000016c + /// Alias for channel 5 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH5_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x16c); + + /// address: 0x50000170 + /// Alias for channel 5 CTRL register + pub const CH5_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x170); + + /// address: 0x50000174 + /// Alias for channel 5 WRITE_ADDR register + pub const CH5_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x174); + + /// address: 0x50000178 + /// Alias for channel 5 TRANS_COUNT register + pub const CH5_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x178); + + /// address: 0x5000017c + /// Alias for channel 5 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH5_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x17c); + + /// address: 0x50000180 + /// DMA Channel 6 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH6_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x180); + + /// address: 0x50000184 + /// DMA Channel 6 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH6_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x184); + + /// address: 0x50000188 + /// DMA Channel 6 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH6_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x188); + + /// address: 0x5000018c + /// DMA Channel 6 Control and Status + pub const CH6_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (6). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0x18c); + + /// address: 0x50000190 + /// Alias for channel 6 CTRL register + pub const CH6_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x190); + + /// address: 0x50000194 + /// Alias for channel 6 READ_ADDR register + pub const CH6_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x194); + + /// address: 0x50000198 + /// Alias for channel 6 WRITE_ADDR register + pub const CH6_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x198); + + /// address: 0x5000019c + /// Alias for channel 6 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH6_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x19c); + + /// address: 0x500001a0 + /// Alias for channel 6 CTRL register + pub const CH6_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x1a0); + + /// address: 0x500001a4 + /// Alias for channel 6 TRANS_COUNT register + pub const CH6_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x1a4); + + /// address: 0x500001a8 + /// Alias for channel 6 READ_ADDR register + pub const CH6_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x1a8); + + /// address: 0x500001ac + /// Alias for channel 6 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH6_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x1ac); + + /// address: 0x500001b0 + /// Alias for channel 6 CTRL register + pub const CH6_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x1b0); + + /// address: 0x500001b4 + /// Alias for channel 6 WRITE_ADDR register + pub const CH6_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x1b4); + + /// address: 0x500001b8 + /// Alias for channel 6 TRANS_COUNT register + pub const CH6_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x1b8); + + /// address: 0x500001bc + /// Alias for channel 6 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH6_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x1bc); + + /// address: 0x500001c0 + /// DMA Channel 7 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH7_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x1c0); + + /// address: 0x500001c4 + /// DMA Channel 7 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH7_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x1c4); + + /// address: 0x500001c8 + /// DMA Channel 7 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH7_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x1c8); + + /// address: 0x500001cc + /// DMA Channel 7 Control and Status + pub const CH7_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (7). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0x1cc); + + /// address: 0x500001d0 + /// Alias for channel 7 CTRL register + pub const CH7_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x1d0); + + /// address: 0x500001d4 + /// Alias for channel 7 READ_ADDR register + pub const CH7_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x1d4); + + /// address: 0x500001d8 + /// Alias for channel 7 WRITE_ADDR register + pub const CH7_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x1d8); + + /// address: 0x500001dc + /// Alias for channel 7 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH7_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x1dc); + + /// address: 0x500001e0 + /// Alias for channel 7 CTRL register + pub const CH7_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x1e0); + + /// address: 0x500001e4 + /// Alias for channel 7 TRANS_COUNT register + pub const CH7_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x1e4); + + /// address: 0x500001e8 + /// Alias for channel 7 READ_ADDR register + pub const CH7_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x1e8); + + /// address: 0x500001ec + /// Alias for channel 7 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH7_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x1ec); + + /// address: 0x500001f0 + /// Alias for channel 7 CTRL register + pub const CH7_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x1f0); + + /// address: 0x500001f4 + /// Alias for channel 7 WRITE_ADDR register + pub const CH7_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x1f4); + + /// address: 0x500001f8 + /// Alias for channel 7 TRANS_COUNT register + pub const CH7_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x1f8); + + /// address: 0x500001fc + /// Alias for channel 7 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH7_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x1fc); + + /// address: 0x50000200 + /// DMA Channel 8 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH8_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x200); + + /// address: 0x50000204 + /// DMA Channel 8 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH8_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x204); + + /// address: 0x50000208 + /// DMA Channel 8 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH8_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x208); + + /// address: 0x5000020c + /// DMA Channel 8 Control and Status + pub const CH8_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (8). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0x20c); + + /// address: 0x50000210 + /// Alias for channel 8 CTRL register + pub const CH8_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x210); + + /// address: 0x50000214 + /// Alias for channel 8 READ_ADDR register + pub const CH8_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x214); + + /// address: 0x50000218 + /// Alias for channel 8 WRITE_ADDR register + pub const CH8_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x218); + + /// address: 0x5000021c + /// Alias for channel 8 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH8_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x21c); + + /// address: 0x50000220 + /// Alias for channel 8 CTRL register + pub const CH8_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x220); + + /// address: 0x50000224 + /// Alias for channel 8 TRANS_COUNT register + pub const CH8_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x224); + + /// address: 0x50000228 + /// Alias for channel 8 READ_ADDR register + pub const CH8_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x228); + + /// address: 0x5000022c + /// Alias for channel 8 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH8_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x22c); + + /// address: 0x50000230 + /// Alias for channel 8 CTRL register + pub const CH8_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x230); + + /// address: 0x50000234 + /// Alias for channel 8 WRITE_ADDR register + pub const CH8_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x234); + + /// address: 0x50000238 + /// Alias for channel 8 TRANS_COUNT register + pub const CH8_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x238); + + /// address: 0x5000023c + /// Alias for channel 8 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH8_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x23c); + + /// address: 0x50000240 + /// DMA Channel 9 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH9_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x240); + + /// address: 0x50000244 + /// DMA Channel 9 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH9_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x244); + + /// address: 0x50000248 + /// DMA Channel 9 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH9_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x248); + + /// address: 0x5000024c + /// DMA Channel 9 Control and Status + pub const CH9_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (9). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0x24c); + + /// address: 0x50000250 + /// Alias for channel 9 CTRL register + pub const CH9_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x250); + + /// address: 0x50000254 + /// Alias for channel 9 READ_ADDR register + pub const CH9_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x254); + + /// address: 0x50000258 + /// Alias for channel 9 WRITE_ADDR register + pub const CH9_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x258); + + /// address: 0x5000025c + /// Alias for channel 9 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH9_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x25c); + + /// address: 0x50000260 + /// Alias for channel 9 CTRL register + pub const CH9_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x260); + + /// address: 0x50000264 + /// Alias for channel 9 TRANS_COUNT register + pub const CH9_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x264); + + /// address: 0x50000268 + /// Alias for channel 9 READ_ADDR register + pub const CH9_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x268); + + /// address: 0x5000026c + /// Alias for channel 9 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH9_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x26c); + + /// address: 0x50000270 + /// Alias for channel 9 CTRL register + pub const CH9_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x270); + + /// address: 0x50000274 + /// Alias for channel 9 WRITE_ADDR register + pub const CH9_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x274); + + /// address: 0x50000278 + /// Alias for channel 9 TRANS_COUNT register + pub const CH9_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x278); + + /// address: 0x5000027c + /// Alias for channel 9 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH9_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x27c); + + /// address: 0x50000280 + /// DMA Channel 10 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH10_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x280); + + /// address: 0x50000284 + /// DMA Channel 10 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH10_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x284); + + /// address: 0x50000288 + /// DMA Channel 10 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH10_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x288); + + /// address: 0x5000028c + /// DMA Channel 10 Control and Status + pub const CH10_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (10). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0x28c); + + /// address: 0x50000290 + /// Alias for channel 10 CTRL register + pub const CH10_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x290); + + /// address: 0x50000294 + /// Alias for channel 10 READ_ADDR register + pub const CH10_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x294); + + /// address: 0x50000298 + /// Alias for channel 10 WRITE_ADDR register + pub const CH10_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x298); + + /// address: 0x5000029c + /// Alias for channel 10 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH10_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x29c); + + /// address: 0x500002a0 + /// Alias for channel 10 CTRL register + pub const CH10_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x2a0); + + /// address: 0x500002a4 + /// Alias for channel 10 TRANS_COUNT register + pub const CH10_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x2a4); + + /// address: 0x500002a8 + /// Alias for channel 10 READ_ADDR register + pub const CH10_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x2a8); + + /// address: 0x500002ac + /// Alias for channel 10 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH10_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x2ac); + + /// address: 0x500002b0 + /// Alias for channel 10 CTRL register + pub const CH10_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x2b0); + + /// address: 0x500002b4 + /// Alias for channel 10 WRITE_ADDR register + pub const CH10_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x2b4); + + /// address: 0x500002b8 + /// Alias for channel 10 TRANS_COUNT register + pub const CH10_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x2b8); + + /// address: 0x500002bc + /// Alias for channel 10 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH10_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x2bc); + + /// address: 0x500002c0 + /// DMA Channel 11 Read Address pointer\n + /// This register updates automatically each time a read completes. The current + /// value is the next address to be read by this channel. + pub const CH11_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x2c0); + + /// address: 0x500002c4 + /// DMA Channel 11 Write Address pointer\n + /// This register updates automatically each time a write completes. The current + /// value is the next address to be written by this channel. + pub const CH11_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x2c4); + + /// address: 0x500002c8 + /// DMA Channel 11 Transfer Count\n + /// Program the number of bus transfers a channel will perform before halting. Note + /// that, if transfers are larger than one byte in size, this is not equal to the + /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n + /// When the channel is active, reading this register shows the number of transfers + /// remaining, updating automatically each time a write transfer completes.\n\n + /// Writing this register sets the RELOAD value for the transfer counter. Each time + /// this channel is triggered, the RELOAD value is copied into the live transfer + /// counter. The channel can be started multiple times, and will perform the same + /// number of transfers each time, as programmed by most recent write.\n\n + /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a + /// trigger, the written value is used immediately as the length of the new transfer + /// sequence, as well as being written to RELOAD. + pub const CH11_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x2c8); + + /// address: 0x500002cc + /// DMA Channel 11 Control and Status + pub const CH11_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct { + /// DMA Channel Enable.\n + /// When 1, the channel will respond to triggering events, which will cause it to + /// become BUSY and start transferring data. When 0, the channel will ignore + /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e. + /// BUSY will remain high if already high) + EN: u1, + /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in + /// each scheduling round, all high priority channels are considered first, and then + /// only a single low priority channel, before returning to the high priority + /// channels.\n\n + /// This only affects the order in which the DMA schedules channels. The DMA's bus + /// priority is not changed. If the DMA is not saturated then a low priority channel + /// will see no loss of throughput. + HIGH_PRIORITY: u1, + /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR + /// advance by this amount (1/2/4 bytes) with each transfer. + DATA_SIZE: u2, + /// If 1, the read address increments with each transfer. If 0, each read is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for peripheral-to-memory transfers. + INCR_READ: u1, + /// If 1, the write address increments with each transfer. If 0, each write is + /// directed to the same, initial address.\n\n + /// Generally this should be disabled for memory-to-peripheral transfers. + INCR_WRITE: u1, + /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower + /// n bits of the address will change. This wraps the address on a (1 << n) byte + /// boundary, facilitating access to naturally-aligned ring buffers.\n\n + /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read + /// or write addresses, based on value of RING_SEL. + RING_SIZE: u4, + /// Select whether RING_SIZE applies to read or write addresses.\n + /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write + /// addresses are wrapped. + RING_SEL: u1, + /// When this channel completes, it will trigger the channel indicated by CHAIN_TO. + /// Disable by setting CHAIN_TO = _(this channel)_.\n + /// Reset value is equal to channel number (11). + CHAIN_TO: u4, + /// Select a Transfer Request signal.\n + /// The channel uses the transfer request signal to pace its data transfer rate. + /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request + /// from the system).\n + /// 0x0 to 0x3a -> select DREQ n as TREQ + TREQ_SEL: u6, + /// In QUIET mode, the channel does not generate IRQs at the end of every transfer + /// block. Instead, an IRQ is raised when NULL is written to a trigger register, + /// indicating the end of a control block chain.\n\n + /// This reduces the number of interrupts to be serviced by the CPU when + /// transferring a DMA chain of many small control blocks. + IRQ_QUIET: u1, + /// Apply byte-swap transformation to DMA data.\n + /// For byte data, this has no effect. For halfword data, the two bytes of each + /// halfword are swapped. For word data, the four bytes of each word are swapped to + /// reverse order. + BSWAP: u1, + /// If 1, this channel's data transfers are visible to the sniff hardware, and each + /// transfer will advance the state of the checksum. This only applies if the sniff + /// hardware is enabled, and has this channel selected.\n\n + /// This allows checksum to be enabled or disabled on a per-control- block basis. + SNIFF_EN: u1, + /// This flag goes high when the channel starts a new transfer sequence, and low + /// when the last transfer of that sequence completes. Clearing EN while BUSY is + /// high pauses the channel, and BUSY will stay high while paused.\n\n + /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT. + BUSY: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// If 1, the channel received a write bus error. Write one to clear.\n + /// WRITE_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 5 transfers later) + WRITE_ERROR: u1, + /// If 1, the channel received a read bus error. Write one to clear.\n + /// READ_ADDR shows the approximate address where the bus error was encountered + /// (will not to be earlier, or more than 3 transfers later) + READ_ERROR: u1, + /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it + /// encounters any bus error, and always raises its channel IRQ flag. + AHB_ERROR: u1, + }), base_address + 0x2cc); + + /// address: 0x500002d0 + /// Alias for channel 11 CTRL register + pub const CH11_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x2d0); + + /// address: 0x500002d4 + /// Alias for channel 11 READ_ADDR register + pub const CH11_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x2d4); + + /// address: 0x500002d8 + /// Alias for channel 11 WRITE_ADDR register + pub const CH11_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x2d8); + + /// address: 0x500002dc + /// Alias for channel 11 TRANS_COUNT register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH11_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x2dc); + + /// address: 0x500002e0 + /// Alias for channel 11 CTRL register + pub const CH11_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x2e0); + + /// address: 0x500002e4 + /// Alias for channel 11 TRANS_COUNT register + pub const CH11_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x2e4); + + /// address: 0x500002e8 + /// Alias for channel 11 READ_ADDR register + pub const CH11_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x2e8); + + /// address: 0x500002ec + /// Alias for channel 11 WRITE_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH11_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x2ec); + + /// address: 0x500002f0 + /// Alias for channel 11 CTRL register + pub const CH11_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x2f0); + + /// address: 0x500002f4 + /// Alias for channel 11 WRITE_ADDR register + pub const CH11_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x2f4); + + /// address: 0x500002f8 + /// Alias for channel 11 TRANS_COUNT register + pub const CH11_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x2f8); + + /// address: 0x500002fc + /// Alias for channel 11 READ_ADDR register\n + /// This is a trigger register (0xc). Writing a nonzero value will\n + /// reload the channel counter and start the channel. + pub const CH11_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x2fc); + + /// address: 0x50000400 + /// Interrupt Status (raw) + pub const INTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x400); + + /// address: 0x50000404 + /// Interrupt Enables for IRQ 0 + pub const INTE0 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x404); + + /// address: 0x50000408 + /// Force Interrupts + pub const INTF0 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x408); + + /// address: 0x5000040c + /// Interrupt Status for IRQ 0 + pub const INTS0 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40c); + + /// address: 0x50000414 + /// Interrupt Enables for IRQ 1 + pub const INTE1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x414); + + /// address: 0x50000418 + /// Force Interrupts for IRQ 1 + pub const INTF1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x418); + + /// address: 0x5000041c + /// Interrupt Status (masked) for IRQ 1 + pub const INTS1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x41c); + + /// address: 0x50000420 + /// Pacing (X/Y) Fractional Timer\n + /// The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). + /// This equation is evaluated every sys_clk cycles and therefore can only generate + /// TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + pub const TIMER0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + Y: u16, + /// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + X: u16, + }), base_address + 0x420); + + /// address: 0x50000424 + /// Pacing (X/Y) Fractional Timer\n + /// The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). + /// This equation is evaluated every sys_clk cycles and therefore can only generate + /// TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + pub const TIMER1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + Y: u16, + /// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + X: u16, + }), base_address + 0x424); + + /// address: 0x50000428 + /// Pacing (X/Y) Fractional Timer\n + /// The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). + /// This equation is evaluated every sys_clk cycles and therefore can only generate + /// TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + pub const TIMER2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + Y: u16, + /// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + X: u16, + }), base_address + 0x428); + + /// address: 0x5000042c + /// Pacing (X/Y) Fractional Timer\n + /// The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). + /// This equation is evaluated every sys_clk cycles and therefore can only generate + /// TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less. + pub const TIMER3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer. + Y: u16, + /// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer. + X: u16, + }), base_address + 0x42c); + + /// address: 0x50000430 + /// Trigger one or more channels simultaneously + pub const MULTI_CHAN_TRIGGER = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x430); + + /// address: 0x50000434 + /// Sniffer Control + pub const SNIFF_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable sniffer + EN: u1, + /// DMA channel for Sniffer to observe + DMACH: u4, + CALC: u4, + /// Locally perform a byte reverse on the sniffed data, before feeding into + /// checksum.\n\n + /// Note that the sniff hardware is downstream of the DMA channel byteswap performed + /// in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, + /// their effects cancel from the sniffer's point of view. + BSWAP: u1, + /// If set, the result appears bit-reversed when read. This does not affect the way + /// the checksum is calculated; the result is transformed on-the-fly between the + /// result register and the bus. + OUT_REV: u1, + /// If set, the result appears inverted (bitwise complement) when read. This does + /// not affect the way the checksum is calculated; the result is transformed + /// on-the-fly between the result register and the bus. + OUT_INV: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x434); + + /// address: 0x50000438 + /// Data accumulator for sniff hardware\n + /// Write an initial seed value here before starting a DMA transfer on the channel + /// indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time + /// it observes a read from the indicated channel. Once the channel completes, the + /// final result can be read from this register. + pub const SNIFF_DATA = @intToPtr(*volatile u32, base_address + 0x438); + + /// address: 0x50000440 + /// Debug RAF, WAF, TDF levels + pub const FIFO_LEVELS = @intToPtr(*volatile Mmio(32, packed struct { + /// Current Transfer-Data-FIFO fill level + TDF_LVL: u8, + /// Current Write-Address-FIFO fill level + WAF_LVL: u8, + /// Current Read-Address-FIFO fill level + RAF_LVL: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0x440); + + /// address: 0x50000444 + /// Abort an in-progress transfer sequence on one or more channels + pub const CHAN_ABORT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x444); + + /// address: 0x50000448 + /// The number of channels this DMA instance is equipped with. This DMA supports up + /// to 16 hardware channels, but can be configured with as few as one, to minimise + /// silicon area. + pub const N_CHANNELS = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x448); + + /// address: 0x50000800 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH0_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x800); + + /// address: 0x50000804 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH0_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x804); + + /// address: 0x50000840 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH1_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x840); + + /// address: 0x50000844 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH1_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x844); + + /// address: 0x50000880 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH2_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x880); + + /// address: 0x50000884 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH2_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x884); + + /// address: 0x500008c0 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH3_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x8c0); + + /// address: 0x500008c4 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH3_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x8c4); + + /// address: 0x50000900 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH4_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x900); + + /// address: 0x50000904 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH4_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x904); + + /// address: 0x50000940 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH5_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x940); + + /// address: 0x50000944 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH5_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x944); + + /// address: 0x50000980 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH6_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x980); + + /// address: 0x50000984 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH6_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x984); + + /// address: 0x500009c0 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH7_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x9c0); + + /// address: 0x500009c4 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH7_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x9c4); + + /// address: 0x50000a00 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH8_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xa00); + + /// address: 0x50000a04 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH8_DBG_TCR = @intToPtr(*volatile u32, base_address + 0xa04); + + /// address: 0x50000a40 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH9_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xa40); + + /// address: 0x50000a44 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH9_DBG_TCR = @intToPtr(*volatile u32, base_address + 0xa44); + + /// address: 0x50000a80 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH10_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xa80); + + /// address: 0x50000a84 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH10_DBG_TCR = @intToPtr(*volatile u32, base_address + 0xa84); + + /// address: 0x50000ac0 + /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can + /// perform on the peripheral without overflow/underflow. Write any value: clears + /// the counter, and cause channel to re-initiate DREQ handshake. + pub const CH11_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xac0); + + /// address: 0x50000ac4 + /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next + /// transfer + pub const CH11_DBG_TCR = @intToPtr(*volatile u32, base_address + 0xac4); + }; + + /// DPRAM layout for USB device. + pub const USBCTRL_DPRAM = struct { + pub const base_address = 0x50100000; + pub const version = "1"; + + /// address: 0x50100000 + /// Bytes 0-3 of the SETUP packet from the host. + pub const SETUP_PACKET_LOW = @intToPtr(*volatile Mmio(32, packed struct { + BMREQUESTTYPE: u8, + BREQUEST: u8, + WVALUE: u16, + }), base_address + 0x0); + + /// address: 0x50100004 + /// Bytes 4-7 of the setup packet from the host. + pub const SETUP_PACKET_HIGH = @intToPtr(*volatile Mmio(32, packed struct { + WINDEX: u16, + WLENGTH: u16, + }), base_address + 0x4); + + /// address: 0x50100008 + pub const EP1_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x8); + + /// address: 0x5010000c + pub const EP1_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0xc); + + /// address: 0x50100010 + pub const EP2_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x10); + + /// address: 0x50100014 + pub const EP2_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x14); + + /// address: 0x50100018 + pub const EP3_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x18); + + /// address: 0x5010001c + pub const EP3_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x1c); + + /// address: 0x50100020 + pub const EP4_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x20); + + /// address: 0x50100024 + pub const EP4_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x24); + + /// address: 0x50100028 + pub const EP5_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x28); + + /// address: 0x5010002c + pub const EP5_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x2c); + + /// address: 0x50100030 + pub const EP6_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x30); + + /// address: 0x50100034 + pub const EP6_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x34); + + /// address: 0x50100038 + pub const EP7_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x38); + + /// address: 0x5010003c + pub const EP7_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x3c); + + /// address: 0x50100040 + pub const EP8_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x40); + + /// address: 0x50100044 + pub const EP8_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x44); + + /// address: 0x50100048 + pub const EP9_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x48); + + /// address: 0x5010004c + pub const EP9_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x4c); + + /// address: 0x50100050 + pub const EP10_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x50); + + /// address: 0x50100054 + pub const EP10_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x54); + + /// address: 0x50100058 + pub const EP11_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x58); + + /// address: 0x5010005c + pub const EP11_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x5c); + + /// address: 0x50100060 + pub const EP12_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x60); + + /// address: 0x50100064 + pub const EP12_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x64); + + /// address: 0x50100068 + pub const EP13_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x68); + + /// address: 0x5010006c + pub const EP13_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x6c); + + /// address: 0x50100070 + pub const EP14_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x70); + + /// address: 0x50100074 + pub const EP14_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x74); + + /// address: 0x50100078 + pub const EP15_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x78); + + /// address: 0x5010007c + pub const EP15_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to + /// the start of the DPRAM. + BUFFER_ADDRESS: u16, + /// Trigger an interrupt if a NAK is sent. Intended for debug only. + INTERRUPT_ON_NAK: u1, + /// Trigger an interrupt if a STALL is sent. Intended for debug only. + INTERRUPT_ON_STALL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + ENDPOINT_TYPE: u2, + /// Trigger an interrupt each time both buffers are done. Only valid in double + /// buffered mode. + INTERRUPT_PER_DOUBLE_BUFF: u1, + /// Trigger an interrupt each time a buffer is done. + INTERRUPT_PER_BUFF: u1, + /// This endpoint is double buffered. + DOUBLE_BUFFERED: u1, + /// Enable this endpoint. The device will not reply to any packets for this endpoint + /// if this bit is not set. + ENABLE: u1, + }), base_address + 0x7c); + + /// address: 0x50100080 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP0_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0x80); + + /// address: 0x50100084 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP0_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0x84); + + /// address: 0x50100088 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP1_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0x88); + + /// address: 0x5010008c + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP1_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0x8c); + + /// address: 0x50100090 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP2_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0x90); + + /// address: 0x50100094 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP2_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0x94); + + /// address: 0x50100098 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP3_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0x98); + + /// address: 0x5010009c + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP3_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0x9c); + + /// address: 0x501000a0 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP4_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xa0); + + /// address: 0x501000a4 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP4_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xa4); + + /// address: 0x501000a8 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP5_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xa8); + + /// address: 0x501000ac + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP5_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xac); + + /// address: 0x501000b0 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP6_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xb0); + + /// address: 0x501000b4 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP6_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xb4); + + /// address: 0x501000b8 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP7_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xb8); + + /// address: 0x501000bc + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP7_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xbc); + + /// address: 0x501000c0 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP8_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xc0); + + /// address: 0x501000c4 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP8_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xc4); + + /// address: 0x501000c8 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP9_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xc8); + + /// address: 0x501000cc + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP9_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xcc); + + /// address: 0x501000d0 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP10_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xd0); + + /// address: 0x501000d4 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP10_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xd4); + + /// address: 0x501000d8 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP11_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xd8); + + /// address: 0x501000dc + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP11_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xdc); + + /// address: 0x501000e0 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP12_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xe0); + + /// address: 0x501000e4 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP12_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xe4); + + /// address: 0x501000e8 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP13_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xe8); + + /// address: 0x501000ec + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP13_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xec); + + /// address: 0x501000f0 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP14_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xf0); + + /// address: 0x501000f4 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP14_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xf4); + + /// address: 0x501000f8 + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP15_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xf8); + + /// address: 0x501000fc + /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for + /// buffer 1.\n + /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the + /// endpoint is in double buffered mode. + pub const EP15_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct { + /// The length of the data in buffer 0. + LENGTH_0: u10, + /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_0: u1, + /// Reply with a stall (valid for both buffers). + STALL: u1, + /// Reset the buffer selector to buffer 0. + RESET: u1, + /// The data pid of buffer 0. + PID_0: u1, + /// Buffer 0 is the last buffer of the transfer. + LAST_0: u1, + /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_0: u1, + /// The length of the data in buffer 1. + LENGTH_1: u10, + /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the + /// controller. The controller clears the available bit when writing the status + /// back. + AVAILABLE_1: u1, + /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only + /// valid in double buffered mode for an Isochronous endpoint.\n + /// For a non Isochronous endpoint the offset is always 64 bytes. + DOUBLE_BUFFER_ISO_OFFSET: u2, + /// The data pid of buffer 1. + PID_1: u1, + /// Buffer 1 is the last buffer of the transfer. + LAST_1: u1, + /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate + /// the data is valid. For an OUT transfer (RX from the host) this bit should be + /// left as a 0. The host will set it when it has filled the buffer with data. + FULL_1: u1, + }), base_address + 0xfc); + }; + + /// USB FS/LS controller device registers + pub const USBCTRL_REGS = struct { + pub const base_address = 0x50110000; + pub const version = "1"; + + /// address: 0x50110000 + /// Device address and endpoint control + pub const ADDR_ENDP = @intToPtr(*volatile Mmio(32, packed struct { + /// In device mode, the address that the device should respond to. Set in response + /// to a SET_ADDR setup packet from the host. In host mode set to the address of the + /// device to communicate with. + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Device endpoint to send data to. Only valid for HOST mode. + ENDPOINT: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + }), base_address + 0x0); + + /// address: 0x50110004 + /// Interrupt endpoint 1. Only valid for HOST mode. + pub const ADDR_ENDP1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x4); + + /// address: 0x50110008 + /// Interrupt endpoint 2. Only valid for HOST mode. + pub const ADDR_ENDP2 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x8); + + /// address: 0x5011000c + /// Interrupt endpoint 3. Only valid for HOST mode. + pub const ADDR_ENDP3 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0xc); + + /// address: 0x50110010 + /// Interrupt endpoint 4. Only valid for HOST mode. + pub const ADDR_ENDP4 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x10); + + /// address: 0x50110014 + /// Interrupt endpoint 5. Only valid for HOST mode. + pub const ADDR_ENDP5 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x14); + + /// address: 0x50110018 + /// Interrupt endpoint 6. Only valid for HOST mode. + pub const ADDR_ENDP6 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x18); + + /// address: 0x5011001c + /// Interrupt endpoint 7. Only valid for HOST mode. + pub const ADDR_ENDP7 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x1c); + + /// address: 0x50110020 + /// Interrupt endpoint 8. Only valid for HOST mode. + pub const ADDR_ENDP8 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x20); + + /// address: 0x50110024 + /// Interrupt endpoint 9. Only valid for HOST mode. + pub const ADDR_ENDP9 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x24); + + /// address: 0x50110028 + /// Interrupt endpoint 10. Only valid for HOST mode. + pub const ADDR_ENDP10 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x28); + + /// address: 0x5011002c + /// Interrupt endpoint 11. Only valid for HOST mode. + pub const ADDR_ENDP11 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x2c); + + /// address: 0x50110030 + /// Interrupt endpoint 12. Only valid for HOST mode. + pub const ADDR_ENDP12 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x30); + + /// address: 0x50110034 + /// Interrupt endpoint 13. Only valid for HOST mode. + pub const ADDR_ENDP13 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x34); + + /// address: 0x50110038 + /// Interrupt endpoint 14. Only valid for HOST mode. + pub const ADDR_ENDP14 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x38); + + /// address: 0x5011003c + /// Interrupt endpoint 15. Only valid for HOST mode. + pub const ADDR_ENDP15 = @intToPtr(*volatile Mmio(32, packed struct { + /// Device address + ADDRESS: u7, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + /// Endpoint number of the interrupt endpoint + ENDPOINT: u4, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + /// Direction of the interrupt endpoint. In=0, Out=1 + INTEP_DIR: u1, + /// Interrupt EP requires preamble (is a low speed device on a full speed hub) + INTEP_PREAMBLE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + }), base_address + 0x3c); + + /// address: 0x50110040 + /// Main control register + pub const MAIN_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable controller + CONTROLLER_EN: u1, + /// Device mode = 0, Host mode = 1 + HOST_NDEVICE: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + reserved24: u1 = 0, + reserved25: u1 = 0, + reserved26: u1 = 0, + reserved27: u1 = 0, + reserved28: u1 = 0, + /// Reduced timings for simulation + SIM_TIMING: u1, + }), base_address + 0x40); + + /// address: 0x50110044 + /// Set the SOF (Start of Frame) frame number in the host controller. The SOF packet + /// is sent every 1ms and the host will increment the frame number by 1 each time. + pub const SOF_WR = @intToPtr(*volatile Mmio(32, packed struct { + COUNT: u11, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x44); + + /// address: 0x50110048 + /// Read the last SOF (Start of Frame) frame number seen. In device mode the last + /// SOF received from the host. In host mode the last SOF sent by the host. + pub const SOF_RD = @intToPtr(*volatile Mmio(32, packed struct { + COUNT: u11, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + }), base_address + 0x48); + + /// address: 0x5011004c + /// SIE control register + pub const SIE_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Host: Start transaction + START_TRANS: u1, + /// Host: Send Setup packet + SEND_SETUP: u1, + /// Host: Send transaction (OUT from host) + SEND_DATA: u1, + /// Host: Receive transaction (IN to host) + RECEIVE_DATA: u1, + /// Host: Stop transaction + STOP_TRANS: u1, + reserved0: u1 = 0, + /// Host: Preable enable for LS device on FS hub + PREAMBLE_EN: u1, + reserved1: u1 = 0, + /// Host: Delay packet(s) until after SOF + SOF_SYNC: u1, + /// Host: Enable SOF generation (for full speed bus) + SOF_EN: u1, + /// Host: Enable keep alive packet (for low speed bus) + KEEP_ALIVE_EN: u1, + /// Host: Enable VBUS + VBUS_EN: u1, + /// Device: Remote wakeup. Device can initiate its own resume after suspend. + RESUME: u1, + /// Host: Reset bus + RESET_BUS: u1, + reserved2: u1 = 0, + /// Host: Enable pull down resistors + PULLDOWN_EN: u1, + /// Device: Enable pull up resistor + PULLUP_EN: u1, + /// Device: Pull-up strength (0=1K2, 1=2k3) + RPU_OPT: u1, + /// Power down bus transceiver + TRANSCEIVER_PD: u1, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Direct control of DM + DIRECT_DM: u1, + /// Direct control of DP + DIRECT_DP: u1, + /// Direct bus drive enable + DIRECT_EN: u1, + /// Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK + EP0_INT_NAK: u1, + /// Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0 + EP0_INT_2BUF: u1, + /// Device: Set bit in BUFF_STATUS for every buffer completed on EP0 + EP0_INT_1BUF: u1, + /// Device: EP0 single buffered = 0, double buffered = 1 + EP0_DOUBLE_BUF: u1, + /// Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL + EP0_INT_STALL: u1, + }), base_address + 0x4c); + + /// address: 0x50110050 + /// SIE status register + pub const SIE_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + /// Device: VBUS Detected + VBUS_DETECTED: u1, + reserved0: u1 = 0, + /// USB bus line state + LINE_STATE: u2, + /// Bus in suspended state. Valid for device and host. Host and device will go into + /// suspend if neither Keep Alive / SOF frames are enabled. + SUSPENDED: u1, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// Host: device speed. Disconnected = 00, LS = 01, FS = 10 + SPEED: u2, + /// VBUS over current detected + VBUS_OVER_CURR: u1, + /// Host: Device has initiated a remote resume. Device: host has initiated a resume. + RESUME: u1, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Device: connected + CONNECTED: u1, + /// Device: Setup packet received + SETUP_REC: u1, + /// Transaction complete.\n\n + /// Raised by device if:\n\n + /// * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control + /// register\n\n + /// Raised by host if:\n\n + /// * A setup packet is sent when no data in or data out transaction follows * An IN + /// packet is received and the `LAST_BUFF` bit is set in the buffer control register + /// * An IN packet is received with zero length * An OUT packet is sent and the + /// `LAST_BUFF` bit is set + TRANS_COMPLETE: u1, + /// Device: bus reset received + BUS_RESET: u1, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// CRC Error. Raised by the Serial RX engine. + CRC_ERROR: u1, + /// Bit Stuff Error. Raised by the Serial RX engine. + BIT_STUFF_ERROR: u1, + /// RX overflow is raised by the Serial RX engine if the incoming data is too fast. + RX_OVERFLOW: u1, + /// RX timeout is raised by both the host and device if an ACK is not received in + /// the maximum time specified by the USB spec. + RX_TIMEOUT: u1, + /// Host: NAK received + NAK_REC: u1, + /// Host: STALL received + STALL_REC: u1, + /// ACK received. Raised by both host and device. + ACK_REC: u1, + /// Data Sequence Error.\n\n + /// The device can raise a sequence error in the following conditions:\n\n + /// * A SETUP packet is received followed by a DATA1 packet (data phase should + /// always be DATA0) * An OUT packet is received from the host but doesn't match the + /// data pid in the buffer control register read from DPSRAM\n\n + /// The host can raise a data sequence error in the following conditions:\n\n + /// * An IN packet from the device has the wrong data PID + DATA_SEQ_ERROR: u1, + }), base_address + 0x50); + + /// address: 0x50110054 + /// interrupt endpoint control register + pub const INT_EP_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + /// Host: Enable interrupt endpoint 1 -> 15 + INT_EP_ACTIVE: u15, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x54); + + /// address: 0x50110058 + /// Buffer status register. A bit set here indicates that a buffer has completed on + /// the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers + /// to be completed, so clearing the buffer status bit may instantly re set it on + /// the next clock cycle. + pub const BUFF_STATUS = @intToPtr(*volatile Mmio(32, packed struct { + EP0_IN: u1, + EP0_OUT: u1, + EP1_IN: u1, + EP1_OUT: u1, + EP2_IN: u1, + EP2_OUT: u1, + EP3_IN: u1, + EP3_OUT: u1, + EP4_IN: u1, + EP4_OUT: u1, + EP5_IN: u1, + EP5_OUT: u1, + EP6_IN: u1, + EP6_OUT: u1, + EP7_IN: u1, + EP7_OUT: u1, + EP8_IN: u1, + EP8_OUT: u1, + EP9_IN: u1, + EP9_OUT: u1, + EP10_IN: u1, + EP10_OUT: u1, + EP11_IN: u1, + EP11_OUT: u1, + EP12_IN: u1, + EP12_OUT: u1, + EP13_IN: u1, + EP13_OUT: u1, + EP14_IN: u1, + EP14_OUT: u1, + EP15_IN: u1, + EP15_OUT: u1, + }), base_address + 0x58); + + /// address: 0x5011005c + /// Which of the double buffers should be handled. Only valid if using an interrupt + /// per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint + /// polling because they are only single buffered. + pub const BUFF_CPU_SHOULD_HANDLE = @intToPtr(*volatile Mmio(32, packed struct { + EP0_IN: u1, + EP0_OUT: u1, + EP1_IN: u1, + EP1_OUT: u1, + EP2_IN: u1, + EP2_OUT: u1, + EP3_IN: u1, + EP3_OUT: u1, + EP4_IN: u1, + EP4_OUT: u1, + EP5_IN: u1, + EP5_OUT: u1, + EP6_IN: u1, + EP6_OUT: u1, + EP7_IN: u1, + EP7_OUT: u1, + EP8_IN: u1, + EP8_OUT: u1, + EP9_IN: u1, + EP9_OUT: u1, + EP10_IN: u1, + EP10_OUT: u1, + EP11_IN: u1, + EP11_OUT: u1, + EP12_IN: u1, + EP12_OUT: u1, + EP13_IN: u1, + EP13_OUT: u1, + EP14_IN: u1, + EP14_OUT: u1, + EP15_IN: u1, + EP15_OUT: u1, + }), base_address + 0x5c); + + /// address: 0x50110060 + /// Device only: Can be set to ignore the buffer control register for this endpoint + /// in case you would like to revoke a buffer. A NAK will be sent for every access + /// to the endpoint until this bit is cleared. A corresponding bit in + /// `EP_ABORT_DONE` is set when it is safe to modify the buffer control register. + pub const EP_ABORT = @intToPtr(*volatile Mmio(32, packed struct { + EP0_IN: u1, + EP0_OUT: u1, + EP1_IN: u1, + EP1_OUT: u1, + EP2_IN: u1, + EP2_OUT: u1, + EP3_IN: u1, + EP3_OUT: u1, + EP4_IN: u1, + EP4_OUT: u1, + EP5_IN: u1, + EP5_OUT: u1, + EP6_IN: u1, + EP6_OUT: u1, + EP7_IN: u1, + EP7_OUT: u1, + EP8_IN: u1, + EP8_OUT: u1, + EP9_IN: u1, + EP9_OUT: u1, + EP10_IN: u1, + EP10_OUT: u1, + EP11_IN: u1, + EP11_OUT: u1, + EP12_IN: u1, + EP12_OUT: u1, + EP13_IN: u1, + EP13_OUT: u1, + EP14_IN: u1, + EP14_OUT: u1, + EP15_IN: u1, + EP15_OUT: u1, + }), base_address + 0x60); + + /// address: 0x50110064 + /// Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle + /// so the programmer knows it is safe to modify the buffer control register. + pub const EP_ABORT_DONE = @intToPtr(*volatile Mmio(32, packed struct { + EP0_IN: u1, + EP0_OUT: u1, + EP1_IN: u1, + EP1_OUT: u1, + EP2_IN: u1, + EP2_OUT: u1, + EP3_IN: u1, + EP3_OUT: u1, + EP4_IN: u1, + EP4_OUT: u1, + EP5_IN: u1, + EP5_OUT: u1, + EP6_IN: u1, + EP6_OUT: u1, + EP7_IN: u1, + EP7_OUT: u1, + EP8_IN: u1, + EP8_OUT: u1, + EP9_IN: u1, + EP9_OUT: u1, + EP10_IN: u1, + EP10_OUT: u1, + EP11_IN: u1, + EP11_OUT: u1, + EP12_IN: u1, + EP12_OUT: u1, + EP13_IN: u1, + EP13_OUT: u1, + EP14_IN: u1, + EP14_OUT: u1, + EP15_IN: u1, + EP15_OUT: u1, + }), base_address + 0x64); + + /// address: 0x50110068 + /// Device: this bit must be set in conjunction with the `STALL` bit in the buffer + /// control register to send a STALL on EP0. The device controller clears these bits + /// when a SETUP packet is received because the USB spec requires that a STALL + /// condition is cleared when a SETUP packet is received. + pub const EP_STALL_ARM = @intToPtr(*volatile Mmio(32, packed struct { + EP0_IN: u1, + EP0_OUT: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x68); + + /// address: 0x5011006c + /// Used by the host controller. Sets the wait time in microseconds before trying + /// again if the device replies with a NAK. + pub const NAK_POLL = @intToPtr(*volatile Mmio(32, packed struct { + /// NAK polling interval for a low speed device + DELAY_LS: u10, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// NAK polling interval for a full speed device + DELAY_FS: u10, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + }), base_address + 0x6c); + + /// address: 0x50110070 + /// Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For + /// EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the + /// endpoint control register. + pub const EP_STATUS_STALL_NAK = @intToPtr(*volatile Mmio(32, packed struct { + EP0_IN: u1, + EP0_OUT: u1, + EP1_IN: u1, + EP1_OUT: u1, + EP2_IN: u1, + EP2_OUT: u1, + EP3_IN: u1, + EP3_OUT: u1, + EP4_IN: u1, + EP4_OUT: u1, + EP5_IN: u1, + EP5_OUT: u1, + EP6_IN: u1, + EP6_OUT: u1, + EP7_IN: u1, + EP7_OUT: u1, + EP8_IN: u1, + EP8_OUT: u1, + EP9_IN: u1, + EP9_OUT: u1, + EP10_IN: u1, + EP10_OUT: u1, + EP11_IN: u1, + EP11_OUT: u1, + EP12_IN: u1, + EP12_OUT: u1, + EP13_IN: u1, + EP13_OUT: u1, + EP14_IN: u1, + EP14_OUT: u1, + EP15_IN: u1, + EP15_OUT: u1, + }), base_address + 0x70); + + /// address: 0x50110074 + /// Where to connect the USB controller. Should be to_phy by default. + pub const USB_MUXING = @intToPtr(*volatile Mmio(32, packed struct { + TO_PHY: u1, + TO_EXTPHY: u1, + TO_DIGITAL_PAD: u1, + SOFTCON: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x74); + + /// address: 0x50110078 + /// Overrides for the power signals in the event that the VBUS signals are not + /// hooked up to GPIO. Set the value of the override and then the override enable to + /// switch over to the override value. + pub const USB_PWR = @intToPtr(*volatile Mmio(32, packed struct { + VBUS_EN: u1, + VBUS_EN_OVERRIDE_EN: u1, + VBUS_DETECT: u1, + VBUS_DETECT_OVERRIDE_EN: u1, + OVERCURR_DETECT: u1, + OVERCURR_DETECT_EN: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + }), base_address + 0x78); + + /// address: 0x5011007c + /// This register allows for direct control of the USB phy. Use in conjunction with + /// usbphy_direct_override register to enable each override bit. + pub const USBPHY_DIRECT = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + DP_PULLUP_HISEL: u1, + /// DP pull up enable + DP_PULLUP_EN: u1, + /// DP pull down enable + DP_PULLDN_EN: u1, + reserved0: u1 = 0, + /// Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2 + DM_PULLUP_HISEL: u1, + /// DM pull up enable + DM_PULLUP_EN: u1, + /// DM pull down enable + DM_PULLDN_EN: u1, + reserved1: u1 = 0, + /// Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z + /// state; 1 - DPP/DPM driving\n + /// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving + TX_DP_OE: u1, + /// Output enable. If TX_DIFFMODE=1, Ignored.\n + /// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving + TX_DM_OE: u1, + /// Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable + /// drive. DPP=TX_DP, DPM=~TX_DP\n + /// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP + TX_DP: u1, + /// Output data. TX_DIFFMODE=1, Ignored\n + /// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM + TX_DM: u1, + /// RX power down override (if override enable is set). 1 = powered down. + RX_PD: u1, + /// TX power down override (if override enable is set). 1 = powered down. + TX_PD: u1, + /// TX_FSSLEW=0: Low speed slew rate\n + /// TX_FSSLEW=1: Full speed slew rate + TX_FSSLEW: u1, + /// TX_DIFFMODE=0: Single ended mode\n + /// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored) + TX_DIFFMODE: u1, + /// Differential RX + RX_DD: u1, + /// DPP pin state + RX_DP: u1, + /// DPM pin state + RX_DM: u1, + /// DP overcurrent + DP_OVCN: u1, + /// DM overcurrent + DM_OVCN: u1, + /// DP over voltage + DP_OVV: u1, + /// DM over voltage + DM_OVV: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + }), base_address + 0x7c); + + /// address: 0x50110080 + /// Override enable for each control in usbphy_direct + pub const USBPHY_DIRECT_OVERRIDE = @intToPtr(*volatile Mmio(32, packed struct { + DP_PULLUP_HISEL_OVERRIDE_EN: u1, + DM_PULLUP_HISEL_OVERRIDE_EN: u1, + DP_PULLUP_EN_OVERRIDE_EN: u1, + DP_PULLDN_EN_OVERRIDE_EN: u1, + DM_PULLDN_EN_OVERRIDE_EN: u1, + TX_DP_OE_OVERRIDE_EN: u1, + TX_DM_OE_OVERRIDE_EN: u1, + TX_DP_OVERRIDE_EN: u1, + TX_DM_OVERRIDE_EN: u1, + RX_PD_OVERRIDE_EN: u1, + TX_PD_OVERRIDE_EN: u1, + TX_FSSLEW_OVERRIDE_EN: u1, + DM_PULLUP_OVERRIDE_EN: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + TX_DIFFMODE_OVERRIDE_EN: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x80); + + /// address: 0x50110084 + /// Used to adjust trim values of USB phy pull down resistors. + pub const USBPHY_TRIM = @intToPtr(*volatile Mmio(32, packed struct { + /// Value to drive to USB PHY\n + /// DP pulldown resistor trim control\n + /// Experimental data suggests that the reset value will work, but this register + /// allows adjustment if required + DP_PULLDN_TRIM: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// Value to drive to USB PHY\n + /// DM pulldown resistor trim control\n + /// Experimental data suggests that the reset value will work, but this register + /// allows adjustment if required + DM_PULLDN_TRIM: u5, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + }), base_address + 0x84); + + /// address: 0x5011008c + /// Raw Interrupts + pub const INTR = @intToPtr(*volatile Mmio(32, packed struct { + /// Host: raised when a device is connected or disconnected (i.e. when + /// SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + HOST_CONN_DIS: u1, + /// Host: raised when a device wakes up the host. Cleared by writing to + /// SIE_STATUS.RESUME + HOST_RESUME: u1, + /// Host: raised every time the host sends a SOF (Start of Frame). Cleared by + /// reading SOF_RD + HOST_SOF: u1, + /// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this + /// bit. + TRANS_COMPLETE: u1, + /// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in + /// BUFF_STATUS. + BUFF_STATUS: u1, + /// Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ: u1, + /// Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT: u1, + /// Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW: u1, + /// Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF: u1, + /// Source: SIE_STATUS.CRC_ERROR + ERROR_CRC: u1, + /// Source: SIE_STATUS.STALL_REC + STALL: u1, + /// Source: SIE_STATUS.VBUS_DETECTED + VBUS_DETECT: u1, + /// Source: SIE_STATUS.BUS_RESET + BUS_RESET: u1, + /// Set when the device connection state changes. Cleared by writing to + /// SIE_STATUS.CONNECTED + DEV_CONN_DIS: u1, + /// Set when the device suspend state changes. Cleared by writing to + /// SIE_STATUS.SUSPENDED + DEV_SUSPEND: u1, + /// Set when the device receives a resume from the host. Cleared by writing to + /// SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST: u1, + /// Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ: u1, + /// Set every time the device receives a SOF (Start of Frame) packet. Cleared by + /// reading SOF_RD + DEV_SOF: u1, + /// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in + /// ABORT_DONE. + ABORT_DONE: u1, + /// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in + /// EP_STATUS_STALL_NAK. + EP_STALL_NAK: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + }), base_address + 0x8c); + + /// address: 0x50110090 + /// Interrupt Enable + pub const INTE = @intToPtr(*volatile Mmio(32, packed struct { + /// Host: raised when a device is connected or disconnected (i.e. when + /// SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + HOST_CONN_DIS: u1, + /// Host: raised when a device wakes up the host. Cleared by writing to + /// SIE_STATUS.RESUME + HOST_RESUME: u1, + /// Host: raised every time the host sends a SOF (Start of Frame). Cleared by + /// reading SOF_RD + HOST_SOF: u1, + /// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this + /// bit. + TRANS_COMPLETE: u1, + /// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in + /// BUFF_STATUS. + BUFF_STATUS: u1, + /// Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ: u1, + /// Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT: u1, + /// Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW: u1, + /// Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF: u1, + /// Source: SIE_STATUS.CRC_ERROR + ERROR_CRC: u1, + /// Source: SIE_STATUS.STALL_REC + STALL: u1, + /// Source: SIE_STATUS.VBUS_DETECTED + VBUS_DETECT: u1, + /// Source: SIE_STATUS.BUS_RESET + BUS_RESET: u1, + /// Set when the device connection state changes. Cleared by writing to + /// SIE_STATUS.CONNECTED + DEV_CONN_DIS: u1, + /// Set when the device suspend state changes. Cleared by writing to + /// SIE_STATUS.SUSPENDED + DEV_SUSPEND: u1, + /// Set when the device receives a resume from the host. Cleared by writing to + /// SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST: u1, + /// Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ: u1, + /// Set every time the device receives a SOF (Start of Frame) packet. Cleared by + /// reading SOF_RD + DEV_SOF: u1, + /// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in + /// ABORT_DONE. + ABORT_DONE: u1, + /// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in + /// EP_STATUS_STALL_NAK. + EP_STALL_NAK: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + }), base_address + 0x90); + + /// address: 0x50110094 + /// Interrupt Force + pub const INTF = @intToPtr(*volatile Mmio(32, packed struct { + /// Host: raised when a device is connected or disconnected (i.e. when + /// SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + HOST_CONN_DIS: u1, + /// Host: raised when a device wakes up the host. Cleared by writing to + /// SIE_STATUS.RESUME + HOST_RESUME: u1, + /// Host: raised every time the host sends a SOF (Start of Frame). Cleared by + /// reading SOF_RD + HOST_SOF: u1, + /// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this + /// bit. + TRANS_COMPLETE: u1, + /// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in + /// BUFF_STATUS. + BUFF_STATUS: u1, + /// Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ: u1, + /// Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT: u1, + /// Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW: u1, + /// Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF: u1, + /// Source: SIE_STATUS.CRC_ERROR + ERROR_CRC: u1, + /// Source: SIE_STATUS.STALL_REC + STALL: u1, + /// Source: SIE_STATUS.VBUS_DETECTED + VBUS_DETECT: u1, + /// Source: SIE_STATUS.BUS_RESET + BUS_RESET: u1, + /// Set when the device connection state changes. Cleared by writing to + /// SIE_STATUS.CONNECTED + DEV_CONN_DIS: u1, + /// Set when the device suspend state changes. Cleared by writing to + /// SIE_STATUS.SUSPENDED + DEV_SUSPEND: u1, + /// Set when the device receives a resume from the host. Cleared by writing to + /// SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST: u1, + /// Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ: u1, + /// Set every time the device receives a SOF (Start of Frame) packet. Cleared by + /// reading SOF_RD + DEV_SOF: u1, + /// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in + /// ABORT_DONE. + ABORT_DONE: u1, + /// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in + /// EP_STATUS_STALL_NAK. + EP_STALL_NAK: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + }), base_address + 0x94); + + /// address: 0x50110098 + /// Interrupt status after masking & forcing + pub const INTS = @intToPtr(*volatile Mmio(32, packed struct { + /// Host: raised when a device is connected or disconnected (i.e. when + /// SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED + HOST_CONN_DIS: u1, + /// Host: raised when a device wakes up the host. Cleared by writing to + /// SIE_STATUS.RESUME + HOST_RESUME: u1, + /// Host: raised every time the host sends a SOF (Start of Frame). Cleared by + /// reading SOF_RD + HOST_SOF: u1, + /// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this + /// bit. + TRANS_COMPLETE: u1, + /// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in + /// BUFF_STATUS. + BUFF_STATUS: u1, + /// Source: SIE_STATUS.DATA_SEQ_ERROR + ERROR_DATA_SEQ: u1, + /// Source: SIE_STATUS.RX_TIMEOUT + ERROR_RX_TIMEOUT: u1, + /// Source: SIE_STATUS.RX_OVERFLOW + ERROR_RX_OVERFLOW: u1, + /// Source: SIE_STATUS.BIT_STUFF_ERROR + ERROR_BIT_STUFF: u1, + /// Source: SIE_STATUS.CRC_ERROR + ERROR_CRC: u1, + /// Source: SIE_STATUS.STALL_REC + STALL: u1, + /// Source: SIE_STATUS.VBUS_DETECTED + VBUS_DETECT: u1, + /// Source: SIE_STATUS.BUS_RESET + BUS_RESET: u1, + /// Set when the device connection state changes. Cleared by writing to + /// SIE_STATUS.CONNECTED + DEV_CONN_DIS: u1, + /// Set when the device suspend state changes. Cleared by writing to + /// SIE_STATUS.SUSPENDED + DEV_SUSPEND: u1, + /// Set when the device receives a resume from the host. Cleared by writing to + /// SIE_STATUS.RESUME + DEV_RESUME_FROM_HOST: u1, + /// Device. Source: SIE_STATUS.SETUP_REC + SETUP_REQ: u1, + /// Set every time the device receives a SOF (Start of Frame) packet. Cleared by + /// reading SOF_RD + DEV_SOF: u1, + /// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in + /// ABORT_DONE. + ABORT_DONE: u1, + /// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in + /// EP_STATUS_STALL_NAK. + EP_STALL_NAK: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + }), base_address + 0x98); + }; + + /// Programmable IO block + pub const PIO0 = struct { + pub const base_address = 0x50200000; + pub const version = "1"; + + /// address: 0x50200000 + /// PIO control register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable/disable each of the four state machines by writing 1/0 to each of these + /// four bits. When disabled, a state machine will cease executing instructions, + /// except those written directly to SMx_INSTR by the system. Multiple bits can be + /// set/cleared at once to run/halt multiple state machines simultaneously. + SM_ENABLE: u4, + /// Write 1 to instantly clear internal SM state which may be otherwise difficult to + /// access and will affect future execution.\n\n + /// Specifically, the following are cleared: input and output shift counters; the + /// contents of the input shift register; the delay counter; the waiting-on-IRQ + /// state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any + /// pin write left asserted due to OUT_STICKY. + SM_RESTART: u4, + /// Restart a state machine's clock divider from an initial phase of 0. Clock + /// dividers are free-running, so once started, their output (including fractional + /// jitter) is completely determined by the integer/fractional divisor configured in + /// SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor + /// are restarted simultaneously, by writing multiple 1 bits to this field, the + /// execution clocks of those state machines will run in precise lockstep.\n\n + /// Note that setting/clearing SM_ENABLE does not stop the clock divider from + /// running, so once multiple state machines' clocks are synchronised, it is safe to + /// disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n + /// Note also that CLKDIV_RESTART can be written to whilst the state machine is + /// running, and this is useful to resynchronise clock dividers after the divisors + /// (SMx_CLKDIV) have been changed on-the-fly. + CLKDIV_RESTART: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x0); + + /// address: 0x50200004 + /// FIFO status register + pub const FSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// State machine RX FIFO is full + RXFULL: u4, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// State machine RX FIFO is empty + RXEMPTY: u4, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// State machine TX FIFO is full + TXFULL: u4, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// State machine TX FIFO is empty + TXEMPTY: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + }), base_address + 0x4); + + /// address: 0x50200008 + /// FIFO debug register + pub const FDEBUG = @intToPtr(*volatile Mmio(32, packed struct { + /// State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with + /// autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO + /// took place, in which case the state machine has dropped data. Write 1 to clear. + RXSTALL: u4, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to + /// clear. Note that read-on-empty does not perturb the state of the FIFO in any + /// way, but the data returned by reading from an empty FIFO is undefined, so this + /// flag generally only becomes set due to some kind of software error. + RXUNDER: u4, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to + /// clear. Note that write-on-full does not alter the state or contents of the FIFO + /// in any way, but the data that the system attempted to write is dropped, so if + /// this flag is set, your software has quite likely dropped some data on the floor. + TXOVER: u4, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT + /// with autopull enabled. Write 1 to clear. + TXSTALL: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + }), base_address + 0x8); + + /// address: 0x5020000c + /// FIFO levels + pub const FLEVEL = @intToPtr(*volatile Mmio(32, packed struct { + TX0: u4, + RX0: u4, + TX1: u4, + RX1: u4, + TX2: u4, + RX2: u4, + TX3: u4, + RX3: u4, + }), base_address + 0xc); + + /// address: 0x50200010 + /// Direct write access to the TX FIFO for this state machine. Each write pushes one + /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO + /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + pub const TXF0 = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x50200014 + /// Direct write access to the TX FIFO for this state machine. Each write pushes one + /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO + /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + pub const TXF1 = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x50200018 + /// Direct write access to the TX FIFO for this state machine. Each write pushes one + /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO + /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + pub const TXF2 = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x5020001c + /// Direct write access to the TX FIFO for this state machine. Each write pushes one + /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO + /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + pub const TXF3 = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x50200020 + /// Direct read access to the RX FIFO for this state machine. Each read pops one + /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the + /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The + /// data returned to the system on a read from an empty FIFO is undefined. + pub const RXF0 = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x50200024 + /// Direct read access to the RX FIFO for this state machine. Each read pops one + /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the + /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The + /// data returned to the system on a read from an empty FIFO is undefined. + pub const RXF1 = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x50200028 + /// Direct read access to the RX FIFO for this state machine. Each read pops one + /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the + /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The + /// data returned to the system on a read from an empty FIFO is undefined. + pub const RXF2 = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x5020002c + /// Direct read access to the RX FIFO for this state machine. Each read pops one + /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the + /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The + /// data returned to the system on a read from an empty FIFO is undefined. + pub const RXF3 = @intToPtr(*volatile u32, base_address + 0x2c); + + /// address: 0x50200030 + /// State machine IRQ flags register. Write 1 to clear. There are 8 state machine + /// IRQ flags, which can be set, cleared, and waited on by the state machines. + /// There's no fixed association between flags and state machines -- any state + /// machine can use any flag.\n\n + /// Any of the 8 flags can be used for timing synchronisation between state + /// machines, using IRQ and WAIT instructions. The lower four of these flags are + /// also routed out to system-level interrupt requests, alongside FIFO status + /// interrupts -- see e.g. IRQ0_INTE. + pub const IRQ = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x30); + + /// address: 0x50200034 + /// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. + /// Note this is different to the INTF register: writing here affects PIO internal + /// state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and + /// is not visible to the state machines. + pub const IRQ_FORCE = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x34); + + /// address: 0x50200038 + /// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic + /// from metastabilities. This increases input delay, and for fast synchronous IO + /// (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this + /// register corresponds to one GPIO.\n + /// 0 -> input is synchronized (default)\n + /// 1 -> synchronizer is bypassed\n + /// If in doubt, leave this register as all zeroes. + pub const INPUT_SYNC_BYPASS = @intToPtr(*volatile u32, base_address + 0x38); + + /// address: 0x5020003c + /// Read to sample the pad output values PIO is currently driving to the GPIOs. On + /// RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + pub const DBG_PADOUT = @intToPtr(*volatile u32, base_address + 0x3c); + + /// address: 0x50200040 + /// Read to sample the pad output enables (direction) PIO is currently driving to + /// the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are + /// hardwired to 0. + pub const DBG_PADOE = @intToPtr(*volatile u32, base_address + 0x40); + + /// address: 0x50200044 + /// The PIO hardware has some free parameters that may vary between chip products.\n + /// These should be provided in the chip datasheet, but are also exposed here. + pub const DBG_CFGINFO = @intToPtr(*volatile Mmio(32, packed struct { + /// The depth of the state machine TX/RX FIFOs, measured in words.\n + /// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n + /// this depth. + FIFO_DEPTH: u6, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// The number of state machines this PIO instance is equipped with. + SM_COUNT: u4, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// The size of the instruction memory, measured in units of one instruction + IMEM_SIZE: u6, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + }), base_address + 0x44); + + /// address: 0x50200048 + /// Write-only access to instruction memory location 0 + pub const INSTR_MEM0 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x48); + + /// address: 0x5020004c + /// Write-only access to instruction memory location 1 + pub const INSTR_MEM1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x4c); + + /// address: 0x50200050 + /// Write-only access to instruction memory location 2 + pub const INSTR_MEM2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x50); + + /// address: 0x50200054 + /// Write-only access to instruction memory location 3 + pub const INSTR_MEM3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x54); + + /// address: 0x50200058 + /// Write-only access to instruction memory location 4 + pub const INSTR_MEM4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x58); + + /// address: 0x5020005c + /// Write-only access to instruction memory location 5 + pub const INSTR_MEM5 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c); + + /// address: 0x50200060 + /// Write-only access to instruction memory location 6 + pub const INSTR_MEM6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x60); + + /// address: 0x50200064 + /// Write-only access to instruction memory location 7 + pub const INSTR_MEM7 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x64); + + /// address: 0x50200068 + /// Write-only access to instruction memory location 8 + pub const INSTR_MEM8 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x68); + + /// address: 0x5020006c + /// Write-only access to instruction memory location 9 + pub const INSTR_MEM9 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x6c); + + /// address: 0x50200070 + /// Write-only access to instruction memory location 10 + pub const INSTR_MEM10 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x70); + + /// address: 0x50200074 + /// Write-only access to instruction memory location 11 + pub const INSTR_MEM11 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x74); + + /// address: 0x50200078 + /// Write-only access to instruction memory location 12 + pub const INSTR_MEM12 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x78); + + /// address: 0x5020007c + /// Write-only access to instruction memory location 13 + pub const INSTR_MEM13 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x7c); + + /// address: 0x50200080 + /// Write-only access to instruction memory location 14 + pub const INSTR_MEM14 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x80); + + /// address: 0x50200084 + /// Write-only access to instruction memory location 15 + pub const INSTR_MEM15 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x84); + + /// address: 0x50200088 + /// Write-only access to instruction memory location 16 + pub const INSTR_MEM16 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x88); + + /// address: 0x5020008c + /// Write-only access to instruction memory location 17 + pub const INSTR_MEM17 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x8c); + + /// address: 0x50200090 + /// Write-only access to instruction memory location 18 + pub const INSTR_MEM18 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x90); + + /// address: 0x50200094 + /// Write-only access to instruction memory location 19 + pub const INSTR_MEM19 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x94); + + /// address: 0x50200098 + /// Write-only access to instruction memory location 20 + pub const INSTR_MEM20 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x98); + + /// address: 0x5020009c + /// Write-only access to instruction memory location 21 + pub const INSTR_MEM21 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x9c); + + /// address: 0x502000a0 + /// Write-only access to instruction memory location 22 + pub const INSTR_MEM22 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa0); + + /// address: 0x502000a4 + /// Write-only access to instruction memory location 23 + pub const INSTR_MEM23 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa4); + + /// address: 0x502000a8 + /// Write-only access to instruction memory location 24 + pub const INSTR_MEM24 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa8); + + /// address: 0x502000ac + /// Write-only access to instruction memory location 25 + pub const INSTR_MEM25 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xac); + + /// address: 0x502000b0 + /// Write-only access to instruction memory location 26 + pub const INSTR_MEM26 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb0); + + /// address: 0x502000b4 + /// Write-only access to instruction memory location 27 + pub const INSTR_MEM27 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb4); + + /// address: 0x502000b8 + /// Write-only access to instruction memory location 28 + pub const INSTR_MEM28 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb8); + + /// address: 0x502000bc + /// Write-only access to instruction memory location 29 + pub const INSTR_MEM29 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xbc); + + /// address: 0x502000c0 + /// Write-only access to instruction memory location 30 + pub const INSTR_MEM30 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc0); + + /// address: 0x502000c4 + /// Write-only access to instruction memory location 31 + pub const INSTR_MEM31 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc4); + + /// address: 0x502000c8 + /// Clock divisor register for state machine 0\n + /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + pub const SM0_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Fractional part of clock divisor + FRAC: u8, + /// Effective frequency is sysclk/(int + frac/256).\n + /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + INT: u16, + }), base_address + 0xc8); + + /// address: 0x502000cc + /// Execution/behavioural settings for state machine 0 + pub const SM0_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Comparison level for the MOV x, STATUS instruction + STATUS_N: u4, + /// Comparison used for the MOV x, STATUS instruction. + STATUS_SEL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM: u5, + /// After reaching this address, execution is wrapped to wrap_bottom.\n + /// If the instruction is a jump, and the jump condition is true, the jump takes + /// priority. + WRAP_TOP: u5, + /// Continuously assert the most recent OUT/SET to the pins + OUT_STICKY: u1, + /// If 1, use a bit of OUT data as an auxiliary write enable\n + /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + /// deassert the latest pin write. This can create useful masking/override + /// behaviour\n + /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN: u1, + /// Which data bit to use for inline OUT enable + OUT_EN_SEL: u5, + /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN: u5, + /// If 1, side-set data is asserted to pin directions, instead of pin values + SIDE_PINDIR: u1, + /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set + /// enable, rather than a side-set data bit. This allows instructions to perform + /// side-set optionally, rather than on every instruction, but the maximum possible + /// side-set width is reduced from 5 to 4. Note that the value of + /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + SIDE_EN: u1, + /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state + /// machine. Will clear to 0 once this instruction completes. + EXEC_STALLED: u1, + }), base_address + 0xcc); + + /// address: 0x502000d0 + /// Control behaviour of the input/output shift registers for state machine 0 + pub const SM0_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + /// Push automatically when the input shift register is filled, i.e. on an IN + /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + AUTOPUSH: u1, + /// Pull automatically when the output shift register is emptied, i.e. on or + /// following an OUT instruction which causes the output shift counter to reach or + /// exceed PULL_THRESH. + AUTOPULL: u1, + /// 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR: u1, + /// 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR: u1, + /// Number of bits shifted into ISR before autopush, or conditional push (PUSH + /// IFFULL), will take place.\n + /// Write 0 for value of 32. + PUSH_THRESH: u5, + /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL + /// IFEMPTY), will take place.\n + /// Write 0 for value of 32. + PULL_THRESH: u5, + /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + /// RX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_TX: u1, + /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + /// TX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_RX: u1, + }), base_address + 0xd0); + + /// address: 0x502000d4 + /// Current instruction address of state machine 0 + pub const SM0_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd4); + + /// address: 0x502000d8 + /// Read to see the instruction currently addressed by state machine 0's program + /// counter\n + /// Write to execute an instruction immediately (including jumps) and then resume + /// execution. + pub const SM0_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xd8); + + /// address: 0x502000dc + /// State machine pin control + pub const SM0_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV + /// PINS instruction. The data written to this pin will always be the + /// least-significant bit of the OUT or MOV data. + OUT_BASE: u5, + /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS + /// instruction. The data written to this pin is the least-significant bit of the + /// SET data. + SET_BASE: u5, + /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs + /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) + /// are used for side-set data, with the remaining LSBs used for delay. The + /// least-significant bit of the side-set portion is the bit written to this pin, + /// with more-significant bits written to higher-numbered pins. + SIDESET_BASE: u5, + /// The pin which is mapped to the least-significant bit of a state machine's IN + /// data bus. Higher-numbered pins are mapped to consecutively more-significant data + /// bits, with a modulo of 32 applied to pin number. + IN_BASE: u5, + /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. + /// In the range 0 to 32 inclusive. + OUT_COUNT: u6, + /// The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT: u3, + /// The number of MSBs of the Delay/Side-set instruction field which are used for + /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, + /// no side-set) and maximum of 5 (all side-set, no delay). + SIDESET_COUNT: u3, + }), base_address + 0xdc); + + /// address: 0x502000e0 + /// Clock divisor register for state machine 1\n + /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + pub const SM1_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Fractional part of clock divisor + FRAC: u8, + /// Effective frequency is sysclk/(int + frac/256).\n + /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + INT: u16, + }), base_address + 0xe0); + + /// address: 0x502000e4 + /// Execution/behavioural settings for state machine 1 + pub const SM1_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Comparison level for the MOV x, STATUS instruction + STATUS_N: u4, + /// Comparison used for the MOV x, STATUS instruction. + STATUS_SEL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM: u5, + /// After reaching this address, execution is wrapped to wrap_bottom.\n + /// If the instruction is a jump, and the jump condition is true, the jump takes + /// priority. + WRAP_TOP: u5, + /// Continuously assert the most recent OUT/SET to the pins + OUT_STICKY: u1, + /// If 1, use a bit of OUT data as an auxiliary write enable\n + /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + /// deassert the latest pin write. This can create useful masking/override + /// behaviour\n + /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN: u1, + /// Which data bit to use for inline OUT enable + OUT_EN_SEL: u5, + /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN: u5, + /// If 1, side-set data is asserted to pin directions, instead of pin values + SIDE_PINDIR: u1, + /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set + /// enable, rather than a side-set data bit. This allows instructions to perform + /// side-set optionally, rather than on every instruction, but the maximum possible + /// side-set width is reduced from 5 to 4. Note that the value of + /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + SIDE_EN: u1, + /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state + /// machine. Will clear to 0 once this instruction completes. + EXEC_STALLED: u1, + }), base_address + 0xe4); + + /// address: 0x502000e8 + /// Control behaviour of the input/output shift registers for state machine 1 + pub const SM1_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + /// Push automatically when the input shift register is filled, i.e. on an IN + /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + AUTOPUSH: u1, + /// Pull automatically when the output shift register is emptied, i.e. on or + /// following an OUT instruction which causes the output shift counter to reach or + /// exceed PULL_THRESH. + AUTOPULL: u1, + /// 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR: u1, + /// 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR: u1, + /// Number of bits shifted into ISR before autopush, or conditional push (PUSH + /// IFFULL), will take place.\n + /// Write 0 for value of 32. + PUSH_THRESH: u5, + /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL + /// IFEMPTY), will take place.\n + /// Write 0 for value of 32. + PULL_THRESH: u5, + /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + /// RX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_TX: u1, + /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + /// TX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_RX: u1, + }), base_address + 0xe8); + + /// address: 0x502000ec + /// Current instruction address of state machine 1 + pub const SM1_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xec); + + /// address: 0x502000f0 + /// Read to see the instruction currently addressed by state machine 1's program + /// counter\n + /// Write to execute an instruction immediately (including jumps) and then resume + /// execution. + pub const SM1_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xf0); + + /// address: 0x502000f4 + /// State machine pin control + pub const SM1_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV + /// PINS instruction. The data written to this pin will always be the + /// least-significant bit of the OUT or MOV data. + OUT_BASE: u5, + /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS + /// instruction. The data written to this pin is the least-significant bit of the + /// SET data. + SET_BASE: u5, + /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs + /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) + /// are used for side-set data, with the remaining LSBs used for delay. The + /// least-significant bit of the side-set portion is the bit written to this pin, + /// with more-significant bits written to higher-numbered pins. + SIDESET_BASE: u5, + /// The pin which is mapped to the least-significant bit of a state machine's IN + /// data bus. Higher-numbered pins are mapped to consecutively more-significant data + /// bits, with a modulo of 32 applied to pin number. + IN_BASE: u5, + /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. + /// In the range 0 to 32 inclusive. + OUT_COUNT: u6, + /// The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT: u3, + /// The number of MSBs of the Delay/Side-set instruction field which are used for + /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, + /// no side-set) and maximum of 5 (all side-set, no delay). + SIDESET_COUNT: u3, + }), base_address + 0xf4); + + /// address: 0x502000f8 + /// Clock divisor register for state machine 2\n + /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + pub const SM2_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Fractional part of clock divisor + FRAC: u8, + /// Effective frequency is sysclk/(int + frac/256).\n + /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + INT: u16, + }), base_address + 0xf8); + + /// address: 0x502000fc + /// Execution/behavioural settings for state machine 2 + pub const SM2_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Comparison level for the MOV x, STATUS instruction + STATUS_N: u4, + /// Comparison used for the MOV x, STATUS instruction. + STATUS_SEL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM: u5, + /// After reaching this address, execution is wrapped to wrap_bottom.\n + /// If the instruction is a jump, and the jump condition is true, the jump takes + /// priority. + WRAP_TOP: u5, + /// Continuously assert the most recent OUT/SET to the pins + OUT_STICKY: u1, + /// If 1, use a bit of OUT data as an auxiliary write enable\n + /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + /// deassert the latest pin write. This can create useful masking/override + /// behaviour\n + /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN: u1, + /// Which data bit to use for inline OUT enable + OUT_EN_SEL: u5, + /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN: u5, + /// If 1, side-set data is asserted to pin directions, instead of pin values + SIDE_PINDIR: u1, + /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set + /// enable, rather than a side-set data bit. This allows instructions to perform + /// side-set optionally, rather than on every instruction, but the maximum possible + /// side-set width is reduced from 5 to 4. Note that the value of + /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + SIDE_EN: u1, + /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state + /// machine. Will clear to 0 once this instruction completes. + EXEC_STALLED: u1, + }), base_address + 0xfc); + + /// address: 0x50200100 + /// Control behaviour of the input/output shift registers for state machine 2 + pub const SM2_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + /// Push automatically when the input shift register is filled, i.e. on an IN + /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + AUTOPUSH: u1, + /// Pull automatically when the output shift register is emptied, i.e. on or + /// following an OUT instruction which causes the output shift counter to reach or + /// exceed PULL_THRESH. + AUTOPULL: u1, + /// 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR: u1, + /// 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR: u1, + /// Number of bits shifted into ISR before autopush, or conditional push (PUSH + /// IFFULL), will take place.\n + /// Write 0 for value of 32. + PUSH_THRESH: u5, + /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL + /// IFEMPTY), will take place.\n + /// Write 0 for value of 32. + PULL_THRESH: u5, + /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + /// RX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_TX: u1, + /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + /// TX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_RX: u1, + }), base_address + 0x100); + + /// address: 0x50200104 + /// Current instruction address of state machine 2 + pub const SM2_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x104); + + /// address: 0x50200108 + /// Read to see the instruction currently addressed by state machine 2's program + /// counter\n + /// Write to execute an instruction immediately (including jumps) and then resume + /// execution. + pub const SM2_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x108); + + /// address: 0x5020010c + /// State machine pin control + pub const SM2_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV + /// PINS instruction. The data written to this pin will always be the + /// least-significant bit of the OUT or MOV data. + OUT_BASE: u5, + /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS + /// instruction. The data written to this pin is the least-significant bit of the + /// SET data. + SET_BASE: u5, + /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs + /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) + /// are used for side-set data, with the remaining LSBs used for delay. The + /// least-significant bit of the side-set portion is the bit written to this pin, + /// with more-significant bits written to higher-numbered pins. + SIDESET_BASE: u5, + /// The pin which is mapped to the least-significant bit of a state machine's IN + /// data bus. Higher-numbered pins are mapped to consecutively more-significant data + /// bits, with a modulo of 32 applied to pin number. + IN_BASE: u5, + /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. + /// In the range 0 to 32 inclusive. + OUT_COUNT: u6, + /// The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT: u3, + /// The number of MSBs of the Delay/Side-set instruction field which are used for + /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, + /// no side-set) and maximum of 5 (all side-set, no delay). + SIDESET_COUNT: u3, + }), base_address + 0x10c); + + /// address: 0x50200110 + /// Clock divisor register for state machine 3\n + /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + pub const SM3_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Fractional part of clock divisor + FRAC: u8, + /// Effective frequency is sysclk/(int + frac/256).\n + /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + INT: u16, + }), base_address + 0x110); + + /// address: 0x50200114 + /// Execution/behavioural settings for state machine 3 + pub const SM3_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Comparison level for the MOV x, STATUS instruction + STATUS_N: u4, + /// Comparison used for the MOV x, STATUS instruction. + STATUS_SEL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM: u5, + /// After reaching this address, execution is wrapped to wrap_bottom.\n + /// If the instruction is a jump, and the jump condition is true, the jump takes + /// priority. + WRAP_TOP: u5, + /// Continuously assert the most recent OUT/SET to the pins + OUT_STICKY: u1, + /// If 1, use a bit of OUT data as an auxiliary write enable\n + /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + /// deassert the latest pin write. This can create useful masking/override + /// behaviour\n + /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN: u1, + /// Which data bit to use for inline OUT enable + OUT_EN_SEL: u5, + /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN: u5, + /// If 1, side-set data is asserted to pin directions, instead of pin values + SIDE_PINDIR: u1, + /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set + /// enable, rather than a side-set data bit. This allows instructions to perform + /// side-set optionally, rather than on every instruction, but the maximum possible + /// side-set width is reduced from 5 to 4. Note that the value of + /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + SIDE_EN: u1, + /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state + /// machine. Will clear to 0 once this instruction completes. + EXEC_STALLED: u1, + }), base_address + 0x114); + + /// address: 0x50200118 + /// Control behaviour of the input/output shift registers for state machine 3 + pub const SM3_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + /// Push automatically when the input shift register is filled, i.e. on an IN + /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + AUTOPUSH: u1, + /// Pull automatically when the output shift register is emptied, i.e. on or + /// following an OUT instruction which causes the output shift counter to reach or + /// exceed PULL_THRESH. + AUTOPULL: u1, + /// 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR: u1, + /// 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR: u1, + /// Number of bits shifted into ISR before autopush, or conditional push (PUSH + /// IFFULL), will take place.\n + /// Write 0 for value of 32. + PUSH_THRESH: u5, + /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL + /// IFEMPTY), will take place.\n + /// Write 0 for value of 32. + PULL_THRESH: u5, + /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + /// RX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_TX: u1, + /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + /// TX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_RX: u1, + }), base_address + 0x118); + + /// address: 0x5020011c + /// Current instruction address of state machine 3 + pub const SM3_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x11c); + + /// address: 0x50200120 + /// Read to see the instruction currently addressed by state machine 3's program + /// counter\n + /// Write to execute an instruction immediately (including jumps) and then resume + /// execution. + pub const SM3_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x120); + + /// address: 0x50200124 + /// State machine pin control + pub const SM3_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV + /// PINS instruction. The data written to this pin will always be the + /// least-significant bit of the OUT or MOV data. + OUT_BASE: u5, + /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS + /// instruction. The data written to this pin is the least-significant bit of the + /// SET data. + SET_BASE: u5, + /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs + /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) + /// are used for side-set data, with the remaining LSBs used for delay. The + /// least-significant bit of the side-set portion is the bit written to this pin, + /// with more-significant bits written to higher-numbered pins. + SIDESET_BASE: u5, + /// The pin which is mapped to the least-significant bit of a state machine's IN + /// data bus. Higher-numbered pins are mapped to consecutively more-significant data + /// bits, with a modulo of 32 applied to pin number. + IN_BASE: u5, + /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. + /// In the range 0 to 32 inclusive. + OUT_COUNT: u6, + /// The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT: u3, + /// The number of MSBs of the Delay/Side-set instruction field which are used for + /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, + /// no side-set) and maximum of 5 (all side-set, no delay). + SIDESET_COUNT: u3, + }), base_address + 0x124); + + /// address: 0x50200128 + /// Raw Interrupts + pub const INTR = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x128); + + /// address: 0x5020012c + /// Interrupt Enable for irq0 + pub const IRQ0_INTE = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x12c); + + /// address: 0x50200130 + /// Interrupt Force for irq0 + pub const IRQ0_INTF = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x130); + + /// address: 0x50200134 + /// Interrupt status after masking & forcing for irq0 + pub const IRQ0_INTS = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x134); + + /// address: 0x50200138 + /// Interrupt Enable for irq1 + pub const IRQ1_INTE = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x138); + + /// address: 0x5020013c + /// Interrupt Force for irq1 + pub const IRQ1_INTF = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x13c); + + /// address: 0x50200140 + /// Interrupt status after masking & forcing for irq1 + pub const IRQ1_INTS = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x140); + }; + pub const PIO1 = struct { + pub const base_address = 0x50300000; + + /// address: 0x50300000 + /// PIO control register + pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable/disable each of the four state machines by writing 1/0 to each of these + /// four bits. When disabled, a state machine will cease executing instructions, + /// except those written directly to SMx_INSTR by the system. Multiple bits can be + /// set/cleared at once to run/halt multiple state machines simultaneously. + SM_ENABLE: u4, + /// Write 1 to instantly clear internal SM state which may be otherwise difficult to + /// access and will affect future execution.\n\n + /// Specifically, the following are cleared: input and output shift counters; the + /// contents of the input shift register; the delay counter; the waiting-on-IRQ + /// state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any + /// pin write left asserted due to OUT_STICKY. + SM_RESTART: u4, + /// Restart a state machine's clock divider from an initial phase of 0. Clock + /// dividers are free-running, so once started, their output (including fractional + /// jitter) is completely determined by the integer/fractional divisor configured in + /// SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor + /// are restarted simultaneously, by writing multiple 1 bits to this field, the + /// execution clocks of those state machines will run in precise lockstep.\n\n + /// Note that setting/clearing SM_ENABLE does not stop the clock divider from + /// running, so once multiple state machines' clocks are synchronised, it is safe to + /// disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n + /// Note also that CLKDIV_RESTART can be written to whilst the state machine is + /// running, and this is useful to resynchronise clock dividers after the divisors + /// (SMx_CLKDIV) have been changed on-the-fly. + CLKDIV_RESTART: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x0); + + /// address: 0x50300004 + /// FIFO status register + pub const FSTAT = @intToPtr(*volatile Mmio(32, packed struct { + /// State machine RX FIFO is full + RXFULL: u4, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// State machine RX FIFO is empty + RXEMPTY: u4, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// State machine TX FIFO is full + TXFULL: u4, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// State machine TX FIFO is empty + TXEMPTY: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + }), base_address + 0x4); + + /// address: 0x50300008 + /// FIFO debug register + pub const FDEBUG = @intToPtr(*volatile Mmio(32, packed struct { + /// State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with + /// autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO + /// took place, in which case the state machine has dropped data. Write 1 to clear. + RXSTALL: u4, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + /// RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to + /// clear. Note that read-on-empty does not perturb the state of the FIFO in any + /// way, but the data returned by reading from an empty FIFO is undefined, so this + /// flag generally only becomes set due to some kind of software error. + RXUNDER: u4, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to + /// clear. Note that write-on-full does not alter the state or contents of the FIFO + /// in any way, but the data that the system attempted to write is dropped, so if + /// this flag is set, your software has quite likely dropped some data on the floor. + TXOVER: u4, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT + /// with autopull enabled. Write 1 to clear. + TXSTALL: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + }), base_address + 0x8); + + /// address: 0x5030000c + /// FIFO levels + pub const FLEVEL = @intToPtr(*volatile Mmio(32, packed struct { + TX0: u4, + RX0: u4, + TX1: u4, + RX1: u4, + TX2: u4, + RX2: u4, + TX3: u4, + RX3: u4, + }), base_address + 0xc); + + /// address: 0x50300010 + /// Direct write access to the TX FIFO for this state machine. Each write pushes one + /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO + /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + pub const TXF0 = @intToPtr(*volatile u32, base_address + 0x10); + + /// address: 0x50300014 + /// Direct write access to the TX FIFO for this state machine. Each write pushes one + /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO + /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + pub const TXF1 = @intToPtr(*volatile u32, base_address + 0x14); + + /// address: 0x50300018 + /// Direct write access to the TX FIFO for this state machine. Each write pushes one + /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO + /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + pub const TXF2 = @intToPtr(*volatile u32, base_address + 0x18); + + /// address: 0x5030001c + /// Direct write access to the TX FIFO for this state machine. Each write pushes one + /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO + /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO. + pub const TXF3 = @intToPtr(*volatile u32, base_address + 0x1c); + + /// address: 0x50300020 + /// Direct read access to the RX FIFO for this state machine. Each read pops one + /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the + /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The + /// data returned to the system on a read from an empty FIFO is undefined. + pub const RXF0 = @intToPtr(*volatile u32, base_address + 0x20); + + /// address: 0x50300024 + /// Direct read access to the RX FIFO for this state machine. Each read pops one + /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the + /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The + /// data returned to the system on a read from an empty FIFO is undefined. + pub const RXF1 = @intToPtr(*volatile u32, base_address + 0x24); + + /// address: 0x50300028 + /// Direct read access to the RX FIFO for this state machine. Each read pops one + /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the + /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The + /// data returned to the system on a read from an empty FIFO is undefined. + pub const RXF2 = @intToPtr(*volatile u32, base_address + 0x28); + + /// address: 0x5030002c + /// Direct read access to the RX FIFO for this state machine. Each read pops one + /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the + /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The + /// data returned to the system on a read from an empty FIFO is undefined. + pub const RXF3 = @intToPtr(*volatile u32, base_address + 0x2c); + + /// address: 0x50300030 + /// State machine IRQ flags register. Write 1 to clear. There are 8 state machine + /// IRQ flags, which can be set, cleared, and waited on by the state machines. + /// There's no fixed association between flags and state machines -- any state + /// machine can use any flag.\n\n + /// Any of the 8 flags can be used for timing synchronisation between state + /// machines, using IRQ and WAIT instructions. The lower four of these flags are + /// also routed out to system-level interrupt requests, alongside FIFO status + /// interrupts -- see e.g. IRQ0_INTE. + pub const IRQ = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x30); + + /// address: 0x50300034 + /// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. + /// Note this is different to the INTF register: writing here affects PIO internal + /// state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and + /// is not visible to the state machines. + pub const IRQ_FORCE = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x34); + + /// address: 0x50300038 + /// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic + /// from metastabilities. This increases input delay, and for fast synchronous IO + /// (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this + /// register corresponds to one GPIO.\n + /// 0 -> input is synchronized (default)\n + /// 1 -> synchronizer is bypassed\n + /// If in doubt, leave this register as all zeroes. + pub const INPUT_SYNC_BYPASS = @intToPtr(*volatile u32, base_address + 0x38); + + /// address: 0x5030003c + /// Read to sample the pad output values PIO is currently driving to the GPIOs. On + /// RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0. + pub const DBG_PADOUT = @intToPtr(*volatile u32, base_address + 0x3c); + + /// address: 0x50300040 + /// Read to sample the pad output enables (direction) PIO is currently driving to + /// the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are + /// hardwired to 0. + pub const DBG_PADOE = @intToPtr(*volatile u32, base_address + 0x40); + + /// address: 0x50300044 + /// The PIO hardware has some free parameters that may vary between chip products.\n + /// These should be provided in the chip datasheet, but are also exposed here. + pub const DBG_CFGINFO = @intToPtr(*volatile Mmio(32, packed struct { + /// The depth of the state machine TX/RX FIFOs, measured in words.\n + /// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n + /// this depth. + FIFO_DEPTH: u6, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// The number of state machines this PIO instance is equipped with. + SM_COUNT: u4, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// The size of the instruction memory, measured in units of one instruction + IMEM_SIZE: u6, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + }), base_address + 0x44); + + /// address: 0x50300048 + /// Write-only access to instruction memory location 0 + pub const INSTR_MEM0 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x48); + + /// address: 0x5030004c + /// Write-only access to instruction memory location 1 + pub const INSTR_MEM1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x4c); + + /// address: 0x50300050 + /// Write-only access to instruction memory location 2 + pub const INSTR_MEM2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x50); + + /// address: 0x50300054 + /// Write-only access to instruction memory location 3 + pub const INSTR_MEM3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x54); + + /// address: 0x50300058 + /// Write-only access to instruction memory location 4 + pub const INSTR_MEM4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x58); + + /// address: 0x5030005c + /// Write-only access to instruction memory location 5 + pub const INSTR_MEM5 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c); + + /// address: 0x50300060 + /// Write-only access to instruction memory location 6 + pub const INSTR_MEM6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x60); + + /// address: 0x50300064 + /// Write-only access to instruction memory location 7 + pub const INSTR_MEM7 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x64); + + /// address: 0x50300068 + /// Write-only access to instruction memory location 8 + pub const INSTR_MEM8 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x68); + + /// address: 0x5030006c + /// Write-only access to instruction memory location 9 + pub const INSTR_MEM9 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x6c); + + /// address: 0x50300070 + /// Write-only access to instruction memory location 10 + pub const INSTR_MEM10 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x70); + + /// address: 0x50300074 + /// Write-only access to instruction memory location 11 + pub const INSTR_MEM11 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x74); + + /// address: 0x50300078 + /// Write-only access to instruction memory location 12 + pub const INSTR_MEM12 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x78); + + /// address: 0x5030007c + /// Write-only access to instruction memory location 13 + pub const INSTR_MEM13 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x7c); + + /// address: 0x50300080 + /// Write-only access to instruction memory location 14 + pub const INSTR_MEM14 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x80); + + /// address: 0x50300084 + /// Write-only access to instruction memory location 15 + pub const INSTR_MEM15 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x84); + + /// address: 0x50300088 + /// Write-only access to instruction memory location 16 + pub const INSTR_MEM16 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x88); + + /// address: 0x5030008c + /// Write-only access to instruction memory location 17 + pub const INSTR_MEM17 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x8c); + + /// address: 0x50300090 + /// Write-only access to instruction memory location 18 + pub const INSTR_MEM18 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x90); + + /// address: 0x50300094 + /// Write-only access to instruction memory location 19 + pub const INSTR_MEM19 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x94); + + /// address: 0x50300098 + /// Write-only access to instruction memory location 20 + pub const INSTR_MEM20 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x98); + + /// address: 0x5030009c + /// Write-only access to instruction memory location 21 + pub const INSTR_MEM21 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x9c); + + /// address: 0x503000a0 + /// Write-only access to instruction memory location 22 + pub const INSTR_MEM22 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa0); + + /// address: 0x503000a4 + /// Write-only access to instruction memory location 23 + pub const INSTR_MEM23 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa4); + + /// address: 0x503000a8 + /// Write-only access to instruction memory location 24 + pub const INSTR_MEM24 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa8); + + /// address: 0x503000ac + /// Write-only access to instruction memory location 25 + pub const INSTR_MEM25 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xac); + + /// address: 0x503000b0 + /// Write-only access to instruction memory location 26 + pub const INSTR_MEM26 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb0); + + /// address: 0x503000b4 + /// Write-only access to instruction memory location 27 + pub const INSTR_MEM27 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb4); + + /// address: 0x503000b8 + /// Write-only access to instruction memory location 28 + pub const INSTR_MEM28 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb8); + + /// address: 0x503000bc + /// Write-only access to instruction memory location 29 + pub const INSTR_MEM29 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xbc); + + /// address: 0x503000c0 + /// Write-only access to instruction memory location 30 + pub const INSTR_MEM30 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc0); + + /// address: 0x503000c4 + /// Write-only access to instruction memory location 31 + pub const INSTR_MEM31 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc4); + + /// address: 0x503000c8 + /// Clock divisor register for state machine 0\n + /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + pub const SM0_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Fractional part of clock divisor + FRAC: u8, + /// Effective frequency is sysclk/(int + frac/256).\n + /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + INT: u16, + }), base_address + 0xc8); + + /// address: 0x503000cc + /// Execution/behavioural settings for state machine 0 + pub const SM0_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Comparison level for the MOV x, STATUS instruction + STATUS_N: u4, + /// Comparison used for the MOV x, STATUS instruction. + STATUS_SEL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM: u5, + /// After reaching this address, execution is wrapped to wrap_bottom.\n + /// If the instruction is a jump, and the jump condition is true, the jump takes + /// priority. + WRAP_TOP: u5, + /// Continuously assert the most recent OUT/SET to the pins + OUT_STICKY: u1, + /// If 1, use a bit of OUT data as an auxiliary write enable\n + /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + /// deassert the latest pin write. This can create useful masking/override + /// behaviour\n + /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN: u1, + /// Which data bit to use for inline OUT enable + OUT_EN_SEL: u5, + /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN: u5, + /// If 1, side-set data is asserted to pin directions, instead of pin values + SIDE_PINDIR: u1, + /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set + /// enable, rather than a side-set data bit. This allows instructions to perform + /// side-set optionally, rather than on every instruction, but the maximum possible + /// side-set width is reduced from 5 to 4. Note that the value of + /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + SIDE_EN: u1, + /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state + /// machine. Will clear to 0 once this instruction completes. + EXEC_STALLED: u1, + }), base_address + 0xcc); + + /// address: 0x503000d0 + /// Control behaviour of the input/output shift registers for state machine 0 + pub const SM0_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + /// Push automatically when the input shift register is filled, i.e. on an IN + /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + AUTOPUSH: u1, + /// Pull automatically when the output shift register is emptied, i.e. on or + /// following an OUT instruction which causes the output shift counter to reach or + /// exceed PULL_THRESH. + AUTOPULL: u1, + /// 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR: u1, + /// 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR: u1, + /// Number of bits shifted into ISR before autopush, or conditional push (PUSH + /// IFFULL), will take place.\n + /// Write 0 for value of 32. + PUSH_THRESH: u5, + /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL + /// IFEMPTY), will take place.\n + /// Write 0 for value of 32. + PULL_THRESH: u5, + /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + /// RX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_TX: u1, + /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + /// TX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_RX: u1, + }), base_address + 0xd0); + + /// address: 0x503000d4 + /// Current instruction address of state machine 0 + pub const SM0_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd4); + + /// address: 0x503000d8 + /// Read to see the instruction currently addressed by state machine 0's program + /// counter\n + /// Write to execute an instruction immediately (including jumps) and then resume + /// execution. + pub const SM0_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xd8); + + /// address: 0x503000dc + /// State machine pin control + pub const SM0_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV + /// PINS instruction. The data written to this pin will always be the + /// least-significant bit of the OUT or MOV data. + OUT_BASE: u5, + /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS + /// instruction. The data written to this pin is the least-significant bit of the + /// SET data. + SET_BASE: u5, + /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs + /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) + /// are used for side-set data, with the remaining LSBs used for delay. The + /// least-significant bit of the side-set portion is the bit written to this pin, + /// with more-significant bits written to higher-numbered pins. + SIDESET_BASE: u5, + /// The pin which is mapped to the least-significant bit of a state machine's IN + /// data bus. Higher-numbered pins are mapped to consecutively more-significant data + /// bits, with a modulo of 32 applied to pin number. + IN_BASE: u5, + /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. + /// In the range 0 to 32 inclusive. + OUT_COUNT: u6, + /// The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT: u3, + /// The number of MSBs of the Delay/Side-set instruction field which are used for + /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, + /// no side-set) and maximum of 5 (all side-set, no delay). + SIDESET_COUNT: u3, + }), base_address + 0xdc); + + /// address: 0x503000e0 + /// Clock divisor register for state machine 1\n + /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + pub const SM1_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Fractional part of clock divisor + FRAC: u8, + /// Effective frequency is sysclk/(int + frac/256).\n + /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + INT: u16, + }), base_address + 0xe0); + + /// address: 0x503000e4 + /// Execution/behavioural settings for state machine 1 + pub const SM1_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Comparison level for the MOV x, STATUS instruction + STATUS_N: u4, + /// Comparison used for the MOV x, STATUS instruction. + STATUS_SEL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM: u5, + /// After reaching this address, execution is wrapped to wrap_bottom.\n + /// If the instruction is a jump, and the jump condition is true, the jump takes + /// priority. + WRAP_TOP: u5, + /// Continuously assert the most recent OUT/SET to the pins + OUT_STICKY: u1, + /// If 1, use a bit of OUT data as an auxiliary write enable\n + /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + /// deassert the latest pin write. This can create useful masking/override + /// behaviour\n + /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN: u1, + /// Which data bit to use for inline OUT enable + OUT_EN_SEL: u5, + /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN: u5, + /// If 1, side-set data is asserted to pin directions, instead of pin values + SIDE_PINDIR: u1, + /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set + /// enable, rather than a side-set data bit. This allows instructions to perform + /// side-set optionally, rather than on every instruction, but the maximum possible + /// side-set width is reduced from 5 to 4. Note that the value of + /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + SIDE_EN: u1, + /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state + /// machine. Will clear to 0 once this instruction completes. + EXEC_STALLED: u1, + }), base_address + 0xe4); + + /// address: 0x503000e8 + /// Control behaviour of the input/output shift registers for state machine 1 + pub const SM1_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + /// Push automatically when the input shift register is filled, i.e. on an IN + /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + AUTOPUSH: u1, + /// Pull automatically when the output shift register is emptied, i.e. on or + /// following an OUT instruction which causes the output shift counter to reach or + /// exceed PULL_THRESH. + AUTOPULL: u1, + /// 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR: u1, + /// 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR: u1, + /// Number of bits shifted into ISR before autopush, or conditional push (PUSH + /// IFFULL), will take place.\n + /// Write 0 for value of 32. + PUSH_THRESH: u5, + /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL + /// IFEMPTY), will take place.\n + /// Write 0 for value of 32. + PULL_THRESH: u5, + /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + /// RX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_TX: u1, + /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + /// TX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_RX: u1, + }), base_address + 0xe8); + + /// address: 0x503000ec + /// Current instruction address of state machine 1 + pub const SM1_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xec); + + /// address: 0x503000f0 + /// Read to see the instruction currently addressed by state machine 1's program + /// counter\n + /// Write to execute an instruction immediately (including jumps) and then resume + /// execution. + pub const SM1_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xf0); + + /// address: 0x503000f4 + /// State machine pin control + pub const SM1_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV + /// PINS instruction. The data written to this pin will always be the + /// least-significant bit of the OUT or MOV data. + OUT_BASE: u5, + /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS + /// instruction. The data written to this pin is the least-significant bit of the + /// SET data. + SET_BASE: u5, + /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs + /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) + /// are used for side-set data, with the remaining LSBs used for delay. The + /// least-significant bit of the side-set portion is the bit written to this pin, + /// with more-significant bits written to higher-numbered pins. + SIDESET_BASE: u5, + /// The pin which is mapped to the least-significant bit of a state machine's IN + /// data bus. Higher-numbered pins are mapped to consecutively more-significant data + /// bits, with a modulo of 32 applied to pin number. + IN_BASE: u5, + /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. + /// In the range 0 to 32 inclusive. + OUT_COUNT: u6, + /// The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT: u3, + /// The number of MSBs of the Delay/Side-set instruction field which are used for + /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, + /// no side-set) and maximum of 5 (all side-set, no delay). + SIDESET_COUNT: u3, + }), base_address + 0xf4); + + /// address: 0x503000f8 + /// Clock divisor register for state machine 2\n + /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + pub const SM2_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Fractional part of clock divisor + FRAC: u8, + /// Effective frequency is sysclk/(int + frac/256).\n + /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + INT: u16, + }), base_address + 0xf8); + + /// address: 0x503000fc + /// Execution/behavioural settings for state machine 2 + pub const SM2_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Comparison level for the MOV x, STATUS instruction + STATUS_N: u4, + /// Comparison used for the MOV x, STATUS instruction. + STATUS_SEL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM: u5, + /// After reaching this address, execution is wrapped to wrap_bottom.\n + /// If the instruction is a jump, and the jump condition is true, the jump takes + /// priority. + WRAP_TOP: u5, + /// Continuously assert the most recent OUT/SET to the pins + OUT_STICKY: u1, + /// If 1, use a bit of OUT data as an auxiliary write enable\n + /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + /// deassert the latest pin write. This can create useful masking/override + /// behaviour\n + /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN: u1, + /// Which data bit to use for inline OUT enable + OUT_EN_SEL: u5, + /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN: u5, + /// If 1, side-set data is asserted to pin directions, instead of pin values + SIDE_PINDIR: u1, + /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set + /// enable, rather than a side-set data bit. This allows instructions to perform + /// side-set optionally, rather than on every instruction, but the maximum possible + /// side-set width is reduced from 5 to 4. Note that the value of + /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + SIDE_EN: u1, + /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state + /// machine. Will clear to 0 once this instruction completes. + EXEC_STALLED: u1, + }), base_address + 0xfc); + + /// address: 0x50300100 + /// Control behaviour of the input/output shift registers for state machine 2 + pub const SM2_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + /// Push automatically when the input shift register is filled, i.e. on an IN + /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + AUTOPUSH: u1, + /// Pull automatically when the output shift register is emptied, i.e. on or + /// following an OUT instruction which causes the output shift counter to reach or + /// exceed PULL_THRESH. + AUTOPULL: u1, + /// 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR: u1, + /// 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR: u1, + /// Number of bits shifted into ISR before autopush, or conditional push (PUSH + /// IFFULL), will take place.\n + /// Write 0 for value of 32. + PUSH_THRESH: u5, + /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL + /// IFEMPTY), will take place.\n + /// Write 0 for value of 32. + PULL_THRESH: u5, + /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + /// RX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_TX: u1, + /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + /// TX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_RX: u1, + }), base_address + 0x100); + + /// address: 0x50300104 + /// Current instruction address of state machine 2 + pub const SM2_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x104); + + /// address: 0x50300108 + /// Read to see the instruction currently addressed by state machine 2's program + /// counter\n + /// Write to execute an instruction immediately (including jumps) and then resume + /// execution. + pub const SM2_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x108); + + /// address: 0x5030010c + /// State machine pin control + pub const SM2_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV + /// PINS instruction. The data written to this pin will always be the + /// least-significant bit of the OUT or MOV data. + OUT_BASE: u5, + /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS + /// instruction. The data written to this pin is the least-significant bit of the + /// SET data. + SET_BASE: u5, + /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs + /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) + /// are used for side-set data, with the remaining LSBs used for delay. The + /// least-significant bit of the side-set portion is the bit written to this pin, + /// with more-significant bits written to higher-numbered pins. + SIDESET_BASE: u5, + /// The pin which is mapped to the least-significant bit of a state machine's IN + /// data bus. Higher-numbered pins are mapped to consecutively more-significant data + /// bits, with a modulo of 32 applied to pin number. + IN_BASE: u5, + /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. + /// In the range 0 to 32 inclusive. + OUT_COUNT: u6, + /// The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT: u3, + /// The number of MSBs of the Delay/Side-set instruction field which are used for + /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, + /// no side-set) and maximum of 5 (all side-set, no delay). + SIDESET_COUNT: u3, + }), base_address + 0x10c); + + /// address: 0x50300110 + /// Clock divisor register for state machine 3\n + /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256) + pub const SM3_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Fractional part of clock divisor + FRAC: u8, + /// Effective frequency is sysclk/(int + frac/256).\n + /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0. + INT: u16, + }), base_address + 0x110); + + /// address: 0x50300114 + /// Execution/behavioural settings for state machine 3 + pub const SM3_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Comparison level for the MOV x, STATUS instruction + STATUS_N: u4, + /// Comparison used for the MOV x, STATUS instruction. + STATUS_SEL: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// After reaching wrap_top, execution is wrapped to this address. + WRAP_BOTTOM: u5, + /// After reaching this address, execution is wrapped to wrap_bottom.\n + /// If the instruction is a jump, and the jump condition is true, the jump takes + /// priority. + WRAP_TOP: u5, + /// Continuously assert the most recent OUT/SET to the pins + OUT_STICKY: u1, + /// If 1, use a bit of OUT data as an auxiliary write enable\n + /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n + /// deassert the latest pin write. This can create useful masking/override + /// behaviour\n + /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...) + INLINE_OUT_EN: u1, + /// Which data bit to use for inline OUT enable + OUT_EN_SEL: u5, + /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping. + JMP_PIN: u5, + /// If 1, side-set data is asserted to pin directions, instead of pin values + SIDE_PINDIR: u1, + /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set + /// enable, rather than a side-set data bit. This allows instructions to perform + /// side-set optionally, rather than on every instruction, but the maximum possible + /// side-set width is reduced from 5 to 4. Note that the value of + /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit. + SIDE_EN: u1, + /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state + /// machine. Will clear to 0 once this instruction completes. + EXEC_STALLED: u1, + }), base_address + 0x114); + + /// address: 0x50300118 + /// Control behaviour of the input/output shift registers for state machine 3 + pub const SM3_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + /// Push automatically when the input shift register is filled, i.e. on an IN + /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH. + AUTOPUSH: u1, + /// Pull automatically when the output shift register is emptied, i.e. on or + /// following an OUT instruction which causes the output shift counter to reach or + /// exceed PULL_THRESH. + AUTOPULL: u1, + /// 1 = shift input shift register to right (data enters from left). 0 = to left. + IN_SHIFTDIR: u1, + /// 1 = shift out of output shift register to right. 0 = to left. + OUT_SHIFTDIR: u1, + /// Number of bits shifted into ISR before autopush, or conditional push (PUSH + /// IFFULL), will take place.\n + /// Write 0 for value of 32. + PUSH_THRESH: u5, + /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL + /// IFEMPTY), will take place.\n + /// Write 0 for value of 32. + PULL_THRESH: u5, + /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n + /// RX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_TX: u1, + /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n + /// TX FIFO is disabled as a result (always reads as both full and empty).\n + /// FIFOs are flushed when this bit is changed. + FJOIN_RX: u1, + }), base_address + 0x118); + + /// address: 0x5030011c + /// Current instruction address of state machine 3 + pub const SM3_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x11c); + + /// address: 0x50300120 + /// Read to see the instruction currently addressed by state machine 3's program + /// counter\n + /// Write to execute an instruction immediately (including jumps) and then resume + /// execution. + pub const SM3_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x120); + + /// address: 0x50300124 + /// State machine pin control + pub const SM3_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV + /// PINS instruction. The data written to this pin will always be the + /// least-significant bit of the OUT or MOV data. + OUT_BASE: u5, + /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS + /// instruction. The data written to this pin is the least-significant bit of the + /// SET data. + SET_BASE: u5, + /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs + /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) + /// are used for side-set data, with the remaining LSBs used for delay. The + /// least-significant bit of the side-set portion is the bit written to this pin, + /// with more-significant bits written to higher-numbered pins. + SIDESET_BASE: u5, + /// The pin which is mapped to the least-significant bit of a state machine's IN + /// data bus. Higher-numbered pins are mapped to consecutively more-significant data + /// bits, with a modulo of 32 applied to pin number. + IN_BASE: u5, + /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. + /// In the range 0 to 32 inclusive. + OUT_COUNT: u6, + /// The number of pins asserted by a SET. In the range 0 to 5 inclusive. + SET_COUNT: u3, + /// The number of MSBs of the Delay/Side-set instruction field which are used for + /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, + /// no side-set) and maximum of 5 (all side-set, no delay). + SIDESET_COUNT: u3, + }), base_address + 0x124); + + /// address: 0x50300128 + /// Raw Interrupts + pub const INTR = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x128); + + /// address: 0x5030012c + /// Interrupt Enable for irq0 + pub const IRQ0_INTE = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x12c); + + /// address: 0x50300130 + /// Interrupt Force for irq0 + pub const IRQ0_INTF = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x130); + + /// address: 0x50300134 + /// Interrupt status after masking & forcing for irq0 + pub const IRQ0_INTS = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x134); + + /// address: 0x50300138 + /// Interrupt Enable for irq1 + pub const IRQ1_INTE = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x138); + + /// address: 0x5030013c + /// Interrupt Force for irq1 + pub const IRQ1_INTF = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x13c); + + /// address: 0x50300140 + /// Interrupt status after masking & forcing for irq1 + pub const IRQ1_INTS = @intToPtr(*volatile Mmio(32, packed struct { + SM0_RXNEMPTY: u1, + SM1_RXNEMPTY: u1, + SM2_RXNEMPTY: u1, + SM3_RXNEMPTY: u1, + SM0_TXNFULL: u1, + SM1_TXNFULL: u1, + SM2_TXNFULL: u1, + SM3_TXNFULL: u1, + SM0: u1, + SM1: u1, + SM2: u1, + SM3: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + }), base_address + 0x140); + }; + + /// Single-cycle IO block\n + /// Provides core-local and inter-core hardware for the two processors, with + /// single-cycle access. + pub const SIO = struct { + pub const base_address = 0xd0000000; + pub const version = "1"; + + /// address: 0xd0000000 + /// Processor core identifier\n + /// Value is 0 when read from processor core 0, and 1 when read from processor core + /// 1. + pub const CPUID = @intToPtr(*volatile u32, base_address + 0x0); + + /// address: 0xd0000004 + /// Input value for GPIO pins + pub const GPIO_IN = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x4); + + /// address: 0xd0000008 + /// Input value for QSPI pins + pub const GPIO_HI_IN = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x8); + + /// address: 0xd0000010 + /// GPIO output value + pub const GPIO_OUT = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x10); + + /// address: 0xd0000014 + /// GPIO output value set + pub const GPIO_OUT_SET = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x14); + + /// address: 0xd0000018 + /// GPIO output value clear + pub const GPIO_OUT_CLR = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x18); + + /// address: 0xd000001c + /// GPIO output value XOR + pub const GPIO_OUT_XOR = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x1c); + + /// address: 0xd0000020 + /// GPIO output enable + pub const GPIO_OE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x20); + + /// address: 0xd0000024 + /// GPIO output enable set + pub const GPIO_OE_SET = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x24); + + /// address: 0xd0000028 + /// GPIO output enable clear + pub const GPIO_OE_CLR = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x28); + + /// address: 0xd000002c + /// GPIO output enable XOR + pub const GPIO_OE_XOR = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x2c); + + /// address: 0xd0000030 + /// QSPI output value + pub const GPIO_HI_OUT = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x30); + + /// address: 0xd0000034 + /// QSPI output value set + pub const GPIO_HI_OUT_SET = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x34); + + /// address: 0xd0000038 + /// QSPI output value clear + pub const GPIO_HI_OUT_CLR = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x38); + + /// address: 0xd000003c + /// QSPI output value XOR + pub const GPIO_HI_OUT_XOR = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x3c); + + /// address: 0xd0000040 + /// QSPI output enable + pub const GPIO_HI_OE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x40); + + /// address: 0xd0000044 + /// QSPI output enable set + pub const GPIO_HI_OE_SET = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x44); + + /// address: 0xd0000048 + /// QSPI output enable clear + pub const GPIO_HI_OE_CLR = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x48); + + /// address: 0xd000004c + /// QSPI output enable XOR + pub const GPIO_HI_OE_XOR = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x4c); + + /// address: 0xd0000050 + /// Status register for inter-core FIFOs (mailboxes).\n + /// There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. + /// Both are 32 bits wide and 8 words deep.\n + /// Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 + /// FIFO (TX).\n + /// Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 + /// FIFO (TX).\n + /// The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of + /// its FIFO_ST register. + pub const FIFO_ST = @intToPtr(*volatile Mmio(32, packed struct { + /// Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid) + VLD: u1, + /// Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more + /// data) + RDY: u1, + /// Sticky flag indicating the TX FIFO was written when full. This write was ignored + /// by the FIFO. + WOF: u1, + /// Sticky flag indicating the RX FIFO was read when empty. This read was ignored by + /// the FIFO. + ROE: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0x50); + + /// address: 0xd0000054 + /// Write access to this core's TX FIFO + pub const FIFO_WR = @intToPtr(*volatile u32, base_address + 0x54); + + /// address: 0xd0000058 + /// Read access to this core's RX FIFO + pub const FIFO_RD = @intToPtr(*volatile u32, base_address + 0x58); + + /// address: 0xd000005c + /// Spinlock state\n + /// A bitmap containing the state of all 32 spinlocks (1=locked).\n + /// Mainly intended for debugging. + pub const SPINLOCK_ST = @intToPtr(*volatile u32, base_address + 0x5c); + + /// address: 0xd0000060 + /// Divider unsigned dividend\n + /// Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\n + /// Any operand write starts a new calculation. The results appear in QUOTIENT, + /// REMAINDER.\n + /// UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias + /// starts an\n + /// unsigned calculation, and the S alias starts a signed calculation. + pub const DIV_UDIVIDEND = @intToPtr(*volatile u32, base_address + 0x60); + + /// address: 0xd0000064 + /// Divider unsigned divisor\n + /// Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\n + /// Any operand write starts a new calculation. The results appear in QUOTIENT, + /// REMAINDER.\n + /// UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias + /// starts an\n + /// unsigned calculation, and the S alias starts a signed calculation. + pub const DIV_UDIVISOR = @intToPtr(*volatile u32, base_address + 0x64); + + /// address: 0xd0000068 + /// Divider signed dividend\n + /// The same as UDIVIDEND, but starts a signed calculation, rather than unsigned. + pub const DIV_SDIVIDEND = @intToPtr(*volatile u32, base_address + 0x68); + + /// address: 0xd000006c + /// Divider signed divisor\n + /// The same as UDIVISOR, but starts a signed calculation, rather than unsigned. + pub const DIV_SDIVISOR = @intToPtr(*volatile u32, base_address + 0x6c); + + /// address: 0xd0000070 + /// Divider result quotient\n + /// The result of `DIVIDEND / DIVISOR` (division). Contents undefined while + /// CSR_READY is low.\n + /// For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and + /// DIVISOR differ.\n + /// This register can be written to directly, for context save/restore purposes. + /// This halts any\n + /// in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n + /// Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the + /// order\n + /// REMAINDER, QUOTIENT if CSR_DIRTY is used. + pub const DIV_QUOTIENT = @intToPtr(*volatile u32, base_address + 0x70); + + /// address: 0xd0000074 + /// Divider result remainder\n + /// The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY + /// is low.\n + /// For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n + /// This register can be written to directly, for context save/restore purposes. + /// This halts any\n + /// in-progress calculation and sets the CSR_READY and CSR_DIRTY flags. + pub const DIV_REMAINDER = @intToPtr(*volatile u32, base_address + 0x74); + + /// address: 0xd0000078 + /// Control and status register for divider. + pub const DIV_CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reads as 0 when a calculation is in progress, 1 otherwise.\n + /// Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new + /// calculation, no\n + /// matter if one is already in progress.\n + /// Writing to a result register will immediately terminate any in-progress + /// calculation\n + /// and set the READY and DIRTY flags. + READY: u1, + /// Changes to 1 when any register is written, and back to 0 when QUOTIENT is + /// read.\n + /// Software can use this flag to make save/restore more efficient (skip if not + /// DIRTY).\n + /// If the flag is used in this way, it's recommended to either read QUOTIENT + /// only,\n + /// or REMAINDER and then QUOTIENT, to prevent data loss on context switch. + DIRTY: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + padding29: u1 = 0, + }), base_address + 0x78); + + /// address: 0xd0000080 + /// Read/write access to accumulator 0 + pub const INTERP0_ACCUM0 = @intToPtr(*volatile u32, base_address + 0x80); + + /// address: 0xd0000084 + /// Read/write access to accumulator 1 + pub const INTERP0_ACCUM1 = @intToPtr(*volatile u32, base_address + 0x84); + + /// address: 0xd0000088 + /// Read/write access to BASE0 register. + pub const INTERP0_BASE0 = @intToPtr(*volatile u32, base_address + 0x88); + + /// address: 0xd000008c + /// Read/write access to BASE1 register. + pub const INTERP0_BASE1 = @intToPtr(*volatile u32, base_address + 0x8c); + + /// address: 0xd0000090 + /// Read/write access to BASE2 register. + pub const INTERP0_BASE2 = @intToPtr(*volatile u32, base_address + 0x90); + + /// address: 0xd0000094 + /// Read LANE0 result, and simultaneously write lane results to both accumulators + /// (POP). + pub const INTERP0_POP_LANE0 = @intToPtr(*volatile u32, base_address + 0x94); + + /// address: 0xd0000098 + /// Read LANE1 result, and simultaneously write lane results to both accumulators + /// (POP). + pub const INTERP0_POP_LANE1 = @intToPtr(*volatile u32, base_address + 0x98); + + /// address: 0xd000009c + /// Read FULL result, and simultaneously write lane results to both accumulators + /// (POP). + pub const INTERP0_POP_FULL = @intToPtr(*volatile u32, base_address + 0x9c); + + /// address: 0xd00000a0 + /// Read LANE0 result, without altering any internal state (PEEK). + pub const INTERP0_PEEK_LANE0 = @intToPtr(*volatile u32, base_address + 0xa0); + + /// address: 0xd00000a4 + /// Read LANE1 result, without altering any internal state (PEEK). + pub const INTERP0_PEEK_LANE1 = @intToPtr(*volatile u32, base_address + 0xa4); + + /// address: 0xd00000a8 + /// Read FULL result, without altering any internal state (PEEK). + pub const INTERP0_PEEK_FULL = @intToPtr(*volatile u32, base_address + 0xa8); + + /// address: 0xd00000ac + /// Control register for lane 0 + pub const INTERP0_CTRL_LANE0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Logical right-shift applied to accumulator before masking + SHIFT: u5, + /// The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB: u5, + /// The most-significant bit allowed to pass by the mask (inclusive)\n + /// Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB: u5, + /// If SIGNED is set, the shifted and masked accumulator value is sign-extended to + /// 32 bits\n + /// before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read + /// by processor. + SIGNED: u1, + /// If 1, feed the opposite lane's accumulator into this lane's shift + mask + /// hardware.\n + /// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the + /// shift+mask bypass) + CROSS_INPUT: u1, + /// If 1, feed the opposite lane's result into this lane's accumulator on POP. + CROSS_RESULT: u1, + /// If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL + /// result. + ADD_RAW: u1, + /// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + /// No effect on the internal 32-bit datapath. Handy for using a lane to generate + /// sequence\n + /// of pointers into flash or SRAM. + FORCE_MSB: u2, + /// Only present on INTERP0 on each core. If BLEND mode is enabled:\n + /// - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n + /// by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n + /// 0 and 255/256ths)\n + /// - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 + /// shift+mask value)\n + /// - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 + /// shift+mask)\n + /// LANE1 SIGNED flag controls whether the interpolation is signed or unsigned. + BLEND: u1, + reserved0: u1 = 0, + /// Indicates if any masked-off MSBs in ACCUM0 are set. + OVERF0: u1, + /// Indicates if any masked-off MSBs in ACCUM1 are set. + OVERF1: u1, + /// Set if either OVERF0 or OVERF1 is set. + OVERF: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + }), base_address + 0xac); + + /// address: 0xd00000b0 + /// Control register for lane 1 + pub const INTERP0_CTRL_LANE1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Logical right-shift applied to accumulator before masking + SHIFT: u5, + /// The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB: u5, + /// The most-significant bit allowed to pass by the mask (inclusive)\n + /// Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB: u5, + /// If SIGNED is set, the shifted and masked accumulator value is sign-extended to + /// 32 bits\n + /// before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read + /// by processor. + SIGNED: u1, + /// If 1, feed the opposite lane's accumulator into this lane's shift + mask + /// hardware.\n + /// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the + /// shift+mask bypass) + CROSS_INPUT: u1, + /// If 1, feed the opposite lane's result into this lane's accumulator on POP. + CROSS_RESULT: u1, + /// If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL + /// result. + ADD_RAW: u1, + /// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + /// No effect on the internal 32-bit datapath. Handy for using a lane to generate + /// sequence\n + /// of pointers into flash or SRAM. + FORCE_MSB: u2, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + }), base_address + 0xb0); + + /// address: 0xd00000b4 + /// Values written here are atomically added to ACCUM0\n + /// Reading yields lane 0's raw shift and mask value (BASE0 not added). + pub const INTERP0_ACCUM0_ADD = @intToPtr(*volatile MmioInt(32, u24), base_address + 0xb4); + + /// address: 0xd00000b8 + /// Values written here are atomically added to ACCUM1\n + /// Reading yields lane 1's raw shift and mask value (BASE1 not added). + pub const INTERP0_ACCUM1_ADD = @intToPtr(*volatile MmioInt(32, u24), base_address + 0xb8); + + /// address: 0xd00000bc + /// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n + /// Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + pub const INTERP0_BASE_1AND0 = @intToPtr(*volatile u32, base_address + 0xbc); + + /// address: 0xd00000c0 + /// Read/write access to accumulator 0 + pub const INTERP1_ACCUM0 = @intToPtr(*volatile u32, base_address + 0xc0); + + /// address: 0xd00000c4 + /// Read/write access to accumulator 1 + pub const INTERP1_ACCUM1 = @intToPtr(*volatile u32, base_address + 0xc4); + + /// address: 0xd00000c8 + /// Read/write access to BASE0 register. + pub const INTERP1_BASE0 = @intToPtr(*volatile u32, base_address + 0xc8); + + /// address: 0xd00000cc + /// Read/write access to BASE1 register. + pub const INTERP1_BASE1 = @intToPtr(*volatile u32, base_address + 0xcc); + + /// address: 0xd00000d0 + /// Read/write access to BASE2 register. + pub const INTERP1_BASE2 = @intToPtr(*volatile u32, base_address + 0xd0); + + /// address: 0xd00000d4 + /// Read LANE0 result, and simultaneously write lane results to both accumulators + /// (POP). + pub const INTERP1_POP_LANE0 = @intToPtr(*volatile u32, base_address + 0xd4); + + /// address: 0xd00000d8 + /// Read LANE1 result, and simultaneously write lane results to both accumulators + /// (POP). + pub const INTERP1_POP_LANE1 = @intToPtr(*volatile u32, base_address + 0xd8); + + /// address: 0xd00000dc + /// Read FULL result, and simultaneously write lane results to both accumulators + /// (POP). + pub const INTERP1_POP_FULL = @intToPtr(*volatile u32, base_address + 0xdc); + + /// address: 0xd00000e0 + /// Read LANE0 result, without altering any internal state (PEEK). + pub const INTERP1_PEEK_LANE0 = @intToPtr(*volatile u32, base_address + 0xe0); + + /// address: 0xd00000e4 + /// Read LANE1 result, without altering any internal state (PEEK). + pub const INTERP1_PEEK_LANE1 = @intToPtr(*volatile u32, base_address + 0xe4); + + /// address: 0xd00000e8 + /// Read FULL result, without altering any internal state (PEEK). + pub const INTERP1_PEEK_FULL = @intToPtr(*volatile u32, base_address + 0xe8); + + /// address: 0xd00000ec + /// Control register for lane 0 + pub const INTERP1_CTRL_LANE0 = @intToPtr(*volatile Mmio(32, packed struct { + /// Logical right-shift applied to accumulator before masking + SHIFT: u5, + /// The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB: u5, + /// The most-significant bit allowed to pass by the mask (inclusive)\n + /// Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB: u5, + /// If SIGNED is set, the shifted and masked accumulator value is sign-extended to + /// 32 bits\n + /// before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read + /// by processor. + SIGNED: u1, + /// If 1, feed the opposite lane's accumulator into this lane's shift + mask + /// hardware.\n + /// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the + /// shift+mask bypass) + CROSS_INPUT: u1, + /// If 1, feed the opposite lane's result into this lane's accumulator on POP. + CROSS_RESULT: u1, + /// If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL + /// result. + ADD_RAW: u1, + /// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + /// No effect on the internal 32-bit datapath. Handy for using a lane to generate + /// sequence\n + /// of pointers into flash or SRAM. + FORCE_MSB: u2, + reserved0: u1 = 0, + /// Only present on INTERP1 on each core. If CLAMP mode is enabled:\n + /// - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n + /// BASE0 and an upper bound of BASE1.\n + /// - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED + CLAMP: u1, + /// Indicates if any masked-off MSBs in ACCUM0 are set. + OVERF0: u1, + /// Indicates if any masked-off MSBs in ACCUM1 are set. + OVERF1: u1, + /// Set if either OVERF0 or OVERF1 is set. + OVERF: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + }), base_address + 0xec); + + /// address: 0xd00000f0 + /// Control register for lane 1 + pub const INTERP1_CTRL_LANE1 = @intToPtr(*volatile Mmio(32, packed struct { + /// Logical right-shift applied to accumulator before masking + SHIFT: u5, + /// The least-significant bit allowed to pass by the mask (inclusive) + MASK_LSB: u5, + /// The most-significant bit allowed to pass by the mask (inclusive)\n + /// Setting MSB < LSB may cause chip to turn inside-out + MASK_MSB: u5, + /// If SIGNED is set, the shifted and masked accumulator value is sign-extended to + /// 32 bits\n + /// before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read + /// by processor. + SIGNED: u1, + /// If 1, feed the opposite lane's accumulator into this lane's shift + mask + /// hardware.\n + /// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the + /// shift+mask bypass) + CROSS_INPUT: u1, + /// If 1, feed the opposite lane's result into this lane's accumulator on POP. + CROSS_RESULT: u1, + /// If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL + /// result. + ADD_RAW: u1, + /// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n + /// No effect on the internal 32-bit datapath. Handy for using a lane to generate + /// sequence\n + /// of pointers into flash or SRAM. + FORCE_MSB: u2, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + }), base_address + 0xf0); + + /// address: 0xd00000f4 + /// Values written here are atomically added to ACCUM0\n + /// Reading yields lane 0's raw shift and mask value (BASE0 not added). + pub const INTERP1_ACCUM0_ADD = @intToPtr(*volatile MmioInt(32, u24), base_address + 0xf4); + + /// address: 0xd00000f8 + /// Values written here are atomically added to ACCUM1\n + /// Reading yields lane 1's raw shift and mask value (BASE1 not added). + pub const INTERP1_ACCUM1_ADD = @intToPtr(*volatile MmioInt(32, u24), base_address + 0xf8); + + /// address: 0xd00000fc + /// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n + /// Each half is sign-extended to 32 bits if that lane's SIGNED flag is set. + pub const INTERP1_BASE_1AND0 = @intToPtr(*volatile u32, base_address + 0xfc); + + /// address: 0xd0000100 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK0 = @intToPtr(*volatile u32, base_address + 0x100); + + /// address: 0xd0000104 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK1 = @intToPtr(*volatile u32, base_address + 0x104); + + /// address: 0xd0000108 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK2 = @intToPtr(*volatile u32, base_address + 0x108); + + /// address: 0xd000010c + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK3 = @intToPtr(*volatile u32, base_address + 0x10c); + + /// address: 0xd0000110 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK4 = @intToPtr(*volatile u32, base_address + 0x110); + + /// address: 0xd0000114 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK5 = @intToPtr(*volatile u32, base_address + 0x114); + + /// address: 0xd0000118 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK6 = @intToPtr(*volatile u32, base_address + 0x118); + + /// address: 0xd000011c + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK7 = @intToPtr(*volatile u32, base_address + 0x11c); + + /// address: 0xd0000120 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK8 = @intToPtr(*volatile u32, base_address + 0x120); + + /// address: 0xd0000124 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK9 = @intToPtr(*volatile u32, base_address + 0x124); + + /// address: 0xd0000128 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK10 = @intToPtr(*volatile u32, base_address + 0x128); + + /// address: 0xd000012c + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK11 = @intToPtr(*volatile u32, base_address + 0x12c); + + /// address: 0xd0000130 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK12 = @intToPtr(*volatile u32, base_address + 0x130); + + /// address: 0xd0000134 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK13 = @intToPtr(*volatile u32, base_address + 0x134); + + /// address: 0xd0000138 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK14 = @intToPtr(*volatile u32, base_address + 0x138); + + /// address: 0xd000013c + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK15 = @intToPtr(*volatile u32, base_address + 0x13c); + + /// address: 0xd0000140 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK16 = @intToPtr(*volatile u32, base_address + 0x140); + + /// address: 0xd0000144 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK17 = @intToPtr(*volatile u32, base_address + 0x144); + + /// address: 0xd0000148 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK18 = @intToPtr(*volatile u32, base_address + 0x148); + + /// address: 0xd000014c + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK19 = @intToPtr(*volatile u32, base_address + 0x14c); + + /// address: 0xd0000150 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK20 = @intToPtr(*volatile u32, base_address + 0x150); + + /// address: 0xd0000154 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK21 = @intToPtr(*volatile u32, base_address + 0x154); + + /// address: 0xd0000158 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK22 = @intToPtr(*volatile u32, base_address + 0x158); + + /// address: 0xd000015c + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK23 = @intToPtr(*volatile u32, base_address + 0x15c); + + /// address: 0xd0000160 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK24 = @intToPtr(*volatile u32, base_address + 0x160); + + /// address: 0xd0000164 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK25 = @intToPtr(*volatile u32, base_address + 0x164); + + /// address: 0xd0000168 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK26 = @intToPtr(*volatile u32, base_address + 0x168); + + /// address: 0xd000016c + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK27 = @intToPtr(*volatile u32, base_address + 0x16c); + + /// address: 0xd0000170 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK28 = @intToPtr(*volatile u32, base_address + 0x170); + + /// address: 0xd0000174 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK29 = @intToPtr(*volatile u32, base_address + 0x174); + + /// address: 0xd0000178 + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK30 = @intToPtr(*volatile u32, base_address + 0x178); + + /// address: 0xd000017c + /// Reading from a spinlock address will:\n + /// - Return 0 if lock is already locked\n + /// - Otherwise return nonzero, and simultaneously claim the lock\n\n + /// Writing (any value) releases the lock.\n + /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 + /// wins.\n + /// The value returned on success is 0x1 << lock number. + pub const SPINLOCK31 = @intToPtr(*volatile u32, base_address + 0x17c); + }; + pub const PPB = struct { + pub const base_address = 0xe0000000; + pub const version = "1"; + + /// address: 0xe000e010 + /// Use the SysTick Control and Status Register to enable the SysTick features. + pub const SYST_CSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enable SysTick counter:\n + /// 0 = Counter disabled.\n + /// 1 = Counter enabled. + ENABLE: u1, + /// Enables SysTick exception request:\n + /// 0 = Counting down to zero does not assert the SysTick exception request.\n + /// 1 = Counting down to zero to asserts the SysTick exception request. + TICKINT: u1, + /// SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n + /// Selects the SysTick timer clock source:\n + /// 0 = External reference clock.\n + /// 1 = Processor clock. + CLKSOURCE: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// Returns 1 if timer counted to 0 since last time this was read. Clears on read by + /// application or debugger. + COUNTFLAG: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + }), base_address + 0xe010); + + /// address: 0xe000e014 + /// Use the SysTick Reload Value Register to specify the start value to load into + /// the current value register when the counter reaches 0. It can be any value + /// between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect + /// because the SysTick interrupt and COUNTFLAG are activated when counting from 1 + /// to 0. The reset value of this register is UNKNOWN.\n + /// To generate a multi-shot timer with a period of N processor clock cycles, use a + /// RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 + /// clock pulses, set RELOAD to 99. + pub const SYST_RVR = @intToPtr(*volatile Mmio(32, packed struct { + /// Value to load into the SysTick Current Value Register when the counter reaches + /// 0. + RELOAD: u24, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0xe014); + + /// address: 0xe000e018 + /// Use the SysTick Current Value Register to find the current value in the + /// register. The reset value of this register is UNKNOWN. + pub const SYST_CVR = @intToPtr(*volatile Mmio(32, packed struct { + /// Reads return the current value of the SysTick counter. This register is + /// write-clear. Writing to it with any value clears the register to 0. Clearing + /// this register also clears the COUNTFLAG bit of the SysTick Control and Status + /// Register. + CURRENT: u24, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0xe018); + + /// address: 0xe000e01c + /// Use the SysTick Calibration Value Register to enable software to scale to any + /// required speed using divide and multiply. + pub const SYST_CALIB = @intToPtr(*volatile Mmio(32, packed struct { + /// An optional Reload value to be used for 10ms (100Hz) timing, subject to system + /// clock skew errors. If the value reads as 0, the calibration value is not known. + TENMS: u24, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// If reads as 1, the calibration value for 10ms is inexact (due to clock + /// frequency). + SKEW: u1, + /// If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the + /// SysTick Control and Status register will be forced to 1 and cannot be cleared to + /// 0. + NOREF: u1, + }), base_address + 0xe01c); + + /// address: 0xe000e100 + /// Use the Interrupt Set-Enable Register to enable interrupts and determine which + /// interrupts are currently enabled.\n + /// If a pending interrupt is enabled, the NVIC activates the interrupt based on its + /// priority. If an interrupt is not enabled, asserting its interrupt signal changes + /// the interrupt state to pending, but the NVIC never activates the interrupt, + /// regardless of its priority. + pub const NVIC_ISER = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt set-enable bits.\n + /// Write:\n + /// 0 = No effect.\n + /// 1 = Enable interrupt.\n + /// Read:\n + /// 0 = Interrupt disabled.\n + /// 1 = Interrupt enabled. + SETENA: u32, + }), base_address + 0xe100); + + /// address: 0xe000e180 + /// Use the Interrupt Clear-Enable Registers to disable interrupts and determine + /// which interrupts are currently enabled. + pub const NVIC_ICER = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt clear-enable bits.\n + /// Write:\n + /// 0 = No effect.\n + /// 1 = Disable interrupt.\n + /// Read:\n + /// 0 = Interrupt disabled.\n + /// 1 = Interrupt enabled. + CLRENA: u32, + }), base_address + 0xe180); + + /// address: 0xe000e200 + /// The NVIC_ISPR forces interrupts into the pending state, and shows which + /// interrupts are pending. + pub const NVIC_ISPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt set-pending bits.\n + /// Write:\n + /// 0 = No effect.\n + /// 1 = Changes interrupt state to pending.\n + /// Read:\n + /// 0 = Interrupt is not pending.\n + /// 1 = Interrupt is pending.\n + /// Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n + /// An interrupt that is pending has no effect.\n + /// A disabled interrupt sets the state of that interrupt to pending. + SETPEND: u32, + }), base_address + 0xe200); + + /// address: 0xe000e280 + /// Use the Interrupt Clear-Pending Register to clear pending interrupts and + /// determine which interrupts are currently pending. + pub const NVIC_ICPR = @intToPtr(*volatile Mmio(32, packed struct { + /// Interrupt clear-pending bits.\n + /// Write:\n + /// 0 = No effect.\n + /// 1 = Removes pending state and interrupt.\n + /// Read:\n + /// 0 = Interrupt is not pending.\n + /// 1 = Interrupt is pending. + CLRPEND: u32, + }), base_address + 0xe280); + + /// address: 0xe000e400 + /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of + /// the available interrupts. 0 is the highest priority, and 3 is the lowest.\n + /// Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the + /// corresponding interrupt.\n + /// These registers are only word-accessible + pub const NVIC_IPR0 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// Priority of interrupt 0 + IP_0: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// Priority of interrupt 1 + IP_1: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// Priority of interrupt 2 + IP_2: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + /// Priority of interrupt 3 + IP_3: u2, + }), base_address + 0xe400); + + /// address: 0xe000e404 + /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of + /// the available interrupts. 0 is the highest priority, and 3 is the lowest. + pub const NVIC_IPR1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// Priority of interrupt 4 + IP_4: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// Priority of interrupt 5 + IP_5: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// Priority of interrupt 6 + IP_6: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + /// Priority of interrupt 7 + IP_7: u2, + }), base_address + 0xe404); + + /// address: 0xe000e408 + /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of + /// the available interrupts. 0 is the highest priority, and 3 is the lowest. + pub const NVIC_IPR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// Priority of interrupt 8 + IP_8: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// Priority of interrupt 9 + IP_9: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// Priority of interrupt 10 + IP_10: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + /// Priority of interrupt 11 + IP_11: u2, + }), base_address + 0xe408); + + /// address: 0xe000e40c + /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of + /// the available interrupts. 0 is the highest priority, and 3 is the lowest. + pub const NVIC_IPR3 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// Priority of interrupt 12 + IP_12: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// Priority of interrupt 13 + IP_13: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// Priority of interrupt 14 + IP_14: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + /// Priority of interrupt 15 + IP_15: u2, + }), base_address + 0xe40c); + + /// address: 0xe000e410 + /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of + /// the available interrupts. 0 is the highest priority, and 3 is the lowest. + pub const NVIC_IPR4 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// Priority of interrupt 16 + IP_16: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// Priority of interrupt 17 + IP_17: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// Priority of interrupt 18 + IP_18: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + /// Priority of interrupt 19 + IP_19: u2, + }), base_address + 0xe410); + + /// address: 0xe000e414 + /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of + /// the available interrupts. 0 is the highest priority, and 3 is the lowest. + pub const NVIC_IPR5 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// Priority of interrupt 20 + IP_20: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// Priority of interrupt 21 + IP_21: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// Priority of interrupt 22 + IP_22: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + /// Priority of interrupt 23 + IP_23: u2, + }), base_address + 0xe414); + + /// address: 0xe000e418 + /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of + /// the available interrupts. 0 is the highest priority, and 3 is the lowest. + pub const NVIC_IPR6 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// Priority of interrupt 24 + IP_24: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// Priority of interrupt 25 + IP_25: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// Priority of interrupt 26 + IP_26: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + /// Priority of interrupt 27 + IP_27: u2, + }), base_address + 0xe418); + + /// address: 0xe000e41c + /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of + /// the available interrupts. 0 is the highest priority, and 3 is the lowest. + pub const NVIC_IPR7 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + /// Priority of interrupt 28 + IP_28: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + /// Priority of interrupt 29 + IP_29: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + /// Priority of interrupt 30 + IP_30: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + /// Priority of interrupt 31 + IP_31: u2, + }), base_address + 0xe41c); + + /// address: 0xe000ed00 + /// Read the CPU ID Base Register to determine: the ID number of the processor core, + /// the version number of the processor core, the implementation details of the + /// processor core. + pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { + /// Minor revision number m in the rnpm revision status:\n + /// 0x1 = Patch 1. + REVISION: u4, + /// Number of processor within family: 0xC60 = Cortex-M0+ + PARTNO: u12, + /// Constant that defines the architecture of the processor:\n + /// 0xC = ARMv6-M architecture. + ARCHITECTURE: u4, + /// Major revision number n in the rnpm revision status:\n + /// 0x0 = Revision 0. + VARIANT: u4, + /// Implementor code: 0x41 = ARM + IMPLEMENTER: u8, + }), base_address + 0xed00); + + /// address: 0xe000ed04 + /// Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt + /// (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for + /// pending exceptions, check the vector number of the highest priority pended + /// exception, check the vector number of the active exception. + pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { + /// Active exception number field. Reset clears the VECTACTIVE field. + VECTACTIVE: u9, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// Indicates the exception number for the highest priority pending exception: 0 = + /// no pending exceptions. Non zero = The pending state includes the effect of + /// memory-mapped enable and mask registers. It does not include the PRIMASK + /// special-purpose register qualifier. + VECTPENDING: u9, + reserved3: u1 = 0, + /// External interrupt pending flag + ISRPENDING: u1, + /// The system can only access this bit when the core is halted. It indicates that a + /// pending interrupt is to be taken in the next running cycle. If C_MASKINTS is + /// clear in the Debug Halting Control and Status Register, the interrupt is + /// serviced. + ISRPREEMPT: u1, + reserved4: u1 = 0, + /// SysTick exception clear-pending bit.\n + /// Write:\n + /// 0 = No effect.\n + /// 1 = Removes the pending state from the SysTick exception.\n + /// This bit is WO. On a register read its value is Unknown. + PENDSTCLR: u1, + /// SysTick exception set-pending bit.\n + /// Write:\n + /// 0 = No effect.\n + /// 1 = Changes SysTick exception state to pending.\n + /// Read:\n + /// 0 = SysTick exception is not pending.\n + /// 1 = SysTick exception is pending. + PENDSTSET: u1, + /// PendSV clear-pending bit.\n + /// Write:\n + /// 0 = No effect.\n + /// 1 = Removes the pending state from the PendSV exception. + PENDSVCLR: u1, + /// PendSV set-pending bit.\n + /// Write:\n + /// 0 = No effect.\n + /// 1 = Changes PendSV exception state to pending.\n + /// Read:\n + /// 0 = PendSV exception is not pending.\n + /// 1 = PendSV exception is pending.\n + /// Writing 1 to this bit is the only way to set the PendSV exception state to + /// pending. + PENDSVSET: u1, + reserved5: u1 = 0, + reserved6: u1 = 0, + /// Setting this bit will activate an NMI. Since NMI is the highest priority + /// exception, it will activate as soon as it is registered.\n + /// NMI set-pending bit.\n + /// Write:\n + /// 0 = No effect.\n + /// 1 = Changes NMI exception state to pending.\n + /// Read:\n + /// 0 = NMI exception is not pending.\n + /// 1 = NMI exception is pending.\n + /// Because NMI is the highest-priority exception, normally the processor enters the + /// NMI\n + /// exception handler as soon as it detects a write of 1 to this bit. Entering the + /// handler then clears\n + /// this bit to 0. This means a read of this bit by the NMI exception handler + /// returns 1 only if the\n + /// NMI signal is reasserted while the processor is executing that handler. + NMIPENDSET: u1, + }), base_address + 0xed04); + + /// address: 0xe000ed08 + /// The VTOR holds the vector table offset address. + pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Bits [31:8] of the indicate the vector table offset address. + TBLOFF: u24, + }), base_address + 0xed08); + + /// address: 0xe000ed0c + /// Use the Application Interrupt and Reset Control Register to: determine data + /// endianness, clear all active state information from debug halt mode, request a + /// system reset. + pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + /// Clears all active state information for fixed and configurable exceptions. This + /// bit: is self-clearing, can only be set by the DAP when the core is halted. When + /// set: clears all active exception status of the processor, forces a return to + /// Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. + VECTCLRACTIVE: u1, + /// Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be + /// asserted to request a reset. The intention is to force a large system reset of + /// all major components except for debug. The C_HALT bit in the DHCSR is cleared as + /// a result of the system reset requested. The debugger does not lose contact with + /// the device. + SYSRESETREQ: u1, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + /// Data endianness implemented:\n + /// 0 = Little-endian. + ENDIANESS: u1, + /// Register key:\n + /// Reads as Unknown\n + /// On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. + VECTKEY: u16, + }), base_address + 0xed0c); + + /// address: 0xe000ed10 + /// System Control Register. Use the System Control Register for power-management + /// functions: signal to the system when the processor can enter a low power state, + /// control how the processor enters and exits low power states. + pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + /// Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n + /// 0 = Do not sleep when returning to Thread mode.\n + /// 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n + /// Setting this bit to 1 enables an interrupt driven application to avoid returning + /// to an empty main application. + SLEEPONEXIT: u1, + /// Controls whether the processor uses sleep or deep sleep as its low power mode:\n + /// 0 = Sleep.\n + /// 1 = Deep sleep. + SLEEPDEEP: u1, + reserved1: u1 = 0, + /// Send Event on Pending bit:\n + /// 0 = Only enabled interrupts or events can wakeup the processor, disabled + /// interrupts are excluded.\n + /// 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup + /// the processor.\n + /// When an event or interrupt becomes pending, the event signal wakes up the + /// processor from WFE. If the\n + /// processor is not waiting for an event, the event is registered and affects the + /// next WFE.\n + /// The processor also wakes up on execution of an SEV instruction or an external + /// event. + SEVONPEND: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + }), base_address + 0xed10); + + /// address: 0xe000ed14 + /// The Configuration and Control Register permanently enables stack alignment and + /// causes unaligned accesses to result in a Hard Fault. + pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// Always reads as one, indicates that all unaligned accesses generate a HardFault. + UNALIGN_TRP: u1, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + /// Always reads as one, indicates 8-byte stack alignment on exception entry. On + /// exception entry, the processor uses bit[9] of the stacked PSR to indicate the + /// stack alignment. On return from the exception it uses this stacked bit to + /// restore the correct stack alignment. + STKALIGN: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + }), base_address + 0xed14); + + /// address: 0xe000ed1c + /// System handlers are a special class of exception handler that can have their + /// priority set to any of the priority levels. Use the System Handler Priority + /// Register 2 to set the priority of SVCall. + pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + reserved24: u1 = 0, + reserved25: u1 = 0, + reserved26: u1 = 0, + reserved27: u1 = 0, + reserved28: u1 = 0, + reserved29: u1 = 0, + /// Priority of system handler 11, SVCall + PRI_11: u2, + }), base_address + 0xed1c); + + /// address: 0xe000ed20 + /// System handlers are a special class of exception handler that can have their + /// priority set to any of the priority levels. Use the System Handler Priority + /// Register 3 to set the priority of PendSV and SysTick. + pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + /// Priority of system handler 14, PendSV + PRI_14: u2, + reserved22: u1 = 0, + reserved23: u1 = 0, + reserved24: u1 = 0, + reserved25: u1 = 0, + reserved26: u1 = 0, + reserved27: u1 = 0, + /// Priority of system handler 15, SysTick + PRI_15: u2, + }), base_address + 0xed20); + + /// address: 0xe000ed24 + /// Use the System Handler Control and State Register to determine or clear the + /// pending status of SVCall. + pub const SHCSR = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + /// Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear + /// pending SVCall. + SVCALLPENDED: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0xed24); + + /// address: 0xe000ed90 + /// Read the MPU Type Register to determine if the processor implements an MPU, and + /// how many regions the MPU supports. + pub const MPU_TYPE = @intToPtr(*volatile Mmio(32, packed struct { + /// Indicates support for separate instruction and data address maps. Reads as 0 as + /// ARMv6-M only supports a unified MPU. + SEPARATE: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + reserved6: u1 = 0, + /// Number of regions supported by the MPU. + DREGION: u8, + /// Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. + IREGION: u8, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + }), base_address + 0xed90); + + /// address: 0xe000ed94 + /// Use the MPU Control Register to enable and disable the MPU, and to control + /// whether the default memory map is enabled as a background region for privileged + /// accesses, and whether the MPU is enabled for HardFaults and NMIs. + pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct { + /// Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses + /// use the default memory map.\n + /// 0 = MPU disabled.\n + /// 1 = MPU enabled. + ENABLE: u1, + /// Controls the use of the MPU for HardFaults and NMIs. Setting this bit when + /// ENABLE is clear results in UNPREDICTABLE behaviour.\n + /// When the MPU is enabled:\n + /// 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value + /// of the ENABLE bit.\n + /// 1 = the MPU is enabled during HardFault and NMI handlers. + HFNMIENA: u1, + /// Controls whether the default memory map is enabled as a background region for + /// privileged accesses. This bit is ignored when ENABLE is clear.\n + /// 0 = If the MPU is enabled, disables use of the default memory map. Any memory + /// access to a location not\n + /// covered by any enabled region causes a fault.\n + /// 1 = If the MPU is enabled, enables use of the default memory map as a background + /// region for privileged software accesses.\n + /// When enabled, the background region acts as if it is region number -1. Any + /// region that is defined and enabled has priority over this default map. + PRIVDEFENA: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + padding28: u1 = 0, + }), base_address + 0xed94); + + /// address: 0xe000ed98 + /// Use the MPU Region Number Register to select the region currently accessed by + /// MPU_RBAR and MPU_RASR. + pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct { + /// Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n + /// The MPU supports 8 memory regions, so the permitted values of this field are + /// 0-7. + REGION: u4, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + padding16: u1 = 0, + padding17: u1 = 0, + padding18: u1 = 0, + padding19: u1 = 0, + padding20: u1 = 0, + padding21: u1 = 0, + padding22: u1 = 0, + padding23: u1 = 0, + padding24: u1 = 0, + padding25: u1 = 0, + padding26: u1 = 0, + padding27: u1 = 0, + }), base_address + 0xed98); + + /// address: 0xe000ed9c + /// Read the MPU Region Base Address Register to determine the base address of the + /// region identified by MPU_RNR. Write to update the base address of said region or + /// that of a specified region, with whose number MPU_RNR will also be updated. + pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct { + /// On writes, specifies the number of the region whose base address to update + /// provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. + REGION: u4, + /// On writes, indicates whether the write must update the base address of the + /// region identified by the REGION field, updating the MPU_RNR to indicate this new + /// region.\n + /// Write:\n + /// 0 = MPU_RNR not changed, and the processor:\n + /// Updates the base address for the region specified in the MPU_RNR.\n + /// Ignores the value of the REGION field.\n + /// 1 = The processor:\n + /// Updates the value of the MPU_RNR to the value of the REGION field.\n + /// Updates the base address for the region specified in the REGION field.\n + /// Always reads as zero. + VALID: u1, + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + /// Base address of the region. + ADDR: u24, + }), base_address + 0xed9c); + + /// address: 0xe000eda0 + /// Use the MPU Region Attribute and Size Register to define the size, access + /// behaviour and memory type of the region identified by MPU_RNR, and enable that + /// region. + pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct { + /// Enables the region. + ENABLE: u1, + /// Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum + /// permitted value is 7 (b00111) = 256Bytes + SIZE: u5, + reserved0: u1 = 0, + reserved1: u1 = 0, + /// Subregion Disable. For regions of 256 bytes or larger, each bit of this field + /// controls whether one of the eight equal subregions is enabled. + SRD: u8, + /// The MPU Region Attribute field. Use to define the region attribute control.\n + /// 28 = XN: Instruction access disable bit:\n + /// 0 = Instruction fetches enabled.\n + /// 1 = Instruction fetches disabled.\n + /// 26:24 = AP: Access permission field\n + /// 18 = S: Shareable bit\n + /// 17 = C: Cacheable bit\n + /// 16 = B: Bufferable bit + ATTRS: u16, + }), base_address + 0xeda0); + }; +}; + +const std = @import("std"); + +pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) { + return @intToPtr(*volatile Mmio(size, PackedT), addr); +} + +pub fn Mmio(comptime size: u8, comptime PackedT: type) type { + if ((size % 8) != 0) + @compileError("size must be divisible by 8!"); + + if (!std.math.isPowerOfTwo(size / 8)) + @compileError("size must encode a power of two number of bytes!"); + + const IntT = std.meta.Int(.unsigned, size); + + if (@sizeOf(PackedT) != (size / 8)) + @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) })); + + return extern struct { + const Self = @This(); + + raw: IntT, + + pub const underlying_type = PackedT; + + pub inline fn read(addr: *volatile Self) PackedT { + return @bitCast(PackedT, addr.raw); + } + + pub inline fn write(addr: *volatile Self, val: PackedT) void { + // This is a workaround for a compiler bug related to miscompilation + // If the tmp var is not used, result location will fuck things up + var tmp = @bitCast(IntT, val); + addr.raw = tmp; + } + + pub inline fn modify(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, field.name) = @field(fields, field.name); + } + write(addr, val); + } + + pub inline fn toggle(addr: *volatile Self, fields: anytype) void { + var val = read(addr); + inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| { + @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?)); + } + write(addr, val); + } + }; +} + +pub fn MmioInt(comptime size: u8, comptime T: type) type { + return extern struct { + const Self = @This(); + + raw: std.meta.Int(.unsigned, size), + + pub inline fn read(addr: *volatile Self) T { + return @truncate(T, addr.raw); + } + + pub inline fn modify(addr: *volatile Self, val: T) void { + const Int = std.meta.Int(.unsigned, size); + const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1); + + var tmp = addr.raw; + addr.raw = (tmp & mask) | val; + } + }; +} + +pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) { + return @intToPtr(*volatile MmioInt(size, T), addr); +} + +const InterruptVector = extern union { + C: fn () callconv(.C) void, + Naked: fn () callconv(.Naked) void, + // Interrupt is not supported on arm +}; + +const unhandled = InterruptVector{ + .C = struct { + fn tmp() callconv(.C) noreturn { + @panic("unhandled interrupt"); + } + }.tmp, +}; From c2a6b718e7fd8fc9d161ddfe95523e3dde602637 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Tue, 7 Jun 2022 01:20:38 -0700 Subject: [PATCH 002/286] add license remove microzig submodule remove submodule --- .gitmodules | 3 --- LICENSE | 11 +++++++++++ microzig | 1 - 3 files changed, 11 insertions(+), 4 deletions(-) delete mode 100644 .gitmodules create mode 100644 LICENSE delete mode 160000 microzig diff --git a/.gitmodules b/.gitmodules deleted file mode 100644 index fdd0dab01..000000000 --- a/.gitmodules +++ /dev/null @@ -1,3 +0,0 @@ -[submodule "microzig"] - path = microzig - url = git@github.com:ZigEmbeddedGroup/microzig.git diff --git a/LICENSE b/LICENSE new file mode 100644 index 000000000..8df59b21f --- /dev/null +++ b/LICENSE @@ -0,0 +1,11 @@ +Copyright (c) 2022 Zig Embedded Group contributors + +This software is provided 'as-is', without any express or implied warranty. In no event will the authors be held liable for any damages arising from the use of this software. + +Permission is granted to anyone to use this software for any purpose, including commercial applications, and to alter it and redistribute it freely, subject to the following restrictions: + +1. The origin of this software must not be misrepresented; you must not claim that you wrote the original software. If you use this software in a product, an acknowledgment in the product documentation would be appreciated but is not required. + +2. Altered source versions must be plainly marked as such, and must not be misrepresented as being the original software. + +3. This notice may not be removed or altered from any source distribution. diff --git a/microzig b/microzig deleted file mode 160000 index ac19b7de8..000000000 --- a/microzig +++ /dev/null @@ -1 +0,0 @@ -Subproject commit ac19b7de8eb1551e603b3ce23a4aab69c71d1216 From 7d68b0bcbad63501235ea6a25f483d04678000f9 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 3 Jul 2022 07:52:26 -0700 Subject: [PATCH 003/286] pads bank bits set when setting gpio function --- src/hal/gpio.zig | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig index ab0f66696..defc71962 100644 --- a/src/hal/gpio.zig +++ b/src/hal/gpio.zig @@ -90,6 +90,12 @@ pub const Enabled = enum { enabled, }; +pub inline fn reset() void { + regs.RESETS.RESET.modify(.{ .io_bank0 = 1, .pads_bank0 = 1 }); + while (regs.RESETS.RESET_DONE.read().io_bank0 == 1) {} + while (regs.RESETS.RESET_DONE.read().pads_bank0 == 1) {} +} + //const gpio_num = gpio_num: { // // calculate max gpios using comptime parsing //}; @@ -122,8 +128,14 @@ pub inline fn put(comptime gpio: u32, value: u1) void { } pub inline fn setFunction(comptime gpio: u32, function: Function) void { - const reg_name = comptime std.fmt.comptimePrint("GPIO{}_CTRL", .{gpio}); - @field(regs.IO_BANK0, reg_name).write(.{ + const pad_bank_reg = comptime std.fmt.comptimePrint("GPIO{}", .{gpio}); + @field(regs.PADS_BANK0, pad_bank_reg).modify(.{ + .IE = 1, + .OD = 0, + }); + + const io_bank_reg = comptime std.fmt.comptimePrint("GPIO{}_CTRL", .{gpio}); + @field(regs.IO_BANK0, io_bank_reg).write(.{ .FUNCSEL = @enumToInt(function), .OUTOVER = 0, .INOVER = 0, From e541f966d42004acbcba9a939c0acfb604a3b4d5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20=27vesim=27=20Kuli=C5=84ski?= Date: Wed, 6 Jul 2022 21:29:36 +0200 Subject: [PATCH 004/286] multicore: add initial support --- src/hal.zig | 1 + src/hal/multicore.zig | 109 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) create mode 100644 src/hal/multicore.zig diff --git a/src/hal.zig b/src/hal.zig index 41f474420..ae181dad4 100644 --- a/src/hal.zig +++ b/src/hal.zig @@ -2,6 +2,7 @@ const microzig = @import("microzig"); const regs = microzig.chip.regsisters; pub const gpio = @import("hal/gpio.zig"); pub const clocks = @import("hal/clocks.zig"); +pub const multicore = @import("hal/multicore.zig"); pub const default_clock_config = clocks.GlobalConfiguration.init(.{ //.ref = .{ .source = .src_xosc }, diff --git a/src/hal/multicore.zig b/src/hal/multicore.zig new file mode 100644 index 000000000..5c95c1334 --- /dev/null +++ b/src/hal/multicore.zig @@ -0,0 +1,109 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const regs = microzig.chip.registers; +const assert = std.debug.assert; + +pub const fifo = struct { + /// Check if the FIFO has valid data for reading. + pub fn is_read_ready() bool { + return regs.SIO.FIFO_ST.read().VLD == 1; + } + + /// Read from the FIFO + /// Will return null if it is empty. + pub fn read() ?u32 { + if (!is_read_ready()) + return null; + + return regs.SIO.FIFO_RD.*; + } + + /// Read from the FIFO, waiting for data if there is none. + pub fn read_blocking() u32 { + while (true) { + if (read()) |value| return value; + microzig.cpu.wfe(); + } + } + + /// Read from the FIFO, and throw everyting away. + pub fn drain() void { + while (read()) |_| {} + } + + /// Check if the FIFO is ready to receive data. + pub fn is_write_ready() bool { + return regs.SIO.FIFO_ST.read().RDY == 1; + } + + /// Write to the FIFO + /// You must check if there is space by calling is_write_ready + pub fn write(value: u32) void { + regs.SIO.FIFO_WR.* = value; + microzig.cpu.sev(); + } + + /// Write to the FIFO, waiting for room if it is full. + pub fn write_blocking(value: u32) void { + while (!is_write_ready()) + std.mem.doNotOptimizeAway(value); + + write(value); + } +}; + +var core1_stack: [128]u32 = undefined; + +/// Runs `entrypoint` on the second core. +pub fn launchCore1(entrypoint: fn () void) void { + launchCore1WithStack(entrypoint, &core1_stack); +} + +pub fn launchCore1WithStack(entrypoint: fn () void, stack: []u32) void { + // TODO: disable SIO interrupts + + const wrapper = struct { + fn wrapper(_: u32, _: u32, _: u32, _: u32, entry: u32, stack_base: [*]u32) callconv(.C) void { + // TODO: protect stack using MPU + _ = stack_base; + @intToPtr(fn () void, entry)(); + } + }.wrapper; + + // reset the second core + regs.PSM.FRCE_OFF.modify(.{ .proc1 = 1 }); + while (regs.PSM.FRCE_OFF.read().proc1 != 1) microzig.cpu.nop(); + regs.PSM.FRCE_OFF.modify(.{ .proc1 = 0 }); + + stack[stack.len - 2] = @ptrToInt(entrypoint); + stack[stack.len - 1] = @ptrToInt(stack.ptr); + + // calculate top of the stack + const stack_ptr: u32 = + @ptrToInt(stack.ptr) + + (stack.len - 2) * @sizeOf(u32); // pop the two elements we "pushed" above + + // after reseting core1 is waiting for this specific sequence + const cmds: [6]u32 = .{ + 0, + 0, + 1, + regs.PPB.VTOR.raw, + stack_ptr, + @ptrToInt(wrapper), + }; + + var seq: usize = 0; + while (seq < cmds.len) { + const cmd = cmds[seq]; + if (cmd == 0) { + // always drain the fifo before sending zero + fifo.drain(); + microzig.cpu.sev(); + } + + fifo.write_blocking(cmd); + // the second core should respond with the same value, if it doesnt't lets start over + seq = if (cmd == fifo.read_blocking()) seq + 1 else 0; + } +} From 0659bcd8c6296fcb10f2e0532ce9ff332ca2afbd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Maciej=20=27vesim=27=20Kuli=C5=84ski?= Date: Thu, 7 Jul 2022 00:05:56 +0200 Subject: [PATCH 005/286] multicore: use camelCase for function names --- src/hal/multicore.zig | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/hal/multicore.zig b/src/hal/multicore.zig index 5c95c1334..dd90d17d5 100644 --- a/src/hal/multicore.zig +++ b/src/hal/multicore.zig @@ -5,21 +5,21 @@ const assert = std.debug.assert; pub const fifo = struct { /// Check if the FIFO has valid data for reading. - pub fn is_read_ready() bool { + pub fn isReadReady() bool { return regs.SIO.FIFO_ST.read().VLD == 1; } /// Read from the FIFO /// Will return null if it is empty. pub fn read() ?u32 { - if (!is_read_ready()) + if (!isReadReady()) return null; return regs.SIO.FIFO_RD.*; } /// Read from the FIFO, waiting for data if there is none. - pub fn read_blocking() u32 { + pub fn readBloacking() u32 { while (true) { if (read()) |value| return value; microzig.cpu.wfe(); @@ -32,7 +32,7 @@ pub const fifo = struct { } /// Check if the FIFO is ready to receive data. - pub fn is_write_ready() bool { + pub fn isWriteReady() bool { return regs.SIO.FIFO_ST.read().RDY == 1; } @@ -44,8 +44,8 @@ pub const fifo = struct { } /// Write to the FIFO, waiting for room if it is full. - pub fn write_blocking(value: u32) void { - while (!is_write_ready()) + pub fn writeBlocking(value: u32) void { + while (!isWriteReady()) std.mem.doNotOptimizeAway(value); write(value); @@ -102,8 +102,8 @@ pub fn launchCore1WithStack(entrypoint: fn () void, stack: []u32) void { microzig.cpu.sev(); } - fifo.write_blocking(cmd); + fifo.writeBlocking(cmd); // the second core should respond with the same value, if it doesnt't lets start over - seq = if (cmd == fifo.read_blocking()) seq + 1 else 0; + seq = if (cmd == fifo.readBloacking()) seq + 1 else 0; } } From 303c9f183f8456edea52ab17f513f4acc8a2df4c Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 7 Jul 2022 21:38:40 -0700 Subject: [PATCH 006/286] add busy sleep functions --- src/hal.zig | 1 + src/hal/time.zig | 44 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+) create mode 100644 src/hal/time.zig diff --git a/src/hal.zig b/src/hal.zig index ae181dad4..1a793b1b3 100644 --- a/src/hal.zig +++ b/src/hal.zig @@ -3,6 +3,7 @@ const regs = microzig.chip.regsisters; pub const gpio = @import("hal/gpio.zig"); pub const clocks = @import("hal/clocks.zig"); pub const multicore = @import("hal/multicore.zig"); +pub const time = @import("hal/time.zig"); pub const default_clock_config = clocks.GlobalConfiguration.init(.{ //.ref = .{ .source = .src_xosc }, diff --git a/src/hal/time.zig b/src/hal/time.zig new file mode 100644 index 000000000..2ed49aeb8 --- /dev/null +++ b/src/hal/time.zig @@ -0,0 +1,44 @@ +const microzig = @import("microzig"); +const TIMER = microzig.chip.registers.TIMER; + +pub const Absolute = struct { + us_since_boot: u64, +}; + +pub fn getTimeSinceBoot() Absolute { + var high_word = TIMER.TIMERAWH.*; + + return while (true) { + var low_word = TIMER.TIMERAWL.*; + const next_high_word = TIMER.TIMERAWH.*; + if (next_high_word == high_word) + break Absolute{ + .us_since_boot = @intCast(u64, high_word) << 32 | low_word, + }; + + high_word = next_high_word; + } else unreachable; +} + +pub fn makeTimeoutUs(timeout_us: u64) Absolute { + return Absolute{ + .us_since_boot = getTimeSinceBoot().us_since_boot + timeout_us, + }; +} + +pub fn reached(time: Absolute) bool { + const now = getTimeSinceBoot(); + return now.us_since_boot >= time.us_since_boot; +} + +pub fn sleepMs(time_ms: u32) void { + sleepUs(time_ms * 1000); +} + +pub fn sleepUs(time_us: u64) void { + const end_time = Absolute{ + .us_since_boot = time_us + getTimeSinceBoot().us_since_boot, + }; + + while (!reached(end_time)) {} +} From ed05258e7ee4f0475bccd10110587e29602df9a7 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 8 Jul 2022 16:52:14 -0700 Subject: [PATCH 007/286] clean up gpios --- src/hal/gpio.zig | 36 ++++++++++++++++++++---------------- 1 file changed, 20 insertions(+), 16 deletions(-) diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig index defc71962..416b1559c 100644 --- a/src/hal/gpio.zig +++ b/src/hal/gpio.zig @@ -79,10 +79,10 @@ pub const SlewRate = enum { }; pub const DriveStrength = enum { - ma_2, - ma_4, - ma_8, - ma_12, + @"2mA", + @"4mA", + @"8mA", + @"12mA", }; pub const Enabled = enum { @@ -92,18 +92,20 @@ pub const Enabled = enum { pub inline fn reset() void { regs.RESETS.RESET.modify(.{ .io_bank0 = 1, .pads_bank0 = 1 }); - while (regs.RESETS.RESET_DONE.read().io_bank0 == 1) {} - while (regs.RESETS.RESET_DONE.read().pads_bank0 == 1) {} -} + regs.RESETS.RESET.modify(.{ .io_bank0 = 0, .pads_bank0 = 0 }); -//const gpio_num = gpio_num: { -// // calculate max gpios using comptime parsing -//}; + while (true) { + const reset_done = regs.RESETS.RESET_DONE.read(); + if (reset_done.io_bank0 == 1 and reset_done.pads_bank0 == 1) + break; + } +} /// Initialize a GPIO, set func to SIO pub inline fn init(comptime gpio: u32) void { - regs.SIO.GPIO_OE_CLR.raw = 1 << gpio; - regs.SIO.GPIO_OUT_CLR.raw = 1 << gpio; + const mask = 1 << gpio; + regs.SIO.GPIO_OE_CLR.raw = mask; + regs.SIO.GPIO_OUT_CLR.raw = mask; setFunction(gpio, .sio); } @@ -113,17 +115,19 @@ pub inline fn deinit(comptime gpio: u32) void { } pub inline fn setDir(comptime gpio: u32, direction: Direction) void { + const mask = 1 << gpio; switch (direction) { - .in => regs.SIO.GPIO_OE_CLR.raw |= (1 << gpio), - .out => regs.SIO.GPIO_OE_SET.raw &= (1 << gpio), + .in => regs.SIO.GPIO_OE_CLR.raw = mask, + .out => regs.SIO.GPIO_OE_SET.raw = mask, } } /// Drive a single GPIO high/low pub inline fn put(comptime gpio: u32, value: u1) void { + const mask = 1 << gpio; switch (value) { - 0 => regs.SIO.GPIO_OUT.raw &= ~@as(u32, 1 << gpio), - 1 => regs.SIO.GPIO_OUT.raw |= (1 << gpio), + 0 => regs.SIO.GPIO_OUT_CLR.raw = mask, + 1 => regs.SIO.GPIO_OUT_SET.raw = mask, } } From 8751f6753d9a187ed6902f075914b77de6ce64e4 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 10 Jul 2022 16:26:47 -0700 Subject: [PATCH 008/286] Clock config (#5) * use array access for better codegen * frequency counter * wip * wip * refactor clock config and plls to reduce binary size --- src/hal.zig | 21 ++- src/hal/clocks.zig | 358 +++++++++++++++++++++++++++++++-------------- src/hal/pll.zig | 79 +++++----- src/hal/util.zig | 18 +++ 4 files changed, 323 insertions(+), 153 deletions(-) create mode 100644 src/hal/util.zig diff --git a/src/hal.zig b/src/hal.zig index 1a793b1b3..3db067744 100644 --- a/src/hal.zig +++ b/src/hal.zig @@ -5,18 +5,23 @@ pub const clocks = @import("hal/clocks.zig"); pub const multicore = @import("hal/multicore.zig"); pub const time = @import("hal/time.zig"); -pub const default_clock_config = clocks.GlobalConfiguration.init(.{ - //.ref = .{ .source = .src_xosc }, - .sys = .{ - .source = .pll_sys, - .freq = 125_000_000, - }, - .usb = .{ .source = .pll_usb }, +pub const clock_config = clocks.GlobalConfiguration.init(.{ + .sys = .{ .source = .src_xosc }, + .peri = .{ .source = .clk_sys }, + //.sys = .{ + // .source = .pll_sys, + // .freq = 125_000_000, + //}, + //.usb = .{ .source = .pll_usb }, //.adc = .{ .source = .pll_usb }, //.rtc = .{ .source = .pll_usb }, - .peri = .{ .source = .clk_sys }, + //.peri = .{ .source = .clk_sys }, }); +pub fn init() void { + clock_config.apply(); +} + pub fn getCpuId() u32 { return regs.SIO.CPUID.*; } diff --git a/src/hal/clocks.zig b/src/hal/clocks.zig index 7f266e299..fc28c1903 100644 --- a/src/hal/clocks.zig +++ b/src/hal/clocks.zig @@ -1,11 +1,12 @@ const std = @import("std"); const microzig = @import("microzig"); const pll = @import("pll.zig"); +const util = @import("util.zig"); const assert = std.debug.assert; const regs = microzig.chip.registers; +const CLOCKS = regs.CLOCKS; const xosc_freq = microzig.board.xosc_freq; -// TODO: move to board file /// this is only nominal, very imprecise and prone to drift over time const rosc_freq = 6_500_000; @@ -64,37 +65,23 @@ pub const Generator = enum { adc, rtc, - // source directly from register definitions - const Source = enum { - rosc_clksrc_ph, - clksrc_clk_ref_aux, - xosc_clksrc, - clk_ref, - clksrc_clk_sys_aux, + // in some cases we can pretend the Generators are a homogenous array of + // register clusters for the sake of smaller codegen + const GeneratorRegs = packed struct { + ctrl: u32, + div: u32, + selected: u32, }; - // aux sources directly from register definitions - const AuxilarySource = enum { - clksrc_pll_sys, - clksrc_gpin0, - clksrc_gpin1, - clksrc_pll_usb, - rosc_clksrc, - xosc_clksrc, - clk_sys, - clk_usb, - clk_adc, - clk_rtc, - clk_ref, - rosc_clksrc_ph, - }; - - const source_map = struct { - const ref = [_]Generator.Source{ .rosc_clksrc_ph, .clksrc_clk_ref, .xosc_clksrc }; - const sys = [_]Generator.Source{ .clk_ref, .clksrc_clk_sys_aux }; - }; + comptime { + assert(12 == @sizeOf(GeneratorRegs)); + assert(24 == @sizeOf([2]GeneratorRegs)); + } - const aux_map = struct {}; + const generators = @intToPtr( + *volatile [9]GeneratorRegs, + regs.CLOCKS.base_address, + ); pub fn hasGlitchlessMux(generator: Generator) bool { return switch (generator) { @@ -104,46 +91,24 @@ pub const Generator = enum { } pub fn enable(generator: Generator) void { - inline for (std.meta.fields(Generator)) |field| { - if (generator == @field(Generator, field.name)) { - const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_CTRL", .{ - uppercase(field.name), - }); - - if (@hasField(@TypeOf(@field(regs.CLOCKS, reg_name).*).underlying_type, "ENABLE")) - @field(regs.CLOCKS, reg_name).modify(.{ .ENABLE = 1 }); - } + switch (generator) { + .ref, .sys => {}, + else => generators[@enumToInt(generator)].ctrl |= (1 << 11), } } pub fn setDiv(generator: Generator, div: u32) void { - inline for (std.meta.fields(Generator)) |field| { - if (generator == @field(Generator, field.name)) { - const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_DIV", .{ - uppercase(field.name), - }); - - if (@hasDecl(regs.CLOCKS, reg_name)) - @field(regs.CLOCKS, reg_name).raw = div - else - assert(false); // doesn't have a divider - } - } + if (generator == .peri) + return; + + generators[@enumToInt(generator)].div = div; } pub fn getDiv(generator: Generator) u32 { - return inline for (std.meta.fields(Generator)) |field| { - if (generator == @field(Generator, field.name)) { - const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_DIV", .{ - uppercase(field.name), - }); - - break if (@hasDecl(regs.CLOCKS, reg_name)) - @field(regs.CLOCKS, reg_name).raw - else - 1; - } - } else unreachable; + if (generator == .peri) + return 1; + + return generators[@enumToInt(generator)].div; } // The bitfields for the *_SELECTED registers are actually a mask of which @@ -153,29 +118,151 @@ pub const Generator = enum { // // Some mention that this is only for the glitchless mux, so if it is non-glitchless then return true pub fn selected(generator: Generator) bool { - inline for (std.meta.fields(Generator)) |field| { - if (generator == @field(Generator, field.name)) { - return if (@field(Generator, field.name).hasGlitchlessMux()) ret: { - const reg_name = comptime std.fmt.comptimePrint("CLK_{s}_SELECTED", .{ - uppercase(field.name), - }); - - break :ret @field(regs.CLOCKS, reg_name).* != 0; - } else true; - } - } else unreachable; + return (0 != generators[@enumToInt(generator)].selected); + } + + pub fn clearSource(generator: Generator) void { + generators[@enumToInt(generator)].ctrl &= ~@as(u32, 0x3); + } + + pub fn disable(generator: Generator) void { + switch (generator) { + .sys, .ref => {}, + else => generators[@enumToInt(generator)].ctrl &= ~@as(u32, 1 << 11), + } + } + + pub fn isAuxSource(generator: Generator, source: Source) bool { + return switch (generator) { + .sys => switch (source) { + .clk_ref => false, + else => true, + }, + .ref => switch (source) { + .src_rosc, .src_xosc => false, + else => true, + }, + else => true, + }; + } + + pub fn setSource(generator: Generator, src: u32) void { + const mask = ~@as(u32, 0x3); + const ctrl_value = generators[@enumToInt(generator)].ctrl; + generators[@enumToInt(generator)].ctrl = (ctrl_value & mask) | src; + } + + pub fn setAuxSource(generator: Generator, auxsrc: u32) void { + const mask = ~@as(u32, 0x1e0); + const ctrl_value = generators[@enumToInt(generator)].ctrl; + generators[@enumToInt(generator)].ctrl = (ctrl_value & mask) | (auxsrc << 5); } }; pub const Source = enum { src_rosc, src_xosc, - src_aux, + src_gpin0, + src_gpin1, pll_sys, pll_usb, clk_sys, + clk_ref, + clk_usb, + clk_adc, + clk_rtc, }; +fn srcValue(generator: Generator, source: Source) u32 { + return switch (generator) { + .sys => src: { + const ret: u32 = switch (source) { + .clk_ref => 0, + else => 1, + }; + break :src ret; + }, + .ref => src: { + const ret: u32 = switch (source) { + .src_rosc => 0, + .src_xosc => 2, + else => 1, + }; + break :src ret; + }, + else => 0, + }; +} + +fn auxSrcValue(generator: Generator, source: Source) u32 { + return switch (generator) { + .sys => auxsrc: { + const ret: u32 = switch (source) { + .pll_sys => 0, + .pll_usb => 1, + .src_rosc => 2, + .src_xosc => 3, + .src_gpin0 => 4, + .src_gpin1 => 5, + else => @panic("invalid source for generator"), + }; + break :auxsrc ret; + }, + .ref => auxsrc: { + const ret: u32 = switch (source) { + // zero'd out because it is a src option + .src_xosc => 0, + .pll_sys => 0, + .src_gpin0 => 1, + .src_gpin1 => 2, + else => @panic("invalid source for generator"), + }; + break :auxsrc ret; + }, + .peri => auxsrc: { + const ret: u32 = switch (source) { + .clk_sys => 0, + .pll_sys => 1, + .pll_usb => 2, + .src_rosc => 3, + .src_xosc => 4, + .src_gpin0 => 5, + .src_gpin1 => 6, + else => @panic("invalid source for generator"), + }; + break :auxsrc ret; + }, + .usb, .adc, .rtc => auxsrc: { + const ret: u32 = switch (source) { + .pll_usb => 0, + .pll_sys => 1, + .src_rosc => 2, + .src_xosc => 3, + .src_gpin0 => 4, + .src_gpin1 => 5, + else => @panic("invalid source for generator"), + }; + break :auxsrc ret; + }, + .gpout0, .gpout1, .gpout2, .gpout3 => auxsrc: { + const ret: u32 = switch (source) { + .pll_sys => 0, + .src_gpin0 => 1, + .src_gpin1 => 2, + .pll_usb => 3, + .src_rosc => 4, + .src_xosc => 5, + .clk_sys => 6, + .clk_usb => 7, + .clk_adc => 8, + .clk_rtc => 9, + .clk_ref => 10, + }; + break :auxsrc ret; + }, + }; +} + pub const GlobalConfiguration = struct { xosc_configured: bool, sys: ?Configuration, @@ -221,8 +308,10 @@ pub const GlobalConfiguration = struct { output_freq = sys_opts.freq orelse rosc_freq; assert(output_freq.? <= rosc_freq); break :input .{ - .source = .rosc, + .source = .src_rosc, .freq = rosc_freq, + .src_value = srcValue(.sys, .src_rosc), + .auxsrc_value = auxSrcValue(.sys, .src_rosc), }; }, .src_xosc => input: { @@ -230,8 +319,10 @@ pub const GlobalConfiguration = struct { output_freq = sys_opts.freq orelse xosc_freq; assert(output_freq.? <= xosc_freq); break :input .{ - .source = .xosc, + .source = .src_xosc, .freq = xosc_freq, + .src_value = srcValue(.sys, .src_xosc), + .auxsrc_value = auxSrcValue(.sys, .src_xosc), }; }, .pll_sys => input: { @@ -252,6 +343,8 @@ pub const GlobalConfiguration = struct { // TODO: not really sure what frequency to // drive pll at yet, but this is an okay start .freq = 125_000_000, + .src_value = srcValue(.sys, .pll_sys), + .auxsrc_value = auxSrcValue(.sys, .pll_sys), }; }, @@ -281,6 +374,8 @@ pub const GlobalConfiguration = struct { .input = .{ .source = .pll_usb, .freq = 48_000_000, + .src_value = srcValue(.usb, .pll_usb), + .auxsrc_value = auxSrcValue(.usb, .pll_usb), }, .output_freq = 48_000_000, }; @@ -297,6 +392,8 @@ pub const GlobalConfiguration = struct { .input = .{ .source = .src_xosc, .freq = xosc_freq, + .src_value = srcValue(.ref, .src_xosc), + .auxsrc_value = auxSrcValue(.ref, .src_xosc), }, .output_freq = xosc_freq, }; @@ -306,10 +403,31 @@ pub const GlobalConfiguration = struct { // either use the ROSC, XOSC, or sys PLL, with whatever dividing // they need - .adc = if (opts.adc) |_| - unreachable // TODO - else - null, + // adc requires a 48MHz clock, so only ever let it get hooked up to + // the usb PLL + .adc = if (opts.adc) |adc_opts| adc_config: { + assert(adc_opts.source == .pll_usb); + xosc_configured = true; + + // TODO: some safety checks for overwriting this + pll_usb = .{ + .refdiv = 1, + .vco_freq = 1_440_000_000, + .postdiv1 = 6, + .postdiv2 = 5, + }; + + break :adc_config .{ + .generator = .usb, + .input = .{ + .source = .pll_usb, + .freq = 48_000_000, + .src_value = srcValue(.adc, .pll_usb), + .auxsrc_value = auxSrcValue(.adc, .pll_usb), + }, + .output_freq = 48_000_000, + }; + } else null, .rtc = if (opts.rtc) |_| unreachable // TODO @@ -320,12 +438,13 @@ pub const GlobalConfiguration = struct { if (peri_opts.source == .src_xosc) xosc_configured = true; - // TODO break :peri_config .{ .generator = .peri, .input = .{ .source = peri_opts.source, .freq = xosc_freq, + .src_value = srcValue(.peri, peri_opts.source), + .auxsrc_value = auxSrcValue(.peri, peri_opts.source), }, .output_freq = xosc_freq, }; @@ -339,7 +458,7 @@ pub const GlobalConfiguration = struct { /// this is explicitly comptime to encourage the user to have separate /// clock configuration declarations instead of mutating them at runtime - pub fn apply(comptime config: GlobalConfiguration) !void { + pub fn apply(comptime config: GlobalConfiguration) void { // disable resus if it has been turned on elsewhere regs.CLOCKS.CLK_SYS_RESUS_CTRL.raw = 0; @@ -357,7 +476,7 @@ pub const GlobalConfiguration = struct { if (config.sys) |sys| switch (sys.input.source) { .pll_usb, .pll_sys => { regs.CLOCKS.CLK_SYS_CTRL.modify(.{ .SRC = 0 }); - while (regs.CLOCKS.CLK_SYS_SELECTED.* != 1) {} + while (regs.CLOCKS.CLK_SYS_SELECTED.* == 0) {} }, else => {}, }; @@ -365,27 +484,21 @@ pub const GlobalConfiguration = struct { if (config.ref) |ref| switch (ref.input.source) { .pll_usb, .pll_sys => { regs.CLOCKS.CLK_REF_CTRL.modify(.{ .SRC = 0 }); - while (regs.CLOCKS.CLK_REF_SELECTED.* != 1) {} + while (regs.CLOCKS.CLK_REF_SELECTED.* == 0) {} }, else => {}, }; - // initialize PLLs - if (config.pll_sys) |pll_sys_config| pll.sys.apply(pll_sys_config); - if (config.pll_usb) |pll_usb_config| pll.usb.apply(pll_usb_config); - - // initialize clock generators - if (config.ref) |ref| try ref.apply(); - if (config.usb) |usb| try usb.apply(); - if (config.adc) |adc| try adc.apply(); - if (config.rtc) |rtc| try rtc.apply(); - if (config.peri) |peri| try peri.apply(); - } + //// initialize PLLs + if (config.pll_sys) |pll_sys_config| pll.PLL.apply(.sys, pll_sys_config); + if (config.pll_usb) |pll_usb_config| pll.PLL.apply(.usb, pll_usb_config); - /// returns frequency of a clock or pll, if unconfigured it returns null - pub fn getFrequency(config: GlobalConfiguration) ?u32 { - _ = config; - return null; + //// initialize clock generators + if (config.ref) |ref| ref.apply(config.sys); + if (config.usb) |usb| usb.apply(config.sys); + if (config.adc) |adc| adc.apply(config.sys); + if (config.rtc) |rtc| rtc.apply(config.sys); + if (config.peri) |peri| peri.apply(config.sys); } }; @@ -393,19 +506,21 @@ pub const Configuration = struct { generator: Generator, input: struct { source: Source, + src_value: u32, + auxsrc_value: u32, freq: u32, }, output_freq: u32, - pub fn apply(config: Configuration) !void { + pub fn apply(comptime config: Configuration, comptime sys_config_opt: ?Configuration) void { const generator = config.generator; const input = config.input; const output_freq = config.output_freq; + const sys_config = sys_config_opt.?; // sys clock config needs to be set! + // source frequency has to be faster because dividing will always reduce. assert(input.freq >= output_freq); - if (output_freq < input.freq) - return error.InvalidArgs; const div = @intCast(u32, (@intCast(u64, input.freq) << 8) / 8); @@ -413,26 +528,47 @@ pub const Configuration = struct { if (div > generator.getDiv()) generator.setDiv(div); - if (generator.hasGlitchlessMux() and input.source == .src_aux) { - // TODO: clear bits - while (!generator.selected()) { - // TODO: is leaving this empty good enough? pico sdk has `tight_loop_contents()` - } + // TODO what _is_ an aux source? + if (generator.hasGlitchlessMux() and input.src_value == 1) { + generator.clearSource(); + while (!generator.selected()) {} } else { - // uh stuff + generator.disable(); + var delay_cycles = sys_config.output_freq / config.output_freq + 1; + asm volatile ( + \\1: + \\subs %[cycles], #1 + \\bne 1b + : [cycles] "=r" (delay_cycles), + ); } + generator.setAuxSource(input.auxsrc_value); + // set aux mux first and then glitchless mex if this clock has one if (generator.hasGlitchlessMux()) { - // write to clock ctrl + generator.setSource(input.src_value); while (!generator.selected()) {} } generator.enable(); generator.setDiv(div); - // should we store global state on configured clocks? } }; -//pub fn countFrequencyKhz(source: Source) u32 {} +pub fn countFrequencyKhz(source: Source, comptime clock_config: GlobalConfiguration) u32 { + const ref_freq = clock_config.ref.?.output_freq; + + // wait for counter to be done + while (CLOCKS.FC0_STATUS.read().RUNNING == 1) {} + CLOCKS.FC0_REF_KHZ.* = ref_freq / 1000; + CLOCKS.FC0_INTERVAL.* = 10; + CLOCKS.FC0_MIN_KHZ.* = 0; + CLOCKS.FC0_MAX_KHZ.* = std.math.maxInt(u32); + CLOCKS.FC0_SRC.* = @enumToInt(source); + + while (CLOCKS.FC0_STATUS.read().DONE != 1) {} + + return CLOCKS.FC0_RESULT.read().KHZ; +} diff --git a/src/hal/pll.zig b/src/hal/pll.zig index 16fb3086d..eb16a63a9 100644 --- a/src/hal/pll.zig +++ b/src/hal/pll.zig @@ -12,44 +12,36 @@ pub const Configuration = struct { postdiv2: u3, }; -pub const sys = @intToPtr(*volatile PLL, regs.PLL_SYS.base_address); -pub const usb = @intToPtr(*volatile PLL, regs.PLL_USB.base_address); - -pub const PLL = packed struct { - cs: @TypeOf(regs.PLL_SYS.CS), - pwr: @TypeOf(regs.PLL_SYS.PWR), - fbdiv_int: @TypeOf(regs.PLL_SYS.FBDIV_INT), - prim: @TypeOf(regs.PLL_SYS.PRIM), - - comptime { - // bunch of comptime checks in here to validate the layout - assert(0 == @bitOffsetOf(PLL, "cs")); - assert(32 == @bitOffsetOf(PLL, "pwr")); - assert(64 == @bitOffsetOf(PLL, "fbdiv_int")); - assert(96 == @bitOffsetOf(PLL, "prim")); - } +pub const PLL = enum { + sys, + usb, - pub fn isLocked(pll: *const volatile PLL) bool { - return pll.cs.read().LOCK == 1; + fn getRegs(pll: PLL) *volatile PllRegs { + return &plls[@enumToInt(pll)]; } - pub fn reset(pll: *const volatile PLL) void { + pub fn reset(pll: PLL) void { switch (pll) { - sys => { + .sys => { regs.RESETS.RESET.modify(.{ .pll_sys = 1 }); regs.RESETS.RESET.modify(.{ .pll_sys = 0 }); - while (regs.RESETS.RESET_DONE.read().pll_sys == 1) {} + while (regs.RESETS.RESET_DONE.read().pll_sys != 1) {} }, - usb => { + .usb => { regs.RESETS.RESET.modify(.{ .pll_usb = 1 }); regs.RESETS.RESET.modify(.{ .pll_usb = 0 }); - while (regs.RESETS.RESET_DONE.read().pll_usb == 1) {} + while (regs.RESETS.RESET_DONE.read().pll_usb != 1) {} }, - else => unreachable, } } - pub fn apply(pll: *volatile PLL, comptime config: Configuration) void { + pub fn isLocked(pll: PLL) bool { + const pll_regs = pll.getRegs(); + return pll_regs.cs.read().LOCK == 1; + } + + pub fn apply(pll: PLL, comptime config: Configuration) void { + const pll_regs = pll.getRegs(); const ref_freq = xosc_freq / @as(u32, config.refdiv); const fbdiv = @intCast(u12, config.vco_freq / ref_freq); @@ -67,10 +59,10 @@ pub const PLL = packed struct { // do not bother a PLL which is already configured if (pll.isLocked() and - config.refdiv == pll.cs.read().REFDIV and - fbdiv == pll.fbdiv_int.read() and - config.postdiv1 == pll.prim.read().POSTDIV1 and - config.postdiv2 == pll.prim.read().POSTDIV2) + config.refdiv == pll_regs.cs.read().REFDIV and + fbdiv == pll_regs.fbdiv_int.read() and + config.postdiv1 == pll_regs.prim.read().POSTDIV1 and + config.postdiv2 == pll_regs.prim.read().POSTDIV2) { return; } @@ -78,20 +70,39 @@ pub const PLL = packed struct { pll.reset(); // load vco related dividers - pll.cs.modify(.{ .REFDIV = config.refdiv }); - pll.fbdiv_int.modify(fbdiv); + pll_regs.cs.modify(.{ .REFDIV = config.refdiv }); + pll_regs.fbdiv_int.modify(fbdiv); // turn on PLL - pll.pwr.modify(.{ .PD = 0, .VCOPD = 0 }); + pll_regs.pwr.modify(.{ .PD = 0, .VCOPD = 0 }); // wait for PLL to lock while (!pll.isLocked()) {} - pll.prim.modify(.{ + pll_regs.prim.modify(.{ .POSTDIV1 = config.postdiv1, .POSTDIV2 = config.postdiv2, }); - pll.pwr.modify(.{ .POSTDIVPD = 0 }); + pll_regs.pwr.modify(.{ .POSTDIVPD = 0 }); } }; + +const plls = @intToPtr(*volatile [2]PllRegs, regs.PLL_SYS.base_address); +comptime { + assert(@sizeOf(PllRegs) == (regs.PLL_USB.base_address - regs.PLL_SYS.base_address)); +} + +const CsReg = @typeInfo(@TypeOf(regs.PLL_SYS.CS)).Pointer.child; +const PwrReg = @typeInfo(@TypeOf(regs.PLL_SYS.PWR)).Pointer.child; +const FbdivIntReg = @typeInfo(@TypeOf(regs.PLL_SYS.FBDIV_INT)).Pointer.child; +const PrimReg = @typeInfo(@TypeOf(regs.PLL_SYS.PRIM)).Pointer.child; + +pub const PllRegs = extern struct { + cs: CsReg, + pwr: PwrReg, + fbdiv_int: FbdivIntReg, + prim: PrimReg, + + padding: [4092]u32, +}; diff --git a/src/hal/util.zig b/src/hal/util.zig new file mode 100644 index 000000000..9d7863c17 --- /dev/null +++ b/src/hal/util.zig @@ -0,0 +1,18 @@ +pub fn xorAlias(ptr: anytype) @TypeOf(ptr) { + const xor_addr = @ptrToInt(ptr) | (1 << 12); + return @ptrCast(@TypeOf(ptr), xor_addr); +} + +pub fn setAlias(ptr: anytype) @TypeOf(ptr) { + const set_addr = @ptrToInt(ptr) | (2 << 12); + return @ptrCast(@TypeOf(ptr), set_addr); +} + +pub fn clearAlias(ptr: anytype) @TypeOf(ptr) { + const clear_addr = @ptrToInt(ptr) | (3 << 12); + return @ptrCast(@TypeOf(ptr), clear_addr); +} + +pub inline fn tightLoopContents() void { + asm volatile ("" ::: "memory"); +} From 2d894103050d2f58fbd5dafcf1a741d2eed0ed72 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 10 Jul 2022 17:10:54 -0700 Subject: [PATCH 009/286] add directive to inline asm (#6) --- src/hal/clocks.zig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/hal/clocks.zig b/src/hal/clocks.zig index fc28c1903..fef6e6150 100644 --- a/src/hal/clocks.zig +++ b/src/hal/clocks.zig @@ -536,6 +536,7 @@ pub const Configuration = struct { generator.disable(); var delay_cycles = sys_config.output_freq / config.output_freq + 1; asm volatile ( + \\.syntax unified \\1: \\subs %[cycles], #1 \\bne 1b From f75a019aa5e1bd915d1d9458df60f65908b156cb Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sun, 10 Jul 2022 17:31:17 -0700 Subject: [PATCH 010/286] try lf endings to fix windows compile error (#7) --- .gitattributes | 1 + 1 file changed, 1 insertion(+) create mode 100644 .gitattributes diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 000000000..ef01f6142 --- /dev/null +++ b/.gitattributes @@ -0,0 +1 @@ +*.zig text eol=lf From f0e51f8302904877c9ebc2ef2b689e4db37491c8 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Thu, 14 Jul 2022 00:09:47 -0700 Subject: [PATCH 011/286] Uart (#8) * refined clock configuration, uart works with clk_peri at xosc frequency * fix pll_sys configuration --- src/hal.zig | 20 +-- src/hal/clocks.zig | 424 ++++++++++++++++++++++++++------------------- src/hal/gpio.zig | 4 + src/hal/pll.zig | 22 ++- src/hal/uart.zig | 212 +++++++++++++++++++++++ src/rp2040.zig | 5 - 6 files changed, 482 insertions(+), 205 deletions(-) create mode 100644 src/hal/uart.zig diff --git a/src/hal.zig b/src/hal.zig index 3db067744..92539f374 100644 --- a/src/hal.zig +++ b/src/hal.zig @@ -1,25 +1,25 @@ const microzig = @import("microzig"); -const regs = microzig.chip.regsisters; +const regs = microzig.chip.registers; + pub const gpio = @import("hal/gpio.zig"); pub const clocks = @import("hal/clocks.zig"); pub const multicore = @import("hal/multicore.zig"); pub const time = @import("hal/time.zig"); +pub const uart = @import("hal/uart.zig"); pub const clock_config = clocks.GlobalConfiguration.init(.{ - .sys = .{ .source = .src_xosc }, + .sys = .{ + .source = .pll_sys, + .freq = 125_000_000, + }, + .ref = .{ .source = .src_xosc }, .peri = .{ .source = .clk_sys }, - //.sys = .{ - // .source = .pll_sys, - // .freq = 125_000_000, - //}, - //.usb = .{ .source = .pll_usb }, - //.adc = .{ .source = .pll_usb }, - //.rtc = .{ .source = .pll_usb }, - //.peri = .{ .source = .clk_sys }, }); pub fn init() void { + // TODO: resets need to be reviewed here clock_config.apply(); + gpio.reset(); } pub fn getCpuId() u32 { diff --git a/src/hal/clocks.zig b/src/hal/clocks.zig index fef6e6150..e81f1ea07 100644 --- a/src/hal/clocks.zig +++ b/src/hal/clocks.zig @@ -83,6 +83,10 @@ pub const Generator = enum { regs.CLOCKS.base_address, ); + fn getRegs(generator: Generator) *volatile GeneratorRegs { + return &generators[@enumToInt(generator)]; + } + pub fn hasGlitchlessMux(generator: Generator) bool { return switch (generator) { .sys, .ref => true, @@ -93,7 +97,7 @@ pub const Generator = enum { pub fn enable(generator: Generator) void { switch (generator) { .ref, .sys => {}, - else => generators[@enumToInt(generator)].ctrl |= (1 << 11), + else => generator.getRegs().ctrl |= (1 << 11), } } @@ -101,14 +105,14 @@ pub const Generator = enum { if (generator == .peri) return; - generators[@enumToInt(generator)].div = div; + generator.getRegs().div = div; } pub fn getDiv(generator: Generator) u32 { if (generator == .peri) return 1; - return generators[@enumToInt(generator)].div; + return generator.getRegs().div; } // The bitfields for the *_SELECTED registers are actually a mask of which @@ -118,17 +122,17 @@ pub const Generator = enum { // // Some mention that this is only for the glitchless mux, so if it is non-glitchless then return true pub fn selected(generator: Generator) bool { - return (0 != generators[@enumToInt(generator)].selected); + return (0 != generator.getRegs().selected); } pub fn clearSource(generator: Generator) void { - generators[@enumToInt(generator)].ctrl &= ~@as(u32, 0x3); + generator.getRegs().ctrl &= ~@as(u32, 0x3); } pub fn disable(generator: Generator) void { switch (generator) { .sys, .ref => {}, - else => generators[@enumToInt(generator)].ctrl &= ~@as(u32, 1 << 11), + else => generator.getRegs().ctrl &= ~@as(u32, 1 << 11), } } @@ -147,15 +151,17 @@ pub const Generator = enum { } pub fn setSource(generator: Generator, src: u32) void { + const gen_regs = generator.getRegs(); const mask = ~@as(u32, 0x3); - const ctrl_value = generators[@enumToInt(generator)].ctrl; - generators[@enumToInt(generator)].ctrl = (ctrl_value & mask) | src; + const ctrl_value = gen_regs.ctrl; + gen_regs.ctrl = (ctrl_value & mask) | src; } pub fn setAuxSource(generator: Generator, auxsrc: u32) void { + const gen_regs = generator.getRegs(); const mask = ~@as(u32, 0x1e0); - const ctrl_value = generators[@enumToInt(generator)].ctrl; - generators[@enumToInt(generator)].ctrl = (ctrl_value & mask) | (auxsrc << 5); + const ctrl_value = gen_regs.ctrl; + gen_regs.ctrl = (ctrl_value & mask) | (auxsrc << 5); } }; @@ -264,16 +270,20 @@ fn auxSrcValue(generator: Generator, source: Source) u32 { } pub const GlobalConfiguration = struct { - xosc_configured: bool, - sys: ?Configuration, - ref: ?Configuration, - usb: ?Configuration, - adc: ?Configuration, - rtc: ?Configuration, - peri: ?Configuration, - - pll_sys: ?pll.Configuration, - pll_usb: ?pll.Configuration, + xosc_configured: bool = false, + sys: ?Configuration = null, + ref: ?Configuration = null, + usb: ?Configuration = null, + adc: ?Configuration = null, + rtc: ?Configuration = null, + peri: ?Configuration = null, + gpout0: ?Configuration = null, + gpout1: ?Configuration = null, + gpout2: ?Configuration = null, + gpout3: ?Configuration = null, + + pll_sys: ?pll.Configuration = null, + pll_usb: ?pll.Configuration = null, pub const Option = struct { source: Source, @@ -287,173 +297,220 @@ pub const GlobalConfiguration = struct { adc: ?Option = null, rtc: ?Option = null, peri: ?Option = null, + gpout0: ?Option = null, + gpout1: ?Option = null, + gpout2: ?Option = null, + gpout3: ?Option = null, // TODO: allow user to configure PLLs to optimize for low-jitter, low-power, or manually specify }; + pub fn getFrequency(config: GlobalConfiguration, source: Source) ?u32 { + return switch (source) { + .src_xosc => xosc_freq, + .src_rosc => rosc_freq, + .clk_sys => if (config.sys) |sys_config| sys_config.output_freq else null, + .clk_usb => if (config.usb) |usb_config| usb_config.output_freq else null, + .clk_ref => if (config.ref) |ref_config| ref_config.output_freq else null, + .pll_sys => if (config.pll_sys) |pll_sys_config| pll_sys_config.frequency() else null, + .pll_usb => if (config.pll_usb) |pll_usb_config| pll_usb_config.frequency() else null, + else => null, + }; + } + /// this function reasons about how to configure the clock system. It will /// assert if the configuration is invalid pub fn init(comptime opts: Options) GlobalConfiguration { - var xosc_configured = false; - var pll_sys: ?pll.Configuration = null; - var pll_usb: ?pll.Configuration = null; - - return GlobalConfiguration{ - // the system clock can either use rosc, xosc, or the sys PLL - .sys = if (opts.sys) |sys_opts| sys_config: { - var output_freq: ?u32 = null; - break :sys_config .{ - .generator = .sys, - .input = switch (sys_opts.source) { - .src_rosc => input: { - output_freq = sys_opts.freq orelse rosc_freq; - assert(output_freq.? <= rosc_freq); - break :input .{ - .source = .src_rosc, - .freq = rosc_freq, - .src_value = srcValue(.sys, .src_rosc), - .auxsrc_value = auxSrcValue(.sys, .src_rosc), - }; - }, - .src_xosc => input: { - xosc_configured = true; - output_freq = sys_opts.freq orelse xosc_freq; - assert(output_freq.? <= xosc_freq); - break :input .{ - .source = .src_xosc, - .freq = xosc_freq, - .src_value = srcValue(.sys, .src_xosc), - .auxsrc_value = auxSrcValue(.sys, .src_xosc), - }; - }, - .pll_sys => input: { - xosc_configured = true; - output_freq = sys_opts.freq orelse 125_000_000; - assert(output_freq.? <= 125_000_000); - - // TODO: proper values for 125MHz - pll_sys = .{ - .refdiv = 2, - .vco_freq = 1_440_000_000, - .postdiv1 = 6, - .postdiv2 = 5, - }; - - break :input .{ - .source = .pll_sys, - // TODO: not really sure what frequency to - // drive pll at yet, but this is an okay start - .freq = 125_000_000, - .src_value = srcValue(.sys, .pll_sys), - .auxsrc_value = auxSrcValue(.sys, .pll_sys), - }; - }, - - else => unreachable, // not an available input + var config = GlobalConfiguration{}; + + // I THINK that if either pll is configured here, then that means + // that the ref clock generator MUST use xosc to feed the PLLs? + config.ref = if (opts.ref) |ref_opts| ref_config: { + assert(ref_opts.source == .src_xosc); + break :ref_config .{ + .generator = .ref, + .input = .{ + .source = ref_opts.source, + .freq = config.getFrequency(ref_opts.source).?, + .src_value = srcValue(.ref, ref_opts.source), + .auxsrc_value = auxSrcValue(.ref, ref_opts.source), + }, + .output_freq = config.getFrequency(ref_opts.source).?, + }; + } else if (config.pll_sys != null or config.pll_usb != null) ref_config: { + config.xosc_configured = true; + break :ref_config .{ + .generator = .ref, + .input = .{ + .source = .src_xosc, + .freq = xosc_freq, + .src_value = srcValue(.ref, .src_xosc), + .auxsrc_value = auxSrcValue(.ref, .src_xosc), + }, + .output_freq = xosc_freq, + }; + } else null; + + // the system clock can either use rosc, xosc, or the sys PLL + config.sys = if (opts.sys) |sys_opts| sys_config: { + var output_freq: ?u32 = null; + break :sys_config .{ + .generator = .sys, + .input = switch (sys_opts.source) { + .src_rosc => input: { + output_freq = sys_opts.freq orelse rosc_freq; + assert(output_freq.? <= rosc_freq); + break :input .{ + .source = .src_rosc, + .freq = rosc_freq, + .src_value = srcValue(.sys, .src_rosc), + .auxsrc_value = auxSrcValue(.sys, .src_rosc), + }; }, - .output_freq = output_freq.?, - }; - } else null, - - // to keep things simple for now, we'll make it so that the usb - // generator can only be hooked up to the usb PLL, and only have - // one configuration for the usb PLL - .usb = if (opts.usb) |usb_opts| usb_config: { - assert(pll_usb == null); - assert(usb_opts.source == .pll_usb); - - xosc_configured = true; - pll_usb = .{ - .refdiv = 1, - .vco_freq = 1_440_000_000, - .postdiv1 = 6, - .postdiv2 = 5, - }; - - break :usb_config .{ - .generator = .usb, - .input = .{ - .source = .pll_usb, - .freq = 48_000_000, - .src_value = srcValue(.usb, .pll_usb), - .auxsrc_value = auxSrcValue(.usb, .pll_usb), + .src_xosc => input: { + config.xosc_configured = true; + output_freq = sys_opts.freq orelse xosc_freq; + assert(output_freq.? <= xosc_freq); + break :input .{ + .source = .src_xosc, + .freq = xosc_freq, + .src_value = srcValue(.sys, .src_xosc), + .auxsrc_value = auxSrcValue(.sys, .src_xosc), + }; }, - .output_freq = 48_000_000, - }; - } else null, - - // I THINK that if either pll is configured here, then that means - // that the ref clock generator MUST use xosc to feed the PLLs? - .ref = if (opts.ref) |_| - unreachable // don't explicitly configure for now - else if (pll_sys != null or pll_usb != null) ref_config: { - xosc_configured = true; - break :ref_config .{ - .generator = .ref, - .input = .{ - .source = .src_xosc, - .freq = xosc_freq, - .src_value = srcValue(.ref, .src_xosc), - .auxsrc_value = auxSrcValue(.ref, .src_xosc), + .pll_sys => input: { + config.xosc_configured = true; + output_freq = sys_opts.freq orelse 125_000_000; + assert(output_freq.? == 125_000_000); // if using pll use 125MHz for now + + // TODO: proper values for 125MHz + config.pll_sys = .{ + .refdiv = 1, + .fbdiv = 125, + .postdiv1 = 6, + .postdiv2 = 2, + }; + + break :input .{ + .source = .pll_sys, + // TODO: not really sure what frequency to + // drive pll at yet, but this is an okay start + .freq = 125_000_000, + .src_value = srcValue(.sys, .pll_sys), + .auxsrc_value = auxSrcValue(.sys, .pll_sys), + }; }, - .output_freq = xosc_freq, - }; - } else null, - - // for the rest of the generators we'll make it so that they can - // either use the ROSC, XOSC, or sys PLL, with whatever dividing - // they need - // adc requires a 48MHz clock, so only ever let it get hooked up to - // the usb PLL - .adc = if (opts.adc) |adc_opts| adc_config: { - assert(adc_opts.source == .pll_usb); - xosc_configured = true; + else => unreachable, // not an available input + }, + .output_freq = output_freq.?, + }; + } else null; + + // to keep things simple for now, we'll make it so that the usb + // generator can only be hooked up to the usb PLL, and only have + // one configuration for the usb PLL + config.usb = if (opts.usb) |usb_opts| usb_config: { + assert(config.pll_usb == null); + assert(usb_opts.source == .pll_usb); + + config.xosc_configured = true; + config.pll_usb = .{ + .refdiv = 1, + .fbdiv = 40, + .postdiv1 = 5, + .postdiv2 = 2, + }; - // TODO: some safety checks for overwriting this - pll_usb = .{ + break :usb_config .{ + .generator = .usb, + .input = .{ + .source = .pll_usb, + .freq = 48_000_000, + .src_value = srcValue(.usb, .pll_usb), + .auxsrc_value = auxSrcValue(.usb, .pll_usb), + }, + .output_freq = 48_000_000, + }; + } else null; + + // for the rest of the generators we'll make it so that they can + // either use the ROSC, XOSC, or sys PLL, with whatever dividing + // they need + + // adc requires a 48MHz clock, so only ever let it get hooked up to + // the usb PLL + config.adc = if (opts.adc) |adc_opts| adc_config: { + assert(adc_opts.source == .pll_usb); + config.xosc_configured = true; + + // TODO: some safety checks for overwriting this + if (config.pll_usb) |pll_usb| { + assert(pll_usb.refdiv == 1); + assert(pll_usb.fbdiv == 40); + assert(pll_usb.postdiv1 == 5); + assert(pll_usb.postdiv2 == 2); + } else { + config.pll_usb = .{ .refdiv = 1, - .vco_freq = 1_440_000_000, - .postdiv1 = 6, - .postdiv2 = 5, - }; - - break :adc_config .{ - .generator = .usb, - .input = .{ - .source = .pll_usb, - .freq = 48_000_000, - .src_value = srcValue(.adc, .pll_usb), - .auxsrc_value = auxSrcValue(.adc, .pll_usb), - }, - .output_freq = 48_000_000, + .fbdiv = 40, + .postdiv1 = 5, + .postdiv2 = 2, }; - } else null, - - .rtc = if (opts.rtc) |_| - unreachable // TODO + } + + break :adc_config .{ + .generator = .usb, + .input = .{ + .source = .pll_usb, + .freq = 48_000_000, + .src_value = srcValue(.adc, .pll_usb), + .auxsrc_value = auxSrcValue(.adc, .pll_usb), + }, + .output_freq = 48_000_000, + }; + } else null; + + config.rtc = if (opts.rtc) |_| + unreachable // TODO + else + null; + + config.peri = if (opts.peri) |peri_opts| peri_config: { + if (peri_opts.source == .src_xosc) + config.xosc_configured = true; + + break :peri_config .{ + .generator = .peri, + .input = .{ + .source = peri_opts.source, + .freq = config.getFrequency(peri_opts.source) orelse + @compileError("you need to configure the source: " ++ @tagName(peri_opts.source)), + .src_value = srcValue(.peri, peri_opts.source), + .auxsrc_value = auxSrcValue(.peri, peri_opts.source), + }, + .output_freq = if (peri_opts.freq) |output_freq| + output_freq + else + config.getFrequency(peri_opts.source).?, + }; + } else null; + + config.gpout0 = if (opts.gpout0) |gpout0_opts| .{ + .generator = .gpout0, + .input = .{ + .source = gpout0_opts.source, + .freq = config.getFrequency(gpout0_opts.source) orelse + @compileError("you need to configure the source: " ++ @tagName(gpout0_opts.source)), + .src_value = srcValue(.gpout0, gpout0_opts.source), + .auxsrc_value = auxSrcValue(.gpout0, gpout0_opts.source), + }, + .output_freq = if (gpout0_opts.freq) |output_freq| + output_freq else - null, - - .peri = if (opts.peri) |peri_opts| peri_config: { - if (peri_opts.source == .src_xosc) - xosc_configured = true; - - break :peri_config .{ - .generator = .peri, - .input = .{ - .source = peri_opts.source, - .freq = xosc_freq, - .src_value = srcValue(.peri, peri_opts.source), - .auxsrc_value = auxSrcValue(.peri, peri_opts.source), - }, - .output_freq = xosc_freq, - }; - } else null, + config.getFrequency(gpout0_opts.source).?, + } else null; - .xosc_configured = xosc_configured, - .pll_sys = pll_sys, - .pll_usb = pll_usb, - }; + return config; } /// this is explicitly comptime to encourage the user to have separate @@ -476,7 +533,7 @@ pub const GlobalConfiguration = struct { if (config.sys) |sys| switch (sys.input.source) { .pll_usb, .pll_sys => { regs.CLOCKS.CLK_SYS_CTRL.modify(.{ .SRC = 0 }); - while (regs.CLOCKS.CLK_SYS_SELECTED.* == 0) {} + while (!Generator.sys.selected()) {} }, else => {}, }; @@ -484,7 +541,7 @@ pub const GlobalConfiguration = struct { if (config.ref) |ref| switch (ref.input.source) { .pll_usb, .pll_sys => { regs.CLOCKS.CLK_REF_CTRL.modify(.{ .SRC = 0 }); - while (regs.CLOCKS.CLK_REF_SELECTED.* == 0) {} + while (!Generator.ref.selected()) {} }, else => {}, }; @@ -495,10 +552,15 @@ pub const GlobalConfiguration = struct { //// initialize clock generators if (config.ref) |ref| ref.apply(config.sys); + if (config.sys) |sys| sys.apply(config.sys); if (config.usb) |usb| usb.apply(config.sys); if (config.adc) |adc| adc.apply(config.sys); if (config.rtc) |rtc| rtc.apply(config.sys); if (config.peri) |peri| peri.apply(config.sys); + if (config.gpout0) |gpout0| gpout0.apply(config.sys); + if (config.gpout1) |gpout1| gpout1.apply(config.sys); + if (config.gpout2) |gpout2| gpout2.apply(config.sys); + if (config.gpout3) |gpout3| gpout3.apply(config.sys); } }; @@ -522,13 +584,12 @@ pub const Configuration = struct { // source frequency has to be faster because dividing will always reduce. assert(input.freq >= output_freq); - const div = @intCast(u32, (@intCast(u64, input.freq) << 8) / 8); + const div = @intCast(u32, (@intCast(u64, input.freq) << 8) / output_freq); // check divisor if (div > generator.getDiv()) generator.setDiv(div); - // TODO what _is_ an aux source? if (generator.hasGlitchlessMux() and input.src_value == 1) { generator.clearSource(); while (!generator.selected()) {} @@ -557,17 +618,18 @@ pub const Configuration = struct { } }; +// NOTE: untested pub fn countFrequencyKhz(source: Source, comptime clock_config: GlobalConfiguration) u32 { const ref_freq = clock_config.ref.?.output_freq; // wait for counter to be done while (CLOCKS.FC0_STATUS.read().RUNNING == 1) {} - CLOCKS.FC0_REF_KHZ.* = ref_freq / 1000; - CLOCKS.FC0_INTERVAL.* = 10; - CLOCKS.FC0_MIN_KHZ.* = 0; - CLOCKS.FC0_MAX_KHZ.* = std.math.maxInt(u32); - CLOCKS.FC0_SRC.* = @enumToInt(source); + CLOCKS.FC0_REF_KHZ.raw = ref_freq / 1000; + CLOCKS.FC0_INTERVAL.raw = 10; + CLOCKS.FC0_MIN_KHZ.raw = 0; + CLOCKS.FC0_MAX_KHZ.raw = std.math.maxInt(u32); + CLOCKS.FC0_SRC.raw = @enumToInt(source); while (CLOCKS.FC0_STATUS.read().DONE != 1) {} diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig index 416b1559c..1aa0e6b45 100644 --- a/src/hal/gpio.zig +++ b/src/hal/gpio.zig @@ -131,6 +131,10 @@ pub inline fn put(comptime gpio: u32, value: u1) void { } } +pub inline fn toggle(comptime gpio: u32) void { + regs.SIO.GPIO_OUT_XOR.raw = (1 << gpio); +} + pub inline fn setFunction(comptime gpio: u32, function: Function) void { const pad_bank_reg = comptime std.fmt.comptimePrint("GPIO{}", .{gpio}); @field(regs.PADS_BANK0, pad_bank_reg).modify(.{ diff --git a/src/hal/pll.zig b/src/hal/pll.zig index eb16a63a9..4481abded 100644 --- a/src/hal/pll.zig +++ b/src/hal/pll.zig @@ -7,9 +7,13 @@ const xosc_freq = microzig.board.xosc_freq; pub const Configuration = struct { refdiv: u6, - vco_freq: u32, + fbdiv: u32, postdiv1: u3, postdiv2: u3, + + pub fn frequency(config: Configuration) u32 { + return @as(u32, xosc_freq) / config.refdiv * config.fbdiv / config.postdiv1 / config.postdiv2; + } }; pub const PLL = enum { @@ -41,15 +45,15 @@ pub const PLL = enum { } pub fn apply(pll: PLL, comptime config: Configuration) void { - const pll_regs = pll.getRegs(); - const ref_freq = xosc_freq / @as(u32, config.refdiv); - const fbdiv = @intCast(u12, config.vco_freq / ref_freq); - - assert(fbdiv >= 16 and fbdiv <= 320); + assert(config.fbdiv >= 16 and config.fbdiv <= 320); assert(config.postdiv1 >= 1 and config.postdiv1 <= 7); assert(config.postdiv2 >= 1 and config.postdiv2 <= 7); assert(config.postdiv2 <= config.postdiv1); - assert(ref_freq <= config.vco_freq / 16); + + const pll_regs = pll.getRegs(); + const ref_freq = xosc_freq / @as(u32, config.refdiv); + const vco_freq = ref_freq * config.fbdiv; + assert(ref_freq <= vco_freq / 16); // 1. program reference clock divider // 2. program feedback divider @@ -60,7 +64,7 @@ pub const PLL = enum { // do not bother a PLL which is already configured if (pll.isLocked() and config.refdiv == pll_regs.cs.read().REFDIV and - fbdiv == pll_regs.fbdiv_int.read() and + config.fbdiv == pll_regs.fbdiv_int.read() and config.postdiv1 == pll_regs.prim.read().POSTDIV1 and config.postdiv2 == pll_regs.prim.read().POSTDIV2) { @@ -71,7 +75,7 @@ pub const PLL = enum { // load vco related dividers pll_regs.cs.modify(.{ .REFDIV = config.refdiv }); - pll_regs.fbdiv_int.modify(fbdiv); + pll_regs.fbdiv_int.modify(config.fbdiv); // turn on PLL pll_regs.pwr.modify(.{ .PD = 0, .VCOPD = 0 }); diff --git a/src/hal/uart.zig b/src/hal/uart.zig new file mode 100644 index 000000000..18163992f --- /dev/null +++ b/src/hal/uart.zig @@ -0,0 +1,212 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const gpio = @import("gpio.zig"); +const clocks = @import("clocks.zig"); + +const assert = std.debug.assert; +const regs = microzig.chip.registers; + +pub const WordBits = enum { + five, + six, + seven, + eight, +}; + +pub const StopBits = enum { + one, + two, +}; + +pub const Parity = enum { + none, + even, + odd, +}; + +pub const Config = struct { + clock_config: clocks.GlobalConfiguration, + tx_pin: u32, + rx_pin: u32, + baud_rate: u32, + word_bits: WordBits = .eight, + stop_bits: StopBits = .one, + parity: Parity = .none, +}; + +pub const UartRegs = extern struct { + dr: u32, + rsr: u32, + reserved0: [4]u32, + fr: @typeInfo(@TypeOf(regs.UART0.UARTFR)).Pointer.child, + resertev1: [1]u32, + ilpr: u32, + ibrd: u32, + fbrd: u32, + lcr_h: @typeInfo(@TypeOf(regs.UART0.UARTLCR_H)).Pointer.child, + cr: @typeInfo(@TypeOf(regs.UART0.UARTCR)).Pointer.child, + ifls: u32, + imsc: u32, + ris: u32, + mis: u32, + icr: u32, + dmacr: @typeInfo(@TypeOf(regs.UART0.UARTDMACR)).Pointer.child, + periphid0: u32, + periphid1: u32, + periphid2: u32, + periphid3: u32, + cellid0: u32, + cellid1: u32, + cellid2: u32, + cellid3: u32, + + padding: [4069]u32, +}; + +const uarts = @intToPtr(*volatile [2]UartRegs, regs.UART0.base_address); +comptime { + assert(@sizeOf(UartRegs) == (regs.UART1.base_address - regs.UART0.base_address)); +} + +pub const UART = enum { + uart0, + uart1, + + const WriteError = error{}; + pub const Writer = std.io.Writer(UART, WriteError, write); + + pub fn writer(uart: UART) Writer { + return .{ .context = uart }; + } + + fn getRegs(uart: UART) *volatile UartRegs { + return &uarts[@enumToInt(uart)]; + } + + pub fn init(comptime id: u32, comptime config: Config) UART { + const uart: UART = switch (id) { + 0 => .uart0, + 1 => .uart1, + else => @compileError("there is only uart0 and uart1"), + }; + + assert(config.baud_rate > 0); + + uart.reset(); + + const uart_regs = uart.getRegs(); + const peri_freq = config.clock_config.peri.?.output_freq; + uart.setBaudRate(config.baud_rate, peri_freq); + uart.setFormat(config.word_bits, config.stop_bits, config.parity); + + uart_regs.cr.modify(.{ + .UARTEN = 1, + .TXE = 1, + .RXE = 1, + }); + + uart_regs.lcr_h.modify(.{ .FEN = 1 }); + + // - always enable DREQ signals -- no harm if dma isn't listening + uart_regs.dmacr.modify(.{ + .TXDMAE = 1, + .RXDMAE = 1, + }); + + // TODO comptime assertions + gpio.setFunction(config.tx_pin, .uart); + gpio.setFunction(config.rx_pin, .uart); + + return uart; + } + + pub fn isReadable(uart: UART) bool { + return (0 == uart.getRegs().fr.read().RXFE); + } + + pub fn isWritable(uart: UART) bool { + return (0 == uart.getRegs().fr.read().TXFF); + } + + // TODO: implement tx fifo + pub fn write(uart: UART, payload: []const u8) WriteError!usize { + const uart_regs = uart.getRegs(); + for (payload) |byte| { + while (!uart.isWritable()) {} + + uart_regs.dr = byte; + } + + return payload.len; + } + + pub fn readWord(uart: UART) u8 { + const uart_regs = uart.getRegs(); + while (!uart.isReadable()) {} + + return @truncate(u8, uart_regs.dr); + } + + pub fn reset(uart: UART) void { + switch (uart) { + .uart0 => { + regs.RESETS.RESET.modify(.{ .uart0 = 1 }); + regs.RESETS.RESET.modify(.{ .uart0 = 0 }); + while (regs.RESETS.RESET_DONE.read().uart0 != 1) {} + }, + .uart1 => { + regs.RESETS.RESET.modify(.{ .uart1 = 1 }); + regs.RESETS.RESET.modify(.{ .uart1 = 0 }); + while (regs.RESETS.RESET_DONE.read().uart1 != 1) {} + }, + } + } + + pub fn setFormat( + uart: UART, + word_bits: WordBits, + stop_bits: StopBits, + parity: Parity, + ) void { + const uart_regs = uart.getRegs(); + uart_regs.lcr_h.modify(.{ + .WLEN = switch (word_bits) { + .eight => @as(u2, 0b11), + .seven => @as(u2, 0b10), + .six => @as(u2, 0b01), + .five => @as(u2, 0b00), + }, + .STP2 = switch (stop_bits) { + .one => @as(u1, 0), + .two => @as(u1, 1), + }, + .PEN = if (parity != .none) @as(u1, 1) else @as(u1, 0), + .EPS = switch (parity) { + .even => @as(u1, 1), + .odd => @as(u1, 0), + else => @as(u1, 0), + }, + }); + } + + fn setBaudRate(uart: UART, baud_rate: u32, peri_freq: u32) void { + assert(baud_rate > 0); + const uart_regs = uart.getRegs(); + const baud_rate_div = (8 * peri_freq / baud_rate); + var baud_ibrd = baud_rate_div >> 7; + + const baud_fbrd = if (baud_ibrd == 0) baud_fbrd: { + baud_ibrd = 1; + break :baud_fbrd 0; + } else if (baud_ibrd >= 65535) baud_fbrd: { + baud_ibrd = 65535; + break :baud_fbrd 0; + } else ((baud_rate_div & 0x7f) + 1) / 2; + + uart_regs.ibrd = baud_ibrd; + uart_regs.fbrd = baud_fbrd; + + // just want a write, don't want to change these values + uart_regs.lcr_h.modify(.{}); + } +}; diff --git a/src/rp2040.zig b/src/rp2040.zig index e96b90134..571b6489e 100644 --- a/src/rp2040.zig +++ b/src/rp2040.zig @@ -44,14 +44,12 @@ pub const VectorTable = extern struct { }; pub const registers = struct { - /// System Control Space pub const SCS = struct { pub const base_address = 0xe000e000; /// System Tick Timer pub const SysTick = struct { - /// address: 0xe000e010 /// SysTick Control and Status Register pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct { @@ -134,7 +132,6 @@ pub const registers = struct { /// Nested Vectored Interrupt Controller pub const NVIC = struct { - /// address: 0xe000e100 /// Interrupt Set Enable Register pub const ISER = @intToPtr(*volatile u32, base_address + 0x100); @@ -158,7 +155,6 @@ pub const registers = struct { /// System Control Block pub const SCB = struct { - /// address: 0xe000ed00 pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { REVISION: u4, @@ -343,7 +339,6 @@ pub const registers = struct { /// Memory Protection Unit pub const MPU = struct { - /// address: 0xe000ed90 /// MPU Type Register pub const TYPE = @intToPtr(*volatile Mmio(32, packed struct { From 1dd837ae43a4cc4943e9753684ea5e620745c746 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 1 Aug 2022 00:26:02 -0700 Subject: [PATCH 012/286] Initial commit --- LICENSE | 21 +++++++++++++++++++++ README.md | 2 ++ 2 files changed, 23 insertions(+) create mode 100644 LICENSE create mode 100644 README.md diff --git a/LICENSE b/LICENSE new file mode 100644 index 000000000..4818f98dd --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2022 Zig Embedded Group + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/README.md b/README.md new file mode 100644 index 000000000..88015b53c --- /dev/null +++ b/README.md @@ -0,0 +1,2 @@ +# stm32 +HAL for stm32 (STMicro) devices From 2ae5eb6d028328a75cd9af9ed7e6214d572b73f3 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 1 Aug 2022 00:27:17 -0700 Subject: [PATCH 013/286] init with empty test --- README.md => README.adoc | 3 ++- tests/stm32f103.robot | 10 ++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) rename README.md => README.adoc (78%) create mode 100644 tests/stm32f103.robot diff --git a/README.md b/README.adoc similarity index 78% rename from README.md rename to README.adoc index 88015b53c..df1b5ccb9 100644 --- a/README.md +++ b/README.adoc @@ -1,2 +1,3 @@ -# stm32 += stm32 + HAL for stm32 (STMicro) devices diff --git a/tests/stm32f103.robot b/tests/stm32f103.robot new file mode 100644 index 000000000..28c77fe96 --- /dev/null +++ b/tests/stm32f103.robot @@ -0,0 +1,10 @@ +*** Settings *** +Suite Setup Setup +Suite Teardown Teardown +Test Teardown Test Teardown +Resource ${RENODEKEYWORDS} + +*** Test Cases *** +Should Print Help + ${x}= Execute Command help + Should Contain ${x} Available commands: From a6f532476962b11f5dc6ceb4be52e8e5907dba96 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Mon, 1 Aug 2022 00:34:39 -0700 Subject: [PATCH 014/286] add list of boards in renode --- README.adoc | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/README.adoc b/README.adoc index df1b5ccb9..d3f2f4097 100644 --- a/README.adoc +++ b/README.adoc @@ -1,3 +1,10 @@ = stm32 HAL for stm32 (STMicro) devices + +== stm32 boards that renode supports: + +- blue pill (stm32f103) +- nucleo 64 (stm32f103) +- f4 discovery +- f7 discovery From 9fa748ff13982950a58fb4ce45815ac5556f1fcc Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 2 Sep 2022 14:45:21 -0700 Subject: [PATCH 015/286] Pin config (#9) * pin config * wip * wip * try some experimental pwm stuff --- build.zig | 27 +-- src/hal.zig | 9 +- src/hal/clocks.zig | 48 ++++- src/hal/gpio.zig | 45 +---- src/hal/pins.zig | 438 +++++++++++++++++++++++++++++++++++++++++++++ src/hal/pll.zig | 3 + src/hal/pwm.zig | 116 ++++++++++++ src/hal/resets.zig | 47 +++++ 8 files changed, 668 insertions(+), 65 deletions(-) create mode 100644 src/hal/pins.zig create mode 100644 src/hal/pwm.zig create mode 100644 src/hal/resets.zig diff --git a/build.zig b/build.zig index 7bf7beaf8..f4675dddd 100644 --- a/build.zig +++ b/build.zig @@ -2,21 +2,25 @@ const std = @import("std"); const Builder = std.build.Builder; const Pkg = std.build.Pkg; +const comptimePrint = std.fmt.comptimePrint; -pub const BuildOptions = struct { - packages: ?[]const Pkg = null, -}; +const chip_path = comptimePrint("{s}/src/rp2040.zig", .{root()}); +const board_path = comptimePrint("{s}/src/raspberry_pi_pico.zig", .{root()}); +const hal_path = comptimePrint("{s}/src/hal.zig", .{root()}); +const linkerscript_path = comptimePrint("{s}/rp2040.ld", .{root()}); + +pub const BuildOptions = struct {}; pub fn addPiPicoExecutable( comptime microzig: type, builder: *Builder, name: []const u8, source: []const u8, - options: BuildOptions, -) *std.build.LibExeObjStep { + _: BuildOptions, +) microzig.EmbeddedExecutable { const rp2040 = microzig.Chip{ .name = "RP2040", - .path = root() ++ "src/rp2040.zig", + .path = chip_path, .cpu = microzig.cpus.cortex_m0plus, .memory_regions = &.{ .{ .kind = .flash, .offset = 0x10000100, .length = (2048 * 1024) - 256 }, @@ -27,7 +31,7 @@ pub fn addPiPicoExecutable( const raspberry_pi_pico = microzig.Board{ .name = "Raspberry Pi Pico", - .path = root() ++ "src/raspberry_pi_pico.zig", + .path = board_path, .chip = rp2040, }; @@ -37,15 +41,14 @@ pub fn addPiPicoExecutable( source, .{ .board = raspberry_pi_pico }, .{ - .packages = options.packages, - .hal_package_path = .{ .path = root() ++ "src/hal.zig" }, + .hal_package_path = .{ .path = hal_path }, }, - ) catch @panic("failed to create embedded executable"); - ret.setLinkerScriptPath(.{ .path = root() ++ "rp2040.ld" }); + ); + ret.inner.setLinkerScriptPath(.{ .path = linkerscript_path }); return ret; } fn root() []const u8 { - return (std.fs.path.dirname(@src().file) orelse unreachable) ++ "/"; + return std.fs.path.dirname(@src().file) orelse "."; } diff --git a/src/hal.zig b/src/hal.zig index 92539f374..1dc50e6b0 100644 --- a/src/hal.zig +++ b/src/hal.zig @@ -1,25 +1,28 @@ const microzig = @import("microzig"); const regs = microzig.chip.registers; +pub const pins = @import("hal/pins.zig"); pub const gpio = @import("hal/gpio.zig"); pub const clocks = @import("hal/clocks.zig"); pub const multicore = @import("hal/multicore.zig"); pub const time = @import("hal/time.zig"); pub const uart = @import("hal/uart.zig"); +pub const pwm = @import("hal/pwm.zig"); pub const clock_config = clocks.GlobalConfiguration.init(.{ + .ref = .{ .source = .src_xosc }, .sys = .{ .source = .pll_sys, .freq = 125_000_000, }, - .ref = .{ .source = .src_xosc }, .peri = .{ .source = .clk_sys }, + .usb = .{ .source = .pll_usb }, + .adc = .{ .source = .pll_usb }, + .rtc = .{ .source = .pll_usb }, }); pub fn init() void { - // TODO: resets need to be reviewed here clock_config.apply(); - gpio.reset(); } pub fn getCpuId() u32 { diff --git a/src/hal/clocks.zig b/src/hal/clocks.zig index e81f1ea07..3553572cf 100644 --- a/src/hal/clocks.zig +++ b/src/hal/clocks.zig @@ -4,6 +4,9 @@ const pll = @import("pll.zig"); const util = @import("util.zig"); const assert = std.debug.assert; +// TODO: remove +const gpio = @import("gpio.zig"); + const regs = microzig.chip.registers; const CLOCKS = regs.CLOCKS; const xosc_freq = microzig.board.xosc_freq; @@ -470,10 +473,36 @@ pub const GlobalConfiguration = struct { }; } else null; - config.rtc = if (opts.rtc) |_| - unreachable // TODO - else - null; + config.rtc = if (opts.rtc) |rtc_opts| rtc_config: { + assert(rtc_opts.source == .pll_usb); + config.xosc_configured = true; + + // TODO: some safety checks for overwriting this + if (config.pll_usb) |pll_usb| { + assert(pll_usb.refdiv == 1); + assert(pll_usb.fbdiv == 40); + assert(pll_usb.postdiv1 == 5); + assert(pll_usb.postdiv2 == 2); + } else { + config.pll_usb = .{ + .refdiv = 1, + .fbdiv = 40, + .postdiv1 = 5, + .postdiv2 = 2, + }; + } + + break :rtc_config .{ + .generator = .usb, + .input = .{ + .source = .pll_usb, + .freq = 48_000_000, + .src_value = srcValue(.rtc, .pll_usb), + .auxsrc_value = auxSrcValue(.rtc, .pll_usb), + }, + .output_freq = 48_000_000, + }; + } else null; config.peri = if (opts.peri) |peri_opts| peri_config: { if (peri_opts.source == .src_xosc) @@ -557,6 +586,7 @@ pub const GlobalConfiguration = struct { if (config.adc) |adc| adc.apply(config.sys); if (config.rtc) |rtc| rtc.apply(config.sys); if (config.peri) |peri| peri.apply(config.sys); + if (config.gpout0) |gpout0| gpout0.apply(config.sys); if (config.gpout1) |gpout1| gpout1.apply(config.sys); if (config.gpout2) |gpout2| gpout2.apply(config.sys); @@ -592,16 +622,20 @@ pub const Configuration = struct { if (generator.hasGlitchlessMux() and input.src_value == 1) { generator.clearSource(); + while (!generator.selected()) {} } else { generator.disable(); - var delay_cycles = sys_config.output_freq / config.output_freq + 1; + const delay_cycles: u32 = sys_config.output_freq / config.output_freq + 1; asm volatile ( \\.syntax unified + \\movs r1, %[cycles] \\1: - \\subs %[cycles], #1 + \\subs r1, #1 \\bne 1b - : [cycles] "=r" (delay_cycles), + : + : [cycles] "i" (delay_cycles), + : "{r1}" ); } diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig index 1aa0e6b45..ec48f114b 100644 --- a/src/hal/gpio.zig +++ b/src/hal/gpio.zig @@ -1,40 +1,6 @@ -//! ### Function Select Table -//! -//! GPIO | F1 | F2 | F3 | F4 | F5 | F6 | F7 | F8 | F9 -//! -------|----------|-----------|----------|--------|-----|------|------|---------------|---- -//! 0 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB OVCUR DET -//! 1 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS DET -//! 2 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB VBUS EN -//! 3 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB OVCUR DET -//! 4 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | | USB VBUS DET -//! 5 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | | USB VBUS EN -//! 6 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | | USB OVCUR DET -//! 7 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | | USB VBUS DET -//! 8 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | | USB VBUS EN -//! 9 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | | USB OVCUR DET -//! 10 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS DET -//! 11 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB VBUS EN -//! 12 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB OVCUR DET -//! 13 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS DET -//! 14 | SPI1 SCK | UART0 CTS | I2C1 SDA | PWM7 A | SIO | PIO0 | PIO1 | | USB VBUS EN -//! 15 | SPI1 TX | UART0 RTS | I2C1 SCL | PWM7 B | SIO | PIO0 | PIO1 | | USB OVCUR DET -//! 16 | SPI0 RX | UART0 TX | I2C0 SDA | PWM0 A | SIO | PIO0 | PIO1 | | USB VBUS DET -//! 17 | SPI0 CSn | UART0 RX | I2C0 SCL | PWM0 B | SIO | PIO0 | PIO1 | | USB VBUS EN -//! 18 | SPI0 SCK | UART0 CTS | I2C1 SDA | PWM1 A | SIO | PIO0 | PIO1 | | USB OVCUR DET -//! 19 | SPI0 TX | UART0 RTS | I2C1 SCL | PWM1 B | SIO | PIO0 | PIO1 | | USB VBUS DET -//! 20 | SPI0 RX | UART1 TX | I2C0 SDA | PWM2 A | SIO | PIO0 | PIO1 | CLOCK GPIN0 | USB VBUS EN -//! 21 | SPI0 CSn | UART1 RX | I2C0 SCL | PWM2 B | SIO | PIO0 | PIO1 | CLOCK GPOUT0 | USB OVCUR DET -//! 22 | SPI0 SCK | UART1 CTS | I2C1 SDA | PWM3 A | SIO | PIO0 | PIO1 | CLOCK GPIN1 | USB VBUS DET -//! 23 | SPI0 TX | UART1 RTS | I2C1 SCL | PWM3 B | SIO | PIO0 | PIO1 | CLOCK GPOUT1 | USB VBUS EN -//! 24 | SPI1 RX | UART1 TX | I2C0 SDA | PWM4 A | SIO | PIO0 | PIO1 | CLOCK GPOUT2 | USB OVCUR DET -//! 25 | SPI1 CSn | UART1 RX | I2C0 SCL | PWM4 B | SIO | PIO0 | PIO1 | CLOCK GPOUT3 | USB VBUS DET -//! 26 | SPI1 SCK | UART1 CTS | I2C1 SDA | PWM5 A | SIO | PIO0 | PIO1 | | USB VBUS EN -//! 27 | SPI1 TX | UART1 RTS | I2C1 SCL | PWM5 B | SIO | PIO0 | PIO1 | | USB OVCUR DET -//! 28 | SPI1 RX | UART0 TX | I2C0 SDA | PWM6 A | SIO | PIO0 | PIO1 | | USB VBUS DET -//! 29 | SPI1 CSn | UART0 RX | I2C0 SCL | PWM6 B | SIO | PIO0 | PIO1 | | USB VBUS EN - const std = @import("std"); const microzig = @import("microzig"); +const resets = @import("resets.zig"); const regs = microzig.chip.registers; const assert = std.debug.assert; @@ -91,14 +57,7 @@ pub const Enabled = enum { }; pub inline fn reset() void { - regs.RESETS.RESET.modify(.{ .io_bank0 = 1, .pads_bank0 = 1 }); - regs.RESETS.RESET.modify(.{ .io_bank0 = 0, .pads_bank0 = 0 }); - - while (true) { - const reset_done = regs.RESETS.RESET_DONE.read(); - if (reset_done.io_bank0 == 1 and reset_done.pads_bank0 == 1) - break; - } + resets.reset(&.{ .io_bank0, .pads_bank0 }); } /// Initialize a GPIO, set func to SIO diff --git a/src/hal/pins.zig b/src/hal/pins.zig new file mode 100644 index 000000000..ed075944b --- /dev/null +++ b/src/hal/pins.zig @@ -0,0 +1,438 @@ +const std = @import("std"); +const gpio = @import("gpio.zig"); +const pwm = @import("pwm.zig"); +const regs = @import("microzig").chip.registers; + +const assert = std.debug.assert; +const comptimePrint = std.fmt.comptimePrint; +const StructField = std.builtin.TypeInfo.StructField; + +pub const Pin = enum { + GPIO0, + GPIO1, + GPIO2, + GPIO3, + GPIO4, + GPIO5, + GPIO6, + GPIO7, + GPIO8, + GPIO9, + GPIO10, + GPIO11, + GPIO12, + GPIO13, + GPIO14, + GPIO15, + GPIO16, + GPIO17, + GPIO18, + GPIO19, + GPIO20, + GPIO21, + GPIO22, + GPIO23, + GPIO24, + GPIO25, + GPIO26, + GPIO27, + GPIO28, + GPIO29, + + pub const Configuration = struct { + name: ?[]const u8 = null, + function: Function = .SIO, + direction: ?gpio.Direction = null, + drive_strength: ?gpio.DriveStrength = null, + pull: ?enum { up, down } = null, + slew_rate: ?gpio.SlewRate = null, + // input/output enable + // schmitt trigger + // hysteresis + + pub fn getDirection(config: Configuration) gpio.Direction { + return if (config.direction) |direction| + direction + else if (config.function.isPwm()) + .out + else + @panic("TODO"); + } + }; +}; + +pub const Function = enum { + SIO, + + PIO0, + PIO1, + + SPI0_RX, + SPI0_CSn, + SPI0_SCK, + SPI0_TX, + + SPI1_RX, + SPI1_CSn, + SPI1_SCK, + SPI1_TX, + + UART0_TX, + UART0_RX, + UART0_CTS, + UART0_RTS, + + UART1_TX, + UART1_RX, + UART1_CTS, + UART1_RTS, + + I2C0_SDA, + I2C0_SCL, + + I2C1_SDA, + I2C1_SCL, + + PWM0_A, + PWM0_B, + + PWM1_A, + PWM1_B, + + PWM2_A, + PWM2_B, + + PWM3_A, + PWM3_B, + + PWM4_A, + PWM4_B, + + PWM5_A, + PWM5_B, + + PWM6_A, + PWM6_B, + + PWM7_A, + PWM7_B, + + CLOCK_GPIN0, + CLOCK_GPIN1, + + CLOCK_GPOUT0, + CLOCK_GPOUT1, + CLOCK_GPOUT2, + CLOCK_GPOUT3, + + USB_OVCUR_DET, + USB_VBUS_DET, + USB_VBUS_EN, + + ADC0, + ADC1, + ADC2, + ADC3, + + pub fn isPwm(function: Function) bool { + return switch (function) { + .PWM0_A, + .PWM0_B, + .PWM1_A, + .PWM1_B, + .PWM2_A, + .PWM2_B, + .PWM3_A, + .PWM3_B, + .PWM4_A, + .PWM4_B, + .PWM5_A, + .PWM5_B, + .PWM6_A, + .PWM6_B, + .PWM7_A, + .PWM7_B, + => true, + else => false, + }; + } + + pub fn pwmSlice(comptime function: Function) u32 { + return switch (function) { + .PWM0_A, .PWM0_B => 0, + .PWM1_A, .PWM1_B => 1, + .PWM2_A, .PWM2_B => 2, + .PWM3_A, .PWM3_B => 3, + .PWM4_A, .PWM4_B => 4, + .PWM5_A, .PWM5_B => 5, + .PWM6_A, .PWM6_B => 6, + .PWM7_A, .PWM7_B => 7, + else => @compileError("not pwm"), + }; + } + + pub fn pwmChannel(comptime function: Function) pwm.Channel { + return switch (function) { + .PWM0_A, + .PWM1_A, + .PWM2_A, + .PWM3_A, + .PWM4_A, + .PWM5_A, + .PWM6_A, + .PWM7_A, + => .a, + .PWM0_B, + .PWM1_B, + .PWM2_B, + .PWM3_B, + .PWM4_B, + .PWM5_B, + .PWM6_B, + .PWM7_B, + => .b, + else => @compileError("not pwm"), + }; + } +}; + +fn all() [30]u1 { + var ret: [30]u1 = undefined; + for (ret) |*elem| + elem.* = 1; + + return ret; +} + +fn list(gpio_list: []const u5) [30]u1 { + var ret = std.mem.zeroes([30]u1); + for (gpio_list) |num| + ret[num] = 1; + + return ret; +} + +fn single(gpio_num: u5) [30]u1 { + var ret = std.mem.zeroes([30]u1); + ret[gpio_num] = 1; + return ret; +} + +const function_table = [@typeInfo(Function).Enum.fields.len][30]u1{ + all(), // SIO + all(), // PIO0 + all(), // PIO1 + list(&.{ 0, 4, 16, 20 }), // SPI0_RX + list(&.{ 1, 5, 17, 21 }), // SPI0_CSn + list(&.{ 2, 6, 18, 22 }), // SPI0_SCK + list(&.{ 3, 7, 19, 23 }), // SPI0_TX + list(&.{ 8, 12, 24, 28 }), // SPI1_RX + list(&.{ 9, 13, 25, 29 }), // SPI1_CSn + list(&.{ 10, 14, 26 }), // SPI1_SCK + list(&.{ 11, 15, 27 }), // SPI1_TX + list(&.{ 0, 11, 16, 28 }), // UART0_TX + list(&.{ 1, 13, 17, 29 }), // UART0_RX + list(&.{ 2, 14, 18 }), // UART0_CTS + list(&.{ 3, 15, 19 }), // UART0_RTS + list(&.{ 4, 8, 20, 24 }), // UART1_TX + list(&.{ 5, 9, 21, 25 }), // UART1_RX + list(&.{ 6, 10, 22, 26 }), // UART1_CTS + list(&.{ 7, 11, 23, 27 }), // UART1_RTS + list(&.{ 0, 4, 8, 12, 16, 20, 24, 28 }), // I2C0_SDA + list(&.{ 1, 5, 9, 13, 17, 21, 25, 29 }), // I2C0_SCL + list(&.{ 2, 6, 10, 14, 18, 22, 26 }), // I2C1_SDA + list(&.{ 3, 7, 11, 15, 19, 23, 27 }), // I2C1_SCL + list(&.{ 0, 16 }), // PWM0_A + list(&.{ 1, 17 }), // PWM0_B + list(&.{ 2, 18 }), // PWM1_A + list(&.{ 3, 19 }), // PWM1_B + list(&.{ 4, 20 }), // PWM2_A + list(&.{ 5, 21 }), // PWM2_B + list(&.{ 6, 22 }), // PWM3_A + list(&.{ 7, 23 }), // PWM3_B + list(&.{ 8, 24 }), // PWM4_A + list(&.{ 9, 25 }), // PWM4_B + list(&.{ 10, 26 }), // PWM5_A + list(&.{ 11, 27 }), // PWM5_B + list(&.{ 12, 28 }), // PWM6_A + list(&.{ 13, 29 }), // PWM6_B + single(14), // PWM7_A + single(15), // PWM7_B + single(20), // CLOCK_GPIN0 + single(22), // CLOCK_GPIN1 + single(21), // CLOCK_GPOUT0 + single(23), // CLOCK_GPOUT1 + single(24), // CLOCK_GPOUT2 + single(25), // CLOCK_GPOUT3 + list(&.{ 0, 3, 6, 9, 12, 15, 18, 21, 24, 27 }), // USB_OVCUR_DET + list(&.{ 1, 4, 7, 10, 13, 16, 19, 22, 25, 28 }), // USB_VBUS_DET + list(&.{ 2, 5, 8, 11, 14, 17, 20, 23, 26, 29 }), // USB_VBUS_EN + single(26), // ADC0 + single(27), // ADC1 + single(28), // ADC2 + single(29), // ADC3 +}; + +pub fn GPIO(comptime num: u5, comptime direction: gpio.Direction) type { + return switch (direction) { + .in => struct { + const gpio_num = num; + + pub inline fn read(self: @This()) u1 { + _ = self; + @compileError("TODO"); + } + }, + .out => struct { + const gpio_num = num; + + pub inline fn put(self: @This(), value: u1) void { + _ = self; + gpio.put(gpio_num, value); + } + + pub inline fn toggle(self: @This()) void { + _ = self; + gpio.toggle(gpio_num); + } + }, + }; +} + +pub fn Pins(comptime config: GlobalConfiguration) type { + const count = count: { + var ret: usize = 0; + inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| { + if (@field(config, field.name)) |pin_config| + if (pin_config.function == .SIO or pin_config.function.isPwm()) { + ret += 1; + }; + } + + break :count ret; + }; + + var i: usize = 0; + var fields: [count]StructField = undefined; + inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| { + if (@field(config, field.name)) |pin_config| + if (pin_config.function == .SIO) { + fields[i] = StructField{ + .name = pin_config.name orelse field.name, + .field_type = GPIO(@enumToInt(@field(Pin, field.name)), pin_config.direction orelse .in), + .is_comptime = false, + .default_value = null, + .alignment = 1, + }; + + i += 1; + } else if (pin_config.function.isPwm()) { + fields[i] = StructField{ + .name = pin_config.name orelse @tagName(pin_config.function), + .field_type = pwm.PWM(pin_config.function.pwmSlice(), pin_config.function.pwmChannel()), + .is_comptime = false, + .default_value = null, + .alignment = 1, + }; + + i += 1; + }; + } + + return @Type(.{ + .Struct = .{ + .layout = .Auto, + .is_tuple = false, + .fields = &fields, + .decls = &.{}, + }, + }); +} + +pub const GlobalConfiguration = struct { + GPIO0: ?Pin.Configuration = null, + GPIO1: ?Pin.Configuration = null, + GPIO2: ?Pin.Configuration = null, + GPIO3: ?Pin.Configuration = null, + GPIO4: ?Pin.Configuration = null, + GPIO5: ?Pin.Configuration = null, + GPIO6: ?Pin.Configuration = null, + GPIO7: ?Pin.Configuration = null, + GPIO8: ?Pin.Configuration = null, + GPIO9: ?Pin.Configuration = null, + GPIO10: ?Pin.Configuration = null, + GPIO11: ?Pin.Configuration = null, + GPIO12: ?Pin.Configuration = null, + GPIO13: ?Pin.Configuration = null, + GPIO14: ?Pin.Configuration = null, + GPIO15: ?Pin.Configuration = null, + GPIO16: ?Pin.Configuration = null, + GPIO17: ?Pin.Configuration = null, + GPIO18: ?Pin.Configuration = null, + GPIO19: ?Pin.Configuration = null, + GPIO20: ?Pin.Configuration = null, + GPIO21: ?Pin.Configuration = null, + GPIO22: ?Pin.Configuration = null, + GPIO23: ?Pin.Configuration = null, + GPIO24: ?Pin.Configuration = null, + GPIO25: ?Pin.Configuration = null, + GPIO26: ?Pin.Configuration = null, + GPIO27: ?Pin.Configuration = null, + GPIO28: ?Pin.Configuration = null, + GPIO29: ?Pin.Configuration = null, + + comptime { + const pin_field_count = @typeInfo(Pin).Enum.fields.len; + const config_field_count = @typeInfo(GlobalConfiguration).Struct.fields.len; + if (pin_field_count != config_field_count) + @compileError(comptimePrint("{} {}", .{ pin_field_count, config_field_count })); + } + + pub fn apply(comptime config: GlobalConfiguration) Pins(config) { + comptime var input_gpios: u32 = 0; + comptime var output_gpios: u32 = 0; + + // validate selected function + comptime { + inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| + if (@field(config, field.name)) |pin_config| { + const gpio_num = @enumToInt(@field(Pin, field.name)); + if (0 == function_table[@enumToInt(pin_config.function)][gpio_num]) + @compileError(comptimePrint("{s} cannot be configured for {}", .{ field.name, pin_config.function })); + + switch (pin_config.getDirection()) { + .in => input_gpios |= 1 << gpio_num, + .out => output_gpios |= 1 << gpio_num, + } + }; + } + // TODO: ensure only one instance of an input function exists + + const used_gpios = comptime input_gpios | output_gpios; + gpio.reset(); + + if (used_gpios != 0) { + regs.SIO.GPIO_OE_CLR.raw = used_gpios; + regs.SIO.GPIO_OUT_CLR.raw = used_gpios; + + comptime var i: u32 = 0; + inline while (i < 32) : (i += 1) + if (0 != used_gpios & 1 << i) + gpio.setFunction(i, .sio); + } + + if (output_gpios != 0) + regs.SIO.GPIO_OE_SET.raw = output_gpios; + + // TODO: pwm initialization + + // fields in the Pins(config) type should be zero sized, so we just + // default build them all (wasn't sure how to do that cleanly in + // `Pins()` + var ret: Pins(config) = undefined; + inline for (@typeInfo(Pins(config)).Struct.fields) |field| + @field(ret, field.name) = .{}; + + return ret; + } +}; diff --git a/src/hal/pll.zig b/src/hal/pll.zig index 4481abded..117a42c14 100644 --- a/src/hal/pll.zig +++ b/src/hal/pll.zig @@ -2,6 +2,9 @@ const std = @import("std"); const microzig = @import("microzig"); const assert = std.debug.assert; +// TODO: remove +const gpio = @import("gpio.zig"); + const regs = microzig.chip.registers; const xosc_freq = microzig.board.xosc_freq; diff --git a/src/hal/pwm.zig b/src/hal/pwm.zig new file mode 100644 index 000000000..457fd2c2c --- /dev/null +++ b/src/hal/pwm.zig @@ -0,0 +1,116 @@ +const microzig = @import("microzig"); +const regs = microzig.chip.registers; + +pub const Config = struct {}; + +fn getRegs(comptime slice: u32) *volatile Regs { + @import("std").debug.assert(slice < 8); + return @intToPtr(*volatile Regs, regs.PWM.base_address); // + (slice * 0x14)); +} + +pub fn PWM(comptime slice_num: u32, comptime chan: Channel) type { + return struct { + pub const slice_number = slice_num; + pub const channel = chan; + + pub inline fn setLevel(_: @This(), level: u16) void { + setChannelLevel(slice_number, channel, level); + } + + pub fn slice(_: @This()) Slice(slice_number) { + return .{}; + } + }; +} + +pub fn Slice(comptime slice_num: u32) type { + return struct { + const slice_number = slice_num; + + pub inline fn setWrap(_: @This(), wrap: u16) void { + setSliceWrap(slice_number, wrap); + } + + pub inline fn enable(_: @This()) void { + getRegs(slice_number).csr.modify(.{ .EN = 1 }); + } + + pub inline fn disable(_: @This()) void { + getRegs(slice_number).csr.modify(.{ .EN = 0 }); + } + + pub inline fn setPhaseCorrect(_: @This(), phase_correct: bool) void { + setSlicePhaseCorrect(slice_number, phase_correct); + } + + pub inline fn setClkDiv(_: @This(), integer: u8, fraction: u4) void { + setSliceClkDiv(slice_number, integer, fraction); + } + }; +} + +pub const ClkDivMode = enum(u2) { + free_running, + b_high, + b_rising, + b_falling, +}; + +pub const Channel = enum(u1) { a, b }; + +const Regs = extern struct { + csr: @typeInfo(@TypeOf(regs.PWM.CH0_CSR)).Pointer.child, + div: @typeInfo(@TypeOf(regs.PWM.CH0_DIV)).Pointer.child, + ctr: @typeInfo(@TypeOf(regs.PWM.CH0_CTR)).Pointer.child, + cc: @typeInfo(@TypeOf(regs.PWM.CH0_CC)).Pointer.child, + top: @typeInfo(@TypeOf(regs.PWM.CH0_TOP)).Pointer.child, +}; + +pub inline fn setSlicePhaseCorrect(comptime slice: u32, phase_correct: bool) void { + getRegs(slice).csr.modify(.{ + .PH_CORRECT = if (phase_correct) 1 else 0, + }); +} + +pub inline fn setSliceClkDiv(comptime slice: u32, integer: u8, fraction: u4) void { + getRegs(slice).div.modify(.{ + .INT = integer, + .FRAC = fraction, + }); +} + +pub inline fn setSliceClkDivMode(comptime slice: u32, mode: ClkDivMode) void { + getRegs(slice).csr.modify(.{ + .DIVMODE = @enumToInt(mode), + }); +} + +pub inline fn setChannelInversion( + comptime slice: u32, + comptime channel: Channel, + invert: bool, +) void { + switch (channel) { + .a => getRegs(slice).csr.modify(.{ + .A_INV = if (invert) 1 else 0, + }), + .b => getRegs(slice).csr.modifi(.{ + .B_INV = if (invert) 1 else 0, + }), + } +} + +pub inline fn setSliceWrap(comptime slice: u32, wrap: u16) void { + getRegs(slice).top.raw = wrap; +} + +pub inline fn setChannelLevel( + comptime slice: u32, + comptime channel: Channel, + level: u16, +) void { + switch (channel) { + .a => getRegs(slice).cc.modify(.{ .A = level }), + .b => getRegs(slice).cc.modify(.{ .B = level }), + } +} diff --git a/src/hal/resets.zig b/src/hal/resets.zig new file mode 100644 index 000000000..0e0ea2bce --- /dev/null +++ b/src/hal/resets.zig @@ -0,0 +1,47 @@ +const std = @import("std"); +const microzig = @import("microzig"); + +const regs = microzig.chip.registers; +const EnumField = std.builtin.TypeInfo.EnumField; +const Mask = @typeInfo(@TypeOf(regs.RESETS.RESET)).Pointer.child.underlying_type; + +pub const Module = enum { + adc, + busctrl, + dma, + i2c0, + i2c1, + io_bank0, + io_qspi, + jtag, + pads_bank0, + pads_qspi, + pio0, + pio1, + pll_sys, + pll_usb, + pwm, + rtc, + spi0, + spi1, + syscfg, + sysinfo, + tbman, + timer, + uart0, + uart1, + usbctrl, +}; + +pub inline fn reset(comptime modules: []const Module) void { + comptime var mask = std.mem.zeroes(Mask); + + inline for (modules) |module| + @field(mask, @tagName(module)) = 1; + + const raw_mask = @bitCast(u32, mask); + regs.RESETS.RESET.raw = raw_mask; + regs.RESETS.RESET.raw = 0; + + while (regs.RESETS.RESET_DONE.raw & raw_mask != raw_mask) {} +} From d4a74cb4f3287fa05156d3aaea049264f4597692 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 17 Sep 2022 16:54:45 -0700 Subject: [PATCH 016/286] move examples in here (#12) --- .gitmodules | 3 + build.zig | 42 +- deps/microzig | 1 + examples/blinky.zig | 20 + examples/blinky_core1.zig | 29 + examples/gpio_clk.zig | 21 + examples/pwm.zig | 23 + examples/uart.zig | 48 ++ src/hal.zig | 2 + src/hal/gpio.zig | 3 + src/hal/irq.zig | 20 + src/hal/multicore.zig | 2 +- src/hal/pwm.zig | 8 + src/hal/uart.zig | 51 +- src/rp2040.zig | 1381 ++++++++++--------------------------- 15 files changed, 635 insertions(+), 1019 deletions(-) create mode 100644 .gitmodules create mode 160000 deps/microzig create mode 100644 examples/blinky.zig create mode 100644 examples/blinky_core1.zig create mode 100644 examples/gpio_clk.zig create mode 100644 examples/pwm.zig create mode 100644 examples/uart.zig create mode 100644 src/hal/irq.zig diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 000000000..32e895ccb --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "deps/microzig"] + path = deps/microzig + url = https://github.com/ZigEmbeddedGroup/microzig.git diff --git a/build.zig b/build.zig index f4675dddd..01a26ae6e 100644 --- a/build.zig +++ b/build.zig @@ -1,9 +1,10 @@ const std = @import("std"); - const Builder = std.build.Builder; const Pkg = std.build.Pkg; const comptimePrint = std.fmt.comptimePrint; +const microzig = @import("deps/microzig/src/main.zig"); + const chip_path = comptimePrint("{s}/src/rp2040.zig", .{root()}); const board_path = comptimePrint("{s}/src/raspberry_pi_pico.zig", .{root()}); const hal_path = comptimePrint("{s}/src/hal.zig", .{root()}); @@ -12,7 +13,6 @@ const linkerscript_path = comptimePrint("{s}/rp2040.ld", .{root()}); pub const BuildOptions = struct {}; pub fn addPiPicoExecutable( - comptime microzig: type, builder: *Builder, name: []const u8, source: []const u8, @@ -49,6 +49,44 @@ pub fn addPiPicoExecutable( return ret; } +// this build script is mostly for testing and verification of this +// package. In an attempt to modularize -- designing for a case where a +// project requires multiple HALs, it accepts microzig as a param +pub fn build(b: *Builder) !void { + const mode = b.standardReleaseOptions(); + var examples = Examples.init(b, mode); + examples.install(); +} + fn root() []const u8 { return std.fs.path.dirname(@src().file) orelse "."; } + +pub const Examples = struct { + blinky: microzig.EmbeddedExecutable, + blinky_core1: microzig.EmbeddedExecutable, + gpio_clk: microzig.EmbeddedExecutable, + pwm: microzig.EmbeddedExecutable, + uart: microzig.EmbeddedExecutable, + //uart_pins: microzig.EmbeddedExecutable, + + pub fn init(b: *Builder, mode: std.builtin.Mode) Examples { + var ret: Examples = undefined; + inline for (@typeInfo(Examples).Struct.fields) |field| { + @field(ret, field.name) = addPiPicoExecutable( + b, + field.name, + comptime root() ++ "/examples/" ++ field.name ++ ".zig", + .{}, + ); + @field(ret, field.name).setBuildMode(mode); + } + + return ret; + } + + pub fn install(examples: *Examples) void { + inline for (@typeInfo(Examples).Struct.fields) |field| + @field(examples, field.name).install(); + } +}; diff --git a/deps/microzig b/deps/microzig new file mode 160000 index 000000000..4159581b4 --- /dev/null +++ b/deps/microzig @@ -0,0 +1 @@ +Subproject commit 4159581b4848bfb8bbdf91dabdebd15ecd503427 diff --git a/examples/blinky.zig b/examples/blinky.zig new file mode 100644 index 000000000..ea3f2d8fd --- /dev/null +++ b/examples/blinky.zig @@ -0,0 +1,20 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const rp2040 = microzig.hal; +const time = rp2040.time; + +const pin_config = rp2040.pins.GlobalConfiguration{ + .GPIO25 = .{ + .name = "led", + .direction = .out, + }, +}; + +pub fn main() !void { + const pins = pin_config.apply(); + + while (true) { + pins.led.toggle(); + time.sleepMs(250); + } +} diff --git a/examples/blinky_core1.zig b/examples/blinky_core1.zig new file mode 100644 index 000000000..a549f3094 --- /dev/null +++ b/examples/blinky_core1.zig @@ -0,0 +1,29 @@ +const std = @import("std"); + +const microzig = @import("microzig"); +const rp2040 = microzig.hal; +const gpio = rp2040.gpio; +const time = rp2040.time; +const multicore = rp2040.multicore; + +const led = 25; + +fn core1() void { + while (true) { + gpio.put(led, 1); + time.sleepMs(250); + gpio.put(led, 0); + time.sleepMs(250); + } +} + +pub fn main() !void { + gpio.init(led); + gpio.setDir(led, .out); + + multicore.launchCore1(core1); + + while (true) { + microzig.cpu.wfi(); + } +} diff --git a/examples/gpio_clk.zig b/examples/gpio_clk.zig new file mode 100644 index 000000000..52280e4a6 --- /dev/null +++ b/examples/gpio_clk.zig @@ -0,0 +1,21 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const rp2040 = microzig.hal; +const gpio = rp2040.gpio; +const clocks = rp2040.clocks; + +const gpout0_pin = 21; +const clock_config = clocks.GlobalConfiguration.init(.{ + .sys = .{ .source = .src_xosc }, + .gpout0 = .{ .source = .clk_sys }, +}); + +pub fn init() void { + clock_config.apply(); + gpio.reset(); +} + +pub fn main() !void { + gpio.setFunction(gpout0_pin, .gpck); + while (true) {} +} diff --git a/examples/pwm.zig b/examples/pwm.zig new file mode 100644 index 000000000..9eff04393 --- /dev/null +++ b/examples/pwm.zig @@ -0,0 +1,23 @@ +const std = @import("std"); +const microzig = @import("microzig"); +const rp2040 = microzig.hal; +const gpio = rp2040.gpio; +const clocks = rp2040.clocks; +const time = rp2040.time; +const regs = microzig.chip.registers; +const multicore = rp2040.multicore; + +const pin_config = rp2040.pins.GlobalConfiguration{ + .GPIO25 = .{ .name = "led", .function = .PWM4_B }, +}; + +pub fn main() !void { + const pins = pin_config.apply(); + pins.led.slice().setWrap(100); + pins.led.setLevel(10); + pins.led.slice().enable(); + + while (true) { + time.sleepMs(250); + } +} diff --git a/examples/uart.zig b/examples/uart.zig new file mode 100644 index 000000000..ed29280b5 --- /dev/null +++ b/examples/uart.zig @@ -0,0 +1,48 @@ +const std = @import("std"); +const microzig = @import("microzig"); + +const rp2040 = microzig.hal; +const time = rp2040.time; +const gpio = rp2040.gpio; +const clocks = rp2040.clocks; + +const led = 25; +const uart_id = 0; +const baud_rate = 115200; +const uart_tx_pin = 0; +const uart_rx_pin = 1; + +pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace) noreturn { + std.log.err("panic: {s}", .{message}); + @breakpoint(); + while (true) {} +} + +pub const log_level = .debug; +pub const log = rp2040.uart.log; + +pub fn main() !void { + gpio.reset(); + gpio.init(led); + gpio.setDir(led, .out); + gpio.put(led, 1); + + const uart = rp2040.uart.UART.init(uart_id, .{ + .baud_rate = baud_rate, + .tx_pin = uart_tx_pin, + .rx_pin = uart_rx_pin, + .clock_config = rp2040.clock_config, + }); + + rp2040.uart.initLogger(uart); + + var i: u32 = 0; + while (true) : (i += 1) { + gpio.put(led, 1); + std.log.info("what {}", .{i}); + time.sleepMs(500); + + gpio.put(led, 0); + time.sleepMs(500); + } +} diff --git a/src/hal.zig b/src/hal.zig index 1dc50e6b0..61132bd86 100644 --- a/src/hal.zig +++ b/src/hal.zig @@ -8,6 +8,8 @@ pub const multicore = @import("hal/multicore.zig"); pub const time = @import("hal/time.zig"); pub const uart = @import("hal/uart.zig"); pub const pwm = @import("hal/pwm.zig"); +pub const resets = @import("hal/resets.zig"); +pub const irq = @import("hal/irq.zig"); pub const clock_config = clocks.GlobalConfiguration.init(.{ .ref = .{ .source = .src_xosc }, diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig index ec48f114b..18624eea9 100644 --- a/src/hal/gpio.zig +++ b/src/hal/gpio.zig @@ -4,6 +4,8 @@ const resets = @import("resets.zig"); const regs = microzig.chip.registers; const assert = std.debug.assert; +const log = std.log.scoped(.gpio); + pub const Function = enum(u5) { xip, spi, @@ -83,6 +85,7 @@ pub inline fn setDir(comptime gpio: u32, direction: Direction) void { /// Drive a single GPIO high/low pub inline fn put(comptime gpio: u32, value: u1) void { + std.log.debug("GPIO{} put: {}", .{ gpio, value }); const mask = 1 << gpio; switch (value) { 0 => regs.SIO.GPIO_OUT_CLR.raw = mask, diff --git a/src/hal/irq.zig b/src/hal/irq.zig new file mode 100644 index 000000000..7d57c7854 --- /dev/null +++ b/src/hal/irq.zig @@ -0,0 +1,20 @@ +const microzig = @import("microzig"); +const regs = microzig.chip.registers; + +// TODO: the register definitions are improved now, use them instead of raw +// writes/reads +fn getInterruptMask(comptime interrupt_name: []const u8) u32 { + const offset = @offsetOf(microzig.chip.VectorTable, interrupt_name); + + return (1 << ((offset / 4) - 16)); +} +pub fn enable(comptime interrupt_name: []const u8) void { + const mask = comptime getInterruptMask(interrupt_name); + regs.SCS.NVIC.ICPR.raw = mask; + regs.SCS.NVIC.ISER.raw = mask; +} + +pub fn disable(comptime interrupt_name: []const u8) void { + const mask = comptime getInterruptMask(interrupt_name); + regs.SCS.NVIC.ICER.raw = mask; +} diff --git a/src/hal/multicore.zig b/src/hal/multicore.zig index dd90d17d5..76811cf2a 100644 --- a/src/hal/multicore.zig +++ b/src/hal/multicore.zig @@ -88,7 +88,7 @@ pub fn launchCore1WithStack(entrypoint: fn () void, stack: []u32) void { 0, 0, 1, - regs.PPB.VTOR.raw, + regs.SCS.SCB.VTOR.raw, stack_ptr, @ptrToInt(wrapper), }; diff --git a/src/hal/pwm.zig b/src/hal/pwm.zig index 457fd2c2c..45cf90b37 100644 --- a/src/hal/pwm.zig +++ b/src/hal/pwm.zig @@ -1,6 +1,9 @@ +const std = @import("std"); const microzig = @import("microzig"); const regs = microzig.chip.registers; +const log = std.log.scoped(.pwm); + pub const Config = struct {}; fn getRegs(comptime slice: u32) *volatile Regs { @@ -67,12 +70,14 @@ const Regs = extern struct { }; pub inline fn setSlicePhaseCorrect(comptime slice: u32, phase_correct: bool) void { + log.debug("PWM{} set phase correct: {}", .{ slice, phase_correct }); getRegs(slice).csr.modify(.{ .PH_CORRECT = if (phase_correct) 1 else 0, }); } pub inline fn setSliceClkDiv(comptime slice: u32, integer: u8, fraction: u4) void { + log.debug("PWM{} set clk div: {}.{}", .{ slice, integer, fraction }); getRegs(slice).div.modify(.{ .INT = integer, .FRAC = fraction, @@ -80,6 +85,7 @@ pub inline fn setSliceClkDiv(comptime slice: u32, integer: u8, fraction: u4) voi } pub inline fn setSliceClkDivMode(comptime slice: u32, mode: ClkDivMode) void { + log.debug("PWM{} set clk div mode: {}", .{ slice, mode }); getRegs(slice).csr.modify(.{ .DIVMODE = @enumToInt(mode), }); @@ -101,6 +107,7 @@ pub inline fn setChannelInversion( } pub inline fn setSliceWrap(comptime slice: u32, wrap: u16) void { + log.debug("PWM{} set wrap: {}", .{ slice, wrap }); getRegs(slice).top.raw = wrap; } @@ -109,6 +116,7 @@ pub inline fn setChannelLevel( comptime channel: Channel, level: u16, ) void { + log.debug("PWM{} {} set level: {}", .{ slice, channel, level }); switch (channel) { .a => getRegs(slice).cc.modify(.{ .A = level }), .b => getRegs(slice).cc.modify(.{ .B = level }), diff --git a/src/hal/uart.zig b/src/hal/uart.zig index 18163992f..5f3f8c61f 100644 --- a/src/hal/uart.zig +++ b/src/hal/uart.zig @@ -2,6 +2,8 @@ const std = @import("std"); const microzig = @import("microzig"); const gpio = @import("gpio.zig"); const clocks = @import("clocks.zig"); +const resets = @import("resets.zig"); +const time = @import("time.zig"); const assert = std.debug.assert; const regs = microzig.chip.registers; @@ -39,7 +41,7 @@ pub const UartRegs = extern struct { rsr: u32, reserved0: [4]u32, fr: @typeInfo(@TypeOf(regs.UART0.UARTFR)).Pointer.child, - resertev1: [1]u32, + reserved1: [1]u32, ilpr: u32, ibrd: u32, fbrd: u32, @@ -149,16 +151,8 @@ pub const UART = enum { pub fn reset(uart: UART) void { switch (uart) { - .uart0 => { - regs.RESETS.RESET.modify(.{ .uart0 = 1 }); - regs.RESETS.RESET.modify(.{ .uart0 = 0 }); - while (regs.RESETS.RESET_DONE.read().uart0 != 1) {} - }, - .uart1 => { - regs.RESETS.RESET.modify(.{ .uart1 = 1 }); - regs.RESETS.RESET.modify(.{ .uart1 = 0 }); - while (regs.RESETS.RESET_DONE.read().uart1 != 1) {} - }, + .uart0 => resets.reset(&.{.uart0}), + .uart1 => resets.reset(&.{.uart1}), } } @@ -180,11 +174,13 @@ pub const UART = enum { .one => @as(u1, 0), .two => @as(u1, 1), }, - .PEN = if (parity != .none) @as(u1, 1) else @as(u1, 0), + .PEN = switch (parity) { + .none => @as(u1, 0), + .even, .odd => @as(u1, 1), + }, .EPS = switch (parity) { .even => @as(u1, 1), - .odd => @as(u1, 0), - else => @as(u1, 0), + .odd, .none => @as(u1, 0), }, }); } @@ -210,3 +206,30 @@ pub const UART = enum { uart_regs.lcr_h.modify(.{}); } }; + +var uart_logger: ?UART.Writer = null; + +pub fn initLogger(uart: UART) void { + uart_logger = uart.writer(); +} + +pub fn log( + comptime level: std.log.Level, + comptime scope: @TypeOf(.EnumLiteral), + comptime format: []const u8, + args: anytype, +) void { + const level_prefix = comptime "[{}.{:0>6}] " ++ level.asText(); + const prefix = comptime level_prefix ++ switch (scope) { + .default => ": ", + else => " (" ++ @tagName(scope) ++ "): ", + }; + + if (uart_logger) |uart| { + const current_time = time.getTimeSinceBoot(); + const seconds = current_time.us_since_boot / std.time.us_per_s; + const microseconds = current_time.us_since_boot % std.time.us_per_s; + + uart.print(prefix ++ format ++ "\r\n", .{ seconds, microseconds } ++ args) catch {}; + } +} diff --git a/src/rp2040.zig b/src/rp2040.zig index 571b6489e..6301bf235 100644 --- a/src/rp2040.zig +++ b/src/rp2040.zig @@ -1,5 +1,5 @@ // this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz -// commit: 09c331e02d8037bf2e5133eaa40b1d762637b441 +// commit: 644b9d6f61ba1e49d90e4f606f82727f3d6581f2 // // vendor: Raspberry Pi // device: RP2040 @@ -134,23 +134,388 @@ pub const registers = struct { pub const NVIC = struct { /// address: 0xe000e100 /// Interrupt Set Enable Register - pub const ISER = @intToPtr(*volatile u32, base_address + 0x100); + pub const ISER = @intToPtr(*volatile Mmio(32, packed struct { + TIMER_IRQ_0: u1, + TIMER_IRQ_1: u1, + TIMER_IRQ_2: u1, + TIMER_IRQ_3: u1, + PWM_IRQ_WRAP: u1, + USBCTRL_IRQ: u1, + XIP_IRQ: u1, + PIO0_IRQ_0: u1, + PIO0_IRQ_1: u1, + PIO1_IRQ_0: u1, + PIO1_IRQ_1: u1, + DMA_IRQ_0: u1, + DMA_IRQ_1: u1, + IO_IRQ_BANK0: u1, + IO_IRQ_QSPI: u1, + SIO_IRQ_PROC0: u1, + SIO_IRQ_PROC1: u1, + CLOCKS_IRQ: u1, + SPI0_IRQ: u1, + SPI1_IRQ: u1, + UART0_IRQ: u1, + UART1_IRQ: u1, + ADC_IRQ_FIFO: u1, + I2C0_IRQ: u1, + I2C1_IRQ: u1, + RTC_IRQ: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + }), base_address + 0x100); /// address: 0xe000e180 /// Interrupt Clear Enable Register - pub const ICER = @intToPtr(*volatile u32, base_address + 0x180); + pub const ICER = @intToPtr(*volatile Mmio(32, packed struct { + TIMER_IRQ_0: u1, + TIMER_IRQ_1: u1, + TIMER_IRQ_2: u1, + TIMER_IRQ_3: u1, + PWM_IRQ_WRAP: u1, + USBCTRL_IRQ: u1, + XIP_IRQ: u1, + PIO0_IRQ_0: u1, + PIO0_IRQ_1: u1, + PIO1_IRQ_0: u1, + PIO1_IRQ_1: u1, + DMA_IRQ_0: u1, + DMA_IRQ_1: u1, + IO_IRQ_BANK0: u1, + IO_IRQ_QSPI: u1, + SIO_IRQ_PROC0: u1, + SIO_IRQ_PROC1: u1, + CLOCKS_IRQ: u1, + SPI0_IRQ: u1, + SPI1_IRQ: u1, + UART0_IRQ: u1, + UART1_IRQ: u1, + ADC_IRQ_FIFO: u1, + I2C0_IRQ: u1, + I2C1_IRQ: u1, + RTC_IRQ: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + }), base_address + 0x180); /// address: 0xe000e200 /// Interrupt Set Pending Register - pub const ISPR = @intToPtr(*volatile u32, base_address + 0x200); + pub const ISPR = @intToPtr(*volatile Mmio(32, packed struct { + TIMER_IRQ_0: u1, + TIMER_IRQ_1: u1, + TIMER_IRQ_2: u1, + TIMER_IRQ_3: u1, + PWM_IRQ_WRAP: u1, + USBCTRL_IRQ: u1, + XIP_IRQ: u1, + PIO0_IRQ_0: u1, + PIO0_IRQ_1: u1, + PIO1_IRQ_0: u1, + PIO1_IRQ_1: u1, + DMA_IRQ_0: u1, + DMA_IRQ_1: u1, + IO_IRQ_BANK0: u1, + IO_IRQ_QSPI: u1, + SIO_IRQ_PROC0: u1, + SIO_IRQ_PROC1: u1, + CLOCKS_IRQ: u1, + SPI0_IRQ: u1, + SPI1_IRQ: u1, + UART0_IRQ: u1, + UART1_IRQ: u1, + ADC_IRQ_FIFO: u1, + I2C0_IRQ: u1, + I2C1_IRQ: u1, + RTC_IRQ: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + }), base_address + 0x200); /// address: 0xe000e280 /// Interrupt Clear Pending Register - pub const ICPR = @intToPtr(*volatile u32, base_address + 0x280); + pub const ICPR = @intToPtr(*volatile Mmio(32, packed struct { + TIMER_IRQ_0: u1, + TIMER_IRQ_1: u1, + TIMER_IRQ_2: u1, + TIMER_IRQ_3: u1, + PWM_IRQ_WRAP: u1, + USBCTRL_IRQ: u1, + XIP_IRQ: u1, + PIO0_IRQ_0: u1, + PIO0_IRQ_1: u1, + PIO1_IRQ_0: u1, + PIO1_IRQ_1: u1, + DMA_IRQ_0: u1, + DMA_IRQ_1: u1, + IO_IRQ_BANK0: u1, + IO_IRQ_QSPI: u1, + SIO_IRQ_PROC0: u1, + SIO_IRQ_PROC1: u1, + CLOCKS_IRQ: u1, + SPI0_IRQ: u1, + SPI1_IRQ: u1, + UART0_IRQ: u1, + UART1_IRQ: u1, + ADC_IRQ_FIFO: u1, + I2C0_IRQ: u1, + I2C1_IRQ: u1, + RTC_IRQ: u1, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + }), base_address + 0x280); /// address: 0xe000e400 /// Interrupt Priority Register - pub const IP = @intToPtr(*volatile u32, base_address + 0x400); + pub const IP0 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + TIMER_IRQ_0: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + TIMER_IRQ_1: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + TIMER_IRQ_2: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + TIMER_IRQ_3: u2, + }), base_address + 0x400); + + /// address: 0xe000e404 + /// Interrupt Priority Register + pub const IP1 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + PWM_IRQ_WRAP: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + USBCTRL_IRQ: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + XIP_IRQ: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + PIO0_IRQ_0: u2, + }), base_address + 0x404); + + /// address: 0xe000e408 + /// Interrupt Priority Register + pub const IP2 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + PIO0_IRQ_1: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + PIO1_IRQ_0: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + PIO1_IRQ_1: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + DMA_IRQ_0: u2, + }), base_address + 0x408); + + /// address: 0xe000e40c + /// Interrupt Priority Register + pub const IP3 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + DMA_IRQ_1: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + IO_IRQ_BANK0: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + IO_IRQ_QSPI: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + SIO_IRQ_PROC0: u2, + }), base_address + 0x40c); + + /// address: 0xe000e410 + /// Interrupt Priority Register + pub const IP4 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + SIO_IRQ_PROC1: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + CLOCKS_IRQ: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + SPI0_IRQ: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + SPI1_IRQ: u2, + }), base_address + 0x410); + + /// address: 0xe000e414 + /// Interrupt Priority Register + pub const IP5 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + UART0_IRQ: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + UART1_IRQ: u2, + reserved12: u1 = 0, + reserved13: u1 = 0, + reserved14: u1 = 0, + reserved15: u1 = 0, + reserved16: u1 = 0, + reserved17: u1 = 0, + ADC_IRQ_FIFO: u2, + reserved18: u1 = 0, + reserved19: u1 = 0, + reserved20: u1 = 0, + reserved21: u1 = 0, + reserved22: u1 = 0, + reserved23: u1 = 0, + I2C0_IRQ: u2, + }), base_address + 0x414); + + /// address: 0xe000e418 + /// Interrupt Priority Register + pub const IP6 = @intToPtr(*volatile Mmio(32, packed struct { + reserved0: u1 = 0, + reserved1: u1 = 0, + reserved2: u1 = 0, + reserved3: u1 = 0, + reserved4: u1 = 0, + reserved5: u1 = 0, + I2C1_IRQ: u2, + reserved6: u1 = 0, + reserved7: u1 = 0, + reserved8: u1 = 0, + reserved9: u1 = 0, + reserved10: u1 = 0, + reserved11: u1 = 0, + RTC_IRQ: u2, + padding0: u1 = 0, + padding1: u1 = 0, + padding2: u1 = 0, + padding3: u1 = 0, + padding4: u1 = 0, + padding5: u1 = 0, + padding6: u1 = 0, + padding7: u1 = 0, + padding8: u1 = 0, + padding9: u1 = 0, + padding10: u1 = 0, + padding11: u1 = 0, + padding12: u1 = 0, + padding13: u1 = 0, + padding14: u1 = 0, + padding15: u1 = 0, + }), base_address + 0x418); + + /// address: 0xe000e41c + /// Interrupt Priority Register + pub const IP7 = @intToPtr(*volatile u32, base_address + 0x41c); }; /// System Control Block @@ -28295,806 +28660,35 @@ pub const registers = struct { pub const base_address = 0xe0000000; pub const version = "1"; - /// address: 0xe000e010 - /// Use the SysTick Control and Status Register to enable the SysTick features. - pub const SYST_CSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Enable SysTick counter:\n - /// 0 = Counter disabled.\n - /// 1 = Counter enabled. - ENABLE: u1, - /// Enables SysTick exception request:\n - /// 0 = Counting down to zero does not assert the SysTick exception request.\n - /// 1 = Counting down to zero to asserts the SysTick exception request. - TICKINT: u1, - /// SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\n - /// Selects the SysTick timer clock source:\n - /// 0 = External reference clock.\n - /// 1 = Processor clock. - CLKSOURCE: u1, - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - reserved12: u1 = 0, - /// Returns 1 if timer counted to 0 since last time this was read. Clears on read by - /// application or debugger. - COUNTFLAG: u1, - padding0: u1 = 0, - padding1: u1 = 0, - padding2: u1 = 0, - padding3: u1 = 0, - padding4: u1 = 0, - padding5: u1 = 0, - padding6: u1 = 0, - padding7: u1 = 0, - padding8: u1 = 0, - padding9: u1 = 0, - padding10: u1 = 0, - padding11: u1 = 0, - padding12: u1 = 0, - padding13: u1 = 0, - padding14: u1 = 0, - }), base_address + 0xe010); - - /// address: 0xe000e014 - /// Use the SysTick Reload Value Register to specify the start value to load into - /// the current value register when the counter reaches 0. It can be any value - /// between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect - /// because the SysTick interrupt and COUNTFLAG are activated when counting from 1 - /// to 0. The reset value of this register is UNKNOWN.\n - /// To generate a multi-shot timer with a period of N processor clock cycles, use a - /// RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 - /// clock pulses, set RELOAD to 99. - pub const SYST_RVR = @intToPtr(*volatile Mmio(32, packed struct { - /// Value to load into the SysTick Current Value Register when the counter reaches - /// 0. - RELOAD: u24, - padding0: u1 = 0, - padding1: u1 = 0, - padding2: u1 = 0, - padding3: u1 = 0, - padding4: u1 = 0, - padding5: u1 = 0, - padding6: u1 = 0, - padding7: u1 = 0, - }), base_address + 0xe014); - - /// address: 0xe000e018 - /// Use the SysTick Current Value Register to find the current value in the - /// register. The reset value of this register is UNKNOWN. - pub const SYST_CVR = @intToPtr(*volatile Mmio(32, packed struct { - /// Reads return the current value of the SysTick counter. This register is - /// write-clear. Writing to it with any value clears the register to 0. Clearing - /// this register also clears the COUNTFLAG bit of the SysTick Control and Status - /// Register. - CURRENT: u24, - padding0: u1 = 0, - padding1: u1 = 0, - padding2: u1 = 0, - padding3: u1 = 0, - padding4: u1 = 0, - padding5: u1 = 0, - padding6: u1 = 0, - padding7: u1 = 0, - }), base_address + 0xe018); - - /// address: 0xe000e01c - /// Use the SysTick Calibration Value Register to enable software to scale to any - /// required speed using divide and multiply. - pub const SYST_CALIB = @intToPtr(*volatile Mmio(32, packed struct { - /// An optional Reload value to be used for 10ms (100Hz) timing, subject to system - /// clock skew errors. If the value reads as 0, the calibration value is not known. - TENMS: u24, - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - /// If reads as 1, the calibration value for 10ms is inexact (due to clock - /// frequency). - SKEW: u1, - /// If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the - /// SysTick Control and Status register will be forced to 1 and cannot be cleared to - /// 0. - NOREF: u1, - }), base_address + 0xe01c); - - /// address: 0xe000e100 - /// Use the Interrupt Set-Enable Register to enable interrupts and determine which - /// interrupts are currently enabled.\n - /// If a pending interrupt is enabled, the NVIC activates the interrupt based on its - /// priority. If an interrupt is not enabled, asserting its interrupt signal changes - /// the interrupt state to pending, but the NVIC never activates the interrupt, - /// regardless of its priority. - pub const NVIC_ISER = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt set-enable bits.\n - /// Write:\n - /// 0 = No effect.\n - /// 1 = Enable interrupt.\n - /// Read:\n - /// 0 = Interrupt disabled.\n - /// 1 = Interrupt enabled. - SETENA: u32, - }), base_address + 0xe100); - - /// address: 0xe000e180 - /// Use the Interrupt Clear-Enable Registers to disable interrupts and determine - /// which interrupts are currently enabled. - pub const NVIC_ICER = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt clear-enable bits.\n - /// Write:\n - /// 0 = No effect.\n - /// 1 = Disable interrupt.\n - /// Read:\n - /// 0 = Interrupt disabled.\n - /// 1 = Interrupt enabled. - CLRENA: u32, - }), base_address + 0xe180); - - /// address: 0xe000e200 - /// The NVIC_ISPR forces interrupts into the pending state, and shows which - /// interrupts are pending. - pub const NVIC_ISPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt set-pending bits.\n - /// Write:\n - /// 0 = No effect.\n - /// 1 = Changes interrupt state to pending.\n - /// Read:\n - /// 0 = Interrupt is not pending.\n - /// 1 = Interrupt is pending.\n - /// Note: Writing 1 to the NVIC_ISPR bit corresponding to:\n - /// An interrupt that is pending has no effect.\n - /// A disabled interrupt sets the state of that interrupt to pending. - SETPEND: u32, - }), base_address + 0xe200); - - /// address: 0xe000e280 - /// Use the Interrupt Clear-Pending Register to clear pending interrupts and - /// determine which interrupts are currently pending. - pub const NVIC_ICPR = @intToPtr(*volatile Mmio(32, packed struct { - /// Interrupt clear-pending bits.\n - /// Write:\n - /// 0 = No effect.\n - /// 1 = Removes pending state and interrupt.\n - /// Read:\n - /// 0 = Interrupt is not pending.\n - /// 1 = Interrupt is pending. - CLRPEND: u32, - }), base_address + 0xe280); - - /// address: 0xe000e400 - /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of - /// the available interrupts. 0 is the highest priority, and 3 is the lowest.\n - /// Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the - /// corresponding interrupt.\n - /// These registers are only word-accessible - pub const NVIC_IPR0 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - /// Priority of interrupt 0 - IP_0: u2, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - /// Priority of interrupt 1 - IP_1: u2, - reserved12: u1 = 0, - reserved13: u1 = 0, - reserved14: u1 = 0, - reserved15: u1 = 0, - reserved16: u1 = 0, - reserved17: u1 = 0, - /// Priority of interrupt 2 - IP_2: u2, - reserved18: u1 = 0, - reserved19: u1 = 0, - reserved20: u1 = 0, - reserved21: u1 = 0, - reserved22: u1 = 0, - reserved23: u1 = 0, - /// Priority of interrupt 3 - IP_3: u2, - }), base_address + 0xe400); - - /// address: 0xe000e404 - /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of - /// the available interrupts. 0 is the highest priority, and 3 is the lowest. - pub const NVIC_IPR1 = @intToPtr(*volatile Mmio(32, packed struct { + /// address: 0xe000ed20 + /// System handlers are a special class of exception handler that can have their + /// priority set to any of the priority levels. Use the System Handler Priority + /// Register 3 to set the priority of PendSV and SysTick. + pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { reserved0: u1 = 0, reserved1: u1 = 0, reserved2: u1 = 0, reserved3: u1 = 0, reserved4: u1 = 0, reserved5: u1 = 0, - /// Priority of interrupt 4 - IP_4: u2, reserved6: u1 = 0, reserved7: u1 = 0, reserved8: u1 = 0, reserved9: u1 = 0, reserved10: u1 = 0, reserved11: u1 = 0, - /// Priority of interrupt 5 - IP_5: u2, reserved12: u1 = 0, reserved13: u1 = 0, reserved14: u1 = 0, reserved15: u1 = 0, reserved16: u1 = 0, reserved17: u1 = 0, - /// Priority of interrupt 6 - IP_6: u2, reserved18: u1 = 0, reserved19: u1 = 0, reserved20: u1 = 0, reserved21: u1 = 0, - reserved22: u1 = 0, - reserved23: u1 = 0, - /// Priority of interrupt 7 - IP_7: u2, - }), base_address + 0xe404); - - /// address: 0xe000e408 - /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of - /// the available interrupts. 0 is the highest priority, and 3 is the lowest. - pub const NVIC_IPR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - /// Priority of interrupt 8 - IP_8: u2, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - /// Priority of interrupt 9 - IP_9: u2, - reserved12: u1 = 0, - reserved13: u1 = 0, - reserved14: u1 = 0, - reserved15: u1 = 0, - reserved16: u1 = 0, - reserved17: u1 = 0, - /// Priority of interrupt 10 - IP_10: u2, - reserved18: u1 = 0, - reserved19: u1 = 0, - reserved20: u1 = 0, - reserved21: u1 = 0, - reserved22: u1 = 0, - reserved23: u1 = 0, - /// Priority of interrupt 11 - IP_11: u2, - }), base_address + 0xe408); - - /// address: 0xe000e40c - /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of - /// the available interrupts. 0 is the highest priority, and 3 is the lowest. - pub const NVIC_IPR3 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - /// Priority of interrupt 12 - IP_12: u2, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - /// Priority of interrupt 13 - IP_13: u2, - reserved12: u1 = 0, - reserved13: u1 = 0, - reserved14: u1 = 0, - reserved15: u1 = 0, - reserved16: u1 = 0, - reserved17: u1 = 0, - /// Priority of interrupt 14 - IP_14: u2, - reserved18: u1 = 0, - reserved19: u1 = 0, - reserved20: u1 = 0, - reserved21: u1 = 0, - reserved22: u1 = 0, - reserved23: u1 = 0, - /// Priority of interrupt 15 - IP_15: u2, - }), base_address + 0xe40c); - - /// address: 0xe000e410 - /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of - /// the available interrupts. 0 is the highest priority, and 3 is the lowest. - pub const NVIC_IPR4 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - /// Priority of interrupt 16 - IP_16: u2, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - /// Priority of interrupt 17 - IP_17: u2, - reserved12: u1 = 0, - reserved13: u1 = 0, - reserved14: u1 = 0, - reserved15: u1 = 0, - reserved16: u1 = 0, - reserved17: u1 = 0, - /// Priority of interrupt 18 - IP_18: u2, - reserved18: u1 = 0, - reserved19: u1 = 0, - reserved20: u1 = 0, - reserved21: u1 = 0, - reserved22: u1 = 0, - reserved23: u1 = 0, - /// Priority of interrupt 19 - IP_19: u2, - }), base_address + 0xe410); - - /// address: 0xe000e414 - /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of - /// the available interrupts. 0 is the highest priority, and 3 is the lowest. - pub const NVIC_IPR5 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - /// Priority of interrupt 20 - IP_20: u2, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - /// Priority of interrupt 21 - IP_21: u2, - reserved12: u1 = 0, - reserved13: u1 = 0, - reserved14: u1 = 0, - reserved15: u1 = 0, - reserved16: u1 = 0, - reserved17: u1 = 0, - /// Priority of interrupt 22 - IP_22: u2, - reserved18: u1 = 0, - reserved19: u1 = 0, - reserved20: u1 = 0, - reserved21: u1 = 0, - reserved22: u1 = 0, - reserved23: u1 = 0, - /// Priority of interrupt 23 - IP_23: u2, - }), base_address + 0xe414); - - /// address: 0xe000e418 - /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of - /// the available interrupts. 0 is the highest priority, and 3 is the lowest. - pub const NVIC_IPR6 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - /// Priority of interrupt 24 - IP_24: u2, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - /// Priority of interrupt 25 - IP_25: u2, - reserved12: u1 = 0, - reserved13: u1 = 0, - reserved14: u1 = 0, - reserved15: u1 = 0, - reserved16: u1 = 0, - reserved17: u1 = 0, - /// Priority of interrupt 26 - IP_26: u2, - reserved18: u1 = 0, - reserved19: u1 = 0, - reserved20: u1 = 0, - reserved21: u1 = 0, - reserved22: u1 = 0, - reserved23: u1 = 0, - /// Priority of interrupt 27 - IP_27: u2, - }), base_address + 0xe418); - - /// address: 0xe000e41c - /// Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of - /// the available interrupts. 0 is the highest priority, and 3 is the lowest. - pub const NVIC_IPR7 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - /// Priority of interrupt 28 - IP_28: u2, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - /// Priority of interrupt 29 - IP_29: u2, - reserved12: u1 = 0, - reserved13: u1 = 0, - reserved14: u1 = 0, - reserved15: u1 = 0, - reserved16: u1 = 0, - reserved17: u1 = 0, - /// Priority of interrupt 30 - IP_30: u2, - reserved18: u1 = 0, - reserved19: u1 = 0, - reserved20: u1 = 0, - reserved21: u1 = 0, - reserved22: u1 = 0, - reserved23: u1 = 0, - /// Priority of interrupt 31 - IP_31: u2, - }), base_address + 0xe41c); - - /// address: 0xe000ed00 - /// Read the CPU ID Base Register to determine: the ID number of the processor core, - /// the version number of the processor core, the implementation details of the - /// processor core. - pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct { - /// Minor revision number m in the rnpm revision status:\n - /// 0x1 = Patch 1. - REVISION: u4, - /// Number of processor within family: 0xC60 = Cortex-M0+ - PARTNO: u12, - /// Constant that defines the architecture of the processor:\n - /// 0xC = ARMv6-M architecture. - ARCHITECTURE: u4, - /// Major revision number n in the rnpm revision status:\n - /// 0x0 = Revision 0. - VARIANT: u4, - /// Implementor code: 0x41 = ARM - IMPLEMENTER: u8, - }), base_address + 0xed00); - - /// address: 0xe000ed04 - /// Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt - /// (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for - /// pending exceptions, check the vector number of the highest priority pended - /// exception, check the vector number of the active exception. - pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct { - /// Active exception number field. Reset clears the VECTACTIVE field. - VECTACTIVE: u9, - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - /// Indicates the exception number for the highest priority pending exception: 0 = - /// no pending exceptions. Non zero = The pending state includes the effect of - /// memory-mapped enable and mask registers. It does not include the PRIMASK - /// special-purpose register qualifier. - VECTPENDING: u9, - reserved3: u1 = 0, - /// External interrupt pending flag - ISRPENDING: u1, - /// The system can only access this bit when the core is halted. It indicates that a - /// pending interrupt is to be taken in the next running cycle. If C_MASKINTS is - /// clear in the Debug Halting Control and Status Register, the interrupt is - /// serviced. - ISRPREEMPT: u1, - reserved4: u1 = 0, - /// SysTick exception clear-pending bit.\n - /// Write:\n - /// 0 = No effect.\n - /// 1 = Removes the pending state from the SysTick exception.\n - /// This bit is WO. On a register read its value is Unknown. - PENDSTCLR: u1, - /// SysTick exception set-pending bit.\n - /// Write:\n - /// 0 = No effect.\n - /// 1 = Changes SysTick exception state to pending.\n - /// Read:\n - /// 0 = SysTick exception is not pending.\n - /// 1 = SysTick exception is pending. - PENDSTSET: u1, - /// PendSV clear-pending bit.\n - /// Write:\n - /// 0 = No effect.\n - /// 1 = Removes the pending state from the PendSV exception. - PENDSVCLR: u1, - /// PendSV set-pending bit.\n - /// Write:\n - /// 0 = No effect.\n - /// 1 = Changes PendSV exception state to pending.\n - /// Read:\n - /// 0 = PendSV exception is not pending.\n - /// 1 = PendSV exception is pending.\n - /// Writing 1 to this bit is the only way to set the PendSV exception state to - /// pending. - PENDSVSET: u1, - reserved5: u1 = 0, - reserved6: u1 = 0, - /// Setting this bit will activate an NMI. Since NMI is the highest priority - /// exception, it will activate as soon as it is registered.\n - /// NMI set-pending bit.\n - /// Write:\n - /// 0 = No effect.\n - /// 1 = Changes NMI exception state to pending.\n - /// Read:\n - /// 0 = NMI exception is not pending.\n - /// 1 = NMI exception is pending.\n - /// Because NMI is the highest-priority exception, normally the processor enters the - /// NMI\n - /// exception handler as soon as it detects a write of 1 to this bit. Entering the - /// handler then clears\n - /// this bit to 0. This means a read of this bit by the NMI exception handler - /// returns 1 only if the\n - /// NMI signal is reasserted while the processor is executing that handler. - NMIPENDSET: u1, - }), base_address + 0xed04); - - /// address: 0xe000ed08 - /// The VTOR holds the vector table offset address. - pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - reserved6: u1 = 0, - reserved7: u1 = 0, - /// Bits [31:8] of the indicate the vector table offset address. - TBLOFF: u24, - }), base_address + 0xed08); - - /// address: 0xe000ed0c - /// Use the Application Interrupt and Reset Control Register to: determine data - /// endianness, clear all active state information from debug halt mode, request a - /// system reset. - pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - /// Clears all active state information for fixed and configurable exceptions. This - /// bit: is self-clearing, can only be set by the DAP when the core is halted. When - /// set: clears all active exception status of the processor, forces a return to - /// Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack. - VECTCLRACTIVE: u1, - /// Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be - /// asserted to request a reset. The intention is to force a large system reset of - /// all major components except for debug. The C_HALT bit in the DHCSR is cleared as - /// a result of the system reset requested. The debugger does not lose contact with - /// the device. - SYSRESETREQ: u1, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - reserved12: u1 = 0, - /// Data endianness implemented:\n - /// 0 = Little-endian. - ENDIANESS: u1, - /// Register key:\n - /// Reads as Unknown\n - /// On writes, write 0x05FA to VECTKEY, otherwise the write is ignored. - VECTKEY: u16, - }), base_address + 0xed0c); - - /// address: 0xe000ed10 - /// System Control Register. Use the System Control Register for power-management - /// functions: signal to the system when the processor can enter a low power state, - /// control how the processor enters and exits low power states. - pub const SCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - /// Indicates sleep-on-exit when returning from Handler mode to Thread mode:\n - /// 0 = Do not sleep when returning to Thread mode.\n - /// 1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\n - /// Setting this bit to 1 enables an interrupt driven application to avoid returning - /// to an empty main application. - SLEEPONEXIT: u1, - /// Controls whether the processor uses sleep or deep sleep as its low power mode:\n - /// 0 = Sleep.\n - /// 1 = Deep sleep. - SLEEPDEEP: u1, - reserved1: u1 = 0, - /// Send Event on Pending bit:\n - /// 0 = Only enabled interrupts or events can wakeup the processor, disabled - /// interrupts are excluded.\n - /// 1 = Enabled events and all interrupts, including disabled interrupts, can wakeup - /// the processor.\n - /// When an event or interrupt becomes pending, the event signal wakes up the - /// processor from WFE. If the\n - /// processor is not waiting for an event, the event is registered and affects the - /// next WFE.\n - /// The processor also wakes up on execution of an SEV instruction or an external - /// event. - SEVONPEND: u1, - padding0: u1 = 0, - padding1: u1 = 0, - padding2: u1 = 0, - padding3: u1 = 0, - padding4: u1 = 0, - padding5: u1 = 0, - padding6: u1 = 0, - padding7: u1 = 0, - padding8: u1 = 0, - padding9: u1 = 0, - padding10: u1 = 0, - padding11: u1 = 0, - padding12: u1 = 0, - padding13: u1 = 0, - padding14: u1 = 0, - padding15: u1 = 0, - padding16: u1 = 0, - padding17: u1 = 0, - padding18: u1 = 0, - padding19: u1 = 0, - padding20: u1 = 0, - padding21: u1 = 0, - padding22: u1 = 0, - padding23: u1 = 0, - padding24: u1 = 0, - padding25: u1 = 0, - padding26: u1 = 0, - }), base_address + 0xed10); - - /// address: 0xe000ed14 - /// The Configuration and Control Register permanently enables stack alignment and - /// causes unaligned accesses to result in a Hard Fault. - pub const CCR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - /// Always reads as one, indicates that all unaligned accesses generate a HardFault. - UNALIGN_TRP: u1, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - reserved6: u1 = 0, - reserved7: u1 = 0, - /// Always reads as one, indicates 8-byte stack alignment on exception entry. On - /// exception entry, the processor uses bit[9] of the stacked PSR to indicate the - /// stack alignment. On return from the exception it uses this stacked bit to - /// restore the correct stack alignment. - STKALIGN: u1, - padding0: u1 = 0, - padding1: u1 = 0, - padding2: u1 = 0, - padding3: u1 = 0, - padding4: u1 = 0, - padding5: u1 = 0, - padding6: u1 = 0, - padding7: u1 = 0, - padding8: u1 = 0, - padding9: u1 = 0, - padding10: u1 = 0, - padding11: u1 = 0, - padding12: u1 = 0, - padding13: u1 = 0, - padding14: u1 = 0, - padding15: u1 = 0, - padding16: u1 = 0, - padding17: u1 = 0, - padding18: u1 = 0, - padding19: u1 = 0, - padding20: u1 = 0, - padding21: u1 = 0, - }), base_address + 0xed14); - - /// address: 0xe000ed1c - /// System handlers are a special class of exception handler that can have their - /// priority set to any of the priority levels. Use the System Handler Priority - /// Register 2 to set the priority of SVCall. - pub const SHPR2 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - reserved12: u1 = 0, - reserved13: u1 = 0, - reserved14: u1 = 0, - reserved15: u1 = 0, - reserved16: u1 = 0, - reserved17: u1 = 0, - reserved18: u1 = 0, - reserved19: u1 = 0, - reserved20: u1 = 0, - reserved21: u1 = 0, - reserved22: u1 = 0, - reserved23: u1 = 0, - reserved24: u1 = 0, - reserved25: u1 = 0, - reserved26: u1 = 0, - reserved27: u1 = 0, - reserved28: u1 = 0, - reserved29: u1 = 0, - /// Priority of system handler 11, SVCall - PRI_11: u2, - }), base_address + 0xed1c); - - /// address: 0xe000ed20 - /// System handlers are a special class of exception handler that can have their - /// priority set to any of the priority levels. Use the System Handler Priority - /// Register 3 to set the priority of PendSV and SysTick. - pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - reserved12: u1 = 0, - reserved13: u1 = 0, - reserved14: u1 = 0, - reserved15: u1 = 0, - reserved16: u1 = 0, - reserved17: u1 = 0, - reserved18: u1 = 0, - reserved19: u1 = 0, - reserved20: u1 = 0, - reserved21: u1 = 0, - /// Priority of system handler 14, PendSV - PRI_14: u2, + /// Priority of system handler 14, PendSV + PRI_14: u2, reserved22: u1 = 0, reserved23: u1 = 0, reserved24: u1 = 0, @@ -29104,223 +28698,6 @@ pub const registers = struct { /// Priority of system handler 15, SysTick PRI_15: u2, }), base_address + 0xed20); - - /// address: 0xe000ed24 - /// Use the System Handler Control and State Register to determine or clear the - /// pending status of SVCall. - pub const SHCSR = @intToPtr(*volatile Mmio(32, packed struct { - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - reserved6: u1 = 0, - reserved7: u1 = 0, - reserved8: u1 = 0, - reserved9: u1 = 0, - reserved10: u1 = 0, - reserved11: u1 = 0, - reserved12: u1 = 0, - reserved13: u1 = 0, - reserved14: u1 = 0, - /// Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear - /// pending SVCall. - SVCALLPENDED: u1, - padding0: u1 = 0, - padding1: u1 = 0, - padding2: u1 = 0, - padding3: u1 = 0, - padding4: u1 = 0, - padding5: u1 = 0, - padding6: u1 = 0, - padding7: u1 = 0, - padding8: u1 = 0, - padding9: u1 = 0, - padding10: u1 = 0, - padding11: u1 = 0, - padding12: u1 = 0, - padding13: u1 = 0, - padding14: u1 = 0, - padding15: u1 = 0, - }), base_address + 0xed24); - - /// address: 0xe000ed90 - /// Read the MPU Type Register to determine if the processor implements an MPU, and - /// how many regions the MPU supports. - pub const MPU_TYPE = @intToPtr(*volatile Mmio(32, packed struct { - /// Indicates support for separate instruction and data address maps. Reads as 0 as - /// ARMv6-M only supports a unified MPU. - SEPARATE: u1, - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - reserved3: u1 = 0, - reserved4: u1 = 0, - reserved5: u1 = 0, - reserved6: u1 = 0, - /// Number of regions supported by the MPU. - DREGION: u8, - /// Instruction region. Reads as zero as ARMv6-M only supports a unified MPU. - IREGION: u8, - padding0: u1 = 0, - padding1: u1 = 0, - padding2: u1 = 0, - padding3: u1 = 0, - padding4: u1 = 0, - padding5: u1 = 0, - padding6: u1 = 0, - padding7: u1 = 0, - }), base_address + 0xed90); - - /// address: 0xe000ed94 - /// Use the MPU Control Register to enable and disable the MPU, and to control - /// whether the default memory map is enabled as a background region for privileged - /// accesses, and whether the MPU is enabled for HardFaults and NMIs. - pub const MPU_CTRL = @intToPtr(*volatile Mmio(32, packed struct { - /// Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses - /// use the default memory map.\n - /// 0 = MPU disabled.\n - /// 1 = MPU enabled. - ENABLE: u1, - /// Controls the use of the MPU for HardFaults and NMIs. Setting this bit when - /// ENABLE is clear results in UNPREDICTABLE behaviour.\n - /// When the MPU is enabled:\n - /// 0 = MPU is disabled during HardFault and NMI handlers, regardless of the value - /// of the ENABLE bit.\n - /// 1 = the MPU is enabled during HardFault and NMI handlers. - HFNMIENA: u1, - /// Controls whether the default memory map is enabled as a background region for - /// privileged accesses. This bit is ignored when ENABLE is clear.\n - /// 0 = If the MPU is enabled, disables use of the default memory map. Any memory - /// access to a location not\n - /// covered by any enabled region causes a fault.\n - /// 1 = If the MPU is enabled, enables use of the default memory map as a background - /// region for privileged software accesses.\n - /// When enabled, the background region acts as if it is region number -1. Any - /// region that is defined and enabled has priority over this default map. - PRIVDEFENA: u1, - padding0: u1 = 0, - padding1: u1 = 0, - padding2: u1 = 0, - padding3: u1 = 0, - padding4: u1 = 0, - padding5: u1 = 0, - padding6: u1 = 0, - padding7: u1 = 0, - padding8: u1 = 0, - padding9: u1 = 0, - padding10: u1 = 0, - padding11: u1 = 0, - padding12: u1 = 0, - padding13: u1 = 0, - padding14: u1 = 0, - padding15: u1 = 0, - padding16: u1 = 0, - padding17: u1 = 0, - padding18: u1 = 0, - padding19: u1 = 0, - padding20: u1 = 0, - padding21: u1 = 0, - padding22: u1 = 0, - padding23: u1 = 0, - padding24: u1 = 0, - padding25: u1 = 0, - padding26: u1 = 0, - padding27: u1 = 0, - padding28: u1 = 0, - }), base_address + 0xed94); - - /// address: 0xe000ed98 - /// Use the MPU Region Number Register to select the region currently accessed by - /// MPU_RBAR and MPU_RASR. - pub const MPU_RNR = @intToPtr(*volatile Mmio(32, packed struct { - /// Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\n - /// The MPU supports 8 memory regions, so the permitted values of this field are - /// 0-7. - REGION: u4, - padding0: u1 = 0, - padding1: u1 = 0, - padding2: u1 = 0, - padding3: u1 = 0, - padding4: u1 = 0, - padding5: u1 = 0, - padding6: u1 = 0, - padding7: u1 = 0, - padding8: u1 = 0, - padding9: u1 = 0, - padding10: u1 = 0, - padding11: u1 = 0, - padding12: u1 = 0, - padding13: u1 = 0, - padding14: u1 = 0, - padding15: u1 = 0, - padding16: u1 = 0, - padding17: u1 = 0, - padding18: u1 = 0, - padding19: u1 = 0, - padding20: u1 = 0, - padding21: u1 = 0, - padding22: u1 = 0, - padding23: u1 = 0, - padding24: u1 = 0, - padding25: u1 = 0, - padding26: u1 = 0, - padding27: u1 = 0, - }), base_address + 0xed98); - - /// address: 0xe000ed9c - /// Read the MPU Region Base Address Register to determine the base address of the - /// region identified by MPU_RNR. Write to update the base address of said region or - /// that of a specified region, with whose number MPU_RNR will also be updated. - pub const MPU_RBAR = @intToPtr(*volatile Mmio(32, packed struct { - /// On writes, specifies the number of the region whose base address to update - /// provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR. - REGION: u4, - /// On writes, indicates whether the write must update the base address of the - /// region identified by the REGION field, updating the MPU_RNR to indicate this new - /// region.\n - /// Write:\n - /// 0 = MPU_RNR not changed, and the processor:\n - /// Updates the base address for the region specified in the MPU_RNR.\n - /// Ignores the value of the REGION field.\n - /// 1 = The processor:\n - /// Updates the value of the MPU_RNR to the value of the REGION field.\n - /// Updates the base address for the region specified in the REGION field.\n - /// Always reads as zero. - VALID: u1, - reserved0: u1 = 0, - reserved1: u1 = 0, - reserved2: u1 = 0, - /// Base address of the region. - ADDR: u24, - }), base_address + 0xed9c); - - /// address: 0xe000eda0 - /// Use the MPU Region Attribute and Size Register to define the size, access - /// behaviour and memory type of the region identified by MPU_RNR, and enable that - /// region. - pub const MPU_RASR = @intToPtr(*volatile Mmio(32, packed struct { - /// Enables the region. - ENABLE: u1, - /// Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum - /// permitted value is 7 (b00111) = 256Bytes - SIZE: u5, - reserved0: u1 = 0, - reserved1: u1 = 0, - /// Subregion Disable. For regions of 256 bytes or larger, each bit of this field - /// controls whether one of the eight equal subregions is enabled. - SRD: u8, - /// The MPU Region Attribute field. Use to define the region attribute control.\n - /// 28 = XN: Instruction access disable bit:\n - /// 0 = Instruction fetches enabled.\n - /// 1 = Instruction fetches disabled.\n - /// 26:24 = AP: Access permission field\n - /// 18 = S: Shareable bit\n - /// 17 = C: Cacheable bit\n - /// 16 = B: Bufferable bit - ATTRS: u16, - }), base_address + 0xeda0); }; }; @@ -29402,7 +28779,7 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm return @intToPtr(*volatile MmioInt(size, T), addr); } -const InterruptVector = extern union { +pub const InterruptVector = extern union { C: fn () callconv(.C) void, Naked: fn () callconv(.Naked) void, // Interrupt is not supported on arm From 29aee14fd24e50f9f526d19bfdeb643a7665b509 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= Date: Fri, 30 Sep 2022 15:47:46 +0200 Subject: [PATCH 017/286] Update to latest master. (#13) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Co-authored-by: Felix "xq" Queißner --- deps/microzig | 2 +- examples/uart.zig | 2 +- src/hal/pins.zig | 2 +- src/hal/resets.zig | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/deps/microzig b/deps/microzig index 4159581b4..681b3b0d7 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 4159581b4848bfb8bbdf91dabdebd15ecd503427 +Subproject commit 681b3b0d7a6b2fc5d0f8918c583c790c646a31f1 diff --git a/examples/uart.zig b/examples/uart.zig index ed29280b5..7ccbe694a 100644 --- a/examples/uart.zig +++ b/examples/uart.zig @@ -12,7 +12,7 @@ const baud_rate = 115200; const uart_tx_pin = 0; const uart_rx_pin = 1; -pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace) noreturn { +pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn { std.log.err("panic: {s}", .{message}); @breakpoint(); while (true) {} diff --git a/src/hal/pins.zig b/src/hal/pins.zig index ed075944b..baa24799f 100644 --- a/src/hal/pins.zig +++ b/src/hal/pins.zig @@ -5,7 +5,7 @@ const regs = @import("microzig").chip.registers; const assert = std.debug.assert; const comptimePrint = std.fmt.comptimePrint; -const StructField = std.builtin.TypeInfo.StructField; +const StructField = std.builtin.Type.StructField; pub const Pin = enum { GPIO0, diff --git a/src/hal/resets.zig b/src/hal/resets.zig index 0e0ea2bce..5dbd81e1e 100644 --- a/src/hal/resets.zig +++ b/src/hal/resets.zig @@ -2,7 +2,7 @@ const std = @import("std"); const microzig = @import("microzig"); const regs = microzig.chip.registers; -const EnumField = std.builtin.TypeInfo.EnumField; +const EnumField = std.builtin.Type.EnumField; const Mask = @typeInfo(@TypeOf(regs.RESETS.RESET)).Pointer.child.underlying_type; pub const Module = enum { From 7c8d4302378be7d12f7af3f417e04c9a263de722 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 30 Sep 2022 12:27:00 -0700 Subject: [PATCH 018/286] adc bindings, mostly there but not quite (#14) --- build.zig | 1 + examples/adc.zig | 38 ++++++++++ src/hal.zig | 1 + src/hal/adc.zig | 194 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 234 insertions(+) create mode 100644 examples/adc.zig create mode 100644 src/hal/adc.zig diff --git a/build.zig b/build.zig index 01a26ae6e..889455dbb 100644 --- a/build.zig +++ b/build.zig @@ -63,6 +63,7 @@ fn root() []const u8 { } pub const Examples = struct { + adc: microzig.EmbeddedExecutable, blinky: microzig.EmbeddedExecutable, blinky_core1: microzig.EmbeddedExecutable, gpio_clk: microzig.EmbeddedExecutable, diff --git a/examples/adc.zig b/examples/adc.zig new file mode 100644 index 000000000..f8e8c6618 --- /dev/null +++ b/examples/adc.zig @@ -0,0 +1,38 @@ +//! This example takes periodic samples of the temperature sensor and +//! prints it to the UART using the stdlib logging facility. +const std = @import("std"); +const microzig = @import("microzig"); +const rp2040 = microzig.hal; +const adc = rp2040.adc; +const time = rp2040.time; + +const temp_sensor: adc.Input = .temperature_sensor; +const uart_id = 0; +const baud_rate = 115200; +const uart_tx_pin = 0; +const uart_rx_pin = 1; + +pub const log = rp2040.uart.log; + +pub fn init() void { + rp2040.clock_config.apply(); + rp2040.gpio.reset(); + adc.init(); + temp_sensor.init(); + + const uart = rp2040.uart.UART.init(uart_id, .{ + .baud_rate = baud_rate, + .tx_pin = uart_tx_pin, + .rx_pin = uart_rx_pin, + .clock_config = rp2040.clock_config, + }); + + rp2040.uart.initLogger(uart); +} + +pub fn main() void { + while (true) : (time.sleepMs(1000)) { + const sample = temp_sensor.read(); + std.log.info("temp value: {}", .{sample}); + } +} diff --git a/src/hal.zig b/src/hal.zig index 61132bd86..06c0cdd9d 100644 --- a/src/hal.zig +++ b/src/hal.zig @@ -1,6 +1,7 @@ const microzig = @import("microzig"); const regs = microzig.chip.registers; +pub const adc = @import("hal/adc.zig"); pub const pins = @import("hal/pins.zig"); pub const gpio = @import("hal/gpio.zig"); pub const clocks = @import("hal/clocks.zig"); diff --git a/src/hal/adc.zig b/src/hal/adc.zig new file mode 100644 index 000000000..a700651bd --- /dev/null +++ b/src/hal/adc.zig @@ -0,0 +1,194 @@ +//! NOTE: no settling time is needed when switching analog inputs + +const std = @import("std"); +const assert = std.debug.assert; + +const microzig = @import("microzig"); +const ADC = microzig.chip.registers.ADC; +const rp2040 = microzig.hal; +const gpio = rp2040.gpio; +const resets = rp2040.resets; + +pub const temperature_sensor = struct { + pub inline fn init() void { + setTempSensorEnabled(true); + } + + pub inline fn deinit() void { + setTempSensorEnabled(false); + } + + pub inline fn readRaw() u16 { + return Input.read(.temperature_sensor); + } + + // One-shot conversion returning the temperature in Celcius + pub inline fn read(comptime T: type, comptime Vref: T) T { + // TODO: consider fixed-point + const raw = @intToFloat(T, readRaw()); + const voltage: T = Vref * raw / 0x0fff; + return (27.0 - ((voltage - 0.706) / 0.001721)); + } +}; + +pub const Input = enum(u3) { + ain0, + ain1, + ain2, + ain3, + temperature_sensor, + + /// Setup the GPIO pin as an ADC input + pub fn init(comptime input: Input) void { + switch (input) { + .temperature_sensor => setTempSensorEnabled(true), + else => { + const gpio_num = @as(u32, @enumToInt(input)) + 26; + + gpio.setFunction(gpio_num, .@"null"); + // TODO: implement these, otherwise adc isn't going to work. + //gpio.disablePulls(gpio_num); + //gpio.setInputEnabled(gpio_num, false); + }, + } + } + + /// Disables temp sensor, otherwise it does nothing if the input is + /// one of the others. + pub inline fn deinit(input: Input) void { + switch (input) { + .temperature_sensor => setTempSensorEnabled(true), + else => {}, + } + } + + /// Single-shot, blocking conversion + pub fn read(input: Input) u12 { + // TODO: not sure if setting these during the same write is + // correct + ADC.CS.modify(.{ + .AINSEL = @enumToInt(input), + .START_ONCE = 1, + }); + + // wait for the + while (ADC.CS.read().READY == 0) {} + + return ADC.RESULT.read(); + } +}; + +pub const InputMask = InputMask: { + const enum_fields = @typeInfo(Input).Enum.fields; + var fields: [enum_fields.len]std.builtin.Type.StructField = undefined; + + const default_value: u1 = 0; + for (enum_fields) |enum_field, i| + fields[i] = std.builtin.Type.StructField{ + .name = enum_field.name, + .field_type = u1, + .default_value = &default_value, + .is_comptime = false, + .alignment = 1, + }; + + break :InputMask @Type(.{ + .Struct = .{ + .layout = .Packed, + .fields = &fields, + .backing_integer = std.meta.Int(.Unsigned, enum_fields.len), + .decls = &.{}, + .is_tuple = false, + }, + }); +}; + +/// Initialize ADC hardware +pub fn init() void { + resets.reset(&.{.adc}); + ADC.CS.write(.{ + .EN = 1, + .TS_EN = 0, + .START_ONCE = 0, + .START_MANY = 0, + .READY = 0, + .ERR = 0, + .ERR_STICKY = 0, + .AINSEL = 0, + .RROBIN = 0, + }); + + while (ADC.CS.read().READY == 0) {} +} + +/// Enable/disable ADC interrupt +pub inline fn irqSetEnabled(enable: bool) void { + // TODO: check if this works + ADC.INTE.write(.{ .FIFO = if (enable) @as(u1, 1) else @as(u1, 0) }); +} + +/// Select analog input for next conversion. +pub inline fn selectInput(input: Input) void { + ADC.CS.modify(.{ .AINSEL = @enumToInt(input) }); +} + +/// Get the currently selected analog input. 0..3 are GPIO 26..29 respectively, +/// 4 is the temperature sensor. +pub inline fn getSelectedInput() Input { + // TODO: ensure that the field shouldn't have other values + return @intToEnum(Input, ADC.CS.read().AINSEL); +} + +/// Set to true to power on the temperature sensor. +pub inline fn setTempSensorEnabled(enable: bool) void { + ADC.CS.modify(.{ .TS_EN = if (enable) @as(u1, 1) else @as(u1, 0) }); +} + +/// Sets which of the inputs are to be run in round-robin mode. Setting all to +/// 0 will disable round-robin mode but `disableRoundRobin()` is provided so +/// the user may be explicit. +pub inline fn setRoundRobin(comptime enabled_inputs: InputMask) void { + ADC.CS.modify(.{ .RROBIN = @bitCast(u5, enabled_inputs) }); +} + +/// Disable round-robin sample mode. +pub inline fn disableRoundRobin() void { + ADC.CS.modify(.{ .RROBIN = 0 }); +} + +/// Enable free-running sample mode. +pub inline fn run(enable: bool) void { + ADC.CS.modify(.{ .START_MANY = if (enable) @as(u1, 1) else @as(u1, 0) }); +} + +/// TODO: implement +pub inline fn setClkDiv() void {} + +/// The fifo is 4 samples long, if a conversion is completed and the FIFO is +/// full, the result is dropped. +pub const fifo = struct { + /// TODO: implement + pub inline fn setup() void { + // There are a number of considerations wrt DMA and error detection + } + + /// TODO: implement + /// Return true if FIFO is empty. + pub inline fn isEmpty() bool {} + + /// TODO: implement + /// Read how many samples are in the FIFO. + pub inline fn getLevel() u8 {} + + /// TODO: implement + /// Pop latest result from FIFO. + pub inline fn get() u16 {} + + /// TODO: implement + /// Block until result is available in FIFO, then pop it. + pub inline fn getBlocking() u16 {} + + /// TODO: implement + /// Wait for conversion to complete then discard results in FIFO. + pub inline fn drain() void {} +}; From 5c853fd23ad400ecb748fba7acb2cc2c0a77c053 Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Fri, 30 Sep 2022 12:32:37 -0700 Subject: [PATCH 019/286] use compile errors instead of comments (#15) --- src/hal/adc.zig | 32 +++++++++++++++++++------------- 1 file changed, 19 insertions(+), 13 deletions(-) diff --git a/src/hal/adc.zig b/src/hal/adc.zig index a700651bd..84b99a7d1 100644 --- a/src/hal/adc.zig +++ b/src/hal/adc.zig @@ -161,34 +161,40 @@ pub inline fn run(enable: bool) void { ADC.CS.modify(.{ .START_MANY = if (enable) @as(u1, 1) else @as(u1, 0) }); } -/// TODO: implement -pub inline fn setClkDiv() void {} +pub inline fn setClkDiv() void { + @compileError("todo"); +} /// The fifo is 4 samples long, if a conversion is completed and the FIFO is /// full, the result is dropped. pub const fifo = struct { - /// TODO: implement pub inline fn setup() void { + @compileError("todo"); // There are a number of considerations wrt DMA and error detection } - /// TODO: implement /// Return true if FIFO is empty. - pub inline fn isEmpty() bool {} + pub inline fn isEmpty() bool { + @compileError("todo"); + } - /// TODO: implement /// Read how many samples are in the FIFO. - pub inline fn getLevel() u8 {} + pub inline fn getLevel() u8 { + @compileError("todo"); + } - /// TODO: implement /// Pop latest result from FIFO. - pub inline fn get() u16 {} + pub inline fn get() u16 { + @compileError("todo"); + } - /// TODO: implement /// Block until result is available in FIFO, then pop it. - pub inline fn getBlocking() u16 {} + pub inline fn getBlocking() u16 { + @compileError("todo"); + } - /// TODO: implement /// Wait for conversion to complete then discard results in FIFO. - pub inline fn drain() void {} + pub inline fn drain() void { + @compileError("todo"); + } }; From fe14d4f03b3f2cd5a989bcf497182cd0a140c4ca Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= Date: Sat, 1 Oct 2022 14:05:57 +0200 Subject: [PATCH 020/286] Implements input, pull up/down and uart routing. --- build.zig | 2 +- src/hal/gpio.zig | 8 ++++++++ src/hal/pins.zig | 43 ++++++++++++++++++++++++++++++++++++++++--- 3 files changed, 49 insertions(+), 4 deletions(-) diff --git a/build.zig b/build.zig index 889455dbb..d00c9621b 100644 --- a/build.zig +++ b/build.zig @@ -3,7 +3,7 @@ const Builder = std.build.Builder; const Pkg = std.build.Pkg; const comptimePrint = std.fmt.comptimePrint; -const microzig = @import("deps/microzig/src/main.zig"); +pub const microzig = @import("deps/microzig/src/main.zig"); const chip_path = comptimePrint("{s}/src/rp2040.zig", .{root()}); const board_path = comptimePrint("{s}/src/raspberry_pi_pico.zig", .{root()}); diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig index 18624eea9..90e214177 100644 --- a/src/hal/gpio.zig +++ b/src/hal/gpio.zig @@ -97,6 +97,14 @@ pub inline fn toggle(comptime gpio: u32) void { regs.SIO.GPIO_OUT_XOR.raw = (1 << gpio); } +pub inline fn read(comptime gpio: u32) u1 { + const mask = 1 << gpio; + return if ((regs.SIO.GPIO_IN.raw & mask) != 0) + 1 + else + 0; +} + pub inline fn setFunction(comptime gpio: u32, function: Function) void { const pad_bank_reg = comptime std.fmt.comptimePrint("GPIO{}", .{gpio}); @field(regs.PADS_BANK0, pad_bank_reg).modify(.{ diff --git a/src/hal/pins.zig b/src/hal/pins.zig index baa24799f..6980bfc2b 100644 --- a/src/hal/pins.zig +++ b/src/hal/pins.zig @@ -50,11 +50,15 @@ pub const Pin = enum { // schmitt trigger // hysteresis - pub fn getDirection(config: Configuration) gpio.Direction { + pub fn getDirection(comptime config: Configuration) gpio.Direction { return if (config.direction) |direction| direction - else if (config.function.isPwm()) + else if (comptime config.function.isPwm()) .out + else if (comptime config.function.isUartTx()) + .out + else if (comptime config.function.isUartRx()) + .in else @panic("TODO"); } @@ -157,6 +161,24 @@ pub const Function = enum { }; } + pub fn isUartTx(function: Function) bool { + return switch (function) { + .UART0_TX, + .UART1_TX, + => true, + else => false, + }; + } + + pub fn isUartRx(function: Function) bool { + return switch (function) { + .UART0_RX, + .UART1_RX, + => true, + else => false, + }; + } + pub fn pwmSlice(comptime function: Function) u32 { return switch (function) { .PWM0_A, .PWM0_B => 0, @@ -280,7 +302,7 @@ pub fn GPIO(comptime num: u5, comptime direction: gpio.Direction) type { pub inline fn read(self: @This()) u1 { _ = self; - @compileError("TODO"); + return gpio.read(gpio_num); } }, .out => struct { @@ -424,6 +446,21 @@ pub const GlobalConfiguration = struct { if (output_gpios != 0) regs.SIO.GPIO_OE_SET.raw = output_gpios; + if (input_gpios != 0) { + inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| + if (@field(config, field.name)) |pin_config| { + const pull = pin_config.pull orelse continue; + if (comptime pin_config.getDirection() != .in) + @compileError("Only input pins can have pull up/down enabled"); + + const gpio_regs = @field(regs.PADS_BANK0, field.name); + gpio_regs.modify(comptime .{ + .PUE = @boolToInt(pull == .up), + .PDE = @boolToInt(pull == .down), + }); + }; + } + // TODO: pwm initialization // fields in the Pins(config) type should be zero sized, so we just From a55df1b52c28a4d0f4eff6e2abfcdeddbf6e5eed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= Date: Sat, 1 Oct 2022 21:03:21 +0200 Subject: [PATCH 021/286] Some debug logs in adc.reset() and resets.reset(), fixes some bugs with booleans. --- src/hal/adc.zig | 5 ++++- src/hal/pwm.zig | 9 +++++---- src/hal/resets.zig | 26 +++++++++++++++++++++++++- 3 files changed, 34 insertions(+), 6 deletions(-) diff --git a/src/hal/adc.zig b/src/hal/adc.zig index 84b99a7d1..92869fcf9 100644 --- a/src/hal/adc.zig +++ b/src/hal/adc.zig @@ -105,7 +105,9 @@ pub const InputMask = InputMask: { /// Initialize ADC hardware pub fn init() void { + std.log.info("init.a", .{}); resets.reset(&.{.adc}); + std.log.info("init.b", .{}); ADC.CS.write(.{ .EN = 1, .TS_EN = 0, @@ -117,8 +119,9 @@ pub fn init() void { .AINSEL = 0, .RROBIN = 0, }); - + std.log.info("init.c", .{}); while (ADC.CS.read().READY == 0) {} + std.log.info("init.d", .{}); } /// Enable/disable ADC interrupt diff --git a/src/hal/pwm.zig b/src/hal/pwm.zig index 45cf90b37..8d2857300 100644 --- a/src/hal/pwm.zig +++ b/src/hal/pwm.zig @@ -8,7 +8,8 @@ pub const Config = struct {}; fn getRegs(comptime slice: u32) *volatile Regs { @import("std").debug.assert(slice < 8); - return @intToPtr(*volatile Regs, regs.PWM.base_address); // + (slice * 0x14)); + const reg_diff = comptime (@ptrToInt(regs.PWM.CH1_CSR) - @ptrToInt(regs.PWM.CH0_CSR)); + return @intToPtr(*volatile Regs, regs.PWM.base_address + reg_diff * slice); } pub fn PWM(comptime slice_num: u32, comptime chan: Channel) type { @@ -72,7 +73,7 @@ const Regs = extern struct { pub inline fn setSlicePhaseCorrect(comptime slice: u32, phase_correct: bool) void { log.debug("PWM{} set phase correct: {}", .{ slice, phase_correct }); getRegs(slice).csr.modify(.{ - .PH_CORRECT = if (phase_correct) 1 else 0, + .PH_CORRECT = @boolToInt(phase_correct), }); } @@ -98,10 +99,10 @@ pub inline fn setChannelInversion( ) void { switch (channel) { .a => getRegs(slice).csr.modify(.{ - .A_INV = if (invert) 1 else 0, + .A_INV = @boolToInt(invert), }), .b => getRegs(slice).csr.modifi(.{ - .B_INV = if (invert) 1 else 0, + .B_INV = @boolToInt(invert), }), } } diff --git a/src/hal/resets.zig b/src/hal/resets.zig index 5dbd81e1e..a4aae840f 100644 --- a/src/hal/resets.zig +++ b/src/hal/resets.zig @@ -40,8 +40,32 @@ pub inline fn reset(comptime modules: []const Module) void { @field(mask, @tagName(module)) = 1; const raw_mask = @bitCast(u32, mask); + + // std.log.info("resets done before: {X:0>8} ", .{regs.RESETS.RESET_DONE.raw}); + + // std.log.info("reset on", .{}); regs.RESETS.RESET.raw = raw_mask; + // std.log.info("=> {X:0>8}\n", .{regs.RESETS.RESET.raw}); + // std.log.info("reset off", .{}); + asm volatile ("nop" ::: "memory"); // delay at least a bit regs.RESETS.RESET.raw = 0; + // std.log.info("=> {X:0>8}\n", .{regs.RESETS.RESET.raw}); + + // std.log.info("reset wait", .{}); + + var last: u32 = 0; + while (true) { + const raw = regs.RESETS.RESET_DONE.raw; + if (last != raw) { + // std.log.info("raw: {X:0>8} {X:0>8}", .{ raw, raw & raw_mask }); + last = raw; + } + if ((raw & raw_mask) == raw_mask) + break; + asm volatile ("" ::: "memory"); + } + + // std.log.info("resets done after: {X:0>8}", .{regs.RESETS.RESET_DONE.raw}); - while (regs.RESETS.RESET_DONE.raw & raw_mask != raw_mask) {} + // std.log.info("reset done", .{}); } From c899778c875d103ab243046c6aa64bbddd839e5a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= Date: Sun, 2 Oct 2022 00:10:13 +0200 Subject: [PATCH 022/286] Clock setup fixes. --- src/hal/clocks.zig | 18 +++++++++++------- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git a/src/hal/clocks.zig b/src/hal/clocks.zig index 3553572cf..eae16a804 100644 --- a/src/hal/clocks.zig +++ b/src/hal/clocks.zig @@ -56,8 +56,8 @@ fn uppercase(bytes: []const u8) std.fmt.Formatter(formatUppercase) { return .{ .data = bytes }; } -pub const Generator = enum { - gpout0, +pub const Generator = enum(u32) { + gpout0 = 0, gpout1, gpout2, gpout3, @@ -70,7 +70,7 @@ pub const Generator = enum { // in some cases we can pretend the Generators are a homogenous array of // register clusters for the sake of smaller codegen - const GeneratorRegs = packed struct { + const GeneratorRegs = extern struct { ctrl: u32, div: u32, selected: u32, @@ -82,7 +82,7 @@ pub const Generator = enum { } const generators = @intToPtr( - *volatile [9]GeneratorRegs, + *volatile [10]GeneratorRegs, regs.CLOCKS.base_address, ); @@ -154,6 +154,7 @@ pub const Generator = enum { } pub fn setSource(generator: Generator, src: u32) void { + std.debug.assert(generator.hasGlitchlessMux()); const gen_regs = generator.getRegs(); const mask = ~@as(u32, 0x3); const ctrl_value = gen_regs.ctrl; @@ -314,9 +315,12 @@ pub const GlobalConfiguration = struct { .clk_sys => if (config.sys) |sys_config| sys_config.output_freq else null, .clk_usb => if (config.usb) |usb_config| usb_config.output_freq else null, .clk_ref => if (config.ref) |ref_config| ref_config.output_freq else null, + .clk_adc => if (config.adc) |adc_config| adc_config.output_freq else null, + .clk_rtc => if (config.rtc) |rtc_config| rtc_config.output_freq else null, .pll_sys => if (config.pll_sys) |pll_sys_config| pll_sys_config.frequency() else null, .pll_usb => if (config.pll_usb) |pll_usb_config| pll_usb_config.frequency() else null, - else => null, + + .src_gpin0, .src_gpin1 => null, }; } @@ -462,7 +466,7 @@ pub const GlobalConfiguration = struct { } break :adc_config .{ - .generator = .usb, + .generator = .adc, .input = .{ .source = .pll_usb, .freq = 48_000_000, @@ -493,7 +497,7 @@ pub const GlobalConfiguration = struct { } break :rtc_config .{ - .generator = .usb, + .generator = .rtc, .input = .{ .source = .pll_usb, .freq = 48_000_000, From 5c07800cdbf9b4369f6442482729e766a180a97b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= Date: Sun, 2 Oct 2022 00:14:52 +0200 Subject: [PATCH 023/286] Removes debug code. --- src/hal/adc.zig | 4 ---- src/hal/resets.zig | 25 +------------------------ 2 files changed, 1 insertion(+), 28 deletions(-) diff --git a/src/hal/adc.zig b/src/hal/adc.zig index 92869fcf9..3cf29fab0 100644 --- a/src/hal/adc.zig +++ b/src/hal/adc.zig @@ -105,9 +105,7 @@ pub const InputMask = InputMask: { /// Initialize ADC hardware pub fn init() void { - std.log.info("init.a", .{}); resets.reset(&.{.adc}); - std.log.info("init.b", .{}); ADC.CS.write(.{ .EN = 1, .TS_EN = 0, @@ -119,9 +117,7 @@ pub fn init() void { .AINSEL = 0, .RROBIN = 0, }); - std.log.info("init.c", .{}); while (ADC.CS.read().READY == 0) {} - std.log.info("init.d", .{}); } /// Enable/disable ADC interrupt diff --git a/src/hal/resets.zig b/src/hal/resets.zig index a4aae840f..45b22305a 100644 --- a/src/hal/resets.zig +++ b/src/hal/resets.zig @@ -41,31 +41,8 @@ pub inline fn reset(comptime modules: []const Module) void { const raw_mask = @bitCast(u32, mask); - // std.log.info("resets done before: {X:0>8} ", .{regs.RESETS.RESET_DONE.raw}); - - // std.log.info("reset on", .{}); regs.RESETS.RESET.raw = raw_mask; - // std.log.info("=> {X:0>8}\n", .{regs.RESETS.RESET.raw}); - // std.log.info("reset off", .{}); - asm volatile ("nop" ::: "memory"); // delay at least a bit regs.RESETS.RESET.raw = 0; - // std.log.info("=> {X:0>8}\n", .{regs.RESETS.RESET.raw}); - - // std.log.info("reset wait", .{}); - - var last: u32 = 0; - while (true) { - const raw = regs.RESETS.RESET_DONE.raw; - if (last != raw) { - // std.log.info("raw: {X:0>8} {X:0>8}", .{ raw, raw & raw_mask }); - last = raw; - } - if ((raw & raw_mask) == raw_mask) - break; - asm volatile ("" ::: "memory"); - } - - // std.log.info("resets done after: {X:0>8}", .{regs.RESETS.RESET_DONE.raw}); - // std.log.info("reset done", .{}); + while ((regs.RESETS.RESET_DONE.raw & raw_mask) != raw_mask) {} } From 86d383e67366dd691974f3688cb40759169f41c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= Date: Sun, 2 Oct 2022 16:57:26 +0200 Subject: [PATCH 024/286] Implements ADC and PWM support in pin config, simplifies Pins() type. --- src/hal/gpio.zig | 2 +- src/hal/pins.zig | 180 +++++++++++++++++++++++++++++++++-------------- src/hal/uart.zig | 8 +-- 3 files changed, 134 insertions(+), 56 deletions(-) diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig index 90e214177..eebb0933b 100644 --- a/src/hal/gpio.zig +++ b/src/hal/gpio.zig @@ -7,7 +7,7 @@ const assert = std.debug.assert; const log = std.log.scoped(.gpio); pub const Function = enum(u5) { - xip, + xip = 0, spi, uart, i2c, diff --git a/src/hal/pins.zig b/src/hal/pins.zig index 6980bfc2b..9194a016a 100644 --- a/src/hal/pins.zig +++ b/src/hal/pins.zig @@ -1,6 +1,8 @@ const std = @import("std"); const gpio = @import("gpio.zig"); const pwm = @import("pwm.zig"); +const adc = @import("adc.zig"); +const resets = @import("resets.zig"); const regs = @import("microzig").chip.registers; const assert = std.debug.assert; @@ -59,6 +61,8 @@ pub const Pin = enum { .out else if (comptime config.function.isUartRx()) .in + else if (comptime config.function.isAdc()) + .in else @panic("TODO"); } @@ -193,6 +197,17 @@ pub const Function = enum { }; } + pub fn isAdc(function: Function) bool { + return switch (function) { + .ADC0, + .ADC1, + .ADC2, + .ADC3, + => true, + else => false, + }; + } + pub fn pwmChannel(comptime function: Function) pwm.Channel { return switch (function) { .PWM0_A, @@ -322,53 +337,66 @@ pub fn GPIO(comptime num: u5, comptime direction: gpio.Direction) type { } pub fn Pins(comptime config: GlobalConfiguration) type { - const count = count: { - var ret: usize = 0; - inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| { - if (@field(config, field.name)) |pin_config| - if (pin_config.function == .SIO or pin_config.function.isPwm()) { - ret += 1; - }; - } - - break :count ret; - }; - - var i: usize = 0; - var fields: [count]StructField = undefined; - inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| { - if (@field(config, field.name)) |pin_config| - if (pin_config.function == .SIO) { - fields[i] = StructField{ - .name = pin_config.name orelse field.name, - .field_type = GPIO(@enumToInt(@field(Pin, field.name)), pin_config.direction orelse .in), + comptime { + var fields: []const StructField = &.{}; + for (@typeInfo(GlobalConfiguration).Struct.fields) |field| { + if (@field(config, field.name)) |pin_config| { + var pin_field = StructField{ .is_comptime = false, .default_value = null, - .alignment = 1, - }; - i += 1; - } else if (pin_config.function.isPwm()) { - fields[i] = StructField{ - .name = pin_config.name orelse @tagName(pin_config.function), - .field_type = pwm.PWM(pin_config.function.pwmSlice(), pin_config.function.pwmChannel()), - .is_comptime = false, - .default_value = null, - .alignment = 1, + // initialized below: + .name = undefined, + .field_type = undefined, + .alignment = undefined, }; - i += 1; - }; - } + if (pin_config.function == .SIO) { + pin_field.name = pin_config.name orelse field.name; + pin_field.field_type = GPIO(@enumToInt(@field(Pin, field.name)), pin_config.direction orelse .in); + } else if (pin_config.function.isPwm()) { + pin_field.name = pin_config.name orelse @tagName(pin_config.function); + pin_field.field_type = pwm.PWM(pin_config.function.pwmSlice(), pin_config.function.pwmChannel()); + } else if (pin_config.function.isAdc()) { + pin_field.name = pin_config.name orelse @tagName(pin_config.function); + pin_field.field_type = adc.Input; + pin_field.default_value = @ptrCast(?*const anyopaque, switch (pin_config.function) { + .ADC0 => &adc.Input.ain0, + .ADC1 => &adc.Input.ain1, + .ADC2 => &adc.Input.ain2, + .ADC3 => &adc.Input.ain3, + else => unreachable, + }); + } else { + continue; + } + + // if (pin_field.default_value == null) { + // if (@sizeOf(pin_field.field_type) > 0) { + // pin_field.default_value = @ptrCast(?*const anyopaque, &pin_field.field_type{}); + // } else { + // const Struct = struct { + // magic_field: pin_field.field_type = .{}, + // }; + // pin_field.default_value = @typeInfo(Struct).Struct.fields[0].default_value; + // } + // } + + pin_field.alignment = @alignOf(field.field_type); + + fields = fields ++ &[_]StructField{pin_field}; + } + } - return @Type(.{ - .Struct = .{ - .layout = .Auto, - .is_tuple = false, - .fields = &fields, - .decls = &.{}, - }, - }); + return @Type(.{ + .Struct = .{ + .layout = .Auto, + .is_tuple = false, + .fields = fields, + .decls = &.{}, + }, + }); + } } pub const GlobalConfiguration = struct { @@ -413,6 +441,8 @@ pub const GlobalConfiguration = struct { pub fn apply(comptime config: GlobalConfiguration) Pins(config) { comptime var input_gpios: u32 = 0; comptime var output_gpios: u32 = 0; + comptime var has_adc = false; + comptime var has_pwm = false; // validate selected function comptime { @@ -422,12 +452,22 @@ pub const GlobalConfiguration = struct { if (0 == function_table[@enumToInt(pin_config.function)][gpio_num]) @compileError(comptimePrint("{s} cannot be configured for {}", .{ field.name, pin_config.function })); - switch (pin_config.getDirection()) { - .in => input_gpios |= 1 << gpio_num, - .out => output_gpios |= 1 << gpio_num, + if (pin_config.function == .SIO) { + switch (pin_config.getDirection()) { + .in => input_gpios |= 1 << gpio_num, + .out => output_gpios |= 1 << gpio_num, + } + } + + if (pin_config.function.isAdc()) { + has_adc = true; + } + if (pin_config.function.isPwm()) { + has_pwm = true; } }; } + // TODO: ensure only one instance of an input function exists const used_gpios = comptime input_gpios | output_gpios; @@ -436,11 +476,38 @@ pub const GlobalConfiguration = struct { if (used_gpios != 0) { regs.SIO.GPIO_OE_CLR.raw = used_gpios; regs.SIO.GPIO_OUT_CLR.raw = used_gpios; + } - comptime var i: u32 = 0; - inline while (i < 32) : (i += 1) - if (0 != used_gpios & 1 << i) - gpio.setFunction(i, .sio); + inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| { + if (@field(config, field.name)) |pin_config| { + const gpio_num = @enumToInt(@field(Pin, field.name)); + const func = pin_config.function; + + // xip = 0, + // spi, + // uart, + // i2c, + // pio0, + // pio1, + // gpck, + // usb, + // @"null" = 0x1f, + + if (func == .SIO) { + gpio.setFunction(gpio_num, .sio); + } else if (comptime func.isPwm()) { + gpio.setFunction(gpio_num, .pwm); + } else if (comptime func.isAdc()) { + gpio.setFunction(gpio_num, .@"null"); + } else if (comptime func.isUartTx() or func.isUartRx()) { + gpio.setFunction(gpio_num, .uart); + } else { + @compileError(comptime std.fmt.comptimePrint("Unimplemented pin function. Please implement setting pin function {s} for GPIO {}", .{ + @tagName(func), + gpio_num, + })); + } + } } if (output_gpios != 0) @@ -461,14 +528,25 @@ pub const GlobalConfiguration = struct { }; } - // TODO: pwm initialization + if (has_pwm) { + resets.reset(&.{.pwm}); + } + + if (has_adc) { + adc.init(); + } // fields in the Pins(config) type should be zero sized, so we just // default build them all (wasn't sure how to do that cleanly in // `Pins()` var ret: Pins(config) = undefined; - inline for (@typeInfo(Pins(config)).Struct.fields) |field| - @field(ret, field.name) = .{}; + inline for (@typeInfo(Pins(config)).Struct.fields) |field| { + if (field.default_value) |default_value| { + @field(ret, field.name) = @ptrCast(*const field.field_type, default_value).*; + } else { + @field(ret, field.name) = .{}; + } + } return ret; } diff --git a/src/hal/uart.zig b/src/hal/uart.zig index 5f3f8c61f..49de5fc28 100644 --- a/src/hal/uart.zig +++ b/src/hal/uart.zig @@ -28,8 +28,8 @@ pub const Parity = enum { pub const Config = struct { clock_config: clocks.GlobalConfiguration, - tx_pin: u32, - rx_pin: u32, + tx_pin: ?u32 = null, + rx_pin: ?u32 = null, baud_rate: u32, word_bits: WordBits = .eight, stop_bits: StopBits = .one, @@ -116,8 +116,8 @@ pub const UART = enum { }); // TODO comptime assertions - gpio.setFunction(config.tx_pin, .uart); - gpio.setFunction(config.rx_pin, .uart); + if (config.tx_pin) |tx_pin| gpio.setFunction(tx_pin, .uart); + if (config.rx_pin) |rx_pin| gpio.setFunction(rx_pin, .uart); return uart; } From 7b69211d4113cf2914a3e5c400357cea46b81ffa Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= Date: Mon, 3 Oct 2022 18:14:37 +0200 Subject: [PATCH 025/286] Implements gpio.setPullUpDown --- src/hal/gpio.zig | 17 +++++++++++++++++ src/hal/pins.zig | 9 +++------ 2 files changed, 20 insertions(+), 6 deletions(-) diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig index eebb0933b..e725d79fa 100644 --- a/src/hal/gpio.zig +++ b/src/hal/gpio.zig @@ -75,6 +75,23 @@ pub inline fn deinit(comptime gpio: u32) void { setFunction(gpio, .@"null"); } +pub const PullUpDown = enum { + up, + down, +}; + +pub inline fn setPullUpDown(comptime gpio: u32, mode: ?PullUpDown) void { + const gpio_name = comptime std.fmt.comptimePrint("GPIO{d}", .{gpio}); + const gpio_regs = @field(regs.PADS_BANK0, gpio_name); + + if (mode == null) { + gpio_regs.modify(.{ .PUE = 0, .PDE = 0 }); + } else switch (mode.?) { + .up => gpio_regs.modify(.{ .PUE = 1, .PDE = 0 }), + .down => gpio_regs.modify(.{ .PUE = 0, .PDE = 1 }), + } +} + pub inline fn setDir(comptime gpio: u32, direction: Direction) void { const mask = 1 << gpio; switch (direction) { diff --git a/src/hal/pins.zig b/src/hal/pins.zig index 9194a016a..94f6caa5d 100644 --- a/src/hal/pins.zig +++ b/src/hal/pins.zig @@ -46,7 +46,7 @@ pub const Pin = enum { function: Function = .SIO, direction: ?gpio.Direction = null, drive_strength: ?gpio.DriveStrength = null, - pull: ?enum { up, down } = null, + pull: ?gpio.PullUpDown = null, slew_rate: ?gpio.SlewRate = null, // input/output enable // schmitt trigger @@ -516,15 +516,12 @@ pub const GlobalConfiguration = struct { if (input_gpios != 0) { inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| if (@field(config, field.name)) |pin_config| { + const gpio_num = @enumToInt(@field(Pin, field.name)); const pull = pin_config.pull orelse continue; if (comptime pin_config.getDirection() != .in) @compileError("Only input pins can have pull up/down enabled"); - const gpio_regs = @field(regs.PADS_BANK0, field.name); - gpio_regs.modify(comptime .{ - .PUE = @boolToInt(pull == .up), - .PDE = @boolToInt(pull == .down), - }); + gpio.setPullUpDown(gpio_num, pull); }; } From b0b90a7cf07704dfef94b17b8be2393479c68192 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= Date: Mon, 3 Oct 2022 19:11:42 +0200 Subject: [PATCH 026/286] Implements UART.reader() --- deps/microzig | 2 +- src/hal/uart.zig | 15 +++++++++++++++ 2 files changed, 16 insertions(+), 1 deletion(-) diff --git a/deps/microzig b/deps/microzig index 681b3b0d7..15bc1fc06 160000 --- a/deps/microzig +++ b/deps/microzig @@ -1 +1 @@ -Subproject commit 681b3b0d7a6b2fc5d0f8918c583c790c646a31f1 +Subproject commit 15bc1fc06da3b6c622a21fa438e40be247d9dee1 diff --git a/src/hal/uart.zig b/src/hal/uart.zig index 49de5fc28..328524987 100644 --- a/src/hal/uart.zig +++ b/src/hal/uart.zig @@ -75,12 +75,18 @@ pub const UART = enum { uart1, const WriteError = error{}; + const ReadError = error{}; pub const Writer = std.io.Writer(UART, WriteError, write); + pub const Reader = std.io.Reader(UART, ReadError, read); pub fn writer(uart: UART) Writer { return .{ .context = uart }; } + pub fn reader(uart: UART) Reader { + return .{ .context = uart }; + } + fn getRegs(uart: UART) *volatile UartRegs { return &uarts[@enumToInt(uart)]; } @@ -142,6 +148,15 @@ pub const UART = enum { return payload.len; } + pub fn read(uart: UART, buffer: []u8) ReadError!usize { + const uart_regs = uart.getRegs(); + for (buffer) |*byte| { + while (!uart.isReadable()) {} + byte.* = @truncate(u8, uart_regs.dr); + } + return buffer.len; + } + pub fn readWord(uart: UART) u8 { const uart_regs = uart.getRegs(); while (!uart.isReadable()) {} From e9af302b69a58a50b25cda9c75580702df859b5d Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Wed, 5 Oct 2022 10:58:03 +0200 Subject: [PATCH 027/286] uart improvements and improved definition of how many clock units there are (#16) --- src/hal/clocks.zig | 2 +- src/hal/uart.zig | 14 ++++++++++++++ 2 files changed, 15 insertions(+), 1 deletion(-) diff --git a/src/hal/clocks.zig b/src/hal/clocks.zig index eae16a804..e703db46a 100644 --- a/src/hal/clocks.zig +++ b/src/hal/clocks.zig @@ -82,7 +82,7 @@ pub const Generator = enum(u32) { } const generators = @intToPtr( - *volatile [10]GeneratorRegs, + *volatile [@typeInfo(Generator).Enum.fields.len]GeneratorRegs, regs.CLOCKS.base_address, ); diff --git a/src/hal/uart.zig b/src/hal/uart.zig index 328524987..6616452cd 100644 --- a/src/hal/uart.zig +++ b/src/hal/uart.zig @@ -226,6 +226,7 @@ var uart_logger: ?UART.Writer = null; pub fn initLogger(uart: UART) void { uart_logger = uart.writer(); + uart_logger.?.writeAll("\r\n================ STARTING NEW LOGGER ================\r\n") catch {}; } pub fn log( @@ -248,3 +249,16 @@ pub fn log( uart.print(prefix ++ format ++ "\r\n", .{ seconds, microseconds } ++ args) catch {}; } } + +pub fn panic( + message: []const u8, + _: ?*std.builtin.StackTrace, + _: ?usize, +) noreturn { + if (uart_logger) |writer| { + writer.print("PANIC: {s}\r\n", .{message}) catch {}; + } + + @breakpoint(); + while (true) {} +} From 0f10a5d8f5be3a9dc23411fe9c05987f7f80384b Mon Sep 17 00:00:00 2001 From: Matt Knight Date: Sat, 8 Oct 2022 10:10:30 +0200 Subject: [PATCH 028/286] Initial commit --- LICENSE | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) create mode 100644 LICENSE diff --git a/LICENSE b/LICENSE new file mode 100644 index 000000000..4818f98dd --- /dev/null +++ b/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2022 Zig Embedded Group + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. From 58cfb98e80f8826980338a7c557d6fde6f9801f6 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= Date: Sat, 8 Oct 2022 10:16:46 +0200 Subject: [PATCH 029/286] Initial vomit: not working at all, basic docs. --- .gitattributes | 1 + .github/FUNDING.yml | 1 + .gitignore | 2 ++ .gitmodules | 3 +++ README.md | 1 + build.zig | 34 ++++++++++++++++++++++++++++++++++ docs/esp32-c3-32s-pinout.png | Bin 0 -> 228243 bytes docs/esp32-c3-32s-pinout.xcf | Bin 0 -> 937723 bytes src/main.zig | 24 ++++++++++++++++++++++++ vendor/microzig | 1 + zpm.zig | 8 ++++++++ 11 files changed, 75 insertions(+) create mode 100644 .gitattributes create mode 100644 .github/FUNDING.yml create mode 100644 .gitignore create mode 100644 .gitmodules create mode 100644 README.md create mode 100644 build.zig create mode 100644 docs/esp32-c3-32s-pinout.png create mode 100644 docs/esp32-c3-32s-pinout.xcf create mode 100644 src/main.zig create mode 160000 vendor/microzig create mode 100644 zpm.zig diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 000000000..0cb064aeb --- /dev/null +++ b/.gitattributes @@ -0,0 +1 @@ +*.zig text=auto eol=lf diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml new file mode 100644 index 000000000..85b5393bb --- /dev/null +++ b/.github/FUNDING.yml @@ -0,0 +1 @@ +github: MasterQ32 diff --git a/.gitignore b/.gitignore new file mode 100644 index 000000000..e73c965f8 --- /dev/null +++ b/.gitignore @@ -0,0 +1,2 @@ +zig-cache/ +zig-out/ diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 000000000..54620ef7a --- /dev/null +++ b/.gitmodules @@ -0,0 +1,3 @@ +[submodule "vendor/microzig"] + path = vendor/microzig + url = https://github.com/ZigEmbeddedGroup/microzig diff --git a/README.md b/README.md new file mode 100644 index 000000000..2cd0dfa3e --- /dev/null +++ b/README.md @@ -0,0 +1 @@ +# esp32-c3-bringup diff --git a/build.zig b/build.zig new file mode 100644 index 000000000..035b12a74 --- /dev/null +++ b/build.zig @@ -0,0 +1,34 @@ +const std = @import("std"); + +pub fn build(b: *std.build.Builder) void { + // Standard target options allows the person running `zig build` to choose + // what target to build for. Here we do not override the defaults, which + // means any target is allowed, and the default is native. Other options + // for restricting supported target set are available. + const target = b.standardTargetOptions(.{}); + + // Standard release options allow the person running `zig build` to select + // between Debug, ReleaseSafe, ReleaseFast, and ReleaseSmall. + const mode = b.standardReleaseOptions(); + + const exe = b.addExecutable("esp32-c3-bringup", "src/main.zig"); + exe.setTarget(target); + exe.setBuildMode(mode); + exe.install(); + + const run_cmd = exe.run(); + run_cmd.step.dependOn(b.getInstallStep()); + if (b.args) |args| { + run_cmd.addArgs(args); + } + + const run_step = b.step("run", "Run the app"); + run_step.dependOn(&run_cmd.step); + + const exe_tests = b.addTest("src/main.zig"); + exe_tests.setTarget(target); + exe_tests.setBuildMode(mode); + + const test_step = b.step("test", "Run unit tests"); + test_step.dependOn(&exe_tests.step); +} diff --git a/docs/esp32-c3-32s-pinout.png b/docs/esp32-c3-32s-pinout.png new file mode 100644 index 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zmM1+N#Sj2JMSPH_&UKFNf92sH-}pD~GKa1Gjt_Ven#vXVo&){;hxYw($ELM6p6x0%
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DjLf+c

literal 0
HcmV?d00001

diff --git a/src/main.zig b/src/main.zig
new file mode 100644
index 000000000..c8a3f67dd
--- /dev/null
+++ b/src/main.zig
@@ -0,0 +1,24 @@
+const std = @import("std");
+
+pub fn main() !void {
+    // Prints to stderr (it's a shortcut based on `std.io.getStdErr()`)
+    std.debug.print("All your {s} are belong to us.\n", .{"codebase"});
+
+    // stdout is for the actual output of your application, for example if you
+    // are implementing gzip, then only the compressed bytes should be sent to
+    // stdout, not any debugging messages.
+    const stdout_file = std.io.getStdOut().writer();
+    var bw = std.io.bufferedWriter(stdout_file);
+    const stdout = bw.writer();
+
+    try stdout.print("Run `zig build test` to run the tests.\n", .{});
+
+    try bw.flush(); // don't forget to flush!
+}
+
+test "simple test" {
+    var list = std.ArrayList(i32).init(std.testing.allocator);
+    defer list.deinit(); // try commenting this out and see if zig detects the memory leak!
+    try list.append(42);
+    try std.testing.expectEqual(@as(i32, 42), list.pop());
+}
diff --git a/vendor/microzig b/vendor/microzig
new file mode 160000
index 000000000..15bc1fc06
--- /dev/null
+++ b/vendor/microzig
@@ -0,0 +1 @@
+Subproject commit 15bc1fc06da3b6c622a21fa438e40be247d9dee1
diff --git a/zpm.zig b/zpm.zig
new file mode 100644
index 000000000..1dcd7b385
--- /dev/null
+++ b/zpm.zig
@@ -0,0 +1,8 @@
+//! This file is auto-generated by zpm-update and *should*
+//! not be changed. This file can be checked into your VCS
+//! and is able to work standalone.
+const std = @import("std");
+
+pub const sdks = struct {
+    pub const microzig = @import("vendor/microzig/src/main.zig");
+};

From e1e525a50d562ec1d1687491f7cdd0a109343ccf Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 8 Oct 2022 11:25:01 +0200
Subject: [PATCH 030/286] conflict fixed

---
 .gitignore      |     4 +-
 README.adoc     |     5 +
 esp32c3.svd     | 36932 ++++++++++++++++++++++++++++++++++++++++++++
 src/esp32c3.zig | 37956 ++++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 74895 insertions(+), 2 deletions(-)
 create mode 100644 README.adoc
 create mode 100644 esp32c3.svd
 create mode 100644 src/esp32c3.zig

diff --git a/.gitignore b/.gitignore
index e73c965f8..c26d4af28 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,2 +1,2 @@
-zig-cache/
-zig-out/
+zig-out
+zig-cache
diff --git a/README.adoc b/README.adoc
new file mode 100644
index 000000000..65801a9ae
--- /dev/null
+++ b/README.adoc
@@ -0,0 +1,5 @@
+= ESP MicroZig Package
+
+[WIP]
+
+SVD is copied from https://github.com/esp-rs/esp-pacs
diff --git a/esp32c3.svd b/esp32c3.svd
new file mode 100644
index 000000000..ab064fa93
--- /dev/null
+++ b/esp32c3.svd
@@ -0,0 +1,36932 @@
+
+
+  ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.
+  ESPRESSIF
+  ESP32-C3
+  ESP32-C3
+  8
+  32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
+  
+    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+
+  
+    RV32IMC
+    r0p0
+    little
+    false
+    false
+    4
+    false
+  
+  32
+  32
+  0x00000000
+  0xFFFFFFFF
+  
+    
+      AES
+      AES (Advanced Encryption Standard) Accelerator
+      AES
+      0x6003A000
+      
+        0x0
+        0xBC
+        registers
+      
+      
+        AES
+        48
+      
+      
+        
+          KEY_0
+          Key material key_0 configure register
+          0x0
+          0x20
+          
+            
+              KEY_0
+              This bits stores key_0 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_1
+          Key material key_1 configure register
+          0x4
+          0x20
+          
+            
+              KEY_1
+              This bits stores key_1 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_2
+          Key material key_2 configure register
+          0x8
+          0x20
+          
+            
+              KEY_2
+              This bits stores key_2 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_3
+          Key material key_3 configure register
+          0xC
+          0x20
+          
+            
+              KEY_3
+              This bits stores key_3 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_4
+          Key material key_4 configure register
+          0x10
+          0x20
+          
+            
+              KEY_4
+              This bits stores key_4 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_5
+          Key material key_5 configure register
+          0x14
+          0x20
+          
+            
+              KEY_5
+              This bits stores key_5 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_6
+          Key material key_6 configure register
+          0x18
+          0x20
+          
+            
+              KEY_6
+              This bits stores key_6 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          KEY_7
+          Key material key_7 configure register
+          0x1C
+          0x20
+          
+            
+              KEY_7
+              This bits stores key_7 that is a part of key material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_IN_0
+          source text material text_in_0 configure register
+          0x20
+          0x20
+          
+            
+              TEXT_IN_0
+              This bits stores text_in_0 that is a part of source text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_IN_1
+          source text material text_in_1 configure register
+          0x24
+          0x20
+          
+            
+              TEXT_IN_1
+              This bits stores text_in_1 that is a part of source text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_IN_2
+          source text material text_in_2 configure register
+          0x28
+          0x20
+          
+            
+              TEXT_IN_2
+              This bits stores text_in_2 that is a part of source text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_IN_3
+          source text material text_in_3 configure register
+          0x2C
+          0x20
+          
+            
+              TEXT_IN_3
+              This bits stores text_in_3 that is a part of source text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_OUT_0
+          result text material text_out_0 configure register
+          0x30
+          0x20
+          
+            
+              TEXT_OUT_0
+              This bits stores text_out_0 that is a part of result text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_OUT_1
+          result text material text_out_1 configure register
+          0x34
+          0x20
+          
+            
+              TEXT_OUT_1
+              This bits stores text_out_1 that is a part of result text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_OUT_2
+          result text material text_out_2 configure register
+          0x38
+          0x20
+          
+            
+              TEXT_OUT_2
+              This bits stores text_out_2 that is a part of result text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TEXT_OUT_3
+          result text material text_out_3 configure register
+          0x3C
+          0x20
+          
+            
+              TEXT_OUT_3
+              This bits stores text_out_3 that is a part of result text material.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          MODE
+          AES Mode register
+          0x40
+          0x20
+          
+            
+              MODE
+              This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          ENDIAN
+          AES Endian configure register
+          0x44
+          0x20
+          
+            
+              ENDIAN
+              endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out endian or out_stream endian
+              0
+              6
+              read-write
+            
+          
+        
+        
+          TRIGGER
+          AES trigger register
+          0x48
+          0x20
+          
+            
+              TRIGGER
+              Set this bit to start AES calculation.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          STATE
+          AES state register
+          0x4C
+          0x20
+          
+            
+              STATE
+              Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.
+              0
+              2
+              read-only
+            
+          
+        
+        
+          16
+          0x1
+          IV_MEM[%s]
+          The memory that stores initialization vector
+          0x50
+          0x8
+        
+        
+          16
+          0x1
+          H_MEM[%s]
+          The memory that stores GCM hash subkey
+          0x60
+          0x8
+        
+        
+          16
+          0x1
+          J0_MEM[%s]
+          The memory that stores J0
+          0x70
+          0x8
+        
+        
+          16
+          0x1
+          T0_MEM[%s]
+          The memory that stores T0
+          0x80
+          0x8
+        
+        
+          DMA_ENABLE
+          DMA-AES working mode register
+          0x90
+          0x20
+          
+            
+              DMA_ENABLE
+              1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          BLOCK_MODE
+          AES cipher block mode register
+          0x94
+          0x20
+          
+            
+              BLOCK_MODE
+              Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          BLOCK_NUM
+          AES block number register
+          0x98
+          0x20
+          
+            
+              BLOCK_NUM
+              Those bits stores the number of Plaintext/ciphertext block.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          INC_SEL
+          Standard incrementing function configure register
+          0x9C
+          0x20
+          
+            
+              INC_SEL
+              This bit decides the standard incrementing function. 0: INC32. 1: INC128.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          AAD_BLOCK_NUM
+          Additional Authential Data block number register
+          0xA0
+          0x20
+          
+            
+              AAD_BLOCK_NUM
+              Those bits stores the number of AAD block.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REMAINDER_BIT_NUM
+          AES remainder bit number register
+          0xA4
+          0x20
+          
+            
+              REMAINDER_BIT_NUM
+              Those bits stores the number of remainder bit.
+              0
+              7
+              read-write
+            
+          
+        
+        
+          CONTINUE
+          AES continue register
+          0xA8
+          0x20
+          
+            
+              CONTINUE
+              Set this bit to continue GCM operation.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          INT_CLEAR
+          AES Interrupt clear register
+          0xAC
+          0x20
+          
+            
+              INT_CLEAR
+              Set this bit to clear the AES interrupt.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          INT_ENA
+          AES Interrupt enable register
+          0xB0
+          0x20
+          
+            
+              INT_ENA
+              Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          AES version control register
+          0xB4
+          0x20
+          0x20191210
+          
+            
+              DATE
+              This bits stores the version information of AES.
+              0
+              30
+              read-write
+            
+          
+        
+        
+          DMA_EXIT
+          AES-DMA exit config
+          0xB8
+          0x20
+          
+            
+              DMA_EXIT
+              Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.
+              0
+              1
+              write-only
+            
+          
+        
+      
+    
+    
+      APB_CTRL
+      Advanced Peripheral Bus Controller
+      APB_CTRL
+      0x60026000
+      
+        0x0
+        0xA0
+        registers
+      
+      
+        
+          SYSCLK_CONF
+          APB_CTRL_SYSCLK_CONF_REG
+          0x0
+          0x20
+          0x00000001
+          
+            
+              PRE_DIV_CNT
+              reg_pre_div_cnt
+              0
+              10
+              read-write
+            
+            
+              CLK_320M_EN
+              reg_clk_320m_en
+              10
+              1
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en
+              11
+              1
+              read-write
+            
+            
+              RST_TICK_CNT
+              reg_rst_tick_cnt
+              12
+              1
+              read-write
+            
+          
+        
+        
+          TICK_CONF
+          APB_CTRL_TICK_CONF_REG
+          0x4
+          0x20
+          0x00010727
+          
+            
+              XTAL_TICK_NUM
+              reg_xtal_tick_num
+              0
+              8
+              read-write
+            
+            
+              CK8M_TICK_NUM
+              reg_ck8m_tick_num
+              8
+              8
+              read-write
+            
+            
+              TICK_ENABLE
+              reg_tick_enable
+              16
+              1
+              read-write
+            
+          
+        
+        
+          CLK_OUT_EN
+          APB_CTRL_CLK_OUT_EN_REG
+          0x8
+          0x20
+          0x000007FF
+          
+            
+              CLK20_OEN
+              reg_clk20_oen
+              0
+              1
+              read-write
+            
+            
+              CLK22_OEN
+              reg_clk22_oen
+              1
+              1
+              read-write
+            
+            
+              CLK44_OEN
+              reg_clk44_oen
+              2
+              1
+              read-write
+            
+            
+              CLK_BB_OEN
+              reg_clk_bb_oen
+              3
+              1
+              read-write
+            
+            
+              CLK80_OEN
+              reg_clk80_oen
+              4
+              1
+              read-write
+            
+            
+              CLK160_OEN
+              reg_clk160_oen
+              5
+              1
+              read-write
+            
+            
+              CLK_320M_OEN
+              reg_clk_320m_oen
+              6
+              1
+              read-write
+            
+            
+              CLK_ADC_INF_OEN
+              reg_clk_adc_inf_oen
+              7
+              1
+              read-write
+            
+            
+              CLK_DAC_CPU_OEN
+              reg_clk_dac_cpu_oen
+              8
+              1
+              read-write
+            
+            
+              CLK40X_BB_OEN
+              reg_clk40x_bb_oen
+              9
+              1
+              read-write
+            
+            
+              CLK_XTAL_OEN
+              reg_clk_xtal_oen
+              10
+              1
+              read-write
+            
+          
+        
+        
+          WIFI_BB_CFG
+          APB_CTRL_WIFI_BB_CFG_REG
+          0xC
+          0x20
+          
+            
+              WIFI_BB_CFG
+              reg_wifi_bb_cfg
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WIFI_BB_CFG_2
+          APB_CTRL_WIFI_BB_CFG_2_REG
+          0x10
+          0x20
+          
+            
+              WIFI_BB_CFG_2
+              reg_wifi_bb_cfg_2
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WIFI_CLK_EN
+          APB_CTRL_WIFI_CLK_EN_REG
+          0x14
+          0x20
+          0xFFFCE030
+          
+            
+              WIFI_CLK_EN
+              reg_wifi_clk_en
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WIFI_RST_EN
+          APB_CTRL_WIFI_RST_EN_REG
+          0x18
+          0x20
+          
+            
+              WIFI_RST
+              reg_wifi_rst
+              0
+              32
+              read-write
+            
+          
+        
+        
+          HOST_INF_SEL
+          APB_CTRL_HOST_INF_SEL_REG
+          0x1C
+          0x20
+          
+            
+              PERI_IO_SWAP
+              reg_peri_io_swap
+              0
+              8
+              read-write
+            
+          
+        
+        
+          EXT_MEM_PMS_LOCK
+          APB_CTRL_EXT_MEM_PMS_LOCK_REG
+          0x20
+          0x20
+          
+            
+              EXT_MEM_PMS_LOCK
+              reg_ext_mem_pms_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          FLASH_ACE0_ATTR
+          APB_CTRL_FLASH_ACE0_ATTR_REG
+          0x28
+          0x20
+          0x00000003
+          
+            
+              FLASH_ACE0_ATTR
+              reg_flash_ace0_attr
+              0
+              2
+              read-write
+            
+          
+        
+        
+          FLASH_ACE1_ATTR
+          APB_CTRL_FLASH_ACE1_ATTR_REG
+          0x2C
+          0x20
+          0x00000003
+          
+            
+              FLASH_ACE1_ATTR
+              reg_flash_ace1_attr
+              0
+              2
+              read-write
+            
+          
+        
+        
+          FLASH_ACE2_ATTR
+          APB_CTRL_FLASH_ACE2_ATTR_REG
+          0x30
+          0x20
+          0x00000003
+          
+            
+              FLASH_ACE2_ATTR
+              reg_flash_ace2_attr
+              0
+              2
+              read-write
+            
+          
+        
+        
+          FLASH_ACE3_ATTR
+          APB_CTRL_FLASH_ACE3_ATTR_REG
+          0x34
+          0x20
+          0x00000003
+          
+            
+              FLASH_ACE3_ATTR
+              reg_flash_ace3_attr
+              0
+              2
+              read-write
+            
+          
+        
+        
+          FLASH_ACE0_ADDR
+          APB_CTRL_FLASH_ACE0_ADDR_REG
+          0x38
+          0x20
+          
+            
+              S
+              reg_flash_ace0_addr_s
+              0
+              32
+              read-write
+            
+          
+        
+        
+          FLASH_ACE1_ADDR
+          APB_CTRL_FLASH_ACE1_ADDR_REG
+          0x3C
+          0x20
+          0x00400000
+          
+            
+              S
+              reg_flash_ace1_addr_s
+              0
+              32
+              read-write
+            
+          
+        
+        
+          FLASH_ACE2_ADDR
+          APB_CTRL_FLASH_ACE2_ADDR_REG
+          0x40
+          0x20
+          0x00800000
+          
+            
+              S
+              reg_flash_ace2_addr_s
+              0
+              32
+              read-write
+            
+          
+        
+        
+          FLASH_ACE3_ADDR
+          APB_CTRL_FLASH_ACE3_ADDR_REG
+          0x44
+          0x20
+          0x00C00000
+          
+            
+              S
+              reg_flash_ace3_addr_s
+              0
+              32
+              read-write
+            
+          
+        
+        
+          FLASH_ACE0_SIZE
+          APB_CTRL_FLASH_ACE0_SIZE_REG
+          0x48
+          0x20
+          0x00000400
+          
+            
+              FLASH_ACE0_SIZE
+              reg_flash_ace0_size
+              0
+              13
+              read-write
+            
+          
+        
+        
+          FLASH_ACE1_SIZE
+          APB_CTRL_FLASH_ACE1_SIZE_REG
+          0x4C
+          0x20
+          0x00000400
+          
+            
+              FLASH_ACE1_SIZE
+              reg_flash_ace1_size
+              0
+              13
+              read-write
+            
+          
+        
+        
+          FLASH_ACE2_SIZE
+          APB_CTRL_FLASH_ACE2_SIZE_REG
+          0x50
+          0x20
+          0x00000400
+          
+            
+              FLASH_ACE2_SIZE
+              reg_flash_ace2_size
+              0
+              13
+              read-write
+            
+          
+        
+        
+          FLASH_ACE3_SIZE
+          APB_CTRL_FLASH_ACE3_SIZE_REG
+          0x54
+          0x20
+          0x00000400
+          
+            
+              FLASH_ACE3_SIZE
+              reg_flash_ace3_size
+              0
+              13
+              read-write
+            
+          
+        
+        
+          SPI_MEM_PMS_CTRL
+          APB_CTRL_SPI_MEM_PMS_CTRL_REG
+          0x88
+          0x20
+          
+            
+              SPI_MEM_REJECT_INT
+              reg_spi_mem_reject_int
+              0
+              1
+              read-only
+            
+            
+              SPI_MEM_REJECT_CLR
+              reg_spi_mem_reject_clr
+              1
+              1
+              write-only
+            
+            
+              SPI_MEM_REJECT_CDE
+              reg_spi_mem_reject_cde
+              2
+              5
+              read-only
+            
+          
+        
+        
+          SPI_MEM_REJECT_ADDR
+          APB_CTRL_SPI_MEM_REJECT_ADDR_REG
+          0x8C
+          0x20
+          
+            
+              SPI_MEM_REJECT_ADDR
+              reg_spi_mem_reject_addr
+              0
+              32
+              read-only
+            
+          
+        
+        
+          SDIO_CTRL
+          APB_CTRL_SDIO_CTRL_REG
+          0x90
+          0x20
+          
+            
+              SDIO_WIN_ACCESS_EN
+              reg_sdio_win_access_en
+              0
+              1
+              read-write
+            
+          
+        
+        
+          REDCY_SIG0
+          APB_CTRL_REDCY_SIG0_REG
+          0x94
+          0x20
+          
+            
+              REDCY_SIG0
+              reg_redcy_sig0
+              0
+              31
+              read-write
+            
+            
+              REDCY_ANDOR
+              reg_redcy_andor
+              31
+              1
+              read-only
+            
+          
+        
+        
+          REDCY_SIG1
+          APB_CTRL_REDCY_SIG1_REG
+          0x98
+          0x20
+          
+            
+              REDCY_SIG1
+              reg_redcy_sig1
+              0
+              31
+              read-write
+            
+            
+              REDCY_NANDOR
+              reg_redcy_nandor
+              31
+              1
+              read-only
+            
+          
+        
+        
+          FRONT_END_MEM_PD
+          APB_CTRL_FRONT_END_MEM_PD_REG
+          0x9C
+          0x20
+          0x00000015
+          
+            
+              AGC_MEM_FORCE_PU
+              reg_agc_mem_force_pu
+              0
+              1
+              read-write
+            
+            
+              AGC_MEM_FORCE_PD
+              reg_agc_mem_force_pd
+              1
+              1
+              read-write
+            
+            
+              PBUS_MEM_FORCE_PU
+              reg_pbus_mem_force_pu
+              2
+              1
+              read-write
+            
+            
+              PBUS_MEM_FORCE_PD
+              reg_pbus_mem_force_pd
+              3
+              1
+              read-write
+            
+            
+              DC_MEM_FORCE_PU
+              reg_dc_mem_force_pu
+              4
+              1
+              read-write
+            
+            
+              DC_MEM_FORCE_PD
+              reg_dc_mem_force_pd
+              5
+              1
+              read-write
+            
+          
+        
+        
+          RETENTION_CTRL
+          APB_CTRL_RETENTION_CTRL_REG
+          0xA0
+          0x20
+          
+            
+              RETENTION_LINK_ADDR
+              reg_retention_link_addr
+              0
+              27
+              read-write
+            
+            
+              NOBYPASS_CPU_ISO_RST
+              reg_nobypass_cpu_iso_rst
+              27
+              1
+              read-write
+            
+          
+        
+        
+          CLKGATE_FORCE_ON
+          APB_CTRL_CLKGATE_FORCE_ON_REG
+          0xA4
+          0x20
+          0x0000003F
+          
+            
+              ROM_CLKGATE_FORCE_ON
+              reg_rom_clkgate_force_on
+              0
+              2
+              read-write
+            
+            
+              SRAM_CLKGATE_FORCE_ON
+              reg_sram_clkgate_force_on
+              2
+              4
+              read-write
+            
+          
+        
+        
+          MEM_POWER_DOWN
+          APB_CTRL_MEM_POWER_DOWN_REG
+          0xA8
+          0x20
+          
+            
+              ROM_POWER_DOWN
+              reg_rom_power_down
+              0
+              2
+              read-write
+            
+            
+              SRAM_POWER_DOWN
+              reg_sram_power_down
+              2
+              4
+              read-write
+            
+          
+        
+        
+          MEM_POWER_UP
+          APB_CTRL_MEM_POWER_UP_REG
+          0xAC
+          0x20
+          0x0000003F
+          
+            
+              ROM_POWER_UP
+              reg_rom_power_up
+              0
+              2
+              read-write
+            
+            
+              SRAM_POWER_UP
+              reg_sram_power_up
+              2
+              4
+              read-write
+            
+          
+        
+        
+          RND_DATA
+          APB_CTRL_RND_DATA_REG
+          0xB0
+          0x20
+          
+            
+              RND_DATA
+              reg_rnd_data
+              0
+              32
+              read-only
+            
+          
+        
+        
+          PERI_BACKUP_CONFIG
+          APB_CTRL_PERI_BACKUP_CONFIG_REG
+          0xB4
+          0x20
+          0x00006480
+          
+            
+              PERI_BACKUP_FLOW_ERR
+              reg_peri_backup_flow_err
+              1
+              2
+              read-only
+            
+            
+              PERI_BACKUP_BURST_LIMIT
+              reg_peri_backup_burst_limit
+              4
+              5
+              read-write
+            
+            
+              PERI_BACKUP_TOUT_THRES
+              reg_peri_backup_tout_thres
+              9
+              10
+              read-write
+            
+            
+              PERI_BACKUP_SIZE
+              reg_peri_backup_size
+              19
+              10
+              read-write
+            
+            
+              PERI_BACKUP_START
+              reg_peri_backup_start
+              29
+              1
+              write-only
+            
+            
+              PERI_BACKUP_TO_MEM
+              reg_peri_backup_to_mem
+              30
+              1
+              read-write
+            
+            
+              PERI_BACKUP_ENA
+              reg_peri_backup_ena
+              31
+              1
+              read-write
+            
+          
+        
+        
+          PERI_BACKUP_APB_ADDR
+          APB_CTRL_PERI_BACKUP_APB_ADDR_REG
+          0xB8
+          0x20
+          
+            
+              BACKUP_APB_START_ADDR
+              reg_backup_apb_start_addr
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PERI_BACKUP_MEM_ADDR
+          APB_CTRL_PERI_BACKUP_MEM_ADDR_REG
+          0xBC
+          0x20
+          
+            
+              BACKUP_MEM_START_ADDR
+              reg_backup_mem_start_addr
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PERI_BACKUP_INT_RAW
+          APB_CTRL_PERI_BACKUP_INT_RAW_REG
+          0xC0
+          0x20
+          
+            
+              PERI_BACKUP_DONE_INT_RAW
+              reg_peri_backup_done_int_raw
+              0
+              1
+              read-only
+            
+            
+              PERI_BACKUP_ERR_INT_RAW
+              reg_peri_backup_err_int_raw
+              1
+              1
+              read-only
+            
+          
+        
+        
+          PERI_BACKUP_INT_ST
+          APB_CTRL_PERI_BACKUP_INT_ST_REG
+          0xC4
+          0x20
+          
+            
+              PERI_BACKUP_DONE_INT_ST
+              reg_peri_backup_done_int_st
+              0
+              1
+              read-only
+            
+            
+              PERI_BACKUP_ERR_INT_ST
+              reg_peri_backup_err_int_st
+              1
+              1
+              read-only
+            
+          
+        
+        
+          PERI_BACKUP_INT_ENA
+          APB_CTRL_PERI_BACKUP_INT_ENA_REG
+          0xC8
+          0x20
+          
+            
+              PERI_BACKUP_DONE_INT_ENA
+              reg_peri_backup_done_int_ena
+              0
+              1
+              read-write
+            
+            
+              PERI_BACKUP_ERR_INT_ENA
+              reg_peri_backup_err_int_ena
+              1
+              1
+              read-write
+            
+          
+        
+        
+          PERI_BACKUP_INT_CLR
+          APB_CTRL_PERI_BACKUP_INT_CLR_REG
+          0xD0
+          0x20
+          
+            
+              PERI_BACKUP_DONE_INT_CLR
+              reg_peri_backup_done_int_clr
+              0
+              1
+              write-only
+            
+            
+              PERI_BACKUP_ERR_INT_CLR
+              reg_peri_backup_err_int_clr
+              1
+              1
+              write-only
+            
+          
+        
+        
+          DATE
+          APB_CTRL_DATE_REG
+          0x3FC
+          0x20
+          0x02007210
+          
+            
+              DATE
+              reg_dateVersion control
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      APB_SARADC
+      Successive Approximation Register Analog to Digital Converter
+      APB_SARADC
+      0x60040000
+      
+        0x0
+        0x68
+        registers
+      
+      
+        APB_ADC
+        43
+      
+      
+        
+          CTRL
+          digital saradc configure register
+          0x0
+          0x20
+          0x40038240
+          
+            
+              SARADC_START_FORCE
+              select software enable saradc sample
+              0
+              1
+              read-write
+            
+            
+              SARADC_START
+              software enable saradc sample
+              1
+              1
+              read-write
+            
+            
+              SARADC_SAR_CLK_GATED
+              SAR clock gated
+              6
+              1
+              read-write
+            
+            
+              SARADC_SAR_CLK_DIV
+              SAR clock divider
+              7
+              8
+              read-write
+            
+            
+              SARADC_SAR_PATT_LEN
+              0 ~ 15 means length 1 ~ 16
+              15
+              3
+              read-write
+            
+            
+              SARADC_SAR_PATT_P_CLEAR
+              clear the pointer of pattern table for DIG ADC1 CTRL
+              23
+              1
+              read-write
+            
+            
+              SARADC_XPD_SAR_FORCE
+              force option to xpd sar blocks
+              27
+              2
+              read-write
+            
+            
+              SARADC_WAIT_ARB_CYCLE
+              wait arbit signal stable after sar_done
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CTRL2
+          digital saradc configure register
+          0x4
+          0x20
+          0x0000A1FE
+          
+            
+              SARADC_MEAS_NUM_LIMIT
+              enable max meas num
+              0
+              1
+              read-write
+            
+            
+              SARADC_MAX_MEAS_NUM
+              max conversion number
+              1
+              8
+              read-write
+            
+            
+              SARADC_SAR1_INV
+              1: data to DIG ADC1 CTRL is inverted, otherwise not
+              9
+              1
+              read-write
+            
+            
+              SARADC_SAR2_INV
+              1: data to DIG ADC2 CTRL is inverted, otherwise not
+              10
+              1
+              read-write
+            
+            
+              SARADC_TIMER_TARGET
+              to set saradc timer target
+              12
+              12
+              read-write
+            
+            
+              SARADC_TIMER_EN
+              to enable saradc timer trigger
+              24
+              1
+              read-write
+            
+          
+        
+        
+          FILTER_CTRL1
+          digital saradc configure register
+          0x8
+          0x20
+          
+            
+              APB_SARADC_FILTER_FACTOR1
+              Factor of saradc filter1
+              26
+              3
+              read-write
+            
+            
+              APB_SARADC_FILTER_FACTOR0
+              Factor of saradc filter0
+              29
+              3
+              read-write
+            
+          
+        
+        
+          FSM_WAIT
+          digital saradc configure register
+          0xC
+          0x20
+          0x00FF0808
+          
+            
+              SARADC_XPD_WAIT
+              saradc_xpd_wait
+              0
+              8
+              read-write
+            
+            
+              SARADC_RSTB_WAIT
+              saradc_rstb_wait
+              8
+              8
+              read-write
+            
+            
+              SARADC_STANDBY_WAIT
+              saradc_standby_wait
+              16
+              8
+              read-write
+            
+          
+        
+        
+          SAR1_STATUS
+          digital saradc configure register
+          0x10
+          0x20
+          
+            
+              SARADC_SAR1_STATUS
+              saradc1 status about data and channel
+              0
+              32
+              read-only
+            
+          
+        
+        
+          SAR2_STATUS
+          digital saradc configure register
+          0x14
+          0x20
+          
+            
+              SARADC_SAR2_STATUS
+              saradc2 status about data and channel
+              0
+              32
+              read-only
+            
+          
+        
+        
+          SAR_PATT_TAB1
+          digital saradc configure register
+          0x18
+          0x20
+          
+            
+              SARADC_SAR_PATT_TAB1
+              item 0 ~ 3 for pattern table 1 (each item one byte)
+              0
+              24
+              read-write
+            
+          
+        
+        
+          SAR_PATT_TAB2
+          digital saradc configure register
+          0x1C
+          0x20
+          
+            
+              SARADC_SAR_PATT_TAB2
+              Item 4 ~ 7 for pattern table 1 (each item one byte)
+              0
+              24
+              read-write
+            
+          
+        
+        
+          ONETIME_SAMPLE
+          digital saradc configure register
+          0x20
+          0x20
+          0x1A000000
+          
+            
+              SARADC_ONETIME_ATTEN
+              configure onetime atten
+              23
+              2
+              read-write
+            
+            
+              SARADC_ONETIME_CHANNEL
+              configure onetime channel
+              25
+              4
+              read-write
+            
+            
+              SARADC_ONETIME_START
+              trigger adc onetime sample
+              29
+              1
+              read-write
+            
+            
+              SARADC2_ONETIME_SAMPLE
+              enable adc2 onetime sample
+              30
+              1
+              read-write
+            
+            
+              SARADC1_ONETIME_SAMPLE
+              enable adc1 onetime sample
+              31
+              1
+              read-write
+            
+          
+        
+        
+          ARB_CTRL
+          digital saradc configure register
+          0x24
+          0x20
+          0x00000900
+          
+            
+              ADC_ARB_APB_FORCE
+              adc2 arbiter force to enableapb controller
+              2
+              1
+              read-write
+            
+            
+              ADC_ARB_RTC_FORCE
+              adc2 arbiter force to enable rtc controller
+              3
+              1
+              read-write
+            
+            
+              ADC_ARB_WIFI_FORCE
+              adc2 arbiter force to enable wifi controller
+              4
+              1
+              read-write
+            
+            
+              ADC_ARB_GRANT_FORCE
+              adc2 arbiter force grant
+              5
+              1
+              read-write
+            
+            
+              ADC_ARB_APB_PRIORITY
+              Set adc2 arbiterapb priority
+              6
+              2
+              read-write
+            
+            
+              ADC_ARB_RTC_PRIORITY
+              Set adc2 arbiter rtc priority
+              8
+              2
+              read-write
+            
+            
+              ADC_ARB_WIFI_PRIORITY
+              Set adc2 arbiter wifi priority
+              10
+              2
+              read-write
+            
+            
+              ADC_ARB_FIX_PRIORITY
+              adc2 arbiter uses fixed priority
+              12
+              1
+              read-write
+            
+          
+        
+        
+          FILTER_CTRL0
+          digital saradc configure register
+          0x28
+          0x20
+          0x03740000
+          
+            
+              APB_SARADC_FILTER_CHANNEL1
+              configure filter1 to adc channel
+              18
+              4
+              read-write
+            
+            
+              APB_SARADC_FILTER_CHANNEL0
+              configure filter0 to adc channel
+              22
+              4
+              read-write
+            
+            
+              APB_SARADC_FILTER_RESET
+              enable apb_adc1_filter
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SAR1DATA_STATUS
+          digital saradc configure register
+          0x2C
+          0x20
+          
+            
+              APB_SARADC1_DATA
+              saradc1 data
+              0
+              17
+              read-only
+            
+          
+        
+        
+          SAR2DATA_STATUS
+          digital saradc configure register
+          0x30
+          0x20
+          
+            
+              APB_SARADC2_DATA
+              saradc2 data
+              0
+              17
+              read-only
+            
+          
+        
+        
+          THRES0_CTRL
+          digital saradc configure register
+          0x34
+          0x20
+          0x0003FFED
+          
+            
+              APB_SARADC_THRES0_CHANNEL
+              configure thres0 to adc channel
+              0
+              4
+              read-write
+            
+            
+              APB_SARADC_THRES0_HIGH
+              saradc thres0 monitor thres
+              5
+              13
+              read-write
+            
+            
+              APB_SARADC_THRES0_LOW
+              saradc thres0 monitor thres
+              18
+              13
+              read-write
+            
+          
+        
+        
+          THRES1_CTRL
+          digital saradc configure register
+          0x38
+          0x20
+          0x0003FFED
+          
+            
+              APB_SARADC_THRES1_CHANNEL
+              configure thres1 to adc channel
+              0
+              4
+              read-write
+            
+            
+              APB_SARADC_THRES1_HIGH
+              saradc thres1 monitor thres
+              5
+              13
+              read-write
+            
+            
+              APB_SARADC_THRES1_LOW
+              saradc thres1 monitor thres
+              18
+              13
+              read-write
+            
+          
+        
+        
+          THRES_CTRL
+          digital saradc configure register
+          0x3C
+          0x20
+          
+            
+              APB_SARADC_THRES_ALL_EN
+              enable thres to all channel
+              27
+              1
+              read-write
+            
+            
+              APB_SARADC_THRES1_EN
+              enable thres1
+              30
+              1
+              read-write
+            
+            
+              APB_SARADC_THRES0_EN
+              enable thres0
+              31
+              1
+              read-write
+            
+          
+        
+        
+          INT_ENA
+          digital saradc int register
+          0x40
+          0x20
+          
+            
+              APB_SARADC_THRES1_LOW_INT_ENA
+              saradc thres1 low  interrupt enable
+              26
+              1
+              read-write
+            
+            
+              APB_SARADC_THRES0_LOW_INT_ENA
+              saradc thres0 low interrupt enable
+              27
+              1
+              read-write
+            
+            
+              APB_SARADC_THRES1_HIGH_INT_ENA
+              saradc thres1 high interrupt enable
+              28
+              1
+              read-write
+            
+            
+              APB_SARADC_THRES0_HIGH_INT_ENA
+              saradc thres0 high interrupt enable
+              29
+              1
+              read-write
+            
+            
+              APB_SARADC2_DONE_INT_ENA
+              saradc2 done interrupt enable
+              30
+              1
+              read-write
+            
+            
+              APB_SARADC1_DONE_INT_ENA
+              saradc1 done interrupt enable
+              31
+              1
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          digital saradc int register
+          0x44
+          0x20
+          
+            
+              APB_SARADC_THRES1_LOW_INT_RAW
+              saradc thres1 low  interrupt raw
+              26
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES0_LOW_INT_RAW
+              saradc thres0 low interrupt raw
+              27
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES1_HIGH_INT_RAW
+              saradc thres1 high interrupt raw
+              28
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES0_HIGH_INT_RAW
+              saradc thres0 high interrupt raw
+              29
+              1
+              read-only
+            
+            
+              APB_SARADC2_DONE_INT_RAW
+              saradc2 done interrupt raw
+              30
+              1
+              read-only
+            
+            
+              APB_SARADC1_DONE_INT_RAW
+              saradc1 done interrupt raw
+              31
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          digital saradc int register
+          0x48
+          0x20
+          
+            
+              APB_SARADC_THRES1_LOW_INT_ST
+              saradc thres1 low  interrupt state
+              26
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES0_LOW_INT_ST
+              saradc thres0 low interrupt state
+              27
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES1_HIGH_INT_ST
+              saradc thres1 high interrupt state
+              28
+              1
+              read-only
+            
+            
+              APB_SARADC_THRES0_HIGH_INT_ST
+              saradc thres0 high interrupt state
+              29
+              1
+              read-only
+            
+            
+              APB_SARADC2_DONE_INT_ST
+              saradc2 done interrupt state
+              30
+              1
+              read-only
+            
+            
+              APB_SARADC1_DONE_INT_ST
+              saradc1 done interrupt state
+              31
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR
+          digital saradc int register
+          0x4C
+          0x20
+          
+            
+              APB_SARADC_THRES1_LOW_INT_CLR
+              saradc thres1 low  interrupt clear
+              26
+              1
+              write-only
+            
+            
+              APB_SARADC_THRES0_LOW_INT_CLR
+              saradc thres0 low interrupt clear
+              27
+              1
+              write-only
+            
+            
+              APB_SARADC_THRES1_HIGH_INT_CLR
+              saradc thres1 high interrupt clear
+              28
+              1
+              write-only
+            
+            
+              APB_SARADC_THRES0_HIGH_INT_CLR
+              saradc thres0 high interrupt clear
+              29
+              1
+              write-only
+            
+            
+              APB_SARADC2_DONE_INT_CLR
+              saradc2 done interrupt clear
+              30
+              1
+              write-only
+            
+            
+              APB_SARADC1_DONE_INT_CLR
+              saradc1 done interrupt clear
+              31
+              1
+              write-only
+            
+          
+        
+        
+          DMA_CONF
+          digital saradc configure register
+          0x50
+          0x20
+          0x000000FF
+          
+            
+              APB_ADC_EOF_NUM
+              the dma_in_suc_eof gen when sample cnt = spi_eof_num
+              0
+              16
+              read-write
+            
+            
+              APB_ADC_RESET_FSM
+              reset_apb_adc_state
+              30
+              1
+              read-write
+            
+            
+              APB_ADC_TRANS
+              enable apb_adc use spi_dma
+              31
+              1
+              read-write
+            
+          
+        
+        
+          CLKM_CONF
+          digital saradc configure register
+          0x54
+          0x20
+          0x00000004
+          
+            
+              CLKM_DIV_NUM
+              Integral I2S clock divider value
+              0
+              8
+              read-write
+            
+            
+              CLKM_DIV_B
+              Fractional clock divider numerator value
+              8
+              6
+              read-write
+            
+            
+              CLKM_DIV_A
+              Fractional clock divider denominator value
+              14
+              6
+              read-write
+            
+            
+              CLK_EN
+              reg clk en
+              20
+              1
+              read-write
+            
+            
+              CLK_SEL
+              Set this bit to enable clk_apll
+              21
+              2
+              read-write
+            
+          
+        
+        
+          APB_TSENS_CTRL
+          digital tsens configure register
+          0x58
+          0x20
+          0x00018000
+          
+            
+              TSENS_OUT
+              temperature sensor data out
+              0
+              8
+              read-only
+            
+            
+              TSENS_IN_INV
+              invert temperature sensor data
+              13
+              1
+              read-write
+            
+            
+              TSENS_CLK_DIV
+              temperature sensor clock divider
+              14
+              8
+              read-write
+            
+            
+              TSENS_PU
+              temperature sensor power up
+              22
+              1
+              read-write
+            
+          
+        
+        
+          TSENS_CTRL2
+          digital tsens configure register
+          0x5C
+          0x20
+          0x00004002
+          
+            
+              TSENS_XPD_WAIT
+              the time that power up tsens need wait
+              0
+              12
+              read-write
+            
+            
+              TSENS_XPD_FORCE
+              force power up tsens
+              12
+              2
+              read-write
+            
+            
+              TSENS_CLK_INV
+              inv tsens clk
+              14
+              1
+              read-write
+            
+            
+              TSENS_CLK_SEL
+              tsens clk select
+              15
+              1
+              read-write
+            
+          
+        
+        
+          CALI
+          digital saradc configure register
+          0x60
+          0x20
+          0x00008000
+          
+            
+              APB_SARADC_CALI_CFG
+              saradc cali factor
+              0
+              17
+              read-write
+            
+          
+        
+        
+          CTRL_DATE
+          version
+          0x3FC
+          0x20
+          0x02007171
+          
+            
+              DATE
+              version
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      ASSIST_DEBUG
+      Debug Assist
+      ASSIST_DEBUG
+      0x600CE000
+      
+        0x0
+        0xA0
+        registers
+      
+      
+        ASSIST_DEBUG
+        54
+      
+      
+        
+          C0RE_0_MONTR_ENA
+          ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG
+          0x0
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_0_RD_ENA
+              reg_core_0_area_dram0_0_rd_ena
+              0
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_0_WR_ENA
+              reg_core_0_area_dram0_0_wr_ena
+              1
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_RD_ENA
+              reg_core_0_area_dram0_1_rd_ena
+              2
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_WR_ENA
+              reg_core_0_area_dram0_1_wr_ena
+              3
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_RD_ENA
+              reg_core_0_area_pif_0_rd_ena
+              4
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_WR_ENA
+              reg_core_0_area_pif_0_wr_ena
+              5
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_RD_ENA
+              reg_core_0_area_pif_1_rd_ena
+              6
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_WR_ENA
+              reg_core_0_area_pif_1_wr_ena
+              7
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MIN_ENA
+              reg_core_0_sp_spill_min_ena
+              8
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MAX_ENA
+              reg_core_0_sp_spill_max_ena
+              9
+              1
+              read-write
+            
+            
+              CORE_0_IRAM0_EXCEPTION_MONITOR_ENA
+              reg_core_0_iram0_exception_monitor_ena
+              10
+              1
+              read-write
+            
+            
+              CORE_0_DRAM0_EXCEPTION_MONITOR_ENA
+              reg_core_0_dram0_exception_monitor_ena
+              11
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_INTR_RAW
+          ASSIST_DEBUG_CORE_0_INTR_RAW_REG
+          0x4
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_0_RD_RAW
+              reg_core_0_area_dram0_0_rd_raw
+              0
+              1
+              read-only
+            
+            
+              CORE_0_AREA_DRAM0_0_WR_RAW
+              reg_core_0_area_dram0_0_wr_raw
+              1
+              1
+              read-only
+            
+            
+              CORE_0_AREA_DRAM0_1_RD_RAW
+              reg_core_0_area_dram0_1_rd_raw
+              2
+              1
+              read-only
+            
+            
+              CORE_0_AREA_DRAM0_1_WR_RAW
+              reg_core_0_area_dram0_1_wr_raw
+              3
+              1
+              read-only
+            
+            
+              CORE_0_AREA_PIF_0_RD_RAW
+              reg_core_0_area_pif_0_rd_raw
+              4
+              1
+              read-only
+            
+            
+              CORE_0_AREA_PIF_0_WR_RAW
+              reg_core_0_area_pif_0_wr_raw
+              5
+              1
+              read-only
+            
+            
+              CORE_0_AREA_PIF_1_RD_RAW
+              reg_core_0_area_pif_1_rd_raw
+              6
+              1
+              read-only
+            
+            
+              CORE_0_AREA_PIF_1_WR_RAW
+              reg_core_0_area_pif_1_wr_raw
+              7
+              1
+              read-only
+            
+            
+              CORE_0_SP_SPILL_MIN_RAW
+              reg_core_0_sp_spill_min_raw
+              8
+              1
+              read-only
+            
+            
+              CORE_0_SP_SPILL_MAX_RAW
+              reg_core_0_sp_spill_max_raw
+              9
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_EXCEPTION_MONITOR_RAW
+              reg_core_0_iram0_exception_monitor_raw
+              10
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_EXCEPTION_MONITOR_RAW
+              reg_core_0_dram0_exception_monitor_raw
+              11
+              1
+              read-only
+            
+          
+        
+        
+          CORE_0_INTR_ENA
+          ASSIST_DEBUG_CORE_0_INTR_ENA_REG
+          0x8
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_0_RD_INTR_ENA
+              reg_core_0_area_dram0_0_rd_intr_ena
+              0
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_0_WR_INTR_ENA
+              reg_core_0_area_dram0_0_wr_intr_ena
+              1
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_RD_INTR_ENA
+              reg_core_0_area_dram0_1_rd_intr_ena
+              2
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_WR_INTR_ENA
+              reg_core_0_area_dram0_1_wr_intr_ena
+              3
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_RD_INTR_ENA
+              reg_core_0_area_pif_0_rd_intr_ena
+              4
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_WR_INTR_ENA
+              reg_core_0_area_pif_0_wr_intr_ena
+              5
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_RD_INTR_ENA
+              reg_core_0_area_pif_1_rd_intr_ena
+              6
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_WR_INTR_ENA
+              reg_core_0_area_pif_1_wr_intr_ena
+              7
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MIN_INTR_ENA
+              reg_core_0_sp_spill_min_intr_ena
+              8
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MAX_INTR_ENA
+              reg_core_0_sp_spill_max_intr_ena
+              9
+              1
+              read-write
+            
+            
+              CORE_0_IRAM0_EXCEPTION_MONITOR_RLS
+              reg_core_0_iram0_exception_monitor_ena
+              10
+              1
+              read-write
+            
+            
+              CORE_0_DRAM0_EXCEPTION_MONITOR_RLS
+              reg_core_0_dram0_exception_monitor_ena
+              11
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_INTR_CLR
+          ASSIST_DEBUG_CORE_0_INTR_CLR_REG
+          0xC
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_0_RD_CLR
+              reg_core_0_area_dram0_0_rd_clr
+              0
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_0_WR_CLR
+              reg_core_0_area_dram0_0_wr_clr
+              1
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_RD_CLR
+              reg_core_0_area_dram0_1_rd_clr
+              2
+              1
+              read-write
+            
+            
+              CORE_0_AREA_DRAM0_1_WR_CLR
+              reg_core_0_area_dram0_1_wr_clr
+              3
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_RD_CLR
+              reg_core_0_area_pif_0_rd_clr
+              4
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_0_WR_CLR
+              reg_core_0_area_pif_0_wr_clr
+              5
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_RD_CLR
+              reg_core_0_area_pif_1_rd_clr
+              6
+              1
+              read-write
+            
+            
+              CORE_0_AREA_PIF_1_WR_CLR
+              reg_core_0_area_pif_1_wr_clr
+              7
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MIN_CLR
+              reg_core_0_sp_spill_min_clr
+              8
+              1
+              read-write
+            
+            
+              CORE_0_SP_SPILL_MAX_CLR
+              reg_core_0_sp_spill_max_clr
+              9
+              1
+              read-write
+            
+            
+              CORE_0_IRAM0_EXCEPTION_MONITOR_CLR
+              reg_core_0_iram0_exception_monitor_clr
+              10
+              1
+              read-write
+            
+            
+              CORE_0_DRAM0_EXCEPTION_MONITOR_CLR
+              reg_core_0_dram0_exception_monitor_clr
+              11
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_DRAM0_0_MIN
+          ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG
+          0x10
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE_0_AREA_DRAM0_0_MIN
+              reg_core_0_area_dram0_0_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_DRAM0_0_MAX
+          ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG
+          0x14
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_0_MAX
+              reg_core_0_area_dram0_0_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_DRAM0_1_MIN
+          ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG
+          0x18
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE_0_AREA_DRAM0_1_MIN
+              reg_core_0_area_dram0_1_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_DRAM0_1_MAX
+          ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG
+          0x1C
+          0x20
+          
+            
+              CORE_0_AREA_DRAM0_1_MAX
+              reg_core_0_area_dram0_1_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_PIF_0_MIN
+          ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG
+          0x20
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE_0_AREA_PIF_0_MIN
+              reg_core_0_area_pif_0_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_PIF_0_MAX
+          ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG
+          0x24
+          0x20
+          
+            
+              CORE_0_AREA_PIF_0_MAX
+              reg_core_0_area_pif_0_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_PIF_1_MIN
+          ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG
+          0x28
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE_0_AREA_PIF_1_MIN
+              reg_core_0_area_pif_1_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_PIF_1_MAX
+          ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG
+          0x2C
+          0x20
+          
+            
+              CORE_0_AREA_PIF_1_MAX
+              reg_core_0_area_pif_1_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_AREA_PC
+          ASSIST_DEBUG_CORE_0_AREA_PC_REG
+          0x30
+          0x20
+          
+            
+              CORE_0_AREA_PC
+              reg_core_0_area_pc
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_AREA_SP
+          ASSIST_DEBUG_CORE_0_AREA_SP_REG
+          0x34
+          0x20
+          
+            
+              CORE_0_AREA_SP
+              reg_core_0_area_sp
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_SP_MIN
+          ASSIST_DEBUG_CORE_0_SP_MIN_REG
+          0x38
+          0x20
+          
+            
+              CORE_0_SP_MIN
+              reg_core_0_sp_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_SP_MAX
+          ASSIST_DEBUG_CORE_0_SP_MAX_REG
+          0x3C
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE_0_SP_MAX
+              reg_core_0_sp_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CORE_0_SP_PC
+          ASSIST_DEBUG_CORE_0_SP_PC_REG
+          0x40
+          0x20
+          
+            
+              CORE_0_SP_PC
+              reg_core_0_sp_pc
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_RCD_EN
+          ASSIST_DEBUG_CORE_0_RCD_EN_REG
+          0x44
+          0x20
+          
+            
+              CORE_0_RCD_RECORDEN
+              reg_core_0_rcd_recorden
+              0
+              1
+              read-write
+            
+            
+              CORE_0_RCD_PDEBUGEN
+              reg_core_0_rcd_pdebugen
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_RCD_PDEBUGPC
+          ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG
+          0x48
+          0x20
+          
+            
+              CORE_0_RCD_PDEBUGPC
+              reg_core_0_rcd_pdebugpc
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_RCD_PDEBUGSP
+          ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+          0x4C
+          0x20
+          
+            
+              CORE_0_RCD_PDEBUGSP
+              reg_core_0_rcd_pdebugsp
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_IRAM0_EXCEPTION_MONITOR_0
+          ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+          0x50
+          0x20
+          
+            
+              CORE_0_IRAM0_RECORDING_ADDR_0
+              reg_core_0_iram0_recording_addr_0
+              0
+              24
+              read-only
+            
+            
+              CORE_0_IRAM0_RECORDING_WR_0
+              reg_core_0_iram0_recording_wr_0
+              24
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_RECORDING_LOADSTORE_0
+              reg_core_0_iram0_recording_loadstore_0
+              25
+              1
+              read-only
+            
+          
+        
+        
+          CORE_0_IRAM0_EXCEPTION_MONITOR_1
+          ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG
+          0x54
+          0x20
+          
+            
+              CORE_0_IRAM0_RECORDING_ADDR_1
+              reg_core_0_iram0_recording_addr_1
+              0
+              24
+              read-only
+            
+            
+              CORE_0_IRAM0_RECORDING_WR_1
+              reg_core_0_iram0_recording_wr_1
+              24
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_RECORDING_LOADSTORE_1
+              reg_core_0_iram0_recording_loadstore_1
+              25
+              1
+              read-only
+            
+          
+        
+        
+          CORE_0_DRAM0_EXCEPTION_MONITOR_0
+          ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG
+          0x58
+          0x20
+          
+            
+              CORE_0_DRAM0_RECORDING_ADDR_0
+              reg_core_0_dram0_recording_addr_0
+              0
+              24
+              read-only
+            
+            
+              CORE_0_DRAM0_RECORDING_WR_0
+              reg_core_0_dram0_recording_wr_0
+              24
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_RECORDING_BYTEEN_0
+              reg_core_0_dram0_recording_byteen_0
+              25
+              4
+              read-only
+            
+          
+        
+        
+          CORE_0_DRAM0_EXCEPTION_MONITOR_1
+          ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+          0x5C
+          0x20
+          
+            
+              CORE_0_DRAM0_RECORDING_PC_0
+              reg_core_0_dram0_recording_pc_0
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_DRAM0_EXCEPTION_MONITOR_2
+          ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+          0x60
+          0x20
+          
+            
+              CORE_0_DRAM0_RECORDING_ADDR_1
+              reg_core_0_dram0_recording_addr_1
+              0
+              24
+              read-only
+            
+            
+              CORE_0_DRAM0_RECORDING_WR_1
+              reg_core_0_dram0_recording_wr_1
+              24
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_RECORDING_BYTEEN_1
+              reg_core_0_dram0_recording_byteen_1
+              25
+              4
+              read-only
+            
+          
+        
+        
+          CORE_0_DRAM0_EXCEPTION_MONITOR_3
+          ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG
+          0x64
+          0x20
+          
+            
+              CORE_0_DRAM0_RECORDING_PC_1
+              reg_core_0_dram0_recording_pc_1
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0
+          ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG
+          0x68
+          0x20
+          
+            
+              CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0
+              reg_core_x_iram0_dram0_limit_cycle_0
+              0
+              20
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1
+          ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG
+          0x6C
+          0x20
+          
+            
+              CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1
+              reg_core_x_iram0_dram0_limit_cycle_1
+              0
+              20
+              read-write
+            
+          
+        
+        
+          LOG_SETTING
+          ASSIST_DEBUG_LOG_SETTING
+          0x70
+          0x20
+          0x00000080
+          
+            
+              LOG_ENA
+              reg_log_ena
+              0
+              3
+              read-write
+            
+            
+              LOG_MODE
+              reg_log_mode
+              3
+              4
+              read-write
+            
+            
+              LOG_MEM_LOOP_ENABLE
+              reg_log_mem_loop_enable
+              7
+              1
+              read-write
+            
+          
+        
+        
+          LOG_DATA_0
+          ASSIST_DEBUG_LOG_DATA_0_REG
+          0x74
+          0x20
+          
+            
+              LOG_DATA_0
+              reg_log_data_0
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOG_DATA_MASK
+          ASSIST_DEBUG_LOG_DATA_MASK_REG
+          0x78
+          0x20
+          
+            
+              LOG_DATA_SIZE
+              reg_log_data_size
+              0
+              16
+              read-write
+            
+          
+        
+        
+          LOG_MIN
+          ASSIST_DEBUG_LOG_MIN_REG
+          0x7C
+          0x20
+          
+            
+              LOG_MIN
+              reg_log_min
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOG_MAX
+          ASSIST_DEBUG_LOG_MAX_REG
+          0x80
+          0x20
+          
+            
+              LOG_MAX
+              reg_log_max
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOG_MEM_START
+          ASSIST_DEBUG_LOG_MEM_START_REG
+          0x84
+          0x20
+          
+            
+              LOG_MEM_START
+              reg_log_mem_start
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOG_MEM_END
+          ASSIST_DEBUG_LOG_MEM_END_REG
+          0x88
+          0x20
+          
+            
+              LOG_MEM_END
+              reg_log_mem_end
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOG_MEM_WRITING_ADDR
+          ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG
+          0x8C
+          0x20
+          
+            
+              LOG_MEM_WRITING_ADDR
+              reg_log_mem_writing_addr
+              0
+              32
+              read-only
+            
+          
+        
+        
+          LOG_MEM_FULL_FLAG
+          ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG
+          0x90
+          0x20
+          
+            
+              LOG_MEM_FULL_FLAG
+              reg_log_mem_full_flag
+              0
+              1
+              read-only
+            
+            
+              CLR_LOG_MEM_FULL_FLAG
+              reg_clr_log_mem_full_flag
+              1
+              1
+              read-write
+            
+          
+        
+        
+          C0RE_0_LASTPC_BEFORE_EXCEPTION
+          ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION
+          0x94
+          0x20
+          
+            
+              CORE_0_LASTPC_BEFORE_EXC
+              reg_core_0_lastpc_before_exc
+              0
+              32
+              read-only
+            
+          
+        
+        
+          C0RE_0_DEBUG_MODE
+          ASSIST_DEBUG_C0RE_0_DEBUG_MODE
+          0x98
+          0x20
+          
+            
+              CORE_0_DEBUG_MODE
+              reg_core_0_debug_mode
+              0
+              1
+              read-only
+            
+            
+              CORE_0_DEBUG_MODULE_ACTIVE
+              reg_core_0_debug_module_active
+              1
+              1
+              read-only
+            
+          
+        
+        
+          DATE
+          ASSIST_DEBUG_DATE_REG
+          0x1FC
+          0x20
+          0x02008010
+          
+            
+              ASSIST_DEBUG_DATE
+              reg_assist_debug_date
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      DMA
+      DMA (Direct Memory Access) Controller
+      DMA
+      0x6003F000
+      
+        0x0
+        0x174
+        registers
+      
+      
+        DMA_CH0
+        44
+      
+      
+        DMA_CH1
+        45
+      
+      
+        DMA_CH2
+        46
+      
+      
+        
+          INT_RAW_CH0
+          DMA_INT_RAW_CH0_REG.
+          0x0
+          0x20
+          
+            
+              IN_DONE_CH0_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH0_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH0_INT_RAW
+              The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH0_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH0_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH0_INT_RAW
+              The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH0_INT_RAW
+              The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH0_INT_RAW
+              The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH0_INT_RAW
+              The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH0_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH0_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH0_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH0_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST_CH0
+          DMA_INT_ST_CH0_REG.
+          0x4
+          0x20
+          
+            
+              IN_DONE_CH0_INT_ST
+              The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH0_INT_ST
+              The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH0_INT_ST
+              The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH0_INT_ST
+              The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH0_INT_ST
+              The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH0_INT_ST
+              The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH0_INT_ST
+              The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH0_INT_ST
+              The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH0_INT_ST
+              The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH0_INT_ST
+              The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH0_INT_ST
+              The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH0_INT_ST
+              The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH0_INT_ST
+              The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA_CH0
+          DMA_INT_ENA_CH0_REG.
+          0x8
+          0x20
+          
+            
+              IN_DONE_CH0_INT_ENA
+              The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              IN_SUC_EOF_CH0_INT_ENA
+              The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              IN_ERR_EOF_CH0_INT_ENA
+              The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-write
+            
+            
+              OUT_DONE_CH0_INT_ENA
+              The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-write
+            
+            
+              OUT_EOF_CH0_INT_ENA
+              The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-write
+            
+            
+              IN_DSCR_ERR_CH0_INT_ENA
+              The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-write
+            
+            
+              OUT_DSCR_ERR_CH0_INT_ENA
+              The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-write
+            
+            
+              IN_DSCR_EMPTY_CH0_INT_ENA
+              The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-write
+            
+            
+              OUT_TOTAL_EOF_CH0_INT_ENA
+              The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-write
+            
+            
+              INFIFO_OVF_CH0_INT_ENA
+              The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-write
+            
+            
+              INFIFO_UDF_CH0_INT_ENA
+              The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-write
+            
+            
+              OUTFIFO_OVF_CH0_INT_ENA
+              The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-write
+            
+            
+              OUTFIFO_UDF_CH0_INT_ENA
+              The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR_CH0
+          DMA_INT_CLR_CH0_REG.
+          0xC
+          0x20
+          
+            
+              IN_DONE_CH0_INT_CLR
+              Set this bit to clear the IN_DONE_CH_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              IN_SUC_EOF_CH0_INT_CLR
+              Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              IN_ERR_EOF_CH0_INT_CLR
+              Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              write-only
+            
+            
+              OUT_DONE_CH0_INT_CLR
+              Set this bit to clear the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              write-only
+            
+            
+              OUT_EOF_CH0_INT_CLR
+              Set this bit to clear the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              write-only
+            
+            
+              IN_DSCR_ERR_CH0_INT_CLR
+              Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              write-only
+            
+            
+              OUT_DSCR_ERR_CH0_INT_CLR
+              Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              write-only
+            
+            
+              IN_DSCR_EMPTY_CH0_INT_CLR
+              Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              write-only
+            
+            
+              OUT_TOTAL_EOF_CH0_INT_CLR
+              Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              write-only
+            
+            
+              INFIFO_OVF_CH0_INT_CLR
+              Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              write-only
+            
+            
+              INFIFO_UDF_CH0_INT_CLR
+              Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              write-only
+            
+            
+              OUTFIFO_OVF_CH0_INT_CLR
+              Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              write-only
+            
+            
+              OUTFIFO_UDF_CH0_INT_CLR
+              Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              write-only
+            
+          
+        
+        
+          INT_RAW_CH1
+          DMA_INT_RAW_CH1_REG.
+          0x10
+          0x20
+          
+            
+              IN_DONE_CH1_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH1_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH1_INT_RAW
+              The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH1_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH1_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH1_INT_RAW
+              The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH1_INT_RAW
+              The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH1_INT_RAW
+              The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH1_INT_RAW
+              The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH1_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH1_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH1_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH1_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST_CH1
+          DMA_INT_ST_CH1_REG.
+          0x14
+          0x20
+          
+            
+              IN_DONE_CH1_INT_ST
+              The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH1_INT_ST
+              The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH1_INT_ST
+              The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH1_INT_ST
+              The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH1_INT_ST
+              The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH1_INT_ST
+              The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH1_INT_ST
+              The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH1_INT_ST
+              The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH1_INT_ST
+              The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH1_INT_ST
+              The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH1_INT_ST
+              The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH1_INT_ST
+              The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH1_INT_ST
+              The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA_CH1
+          DMA_INT_ENA_CH1_REG.
+          0x18
+          0x20
+          
+            
+              IN_DONE_CH1_INT_ENA
+              The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              IN_SUC_EOF_CH1_INT_ENA
+              The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              IN_ERR_EOF_CH1_INT_ENA
+              The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-write
+            
+            
+              OUT_DONE_CH1_INT_ENA
+              The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-write
+            
+            
+              OUT_EOF_CH1_INT_ENA
+              The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-write
+            
+            
+              IN_DSCR_ERR_CH1_INT_ENA
+              The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-write
+            
+            
+              OUT_DSCR_ERR_CH1_INT_ENA
+              The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-write
+            
+            
+              IN_DSCR_EMPTY_CH1_INT_ENA
+              The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-write
+            
+            
+              OUT_TOTAL_EOF_CH1_INT_ENA
+              The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-write
+            
+            
+              INFIFO_OVF_CH1_INT_ENA
+              The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-write
+            
+            
+              INFIFO_UDF_CH1_INT_ENA
+              The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-write
+            
+            
+              OUTFIFO_OVF_CH1_INT_ENA
+              The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-write
+            
+            
+              OUTFIFO_UDF_CH1_INT_ENA
+              The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR_CH1
+          DMA_INT_CLR_CH1_REG.
+          0x1C
+          0x20
+          
+            
+              IN_DONE_CH1_INT_CLR
+              Set this bit to clear the IN_DONE_CH_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              IN_SUC_EOF_CH1_INT_CLR
+              Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              IN_ERR_EOF_CH1_INT_CLR
+              Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              write-only
+            
+            
+              OUT_DONE_CH1_INT_CLR
+              Set this bit to clear the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              write-only
+            
+            
+              OUT_EOF_CH1_INT_CLR
+              Set this bit to clear the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              write-only
+            
+            
+              IN_DSCR_ERR_CH1_INT_CLR
+              Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              write-only
+            
+            
+              OUT_DSCR_ERR_CH1_INT_CLR
+              Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              write-only
+            
+            
+              IN_DSCR_EMPTY_CH1_INT_CLR
+              Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              write-only
+            
+            
+              OUT_TOTAL_EOF_CH1_INT_CLR
+              Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              write-only
+            
+            
+              INFIFO_OVF_CH1_INT_CLR
+              Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              write-only
+            
+            
+              INFIFO_UDF_CH1_INT_CLR
+              Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              write-only
+            
+            
+              OUTFIFO_OVF_CH1_INT_CLR
+              Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              write-only
+            
+            
+              OUTFIFO_UDF_CH1_INT_CLR
+              Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              write-only
+            
+          
+        
+        
+          INT_RAW_CH2
+          DMA_INT_RAW_CH2_REG.
+          0x20
+          0x20
+          
+            
+              IN_DONE_CH2_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH2_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH2_INT_RAW
+              The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH2_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH2_INT_RAW
+              The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH2_INT_RAW
+              The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH2_INT_RAW
+              The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH2_INT_RAW
+              The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH2_INT_RAW
+              The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH2_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH2_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH2_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH2_INT_RAW
+              This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST_CH2
+          DMA_INT_ST_CH2_REG.
+          0x24
+          0x20
+          
+            
+              IN_DONE_CH2_INT_ST
+              The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              IN_SUC_EOF_CH2_INT_ST
+              The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              IN_ERR_EOF_CH2_INT_ST
+              The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-only
+            
+            
+              OUT_DONE_CH2_INT_ST
+              The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-only
+            
+            
+              OUT_EOF_CH2_INT_ST
+              The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-only
+            
+            
+              IN_DSCR_ERR_CH2_INT_ST
+              The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-only
+            
+            
+              OUT_DSCR_ERR_CH2_INT_ST
+              The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-only
+            
+            
+              IN_DSCR_EMPTY_CH2_INT_ST
+              The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-only
+            
+            
+              OUT_TOTAL_EOF_CH2_INT_ST
+              The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-only
+            
+            
+              INFIFO_OVF_CH2_INT_ST
+              The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-only
+            
+            
+              INFIFO_UDF_CH2_INT_ST
+              The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-only
+            
+            
+              OUTFIFO_OVF_CH2_INT_ST
+              The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-only
+            
+            
+              OUTFIFO_UDF_CH2_INT_ST
+              The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA_CH2
+          DMA_INT_ENA_CH2_REG.
+          0x28
+          0x20
+          
+            
+              IN_DONE_CH2_INT_ENA
+              The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              IN_SUC_EOF_CH2_INT_ENA
+              The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              IN_ERR_EOF_CH2_INT_ENA
+              The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              read-write
+            
+            
+              OUT_DONE_CH2_INT_ENA
+              The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              read-write
+            
+            
+              OUT_EOF_CH2_INT_ENA
+              The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              read-write
+            
+            
+              IN_DSCR_ERR_CH2_INT_ENA
+              The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              read-write
+            
+            
+              OUT_DSCR_ERR_CH2_INT_ENA
+              The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              read-write
+            
+            
+              IN_DSCR_EMPTY_CH2_INT_ENA
+              The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              read-write
+            
+            
+              OUT_TOTAL_EOF_CH2_INT_ENA
+              The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              read-write
+            
+            
+              INFIFO_OVF_CH2_INT_ENA
+              The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              read-write
+            
+            
+              INFIFO_UDF_CH2_INT_ENA
+              The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              read-write
+            
+            
+              OUTFIFO_OVF_CH2_INT_ENA
+              The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              read-write
+            
+            
+              OUTFIFO_UDF_CH2_INT_ENA
+              The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR_CH2
+          DMA_INT_CLR_CH2_REG.
+          0x2C
+          0x20
+          
+            
+              IN_DONE_CH2_INT_CLR
+              Set this bit to clear the IN_DONE_CH_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              IN_SUC_EOF_CH2_INT_CLR
+              Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              IN_ERR_EOF_CH2_INT_CLR
+              Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+              2
+              1
+              write-only
+            
+            
+              OUT_DONE_CH2_INT_CLR
+              Set this bit to clear the OUT_DONE_CH_INT interrupt.
+              3
+              1
+              write-only
+            
+            
+              OUT_EOF_CH2_INT_CLR
+              Set this bit to clear the OUT_EOF_CH_INT interrupt.
+              4
+              1
+              write-only
+            
+            
+              IN_DSCR_ERR_CH2_INT_CLR
+              Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+              5
+              1
+              write-only
+            
+            
+              OUT_DSCR_ERR_CH2_INT_CLR
+              Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+              6
+              1
+              write-only
+            
+            
+              IN_DSCR_EMPTY_CH2_INT_CLR
+              Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+              7
+              1
+              write-only
+            
+            
+              OUT_TOTAL_EOF_CH2_INT_CLR
+              Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+              8
+              1
+              write-only
+            
+            
+              INFIFO_OVF_CH2_INT_CLR
+              Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+              9
+              1
+              write-only
+            
+            
+              INFIFO_UDF_CH2_INT_CLR
+              Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+              10
+              1
+              write-only
+            
+            
+              OUTFIFO_OVF_CH2_INT_CLR
+              Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+              11
+              1
+              write-only
+            
+            
+              OUTFIFO_UDF_CH2_INT_CLR
+              Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+              12
+              1
+              write-only
+            
+          
+        
+        
+          AHB_TEST
+          DMA_AHB_TEST_REG.
+          0x40
+          0x20
+          
+            
+              AHB_TESTMODE
+              reserved
+              0
+              3
+              read-write
+            
+            
+              AHB_TESTADDR
+              reserved
+              4
+              2
+              read-write
+            
+          
+        
+        
+          MISC_CONF
+          DMA_MISC_CONF_REG.
+          0x44
+          0x20
+          
+            
+              AHBM_RST_INTER
+              Set this bit, then clear this bit to reset the internal ahb FSM.
+              0
+              1
+              read-write
+            
+            
+              ARB_PRI_DIS
+              Set this bit to disable priority arbitration function.
+              2
+              1
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en
+              3
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          DMA_DATE_REG.
+          0x48
+          0x20
+          0x02008250
+          
+            
+              DATE
+              register version.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          IN_CONF0_CH0
+          DMA_IN_CONF0_CH0_REG.
+          0x70
+          0x20
+          
+            
+              IN_RST_CH0
+              This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              IN_LOOP_TEST_CH0
+              reserved
+              1
+              1
+              read-write
+            
+            
+              INDSCR_BURST_EN_CH0
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.
+              2
+              1
+              read-write
+            
+            
+              IN_DATA_BURST_EN_CH0
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.
+              3
+              1
+              read-write
+            
+            
+              MEM_TRANS_EN_CH0
+              Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+              4
+              1
+              read-write
+            
+          
+        
+        
+          IN_CONF1_CH0
+          DMA_IN_CONF1_CH0_REG.
+          0x74
+          0x20
+          
+            
+              IN_CHECK_OWNER_CH0
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INFIFO_STATUS_CH0
+          DMA_INFIFO_STATUS_CH0_REG.
+          0x78
+          0x20
+          0x07800003
+          
+            
+              INFIFO_FULL_CH0
+              L1 Rx FIFO full signal for Rx channel 0.
+              0
+              1
+              read-only
+            
+            
+              INFIFO_EMPTY_CH0
+              L1 Rx FIFO empty signal for Rx channel 0.
+              1
+              1
+              read-only
+            
+            
+              INFIFO_CNT_CH0
+              The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+              2
+              6
+              read-only
+            
+            
+              IN_REMAIN_UNDER_1B_CH0
+              reserved
+              23
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_2B_CH0
+              reserved
+              24
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_3B_CH0
+              reserved
+              25
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_4B_CH0
+              reserved
+              26
+              1
+              read-only
+            
+            
+              IN_BUF_HUNGRY_CH0
+              reserved
+              27
+              1
+              read-only
+            
+          
+        
+        
+          IN_POP_CH0
+          DMA_IN_POP_CH0_REG.
+          0x7C
+          0x20
+          0x00000800
+          
+            
+              INFIFO_RDATA_CH0
+              This register stores the data popping from DMA FIFO.
+              0
+              12
+              read-only
+            
+            
+              INFIFO_POP_CH0
+              Set this bit to pop data from DMA FIFO.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          IN_LINK_CH0
+          DMA_IN_LINK_CH0_REG.
+          0x80
+          0x20
+          0x01100000
+          
+            
+              INLINK_ADDR_CH0
+              This register stores the 20 least significant bits of the first inlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              INLINK_AUTO_RET_CH0
+              Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+              20
+              1
+              read-write
+            
+            
+              INLINK_STOP_CH0
+              Set this bit to stop dealing with the inlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              INLINK_START_CH0
+              Set this bit to start dealing with the inlink descriptors.
+              22
+              1
+              read-write
+            
+            
+              INLINK_RESTART_CH0
+              Set this bit to mount a new inlink descriptor.
+              23
+              1
+              read-write
+            
+            
+              INLINK_PARK_CH0
+              1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.
+              24
+              1
+              read-only
+            
+          
+        
+        
+          IN_STATE_CH0
+          DMA_IN_STATE_CH0_REG.
+          0x84
+          0x20
+          
+            
+              INLINK_DSCR_ADDR_CH0
+              This register stores the current inlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              IN_DSCR_STATE_CH0
+              reserved
+              18
+              2
+              read-only
+            
+            
+              IN_STATE_CH0
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          IN_SUC_EOF_DES_ADDR_CH0
+          DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
+          0x88
+          0x20
+          
+            
+              IN_SUC_EOF_DES_ADDR_CH0
+              This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_ERR_EOF_DES_ADDR_CH0
+          DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
+          0x8C
+          0x20
+          
+            
+              IN_ERR_EOF_DES_ADDR_CH0
+              This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_CH0
+          DMA_IN_DSCR_CH0_REG.
+          0x90
+          0x20
+          
+            
+              INLINK_DSCR_CH0
+              The address of the current inlink descriptor x.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF0_CH0
+          DMA_IN_DSCR_BF0_CH0_REG.
+          0x94
+          0x20
+          
+            
+              INLINK_DSCR_BF0_CH0
+              The address of the last inlink descriptor x-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF1_CH0
+          DMA_IN_DSCR_BF1_CH0_REG.
+          0x98
+          0x20
+          
+            
+              INLINK_DSCR_BF1_CH0
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_PRI_CH0
+          DMA_IN_PRI_CH0_REG.
+          0x9C
+          0x20
+          
+            
+              RX_PRI_CH0
+              The priority of Rx channel 0. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          IN_PERI_SEL_CH0
+          DMA_IN_PERI_SEL_CH0_REG.
+          0xA0
+          0x20
+          0x0000003F
+          
+            
+              PERI_IN_SEL_CH0
+              This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          OUT_CONF0_CH0
+          DMA_OUT_CONF0_CH0_REG.
+          0xD0
+          0x20
+          0x00000008
+          
+            
+              OUT_RST_CH0
+              This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              OUT_LOOP_TEST_CH0
+              reserved
+              1
+              1
+              read-write
+            
+            
+              OUT_AUTO_WRBACK_CH0
+              Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+              2
+              1
+              read-write
+            
+            
+              OUT_EOF_MODE_CH0
+              EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA
+              3
+              1
+              read-write
+            
+            
+              OUTDSCR_BURST_EN_CH0
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.
+              4
+              1
+              read-write
+            
+            
+              OUT_DATA_BURST_EN_CH0
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.
+              5
+              1
+              read-write
+            
+          
+        
+        
+          OUT_CONF1_CH0
+          DMA_OUT_CONF1_CH0_REG.
+          0xD4
+          0x20
+          
+            
+              OUT_CHECK_OWNER_CH0
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          OUTFIFO_STATUS_CH0
+          DMA_OUTFIFO_STATUS_CH0_REG.
+          0xD8
+          0x20
+          0x07800002
+          
+            
+              OUTFIFO_FULL_CH0
+              L1 Tx FIFO full signal for Tx channel 0.
+              0
+              1
+              read-only
+            
+            
+              OUTFIFO_EMPTY_CH0
+              L1 Tx FIFO empty signal for Tx channel 0.
+              1
+              1
+              read-only
+            
+            
+              OUTFIFO_CNT_CH0
+              The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+              2
+              6
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_1B_CH0
+              reserved
+              23
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_2B_CH0
+              reserved
+              24
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_3B_CH0
+              reserved
+              25
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_4B_CH0
+              reserved
+              26
+              1
+              read-only
+            
+          
+        
+        
+          OUT_PUSH_CH0
+          DMA_OUT_PUSH_CH0_REG.
+          0xDC
+          0x20
+          
+            
+              OUTFIFO_WDATA_CH0
+              This register stores the data that need to be pushed into DMA FIFO.
+              0
+              9
+              read-write
+            
+            
+              OUTFIFO_PUSH_CH0
+              Set this bit to push data into DMA FIFO.
+              9
+              1
+              read-write
+            
+          
+        
+        
+          OUT_LINK_CH0
+          DMA_OUT_LINK_CH0_REG.
+          0xE0
+          0x20
+          0x00800000
+          
+            
+              OUTLINK_ADDR_CH0
+              This register stores the 20 least significant bits of the first outlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              OUTLINK_STOP_CH0
+              Set this bit to stop dealing with the outlink descriptors.
+              20
+              1
+              read-write
+            
+            
+              OUTLINK_START_CH0
+              Set this bit to start dealing with the outlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              OUTLINK_RESTART_CH0
+              Set this bit to restart a new outlink from the last address.
+              22
+              1
+              read-write
+            
+            
+              OUTLINK_PARK_CH0
+              1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.
+              23
+              1
+              read-only
+            
+          
+        
+        
+          OUT_STATE_CH0
+          DMA_OUT_STATE_CH0_REG.
+          0xE4
+          0x20
+          
+            
+              OUTLINK_DSCR_ADDR_CH0
+              This register stores the current outlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              OUT_DSCR_STATE_CH0
+              reserved
+              18
+              2
+              read-only
+            
+            
+              OUT_STATE_CH0
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          OUT_EOF_DES_ADDR_CH0
+          DMA_OUT_EOF_DES_ADDR_CH0_REG.
+          0xE8
+          0x20
+          
+            
+              OUT_EOF_DES_ADDR_CH0
+              This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_EOF_BFR_DES_ADDR_CH0
+          DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
+          0xEC
+          0x20
+          
+            
+              OUT_EOF_BFR_DES_ADDR_CH0
+              This register stores the address of the outlink descriptor before the last outlink descriptor.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_CH0
+          DMA_OUT_DSCR_CH0_REG.
+          0xF0
+          0x20
+          
+            
+              OUTLINK_DSCR_CH0
+              The address of the current outlink descriptor y.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF0_CH0
+          DMA_OUT_DSCR_BF0_CH0_REG.
+          0xF4
+          0x20
+          
+            
+              OUTLINK_DSCR_BF0_CH0
+              The address of the last outlink descriptor y-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF1_CH0
+          DMA_OUT_DSCR_BF1_CH0_REG.
+          0xF8
+          0x20
+          
+            
+              OUTLINK_DSCR_BF1_CH0
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_PRI_CH0
+          DMA_OUT_PRI_CH0_REG.
+          0xFC
+          0x20
+          
+            
+              TX_PRI_CH0
+              The priority of Tx channel 0. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          OUT_PERI_SEL_CH0
+          DMA_OUT_PERI_SEL_CH0_REG.
+          0x100
+          0x20
+          0x0000003F
+          
+            
+              PERI_OUT_SEL_CH0
+              This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          IN_CONF0_CH1
+          DMA_IN_CONF0_CH1_REG.
+          0x130
+          0x20
+          
+            
+              IN_RST_CH1
+              This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              IN_LOOP_TEST_CH1
+              reserved
+              1
+              1
+              read-write
+            
+            
+              INDSCR_BURST_EN_CH1
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.
+              2
+              1
+              read-write
+            
+            
+              IN_DATA_BURST_EN_CH1
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.
+              3
+              1
+              read-write
+            
+            
+              MEM_TRANS_EN_CH1
+              Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+              4
+              1
+              read-write
+            
+          
+        
+        
+          IN_CONF1_CH1
+          DMA_IN_CONF1_CH1_REG.
+          0x134
+          0x20
+          
+            
+              IN_CHECK_OWNER_CH1
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INFIFO_STATUS_CH1
+          DMA_INFIFO_STATUS_CH1_REG.
+          0x138
+          0x20
+          0x07800003
+          
+            
+              INFIFO_FULL_CH1
+              L1 Rx FIFO full signal for Rx channel 1.
+              0
+              1
+              read-only
+            
+            
+              INFIFO_EMPTY_CH1
+              L1 Rx FIFO empty signal for Rx channel 1.
+              1
+              1
+              read-only
+            
+            
+              INFIFO_CNT_CH1
+              The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.
+              2
+              6
+              read-only
+            
+            
+              IN_REMAIN_UNDER_1B_CH1
+              reserved
+              23
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_2B_CH1
+              reserved
+              24
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_3B_CH1
+              reserved
+              25
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_4B_CH1
+              reserved
+              26
+              1
+              read-only
+            
+            
+              IN_BUF_HUNGRY_CH1
+              reserved
+              27
+              1
+              read-only
+            
+          
+        
+        
+          IN_POP_CH1
+          DMA_IN_POP_CH1_REG.
+          0x13C
+          0x20
+          0x00000800
+          
+            
+              INFIFO_RDATA_CH1
+              This register stores the data popping from DMA FIFO.
+              0
+              12
+              read-only
+            
+            
+              INFIFO_POP_CH1
+              Set this bit to pop data from DMA FIFO.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          IN_LINK_CH1
+          DMA_IN_LINK_CH1_REG.
+          0x140
+          0x20
+          0x01100000
+          
+            
+              INLINK_ADDR_CH1
+              This register stores the 20 least significant bits of the first inlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              INLINK_AUTO_RET_CH1
+              Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+              20
+              1
+              read-write
+            
+            
+              INLINK_STOP_CH1
+              Set this bit to stop dealing with the inlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              INLINK_START_CH1
+              Set this bit to start dealing with the inlink descriptors.
+              22
+              1
+              read-write
+            
+            
+              INLINK_RESTART_CH1
+              Set this bit to mount a new inlink descriptor.
+              23
+              1
+              read-write
+            
+            
+              INLINK_PARK_CH1
+              1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.
+              24
+              1
+              read-only
+            
+          
+        
+        
+          IN_STATE_CH1
+          DMA_IN_STATE_CH1_REG.
+          0x144
+          0x20
+          
+            
+              INLINK_DSCR_ADDR_CH1
+              This register stores the current inlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              IN_DSCR_STATE_CH1
+              reserved
+              18
+              2
+              read-only
+            
+            
+              IN_STATE_CH1
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          IN_SUC_EOF_DES_ADDR_CH1
+          DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.
+          0x148
+          0x20
+          
+            
+              IN_SUC_EOF_DES_ADDR_CH1
+              This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_ERR_EOF_DES_ADDR_CH1
+          DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.
+          0x14C
+          0x20
+          
+            
+              IN_ERR_EOF_DES_ADDR_CH1
+              This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_CH1
+          DMA_IN_DSCR_CH1_REG.
+          0x150
+          0x20
+          
+            
+              INLINK_DSCR_CH1
+              The address of the current inlink descriptor x.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF0_CH1
+          DMA_IN_DSCR_BF0_CH1_REG.
+          0x154
+          0x20
+          
+            
+              INLINK_DSCR_BF0_CH1
+              The address of the last inlink descriptor x-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF1_CH1
+          DMA_IN_DSCR_BF1_CH1_REG.
+          0x158
+          0x20
+          
+            
+              INLINK_DSCR_BF1_CH1
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_PRI_CH1
+          DMA_IN_PRI_CH1_REG.
+          0x15C
+          0x20
+          
+            
+              RX_PRI_CH1
+              The priority of Rx channel 1. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          IN_PERI_SEL_CH1
+          DMA_IN_PERI_SEL_CH1_REG.
+          0x160
+          0x20
+          0x0000003F
+          
+            
+              PERI_IN_SEL_CH1
+              This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          OUT_CONF0_CH1
+          DMA_OUT_CONF0_CH1_REG.
+          0x190
+          0x20
+          0x00000008
+          
+            
+              OUT_RST_CH1
+              This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              OUT_LOOP_TEST_CH1
+              reserved
+              1
+              1
+              read-write
+            
+            
+              OUT_AUTO_WRBACK_CH1
+              Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+              2
+              1
+              read-write
+            
+            
+              OUT_EOF_MODE_CH1
+              EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA
+              3
+              1
+              read-write
+            
+            
+              OUTDSCR_BURST_EN_CH1
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.
+              4
+              1
+              read-write
+            
+            
+              OUT_DATA_BURST_EN_CH1
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.
+              5
+              1
+              read-write
+            
+          
+        
+        
+          OUT_CONF1_CH1
+          DMA_OUT_CONF1_CH1_REG.
+          0x194
+          0x20
+          
+            
+              OUT_CHECK_OWNER_CH1
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          OUTFIFO_STATUS_CH1
+          DMA_OUTFIFO_STATUS_CH1_REG.
+          0x198
+          0x20
+          0x07800002
+          
+            
+              OUTFIFO_FULL_CH1
+              L1 Tx FIFO full signal for Tx channel 1.
+              0
+              1
+              read-only
+            
+            
+              OUTFIFO_EMPTY_CH1
+              L1 Tx FIFO empty signal for Tx channel 1.
+              1
+              1
+              read-only
+            
+            
+              OUTFIFO_CNT_CH1
+              The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.
+              2
+              6
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_1B_CH1
+              reserved
+              23
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_2B_CH1
+              reserved
+              24
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_3B_CH1
+              reserved
+              25
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_4B_CH1
+              reserved
+              26
+              1
+              read-only
+            
+          
+        
+        
+          OUT_PUSH_CH1
+          DMA_OUT_PUSH_CH1_REG.
+          0x19C
+          0x20
+          
+            
+              OUTFIFO_WDATA_CH1
+              This register stores the data that need to be pushed into DMA FIFO.
+              0
+              9
+              read-write
+            
+            
+              OUTFIFO_PUSH_CH1
+              Set this bit to push data into DMA FIFO.
+              9
+              1
+              read-write
+            
+          
+        
+        
+          OUT_LINK_CH1
+          DMA_OUT_LINK_CH1_REG.
+          0x1A0
+          0x20
+          0x00800000
+          
+            
+              OUTLINK_ADDR_CH1
+              This register stores the 20 least significant bits of the first outlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              OUTLINK_STOP_CH1
+              Set this bit to stop dealing with the outlink descriptors.
+              20
+              1
+              read-write
+            
+            
+              OUTLINK_START_CH1
+              Set this bit to start dealing with the outlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              OUTLINK_RESTART_CH1
+              Set this bit to restart a new outlink from the last address.
+              22
+              1
+              read-write
+            
+            
+              OUTLINK_PARK_CH1
+              1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.
+              23
+              1
+              read-only
+            
+          
+        
+        
+          OUT_STATE_CH1
+          DMA_OUT_STATE_CH1_REG.
+          0x1A4
+          0x20
+          
+            
+              OUTLINK_DSCR_ADDR_CH1
+              This register stores the current outlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              OUT_DSCR_STATE_CH1
+              reserved
+              18
+              2
+              read-only
+            
+            
+              OUT_STATE_CH1
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          OUT_EOF_DES_ADDR_CH1
+          DMA_OUT_EOF_DES_ADDR_CH1_REG.
+          0x1A8
+          0x20
+          
+            
+              OUT_EOF_DES_ADDR_CH1
+              This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_EOF_BFR_DES_ADDR_CH1
+          DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.
+          0x1AC
+          0x20
+          
+            
+              OUT_EOF_BFR_DES_ADDR_CH1
+              This register stores the address of the outlink descriptor before the last outlink descriptor.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_CH1
+          DMA_OUT_DSCR_CH1_REG.
+          0x1B0
+          0x20
+          
+            
+              OUTLINK_DSCR_CH1
+              The address of the current outlink descriptor y.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF0_CH1
+          DMA_OUT_DSCR_BF0_CH1_REG.
+          0x1B4
+          0x20
+          
+            
+              OUTLINK_DSCR_BF0_CH1
+              The address of the last outlink descriptor y-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF1_CH1
+          DMA_OUT_DSCR_BF1_CH1_REG.
+          0x1B8
+          0x20
+          
+            
+              OUTLINK_DSCR_BF1_CH1
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_PRI_CH1
+          DMA_OUT_PRI_CH1_REG.
+          0x1BC
+          0x20
+          
+            
+              TX_PRI_CH1
+              The priority of Tx channel 1. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          OUT_PERI_SEL_CH1
+          DMA_OUT_PERI_SEL_CH1_REG.
+          0x1C0
+          0x20
+          0x0000003F
+          
+            
+              PERI_OUT_SEL_CH1
+              This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          IN_CONF0_CH2
+          DMA_IN_CONF0_CH2_REG.
+          0x1F0
+          0x20
+          
+            
+              IN_RST_CH2
+              This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              IN_LOOP_TEST_CH2
+              reserved
+              1
+              1
+              read-write
+            
+            
+              INDSCR_BURST_EN_CH2
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.
+              2
+              1
+              read-write
+            
+            
+              IN_DATA_BURST_EN_CH2
+              Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.
+              3
+              1
+              read-write
+            
+            
+              MEM_TRANS_EN_CH2
+              Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+              4
+              1
+              read-write
+            
+          
+        
+        
+          IN_CONF1_CH2
+          DMA_IN_CONF1_CH2_REG.
+          0x1F4
+          0x20
+          
+            
+              IN_CHECK_OWNER_CH2
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INFIFO_STATUS_CH2
+          DMA_INFIFO_STATUS_CH2_REG.
+          0x1F8
+          0x20
+          0x07800003
+          
+            
+              INFIFO_FULL_CH2
+              L1 Rx FIFO full signal for Rx channel 2.
+              0
+              1
+              read-only
+            
+            
+              INFIFO_EMPTY_CH2
+              L1 Rx FIFO empty signal for Rx channel 2.
+              1
+              1
+              read-only
+            
+            
+              INFIFO_CNT_CH2
+              The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.
+              2
+              6
+              read-only
+            
+            
+              IN_REMAIN_UNDER_1B_CH2
+              reserved
+              23
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_2B_CH2
+              reserved
+              24
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_3B_CH2
+              reserved
+              25
+              1
+              read-only
+            
+            
+              IN_REMAIN_UNDER_4B_CH2
+              reserved
+              26
+              1
+              read-only
+            
+            
+              IN_BUF_HUNGRY_CH2
+              reserved
+              27
+              1
+              read-only
+            
+          
+        
+        
+          IN_POP_CH2
+          DMA_IN_POP_CH2_REG.
+          0x1FC
+          0x20
+          0x00000800
+          
+            
+              INFIFO_RDATA_CH2
+              This register stores the data popping from DMA FIFO.
+              0
+              12
+              read-only
+            
+            
+              INFIFO_POP_CH2
+              Set this bit to pop data from DMA FIFO.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          IN_LINK_CH2
+          DMA_IN_LINK_CH2_REG.
+          0x200
+          0x20
+          0x01100000
+          
+            
+              INLINK_ADDR_CH2
+              This register stores the 20 least significant bits of the first inlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              INLINK_AUTO_RET_CH2
+              Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+              20
+              1
+              read-write
+            
+            
+              INLINK_STOP_CH2
+              Set this bit to stop dealing with the inlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              INLINK_START_CH2
+              Set this bit to start dealing with the inlink descriptors.
+              22
+              1
+              read-write
+            
+            
+              INLINK_RESTART_CH2
+              Set this bit to mount a new inlink descriptor.
+              23
+              1
+              read-write
+            
+            
+              INLINK_PARK_CH2
+              1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.
+              24
+              1
+              read-only
+            
+          
+        
+        
+          IN_STATE_CH2
+          DMA_IN_STATE_CH2_REG.
+          0x204
+          0x20
+          
+            
+              INLINK_DSCR_ADDR_CH2
+              This register stores the current inlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              IN_DSCR_STATE_CH2
+              reserved
+              18
+              2
+              read-only
+            
+            
+              IN_STATE_CH2
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          IN_SUC_EOF_DES_ADDR_CH2
+          DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.
+          0x208
+          0x20
+          
+            
+              IN_SUC_EOF_DES_ADDR_CH2
+              This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_ERR_EOF_DES_ADDR_CH2
+          DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.
+          0x20C
+          0x20
+          
+            
+              IN_ERR_EOF_DES_ADDR_CH2
+              This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_CH2
+          DMA_IN_DSCR_CH2_REG.
+          0x210
+          0x20
+          
+            
+              INLINK_DSCR_CH2
+              The address of the current inlink descriptor x.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF0_CH2
+          DMA_IN_DSCR_BF0_CH2_REG.
+          0x214
+          0x20
+          
+            
+              INLINK_DSCR_BF0_CH2
+              The address of the last inlink descriptor x-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_DSCR_BF1_CH2
+          DMA_IN_DSCR_BF1_CH2_REG.
+          0x218
+          0x20
+          
+            
+              INLINK_DSCR_BF1_CH2
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IN_PRI_CH2
+          DMA_IN_PRI_CH2_REG.
+          0x21C
+          0x20
+          
+            
+              RX_PRI_CH2
+              The priority of Rx channel 2. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          IN_PERI_SEL_CH2
+          DMA_IN_PERI_SEL_CH2_REG.
+          0x220
+          0x20
+          0x0000003F
+          
+            
+              PERI_IN_SEL_CH2
+              This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          OUT_CONF0_CH2
+          DMA_OUT_CONF0_CH2_REG.
+          0x250
+          0x20
+          0x00000008
+          
+            
+              OUT_RST_CH2
+              This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
+              0
+              1
+              read-write
+            
+            
+              OUT_LOOP_TEST_CH2
+              reserved
+              1
+              1
+              read-write
+            
+            
+              OUT_AUTO_WRBACK_CH2
+              Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+              2
+              1
+              read-write
+            
+            
+              OUT_EOF_MODE_CH2
+              EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA
+              3
+              1
+              read-write
+            
+            
+              OUTDSCR_BURST_EN_CH2
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.
+              4
+              1
+              read-write
+            
+            
+              OUT_DATA_BURST_EN_CH2
+              Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.
+              5
+              1
+              read-write
+            
+          
+        
+        
+          OUT_CONF1_CH2
+          DMA_OUT_CONF1_CH2_REG.
+          0x254
+          0x20
+          
+            
+              OUT_CHECK_OWNER_CH2
+              Set this bit to enable checking the owner attribute of the link descriptor.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          OUTFIFO_STATUS_CH2
+          DMA_OUTFIFO_STATUS_CH2_REG.
+          0x258
+          0x20
+          0x07800002
+          
+            
+              OUTFIFO_FULL_CH2
+              L1 Tx FIFO full signal for Tx channel 2.
+              0
+              1
+              read-only
+            
+            
+              OUTFIFO_EMPTY_CH2
+              L1 Tx FIFO empty signal for Tx channel 2.
+              1
+              1
+              read-only
+            
+            
+              OUTFIFO_CNT_CH2
+              The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.
+              2
+              6
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_1B_CH2
+              reserved
+              23
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_2B_CH2
+              reserved
+              24
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_3B_CH2
+              reserved
+              25
+              1
+              read-only
+            
+            
+              OUT_REMAIN_UNDER_4B_CH2
+              reserved
+              26
+              1
+              read-only
+            
+          
+        
+        
+          OUT_PUSH_CH2
+          DMA_OUT_PUSH_CH2_REG.
+          0x25C
+          0x20
+          
+            
+              OUTFIFO_WDATA_CH2
+              This register stores the data that need to be pushed into DMA FIFO.
+              0
+              9
+              read-write
+            
+            
+              OUTFIFO_PUSH_CH2
+              Set this bit to push data into DMA FIFO.
+              9
+              1
+              read-write
+            
+          
+        
+        
+          OUT_LINK_CH2
+          DMA_OUT_LINK_CH2_REG.
+          0x260
+          0x20
+          0x00800000
+          
+            
+              OUTLINK_ADDR_CH2
+              This register stores the 20 least significant bits of the first outlink descriptor's address.
+              0
+              20
+              read-write
+            
+            
+              OUTLINK_STOP_CH2
+              Set this bit to stop dealing with the outlink descriptors.
+              20
+              1
+              read-write
+            
+            
+              OUTLINK_START_CH2
+              Set this bit to start dealing with the outlink descriptors.
+              21
+              1
+              read-write
+            
+            
+              OUTLINK_RESTART_CH2
+              Set this bit to restart a new outlink from the last address.
+              22
+              1
+              read-write
+            
+            
+              OUTLINK_PARK_CH2
+              1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.
+              23
+              1
+              read-only
+            
+          
+        
+        
+          OUT_STATE_CH2
+          DMA_OUT_STATE_CH2_REG.
+          0x264
+          0x20
+          
+            
+              OUTLINK_DSCR_ADDR_CH2
+              This register stores the current outlink descriptor's address.
+              0
+              18
+              read-only
+            
+            
+              OUT_DSCR_STATE_CH2
+              reserved
+              18
+              2
+              read-only
+            
+            
+              OUT_STATE_CH2
+              reserved
+              20
+              3
+              read-only
+            
+          
+        
+        
+          OUT_EOF_DES_ADDR_CH2
+          DMA_OUT_EOF_DES_ADDR_CH2_REG.
+          0x268
+          0x20
+          
+            
+              OUT_EOF_DES_ADDR_CH2
+              This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_EOF_BFR_DES_ADDR_CH2
+          DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.
+          0x26C
+          0x20
+          
+            
+              OUT_EOF_BFR_DES_ADDR_CH2
+              This register stores the address of the outlink descriptor before the last outlink descriptor.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_CH2
+          DMA_OUT_DSCR_CH2_REG.
+          0x270
+          0x20
+          
+            
+              OUTLINK_DSCR_CH2
+              The address of the current outlink descriptor y.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF0_CH2
+          DMA_OUT_DSCR_BF0_CH2_REG.
+          0x274
+          0x20
+          
+            
+              OUTLINK_DSCR_BF0_CH2
+              The address of the last outlink descriptor y-1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_DSCR_BF1_CH2
+          DMA_OUT_DSCR_BF1_CH2_REG.
+          0x278
+          0x20
+          
+            
+              OUTLINK_DSCR_BF1_CH2
+              The address of the second-to-last inlink descriptor x-2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          OUT_PRI_CH2
+          DMA_OUT_PRI_CH2_REG.
+          0x27C
+          0x20
+          
+            
+              TX_PRI_CH2
+              The priority of Tx channel 2. The larger of the value, the higher of the priority.
+              0
+              4
+              read-write
+            
+          
+        
+        
+          OUT_PERI_SEL_CH2
+          DMA_OUT_PERI_SEL_CH2_REG.
+          0x280
+          0x20
+          0x0000003F
+          
+            
+              PERI_OUT_SEL_CH2
+              This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+              0
+              6
+              read-write
+            
+          
+        
+      
+    
+    
+      DS
+      Digital Signature
+      DS
+      0x6003D000
+      
+        0x0
+        0xA4C
+        registers
+      
+      
+        
+          512
+          0x1
+          Y_MEM[%s]
+          memory that stores Y
+          0x0
+          0x8
+        
+        
+          512
+          0x1
+          M_MEM[%s]
+          memory that stores M
+          0x200
+          0x8
+        
+        
+          512
+          0x1
+          RB_MEM[%s]
+          memory that stores Rb
+          0x400
+          0x8
+        
+        
+          48
+          0x1
+          BOX_MEM[%s]
+          memory that stores BOX
+          0x600
+          0x8
+        
+        
+          512
+          0x1
+          X_MEM[%s]
+          memory that stores X
+          0x800
+          0x8
+        
+        
+          512
+          0x1
+          Z_MEM[%s]
+          memory that stores Z
+          0xA00
+          0x8
+        
+        
+          SET_START
+          DS start control register
+          0xE00
+          0x20
+          
+            
+              SET_START
+              set this bit to start DS operation.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_CONTINUE
+          DS continue control register
+          0xE04
+          0x20
+          
+            
+              SET_CONTINUE
+              set this bit to continue DS operation.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_FINISH
+          DS finish control register
+          0xE08
+          0x20
+          
+            
+              SET_FINISH
+              Set this bit to finish DS process.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          QUERY_BUSY
+          DS query busy register
+          0xE0C
+          0x20
+          
+            
+              QUERY_BUSY
+              digital signature state. 1'b0: idle, 1'b1: busy
+              0
+              1
+              read-only
+            
+          
+        
+        
+          QUERY_KEY_WRONG
+          DS query key-wrong counter register
+          0xE10
+          0x20
+          
+            
+              QUERY_KEY_WRONG
+              digital signature key wrong counter
+              0
+              4
+              read-only
+            
+          
+        
+        
+          QUERY_CHECK
+          DS query check result register
+          0xE14
+          0x20
+          
+            
+              MD_ERROR
+              MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
+              0
+              1
+              read-only
+            
+            
+              PADDING_BAD
+              padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
+              1
+              1
+              read-only
+            
+          
+        
+        
+          DATE
+          DS version control register
+          0xE20
+          0x20
+          0x20200618
+          
+            
+              DATE
+              ds version information
+              0
+              30
+              read-write
+            
+          
+        
+      
+    
+    
+      EFUSE
+      eFuse Controller
+      EFUSE
+      0x60008800
+      
+        0x0
+        0x1CC
+        registers
+      
+      
+        EFUSE
+        24
+      
+      
+        
+          PGM_DATA0
+          Register 0 that stores data to be programmed.
+          0x0
+          0x20
+          
+            
+              PGM_DATA_0
+              The content of the 0th 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA1
+          Register 1 that stores data to be programmed.
+          0x4
+          0x20
+          
+            
+              PGM_DATA_1
+              The content of the 1st 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA2
+          Register 2 that stores data to be programmed.
+          0x8
+          0x20
+          
+            
+              PGM_DATA_2
+              The content of the 2nd 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA3
+          Register 3 that stores data to be programmed.
+          0xC
+          0x20
+          
+            
+              PGM_DATA_3
+              The content of the 3rd 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA4
+          Register 4 that stores data to be programmed.
+          0x10
+          0x20
+          
+            
+              PGM_DATA_4
+              The content of the 4th 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA5
+          Register 5 that stores data to be programmed.
+          0x14
+          0x20
+          
+            
+              PGM_DATA_5
+              The content of the 5th 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA6
+          Register 6 that stores data to be programmed.
+          0x18
+          0x20
+          
+            
+              PGM_DATA_6
+              The content of the 6th 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_DATA7
+          Register 7 that stores data to be programmed.
+          0x1C
+          0x20
+          
+            
+              PGM_DATA_7
+              The content of the 7th 32-bit data to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_CHECK_VALUE0
+          Register 0 that stores the RS code to be programmed.
+          0x20
+          0x20
+          
+            
+              PGM_RS_DATA_0
+              The content of the 0th 32-bit RS code to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_CHECK_VALUE1
+          Register 1 that stores the RS code to be programmed.
+          0x24
+          0x20
+          
+            
+              PGM_RS_DATA_1
+              The content of the 1st 32-bit RS code to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PGM_CHECK_VALUE2
+          Register 2 that stores the RS code to be programmed.
+          0x28
+          0x20
+          
+            
+              PGM_RS_DATA_2
+              The content of the 2nd 32-bit RS code to be programmed.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          RD_WR_DIS
+          BLOCK0 data register 0.
+          0x2C
+          0x20
+          
+            
+              WR_DIS
+              Disable programming of individual eFuses.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_DATA0
+          BLOCK0 data register 1.
+          0x30
+          0x20
+          
+            
+              RD_DIS
+              Set this bit to disable reading from BlOCK4-10.
+              0
+              7
+              read-only
+            
+            
+              DIS_RTC_RAM_BOOT
+              Set this bit to disable boot from RTC RAM.
+              7
+              1
+              read-only
+            
+            
+              DIS_ICACHE
+              Set this bit to disable Icache.
+              8
+              1
+              read-only
+            
+            
+              DIS_USB_JTAG
+              Set this bit to disable function of usb switch to jtag in module of usb device.
+              9
+              1
+              read-only
+            
+            
+              DIS_DOWNLOAD_ICACHE
+              Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).
+              10
+              1
+              read-only
+            
+            
+              DIS_USB_DEVICE
+              Set this bit to disable usb device.
+              11
+              1
+              read-only
+            
+            
+              DIS_FORCE_DOWNLOAD
+              Set this bit to disable the function that forces chip into download mode.
+              12
+              1
+              read-only
+            
+            
+              RPT4_RESERVED6
+              Reserved (used for four backups method).
+              13
+              1
+              read-only
+            
+            
+              DIS_CAN
+              Set this bit to disable CAN function.
+              14
+              1
+              read-only
+            
+            
+              JTAG_SEL_ENABLE
+              Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+              15
+              1
+              read-only
+            
+            
+              SOFT_DIS_JTAG
+              Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.
+              16
+              3
+              read-only
+            
+            
+              DIS_PAD_JTAG
+              Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+              19
+              1
+              read-only
+            
+            
+              DIS_DOWNLOAD_MANUAL_ENCRYPT
+              Set this bit to disable flash encryption when in download boot modes.
+              20
+              1
+              read-only
+            
+            
+              USB_DREFH
+              Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.
+              21
+              2
+              read-only
+            
+            
+              USB_DREFL
+              Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.
+              23
+              2
+              read-only
+            
+            
+              USB_EXCHG_PINS
+              Set this bit to exchange USB D+ and D- pins.
+              25
+              1
+              read-only
+            
+            
+              VDD_SPI_AS_GPIO
+              Set this bit to vdd spi pin function as gpio.
+              26
+              1
+              read-only
+            
+            
+              BTLC_GPIO_ENABLE
+              Enable btlc gpio.
+              27
+              2
+              read-only
+            
+            
+              POWERGLITCH_EN
+              Set this bit to enable power glitch function.
+              29
+              1
+              read-only
+            
+            
+              POWER_GLITCH_DSENSE
+              Sample delay configuration of power glitch.
+              30
+              2
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_DATA1
+          BLOCK0 data register 2.
+          0x34
+          0x20
+          
+            
+              RPT4_RESERVED2
+              Reserved (used for four backups method).
+              0
+              16
+              read-only
+            
+            
+              WDT_DELAY_SEL
+              Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.
+              16
+              2
+              read-only
+            
+            
+              SPI_BOOT_CRYPT_CNT
+              Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.
+              18
+              3
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE0
+              Set this bit to enable revoking first secure boot key.
+              21
+              1
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE1
+              Set this bit to enable revoking second secure boot key.
+              22
+              1
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE2
+              Set this bit to enable revoking third secure boot key.
+              23
+              1
+              read-only
+            
+            
+              KEY_PURPOSE_0
+              Purpose of Key0.
+              24
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_1
+              Purpose of Key1.
+              28
+              4
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_DATA2
+          BLOCK0 data register 3.
+          0x38
+          0x20
+          
+            
+              KEY_PURPOSE_2
+              Purpose of Key2.
+              0
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_3
+              Purpose of Key3.
+              4
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_4
+              Purpose of Key4.
+              8
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_5
+              Purpose of Key5.
+              12
+              4
+              read-only
+            
+            
+              RPT4_RESERVED3
+              Reserved (used for four backups method).
+              16
+              4
+              read-only
+            
+            
+              SECURE_BOOT_EN
+              Set this bit to enable secure boot.
+              20
+              1
+              read-only
+            
+            
+              SECURE_BOOT_AGGRESSIVE_REVOKE
+              Set this bit to enable revoking aggressive secure boot.
+              21
+              1
+              read-only
+            
+            
+              RPT4_RESERVED0
+              Reserved (used for four backups method).
+              22
+              6
+              read-only
+            
+            
+              FLASH_TPUW
+              Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.
+              28
+              4
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_DATA3
+          BLOCK0 data register 4.
+          0x3C
+          0x20
+          
+            
+              DIS_DOWNLOAD_MODE
+              Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
+              0
+              1
+              read-only
+            
+            
+              DIS_LEGACY_SPI_BOOT
+              Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).
+              1
+              1
+              read-only
+            
+            
+              UART_PRINT_CHANNEL
+              Selectes the default UART print channel. 0: UART0. 1: UART1.
+              2
+              1
+              read-only
+            
+            
+              FLASH_ECC_MODE
+              Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.
+              3
+              1
+              read-only
+            
+            
+              DIS_USB_DOWNLOAD_MODE
+              Set this bit to disable UART download mode through USB.
+              4
+              1
+              read-only
+            
+            
+              ENABLE_SECURITY_DOWNLOAD
+              Set this bit to enable secure UART download mode.
+              5
+              1
+              read-only
+            
+            
+              UART_PRINT_CONTROL
+              Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
+              6
+              2
+              read-only
+            
+            
+              PIN_POWER_SELECTION
+              GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
+              8
+              1
+              read-only
+            
+            
+              FLASH_TYPE
+              Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
+              9
+              1
+              read-only
+            
+            
+              FLASH_PAGE_SIZE
+              Set Flash page size.
+              10
+              2
+              read-only
+            
+            
+              FLASH_ECC_EN
+              Set 1 to enable ECC for flash boot.
+              12
+              1
+              read-only
+            
+            
+              FORCE_SEND_RESUME
+              Set this bit to force ROM code to send a resume command during SPI boot.
+              13
+              1
+              read-only
+            
+            
+              SECURE_VERSION
+              Secure version (used by ESP-IDF anti-rollback feature).
+              14
+              16
+              read-only
+            
+            
+              RPT4_RESERVED1
+              Reserved (used for four backups method).
+              30
+              2
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_DATA4
+          BLOCK0 data register 5.
+          0x40
+          0x20
+          
+            
+              RPT4_RESERVED4
+              Reserved (used for four backups method).
+              0
+              24
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_0
+          BLOCK1 data register 0.
+          0x44
+          0x20
+          
+            
+              MAC_0
+              Stores the low 32 bits of MAC address.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_1
+          BLOCK1 data register 1.
+          0x48
+          0x20
+          
+            
+              MAC_1
+              Stores the high 16 bits of MAC address.
+              0
+              16
+              read-only
+            
+            
+              SPI_PAD_CONF_0
+              Stores the zeroth part of SPI_PAD_CONF.
+              16
+              16
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_2
+          BLOCK1 data register 2.
+          0x4C
+          0x20
+          
+            
+              SPI_PAD_CONF_1
+              Stores the first part of SPI_PAD_CONF.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_3
+          BLOCK1 data register 3.
+          0x50
+          0x20
+          
+            
+              SPI_PAD_CONF_2
+              Stores the second part of SPI_PAD_CONF.
+              0
+              18
+              read-only
+            
+            
+              SYS_DATA_PART0_0
+              Stores the fist 14 bits of the zeroth part of system data.
+              18
+              14
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_4
+          BLOCK1 data register 4.
+          0x54
+          0x20
+          
+            
+              SYS_DATA_PART0_1
+              Stores the fist 32 bits of the zeroth part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_MAC_SPI_SYS_5
+          BLOCK1 data register 5.
+          0x58
+          0x20
+          
+            
+              SYS_DATA_PART0_2
+              Stores the second 32 bits of the zeroth part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA0
+          Register 0 of BLOCK2 (system).
+          0x5C
+          0x20
+          
+            
+              SYS_DATA_PART1_0
+              Stores the zeroth 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA1
+          Register 1 of BLOCK2 (system).
+          0x60
+          0x20
+          
+            
+              SYS_DATA_PART1_1
+              Stores the first 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA2
+          Register 2 of BLOCK2 (system).
+          0x64
+          0x20
+          
+            
+              SYS_DATA_PART1_2
+              Stores the second 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA3
+          Register 3 of BLOCK2 (system).
+          0x68
+          0x20
+          
+            
+              SYS_DATA_PART1_3
+              Stores the third 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA4
+          Register 4 of BLOCK2 (system).
+          0x6C
+          0x20
+          
+            
+              SYS_DATA_PART1_4
+              Stores the fourth 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA5
+          Register 5 of BLOCK2 (system).
+          0x70
+          0x20
+          
+            
+              SYS_DATA_PART1_5
+              Stores the fifth 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA6
+          Register 6 of BLOCK2 (system).
+          0x74
+          0x20
+          
+            
+              SYS_DATA_PART1_6
+              Stores the sixth 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART1_DATA7
+          Register 7 of BLOCK2 (system).
+          0x78
+          0x20
+          
+            
+              SYS_DATA_PART1_7
+              Stores the seventh 32 bits of the first part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA0
+          Register 0 of BLOCK3 (user).
+          0x7C
+          0x20
+          
+            
+              USR_DATA0
+              Stores the zeroth 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA1
+          Register 1 of BLOCK3 (user).
+          0x80
+          0x20
+          
+            
+              USR_DATA1
+              Stores the first 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA2
+          Register 2 of BLOCK3 (user).
+          0x84
+          0x20
+          
+            
+              USR_DATA2
+              Stores the second 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA3
+          Register 3 of BLOCK3 (user).
+          0x88
+          0x20
+          
+            
+              USR_DATA3
+              Stores the third 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA4
+          Register 4 of BLOCK3 (user).
+          0x8C
+          0x20
+          
+            
+              USR_DATA4
+              Stores the fourth 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA5
+          Register 5 of BLOCK3 (user).
+          0x90
+          0x20
+          
+            
+              USR_DATA5
+              Stores the fifth 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA6
+          Register 6 of BLOCK3 (user).
+          0x94
+          0x20
+          
+            
+              USR_DATA6
+              Stores the sixth 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_USR_DATA7
+          Register 7 of BLOCK3 (user).
+          0x98
+          0x20
+          
+            
+              USR_DATA7
+              Stores the seventh 32 bits of BLOCK3 (user).
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA0
+          Register 0 of BLOCK4 (KEY0).
+          0x9C
+          0x20
+          
+            
+              KEY0_DATA0
+              Stores the zeroth 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA1
+          Register 1 of BLOCK4 (KEY0).
+          0xA0
+          0x20
+          
+            
+              KEY0_DATA1
+              Stores the first 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA2
+          Register 2 of BLOCK4 (KEY0).
+          0xA4
+          0x20
+          
+            
+              KEY0_DATA2
+              Stores the second 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA3
+          Register 3 of BLOCK4 (KEY0).
+          0xA8
+          0x20
+          
+            
+              KEY0_DATA3
+              Stores the third 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA4
+          Register 4 of BLOCK4 (KEY0).
+          0xAC
+          0x20
+          
+            
+              KEY0_DATA4
+              Stores the fourth 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA5
+          Register 5 of BLOCK4 (KEY0).
+          0xB0
+          0x20
+          
+            
+              KEY0_DATA5
+              Stores the fifth 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA6
+          Register 6 of BLOCK4 (KEY0).
+          0xB4
+          0x20
+          
+            
+              KEY0_DATA6
+              Stores the sixth 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY0_DATA7
+          Register 7 of BLOCK4 (KEY0).
+          0xB8
+          0x20
+          
+            
+              KEY0_DATA7
+              Stores the seventh 32 bits of KEY0.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA0
+          Register 0 of BLOCK5 (KEY1).
+          0xBC
+          0x20
+          
+            
+              KEY1_DATA0
+              Stores the zeroth 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA1
+          Register 1 of BLOCK5 (KEY1).
+          0xC0
+          0x20
+          
+            
+              KEY1_DATA1
+              Stores the first 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA2
+          Register 2 of BLOCK5 (KEY1).
+          0xC4
+          0x20
+          
+            
+              KEY1_DATA2
+              Stores the second 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA3
+          Register 3 of BLOCK5 (KEY1).
+          0xC8
+          0x20
+          
+            
+              KEY1_DATA3
+              Stores the third 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA4
+          Register 4 of BLOCK5 (KEY1).
+          0xCC
+          0x20
+          
+            
+              KEY1_DATA4
+              Stores the fourth 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA5
+          Register 5 of BLOCK5 (KEY1).
+          0xD0
+          0x20
+          
+            
+              KEY1_DATA5
+              Stores the fifth 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA6
+          Register 6 of BLOCK5 (KEY1).
+          0xD4
+          0x20
+          
+            
+              KEY1_DATA6
+              Stores the sixth 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY1_DATA7
+          Register 7 of BLOCK5 (KEY1).
+          0xD8
+          0x20
+          
+            
+              KEY1_DATA7
+              Stores the seventh 32 bits of KEY1.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA0
+          Register 0 of BLOCK6 (KEY2).
+          0xDC
+          0x20
+          
+            
+              KEY2_DATA0
+              Stores the zeroth 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA1
+          Register 1 of BLOCK6 (KEY2).
+          0xE0
+          0x20
+          
+            
+              KEY2_DATA1
+              Stores the first 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA2
+          Register 2 of BLOCK6 (KEY2).
+          0xE4
+          0x20
+          
+            
+              KEY2_DATA2
+              Stores the second 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA3
+          Register 3 of BLOCK6 (KEY2).
+          0xE8
+          0x20
+          
+            
+              KEY2_DATA3
+              Stores the third 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA4
+          Register 4 of BLOCK6 (KEY2).
+          0xEC
+          0x20
+          
+            
+              KEY2_DATA4
+              Stores the fourth 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA5
+          Register 5 of BLOCK6 (KEY2).
+          0xF0
+          0x20
+          
+            
+              KEY2_DATA5
+              Stores the fifth 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA6
+          Register 6 of BLOCK6 (KEY2).
+          0xF4
+          0x20
+          
+            
+              KEY2_DATA6
+              Stores the sixth 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY2_DATA7
+          Register 7 of BLOCK6 (KEY2).
+          0xF8
+          0x20
+          
+            
+              KEY2_DATA7
+              Stores the seventh 32 bits of KEY2.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA0
+          Register 0 of BLOCK7 (KEY3).
+          0xFC
+          0x20
+          
+            
+              KEY3_DATA0
+              Stores the zeroth 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA1
+          Register 1 of BLOCK7 (KEY3).
+          0x100
+          0x20
+          
+            
+              KEY3_DATA1
+              Stores the first 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA2
+          Register 2 of BLOCK7 (KEY3).
+          0x104
+          0x20
+          
+            
+              KEY3_DATA2
+              Stores the second 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA3
+          Register 3 of BLOCK7 (KEY3).
+          0x108
+          0x20
+          
+            
+              KEY3_DATA3
+              Stores the third 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA4
+          Register 4 of BLOCK7 (KEY3).
+          0x10C
+          0x20
+          
+            
+              KEY3_DATA4
+              Stores the fourth 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA5
+          Register 5 of BLOCK7 (KEY3).
+          0x110
+          0x20
+          
+            
+              KEY3_DATA5
+              Stores the fifth 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA6
+          Register 6 of BLOCK7 (KEY3).
+          0x114
+          0x20
+          
+            
+              KEY3_DATA6
+              Stores the sixth 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY3_DATA7
+          Register 7 of BLOCK7 (KEY3).
+          0x118
+          0x20
+          
+            
+              KEY3_DATA7
+              Stores the seventh 32 bits of KEY3.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA0
+          Register 0 of BLOCK8 (KEY4).
+          0x11C
+          0x20
+          
+            
+              KEY4_DATA0
+              Stores the zeroth 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA1
+          Register 1 of BLOCK8 (KEY4).
+          0x120
+          0x20
+          
+            
+              KEY4_DATA1
+              Stores the first 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA2
+          Register 2 of BLOCK8 (KEY4).
+          0x124
+          0x20
+          
+            
+              KEY4_DATA2
+              Stores the second 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA3
+          Register 3 of BLOCK8 (KEY4).
+          0x128
+          0x20
+          
+            
+              KEY4_DATA3
+              Stores the third 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA4
+          Register 4 of BLOCK8 (KEY4).
+          0x12C
+          0x20
+          
+            
+              KEY4_DATA4
+              Stores the fourth 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA5
+          Register 5 of BLOCK8 (KEY4).
+          0x130
+          0x20
+          
+            
+              KEY4_DATA5
+              Stores the fifth 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA6
+          Register 6 of BLOCK8 (KEY4).
+          0x134
+          0x20
+          
+            
+              KEY4_DATA6
+              Stores the sixth 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY4_DATA7
+          Register 7 of BLOCK8 (KEY4).
+          0x138
+          0x20
+          
+            
+              KEY4_DATA7
+              Stores the seventh 32 bits of KEY4.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA0
+          Register 0 of BLOCK9 (KEY5).
+          0x13C
+          0x20
+          
+            
+              KEY5_DATA0
+              Stores the zeroth 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA1
+          Register 1 of BLOCK9 (KEY5).
+          0x140
+          0x20
+          
+            
+              KEY5_DATA1
+              Stores the first 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA2
+          Register 2 of BLOCK9 (KEY5).
+          0x144
+          0x20
+          
+            
+              KEY5_DATA2
+              Stores the second 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA3
+          Register 3 of BLOCK9 (KEY5).
+          0x148
+          0x20
+          
+            
+              KEY5_DATA3
+              Stores the third 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA4
+          Register 4 of BLOCK9 (KEY5).
+          0x14C
+          0x20
+          
+            
+              KEY5_DATA4
+              Stores the fourth 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA5
+          Register 5 of BLOCK9 (KEY5).
+          0x150
+          0x20
+          
+            
+              KEY5_DATA5
+              Stores the fifth 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA6
+          Register 6 of BLOCK9 (KEY5).
+          0x154
+          0x20
+          
+            
+              KEY5_DATA6
+              Stores the sixth 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_KEY5_DATA7
+          Register 7 of BLOCK9 (KEY5).
+          0x158
+          0x20
+          
+            
+              KEY5_DATA7
+              Stores the seventh 32 bits of KEY5.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA0
+          Register 0 of BLOCK10 (system).
+          0x15C
+          0x20
+          
+            
+              SYS_DATA_PART2_0
+              Stores the 0th 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA1
+          Register 1 of BLOCK9 (KEY5).
+          0x160
+          0x20
+          
+            
+              SYS_DATA_PART2_1
+              Stores the 1st 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA2
+          Register 2 of BLOCK10 (system).
+          0x164
+          0x20
+          
+            
+              SYS_DATA_PART2_2
+              Stores the 2nd 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA3
+          Register 3 of BLOCK10 (system).
+          0x168
+          0x20
+          
+            
+              SYS_DATA_PART2_3
+              Stores the 3rd 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA4
+          Register 4 of BLOCK10 (system).
+          0x16C
+          0x20
+          
+            
+              SYS_DATA_PART2_4
+              Stores the 4th 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA5
+          Register 5 of BLOCK10 (system).
+          0x170
+          0x20
+          
+            
+              SYS_DATA_PART2_5
+              Stores the 5th 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA6
+          Register 6 of BLOCK10 (system).
+          0x174
+          0x20
+          
+            
+              SYS_DATA_PART2_6
+              Stores the 6th 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_SYS_PART2_DATA7
+          Register 7 of BLOCK10 (system).
+          0x178
+          0x20
+          
+            
+              SYS_DATA_PART2_7
+              Stores the 7th 32 bits of the 2nd part of system data.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_ERR0
+          Programming error record register 0 of BLOCK0.
+          0x17C
+          0x20
+          
+            
+              RD_DIS_ERR
+              If any bit in RD_DIS is 1, then it indicates a programming error.
+              0
+              7
+              read-only
+            
+            
+              DIS_RTC_RAM_BOOT_ERR
+              If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
+              7
+              1
+              read-only
+            
+            
+              DIS_ICACHE_ERR
+              If DIS_ICACHE is 1, then it indicates a programming error.
+              8
+              1
+              read-only
+            
+            
+              DIS_USB_JTAG_ERR
+              If DIS_USB_JTAG is 1, then it indicates a programming error.
+              9
+              1
+              read-only
+            
+            
+              DIS_DOWNLOAD_ICACHE_ERR
+              If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
+              10
+              1
+              read-only
+            
+            
+              DIS_USB_DEVICE_ERR
+              If DIS_USB_DEVICE is 1, then it indicates a programming error.
+              11
+              1
+              read-only
+            
+            
+              DIS_FORCE_DOWNLOAD_ERR
+              If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
+              12
+              1
+              read-only
+            
+            
+              RPT4_RESERVED6_ERR
+              Reserved.
+              13
+              1
+              read-only
+            
+            
+              DIS_CAN_ERR
+              If DIS_CAN is 1, then it indicates a programming error.
+              14
+              1
+              read-only
+            
+            
+              JTAG_SEL_ENABLE_ERR
+              If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
+              15
+              1
+              read-only
+            
+            
+              SOFT_DIS_JTAG_ERR
+              If SOFT_DIS_JTAG is 1, then it indicates a programming error.
+              16
+              3
+              read-only
+            
+            
+              DIS_PAD_JTAG_ERR
+              If DIS_PAD_JTAG is 1, then it indicates a programming error.
+              19
+              1
+              read-only
+            
+            
+              DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR
+              If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
+              20
+              1
+              read-only
+            
+            
+              USB_DREFH_ERR
+              If any bit in USB_DREFH is 1, then it indicates a programming error.
+              21
+              2
+              read-only
+            
+            
+              USB_DREFL_ERR
+              If any bit in USB_DREFL is 1, then it indicates a programming error.
+              23
+              2
+              read-only
+            
+            
+              USB_EXCHG_PINS_ERR
+              If USB_EXCHG_PINS is 1, then it indicates a programming error.
+              25
+              1
+              read-only
+            
+            
+              VDD_SPI_AS_GPIO_ERR
+              If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
+              26
+              1
+              read-only
+            
+            
+              BTLC_GPIO_ENABLE_ERR
+              If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
+              27
+              2
+              read-only
+            
+            
+              POWERGLITCH_EN_ERR
+              If POWERGLITCH_EN is 1, then it indicates a programming error.
+              29
+              1
+              read-only
+            
+            
+              POWER_GLITCH_DSENSE_ERR
+              If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
+              30
+              2
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_ERR1
+          Programming error record register 1 of BLOCK0.
+          0x180
+          0x20
+          
+            
+              RPT4_RESERVED2_ERR
+              Reserved.
+              0
+              16
+              read-only
+            
+            
+              WDT_DELAY_SEL_ERR
+              If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+              16
+              2
+              read-only
+            
+            
+              SPI_BOOT_CRYPT_CNT_ERR
+              If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
+              18
+              3
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE0_ERR
+              If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
+              21
+              1
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE1_ERR
+              If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
+              22
+              1
+              read-only
+            
+            
+              SECURE_BOOT_KEY_REVOKE2_ERR
+              If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
+              23
+              1
+              read-only
+            
+            
+              KEY_PURPOSE_0_ERR
+              If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
+              24
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_1_ERR
+              If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
+              28
+              4
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_ERR2
+          Programming error record register 2 of BLOCK0.
+          0x184
+          0x20
+          
+            
+              KEY_PURPOSE_2_ERR
+              If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
+              0
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_3_ERR
+              If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
+              4
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_4_ERR
+              If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
+              8
+              4
+              read-only
+            
+            
+              KEY_PURPOSE_5_ERR
+              If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
+              12
+              4
+              read-only
+            
+            
+              RPT4_RESERVED3_ERR
+              Reserved.
+              16
+              4
+              read-only
+            
+            
+              SECURE_BOOT_EN_ERR
+              If SECURE_BOOT_EN is 1, then it indicates a programming error.
+              20
+              1
+              read-only
+            
+            
+              SECURE_BOOT_AGGRESSIVE_REVOKE_ERR
+              If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
+              21
+              1
+              read-only
+            
+            
+              RPT4_RESERVED0_ERR
+              Reserved.
+              22
+              6
+              read-only
+            
+            
+              FLASH_TPUW_ERR
+              If any bit in FLASH_TPUM is 1, then it indicates a programming error.
+              28
+              4
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_ERR3
+          Programming error record register 3 of BLOCK0.
+          0x188
+          0x20
+          
+            
+              DIS_DOWNLOAD_MODE_ERR
+              If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
+              0
+              1
+              read-only
+            
+            
+              DIS_LEGACY_SPI_BOOT_ERR
+              If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
+              1
+              1
+              read-only
+            
+            
+              UART_PRINT_CHANNEL_ERR
+              If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
+              2
+              1
+              read-only
+            
+            
+              FLASH_ECC_MODE_ERR
+              If FLASH_ECC_MODE is 1, then it indicates a programming error.
+              3
+              1
+              read-only
+            
+            
+              DIS_USB_DOWNLOAD_MODE_ERR
+              If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
+              4
+              1
+              read-only
+            
+            
+              ENABLE_SECURITY_DOWNLOAD_ERR
+              If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
+              5
+              1
+              read-only
+            
+            
+              UART_PRINT_CONTROL_ERR
+              If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+              6
+              2
+              read-only
+            
+            
+              PIN_POWER_SELECTION_ERR
+              If PIN_POWER_SELECTION is 1, then it indicates a programming error.
+              8
+              1
+              read-only
+            
+            
+              FLASH_TYPE_ERR
+              If FLASH_TYPE is 1, then it indicates a programming error.
+              9
+              1
+              read-only
+            
+            
+              FLASH_PAGE_SIZE_ERR
+              If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
+              10
+              2
+              read-only
+            
+            
+              FLASH_ECC_EN_ERR
+              If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
+              12
+              1
+              read-only
+            
+            
+              FORCE_SEND_RESUME_ERR
+              If FORCE_SEND_RESUME is 1, then it indicates a programming error.
+              13
+              1
+              read-only
+            
+            
+              SECURE_VERSION_ERR
+              If any bit in SECURE_VERSION is 1, then it indicates a programming error.
+              14
+              16
+              read-only
+            
+            
+              RPT4_RESERVED1_ERR
+              Reserved.
+              30
+              2
+              read-only
+            
+          
+        
+        
+          RD_REPEAT_ERR4
+          Programming error record register 4 of BLOCK0.
+          0x190
+          0x20
+          
+            
+              RPT4_RESERVED4_ERR
+              Reserved.
+              0
+              24
+              read-only
+            
+          
+        
+        
+          RD_RS_ERR0
+          Programming error record register 0 of BLOCK1-10.
+          0x1C0
+          0x20
+          
+            
+              MAC_SPI_8M_ERR_NUM
+              The value of this signal means the number of error bytes.
+              0
+              3
+              read-only
+            
+            
+              MAC_SPI_8M_FAIL
+              0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+              3
+              1
+              read-only
+            
+            
+              SYS_PART1_NUM
+              The value of this signal means the number of error bytes.
+              4
+              3
+              read-only
+            
+            
+              SYS_PART1_FAIL
+              0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+              7
+              1
+              read-only
+            
+            
+              USR_DATA_ERR_NUM
+              The value of this signal means the number of error bytes.
+              8
+              3
+              read-only
+            
+            
+              USR_DATA_FAIL
+              0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+              11
+              1
+              read-only
+            
+            
+              KEY0_ERR_NUM
+              The value of this signal means the number of error bytes.
+              12
+              3
+              read-only
+            
+            
+              KEY0_FAIL
+              0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.
+              15
+              1
+              read-only
+            
+            
+              KEY1_ERR_NUM
+              The value of this signal means the number of error bytes.
+              16
+              3
+              read-only
+            
+            
+              KEY1_FAIL
+              0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.
+              19
+              1
+              read-only
+            
+            
+              KEY2_ERR_NUM
+              The value of this signal means the number of error bytes.
+              20
+              3
+              read-only
+            
+            
+              KEY2_FAIL
+              0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.
+              23
+              1
+              read-only
+            
+            
+              KEY3_ERR_NUM
+              The value of this signal means the number of error bytes.
+              24
+              3
+              read-only
+            
+            
+              KEY3_FAIL
+              0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.
+              27
+              1
+              read-only
+            
+            
+              KEY4_ERR_NUM
+              The value of this signal means the number of error bytes.
+              28
+              3
+              read-only
+            
+            
+              KEY4_FAIL
+              0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.
+              31
+              1
+              read-only
+            
+          
+        
+        
+          RD_RS_ERR1
+          Programming error record register 1 of BLOCK1-10.
+          0x1C4
+          0x20
+          
+            
+              KEY5_ERR_NUM
+              The value of this signal means the number of error bytes.
+              0
+              3
+              read-only
+            
+            
+              KEY5_FAIL
+              0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+              3
+              1
+              read-only
+            
+            
+              SYS_PART2_ERR_NUM
+              The value of this signal means the number of error bytes.
+              4
+              3
+              read-only
+            
+            
+              SYS_PART2_FAIL
+              0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+              7
+              1
+              read-only
+            
+          
+        
+        
+          CLK
+          eFuse clcok configuration register.
+          0x1C8
+          0x20
+          0x00000002
+          
+            
+              EFUSE_MEM_FORCE_PD
+              Set this bit to force eFuse SRAM into power-saving mode.
+              0
+              1
+              read-write
+            
+            
+              MEM_CLK_FORCE_ON
+              Set this bit and force to activate clock signal of eFuse SRAM.
+              1
+              1
+              read-write
+            
+            
+              EFUSE_MEM_FORCE_PU
+              Set this bit to force eFuse SRAM into working mode.
+              2
+              1
+              read-write
+            
+            
+              EN
+              Set this bit and force to enable clock signal of eFuse memory.
+              16
+              1
+              read-write
+            
+          
+        
+        
+          CONF
+          eFuse operation mode configuraiton register;
+          0x1CC
+          0x20
+          
+            
+              OP_CODE
+              0x5A5A: Operate programming command 0x5AA5: Operate read command.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          STATUS
+          eFuse status register.
+          0x1D0
+          0x20
+          
+            
+              STATE
+              Indicates the state of the eFuse state machine.
+              0
+              4
+              read-only
+            
+            
+              OTP_LOAD_SW
+              The value of OTP_LOAD_SW.
+              4
+              1
+              read-only
+            
+            
+              OTP_VDDQ_C_SYNC2
+              The value of OTP_VDDQ_C_SYNC2.
+              5
+              1
+              read-only
+            
+            
+              OTP_STROBE_SW
+              The value of OTP_STROBE_SW.
+              6
+              1
+              read-only
+            
+            
+              OTP_CSB_SW
+              The value of OTP_CSB_SW.
+              7
+              1
+              read-only
+            
+            
+              OTP_PGENB_SW
+              The value of OTP_PGENB_SW.
+              8
+              1
+              read-only
+            
+            
+              OTP_VDDQ_IS_SW
+              The value of OTP_VDDQ_IS_SW.
+              9
+              1
+              read-only
+            
+            
+              REPEAT_ERR_CNT
+              Indicates the number of error bits during programming BLOCK0.
+              10
+              8
+              read-only
+            
+          
+        
+        
+          CMD
+          eFuse command register.
+          0x1D4
+          0x20
+          
+            
+              READ_CMD
+              Set this bit to send read command.
+              0
+              1
+              read-write
+            
+            
+              PGM_CMD
+              Set this bit to send programming command.
+              1
+              1
+              read-write
+            
+            
+              BLK_NUM
+              The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.
+              2
+              4
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          eFuse raw interrupt register.
+          0x1D8
+          0x20
+          
+            
+              READ_DONE_INT_RAW
+              The raw bit signal for read_done interrupt.
+              0
+              1
+              read-write
+            
+            
+              PGM_DONE_INT_RAW
+              The raw bit signal for pgm_done interrupt.
+              1
+              1
+              read-write
+            
+          
+        
+        
+          INT_ST
+          eFuse interrupt status register.
+          0x1DC
+          0x20
+          
+            
+              READ_DONE_INT_ST
+              The status signal for read_done interrupt.
+              0
+              1
+              read-only
+            
+            
+              PGM_DONE_INT_ST
+              The status signal for pgm_done interrupt.
+              1
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          eFuse interrupt enable register.
+          0x1E0
+          0x20
+          
+            
+              READ_DONE_INT_ENA
+              The enable signal for read_done interrupt.
+              0
+              1
+              read-write
+            
+            
+              PGM_DONE_INT_ENA
+              The enable signal for pgm_done interrupt.
+              1
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          eFuse interrupt clear register.
+          0x1E4
+          0x20
+          
+            
+              READ_DONE_INT_CLR
+              The clear signal for read_done interrupt.
+              0
+              1
+              write-only
+            
+            
+              PGM_DONE_INT_CLR
+              The clear signal for pgm_done interrupt.
+              1
+              1
+              write-only
+            
+          
+        
+        
+          DAC_CONF
+          Controls the eFuse programming voltage.
+          0x1E8
+          0x20
+          0x0001FE1C
+          
+            
+              DAC_CLK_DIV
+              Controls the division factor of the rising clock of the programming voltage.
+              0
+              8
+              read-write
+            
+            
+              DAC_CLK_PAD_SEL
+              Don't care.
+              8
+              1
+              read-write
+            
+            
+              DAC_NUM
+              Controls the rising period of the programming voltage.
+              9
+              8
+              read-write
+            
+            
+              OE_CLR
+              Reduces the power supply of the programming voltage.
+              17
+              1
+              read-write
+            
+          
+        
+        
+          RD_TIM_CONF
+          Configures read timing parameters.
+          0x1EC
+          0x20
+          0x12000000
+          
+            
+              READ_INIT_NUM
+              Configures the initial read time of eFuse.
+              24
+              8
+              read-write
+            
+          
+        
+        
+          WR_TIM_CONF1
+          Configurarion register 1 of eFuse programming timing parameters.
+          0x1F0
+          0x20
+          0x00288000
+          
+            
+              PWR_ON_NUM
+              Configures the power up time for VDDQ.
+              8
+              16
+              read-write
+            
+          
+        
+        
+          WR_TIM_CONF2
+          Configurarion register 2 of eFuse programming timing parameters.
+          0x1F4
+          0x20
+          0x00000190
+          
+            
+              PWR_OFF_NUM
+              Configures the power outage time for VDDQ.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          DATE
+          eFuse version register.
+          0x1FC
+          0x20
+          0x02007200
+          
+            
+              DATE
+              Stores eFuse version.
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      EXTMEM
+      External Memory
+      EXTMEM
+      0x600C4000
+      
+        0x0
+        0x108
+        registers
+      
+      
+        
+          ICACHE_CTRL
+          This description will be updated in the near future.
+          0x0
+          0x20
+          
+            
+              ICACHE_ENABLE
+              The bit is used to activate the data cache. 0: disable, 1: enable
+              0
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_CTRL1
+          This description will be updated in the near future.
+          0x4
+          0x20
+          0x00000003
+          
+            
+              ICACHE_SHUT_IBUS
+              The bit is used to disable core0 ibus, 0: enable, 1: disable
+              0
+              1
+              read-write
+            
+            
+              ICACHE_SHUT_DBUS
+              The bit is used to disable core1 ibus, 0: enable, 1: disable
+              1
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_TAG_POWER_CTRL
+          This description will be updated in the near future.
+          0x8
+          0x20
+          0x00000005
+          
+            
+              ICACHE_TAG_MEM_FORCE_ON
+              The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_TAG_MEM_FORCE_PD
+              The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down
+              1
+              1
+              read-write
+            
+            
+              ICACHE_TAG_MEM_FORCE_PU
+              The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up
+              2
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOCK_CTRL
+          This description will be updated in the near future.
+          0xC
+          0x20
+          
+            
+              ICACHE_PRELOCK_SCT0_EN
+              The bit is used to enable the first section of prelock function.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_PRELOCK_SCT1_EN
+              The bit is used to enable the second section of prelock function.
+              1
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOCK_SCT0_ADDR
+          This description will be updated in the near future.
+          0x10
+          0x20
+          
+            
+              ICACHE_PRELOCK_SCT0_ADDR
+              The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOCK_SCT1_ADDR
+          This description will be updated in the near future.
+          0x14
+          0x20
+          
+            
+              ICACHE_PRELOCK_SCT1_ADDR
+              The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOCK_SCT_SIZE
+          This description will be updated in the near future.
+          0x18
+          0x20
+          
+            
+              ICACHE_PRELOCK_SCT1_SIZE
+              The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG
+              0
+              16
+              read-write
+            
+            
+              ICACHE_PRELOCK_SCT0_SIZE
+              The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG
+              16
+              16
+              read-write
+            
+          
+        
+        
+          ICACHE_LOCK_CTRL
+          This description will be updated in the near future.
+          0x1C
+          0x20
+          0x00000004
+          
+            
+              ICACHE_LOCK_ENA
+              The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_UNLOCK_ENA
+              The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.
+              1
+              1
+              read-write
+            
+            
+              ICACHE_LOCK_DONE
+              The bit is used to indicate unlock/lock operation is finished.
+              2
+              1
+              read-only
+            
+          
+        
+        
+          ICACHE_LOCK_ADDR
+          This description will be updated in the near future.
+          0x20
+          0x20
+          
+            
+              ICACHE_LOCK_ADDR
+              The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_LOCK_SIZE
+          This description will be updated in the near future.
+          0x24
+          0x20
+          
+            
+              ICACHE_LOCK_SIZE
+              The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          ICACHE_SYNC_CTRL
+          This description will be updated in the near future.
+          0x28
+          0x20
+          0x00000001
+          
+            
+              ICACHE_INVALIDATE_ENA
+              The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_SYNC_DONE
+              The bit is used to indicate invalidate operation is finished.
+              1
+              1
+              read-only
+            
+          
+        
+        
+          ICACHE_SYNC_ADDR
+          This description will be updated in the near future.
+          0x2C
+          0x20
+          
+            
+              ICACHE_SYNC_ADDR
+              The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_SYNC_SIZE
+          This description will be updated in the near future.
+          0x30
+          0x20
+          
+            
+              ICACHE_SYNC_SIZE
+              The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.
+              0
+              23
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOAD_CTRL
+          This description will be updated in the near future.
+          0x34
+          0x20
+          0x00000002
+          
+            
+              ICACHE_PRELOAD_ENA
+              The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_PRELOAD_DONE
+              The bit is used to indicate preload operation is finished.
+              1
+              1
+              read-only
+            
+            
+              ICACHE_PRELOAD_ORDER
+              The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.
+              2
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOAD_ADDR
+          This description will be updated in the near future.
+          0x38
+          0x20
+          
+            
+              ICACHE_PRELOAD_ADDR
+              The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOAD_SIZE
+          This description will be updated in the near future.
+          0x3C
+          0x20
+          
+            
+              ICACHE_PRELOAD_SIZE
+              The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..
+              0
+              16
+              read-write
+            
+          
+        
+        
+          ICACHE_AUTOLOAD_CTRL
+          This description will be updated in the near future.
+          0x40
+          0x20
+          0x00000008
+          
+            
+              ICACHE_AUTOLOAD_SCT0_ENA
+              The bits are used to enable the first section for autoload operation.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_AUTOLOAD_SCT1_ENA
+              The bits are used to enable the second section for autoload operation.
+              1
+              1
+              read-write
+            
+            
+              ICACHE_AUTOLOAD_ENA
+              The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.
+              2
+              1
+              read-write
+            
+            
+              ICACHE_AUTOLOAD_DONE
+              The bit is used to indicate autoload operation is finished.
+              3
+              1
+              read-only
+            
+            
+              ICACHE_AUTOLOAD_ORDER
+              The bits are used to configure the direction of autoload. 1: descending, 0: ascending.
+              4
+              1
+              read-write
+            
+            
+              ICACHE_AUTOLOAD_RQST
+              The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
+              5
+              2
+              read-write
+            
+          
+        
+        
+          ICACHE_AUTOLOAD_SCT0_ADDR
+          This description will be updated in the near future.
+          0x44
+          0x20
+          
+            
+              ICACHE_AUTOLOAD_SCT0_ADDR
+              The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_AUTOLOAD_SCT0_SIZE
+          This description will be updated in the near future.
+          0x48
+          0x20
+          
+            
+              ICACHE_AUTOLOAD_SCT0_SIZE
+              The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
+              0
+              27
+              read-write
+            
+          
+        
+        
+          ICACHE_AUTOLOAD_SCT1_ADDR
+          This description will be updated in the near future.
+          0x4C
+          0x20
+          
+            
+              ICACHE_AUTOLOAD_SCT1_ADDR
+              The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ICACHE_AUTOLOAD_SCT1_SIZE
+          This description will be updated in the near future.
+          0x50
+          0x20
+          
+            
+              ICACHE_AUTOLOAD_SCT1_SIZE
+              The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
+              0
+              27
+              read-write
+            
+          
+        
+        
+          IBUS_TO_FLASH_START_VADDR
+          This description will be updated in the near future.
+          0x54
+          0x20
+          0x42000000
+          
+            
+              IBUS_TO_FLASH_START_VADDR
+              The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          IBUS_TO_FLASH_END_VADDR
+          This description will be updated in the near future.
+          0x58
+          0x20
+          0x427FFFFF
+          
+            
+              IBUS_TO_FLASH_END_VADDR
+              The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          DBUS_TO_FLASH_START_VADDR
+          This description will be updated in the near future.
+          0x5C
+          0x20
+          0x3C000000
+          
+            
+              DBUS_TO_FLASH_START_VADDR
+              The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          DBUS_TO_FLASH_END_VADDR
+          This description will be updated in the near future.
+          0x60
+          0x20
+          0x3C7FFFFF
+          
+            
+              DBUS_TO_FLASH_END_VADDR
+              The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CACHE_ACS_CNT_CLR
+          This description will be updated in the near future.
+          0x64
+          0x20
+          
+            
+              IBUS_ACS_CNT_CLR
+              The bit is used to clear ibus counter.
+              0
+              1
+              write-only
+            
+            
+              DBUS_ACS_CNT_CLR
+              The bit is used to clear dbus counter.
+              1
+              1
+              write-only
+            
+          
+        
+        
+          IBUS_ACS_MISS_CNT
+          This description will be updated in the near future.
+          0x68
+          0x20
+          
+            
+              IBUS_ACS_MISS_CNT
+              The bits are used to count the number of the cache miss caused by ibus access flash.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          IBUS_ACS_CNT
+          This description will be updated in the near future.
+          0x6C
+          0x20
+          
+            
+              IBUS_ACS_CNT
+              The bits are used to count the number of ibus access flash through icache.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          DBUS_ACS_FLASH_MISS_CNT
+          This description will be updated in the near future.
+          0x70
+          0x20
+          
+            
+              DBUS_ACS_FLASH_MISS_CNT
+              The bits are used to count the number of the cache miss caused by dbus access flash.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          DBUS_ACS_CNT
+          This description will be updated in the near future.
+          0x74
+          0x20
+          
+            
+              DBUS_ACS_CNT
+              The bits are used to count the number of dbus access flash through icache.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CACHE_ILG_INT_ENA
+          This description will be updated in the near future.
+          0x78
+          0x20
+          
+            
+              ICACHE_SYNC_OP_FAULT_INT_ENA
+              The bit is used to enable interrupt by sync configurations fault.
+              0
+              1
+              read-write
+            
+            
+              ICACHE_PRELOAD_OP_FAULT_INT_ENA
+              The bit is used to enable interrupt by preload configurations fault.
+              1
+              1
+              read-write
+            
+            
+              MMU_ENTRY_FAULT_INT_ENA
+              The bit is used to enable interrupt by mmu entry fault.
+              5
+              1
+              read-write
+            
+            
+              IBUS_CNT_OVF_INT_ENA
+              The bit is used to enable interrupt by ibus counter overflow.
+              7
+              1
+              read-write
+            
+            
+              DBUS_CNT_OVF_INT_ENA
+              The bit is used to enable interrupt by dbus counter overflow.
+              8
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_ILG_INT_CLR
+          This description will be updated in the near future.
+          0x7C
+          0x20
+          
+            
+              ICACHE_SYNC_OP_FAULT_INT_CLR
+              The bit is used to clear interrupt by sync configurations fault.
+              0
+              1
+              write-only
+            
+            
+              ICACHE_PRELOAD_OP_FAULT_INT_CLR
+              The bit is used to clear interrupt by preload configurations fault.
+              1
+              1
+              write-only
+            
+            
+              MMU_ENTRY_FAULT_INT_CLR
+              The bit is used to clear interrupt by mmu entry fault.
+              5
+              1
+              write-only
+            
+            
+              IBUS_CNT_OVF_INT_CLR
+              The bit is used to clear interrupt by ibus counter overflow.
+              7
+              1
+              write-only
+            
+            
+              DBUS_CNT_OVF_INT_CLR
+              The bit is used to clear interrupt by dbus counter overflow.
+              8
+              1
+              write-only
+            
+          
+        
+        
+          CACHE_ILG_INT_ST
+          This description will be updated in the near future.
+          0x80
+          0x20
+          
+            
+              ICACHE_SYNC_OP_FAULT_ST
+              The bit is used to indicate interrupt by sync configurations fault.
+              0
+              1
+              read-only
+            
+            
+              ICACHE_PRELOAD_OP_FAULT_ST
+              The bit is used to indicate interrupt by preload configurations fault.
+              1
+              1
+              read-only
+            
+            
+              MMU_ENTRY_FAULT_ST
+              The bit is used to indicate interrupt by mmu entry fault.
+              5
+              1
+              read-only
+            
+            
+              IBUS_ACS_CNT_OVF_ST
+              The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.
+              7
+              1
+              read-only
+            
+            
+              IBUS_ACS_MISS_CNT_OVF_ST
+              The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.
+              8
+              1
+              read-only
+            
+            
+              DBUS_ACS_CNT_OVF_ST
+              The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.
+              9
+              1
+              read-only
+            
+            
+              DBUS_ACS_FLASH_MISS_CNT_OVF_ST
+              The bit is used to indicate interrupt by dbus access flash miss counter overflow.
+              10
+              1
+              read-only
+            
+          
+        
+        
+          CORE0_ACS_CACHE_INT_ENA
+          This description will be updated in the near future.
+          0x84
+          0x20
+          
+            
+              CORE0_IBUS_ACS_MSK_IC_INT_ENA
+              The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.
+              0
+              1
+              read-write
+            
+            
+              CORE0_IBUS_WR_IC_INT_ENA
+              The bit is used to enable interrupt by ibus trying to write icache
+              1
+              1
+              read-write
+            
+            
+              CORE0_IBUS_REJECT_INT_ENA
+              The bit is used to enable interrupt by authentication fail.
+              2
+              1
+              read-write
+            
+            
+              CORE0_DBUS_ACS_MSK_IC_INT_ENA
+              The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.
+              3
+              1
+              read-write
+            
+            
+              CORE0_DBUS_REJECT_INT_ENA
+              The bit is used to enable interrupt by authentication fail.
+              4
+              1
+              read-write
+            
+            
+              CORE0_DBUS_WR_IC_INT_ENA
+              The bit is used to enable interrupt by dbus trying to write icache
+              5
+              1
+              read-write
+            
+          
+        
+        
+          CORE0_ACS_CACHE_INT_CLR
+          This description will be updated in the near future.
+          0x88
+          0x20
+          
+            
+              CORE0_IBUS_ACS_MSK_IC_INT_CLR
+              The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.
+              0
+              1
+              write-only
+            
+            
+              CORE0_IBUS_WR_IC_INT_CLR
+              The bit is used to clear interrupt by ibus trying to write icache
+              1
+              1
+              write-only
+            
+            
+              CORE0_IBUS_REJECT_INT_CLR
+              The bit is used to clear interrupt by authentication fail.
+              2
+              1
+              write-only
+            
+            
+              CORE0_DBUS_ACS_MSK_IC_INT_CLR
+              The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.
+              3
+              1
+              write-only
+            
+            
+              CORE0_DBUS_REJECT_INT_CLR
+              The bit is used to clear interrupt by authentication fail.
+              4
+              1
+              write-only
+            
+            
+              CORE0_DBUS_WR_IC_INT_CLR
+              The bit is used to clear interrupt by dbus trying to write icache
+              5
+              1
+              write-only
+            
+          
+        
+        
+          CORE0_ACS_CACHE_INT_ST
+          This description will be updated in the near future.
+          0x8C
+          0x20
+          
+            
+              CORE0_IBUS_ACS_MSK_ICACHE_ST
+              The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.
+              0
+              1
+              read-only
+            
+            
+              CORE0_IBUS_WR_ICACHE_ST
+              The bit is used to indicate interrupt by ibus trying to write icache
+              1
+              1
+              read-only
+            
+            
+              CORE0_IBUS_REJECT_ST
+              The bit is used to indicate interrupt by authentication fail.
+              2
+              1
+              read-only
+            
+            
+              CORE0_DBUS_ACS_MSK_ICACHE_ST
+              The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.
+              3
+              1
+              read-only
+            
+            
+              CORE0_DBUS_REJECT_ST
+              The bit is used to indicate interrupt by authentication fail.
+              4
+              1
+              read-only
+            
+            
+              CORE0_DBUS_WR_ICACHE_ST
+              The bit is used to indicate interrupt by dbus trying to write icache
+              5
+              1
+              read-only
+            
+          
+        
+        
+          CORE0_DBUS_REJECT_ST
+          This description will be updated in the near future.
+          0x90
+          0x20
+          
+            
+              CORE0_DBUS_ATTR
+              The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.
+              0
+              3
+              read-only
+            
+            
+              CORE0_DBUS_WORLD
+              The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1
+              3
+              1
+              read-only
+            
+          
+        
+        
+          CORE0_DBUS_REJECT_VADDR
+          This description will be updated in the near future.
+          0x94
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE0_DBUS_VADDR
+              The bits are used to indicate the virtual address of CPU access dbus when authentication fail.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE0_IBUS_REJECT_ST
+          This description will be updated in the near future.
+          0x98
+          0x20
+          
+            
+              CORE0_IBUS_ATTR
+              The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able
+              0
+              3
+              read-only
+            
+            
+              CORE0_IBUS_WORLD
+              The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1
+              3
+              1
+              read-only
+            
+          
+        
+        
+          CORE0_IBUS_REJECT_VADDR
+          This description will be updated in the near future.
+          0x9C
+          0x20
+          0xFFFFFFFF
+          
+            
+              CORE0_IBUS_VADDR
+              The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CACHE_MMU_FAULT_CONTENT
+          This description will be updated in the near future.
+          0xA0
+          0x20
+          
+            
+              CACHE_MMU_FAULT_CONTENT
+              The bits are used to indicate the content of mmu entry which cause mmu fault..
+              0
+              10
+              read-only
+            
+            
+              CACHE_MMU_FAULT_CODE
+              The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.
+              10
+              4
+              read-only
+            
+          
+        
+        
+          CACHE_MMU_FAULT_VADDR
+          This description will be updated in the near future.
+          0xA4
+          0x20
+          
+            
+              CACHE_MMU_FAULT_VADDR
+              The bits are used to indicate the virtual address which cause mmu fault..
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CACHE_WRAP_AROUND_CTRL
+          This description will be updated in the near future.
+          0xA8
+          0x20
+          
+            
+              CACHE_FLASH_WRAP_AROUND
+              The bit is used to enable wrap around mode when read data from flash.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_MMU_POWER_CTRL
+          This description will be updated in the near future.
+          0xAC
+          0x20
+          0x00000005
+          
+            
+              CACHE_MMU_MEM_FORCE_ON
+              The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable
+              0
+              1
+              read-write
+            
+            
+              CACHE_MMU_MEM_FORCE_PD
+              The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down
+              1
+              1
+              read-write
+            
+            
+              CACHE_MMU_MEM_FORCE_PU
+              The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up
+              2
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_STATE
+          This description will be updated in the near future.
+          0xB0
+          0x20
+          0x00000001
+          
+            
+              ICACHE_STATE
+              The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state
+              0
+              12
+              read-only
+            
+          
+        
+        
+          CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE
+          This description will be updated in the near future.
+          0xB4
+          0x20
+          
+            
+              RECORD_DISABLE_DB_ENCRYPT
+              Reserved.
+              0
+              1
+              read-write
+            
+            
+              RECORD_DISABLE_G0CB_DECRYPT
+              Reserved.
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON
+          This description will be updated in the near future.
+          0xB8
+          0x20
+          0x00000007
+          
+            
+              CLK_FORCE_ON_MANUAL_CRYPT
+              The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.
+              0
+              1
+              read-write
+            
+            
+              CLK_FORCE_ON_AUTO_CRYPT
+              The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.
+              1
+              1
+              read-write
+            
+            
+              CLK_FORCE_ON_CRYPT
+              The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.
+              2
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_PRELOAD_INT_CTRL
+          This description will be updated in the near future.
+          0xBC
+          0x20
+          
+            
+              ICACHE_PRELOAD_INT_ST
+              The bit is used to indicate the interrupt by  icache pre-load done.
+              0
+              1
+              read-only
+            
+            
+              ICACHE_PRELOAD_INT_ENA
+              The bit is used to enable the interrupt by  icache pre-load done.
+              1
+              1
+              read-write
+            
+            
+              ICACHE_PRELOAD_INT_CLR
+              The bit is used to clear the interrupt by  icache pre-load done.
+              2
+              1
+              write-only
+            
+          
+        
+        
+          CACHE_SYNC_INT_CTRL
+          This description will be updated in the near future.
+          0xC0
+          0x20
+          
+            
+              ICACHE_SYNC_INT_ST
+              The bit is used to indicate the interrupt by  icache sync done.
+              0
+              1
+              read-only
+            
+            
+              ICACHE_SYNC_INT_ENA
+              The bit is used to enable the interrupt by  icache sync done.
+              1
+              1
+              read-write
+            
+            
+              ICACHE_SYNC_INT_CLR
+              The bit is used to clear the interrupt by  icache sync done.
+              2
+              1
+              write-only
+            
+          
+        
+        
+          CACHE_MMU_OWNER
+          This description will be updated in the near future.
+          0xC4
+          0x20
+          
+            
+              CACHE_MMU_OWNER
+              The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CACHE_CONF_MISC
+          This description will be updated in the near future.
+          0xC8
+          0x20
+          0x00000007
+          
+            
+              CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT
+              The bit is used to disable checking mmu entry fault by preload operation.
+              0
+              1
+              read-write
+            
+            
+              CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT
+              The bit is used to disable checking mmu entry fault by sync operation.
+              1
+              1
+              read-write
+            
+            
+              CACHE_TRACE_ENA
+              The bit is used to enable cache trace function.
+              2
+              1
+              read-write
+            
+          
+        
+        
+          ICACHE_FREEZE
+          This description will be updated in the near future.
+          0xCC
+          0x20
+          
+            
+              ENA
+              The bit is used to enable icache freeze mode
+              0
+              1
+              read-write
+            
+            
+              MODE
+              The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss
+              1
+              1
+              read-write
+            
+            
+              DONE
+              The bit is used to indicate icache freeze success
+              2
+              1
+              read-only
+            
+          
+        
+        
+          ICACHE_ATOMIC_OPERATE_ENA
+          This description will be updated in the near future.
+          0xD0
+          0x20
+          0x00000001
+          
+            
+              ICACHE_ATOMIC_OPERATE_ENA
+              The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_REQUEST
+          This description will be updated in the near future.
+          0xD4
+          0x20
+          
+            
+              BYPASS
+              The bit is used to disable request recording which could cause performance issue
+              0
+              1
+              read-write
+            
+          
+        
+        
+          IBUS_PMS_TBL_LOCK
+          This description will be updated in the near future.
+          0xD8
+          0x20
+          
+            
+              IBUS_PMS_LOCK
+              The bit is used to configure the ibus permission control section boundary0
+              0
+              1
+              read-write
+            
+          
+        
+        
+          IBUS_PMS_TBL_BOUNDARY0
+          This description will be updated in the near future.
+          0xDC
+          0x20
+          
+            
+              IBUS_PMS_BOUNDARY0
+              The bit is used to configure the ibus permission control section boundary0
+              0
+              12
+              read-write
+            
+          
+        
+        
+          IBUS_PMS_TBL_BOUNDARY1
+          This description will be updated in the near future.
+          0xE0
+          0x20
+          0x00000800
+          
+            
+              IBUS_PMS_BOUNDARY1
+              The bit is used to configure the ibus permission control section boundary1
+              0
+              12
+              read-write
+            
+          
+        
+        
+          IBUS_PMS_TBL_BOUNDARY2
+          This description will be updated in the near future.
+          0xE4
+          0x20
+          0x00000800
+          
+            
+              IBUS_PMS_BOUNDARY2
+              The bit is used to configure the ibus permission control section boundary2
+              0
+              12
+              read-write
+            
+          
+        
+        
+          IBUS_PMS_TBL_ATTR
+          This description will be updated in the near future.
+          0xE8
+          0x20
+          0x000000FF
+          
+            
+              IBUS_PMS_SCT1_ATTR
+              The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
+              0
+              4
+              read-write
+            
+            
+              IBUS_PMS_SCT2_ATTR
+              The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
+              4
+              4
+              read-write
+            
+          
+        
+        
+          DBUS_PMS_TBL_LOCK
+          This description will be updated in the near future.
+          0xEC
+          0x20
+          
+            
+              DBUS_PMS_LOCK
+              The bit is used to configure the ibus permission control section boundary0
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DBUS_PMS_TBL_BOUNDARY0
+          This description will be updated in the near future.
+          0xF0
+          0x20
+          
+            
+              DBUS_PMS_BOUNDARY0
+              The bit is used to configure the dbus permission control section boundary0
+              0
+              12
+              read-write
+            
+          
+        
+        
+          DBUS_PMS_TBL_BOUNDARY1
+          This description will be updated in the near future.
+          0xF4
+          0x20
+          0x00000800
+          
+            
+              DBUS_PMS_BOUNDARY1
+              The bit is used to configure the dbus permission control section boundary1
+              0
+              12
+              read-write
+            
+          
+        
+        
+          DBUS_PMS_TBL_BOUNDARY2
+          This description will be updated in the near future.
+          0xF8
+          0x20
+          0x00000800
+          
+            
+              DBUS_PMS_BOUNDARY2
+              The bit is used to configure the dbus permission control section boundary2
+              0
+              12
+              read-write
+            
+          
+        
+        
+          DBUS_PMS_TBL_ATTR
+          This description will be updated in the near future.
+          0xFC
+          0x20
+          0x0000000F
+          
+            
+              DBUS_PMS_SCT1_ATTR
+              The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1
+              0
+              2
+              read-write
+            
+            
+              DBUS_PMS_SCT2_ATTR
+              The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1
+              2
+              2
+              read-write
+            
+          
+        
+        
+          CLOCK_GATE
+          This description will be updated in the near future.
+          0x100
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              clock gate enable.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          REG_DATE
+          This description will be updated in the near future.
+          0x3FC
+          0x20
+          0x02007160
+          
+            
+              DATE
+              version information
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      GPIO
+      General Purpose Input/Output
+      GPIO
+      0x60004000
+      
+        0x0
+        0x31C
+        registers
+      
+      
+        GPIO
+        16
+      
+      
+        GPIO_NMI
+        17
+      
+      
+        
+          BT_SELECT
+          GPIO bit select register
+          0x0
+          0x20
+          
+            
+              BT_SEL
+              GPIO bit select register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          OUT
+          GPIO output register
+          0x4
+          0x20
+          
+            
+              DATA_ORIG
+              GPIO output register for GPIO0-25
+              0
+              26
+              read-write
+            
+          
+        
+        
+          OUT_W1TS
+          GPIO output set register
+          0x8
+          0x20
+          
+            
+              OUT_W1TS
+              GPIO output set register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          OUT_W1TC
+          GPIO output clear register
+          0xC
+          0x20
+          
+            
+              OUT_W1TC
+              GPIO output clear register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          SDIO_SELECT
+          GPIO sdio select register
+          0x1C
+          0x20
+          
+            
+              SDIO_SEL
+              GPIO sdio select register
+              0
+              8
+              read-write
+            
+          
+        
+        
+          ENABLE
+          GPIO output enable register
+          0x20
+          0x20
+          
+            
+              DATA
+              GPIO output enable register for GPIO0-25
+              0
+              26
+              read-write
+            
+          
+        
+        
+          ENABLE_W1TS
+          GPIO output enable set register
+          0x24
+          0x20
+          
+            
+              ENABLE_W1TS
+              GPIO output enable set register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          ENABLE_W1TC
+          GPIO output enable clear register
+          0x28
+          0x20
+          
+            
+              ENABLE_W1TC
+              GPIO output enable clear register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          STRAP
+          pad strapping register
+          0x38
+          0x20
+          
+            
+              STRAPPING
+              pad strapping register
+              0
+              16
+              read-only
+            
+          
+        
+        
+          IN
+          GPIO input register
+          0x3C
+          0x20
+          
+            
+              DATA_NEXT
+              GPIO input register for GPIO0-25
+              0
+              26
+              read-only
+            
+          
+        
+        
+          STATUS
+          GPIO interrupt status register
+          0x44
+          0x20
+          
+            
+              INTERRUPT
+              GPIO interrupt status register for GPIO0-25
+              0
+              26
+              read-write
+            
+          
+        
+        
+          STATUS_W1TS
+          GPIO interrupt status set register
+          0x48
+          0x20
+          
+            
+              STATUS_W1TS
+              GPIO interrupt status set register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          STATUS_W1TC
+          GPIO interrupt status clear register
+          0x4C
+          0x20
+          
+            
+              STATUS_W1TC
+              GPIO interrupt status clear register for GPIO0-25
+              0
+              26
+              write-only
+            
+          
+        
+        
+          PCPU_INT
+          GPIO PRO_CPU interrupt status register
+          0x5C
+          0x20
+          
+            
+              PROCPU_INT
+              GPIO PRO_CPU interrupt status register for GPIO0-25
+              0
+              26
+              read-only
+            
+          
+        
+        
+          PCPU_NMI_INT
+          GPIO PRO_CPU(not shielded) interrupt status register
+          0x60
+          0x20
+          
+            
+              PROCPU_NMI_INT
+              GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25
+              0
+              26
+              read-only
+            
+          
+        
+        
+          CPUSDIO_INT
+          GPIO CPUSDIO interrupt status register
+          0x64
+          0x20
+          
+            
+              SDIO_INT
+              GPIO CPUSDIO interrupt status register for GPIO0-25
+              0
+              26
+              read-only
+            
+          
+        
+        
+          26
+          0x4
+          PIN%s
+          GPIO pin configuration register
+          0x74
+          0x20
+          
+            
+              PIN_SYNC2_BYPASS
+              set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
+              0
+              2
+              read-write
+            
+            
+              PIN_PAD_DRIVER
+              set this bit to select pad driver. 1:open-drain. :normal.
+              2
+              1
+              read-write
+            
+            
+              PIN_SYNC1_BYPASS
+              set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
+              3
+              2
+              read-write
+            
+            
+              PIN_INT_TYPE
+              set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level
+              7
+              3
+              read-write
+            
+            
+              PIN_WAKEUP_ENABLE
+              set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+              10
+              1
+              read-write
+            
+            
+              PIN_CONFIG
+              reserved
+              11
+              2
+              read-write
+            
+            
+              PIN_INT_ENA
+              set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.
+              13
+              5
+              read-write
+            
+          
+        
+        
+          STATUS_NEXT
+          GPIO interrupt source register
+          0x14C
+          0x20
+          
+            
+              STATUS_INTERRUPT_NEXT
+              GPIO interrupt source register for GPIO0-25
+              0
+              26
+              read-only
+            
+          
+        
+        
+          128
+          0x4
+          FUNC%s_IN_SEL_CFG
+          GPIO input function configuration register
+          0x154
+          0x20
+          
+            
+              IN_SEL
+              set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level.
+              0
+              5
+              read-write
+            
+            
+              IN_INV_SEL
+              set this bit to invert input signal. 1:invert. :not invert.
+              5
+              1
+              read-write
+            
+            
+              SEL
+              set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+              6
+              1
+              read-write
+            
+          
+        
+        
+          26
+          0x4
+          FUNC%s_OUT_SEL_CFG
+          GPIO output function select register
+          0x554
+          0x20
+          0x00000080
+          
+            
+              OUT_SEL
+              The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].
+              0
+              8
+              read-write
+            
+            
+              INV_SEL
+              set this bit to invert output signal.1:invert.:not invert.
+              8
+              1
+              read-write
+            
+            
+              OEN_SEL
+              set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal.
+              9
+              1
+              read-write
+            
+            
+              OEN_INV_SEL
+              set this bit to invert output enable signal.1:invert.:not invert.
+              10
+              1
+              read-write
+            
+          
+        
+        
+          CLOCK_GATE
+          GPIO clock gate register
+          0x62C
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              set this bit to enable GPIO clock gate
+              0
+              1
+              read-write
+            
+          
+        
+        
+          REG_DATE
+          GPIO version register
+          0x6FC
+          0x20
+          0x02006130
+          
+            
+              REG_DATE
+              version register
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      GPIOSD
+      Sigma-Delta Modulation
+      GPIOSD
+      0x60004F00
+      
+        0x0
+        0x1C
+        registers
+      
+      
+        
+          4
+          0x4
+          SIGMADELTA%s
+          Duty Cycle Configure Register of SDM%s
+          0x0
+          0x20
+          0x0000FF00
+          
+            
+              SD0_IN
+              This field is used to configure the duty cycle of sigma delta modulation output.
+              0
+              8
+              read-write
+            
+            
+              SD0_PRESCALE
+              This field is used to set a divider value to divide APB clock.
+              8
+              8
+              read-write
+            
+          
+        
+        
+          SIGMADELTA_CG
+          Clock Gating Configure Register
+          0x20
+          0x20
+          
+            
+              CLK_EN
+              Clock enable bit of configuration registers for sigma delta modulation.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SIGMADELTA_MISC
+          MISC Register
+          0x24
+          0x20
+          
+            
+              FUNCTION_CLK_EN
+              Clock enable bit of sigma delta modulation.
+              30
+              1
+              read-write
+            
+            
+              SPI_SWAP
+              Reserved.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SIGMADELTA_VERSION
+          Version Control Register
+          0x28
+          0x20
+          0x02006230
+          
+            
+              GPIO_SD_DATE
+              Version control register.
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      HMAC
+      HMAC (Hash-based Message Authentication Code) Accelerator
+      HMAC
+      0x6003E000
+      
+        0x0
+        0xA0
+        registers
+      
+      
+        
+          SET_START
+          Process control register 0.
+          0x40
+          0x20
+          
+            
+              SET_START
+              Start hmac operation.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_PARA_PURPOSE
+          Configure purpose.
+          0x44
+          0x20
+          
+            
+              PURPOSE_SET
+              Set hmac parameter purpose.
+              0
+              4
+              write-only
+            
+          
+        
+        
+          SET_PARA_KEY
+          Configure key.
+          0x48
+          0x20
+          
+            
+              KEY_SET
+              Set hmac parameter key.
+              0
+              3
+              write-only
+            
+          
+        
+        
+          SET_PARA_FINISH
+          Finish initial configuration.
+          0x4C
+          0x20
+          
+            
+              SET_PARA_END
+              Finish hmac configuration.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_MESSAGE_ONE
+          Process control register 1.
+          0x50
+          0x20
+          
+            
+              SET_TEXT_ONE
+              Call SHA to calculate one message block.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_MESSAGE_ING
+          Process control register 2.
+          0x54
+          0x20
+          
+            
+              SET_TEXT_ING
+              Continue typical hmac.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_MESSAGE_END
+          Process control register 3.
+          0x58
+          0x20
+          
+            
+              SET_TEXT_END
+              Start hardware padding.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_RESULT_FINISH
+          Process control register 4.
+          0x5C
+          0x20
+          
+            
+              SET_RESULT_END
+              After read result from upstream, then let hmac back to idle.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_INVALIDATE_JTAG
+          Invalidate register 0.
+          0x60
+          0x20
+          
+            
+              SET_INVALIDATE_JTAG
+              Clear result from hmac downstream JTAG.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_INVALIDATE_DS
+          Invalidate register 1.
+          0x64
+          0x20
+          
+            
+              SET_INVALIDATE_DS
+              Clear result from hmac downstream DS.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          QUERY_ERROR
+          Error register.
+          0x68
+          0x20
+          
+            
+              QUREY_CHECK
+              Hmac configuration state. 0: key are agree with purpose. 1: error
+              0
+              1
+              read-only
+            
+          
+        
+        
+          QUERY_BUSY
+          Busy register.
+          0x6C
+          0x20
+          
+            
+              BUSY_STATE
+              Hmac state. 1'b0: idle. 1'b1: busy
+              0
+              1
+              read-only
+            
+          
+        
+        
+          64
+          0x1
+          WR_MESSAGE_MEM[%s]
+          Message block memory.
+          0x80
+          0x8
+        
+        
+          32
+          0x1
+          RD_RESULT_MEM[%s]
+          Result from upstream.
+          0xC0
+          0x8
+        
+        
+          SET_MESSAGE_PAD
+          Process control register 5.
+          0xF0
+          0x20
+          
+            
+              SET_TEXT_PAD
+              Start software padding.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          ONE_BLOCK
+          Process control register 6.
+          0xF4
+          0x20
+          
+            
+              SET_ONE_BLOCK
+              Don't have to do padding.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SOFT_JTAG_CTRL
+          Jtag register 0.
+          0xF8
+          0x20
+          
+            
+              SOFT_JTAG_CTRL
+              Turn on JTAG verification.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          WR_JTAG
+          Jtag register 1.
+          0xFC
+          0x20
+          
+            
+              WR_JTAG
+              32-bit of key to be compared.
+              0
+              32
+              write-only
+            
+          
+        
+      
+    
+    
+      I2C0
+      I2C (Inter-Integrated Circuit) Controller
+      I2C
+      0x60013000
+      
+        0x0
+        0x90
+        registers
+      
+      
+        I2C_EXT0
+        29
+      
+      
+        
+          SCL_LOW_PERIOD
+          I2C_SCL_LOW_PERIOD_REG
+          0x0
+          0x20
+          
+            
+              SCL_LOW_PERIOD
+              reg_scl_low_period
+              0
+              9
+              read-write
+            
+          
+        
+        
+          CTR
+          I2C_CTR_REG
+          0x4
+          0x20
+          0x0000020B
+          
+            
+              SDA_FORCE_OUT
+              reg_sda_force_out
+              0
+              1
+              read-write
+            
+            
+              SCL_FORCE_OUT
+              reg_scl_force_out
+              1
+              1
+              read-write
+            
+            
+              SAMPLE_SCL_LEVEL
+              reg_sample_scl_level
+              2
+              1
+              read-write
+            
+            
+              RX_FULL_ACK_LEVEL
+              reg_rx_full_ack_level
+              3
+              1
+              read-write
+            
+            
+              MS_MODE
+              reg_ms_mode
+              4
+              1
+              read-write
+            
+            
+              TRANS_START
+              reg_trans_start
+              5
+              1
+              write-only
+            
+            
+              TX_LSB_FIRST
+              reg_tx_lsb_first
+              6
+              1
+              read-write
+            
+            
+              RX_LSB_FIRST
+              reg_rx_lsb_first
+              7
+              1
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en
+              8
+              1
+              read-write
+            
+            
+              ARBITRATION_EN
+              reg_arbitration_en
+              9
+              1
+              read-write
+            
+            
+              FSM_RST
+              reg_fsm_rst
+              10
+              1
+              write-only
+            
+            
+              CONF_UPGATE
+              reg_conf_upgate
+              11
+              1
+              write-only
+            
+            
+              SLV_TX_AUTO_START_EN
+              reg_slv_tx_auto_start_en
+              12
+              1
+              read-write
+            
+            
+              ADDR_10BIT_RW_CHECK_EN
+              reg_addr_10bit_rw_check_en
+              13
+              1
+              read-write
+            
+            
+              ADDR_BROADCASTING_EN
+              reg_addr_broadcasting_en
+              14
+              1
+              read-write
+            
+          
+        
+        
+          SR
+          I2C_SR_REG
+          0x8
+          0x20
+          0x0000C000
+          
+            
+              RESP_REC
+              reg_resp_rec
+              0
+              1
+              read-only
+            
+            
+              SLAVE_RW
+              reg_slave_rw
+              1
+              1
+              read-only
+            
+            
+              ARB_LOST
+              reg_arb_lost
+              3
+              1
+              read-only
+            
+            
+              BUS_BUSY
+              reg_bus_busy
+              4
+              1
+              read-only
+            
+            
+              SLAVE_ADDRESSED
+              reg_slave_addressed
+              5
+              1
+              read-only
+            
+            
+              RXFIFO_CNT
+              reg_rxfifo_cnt
+              8
+              6
+              read-only
+            
+            
+              STRETCH_CAUSE
+              reg_stretch_cause
+              14
+              2
+              read-only
+            
+            
+              TXFIFO_CNT
+              reg_txfifo_cnt
+              18
+              6
+              read-only
+            
+            
+              SCL_MAIN_STATE_LAST
+              reg_scl_main_state_last
+              24
+              3
+              read-only
+            
+            
+              SCL_STATE_LAST
+              reg_scl_state_last
+              28
+              3
+              read-only
+            
+          
+        
+        
+          TO
+          I2C_TO_REG
+          0xC
+          0x20
+          0x00000010
+          
+            
+              TIME_OUT_VALUE
+              reg_time_out_value
+              0
+              5
+              read-write
+            
+            
+              TIME_OUT_EN
+              reg_time_out_en
+              5
+              1
+              read-write
+            
+          
+        
+        
+          SLAVE_ADDR
+          I2C_SLAVE_ADDR_REG
+          0x10
+          0x20
+          
+            
+              SLAVE_ADDR
+              reg_slave_addr
+              0
+              15
+              read-write
+            
+            
+              ADDR_10BIT_EN
+              reg_addr_10bit_en
+              31
+              1
+              read-write
+            
+          
+        
+        
+          FIFO_ST
+          I2C_FIFO_ST_REG
+          0x14
+          0x20
+          
+            
+              RXFIFO_RADDR
+              reg_rxfifo_raddr
+              0
+              5
+              read-only
+            
+            
+              RXFIFO_WADDR
+              reg_rxfifo_waddr
+              5
+              5
+              read-only
+            
+            
+              TXFIFO_RADDR
+              reg_txfifo_raddr
+              10
+              5
+              read-only
+            
+            
+              TXFIFO_WADDR
+              reg_txfifo_waddr
+              15
+              5
+              read-only
+            
+            
+              SLAVE_RW_POINT
+              reg_slave_rw_point
+              22
+              8
+              read-only
+            
+          
+        
+        
+          FIFO_CONF
+          I2C_FIFO_CONF_REG
+          0x18
+          0x20
+          0x0000408B
+          
+            
+              RXFIFO_WM_THRHD
+              reg_rxfifo_wm_thrhd
+              0
+              5
+              read-write
+            
+            
+              TXFIFO_WM_THRHD
+              reg_txfifo_wm_thrhd
+              5
+              5
+              read-write
+            
+            
+              NONFIFO_EN
+              reg_nonfifo_en
+              10
+              1
+              read-write
+            
+            
+              FIFO_ADDR_CFG_EN
+              reg_fifo_addr_cfg_en
+              11
+              1
+              read-write
+            
+            
+              RX_FIFO_RST
+              reg_rx_fifo_rst
+              12
+              1
+              read-write
+            
+            
+              TX_FIFO_RST
+              reg_tx_fifo_rst
+              13
+              1
+              read-write
+            
+            
+              FIFO_PRT_EN
+              reg_fifo_prt_en
+              14
+              1
+              read-write
+            
+          
+        
+        
+          DATA
+          I2C_FIFO_DATA_REG
+          0x1C
+          0x20
+          
+            
+              FIFO_RDATA
+              reg_fifo_rdata
+              0
+              8
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          I2C_INT_RAW_REG
+          0x20
+          0x20
+          0x00000002
+          
+            
+              RXFIFO_WM_INT_RAW
+              reg_rxfifo_wm_int_raw
+              0
+              1
+              read-only
+            
+            
+              TXFIFO_WM_INT_RAW
+              reg_txfifo_wm_int_raw
+              1
+              1
+              read-only
+            
+            
+              RXFIFO_OVF_INT_RAW
+              reg_rxfifo_ovf_int_raw
+              2
+              1
+              read-only
+            
+            
+              END_DETECT_INT_RAW
+              reg_end_detect_int_raw
+              3
+              1
+              read-only
+            
+            
+              BYTE_TRANS_DONE_INT_RAW
+              reg_byte_trans_done_int_raw
+              4
+              1
+              read-only
+            
+            
+              ARBITRATION_LOST_INT_RAW
+              reg_arbitration_lost_int_raw
+              5
+              1
+              read-only
+            
+            
+              MST_TXFIFO_UDF_INT_RAW
+              reg_mst_txfifo_udf_int_raw
+              6
+              1
+              read-only
+            
+            
+              TRANS_COMPLETE_INT_RAW
+              reg_trans_complete_int_raw
+              7
+              1
+              read-only
+            
+            
+              TIME_OUT_INT_RAW
+              reg_time_out_int_raw
+              8
+              1
+              read-only
+            
+            
+              TRANS_START_INT_RAW
+              reg_trans_start_int_raw
+              9
+              1
+              read-only
+            
+            
+              NACK_INT_RAW
+              reg_nack_int_raw
+              10
+              1
+              read-only
+            
+            
+              TXFIFO_OVF_INT_RAW
+              reg_txfifo_ovf_int_raw
+              11
+              1
+              read-only
+            
+            
+              RXFIFO_UDF_INT_RAW
+              reg_rxfifo_udf_int_raw
+              12
+              1
+              read-only
+            
+            
+              SCL_ST_TO_INT_RAW
+              reg_scl_st_to_int_raw
+              13
+              1
+              read-only
+            
+            
+              SCL_MAIN_ST_TO_INT_RAW
+              reg_scl_main_st_to_int_raw
+              14
+              1
+              read-only
+            
+            
+              DET_START_INT_RAW
+              reg_det_start_int_raw
+              15
+              1
+              read-only
+            
+            
+              SLAVE_STRETCH_INT_RAW
+              reg_slave_stretch_int_raw
+              16
+              1
+              read-only
+            
+            
+              GENERAL_CALL_INT_RAW
+              reg_general_call_int_raw
+              17
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR
+          I2C_INT_CLR_REG
+          0x24
+          0x20
+          
+            
+              RXFIFO_WM_INT_CLR
+              reg_rxfifo_wm_int_clr
+              0
+              1
+              write-only
+            
+            
+              TXFIFO_WM_INT_CLR
+              reg_txfifo_wm_int_clr
+              1
+              1
+              write-only
+            
+            
+              RXFIFO_OVF_INT_CLR
+              reg_rxfifo_ovf_int_clr
+              2
+              1
+              write-only
+            
+            
+              END_DETECT_INT_CLR
+              reg_end_detect_int_clr
+              3
+              1
+              write-only
+            
+            
+              BYTE_TRANS_DONE_INT_CLR
+              reg_byte_trans_done_int_clr
+              4
+              1
+              write-only
+            
+            
+              ARBITRATION_LOST_INT_CLR
+              reg_arbitration_lost_int_clr
+              5
+              1
+              write-only
+            
+            
+              MST_TXFIFO_UDF_INT_CLR
+              reg_mst_txfifo_udf_int_clr
+              6
+              1
+              write-only
+            
+            
+              TRANS_COMPLETE_INT_CLR
+              reg_trans_complete_int_clr
+              7
+              1
+              write-only
+            
+            
+              TIME_OUT_INT_CLR
+              reg_time_out_int_clr
+              8
+              1
+              write-only
+            
+            
+              TRANS_START_INT_CLR
+              reg_trans_start_int_clr
+              9
+              1
+              write-only
+            
+            
+              NACK_INT_CLR
+              reg_nack_int_clr
+              10
+              1
+              write-only
+            
+            
+              TXFIFO_OVF_INT_CLR
+              reg_txfifo_ovf_int_clr
+              11
+              1
+              write-only
+            
+            
+              RXFIFO_UDF_INT_CLR
+              reg_rxfifo_udf_int_clr
+              12
+              1
+              write-only
+            
+            
+              SCL_ST_TO_INT_CLR
+              reg_scl_st_to_int_clr
+              13
+              1
+              write-only
+            
+            
+              SCL_MAIN_ST_TO_INT_CLR
+              reg_scl_main_st_to_int_clr
+              14
+              1
+              write-only
+            
+            
+              DET_START_INT_CLR
+              reg_det_start_int_clr
+              15
+              1
+              write-only
+            
+            
+              SLAVE_STRETCH_INT_CLR
+              reg_slave_stretch_int_clr
+              16
+              1
+              write-only
+            
+            
+              GENERAL_CALL_INT_CLR
+              reg_general_call_int_clr
+              17
+              1
+              write-only
+            
+          
+        
+        
+          INT_ENA
+          I2C_INT_ENA_REG
+          0x28
+          0x20
+          
+            
+              RXFIFO_WM_INT_ENA
+              reg_rxfifo_wm_int_ena
+              0
+              1
+              read-write
+            
+            
+              TXFIFO_WM_INT_ENA
+              reg_txfifo_wm_int_ena
+              1
+              1
+              read-write
+            
+            
+              RXFIFO_OVF_INT_ENA
+              reg_rxfifo_ovf_int_ena
+              2
+              1
+              read-write
+            
+            
+              END_DETECT_INT_ENA
+              reg_end_detect_int_ena
+              3
+              1
+              read-write
+            
+            
+              BYTE_TRANS_DONE_INT_ENA
+              reg_byte_trans_done_int_ena
+              4
+              1
+              read-write
+            
+            
+              ARBITRATION_LOST_INT_ENA
+              reg_arbitration_lost_int_ena
+              5
+              1
+              read-write
+            
+            
+              MST_TXFIFO_UDF_INT_ENA
+              reg_mst_txfifo_udf_int_ena
+              6
+              1
+              read-write
+            
+            
+              TRANS_COMPLETE_INT_ENA
+              reg_trans_complete_int_ena
+              7
+              1
+              read-write
+            
+            
+              TIME_OUT_INT_ENA
+              reg_time_out_int_ena
+              8
+              1
+              read-write
+            
+            
+              TRANS_START_INT_ENA
+              reg_trans_start_int_ena
+              9
+              1
+              read-write
+            
+            
+              NACK_INT_ENA
+              reg_nack_int_ena
+              10
+              1
+              read-write
+            
+            
+              TXFIFO_OVF_INT_ENA
+              reg_txfifo_ovf_int_ena
+              11
+              1
+              read-write
+            
+            
+              RXFIFO_UDF_INT_ENA
+              reg_rxfifo_udf_int_ena
+              12
+              1
+              read-write
+            
+            
+              SCL_ST_TO_INT_ENA
+              reg_scl_st_to_int_ena
+              13
+              1
+              read-write
+            
+            
+              SCL_MAIN_ST_TO_INT_ENA
+              reg_scl_main_st_to_int_ena
+              14
+              1
+              read-write
+            
+            
+              DET_START_INT_ENA
+              reg_det_start_int_ena
+              15
+              1
+              read-write
+            
+            
+              SLAVE_STRETCH_INT_ENA
+              reg_slave_stretch_int_ena
+              16
+              1
+              read-write
+            
+            
+              GENERAL_CALL_INT_ENA
+              reg_general_call_int_ena
+              17
+              1
+              read-write
+            
+          
+        
+        
+          INT_STATUS
+          I2C_INT_STATUS_REG
+          0x2C
+          0x20
+          
+            
+              RXFIFO_WM_INT_ST
+              reg_rxfifo_wm_int_st
+              0
+              1
+              read-only
+            
+            
+              TXFIFO_WM_INT_ST
+              reg_txfifo_wm_int_st
+              1
+              1
+              read-only
+            
+            
+              RXFIFO_OVF_INT_ST
+              reg_rxfifo_ovf_int_st
+              2
+              1
+              read-only
+            
+            
+              END_DETECT_INT_ST
+              reg_end_detect_int_st
+              3
+              1
+              read-only
+            
+            
+              BYTE_TRANS_DONE_INT_ST
+              reg_byte_trans_done_int_st
+              4
+              1
+              read-only
+            
+            
+              ARBITRATION_LOST_INT_ST
+              reg_arbitration_lost_int_st
+              5
+              1
+              read-only
+            
+            
+              MST_TXFIFO_UDF_INT_ST
+              reg_mst_txfifo_udf_int_st
+              6
+              1
+              read-only
+            
+            
+              TRANS_COMPLETE_INT_ST
+              reg_trans_complete_int_st
+              7
+              1
+              read-only
+            
+            
+              TIME_OUT_INT_ST
+              reg_time_out_int_st
+              8
+              1
+              read-only
+            
+            
+              TRANS_START_INT_ST
+              reg_trans_start_int_st
+              9
+              1
+              read-only
+            
+            
+              NACK_INT_ST
+              reg_nack_int_st
+              10
+              1
+              read-only
+            
+            
+              TXFIFO_OVF_INT_ST
+              reg_txfifo_ovf_int_st
+              11
+              1
+              read-only
+            
+            
+              RXFIFO_UDF_INT_ST
+              reg_rxfifo_udf_int_st
+              12
+              1
+              read-only
+            
+            
+              SCL_ST_TO_INT_ST
+              reg_scl_st_to_int_st
+              13
+              1
+              read-only
+            
+            
+              SCL_MAIN_ST_TO_INT_ST
+              reg_scl_main_st_to_int_st
+              14
+              1
+              read-only
+            
+            
+              DET_START_INT_ST
+              reg_det_start_int_st
+              15
+              1
+              read-only
+            
+            
+              SLAVE_STRETCH_INT_ST
+              reg_slave_stretch_int_st
+              16
+              1
+              read-only
+            
+            
+              GENERAL_CALL_INT_ST
+              reg_general_call_int_st
+              17
+              1
+              read-only
+            
+          
+        
+        
+          SDA_HOLD
+          I2C_SDA_HOLD_REG
+          0x30
+          0x20
+          
+            
+              TIME
+              reg_sda_hold_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SDA_SAMPLE
+          I2C_SDA_SAMPLE_REG
+          0x34
+          0x20
+          
+            
+              TIME
+              reg_sda_sample_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SCL_HIGH_PERIOD
+          I2C_SCL_HIGH_PERIOD_REG
+          0x38
+          0x20
+          
+            
+              SCL_HIGH_PERIOD
+              reg_scl_high_period
+              0
+              9
+              read-write
+            
+            
+              SCL_WAIT_HIGH_PERIOD
+              reg_scl_wait_high_period
+              9
+              7
+              read-write
+            
+          
+        
+        
+          SCL_START_HOLD
+          I2C_SCL_START_HOLD_REG
+          0x40
+          0x20
+          0x00000008
+          
+            
+              TIME
+              reg_scl_start_hold_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SCL_RSTART_SETUP
+          I2C_SCL_RSTART_SETUP_REG
+          0x44
+          0x20
+          0x00000008
+          
+            
+              TIME
+              reg_scl_rstart_setup_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SCL_STOP_HOLD
+          I2C_SCL_STOP_HOLD_REG
+          0x48
+          0x20
+          0x00000008
+          
+            
+              TIME
+              reg_scl_stop_hold_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SCL_STOP_SETUP
+          I2C_SCL_STOP_SETUP_REG
+          0x4C
+          0x20
+          0x00000008
+          
+            
+              TIME
+              reg_scl_stop_setup_time
+              0
+              9
+              read-write
+            
+          
+        
+        
+          FILTER_CFG
+          I2C_FILTER_CFG_REG
+          0x50
+          0x20
+          0x00000300
+          
+            
+              SCL_FILTER_THRES
+              reg_scl_filter_thres
+              0
+              4
+              read-write
+            
+            
+              SDA_FILTER_THRES
+              reg_sda_filter_thres
+              4
+              4
+              read-write
+            
+            
+              SCL_FILTER_EN
+              reg_scl_filter_en
+              8
+              1
+              read-write
+            
+            
+              SDA_FILTER_EN
+              reg_sda_filter_en
+              9
+              1
+              read-write
+            
+          
+        
+        
+          CLK_CONF
+          I2C_CLK_CONF_REG
+          0x54
+          0x20
+          0x00200000
+          
+            
+              SCLK_DIV_NUM
+              reg_sclk_div_num
+              0
+              8
+              read-write
+            
+            
+              SCLK_DIV_A
+              reg_sclk_div_a
+              8
+              6
+              read-write
+            
+            
+              SCLK_DIV_B
+              reg_sclk_div_b
+              14
+              6
+              read-write
+            
+            
+              SCLK_SEL
+              reg_sclk_sel
+              20
+              1
+              read-write
+            
+            
+              SCLK_ACTIVE
+              reg_sclk_active
+              21
+              1
+              read-write
+            
+          
+        
+        
+          8
+          0x4
+          COMD%s
+          I2C_COMD%s_REG
+          0x58
+          0x20
+          
+            
+              COMMAND
+              reg_command
+              0
+              14
+              read-write
+            
+            
+              COMMAND_DONE
+              reg_command_done
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SCL_ST_TIME_OUT
+          I2C_SCL_ST_TIME_OUT_REG
+          0x78
+          0x20
+          0x00000010
+          
+            
+              SCL_ST_TO_I2C
+              reg_scl_st_to_regno more than 23
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SCL_MAIN_ST_TIME_OUT
+          I2C_SCL_MAIN_ST_TIME_OUT_REG
+          0x7C
+          0x20
+          0x00000010
+          
+            
+              SCL_MAIN_ST_TO_I2C
+              reg_scl_main_st_to_regno more than 23
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SCL_SP_CONF
+          I2C_SCL_SP_CONF_REG
+          0x80
+          0x20
+          
+            
+              SCL_RST_SLV_EN
+              reg_scl_rst_slv_en
+              0
+              1
+              read-write
+            
+            
+              SCL_RST_SLV_NUM
+              reg_scl_rst_slv_num
+              1
+              5
+              read-write
+            
+            
+              SCL_PD_EN
+              reg_scl_pd_en
+              6
+              1
+              read-write
+            
+            
+              SDA_PD_EN
+              reg_sda_pd_en
+              7
+              1
+              read-write
+            
+          
+        
+        
+          SCL_STRETCH_CONF
+          I2C_SCL_STRETCH_CONF_REG
+          0x84
+          0x20
+          
+            
+              STRETCH_PROTECT_NUM
+              reg_stretch_protect_num
+              0
+              10
+              read-write
+            
+            
+              SLAVE_SCL_STRETCH_EN
+              reg_slave_scl_stretch_en
+              10
+              1
+              read-write
+            
+            
+              SLAVE_SCL_STRETCH_CLR
+              reg_slave_scl_stretch_clr
+              11
+              1
+              write-only
+            
+            
+              SLAVE_BYTE_ACK_CTL_EN
+              reg_slave_byte_ack_ctl_en
+              12
+              1
+              read-write
+            
+            
+              SLAVE_BYTE_ACK_LVL
+              reg_slave_byte_ack_lvl
+              13
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          I2C_DATE_REG
+          0xF8
+          0x20
+          0x20070201
+          
+            
+              DATE
+              reg_date
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TXFIFO_START_ADDR
+          I2C_TXFIFO_START_ADDR_REG
+          0x100
+          0x20
+          
+            
+              TXFIFO_START_ADDR
+              reg_txfifo_start_addr.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          RXFIFO_START_ADDR
+          I2C_RXFIFO_START_ADDR_REG
+          0x180
+          0x20
+          
+            
+              RXFIFO_START_ADDR
+              reg_rxfifo_start_addr.
+              0
+              32
+              read-only
+            
+          
+        
+      
+    
+    
+      I2S
+      I2S (Inter-IC Sound) Controller
+      I2S
+      0x6002D000
+      
+        0x0
+        0x5C
+        registers
+      
+      
+        I2S
+        20
+      
+      
+        
+          INT_RAW
+          I2S interrupt raw register, valid in level.
+          0xC
+          0x20
+          
+            
+              RX_DONE_INT_RAW
+              The raw interrupt status bit  for the i2s_rx_done_int interrupt
+              0
+              1
+              read-only
+            
+            
+              TX_DONE_INT_RAW
+              The raw interrupt status bit  for the i2s_tx_done_int interrupt
+              1
+              1
+              read-only
+            
+            
+              RX_HUNG_INT_RAW
+              The raw interrupt status bit  for the i2s_rx_hung_int interrupt
+              2
+              1
+              read-only
+            
+            
+              TX_HUNG_INT_RAW
+              The raw interrupt status bit  for the i2s_tx_hung_int interrupt
+              3
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          I2S interrupt status register.
+          0x10
+          0x20
+          
+            
+              RX_DONE_INT_ST
+              The masked interrupt status bit  for the i2s_rx_done_int interrupt
+              0
+              1
+              read-only
+            
+            
+              TX_DONE_INT_ST
+              The masked interrupt status bit  for the i2s_tx_done_int interrupt
+              1
+              1
+              read-only
+            
+            
+              RX_HUNG_INT_ST
+              The masked interrupt status bit  for the i2s_rx_hung_int interrupt
+              2
+              1
+              read-only
+            
+            
+              TX_HUNG_INT_ST
+              The masked interrupt status bit  for the i2s_tx_hung_int interrupt
+              3
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          I2S interrupt enable register.
+          0x14
+          0x20
+          
+            
+              RX_DONE_INT_ENA
+              The interrupt enable bit  for the i2s_rx_done_int interrupt
+              0
+              1
+              read-write
+            
+            
+              TX_DONE_INT_ENA
+              The interrupt enable bit  for the i2s_tx_done_int interrupt
+              1
+              1
+              read-write
+            
+            
+              RX_HUNG_INT_ENA
+              The interrupt enable bit  for the i2s_rx_hung_int interrupt
+              2
+              1
+              read-write
+            
+            
+              TX_HUNG_INT_ENA
+              The interrupt enable bit  for the i2s_tx_hung_int interrupt
+              3
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          I2S interrupt clear register.
+          0x18
+          0x20
+          
+            
+              RX_DONE_INT_CLR
+              Set this bit to clear the i2s_rx_done_int interrupt
+              0
+              1
+              write-only
+            
+            
+              TX_DONE_INT_CLR
+              Set this bit to clear the i2s_tx_done_int interrupt
+              1
+              1
+              write-only
+            
+            
+              RX_HUNG_INT_CLR
+              Set this bit to clear the i2s_rx_hung_int interrupt
+              2
+              1
+              write-only
+            
+            
+              TX_HUNG_INT_CLR
+              Set this bit to clear the i2s_tx_hung_int interrupt
+              3
+              1
+              write-only
+            
+          
+        
+        
+          RX_CONF
+          I2S RX configure register
+          0x20
+          0x20
+          0x00009600
+          
+            
+              RX_RESET
+              Set this bit to reset receiver
+              0
+              1
+              write-only
+            
+            
+              RX_FIFO_RESET
+              Set this bit to reset Rx AFIFO
+              1
+              1
+              write-only
+            
+            
+              RX_START
+              Set this bit to start receiving data
+              2
+              1
+              read-write
+            
+            
+              RX_SLAVE_MOD
+              Set this bit to enable slave receiver mode
+              3
+              1
+              read-write
+            
+            
+              RX_MONO
+              Set this bit to enable receiver  in mono mode
+              5
+              1
+              read-write
+            
+            
+              RX_BIG_ENDIAN
+              I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+              7
+              1
+              read-write
+            
+            
+              RX_UPDATE
+              Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.
+              8
+              1
+              read-write
+            
+            
+              RX_MONO_FST_VLD
+              1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.
+              9
+              1
+              read-write
+            
+            
+              RX_PCM_CONF
+              I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+              10
+              2
+              read-write
+            
+            
+              RX_PCM_BYPASS
+              Set this bit to bypass Compress/Decompress module for received data.
+              12
+              1
+              read-write
+            
+            
+              RX_STOP_MODE
+              0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+              13
+              2
+              read-write
+            
+            
+              RX_LEFT_ALIGN
+              1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+              15
+              1
+              read-write
+            
+            
+              RX_24_FILL_EN
+              1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+              16
+              1
+              read-write
+            
+            
+              RX_WS_IDLE_POL
+              0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+              17
+              1
+              read-write
+            
+            
+              RX_BIT_ORDER
+              I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.
+              18
+              1
+              read-write
+            
+            
+              RX_TDM_EN
+              1: Enable I2S TDM Rx mode . 0: Disable.
+              19
+              1
+              read-write
+            
+            
+              RX_PDM_EN
+              1: Enable I2S PDM Rx mode . 0: Disable.
+              20
+              1
+              read-write
+            
+          
+        
+        
+          TX_CONF
+          I2S TX configure register
+          0x24
+          0x20
+          0x0000B200
+          
+            
+              TX_RESET
+              Set this bit to reset transmitter
+              0
+              1
+              write-only
+            
+            
+              TX_FIFO_RESET
+              Set this bit to reset Tx AFIFO
+              1
+              1
+              write-only
+            
+            
+              TX_START
+              Set this bit to start transmitting data
+              2
+              1
+              read-write
+            
+            
+              TX_SLAVE_MOD
+              Set this bit to enable slave transmitter mode
+              3
+              1
+              read-write
+            
+            
+              TX_MONO
+              Set this bit to enable transmitter in mono mode
+              5
+              1
+              read-write
+            
+            
+              TX_CHAN_EQUAL
+              1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+              6
+              1
+              read-write
+            
+            
+              TX_BIG_ENDIAN
+              I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.
+              7
+              1
+              read-write
+            
+            
+              TX_UPDATE
+              Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.
+              8
+              1
+              read-write
+            
+            
+              TX_MONO_FST_VLD
+              1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.
+              9
+              1
+              read-write
+            
+            
+              TX_PCM_CONF
+              I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+              10
+              2
+              read-write
+            
+            
+              TX_PCM_BYPASS
+              Set this bit to bypass  Compress/Decompress module for transmitted data.
+              12
+              1
+              read-write
+            
+            
+              TX_STOP_EN
+              Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+              13
+              1
+              read-write
+            
+            
+              TX_LEFT_ALIGN
+              1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+              15
+              1
+              read-write
+            
+            
+              TX_24_FILL_EN
+              1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+              16
+              1
+              read-write
+            
+            
+              TX_WS_IDLE_POL
+              0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel.
+              17
+              1
+              read-write
+            
+            
+              TX_BIT_ORDER
+              I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.
+              18
+              1
+              read-write
+            
+            
+              TX_TDM_EN
+              1: Enable I2S TDM Tx mode . 0: Disable.
+              19
+              1
+              read-write
+            
+            
+              TX_PDM_EN
+              1: Enable I2S PDM Tx mode . 0: Disable.
+              20
+              1
+              read-write
+            
+            
+              TX_CHAN_MOD
+              I2S transmitter channel mode configuration bits.
+              24
+              3
+              read-write
+            
+            
+              SIG_LOOPBACK
+              Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.
+              27
+              1
+              read-write
+            
+          
+        
+        
+          RX_CONF1
+          I2S RX configure register 1
+          0x28
+          0x20
+          0x2F3DE300
+          
+            
+              RX_TDM_WS_WIDTH
+              The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
+              0
+              7
+              read-write
+            
+            
+              RX_BCK_DIV_NUM
+              Bit clock configuration bits in receiver mode.
+              7
+              6
+              read-write
+            
+            
+              RX_BITS_MOD
+              Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
+              13
+              5
+              read-write
+            
+            
+              RX_HALF_SAMPLE_BITS
+              I2S Rx half sample bits -1.
+              18
+              6
+              read-write
+            
+            
+              RX_TDM_CHAN_BITS
+              The Rx bit number for each channel minus 1in TDM mode.
+              24
+              5
+              read-write
+            
+            
+              RX_MSB_SHIFT
+              Set this bit to enable receiver in Phillips standard mode
+              29
+              1
+              read-write
+            
+          
+        
+        
+          TX_CONF1
+          I2S TX configure register 1
+          0x2C
+          0x20
+          0x6F3DE300
+          
+            
+              TX_TDM_WS_WIDTH
+              The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
+              0
+              7
+              read-write
+            
+            
+              TX_BCK_DIV_NUM
+              Bit clock configuration bits in transmitter mode.
+              7
+              6
+              read-write
+            
+            
+              TX_BITS_MOD
+              Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
+              13
+              5
+              read-write
+            
+            
+              TX_HALF_SAMPLE_BITS
+              I2S Tx half sample bits -1.
+              18
+              6
+              read-write
+            
+            
+              TX_TDM_CHAN_BITS
+              The Tx bit number for each channel minus 1in TDM mode.
+              24
+              5
+              read-write
+            
+            
+              TX_MSB_SHIFT
+              Set this bit to enable transmitter in Phillips standard mode
+              29
+              1
+              read-write
+            
+            
+              TX_BCK_NO_DLY
+              1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.
+              30
+              1
+              read-write
+            
+          
+        
+        
+          RX_CLKM_CONF
+          I2S RX clock configure register
+          0x30
+          0x20
+          0x00000002
+          
+            
+              RX_CLKM_DIV_NUM
+              Integral I2S clock divider value
+              0
+              8
+              read-write
+            
+            
+              RX_CLK_ACTIVE
+              I2S Rx module clock enable signal.
+              26
+              1
+              read-write
+            
+            
+              RX_CLK_SEL
+              Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+              27
+              2
+              read-write
+            
+            
+              MCLK_SEL
+              0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.
+              29
+              1
+              read-write
+            
+          
+        
+        
+          TX_CLKM_CONF
+          I2S TX clock configure register
+          0x34
+          0x20
+          0x00000002
+          
+            
+              TX_CLKM_DIV_NUM
+              Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.
+              0
+              8
+              read-write
+            
+            
+              TX_CLK_ACTIVE
+              I2S Tx module clock enable signal.
+              26
+              1
+              read-write
+            
+            
+              TX_CLK_SEL
+              Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+              27
+              2
+              read-write
+            
+            
+              CLK_EN
+              Set this bit to enable clk gate
+              29
+              1
+              read-write
+            
+          
+        
+        
+          RX_CLKM_DIV_CONF
+          I2S RX module clock divider configure register
+          0x38
+          0x20
+          0x00000200
+          
+            
+              RX_CLKM_DIV_Z
+              For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).
+              0
+              9
+              read-write
+            
+            
+              RX_CLKM_DIV_Y
+              For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+              9
+              9
+              read-write
+            
+            
+              RX_CLKM_DIV_X
+              For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+              18
+              9
+              read-write
+            
+            
+              RX_CLKM_DIV_YN1
+              For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.
+              27
+              1
+              read-write
+            
+          
+        
+        
+          TX_CLKM_DIV_CONF
+          I2S TX module clock divider configure register
+          0x3C
+          0x20
+          0x00000200
+          
+            
+              TX_CLKM_DIV_Z
+              For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).
+              0
+              9
+              read-write
+            
+            
+              TX_CLKM_DIV_Y
+              For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+              9
+              9
+              read-write
+            
+            
+              TX_CLKM_DIV_X
+              For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+              18
+              9
+              read-write
+            
+            
+              TX_CLKM_DIV_YN1
+              For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.
+              27
+              1
+              read-write
+            
+          
+        
+        
+          TX_PCM2PDM_CONF
+          I2S TX PCM2PDM configuration register
+          0x40
+          0x20
+          0x004AA004
+          
+            
+              TX_PDM_HP_BYPASS
+              I2S TX PDM bypass hp filter or not. The option has been removed.
+              0
+              1
+              read-write
+            
+            
+              TX_PDM_SINC_OSR2
+              I2S TX PDM OSR2 value
+              1
+              4
+              read-write
+            
+            
+              TX_PDM_PRESCALE
+              I2S TX PDM prescale for sigmadelta
+              5
+              8
+              read-write
+            
+            
+              TX_PDM_HP_IN_SHIFT
+              I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+              13
+              2
+              read-write
+            
+            
+              TX_PDM_LP_IN_SHIFT
+              I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+              15
+              2
+              read-write
+            
+            
+              TX_PDM_SINC_IN_SHIFT
+              I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+              17
+              2
+              read-write
+            
+            
+              TX_PDM_SIGMADELTA_IN_SHIFT
+              I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+              19
+              2
+              read-write
+            
+            
+              TX_PDM_SIGMADELTA_DITHER2
+              I2S TX PDM sigmadelta dither2 value
+              21
+              1
+              read-write
+            
+            
+              TX_PDM_SIGMADELTA_DITHER
+              I2S TX PDM sigmadelta dither value
+              22
+              1
+              read-write
+            
+            
+              TX_PDM_DAC_2OUT_EN
+              I2S TX PDM dac mode enable
+              23
+              1
+              read-write
+            
+            
+              TX_PDM_DAC_MODE_EN
+              I2S TX PDM dac 2channel enable
+              24
+              1
+              read-write
+            
+            
+              PCM2PDM_CONV_EN
+              I2S TX PDM Converter enable
+              25
+              1
+              read-write
+            
+          
+        
+        
+          TX_PCM2PDM_CONF1
+          I2S TX PCM2PDM configuration register
+          0x44
+          0x20
+          0x03F783C0
+          
+            
+              TX_PDM_FP
+              I2S TX PDM Fp
+              0
+              10
+              read-write
+            
+            
+              TX_PDM_FS
+              I2S TX PDM Fs
+              10
+              10
+              read-write
+            
+            
+              TX_IIR_HP_MULT12_5
+              The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])
+              20
+              3
+              read-write
+            
+            
+              TX_IIR_HP_MULT12_0
+              The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])
+              23
+              3
+              read-write
+            
+          
+        
+        
+          RX_TDM_CTRL
+          I2S TX TDM mode control register
+          0x50
+          0x20
+          0x0000FFFF
+          
+            
+              RX_TDM_PDM_CHAN0_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0:  Disable, just input 0 in this channel.
+              0
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN1_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0:  Disable, just input 0 in this channel.
+              1
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN2_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0:  Disable, just input 0 in this channel.
+              2
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN3_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0:  Disable, just input 0 in this channel.
+              3
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN4_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0:  Disable, just input 0 in this channel.
+              4
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN5_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0:  Disable, just input 0 in this channel.
+              5
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN6_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0:  Disable, just input 0 in this channel.
+              6
+              1
+              read-write
+            
+            
+              RX_TDM_PDM_CHAN7_EN
+              1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0:  Disable, just input 0 in this channel.
+              7
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN8_EN
+              1: Enable the valid data input of I2S RX TDM channel 8. 0:  Disable, just input 0 in this channel.
+              8
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN9_EN
+              1: Enable the valid data input of I2S RX TDM channel 9. 0:  Disable, just input 0 in this channel.
+              9
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN10_EN
+              1: Enable the valid data input of I2S RX TDM channel 10. 0:  Disable, just input 0 in this channel.
+              10
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN11_EN
+              1: Enable the valid data input of I2S RX TDM channel 11. 0:  Disable, just input 0 in this channel.
+              11
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN12_EN
+              1: Enable the valid data input of I2S RX TDM channel 12. 0:  Disable, just input 0 in this channel.
+              12
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN13_EN
+              1: Enable the valid data input of I2S RX TDM channel 13. 0:  Disable, just input 0 in this channel.
+              13
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN14_EN
+              1: Enable the valid data input of I2S RX TDM channel 14. 0:  Disable, just input 0 in this channel.
+              14
+              1
+              read-write
+            
+            
+              RX_TDM_CHAN15_EN
+              1: Enable the valid data input of I2S RX TDM channel 15. 0:  Disable, just input 0 in this channel.
+              15
+              1
+              read-write
+            
+            
+              RX_TDM_TOT_CHAN_NUM
+              The total channel number of I2S TX TDM mode.
+              16
+              4
+              read-write
+            
+          
+        
+        
+          TX_TDM_CTRL
+          I2S TX TDM mode control register
+          0x54
+          0x20
+          0x0000FFFF
+          
+            
+              TX_TDM_CHAN0_EN
+              1: Enable the valid data output of I2S TX TDM channel 0. 0:  Disable, just output 0 in this channel.
+              0
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN1_EN
+              1: Enable the valid data output of I2S TX TDM channel 1. 0:  Disable, just output 0 in this channel.
+              1
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN2_EN
+              1: Enable the valid data output of I2S TX TDM channel 2. 0:  Disable, just output 0 in this channel.
+              2
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN3_EN
+              1: Enable the valid data output of I2S TX TDM channel 3. 0:  Disable, just output 0 in this channel.
+              3
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN4_EN
+              1: Enable the valid data output of I2S TX TDM channel 4. 0:  Disable, just output 0 in this channel.
+              4
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN5_EN
+              1: Enable the valid data output of I2S TX TDM channel 5. 0:  Disable, just output 0 in this channel.
+              5
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN6_EN
+              1: Enable the valid data output of I2S TX TDM channel 6. 0:  Disable, just output 0 in this channel.
+              6
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN7_EN
+              1: Enable the valid data output of I2S TX TDM channel 7. 0:  Disable, just output 0 in this channel.
+              7
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN8_EN
+              1: Enable the valid data output of I2S TX TDM channel 8. 0:  Disable, just output 0 in this channel.
+              8
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN9_EN
+              1: Enable the valid data output of I2S TX TDM channel 9. 0:  Disable, just output 0 in this channel.
+              9
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN10_EN
+              1: Enable the valid data output of I2S TX TDM channel 10. 0:  Disable, just output 0 in this channel.
+              10
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN11_EN
+              1: Enable the valid data output of I2S TX TDM channel 11. 0:  Disable, just output 0 in this channel.
+              11
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN12_EN
+              1: Enable the valid data output of I2S TX TDM channel 12. 0:  Disable, just output 0 in this channel.
+              12
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN13_EN
+              1: Enable the valid data output of I2S TX TDM channel 13. 0:  Disable, just output 0 in this channel.
+              13
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN14_EN
+              1: Enable the valid data output of I2S TX TDM channel 14. 0:  Disable, just output 0 in this channel.
+              14
+              1
+              read-write
+            
+            
+              TX_TDM_CHAN15_EN
+              1: Enable the valid data output of I2S TX TDM channel 15. 0:  Disable, just output 0 in this channel.
+              15
+              1
+              read-write
+            
+            
+              TX_TDM_TOT_CHAN_NUM
+              The total channel number of I2S TX TDM mode.
+              16
+              4
+              read-write
+            
+            
+              TX_TDM_SKIP_MSK_EN
+              When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.
+              20
+              1
+              read-write
+            
+          
+        
+        
+          RX_TIMING
+          I2S RX timing control register
+          0x58
+          0x20
+          
+            
+              RX_SD_IN_DM
+              The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              0
+              2
+              read-write
+            
+            
+              RX_WS_OUT_DM
+              The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              16
+              2
+              read-write
+            
+            
+              RX_BCK_OUT_DM
+              The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              20
+              2
+              read-write
+            
+            
+              RX_WS_IN_DM
+              The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              24
+              2
+              read-write
+            
+            
+              RX_BCK_IN_DM
+              The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              28
+              2
+              read-write
+            
+          
+        
+        
+          TX_TIMING
+          I2S TX timing control register
+          0x5C
+          0x20
+          
+            
+              TX_SD_OUT_DM
+              The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              0
+              2
+              read-write
+            
+            
+              TX_SD1_OUT_DM
+              The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              4
+              2
+              read-write
+            
+            
+              TX_WS_OUT_DM
+              The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              16
+              2
+              read-write
+            
+            
+              TX_BCK_OUT_DM
+              The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              20
+              2
+              read-write
+            
+            
+              TX_WS_IN_DM
+              The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              24
+              2
+              read-write
+            
+            
+              TX_BCK_IN_DM
+              The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.
+              28
+              2
+              read-write
+            
+          
+        
+        
+          LC_HUNG_CONF
+          I2S HUNG configure register.
+          0x60
+          0x20
+          0x00000810
+          
+            
+              LC_FIFO_TIMEOUT
+              the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value
+              0
+              8
+              read-write
+            
+            
+              LC_FIFO_TIMEOUT_SHIFT
+              The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+              8
+              3
+              read-write
+            
+            
+              LC_FIFO_TIMEOUT_ENA
+              The enable bit for FIFO timeout
+              11
+              1
+              read-write
+            
+          
+        
+        
+          RXEOF_NUM
+          I2S RX data number control register.
+          0x64
+          0x20
+          0x00000040
+          
+            
+              RX_EOF_NUM
+              The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+              0
+              12
+              read-write
+            
+          
+        
+        
+          CONF_SIGLE_DATA
+          I2S signal data register
+          0x68
+          0x20
+          
+            
+              SINGLE_DATA
+              The configured constant channel data to be sent out.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STATE
+          I2S TX status register
+          0x6C
+          0x20
+          0x00000001
+          
+            
+              TX_IDLE
+              1: i2s_tx is idle state. 0: i2s_tx is working.
+              0
+              1
+              read-only
+            
+          
+        
+        
+          DATE
+          Version control register
+          0x80
+          0x20
+          0x02007220
+          
+            
+              DATE
+              I2S version control register
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      INTERRUPT_CORE0
+      Interrupt Core
+      INTERRUPT_CORE0
+      0x600C2000
+      
+        0x0
+        0x19C
+        registers
+      
+      
+        
+          MAC_INTR_MAP
+          mac intr map register
+          0x0
+          0x20
+          
+            
+              MAC_INTR_MAP
+              core0_mac_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          MAC_NMI_MAP
+          mac nmi_intr map register
+          0x4
+          0x20
+          
+            
+              MAC_NMI_MAP
+              reg_core0_mac_nmi_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          PWR_INTR_MAP
+          pwr intr map register
+          0x8
+          0x20
+          
+            
+              PWR_INTR_MAP
+              reg_core0_pwr_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          BB_INT_MAP
+          bb intr map register
+          0xC
+          0x20
+          
+            
+              BB_INT_MAP
+              reg_core0_bb_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          BT_MAC_INT_MAP
+          bt intr map register
+          0x10
+          0x20
+          
+            
+              BT_MAC_INT_MAP
+              reg_core0_bt_mac_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          BT_BB_INT_MAP
+          bb_bt intr map register
+          0x14
+          0x20
+          
+            
+              BT_BB_INT_MAP
+              reg_core0_bt_bb_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          BT_BB_NMI_MAP
+          bb_bt_nmi intr map register
+          0x18
+          0x20
+          
+            
+              BT_BB_NMI_MAP
+              reg_core0_bt_bb_nmi_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RWBT_IRQ_MAP
+          rwbt intr map register
+          0x1C
+          0x20
+          
+            
+              RWBT_IRQ_MAP
+              reg_core0_rwbt_irq_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RWBLE_IRQ_MAP
+          rwble intr map register
+          0x20
+          0x20
+          
+            
+              RWBLE_IRQ_MAP
+              reg_core0_rwble_irq_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RWBT_NMI_MAP
+          rwbt_nmi intr map register
+          0x24
+          0x20
+          
+            
+              RWBT_NMI_MAP
+              reg_core0_rwbt_nmi_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RWBLE_NMI_MAP
+          rwble_nmi intr map register
+          0x28
+          0x20
+          
+            
+              RWBLE_NMI_MAP
+              reg_core0_rwble_nmi_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          I2C_MST_INT_MAP
+          i2c intr map register
+          0x2C
+          0x20
+          
+            
+              I2C_MST_INT_MAP
+              reg_core0_i2c_mst_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SLC0_INTR_MAP
+          slc0 intr map register
+          0x30
+          0x20
+          
+            
+              SLC0_INTR_MAP
+              reg_core0_slc0_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SLC1_INTR_MAP
+          slc1 intr map register
+          0x34
+          0x20
+          
+            
+              SLC1_INTR_MAP
+              reg_core0_slc1_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          APB_CTRL_INTR_MAP
+          apb_ctrl intr map register
+          0x38
+          0x20
+          
+            
+              APB_CTRL_INTR_MAP
+              reg_core0_apb_ctrl_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          UHCI0_INTR_MAP
+          uchi0 intr map register
+          0x3C
+          0x20
+          
+            
+              UHCI0_INTR_MAP
+              reg_core0_uhci0_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          GPIO_INTERRUPT_PRO_MAP
+          gpio intr map register
+          0x40
+          0x20
+          
+            
+              GPIO_INTERRUPT_PRO_MAP
+              reg_core0_gpio_interrupt_pro_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          GPIO_INTERRUPT_PRO_NMI_MAP
+          gpio_pro intr map register
+          0x44
+          0x20
+          
+            
+              GPIO_INTERRUPT_PRO_NMI_MAP
+              reg_core0_gpio_interrupt_pro_nmi_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SPI_INTR_1_MAP
+          gpio_pro_nmi intr map register
+          0x48
+          0x20
+          
+            
+              SPI_INTR_1_MAP
+              reg_core0_spi_intr_1_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SPI_INTR_2_MAP
+          spi1 intr map register
+          0x4C
+          0x20
+          
+            
+              SPI_INTR_2_MAP
+              reg_core0_spi_intr_2_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          I2S1_INT_MAP
+          spi2 intr map register
+          0x50
+          0x20
+          
+            
+              I2S1_INT_MAP
+              reg_core0_i2s1_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          UART_INTR_MAP
+          i2s1 intr map register
+          0x54
+          0x20
+          
+            
+              UART_INTR_MAP
+              reg_core0_uart_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          UART1_INTR_MAP
+          uart1 intr map register
+          0x58
+          0x20
+          
+            
+              UART1_INTR_MAP
+              reg_core0_uart1_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          LEDC_INT_MAP
+          ledc intr map register
+          0x5C
+          0x20
+          
+            
+              LEDC_INT_MAP
+              reg_core0_ledc_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          EFUSE_INT_MAP
+          efuse intr map register
+          0x60
+          0x20
+          
+            
+              EFUSE_INT_MAP
+              reg_core0_efuse_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CAN_INT_MAP
+          can intr map register
+          0x64
+          0x20
+          
+            
+              CAN_INT_MAP
+              reg_core0_can_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          USB_INTR_MAP
+          usb intr map register
+          0x68
+          0x20
+          
+            
+              USB_INTR_MAP
+              reg_core0_usb_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RTC_CORE_INTR_MAP
+          rtc intr map register
+          0x6C
+          0x20
+          
+            
+              RTC_CORE_INTR_MAP
+              reg_core0_rtc_core_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RMT_INTR_MAP
+          rmt intr map register
+          0x70
+          0x20
+          
+            
+              RMT_INTR_MAP
+              reg_core0_rmt_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          I2C_EXT0_INTR_MAP
+          i2c intr map register
+          0x74
+          0x20
+          
+            
+              I2C_EXT0_INTR_MAP
+              reg_core0_i2c_ext0_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TIMER_INT1_MAP
+          timer1 intr map register
+          0x78
+          0x20
+          
+            
+              TIMER_INT1_MAP
+              reg_core0_timer_int1_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TIMER_INT2_MAP
+          timer2 intr map register
+          0x7C
+          0x20
+          
+            
+              TIMER_INT2_MAP
+              reg_core0_timer_int2_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TG_T0_INT_MAP
+          tg to intr map register
+          0x80
+          0x20
+          
+            
+              TG_T0_INT_MAP
+              reg_core0_tg_t0_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TG_WDT_INT_MAP
+          tg wdt intr map register
+          0x84
+          0x20
+          
+            
+              TG_WDT_INT_MAP
+              reg_core0_tg_wdt_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TG1_T0_INT_MAP
+          tg1 to intr map register
+          0x88
+          0x20
+          
+            
+              TG1_T0_INT_MAP
+              reg_core0_tg1_t0_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          TG1_WDT_INT_MAP
+          tg1 wdt intr map register
+          0x8C
+          0x20
+          
+            
+              TG1_WDT_INT_MAP
+              reg_core0_tg1_wdt_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CACHE_IA_INT_MAP
+          cache ia intr map register
+          0x90
+          0x20
+          
+            
+              CACHE_IA_INT_MAP
+              reg_core0_cache_ia_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SYSTIMER_TARGET0_INT_MAP
+          systimer intr map register
+          0x94
+          0x20
+          
+            
+              SYSTIMER_TARGET0_INT_MAP
+              reg_core0_systimer_target0_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SYSTIMER_TARGET1_INT_MAP
+          systimer target1 intr map register
+          0x98
+          0x20
+          
+            
+              SYSTIMER_TARGET1_INT_MAP
+              reg_core0_systimer_target1_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SYSTIMER_TARGET2_INT_MAP
+          systimer target2 intr map register
+          0x9C
+          0x20
+          
+            
+              SYSTIMER_TARGET2_INT_MAP
+              reg_core0_systimer_target2_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SPI_MEM_REJECT_INTR_MAP
+          spi mem reject intr map register
+          0xA0
+          0x20
+          
+            
+              SPI_MEM_REJECT_INTR_MAP
+              reg_core0_spi_mem_reject_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          ICACHE_PRELOAD_INT_MAP
+          icache perload intr map register
+          0xA4
+          0x20
+          
+            
+              ICACHE_PRELOAD_INT_MAP
+              reg_core0_icache_preload_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          ICACHE_SYNC_INT_MAP
+          icache sync intr map register
+          0xA8
+          0x20
+          
+            
+              ICACHE_SYNC_INT_MAP
+              reg_core0_icache_sync_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          APB_ADC_INT_MAP
+          adc intr map register
+          0xAC
+          0x20
+          
+            
+              APB_ADC_INT_MAP
+              reg_core0_apb_adc_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          DMA_CH0_INT_MAP
+          dma ch0 intr map register
+          0xB0
+          0x20
+          
+            
+              DMA_CH0_INT_MAP
+              reg_core0_dma_ch0_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          DMA_CH1_INT_MAP
+          dma ch1 intr map register
+          0xB4
+          0x20
+          
+            
+              DMA_CH1_INT_MAP
+              reg_core0_dma_ch1_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          DMA_CH2_INT_MAP
+          dma ch2 intr map register
+          0xB8
+          0x20
+          
+            
+              DMA_CH2_INT_MAP
+              reg_core0_dma_ch2_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          RSA_INT_MAP
+          rsa intr map register
+          0xBC
+          0x20
+          
+            
+              RSA_INT_MAP
+              reg_core0_rsa_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          AES_INT_MAP
+          aes intr map register
+          0xC0
+          0x20
+          
+            
+              AES_INT_MAP
+              reg_core0_aes_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          SHA_INT_MAP
+          sha intr map register
+          0xC4
+          0x20
+          
+            
+              SHA_INT_MAP
+              reg_core0_sha_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_0_MAP
+          cpu from cpu 0 intr map register
+          0xC8
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_0_MAP
+              reg_core0_cpu_intr_from_cpu_0_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_1_MAP
+          cpu from cpu 0 intr map register
+          0xCC
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_1_MAP
+              reg_core0_cpu_intr_from_cpu_1_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_2_MAP
+          cpu from cpu 1 intr map register
+          0xD0
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_2_MAP
+              reg_core0_cpu_intr_from_cpu_2_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_3_MAP
+          cpu from cpu 3 intr map register
+          0xD4
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_3_MAP
+              reg_core0_cpu_intr_from_cpu_3_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          ASSIST_DEBUG_INTR_MAP
+          assist debug intr map register
+          0xD8
+          0x20
+          
+            
+              ASSIST_DEBUG_INTR_MAP
+              reg_core0_assist_debug_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP
+          dma pms violatile intr map register
+          0xDC
+          0x20
+          
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP
+              reg_core0_dma_apbperi_pms_monitor_violate_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP
+          iram0 pms violatile intr map register
+          0xE0
+          0x20
+          
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP
+              reg_core0_core_0_iram0_pms_monitor_violate_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP
+          mac intr map register
+          0xE4
+          0x20
+          
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP
+              reg_core0_core_0_dram0_pms_monitor_violate_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP
+          mac intr map register
+          0xE8
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP
+              reg_core0_core_0_pif_pms_monitor_violate_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP
+          mac intr map register
+          0xEC
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP
+              reg_core0_core_0_pif_pms_monitor_violate_size_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          BACKUP_PMS_VIOLATE_INTR_MAP
+          mac intr map register
+          0xF0
+          0x20
+          
+            
+              BACKUP_PMS_VIOLATE_INTR_MAP
+              reg_core0_backup_pms_violate_intr_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          CACHE_CORE0_ACS_INT_MAP
+          mac intr map register
+          0xF4
+          0x20
+          
+            
+              CACHE_CORE0_ACS_INT_MAP
+              reg_core0_cache_core0_acs_int_map
+              0
+              5
+              read-write
+            
+          
+        
+        
+          INTR_STATUS_REG_0
+          mac intr map register
+          0xF8
+          0x20
+          
+            
+              INTR_STATUS_0
+              reg_core0_intr_status_0
+              0
+              32
+              read-only
+            
+          
+        
+        
+          INTR_STATUS_REG_1
+          mac intr map register
+          0xFC
+          0x20
+          
+            
+              INTR_STATUS_1
+              reg_core0_intr_status_1
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CLOCK_GATE
+          mac intr map register
+          0x100
+          0x20
+          0x00000001
+          
+            
+              REG_CLK_EN
+              reg_core0_reg_clk_en
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CPU_INT_ENABLE
+          mac intr map register
+          0x104
+          0x20
+          
+            
+              CPU_INT_ENABLE
+              reg_core0_cpu_int_enable
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CPU_INT_TYPE
+          mac intr map register
+          0x108
+          0x20
+          
+            
+              CPU_INT_TYPE
+              reg_core0_cpu_int_type
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CPU_INT_CLEAR
+          mac intr map register
+          0x10C
+          0x20
+          
+            
+              CPU_INT_CLEAR
+              reg_core0_cpu_int_clear
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CPU_INT_EIP_STATUS
+          mac intr map register
+          0x110
+          0x20
+          
+            
+              CPU_INT_EIP_STATUS
+              reg_core0_cpu_int_eip_status
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CPU_INT_PRI_0
+          mac intr map register
+          0x114
+          0x20
+          
+            
+              CPU_PRI_0_MAP
+              reg_core0_cpu_pri_0_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_1
+          mac intr map register
+          0x118
+          0x20
+          
+            
+              CPU_PRI_1_MAP
+              reg_core0_cpu_pri_1_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_2
+          mac intr map register
+          0x11C
+          0x20
+          
+            
+              CPU_PRI_2_MAP
+              reg_core0_cpu_pri_2_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_3
+          mac intr map register
+          0x120
+          0x20
+          
+            
+              CPU_PRI_3_MAP
+              reg_core0_cpu_pri_3_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_4
+          mac intr map register
+          0x124
+          0x20
+          
+            
+              CPU_PRI_4_MAP
+              reg_core0_cpu_pri_4_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_5
+          mac intr map register
+          0x128
+          0x20
+          
+            
+              CPU_PRI_5_MAP
+              reg_core0_cpu_pri_5_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_6
+          mac intr map register
+          0x12C
+          0x20
+          
+            
+              CPU_PRI_6_MAP
+              reg_core0_cpu_pri_6_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_7
+          mac intr map register
+          0x130
+          0x20
+          
+            
+              CPU_PRI_7_MAP
+              reg_core0_cpu_pri_7_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_8
+          mac intr map register
+          0x134
+          0x20
+          
+            
+              CPU_PRI_8_MAP
+              reg_core0_cpu_pri_8_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_9
+          mac intr map register
+          0x138
+          0x20
+          
+            
+              CPU_PRI_9_MAP
+              reg_core0_cpu_pri_9_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_10
+          mac intr map register
+          0x13C
+          0x20
+          
+            
+              CPU_PRI_10_MAP
+              reg_core0_cpu_pri_10_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_11
+          mac intr map register
+          0x140
+          0x20
+          
+            
+              CPU_PRI_11_MAP
+              reg_core0_cpu_pri_11_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_12
+          mac intr map register
+          0x144
+          0x20
+          
+            
+              CPU_PRI_12_MAP
+              reg_core0_cpu_pri_12_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_13
+          mac intr map register
+          0x148
+          0x20
+          
+            
+              CPU_PRI_13_MAP
+              reg_core0_cpu_pri_13_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_14
+          mac intr map register
+          0x14C
+          0x20
+          
+            
+              CPU_PRI_14_MAP
+              reg_core0_cpu_pri_14_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_15
+          mac intr map register
+          0x150
+          0x20
+          
+            
+              CPU_PRI_15_MAP
+              reg_core0_cpu_pri_15_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_16
+          mac intr map register
+          0x154
+          0x20
+          
+            
+              CPU_PRI_16_MAP
+              reg_core0_cpu_pri_16_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_17
+          mac intr map register
+          0x158
+          0x20
+          
+            
+              CPU_PRI_17_MAP
+              reg_core0_cpu_pri_17_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_18
+          mac intr map register
+          0x15C
+          0x20
+          
+            
+              CPU_PRI_18_MAP
+              reg_core0_cpu_pri_18_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_19
+          mac intr map register
+          0x160
+          0x20
+          
+            
+              CPU_PRI_19_MAP
+              reg_core0_cpu_pri_19_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_20
+          mac intr map register
+          0x164
+          0x20
+          
+            
+              CPU_PRI_20_MAP
+              reg_core0_cpu_pri_20_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_21
+          mac intr map register
+          0x168
+          0x20
+          
+            
+              CPU_PRI_21_MAP
+              reg_core0_cpu_pri_21_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_22
+          mac intr map register
+          0x16C
+          0x20
+          
+            
+              CPU_PRI_22_MAP
+              reg_core0_cpu_pri_22_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_23
+          mac intr map register
+          0x170
+          0x20
+          
+            
+              CPU_PRI_23_MAP
+              reg_core0_cpu_pri_23_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_24
+          mac intr map register
+          0x174
+          0x20
+          
+            
+              CPU_PRI_24_MAP
+              reg_core0_cpu_pri_24_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_25
+          mac intr map register
+          0x178
+          0x20
+          
+            
+              CPU_PRI_25_MAP
+              reg_core0_cpu_pri_25_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_26
+          mac intr map register
+          0x17C
+          0x20
+          
+            
+              CPU_PRI_26_MAP
+              reg_core0_cpu_pri_26_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_27
+          mac intr map register
+          0x180
+          0x20
+          
+            
+              CPU_PRI_27_MAP
+              reg_core0_cpu_pri_27_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_28
+          mac intr map register
+          0x184
+          0x20
+          
+            
+              CPU_PRI_28_MAP
+              reg_core0_cpu_pri_28_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_29
+          mac intr map register
+          0x188
+          0x20
+          
+            
+              CPU_PRI_29_MAP
+              reg_core0_cpu_pri_29_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_30
+          mac intr map register
+          0x18C
+          0x20
+          
+            
+              CPU_PRI_30_MAP
+              reg_core0_cpu_pri_30_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_PRI_31
+          mac intr map register
+          0x190
+          0x20
+          
+            
+              CPU_PRI_31_MAP
+              reg_core0_cpu_pri_31_map
+              0
+              4
+              read-write
+            
+          
+        
+        
+          CPU_INT_THRESH
+          mac intr map register
+          0x194
+          0x20
+          
+            
+              CPU_INT_THRESH
+              reg_core0_cpu_int_thresh
+              0
+              4
+              read-write
+            
+          
+        
+        
+          INTERRUPT_REG_DATE
+          mac intr map register
+          0x7FC
+          0x20
+          0x02007210
+          
+            
+              INTERRUPT_REG_DATE
+              reg_core0_interrupt_reg_date
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      IO_MUX
+      Input/Output Multiplexer
+      IO_MUX
+      0x60009000
+      
+        0x0
+        0x60
+        registers
+      
+      
+        
+          PIN_CTRL
+          Clock Output Configuration Register
+          0x0
+          0x20
+          0x000007FF
+          
+            
+              CLK_OUT1
+              If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.
+              0
+              4
+              read-write
+            
+            
+              CLK_OUT2
+              If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.
+              4
+              4
+              read-write
+            
+            
+              CLK_OUT3
+              If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.
+              8
+              4
+              read-write
+            
+          
+        
+        
+          22
+          0x4
+          GPIO%s
+          IO MUX Configure Register for pad XTAL_32K_P
+          0x4
+          0x20
+          0x00000B00
+          
+            
+              MCU_OE
+              Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+              0
+              1
+              read-write
+            
+            
+              SLP_SEL
+              Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+              1
+              1
+              read-write
+            
+            
+              MCU_WPD
+              Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.
+              2
+              1
+              read-write
+            
+            
+              MCU_WPU
+              Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.
+              3
+              1
+              read-write
+            
+            
+              MCU_IE
+              Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+              4
+              1
+              read-write
+            
+            
+              FUN_WPD
+              Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.
+              7
+              1
+              read-write
+            
+            
+              FUN_WPU
+              Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.
+              8
+              1
+              read-write
+            
+            
+              FUN_IE
+              Input enable of the pad. 1: input enabled; 0: input disabled.
+              9
+              1
+              read-write
+            
+            
+              FUN_DRV
+              Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+              10
+              2
+              read-write
+            
+            
+              MCU_SEL
+              Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.
+              12
+              3
+              read-write
+            
+            
+              FILTER_EN
+              Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+              15
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          IO MUX Version Control Register
+          0xFC
+          0x20
+          0x02006050
+          
+            
+              REG_DATE
+              Version control register
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      LEDC
+      LED Control PWM (Pulse Width Modulation)
+      LEDC
+      0x60019000
+      
+        0x0
+        0xB0
+        registers
+      
+      
+        LEDC
+        23
+      
+      
+        
+          LSCH0_CONF0
+          LEDC_LSCH0_CONF0.
+          0x0
+          0x20
+          
+            
+              TIMER_SEL_LSCH0
+              reg_timer_sel_lsch0.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH0
+              reg_sig_out_en_lsch0.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH0
+              reg_idle_lv_lsch0.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH0
+              reg_para_up_lsch0.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH0
+              reg_ovf_num_lsch0.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH0
+              reg_ovf_cnt_en_lsch0.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH0
+              reg_ovf_cnt_reset_lsch0.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH0_HPOINT
+          LEDC_LSCH0_HPOINT.
+          0x4
+          0x20
+          
+            
+              HPOINT_LSCH0
+              reg_hpoint_lsch0.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH0_DUTY
+          LEDC_LSCH0_DUTY.
+          0x8
+          0x20
+          
+            
+              DUTY_LSCH0
+              reg_duty_lsch0.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH0_CONF1
+          LEDC_LSCH0_CONF1.
+          0xC
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH0
+              reg_duty_scale_lsch0.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH0
+              reg_duty_cycle_lsch0.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH0
+              reg_duty_num_lsch0.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH0
+              reg_duty_inc_lsch0.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH0
+              reg_duty_start_lsch0.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH0_DUTY_R
+          LEDC_LSCH0_DUTY_R.
+          0x10
+          0x20
+          
+            
+              DUTY_LSCH0_R
+              reg_duty_lsch0_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSCH1_CONF0
+          LEDC_LSCH1_CONF0.
+          0x14
+          0x20
+          
+            
+              TIMER_SEL_LSCH1
+              reg_timer_sel_lsch1.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH1
+              reg_sig_out_en_lsch1.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH1
+              reg_idle_lv_lsch1.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH1
+              reg_para_up_lsch1.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH1
+              reg_ovf_num_lsch1.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH1
+              reg_ovf_cnt_en_lsch1.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH1
+              reg_ovf_cnt_reset_lsch1.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH1_HPOINT
+          LEDC_LSCH1_HPOINT.
+          0x18
+          0x20
+          
+            
+              HPOINT_LSCH1
+              reg_hpoint_lsch1.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH1_DUTY
+          LEDC_LSCH1_DUTY.
+          0x1C
+          0x20
+          
+            
+              DUTY_LSCH1
+              reg_duty_lsch1.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH1_CONF1
+          LEDC_LSCH1_CONF1.
+          0x20
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH1
+              reg_duty_scale_lsch1.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH1
+              reg_duty_cycle_lsch1.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH1
+              reg_duty_num_lsch1.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH1
+              reg_duty_inc_lsch1.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH1
+              reg_duty_start_lsch1.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH1_DUTY_R
+          LEDC_LSCH1_DUTY_R.
+          0x24
+          0x20
+          
+            
+              DUTY_LSCH1_R
+              reg_duty_lsch1_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSCH2_CONF0
+          LEDC_LSCH2_CONF0.
+          0x28
+          0x20
+          
+            
+              TIMER_SEL_LSCH2
+              reg_timer_sel_lsch2.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH2
+              reg_sig_out_en_lsch2.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH2
+              reg_idle_lv_lsch2.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH2
+              reg_para_up_lsch2.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH2
+              reg_ovf_num_lsch2.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH2
+              reg_ovf_cnt_en_lsch2.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH2
+              reg_ovf_cnt_reset_lsch2.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH2_HPOINT
+          LEDC_LSCH2_HPOINT.
+          0x2C
+          0x20
+          
+            
+              HPOINT_LSCH2
+              reg_hpoint_lsch2.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH2_DUTY
+          LEDC_LSCH2_DUTY.
+          0x30
+          0x20
+          
+            
+              DUTY_LSCH2
+              reg_duty_lsch2.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH2_CONF1
+          LEDC_LSCH2_CONF1.
+          0x34
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH2
+              reg_duty_scale_lsch2.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH2
+              reg_duty_cycle_lsch2.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH2
+              reg_duty_num_lsch2.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH2
+              reg_duty_inc_lsch2.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH2
+              reg_duty_start_lsch2.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH2_DUTY_R
+          LEDC_LSCH2_DUTY_R.
+          0x38
+          0x20
+          
+            
+              DUTY_LSCH2_R
+              reg_duty_lsch2_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSCH3_CONF0
+          LEDC_LSCH3_CONF0.
+          0x3C
+          0x20
+          
+            
+              TIMER_SEL_LSCH3
+              reg_timer_sel_lsch3.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH3
+              reg_sig_out_en_lsch3.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH3
+              reg_idle_lv_lsch3.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH3
+              reg_para_up_lsch3.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH3
+              reg_ovf_num_lsch3.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH3
+              reg_ovf_cnt_en_lsch3.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH3
+              reg_ovf_cnt_reset_lsch3.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH3_HPOINT
+          LEDC_LSCH3_HPOINT.
+          0x40
+          0x20
+          
+            
+              HPOINT_LSCH3
+              reg_hpoint_lsch3.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH3_DUTY
+          LEDC_LSCH3_DUTY.
+          0x44
+          0x20
+          
+            
+              DUTY_LSCH3
+              reg_duty_lsch3.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH3_CONF1
+          LEDC_LSCH3_CONF1.
+          0x48
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH3
+              reg_duty_scale_lsch3.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH3
+              reg_duty_cycle_lsch3.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH3
+              reg_duty_num_lsch3.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH3
+              reg_duty_inc_lsch3.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH3
+              reg_duty_start_lsch3.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH3_DUTY_R
+          LEDC_LSCH3_DUTY_R.
+          0x4C
+          0x20
+          
+            
+              DUTY_LSCH3_R
+              reg_duty_lsch3_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSCH4_CONF0
+          LEDC_LSCH4_CONF0.
+          0x50
+          0x20
+          
+            
+              TIMER_SEL_LSCH4
+              reg_timer_sel_lsch4.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH4
+              reg_sig_out_en_lsch4.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH4
+              reg_idle_lv_lsch4.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH4
+              reg_para_up_lsch4.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH4
+              reg_ovf_num_lsch4.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH4
+              reg_ovf_cnt_en_lsch4.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH4
+              reg_ovf_cnt_reset_lsch4.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH4_HPOINT
+          LEDC_LSCH4_HPOINT.
+          0x54
+          0x20
+          
+            
+              HPOINT_LSCH4
+              reg_hpoint_lsch4.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH4_DUTY
+          LEDC_LSCH4_DUTY.
+          0x58
+          0x20
+          
+            
+              DUTY_LSCH4
+              reg_duty_lsch4.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH4_CONF1
+          LEDC_LSCH4_CONF1.
+          0x5C
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH4
+              reg_duty_scale_lsch4.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH4
+              reg_duty_cycle_lsch4.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH4
+              reg_duty_num_lsch4.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH4
+              reg_duty_inc_lsch4.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH4
+              reg_duty_start_lsch4.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH4_DUTY_R
+          LEDC_LSCH4_DUTY_R.
+          0x60
+          0x20
+          
+            
+              DUTY_LSCH4_R
+              reg_duty_lsch4_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSCH5_CONF0
+          LEDC_LSCH5_CONF0.
+          0x64
+          0x20
+          
+            
+              TIMER_SEL_LSCH5
+              reg_timer_sel_lsch5.
+              0
+              2
+              read-write
+            
+            
+              SIG_OUT_EN_LSCH5
+              reg_sig_out_en_lsch5.
+              2
+              1
+              read-write
+            
+            
+              IDLE_LV_LSCH5
+              reg_idle_lv_lsch5.
+              3
+              1
+              read-write
+            
+            
+              PARA_UP_LSCH5
+              reg_para_up_lsch5.
+              4
+              1
+              write-only
+            
+            
+              OVF_NUM_LSCH5
+              reg_ovf_num_lsch5.
+              5
+              10
+              read-write
+            
+            
+              OVF_CNT_EN_LSCH5
+              reg_ovf_cnt_en_lsch5.
+              15
+              1
+              read-write
+            
+            
+              OVF_CNT_RESET_LSCH5
+              reg_ovf_cnt_reset_lsch5.
+              16
+              1
+              write-only
+            
+          
+        
+        
+          LSCH5_HPOINT
+          LEDC_LSCH5_HPOINT.
+          0x68
+          0x20
+          
+            
+              HPOINT_LSCH5
+              reg_hpoint_lsch5.
+              0
+              14
+              read-write
+            
+          
+        
+        
+          LSCH5_DUTY
+          LEDC_LSCH5_DUTY.
+          0x6C
+          0x20
+          
+            
+              DUTY_LSCH5
+              reg_duty_lsch5.
+              0
+              19
+              read-write
+            
+          
+        
+        
+          LSCH5_CONF1
+          LEDC_LSCH5_CONF1.
+          0x70
+          0x20
+          0x40000000
+          
+            
+              DUTY_SCALE_LSCH5
+              reg_duty_scale_lsch5.
+              0
+              10
+              read-write
+            
+            
+              DUTY_CYCLE_LSCH5
+              reg_duty_cycle_lsch5.
+              10
+              10
+              read-write
+            
+            
+              DUTY_NUM_LSCH5
+              reg_duty_num_lsch5.
+              20
+              10
+              read-write
+            
+            
+              DUTY_INC_LSCH5
+              reg_duty_inc_lsch5.
+              30
+              1
+              read-write
+            
+            
+              DUTY_START_LSCH5
+              reg_duty_start_lsch5.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          LSCH5_DUTY_R
+          LEDC_LSCH5_DUTY_R.
+          0x74
+          0x20
+          
+            
+              DUTY_LSCH5_R
+              reg_duty_lsch5_r.
+              0
+              19
+              read-only
+            
+          
+        
+        
+          LSTIMER0_CONF
+          LEDC_LSTIMER0_CONF.
+          0xA0
+          0x20
+          0x00800000
+          
+            
+              LSTIMER0_DUTY_RES
+              reg_lstimer0_duty_res.
+              0
+              4
+              read-write
+            
+            
+              CLK_DIV_LSTIMER0
+              reg_clk_div_lstimer0.
+              4
+              18
+              read-write
+            
+            
+              LSTIMER0_PAUSE
+              reg_lstimer0_pause.
+              22
+              1
+              read-write
+            
+            
+              LSTIMER0_RST
+              reg_lstimer0_rst.
+              23
+              1
+              read-write
+            
+            
+              TICK_SEL_LSTIMER0
+              reg_tick_sel_lstimer0.
+              24
+              1
+              read-write
+            
+            
+              LSTIMER0_PARA_UP
+              reg_lstimer0_para_up.
+              25
+              1
+              write-only
+            
+          
+        
+        
+          LSTIMER0_VALUE
+          LEDC_LSTIMER0_VALUE.
+          0xA4
+          0x20
+          
+            
+              LSTIMER0_CNT
+              reg_lstimer0_cnt.
+              0
+              14
+              read-only
+            
+          
+        
+        
+          LSTIMER1_CONF
+          LEDC_LSTIMER1_CONF.
+          0xA8
+          0x20
+          0x00800000
+          
+            
+              LSTIMER1_DUTY_RES
+              reg_lstimer1_duty_res.
+              0
+              4
+              read-write
+            
+            
+              CLK_DIV_LSTIMER1
+              reg_clk_div_lstimer1.
+              4
+              18
+              read-write
+            
+            
+              LSTIMER1_PAUSE
+              reg_lstimer1_pause.
+              22
+              1
+              read-write
+            
+            
+              LSTIMER1_RST
+              reg_lstimer1_rst.
+              23
+              1
+              read-write
+            
+            
+              TICK_SEL_LSTIMER1
+              reg_tick_sel_lstimer1.
+              24
+              1
+              read-write
+            
+            
+              LSTIMER1_PARA_UP
+              reg_lstimer1_para_up.
+              25
+              1
+              write-only
+            
+          
+        
+        
+          LSTIMER1_VALUE
+          LEDC_LSTIMER1_VALUE.
+          0xAC
+          0x20
+          
+            
+              LSTIMER1_CNT
+              reg_lstimer1_cnt.
+              0
+              14
+              read-only
+            
+          
+        
+        
+          LSTIMER2_CONF
+          LEDC_LSTIMER2_CONF.
+          0xB0
+          0x20
+          0x00800000
+          
+            
+              LSTIMER2_DUTY_RES
+              reg_lstimer2_duty_res.
+              0
+              4
+              read-write
+            
+            
+              CLK_DIV_LSTIMER2
+              reg_clk_div_lstimer2.
+              4
+              18
+              read-write
+            
+            
+              LSTIMER2_PAUSE
+              reg_lstimer2_pause.
+              22
+              1
+              read-write
+            
+            
+              LSTIMER2_RST
+              reg_lstimer2_rst.
+              23
+              1
+              read-write
+            
+            
+              TICK_SEL_LSTIMER2
+              reg_tick_sel_lstimer2.
+              24
+              1
+              read-write
+            
+            
+              LSTIMER2_PARA_UP
+              reg_lstimer2_para_up.
+              25
+              1
+              write-only
+            
+          
+        
+        
+          LSTIMER2_VALUE
+          LEDC_LSTIMER2_VALUE.
+          0xB4
+          0x20
+          
+            
+              LSTIMER2_CNT
+              reg_lstimer2_cnt.
+              0
+              14
+              read-only
+            
+          
+        
+        
+          LSTIMER3_CONF
+          LEDC_LSTIMER3_CONF.
+          0xB8
+          0x20
+          0x00800000
+          
+            
+              LSTIMER3_DUTY_RES
+              reg_lstimer3_duty_res.
+              0
+              4
+              read-write
+            
+            
+              CLK_DIV_LSTIMER3
+              reg_clk_div_lstimer3.
+              4
+              18
+              read-write
+            
+            
+              LSTIMER3_PAUSE
+              reg_lstimer3_pause.
+              22
+              1
+              read-write
+            
+            
+              LSTIMER3_RST
+              reg_lstimer3_rst.
+              23
+              1
+              read-write
+            
+            
+              TICK_SEL_LSTIMER3
+              reg_tick_sel_lstimer3.
+              24
+              1
+              read-write
+            
+            
+              LSTIMER3_PARA_UP
+              reg_lstimer3_para_up.
+              25
+              1
+              write-only
+            
+          
+        
+        
+          LSTIMER3_VALUE
+          LEDC_LSTIMER3_VALUE.
+          0xBC
+          0x20
+          
+            
+              LSTIMER3_CNT
+              reg_lstimer3_cnt.
+              0
+              14
+              read-only
+            
+          
+        
+        
+          INT_RAW
+          LEDC_INT_RAW.
+          0xC0
+          0x20
+          
+            
+              LSTIMER0_OVF_INT_RAW
+              reg_lstimer0_ovf_int_raw.
+              0
+              1
+              read-only
+            
+            
+              LSTIMER1_OVF_INT_RAW
+              reg_lstimer1_ovf_int_raw.
+              1
+              1
+              read-only
+            
+            
+              LSTIMER2_OVF_INT_RAW
+              reg_lstimer2_ovf_int_raw.
+              2
+              1
+              read-only
+            
+            
+              LSTIMER3_OVF_INT_RAW
+              reg_lstimer3_ovf_int_raw.
+              3
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH0_INT_RAW
+              reg_duty_chng_end_lsch0_int_raw.
+              4
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH1_INT_RAW
+              reg_duty_chng_end_lsch1_int_raw.
+              5
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH2_INT_RAW
+              reg_duty_chng_end_lsch2_int_raw.
+              6
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH3_INT_RAW
+              reg_duty_chng_end_lsch3_int_raw.
+              7
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH4_INT_RAW
+              reg_duty_chng_end_lsch4_int_raw.
+              8
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH5_INT_RAW
+              reg_duty_chng_end_lsch5_int_raw.
+              9
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH0_INT_RAW
+              reg_ovf_cnt_lsch0_int_raw.
+              10
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH1_INT_RAW
+              reg_ovf_cnt_lsch1_int_raw.
+              11
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH2_INT_RAW
+              reg_ovf_cnt_lsch2_int_raw.
+              12
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH3_INT_RAW
+              reg_ovf_cnt_lsch3_int_raw.
+              13
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH4_INT_RAW
+              reg_ovf_cnt_lsch4_int_raw.
+              14
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH5_INT_RAW
+              reg_ovf_cnt_lsch5_int_raw.
+              15
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          LEDC_INT_ST.
+          0xC4
+          0x20
+          
+            
+              LSTIMER0_OVF_INT_ST
+              reg_lstimer0_ovf_int_st.
+              0
+              1
+              read-only
+            
+            
+              LSTIMER1_OVF_INT_ST
+              reg_lstimer1_ovf_int_st.
+              1
+              1
+              read-only
+            
+            
+              LSTIMER2_OVF_INT_ST
+              reg_lstimer2_ovf_int_st.
+              2
+              1
+              read-only
+            
+            
+              LSTIMER3_OVF_INT_ST
+              reg_lstimer3_ovf_int_st.
+              3
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH0_INT_ST
+              reg_duty_chng_end_lsch0_int_st.
+              4
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH1_INT_ST
+              reg_duty_chng_end_lsch1_int_st.
+              5
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH2_INT_ST
+              reg_duty_chng_end_lsch2_int_st.
+              6
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH3_INT_ST
+              reg_duty_chng_end_lsch3_int_st.
+              7
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH4_INT_ST
+              reg_duty_chng_end_lsch4_int_st.
+              8
+              1
+              read-only
+            
+            
+              DUTY_CHNG_END_LSCH5_INT_ST
+              reg_duty_chng_end_lsch5_int_st.
+              9
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH0_INT_ST
+              reg_ovf_cnt_lsch0_int_st.
+              10
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH1_INT_ST
+              reg_ovf_cnt_lsch1_int_st.
+              11
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH2_INT_ST
+              reg_ovf_cnt_lsch2_int_st.
+              12
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH3_INT_ST
+              reg_ovf_cnt_lsch3_int_st.
+              13
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH4_INT_ST
+              reg_ovf_cnt_lsch4_int_st.
+              14
+              1
+              read-only
+            
+            
+              OVF_CNT_LSCH5_INT_ST
+              reg_ovf_cnt_lsch5_int_st.
+              15
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          LEDC_INT_ENA.
+          0xC8
+          0x20
+          
+            
+              LSTIMER0_OVF_INT_ENA
+              reg_lstimer0_ovf_int_ena.
+              0
+              1
+              read-write
+            
+            
+              LSTIMER1_OVF_INT_ENA
+              reg_lstimer1_ovf_int_ena.
+              1
+              1
+              read-write
+            
+            
+              LSTIMER2_OVF_INT_ENA
+              reg_lstimer2_ovf_int_ena.
+              2
+              1
+              read-write
+            
+            
+              LSTIMER3_OVF_INT_ENA
+              reg_lstimer3_ovf_int_ena.
+              3
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH0_INT_ENA
+              reg_duty_chng_end_lsch0_int_ena.
+              4
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH1_INT_ENA
+              reg_duty_chng_end_lsch1_int_ena.
+              5
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH2_INT_ENA
+              reg_duty_chng_end_lsch2_int_ena.
+              6
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH3_INT_ENA
+              reg_duty_chng_end_lsch3_int_ena.
+              7
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH4_INT_ENA
+              reg_duty_chng_end_lsch4_int_ena.
+              8
+              1
+              read-write
+            
+            
+              DUTY_CHNG_END_LSCH5_INT_ENA
+              reg_duty_chng_end_lsch5_int_ena.
+              9
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH0_INT_ENA
+              reg_ovf_cnt_lsch0_int_ena.
+              10
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH1_INT_ENA
+              reg_ovf_cnt_lsch1_int_ena.
+              11
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH2_INT_ENA
+              reg_ovf_cnt_lsch2_int_ena.
+              12
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH3_INT_ENA
+              reg_ovf_cnt_lsch3_int_ena.
+              13
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH4_INT_ENA
+              reg_ovf_cnt_lsch4_int_ena.
+              14
+              1
+              read-write
+            
+            
+              OVF_CNT_LSCH5_INT_ENA
+              reg_ovf_cnt_lsch5_int_ena.
+              15
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          LEDC_INT_CLR.
+          0xCC
+          0x20
+          
+            
+              LSTIMER0_OVF_INT_CLR
+              reg_lstimer0_ovf_int_clr.
+              0
+              1
+              write-only
+            
+            
+              LSTIMER1_OVF_INT_CLR
+              reg_lstimer1_ovf_int_clr.
+              1
+              1
+              write-only
+            
+            
+              LSTIMER2_OVF_INT_CLR
+              reg_lstimer2_ovf_int_clr.
+              2
+              1
+              write-only
+            
+            
+              LSTIMER3_OVF_INT_CLR
+              reg_lstimer3_ovf_int_clr.
+              3
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH0_INT_CLR
+              reg_duty_chng_end_lsch0_int_clr.
+              4
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH1_INT_CLR
+              reg_duty_chng_end_lsch1_int_clr.
+              5
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH2_INT_CLR
+              reg_duty_chng_end_lsch2_int_clr.
+              6
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH3_INT_CLR
+              reg_duty_chng_end_lsch3_int_clr.
+              7
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH4_INT_CLR
+              reg_duty_chng_end_lsch4_int_clr.
+              8
+              1
+              write-only
+            
+            
+              DUTY_CHNG_END_LSCH5_INT_CLR
+              reg_duty_chng_end_lsch5_int_clr.
+              9
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH0_INT_CLR
+              reg_ovf_cnt_lsch0_int_clr.
+              10
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH1_INT_CLR
+              reg_ovf_cnt_lsch1_int_clr.
+              11
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH2_INT_CLR
+              reg_ovf_cnt_lsch2_int_clr.
+              12
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH3_INT_CLR
+              reg_ovf_cnt_lsch3_int_clr.
+              13
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH4_INT_CLR
+              reg_ovf_cnt_lsch4_int_clr.
+              14
+              1
+              write-only
+            
+            
+              OVF_CNT_LSCH5_INT_CLR
+              reg_ovf_cnt_lsch5_int_clr.
+              15
+              1
+              write-only
+            
+          
+        
+        
+          CONF
+          LEDC_CONF.
+          0xD0
+          0x20
+          
+            
+              APB_CLK_SEL
+              reg_apb_clk_sel.
+              0
+              2
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          LEDC_DATE.
+          0xFC
+          0x20
+          0x19061700
+          
+            
+              LEDC_DATE
+              reg_ledc_date.
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      RMT
+      Remote Control Peripheral
+      RMT
+      0x60016000
+      
+        0x0
+        0x78
+        registers
+      
+      
+        RMT
+        28
+      
+      
+        
+          CH0DATA
+          RMT_CH0DATA_REG.
+          0x0
+          0x20
+          
+            
+              DATA
+              Reserved.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CH1DATA
+          RMT_CH1DATA_REG.
+          0x4
+          0x20
+          
+            
+              DATA
+              Reserved.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CH2DATA
+          RMT_CH2DATA_REG.
+          0x8
+          0x20
+          
+            
+              DATA
+              Reserved.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CH3DATA
+          RMT_CH3DATA_REG.
+          0xC
+          0x20
+          
+            
+              DATA
+              Reserved.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          2
+          0x4
+          0-1
+          CH%s_TX_CONF0
+          RMT_CH%sCONF%s_REG.
+          0x10
+          0x20
+          0x00710200
+          
+            
+              TX_START
+              reg_tx_start_ch0.
+              0
+              1
+              write-only
+            
+            
+              MEM_RD_RST
+              reg_mem_rd_rst_ch0.
+              1
+              1
+              write-only
+            
+            
+              APB_MEM_RST
+              reg_apb_mem_rst_ch0.
+              2
+              1
+              write-only
+            
+            
+              TX_CONTI_MODE
+              reg_tx_conti_mode_ch0.
+              3
+              1
+              read-write
+            
+            
+              MEM_TX_WRAP_EN
+              reg_mem_tx_wrap_en_ch0.
+              4
+              1
+              read-write
+            
+            
+              IDLE_OUT_LV
+              reg_idle_out_lv_ch0.
+              5
+              1
+              read-write
+            
+            
+              IDLE_OUT_EN
+              reg_idle_out_en_ch0.
+              6
+              1
+              read-write
+            
+            
+              TX_STOP
+              reg_tx_stop_ch0.
+              7
+              1
+              read-write
+            
+            
+              DIV_CNT
+              reg_div_cnt_ch0.
+              8
+              8
+              read-write
+            
+            
+              MEM_SIZE
+              reg_mem_size_ch0.
+              16
+              3
+              read-write
+            
+            
+              CARRIER_EFF_EN
+              reg_carrier_eff_en_ch0.
+              20
+              1
+              read-write
+            
+            
+              CARRIER_EN
+              reg_carrier_en_ch0.
+              21
+              1
+              read-write
+            
+            
+              CARRIER_OUT_LV
+              reg_carrier_out_lv_ch0.
+              22
+              1
+              read-write
+            
+            
+              AFIFO_RST
+              reg_afifo_rst_ch0.
+              23
+              1
+              write-only
+            
+            
+              CONF_UPDATE
+              reg_reg_conf_update_ch0.
+              24
+              1
+              write-only
+            
+          
+        
+        
+          2
+          0x8
+          2-3
+          CH%s_RX_CONF0
+          RMT_CH2CONF0_REG.
+          0x18
+          0x20
+          0x30FFFF02
+          
+            
+              DIV_CNT
+              reg_div_cnt_ch2.
+              0
+              8
+              read-write
+            
+            
+              IDLE_THRES
+              reg_idle_thres_ch2.
+              8
+              15
+              read-write
+            
+            
+              MEM_SIZE
+              reg_mem_size_ch2.
+              23
+              3
+              read-write
+            
+            
+              CARRIER_EN
+              reg_carrier_en_ch2.
+              28
+              1
+              read-write
+            
+            
+              CARRIER_OUT_LV
+              reg_carrier_out_lv_ch2.
+              29
+              1
+              read-write
+            
+          
+        
+        
+          CH2CONF1
+          RMT_CH2CONF1_REG.
+          0x1C
+          0x20
+          0x000001E8
+          
+            
+              RX_EN
+              reg_rx_en_ch2.
+              0
+              1
+              read-write
+            
+            
+              MEM_WR_RST
+              reg_mem_wr_rst_ch2.
+              1
+              1
+              write-only
+            
+            
+              APB_MEM_RST
+              reg_apb_mem_rst_ch2.
+              2
+              1
+              write-only
+            
+            
+              MEM_OWNER
+              reg_mem_owner_ch2.
+              3
+              1
+              read-write
+            
+            
+              RX_FILTER_EN
+              reg_rx_filter_en_ch2.
+              4
+              1
+              read-write
+            
+            
+              RX_FILTER_THRES
+              reg_rx_filter_thres_ch2.
+              5
+              8
+              read-write
+            
+            
+              MEM_RX_WRAP_EN
+              reg_mem_rx_wrap_en_ch2.
+              13
+              1
+              read-write
+            
+            
+              AFIFO_RST
+              reg_afifo_rst_ch2.
+              14
+              1
+              write-only
+            
+            
+              CONF_UPDATE
+              reg_conf_update_ch2.
+              15
+              1
+              write-only
+            
+          
+        
+        
+          CH3CONF1
+          RMT_CH3CONF1_REG.
+          0x24
+          0x20
+          0x000001E8
+          
+            
+              RX_EN
+              reg_rx_en_ch3.
+              0
+              1
+              read-write
+            
+            
+              MEM_WR_RST
+              reg_mem_wr_rst_ch3.
+              1
+              1
+              write-only
+            
+            
+              APB_MEM_RST
+              reg_apb_mem_rst_ch3.
+              2
+              1
+              write-only
+            
+            
+              MEM_OWNER
+              reg_mem_owner_ch3.
+              3
+              1
+              read-write
+            
+            
+              RX_FILTER_EN
+              reg_rx_filter_en_ch3.
+              4
+              1
+              read-write
+            
+            
+              RX_FILTER_THRES
+              reg_rx_filter_thres_ch3.
+              5
+              8
+              read-write
+            
+            
+              MEM_RX_WRAP_EN
+              reg_mem_rx_wrap_en_ch3.
+              13
+              1
+              read-write
+            
+            
+              AFIFO_RST
+              reg_afifo_rst_ch3.
+              14
+              1
+              write-only
+            
+            
+              CONF_UPDATE
+              reg_conf_update_ch3.
+              15
+              1
+              write-only
+            
+          
+        
+        
+          CH0STATUS
+          RMT_CH0STATUS_REG.
+          0x28
+          0x20
+          
+            
+              MEM_RADDR_EX
+              reg_mem_raddr_ex_ch0.
+              0
+              9
+              read-only
+            
+            
+              STATE
+              reg_state_ch0.
+              9
+              3
+              read-only
+            
+            
+              APB_MEM_WADDR
+              reg_apb_mem_waddr_ch0.
+              12
+              9
+              read-only
+            
+            
+              APB_MEM_RD_ERR
+              reg_apb_mem_rd_err_ch0.
+              21
+              1
+              read-only
+            
+            
+              MEM_EMPTY
+              reg_mem_empty_ch0.
+              22
+              1
+              read-only
+            
+            
+              APB_MEM_WR_ERR
+              reg_apb_mem_wr_err_ch0.
+              23
+              1
+              read-only
+            
+            
+              APB_MEM_RADDR
+              reg_apb_mem_raddr_ch0.
+              24
+              8
+              read-only
+            
+          
+        
+        
+          CH1STATUS
+          RMT_CH1STATUS_REG.
+          0x2C
+          0x20
+          
+            
+              MEM_RADDR_EX
+              reg_mem_raddr_ex_ch1.
+              0
+              9
+              read-only
+            
+            
+              STATE
+              reg_state_ch1.
+              9
+              3
+              read-only
+            
+            
+              APB_MEM_WADDR
+              reg_apb_mem_waddr_ch1.
+              12
+              9
+              read-only
+            
+            
+              APB_MEM_RD_ERR
+              reg_apb_mem_rd_err_ch1.
+              21
+              1
+              read-only
+            
+            
+              MEM_EMPTY
+              reg_mem_empty_ch1.
+              22
+              1
+              read-only
+            
+            
+              APB_MEM_WR_ERR
+              reg_apb_mem_wr_err_ch1.
+              23
+              1
+              read-only
+            
+            
+              APB_MEM_RADDR
+              reg_apb_mem_raddr_ch1.
+              24
+              8
+              read-only
+            
+          
+        
+        
+          CH2STATUS
+          RMT_CH2STATUS_REG.
+          0x30
+          0x20
+          
+            
+              MEM_WADDR_EX
+              reg_mem_waddr_ex_ch2.
+              0
+              9
+              read-only
+            
+            
+              APB_MEM_RADDR
+              reg_apb_mem_raddr_ch2.
+              12
+              9
+              read-only
+            
+            
+              STATE
+              reg_state_ch2.
+              22
+              3
+              read-only
+            
+            
+              MEM_OWNER_ERR
+              reg_mem_owner_err_ch2.
+              25
+              1
+              read-only
+            
+            
+              MEM_FULL
+              reg_mem_full_ch2.
+              26
+              1
+              read-only
+            
+            
+              APB_MEM_RD_ERR
+              reg_apb_mem_rd_err_ch2.
+              27
+              1
+              read-only
+            
+          
+        
+        
+          CH3STATUS
+          RMT_CH3STATUS_REG.
+          0x34
+          0x20
+          
+            
+              MEM_WADDR_EX
+              reg_mem_waddr_ex_ch3.
+              0
+              9
+              read-only
+            
+            
+              APB_MEM_RADDR
+              reg_apb_mem_raddr_ch3.
+              12
+              9
+              read-only
+            
+            
+              STATE
+              reg_state_ch3.
+              22
+              3
+              read-only
+            
+            
+              MEM_OWNER_ERR
+              reg_mem_owner_err_ch3.
+              25
+              1
+              read-only
+            
+            
+              MEM_FULL
+              reg_mem_full_ch3.
+              26
+              1
+              read-only
+            
+            
+              APB_MEM_RD_ERR
+              reg_apb_mem_rd_err_ch3.
+              27
+              1
+              read-only
+            
+          
+        
+        
+          INT_RAW
+          RMT_INT_RAW_REG.
+          0x38
+          0x20
+          
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_END_INT_RAW
+              reg_ch%s_tx_end_int_raw.
+              0
+              1
+              read-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_END_INT_RAW
+              reg_ch2_rx_end_int_raw.
+              2
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_ERR_INT_RAW
+              reg_ch%s_err_int_raw.
+              4
+              1
+              read-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_ERR_INT_RAW
+              reg_ch2_err_int_raw.
+              6
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_THR_EVENT_INT_RAW
+              reg_ch%s_tx_thr_event_int_raw.
+              8
+              1
+              read-only
+            
+            
+              CH2_RX_THR_EVENT_INT_RAW
+              reg_ch2_rx_thr_event_int_raw.
+              10
+              1
+              read-only
+            
+            
+              CH3_RX_THR_EVENT_INT_RAW
+              reg_ch3_rx_thr_event_int_raw.
+              11
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_LOOP_INT_RAW
+              reg_ch%s_tx_loop_int_raw.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          RMT_INT_ST_REG.
+          0x3C
+          0x20
+          
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_END_INT_ST
+              reg_ch%s_tx_end_int_st.
+              0
+              1
+              read-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_END_INT_ST
+              reg_ch2_rx_end_int_st.
+              2
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_ERR_INT_ST
+              reg_ch%s_err_int_st.
+              4
+              1
+              read-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_ERR_INT_ST
+              reg_ch2_err_int_st.
+              6
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_THR_EVENT_INT_ST
+              reg_ch%s_tx_thr_event_int_st.
+              8
+              1
+              read-only
+            
+            
+              CH2_RX_THR_EVENT_INT_ST
+              reg_ch2_rx_thr_event_int_st.
+              10
+              1
+              read-only
+            
+            
+              CH3_RX_THR_EVENT_INT_ST
+              reg_ch3_rx_thr_event_int_st.
+              11
+              1
+              read-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_LOOP_INT_ST
+              reg_ch%s_tx_loop_int_st.
+              12
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          RMT_INT_ENA_REG.
+          0x40
+          0x20
+          
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_END_INT_ENA
+              reg_ch%s_tx_end_int_ena.
+              0
+              1
+              read-write
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_END_INT_ENA
+              reg_ch2_rx_end_int_ena.
+              2
+              1
+              read-write
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_ERR_INT_ENA
+              reg_ch%s_err_int_ena.
+              4
+              1
+              read-write
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_ERR_INT_ENA
+              reg_ch2_err_int_ena.
+              6
+              1
+              read-write
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_THR_EVENT_INT_ENA
+              reg_ch%s_tx_thr_event_int_ena.
+              8
+              1
+              read-write
+            
+            
+              CH2_RX_THR_EVENT_INT_ENA
+              reg_ch2_rx_thr_event_int_ena.
+              10
+              1
+              read-write
+            
+            
+              CH3_RX_THR_EVENT_INT_ENA
+              reg_ch3_rx_thr_event_int_ena.
+              11
+              1
+              read-write
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_LOOP_INT_ENA
+              reg_ch%s_tx_loop_int_ena.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          RMT_INT_CLR_REG.
+          0x44
+          0x20
+          
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_END_INT_CLR
+              reg_ch%s_tx_end_int_clr.
+              0
+              1
+              write-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_END_INT_CLR
+              reg_ch2_rx_end_int_clr.
+              2
+              1
+              write-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_ERR_INT_CLR
+              reg_ch%s_err_int_clr.
+              4
+              1
+              write-only
+            
+            
+              2
+              0x1
+              2-3
+              CH%s_RX_ERR_INT_CLR
+              reg_ch2_err_int_clr.
+              6
+              1
+              write-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_THR_EVENT_INT_CLR
+              reg_ch%s_tx_thr_event_int_clr.
+              8
+              1
+              write-only
+            
+            
+              CH2_RX_THR_EVENT_INT_CLR
+              reg_ch2_rx_thr_event_int_clr.
+              10
+              1
+              write-only
+            
+            
+              CH3_RX_THR_EVENT_INT_CLR
+              reg_ch3_rx_thr_event_int_clr.
+              11
+              1
+              write-only
+            
+            
+              2
+              0x1
+              0-1
+              CH%s_TX_LOOP_INT_CLR
+              reg_ch%s_tx_loop_int_clr.
+              12
+              1
+              write-only
+            
+          
+        
+        
+          CH0CARRIER_DUTY
+          RMT_CH0CARRIER_DUTY_REG.
+          0x48
+          0x20
+          0x00400040
+          
+            
+              CARRIER_LOW
+              reg_carrier_low_ch0.
+              0
+              16
+              read-write
+            
+            
+              CARRIER_HIGH
+              reg_carrier_high_ch0.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          CH1CARRIER_DUTY
+          RMT_CH1CARRIER_DUTY_REG.
+          0x4C
+          0x20
+          0x00400040
+          
+            
+              CARRIER_LOW
+              reg_carrier_low_ch1.
+              0
+              16
+              read-write
+            
+            
+              CARRIER_HIGH
+              reg_carrier_high_ch1.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          CH2_RX_CARRIER_RM
+          RMT_CH2_RX_CARRIER_RM_REG.
+          0x50
+          0x20
+          
+            
+              CARRIER_LOW_THRES
+              reg_carrier_low_thres_ch2.
+              0
+              16
+              read-write
+            
+            
+              CARRIER_HIGH_THRES
+              reg_carrier_high_thres_ch2.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          CH3_RX_CARRIER_RM
+          RMT_CH3_RX_CARRIER_RM_REG.
+          0x54
+          0x20
+          
+            
+              CARRIER_LOW_THRES
+              reg_carrier_low_thres_ch3.
+              0
+              16
+              read-write
+            
+            
+              CARRIER_HIGH_THRES
+              reg_carrier_high_thres_ch3.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          2
+          0x4
+          0-1
+          CH%s_TX_LIM
+          RMT_CH%s_TX_LIM_REG.
+          0x58
+          0x20
+          0x00000080
+          
+            
+              TX_LIM
+              reg_rmt_tx_lim_ch0.
+              0
+              9
+              read-write
+            
+            
+              TX_LOOP_NUM
+              reg_rmt_tx_loop_num_ch0.
+              9
+              10
+              read-write
+            
+            
+              TX_LOOP_CNT_EN
+              reg_rmt_tx_loop_cnt_en_ch0.
+              19
+              1
+              read-write
+            
+            
+              LOOP_COUNT_RESET
+              reg_loop_count_reset_ch0.
+              20
+              1
+              write-only
+            
+          
+        
+        
+          2
+          0x4
+          2-3
+          CH%s_RX_LIM
+          RMT_CH2_RX_LIM_REG.
+          0x60
+          0x20
+          0x00000080
+          
+            
+              RX_LIM
+              reg_rmt_rx_lim_ch2.
+              0
+              9
+              read-write
+            
+          
+        
+        
+          SYS_CONF
+          RMT_SYS_CONF_REG.
+          0x68
+          0x20
+          0x05000010
+          
+            
+              APB_FIFO_MASK
+              reg_apb_fifo_mask.
+              0
+              1
+              read-write
+            
+            
+              MEM_CLK_FORCE_ON
+              reg_mem_clk_force_on.
+              1
+              1
+              read-write
+            
+            
+              MEM_FORCE_PD
+              reg_rmt_mem_force_pd.
+              2
+              1
+              read-write
+            
+            
+              MEM_FORCE_PU
+              reg_rmt_mem_force_pu.
+              3
+              1
+              read-write
+            
+            
+              SCLK_DIV_NUM
+              reg_rmt_sclk_div_num.
+              4
+              8
+              read-write
+            
+            
+              SCLK_DIV_A
+              reg_rmt_sclk_div_a.
+              12
+              6
+              read-write
+            
+            
+              SCLK_DIV_B
+              reg_rmt_sclk_div_b.
+              18
+              6
+              read-write
+            
+            
+              SCLK_SEL
+              reg_rmt_sclk_sel.
+              24
+              2
+              read-write
+            
+            
+              SCLK_ACTIVE
+              reg_rmt_sclk_active.
+              26
+              1
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          TX_SIM
+          RMT_TX_SIM_REG.
+          0x6C
+          0x20
+          
+            
+              TX_SIM_CH0
+              reg_rmt_tx_sim_ch0.
+              0
+              1
+              read-write
+            
+            
+              TX_SIM_CH1
+              reg_rmt_tx_sim_ch1.
+              1
+              1
+              read-write
+            
+            
+              TX_SIM_EN
+              reg_rmt_tx_sim_en.
+              2
+              1
+              read-write
+            
+          
+        
+        
+          REF_CNT_RST
+          RMT_REF_CNT_RST_REG.
+          0x70
+          0x20
+          
+            
+              CH0
+              reg_ref_cnt_rst_ch0.
+              0
+              1
+              write-only
+            
+            
+              CH1
+              reg_ref_cnt_rst_ch1.
+              1
+              1
+              write-only
+            
+            
+              CH2
+              reg_ref_cnt_rst_ch2.
+              2
+              1
+              write-only
+            
+            
+              CH3
+              reg_ref_cnt_rst_ch3.
+              3
+              1
+              write-only
+            
+          
+        
+        
+          DATE
+          RMT_DATE_REG.
+          0xCC
+          0x20
+          0x02006231
+          
+            
+              DATE
+              reg_rmt_date.
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      RNG
+      Hardware random number generator
+      RNG
+      0x60026000
+      
+        0x0
+        0x4
+        registers
+      
+      
+        
+          DATA
+          Random number data
+          0xB0
+          0x20
+        
+      
+    
+    
+      RSA
+      RSA (Rivest Shamir Adleman) Accelerator
+      RSA
+      0x6003C000
+      
+        0x0
+        0x74
+        registers
+      
+      
+        RSA
+        47
+      
+      
+        
+          16
+          0x1
+          M_MEM[%s]
+          The memory that stores M
+          0x0
+          0x8
+        
+        
+          16
+          0x1
+          Z_MEM[%s]
+          The memory that stores Z
+          0x200
+          0x8
+        
+        
+          16
+          0x1
+          Y_MEM[%s]
+          The memory that stores Y
+          0x400
+          0x8
+        
+        
+          16
+          0x1
+          X_MEM[%s]
+          The memory that stores X
+          0x600
+          0x8
+        
+        
+          M_PRIME
+          RSA M_prime register
+          0x800
+          0x20
+          
+            
+              M_PRIME
+              Those bits stores m'
+              0
+              32
+              read-write
+            
+          
+        
+        
+          MODE
+          RSA mode register
+          0x804
+          0x20
+          
+            
+              MODE
+              rsa mode (rsa length).
+              0
+              7
+              read-write
+            
+          
+        
+        
+          QUERY_CLEAN
+          RSA query clean register
+          0x808
+          0x20
+          
+            
+              QUERY_CLEAN
+              query clean
+              0
+              1
+              read-only
+            
+          
+        
+        
+          SET_START_MODEXP
+          RSA modular exponentiation trigger register.
+          0x80C
+          0x20
+          
+            
+              SET_START_MODEXP
+              start modular exponentiation
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_START_MODMULT
+          RSA modular multiplication trigger register.
+          0x810
+          0x20
+          
+            
+              SET_START_MODMULT
+              start modular multiplication
+              0
+              1
+              write-only
+            
+          
+        
+        
+          SET_START_MULT
+          RSA normal multiplication trigger register.
+          0x814
+          0x20
+          
+            
+              SET_START_MULT
+              start multiplicaiton
+              0
+              1
+              write-only
+            
+          
+        
+        
+          QUERY_IDLE
+          RSA query idle register
+          0x818
+          0x20
+          
+            
+              QUERY_IDLE
+              query rsa idle. 1'b0: busy, 1'b1: idle
+              0
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR
+          RSA interrupt clear register
+          0x81C
+          0x20
+          
+            
+              CLEAR_INTERRUPT
+              set this bit to clear RSA interrupt.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          CONSTANT_TIME
+          RSA constant time option register
+          0x820
+          0x20
+          0x00000001
+          
+            
+              CONSTANT_TIME
+              Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).
+              0
+              1
+              read-write
+            
+          
+        
+        
+          SEARCH_ENABLE
+          RSA search option
+          0x824
+          0x20
+          
+            
+              SEARCH_ENABLE
+              Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          SEARCH_POS
+          RSA search position configure register
+          0x828
+          0x20
+          
+            
+              SEARCH_POS
+              Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.
+              0
+              12
+              read-write
+            
+          
+        
+        
+          INT_ENA
+          RSA interrupt enable register
+          0x82C
+          0x20
+          
+            
+              INT_ENA
+              Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          RSA version control register
+          0x830
+          0x20
+          0x20200618
+          
+            
+              DATE
+              rsa version information
+              0
+              30
+              read-write
+            
+          
+        
+      
+    
+    
+      RTC_CNTL
+      Real-Time Clock Control
+      RTC_CNTL
+      0x60008000
+      
+        0x0
+        0x12C
+        registers
+      
+      
+        RTC_CORE
+        27
+      
+      
+        
+          OPTIONS0
+          rtc configure register
+          0x0
+          0x20
+          0x1C00A000
+          
+            
+              SW_STALL_APPCPU_C0
+              {reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU
+              0
+              2
+              read-write
+            
+            
+              SW_STALL_PROCPU_C0
+              {reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU
+              2
+              2
+              read-write
+            
+            
+              SW_APPCPU_RST
+              APP CPU SW reset
+              4
+              1
+              write-only
+            
+            
+              SW_PROCPU_RST
+              PRO CPU SW reset
+              5
+              1
+              write-only
+            
+            
+              BB_I2C_FORCE_PD
+              BB_I2C force power down
+              6
+              1
+              read-write
+            
+            
+              BB_I2C_FORCE_PU
+              BB_I2C force power up
+              7
+              1
+              read-write
+            
+            
+              BBPLL_I2C_FORCE_PD
+              BB_PLL _I2C force power down
+              8
+              1
+              read-write
+            
+            
+              BBPLL_I2C_FORCE_PU
+              BB_PLL_I2C force power up
+              9
+              1
+              read-write
+            
+            
+              BBPLL_FORCE_PD
+              BB_PLL force power down
+              10
+              1
+              read-write
+            
+            
+              BBPLL_FORCE_PU
+              BB_PLL force power up
+              11
+              1
+              read-write
+            
+            
+              XTL_FORCE_PD
+              crystall force power down
+              12
+              1
+              read-write
+            
+            
+              XTL_FORCE_PU
+              crystall force power up
+              13
+              1
+              read-write
+            
+            
+              XTL_EN_WAIT
+              wait bias_sleep and current source wakeup
+              14
+              4
+              read-write
+            
+            
+              XTL_EXT_CTR_SEL
+              analog configure
+              20
+              3
+              read-write
+            
+            
+              XTL_FORCE_ISO
+              analog configure
+              23
+              1
+              read-write
+            
+            
+              PLL_FORCE_ISO
+              analog configure
+              24
+              1
+              read-write
+            
+            
+              ANALOG_FORCE_ISO
+              analog configure
+              25
+              1
+              read-write
+            
+            
+              XTL_FORCE_NOISO
+              analog configure
+              26
+              1
+              read-write
+            
+            
+              PLL_FORCE_NOISO
+              analog configure
+              27
+              1
+              read-write
+            
+            
+              ANALOG_FORCE_NOISO
+              analog configure
+              28
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_RST
+              digital wrap force reset in deep sleep
+              29
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_NORST
+              digital core force no reset in deep sleep
+              30
+              1
+              read-write
+            
+            
+              SW_SYS_RST
+              SW system reset
+              31
+              1
+              write-only
+            
+          
+        
+        
+          SLP_TIMER0
+          rtc configure register
+          0x4
+          0x20
+          
+            
+              SLP_VAL_LO
+              configure the  sleep time
+              0
+              32
+              read-write
+            
+          
+        
+        
+          SLP_TIMER1
+          rtc configure register
+          0x8
+          0x20
+          
+            
+              SLP_VAL_HI
+              RTC sleep timer high 16 bits
+              0
+              16
+              read-write
+            
+            
+              RTC_MAIN_TIMER_ALARM_EN
+              timer alarm enable bit
+              16
+              1
+              write-only
+            
+          
+        
+        
+          TIME_UPDATE
+          rtc configure register
+          0xC
+          0x20
+          
+            
+              TIMER_SYS_STALL
+              Enable to record system stall time
+              27
+              1
+              read-write
+            
+            
+              TIMER_XTL_OFF
+              Enable to record 40M XTAL OFF time
+              28
+              1
+              read-write
+            
+            
+              TIMER_SYS_RST
+              enable to record system reset time
+              29
+              1
+              read-write
+            
+            
+              RTC_TIME_UPDATE
+              Set 1: to update register with RTC timer
+              31
+              1
+              write-only
+            
+          
+        
+        
+          TIME_LOW0
+          rtc configure register
+          0x10
+          0x20
+          
+            
+              RTC_TIMER_VALUE0_LOW
+              RTC timer low 32 bits
+              0
+              32
+              read-only
+            
+          
+        
+        
+          TIME_HIGH0
+          rtc configure register
+          0x14
+          0x20
+          
+            
+              RTC_TIMER_VALUE0_HIGH
+              RTC timer high 16 bits
+              0
+              16
+              read-only
+            
+          
+        
+        
+          STATE0
+          rtc configure register
+          0x18
+          0x20
+          
+            
+              RTC_SW_CPU_INT
+              rtc software interrupt to main cpu
+              0
+              1
+              write-only
+            
+            
+              RTC_SLP_REJECT_CAUSE_CLR
+              clear rtc sleep reject cause
+              1
+              1
+              write-only
+            
+            
+              APB2RTC_BRIDGE_SEL
+              1: APB to RTC using bridge
+              22
+              1
+              read-write
+            
+            
+              SDIO_ACTIVE_IND
+              SDIO active indication
+              28
+              1
+              read-only
+            
+            
+              SLP_WAKEUP
+              leep wakeup bit
+              29
+              1
+              read-write
+            
+            
+              SLP_REJECT
+              leep reject bit
+              30
+              1
+              read-write
+            
+            
+              SLEEP_EN
+              sleep enable bit
+              31
+              1
+              read-write
+            
+          
+        
+        
+          TIMER1
+          rtc configure register
+          0x1C
+          0x20
+          0x28140403
+          
+            
+              CPU_STALL_EN
+              CPU stall enable bit
+              0
+              1
+              read-write
+            
+            
+              CPU_STALL_WAIT
+              CPU stall wait cycles in fast_clk_rtc
+              1
+              5
+              read-write
+            
+            
+              CK8M_WAIT
+              CK8M wait cycles in slow_clk_rtc
+              6
+              8
+              read-write
+            
+            
+              XTL_BUF_WAIT
+              XTAL wait cycles in slow_clk_rtc
+              14
+              10
+              read-write
+            
+            
+              PLL_BUF_WAIT
+              PLL wait cycles in slow_clk_rtc
+              24
+              8
+              read-write
+            
+          
+        
+        
+          TIMER2
+          rtc configure register
+          0x20
+          0x20
+          0x01000000
+          
+            
+              MIN_TIME_CK8M_OFF
+              minimal cycles in slow_clk_rtc for CK8M in power down state
+              24
+              8
+              read-write
+            
+          
+        
+        
+          TIMER3
+          rtc configure register
+          0x24
+          0x20
+          0x0A080A08
+          
+            
+              WIFI_WAIT_TIMER
+              wifi power domain wakeup time
+              0
+              9
+              read-write
+            
+            
+              WIFI_POWERUP_TIMER
+              wifi power domain power on time
+              9
+              7
+              read-write
+            
+            
+              BT_WAIT_TIMER
+              bt power domain wakeup time
+              16
+              9
+              read-write
+            
+            
+              BT_POWERUP_TIMER
+              bt power domain power on time
+              25
+              7
+              read-write
+            
+          
+        
+        
+          TIMER4
+          rtc configure register
+          0x28
+          0x20
+          0x10200A08
+          
+            
+              CPU_TOP_WAIT_TIMER
+              cpu top power domain wakeup time
+              0
+              9
+              read-write
+            
+            
+              CPU_TOP_POWERUP_TIMER
+              cpu top power domain power on time
+              9
+              7
+              read-write
+            
+            
+              DG_WRAP_WAIT_TIMER
+              digital wrap power domain wakeup time
+              16
+              9
+              read-write
+            
+            
+              DG_WRAP_POWERUP_TIMER
+              digital wrap power domain power on time
+              25
+              7
+              read-write
+            
+          
+        
+        
+          TIMER5
+          rtc configure register
+          0x2C
+          0x20
+          0x00008000
+          
+            
+              MIN_SLP_VAL
+              minimal sleep cycles in slow_clk_rtc
+              8
+              8
+              read-write
+            
+          
+        
+        
+          TIMER6
+          rtc configure register
+          0x30
+          0x20
+          0x0A080000
+          
+            
+              DG_PERI_WAIT_TIMER
+              digital peri power domain wakeup time
+              16
+              9
+              read-write
+            
+            
+              DG_PERI_POWERUP_TIMER
+              digital peri power domain power on time
+              25
+              7
+              read-write
+            
+          
+        
+        
+          ANA_CONF
+          rtc configure register
+          0x34
+          0x20
+          0x00C40000
+          
+            
+              RESET_POR_FORCE_PD
+              force no bypass i2c power on reset
+              18
+              1
+              read-write
+            
+            
+              RESET_POR_FORCE_PU
+              force bypass i2c power on reset
+              19
+              1
+              read-write
+            
+            
+              GLITCH_RST_EN
+              enable glitch reset
+              20
+              1
+              read-write
+            
+            
+              SAR_I2C_PU
+              PLLA force power up
+              22
+              1
+              read-write
+            
+            
+              PLLA_FORCE_PD
+              PLLA force power down
+              23
+              1
+              read-write
+            
+            
+              PLLA_FORCE_PU
+              PLLA force power up
+              24
+              1
+              read-write
+            
+            
+              BBPLL_CAL_SLP_START
+              start BBPLL calibration during sleep
+              25
+              1
+              read-write
+            
+            
+              PVTMON_PU
+              1: PVTMON power up
+              26
+              1
+              read-write
+            
+            
+              TXRF_I2C_PU
+              1: TXRF_I2C power up
+              27
+              1
+              read-write
+            
+            
+              RFRX_PBUS_PU
+              1: RFRX_PBUS power up
+              28
+              1
+              read-write
+            
+            
+              CKGEN_I2C_PU
+              1: CKGEN_I2C power up
+              30
+              1
+              read-write
+            
+            
+              PLL_I2C_PU
+              power up pll i2c
+              31
+              1
+              read-write
+            
+          
+        
+        
+          RESET_STATE
+          rtc configure register
+          0x38
+          0x20
+          0x00003000
+          
+            
+              RESET_CAUSE_PROCPU
+              reset cause of PRO CPU
+              0
+              6
+              read-only
+            
+            
+              RESET_CAUSE_APPCPU
+              reset cause of APP CPU
+              6
+              6
+              read-only
+            
+            
+              STAT_VECTOR_SEL_APPCPU
+              APP CPU state vector sel
+              12
+              1
+              read-write
+            
+            
+              STAT_VECTOR_SEL_PROCPU
+              PRO CPU state vector sel
+              13
+              1
+              read-write
+            
+            
+              ALL_RESET_FLAG_PROCPU
+              PRO CPU reset_flag
+              14
+              1
+              read-only
+            
+            
+              ALL_RESET_FLAG_APPCPU
+              APP CPU reset flag
+              15
+              1
+              read-only
+            
+            
+              ALL_RESET_FLAG_CLR_PROCPU
+              clear PRO CPU reset_flag
+              16
+              1
+              write-only
+            
+            
+              ALL_RESET_FLAG_CLR_APPCPU
+              clear APP CPU reset flag
+              17
+              1
+              write-only
+            
+            
+              OCD_HALT_ON_RESET_APPCPU
+              APPCPU OcdHaltOnReset
+              18
+              1
+              read-write
+            
+            
+              OCD_HALT_ON_RESET_PROCPU
+              PROCPU OcdHaltOnReset
+              19
+              1
+              read-write
+            
+            
+              JTAG_RESET_FLAG_PROCPU
+              configure jtag reset configure
+              20
+              1
+              read-only
+            
+            
+              JTAG_RESET_FLAG_APPCPU
+              configure jtag reset configure
+              21
+              1
+              read-only
+            
+            
+              JTAG_RESET_FLAG_CLR_PROCPU
+              configure jtag reset configure
+              22
+              1
+              write-only
+            
+            
+              JTAG_RESET_FLAG_CLR_APPCPU
+              configure jtag reset configure
+              23
+              1
+              write-only
+            
+            
+              RTC_DRESET_MASK_APPCPU
+              configure dreset configure
+              24
+              1
+              read-write
+            
+            
+              RTC_DRESET_MASK_PROCPU
+              configure dreset configure
+              25
+              1
+              read-write
+            
+          
+        
+        
+          WAKEUP_STATE
+          rtc configure register
+          0x3C
+          0x20
+          0x00060000
+          
+            
+              RTC_WAKEUP_ENA
+              wakeup enable bitmap
+              15
+              17
+              read-write
+            
+          
+        
+        
+          INT_ENA_RTC
+          rtc configure register
+          0x40
+          0x20
+          
+            
+              SLP_WAKEUP_INT_ENA
+              enable sleep wakeup interrupt
+              0
+              1
+              read-write
+            
+            
+              SLP_REJECT_INT_ENA
+              enable sleep reject interrupt
+              1
+              1
+              read-write
+            
+            
+              RTC_WDT_INT_ENA
+              enable RTC WDT interrupt
+              3
+              1
+              read-write
+            
+            
+              RTC_BROWN_OUT_INT_ENA
+              enable brown out interrupt
+              9
+              1
+              read-write
+            
+            
+              RTC_MAIN_TIMER_INT_ENA
+              enable RTC main timer interrupt
+              10
+              1
+              read-write
+            
+            
+              RTC_SWD_INT_ENA
+              enable super watch dog interrupt
+              15
+              1
+              read-write
+            
+            
+              RTC_XTAL32K_DEAD_INT_ENA
+              enable xtal32k_dead  interrupt
+              16
+              1
+              read-write
+            
+            
+              RTC_GLITCH_DET_INT_ENA
+              enbale gitch det interrupt
+              19
+              1
+              read-write
+            
+            
+              RTC_BBPLL_CAL_INT_ENA
+              enbale bbpll cal end interrupt
+              20
+              1
+              read-write
+            
+          
+        
+        
+          INT_RAW_RTC
+          rtc configure register
+          0x44
+          0x20
+          
+            
+              SLP_WAKEUP_INT_RAW
+              sleep wakeup interrupt raw
+              0
+              1
+              read-only
+            
+            
+              SLP_REJECT_INT_RAW
+              sleep reject interrupt raw
+              1
+              1
+              read-only
+            
+            
+              RTC_WDT_INT_RAW
+              RTC WDT interrupt raw
+              3
+              1
+              read-only
+            
+            
+              RTC_BROWN_OUT_INT_RAW
+              brown out interrupt raw
+              9
+              1
+              read-only
+            
+            
+              RTC_MAIN_TIMER_INT_RAW
+              RTC main timer interrupt raw
+              10
+              1
+              read-only
+            
+            
+              RTC_SWD_INT_RAW
+              super watch dog interrupt raw
+              15
+              1
+              read-only
+            
+            
+              RTC_XTAL32K_DEAD_INT_RAW
+              xtal32k dead detection interrupt raw
+              16
+              1
+              read-only
+            
+            
+              RTC_GLITCH_DET_INT_RAW
+              glitch_det_interrupt_raw
+              19
+              1
+              read-only
+            
+            
+              RTC_BBPLL_CAL_INT_RAW
+              bbpll cal end interrupt state
+              20
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST_RTC
+          rtc configure register
+          0x48
+          0x20
+          
+            
+              SLP_WAKEUP_INT_ST
+              sleep wakeup interrupt state
+              0
+              1
+              read-only
+            
+            
+              SLP_REJECT_INT_ST
+              sleep reject interrupt state
+              1
+              1
+              read-only
+            
+            
+              RTC_WDT_INT_ST
+              RTC WDT interrupt state
+              3
+              1
+              read-only
+            
+            
+              RTC_BROWN_OUT_INT_ST
+              brown out interrupt state
+              9
+              1
+              read-only
+            
+            
+              RTC_MAIN_TIMER_INT_ST
+              RTC main timer interrupt state
+              10
+              1
+              read-only
+            
+            
+              RTC_SWD_INT_ST
+              super watch dog interrupt state
+              15
+              1
+              read-only
+            
+            
+              RTC_XTAL32K_DEAD_INT_ST
+              xtal32k dead detection interrupt state
+              16
+              1
+              read-only
+            
+            
+              RTC_GLITCH_DET_INT_ST
+              glitch_det_interrupt state
+              19
+              1
+              read-only
+            
+            
+              RTC_BBPLL_CAL_INT_ST
+              bbpll cal end interrupt state
+              20
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR_RTC
+          rtc configure register
+          0x4C
+          0x20
+          
+            
+              SLP_WAKEUP_INT_CLR
+              Clear sleep wakeup interrupt state
+              0
+              1
+              write-only
+            
+            
+              SLP_REJECT_INT_CLR
+              Clear sleep reject interrupt state
+              1
+              1
+              write-only
+            
+            
+              RTC_WDT_INT_CLR
+              Clear RTC WDT interrupt state
+              3
+              1
+              write-only
+            
+            
+              RTC_BROWN_OUT_INT_CLR
+              Clear brown out interrupt state
+              9
+              1
+              write-only
+            
+            
+              RTC_MAIN_TIMER_INT_CLR
+              Clear RTC main timer interrupt state
+              10
+              1
+              write-only
+            
+            
+              RTC_SWD_INT_CLR
+              Clear super watch dog interrupt state
+              15
+              1
+              write-only
+            
+            
+              RTC_XTAL32K_DEAD_INT_CLR
+              Clear RTC WDT interrupt state
+              16
+              1
+              write-only
+            
+            
+              RTC_GLITCH_DET_INT_CLR
+              Clear glitch det interrupt state
+              19
+              1
+              write-only
+            
+            
+              RTC_BBPLL_CAL_INT_CLR
+              clear bbpll cal end interrupt state
+              20
+              1
+              write-only
+            
+          
+        
+        
+          STORE0
+          rtc configure register
+          0x50
+          0x20
+          
+            
+              RTC_SCRATCH0
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE1
+          rtc configure register
+          0x54
+          0x20
+          
+            
+              RTC_SCRATCH1
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE2
+          rtc configure register
+          0x58
+          0x20
+          
+            
+              RTC_SCRATCH2
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE3
+          rtc configure register
+          0x5C
+          0x20
+          
+            
+              RTC_SCRATCH3
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          EXT_XTL_CONF
+          rtc configure register
+          0x60
+          0x20
+          0x00066C80
+          
+            
+              XTAL32K_WDT_EN
+              xtal 32k watch dog enable
+              0
+              1
+              read-write
+            
+            
+              XTAL32K_WDT_CLK_FO
+              xtal 32k watch dog clock force on
+              1
+              1
+              read-write
+            
+            
+              XTAL32K_WDT_RESET
+              xtal 32k watch dog sw reset
+              2
+              1
+              read-write
+            
+            
+              XTAL32K_EXT_CLK_FO
+              xtal 32k external xtal clock force on
+              3
+              1
+              read-write
+            
+            
+              XTAL32K_AUTO_BACKUP
+              xtal 32k switch to back up clock when xtal is dead
+              4
+              1
+              read-write
+            
+            
+              XTAL32K_AUTO_RESTART
+              xtal 32k restart xtal when xtal is dead
+              5
+              1
+              read-write
+            
+            
+              XTAL32K_AUTO_RETURN
+              xtal 32k switch back xtal when xtal is restarted
+              6
+              1
+              read-write
+            
+            
+              XTAL32K_XPD_FORCE
+              Xtal 32k xpd control by sw or fsm
+              7
+              1
+              read-write
+            
+            
+              ENCKINIT_XTAL_32K
+              apply an internal clock to help xtal 32k to start
+              8
+              1
+              read-write
+            
+            
+              DBUF_XTAL_32K
+              0: single-end buffer 1: differential buffer
+              9
+              1
+              read-write
+            
+            
+              DGM_XTAL_32K
+              xtal_32k gm control
+              10
+              3
+              read-write
+            
+            
+              DRES_XTAL_32K
+              DRES_XTAL_32K
+              13
+              3
+              read-write
+            
+            
+              XPD_XTAL_32K
+              XPD_XTAL_32K
+              16
+              1
+              read-write
+            
+            
+              DAC_XTAL_32K
+              DAC_XTAL_32K
+              17
+              3
+              read-write
+            
+            
+              RTC_WDT_STATE
+              state of 32k_wdt
+              20
+              3
+              read-only
+            
+            
+              RTC_XTAL32K_GPIO_SEL
+              XTAL_32K sel. 0: external XTAL_32K
+              23
+              1
+              read-write
+            
+            
+              XTL_EXT_CTR_LV
+              0: power down XTAL at high level
+              30
+              1
+              read-write
+            
+            
+              XTL_EXT_CTR_EN
+              enable gpio configure xtal power on
+              31
+              1
+              read-write
+            
+          
+        
+        
+          EXT_WAKEUP_CONF
+          rtc configure register
+          0x64
+          0x20
+          
+            
+              GPIO_WAKEUP_FILTER
+              enable filter for gpio wakeup event
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SLP_REJECT_CONF
+          rtc configure register
+          0x68
+          0x20
+          
+            
+              RTC_SLEEP_REJECT_ENA
+              sleep reject enable
+              12
+              18
+              read-write
+            
+            
+              LIGHT_SLP_REJECT_EN
+              enable reject for light sleep
+              30
+              1
+              read-write
+            
+            
+              DEEP_SLP_REJECT_EN
+              enable reject for deep sleep
+              31
+              1
+              read-write
+            
+          
+        
+        
+          CPU_PERIOD_CONF
+          rtc configure register
+          0x6C
+          0x20
+          
+            
+              RTC_CPUSEL_CONF
+              CPU sel option
+              29
+              1
+              read-write
+            
+            
+              RTC_CPUPERIOD_SEL
+              CPU clk sel option
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CLK_CONF
+          rtc configure register
+          0x70
+          0x20
+          0x11583218
+          
+            
+              EFUSE_CLK_FORCE_GATING
+              efuse_clk_force_gating
+              1
+              1
+              read-write
+            
+            
+              EFUSE_CLK_FORCE_NOGATING
+              efuse_clk_force_nogating
+              2
+              1
+              read-write
+            
+            
+              CK8M_DIV_SEL_VLD
+              used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel
+              3
+              1
+              read-write
+            
+            
+              CK8M_DIV
+              CK8M_D256_OUT divider. 00: div128
+              4
+              2
+              read-write
+            
+            
+              ENB_CK8M
+              disable CK8M and CK8M_D256_OUT
+              6
+              1
+              read-write
+            
+            
+              ENB_CK8M_DIV
+              1: CK8M_D256_OUT is actually CK8M
+              7
+              1
+              read-write
+            
+            
+              DIG_XTAL32K_EN
+              enable CK_XTAL_32K for digital core (no relationship with RTC core)
+              8
+              1
+              read-write
+            
+            
+              DIG_CLK8M_D256_EN
+              enable CK8M_D256_OUT for digital core (no relationship with RTC core)
+              9
+              1
+              read-write
+            
+            
+              DIG_CLK8M_EN
+              enable CK8M for digital core (no relationship with RTC core)
+              10
+              1
+              read-write
+            
+            
+              CK8M_DIV_SEL
+              divider = reg_ck8m_div_sel + 1
+              12
+              3
+              read-write
+            
+            
+              XTAL_FORCE_NOGATING
+              XTAL force no gating during sleep
+              15
+              1
+              read-write
+            
+            
+              CK8M_FORCE_NOGATING
+              CK8M force no gating during sleep
+              16
+              1
+              read-write
+            
+            
+              CK8M_DFREQ
+              CK8M_DFREQ
+              17
+              8
+              read-write
+            
+            
+              CK8M_FORCE_PD
+              CK8M force power down
+              25
+              1
+              read-write
+            
+            
+              CK8M_FORCE_PU
+              CK8M force power up
+              26
+              1
+              read-write
+            
+            
+              XTAL_GLOBAL_FORCE_GATING
+              force enable xtal clk gating
+              27
+              1
+              read-write
+            
+            
+              XTAL_GLOBAL_FORCE_NOGATING
+              force bypass xtal clk gating
+              28
+              1
+              read-write
+            
+            
+              FAST_CLK_RTC_SEL
+              fast_clk_rtc sel. 0: XTAL div 4
+              29
+              1
+              read-write
+            
+            
+              ANA_CLK_RTC_SEL
+              slelect rtc slow clk
+              30
+              2
+              read-write
+            
+          
+        
+        
+          SLOW_CLK_CONF
+          rtc configure register
+          0x74
+          0x20
+          0x00400000
+          
+            
+              RTC_ANA_CLK_DIV_VLD
+              used to sync div bus. clear vld before set reg_rtc_ana_clk_div
+              22
+              1
+              read-write
+            
+            
+              RTC_ANA_CLK_DIV
+              the clk divider num of RTC_CLK
+              23
+              8
+              read-write
+            
+            
+              RTC_SLOW_CLK_NEXT_EDGE
+              flag rtc_slow_clk_next_edge
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SDIO_CONF
+          rtc configure register
+          0x78
+          0x20
+          0x0AB0BE0A
+          
+            
+              SDIO_TIMER_TARGET
+              timer count to apply reg_sdio_dcap after sdio power on
+              0
+              8
+              read-write
+            
+            
+              SDIO_DTHDRV
+              Tieh = 1 mode drive ability. Initially set to 0 to limit charge current
+              9
+              2
+              read-write
+            
+            
+              SDIO_DCAP
+              ability to prevent LDO from overshoot
+              11
+              2
+              read-write
+            
+            
+              SDIO_INITI
+              add resistor from ldo output to ground. 0: no res
+              13
+              2
+              read-write
+            
+            
+              SDIO_EN_INITI
+              0 to set init[1:0]=0
+              15
+              1
+              read-write
+            
+            
+              SDIO_DCURLIM
+              tune current limit threshold when tieh = 0. About 800mA/(8+d)
+              16
+              3
+              read-write
+            
+            
+              SDIO_MODECURLIM
+              select current limit mode
+              19
+              1
+              read-write
+            
+            
+              SDIO_ENCURLIM
+              enable current limit
+              20
+              1
+              read-write
+            
+            
+              SDIO_REG_PD_EN
+              power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
+              21
+              1
+              read-write
+            
+            
+              SDIO_FORCE
+              1: use SW option to control SDIO_REG
+              22
+              1
+              read-write
+            
+            
+              SDIO_TIEH
+              SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
+              23
+              1
+              read-write
+            
+            
+              _1P8_READY
+              read only register for REG1P8_READY
+              24
+              1
+              read-only
+            
+            
+              DREFL_SDIO
+              SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
+              25
+              2
+              read-write
+            
+            
+              DREFM_SDIO
+              SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
+              27
+              2
+              read-write
+            
+            
+              DREFH_SDIO
+              SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
+              29
+              2
+              read-write
+            
+            
+              XPD_SDIO
+              31
+              1
+              read-write
+            
+          
+        
+        
+          BIAS_CONF
+          rtc configure register
+          0x7C
+          0x20
+          0x00010800
+          
+            
+              DG_VDD_DRV_B_SLP
+              0
+              8
+              read-write
+            
+            
+              DG_VDD_DRV_B_SLP_EN
+              8
+              1
+              read-write
+            
+            
+              BIAS_BUF_IDLE
+              bias buf when rtc in normal work state
+              10
+              1
+              read-write
+            
+            
+              BIAS_BUF_WAKE
+              bias buf when rtc in wakeup state
+              11
+              1
+              read-write
+            
+            
+              BIAS_BUF_DEEP_SLP
+              bias buf when rtc in sleep state
+              12
+              1
+              read-write
+            
+            
+              BIAS_BUF_MONITOR
+              bias buf when rtc in monitor state
+              13
+              1
+              read-write
+            
+            
+              PD_CUR_DEEP_SLP
+              xpd cur when rtc in sleep_state
+              14
+              1
+              read-write
+            
+            
+              PD_CUR_MONITOR
+              xpd cur when rtc in monitor state
+              15
+              1
+              read-write
+            
+            
+              BIAS_SLEEP_DEEP_SLP
+              bias_sleep when rtc in sleep_state
+              16
+              1
+              read-write
+            
+            
+              BIAS_SLEEP_MONITOR
+              bias_sleep when rtc in monitor state
+              17
+              1
+              read-write
+            
+            
+              DBG_ATTEN_DEEP_SLP
+              DBG_ATTEN when rtc in sleep state
+              18
+              4
+              read-write
+            
+            
+              DBG_ATTEN_MONITOR
+              DBG_ATTEN when rtc in monitor state
+              22
+              4
+              read-write
+            
+          
+        
+        
+          RTC_CNTL
+          rtc configure register
+          0x80
+          0x20
+          0xA0000000
+          
+            
+              DIG_REG_CAL_EN
+              software enable digital regulator cali
+              7
+              1
+              read-write
+            
+            
+              SCK_DCAP
+              SCK_DCAP
+              14
+              8
+              read-write
+            
+            
+              DBOOST_FORCE_PD
+              RTC_DBOOST force power down
+              28
+              1
+              read-write
+            
+            
+              DBOOST_FORCE_PU
+              RTC_DBOOST force power up
+              29
+              1
+              read-write
+            
+            
+              REGULATOR_FORCE_PD
+              RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )
+              30
+              1
+              read-write
+            
+            
+              REGULATOR_FORCE_PU
+              RTC_REG force power up
+              31
+              1
+              read-write
+            
+          
+        
+        
+          PWC
+          rtc configure register
+          0x84
+          0x20
+          
+            
+              RTC_PAD_FORCE_HOLD
+              rtc pad force hold
+              21
+              1
+              read-write
+            
+          
+        
+        
+          DIG_PWC
+          rtc configure register
+          0x88
+          0x20
+          0x00555010
+          
+            
+              VDD_SPI_PWR_DRV
+              vdd_spi drv's software value
+              0
+              2
+              read-write
+            
+            
+              VDD_SPI_PWR_FORCE
+              vdd_spi drv use software value
+              2
+              1
+              read-write
+            
+            
+              LSLP_MEM_FORCE_PD
+              memories in digital core force PD in sleep
+              3
+              1
+              read-write
+            
+            
+              LSLP_MEM_FORCE_PU
+              memories in digital core force PU in sleep
+              4
+              1
+              read-write
+            
+            
+              BT_FORCE_PD
+              bt force power down
+              11
+              1
+              read-write
+            
+            
+              BT_FORCE_PU
+              bt force power up
+              12
+              1
+              read-write
+            
+            
+              DG_PERI_FORCE_PD
+              digital peri force power down
+              13
+              1
+              read-write
+            
+            
+              DG_PERI_FORCE_PU
+              digital peri force power up
+              14
+              1
+              read-write
+            
+            
+              RTC_FASTMEM_FORCE_LPD
+              fastmemory  retention mode in sleep
+              15
+              1
+              read-write
+            
+            
+              RTC_FASTMEM_FORCE_LPU
+              fastmemory donlt entry retention mode in sleep
+              16
+              1
+              read-write
+            
+            
+              WIFI_FORCE_PD
+              wifi force power down
+              17
+              1
+              read-write
+            
+            
+              WIFI_FORCE_PU
+              wifi force power up
+              18
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_PD
+              digital core force power down
+              19
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_PU
+              digital core force power up
+              20
+              1
+              read-write
+            
+            
+              CPU_TOP_FORCE_PD
+              cpu core force power down
+              21
+              1
+              read-write
+            
+            
+              CPU_TOP_FORCE_PU
+              cpu force power up
+              22
+              1
+              read-write
+            
+            
+              BT_PD_EN
+              enable power down bt in sleep
+              27
+              1
+              read-write
+            
+            
+              DG_PERI_PD_EN
+              enable power down digital peri in sleep
+              28
+              1
+              read-write
+            
+            
+              CPU_TOP_PD_EN
+              enable power down cpu in sleep
+              29
+              1
+              read-write
+            
+            
+              WIFI_PD_EN
+              enable power down wifi in sleep
+              30
+              1
+              read-write
+            
+            
+              DG_WRAP_PD_EN
+              enable power down digital wrap in sleep
+              31
+              1
+              read-write
+            
+          
+        
+        
+          DIG_ISO
+          rtc configure register
+          0x8C
+          0x20
+          0xAA805080
+          
+            
+              FORCE_OFF
+              DIG_ISO force off
+              7
+              1
+              read-write
+            
+            
+              FORCE_ON
+              DIG_ISO force on
+              8
+              1
+              read-write
+            
+            
+              DG_PAD_AUTOHOLD
+              read only register to indicate digital pad auto-hold status
+              9
+              1
+              read-only
+            
+            
+              CLR_DG_PAD_AUTOHOLD
+              wtite only register to clear digital pad auto-hold
+              10
+              1
+              write-only
+            
+            
+              DG_PAD_AUTOHOLD_EN
+              digital pad enable auto-hold
+              11
+              1
+              read-write
+            
+            
+              DG_PAD_FORCE_NOISO
+              digital pad force no ISO
+              12
+              1
+              read-write
+            
+            
+              DG_PAD_FORCE_ISO
+              digital pad force ISO
+              13
+              1
+              read-write
+            
+            
+              DG_PAD_FORCE_UNHOLD
+              digital pad force un-hold
+              14
+              1
+              read-write
+            
+            
+              DG_PAD_FORCE_HOLD
+              digital pad force hold
+              15
+              1
+              read-write
+            
+            
+              BT_FORCE_ISO
+              bt force ISO
+              22
+              1
+              read-write
+            
+            
+              BT_FORCE_NOISO
+              bt force no ISO
+              23
+              1
+              read-write
+            
+            
+              DG_PERI_FORCE_ISO
+              Digital peri force ISO
+              24
+              1
+              read-write
+            
+            
+              DG_PERI_FORCE_NOISO
+              digital peri force no ISO
+              25
+              1
+              read-write
+            
+            
+              CPU_TOP_FORCE_ISO
+              cpu force ISO
+              26
+              1
+              read-write
+            
+            
+              CPU_TOP_FORCE_NOISO
+              cpu force no ISO
+              27
+              1
+              read-write
+            
+            
+              WIFI_FORCE_ISO
+              wifi force ISO
+              28
+              1
+              read-write
+            
+            
+              WIFI_FORCE_NOISO
+              wifi force no ISO
+              29
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_ISO
+              digital core force ISO
+              30
+              1
+              read-write
+            
+            
+              DG_WRAP_FORCE_NOISO
+              digital core force no ISO
+              31
+              1
+              read-write
+            
+          
+        
+        
+          WDTCONFIG0
+          rtc configure register
+          0x90
+          0x20
+          0x00013214
+          
+            
+              WDT_CHIP_RESET_WIDTH
+              chip reset siginal pulse width
+              0
+              8
+              read-write
+            
+            
+              WDT_CHIP_RESET_EN
+              wdt reset whole chip enable
+              8
+              1
+              read-write
+            
+            
+              WDT_PAUSE_IN_SLP
+              pause WDT in sleep
+              9
+              1
+              read-write
+            
+            
+              WDT_APPCPU_RESET_EN
+              enable WDT reset APP CPU
+              10
+              1
+              read-write
+            
+            
+              WDT_PROCPU_RESET_EN
+              enable WDT reset PRO CPU
+              11
+              1
+              read-write
+            
+            
+              WDT_FLASHBOOT_MOD_EN
+              enable WDT in flash boot
+              12
+              1
+              read-write
+            
+            
+              WDT_SYS_RESET_LENGTH
+              system reset counter length
+              13
+              3
+              read-write
+            
+            
+              WDT_CPU_RESET_LENGTH
+              CPU reset counter length
+              16
+              3
+              read-write
+            
+            
+              WDT_STG3
+              1: interrupt stage en
+              19
+              3
+              read-write
+            
+            
+              WDT_STG2
+              1: interrupt stage en
+              22
+              3
+              read-write
+            
+            
+              WDT_STG1
+              1: interrupt stage en
+              25
+              3
+              read-write
+            
+            
+              WDT_STG0
+              1: interrupt stage en
+              28
+              3
+              read-write
+            
+            
+              WDT_EN
+              enable rtc wdt
+              31
+              1
+              read-write
+            
+          
+        
+        
+          WDTCONFIG1
+          rtc configure register
+          0x94
+          0x20
+          0x00030D40
+          
+            
+              WDT_STG0_HOLD
+              the hold time of stage0
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG2
+          rtc configure register
+          0x98
+          0x20
+          0x00013880
+          
+            
+              WDT_STG1_HOLD
+              the hold time of stage1
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG3
+          rtc configure register
+          0x9C
+          0x20
+          0x00000FFF
+          
+            
+              WDT_STG2_HOLD
+              the hold time of stage2
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG4
+          rtc configure register
+          0xA0
+          0x20
+          0x00000FFF
+          
+            
+              WDT_STG3_HOLD
+              the hold time of stage3
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTFEED
+          rtc configure register
+          0xA4
+          0x20
+          
+            
+              RTC_WDT_FEED
+              sw feed rtc wdt
+              31
+              1
+              write-only
+            
+          
+        
+        
+          WDTWPROTECT
+          rtc configure register
+          0xA8
+          0x20
+          
+            
+              WDT_WKEY
+              the key of rtc wdt
+              0
+              32
+              read-write
+            
+          
+        
+        
+          SWD_CONF
+          rtc configure register
+          0xAC
+          0x20
+          0x04B00000
+          
+            
+              SWD_RESET_FLAG
+              swd reset flag
+              0
+              1
+              read-only
+            
+            
+              SWD_FEED_INT
+              swd interrupt for feeding
+              1
+              1
+              read-only
+            
+            
+              SWD_BYPASS_RST
+              Bypass swd rst
+              17
+              1
+              read-write
+            
+            
+              SWD_SIGNAL_WIDTH
+              adjust signal width send to swd
+              18
+              10
+              read-write
+            
+            
+              SWD_RST_FLAG_CLR
+              reset swd reset flag
+              28
+              1
+              write-only
+            
+            
+              SWD_FEED
+              Sw feed swd
+              29
+              1
+              write-only
+            
+            
+              SWD_DISABLE
+              disabel SWD
+              30
+              1
+              read-write
+            
+            
+              SWD_AUTO_FEED_EN
+              automatically feed swd when int comes
+              31
+              1
+              read-write
+            
+          
+        
+        
+          SWD_WPROTECT
+          rtc configure register
+          0xB0
+          0x20
+          
+            
+              SWD_WKEY
+              the key of super wdt
+              0
+              32
+              read-write
+            
+          
+        
+        
+          SW_CPU_STALL
+          rtc configure register
+          0xB4
+          0x20
+          
+            
+              SW_STALL_APPCPU_C1
+              {reg_sw_stall_appcpu_c1[5:0]
+              20
+              6
+              read-write
+            
+            
+              SW_STALL_PROCPU_C1
+              stall cpu by software
+              26
+              6
+              read-write
+            
+          
+        
+        
+          STORE4
+          rtc configure register
+          0xB8
+          0x20
+          
+            
+              RTC_SCRATCH4
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE5
+          rtc configure register
+          0xBC
+          0x20
+          
+            
+              RTC_SCRATCH5
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE6
+          rtc configure register
+          0xC0
+          0x20
+          
+            
+              RTC_SCRATCH6
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          STORE7
+          rtc configure register
+          0xC4
+          0x20
+          
+            
+              RTC_SCRATCH7
+              reserved register
+              0
+              32
+              read-write
+            
+          
+        
+        
+          LOW_POWER_ST
+          rtc configure register
+          0xC8
+          0x20
+          
+            
+              XPD_ROM0
+              rom0 power down
+              0
+              1
+              read-only
+            
+            
+              XPD_DIG_DCDC
+              External DCDC power down
+              2
+              1
+              read-only
+            
+            
+              RTC_PERI_ISO
+              rtc peripheral iso
+              3
+              1
+              read-only
+            
+            
+              XPD_RTC_PERI
+              rtc peripheral power down
+              4
+              1
+              read-only
+            
+            
+              WIFI_ISO
+              wifi iso
+              5
+              1
+              read-only
+            
+            
+              XPD_WIFI
+              wifi wrap power down
+              6
+              1
+              read-only
+            
+            
+              DIG_ISO
+              digital wrap iso
+              7
+              1
+              read-only
+            
+            
+              XPD_DIG
+              digital wrap power down
+              8
+              1
+              read-only
+            
+            
+              RTC_TOUCH_STATE_START
+              touch should start to work
+              9
+              1
+              read-only
+            
+            
+              RTC_TOUCH_STATE_SWITCH
+              touch is about to working. Switch rtc main state
+              10
+              1
+              read-only
+            
+            
+              RTC_TOUCH_STATE_SLP
+              touch is in sleep state
+              11
+              1
+              read-only
+            
+            
+              RTC_TOUCH_STATE_DONE
+              touch is done
+              12
+              1
+              read-only
+            
+            
+              RTC_COCPU_STATE_START
+              ulp/cocpu should start to work
+              13
+              1
+              read-only
+            
+            
+              RTC_COCPU_STATE_SWITCH
+              ulp/cocpu is about to working. Switch rtc main state
+              14
+              1
+              read-only
+            
+            
+              RTC_COCPU_STATE_SLP
+              ulp/cocpu is in sleep state
+              15
+              1
+              read-only
+            
+            
+              RTC_COCPU_STATE_DONE
+              ulp/cocpu is done
+              16
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_XTAL_ISO
+              no use any more
+              17
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_PLL_ON
+              rtc main state machine is in states that pll should be running
+              18
+              1
+              read-only
+            
+            
+              RTC_RDY_FOR_WAKEUP
+              rtc is ready to receive wake up trigger from wake up source
+              19
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_WAIT_END
+              rtc main state machine has been waited for some cycles
+              20
+              1
+              read-only
+            
+            
+              RTC_IN_WAKEUP_STATE
+              rtc main state machine is in the states of wakeup process
+              21
+              1
+              read-only
+            
+            
+              RTC_IN_LOW_POWER_STATE
+              rtc main state machine is in the states of low power
+              22
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_IN_WAIT_8M
+              rtc main state machine is in wait 8m state
+              23
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_IN_WAIT_PLL
+              rtc main state machine is in wait pll state
+              24
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_IN_WAIT_XTL
+              rtc main state machine is in wait xtal state
+              25
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_IN_SLP
+              rtc main state machine is in sleep state
+              26
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE_IN_IDLE
+              rtc main state machine is in idle state
+              27
+              1
+              read-only
+            
+            
+              RTC_MAIN_STATE
+              rtc main state machine status
+              28
+              4
+              read-only
+            
+          
+        
+        
+          DIAG0
+          rtc configure register
+          0xCC
+          0x20
+          
+            
+              RTC_LOW_POWER_DIAG1
+              0
+              32
+              read-only
+            
+          
+        
+        
+          PAD_HOLD
+          rtc configure register
+          0xD0
+          0x20
+          
+            
+              RTC_GPIO_PIN0_HOLD
+              the hold configure of rtc gpio0
+              0
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN1_HOLD
+              the hold configure of rtc gpio1
+              1
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN2_HOLD
+              the hold configure of rtc gpio2
+              2
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN3_HOLD
+              the hold configure of rtc gpio3
+              3
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN4_HOLD
+              the hold configure of rtc gpio4
+              4
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN5_HOLD
+              the hold configure of rtc gpio5
+              5
+              1
+              read-write
+            
+          
+        
+        
+          DIG_PAD_HOLD
+          rtc configure register
+          0xD4
+          0x20
+          
+            
+              DIG_PAD_HOLD
+              the configure of digital pad
+              0
+              32
+              read-write
+            
+          
+        
+        
+          BROWN_OUT
+          rtc configure register
+          0xD8
+          0x20
+          0x43FF0010
+          
+            
+              INT_WAIT
+              brown out interrupt wait cycles
+              4
+              10
+              read-write
+            
+            
+              CLOSE_FLASH_ENA
+              enable close flash when brown out happens
+              14
+              1
+              read-write
+            
+            
+              PD_RF_ENA
+              enable power down RF when brown out happens
+              15
+              1
+              read-write
+            
+            
+              RST_WAIT
+              brown out reset wait cycles
+              16
+              10
+              read-write
+            
+            
+              RST_ENA
+              enable brown out reset
+              26
+              1
+              read-write
+            
+            
+              RST_SEL
+              1:  4-pos reset
+              27
+              1
+              read-write
+            
+            
+              ANA_RST_EN
+              brown_out origin reset enable
+              28
+              1
+              read-write
+            
+            
+              CNT_CLR
+              clear brown out counter
+              29
+              1
+              write-only
+            
+            
+              ENA
+              enable brown out
+              30
+              1
+              read-write
+            
+            
+              DET
+              the flag of brown det from analog
+              31
+              1
+              read-only
+            
+          
+        
+        
+          TIME_LOW1
+          rtc configure register
+          0xDC
+          0x20
+          
+            
+              RTC_TIMER_VALUE1_LOW
+              RTC timer low 32 bits
+              0
+              32
+              read-only
+            
+          
+        
+        
+          TIME_HIGH1
+          rtc configure register
+          0xE0
+          0x20
+          
+            
+              RTC_TIMER_VALUE1_HIGH
+              RTC timer high 16 bits
+              0
+              16
+              read-only
+            
+          
+        
+        
+          XTAL32K_CLK_FACTOR
+          rtc configure register
+          0xE4
+          0x20
+          
+            
+              XTAL32K_CLK_FACTOR
+              xtal 32k watch dog backup clock factor
+              0
+              32
+              read-write
+            
+          
+        
+        
+          XTAL32K_CONF
+          rtc configure register
+          0xE8
+          0x20
+          0x0FF00000
+          
+            
+              XTAL32K_RETURN_WAIT
+              cycles to wait to return noral xtal 32k
+              0
+              4
+              read-write
+            
+            
+              XTAL32K_RESTART_WAIT
+              cycles to wait to repower on xtal 32k
+              4
+              16
+              read-write
+            
+            
+              XTAL32K_WDT_TIMEOUT
+              If no clock detected for this amount of time
+              20
+              8
+              read-write
+            
+            
+              XTAL32K_STABLE_THRES
+              if restarted xtal32k period is smaller than this
+              28
+              4
+              read-write
+            
+          
+        
+        
+          USB_CONF
+          rtc configure register
+          0xEC
+          0x20
+          
+            
+              IO_MUX_RESET_DISABLE
+              disable io_mux reset
+              18
+              1
+              read-write
+            
+          
+        
+        
+          SLP_REJECT_CAUSE
+          RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG
+          0xF0
+          0x20
+          
+            
+              REJECT_CAUSE
+              sleep reject cause
+              0
+              18
+              read-only
+            
+          
+        
+        
+          OPTION1
+          rtc configure register
+          0xF4
+          0x20
+          
+            
+              FORCE_DOWNLOAD_BOOT
+              force chip entry download mode
+              0
+              1
+              read-write
+            
+          
+        
+        
+          SLP_WAKEUP_CAUSE
+          RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG
+          0xF8
+          0x20
+          
+            
+              WAKEUP_CAUSE
+              sleep wakeup cause
+              0
+              17
+              read-only
+            
+          
+        
+        
+          ULP_CP_TIMER_1
+          rtc configure register
+          0xFC
+          0x20
+          0x0000C800
+          
+            
+              ULP_CP_TIMER_SLP_CYCLE
+              sleep cycles for ULP-coprocessor timer
+              8
+              24
+              read-write
+            
+          
+        
+        
+          INT_ENA_RTC_W1TS
+          rtc configure register
+          0x100
+          0x20
+          
+            
+              SLP_WAKEUP_INT_ENA_W1TS
+              enable sleep wakeup interrupt
+              0
+              1
+              write-only
+            
+            
+              SLP_REJECT_INT_ENA_W1TS
+              enable sleep reject interrupt
+              1
+              1
+              write-only
+            
+            
+              RTC_WDT_INT_ENA_W1TS
+              enable RTC WDT interrupt
+              3
+              1
+              write-only
+            
+            
+              RTC_BROWN_OUT_INT_ENA_W1TS
+              enable brown out interrupt
+              9
+              1
+              write-only
+            
+            
+              RTC_MAIN_TIMER_INT_ENA_W1TS
+              enable RTC main timer interrupt
+              10
+              1
+              write-only
+            
+            
+              RTC_SWD_INT_ENA_W1TS
+              enable super watch dog interrupt
+              15
+              1
+              write-only
+            
+            
+              RTC_XTAL32K_DEAD_INT_ENA_W1TS
+              enable xtal32k_dead  interrupt
+              16
+              1
+              write-only
+            
+            
+              RTC_GLITCH_DET_INT_ENA_W1TS
+              enbale gitch det interrupt
+              19
+              1
+              write-only
+            
+            
+              RTC_BBPLL_CAL_INT_ENA_W1TS
+              enbale bbpll cal interrupt
+              20
+              1
+              write-only
+            
+          
+        
+        
+          INT_ENA_RTC_W1TC
+          rtc configure register
+          0x104
+          0x20
+          
+            
+              SLP_WAKEUP_INT_ENA_W1TC
+              clear sleep wakeup interrupt enable
+              0
+              1
+              write-only
+            
+            
+              SLP_REJECT_INT_ENA_W1TC
+              clear sleep reject interrupt enable
+              1
+              1
+              write-only
+            
+            
+              RTC_WDT_INT_ENA_W1TC
+              clear RTC WDT interrupt enable
+              3
+              1
+              write-only
+            
+            
+              RTC_BROWN_OUT_INT_ENA_W1TC
+              clear brown out interrupt enable
+              9
+              1
+              write-only
+            
+            
+              RTC_MAIN_TIMER_INT_ENA_W1TC
+              Clear RTC main timer interrupt enable
+              10
+              1
+              write-only
+            
+            
+              RTC_SWD_INT_ENA_W1TC
+              clear super watch dog interrupt enable
+              15
+              1
+              write-only
+            
+            
+              RTC_XTAL32K_DEAD_INT_ENA_W1TC
+              clear xtal32k_dead  interrupt enable
+              16
+              1
+              write-only
+            
+            
+              RTC_GLITCH_DET_INT_ENA_W1TC
+              clear gitch det interrupt enable
+              19
+              1
+              write-only
+            
+            
+              RTC_BBPLL_CAL_INT_ENA_W1TC
+              clear bbpll cal interrupt enable
+              20
+              1
+              write-only
+            
+          
+        
+        
+          RETENTION_CTRL
+          rtc configure register
+          0x108
+          0x20
+          0xA0D00000
+          
+            
+              RETENTION_CLK_SEL
+              Retention clk sel
+              18
+              1
+              read-write
+            
+            
+              RETENTION_DONE_WAIT
+              Retention done wait time
+              19
+              3
+              read-write
+            
+            
+              RETENTION_CLKOFF_WAIT
+              Retention clkoff wait time
+              22
+              4
+              read-write
+            
+            
+              RETENTION_EN
+              enable cpu retention when light sleep
+              26
+              1
+              read-write
+            
+            
+              RETENTION_WAIT
+              wait cycles for rention operation
+              27
+              5
+              read-write
+            
+          
+        
+        
+          FIB_SEL
+          rtc configure register
+          0x10C
+          0x20
+          0x00000007
+          
+            
+              RTC_FIB_SEL
+              select use analog fib signal
+              0
+              3
+              read-write
+            
+          
+        
+        
+          GPIO_WAKEUP
+          rtc configure register
+          0x110
+          0x20
+          
+            
+              RTC_GPIO_WAKEUP_STATUS
+              rtc gpio wakeup flag
+              0
+              6
+              read-only
+            
+            
+              RTC_GPIO_WAKEUP_STATUS_CLR
+              clear rtc gpio wakeup flag
+              6
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN_CLK_GATE
+              enable rtc io clk gate
+              7
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN5_INT_TYPE
+              configure gpio wakeup type
+              8
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN4_INT_TYPE
+              configure gpio wakeup type
+              11
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN3_INT_TYPE
+              configure gpio wakeup type
+              14
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN2_INT_TYPE
+              configure gpio wakeup type
+              17
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN1_INT_TYPE
+              configure gpio wakeup type
+              20
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN0_INT_TYPE
+              configure gpio wakeup type
+              23
+              3
+              read-write
+            
+            
+              RTC_GPIO_PIN5_WAKEUP_ENABLE
+              enable wakeup from rtc gpio5
+              26
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN4_WAKEUP_ENABLE
+              enable wakeup from rtc gpio4
+              27
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN3_WAKEUP_ENABLE
+              enable wakeup from rtc gpio3
+              28
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN2_WAKEUP_ENABLE
+              enable wakeup from rtc gpio2
+              29
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN1_WAKEUP_ENABLE
+              enable wakeup from rtc gpio1
+              30
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN0_WAKEUP_ENABLE
+              enable wakeup from rtc gpio0
+              31
+              1
+              read-write
+            
+          
+        
+        
+          DBG_SEL
+          rtc configure register
+          0x114
+          0x20
+          
+            
+              RTC_DEBUG_12M_NO_GATING
+              use for debug
+              1
+              1
+              read-write
+            
+            
+              RTC_DEBUG_BIT_SEL
+              use for debug
+              2
+              5
+              read-write
+            
+            
+              RTC_DEBUG_SEL0
+              use for debug
+              7
+              5
+              read-write
+            
+            
+              RTC_DEBUG_SEL1
+              use for debug
+              12
+              5
+              read-write
+            
+            
+              RTC_DEBUG_SEL2
+              use for debug
+              17
+              5
+              read-write
+            
+            
+              RTC_DEBUG_SEL3
+              use for debug
+              22
+              5
+              read-write
+            
+            
+              RTC_DEBUG_SEL4
+              use for debug
+              27
+              5
+              read-write
+            
+          
+        
+        
+          DBG_MAP
+          rtc configure register
+          0x118
+          0x20
+          
+            
+              RTC_GPIO_PIN5_MUX_SEL
+              use for debug
+              2
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN4_MUX_SEL
+              use for debug
+              3
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN3_MUX_SEL
+              use for debug
+              4
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN2_MUX_SEL
+              use for debug
+              5
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN1_MUX_SEL
+              use for debug
+              6
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN0_MUX_SEL
+              use for debug
+              7
+              1
+              read-write
+            
+            
+              RTC_GPIO_PIN5_FUN_SEL
+              use for debug
+              8
+              4
+              read-write
+            
+            
+              RTC_GPIO_PIN4_FUN_SEL
+              use for debug
+              12
+              4
+              read-write
+            
+            
+              RTC_GPIO_PIN3_FUN_SEL
+              use for debug
+              16
+              4
+              read-write
+            
+            
+              RTC_GPIO_PIN2_FUN_SEL
+              use for debug
+              20
+              4
+              read-write
+            
+            
+              RTC_GPIO_PIN1_FUN_SEL
+              use for debug
+              24
+              4
+              read-write
+            
+            
+              RTC_GPIO_PIN0_FUN_SEL
+              use for debug
+              28
+              4
+              read-write
+            
+          
+        
+        
+          SENSOR_CTRL
+          rtc configure register
+          0x11C
+          0x20
+          
+            
+              SAR2_PWDET_CCT
+              reg_sar2_pwdet_cct
+              27
+              3
+              read-write
+            
+            
+              FORCE_XPD_SAR
+              force power up SAR
+              30
+              2
+              read-write
+            
+          
+        
+        
+          DBG_SAR_SEL
+          rtc configure register
+          0x120
+          0x20
+          
+            
+              SAR_DEBUG_SEL
+              use for debug
+              27
+              5
+              read-write
+            
+          
+        
+        
+          PG_CTRL
+          rtc configure register
+          0x124
+          0x20
+          
+            
+              POWER_GLITCH_DSENSE
+              power glitch desense
+              26
+              2
+              read-write
+            
+            
+              POWER_GLITCH_FORCE_PD
+              force disable power glitch
+              28
+              1
+              read-write
+            
+            
+              POWER_GLITCH_FORCE_PU
+              force enable power glitch
+              29
+              1
+              read-write
+            
+            
+              POWER_GLITCH_EFUSE_SEL
+              use efuse value control power glitch enable
+              30
+              1
+              read-write
+            
+            
+              POWER_GLITCH_EN
+              enable power glitch
+              31
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          rtc configure register
+          0x1FC
+          0x20
+          0x02007270
+          
+            
+              RTC_CNTL_DATE
+              verision
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SENSITIVE
+      Sensitive
+      SENSITIVE
+      0x600C1000
+      
+        0x0
+        0x178
+        registers
+      
+      
+        
+          ROM_TABLE_LOCK
+          SENSITIVE_ROM_TABLE_LOCK_REG
+          0x0
+          0x20
+          
+            
+              ROM_TABLE_LOCK
+              rom_table_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          ROM_TABLE
+          SENSITIVE_ROM_TABLE_REG
+          0x4
+          0x20
+          
+            
+              ROM_TABLE
+              rom_table
+              0
+              32
+              read-write
+            
+          
+        
+        
+          PRIVILEGE_MODE_SEL_LOCK
+          SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
+          0x8
+          0x20
+          
+            
+              PRIVILEGE_MODE_SEL_LOCK
+              privilege_mode_sel_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          PRIVILEGE_MODE_SEL
+          SENSITIVE_PRIVILEGE_MODE_SEL_REG
+          0xC
+          0x20
+          
+            
+              PRIVILEGE_MODE_SEL
+              privilege_mode_sel
+              0
+              1
+              read-write
+            
+          
+        
+        
+          APB_PERIPHERAL_ACCESS_0
+          SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
+          0x10
+          0x20
+          
+            
+              APB_PERIPHERAL_ACCESS_LOCK
+              apb_peripheral_access_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          APB_PERIPHERAL_ACCESS_1
+          SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
+          0x14
+          0x20
+          0x00000001
+          
+            
+              APB_PERIPHERAL_ACCESS_SPLIT_BURST
+              apb_peripheral_access_split_burst
+              0
+              1
+              read-write
+            
+          
+        
+        
+          INTERNAL_SRAM_USAGE_0
+          SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
+          0x18
+          0x20
+          
+            
+              INTERNAL_SRAM_USAGE_LOCK
+              internal_sram_usage_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          INTERNAL_SRAM_USAGE_1
+          SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
+          0x1C
+          0x20
+          0x0000000F
+          
+            
+              INTERNAL_SRAM_USAGE_CPU_CACHE
+              internal_sram_usage_cpu_cache
+              0
+              1
+              read-write
+            
+            
+              INTERNAL_SRAM_USAGE_CPU_SRAM
+              internal_sram_usage_cpu_sram
+              1
+              3
+              read-write
+            
+          
+        
+        
+          INTERNAL_SRAM_USAGE_3
+          SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
+          0x20
+          0x20
+          
+            
+              INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM
+              internal_sram_usage_mac_dump_sram
+              0
+              3
+              read-write
+            
+            
+              INTERNAL_SRAM_ALLOC_MAC_DUMP
+              internal_sram_alloc_mac_dump
+              3
+              1
+              read-write
+            
+          
+        
+        
+          INTERNAL_SRAM_USAGE_4
+          SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
+          0x24
+          0x20
+          
+            
+              INTERNAL_SRAM_USAGE_LOG_SRAM
+              internal_sram_usage_log_sram
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_TAG_ACCESS_0
+          SENSITIVE_CACHE_TAG_ACCESS_0_REG
+          0x28
+          0x20
+          
+            
+              CACHE_TAG_ACCESS_LOCK
+              cache_tag_access_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_TAG_ACCESS_1
+          SENSITIVE_CACHE_TAG_ACCESS_1_REG
+          0x2C
+          0x20
+          0x0000000F
+          
+            
+              PRO_I_TAG_RD_ACS
+              pro_i_tag_rd_acs
+              0
+              1
+              read-write
+            
+            
+              PRO_I_TAG_WR_ACS
+              pro_i_tag_wr_acs
+              1
+              1
+              read-write
+            
+            
+              PRO_D_TAG_RD_ACS
+              pro_d_tag_rd_acs
+              2
+              1
+              read-write
+            
+            
+              PRO_D_TAG_WR_ACS
+              pro_d_tag_wr_acs
+              3
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_MMU_ACCESS_0
+          SENSITIVE_CACHE_MMU_ACCESS_0_REG
+          0x30
+          0x20
+          
+            
+              CACHE_MMU_ACCESS_LOCK
+              cache_mmu_access_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_MMU_ACCESS_1
+          SENSITIVE_CACHE_MMU_ACCESS_1_REG
+          0x34
+          0x20
+          0x00000003
+          
+            
+              PRO_MMU_RD_ACS
+              pro_mmu_rd_acs
+              0
+              1
+              read-write
+            
+            
+              PRO_MMU_WR_ACS
+              pro_mmu_wr_acs
+              1
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_SPI2_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
+          0x38
+          0x20
+          
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK
+              dma_apbperi_spi2_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_SPI2_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
+          0x3C
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
+          0x40
+          0x20
+          
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK
+              dma_apbperi_uchi0_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
+          0x44
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_I2S0_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
+          0x48
+          0x20
+          
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK
+              dma_apbperi_i2s0_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_I2S0_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
+          0x4C
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_MAC_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
+          0x50
+          0x20
+          
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK
+              dma_apbperi_mac_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_MAC_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
+          0x54
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_mac_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_mac_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_mac_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_mac_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_mac_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_mac_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_mac_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_mac_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
+          0x58
+          0x20
+          
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK
+              dma_apbperi_backup_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
+          0x5C
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_backup_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_backup_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_backup_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_backup_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_backup_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_backup_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_backup_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_backup_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_LC_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
+          0x60
+          0x20
+          
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK
+              dma_apbperi_lc_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_LC_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
+          0x64
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_lc_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_lc_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_lc_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_lc_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_lc_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_lc_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_lc_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_lc_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_AES_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
+          0x68
+          0x20
+          
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK
+              dma_apbperi_aes_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_AES_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
+          0x6C
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_aes_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_aes_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_aes_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_aes_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_aes_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_aes_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_aes_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_aes_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_SHA_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
+          0x70
+          0x20
+          
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK
+              dma_apbperi_sha_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_SHA_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
+          0x74
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_sha_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_sha_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_sha_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_sha_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_sha_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_sha_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_sha_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_sha_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0
+          SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
+          0x78
+          0x20
+          
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK
+              dma_apbperi_adc_dac_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1
+          SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
+          0x7C
+          0x20
+          0x000FF0FF
+          
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_PMS_MONITOR_0
+          SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
+          0x80
+          0x20
+          
+            
+              DMA_APBPERI_PMS_MONITOR_LOCK
+              dma_apbperi_pms_monitor_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_PMS_MONITOR_1
+          SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
+          0x84
+          0x20
+          0x00000003
+          
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR
+              dma_apbperi_pms_monitor_violate_clr
+              0
+              1
+              read-write
+            
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_EN
+              dma_apbperi_pms_monitor_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          DMA_APBPERI_PMS_MONITOR_2
+          SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
+          0x88
+          0x20
+          
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR
+              dma_apbperi_pms_monitor_violate_intr
+              0
+              1
+              read-only
+            
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD
+              dma_apbperi_pms_monitor_violate_status_world
+              1
+              2
+              read-only
+            
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR
+              dma_apbperi_pms_monitor_violate_status_addr
+              3
+              24
+              read-only
+            
+          
+        
+        
+          DMA_APBPERI_PMS_MONITOR_3
+          SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
+          0x8C
+          0x20
+          
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR
+              dma_apbperi_pms_monitor_violate_status_wr
+              0
+              1
+              read-only
+            
+            
+              DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN
+              dma_apbperi_pms_monitor_violate_status_byteen
+              1
+              4
+              read-only
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
+          0x90
+          0x20
+          
+            
+              CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK
+              core_x_iram0_dram0_dma_split_line_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
+          0x94
+          0x20
+          
+            
+              CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0
+              core_x_iram0_dram0_dma_sram_category_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1
+              core_x_iram0_dram0_dma_sram_category_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2
+              core_x_iram0_dram0_dma_sram_category_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR
+              core_x_iram0_dram0_dma_sram_splitaddr
+              14
+              8
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
+          0x98
+          0x20
+          
+            
+              CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0
+              core_x_iram0_sram_line_0_category_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1
+              core_x_iram0_sram_line_0_category_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2
+              core_x_iram0_sram_line_0_category_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR
+              core_x_iram0_sram_line_0_splitaddr
+              14
+              8
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
+          0x9C
+          0x20
+          
+            
+              CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0
+              core_x_iram0_sram_line_1_category_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1
+              core_x_iram0_sram_line_1_category_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2
+              core_x_iram0_sram_line_1_category_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR
+              core_x_iram0_sram_line_1_splitaddr
+              14
+              8
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
+          0xA0
+          0x20
+          
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0
+              core_x_dram0_dma_sram_line_0_category_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1
+              core_x_dram0_dma_sram_line_0_category_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2
+              core_x_dram0_dma_sram_line_0_category_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR
+              core_x_dram0_dma_sram_line_0_splitaddr
+              14
+              8
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5
+          SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
+          0xA4
+          0x20
+          
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0
+              core_x_dram0_dma_sram_line_1_category_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1
+              core_x_dram0_dma_sram_line_1_category_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2
+              core_x_dram0_dma_sram_line_1_category_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR
+              core_x_dram0_dma_sram_line_1_splitaddr
+              14
+              8
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_PMS_CONSTRAIN_0
+          SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+          0xA8
+          0x20
+          
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_LOCK
+              core_x_iram0_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_PMS_CONSTRAIN_1
+          SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
+          0xAC
+          0x20
+          0x001C7FFF
+          
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              core_x_iram0_pms_constrain_sram_world_1_pms_0
+              0
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              core_x_iram0_pms_constrain_sram_world_1_pms_1
+              3
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              core_x_iram0_pms_constrain_sram_world_1_pms_2
+              6
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              core_x_iram0_pms_constrain_sram_world_1_pms_3
+              9
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0
+              core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0
+              12
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS
+              core_x_iram0_pms_constrain_rom_world_1_pms
+              18
+              3
+              read-write
+            
+          
+        
+        
+          CORE_X_IRAM0_PMS_CONSTRAIN_2
+          SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
+          0xB0
+          0x20
+          0x001C7FFF
+          
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              core_x_iram0_pms_constrain_sram_world_0_pms_0
+              0
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              core_x_iram0_pms_constrain_sram_world_0_pms_1
+              3
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              core_x_iram0_pms_constrain_sram_world_0_pms_2
+              6
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              core_x_iram0_pms_constrain_sram_world_0_pms_3
+              9
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0
+              core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0
+              12
+              3
+              read-write
+            
+            
+              CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS
+              core_x_iram0_pms_constrain_rom_world_0_pms
+              18
+              3
+              read-write
+            
+          
+        
+        
+          CORE_0_IRAM0_PMS_MONITOR_0
+          SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
+          0xB4
+          0x20
+          
+            
+              CORE_0_IRAM0_PMS_MONITOR_LOCK
+              core_0_iram0_pms_monitor_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_IRAM0_PMS_MONITOR_1
+          SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
+          0xB8
+          0x20
+          0x00000003
+          
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR
+              core_0_iram0_pms_monitor_violate_clr
+              0
+              1
+              read-write
+            
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN
+              core_0_iram0_pms_monitor_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_IRAM0_PMS_MONITOR_2
+          SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
+          0xBC
+          0x20
+          
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR
+              core_0_iram0_pms_monitor_violate_intr
+              0
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR
+              core_0_iram0_pms_monitor_violate_status_wr
+              1
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE
+              core_0_iram0_pms_monitor_violate_status_loadstore
+              2
+              1
+              read-only
+            
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD
+              core_0_iram0_pms_monitor_violate_status_world
+              3
+              2
+              read-only
+            
+            
+              CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR
+              core_0_iram0_pms_monitor_violate_status_addr
+              5
+              24
+              read-only
+            
+          
+        
+        
+          CORE_X_DRAM0_PMS_CONSTRAIN_0
+          SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+          0xC0
+          0x20
+          
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_LOCK
+              core_x_dram0_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_X_DRAM0_PMS_CONSTRAIN_1
+          SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
+          0xC4
+          0x20
+          0x0F0FF0FF
+          
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0
+              core_x_dram0_pms_constrain_sram_world_0_pms_0
+              0
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1
+              core_x_dram0_pms_constrain_sram_world_0_pms_1
+              2
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2
+              core_x_dram0_pms_constrain_sram_world_0_pms_2
+              4
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3
+              core_x_dram0_pms_constrain_sram_world_0_pms_3
+              6
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0
+              core_x_dram0_pms_constrain_sram_world_1_pms_0
+              12
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1
+              core_x_dram0_pms_constrain_sram_world_1_pms_1
+              14
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2
+              core_x_dram0_pms_constrain_sram_world_1_pms_2
+              16
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3
+              core_x_dram0_pms_constrain_sram_world_1_pms_3
+              18
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS
+              core_x_dram0_pms_constrain_rom_world_0_pms
+              24
+              2
+              read-write
+            
+            
+              CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS
+              core_x_dram0_pms_constrain_rom_world_1_pms
+              26
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_DRAM0_PMS_MONITOR_0
+          SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
+          0xC8
+          0x20
+          
+            
+              CORE_0_DRAM0_PMS_MONITOR_LOCK
+              core_0_dram0_pms_monitor_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_DRAM0_PMS_MONITOR_1
+          SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
+          0xCC
+          0x20
+          0x00000003
+          
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR
+              core_0_dram0_pms_monitor_violate_clr
+              0
+              1
+              read-write
+            
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN
+              core_0_dram0_pms_monitor_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_DRAM0_PMS_MONITOR_2
+          SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
+          0xD0
+          0x20
+          
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR
+              core_0_dram0_pms_monitor_violate_intr
+              0
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK
+              core_0_dram0_pms_monitor_violate_status_lock
+              1
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD
+              core_0_dram0_pms_monitor_violate_status_world
+              2
+              2
+              read-only
+            
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR
+              core_0_dram0_pms_monitor_violate_status_addr
+              4
+              24
+              read-only
+            
+          
+        
+        
+          CORE_0_DRAM0_PMS_MONITOR_3
+          SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
+          0xD4
+          0x20
+          
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR
+              core_0_dram0_pms_monitor_violate_status_wr
+              0
+              1
+              read-only
+            
+            
+              CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN
+              core_0_dram0_pms_monitor_violate_status_byteen
+              1
+              4
+              read-only
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_0
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
+          0xD8
+          0x20
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_LOCK
+              core_0_pif_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_1
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
+          0xDC
+          0x20
+          0xCF0FFFFF
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART
+              core_0_pif_pms_constrain_world_0_uart
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1
+              core_0_pif_pms_constrain_world_0_g0spi_1
+              2
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0
+              core_0_pif_pms_constrain_world_0_g0spi_0
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO
+              core_0_pif_pms_constrain_world_0_gpio
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2
+              core_0_pif_pms_constrain_world_0_fe2
+              8
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE
+              core_0_pif_pms_constrain_world_0_fe
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER
+              core_0_pif_pms_constrain_world_0_timer
+              12
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC
+              core_0_pif_pms_constrain_world_0_rtc
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX
+              core_0_pif_pms_constrain_world_0_io_mux
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG
+              core_0_pif_pms_constrain_world_0_wdg
+              18
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC
+              core_0_pif_pms_constrain_world_0_misc
+              24
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C
+              core_0_pif_pms_constrain_world_0_i2c
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1
+              core_0_pif_pms_constrain_world_0_uart1
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_2
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
+          0xE0
+          0x20
+          0xFCC30CF3
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT
+              core_0_pif_pms_constrain_world_0_bt
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0
+              core_0_pif_pms_constrain_world_0_i2c_ext0
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0
+              core_0_pif_pms_constrain_world_0_uhci0
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT
+              core_0_pif_pms_constrain_world_0_rmt
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC
+              core_0_pif_pms_constrain_world_0_ledc
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB
+              core_0_pif_pms_constrain_world_0_bb
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP
+              core_0_pif_pms_constrain_world_0_timergroup
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1
+              core_0_pif_pms_constrain_world_0_timergroup1
+              28
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER
+              core_0_pif_pms_constrain_world_0_systimer
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_3
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
+          0xE4
+          0x20
+          0x3CC0CC33
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2
+              core_0_pif_pms_constrain_world_0_spi_2
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL
+              core_0_pif_pms_constrain_world_0_apb_ctrl
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN
+              core_0_pif_pms_constrain_world_0_can
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1
+              core_0_pif_pms_constrain_world_0_i2s1
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT
+              core_0_pif_pms_constrain_world_0_rwbt
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC
+              core_0_pif_pms_constrain_world_0_wifimac
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR
+              core_0_pif_pms_constrain_world_0_pwr
+              28
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_4
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
+          0xE8
+          0x20
+          0xFFFFF3FC
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP
+              core_0_pif_pms_constrain_world_0_usb_wrap
+              2
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI
+              core_0_pif_pms_constrain_world_0_crypto_peri
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA
+              core_0_pif_pms_constrain_world_0_crypto_dma
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC
+              core_0_pif_pms_constrain_world_0_apb_adc
+              8
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR
+              core_0_pif_pms_constrain_world_0_bt_pwr
+              12
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE
+              core_0_pif_pms_constrain_world_0_usb_device
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM
+              core_0_pif_pms_constrain_world_0_system
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE
+              core_0_pif_pms_constrain_world_0_sensitive
+              18
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT
+              core_0_pif_pms_constrain_world_0_interrupt
+              20
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY
+              core_0_pif_pms_constrain_world_0_dma_copy
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG
+              core_0_pif_pms_constrain_world_0_cache_config
+              24
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD
+              core_0_pif_pms_constrain_world_0_ad
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO
+              core_0_pif_pms_constrain_world_0_dio
+              28
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER
+              core_0_pif_pms_constrain_world_0_world_controller
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_5
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
+          0xEC
+          0x20
+          0xCF0FFFFF
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART
+              core_0_pif_pms_constrain_world_1_uart
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1
+              core_0_pif_pms_constrain_world_1_g0spi_1
+              2
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0
+              core_0_pif_pms_constrain_world_1_g0spi_0
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO
+              core_0_pif_pms_constrain_world_1_gpio
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2
+              core_0_pif_pms_constrain_world_1_fe2
+              8
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE
+              core_0_pif_pms_constrain_world_1_fe
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER
+              core_0_pif_pms_constrain_world_1_timer
+              12
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC
+              core_0_pif_pms_constrain_world_1_rtc
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX
+              core_0_pif_pms_constrain_world_1_io_mux
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG
+              core_0_pif_pms_constrain_world_1_wdg
+              18
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC
+              core_0_pif_pms_constrain_world_1_misc
+              24
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C
+              core_0_pif_pms_constrain_world_1_i2c
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1
+              core_0_pif_pms_constrain_world_1_uart1
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_6
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
+          0xF0
+          0x20
+          0xFCC30CF3
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT
+              core_0_pif_pms_constrain_world_1_bt
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0
+              core_0_pif_pms_constrain_world_1_i2c_ext0
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0
+              core_0_pif_pms_constrain_world_1_uhci0
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT
+              core_0_pif_pms_constrain_world_1_rmt
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC
+              core_0_pif_pms_constrain_world_1_ledc
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB
+              core_0_pif_pms_constrain_world_1_bb
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP
+              core_0_pif_pms_constrain_world_1_timergroup
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1
+              core_0_pif_pms_constrain_world_1_timergroup1
+              28
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER
+              core_0_pif_pms_constrain_world_1_systimer
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_7
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
+          0xF4
+          0x20
+          0x3CC0CC33
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2
+              core_0_pif_pms_constrain_world_1_spi_2
+              0
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL
+              core_0_pif_pms_constrain_world_1_apb_ctrl
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN
+              core_0_pif_pms_constrain_world_1_can
+              10
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1
+              core_0_pif_pms_constrain_world_1_i2s1
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT
+              core_0_pif_pms_constrain_world_1_rwbt
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC
+              core_0_pif_pms_constrain_world_1_wifimac
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR
+              core_0_pif_pms_constrain_world_1_pwr
+              28
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_8
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
+          0xF8
+          0x20
+          0xFFFFF3FC
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP
+              core_0_pif_pms_constrain_world_1_usb_wrap
+              2
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI
+              core_0_pif_pms_constrain_world_1_crypto_peri
+              4
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA
+              core_0_pif_pms_constrain_world_1_crypto_dma
+              6
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC
+              core_0_pif_pms_constrain_world_1_apb_adc
+              8
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR
+              core_0_pif_pms_constrain_world_1_bt_pwr
+              12
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE
+              core_0_pif_pms_constrain_world_1_usb_device
+              14
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM
+              core_0_pif_pms_constrain_world_1_system
+              16
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE
+              core_0_pif_pms_constrain_world_1_sensitive
+              18
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT
+              core_0_pif_pms_constrain_world_1_interrupt
+              20
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY
+              core_0_pif_pms_constrain_world_1_dma_copy
+              22
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG
+              core_0_pif_pms_constrain_world_1_cache_config
+              24
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD
+              core_0_pif_pms_constrain_world_1_ad
+              26
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO
+              core_0_pif_pms_constrain_world_1_dio
+              28
+              2
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER
+              core_0_pif_pms_constrain_world_1_world_controller
+              30
+              2
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_9
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
+          0xFC
+          0x20
+          0x003FFFFF
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0
+              core_0_pif_pms_constrain_rtcfast_spltaddr_world_0
+              0
+              11
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1
+              core_0_pif_pms_constrain_rtcfast_spltaddr_world_1
+              11
+              11
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_CONSTRAIN_10
+          SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
+          0x100
+          0x20
+          0x00000FFF
+          
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L
+              core_0_pif_pms_constrain_rtcfast_world_0_l
+              0
+              3
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H
+              core_0_pif_pms_constrain_rtcfast_world_0_h
+              3
+              3
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L
+              core_0_pif_pms_constrain_rtcfast_world_1_l
+              6
+              3
+              read-write
+            
+            
+              CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H
+              core_0_pif_pms_constrain_rtcfast_world_1_h
+              9
+              3
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_0
+          SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
+          0x104
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_LOCK
+              region_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_1
+          SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
+          0x108
+          0x20
+          0x00003FFF
+          
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_0
+              region_pms_constrain_world_0_area_0
+              0
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_1
+              region_pms_constrain_world_0_area_1
+              2
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_2
+              region_pms_constrain_world_0_area_2
+              4
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_3
+              region_pms_constrain_world_0_area_3
+              6
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_4
+              region_pms_constrain_world_0_area_4
+              8
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_5
+              region_pms_constrain_world_0_area_5
+              10
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_0_AREA_6
+              region_pms_constrain_world_0_area_6
+              12
+              2
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_2
+          SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
+          0x10C
+          0x20
+          0x00003FFF
+          
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_0
+              region_pms_constrain_world_1_area_0
+              0
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_1
+              region_pms_constrain_world_1_area_1
+              2
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_2
+              region_pms_constrain_world_1_area_2
+              4
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_3
+              region_pms_constrain_world_1_area_3
+              6
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_4
+              region_pms_constrain_world_1_area_4
+              8
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_5
+              region_pms_constrain_world_1_area_5
+              10
+              2
+              read-write
+            
+            
+              REGION_PMS_CONSTRAIN_WORLD_1_AREA_6
+              region_pms_constrain_world_1_area_6
+              12
+              2
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_3
+          SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
+          0x110
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_0
+              region_pms_constrain_addr_0
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_4
+          SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
+          0x114
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_1
+              region_pms_constrain_addr_1
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_5
+          SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
+          0x118
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_2
+              region_pms_constrain_addr_2
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_6
+          SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
+          0x11C
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_3
+              region_pms_constrain_addr_3
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_7
+          SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
+          0x120
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_4
+              region_pms_constrain_addr_4
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_8
+          SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
+          0x124
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_5
+              region_pms_constrain_addr_5
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_9
+          SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
+          0x128
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_6
+              region_pms_constrain_addr_6
+              0
+              30
+              read-write
+            
+          
+        
+        
+          REGION_PMS_CONSTRAIN_10
+          SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
+          0x12C
+          0x20
+          
+            
+              REGION_PMS_CONSTRAIN_ADDR_7
+              region_pms_constrain_addr_7
+              0
+              30
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_0
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
+          0x130
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_LOCK
+              core_0_pif_pms_monitor_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_1
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
+          0x134
+          0x20
+          0x00000003
+          
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR
+              core_0_pif_pms_monitor_violate_clr
+              0
+              1
+              read-write
+            
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_EN
+              core_0_pif_pms_monitor_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_2
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
+          0x138
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR
+              core_0_pif_pms_monitor_violate_intr
+              0
+              1
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0
+              core_0_pif_pms_monitor_violate_status_hport_0
+              1
+              1
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE
+              core_0_pif_pms_monitor_violate_status_hsize
+              2
+              3
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE
+              core_0_pif_pms_monitor_violate_status_hwrite
+              5
+              1
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD
+              core_0_pif_pms_monitor_violate_status_hworld
+              6
+              2
+              read-only
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_3
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
+          0x13C
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR
+              core_0_pif_pms_monitor_violate_status_haddr
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_4
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
+          0x140
+          0x20
+          0x00000003
+          
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR
+              core_0_pif_pms_monitor_nonword_violate_clr
+              0
+              1
+              read-write
+            
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN
+              core_0_pif_pms_monitor_nonword_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_5
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
+          0x144
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR
+              core_0_pif_pms_monitor_nonword_violate_intr
+              0
+              1
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE
+              core_0_pif_pms_monitor_nonword_violate_status_hsize
+              1
+              2
+              read-only
+            
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD
+              core_0_pif_pms_monitor_nonword_violate_status_hworld
+              3
+              2
+              read-only
+            
+          
+        
+        
+          CORE_0_PIF_PMS_MONITOR_6
+          SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
+          0x148
+          0x20
+          
+            
+              CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR
+              core_0_pif_pms_monitor_nonword_violate_status_haddr
+              0
+              32
+              read-only
+            
+          
+        
+        
+          BACKUP_BUS_PMS_CONSTRAIN_0
+          SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
+          0x14C
+          0x20
+          
+            
+              BACKUP_BUS_PMS_CONSTRAIN_LOCK
+              backup_bus_pms_constrain_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_CONSTRAIN_1
+          SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
+          0x150
+          0x20
+          0xCF0FFFFF
+          
+            
+              BACKUP_BUS_PMS_CONSTRAIN_UART
+              backup_bus_pms_constrain_uart
+              0
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1
+              backup_bus_pms_constrain_g0spi_1
+              2
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0
+              backup_bus_pms_constrain_g0spi_0
+              4
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_GPIO
+              backup_bus_pms_constrain_gpio
+              6
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_FE2
+              backup_bus_pms_constrain_fe2
+              8
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_FE
+              backup_bus_pms_constrain_fe
+              10
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_TIMER
+              backup_bus_pms_constrain_timer
+              12
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_RTC
+              backup_bus_pms_constrain_rtc
+              14
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_IO_MUX
+              backup_bus_pms_constrain_io_mux
+              16
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_WDG
+              backup_bus_pms_constrain_wdg
+              18
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_MISC
+              backup_bus_pms_constrain_misc
+              24
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_I2C
+              backup_bus_pms_constrain_i2c
+              26
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_UART1
+              backup_bus_pms_constrain_uart1
+              30
+              2
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_CONSTRAIN_2
+          SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
+          0x154
+          0x20
+          0xFCC30CF3
+          
+            
+              BACKUP_BUS_PMS_CONSTRAIN_BT
+              backup_bus_pms_constrain_bt
+              0
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0
+              backup_bus_pms_constrain_i2c_ext0
+              4
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_UHCI0
+              backup_bus_pms_constrain_uhci0
+              6
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_RMT
+              backup_bus_pms_constrain_rmt
+              10
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_LEDC
+              backup_bus_pms_constrain_ledc
+              16
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_BB
+              backup_bus_pms_constrain_bb
+              22
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP
+              backup_bus_pms_constrain_timergroup
+              26
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1
+              backup_bus_pms_constrain_timergroup1
+              28
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER
+              backup_bus_pms_constrain_systimer
+              30
+              2
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_CONSTRAIN_3
+          SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
+          0x158
+          0x20
+          0x3CC0CC33
+          
+            
+              BACKUP_BUS_PMS_CONSTRAIN_SPI_2
+              backup_bus_pms_constrain_spi_2
+              0
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL
+              backup_bus_pms_constrain_apb_ctrl
+              4
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_CAN
+              backup_bus_pms_constrain_can
+              10
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_I2S1
+              backup_bus_pms_constrain_i2s1
+              14
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_RWBT
+              backup_bus_pms_constrain_rwbt
+              22
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC
+              backup_bus_pms_constrain_wifimac
+              26
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_PWR
+              backup_bus_pms_constrain_pwr
+              28
+              2
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_CONSTRAIN_4
+          SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
+          0x15C
+          0x20
+          0x0000F3FC
+          
+            
+              BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP
+              backup_bus_pms_constrain_usb_wrap
+              2
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI
+              backup_bus_pms_constrain_crypto_peri
+              4
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA
+              backup_bus_pms_constrain_crypto_dma
+              6
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_APB_ADC
+              backup_bus_pms_constrain_apb_adc
+              8
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_BT_PWR
+              backup_bus_pms_constrain_bt_pwr
+              12
+              2
+              read-write
+            
+            
+              BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE
+              backup_bus_pms_constrain_usb_device
+              14
+              2
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_MONITOR_0
+          SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
+          0x160
+          0x20
+          
+            
+              BACKUP_BUS_PMS_MONITOR_LOCK
+              backup_bus_pms_monitor_lock
+              0
+              1
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_MONITOR_1
+          SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
+          0x164
+          0x20
+          0x00000003
+          
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR
+              backup_bus_pms_monitor_violate_clr
+              0
+              1
+              read-write
+            
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_EN
+              backup_bus_pms_monitor_violate_en
+              1
+              1
+              read-write
+            
+          
+        
+        
+          BACKUP_BUS_PMS_MONITOR_2
+          SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
+          0x168
+          0x20
+          
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR
+              backup_bus_pms_monitor_violate_intr
+              0
+              1
+              read-only
+            
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS
+              backup_bus_pms_monitor_violate_status_htrans
+              1
+              2
+              read-only
+            
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE
+              backup_bus_pms_monitor_violate_status_hsize
+              3
+              3
+              read-only
+            
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE
+              backup_bus_pms_monitor_violate_status_hwrite
+              6
+              1
+              read-only
+            
+          
+        
+        
+          BACKUP_BUS_PMS_MONITOR_3
+          SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
+          0x16C
+          0x20
+          
+            
+              BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR
+              backup_bus_pms_monitor_violate_haddr
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CLOCK_GATE
+          SENSITIVE_CLOCK_GATE_REG
+          0x170
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              clk_en
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          SENSITIVE_DATE_REG
+          0xFFC
+          0x20
+          0x02010200
+          
+            
+              DATE
+              reg_date
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SHA
+      SHA (Secure Hash Algorithm) Accelerator
+      SHA
+      0x6003B000
+      
+        0x0
+        0xB0
+        registers
+      
+      
+        SHA
+        49
+      
+      
+        
+          MODE
+          Initial configuration register.
+          0x0
+          0x20
+          
+            
+              MODE
+              Sha mode.
+              0
+              3
+              read-write
+            
+          
+        
+        
+          T_STRING
+          SHA 512/t configuration register 0.
+          0x4
+          0x20
+          
+            
+              T_STRING
+              Sha t_string (used if and only if mode == SHA_512/t).
+              0
+              32
+              read-write
+            
+          
+        
+        
+          T_LENGTH
+          SHA 512/t configuration register 1.
+          0x8
+          0x20
+          
+            
+              T_LENGTH
+              Sha t_length (used if and only if mode == SHA_512/t).
+              0
+              6
+              read-write
+            
+          
+        
+        
+          DMA_BLOCK_NUM
+          DMA configuration register 0.
+          0xC
+          0x20
+          
+            
+              DMA_BLOCK_NUM
+              Dma-sha block number.
+              0
+              6
+              read-write
+            
+          
+        
+        
+          START
+          Typical SHA configuration register 0.
+          0x10
+          0x20
+          
+            
+              START
+              Reserved.
+              1
+              31
+              read-only
+            
+          
+        
+        
+          CONTINUE
+          Typical SHA configuration register 1.
+          0x14
+          0x20
+          
+            
+              CONTINUE
+              Reserved.
+              1
+              31
+              read-only
+            
+          
+        
+        
+          BUSY
+          Busy register.
+          0x18
+          0x20
+          
+            
+              STATE
+              Sha busy state. 1'b0: idle. 1'b1: busy.
+              0
+              1
+              read-only
+            
+          
+        
+        
+          DMA_START
+          DMA configuration register 1.
+          0x1C
+          0x20
+          
+            
+              DMA_START
+              Start dma-sha.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          DMA_CONTINUE
+          DMA configuration register 2.
+          0x20
+          0x20
+          
+            
+              DMA_CONTINUE
+              Continue dma-sha.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          CLEAR_IRQ
+          Interrupt clear register.
+          0x24
+          0x20
+          
+            
+              CLEAR_INTERRUPT
+              Clear sha interrupt.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          IRQ_ENA
+          Interrupt enable register.
+          0x28
+          0x20
+          
+            
+              INTERRUPT_ENA
+              Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          Date register.
+          0x2C
+          0x20
+          0x20200616
+          
+            
+              DATE
+              Sha date information/ sha version information.
+              0
+              30
+              read-write
+            
+          
+        
+        
+          64
+          0x1
+          H_MEM[%s]
+          Sha H memory which contains intermediate hash or finial hash.
+          0x40
+          0x8
+        
+        
+          64
+          0x1
+          M_MEM[%s]
+          Sha M memory which contains message.
+          0x80
+          0x8
+        
+      
+    
+    
+      SPI0
+      SPI (Serial Peripheral Interface) Controller
+      SPI0
+      0x60003000
+      
+        0x0
+        0x48
+        registers
+      
+      
+        
+          CTRL
+          SPI0 control register.
+          0x8
+          0x20
+          0x002C2000
+          
+            
+              FDUMMY_OUT
+              In the dummy phase the signal level of spi is output by the spi controller.
+              3
+              1
+              read-write
+            
+            
+              FCMD_DUAL
+              Apply 2 signals during command phase 1:enable 0: disable
+              7
+              1
+              read-write
+            
+            
+              FCMD_QUAD
+              Apply 4 signals during command phase 1:enable 0: disable
+              8
+              1
+              read-write
+            
+            
+              FASTRD_MODE
+              This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+              13
+              1
+              read-write
+            
+            
+              FREAD_DUAL
+              In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+              14
+              1
+              read-write
+            
+            
+              Q_POL
+              The bit is used to set MISO line polarity, 1: high 0, low
+              18
+              1
+              read-write
+            
+            
+              D_POL
+              The bit is used to set MOSI line polarity, 1: high 0, low
+              19
+              1
+              read-write
+            
+            
+              FREAD_QUAD
+              In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+              20
+              1
+              read-write
+            
+            
+              WP
+              Write protect signal output when SPI is idle.  1: output high, 0: output low.
+              21
+              1
+              read-write
+            
+            
+              FREAD_DIO
+              In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
+              23
+              1
+              read-write
+            
+            
+              FREAD_QIO
+              In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
+              24
+              1
+              read-write
+            
+          
+        
+        
+          CTRL1
+          SPI0 control1 register.
+          0xC
+          0x20
+          
+            
+              CLK_MODE
+              SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
+              0
+              2
+              read-write
+            
+            
+              RXFIFO_RST
+              SPI0 RX FIFO reset signal.
+              30
+              1
+              write-only
+            
+          
+        
+        
+          CTRL2
+          SPI0 control2 register.
+          0x10
+          0x20
+          0x00000021
+          
+            
+              CS_SETUP_TIME
+              (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.
+              0
+              5
+              read-write
+            
+            
+              CS_HOLD_TIME
+              Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.
+              5
+              5
+              read-write
+            
+            
+              CS_HOLD_DELAY
+              These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.
+              25
+              6
+              read-write
+            
+            
+              SYNC_RESET
+              The FSM will be reset.
+              31
+              1
+              write-only
+            
+          
+        
+        
+          CLOCK
+          SPI clock division control register.
+          0x14
+          0x20
+          0x00030103
+          
+            
+              CLKCNT_L
+              In the master mode it must be equal to spi_mem_clkcnt_N.
+              0
+              8
+              read-write
+            
+            
+              CLKCNT_H
+              In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+              8
+              8
+              read-write
+            
+            
+              CLKCNT_N
+              In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
+              16
+              8
+              read-write
+            
+            
+              CLK_EQU_SYSCLK
+              Set this bit in 1-division mode.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          USER
+          SPI0 user register.
+          0x18
+          0x20
+          
+            
+              CS_HOLD
+              spi cs keep low when spi is in  done  phase. 1: enable 0: disable.
+              6
+              1
+              read-write
+            
+            
+              CS_SETUP
+              spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.
+              7
+              1
+              read-write
+            
+            
+              CK_OUT_EDGE
+              the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+              9
+              1
+              read-write
+            
+            
+              USR_DUMMY_IDLE
+              spi clock is disable in dummy phase when the bit is enable.
+              26
+              1
+              read-write
+            
+            
+              USR_DUMMY
+              This bit enable the dummy phase of an operation.
+              29
+              1
+              read-write
+            
+          
+        
+        
+          USER1
+          SPI0 user1 register.
+          0x1C
+          0x20
+          0x5C000007
+          
+            
+              USR_DUMMY_CYCLELEN
+              The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
+              0
+              6
+              read-write
+            
+            
+              USR_ADDR_BITLEN
+              The length in bits of address phase. The register value shall be (bit_num-1).
+              26
+              6
+              read-write
+            
+          
+        
+        
+          USER2
+          SPI0 user2 register.
+          0x20
+          0x20
+          0x70000000
+          
+            
+              USR_COMMAND_VALUE
+              The value of  command.
+              0
+              16
+              read-write
+            
+            
+              USR_COMMAND_BITLEN
+              The length in bits of command phase. The register value shall be (bit_num-1)
+              28
+              4
+              read-write
+            
+          
+        
+        
+          RD_STATUS
+          SPI0 read control register.
+          0x2C
+          0x20
+          
+            
+              WB_MODE
+              Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+              16
+              8
+              read-write
+            
+          
+        
+        
+          MISC
+          SPI0 misc register
+          0x34
+          0x20
+          
+            
+              TRANS_END
+              The bit is used to indicate the  spi0_mst_st controlled transmitting is done.
+              3
+              1
+              read-write
+            
+            
+              TRANS_END_INT_ENA
+              The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.
+              4
+              1
+              read-write
+            
+            
+              CSPI_ST_TRANS_END
+              The bit is used to indicate the  spi0_slv_st controlled transmitting is done.
+              5
+              1
+              read-write
+            
+            
+              CSPI_ST_TRANS_END_INT_ENA
+              The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.
+              6
+              1
+              read-write
+            
+            
+              CK_IDLE_EDGE
+              1: spi clk line is high when idle     0: spi clk line is low when idle
+              9
+              1
+              read-write
+            
+            
+              CS_KEEP_ACTIVE
+              spi cs line keep low when the bit is set.
+              10
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_FCTRL
+          SPI0 bit mode control register.
+          0x3C
+          0x20
+          
+            
+              CACHE_REQ_EN
+              For SPI0, Cache access enable, 1: enable, 0:disable.
+              0
+              1
+              read-write
+            
+            
+              CACHE_USR_ADDR_4BYTE
+              For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
+              1
+              1
+              read-write
+            
+            
+              CACHE_FLASH_USR_CMD
+              For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.
+              2
+              1
+              read-write
+            
+            
+              FDIN_DUAL
+              For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+              3
+              1
+              read-write
+            
+            
+              FDOUT_DUAL
+              For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+              4
+              1
+              read-write
+            
+            
+              FADDR_DUAL
+              For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.
+              5
+              1
+              read-write
+            
+            
+              FDIN_QUAD
+              For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              6
+              1
+              read-write
+            
+            
+              FDOUT_QUAD
+              For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              7
+              1
+              read-write
+            
+            
+              FADDR_QUAD
+              For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              8
+              1
+              read-write
+            
+          
+        
+        
+          FSM
+          SPI0 FSM status register
+          0x54
+          0x20
+          0x00000200
+          
+            
+              CSPI_ST
+              The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
+              0
+              4
+              read-only
+            
+            
+              EM_ST
+              The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
+              4
+              3
+              read-only
+            
+            
+              CSPI_LOCK_DELAY_TIME
+              The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
+              7
+              5
+              read-write
+            
+          
+        
+        
+          TIMING_CALI
+          SPI0 timing calibration register
+          0xA8
+          0x20
+          0x00000001
+          
+            
+              TIMING_CLK_ENA
+              The bit is used to enable timing adjust clock for all reading operations.
+              0
+              1
+              read-write
+            
+            
+              TIMING_CALI
+              The bit is used to enable timing auto-calibration for all reading operations.
+              1
+              1
+              read-write
+            
+            
+              EXTRA_DUMMY_CYCLELEN
+              add extra dummy spi clock cycle length for spi clock calibration.
+              2
+              3
+              read-write
+            
+          
+        
+        
+          DIN_MODE
+          SPI0 input delay mode control register
+          0xAC
+          0x20
+          
+            
+              DIN0_MODE
+              the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge
+              0
+              2
+              read-write
+            
+            
+              DIN1_MODE
+              the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge
+              2
+              2
+              read-write
+            
+            
+              DIN2_MODE
+              the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge
+              4
+              2
+              read-write
+            
+            
+              DIN3_MODE
+              the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge
+              6
+              2
+              read-write
+            
+          
+        
+        
+          DIN_NUM
+          SPI0 input delay number control register
+          0xB0
+          0x20
+          
+            
+              DIN0_NUM
+              the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+              0
+              2
+              read-write
+            
+            
+              DIN1_NUM
+              the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+              2
+              2
+              read-write
+            
+            
+              DIN2_NUM
+              the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+              4
+              2
+              read-write
+            
+            
+              DIN3_NUM
+              the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+              6
+              2
+              read-write
+            
+          
+        
+        
+          DOUT_MODE
+          SPI0 output delay mode control register
+          0xB4
+          0x20
+          
+            
+              DOUT0_MODE
+              the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+              0
+              1
+              read-write
+            
+            
+              DOUT1_MODE
+              the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+              1
+              1
+              read-write
+            
+            
+              DOUT2_MODE
+              the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+              2
+              1
+              read-write
+            
+            
+              DOUT3_MODE
+              the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+              3
+              1
+              read-write
+            
+          
+        
+        
+          CLOCK_GATE
+          SPI0 clk_gate register
+          0xDC
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              Register clock gate enable signal. 1: Enable. 0: Disable.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CORE_CLK_SEL
+          SPI0 module clock select register
+          0xE0
+          0x20
+          
+            
+              SPI01_CLK_SEL
+              When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.
+              0
+              2
+              read-write
+            
+          
+        
+        
+          DATE
+          Version control register
+          0x3FC
+          0x20
+          0x02007130
+          
+            
+              DATE
+              SPI register version.
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SPI1
+      SPI (Serial Peripheral Interface) Controller
+      SPI1
+      0x60002000
+      
+        0x0
+        0xA8
+        registers
+      
+      
+        
+          CMD
+          SPI1 memory command register
+          0x0
+          0x20
+          
+            
+              SPI1_MST_ST
+              The current status of SPI1 master FSM.
+              0
+              4
+              read-only
+            
+            
+              MSPI_ST
+              The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
+              4
+              4
+              read-only
+            
+            
+              FLASH_PE
+              In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.
+              17
+              1
+              read-write
+            
+            
+              USR
+              User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              18
+              1
+              read-write
+            
+            
+              FLASH_HPM
+              Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.
+              19
+              1
+              read-write
+            
+            
+              FLASH_RES
+              This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.
+              20
+              1
+              read-write
+            
+            
+              FLASH_DP
+              Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              21
+              1
+              read-write
+            
+            
+              FLASH_CE
+              Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              22
+              1
+              read-write
+            
+            
+              FLASH_BE
+              Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              23
+              1
+              read-write
+            
+            
+              FLASH_SE
+              Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              24
+              1
+              read-write
+            
+            
+              FLASH_PP
+              Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.
+              25
+              1
+              read-write
+            
+            
+              FLASH_WRSR
+              Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              26
+              1
+              read-write
+            
+            
+              FLASH_RDSR
+              Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              27
+              1
+              read-write
+            
+            
+              FLASH_RDID
+              Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+              28
+              1
+              read-write
+            
+            
+              FLASH_WRDI
+              Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+              29
+              1
+              read-write
+            
+            
+              FLASH_WREN
+              Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+              30
+              1
+              read-write
+            
+            
+              FLASH_READ
+              Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          ADDR
+          SPI1 address register
+          0x4
+          0x20
+          
+            
+              USR_ADDR_VALUE
+              In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CTRL
+          SPI1 control register.
+          0x8
+          0x20
+          0x002CA000
+          
+            
+              FDUMMY_OUT
+              In the dummy phase the signal level of spi is output by the spi controller.
+              3
+              1
+              read-write
+            
+            
+              FCMD_DUAL
+              Apply 2 signals during command phase 1:enable 0: disable
+              7
+              1
+              read-write
+            
+            
+              FCMD_QUAD
+              Apply 4 signals during command phase 1:enable 0: disable
+              8
+              1
+              read-write
+            
+            
+              FCS_CRC_EN
+              For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.
+              10
+              1
+              read-write
+            
+            
+              TX_CRC_EN
+              For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+              11
+              1
+              read-write
+            
+            
+              FASTRD_MODE
+              This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+              13
+              1
+              read-write
+            
+            
+              FREAD_DUAL
+              In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+              14
+              1
+              read-write
+            
+            
+              RESANDRES
+              The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
+              15
+              1
+              read-write
+            
+            
+              Q_POL
+              The bit is used to set MISO line polarity, 1: high 0, low
+              18
+              1
+              read-write
+            
+            
+              D_POL
+              The bit is used to set MOSI line polarity, 1: high 0, low
+              19
+              1
+              read-write
+            
+            
+              FREAD_QUAD
+              In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+              20
+              1
+              read-write
+            
+            
+              WP
+              Write protect signal output when SPI is idle.  1: output high, 0: output low.
+              21
+              1
+              read-write
+            
+            
+              WRSR_2B
+              two bytes data will be written to status register when it is set. 1: enable 0: disable.
+              22
+              1
+              read-write
+            
+            
+              FREAD_DIO
+              In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
+              23
+              1
+              read-write
+            
+            
+              FREAD_QIO
+              In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
+              24
+              1
+              read-write
+            
+          
+        
+        
+          CTRL1
+          SPI1 control1 register.
+          0xC
+          0x20
+          0x00000FFC
+          
+            
+              CLK_MODE
+              SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
+              0
+              2
+              read-write
+            
+            
+              CS_HOLD_DLY_RES
+              After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.
+              2
+              10
+              read-write
+            
+          
+        
+        
+          CTRL2
+          SPI1 control2 register.
+          0x10
+          0x20
+          
+            
+              SYNC_RESET
+              The FSM will be reset.
+              31
+              1
+              write-only
+            
+          
+        
+        
+          CLOCK
+          SPI1 clock division control register.
+          0x14
+          0x20
+          0x00030103
+          
+            
+              CLKCNT_L
+              In the master mode it must be equal to spi_mem_clkcnt_N.
+              0
+              8
+              read-write
+            
+            
+              CLKCNT_H
+              In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+              8
+              8
+              read-write
+            
+            
+              CLKCNT_N
+              In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
+              16
+              8
+              read-write
+            
+            
+              CLK_EQU_SYSCLK
+              reserved
+              31
+              1
+              read-write
+            
+          
+        
+        
+          USER
+          SPI1 user register.
+          0x18
+          0x20
+          0x80000000
+          
+            
+              CK_OUT_EDGE
+              the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+              9
+              1
+              read-write
+            
+            
+              FWRITE_DUAL
+              In the write operations read-data phase apply 2 signals
+              12
+              1
+              read-write
+            
+            
+              FWRITE_QUAD
+              In the write operations read-data phase apply 4 signals
+              13
+              1
+              read-write
+            
+            
+              FWRITE_DIO
+              In the write operations address phase and read-data phase apply 2 signals.
+              14
+              1
+              read-write
+            
+            
+              FWRITE_QIO
+              In the write operations address phase and read-data phase apply 4 signals.
+              15
+              1
+              read-write
+            
+            
+              USR_MISO_HIGHPART
+              read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
+              24
+              1
+              read-write
+            
+            
+              USR_MOSI_HIGHPART
+              write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
+              25
+              1
+              read-write
+            
+            
+              USR_DUMMY_IDLE
+              SPI clock is disable in dummy phase when the bit is enable.
+              26
+              1
+              read-write
+            
+            
+              USR_MOSI
+              This bit enable the write-data phase of an operation.
+              27
+              1
+              read-write
+            
+            
+              USR_MISO
+              This bit enable the read-data phase of an operation.
+              28
+              1
+              read-write
+            
+            
+              USR_DUMMY
+              This bit enable the dummy phase of an operation.
+              29
+              1
+              read-write
+            
+            
+              USR_ADDR
+              This bit enable the address phase of an operation.
+              30
+              1
+              read-write
+            
+            
+              USR_COMMAND
+              This bit enable the command phase of an operation.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          USER1
+          SPI1 user1 register.
+          0x1C
+          0x20
+          0x5C000007
+          
+            
+              USR_DUMMY_CYCLELEN
+              The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
+              0
+              6
+              read-write
+            
+            
+              USR_ADDR_BITLEN
+              The length in bits of address phase. The register value shall be (bit_num-1).
+              26
+              6
+              read-write
+            
+          
+        
+        
+          USER2
+          SPI1 user2 register.
+          0x20
+          0x20
+          0x70000000
+          
+            
+              USR_COMMAND_VALUE
+              The value of  command.
+              0
+              16
+              read-write
+            
+            
+              USR_COMMAND_BITLEN
+              The length in bits of command phase. The register value shall be (bit_num-1)
+              28
+              4
+              read-write
+            
+          
+        
+        
+          MOSI_DLEN
+          SPI1 send data bit length control register.
+          0x24
+          0x20
+          
+            
+              USR_MOSI_DBITLEN
+              The length in bits of write-data. The register value shall be (bit_num-1).
+              0
+              10
+              read-write
+            
+          
+        
+        
+          MISO_DLEN
+          SPI1 receive data bit length control register.
+          0x28
+          0x20
+          
+            
+              USR_MISO_DBITLEN
+              The length in bits of  read-data. The register value shall be (bit_num-1).
+              0
+              10
+              read-write
+            
+          
+        
+        
+          RD_STATUS
+          SPI1 status register.
+          0x2C
+          0x20
+          
+            
+              STATUS
+              The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+              0
+              16
+              read-write
+            
+            
+              WB_MODE
+              Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.
+              16
+              8
+              read-write
+            
+          
+        
+        
+          MISC
+          SPI1 misc register
+          0x34
+          0x20
+          0x00000002
+          
+            
+              CS0_DIS
+              SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.
+              0
+              1
+              read-write
+            
+            
+              CS1_DIS
+              SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.
+              1
+              1
+              read-write
+            
+            
+              CK_IDLE_EDGE
+              1: spi clk line is high when idle     0: spi clk line is low when idle
+              9
+              1
+              read-write
+            
+            
+              CS_KEEP_ACTIVE
+              spi cs line keep low when the bit is set.
+              10
+              1
+              read-write
+            
+          
+        
+        
+          TX_CRC
+          SPI1 TX CRC data register.
+          0x38
+          0x20
+          0xFFFFFFFF
+          
+            
+              DATA
+              For SPI1, the value of crc32.
+              0
+              32
+              read-only
+            
+          
+        
+        
+          CACHE_FCTRL
+          SPI1 bit mode control register.
+          0x3C
+          0x20
+          
+            
+              CACHE_USR_ADDR_4BYTE
+              For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.
+              1
+              1
+              read-write
+            
+            
+              FDIN_DUAL
+              For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+              3
+              1
+              read-write
+            
+            
+              FDOUT_DUAL
+              For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+              4
+              1
+              read-write
+            
+            
+              FADDR_DUAL
+              For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.
+              5
+              1
+              read-write
+            
+            
+              FDIN_QUAD
+              For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              6
+              1
+              read-write
+            
+            
+              FDOUT_QUAD
+              For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              7
+              1
+              read-write
+            
+            
+              FADDR_QUAD
+              For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.
+              8
+              1
+              read-write
+            
+          
+        
+        
+          W0
+          SPI1 memory data buffer0
+          0x58
+          0x20
+          
+            
+              BUF0
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W1
+          SPI1 memory data buffer1
+          0x5C
+          0x20
+          
+            
+              BUF1
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W2
+          SPI1 memory data buffer2
+          0x60
+          0x20
+          
+            
+              BUF2
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W3
+          SPI1 memory data buffer3
+          0x64
+          0x20
+          
+            
+              BUF3
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W4
+          SPI1 memory data buffer4
+          0x68
+          0x20
+          
+            
+              BUF4
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W5
+          SPI1 memory data buffer5
+          0x6C
+          0x20
+          
+            
+              BUF5
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W6
+          SPI1 memory data buffer6
+          0x70
+          0x20
+          
+            
+              BUF6
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W7
+          SPI1 memory data buffer7
+          0x74
+          0x20
+          
+            
+              BUF7
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W8
+          SPI1 memory data buffer8
+          0x78
+          0x20
+          
+            
+              BUF8
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W9
+          SPI1 memory data buffer9
+          0x7C
+          0x20
+          
+            
+              BUF9
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W10
+          SPI1 memory data buffer10
+          0x80
+          0x20
+          
+            
+              BUF10
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W11
+          SPI1 memory data buffer11
+          0x84
+          0x20
+          
+            
+              BUF11
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W12
+          SPI1 memory data buffer12
+          0x88
+          0x20
+          
+            
+              BUF12
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W13
+          SPI1 memory data buffer13
+          0x8C
+          0x20
+          
+            
+              BUF13
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W14
+          SPI1 memory data buffer14
+          0x90
+          0x20
+          
+            
+              BUF14
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W15
+          SPI1 memory data buffer15
+          0x94
+          0x20
+          
+            
+              BUF15
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          FLASH_WAITI_CTRL
+          SPI1 wait idle control register
+          0x98
+          0x20
+          0x00000014
+          
+            
+              WAITI_DUMMY
+              The dummy phase enable when wait flash idle (RDSR)
+              1
+              1
+              read-write
+            
+            
+              WAITI_CMD
+              The command to wait flash idle(RDSR).
+              2
+              8
+              read-write
+            
+            
+              WAITI_DUMMY_CYCLELEN
+              The dummy cycle length when wait flash idle(RDSR).
+              10
+              6
+              read-write
+            
+          
+        
+        
+          FLASH_SUS_CTRL
+          SPI1 flash suspend control register
+          0x9C
+          0x20
+          0x08002000
+          
+            
+              FLASH_PER
+              program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              0
+              1
+              read-write
+            
+            
+              FLASH_PES
+              program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+              1
+              1
+              read-write
+            
+            
+              FLASH_PER_WAIT_EN
+              1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.
+              2
+              1
+              read-write
+            
+            
+              FLASH_PES_WAIT_EN
+              1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.
+              3
+              1
+              read-write
+            
+            
+              PES_PER_EN
+              Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.
+              4
+              1
+              read-write
+            
+            
+              FLASH_PES_EN
+              Set this bit to enable Auto-suspending function.
+              5
+              1
+              read-write
+            
+            
+              PESR_END_MSK
+              The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+              6
+              16
+              read-write
+            
+            
+              RD_SUS_2B
+              1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit
+              22
+              1
+              read-write
+            
+            
+              PER_END_EN
+              1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.
+              23
+              1
+              read-write
+            
+            
+              PES_END_EN
+              1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.
+              24
+              1
+              read-write
+            
+            
+              SUS_TIMEOUT_CNT
+              When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.
+              25
+              7
+              read-write
+            
+          
+        
+        
+          FLASH_SUS_CMD
+          SPI1 flash suspend command register
+          0xA0
+          0x20
+          0x0005757A
+          
+            
+              FLASH_PER_COMMAND
+              Program/Erase resume command.
+              0
+              8
+              read-write
+            
+            
+              FLASH_PES_COMMAND
+              Program/Erase suspend command.
+              8
+              8
+              read-write
+            
+            
+              WAIT_PESR_COMMAND
+              Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          SUS_STATUS
+          SPI1 flash suspend status register
+          0xA4
+          0x20
+          
+            
+              FLASH_SUS
+              The status of flash suspend, only used in SPI1.
+              0
+              1
+              read-write
+            
+            
+              WAIT_PESR_CMD_2B
+              1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+              1
+              1
+              read-write
+            
+            
+              FLASH_HPM_DLY_128
+              1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.
+              2
+              1
+              read-write
+            
+            
+              FLASH_RES_DLY_128
+              1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.
+              3
+              1
+              read-write
+            
+            
+              FLASH_DP_DLY_128
+              1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.
+              4
+              1
+              read-write
+            
+            
+              FLASH_PER_DLY_128
+              Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.
+              5
+              1
+              read-write
+            
+            
+              FLASH_PES_DLY_128
+              Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.
+              6
+              1
+              read-write
+            
+            
+              SPI0_LOCK_EN
+              1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
+              7
+              1
+              read-write
+            
+          
+        
+        
+          TIMING_CALI
+          SPI1 timing control register
+          0xA8
+          0x20
+          
+            
+              TIMING_CALI
+              The bit is used to enable timing auto-calibration for all reading operations.
+              1
+              1
+              read-write
+            
+            
+              EXTRA_DUMMY_CYCLELEN
+              add extra dummy spi clock cycle length for spi clock calibration.
+              2
+              3
+              read-write
+            
+          
+        
+        
+          INT_ENA
+          SPI1 interrupt enable register
+          0xC0
+          0x20
+          
+            
+              PER_END_INT_ENA
+              The enable bit for SPI_MEM_PER_END_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              PES_END_INT_ENA
+              The enable bit for SPI_MEM_PES_END_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              WPE_END_INT_ENA
+              The enable bit for SPI_MEM_WPE_END_INT interrupt.
+              2
+              1
+              read-write
+            
+            
+              SLV_ST_END_INT_ENA
+              The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+              3
+              1
+              read-write
+            
+            
+              MST_ST_END_INT_ENA
+              The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+              4
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          SPI1 interrupt clear register
+          0xC4
+          0x20
+          
+            
+              PER_END_INT_CLR
+              The clear bit for SPI_MEM_PER_END_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              PES_END_INT_CLR
+              The clear bit for SPI_MEM_PES_END_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              WPE_END_INT_CLR
+              The clear bit for SPI_MEM_WPE_END_INT interrupt.
+              2
+              1
+              write-only
+            
+            
+              SLV_ST_END_INT_CLR
+              The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+              3
+              1
+              write-only
+            
+            
+              MST_ST_END_INT_CLR
+              The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+              4
+              1
+              write-only
+            
+          
+        
+        
+          INT_RAW
+          SPI1 interrupt raw register
+          0xC8
+          0x20
+          
+            
+              PER_END_INT_RAW
+              The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.
+              0
+              1
+              read-only
+            
+            
+              PES_END_INT_RAW
+              The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.
+              1
+              1
+              read-only
+            
+            
+              WPE_END_INT_RAW
+              The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
+              2
+              1
+              read-only
+            
+            
+              SLV_ST_END_INT_RAW
+              The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others
+              3
+              1
+              read-only
+            
+            
+              MST_ST_END_INT_RAW
+              The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.
+              4
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          SPI1 interrupt status register
+          0xCC
+          0x20
+          
+            
+              PER_END_INT_ST
+              The status bit for SPI_MEM_PER_END_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              PES_END_INT_ST
+              The status bit for SPI_MEM_PES_END_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              WPE_END_INT_ST
+              The status bit for SPI_MEM_WPE_END_INT interrupt.
+              2
+              1
+              read-only
+            
+            
+              SLV_ST_END_INT_ST
+              The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+              3
+              1
+              read-only
+            
+            
+              MST_ST_END_INT_ST
+              The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+              4
+              1
+              read-only
+            
+          
+        
+        
+          CLOCK_GATE
+          SPI1 clk_gate register
+          0xDC
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              Register clock gate enable signal. 1: Enable. 0: Disable.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          Version control register
+          0x3FC
+          0x20
+          0x02007170
+          
+            
+              DATE
+              Version control register
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SPI2
+      SPI (Serial Peripheral Interface) Controller
+      SPI2
+      0x60024000
+      
+        0x0
+        0x94
+        registers
+      
+      
+        SPI2
+        19
+      
+      
+        
+          CMD
+          Command control register
+          0x0
+          0x20
+          
+            
+              CONF_BITLEN
+              Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.
+              0
+              18
+              read-write
+            
+            
+              UPDATE
+              Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.
+              23
+              1
+              read-write
+            
+            
+              USR
+              User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.
+              24
+              1
+              read-write
+            
+          
+        
+        
+          ADDR
+          Address value register
+          0x4
+          0x20
+          
+            
+              USR_ADDR_VALUE
+              Address to slave. Can be configured in CONF state.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          CTRL
+          SPI control register
+          0x8
+          0x20
+          0x003C0000
+          
+            
+              DUMMY_OUT
+              In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.
+              3
+              1
+              read-write
+            
+            
+              FADDR_DUAL
+              Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
+              5
+              1
+              read-write
+            
+            
+              FADDR_QUAD
+              Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
+              6
+              1
+              read-write
+            
+            
+              FCMD_DUAL
+              Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
+              8
+              1
+              read-write
+            
+            
+              FCMD_QUAD
+              Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
+              9
+              1
+              read-write
+            
+            
+              FREAD_DUAL
+              In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.
+              14
+              1
+              read-write
+            
+            
+              FREAD_QUAD
+              In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.
+              15
+              1
+              read-write
+            
+            
+              Q_POL
+              The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.
+              18
+              1
+              read-write
+            
+            
+              D_POL
+              The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.
+              19
+              1
+              read-write
+            
+            
+              HOLD_POL
+              SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
+              20
+              1
+              read-write
+            
+            
+              WP_POL
+              Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.
+              21
+              1
+              read-write
+            
+            
+              RD_BIT_ORDER
+              In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.
+              25
+              1
+              read-write
+            
+            
+              WR_BIT_ORDER
+              In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.
+              26
+              1
+              read-write
+            
+          
+        
+        
+          CLOCK
+          SPI clock control register
+          0xC
+          0x20
+          0x80003043
+          
+            
+              CLKCNT_L
+              In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.
+              0
+              6
+              read-write
+            
+            
+              CLKCNT_H
+              In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.
+              6
+              6
+              read-write
+            
+            
+              CLKCNT_N
+              In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+              12
+              6
+              read-write
+            
+            
+              CLKDIV_PRE
+              In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.
+              18
+              4
+              read-write
+            
+            
+              CLK_EQU_SYSCLK
+              In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          USER
+          SPI USER control register
+          0x10
+          0x20
+          0x800000C0
+          
+            
+              DOUTDIN
+              Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.
+              0
+              1
+              read-write
+            
+            
+              QPI_MODE
+              Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.
+              3
+              1
+              read-write
+            
+            
+              TSCK_I_EDGE
+              In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.
+              5
+              1
+              read-write
+            
+            
+              CS_HOLD
+              spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.
+              6
+              1
+              read-write
+            
+            
+              CS_SETUP
+              spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.
+              7
+              1
+              read-write
+            
+            
+              RSCK_I_EDGE
+              In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.
+              8
+              1
+              read-write
+            
+            
+              CK_OUT_EDGE
+              the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.
+              9
+              1
+              read-write
+            
+            
+              FWRITE_DUAL
+              In the write operations read-data phase apply 2 signals. Can be configured in CONF state.
+              12
+              1
+              read-write
+            
+            
+              FWRITE_QUAD
+              In the write operations read-data phase apply 4 signals. Can be configured in CONF state.
+              13
+              1
+              read-write
+            
+            
+              USR_CONF_NXT
+              1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.
+              15
+              1
+              read-write
+            
+            
+              SIO
+              Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.
+              17
+              1
+              read-write
+            
+            
+              USR_MISO_HIGHPART
+              read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
+              24
+              1
+              read-write
+            
+            
+              USR_MOSI_HIGHPART
+              write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.
+              25
+              1
+              read-write
+            
+            
+              USR_DUMMY_IDLE
+              spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.
+              26
+              1
+              read-write
+            
+            
+              USR_MOSI
+              This bit enable the write-data phase of an operation. Can be configured in CONF state.
+              27
+              1
+              read-write
+            
+            
+              USR_MISO
+              This bit enable the read-data phase of an operation. Can be configured in CONF state.
+              28
+              1
+              read-write
+            
+            
+              USR_DUMMY
+              This bit enable the dummy phase of an operation. Can be configured in CONF state.
+              29
+              1
+              read-write
+            
+            
+              USR_ADDR
+              This bit enable the address phase of an operation. Can be configured in CONF state.
+              30
+              1
+              read-write
+            
+            
+              USR_COMMAND
+              This bit enable the command phase of an operation. Can be configured in CONF state.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          USER1
+          SPI USER control register 1
+          0x14
+          0x20
+          0xB8410007
+          
+            
+              USR_DUMMY_CYCLELEN
+              The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.
+              0
+              8
+              read-write
+            
+            
+              MST_WFULL_ERR_END_EN
+              1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.
+              16
+              1
+              read-write
+            
+            
+              CS_SETUP_TIME
+              (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.
+              17
+              5
+              read-write
+            
+            
+              CS_HOLD_TIME
+              delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.
+              22
+              5
+              read-write
+            
+            
+              USR_ADDR_BITLEN
+              The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.
+              27
+              5
+              read-write
+            
+          
+        
+        
+          USER2
+          SPI USER control register 2
+          0x18
+          0x20
+          0x78000000
+          
+            
+              USR_COMMAND_VALUE
+              The value of  command. Can be configured in CONF state.
+              0
+              16
+              read-write
+            
+            
+              MST_REMPTY_ERR_END_EN
+              1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.
+              27
+              1
+              read-write
+            
+            
+              USR_COMMAND_BITLEN
+              The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.
+              28
+              4
+              read-write
+            
+          
+        
+        
+          MS_DLEN
+          SPI data bit length control register
+          0x1C
+          0x20
+          
+            
+              MS_DATA_BITLEN
+              The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.
+              0
+              18
+              read-write
+            
+          
+        
+        
+          MISC
+          SPI misc register
+          0x20
+          0x20
+          0x0000003E
+          
+            
+              CS0_DIS
+              SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.
+              0
+              1
+              read-write
+            
+            
+              CS1_DIS
+              SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.
+              1
+              1
+              read-write
+            
+            
+              CS2_DIS
+              SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.
+              2
+              1
+              read-write
+            
+            
+              CS3_DIS
+              SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.
+              3
+              1
+              read-write
+            
+            
+              CS4_DIS
+              SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.
+              4
+              1
+              read-write
+            
+            
+              CS5_DIS
+              SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.
+              5
+              1
+              read-write
+            
+            
+              CK_DIS
+              1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.
+              6
+              1
+              read-write
+            
+            
+              MASTER_CS_POL
+              In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+              7
+              6
+              read-write
+            
+            
+              SLAVE_CS_POL
+              spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.
+              23
+              1
+              read-write
+            
+            
+              CK_IDLE_EDGE
+              1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.
+              29
+              1
+              read-write
+            
+            
+              CS_KEEP_ACTIVE
+              spi cs line keep low when the bit is set. Can be configured in CONF state.
+              30
+              1
+              read-write
+            
+            
+              QUAD_DIN_PIN_SWAP
+              1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          DIN_MODE
+          SPI input delay mode configuration
+          0x24
+          0x20
+          
+            
+              DIN0_MODE
+              the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+              0
+              2
+              read-write
+            
+            
+              DIN1_MODE
+              the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+              2
+              2
+              read-write
+            
+            
+              DIN2_MODE
+              the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+              4
+              2
+              read-write
+            
+            
+              DIN3_MODE
+              the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+              6
+              2
+              read-write
+            
+            
+              TIMING_HCLK_ACTIVE
+              1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.
+              16
+              1
+              read-write
+            
+          
+        
+        
+          DIN_NUM
+          SPI input delay number configuration
+          0x28
+          0x20
+          
+            
+              DIN0_NUM
+              the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.
+              0
+              2
+              read-write
+            
+            
+              DIN1_NUM
+              the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.
+              2
+              2
+              read-write
+            
+            
+              DIN2_NUM
+              the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.
+              4
+              2
+              read-write
+            
+            
+              DIN3_NUM
+              the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.
+              6
+              2
+              read-write
+            
+          
+        
+        
+          DOUT_MODE
+          SPI output delay mode configuration
+          0x2C
+          0x20
+          
+            
+              DOUT0_MODE
+              The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+              0
+              1
+              read-write
+            
+            
+              DOUT1_MODE
+              The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+              1
+              1
+              read-write
+            
+            
+              DOUT2_MODE
+              The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+              2
+              1
+              read-write
+            
+            
+              DOUT3_MODE
+              The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+              3
+              1
+              read-write
+            
+          
+        
+        
+          DMA_CONF
+          SPI DMA control register
+          0x30
+          0x20
+          
+            
+              DMA_SLV_SEG_TRANS_EN
+              Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+              18
+              1
+              read-write
+            
+            
+              SLV_RX_SEG_TRANS_CLR_EN
+              1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.
+              19
+              1
+              read-write
+            
+            
+              SLV_TX_SEG_TRANS_CLR_EN
+              1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+              20
+              1
+              read-write
+            
+            
+              RX_EOF_EN
+              1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.
+              21
+              1
+              read-write
+            
+            
+              DMA_RX_ENA
+              Set this bit to enable SPI DMA controlled receive data mode.
+              27
+              1
+              read-write
+            
+            
+              DMA_TX_ENA
+              Set this bit to enable SPI DMA controlled send data mode.
+              28
+              1
+              read-write
+            
+            
+              RX_AFIFO_RST
+              Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.
+              29
+              1
+              write-only
+            
+            
+              BUF_AFIFO_RST
+              Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.
+              30
+              1
+              write-only
+            
+            
+              DMA_AFIFO_RST
+              Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.
+              31
+              1
+              write-only
+            
+          
+        
+        
+          DMA_INT_ENA
+          SPI DMA interrupt enable register
+          0x34
+          0x20
+          
+            
+              DMA_INFIFO_FULL_ERR_INT_ENA
+              The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              DMA_OUTFIFO_EMPTY_ERR_INT_ENA
+              The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              SLV_EX_QPI_INT_ENA
+              The enable bit for SPI slave Ex_QPI interrupt.
+              2
+              1
+              read-write
+            
+            
+              SLV_EN_QPI_INT_ENA
+              The enable bit for SPI slave En_QPI interrupt.
+              3
+              1
+              read-write
+            
+            
+              SLV_CMD7_INT_ENA
+              The enable bit for SPI slave CMD7 interrupt.
+              4
+              1
+              read-write
+            
+            
+              SLV_CMD8_INT_ENA
+              The enable bit for SPI slave CMD8 interrupt.
+              5
+              1
+              read-write
+            
+            
+              SLV_CMD9_INT_ENA
+              The enable bit for SPI slave CMD9 interrupt.
+              6
+              1
+              read-write
+            
+            
+              SLV_CMDA_INT_ENA
+              The enable bit for SPI slave CMDA interrupt.
+              7
+              1
+              read-write
+            
+            
+              SLV_RD_DMA_DONE_INT_ENA
+              The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+              8
+              1
+              read-write
+            
+            
+              SLV_WR_DMA_DONE_INT_ENA
+              The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+              9
+              1
+              read-write
+            
+            
+              SLV_RD_BUF_DONE_INT_ENA
+              The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+              10
+              1
+              read-write
+            
+            
+              SLV_WR_BUF_DONE_INT_ENA
+              The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+              11
+              1
+              read-write
+            
+            
+              TRANS_DONE_INT_ENA
+              The enable bit for SPI_TRANS_DONE_INT interrupt.
+              12
+              1
+              read-write
+            
+            
+              DMA_SEG_TRANS_DONE_INT_ENA
+              The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+              13
+              1
+              read-write
+            
+            
+              SEG_MAGIC_ERR_INT_ENA
+              The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+              14
+              1
+              read-write
+            
+            
+              SLV_BUF_ADDR_ERR_INT_ENA
+              The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+              15
+              1
+              read-write
+            
+            
+              SLV_CMD_ERR_INT_ENA
+              The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+              16
+              1
+              read-write
+            
+            
+              MST_RX_AFIFO_WFULL_ERR_INT_ENA
+              The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+              17
+              1
+              read-write
+            
+            
+              MST_TX_AFIFO_REMPTY_ERR_INT_ENA
+              The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+              18
+              1
+              read-write
+            
+            
+              APP2_INT_ENA
+              The enable bit for SPI_APP2_INT interrupt.
+              19
+              1
+              read-write
+            
+            
+              APP1_INT_ENA
+              The enable bit for SPI_APP1_INT interrupt.
+              20
+              1
+              read-write
+            
+          
+        
+        
+          DMA_INT_CLR
+          SPI DMA interrupt clear register
+          0x38
+          0x20
+          
+            
+              DMA_INFIFO_FULL_ERR_INT_CLR
+              The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              DMA_OUTFIFO_EMPTY_ERR_INT_CLR
+              The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              SLV_EX_QPI_INT_CLR
+              The clear bit for SPI slave Ex_QPI interrupt.
+              2
+              1
+              write-only
+            
+            
+              SLV_EN_QPI_INT_CLR
+              The clear bit for SPI slave En_QPI interrupt.
+              3
+              1
+              write-only
+            
+            
+              SLV_CMD7_INT_CLR
+              The clear bit for SPI slave CMD7 interrupt.
+              4
+              1
+              write-only
+            
+            
+              SLV_CMD8_INT_CLR
+              The clear bit for SPI slave CMD8 interrupt.
+              5
+              1
+              write-only
+            
+            
+              SLV_CMD9_INT_CLR
+              The clear bit for SPI slave CMD9 interrupt.
+              6
+              1
+              write-only
+            
+            
+              SLV_CMDA_INT_CLR
+              The clear bit for SPI slave CMDA interrupt.
+              7
+              1
+              write-only
+            
+            
+              SLV_RD_DMA_DONE_INT_CLR
+              The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+              8
+              1
+              write-only
+            
+            
+              SLV_WR_DMA_DONE_INT_CLR
+              The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+              9
+              1
+              write-only
+            
+            
+              SLV_RD_BUF_DONE_INT_CLR
+              The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+              10
+              1
+              write-only
+            
+            
+              SLV_WR_BUF_DONE_INT_CLR
+              The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+              11
+              1
+              write-only
+            
+            
+              TRANS_DONE_INT_CLR
+              The clear bit for SPI_TRANS_DONE_INT interrupt.
+              12
+              1
+              write-only
+            
+            
+              DMA_SEG_TRANS_DONE_INT_CLR
+              The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+              13
+              1
+              write-only
+            
+            
+              SEG_MAGIC_ERR_INT_CLR
+              The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+              14
+              1
+              write-only
+            
+            
+              SLV_BUF_ADDR_ERR_INT_CLR
+              The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+              15
+              1
+              write-only
+            
+            
+              SLV_CMD_ERR_INT_CLR
+              The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+              16
+              1
+              write-only
+            
+            
+              MST_RX_AFIFO_WFULL_ERR_INT_CLR
+              The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+              17
+              1
+              write-only
+            
+            
+              MST_TX_AFIFO_REMPTY_ERR_INT_CLR
+              The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+              18
+              1
+              write-only
+            
+            
+              APP2_INT_CLR
+              The clear bit for SPI_APP2_INT interrupt.
+              19
+              1
+              write-only
+            
+            
+              APP1_INT_CLR
+              The clear bit for SPI_APP1_INT interrupt.
+              20
+              1
+              write-only
+            
+          
+        
+        
+          DMA_INT_RAW
+          SPI DMA interrupt raw register
+          0x3C
+          0x20
+          
+            
+              DMA_INFIFO_FULL_ERR_INT_RAW
+              1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.
+              0
+              1
+              read-write
+            
+            
+              DMA_OUTFIFO_EMPTY_ERR_INT_RAW
+              1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.
+              1
+              1
+              read-write
+            
+            
+              SLV_EX_QPI_INT_RAW
+              The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.
+              2
+              1
+              read-write
+            
+            
+              SLV_EN_QPI_INT_RAW
+              The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.
+              3
+              1
+              read-write
+            
+            
+              SLV_CMD7_INT_RAW
+              The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.
+              4
+              1
+              read-write
+            
+            
+              SLV_CMD8_INT_RAW
+              The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.
+              5
+              1
+              read-write
+            
+            
+              SLV_CMD9_INT_RAW
+              The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.
+              6
+              1
+              read-write
+            
+            
+              SLV_CMDA_INT_RAW
+              The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.
+              7
+              1
+              read-write
+            
+            
+              SLV_RD_DMA_DONE_INT_RAW
+              The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.
+              8
+              1
+              read-write
+            
+            
+              SLV_WR_DMA_DONE_INT_RAW
+              The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.
+              9
+              1
+              read-write
+            
+            
+              SLV_RD_BUF_DONE_INT_RAW
+              The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.
+              10
+              1
+              read-write
+            
+            
+              SLV_WR_BUF_DONE_INT_RAW
+              The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.
+              11
+              1
+              read-write
+            
+            
+              TRANS_DONE_INT_RAW
+              The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.
+              12
+              1
+              read-write
+            
+            
+              DMA_SEG_TRANS_DONE_INT_RAW
+              The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.
+              13
+              1
+              read-write
+            
+            
+              SEG_MAGIC_ERR_INT_RAW
+              The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.
+              14
+              1
+              read-write
+            
+            
+              SLV_BUF_ADDR_ERR_INT_RAW
+              The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.
+              15
+              1
+              read-write
+            
+            
+              SLV_CMD_ERR_INT_RAW
+              The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.
+              16
+              1
+              read-write
+            
+            
+              MST_RX_AFIFO_WFULL_ERR_INT_RAW
+              The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.
+              17
+              1
+              read-write
+            
+            
+              MST_TX_AFIFO_REMPTY_ERR_INT_RAW
+              The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+              18
+              1
+              read-write
+            
+            
+              APP2_INT_RAW
+              The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.
+              19
+              1
+              read-write
+            
+            
+              APP1_INT_RAW
+              The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.
+              20
+              1
+              read-write
+            
+          
+        
+        
+          DMA_INT_ST
+          SPI DMA interrupt status register
+          0x40
+          0x20
+          
+            
+              DMA_INFIFO_FULL_ERR_INT_ST
+              The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              DMA_OUTFIFO_EMPTY_ERR_INT_ST
+              The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              SLV_EX_QPI_INT_ST
+              The status bit for SPI slave Ex_QPI interrupt.
+              2
+              1
+              read-only
+            
+            
+              SLV_EN_QPI_INT_ST
+              The status bit for SPI slave En_QPI interrupt.
+              3
+              1
+              read-only
+            
+            
+              SLV_CMD7_INT_ST
+              The status bit for SPI slave CMD7 interrupt.
+              4
+              1
+              read-only
+            
+            
+              SLV_CMD8_INT_ST
+              The status bit for SPI slave CMD8 interrupt.
+              5
+              1
+              read-only
+            
+            
+              SLV_CMD9_INT_ST
+              The status bit for SPI slave CMD9 interrupt.
+              6
+              1
+              read-only
+            
+            
+              SLV_CMDA_INT_ST
+              The status bit for SPI slave CMDA interrupt.
+              7
+              1
+              read-only
+            
+            
+              SLV_RD_DMA_DONE_INT_ST
+              The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+              8
+              1
+              read-only
+            
+            
+              SLV_WR_DMA_DONE_INT_ST
+              The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+              9
+              1
+              read-only
+            
+            
+              SLV_RD_BUF_DONE_INT_ST
+              The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+              10
+              1
+              read-only
+            
+            
+              SLV_WR_BUF_DONE_INT_ST
+              The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+              11
+              1
+              read-only
+            
+            
+              TRANS_DONE_INT_ST
+              The status bit for SPI_TRANS_DONE_INT interrupt.
+              12
+              1
+              read-only
+            
+            
+              DMA_SEG_TRANS_DONE_INT_ST
+              The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+              13
+              1
+              read-only
+            
+            
+              SEG_MAGIC_ERR_INT_ST
+              The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+              14
+              1
+              read-only
+            
+            
+              SLV_BUF_ADDR_ERR_INT_ST
+              The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+              15
+              1
+              read-only
+            
+            
+              SLV_CMD_ERR_INT_ST
+              The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+              16
+              1
+              read-only
+            
+            
+              MST_RX_AFIFO_WFULL_ERR_INT_ST
+              The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+              17
+              1
+              read-only
+            
+            
+              MST_TX_AFIFO_REMPTY_ERR_INT_ST
+              The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+              18
+              1
+              read-only
+            
+            
+              APP2_INT_ST
+              The status bit for SPI_APP2_INT interrupt.
+              19
+              1
+              read-only
+            
+            
+              APP1_INT_ST
+              The status bit for SPI_APP1_INT interrupt.
+              20
+              1
+              read-only
+            
+          
+        
+        
+          W0
+          SPI CPU-controlled buffer0
+          0x98
+          0x20
+          
+            
+              BUF0
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W1
+          SPI CPU-controlled buffer1
+          0x9C
+          0x20
+          
+            
+              BUF1
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W2
+          SPI CPU-controlled buffer2
+          0xA0
+          0x20
+          
+            
+              BUF2
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W3
+          SPI CPU-controlled buffer3
+          0xA4
+          0x20
+          
+            
+              BUF3
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W4
+          SPI CPU-controlled buffer4
+          0xA8
+          0x20
+          
+            
+              BUF4
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W5
+          SPI CPU-controlled buffer5
+          0xAC
+          0x20
+          
+            
+              BUF5
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W6
+          SPI CPU-controlled buffer6
+          0xB0
+          0x20
+          
+            
+              BUF6
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W7
+          SPI CPU-controlled buffer7
+          0xB4
+          0x20
+          
+            
+              BUF7
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W8
+          SPI CPU-controlled buffer8
+          0xB8
+          0x20
+          
+            
+              BUF8
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W9
+          SPI CPU-controlled buffer9
+          0xBC
+          0x20
+          
+            
+              BUF9
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W10
+          SPI CPU-controlled buffer10
+          0xC0
+          0x20
+          
+            
+              BUF10
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W11
+          SPI CPU-controlled buffer11
+          0xC4
+          0x20
+          
+            
+              BUF11
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W12
+          SPI CPU-controlled buffer12
+          0xC8
+          0x20
+          
+            
+              BUF12
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W13
+          SPI CPU-controlled buffer13
+          0xCC
+          0x20
+          
+            
+              BUF13
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W14
+          SPI CPU-controlled buffer14
+          0xD0
+          0x20
+          
+            
+              BUF14
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          W15
+          SPI CPU-controlled buffer15
+          0xD4
+          0x20
+          
+            
+              BUF15
+              data buffer
+              0
+              32
+              read-write
+            
+          
+        
+        
+          SLAVE
+          SPI slave control register
+          0xE0
+          0x20
+          0x02800000
+          
+            
+              CLK_MODE
+              SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.
+              0
+              2
+              read-write
+            
+            
+              CLK_MODE_13
+              {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+              2
+              1
+              read-write
+            
+            
+              RSCK_DATA_OUT
+              It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge
+              3
+              1
+              read-write
+            
+            
+              SLV_RDDMA_BITLEN_EN
+              1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others
+              8
+              1
+              read-write
+            
+            
+              SLV_WRDMA_BITLEN_EN
+              1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others
+              9
+              1
+              read-write
+            
+            
+              SLV_RDBUF_BITLEN_EN
+              1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others
+              10
+              1
+              read-write
+            
+            
+              SLV_WRBUF_BITLEN_EN
+              1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others
+              11
+              1
+              read-write
+            
+            
+              DMA_SEG_MAGIC_VALUE
+              The magic value of BM table in master DMA seg-trans.
+              22
+              4
+              read-write
+            
+            
+              MODE
+              Set SPI work mode. 1: slave mode 0: master mode.
+              26
+              1
+              read-write
+            
+            
+              SOFT_RESET
+              Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.
+              27
+              1
+              write-only
+            
+            
+              USR_CONF
+              1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.
+              28
+              1
+              read-write
+            
+          
+        
+        
+          SLAVE1
+          SPI slave control register 1
+          0xE4
+          0x20
+          
+            
+              SLV_DATA_BITLEN
+              The transferred data bit length in SPI slave FD and HD mode.
+              0
+              18
+              read-write
+            
+            
+              SLV_LAST_COMMAND
+              In the slave mode it is the value of command.
+              18
+              8
+              read-write
+            
+            
+              SLV_LAST_ADDR
+              In the slave mode it is the value of address.
+              26
+              6
+              read-write
+            
+          
+        
+        
+          CLK_GATE
+          SPI module clock and register clock control
+          0xE8
+          0x20
+          
+            
+              CLK_EN
+              Set this bit to enable clk gate
+              0
+              1
+              read-write
+            
+            
+              MST_CLK_ACTIVE
+              Set this bit to power on the SPI module clock.
+              1
+              1
+              read-write
+            
+            
+              MST_CLK_SEL
+              This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.
+              2
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          Version control
+          0xF0
+          0x20
+          0x02007220
+          
+            
+              DATE
+              SPI register version.
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SYSTEM
+      System
+      SYSTEM
+      0x600C0000
+      
+        0x0
+        0xA0
+        registers
+      
+      
+        
+          CPU_PERI_CLK_EN
+          cpu_peripheral clock gating register
+          0x0
+          0x20
+          
+            
+              CLK_EN_ASSIST_DEBUG
+              reg_clk_en_assist_debug
+              6
+              1
+              read-write
+            
+            
+              CLK_EN_DEDICATED_GPIO
+              reg_clk_en_dedicated_gpio
+              7
+              1
+              read-write
+            
+          
+        
+        
+          CPU_PERI_RST_EN
+          cpu_peripheral reset register
+          0x4
+          0x20
+          0x000000C0
+          
+            
+              RST_EN_ASSIST_DEBUG
+              reg_rst_en_assist_debug
+              6
+              1
+              read-write
+            
+            
+              RST_EN_DEDICATED_GPIO
+              reg_rst_en_dedicated_gpio
+              7
+              1
+              read-write
+            
+          
+        
+        
+          CPU_PER_CONF
+          cpu clock config register
+          0x8
+          0x20
+          0x0000000C
+          
+            
+              CPUPERIOD_SEL
+              reg_cpuperiod_sel
+              0
+              2
+              read-write
+            
+            
+              PLL_FREQ_SEL
+              reg_pll_freq_sel
+              2
+              1
+              read-write
+            
+            
+              CPU_WAIT_MODE_FORCE_ON
+              reg_cpu_wait_mode_force_on
+              3
+              1
+              read-write
+            
+            
+              CPU_WAITI_DELAY_NUM
+              reg_cpu_waiti_delay_num
+              4
+              4
+              read-write
+            
+          
+        
+        
+          MEM_PD_MASK
+          memory power down mask register
+          0xC
+          0x20
+          0x00000001
+          
+            
+              LSLP_MEM_PD_MASK
+              reg_lslp_mem_pd_mask
+              0
+              1
+              read-write
+            
+          
+        
+        
+          PERIP_CLK_EN0
+          peripheral clock gating register
+          0x10
+          0x20
+          0xF9C1E06F
+          
+            
+              TIMERS_CLK_EN
+              reg_timers_clk_en
+              0
+              1
+              read-write
+            
+            
+              SPI01_CLK_EN
+              reg_spi01_clk_en
+              1
+              1
+              read-write
+            
+            
+              UART_CLK_EN
+              reg_uart_clk_en
+              2
+              1
+              read-write
+            
+            
+              WDG_CLK_EN
+              reg_wdg_clk_en
+              3
+              1
+              read-write
+            
+            
+              I2S0_CLK_EN
+              reg_i2s0_clk_en
+              4
+              1
+              read-write
+            
+            
+              UART1_CLK_EN
+              reg_uart1_clk_en
+              5
+              1
+              read-write
+            
+            
+              SPI2_CLK_EN
+              reg_spi2_clk_en
+              6
+              1
+              read-write
+            
+            
+              I2C_EXT0_CLK_EN
+              reg_ext0_clk_en
+              7
+              1
+              read-write
+            
+            
+              UHCI0_CLK_EN
+              reg_uhci0_clk_en
+              8
+              1
+              read-write
+            
+            
+              RMT_CLK_EN
+              reg_rmt_clk_en
+              9
+              1
+              read-write
+            
+            
+              PCNT_CLK_EN
+              reg_pcnt_clk_en
+              10
+              1
+              read-write
+            
+            
+              LEDC_CLK_EN
+              reg_ledc_clk_en
+              11
+              1
+              read-write
+            
+            
+              UHCI1_CLK_EN
+              reg_uhci1_clk_en
+              12
+              1
+              read-write
+            
+            
+              TIMERGROUP_CLK_EN
+              reg_timergroup_clk_en
+              13
+              1
+              read-write
+            
+            
+              EFUSE_CLK_EN
+              reg_efuse_clk_en
+              14
+              1
+              read-write
+            
+            
+              TIMERGROUP1_CLK_EN
+              reg_timergroup1_clk_en
+              15
+              1
+              read-write
+            
+            
+              SPI3_CLK_EN
+              reg_spi3_clk_en
+              16
+              1
+              read-write
+            
+            
+              PWM0_CLK_EN
+              reg_pwm0_clk_en
+              17
+              1
+              read-write
+            
+            
+              EXT1_CLK_EN
+              reg_ext1_clk_en
+              18
+              1
+              read-write
+            
+            
+              CAN_CLK_EN
+              reg_can_clk_en
+              19
+              1
+              read-write
+            
+            
+              PWM1_CLK_EN
+              reg_pwm1_clk_en
+              20
+              1
+              read-write
+            
+            
+              I2S1_CLK_EN
+              reg_i2s1_clk_en
+              21
+              1
+              read-write
+            
+            
+              SPI2_DMA_CLK_EN
+              reg_spi2_dma_clk_en
+              22
+              1
+              read-write
+            
+            
+              USB_DEVICE_CLK_EN
+              reg_usb_device_clk_en
+              23
+              1
+              read-write
+            
+            
+              UART_MEM_CLK_EN
+              reg_uart_mem_clk_en
+              24
+              1
+              read-write
+            
+            
+              PWM2_CLK_EN
+              reg_pwm2_clk_en
+              25
+              1
+              read-write
+            
+            
+              PWM3_CLK_EN
+              reg_pwm3_clk_en
+              26
+              1
+              read-write
+            
+            
+              SPI3_DMA_CLK_EN
+              reg_spi3_dma_clk_en
+              27
+              1
+              read-write
+            
+            
+              APB_SARADC_CLK_EN
+              reg_apb_saradc_clk_en
+              28
+              1
+              read-write
+            
+            
+              SYSTIMER_CLK_EN
+              reg_systimer_clk_en
+              29
+              1
+              read-write
+            
+            
+              ADC2_ARB_CLK_EN
+              reg_adc2_arb_clk_en
+              30
+              1
+              read-write
+            
+            
+              SPI4_CLK_EN
+              reg_spi4_clk_en
+              31
+              1
+              read-write
+            
+          
+        
+        
+          PERIP_CLK_EN1
+          peripheral clock gating register
+          0x14
+          0x20
+          0x00000200
+          
+            
+              CRYPTO_AES_CLK_EN
+              reg_crypto_aes_clk_en
+              1
+              1
+              read-write
+            
+            
+              CRYPTO_SHA_CLK_EN
+              reg_crypto_sha_clk_en
+              2
+              1
+              read-write
+            
+            
+              CRYPTO_RSA_CLK_EN
+              reg_crypto_rsa_clk_en
+              3
+              1
+              read-write
+            
+            
+              CRYPTO_DS_CLK_EN
+              reg_crypto_ds_clk_en
+              4
+              1
+              read-write
+            
+            
+              CRYPTO_HMAC_CLK_EN
+              reg_crypto_hmac_clk_en
+              5
+              1
+              read-write
+            
+            
+              DMA_CLK_EN
+              reg_dma_clk_en
+              6
+              1
+              read-write
+            
+            
+              SDIO_HOST_CLK_EN
+              reg_sdio_host_clk_en
+              7
+              1
+              read-write
+            
+            
+              LCD_CAM_CLK_EN
+              reg_lcd_cam_clk_en
+              8
+              1
+              read-write
+            
+            
+              UART2_CLK_EN
+              reg_uart2_clk_en
+              9
+              1
+              read-write
+            
+            
+              TSENS_CLK_EN
+              reg_tsens_clk_en
+              10
+              1
+              read-write
+            
+          
+        
+        
+          PERIP_RST_EN0
+          reserved
+          0x18
+          0x20
+          
+            
+              TIMERS_RST
+              reg_timers_rst
+              0
+              1
+              read-write
+            
+            
+              SPI01_RST
+              reg_spi01_rst
+              1
+              1
+              read-write
+            
+            
+              UART_RST
+              reg_uart_rst
+              2
+              1
+              read-write
+            
+            
+              WDG_RST
+              reg_wdg_rst
+              3
+              1
+              read-write
+            
+            
+              I2S0_RST
+              reg_i2s0_rst
+              4
+              1
+              read-write
+            
+            
+              UART1_RST
+              reg_uart1_rst
+              5
+              1
+              read-write
+            
+            
+              SPI2_RST
+              reg_spi2_rst
+              6
+              1
+              read-write
+            
+            
+              I2C_EXT0_RST
+              reg_ext0_rst
+              7
+              1
+              read-write
+            
+            
+              UHCI0_RST
+              reg_uhci0_rst
+              8
+              1
+              read-write
+            
+            
+              RMT_RST
+              reg_rmt_rst
+              9
+              1
+              read-write
+            
+            
+              PCNT_RST
+              reg_pcnt_rst
+              10
+              1
+              read-write
+            
+            
+              LEDC_RST
+              reg_ledc_rst
+              11
+              1
+              read-write
+            
+            
+              UHCI1_RST
+              reg_uhci1_rst
+              12
+              1
+              read-write
+            
+            
+              TIMERGROUP_RST
+              reg_timergroup_rst
+              13
+              1
+              read-write
+            
+            
+              EFUSE_RST
+              reg_efuse_rst
+              14
+              1
+              read-write
+            
+            
+              TIMERGROUP1_RST
+              reg_timergroup1_rst
+              15
+              1
+              read-write
+            
+            
+              SPI3_RST
+              reg_spi3_rst
+              16
+              1
+              read-write
+            
+            
+              PWM0_RST
+              reg_pwm0_rst
+              17
+              1
+              read-write
+            
+            
+              EXT1_RST
+              reg_ext1_rst
+              18
+              1
+              read-write
+            
+            
+              CAN_RST
+              reg_can_rst
+              19
+              1
+              read-write
+            
+            
+              PWM1_RST
+              reg_pwm1_rst
+              20
+              1
+              read-write
+            
+            
+              I2S1_RST
+              reg_i2s1_rst
+              21
+              1
+              read-write
+            
+            
+              SPI2_DMA_RST
+              reg_spi2_dma_rst
+              22
+              1
+              read-write
+            
+            
+              USB_DEVICE_RST
+              reg_usb_device_rst
+              23
+              1
+              read-write
+            
+            
+              UART_MEM_RST
+              reg_uart_mem_rst
+              24
+              1
+              read-write
+            
+            
+              PWM2_RST
+              reg_pwm2_rst
+              25
+              1
+              read-write
+            
+            
+              PWM3_RST
+              reg_pwm3_rst
+              26
+              1
+              read-write
+            
+            
+              SPI3_DMA_RST
+              reg_spi3_dma_rst
+              27
+              1
+              read-write
+            
+            
+              APB_SARADC_RST
+              reg_apb_saradc_rst
+              28
+              1
+              read-write
+            
+            
+              SYSTIMER_RST
+              reg_systimer_rst
+              29
+              1
+              read-write
+            
+            
+              ADC2_ARB_RST
+              reg_adc2_arb_rst
+              30
+              1
+              read-write
+            
+            
+              SPI4_RST
+              reg_spi4_rst
+              31
+              1
+              read-write
+            
+          
+        
+        
+          PERIP_RST_EN1
+          peripheral reset register
+          0x1C
+          0x20
+          0x000001FE
+          
+            
+              CRYPTO_AES_RST
+              reg_crypto_aes_rst
+              1
+              1
+              read-write
+            
+            
+              CRYPTO_SHA_RST
+              reg_crypto_sha_rst
+              2
+              1
+              read-write
+            
+            
+              CRYPTO_RSA_RST
+              reg_crypto_rsa_rst
+              3
+              1
+              read-write
+            
+            
+              CRYPTO_DS_RST
+              reg_crypto_ds_rst
+              4
+              1
+              read-write
+            
+            
+              CRYPTO_HMAC_RST
+              reg_crypto_hmac_rst
+              5
+              1
+              read-write
+            
+            
+              DMA_RST
+              reg_dma_rst
+              6
+              1
+              read-write
+            
+            
+              SDIO_HOST_RST
+              reg_sdio_host_rst
+              7
+              1
+              read-write
+            
+            
+              LCD_CAM_RST
+              reg_lcd_cam_rst
+              8
+              1
+              read-write
+            
+            
+              UART2_RST
+              reg_uart2_rst
+              9
+              1
+              read-write
+            
+            
+              TSENS_RST
+              reg_tsens_rst
+              10
+              1
+              read-write
+            
+          
+        
+        
+          BT_LPCK_DIV_INT
+          clock config register
+          0x20
+          0x20
+          0x000000FF
+          
+            
+              BT_LPCK_DIV_NUM
+              reg_bt_lpck_div_num
+              0
+              12
+              read-write
+            
+          
+        
+        
+          BT_LPCK_DIV_FRAC
+          clock config register
+          0x24
+          0x20
+          0x02001001
+          
+            
+              BT_LPCK_DIV_B
+              reg_bt_lpck_div_b
+              0
+              12
+              read-write
+            
+            
+              BT_LPCK_DIV_A
+              reg_bt_lpck_div_a
+              12
+              12
+              read-write
+            
+            
+              LPCLK_SEL_RTC_SLOW
+              reg_lpclk_sel_rtc_slow
+              24
+              1
+              read-write
+            
+            
+              LPCLK_SEL_8M
+              reg_lpclk_sel_8m
+              25
+              1
+              read-write
+            
+            
+              LPCLK_SEL_XTAL
+              reg_lpclk_sel_xtal
+              26
+              1
+              read-write
+            
+            
+              LPCLK_SEL_XTAL32K
+              reg_lpclk_sel_xtal32k
+              27
+              1
+              read-write
+            
+            
+              LPCLK_RTC_EN
+              reg_lpclk_rtc_en
+              28
+              1
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_0
+          interrupt generate register
+          0x28
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_0
+              reg_cpu_intr_from_cpu_0
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_1
+          interrupt generate register
+          0x2C
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_1
+              reg_cpu_intr_from_cpu_1
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_2
+          interrupt generate register
+          0x30
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_2
+              reg_cpu_intr_from_cpu_2
+              0
+              1
+              read-write
+            
+          
+        
+        
+          CPU_INTR_FROM_CPU_3
+          interrupt generate register
+          0x34
+          0x20
+          
+            
+              CPU_INTR_FROM_CPU_3
+              reg_cpu_intr_from_cpu_3
+              0
+              1
+              read-write
+            
+          
+        
+        
+          RSA_PD_CTRL
+          rsa memory power control register
+          0x38
+          0x20
+          0x00000001
+          
+            
+              RSA_MEM_PD
+              reg_rsa_mem_pd
+              0
+              1
+              read-write
+            
+            
+              RSA_MEM_FORCE_PU
+              reg_rsa_mem_force_pu
+              1
+              1
+              read-write
+            
+            
+              RSA_MEM_FORCE_PD
+              reg_rsa_mem_force_pd
+              2
+              1
+              read-write
+            
+          
+        
+        
+          EDMA_CTRL
+          edma clcok and reset register
+          0x3C
+          0x20
+          0x00000001
+          
+            
+              EDMA_CLK_ON
+              reg_edma_clk_on
+              0
+              1
+              read-write
+            
+            
+              EDMA_RESET
+              reg_edma_reset
+              1
+              1
+              read-write
+            
+          
+        
+        
+          CACHE_CONTROL
+          cache control register
+          0x40
+          0x20
+          0x00000005
+          
+            
+              ICACHE_CLK_ON
+              reg_icache_clk_on
+              0
+              1
+              read-write
+            
+            
+              ICACHE_RESET
+              reg_icache_reset
+              1
+              1
+              read-write
+            
+            
+              DCACHE_CLK_ON
+              reg_dcache_clk_on
+              2
+              1
+              read-write
+            
+            
+              DCACHE_RESET
+              reg_dcache_reset
+              3
+              1
+              read-write
+            
+          
+        
+        
+          EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL
+          SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
+          0x44
+          0x20
+          
+            
+              ENABLE_SPI_MANUAL_ENCRYPT
+              reg_enable_spi_manual_encrypt
+              0
+              1
+              read-write
+            
+            
+              ENABLE_DOWNLOAD_DB_ENCRYPT
+              reg_enable_download_db_encrypt
+              1
+              1
+              read-write
+            
+            
+              ENABLE_DOWNLOAD_G0CB_DECRYPT
+              reg_enable_download_g0cb_decrypt
+              2
+              1
+              read-write
+            
+            
+              ENABLE_DOWNLOAD_MANUAL_ENCRYPT
+              reg_enable_download_manual_encrypt
+              3
+              1
+              read-write
+            
+          
+        
+        
+          RTC_FASTMEM_CONFIG
+          fast memory config register
+          0x48
+          0x20
+          0x7FF00000
+          
+            
+              RTC_MEM_CRC_START
+              reg_rtc_mem_crc_start
+              8
+              1
+              read-write
+            
+            
+              RTC_MEM_CRC_ADDR
+              reg_rtc_mem_crc_addr
+              9
+              11
+              read-write
+            
+            
+              RTC_MEM_CRC_LEN
+              reg_rtc_mem_crc_len
+              20
+              11
+              read-write
+            
+            
+              RTC_MEM_CRC_FINISH
+              reg_rtc_mem_crc_finish
+              31
+              1
+              read-only
+            
+          
+        
+        
+          RTC_FASTMEM_CRC
+          reserved
+          0x4C
+          0x20
+          
+            
+              RTC_MEM_CRC_RES
+              reg_rtc_mem_crc_res
+              0
+              32
+              read-only
+            
+          
+        
+        
+          REDUNDANT_ECO_CTRL
+          eco register
+          0x50
+          0x20
+          
+            
+              REDUNDANT_ECO_DRIVE
+              reg_redundant_eco_drive
+              0
+              1
+              read-write
+            
+            
+              REDUNDANT_ECO_RESULT
+              reg_redundant_eco_result
+              1
+              1
+              read-only
+            
+          
+        
+        
+          CLOCK_GATE
+          clock gating register
+          0x54
+          0x20
+          0x00000001
+          
+            
+              CLK_EN
+              reg_clk_en
+              0
+              1
+              read-write
+            
+          
+        
+        
+          SYSCLK_CONF
+          system clock config register
+          0x58
+          0x20
+          0x00000001
+          
+            
+              PRE_DIV_CNT
+              reg_pre_div_cnt
+              0
+              10
+              read-write
+            
+            
+              SOC_CLK_SEL
+              reg_soc_clk_sel
+              10
+              2
+              read-write
+            
+            
+              CLK_XTAL_FREQ
+              reg_clk_xtal_freq
+              12
+              7
+              read-only
+            
+            
+              CLK_DIV_EN
+              reg_clk_div_en
+              19
+              1
+              read-only
+            
+          
+        
+        
+          MEM_PVT
+          mem pvt register
+          0x5C
+          0x20
+          0x00000003
+          
+            
+              MEM_PATH_LEN
+              reg_mem_path_len
+              0
+              4
+              read-write
+            
+            
+              MEM_ERR_CNT_CLR
+              reg_mem_err_cnt_clr
+              4
+              1
+              write-only
+            
+            
+              MONITOR_EN
+              reg_mem_pvt_monitor_en
+              5
+              1
+              read-write
+            
+            
+              MEM_TIMING_ERR_CNT
+              reg_mem_timing_err_cnt
+              6
+              16
+              read-only
+            
+            
+              MEM_VT_SEL
+              reg_mem_vt_sel
+              22
+              2
+              read-write
+            
+          
+        
+        
+          COMB_PVT_LVT_CONF
+          mem pvt register
+          0x60
+          0x20
+          0x00000003
+          
+            
+              COMB_PATH_LEN_LVT
+              reg_comb_path_len_lvt
+              0
+              5
+              read-write
+            
+            
+              COMB_ERR_CNT_CLR_LVT
+              reg_comb_err_cnt_clr_lvt
+              5
+              1
+              write-only
+            
+            
+              COMB_PVT_MONITOR_EN_LVT
+              reg_comb_pvt_monitor_en_lvt
+              6
+              1
+              read-write
+            
+          
+        
+        
+          COMB_PVT_NVT_CONF
+          mem pvt register
+          0x64
+          0x20
+          0x00000003
+          
+            
+              COMB_PATH_LEN_NVT
+              reg_comb_path_len_nvt
+              0
+              5
+              read-write
+            
+            
+              COMB_ERR_CNT_CLR_NVT
+              reg_comb_err_cnt_clr_nvt
+              5
+              1
+              write-only
+            
+            
+              COMB_PVT_MONITOR_EN_NVT
+              reg_comb_pvt_monitor_en_nvt
+              6
+              1
+              read-write
+            
+          
+        
+        
+          COMB_PVT_HVT_CONF
+          mem pvt register
+          0x68
+          0x20
+          0x00000003
+          
+            
+              COMB_PATH_LEN_HVT
+              reg_comb_path_len_hvt
+              0
+              5
+              read-write
+            
+            
+              COMB_ERR_CNT_CLR_HVT
+              reg_comb_err_cnt_clr_hvt
+              5
+              1
+              write-only
+            
+            
+              COMB_PVT_MONITOR_EN_HVT
+              reg_comb_pvt_monitor_en_hvt
+              6
+              1
+              read-write
+            
+          
+        
+        
+          COMB_PVT_ERR_LVT_SITE0
+          mem pvt register
+          0x6C
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_LVT_SITE0
+              reg_comb_timing_err_cnt_lvt_site0
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_NVT_SITE0
+          mem pvt register
+          0x70
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_NVT_SITE0
+              reg_comb_timing_err_cnt_nvt_site0
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_HVT_SITE0
+          mem pvt register
+          0x74
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_HVT_SITE0
+              reg_comb_timing_err_cnt_hvt_site0
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_LVT_SITE1
+          mem pvt register
+          0x78
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_LVT_SITE1
+              reg_comb_timing_err_cnt_lvt_site1
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_NVT_SITE1
+          mem pvt register
+          0x7C
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_NVT_SITE1
+              reg_comb_timing_err_cnt_nvt_site1
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_HVT_SITE1
+          mem pvt register
+          0x80
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_HVT_SITE1
+              reg_comb_timing_err_cnt_hvt_site1
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_LVT_SITE2
+          mem pvt register
+          0x84
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_LVT_SITE2
+              reg_comb_timing_err_cnt_lvt_site2
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_NVT_SITE2
+          mem pvt register
+          0x88
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_NVT_SITE2
+              reg_comb_timing_err_cnt_nvt_site2
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_HVT_SITE2
+          mem pvt register
+          0x8C
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_HVT_SITE2
+              reg_comb_timing_err_cnt_hvt_site2
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_LVT_SITE3
+          mem pvt register
+          0x90
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_LVT_SITE3
+              reg_comb_timing_err_cnt_lvt_site3
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_NVT_SITE3
+          mem pvt register
+          0x94
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_NVT_SITE3
+              reg_comb_timing_err_cnt_nvt_site3
+              0
+              16
+              read-only
+            
+          
+        
+        
+          COMB_PVT_ERR_HVT_SITE3
+          mem pvt register
+          0x98
+          0x20
+          
+            
+              COMB_TIMING_ERR_CNT_HVT_SITE3
+              reg_comb_timing_err_cnt_hvt_site3
+              0
+              16
+              read-only
+            
+          
+        
+        
+          SYSTEM_REG_DATE
+          Version register
+          0xFFC
+          0x20
+          0x02007150
+          
+            
+              SYSTEM_REG_DATE
+              reg_system_reg_date
+              0
+              28
+              read-write
+            
+          
+        
+      
+    
+    
+      SYSTIMER
+      System Timer
+      SYSTIMER
+      0x60023000
+      
+        0x0
+        0x78
+        registers
+      
+      
+        SYSTIMER_TARGET0
+        37
+      
+      
+        SYSTIMER_TARGET1
+        38
+      
+      
+        SYSTIMER_TARGET2
+        39
+      
+      
+        
+          CONF
+          SYSTIMER_CONF.
+          0x0
+          0x20
+          0x46000000
+          
+            
+              SYSTIMER_CLK_FO
+              systimer clock force on
+              0
+              1
+              read-write
+            
+            
+              TARGET2_WORK_EN
+              target2 work enable
+              22
+              1
+              read-write
+            
+            
+              TARGET1_WORK_EN
+              target1 work enable
+              23
+              1
+              read-write
+            
+            
+              TARGET0_WORK_EN
+              target0 work enable
+              24
+              1
+              read-write
+            
+            
+              TIMER_UNIT1_CORE1_STALL_EN
+              If timer unit1 is stalled when core1 stalled
+              25
+              1
+              read-write
+            
+            
+              TIMER_UNIT1_CORE0_STALL_EN
+              If timer unit1 is stalled when core0 stalled
+              26
+              1
+              read-write
+            
+            
+              TIMER_UNIT0_CORE1_STALL_EN
+              If timer unit0 is stalled when core1 stalled
+              27
+              1
+              read-write
+            
+            
+              TIMER_UNIT0_CORE0_STALL_EN
+              If timer unit0 is stalled when core0 stalled
+              28
+              1
+              read-write
+            
+            
+              TIMER_UNIT1_WORK_EN
+              timer unit1 work enable
+              29
+              1
+              read-write
+            
+            
+              TIMER_UNIT0_WORK_EN
+              timer unit0 work enable
+              30
+              1
+              read-write
+            
+            
+              CLK_EN
+              register file clk gating
+              31
+              1
+              read-write
+            
+          
+        
+        
+          UNIT0_OP
+          SYSTIMER_UNIT0_OP.
+          0x4
+          0x20
+          
+            
+              TIMER_UNIT0_VALUE_VALID
+              reg_timer_unit0_value_valid
+              29
+              1
+              read-only
+            
+            
+              TIMER_UNIT0_UPDATE
+              update timer_unit0
+              30
+              1
+              write-only
+            
+          
+        
+        
+          UNIT1_OP
+          SYSTIMER_UNIT1_OP.
+          0x8
+          0x20
+          
+            
+              TIMER_UNIT1_VALUE_VALID
+              timer value is sync and valid
+              29
+              1
+              read-only
+            
+            
+              TIMER_UNIT1_UPDATE
+              update timer unit1
+              30
+              1
+              write-only
+            
+          
+        
+        
+          UNIT0_LOAD_HI
+          SYSTIMER_UNIT0_LOAD_HI.
+          0xC
+          0x20
+          
+            
+              TIMER_UNIT0_LOAD_HI
+              timer unit0 load high 32 bit
+              0
+              20
+              read-write
+            
+          
+        
+        
+          UNIT0_LOAD_LO
+          SYSTIMER_UNIT0_LOAD_LO.
+          0x10
+          0x20
+          
+            
+              TIMER_UNIT0_LOAD_LO
+              timer unit0 load low 32 bit
+              0
+              32
+              read-write
+            
+          
+        
+        
+          UNIT1_LOAD_HI
+          SYSTIMER_UNIT1_LOAD_HI.
+          0x14
+          0x20
+          
+            
+              TIMER_UNIT1_LOAD_HI
+              timer unit1 load high 32 bit
+              0
+              20
+              read-write
+            
+          
+        
+        
+          UNIT1_LOAD_LO
+          SYSTIMER_UNIT1_LOAD_LO.
+          0x18
+          0x20
+          
+            
+              TIMER_UNIT1_LOAD_LO
+              timer unit1 load low 32 bit
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TARGET0_HI
+          SYSTIMER_TARGET0_HI.
+          0x1C
+          0x20
+          
+            
+              TIMER_TARGET0_HI
+              timer taget0 high 32 bit
+              0
+              20
+              read-write
+            
+          
+        
+        
+          TARGET0_LO
+          SYSTIMER_TARGET0_LO.
+          0x20
+          0x20
+          
+            
+              TIMER_TARGET0_LO
+              timer taget0 low 32 bit
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TARGET1_HI
+          SYSTIMER_TARGET1_HI.
+          0x24
+          0x20
+          
+            
+              TIMER_TARGET1_HI
+              timer taget1 high 32 bit
+              0
+              20
+              read-write
+            
+          
+        
+        
+          TARGET1_LO
+          SYSTIMER_TARGET1_LO.
+          0x28
+          0x20
+          
+            
+              TIMER_TARGET1_LO
+              timer taget1 low 32 bit
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TARGET2_HI
+          SYSTIMER_TARGET2_HI.
+          0x2C
+          0x20
+          
+            
+              TIMER_TARGET2_HI
+              timer taget2 high 32 bit
+              0
+              20
+              read-write
+            
+          
+        
+        
+          TARGET2_LO
+          SYSTIMER_TARGET2_LO.
+          0x30
+          0x20
+          
+            
+              TIMER_TARGET2_LO
+              timer taget2 low 32 bit
+              0
+              32
+              read-write
+            
+          
+        
+        
+          TARGET0_CONF
+          SYSTIMER_TARGET0_CONF.
+          0x34
+          0x20
+          
+            
+              TARGET0_PERIOD
+              target0 period
+              0
+              26
+              read-write
+            
+            
+              TARGET0_PERIOD_MODE
+              Set target0 to period mode
+              30
+              1
+              read-write
+            
+            
+              TARGET0_TIMER_UNIT_SEL
+              select which unit to compare
+              31
+              1
+              read-write
+            
+          
+        
+        
+          TARGET1_CONF
+          SYSTIMER_TARGET1_CONF.
+          0x38
+          0x20
+          
+            
+              TARGET1_PERIOD
+              target1 period
+              0
+              26
+              read-write
+            
+            
+              TARGET1_PERIOD_MODE
+              Set target1 to period mode
+              30
+              1
+              read-write
+            
+            
+              TARGET1_TIMER_UNIT_SEL
+              select which unit to compare
+              31
+              1
+              read-write
+            
+          
+        
+        
+          TARGET2_CONF
+          SYSTIMER_TARGET2_CONF.
+          0x3C
+          0x20
+          
+            
+              TARGET2_PERIOD
+              target2 period
+              0
+              26
+              read-write
+            
+            
+              TARGET2_PERIOD_MODE
+              Set target2 to period mode
+              30
+              1
+              read-write
+            
+            
+              TARGET2_TIMER_UNIT_SEL
+              select which unit to compare
+              31
+              1
+              read-write
+            
+          
+        
+        
+          UNIT0_VALUE_HI
+          SYSTIMER_UNIT0_VALUE_HI.
+          0x40
+          0x20
+          
+            
+              TIMER_UNIT0_VALUE_HI
+              timer read value high 32bit
+              0
+              20
+              read-only
+            
+          
+        
+        
+          UNIT0_VALUE_LO
+          SYSTIMER_UNIT0_VALUE_LO.
+          0x44
+          0x20
+          
+            
+              TIMER_UNIT0_VALUE_LO
+              timer read value low 32bit
+              0
+              32
+              read-only
+            
+          
+        
+        
+          UNIT1_VALUE_HI
+          SYSTIMER_UNIT1_VALUE_HI.
+          0x48
+          0x20
+          
+            
+              TIMER_UNIT1_VALUE_HI
+              timer read value high 32bit
+              0
+              20
+              read-only
+            
+          
+        
+        
+          UNIT1_VALUE_LO
+          SYSTIMER_UNIT1_VALUE_LO.
+          0x4C
+          0x20
+          
+            
+              TIMER_UNIT1_VALUE_LO
+              timer read value low 32bit
+              0
+              32
+              read-only
+            
+          
+        
+        
+          COMP0_LOAD
+          SYSTIMER_COMP0_LOAD.
+          0x50
+          0x20
+          
+            
+              TIMER_COMP0_LOAD
+              timer comp0 load value
+              0
+              1
+              write-only
+            
+          
+        
+        
+          COMP1_LOAD
+          SYSTIMER_COMP1_LOAD.
+          0x54
+          0x20
+          
+            
+              TIMER_COMP1_LOAD
+              timer comp1 load value
+              0
+              1
+              write-only
+            
+          
+        
+        
+          COMP2_LOAD
+          SYSTIMER_COMP2_LOAD.
+          0x58
+          0x20
+          
+            
+              TIMER_COMP2_LOAD
+              timer comp2 load value
+              0
+              1
+              write-only
+            
+          
+        
+        
+          UNIT0_LOAD
+          SYSTIMER_UNIT0_LOAD.
+          0x5C
+          0x20
+          
+            
+              TIMER_UNIT0_LOAD
+              timer unit0 load value
+              0
+              1
+              write-only
+            
+          
+        
+        
+          UNIT1_LOAD
+          SYSTIMER_UNIT1_LOAD.
+          0x60
+          0x20
+          
+            
+              TIMER_UNIT1_LOAD
+              timer unit1 load value
+              0
+              1
+              write-only
+            
+          
+        
+        
+          INT_ENA
+          SYSTIMER_INT_ENA.
+          0x64
+          0x20
+          
+            
+              TARGET0_INT_ENA
+              interupt0 enable
+              0
+              1
+              read-write
+            
+            
+              TARGET1_INT_ENA
+              interupt1 enable
+              1
+              1
+              read-write
+            
+            
+              TARGET2_INT_ENA
+              interupt2 enable
+              2
+              1
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          SYSTIMER_INT_RAW.
+          0x68
+          0x20
+          
+            
+              TARGET0_INT_RAW
+              interupt0 raw
+              0
+              1
+              read-only
+            
+            
+              TARGET1_INT_RAW
+              interupt1 raw
+              1
+              1
+              read-only
+            
+            
+              TARGET2_INT_RAW
+              interupt2 raw
+              2
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR
+          SYSTIMER_INT_CLR.
+          0x6C
+          0x20
+          
+            
+              TARGET0_INT_CLR
+              interupt0 clear
+              0
+              1
+              write-only
+            
+            
+              TARGET1_INT_CLR
+              interupt1 clear
+              1
+              1
+              write-only
+            
+            
+              TARGET2_INT_CLR
+              interupt2 clear
+              2
+              1
+              write-only
+            
+          
+        
+        
+          INT_ST
+          SYSTIMER_INT_ST.
+          0x70
+          0x20
+          
+            
+              TARGET0_INT_ST
+              reg_target0_int_st
+              0
+              1
+              read-only
+            
+            
+              TARGET1_INT_ST
+              reg_target1_int_st
+              1
+              1
+              read-only
+            
+            
+              TARGET2_INT_ST
+              reg_target2_int_st
+              2
+              1
+              read-only
+            
+          
+        
+        
+          DATE
+          SYSTIMER_DATE.
+          0xFC
+          0x20
+          0x02006171
+          
+            
+              DATE
+              reg_date
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      TIMG0
+      Timer Group
+      TIMG
+      0x6001F000
+      
+        0x0
+        0x68
+        registers
+      
+      
+        TG0_T0_LEVEL
+        32
+      
+      
+        TG0_WDT_LEVEL
+        33
+      
+      
+        
+          T0CONFIG
+          TIMG_T0CONFIG_REG.
+          0x0
+          0x20
+          0x60002000
+          
+            
+              T0_USE_XTAL
+              reg_t0_use_xtal.
+              9
+              1
+              read-write
+            
+            
+              T0_ALARM_EN
+              reg_t0_alarm_en.
+              10
+              1
+              read-write
+            
+            
+              T0_DIVCNT_RST
+              reg_t0_divcnt_rst.
+              12
+              1
+              write-only
+            
+            
+              T0_DIVIDER
+              reg_t0_divider.
+              13
+              16
+              read-write
+            
+            
+              T0_AUTORELOAD
+              reg_t0_autoreload.
+              29
+              1
+              read-write
+            
+            
+              T0_INCREASE
+              reg_t0_increase.
+              30
+              1
+              read-write
+            
+            
+              T0_EN
+              reg_t0_en.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          T0LO
+          TIMG_T0LO_REG.
+          0x4
+          0x20
+          
+            
+              T0_LO
+              t0_lo
+              0
+              32
+              read-only
+            
+          
+        
+        
+          T0HI
+          TIMG_T0HI_REG.
+          0x8
+          0x20
+          
+            
+              T0_HI
+              t0_hi
+              0
+              22
+              read-only
+            
+          
+        
+        
+          T0UPDATE
+          TIMG_T0UPDATE_REG.
+          0xC
+          0x20
+          
+            
+              T0_UPDATE
+              t0_update
+              31
+              1
+              read-write
+            
+          
+        
+        
+          T0ALARMLO
+          TIMG_T0ALARMLO_REG.
+          0x10
+          0x20
+          
+            
+              T0_ALARM_LO
+              reg_t0_alarm_lo.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          T0ALARMHI
+          TIMG_T0ALARMHI_REG.
+          0x14
+          0x20
+          
+            
+              T0_ALARM_HI
+              reg_t0_alarm_hi.
+              0
+              22
+              read-write
+            
+          
+        
+        
+          T0LOADLO
+          TIMG_T0LOADLO_REG.
+          0x18
+          0x20
+          
+            
+              T0_LOAD_LO
+              reg_t0_load_lo.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          T0LOADHI
+          TIMG_T0LOADHI_REG.
+          0x1C
+          0x20
+          
+            
+              T0_LOAD_HI
+              reg_t0_load_hi.
+              0
+              22
+              read-write
+            
+          
+        
+        
+          T0LOAD
+          TIMG_T0LOAD_REG.
+          0x20
+          0x20
+          
+            
+              T0_LOAD
+              t0_load
+              0
+              32
+              write-only
+            
+          
+        
+        
+          WDTCONFIG0
+          TIMG_WDTCONFIG0_REG.
+          0x48
+          0x20
+          0x0004C000
+          
+            
+              WDT_APPCPU_RESET_EN
+              reg_wdt_appcpu_reset_en.
+              12
+              1
+              read-write
+            
+            
+              WDT_PROCPU_RESET_EN
+              reg_wdt_procpu_reset_en.
+              13
+              1
+              read-write
+            
+            
+              WDT_FLASHBOOT_MOD_EN
+              reg_wdt_flashboot_mod_en.
+              14
+              1
+              read-write
+            
+            
+              WDT_SYS_RESET_LENGTH
+              reg_wdt_sys_reset_length.
+              15
+              3
+              read-write
+            
+            
+              WDT_CPU_RESET_LENGTH
+              reg_wdt_cpu_reset_length.
+              18
+              3
+              read-write
+            
+            
+              WDT_USE_XTAL
+              reg_wdt_use_xtal.
+              21
+              1
+              read-write
+            
+            
+              WDT_CONF_UPDATE_EN
+              reg_wdt_conf_update_en.
+              22
+              1
+              write-only
+            
+            
+              WDT_STG3
+              reg_wdt_stg3.
+              23
+              2
+              read-write
+            
+            
+              WDT_STG2
+              reg_wdt_stg2.
+              25
+              2
+              read-write
+            
+            
+              WDT_STG1
+              reg_wdt_stg1.
+              27
+              2
+              read-write
+            
+            
+              WDT_STG0
+              reg_wdt_stg0.
+              29
+              2
+              read-write
+            
+            
+              WDT_EN
+              reg_wdt_en.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          WDTCONFIG1
+          TIMG_WDTCONFIG1_REG.
+          0x4C
+          0x20
+          0x00010000
+          
+            
+              WDT_DIVCNT_RST
+              reg_wdt_divcnt_rst.
+              0
+              1
+              write-only
+            
+            
+              WDT_CLK_PRESCALE
+              reg_wdt_clk_prescale.
+              16
+              16
+              read-write
+            
+          
+        
+        
+          WDTCONFIG2
+          TIMG_WDTCONFIG2_REG.
+          0x50
+          0x20
+          0x018CBA80
+          
+            
+              WDT_STG0_HOLD
+              reg_wdt_stg0_hold.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG3
+          TIMG_WDTCONFIG3_REG.
+          0x54
+          0x20
+          0x07FFFFFF
+          
+            
+              WDT_STG1_HOLD
+              reg_wdt_stg1_hold.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG4
+          TIMG_WDTCONFIG4_REG.
+          0x58
+          0x20
+          0x000FFFFF
+          
+            
+              WDT_STG2_HOLD
+              reg_wdt_stg2_hold.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTCONFIG5
+          TIMG_WDTCONFIG5_REG.
+          0x5C
+          0x20
+          0x000FFFFF
+          
+            
+              WDT_STG3_HOLD
+              reg_wdt_stg3_hold.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          WDTFEED
+          TIMG_WDTFEED_REG.
+          0x60
+          0x20
+          
+            
+              WDT_FEED
+              wdt_feed
+              0
+              32
+              write-only
+            
+          
+        
+        
+          WDTWPROTECT
+          TIMG_WDTWPROTECT_REG.
+          0x64
+          0x20
+          0x50D83AA1
+          
+            
+              WDT_WKEY
+              reg_wdt_wkey.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          RTCCALICFG
+          TIMG_RTCCALICFG_REG.
+          0x68
+          0x20
+          0x00013000
+          
+            
+              RTC_CALI_START_CYCLING
+              reg_rtc_cali_start_cycling.
+              12
+              1
+              read-write
+            
+            
+              RTC_CALI_CLK_SEL
+              reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
+              13
+              2
+              read-write
+            
+            
+              RTC_CALI_RDY
+              rtc_cali_rdy
+              15
+              1
+              read-only
+            
+            
+              RTC_CALI_MAX
+              reg_rtc_cali_max.
+              16
+              15
+              read-write
+            
+            
+              RTC_CALI_START
+              reg_rtc_cali_start.
+              31
+              1
+              read-write
+            
+          
+        
+        
+          RTCCALICFG1
+          TIMG_RTCCALICFG1_REG.
+          0x6C
+          0x20
+          
+            
+              RTC_CALI_CYCLING_DATA_VLD
+              rtc_cali_cycling_data_vld
+              0
+              1
+              read-only
+            
+            
+              RTC_CALI_VALUE
+              rtc_cali_value
+              7
+              25
+              read-only
+            
+          
+        
+        
+          INT_ENA_TIMERS
+          INT_ENA_TIMG_REG
+          0x70
+          0x20
+          
+            
+              T0_INT_ENA
+              t0_int_ena
+              0
+              1
+              read-write
+            
+            
+              WDT_INT_ENA
+              wdt_int_ena
+              1
+              1
+              read-write
+            
+          
+        
+        
+          INT_RAW_TIMERS
+          INT_RAW_TIMG_REG
+          0x74
+          0x20
+          
+            
+              T0_INT_RAW
+              t0_int_raw
+              0
+              1
+              read-only
+            
+            
+              WDT_INT_RAW
+              wdt_int_raw
+              1
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST_TIMERS
+          INT_ST_TIMG_REG
+          0x78
+          0x20
+          
+            
+              T0_INT_ST
+              t0_int_st
+              0
+              1
+              read-only
+            
+            
+              WDT_INT_ST
+              wdt_int_st
+              1
+              1
+              read-only
+            
+          
+        
+        
+          INT_CLR_TIMERS
+          INT_CLR_TIMG_REG
+          0x7C
+          0x20
+          
+            
+              T0_INT_CLR
+              t0_int_clr
+              0
+              1
+              write-only
+            
+            
+              WDT_INT_CLR
+              wdt_int_clr
+              1
+              1
+              write-only
+            
+          
+        
+        
+          RTCCALICFG2
+          TIMG_RTCCALICFG2_REG.
+          0x80
+          0x20
+          0xFFFFFF98
+          
+            
+              RTC_CALI_TIMEOUT
+              timeoutindicator
+              0
+              1
+              read-only
+            
+            
+              RTC_CALI_TIMEOUT_RST_CNT
+              reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
+              3
+              4
+              read-write
+            
+            
+              RTC_CALI_TIMEOUT_THRES
+              reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
+              7
+              25
+              read-write
+            
+          
+        
+        
+          NTIMG_DATE
+          TIMG_NTIMG_DATE_REG.
+          0xF8
+          0x20
+          0x02006191
+          
+            
+              NTIMGS_DATE
+              reg_ntimers_date.
+              0
+              28
+              read-write
+            
+          
+        
+        
+          REGCLK
+          TIMG_REGCLK_REG.
+          0xFC
+          0x20
+          0x60000000
+          
+            
+              WDT_CLK_IS_ACTIVE
+              reg_wdt_clk_is_active.
+              29
+              1
+              read-write
+            
+            
+              TIMER_CLK_IS_ACTIVE
+              reg_timer_clk_is_active.
+              30
+              1
+              read-write
+            
+            
+              CLK_EN
+              reg_clk_en.
+              31
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      TIMG1
+      Timer Group
+      0x60020000
+      
+        TG1_T0_LEVEL
+        34
+      
+      
+        TG1_WDT_LEVEL
+        35
+      
+    
+    
+      TWAI
+      Two-Wire Automotive Interface
+      TWAI
+      0x6002B000
+      
+        0x0
+        0x6C
+        registers
+      
+      
+        TWAI
+        25
+      
+      
+        
+          MODE
+          Mode Register
+          0x0
+          0x20
+          0x00000001
+          
+            
+              RESET_MODE
+              This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.
+              0
+              1
+              read-write
+            
+            
+              LISTEN_ONLY_MODE
+              1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.
+              1
+              1
+              read-write
+            
+            
+              SELF_TEST_MODE
+              1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.
+              2
+              1
+              read-write
+            
+            
+              RX_FILTER_MODE
+              This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.
+              3
+              1
+              read-write
+            
+          
+        
+        
+          CMD
+          Command Register
+          0x4
+          0x20
+          
+            
+              TX_REQ
+              Set the bit to 1 to allow the driving nodes start transmission.
+              0
+              1
+              write-only
+            
+            
+              ABORT_TX
+              Set the bit to 1 to cancel a pending transmission request.
+              1
+              1
+              write-only
+            
+            
+              RELEASE_BUF
+              Set the bit to 1 to release the RX buffer.
+              2
+              1
+              write-only
+            
+            
+              CLR_OVERRUN
+              Set the bit to 1 to clear the data overrun status bit.
+              3
+              1
+              write-only
+            
+            
+              SELF_RX_REQ
+              Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.
+              4
+              1
+              write-only
+            
+          
+        
+        
+          STATUS
+          Status register
+          0x8
+          0x20
+          
+            
+              RX_BUF_ST
+              1: The data in the RX buffer is not empty, with at least one received data packet.
+              0
+              1
+              read-only
+            
+            
+              OVERRUN_ST
+              1: The RX FIFO is full and data overrun has occurred.
+              1
+              1
+              read-only
+            
+            
+              TX_BUF_ST
+              1: The TX buffer is empty, the CPU may write a message into it.
+              2
+              1
+              read-only
+            
+            
+              TX_COMPLETE
+              1: The TWAI controller has successfully received a packet from the bus.
+              3
+              1
+              read-only
+            
+            
+              RX_ST
+              1: The TWAI Controller is receiving a message from the bus.
+              4
+              1
+              read-only
+            
+            
+              TX_ST
+              1: The TWAI Controller is transmitting a message to the bus.
+              5
+              1
+              read-only
+            
+            
+              ERR_ST
+              1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.
+              6
+              1
+              read-only
+            
+            
+              BUS_OFF_ST
+              1: In bus-off status, the TWAI Controller is no longer involved in bus activities.
+              7
+              1
+              read-only
+            
+            
+              MISS_ST
+              This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete
+              8
+              1
+              read-only
+            
+          
+        
+        
+          INT_RAW
+          Interrupt Register
+          0xC
+          0x20
+          
+            
+              RX_INT_ST
+              Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.
+              0
+              1
+              read-only
+            
+            
+              TX_INT_ST
+              Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.
+              1
+              1
+              read-only
+            
+            
+              ERR_WARN_INT_ST
+              Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).
+              2
+              1
+              read-only
+            
+            
+              OVERRUN_INT_ST
+              Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.
+              3
+              1
+              read-only
+            
+            
+              ERR_PASSIVE_INT_ST
+              Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.
+              5
+              1
+              read-only
+            
+            
+              ARB_LOST_INT_ST
+              Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.
+              6
+              1
+              read-only
+            
+            
+              BUS_ERR_INT_ST
+              Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.
+              7
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          Interrupt Enable Register
+          0x10
+          0x20
+          
+            
+              RX_INT_ENA
+              Set this bit to 1 to enable receive interrupt.
+              0
+              1
+              read-write
+            
+            
+              TX_INT_ENA
+              Set this bit to 1 to enable transmit interrupt.
+              1
+              1
+              read-write
+            
+            
+              ERR_WARN_INT_ENA
+              Set this bit to 1 to enable error warning interrupt.
+              2
+              1
+              read-write
+            
+            
+              OVERRUN_INT_ENA
+              Set this bit to 1 to enable data overrun interrupt.
+              3
+              1
+              read-write
+            
+            
+              ERR_PASSIVE_INT_ENA
+              Set this bit to 1 to enable error passive interrupt.
+              5
+              1
+              read-write
+            
+            
+              ARB_LOST_INT_ENA
+              Set this bit to 1 to enable arbitration lost interrupt.
+              6
+              1
+              read-write
+            
+            
+              BUS_ERR_INT_ENA
+              Set this bit to 1 to enable error interrupt.
+              7
+              1
+              read-write
+            
+          
+        
+        
+          BUS_TIMING_0
+          Bus Timing Register 0
+          0x18
+          0x20
+          
+            
+              BAUD_PRESC
+              Baud Rate Prescaler, determines the frequency dividing ratio.
+              0
+              13
+            
+            
+              SYNC_JUMP_WIDTH
+              Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.
+              14
+              2
+            
+          
+        
+        
+          BUS_TIMING_1
+          Bus Timing Register 1
+          0x1C
+          0x20
+          
+            
+              TIME_SEG1
+              The width of PBS1.
+              0
+              4
+            
+            
+              TIME_SEG2
+              The width of PBS2.
+              4
+              3
+            
+            
+              TIME_SAMP
+              The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times
+              7
+              1
+            
+          
+        
+        
+          ARB_LOST_CAP
+          Arbitration Lost Capture Register
+          0x2C
+          0x20
+          
+            
+              ARB_LOST_CAP
+              This register contains information about the bit position of lost arbitration.
+              0
+              5
+              read-only
+            
+          
+        
+        
+          ERR_CODE_CAP
+          Error Code Capture Register
+          0x30
+          0x20
+          
+            
+              ECC_SEGMENT
+              This register contains information about the location of errors, see Table 181 for details.
+              0
+              5
+              read-only
+            
+            
+              ECC_DIRECTION
+              This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message
+              5
+              1
+              read-only
+            
+            
+              ECC_TYPE
+              This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error
+              6
+              2
+              read-only
+            
+          
+        
+        
+          ERR_WARNING_LIMIT
+          Error Warning Limit Register
+          0x34
+          0x20
+          0x00000060
+          
+            
+              ERR_WARNING_LIMIT
+              Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).
+              0
+              8
+            
+          
+        
+        
+          RX_ERR_CNT
+          Receive Error Counter Register
+          0x38
+          0x20
+          
+            
+              RX_ERR_CNT
+              The RX error counter register, reflects value changes under reception status.
+              0
+              8
+            
+          
+        
+        
+          TX_ERR_CNT
+          Transmit Error Counter Register
+          0x3C
+          0x20
+          
+            
+              TX_ERR_CNT
+              The TX error counter register, reflects value changes under transmission status.
+              0
+              8
+            
+          
+        
+        
+          DATA_0
+          Data register 0
+          0x40
+          0x20
+          
+            
+              TX_BYTE_0
+              In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_1
+          Data register 1
+          0x44
+          0x20
+          
+            
+              TX_BYTE_1
+              In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_2
+          Data register 2
+          0x48
+          0x20
+          
+            
+              TX_BYTE_2
+              In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_3
+          Data register 3
+          0x4C
+          0x20
+          
+            
+              TX_BYTE_3
+              In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_4
+          Data register 4
+          0x50
+          0x20
+          
+            
+              TX_BYTE_4
+              In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_5
+          Data register 5
+          0x54
+          0x20
+          
+            
+              TX_BYTE_5
+              In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_6
+          Data register 6
+          0x58
+          0x20
+          
+            
+              TX_BYTE_6
+              In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_7
+          Data register 7
+          0x5C
+          0x20
+          
+            
+              TX_BYTE_7
+              In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_8
+          Data register 8
+          0x60
+          0x20
+          
+            
+              TX_BYTE_8
+              Stored the 8th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_9
+          Data register 9
+          0x64
+          0x20
+          
+            
+              TX_BYTE_9
+              Stored the 9th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_10
+          Data register 10
+          0x68
+          0x20
+          
+            
+              TX_BYTE_10
+              Stored the 10th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_11
+          Data register 11
+          0x6C
+          0x20
+          
+            
+              TX_BYTE_11
+              Stored the 11th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          DATA_12
+          Data register 12
+          0x70
+          0x20
+          
+            
+              TX_BYTE_12
+              Stored the 12th byte information of the data to be transmitted under operating mode.
+              0
+              8
+              write-only
+            
+          
+        
+        
+          RX_MESSAGE_CNT
+          Receive Message Counter Register
+          0x74
+          0x20
+          
+            
+              RX_MESSAGE_COUNTER
+              This register reflects the number of messages available within the RX FIFO.
+              0
+              7
+              read-only
+            
+          
+        
+        
+          CLOCK_DIVIDER
+          Clock Divider register
+          0x7C
+          0x20
+          
+            
+              CD
+              These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.
+              0
+              8
+              read-write
+            
+            
+              CLOCK_OFF
+              This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin
+              8
+              1
+            
+          
+        
+      
+    
+    
+      UART0
+      UART (Universal Asynchronous Receiver-Transmitter) Controller
+      UART
+      0x60000000
+      
+        0x0
+        0x84
+        registers
+      
+      
+        UART0
+        21
+      
+      
+        
+          FIFO
+          FIFO data register
+          0x0
+          0x20
+          
+            
+              RXFIFO_RD_BYTE
+              UART 0 accesses FIFO via this register.
+              0
+              8
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          Raw interrupt status
+          0x4
+          0x20
+          0x00000002
+          
+            
+              RXFIFO_FULL_INT_RAW
+              This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.
+              0
+              1
+              read-only
+            
+            
+              TXFIFO_EMPTY_INT_RAW
+              This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .
+              1
+              1
+              read-only
+            
+            
+              PARITY_ERR_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a parity error in the data.
+              2
+              1
+              read-only
+            
+            
+              FRM_ERR_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a data frame error .
+              3
+              1
+              read-only
+            
+            
+              RXFIFO_OVF_INT_RAW
+              This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.
+              4
+              1
+              read-only
+            
+            
+              DSR_CHG_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.
+              5
+              1
+              read-only
+            
+            
+              CTS_CHG_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.
+              6
+              1
+              read-only
+            
+            
+              BRK_DET_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.
+              7
+              1
+              read-only
+            
+            
+              RXFIFO_TOUT_INT_RAW
+              This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.
+              8
+              1
+              read-only
+            
+            
+              SW_XON_INT_RAW
+              This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.
+              9
+              1
+              read-only
+            
+            
+              SW_XOFF_INT_RAW
+              This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.
+              10
+              1
+              read-only
+            
+            
+              GLITCH_DET_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.
+              11
+              1
+              read-only
+            
+            
+              TX_BRK_DONE_INT_RAW
+              This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.
+              12
+              1
+              read-only
+            
+            
+              TX_BRK_IDLE_DONE_INT_RAW
+              This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.
+              13
+              1
+              read-only
+            
+            
+              TX_DONE_INT_RAW
+              This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.
+              14
+              1
+              read-only
+            
+            
+              RS485_PARITY_ERR_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.
+              15
+              1
+              read-only
+            
+            
+              RS485_FRM_ERR_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.
+              16
+              1
+              read-only
+            
+            
+              RS485_CLASH_INT_RAW
+              This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.
+              17
+              1
+              read-only
+            
+            
+              AT_CMD_CHAR_DET_INT_RAW
+              This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.
+              18
+              1
+              read-only
+            
+            
+              WAKEUP_INT_RAW
+              This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.
+              19
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          Masked interrupt status
+          0x8
+          0x20
+          
+            
+              RXFIFO_FULL_INT_ST
+              This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+              0
+              1
+              read-only
+            
+            
+              TXFIFO_EMPTY_INT_ST
+              This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.
+              1
+              1
+              read-only
+            
+            
+              PARITY_ERR_INT_ST
+              This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+              2
+              1
+              read-only
+            
+            
+              FRM_ERR_INT_ST
+              This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+              3
+              1
+              read-only
+            
+            
+              RXFIFO_OVF_INT_ST
+              This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+              4
+              1
+              read-only
+            
+            
+              DSR_CHG_INT_ST
+              This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+              5
+              1
+              read-only
+            
+            
+              CTS_CHG_INT_ST
+              This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+              6
+              1
+              read-only
+            
+            
+              BRK_DET_INT_ST
+              This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+              7
+              1
+              read-only
+            
+            
+              RXFIFO_TOUT_INT_ST
+              This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+              8
+              1
+              read-only
+            
+            
+              SW_XON_INT_ST
+              This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+              9
+              1
+              read-only
+            
+            
+              SW_XOFF_INT_ST
+              This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+              10
+              1
+              read-only
+            
+            
+              GLITCH_DET_INT_ST
+              This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+              11
+              1
+              read-only
+            
+            
+              TX_BRK_DONE_INT_ST
+              This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+              12
+              1
+              read-only
+            
+            
+              TX_BRK_IDLE_DONE_INT_ST
+              This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.
+              13
+              1
+              read-only
+            
+            
+              TX_DONE_INT_ST
+              This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+              14
+              1
+              read-only
+            
+            
+              RS485_PARITY_ERR_INT_ST
+              This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.
+              15
+              1
+              read-only
+            
+            
+              RS485_FRM_ERR_INT_ST
+              This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.
+              16
+              1
+              read-only
+            
+            
+              RS485_CLASH_INT_ST
+              This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+              17
+              1
+              read-only
+            
+            
+              AT_CMD_CHAR_DET_INT_ST
+              This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.
+              18
+              1
+              read-only
+            
+            
+              WAKEUP_INT_ST
+              This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+              19
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          Interrupt enable bits
+          0xC
+          0x20
+          
+            
+              RXFIFO_FULL_INT_ENA
+              This is the enable bit for rxfifo_full_int_st register.
+              0
+              1
+              read-write
+            
+            
+              TXFIFO_EMPTY_INT_ENA
+              This is the enable bit for txfifo_empty_int_st register.
+              1
+              1
+              read-write
+            
+            
+              PARITY_ERR_INT_ENA
+              This is the enable bit for parity_err_int_st register.
+              2
+              1
+              read-write
+            
+            
+              FRM_ERR_INT_ENA
+              This is the enable bit for frm_err_int_st register.
+              3
+              1
+              read-write
+            
+            
+              RXFIFO_OVF_INT_ENA
+              This is the enable bit for rxfifo_ovf_int_st register.
+              4
+              1
+              read-write
+            
+            
+              DSR_CHG_INT_ENA
+              This is the enable bit for dsr_chg_int_st register.
+              5
+              1
+              read-write
+            
+            
+              CTS_CHG_INT_ENA
+              This is the enable bit for cts_chg_int_st register.
+              6
+              1
+              read-write
+            
+            
+              BRK_DET_INT_ENA
+              This is the enable bit for brk_det_int_st register.
+              7
+              1
+              read-write
+            
+            
+              RXFIFO_TOUT_INT_ENA
+              This is the enable bit for rxfifo_tout_int_st register.
+              8
+              1
+              read-write
+            
+            
+              SW_XON_INT_ENA
+              This is the enable bit for sw_xon_int_st register.
+              9
+              1
+              read-write
+            
+            
+              SW_XOFF_INT_ENA
+              This is the enable bit for sw_xoff_int_st register.
+              10
+              1
+              read-write
+            
+            
+              GLITCH_DET_INT_ENA
+              This is the enable bit for glitch_det_int_st register.
+              11
+              1
+              read-write
+            
+            
+              TX_BRK_DONE_INT_ENA
+              This is the enable bit for tx_brk_done_int_st register.
+              12
+              1
+              read-write
+            
+            
+              TX_BRK_IDLE_DONE_INT_ENA
+              This is the enable bit for tx_brk_idle_done_int_st register.
+              13
+              1
+              read-write
+            
+            
+              TX_DONE_INT_ENA
+              This is the enable bit for tx_done_int_st register.
+              14
+              1
+              read-write
+            
+            
+              RS485_PARITY_ERR_INT_ENA
+              This is the enable bit for rs485_parity_err_int_st register.
+              15
+              1
+              read-write
+            
+            
+              RS485_FRM_ERR_INT_ENA
+              This is the enable bit for rs485_parity_err_int_st register.
+              16
+              1
+              read-write
+            
+            
+              RS485_CLASH_INT_ENA
+              This is the enable bit for rs485_clash_int_st register.
+              17
+              1
+              read-write
+            
+            
+              AT_CMD_CHAR_DET_INT_ENA
+              This is the enable bit for at_cmd_char_det_int_st register.
+              18
+              1
+              read-write
+            
+            
+              WAKEUP_INT_ENA
+              This is the enable bit for uart_wakeup_int_st register.
+              19
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          Interrupt clear bits
+          0x10
+          0x20
+          
+            
+              RXFIFO_FULL_INT_CLR
+              Set this bit to clear the rxfifo_full_int_raw interrupt.
+              0
+              1
+              write-only
+            
+            
+              TXFIFO_EMPTY_INT_CLR
+              Set this bit to clear txfifo_empty_int_raw interrupt.
+              1
+              1
+              write-only
+            
+            
+              PARITY_ERR_INT_CLR
+              Set this bit to clear parity_err_int_raw interrupt.
+              2
+              1
+              write-only
+            
+            
+              FRM_ERR_INT_CLR
+              Set this bit to clear frm_err_int_raw interrupt.
+              3
+              1
+              write-only
+            
+            
+              RXFIFO_OVF_INT_CLR
+              Set this bit to clear rxfifo_ovf_int_raw interrupt.
+              4
+              1
+              write-only
+            
+            
+              DSR_CHG_INT_CLR
+              Set this bit to clear the dsr_chg_int_raw interrupt.
+              5
+              1
+              write-only
+            
+            
+              CTS_CHG_INT_CLR
+              Set this bit to clear the cts_chg_int_raw interrupt.
+              6
+              1
+              write-only
+            
+            
+              BRK_DET_INT_CLR
+              Set this bit to clear the brk_det_int_raw interrupt.
+              7
+              1
+              write-only
+            
+            
+              RXFIFO_TOUT_INT_CLR
+              Set this bit to clear the rxfifo_tout_int_raw interrupt.
+              8
+              1
+              write-only
+            
+            
+              SW_XON_INT_CLR
+              Set this bit to clear the sw_xon_int_raw interrupt.
+              9
+              1
+              write-only
+            
+            
+              SW_XOFF_INT_CLR
+              Set this bit to clear the sw_xoff_int_raw interrupt.
+              10
+              1
+              write-only
+            
+            
+              GLITCH_DET_INT_CLR
+              Set this bit to clear the glitch_det_int_raw interrupt.
+              11
+              1
+              write-only
+            
+            
+              TX_BRK_DONE_INT_CLR
+              Set this bit to clear the tx_brk_done_int_raw interrupt..
+              12
+              1
+              write-only
+            
+            
+              TX_BRK_IDLE_DONE_INT_CLR
+              Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+              13
+              1
+              write-only
+            
+            
+              TX_DONE_INT_CLR
+              Set this bit to clear the tx_done_int_raw interrupt.
+              14
+              1
+              write-only
+            
+            
+              RS485_PARITY_ERR_INT_CLR
+              Set this bit to clear the rs485_parity_err_int_raw interrupt.
+              15
+              1
+              write-only
+            
+            
+              RS485_FRM_ERR_INT_CLR
+              Set this bit to clear the rs485_frm_err_int_raw interrupt.
+              16
+              1
+              write-only
+            
+            
+              RS485_CLASH_INT_CLR
+              Set this bit to clear the rs485_clash_int_raw interrupt.
+              17
+              1
+              write-only
+            
+            
+              AT_CMD_CHAR_DET_INT_CLR
+              Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+              18
+              1
+              write-only
+            
+            
+              WAKEUP_INT_CLR
+              Set this bit to clear the uart_wakeup_int_raw interrupt.
+              19
+              1
+              write-only
+            
+          
+        
+        
+          CLKDIV
+          Clock divider configuration
+          0x14
+          0x20
+          0x000002B6
+          
+            
+              CLKDIV
+              The integral part of the frequency divider factor.
+              0
+              12
+              read-write
+            
+            
+              FRAG
+              The decimal part of the frequency divider factor.
+              20
+              4
+              read-write
+            
+          
+        
+        
+          RX_FILT
+          Rx Filter configuration
+          0x18
+          0x20
+          0x00000008
+          
+            
+              GLITCH_FILT
+              when input pulse width is lower than this value, the pulse is ignored.
+              0
+              8
+              read-write
+            
+            
+              GLITCH_FILT_EN
+              Set this bit to enable Rx signal filter.
+              8
+              1
+              read-write
+            
+          
+        
+        
+          STATUS
+          UART status register
+          0x1C
+          0x20
+          0xE000C000
+          
+            
+              RXFIFO_CNT
+              Stores the byte number of valid data in Rx-FIFO.
+              0
+              10
+              read-only
+            
+            
+              DSRN
+              The register represent the level value of the internal uart dsr signal.
+              13
+              1
+              read-only
+            
+            
+              CTSN
+              This register represent the level value of the internal uart cts signal.
+              14
+              1
+              read-only
+            
+            
+              RXD
+              This register represent the  level value of the internal uart rxd signal.
+              15
+              1
+              read-only
+            
+            
+              TXFIFO_CNT
+              Stores the byte number of data in Tx-FIFO.
+              16
+              10
+              read-only
+            
+            
+              DTRN
+              This bit represents the level of the internal uart dtr signal.
+              29
+              1
+              read-only
+            
+            
+              RTSN
+              This bit represents the level of the internal uart rts signal.
+              30
+              1
+              read-only
+            
+            
+              TXD
+              This bit represents the  level of the internal uart txd signal.
+              31
+              1
+              read-only
+            
+          
+        
+        
+          CONF0
+          a
+          0x20
+          0x20
+          0x1000001C
+          
+            
+              PARITY
+              This register is used to configure the parity check mode.
+              0
+              1
+              read-write
+            
+            
+              PARITY_EN
+              Set this bit to enable uart parity check.
+              1
+              1
+              read-write
+            
+            
+              BIT_NUM
+              This register is used to set the length of data.
+              2
+              2
+              read-write
+            
+            
+              STOP_BIT_NUM
+              This register is used to set the length of  stop bit.
+              4
+              2
+              read-write
+            
+            
+              SW_RTS
+              This register is used to configure the software rts signal which is used in software flow control.
+              6
+              1
+              read-write
+            
+            
+              SW_DTR
+              This register is used to configure the software dtr signal which is used in software flow control.
+              7
+              1
+              read-write
+            
+            
+              TXD_BRK
+              Set this bit to enbale transmitter to  send NULL when the process of sending data is done.
+              8
+              1
+              read-write
+            
+            
+              IRDA_DPLX
+              Set this bit to enable IrDA loopback mode.
+              9
+              1
+              read-write
+            
+            
+              IRDA_TX_EN
+              This is the start enable bit for IrDA transmitter.
+              10
+              1
+              read-write
+            
+            
+              IRDA_WCTL
+              1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.
+              11
+              1
+              read-write
+            
+            
+              IRDA_TX_INV
+              Set this bit to invert the level of  IrDA transmitter.
+              12
+              1
+              read-write
+            
+            
+              IRDA_RX_INV
+              Set this bit to invert the level of IrDA receiver.
+              13
+              1
+              read-write
+            
+            
+              LOOPBACK
+              Set this bit to enable uart loopback test mode.
+              14
+              1
+              read-write
+            
+            
+              TX_FLOW_EN
+              Set this bit to enable flow control function for transmitter.
+              15
+              1
+              read-write
+            
+            
+              IRDA_EN
+              Set this bit to enable IrDA protocol.
+              16
+              1
+              read-write
+            
+            
+              RXFIFO_RST
+              Set this bit to reset the uart receive-FIFO.
+              17
+              1
+              read-write
+            
+            
+              TXFIFO_RST
+              Set this bit to reset the uart transmit-FIFO.
+              18
+              1
+              read-write
+            
+            
+              RXD_INV
+              Set this bit to inverse the level value of uart rxd signal.
+              19
+              1
+              read-write
+            
+            
+              CTS_INV
+              Set this bit to inverse the level value of uart cts signal.
+              20
+              1
+              read-write
+            
+            
+              DSR_INV
+              Set this bit to inverse the level value of uart dsr signal.
+              21
+              1
+              read-write
+            
+            
+              TXD_INV
+              Set this bit to inverse the level value of uart txd signal.
+              22
+              1
+              read-write
+            
+            
+              RTS_INV
+              Set this bit to inverse the level value of uart rts signal.
+              23
+              1
+              read-write
+            
+            
+              DTR_INV
+              Set this bit to inverse the level value of uart dtr signal.
+              24
+              1
+              read-write
+            
+            
+              CLK_EN
+              1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
+              25
+              1
+              read-write
+            
+            
+              ERR_WR_MASK
+              1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.
+              26
+              1
+              read-write
+            
+            
+              AUTOBAUD_EN
+              This is the enable bit for detecting baudrate.
+              27
+              1
+              read-write
+            
+            
+              MEM_CLK_EN
+              UART memory clock gate enable signal.
+              28
+              1
+              read-write
+            
+          
+        
+        
+          CONF1
+          Configuration register 1
+          0x24
+          0x20
+          0x0000C060
+          
+            
+              RXFIFO_FULL_THRHD
+              It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.
+              0
+              9
+              read-write
+            
+            
+              TXFIFO_EMPTY_THRHD
+              It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.
+              9
+              9
+              read-write
+            
+            
+              DIS_RX_DAT_OVF
+              Disable UART Rx data overflow detect.
+              18
+              1
+              read-write
+            
+            
+              RX_TOUT_FLOW_DIS
+              Set this bit to stop accumulating idle_cnt when hardware flow control works.
+              19
+              1
+              read-write
+            
+            
+              RX_FLOW_EN
+              This is the flow enable bit for UART receiver.
+              20
+              1
+              read-write
+            
+            
+              RX_TOUT_EN
+              This is the enble bit for uart receiver's timeout function.
+              21
+              1
+              read-write
+            
+          
+        
+        
+          LOWPULSE
+          Autobaud minimum low pulse duration register
+          0x28
+          0x20
+          0x00000FFF
+          
+            
+              MIN_CNT
+              This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.
+              0
+              12
+              read-only
+            
+          
+        
+        
+          HIGHPULSE
+          Autobaud minimum high pulse duration register
+          0x2C
+          0x20
+          0x00000FFF
+          
+            
+              MIN_CNT
+              This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.
+              0
+              12
+              read-only
+            
+          
+        
+        
+          RXD_CNT
+          Autobaud edge change count register
+          0x30
+          0x20
+          
+            
+              RXD_EDGE_CNT
+              This register stores the count of rxd edge change. It is used in baud rate-detect process.
+              0
+              10
+              read-only
+            
+          
+        
+        
+          FLOW_CONF
+          Software flow-control configuration
+          0x34
+          0x20
+          
+            
+              SW_FLOW_CON_EN
+              Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.
+              0
+              1
+              read-write
+            
+            
+              XONOFF_DEL
+              Set this bit to remove flow control char from the received data.
+              1
+              1
+              read-write
+            
+            
+              FORCE_XON
+              Set this bit to enable the transmitter to go on sending data.
+              2
+              1
+              read-write
+            
+            
+              FORCE_XOFF
+              Set this bit to stop the  transmitter from sending data.
+              3
+              1
+              read-write
+            
+            
+              SEND_XON
+              Set this bit to send Xon char. It is cleared by hardware automatically.
+              4
+              1
+              read-write
+            
+            
+              SEND_XOFF
+              Set this bit to send Xoff char. It is cleared by hardware automatically.
+              5
+              1
+              read-write
+            
+          
+        
+        
+          SLEEP_CONF
+          Sleep-mode configuration
+          0x38
+          0x20
+          0x000000F0
+          
+            
+              ACTIVE_THRESHOLD
+              The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.
+              0
+              10
+              read-write
+            
+          
+        
+        
+          SWFC_CONF0
+          Software flow-control character configuration
+          0x3C
+          0x20
+          0x000026E0
+          
+            
+              XOFF_THRESHOLD
+              When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.
+              0
+              9
+              read-write
+            
+            
+              XOFF_CHAR
+              This register stores the Xoff flow control char.
+              9
+              8
+              read-write
+            
+          
+        
+        
+          SWFC_CONF1
+          Software flow-control character configuration
+          0x40
+          0x20
+          0x00002200
+          
+            
+              XON_THRESHOLD
+              When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.
+              0
+              9
+              read-write
+            
+            
+              XON_CHAR
+              This register stores the Xon flow control char.
+              9
+              8
+              read-write
+            
+          
+        
+        
+          TXBRK_CONF
+          Tx Break character configuration
+          0x44
+          0x20
+          0x0000000A
+          
+            
+              TX_BRK_NUM
+              This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.
+              0
+              8
+              read-write
+            
+          
+        
+        
+          IDLE_CONF
+          Frame-end idle configuration
+          0x48
+          0x20
+          0x00040100
+          
+            
+              RX_IDLE_THRHD
+              It will produce frame end signal when receiver takes more time to receive one byte data than this register value.
+              0
+              10
+              read-write
+            
+            
+              TX_IDLE_NUM
+              This register is used to configure the duration time between transfers.
+              10
+              10
+              read-write
+            
+          
+        
+        
+          RS485_CONF
+          RS485 mode configuration
+          0x4C
+          0x20
+          
+            
+              RS485_EN
+              Set this bit to choose the rs485 mode.
+              0
+              1
+              read-write
+            
+            
+              DL0_EN
+              Set this bit to delay the stop bit by 1 bit.
+              1
+              1
+              read-write
+            
+            
+              DL1_EN
+              Set this bit to delay the stop bit by 1 bit.
+              2
+              1
+              read-write
+            
+            
+              RS485TX_RX_EN
+              Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.
+              3
+              1
+              read-write
+            
+            
+              RS485RXBY_TX_EN
+              1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+              4
+              1
+              read-write
+            
+            
+              RS485_RX_DLY_NUM
+              This register is used to delay the receiver's internal data signal.
+              5
+              1
+              read-write
+            
+            
+              RS485_TX_DLY_NUM
+              This register is used to delay the transmitter's internal data signal.
+              6
+              4
+              read-write
+            
+          
+        
+        
+          AT_CMD_PRECNT
+          Pre-sequence timing configuration
+          0x50
+          0x20
+          0x00000901
+          
+            
+              PRE_IDLE_NUM
+              This register is used to configure the idle duration time before the first at_cmd is received by receiver.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          AT_CMD_POSTCNT
+          Post-sequence timing configuration
+          0x54
+          0x20
+          0x00000901
+          
+            
+              POST_IDLE_NUM
+              This register is used to configure the duration time between the last at_cmd and the next data.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          AT_CMD_GAPTOUT
+          Timeout configuration
+          0x58
+          0x20
+          0x0000000B
+          
+            
+              RX_GAP_TOUT
+              This register is used to configure the duration time between the at_cmd chars.
+              0
+              16
+              read-write
+            
+          
+        
+        
+          AT_CMD_CHAR
+          AT escape sequence detection configuration
+          0x5C
+          0x20
+          0x0000032B
+          
+            
+              AT_CMD_CHAR
+              This register is used to configure the content of at_cmd char.
+              0
+              8
+              read-write
+            
+            
+              CHAR_NUM
+              This register is used to configure the num of continuous at_cmd chars received by receiver.
+              8
+              8
+              read-write
+            
+          
+        
+        
+          MEM_CONF
+          UART threshold and allocation configuration
+          0x60
+          0x20
+          0x000A0012
+          
+            
+              RX_SIZE
+              This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.
+              1
+              3
+              read-write
+            
+            
+              TX_SIZE
+              This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.
+              4
+              3
+              read-write
+            
+            
+              RX_FLOW_THRHD
+              This register is used to configure the maximum amount of data that can be received  when hardware flow control works.
+              7
+              9
+              read-write
+            
+            
+              RX_TOUT_THRHD
+              This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.
+              16
+              10
+              read-write
+            
+            
+              MEM_FORCE_PD
+              Set this bit to force power down UART memory.
+              26
+              1
+              read-write
+            
+            
+              MEM_FORCE_PU
+              Set this bit to force power up UART memory.
+              27
+              1
+              read-write
+            
+          
+        
+        
+          MEM_TX_STATUS
+          Tx-FIFO write and read offset address.
+          0x64
+          0x20
+          
+            
+              APB_TX_WADDR
+              This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.
+              0
+              10
+              read-only
+            
+            
+              TX_RADDR
+              This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.
+              11
+              10
+              read-only
+            
+          
+        
+        
+          MEM_RX_STATUS
+          Rx-FIFO write and read offset address.
+          0x68
+          0x20
+          0x00080100
+          
+            
+              APB_RX_RADDR
+              This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
+              0
+              10
+              read-only
+            
+            
+              RX_WADDR
+              This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
+              11
+              10
+              read-only
+            
+          
+        
+        
+          FSM_STATUS
+          UART transmit and receive status.
+          0x6C
+          0x20
+          
+            
+              ST_URX_OUT
+              This is the status register of receiver.
+              0
+              4
+              read-only
+            
+            
+              ST_UTX_OUT
+              This is the status register of transmitter.
+              4
+              4
+              read-only
+            
+          
+        
+        
+          POSPULSE
+          Autobaud high pulse register
+          0x70
+          0x20
+          0x00000FFF
+          
+            
+              POSEDGE_MIN_CNT
+              This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.
+              0
+              12
+              read-only
+            
+          
+        
+        
+          NEGPULSE
+          Autobaud low pulse register
+          0x74
+          0x20
+          0x00000FFF
+          
+            
+              NEGEDGE_MIN_CNT
+              This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.
+              0
+              12
+              read-only
+            
+          
+        
+        
+          CLK_CONF
+          UART core clock configuration
+          0x78
+          0x20
+          0x03701000
+          
+            
+              SCLK_DIV_B
+              The  denominator of the frequency divider factor.
+              0
+              6
+              read-write
+            
+            
+              SCLK_DIV_A
+              The numerator of the frequency divider factor.
+              6
+              6
+              read-write
+            
+            
+              SCLK_DIV_NUM
+              The integral part of the frequency divider factor.
+              12
+              8
+              read-write
+            
+            
+              SCLK_SEL
+              UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+              20
+              2
+              read-write
+            
+            
+              SCLK_EN
+              Set this bit to enable UART Tx/Rx clock.
+              22
+              1
+              read-write
+            
+            
+              RST_CORE
+              Write 1 then write 0 to this bit, reset UART Tx/Rx.
+              23
+              1
+              read-write
+            
+            
+              TX_SCLK_EN
+              Set this bit to enable UART Tx clock.
+              24
+              1
+              read-write
+            
+            
+              RX_SCLK_EN
+              Set this bit to enable UART Rx clock.
+              25
+              1
+              read-write
+            
+            
+              TX_RST_CORE
+              Write 1 then write 0 to this bit, reset UART Tx.
+              26
+              1
+              read-write
+            
+            
+              RX_RST_CORE
+              Write 1 then write 0 to this bit, reset UART Rx.
+              27
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          UART Version register
+          0x7C
+          0x20
+          0x02008270
+          
+            
+              DATE
+              This is the version register.
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ID
+          UART ID register
+          0x80
+          0x20
+          0x40000500
+          
+            
+              ID
+              This register is used to configure the uart_id.
+              0
+              30
+              read-write
+            
+            
+              HIGH_SPEED
+              This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.
+              30
+              1
+              read-write
+            
+            
+              REG_UPDATE
+              Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.
+              31
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      UART1
+      UART (Universal Asynchronous Receiver-Transmitter) Controller
+      0x60010000
+      
+        UART1
+        22
+      
+    
+    
+      UHCI0
+      Universal Host Controller Interface
+      UHCI
+      0x60014000
+      
+        0x0
+        0x84
+        registers
+      
+      
+        UHCI0
+        15
+      
+      
+        
+          CONF0
+          a
+          0x0
+          0x20
+          0x000006E0
+          
+            
+              TX_RST
+              Write 1, then write 0 to this bit to reset decode state machine.
+              0
+              1
+              read-write
+            
+            
+              RX_RST
+              Write 1, then write 0 to this bit to reset encode state machine.
+              1
+              1
+              read-write
+            
+            
+              UART0_CE
+              Set this bit to link up HCI and UART0.
+              2
+              1
+              read-write
+            
+            
+              UART1_CE
+              Set this bit to link up HCI and UART1.
+              3
+              1
+              read-write
+            
+            
+              SEPER_EN
+              Set this bit to separate the data frame using a special char.
+              5
+              1
+              read-write
+            
+            
+              HEAD_EN
+              Set this bit to encode the data packet with a formatting header.
+              6
+              1
+              read-write
+            
+            
+              CRC_REC_EN
+              Set this bit to enable UHCI to receive the 16 bit CRC.
+              7
+              1
+              read-write
+            
+            
+              UART_IDLE_EOF_EN
+              If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.
+              8
+              1
+              read-write
+            
+            
+              LEN_EOF_EN
+              If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.
+              9
+              1
+              read-write
+            
+            
+              ENCODE_CRC_EN
+              Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.
+              10
+              1
+              read-write
+            
+            
+              CLK_EN
+              1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.
+              11
+              1
+              read-write
+            
+            
+              UART_RX_BRK_EOF_EN
+              If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.
+              12
+              1
+              read-write
+            
+          
+        
+        
+          INT_RAW
+          a
+          0x4
+          0x20
+          
+            
+              RX_START_INT_RAW
+              a
+              0
+              1
+              read-only
+            
+            
+              TX_START_INT_RAW
+              a
+              1
+              1
+              read-only
+            
+            
+              RX_HUNG_INT_RAW
+              a
+              2
+              1
+              read-only
+            
+            
+              TX_HUNG_INT_RAW
+              a
+              3
+              1
+              read-only
+            
+            
+              SEND_S_REG_Q_INT_RAW
+              a
+              4
+              1
+              read-only
+            
+            
+              SEND_A_REG_Q_INT_RAW
+              a
+              5
+              1
+              read-only
+            
+            
+              OUT_EOF_INT_RAW
+              This is the interrupt raw bit. Triggered when there are some errors in EOF in the
+              6
+              1
+              read-only
+            
+            
+              APP_CTRL0_INT_RAW
+              Soft control int raw bit.
+              7
+              1
+              read-write
+            
+            
+              APP_CTRL1_INT_RAW
+              Soft control int raw bit.
+              8
+              1
+              read-write
+            
+          
+        
+        
+          INT_ST
+          a
+          0x8
+          0x20
+          
+            
+              RX_START_INT_ST
+              a
+              0
+              1
+              read-only
+            
+            
+              TX_START_INT_ST
+              a
+              1
+              1
+              read-only
+            
+            
+              RX_HUNG_INT_ST
+              a
+              2
+              1
+              read-only
+            
+            
+              TX_HUNG_INT_ST
+              a
+              3
+              1
+              read-only
+            
+            
+              SEND_S_REG_Q_INT_ST
+              a
+              4
+              1
+              read-only
+            
+            
+              SEND_A_REG_Q_INT_ST
+              a
+              5
+              1
+              read-only
+            
+            
+              OUTLINK_EOF_ERR_INT_ST
+              a
+              6
+              1
+              read-only
+            
+            
+              APP_CTRL0_INT_ST
+              a
+              7
+              1
+              read-only
+            
+            
+              APP_CTRL1_INT_ST
+              a
+              8
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          a
+          0xC
+          0x20
+          
+            
+              RX_START_INT_ENA
+              a
+              0
+              1
+              read-write
+            
+            
+              TX_START_INT_ENA
+              a
+              1
+              1
+              read-write
+            
+            
+              RX_HUNG_INT_ENA
+              a
+              2
+              1
+              read-write
+            
+            
+              TX_HUNG_INT_ENA
+              a
+              3
+              1
+              read-write
+            
+            
+              SEND_S_REG_Q_INT_ENA
+              a
+              4
+              1
+              read-write
+            
+            
+              SEND_A_REG_Q_INT_ENA
+              a
+              5
+              1
+              read-write
+            
+            
+              OUTLINK_EOF_ERR_INT_ENA
+              a
+              6
+              1
+              read-write
+            
+            
+              APP_CTRL0_INT_ENA
+              a
+              7
+              1
+              read-write
+            
+            
+              APP_CTRL1_INT_ENA
+              a
+              8
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          a
+          0x10
+          0x20
+          
+            
+              RX_START_INT_CLR
+              a
+              0
+              1
+              write-only
+            
+            
+              TX_START_INT_CLR
+              a
+              1
+              1
+              write-only
+            
+            
+              RX_HUNG_INT_CLR
+              a
+              2
+              1
+              write-only
+            
+            
+              TX_HUNG_INT_CLR
+              a
+              3
+              1
+              write-only
+            
+            
+              SEND_S_REG_Q_INT_CLR
+              a
+              4
+              1
+              write-only
+            
+            
+              SEND_A_REG_Q_INT_CLR
+              a
+              5
+              1
+              write-only
+            
+            
+              OUTLINK_EOF_ERR_INT_CLR
+              a
+              6
+              1
+              write-only
+            
+            
+              APP_CTRL0_INT_CLR
+              a
+              7
+              1
+              write-only
+            
+            
+              APP_CTRL1_INT_CLR
+              a
+              8
+              1
+              write-only
+            
+          
+        
+        
+          CONF1
+          a
+          0x14
+          0x20
+          0x00000033
+          
+            
+              CHECK_SUM_EN
+              a
+              0
+              1
+              read-write
+            
+            
+              CHECK_SEQ_EN
+              a
+              1
+              1
+              read-write
+            
+            
+              CRC_DISABLE
+              a
+              2
+              1
+              read-write
+            
+            
+              SAVE_HEAD
+              a
+              3
+              1
+              read-write
+            
+            
+              TX_CHECK_SUM_RE
+              a
+              4
+              1
+              read-write
+            
+            
+              TX_ACK_NUM_RE
+              a
+              5
+              1
+              read-write
+            
+            
+              WAIT_SW_START
+              a
+              7
+              1
+              read-write
+            
+            
+              SW_START
+              a
+              8
+              1
+              read-write
+            
+          
+        
+        
+          STATE0
+          a
+          0x18
+          0x20
+          
+            
+              RX_ERR_CAUSE
+              a
+              0
+              3
+              read-only
+            
+            
+              DECODE_STATE
+              a
+              3
+              3
+              read-only
+            
+          
+        
+        
+          STATE1
+          a
+          0x1C
+          0x20
+          
+            
+              ENCODE_STATE
+              a
+              0
+              3
+              read-only
+            
+          
+        
+        
+          ESCAPE_CONF
+          a
+          0x20
+          0x20
+          0x00000033
+          
+            
+              TX_C0_ESC_EN
+              a
+              0
+              1
+              read-write
+            
+            
+              TX_DB_ESC_EN
+              a
+              1
+              1
+              read-write
+            
+            
+              TX_11_ESC_EN
+              a
+              2
+              1
+              read-write
+            
+            
+              TX_13_ESC_EN
+              a
+              3
+              1
+              read-write
+            
+            
+              RX_C0_ESC_EN
+              a
+              4
+              1
+              read-write
+            
+            
+              RX_DB_ESC_EN
+              a
+              5
+              1
+              read-write
+            
+            
+              RX_11_ESC_EN
+              a
+              6
+              1
+              read-write
+            
+            
+              RX_13_ESC_EN
+              a
+              7
+              1
+              read-write
+            
+          
+        
+        
+          HUNG_CONF
+          a
+          0x24
+          0x20
+          0x00810810
+          
+            
+              TXFIFO_TIMEOUT
+              a
+              0
+              8
+              read-write
+            
+            
+              TXFIFO_TIMEOUT_SHIFT
+              a
+              8
+              3
+              read-write
+            
+            
+              TXFIFO_TIMEOUT_ENA
+              a
+              11
+              1
+              read-write
+            
+            
+              RXFIFO_TIMEOUT
+              a
+              12
+              8
+              read-write
+            
+            
+              RXFIFO_TIMEOUT_SHIFT
+              a
+              20
+              3
+              read-write
+            
+            
+              RXFIFO_TIMEOUT_ENA
+              a
+              23
+              1
+              read-write
+            
+          
+        
+        
+          ACK_NUM
+          a
+          0x28
+          0x20
+          0x00000008
+          
+            
+              ACK_NUM
+              a
+              0
+              3
+              read-write
+            
+            
+              LOAD
+              a
+              3
+              1
+              write-only
+            
+          
+        
+        
+          RX_HEAD
+          a
+          0x2C
+          0x20
+          
+            
+              RX_HEAD
+              a
+              0
+              32
+              read-only
+            
+          
+        
+        
+          QUICK_SENT
+          a
+          0x30
+          0x20
+          
+            
+              SINGLE_SEND_NUM
+              a
+              0
+              3
+              read-write
+            
+            
+              SINGLE_SEND_EN
+              a
+              3
+              1
+              read-write
+            
+            
+              ALWAYS_SEND_NUM
+              a
+              4
+              3
+              read-write
+            
+            
+              ALWAYS_SEND_EN
+              a
+              7
+              1
+              read-write
+            
+          
+        
+        
+          REG_Q0_WORD0
+          a
+          0x34
+          0x20
+          
+            
+              SEND_Q0_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q0_WORD1
+          a
+          0x38
+          0x20
+          
+            
+              SEND_Q0_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q1_WORD0
+          a
+          0x3C
+          0x20
+          
+            
+              SEND_Q1_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q1_WORD1
+          a
+          0x40
+          0x20
+          
+            
+              SEND_Q1_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q2_WORD0
+          a
+          0x44
+          0x20
+          
+            
+              SEND_Q2_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q2_WORD1
+          a
+          0x48
+          0x20
+          
+            
+              SEND_Q2_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q3_WORD0
+          a
+          0x4C
+          0x20
+          
+            
+              SEND_Q3_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q3_WORD1
+          a
+          0x50
+          0x20
+          
+            
+              SEND_Q3_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q4_WORD0
+          a
+          0x54
+          0x20
+          
+            
+              SEND_Q4_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q4_WORD1
+          a
+          0x58
+          0x20
+          
+            
+              SEND_Q4_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q5_WORD0
+          a
+          0x5C
+          0x20
+          
+            
+              SEND_Q5_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q5_WORD1
+          a
+          0x60
+          0x20
+          
+            
+              SEND_Q5_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q6_WORD0
+          a
+          0x64
+          0x20
+          
+            
+              SEND_Q6_WORD0
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          REG_Q6_WORD1
+          a
+          0x68
+          0x20
+          
+            
+              SEND_Q6_WORD1
+              a
+              0
+              32
+              read-write
+            
+          
+        
+        
+          ESC_CONF0
+          a
+          0x6C
+          0x20
+          0x00DCDBC0
+          
+            
+              SEPER_CHAR
+              a
+              0
+              8
+              read-write
+            
+            
+              SEPER_ESC_CHAR0
+              a
+              8
+              8
+              read-write
+            
+            
+              SEPER_ESC_CHAR1
+              a
+              16
+              8
+              read-write
+            
+          
+        
+        
+          ESC_CONF1
+          a
+          0x70
+          0x20
+          0x00DDDBDB
+          
+            
+              ESC_SEQ0
+              a
+              0
+              8
+              read-write
+            
+            
+              ESC_SEQ0_CHAR0
+              a
+              8
+              8
+              read-write
+            
+            
+              ESC_SEQ0_CHAR1
+              a
+              16
+              8
+              read-write
+            
+          
+        
+        
+          ESC_CONF2
+          a
+          0x74
+          0x20
+          0x00DEDB11
+          
+            
+              ESC_SEQ1
+              a
+              0
+              8
+              read-write
+            
+            
+              ESC_SEQ1_CHAR0
+              a
+              8
+              8
+              read-write
+            
+            
+              ESC_SEQ1_CHAR1
+              a
+              16
+              8
+              read-write
+            
+          
+        
+        
+          ESC_CONF3
+          a
+          0x78
+          0x20
+          0x00DFDB13
+          
+            
+              ESC_SEQ2
+              a
+              0
+              8
+              read-write
+            
+            
+              ESC_SEQ2_CHAR0
+              a
+              8
+              8
+              read-write
+            
+            
+              ESC_SEQ2_CHAR1
+              a
+              16
+              8
+              read-write
+            
+          
+        
+        
+          PKT_THRES
+          a
+          0x7C
+          0x20
+          0x00000080
+          
+            
+              PKT_THRS
+              a
+              0
+              13
+              read-write
+            
+          
+        
+        
+          DATE
+          a
+          0x80
+          0x20
+          0x02007170
+          
+            
+              DATE
+              a
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      UHCI1
+      Universal Host Controller Interface
+      0x6000C000
+    
+    
+      USB_DEVICE
+      Full-speed USB Serial/JTAG Controller
+      USB_DEVICE
+      0x60043000
+      
+        0x0
+        0x50
+        registers
+      
+      
+        USB_SERIAL_JTAG
+        26
+      
+      
+        
+          EP1
+          USB_DEVICE_EP1_REG.
+          0x0
+          0x20
+          
+            
+              RDWR_BYTE
+              Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.
+              0
+              8
+              read-write
+            
+          
+        
+        
+          EP1_CONF
+          USB_DEVICE_EP1_CONF_REG.
+          0x4
+          0x20
+          0x00000002
+          
+            
+              WR_DONE
+              Set this bit to indicate writing byte data to UART Tx FIFO is done.
+              0
+              1
+              write-only
+            
+            
+              SERIAL_IN_EP_DATA_FREE
+              1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.
+              1
+              1
+              read-only
+            
+            
+              SERIAL_OUT_EP_DATA_AVAIL
+              1'b1: Indicate there is data in UART Rx FIFO.
+              2
+              1
+              read-only
+            
+          
+        
+        
+          INT_RAW
+          USB_DEVICE_INT_RAW_REG.
+          0x8
+          0x20
+          0x00000008
+          
+            
+              JTAG_IN_FLUSH_INT_RAW
+              The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.
+              0
+              1
+              read-only
+            
+            
+              SOF_INT_RAW
+              The raw interrupt bit turns to high level when SOF frame is received.
+              1
+              1
+              read-only
+            
+            
+              SERIAL_OUT_RECV_PKT_INT_RAW
+              The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.
+              2
+              1
+              read-only
+            
+            
+              SERIAL_IN_EMPTY_INT_RAW
+              The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+              3
+              1
+              read-only
+            
+            
+              PID_ERR_INT_RAW
+              The raw interrupt bit turns to high level when pid error is detected.
+              4
+              1
+              read-only
+            
+            
+              CRC5_ERR_INT_RAW
+              The raw interrupt bit turns to high level when CRC5 error is detected.
+              5
+              1
+              read-only
+            
+            
+              CRC16_ERR_INT_RAW
+              The raw interrupt bit turns to high level when CRC16 error is detected.
+              6
+              1
+              read-only
+            
+            
+              STUFF_ERR_INT_RAW
+              The raw interrupt bit turns to high level when stuff error is detected.
+              7
+              1
+              read-only
+            
+            
+              IN_TOKEN_REC_IN_EP1_INT_RAW
+              The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.
+              8
+              1
+              read-only
+            
+            
+              USB_BUS_RESET_INT_RAW
+              The raw interrupt bit turns to high level when usb bus reset is detected.
+              9
+              1
+              read-only
+            
+            
+              OUT_EP1_ZERO_PAYLOAD_INT_RAW
+              The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.
+              10
+              1
+              read-only
+            
+            
+              OUT_EP2_ZERO_PAYLOAD_INT_RAW
+              The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.
+              11
+              1
+              read-only
+            
+          
+        
+        
+          INT_ST
+          USB_DEVICE_INT_ST_REG.
+          0xC
+          0x20
+          
+            
+              JTAG_IN_FLUSH_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+              0
+              1
+              read-only
+            
+            
+              SOF_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+              1
+              1
+              read-only
+            
+            
+              SERIAL_OUT_RECV_PKT_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+              2
+              1
+              read-only
+            
+            
+              SERIAL_IN_EMPTY_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+              3
+              1
+              read-only
+            
+            
+              PID_ERR_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+              4
+              1
+              read-only
+            
+            
+              CRC5_ERR_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+              5
+              1
+              read-only
+            
+            
+              CRC16_ERR_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+              6
+              1
+              read-only
+            
+            
+              STUFF_ERR_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+              7
+              1
+              read-only
+            
+            
+              IN_TOKEN_REC_IN_EP1_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+              8
+              1
+              read-only
+            
+            
+              USB_BUS_RESET_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+              9
+              1
+              read-only
+            
+            
+              OUT_EP1_ZERO_PAYLOAD_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+              10
+              1
+              read-only
+            
+            
+              OUT_EP2_ZERO_PAYLOAD_INT_ST
+              The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+              11
+              1
+              read-only
+            
+          
+        
+        
+          INT_ENA
+          USB_DEVICE_INT_ENA_REG.
+          0x10
+          0x20
+          
+            
+              JTAG_IN_FLUSH_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+              0
+              1
+              read-write
+            
+            
+              SOF_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+              1
+              1
+              read-write
+            
+            
+              SERIAL_OUT_RECV_PKT_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+              2
+              1
+              read-write
+            
+            
+              SERIAL_IN_EMPTY_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+              3
+              1
+              read-write
+            
+            
+              PID_ERR_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+              4
+              1
+              read-write
+            
+            
+              CRC5_ERR_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+              5
+              1
+              read-write
+            
+            
+              CRC16_ERR_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+              6
+              1
+              read-write
+            
+            
+              STUFF_ERR_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+              7
+              1
+              read-write
+            
+            
+              IN_TOKEN_REC_IN_EP1_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+              8
+              1
+              read-write
+            
+            
+              USB_BUS_RESET_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+              9
+              1
+              read-write
+            
+            
+              OUT_EP1_ZERO_PAYLOAD_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+              10
+              1
+              read-write
+            
+            
+              OUT_EP2_ZERO_PAYLOAD_INT_ENA
+              The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+              11
+              1
+              read-write
+            
+          
+        
+        
+          INT_CLR
+          USB_DEVICE_INT_CLR_REG.
+          0x14
+          0x20
+          
+            
+              JTAG_IN_FLUSH_INT_CLR
+              Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+              0
+              1
+              write-only
+            
+            
+              SOF_INT_CLR
+              Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+              1
+              1
+              write-only
+            
+            
+              SERIAL_OUT_RECV_PKT_INT_CLR
+              Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+              2
+              1
+              write-only
+            
+            
+              SERIAL_IN_EMPTY_INT_CLR
+              Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+              3
+              1
+              write-only
+            
+            
+              PID_ERR_INT_CLR
+              Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+              4
+              1
+              write-only
+            
+            
+              CRC5_ERR_INT_CLR
+              Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+              5
+              1
+              write-only
+            
+            
+              CRC16_ERR_INT_CLR
+              Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+              6
+              1
+              write-only
+            
+            
+              STUFF_ERR_INT_CLR
+              Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+              7
+              1
+              write-only
+            
+            
+              IN_TOKEN_REC_IN_EP1_INT_CLR
+              Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+              8
+              1
+              write-only
+            
+            
+              USB_BUS_RESET_INT_CLR
+              Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+              9
+              1
+              write-only
+            
+            
+              OUT_EP1_ZERO_PAYLOAD_INT_CLR
+              Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+              10
+              1
+              write-only
+            
+            
+              OUT_EP2_ZERO_PAYLOAD_INT_CLR
+              Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+              11
+              1
+              write-only
+            
+          
+        
+        
+          CONF0
+          USB_DEVICE_CONF0_REG.
+          0x18
+          0x20
+          0x00004200
+          
+            
+              PHY_SEL
+              Select internal/external PHY
+              0
+              1
+              read-write
+            
+            
+              EXCHG_PINS_OVERRIDE
+              Enable software control USB D+ D- exchange
+              1
+              1
+              read-write
+            
+            
+              EXCHG_PINS
+              USB D+ D- exchange
+              2
+              1
+              read-write
+            
+            
+              VREFH
+              Control single-end input high threshold,1.76V to 2V, step 80mV
+              3
+              2
+              read-write
+            
+            
+              VREFL
+              Control single-end input low threshold,0.8V to 1.04V, step 80mV
+              5
+              2
+              read-write
+            
+            
+              VREF_OVERRIDE
+              Enable software control input  threshold
+              7
+              1
+              read-write
+            
+            
+              PAD_PULL_OVERRIDE
+              Enable software control USB D+ D- pullup pulldown
+              8
+              1
+              read-write
+            
+            
+              DP_PULLUP
+              Control USB D+ pull up.
+              9
+              1
+              read-write
+            
+            
+              DP_PULLDOWN
+              Control USB D+ pull down.
+              10
+              1
+              read-write
+            
+            
+              DM_PULLUP
+              Control USB D- pull up.
+              11
+              1
+              read-write
+            
+            
+              DM_PULLDOWN
+              Control USB D- pull down.
+              12
+              1
+              read-write
+            
+            
+              PULLUP_VALUE
+              Control pull up value.
+              13
+              1
+              read-write
+            
+            
+              USB_PAD_ENABLE
+              Enable USB pad function.
+              14
+              1
+              read-write
+            
+          
+        
+        
+          TEST
+          USB_DEVICE_TEST_REG.
+          0x1C
+          0x20
+          
+            
+              ENABLE
+              Enable test of the USB pad
+              0
+              1
+              read-write
+            
+            
+              USB_OE
+              USB pad oen in test
+              1
+              1
+              read-write
+            
+            
+              TX_DP
+              USB D+ tx value in test
+              2
+              1
+              read-write
+            
+            
+              TX_DM
+              USB D- tx value in test
+              3
+              1
+              read-write
+            
+          
+        
+        
+          JFIFO_ST
+          USB_DEVICE_JFIFO_ST_REG.
+          0x20
+          0x20
+          0x00000044
+          
+            
+              IN_FIFO_CNT
+              JTAT in fifo counter.
+              0
+              2
+              read-only
+            
+            
+              IN_FIFO_EMPTY
+              1: JTAG in fifo is empty.
+              2
+              1
+              read-only
+            
+            
+              IN_FIFO_FULL
+              1: JTAG in fifo is full.
+              3
+              1
+              read-only
+            
+            
+              OUT_FIFO_CNT
+              JTAT out fifo counter.
+              4
+              2
+              read-only
+            
+            
+              OUT_FIFO_EMPTY
+              1: JTAG out fifo is empty.
+              6
+              1
+              read-only
+            
+            
+              OUT_FIFO_FULL
+              1: JTAG out fifo is full.
+              7
+              1
+              read-only
+            
+            
+              IN_FIFO_RESET
+              Write 1 to reset JTAG in fifo.
+              8
+              1
+              read-write
+            
+            
+              OUT_FIFO_RESET
+              Write 1 to reset JTAG out fifo.
+              9
+              1
+              read-write
+            
+          
+        
+        
+          FRAM_NUM
+          USB_DEVICE_FRAM_NUM_REG.
+          0x24
+          0x20
+          
+            
+              SOF_FRAME_INDEX
+              Frame index of received SOF frame.
+              0
+              11
+              read-only
+            
+          
+        
+        
+          IN_EP0_ST
+          USB_DEVICE_IN_EP0_ST_REG.
+          0x28
+          0x20
+          0x00000001
+          
+            
+              IN_EP0_STATE
+              State of IN Endpoint 0.
+              0
+              2
+              read-only
+            
+            
+              IN_EP0_WR_ADDR
+              Write data address of IN endpoint 0.
+              2
+              7
+              read-only
+            
+            
+              IN_EP0_RD_ADDR
+              Read data address of IN endpoint 0.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          IN_EP1_ST
+          USB_DEVICE_IN_EP1_ST_REG.
+          0x2C
+          0x20
+          0x00000001
+          
+            
+              IN_EP1_STATE
+              State of IN Endpoint 1.
+              0
+              2
+              read-only
+            
+            
+              IN_EP1_WR_ADDR
+              Write data address of IN endpoint 1.
+              2
+              7
+              read-only
+            
+            
+              IN_EP1_RD_ADDR
+              Read data address of IN endpoint 1.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          IN_EP2_ST
+          USB_DEVICE_IN_EP2_ST_REG.
+          0x30
+          0x20
+          0x00000001
+          
+            
+              IN_EP2_STATE
+              State of IN Endpoint 2.
+              0
+              2
+              read-only
+            
+            
+              IN_EP2_WR_ADDR
+              Write data address of IN endpoint 2.
+              2
+              7
+              read-only
+            
+            
+              IN_EP2_RD_ADDR
+              Read data address of IN endpoint 2.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          IN_EP3_ST
+          USB_DEVICE_IN_EP3_ST_REG.
+          0x34
+          0x20
+          0x00000001
+          
+            
+              IN_EP3_STATE
+              State of IN Endpoint 3.
+              0
+              2
+              read-only
+            
+            
+              IN_EP3_WR_ADDR
+              Write data address of IN endpoint 3.
+              2
+              7
+              read-only
+            
+            
+              IN_EP3_RD_ADDR
+              Read data address of IN endpoint 3.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          OUT_EP0_ST
+          USB_DEVICE_OUT_EP0_ST_REG.
+          0x38
+          0x20
+          
+            
+              OUT_EP0_STATE
+              State of OUT Endpoint 0.
+              0
+              2
+              read-only
+            
+            
+              OUT_EP0_WR_ADDR
+              Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+              2
+              7
+              read-only
+            
+            
+              OUT_EP0_RD_ADDR
+              Read data address of OUT endpoint 0.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          OUT_EP1_ST
+          USB_DEVICE_OUT_EP1_ST_REG.
+          0x3C
+          0x20
+          
+            
+              OUT_EP1_STATE
+              State of OUT Endpoint 1.
+              0
+              2
+              read-only
+            
+            
+              OUT_EP1_WR_ADDR
+              Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+              2
+              7
+              read-only
+            
+            
+              OUT_EP1_RD_ADDR
+              Read data address of OUT endpoint 1.
+              9
+              7
+              read-only
+            
+            
+              OUT_EP1_REC_DATA_CNT
+              Data count in OUT endpoint 1 when one packet is received.
+              16
+              7
+              read-only
+            
+          
+        
+        
+          OUT_EP2_ST
+          USB_DEVICE_OUT_EP2_ST_REG.
+          0x40
+          0x20
+          
+            
+              OUT_EP2_STATE
+              State of OUT Endpoint 2.
+              0
+              2
+              read-only
+            
+            
+              OUT_EP2_WR_ADDR
+              Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+              2
+              7
+              read-only
+            
+            
+              OUT_EP2_RD_ADDR
+              Read data address of OUT endpoint 2.
+              9
+              7
+              read-only
+            
+          
+        
+        
+          MISC_CONF
+          USB_DEVICE_MISC_CONF_REG.
+          0x44
+          0x20
+          
+            
+              CLK_EN
+              1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          MEM_CONF
+          USB_DEVICE_MEM_CONF_REG.
+          0x48
+          0x20
+          0x00000002
+          
+            
+              USB_MEM_PD
+              1: power down usb memory.
+              0
+              1
+              read-write
+            
+            
+              USB_MEM_CLK_EN
+              1: Force clock on for usb memory.
+              1
+              1
+              read-write
+            
+          
+        
+        
+          DATE
+          USB_DEVICE_DATE_REG.
+          0x80
+          0x20
+          0x02007300
+          
+            
+              DATE
+              register version.
+              0
+              32
+              read-write
+            
+          
+        
+      
+    
+    
+      XTS_AES
+      XTS-AES-128 Flash Encryption
+      XTS_AES
+      0x600CC000
+      
+        0x0
+        0x30
+        registers
+      
+      
+        
+          16
+          0x1
+          PLAIN_MEM[%s]
+          The memory that stores plaintext
+          0x0
+          0x8
+        
+        
+          LINESIZE
+          XTS-AES line-size register
+          0x40
+          0x20
+          
+            
+              LINESIZE
+              This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          DESTINATION
+          XTS-AES destination register
+          0x44
+          0x20
+          
+            
+              DESTINATION
+              This bit stores the destination. 0: flash(default). 1: reserved.
+              0
+              1
+              read-write
+            
+          
+        
+        
+          PHYSICAL_ADDRESS
+          XTS-AES physical address register
+          0x48
+          0x20
+          
+            
+              PHYSICAL_ADDRESS
+              Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.
+              0
+              30
+              read-write
+            
+          
+        
+        
+          TRIGGER
+          XTS-AES trigger register
+          0x4C
+          0x20
+          
+            
+              TRIGGER
+              Set this bit to start manual encryption calculation
+              0
+              1
+              write-only
+            
+          
+        
+        
+          RELEASE
+          XTS-AES release register
+          0x50
+          0x20
+          
+            
+              RELEASE
+              Set this bit to release the manual encrypted result, after that the result will be visible to spi
+              0
+              1
+              write-only
+            
+          
+        
+        
+          DESTROY
+          XTS-AES destroy register
+          0x54
+          0x20
+          
+            
+              DESTROY
+              Set this bit to destroy XTS-AES result.
+              0
+              1
+              write-only
+            
+          
+        
+        
+          STATE
+          XTS-AES status register
+          0x58
+          0x20
+          
+            
+              STATE
+              Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.
+              0
+              2
+              read-only
+            
+          
+        
+        
+          DATE
+          XTS-AES version control register
+          0x5C
+          0x20
+          0x20200623
+          
+            
+              DATE
+              Those bits stores the version information of XTS-AES.
+              0
+              30
+              read-write
+            
+          
+        
+      
+    
+  
+
\ No newline at end of file
diff --git a/src/esp32c3.zig b/src/esp32c3.zig
new file mode 100644
index 000000000..77bed3f3d
--- /dev/null
+++ b/src/esp32c3.zig
@@ -0,0 +1,37956 @@
+// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz
+// commit: 62e33d0e2175e4c1621e1dbf9f6ac3ec18f6ba38
+//
+// vendor: ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.
+// device: ESP32-C3
+// cpu: RV32IMC
+
+pub const registers = struct {
+    /// AES (Advanced Encryption Standard) Accelerator
+    pub const AES = struct {
+        pub const base_address = 0x6003a000;
+
+        /// address: 0x6003a000
+        /// Key material key_0 configure register
+        pub const KEY_0 = @intToPtr(*volatile u32, base_address + 0x0);
+
+        /// address: 0x6003a004
+        /// Key material key_1 configure register
+        pub const KEY_1 = @intToPtr(*volatile u32, base_address + 0x4);
+
+        /// address: 0x6003a008
+        /// Key material key_2 configure register
+        pub const KEY_2 = @intToPtr(*volatile u32, base_address + 0x8);
+
+        /// address: 0x6003a00c
+        /// Key material key_3 configure register
+        pub const KEY_3 = @intToPtr(*volatile u32, base_address + 0xc);
+
+        /// address: 0x6003a010
+        /// Key material key_4 configure register
+        pub const KEY_4 = @intToPtr(*volatile u32, base_address + 0x10);
+
+        /// address: 0x6003a014
+        /// Key material key_5 configure register
+        pub const KEY_5 = @intToPtr(*volatile u32, base_address + 0x14);
+
+        /// address: 0x6003a018
+        /// Key material key_6 configure register
+        pub const KEY_6 = @intToPtr(*volatile u32, base_address + 0x18);
+
+        /// address: 0x6003a01c
+        /// Key material key_7 configure register
+        pub const KEY_7 = @intToPtr(*volatile u32, base_address + 0x1c);
+
+        /// address: 0x6003a020
+        /// source text material text_in_0 configure register
+        pub const TEXT_IN_0 = @intToPtr(*volatile u32, base_address + 0x20);
+
+        /// address: 0x6003a024
+        /// source text material text_in_1 configure register
+        pub const TEXT_IN_1 = @intToPtr(*volatile u32, base_address + 0x24);
+
+        /// address: 0x6003a028
+        /// source text material text_in_2 configure register
+        pub const TEXT_IN_2 = @intToPtr(*volatile u32, base_address + 0x28);
+
+        /// address: 0x6003a02c
+        /// source text material text_in_3 configure register
+        pub const TEXT_IN_3 = @intToPtr(*volatile u32, base_address + 0x2c);
+
+        /// address: 0x6003a030
+        /// result text material text_out_0 configure register
+        pub const TEXT_OUT_0 = @intToPtr(*volatile u32, base_address + 0x30);
+
+        /// address: 0x6003a034
+        /// result text material text_out_1 configure register
+        pub const TEXT_OUT_1 = @intToPtr(*volatile u32, base_address + 0x34);
+
+        /// address: 0x6003a038
+        /// result text material text_out_2 configure register
+        pub const TEXT_OUT_2 = @intToPtr(*volatile u32, base_address + 0x38);
+
+        /// address: 0x6003a03c
+        /// result text material text_out_3 configure register
+        pub const TEXT_OUT_3 = @intToPtr(*volatile u32, base_address + 0x3c);
+
+        /// address: 0x6003a040
+        /// AES Mode register
+        pub const MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x40);
+
+        /// address: 0x6003a044
+        /// AES Endian configure register
+        pub const ENDIAN = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x44);
+
+        /// address: 0x6003a048
+        /// AES trigger register
+        pub const TRIGGER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x48);
+
+        /// address: 0x6003a04c
+        /// AES state register
+        pub const STATE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x4c);
+
+        /// address: 0x6003a050
+        /// The memory that stores initialization vector
+        pub const IV_MEM = @intToPtr(*volatile [16]u8, base_address + 0x50);
+
+        /// address: 0x6003a060
+        /// The memory that stores GCM hash subkey
+        pub const H_MEM = @intToPtr(*volatile [16]u8, base_address + 0x60);
+
+        /// address: 0x6003a070
+        /// The memory that stores J0
+        pub const J0_MEM = @intToPtr(*volatile [16]u8, base_address + 0x70);
+
+        /// address: 0x6003a080
+        /// The memory that stores T0
+        pub const T0_MEM = @intToPtr(*volatile [16]u8, base_address + 0x80);
+
+        /// address: 0x6003a090
+        /// DMA-AES working mode register
+        pub const DMA_ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x90);
+
+        /// address: 0x6003a094
+        /// AES cipher block mode register
+        pub const BLOCK_MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x94);
+
+        /// address: 0x6003a098
+        /// AES block number register
+        pub const BLOCK_NUM = @intToPtr(*volatile u32, base_address + 0x98);
+
+        /// address: 0x6003a09c
+        /// Standard incrementing function configure register
+        pub const INC_SEL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x9c);
+
+        /// address: 0x6003a0a0
+        /// Additional Authential Data block number register
+        pub const AAD_BLOCK_NUM = @intToPtr(*volatile u32, base_address + 0xa0);
+
+        /// address: 0x6003a0a4
+        /// AES remainder bit number register
+        pub const REMAINDER_BIT_NUM = @intToPtr(*volatile MmioInt(32, u7), base_address + 0xa4);
+
+        /// address: 0x6003a0a8
+        /// AES continue register
+        pub const CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xa8);
+
+        /// address: 0x6003a0ac
+        /// AES Interrupt clear register
+        pub const INT_CLEAR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xac);
+
+        /// address: 0x6003a0b0
+        /// AES Interrupt enable register
+        pub const INT_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xb0);
+
+        /// address: 0x6003a0b4
+        /// AES version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0xb4);
+
+        /// address: 0x6003a0b8
+        /// AES-DMA exit config
+        pub const DMA_EXIT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xb8);
+    };
+
+    /// Advanced Peripheral Bus Controller
+    pub const APB_CTRL = struct {
+        pub const base_address = 0x60026000;
+
+        /// address: 0x60026000
+        /// APB_CTRL_SYSCLK_CONF_REG
+        pub const SYSCLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_pre_div_cnt
+            PRE_DIV_CNT: u10,
+            /// reg_clk_320m_en
+            CLK_320M_EN: u1,
+            /// reg_clk_en
+            CLK_EN: u1,
+            /// reg_rst_tick_cnt
+            RST_TICK_CNT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60026004
+        /// APB_CTRL_TICK_CONF_REG
+        pub const TICK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_xtal_tick_num
+            XTAL_TICK_NUM: u8,
+            /// reg_ck8m_tick_num
+            CK8M_TICK_NUM: u8,
+            /// reg_tick_enable
+            TICK_ENABLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60026008
+        /// APB_CTRL_CLK_OUT_EN_REG
+        pub const CLK_OUT_EN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_clk20_oen
+            CLK20_OEN: u1,
+            /// reg_clk22_oen
+            CLK22_OEN: u1,
+            /// reg_clk44_oen
+            CLK44_OEN: u1,
+            /// reg_clk_bb_oen
+            CLK_BB_OEN: u1,
+            /// reg_clk80_oen
+            CLK80_OEN: u1,
+            /// reg_clk160_oen
+            CLK160_OEN: u1,
+            /// reg_clk_320m_oen
+            CLK_320M_OEN: u1,
+            /// reg_clk_adc_inf_oen
+            CLK_ADC_INF_OEN: u1,
+            /// reg_clk_dac_cpu_oen
+            CLK_DAC_CPU_OEN: u1,
+            /// reg_clk40x_bb_oen
+            CLK40X_BB_OEN: u1,
+            /// reg_clk_xtal_oen
+            CLK_XTAL_OEN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6002600c
+        /// APB_CTRL_WIFI_BB_CFG_REG
+        pub const WIFI_BB_CFG = @intToPtr(*volatile u32, base_address + 0xc);
+
+        /// address: 0x60026010
+        /// APB_CTRL_WIFI_BB_CFG_2_REG
+        pub const WIFI_BB_CFG_2 = @intToPtr(*volatile u32, base_address + 0x10);
+
+        /// address: 0x60026014
+        /// APB_CTRL_WIFI_CLK_EN_REG
+        pub const WIFI_CLK_EN = @intToPtr(*volatile u32, base_address + 0x14);
+
+        /// address: 0x60026018
+        /// APB_CTRL_WIFI_RST_EN_REG
+        pub const WIFI_RST_EN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wifi_rst
+            WIFI_RST: u32,
+        }), base_address + 0x18);
+
+        /// address: 0x6002601c
+        /// APB_CTRL_HOST_INF_SEL_REG
+        pub const HOST_INF_SEL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_peri_io_swap
+            PERI_IO_SWAP: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60026020
+        /// APB_CTRL_EXT_MEM_PMS_LOCK_REG
+        pub const EXT_MEM_PMS_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x20);
+
+        /// address: 0x60026028
+        /// APB_CTRL_FLASH_ACE0_ATTR_REG
+        pub const FLASH_ACE0_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x28);
+
+        /// address: 0x6002602c
+        /// APB_CTRL_FLASH_ACE1_ATTR_REG
+        pub const FLASH_ACE1_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x2c);
+
+        /// address: 0x60026030
+        /// APB_CTRL_FLASH_ACE2_ATTR_REG
+        pub const FLASH_ACE2_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x30);
+
+        /// address: 0x60026034
+        /// APB_CTRL_FLASH_ACE3_ATTR_REG
+        pub const FLASH_ACE3_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x34);
+
+        /// address: 0x60026038
+        /// APB_CTRL_FLASH_ACE0_ADDR_REG
+        pub const FLASH_ACE0_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_flash_ace0_addr_s
+            S: u32,
+        }), base_address + 0x38);
+
+        /// address: 0x6002603c
+        /// APB_CTRL_FLASH_ACE1_ADDR_REG
+        pub const FLASH_ACE1_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_flash_ace1_addr_s
+            S: u32,
+        }), base_address + 0x3c);
+
+        /// address: 0x60026040
+        /// APB_CTRL_FLASH_ACE2_ADDR_REG
+        pub const FLASH_ACE2_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_flash_ace2_addr_s
+            S: u32,
+        }), base_address + 0x40);
+
+        /// address: 0x60026044
+        /// APB_CTRL_FLASH_ACE3_ADDR_REG
+        pub const FLASH_ACE3_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_flash_ace3_addr_s
+            S: u32,
+        }), base_address + 0x44);
+
+        /// address: 0x60026048
+        /// APB_CTRL_FLASH_ACE0_SIZE_REG
+        pub const FLASH_ACE0_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x48);
+
+        /// address: 0x6002604c
+        /// APB_CTRL_FLASH_ACE1_SIZE_REG
+        pub const FLASH_ACE1_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x4c);
+
+        /// address: 0x60026050
+        /// APB_CTRL_FLASH_ACE2_SIZE_REG
+        pub const FLASH_ACE2_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x50);
+
+        /// address: 0x60026054
+        /// APB_CTRL_FLASH_ACE3_SIZE_REG
+        pub const FLASH_ACE3_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x54);
+
+        /// address: 0x60026088
+        /// APB_CTRL_SPI_MEM_PMS_CTRL_REG
+        pub const SPI_MEM_PMS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_spi_mem_reject_int
+            SPI_MEM_REJECT_INT: u1,
+            /// reg_spi_mem_reject_clr
+            SPI_MEM_REJECT_CLR: u1,
+            /// reg_spi_mem_reject_cde
+            SPI_MEM_REJECT_CDE: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x6002608c
+        /// APB_CTRL_SPI_MEM_REJECT_ADDR_REG
+        pub const SPI_MEM_REJECT_ADDR = @intToPtr(*volatile u32, base_address + 0x8c);
+
+        /// address: 0x60026090
+        /// APB_CTRL_SDIO_CTRL_REG
+        pub const SDIO_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_sdio_win_access_en
+            SDIO_WIN_ACCESS_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x60026094
+        /// APB_CTRL_REDCY_SIG0_REG
+        pub const REDCY_SIG0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_redcy_sig0
+            REDCY_SIG0: u31,
+            /// reg_redcy_andor
+            REDCY_ANDOR: u1,
+        }), base_address + 0x94);
+
+        /// address: 0x60026098
+        /// APB_CTRL_REDCY_SIG1_REG
+        pub const REDCY_SIG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_redcy_sig1
+            REDCY_SIG1: u31,
+            /// reg_redcy_nandor
+            REDCY_NANDOR: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x6002609c
+        /// APB_CTRL_FRONT_END_MEM_PD_REG
+        pub const FRONT_END_MEM_PD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_agc_mem_force_pu
+            AGC_MEM_FORCE_PU: u1,
+            /// reg_agc_mem_force_pd
+            AGC_MEM_FORCE_PD: u1,
+            /// reg_pbus_mem_force_pu
+            PBUS_MEM_FORCE_PU: u1,
+            /// reg_pbus_mem_force_pd
+            PBUS_MEM_FORCE_PD: u1,
+            /// reg_dc_mem_force_pu
+            DC_MEM_FORCE_PU: u1,
+            /// reg_dc_mem_force_pd
+            DC_MEM_FORCE_PD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x9c);
+
+        /// address: 0x600260a0
+        /// APB_CTRL_RETENTION_CTRL_REG
+        pub const RETENTION_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_retention_link_addr
+            RETENTION_LINK_ADDR: u27,
+            /// reg_nobypass_cpu_iso_rst
+            NOBYPASS_CPU_ISO_RST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x600260a4
+        /// APB_CTRL_CLKGATE_FORCE_ON_REG
+        pub const CLKGATE_FORCE_ON = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rom_clkgate_force_on
+            ROM_CLKGATE_FORCE_ON: u2,
+            /// reg_sram_clkgate_force_on
+            SRAM_CLKGATE_FORCE_ON: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600260a8
+        /// APB_CTRL_MEM_POWER_DOWN_REG
+        pub const MEM_POWER_DOWN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rom_power_down
+            ROM_POWER_DOWN: u2,
+            /// reg_sram_power_down
+            SRAM_POWER_DOWN: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600260ac
+        /// APB_CTRL_MEM_POWER_UP_REG
+        pub const MEM_POWER_UP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rom_power_up
+            ROM_POWER_UP: u2,
+            /// reg_sram_power_up
+            SRAM_POWER_UP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600260b0
+        /// APB_CTRL_RND_DATA_REG
+        pub const RND_DATA = @intToPtr(*volatile u32, base_address + 0xb0);
+
+        /// address: 0x600260b4
+        /// APB_CTRL_PERI_BACKUP_CONFIG_REG
+        pub const PERI_BACKUP_CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// reg_peri_backup_flow_err
+            PERI_BACKUP_FLOW_ERR: u2,
+            reserved1: u1,
+            /// reg_peri_backup_burst_limit
+            PERI_BACKUP_BURST_LIMIT: u5,
+            /// reg_peri_backup_tout_thres
+            PERI_BACKUP_TOUT_THRES: u10,
+            /// reg_peri_backup_size
+            PERI_BACKUP_SIZE: u10,
+            /// reg_peri_backup_start
+            PERI_BACKUP_START: u1,
+            /// reg_peri_backup_to_mem
+            PERI_BACKUP_TO_MEM: u1,
+            /// reg_peri_backup_ena
+            PERI_BACKUP_ENA: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600260b8
+        /// APB_CTRL_PERI_BACKUP_APB_ADDR_REG
+        pub const PERI_BACKUP_APB_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_backup_apb_start_addr
+            BACKUP_APB_START_ADDR: u32,
+        }), base_address + 0xb8);
+
+        /// address: 0x600260bc
+        /// APB_CTRL_PERI_BACKUP_MEM_ADDR_REG
+        pub const PERI_BACKUP_MEM_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_backup_mem_start_addr
+            BACKUP_MEM_START_ADDR: u32,
+        }), base_address + 0xbc);
+
+        /// address: 0x600260c0
+        /// APB_CTRL_PERI_BACKUP_INT_RAW_REG
+        pub const PERI_BACKUP_INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_peri_backup_done_int_raw
+            PERI_BACKUP_DONE_INT_RAW: u1,
+            /// reg_peri_backup_err_int_raw
+            PERI_BACKUP_ERR_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600260c4
+        /// APB_CTRL_PERI_BACKUP_INT_ST_REG
+        pub const PERI_BACKUP_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_peri_backup_done_int_st
+            PERI_BACKUP_DONE_INT_ST: u1,
+            /// reg_peri_backup_err_int_st
+            PERI_BACKUP_ERR_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xc4);
+
+        /// address: 0x600260c8
+        /// APB_CTRL_PERI_BACKUP_INT_ENA_REG
+        pub const PERI_BACKUP_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_peri_backup_done_int_ena
+            PERI_BACKUP_DONE_INT_ENA: u1,
+            /// reg_peri_backup_err_int_ena
+            PERI_BACKUP_ERR_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600260d0
+        /// APB_CTRL_PERI_BACKUP_INT_CLR_REG
+        pub const PERI_BACKUP_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_peri_backup_done_int_clr
+            PERI_BACKUP_DONE_INT_CLR: u1,
+            /// reg_peri_backup_err_int_clr
+            PERI_BACKUP_ERR_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x600263fc
+        /// APB_CTRL_DATE_REG
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x3fc);
+    };
+
+    /// Successive Approximation Register Analog to Digital Converter
+    pub const APB_SARADC = struct {
+        pub const base_address = 0x60040000;
+
+        /// address: 0x60040000
+        /// digital saradc configure register
+        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// select software enable saradc sample
+            SARADC_START_FORCE: u1,
+            /// software enable saradc sample
+            SARADC_START: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// SAR clock gated
+            SARADC_SAR_CLK_GATED: u1,
+            /// SAR clock divider
+            SARADC_SAR_CLK_DIV: u8,
+            /// 0 ~ 15 means length 1 ~ 16
+            SARADC_SAR_PATT_LEN: u3,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// clear the pointer of pattern table for DIG ADC1 CTRL
+            SARADC_SAR_PATT_P_CLEAR: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// force option to xpd sar blocks
+            SARADC_XPD_SAR_FORCE: u2,
+            reserved12: u1,
+            /// wait arbit signal stable after sar_done
+            SARADC_WAIT_ARB_CYCLE: u2,
+        }), base_address + 0x0);
+
+        /// address: 0x60040004
+        /// digital saradc configure register
+        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// enable max meas num
+            SARADC_MEAS_NUM_LIMIT: u1,
+            /// max conversion number
+            SARADC_MAX_MEAS_NUM: u8,
+            /// 1: data to DIG ADC1 CTRL is inverted, otherwise not
+            SARADC_SAR1_INV: u1,
+            /// 1: data to DIG ADC2 CTRL is inverted, otherwise not
+            SARADC_SAR2_INV: u1,
+            reserved0: u1,
+            /// to set saradc timer target
+            SARADC_TIMER_TARGET: u12,
+            /// to enable saradc timer trigger
+            SARADC_TIMER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60040008
+        /// digital saradc configure register
+        pub const FILTER_CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// Factor of saradc filter1
+            APB_SARADC_FILTER_FACTOR1: u3,
+            /// Factor of saradc filter0
+            APB_SARADC_FILTER_FACTOR0: u3,
+        }), base_address + 0x8);
+
+        /// address: 0x6004000c
+        /// digital saradc configure register
+        pub const FSM_WAIT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc_xpd_wait
+            SARADC_XPD_WAIT: u8,
+            /// saradc_rstb_wait
+            SARADC_RSTB_WAIT: u8,
+            /// saradc_standby_wait
+            SARADC_STANDBY_WAIT: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60040010
+        /// digital saradc configure register
+        pub const SAR1_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc1 status about data and channel
+            SARADC_SAR1_STATUS: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x60040014
+        /// digital saradc configure register
+        pub const SAR2_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc2 status about data and channel
+            SARADC_SAR2_STATUS: u32,
+        }), base_address + 0x14);
+
+        /// address: 0x60040018
+        /// digital saradc configure register
+        pub const SAR_PATT_TAB1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// item 0 ~ 3 for pattern table 1 (each item one byte)
+            SARADC_SAR_PATT_TAB1: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6004001c
+        /// digital saradc configure register
+        pub const SAR_PATT_TAB2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Item 4 ~ 7 for pattern table 1 (each item one byte)
+            SARADC_SAR_PATT_TAB2: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60040020
+        /// digital saradc configure register
+        pub const ONETIME_SAMPLE = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            /// configure onetime atten
+            SARADC_ONETIME_ATTEN: u2,
+            /// configure onetime channel
+            SARADC_ONETIME_CHANNEL: u4,
+            /// trigger adc onetime sample
+            SARADC_ONETIME_START: u1,
+            /// enable adc2 onetime sample
+            SARADC2_ONETIME_SAMPLE: u1,
+            /// enable adc1 onetime sample
+            SARADC1_ONETIME_SAMPLE: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60040024
+        /// digital saradc configure register
+        pub const ARB_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            /// adc2 arbiter force to enableapb controller
+            ADC_ARB_APB_FORCE: u1,
+            /// adc2 arbiter force to enable rtc controller
+            ADC_ARB_RTC_FORCE: u1,
+            /// adc2 arbiter force to enable wifi controller
+            ADC_ARB_WIFI_FORCE: u1,
+            /// adc2 arbiter force grant
+            ADC_ARB_GRANT_FORCE: u1,
+            /// Set adc2 arbiterapb priority
+            ADC_ARB_APB_PRIORITY: u2,
+            /// Set adc2 arbiter rtc priority
+            ADC_ARB_RTC_PRIORITY: u2,
+            /// Set adc2 arbiter wifi priority
+            ADC_ARB_WIFI_PRIORITY: u2,
+            /// adc2 arbiter uses fixed priority
+            ADC_ARB_FIX_PRIORITY: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60040028
+        /// digital saradc configure register
+        pub const FILTER_CTRL0 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// configure filter1 to adc channel
+            APB_SARADC_FILTER_CHANNEL1: u4,
+            /// configure filter0 to adc channel
+            APB_SARADC_FILTER_CHANNEL0: u4,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            /// enable apb_adc1_filter
+            APB_SARADC_FILTER_RESET: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6004002c
+        /// digital saradc configure register
+        pub const SAR1DATA_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc1 data
+            APB_SARADC1_DATA: u17,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60040030
+        /// digital saradc configure register
+        pub const SAR2DATA_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc2 data
+            APB_SARADC2_DATA: u17,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60040034
+        /// digital saradc configure register
+        pub const THRES0_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// configure thres0 to adc channel
+            APB_SARADC_THRES0_CHANNEL: u4,
+            reserved0: u1,
+            /// saradc thres0 monitor thres
+            APB_SARADC_THRES0_HIGH: u13,
+            /// saradc thres0 monitor thres
+            APB_SARADC_THRES0_LOW: u13,
+            padding0: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60040038
+        /// digital saradc configure register
+        pub const THRES1_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// configure thres1 to adc channel
+            APB_SARADC_THRES1_CHANNEL: u4,
+            reserved0: u1,
+            /// saradc thres1 monitor thres
+            APB_SARADC_THRES1_HIGH: u13,
+            /// saradc thres1 monitor thres
+            APB_SARADC_THRES1_LOW: u13,
+            padding0: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6004003c
+        /// digital saradc configure register
+        pub const THRES_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            /// enable thres to all channel
+            APB_SARADC_THRES_ALL_EN: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// enable thres1
+            APB_SARADC_THRES1_EN: u1,
+            /// enable thres0
+            APB_SARADC_THRES0_EN: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60040040
+        /// digital saradc int register
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// saradc thres1 low interrupt enable
+            APB_SARADC_THRES1_LOW_INT_ENA: u1,
+            /// saradc thres0 low interrupt enable
+            APB_SARADC_THRES0_LOW_INT_ENA: u1,
+            /// saradc thres1 high interrupt enable
+            APB_SARADC_THRES1_HIGH_INT_ENA: u1,
+            /// saradc thres0 high interrupt enable
+            APB_SARADC_THRES0_HIGH_INT_ENA: u1,
+            /// saradc2 done interrupt enable
+            APB_SARADC2_DONE_INT_ENA: u1,
+            /// saradc1 done interrupt enable
+            APB_SARADC1_DONE_INT_ENA: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60040044
+        /// digital saradc int register
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// saradc thres1 low interrupt raw
+            APB_SARADC_THRES1_LOW_INT_RAW: u1,
+            /// saradc thres0 low interrupt raw
+            APB_SARADC_THRES0_LOW_INT_RAW: u1,
+            /// saradc thres1 high interrupt raw
+            APB_SARADC_THRES1_HIGH_INT_RAW: u1,
+            /// saradc thres0 high interrupt raw
+            APB_SARADC_THRES0_HIGH_INT_RAW: u1,
+            /// saradc2 done interrupt raw
+            APB_SARADC2_DONE_INT_RAW: u1,
+            /// saradc1 done interrupt raw
+            APB_SARADC1_DONE_INT_RAW: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60040048
+        /// digital saradc int register
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// saradc thres1 low interrupt state
+            APB_SARADC_THRES1_LOW_INT_ST: u1,
+            /// saradc thres0 low interrupt state
+            APB_SARADC_THRES0_LOW_INT_ST: u1,
+            /// saradc thres1 high interrupt state
+            APB_SARADC_THRES1_HIGH_INT_ST: u1,
+            /// saradc thres0 high interrupt state
+            APB_SARADC_THRES0_HIGH_INT_ST: u1,
+            /// saradc2 done interrupt state
+            APB_SARADC2_DONE_INT_ST: u1,
+            /// saradc1 done interrupt state
+            APB_SARADC1_DONE_INT_ST: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6004004c
+        /// digital saradc int register
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// saradc thres1 low interrupt clear
+            APB_SARADC_THRES1_LOW_INT_CLR: u1,
+            /// saradc thres0 low interrupt clear
+            APB_SARADC_THRES0_LOW_INT_CLR: u1,
+            /// saradc thres1 high interrupt clear
+            APB_SARADC_THRES1_HIGH_INT_CLR: u1,
+            /// saradc thres0 high interrupt clear
+            APB_SARADC_THRES0_HIGH_INT_CLR: u1,
+            /// saradc2 done interrupt clear
+            APB_SARADC2_DONE_INT_CLR: u1,
+            /// saradc1 done interrupt clear
+            APB_SARADC1_DONE_INT_CLR: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60040050
+        /// digital saradc configure register
+        pub const DMA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the dma_in_suc_eof gen when sample cnt = spi_eof_num
+            APB_ADC_EOF_NUM: u16,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// reset_apb_adc_state
+            APB_ADC_RESET_FSM: u1,
+            /// enable apb_adc use spi_dma
+            APB_ADC_TRANS: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60040054
+        /// digital saradc configure register
+        pub const CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Integral I2S clock divider value
+            CLKM_DIV_NUM: u8,
+            /// Fractional clock divider numerator value
+            CLKM_DIV_B: u6,
+            /// Fractional clock divider denominator value
+            CLKM_DIV_A: u6,
+            /// reg clk en
+            CLK_EN: u1,
+            /// Set this bit to enable clk_apll
+            CLK_SEL: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60040058
+        /// digital tsens configure register
+        pub const APB_TSENS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// temperature sensor data out
+            TSENS_OUT: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            /// invert temperature sensor data
+            TSENS_IN_INV: u1,
+            /// temperature sensor clock divider
+            TSENS_CLK_DIV: u8,
+            /// temperature sensor power up
+            TSENS_PU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6004005c
+        /// digital tsens configure register
+        pub const TSENS_CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the time that power up tsens need wait
+            TSENS_XPD_WAIT: u12,
+            /// force power up tsens
+            TSENS_XPD_FORCE: u2,
+            /// inv tsens clk
+            TSENS_CLK_INV: u1,
+            /// tsens clk select
+            TSENS_CLK_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60040060
+        /// digital saradc configure register
+        pub const CALI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// saradc cali factor
+            APB_SARADC_CALI_CFG: u17,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x600403fc
+        /// version
+        pub const CTRL_DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// version
+            DATE: u32,
+        }), base_address + 0x3fc);
+    };
+
+    /// Debug Assist
+    pub const ASSIST_DEBUG = struct {
+        pub const base_address = 0x600ce000;
+
+        /// address: 0x600ce000
+        /// ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG
+        pub const C0RE_0_MONTR_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_area_dram0_0_rd_ena
+            CORE_0_AREA_DRAM0_0_RD_ENA: u1,
+            /// reg_core_0_area_dram0_0_wr_ena
+            CORE_0_AREA_DRAM0_0_WR_ENA: u1,
+            /// reg_core_0_area_dram0_1_rd_ena
+            CORE_0_AREA_DRAM0_1_RD_ENA: u1,
+            /// reg_core_0_area_dram0_1_wr_ena
+            CORE_0_AREA_DRAM0_1_WR_ENA: u1,
+            /// reg_core_0_area_pif_0_rd_ena
+            CORE_0_AREA_PIF_0_RD_ENA: u1,
+            /// reg_core_0_area_pif_0_wr_ena
+            CORE_0_AREA_PIF_0_WR_ENA: u1,
+            /// reg_core_0_area_pif_1_rd_ena
+            CORE_0_AREA_PIF_1_RD_ENA: u1,
+            /// reg_core_0_area_pif_1_wr_ena
+            CORE_0_AREA_PIF_1_WR_ENA: u1,
+            /// reg_core_0_sp_spill_min_ena
+            CORE_0_SP_SPILL_MIN_ENA: u1,
+            /// reg_core_0_sp_spill_max_ena
+            CORE_0_SP_SPILL_MAX_ENA: u1,
+            /// reg_core_0_iram0_exception_monitor_ena
+            CORE_0_IRAM0_EXCEPTION_MONITOR_ENA: u1,
+            /// reg_core_0_dram0_exception_monitor_ena
+            CORE_0_DRAM0_EXCEPTION_MONITOR_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x600ce004
+        /// ASSIST_DEBUG_CORE_0_INTR_RAW_REG
+        pub const CORE_0_INTR_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_area_dram0_0_rd_raw
+            CORE_0_AREA_DRAM0_0_RD_RAW: u1,
+            /// reg_core_0_area_dram0_0_wr_raw
+            CORE_0_AREA_DRAM0_0_WR_RAW: u1,
+            /// reg_core_0_area_dram0_1_rd_raw
+            CORE_0_AREA_DRAM0_1_RD_RAW: u1,
+            /// reg_core_0_area_dram0_1_wr_raw
+            CORE_0_AREA_DRAM0_1_WR_RAW: u1,
+            /// reg_core_0_area_pif_0_rd_raw
+            CORE_0_AREA_PIF_0_RD_RAW: u1,
+            /// reg_core_0_area_pif_0_wr_raw
+            CORE_0_AREA_PIF_0_WR_RAW: u1,
+            /// reg_core_0_area_pif_1_rd_raw
+            CORE_0_AREA_PIF_1_RD_RAW: u1,
+            /// reg_core_0_area_pif_1_wr_raw
+            CORE_0_AREA_PIF_1_WR_RAW: u1,
+            /// reg_core_0_sp_spill_min_raw
+            CORE_0_SP_SPILL_MIN_RAW: u1,
+            /// reg_core_0_sp_spill_max_raw
+            CORE_0_SP_SPILL_MAX_RAW: u1,
+            /// reg_core_0_iram0_exception_monitor_raw
+            CORE_0_IRAM0_EXCEPTION_MONITOR_RAW: u1,
+            /// reg_core_0_dram0_exception_monitor_raw
+            CORE_0_DRAM0_EXCEPTION_MONITOR_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x600ce008
+        /// ASSIST_DEBUG_CORE_0_INTR_ENA_REG
+        pub const CORE_0_INTR_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_area_dram0_0_rd_intr_ena
+            CORE_0_AREA_DRAM0_0_RD_INTR_ENA: u1,
+            /// reg_core_0_area_dram0_0_wr_intr_ena
+            CORE_0_AREA_DRAM0_0_WR_INTR_ENA: u1,
+            /// reg_core_0_area_dram0_1_rd_intr_ena
+            CORE_0_AREA_DRAM0_1_RD_INTR_ENA: u1,
+            /// reg_core_0_area_dram0_1_wr_intr_ena
+            CORE_0_AREA_DRAM0_1_WR_INTR_ENA: u1,
+            /// reg_core_0_area_pif_0_rd_intr_ena
+            CORE_0_AREA_PIF_0_RD_INTR_ENA: u1,
+            /// reg_core_0_area_pif_0_wr_intr_ena
+            CORE_0_AREA_PIF_0_WR_INTR_ENA: u1,
+            /// reg_core_0_area_pif_1_rd_intr_ena
+            CORE_0_AREA_PIF_1_RD_INTR_ENA: u1,
+            /// reg_core_0_area_pif_1_wr_intr_ena
+            CORE_0_AREA_PIF_1_WR_INTR_ENA: u1,
+            /// reg_core_0_sp_spill_min_intr_ena
+            CORE_0_SP_SPILL_MIN_INTR_ENA: u1,
+            /// reg_core_0_sp_spill_max_intr_ena
+            CORE_0_SP_SPILL_MAX_INTR_ENA: u1,
+            /// reg_core_0_iram0_exception_monitor_ena
+            CORE_0_IRAM0_EXCEPTION_MONITOR_RLS: u1,
+            /// reg_core_0_dram0_exception_monitor_ena
+            CORE_0_DRAM0_EXCEPTION_MONITOR_RLS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x600ce00c
+        /// ASSIST_DEBUG_CORE_0_INTR_CLR_REG
+        pub const CORE_0_INTR_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_area_dram0_0_rd_clr
+            CORE_0_AREA_DRAM0_0_RD_CLR: u1,
+            /// reg_core_0_area_dram0_0_wr_clr
+            CORE_0_AREA_DRAM0_0_WR_CLR: u1,
+            /// reg_core_0_area_dram0_1_rd_clr
+            CORE_0_AREA_DRAM0_1_RD_CLR: u1,
+            /// reg_core_0_area_dram0_1_wr_clr
+            CORE_0_AREA_DRAM0_1_WR_CLR: u1,
+            /// reg_core_0_area_pif_0_rd_clr
+            CORE_0_AREA_PIF_0_RD_CLR: u1,
+            /// reg_core_0_area_pif_0_wr_clr
+            CORE_0_AREA_PIF_0_WR_CLR: u1,
+            /// reg_core_0_area_pif_1_rd_clr
+            CORE_0_AREA_PIF_1_RD_CLR: u1,
+            /// reg_core_0_area_pif_1_wr_clr
+            CORE_0_AREA_PIF_1_WR_CLR: u1,
+            /// reg_core_0_sp_spill_min_clr
+            CORE_0_SP_SPILL_MIN_CLR: u1,
+            /// reg_core_0_sp_spill_max_clr
+            CORE_0_SP_SPILL_MAX_CLR: u1,
+            /// reg_core_0_iram0_exception_monitor_clr
+            CORE_0_IRAM0_EXCEPTION_MONITOR_CLR: u1,
+            /// reg_core_0_dram0_exception_monitor_clr
+            CORE_0_DRAM0_EXCEPTION_MONITOR_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x600ce010
+        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG
+        pub const CORE_0_AREA_DRAM0_0_MIN = @intToPtr(*volatile u32, base_address + 0x10);
+
+        /// address: 0x600ce014
+        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG
+        pub const CORE_0_AREA_DRAM0_0_MAX = @intToPtr(*volatile u32, base_address + 0x14);
+
+        /// address: 0x600ce018
+        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG
+        pub const CORE_0_AREA_DRAM0_1_MIN = @intToPtr(*volatile u32, base_address + 0x18);
+
+        /// address: 0x600ce01c
+        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG
+        pub const CORE_0_AREA_DRAM0_1_MAX = @intToPtr(*volatile u32, base_address + 0x1c);
+
+        /// address: 0x600ce020
+        /// ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG
+        pub const CORE_0_AREA_PIF_0_MIN = @intToPtr(*volatile u32, base_address + 0x20);
+
+        /// address: 0x600ce024
+        /// ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG
+        pub const CORE_0_AREA_PIF_0_MAX = @intToPtr(*volatile u32, base_address + 0x24);
+
+        /// address: 0x600ce028
+        /// ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG
+        pub const CORE_0_AREA_PIF_1_MIN = @intToPtr(*volatile u32, base_address + 0x28);
+
+        /// address: 0x600ce02c
+        /// ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG
+        pub const CORE_0_AREA_PIF_1_MAX = @intToPtr(*volatile u32, base_address + 0x2c);
+
+        /// address: 0x600ce030
+        /// ASSIST_DEBUG_CORE_0_AREA_PC_REG
+        pub const CORE_0_AREA_PC = @intToPtr(*volatile u32, base_address + 0x30);
+
+        /// address: 0x600ce034
+        /// ASSIST_DEBUG_CORE_0_AREA_SP_REG
+        pub const CORE_0_AREA_SP = @intToPtr(*volatile u32, base_address + 0x34);
+
+        /// address: 0x600ce038
+        /// ASSIST_DEBUG_CORE_0_SP_MIN_REG
+        pub const CORE_0_SP_MIN = @intToPtr(*volatile u32, base_address + 0x38);
+
+        /// address: 0x600ce03c
+        /// ASSIST_DEBUG_CORE_0_SP_MAX_REG
+        pub const CORE_0_SP_MAX = @intToPtr(*volatile u32, base_address + 0x3c);
+
+        /// address: 0x600ce040
+        /// ASSIST_DEBUG_CORE_0_SP_PC_REG
+        pub const CORE_0_SP_PC = @intToPtr(*volatile u32, base_address + 0x40);
+
+        /// address: 0x600ce044
+        /// ASSIST_DEBUG_CORE_0_RCD_EN_REG
+        pub const CORE_0_RCD_EN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_rcd_recorden
+            CORE_0_RCD_RECORDEN: u1,
+            /// reg_core_0_rcd_pdebugen
+            CORE_0_RCD_PDEBUGEN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x600ce048
+        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG
+        pub const CORE_0_RCD_PDEBUGPC = @intToPtr(*volatile u32, base_address + 0x48);
+
+        /// address: 0x600ce04c
+        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+        pub const CORE_0_RCD_PDEBUGSP = @intToPtr(*volatile u32, base_address + 0x4c);
+
+        /// address: 0x600ce050
+        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+        pub const CORE_0_IRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_iram0_recording_addr_0
+            CORE_0_IRAM0_RECORDING_ADDR_0: u24,
+            /// reg_core_0_iram0_recording_wr_0
+            CORE_0_IRAM0_RECORDING_WR_0: u1,
+            /// reg_core_0_iram0_recording_loadstore_0
+            CORE_0_IRAM0_RECORDING_LOADSTORE_0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x600ce054
+        /// ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG
+        pub const CORE_0_IRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_iram0_recording_addr_1
+            CORE_0_IRAM0_RECORDING_ADDR_1: u24,
+            /// reg_core_0_iram0_recording_wr_1
+            CORE_0_IRAM0_RECORDING_WR_1: u1,
+            /// reg_core_0_iram0_recording_loadstore_1
+            CORE_0_IRAM0_RECORDING_LOADSTORE_1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x600ce058
+        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG
+        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_dram0_recording_addr_0
+            CORE_0_DRAM0_RECORDING_ADDR_0: u24,
+            /// reg_core_0_dram0_recording_wr_0
+            CORE_0_DRAM0_RECORDING_WR_0: u1,
+            /// reg_core_0_dram0_recording_byteen_0
+            CORE_0_DRAM0_RECORDING_BYTEEN_0: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x600ce05c
+        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_dram0_recording_pc_0
+            CORE_0_DRAM0_RECORDING_PC_0: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x600ce060
+        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_dram0_recording_addr_1
+            CORE_0_DRAM0_RECORDING_ADDR_1: u24,
+            /// reg_core_0_dram0_recording_wr_1
+            CORE_0_DRAM0_RECORDING_WR_1: u1,
+            /// reg_core_0_dram0_recording_byteen_1
+            CORE_0_DRAM0_RECORDING_BYTEEN_1: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x600ce064
+        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG
+        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_dram0_recording_pc_1
+            CORE_0_DRAM0_RECORDING_PC_1: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x600ce068
+        /// ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG
+        pub const CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_x_iram0_dram0_limit_cycle_0
+            CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x600ce06c
+        /// ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG
+        pub const CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_x_iram0_dram0_limit_cycle_1
+            CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x600ce070
+        /// ASSIST_DEBUG_LOG_SETTING
+        pub const LOG_SETTING = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_log_ena
+            LOG_ENA: u3,
+            /// reg_log_mode
+            LOG_MODE: u4,
+            /// reg_log_mem_loop_enable
+            LOG_MEM_LOOP_ENABLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x600ce074
+        /// ASSIST_DEBUG_LOG_DATA_0_REG
+        pub const LOG_DATA_0 = @intToPtr(*volatile u32, base_address + 0x74);
+
+        /// address: 0x600ce078
+        /// ASSIST_DEBUG_LOG_DATA_MASK_REG
+        pub const LOG_DATA_MASK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_log_data_size
+            LOG_DATA_SIZE: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x600ce07c
+        /// ASSIST_DEBUG_LOG_MIN_REG
+        pub const LOG_MIN = @intToPtr(*volatile u32, base_address + 0x7c);
+
+        /// address: 0x600ce080
+        /// ASSIST_DEBUG_LOG_MAX_REG
+        pub const LOG_MAX = @intToPtr(*volatile u32, base_address + 0x80);
+
+        /// address: 0x600ce084
+        /// ASSIST_DEBUG_LOG_MEM_START_REG
+        pub const LOG_MEM_START = @intToPtr(*volatile u32, base_address + 0x84);
+
+        /// address: 0x600ce088
+        /// ASSIST_DEBUG_LOG_MEM_END_REG
+        pub const LOG_MEM_END = @intToPtr(*volatile u32, base_address + 0x88);
+
+        /// address: 0x600ce08c
+        /// ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG
+        pub const LOG_MEM_WRITING_ADDR = @intToPtr(*volatile u32, base_address + 0x8c);
+
+        /// address: 0x600ce090
+        /// ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG
+        pub const LOG_MEM_FULL_FLAG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_log_mem_full_flag
+            LOG_MEM_FULL_FLAG: u1,
+            /// reg_clr_log_mem_full_flag
+            CLR_LOG_MEM_FULL_FLAG: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x600ce094
+        /// ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION
+        pub const C0RE_0_LASTPC_BEFORE_EXCEPTION = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_lastpc_before_exc
+            CORE_0_LASTPC_BEFORE_EXC: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x600ce098
+        /// ASSIST_DEBUG_C0RE_0_DEBUG_MODE
+        pub const C0RE_0_DEBUG_MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core_0_debug_mode
+            CORE_0_DEBUG_MODE: u1,
+            /// reg_core_0_debug_module_active
+            CORE_0_DEBUG_MODULE_ACTIVE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x600ce1fc
+        /// ASSIST_DEBUG_DATE_REG
+        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_assist_debug_date
+            ASSIST_DEBUG_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x1fc);
+    };
+
+    /// DMA (Direct Memory Access) Controller
+    pub const DMA = struct {
+        pub const base_address = 0x6003f000;
+
+        /// address: 0x6003f000
+        /// DMA_INT_RAW_CH0_REG.
+        pub const INT_RAW_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 0.
+            IN_DONE_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 0. For UHCI0, the raw
+            /// interrupt bit turns to high level when the last data pointed by one inlink
+            /// descriptor has been received and no data error is detected for Rx channel 0.
+            IN_SUC_EOF_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data error is detected only in
+            /// the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals,
+            /// this raw interrupt is reserved.
+            IN_ERR_EOF_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been transmitted to peripherals for Tx channel 0.
+            OUT_DONE_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been read from memory for Tx channel 0.
+            OUT_EOF_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting inlink descriptor
+            /// error, including owner error, the second and third word error of inlink
+            /// descriptor for Rx channel 0.
+            IN_DSCR_ERR_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting outlink descriptor
+            /// error, including owner error, the second and third word error of outlink
+            /// descriptor for Tx channel 0.
+            OUT_DSCR_ERR_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
+            /// full and receiving data is not completed, but there is no more inlink for Rx
+            /// channel 0.
+            IN_DSCR_EMPTY_CH0_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data corresponding a outlink
+            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
+            /// channel 0.
+            OUT_TOTAL_EOF_CH0_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+            /// overflow.
+            INFIFO_OVF_CH0_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
+            /// underflow.
+            INFIFO_UDF_CH0_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
+            /// overflow.
+            OUTFIFO_OVF_CH0_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
+            /// underflow.
+            OUTFIFO_UDF_CH0_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x6003f004
+        /// DMA_INT_ST_CH0_REG.
+        pub const INT_ST_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH0_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH0_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x6003f008
+        /// DMA_INT_ENA_CH0_REG.
+        pub const INT_ENA_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH0_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH0_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6003f00c
+        /// DMA_INT_CLR_CH0_REG.
+        pub const INT_CLR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH0_INT_CLR: u1,
+            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH0_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH0_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH0_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x6003f010
+        /// DMA_INT_RAW_CH1_REG.
+        pub const INT_RAW_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 1.
+            IN_DONE_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 1. For UHCI0, the raw
+            /// interrupt bit turns to high level when the last data pointed by one inlink
+            /// descriptor has been received and no data error is detected for Rx channel 1.
+            IN_SUC_EOF_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data error is detected only in
+            /// the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals,
+            /// this raw interrupt is reserved.
+            IN_ERR_EOF_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been transmitted to peripherals for Tx channel 1.
+            OUT_DONE_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been read from memory for Tx channel 1.
+            OUT_EOF_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting inlink descriptor
+            /// error, including owner error, the second and third word error of inlink
+            /// descriptor for Rx channel 1.
+            IN_DSCR_ERR_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting outlink descriptor
+            /// error, including owner error, the second and third word error of outlink
+            /// descriptor for Tx channel 1.
+            OUT_DSCR_ERR_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
+            /// full and receiving data is not completed, but there is no more inlink for Rx
+            /// channel 1.
+            IN_DSCR_EMPTY_CH1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data corresponding a outlink
+            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
+            /// channel 1.
+            OUT_TOTAL_EOF_CH1_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is
+            /// overflow.
+            INFIFO_OVF_CH1_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is
+            /// underflow.
+            INFIFO_UDF_CH1_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is
+            /// overflow.
+            OUTFIFO_OVF_CH1_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is
+            /// underflow.
+            OUTFIFO_UDF_CH1_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x6003f014
+        /// DMA_INT_ST_CH1_REG.
+        pub const INT_ST_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH1_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH1_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x6003f018
+        /// DMA_INT_ENA_CH1_REG.
+        pub const INT_ENA_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH1_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH1_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6003f01c
+        /// DMA_INT_CLR_CH1_REG.
+        pub const INT_CLR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH1_INT_CLR: u1,
+            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH1_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH1_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH1_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x6003f020
+        /// DMA_INT_RAW_CH2_REG.
+        pub const INT_RAW_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 2.
+            IN_DONE_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// inlink descriptor has been received for Rx channel 2. For UHCI0, the raw
+            /// interrupt bit turns to high level when the last data pointed by one inlink
+            /// descriptor has been received and no data error is detected for Rx channel 2.
+            IN_SUC_EOF_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data error is detected only in
+            /// the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals,
+            /// this raw interrupt is reserved.
+            IN_ERR_EOF_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been transmitted to peripherals for Tx channel 2.
+            OUT_DONE_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when the last data pointed by one
+            /// outlink descriptor has been read from memory for Tx channel 2.
+            OUT_EOF_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting inlink descriptor
+            /// error, including owner error, the second and third word error of inlink
+            /// descriptor for Rx channel 2.
+            IN_DSCR_ERR_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when detecting outlink descriptor
+            /// error, including owner error, the second and third word error of outlink
+            /// descriptor for Tx channel 2.
+            OUT_DSCR_ERR_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
+            /// full and receiving data is not completed, but there is no more inlink for Rx
+            /// channel 2.
+            IN_DSCR_EMPTY_CH2_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when data corresponding a outlink
+            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
+            /// channel 2.
+            OUT_TOTAL_EOF_CH2_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is
+            /// overflow.
+            INFIFO_OVF_CH2_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is
+            /// underflow.
+            INFIFO_UDF_CH2_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is
+            /// overflow.
+            OUTFIFO_OVF_CH2_INT_RAW: u1,
+            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is
+            /// underflow.
+            OUTFIFO_UDF_CH2_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x6003f024
+        /// DMA_INT_ST_CH2_REG.
+        pub const INT_ST_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH2_INT_ST: u1,
+            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH2_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x6003f028
+        /// DMA_INT_ENA_CH2_REG.
+        pub const INT_ENA_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH2_INT_ENA: u1,
+            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH2_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6003f02c
+        /// DMA_INT_CLR_CH2_REG.
+        pub const INT_CLR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
+            IN_DONE_CH2_INT_CLR: u1,
+            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+            IN_SUC_EOF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+            IN_ERR_EOF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
+            OUT_DONE_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
+            OUT_EOF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+            IN_DSCR_ERR_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+            OUT_DSCR_ERR_CH2_INT_CLR: u1,
+            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+            IN_DSCR_EMPTY_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+            OUT_TOTAL_EOF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+            INFIFO_OVF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+            INFIFO_UDF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+            OUTFIFO_OVF_CH2_INT_CLR: u1,
+            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+            OUTFIFO_UDF_CH2_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x6003f040
+        /// DMA_AHB_TEST_REG.
+        pub const AHB_TEST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved
+            AHB_TESTMODE: u3,
+            reserved0: u1,
+            /// reserved
+            AHB_TESTADDR: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x6003f044
+        /// DMA_MISC_CONF_REG.
+        pub const MISC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit, then clear this bit to reset the internal ahb FSM.
+            AHBM_RST_INTER: u1,
+            reserved0: u1,
+            /// Set this bit to disable priority arbitration function.
+            ARB_PRI_DIS: u1,
+            /// reg_clk_en
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x6003f048
+        /// DMA_DATE_REG.
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x48);
+
+        /// address: 0x6003f070
+        /// DMA_IN_CONF0_CH0_REG.
+        pub const IN_CONF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
+            IN_RST_CH0: u1,
+            /// reserved
+            IN_LOOP_TEST_CH0: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
+            /// descriptor when accessing internal SRAM.
+            INDSCR_BURST_EN_CH0: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data
+            /// when accessing internal SRAM.
+            IN_DATA_BURST_EN_CH0: u1,
+            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
+            /// DMA.
+            MEM_TRANS_EN_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x6003f074
+        /// DMA_IN_CONF1_CH0_REG.
+        pub const IN_CONF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            IN_CHECK_OWNER_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x6003f078
+        /// DMA_INFIFO_STATUS_CH0_REG.
+        pub const INFIFO_STATUS_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Rx FIFO full signal for Rx channel 0.
+            INFIFO_FULL_CH0: u1,
+            /// L1 Rx FIFO empty signal for Rx channel 0.
+            INFIFO_EMPTY_CH0: u1,
+            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+            INFIFO_CNT_CH0: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            IN_REMAIN_UNDER_1B_CH0: u1,
+            /// reserved
+            IN_REMAIN_UNDER_2B_CH0: u1,
+            /// reserved
+            IN_REMAIN_UNDER_3B_CH0: u1,
+            /// reserved
+            IN_REMAIN_UNDER_4B_CH0: u1,
+            /// reserved
+            IN_BUF_HUNGRY_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6003f07c
+        /// DMA_IN_POP_CH0_REG.
+        pub const IN_POP_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data popping from DMA FIFO.
+            INFIFO_RDATA_CH0: u12,
+            /// Set this bit to pop data from DMA FIFO.
+            INFIFO_POP_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x6003f080
+        /// DMA_IN_LINK_CH0_REG.
+        pub const IN_LINK_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first inlink
+            /// descriptor's address.
+            INLINK_ADDR_CH0: u20,
+            /// Set this bit to return to current inlink descriptor's address, when there are
+            /// some errors in current receiving data.
+            INLINK_AUTO_RET_CH0: u1,
+            /// Set this bit to stop dealing with the inlink descriptors.
+            INLINK_STOP_CH0: u1,
+            /// Set this bit to start dealing with the inlink descriptors.
+            INLINK_START_CH0: u1,
+            /// Set this bit to mount a new inlink descriptor.
+            INLINK_RESTART_CH0: u1,
+            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
+            /// is working.
+            INLINK_PARK_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x6003f084
+        /// DMA_IN_STATE_CH0_REG.
+        pub const IN_STATE_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current inlink descriptor's address.
+            INLINK_DSCR_ADDR_CH0: u18,
+            /// reserved
+            IN_DSCR_STATE_CH0: u2,
+            /// reserved
+            IN_STATE_CH0: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x6003f088
+        /// DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
+        pub const IN_SUC_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0x88);
+
+        /// address: 0x6003f08c
+        /// DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
+        pub const IN_ERR_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0x8c);
+
+        /// address: 0x6003f090
+        /// DMA_IN_DSCR_CH0_REG.
+        pub const IN_DSCR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current inlink descriptor x.
+            INLINK_DSCR_CH0: u32,
+        }), base_address + 0x90);
+
+        /// address: 0x6003f094
+        /// DMA_IN_DSCR_BF0_CH0_REG.
+        pub const IN_DSCR_BF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last inlink descriptor x-1.
+            INLINK_DSCR_BF0_CH0: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x6003f098
+        /// DMA_IN_DSCR_BF1_CH0_REG.
+        pub const IN_DSCR_BF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            INLINK_DSCR_BF1_CH0: u32,
+        }), base_address + 0x98);
+
+        /// address: 0x6003f09c
+        /// DMA_IN_PRI_CH0_REG.
+        pub const IN_PRI_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Rx channel 0. The larger of the value, the higher of the
+            /// priority.
+            RX_PRI_CH0: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x9c);
+
+        /// address: 0x6003f0a0
+        /// DMA_IN_PERI_SEL_CH0_REG.
+        pub const IN_PERI_SEL_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Rx channel 0. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_IN_SEL_CH0: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x6003f0d0
+        /// DMA_OUT_CONF0_CH0_REG.
+        pub const OUT_CONF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
+            OUT_RST_CH0: u1,
+            /// reserved
+            OUT_LOOP_TEST_CH0: u1,
+            /// Set this bit to enable automatic outlink-writeback when all the data in tx
+            /// buffer has been transmitted.
+            OUT_AUTO_WRBACK_CH0: u1,
+            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is
+            /// generated when data need to transmit has been popped from FIFO in DMA
+            OUT_EOF_MODE_CH0: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
+            /// descriptor when accessing internal SRAM.
+            OUTDSCR_BURST_EN_CH0: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting
+            /// data when accessing internal SRAM.
+            OUT_DATA_BURST_EN_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x6003f0d4
+        /// DMA_OUT_CONF1_CH0_REG.
+        pub const OUT_CONF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            OUT_CHECK_OWNER_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0xd4);
+
+        /// address: 0x6003f0d8
+        /// DMA_OUTFIFO_STATUS_CH0_REG.
+        pub const OUTFIFO_STATUS_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Tx FIFO full signal for Tx channel 0.
+            OUTFIFO_FULL_CH0: u1,
+            /// L1 Tx FIFO empty signal for Tx channel 0.
+            OUTFIFO_EMPTY_CH0: u1,
+            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+            OUTFIFO_CNT_CH0: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_1B_CH0: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_2B_CH0: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_3B_CH0: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_4B_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+        }), base_address + 0xd8);
+
+        /// address: 0x6003f0dc
+        /// DMA_OUT_PUSH_CH0_REG.
+        pub const OUT_PUSH_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data that need to be pushed into DMA FIFO.
+            OUTFIFO_WDATA_CH0: u9,
+            /// Set this bit to push data into DMA FIFO.
+            OUTFIFO_PUSH_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0xdc);
+
+        /// address: 0x6003f0e0
+        /// DMA_OUT_LINK_CH0_REG.
+        pub const OUT_LINK_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first outlink
+            /// descriptor's address.
+            OUTLINK_ADDR_CH0: u20,
+            /// Set this bit to stop dealing with the outlink descriptors.
+            OUTLINK_STOP_CH0: u1,
+            /// Set this bit to start dealing with the outlink descriptors.
+            OUTLINK_START_CH0: u1,
+            /// Set this bit to restart a new outlink from the last address.
+            OUTLINK_RESTART_CH0: u1,
+            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
+            /// FSM is working.
+            OUTLINK_PARK_CH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0xe0);
+
+        /// address: 0x6003f0e4
+        /// DMA_OUT_STATE_CH0_REG.
+        pub const OUT_STATE_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current outlink descriptor's address.
+            OUTLINK_DSCR_ADDR_CH0: u18,
+            /// reserved
+            OUT_DSCR_STATE_CH0: u2,
+            /// reserved
+            OUT_STATE_CH0: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0xe4);
+
+        /// address: 0x6003f0e8
+        /// DMA_OUT_EOF_DES_ADDR_CH0_REG.
+        pub const OUT_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0xe8);
+
+        /// address: 0x6003f0ec
+        /// DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
+        pub const OUT_EOF_BFR_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0xec);
+
+        /// address: 0x6003f0f0
+        /// DMA_OUT_DSCR_CH0_REG.
+        pub const OUT_DSCR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current outlink descriptor y.
+            OUTLINK_DSCR_CH0: u32,
+        }), base_address + 0xf0);
+
+        /// address: 0x6003f0f4
+        /// DMA_OUT_DSCR_BF0_CH0_REG.
+        pub const OUT_DSCR_BF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last outlink descriptor y-1.
+            OUTLINK_DSCR_BF0_CH0: u32,
+        }), base_address + 0xf4);
+
+        /// address: 0x6003f0f8
+        /// DMA_OUT_DSCR_BF1_CH0_REG.
+        pub const OUT_DSCR_BF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            OUTLINK_DSCR_BF1_CH0: u32,
+        }), base_address + 0xf8);
+
+        /// address: 0x6003f0fc
+        /// DMA_OUT_PRI_CH0_REG.
+        pub const OUT_PRI_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Tx channel 0. The larger of the value, the higher of the
+            /// priority.
+            TX_PRI_CH0: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0xfc);
+
+        /// address: 0x6003f100
+        /// DMA_OUT_PERI_SEL_CH0_REG.
+        pub const OUT_PERI_SEL_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Tx channel 0. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_OUT_SEL_CH0: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x100);
+
+        /// address: 0x6003f130
+        /// DMA_IN_CONF0_CH1_REG.
+        pub const IN_CONF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
+            IN_RST_CH1: u1,
+            /// reserved
+            IN_LOOP_TEST_CH1: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link
+            /// descriptor when accessing internal SRAM.
+            INDSCR_BURST_EN_CH1: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data
+            /// when accessing internal SRAM.
+            IN_DATA_BURST_EN_CH1: u1,
+            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
+            /// DMA.
+            MEM_TRANS_EN_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x130);
+
+        /// address: 0x6003f134
+        /// DMA_IN_CONF1_CH1_REG.
+        pub const IN_CONF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            IN_CHECK_OWNER_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x134);
+
+        /// address: 0x6003f138
+        /// DMA_INFIFO_STATUS_CH1_REG.
+        pub const INFIFO_STATUS_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Rx FIFO full signal for Rx channel 1.
+            INFIFO_FULL_CH1: u1,
+            /// L1 Rx FIFO empty signal for Rx channel 1.
+            INFIFO_EMPTY_CH1: u1,
+            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.
+            INFIFO_CNT_CH1: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            IN_REMAIN_UNDER_1B_CH1: u1,
+            /// reserved
+            IN_REMAIN_UNDER_2B_CH1: u1,
+            /// reserved
+            IN_REMAIN_UNDER_3B_CH1: u1,
+            /// reserved
+            IN_REMAIN_UNDER_4B_CH1: u1,
+            /// reserved
+            IN_BUF_HUNGRY_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x138);
+
+        /// address: 0x6003f13c
+        /// DMA_IN_POP_CH1_REG.
+        pub const IN_POP_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data popping from DMA FIFO.
+            INFIFO_RDATA_CH1: u12,
+            /// Set this bit to pop data from DMA FIFO.
+            INFIFO_POP_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x13c);
+
+        /// address: 0x6003f140
+        /// DMA_IN_LINK_CH1_REG.
+        pub const IN_LINK_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first inlink
+            /// descriptor's address.
+            INLINK_ADDR_CH1: u20,
+            /// Set this bit to return to current inlink descriptor's address, when there are
+            /// some errors in current receiving data.
+            INLINK_AUTO_RET_CH1: u1,
+            /// Set this bit to stop dealing with the inlink descriptors.
+            INLINK_STOP_CH1: u1,
+            /// Set this bit to start dealing with the inlink descriptors.
+            INLINK_START_CH1: u1,
+            /// Set this bit to mount a new inlink descriptor.
+            INLINK_RESTART_CH1: u1,
+            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
+            /// is working.
+            INLINK_PARK_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x140);
+
+        /// address: 0x6003f144
+        /// DMA_IN_STATE_CH1_REG.
+        pub const IN_STATE_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current inlink descriptor's address.
+            INLINK_DSCR_ADDR_CH1: u18,
+            /// reserved
+            IN_DSCR_STATE_CH1: u2,
+            /// reserved
+            IN_STATE_CH1: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x144);
+
+        /// address: 0x6003f148
+        /// DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.
+        pub const IN_SUC_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x148);
+
+        /// address: 0x6003f14c
+        /// DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.
+        pub const IN_ERR_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x14c);
+
+        /// address: 0x6003f150
+        /// DMA_IN_DSCR_CH1_REG.
+        pub const IN_DSCR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current inlink descriptor x.
+            INLINK_DSCR_CH1: u32,
+        }), base_address + 0x150);
+
+        /// address: 0x6003f154
+        /// DMA_IN_DSCR_BF0_CH1_REG.
+        pub const IN_DSCR_BF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last inlink descriptor x-1.
+            INLINK_DSCR_BF0_CH1: u32,
+        }), base_address + 0x154);
+
+        /// address: 0x6003f158
+        /// DMA_IN_DSCR_BF1_CH1_REG.
+        pub const IN_DSCR_BF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            INLINK_DSCR_BF1_CH1: u32,
+        }), base_address + 0x158);
+
+        /// address: 0x6003f15c
+        /// DMA_IN_PRI_CH1_REG.
+        pub const IN_PRI_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Rx channel 1. The larger of the value, the higher of the
+            /// priority.
+            RX_PRI_CH1: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x15c);
+
+        /// address: 0x6003f160
+        /// DMA_IN_PERI_SEL_CH1_REG.
+        pub const IN_PERI_SEL_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Rx channel 1. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_IN_SEL_CH1: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x160);
+
+        /// address: 0x6003f190
+        /// DMA_OUT_CONF0_CH1_REG.
+        pub const OUT_CONF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
+            OUT_RST_CH1: u1,
+            /// reserved
+            OUT_LOOP_TEST_CH1: u1,
+            /// Set this bit to enable automatic outlink-writeback when all the data in tx
+            /// buffer has been transmitted.
+            OUT_AUTO_WRBACK_CH1: u1,
+            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is
+            /// generated when data need to transmit has been popped from FIFO in DMA
+            OUT_EOF_MODE_CH1: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link
+            /// descriptor when accessing internal SRAM.
+            OUTDSCR_BURST_EN_CH1: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting
+            /// data when accessing internal SRAM.
+            OUT_DATA_BURST_EN_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x190);
+
+        /// address: 0x6003f194
+        /// DMA_OUT_CONF1_CH1_REG.
+        pub const OUT_CONF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            OUT_CHECK_OWNER_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x194);
+
+        /// address: 0x6003f198
+        /// DMA_OUTFIFO_STATUS_CH1_REG.
+        pub const OUTFIFO_STATUS_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Tx FIFO full signal for Tx channel 1.
+            OUTFIFO_FULL_CH1: u1,
+            /// L1 Tx FIFO empty signal for Tx channel 1.
+            OUTFIFO_EMPTY_CH1: u1,
+            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.
+            OUTFIFO_CNT_CH1: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_1B_CH1: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_2B_CH1: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_3B_CH1: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_4B_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+        }), base_address + 0x198);
+
+        /// address: 0x6003f19c
+        /// DMA_OUT_PUSH_CH1_REG.
+        pub const OUT_PUSH_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data that need to be pushed into DMA FIFO.
+            OUTFIFO_WDATA_CH1: u9,
+            /// Set this bit to push data into DMA FIFO.
+            OUTFIFO_PUSH_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x19c);
+
+        /// address: 0x6003f1a0
+        /// DMA_OUT_LINK_CH1_REG.
+        pub const OUT_LINK_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first outlink
+            /// descriptor's address.
+            OUTLINK_ADDR_CH1: u20,
+            /// Set this bit to stop dealing with the outlink descriptors.
+            OUTLINK_STOP_CH1: u1,
+            /// Set this bit to start dealing with the outlink descriptors.
+            OUTLINK_START_CH1: u1,
+            /// Set this bit to restart a new outlink from the last address.
+            OUTLINK_RESTART_CH1: u1,
+            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
+            /// FSM is working.
+            OUTLINK_PARK_CH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x1a0);
+
+        /// address: 0x6003f1a4
+        /// DMA_OUT_STATE_CH1_REG.
+        pub const OUT_STATE_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current outlink descriptor's address.
+            OUTLINK_DSCR_ADDR_CH1: u18,
+            /// reserved
+            OUT_DSCR_STATE_CH1: u2,
+            /// reserved
+            OUT_STATE_CH1: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x1a4);
+
+        /// address: 0x6003f1a8
+        /// DMA_OUT_EOF_DES_ADDR_CH1_REG.
+        pub const OUT_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x1a8);
+
+        /// address: 0x6003f1ac
+        /// DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.
+        pub const OUT_EOF_BFR_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x1ac);
+
+        /// address: 0x6003f1b0
+        /// DMA_OUT_DSCR_CH1_REG.
+        pub const OUT_DSCR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current outlink descriptor y.
+            OUTLINK_DSCR_CH1: u32,
+        }), base_address + 0x1b0);
+
+        /// address: 0x6003f1b4
+        /// DMA_OUT_DSCR_BF0_CH1_REG.
+        pub const OUT_DSCR_BF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last outlink descriptor y-1.
+            OUTLINK_DSCR_BF0_CH1: u32,
+        }), base_address + 0x1b4);
+
+        /// address: 0x6003f1b8
+        /// DMA_OUT_DSCR_BF1_CH1_REG.
+        pub const OUT_DSCR_BF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            OUTLINK_DSCR_BF1_CH1: u32,
+        }), base_address + 0x1b8);
+
+        /// address: 0x6003f1bc
+        /// DMA_OUT_PRI_CH1_REG.
+        pub const OUT_PRI_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Tx channel 1. The larger of the value, the higher of the
+            /// priority.
+            TX_PRI_CH1: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x1bc);
+
+        /// address: 0x6003f1c0
+        /// DMA_OUT_PERI_SEL_CH1_REG.
+        pub const OUT_PERI_SEL_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Tx channel 1. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_OUT_SEL_CH1: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x1c0);
+
+        /// address: 0x6003f1f0
+        /// DMA_IN_CONF0_CH2_REG.
+        pub const IN_CONF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
+            IN_RST_CH2: u1,
+            /// reserved
+            IN_LOOP_TEST_CH2: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link
+            /// descriptor when accessing internal SRAM.
+            INDSCR_BURST_EN_CH2: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data
+            /// when accessing internal SRAM.
+            IN_DATA_BURST_EN_CH2: u1,
+            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
+            /// DMA.
+            MEM_TRANS_EN_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x1f0);
+
+        /// address: 0x6003f1f4
+        /// DMA_IN_CONF1_CH2_REG.
+        pub const IN_CONF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            IN_CHECK_OWNER_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x1f4);
+
+        /// address: 0x6003f1f8
+        /// DMA_INFIFO_STATUS_CH2_REG.
+        pub const INFIFO_STATUS_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Rx FIFO full signal for Rx channel 2.
+            INFIFO_FULL_CH2: u1,
+            /// L1 Rx FIFO empty signal for Rx channel 2.
+            INFIFO_EMPTY_CH2: u1,
+            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.
+            INFIFO_CNT_CH2: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            IN_REMAIN_UNDER_1B_CH2: u1,
+            /// reserved
+            IN_REMAIN_UNDER_2B_CH2: u1,
+            /// reserved
+            IN_REMAIN_UNDER_3B_CH2: u1,
+            /// reserved
+            IN_REMAIN_UNDER_4B_CH2: u1,
+            /// reserved
+            IN_BUF_HUNGRY_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x1f8);
+
+        /// address: 0x6003f1fc
+        /// DMA_IN_POP_CH2_REG.
+        pub const IN_POP_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data popping from DMA FIFO.
+            INFIFO_RDATA_CH2: u12,
+            /// Set this bit to pop data from DMA FIFO.
+            INFIFO_POP_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x1fc);
+
+        /// address: 0x6003f200
+        /// DMA_IN_LINK_CH2_REG.
+        pub const IN_LINK_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first inlink
+            /// descriptor's address.
+            INLINK_ADDR_CH2: u20,
+            /// Set this bit to return to current inlink descriptor's address, when there are
+            /// some errors in current receiving data.
+            INLINK_AUTO_RET_CH2: u1,
+            /// Set this bit to stop dealing with the inlink descriptors.
+            INLINK_STOP_CH2: u1,
+            /// Set this bit to start dealing with the inlink descriptors.
+            INLINK_START_CH2: u1,
+            /// Set this bit to mount a new inlink descriptor.
+            INLINK_RESTART_CH2: u1,
+            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
+            /// is working.
+            INLINK_PARK_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x200);
+
+        /// address: 0x6003f204
+        /// DMA_IN_STATE_CH2_REG.
+        pub const IN_STATE_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current inlink descriptor's address.
+            INLINK_DSCR_ADDR_CH2: u18,
+            /// reserved
+            IN_DSCR_STATE_CH2: u2,
+            /// reserved
+            IN_STATE_CH2: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x204);
+
+        /// address: 0x6003f208
+        /// DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.
+        pub const IN_SUC_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x208);
+
+        /// address: 0x6003f20c
+        /// DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.
+        pub const IN_ERR_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x20c);
+
+        /// address: 0x6003f210
+        /// DMA_IN_DSCR_CH2_REG.
+        pub const IN_DSCR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current inlink descriptor x.
+            INLINK_DSCR_CH2: u32,
+        }), base_address + 0x210);
+
+        /// address: 0x6003f214
+        /// DMA_IN_DSCR_BF0_CH2_REG.
+        pub const IN_DSCR_BF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last inlink descriptor x-1.
+            INLINK_DSCR_BF0_CH2: u32,
+        }), base_address + 0x214);
+
+        /// address: 0x6003f218
+        /// DMA_IN_DSCR_BF1_CH2_REG.
+        pub const IN_DSCR_BF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            INLINK_DSCR_BF1_CH2: u32,
+        }), base_address + 0x218);
+
+        /// address: 0x6003f21c
+        /// DMA_IN_PRI_CH2_REG.
+        pub const IN_PRI_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Rx channel 2. The larger of the value, the higher of the
+            /// priority.
+            RX_PRI_CH2: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x21c);
+
+        /// address: 0x6003f220
+        /// DMA_IN_PERI_SEL_CH2_REG.
+        pub const IN_PERI_SEL_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Rx channel 2. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_IN_SEL_CH2: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x220);
+
+        /// address: 0x6003f250
+        /// DMA_OUT_CONF0_CH2_REG.
+        pub const OUT_CONF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
+            OUT_RST_CH2: u1,
+            /// reserved
+            OUT_LOOP_TEST_CH2: u1,
+            /// Set this bit to enable automatic outlink-writeback when all the data in tx
+            /// buffer has been transmitted.
+            OUT_AUTO_WRBACK_CH2: u1,
+            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is
+            /// generated when data need to transmit has been popped from FIFO in DMA
+            OUT_EOF_MODE_CH2: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link
+            /// descriptor when accessing internal SRAM.
+            OUTDSCR_BURST_EN_CH2: u1,
+            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting
+            /// data when accessing internal SRAM.
+            OUT_DATA_BURST_EN_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x250);
+
+        /// address: 0x6003f254
+        /// DMA_OUT_CONF1_CH2_REG.
+        pub const OUT_CONF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Set this bit to enable checking the owner attribute of the link descriptor.
+            OUT_CHECK_OWNER_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x254);
+
+        /// address: 0x6003f258
+        /// DMA_OUTFIFO_STATUS_CH2_REG.
+        pub const OUTFIFO_STATUS_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// L1 Tx FIFO full signal for Tx channel 2.
+            OUTFIFO_FULL_CH2: u1,
+            /// L1 Tx FIFO empty signal for Tx channel 2.
+            OUTFIFO_EMPTY_CH2: u1,
+            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.
+            OUTFIFO_CNT_CH2: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_1B_CH2: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_2B_CH2: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_3B_CH2: u1,
+            /// reserved
+            OUT_REMAIN_UNDER_4B_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+        }), base_address + 0x258);
+
+        /// address: 0x6003f25c
+        /// DMA_OUT_PUSH_CH2_REG.
+        pub const OUT_PUSH_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the data that need to be pushed into DMA FIFO.
+            OUTFIFO_WDATA_CH2: u9,
+            /// Set this bit to push data into DMA FIFO.
+            OUTFIFO_PUSH_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x25c);
+
+        /// address: 0x6003f260
+        /// DMA_OUT_LINK_CH2_REG.
+        pub const OUT_LINK_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the 20 least significant bits of the first outlink
+            /// descriptor's address.
+            OUTLINK_ADDR_CH2: u20,
+            /// Set this bit to stop dealing with the outlink descriptors.
+            OUTLINK_STOP_CH2: u1,
+            /// Set this bit to start dealing with the outlink descriptors.
+            OUTLINK_START_CH2: u1,
+            /// Set this bit to restart a new outlink from the last address.
+            OUTLINK_RESTART_CH2: u1,
+            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
+            /// FSM is working.
+            OUTLINK_PARK_CH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x260);
+
+        /// address: 0x6003f264
+        /// DMA_OUT_STATE_CH2_REG.
+        pub const OUT_STATE_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the current outlink descriptor's address.
+            OUTLINK_DSCR_ADDR_CH2: u18,
+            /// reserved
+            OUT_DSCR_STATE_CH2: u2,
+            /// reserved
+            OUT_STATE_CH2: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x264);
+
+        /// address: 0x6003f268
+        /// DMA_OUT_EOF_DES_ADDR_CH2_REG.
+        pub const OUT_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x268);
+
+        /// address: 0x6003f26c
+        /// DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.
+        pub const OUT_EOF_BFR_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x26c);
+
+        /// address: 0x6003f270
+        /// DMA_OUT_DSCR_CH2_REG.
+        pub const OUT_DSCR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the current outlink descriptor y.
+            OUTLINK_DSCR_CH2: u32,
+        }), base_address + 0x270);
+
+        /// address: 0x6003f274
+        /// DMA_OUT_DSCR_BF0_CH2_REG.
+        pub const OUT_DSCR_BF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the last outlink descriptor y-1.
+            OUTLINK_DSCR_BF0_CH2: u32,
+        }), base_address + 0x274);
+
+        /// address: 0x6003f278
+        /// DMA_OUT_DSCR_BF1_CH2_REG.
+        pub const OUT_DSCR_BF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The address of the second-to-last inlink descriptor x-2.
+            OUTLINK_DSCR_BF1_CH2: u32,
+        }), base_address + 0x278);
+
+        /// address: 0x6003f27c
+        /// DMA_OUT_PRI_CH2_REG.
+        pub const OUT_PRI_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The priority of Tx channel 2. The larger of the value, the higher of the
+            /// priority.
+            TX_PRI_CH2: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x27c);
+
+        /// address: 0x6003f280
+        /// DMA_OUT_PERI_SEL_CH2_REG.
+        pub const OUT_PERI_SEL_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to select peripheral for Tx channel 2. 0:SPI2. 1:
+            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
+            /// ADC_DAC.
+            PERI_OUT_SEL_CH2: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x280);
+    };
+
+    /// Digital Signature
+    pub const DS = struct {
+        pub const base_address = 0x6003d000;
+
+        /// address: 0x6003d000
+        /// memory that stores Y
+        pub const Y_MEM = @intToPtr(*volatile [512]u8, base_address + 0x0);
+
+        /// address: 0x6003d200
+        /// memory that stores M
+        pub const M_MEM = @intToPtr(*volatile [512]u8, base_address + 0x200);
+
+        /// address: 0x6003d400
+        /// memory that stores Rb
+        pub const RB_MEM = @intToPtr(*volatile [512]u8, base_address + 0x400);
+
+        /// address: 0x6003d600
+        /// memory that stores BOX
+        pub const BOX_MEM = @intToPtr(*volatile [48]u8, base_address + 0x600);
+
+        /// address: 0x6003d800
+        /// memory that stores X
+        pub const X_MEM = @intToPtr(*volatile [512]u8, base_address + 0x800);
+
+        /// address: 0x6003da00
+        /// memory that stores Z
+        pub const Z_MEM = @intToPtr(*volatile [512]u8, base_address + 0xa00);
+
+        /// address: 0x6003de00
+        /// DS start control register
+        pub const SET_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe00);
+
+        /// address: 0x6003de04
+        /// DS continue control register
+        pub const SET_CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe04);
+
+        /// address: 0x6003de08
+        /// DS finish control register
+        pub const SET_FINISH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe08);
+
+        /// address: 0x6003de0c
+        /// DS query busy register
+        pub const QUERY_BUSY = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe0c);
+
+        /// address: 0x6003de10
+        /// DS query key-wrong counter register
+        pub const QUERY_KEY_WRONG = @intToPtr(*volatile MmioInt(32, u4), base_address + 0xe10);
+
+        /// address: 0x6003de14
+        /// DS query check result register
+        pub const QUERY_CHECK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
+            MD_ERROR: u1,
+            /// padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
+            PADDING_BAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xe14);
+
+        /// address: 0x6003de20
+        /// DS version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0xe20);
+    };
+
+    /// eFuse Controller
+    pub const EFUSE = struct {
+        pub const base_address = 0x60008800;
+
+        /// address: 0x60008800
+        /// Register 0 that stores data to be programmed.
+        pub const PGM_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 0th 32-bit data to be programmed.
+            PGM_DATA_0: u32,
+        }), base_address + 0x0);
+
+        /// address: 0x60008804
+        /// Register 1 that stores data to be programmed.
+        pub const PGM_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 1st 32-bit data to be programmed.
+            PGM_DATA_1: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60008808
+        /// Register 2 that stores data to be programmed.
+        pub const PGM_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 2nd 32-bit data to be programmed.
+            PGM_DATA_2: u32,
+        }), base_address + 0x8);
+
+        /// address: 0x6000880c
+        /// Register 3 that stores data to be programmed.
+        pub const PGM_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 3rd 32-bit data to be programmed.
+            PGM_DATA_3: u32,
+        }), base_address + 0xc);
+
+        /// address: 0x60008810
+        /// Register 4 that stores data to be programmed.
+        pub const PGM_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 4th 32-bit data to be programmed.
+            PGM_DATA_4: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x60008814
+        /// Register 5 that stores data to be programmed.
+        pub const PGM_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 5th 32-bit data to be programmed.
+            PGM_DATA_5: u32,
+        }), base_address + 0x14);
+
+        /// address: 0x60008818
+        /// Register 6 that stores data to be programmed.
+        pub const PGM_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 6th 32-bit data to be programmed.
+            PGM_DATA_6: u32,
+        }), base_address + 0x18);
+
+        /// address: 0x6000881c
+        /// Register 7 that stores data to be programmed.
+        pub const PGM_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 7th 32-bit data to be programmed.
+            PGM_DATA_7: u32,
+        }), base_address + 0x1c);
+
+        /// address: 0x60008820
+        /// Register 0 that stores the RS code to be programmed.
+        pub const PGM_CHECK_VALUE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 0th 32-bit RS code to be programmed.
+            PGM_RS_DATA_0: u32,
+        }), base_address + 0x20);
+
+        /// address: 0x60008824
+        /// Register 1 that stores the RS code to be programmed.
+        pub const PGM_CHECK_VALUE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 1st 32-bit RS code to be programmed.
+            PGM_RS_DATA_1: u32,
+        }), base_address + 0x24);
+
+        /// address: 0x60008828
+        /// Register 2 that stores the RS code to be programmed.
+        pub const PGM_CHECK_VALUE2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The content of the 2nd 32-bit RS code to be programmed.
+            PGM_RS_DATA_2: u32,
+        }), base_address + 0x28);
+
+        /// address: 0x6000882c
+        /// BLOCK0 data register 0.
+        pub const RD_WR_DIS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Disable programming of individual eFuses.
+            WR_DIS: u32,
+        }), base_address + 0x2c);
+
+        /// address: 0x60008830
+        /// BLOCK0 data register 1.
+        pub const RD_REPEAT_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to disable reading from BlOCK4-10.
+            RD_DIS: u7,
+            /// Set this bit to disable boot from RTC RAM.
+            DIS_RTC_RAM_BOOT: u1,
+            /// Set this bit to disable Icache.
+            DIS_ICACHE: u1,
+            /// Set this bit to disable function of usb switch to jtag in module of usb device.
+            DIS_USB_JTAG: u1,
+            /// Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3,
+            /// 6, 7).
+            DIS_DOWNLOAD_ICACHE: u1,
+            /// Set this bit to disable usb device.
+            DIS_USB_DEVICE: u1,
+            /// Set this bit to disable the function that forces chip into download mode.
+            DIS_FORCE_DOWNLOAD: u1,
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED6: u1,
+            /// Set this bit to disable CAN function.
+            DIS_CAN: u1,
+            /// Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
+            /// strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+            JTAG_SEL_ENABLE: u1,
+            /// Set these bits to disable JTAG in the soft way (odd number 1 means disable ).
+            /// JTAG can be enabled in HMAC module.
+            SOFT_DIS_JTAG: u3,
+            /// Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+            DIS_PAD_JTAG: u1,
+            /// Set this bit to disable flash encryption when in download boot modes.
+            DIS_DOWNLOAD_MANUAL_ENCRYPT: u1,
+            /// Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV,
+            /// stored in eFuse.
+            USB_DREFH: u2,
+            /// Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
+            /// stored in eFuse.
+            USB_DREFL: u2,
+            /// Set this bit to exchange USB D+ and D- pins.
+            USB_EXCHG_PINS: u1,
+            /// Set this bit to vdd spi pin function as gpio.
+            VDD_SPI_AS_GPIO: u1,
+            /// Enable btlc gpio.
+            BTLC_GPIO_ENABLE: u2,
+            /// Set this bit to enable power glitch function.
+            POWERGLITCH_EN: u1,
+            /// Sample delay configuration of power glitch.
+            POWER_GLITCH_DSENSE: u2,
+        }), base_address + 0x30);
+
+        /// address: 0x60008834
+        /// BLOCK0 data register 2.
+        pub const RD_REPEAT_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED2: u16,
+            /// Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000.
+            /// 1: 80000. 2: 160000. 3:320000.
+            WDT_DELAY_SEL: u2,
+            /// Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
+            /// number of 1: disable.
+            SPI_BOOT_CRYPT_CNT: u3,
+            /// Set this bit to enable revoking first secure boot key.
+            SECURE_BOOT_KEY_REVOKE0: u1,
+            /// Set this bit to enable revoking second secure boot key.
+            SECURE_BOOT_KEY_REVOKE1: u1,
+            /// Set this bit to enable revoking third secure boot key.
+            SECURE_BOOT_KEY_REVOKE2: u1,
+            /// Purpose of Key0.
+            KEY_PURPOSE_0: u4,
+            /// Purpose of Key1.
+            KEY_PURPOSE_1: u4,
+        }), base_address + 0x34);
+
+        /// address: 0x60008838
+        /// BLOCK0 data register 3.
+        pub const RD_REPEAT_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Purpose of Key2.
+            KEY_PURPOSE_2: u4,
+            /// Purpose of Key3.
+            KEY_PURPOSE_3: u4,
+            /// Purpose of Key4.
+            KEY_PURPOSE_4: u4,
+            /// Purpose of Key5.
+            KEY_PURPOSE_5: u4,
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED3: u4,
+            /// Set this bit to enable secure boot.
+            SECURE_BOOT_EN: u1,
+            /// Set this bit to enable revoking aggressive secure boot.
+            SECURE_BOOT_AGGRESSIVE_REVOKE: u1,
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED0: u6,
+            /// Configures flash waiting time after power-up, in unit of ms. If the value is
+            /// less than 15, the waiting time is the configurable value; Otherwise, the waiting
+            /// time is twice the configurable value.
+            FLASH_TPUW: u4,
+        }), base_address + 0x38);
+
+        /// address: 0x6000883c
+        /// BLOCK0 data register 4.
+        pub const RD_REPEAT_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
+            DIS_DOWNLOAD_MODE: u1,
+            /// Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).
+            DIS_LEGACY_SPI_BOOT: u1,
+            /// Selectes the default UART print channel. 0: UART0. 1: UART1.
+            UART_PRINT_CHANNEL: u1,
+            /// Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
+            /// use 16to17 byte mode.
+            FLASH_ECC_MODE: u1,
+            /// Set this bit to disable UART download mode through USB.
+            DIS_USB_DOWNLOAD_MODE: u1,
+            /// Set this bit to enable secure UART download mode.
+            ENABLE_SECURITY_DOWNLOAD: u1,
+            /// Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when
+            /// GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
+            UART_PRINT_CONTROL: u2,
+            /// GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
+            PIN_POWER_SELECTION: u1,
+            /// Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
+            FLASH_TYPE: u1,
+            /// Set Flash page size.
+            FLASH_PAGE_SIZE: u2,
+            /// Set 1 to enable ECC for flash boot.
+            FLASH_ECC_EN: u1,
+            /// Set this bit to force ROM code to send a resume command during SPI boot.
+            FORCE_SEND_RESUME: u1,
+            /// Secure version (used by ESP-IDF anti-rollback feature).
+            SECURE_VERSION: u16,
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED1: u2,
+        }), base_address + 0x3c);
+
+        /// address: 0x60008840
+        /// BLOCK0 data register 5.
+        pub const RD_REPEAT_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved (used for four backups method).
+            RPT4_RESERVED4: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60008844
+        /// BLOCK1 data register 0.
+        pub const RD_MAC_SPI_SYS_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the low 32 bits of MAC address.
+            MAC_0: u32,
+        }), base_address + 0x44);
+
+        /// address: 0x60008848
+        /// BLOCK1 data register 1.
+        pub const RD_MAC_SPI_SYS_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the high 16 bits of MAC address.
+            MAC_1: u16,
+            /// Stores the zeroth part of SPI_PAD_CONF.
+            SPI_PAD_CONF_0: u16,
+        }), base_address + 0x48);
+
+        /// address: 0x6000884c
+        /// BLOCK1 data register 2.
+        pub const RD_MAC_SPI_SYS_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first part of SPI_PAD_CONF.
+            SPI_PAD_CONF_1: u32,
+        }), base_address + 0x4c);
+
+        /// address: 0x60008850
+        /// BLOCK1 data register 3.
+        pub const RD_MAC_SPI_SYS_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second part of SPI_PAD_CONF.
+            SPI_PAD_CONF_2: u18,
+            /// Stores the fist 14 bits of the zeroth part of system data.
+            SYS_DATA_PART0_0: u14,
+        }), base_address + 0x50);
+
+        /// address: 0x60008854
+        /// BLOCK1 data register 4.
+        pub const RD_MAC_SPI_SYS_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fist 32 bits of the zeroth part of system data.
+            SYS_DATA_PART0_1: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x60008858
+        /// BLOCK1 data register 5.
+        pub const RD_MAC_SPI_SYS_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of the zeroth part of system data.
+            SYS_DATA_PART0_2: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6000885c
+        /// Register 0 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of the first part of system data.
+            SYS_DATA_PART1_0: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x60008860
+        /// Register 1 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of the first part of system data.
+            SYS_DATA_PART1_1: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x60008864
+        /// Register 2 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of the first part of system data.
+            SYS_DATA_PART1_2: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x60008868
+        /// Register 3 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of the first part of system data.
+            SYS_DATA_PART1_3: u32,
+        }), base_address + 0x68);
+
+        /// address: 0x6000886c
+        /// Register 4 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of the first part of system data.
+            SYS_DATA_PART1_4: u32,
+        }), base_address + 0x6c);
+
+        /// address: 0x60008870
+        /// Register 5 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of the first part of system data.
+            SYS_DATA_PART1_5: u32,
+        }), base_address + 0x70);
+
+        /// address: 0x60008874
+        /// Register 6 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of the first part of system data.
+            SYS_DATA_PART1_6: u32,
+        }), base_address + 0x74);
+
+        /// address: 0x60008878
+        /// Register 7 of BLOCK2 (system).
+        pub const RD_SYS_PART1_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of the first part of system data.
+            SYS_DATA_PART1_7: u32,
+        }), base_address + 0x78);
+
+        /// address: 0x6000887c
+        /// Register 0 of BLOCK3 (user).
+        pub const RD_USR_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of BLOCK3 (user).
+            USR_DATA0: u32,
+        }), base_address + 0x7c);
+
+        /// address: 0x60008880
+        /// Register 1 of BLOCK3 (user).
+        pub const RD_USR_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of BLOCK3 (user).
+            USR_DATA1: u32,
+        }), base_address + 0x80);
+
+        /// address: 0x60008884
+        /// Register 2 of BLOCK3 (user).
+        pub const RD_USR_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of BLOCK3 (user).
+            USR_DATA2: u32,
+        }), base_address + 0x84);
+
+        /// address: 0x60008888
+        /// Register 3 of BLOCK3 (user).
+        pub const RD_USR_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of BLOCK3 (user).
+            USR_DATA3: u32,
+        }), base_address + 0x88);
+
+        /// address: 0x6000888c
+        /// Register 4 of BLOCK3 (user).
+        pub const RD_USR_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of BLOCK3 (user).
+            USR_DATA4: u32,
+        }), base_address + 0x8c);
+
+        /// address: 0x60008890
+        /// Register 5 of BLOCK3 (user).
+        pub const RD_USR_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of BLOCK3 (user).
+            USR_DATA5: u32,
+        }), base_address + 0x90);
+
+        /// address: 0x60008894
+        /// Register 6 of BLOCK3 (user).
+        pub const RD_USR_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of BLOCK3 (user).
+            USR_DATA6: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x60008898
+        /// Register 7 of BLOCK3 (user).
+        pub const RD_USR_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of BLOCK3 (user).
+            USR_DATA7: u32,
+        }), base_address + 0x98);
+
+        /// address: 0x6000889c
+        /// Register 0 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY0.
+            KEY0_DATA0: u32,
+        }), base_address + 0x9c);
+
+        /// address: 0x600088a0
+        /// Register 1 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY0.
+            KEY0_DATA1: u32,
+        }), base_address + 0xa0);
+
+        /// address: 0x600088a4
+        /// Register 2 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY0.
+            KEY0_DATA2: u32,
+        }), base_address + 0xa4);
+
+        /// address: 0x600088a8
+        /// Register 3 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY0.
+            KEY0_DATA3: u32,
+        }), base_address + 0xa8);
+
+        /// address: 0x600088ac
+        /// Register 4 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY0.
+            KEY0_DATA4: u32,
+        }), base_address + 0xac);
+
+        /// address: 0x600088b0
+        /// Register 5 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY0.
+            KEY0_DATA5: u32,
+        }), base_address + 0xb0);
+
+        /// address: 0x600088b4
+        /// Register 6 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY0.
+            KEY0_DATA6: u32,
+        }), base_address + 0xb4);
+
+        /// address: 0x600088b8
+        /// Register 7 of BLOCK4 (KEY0).
+        pub const RD_KEY0_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY0.
+            KEY0_DATA7: u32,
+        }), base_address + 0xb8);
+
+        /// address: 0x600088bc
+        /// Register 0 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY1.
+            KEY1_DATA0: u32,
+        }), base_address + 0xbc);
+
+        /// address: 0x600088c0
+        /// Register 1 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY1.
+            KEY1_DATA1: u32,
+        }), base_address + 0xc0);
+
+        /// address: 0x600088c4
+        /// Register 2 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY1.
+            KEY1_DATA2: u32,
+        }), base_address + 0xc4);
+
+        /// address: 0x600088c8
+        /// Register 3 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY1.
+            KEY1_DATA3: u32,
+        }), base_address + 0xc8);
+
+        /// address: 0x600088cc
+        /// Register 4 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY1.
+            KEY1_DATA4: u32,
+        }), base_address + 0xcc);
+
+        /// address: 0x600088d0
+        /// Register 5 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY1.
+            KEY1_DATA5: u32,
+        }), base_address + 0xd0);
+
+        /// address: 0x600088d4
+        /// Register 6 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY1.
+            KEY1_DATA6: u32,
+        }), base_address + 0xd4);
+
+        /// address: 0x600088d8
+        /// Register 7 of BLOCK5 (KEY1).
+        pub const RD_KEY1_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY1.
+            KEY1_DATA7: u32,
+        }), base_address + 0xd8);
+
+        /// address: 0x600088dc
+        /// Register 0 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY2.
+            KEY2_DATA0: u32,
+        }), base_address + 0xdc);
+
+        /// address: 0x600088e0
+        /// Register 1 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY2.
+            KEY2_DATA1: u32,
+        }), base_address + 0xe0);
+
+        /// address: 0x600088e4
+        /// Register 2 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY2.
+            KEY2_DATA2: u32,
+        }), base_address + 0xe4);
+
+        /// address: 0x600088e8
+        /// Register 3 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY2.
+            KEY2_DATA3: u32,
+        }), base_address + 0xe8);
+
+        /// address: 0x600088ec
+        /// Register 4 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY2.
+            KEY2_DATA4: u32,
+        }), base_address + 0xec);
+
+        /// address: 0x600088f0
+        /// Register 5 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY2.
+            KEY2_DATA5: u32,
+        }), base_address + 0xf0);
+
+        /// address: 0x600088f4
+        /// Register 6 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY2.
+            KEY2_DATA6: u32,
+        }), base_address + 0xf4);
+
+        /// address: 0x600088f8
+        /// Register 7 of BLOCK6 (KEY2).
+        pub const RD_KEY2_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY2.
+            KEY2_DATA7: u32,
+        }), base_address + 0xf8);
+
+        /// address: 0x600088fc
+        /// Register 0 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY3.
+            KEY3_DATA0: u32,
+        }), base_address + 0xfc);
+
+        /// address: 0x60008900
+        /// Register 1 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY3.
+            KEY3_DATA1: u32,
+        }), base_address + 0x100);
+
+        /// address: 0x60008904
+        /// Register 2 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY3.
+            KEY3_DATA2: u32,
+        }), base_address + 0x104);
+
+        /// address: 0x60008908
+        /// Register 3 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY3.
+            KEY3_DATA3: u32,
+        }), base_address + 0x108);
+
+        /// address: 0x6000890c
+        /// Register 4 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY3.
+            KEY3_DATA4: u32,
+        }), base_address + 0x10c);
+
+        /// address: 0x60008910
+        /// Register 5 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY3.
+            KEY3_DATA5: u32,
+        }), base_address + 0x110);
+
+        /// address: 0x60008914
+        /// Register 6 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY3.
+            KEY3_DATA6: u32,
+        }), base_address + 0x114);
+
+        /// address: 0x60008918
+        /// Register 7 of BLOCK7 (KEY3).
+        pub const RD_KEY3_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY3.
+            KEY3_DATA7: u32,
+        }), base_address + 0x118);
+
+        /// address: 0x6000891c
+        /// Register 0 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY4.
+            KEY4_DATA0: u32,
+        }), base_address + 0x11c);
+
+        /// address: 0x60008920
+        /// Register 1 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY4.
+            KEY4_DATA1: u32,
+        }), base_address + 0x120);
+
+        /// address: 0x60008924
+        /// Register 2 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY4.
+            KEY4_DATA2: u32,
+        }), base_address + 0x124);
+
+        /// address: 0x60008928
+        /// Register 3 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY4.
+            KEY4_DATA3: u32,
+        }), base_address + 0x128);
+
+        /// address: 0x6000892c
+        /// Register 4 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY4.
+            KEY4_DATA4: u32,
+        }), base_address + 0x12c);
+
+        /// address: 0x60008930
+        /// Register 5 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY4.
+            KEY4_DATA5: u32,
+        }), base_address + 0x130);
+
+        /// address: 0x60008934
+        /// Register 6 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY4.
+            KEY4_DATA6: u32,
+        }), base_address + 0x134);
+
+        /// address: 0x60008938
+        /// Register 7 of BLOCK8 (KEY4).
+        pub const RD_KEY4_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY4.
+            KEY4_DATA7: u32,
+        }), base_address + 0x138);
+
+        /// address: 0x6000893c
+        /// Register 0 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the zeroth 32 bits of KEY5.
+            KEY5_DATA0: u32,
+        }), base_address + 0x13c);
+
+        /// address: 0x60008940
+        /// Register 1 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the first 32 bits of KEY5.
+            KEY5_DATA1: u32,
+        }), base_address + 0x140);
+
+        /// address: 0x60008944
+        /// Register 2 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the second 32 bits of KEY5.
+            KEY5_DATA2: u32,
+        }), base_address + 0x144);
+
+        /// address: 0x60008948
+        /// Register 3 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the third 32 bits of KEY5.
+            KEY5_DATA3: u32,
+        }), base_address + 0x148);
+
+        /// address: 0x6000894c
+        /// Register 4 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fourth 32 bits of KEY5.
+            KEY5_DATA4: u32,
+        }), base_address + 0x14c);
+
+        /// address: 0x60008950
+        /// Register 5 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the fifth 32 bits of KEY5.
+            KEY5_DATA5: u32,
+        }), base_address + 0x150);
+
+        /// address: 0x60008954
+        /// Register 6 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the sixth 32 bits of KEY5.
+            KEY5_DATA6: u32,
+        }), base_address + 0x154);
+
+        /// address: 0x60008958
+        /// Register 7 of BLOCK9 (KEY5).
+        pub const RD_KEY5_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the seventh 32 bits of KEY5.
+            KEY5_DATA7: u32,
+        }), base_address + 0x158);
+
+        /// address: 0x6000895c
+        /// Register 0 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 0th 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_0: u32,
+        }), base_address + 0x15c);
+
+        /// address: 0x60008960
+        /// Register 1 of BLOCK9 (KEY5).
+        pub const RD_SYS_PART2_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 1st 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_1: u32,
+        }), base_address + 0x160);
+
+        /// address: 0x60008964
+        /// Register 2 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 2nd 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_2: u32,
+        }), base_address + 0x164);
+
+        /// address: 0x60008968
+        /// Register 3 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 3rd 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_3: u32,
+        }), base_address + 0x168);
+
+        /// address: 0x6000896c
+        /// Register 4 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 4th 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_4: u32,
+        }), base_address + 0x16c);
+
+        /// address: 0x60008970
+        /// Register 5 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 5th 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_5: u32,
+        }), base_address + 0x170);
+
+        /// address: 0x60008974
+        /// Register 6 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 6th 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_6: u32,
+        }), base_address + 0x174);
+
+        /// address: 0x60008978
+        /// Register 7 of BLOCK10 (system).
+        pub const RD_SYS_PART2_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the 7th 32 bits of the 2nd part of system data.
+            SYS_DATA_PART2_7: u32,
+        }), base_address + 0x178);
+
+        /// address: 0x6000897c
+        /// Programming error record register 0 of BLOCK0.
+        pub const RD_REPEAT_ERR0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// If any bit in RD_DIS is 1, then it indicates a programming error.
+            RD_DIS_ERR: u7,
+            /// If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
+            DIS_RTC_RAM_BOOT_ERR: u1,
+            /// If DIS_ICACHE is 1, then it indicates a programming error.
+            DIS_ICACHE_ERR: u1,
+            /// If DIS_USB_JTAG is 1, then it indicates a programming error.
+            DIS_USB_JTAG_ERR: u1,
+            /// If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
+            DIS_DOWNLOAD_ICACHE_ERR: u1,
+            /// If DIS_USB_DEVICE is 1, then it indicates a programming error.
+            DIS_USB_DEVICE_ERR: u1,
+            /// If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
+            DIS_FORCE_DOWNLOAD_ERR: u1,
+            /// Reserved.
+            RPT4_RESERVED6_ERR: u1,
+            /// If DIS_CAN is 1, then it indicates a programming error.
+            DIS_CAN_ERR: u1,
+            /// If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
+            JTAG_SEL_ENABLE_ERR: u1,
+            /// If SOFT_DIS_JTAG is 1, then it indicates a programming error.
+            SOFT_DIS_JTAG_ERR: u3,
+            /// If DIS_PAD_JTAG is 1, then it indicates a programming error.
+            DIS_PAD_JTAG_ERR: u1,
+            /// If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
+            DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR: u1,
+            /// If any bit in USB_DREFH is 1, then it indicates a programming error.
+            USB_DREFH_ERR: u2,
+            /// If any bit in USB_DREFL is 1, then it indicates a programming error.
+            USB_DREFL_ERR: u2,
+            /// If USB_EXCHG_PINS is 1, then it indicates a programming error.
+            USB_EXCHG_PINS_ERR: u1,
+            /// If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
+            VDD_SPI_AS_GPIO_ERR: u1,
+            /// If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
+            BTLC_GPIO_ENABLE_ERR: u2,
+            /// If POWERGLITCH_EN is 1, then it indicates a programming error.
+            POWERGLITCH_EN_ERR: u1,
+            /// If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
+            POWER_GLITCH_DSENSE_ERR: u2,
+        }), base_address + 0x17c);
+
+        /// address: 0x60008980
+        /// Programming error record register 1 of BLOCK0.
+        pub const RD_REPEAT_ERR1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            RPT4_RESERVED2_ERR: u16,
+            /// If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+            WDT_DELAY_SEL_ERR: u2,
+            /// If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
+            SPI_BOOT_CRYPT_CNT_ERR: u3,
+            /// If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
+            SECURE_BOOT_KEY_REVOKE0_ERR: u1,
+            /// If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
+            SECURE_BOOT_KEY_REVOKE1_ERR: u1,
+            /// If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
+            SECURE_BOOT_KEY_REVOKE2_ERR: u1,
+            /// If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
+            KEY_PURPOSE_0_ERR: u4,
+            /// If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
+            KEY_PURPOSE_1_ERR: u4,
+        }), base_address + 0x180);
+
+        /// address: 0x60008984
+        /// Programming error record register 2 of BLOCK0.
+        pub const RD_REPEAT_ERR2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
+            KEY_PURPOSE_2_ERR: u4,
+            /// If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
+            KEY_PURPOSE_3_ERR: u4,
+            /// If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
+            KEY_PURPOSE_4_ERR: u4,
+            /// If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
+            KEY_PURPOSE_5_ERR: u4,
+            /// Reserved.
+            RPT4_RESERVED3_ERR: u4,
+            /// If SECURE_BOOT_EN is 1, then it indicates a programming error.
+            SECURE_BOOT_EN_ERR: u1,
+            /// If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
+            SECURE_BOOT_AGGRESSIVE_REVOKE_ERR: u1,
+            /// Reserved.
+            RPT4_RESERVED0_ERR: u6,
+            /// If any bit in FLASH_TPUM is 1, then it indicates a programming error.
+            FLASH_TPUW_ERR: u4,
+        }), base_address + 0x184);
+
+        /// address: 0x60008988
+        /// Programming error record register 3 of BLOCK0.
+        pub const RD_REPEAT_ERR3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
+            DIS_DOWNLOAD_MODE_ERR: u1,
+            /// If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
+            DIS_LEGACY_SPI_BOOT_ERR: u1,
+            /// If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
+            UART_PRINT_CHANNEL_ERR: u1,
+            /// If FLASH_ECC_MODE is 1, then it indicates a programming error.
+            FLASH_ECC_MODE_ERR: u1,
+            /// If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
+            DIS_USB_DOWNLOAD_MODE_ERR: u1,
+            /// If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
+            ENABLE_SECURITY_DOWNLOAD_ERR: u1,
+            /// If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+            UART_PRINT_CONTROL_ERR: u2,
+            /// If PIN_POWER_SELECTION is 1, then it indicates a programming error.
+            PIN_POWER_SELECTION_ERR: u1,
+            /// If FLASH_TYPE is 1, then it indicates a programming error.
+            FLASH_TYPE_ERR: u1,
+            /// If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
+            FLASH_PAGE_SIZE_ERR: u2,
+            /// If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
+            FLASH_ECC_EN_ERR: u1,
+            /// If FORCE_SEND_RESUME is 1, then it indicates a programming error.
+            FORCE_SEND_RESUME_ERR: u1,
+            /// If any bit in SECURE_VERSION is 1, then it indicates a programming error.
+            SECURE_VERSION_ERR: u16,
+            /// Reserved.
+            RPT4_RESERVED1_ERR: u2,
+        }), base_address + 0x188);
+
+        /// address: 0x60008990
+        /// Programming error record register 4 of BLOCK0.
+        pub const RD_REPEAT_ERR4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            RPT4_RESERVED4_ERR: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x190);
+
+        /// address: 0x600089c0
+        /// Programming error record register 0 of BLOCK1-10.
+        pub const RD_RS_ERR0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of this signal means the number of error bytes.
+            MAC_SPI_8M_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
+            /// programming user data failed and the number of error bytes is over 6.
+            MAC_SPI_8M_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            SYS_PART1_NUM: u3,
+            /// 0: Means no failure and that the data of system part1 is reliable 1: Means that
+            /// programming user data failed and the number of error bytes is over 6.
+            SYS_PART1_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            USR_DATA_ERR_NUM: u3,
+            /// 0: Means no failure and that the user data is reliable 1: Means that programming
+            /// user data failed and the number of error bytes is over 6.
+            USR_DATA_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            KEY0_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of key0 is reliable 1: Means that
+            /// programming key0 failed and the number of error bytes is over 6.
+            KEY0_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            KEY1_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of key1 is reliable 1: Means that
+            /// programming key1 failed and the number of error bytes is over 6.
+            KEY1_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            KEY2_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of key2 is reliable 1: Means that
+            /// programming key2 failed and the number of error bytes is over 6.
+            KEY2_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            KEY3_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of key3 is reliable 1: Means that
+            /// programming key3 failed and the number of error bytes is over 6.
+            KEY3_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            KEY4_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of key4 is reliable 1: Means that
+            /// programming key4 failed and the number of error bytes is over 6.
+            KEY4_FAIL: u1,
+        }), base_address + 0x1c0);
+
+        /// address: 0x600089c4
+        /// Programming error record register 1 of BLOCK1-10.
+        pub const RD_RS_ERR1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of this signal means the number of error bytes.
+            KEY5_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of KEY5 is reliable 1: Means that
+            /// programming user data failed and the number of error bytes is over 6.
+            KEY5_FAIL: u1,
+            /// The value of this signal means the number of error bytes.
+            SYS_PART2_ERR_NUM: u3,
+            /// 0: Means no failure and that the data of system part2 is reliable 1: Means that
+            /// programming user data failed and the number of error bytes is over 6.
+            SYS_PART2_FAIL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x1c4);
+
+        /// address: 0x600089c8
+        /// eFuse clcok configuration register.
+        pub const CLK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to force eFuse SRAM into power-saving mode.
+            EFUSE_MEM_FORCE_PD: u1,
+            /// Set this bit and force to activate clock signal of eFuse SRAM.
+            MEM_CLK_FORCE_ON: u1,
+            /// Set this bit to force eFuse SRAM into working mode.
+            EFUSE_MEM_FORCE_PU: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            /// Set this bit and force to enable clock signal of eFuse memory.
+            EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x1c8);
+
+        /// address: 0x600089cc
+        /// eFuse operation mode configuraiton register;
+        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 0x5A5A: Operate programming command 0x5AA5: Operate read command.
+            OP_CODE: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x1cc);
+
+        /// address: 0x600089d0
+        /// eFuse status register.
+        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Indicates the state of the eFuse state machine.
+            STATE: u4,
+            /// The value of OTP_LOAD_SW.
+            OTP_LOAD_SW: u1,
+            /// The value of OTP_VDDQ_C_SYNC2.
+            OTP_VDDQ_C_SYNC2: u1,
+            /// The value of OTP_STROBE_SW.
+            OTP_STROBE_SW: u1,
+            /// The value of OTP_CSB_SW.
+            OTP_CSB_SW: u1,
+            /// The value of OTP_PGENB_SW.
+            OTP_PGENB_SW: u1,
+            /// The value of OTP_VDDQ_IS_SW.
+            OTP_VDDQ_IS_SW: u1,
+            /// Indicates the number of error bits during programming BLOCK0.
+            REPEAT_ERR_CNT: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x1d0);
+
+        /// address: 0x600089d4
+        /// eFuse command register.
+        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to send read command.
+            READ_CMD: u1,
+            /// Set this bit to send programming command.
+            PGM_CMD: u1,
+            /// The serial number of the block to be programmed. Value 0-10 corresponds to block
+            /// number 0-10, respectively.
+            BLK_NUM: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x1d4);
+
+        /// address: 0x600089d8
+        /// eFuse raw interrupt register.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw bit signal for read_done interrupt.
+            READ_DONE_INT_RAW: u1,
+            /// The raw bit signal for pgm_done interrupt.
+            PGM_DONE_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x1d8);
+
+        /// address: 0x600089dc
+        /// eFuse interrupt status register.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The status signal for read_done interrupt.
+            READ_DONE_INT_ST: u1,
+            /// The status signal for pgm_done interrupt.
+            PGM_DONE_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x1dc);
+
+        /// address: 0x600089e0
+        /// eFuse interrupt enable register.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The enable signal for read_done interrupt.
+            READ_DONE_INT_ENA: u1,
+            /// The enable signal for pgm_done interrupt.
+            PGM_DONE_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x1e0);
+
+        /// address: 0x600089e4
+        /// eFuse interrupt clear register.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The clear signal for read_done interrupt.
+            READ_DONE_INT_CLR: u1,
+            /// The clear signal for pgm_done interrupt.
+            PGM_DONE_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x1e4);
+
+        /// address: 0x600089e8
+        /// Controls the eFuse programming voltage.
+        pub const DAC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Controls the division factor of the rising clock of the programming voltage.
+            DAC_CLK_DIV: u8,
+            /// Don't care.
+            DAC_CLK_PAD_SEL: u1,
+            /// Controls the rising period of the programming voltage.
+            DAC_NUM: u8,
+            /// Reduces the power supply of the programming voltage.
+            OE_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x1e8);
+
+        /// address: 0x600089ec
+        /// Configures read timing parameters.
+        pub const RD_TIM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            /// Configures the initial read time of eFuse.
+            READ_INIT_NUM: u8,
+        }), base_address + 0x1ec);
+
+        /// address: 0x600089f0
+        /// Configurarion register 1 of eFuse programming timing parameters.
+        pub const WR_TIM_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// Configures the power up time for VDDQ.
+            PWR_ON_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x1f0);
+
+        /// address: 0x600089f4
+        /// Configurarion register 2 of eFuse programming timing parameters.
+        pub const WR_TIM_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Configures the power outage time for VDDQ.
+            PWR_OFF_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x1f4);
+
+        /// address: 0x600089fc
+        /// eFuse version register.
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x1fc);
+    };
+
+    /// External Memory
+    pub const EXTMEM = struct {
+        pub const base_address = 0x600c4000;
+
+        /// address: 0x600c4000
+        /// This description will be updated in the near future.
+        pub const ICACHE_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to activate the data cache. 0: disable, 1: enable
+            ICACHE_ENABLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x600c4004
+        /// This description will be updated in the near future.
+        pub const ICACHE_CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to disable core0 ibus, 0: enable, 1: disable
+            ICACHE_SHUT_IBUS: u1,
+            /// The bit is used to disable core1 ibus, 0: enable, 1: disable
+            ICACHE_SHUT_DBUS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x600c4008
+        /// This description will be updated in the near future.
+        pub const ICACHE_TAG_POWER_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to close clock gating of icache tag memory. 1: close gating, 0:
+            /// open clock gating.
+            ICACHE_TAG_MEM_FORCE_ON: u1,
+            /// The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power
+            /// down
+            ICACHE_TAG_MEM_FORCE_PD: u1,
+            /// The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up
+            ICACHE_TAG_MEM_FORCE_PU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x600c400c
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOCK_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable the first section of prelock function.
+            ICACHE_PRELOCK_SCT0_EN: u1,
+            /// The bit is used to enable the second section of prelock function.
+            ICACHE_PRELOCK_SCT1_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x600c4010
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOCK_SCT0_ADDR = @intToPtr(*volatile u32, base_address + 0x10);
+
+        /// address: 0x600c4014
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOCK_SCT1_ADDR = @intToPtr(*volatile u32, base_address + 0x14);
+
+        /// address: 0x600c4018
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOCK_SCT_SIZE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to configure the second length of data locking, which is
+            /// combined with ICACHE_PRELOCK_SCT1_ADDR_REG
+            ICACHE_PRELOCK_SCT1_SIZE: u16,
+            /// The bits are used to configure the first length of data locking, which is
+            /// combined with ICACHE_PRELOCK_SCT0_ADDR_REG
+            ICACHE_PRELOCK_SCT0_SIZE: u16,
+        }), base_address + 0x18);
+
+        /// address: 0x600c401c
+        /// This description will be updated in the near future.
+        pub const ICACHE_LOCK_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable lock operation. It will be cleared by hardware after
+            /// lock operation done.
+            ICACHE_LOCK_ENA: u1,
+            /// The bit is used to enable unlock operation. It will be cleared by hardware after
+            /// unlock operation done.
+            ICACHE_UNLOCK_ENA: u1,
+            /// The bit is used to indicate unlock/lock operation is finished.
+            ICACHE_LOCK_DONE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x600c4020
+        /// This description will be updated in the near future.
+        pub const ICACHE_LOCK_ADDR = @intToPtr(*volatile u32, base_address + 0x20);
+
+        /// address: 0x600c4024
+        /// This description will be updated in the near future.
+        pub const ICACHE_LOCK_SIZE = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24);
+
+        /// address: 0x600c4028
+        /// This description will be updated in the near future.
+        pub const ICACHE_SYNC_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable invalidate operation. It will be cleared by hardware
+            /// after invalidate operation done.
+            ICACHE_INVALIDATE_ENA: u1,
+            /// The bit is used to indicate invalidate operation is finished.
+            ICACHE_SYNC_DONE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x600c402c
+        /// This description will be updated in the near future.
+        pub const ICACHE_SYNC_ADDR = @intToPtr(*volatile u32, base_address + 0x2c);
+
+        /// address: 0x600c4030
+        /// This description will be updated in the near future.
+        pub const ICACHE_SYNC_SIZE = @intToPtr(*volatile MmioInt(32, u23), base_address + 0x30);
+
+        /// address: 0x600c4034
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOAD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable preload operation. It will be cleared by hardware
+            /// after preload operation done.
+            ICACHE_PRELOAD_ENA: u1,
+            /// The bit is used to indicate preload operation is finished.
+            ICACHE_PRELOAD_DONE: u1,
+            /// The bit is used to configure the direction of preload operation. 1: descending,
+            /// 0: ascending.
+            ICACHE_PRELOAD_ORDER: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x600c4038
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOAD_ADDR = @intToPtr(*volatile u32, base_address + 0x38);
+
+        /// address: 0x600c403c
+        /// This description will be updated in the near future.
+        pub const ICACHE_PRELOAD_SIZE = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c);
+
+        /// address: 0x600c4040
+        /// This description will be updated in the near future.
+        pub const ICACHE_AUTOLOAD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to enable the first section for autoload operation.
+            ICACHE_AUTOLOAD_SCT0_ENA: u1,
+            /// The bits are used to enable the second section for autoload operation.
+            ICACHE_AUTOLOAD_SCT1_ENA: u1,
+            /// The bit is used to enable and disable autoload operation. It is combined with
+            /// icache_autoload_done. 1: enable, 0: disable.
+            ICACHE_AUTOLOAD_ENA: u1,
+            /// The bit is used to indicate autoload operation is finished.
+            ICACHE_AUTOLOAD_DONE: u1,
+            /// The bits are used to configure the direction of autoload. 1: descending, 0:
+            /// ascending.
+            ICACHE_AUTOLOAD_ORDER: u1,
+            /// The bits are used to configure trigger conditions for autoload. 0/3: cache miss,
+            /// 1: cache hit, 2: both cache miss and hit.
+            ICACHE_AUTOLOAD_RQST: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x600c4044
+        /// This description will be updated in the near future.
+        pub const ICACHE_AUTOLOAD_SCT0_ADDR = @intToPtr(*volatile u32, base_address + 0x44);
+
+        /// address: 0x600c4048
+        /// This description will be updated in the near future.
+        pub const ICACHE_AUTOLOAD_SCT0_SIZE = @intToPtr(*volatile MmioInt(32, u27), base_address + 0x48);
+
+        /// address: 0x600c404c
+        /// This description will be updated in the near future.
+        pub const ICACHE_AUTOLOAD_SCT1_ADDR = @intToPtr(*volatile u32, base_address + 0x4c);
+
+        /// address: 0x600c4050
+        /// This description will be updated in the near future.
+        pub const ICACHE_AUTOLOAD_SCT1_SIZE = @intToPtr(*volatile MmioInt(32, u27), base_address + 0x50);
+
+        /// address: 0x600c4054
+        /// This description will be updated in the near future.
+        pub const IBUS_TO_FLASH_START_VADDR = @intToPtr(*volatile u32, base_address + 0x54);
+
+        /// address: 0x600c4058
+        /// This description will be updated in the near future.
+        pub const IBUS_TO_FLASH_END_VADDR = @intToPtr(*volatile u32, base_address + 0x58);
+
+        /// address: 0x600c405c
+        /// This description will be updated in the near future.
+        pub const DBUS_TO_FLASH_START_VADDR = @intToPtr(*volatile u32, base_address + 0x5c);
+
+        /// address: 0x600c4060
+        /// This description will be updated in the near future.
+        pub const DBUS_TO_FLASH_END_VADDR = @intToPtr(*volatile u32, base_address + 0x60);
+
+        /// address: 0x600c4064
+        /// This description will be updated in the near future.
+        pub const CACHE_ACS_CNT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to clear ibus counter.
+            IBUS_ACS_CNT_CLR: u1,
+            /// The bit is used to clear dbus counter.
+            DBUS_ACS_CNT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x600c4068
+        /// This description will be updated in the near future.
+        pub const IBUS_ACS_MISS_CNT = @intToPtr(*volatile u32, base_address + 0x68);
+
+        /// address: 0x600c406c
+        /// This description will be updated in the near future.
+        pub const IBUS_ACS_CNT = @intToPtr(*volatile u32, base_address + 0x6c);
+
+        /// address: 0x600c4070
+        /// This description will be updated in the near future.
+        pub const DBUS_ACS_FLASH_MISS_CNT = @intToPtr(*volatile u32, base_address + 0x70);
+
+        /// address: 0x600c4074
+        /// This description will be updated in the near future.
+        pub const DBUS_ACS_CNT = @intToPtr(*volatile u32, base_address + 0x74);
+
+        /// address: 0x600c4078
+        /// This description will be updated in the near future.
+        pub const CACHE_ILG_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable interrupt by sync configurations fault.
+            ICACHE_SYNC_OP_FAULT_INT_ENA: u1,
+            /// The bit is used to enable interrupt by preload configurations fault.
+            ICACHE_PRELOAD_OP_FAULT_INT_ENA: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The bit is used to enable interrupt by mmu entry fault.
+            MMU_ENTRY_FAULT_INT_ENA: u1,
+            reserved3: u1,
+            /// The bit is used to enable interrupt by ibus counter overflow.
+            IBUS_CNT_OVF_INT_ENA: u1,
+            /// The bit is used to enable interrupt by dbus counter overflow.
+            DBUS_CNT_OVF_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x600c407c
+        /// This description will be updated in the near future.
+        pub const CACHE_ILG_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to clear interrupt by sync configurations fault.
+            ICACHE_SYNC_OP_FAULT_INT_CLR: u1,
+            /// The bit is used to clear interrupt by preload configurations fault.
+            ICACHE_PRELOAD_OP_FAULT_INT_CLR: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The bit is used to clear interrupt by mmu entry fault.
+            MMU_ENTRY_FAULT_INT_CLR: u1,
+            reserved3: u1,
+            /// The bit is used to clear interrupt by ibus counter overflow.
+            IBUS_CNT_OVF_INT_CLR: u1,
+            /// The bit is used to clear interrupt by dbus counter overflow.
+            DBUS_CNT_OVF_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x600c4080
+        /// This description will be updated in the near future.
+        pub const CACHE_ILG_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to indicate interrupt by sync configurations fault.
+            ICACHE_SYNC_OP_FAULT_ST: u1,
+            /// The bit is used to indicate interrupt by preload configurations fault.
+            ICACHE_PRELOAD_OP_FAULT_ST: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The bit is used to indicate interrupt by mmu entry fault.
+            MMU_ENTRY_FAULT_ST: u1,
+            reserved3: u1,
+            /// The bit is used to indicate interrupt by ibus access flash/spiram counter
+            /// overflow.
+            IBUS_ACS_CNT_OVF_ST: u1,
+            /// The bit is used to indicate interrupt by ibus access flash/spiram miss counter
+            /// overflow.
+            IBUS_ACS_MISS_CNT_OVF_ST: u1,
+            /// The bit is used to indicate interrupt by dbus access flash/spiram counter
+            /// overflow.
+            DBUS_ACS_CNT_OVF_ST: u1,
+            /// The bit is used to indicate interrupt by dbus access flash miss counter
+            /// overflow.
+            DBUS_ACS_FLASH_MISS_CNT_OVF_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x600c4084
+        /// This description will be updated in the near future.
+        pub const CORE0_ACS_CACHE_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable interrupt by cpu access icache while the corresponding
+            /// ibus is disabled which include speculative access.
+            CORE0_IBUS_ACS_MSK_IC_INT_ENA: u1,
+            /// The bit is used to enable interrupt by ibus trying to write icache
+            CORE0_IBUS_WR_IC_INT_ENA: u1,
+            /// The bit is used to enable interrupt by authentication fail.
+            CORE0_IBUS_REJECT_INT_ENA: u1,
+            /// The bit is used to enable interrupt by cpu access icache while the corresponding
+            /// dbus is disabled which include speculative access.
+            CORE0_DBUS_ACS_MSK_IC_INT_ENA: u1,
+            /// The bit is used to enable interrupt by authentication fail.
+            CORE0_DBUS_REJECT_INT_ENA: u1,
+            /// The bit is used to enable interrupt by dbus trying to write icache
+            CORE0_DBUS_WR_IC_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x600c4088
+        /// This description will be updated in the near future.
+        pub const CORE0_ACS_CACHE_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to clear interrupt by cpu access icache while the corresponding
+            /// ibus is disabled or icache is disabled which include speculative access.
+            CORE0_IBUS_ACS_MSK_IC_INT_CLR: u1,
+            /// The bit is used to clear interrupt by ibus trying to write icache
+            CORE0_IBUS_WR_IC_INT_CLR: u1,
+            /// The bit is used to clear interrupt by authentication fail.
+            CORE0_IBUS_REJECT_INT_CLR: u1,
+            /// The bit is used to clear interrupt by cpu access icache while the corresponding
+            /// dbus is disabled or icache is disabled which include speculative access.
+            CORE0_DBUS_ACS_MSK_IC_INT_CLR: u1,
+            /// The bit is used to clear interrupt by authentication fail.
+            CORE0_DBUS_REJECT_INT_CLR: u1,
+            /// The bit is used to clear interrupt by dbus trying to write icache
+            CORE0_DBUS_WR_IC_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x600c408c
+        /// This description will be updated in the near future.
+        pub const CORE0_ACS_CACHE_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to indicate interrupt by cpu access icache while the core0_ibus
+            /// is disabled or icache is disabled which include speculative access.
+            CORE0_IBUS_ACS_MSK_ICACHE_ST: u1,
+            /// The bit is used to indicate interrupt by ibus trying to write icache
+            CORE0_IBUS_WR_ICACHE_ST: u1,
+            /// The bit is used to indicate interrupt by authentication fail.
+            CORE0_IBUS_REJECT_ST: u1,
+            /// The bit is used to indicate interrupt by cpu access icache while the core0_dbus
+            /// is disabled or icache is disabled which include speculative access.
+            CORE0_DBUS_ACS_MSK_ICACHE_ST: u1,
+            /// The bit is used to indicate interrupt by authentication fail.
+            CORE0_DBUS_REJECT_ST: u1,
+            /// The bit is used to indicate interrupt by dbus trying to write icache
+            CORE0_DBUS_WR_ICACHE_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x8c);
+
+        /// address: 0x600c4090
+        /// This description will be updated in the near future.
+        pub const CORE0_DBUS_REJECT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to indicate the attribute of CPU access dbus when
+            /// authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4:
+            /// write-able.
+            CORE0_DBUS_ATTR: u3,
+            /// The bit is used to indicate the world of CPU access dbus when authentication
+            /// fail. 0: WORLD0, 1: WORLD1
+            CORE0_DBUS_WORLD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x600c4094
+        /// This description will be updated in the near future.
+        pub const CORE0_DBUS_REJECT_VADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to indicate the virtual address of CPU access dbus when
+            /// authentication fail.
+            CORE0_DBUS_VADDR: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x600c4098
+        /// This description will be updated in the near future.
+        pub const CORE0_IBUS_REJECT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to indicate the attribute of CPU access ibus when
+            /// authentication fail. 0: invalidate, 1: execute-able, 2: read-able
+            CORE0_IBUS_ATTR: u3,
+            /// The bit is used to indicate the world of CPU access ibus when authentication
+            /// fail. 0: WORLD0, 1: WORLD1
+            CORE0_IBUS_WORLD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x600c409c
+        /// This description will be updated in the near future.
+        pub const CORE0_IBUS_REJECT_VADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to indicate the virtual address of CPU access ibus when
+            /// authentication fail.
+            CORE0_IBUS_VADDR: u32,
+        }), base_address + 0x9c);
+
+        /// address: 0x600c40a0
+        /// This description will be updated in the near future.
+        pub const CACHE_MMU_FAULT_CONTENT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bits are used to indicate the content of mmu entry which cause mmu fault..
+            CACHE_MMU_FAULT_CONTENT: u10,
+            /// The right-most 3 bits are used to indicate the operations which cause mmu fault
+            /// occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss
+            /// evict recovery address, 5: load miss evict recovery address, 6: external dma tx,
+            /// 7: external dma rx. The most significant bit is used to indicate this operation
+            /// occurs in which one icache.
+            CACHE_MMU_FAULT_CODE: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x600c40a4
+        /// This description will be updated in the near future.
+        pub const CACHE_MMU_FAULT_VADDR = @intToPtr(*volatile u32, base_address + 0xa4);
+
+        /// address: 0x600c40a8
+        /// This description will be updated in the near future.
+        pub const CACHE_WRAP_AROUND_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable wrap around mode when read data from flash.
+            CACHE_FLASH_WRAP_AROUND: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600c40ac
+        /// This description will be updated in the near future.
+        pub const CACHE_MMU_POWER_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable clock gating to save power when access mmu memory, 0:
+            /// enable, 1: disable
+            CACHE_MMU_MEM_FORCE_ON: u1,
+            /// The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down
+            CACHE_MMU_MEM_FORCE_PD: u1,
+            /// The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up
+            CACHE_MMU_MEM_FORCE_PU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600c40b0
+        /// This description will be updated in the near future.
+        pub const CACHE_STATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to indicate whether icache main fsm is in idle state or not. 1:
+            /// in idle state, 0: not in idle state
+            ICACHE_STATE: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xb0);
+
+        /// address: 0x600c40b4
+        /// This description will be updated in the near future.
+        pub const CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            RECORD_DISABLE_DB_ENCRYPT: u1,
+            /// Reserved.
+            RECORD_DISABLE_G0CB_DECRYPT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600c40b8
+        /// This description will be updated in the near future.
+        pub const CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to close clock gating of manual crypt clock. 1: close gating, 0:
+            /// open clock gating.
+            CLK_FORCE_ON_MANUAL_CRYPT: u1,
+            /// The bit is used to close clock gating of automatic crypt clock. 1: close gating,
+            /// 0: open clock gating.
+            CLK_FORCE_ON_AUTO_CRYPT: u1,
+            /// The bit is used to close clock gating of external memory encrypt and decrypt
+            /// clock. 1: close gating, 0: open clock gating.
+            CLK_FORCE_ON_CRYPT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xb8);
+
+        /// address: 0x600c40bc
+        /// This description will be updated in the near future.
+        pub const CACHE_PRELOAD_INT_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to indicate the interrupt by icache pre-load done.
+            ICACHE_PRELOAD_INT_ST: u1,
+            /// The bit is used to enable the interrupt by icache pre-load done.
+            ICACHE_PRELOAD_INT_ENA: u1,
+            /// The bit is used to clear the interrupt by icache pre-load done.
+            ICACHE_PRELOAD_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xbc);
+
+        /// address: 0x600c40c0
+        /// This description will be updated in the near future.
+        pub const CACHE_SYNC_INT_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to indicate the interrupt by icache sync done.
+            ICACHE_SYNC_INT_ST: u1,
+            /// The bit is used to enable the interrupt by icache sync done.
+            ICACHE_SYNC_INT_ENA: u1,
+            /// The bit is used to clear the interrupt by icache sync done.
+            ICACHE_SYNC_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600c40c4
+        /// This description will be updated in the near future.
+        pub const CACHE_MMU_OWNER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0xc4);
+
+        /// address: 0x600c40c8
+        /// This description will be updated in the near future.
+        pub const CACHE_CONF_MISC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to disable checking mmu entry fault by preload operation.
+            CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT: u1,
+            /// The bit is used to disable checking mmu entry fault by sync operation.
+            CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT: u1,
+            /// The bit is used to enable cache trace function.
+            CACHE_TRACE_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600c40cc
+        /// This description will be updated in the near future.
+        pub const ICACHE_FREEZE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable icache freeze mode
+            ENA: u1,
+            /// The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert
+            /// hit if CPU miss
+            MODE: u1,
+            /// The bit is used to indicate icache freeze success
+            DONE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xcc);
+
+        /// address: 0x600c40d0
+        /// This description will be updated in the near future.
+        pub const ICACHE_ATOMIC_OPERATE_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xd0);
+
+        /// address: 0x600c40d4
+        /// This description will be updated in the near future.
+        pub const CACHE_REQUEST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to disable request recording which could cause performance issue
+            BYPASS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xd4);
+
+        /// address: 0x600c40d8
+        /// This description will be updated in the near future.
+        pub const IBUS_PMS_TBL_LOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the ibus permission control section boundary0
+            IBUS_PMS_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xd8);
+
+        /// address: 0x600c40dc
+        /// This description will be updated in the near future.
+        pub const IBUS_PMS_TBL_BOUNDARY0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the ibus permission control section boundary0
+            IBUS_PMS_BOUNDARY0: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xdc);
+
+        /// address: 0x600c40e0
+        /// This description will be updated in the near future.
+        pub const IBUS_PMS_TBL_BOUNDARY1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the ibus permission control section boundary1
+            IBUS_PMS_BOUNDARY1: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xe0);
+
+        /// address: 0x600c40e4
+        /// This description will be updated in the near future.
+        pub const IBUS_PMS_TBL_BOUNDARY2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the ibus permission control section boundary2
+            IBUS_PMS_BOUNDARY2: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xe4);
+
+        /// address: 0x600c40e8
+        /// This description will be updated in the near future.
+        pub const IBUS_PMS_TBL_ATTR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure attribute of the ibus permission control section1,
+            /// bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load
+            /// in world1
+            IBUS_PMS_SCT1_ATTR: u4,
+            /// The bit is used to configure attribute of the ibus permission control section2,
+            /// bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load
+            /// in world1
+            IBUS_PMS_SCT2_ATTR: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0xe8);
+
+        /// address: 0x600c40ec
+        /// This description will be updated in the near future.
+        pub const DBUS_PMS_TBL_LOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the ibus permission control section boundary0
+            DBUS_PMS_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xec);
+
+        /// address: 0x600c40f0
+        /// This description will be updated in the near future.
+        pub const DBUS_PMS_TBL_BOUNDARY0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the dbus permission control section boundary0
+            DBUS_PMS_BOUNDARY0: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xf0);
+
+        /// address: 0x600c40f4
+        /// This description will be updated in the near future.
+        pub const DBUS_PMS_TBL_BOUNDARY1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the dbus permission control section boundary1
+            DBUS_PMS_BOUNDARY1: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xf4);
+
+        /// address: 0x600c40f8
+        /// This description will be updated in the near future.
+        pub const DBUS_PMS_TBL_BOUNDARY2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure the dbus permission control section boundary2
+            DBUS_PMS_BOUNDARY2: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xf8);
+
+        /// address: 0x600c40fc
+        /// This description will be updated in the near future.
+        pub const DBUS_PMS_TBL_ATTR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to configure attribute of the dbus permission control section1,
+            /// bit0: load in world0, bit2: load in world1
+            DBUS_PMS_SCT1_ATTR: u2,
+            /// The bit is used to configure attribute of the dbus permission control section2,
+            /// bit0: load in world0, bit2: load in world1
+            DBUS_PMS_SCT2_ATTR: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0xfc);
+
+        /// address: 0x600c4100
+        /// This description will be updated in the near future.
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// clock gate enable.
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x100);
+
+        /// address: 0x600c43fc
+        /// This description will be updated in the near future.
+        pub const REG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// version information
+            DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x3fc);
+    };
+
+    /// General Purpose Input/Output
+    pub const GPIO = struct {
+        pub const base_address = 0x60004000;
+
+        /// address: 0x60004000
+        /// GPIO bit select register
+        pub const BT_SELECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO bit select register
+            BT_SEL: u32,
+        }), base_address + 0x0);
+
+        /// address: 0x60004004
+        /// GPIO output register
+        pub const OUT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO output register for GPIO0-25
+            DATA_ORIG: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60004008
+        /// GPIO output set register
+        pub const OUT_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x8);
+
+        /// address: 0x6000400c
+        /// GPIO output clear register
+        pub const OUT_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0xc);
+
+        /// address: 0x6000401c
+        /// GPIO sdio select register
+        pub const SDIO_SELECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO sdio select register
+            SDIO_SEL: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60004020
+        /// GPIO output enable register
+        pub const ENABLE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO output enable register for GPIO0-25
+            DATA: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60004024
+        /// GPIO output enable set register
+        pub const ENABLE_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x24);
+
+        /// address: 0x60004028
+        /// GPIO output enable clear register
+        pub const ENABLE_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x28);
+
+        /// address: 0x60004038
+        /// pad strapping register
+        pub const STRAP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// pad strapping register
+            STRAPPING: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6000403c
+        /// GPIO input register
+        pub const IN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO input register for GPIO0-25
+            DATA_NEXT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60004044
+        /// GPIO interrupt status register
+        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO interrupt status register for GPIO0-25
+            INTERRUPT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60004048
+        /// GPIO interrupt status set register
+        pub const STATUS_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x48);
+
+        /// address: 0x6000404c
+        /// GPIO interrupt status clear register
+        pub const STATUS_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x4c);
+
+        /// address: 0x6000405c
+        /// GPIO PRO_CPU interrupt status register
+        pub const PCPU_INT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO PRO_CPU interrupt status register for GPIO0-25
+            PROCPU_INT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60004060
+        /// GPIO PRO_CPU(not shielded) interrupt status register
+        pub const PCPU_NMI_INT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25
+            PROCPU_NMI_INT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60004064
+        /// GPIO CPUSDIO interrupt status register
+        pub const CPUSDIO_INT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO CPUSDIO interrupt status register for GPIO0-25
+            SDIO_INT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60004074
+        /// GPIO pin configuration register
+        pub const PIN0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60004078
+        /// GPIO pin configuration register
+        pub const PIN1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6000407c
+        /// GPIO pin configuration register
+        pub const PIN2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x60004080
+        /// GPIO pin configuration register
+        pub const PIN3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x60004084
+        /// GPIO pin configuration register
+        pub const PIN4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x60004088
+        /// GPIO pin configuration register
+        pub const PIN5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x6000408c
+        /// GPIO pin configuration register
+        pub const PIN6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x8c);
+
+        /// address: 0x60004090
+        /// GPIO pin configuration register
+        pub const PIN7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x60004094
+        /// GPIO pin configuration register
+        pub const PIN8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x94);
+
+        /// address: 0x60004098
+        /// GPIO pin configuration register
+        pub const PIN9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x6000409c
+        /// GPIO pin configuration register
+        pub const PIN10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x9c);
+
+        /// address: 0x600040a0
+        /// GPIO pin configuration register
+        pub const PIN11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x600040a4
+        /// GPIO pin configuration register
+        pub const PIN12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600040a8
+        /// GPIO pin configuration register
+        pub const PIN13 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600040ac
+        /// GPIO pin configuration register
+        pub const PIN14 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600040b0
+        /// GPIO pin configuration register
+        pub const PIN15 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xb0);
+
+        /// address: 0x600040b4
+        /// GPIO pin configuration register
+        pub const PIN16 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600040b8
+        /// GPIO pin configuration register
+        pub const PIN17 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xb8);
+
+        /// address: 0x600040bc
+        /// GPIO pin configuration register
+        pub const PIN18 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xbc);
+
+        /// address: 0x600040c0
+        /// GPIO pin configuration register
+        pub const PIN19 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600040c4
+        /// GPIO pin configuration register
+        pub const PIN20 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xc4);
+
+        /// address: 0x600040c8
+        /// GPIO pin configuration register
+        pub const PIN21 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600040cc
+        /// GPIO pin configuration register
+        pub const PIN22 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xcc);
+
+        /// address: 0x600040d0
+        /// GPIO pin configuration register
+        pub const PIN23 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x600040d4
+        /// GPIO pin configuration register
+        pub const PIN24 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xd4);
+
+        /// address: 0x600040d8
+        /// GPIO pin configuration register
+        pub const PIN25 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC2_BYPASS: u2,
+            /// set this bit to select pad driver. 1:open-drain. :normal.
+            PIN_PAD_DRIVER: u1,
+            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
+            /// at posedge.
+            PIN_SYNC1_BYPASS: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
+            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
+            /// 5:valid at high level
+            PIN_INT_TYPE: u3,
+            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+            PIN_WAKEUP_ENABLE: u1,
+            /// reserved
+            PIN_CONFIG: u2,
+            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
+            /// interrupt.
+            PIN_INT_ENA: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xd8);
+
+        /// address: 0x6000414c
+        /// GPIO interrupt source register
+        pub const STATUS_NEXT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// GPIO interrupt source register for GPIO0-25
+            STATUS_INTERRUPT_NEXT: u26,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x14c);
+
+        /// address: 0x60004154
+        /// GPIO input function configuration register
+        pub const FUNC0_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x154);
+
+        /// address: 0x60004158
+        /// GPIO input function configuration register
+        pub const FUNC1_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x158);
+
+        /// address: 0x6000415c
+        /// GPIO input function configuration register
+        pub const FUNC2_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x15c);
+
+        /// address: 0x60004160
+        /// GPIO input function configuration register
+        pub const FUNC3_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x160);
+
+        /// address: 0x60004164
+        /// GPIO input function configuration register
+        pub const FUNC4_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x164);
+
+        /// address: 0x60004168
+        /// GPIO input function configuration register
+        pub const FUNC5_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x168);
+
+        /// address: 0x6000416c
+        /// GPIO input function configuration register
+        pub const FUNC6_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x16c);
+
+        /// address: 0x60004170
+        /// GPIO input function configuration register
+        pub const FUNC7_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x170);
+
+        /// address: 0x60004174
+        /// GPIO input function configuration register
+        pub const FUNC8_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x174);
+
+        /// address: 0x60004178
+        /// GPIO input function configuration register
+        pub const FUNC9_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x178);
+
+        /// address: 0x6000417c
+        /// GPIO input function configuration register
+        pub const FUNC10_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x17c);
+
+        /// address: 0x60004180
+        /// GPIO input function configuration register
+        pub const FUNC11_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x180);
+
+        /// address: 0x60004184
+        /// GPIO input function configuration register
+        pub const FUNC12_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x184);
+
+        /// address: 0x60004188
+        /// GPIO input function configuration register
+        pub const FUNC13_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x188);
+
+        /// address: 0x6000418c
+        /// GPIO input function configuration register
+        pub const FUNC14_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x18c);
+
+        /// address: 0x60004190
+        /// GPIO input function configuration register
+        pub const FUNC15_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x190);
+
+        /// address: 0x60004194
+        /// GPIO input function configuration register
+        pub const FUNC16_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x194);
+
+        /// address: 0x60004198
+        /// GPIO input function configuration register
+        pub const FUNC17_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x198);
+
+        /// address: 0x6000419c
+        /// GPIO input function configuration register
+        pub const FUNC18_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x19c);
+
+        /// address: 0x600041a0
+        /// GPIO input function configuration register
+        pub const FUNC19_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1a0);
+
+        /// address: 0x600041a4
+        /// GPIO input function configuration register
+        pub const FUNC20_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1a4);
+
+        /// address: 0x600041a8
+        /// GPIO input function configuration register
+        pub const FUNC21_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1a8);
+
+        /// address: 0x600041ac
+        /// GPIO input function configuration register
+        pub const FUNC22_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1ac);
+
+        /// address: 0x600041b0
+        /// GPIO input function configuration register
+        pub const FUNC23_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1b0);
+
+        /// address: 0x600041b4
+        /// GPIO input function configuration register
+        pub const FUNC24_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1b4);
+
+        /// address: 0x600041b8
+        /// GPIO input function configuration register
+        pub const FUNC25_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1b8);
+
+        /// address: 0x600041bc
+        /// GPIO input function configuration register
+        pub const FUNC26_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1bc);
+
+        /// address: 0x600041c0
+        /// GPIO input function configuration register
+        pub const FUNC27_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1c0);
+
+        /// address: 0x600041c4
+        /// GPIO input function configuration register
+        pub const FUNC28_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1c4);
+
+        /// address: 0x600041c8
+        /// GPIO input function configuration register
+        pub const FUNC29_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1c8);
+
+        /// address: 0x600041cc
+        /// GPIO input function configuration register
+        pub const FUNC30_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1cc);
+
+        /// address: 0x600041d0
+        /// GPIO input function configuration register
+        pub const FUNC31_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1d0);
+
+        /// address: 0x600041d4
+        /// GPIO input function configuration register
+        pub const FUNC32_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1d4);
+
+        /// address: 0x600041d8
+        /// GPIO input function configuration register
+        pub const FUNC33_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1d8);
+
+        /// address: 0x600041dc
+        /// GPIO input function configuration register
+        pub const FUNC34_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1dc);
+
+        /// address: 0x600041e0
+        /// GPIO input function configuration register
+        pub const FUNC35_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1e0);
+
+        /// address: 0x600041e4
+        /// GPIO input function configuration register
+        pub const FUNC36_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1e4);
+
+        /// address: 0x600041e8
+        /// GPIO input function configuration register
+        pub const FUNC37_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1e8);
+
+        /// address: 0x600041ec
+        /// GPIO input function configuration register
+        pub const FUNC38_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1ec);
+
+        /// address: 0x600041f0
+        /// GPIO input function configuration register
+        pub const FUNC39_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1f0);
+
+        /// address: 0x600041f4
+        /// GPIO input function configuration register
+        pub const FUNC40_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1f4);
+
+        /// address: 0x600041f8
+        /// GPIO input function configuration register
+        pub const FUNC41_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1f8);
+
+        /// address: 0x600041fc
+        /// GPIO input function configuration register
+        pub const FUNC42_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x1fc);
+
+        /// address: 0x60004200
+        /// GPIO input function configuration register
+        pub const FUNC43_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x200);
+
+        /// address: 0x60004204
+        /// GPIO input function configuration register
+        pub const FUNC44_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x204);
+
+        /// address: 0x60004208
+        /// GPIO input function configuration register
+        pub const FUNC45_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x208);
+
+        /// address: 0x6000420c
+        /// GPIO input function configuration register
+        pub const FUNC46_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x20c);
+
+        /// address: 0x60004210
+        /// GPIO input function configuration register
+        pub const FUNC47_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x210);
+
+        /// address: 0x60004214
+        /// GPIO input function configuration register
+        pub const FUNC48_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x214);
+
+        /// address: 0x60004218
+        /// GPIO input function configuration register
+        pub const FUNC49_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x218);
+
+        /// address: 0x6000421c
+        /// GPIO input function configuration register
+        pub const FUNC50_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x21c);
+
+        /// address: 0x60004220
+        /// GPIO input function configuration register
+        pub const FUNC51_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x220);
+
+        /// address: 0x60004224
+        /// GPIO input function configuration register
+        pub const FUNC52_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x224);
+
+        /// address: 0x60004228
+        /// GPIO input function configuration register
+        pub const FUNC53_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x228);
+
+        /// address: 0x6000422c
+        /// GPIO input function configuration register
+        pub const FUNC54_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x22c);
+
+        /// address: 0x60004230
+        /// GPIO input function configuration register
+        pub const FUNC55_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x230);
+
+        /// address: 0x60004234
+        /// GPIO input function configuration register
+        pub const FUNC56_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x234);
+
+        /// address: 0x60004238
+        /// GPIO input function configuration register
+        pub const FUNC57_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x238);
+
+        /// address: 0x6000423c
+        /// GPIO input function configuration register
+        pub const FUNC58_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x23c);
+
+        /// address: 0x60004240
+        /// GPIO input function configuration register
+        pub const FUNC59_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x240);
+
+        /// address: 0x60004244
+        /// GPIO input function configuration register
+        pub const FUNC60_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x244);
+
+        /// address: 0x60004248
+        /// GPIO input function configuration register
+        pub const FUNC61_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x248);
+
+        /// address: 0x6000424c
+        /// GPIO input function configuration register
+        pub const FUNC62_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x24c);
+
+        /// address: 0x60004250
+        /// GPIO input function configuration register
+        pub const FUNC63_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x250);
+
+        /// address: 0x60004254
+        /// GPIO input function configuration register
+        pub const FUNC64_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x254);
+
+        /// address: 0x60004258
+        /// GPIO input function configuration register
+        pub const FUNC65_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x258);
+
+        /// address: 0x6000425c
+        /// GPIO input function configuration register
+        pub const FUNC66_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x25c);
+
+        /// address: 0x60004260
+        /// GPIO input function configuration register
+        pub const FUNC67_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x260);
+
+        /// address: 0x60004264
+        /// GPIO input function configuration register
+        pub const FUNC68_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x264);
+
+        /// address: 0x60004268
+        /// GPIO input function configuration register
+        pub const FUNC69_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x268);
+
+        /// address: 0x6000426c
+        /// GPIO input function configuration register
+        pub const FUNC70_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x26c);
+
+        /// address: 0x60004270
+        /// GPIO input function configuration register
+        pub const FUNC71_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x270);
+
+        /// address: 0x60004274
+        /// GPIO input function configuration register
+        pub const FUNC72_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x274);
+
+        /// address: 0x60004278
+        /// GPIO input function configuration register
+        pub const FUNC73_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x278);
+
+        /// address: 0x6000427c
+        /// GPIO input function configuration register
+        pub const FUNC74_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x27c);
+
+        /// address: 0x60004280
+        /// GPIO input function configuration register
+        pub const FUNC75_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x280);
+
+        /// address: 0x60004284
+        /// GPIO input function configuration register
+        pub const FUNC76_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x284);
+
+        /// address: 0x60004288
+        /// GPIO input function configuration register
+        pub const FUNC77_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x288);
+
+        /// address: 0x6000428c
+        /// GPIO input function configuration register
+        pub const FUNC78_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x28c);
+
+        /// address: 0x60004290
+        /// GPIO input function configuration register
+        pub const FUNC79_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x290);
+
+        /// address: 0x60004294
+        /// GPIO input function configuration register
+        pub const FUNC80_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x294);
+
+        /// address: 0x60004298
+        /// GPIO input function configuration register
+        pub const FUNC81_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x298);
+
+        /// address: 0x6000429c
+        /// GPIO input function configuration register
+        pub const FUNC82_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x29c);
+
+        /// address: 0x600042a0
+        /// GPIO input function configuration register
+        pub const FUNC83_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2a0);
+
+        /// address: 0x600042a4
+        /// GPIO input function configuration register
+        pub const FUNC84_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2a4);
+
+        /// address: 0x600042a8
+        /// GPIO input function configuration register
+        pub const FUNC85_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2a8);
+
+        /// address: 0x600042ac
+        /// GPIO input function configuration register
+        pub const FUNC86_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2ac);
+
+        /// address: 0x600042b0
+        /// GPIO input function configuration register
+        pub const FUNC87_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2b0);
+
+        /// address: 0x600042b4
+        /// GPIO input function configuration register
+        pub const FUNC88_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2b4);
+
+        /// address: 0x600042b8
+        /// GPIO input function configuration register
+        pub const FUNC89_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2b8);
+
+        /// address: 0x600042bc
+        /// GPIO input function configuration register
+        pub const FUNC90_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2bc);
+
+        /// address: 0x600042c0
+        /// GPIO input function configuration register
+        pub const FUNC91_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2c0);
+
+        /// address: 0x600042c4
+        /// GPIO input function configuration register
+        pub const FUNC92_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2c4);
+
+        /// address: 0x600042c8
+        /// GPIO input function configuration register
+        pub const FUNC93_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2c8);
+
+        /// address: 0x600042cc
+        /// GPIO input function configuration register
+        pub const FUNC94_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2cc);
+
+        /// address: 0x600042d0
+        /// GPIO input function configuration register
+        pub const FUNC95_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2d0);
+
+        /// address: 0x600042d4
+        /// GPIO input function configuration register
+        pub const FUNC96_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2d4);
+
+        /// address: 0x600042d8
+        /// GPIO input function configuration register
+        pub const FUNC97_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2d8);
+
+        /// address: 0x600042dc
+        /// GPIO input function configuration register
+        pub const FUNC98_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2dc);
+
+        /// address: 0x600042e0
+        /// GPIO input function configuration register
+        pub const FUNC99_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2e0);
+
+        /// address: 0x600042e4
+        /// GPIO input function configuration register
+        pub const FUNC100_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2e4);
+
+        /// address: 0x600042e8
+        /// GPIO input function configuration register
+        pub const FUNC101_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2e8);
+
+        /// address: 0x600042ec
+        /// GPIO input function configuration register
+        pub const FUNC102_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2ec);
+
+        /// address: 0x600042f0
+        /// GPIO input function configuration register
+        pub const FUNC103_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2f0);
+
+        /// address: 0x600042f4
+        /// GPIO input function configuration register
+        pub const FUNC104_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2f4);
+
+        /// address: 0x600042f8
+        /// GPIO input function configuration register
+        pub const FUNC105_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2f8);
+
+        /// address: 0x600042fc
+        /// GPIO input function configuration register
+        pub const FUNC106_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x2fc);
+
+        /// address: 0x60004300
+        /// GPIO input function configuration register
+        pub const FUNC107_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x300);
+
+        /// address: 0x60004304
+        /// GPIO input function configuration register
+        pub const FUNC108_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x304);
+
+        /// address: 0x60004308
+        /// GPIO input function configuration register
+        pub const FUNC109_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x308);
+
+        /// address: 0x6000430c
+        /// GPIO input function configuration register
+        pub const FUNC110_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x30c);
+
+        /// address: 0x60004310
+        /// GPIO input function configuration register
+        pub const FUNC111_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x310);
+
+        /// address: 0x60004314
+        /// GPIO input function configuration register
+        pub const FUNC112_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x314);
+
+        /// address: 0x60004318
+        /// GPIO input function configuration register
+        pub const FUNC113_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x318);
+
+        /// address: 0x6000431c
+        /// GPIO input function configuration register
+        pub const FUNC114_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x31c);
+
+        /// address: 0x60004320
+        /// GPIO input function configuration register
+        pub const FUNC115_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x320);
+
+        /// address: 0x60004324
+        /// GPIO input function configuration register
+        pub const FUNC116_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x324);
+
+        /// address: 0x60004328
+        /// GPIO input function configuration register
+        pub const FUNC117_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x328);
+
+        /// address: 0x6000432c
+        /// GPIO input function configuration register
+        pub const FUNC118_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x32c);
+
+        /// address: 0x60004330
+        /// GPIO input function configuration register
+        pub const FUNC119_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x330);
+
+        /// address: 0x60004334
+        /// GPIO input function configuration register
+        pub const FUNC120_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x334);
+
+        /// address: 0x60004338
+        /// GPIO input function configuration register
+        pub const FUNC121_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x338);
+
+        /// address: 0x6000433c
+        /// GPIO input function configuration register
+        pub const FUNC122_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x33c);
+
+        /// address: 0x60004340
+        /// GPIO input function configuration register
+        pub const FUNC123_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x340);
+
+        /// address: 0x60004344
+        /// GPIO input function configuration register
+        pub const FUNC124_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x344);
+
+        /// address: 0x60004348
+        /// GPIO input function configuration register
+        pub const FUNC125_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x348);
+
+        /// address: 0x6000434c
+        /// GPIO input function configuration register
+        pub const FUNC126_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x34c);
+
+        /// address: 0x60004350
+        /// GPIO input function configuration register
+        pub const FUNC127_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
+            /// high level. s=x3C: set this port always low level.
+            IN_SEL: u5,
+            /// set this bit to invert input signal. 1:invert. :not invert.
+            IN_INV_SEL: u1,
+            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+            SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x350);
+
+        /// address: 0x60004554
+        /// GPIO output function select register
+        pub const FUNC0_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x554);
+
+        /// address: 0x60004558
+        /// GPIO output function select register
+        pub const FUNC1_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x558);
+
+        /// address: 0x6000455c
+        /// GPIO output function select register
+        pub const FUNC2_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x55c);
+
+        /// address: 0x60004560
+        /// GPIO output function select register
+        pub const FUNC3_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x560);
+
+        /// address: 0x60004564
+        /// GPIO output function select register
+        pub const FUNC4_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x564);
+
+        /// address: 0x60004568
+        /// GPIO output function select register
+        pub const FUNC5_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x568);
+
+        /// address: 0x6000456c
+        /// GPIO output function select register
+        pub const FUNC6_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x56c);
+
+        /// address: 0x60004570
+        /// GPIO output function select register
+        pub const FUNC7_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x570);
+
+        /// address: 0x60004574
+        /// GPIO output function select register
+        pub const FUNC8_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x574);
+
+        /// address: 0x60004578
+        /// GPIO output function select register
+        pub const FUNC9_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x578);
+
+        /// address: 0x6000457c
+        /// GPIO output function select register
+        pub const FUNC10_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x57c);
+
+        /// address: 0x60004580
+        /// GPIO output function select register
+        pub const FUNC11_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x580);
+
+        /// address: 0x60004584
+        /// GPIO output function select register
+        pub const FUNC12_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x584);
+
+        /// address: 0x60004588
+        /// GPIO output function select register
+        pub const FUNC13_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x588);
+
+        /// address: 0x6000458c
+        /// GPIO output function select register
+        pub const FUNC14_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x58c);
+
+        /// address: 0x60004590
+        /// GPIO output function select register
+        pub const FUNC15_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x590);
+
+        /// address: 0x60004594
+        /// GPIO output function select register
+        pub const FUNC16_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x594);
+
+        /// address: 0x60004598
+        /// GPIO output function select register
+        pub const FUNC17_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x598);
+
+        /// address: 0x6000459c
+        /// GPIO output function select register
+        pub const FUNC18_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x59c);
+
+        /// address: 0x600045a0
+        /// GPIO output function select register
+        pub const FUNC19_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5a0);
+
+        /// address: 0x600045a4
+        /// GPIO output function select register
+        pub const FUNC20_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5a4);
+
+        /// address: 0x600045a8
+        /// GPIO output function select register
+        pub const FUNC21_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5a8);
+
+        /// address: 0x600045ac
+        /// GPIO output function select register
+        pub const FUNC22_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5ac);
+
+        /// address: 0x600045b0
+        /// GPIO output function select register
+        pub const FUNC23_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5b0);
+
+        /// address: 0x600045b4
+        /// GPIO output function select register
+        pub const FUNC24_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5b4);
+
+        /// address: 0x600045b8
+        /// GPIO output function select register
+        pub const FUNC25_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
+            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
+            /// GPIO_OUT_REG[n].
+            OUT_SEL: u8,
+            /// set this bit to invert output signal.1:invert.:not invert.
+            INV_SEL: u1,
+            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
+            /// enable signal.:use peripheral output enable signal.
+            OEN_SEL: u1,
+            /// set this bit to invert output enable signal.1:invert.:not invert.
+            OEN_INV_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x5b8);
+
+        /// address: 0x6000462c
+        /// GPIO clock gate register
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this bit to enable GPIO clock gate
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x62c);
+
+        /// address: 0x600046fc
+        /// GPIO version register
+        pub const REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x6fc);
+    };
+
+    /// Sigma-Delta Modulation
+    pub const GPIOSD = struct {
+        pub const base_address = 0x60004f00;
+
+        /// address: 0x60004f00
+        /// Duty Cycle Configure Register of SDM%s
+        pub const SIGMADELTA0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This field is used to configure the duty cycle of sigma delta modulation output.
+            SD0_IN: u8,
+            /// This field is used to set a divider value to divide APB clock.
+            SD0_PRESCALE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60004f04
+        /// Duty Cycle Configure Register of SDM%s
+        pub const SIGMADELTA1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This field is used to configure the duty cycle of sigma delta modulation output.
+            SD0_IN: u8,
+            /// This field is used to set a divider value to divide APB clock.
+            SD0_PRESCALE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60004f08
+        /// Duty Cycle Configure Register of SDM%s
+        pub const SIGMADELTA2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This field is used to configure the duty cycle of sigma delta modulation output.
+            SD0_IN: u8,
+            /// This field is used to set a divider value to divide APB clock.
+            SD0_PRESCALE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x60004f0c
+        /// Duty Cycle Configure Register of SDM%s
+        pub const SIGMADELTA3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This field is used to configure the duty cycle of sigma delta modulation output.
+            SD0_IN: u8,
+            /// This field is used to set a divider value to divide APB clock.
+            SD0_PRESCALE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60004f20
+        /// Clock Gating Configure Register
+        pub const SIGMADELTA_CG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// Clock enable bit of configuration registers for sigma delta modulation.
+            CLK_EN: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60004f24
+        /// MISC Register
+        pub const SIGMADELTA_MISC = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            /// Clock enable bit of sigma delta modulation.
+            FUNCTION_CLK_EN: u1,
+            /// Reserved.
+            SPI_SWAP: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60004f28
+        /// Version Control Register
+        pub const SIGMADELTA_VERSION = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Version control register.
+            GPIO_SD_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x28);
+    };
+
+    /// HMAC (Hash-based Message Authentication Code) Accelerator
+    pub const HMAC = struct {
+        pub const base_address = 0x6003e000;
+
+        /// address: 0x6003e040
+        /// Process control register 0.
+        pub const SET_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x40);
+
+        /// address: 0x6003e044
+        /// Configure purpose.
+        pub const SET_PARA_PURPOSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set hmac parameter purpose.
+            PURPOSE_SET: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x6003e048
+        /// Configure key.
+        pub const SET_PARA_KEY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set hmac parameter key.
+            KEY_SET: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6003e04c
+        /// Finish initial configuration.
+        pub const SET_PARA_FINISH = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Finish hmac configuration.
+            SET_PARA_END: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x6003e050
+        /// Process control register 1.
+        pub const SET_MESSAGE_ONE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Call SHA to calculate one message block.
+            SET_TEXT_ONE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x6003e054
+        /// Process control register 2.
+        pub const SET_MESSAGE_ING = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Continue typical hmac.
+            SET_TEXT_ING: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x6003e058
+        /// Process control register 3.
+        pub const SET_MESSAGE_END = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Start hardware padding.
+            SET_TEXT_END: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6003e05c
+        /// Process control register 4.
+        pub const SET_RESULT_FINISH = @intToPtr(*volatile Mmio(32, packed struct {
+            /// After read result from upstream, then let hmac back to idle.
+            SET_RESULT_END: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x6003e060
+        /// Invalidate register 0.
+        pub const SET_INVALIDATE_JTAG = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x60);
+
+        /// address: 0x6003e064
+        /// Invalidate register 1.
+        pub const SET_INVALIDATE_DS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x64);
+
+        /// address: 0x6003e068
+        /// Error register.
+        pub const QUERY_ERROR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Hmac configuration state. 0: key are agree with purpose. 1: error
+            QUREY_CHECK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6003e06c
+        /// Busy register.
+        pub const QUERY_BUSY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Hmac state. 1'b0: idle. 1'b1: busy
+            BUSY_STATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x6003e080
+        /// Message block memory.
+        pub const WR_MESSAGE_MEM = @intToPtr(*volatile [64]u8, base_address + 0x80);
+
+        /// address: 0x6003e0c0
+        /// Result from upstream.
+        pub const RD_RESULT_MEM = @intToPtr(*volatile [32]u8, base_address + 0xc0);
+
+        /// address: 0x6003e0f0
+        /// Process control register 5.
+        pub const SET_MESSAGE_PAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Start software padding.
+            SET_TEXT_PAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xf0);
+
+        /// address: 0x6003e0f4
+        /// Process control register 6.
+        pub const ONE_BLOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Don't have to do padding.
+            SET_ONE_BLOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xf4);
+
+        /// address: 0x6003e0f8
+        /// Jtag register 0.
+        pub const SOFT_JTAG_CTRL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xf8);
+
+        /// address: 0x6003e0fc
+        /// Jtag register 1.
+        pub const WR_JTAG = @intToPtr(*volatile u32, base_address + 0xfc);
+    };
+
+    /// I2C (Inter-Integrated Circuit) Controller
+    pub const I2C0 = struct {
+        pub const base_address = 0x60013000;
+
+        /// address: 0x60013000
+        /// I2C_SCL_LOW_PERIOD_REG
+        pub const SCL_LOW_PERIOD = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x0);
+
+        /// address: 0x60013004
+        /// I2C_CTR_REG
+        pub const CTR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_sda_force_out
+            SDA_FORCE_OUT: u1,
+            /// reg_scl_force_out
+            SCL_FORCE_OUT: u1,
+            /// reg_sample_scl_level
+            SAMPLE_SCL_LEVEL: u1,
+            /// reg_rx_full_ack_level
+            RX_FULL_ACK_LEVEL: u1,
+            /// reg_ms_mode
+            MS_MODE: u1,
+            /// reg_trans_start
+            TRANS_START: u1,
+            /// reg_tx_lsb_first
+            TX_LSB_FIRST: u1,
+            /// reg_rx_lsb_first
+            RX_LSB_FIRST: u1,
+            /// reg_clk_en
+            CLK_EN: u1,
+            /// reg_arbitration_en
+            ARBITRATION_EN: u1,
+            /// reg_fsm_rst
+            FSM_RST: u1,
+            /// reg_conf_upgate
+            CONF_UPGATE: u1,
+            /// reg_slv_tx_auto_start_en
+            SLV_TX_AUTO_START_EN: u1,
+            /// reg_addr_10bit_rw_check_en
+            ADDR_10BIT_RW_CHECK_EN: u1,
+            /// reg_addr_broadcasting_en
+            ADDR_BROADCASTING_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60013008
+        /// I2C_SR_REG
+        pub const SR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_resp_rec
+            RESP_REC: u1,
+            /// reg_slave_rw
+            SLAVE_RW: u1,
+            reserved0: u1,
+            /// reg_arb_lost
+            ARB_LOST: u1,
+            /// reg_bus_busy
+            BUS_BUSY: u1,
+            /// reg_slave_addressed
+            SLAVE_ADDRESSED: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// reg_rxfifo_cnt
+            RXFIFO_CNT: u6,
+            /// reg_stretch_cause
+            STRETCH_CAUSE: u2,
+            reserved3: u1,
+            reserved4: u1,
+            /// reg_txfifo_cnt
+            TXFIFO_CNT: u6,
+            /// reg_scl_main_state_last
+            SCL_MAIN_STATE_LAST: u3,
+            reserved5: u1,
+            /// reg_scl_state_last
+            SCL_STATE_LAST: u3,
+            padding0: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6001300c
+        /// I2C_TO_REG
+        pub const TO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_time_out_value
+            TIME_OUT_VALUE: u5,
+            /// reg_time_out_en
+            TIME_OUT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60013010
+        /// I2C_SLAVE_ADDR_REG
+        pub const SLAVE_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_slave_addr
+            SLAVE_ADDR: u15,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            /// reg_addr_10bit_en
+            ADDR_10BIT_EN: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60013014
+        /// I2C_FIFO_ST_REG
+        pub const FIFO_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_raddr
+            RXFIFO_RADDR: u5,
+            /// reg_rxfifo_waddr
+            RXFIFO_WADDR: u5,
+            /// reg_txfifo_raddr
+            TXFIFO_RADDR: u5,
+            /// reg_txfifo_waddr
+            TXFIFO_WADDR: u5,
+            reserved0: u1,
+            reserved1: u1,
+            /// reg_slave_rw_point
+            SLAVE_RW_POINT: u8,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60013018
+        /// I2C_FIFO_CONF_REG
+        pub const FIFO_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_wm_thrhd
+            RXFIFO_WM_THRHD: u5,
+            /// reg_txfifo_wm_thrhd
+            TXFIFO_WM_THRHD: u5,
+            /// reg_nonfifo_en
+            NONFIFO_EN: u1,
+            /// reg_fifo_addr_cfg_en
+            FIFO_ADDR_CFG_EN: u1,
+            /// reg_rx_fifo_rst
+            RX_FIFO_RST: u1,
+            /// reg_tx_fifo_rst
+            TX_FIFO_RST: u1,
+            /// reg_fifo_prt_en
+            FIFO_PRT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6001301c
+        /// I2C_FIFO_DATA_REG
+        pub const DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_fifo_rdata
+            FIFO_RDATA: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60013020
+        /// I2C_INT_RAW_REG
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_wm_int_raw
+            RXFIFO_WM_INT_RAW: u1,
+            /// reg_txfifo_wm_int_raw
+            TXFIFO_WM_INT_RAW: u1,
+            /// reg_rxfifo_ovf_int_raw
+            RXFIFO_OVF_INT_RAW: u1,
+            /// reg_end_detect_int_raw
+            END_DETECT_INT_RAW: u1,
+            /// reg_byte_trans_done_int_raw
+            BYTE_TRANS_DONE_INT_RAW: u1,
+            /// reg_arbitration_lost_int_raw
+            ARBITRATION_LOST_INT_RAW: u1,
+            /// reg_mst_txfifo_udf_int_raw
+            MST_TXFIFO_UDF_INT_RAW: u1,
+            /// reg_trans_complete_int_raw
+            TRANS_COMPLETE_INT_RAW: u1,
+            /// reg_time_out_int_raw
+            TIME_OUT_INT_RAW: u1,
+            /// reg_trans_start_int_raw
+            TRANS_START_INT_RAW: u1,
+            /// reg_nack_int_raw
+            NACK_INT_RAW: u1,
+            /// reg_txfifo_ovf_int_raw
+            TXFIFO_OVF_INT_RAW: u1,
+            /// reg_rxfifo_udf_int_raw
+            RXFIFO_UDF_INT_RAW: u1,
+            /// reg_scl_st_to_int_raw
+            SCL_ST_TO_INT_RAW: u1,
+            /// reg_scl_main_st_to_int_raw
+            SCL_MAIN_ST_TO_INT_RAW: u1,
+            /// reg_det_start_int_raw
+            DET_START_INT_RAW: u1,
+            /// reg_slave_stretch_int_raw
+            SLAVE_STRETCH_INT_RAW: u1,
+            /// reg_general_call_int_raw
+            GENERAL_CALL_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60013024
+        /// I2C_INT_CLR_REG
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_wm_int_clr
+            RXFIFO_WM_INT_CLR: u1,
+            /// reg_txfifo_wm_int_clr
+            TXFIFO_WM_INT_CLR: u1,
+            /// reg_rxfifo_ovf_int_clr
+            RXFIFO_OVF_INT_CLR: u1,
+            /// reg_end_detect_int_clr
+            END_DETECT_INT_CLR: u1,
+            /// reg_byte_trans_done_int_clr
+            BYTE_TRANS_DONE_INT_CLR: u1,
+            /// reg_arbitration_lost_int_clr
+            ARBITRATION_LOST_INT_CLR: u1,
+            /// reg_mst_txfifo_udf_int_clr
+            MST_TXFIFO_UDF_INT_CLR: u1,
+            /// reg_trans_complete_int_clr
+            TRANS_COMPLETE_INT_CLR: u1,
+            /// reg_time_out_int_clr
+            TIME_OUT_INT_CLR: u1,
+            /// reg_trans_start_int_clr
+            TRANS_START_INT_CLR: u1,
+            /// reg_nack_int_clr
+            NACK_INT_CLR: u1,
+            /// reg_txfifo_ovf_int_clr
+            TXFIFO_OVF_INT_CLR: u1,
+            /// reg_rxfifo_udf_int_clr
+            RXFIFO_UDF_INT_CLR: u1,
+            /// reg_scl_st_to_int_clr
+            SCL_ST_TO_INT_CLR: u1,
+            /// reg_scl_main_st_to_int_clr
+            SCL_MAIN_ST_TO_INT_CLR: u1,
+            /// reg_det_start_int_clr
+            DET_START_INT_CLR: u1,
+            /// reg_slave_stretch_int_clr
+            SLAVE_STRETCH_INT_CLR: u1,
+            /// reg_general_call_int_clr
+            GENERAL_CALL_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60013028
+        /// I2C_INT_ENA_REG
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_wm_int_ena
+            RXFIFO_WM_INT_ENA: u1,
+            /// reg_txfifo_wm_int_ena
+            TXFIFO_WM_INT_ENA: u1,
+            /// reg_rxfifo_ovf_int_ena
+            RXFIFO_OVF_INT_ENA: u1,
+            /// reg_end_detect_int_ena
+            END_DETECT_INT_ENA: u1,
+            /// reg_byte_trans_done_int_ena
+            BYTE_TRANS_DONE_INT_ENA: u1,
+            /// reg_arbitration_lost_int_ena
+            ARBITRATION_LOST_INT_ENA: u1,
+            /// reg_mst_txfifo_udf_int_ena
+            MST_TXFIFO_UDF_INT_ENA: u1,
+            /// reg_trans_complete_int_ena
+            TRANS_COMPLETE_INT_ENA: u1,
+            /// reg_time_out_int_ena
+            TIME_OUT_INT_ENA: u1,
+            /// reg_trans_start_int_ena
+            TRANS_START_INT_ENA: u1,
+            /// reg_nack_int_ena
+            NACK_INT_ENA: u1,
+            /// reg_txfifo_ovf_int_ena
+            TXFIFO_OVF_INT_ENA: u1,
+            /// reg_rxfifo_udf_int_ena
+            RXFIFO_UDF_INT_ENA: u1,
+            /// reg_scl_st_to_int_ena
+            SCL_ST_TO_INT_ENA: u1,
+            /// reg_scl_main_st_to_int_ena
+            SCL_MAIN_ST_TO_INT_ENA: u1,
+            /// reg_det_start_int_ena
+            DET_START_INT_ENA: u1,
+            /// reg_slave_stretch_int_ena
+            SLAVE_STRETCH_INT_ENA: u1,
+            /// reg_general_call_int_ena
+            GENERAL_CALL_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6001302c
+        /// I2C_INT_STATUS_REG
+        pub const INT_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rxfifo_wm_int_st
+            RXFIFO_WM_INT_ST: u1,
+            /// reg_txfifo_wm_int_st
+            TXFIFO_WM_INT_ST: u1,
+            /// reg_rxfifo_ovf_int_st
+            RXFIFO_OVF_INT_ST: u1,
+            /// reg_end_detect_int_st
+            END_DETECT_INT_ST: u1,
+            /// reg_byte_trans_done_int_st
+            BYTE_TRANS_DONE_INT_ST: u1,
+            /// reg_arbitration_lost_int_st
+            ARBITRATION_LOST_INT_ST: u1,
+            /// reg_mst_txfifo_udf_int_st
+            MST_TXFIFO_UDF_INT_ST: u1,
+            /// reg_trans_complete_int_st
+            TRANS_COMPLETE_INT_ST: u1,
+            /// reg_time_out_int_st
+            TIME_OUT_INT_ST: u1,
+            /// reg_trans_start_int_st
+            TRANS_START_INT_ST: u1,
+            /// reg_nack_int_st
+            NACK_INT_ST: u1,
+            /// reg_txfifo_ovf_int_st
+            TXFIFO_OVF_INT_ST: u1,
+            /// reg_rxfifo_udf_int_st
+            RXFIFO_UDF_INT_ST: u1,
+            /// reg_scl_st_to_int_st
+            SCL_ST_TO_INT_ST: u1,
+            /// reg_scl_main_st_to_int_st
+            SCL_MAIN_ST_TO_INT_ST: u1,
+            /// reg_det_start_int_st
+            DET_START_INT_ST: u1,
+            /// reg_slave_stretch_int_st
+            SLAVE_STRETCH_INT_ST: u1,
+            /// reg_general_call_int_st
+            GENERAL_CALL_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60013030
+        /// I2C_SDA_HOLD_REG
+        pub const SDA_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_sda_hold_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60013034
+        /// I2C_SDA_SAMPLE_REG
+        pub const SDA_SAMPLE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_sda_sample_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60013038
+        /// I2C_SCL_HIGH_PERIOD_REG
+        pub const SCL_HIGH_PERIOD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_high_period
+            SCL_HIGH_PERIOD: u9,
+            /// reg_scl_wait_high_period
+            SCL_WAIT_HIGH_PERIOD: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x60013040
+        /// I2C_SCL_START_HOLD_REG
+        pub const SCL_START_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_start_hold_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60013044
+        /// I2C_SCL_RSTART_SETUP_REG
+        pub const SCL_RSTART_SETUP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_rstart_setup_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60013048
+        /// I2C_SCL_STOP_HOLD_REG
+        pub const SCL_STOP_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_stop_hold_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6001304c
+        /// I2C_SCL_STOP_SETUP_REG
+        pub const SCL_STOP_SETUP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_stop_setup_time
+            TIME: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60013050
+        /// I2C_FILTER_CFG_REG
+        pub const FILTER_CFG = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_filter_thres
+            SCL_FILTER_THRES: u4,
+            /// reg_sda_filter_thres
+            SDA_FILTER_THRES: u4,
+            /// reg_scl_filter_en
+            SCL_FILTER_EN: u1,
+            /// reg_sda_filter_en
+            SDA_FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60013054
+        /// I2C_CLK_CONF_REG
+        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_sclk_div_num
+            SCLK_DIV_NUM: u8,
+            /// reg_sclk_div_a
+            SCLK_DIV_A: u6,
+            /// reg_sclk_div_b
+            SCLK_DIV_B: u6,
+            /// reg_sclk_sel
+            SCLK_SEL: u1,
+            /// reg_sclk_active
+            SCLK_ACTIVE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60013058
+        /// I2C_COMD%s_REG
+        pub const COMD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6001305c
+        /// I2C_COMD%s_REG
+        pub const COMD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60013060
+        /// I2C_COMD%s_REG
+        pub const COMD2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60013064
+        /// I2C_COMD%s_REG
+        pub const COMD3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60013068
+        /// I2C_COMD%s_REG
+        pub const COMD4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6001306c
+        /// I2C_COMD%s_REG
+        pub const COMD5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60013070
+        /// I2C_COMD%s_REG
+        pub const COMD6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60013074
+        /// I2C_COMD%s_REG
+        pub const COMD7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_command
+            COMMAND: u14,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            /// reg_command_done
+            COMMAND_DONE: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60013078
+        /// I2C_SCL_ST_TIME_OUT_REG
+        pub const SCL_ST_TIME_OUT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_st_to_regno more than 23
+            SCL_ST_TO_I2C: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6001307c
+        /// I2C_SCL_MAIN_ST_TIME_OUT_REG
+        pub const SCL_MAIN_ST_TIME_OUT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_main_st_to_regno more than 23
+            SCL_MAIN_ST_TO_I2C: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x60013080
+        /// I2C_SCL_SP_CONF_REG
+        pub const SCL_SP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_scl_rst_slv_en
+            SCL_RST_SLV_EN: u1,
+            /// reg_scl_rst_slv_num
+            SCL_RST_SLV_NUM: u5,
+            /// reg_scl_pd_en
+            SCL_PD_EN: u1,
+            /// reg_sda_pd_en
+            SDA_PD_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x60013084
+        /// I2C_SCL_STRETCH_CONF_REG
+        pub const SCL_STRETCH_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_stretch_protect_num
+            STRETCH_PROTECT_NUM: u10,
+            /// reg_slave_scl_stretch_en
+            SLAVE_SCL_STRETCH_EN: u1,
+            /// reg_slave_scl_stretch_clr
+            SLAVE_SCL_STRETCH_CLR: u1,
+            /// reg_slave_byte_ack_ctl_en
+            SLAVE_BYTE_ACK_CTL_EN: u1,
+            /// reg_slave_byte_ack_lvl
+            SLAVE_BYTE_ACK_LVL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x600130f8
+        /// I2C_DATE_REG
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0xf8);
+
+        /// address: 0x60013100
+        /// I2C_TXFIFO_START_ADDR_REG
+        pub const TXFIFO_START_ADDR = @intToPtr(*volatile u32, base_address + 0x100);
+
+        /// address: 0x60013180
+        /// I2C_RXFIFO_START_ADDR_REG
+        pub const RXFIFO_START_ADDR = @intToPtr(*volatile u32, base_address + 0x180);
+    };
+
+    /// I2S (Inter-IC Sound) Controller
+    pub const I2S = struct {
+        pub const base_address = 0x6002d000;
+
+        /// address: 0x6002d00c
+        /// I2S interrupt raw register, valid in level.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt status bit for the i2s_rx_done_int interrupt
+            RX_DONE_INT_RAW: u1,
+            /// The raw interrupt status bit for the i2s_tx_done_int interrupt
+            TX_DONE_INT_RAW: u1,
+            /// The raw interrupt status bit for the i2s_rx_hung_int interrupt
+            RX_HUNG_INT_RAW: u1,
+            /// The raw interrupt status bit for the i2s_tx_hung_int interrupt
+            TX_HUNG_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x6002d010
+        /// I2S interrupt status register.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The masked interrupt status bit for the i2s_rx_done_int interrupt
+            RX_DONE_INT_ST: u1,
+            /// The masked interrupt status bit for the i2s_tx_done_int interrupt
+            TX_DONE_INT_ST: u1,
+            /// The masked interrupt status bit for the i2s_rx_hung_int interrupt
+            RX_HUNG_INT_ST: u1,
+            /// The masked interrupt status bit for the i2s_tx_hung_int interrupt
+            TX_HUNG_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x6002d014
+        /// I2S interrupt enable register.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The interrupt enable bit for the i2s_rx_done_int interrupt
+            RX_DONE_INT_ENA: u1,
+            /// The interrupt enable bit for the i2s_tx_done_int interrupt
+            TX_DONE_INT_ENA: u1,
+            /// The interrupt enable bit for the i2s_rx_hung_int interrupt
+            RX_HUNG_INT_ENA: u1,
+            /// The interrupt enable bit for the i2s_tx_hung_int interrupt
+            TX_HUNG_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x6002d018
+        /// I2S interrupt clear register.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the i2s_rx_done_int interrupt
+            RX_DONE_INT_CLR: u1,
+            /// Set this bit to clear the i2s_tx_done_int interrupt
+            TX_DONE_INT_CLR: u1,
+            /// Set this bit to clear the i2s_rx_hung_int interrupt
+            RX_HUNG_INT_CLR: u1,
+            /// Set this bit to clear the i2s_tx_hung_int interrupt
+            TX_HUNG_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6002d020
+        /// I2S RX configure register
+        pub const RX_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to reset receiver
+            RX_RESET: u1,
+            /// Set this bit to reset Rx AFIFO
+            RX_FIFO_RESET: u1,
+            /// Set this bit to start receiving data
+            RX_START: u1,
+            /// Set this bit to enable slave receiver mode
+            RX_SLAVE_MOD: u1,
+            reserved0: u1,
+            /// Set this bit to enable receiver in mono mode
+            RX_MONO: u1,
+            reserved1: u1,
+            /// I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr
+            /// value.
+            RX_BIG_ENDIAN: u1,
+            /// Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain.
+            /// This bit will be cleared by hardware after update register done.
+            RX_UPDATE: u1,
+            /// 1: The first channel data value is valid in I2S RX mono mode. 0: The second
+            /// channel data value is valid in I2S RX mono mode.
+            RX_MONO_FST_VLD: u1,
+            /// I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+            /// (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress.
+            /// &
+            RX_PCM_CONF: u2,
+            /// Set this bit to bypass Compress/Decompress module for received data.
+            RX_PCM_BYPASS: u1,
+            /// 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is
+            /// 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+            RX_STOP_MODE: u2,
+            /// 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+            RX_LEFT_ALIGN: u1,
+            /// 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+            RX_24_FILL_EN: u1,
+            /// 0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
+            /// 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+            RX_WS_IDLE_POL: u1,
+            /// I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the
+            /// MSB is received first.
+            RX_BIT_ORDER: u1,
+            /// 1: Enable I2S TDM Rx mode . 0: Disable.
+            RX_TDM_EN: u1,
+            /// 1: Enable I2S PDM Rx mode . 0: Disable.
+            RX_PDM_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x6002d024
+        /// I2S TX configure register
+        pub const TX_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to reset transmitter
+            TX_RESET: u1,
+            /// Set this bit to reset Tx AFIFO
+            TX_FIFO_RESET: u1,
+            /// Set this bit to start transmitting data
+            TX_START: u1,
+            /// Set this bit to enable slave transmitter mode
+            TX_SLAVE_MOD: u1,
+            reserved0: u1,
+            /// Set this bit to enable transmitter in mono mode
+            TX_MONO: u1,
+            /// 1: The value of Left channel data is equal to the value of right channel data in
+            /// I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
+            /// reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+            TX_CHAN_EQUAL: u1,
+            /// I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr
+            /// value.
+            TX_BIG_ENDIAN: u1,
+            /// Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain.
+            /// This bit will be cleared by hardware after update register done.
+            TX_UPDATE: u1,
+            /// 1: The first channel data value is valid in I2S TX mono mode. 0: The second
+            /// channel data value is valid in I2S TX mono mode.
+            TX_MONO_FST_VLD: u1,
+            /// I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
+            /// (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress.
+            /// &
+            TX_PCM_CONF: u2,
+            /// Set this bit to bypass Compress/Decompress module for transmitted data.
+            TX_PCM_BYPASS: u1,
+            /// Set this bit to stop disable output BCK signal and WS signal when tx FIFO is
+            /// emtpy
+            TX_STOP_EN: u1,
+            reserved1: u1,
+            /// 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+            TX_LEFT_ALIGN: u1,
+            /// 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+            TX_24_FILL_EN: u1,
+            /// 0: WS should be 0 when sending left channel data, and WS is 1in right channel.
+            /// 1: WS should be 1 when sending left channel data, and WS is 0in right channel.
+            TX_WS_IDLE_POL: u1,
+            /// I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB
+            /// is sent first.
+            TX_BIT_ORDER: u1,
+            /// 1: Enable I2S TDM Tx mode . 0: Disable.
+            TX_TDM_EN: u1,
+            /// 1: Enable I2S PDM Tx mode . 0: Disable.
+            TX_PDM_EN: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            /// I2S transmitter channel mode configuration bits.
+            TX_CHAN_MOD: u3,
+            /// Enable signal loop back mode with transmitter module and receiver module sharing
+            /// the same WS and BCK signals.
+            SIG_LOOPBACK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x6002d028
+        /// I2S RX configure register 1
+        pub const RX_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
+            RX_TDM_WS_WIDTH: u7,
+            /// Bit clock configuration bits in receiver mode.
+            RX_BCK_DIV_NUM: u6,
+            /// Set the bits to configure the valid data bit length of I2S receiver channel. 7:
+            /// all the valid channel data is in 8-bit-mode. 15: all the valid channel data is
+            /// in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the
+            /// valid channel data is in 32-bit-mode.
+            RX_BITS_MOD: u5,
+            /// I2S Rx half sample bits -1.
+            RX_HALF_SAMPLE_BITS: u6,
+            /// The Rx bit number for each channel minus 1in TDM mode.
+            RX_TDM_CHAN_BITS: u5,
+            /// Set this bit to enable receiver in Phillips standard mode
+            RX_MSB_SHIFT: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6002d02c
+        /// I2S TX configure register 1
+        pub const TX_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
+            TX_TDM_WS_WIDTH: u7,
+            /// Bit clock configuration bits in transmitter mode.
+            TX_BCK_DIV_NUM: u6,
+            /// Set the bits to configure the valid data bit length of I2S transmitter channel.
+            /// 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data
+            /// is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the
+            /// valid channel data is in 32-bit-mode.
+            TX_BITS_MOD: u5,
+            /// I2S Tx half sample bits -1.
+            TX_HALF_SAMPLE_BITS: u6,
+            /// The Tx bit number for each channel minus 1in TDM mode.
+            TX_TDM_CHAN_BITS: u5,
+            /// Set this bit to enable transmitter in Phillips standard mode
+            TX_MSB_SHIFT: u1,
+            /// 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed
+            /// to generate pos/neg edge in master mode.
+            TX_BCK_NO_DLY: u1,
+            padding0: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x6002d030
+        /// I2S RX clock configure register
+        pub const RX_CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Integral I2S clock divider value
+            RX_CLKM_DIV_NUM: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// I2S Rx module clock enable signal.
+            RX_CLK_ACTIVE: u1,
+            /// Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3:
+            /// I2S_MCLK_in.
+            RX_CLK_SEL: u2,
+            /// 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as
+            /// I2S_MCLK_OUT.
+            MCLK_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x6002d034
+        /// I2S TX clock configure register
+        pub const TX_CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will
+            /// be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <=
+            /// a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
+            /// (n+1)-div] + y * (n+1)-div.
+            TX_CLKM_DIV_NUM: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// I2S Tx module clock enable signal.
+            TX_CLK_ACTIVE: u1,
+            /// Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
+            /// I2S_MCLK_in.
+            TX_CLK_SEL: u2,
+            /// Set this bit to enable clk gate
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x6002d038
+        /// I2S RX module clock divider configure register
+        pub const RX_CLKM_DIV_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
+            /// I2S_RX_CLKM_DIV_Z is (a-b).
+            RX_CLKM_DIV_Z: u9,
+            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value
+            /// of I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+            RX_CLKM_DIV_Y: u9,
+            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the
+            /// value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+            RX_CLKM_DIV_X: u9,
+            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+            /// I2S_RX_CLKM_DIV_YN1 is 1.
+            RX_CLKM_DIV_YN1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6002d03c
+        /// I2S TX module clock divider configure register
+        pub const TX_CLKM_DIV_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
+            /// I2S_TX_CLKM_DIV_Z is (a-b).
+            TX_CLKM_DIV_Z: u9,
+            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value
+            /// of I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+            TX_CLKM_DIV_Y: u9,
+            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the
+            /// value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+            TX_CLKM_DIV_X: u9,
+            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
+            /// I2S_TX_CLKM_DIV_YN1 is 1.
+            TX_CLKM_DIV_YN1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x6002d040
+        /// I2S TX PCM2PDM configuration register
+        pub const TX_PCM2PDM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// I2S TX PDM bypass hp filter or not. The option has been removed.
+            TX_PDM_HP_BYPASS: u1,
+            /// I2S TX PDM OSR2 value
+            TX_PDM_SINC_OSR2: u4,
+            /// I2S TX PDM prescale for sigmadelta
+            TX_PDM_PRESCALE: u8,
+            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+            TX_PDM_HP_IN_SHIFT: u2,
+            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+            TX_PDM_LP_IN_SHIFT: u2,
+            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+            TX_PDM_SINC_IN_SHIFT: u2,
+            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+            TX_PDM_SIGMADELTA_IN_SHIFT: u2,
+            /// I2S TX PDM sigmadelta dither2 value
+            TX_PDM_SIGMADELTA_DITHER2: u1,
+            /// I2S TX PDM sigmadelta dither value
+            TX_PDM_SIGMADELTA_DITHER: u1,
+            /// I2S TX PDM dac mode enable
+            TX_PDM_DAC_2OUT_EN: u1,
+            /// I2S TX PDM dac 2channel enable
+            TX_PDM_DAC_MODE_EN: u1,
+            /// I2S TX PDM Converter enable
+            PCM2PDM_CONV_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x6002d044
+        /// I2S TX PCM2PDM configuration register
+        pub const TX_PCM2PDM_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// I2S TX PDM Fp
+            TX_PDM_FP: u10,
+            /// I2S TX PDM Fs
+            TX_PDM_FS: u10,
+            /// The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
+            /// I2S_TX_IIR_HP_MULT12_5[2:0])
+            TX_IIR_HP_MULT12_5: u3,
+            /// The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
+            /// I2S_TX_IIR_HP_MULT12_0[2:0])
+            TX_IIR_HP_MULT12_0: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x6002d050
+        /// I2S TX TDM mode control register
+        pub const RX_TDM_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN0_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN1_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN2_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN3_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN4_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN5_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN6_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just
+            /// input 0 in this channel.
+            RX_TDM_PDM_CHAN7_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0
+            /// in this channel.
+            RX_TDM_CHAN8_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0
+            /// in this channel.
+            RX_TDM_CHAN9_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN10_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN11_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN12_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN13_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN14_EN: u1,
+            /// 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input
+            /// 0 in this channel.
+            RX_TDM_CHAN15_EN: u1,
+            /// The total channel number of I2S TX TDM mode.
+            RX_TDM_TOT_CHAN_NUM: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x6002d054
+        /// I2S TX TDM mode control register
+        pub const TX_TDM_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN0_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN1_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN2_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN3_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN4_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN5_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN6_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN7_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN8_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output
+            /// 0 in this channel.
+            TX_TDM_CHAN9_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN10_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN11_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN12_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN13_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN14_EN: u1,
+            /// 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just
+            /// output 0 in this channel.
+            TX_TDM_CHAN15_EN: u1,
+            /// The total channel number of I2S TX TDM mode.
+            TX_TDM_TOT_CHAN_NUM: u4,
+            /// When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels,
+            /// and only the data of the enabled channels is sent, then this bit should be set.
+            /// Clear it when all the data stored in DMA TX buffer is for enabled channels.
+            TX_TDM_SKIP_MSK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x6002d058
+        /// I2S RX timing control register
+        pub const RX_TIMING = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            RX_SD_IN_DM: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            RX_WS_OUT_DM: u2,
+            reserved14: u1,
+            reserved15: u1,
+            /// The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            RX_BCK_OUT_DM: u2,
+            reserved16: u1,
+            reserved17: u1,
+            /// The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            RX_WS_IN_DM: u2,
+            reserved18: u1,
+            reserved19: u1,
+            /// The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            RX_BCK_IN_DM: u2,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6002d05c
+        /// I2S TX timing control register
+        pub const TX_TIMING = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_SD_OUT_DM: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_SD1_OUT_DM: u2,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_WS_OUT_DM: u2,
+            reserved12: u1,
+            reserved13: u1,
+            /// The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_BCK_OUT_DM: u2,
+            reserved14: u1,
+            reserved15: u1,
+            /// The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_WS_IN_DM: u2,
+            reserved16: u1,
+            reserved17: u1,
+            /// The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2:
+            /// delay by neg edge. 3: not used.
+            TX_BCK_IN_DM: u2,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x6002d060
+        /// I2S HUNG configure register.
+        pub const LC_HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
+            /// when fifo hung counter is equal to this value
+            LC_FIFO_TIMEOUT: u8,
+            /// The bits are used to scale tick counter threshold. The tick counter is reset
+            /// when counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+            LC_FIFO_TIMEOUT_SHIFT: u3,
+            /// The enable bit for FIFO timeout
+            LC_FIFO_TIMEOUT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x6002d064
+        /// I2S RX data number control register.
+        pub const RXEOF_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) *
+            /// (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the
+            /// configured DMA RX channel.
+            RX_EOF_NUM: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x6002d068
+        /// I2S signal data register
+        pub const CONF_SIGLE_DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The configured constant channel data to be sent out.
+            SINGLE_DATA: u32,
+        }), base_address + 0x68);
+
+        /// address: 0x6002d06c
+        /// I2S TX status register
+        pub const STATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: i2s_tx is idle state. 0: i2s_tx is working.
+            TX_IDLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x6002d080
+        /// Version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x80);
+    };
+
+    /// Interrupt Core
+    pub const INTERRUPT_CORE0 = struct {
+        pub const base_address = 0x600c2000;
+
+        /// address: 0x600c2000
+        /// mac intr map register
+        pub const MAC_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x0);
+
+        /// address: 0x600c2004
+        /// mac nmi_intr map register
+        pub const MAC_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x4);
+
+        /// address: 0x600c2008
+        /// pwr intr map register
+        pub const PWR_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x8);
+
+        /// address: 0x600c200c
+        /// bb intr map register
+        pub const BB_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc);
+
+        /// address: 0x600c2010
+        /// bt intr map register
+        pub const BT_MAC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x10);
+
+        /// address: 0x600c2014
+        /// bb_bt intr map register
+        pub const BT_BB_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x14);
+
+        /// address: 0x600c2018
+        /// bb_bt_nmi intr map register
+        pub const BT_BB_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x18);
+
+        /// address: 0x600c201c
+        /// rwbt intr map register
+        pub const RWBT_IRQ_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x1c);
+
+        /// address: 0x600c2020
+        /// rwble intr map register
+        pub const RWBLE_IRQ_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x20);
+
+        /// address: 0x600c2024
+        /// rwbt_nmi intr map register
+        pub const RWBT_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x24);
+
+        /// address: 0x600c2028
+        /// rwble_nmi intr map register
+        pub const RWBLE_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x28);
+
+        /// address: 0x600c202c
+        /// i2c intr map register
+        pub const I2C_MST_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x2c);
+
+        /// address: 0x600c2030
+        /// slc0 intr map register
+        pub const SLC0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x30);
+
+        /// address: 0x600c2034
+        /// slc1 intr map register
+        pub const SLC1_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x34);
+
+        /// address: 0x600c2038
+        /// apb_ctrl intr map register
+        pub const APB_CTRL_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x38);
+
+        /// address: 0x600c203c
+        /// uchi0 intr map register
+        pub const UHCI0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x3c);
+
+        /// address: 0x600c2040
+        /// gpio intr map register
+        pub const GPIO_INTERRUPT_PRO_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x40);
+
+        /// address: 0x600c2044
+        /// gpio_pro intr map register
+        pub const GPIO_INTERRUPT_PRO_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x44);
+
+        /// address: 0x600c2048
+        /// gpio_pro_nmi intr map register
+        pub const SPI_INTR_1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x48);
+
+        /// address: 0x600c204c
+        /// spi1 intr map register
+        pub const SPI_INTR_2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x4c);
+
+        /// address: 0x600c2050
+        /// spi2 intr map register
+        pub const I2S1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x50);
+
+        /// address: 0x600c2054
+        /// i2s1 intr map register
+        pub const UART_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x54);
+
+        /// address: 0x600c2058
+        /// uart1 intr map register
+        pub const UART1_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x58);
+
+        /// address: 0x600c205c
+        /// ledc intr map register
+        pub const LEDC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x5c);
+
+        /// address: 0x600c2060
+        /// efuse intr map register
+        pub const EFUSE_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x60);
+
+        /// address: 0x600c2064
+        /// can intr map register
+        pub const CAN_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x64);
+
+        /// address: 0x600c2068
+        /// usb intr map register
+        pub const USB_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x68);
+
+        /// address: 0x600c206c
+        /// rtc intr map register
+        pub const RTC_CORE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x6c);
+
+        /// address: 0x600c2070
+        /// rmt intr map register
+        pub const RMT_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x70);
+
+        /// address: 0x600c2074
+        /// i2c intr map register
+        pub const I2C_EXT0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x74);
+
+        /// address: 0x600c2078
+        /// timer1 intr map register
+        pub const TIMER_INT1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x78);
+
+        /// address: 0x600c207c
+        /// timer2 intr map register
+        pub const TIMER_INT2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x7c);
+
+        /// address: 0x600c2080
+        /// tg to intr map register
+        pub const TG_T0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x80);
+
+        /// address: 0x600c2084
+        /// tg wdt intr map register
+        pub const TG_WDT_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x84);
+
+        /// address: 0x600c2088
+        /// tg1 to intr map register
+        pub const TG1_T0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x88);
+
+        /// address: 0x600c208c
+        /// tg1 wdt intr map register
+        pub const TG1_WDT_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x8c);
+
+        /// address: 0x600c2090
+        /// cache ia intr map register
+        pub const CACHE_IA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x90);
+
+        /// address: 0x600c2094
+        /// systimer intr map register
+        pub const SYSTIMER_TARGET0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x94);
+
+        /// address: 0x600c2098
+        /// systimer target1 intr map register
+        pub const SYSTIMER_TARGET1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x98);
+
+        /// address: 0x600c209c
+        /// systimer target2 intr map register
+        pub const SYSTIMER_TARGET2_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x9c);
+
+        /// address: 0x600c20a0
+        /// spi mem reject intr map register
+        pub const SPI_MEM_REJECT_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa0);
+
+        /// address: 0x600c20a4
+        /// icache perload intr map register
+        pub const ICACHE_PRELOAD_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa4);
+
+        /// address: 0x600c20a8
+        /// icache sync intr map register
+        pub const ICACHE_SYNC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa8);
+
+        /// address: 0x600c20ac
+        /// adc intr map register
+        pub const APB_ADC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xac);
+
+        /// address: 0x600c20b0
+        /// dma ch0 intr map register
+        pub const DMA_CH0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb0);
+
+        /// address: 0x600c20b4
+        /// dma ch1 intr map register
+        pub const DMA_CH1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb4);
+
+        /// address: 0x600c20b8
+        /// dma ch2 intr map register
+        pub const DMA_CH2_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb8);
+
+        /// address: 0x600c20bc
+        /// rsa intr map register
+        pub const RSA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xbc);
+
+        /// address: 0x600c20c0
+        /// aes intr map register
+        pub const AES_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc0);
+
+        /// address: 0x600c20c4
+        /// sha intr map register
+        pub const SHA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc4);
+
+        /// address: 0x600c20c8
+        /// cpu from cpu 0 intr map register
+        pub const CPU_INTR_FROM_CPU_0_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc8);
+
+        /// address: 0x600c20cc
+        /// cpu from cpu 0 intr map register
+        pub const CPU_INTR_FROM_CPU_1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xcc);
+
+        /// address: 0x600c20d0
+        /// cpu from cpu 1 intr map register
+        pub const CPU_INTR_FROM_CPU_2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd0);
+
+        /// address: 0x600c20d4
+        /// cpu from cpu 3 intr map register
+        pub const CPU_INTR_FROM_CPU_3_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd4);
+
+        /// address: 0x600c20d8
+        /// assist debug intr map register
+        pub const ASSIST_DEBUG_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd8);
+
+        /// address: 0x600c20dc
+        /// dma pms violatile intr map register
+        pub const DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xdc);
+
+        /// address: 0x600c20e0
+        /// iram0 pms violatile intr map register
+        pub const CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe0);
+
+        /// address: 0x600c20e4
+        /// mac intr map register
+        pub const CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe4);
+
+        /// address: 0x600c20e8
+        /// mac intr map register
+        pub const CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe8);
+
+        /// address: 0x600c20ec
+        /// mac intr map register
+        pub const CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xec);
+
+        /// address: 0x600c20f0
+        /// mac intr map register
+        pub const BACKUP_PMS_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xf0);
+
+        /// address: 0x600c20f4
+        /// mac intr map register
+        pub const CACHE_CORE0_ACS_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xf4);
+
+        /// address: 0x600c20f8
+        /// mac intr map register
+        pub const INTR_STATUS_REG_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_intr_status_0
+            INTR_STATUS_0: u32,
+        }), base_address + 0xf8);
+
+        /// address: 0x600c20fc
+        /// mac intr map register
+        pub const INTR_STATUS_REG_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_intr_status_1
+            INTR_STATUS_1: u32,
+        }), base_address + 0xfc);
+
+        /// address: 0x600c2100
+        /// mac intr map register
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_reg_clk_en
+            REG_CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x100);
+
+        /// address: 0x600c2104
+        /// mac intr map register
+        pub const CPU_INT_ENABLE = @intToPtr(*volatile u32, base_address + 0x104);
+
+        /// address: 0x600c2108
+        /// mac intr map register
+        pub const CPU_INT_TYPE = @intToPtr(*volatile u32, base_address + 0x108);
+
+        /// address: 0x600c210c
+        /// mac intr map register
+        pub const CPU_INT_CLEAR = @intToPtr(*volatile u32, base_address + 0x10c);
+
+        /// address: 0x600c2110
+        /// mac intr map register
+        pub const CPU_INT_EIP_STATUS = @intToPtr(*volatile u32, base_address + 0x110);
+
+        /// address: 0x600c2114
+        /// mac intr map register
+        pub const CPU_INT_PRI_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_0_map
+            CPU_PRI_0_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x114);
+
+        /// address: 0x600c2118
+        /// mac intr map register
+        pub const CPU_INT_PRI_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_1_map
+            CPU_PRI_1_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x118);
+
+        /// address: 0x600c211c
+        /// mac intr map register
+        pub const CPU_INT_PRI_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_2_map
+            CPU_PRI_2_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x11c);
+
+        /// address: 0x600c2120
+        /// mac intr map register
+        pub const CPU_INT_PRI_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_3_map
+            CPU_PRI_3_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x120);
+
+        /// address: 0x600c2124
+        /// mac intr map register
+        pub const CPU_INT_PRI_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_4_map
+            CPU_PRI_4_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x124);
+
+        /// address: 0x600c2128
+        /// mac intr map register
+        pub const CPU_INT_PRI_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_5_map
+            CPU_PRI_5_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x128);
+
+        /// address: 0x600c212c
+        /// mac intr map register
+        pub const CPU_INT_PRI_6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_6_map
+            CPU_PRI_6_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x12c);
+
+        /// address: 0x600c2130
+        /// mac intr map register
+        pub const CPU_INT_PRI_7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_7_map
+            CPU_PRI_7_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x130);
+
+        /// address: 0x600c2134
+        /// mac intr map register
+        pub const CPU_INT_PRI_8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_8_map
+            CPU_PRI_8_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x134);
+
+        /// address: 0x600c2138
+        /// mac intr map register
+        pub const CPU_INT_PRI_9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_9_map
+            CPU_PRI_9_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x138);
+
+        /// address: 0x600c213c
+        /// mac intr map register
+        pub const CPU_INT_PRI_10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_10_map
+            CPU_PRI_10_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x13c);
+
+        /// address: 0x600c2140
+        /// mac intr map register
+        pub const CPU_INT_PRI_11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_11_map
+            CPU_PRI_11_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x140);
+
+        /// address: 0x600c2144
+        /// mac intr map register
+        pub const CPU_INT_PRI_12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_12_map
+            CPU_PRI_12_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x144);
+
+        /// address: 0x600c2148
+        /// mac intr map register
+        pub const CPU_INT_PRI_13 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_13_map
+            CPU_PRI_13_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x148);
+
+        /// address: 0x600c214c
+        /// mac intr map register
+        pub const CPU_INT_PRI_14 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_14_map
+            CPU_PRI_14_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x14c);
+
+        /// address: 0x600c2150
+        /// mac intr map register
+        pub const CPU_INT_PRI_15 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_15_map
+            CPU_PRI_15_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x150);
+
+        /// address: 0x600c2154
+        /// mac intr map register
+        pub const CPU_INT_PRI_16 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_16_map
+            CPU_PRI_16_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x154);
+
+        /// address: 0x600c2158
+        /// mac intr map register
+        pub const CPU_INT_PRI_17 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_17_map
+            CPU_PRI_17_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x158);
+
+        /// address: 0x600c215c
+        /// mac intr map register
+        pub const CPU_INT_PRI_18 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_18_map
+            CPU_PRI_18_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x15c);
+
+        /// address: 0x600c2160
+        /// mac intr map register
+        pub const CPU_INT_PRI_19 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_19_map
+            CPU_PRI_19_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x160);
+
+        /// address: 0x600c2164
+        /// mac intr map register
+        pub const CPU_INT_PRI_20 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_20_map
+            CPU_PRI_20_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x164);
+
+        /// address: 0x600c2168
+        /// mac intr map register
+        pub const CPU_INT_PRI_21 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_21_map
+            CPU_PRI_21_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x168);
+
+        /// address: 0x600c216c
+        /// mac intr map register
+        pub const CPU_INT_PRI_22 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_22_map
+            CPU_PRI_22_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x16c);
+
+        /// address: 0x600c2170
+        /// mac intr map register
+        pub const CPU_INT_PRI_23 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_23_map
+            CPU_PRI_23_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x170);
+
+        /// address: 0x600c2174
+        /// mac intr map register
+        pub const CPU_INT_PRI_24 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_24_map
+            CPU_PRI_24_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x174);
+
+        /// address: 0x600c2178
+        /// mac intr map register
+        pub const CPU_INT_PRI_25 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_25_map
+            CPU_PRI_25_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x178);
+
+        /// address: 0x600c217c
+        /// mac intr map register
+        pub const CPU_INT_PRI_26 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_26_map
+            CPU_PRI_26_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x17c);
+
+        /// address: 0x600c2180
+        /// mac intr map register
+        pub const CPU_INT_PRI_27 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_27_map
+            CPU_PRI_27_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x180);
+
+        /// address: 0x600c2184
+        /// mac intr map register
+        pub const CPU_INT_PRI_28 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_28_map
+            CPU_PRI_28_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x184);
+
+        /// address: 0x600c2188
+        /// mac intr map register
+        pub const CPU_INT_PRI_29 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_29_map
+            CPU_PRI_29_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x188);
+
+        /// address: 0x600c218c
+        /// mac intr map register
+        pub const CPU_INT_PRI_30 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_30_map
+            CPU_PRI_30_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x18c);
+
+        /// address: 0x600c2190
+        /// mac intr map register
+        pub const CPU_INT_PRI_31 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_core0_cpu_pri_31_map
+            CPU_PRI_31_MAP: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x190);
+
+        /// address: 0x600c2194
+        /// mac intr map register
+        pub const CPU_INT_THRESH = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x194);
+
+        /// address: 0x600c27fc
+        /// mac intr map register
+        pub const INTERRUPT_REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x7fc);
+    };
+
+    /// Input/Output Multiplexer
+    pub const IO_MUX = struct {
+        pub const base_address = 0x60009000;
+
+        /// address: 0x60009000
+        /// Clock Output Configuration Register
+        pub const PIN_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
+            /// CLK_OUT_out1 can be found in peripheral output signals.
+            CLK_OUT1: u4,
+            /// If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
+            /// CLK_OUT_out2 can be found in peripheral output signals.
+            CLK_OUT2: u4,
+            /// If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
+            /// CLK_OUT_out3 can be found in peripheral output signals.
+            CLK_OUT3: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60009004
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60009008
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000900c
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60009010
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60009014
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60009018
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000901c
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60009020
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60009024
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60009028
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6000902c
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60009030
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60009034
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60009038
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO13 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6000903c
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO14 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60009040
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO15 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60009044
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO16 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60009048
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO17 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6000904c
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO18 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60009050
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO19 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60009054
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO20 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60009058
+        /// IO MUX Configure Register for pad XTAL_32K_P
+        pub const GPIO21 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+            MCU_OE: u1,
+            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+            SLP_SEL: u1,
+            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
+            /// internal pull-down disabled.
+            MCU_WPD: u1,
+            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
+            /// internal pull-up disabled.
+            MCU_WPU: u1,
+            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+            MCU_IE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
+            /// pull-down disabled.
+            FUN_WPD: u1,
+            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
+            /// disabled.
+            FUN_WPU: u1,
+            /// Input enable of the pad. 1: input enabled; 0: input disabled.
+            FUN_IE: u1,
+            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+            FUN_DRV: u2,
+            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
+            /// 2; etc.
+            MCU_SEL: u3,
+            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+            FILTER_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x600090fc
+        /// IO MUX Version Control Register
+        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Version control register
+            REG_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xfc);
+    };
+
+    /// LED Control PWM (Pulse Width Modulation)
+    pub const LEDC = struct {
+        pub const base_address = 0x60019000;
+
+        /// address: 0x60019000
+        /// LEDC_LSCH0_CONF0.
+        pub const LSCH0_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch0.
+            TIMER_SEL_LSCH0: u2,
+            /// reg_sig_out_en_lsch0.
+            SIG_OUT_EN_LSCH0: u1,
+            /// reg_idle_lv_lsch0.
+            IDLE_LV_LSCH0: u1,
+            /// reg_para_up_lsch0.
+            PARA_UP_LSCH0: u1,
+            /// reg_ovf_num_lsch0.
+            OVF_NUM_LSCH0: u10,
+            /// reg_ovf_cnt_en_lsch0.
+            OVF_CNT_EN_LSCH0: u1,
+            /// reg_ovf_cnt_reset_lsch0.
+            OVF_CNT_RESET_LSCH0: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60019004
+        /// LEDC_LSCH0_HPOINT.
+        pub const LSCH0_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch0.
+            HPOINT_LSCH0: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60019008
+        /// LEDC_LSCH0_DUTY.
+        pub const LSCH0_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch0.
+            DUTY_LSCH0: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6001900c
+        /// LEDC_LSCH0_CONF1.
+        pub const LSCH0_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch0.
+            DUTY_SCALE_LSCH0: u10,
+            /// reg_duty_cycle_lsch0.
+            DUTY_CYCLE_LSCH0: u10,
+            /// reg_duty_num_lsch0.
+            DUTY_NUM_LSCH0: u10,
+            /// reg_duty_inc_lsch0.
+            DUTY_INC_LSCH0: u1,
+            /// reg_duty_start_lsch0.
+            DUTY_START_LSCH0: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60019010
+        /// LEDC_LSCH0_DUTY_R.
+        pub const LSCH0_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch0_r.
+            DUTY_LSCH0_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60019014
+        /// LEDC_LSCH1_CONF0.
+        pub const LSCH1_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch1.
+            TIMER_SEL_LSCH1: u2,
+            /// reg_sig_out_en_lsch1.
+            SIG_OUT_EN_LSCH1: u1,
+            /// reg_idle_lv_lsch1.
+            IDLE_LV_LSCH1: u1,
+            /// reg_para_up_lsch1.
+            PARA_UP_LSCH1: u1,
+            /// reg_ovf_num_lsch1.
+            OVF_NUM_LSCH1: u10,
+            /// reg_ovf_cnt_en_lsch1.
+            OVF_CNT_EN_LSCH1: u1,
+            /// reg_ovf_cnt_reset_lsch1.
+            OVF_CNT_RESET_LSCH1: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60019018
+        /// LEDC_LSCH1_HPOINT.
+        pub const LSCH1_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch1.
+            HPOINT_LSCH1: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6001901c
+        /// LEDC_LSCH1_DUTY.
+        pub const LSCH1_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch1.
+            DUTY_LSCH1: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60019020
+        /// LEDC_LSCH1_CONF1.
+        pub const LSCH1_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch1.
+            DUTY_SCALE_LSCH1: u10,
+            /// reg_duty_cycle_lsch1.
+            DUTY_CYCLE_LSCH1: u10,
+            /// reg_duty_num_lsch1.
+            DUTY_NUM_LSCH1: u10,
+            /// reg_duty_inc_lsch1.
+            DUTY_INC_LSCH1: u1,
+            /// reg_duty_start_lsch1.
+            DUTY_START_LSCH1: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60019024
+        /// LEDC_LSCH1_DUTY_R.
+        pub const LSCH1_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch1_r.
+            DUTY_LSCH1_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60019028
+        /// LEDC_LSCH2_CONF0.
+        pub const LSCH2_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch2.
+            TIMER_SEL_LSCH2: u2,
+            /// reg_sig_out_en_lsch2.
+            SIG_OUT_EN_LSCH2: u1,
+            /// reg_idle_lv_lsch2.
+            IDLE_LV_LSCH2: u1,
+            /// reg_para_up_lsch2.
+            PARA_UP_LSCH2: u1,
+            /// reg_ovf_num_lsch2.
+            OVF_NUM_LSCH2: u10,
+            /// reg_ovf_cnt_en_lsch2.
+            OVF_CNT_EN_LSCH2: u1,
+            /// reg_ovf_cnt_reset_lsch2.
+            OVF_CNT_RESET_LSCH2: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6001902c
+        /// LEDC_LSCH2_HPOINT.
+        pub const LSCH2_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch2.
+            HPOINT_LSCH2: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60019030
+        /// LEDC_LSCH2_DUTY.
+        pub const LSCH2_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch2.
+            DUTY_LSCH2: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60019034
+        /// LEDC_LSCH2_CONF1.
+        pub const LSCH2_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch2.
+            DUTY_SCALE_LSCH2: u10,
+            /// reg_duty_cycle_lsch2.
+            DUTY_CYCLE_LSCH2: u10,
+            /// reg_duty_num_lsch2.
+            DUTY_NUM_LSCH2: u10,
+            /// reg_duty_inc_lsch2.
+            DUTY_INC_LSCH2: u1,
+            /// reg_duty_start_lsch2.
+            DUTY_START_LSCH2: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60019038
+        /// LEDC_LSCH2_DUTY_R.
+        pub const LSCH2_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch2_r.
+            DUTY_LSCH2_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6001903c
+        /// LEDC_LSCH3_CONF0.
+        pub const LSCH3_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch3.
+            TIMER_SEL_LSCH3: u2,
+            /// reg_sig_out_en_lsch3.
+            SIG_OUT_EN_LSCH3: u1,
+            /// reg_idle_lv_lsch3.
+            IDLE_LV_LSCH3: u1,
+            /// reg_para_up_lsch3.
+            PARA_UP_LSCH3: u1,
+            /// reg_ovf_num_lsch3.
+            OVF_NUM_LSCH3: u10,
+            /// reg_ovf_cnt_en_lsch3.
+            OVF_CNT_EN_LSCH3: u1,
+            /// reg_ovf_cnt_reset_lsch3.
+            OVF_CNT_RESET_LSCH3: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60019040
+        /// LEDC_LSCH3_HPOINT.
+        pub const LSCH3_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch3.
+            HPOINT_LSCH3: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60019044
+        /// LEDC_LSCH3_DUTY.
+        pub const LSCH3_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch3.
+            DUTY_LSCH3: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60019048
+        /// LEDC_LSCH3_CONF1.
+        pub const LSCH3_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch3.
+            DUTY_SCALE_LSCH3: u10,
+            /// reg_duty_cycle_lsch3.
+            DUTY_CYCLE_LSCH3: u10,
+            /// reg_duty_num_lsch3.
+            DUTY_NUM_LSCH3: u10,
+            /// reg_duty_inc_lsch3.
+            DUTY_INC_LSCH3: u1,
+            /// reg_duty_start_lsch3.
+            DUTY_START_LSCH3: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6001904c
+        /// LEDC_LSCH3_DUTY_R.
+        pub const LSCH3_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch3_r.
+            DUTY_LSCH3_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60019050
+        /// LEDC_LSCH4_CONF0.
+        pub const LSCH4_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch4.
+            TIMER_SEL_LSCH4: u2,
+            /// reg_sig_out_en_lsch4.
+            SIG_OUT_EN_LSCH4: u1,
+            /// reg_idle_lv_lsch4.
+            IDLE_LV_LSCH4: u1,
+            /// reg_para_up_lsch4.
+            PARA_UP_LSCH4: u1,
+            /// reg_ovf_num_lsch4.
+            OVF_NUM_LSCH4: u10,
+            /// reg_ovf_cnt_en_lsch4.
+            OVF_CNT_EN_LSCH4: u1,
+            /// reg_ovf_cnt_reset_lsch4.
+            OVF_CNT_RESET_LSCH4: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60019054
+        /// LEDC_LSCH4_HPOINT.
+        pub const LSCH4_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch4.
+            HPOINT_LSCH4: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60019058
+        /// LEDC_LSCH4_DUTY.
+        pub const LSCH4_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch4.
+            DUTY_LSCH4: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6001905c
+        /// LEDC_LSCH4_CONF1.
+        pub const LSCH4_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch4.
+            DUTY_SCALE_LSCH4: u10,
+            /// reg_duty_cycle_lsch4.
+            DUTY_CYCLE_LSCH4: u10,
+            /// reg_duty_num_lsch4.
+            DUTY_NUM_LSCH4: u10,
+            /// reg_duty_inc_lsch4.
+            DUTY_INC_LSCH4: u1,
+            /// reg_duty_start_lsch4.
+            DUTY_START_LSCH4: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60019060
+        /// LEDC_LSCH4_DUTY_R.
+        pub const LSCH4_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch4_r.
+            DUTY_LSCH4_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60019064
+        /// LEDC_LSCH5_CONF0.
+        pub const LSCH5_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timer_sel_lsch5.
+            TIMER_SEL_LSCH5: u2,
+            /// reg_sig_out_en_lsch5.
+            SIG_OUT_EN_LSCH5: u1,
+            /// reg_idle_lv_lsch5.
+            IDLE_LV_LSCH5: u1,
+            /// reg_para_up_lsch5.
+            PARA_UP_LSCH5: u1,
+            /// reg_ovf_num_lsch5.
+            OVF_NUM_LSCH5: u10,
+            /// reg_ovf_cnt_en_lsch5.
+            OVF_CNT_EN_LSCH5: u1,
+            /// reg_ovf_cnt_reset_lsch5.
+            OVF_CNT_RESET_LSCH5: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60019068
+        /// LEDC_LSCH5_HPOINT.
+        pub const LSCH5_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_hpoint_lsch5.
+            HPOINT_LSCH5: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6001906c
+        /// LEDC_LSCH5_DUTY.
+        pub const LSCH5_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch5.
+            DUTY_LSCH5: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60019070
+        /// LEDC_LSCH5_CONF1.
+        pub const LSCH5_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_scale_lsch5.
+            DUTY_SCALE_LSCH5: u10,
+            /// reg_duty_cycle_lsch5.
+            DUTY_CYCLE_LSCH5: u10,
+            /// reg_duty_num_lsch5.
+            DUTY_NUM_LSCH5: u10,
+            /// reg_duty_inc_lsch5.
+            DUTY_INC_LSCH5: u1,
+            /// reg_duty_start_lsch5.
+            DUTY_START_LSCH5: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60019074
+        /// LEDC_LSCH5_DUTY_R.
+        pub const LSCH5_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_duty_lsch5_r.
+            DUTY_LSCH5_R: u19,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x600190a0
+        /// LEDC_LSTIMER0_CONF.
+        pub const LSTIMER0_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_duty_res.
+            LSTIMER0_DUTY_RES: u4,
+            /// reg_clk_div_lstimer0.
+            CLK_DIV_LSTIMER0: u18,
+            /// reg_lstimer0_pause.
+            LSTIMER0_PAUSE: u1,
+            /// reg_lstimer0_rst.
+            LSTIMER0_RST: u1,
+            /// reg_tick_sel_lstimer0.
+            TICK_SEL_LSTIMER0: u1,
+            /// reg_lstimer0_para_up.
+            LSTIMER0_PARA_UP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x600190a4
+        /// LEDC_LSTIMER0_VALUE.
+        pub const LSTIMER0_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_cnt.
+            LSTIMER0_CNT: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600190a8
+        /// LEDC_LSTIMER1_CONF.
+        pub const LSTIMER1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer1_duty_res.
+            LSTIMER1_DUTY_RES: u4,
+            /// reg_clk_div_lstimer1.
+            CLK_DIV_LSTIMER1: u18,
+            /// reg_lstimer1_pause.
+            LSTIMER1_PAUSE: u1,
+            /// reg_lstimer1_rst.
+            LSTIMER1_RST: u1,
+            /// reg_tick_sel_lstimer1.
+            TICK_SEL_LSTIMER1: u1,
+            /// reg_lstimer1_para_up.
+            LSTIMER1_PARA_UP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600190ac
+        /// LEDC_LSTIMER1_VALUE.
+        pub const LSTIMER1_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer1_cnt.
+            LSTIMER1_CNT: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600190b0
+        /// LEDC_LSTIMER2_CONF.
+        pub const LSTIMER2_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer2_duty_res.
+            LSTIMER2_DUTY_RES: u4,
+            /// reg_clk_div_lstimer2.
+            CLK_DIV_LSTIMER2: u18,
+            /// reg_lstimer2_pause.
+            LSTIMER2_PAUSE: u1,
+            /// reg_lstimer2_rst.
+            LSTIMER2_RST: u1,
+            /// reg_tick_sel_lstimer2.
+            TICK_SEL_LSTIMER2: u1,
+            /// reg_lstimer2_para_up.
+            LSTIMER2_PARA_UP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0xb0);
+
+        /// address: 0x600190b4
+        /// LEDC_LSTIMER2_VALUE.
+        pub const LSTIMER2_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer2_cnt.
+            LSTIMER2_CNT: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600190b8
+        /// LEDC_LSTIMER3_CONF.
+        pub const LSTIMER3_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer3_duty_res.
+            LSTIMER3_DUTY_RES: u4,
+            /// reg_clk_div_lstimer3.
+            CLK_DIV_LSTIMER3: u18,
+            /// reg_lstimer3_pause.
+            LSTIMER3_PAUSE: u1,
+            /// reg_lstimer3_rst.
+            LSTIMER3_RST: u1,
+            /// reg_tick_sel_lstimer3.
+            TICK_SEL_LSTIMER3: u1,
+            /// reg_lstimer3_para_up.
+            LSTIMER3_PARA_UP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0xb8);
+
+        /// address: 0x600190bc
+        /// LEDC_LSTIMER3_VALUE.
+        pub const LSTIMER3_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer3_cnt.
+            LSTIMER3_CNT: u14,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0xbc);
+
+        /// address: 0x600190c0
+        /// LEDC_INT_RAW.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_ovf_int_raw.
+            LSTIMER0_OVF_INT_RAW: u1,
+            /// reg_lstimer1_ovf_int_raw.
+            LSTIMER1_OVF_INT_RAW: u1,
+            /// reg_lstimer2_ovf_int_raw.
+            LSTIMER2_OVF_INT_RAW: u1,
+            /// reg_lstimer3_ovf_int_raw.
+            LSTIMER3_OVF_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch0_int_raw.
+            DUTY_CHNG_END_LSCH0_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch1_int_raw.
+            DUTY_CHNG_END_LSCH1_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch2_int_raw.
+            DUTY_CHNG_END_LSCH2_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch3_int_raw.
+            DUTY_CHNG_END_LSCH3_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch4_int_raw.
+            DUTY_CHNG_END_LSCH4_INT_RAW: u1,
+            /// reg_duty_chng_end_lsch5_int_raw.
+            DUTY_CHNG_END_LSCH5_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch0_int_raw.
+            OVF_CNT_LSCH0_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch1_int_raw.
+            OVF_CNT_LSCH1_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch2_int_raw.
+            OVF_CNT_LSCH2_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch3_int_raw.
+            OVF_CNT_LSCH3_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch4_int_raw.
+            OVF_CNT_LSCH4_INT_RAW: u1,
+            /// reg_ovf_cnt_lsch5_int_raw.
+            OVF_CNT_LSCH5_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600190c4
+        /// LEDC_INT_ST.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_ovf_int_st.
+            LSTIMER0_OVF_INT_ST: u1,
+            /// reg_lstimer1_ovf_int_st.
+            LSTIMER1_OVF_INT_ST: u1,
+            /// reg_lstimer2_ovf_int_st.
+            LSTIMER2_OVF_INT_ST: u1,
+            /// reg_lstimer3_ovf_int_st.
+            LSTIMER3_OVF_INT_ST: u1,
+            /// reg_duty_chng_end_lsch0_int_st.
+            DUTY_CHNG_END_LSCH0_INT_ST: u1,
+            /// reg_duty_chng_end_lsch1_int_st.
+            DUTY_CHNG_END_LSCH1_INT_ST: u1,
+            /// reg_duty_chng_end_lsch2_int_st.
+            DUTY_CHNG_END_LSCH2_INT_ST: u1,
+            /// reg_duty_chng_end_lsch3_int_st.
+            DUTY_CHNG_END_LSCH3_INT_ST: u1,
+            /// reg_duty_chng_end_lsch4_int_st.
+            DUTY_CHNG_END_LSCH4_INT_ST: u1,
+            /// reg_duty_chng_end_lsch5_int_st.
+            DUTY_CHNG_END_LSCH5_INT_ST: u1,
+            /// reg_ovf_cnt_lsch0_int_st.
+            OVF_CNT_LSCH0_INT_ST: u1,
+            /// reg_ovf_cnt_lsch1_int_st.
+            OVF_CNT_LSCH1_INT_ST: u1,
+            /// reg_ovf_cnt_lsch2_int_st.
+            OVF_CNT_LSCH2_INT_ST: u1,
+            /// reg_ovf_cnt_lsch3_int_st.
+            OVF_CNT_LSCH3_INT_ST: u1,
+            /// reg_ovf_cnt_lsch4_int_st.
+            OVF_CNT_LSCH4_INT_ST: u1,
+            /// reg_ovf_cnt_lsch5_int_st.
+            OVF_CNT_LSCH5_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xc4);
+
+        /// address: 0x600190c8
+        /// LEDC_INT_ENA.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_ovf_int_ena.
+            LSTIMER0_OVF_INT_ENA: u1,
+            /// reg_lstimer1_ovf_int_ena.
+            LSTIMER1_OVF_INT_ENA: u1,
+            /// reg_lstimer2_ovf_int_ena.
+            LSTIMER2_OVF_INT_ENA: u1,
+            /// reg_lstimer3_ovf_int_ena.
+            LSTIMER3_OVF_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch0_int_ena.
+            DUTY_CHNG_END_LSCH0_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch1_int_ena.
+            DUTY_CHNG_END_LSCH1_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch2_int_ena.
+            DUTY_CHNG_END_LSCH2_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch3_int_ena.
+            DUTY_CHNG_END_LSCH3_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch4_int_ena.
+            DUTY_CHNG_END_LSCH4_INT_ENA: u1,
+            /// reg_duty_chng_end_lsch5_int_ena.
+            DUTY_CHNG_END_LSCH5_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch0_int_ena.
+            OVF_CNT_LSCH0_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch1_int_ena.
+            OVF_CNT_LSCH1_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch2_int_ena.
+            OVF_CNT_LSCH2_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch3_int_ena.
+            OVF_CNT_LSCH3_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch4_int_ena.
+            OVF_CNT_LSCH4_INT_ENA: u1,
+            /// reg_ovf_cnt_lsch5_int_ena.
+            OVF_CNT_LSCH5_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600190cc
+        /// LEDC_INT_CLR.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lstimer0_ovf_int_clr.
+            LSTIMER0_OVF_INT_CLR: u1,
+            /// reg_lstimer1_ovf_int_clr.
+            LSTIMER1_OVF_INT_CLR: u1,
+            /// reg_lstimer2_ovf_int_clr.
+            LSTIMER2_OVF_INT_CLR: u1,
+            /// reg_lstimer3_ovf_int_clr.
+            LSTIMER3_OVF_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch0_int_clr.
+            DUTY_CHNG_END_LSCH0_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch1_int_clr.
+            DUTY_CHNG_END_LSCH1_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch2_int_clr.
+            DUTY_CHNG_END_LSCH2_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch3_int_clr.
+            DUTY_CHNG_END_LSCH3_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch4_int_clr.
+            DUTY_CHNG_END_LSCH4_INT_CLR: u1,
+            /// reg_duty_chng_end_lsch5_int_clr.
+            DUTY_CHNG_END_LSCH5_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch0_int_clr.
+            OVF_CNT_LSCH0_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch1_int_clr.
+            OVF_CNT_LSCH1_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch2_int_clr.
+            OVF_CNT_LSCH2_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch3_int_clr.
+            OVF_CNT_LSCH3_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch4_int_clr.
+            OVF_CNT_LSCH4_INT_CLR: u1,
+            /// reg_ovf_cnt_lsch5_int_clr.
+            OVF_CNT_LSCH5_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xcc);
+
+        /// address: 0x600190d0
+        /// LEDC_CONF.
+        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_apb_clk_sel.
+            APB_CLK_SEL: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// reg_clk_en.
+            CLK_EN: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x600190fc
+        /// LEDC_DATE.
+        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_ledc_date.
+            LEDC_DATE: u32,
+        }), base_address + 0xfc);
+    };
+
+    /// Remote Control Peripheral
+    pub const RMT = struct {
+        pub const base_address = 0x60016000;
+
+        /// address: 0x60016000
+        /// RMT_CH0DATA_REG.
+        pub const CH0DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            DATA: u32,
+        }), base_address + 0x0);
+
+        /// address: 0x60016004
+        /// RMT_CH1DATA_REG.
+        pub const CH1DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            DATA: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60016008
+        /// RMT_CH2DATA_REG.
+        pub const CH2DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            DATA: u32,
+        }), base_address + 0x8);
+
+        /// address: 0x6001600c
+        /// RMT_CH3DATA_REG.
+        pub const CH3DATA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Reserved.
+            DATA: u32,
+        }), base_address + 0xc);
+
+        /// address: 0x60016010
+        /// RMT_CH%sCONF%s_REG.
+        pub const CH0_TX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_tx_start_ch0.
+            TX_START: u1,
+            /// reg_mem_rd_rst_ch0.
+            MEM_RD_RST: u1,
+            /// reg_apb_mem_rst_ch0.
+            APB_MEM_RST: u1,
+            /// reg_tx_conti_mode_ch0.
+            TX_CONTI_MODE: u1,
+            /// reg_mem_tx_wrap_en_ch0.
+            MEM_TX_WRAP_EN: u1,
+            /// reg_idle_out_lv_ch0.
+            IDLE_OUT_LV: u1,
+            /// reg_idle_out_en_ch0.
+            IDLE_OUT_EN: u1,
+            /// reg_tx_stop_ch0.
+            TX_STOP: u1,
+            /// reg_div_cnt_ch0.
+            DIV_CNT: u8,
+            /// reg_mem_size_ch0.
+            MEM_SIZE: u3,
+            reserved0: u1,
+            /// reg_carrier_eff_en_ch0.
+            CARRIER_EFF_EN: u1,
+            /// reg_carrier_en_ch0.
+            CARRIER_EN: u1,
+            /// reg_carrier_out_lv_ch0.
+            CARRIER_OUT_LV: u1,
+            /// reg_afifo_rst_ch0.
+            AFIFO_RST: u1,
+            /// reg_reg_conf_update_ch0.
+            CONF_UPDATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60016014
+        /// RMT_CH%sCONF%s_REG.
+        pub const CH1_TX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_tx_start_ch0.
+            TX_START: u1,
+            /// reg_mem_rd_rst_ch0.
+            MEM_RD_RST: u1,
+            /// reg_apb_mem_rst_ch0.
+            APB_MEM_RST: u1,
+            /// reg_tx_conti_mode_ch0.
+            TX_CONTI_MODE: u1,
+            /// reg_mem_tx_wrap_en_ch0.
+            MEM_TX_WRAP_EN: u1,
+            /// reg_idle_out_lv_ch0.
+            IDLE_OUT_LV: u1,
+            /// reg_idle_out_en_ch0.
+            IDLE_OUT_EN: u1,
+            /// reg_tx_stop_ch0.
+            TX_STOP: u1,
+            /// reg_div_cnt_ch0.
+            DIV_CNT: u8,
+            /// reg_mem_size_ch0.
+            MEM_SIZE: u3,
+            reserved0: u1,
+            /// reg_carrier_eff_en_ch0.
+            CARRIER_EFF_EN: u1,
+            /// reg_carrier_en_ch0.
+            CARRIER_EN: u1,
+            /// reg_carrier_out_lv_ch0.
+            CARRIER_OUT_LV: u1,
+            /// reg_afifo_rst_ch0.
+            AFIFO_RST: u1,
+            /// reg_reg_conf_update_ch0.
+            CONF_UPDATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60016018
+        /// RMT_CH2CONF0_REG.
+        pub const CH2_RX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_div_cnt_ch2.
+            DIV_CNT: u8,
+            /// reg_idle_thres_ch2.
+            IDLE_THRES: u15,
+            /// reg_mem_size_ch2.
+            MEM_SIZE: u3,
+            reserved0: u1,
+            reserved1: u1,
+            /// reg_carrier_en_ch2.
+            CARRIER_EN: u1,
+            /// reg_carrier_out_lv_ch2.
+            CARRIER_OUT_LV: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x60016020
+        /// RMT_CH2CONF0_REG.
+        pub const CH3_RX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_div_cnt_ch2.
+            DIV_CNT: u8,
+            /// reg_idle_thres_ch2.
+            IDLE_THRES: u15,
+            /// reg_mem_size_ch2.
+            MEM_SIZE: u3,
+            reserved0: u1,
+            reserved1: u1,
+            /// reg_carrier_en_ch2.
+            CARRIER_EN: u1,
+            /// reg_carrier_out_lv_ch2.
+            CARRIER_OUT_LV: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x6001601c
+        /// RMT_CH2CONF1_REG.
+        pub const CH2CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rx_en_ch2.
+            RX_EN: u1,
+            /// reg_mem_wr_rst_ch2.
+            MEM_WR_RST: u1,
+            /// reg_apb_mem_rst_ch2.
+            APB_MEM_RST: u1,
+            /// reg_mem_owner_ch2.
+            MEM_OWNER: u1,
+            /// reg_rx_filter_en_ch2.
+            RX_FILTER_EN: u1,
+            /// reg_rx_filter_thres_ch2.
+            RX_FILTER_THRES: u8,
+            /// reg_mem_rx_wrap_en_ch2.
+            MEM_RX_WRAP_EN: u1,
+            /// reg_afifo_rst_ch2.
+            AFIFO_RST: u1,
+            /// reg_conf_update_ch2.
+            CONF_UPDATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60016024
+        /// RMT_CH3CONF1_REG.
+        pub const CH3CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rx_en_ch3.
+            RX_EN: u1,
+            /// reg_mem_wr_rst_ch3.
+            MEM_WR_RST: u1,
+            /// reg_apb_mem_rst_ch3.
+            APB_MEM_RST: u1,
+            /// reg_mem_owner_ch3.
+            MEM_OWNER: u1,
+            /// reg_rx_filter_en_ch3.
+            RX_FILTER_EN: u1,
+            /// reg_rx_filter_thres_ch3.
+            RX_FILTER_THRES: u8,
+            /// reg_mem_rx_wrap_en_ch3.
+            MEM_RX_WRAP_EN: u1,
+            /// reg_afifo_rst_ch3.
+            AFIFO_RST: u1,
+            /// reg_conf_update_ch3.
+            CONF_UPDATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60016028
+        /// RMT_CH0STATUS_REG.
+        pub const CH0STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_mem_raddr_ex_ch0.
+            MEM_RADDR_EX: u9,
+            /// reg_state_ch0.
+            STATE: u3,
+            /// reg_apb_mem_waddr_ch0.
+            APB_MEM_WADDR: u9,
+            /// reg_apb_mem_rd_err_ch0.
+            APB_MEM_RD_ERR: u1,
+            /// reg_mem_empty_ch0.
+            MEM_EMPTY: u1,
+            /// reg_apb_mem_wr_err_ch0.
+            APB_MEM_WR_ERR: u1,
+            /// reg_apb_mem_raddr_ch0.
+            APB_MEM_RADDR: u8,
+        }), base_address + 0x28);
+
+        /// address: 0x6001602c
+        /// RMT_CH1STATUS_REG.
+        pub const CH1STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_mem_raddr_ex_ch1.
+            MEM_RADDR_EX: u9,
+            /// reg_state_ch1.
+            STATE: u3,
+            /// reg_apb_mem_waddr_ch1.
+            APB_MEM_WADDR: u9,
+            /// reg_apb_mem_rd_err_ch1.
+            APB_MEM_RD_ERR: u1,
+            /// reg_mem_empty_ch1.
+            MEM_EMPTY: u1,
+            /// reg_apb_mem_wr_err_ch1.
+            APB_MEM_WR_ERR: u1,
+            /// reg_apb_mem_raddr_ch1.
+            APB_MEM_RADDR: u8,
+        }), base_address + 0x2c);
+
+        /// address: 0x60016030
+        /// RMT_CH2STATUS_REG.
+        pub const CH2STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_mem_waddr_ex_ch2.
+            MEM_WADDR_EX: u9,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// reg_apb_mem_raddr_ch2.
+            APB_MEM_RADDR: u9,
+            reserved3: u1,
+            /// reg_state_ch2.
+            STATE: u3,
+            /// reg_mem_owner_err_ch2.
+            MEM_OWNER_ERR: u1,
+            /// reg_mem_full_ch2.
+            MEM_FULL: u1,
+            /// reg_apb_mem_rd_err_ch2.
+            APB_MEM_RD_ERR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60016034
+        /// RMT_CH3STATUS_REG.
+        pub const CH3STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_mem_waddr_ex_ch3.
+            MEM_WADDR_EX: u9,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// reg_apb_mem_raddr_ch3.
+            APB_MEM_RADDR: u9,
+            reserved3: u1,
+            /// reg_state_ch3.
+            STATE: u3,
+            /// reg_mem_owner_err_ch3.
+            MEM_OWNER_ERR: u1,
+            /// reg_mem_full_ch3.
+            MEM_FULL: u1,
+            /// reg_apb_mem_rd_err_ch3.
+            APB_MEM_RD_ERR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60016038
+        /// RMT_INT_RAW_REG.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            CH0_TX_END_INT_RAW: u1,
+            CH1_TX_END_INT_RAW: u1,
+            CH2_RX_END_INT_RAW: u1,
+            CH3_RX_END_INT_RAW: u1,
+            CH0_TX_ERR_INT_RAW: u1,
+            CH1_TX_ERR_INT_RAW: u1,
+            CH2_RX_ERR_INT_RAW: u1,
+            CH3_RX_ERR_INT_RAW: u1,
+            CH0_TX_THR_EVENT_INT_RAW: u1,
+            CH1_TX_THR_EVENT_INT_RAW: u1,
+            /// reg_ch2_rx_thr_event_int_raw.
+            CH2_RX_THR_EVENT_INT_RAW: u1,
+            /// reg_ch3_rx_thr_event_int_raw.
+            CH3_RX_THR_EVENT_INT_RAW: u1,
+            CH0_TX_LOOP_INT_RAW: u1,
+            CH1_TX_LOOP_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6001603c
+        /// RMT_INT_ST_REG.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            CH0_TX_END_INT_ST: u1,
+            CH1_TX_END_INT_ST: u1,
+            CH2_RX_END_INT_ST: u1,
+            CH3_RX_END_INT_ST: u1,
+            CH0_TX_ERR_INT_ST: u1,
+            CH1_TX_ERR_INT_ST: u1,
+            CH2_RX_ERR_INT_ST: u1,
+            CH3_RX_ERR_INT_ST: u1,
+            CH0_TX_THR_EVENT_INT_ST: u1,
+            CH1_TX_THR_EVENT_INT_ST: u1,
+            /// reg_ch2_rx_thr_event_int_st.
+            CH2_RX_THR_EVENT_INT_ST: u1,
+            /// reg_ch3_rx_thr_event_int_st.
+            CH3_RX_THR_EVENT_INT_ST: u1,
+            CH0_TX_LOOP_INT_ST: u1,
+            CH1_TX_LOOP_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60016040
+        /// RMT_INT_ENA_REG.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            CH0_TX_END_INT_ENA: u1,
+            CH1_TX_END_INT_ENA: u1,
+            CH2_RX_END_INT_ENA: u1,
+            CH3_RX_END_INT_ENA: u1,
+            CH0_TX_ERR_INT_ENA: u1,
+            CH1_TX_ERR_INT_ENA: u1,
+            CH2_RX_ERR_INT_ENA: u1,
+            CH3_RX_ERR_INT_ENA: u1,
+            CH0_TX_THR_EVENT_INT_ENA: u1,
+            CH1_TX_THR_EVENT_INT_ENA: u1,
+            /// reg_ch2_rx_thr_event_int_ena.
+            CH2_RX_THR_EVENT_INT_ENA: u1,
+            /// reg_ch3_rx_thr_event_int_ena.
+            CH3_RX_THR_EVENT_INT_ENA: u1,
+            CH0_TX_LOOP_INT_ENA: u1,
+            CH1_TX_LOOP_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60016044
+        /// RMT_INT_CLR_REG.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            CH0_TX_END_INT_CLR: u1,
+            CH1_TX_END_INT_CLR: u1,
+            CH2_RX_END_INT_CLR: u1,
+            CH3_RX_END_INT_CLR: u1,
+            CH0_TX_ERR_INT_CLR: u1,
+            CH1_TX_ERR_INT_CLR: u1,
+            CH2_RX_ERR_INT_CLR: u1,
+            CH3_RX_ERR_INT_CLR: u1,
+            CH0_TX_THR_EVENT_INT_CLR: u1,
+            CH1_TX_THR_EVENT_INT_CLR: u1,
+            /// reg_ch2_rx_thr_event_int_clr.
+            CH2_RX_THR_EVENT_INT_CLR: u1,
+            /// reg_ch3_rx_thr_event_int_clr.
+            CH3_RX_THR_EVENT_INT_CLR: u1,
+            CH0_TX_LOOP_INT_CLR: u1,
+            CH1_TX_LOOP_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60016048
+        /// RMT_CH0CARRIER_DUTY_REG.
+        pub const CH0CARRIER_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_carrier_low_ch0.
+            CARRIER_LOW: u16,
+            /// reg_carrier_high_ch0.
+            CARRIER_HIGH: u16,
+        }), base_address + 0x48);
+
+        /// address: 0x6001604c
+        /// RMT_CH1CARRIER_DUTY_REG.
+        pub const CH1CARRIER_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_carrier_low_ch1.
+            CARRIER_LOW: u16,
+            /// reg_carrier_high_ch1.
+            CARRIER_HIGH: u16,
+        }), base_address + 0x4c);
+
+        /// address: 0x60016050
+        /// RMT_CH2_RX_CARRIER_RM_REG.
+        pub const CH2_RX_CARRIER_RM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_carrier_low_thres_ch2.
+            CARRIER_LOW_THRES: u16,
+            /// reg_carrier_high_thres_ch2.
+            CARRIER_HIGH_THRES: u16,
+        }), base_address + 0x50);
+
+        /// address: 0x60016054
+        /// RMT_CH3_RX_CARRIER_RM_REG.
+        pub const CH3_RX_CARRIER_RM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_carrier_low_thres_ch3.
+            CARRIER_LOW_THRES: u16,
+            /// reg_carrier_high_thres_ch3.
+            CARRIER_HIGH_THRES: u16,
+        }), base_address + 0x54);
+
+        /// address: 0x60016058
+        /// RMT_CH%s_TX_LIM_REG.
+        pub const CH0_TX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rmt_tx_lim_ch0.
+            TX_LIM: u9,
+            /// reg_rmt_tx_loop_num_ch0.
+            TX_LOOP_NUM: u10,
+            /// reg_rmt_tx_loop_cnt_en_ch0.
+            TX_LOOP_CNT_EN: u1,
+            /// reg_loop_count_reset_ch0.
+            LOOP_COUNT_RESET: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6001605c
+        /// RMT_CH%s_TX_LIM_REG.
+        pub const CH1_TX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rmt_tx_lim_ch0.
+            TX_LIM: u9,
+            /// reg_rmt_tx_loop_num_ch0.
+            TX_LOOP_NUM: u10,
+            /// reg_rmt_tx_loop_cnt_en_ch0.
+            TX_LOOP_CNT_EN: u1,
+            /// reg_loop_count_reset_ch0.
+            LOOP_COUNT_RESET: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60016060
+        /// RMT_CH2_RX_LIM_REG.
+        pub const CH2_RX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rmt_rx_lim_ch2.
+            RX_LIM: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60016064
+        /// RMT_CH2_RX_LIM_REG.
+        pub const CH3_RX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rmt_rx_lim_ch2.
+            RX_LIM: u9,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60016068
+        /// RMT_SYS_CONF_REG.
+        pub const SYS_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_apb_fifo_mask.
+            APB_FIFO_MASK: u1,
+            /// reg_mem_clk_force_on.
+            MEM_CLK_FORCE_ON: u1,
+            /// reg_rmt_mem_force_pd.
+            MEM_FORCE_PD: u1,
+            /// reg_rmt_mem_force_pu.
+            MEM_FORCE_PU: u1,
+            /// reg_rmt_sclk_div_num.
+            SCLK_DIV_NUM: u8,
+            /// reg_rmt_sclk_div_a.
+            SCLK_DIV_A: u6,
+            /// reg_rmt_sclk_div_b.
+            SCLK_DIV_B: u6,
+            /// reg_rmt_sclk_sel.
+            SCLK_SEL: u2,
+            /// reg_rmt_sclk_active.
+            SCLK_ACTIVE: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// reg_clk_en.
+            CLK_EN: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6001606c
+        /// RMT_TX_SIM_REG.
+        pub const TX_SIM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rmt_tx_sim_ch0.
+            TX_SIM_CH0: u1,
+            /// reg_rmt_tx_sim_ch1.
+            TX_SIM_CH1: u1,
+            /// reg_rmt_tx_sim_en.
+            TX_SIM_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60016070
+        /// RMT_REF_CNT_RST_REG.
+        pub const REF_CNT_RST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_ref_cnt_rst_ch0.
+            CH0: u1,
+            /// reg_ref_cnt_rst_ch1.
+            CH1: u1,
+            /// reg_ref_cnt_rst_ch2.
+            CH2: u1,
+            /// reg_ref_cnt_rst_ch3.
+            CH3: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x600160cc
+        /// RMT_DATE_REG.
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xcc);
+    };
+
+    /// Hardware random number generator
+    pub const RNG = struct {
+        pub const base_address = 0x60026000;
+
+        /// address: 0x600260b0
+        /// Random number data
+        pub const DATA = @intToPtr(*volatile u32, base_address + 0xb0);
+    };
+
+    /// RSA (Rivest Shamir Adleman) Accelerator
+    pub const RSA = struct {
+        pub const base_address = 0x6003c000;
+
+        /// address: 0x6003c000
+        /// The memory that stores M
+        pub const M_MEM = @intToPtr(*volatile [16]u8, base_address + 0x0);
+
+        /// address: 0x6003c200
+        /// The memory that stores Z
+        pub const Z_MEM = @intToPtr(*volatile [16]u8, base_address + 0x200);
+
+        /// address: 0x6003c400
+        /// The memory that stores Y
+        pub const Y_MEM = @intToPtr(*volatile [16]u8, base_address + 0x400);
+
+        /// address: 0x6003c600
+        /// The memory that stores X
+        pub const X_MEM = @intToPtr(*volatile [16]u8, base_address + 0x600);
+
+        /// address: 0x6003c800
+        /// RSA M_prime register
+        pub const M_PRIME = @intToPtr(*volatile u32, base_address + 0x800);
+
+        /// address: 0x6003c804
+        /// RSA mode register
+        pub const MODE = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x804);
+
+        /// address: 0x6003c808
+        /// RSA query clean register
+        pub const QUERY_CLEAN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x808);
+
+        /// address: 0x6003c80c
+        /// RSA modular exponentiation trigger register.
+        pub const SET_START_MODEXP = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x80c);
+
+        /// address: 0x6003c810
+        /// RSA modular multiplication trigger register.
+        pub const SET_START_MODMULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x810);
+
+        /// address: 0x6003c814
+        /// RSA normal multiplication trigger register.
+        pub const SET_START_MULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x814);
+
+        /// address: 0x6003c818
+        /// RSA query idle register
+        pub const QUERY_IDLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x818);
+
+        /// address: 0x6003c81c
+        /// RSA interrupt clear register
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// set this bit to clear RSA interrupt.
+            CLEAR_INTERRUPT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x81c);
+
+        /// address: 0x6003c820
+        /// RSA constant time option register
+        pub const CONSTANT_TIME = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x820);
+
+        /// address: 0x6003c824
+        /// RSA search option
+        pub const SEARCH_ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x824);
+
+        /// address: 0x6003c828
+        /// RSA search position configure register
+        pub const SEARCH_POS = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x828);
+
+        /// address: 0x6003c82c
+        /// RSA interrupt enable register
+        pub const INT_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x82c);
+
+        /// address: 0x6003c830
+        /// RSA version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x830);
+    };
+
+    /// Real-Time Clock Control
+    pub const RTC_CNTL = struct {
+        pub const base_address = 0x60008000;
+
+        /// address: 0x60008000
+        /// rtc configure register
+        pub const OPTIONS0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall
+            /// APP CPU
+            SW_STALL_APPCPU_C0: u2,
+            /// {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall
+            /// PRO CPU
+            SW_STALL_PROCPU_C0: u2,
+            /// APP CPU SW reset
+            SW_APPCPU_RST: u1,
+            /// PRO CPU SW reset
+            SW_PROCPU_RST: u1,
+            /// BB_I2C force power down
+            BB_I2C_FORCE_PD: u1,
+            /// BB_I2C force power up
+            BB_I2C_FORCE_PU: u1,
+            /// BB_PLL _I2C force power down
+            BBPLL_I2C_FORCE_PD: u1,
+            /// BB_PLL_I2C force power up
+            BBPLL_I2C_FORCE_PU: u1,
+            /// BB_PLL force power down
+            BBPLL_FORCE_PD: u1,
+            /// BB_PLL force power up
+            BBPLL_FORCE_PU: u1,
+            /// crystall force power down
+            XTL_FORCE_PD: u1,
+            /// crystall force power up
+            XTL_FORCE_PU: u1,
+            /// wait bias_sleep and current source wakeup
+            XTL_EN_WAIT: u4,
+            reserved0: u1,
+            reserved1: u1,
+            /// analog configure
+            XTL_EXT_CTR_SEL: u3,
+            /// analog configure
+            XTL_FORCE_ISO: u1,
+            /// analog configure
+            PLL_FORCE_ISO: u1,
+            /// analog configure
+            ANALOG_FORCE_ISO: u1,
+            /// analog configure
+            XTL_FORCE_NOISO: u1,
+            /// analog configure
+            PLL_FORCE_NOISO: u1,
+            /// analog configure
+            ANALOG_FORCE_NOISO: u1,
+            /// digital wrap force reset in deep sleep
+            DG_WRAP_FORCE_RST: u1,
+            /// digital core force no reset in deep sleep
+            DG_WRAP_FORCE_NORST: u1,
+            /// SW system reset
+            SW_SYS_RST: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60008004
+        /// rtc configure register
+        pub const SLP_TIMER0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// configure the sleep time
+            SLP_VAL_LO: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60008008
+        /// rtc configure register
+        pub const SLP_TIMER1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// RTC sleep timer high 16 bits
+            SLP_VAL_HI: u16,
+            /// timer alarm enable bit
+            RTC_MAIN_TIMER_ALARM_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000800c
+        /// rtc configure register
+        pub const TIME_UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            /// Enable to record system stall time
+            TIMER_SYS_STALL: u1,
+            /// Enable to record 40M XTAL OFF time
+            TIMER_XTL_OFF: u1,
+            /// enable to record system reset time
+            TIMER_SYS_RST: u1,
+            reserved27: u1,
+            /// Set 1: to update register with RTC timer
+            RTC_TIME_UPDATE: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60008010
+        /// rtc configure register
+        pub const TIME_LOW0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// RTC timer low 32 bits
+            RTC_TIMER_VALUE0_LOW: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x60008014
+        /// rtc configure register
+        pub const TIME_HIGH0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// RTC timer high 16 bits
+            RTC_TIMER_VALUE0_HIGH: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60008018
+        /// rtc configure register
+        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// rtc software interrupt to main cpu
+            RTC_SW_CPU_INT: u1,
+            /// clear rtc sleep reject cause
+            RTC_SLP_REJECT_CAUSE_CLR: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            /// 1: APB to RTC using bridge
+            APB2RTC_BRIDGE_SEL: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            /// SDIO active indication
+            SDIO_ACTIVE_IND: u1,
+            /// leep wakeup bit
+            SLP_WAKEUP: u1,
+            /// leep reject bit
+            SLP_REJECT: u1,
+            /// sleep enable bit
+            SLEEP_EN: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000801c
+        /// rtc configure register
+        pub const TIMER1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// CPU stall enable bit
+            CPU_STALL_EN: u1,
+            /// CPU stall wait cycles in fast_clk_rtc
+            CPU_STALL_WAIT: u5,
+            /// CK8M wait cycles in slow_clk_rtc
+            CK8M_WAIT: u8,
+            /// XTAL wait cycles in slow_clk_rtc
+            XTL_BUF_WAIT: u10,
+            /// PLL wait cycles in slow_clk_rtc
+            PLL_BUF_WAIT: u8,
+        }), base_address + 0x1c);
+
+        /// address: 0x60008020
+        /// rtc configure register
+        pub const TIMER2 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            /// minimal cycles in slow_clk_rtc for CK8M in power down state
+            MIN_TIME_CK8M_OFF: u8,
+        }), base_address + 0x20);
+
+        /// address: 0x60008024
+        /// rtc configure register
+        pub const TIMER3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// wifi power domain wakeup time
+            WIFI_WAIT_TIMER: u9,
+            /// wifi power domain power on time
+            WIFI_POWERUP_TIMER: u7,
+            /// bt power domain wakeup time
+            BT_WAIT_TIMER: u9,
+            /// bt power domain power on time
+            BT_POWERUP_TIMER: u7,
+        }), base_address + 0x24);
+
+        /// address: 0x60008028
+        /// rtc configure register
+        pub const TIMER4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// cpu top power domain wakeup time
+            CPU_TOP_WAIT_TIMER: u9,
+            /// cpu top power domain power on time
+            CPU_TOP_POWERUP_TIMER: u7,
+            /// digital wrap power domain wakeup time
+            DG_WRAP_WAIT_TIMER: u9,
+            /// digital wrap power domain power on time
+            DG_WRAP_POWERUP_TIMER: u7,
+        }), base_address + 0x28);
+
+        /// address: 0x6000802c
+        /// rtc configure register
+        pub const TIMER5 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// minimal sleep cycles in slow_clk_rtc
+            MIN_SLP_VAL: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60008030
+        /// rtc configure register
+        pub const TIMER6 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            /// digital peri power domain wakeup time
+            DG_PERI_WAIT_TIMER: u9,
+            /// digital peri power domain power on time
+            DG_PERI_POWERUP_TIMER: u7,
+        }), base_address + 0x30);
+
+        /// address: 0x60008034
+        /// rtc configure register
+        pub const ANA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// force no bypass i2c power on reset
+            RESET_POR_FORCE_PD: u1,
+            /// force bypass i2c power on reset
+            RESET_POR_FORCE_PU: u1,
+            /// enable glitch reset
+            GLITCH_RST_EN: u1,
+            reserved18: u1,
+            /// PLLA force power up
+            SAR_I2C_PU: u1,
+            /// PLLA force power down
+            PLLA_FORCE_PD: u1,
+            /// PLLA force power up
+            PLLA_FORCE_PU: u1,
+            /// start BBPLL calibration during sleep
+            BBPLL_CAL_SLP_START: u1,
+            /// 1: PVTMON power up
+            PVTMON_PU: u1,
+            /// 1: TXRF_I2C power up
+            TXRF_I2C_PU: u1,
+            /// 1: RFRX_PBUS power up
+            RFRX_PBUS_PU: u1,
+            reserved19: u1,
+            /// 1: CKGEN_I2C power up
+            CKGEN_I2C_PU: u1,
+            /// power up pll i2c
+            PLL_I2C_PU: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60008038
+        /// rtc configure register
+        pub const RESET_STATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reset cause of PRO CPU
+            RESET_CAUSE_PROCPU: u6,
+            /// reset cause of APP CPU
+            RESET_CAUSE_APPCPU: u6,
+            /// APP CPU state vector sel
+            STAT_VECTOR_SEL_APPCPU: u1,
+            /// PRO CPU state vector sel
+            STAT_VECTOR_SEL_PROCPU: u1,
+            /// PRO CPU reset_flag
+            ALL_RESET_FLAG_PROCPU: u1,
+            /// APP CPU reset flag
+            ALL_RESET_FLAG_APPCPU: u1,
+            /// clear PRO CPU reset_flag
+            ALL_RESET_FLAG_CLR_PROCPU: u1,
+            /// clear APP CPU reset flag
+            ALL_RESET_FLAG_CLR_APPCPU: u1,
+            /// APPCPU OcdHaltOnReset
+            OCD_HALT_ON_RESET_APPCPU: u1,
+            /// PROCPU OcdHaltOnReset
+            OCD_HALT_ON_RESET_PROCPU: u1,
+            /// configure jtag reset configure
+            JTAG_RESET_FLAG_PROCPU: u1,
+            /// configure jtag reset configure
+            JTAG_RESET_FLAG_APPCPU: u1,
+            /// configure jtag reset configure
+            JTAG_RESET_FLAG_CLR_PROCPU: u1,
+            /// configure jtag reset configure
+            JTAG_RESET_FLAG_CLR_APPCPU: u1,
+            /// configure dreset configure
+            RTC_DRESET_MASK_APPCPU: u1,
+            /// configure dreset configure
+            RTC_DRESET_MASK_PROCPU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6000803c
+        /// rtc configure register
+        pub const WAKEUP_STATE = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// wakeup enable bitmap
+            RTC_WAKEUP_ENA: u17,
+        }), base_address + 0x3c);
+
+        /// address: 0x60008040
+        /// rtc configure register
+        pub const INT_ENA_RTC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// enable sleep wakeup interrupt
+            SLP_WAKEUP_INT_ENA: u1,
+            /// enable sleep reject interrupt
+            SLP_REJECT_INT_ENA: u1,
+            reserved0: u1,
+            /// enable RTC WDT interrupt
+            RTC_WDT_INT_ENA: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// enable brown out interrupt
+            RTC_BROWN_OUT_INT_ENA: u1,
+            /// enable RTC main timer interrupt
+            RTC_MAIN_TIMER_INT_ENA: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// enable super watch dog interrupt
+            RTC_SWD_INT_ENA: u1,
+            /// enable xtal32k_dead interrupt
+            RTC_XTAL32K_DEAD_INT_ENA: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// enbale gitch det interrupt
+            RTC_GLITCH_DET_INT_ENA: u1,
+            /// enbale bbpll cal end interrupt
+            RTC_BBPLL_CAL_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60008044
+        /// rtc configure register
+        pub const INT_RAW_RTC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// sleep wakeup interrupt raw
+            SLP_WAKEUP_INT_RAW: u1,
+            /// sleep reject interrupt raw
+            SLP_REJECT_INT_RAW: u1,
+            reserved0: u1,
+            /// RTC WDT interrupt raw
+            RTC_WDT_INT_RAW: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// brown out interrupt raw
+            RTC_BROWN_OUT_INT_RAW: u1,
+            /// RTC main timer interrupt raw
+            RTC_MAIN_TIMER_INT_RAW: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// super watch dog interrupt raw
+            RTC_SWD_INT_RAW: u1,
+            /// xtal32k dead detection interrupt raw
+            RTC_XTAL32K_DEAD_INT_RAW: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// glitch_det_interrupt_raw
+            RTC_GLITCH_DET_INT_RAW: u1,
+            /// bbpll cal end interrupt state
+            RTC_BBPLL_CAL_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60008048
+        /// rtc configure register
+        pub const INT_ST_RTC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// sleep wakeup interrupt state
+            SLP_WAKEUP_INT_ST: u1,
+            /// sleep reject interrupt state
+            SLP_REJECT_INT_ST: u1,
+            reserved0: u1,
+            /// RTC WDT interrupt state
+            RTC_WDT_INT_ST: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// brown out interrupt state
+            RTC_BROWN_OUT_INT_ST: u1,
+            /// RTC main timer interrupt state
+            RTC_MAIN_TIMER_INT_ST: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// super watch dog interrupt state
+            RTC_SWD_INT_ST: u1,
+            /// xtal32k dead detection interrupt state
+            RTC_XTAL32K_DEAD_INT_ST: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// glitch_det_interrupt state
+            RTC_GLITCH_DET_INT_ST: u1,
+            /// bbpll cal end interrupt state
+            RTC_BBPLL_CAL_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6000804c
+        /// rtc configure register
+        pub const INT_CLR_RTC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Clear sleep wakeup interrupt state
+            SLP_WAKEUP_INT_CLR: u1,
+            /// Clear sleep reject interrupt state
+            SLP_REJECT_INT_CLR: u1,
+            reserved0: u1,
+            /// Clear RTC WDT interrupt state
+            RTC_WDT_INT_CLR: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// Clear brown out interrupt state
+            RTC_BROWN_OUT_INT_CLR: u1,
+            /// Clear RTC main timer interrupt state
+            RTC_MAIN_TIMER_INT_CLR: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// Clear super watch dog interrupt state
+            RTC_SWD_INT_CLR: u1,
+            /// Clear RTC WDT interrupt state
+            RTC_XTAL32K_DEAD_INT_CLR: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// Clear glitch det interrupt state
+            RTC_GLITCH_DET_INT_CLR: u1,
+            /// clear bbpll cal end interrupt state
+            RTC_BBPLL_CAL_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60008050
+        /// rtc configure register
+        pub const STORE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH0: u32,
+        }), base_address + 0x50);
+
+        /// address: 0x60008054
+        /// rtc configure register
+        pub const STORE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH1: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x60008058
+        /// rtc configure register
+        pub const STORE2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH2: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6000805c
+        /// rtc configure register
+        pub const STORE3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH3: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x60008060
+        /// rtc configure register
+        pub const EXT_XTL_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// xtal 32k watch dog enable
+            XTAL32K_WDT_EN: u1,
+            /// xtal 32k watch dog clock force on
+            XTAL32K_WDT_CLK_FO: u1,
+            /// xtal 32k watch dog sw reset
+            XTAL32K_WDT_RESET: u1,
+            /// xtal 32k external xtal clock force on
+            XTAL32K_EXT_CLK_FO: u1,
+            /// xtal 32k switch to back up clock when xtal is dead
+            XTAL32K_AUTO_BACKUP: u1,
+            /// xtal 32k restart xtal when xtal is dead
+            XTAL32K_AUTO_RESTART: u1,
+            /// xtal 32k switch back xtal when xtal is restarted
+            XTAL32K_AUTO_RETURN: u1,
+            /// Xtal 32k xpd control by sw or fsm
+            XTAL32K_XPD_FORCE: u1,
+            /// apply an internal clock to help xtal 32k to start
+            ENCKINIT_XTAL_32K: u1,
+            /// 0: single-end buffer 1: differential buffer
+            DBUF_XTAL_32K: u1,
+            /// xtal_32k gm control
+            DGM_XTAL_32K: u3,
+            /// DRES_XTAL_32K
+            DRES_XTAL_32K: u3,
+            /// XPD_XTAL_32K
+            XPD_XTAL_32K: u1,
+            /// DAC_XTAL_32K
+            DAC_XTAL_32K: u3,
+            /// state of 32k_wdt
+            RTC_WDT_STATE: u3,
+            /// XTAL_32K sel. 0: external XTAL_32K
+            RTC_XTAL32K_GPIO_SEL: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// 0: power down XTAL at high level
+            XTL_EXT_CTR_LV: u1,
+            /// enable gpio configure xtal power on
+            XTL_EXT_CTR_EN: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60008064
+        /// rtc configure register
+        pub const EXT_WAKEUP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// enable filter for gpio wakeup event
+            GPIO_WAKEUP_FILTER: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60008068
+        /// rtc configure register
+        pub const SLP_REJECT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// sleep reject enable
+            RTC_SLEEP_REJECT_ENA: u18,
+            /// enable reject for light sleep
+            LIGHT_SLP_REJECT_EN: u1,
+            /// enable reject for deep sleep
+            DEEP_SLP_REJECT_EN: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6000806c
+        /// rtc configure register
+        pub const CPU_PERIOD_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// CPU sel option
+            RTC_CPUSEL_CONF: u1,
+            /// CPU clk sel option
+            RTC_CPUPERIOD_SEL: u2,
+        }), base_address + 0x6c);
+
+        /// address: 0x60008070
+        /// rtc configure register
+        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// efuse_clk_force_gating
+            EFUSE_CLK_FORCE_GATING: u1,
+            /// efuse_clk_force_nogating
+            EFUSE_CLK_FORCE_NOGATING: u1,
+            /// used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel
+            CK8M_DIV_SEL_VLD: u1,
+            /// CK8M_D256_OUT divider. 00: div128
+            CK8M_DIV: u2,
+            /// disable CK8M and CK8M_D256_OUT
+            ENB_CK8M: u1,
+            /// 1: CK8M_D256_OUT is actually CK8M
+            ENB_CK8M_DIV: u1,
+            /// enable CK_XTAL_32K for digital core (no relationship with RTC core)
+            DIG_XTAL32K_EN: u1,
+            /// enable CK8M_D256_OUT for digital core (no relationship with RTC core)
+            DIG_CLK8M_D256_EN: u1,
+            /// enable CK8M for digital core (no relationship with RTC core)
+            DIG_CLK8M_EN: u1,
+            reserved1: u1,
+            /// divider = reg_ck8m_div_sel + 1
+            CK8M_DIV_SEL: u3,
+            /// XTAL force no gating during sleep
+            XTAL_FORCE_NOGATING: u1,
+            /// CK8M force no gating during sleep
+            CK8M_FORCE_NOGATING: u1,
+            /// CK8M_DFREQ
+            CK8M_DFREQ: u8,
+            /// CK8M force power down
+            CK8M_FORCE_PD: u1,
+            /// CK8M force power up
+            CK8M_FORCE_PU: u1,
+            /// force enable xtal clk gating
+            XTAL_GLOBAL_FORCE_GATING: u1,
+            /// force bypass xtal clk gating
+            XTAL_GLOBAL_FORCE_NOGATING: u1,
+            /// fast_clk_rtc sel. 0: XTAL div 4
+            FAST_CLK_RTC_SEL: u1,
+            /// slelect rtc slow clk
+            ANA_CLK_RTC_SEL: u2,
+        }), base_address + 0x70);
+
+        /// address: 0x60008074
+        /// rtc configure register
+        pub const SLOW_CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            /// used to sync div bus. clear vld before set reg_rtc_ana_clk_div
+            RTC_ANA_CLK_DIV_VLD: u1,
+            /// the clk divider num of RTC_CLK
+            RTC_ANA_CLK_DIV: u8,
+            /// flag rtc_slow_clk_next_edge
+            RTC_SLOW_CLK_NEXT_EDGE: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60008078
+        /// rtc configure register
+        pub const SDIO_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer count to apply reg_sdio_dcap after sdio power on
+            SDIO_TIMER_TARGET: u8,
+            reserved0: u1,
+            /// Tieh = 1 mode drive ability. Initially set to 0 to limit charge current
+            SDIO_DTHDRV: u2,
+            /// ability to prevent LDO from overshoot
+            SDIO_DCAP: u2,
+            /// add resistor from ldo output to ground. 0: no res
+            SDIO_INITI: u2,
+            /// 0 to set init[1:0]=0
+            SDIO_EN_INITI: u1,
+            /// tune current limit threshold when tieh = 0. About 800mA/(8+d)
+            SDIO_DCURLIM: u3,
+            /// select current limit mode
+            SDIO_MODECURLIM: u1,
+            /// enable current limit
+            SDIO_ENCURLIM: u1,
+            /// power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
+            SDIO_REG_PD_EN: u1,
+            /// 1: use SW option to control SDIO_REG
+            SDIO_FORCE: u1,
+            /// SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
+            SDIO_TIEH: u1,
+            /// read only register for REG1P8_READY
+            _1P8_READY: u1,
+            /// SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
+            DREFL_SDIO: u2,
+            /// SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
+            DREFM_SDIO: u2,
+            /// SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
+            DREFH_SDIO: u2,
+            XPD_SDIO: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6000807c
+        /// rtc configure register
+        pub const BIAS_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            DG_VDD_DRV_B_SLP: u8,
+            DG_VDD_DRV_B_SLP_EN: u1,
+            reserved0: u1,
+            /// bias buf when rtc in normal work state
+            BIAS_BUF_IDLE: u1,
+            /// bias buf when rtc in wakeup state
+            BIAS_BUF_WAKE: u1,
+            /// bias buf when rtc in sleep state
+            BIAS_BUF_DEEP_SLP: u1,
+            /// bias buf when rtc in monitor state
+            BIAS_BUF_MONITOR: u1,
+            /// xpd cur when rtc in sleep_state
+            PD_CUR_DEEP_SLP: u1,
+            /// xpd cur when rtc in monitor state
+            PD_CUR_MONITOR: u1,
+            /// bias_sleep when rtc in sleep_state
+            BIAS_SLEEP_DEEP_SLP: u1,
+            /// bias_sleep when rtc in monitor state
+            BIAS_SLEEP_MONITOR: u1,
+            /// DBG_ATTEN when rtc in sleep state
+            DBG_ATTEN_DEEP_SLP: u4,
+            /// DBG_ATTEN when rtc in monitor state
+            DBG_ATTEN_MONITOR: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x60008080
+        /// rtc configure register
+        pub const RTC_CNTL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            /// software enable digital regulator cali
+            DIG_REG_CAL_EN: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            /// SCK_DCAP
+            SCK_DCAP: u8,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            /// RTC_DBOOST force power down
+            DBOOST_FORCE_PD: u1,
+            /// RTC_DBOOST force power up
+            DBOOST_FORCE_PU: u1,
+            /// RTC_REG force power down (for RTC_REG power down means decrease the voltage to
+            /// 0.8v or lower )
+            REGULATOR_FORCE_PD: u1,
+            /// RTC_REG force power up
+            REGULATOR_FORCE_PU: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x60008084
+        /// rtc configure register
+        pub const PWC = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            /// rtc pad force hold
+            RTC_PAD_FORCE_HOLD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x60008088
+        /// rtc configure register
+        pub const DIG_PWC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// vdd_spi drv's software value
+            VDD_SPI_PWR_DRV: u2,
+            /// vdd_spi drv use software value
+            VDD_SPI_PWR_FORCE: u1,
+            /// memories in digital core force PD in sleep
+            LSLP_MEM_FORCE_PD: u1,
+            /// memories in digital core force PU in sleep
+            LSLP_MEM_FORCE_PU: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// bt force power down
+            BT_FORCE_PD: u1,
+            /// bt force power up
+            BT_FORCE_PU: u1,
+            /// digital peri force power down
+            DG_PERI_FORCE_PD: u1,
+            /// digital peri force power up
+            DG_PERI_FORCE_PU: u1,
+            /// fastmemory retention mode in sleep
+            RTC_FASTMEM_FORCE_LPD: u1,
+            /// fastmemory donlt entry retention mode in sleep
+            RTC_FASTMEM_FORCE_LPU: u1,
+            /// wifi force power down
+            WIFI_FORCE_PD: u1,
+            /// wifi force power up
+            WIFI_FORCE_PU: u1,
+            /// digital core force power down
+            DG_WRAP_FORCE_PD: u1,
+            /// digital core force power up
+            DG_WRAP_FORCE_PU: u1,
+            /// cpu core force power down
+            CPU_TOP_FORCE_PD: u1,
+            /// cpu force power up
+            CPU_TOP_FORCE_PU: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// enable power down bt in sleep
+            BT_PD_EN: u1,
+            /// enable power down digital peri in sleep
+            DG_PERI_PD_EN: u1,
+            /// enable power down cpu in sleep
+            CPU_TOP_PD_EN: u1,
+            /// enable power down wifi in sleep
+            WIFI_PD_EN: u1,
+            /// enable power down digital wrap in sleep
+            DG_WRAP_PD_EN: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x6000808c
+        /// rtc configure register
+        pub const DIG_ISO = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            /// DIG_ISO force off
+            FORCE_OFF: u1,
+            /// DIG_ISO force on
+            FORCE_ON: u1,
+            /// read only register to indicate digital pad auto-hold status
+            DG_PAD_AUTOHOLD: u1,
+            /// wtite only register to clear digital pad auto-hold
+            CLR_DG_PAD_AUTOHOLD: u1,
+            /// digital pad enable auto-hold
+            DG_PAD_AUTOHOLD_EN: u1,
+            /// digital pad force no ISO
+            DG_PAD_FORCE_NOISO: u1,
+            /// digital pad force ISO
+            DG_PAD_FORCE_ISO: u1,
+            /// digital pad force un-hold
+            DG_PAD_FORCE_UNHOLD: u1,
+            /// digital pad force hold
+            DG_PAD_FORCE_HOLD: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            /// bt force ISO
+            BT_FORCE_ISO: u1,
+            /// bt force no ISO
+            BT_FORCE_NOISO: u1,
+            /// Digital peri force ISO
+            DG_PERI_FORCE_ISO: u1,
+            /// digital peri force no ISO
+            DG_PERI_FORCE_NOISO: u1,
+            /// cpu force ISO
+            CPU_TOP_FORCE_ISO: u1,
+            /// cpu force no ISO
+            CPU_TOP_FORCE_NOISO: u1,
+            /// wifi force ISO
+            WIFI_FORCE_ISO: u1,
+            /// wifi force no ISO
+            WIFI_FORCE_NOISO: u1,
+            /// digital core force ISO
+            DG_WRAP_FORCE_ISO: u1,
+            /// digital core force no ISO
+            DG_WRAP_FORCE_NOISO: u1,
+        }), base_address + 0x8c);
+
+        /// address: 0x60008090
+        /// rtc configure register
+        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// chip reset siginal pulse width
+            WDT_CHIP_RESET_WIDTH: u8,
+            /// wdt reset whole chip enable
+            WDT_CHIP_RESET_EN: u1,
+            /// pause WDT in sleep
+            WDT_PAUSE_IN_SLP: u1,
+            /// enable WDT reset APP CPU
+            WDT_APPCPU_RESET_EN: u1,
+            /// enable WDT reset PRO CPU
+            WDT_PROCPU_RESET_EN: u1,
+            /// enable WDT in flash boot
+            WDT_FLASHBOOT_MOD_EN: u1,
+            /// system reset counter length
+            WDT_SYS_RESET_LENGTH: u3,
+            /// CPU reset counter length
+            WDT_CPU_RESET_LENGTH: u3,
+            /// 1: interrupt stage en
+            WDT_STG3: u3,
+            /// 1: interrupt stage en
+            WDT_STG2: u3,
+            /// 1: interrupt stage en
+            WDT_STG1: u3,
+            /// 1: interrupt stage en
+            WDT_STG0: u3,
+            /// enable rtc wdt
+            WDT_EN: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x60008094
+        /// rtc configure register
+        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the hold time of stage0
+            WDT_STG0_HOLD: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x60008098
+        /// rtc configure register
+        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the hold time of stage1
+            WDT_STG1_HOLD: u32,
+        }), base_address + 0x98);
+
+        /// address: 0x6000809c
+        /// rtc configure register
+        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the hold time of stage2
+            WDT_STG2_HOLD: u32,
+        }), base_address + 0x9c);
+
+        /// address: 0x600080a0
+        /// rtc configure register
+        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the hold time of stage3
+            WDT_STG3_HOLD: u32,
+        }), base_address + 0xa0);
+
+        /// address: 0x600080a4
+        /// rtc configure register
+        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// sw feed rtc wdt
+            RTC_WDT_FEED: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600080a8
+        /// rtc configure register
+        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the key of rtc wdt
+            WDT_WKEY: u32,
+        }), base_address + 0xa8);
+
+        /// address: 0x600080ac
+        /// rtc configure register
+        pub const SWD_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// swd reset flag
+            SWD_RESET_FLAG: u1,
+            /// swd interrupt for feeding
+            SWD_FEED_INT: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// Bypass swd rst
+            SWD_BYPASS_RST: u1,
+            /// adjust signal width send to swd
+            SWD_SIGNAL_WIDTH: u10,
+            /// reset swd reset flag
+            SWD_RST_FLAG_CLR: u1,
+            /// Sw feed swd
+            SWD_FEED: u1,
+            /// disabel SWD
+            SWD_DISABLE: u1,
+            /// automatically feed swd when int comes
+            SWD_AUTO_FEED_EN: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600080b0
+        /// rtc configure register
+        pub const SWD_WPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the key of super wdt
+            SWD_WKEY: u32,
+        }), base_address + 0xb0);
+
+        /// address: 0x600080b4
+        /// rtc configure register
+        pub const SW_CPU_STALL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            /// {reg_sw_stall_appcpu_c1[5:0]
+            SW_STALL_APPCPU_C1: u6,
+            /// stall cpu by software
+            SW_STALL_PROCPU_C1: u6,
+        }), base_address + 0xb4);
+
+        /// address: 0x600080b8
+        /// rtc configure register
+        pub const STORE4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH4: u32,
+        }), base_address + 0xb8);
+
+        /// address: 0x600080bc
+        /// rtc configure register
+        pub const STORE5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH5: u32,
+        }), base_address + 0xbc);
+
+        /// address: 0x600080c0
+        /// rtc configure register
+        pub const STORE6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH6: u32,
+        }), base_address + 0xc0);
+
+        /// address: 0x600080c4
+        /// rtc configure register
+        pub const STORE7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reserved register
+            RTC_SCRATCH7: u32,
+        }), base_address + 0xc4);
+
+        /// address: 0x600080c8
+        /// rtc configure register
+        pub const LOW_POWER_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// rom0 power down
+            XPD_ROM0: u1,
+            reserved0: u1,
+            /// External DCDC power down
+            XPD_DIG_DCDC: u1,
+            /// rtc peripheral iso
+            RTC_PERI_ISO: u1,
+            /// rtc peripheral power down
+            XPD_RTC_PERI: u1,
+            /// wifi iso
+            WIFI_ISO: u1,
+            /// wifi wrap power down
+            XPD_WIFI: u1,
+            /// digital wrap iso
+            DIG_ISO: u1,
+            /// digital wrap power down
+            XPD_DIG: u1,
+            /// touch should start to work
+            RTC_TOUCH_STATE_START: u1,
+            /// touch is about to working. Switch rtc main state
+            RTC_TOUCH_STATE_SWITCH: u1,
+            /// touch is in sleep state
+            RTC_TOUCH_STATE_SLP: u1,
+            /// touch is done
+            RTC_TOUCH_STATE_DONE: u1,
+            /// ulp/cocpu should start to work
+            RTC_COCPU_STATE_START: u1,
+            /// ulp/cocpu is about to working. Switch rtc main state
+            RTC_COCPU_STATE_SWITCH: u1,
+            /// ulp/cocpu is in sleep state
+            RTC_COCPU_STATE_SLP: u1,
+            /// ulp/cocpu is done
+            RTC_COCPU_STATE_DONE: u1,
+            /// no use any more
+            RTC_MAIN_STATE_XTAL_ISO: u1,
+            /// rtc main state machine is in states that pll should be running
+            RTC_MAIN_STATE_PLL_ON: u1,
+            /// rtc is ready to receive wake up trigger from wake up source
+            RTC_RDY_FOR_WAKEUP: u1,
+            /// rtc main state machine has been waited for some cycles
+            RTC_MAIN_STATE_WAIT_END: u1,
+            /// rtc main state machine is in the states of wakeup process
+            RTC_IN_WAKEUP_STATE: u1,
+            /// rtc main state machine is in the states of low power
+            RTC_IN_LOW_POWER_STATE: u1,
+            /// rtc main state machine is in wait 8m state
+            RTC_MAIN_STATE_IN_WAIT_8M: u1,
+            /// rtc main state machine is in wait pll state
+            RTC_MAIN_STATE_IN_WAIT_PLL: u1,
+            /// rtc main state machine is in wait xtal state
+            RTC_MAIN_STATE_IN_WAIT_XTL: u1,
+            /// rtc main state machine is in sleep state
+            RTC_MAIN_STATE_IN_SLP: u1,
+            /// rtc main state machine is in idle state
+            RTC_MAIN_STATE_IN_IDLE: u1,
+            /// rtc main state machine status
+            RTC_MAIN_STATE: u4,
+        }), base_address + 0xc8);
+
+        /// address: 0x600080cc
+        /// rtc configure register
+        pub const DIAG0 = @intToPtr(*volatile Mmio(32, packed struct {
+            RTC_LOW_POWER_DIAG1: u32,
+        }), base_address + 0xcc);
+
+        /// address: 0x600080d0
+        /// rtc configure register
+        pub const PAD_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the hold configure of rtc gpio0
+            RTC_GPIO_PIN0_HOLD: u1,
+            /// the hold configure of rtc gpio1
+            RTC_GPIO_PIN1_HOLD: u1,
+            /// the hold configure of rtc gpio2
+            RTC_GPIO_PIN2_HOLD: u1,
+            /// the hold configure of rtc gpio3
+            RTC_GPIO_PIN3_HOLD: u1,
+            /// the hold configure of rtc gpio4
+            RTC_GPIO_PIN4_HOLD: u1,
+            /// the hold configure of rtc gpio5
+            RTC_GPIO_PIN5_HOLD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x600080d4
+        /// rtc configure register
+        pub const DIG_PAD_HOLD = @intToPtr(*volatile u32, base_address + 0xd4);
+
+        /// address: 0x600080d8
+        /// rtc configure register
+        pub const BROWN_OUT = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// brown out interrupt wait cycles
+            INT_WAIT: u10,
+            /// enable close flash when brown out happens
+            CLOSE_FLASH_ENA: u1,
+            /// enable power down RF when brown out happens
+            PD_RF_ENA: u1,
+            /// brown out reset wait cycles
+            RST_WAIT: u10,
+            /// enable brown out reset
+            RST_ENA: u1,
+            /// 1: 4-pos reset
+            RST_SEL: u1,
+            /// brown_out origin reset enable
+            ANA_RST_EN: u1,
+            /// clear brown out counter
+            CNT_CLR: u1,
+            /// enable brown out
+            ENA: u1,
+            /// the flag of brown det from analog
+            DET: u1,
+        }), base_address + 0xd8);
+
+        /// address: 0x600080dc
+        /// rtc configure register
+        pub const TIME_LOW1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// RTC timer low 32 bits
+            RTC_TIMER_VALUE1_LOW: u32,
+        }), base_address + 0xdc);
+
+        /// address: 0x600080e0
+        /// rtc configure register
+        pub const TIME_HIGH1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// RTC timer high 16 bits
+            RTC_TIMER_VALUE1_HIGH: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0xe0);
+
+        /// address: 0x600080e4
+        /// rtc configure register
+        pub const XTAL32K_CLK_FACTOR = @intToPtr(*volatile u32, base_address + 0xe4);
+
+        /// address: 0x600080e8
+        /// rtc configure register
+        pub const XTAL32K_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// cycles to wait to return noral xtal 32k
+            XTAL32K_RETURN_WAIT: u4,
+            /// cycles to wait to repower on xtal 32k
+            XTAL32K_RESTART_WAIT: u16,
+            /// If no clock detected for this amount of time
+            XTAL32K_WDT_TIMEOUT: u8,
+            /// if restarted xtal32k period is smaller than this
+            XTAL32K_STABLE_THRES: u4,
+        }), base_address + 0xe8);
+
+        /// address: 0x600080ec
+        /// rtc configure register
+        pub const USB_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// disable io_mux reset
+            IO_MUX_RESET_DISABLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+        }), base_address + 0xec);
+
+        /// address: 0x600080f0
+        /// RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG
+        pub const SLP_REJECT_CAUSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// sleep reject cause
+            REJECT_CAUSE: u18,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0xf0);
+
+        /// address: 0x600080f4
+        /// rtc configure register
+        pub const OPTION1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// force chip entry download mode
+            FORCE_DOWNLOAD_BOOT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xf4);
+
+        /// address: 0x600080f8
+        /// RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG
+        pub const SLP_WAKEUP_CAUSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// sleep wakeup cause
+            WAKEUP_CAUSE: u17,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0xf8);
+
+        /// address: 0x600080fc
+        /// rtc configure register
+        pub const ULP_CP_TIMER_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// sleep cycles for ULP-coprocessor timer
+            ULP_CP_TIMER_SLP_CYCLE: u24,
+        }), base_address + 0xfc);
+
+        /// address: 0x60008100
+        /// rtc configure register
+        pub const INT_ENA_RTC_W1TS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// enable sleep wakeup interrupt
+            SLP_WAKEUP_INT_ENA_W1TS: u1,
+            /// enable sleep reject interrupt
+            SLP_REJECT_INT_ENA_W1TS: u1,
+            reserved0: u1,
+            /// enable RTC WDT interrupt
+            RTC_WDT_INT_ENA_W1TS: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// enable brown out interrupt
+            RTC_BROWN_OUT_INT_ENA_W1TS: u1,
+            /// enable RTC main timer interrupt
+            RTC_MAIN_TIMER_INT_ENA_W1TS: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// enable super watch dog interrupt
+            RTC_SWD_INT_ENA_W1TS: u1,
+            /// enable xtal32k_dead interrupt
+            RTC_XTAL32K_DEAD_INT_ENA_W1TS: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// enbale gitch det interrupt
+            RTC_GLITCH_DET_INT_ENA_W1TS: u1,
+            /// enbale bbpll cal interrupt
+            RTC_BBPLL_CAL_INT_ENA_W1TS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x100);
+
+        /// address: 0x60008104
+        /// rtc configure register
+        pub const INT_ENA_RTC_W1TC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// clear sleep wakeup interrupt enable
+            SLP_WAKEUP_INT_ENA_W1TC: u1,
+            /// clear sleep reject interrupt enable
+            SLP_REJECT_INT_ENA_W1TC: u1,
+            reserved0: u1,
+            /// clear RTC WDT interrupt enable
+            RTC_WDT_INT_ENA_W1TC: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// clear brown out interrupt enable
+            RTC_BROWN_OUT_INT_ENA_W1TC: u1,
+            /// Clear RTC main timer interrupt enable
+            RTC_MAIN_TIMER_INT_ENA_W1TC: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// clear super watch dog interrupt enable
+            RTC_SWD_INT_ENA_W1TC: u1,
+            /// clear xtal32k_dead interrupt enable
+            RTC_XTAL32K_DEAD_INT_ENA_W1TC: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// clear gitch det interrupt enable
+            RTC_GLITCH_DET_INT_ENA_W1TC: u1,
+            /// clear bbpll cal interrupt enable
+            RTC_BBPLL_CAL_INT_ENA_W1TC: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x104);
+
+        /// address: 0x60008108
+        /// rtc configure register
+        pub const RETENTION_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// Retention clk sel
+            RETENTION_CLK_SEL: u1,
+            /// Retention done wait time
+            RETENTION_DONE_WAIT: u3,
+            /// Retention clkoff wait time
+            RETENTION_CLKOFF_WAIT: u4,
+            /// enable cpu retention when light sleep
+            RETENTION_EN: u1,
+            /// wait cycles for rention operation
+            RETENTION_WAIT: u5,
+        }), base_address + 0x108);
+
+        /// address: 0x6000810c
+        /// rtc configure register
+        pub const FIB_SEL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// select use analog fib signal
+            RTC_FIB_SEL: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x10c);
+
+        /// address: 0x60008110
+        /// rtc configure register
+        pub const GPIO_WAKEUP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// rtc gpio wakeup flag
+            RTC_GPIO_WAKEUP_STATUS: u6,
+            /// clear rtc gpio wakeup flag
+            RTC_GPIO_WAKEUP_STATUS_CLR: u1,
+            /// enable rtc io clk gate
+            RTC_GPIO_PIN_CLK_GATE: u1,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN5_INT_TYPE: u3,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN4_INT_TYPE: u3,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN3_INT_TYPE: u3,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN2_INT_TYPE: u3,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN1_INT_TYPE: u3,
+            /// configure gpio wakeup type
+            RTC_GPIO_PIN0_INT_TYPE: u3,
+            /// enable wakeup from rtc gpio5
+            RTC_GPIO_PIN5_WAKEUP_ENABLE: u1,
+            /// enable wakeup from rtc gpio4
+            RTC_GPIO_PIN4_WAKEUP_ENABLE: u1,
+            /// enable wakeup from rtc gpio3
+            RTC_GPIO_PIN3_WAKEUP_ENABLE: u1,
+            /// enable wakeup from rtc gpio2
+            RTC_GPIO_PIN2_WAKEUP_ENABLE: u1,
+            /// enable wakeup from rtc gpio1
+            RTC_GPIO_PIN1_WAKEUP_ENABLE: u1,
+            /// enable wakeup from rtc gpio0
+            RTC_GPIO_PIN0_WAKEUP_ENABLE: u1,
+        }), base_address + 0x110);
+
+        /// address: 0x60008114
+        /// rtc configure register
+        pub const DBG_SEL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// use for debug
+            RTC_DEBUG_12M_NO_GATING: u1,
+            /// use for debug
+            RTC_DEBUG_BIT_SEL: u5,
+            /// use for debug
+            RTC_DEBUG_SEL0: u5,
+            /// use for debug
+            RTC_DEBUG_SEL1: u5,
+            /// use for debug
+            RTC_DEBUG_SEL2: u5,
+            /// use for debug
+            RTC_DEBUG_SEL3: u5,
+            /// use for debug
+            RTC_DEBUG_SEL4: u5,
+        }), base_address + 0x114);
+
+        /// address: 0x60008118
+        /// rtc configure register
+        pub const DBG_MAP = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            /// use for debug
+            RTC_GPIO_PIN5_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN4_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN3_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN2_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN1_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN0_MUX_SEL: u1,
+            /// use for debug
+            RTC_GPIO_PIN5_FUN_SEL: u4,
+            /// use for debug
+            RTC_GPIO_PIN4_FUN_SEL: u4,
+            /// use for debug
+            RTC_GPIO_PIN3_FUN_SEL: u4,
+            /// use for debug
+            RTC_GPIO_PIN2_FUN_SEL: u4,
+            /// use for debug
+            RTC_GPIO_PIN1_FUN_SEL: u4,
+            /// use for debug
+            RTC_GPIO_PIN0_FUN_SEL: u4,
+        }), base_address + 0x118);
+
+        /// address: 0x6000811c
+        /// rtc configure register
+        pub const SENSOR_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            /// reg_sar2_pwdet_cct
+            SAR2_PWDET_CCT: u3,
+            /// force power up SAR
+            FORCE_XPD_SAR: u2,
+        }), base_address + 0x11c);
+
+        /// address: 0x60008120
+        /// rtc configure register
+        pub const DBG_SAR_SEL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            /// use for debug
+            SAR_DEBUG_SEL: u5,
+        }), base_address + 0x120);
+
+        /// address: 0x60008124
+        /// rtc configure register
+        pub const PG_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            /// power glitch desense
+            POWER_GLITCH_DSENSE: u2,
+            /// force disable power glitch
+            POWER_GLITCH_FORCE_PD: u1,
+            /// force enable power glitch
+            POWER_GLITCH_FORCE_PU: u1,
+            /// use efuse value control power glitch enable
+            POWER_GLITCH_EFUSE_SEL: u1,
+            /// enable power glitch
+            POWER_GLITCH_EN: u1,
+        }), base_address + 0x124);
+
+        /// address: 0x600081fc
+        /// rtc configure register
+        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// verision
+            RTC_CNTL_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x1fc);
+    };
+
+    /// Sensitive
+    pub const SENSITIVE = struct {
+        pub const base_address = 0x600c1000;
+
+        /// address: 0x600c1000
+        /// SENSITIVE_ROM_TABLE_LOCK_REG
+        pub const ROM_TABLE_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0);
+
+        /// address: 0x600c1004
+        /// SENSITIVE_ROM_TABLE_REG
+        pub const ROM_TABLE = @intToPtr(*volatile u32, base_address + 0x4);
+
+        /// address: 0x600c1008
+        /// SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
+        pub const PRIVILEGE_MODE_SEL_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8);
+
+        /// address: 0x600c100c
+        /// SENSITIVE_PRIVILEGE_MODE_SEL_REG
+        pub const PRIVILEGE_MODE_SEL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xc);
+
+        /// address: 0x600c1010
+        /// SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
+        pub const APB_PERIPHERAL_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// apb_peripheral_access_lock
+            APB_PERIPHERAL_ACCESS_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x600c1014
+        /// SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
+        pub const APB_PERIPHERAL_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// apb_peripheral_access_split_burst
+            APB_PERIPHERAL_ACCESS_SPLIT_BURST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x600c1018
+        /// SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
+        pub const INTERNAL_SRAM_USAGE_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// internal_sram_usage_lock
+            INTERNAL_SRAM_USAGE_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x600c101c
+        /// SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
+        pub const INTERNAL_SRAM_USAGE_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// internal_sram_usage_cpu_cache
+            INTERNAL_SRAM_USAGE_CPU_CACHE: u1,
+            /// internal_sram_usage_cpu_sram
+            INTERNAL_SRAM_USAGE_CPU_SRAM: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x600c1020
+        /// SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
+        pub const INTERNAL_SRAM_USAGE_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// internal_sram_usage_mac_dump_sram
+            INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM: u3,
+            /// internal_sram_alloc_mac_dump
+            INTERNAL_SRAM_ALLOC_MAC_DUMP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x600c1024
+        /// SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
+        pub const INTERNAL_SRAM_USAGE_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// internal_sram_usage_log_sram
+            INTERNAL_SRAM_USAGE_LOG_SRAM: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x600c1028
+        /// SENSITIVE_CACHE_TAG_ACCESS_0_REG
+        pub const CACHE_TAG_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// cache_tag_access_lock
+            CACHE_TAG_ACCESS_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x600c102c
+        /// SENSITIVE_CACHE_TAG_ACCESS_1_REG
+        pub const CACHE_TAG_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// pro_i_tag_rd_acs
+            PRO_I_TAG_RD_ACS: u1,
+            /// pro_i_tag_wr_acs
+            PRO_I_TAG_WR_ACS: u1,
+            /// pro_d_tag_rd_acs
+            PRO_D_TAG_RD_ACS: u1,
+            /// pro_d_tag_wr_acs
+            PRO_D_TAG_WR_ACS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x600c1030
+        /// SENSITIVE_CACHE_MMU_ACCESS_0_REG
+        pub const CACHE_MMU_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// cache_mmu_access_lock
+            CACHE_MMU_ACCESS_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x600c1034
+        /// SENSITIVE_CACHE_MMU_ACCESS_1_REG
+        pub const CACHE_MMU_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// pro_mmu_rd_acs
+            PRO_MMU_RD_ACS: u1,
+            /// pro_mmu_wr_acs
+            PRO_MMU_WR_ACS: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x600c1038
+        /// SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_spi2_pms_constrain_lock
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x600c103c
+        /// SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x600c1040
+        /// SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_uchi0_pms_constrain_lock
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x600c1044
+        /// SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x600c1048
+        /// SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_i2s0_pms_constrain_lock
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x600c104c
+        /// SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x600c1050
+        /// SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_MAC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_mac_pms_constrain_lock
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x600c1054
+        /// SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_MAC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x600c1058
+        /// SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_backup_pms_constrain_lock
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x600c105c
+        /// SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x600c1060
+        /// SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_LC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_lc_pms_constrain_lock
+            DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x600c1064
+        /// SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_LC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x600c1068
+        /// SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_AES_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_aes_pms_constrain_lock
+            DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x600c106c
+        /// SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_AES_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x600c1070
+        /// SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_SHA_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_sha_pms_constrain_lock
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x600c1074
+        /// SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_SHA_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x600c1078
+        /// SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
+        pub const DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_adc_dac_pms_constrain_lock
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x600c107c
+        /// SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
+        pub const DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x600c1080
+        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
+        pub const DMA_APBPERI_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_pms_monitor_lock
+            DMA_APBPERI_PMS_MONITOR_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x600c1084
+        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
+        pub const DMA_APBPERI_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_pms_monitor_violate_clr
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR: u1,
+            /// dma_apbperi_pms_monitor_violate_en
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x600c1088
+        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
+        pub const DMA_APBPERI_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_pms_monitor_violate_intr
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR: u1,
+            /// dma_apbperi_pms_monitor_violate_status_world
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+            /// dma_apbperi_pms_monitor_violate_status_addr
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x600c108c
+        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
+        pub const DMA_APBPERI_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// dma_apbperi_pms_monitor_violate_status_wr
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+            /// dma_apbperi_pms_monitor_violate_status_byteen
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x8c);
+
+        /// address: 0x600c1090
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_dram0_dma_split_line_constrain_lock
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x600c1094
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_dram0_dma_sram_category_0
+            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0: u2,
+            /// core_x_iram0_dram0_dma_sram_category_1
+            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1: u2,
+            /// core_x_iram0_dram0_dma_sram_category_2
+            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_iram0_dram0_dma_sram_splitaddr
+            CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x94);
+
+        /// address: 0x600c1098
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_sram_line_0_category_0
+            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0: u2,
+            /// core_x_iram0_sram_line_0_category_1
+            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1: u2,
+            /// core_x_iram0_sram_line_0_category_2
+            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_iram0_sram_line_0_splitaddr
+            CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x600c109c
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_sram_line_1_category_0
+            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0: u2,
+            /// core_x_iram0_sram_line_1_category_1
+            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1: u2,
+            /// core_x_iram0_sram_line_1_category_2
+            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_iram0_sram_line_1_splitaddr
+            CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x9c);
+
+        /// address: 0x600c10a0
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_dram0_dma_sram_line_0_category_0
+            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0: u2,
+            /// core_x_dram0_dma_sram_line_0_category_1
+            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1: u2,
+            /// core_x_dram0_dma_sram_line_0_category_2
+            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_dram0_dma_sram_line_0_splitaddr
+            CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0xa0);
+
+        /// address: 0x600c10a4
+        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
+        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_dram0_dma_sram_line_1_category_0
+            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0: u2,
+            /// core_x_dram0_dma_sram_line_1_category_1
+            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1: u2,
+            /// core_x_dram0_dma_sram_line_1_category_2
+            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_dram0_dma_sram_line_1_splitaddr
+            CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600c10a8
+        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+        pub const CORE_X_IRAM0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_pms_constrain_lock
+            CORE_X_IRAM0_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600c10ac
+        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
+        pub const CORE_X_IRAM0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_pms_constrain_sram_world_1_pms_0
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u3,
+            /// core_x_iram0_pms_constrain_sram_world_1_pms_1
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u3,
+            /// core_x_iram0_pms_constrain_sram_world_1_pms_2
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u3,
+            /// core_x_iram0_pms_constrain_sram_world_1_pms_3
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u3,
+            /// core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0: u3,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// core_x_iram0_pms_constrain_rom_world_1_pms
+            CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600c10b0
+        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
+        pub const CORE_X_IRAM0_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_iram0_pms_constrain_sram_world_0_pms_0
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u3,
+            /// core_x_iram0_pms_constrain_sram_world_0_pms_1
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u3,
+            /// core_x_iram0_pms_constrain_sram_world_0_pms_2
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u3,
+            /// core_x_iram0_pms_constrain_sram_world_0_pms_3
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u3,
+            /// core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0
+            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0: u3,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// core_x_iram0_pms_constrain_rom_world_0_pms
+            CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0xb0);
+
+        /// address: 0x600c10b4
+        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
+        pub const CORE_0_IRAM0_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_iram0_pms_monitor_lock
+            CORE_0_IRAM0_PMS_MONITOR_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600c10b8
+        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
+        pub const CORE_0_IRAM0_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_iram0_pms_monitor_violate_clr
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
+            /// core_0_iram0_pms_monitor_violate_en
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xb8);
+
+        /// address: 0x600c10bc
+        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
+        pub const CORE_0_IRAM0_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_iram0_pms_monitor_violate_intr
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
+            /// core_0_iram0_pms_monitor_violate_status_wr
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+            /// core_0_iram0_pms_monitor_violate_status_loadstore
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE: u1,
+            /// core_0_iram0_pms_monitor_violate_status_world
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+            /// core_0_iram0_pms_monitor_violate_status_addr
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0xbc);
+
+        /// address: 0x600c10c0
+        /// SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+        pub const CORE_X_DRAM0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_dram0_pms_constrain_lock
+            CORE_X_DRAM0_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600c10c4
+        /// SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
+        pub const CORE_X_DRAM0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_x_dram0_pms_constrain_sram_world_0_pms_0
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+            /// core_x_dram0_pms_constrain_sram_world_0_pms_1
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+            /// core_x_dram0_pms_constrain_sram_world_0_pms_2
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+            /// core_x_dram0_pms_constrain_sram_world_0_pms_3
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_x_dram0_pms_constrain_sram_world_1_pms_0
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+            /// core_x_dram0_pms_constrain_sram_world_1_pms_1
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+            /// core_x_dram0_pms_constrain_sram_world_1_pms_2
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+            /// core_x_dram0_pms_constrain_sram_world_1_pms_3
+            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_x_dram0_pms_constrain_rom_world_0_pms
+            CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u2,
+            /// core_x_dram0_pms_constrain_rom_world_1_pms
+            CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xc4);
+
+        /// address: 0x600c10c8
+        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
+        pub const CORE_0_DRAM0_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_dram0_pms_monitor_lock
+            CORE_0_DRAM0_PMS_MONITOR_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600c10cc
+        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
+        pub const CORE_0_DRAM0_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_dram0_pms_monitor_violate_clr
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
+            /// core_0_dram0_pms_monitor_violate_en
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xcc);
+
+        /// address: 0x600c10d0
+        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
+        pub const CORE_0_DRAM0_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_dram0_pms_monitor_violate_intr
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
+            /// core_0_dram0_pms_monitor_violate_status_lock
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK: u1,
+            /// core_0_dram0_pms_monitor_violate_status_world
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+            /// core_0_dram0_pms_monitor_violate_status_addr
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xd0);
+
+        /// address: 0x600c10d4
+        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
+        pub const CORE_0_DRAM0_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_dram0_pms_monitor_violate_status_wr
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+            /// core_0_dram0_pms_monitor_violate_status_byteen
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xd4);
+
+        /// address: 0x600c10d8
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_lock
+            CORE_0_PIF_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xd8);
+
+        /// address: 0x600c10dc
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_0_uart
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART: u2,
+            /// core_0_pif_pms_constrain_world_0_g0spi_1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1: u2,
+            /// core_0_pif_pms_constrain_world_0_g0spi_0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0: u2,
+            /// core_0_pif_pms_constrain_world_0_gpio
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO: u2,
+            /// core_0_pif_pms_constrain_world_0_fe2
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2: u2,
+            /// core_0_pif_pms_constrain_world_0_fe
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE: u2,
+            /// core_0_pif_pms_constrain_world_0_timer
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER: u2,
+            /// core_0_pif_pms_constrain_world_0_rtc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC: u2,
+            /// core_0_pif_pms_constrain_world_0_io_mux
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX: u2,
+            /// core_0_pif_pms_constrain_world_0_wdg
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_0_misc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC: u2,
+            /// core_0_pif_pms_constrain_world_0_i2c
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C: u2,
+            reserved4: u1,
+            reserved5: u1,
+            /// core_0_pif_pms_constrain_world_0_uart1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1: u2,
+        }), base_address + 0xdc);
+
+        /// address: 0x600c10e0
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_0_bt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_0_i2c_ext0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0: u2,
+            /// core_0_pif_pms_constrain_world_0_uhci0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_0_rmt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT: u2,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_0_pif_pms_constrain_world_0_ledc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// core_0_pif_pms_constrain_world_0_bb
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB: u2,
+            reserved12: u1,
+            reserved13: u1,
+            /// core_0_pif_pms_constrain_world_0_timergroup
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP: u2,
+            /// core_0_pif_pms_constrain_world_0_timergroup1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1: u2,
+            /// core_0_pif_pms_constrain_world_0_systimer
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER: u2,
+        }), base_address + 0xe0);
+
+        /// address: 0x600c10e4
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_0_spi_2
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_0_apb_ctrl
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL: u2,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// core_0_pif_pms_constrain_world_0_can
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN: u2,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_0_pif_pms_constrain_world_0_i2s1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// core_0_pif_pms_constrain_world_0_rwbt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT: u2,
+            reserved14: u1,
+            reserved15: u1,
+            /// core_0_pif_pms_constrain_world_0_wifimac
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC: u2,
+            /// core_0_pif_pms_constrain_world_0_pwr
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR: u2,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0xe4);
+
+        /// address: 0x600c10e8
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_0_usb_wrap
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP: u2,
+            /// core_0_pif_pms_constrain_world_0_crypto_peri
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI: u2,
+            /// core_0_pif_pms_constrain_world_0_crypto_dma
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA: u2,
+            /// core_0_pif_pms_constrain_world_0_apb_adc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_0_bt_pwr
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR: u2,
+            /// core_0_pif_pms_constrain_world_0_usb_device
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE: u2,
+            /// core_0_pif_pms_constrain_world_0_system
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM: u2,
+            /// core_0_pif_pms_constrain_world_0_sensitive
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE: u2,
+            /// core_0_pif_pms_constrain_world_0_interrupt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT: u2,
+            /// core_0_pif_pms_constrain_world_0_dma_copy
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY: u2,
+            /// core_0_pif_pms_constrain_world_0_cache_config
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG: u2,
+            /// core_0_pif_pms_constrain_world_0_ad
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD: u2,
+            /// core_0_pif_pms_constrain_world_0_dio
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO: u2,
+            /// core_0_pif_pms_constrain_world_0_world_controller
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER: u2,
+        }), base_address + 0xe8);
+
+        /// address: 0x600c10ec
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_1_uart
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART: u2,
+            /// core_0_pif_pms_constrain_world_1_g0spi_1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1: u2,
+            /// core_0_pif_pms_constrain_world_1_g0spi_0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0: u2,
+            /// core_0_pif_pms_constrain_world_1_gpio
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO: u2,
+            /// core_0_pif_pms_constrain_world_1_fe2
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2: u2,
+            /// core_0_pif_pms_constrain_world_1_fe
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE: u2,
+            /// core_0_pif_pms_constrain_world_1_timer
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER: u2,
+            /// core_0_pif_pms_constrain_world_1_rtc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC: u2,
+            /// core_0_pif_pms_constrain_world_1_io_mux
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX: u2,
+            /// core_0_pif_pms_constrain_world_1_wdg
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_1_misc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC: u2,
+            /// core_0_pif_pms_constrain_world_1_i2c
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C: u2,
+            reserved4: u1,
+            reserved5: u1,
+            /// core_0_pif_pms_constrain_world_1_uart1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1: u2,
+        }), base_address + 0xec);
+
+        /// address: 0x600c10f0
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_1_bt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_1_i2c_ext0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0: u2,
+            /// core_0_pif_pms_constrain_world_1_uhci0
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_1_rmt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT: u2,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_0_pif_pms_constrain_world_1_ledc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// core_0_pif_pms_constrain_world_1_bb
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB: u2,
+            reserved12: u1,
+            reserved13: u1,
+            /// core_0_pif_pms_constrain_world_1_timergroup
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP: u2,
+            /// core_0_pif_pms_constrain_world_1_timergroup1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1: u2,
+            /// core_0_pif_pms_constrain_world_1_systimer
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER: u2,
+        }), base_address + 0xf0);
+
+        /// address: 0x600c10f4
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_world_1_spi_2
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_1_apb_ctrl
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL: u2,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// core_0_pif_pms_constrain_world_1_can
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN: u2,
+            reserved6: u1,
+            reserved7: u1,
+            /// core_0_pif_pms_constrain_world_1_i2s1
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// core_0_pif_pms_constrain_world_1_rwbt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT: u2,
+            reserved14: u1,
+            reserved15: u1,
+            /// core_0_pif_pms_constrain_world_1_wifimac
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC: u2,
+            /// core_0_pif_pms_constrain_world_1_pwr
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR: u2,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0xf4);
+
+        /// address: 0x600c10f8
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_8 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            /// core_0_pif_pms_constrain_world_1_usb_wrap
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP: u2,
+            /// core_0_pif_pms_constrain_world_1_crypto_peri
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI: u2,
+            /// core_0_pif_pms_constrain_world_1_crypto_dma
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA: u2,
+            /// core_0_pif_pms_constrain_world_1_apb_adc
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// core_0_pif_pms_constrain_world_1_bt_pwr
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR: u2,
+            /// core_0_pif_pms_constrain_world_1_usb_device
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE: u2,
+            /// core_0_pif_pms_constrain_world_1_system
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM: u2,
+            /// core_0_pif_pms_constrain_world_1_sensitive
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE: u2,
+            /// core_0_pif_pms_constrain_world_1_interrupt
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT: u2,
+            /// core_0_pif_pms_constrain_world_1_dma_copy
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY: u2,
+            /// core_0_pif_pms_constrain_world_1_cache_config
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG: u2,
+            /// core_0_pif_pms_constrain_world_1_ad
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD: u2,
+            /// core_0_pif_pms_constrain_world_1_dio
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO: u2,
+            /// core_0_pif_pms_constrain_world_1_world_controller
+            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER: u2,
+        }), base_address + 0xf8);
+
+        /// address: 0x600c10fc
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_rtcfast_spltaddr_world_0
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0: u11,
+            /// core_0_pif_pms_constrain_rtcfast_spltaddr_world_1
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1: u11,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0xfc);
+
+        /// address: 0x600c1100
+        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
+        pub const CORE_0_PIF_PMS_CONSTRAIN_10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_constrain_rtcfast_world_0_l
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L: u3,
+            /// core_0_pif_pms_constrain_rtcfast_world_0_h
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H: u3,
+            /// core_0_pif_pms_constrain_rtcfast_world_1_l
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L: u3,
+            /// core_0_pif_pms_constrain_rtcfast_world_1_h
+            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x100);
+
+        /// address: 0x600c1104
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
+        pub const REGION_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_lock
+            REGION_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x104);
+
+        /// address: 0x600c1108
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
+        pub const REGION_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_world_0_area_0
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_0: u2,
+            /// region_pms_constrain_world_0_area_1
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_1: u2,
+            /// region_pms_constrain_world_0_area_2
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_2: u2,
+            /// region_pms_constrain_world_0_area_3
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_3: u2,
+            /// region_pms_constrain_world_0_area_4
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_4: u2,
+            /// region_pms_constrain_world_0_area_5
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_5: u2,
+            /// region_pms_constrain_world_0_area_6
+            REGION_PMS_CONSTRAIN_WORLD_0_AREA_6: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x108);
+
+        /// address: 0x600c110c
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
+        pub const REGION_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_world_1_area_0
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_0: u2,
+            /// region_pms_constrain_world_1_area_1
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_1: u2,
+            /// region_pms_constrain_world_1_area_2
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_2: u2,
+            /// region_pms_constrain_world_1_area_3
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_3: u2,
+            /// region_pms_constrain_world_1_area_4
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_4: u2,
+            /// region_pms_constrain_world_1_area_5
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_5: u2,
+            /// region_pms_constrain_world_1_area_6
+            REGION_PMS_CONSTRAIN_WORLD_1_AREA_6: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+        }), base_address + 0x10c);
+
+        /// address: 0x600c1110
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
+        pub const REGION_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_0
+            REGION_PMS_CONSTRAIN_ADDR_0: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x110);
+
+        /// address: 0x600c1114
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
+        pub const REGION_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_1
+            REGION_PMS_CONSTRAIN_ADDR_1: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x114);
+
+        /// address: 0x600c1118
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
+        pub const REGION_PMS_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_2
+            REGION_PMS_CONSTRAIN_ADDR_2: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x118);
+
+        /// address: 0x600c111c
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
+        pub const REGION_PMS_CONSTRAIN_6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_3
+            REGION_PMS_CONSTRAIN_ADDR_3: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x11c);
+
+        /// address: 0x600c1120
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
+        pub const REGION_PMS_CONSTRAIN_7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_4
+            REGION_PMS_CONSTRAIN_ADDR_4: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x120);
+
+        /// address: 0x600c1124
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
+        pub const REGION_PMS_CONSTRAIN_8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_5
+            REGION_PMS_CONSTRAIN_ADDR_5: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x124);
+
+        /// address: 0x600c1128
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
+        pub const REGION_PMS_CONSTRAIN_9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_6
+            REGION_PMS_CONSTRAIN_ADDR_6: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x128);
+
+        /// address: 0x600c112c
+        /// SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
+        pub const REGION_PMS_CONSTRAIN_10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// region_pms_constrain_addr_7
+            REGION_PMS_CONSTRAIN_ADDR_7: u30,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x12c);
+
+        /// address: 0x600c1130
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
+        pub const CORE_0_PIF_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_lock
+            CORE_0_PIF_PMS_MONITOR_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x130);
+
+        /// address: 0x600c1134
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
+        pub const CORE_0_PIF_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_violate_clr
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR: u1,
+            /// core_0_pif_pms_monitor_violate_en
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x134);
+
+        /// address: 0x600c1138
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
+        pub const CORE_0_PIF_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_violate_intr
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR: u1,
+            /// core_0_pif_pms_monitor_violate_status_hport_0
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0: u1,
+            /// core_0_pif_pms_monitor_violate_status_hsize
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
+            /// core_0_pif_pms_monitor_violate_status_hwrite
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
+            /// core_0_pif_pms_monitor_violate_status_hworld
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x138);
+
+        /// address: 0x600c113c
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
+        pub const CORE_0_PIF_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_violate_status_haddr
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR: u32,
+        }), base_address + 0x13c);
+
+        /// address: 0x600c1140
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
+        pub const CORE_0_PIF_PMS_MONITOR_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_nonword_violate_clr
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR: u1,
+            /// core_0_pif_pms_monitor_nonword_violate_en
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x140);
+
+        /// address: 0x600c1144
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
+        pub const CORE_0_PIF_PMS_MONITOR_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_nonword_violate_intr
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR: u1,
+            /// core_0_pif_pms_monitor_nonword_violate_status_hsize
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE: u2,
+            /// core_0_pif_pms_monitor_nonword_violate_status_hworld
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x144);
+
+        /// address: 0x600c1148
+        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
+        pub const CORE_0_PIF_PMS_MONITOR_6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// core_0_pif_pms_monitor_nonword_violate_status_haddr
+            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR: u32,
+        }), base_address + 0x148);
+
+        /// address: 0x600c114c
+        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
+        pub const BACKUP_BUS_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_constrain_lock
+            BACKUP_BUS_PMS_CONSTRAIN_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x14c);
+
+        /// address: 0x600c1150
+        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
+        pub const BACKUP_BUS_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_constrain_uart
+            BACKUP_BUS_PMS_CONSTRAIN_UART: u2,
+            /// backup_bus_pms_constrain_g0spi_1
+            BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1: u2,
+            /// backup_bus_pms_constrain_g0spi_0
+            BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0: u2,
+            /// backup_bus_pms_constrain_gpio
+            BACKUP_BUS_PMS_CONSTRAIN_GPIO: u2,
+            /// backup_bus_pms_constrain_fe2
+            BACKUP_BUS_PMS_CONSTRAIN_FE2: u2,
+            /// backup_bus_pms_constrain_fe
+            BACKUP_BUS_PMS_CONSTRAIN_FE: u2,
+            /// backup_bus_pms_constrain_timer
+            BACKUP_BUS_PMS_CONSTRAIN_TIMER: u2,
+            /// backup_bus_pms_constrain_rtc
+            BACKUP_BUS_PMS_CONSTRAIN_RTC: u2,
+            /// backup_bus_pms_constrain_io_mux
+            BACKUP_BUS_PMS_CONSTRAIN_IO_MUX: u2,
+            /// backup_bus_pms_constrain_wdg
+            BACKUP_BUS_PMS_CONSTRAIN_WDG: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// backup_bus_pms_constrain_misc
+            BACKUP_BUS_PMS_CONSTRAIN_MISC: u2,
+            /// backup_bus_pms_constrain_i2c
+            BACKUP_BUS_PMS_CONSTRAIN_I2C: u2,
+            reserved4: u1,
+            reserved5: u1,
+            /// backup_bus_pms_constrain_uart1
+            BACKUP_BUS_PMS_CONSTRAIN_UART1: u2,
+        }), base_address + 0x150);
+
+        /// address: 0x600c1154
+        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
+        pub const BACKUP_BUS_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_constrain_bt
+            BACKUP_BUS_PMS_CONSTRAIN_BT: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// backup_bus_pms_constrain_i2c_ext0
+            BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0: u2,
+            /// backup_bus_pms_constrain_uhci0
+            BACKUP_BUS_PMS_CONSTRAIN_UHCI0: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// backup_bus_pms_constrain_rmt
+            BACKUP_BUS_PMS_CONSTRAIN_RMT: u2,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// backup_bus_pms_constrain_ledc
+            BACKUP_BUS_PMS_CONSTRAIN_LEDC: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// backup_bus_pms_constrain_bb
+            BACKUP_BUS_PMS_CONSTRAIN_BB: u2,
+            reserved12: u1,
+            reserved13: u1,
+            /// backup_bus_pms_constrain_timergroup
+            BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP: u2,
+            /// backup_bus_pms_constrain_timergroup1
+            BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1: u2,
+            /// backup_bus_pms_constrain_systimer
+            BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER: u2,
+        }), base_address + 0x154);
+
+        /// address: 0x600c1158
+        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
+        pub const BACKUP_BUS_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_constrain_spi_2
+            BACKUP_BUS_PMS_CONSTRAIN_SPI_2: u2,
+            reserved0: u1,
+            reserved1: u1,
+            /// backup_bus_pms_constrain_apb_ctrl
+            BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL: u2,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// backup_bus_pms_constrain_can
+            BACKUP_BUS_PMS_CONSTRAIN_CAN: u2,
+            reserved6: u1,
+            reserved7: u1,
+            /// backup_bus_pms_constrain_i2s1
+            BACKUP_BUS_PMS_CONSTRAIN_I2S1: u2,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// backup_bus_pms_constrain_rwbt
+            BACKUP_BUS_PMS_CONSTRAIN_RWBT: u2,
+            reserved14: u1,
+            reserved15: u1,
+            /// backup_bus_pms_constrain_wifimac
+            BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC: u2,
+            /// backup_bus_pms_constrain_pwr
+            BACKUP_BUS_PMS_CONSTRAIN_PWR: u2,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x158);
+
+        /// address: 0x600c115c
+        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
+        pub const BACKUP_BUS_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            /// backup_bus_pms_constrain_usb_wrap
+            BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP: u2,
+            /// backup_bus_pms_constrain_crypto_peri
+            BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI: u2,
+            /// backup_bus_pms_constrain_crypto_dma
+            BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA: u2,
+            /// backup_bus_pms_constrain_apb_adc
+            BACKUP_BUS_PMS_CONSTRAIN_APB_ADC: u2,
+            reserved2: u1,
+            reserved3: u1,
+            /// backup_bus_pms_constrain_bt_pwr
+            BACKUP_BUS_PMS_CONSTRAIN_BT_PWR: u2,
+            /// backup_bus_pms_constrain_usb_device
+            BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x15c);
+
+        /// address: 0x600c1160
+        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
+        pub const BACKUP_BUS_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_monitor_lock
+            BACKUP_BUS_PMS_MONITOR_LOCK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x160);
+
+        /// address: 0x600c1164
+        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
+        pub const BACKUP_BUS_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_monitor_violate_clr
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR: u1,
+            /// backup_bus_pms_monitor_violate_en
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x164);
+
+        /// address: 0x600c1168
+        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
+        pub const BACKUP_BUS_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_monitor_violate_intr
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR: u1,
+            /// backup_bus_pms_monitor_violate_status_htrans
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS: u2,
+            /// backup_bus_pms_monitor_violate_status_hsize
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
+            /// backup_bus_pms_monitor_violate_status_hwrite
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x168);
+
+        /// address: 0x600c116c
+        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
+        pub const BACKUP_BUS_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// backup_bus_pms_monitor_violate_haddr
+            BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR: u32,
+        }), base_address + 0x16c);
+
+        /// address: 0x600c1170
+        /// SENSITIVE_CLOCK_GATE_REG
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// clk_en
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x170);
+
+        /// address: 0x600c1ffc
+        /// SENSITIVE_DATE_REG
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xffc);
+    };
+
+    /// SHA (Secure Hash Algorithm) Accelerator
+    pub const SHA = struct {
+        pub const base_address = 0x6003b000;
+
+        /// address: 0x6003b000
+        /// Initial configuration register.
+        pub const MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x0);
+
+        /// address: 0x6003b004
+        /// SHA 512/t configuration register 0.
+        pub const T_STRING = @intToPtr(*volatile u32, base_address + 0x4);
+
+        /// address: 0x6003b008
+        /// SHA 512/t configuration register 1.
+        pub const T_LENGTH = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x8);
+
+        /// address: 0x6003b00c
+        /// DMA configuration register 0.
+        pub const DMA_BLOCK_NUM = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xc);
+
+        /// address: 0x6003b010
+        /// Typical SHA configuration register 0.
+        pub const START = @intToPtr(*volatile MmioInt(32, u31), base_address + 0x10);
+
+        /// address: 0x6003b014
+        /// Typical SHA configuration register 1.
+        pub const CONTINUE = @intToPtr(*volatile MmioInt(32, u31), base_address + 0x14);
+
+        /// address: 0x6003b018
+        /// Busy register.
+        pub const BUSY = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Sha busy state. 1'b0: idle. 1'b1: busy.
+            STATE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6003b01c
+        /// DMA configuration register 1.
+        pub const DMA_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x1c);
+
+        /// address: 0x6003b020
+        /// DMA configuration register 2.
+        pub const DMA_CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x20);
+
+        /// address: 0x6003b024
+        /// Interrupt clear register.
+        pub const CLEAR_IRQ = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Clear sha interrupt.
+            CLEAR_INTERRUPT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x6003b028
+        /// Interrupt enable register.
+        pub const IRQ_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
+            INTERRUPT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6003b02c
+        /// Date register.
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x2c);
+
+        /// address: 0x6003b040
+        /// Sha H memory which contains intermediate hash or finial hash.
+        pub const H_MEM = @intToPtr(*volatile [64]u8, base_address + 0x40);
+
+        /// address: 0x6003b080
+        /// Sha M memory which contains message.
+        pub const M_MEM = @intToPtr(*volatile [64]u8, base_address + 0x80);
+    };
+
+    /// SPI (Serial Peripheral Interface) Controller
+    pub const SPI0 = struct {
+        pub const base_address = 0x60003000;
+
+        /// address: 0x60003008
+        /// SPI0 control register.
+        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// In the dummy phase the signal level of spi is output by the spi controller.
+            FDUMMY_OUT: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// Apply 2 signals during command phase 1:enable 0: disable
+            FCMD_DUAL: u1,
+            /// Apply 4 signals during command phase 1:enable 0: disable
+            FCMD_QUAD: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio,
+            /// spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+            FASTRD_MODE: u1,
+            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+            FREAD_DUAL: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            /// The bit is used to set MISO line polarity, 1: high 0, low
+            Q_POL: u1,
+            /// The bit is used to set MOSI line polarity, 1: high 0, low
+            D_POL: u1,
+            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+            FREAD_QUAD: u1,
+            /// Write protect signal output when SPI is idle. 1: output high, 0: output low.
+            WP: u1,
+            reserved13: u1,
+            /// In the read operations address phase and read-data phase apply 2 signals. 1:
+            /// enable 0: disable.
+            FREAD_DIO: u1,
+            /// In the read operations address phase and read-data phase apply 4 signals. 1:
+            /// enable 0: disable.
+            FREAD_QIO: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000300c
+        /// SPI0 control1 register.
+        pub const CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
+            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
+            /// inactive 3: SPI clock is alwasy on.
+            CLK_MODE: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            /// SPI0 RX FIFO reset signal.
+            RXFIFO_RST: u1,
+            padding0: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60003010
+        /// SPI0 control2 register.
+        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// (cycles-1) of prepare phase by spi clock this bits are combined with
+            /// spi_mem_cs_setup bit.
+            CS_SETUP_TIME: u5,
+            /// Spi cs signal is delayed to inactive by spi clock this bits are combined with
+            /// spi_mem_cs_hold bit.
+            CS_HOLD_TIME: u5,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// These bits are used to set the minimum CS high time tSHSL between SPI burst
+            /// transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI
+            /// core clock cycles.
+            CS_HOLD_DELAY: u6,
+            /// The FSM will be reset.
+            SYNC_RESET: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60003014
+        /// SPI clock division control register.
+        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In the master mode it must be equal to spi_mem_clkcnt_N.
+            CLKCNT_L: u8,
+            /// In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+            CLKCNT_H: u8,
+            /// In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+            /// system/(spi_mem_clkcnt_N+1)
+            CLKCNT_N: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            /// Set this bit in 1-division mode.
+            CLK_EQU_SYSCLK: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60003018
+        /// SPI0 user register.
+        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// spi cs keep low when spi is in done phase. 1: enable 0: disable.
+            CS_HOLD: u1,
+            /// spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
+            CS_SETUP: u1,
+            reserved6: u1,
+            /// the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay
+            /// mode.
+            CK_OUT_EDGE: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            /// spi clock is disable in dummy phase when the bit is enable.
+            USR_DUMMY_IDLE: u1,
+            reserved23: u1,
+            reserved24: u1,
+            /// This bit enable the dummy phase of an operation.
+            USR_DUMMY: u1,
+            padding0: u1,
+            padding1: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000301c
+        /// SPI0 user1 register.
+        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The length in spi_mem_clk cycles of dummy phase. The register value shall be
+            /// (cycle_num-1).
+            USR_DUMMY_CYCLELEN: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            /// The length in bits of address phase. The register value shall be (bit_num-1).
+            USR_ADDR_BITLEN: u6,
+        }), base_address + 0x1c);
+
+        /// address: 0x60003020
+        /// SPI0 user2 register.
+        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of command.
+            USR_COMMAND_VALUE: u16,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// The length in bits of command phase. The register value shall be (bit_num-1)
+            USR_COMMAND_BITLEN: u4,
+        }), base_address + 0x20);
+
+        /// address: 0x6000302c
+        /// SPI0 read control register.
+        pub const RD_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            /// Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode
+            /// bit.
+            WB_MODE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60003034
+        /// SPI0 misc register
+        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The bit is used to indicate the spi0_mst_st controlled transmitting is done.
+            TRANS_END: u1,
+            /// The bit is used to enable the interrupt of spi0_mst_st controlled transmitting
+            /// is done.
+            TRANS_END_INT_ENA: u1,
+            /// The bit is used to indicate the spi0_slv_st controlled transmitting is done.
+            CSPI_ST_TRANS_END: u1,
+            /// The bit is used to enable the interrupt of spi0_slv_st controlled transmitting
+            /// is done.
+            CSPI_ST_TRANS_END_INT_ENA: u1,
+            reserved3: u1,
+            reserved4: u1,
+            /// 1: spi clk line is high when idle 0: spi clk line is low when idle
+            CK_IDLE_EDGE: u1,
+            /// spi cs line keep low when the bit is set.
+            CS_KEEP_ACTIVE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x6000303c
+        /// SPI0 bit mode control register.
+        pub const CACHE_FCTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// For SPI0, Cache access enable, 1: enable, 0:disable.
+            CACHE_REQ_EN: u1,
+            /// For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
+            CACHE_USR_ADDR_4BYTE: u1,
+            /// For SPI0, cache read flash for user define command, 1: enable, 0:disable.
+            CACHE_FLASH_USR_CMD: u1,
+            /// For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_dio.
+            FDIN_DUAL: u1,
+            /// For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_dio.
+            FDOUT_DUAL: u1,
+            /// For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is
+            /// the same with spi_mem_fread_dio.
+            FADDR_DUAL: u1,
+            /// For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_qio.
+            FDIN_QUAD: u1,
+            /// For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_qio.
+            FDOUT_QUAD: u1,
+            /// For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is
+            /// the same with spi_mem_fread_qio.
+            FADDR_QUAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60003054
+        /// SPI0 FSM status register
+        pub const FSM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation
+            /// state, 2: send command state, 3: send address state, 4: wait state, 5: read data
+            /// state, 6:write data state, 7: done state, 8: read data end state.
+            CSPI_ST: u4,
+            /// The current status of SPI0 master FSM: spi0_mst_st. 0: idle state,
+            /// 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4:
+            /// wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
+            EM_ST: u3,
+            /// The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
+            CSPI_LOCK_DELAY_TIME: u5,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x600030a8
+        /// SPI0 timing calibration register
+        pub const TIMING_CALI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The bit is used to enable timing adjust clock for all reading operations.
+            TIMING_CLK_ENA: u1,
+            /// The bit is used to enable timing auto-calibration for all reading operations.
+            TIMING_CALI: u1,
+            /// add extra dummy spi clock cycle length for spi clock calibration.
+            EXTRA_DUMMY_CYCLELEN: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600030ac
+        /// SPI0 input delay mode control register
+        pub const DIN_MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the input signals are delayed by system clock cycles, 0: input without delayed,
+            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
+            /// with the spi_clk high edge, 6: input with the spi_clk low edge
+            DIN0_MODE: u2,
+            /// the input signals are delayed by system clock cycles, 0: input without delayed,
+            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
+            /// with the spi_clk high edge, 6: input with the spi_clk low edge
+            DIN1_MODE: u2,
+            /// the input signals are delayed by system clock cycles, 0: input without delayed,
+            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
+            /// with the spi_clk high edge, 6: input with the spi_clk low edge
+            DIN2_MODE: u2,
+            /// the input signals are delayed by system clock cycles, 0: input without delayed,
+            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
+            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
+            /// with the spi_clk high edge, 6: input with the spi_clk low edge
+            DIN3_MODE: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0xac);
+
+        /// address: 0x600030b0
+        /// SPI0 input delay number control register
+        pub const DIN_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+            /// delayed by 2 cycles,...
+            DIN0_NUM: u2,
+            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+            /// delayed by 2 cycles,...
+            DIN1_NUM: u2,
+            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+            /// delayed by 2 cycles,...
+            DIN2_NUM: u2,
+            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
+            /// delayed by 2 cycles,...
+            DIN3_NUM: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0xb0);
+
+        /// address: 0x600030b4
+        /// SPI0 output delay mode control register
+        pub const DOUT_MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the output signals are delayed by system clock cycles, 0: output without
+            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
+            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
+            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
+            /// edge
+            DOUT0_MODE: u1,
+            /// the output signals are delayed by system clock cycles, 0: output without
+            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
+            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
+            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
+            /// edge
+            DOUT1_MODE: u1,
+            /// the output signals are delayed by system clock cycles, 0: output without
+            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
+            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
+            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
+            /// edge
+            DOUT2_MODE: u1,
+            /// the output signals are delayed by system clock cycles, 0: output without
+            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
+            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
+            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
+            /// edge
+            DOUT3_MODE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0xb4);
+
+        /// address: 0x600030dc
+        /// SPI0 clk_gate register
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Register clock gate enable signal. 1: Enable. 0: Disable.
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xdc);
+
+        /// address: 0x600030e0
+        /// SPI0 module clock select register
+        pub const CORE_CLK_SEL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// When the digital system clock selects PLL clock and the frequency of PLL clock
+            /// is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is
+            /// 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk)
+            /// 160MHz. 3: Not used. When the digital system clock selects PLL clock and the
+            /// frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1
+            /// module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1
+            /// module clock (clk) 160MHz. 3: Not used.
+            SPI01_CLK_SEL: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0xe0);
+
+        /// address: 0x600033fc
+        /// Version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x3fc);
+    };
+
+    /// SPI (Serial Peripheral Interface) Controller
+    pub const SPI1 = struct {
+        pub const base_address = 0x60002000;
+
+        /// address: 0x60002000
+        /// SPI1 memory command register
+        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The current status of SPI1 master FSM.
+            SPI1_MST_ST: u4,
+            /// The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation
+            /// state, 2: send command state, 3: send address state, 4: wait state, 5: read data
+            /// state, 6:write data state, 7: done state, 8: read data end state.
+            MSPI_ST: u4,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// In user mode, it is set to indicate that program/erase operation will be
+            /// triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared
+            /// once the operation done.1: enable 0: disable.
+            FLASH_PE: u1,
+            /// User define command enable. An operation will be triggered when the bit is set.
+            /// The bit will be cleared once the operation done.1: enable 0: disable.
+            USR: u1,
+            /// Drive Flash into high performance mode. The bit will be cleared once the
+            /// operation done.1: enable 0: disable.
+            FLASH_HPM: u1,
+            /// This bit combined with reg_resandres bit releases Flash from the power-down
+            /// state or high performance mode and obtains the devices ID. The bit will be
+            /// cleared once the operation done.1: enable 0: disable.
+            FLASH_RES: u1,
+            /// Drive Flash into power down. An operation will be triggered when the bit is set.
+            /// The bit will be cleared once the operation done.1: enable 0: disable.
+            FLASH_DP: u1,
+            /// Chip erase enable. Chip erase operation will be triggered when the bit is set.
+            /// The bit will be cleared once the operation done.1: enable 0: disable.
+            FLASH_CE: u1,
+            /// Block erase enable(32KB) . Block erase operation will be triggered when the bit
+            /// is set. The bit will be cleared once the operation done.1: enable 0: disable.
+            FLASH_BE: u1,
+            /// Sector erase enable(4KB). Sector erase operation will be triggered when the bit
+            /// is set. The bit will be cleared once the operation done.1: enable 0: disable.
+            FLASH_SE: u1,
+            /// Page program enable(1 byte ~256 bytes data to be programmed). Page program
+            /// operation will be triggered when the bit is set. The bit will be cleared once
+            /// the operation done .1: enable 0: disable.
+            FLASH_PP: u1,
+            /// Write status register enable. Write status operation will be triggered when the
+            /// bit is set. The bit will be cleared once the operation done.1: enable 0:
+            /// disable.
+            FLASH_WRSR: u1,
+            /// Read status register-1. Read status operation will be triggered when the bit is
+            /// set. The bit will be cleared once the operation done.1: enable 0: disable.
+            FLASH_RDSR: u1,
+            /// Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will
+            /// be cleared once the operation done. 1: enable 0: disable.
+            FLASH_RDID: u1,
+            /// Write flash disable. Write disable command will be sent when the bit is set. The
+            /// bit will be cleared once the operation done. 1: enable 0: disable.
+            FLASH_WRDI: u1,
+            /// Write flash enable. Write enable command will be sent when the bit is set. The
+            /// bit will be cleared once the operation done. 1: enable 0: disable.
+            FLASH_WREN: u1,
+            /// Read flash enable. Read flash operation will be triggered when the bit is set.
+            /// The bit will be cleared once the operation done. 1: enable 0: disable.
+            FLASH_READ: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60002004
+        /// SPI1 address register
+        pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In user mode, it is the memory address. other then the bit0-bit23 is the memory
+            /// address, the bit24-bit31 are the byte length of a transfer.
+            USR_ADDR_VALUE: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60002008
+        /// SPI1 control register.
+        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// In the dummy phase the signal level of spi is output by the spi controller.
+            FDUMMY_OUT: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// Apply 2 signals during command phase 1:enable 0: disable
+            FCMD_DUAL: u1,
+            /// Apply 4 signals during command phase 1:enable 0: disable
+            FCMD_QUAD: u1,
+            reserved6: u1,
+            /// For SPI1, initialize crc32 module before writing encrypted data to flash. Active
+            /// low.
+            FCS_CRC_EN: u1,
+            /// For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+            TX_CRC_EN: u1,
+            reserved7: u1,
+            /// This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio,
+            /// spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+            FASTRD_MODE: u1,
+            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+            FREAD_DUAL: u1,
+            /// The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with
+            /// spi_mem_flash_res bit. 1: enable 0: disable.
+            RESANDRES: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// The bit is used to set MISO line polarity, 1: high 0, low
+            Q_POL: u1,
+            /// The bit is used to set MOSI line polarity, 1: high 0, low
+            D_POL: u1,
+            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+            FREAD_QUAD: u1,
+            /// Write protect signal output when SPI is idle. 1: output high, 0: output low.
+            WP: u1,
+            /// two bytes data will be written to status register when it is set. 1: enable 0:
+            /// disable.
+            WRSR_2B: u1,
+            /// In the read operations address phase and read-data phase apply 2 signals. 1:
+            /// enable 0: disable.
+            FREAD_DIO: u1,
+            /// In the read operations address phase and read-data phase apply 4 signals. 1:
+            /// enable 0: disable.
+            FREAD_QIO: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000200c
+        /// SPI1 control1 register.
+        pub const CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
+            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
+            /// inactive 3: SPI clock is alwasy on.
+            CLK_MODE: u2,
+            /// After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] *
+            /// 512) SPI_CLK cycles.
+            CS_HOLD_DLY_RES: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60002010
+        /// SPI1 control2 register.
+        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// The FSM will be reset.
+            SYNC_RESET: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60002014
+        /// SPI1 clock division control register.
+        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In the master mode it must be equal to spi_mem_clkcnt_N.
+            CLKCNT_L: u8,
+            /// In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+            CLKCNT_H: u8,
+            /// In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
+            /// system/(spi_mem_clkcnt_N+1)
+            CLKCNT_N: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            /// reserved
+            CLK_EQU_SYSCLK: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60002018
+        /// SPI1 user register.
+        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay
+            /// mode.
+            CK_OUT_EDGE: u1,
+            reserved9: u1,
+            reserved10: u1,
+            /// In the write operations read-data phase apply 2 signals
+            FWRITE_DUAL: u1,
+            /// In the write operations read-data phase apply 4 signals
+            FWRITE_QUAD: u1,
+            /// In the write operations address phase and read-data phase apply 2 signals.
+            FWRITE_DIO: u1,
+            /// In the write operations address phase and read-data phase apply 4 signals.
+            FWRITE_QIO: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            /// read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+            /// 1: enable 0: disable.
+            USR_MISO_HIGHPART: u1,
+            /// write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
+            /// 1: enable 0: disable.
+            USR_MOSI_HIGHPART: u1,
+            /// SPI clock is disable in dummy phase when the bit is enable.
+            USR_DUMMY_IDLE: u1,
+            /// This bit enable the write-data phase of an operation.
+            USR_MOSI: u1,
+            /// This bit enable the read-data phase of an operation.
+            USR_MISO: u1,
+            /// This bit enable the dummy phase of an operation.
+            USR_DUMMY: u1,
+            /// This bit enable the address phase of an operation.
+            USR_ADDR: u1,
+            /// This bit enable the command phase of an operation.
+            USR_COMMAND: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000201c
+        /// SPI1 user1 register.
+        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The length in spi_mem_clk cycles of dummy phase. The register value shall be
+            /// (cycle_num-1).
+            USR_DUMMY_CYCLELEN: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            /// The length in bits of address phase. The register value shall be (bit_num-1).
+            USR_ADDR_BITLEN: u6,
+        }), base_address + 0x1c);
+
+        /// address: 0x60002020
+        /// SPI1 user2 register.
+        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of command.
+            USR_COMMAND_VALUE: u16,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// The length in bits of command phase. The register value shall be (bit_num-1)
+            USR_COMMAND_BITLEN: u4,
+        }), base_address + 0x20);
+
+        /// address: 0x60002024
+        /// SPI1 send data bit length control register.
+        pub const MOSI_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The length in bits of write-data. The register value shall be (bit_num-1).
+            USR_MOSI_DBITLEN: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60002028
+        /// SPI1 receive data bit length control register.
+        pub const MISO_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The length in bits of read-data. The register value shall be (bit_num-1).
+            USR_MISO_DBITLEN: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6000202c
+        /// SPI1 status register.
+        pub const RD_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+            STATUS: u16,
+            /// Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode
+            /// bit.
+            WB_MODE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60002034
+        /// SPI1 misc register
+        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
+            /// device, such as flash, external RAM and so on.
+            CS0_DIS: u1,
+            /// SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
+            /// device, such as flash, external RAM and so on.
+            CS1_DIS: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            /// 1: spi clk line is high when idle 0: spi clk line is low when idle
+            CK_IDLE_EDGE: u1,
+            /// spi cs line keep low when the bit is set.
+            CS_KEEP_ACTIVE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60002038
+        /// SPI1 TX CRC data register.
+        pub const TX_CRC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// For SPI1, the value of crc32.
+            DATA: u32,
+        }), base_address + 0x38);
+
+        /// address: 0x6000203c
+        /// SPI1 bit mode control register.
+        pub const CACHE_FCTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
+            CACHE_USR_ADDR_4BYTE: u1,
+            reserved1: u1,
+            /// For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same
+            /// with spi_mem_fread_dio.
+            FDIN_DUAL: u1,
+            /// For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
+            /// with spi_mem_fread_dio.
+            FDOUT_DUAL: u1,
+            /// For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_dio.
+            FADDR_DUAL: u1,
+            /// For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same
+            /// with spi_mem_fread_qio.
+            FDIN_QUAD: u1,
+            /// For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same
+            /// with spi_mem_fread_qio.
+            FDOUT_QUAD: u1,
+            /// For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the
+            /// same with spi_mem_fread_qio.
+            FADDR_QUAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60002058
+        /// SPI1 memory data buffer0
+        pub const W0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF0: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6000205c
+        /// SPI1 memory data buffer1
+        pub const W1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF1: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x60002060
+        /// SPI1 memory data buffer2
+        pub const W2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF2: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x60002064
+        /// SPI1 memory data buffer3
+        pub const W3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF3: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x60002068
+        /// SPI1 memory data buffer4
+        pub const W4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF4: u32,
+        }), base_address + 0x68);
+
+        /// address: 0x6000206c
+        /// SPI1 memory data buffer5
+        pub const W5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF5: u32,
+        }), base_address + 0x6c);
+
+        /// address: 0x60002070
+        /// SPI1 memory data buffer6
+        pub const W6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF6: u32,
+        }), base_address + 0x70);
+
+        /// address: 0x60002074
+        /// SPI1 memory data buffer7
+        pub const W7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF7: u32,
+        }), base_address + 0x74);
+
+        /// address: 0x60002078
+        /// SPI1 memory data buffer8
+        pub const W8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF8: u32,
+        }), base_address + 0x78);
+
+        /// address: 0x6000207c
+        /// SPI1 memory data buffer9
+        pub const W9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF9: u32,
+        }), base_address + 0x7c);
+
+        /// address: 0x60002080
+        /// SPI1 memory data buffer10
+        pub const W10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF10: u32,
+        }), base_address + 0x80);
+
+        /// address: 0x60002084
+        /// SPI1 memory data buffer11
+        pub const W11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF11: u32,
+        }), base_address + 0x84);
+
+        /// address: 0x60002088
+        /// SPI1 memory data buffer12
+        pub const W12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF12: u32,
+        }), base_address + 0x88);
+
+        /// address: 0x6000208c
+        /// SPI1 memory data buffer13
+        pub const W13 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF13: u32,
+        }), base_address + 0x8c);
+
+        /// address: 0x60002090
+        /// SPI1 memory data buffer14
+        pub const W14 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF14: u32,
+        }), base_address + 0x90);
+
+        /// address: 0x60002094
+        /// SPI1 memory data buffer15
+        pub const W15 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF15: u32,
+        }), base_address + 0x94);
+
+        /// address: 0x60002098
+        /// SPI1 wait idle control register
+        pub const FLASH_WAITI_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// The dummy phase enable when wait flash idle (RDSR)
+            WAITI_DUMMY: u1,
+            /// The command to wait flash idle(RDSR).
+            WAITI_CMD: u8,
+            /// The dummy cycle length when wait flash idle(RDSR).
+            WAITI_DUMMY_CYCLELEN: u6,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x6000209c
+        /// SPI1 flash suspend control register
+        pub const FLASH_SUS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// program erase resume bit, program erase suspend operation will be triggered when
+            /// the bit is set. The bit will be cleared once the operation done.1: enable 0:
+            /// disable.
+            FLASH_PER: u1,
+            /// program erase suspend bit, program erase suspend operation will be triggered
+            /// when the bit is set. The bit will be cleared once the operation done.1: enable
+            /// 0: disable.
+            FLASH_PES: u1,
+            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+            /// program erase resume command is sent. 0: SPI1 does not wait after program erase
+            /// resume command is sent.
+            FLASH_PER_WAIT_EN: u1,
+            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
+            /// program erase suspend command is sent. 0: SPI1 does not wait after program erase
+            /// suspend command is sent.
+            FLASH_PES_WAIT_EN: u1,
+            /// Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
+            /// application should send PER after PES is done.
+            PES_PER_EN: u1,
+            /// Set this bit to enable Auto-suspending function.
+            FLASH_PES_EN: u1,
+            /// The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
+            /// status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
+            /// out, status_in[15:0] is valid when two bytes of data are read out),
+            /// SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+            PESR_END_MSK: u16,
+            /// 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte
+            /// when check flash SUS/SUS1/SUS2 status bit
+            RD_SUS_2B: u1,
+            /// 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
+            /// of flash. 0: Only need to check WIP is 0.
+            PER_END_EN: u1,
+            /// 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend
+            /// status of flash. 0: Only need to check WIP is 0.
+            PES_END_EN: u1,
+            /// When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
+            /// it will be treated as check pass.
+            SUS_TIMEOUT_CNT: u7,
+        }), base_address + 0x9c);
+
+        /// address: 0x600020a0
+        /// SPI1 flash suspend command register
+        pub const FLASH_SUS_CMD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Program/Erase resume command.
+            FLASH_PER_COMMAND: u8,
+            /// Program/Erase suspend command.
+            FLASH_PES_COMMAND: u8,
+            /// Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
+            /// SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of
+            /// flash.
+            WAIT_PESR_COMMAND: u16,
+        }), base_address + 0xa0);
+
+        /// address: 0x600020a4
+        /// SPI1 flash suspend status register
+        pub const SUS_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The status of flash suspend, only used in SPI1.
+            FLASH_SUS: u1,
+            /// 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
+            /// SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+            WAIT_PESR_CMD_2B: u1,
+            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
+            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
+            /// cycles after HPM command is sent.
+            FLASH_HPM_DLY_128: u1,
+            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
+            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
+            /// cycles after RES command is sent.
+            FLASH_RES_DLY_128: u1,
+            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
+            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
+            /// cycles after DP command is sent.
+            FLASH_DP_DLY_128: u1,
+            /// Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
+            /// (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent.
+            /// 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER
+            /// command is sent.
+            FLASH_PER_DLY_128: u1,
+            /// Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
+            /// (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent.
+            /// 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES
+            /// command is sent.
+            FLASH_PES_DLY_128: u1,
+            /// 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
+            SPI0_LOCK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0xa4);
+
+        /// address: 0x600020a8
+        /// SPI1 timing control register
+        pub const TIMING_CALI = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// The bit is used to enable timing auto-calibration for all reading operations.
+            TIMING_CALI: u1,
+            /// add extra dummy spi clock cycle length for spi clock calibration.
+            EXTRA_DUMMY_CYCLELEN: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xa8);
+
+        /// address: 0x600020c0
+        /// SPI1 interrupt enable register
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The enable bit for SPI_MEM_PER_END_INT interrupt.
+            PER_END_INT_ENA: u1,
+            /// The enable bit for SPI_MEM_PES_END_INT interrupt.
+            PES_END_INT_ENA: u1,
+            /// The enable bit for SPI_MEM_WPE_END_INT interrupt.
+            WPE_END_INT_ENA: u1,
+            /// The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+            SLV_ST_END_INT_ENA: u1,
+            /// The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+            MST_ST_END_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xc0);
+
+        /// address: 0x600020c4
+        /// SPI1 interrupt clear register
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The clear bit for SPI_MEM_PER_END_INT interrupt.
+            PER_END_INT_CLR: u1,
+            /// The clear bit for SPI_MEM_PES_END_INT interrupt.
+            PES_END_INT_CLR: u1,
+            /// The clear bit for SPI_MEM_WPE_END_INT interrupt.
+            WPE_END_INT_CLR: u1,
+            /// The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+            SLV_ST_END_INT_CLR: u1,
+            /// The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+            MST_ST_END_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xc4);
+
+        /// address: 0x600020c8
+        /// SPI1 interrupt raw register
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
+            /// command (0x7A) is sent and flash is resumed. 0: Others.
+            PER_END_INT_RAW: u1,
+            /// The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
+            /// command (0x75) is sent and flash is suspended. 0: Others.
+            PES_END_INT_RAW: u1,
+            /// The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when
+            /// WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
+            WPE_END_INT_RAW: u1,
+            /// The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st
+            /// is changed from non idle state to idle state. It means that SPI_CS raises high.
+            /// 0: Others
+            SLV_ST_END_INT_RAW: u1,
+            /// The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st
+            /// is changed from non idle state to idle state. 0: Others.
+            MST_ST_END_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xc8);
+
+        /// address: 0x600020cc
+        /// SPI1 interrupt status register
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The status bit for SPI_MEM_PER_END_INT interrupt.
+            PER_END_INT_ST: u1,
+            /// The status bit for SPI_MEM_PES_END_INT interrupt.
+            PES_END_INT_ST: u1,
+            /// The status bit for SPI_MEM_WPE_END_INT interrupt.
+            WPE_END_INT_ST: u1,
+            /// The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+            SLV_ST_END_INT_ST: u1,
+            /// The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+            MST_ST_END_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0xcc);
+
+        /// address: 0x600020dc
+        /// SPI1 clk_gate register
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Register clock gate enable signal. 1: Enable. 0: Disable.
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xdc);
+
+        /// address: 0x600023fc
+        /// Version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x3fc);
+    };
+
+    /// SPI (Serial Peripheral Interface) Controller
+    pub const SPI2 = struct {
+        pub const base_address = 0x60024000;
+
+        /// address: 0x60024000
+        /// Command control register
+        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
+            CONF_BITLEN: u18,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            /// Set this bit to synchronize SPI registers from APB clock domain into SPI module
+            /// clock domain, which is only used in SPI master mode.
+            UPDATE: u1,
+            /// User define command enable. An operation will be triggered when the bit is set.
+            /// The bit will be cleared once the operation done.1: enable 0: disable. Can not be
+            /// changed by CONF_buf.
+            USR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60024004
+        /// Address value register
+        pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Address to slave. Can be configured in CONF state.
+            USR_ADDR_VALUE: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60024008
+        /// SPI control register
+        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// In the dummy phase the signal level of spi is output by the spi controller. Can
+            /// be configured in CONF state.
+            DUMMY_OUT: u1,
+            reserved3: u1,
+            /// Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+            /// state.
+            FADDR_DUAL: u1,
+            /// Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
+            /// state.
+            FADDR_QUAD: u1,
+            reserved4: u1,
+            /// Apply 2 signals during command phase 1:enable 0: disable. Can be configured in
+            /// CONF state.
+            FCMD_DUAL: u1,
+            /// Apply 4 signals during command phase 1:enable 0: disable. Can be configured in
+            /// CONF state.
+            FCMD_QUAD: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+            /// Can be configured in CONF state.
+            FREAD_DUAL: u1,
+            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+            /// Can be configured in CONF state.
+            FREAD_QUAD: u1,
+            reserved9: u1,
+            reserved10: u1,
+            /// The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
+            /// CONF state.
+            Q_POL: u1,
+            /// The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
+            /// CONF state.
+            D_POL: u1,
+            /// SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
+            /// configured in CONF state.
+            HOLD_POL: u1,
+            /// Write protect signal output when SPI is idle. 1: output high, 0: output low. Can
+            /// be configured in CONF state.
+            WP_POL: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
+            /// state.
+            RD_BIT_ORDER: u1,
+            /// In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
+            /// configured in CONF state.
+            WR_BIT_ORDER: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6002400c
+        /// SPI clock control register
+        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must
+            /// be 0. Can be configured in CONF state.
+            CLKCNT_L: u6,
+            /// In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
+            /// must be 0. Can be configured in CONF state.
+            CLKCNT_H: u6,
+            /// In the master mode it is the divider of spi_clk. So spi_clk frequency is
+            /// system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+            CLKCNT_N: u6,
+            /// In the master mode it is pre-divider of spi_clk. Can be configured in CONF
+            /// state.
+            CLKDIV_PRE: u4,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from
+            /// system clock. Can be configured in CONF state.
+            CLK_EQU_SYSCLK: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60024010
+        /// SPI USER control register
+        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
+            /// configured in CONF state.
+            DOUTDIN: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// Both for master mode and slave mode. 1: spi controller is in QPI mode. 0:
+            /// others. Can be configured in CONF state.
+            QPI_MODE: u1,
+            reserved2: u1,
+            /// In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
+            /// = spi_ck_i. 1:tsck = !spi_ck_i.
+            TSCK_I_EDGE: u1,
+            /// spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be
+            /// configured in CONF state.
+            CS_HOLD: u1,
+            /// spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be
+            /// configured in CONF state.
+            CS_SETUP: u1,
+            /// In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
+            /// = !spi_ck_i. 1:rsck = spi_ck_i.
+            RSCK_I_EDGE: u1,
+            /// the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.
+            /// Can be configured in CONF state.
+            CK_OUT_EDGE: u1,
+            reserved3: u1,
+            reserved4: u1,
+            /// In the write operations read-data phase apply 2 signals. Can be configured in
+            /// CONF state.
+            FWRITE_DUAL: u1,
+            /// In the write operations read-data phase apply 4 signals. Can be configured in
+            /// CONF state.
+            FWRITE_QUAD: u1,
+            reserved5: u1,
+            /// 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
+            /// will continue. 0: The seg-trans will end after the current SPI seg-trans or this
+            /// is not seg-trans mode. Can be configured in CONF state.
+            USR_CONF_NXT: u1,
+            reserved6: u1,
+            /// Set the bit to enable 3-line half duplex communication mosi and miso signals
+            /// share the same pin. 1: enable 0: disable. Can be configured in CONF state.
+            SIO: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            /// read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
+            /// 0: disable. Can be configured in CONF state.
+            USR_MISO_HIGHPART: u1,
+            /// write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1:
+            /// enable 0: disable. Can be configured in CONF state.
+            USR_MOSI_HIGHPART: u1,
+            /// spi clock is disable in dummy phase when the bit is enable. Can be configured in
+            /// CONF state.
+            USR_DUMMY_IDLE: u1,
+            /// This bit enable the write-data phase of an operation. Can be configured in CONF
+            /// state.
+            USR_MOSI: u1,
+            /// This bit enable the read-data phase of an operation. Can be configured in CONF
+            /// state.
+            USR_MISO: u1,
+            /// This bit enable the dummy phase of an operation. Can be configured in CONF
+            /// state.
+            USR_DUMMY: u1,
+            /// This bit enable the address phase of an operation. Can be configured in CONF
+            /// state.
+            USR_ADDR: u1,
+            /// This bit enable the command phase of an operation. Can be configured in CONF
+            /// state.
+            USR_COMMAND: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60024014
+        /// SPI USER control register 1
+        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The length in spi_clk cycles of dummy phase. The register value shall be
+            /// (cycle_num-1). Can be configured in CONF state.
+            USR_DUMMY_CYCLELEN: u8,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
+            /// FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
+            /// in GP-SPI master FD/HD-mode.
+            MST_WFULL_ERR_END_EN: u1,
+            /// (cycles+1) of prepare phase by spi clock this bits are combined with
+            /// spi_cs_setup bit. Can be configured in CONF state.
+            CS_SETUP_TIME: u5,
+            /// delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
+            /// Can be configured in CONF state.
+            CS_HOLD_TIME: u5,
+            /// The length in bits of address phase. The register value shall be (bit_num-1).
+            /// Can be configured in CONF state.
+            USR_ADDR_BITLEN: u5,
+        }), base_address + 0x14);
+
+        /// address: 0x60024018
+        /// SPI USER control register 2
+        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of command. Can be configured in CONF state.
+            USR_COMMAND_VALUE: u16,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            /// 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
+            /// master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty
+            /// error is valid in GP-SPI master FD/HD-mode.
+            MST_REMPTY_ERR_END_EN: u1,
+            /// The length in bits of command phase. The register value shall be (bit_num-1).
+            /// Can be configured in CONF state.
+            USR_COMMAND_BITLEN: u4,
+        }), base_address + 0x18);
+
+        /// address: 0x6002401c
+        /// SPI data bit length control register
+        pub const MS_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The value of these bits is the configured SPI transmission data bit length in
+            /// master mode DMA controlled transfer or CPU controlled transfer. The value is
+            /// also the configured bit length in slave mode DMA RX controlled transfer. The
+            /// register value shall be (bit_num-1). Can be configured in CONF state.
+            MS_DATA_BITLEN: u18,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60024020
+        /// SPI misc register
+        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be
+            /// configured in CONF state.
+            CS0_DIS: u1,
+            /// SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be
+            /// configured in CONF state.
+            CS1_DIS: u1,
+            /// SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be
+            /// configured in CONF state.
+            CS2_DIS: u1,
+            /// SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be
+            /// configured in CONF state.
+            CS3_DIS: u1,
+            /// SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be
+            /// configured in CONF state.
+            CS4_DIS: u1,
+            /// SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be
+            /// configured in CONF state.
+            CS5_DIS: u1,
+            /// 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.
+            CK_DIS: u1,
+            /// In the master mode the bits are the polarity of spi cs line, the value is
+            /// equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+            MASTER_CS_POL: u6,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            /// spi slave input cs polarity select. 1: inv 0: not change. Can be configured in
+            /// CONF state.
+            SLAVE_CS_POL: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be
+            /// configured in CONF state.
+            CK_IDLE_EDGE: u1,
+            /// spi cs line keep low when the bit is set. Can be configured in CONF state.
+            CS_KEEP_ACTIVE: u1,
+            /// 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured
+            /// in CONF state.
+            QUAD_DIN_PIN_SWAP: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60024024
+        /// SPI input delay mode configuration
+        pub const DIN_MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the input signals are delayed by SPI module clock cycles, 0: input without
+            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
+            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+            DIN0_MODE: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: input without
+            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
+            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+            DIN1_MODE: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: input without
+            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
+            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+            DIN2_MODE: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: input without
+            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
+            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+            DIN3_MODE: u2,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in
+            /// CONF state.
+            TIMING_HCLK_ACTIVE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60024028
+        /// SPI input delay number configuration
+        pub const DIN_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
+            DIN0_NUM: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
+            DIN1_NUM: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
+            DIN2_NUM: u2,
+            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
+            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
+            DIN3_NUM: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6002402c
+        /// SPI output delay mode configuration
+        pub const DOUT_MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The output signal 0 is delayed by the SPI module clock, 0: output without
+            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
+            /// be configured in CONF state.
+            DOUT0_MODE: u1,
+            /// The output signal 1 is delayed by the SPI module clock, 0: output without
+            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
+            /// be configured in CONF state.
+            DOUT1_MODE: u1,
+            /// The output signal 2 is delayed by the SPI module clock, 0: output without
+            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
+            /// be configured in CONF state.
+            DOUT2_MODE: u1,
+            /// The output signal 3 is delayed by the SPI module clock, 0: output without
+            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
+            /// be configured in CONF state.
+            DOUT3_MODE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60024030
+        /// SPI DMA control register
+        pub const DMA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            /// Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+            DMA_SLV_SEG_TRANS_EN: u1,
+            /// 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
+            /// spi_dma_infifo_full_vld is cleared by spi_trans_done.
+            SLV_RX_SEG_TRANS_CLR_EN: u1,
+            /// 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
+            /// spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+            SLV_TX_SEG_TRANS_CLR_EN: u1,
+            /// 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal
+            /// to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0:
+            /// spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
+            /// spi_dma_seg_trans_done in seg-trans.
+            RX_EOF_EN: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            /// Set this bit to enable SPI DMA controlled receive data mode.
+            DMA_RX_ENA: u1,
+            /// Set this bit to enable SPI DMA controlled send data mode.
+            DMA_TX_ENA: u1,
+            /// Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
+            /// slave mode transfer.
+            RX_AFIFO_RST: u1,
+            /// Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
+            /// controlled mode transfer and master mode transfer.
+            BUF_AFIFO_RST: u1,
+            /// Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
+            /// DMA controlled mode transfer.
+            DMA_AFIFO_RST: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60024034
+        /// SPI DMA interrupt enable register
+        pub const DMA_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+            DMA_INFIFO_FULL_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+            DMA_OUTFIFO_EMPTY_ERR_INT_ENA: u1,
+            /// The enable bit for SPI slave Ex_QPI interrupt.
+            SLV_EX_QPI_INT_ENA: u1,
+            /// The enable bit for SPI slave En_QPI interrupt.
+            SLV_EN_QPI_INT_ENA: u1,
+            /// The enable bit for SPI slave CMD7 interrupt.
+            SLV_CMD7_INT_ENA: u1,
+            /// The enable bit for SPI slave CMD8 interrupt.
+            SLV_CMD8_INT_ENA: u1,
+            /// The enable bit for SPI slave CMD9 interrupt.
+            SLV_CMD9_INT_ENA: u1,
+            /// The enable bit for SPI slave CMDA interrupt.
+            SLV_CMDA_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+            SLV_RD_DMA_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+            SLV_WR_DMA_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+            SLV_RD_BUF_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+            SLV_WR_BUF_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_TRANS_DONE_INT interrupt.
+            TRANS_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+            DMA_SEG_TRANS_DONE_INT_ENA: u1,
+            /// The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+            SEG_MAGIC_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+            SLV_BUF_ADDR_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+            SLV_CMD_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+            MST_RX_AFIFO_WFULL_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+            MST_TX_AFIFO_REMPTY_ERR_INT_ENA: u1,
+            /// The enable bit for SPI_APP2_INT interrupt.
+            APP2_INT_ENA: u1,
+            /// The enable bit for SPI_APP1_INT interrupt.
+            APP1_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60024038
+        /// SPI DMA interrupt clear register
+        pub const DMA_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+            DMA_INFIFO_FULL_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+            DMA_OUTFIFO_EMPTY_ERR_INT_CLR: u1,
+            /// The clear bit for SPI slave Ex_QPI interrupt.
+            SLV_EX_QPI_INT_CLR: u1,
+            /// The clear bit for SPI slave En_QPI interrupt.
+            SLV_EN_QPI_INT_CLR: u1,
+            /// The clear bit for SPI slave CMD7 interrupt.
+            SLV_CMD7_INT_CLR: u1,
+            /// The clear bit for SPI slave CMD8 interrupt.
+            SLV_CMD8_INT_CLR: u1,
+            /// The clear bit for SPI slave CMD9 interrupt.
+            SLV_CMD9_INT_CLR: u1,
+            /// The clear bit for SPI slave CMDA interrupt.
+            SLV_CMDA_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+            SLV_RD_DMA_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+            SLV_WR_DMA_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+            SLV_RD_BUF_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+            SLV_WR_BUF_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_TRANS_DONE_INT interrupt.
+            TRANS_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+            DMA_SEG_TRANS_DONE_INT_CLR: u1,
+            /// The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+            SEG_MAGIC_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+            SLV_BUF_ADDR_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+            SLV_CMD_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+            MST_RX_AFIFO_WFULL_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+            MST_TX_AFIFO_REMPTY_ERR_INT_CLR: u1,
+            /// The clear bit for SPI_APP2_INT interrupt.
+            APP2_INT_CLR: u1,
+            /// The clear bit for SPI_APP1_INT interrupt.
+            APP1_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6002403c
+        /// SPI DMA interrupt raw register
+        pub const DMA_INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
+            /// the receive data. 0: Others.
+            DMA_INFIFO_FULL_ERR_INT_RAW: u1,
+            /// 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
+            /// master mode and send out all 0 in slave mode. 0: Others.
+            DMA_OUTFIFO_EMPTY_ERR_INT_RAW: u1,
+            /// The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI
+            /// transmission is ended. 0: Others.
+            SLV_EX_QPI_INT_RAW: u1,
+            /// The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI
+            /// transmission is ended. 0: Others.
+            SLV_EN_QPI_INT_RAW: u1,
+            /// The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
+            /// ended. 0: Others.
+            SLV_CMD7_INT_RAW: u1,
+            /// The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
+            /// ended. 0: Others.
+            SLV_CMD8_INT_RAW: u1,
+            /// The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
+            /// ended. 0: Others.
+            SLV_CMD9_INT_RAW: u1,
+            /// The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
+            /// ended. 0: Others.
+            SLV_CMDA_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
+            /// transmission is ended. 0: Others.
+            SLV_RD_DMA_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
+            /// transmission is ended. 0: Others.
+            SLV_WR_DMA_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
+            /// transmission is ended. 0: Others.
+            SLV_RD_BUF_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
+            /// transmission is ended. 0: Others.
+            SLV_WR_BUF_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
+            /// ended. 0: others.
+            TRANS_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA
+            /// full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
+            /// And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans
+            /// is not ended or not occurred.
+            DMA_SEG_TRANS_DONE_INT_RAW: u1,
+            /// The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF
+            /// buffer is error in the DMA seg-conf-trans. 0: others.
+            SEG_MAGIC_ERR_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data
+            /// address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF
+            /// transmission is bigger than 63. 0: Others.
+            SLV_BUF_ADDR_ERR_INT_RAW: u1,
+            /// The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
+            /// current SPI slave HD mode transmission is not supported. 0: Others.
+            SLV_CMD_ERR_INT_RAW: u1,
+            /// The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
+            /// write-full error when SPI inputs data in master mode. 0: Others.
+            MST_RX_AFIFO_WFULL_ERR_INT_RAW: u1,
+            /// The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
+            /// AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+            MST_TX_AFIFO_REMPTY_ERR_INT_RAW: u1,
+            /// The raw bit for SPI_APP2_INT interrupt. The value is only controlled by
+            /// application.
+            APP2_INT_RAW: u1,
+            /// The raw bit for SPI_APP1_INT interrupt. The value is only controlled by
+            /// application.
+            APP1_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60024040
+        /// SPI DMA interrupt status register
+        pub const DMA_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+            DMA_INFIFO_FULL_ERR_INT_ST: u1,
+            /// The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+            DMA_OUTFIFO_EMPTY_ERR_INT_ST: u1,
+            /// The status bit for SPI slave Ex_QPI interrupt.
+            SLV_EX_QPI_INT_ST: u1,
+            /// The status bit for SPI slave En_QPI interrupt.
+            SLV_EN_QPI_INT_ST: u1,
+            /// The status bit for SPI slave CMD7 interrupt.
+            SLV_CMD7_INT_ST: u1,
+            /// The status bit for SPI slave CMD8 interrupt.
+            SLV_CMD8_INT_ST: u1,
+            /// The status bit for SPI slave CMD9 interrupt.
+            SLV_CMD9_INT_ST: u1,
+            /// The status bit for SPI slave CMDA interrupt.
+            SLV_CMDA_INT_ST: u1,
+            /// The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+            SLV_RD_DMA_DONE_INT_ST: u1,
+            /// The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+            SLV_WR_DMA_DONE_INT_ST: u1,
+            /// The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+            SLV_RD_BUF_DONE_INT_ST: u1,
+            /// The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+            SLV_WR_BUF_DONE_INT_ST: u1,
+            /// The status bit for SPI_TRANS_DONE_INT interrupt.
+            TRANS_DONE_INT_ST: u1,
+            /// The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+            DMA_SEG_TRANS_DONE_INT_ST: u1,
+            /// The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+            SEG_MAGIC_ERR_INT_ST: u1,
+            /// The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+            SLV_BUF_ADDR_ERR_INT_ST: u1,
+            /// The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+            SLV_CMD_ERR_INT_ST: u1,
+            /// The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+            MST_RX_AFIFO_WFULL_ERR_INT_ST: u1,
+            /// The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+            MST_TX_AFIFO_REMPTY_ERR_INT_ST: u1,
+            /// The status bit for SPI_APP2_INT interrupt.
+            APP2_INT_ST: u1,
+            /// The status bit for SPI_APP1_INT interrupt.
+            APP1_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60024098
+        /// SPI CPU-controlled buffer0
+        pub const W0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF0: u32,
+        }), base_address + 0x98);
+
+        /// address: 0x6002409c
+        /// SPI CPU-controlled buffer1
+        pub const W1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF1: u32,
+        }), base_address + 0x9c);
+
+        /// address: 0x600240a0
+        /// SPI CPU-controlled buffer2
+        pub const W2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF2: u32,
+        }), base_address + 0xa0);
+
+        /// address: 0x600240a4
+        /// SPI CPU-controlled buffer3
+        pub const W3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF3: u32,
+        }), base_address + 0xa4);
+
+        /// address: 0x600240a8
+        /// SPI CPU-controlled buffer4
+        pub const W4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF4: u32,
+        }), base_address + 0xa8);
+
+        /// address: 0x600240ac
+        /// SPI CPU-controlled buffer5
+        pub const W5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF5: u32,
+        }), base_address + 0xac);
+
+        /// address: 0x600240b0
+        /// SPI CPU-controlled buffer6
+        pub const W6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF6: u32,
+        }), base_address + 0xb0);
+
+        /// address: 0x600240b4
+        /// SPI CPU-controlled buffer7
+        pub const W7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF7: u32,
+        }), base_address + 0xb4);
+
+        /// address: 0x600240b8
+        /// SPI CPU-controlled buffer8
+        pub const W8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF8: u32,
+        }), base_address + 0xb8);
+
+        /// address: 0x600240bc
+        /// SPI CPU-controlled buffer9
+        pub const W9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF9: u32,
+        }), base_address + 0xbc);
+
+        /// address: 0x600240c0
+        /// SPI CPU-controlled buffer10
+        pub const W10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF10: u32,
+        }), base_address + 0xc0);
+
+        /// address: 0x600240c4
+        /// SPI CPU-controlled buffer11
+        pub const W11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF11: u32,
+        }), base_address + 0xc4);
+
+        /// address: 0x600240c8
+        /// SPI CPU-controlled buffer12
+        pub const W12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF12: u32,
+        }), base_address + 0xc8);
+
+        /// address: 0x600240cc
+        /// SPI CPU-controlled buffer13
+        pub const W13 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF13: u32,
+        }), base_address + 0xcc);
+
+        /// address: 0x600240d0
+        /// SPI CPU-controlled buffer14
+        pub const W14 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF14: u32,
+        }), base_address + 0xd0);
+
+        /// address: 0x600240d4
+        /// SPI CPU-controlled buffer15
+        pub const W15 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// data buffer
+            BUF15: u32,
+        }), base_address + 0xd4);
+
+        /// address: 0x600240e0
+        /// SPI slave control register
+        pub const SLAVE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
+            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
+            /// inactive 3: SPI clock is alwasy on. Can be configured in CONF state.
+            CLK_MODE: u2,
+            /// {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
+            /// 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+            CLK_MODE_13: u1,
+            /// It saves half a cycle when tsck is the same as rsck. 1: output data at rsck
+            /// posedge 0: output data at tsck posedge
+            RSCK_DATA_OUT: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length
+            /// in DMA controlled mode(Rd_DMA). 0: others
+            SLV_RDDMA_BITLEN_EN: u1,
+            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data
+            /// length in DMA controlled mode(Wr_DMA). 0: others
+            SLV_WRDMA_BITLEN_EN: u1,
+            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length
+            /// in CPU controlled mode(Rd_BUF). 0: others
+            SLV_RDBUF_BITLEN_EN: u1,
+            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data
+            /// length in CPU controlled mode(Wr_BUF). 0: others
+            SLV_WRBUF_BITLEN_EN: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            /// The magic value of BM table in master DMA seg-trans.
+            DMA_SEG_MAGIC_VALUE: u4,
+            /// Set SPI work mode. 1: slave mode 0: master mode.
+            MODE: u1,
+            /// Software reset enable, reset the spi clock line cs line and data lines. Can be
+            /// configured in CONF state.
+            SOFT_RESET: u1,
+            /// 1: Enable the DMA CONF phase of current seg-trans operation, which means
+            /// seg-trans will start. 0: This is not seg-trans mode.
+            USR_CONF: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0xe0);
+
+        /// address: 0x600240e4
+        /// SPI slave control register 1
+        pub const SLAVE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The transferred data bit length in SPI slave FD and HD mode.
+            SLV_DATA_BITLEN: u18,
+            /// In the slave mode it is the value of command.
+            SLV_LAST_COMMAND: u8,
+            /// In the slave mode it is the value of address.
+            SLV_LAST_ADDR: u6,
+        }), base_address + 0xe4);
+
+        /// address: 0x600240e8
+        /// SPI module clock and register clock control
+        pub const CLK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to enable clk gate
+            CLK_EN: u1,
+            /// Set this bit to power on the SPI module clock.
+            MST_CLK_ACTIVE: u1,
+            /// This bit is used to select SPI module clock source in master mode. 1:
+            /// PLL_CLK_80M. 0: XTAL CLK.
+            MST_CLK_SEL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0xe8);
+
+        /// address: 0x600240f0
+        /// Version control
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xf0);
+    };
+
+    /// System
+    pub const SYSTEM = struct {
+        pub const base_address = 0x600c0000;
+
+        /// address: 0x600c0000
+        /// cpu_peripheral clock gating register
+        pub const CPU_PERI_CLK_EN = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// reg_clk_en_assist_debug
+            CLK_EN_ASSIST_DEBUG: u1,
+            /// reg_clk_en_dedicated_gpio
+            CLK_EN_DEDICATED_GPIO: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x600c0004
+        /// cpu_peripheral reset register
+        pub const CPU_PERI_RST_EN = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// reg_rst_en_assist_debug
+            RST_EN_ASSIST_DEBUG: u1,
+            /// reg_rst_en_dedicated_gpio
+            RST_EN_DEDICATED_GPIO: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x600c0008
+        /// cpu clock config register
+        pub const CPU_PER_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_cpuperiod_sel
+            CPUPERIOD_SEL: u2,
+            /// reg_pll_freq_sel
+            PLL_FREQ_SEL: u1,
+            /// reg_cpu_wait_mode_force_on
+            CPU_WAIT_MODE_FORCE_ON: u1,
+            /// reg_cpu_waiti_delay_num
+            CPU_WAITI_DELAY_NUM: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x600c000c
+        /// memory power down mask register
+        pub const MEM_PD_MASK = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_lslp_mem_pd_mask
+            LSLP_MEM_PD_MASK: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x600c0010
+        /// peripheral clock gating register
+        pub const PERIP_CLK_EN0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timers_clk_en
+            TIMERS_CLK_EN: u1,
+            /// reg_spi01_clk_en
+            SPI01_CLK_EN: u1,
+            /// reg_uart_clk_en
+            UART_CLK_EN: u1,
+            /// reg_wdg_clk_en
+            WDG_CLK_EN: u1,
+            /// reg_i2s0_clk_en
+            I2S0_CLK_EN: u1,
+            /// reg_uart1_clk_en
+            UART1_CLK_EN: u1,
+            /// reg_spi2_clk_en
+            SPI2_CLK_EN: u1,
+            /// reg_ext0_clk_en
+            I2C_EXT0_CLK_EN: u1,
+            /// reg_uhci0_clk_en
+            UHCI0_CLK_EN: u1,
+            /// reg_rmt_clk_en
+            RMT_CLK_EN: u1,
+            /// reg_pcnt_clk_en
+            PCNT_CLK_EN: u1,
+            /// reg_ledc_clk_en
+            LEDC_CLK_EN: u1,
+            /// reg_uhci1_clk_en
+            UHCI1_CLK_EN: u1,
+            /// reg_timergroup_clk_en
+            TIMERGROUP_CLK_EN: u1,
+            /// reg_efuse_clk_en
+            EFUSE_CLK_EN: u1,
+            /// reg_timergroup1_clk_en
+            TIMERGROUP1_CLK_EN: u1,
+            /// reg_spi3_clk_en
+            SPI3_CLK_EN: u1,
+            /// reg_pwm0_clk_en
+            PWM0_CLK_EN: u1,
+            /// reg_ext1_clk_en
+            EXT1_CLK_EN: u1,
+            /// reg_can_clk_en
+            CAN_CLK_EN: u1,
+            /// reg_pwm1_clk_en
+            PWM1_CLK_EN: u1,
+            /// reg_i2s1_clk_en
+            I2S1_CLK_EN: u1,
+            /// reg_spi2_dma_clk_en
+            SPI2_DMA_CLK_EN: u1,
+            /// reg_usb_device_clk_en
+            USB_DEVICE_CLK_EN: u1,
+            /// reg_uart_mem_clk_en
+            UART_MEM_CLK_EN: u1,
+            /// reg_pwm2_clk_en
+            PWM2_CLK_EN: u1,
+            /// reg_pwm3_clk_en
+            PWM3_CLK_EN: u1,
+            /// reg_spi3_dma_clk_en
+            SPI3_DMA_CLK_EN: u1,
+            /// reg_apb_saradc_clk_en
+            APB_SARADC_CLK_EN: u1,
+            /// reg_systimer_clk_en
+            SYSTIMER_CLK_EN: u1,
+            /// reg_adc2_arb_clk_en
+            ADC2_ARB_CLK_EN: u1,
+            /// reg_spi4_clk_en
+            SPI4_CLK_EN: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x600c0014
+        /// peripheral clock gating register
+        pub const PERIP_CLK_EN1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// reg_crypto_aes_clk_en
+            CRYPTO_AES_CLK_EN: u1,
+            /// reg_crypto_sha_clk_en
+            CRYPTO_SHA_CLK_EN: u1,
+            /// reg_crypto_rsa_clk_en
+            CRYPTO_RSA_CLK_EN: u1,
+            /// reg_crypto_ds_clk_en
+            CRYPTO_DS_CLK_EN: u1,
+            /// reg_crypto_hmac_clk_en
+            CRYPTO_HMAC_CLK_EN: u1,
+            /// reg_dma_clk_en
+            DMA_CLK_EN: u1,
+            /// reg_sdio_host_clk_en
+            SDIO_HOST_CLK_EN: u1,
+            /// reg_lcd_cam_clk_en
+            LCD_CAM_CLK_EN: u1,
+            /// reg_uart2_clk_en
+            UART2_CLK_EN: u1,
+            /// reg_tsens_clk_en
+            TSENS_CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x600c0018
+        /// reserved
+        pub const PERIP_RST_EN0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_timers_rst
+            TIMERS_RST: u1,
+            /// reg_spi01_rst
+            SPI01_RST: u1,
+            /// reg_uart_rst
+            UART_RST: u1,
+            /// reg_wdg_rst
+            WDG_RST: u1,
+            /// reg_i2s0_rst
+            I2S0_RST: u1,
+            /// reg_uart1_rst
+            UART1_RST: u1,
+            /// reg_spi2_rst
+            SPI2_RST: u1,
+            /// reg_ext0_rst
+            I2C_EXT0_RST: u1,
+            /// reg_uhci0_rst
+            UHCI0_RST: u1,
+            /// reg_rmt_rst
+            RMT_RST: u1,
+            /// reg_pcnt_rst
+            PCNT_RST: u1,
+            /// reg_ledc_rst
+            LEDC_RST: u1,
+            /// reg_uhci1_rst
+            UHCI1_RST: u1,
+            /// reg_timergroup_rst
+            TIMERGROUP_RST: u1,
+            /// reg_efuse_rst
+            EFUSE_RST: u1,
+            /// reg_timergroup1_rst
+            TIMERGROUP1_RST: u1,
+            /// reg_spi3_rst
+            SPI3_RST: u1,
+            /// reg_pwm0_rst
+            PWM0_RST: u1,
+            /// reg_ext1_rst
+            EXT1_RST: u1,
+            /// reg_can_rst
+            CAN_RST: u1,
+            /// reg_pwm1_rst
+            PWM1_RST: u1,
+            /// reg_i2s1_rst
+            I2S1_RST: u1,
+            /// reg_spi2_dma_rst
+            SPI2_DMA_RST: u1,
+            /// reg_usb_device_rst
+            USB_DEVICE_RST: u1,
+            /// reg_uart_mem_rst
+            UART_MEM_RST: u1,
+            /// reg_pwm2_rst
+            PWM2_RST: u1,
+            /// reg_pwm3_rst
+            PWM3_RST: u1,
+            /// reg_spi3_dma_rst
+            SPI3_DMA_RST: u1,
+            /// reg_apb_saradc_rst
+            APB_SARADC_RST: u1,
+            /// reg_systimer_rst
+            SYSTIMER_RST: u1,
+            /// reg_adc2_arb_rst
+            ADC2_ARB_RST: u1,
+            /// reg_spi4_rst
+            SPI4_RST: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x600c001c
+        /// peripheral reset register
+        pub const PERIP_RST_EN1 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// reg_crypto_aes_rst
+            CRYPTO_AES_RST: u1,
+            /// reg_crypto_sha_rst
+            CRYPTO_SHA_RST: u1,
+            /// reg_crypto_rsa_rst
+            CRYPTO_RSA_RST: u1,
+            /// reg_crypto_ds_rst
+            CRYPTO_DS_RST: u1,
+            /// reg_crypto_hmac_rst
+            CRYPTO_HMAC_RST: u1,
+            /// reg_dma_rst
+            DMA_RST: u1,
+            /// reg_sdio_host_rst
+            SDIO_HOST_RST: u1,
+            /// reg_lcd_cam_rst
+            LCD_CAM_RST: u1,
+            /// reg_uart2_rst
+            UART2_RST: u1,
+            /// reg_tsens_rst
+            TSENS_RST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x600c0020
+        /// clock config register
+        pub const BT_LPCK_DIV_INT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_bt_lpck_div_num
+            BT_LPCK_DIV_NUM: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x600c0024
+        /// clock config register
+        pub const BT_LPCK_DIV_FRAC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_bt_lpck_div_b
+            BT_LPCK_DIV_B: u12,
+            /// reg_bt_lpck_div_a
+            BT_LPCK_DIV_A: u12,
+            /// reg_lpclk_sel_rtc_slow
+            LPCLK_SEL_RTC_SLOW: u1,
+            /// reg_lpclk_sel_8m
+            LPCLK_SEL_8M: u1,
+            /// reg_lpclk_sel_xtal
+            LPCLK_SEL_XTAL: u1,
+            /// reg_lpclk_sel_xtal32k
+            LPCLK_SEL_XTAL32K: u1,
+            /// reg_lpclk_rtc_en
+            LPCLK_RTC_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x600c0028
+        /// interrupt generate register
+        pub const CPU_INTR_FROM_CPU_0 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x28);
+
+        /// address: 0x600c002c
+        /// interrupt generate register
+        pub const CPU_INTR_FROM_CPU_1 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x2c);
+
+        /// address: 0x600c0030
+        /// interrupt generate register
+        pub const CPU_INTR_FROM_CPU_2 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x30);
+
+        /// address: 0x600c0034
+        /// interrupt generate register
+        pub const CPU_INTR_FROM_CPU_3 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x34);
+
+        /// address: 0x600c0038
+        /// rsa memory power control register
+        pub const RSA_PD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rsa_mem_pd
+            RSA_MEM_PD: u1,
+            /// reg_rsa_mem_force_pu
+            RSA_MEM_FORCE_PU: u1,
+            /// reg_rsa_mem_force_pd
+            RSA_MEM_FORCE_PD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x600c003c
+        /// edma clcok and reset register
+        pub const EDMA_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_edma_clk_on
+            EDMA_CLK_ON: u1,
+            /// reg_edma_reset
+            EDMA_RESET: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x600c0040
+        /// cache control register
+        pub const CACHE_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_icache_clk_on
+            ICACHE_CLK_ON: u1,
+            /// reg_icache_reset
+            ICACHE_RESET: u1,
+            /// reg_dcache_clk_on
+            DCACHE_CLK_ON: u1,
+            /// reg_dcache_reset
+            DCACHE_RESET: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x600c0044
+        /// SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
+        pub const EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_enable_spi_manual_encrypt
+            ENABLE_SPI_MANUAL_ENCRYPT: u1,
+            /// reg_enable_download_db_encrypt
+            ENABLE_DOWNLOAD_DB_ENCRYPT: u1,
+            /// reg_enable_download_g0cb_decrypt
+            ENABLE_DOWNLOAD_G0CB_DECRYPT: u1,
+            /// reg_enable_download_manual_encrypt
+            ENABLE_DOWNLOAD_MANUAL_ENCRYPT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x600c0048
+        /// fast memory config register
+        pub const RTC_FASTMEM_CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// reg_rtc_mem_crc_start
+            RTC_MEM_CRC_START: u1,
+            /// reg_rtc_mem_crc_addr
+            RTC_MEM_CRC_ADDR: u11,
+            /// reg_rtc_mem_crc_len
+            RTC_MEM_CRC_LEN: u11,
+            /// reg_rtc_mem_crc_finish
+            RTC_MEM_CRC_FINISH: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x600c004c
+        /// reserved
+        pub const RTC_FASTMEM_CRC = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_rtc_mem_crc_res
+            RTC_MEM_CRC_RES: u32,
+        }), base_address + 0x4c);
+
+        /// address: 0x600c0050
+        /// eco register
+        pub const REDUNDANT_ECO_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_redundant_eco_drive
+            REDUNDANT_ECO_DRIVE: u1,
+            /// reg_redundant_eco_result
+            REDUNDANT_ECO_RESULT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x600c0054
+        /// clock gating register
+        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_clk_en
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x600c0058
+        /// system clock config register
+        pub const SYSCLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_pre_div_cnt
+            PRE_DIV_CNT: u10,
+            /// reg_soc_clk_sel
+            SOC_CLK_SEL: u2,
+            /// reg_clk_xtal_freq
+            CLK_XTAL_FREQ: u7,
+            /// reg_clk_div_en
+            CLK_DIV_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x600c005c
+        /// mem pvt register
+        pub const MEM_PVT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_mem_path_len
+            MEM_PATH_LEN: u4,
+            /// reg_mem_err_cnt_clr
+            MEM_ERR_CNT_CLR: u1,
+            /// reg_mem_pvt_monitor_en
+            MONITOR_EN: u1,
+            /// reg_mem_timing_err_cnt
+            MEM_TIMING_ERR_CNT: u16,
+            /// reg_mem_vt_sel
+            MEM_VT_SEL: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x600c0060
+        /// mem pvt register
+        pub const COMB_PVT_LVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_path_len_lvt
+            COMB_PATH_LEN_LVT: u5,
+            /// reg_comb_err_cnt_clr_lvt
+            COMB_ERR_CNT_CLR_LVT: u1,
+            /// reg_comb_pvt_monitor_en_lvt
+            COMB_PVT_MONITOR_EN_LVT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x600c0064
+        /// mem pvt register
+        pub const COMB_PVT_NVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_path_len_nvt
+            COMB_PATH_LEN_NVT: u5,
+            /// reg_comb_err_cnt_clr_nvt
+            COMB_ERR_CNT_CLR_NVT: u1,
+            /// reg_comb_pvt_monitor_en_nvt
+            COMB_PVT_MONITOR_EN_NVT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x600c0068
+        /// mem pvt register
+        pub const COMB_PVT_HVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_path_len_hvt
+            COMB_PATH_LEN_HVT: u5,
+            /// reg_comb_err_cnt_clr_hvt
+            COMB_ERR_CNT_CLR_HVT: u1,
+            /// reg_comb_pvt_monitor_en_hvt
+            COMB_PVT_MONITOR_EN_HVT: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x600c006c
+        /// mem pvt register
+        pub const COMB_PVT_ERR_LVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_lvt_site0
+            COMB_TIMING_ERR_CNT_LVT_SITE0: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x600c0070
+        /// mem pvt register
+        pub const COMB_PVT_ERR_NVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_nvt_site0
+            COMB_TIMING_ERR_CNT_NVT_SITE0: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x600c0074
+        /// mem pvt register
+        pub const COMB_PVT_ERR_HVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_hvt_site0
+            COMB_TIMING_ERR_CNT_HVT_SITE0: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x600c0078
+        /// mem pvt register
+        pub const COMB_PVT_ERR_LVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_lvt_site1
+            COMB_TIMING_ERR_CNT_LVT_SITE1: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x600c007c
+        /// mem pvt register
+        pub const COMB_PVT_ERR_NVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_nvt_site1
+            COMB_TIMING_ERR_CNT_NVT_SITE1: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x600c0080
+        /// mem pvt register
+        pub const COMB_PVT_ERR_HVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_hvt_site1
+            COMB_TIMING_ERR_CNT_HVT_SITE1: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x80);
+
+        /// address: 0x600c0084
+        /// mem pvt register
+        pub const COMB_PVT_ERR_LVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_lvt_site2
+            COMB_TIMING_ERR_CNT_LVT_SITE2: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x84);
+
+        /// address: 0x600c0088
+        /// mem pvt register
+        pub const COMB_PVT_ERR_NVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_nvt_site2
+            COMB_TIMING_ERR_CNT_NVT_SITE2: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x88);
+
+        /// address: 0x600c008c
+        /// mem pvt register
+        pub const COMB_PVT_ERR_HVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_hvt_site2
+            COMB_TIMING_ERR_CNT_HVT_SITE2: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x8c);
+
+        /// address: 0x600c0090
+        /// mem pvt register
+        pub const COMB_PVT_ERR_LVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_lvt_site3
+            COMB_TIMING_ERR_CNT_LVT_SITE3: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x90);
+
+        /// address: 0x600c0094
+        /// mem pvt register
+        pub const COMB_PVT_ERR_NVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_nvt_site3
+            COMB_TIMING_ERR_CNT_NVT_SITE3: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x94);
+
+        /// address: 0x600c0098
+        /// mem pvt register
+        pub const COMB_PVT_ERR_HVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_comb_timing_err_cnt_hvt_site3
+            COMB_TIMING_ERR_CNT_HVT_SITE3: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x98);
+
+        /// address: 0x600c0ffc
+        /// Version register
+        pub const SYSTEM_REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xffc);
+    };
+
+    /// System Timer
+    pub const SYSTIMER = struct {
+        pub const base_address = 0x60023000;
+
+        /// address: 0x60023000
+        /// SYSTIMER_CONF.
+        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// systimer clock force on
+            SYSTIMER_CLK_FO: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            /// target2 work enable
+            TARGET2_WORK_EN: u1,
+            /// target1 work enable
+            TARGET1_WORK_EN: u1,
+            /// target0 work enable
+            TARGET0_WORK_EN: u1,
+            /// If timer unit1 is stalled when core1 stalled
+            TIMER_UNIT1_CORE1_STALL_EN: u1,
+            /// If timer unit1 is stalled when core0 stalled
+            TIMER_UNIT1_CORE0_STALL_EN: u1,
+            /// If timer unit0 is stalled when core1 stalled
+            TIMER_UNIT0_CORE1_STALL_EN: u1,
+            /// If timer unit0 is stalled when core0 stalled
+            TIMER_UNIT0_CORE0_STALL_EN: u1,
+            /// timer unit1 work enable
+            TIMER_UNIT1_WORK_EN: u1,
+            /// timer unit0 work enable
+            TIMER_UNIT0_WORK_EN: u1,
+            /// register file clk gating
+            CLK_EN: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60023004
+        /// SYSTIMER_UNIT0_OP.
+        pub const UNIT0_OP = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// reg_timer_unit0_value_valid
+            TIMER_UNIT0_VALUE_VALID: u1,
+            /// update timer_unit0
+            TIMER_UNIT0_UPDATE: u1,
+            padding0: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60023008
+        /// SYSTIMER_UNIT1_OP.
+        pub const UNIT1_OP = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// timer value is sync and valid
+            TIMER_UNIT1_VALUE_VALID: u1,
+            /// update timer unit1
+            TIMER_UNIT1_UPDATE: u1,
+            padding0: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6002300c
+        /// SYSTIMER_UNIT0_LOAD_HI.
+        pub const UNIT0_LOAD_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit0 load high 32 bit
+            TIMER_UNIT0_LOAD_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60023010
+        /// SYSTIMER_UNIT0_LOAD_LO.
+        pub const UNIT0_LOAD_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit0 load low 32 bit
+            TIMER_UNIT0_LOAD_LO: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x60023014
+        /// SYSTIMER_UNIT1_LOAD_HI.
+        pub const UNIT1_LOAD_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit1 load high 32 bit
+            TIMER_UNIT1_LOAD_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60023018
+        /// SYSTIMER_UNIT1_LOAD_LO.
+        pub const UNIT1_LOAD_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit1 load low 32 bit
+            TIMER_UNIT1_LOAD_LO: u32,
+        }), base_address + 0x18);
+
+        /// address: 0x6002301c
+        /// SYSTIMER_TARGET0_HI.
+        pub const TARGET0_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget0 high 32 bit
+            TIMER_TARGET0_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60023020
+        /// SYSTIMER_TARGET0_LO.
+        pub const TARGET0_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget0 low 32 bit
+            TIMER_TARGET0_LO: u32,
+        }), base_address + 0x20);
+
+        /// address: 0x60023024
+        /// SYSTIMER_TARGET1_HI.
+        pub const TARGET1_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget1 high 32 bit
+            TIMER_TARGET1_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60023028
+        /// SYSTIMER_TARGET1_LO.
+        pub const TARGET1_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget1 low 32 bit
+            TIMER_TARGET1_LO: u32,
+        }), base_address + 0x28);
+
+        /// address: 0x6002302c
+        /// SYSTIMER_TARGET2_HI.
+        pub const TARGET2_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget2 high 32 bit
+            TIMER_TARGET2_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60023030
+        /// SYSTIMER_TARGET2_LO.
+        pub const TARGET2_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer taget2 low 32 bit
+            TIMER_TARGET2_LO: u32,
+        }), base_address + 0x30);
+
+        /// address: 0x60023034
+        /// SYSTIMER_TARGET0_CONF.
+        pub const TARGET0_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// target0 period
+            TARGET0_PERIOD: u26,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// Set target0 to period mode
+            TARGET0_PERIOD_MODE: u1,
+            /// select which unit to compare
+            TARGET0_TIMER_UNIT_SEL: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60023038
+        /// SYSTIMER_TARGET1_CONF.
+        pub const TARGET1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// target1 period
+            TARGET1_PERIOD: u26,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// Set target1 to period mode
+            TARGET1_PERIOD_MODE: u1,
+            /// select which unit to compare
+            TARGET1_TIMER_UNIT_SEL: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6002303c
+        /// SYSTIMER_TARGET2_CONF.
+        pub const TARGET2_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// target2 period
+            TARGET2_PERIOD: u26,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            /// Set target2 to period mode
+            TARGET2_PERIOD_MODE: u1,
+            /// select which unit to compare
+            TARGET2_TIMER_UNIT_SEL: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60023040
+        /// SYSTIMER_UNIT0_VALUE_HI.
+        pub const UNIT0_VALUE_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer read value high 32bit
+            TIMER_UNIT0_VALUE_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60023044
+        /// SYSTIMER_UNIT0_VALUE_LO.
+        pub const UNIT0_VALUE_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer read value low 32bit
+            TIMER_UNIT0_VALUE_LO: u32,
+        }), base_address + 0x44);
+
+        /// address: 0x60023048
+        /// SYSTIMER_UNIT1_VALUE_HI.
+        pub const UNIT1_VALUE_HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer read value high 32bit
+            TIMER_UNIT1_VALUE_HI: u20,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6002304c
+        /// SYSTIMER_UNIT1_VALUE_LO.
+        pub const UNIT1_VALUE_LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer read value low 32bit
+            TIMER_UNIT1_VALUE_LO: u32,
+        }), base_address + 0x4c);
+
+        /// address: 0x60023050
+        /// SYSTIMER_COMP0_LOAD.
+        pub const COMP0_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer comp0 load value
+            TIMER_COMP0_LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60023054
+        /// SYSTIMER_COMP1_LOAD.
+        pub const COMP1_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer comp1 load value
+            TIMER_COMP1_LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60023058
+        /// SYSTIMER_COMP2_LOAD.
+        pub const COMP2_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer comp2 load value
+            TIMER_COMP2_LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6002305c
+        /// SYSTIMER_UNIT0_LOAD.
+        pub const UNIT0_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit0 load value
+            TIMER_UNIT0_LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60023060
+        /// SYSTIMER_UNIT1_LOAD.
+        pub const UNIT1_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timer unit1 load value
+            TIMER_UNIT1_LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60023064
+        /// SYSTIMER_INT_ENA.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// interupt0 enable
+            TARGET0_INT_ENA: u1,
+            /// interupt1 enable
+            TARGET1_INT_ENA: u1,
+            /// interupt2 enable
+            TARGET2_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60023068
+        /// SYSTIMER_INT_RAW.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// interupt0 raw
+            TARGET0_INT_RAW: u1,
+            /// interupt1 raw
+            TARGET1_INT_RAW: u1,
+            /// interupt2 raw
+            TARGET2_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6002306c
+        /// SYSTIMER_INT_CLR.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// interupt0 clear
+            TARGET0_INT_CLR: u1,
+            /// interupt1 clear
+            TARGET1_INT_CLR: u1,
+            /// interupt2 clear
+            TARGET2_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60023070
+        /// SYSTIMER_INT_ST.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_target0_int_st
+            TARGET0_INT_ST: u1,
+            /// reg_target1_int_st
+            TARGET1_INT_ST: u1,
+            /// reg_target2_int_st
+            TARGET2_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x600230fc
+        /// SYSTIMER_DATE.
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0xfc);
+    };
+
+    /// Timer Group
+    pub const TIMG0 = struct {
+        pub const base_address = 0x6001f000;
+
+        /// address: 0x6001f000
+        /// TIMG_T0CONFIG_REG.
+        pub const T0CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// reg_t0_use_xtal.
+            T0_USE_XTAL: u1,
+            /// reg_t0_alarm_en.
+            T0_ALARM_EN: u1,
+            reserved9: u1,
+            /// reg_t0_divcnt_rst.
+            T0_DIVCNT_RST: u1,
+            /// reg_t0_divider.
+            T0_DIVIDER: u16,
+            /// reg_t0_autoreload.
+            T0_AUTORELOAD: u1,
+            /// reg_t0_increase.
+            T0_INCREASE: u1,
+            /// reg_t0_en.
+            T0_EN: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x6001f004
+        /// TIMG_T0LO_REG.
+        pub const T0LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_lo
+            T0_LO: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x6001f008
+        /// TIMG_T0HI_REG.
+        pub const T0HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_hi
+            T0_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6001f00c
+        /// TIMG_T0UPDATE_REG.
+        pub const T0UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// t0_update
+            T0_UPDATE: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x6001f010
+        /// TIMG_T0ALARMLO_REG.
+        pub const T0ALARMLO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_alarm_lo.
+            T0_ALARM_LO: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x6001f014
+        /// TIMG_T0ALARMHI_REG.
+        pub const T0ALARMHI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_alarm_hi.
+            T0_ALARM_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x6001f018
+        /// TIMG_T0LOADLO_REG.
+        pub const T0LOADLO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_load_lo.
+            T0_LOAD_LO: u32,
+        }), base_address + 0x18);
+
+        /// address: 0x6001f01c
+        /// TIMG_T0LOADHI_REG.
+        pub const T0LOADHI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_load_hi.
+            T0_LOAD_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x6001f020
+        /// TIMG_T0LOAD_REG.
+        pub const T0LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_load
+            T0_LOAD: u32,
+        }), base_address + 0x20);
+
+        /// address: 0x6001f048
+        /// TIMG_WDTCONFIG0_REG.
+        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// reg_wdt_appcpu_reset_en.
+            WDT_APPCPU_RESET_EN: u1,
+            /// reg_wdt_procpu_reset_en.
+            WDT_PROCPU_RESET_EN: u1,
+            /// reg_wdt_flashboot_mod_en.
+            WDT_FLASHBOOT_MOD_EN: u1,
+            /// reg_wdt_sys_reset_length.
+            WDT_SYS_RESET_LENGTH: u3,
+            /// reg_wdt_cpu_reset_length.
+            WDT_CPU_RESET_LENGTH: u3,
+            /// reg_wdt_use_xtal.
+            WDT_USE_XTAL: u1,
+            /// reg_wdt_conf_update_en.
+            WDT_CONF_UPDATE_EN: u1,
+            /// reg_wdt_stg3.
+            WDT_STG3: u2,
+            /// reg_wdt_stg2.
+            WDT_STG2: u2,
+            /// reg_wdt_stg1.
+            WDT_STG1: u2,
+            /// reg_wdt_stg0.
+            WDT_STG0: u2,
+            /// reg_wdt_en.
+            WDT_EN: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6001f04c
+        /// TIMG_WDTCONFIG1_REG.
+        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_divcnt_rst.
+            WDT_DIVCNT_RST: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reg_wdt_clk_prescale.
+            WDT_CLK_PRESCALE: u16,
+        }), base_address + 0x4c);
+
+        /// address: 0x6001f050
+        /// TIMG_WDTCONFIG2_REG.
+        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg0_hold.
+            WDT_STG0_HOLD: u32,
+        }), base_address + 0x50);
+
+        /// address: 0x6001f054
+        /// TIMG_WDTCONFIG3_REG.
+        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg1_hold.
+            WDT_STG1_HOLD: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x6001f058
+        /// TIMG_WDTCONFIG4_REG.
+        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg2_hold.
+            WDT_STG2_HOLD: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6001f05c
+        /// TIMG_WDTCONFIG5_REG.
+        pub const WDTCONFIG5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg3_hold.
+            WDT_STG3_HOLD: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x6001f060
+        /// TIMG_WDTFEED_REG.
+        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
+            /// wdt_feed
+            WDT_FEED: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x6001f064
+        /// TIMG_WDTWPROTECT_REG.
+        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_wkey.
+            WDT_WKEY: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x6001f068
+        /// TIMG_RTCCALICFG_REG.
+        pub const RTCCALICFG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// reg_rtc_cali_start_cycling.
+            RTC_CALI_START_CYCLING: u1,
+            /// reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
+            RTC_CALI_CLK_SEL: u2,
+            /// rtc_cali_rdy
+            RTC_CALI_RDY: u1,
+            /// reg_rtc_cali_max.
+            RTC_CALI_MAX: u15,
+            /// reg_rtc_cali_start.
+            RTC_CALI_START: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6001f06c
+        /// TIMG_RTCCALICFG1_REG.
+        pub const RTCCALICFG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// rtc_cali_cycling_data_vld
+            RTC_CALI_CYCLING_DATA_VLD: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// rtc_cali_value
+            RTC_CALI_VALUE: u25,
+        }), base_address + 0x6c);
+
+        /// address: 0x6001f070
+        /// INT_ENA_TIMG_REG
+        pub const INT_ENA_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_ena
+            T0_INT_ENA: u1,
+            /// wdt_int_ena
+            WDT_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x6001f074
+        /// INT_RAW_TIMG_REG
+        pub const INT_RAW_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_raw
+            T0_INT_RAW: u1,
+            /// wdt_int_raw
+            WDT_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x6001f078
+        /// INT_ST_TIMG_REG
+        pub const INT_ST_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_st
+            T0_INT_ST: u1,
+            /// wdt_int_st
+            WDT_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6001f07c
+        /// INT_CLR_TIMG_REG
+        pub const INT_CLR_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_clr
+            T0_INT_CLR: u1,
+            /// wdt_int_clr
+            WDT_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x6001f080
+        /// TIMG_RTCCALICFG2_REG.
+        pub const RTCCALICFG2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timeoutindicator
+            RTC_CALI_TIMEOUT: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
+            RTC_CALI_TIMEOUT_RST_CNT: u4,
+            /// reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
+            RTC_CALI_TIMEOUT_THRES: u25,
+        }), base_address + 0x80);
+
+        /// address: 0x6001f0f8
+        /// TIMG_NTIMG_DATE_REG.
+        pub const NTIMG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_ntimers_date.
+            NTIMGS_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xf8);
+
+        /// address: 0x6001f0fc
+        /// TIMG_REGCLK_REG.
+        pub const REGCLK = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// reg_wdt_clk_is_active.
+            WDT_CLK_IS_ACTIVE: u1,
+            /// reg_timer_clk_is_active.
+            TIMER_CLK_IS_ACTIVE: u1,
+            /// reg_clk_en.
+            CLK_EN: u1,
+        }), base_address + 0xfc);
+    };
+
+    /// Timer Group
+    pub const TIMG1 = struct {
+        pub const base_address = 0x60020000;
+
+        /// address: 0x60020000
+        /// TIMG_T0CONFIG_REG.
+        pub const T0CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            /// reg_t0_use_xtal.
+            T0_USE_XTAL: u1,
+            /// reg_t0_alarm_en.
+            T0_ALARM_EN: u1,
+            reserved9: u1,
+            /// reg_t0_divcnt_rst.
+            T0_DIVCNT_RST: u1,
+            /// reg_t0_divider.
+            T0_DIVIDER: u16,
+            /// reg_t0_autoreload.
+            T0_AUTORELOAD: u1,
+            /// reg_t0_increase.
+            T0_INCREASE: u1,
+            /// reg_t0_en.
+            T0_EN: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60020004
+        /// TIMG_T0LO_REG.
+        pub const T0LO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_lo
+            T0_LO: u32,
+        }), base_address + 0x4);
+
+        /// address: 0x60020008
+        /// TIMG_T0HI_REG.
+        pub const T0HI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_hi
+            T0_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6002000c
+        /// TIMG_T0UPDATE_REG.
+        pub const T0UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            reserved29: u1,
+            reserved30: u1,
+            /// t0_update
+            T0_UPDATE: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60020010
+        /// TIMG_T0ALARMLO_REG.
+        pub const T0ALARMLO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_alarm_lo.
+            T0_ALARM_LO: u32,
+        }), base_address + 0x10);
+
+        /// address: 0x60020014
+        /// TIMG_T0ALARMHI_REG.
+        pub const T0ALARMHI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_alarm_hi.
+            T0_ALARM_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60020018
+        /// TIMG_T0LOADLO_REG.
+        pub const T0LOADLO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_load_lo.
+            T0_LOAD_LO: u32,
+        }), base_address + 0x18);
+
+        /// address: 0x6002001c
+        /// TIMG_T0LOADHI_REG.
+        pub const T0LOADHI = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_t0_load_hi.
+            T0_LOAD_HI: u22,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60020020
+        /// TIMG_T0LOAD_REG.
+        pub const T0LOAD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_load
+            T0_LOAD: u32,
+        }), base_address + 0x20);
+
+        /// address: 0x60020048
+        /// TIMG_WDTCONFIG0_REG.
+        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// reg_wdt_appcpu_reset_en.
+            WDT_APPCPU_RESET_EN: u1,
+            /// reg_wdt_procpu_reset_en.
+            WDT_PROCPU_RESET_EN: u1,
+            /// reg_wdt_flashboot_mod_en.
+            WDT_FLASHBOOT_MOD_EN: u1,
+            /// reg_wdt_sys_reset_length.
+            WDT_SYS_RESET_LENGTH: u3,
+            /// reg_wdt_cpu_reset_length.
+            WDT_CPU_RESET_LENGTH: u3,
+            /// reg_wdt_use_xtal.
+            WDT_USE_XTAL: u1,
+            /// reg_wdt_conf_update_en.
+            WDT_CONF_UPDATE_EN: u1,
+            /// reg_wdt_stg3.
+            WDT_STG3: u2,
+            /// reg_wdt_stg2.
+            WDT_STG2: u2,
+            /// reg_wdt_stg1.
+            WDT_STG1: u2,
+            /// reg_wdt_stg0.
+            WDT_STG0: u2,
+            /// reg_wdt_en.
+            WDT_EN: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6002004c
+        /// TIMG_WDTCONFIG1_REG.
+        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_divcnt_rst.
+            WDT_DIVCNT_RST: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            /// reg_wdt_clk_prescale.
+            WDT_CLK_PRESCALE: u16,
+        }), base_address + 0x4c);
+
+        /// address: 0x60020050
+        /// TIMG_WDTCONFIG2_REG.
+        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg0_hold.
+            WDT_STG0_HOLD: u32,
+        }), base_address + 0x50);
+
+        /// address: 0x60020054
+        /// TIMG_WDTCONFIG3_REG.
+        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg1_hold.
+            WDT_STG1_HOLD: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x60020058
+        /// TIMG_WDTCONFIG4_REG.
+        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg2_hold.
+            WDT_STG2_HOLD: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6002005c
+        /// TIMG_WDTCONFIG5_REG.
+        pub const WDTCONFIG5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_stg3_hold.
+            WDT_STG3_HOLD: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x60020060
+        /// TIMG_WDTFEED_REG.
+        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
+            /// wdt_feed
+            WDT_FEED: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x60020064
+        /// TIMG_WDTWPROTECT_REG.
+        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_wdt_wkey.
+            WDT_WKEY: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x60020068
+        /// TIMG_RTCCALICFG_REG.
+        pub const RTCCALICFG = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            /// reg_rtc_cali_start_cycling.
+            RTC_CALI_START_CYCLING: u1,
+            /// reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
+            RTC_CALI_CLK_SEL: u2,
+            /// rtc_cali_rdy
+            RTC_CALI_RDY: u1,
+            /// reg_rtc_cali_max.
+            RTC_CALI_MAX: u15,
+            /// reg_rtc_cali_start.
+            RTC_CALI_START: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6002006c
+        /// TIMG_RTCCALICFG1_REG.
+        pub const RTCCALICFG1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// rtc_cali_cycling_data_vld
+            RTC_CALI_CYCLING_DATA_VLD: u1,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// rtc_cali_value
+            RTC_CALI_VALUE: u25,
+        }), base_address + 0x6c);
+
+        /// address: 0x60020070
+        /// INT_ENA_TIMG_REG
+        pub const INT_ENA_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_ena
+            T0_INT_ENA: u1,
+            /// wdt_int_ena
+            WDT_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60020074
+        /// INT_RAW_TIMG_REG
+        pub const INT_RAW_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_raw
+            T0_INT_RAW: u1,
+            /// wdt_int_raw
+            WDT_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60020078
+        /// INT_ST_TIMG_REG
+        pub const INT_ST_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_st
+            T0_INT_ST: u1,
+            /// wdt_int_st
+            WDT_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6002007c
+        /// INT_CLR_TIMG_REG
+        pub const INT_CLR_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// t0_int_clr
+            T0_INT_CLR: u1,
+            /// wdt_int_clr
+            WDT_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x60020080
+        /// TIMG_RTCCALICFG2_REG.
+        pub const RTCCALICFG2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// timeoutindicator
+            RTC_CALI_TIMEOUT: u1,
+            reserved0: u1,
+            reserved1: u1,
+            /// reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
+            RTC_CALI_TIMEOUT_RST_CNT: u4,
+            /// reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
+            RTC_CALI_TIMEOUT_THRES: u25,
+        }), base_address + 0x80);
+
+        /// address: 0x600200f8
+        /// TIMG_NTIMG_DATE_REG.
+        pub const NTIMG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// reg_ntimers_date.
+            NTIMGS_DATE: u28,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0xf8);
+
+        /// address: 0x600200fc
+        /// TIMG_REGCLK_REG.
+        pub const REGCLK = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            reserved8: u1,
+            reserved9: u1,
+            reserved10: u1,
+            reserved11: u1,
+            reserved12: u1,
+            reserved13: u1,
+            reserved14: u1,
+            reserved15: u1,
+            reserved16: u1,
+            reserved17: u1,
+            reserved18: u1,
+            reserved19: u1,
+            reserved20: u1,
+            reserved21: u1,
+            reserved22: u1,
+            reserved23: u1,
+            reserved24: u1,
+            reserved25: u1,
+            reserved26: u1,
+            reserved27: u1,
+            reserved28: u1,
+            /// reg_wdt_clk_is_active.
+            WDT_CLK_IS_ACTIVE: u1,
+            /// reg_timer_clk_is_active.
+            TIMER_CLK_IS_ACTIVE: u1,
+            /// reg_clk_en.
+            CLK_EN: u1,
+        }), base_address + 0xfc);
+    };
+
+    /// Two-Wire Automotive Interface
+    pub const TWAI = struct {
+        pub const base_address = 0x6002b000;
+
+        /// address: 0x6002b000
+        /// Mode Register
+        pub const MODE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This bit is used to configure the operating mode of the TWAI Controller. 1:
+            /// Reset mode; 0: Operating mode.
+            RESET_MODE: u1,
+            /// 1: Listen only mode. In this mode the nodes will only receive messages from the
+            /// bus, without generating the acknowledge signal nor updating the RX error
+            /// counter.
+            LISTEN_ONLY_MODE: u1,
+            /// 1: Self test mode. In this mode the TX nodes can perform a successful
+            /// transmission without receiving the acknowledge signal. This mode is often used
+            /// to test a single node with the self reception request command.
+            SELF_TEST_MODE: u1,
+            /// This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single
+            /// filter mode.
+            RX_FILTER_MODE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x6002b004
+        /// Command Register
+        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set the bit to 1 to allow the driving nodes start transmission.
+            TX_REQ: u1,
+            /// Set the bit to 1 to cancel a pending transmission request.
+            ABORT_TX: u1,
+            /// Set the bit to 1 to release the RX buffer.
+            RELEASE_BUF: u1,
+            /// Set the bit to 1 to clear the data overrun status bit.
+            CLR_OVERRUN: u1,
+            /// Self reception request command. Set the bit to 1 to allow a message be
+            /// transmitted and received simultaneously.
+            SELF_RX_REQ: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x6002b008
+        /// Status register
+        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: The data in the RX buffer is not empty, with at least one received data
+            /// packet.
+            RX_BUF_ST: u1,
+            /// 1: The RX FIFO is full and data overrun has occurred.
+            OVERRUN_ST: u1,
+            /// 1: The TX buffer is empty, the CPU may write a message into it.
+            TX_BUF_ST: u1,
+            /// 1: The TWAI controller has successfully received a packet from the bus.
+            TX_COMPLETE: u1,
+            /// 1: The TWAI Controller is receiving a message from the bus.
+            RX_ST: u1,
+            /// 1: The TWAI Controller is transmitting a message to the bus.
+            TX_ST: u1,
+            /// 1: At least one of the RX/TX error counter has reached or exceeded the value set
+            /// in register TWAI_ERR_WARNING_LIMIT_REG.
+            ERR_ST: u1,
+            /// 1: In bus-off status, the TWAI Controller is no longer involved in bus
+            /// activities.
+            BUS_OFF_ST: u1,
+            /// This bit reflects whether the data packet in the RX FIFO is complete. 1: The
+            /// current packet is missing; 0: The current packet is complete
+            MISS_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6002b00c
+        /// Interrupt Register
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Receive interrupt. If this bit is set to 1, it indicates there are messages to
+            /// be handled in the RX FIFO.
+            RX_INT_ST: u1,
+            /// Transmit interrupt. If this bit is set to 1, it indicates the message
+            /// transmitting mis- sion is finished and a new transmission is able to execute.
+            TX_INT_ST: u1,
+            /// Error warning interrupt. If this bit is set to 1, it indicates the error status
+            /// signal and the bus-off status signal of Status register have changed (e.g.,
+            /// switched from 0 to 1 or from 1 to 0).
+            ERR_WARN_INT_ST: u1,
+            /// Data overrun interrupt. If this bit is set to 1, it indicates a data overrun
+            /// interrupt is generated in the RX FIFO.
+            OVERRUN_INT_ST: u1,
+            reserved0: u1,
+            /// Error passive interrupt. If this bit is set to 1, it indicates the TWAI
+            /// Controller is switched between error active status and error passive status due
+            /// to the change of error counters.
+            ERR_PASSIVE_INT_ST: u1,
+            /// Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration
+            /// lost interrupt is generated.
+            ARB_LOST_INT_ST: u1,
+            /// Error interrupt. If this bit is set to 1, it indicates an error is detected on
+            /// the bus.
+            BUS_ERR_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x6002b010
+        /// Interrupt Enable Register
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to 1 to enable receive interrupt.
+            RX_INT_ENA: u1,
+            /// Set this bit to 1 to enable transmit interrupt.
+            TX_INT_ENA: u1,
+            /// Set this bit to 1 to enable error warning interrupt.
+            ERR_WARN_INT_ENA: u1,
+            /// Set this bit to 1 to enable data overrun interrupt.
+            OVERRUN_INT_ENA: u1,
+            reserved0: u1,
+            /// Set this bit to 1 to enable error passive interrupt.
+            ERR_PASSIVE_INT_ENA: u1,
+            /// Set this bit to 1 to enable arbitration lost interrupt.
+            ARB_LOST_INT_ENA: u1,
+            /// Set this bit to 1 to enable error interrupt.
+            BUS_ERR_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x6002b018
+        /// Bus Timing Register 0
+        pub const BUS_TIMING_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Baud Rate Prescaler, determines the frequency dividing ratio.
+            BAUD_PRESC: u13,
+            reserved0: u1,
+            /// Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.
+            SYNC_JUMP_WIDTH: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6002b01c
+        /// Bus Timing Register 1
+        pub const BUS_TIMING_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The width of PBS1.
+            TIME_SEG1: u4,
+            /// The width of PBS2.
+            TIME_SEG2: u3,
+            /// The number of sample points. 0: the bus is sampled once; 1: the bus is sampled
+            /// three times
+            TIME_SAMP: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x6002b02c
+        /// Arbitration Lost Capture Register
+        pub const ARB_LOST_CAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x2c);
+
+        /// address: 0x6002b030
+        /// Error Code Capture Register
+        pub const ERR_CODE_CAP = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register contains information about the location of errors, see Table 181
+            /// for details.
+            ECC_SEGMENT: u5,
+            /// This register contains information about transmission direction of the node when
+            /// error occurs. 1: Error occurs when receiving a message; 0: Error occurs when
+            /// transmitting a message
+            ECC_DIRECTION: u1,
+            /// This register contains information about error types: 00: bit error; 01: form
+            /// error; 10: stuff error; 11: other type of error
+            ECC_TYPE: u2,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x6002b034
+        /// Error Warning Limit Register
+        pub const ERR_WARNING_LIMIT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x34);
+
+        /// address: 0x6002b038
+        /// Receive Error Counter Register
+        pub const RX_ERR_CNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x38);
+
+        /// address: 0x6002b03c
+        /// Transmit Error Counter Register
+        pub const TX_ERR_CNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x3c);
+
+        /// address: 0x6002b040
+        /// Data register 0
+        pub const DATA_0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance code register 0 with R/W Permission. In
+            /// operation mode, it stores the 0th byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_0: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x6002b044
+        /// Data register 1
+        pub const DATA_1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance code register 1 with R/W Permission. In
+            /// operation mode, it stores the 1st byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x6002b048
+        /// Data register 2
+        pub const DATA_2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance code register 2 with R/W Permission. In
+            /// operation mode, it stores the 2nd byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_2: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6002b04c
+        /// Data register 3
+        pub const DATA_3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance code register 3 with R/W Permission. In
+            /// operation mode, it stores the 3rd byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_3: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x6002b050
+        /// Data register 4
+        pub const DATA_4 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance mask register 0 with R/W Permission. In
+            /// operation mode, it stores the 4th byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_4: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x6002b054
+        /// Data register 5
+        pub const DATA_5 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance mask register 1 with R/W Permission. In
+            /// operation mode, it stores the 5th byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_5: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x6002b058
+        /// Data register 6
+        pub const DATA_6 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance mask register 2 with R/W Permission. In
+            /// operation mode, it stores the 6th byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_6: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6002b05c
+        /// Data register 7
+        pub const DATA_7 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// In reset mode, it is acceptance mask register 3 with R/W Permission. In
+            /// operation mode, it stores the 7th byte information of the data to be transmitted
+            /// under operating mode.
+            TX_BYTE_7: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x6002b060
+        /// Data register 8
+        pub const DATA_8 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stored the 8th byte information of the data to be transmitted under operating
+            /// mode.
+            TX_BYTE_8: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x6002b064
+        /// Data register 9
+        pub const DATA_9 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stored the 9th byte information of the data to be transmitted under operating
+            /// mode.
+            TX_BYTE_9: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x6002b068
+        /// Data register 10
+        pub const DATA_10 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stored the 10th byte information of the data to be transmitted under operating
+            /// mode.
+            TX_BYTE_10: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6002b06c
+        /// Data register 11
+        pub const DATA_11 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stored the 11th byte information of the data to be transmitted under operating
+            /// mode.
+            TX_BYTE_11: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x6002b070
+        /// Data register 12
+        pub const DATA_12 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stored the 12th byte information of the data to be transmitted under operating
+            /// mode.
+            TX_BYTE_12: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x6002b074
+        /// Receive Message Counter Register
+        pub const RX_MESSAGE_CNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register reflects the number of messages available within the RX FIFO.
+            RX_MESSAGE_COUNTER: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x6002b07c
+        /// Clock Divider register
+        pub const CLOCK_DIVIDER = @intToPtr(*volatile Mmio(32, packed struct {
+            /// These bits are used to configure frequency dividing coefficients of the external
+            /// CLKOUT pin.
+            CD: u8,
+            /// This bit can be configured under reset mode. 1: Disable the external CLKOUT pin;
+            /// 0: Enable the external CLKOUT pin
+            CLOCK_OFF: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x7c);
+    };
+
+    /// UART (Universal Asynchronous Receiver-Transmitter) Controller
+    pub const UART0 = struct {
+        pub const base_address = 0x60000000;
+
+        /// address: 0x60000000
+        /// FIFO data register
+        pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// UART 0 accesses FIFO via this register.
+            RXFIFO_RD_BYTE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60000004
+        /// Raw interrupt status
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This interrupt raw bit turns to high level when receiver receives more data than
+            /// what rxfifo_full_thrhd specifies.
+            RXFIFO_FULL_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+            /// less than what txfifo_empty_thrhd specifies .
+            TXFIFO_EMPTY_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a parity error
+            /// in the data.
+            PARITY_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a data frame
+            /// error .
+            FRM_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver receives more data than
+            /// the FIFO can store.
+            RXFIFO_OVF_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the edge change
+            /// of DSRn signal.
+            DSR_CHG_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the edge change
+            /// of CTSn signal.
+            CTS_CHG_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a 0 after the
+            /// stop bit.
+            BRK_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver takes more time than
+            /// rx_tout_thrhd to receive a byte.
+            RXFIFO_TOUT_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver recevies Xon char when
+            /// uart_sw_flow_con_en is set to 1.
+            SW_XON_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver receives Xoff char when
+            /// uart_sw_flow_con_en is set to 1.
+            SW_XOFF_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a glitch in the
+            /// middle of a start bit.
+            GLITCH_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter completes sending
+            /// NULL characters, after all data in Tx-FIFO are sent.
+            TX_BRK_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter has kept the
+            /// shortest duration after sending the last data.
+            TX_BRK_IDLE_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter has send out all
+            /// data in FIFO.
+            TX_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a parity error
+            /// from the echo of transmitter in rs485 mode.
+            RS485_PARITY_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a data frame
+            /// error from the echo of transmitter in rs485 mode.
+            RS485_FRM_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when detects a clash between
+            /// transmitter and receiver in rs485 mode.
+            RS485_CLASH_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the configured
+            /// at_cmd char.
+            AT_CMD_CHAR_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when input rxd edge changes more
+            /// times than what reg_active_threshold specifies in light sleeping mode.
+            WAKEUP_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60000008
+        /// Masked interrupt status
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set
+            /// to 1.
+            RXFIFO_FULL_INT_ST: u1,
+            /// This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set
+            /// to 1.
+            TXFIFO_EMPTY_INT_ST: u1,
+            /// This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
+            /// 1.
+            PARITY_ERR_INT_ST: u1,
+            /// This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+            FRM_ERR_INT_ST: u1,
+            /// This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
+            /// 1.
+            RXFIFO_OVF_INT_ST: u1,
+            /// This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+            DSR_CHG_INT_ST: u1,
+            /// This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+            CTS_CHG_INT_ST: u1,
+            /// This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+            BRK_DET_INT_ST: u1,
+            /// This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set
+            /// to 1.
+            RXFIFO_TOUT_INT_ST: u1,
+            /// This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+            SW_XON_INT_ST: u1,
+            /// This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+            SW_XOFF_INT_ST: u1,
+            /// This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
+            /// 1.
+            GLITCH_DET_INT_ST: u1,
+            /// This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set
+            /// to 1.
+            TX_BRK_DONE_INT_ST: u1,
+            /// This is the stauts bit for tx_brk_idle_done_int_raw when
+            /// tx_brk_idle_done_int_ena is set to 1.
+            TX_BRK_IDLE_DONE_INT_ST: u1,
+            /// This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+            TX_DONE_INT_ST: u1,
+            /// This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+            /// set to 1.
+            RS485_PARITY_ERR_INT_ST: u1,
+            /// This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is
+            /// set to 1.
+            RS485_FRM_ERR_INT_ST: u1,
+            /// This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set
+            /// to 1.
+            RS485_CLASH_INT_ST: u1,
+            /// This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is
+            /// set to 1.
+            AT_CMD_CHAR_DET_INT_ST: u1,
+            /// This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set
+            /// to 1.
+            WAKEUP_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000000c
+        /// Interrupt enable bits
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the enable bit for rxfifo_full_int_st register.
+            RXFIFO_FULL_INT_ENA: u1,
+            /// This is the enable bit for txfifo_empty_int_st register.
+            TXFIFO_EMPTY_INT_ENA: u1,
+            /// This is the enable bit for parity_err_int_st register.
+            PARITY_ERR_INT_ENA: u1,
+            /// This is the enable bit for frm_err_int_st register.
+            FRM_ERR_INT_ENA: u1,
+            /// This is the enable bit for rxfifo_ovf_int_st register.
+            RXFIFO_OVF_INT_ENA: u1,
+            /// This is the enable bit for dsr_chg_int_st register.
+            DSR_CHG_INT_ENA: u1,
+            /// This is the enable bit for cts_chg_int_st register.
+            CTS_CHG_INT_ENA: u1,
+            /// This is the enable bit for brk_det_int_st register.
+            BRK_DET_INT_ENA: u1,
+            /// This is the enable bit for rxfifo_tout_int_st register.
+            RXFIFO_TOUT_INT_ENA: u1,
+            /// This is the enable bit for sw_xon_int_st register.
+            SW_XON_INT_ENA: u1,
+            /// This is the enable bit for sw_xoff_int_st register.
+            SW_XOFF_INT_ENA: u1,
+            /// This is the enable bit for glitch_det_int_st register.
+            GLITCH_DET_INT_ENA: u1,
+            /// This is the enable bit for tx_brk_done_int_st register.
+            TX_BRK_DONE_INT_ENA: u1,
+            /// This is the enable bit for tx_brk_idle_done_int_st register.
+            TX_BRK_IDLE_DONE_INT_ENA: u1,
+            /// This is the enable bit for tx_done_int_st register.
+            TX_DONE_INT_ENA: u1,
+            /// This is the enable bit for rs485_parity_err_int_st register.
+            RS485_PARITY_ERR_INT_ENA: u1,
+            /// This is the enable bit for rs485_parity_err_int_st register.
+            RS485_FRM_ERR_INT_ENA: u1,
+            /// This is the enable bit for rs485_clash_int_st register.
+            RS485_CLASH_INT_ENA: u1,
+            /// This is the enable bit for at_cmd_char_det_int_st register.
+            AT_CMD_CHAR_DET_INT_ENA: u1,
+            /// This is the enable bit for uart_wakeup_int_st register.
+            WAKEUP_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60000010
+        /// Interrupt clear bits
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the rxfifo_full_int_raw interrupt.
+            RXFIFO_FULL_INT_CLR: u1,
+            /// Set this bit to clear txfifo_empty_int_raw interrupt.
+            TXFIFO_EMPTY_INT_CLR: u1,
+            /// Set this bit to clear parity_err_int_raw interrupt.
+            PARITY_ERR_INT_CLR: u1,
+            /// Set this bit to clear frm_err_int_raw interrupt.
+            FRM_ERR_INT_CLR: u1,
+            /// Set this bit to clear rxfifo_ovf_int_raw interrupt.
+            RXFIFO_OVF_INT_CLR: u1,
+            /// Set this bit to clear the dsr_chg_int_raw interrupt.
+            DSR_CHG_INT_CLR: u1,
+            /// Set this bit to clear the cts_chg_int_raw interrupt.
+            CTS_CHG_INT_CLR: u1,
+            /// Set this bit to clear the brk_det_int_raw interrupt.
+            BRK_DET_INT_CLR: u1,
+            /// Set this bit to clear the rxfifo_tout_int_raw interrupt.
+            RXFIFO_TOUT_INT_CLR: u1,
+            /// Set this bit to clear the sw_xon_int_raw interrupt.
+            SW_XON_INT_CLR: u1,
+            /// Set this bit to clear the sw_xoff_int_raw interrupt.
+            SW_XOFF_INT_CLR: u1,
+            /// Set this bit to clear the glitch_det_int_raw interrupt.
+            GLITCH_DET_INT_CLR: u1,
+            /// Set this bit to clear the tx_brk_done_int_raw interrupt..
+            TX_BRK_DONE_INT_CLR: u1,
+            /// Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+            TX_BRK_IDLE_DONE_INT_CLR: u1,
+            /// Set this bit to clear the tx_done_int_raw interrupt.
+            TX_DONE_INT_CLR: u1,
+            /// Set this bit to clear the rs485_parity_err_int_raw interrupt.
+            RS485_PARITY_ERR_INT_CLR: u1,
+            /// Set this bit to clear the rs485_frm_err_int_raw interrupt.
+            RS485_FRM_ERR_INT_CLR: u1,
+            /// Set this bit to clear the rs485_clash_int_raw interrupt.
+            RS485_CLASH_INT_CLR: u1,
+            /// Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+            AT_CMD_CHAR_DET_INT_CLR: u1,
+            /// Set this bit to clear the uart_wakeup_int_raw interrupt.
+            WAKEUP_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60000014
+        /// Clock divider configuration
+        pub const CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The integral part of the frequency divider factor.
+            CLKDIV: u12,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// The decimal part of the frequency divider factor.
+            FRAG: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60000018
+        /// Rx Filter configuration
+        pub const RX_FILT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// when input pulse width is lower than this value, the pulse is ignored.
+            GLITCH_FILT: u8,
+            /// Set this bit to enable Rx signal filter.
+            GLITCH_FILT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000001c
+        /// UART status register
+        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the byte number of valid data in Rx-FIFO.
+            RXFIFO_CNT: u10,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The register represent the level value of the internal uart dsr signal.
+            DSRN: u1,
+            /// This register represent the level value of the internal uart cts signal.
+            CTSN: u1,
+            /// This register represent the level value of the internal uart rxd signal.
+            RXD: u1,
+            /// Stores the byte number of data in Tx-FIFO.
+            TXFIFO_CNT: u10,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// This bit represents the level of the internal uart dtr signal.
+            DTRN: u1,
+            /// This bit represents the level of the internal uart rts signal.
+            RTSN: u1,
+            /// This bit represents the level of the internal uart txd signal.
+            TXD: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60000020
+        /// a
+        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the parity check mode.
+            PARITY: u1,
+            /// Set this bit to enable uart parity check.
+            PARITY_EN: u1,
+            /// This register is used to set the length of data.
+            BIT_NUM: u2,
+            /// This register is used to set the length of stop bit.
+            STOP_BIT_NUM: u2,
+            /// This register is used to configure the software rts signal which is used in
+            /// software flow control.
+            SW_RTS: u1,
+            /// This register is used to configure the software dtr signal which is used in
+            /// software flow control.
+            SW_DTR: u1,
+            /// Set this bit to enbale transmitter to send NULL when the process of sending data
+            /// is done.
+            TXD_BRK: u1,
+            /// Set this bit to enable IrDA loopback mode.
+            IRDA_DPLX: u1,
+            /// This is the start enable bit for IrDA transmitter.
+            IRDA_TX_EN: u1,
+            /// 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+            /// transmitter's 11th bit to 0.
+            IRDA_WCTL: u1,
+            /// Set this bit to invert the level of IrDA transmitter.
+            IRDA_TX_INV: u1,
+            /// Set this bit to invert the level of IrDA receiver.
+            IRDA_RX_INV: u1,
+            /// Set this bit to enable uart loopback test mode.
+            LOOPBACK: u1,
+            /// Set this bit to enable flow control function for transmitter.
+            TX_FLOW_EN: u1,
+            /// Set this bit to enable IrDA protocol.
+            IRDA_EN: u1,
+            /// Set this bit to reset the uart receive-FIFO.
+            RXFIFO_RST: u1,
+            /// Set this bit to reset the uart transmit-FIFO.
+            TXFIFO_RST: u1,
+            /// Set this bit to inverse the level value of uart rxd signal.
+            RXD_INV: u1,
+            /// Set this bit to inverse the level value of uart cts signal.
+            CTS_INV: u1,
+            /// Set this bit to inverse the level value of uart dsr signal.
+            DSR_INV: u1,
+            /// Set this bit to inverse the level value of uart txd signal.
+            TXD_INV: u1,
+            /// Set this bit to inverse the level value of uart rts signal.
+            RTS_INV: u1,
+            /// Set this bit to inverse the level value of uart dtr signal.
+            DTR_INV: u1,
+            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
+            /// writes registers.
+            CLK_EN: u1,
+            /// 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+            /// stores the data even if the received data is wrong.
+            ERR_WR_MASK: u1,
+            /// This is the enable bit for detecting baudrate.
+            AUTOBAUD_EN: u1,
+            /// UART memory clock gate enable signal.
+            MEM_CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60000024
+        /// Configuration register 1
+        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// It will produce rxfifo_full_int interrupt when receiver receives more data than
+            /// this register value.
+            RXFIFO_FULL_THRHD: u9,
+            /// It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is
+            /// less than this register value.
+            TXFIFO_EMPTY_THRHD: u9,
+            /// Disable UART Rx data overflow detect.
+            DIS_RX_DAT_OVF: u1,
+            /// Set this bit to stop accumulating idle_cnt when hardware flow control works.
+            RX_TOUT_FLOW_DIS: u1,
+            /// This is the flow enable bit for UART receiver.
+            RX_FLOW_EN: u1,
+            /// This is the enble bit for uart receiver's timeout function.
+            RX_TOUT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60000028
+        /// Autobaud minimum low pulse duration register
+        pub const LOWPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the value of the minimum duration time of the low level
+            /// pulse. It is used in baud rate-detect process.
+            MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6000002c
+        /// Autobaud minimum high pulse duration register
+        pub const HIGHPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the value of the maxinum duration time for the high level
+            /// pulse. It is used in baud rate-detect process.
+            MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60000030
+        /// Autobaud edge change count register
+        pub const RXD_CNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the count of rxd edge change. It is used in baud
+            /// rate-detect process.
+            RXD_EDGE_CNT: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60000034
+        /// Software flow-control configuration
+        pub const FLOW_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to enable software flow control. It is used with register sw_xon or
+            /// sw_xoff.
+            SW_FLOW_CON_EN: u1,
+            /// Set this bit to remove flow control char from the received data.
+            XONOFF_DEL: u1,
+            /// Set this bit to enable the transmitter to go on sending data.
+            FORCE_XON: u1,
+            /// Set this bit to stop the transmitter from sending data.
+            FORCE_XOFF: u1,
+            /// Set this bit to send Xon char. It is cleared by hardware automatically.
+            SEND_XON: u1,
+            /// Set this bit to send Xoff char. It is cleared by hardware automatically.
+            SEND_XOFF: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60000038
+        /// Sleep-mode configuration
+        pub const SLEEP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The uart is activated from light sleeping mode when the input rxd edge changes
+            /// more times than this register value.
+            ACTIVE_THRESHOLD: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6000003c
+        /// Software flow-control character configuration
+        pub const SWFC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// When the data amount in Rx-FIFO is more than this register value with
+            /// uart_sw_flow_con_en set to 1, it will send a Xoff char.
+            XOFF_THRESHOLD: u9,
+            /// This register stores the Xoff flow control char.
+            XOFF_CHAR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60000040
+        /// Software flow-control character configuration
+        pub const SWFC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// When the data amount in Rx-FIFO is less than this register value with
+            /// uart_sw_flow_con_en set to 1, it will send a Xon char.
+            XON_THRESHOLD: u9,
+            /// This register stores the Xon flow control char.
+            XON_CHAR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60000044
+        /// Tx Break character configuration
+        pub const TXBRK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the number of 0 to be sent after the process
+            /// of sending data is done. It is active when txd_brk is set to 1.
+            TX_BRK_NUM: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60000048
+        /// Frame-end idle configuration
+        pub const IDLE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// It will produce frame end signal when receiver takes more time to receive one
+            /// byte data than this register value.
+            RX_IDLE_THRHD: u10,
+            /// This register is used to configure the duration time between transfers.
+            TX_IDLE_NUM: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6000004c
+        /// RS485 mode configuration
+        pub const RS485_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to choose the rs485 mode.
+            RS485_EN: u1,
+            /// Set this bit to delay the stop bit by 1 bit.
+            DL0_EN: u1,
+            /// Set this bit to delay the stop bit by 1 bit.
+            DL1_EN: u1,
+            /// Set this bit to enable receiver could receive data when the transmitter is
+            /// transmitting data in rs485 mode.
+            RS485TX_RX_EN: u1,
+            /// 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+            RS485RXBY_TX_EN: u1,
+            /// This register is used to delay the receiver's internal data signal.
+            RS485_RX_DLY_NUM: u1,
+            /// This register is used to delay the transmitter's internal data signal.
+            RS485_TX_DLY_NUM: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60000050
+        /// Pre-sequence timing configuration
+        pub const AT_CMD_PRECNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the idle duration time before the first
+            /// at_cmd is received by receiver.
+            PRE_IDLE_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60000054
+        /// Post-sequence timing configuration
+        pub const AT_CMD_POSTCNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the duration time between the last at_cmd and
+            /// the next data.
+            POST_IDLE_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60000058
+        /// Timeout configuration
+        pub const AT_CMD_GAPTOUT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the duration time between the at_cmd chars.
+            RX_GAP_TOUT: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6000005c
+        /// AT escape sequence detection configuration
+        pub const AT_CMD_CHAR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the content of at_cmd char.
+            AT_CMD_CHAR: u8,
+            /// This register is used to configure the num of continuous at_cmd chars received
+            /// by receiver.
+            CHAR_NUM: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60000060
+        /// UART threshold and allocation configuration
+        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// This register is used to configure the amount of mem allocated for receive-FIFO.
+            /// The default number is 128 bytes.
+            RX_SIZE: u3,
+            /// This register is used to configure the amount of mem allocated for
+            /// transmit-FIFO. The default number is 128 bytes.
+            TX_SIZE: u3,
+            /// This register is used to configure the maximum amount of data that can be
+            /// received when hardware flow control works.
+            RX_FLOW_THRHD: u9,
+            /// This register is used to configure the threshold time that receiver takes to
+            /// receive one byte. The rxfifo_tout_int interrupt will be trigger when the
+            /// receiver takes more time to receive one byte with rx_tout_en set to 1.
+            RX_TOUT_THRHD: u10,
+            /// Set this bit to force power down UART memory.
+            MEM_FORCE_PD: u1,
+            /// Set this bit to force power up UART memory.
+            MEM_FORCE_PU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60000064
+        /// Tx-FIFO write and read offset address.
+        pub const MEM_TX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
+            /// via APB.
+            APB_TX_WADDR: u10,
+            reserved0: u1,
+            /// This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
+            /// Tx-FIFO_Ctrl.
+            TX_RADDR: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60000068
+        /// Rx-FIFO write and read offset address.
+        pub const MEM_RX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the offset address in RX-FIFO when software reads data from
+            /// Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
+            APB_RX_RADDR: u10,
+            reserved0: u1,
+            /// This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
+            /// Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
+            RX_WADDR: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6000006c
+        /// UART transmit and receive status.
+        pub const FSM_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the status register of receiver.
+            ST_URX_OUT: u4,
+            /// This is the status register of transmitter.
+            ST_UTX_OUT: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60000070
+        /// Autobaud high pulse register
+        pub const POSPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the minimal input clock count between two positive edges.
+            /// It is used in boudrate-detect process.
+            POSEDGE_MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60000074
+        /// Autobaud low pulse register
+        pub const NEGPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the minimal input clock count between two negative edges.
+            /// It is used in boudrate-detect process.
+            NEGEDGE_MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60000078
+        /// UART core clock configuration
+        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The denominator of the frequency divider factor.
+            SCLK_DIV_B: u6,
+            /// The numerator of the frequency divider factor.
+            SCLK_DIV_A: u6,
+            /// The integral part of the frequency divider factor.
+            SCLK_DIV_NUM: u8,
+            /// UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+            SCLK_SEL: u2,
+            /// Set this bit to enable UART Tx/Rx clock.
+            SCLK_EN: u1,
+            /// Write 1 then write 0 to this bit, reset UART Tx/Rx.
+            RST_CORE: u1,
+            /// Set this bit to enable UART Tx clock.
+            TX_SCLK_EN: u1,
+            /// Set this bit to enable UART Rx clock.
+            RX_SCLK_EN: u1,
+            /// Write 1 then write 0 to this bit, reset UART Tx.
+            TX_RST_CORE: u1,
+            /// Write 1 then write 0 to this bit, reset UART Rx.
+            RX_RST_CORE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6000007c
+        /// UART Version register
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x7c);
+
+        /// address: 0x60000080
+        /// UART ID register
+        pub const ID = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the uart_id.
+            ID: u30,
+            /// This bit used to select synchronize mode. 1: Registers are auto synchronized
+            /// into UART Core clock and UART core should be keep the same with APB clock. 0:
+            /// After configure registers, software needs to write 1 to UART_REG_UPDATE to
+            /// synchronize registers.
+            HIGH_SPEED: u1,
+            /// Software write 1 would synchronize registers into UART Core clock domain and
+            /// would be cleared by hardware after synchronization is done.
+            REG_UPDATE: u1,
+        }), base_address + 0x80);
+    };
+
+    /// UART (Universal Asynchronous Receiver-Transmitter) Controller
+    pub const UART1 = struct {
+        pub const base_address = 0x60010000;
+
+        /// address: 0x60010000
+        /// FIFO data register
+        pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct {
+            /// UART 0 accesses FIFO via this register.
+            RXFIFO_RD_BYTE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60010004
+        /// Raw interrupt status
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This interrupt raw bit turns to high level when receiver receives more data than
+            /// what rxfifo_full_thrhd specifies.
+            RXFIFO_FULL_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
+            /// less than what txfifo_empty_thrhd specifies .
+            TXFIFO_EMPTY_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a parity error
+            /// in the data.
+            PARITY_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a data frame
+            /// error .
+            FRM_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver receives more data than
+            /// the FIFO can store.
+            RXFIFO_OVF_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the edge change
+            /// of DSRn signal.
+            DSR_CHG_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the edge change
+            /// of CTSn signal.
+            CTS_CHG_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a 0 after the
+            /// stop bit.
+            BRK_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver takes more time than
+            /// rx_tout_thrhd to receive a byte.
+            RXFIFO_TOUT_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver recevies Xon char when
+            /// uart_sw_flow_con_en is set to 1.
+            SW_XON_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver receives Xoff char when
+            /// uart_sw_flow_con_en is set to 1.
+            SW_XOFF_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a glitch in the
+            /// middle of a start bit.
+            GLITCH_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter completes sending
+            /// NULL characters, after all data in Tx-FIFO are sent.
+            TX_BRK_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter has kept the
+            /// shortest duration after sending the last data.
+            TX_BRK_IDLE_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when transmitter has send out all
+            /// data in FIFO.
+            TX_DONE_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a parity error
+            /// from the echo of transmitter in rs485 mode.
+            RS485_PARITY_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects a data frame
+            /// error from the echo of transmitter in rs485 mode.
+            RS485_FRM_ERR_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when detects a clash between
+            /// transmitter and receiver in rs485 mode.
+            RS485_CLASH_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when receiver detects the configured
+            /// at_cmd char.
+            AT_CMD_CHAR_DET_INT_RAW: u1,
+            /// This interrupt raw bit turns to high level when input rxd edge changes more
+            /// times than what reg_active_threshold specifies in light sleeping mode.
+            WAKEUP_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60010008
+        /// Masked interrupt status
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set
+            /// to 1.
+            RXFIFO_FULL_INT_ST: u1,
+            /// This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set
+            /// to 1.
+            TXFIFO_EMPTY_INT_ST: u1,
+            /// This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
+            /// 1.
+            PARITY_ERR_INT_ST: u1,
+            /// This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+            FRM_ERR_INT_ST: u1,
+            /// This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
+            /// 1.
+            RXFIFO_OVF_INT_ST: u1,
+            /// This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+            DSR_CHG_INT_ST: u1,
+            /// This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+            CTS_CHG_INT_ST: u1,
+            /// This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+            BRK_DET_INT_ST: u1,
+            /// This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set
+            /// to 1.
+            RXFIFO_TOUT_INT_ST: u1,
+            /// This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+            SW_XON_INT_ST: u1,
+            /// This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+            SW_XOFF_INT_ST: u1,
+            /// This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
+            /// 1.
+            GLITCH_DET_INT_ST: u1,
+            /// This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set
+            /// to 1.
+            TX_BRK_DONE_INT_ST: u1,
+            /// This is the stauts bit for tx_brk_idle_done_int_raw when
+            /// tx_brk_idle_done_int_ena is set to 1.
+            TX_BRK_IDLE_DONE_INT_ST: u1,
+            /// This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+            TX_DONE_INT_ST: u1,
+            /// This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
+            /// set to 1.
+            RS485_PARITY_ERR_INT_ST: u1,
+            /// This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is
+            /// set to 1.
+            RS485_FRM_ERR_INT_ST: u1,
+            /// This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set
+            /// to 1.
+            RS485_CLASH_INT_ST: u1,
+            /// This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is
+            /// set to 1.
+            AT_CMD_CHAR_DET_INT_ST: u1,
+            /// This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set
+            /// to 1.
+            WAKEUP_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6001000c
+        /// Interrupt enable bits
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the enable bit for rxfifo_full_int_st register.
+            RXFIFO_FULL_INT_ENA: u1,
+            /// This is the enable bit for txfifo_empty_int_st register.
+            TXFIFO_EMPTY_INT_ENA: u1,
+            /// This is the enable bit for parity_err_int_st register.
+            PARITY_ERR_INT_ENA: u1,
+            /// This is the enable bit for frm_err_int_st register.
+            FRM_ERR_INT_ENA: u1,
+            /// This is the enable bit for rxfifo_ovf_int_st register.
+            RXFIFO_OVF_INT_ENA: u1,
+            /// This is the enable bit for dsr_chg_int_st register.
+            DSR_CHG_INT_ENA: u1,
+            /// This is the enable bit for cts_chg_int_st register.
+            CTS_CHG_INT_ENA: u1,
+            /// This is the enable bit for brk_det_int_st register.
+            BRK_DET_INT_ENA: u1,
+            /// This is the enable bit for rxfifo_tout_int_st register.
+            RXFIFO_TOUT_INT_ENA: u1,
+            /// This is the enable bit for sw_xon_int_st register.
+            SW_XON_INT_ENA: u1,
+            /// This is the enable bit for sw_xoff_int_st register.
+            SW_XOFF_INT_ENA: u1,
+            /// This is the enable bit for glitch_det_int_st register.
+            GLITCH_DET_INT_ENA: u1,
+            /// This is the enable bit for tx_brk_done_int_st register.
+            TX_BRK_DONE_INT_ENA: u1,
+            /// This is the enable bit for tx_brk_idle_done_int_st register.
+            TX_BRK_IDLE_DONE_INT_ENA: u1,
+            /// This is the enable bit for tx_done_int_st register.
+            TX_DONE_INT_ENA: u1,
+            /// This is the enable bit for rs485_parity_err_int_st register.
+            RS485_PARITY_ERR_INT_ENA: u1,
+            /// This is the enable bit for rs485_parity_err_int_st register.
+            RS485_FRM_ERR_INT_ENA: u1,
+            /// This is the enable bit for rs485_clash_int_st register.
+            RS485_CLASH_INT_ENA: u1,
+            /// This is the enable bit for at_cmd_char_det_int_st register.
+            AT_CMD_CHAR_DET_INT_ENA: u1,
+            /// This is the enable bit for uart_wakeup_int_st register.
+            WAKEUP_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60010010
+        /// Interrupt clear bits
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the rxfifo_full_int_raw interrupt.
+            RXFIFO_FULL_INT_CLR: u1,
+            /// Set this bit to clear txfifo_empty_int_raw interrupt.
+            TXFIFO_EMPTY_INT_CLR: u1,
+            /// Set this bit to clear parity_err_int_raw interrupt.
+            PARITY_ERR_INT_CLR: u1,
+            /// Set this bit to clear frm_err_int_raw interrupt.
+            FRM_ERR_INT_CLR: u1,
+            /// Set this bit to clear rxfifo_ovf_int_raw interrupt.
+            RXFIFO_OVF_INT_CLR: u1,
+            /// Set this bit to clear the dsr_chg_int_raw interrupt.
+            DSR_CHG_INT_CLR: u1,
+            /// Set this bit to clear the cts_chg_int_raw interrupt.
+            CTS_CHG_INT_CLR: u1,
+            /// Set this bit to clear the brk_det_int_raw interrupt.
+            BRK_DET_INT_CLR: u1,
+            /// Set this bit to clear the rxfifo_tout_int_raw interrupt.
+            RXFIFO_TOUT_INT_CLR: u1,
+            /// Set this bit to clear the sw_xon_int_raw interrupt.
+            SW_XON_INT_CLR: u1,
+            /// Set this bit to clear the sw_xoff_int_raw interrupt.
+            SW_XOFF_INT_CLR: u1,
+            /// Set this bit to clear the glitch_det_int_raw interrupt.
+            GLITCH_DET_INT_CLR: u1,
+            /// Set this bit to clear the tx_brk_done_int_raw interrupt..
+            TX_BRK_DONE_INT_CLR: u1,
+            /// Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+            TX_BRK_IDLE_DONE_INT_CLR: u1,
+            /// Set this bit to clear the tx_done_int_raw interrupt.
+            TX_DONE_INT_CLR: u1,
+            /// Set this bit to clear the rs485_parity_err_int_raw interrupt.
+            RS485_PARITY_ERR_INT_CLR: u1,
+            /// Set this bit to clear the rs485_frm_err_int_raw interrupt.
+            RS485_FRM_ERR_INT_CLR: u1,
+            /// Set this bit to clear the rs485_clash_int_raw interrupt.
+            RS485_CLASH_INT_CLR: u1,
+            /// Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+            AT_CMD_CHAR_DET_INT_CLR: u1,
+            /// Set this bit to clear the uart_wakeup_int_raw interrupt.
+            WAKEUP_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60010014
+        /// Clock divider configuration
+        pub const CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The integral part of the frequency divider factor.
+            CLKDIV: u12,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            reserved6: u1,
+            reserved7: u1,
+            /// The decimal part of the frequency divider factor.
+            FRAG: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60010018
+        /// Rx Filter configuration
+        pub const RX_FILT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// when input pulse width is lower than this value, the pulse is ignored.
+            GLITCH_FILT: u8,
+            /// Set this bit to enable Rx signal filter.
+            GLITCH_FILT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6001001c
+        /// UART status register
+        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Stores the byte number of valid data in Rx-FIFO.
+            RXFIFO_CNT: u10,
+            reserved0: u1,
+            reserved1: u1,
+            reserved2: u1,
+            /// The register represent the level value of the internal uart dsr signal.
+            DSRN: u1,
+            /// This register represent the level value of the internal uart cts signal.
+            CTSN: u1,
+            /// This register represent the level value of the internal uart rxd signal.
+            RXD: u1,
+            /// Stores the byte number of data in Tx-FIFO.
+            TXFIFO_CNT: u10,
+            reserved3: u1,
+            reserved4: u1,
+            reserved5: u1,
+            /// This bit represents the level of the internal uart dtr signal.
+            DTRN: u1,
+            /// This bit represents the level of the internal uart rts signal.
+            RTSN: u1,
+            /// This bit represents the level of the internal uart txd signal.
+            TXD: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60010020
+        /// a
+        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the parity check mode.
+            PARITY: u1,
+            /// Set this bit to enable uart parity check.
+            PARITY_EN: u1,
+            /// This register is used to set the length of data.
+            BIT_NUM: u2,
+            /// This register is used to set the length of stop bit.
+            STOP_BIT_NUM: u2,
+            /// This register is used to configure the software rts signal which is used in
+            /// software flow control.
+            SW_RTS: u1,
+            /// This register is used to configure the software dtr signal which is used in
+            /// software flow control.
+            SW_DTR: u1,
+            /// Set this bit to enbale transmitter to send NULL when the process of sending data
+            /// is done.
+            TXD_BRK: u1,
+            /// Set this bit to enable IrDA loopback mode.
+            IRDA_DPLX: u1,
+            /// This is the start enable bit for IrDA transmitter.
+            IRDA_TX_EN: u1,
+            /// 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
+            /// transmitter's 11th bit to 0.
+            IRDA_WCTL: u1,
+            /// Set this bit to invert the level of IrDA transmitter.
+            IRDA_TX_INV: u1,
+            /// Set this bit to invert the level of IrDA receiver.
+            IRDA_RX_INV: u1,
+            /// Set this bit to enable uart loopback test mode.
+            LOOPBACK: u1,
+            /// Set this bit to enable flow control function for transmitter.
+            TX_FLOW_EN: u1,
+            /// Set this bit to enable IrDA protocol.
+            IRDA_EN: u1,
+            /// Set this bit to reset the uart receive-FIFO.
+            RXFIFO_RST: u1,
+            /// Set this bit to reset the uart transmit-FIFO.
+            TXFIFO_RST: u1,
+            /// Set this bit to inverse the level value of uart rxd signal.
+            RXD_INV: u1,
+            /// Set this bit to inverse the level value of uart cts signal.
+            CTS_INV: u1,
+            /// Set this bit to inverse the level value of uart dsr signal.
+            DSR_INV: u1,
+            /// Set this bit to inverse the level value of uart txd signal.
+            TXD_INV: u1,
+            /// Set this bit to inverse the level value of uart rts signal.
+            RTS_INV: u1,
+            /// Set this bit to inverse the level value of uart dtr signal.
+            DTR_INV: u1,
+            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
+            /// writes registers.
+            CLK_EN: u1,
+            /// 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
+            /// stores the data even if the received data is wrong.
+            ERR_WR_MASK: u1,
+            /// This is the enable bit for detecting baudrate.
+            AUTOBAUD_EN: u1,
+            /// UART memory clock gate enable signal.
+            MEM_CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60010024
+        /// Configuration register 1
+        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// It will produce rxfifo_full_int interrupt when receiver receives more data than
+            /// this register value.
+            RXFIFO_FULL_THRHD: u9,
+            /// It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is
+            /// less than this register value.
+            TXFIFO_EMPTY_THRHD: u9,
+            /// Disable UART Rx data overflow detect.
+            DIS_RX_DAT_OVF: u1,
+            /// Set this bit to stop accumulating idle_cnt when hardware flow control works.
+            RX_TOUT_FLOW_DIS: u1,
+            /// This is the flow enable bit for UART receiver.
+            RX_FLOW_EN: u1,
+            /// This is the enble bit for uart receiver's timeout function.
+            RX_TOUT_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60010028
+        /// Autobaud minimum low pulse duration register
+        pub const LOWPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the value of the minimum duration time of the low level
+            /// pulse. It is used in baud rate-detect process.
+            MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6001002c
+        /// Autobaud minimum high pulse duration register
+        pub const HIGHPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the value of the maxinum duration time for the high level
+            /// pulse. It is used in baud rate-detect process.
+            MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60010030
+        /// Autobaud edge change count register
+        pub const RXD_CNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the count of rxd edge change. It is used in baud
+            /// rate-detect process.
+            RXD_EDGE_CNT: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60010034
+        /// Software flow-control configuration
+        pub const FLOW_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to enable software flow control. It is used with register sw_xon or
+            /// sw_xoff.
+            SW_FLOW_CON_EN: u1,
+            /// Set this bit to remove flow control char from the received data.
+            XONOFF_DEL: u1,
+            /// Set this bit to enable the transmitter to go on sending data.
+            FORCE_XON: u1,
+            /// Set this bit to stop the transmitter from sending data.
+            FORCE_XOFF: u1,
+            /// Set this bit to send Xon char. It is cleared by hardware automatically.
+            SEND_XON: u1,
+            /// Set this bit to send Xoff char. It is cleared by hardware automatically.
+            SEND_XOFF: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60010038
+        /// Sleep-mode configuration
+        pub const SLEEP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The uart is activated from light sleeping mode when the input rxd edge changes
+            /// more times than this register value.
+            ACTIVE_THRESHOLD: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6001003c
+        /// Software flow-control character configuration
+        pub const SWFC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// When the data amount in Rx-FIFO is more than this register value with
+            /// uart_sw_flow_con_en set to 1, it will send a Xoff char.
+            XOFF_THRESHOLD: u9,
+            /// This register stores the Xoff flow control char.
+            XOFF_CHAR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60010040
+        /// Software flow-control character configuration
+        pub const SWFC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// When the data amount in Rx-FIFO is less than this register value with
+            /// uart_sw_flow_con_en set to 1, it will send a Xon char.
+            XON_THRESHOLD: u9,
+            /// This register stores the Xon flow control char.
+            XON_CHAR: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60010044
+        /// Tx Break character configuration
+        pub const TXBRK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the number of 0 to be sent after the process
+            /// of sending data is done. It is active when txd_brk is set to 1.
+            TX_BRK_NUM: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60010048
+        /// Frame-end idle configuration
+        pub const IDLE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// It will produce frame end signal when receiver takes more time to receive one
+            /// byte data than this register value.
+            RX_IDLE_THRHD: u10,
+            /// This register is used to configure the duration time between transfers.
+            TX_IDLE_NUM: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x6001004c
+        /// RS485 mode configuration
+        pub const RS485_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to choose the rs485 mode.
+            RS485_EN: u1,
+            /// Set this bit to delay the stop bit by 1 bit.
+            DL0_EN: u1,
+            /// Set this bit to delay the stop bit by 1 bit.
+            DL1_EN: u1,
+            /// Set this bit to enable receiver could receive data when the transmitter is
+            /// transmitting data in rs485 mode.
+            RS485TX_RX_EN: u1,
+            /// 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+            RS485RXBY_TX_EN: u1,
+            /// This register is used to delay the receiver's internal data signal.
+            RS485_RX_DLY_NUM: u1,
+            /// This register is used to delay the transmitter's internal data signal.
+            RS485_TX_DLY_NUM: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x4c);
+
+        /// address: 0x60010050
+        /// Pre-sequence timing configuration
+        pub const AT_CMD_PRECNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the idle duration time before the first
+            /// at_cmd is received by receiver.
+            PRE_IDLE_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x50);
+
+        /// address: 0x60010054
+        /// Post-sequence timing configuration
+        pub const AT_CMD_POSTCNT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the duration time between the last at_cmd and
+            /// the next data.
+            POST_IDLE_NUM: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x54);
+
+        /// address: 0x60010058
+        /// Timeout configuration
+        pub const AT_CMD_GAPTOUT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the duration time between the at_cmd chars.
+            RX_GAP_TOUT: u16,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x58);
+
+        /// address: 0x6001005c
+        /// AT escape sequence detection configuration
+        pub const AT_CMD_CHAR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the content of at_cmd char.
+            AT_CMD_CHAR: u8,
+            /// This register is used to configure the num of continuous at_cmd chars received
+            /// by receiver.
+            CHAR_NUM: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x5c);
+
+        /// address: 0x60010060
+        /// UART threshold and allocation configuration
+        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            reserved0: u1,
+            /// This register is used to configure the amount of mem allocated for receive-FIFO.
+            /// The default number is 128 bytes.
+            RX_SIZE: u3,
+            /// This register is used to configure the amount of mem allocated for
+            /// transmit-FIFO. The default number is 128 bytes.
+            TX_SIZE: u3,
+            /// This register is used to configure the maximum amount of data that can be
+            /// received when hardware flow control works.
+            RX_FLOW_THRHD: u9,
+            /// This register is used to configure the threshold time that receiver takes to
+            /// receive one byte. The rxfifo_tout_int interrupt will be trigger when the
+            /// receiver takes more time to receive one byte with rx_tout_en set to 1.
+            RX_TOUT_THRHD: u10,
+            /// Set this bit to force power down UART memory.
+            MEM_FORCE_PD: u1,
+            /// Set this bit to force power up UART memory.
+            MEM_FORCE_PU: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x60);
+
+        /// address: 0x60010064
+        /// Tx-FIFO write and read offset address.
+        pub const MEM_TX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
+            /// via APB.
+            APB_TX_WADDR: u10,
+            reserved0: u1,
+            /// This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
+            /// Tx-FIFO_Ctrl.
+            TX_RADDR: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x64);
+
+        /// address: 0x60010068
+        /// Rx-FIFO write and read offset address.
+        pub const MEM_RX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the offset address in RX-FIFO when software reads data from
+            /// Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
+            APB_RX_RADDR: u10,
+            reserved0: u1,
+            /// This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
+            /// Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
+            RX_WADDR: u10,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+        }), base_address + 0x68);
+
+        /// address: 0x6001006c
+        /// UART transmit and receive status.
+        pub const FSM_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This is the status register of receiver.
+            ST_URX_OUT: u4,
+            /// This is the status register of transmitter.
+            ST_UTX_OUT: u4,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60010070
+        /// Autobaud high pulse register
+        pub const POSPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the minimal input clock count between two positive edges.
+            /// It is used in boudrate-detect process.
+            POSEDGE_MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60010074
+        /// Autobaud low pulse register
+        pub const NEGPULSE = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register stores the minimal input clock count between two negative edges.
+            /// It is used in boudrate-detect process.
+            NEGEDGE_MIN_CNT: u12,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60010078
+        /// UART core clock configuration
+        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The denominator of the frequency divider factor.
+            SCLK_DIV_B: u6,
+            /// The numerator of the frequency divider factor.
+            SCLK_DIV_A: u6,
+            /// The integral part of the frequency divider factor.
+            SCLK_DIV_NUM: u8,
+            /// UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+            SCLK_SEL: u2,
+            /// Set this bit to enable UART Tx/Rx clock.
+            SCLK_EN: u1,
+            /// Write 1 then write 0 to this bit, reset UART Tx/Rx.
+            RST_CORE: u1,
+            /// Set this bit to enable UART Tx clock.
+            TX_SCLK_EN: u1,
+            /// Set this bit to enable UART Rx clock.
+            RX_SCLK_EN: u1,
+            /// Write 1 then write 0 to this bit, reset UART Tx.
+            TX_RST_CORE: u1,
+            /// Write 1 then write 0 to this bit, reset UART Rx.
+            RX_RST_CORE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6001007c
+        /// UART Version register
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x7c);
+
+        /// address: 0x60010080
+        /// UART ID register
+        pub const ID = @intToPtr(*volatile Mmio(32, packed struct {
+            /// This register is used to configure the uart_id.
+            ID: u30,
+            /// This bit used to select synchronize mode. 1: Registers are auto synchronized
+            /// into UART Core clock and UART core should be keep the same with APB clock. 0:
+            /// After configure registers, software needs to write 1 to UART_REG_UPDATE to
+            /// synchronize registers.
+            HIGH_SPEED: u1,
+            /// Software write 1 would synchronize registers into UART Core clock domain and
+            /// would be cleared by hardware after synchronization is done.
+            REG_UPDATE: u1,
+        }), base_address + 0x80);
+    };
+
+    /// Universal Host Controller Interface
+    pub const UHCI0 = struct {
+        pub const base_address = 0x60014000;
+
+        /// address: 0x60014000
+        /// a
+        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Write 1, then write 0 to this bit to reset decode state machine.
+            TX_RST: u1,
+            /// Write 1, then write 0 to this bit to reset encode state machine.
+            RX_RST: u1,
+            /// Set this bit to link up HCI and UART0.
+            UART0_CE: u1,
+            /// Set this bit to link up HCI and UART1.
+            UART1_CE: u1,
+            reserved0: u1,
+            /// Set this bit to separate the data frame using a special char.
+            SEPER_EN: u1,
+            /// Set this bit to encode the data packet with a formatting header.
+            HEAD_EN: u1,
+            /// Set this bit to enable UHCI to receive the 16 bit CRC.
+            CRC_REC_EN: u1,
+            /// If this bit is set to 1, UHCI will end the payload receiving process when UART
+            /// has been in idle state.
+            UART_IDLE_EOF_EN: u1,
+            /// If this bit is set to 1, UHCI decoder receiving payload data is end when the
+            /// receiving byte count has reached the specified value. The value is payload
+            /// length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
+            /// configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI
+            /// decoder receiving payload data is end when 0xc0 is received.
+            LEN_EOF_EN: u1,
+            /// Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC
+            /// to end of the payload.
+            ENCODE_CRC_EN: u1,
+            /// 1'b1: Force clock on for register. 1'b0: Support clock only when application
+            /// writes registers.
+            CLK_EN: u1,
+            /// If this bit is set to 1, UHCI will end payload receive process when NULL frame
+            /// is received by UART.
+            UART_RX_BRK_EOF_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60014004
+        /// a
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_RAW: u1,
+            /// a
+            TX_START_INT_RAW: u1,
+            /// a
+            RX_HUNG_INT_RAW: u1,
+            /// a
+            TX_HUNG_INT_RAW: u1,
+            /// a
+            SEND_S_REG_Q_INT_RAW: u1,
+            /// a
+            SEND_A_REG_Q_INT_RAW: u1,
+            /// This is the interrupt raw bit. Triggered when there are some errors in EOF in
+            /// the
+            OUT_EOF_INT_RAW: u1,
+            /// Soft control int raw bit.
+            APP_CTRL0_INT_RAW: u1,
+            /// Soft control int raw bit.
+            APP_CTRL1_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60014008
+        /// a
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_ST: u1,
+            /// a
+            TX_START_INT_ST: u1,
+            /// a
+            RX_HUNG_INT_ST: u1,
+            /// a
+            TX_HUNG_INT_ST: u1,
+            /// a
+            SEND_S_REG_Q_INT_ST: u1,
+            /// a
+            SEND_A_REG_Q_INT_ST: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_ST: u1,
+            /// a
+            APP_CTRL0_INT_ST: u1,
+            /// a
+            APP_CTRL1_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6001400c
+        /// a
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_ENA: u1,
+            /// a
+            TX_START_INT_ENA: u1,
+            /// a
+            RX_HUNG_INT_ENA: u1,
+            /// a
+            TX_HUNG_INT_ENA: u1,
+            /// a
+            SEND_S_REG_Q_INT_ENA: u1,
+            /// a
+            SEND_A_REG_Q_INT_ENA: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_ENA: u1,
+            /// a
+            APP_CTRL0_INT_ENA: u1,
+            /// a
+            APP_CTRL1_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60014010
+        /// a
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_CLR: u1,
+            /// a
+            TX_START_INT_CLR: u1,
+            /// a
+            RX_HUNG_INT_CLR: u1,
+            /// a
+            TX_HUNG_INT_CLR: u1,
+            /// a
+            SEND_S_REG_Q_INT_CLR: u1,
+            /// a
+            SEND_A_REG_Q_INT_CLR: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_CLR: u1,
+            /// a
+            APP_CTRL0_INT_CLR: u1,
+            /// a
+            APP_CTRL1_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60014014
+        /// a
+        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            CHECK_SUM_EN: u1,
+            /// a
+            CHECK_SEQ_EN: u1,
+            /// a
+            CRC_DISABLE: u1,
+            /// a
+            SAVE_HEAD: u1,
+            /// a
+            TX_CHECK_SUM_RE: u1,
+            /// a
+            TX_ACK_NUM_RE: u1,
+            reserved0: u1,
+            /// a
+            WAIT_SW_START: u1,
+            /// a
+            SW_START: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60014018
+        /// a
+        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_ERR_CAUSE: u3,
+            /// a
+            DECODE_STATE: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6001401c
+        /// a
+        pub const STATE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ENCODE_STATE: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60014020
+        /// a
+        pub const ESCAPE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            TX_C0_ESC_EN: u1,
+            /// a
+            TX_DB_ESC_EN: u1,
+            /// a
+            TX_11_ESC_EN: u1,
+            /// a
+            TX_13_ESC_EN: u1,
+            /// a
+            RX_C0_ESC_EN: u1,
+            /// a
+            RX_DB_ESC_EN: u1,
+            /// a
+            RX_11_ESC_EN: u1,
+            /// a
+            RX_13_ESC_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60014024
+        /// a
+        pub const HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            TXFIFO_TIMEOUT: u8,
+            /// a
+            TXFIFO_TIMEOUT_SHIFT: u3,
+            /// a
+            TXFIFO_TIMEOUT_ENA: u1,
+            /// a
+            RXFIFO_TIMEOUT: u8,
+            /// a
+            RXFIFO_TIMEOUT_SHIFT: u3,
+            /// a
+            RXFIFO_TIMEOUT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60014028
+        /// a
+        pub const ACK_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ACK_NUM: u3,
+            /// a
+            LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6001402c
+        /// a
+        pub const RX_HEAD = @intToPtr(*volatile u32, base_address + 0x2c);
+
+        /// address: 0x60014030
+        /// a
+        pub const QUICK_SENT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SINGLE_SEND_NUM: u3,
+            /// a
+            SINGLE_SEND_EN: u1,
+            /// a
+            ALWAYS_SEND_NUM: u3,
+            /// a
+            ALWAYS_SEND_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60014034
+        /// a
+        pub const REG_Q0_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q0_WORD0: u32,
+        }), base_address + 0x34);
+
+        /// address: 0x60014038
+        /// a
+        pub const REG_Q0_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q0_WORD1: u32,
+        }), base_address + 0x38);
+
+        /// address: 0x6001403c
+        /// a
+        pub const REG_Q1_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q1_WORD0: u32,
+        }), base_address + 0x3c);
+
+        /// address: 0x60014040
+        /// a
+        pub const REG_Q1_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q1_WORD1: u32,
+        }), base_address + 0x40);
+
+        /// address: 0x60014044
+        /// a
+        pub const REG_Q2_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q2_WORD0: u32,
+        }), base_address + 0x44);
+
+        /// address: 0x60014048
+        /// a
+        pub const REG_Q2_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q2_WORD1: u32,
+        }), base_address + 0x48);
+
+        /// address: 0x6001404c
+        /// a
+        pub const REG_Q3_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q3_WORD0: u32,
+        }), base_address + 0x4c);
+
+        /// address: 0x60014050
+        /// a
+        pub const REG_Q3_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q3_WORD1: u32,
+        }), base_address + 0x50);
+
+        /// address: 0x60014054
+        /// a
+        pub const REG_Q4_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q4_WORD0: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x60014058
+        /// a
+        pub const REG_Q4_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q4_WORD1: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6001405c
+        /// a
+        pub const REG_Q5_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q5_WORD0: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x60014060
+        /// a
+        pub const REG_Q5_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q5_WORD1: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x60014064
+        /// a
+        pub const REG_Q6_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q6_WORD0: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x60014068
+        /// a
+        pub const REG_Q6_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q6_WORD1: u32,
+        }), base_address + 0x68);
+
+        /// address: 0x6001406c
+        /// a
+        pub const ESC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEPER_CHAR: u8,
+            /// a
+            SEPER_ESC_CHAR0: u8,
+            /// a
+            SEPER_ESC_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x60014070
+        /// a
+        pub const ESC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ0: u8,
+            /// a
+            ESC_SEQ0_CHAR0: u8,
+            /// a
+            ESC_SEQ0_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x60014074
+        /// a
+        pub const ESC_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ1: u8,
+            /// a
+            ESC_SEQ1_CHAR0: u8,
+            /// a
+            ESC_SEQ1_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x60014078
+        /// a
+        pub const ESC_CONF3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ2: u8,
+            /// a
+            ESC_SEQ2_CHAR0: u8,
+            /// a
+            ESC_SEQ2_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6001407c
+        /// a
+        pub const PKT_THRES = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            PKT_THRS: u13,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x60014080
+        /// a
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
+    };
+
+    /// Universal Host Controller Interface
+    pub const UHCI1 = struct {
+        pub const base_address = 0x6000c000;
+
+        /// address: 0x6000c000
+        /// a
+        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Write 1, then write 0 to this bit to reset decode state machine.
+            TX_RST: u1,
+            /// Write 1, then write 0 to this bit to reset encode state machine.
+            RX_RST: u1,
+            /// Set this bit to link up HCI and UART0.
+            UART0_CE: u1,
+            /// Set this bit to link up HCI and UART1.
+            UART1_CE: u1,
+            reserved0: u1,
+            /// Set this bit to separate the data frame using a special char.
+            SEPER_EN: u1,
+            /// Set this bit to encode the data packet with a formatting header.
+            HEAD_EN: u1,
+            /// Set this bit to enable UHCI to receive the 16 bit CRC.
+            CRC_REC_EN: u1,
+            /// If this bit is set to 1, UHCI will end the payload receiving process when UART
+            /// has been in idle state.
+            UART_IDLE_EOF_EN: u1,
+            /// If this bit is set to 1, UHCI decoder receiving payload data is end when the
+            /// receiving byte count has reached the specified value. The value is payload
+            /// length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
+            /// configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI
+            /// decoder receiving payload data is end when 0xc0 is received.
+            LEN_EOF_EN: u1,
+            /// Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC
+            /// to end of the payload.
+            ENCODE_CRC_EN: u1,
+            /// 1'b1: Force clock on for register. 1'b0: Support clock only when application
+            /// writes registers.
+            CLK_EN: u1,
+            /// If this bit is set to 1, UHCI will end payload receive process when NULL frame
+            /// is received by UART.
+            UART_RX_BRK_EOF_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x6000c004
+        /// a
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_RAW: u1,
+            /// a
+            TX_START_INT_RAW: u1,
+            /// a
+            RX_HUNG_INT_RAW: u1,
+            /// a
+            TX_HUNG_INT_RAW: u1,
+            /// a
+            SEND_S_REG_Q_INT_RAW: u1,
+            /// a
+            SEND_A_REG_Q_INT_RAW: u1,
+            /// This is the interrupt raw bit. Triggered when there are some errors in EOF in
+            /// the
+            OUT_EOF_INT_RAW: u1,
+            /// Soft control int raw bit.
+            APP_CTRL0_INT_RAW: u1,
+            /// Soft control int raw bit.
+            APP_CTRL1_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x6000c008
+        /// a
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_ST: u1,
+            /// a
+            TX_START_INT_ST: u1,
+            /// a
+            RX_HUNG_INT_ST: u1,
+            /// a
+            TX_HUNG_INT_ST: u1,
+            /// a
+            SEND_S_REG_Q_INT_ST: u1,
+            /// a
+            SEND_A_REG_Q_INT_ST: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_ST: u1,
+            /// a
+            APP_CTRL0_INT_ST: u1,
+            /// a
+            APP_CTRL1_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6000c00c
+        /// a
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_ENA: u1,
+            /// a
+            TX_START_INT_ENA: u1,
+            /// a
+            RX_HUNG_INT_ENA: u1,
+            /// a
+            TX_HUNG_INT_ENA: u1,
+            /// a
+            SEND_S_REG_Q_INT_ENA: u1,
+            /// a
+            SEND_A_REG_Q_INT_ENA: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_ENA: u1,
+            /// a
+            APP_CTRL0_INT_ENA: u1,
+            /// a
+            APP_CTRL1_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x6000c010
+        /// a
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_START_INT_CLR: u1,
+            /// a
+            TX_START_INT_CLR: u1,
+            /// a
+            RX_HUNG_INT_CLR: u1,
+            /// a
+            TX_HUNG_INT_CLR: u1,
+            /// a
+            SEND_S_REG_Q_INT_CLR: u1,
+            /// a
+            SEND_A_REG_Q_INT_CLR: u1,
+            /// a
+            OUTLINK_EOF_ERR_INT_CLR: u1,
+            /// a
+            APP_CTRL0_INT_CLR: u1,
+            /// a
+            APP_CTRL1_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x6000c014
+        /// a
+        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            CHECK_SUM_EN: u1,
+            /// a
+            CHECK_SEQ_EN: u1,
+            /// a
+            CRC_DISABLE: u1,
+            /// a
+            SAVE_HEAD: u1,
+            /// a
+            TX_CHECK_SUM_RE: u1,
+            /// a
+            TX_ACK_NUM_RE: u1,
+            reserved0: u1,
+            /// a
+            WAIT_SW_START: u1,
+            /// a
+            SW_START: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x6000c018
+        /// a
+        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            RX_ERR_CAUSE: u3,
+            /// a
+            DECODE_STATE: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6000c01c
+        /// a
+        pub const STATE1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ENCODE_STATE: u3,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x6000c020
+        /// a
+        pub const ESCAPE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            TX_C0_ESC_EN: u1,
+            /// a
+            TX_DB_ESC_EN: u1,
+            /// a
+            TX_11_ESC_EN: u1,
+            /// a
+            TX_13_ESC_EN: u1,
+            /// a
+            RX_C0_ESC_EN: u1,
+            /// a
+            RX_DB_ESC_EN: u1,
+            /// a
+            RX_11_ESC_EN: u1,
+            /// a
+            RX_13_ESC_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x6000c024
+        /// a
+        pub const HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            TXFIFO_TIMEOUT: u8,
+            /// a
+            TXFIFO_TIMEOUT_SHIFT: u3,
+            /// a
+            TXFIFO_TIMEOUT_ENA: u1,
+            /// a
+            RXFIFO_TIMEOUT: u8,
+            /// a
+            RXFIFO_TIMEOUT_SHIFT: u3,
+            /// a
+            RXFIFO_TIMEOUT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x6000c028
+        /// a
+        pub const ACK_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ACK_NUM: u3,
+            /// a
+            LOAD: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6000c02c
+        /// a
+        pub const RX_HEAD = @intToPtr(*volatile u32, base_address + 0x2c);
+
+        /// address: 0x6000c030
+        /// a
+        pub const QUICK_SENT = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SINGLE_SEND_NUM: u3,
+            /// a
+            SINGLE_SEND_EN: u1,
+            /// a
+            ALWAYS_SEND_NUM: u3,
+            /// a
+            ALWAYS_SEND_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x6000c034
+        /// a
+        pub const REG_Q0_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q0_WORD0: u32,
+        }), base_address + 0x34);
+
+        /// address: 0x6000c038
+        /// a
+        pub const REG_Q0_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q0_WORD1: u32,
+        }), base_address + 0x38);
+
+        /// address: 0x6000c03c
+        /// a
+        pub const REG_Q1_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q1_WORD0: u32,
+        }), base_address + 0x3c);
+
+        /// address: 0x6000c040
+        /// a
+        pub const REG_Q1_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q1_WORD1: u32,
+        }), base_address + 0x40);
+
+        /// address: 0x6000c044
+        /// a
+        pub const REG_Q2_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q2_WORD0: u32,
+        }), base_address + 0x44);
+
+        /// address: 0x6000c048
+        /// a
+        pub const REG_Q2_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q2_WORD1: u32,
+        }), base_address + 0x48);
+
+        /// address: 0x6000c04c
+        /// a
+        pub const REG_Q3_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q3_WORD0: u32,
+        }), base_address + 0x4c);
+
+        /// address: 0x6000c050
+        /// a
+        pub const REG_Q3_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q3_WORD1: u32,
+        }), base_address + 0x50);
+
+        /// address: 0x6000c054
+        /// a
+        pub const REG_Q4_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q4_WORD0: u32,
+        }), base_address + 0x54);
+
+        /// address: 0x6000c058
+        /// a
+        pub const REG_Q4_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q4_WORD1: u32,
+        }), base_address + 0x58);
+
+        /// address: 0x6000c05c
+        /// a
+        pub const REG_Q5_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q5_WORD0: u32,
+        }), base_address + 0x5c);
+
+        /// address: 0x6000c060
+        /// a
+        pub const REG_Q5_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q5_WORD1: u32,
+        }), base_address + 0x60);
+
+        /// address: 0x6000c064
+        /// a
+        pub const REG_Q6_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q6_WORD0: u32,
+        }), base_address + 0x64);
+
+        /// address: 0x6000c068
+        /// a
+        pub const REG_Q6_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEND_Q6_WORD1: u32,
+        }), base_address + 0x68);
+
+        /// address: 0x6000c06c
+        /// a
+        pub const ESC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            SEPER_CHAR: u8,
+            /// a
+            SEPER_ESC_CHAR0: u8,
+            /// a
+            SEPER_ESC_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x6c);
+
+        /// address: 0x6000c070
+        /// a
+        pub const ESC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ0: u8,
+            /// a
+            ESC_SEQ0_CHAR0: u8,
+            /// a
+            ESC_SEQ0_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x70);
+
+        /// address: 0x6000c074
+        /// a
+        pub const ESC_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ1: u8,
+            /// a
+            ESC_SEQ1_CHAR0: u8,
+            /// a
+            ESC_SEQ1_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x74);
+
+        /// address: 0x6000c078
+        /// a
+        pub const ESC_CONF3 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            ESC_SEQ2: u8,
+            /// a
+            ESC_SEQ2_CHAR0: u8,
+            /// a
+            ESC_SEQ2_CHAR1: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+        }), base_address + 0x78);
+
+        /// address: 0x6000c07c
+        /// a
+        pub const PKT_THRES = @intToPtr(*volatile Mmio(32, packed struct {
+            /// a
+            PKT_THRS: u13,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+        }), base_address + 0x7c);
+
+        /// address: 0x6000c080
+        /// a
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
+    };
+
+    /// Full-speed USB Serial/JTAG Controller
+    pub const USB_DEVICE = struct {
+        pub const base_address = 0x60043000;
+
+        /// address: 0x60043000
+        /// USB_DEVICE_EP1_REG.
+        pub const EP1 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Write and read byte data to/from UART Tx/Rx FIFO through this field. When
+            /// USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
+            /// into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can
+            /// check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many
+            /// data is received, then read data from UART Rx FIFO.
+            RDWR_BYTE: u8,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+        }), base_address + 0x0);
+
+        /// address: 0x60043004
+        /// USB_DEVICE_EP1_CONF_REG.
+        pub const EP1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to indicate writing byte data to UART Tx FIFO is done.
+            WR_DONE: u1,
+            /// 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After
+            /// writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is
+            /// read by USB Host.
+            SERIAL_IN_EP_DATA_FREE: u1,
+            /// 1'b1: Indicate there is data in UART Rx FIFO.
+            SERIAL_OUT_EP_DATA_AVAIL: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+        }), base_address + 0x4);
+
+        /// address: 0x60043008
+        /// USB_DEVICE_INT_RAW_REG.
+        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt bit turns to high level when flush cmd is received for IN
+            /// endpoint 2 of JTAG.
+            JTAG_IN_FLUSH_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when SOF frame is received.
+            SOF_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
+            /// one packet.
+            SERIAL_OUT_RECV_PKT_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+            SERIAL_IN_EMPTY_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when pid error is detected.
+            PID_ERR_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when CRC5 error is detected.
+            CRC5_ERR_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when CRC16 error is detected.
+            CRC16_ERR_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when stuff error is detected.
+            STUFF_ERR_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
+            /// received.
+            IN_TOKEN_REC_IN_EP1_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when usb bus reset is detected.
+            USB_BUS_RESET_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when OUT endpoint 1 received packet
+            /// with zero palyload.
+            OUT_EP1_ZERO_PAYLOAD_INT_RAW: u1,
+            /// The raw interrupt bit turns to high level when OUT endpoint 2 received packet
+            /// with zero palyload.
+            OUT_EP2_ZERO_PAYLOAD_INT_RAW: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x8);
+
+        /// address: 0x6004300c
+        /// USB_DEVICE_INT_ST_REG.
+        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+            JTAG_IN_FLUSH_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+            SOF_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT
+            /// interrupt.
+            SERIAL_OUT_RECV_PKT_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+            SERIAL_IN_EMPTY_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+            PID_ERR_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+            CRC5_ERR_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+            CRC16_ERR_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+            STUFF_ERR_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT
+            /// interrupt.
+            IN_TOKEN_REC_IN_EP1_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+            USB_BUS_RESET_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT
+            /// interrupt.
+            OUT_EP1_ZERO_PAYLOAD_INT_ST: u1,
+            /// The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT
+            /// interrupt.
+            OUT_EP2_ZERO_PAYLOAD_INT_ST: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0xc);
+
+        /// address: 0x60043010
+        /// USB_DEVICE_INT_ENA_REG.
+        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
+            /// The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+            JTAG_IN_FLUSH_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+            SOF_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+            SERIAL_OUT_RECV_PKT_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+            SERIAL_IN_EMPTY_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+            PID_ERR_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+            CRC5_ERR_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+            CRC16_ERR_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+            STUFF_ERR_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+            IN_TOKEN_REC_IN_EP1_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+            USB_BUS_RESET_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+            OUT_EP1_ZERO_PAYLOAD_INT_ENA: u1,
+            /// The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+            OUT_EP2_ZERO_PAYLOAD_INT_ENA: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x10);
+
+        /// address: 0x60043014
+        /// USB_DEVICE_INT_CLR_REG.
+        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+            JTAG_IN_FLUSH_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+            SOF_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+            SERIAL_OUT_RECV_PKT_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+            SERIAL_IN_EMPTY_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+            PID_ERR_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+            CRC5_ERR_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+            CRC16_ERR_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+            STUFF_ERR_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+            IN_TOKEN_REC_IN_EP1_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+            USB_BUS_RESET_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+            OUT_EP1_ZERO_PAYLOAD_INT_CLR: u1,
+            /// Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+            OUT_EP2_ZERO_PAYLOAD_INT_CLR: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+        }), base_address + 0x14);
+
+        /// address: 0x60043018
+        /// USB_DEVICE_CONF0_REG.
+        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Select internal/external PHY
+            PHY_SEL: u1,
+            /// Enable software control USB D+ D- exchange
+            EXCHG_PINS_OVERRIDE: u1,
+            /// USB D+ D- exchange
+            EXCHG_PINS: u1,
+            /// Control single-end input high threshold,1.76V to 2V, step 80mV
+            VREFH: u2,
+            /// Control single-end input low threshold,0.8V to 1.04V, step 80mV
+            VREFL: u2,
+            /// Enable software control input threshold
+            VREF_OVERRIDE: u1,
+            /// Enable software control USB D+ D- pullup pulldown
+            PAD_PULL_OVERRIDE: u1,
+            /// Control USB D+ pull up.
+            DP_PULLUP: u1,
+            /// Control USB D+ pull down.
+            DP_PULLDOWN: u1,
+            /// Control USB D- pull up.
+            DM_PULLUP: u1,
+            /// Control USB D- pull down.
+            DM_PULLDOWN: u1,
+            /// Control pull up value.
+            PULLUP_VALUE: u1,
+            /// Enable USB pad function.
+            USB_PAD_ENABLE: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+        }), base_address + 0x18);
+
+        /// address: 0x6004301c
+        /// USB_DEVICE_TEST_REG.
+        pub const TEST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Enable test of the USB pad
+            ENABLE: u1,
+            /// USB pad oen in test
+            USB_OE: u1,
+            /// USB D+ tx value in test
+            TX_DP: u1,
+            /// USB D- tx value in test
+            TX_DM: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+        }), base_address + 0x1c);
+
+        /// address: 0x60043020
+        /// USB_DEVICE_JFIFO_ST_REG.
+        pub const JFIFO_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// JTAT in fifo counter.
+            IN_FIFO_CNT: u2,
+            /// 1: JTAG in fifo is empty.
+            IN_FIFO_EMPTY: u1,
+            /// 1: JTAG in fifo is full.
+            IN_FIFO_FULL: u1,
+            /// JTAT out fifo counter.
+            OUT_FIFO_CNT: u2,
+            /// 1: JTAG out fifo is empty.
+            OUT_FIFO_EMPTY: u1,
+            /// 1: JTAG out fifo is full.
+            OUT_FIFO_FULL: u1,
+            /// Write 1 to reset JTAG in fifo.
+            IN_FIFO_RESET: u1,
+            /// Write 1 to reset JTAG out fifo.
+            OUT_FIFO_RESET: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+        }), base_address + 0x20);
+
+        /// address: 0x60043024
+        /// USB_DEVICE_FRAM_NUM_REG.
+        pub const FRAM_NUM = @intToPtr(*volatile Mmio(32, packed struct {
+            /// Frame index of received SOF frame.
+            SOF_FRAME_INDEX: u11,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+        }), base_address + 0x24);
+
+        /// address: 0x60043028
+        /// USB_DEVICE_IN_EP0_ST_REG.
+        pub const IN_EP0_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of IN Endpoint 0.
+            IN_EP0_STATE: u2,
+            /// Write data address of IN endpoint 0.
+            IN_EP0_WR_ADDR: u7,
+            /// Read data address of IN endpoint 0.
+            IN_EP0_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x28);
+
+        /// address: 0x6004302c
+        /// USB_DEVICE_IN_EP1_ST_REG.
+        pub const IN_EP1_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of IN Endpoint 1.
+            IN_EP1_STATE: u2,
+            /// Write data address of IN endpoint 1.
+            IN_EP1_WR_ADDR: u7,
+            /// Read data address of IN endpoint 1.
+            IN_EP1_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x2c);
+
+        /// address: 0x60043030
+        /// USB_DEVICE_IN_EP2_ST_REG.
+        pub const IN_EP2_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of IN Endpoint 2.
+            IN_EP2_STATE: u2,
+            /// Write data address of IN endpoint 2.
+            IN_EP2_WR_ADDR: u7,
+            /// Read data address of IN endpoint 2.
+            IN_EP2_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x30);
+
+        /// address: 0x60043034
+        /// USB_DEVICE_IN_EP3_ST_REG.
+        pub const IN_EP3_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of IN Endpoint 3.
+            IN_EP3_STATE: u2,
+            /// Write data address of IN endpoint 3.
+            IN_EP3_WR_ADDR: u7,
+            /// Read data address of IN endpoint 3.
+            IN_EP3_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x34);
+
+        /// address: 0x60043038
+        /// USB_DEVICE_OUT_EP0_ST_REG.
+        pub const OUT_EP0_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of OUT Endpoint 0.
+            OUT_EP0_STATE: u2,
+            /// Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+            /// detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+            OUT_EP0_WR_ADDR: u7,
+            /// Read data address of OUT endpoint 0.
+            OUT_EP0_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x38);
+
+        /// address: 0x6004303c
+        /// USB_DEVICE_OUT_EP1_ST_REG.
+        pub const OUT_EP1_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of OUT Endpoint 1.
+            OUT_EP1_STATE: u2,
+            /// Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+            /// detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+            OUT_EP1_WR_ADDR: u7,
+            /// Read data address of OUT endpoint 1.
+            OUT_EP1_RD_ADDR: u7,
+            /// Data count in OUT endpoint 1 when one packet is received.
+            OUT_EP1_REC_DATA_CNT: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+        }), base_address + 0x3c);
+
+        /// address: 0x60043040
+        /// USB_DEVICE_OUT_EP2_ST_REG.
+        pub const OUT_EP2_ST = @intToPtr(*volatile Mmio(32, packed struct {
+            /// State of OUT Endpoint 2.
+            OUT_EP2_STATE: u2,
+            /// Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
+            /// detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+            OUT_EP2_WR_ADDR: u7,
+            /// Read data address of OUT endpoint 2.
+            OUT_EP2_RD_ADDR: u7,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+        }), base_address + 0x40);
+
+        /// address: 0x60043044
+        /// USB_DEVICE_MISC_CONF_REG.
+        pub const MISC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
+            /// writes registers.
+            CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+            padding30: u1,
+        }), base_address + 0x44);
+
+        /// address: 0x60043048
+        /// USB_DEVICE_MEM_CONF_REG.
+        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
+            /// 1: power down usb memory.
+            USB_MEM_PD: u1,
+            /// 1: Force clock on for usb memory.
+            USB_MEM_CLK_EN: u1,
+            padding0: u1,
+            padding1: u1,
+            padding2: u1,
+            padding3: u1,
+            padding4: u1,
+            padding5: u1,
+            padding6: u1,
+            padding7: u1,
+            padding8: u1,
+            padding9: u1,
+            padding10: u1,
+            padding11: u1,
+            padding12: u1,
+            padding13: u1,
+            padding14: u1,
+            padding15: u1,
+            padding16: u1,
+            padding17: u1,
+            padding18: u1,
+            padding19: u1,
+            padding20: u1,
+            padding21: u1,
+            padding22: u1,
+            padding23: u1,
+            padding24: u1,
+            padding25: u1,
+            padding26: u1,
+            padding27: u1,
+            padding28: u1,
+            padding29: u1,
+        }), base_address + 0x48);
+
+        /// address: 0x60043080
+        /// USB_DEVICE_DATE_REG.
+        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
+    };
+
+    /// XTS-AES-128 Flash Encryption
+    pub const XTS_AES = struct {
+        pub const base_address = 0x600cc000;
+
+        /// address: 0x600cc000
+        /// The memory that stores plaintext
+        pub const PLAIN_MEM = @intToPtr(*volatile [16]u8, base_address + 0x0);
+
+        /// address: 0x600cc040
+        /// XTS-AES line-size register
+        pub const LINESIZE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x40);
+
+        /// address: 0x600cc044
+        /// XTS-AES destination register
+        pub const DESTINATION = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x44);
+
+        /// address: 0x600cc048
+        /// XTS-AES physical address register
+        pub const PHYSICAL_ADDRESS = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x48);
+
+        /// address: 0x600cc04c
+        /// XTS-AES trigger register
+        pub const TRIGGER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4c);
+
+        /// address: 0x600cc050
+        /// XTS-AES release register
+        pub const RELEASE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x50);
+
+        /// address: 0x600cc054
+        /// XTS-AES destroy register
+        pub const DESTROY = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x54);
+
+        /// address: 0x600cc058
+        /// XTS-AES status register
+        pub const STATE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x58);
+
+        /// address: 0x600cc05c
+        /// XTS-AES version control register
+        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x5c);
+    };
+};
+
+const std = @import("std");
+
+pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) {
+    return @intToPtr(*volatile Mmio(size, PackedT), addr);
+}
+
+pub fn Mmio(comptime size: u8, comptime PackedT: type) type {
+    if ((size % 8) != 0)
+        @compileError("size must be divisible by 8!");
+
+    if (!std.math.isPowerOfTwo(size / 8))
+        @compileError("size must encode a power of two number of bytes!");
+
+    const IntT = std.meta.Int(.unsigned, size);
+
+    if (@sizeOf(PackedT) != (size / 8))
+        @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) }));
+
+    return extern struct {
+        const Self = @This();
+
+        raw: IntT,
+
+        pub const underlying_type = PackedT;
+
+        pub inline fn read(addr: *volatile Self) PackedT {
+            return @bitCast(PackedT, addr.raw);
+        }
+
+        pub inline fn write(addr: *volatile Self, val: PackedT) void {
+            // This is a workaround for a compiler bug related to miscompilation
+            // If the tmp var is not used, result location will fuck things up
+            var tmp = @bitCast(IntT, val);
+            addr.raw = tmp;
+        }
+
+        pub inline fn modify(addr: *volatile Self, fields: anytype) void {
+            var val = read(addr);
+            inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
+                @field(val, field.name) = @field(fields, field.name);
+            }
+            write(addr, val);
+        }
+
+        pub inline fn toggle(addr: *volatile Self, fields: anytype) void {
+            var val = read(addr);
+            inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
+                @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?));
+            }
+            write(addr, val);
+        }
+    };
+}
+
+pub fn MmioInt(comptime size: u8, comptime T: type) type {
+    return extern struct {
+        const Self = @This();
+
+        raw: std.meta.Int(.unsigned, size),
+
+        pub inline fn read(addr: *volatile Self) T {
+            return @truncate(T, addr.raw);
+        }
+
+        pub inline fn modify(addr: *volatile Self, val: T) void {
+            const Int = std.meta.Int(.unsigned, size);
+            const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1);
+
+            var tmp = addr.raw;
+            addr.raw = (tmp & mask) | val;
+        }
+    };
+}
+
+pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) {
+    return @intToPtr(*volatile MmioInt(size, T), addr);
+}
+
+pub const InterruptVector = extern union {
+    C: fn () callconv(.C) void,
+    Naked: fn () callconv(.Naked) void,
+    // Interrupt is not supported on arm
+};
+
+const unhandled = InterruptVector{
+    .C = struct {
+        fn tmp() callconv(.C) noreturn {
+            @panic("unhandled interrupt");
+        }
+    }.tmp,
+};

From 144d557357314f25dd479e28ef1e16f157f0bb50 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 8 Oct 2022 11:41:01 +0200
Subject: [PATCH 031/286] remove hal.uart.panic

---
 src/hal/uart.zig | 13 -------------
 1 file changed, 13 deletions(-)

diff --git a/src/hal/uart.zig b/src/hal/uart.zig
index 6616452cd..d1ca4193d 100644
--- a/src/hal/uart.zig
+++ b/src/hal/uart.zig
@@ -249,16 +249,3 @@ pub fn log(
         uart.print(prefix ++ format ++ "\r\n", .{ seconds, microseconds } ++ args) catch {};
     }
 }
-
-pub fn panic(
-    message: []const u8,
-    _: ?*std.builtin.StackTrace,
-    _: ?usize,
-) noreturn {
-    if (uart_logger) |writer| {
-        writer.print("PANIC: {s}\r\n", .{message}) catch {};
-    }
-
-    @breakpoint();
-    while (true) {}
-}

From e7e70cb96c5aaae4044ea903df1ac278f7d30f14 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 8 Oct 2022 13:02:39 +0200
Subject: [PATCH 032/286] LED 1 is RED. Reset loop tho

---
 build.zig                       | 59 +++++++++++++++++++--------------
 src/example/blinky.zig          | 29 ++++++++++++++++
 src/main.zig                    | 24 --------------
 src/package/esp32-c3.zig        | 45 +++++++++++++++++++++++++
 src/package/espressif-riscv.zig | 12 +++++++
 vendor/microzig                 |  2 +-
 6 files changed, 122 insertions(+), 49 deletions(-)
 create mode 100644 src/example/blinky.zig
 delete mode 100644 src/main.zig
 create mode 100644 src/package/esp32-c3.zig
 create mode 100644 src/package/espressif-riscv.zig

diff --git a/build.zig b/build.zig
index 035b12a74..3f49cf7dd 100644
--- a/build.zig
+++ b/build.zig
@@ -1,34 +1,45 @@
 const std = @import("std");
+const microzig = @import("zpm.zig").sdks.microzig;
 
 pub fn build(b: *std.build.Builder) void {
-    // Standard target options allows the person running `zig build` to choose
-    // what target to build for. Here we do not override the defaults, which
-    // means any target is allowed, and the default is native. Other options
-    // for restricting supported target set are available.
-    const target = b.standardTargetOptions(.{});
-
-    // Standard release options allow the person running `zig build` to select
-    // between Debug, ReleaseSafe, ReleaseFast, and ReleaseSmall.
     const mode = b.standardReleaseOptions();
 
-    const exe = b.addExecutable("esp32-c3-bringup", "src/main.zig");
-    exe.setTarget(target);
-    exe.setBuildMode(mode);
-    exe.install();
+    const esp32_c3_cpu = microzig.Cpu{
+        .name = "Espressif RISC-V",
+        .path = "src/package/espressif-riscv.zig",
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .riscv32,
+            .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
+            .cpu_features_add = std.Target.riscv.featureSet(&.{
+                std.Target.riscv.Feature.c,
+                std.Target.riscv.Feature.m,
+            }),
+            .os_tag = .freestanding,
+            .abi = .eabi,
+        },
+    };
 
-    const run_cmd = exe.run();
-    run_cmd.step.dependOn(b.getInstallStep());
-    if (b.args) |args| {
-        run_cmd.addArgs(args);
-    }
+    const esp32_c3 = microzig.Chip{
+        .name = "ESP32 C3",
+        .path = "src/package/esp32-c3.zig",
+        .cpu = esp32_c3_cpu,
+        .memory_regions = &.{
+            .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
+            .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
+        },
+    };
 
-    const run_step = b.step("run", "Run the app");
-    run_step.dependOn(&run_cmd.step);
+    var exe = microzig.addEmbeddedExecutable(
+        b,
+        "esp-bringup",
+        "src/example/blinky.zig",
+        .{ .chip = esp32_c3 },
+        .{},
+    );
+    exe.setBuildMode(mode);
+    exe.install();
 
-    const exe_tests = b.addTest("src/main.zig");
-    exe_tests.setTarget(target);
-    exe_tests.setBuildMode(mode);
+    const raw_step = exe.installRaw("firmware.bin", .{});
 
-    const test_step = b.step("test", "Run unit tests");
-    test_step.dependOn(&exe_tests.step);
+    b.getInstallStep().dependOn(&raw_step.step);
 }
diff --git a/src/example/blinky.zig b/src/example/blinky.zig
new file mode 100644
index 000000000..6bba15b0b
--- /dev/null
+++ b/src/example/blinky.zig
@@ -0,0 +1,29 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+pub fn main() !void {
+    // const led_r_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_R_PIN));
+    // const led_g_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_G_PIN));
+    // const led_b_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_B_PIN));
+
+    // led_r_mux.* = 0x80;
+
+    const gpio_out = @intToPtr(*volatile u32, GPIO_BASE + GPIO_OUT_REG);
+    const gpio_ena = @intToPtr(*volatile u32, GPIO_BASE + GPIO_ENABLE_REG);
+    gpio_ena.* = (1 << LED_R_PIN) | (1 << LED_G_PIN) | (1 << LED_B_PIN);
+    gpio_out.* = (1 << LED_R_PIN) | (1 << LED_G_PIN) | (1 << LED_B_PIN);
+}
+
+const GPIO_BASE = 0x6000_4000;
+const IO_MUX_BASE = 0x6000_9000;
+
+const GPIO_OUT_REG = 0x0004;
+const GPIO_ENABLE_REG = 0x0020;
+
+fn GPIO_FUNCn_OUT_SEL_CFG_REG(comptime n: comptime_int) comptime_int {
+    return 0x0554 + 4 * n;
+}
+
+const LED_R_PIN = 3;
+const LED_G_PIN = 4;
+const LED_B_PIN = 5;
diff --git a/src/main.zig b/src/main.zig
deleted file mode 100644
index c8a3f67dd..000000000
--- a/src/main.zig
+++ /dev/null
@@ -1,24 +0,0 @@
-const std = @import("std");
-
-pub fn main() !void {
-    // Prints to stderr (it's a shortcut based on `std.io.getStdErr()`)
-    std.debug.print("All your {s} are belong to us.\n", .{"codebase"});
-
-    // stdout is for the actual output of your application, for example if you
-    // are implementing gzip, then only the compressed bytes should be sent to
-    // stdout, not any debugging messages.
-    const stdout_file = std.io.getStdOut().writer();
-    var bw = std.io.bufferedWriter(stdout_file);
-    const stdout = bw.writer();
-
-    try stdout.print("Run `zig build test` to run the tests.\n", .{});
-
-    try bw.flush(); // don't forget to flush!
-}
-
-test "simple test" {
-    var list = std.ArrayList(i32).init(std.testing.allocator);
-    defer list.deinit(); // try commenting this out and see if zig detects the memory leak!
-    try list.append(42);
-    try std.testing.expectEqual(@as(i32, 42), list.pop());
-}
diff --git a/src/package/esp32-c3.zig b/src/package/esp32-c3.zig
new file mode 100644
index 000000000..0a0f4fef2
--- /dev/null
+++ b/src/package/esp32-c3.zig
@@ -0,0 +1,45 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+pub const startup_logic = struct {
+    comptime {
+        // See this:
+        // https://github.com/espressif/esp32c3-direct-boot-example
+
+        // Direct Boot: does not support Security Boot and programs run directly in flash. To enable this mode, make
+        // sure that the first two words of the bin file downloading to flash (address: 0x42000000) are 0xaedb041d.
+
+        // In this case, the ROM bootloader sets up Flash MMU to map 4 MB of Flash to
+        // addresses 0x42000000 (for code execution) and 0x3C000000 (for read-only data
+        // access). The bootloader then jumps to address 0x42000008, i.e. to the
+        // instruction at offset 8 in flash, immediately after the magic numbers.
+
+        asm (std.fmt.comptimePrint(".equ MICROZIG_INITIAL_STACK, {}", .{microzig.config.end_of_stack}));
+
+        asm (
+            \\.extern _start
+            \\.section microzig_flash_start
+            \\.align 4
+            \\.byte 0x1d, 0x04, 0xdb, 0xae
+            \\.byte 0x1d, 0x04, 0xdb, 0xae
+        );
+    }
+
+    extern fn microzig_main() noreturn;
+
+    export fn _start() linksection("microzig_flash_start") callconv(.C) noreturn {
+        asm volatile (
+            \\li sp, MICROZIG_INITIAL_STACK
+            \\lui  a0, %%hi(_rv32_trap)
+            \\addi a0, a0, %%lo(_rv32_trap)
+            \\sw t0, 0x305(zero)
+        );
+
+        microzig.initializeSystemMemories();
+        microzig_main();
+    }
+
+    export fn _rv32_trap() callconv(.C) noreturn {
+        while (true) {}
+    }
+};
diff --git a/src/package/espressif-riscv.zig b/src/package/espressif-riscv.zig
new file mode 100644
index 000000000..34dbffd30
--- /dev/null
+++ b/src/package/espressif-riscv.zig
@@ -0,0 +1,12 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+pub inline fn cli() void {
+    asm volatile ("");
+}
+
+pub inline fn sei() void {
+    asm volatile ("");
+}
+
+pub const startup_logic = microzig.chip.startup_logic;
diff --git a/vendor/microzig b/vendor/microzig
index 15bc1fc06..0d9721d90 160000
--- a/vendor/microzig
+++ b/vendor/microzig
@@ -1 +1 @@
-Subproject commit 15bc1fc06da3b6c622a21fa438e40be247d9dee1
+Subproject commit 0d9721d9070c356f4ffaf6f4a312bccdb574b8a9

From 33984fa9605172a8b8e55711738d2e1b4be97247 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 8 Oct 2022 13:13:43 +0200
Subject: [PATCH 033/286] one readme

---
 README.md | 1 -
 1 file changed, 1 deletion(-)
 delete mode 100644 README.md

diff --git a/README.md b/README.md
deleted file mode 100644
index 2cd0dfa3e..000000000
--- a/README.md
+++ /dev/null
@@ -1 +0,0 @@
-# esp32-c3-bringup

From e84264e64ba5fc8cf5e01a5035c8e64e2fe2270a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 8 Oct 2022 16:19:20 +0200
Subject: [PATCH 034/286] Blinky! \o/

---
 build.zig                                  |  2 +-
 perform-flash.sh                           | 13 +++++
 src/example/blinky.zig                     | 59 +++++++++++++++-------
 src/hal/root.zig                           | 54 ++++++++++++++++++++
 src/package/esp32-c3.zig                   | 42 +++++++++++----
 src/package/espressif-riscv.zig            | 31 +++++++++++-
 src/{esp32c3.zig => package/registers.zig} |  0
 7 files changed, 171 insertions(+), 30 deletions(-)
 create mode 100755 perform-flash.sh
 create mode 100644 src/hal/root.zig
 rename src/{esp32c3.zig => package/registers.zig} (100%)

diff --git a/build.zig b/build.zig
index 3f49cf7dd..c0d71db84 100644
--- a/build.zig
+++ b/build.zig
@@ -34,7 +34,7 @@ pub fn build(b: *std.build.Builder) void {
         "esp-bringup",
         "src/example/blinky.zig",
         .{ .chip = esp32_c3 },
-        .{},
+        .{ .hal_package_path = .{ .path = "src/hal/root.zig" } },
     );
     exe.setBuildMode(mode);
     exe.install();
diff --git a/perform-flash.sh b/perform-flash.sh
new file mode 100755
index 000000000..ce1f5de72
--- /dev/null
+++ b/perform-flash.sh
@@ -0,0 +1,13 @@
+#!/bin/bash
+
+set -e
+
+clear
+zig build -Drelease-small
+llvm-objdump -S ./zig-out/bin/esp-bringup > /tmp/dump.txt
+esptool.py \
+  --port /dev/ttyUSB0 \
+  --baud 115200 \
+  write_flash 0x00000000 zig-out/bin/firmware.bin \
+  --verify
+picocom --baud 115200 /dev/ttyUSB0
\ No newline at end of file
diff --git a/src/example/blinky.zig b/src/example/blinky.zig
index 6bba15b0b..0518c5334 100644
--- a/src/example/blinky.zig
+++ b/src/example/blinky.zig
@@ -1,29 +1,52 @@
 const std = @import("std");
 const microzig = @import("microzig");
 
+const dogfood: u32 = 0x50D83AA1;
+const super_dogfood: u32 = 0x8F1D312A;
+
 pub fn main() !void {
-    // const led_r_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_R_PIN));
-    // const led_g_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_G_PIN));
-    // const led_b_mux = @ptrToInt(*volatile u32, IO_MUX_BASE + IO_MUX_GPIOn_REG(LED_B_PIN));
+    microzig.chip.registers.TIMG0.WDTWPROTECT.raw = dogfood;
+    microzig.chip.registers.TIMG0.WDTCONFIG0.raw = 0;
+    microzig.chip.registers.TIMG0.WDTWPROTECT.raw = 0;
 
-    // led_r_mux.* = 0x80;
+    microzig.chip.registers.RTC_CNTL.WDTWPROTECT.raw = dogfood;
+    microzig.chip.registers.RTC_CNTL.WDTCONFIG0.raw = 0;
+    microzig.chip.registers.RTC_CNTL.WDTWPROTECT.raw = 0;
 
-    const gpio_out = @intToPtr(*volatile u32, GPIO_BASE + GPIO_OUT_REG);
-    const gpio_ena = @intToPtr(*volatile u32, GPIO_BASE + GPIO_ENABLE_REG);
-    gpio_ena.* = (1 << LED_R_PIN) | (1 << LED_G_PIN) | (1 << LED_B_PIN);
-    gpio_out.* = (1 << LED_R_PIN) | (1 << LED_G_PIN) | (1 << LED_B_PIN);
-}
+    microzig.chip.registers.RTC_CNTL.SWD_WPROTECT.raw = super_dogfood;
+    microzig.chip.registers.RTC_CNTL.SWD_CONF.modify(.{ .SWD_DISABLE = 1 });
+    microzig.chip.registers.RTC_CNTL.SWD_WPROTECT.raw = 0;
+
+    microzig.chip.registers.INTERRUPT_CORE0.CPU_INT_ENABLE.* = 0;
 
-const GPIO_BASE = 0x6000_4000;
-const IO_MUX_BASE = 0x6000_9000;
+    microzig.hal.gpio.init(LED_R_PIN, .{
+        .direction = .output,
+        .direct_io = true,
+    });
+    microzig.hal.gpio.init(LED_G_PIN, .{
+        .direction = .output,
+        .direct_io = true,
+    });
+    microzig.hal.gpio.init(LED_B_PIN, .{
+        .direction = .output,
+        .direct_io = true,
+    });
 
-const GPIO_OUT_REG = 0x0004;
-const GPIO_ENABLE_REG = 0x0020;
+    microzig.hal.uart.write(0, "Hello from Zig!\r\n");
 
-fn GPIO_FUNCn_OUT_SEL_CFG_REG(comptime n: comptime_int) comptime_int {
-    return 0x0554 + 4 * n;
+    while (true) {
+        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
+        microzig.hal.uart.write(0, "R");
+        microzig.debug.busySleep(1_000_000);
+        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
+        microzig.hal.uart.write(0, "G");
+        microzig.debug.busySleep(1_000_000);
+        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
+        microzig.hal.uart.write(0, "B");
+        microzig.debug.busySleep(1_000_000);
+    }
 }
 
-const LED_R_PIN = 3;
-const LED_G_PIN = 4;
-const LED_B_PIN = 5;
+const LED_R_PIN = 3; // GPIO
+const LED_G_PIN = 16; // GPIO
+const LED_B_PIN = 17; // GPIO
diff --git a/src/hal/root.zig b/src/hal/root.zig
new file mode 100644
index 000000000..d87dab85e
--- /dev/null
+++ b/src/hal/root.zig
@@ -0,0 +1,54 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const regz = microzig.chip.registers;
+
+pub const gpio = struct {
+    fn getRegNamed(comptime fld: []const u8) @TypeOf(@field(regz.GPIO, fld)) {
+        return @field(regz.GPIO, fld);
+    }
+
+    fn getReg(comptime template: []const u8, comptime pin: comptime_int) @TypeOf(@field(regz.GPIO, std.fmt.comptimePrint(template, .{pin}))) {
+        return getRegNamed(comptime std.fmt.comptimePrint(template, .{pin}));
+    }
+
+    fn assertRange(comptime p: comptime_int) void {
+        if (p < 0 or p >= 21)
+            @compileError(std.fmt.comptimePrint("GPIO {} does not exist. GPIO pins can be between 0 and 21", .{p}));
+    }
+
+    pub const Config = struct {
+        function: u8 = 0x80,
+        invert_function: bool = false,
+        direction: microzig.gpio.Direction,
+        direct_io: bool = false,
+        invert_direct_io: bool = false,
+    };
+
+    pub fn init(comptime pin: comptime_int, comptime config: Config) void {
+        assertRange(pin);
+        getReg("FUNC{}_OUT_SEL_CFG", pin).modify(.{
+            .OUT_SEL = config.function,
+            .INV_SEL = @boolToInt(config.invert_function),
+            .OEN_SEL = @boolToInt(config.direct_io),
+            .OEN_INV_SEL = @boolToInt(config.invert_direct_io),
+        });
+        switch (config.direction) {
+            .input => microzig.chip.registers.GPIO.ENABLE.raw &= ~(@as(u32, 1) << pin),
+            .output => microzig.chip.registers.GPIO.ENABLE.raw |= (@as(u32, 1) << pin),
+        }
+    }
+};
+
+pub const uart = struct {
+    fn reg(comptime index: comptime_int) @TypeOf(@field(regz, std.fmt.comptimePrint("UART{}", .{index}))) {
+        return @field(regz, std.fmt.comptimePrint("UART{}", .{index}));
+    }
+
+    pub fn write(comptime index: comptime_int, slice: []const u8) void {
+        const r = reg(index);
+        for (slice) |c| {
+            while (r.STATUS.read().TXFIFO_CNT > 8) {}
+            r.FIFO.raw = c;
+        }
+    }
+};
diff --git a/src/package/esp32-c3.zig b/src/package/esp32-c3.zig
index 0a0f4fef2..0ab49440d 100644
--- a/src/package/esp32-c3.zig
+++ b/src/package/esp32-c3.zig
@@ -1,6 +1,8 @@
 const std = @import("std");
 const microzig = @import("microzig");
 
+pub const registers = @import("registers.zig").registers;
+
 pub const startup_logic = struct {
     comptime {
         // See this:
@@ -14,8 +16,6 @@ pub const startup_logic = struct {
         // access). The bootloader then jumps to address 0x42000008, i.e. to the
         // instruction at offset 8 in flash, immediately after the magic numbers.
 
-        asm (std.fmt.comptimePrint(".equ MICROZIG_INITIAL_STACK, {}", .{microzig.config.end_of_stack}));
-
         asm (
             \\.extern _start
             \\.section microzig_flash_start
@@ -27,14 +27,14 @@ pub const startup_logic = struct {
 
     extern fn microzig_main() noreturn;
 
-    export fn _start() linksection("microzig_flash_start") callconv(.C) noreturn {
-        asm volatile (
-            \\li sp, MICROZIG_INITIAL_STACK
-            \\lui  a0, %%hi(_rv32_trap)
-            \\addi a0, a0, %%lo(_rv32_trap)
-            \\sw t0, 0x305(zero)
+    export fn _start() linksection("microzig_flash_start") callconv(.Naked) noreturn {
+        microzig.cpu.cli();
+        asm volatile ("mv sp, %[eos]"
+            :
+            : [eos] "r" (@as(u32, microzig.config.end_of_stack)),
         );
-
+        asm volatile ("la gp, __global_pointer$");
+        microzig.cpu.setStatusBit(.mtvec, microzig.config.end_of_stack);
         microzig.initializeSystemMemories();
         microzig_main();
     }
@@ -42,4 +42,28 @@ pub const startup_logic = struct {
     export fn _rv32_trap() callconv(.C) noreturn {
         while (true) {}
     }
+
+    const vector_table = [_]fn () callconv(.C) noreturn{
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+        _rv32_trap,
+    };
 };
diff --git a/src/package/espressif-riscv.zig b/src/package/espressif-riscv.zig
index 34dbffd30..06d7bc444 100644
--- a/src/package/espressif-riscv.zig
+++ b/src/package/espressif-riscv.zig
@@ -1,12 +1,39 @@
 const std = @import("std");
 const microzig = @import("microzig");
 
+pub const StatusRegister = enum(u8) {
+    // machine information
+    mvendorid,
+    marchid,
+    mimpid,
+    mhartid,
+
+    // machine trap setup
+    mstatus,
+    misa,
+    mtvec,
+};
+
+pub inline fn setStatusBit(comptime reg: StatusRegister, bits: u32) void {
+    asm volatile ("csrrs zero, " ++ @tagName(reg) ++ ", %[value]"
+        :
+        : [value] "r" (bits),
+    );
+}
+
+pub inline fn clearStatusBit(comptime reg: StatusRegister, bits: u32) void {
+    asm volatile ("csrrc zero, " ++ @tagName(reg) ++ ", %[value]"
+        :
+        : [value] "r" (bits),
+    );
+}
+
 pub inline fn cli() void {
-    asm volatile ("");
+    clearStatusBit(.mstatus, 0x08);
 }
 
 pub inline fn sei() void {
-    asm volatile ("");
+    setStatusBit(.mstatus, 0x08);
 }
 
 pub const startup_logic = microzig.chip.startup_logic;
diff --git a/src/esp32c3.zig b/src/package/registers.zig
similarity index 100%
rename from src/esp32c3.zig
rename to src/package/registers.zig

From 72a5680af839c1bb8d84459690e28d4f50673300 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 22 Dec 2022 10:43:44 -0800
Subject: [PATCH 035/286] Initial commit

---
 LICENSE   | 21 +++++++++++++++++++++
 README.md |  2 ++
 2 files changed, 23 insertions(+)
 create mode 100644 LICENSE
 create mode 100644 README.md

diff --git a/LICENSE b/LICENSE
new file mode 100644
index 000000000..4818f98dd
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,21 @@
+MIT License
+
+Copyright (c) 2022 Zig Embedded Group
+
+Permission is hereby granted, free of charge, to any person obtaining a copy
+of this software and associated documentation files (the "Software"), to deal
+in the Software without restriction, including without limitation the rights
+to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+copies of the Software, and to permit persons to whom the Software is
+furnished to do so, subject to the following conditions:
+
+The above copyright notice and this permission notice shall be included in all
+copies or substantial portions of the Software.
+
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+SOFTWARE.
diff --git a/README.md b/README.md
new file mode 100644
index 000000000..c3bfa2788
--- /dev/null
+++ b/README.md
@@ -0,0 +1,2 @@
+# microzig-examples
+Examples for embedded zig!

From 0713809eaf2eab45b06166f9d33ad3d996601822 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 1 Jan 2023 13:00:47 -0800
Subject: [PATCH 036/286] catch up to master (#17)

---
 deps/microzig         |  2 +-
 src/hal/multicore.zig |  8 ++++----
 src/hal/pins.zig      | 14 +++++++-------
 src/rp2040.zig        |  4 ++--
 4 files changed, 14 insertions(+), 14 deletions(-)

diff --git a/deps/microzig b/deps/microzig
index 15bc1fc06..4f0d25220 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 15bc1fc06da3b6c622a21fa438e40be247d9dee1
+Subproject commit 4f0d25220ec8f0501f8e0e9f6765689eb32faa5f
diff --git a/src/hal/multicore.zig b/src/hal/multicore.zig
index 76811cf2a..f1bcfe08c 100644
--- a/src/hal/multicore.zig
+++ b/src/hal/multicore.zig
@@ -55,18 +55,18 @@ pub const fifo = struct {
 var core1_stack: [128]u32 = undefined;
 
 /// Runs `entrypoint` on the second core.
-pub fn launchCore1(entrypoint: fn () void) void {
+pub fn launchCore1(entrypoint: *const fn () void) void {
     launchCore1WithStack(entrypoint, &core1_stack);
 }
 
-pub fn launchCore1WithStack(entrypoint: fn () void, stack: []u32) void {
+pub fn launchCore1WithStack(entrypoint: *const fn () void, stack: []u32) void {
     // TODO: disable SIO interrupts
 
-    const wrapper = struct {
+    const wrapper = &struct {
         fn wrapper(_: u32, _: u32, _: u32, _: u32, entry: u32, stack_base: [*]u32) callconv(.C) void {
             // TODO: protect stack using MPU
             _ = stack_base;
-            @intToPtr(fn () void, entry)();
+            @intToPtr(*const fn () void, entry)();
         }
     }.wrapper;
 
diff --git a/src/hal/pins.zig b/src/hal/pins.zig
index 94f6caa5d..dce1c2418 100644
--- a/src/hal/pins.zig
+++ b/src/hal/pins.zig
@@ -347,19 +347,19 @@ pub fn Pins(comptime config: GlobalConfiguration) type {
 
                     // initialized below:
                     .name = undefined,
-                    .field_type = undefined,
+                    .type = undefined,
                     .alignment = undefined,
                 };
 
                 if (pin_config.function == .SIO) {
                     pin_field.name = pin_config.name orelse field.name;
-                    pin_field.field_type = GPIO(@enumToInt(@field(Pin, field.name)), pin_config.direction orelse .in);
+                    pin_field.type = GPIO(@enumToInt(@field(Pin, field.name)), pin_config.direction orelse .in);
                 } else if (pin_config.function.isPwm()) {
                     pin_field.name = pin_config.name orelse @tagName(pin_config.function);
-                    pin_field.field_type = pwm.PWM(pin_config.function.pwmSlice(), pin_config.function.pwmChannel());
+                    pin_field.type = pwm.PWM(pin_config.function.pwmSlice(), pin_config.function.pwmChannel());
                 } else if (pin_config.function.isAdc()) {
                     pin_field.name = pin_config.name orelse @tagName(pin_config.function);
-                    pin_field.field_type = adc.Input;
+                    pin_field.type = adc.Input;
                     pin_field.default_value = @ptrCast(?*const anyopaque, switch (pin_config.function) {
                         .ADC0 => &adc.Input.ain0,
                         .ADC1 => &adc.Input.ain1,
@@ -382,7 +382,7 @@ pub fn Pins(comptime config: GlobalConfiguration) type {
                 //     }
                 // }
 
-                pin_field.alignment = @alignOf(field.field_type);
+                pin_field.alignment = @alignOf(field.type);
 
                 fields = fields ++ &[_]StructField{pin_field};
             }
@@ -498,11 +498,11 @@ pub const GlobalConfiguration = struct {
                 } else if (comptime func.isPwm()) {
                     gpio.setFunction(gpio_num, .pwm);
                 } else if (comptime func.isAdc()) {
-                    gpio.setFunction(gpio_num, .@"null");
+                    gpio.setFunction(gpio_num, .null);
                 } else if (comptime func.isUartTx() or func.isUartRx()) {
                     gpio.setFunction(gpio_num, .uart);
                 } else {
-                    @compileError(comptime std.fmt.comptimePrint("Unimplemented pin function. Please implement setting pin function {s} for GPIO {}", .{
+                    @compileError(std.fmt.comptimePrint("Unimplemented pin function. Please implement setting pin function {s} for GPIO {}", .{
                         @tagName(func),
                         gpio_num,
                     }));
diff --git a/src/rp2040.zig b/src/rp2040.zig
index 6301bf235..d3c2e1868 100644
--- a/src/rp2040.zig
+++ b/src/rp2040.zig
@@ -28780,8 +28780,8 @@ pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile Mm
 }
 
 pub const InterruptVector = extern union {
-    C: fn () callconv(.C) void,
-    Naked: fn () callconv(.Naked) void,
+    C: *const fn () callconv(.C) void,
+    Naked: *const fn () callconv(.Naked) void,
     // Interrupt is not supported on arm
 };
 

From e3562492df5e3f564e5804eca073efe8aa68e88b Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 14 Feb 2023 21:00:04 +0200
Subject: [PATCH 037/286] update to master (#19)

---
 build.zig     | 18 ++++++++++--------
 deps/microzig |  2 +-
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/build.zig b/build.zig
index d00c9621b..35bad24c9 100644
--- a/build.zig
+++ b/build.zig
@@ -10,13 +10,15 @@ const board_path = comptimePrint("{s}/src/raspberry_pi_pico.zig", .{root()});
 const hal_path = comptimePrint("{s}/src/hal.zig", .{root()});
 const linkerscript_path = comptimePrint("{s}/rp2040.ld", .{root()});
 
-pub const BuildOptions = struct {};
+pub const BuildOptions = struct {
+    optimize: std.builtin.OptimizeMode,
+};
 
 pub fn addPiPicoExecutable(
     builder: *Builder,
     name: []const u8,
     source: []const u8,
-    _: BuildOptions,
+    options: BuildOptions,
 ) microzig.EmbeddedExecutable {
     const rp2040 = microzig.Chip{
         .name = "RP2040",
@@ -41,7 +43,8 @@ pub fn addPiPicoExecutable(
         source,
         .{ .board = raspberry_pi_pico },
         .{
-            .hal_package_path = .{ .path = hal_path },
+            .optimize = options.optimize,
+            .hal_module_path = .{ .path = hal_path },
         },
     );
     ret.inner.setLinkerScriptPath(.{ .path = linkerscript_path });
@@ -53,8 +56,8 @@ pub fn addPiPicoExecutable(
 // package. In an attempt to modularize -- designing for a case where a
 // project requires multiple HALs, it accepts microzig as a param
 pub fn build(b: *Builder) !void {
-    const mode = b.standardReleaseOptions();
-    var examples = Examples.init(b, mode);
+    const optimize = b.standardOptimizeOption(.{});
+    var examples = Examples.init(b, optimize);
     examples.install();
 }
 
@@ -71,16 +74,15 @@ pub const Examples = struct {
     uart: microzig.EmbeddedExecutable,
     //uart_pins: microzig.EmbeddedExecutable,
 
-    pub fn init(b: *Builder, mode: std.builtin.Mode) Examples {
+    pub fn init(b: *Builder, optimize: std.builtin.OptimizeMode) Examples {
         var ret: Examples = undefined;
         inline for (@typeInfo(Examples).Struct.fields) |field| {
             @field(ret, field.name) = addPiPicoExecutable(
                 b,
                 field.name,
                 comptime root() ++ "/examples/" ++ field.name ++ ".zig",
-                .{},
+                .{ .optimize = optimize },
             );
-            @field(ret, field.name).setBuildMode(mode);
         }
 
         return ret;
diff --git a/deps/microzig b/deps/microzig
index 4f0d25220..9ccde9ff3 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4f0d25220ec8f0501f8e0e9f6765689eb32faa5f
+Subproject commit 9ccde9ff371b355394f65eacb6b51c5880768505

From d8e329d90b75800964f3681df2e41ee8d19f7a77 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 18 Feb 2023 07:22:55 -0500
Subject: [PATCH 038/286] restructure for regz rewrite

---
 .gitignore                |     2 +
 README.adoc               |     7 +
 build.zig                 |    20 +
 src/chips.zig             |    43 +
 src/chips/nrf52.json      | 34901 ++++++++++++++++++++++++++++
 src/chips/nrf52.zig       | 16821 ++++++++++++++
 src/chips/nrf52840.json   | 44867 ++++++++++++++++++++++++++++++++++++
 src/chips/nrf52840.zig    | 21782 +++++++++++++++++
 test/nrf52840.robot       |    10 +
 test/programs/minimal.zig |     5 +
 10 files changed, 118458 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 README.adoc
 create mode 100644 build.zig
 create mode 100644 src/chips.zig
 create mode 100644 src/chips/nrf52.json
 create mode 100644 src/chips/nrf52.zig
 create mode 100644 src/chips/nrf52840.json
 create mode 100644 src/chips/nrf52840.zig
 create mode 100644 test/nrf52840.robot
 create mode 100644 test/programs/minimal.zig

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 000000000..c26d4af28
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+zig-out
+zig-cache
diff --git a/README.adoc b/README.adoc
new file mode 100644
index 000000000..0a66afd4e
--- /dev/null
+++ b/README.adoc
@@ -0,0 +1,7 @@
+= Nordic nrf5x
+
+HALs and register definitions for nrf5x devices
+
+== Renode supports:
+
+- nrf52840 development kit
diff --git a/build.zig b/build.zig
new file mode 100644
index 000000000..40398384d
--- /dev/null
+++ b/build.zig
@@ -0,0 +1,20 @@
+const std = @import("std");
+const microzig = @import("deps/microzig/src/main.zig");
+const chips = @import("src/chips.zig");
+
+pub fn build(b: *std.build.Builder) void {
+    const optimize = b.standardOptimizeOption(.{});
+    inline for (@typeInfo(chips).Struct.decls) |decl| {
+        if (!decl.is_pub)
+            continue;
+
+        const exe = microzig.addEmbeddedExecutable(
+            b,
+            decl.name ++ ".minimal",
+            "test/programs/minimal.zig",
+            .{ .chip = @field(chips, decl.name) },
+            .{ .optimize = optimize },
+        );
+        exe.install();
+    }
+}
diff --git a/src/chips.zig b/src/chips.zig
new file mode 100644
index 000000000..50b2aad62
--- /dev/null
+++ b/src/chips.zig
@@ -0,0 +1,43 @@
+const std = @import("std");
+const micro = @import("../deps/microzig/src/main.zig");
+const Chip = micro.Chip;
+const MemoryRegion = micro.MemoryRegion;
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse unreachable;
+}
+
+pub const nrf52840 = Chip{
+    .name = "nrf52840",
+    .source = .{
+        .path = root_dir() ++ "/chips/nrf52840.zig",
+    },
+    .json_register_schema = .{
+        .path = root_dir() ++ "/chips.nrf52840.json",
+    },
+    .cpu = micro.cpus.cortex_m4,
+    .memory_regions = &.{
+        MemoryRegion{ .offset = 0x00000000, .length = 0x100000, .kind = .flash },
+        MemoryRegion{ .offset = 0x20000000, .length = 0x40000, .kind = .ram },
+
+        // EXTFLASH
+        MemoryRegion{ .offset = 0x12000000, .length = 0x8000000, .kind = .flash },
+        // CODE_RAM
+        MemoryRegion{ .offset = 0x800000, .length = 0x40000, .kind = .ram },
+    },
+};
+
+pub const nrf52832 = Chip{
+    .name = "nrf52",
+    .source = .{
+        .path = root_dir() ++ "/chips/nrf52.zig",
+    },
+    .json_register_schema = .{
+        .path = root_dir() ++ "/chips.nrf52.json",
+    },
+    .cpu = micro.cpus.cortex_m4,
+    .memory_regions = &.{
+        MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash },
+        MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram },
+    },
+};
diff --git a/src/chips/nrf52.json b/src/chips/nrf52.json
new file mode 100644
index 000000000..8c71c649b
--- /dev/null
+++ b/src/chips/nrf52.json
@@ -0,0 +1,34901 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "SCS": {
+        "description": "System Control Space",
+        "children": {
+          "register_groups": {
+            "SysTick": {
+              "description": "System Tick Timer",
+              "children": {
+                "registers": {
+                  "CTRL": {
+                    "description": "SysTick Control and Status Register",
+                    "offset": 0,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "ENABLE": {
+                          "offset": 0,
+                          "size": 1
+                        },
+                        "TICKINT": {
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "CLKSOURCE": {
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "COUNTFLAG": {
+                          "offset": 16,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "LOAD": {
+                    "description": "SysTick Reload Value Register",
+                    "offset": 4,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "RELOAD": {
+                          "offset": 0,
+                          "size": 24
+                        }
+                      }
+                    }
+                  },
+                  "VAL": {
+                    "description": "SysTick Current Value Register",
+                    "offset": 8,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "CURRENT": {
+                          "offset": 0,
+                          "size": 24
+                        }
+                      }
+                    }
+                  },
+                  "CALIB": {
+                    "description": "SysTick Calibration Register",
+                    "offset": 12,
+                    "size": 32,
+                    "access": "read-only",
+                    "children": {
+                      "fields": {
+                        "TENMS": {
+                          "offset": 0,
+                          "size": 24
+                        },
+                        "SKEW": {
+                          "offset": 30,
+                          "size": 1
+                        },
+                        "NOREF": {
+                          "offset": 31,
+                          "size": 1
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FICR": {
+        "description": "Factory Information Configuration Registers",
+        "children": {
+          "registers": {
+            "CODEPAGESIZE": {
+              "description": "Code memory page size",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CODEPAGESIZE": {
+                    "description": "Code memory page size",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CODESIZE": {
+              "description": "Code memory size",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CODESIZE": {
+                    "description": "Code memory size in number of pages",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DEVICEID": {
+              "description": "Description collection[0]:  Device identifier",
+              "offset": 96,
+              "size": 32,
+              "count": 2,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DEVICEID": {
+                    "description": "64 bit unique device identifier",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ER": {
+              "description": "Description collection[0]:  Encryption Root, word 0",
+              "offset": 128,
+              "size": 32,
+              "count": 4,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ER": {
+                    "description": "Encryption Root, word n",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IR": {
+              "description": "Description collection[0]:  Identity Root, word 0",
+              "offset": 144,
+              "size": 32,
+              "count": 4,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IR": {
+                    "description": "Identity Root, word n",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DEVICEADDRTYPE": {
+              "description": "Device address type",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DEVICEADDRTYPE": {
+                    "description": "Device address type",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Public": {
+                            "description": "Public address",
+                            "value": 0
+                          },
+                          "Random": {
+                            "description": "Random address",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DEVICEADDR": {
+              "description": "Description collection[0]:  Device address 0",
+              "offset": 164,
+              "size": 32,
+              "count": 2,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DEVICEADDR": {
+                    "description": "48 bit device address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UICR": {
+        "description": "User Information Configuration Registers",
+        "children": {
+          "registers": {
+            "UNUSED0": {
+              "description": "Unspecified",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "UNUSED1": {
+              "description": "Unspecified",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "UNUSED2": {
+              "description": "Unspecified",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "UNUSED3": {
+              "description": "Unspecified",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "NRFFW": {
+              "description": "Description collection[0]:  Reserved for Nordic firmware design",
+              "offset": 20,
+              "size": 32,
+              "count": 15,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NRFFW": {
+                    "description": "Reserved for Nordic firmware design",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "NRFHW": {
+              "description": "Description collection[0]:  Reserved for Nordic hardware design",
+              "offset": 80,
+              "size": 32,
+              "count": 12,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NRFHW": {
+                    "description": "Reserved for Nordic hardware design",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CUSTOMER": {
+              "description": "Description collection[0]:  Reserved for customer",
+              "offset": 128,
+              "size": 32,
+              "count": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CUSTOMER": {
+                    "description": "Reserved for customer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PSELRESET": {
+              "description": "Description collection[0]:  Mapping of the nRESET function (see POWER chapter for details)",
+              "offset": 512,
+              "size": 32,
+              "count": 2,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN": {
+                    "description": "GPIO number P0.n onto which Reset is exposed",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "CONNECT": {
+                    "description": "Connection",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disconnected": {
+                            "description": "Disconnect",
+                            "value": 1
+                          },
+                          "Connected": {
+                            "description": "Connect",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "APPROTECT": {
+              "description": "Access Port protection",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PALL": {
+                    "description": "Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection.",
+                    "offset": 0,
+                    "size": 8,
+                    "enum": {
+                      "size": 8,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 255
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "NFCPINS": {
+              "description": "Setting of pins dedicated to NFC functionality: NFC antenna or GPIO",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PROTECT": {
+                    "description": "Setting of pins dedicated to NFC functionality",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Operation as GPIO pins. Same protection as normal GPIO pins",
+                            "value": 0
+                          },
+                          "NFC": {
+                            "description": "Operation as NFC antenna pins. Configures the protection for NFC operation",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "BPROT": {
+        "description": "Block Protect",
+        "children": {
+          "registers": {
+            "CONFIG0": {
+              "description": "Block protect configuration register 0",
+              "offset": 1536,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0": {
+                    "description": "Enable protection for region 0. Write '0' has no effect.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1": {
+                    "description": "Enable protection for region 1. Write '0' has no effect.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2": {
+                    "description": "Enable protection for region 2. Write '0' has no effect.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3": {
+                    "description": "Enable protection for region 3. Write '0' has no effect.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION4": {
+                    "description": "Enable protection for region 4. Write '0' has no effect.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION5": {
+                    "description": "Enable protection for region 5. Write '0' has no effect.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION6": {
+                    "description": "Enable protection for region 6. Write '0' has no effect.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION7": {
+                    "description": "Enable protection for region 7. Write '0' has no effect.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION8": {
+                    "description": "Enable protection for region 8. Write '0' has no effect.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION9": {
+                    "description": "Enable protection for region 9. Write '0' has no effect.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION10": {
+                    "description": "Enable protection for region 10. Write '0' has no effect.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION11": {
+                    "description": "Enable protection for region 11. Write '0' has no effect.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION12": {
+                    "description": "Enable protection for region 12. Write '0' has no effect.",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION13": {
+                    "description": "Enable protection for region 13. Write '0' has no effect.",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION14": {
+                    "description": "Enable protection for region 14. Write '0' has no effect.",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION15": {
+                    "description": "Enable protection for region 15. Write '0' has no effect.",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION16": {
+                    "description": "Enable protection for region 16. Write '0' has no effect.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION17": {
+                    "description": "Enable protection for region 17. Write '0' has no effect.",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION18": {
+                    "description": "Enable protection for region 18. Write '0' has no effect.",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION19": {
+                    "description": "Enable protection for region 19. Write '0' has no effect.",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION20": {
+                    "description": "Enable protection for region 20. Write '0' has no effect.",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION21": {
+                    "description": "Enable protection for region 21. Write '0' has no effect.",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION22": {
+                    "description": "Enable protection for region 22. Write '0' has no effect.",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION23": {
+                    "description": "Enable protection for region 23. Write '0' has no effect.",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION24": {
+                    "description": "Enable protection for region 24. Write '0' has no effect.",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION25": {
+                    "description": "Enable protection for region 25. Write '0' has no effect.",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION26": {
+                    "description": "Enable protection for region 26. Write '0' has no effect.",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION27": {
+                    "description": "Enable protection for region 27. Write '0' has no effect.",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION28": {
+                    "description": "Enable protection for region 28. Write '0' has no effect.",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION29": {
+                    "description": "Enable protection for region 29. Write '0' has no effect.",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION30": {
+                    "description": "Enable protection for region 30. Write '0' has no effect.",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION31": {
+                    "description": "Enable protection for region 31. Write '0' has no effect.",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG1": {
+              "description": "Block protect configuration register 1",
+              "offset": 1540,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION32": {
+                    "description": "Enable protection for region 32. Write '0' has no effect.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION33": {
+                    "description": "Enable protection for region 33. Write '0' has no effect.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION34": {
+                    "description": "Enable protection for region 34. Write '0' has no effect.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION35": {
+                    "description": "Enable protection for region 35. Write '0' has no effect.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION36": {
+                    "description": "Enable protection for region 36. Write '0' has no effect.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION37": {
+                    "description": "Enable protection for region 37. Write '0' has no effect.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION38": {
+                    "description": "Enable protection for region 38. Write '0' has no effect.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION39": {
+                    "description": "Enable protection for region 39. Write '0' has no effect.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION40": {
+                    "description": "Enable protection for region 40. Write '0' has no effect.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION41": {
+                    "description": "Enable protection for region 41. Write '0' has no effect.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION42": {
+                    "description": "Enable protection for region 42. Write '0' has no effect.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION43": {
+                    "description": "Enable protection for region 43. Write '0' has no effect.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION44": {
+                    "description": "Enable protection for region 44. Write '0' has no effect.",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION45": {
+                    "description": "Enable protection for region 45. Write '0' has no effect.",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION46": {
+                    "description": "Enable protection for region 46. Write '0' has no effect.",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION47": {
+                    "description": "Enable protection for region 47. Write '0' has no effect.",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION48": {
+                    "description": "Enable protection for region 48. Write '0' has no effect.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION49": {
+                    "description": "Enable protection for region 49. Write '0' has no effect.",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION50": {
+                    "description": "Enable protection for region 50. Write '0' has no effect.",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION51": {
+                    "description": "Enable protection for region 51. Write '0' has no effect.",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION52": {
+                    "description": "Enable protection for region 52. Write '0' has no effect.",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION53": {
+                    "description": "Enable protection for region 53. Write '0' has no effect.",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION54": {
+                    "description": "Enable protection for region 54. Write '0' has no effect.",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION55": {
+                    "description": "Enable protection for region 55. Write '0' has no effect.",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION56": {
+                    "description": "Enable protection for region 56. Write '0' has no effect.",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION57": {
+                    "description": "Enable protection for region 57. Write '0' has no effect.",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION58": {
+                    "description": "Enable protection for region 58. Write '0' has no effect.",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION59": {
+                    "description": "Enable protection for region 59. Write '0' has no effect.",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION60": {
+                    "description": "Enable protection for region 60. Write '0' has no effect.",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION61": {
+                    "description": "Enable protection for region 61. Write '0' has no effect.",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION62": {
+                    "description": "Enable protection for region 62. Write '0' has no effect.",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION63": {
+                    "description": "Enable protection for region 63. Write '0' has no effect.",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DISABLEINDEBUG": {
+              "description": "Disable protection mechanism in debug interface mode",
+              "offset": 1544,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DISABLEINDEBUG": {
+                    "description": "Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable in debug",
+                            "value": 1
+                          },
+                          "Enabled": {
+                            "description": "Enable in debug",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "UNUSED0": {
+              "description": "Unspecified",
+              "offset": 1548,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "CONFIG2": {
+              "description": "Block protect configuration register 2",
+              "offset": 1552,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION64": {
+                    "description": "Enable protection for region 64. Write '0' has no effect.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION65": {
+                    "description": "Enable protection for region 65. Write '0' has no effect.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION66": {
+                    "description": "Enable protection for region 66. Write '0' has no effect.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION67": {
+                    "description": "Enable protection for region 67. Write '0' has no effect.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION68": {
+                    "description": "Enable protection for region 68. Write '0' has no effect.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION69": {
+                    "description": "Enable protection for region 69. Write '0' has no effect.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION70": {
+                    "description": "Enable protection for region 70. Write '0' has no effect.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION71": {
+                    "description": "Enable protection for region 71. Write '0' has no effect.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION72": {
+                    "description": "Enable protection for region 72. Write '0' has no effect.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION73": {
+                    "description": "Enable protection for region 73. Write '0' has no effect.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION74": {
+                    "description": "Enable protection for region 74. Write '0' has no effect.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION75": {
+                    "description": "Enable protection for region 75. Write '0' has no effect.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION76": {
+                    "description": "Enable protection for region 76. Write '0' has no effect.",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION77": {
+                    "description": "Enable protection for region 77. Write '0' has no effect.",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION78": {
+                    "description": "Enable protection for region 78. Write '0' has no effect.",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION79": {
+                    "description": "Enable protection for region 79. Write '0' has no effect.",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION80": {
+                    "description": "Enable protection for region 80. Write '0' has no effect.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION81": {
+                    "description": "Enable protection for region 81. Write '0' has no effect.",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION82": {
+                    "description": "Enable protection for region 82. Write '0' has no effect.",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION83": {
+                    "description": "Enable protection for region 83. Write '0' has no effect.",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION84": {
+                    "description": "Enable protection for region 84. Write '0' has no effect.",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION85": {
+                    "description": "Enable protection for region 85. Write '0' has no effect.",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION86": {
+                    "description": "Enable protection for region 86. Write '0' has no effect.",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION87": {
+                    "description": "Enable protection for region 87. Write '0' has no effect.",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION88": {
+                    "description": "Enable protection for region 88. Write '0' has no effect.",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION89": {
+                    "description": "Enable protection for region 89. Write '0' has no effect.",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION90": {
+                    "description": "Enable protection for region 90. Write '0' has no effect.",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION91": {
+                    "description": "Enable protection for region 91. Write '0' has no effect.",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION92": {
+                    "description": "Enable protection for region 92. Write '0' has no effect.",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION93": {
+                    "description": "Enable protection for region 93. Write '0' has no effect.",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION94": {
+                    "description": "Enable protection for region 94. Write '0' has no effect.",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION95": {
+                    "description": "Enable protection for region 95. Write '0' has no effect.",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG3": {
+              "description": "Block protect configuration register 3",
+              "offset": 1556,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION96": {
+                    "description": "Enable protection for region 96. Write '0' has no effect.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION97": {
+                    "description": "Enable protection for region 97. Write '0' has no effect.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION98": {
+                    "description": "Enable protection for region 98. Write '0' has no effect.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION99": {
+                    "description": "Enable protection for region 99. Write '0' has no effect.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION100": {
+                    "description": "Enable protection for region 100. Write '0' has no effect.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION101": {
+                    "description": "Enable protection for region 101. Write '0' has no effect.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION102": {
+                    "description": "Enable protection for region 102. Write '0' has no effect.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION103": {
+                    "description": "Enable protection for region 103. Write '0' has no effect.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION104": {
+                    "description": "Enable protection for region 104. Write '0' has no effect.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION105": {
+                    "description": "Enable protection for region 105. Write '0' has no effect.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION106": {
+                    "description": "Enable protection for region 106. Write '0' has no effect.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION107": {
+                    "description": "Enable protection for region 107. Write '0' has no effect.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION108": {
+                    "description": "Enable protection for region 108. Write '0' has no effect.",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION109": {
+                    "description": "Enable protection for region 109. Write '0' has no effect.",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION110": {
+                    "description": "Enable protection for region 110. Write '0' has no effect.",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION111": {
+                    "description": "Enable protection for region 111. Write '0' has no effect.",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION112": {
+                    "description": "Enable protection for region 112. Write '0' has no effect.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION113": {
+                    "description": "Enable protection for region 113. Write '0' has no effect.",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION114": {
+                    "description": "Enable protection for region 114. Write '0' has no effect.",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION115": {
+                    "description": "Enable protection for region 115. Write '0' has no effect.",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION116": {
+                    "description": "Enable protection for region 116. Write '0' has no effect.",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION117": {
+                    "description": "Enable protection for region 117. Write '0' has no effect.",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION118": {
+                    "description": "Enable protection for region 118. Write '0' has no effect.",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION119": {
+                    "description": "Enable protection for region 119. Write '0' has no effect.",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION120": {
+                    "description": "Enable protection for region 120. Write '0' has no effect.",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION121": {
+                    "description": "Enable protection for region 121. Write '0' has no effect.",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION122": {
+                    "description": "Enable protection for region 122. Write '0' has no effect.",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION123": {
+                    "description": "Enable protection for region 123. Write '0' has no effect.",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION124": {
+                    "description": "Enable protection for region 124. Write '0' has no effect.",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION125": {
+                    "description": "Enable protection for region 125. Write '0' has no effect.",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION126": {
+                    "description": "Enable protection for region 126. Write '0' has no effect.",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION127": {
+                    "description": "Enable protection for region 127. Write '0' has no effect.",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Protection disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Protection enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "POWER": {
+        "description": "Power control",
+        "children": {
+          "registers": {
+            "TASKS_CONSTLAT": {
+              "description": "Enable constant latency mode",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_LOWPWR": {
+              "description": "Enable low power mode (variable latency)",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_POFWARN": {
+              "description": "Power failure warning",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_SLEEPENTER": {
+              "description": "CPU entered WFI/WFE sleep",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_SLEEPEXIT": {
+              "description": "CPU exited WFI/WFE sleep",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POFWARN": {
+                    "description": "Write '1' to Enable interrupt for POFWARN event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SLEEPENTER": {
+                    "description": "Write '1' to Enable interrupt for SLEEPENTER event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SLEEPEXIT": {
+                    "description": "Write '1' to Enable interrupt for SLEEPEXIT event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POFWARN": {
+                    "description": "Write '1' to Disable interrupt for POFWARN event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SLEEPENTER": {
+                    "description": "Write '1' to Disable interrupt for SLEEPENTER event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SLEEPEXIT": {
+                    "description": "Write '1' to Disable interrupt for SLEEPEXIT event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RESETREAS": {
+              "description": "Reset reason",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESETPIN": {
+                    "description": "Reset from pin-reset detected",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOG": {
+                    "description": "Reset from watchdog detected",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SREQ": {
+                    "description": "Reset from soft reset detected",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOCKUP": {
+                    "description": "Reset from CPU lock-up detected",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OFF": {
+                    "description": "Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LPCOMP": {
+                    "description": "Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DIF": {
+                    "description": "Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NFC": {
+                    "description": "Reset due to wake up from System OFF mode by NFC field detect",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RAMSTATUS": {
+              "description": "Deprecated register -  RAM status register",
+              "offset": 1064,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RAMBLOCK0": {
+                    "description": "RAM block 0 is on or off/powering up",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RAMBLOCK1": {
+                    "description": "RAM block 1 is on or off/powering up",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RAMBLOCK2": {
+                    "description": "RAM block 2 is on or off/powering up",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RAMBLOCK3": {
+                    "description": "RAM block 3 is on or off/powering up",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SYSTEMOFF": {
+              "description": "System OFF register",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "SYSTEMOFF": {
+                    "description": "Enable System OFF mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Enter": {
+                            "description": "Enable System OFF mode",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "POFCON": {
+              "description": "Power failure comparator configuration",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POF": {
+                    "description": "Enable or disable power failure comparator",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "THRESHOLD": {
+                    "description": "Power failure comparator threshold setting",
+                    "offset": 1,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "V17": {
+                            "description": "Set threshold to 1.7 V",
+                            "value": 4
+                          },
+                          "V18": {
+                            "description": "Set threshold to 1.8 V",
+                            "value": 5
+                          },
+                          "V19": {
+                            "description": "Set threshold to 1.9 V",
+                            "value": 6
+                          },
+                          "V20": {
+                            "description": "Set threshold to 2.0 V",
+                            "value": 7
+                          },
+                          "V21": {
+                            "description": "Set threshold to 2.1 V",
+                            "value": 8
+                          },
+                          "V22": {
+                            "description": "Set threshold to 2.2 V",
+                            "value": 9
+                          },
+                          "V23": {
+                            "description": "Set threshold to 2.3 V",
+                            "value": 10
+                          },
+                          "V24": {
+                            "description": "Set threshold to 2.4 V",
+                            "value": 11
+                          },
+                          "V25": {
+                            "description": "Set threshold to 2.5 V",
+                            "value": 12
+                          },
+                          "V26": {
+                            "description": "Set threshold to 2.6 V",
+                            "value": 13
+                          },
+                          "V27": {
+                            "description": "Set threshold to 2.7 V",
+                            "value": 14
+                          },
+                          "V28": {
+                            "description": "Set threshold to 2.8 V",
+                            "value": 15
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPREGRET": {
+              "description": "General purpose retention register",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPREGRET": {
+                    "description": "General purpose retention register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "GPREGRET2": {
+              "description": "General purpose retention register",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPREGRET": {
+                    "description": "General purpose retention register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RAMON": {
+              "description": "Deprecated register -  RAM on/off register (this register is retained)",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ONRAM0": {
+                    "description": "Keep RAM block 0 on or off in system ON Mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RAM0Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "RAM0On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ONRAM1": {
+                    "description": "Keep RAM block 1 on or off in system ON Mode",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RAM1Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "RAM1On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OFFRAM0": {
+                    "description": "Keep retention on RAM block 0 when RAM block is switched off",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RAM0Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "RAM0On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OFFRAM1": {
+                    "description": "Keep retention on RAM block 1 when RAM block is switched off",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RAM1Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "RAM1On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RAMONB": {
+              "description": "Deprecated register -  RAM on/off register (this register is retained)",
+              "offset": 1364,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ONRAM2": {
+                    "description": "Keep RAM block 2 on or off in system ON Mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RAM2Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "RAM2On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ONRAM3": {
+                    "description": "Keep RAM block 3 on or off in system ON Mode",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RAM3Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "RAM3On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OFFRAM2": {
+                    "description": "Keep retention on RAM block 2 when RAM block is switched off",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RAM2Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "RAM2On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OFFRAM3": {
+                    "description": "Keep retention on RAM block 3 when RAM block is switched off",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RAM3Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "RAM3On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DCDCEN": {
+              "description": "DC/DC enable register",
+              "offset": 1400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCDCEN": {
+                    "description": "Enable or disable DC/DC converter",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CLOCK": {
+        "description": "Clock control",
+        "children": {
+          "registers": {
+            "TASKS_HFCLKSTART": {
+              "description": "Start HFCLK crystal oscillator",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_HFCLKSTOP": {
+              "description": "Stop HFCLK crystal oscillator",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_LFCLKSTART": {
+              "description": "Start LFCLK source",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_LFCLKSTOP": {
+              "description": "Stop LFCLK source",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_CAL": {
+              "description": "Start calibration of LFRC oscillator",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_CTSTART": {
+              "description": "Start calibration timer",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_CTSTOP": {
+              "description": "Stop calibration timer",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_HFCLKSTARTED": {
+              "description": "HFCLK oscillator started",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_LFCLKSTARTED": {
+              "description": "LFCLK started",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_DONE": {
+              "description": "Calibration of LFCLK RC oscillator complete event",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_CTTO": {
+              "description": "Calibration timer timeout",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HFCLKSTARTED": {
+                    "description": "Write '1' to Enable interrupt for HFCLKSTARTED event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LFCLKSTARTED": {
+                    "description": "Write '1' to Enable interrupt for LFCLKSTARTED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DONE": {
+                    "description": "Write '1' to Enable interrupt for DONE event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CTTO": {
+                    "description": "Write '1' to Enable interrupt for CTTO event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HFCLKSTARTED": {
+                    "description": "Write '1' to Disable interrupt for HFCLKSTARTED event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LFCLKSTARTED": {
+                    "description": "Write '1' to Disable interrupt for LFCLKSTARTED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DONE": {
+                    "description": "Write '1' to Disable interrupt for DONE event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CTTO": {
+                    "description": "Write '1' to Disable interrupt for CTTO event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "HFCLKRUN": {
+              "description": "Status indicating that HFCLKSTART task has been triggered",
+              "offset": 1032,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STATUS": {
+                    "description": "HFCLKSTART task triggered or not",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotTriggered": {
+                            "description": "Task not triggered",
+                            "value": 0
+                          },
+                          "Triggered": {
+                            "description": "Task triggered",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "HFCLKSTAT": {
+              "description": "HFCLK status",
+              "offset": 1036,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SRC": {
+                    "description": "Source of HFCLK",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RC": {
+                            "description": "64 MHz internal oscillator (HFINT)",
+                            "value": 0
+                          },
+                          "Xtal": {
+                            "description": "64 MHz crystal oscillator (HFXO)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STATE": {
+                    "description": "HFCLK state",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotRunning": {
+                            "description": "HFCLK not running",
+                            "value": 0
+                          },
+                          "Running": {
+                            "description": "HFCLK running",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LFCLKRUN": {
+              "description": "Status indicating that LFCLKSTART task has been triggered",
+              "offset": 1044,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STATUS": {
+                    "description": "LFCLKSTART task triggered or not",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotTriggered": {
+                            "description": "Task not triggered",
+                            "value": 0
+                          },
+                          "Triggered": {
+                            "description": "Task triggered",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LFCLKSTAT": {
+              "description": "LFCLK status",
+              "offset": 1048,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SRC": {
+                    "description": "Source of LFCLK",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "RC": {
+                            "description": "32.768 kHz RC oscillator",
+                            "value": 0
+                          },
+                          "Xtal": {
+                            "description": "32.768 kHz crystal oscillator",
+                            "value": 1
+                          },
+                          "Synth": {
+                            "description": "32.768 kHz synthesized from HFCLK",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STATE": {
+                    "description": "LFCLK state",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotRunning": {
+                            "description": "LFCLK not running",
+                            "value": 0
+                          },
+                          "Running": {
+                            "description": "LFCLK running",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LFCLKSRCCOPY": {
+              "description": "Copy of LFCLKSRC register, set when LFCLKSTART task was triggered",
+              "offset": 1052,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SRC": {
+                    "description": "Clock source",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "RC": {
+                            "description": "32.768 kHz RC oscillator",
+                            "value": 0
+                          },
+                          "Xtal": {
+                            "description": "32.768 kHz crystal oscillator",
+                            "value": 1
+                          },
+                          "Synth": {
+                            "description": "32.768 kHz synthesized from HFCLK",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LFCLKSRC": {
+              "description": "Clock source for the LFCLK",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRC": {
+                    "description": "Clock source",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "RC": {
+                            "description": "32.768 kHz RC oscillator",
+                            "value": 0
+                          },
+                          "Xtal": {
+                            "description": "32.768 kHz crystal oscillator",
+                            "value": 1
+                          },
+                          "Synth": {
+                            "description": "32.768 kHz synthesized from HFCLK",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BYPASS": {
+                    "description": "Enable or disable bypass of LFCLK crystal oscillator with external clock source",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable (use with Xtal or low-swing external source)",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable (use with rail-to-rail external source)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EXTERNAL": {
+                    "description": "Enable or disable external source for LFCLK",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable external source (use with Xtal)",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable use of external source instead of Xtal (SRC needs to be set to Xtal)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CTIV": {
+              "description": "Calibration timer interval",
+              "offset": 1336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTIV": {
+                    "description": "Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "TRACECONFIG": {
+              "description": "Clocking options for the Trace Port debug interface",
+              "offset": 1372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRACEPORTSPEED": {
+                    "description": "Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "32MHz": {
+                            "description": "32 MHz Trace Port clock (TRACECLK = 16 MHz)",
+                            "value": 0
+                          },
+                          "16MHz": {
+                            "description": "16 MHz Trace Port clock (TRACECLK = 8 MHz)",
+                            "value": 1
+                          },
+                          "8MHz": {
+                            "description": "8 MHz Trace Port clock (TRACECLK = 4 MHz)",
+                            "value": 2
+                          },
+                          "4MHz": {
+                            "description": "4 MHz Trace Port clock (TRACECLK = 2 MHz)",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRACEMUX": {
+                    "description": "Pin multiplexing of trace signals.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO": {
+                            "description": "GPIOs multiplexed onto all trace-pins",
+                            "value": 0
+                          },
+                          "Serial": {
+                            "description": "SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins",
+                            "value": 1
+                          },
+                          "Parallel": {
+                            "description": "TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14.",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RADIO": {
+        "description": "2.4 GHz Radio",
+        "children": {
+          "registers": {
+            "TASKS_TXEN": {
+              "description": "Enable RADIO in TX mode",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_RXEN": {
+              "description": "Enable RADIO in RX mode",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_START": {
+              "description": "Start RADIO",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop RADIO",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_DISABLE": {
+              "description": "Disable RADIO",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_RSSISTART": {
+              "description": "Start the RSSI and take one single sample of the receive signal strength.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_RSSISTOP": {
+              "description": "Stop the RSSI measurement",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_BCSTART": {
+              "description": "Start the bit counter",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_BCSTOP": {
+              "description": "Stop the bit counter",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_READY": {
+              "description": "RADIO has ramped up and is ready to be started",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ADDRESS": {
+              "description": "Address sent or received",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_PAYLOAD": {
+              "description": "Packet payload sent or received",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_END": {
+              "description": "Packet sent or received",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_DISABLED": {
+              "description": "RADIO has been disabled",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_DEVMATCH": {
+              "description": "A device address match occurred on the last received packet",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_DEVMISS": {
+              "description": "No device address match occurred on the last received packet",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RSSIEND": {
+              "description": "Sampling of receive signal strength complete.",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_BCMATCH": {
+              "description": "Bit counter reached bit count value.",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_CRCOK": {
+              "description": "Packet received with CRC ok",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_CRCERROR": {
+              "description": "Packet received with CRC error",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY_START": {
+                    "description": "Shortcut between READY event and START task",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END_DISABLE": {
+                    "description": "Shortcut between END event and DISABLE task",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISABLED_TXEN": {
+                    "description": "Shortcut between DISABLED event and TXEN task",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISABLED_RXEN": {
+                    "description": "Shortcut between DISABLED event and RXEN task",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDRESS_RSSISTART": {
+                    "description": "Shortcut between ADDRESS event and RSSISTART task",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END_START": {
+                    "description": "Shortcut between END event and START task",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDRESS_BCSTART": {
+                    "description": "Shortcut between ADDRESS event and BCSTART task",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISABLED_RSSISTOP": {
+                    "description": "Shortcut between DISABLED event and RSSISTOP task",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to Enable interrupt for READY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDRESS": {
+                    "description": "Write '1' to Enable interrupt for ADDRESS event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PAYLOAD": {
+                    "description": "Write '1' to Enable interrupt for PAYLOAD event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to Enable interrupt for END event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISABLED": {
+                    "description": "Write '1' to Enable interrupt for DISABLED event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DEVMATCH": {
+                    "description": "Write '1' to Enable interrupt for DEVMATCH event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DEVMISS": {
+                    "description": "Write '1' to Enable interrupt for DEVMISS event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RSSIEND": {
+                    "description": "Write '1' to Enable interrupt for RSSIEND event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BCMATCH": {
+                    "description": "Write '1' to Enable interrupt for BCMATCH event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CRCOK": {
+                    "description": "Write '1' to Enable interrupt for CRCOK event",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CRCERROR": {
+                    "description": "Write '1' to Enable interrupt for CRCERROR event",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to Disable interrupt for READY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDRESS": {
+                    "description": "Write '1' to Disable interrupt for ADDRESS event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PAYLOAD": {
+                    "description": "Write '1' to Disable interrupt for PAYLOAD event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to Disable interrupt for END event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISABLED": {
+                    "description": "Write '1' to Disable interrupt for DISABLED event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DEVMATCH": {
+                    "description": "Write '1' to Disable interrupt for DEVMATCH event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DEVMISS": {
+                    "description": "Write '1' to Disable interrupt for DEVMISS event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RSSIEND": {
+                    "description": "Write '1' to Disable interrupt for RSSIEND event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BCMATCH": {
+                    "description": "Write '1' to Disable interrupt for BCMATCH event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CRCOK": {
+                    "description": "Write '1' to Disable interrupt for CRCOK event",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CRCERROR": {
+                    "description": "Write '1' to Disable interrupt for CRCERROR event",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CRCSTATUS": {
+              "description": "CRC status",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CRCSTATUS": {
+                    "description": "CRC status of packet received",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "CRCError": {
+                            "description": "Packet received with CRC error",
+                            "value": 0
+                          },
+                          "CRCOk": {
+                            "description": "Packet received with CRC ok",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RXMATCH": {
+              "description": "Received address",
+              "offset": 1032,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXMATCH": {
+                    "description": "Received address",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "RXCRC": {
+              "description": "CRC field of previously received packet",
+              "offset": 1036,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXCRC": {
+                    "description": "CRC field of previously received packet",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "DAI": {
+              "description": "Device address match index",
+              "offset": 1040,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DAI": {
+                    "description": "Device address match index",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "PACKETPTR": {
+              "description": "Packet pointer",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PACKETPTR": {
+                    "description": "Packet pointer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FREQUENCY": {
+              "description": "Frequency",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQUENCY": {
+                    "description": "Radio channel frequency",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "MAP": {
+                    "description": "Channel map selection.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Default": {
+                            "description": "Channel map between 2400 MHZ .. 2500 MHz",
+                            "value": 0
+                          },
+                          "Low": {
+                            "description": "Channel map between 2360 MHZ .. 2460 MHz",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TXPOWER": {
+              "description": "Output power",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXPOWER": {
+                    "description": "RADIO output power.",
+                    "offset": 0,
+                    "size": 8,
+                    "enum": {
+                      "size": 8,
+                      "children": {
+                        "enum_fields": {
+                          "Pos4dBm": {
+                            "description": "+4 dBm",
+                            "value": 4
+                          },
+                          "Pos3dBm": {
+                            "description": "+3 dBm",
+                            "value": 3
+                          },
+                          "0dBm": {
+                            "description": "0 dBm",
+                            "value": 0
+                          },
+                          "Neg4dBm": {
+                            "description": "-4 dBm",
+                            "value": 252
+                          },
+                          "Neg8dBm": {
+                            "description": "-8 dBm",
+                            "value": 248
+                          },
+                          "Neg12dBm": {
+                            "description": "-12 dBm",
+                            "value": 244
+                          },
+                          "Neg16dBm": {
+                            "description": "-16 dBm",
+                            "value": 240
+                          },
+                          "Neg20dBm": {
+                            "description": "-20 dBm",
+                            "value": 236
+                          },
+                          "Neg30dBm": {
+                            "description": "Deprecated enumerator -  -40 dBm",
+                            "value": 255
+                          },
+                          "Neg40dBm": {
+                            "description": "-40 dBm",
+                            "value": 216
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Data rate and modulation",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation.",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Nrf_1Mbit": {
+                            "description": "1 Mbit/s Nordic proprietary radio mode",
+                            "value": 0
+                          },
+                          "Nrf_2Mbit": {
+                            "description": "2 Mbit/s Nordic proprietary radio mode",
+                            "value": 1
+                          },
+                          "Nrf_250Kbit": {
+                            "description": "Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode",
+                            "value": 2
+                          },
+                          "Ble_1Mbit": {
+                            "description": "1 Mbit/s Bluetooth Low Energy",
+                            "value": 3
+                          },
+                          "Ble_2Mbit": {
+                            "description": "2 Mbit/s Bluetooth Low Energy",
+                            "value": 4
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PCNF0": {
+              "description": "Packet configuration register 0",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LFLEN": {
+                    "description": "Length on air of LENGTH field in number of bits.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "S0LEN": {
+                    "description": "Length on air of S0 field in number of bytes.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "S1LEN": {
+                    "description": "Length on air of S1 field in number of bits.",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "S1INCL": {
+                    "description": "Include or exclude S1 field in RAM",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Automatic": {
+                            "description": "Include S1 field in RAM only if S1LEN > 0",
+                            "value": 0
+                          },
+                          "Include": {
+                            "description": "Always include S1 field in RAM independent of S1LEN",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PLEN": {
+                    "description": "Length of preamble on air. Decision point: TASKS_START task",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "8bit": {
+                            "description": "8-bit preamble",
+                            "value": 0
+                          },
+                          "16bit": {
+                            "description": "16-bit preamble",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PCNF1": {
+              "description": "Packet configuration register 1",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAXLEN": {
+                    "description": "Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "STATLEN": {
+                    "description": "Static length in number of bytes",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BALEN": {
+                    "description": "Base address length in number of bytes",
+                    "offset": 16,
+                    "size": 3
+                  },
+                  "ENDIAN": {
+                    "description": "On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Little": {
+                            "description": "Least Significant bit on air first",
+                            "value": 0
+                          },
+                          "Big": {
+                            "description": "Most significant bit on air first",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WHITEEN": {
+                    "description": "Enable or disable packet whitening",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "BASE0": {
+              "description": "Base address 0",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BASE0": {
+                    "description": "Base address 0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BASE1": {
+              "description": "Base address 1",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BASE1": {
+                    "description": "Base address 1",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PREFIX0": {
+              "description": "Prefixes bytes for logical addresses 0-3",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AP0": {
+                    "description": "Address prefix 0.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "AP1": {
+                    "description": "Address prefix 1.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "AP2": {
+                    "description": "Address prefix 2.",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "AP3": {
+                    "description": "Address prefix 3.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PREFIX1": {
+              "description": "Prefixes bytes for logical addresses 4-7",
+              "offset": 1320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AP4": {
+                    "description": "Address prefix 4.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "AP5": {
+                    "description": "Address prefix 5.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "AP6": {
+                    "description": "Address prefix 6.",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "AP7": {
+                    "description": "Address prefix 7.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXADDRESS": {
+              "description": "Transmit address select",
+              "offset": 1324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXADDRESS": {
+                    "description": "Transmit address select",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "RXADDRESSES": {
+              "description": "Receive address select",
+              "offset": 1328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDR0": {
+                    "description": "Enable or disable reception on logical address 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR1": {
+                    "description": "Enable or disable reception on logical address 1.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR2": {
+                    "description": "Enable or disable reception on logical address 2.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR3": {
+                    "description": "Enable or disable reception on logical address 3.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR4": {
+                    "description": "Enable or disable reception on logical address 4.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR5": {
+                    "description": "Enable or disable reception on logical address 5.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR6": {
+                    "description": "Enable or disable reception on logical address 6.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR7": {
+                    "description": "Enable or disable reception on logical address 7.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CRCCNF": {
+              "description": "CRC configuration",
+              "offset": 1332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEN": {
+                    "description": "CRC length in number of bytes.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "CRC length is zero and CRC calculation is disabled",
+                            "value": 0
+                          },
+                          "One": {
+                            "description": "CRC length is one byte and CRC calculation is enabled",
+                            "value": 1
+                          },
+                          "Two": {
+                            "description": "CRC length is two bytes and CRC calculation is enabled",
+                            "value": 2
+                          },
+                          "Three": {
+                            "description": "CRC length is three bytes and CRC calculation is enabled",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SKIPADDR": {
+                    "description": "Include or exclude packet address field out of CRC calculation.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Include": {
+                            "description": "CRC calculation includes address field",
+                            "value": 0
+                          },
+                          "Skip": {
+                            "description": "CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CRCPOLY": {
+              "description": "CRC polynomial",
+              "offset": 1336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRCPOLY": {
+                    "description": "CRC polynomial",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "CRCINIT": {
+              "description": "CRC initial value",
+              "offset": 1340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRCINIT": {
+                    "description": "CRC initial value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "UNUSED0": {
+              "description": "Unspecified",
+              "offset": 1344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "TIFS": {
+              "description": "Inter Frame Spacing in us",
+              "offset": 1348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIFS": {
+                    "description": "Inter Frame Spacing in us",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RSSISAMPLE": {
+              "description": "RSSI sample",
+              "offset": 1352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RSSISAMPLE": {
+                    "description": "RSSI sample",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "STATE": {
+              "description": "Current radio state",
+              "offset": 1360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STATE": {
+                    "description": "Current radio state",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "RADIO is in the Disabled state",
+                            "value": 0
+                          },
+                          "RxRu": {
+                            "description": "RADIO is in the RXRU state",
+                            "value": 1
+                          },
+                          "RxIdle": {
+                            "description": "RADIO is in the RXIDLE state",
+                            "value": 2
+                          },
+                          "Rx": {
+                            "description": "RADIO is in the RX state",
+                            "value": 3
+                          },
+                          "RxDisable": {
+                            "description": "RADIO is in the RXDISABLED state",
+                            "value": 4
+                          },
+                          "TxRu": {
+                            "description": "RADIO is in the TXRU state",
+                            "value": 9
+                          },
+                          "TxIdle": {
+                            "description": "RADIO is in the TXIDLE state",
+                            "value": 10
+                          },
+                          "Tx": {
+                            "description": "RADIO is in the TX state",
+                            "value": 11
+                          },
+                          "TxDisable": {
+                            "description": "RADIO is in the TXDISABLED state",
+                            "value": 12
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DATAWHITEIV": {
+              "description": "Data whitening initial value",
+              "offset": 1364,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATAWHITEIV": {
+                    "description": "Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "BCC": {
+              "description": "Bit counter compare",
+              "offset": 1376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BCC": {
+                    "description": "Bit counter compare",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DAB": {
+              "description": "Description collection[0]:  Device address base segment 0",
+              "offset": 1536,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAB": {
+                    "description": "Device address base segment 0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DAP": {
+              "description": "Description collection[0]:  Device address prefix 0",
+              "offset": 1568,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAP": {
+                    "description": "Device address prefix 0",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DACNF": {
+              "description": "Device address match configuration",
+              "offset": 1600,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENA0": {
+                    "description": "Enable or disable device address matching using device address 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA1": {
+                    "description": "Enable or disable device address matching using device address 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA2": {
+                    "description": "Enable or disable device address matching using device address 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA3": {
+                    "description": "Enable or disable device address matching using device address 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA4": {
+                    "description": "Enable or disable device address matching using device address 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA5": {
+                    "description": "Enable or disable device address matching using device address 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA6": {
+                    "description": "Enable or disable device address matching using device address 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA7": {
+                    "description": "Enable or disable device address matching using device address 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXADD0": {
+                    "description": "TxAdd for device address 0",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXADD1": {
+                    "description": "TxAdd for device address 1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TXADD2": {
+                    "description": "TxAdd for device address 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TXADD3": {
+                    "description": "TxAdd for device address 3",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TXADD4": {
+                    "description": "TxAdd for device address 4",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TXADD5": {
+                    "description": "TxAdd for device address 5",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TXADD6": {
+                    "description": "TxAdd for device address 6",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TXADD7": {
+                    "description": "TxAdd for device address 7",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MODECNF0": {
+              "description": "Radio mode configuration register 0",
+              "offset": 1616,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RU": {
+                    "description": "Radio ramp-up time",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Default": {
+                            "description": "Default ramp-up time (tRXEN), compatible with firmware written for nRF51",
+                            "value": 0
+                          },
+                          "Fast": {
+                            "description": "Fast ramp-up (tRXEN,FAST), see electrical specification for more information",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DTX": {
+                    "description": "Default TX value",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "B1": {
+                            "description": "Transmit '1'",
+                            "value": 0
+                          },
+                          "B0": {
+                            "description": "Transmit '0'",
+                            "value": 1
+                          },
+                          "Center": {
+                            "description": "Transmit center frequency",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "POWER": {
+              "description": "Peripheral power control",
+              "offset": 4092,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POWER": {
+                    "description": "Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Peripheral is powered off",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Peripheral is powered on",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UARTE0": {
+        "description": "UART with EasyDMA",
+        "children": {
+          "registers": {
+            "TASKS_STARTRX": {
+              "description": "Start UART receiver",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOPRX": {
+              "description": "Stop UART receiver",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STARTTX": {
+              "description": "Start UART transmitter",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOPTX": {
+              "description": "Stop UART transmitter",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_FLUSHRX": {
+              "description": "Flush RX FIFO into RX buffer",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_CTS": {
+              "description": "CTS is activated (set low). Clear To Send.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_NCTS": {
+              "description": "CTS is deactivated (set high). Not Clear To Send.",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RXDRDY": {
+              "description": "Data received in RXD (but potentially not yet transferred to Data RAM)",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ENDRX": {
+              "description": "Receive buffer is filled up",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_TXDRDY": {
+              "description": "Data sent from TXD",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ENDTX": {
+              "description": "Last TX byte transmitted",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ERROR": {
+              "description": "Error detected",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RXTO": {
+              "description": "Receiver timeout",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RXSTARTED": {
+              "description": "UART receiver has started",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_TXSTARTED": {
+              "description": "UART transmitter has started",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_TXSTOPPED": {
+              "description": "Transmitter stopped",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDRX_STARTRX": {
+                    "description": "Shortcut between ENDRX event and STARTRX task",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX_STOPRX": {
+                    "description": "Shortcut between ENDRX event and STOPRX task",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "Enable or disable interrupt for CTS event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS": {
+                    "description": "Enable or disable interrupt for NCTS event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDRDY": {
+                    "description": "Enable or disable interrupt for RXDRDY event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Enable or disable interrupt for ENDRX event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDRDY": {
+                    "description": "Enable or disable interrupt for TXDRDY event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Enable or disable interrupt for ENDTX event",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Enable or disable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXTO": {
+                    "description": "Enable or disable interrupt for RXTO event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Enable or disable interrupt for RXSTARTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Enable or disable interrupt for TXSTARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTOPPED": {
+                    "description": "Enable or disable interrupt for TXSTOPPED event",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "Write '1' to Enable interrupt for CTS event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS": {
+                    "description": "Write '1' to Enable interrupt for NCTS event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDRDY": {
+                    "description": "Write '1' to Enable interrupt for RXDRDY event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to Enable interrupt for ENDRX event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDRDY": {
+                    "description": "Write '1' to Enable interrupt for TXDRDY event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to Enable interrupt for ENDTX event",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Enable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXTO": {
+                    "description": "Write '1' to Enable interrupt for RXTO event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to Enable interrupt for RXSTARTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to Enable interrupt for TXSTARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTOPPED": {
+                    "description": "Write '1' to Enable interrupt for TXSTOPPED event",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "Write '1' to Disable interrupt for CTS event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS": {
+                    "description": "Write '1' to Disable interrupt for NCTS event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDRDY": {
+                    "description": "Write '1' to Disable interrupt for RXDRDY event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to Disable interrupt for ENDRX event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDRDY": {
+                    "description": "Write '1' to Disable interrupt for TXDRDY event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to Disable interrupt for ENDTX event",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Disable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXTO": {
+                    "description": "Write '1' to Disable interrupt for RXTO event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to Disable interrupt for RXSTARTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to Disable interrupt for TXSTARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTOPPED": {
+                    "description": "Write '1' to Disable interrupt for TXSTOPPED event",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSRC": {
+              "description": "Error source",
+              "offset": 1152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERRUN": {
+                    "description": "Overrun error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PARITY": {
+                    "description": "Parity error",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FRAMING": {
+                    "description": "Framing error occurred",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BREAK": {
+                    "description": "Break condition",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable UART",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable UARTE",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable UARTE",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable UARTE",
+                            "value": 8
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "BAUDRATE": {
+              "description": "Baud rate. Accuracy depends on the HFCLK source selected.",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BAUDRATE": {
+                    "description": "Baud rate",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Baud1200": {
+                            "description": "1200 baud (actual rate: 1205)",
+                            "value": 323584
+                          },
+                          "Baud2400": {
+                            "description": "2400 baud (actual rate: 2396)",
+                            "value": 643072
+                          },
+                          "Baud4800": {
+                            "description": "4800 baud (actual rate: 4808)",
+                            "value": 1290240
+                          },
+                          "Baud9600": {
+                            "description": "9600 baud (actual rate: 9598)",
+                            "value": 2576384
+                          },
+                          "Baud14400": {
+                            "description": "14400 baud (actual rate: 14401)",
+                            "value": 3862528
+                          },
+                          "Baud19200": {
+                            "description": "19200 baud (actual rate: 19208)",
+                            "value": 5152768
+                          },
+                          "Baud28800": {
+                            "description": "28800 baud (actual rate: 28777)",
+                            "value": 7716864
+                          },
+                          "Baud31250": {
+                            "description": "31250 baud",
+                            "value": 8388608
+                          },
+                          "Baud38400": {
+                            "description": "38400 baud (actual rate: 38369)",
+                            "value": 10289152
+                          },
+                          "Baud56000": {
+                            "description": "56000 baud (actual rate: 55944)",
+                            "value": 15007744
+                          },
+                          "Baud57600": {
+                            "description": "57600 baud (actual rate: 57554)",
+                            "value": 15400960
+                          },
+                          "Baud76800": {
+                            "description": "76800 baud (actual rate: 76923)",
+                            "value": 20615168
+                          },
+                          "Baud115200": {
+                            "description": "115200 baud (actual rate: 115108)",
+                            "value": 30801920
+                          },
+                          "Baud230400": {
+                            "description": "230400 baud (actual rate: 231884)",
+                            "value": 61865984
+                          },
+                          "Baud250000": {
+                            "description": "250000 baud",
+                            "value": 67108864
+                          },
+                          "Baud460800": {
+                            "description": "460800 baud (actual rate: 457143)",
+                            "value": 121634816
+                          },
+                          "Baud921600": {
+                            "description": "921600 baud (actual rate: 941176)",
+                            "value": 251658240
+                          },
+                          "Baud1M": {
+                            "description": "1Mega baud",
+                            "value": 268435456
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration of parity and hardware flow control",
+              "offset": 1388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HWFC": {
+                    "description": "Hardware flow control",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PARITY": {
+                    "description": "Parity",
+                    "offset": 1,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude parity bit",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include parity bit",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UART0": {
+        "description": "Universal Asynchronous Receiver/Transmitter",
+        "children": {
+          "registers": {
+            "TASKS_STARTRX": {
+              "description": "Start UART receiver",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOPRX": {
+              "description": "Stop UART receiver",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STARTTX": {
+              "description": "Start UART transmitter",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOPTX": {
+              "description": "Stop UART transmitter",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SUSPEND": {
+              "description": "Suspend UART",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_CTS": {
+              "description": "CTS is activated (set low). Clear To Send.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_NCTS": {
+              "description": "CTS is deactivated (set high). Not Clear To Send.",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RXDRDY": {
+              "description": "Data received in RXD",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_TXDRDY": {
+              "description": "Data sent from TXD",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ERROR": {
+              "description": "Error detected",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RXTO": {
+              "description": "Receiver timeout",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS_STARTRX": {
+                    "description": "Shortcut between CTS event and STARTRX task",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS_STOPRX": {
+                    "description": "Shortcut between NCTS event and STOPRX task",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "Write '1' to Enable interrupt for CTS event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS": {
+                    "description": "Write '1' to Enable interrupt for NCTS event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDRDY": {
+                    "description": "Write '1' to Enable interrupt for RXDRDY event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDRDY": {
+                    "description": "Write '1' to Enable interrupt for TXDRDY event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Enable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXTO": {
+                    "description": "Write '1' to Enable interrupt for RXTO event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "Write '1' to Disable interrupt for CTS event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS": {
+                    "description": "Write '1' to Disable interrupt for NCTS event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDRDY": {
+                    "description": "Write '1' to Disable interrupt for RXDRDY event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDRDY": {
+                    "description": "Write '1' to Disable interrupt for TXDRDY event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Disable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXTO": {
+                    "description": "Write '1' to Disable interrupt for RXTO event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSRC": {
+              "description": "Error source",
+              "offset": 1152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERRUN": {
+                    "description": "Overrun error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PARITY": {
+                    "description": "Parity error",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FRAMING": {
+                    "description": "Framing error occurred",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BREAK": {
+                    "description": "Break condition",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable UART",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable UART",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable UART",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable UART",
+                            "value": 4
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PSELRTS": {
+              "description": "Pin select for RTS",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSELRTS": {
+                    "description": "Pin number configuration for UART RTS signal",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Disconnected": {
+                            "description": "Disconnect",
+                            "value": 4294967295
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PSELTXD": {
+              "description": "Pin select for TXD",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSELTXD": {
+                    "description": "Pin number configuration for UART TXD signal",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Disconnected": {
+                            "description": "Disconnect",
+                            "value": 4294967295
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PSELCTS": {
+              "description": "Pin select for CTS",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSELCTS": {
+                    "description": "Pin number configuration for UART CTS signal",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Disconnected": {
+                            "description": "Disconnect",
+                            "value": 4294967295
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PSELRXD": {
+              "description": "Pin select for RXD",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSELRXD": {
+                    "description": "Pin number configuration for UART RXD signal",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Disconnected": {
+                            "description": "Disconnect",
+                            "value": 4294967295
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RXD": {
+              "description": "RXD register",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXD": {
+                    "description": "RX data received in previous transfers, double buffered",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXD": {
+              "description": "TXD register",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TXD": {
+                    "description": "TX data to be transferred",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BAUDRATE": {
+              "description": "Baud rate",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BAUDRATE": {
+                    "description": "Baud rate",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Baud1200": {
+                            "description": "1200 baud (actual rate: 1205)",
+                            "value": 323584
+                          },
+                          "Baud2400": {
+                            "description": "2400 baud (actual rate: 2396)",
+                            "value": 643072
+                          },
+                          "Baud4800": {
+                            "description": "4800 baud (actual rate: 4808)",
+                            "value": 1290240
+                          },
+                          "Baud9600": {
+                            "description": "9600 baud (actual rate: 9598)",
+                            "value": 2576384
+                          },
+                          "Baud14400": {
+                            "description": "14400 baud (actual rate: 14414)",
+                            "value": 3866624
+                          },
+                          "Baud19200": {
+                            "description": "19200 baud (actual rate: 19208)",
+                            "value": 5152768
+                          },
+                          "Baud28800": {
+                            "description": "28800 baud (actual rate: 28829)",
+                            "value": 7729152
+                          },
+                          "Baud31250": {
+                            "description": "31250 baud",
+                            "value": 8388608
+                          },
+                          "Baud38400": {
+                            "description": "38400 baud (actual rate: 38462)",
+                            "value": 10309632
+                          },
+                          "Baud56000": {
+                            "description": "56000 baud (actual rate: 55944)",
+                            "value": 15007744
+                          },
+                          "Baud57600": {
+                            "description": "57600 baud (actual rate: 57762)",
+                            "value": 15462400
+                          },
+                          "Baud76800": {
+                            "description": "76800 baud (actual rate: 76923)",
+                            "value": 20615168
+                          },
+                          "Baud115200": {
+                            "description": "115200 baud (actual rate: 115942)",
+                            "value": 30924800
+                          },
+                          "Baud230400": {
+                            "description": "230400 baud (actual rate: 231884)",
+                            "value": 61845504
+                          },
+                          "Baud250000": {
+                            "description": "250000 baud",
+                            "value": 67108864
+                          },
+                          "Baud460800": {
+                            "description": "460800 baud (actual rate: 470588)",
+                            "value": 123695104
+                          },
+                          "Baud921600": {
+                            "description": "921600 baud (actual rate: 941176)",
+                            "value": 247386112
+                          },
+                          "Baud1M": {
+                            "description": "1Mega baud",
+                            "value": 268435456
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration of parity and hardware flow control",
+              "offset": 1388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HWFC": {
+                    "description": "Hardware flow control",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PARITY": {
+                    "description": "Parity",
+                    "offset": 1,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude parity bit",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include parity bit",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPIM0": {
+        "description": "Serial Peripheral Interface Master with EasyDMA 0",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start SPI transaction",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop SPI transaction",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SUSPEND": {
+              "description": "Suspend SPI transaction",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_RESUME": {
+              "description": "Resume SPI transaction",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_STOPPED": {
+              "description": "SPI transaction has stopped",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ENDRX": {
+              "description": "End of RXD buffer reached",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_END": {
+              "description": "End of RXD buffer and TXD buffer reached",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ENDTX": {
+              "description": "End of TXD buffer reached",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_STARTED": {
+              "description": "Transaction started",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END_START": {
+                    "description": "Shortcut between END event and START task",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to Enable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to Enable interrupt for ENDRX event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to Enable interrupt for END event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to Enable interrupt for ENDTX event",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Write '1' to Enable interrupt for STARTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to Disable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to Disable interrupt for ENDRX event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to Disable interrupt for END event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to Disable interrupt for ENDTX event",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Write '1' to Disable interrupt for STARTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable SPIM",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable SPIM",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable SPIM",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable SPIM",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FREQUENCY": {
+              "description": "SPI frequency. Accuracy depends on the HFCLK source selected.",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQUENCY": {
+                    "description": "SPI master data rate",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "K125": {
+                            "description": "125 kbps",
+                            "value": 33554432
+                          },
+                          "K250": {
+                            "description": "250 kbps",
+                            "value": 67108864
+                          },
+                          "K500": {
+                            "description": "500 kbps",
+                            "value": 134217728
+                          },
+                          "M1": {
+                            "description": "1 Mbps",
+                            "value": 268435456
+                          },
+                          "M2": {
+                            "description": "2 Mbps",
+                            "value": 536870912
+                          },
+                          "M4": {
+                            "description": "4 Mbps",
+                            "value": 1073741824
+                          },
+                          "M8": {
+                            "description": "8 Mbps",
+                            "value": 2147483648
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORDER": {
+                    "description": "Bit order",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MsbFirst": {
+                            "description": "Most significant bit shifted out first",
+                            "value": 0
+                          },
+                          "LsbFirst": {
+                            "description": "Least significant bit shifted out first",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPHA": {
+                    "description": "Serial clock (SCK) phase",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Leading": {
+                            "description": "Sample on leading edge of clock, shift serial data on trailing edge",
+                            "value": 0
+                          },
+                          "Trailing": {
+                            "description": "Sample on trailing edge of clock, shift serial data on leading edge",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPOL": {
+                    "description": "Serial clock (SCK) polarity",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ActiveHigh": {
+                            "description": "Active high",
+                            "value": 0
+                          },
+                          "ActiveLow": {
+                            "description": "Active low",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ORC": {
+              "description": "Over-read character. Character clocked out in case and over-read of the TXD buffer.",
+              "offset": 1472,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORC": {
+                    "description": "Over-read character. Character clocked out in case and over-read of the TXD buffer.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPIS0": {
+        "description": "SPI Slave 0",
+        "children": {
+          "registers": {
+            "TASKS_ACQUIRE": {
+              "description": "Acquire SPI semaphore",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_RELEASE": {
+              "description": "Release SPI semaphore, enabling the SPI slave to acquire it",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_END": {
+              "description": "Granted transaction completed",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ENDRX": {
+              "description": "End of RXD buffer reached",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ACQUIRED": {
+              "description": "Semaphore acquired",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END_ACQUIRE": {
+                    "description": "Shortcut between END event and ACQUIRE task",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END": {
+                    "description": "Write '1' to Enable interrupt for END event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to Enable interrupt for ENDRX event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ACQUIRED": {
+                    "description": "Write '1' to Enable interrupt for ACQUIRED event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END": {
+                    "description": "Write '1' to Disable interrupt for END event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to Disable interrupt for ENDRX event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ACQUIRED": {
+                    "description": "Write '1' to Disable interrupt for ACQUIRED event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SEMSTAT": {
+              "description": "Semaphore status register",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SEMSTAT": {
+                    "description": "Semaphore status",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Free": {
+                            "description": "Semaphore is free",
+                            "value": 0
+                          },
+                          "CPU": {
+                            "description": "Semaphore is assigned to CPU",
+                            "value": 1
+                          },
+                          "SPIS": {
+                            "description": "Semaphore is assigned to SPI slave",
+                            "value": 2
+                          },
+                          "CPUPending": {
+                            "description": "Semaphore is assigned to SPI but a handover to the CPU is pending",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Status from last transaction",
+              "offset": 1088,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERREAD": {
+                    "description": "TX buffer over-read detected, and prevented",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVERFLOW": {
+                    "description": "RX buffer overflow detected, and prevented",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable SPI slave",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable SPI slave",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable SPI slave",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable SPI slave",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORDER": {
+                    "description": "Bit order",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MsbFirst": {
+                            "description": "Most significant bit shifted out first",
+                            "value": 0
+                          },
+                          "LsbFirst": {
+                            "description": "Least significant bit shifted out first",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPHA": {
+                    "description": "Serial clock (SCK) phase",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Leading": {
+                            "description": "Sample on leading edge of clock, shift serial data on trailing edge",
+                            "value": 0
+                          },
+                          "Trailing": {
+                            "description": "Sample on trailing edge of clock, shift serial data on leading edge",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPOL": {
+                    "description": "Serial clock (SCK) polarity",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ActiveHigh": {
+                            "description": "Active high",
+                            "value": 0
+                          },
+                          "ActiveLow": {
+                            "description": "Active low",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DEF": {
+              "description": "Default character. Character clocked out in case of an ignored transaction.",
+              "offset": 1372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DEF": {
+                    "description": "Default character. Character clocked out in case of an ignored transaction.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ORC": {
+              "description": "Over-read character",
+              "offset": 1472,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORC": {
+                    "description": "Over-read character. Character clocked out after an over-read of the transmit buffer.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TWIM0": {
+        "description": "I2C compatible Two-Wire Master Interface with EasyDMA 0",
+        "children": {
+          "registers": {
+            "TASKS_STARTRX": {
+              "description": "Start TWI receive sequence",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STARTTX": {
+              "description": "Start TWI transmit sequence",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop TWI transaction. Must be issued while the TWI master is not suspended.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SUSPEND": {
+              "description": "Suspend TWI transaction",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_RESUME": {
+              "description": "Resume TWI transaction",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_STOPPED": {
+              "description": "TWI stopped",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ERROR": {
+              "description": "TWI error",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_SUSPENDED": {
+              "description": "Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RXSTARTED": {
+              "description": "Receive sequence started",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_TXSTARTED": {
+              "description": "Transmit sequence started",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_LASTRX": {
+              "description": "Byte boundary, starting to receive the last byte",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_LASTTX": {
+              "description": "Byte boundary, starting to transmit the last byte",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LASTTX_STARTRX": {
+                    "description": "Shortcut between LASTTX event and STARTRX task",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTTX_SUSPEND": {
+                    "description": "Shortcut between LASTTX event and SUSPEND task",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTTX_STOP": {
+                    "description": "Shortcut between LASTTX event and STOP task",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTRX_STARTTX": {
+                    "description": "Shortcut between LASTRX event and STARTTX task",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTRX_STOP": {
+                    "description": "Shortcut between LASTRX event and STOP task",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Enable or disable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SUSPENDED": {
+                    "description": "Enable or disable interrupt for SUSPENDED event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Enable or disable interrupt for RXSTARTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Enable or disable interrupt for TXSTARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTRX": {
+                    "description": "Enable or disable interrupt for LASTRX event",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTTX": {
+                    "description": "Enable or disable interrupt for LASTTX event",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to Enable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Enable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SUSPENDED": {
+                    "description": "Write '1' to Enable interrupt for SUSPENDED event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to Enable interrupt for RXSTARTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to Enable interrupt for TXSTARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTRX": {
+                    "description": "Write '1' to Enable interrupt for LASTRX event",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTTX": {
+                    "description": "Write '1' to Enable interrupt for LASTTX event",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to Disable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Disable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SUSPENDED": {
+                    "description": "Write '1' to Disable interrupt for SUSPENDED event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to Disable interrupt for RXSTARTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to Disable interrupt for TXSTARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTRX": {
+                    "description": "Write '1' to Disable interrupt for LASTRX event",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTTX": {
+                    "description": "Write '1' to Disable interrupt for LASTTX event",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSRC": {
+              "description": "Error source",
+              "offset": 1220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERRUN": {
+                    "description": "Overrun error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotReceived": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Received": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ANACK": {
+                    "description": "NACK received after sending the address (write '1' to clear)",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotReceived": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Received": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DNACK": {
+                    "description": "NACK received after sending a data byte (write '1' to clear)",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotReceived": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Received": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable TWIM",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable TWIM",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable TWIM",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable TWIM",
+                            "value": 6
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FREQUENCY": {
+              "description": "TWI frequency",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQUENCY": {
+                    "description": "TWI master clock frequency",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "K100": {
+                            "description": "100 kbps",
+                            "value": 26738688
+                          },
+                          "K250": {
+                            "description": "250 kbps",
+                            "value": 67108864
+                          },
+                          "K400": {
+                            "description": "400 kbps",
+                            "value": 104857600
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ADDRESS": {
+              "description": "Address used in the TWI transfer",
+              "offset": 1416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS": {
+                    "description": "Address used in the TWI transfer",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TWIS0": {
+        "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 0",
+        "children": {
+          "registers": {
+            "TASKS_STOP": {
+              "description": "Stop TWI transaction",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SUSPEND": {
+              "description": "Suspend TWI transaction",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_RESUME": {
+              "description": "Resume TWI transaction",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_PREPARERX": {
+              "description": "Prepare the TWI slave to respond to a write command",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_PREPARETX": {
+              "description": "Prepare the TWI slave to respond to a read command",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_STOPPED": {
+              "description": "TWI stopped",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ERROR": {
+              "description": "TWI error",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RXSTARTED": {
+              "description": "Receive sequence started",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_TXSTARTED": {
+              "description": "Transmit sequence started",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_WRITE": {
+              "description": "Write command received",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_READ": {
+              "description": "Read command received",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WRITE_SUSPEND": {
+                    "description": "Shortcut between WRITE event and SUSPEND task",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READ_SUSPEND": {
+                    "description": "Shortcut between READ event and SUSPEND task",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Enable or disable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Enable or disable interrupt for RXSTARTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Enable or disable interrupt for TXSTARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WRITE": {
+                    "description": "Enable or disable interrupt for WRITE event",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READ": {
+                    "description": "Enable or disable interrupt for READ event",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to Enable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Enable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to Enable interrupt for RXSTARTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to Enable interrupt for TXSTARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WRITE": {
+                    "description": "Write '1' to Enable interrupt for WRITE event",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READ": {
+                    "description": "Write '1' to Enable interrupt for READ event",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to Disable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Disable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to Disable interrupt for RXSTARTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to Disable interrupt for TXSTARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WRITE": {
+                    "description": "Write '1' to Disable interrupt for WRITE event",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READ": {
+                    "description": "Write '1' to Disable interrupt for READ event",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSRC": {
+              "description": "Error source",
+              "offset": 1232,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERFLOW": {
+                    "description": "RX buffer overflow detected, and prevented",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DNACK": {
+                    "description": "NACK sent after receiving a data byte",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotReceived": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Received": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVERREAD": {
+                    "description": "TX buffer over-read detected, and prevented",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MATCH": {
+              "description": "Status register indicating which address had a match",
+              "offset": 1236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "MATCH": {
+                    "description": "Which of the addresses in {ADDRESS} matched the incoming address",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable TWIS",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable TWIS",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable TWIS",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable TWIS",
+                            "value": 9
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ADDRESS": {
+              "description": "Description collection[0]:  TWI slave address 0",
+              "offset": 1416,
+              "size": 32,
+              "count": 2,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS": {
+                    "description": "TWI slave address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register for the address match mechanism",
+              "offset": 1428,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS0": {
+                    "description": "Enable or disable address matching on ADDRESS[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDRESS1": {
+                    "description": "Enable or disable address matching on ADDRESS[1]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ORC": {
+              "description": "Over-read character. Character sent out in case of an over-read of the transmit buffer.",
+              "offset": 1472,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORC": {
+                    "description": "Over-read character. Character sent out in case of an over-read of the transmit buffer.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI0": {
+        "description": "Serial Peripheral Interface 0",
+        "children": {
+          "registers": {
+            "EVENTS_READY": {
+              "description": "TXD byte sent and RXD byte received",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to Enable interrupt for READY event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to Disable interrupt for READY event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable SPI",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable SPI",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable SPI",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable SPI",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RXD": {
+              "description": "RXD register",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXD": {
+                    "description": "RX data received. Double buffered",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXD": {
+              "description": "TXD register",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXD": {
+                    "description": "TX data to send. Double buffered",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "FREQUENCY": {
+              "description": "SPI frequency",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQUENCY": {
+                    "description": "SPI master data rate",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "K125": {
+                            "description": "125 kbps",
+                            "value": 33554432
+                          },
+                          "K250": {
+                            "description": "250 kbps",
+                            "value": 67108864
+                          },
+                          "K500": {
+                            "description": "500 kbps",
+                            "value": 134217728
+                          },
+                          "M1": {
+                            "description": "1 Mbps",
+                            "value": 268435456
+                          },
+                          "M2": {
+                            "description": "2 Mbps",
+                            "value": 536870912
+                          },
+                          "M4": {
+                            "description": "4 Mbps",
+                            "value": 1073741824
+                          },
+                          "M8": {
+                            "description": "8 Mbps",
+                            "value": 2147483648
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORDER": {
+                    "description": "Bit order",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MsbFirst": {
+                            "description": "Most significant bit shifted out first",
+                            "value": 0
+                          },
+                          "LsbFirst": {
+                            "description": "Least significant bit shifted out first",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPHA": {
+                    "description": "Serial clock (SCK) phase",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Leading": {
+                            "description": "Sample on leading edge of clock, shift serial data on trailing edge",
+                            "value": 0
+                          },
+                          "Trailing": {
+                            "description": "Sample on trailing edge of clock, shift serial data on leading edge",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPOL": {
+                    "description": "Serial clock (SCK) polarity",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ActiveHigh": {
+                            "description": "Active high",
+                            "value": 0
+                          },
+                          "ActiveLow": {
+                            "description": "Active low",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TWI0": {
+        "description": "I2C compatible Two-Wire Interface 0",
+        "children": {
+          "registers": {
+            "TASKS_STARTRX": {
+              "description": "Start TWI receive sequence",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STARTTX": {
+              "description": "Start TWI transmit sequence",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop TWI transaction",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SUSPEND": {
+              "description": "Suspend TWI transaction",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_RESUME": {
+              "description": "Resume TWI transaction",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_STOPPED": {
+              "description": "TWI stopped",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RXDREADY": {
+              "description": "TWI RXD byte received",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_TXDSENT": {
+              "description": "TWI TXD byte sent",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ERROR": {
+              "description": "TWI error",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_BB": {
+              "description": "TWI byte boundary, generated before each byte that is sent or received",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_SUSPENDED": {
+              "description": "TWI entered the suspended state",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BB_SUSPEND": {
+                    "description": "Shortcut between BB event and SUSPEND task",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BB_STOP": {
+                    "description": "Shortcut between BB event and STOP task",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to Enable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDREADY": {
+                    "description": "Write '1' to Enable interrupt for RXDREADY event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDSENT": {
+                    "description": "Write '1' to Enable interrupt for TXDSENT event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Enable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BB": {
+                    "description": "Write '1' to Enable interrupt for BB event",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SUSPENDED": {
+                    "description": "Write '1' to Enable interrupt for SUSPENDED event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to Disable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDREADY": {
+                    "description": "Write '1' to Disable interrupt for RXDREADY event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDSENT": {
+                    "description": "Write '1' to Disable interrupt for TXDSENT event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Disable interrupt for ERROR event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BB": {
+                    "description": "Write '1' to Disable interrupt for BB event",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SUSPENDED": {
+                    "description": "Write '1' to Disable interrupt for SUSPENDED event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSRC": {
+              "description": "Error source",
+              "offset": 1220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERRUN": {
+                    "description": "Overrun error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: no overrun occured",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: overrun occured",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ANACK": {
+                    "description": "NACK received after sending the address (write '1' to clear)",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DNACK": {
+                    "description": "NACK received after sending a data byte (write '1' to clear)",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable TWI",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable TWI",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable TWI",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable TWI",
+                            "value": 5
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PSELSCL": {
+              "description": "Pin select for SCL",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSELSCL": {
+                    "description": "Pin number configuration for TWI SCL signal",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Disconnected": {
+                            "description": "Disconnect",
+                            "value": 4294967295
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PSELSDA": {
+              "description": "Pin select for SDA",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSELSDA": {
+                    "description": "Pin number configuration for TWI SDA signal",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Disconnected": {
+                            "description": "Disconnect",
+                            "value": 4294967295
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RXD": {
+              "description": "RXD register",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXD": {
+                    "description": "RXD register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXD": {
+              "description": "TXD register",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXD": {
+                    "description": "TXD register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "FREQUENCY": {
+              "description": "TWI frequency",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQUENCY": {
+                    "description": "TWI master clock frequency",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "K100": {
+                            "description": "100 kbps",
+                            "value": 26738688
+                          },
+                          "K250": {
+                            "description": "250 kbps",
+                            "value": 67108864
+                          },
+                          "K400": {
+                            "description": "400 kbps (actual rate 410.256 kbps)",
+                            "value": 107479040
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ADDRESS": {
+              "description": "Address used in the TWI transfer",
+              "offset": 1416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS": {
+                    "description": "Address used in the TWI transfer",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "P0": {
+        "description": "GPIO Port 1",
+        "children": {
+          "registers": {
+            "OUT": {
+              "description": "Write GPIO port",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "OUTSET": {
+              "description": "Set individual bits in GPIO port",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "OUTCLR": {
+              "description": "Clear individual bits in GPIO port",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IN": {
+              "description": "Read GPIO port",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DIR": {
+              "description": "Direction of GPIO pins",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DIRSET": {
+              "description": "DIR set register",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Set as output pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Set as output pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Set as output pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Set as output pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Set as output pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Set as output pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Set as output pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Set as output pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Set as output pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Set as output pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Set as output pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Set as output pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Set as output pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Set as output pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Set as output pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Set as output pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Set as output pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Set as output pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Set as output pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Set as output pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Set as output pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Set as output pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Set as output pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Set as output pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Set as output pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Set as output pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Set as output pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Set as output pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Set as output pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Set as output pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Set as output pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Set as output pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DIRCLR": {
+              "description": "DIR clear register",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Set as input pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Set as input pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Set as input pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Set as input pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Set as input pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Set as input pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Set as input pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Set as input pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Set as input pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Set as input pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Set as input pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Set as input pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Set as input pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Set as input pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Set as input pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Set as input pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Set as input pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Set as input pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Set as input pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Set as input pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Set as input pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Set as input pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Set as input pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Set as input pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Set as input pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Set as input pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Set as input pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Set as input pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Set as input pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Set as input pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Set as input pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Set as input pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LATCH": {
+              "description": "Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DETECTMODE": {
+              "description": "Select between default DETECT signal behaviour and LDETECT mode",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DETECTMODE": {
+                    "description": "Select between default DETECT signal behaviour and LDETECT mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Default": {
+                            "description": "DETECT directly connected to PIN DETECT signals",
+                            "value": 0
+                          },
+                          "LDETECT": {
+                            "description": "Use the latched LDETECT behaviour",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PIN_CNF": {
+              "description": "Description collection[0]:  Configuration of GPIO pins",
+              "offset": 1792,
+              "size": 32,
+              "count": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIR": {
+                    "description": "Pin direction. Same physical register as DIR register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Configure pin as an input pin",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Configure pin as an output pin",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INPUT": {
+                    "description": "Connect or disconnect input buffer",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Connect": {
+                            "description": "Connect input buffer",
+                            "value": 0
+                          },
+                          "Disconnect": {
+                            "description": "Disconnect input buffer",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PULL": {
+                    "description": "Pull configuration",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "No pull",
+                            "value": 0
+                          },
+                          "Pulldown": {
+                            "description": "Pull down on pin",
+                            "value": 1
+                          },
+                          "Pullup": {
+                            "description": "Pull up on pin",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DRIVE": {
+                    "description": "Drive configuration",
+                    "offset": 8,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "S0S1": {
+                            "description": "Standard '0', standard '1'",
+                            "value": 0
+                          },
+                          "H0S1": {
+                            "description": "High drive '0', standard '1'",
+                            "value": 1
+                          },
+                          "S0H1": {
+                            "description": "Standard '0', high drive '1'",
+                            "value": 2
+                          },
+                          "H0H1": {
+                            "description": "High drive '0', high 'drive '1''",
+                            "value": 3
+                          },
+                          "D0S1": {
+                            "description": "Disconnect '0' standard '1' (normally used for wired-or connections)",
+                            "value": 4
+                          },
+                          "D0H1": {
+                            "description": "Disconnect '0', high drive '1' (normally used for wired-or connections)",
+                            "value": 5
+                          },
+                          "S0D1": {
+                            "description": "Standard '0'. disconnect '1' (normally used for wired-and connections)",
+                            "value": 6
+                          },
+                          "H0D1": {
+                            "description": "High drive '0', disconnect '1' (normally used for wired-and connections)",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SENSE": {
+                    "description": "Pin sensing mechanism",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Sense for high level",
+                            "value": 2
+                          },
+                          "Low": {
+                            "description": "Sense for low level",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FPU": {
+        "description": "FPU",
+        "children": {
+          "registers": {
+            "UNUSED": {
+              "description": "Unused.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only"
+            }
+          }
+        }
+      },
+      "I2S": {
+        "description": "Inter-IC Sound",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Starts continuous I2S transfer. Also starts MCK generator when this is enabled.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_RXPTRUPD": {
+              "description": "The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_STOPPED": {
+              "description": "I2S transfer stopped.",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_TXPTRUPD": {
+              "description": "The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXPTRUPD": {
+                    "description": "Enable or disable interrupt for RXPTRUPD event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for STOPPED event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXPTRUPD": {
+                    "description": "Enable or disable interrupt for TXPTRUPD event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXPTRUPD": {
+                    "description": "Write '1' to Enable interrupt for RXPTRUPD event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to Enable interrupt for STOPPED event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXPTRUPD": {
+                    "description": "Write '1' to Enable interrupt for TXPTRUPD event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXPTRUPD": {
+                    "description": "Write '1' to Disable interrupt for RXPTRUPD event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to Disable interrupt for STOPPED event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXPTRUPD": {
+                    "description": "Write '1' to Disable interrupt for TXPTRUPD event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable I2S module.",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable I2S module.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EGU0": {
+        "description": "Event Generator Unit 0",
+        "children": {
+          "registers": {
+            "TASKS_TRIGGER": {
+              "description": "Description collection[0]:  Trigger 0 for triggering the corresponding TRIGGERED[0] event",
+              "offset": 0,
+              "size": 32,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_TRIGGERED": {
+              "description": "Description collection[0]:  Event number 0 generated by triggering the corresponding TRIGGER[0] task",
+              "offset": 256,
+              "size": 32,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRIGGERED0": {
+                    "description": "Enable or disable interrupt for TRIGGERED[0] event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED1": {
+                    "description": "Enable or disable interrupt for TRIGGERED[1] event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED2": {
+                    "description": "Enable or disable interrupt for TRIGGERED[2] event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED3": {
+                    "description": "Enable or disable interrupt for TRIGGERED[3] event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED4": {
+                    "description": "Enable or disable interrupt for TRIGGERED[4] event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED5": {
+                    "description": "Enable or disable interrupt for TRIGGERED[5] event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED6": {
+                    "description": "Enable or disable interrupt for TRIGGERED[6] event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED7": {
+                    "description": "Enable or disable interrupt for TRIGGERED[7] event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED8": {
+                    "description": "Enable or disable interrupt for TRIGGERED[8] event",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED9": {
+                    "description": "Enable or disable interrupt for TRIGGERED[9] event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED10": {
+                    "description": "Enable or disable interrupt for TRIGGERED[10] event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED11": {
+                    "description": "Enable or disable interrupt for TRIGGERED[11] event",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED12": {
+                    "description": "Enable or disable interrupt for TRIGGERED[12] event",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED13": {
+                    "description": "Enable or disable interrupt for TRIGGERED[13] event",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED14": {
+                    "description": "Enable or disable interrupt for TRIGGERED[14] event",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED15": {
+                    "description": "Enable or disable interrupt for TRIGGERED[15] event",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRIGGERED0": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[0] event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED1": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[1] event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED2": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[2] event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED3": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[3] event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED4": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[4] event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED5": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[5] event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED6": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[6] event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED7": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[7] event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED8": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[8] event",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED9": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[9] event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED10": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[10] event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED11": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[11] event",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED12": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[12] event",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED13": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[13] event",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED14": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[14] event",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED15": {
+                    "description": "Write '1' to Enable interrupt for TRIGGERED[15] event",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRIGGERED0": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[0] event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED1": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[1] event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED2": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[2] event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED3": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[3] event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED4": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[4] event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED5": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[5] event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED6": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[6] event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED7": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[7] event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED8": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[8] event",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED9": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[9] event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED10": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[10] event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED11": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[11] event",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED12": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[12] event",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED13": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[13] event",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED14": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[14] event",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED15": {
+                    "description": "Write '1' to Disable interrupt for TRIGGERED[15] event",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "MWU": {
+        "description": "Memory Watch Unit",
+        "children": {
+          "registers": {
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Enable or disable interrupt for REGION[0].WA event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Enable or disable interrupt for REGION[0].RA event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Enable or disable interrupt for REGION[1].WA event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Enable or disable interrupt for REGION[1].RA event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Enable or disable interrupt for REGION[2].WA event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Enable or disable interrupt for REGION[2].RA event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Enable or disable interrupt for REGION[3].WA event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Enable or disable interrupt for REGION[3].RA event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Enable or disable interrupt for PREGION[0].WA event",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Enable or disable interrupt for PREGION[0].RA event",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Enable or disable interrupt for PREGION[1].WA event",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Enable or disable interrupt for PREGION[1].RA event",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Write '1' to Enable interrupt for REGION[0].WA event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Write '1' to Enable interrupt for REGION[0].RA event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Write '1' to Enable interrupt for REGION[1].WA event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Write '1' to Enable interrupt for REGION[1].RA event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Write '1' to Enable interrupt for REGION[2].WA event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Write '1' to Enable interrupt for REGION[2].RA event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Write '1' to Enable interrupt for REGION[3].WA event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Write '1' to Enable interrupt for REGION[3].RA event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Write '1' to Enable interrupt for PREGION[0].WA event",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Write '1' to Enable interrupt for PREGION[0].RA event",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Write '1' to Enable interrupt for PREGION[1].WA event",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Write '1' to Enable interrupt for PREGION[1].RA event",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Write '1' to Disable interrupt for REGION[0].WA event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Write '1' to Disable interrupt for REGION[0].RA event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Write '1' to Disable interrupt for REGION[1].WA event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Write '1' to Disable interrupt for REGION[1].RA event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Write '1' to Disable interrupt for REGION[2].WA event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Write '1' to Disable interrupt for REGION[2].RA event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Write '1' to Disable interrupt for REGION[3].WA event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Write '1' to Disable interrupt for REGION[3].RA event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Write '1' to Disable interrupt for PREGION[0].WA event",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Write '1' to Disable interrupt for PREGION[0].RA event",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Write '1' to Disable interrupt for PREGION[1].WA event",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Write '1' to Disable interrupt for PREGION[1].RA event",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "NMIEN": {
+              "description": "Enable or disable non-maskable interrupt",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Enable or disable non-maskable interrupt for REGION[0].WA event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Enable or disable non-maskable interrupt for REGION[0].RA event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Enable or disable non-maskable interrupt for REGION[1].WA event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Enable or disable non-maskable interrupt for REGION[1].RA event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Enable or disable non-maskable interrupt for REGION[2].WA event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Enable or disable non-maskable interrupt for REGION[2].RA event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Enable or disable non-maskable interrupt for REGION[3].WA event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Enable or disable non-maskable interrupt for REGION[3].RA event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Enable or disable non-maskable interrupt for PREGION[0].WA event",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Enable or disable non-maskable interrupt for PREGION[0].RA event",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Enable or disable non-maskable interrupt for PREGION[1].WA event",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Enable or disable non-maskable interrupt for PREGION[1].RA event",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "NMIENSET": {
+              "description": "Enable non-maskable interrupt",
+              "offset": 804,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for REGION[0].WA event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for REGION[0].RA event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for REGION[1].WA event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for REGION[1].RA event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for REGION[2].WA event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for REGION[2].RA event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for REGION[3].WA event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for REGION[3].RA event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for PREGION[0].WA event",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for PREGION[0].RA event",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for PREGION[1].WA event",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Write '1' to Enable non-maskable interrupt for PREGION[1].RA event",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "NMIENCLR": {
+              "description": "Disable non-maskable interrupt",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for REGION[0].WA event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for REGION[0].RA event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for REGION[1].WA event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for REGION[1].RA event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for REGION[2].WA event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for REGION[2].RA event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for REGION[3].WA event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for REGION[3].RA event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for PREGION[0].WA event",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for PREGION[0].RA event",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for PREGION[1].WA event",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Write '1' to Disable non-maskable interrupt for PREGION[1].RA event",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REGIONEN": {
+              "description": "Enable/disable regions watch",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RGN0WA": {
+                    "description": "Enable/disable write access watch in region[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN0RA": {
+                    "description": "Enable/disable read access watch in region[0]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1WA": {
+                    "description": "Enable/disable write access watch in region[1]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1RA": {
+                    "description": "Enable/disable read access watch in region[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2WA": {
+                    "description": "Enable/disable write access watch in region[2]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2RA": {
+                    "description": "Enable/disable read access watch in region[2]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3WA": {
+                    "description": "Enable/disable write access watch in region[3]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3RA": {
+                    "description": "Enable/disable read access watch in region[3]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0WA": {
+                    "description": "Enable/disable write access watch in PREGION[0]",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this PREGION",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this PREGION",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0RA": {
+                    "description": "Enable/disable read access watch in PREGION[0]",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this PREGION",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this PREGION",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1WA": {
+                    "description": "Enable/disable write access watch in PREGION[1]",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this PREGION",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this PREGION",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1RA": {
+                    "description": "Enable/disable read access watch in PREGION[1]",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this PREGION",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this PREGION",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REGIONENSET": {
+              "description": "Enable regions watch",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RGN0WA": {
+                    "description": "Enable write access watch in region[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN0RA": {
+                    "description": "Enable read access watch in region[0]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1WA": {
+                    "description": "Enable write access watch in region[1]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1RA": {
+                    "description": "Enable read access watch in region[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2WA": {
+                    "description": "Enable write access watch in region[2]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2RA": {
+                    "description": "Enable read access watch in region[2]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3WA": {
+                    "description": "Enable write access watch in region[3]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3RA": {
+                    "description": "Enable read access watch in region[3]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0WA": {
+                    "description": "Enable write access watch in PREGION[0]",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0RA": {
+                    "description": "Enable read access watch in PREGION[0]",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1WA": {
+                    "description": "Enable write access watch in PREGION[1]",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1RA": {
+                    "description": "Enable read access watch in PREGION[1]",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REGIONENCLR": {
+              "description": "Disable regions watch",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RGN0WA": {
+                    "description": "Disable write access watch in region[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN0RA": {
+                    "description": "Disable read access watch in region[0]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1WA": {
+                    "description": "Disable write access watch in region[1]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1RA": {
+                    "description": "Disable read access watch in region[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2WA": {
+                    "description": "Disable write access watch in region[2]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2RA": {
+                    "description": "Disable read access watch in region[2]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3WA": {
+                    "description": "Disable write access watch in region[3]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3RA": {
+                    "description": "Disable read access watch in region[3]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0WA": {
+                    "description": "Disable write access watch in PREGION[0]",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0RA": {
+                    "description": "Disable read access watch in PREGION[0]",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1WA": {
+                    "description": "Disable write access watch in PREGION[1]",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1RA": {
+                    "description": "Disable read access watch in PREGION[1]",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PPI": {
+        "description": "Programmable Peripheral Interconnect",
+        "children": {
+          "registers": {
+            "CHEN": {
+              "description": "Channel enable register",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0": {
+                    "description": "Enable or disable channel 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1": {
+                    "description": "Enable or disable channel 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2": {
+                    "description": "Enable or disable channel 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3": {
+                    "description": "Enable or disable channel 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4": {
+                    "description": "Enable or disable channel 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5": {
+                    "description": "Enable or disable channel 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6": {
+                    "description": "Enable or disable channel 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7": {
+                    "description": "Enable or disable channel 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH8": {
+                    "description": "Enable or disable channel 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH9": {
+                    "description": "Enable or disable channel 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH10": {
+                    "description": "Enable or disable channel 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH11": {
+                    "description": "Enable or disable channel 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH12": {
+                    "description": "Enable or disable channel 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH13": {
+                    "description": "Enable or disable channel 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH14": {
+                    "description": "Enable or disable channel 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH15": {
+                    "description": "Enable or disable channel 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH16": {
+                    "description": "Enable or disable channel 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH17": {
+                    "description": "Enable or disable channel 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH18": {
+                    "description": "Enable or disable channel 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH19": {
+                    "description": "Enable or disable channel 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH20": {
+                    "description": "Enable or disable channel 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH21": {
+                    "description": "Enable or disable channel 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH22": {
+                    "description": "Enable or disable channel 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH23": {
+                    "description": "Enable or disable channel 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH24": {
+                    "description": "Enable or disable channel 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH25": {
+                    "description": "Enable or disable channel 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH26": {
+                    "description": "Enable or disable channel 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH27": {
+                    "description": "Enable or disable channel 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH28": {
+                    "description": "Enable or disable channel 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH29": {
+                    "description": "Enable or disable channel 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH30": {
+                    "description": "Enable or disable channel 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH31": {
+                    "description": "Enable or disable channel 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CHENSET": {
+              "description": "Channel enable set register",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0": {
+                    "description": "Channel 0 enable set register.  Writing '0' has no effect",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1": {
+                    "description": "Channel 1 enable set register.  Writing '0' has no effect",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2": {
+                    "description": "Channel 2 enable set register.  Writing '0' has no effect",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3": {
+                    "description": "Channel 3 enable set register.  Writing '0' has no effect",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4": {
+                    "description": "Channel 4 enable set register.  Writing '0' has no effect",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5": {
+                    "description": "Channel 5 enable set register.  Writing '0' has no effect",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6": {
+                    "description": "Channel 6 enable set register.  Writing '0' has no effect",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7": {
+                    "description": "Channel 7 enable set register.  Writing '0' has no effect",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH8": {
+                    "description": "Channel 8 enable set register.  Writing '0' has no effect",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH9": {
+                    "description": "Channel 9 enable set register.  Writing '0' has no effect",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH10": {
+                    "description": "Channel 10 enable set register.  Writing '0' has no effect",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH11": {
+                    "description": "Channel 11 enable set register.  Writing '0' has no effect",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH12": {
+                    "description": "Channel 12 enable set register.  Writing '0' has no effect",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH13": {
+                    "description": "Channel 13 enable set register.  Writing '0' has no effect",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH14": {
+                    "description": "Channel 14 enable set register.  Writing '0' has no effect",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH15": {
+                    "description": "Channel 15 enable set register.  Writing '0' has no effect",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH16": {
+                    "description": "Channel 16 enable set register.  Writing '0' has no effect",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH17": {
+                    "description": "Channel 17 enable set register.  Writing '0' has no effect",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH18": {
+                    "description": "Channel 18 enable set register.  Writing '0' has no effect",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH19": {
+                    "description": "Channel 19 enable set register.  Writing '0' has no effect",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH20": {
+                    "description": "Channel 20 enable set register.  Writing '0' has no effect",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH21": {
+                    "description": "Channel 21 enable set register.  Writing '0' has no effect",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH22": {
+                    "description": "Channel 22 enable set register.  Writing '0' has no effect",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH23": {
+                    "description": "Channel 23 enable set register.  Writing '0' has no effect",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH24": {
+                    "description": "Channel 24 enable set register.  Writing '0' has no effect",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH25": {
+                    "description": "Channel 25 enable set register.  Writing '0' has no effect",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH26": {
+                    "description": "Channel 26 enable set register.  Writing '0' has no effect",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH27": {
+                    "description": "Channel 27 enable set register.  Writing '0' has no effect",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH28": {
+                    "description": "Channel 28 enable set register.  Writing '0' has no effect",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH29": {
+                    "description": "Channel 29 enable set register.  Writing '0' has no effect",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH30": {
+                    "description": "Channel 30 enable set register.  Writing '0' has no effect",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH31": {
+                    "description": "Channel 31 enable set register.  Writing '0' has no effect",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CHENCLR": {
+              "description": "Channel enable clear register",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0": {
+                    "description": "Channel 0 enable clear register.  Writing '0' has no effect",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1": {
+                    "description": "Channel 1 enable clear register.  Writing '0' has no effect",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2": {
+                    "description": "Channel 2 enable clear register.  Writing '0' has no effect",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3": {
+                    "description": "Channel 3 enable clear register.  Writing '0' has no effect",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4": {
+                    "description": "Channel 4 enable clear register.  Writing '0' has no effect",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5": {
+                    "description": "Channel 5 enable clear register.  Writing '0' has no effect",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6": {
+                    "description": "Channel 6 enable clear register.  Writing '0' has no effect",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7": {
+                    "description": "Channel 7 enable clear register.  Writing '0' has no effect",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH8": {
+                    "description": "Channel 8 enable clear register.  Writing '0' has no effect",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH9": {
+                    "description": "Channel 9 enable clear register.  Writing '0' has no effect",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH10": {
+                    "description": "Channel 10 enable clear register.  Writing '0' has no effect",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH11": {
+                    "description": "Channel 11 enable clear register.  Writing '0' has no effect",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH12": {
+                    "description": "Channel 12 enable clear register.  Writing '0' has no effect",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH13": {
+                    "description": "Channel 13 enable clear register.  Writing '0' has no effect",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH14": {
+                    "description": "Channel 14 enable clear register.  Writing '0' has no effect",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH15": {
+                    "description": "Channel 15 enable clear register.  Writing '0' has no effect",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH16": {
+                    "description": "Channel 16 enable clear register.  Writing '0' has no effect",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH17": {
+                    "description": "Channel 17 enable clear register.  Writing '0' has no effect",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH18": {
+                    "description": "Channel 18 enable clear register.  Writing '0' has no effect",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH19": {
+                    "description": "Channel 19 enable clear register.  Writing '0' has no effect",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH20": {
+                    "description": "Channel 20 enable clear register.  Writing '0' has no effect",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH21": {
+                    "description": "Channel 21 enable clear register.  Writing '0' has no effect",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH22": {
+                    "description": "Channel 22 enable clear register.  Writing '0' has no effect",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH23": {
+                    "description": "Channel 23 enable clear register.  Writing '0' has no effect",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH24": {
+                    "description": "Channel 24 enable clear register.  Writing '0' has no effect",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH25": {
+                    "description": "Channel 25 enable clear register.  Writing '0' has no effect",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH26": {
+                    "description": "Channel 26 enable clear register.  Writing '0' has no effect",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH27": {
+                    "description": "Channel 27 enable clear register.  Writing '0' has no effect",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH28": {
+                    "description": "Channel 28 enable clear register.  Writing '0' has no effect",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH29": {
+                    "description": "Channel 29 enable clear register.  Writing '0' has no effect",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH30": {
+                    "description": "Channel 30 enable clear register.  Writing '0' has no effect",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH31": {
+                    "description": "Channel 31 enable clear register.  Writing '0' has no effect",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CHG": {
+              "description": "Description collection[0]:  Channel group 0",
+              "offset": 2048,
+              "size": 32,
+              "count": 6,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0": {
+                    "description": "Include or exclude channel 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1": {
+                    "description": "Include or exclude channel 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2": {
+                    "description": "Include or exclude channel 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3": {
+                    "description": "Include or exclude channel 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4": {
+                    "description": "Include or exclude channel 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5": {
+                    "description": "Include or exclude channel 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6": {
+                    "description": "Include or exclude channel 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7": {
+                    "description": "Include or exclude channel 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH8": {
+                    "description": "Include or exclude channel 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH9": {
+                    "description": "Include or exclude channel 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH10": {
+                    "description": "Include or exclude channel 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH11": {
+                    "description": "Include or exclude channel 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH12": {
+                    "description": "Include or exclude channel 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH13": {
+                    "description": "Include or exclude channel 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH14": {
+                    "description": "Include or exclude channel 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH15": {
+                    "description": "Include or exclude channel 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH16": {
+                    "description": "Include or exclude channel 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH17": {
+                    "description": "Include or exclude channel 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH18": {
+                    "description": "Include or exclude channel 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH19": {
+                    "description": "Include or exclude channel 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH20": {
+                    "description": "Include or exclude channel 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH21": {
+                    "description": "Include or exclude channel 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH22": {
+                    "description": "Include or exclude channel 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH23": {
+                    "description": "Include or exclude channel 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH24": {
+                    "description": "Include or exclude channel 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH25": {
+                    "description": "Include or exclude channel 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH26": {
+                    "description": "Include or exclude channel 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH27": {
+                    "description": "Include or exclude channel 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH28": {
+                    "description": "Include or exclude channel 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH29": {
+                    "description": "Include or exclude channel 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH30": {
+                    "description": "Include or exclude channel 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH31": {
+                    "description": "Include or exclude channel 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NFCT": {
+        "description": "NFC-A compatible radio",
+        "children": {
+          "registers": {
+            "TASKS_ACTIVATE": {
+              "description": "Activate NFC peripheral for incoming and outgoing frames, change state to activated",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_DISABLE": {
+              "description": "Disable NFC peripheral",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SENSE": {
+              "description": "Enable NFC sense field mode, change state to sense mode",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STARTTX": {
+              "description": "Start transmission of a outgoing frame, change state to transmit",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_ENABLERXDATA": {
+              "description": "Initializes the EasyDMA for receive.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_GOIDLE": {
+              "description": "Force state machine to IDLE state",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_GOSLEEP": {
+              "description": "Force state machine to SLEEP_A state",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_READY": {
+              "description": "The NFC peripheral is ready to receive and send frames",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_FIELDDETECTED": {
+              "description": "Remote NFC field detected",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_FIELDLOST": {
+              "description": "Remote NFC field lost",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_TXFRAMESTART": {
+              "description": "Marks the start of the first symbol of a transmitted frame",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_TXFRAMEEND": {
+              "description": "Marks the end of the last transmitted on-air symbol of a frame",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RXFRAMESTART": {
+              "description": "Marks the end of the first symbol of a received frame",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RXFRAMEEND": {
+              "description": "Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ERROR": {
+              "description": "NFC error reported. The ERRORSTATUS register contains details on the source of the error.",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RXERROR": {
+              "description": "NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ENDRX": {
+              "description": "RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ENDTX": {
+              "description": "Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_AUTOCOLRESSTARTED": {
+              "description": "Auto collision resolution process has started",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_COLLISION": {
+              "description": "NFC Auto collision resolution error reported.",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_SELECTED": {
+              "description": "NFC Auto collision resolution successfully completed",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_STARTED": {
+              "description": "EasyDMA is ready to receive or send frames.",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FIELDDETECTED_ACTIVATE": {
+                    "description": "Shortcut between FIELDDETECTED event and ACTIVATE task",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDLOST_SENSE": {
+                    "description": "Shortcut between FIELDLOST event and SENSE task",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Enable or disable interrupt for READY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDDETECTED": {
+                    "description": "Enable or disable interrupt for FIELDDETECTED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDLOST": {
+                    "description": "Enable or disable interrupt for FIELDLOST event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMESTART": {
+                    "description": "Enable or disable interrupt for TXFRAMESTART event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMEEND": {
+                    "description": "Enable or disable interrupt for TXFRAMEEND event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMESTART": {
+                    "description": "Enable or disable interrupt for RXFRAMESTART event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMEEND": {
+                    "description": "Enable or disable interrupt for RXFRAMEEND event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Enable or disable interrupt for ERROR event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXERROR": {
+                    "description": "Enable or disable interrupt for RXERROR event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Enable or disable interrupt for ENDRX event",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Enable or disable interrupt for ENDTX event",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AUTOCOLRESSTARTED": {
+                    "description": "Enable or disable interrupt for AUTOCOLRESSTARTED event",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COLLISION": {
+                    "description": "Enable or disable interrupt for COLLISION event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SELECTED": {
+                    "description": "Enable or disable interrupt for SELECTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Enable or disable interrupt for STARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to Enable interrupt for READY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDDETECTED": {
+                    "description": "Write '1' to Enable interrupt for FIELDDETECTED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDLOST": {
+                    "description": "Write '1' to Enable interrupt for FIELDLOST event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMESTART": {
+                    "description": "Write '1' to Enable interrupt for TXFRAMESTART event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMEEND": {
+                    "description": "Write '1' to Enable interrupt for TXFRAMEEND event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMESTART": {
+                    "description": "Write '1' to Enable interrupt for RXFRAMESTART event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMEEND": {
+                    "description": "Write '1' to Enable interrupt for RXFRAMEEND event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Enable interrupt for ERROR event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXERROR": {
+                    "description": "Write '1' to Enable interrupt for RXERROR event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to Enable interrupt for ENDRX event",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to Enable interrupt for ENDTX event",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AUTOCOLRESSTARTED": {
+                    "description": "Write '1' to Enable interrupt for AUTOCOLRESSTARTED event",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COLLISION": {
+                    "description": "Write '1' to Enable interrupt for COLLISION event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SELECTED": {
+                    "description": "Write '1' to Enable interrupt for SELECTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Write '1' to Enable interrupt for STARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to Disable interrupt for READY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDDETECTED": {
+                    "description": "Write '1' to Disable interrupt for FIELDDETECTED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDLOST": {
+                    "description": "Write '1' to Disable interrupt for FIELDLOST event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMESTART": {
+                    "description": "Write '1' to Disable interrupt for TXFRAMESTART event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMEEND": {
+                    "description": "Write '1' to Disable interrupt for TXFRAMEEND event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMESTART": {
+                    "description": "Write '1' to Disable interrupt for RXFRAMESTART event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMEEND": {
+                    "description": "Write '1' to Disable interrupt for RXFRAMEEND event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Disable interrupt for ERROR event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXERROR": {
+                    "description": "Write '1' to Disable interrupt for RXERROR event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to Disable interrupt for ENDRX event",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to Disable interrupt for ENDTX event",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AUTOCOLRESSTARTED": {
+                    "description": "Write '1' to Disable interrupt for AUTOCOLRESSTARTED event",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COLLISION": {
+                    "description": "Write '1' to Disable interrupt for COLLISION event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SELECTED": {
+                    "description": "Write '1' to Disable interrupt for SELECTED event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Write '1' to Disable interrupt for STARTED event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSTATUS": {
+              "description": "NFC Error Status register",
+              "offset": 1028,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRAMEDELAYTIMEOUT": {
+                    "description": "No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "NFCFIELDTOOSTRONG": {
+                    "description": "Field level is too high at max load resistance",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "NFCFIELDTOOWEAK": {
+                    "description": "Field level is too low at min load resistance",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CURRENTLOADCTRL": {
+              "description": "Current value driven to the NFC Load Control",
+              "offset": 1072,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CURRENTLOADCTRL": {
+                    "description": "Current value driven to the NFC Load Control",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "FIELDPRESENT": {
+              "description": "Indicates the presence or not of a valid field",
+              "offset": 1084,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FIELDPRESENT": {
+                    "description": "Indicates the presence or not of a valid field. Available only in the activated state.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoField": {
+                            "description": "No valid field detected",
+                            "value": 0
+                          },
+                          "FieldPresent": {
+                            "description": "Valid field detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOCKDETECT": {
+                    "description": "Indicates if the low level has locked to the field",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLocked": {
+                            "description": "Not locked to field",
+                            "value": 0
+                          },
+                          "Locked": {
+                            "description": "Locked to field",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FRAMEDELAYMIN": {
+              "description": "Minimum frame delay",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 1152,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRAMEDELAYMIN": {
+                    "description": "Minimum frame delay in number of 13.56 MHz clocks",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FRAMEDELAYMAX": {
+              "description": "Maximum frame delay",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 4096,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRAMEDELAYMAX": {
+                    "description": "Maximum frame delay in number of 13.56 MHz clocks",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FRAMEDELAYMODE": {
+              "description": "Configuration register for the Frame Delay Timer",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRAMEDELAYMODE": {
+                    "description": "Configuration register for the Frame Delay Timer",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "FreeRun": {
+                            "description": "Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout.",
+                            "value": 0
+                          },
+                          "Window": {
+                            "description": "Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX",
+                            "value": 1
+                          },
+                          "ExactVal": {
+                            "description": "Frame is transmitted exactly at FRAMEDELAYMAX",
+                            "value": 2
+                          },
+                          "WindowGrid": {
+                            "description": "Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PACKETPTR": {
+              "description": "Packet pointer for TXD and RXD data storage in Data RAM",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTR": {
+                    "description": "Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MAXLEN": {
+              "description": "Size of allocated for TXD and RXD data storage buffer in Data RAM",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAXLEN": {
+                    "description": "Size of allocated for TXD and RXD data storage buffer in Data RAM",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "NFCID1_LAST": {
+              "description": "Last NFCID1 part (4, 7 or 10 bytes ID)",
+              "offset": 1424,
+              "size": 32,
+              "reset_value": 25443,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NFCID1_Z": {
+                    "description": "NFCID1 byte Z (very last byte sent)",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "NFCID1_Y": {
+                    "description": "NFCID1 byte Y",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "NFCID1_X": {
+                    "description": "NFCID1 byte X",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "NFCID1_W": {
+                    "description": "NFCID1 byte W",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "NFCID1_2ND_LAST": {
+              "description": "Second last NFCID1 part (7 or 10 bytes ID)",
+              "offset": 1428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NFCID1_V": {
+                    "description": "NFCID1 byte V",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "NFCID1_U": {
+                    "description": "NFCID1 byte U",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "NFCID1_T": {
+                    "description": "NFCID1 byte T",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "NFCID1_3RD_LAST": {
+              "description": "Third last NFCID1 part (10 bytes ID)",
+              "offset": 1432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NFCID1_S": {
+                    "description": "NFCID1 byte S",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "NFCID1_R": {
+                    "description": "NFCID1 byte R",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "NFCID1_Q": {
+                    "description": "NFCID1 byte Q",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SENSRES": {
+              "description": "NFC-A SENS_RES auto-response settings",
+              "offset": 1440,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BITFRAMESDD": {
+                    "description": "Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "SDD00000": {
+                            "description": "SDD pattern 00000",
+                            "value": 0
+                          },
+                          "SDD00001": {
+                            "description": "SDD pattern 00001",
+                            "value": 1
+                          },
+                          "SDD00010": {
+                            "description": "SDD pattern 00010",
+                            "value": 2
+                          },
+                          "SDD00100": {
+                            "description": "SDD pattern 00100",
+                            "value": 4
+                          },
+                          "SDD01000": {
+                            "description": "SDD pattern 01000",
+                            "value": 8
+                          },
+                          "SDD10000": {
+                            "description": "SDD pattern 10000",
+                            "value": 16
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RFU5": {
+                    "description": "Reserved for future use. Shall be 0.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NFCIDSIZE": {
+                    "description": "NFCID1 size. This value is used by the Auto collision resolution engine.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NFCID1Single": {
+                            "description": "NFCID1 size: single (4 bytes)",
+                            "value": 0
+                          },
+                          "NFCID1Double": {
+                            "description": "NFCID1 size: double (7 bytes)",
+                            "value": 1
+                          },
+                          "NFCID1Triple": {
+                            "description": "NFCID1 size: triple (10 bytes)",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PLATFCONFIG": {
+                    "description": "Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "RFU74": {
+                    "description": "Reserved for future use. Shall be 0.",
+                    "offset": 12,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SELRES": {
+              "description": "NFC-A SEL_RES auto-response settings",
+              "offset": 1444,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFU10": {
+                    "description": "Reserved for future use. Shall be 0.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CASCADE": {
+                    "description": "Cascade bit (controlled by hardware, write has no effect)",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Complete": {
+                            "description": "NFCID1 complete",
+                            "value": 0
+                          },
+                          "NotComplete": {
+                            "description": "NFCID1 not complete",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RFU43": {
+                    "description": "Reserved for future use. Shall be 0.",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "PROTOCOL": {
+                    "description": "Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "RFU7": {
+                    "description": "Reserved for future use. Shall be 0.",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOTE": {
+        "description": "GPIO Tasks and Events",
+        "children": {
+          "registers": {
+            "TASKS_OUT": {
+              "description": "Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY.",
+              "offset": 0,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SET": {
+              "description": "Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high.",
+              "offset": 48,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_CLR": {
+              "description": "Description collection[0]:  Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low.",
+              "offset": 96,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_IN": {
+              "description": "Description collection[0]:  Event generated from pin specified in CONFIG[0].PSEL",
+              "offset": 256,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_PORT": {
+              "description": "Event generated from multiple input GPIO pins with SENSE mechanism enabled",
+              "offset": 380,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN0": {
+                    "description": "Write '1' to Enable interrupt for IN[0] event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN1": {
+                    "description": "Write '1' to Enable interrupt for IN[1] event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN2": {
+                    "description": "Write '1' to Enable interrupt for IN[2] event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN3": {
+                    "description": "Write '1' to Enable interrupt for IN[3] event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN4": {
+                    "description": "Write '1' to Enable interrupt for IN[4] event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN5": {
+                    "description": "Write '1' to Enable interrupt for IN[5] event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN6": {
+                    "description": "Write '1' to Enable interrupt for IN[6] event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN7": {
+                    "description": "Write '1' to Enable interrupt for IN[7] event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PORT": {
+                    "description": "Write '1' to Enable interrupt for PORT event",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN0": {
+                    "description": "Write '1' to Disable interrupt for IN[0] event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN1": {
+                    "description": "Write '1' to Disable interrupt for IN[1] event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN2": {
+                    "description": "Write '1' to Disable interrupt for IN[2] event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN3": {
+                    "description": "Write '1' to Disable interrupt for IN[3] event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN4": {
+                    "description": "Write '1' to Disable interrupt for IN[4] event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN5": {
+                    "description": "Write '1' to Disable interrupt for IN[5] event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN6": {
+                    "description": "Write '1' to Disable interrupt for IN[6] event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN7": {
+                    "description": "Write '1' to Disable interrupt for IN[7] event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PORT": {
+                    "description": "Write '1' to Disable interrupt for PORT event",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event",
+              "offset": 1296,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Mode",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.",
+                            "value": 0
+                          },
+                          "Event": {
+                            "description": "Event mode",
+                            "value": 1
+                          },
+                          "Task": {
+                            "description": "Task mode",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PSEL": {
+                    "description": "GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "POLARITY": {
+                    "description": "When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "None": {
+                            "description": "Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.",
+                            "value": 0
+                          },
+                          "LoToHi": {
+                            "description": "Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.",
+                            "value": 1
+                          },
+                          "HiToLo": {
+                            "description": "Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.",
+                            "value": 2
+                          },
+                          "Toggle": {
+                            "description": "Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTINIT": {
+                    "description": "When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Task mode: Initial value of pin before task triggering is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Task mode: Initial value of pin before task triggering is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SAADC": {
+        "description": "Analog to Digital Converter",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start the ADC and prepare the result buffer in RAM",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SAMPLE": {
+              "description": "Take one ADC sample, if scan is enabled all channels are sampled",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop the ADC and terminate any on-going conversion",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_CALIBRATEOFFSET": {
+              "description": "Starts offset auto-calibration",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_STARTED": {
+              "description": "The ADC has started",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_END": {
+              "description": "The ADC has filled up the Result buffer",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_DONE": {
+              "description": "A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RESULTDONE": {
+              "description": "A result is ready to get transferred to RAM.",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_CALIBRATEDONE": {
+              "description": "Calibration is complete",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_STOPPED": {
+              "description": "The ADC has stopped",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Enable or disable interrupt for STARTED event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Enable or disable interrupt for END event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DONE": {
+                    "description": "Enable or disable interrupt for DONE event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESULTDONE": {
+                    "description": "Enable or disable interrupt for RESULTDONE event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CALIBRATEDONE": {
+                    "description": "Enable or disable interrupt for CALIBRATEDONE event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for STOPPED event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITH": {
+                    "description": "Enable or disable interrupt for CH[0].LIMITH event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITL": {
+                    "description": "Enable or disable interrupt for CH[0].LIMITL event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITH": {
+                    "description": "Enable or disable interrupt for CH[1].LIMITH event",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITL": {
+                    "description": "Enable or disable interrupt for CH[1].LIMITL event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITH": {
+                    "description": "Enable or disable interrupt for CH[2].LIMITH event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITL": {
+                    "description": "Enable or disable interrupt for CH[2].LIMITL event",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITH": {
+                    "description": "Enable or disable interrupt for CH[3].LIMITH event",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITL": {
+                    "description": "Enable or disable interrupt for CH[3].LIMITL event",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITH": {
+                    "description": "Enable or disable interrupt for CH[4].LIMITH event",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITL": {
+                    "description": "Enable or disable interrupt for CH[4].LIMITL event",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITH": {
+                    "description": "Enable or disable interrupt for CH[5].LIMITH event",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITL": {
+                    "description": "Enable or disable interrupt for CH[5].LIMITL event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITH": {
+                    "description": "Enable or disable interrupt for CH[6].LIMITH event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITL": {
+                    "description": "Enable or disable interrupt for CH[6].LIMITL event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITH": {
+                    "description": "Enable or disable interrupt for CH[7].LIMITH event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITL": {
+                    "description": "Enable or disable interrupt for CH[7].LIMITL event",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Write '1' to Enable interrupt for STARTED event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to Enable interrupt for END event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DONE": {
+                    "description": "Write '1' to Enable interrupt for DONE event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESULTDONE": {
+                    "description": "Write '1' to Enable interrupt for RESULTDONE event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CALIBRATEDONE": {
+                    "description": "Write '1' to Enable interrupt for CALIBRATEDONE event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to Enable interrupt for STOPPED event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITH": {
+                    "description": "Write '1' to Enable interrupt for CH[0].LIMITH event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITL": {
+                    "description": "Write '1' to Enable interrupt for CH[0].LIMITL event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITH": {
+                    "description": "Write '1' to Enable interrupt for CH[1].LIMITH event",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITL": {
+                    "description": "Write '1' to Enable interrupt for CH[1].LIMITL event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITH": {
+                    "description": "Write '1' to Enable interrupt for CH[2].LIMITH event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITL": {
+                    "description": "Write '1' to Enable interrupt for CH[2].LIMITL event",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITH": {
+                    "description": "Write '1' to Enable interrupt for CH[3].LIMITH event",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITL": {
+                    "description": "Write '1' to Enable interrupt for CH[3].LIMITL event",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITH": {
+                    "description": "Write '1' to Enable interrupt for CH[4].LIMITH event",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITL": {
+                    "description": "Write '1' to Enable interrupt for CH[4].LIMITL event",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITH": {
+                    "description": "Write '1' to Enable interrupt for CH[5].LIMITH event",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITL": {
+                    "description": "Write '1' to Enable interrupt for CH[5].LIMITL event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITH": {
+                    "description": "Write '1' to Enable interrupt for CH[6].LIMITH event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITL": {
+                    "description": "Write '1' to Enable interrupt for CH[6].LIMITL event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITH": {
+                    "description": "Write '1' to Enable interrupt for CH[7].LIMITH event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITL": {
+                    "description": "Write '1' to Enable interrupt for CH[7].LIMITL event",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Write '1' to Disable interrupt for STARTED event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to Disable interrupt for END event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DONE": {
+                    "description": "Write '1' to Disable interrupt for DONE event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESULTDONE": {
+                    "description": "Write '1' to Disable interrupt for RESULTDONE event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CALIBRATEDONE": {
+                    "description": "Write '1' to Disable interrupt for CALIBRATEDONE event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to Disable interrupt for STOPPED event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITH": {
+                    "description": "Write '1' to Disable interrupt for CH[0].LIMITH event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITL": {
+                    "description": "Write '1' to Disable interrupt for CH[0].LIMITL event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITH": {
+                    "description": "Write '1' to Disable interrupt for CH[1].LIMITH event",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITL": {
+                    "description": "Write '1' to Disable interrupt for CH[1].LIMITL event",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITH": {
+                    "description": "Write '1' to Disable interrupt for CH[2].LIMITH event",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITL": {
+                    "description": "Write '1' to Disable interrupt for CH[2].LIMITL event",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITH": {
+                    "description": "Write '1' to Disable interrupt for CH[3].LIMITH event",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITL": {
+                    "description": "Write '1' to Disable interrupt for CH[3].LIMITL event",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITH": {
+                    "description": "Write '1' to Disable interrupt for CH[4].LIMITH event",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITL": {
+                    "description": "Write '1' to Disable interrupt for CH[4].LIMITL event",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITH": {
+                    "description": "Write '1' to Disable interrupt for CH[5].LIMITH event",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITL": {
+                    "description": "Write '1' to Disable interrupt for CH[5].LIMITL event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITH": {
+                    "description": "Write '1' to Disable interrupt for CH[6].LIMITH event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITL": {
+                    "description": "Write '1' to Disable interrupt for CH[6].LIMITL event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITH": {
+                    "description": "Write '1' to Disable interrupt for CH[7].LIMITH event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITL": {
+                    "description": "Write '1' to Disable interrupt for CH[7].LIMITL event",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Status",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STATUS": {
+                    "description": "Status",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Ready": {
+                            "description": "ADC is ready. No on-going conversion.",
+                            "value": 0
+                          },
+                          "Busy": {
+                            "description": "ADC is busy. Conversion in progress.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable or disable ADC",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable ADC",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable ADC",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable ADC",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RESOLUTION": {
+              "description": "Resolution configuration",
+              "offset": 1520,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VAL": {
+                    "description": "Set the resolution",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "8bit": {
+                            "description": "8 bit",
+                            "value": 0
+                          },
+                          "10bit": {
+                            "description": "10 bit",
+                            "value": 1
+                          },
+                          "12bit": {
+                            "description": "12 bit",
+                            "value": 2
+                          },
+                          "14bit": {
+                            "description": "14 bit",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "OVERSAMPLE": {
+              "description": "Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.",
+              "offset": 1524,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERSAMPLE": {
+                    "description": "Oversample control",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Bypass": {
+                            "description": "Bypass oversampling",
+                            "value": 0
+                          },
+                          "Over2x": {
+                            "description": "Oversample 2x",
+                            "value": 1
+                          },
+                          "Over4x": {
+                            "description": "Oversample 4x",
+                            "value": 2
+                          },
+                          "Over8x": {
+                            "description": "Oversample 8x",
+                            "value": 3
+                          },
+                          "Over16x": {
+                            "description": "Oversample 16x",
+                            "value": 4
+                          },
+                          "Over32x": {
+                            "description": "Oversample 32x",
+                            "value": 5
+                          },
+                          "Over64x": {
+                            "description": "Oversample 64x",
+                            "value": 6
+                          },
+                          "Over128x": {
+                            "description": "Oversample 128x",
+                            "value": 7
+                          },
+                          "Over256x": {
+                            "description": "Oversample 256x",
+                            "value": 8
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SAMPLERATE": {
+              "description": "Controls normal or continuous sample rate",
+              "offset": 1528,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC": {
+                    "description": "Capture and compare value. Sample rate is 16 MHz/CC",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "MODE": {
+                    "description": "Select mode for sample rate control",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Task": {
+                            "description": "Rate is controlled from SAMPLE task",
+                            "value": 0
+                          },
+                          "Timers": {
+                            "description": "Rate is controlled from local timer (use CC to control the rate)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIMER0": {
+        "description": "Timer/Counter 0",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start Timer",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop Timer",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_COUNT": {
+              "description": "Increment Timer (Counter mode only)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_CLEAR": {
+              "description": "Clear time",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SHUTDOWN": {
+              "description": "Deprecated register -  Shut down timer",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_CAPTURE": {
+              "description": "Description collection[0]:  Capture Timer value to CC[0] register",
+              "offset": 64,
+              "size": 32,
+              "count": 6,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_COMPARE": {
+              "description": "Description collection[0]:  Compare event on CC[0] match",
+              "offset": 320,
+              "size": 32,
+              "count": 6,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMPARE0_CLEAR": {
+                    "description": "Shortcut between COMPARE[0] event and CLEAR task",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1_CLEAR": {
+                    "description": "Shortcut between COMPARE[1] event and CLEAR task",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2_CLEAR": {
+                    "description": "Shortcut between COMPARE[2] event and CLEAR task",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3_CLEAR": {
+                    "description": "Shortcut between COMPARE[3] event and CLEAR task",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE4_CLEAR": {
+                    "description": "Shortcut between COMPARE[4] event and CLEAR task",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE5_CLEAR": {
+                    "description": "Shortcut between COMPARE[5] event and CLEAR task",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0_STOP": {
+                    "description": "Shortcut between COMPARE[0] event and STOP task",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1_STOP": {
+                    "description": "Shortcut between COMPARE[1] event and STOP task",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2_STOP": {
+                    "description": "Shortcut between COMPARE[2] event and STOP task",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3_STOP": {
+                    "description": "Shortcut between COMPARE[3] event and STOP task",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE4_STOP": {
+                    "description": "Shortcut between COMPARE[4] event and STOP task",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE5_STOP": {
+                    "description": "Shortcut between COMPARE[5] event and STOP task",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMPARE0": {
+                    "description": "Write '1' to Enable interrupt for COMPARE[0] event",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to Enable interrupt for COMPARE[1] event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to Enable interrupt for COMPARE[2] event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to Enable interrupt for COMPARE[3] event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE4": {
+                    "description": "Write '1' to Enable interrupt for COMPARE[4] event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE5": {
+                    "description": "Write '1' to Enable interrupt for COMPARE[5] event",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMPARE0": {
+                    "description": "Write '1' to Disable interrupt for COMPARE[0] event",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to Disable interrupt for COMPARE[1] event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to Disable interrupt for COMPARE[2] event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to Disable interrupt for COMPARE[3] event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE4": {
+                    "description": "Write '1' to Disable interrupt for COMPARE[4] event",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE5": {
+                    "description": "Write '1' to Disable interrupt for COMPARE[5] event",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Timer mode selection",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Timer mode",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Timer": {
+                            "description": "Select Timer mode",
+                            "value": 0
+                          },
+                          "Counter": {
+                            "description": "Deprecated enumerator -  Select Counter mode",
+                            "value": 1
+                          },
+                          "LowPowerCounter": {
+                            "description": "Select Low Power Counter mode",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "BITMODE": {
+              "description": "Configure the number of bits used by the TIMER",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BITMODE": {
+                    "description": "Timer bit width",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "16Bit": {
+                            "description": "16 bit timer bit width",
+                            "value": 0
+                          },
+                          "08Bit": {
+                            "description": "8 bit timer bit width",
+                            "value": 1
+                          },
+                          "24Bit": {
+                            "description": "24 bit timer bit width",
+                            "value": 2
+                          },
+                          "32Bit": {
+                            "description": "32 bit timer bit width",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PRESCALER": {
+              "description": "Timer prescaler register",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRESCALER": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CC": {
+              "description": "Description collection[0]:  Capture/Compare register 0",
+              "offset": 1344,
+              "size": 32,
+              "count": 6,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC": {
+                    "description": "Capture/Compare value",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NVMC": {
+        "description": "Non Volatile Memory Controller",
+        "children": {
+          "registers": {
+            "READY": {
+              "description": "Ready flag",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "NVMC is ready or busy",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Busy": {
+                            "description": "NVMC is busy (on-going write or erase operation)",
+                            "value": 0
+                          },
+                          "Ready": {
+                            "description": "NVMC is ready",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WEN": {
+                    "description": "Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Ren": {
+                            "description": "Read only access",
+                            "value": 0
+                          },
+                          "Wen": {
+                            "description": "Write Enabled",
+                            "value": 1
+                          },
+                          "Een": {
+                            "description": "Erase enabled",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERASEPAGE": {
+              "description": "Register for erasing a page in Code area",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERASEPAGE": {
+                    "description": "Register for starting erase of a page in Code area",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ERASEPCR1": {
+              "description": "Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE.",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERASEPCR1": {
+                    "description": "Register for erasing a page in Code area. Equivalent to ERASEPAGE.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ERASEALL": {
+              "description": "Register for erasing all non-volatile user memory",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERASEALL": {
+                    "description": "Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoOperation": {
+                            "description": "No operation",
+                            "value": 0
+                          },
+                          "Erase": {
+                            "description": "Start chip erase",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERASEPCR0": {
+              "description": "Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE.",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERASEPCR0": {
+                    "description": "Register for starting erase of a page in Code area. Equivalent to ERASEPAGE.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ERASEUICR": {
+              "description": "Register for erasing User Information Configuration Registers",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERASEUICR": {
+                    "description": "Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoOperation": {
+                            "description": "No operation",
+                            "value": 0
+                          },
+                          "Erase": {
+                            "description": "Start erase of UICR",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ICACHECNF": {
+              "description": "I-Code cache configuration register.",
+              "offset": 1344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHEEN": {
+                    "description": "Cache enable",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable cache. Invalidates all cache entries.",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable cache",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CACHEPROFEN": {
+                    "description": "Cache profiling enable",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable cache profiling",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable cache profiling",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IHIT": {
+              "description": "I-Code cache hit counter.",
+              "offset": 1352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HITS": {
+                    "description": "Number of cache hits",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IMISS": {
+              "description": "I-Code cache miss counter.",
+              "offset": 1356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MISSES": {
+                    "description": "Number of cache misses",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PDM": {
+        "description": "Pulse Density Modulation (Digital Microphone) Interface",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Starts continuous PDM transfer",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stops PDM transfer",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_STARTED": {
+              "description": "PDM transfer has started",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_STOPPED": {
+              "description": "PDM transfer has finished",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_END": {
+              "description": "The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Enable or disable interrupt for STARTED event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Enable or disable interrupt for END event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Write '1' to Enable interrupt for STARTED event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to Enable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to Enable interrupt for END event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Write '1' to Disable interrupt for STARTED event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to Disable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to Disable interrupt for END event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "PDM module enable register",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable PDM module",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PDMCLKCTRL": {
+              "description": "PDM clock generator control",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 138412032,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQ": {
+                    "description": "PDM_CLK frequency",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "1000K": {
+                            "description": "PDM_CLK = 32 MHz / 32 = 1.000 MHz",
+                            "value": 134217728
+                          },
+                          "Default": {
+                            "description": "PDM_CLK = 32 MHz / 31 = 1.032 MHz",
+                            "value": 138412032
+                          },
+                          "1067K": {
+                            "description": "PDM_CLK = 32 MHz / 30 = 1.067 MHz",
+                            "value": 142606336
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Defines the routing of the connected PDM microphones' signals",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OPERATION": {
+                    "description": "Mono or stereo operation",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Stereo": {
+                            "description": "Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]",
+                            "value": 0
+                          },
+                          "Mono": {
+                            "description": "Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EDGE": {
+                    "description": "Defines on which PDM_CLK edge Left (or mono) is sampled",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LeftFalling": {
+                            "description": "Left (or mono) is sampled on falling edge of PDM_CLK",
+                            "value": 0
+                          },
+                          "LeftRising": {
+                            "description": "Left (or mono) is sampled on rising edge of PDM_CLK",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GAINL": {
+              "description": "Left output gain adjustment",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 40,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GAINL": {
+                    "description": "Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust",
+                    "offset": 0,
+                    "size": 7,
+                    "enum": {
+                      "size": 7,
+                      "children": {
+                        "enum_fields": {
+                          "MinGain": {
+                            "description": "-20dB gain adjustment (minimum)",
+                            "value": 0
+                          },
+                          "DefaultGain": {
+                            "description": "0dB gain adjustment ('2500 RMS' requirement)",
+                            "value": 40
+                          },
+                          "MaxGain": {
+                            "description": "+20dB gain adjustment (maximum)",
+                            "value": 80
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GAINR": {
+              "description": "Right output gain adjustment",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 40,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GAINR": {
+                    "description": "Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)",
+                    "offset": 0,
+                    "size": 8,
+                    "enum": {
+                      "size": 8,
+                      "children": {
+                        "enum_fields": {
+                          "MinGain": {
+                            "description": "-20dB gain adjustment (minimum)",
+                            "value": 0
+                          },
+                          "DefaultGain": {
+                            "description": "0dB gain adjustment ('2500 RMS' requirement)",
+                            "value": 40
+                          },
+                          "MaxGain": {
+                            "description": "+20dB gain adjustment (maximum)",
+                            "value": 80
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RTC0": {
+        "description": "Real time counter 0",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start RTC COUNTER",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop RTC COUNTER",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_CLEAR": {
+              "description": "Clear RTC COUNTER",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_TRIGOVRFLW": {
+              "description": "Set COUNTER to 0xFFFFF0",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_TICK": {
+              "description": "Event on COUNTER increment",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_OVRFLW": {
+              "description": "Event on COUNTER overflow",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_COMPARE": {
+              "description": "Description collection[0]:  Compare event on CC[0] match",
+              "offset": 320,
+              "size": 32,
+              "count": 4,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TICK": {
+                    "description": "Write '1' to Enable interrupt for TICK event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVRFLW": {
+                    "description": "Write '1' to Enable interrupt for OVRFLW event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0": {
+                    "description": "Write '1' to Enable interrupt for COMPARE[0] event",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to Enable interrupt for COMPARE[1] event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to Enable interrupt for COMPARE[2] event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to Enable interrupt for COMPARE[3] event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TICK": {
+                    "description": "Write '1' to Disable interrupt for TICK event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVRFLW": {
+                    "description": "Write '1' to Disable interrupt for OVRFLW event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0": {
+                    "description": "Write '1' to Disable interrupt for COMPARE[0] event",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to Disable interrupt for COMPARE[1] event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to Disable interrupt for COMPARE[2] event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to Disable interrupt for COMPARE[3] event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVTEN": {
+              "description": "Enable or disable event routing",
+              "offset": 832,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TICK": {
+                    "description": "Enable or disable event routing for TICK event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVRFLW": {
+                    "description": "Enable or disable event routing for OVRFLW event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0": {
+                    "description": "Enable or disable event routing for COMPARE[0] event",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Enable or disable event routing for COMPARE[1] event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Enable or disable event routing for COMPARE[2] event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Enable or disable event routing for COMPARE[3] event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVTENSET": {
+              "description": "Enable event routing",
+              "offset": 836,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TICK": {
+                    "description": "Write '1' to Enable event routing for TICK event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVRFLW": {
+                    "description": "Write '1' to Enable event routing for OVRFLW event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0": {
+                    "description": "Write '1' to Enable event routing for COMPARE[0] event",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to Enable event routing for COMPARE[1] event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to Enable event routing for COMPARE[2] event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to Enable event routing for COMPARE[3] event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVTENCLR": {
+              "description": "Disable event routing",
+              "offset": 840,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TICK": {
+                    "description": "Write '1' to Disable event routing for TICK event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVRFLW": {
+                    "description": "Write '1' to Disable event routing for OVRFLW event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0": {
+                    "description": "Write '1' to Disable event routing for COMPARE[0] event",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to Disable event routing for COMPARE[1] event",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to Disable event routing for COMPARE[2] event",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to Disable event routing for COMPARE[3] event",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "COUNTER": {
+              "description": "Current COUNTER value",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "COUNTER": {
+                    "description": "Counter value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "PRESCALER": {
+              "description": "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRESCALER": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "CC": {
+              "description": "Description collection[0]:  Compare register 0",
+              "offset": 1344,
+              "size": 32,
+              "count": 4,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMPARE": {
+                    "description": "Compare value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TEMP": {
+        "description": "Temperature Sensor",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start temperature measurement",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop temperature measurement",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_DATARDY": {
+              "description": "Temperature measurement complete, data ready",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATARDY": {
+                    "description": "Write '1' to Enable interrupt for DATARDY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATARDY": {
+                    "description": "Write '1' to Disable interrupt for DATARDY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TEMP": {
+              "description": "Temperature in degC (0.25deg steps)",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TEMP": {
+                    "description": "Temperature in degC (0.25deg steps)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "A0": {
+              "description": "Slope of 1st piece wise linear function",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 800,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A0": {
+                    "description": "Slope of 1st piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "A1": {
+              "description": "Slope of 2nd piece wise linear function",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 835,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A1": {
+                    "description": "Slope of 2nd piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "A2": {
+              "description": "Slope of 3rd piece wise linear function",
+              "offset": 1320,
+              "size": 32,
+              "reset_value": 861,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A2": {
+                    "description": "Slope of 3rd piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "A3": {
+              "description": "Slope of 4th piece wise linear function",
+              "offset": 1324,
+              "size": 32,
+              "reset_value": 1024,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A3": {
+                    "description": "Slope of 4th piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "A4": {
+              "description": "Slope of 5th piece wise linear function",
+              "offset": 1328,
+              "size": 32,
+              "reset_value": 1151,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A4": {
+                    "description": "Slope of 5th piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "A5": {
+              "description": "Slope of 6th piece wise linear function",
+              "offset": 1332,
+              "size": 32,
+              "reset_value": 891,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A5": {
+                    "description": "Slope of 6th piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "B0": {
+              "description": "y-intercept of 1st piece wise linear function",
+              "offset": 1344,
+              "size": 32,
+              "reset_value": 16332,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B0": {
+                    "description": "y-intercept of 1st piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "B1": {
+              "description": "y-intercept of 2nd piece wise linear function",
+              "offset": 1348,
+              "size": 32,
+              "reset_value": 16280,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B1": {
+                    "description": "y-intercept of 2nd piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "B2": {
+              "description": "y-intercept of 3rd piece wise linear function",
+              "offset": 1352,
+              "size": 32,
+              "reset_value": 16280,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2": {
+                    "description": "y-intercept of 3rd piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "B3": {
+              "description": "y-intercept of 4th piece wise linear function",
+              "offset": 1356,
+              "size": 32,
+              "reset_value": 18,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B3": {
+                    "description": "y-intercept of 4th piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "B4": {
+              "description": "y-intercept of 5th piece wise linear function",
+              "offset": 1360,
+              "size": 32,
+              "reset_value": 106,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B4": {
+                    "description": "y-intercept of 5th piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "B5": {
+              "description": "y-intercept of 6th piece wise linear function",
+              "offset": 1364,
+              "size": 32,
+              "reset_value": 15824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B5": {
+                    "description": "y-intercept of 6th piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "T0": {
+              "description": "End point of 1st piece wise linear function",
+              "offset": 1376,
+              "size": 32,
+              "reset_value": 226,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0": {
+                    "description": "End point of 1st piece wise linear function",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "T1": {
+              "description": "End point of 2nd piece wise linear function",
+              "offset": 1380,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T1": {
+                    "description": "End point of 2nd piece wise linear function",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "T2": {
+              "description": "End point of 3rd piece wise linear function",
+              "offset": 1384,
+              "size": 32,
+              "reset_value": 20,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T2": {
+                    "description": "End point of 3rd piece wise linear function",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "T3": {
+              "description": "End point of 4th piece wise linear function",
+              "offset": 1388,
+              "size": 32,
+              "reset_value": 25,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T3": {
+                    "description": "End point of 4th piece wise linear function",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "T4": {
+              "description": "End point of 5th piece wise linear function",
+              "offset": 1392,
+              "size": 32,
+              "reset_value": 80,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T4": {
+                    "description": "End point of 5th piece wise linear function",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RNG": {
+        "description": "Random Number Generator",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Task starting the random number generator",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Task stopping the random number generator",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_VALRDY": {
+              "description": "Event being generated for every new random number written to the VALUE register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VALRDY_STOP": {
+                    "description": "Shortcut between VALRDY event and STOP task",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VALRDY": {
+                    "description": "Write '1' to Enable interrupt for VALRDY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VALRDY": {
+                    "description": "Write '1' to Disable interrupt for VALRDY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DERCEN": {
+                    "description": "Bias correction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "VALUE": {
+              "description": "Output random number",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "VALUE": {
+                    "description": "Generated random number",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ECB": {
+        "description": "AES ECB Mode Encryption",
+        "children": {
+          "registers": {
+            "TASKS_STARTECB": {
+              "description": "Start ECB block encrypt",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOPECB": {
+              "description": "Abort a possible executing ECB operation",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_ENDECB": {
+              "description": "ECB block encrypt complete",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ERRORECB": {
+              "description": "ECB block encrypt aborted because of a STOPECB task or due to an error",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDECB": {
+                    "description": "Write '1' to Enable interrupt for ENDECB event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERRORECB": {
+                    "description": "Write '1' to Enable interrupt for ERRORECB event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDECB": {
+                    "description": "Write '1' to Disable interrupt for ENDECB event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERRORECB": {
+                    "description": "Write '1' to Disable interrupt for ERRORECB event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ECBDATAPTR": {
+              "description": "ECB block encrypt memory pointers",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECBDATAPTR": {
+                    "description": "Pointer to the ECB data structure (see Table 1 ECB data structure overview)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CCM": {
+        "description": "AES CCM Mode Encryption",
+        "children": {
+          "registers": {
+            "TASKS_KSGEN": {
+              "description": "Start generation of key-stream. This operation will stop by itself when completed.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_CRYPT": {
+              "description": "Start encryption/decryption. This operation will stop by itself when completed.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop encryption/decryption",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_ENDKSGEN": {
+              "description": "Key-stream generation complete",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ENDCRYPT": {
+              "description": "Encrypt/decrypt complete",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ERROR": {
+              "description": "CCM error event",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDKSGEN_CRYPT": {
+                    "description": "Shortcut between ENDKSGEN event and CRYPT task",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDKSGEN": {
+                    "description": "Write '1' to Enable interrupt for ENDKSGEN event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDCRYPT": {
+                    "description": "Write '1' to Enable interrupt for ENDCRYPT event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Enable interrupt for ERROR event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDKSGEN": {
+                    "description": "Write '1' to Disable interrupt for ENDKSGEN event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDCRYPT": {
+                    "description": "Write '1' to Disable interrupt for ENDCRYPT event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to Disable interrupt for ERROR event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MICSTATUS": {
+              "description": "MIC check result",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "MICSTATUS": {
+                    "description": "The result of the MIC check performed during the previous decryption operation",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "CheckFailed": {
+                            "description": "MIC check failed",
+                            "value": 0
+                          },
+                          "CheckPassed": {
+                            "description": "MIC check passed",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable CCM",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Operation mode",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "The mode of operation to be used",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Encryption": {
+                            "description": "AES CCM packet encryption mode",
+                            "value": 0
+                          },
+                          "Decryption": {
+                            "description": "AES CCM packet decryption mode",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DATARATE": {
+                    "description": "Data rate that the CCM shall run in synch with",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "1Mbit": {
+                            "description": "In synch with 1 Mbit data rate",
+                            "value": 0
+                          },
+                          "2Mbit": {
+                            "description": "In synch with 2 Mbit data rate",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LENGTH": {
+                    "description": "Packet length configuration",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Default": {
+                            "description": "Default length. Effective length of LENGTH field is 5-bit",
+                            "value": 0
+                          },
+                          "Extended": {
+                            "description": "Extended length. Effective length of LENGTH field is 8-bit",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CNFPTR": {
+              "description": "Pointer to data structure holding AES key and NONCE vector",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNFPTR": {
+                    "description": "Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "INPTR": {
+              "description": "Input pointer",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INPTR": {
+                    "description": "Input pointer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OUTPTR": {
+              "description": "Output pointer",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTPTR": {
+                    "description": "Output pointer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SCRATCHPTR": {
+              "description": "Pointer to data area used for temporary storage",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCRATCHPTR": {
+                    "description": "Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "AAR": {
+        "description": "Accelerated Address Resolver",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start resolving addresses based on IRKs specified in the IRK data structure",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop resolving addresses",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_END": {
+              "description": "Address resolution procedure complete",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_RESOLVED": {
+              "description": "Address resolved",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_NOTRESOLVED": {
+              "description": "Address not resolved",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END": {
+                    "description": "Write '1' to Enable interrupt for END event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESOLVED": {
+                    "description": "Write '1' to Enable interrupt for RESOLVED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NOTRESOLVED": {
+                    "description": "Write '1' to Enable interrupt for NOTRESOLVED event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END": {
+                    "description": "Write '1' to Disable interrupt for END event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESOLVED": {
+                    "description": "Write '1' to Disable interrupt for RESOLVED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NOTRESOLVED": {
+                    "description": "Write '1' to Disable interrupt for NOTRESOLVED event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Resolution status",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STATUS": {
+                    "description": "The IRK that was used last time an address was resolved",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable AAR",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable AAR",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "NIRK": {
+              "description": "Number of IRKs",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NIRK": {
+                    "description": "Number of Identity root keys available in the IRK data structure",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "IRKPTR": {
+              "description": "Pointer to IRK data structure",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IRKPTR": {
+                    "description": "Pointer to the IRK data structure",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ADDRPTR": {
+              "description": "Pointer to the resolvable address",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRPTR": {
+                    "description": "Pointer to the resolvable address (6-bytes)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SCRATCHPTR": {
+              "description": "Pointer to data area used for temporary storage",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCRATCHPTR": {
+                    "description": "Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "WDT": {
+        "description": "Watchdog Timer",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start the watchdog",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_TIMEOUT": {
+              "description": "Watchdog timeout",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMEOUT": {
+                    "description": "Write '1' to Enable interrupt for TIMEOUT event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMEOUT": {
+                    "description": "Write '1' to Disable interrupt for TIMEOUT event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RUNSTATUS": {
+              "description": "Run status",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RUNSTATUS": {
+                    "description": "Indicates whether or not the watchdog is running",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotRunning": {
+                            "description": "Watchdog not running",
+                            "value": 0
+                          },
+                          "Running": {
+                            "description": "Watchdog is running",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REQSTATUS": {
+              "description": "Request status",
+              "offset": 1028,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RR0": {
+                    "description": "Request status for RR[0] register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[0] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[0] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR1": {
+                    "description": "Request status for RR[1] register",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[1] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[1] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR2": {
+                    "description": "Request status for RR[2] register",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[2] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[2] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR3": {
+                    "description": "Request status for RR[3] register",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[3] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[3] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR4": {
+                    "description": "Request status for RR[4] register",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[4] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[4] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR5": {
+                    "description": "Request status for RR[5] register",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[5] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[5] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR6": {
+                    "description": "Request status for RR[6] register",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[6] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[6] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR7": {
+                    "description": "Request status for RR[7] register",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[7] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[7] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CRV": {
+              "description": "Counter reload value",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRV": {
+                    "description": "Counter reload value in number of cycles of the 32.768 kHz clock",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RREN": {
+              "description": "Enable register for reload request registers",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RR0": {
+                    "description": "Enable or disable RR[0] register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[0] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[0] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR1": {
+                    "description": "Enable or disable RR[1] register",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[1] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[1] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR2": {
+                    "description": "Enable or disable RR[2] register",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[2] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[2] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR3": {
+                    "description": "Enable or disable RR[3] register",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[3] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[3] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR4": {
+                    "description": "Enable or disable RR[4] register",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[4] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[4] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR5": {
+                    "description": "Enable or disable RR[5] register",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[5] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[5] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR6": {
+                    "description": "Enable or disable RR[6] register",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[6] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[6] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR7": {
+                    "description": "Enable or disable RR[7] register",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[7] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[7] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLEEP": {
+                    "description": "Configure the watchdog to either be paused, or kept running, while the CPU is sleeping",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Pause": {
+                            "description": "Pause watchdog while the CPU is sleeping",
+                            "value": 0
+                          },
+                          "Run": {
+                            "description": "Keep the watchdog running while the CPU is sleeping",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HALT": {
+                    "description": "Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Pause": {
+                            "description": "Pause watchdog while the CPU is halted by the debugger",
+                            "value": 0
+                          },
+                          "Run": {
+                            "description": "Keep the watchdog running while the CPU is halted by the debugger",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RR": {
+              "description": "Description collection[0]:  Reload request 0",
+              "offset": 1536,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "RR": {
+                    "description": "Reload request register",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Reload": {
+                            "description": "Value to request a reload of the watchdog timer",
+                            "value": 1850885685
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PWM0": {
+        "description": "Pulse Width Modulation Unit 0",
+        "children": {
+          "registers": {
+            "TASKS_STOP": {
+              "description": "Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SEQSTART": {
+              "description": "Description collection[0]:  Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running.",
+              "offset": 8,
+              "size": 32,
+              "count": 2,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_NEXTSTEP": {
+              "description": "Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_STOPPED": {
+              "description": "Response to STOP task, emitted when PWM pulses are no longer generated",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_SEQSTARTED": {
+              "description": "Description collection[0]:  First PWM period started on sequence 0",
+              "offset": 264,
+              "size": 32,
+              "count": 2,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_SEQEND": {
+              "description": "Description collection[0]:  Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter",
+              "offset": 272,
+              "size": 32,
+              "count": 2,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_PWMPERIODEND": {
+              "description": "Emitted at the end of each PWM period",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_LOOPSDONE": {
+              "description": "Concatenated sequences have been played the amount of times defined in LOOP.CNT",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEQEND0_STOP": {
+                    "description": "Shortcut between SEQEND[0] event and STOP task",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND1_STOP": {
+                    "description": "Shortcut between SEQEND[1] event and STOP task",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE_SEQSTART0": {
+                    "description": "Shortcut between LOOPSDONE event and SEQSTART[0] task",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE_SEQSTART1": {
+                    "description": "Shortcut between LOOPSDONE event and SEQSTART[1] task",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE_STOP": {
+                    "description": "Shortcut between LOOPSDONE event and STOP task",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED0": {
+                    "description": "Enable or disable interrupt for SEQSTARTED[0] event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED1": {
+                    "description": "Enable or disable interrupt for SEQSTARTED[1] event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND0": {
+                    "description": "Enable or disable interrupt for SEQEND[0] event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND1": {
+                    "description": "Enable or disable interrupt for SEQEND[1] event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMPERIODEND": {
+                    "description": "Enable or disable interrupt for PWMPERIODEND event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE": {
+                    "description": "Enable or disable interrupt for LOOPSDONE event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to Enable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED0": {
+                    "description": "Write '1' to Enable interrupt for SEQSTARTED[0] event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED1": {
+                    "description": "Write '1' to Enable interrupt for SEQSTARTED[1] event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND0": {
+                    "description": "Write '1' to Enable interrupt for SEQEND[0] event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND1": {
+                    "description": "Write '1' to Enable interrupt for SEQEND[1] event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMPERIODEND": {
+                    "description": "Write '1' to Enable interrupt for PWMPERIODEND event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE": {
+                    "description": "Write '1' to Enable interrupt for LOOPSDONE event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to Disable interrupt for STOPPED event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED0": {
+                    "description": "Write '1' to Disable interrupt for SEQSTARTED[0] event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED1": {
+                    "description": "Write '1' to Disable interrupt for SEQSTARTED[1] event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND0": {
+                    "description": "Write '1' to Disable interrupt for SEQEND[0] event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND1": {
+                    "description": "Write '1' to Disable interrupt for SEQEND[1] event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMPERIODEND": {
+                    "description": "Write '1' to Disable interrupt for PWMPERIODEND event",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE": {
+                    "description": "Write '1' to Disable interrupt for LOOPSDONE event",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "PWM module enable register",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable PWM module",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Selects operating mode of the wave counter",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UPDOWN": {
+                    "description": "Selects up or up and down as wave counter mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Up": {
+                            "description": "Up counter - edge aligned PWM duty-cycle",
+                            "value": 0
+                          },
+                          "UpAndDown": {
+                            "description": "Up and down counter - center aligned PWM duty cycle",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "COUNTERTOP": {
+              "description": "Value up to which the pulse generator counter counts",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 1023,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COUNTERTOP": {
+                    "description": "Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used.",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "PRESCALER": {
+              "description": "Configuration for PWM_CLK",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRESCALER": {
+                    "description": "Pre-scaler of PWM_CLK",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "DIV_1": {
+                            "description": "Divide by   1 (16MHz)",
+                            "value": 0
+                          },
+                          "DIV_2": {
+                            "description": "Divide by   2 ( 8MHz)",
+                            "value": 1
+                          },
+                          "DIV_4": {
+                            "description": "Divide by   4 ( 4MHz)",
+                            "value": 2
+                          },
+                          "DIV_8": {
+                            "description": "Divide by   8 ( 2MHz)",
+                            "value": 3
+                          },
+                          "DIV_16": {
+                            "description": "Divide by  16 ( 1MHz)",
+                            "value": 4
+                          },
+                          "DIV_32": {
+                            "description": "Divide by  32 ( 500kHz)",
+                            "value": 5
+                          },
+                          "DIV_64": {
+                            "description": "Divide by  64 ( 250kHz)",
+                            "value": 6
+                          },
+                          "DIV_128": {
+                            "description": "Divide by 128 ( 125kHz)",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DECODER": {
+              "description": "Configuration of the decoder",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOAD": {
+                    "description": "How a sequence is read from RAM and spread to the compare register",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Common": {
+                            "description": "1st half word (16-bit) used in all PWM channels 0..3",
+                            "value": 0
+                          },
+                          "Grouped": {
+                            "description": "1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3",
+                            "value": 1
+                          },
+                          "Individual": {
+                            "description": "1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3",
+                            "value": 2
+                          },
+                          "WaveForm": {
+                            "description": "1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MODE": {
+                    "description": "Selects source for advancing the active sequence",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RefreshCount": {
+                            "description": "SEQ[n].REFRESH is used to determine loading internal compare registers",
+                            "value": 0
+                          },
+                          "NextStep": {
+                            "description": "NEXTSTEP task causes a new value to be loaded to internal compare registers",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LOOP": {
+              "description": "Amount of playback of a loop",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Amount of playback of pattern cycles",
+                    "offset": 0,
+                    "size": 16,
+                    "enum": {
+                      "size": 16,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Looping disabled (stop at the end of the sequence)",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "QDEC": {
+        "description": "Quadrature Decoder",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Task starting the quadrature decoder",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Task stopping the quadrature decoder",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_READCLRACC": {
+              "description": "Read and clear ACC and ACCDBL",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_RDCLRACC": {
+              "description": "Read and clear ACC",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_RDCLRDBL": {
+              "description": "Read and clear ACCDBL",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_SAMPLERDY": {
+              "description": "Event being generated for every new sample value written to the SAMPLE register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_REPORTRDY": {
+              "description": "Non-null report ready",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_ACCOF": {
+              "description": "ACC or ACCDBL register overflow",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_DBLRDY": {
+              "description": "Double displacement(s) detected",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_STOPPED": {
+              "description": "QDEC has been stopped",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REPORTRDY_READCLRACC": {
+                    "description": "Shortcut between REPORTRDY event and READCLRACC task",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SAMPLERDY_STOP": {
+                    "description": "Shortcut between SAMPLERDY event and STOP task",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REPORTRDY_RDCLRACC": {
+                    "description": "Shortcut between REPORTRDY event and RDCLRACC task",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REPORTRDY_STOP": {
+                    "description": "Shortcut between REPORTRDY event and STOP task",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DBLRDY_RDCLRDBL": {
+                    "description": "Shortcut between DBLRDY event and RDCLRDBL task",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DBLRDY_STOP": {
+                    "description": "Shortcut between DBLRDY event and STOP task",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SAMPLERDY_READCLRACC": {
+                    "description": "Shortcut between SAMPLERDY event and READCLRACC task",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SAMPLERDY": {
+                    "description": "Write '1' to Enable interrupt for SAMPLERDY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REPORTRDY": {
+                    "description": "Write '1' to Enable interrupt for REPORTRDY event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ACCOF": {
+                    "description": "Write '1' to Enable interrupt for ACCOF event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DBLRDY": {
+                    "description": "Write '1' to Enable interrupt for DBLRDY event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to Enable interrupt for STOPPED event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SAMPLERDY": {
+                    "description": "Write '1' to Disable interrupt for SAMPLERDY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REPORTRDY": {
+                    "description": "Write '1' to Disable interrupt for REPORTRDY event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ACCOF": {
+                    "description": "Write '1' to Disable interrupt for ACCOF event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DBLRDY": {
+                    "description": "Write '1' to Disable interrupt for DBLRDY event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to Disable interrupt for STOPPED event",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable the quadrature decoder",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable the quadrature decoder",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LEDPOL": {
+              "description": "LED output pin polarity",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEDPOL": {
+                    "description": "LED output pin polarity",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ActiveLow": {
+                            "description": "Led active on output pin low",
+                            "value": 0
+                          },
+                          "ActiveHigh": {
+                            "description": "Led active on output pin high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SAMPLEPER": {
+              "description": "Sample period",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SAMPLEPER": {
+                    "description": "Sample period. The SAMPLE register will be updated for every new sample",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "128us": {
+                            "description": "128 us",
+                            "value": 0
+                          },
+                          "256us": {
+                            "description": "256 us",
+                            "value": 1
+                          },
+                          "512us": {
+                            "description": "512 us",
+                            "value": 2
+                          },
+                          "1024us": {
+                            "description": "1024 us",
+                            "value": 3
+                          },
+                          "2048us": {
+                            "description": "2048 us",
+                            "value": 4
+                          },
+                          "4096us": {
+                            "description": "4096 us",
+                            "value": 5
+                          },
+                          "8192us": {
+                            "description": "8192 us",
+                            "value": 6
+                          },
+                          "16384us": {
+                            "description": "16384 us",
+                            "value": 7
+                          },
+                          "32ms": {
+                            "description": "32768 us",
+                            "value": 8
+                          },
+                          "65ms": {
+                            "description": "65536 us",
+                            "value": 9
+                          },
+                          "131ms": {
+                            "description": "131072 us",
+                            "value": 10
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SAMPLE": {
+              "description": "Motion sample value",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SAMPLE": {
+                    "description": "Last motion sample",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REPORTPER": {
+              "description": "Number of samples to be taken before REPORTRDY and DBLRDY events can be generated",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REPORTPER": {
+                    "description": "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "10Smpl": {
+                            "description": "10 samples / report",
+                            "value": 0
+                          },
+                          "40Smpl": {
+                            "description": "40 samples / report",
+                            "value": 1
+                          },
+                          "80Smpl": {
+                            "description": "80 samples / report",
+                            "value": 2
+                          },
+                          "120Smpl": {
+                            "description": "120 samples / report",
+                            "value": 3
+                          },
+                          "160Smpl": {
+                            "description": "160 samples / report",
+                            "value": 4
+                          },
+                          "200Smpl": {
+                            "description": "200 samples / report",
+                            "value": 5
+                          },
+                          "240Smpl": {
+                            "description": "240 samples / report",
+                            "value": 6
+                          },
+                          "280Smpl": {
+                            "description": "280 samples / report",
+                            "value": 7
+                          },
+                          "1Smpl": {
+                            "description": "1 sample / report",
+                            "value": 8
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ACC": {
+              "description": "Register accumulating the valid transitions",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACC": {
+                    "description": "Register accumulating all valid samples (not double transition) read from the SAMPLE register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ACCREAD": {
+              "description": "Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACCREAD": {
+                    "description": "Snapshot of the ACC register.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DBFEN": {
+              "description": "Enable input debounce filters",
+              "offset": 1320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBFEN": {
+                    "description": "Enable input debounce filters",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Debounce input filters disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Debounce input filters enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LEDPRE": {
+              "description": "Time period the LED is switched ON prior to sampling",
+              "offset": 1344,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEDPRE": {
+                    "description": "Period in us the LED is switched on prior to sampling",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "ACCDBL": {
+              "description": "Register accumulating the number of detected double transitions",
+              "offset": 1348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACCDBL": {
+                    "description": "Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "ACCDBLREAD": {
+              "description": "Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task",
+              "offset": 1352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACCDBLREAD": {
+                    "description": "Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "COMP": {
+        "description": "Comparator",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start comparator",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop comparator",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SAMPLE": {
+              "description": "Sample comparator value",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_READY": {
+              "description": "COMP is ready and output is valid",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_DOWN": {
+              "description": "Downward crossing",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_UP": {
+              "description": "Upward crossing",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_CROSS": {
+              "description": "Downward or upward crossing",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY_SAMPLE": {
+                    "description": "Shortcut between READY event and SAMPLE task",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READY_STOP": {
+                    "description": "Shortcut between READY event and STOP task",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN_STOP": {
+                    "description": "Shortcut between DOWN event and STOP task",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP_STOP": {
+                    "description": "Shortcut between UP event and STOP task",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS_STOP": {
+                    "description": "Shortcut between CROSS event and STOP task",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Enable or disable interrupt for READY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN": {
+                    "description": "Enable or disable interrupt for DOWN event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP": {
+                    "description": "Enable or disable interrupt for UP event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS": {
+                    "description": "Enable or disable interrupt for CROSS event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to Enable interrupt for READY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN": {
+                    "description": "Write '1' to Enable interrupt for DOWN event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP": {
+                    "description": "Write '1' to Enable interrupt for UP event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS": {
+                    "description": "Write '1' to Enable interrupt for CROSS event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to Disable interrupt for READY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN": {
+                    "description": "Write '1' to Disable interrupt for DOWN event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP": {
+                    "description": "Write '1' to Disable interrupt for UP event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS": {
+                    "description": "Write '1' to Disable interrupt for CROSS event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RESULT": {
+              "description": "Compare result",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RESULT": {
+                    "description": "Result of last compare. Decision point SAMPLE task.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Below": {
+                            "description": "Input voltage is below the threshold (VIN+ < VIN-)",
+                            "value": 0
+                          },
+                          "Above": {
+                            "description": "Input voltage is above the threshold (VIN+ > VIN-)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "COMP enable",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable COMP",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PSEL": {
+              "description": "Pin select",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSEL": {
+                    "description": "Analog pin select",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "AnalogInput0": {
+                            "description": "AIN0 selected as analog input",
+                            "value": 0
+                          },
+                          "AnalogInput1": {
+                            "description": "AIN1 selected as analog input",
+                            "value": 1
+                          },
+                          "AnalogInput2": {
+                            "description": "AIN2 selected as analog input",
+                            "value": 2
+                          },
+                          "AnalogInput3": {
+                            "description": "AIN3 selected as analog input",
+                            "value": 3
+                          },
+                          "AnalogInput4": {
+                            "description": "AIN4 selected as analog input",
+                            "value": 4
+                          },
+                          "AnalogInput5": {
+                            "description": "AIN5 selected as analog input",
+                            "value": 5
+                          },
+                          "AnalogInput6": {
+                            "description": "AIN6 selected as analog input",
+                            "value": 6
+                          },
+                          "AnalogInput7": {
+                            "description": "AIN7 selected as analog input",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REFSEL": {
+              "description": "Reference source select for single-ended mode",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REFSEL": {
+                    "description": "Reference select",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "Int1V2": {
+                            "description": "VREF = internal 1.2 V reference (VDD >= 1.7 V)",
+                            "value": 0
+                          },
+                          "Int1V8": {
+                            "description": "VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)",
+                            "value": 1
+                          },
+                          "Int2V4": {
+                            "description": "VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)",
+                            "value": 2
+                          },
+                          "VDD": {
+                            "description": "VREF = VDD",
+                            "value": 4
+                          },
+                          "ARef": {
+                            "description": "VREF = AREF (VDD >= VREF >= AREFMIN)",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EXTREFSEL": {
+              "description": "External reference select",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTREFSEL": {
+                    "description": "External analog reference select",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "AnalogReference0": {
+                            "description": "Use AIN0 as external analog reference",
+                            "value": 0
+                          },
+                          "AnalogReference1": {
+                            "description": "Use AIN1 as external analog reference",
+                            "value": 1
+                          },
+                          "AnalogReference2": {
+                            "description": "Use AIN2 as external analog reference",
+                            "value": 2
+                          },
+                          "AnalogReference3": {
+                            "description": "Use AIN3 as external analog reference",
+                            "value": 3
+                          },
+                          "AnalogReference4": {
+                            "description": "Use AIN4 as external analog reference",
+                            "value": 4
+                          },
+                          "AnalogReference5": {
+                            "description": "Use AIN5 as external analog reference",
+                            "value": 5
+                          },
+                          "AnalogReference6": {
+                            "description": "Use AIN6 as external analog reference",
+                            "value": 6
+                          },
+                          "AnalogReference7": {
+                            "description": "Use AIN7 as external analog reference",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TH": {
+              "description": "Threshold configuration for hysteresis unit",
+              "offset": 1328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "THDOWN": {
+                    "description": "VDOWN = (THDOWN+1)/64*VREF",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "THUP": {
+                    "description": "VUP = (THUP+1)/64*VREF",
+                    "offset": 8,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Mode configuration",
+              "offset": 1332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SP": {
+                    "description": "Speed and power modes",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Low-power mode",
+                            "value": 0
+                          },
+                          "Normal": {
+                            "description": "Normal mode",
+                            "value": 1
+                          },
+                          "High": {
+                            "description": "High-speed mode",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MAIN": {
+                    "description": "Main operation modes",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "SE": {
+                            "description": "Single-ended mode",
+                            "value": 0
+                          },
+                          "Diff": {
+                            "description": "Differential mode",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "HYST": {
+              "description": "Comparator hysteresis enable",
+              "offset": 1336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HYST": {
+                    "description": "Comparator hysteresis",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoHyst": {
+                            "description": "Comparator hysteresis disabled",
+                            "value": 0
+                          },
+                          "Hyst50mV": {
+                            "description": "Comparator hysteresis enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ISOURCE": {
+              "description": "Current source select on analog input",
+              "offset": 1340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ISOURCE": {
+                    "description": "Comparator hysteresis",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Off": {
+                            "description": "Current source disabled",
+                            "value": 0
+                          },
+                          "Ien2mA5": {
+                            "description": "Current source enabled (+/- 2.5 uA)",
+                            "value": 1
+                          },
+                          "Ien5mA": {
+                            "description": "Current source enabled (+/- 5 uA)",
+                            "value": 2
+                          },
+                          "Ien10mA": {
+                            "description": "Current source enabled (+/- 10 uA)",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "LPCOMP": {
+        "description": "Low Power Comparator",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start comparator",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_STOP": {
+              "description": "Stop comparator",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "TASKS_SAMPLE": {
+              "description": "Sample comparator value",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only"
+            },
+            "EVENTS_READY": {
+              "description": "LPCOMP is ready and output is valid",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_DOWN": {
+              "description": "Downward crossing",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_UP": {
+              "description": "Upward crossing",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "EVENTS_CROSS": {
+              "description": "Downward or upward crossing",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SHORTS": {
+              "description": "Shortcut register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY_SAMPLE": {
+                    "description": "Shortcut between READY event and SAMPLE task",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READY_STOP": {
+                    "description": "Shortcut between READY event and STOP task",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN_STOP": {
+                    "description": "Shortcut between DOWN event and STOP task",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP_STOP": {
+                    "description": "Shortcut between UP event and STOP task",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS_STOP": {
+                    "description": "Shortcut between CROSS event and STOP task",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to Enable interrupt for READY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN": {
+                    "description": "Write '1' to Enable interrupt for DOWN event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP": {
+                    "description": "Write '1' to Enable interrupt for UP event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS": {
+                    "description": "Write '1' to Enable interrupt for CROSS event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to Disable interrupt for READY event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN": {
+                    "description": "Write '1' to Disable interrupt for DOWN event",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP": {
+                    "description": "Write '1' to Disable interrupt for UP event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS": {
+                    "description": "Write '1' to Disable interrupt for CROSS event",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RESULT": {
+              "description": "Compare result",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RESULT": {
+                    "description": "Result of last compare. Decision point SAMPLE task.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Below": {
+                            "description": "Input voltage is below the reference threshold (VIN+ < VIN-).",
+                            "value": 0
+                          },
+                          "Above": {
+                            "description": "Input voltage is above the reference threshold (VIN+ > VIN-).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable LPCOMP",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable LPCOMP",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PSEL": {
+              "description": "Input pin select",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSEL": {
+                    "description": "Analog pin select",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "AnalogInput0": {
+                            "description": "AIN0 selected as analog input",
+                            "value": 0
+                          },
+                          "AnalogInput1": {
+                            "description": "AIN1 selected as analog input",
+                            "value": 1
+                          },
+                          "AnalogInput2": {
+                            "description": "AIN2 selected as analog input",
+                            "value": 2
+                          },
+                          "AnalogInput3": {
+                            "description": "AIN3 selected as analog input",
+                            "value": 3
+                          },
+                          "AnalogInput4": {
+                            "description": "AIN4 selected as analog input",
+                            "value": 4
+                          },
+                          "AnalogInput5": {
+                            "description": "AIN5 selected as analog input",
+                            "value": 5
+                          },
+                          "AnalogInput6": {
+                            "description": "AIN6 selected as analog input",
+                            "value": 6
+                          },
+                          "AnalogInput7": {
+                            "description": "AIN7 selected as analog input",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REFSEL": {
+              "description": "Reference select",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REFSEL": {
+                    "description": "Reference select",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Ref1_8Vdd": {
+                            "description": "VDD * 1/8 selected as reference",
+                            "value": 0
+                          },
+                          "Ref2_8Vdd": {
+                            "description": "VDD * 2/8 selected as reference",
+                            "value": 1
+                          },
+                          "Ref3_8Vdd": {
+                            "description": "VDD * 3/8 selected as reference",
+                            "value": 2
+                          },
+                          "Ref4_8Vdd": {
+                            "description": "VDD * 4/8 selected as reference",
+                            "value": 3
+                          },
+                          "Ref5_8Vdd": {
+                            "description": "VDD * 5/8 selected as reference",
+                            "value": 4
+                          },
+                          "Ref6_8Vdd": {
+                            "description": "VDD * 6/8 selected as reference",
+                            "value": 5
+                          },
+                          "Ref7_8Vdd": {
+                            "description": "VDD * 7/8 selected as reference",
+                            "value": 6
+                          },
+                          "ARef": {
+                            "description": "External analog reference selected",
+                            "value": 7
+                          },
+                          "Ref1_16Vdd": {
+                            "description": "VDD * 1/16 selected as reference",
+                            "value": 8
+                          },
+                          "Ref3_16Vdd": {
+                            "description": "VDD * 3/16 selected as reference",
+                            "value": 9
+                          },
+                          "Ref5_16Vdd": {
+                            "description": "VDD * 5/16 selected as reference",
+                            "value": 10
+                          },
+                          "Ref7_16Vdd": {
+                            "description": "VDD * 7/16 selected as reference",
+                            "value": 11
+                          },
+                          "Ref9_16Vdd": {
+                            "description": "VDD * 9/16 selected as reference",
+                            "value": 12
+                          },
+                          "Ref11_16Vdd": {
+                            "description": "VDD * 11/16 selected as reference",
+                            "value": 13
+                          },
+                          "Ref13_16Vdd": {
+                            "description": "VDD * 13/16 selected as reference",
+                            "value": 14
+                          },
+                          "Ref15_16Vdd": {
+                            "description": "VDD * 15/16 selected as reference",
+                            "value": 15
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EXTREFSEL": {
+              "description": "External reference select",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTREFSEL": {
+                    "description": "External analog reference select",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "AnalogReference0": {
+                            "description": "Use AIN0 as external analog reference",
+                            "value": 0
+                          },
+                          "AnalogReference1": {
+                            "description": "Use AIN1 as external analog reference",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ANADETECT": {
+              "description": "Analog detect configuration",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ANADETECT": {
+                    "description": "Analog detect configuration",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Cross": {
+                            "description": "Generate ANADETECT on crossing, both upward crossing and downward crossing",
+                            "value": 0
+                          },
+                          "Up": {
+                            "description": "Generate ANADETECT on upward crossing only",
+                            "value": 1
+                          },
+                          "Down": {
+                            "description": "Generate ANADETECT on downward crossing only",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "HYST": {
+              "description": "Comparator hysteresis enable",
+              "offset": 1336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HYST": {
+                    "description": "Comparator hysteresis enable",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoHyst": {
+                            "description": "Comparator hysteresis disabled",
+                            "value": 0
+                          },
+                          "Hyst50mV": {
+                            "description": "Comparator hysteresis disabled (typ. 50 mV)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SWI0": {
+        "description": "Software interrupt 0",
+        "children": {
+          "registers": {
+            "UNUSED": {
+              "description": "Unused.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only"
+            }
+          }
+        }
+      }
+    }
+  },
+  "devices": {
+    "nrf52": {
+      "arch": "cortex_m4",
+      "description": "nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller ",
+      "properties": {
+        "cpu.nvic_prio_bits": "3",
+        "cpu.mpu": "1",
+        "cpu.fpu": "1",
+        "cpu.revision": "r0p1",
+        "cpu.vendor_systick_config": "0",
+        "license": "\nCopyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\\n\n\\n\nRedistribution and use in source and binary forms, with or without\\n\nmodification, are permitted provided that the following conditions are met:\\n\n\\n\n1. Redistributions of source code must retain the above copyright notice, this\\n\n   list of conditions and the following disclaimer.\\n\n\\n\n2. Redistributions in binary form must reproduce the above copyright\\n\n   notice, this list of conditions and the following disclaimer in the\\n\n   documentation and/or other materials provided with the distribution.\\n\n\\n\n3. Neither the name of Nordic Semiconductor ASA nor the names of its\\n\n   contributors may be used to endorse or promote products derived from this\\n\n   software without specific prior written permission.\\n\n\\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\\n\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\\n\nIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\\n\nARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\\n\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\\n\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\\n\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\\n\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\\n\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\\n\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\\n\nPOSSIBILITY OF SUCH DAMAGE.\\n\n        ",
+        "cpu.name": "CM4",
+        "cpu.endian": "little"
+      },
+      "children": {
+        "interrupts": {
+          "MemManageFault": {
+            "index": -12
+          },
+          "BusFault": {
+            "index": -11
+          },
+          "UsageFault": {
+            "index": -10
+          },
+          "DebugMonitor": {
+            "index": -4
+          },
+          "NMI": {
+            "index": -14
+          },
+          "HardFault": {
+            "index": -13
+          },
+          "SVCall": {
+            "index": -5
+          },
+          "PendSV": {
+            "index": -2
+          },
+          "SysTick": {
+            "index": -1
+          },
+          "POWER_CLOCK": {
+            "index": 0
+          },
+          "RADIO": {
+            "index": 1
+          },
+          "UARTE0_UART0": {
+            "index": 2
+          },
+          "SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0": {
+            "index": 3
+          },
+          "SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1": {
+            "index": 4
+          },
+          "NFCT": {
+            "index": 5
+          },
+          "GPIOTE": {
+            "index": 6
+          },
+          "SAADC": {
+            "index": 7
+          },
+          "TIMER0": {
+            "index": 8
+          },
+          "TIMER1": {
+            "index": 9
+          },
+          "TIMER2": {
+            "index": 10
+          },
+          "RTC0": {
+            "index": 11
+          },
+          "TEMP": {
+            "index": 12
+          },
+          "RNG": {
+            "index": 13
+          },
+          "ECB": {
+            "index": 14
+          },
+          "CCM_AAR": {
+            "index": 15
+          },
+          "WDT": {
+            "index": 16
+          },
+          "RTC1": {
+            "index": 17
+          },
+          "QDEC": {
+            "index": 18
+          },
+          "COMP_LPCOMP": {
+            "index": 19
+          },
+          "SWI0_EGU0": {
+            "index": 20
+          },
+          "SWI1_EGU1": {
+            "index": 21
+          },
+          "SWI2_EGU2": {
+            "index": 22
+          },
+          "SWI3_EGU3": {
+            "index": 23
+          },
+          "SWI4_EGU4": {
+            "index": 24
+          },
+          "SWI5_EGU5": {
+            "index": 25
+          },
+          "TIMER3": {
+            "index": 26
+          },
+          "TIMER4": {
+            "index": 27
+          },
+          "PWM0": {
+            "index": 28
+          },
+          "PDM": {
+            "index": 29
+          },
+          "MWU": {
+            "index": 32
+          },
+          "PWM1": {
+            "index": 33
+          },
+          "PWM2": {
+            "index": 34
+          },
+          "SPIM2_SPIS2_SPI2": {
+            "index": 35
+          },
+          "RTC2": {
+            "index": 36
+          },
+          "I2S": {
+            "index": 37
+          },
+          "FPU": {
+            "index": 38
+          }
+        },
+        "peripheral_instances": {
+          "SysTick": {
+            "offset": 3758153744,
+            "type": "types.peripherals.SCS.children.register_groups.SysTick"
+          },
+          "FICR": {
+            "description": "Factory Information Configuration Registers",
+            "offset": 268435456,
+            "type": "types.peripherals.FICR"
+          },
+          "UICR": {
+            "description": "User Information Configuration Registers",
+            "offset": 268439552,
+            "type": "types.peripherals.UICR"
+          },
+          "BPROT": {
+            "description": "Block Protect",
+            "offset": 1073741824,
+            "type": "types.peripherals.BPROT"
+          },
+          "POWER": {
+            "description": "Power control",
+            "offset": 1073741824,
+            "type": "types.peripherals.POWER"
+          },
+          "CLOCK": {
+            "description": "Clock control",
+            "offset": 1073741824,
+            "type": "types.peripherals.CLOCK"
+          },
+          "RADIO": {
+            "description": "2.4 GHz Radio",
+            "offset": 1073745920,
+            "type": "types.peripherals.RADIO"
+          },
+          "UARTE0": {
+            "description": "UART with EasyDMA",
+            "offset": 1073750016,
+            "type": "types.peripherals.UARTE0"
+          },
+          "UART0": {
+            "description": "Universal Asynchronous Receiver/Transmitter",
+            "offset": 1073750016,
+            "type": "types.peripherals.UART0"
+          },
+          "SPIM0": {
+            "description": "Serial Peripheral Interface Master with EasyDMA 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.SPIM0"
+          },
+          "SPIS0": {
+            "description": "SPI Slave 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.SPIS0"
+          },
+          "TWIM0": {
+            "description": "I2C compatible Two-Wire Master Interface with EasyDMA 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.TWIM0"
+          },
+          "TWIS0": {
+            "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.TWIS0"
+          },
+          "SPI0": {
+            "description": "Serial Peripheral Interface 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.SPI0"
+          },
+          "TWI0": {
+            "description": "I2C compatible Two-Wire Interface 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.TWI0"
+          },
+          "SPIM1": {
+            "description": "Serial Peripheral Interface Master with EasyDMA 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.SPIM0"
+          },
+          "SPIS1": {
+            "description": "SPI Slave 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.SPIS0"
+          },
+          "TWIM1": {
+            "description": "I2C compatible Two-Wire Master Interface with EasyDMA 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.TWIM0"
+          },
+          "TWIS1": {
+            "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.TWIS0"
+          },
+          "SPI1": {
+            "description": "Serial Peripheral Interface 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.SPI0"
+          },
+          "TWI1": {
+            "description": "I2C compatible Two-Wire Interface 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.TWI0"
+          },
+          "NFCT": {
+            "description": "NFC-A compatible radio",
+            "offset": 1073762304,
+            "type": "types.peripherals.NFCT"
+          },
+          "GPIOTE": {
+            "description": "GPIO Tasks and Events",
+            "offset": 1073766400,
+            "type": "types.peripherals.GPIOTE"
+          },
+          "SAADC": {
+            "description": "Analog to Digital Converter",
+            "offset": 1073770496,
+            "type": "types.peripherals.SAADC"
+          },
+          "TIMER0": {
+            "description": "Timer/Counter 0",
+            "offset": 1073774592,
+            "type": "types.peripherals.TIMER0"
+          },
+          "TIMER1": {
+            "description": "Timer/Counter 1",
+            "offset": 1073778688,
+            "type": "types.peripherals.TIMER0"
+          },
+          "TIMER2": {
+            "description": "Timer/Counter 2",
+            "offset": 1073782784,
+            "type": "types.peripherals.TIMER0"
+          },
+          "RTC0": {
+            "description": "Real time counter 0",
+            "offset": 1073786880,
+            "type": "types.peripherals.RTC0"
+          },
+          "TEMP": {
+            "description": "Temperature Sensor",
+            "offset": 1073790976,
+            "type": "types.peripherals.TEMP"
+          },
+          "RNG": {
+            "description": "Random Number Generator",
+            "offset": 1073795072,
+            "type": "types.peripherals.RNG"
+          },
+          "ECB": {
+            "description": "AES ECB Mode Encryption",
+            "offset": 1073799168,
+            "type": "types.peripherals.ECB"
+          },
+          "CCM": {
+            "description": "AES CCM Mode Encryption",
+            "offset": 1073803264,
+            "type": "types.peripherals.CCM"
+          },
+          "AAR": {
+            "description": "Accelerated Address Resolver",
+            "offset": 1073803264,
+            "type": "types.peripherals.AAR"
+          },
+          "WDT": {
+            "description": "Watchdog Timer",
+            "offset": 1073807360,
+            "type": "types.peripherals.WDT"
+          },
+          "RTC1": {
+            "description": "Real time counter 1",
+            "offset": 1073811456,
+            "type": "types.peripherals.RTC0"
+          },
+          "QDEC": {
+            "description": "Quadrature Decoder",
+            "offset": 1073815552,
+            "type": "types.peripherals.QDEC"
+          },
+          "COMP": {
+            "description": "Comparator",
+            "offset": 1073819648,
+            "type": "types.peripherals.COMP"
+          },
+          "LPCOMP": {
+            "description": "Low Power Comparator",
+            "offset": 1073819648,
+            "type": "types.peripherals.LPCOMP"
+          },
+          "SWI0": {
+            "description": "Software interrupt 0",
+            "offset": 1073823744,
+            "type": "types.peripherals.SWI0"
+          },
+          "EGU0": {
+            "description": "Event Generator Unit 0",
+            "offset": 1073823744,
+            "type": "types.peripherals.EGU0"
+          },
+          "SWI1": {
+            "description": "Software interrupt 1",
+            "offset": 1073827840,
+            "type": "types.peripherals.SWI0"
+          },
+          "EGU1": {
+            "description": "Event Generator Unit 1",
+            "offset": 1073827840,
+            "type": "types.peripherals.EGU0"
+          },
+          "SWI2": {
+            "description": "Software interrupt 2",
+            "offset": 1073831936,
+            "type": "types.peripherals.SWI0"
+          },
+          "EGU2": {
+            "description": "Event Generator Unit 2",
+            "offset": 1073831936,
+            "type": "types.peripherals.EGU0"
+          },
+          "SWI3": {
+            "description": "Software interrupt 3",
+            "offset": 1073836032,
+            "type": "types.peripherals.SWI0"
+          },
+          "EGU3": {
+            "description": "Event Generator Unit 3",
+            "offset": 1073836032,
+            "type": "types.peripherals.EGU0"
+          },
+          "SWI4": {
+            "description": "Software interrupt 4",
+            "offset": 1073840128,
+            "type": "types.peripherals.SWI0"
+          },
+          "EGU4": {
+            "description": "Event Generator Unit 4",
+            "offset": 1073840128,
+            "type": "types.peripherals.EGU0"
+          },
+          "SWI5": {
+            "description": "Software interrupt 5",
+            "offset": 1073844224,
+            "type": "types.peripherals.SWI0"
+          },
+          "EGU5": {
+            "description": "Event Generator Unit 5",
+            "offset": 1073844224,
+            "type": "types.peripherals.EGU0"
+          },
+          "TIMER3": {
+            "description": "Timer/Counter 3",
+            "offset": 1073848320,
+            "type": "types.peripherals.TIMER0"
+          },
+          "TIMER4": {
+            "description": "Timer/Counter 4",
+            "offset": 1073852416,
+            "type": "types.peripherals.TIMER0"
+          },
+          "PWM0": {
+            "description": "Pulse Width Modulation Unit 0",
+            "offset": 1073856512,
+            "type": "types.peripherals.PWM0"
+          },
+          "PDM": {
+            "description": "Pulse Density Modulation (Digital Microphone) Interface",
+            "offset": 1073860608,
+            "type": "types.peripherals.PDM"
+          },
+          "NVMC": {
+            "description": "Non Volatile Memory Controller",
+            "offset": 1073864704,
+            "type": "types.peripherals.NVMC"
+          },
+          "PPI": {
+            "description": "Programmable Peripheral Interconnect",
+            "offset": 1073868800,
+            "type": "types.peripherals.PPI"
+          },
+          "MWU": {
+            "description": "Memory Watch Unit",
+            "offset": 1073872896,
+            "type": "types.peripherals.MWU"
+          },
+          "PWM1": {
+            "description": "Pulse Width Modulation Unit 1",
+            "offset": 1073876992,
+            "type": "types.peripherals.PWM0"
+          },
+          "PWM2": {
+            "description": "Pulse Width Modulation Unit 2",
+            "offset": 1073881088,
+            "type": "types.peripherals.PWM0"
+          },
+          "SPIM2": {
+            "description": "Serial Peripheral Interface Master with EasyDMA 2",
+            "offset": 1073885184,
+            "type": "types.peripherals.SPIM0"
+          },
+          "SPIS2": {
+            "description": "SPI Slave 2",
+            "offset": 1073885184,
+            "type": "types.peripherals.SPIS0"
+          },
+          "SPI2": {
+            "description": "Serial Peripheral Interface 2",
+            "offset": 1073885184,
+            "type": "types.peripherals.SPI0"
+          },
+          "RTC2": {
+            "description": "Real time counter 2",
+            "offset": 1073889280,
+            "type": "types.peripherals.RTC0"
+          },
+          "I2S": {
+            "description": "Inter-IC Sound",
+            "offset": 1073893376,
+            "type": "types.peripherals.I2S"
+          },
+          "FPU": {
+            "description": "FPU",
+            "offset": 1073897472,
+            "type": "types.peripherals.FPU"
+          },
+          "P0": {
+            "description": "GPIO Port 1",
+            "offset": 1342177280,
+            "type": "types.peripherals.P0"
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/chips/nrf52.zig b/src/chips/nrf52.zig
new file mode 100644
index 000000000..1e3de3bc8
--- /dev/null
+++ b/src/chips/nrf52.zig
@@ -0,0 +1,16821 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    ///  nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller
+    pub const nrf52 = struct {
+        pub const properties = struct {
+            pub const @"cpu.nvic_prio_bits" = "3";
+            pub const @"cpu.mpu" = "1";
+            pub const @"cpu.fpu" = "1";
+            pub const @"cpu.revision" = "r0p1";
+            pub const @"cpu.vendor_systick_config" = "0";
+            pub const license =
+                \\
+                \\Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n
+                \\\n
+                \\Redistribution and use in source and binary forms, with or without\n
+                \\modification, are permitted provided that the following conditions are met:\n
+                \\\n
+                \\1. Redistributions of source code must retain the above copyright notice, this\n
+                \\   list of conditions and the following disclaimer.\n
+                \\\n
+                \\2. Redistributions in binary form must reproduce the above copyright\n
+                \\   notice, this list of conditions and the following disclaimer in the\n
+                \\   documentation and/or other materials provided with the distribution.\n
+                \\\n
+                \\3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
+                \\   contributors may be used to endorse or promote products derived from this\n
+                \\   software without specific prior written permission.\n
+                \\\n
+                \\THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
+                \\AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
+                \\IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
+                \\ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
+                \\LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
+                \\CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
+                \\SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
+                \\INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
+                \\CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
+                \\ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
+                \\POSSIBILITY OF SUCH DAMAGE.\n
+                \\        
+            ;
+            pub const @"cpu.name" = "CM4";
+            pub const @"cpu.endian" = "little";
+        };
+
+        pub const VectorTable = extern struct {
+            const Handler = micro.interrupt.Handler;
+            const unhandled = micro.interrupt.unhandled;
+
+            initial_stack_pointer: u32,
+            Reset: Handler = unhandled,
+            NMI: Handler = unhandled,
+            HardFault: Handler = unhandled,
+            MemManageFault: Handler = unhandled,
+            BusFault: Handler = unhandled,
+            UsageFault: Handler = unhandled,
+            reserved5: [4]u32 = undefined,
+            SVCall: Handler = unhandled,
+            DebugMonitor: Handler = unhandled,
+            reserved11: [1]u32 = undefined,
+            PendSV: Handler = unhandled,
+            SysTick: Handler = unhandled,
+            POWER_CLOCK: Handler = unhandled,
+            RADIO: Handler = unhandled,
+            UARTE0_UART0: Handler = unhandled,
+            SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: Handler = unhandled,
+            SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: Handler = unhandled,
+            NFCT: Handler = unhandled,
+            GPIOTE: Handler = unhandled,
+            SAADC: Handler = unhandled,
+            TIMER0: Handler = unhandled,
+            TIMER1: Handler = unhandled,
+            TIMER2: Handler = unhandled,
+            RTC0: Handler = unhandled,
+            TEMP: Handler = unhandled,
+            RNG: Handler = unhandled,
+            ECB: Handler = unhandled,
+            CCM_AAR: Handler = unhandled,
+            WDT: Handler = unhandled,
+            RTC1: Handler = unhandled,
+            QDEC: Handler = unhandled,
+            COMP_LPCOMP: Handler = unhandled,
+            SWI0_EGU0: Handler = unhandled,
+            SWI1_EGU1: Handler = unhandled,
+            SWI2_EGU2: Handler = unhandled,
+            SWI3_EGU3: Handler = unhandled,
+            SWI4_EGU4: Handler = unhandled,
+            SWI5_EGU5: Handler = unhandled,
+            TIMER3: Handler = unhandled,
+            TIMER4: Handler = unhandled,
+            PWM0: Handler = unhandled,
+            PDM: Handler = unhandled,
+            reserved44: [2]u32 = undefined,
+            MWU: Handler = unhandled,
+            PWM1: Handler = unhandled,
+            PWM2: Handler = unhandled,
+            SPIM2_SPIS2_SPI2: Handler = unhandled,
+            RTC2: Handler = unhandled,
+            I2S: Handler = unhandled,
+            FPU: Handler = unhandled,
+        };
+
+        pub const peripherals = struct {
+            ///  Factory Information Configuration Registers
+            pub const FICR = @intToPtr(*volatile types.peripherals.FICR, 0x10000000);
+            ///  User Information Configuration Registers
+            pub const UICR = @intToPtr(*volatile types.peripherals.UICR, 0x10001000);
+            ///  Block Protect
+            pub const BPROT = @intToPtr(*volatile types.peripherals.BPROT, 0x40000000);
+            ///  Power control
+            pub const POWER = @intToPtr(*volatile types.peripherals.POWER, 0x40000000);
+            ///  Clock control
+            pub const CLOCK = @intToPtr(*volatile types.peripherals.CLOCK, 0x40000000);
+            ///  2.4 GHz Radio
+            pub const RADIO = @intToPtr(*volatile types.peripherals.RADIO, 0x40001000);
+            ///  UART with EasyDMA
+            pub const UARTE0 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40002000);
+            ///  Universal Asynchronous Receiver/Transmitter
+            pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x40002000);
+            ///  Serial Peripheral Interface Master with EasyDMA 0
+            pub const SPIM0 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40003000);
+            ///  SPI Slave 0
+            pub const SPIS0 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40003000);
+            ///  I2C compatible Two-Wire Master Interface with EasyDMA 0
+            pub const TWIM0 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40003000);
+            ///  I2C compatible Two-Wire Slave Interface with EasyDMA 0
+            pub const TWIS0 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40003000);
+            ///  Serial Peripheral Interface 0
+            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003000);
+            ///  I2C compatible Two-Wire Interface 0
+            pub const TWI0 = @intToPtr(*volatile types.peripherals.TWI0, 0x40003000);
+            ///  Serial Peripheral Interface Master with EasyDMA 1
+            pub const SPIM1 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40004000);
+            ///  SPI Slave 1
+            pub const SPIS1 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40004000);
+            ///  I2C compatible Two-Wire Master Interface with EasyDMA 1
+            pub const TWIM1 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40004000);
+            ///  I2C compatible Two-Wire Slave Interface with EasyDMA 1
+            pub const TWIS1 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40004000);
+            ///  Serial Peripheral Interface 1
+            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40004000);
+            ///  I2C compatible Two-Wire Interface 1
+            pub const TWI1 = @intToPtr(*volatile types.peripherals.TWI0, 0x40004000);
+            ///  NFC-A compatible radio
+            pub const NFCT = @intToPtr(*volatile types.peripherals.NFCT, 0x40005000);
+            ///  GPIO Tasks and Events
+            pub const GPIOTE = @intToPtr(*volatile types.peripherals.GPIOTE, 0x40006000);
+            ///  Analog to Digital Converter
+            pub const SAADC = @intToPtr(*volatile types.peripherals.SAADC, 0x40007000);
+            ///  Timer/Counter 0
+            pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40008000);
+            ///  Timer/Counter 1
+            pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40009000);
+            ///  Timer/Counter 2
+            pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4000a000);
+            ///  Real time counter 0
+            pub const RTC0 = @intToPtr(*volatile types.peripherals.RTC0, 0x4000b000);
+            ///  Temperature Sensor
+            pub const TEMP = @intToPtr(*volatile types.peripherals.TEMP, 0x4000c000);
+            ///  Random Number Generator
+            pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x4000d000);
+            ///  AES ECB Mode Encryption
+            pub const ECB = @intToPtr(*volatile types.peripherals.ECB, 0x4000e000);
+            ///  AES CCM Mode Encryption
+            pub const CCM = @intToPtr(*volatile types.peripherals.CCM, 0x4000f000);
+            ///  Accelerated Address Resolver
+            pub const AAR = @intToPtr(*volatile types.peripherals.AAR, 0x4000f000);
+            ///  Watchdog Timer
+            pub const WDT = @intToPtr(*volatile types.peripherals.WDT, 0x40010000);
+            ///  Real time counter 1
+            pub const RTC1 = @intToPtr(*volatile types.peripherals.RTC0, 0x40011000);
+            ///  Quadrature Decoder
+            pub const QDEC = @intToPtr(*volatile types.peripherals.QDEC, 0x40012000);
+            ///  Comparator
+            pub const COMP = @intToPtr(*volatile types.peripherals.COMP, 0x40013000);
+            ///  Low Power Comparator
+            pub const LPCOMP = @intToPtr(*volatile types.peripherals.LPCOMP, 0x40013000);
+            ///  Software interrupt 0
+            pub const SWI0 = @intToPtr(*volatile types.peripherals.SWI0, 0x40014000);
+            ///  Event Generator Unit 0
+            pub const EGU0 = @intToPtr(*volatile types.peripherals.EGU0, 0x40014000);
+            ///  Software interrupt 1
+            pub const SWI1 = @intToPtr(*volatile types.peripherals.SWI0, 0x40015000);
+            ///  Event Generator Unit 1
+            pub const EGU1 = @intToPtr(*volatile types.peripherals.EGU0, 0x40015000);
+            ///  Software interrupt 2
+            pub const SWI2 = @intToPtr(*volatile types.peripherals.SWI0, 0x40016000);
+            ///  Event Generator Unit 2
+            pub const EGU2 = @intToPtr(*volatile types.peripherals.EGU0, 0x40016000);
+            ///  Software interrupt 3
+            pub const SWI3 = @intToPtr(*volatile types.peripherals.SWI0, 0x40017000);
+            ///  Event Generator Unit 3
+            pub const EGU3 = @intToPtr(*volatile types.peripherals.EGU0, 0x40017000);
+            ///  Software interrupt 4
+            pub const SWI4 = @intToPtr(*volatile types.peripherals.SWI0, 0x40018000);
+            ///  Event Generator Unit 4
+            pub const EGU4 = @intToPtr(*volatile types.peripherals.EGU0, 0x40018000);
+            ///  Software interrupt 5
+            pub const SWI5 = @intToPtr(*volatile types.peripherals.SWI0, 0x40019000);
+            ///  Event Generator Unit 5
+            pub const EGU5 = @intToPtr(*volatile types.peripherals.EGU0, 0x40019000);
+            ///  Timer/Counter 3
+            pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001a000);
+            ///  Timer/Counter 4
+            pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001b000);
+            ///  Pulse Width Modulation Unit 0
+            pub const PWM0 = @intToPtr(*volatile types.peripherals.PWM0, 0x4001c000);
+            ///  Pulse Density Modulation (Digital Microphone) Interface
+            pub const PDM = @intToPtr(*volatile types.peripherals.PDM, 0x4001d000);
+            ///  Non Volatile Memory Controller
+            pub const NVMC = @intToPtr(*volatile types.peripherals.NVMC, 0x4001e000);
+            ///  Programmable Peripheral Interconnect
+            pub const PPI = @intToPtr(*volatile types.peripherals.PPI, 0x4001f000);
+            ///  Memory Watch Unit
+            pub const MWU = @intToPtr(*volatile types.peripherals.MWU, 0x40020000);
+            ///  Pulse Width Modulation Unit 1
+            pub const PWM1 = @intToPtr(*volatile types.peripherals.PWM0, 0x40021000);
+            ///  Pulse Width Modulation Unit 2
+            pub const PWM2 = @intToPtr(*volatile types.peripherals.PWM0, 0x40022000);
+            ///  Serial Peripheral Interface Master with EasyDMA 2
+            pub const SPIM2 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40023000);
+            ///  SPI Slave 2
+            pub const SPIS2 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40023000);
+            ///  Serial Peripheral Interface 2
+            pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40023000);
+            ///  Real time counter 2
+            pub const RTC2 = @intToPtr(*volatile types.peripherals.RTC0, 0x40024000);
+            ///  Inter-IC Sound
+            pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x40025000);
+            ///  FPU
+            pub const FPU = @intToPtr(*volatile types.peripherals.FPU, 0x40026000);
+            ///  GPIO Port 1
+            pub const P0 = @intToPtr(*volatile types.peripherals.P0, 0x50000000);
+            ///  System Tick Timer
+            pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010);
+        };
+    };
+};
+
+pub const types = struct {
+    pub const peripherals = struct {
+        ///  System Control Space
+        pub const SCS = struct {
+            ///  System Tick Timer
+            pub const SysTick = extern struct {
+                ///  SysTick Control and Status Register
+                CTRL: mmio.Mmio(packed struct(u32) {
+                    ENABLE: u1,
+                    TICKINT: u1,
+                    CLKSOURCE: u1,
+                    reserved16: u13,
+                    COUNTFLAG: u1,
+                    padding: u15,
+                }),
+                ///  SysTick Reload Value Register
+                LOAD: mmio.Mmio(packed struct(u32) {
+                    RELOAD: u24,
+                    padding: u8,
+                }),
+                ///  SysTick Current Value Register
+                VAL: mmio.Mmio(packed struct(u32) {
+                    CURRENT: u24,
+                    padding: u8,
+                }),
+                ///  SysTick Calibration Register
+                CALIB: mmio.Mmio(packed struct(u32) {
+                    TENMS: u24,
+                    reserved30: u6,
+                    SKEW: u1,
+                    NOREF: u1,
+                }),
+            };
+        };
+
+        ///  Factory Information Configuration Registers
+        pub const FICR = extern struct {
+            reserved16: [16]u8,
+            ///  Code memory page size
+            CODEPAGESIZE: mmio.Mmio(packed struct(u32) {
+                ///  Code memory page size
+                CODEPAGESIZE: u32,
+            }),
+            ///  Code memory size
+            CODESIZE: mmio.Mmio(packed struct(u32) {
+                ///  Code memory size in number of pages
+                CODESIZE: u32,
+            }),
+            reserved96: [72]u8,
+            ///  Description collection[0]: Device identifier
+            DEVICEID: [2]mmio.Mmio(packed struct(u32) {
+                ///  64 bit unique device identifier
+                DEVICEID: u32,
+            }),
+            reserved128: [24]u8,
+            ///  Description collection[0]: Encryption Root, word 0
+            ER: [4]mmio.Mmio(packed struct(u32) {
+                ///  Encryption Root, word n
+                ER: u32,
+            }),
+            ///  Description collection[0]: Identity Root, word 0
+            IR: [4]mmio.Mmio(packed struct(u32) {
+                ///  Identity Root, word n
+                IR: u32,
+            }),
+            ///  Device address type
+            DEVICEADDRTYPE: mmio.Mmio(packed struct(u32) {
+                ///  Device address type
+                DEVICEADDRTYPE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Public address
+                        Public = 0x0,
+                        ///  Random address
+                        Random = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Description collection[0]: Device address 0
+            DEVICEADDR: [2]mmio.Mmio(packed struct(u32) {
+                ///  48 bit device address
+                DEVICEADDR: u32,
+            }),
+        };
+
+        ///  User Information Configuration Registers
+        pub const UICR = extern struct {
+            ///  Unspecified
+            UNUSED0: u32,
+            ///  Unspecified
+            UNUSED1: u32,
+            ///  Unspecified
+            UNUSED2: u32,
+            reserved16: [4]u8,
+            ///  Unspecified
+            UNUSED3: u32,
+            ///  Description collection[0]: Reserved for Nordic firmware design
+            NRFFW: [15]mmio.Mmio(packed struct(u32) {
+                ///  Reserved for Nordic firmware design
+                NRFFW: u32,
+            }),
+            ///  Description collection[0]: Reserved for Nordic hardware design
+            NRFHW: [12]mmio.Mmio(packed struct(u32) {
+                ///  Reserved for Nordic hardware design
+                NRFHW: u32,
+            }),
+            ///  Description collection[0]: Reserved for customer
+            CUSTOMER: [32]mmio.Mmio(packed struct(u32) {
+                ///  Reserved for customer
+                CUSTOMER: u32,
+            }),
+            reserved512: [256]u8,
+            ///  Description collection[0]: Mapping of the nRESET function (see POWER chapter for details)
+            PSELRESET: [2]mmio.Mmio(packed struct(u32) {
+                ///  GPIO number P0.n onto which Reset is exposed
+                PIN: u6,
+                reserved31: u25,
+                ///  Connection
+                CONNECT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disconnect
+                        Disconnected = 0x1,
+                        ///  Connect
+                        Connected = 0x0,
+                    },
+                },
+            }),
+            ///  Access Port protection
+            APPROTECT: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection.
+                PALL: packed union {
+                    raw: u8,
+                    value: enum(u8) {
+                        ///  Disable
+                        Disabled = 0xff,
+                        ///  Enable
+                        Enabled = 0x0,
+                        _,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
+            NFCPINS: mmio.Mmio(packed struct(u32) {
+                ///  Setting of pins dedicated to NFC functionality
+                PROTECT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Operation as GPIO pins. Same protection as normal GPIO pins
+                        Disabled = 0x0,
+                        ///  Operation as NFC antenna pins. Configures the protection for NFC operation
+                        NFC = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  Block Protect
+        pub const BPROT = extern struct {
+            reserved1536: [1536]u8,
+            ///  Block protect configuration register 0
+            CONFIG0: mmio.Mmio(packed struct(u32) {
+                ///  Enable protection for region 0. Write '0' has no effect.
+                REGION0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 1. Write '0' has no effect.
+                REGION1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 2. Write '0' has no effect.
+                REGION2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 3. Write '0' has no effect.
+                REGION3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 4. Write '0' has no effect.
+                REGION4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 5. Write '0' has no effect.
+                REGION5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 6. Write '0' has no effect.
+                REGION6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 7. Write '0' has no effect.
+                REGION7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 8. Write '0' has no effect.
+                REGION8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 9. Write '0' has no effect.
+                REGION9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 10. Write '0' has no effect.
+                REGION10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 11. Write '0' has no effect.
+                REGION11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 12. Write '0' has no effect.
+                REGION12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 13. Write '0' has no effect.
+                REGION13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 14. Write '0' has no effect.
+                REGION14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 15. Write '0' has no effect.
+                REGION15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 16. Write '0' has no effect.
+                REGION16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 17. Write '0' has no effect.
+                REGION17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 18. Write '0' has no effect.
+                REGION18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 19. Write '0' has no effect.
+                REGION19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 20. Write '0' has no effect.
+                REGION20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 21. Write '0' has no effect.
+                REGION21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 22. Write '0' has no effect.
+                REGION22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 23. Write '0' has no effect.
+                REGION23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 24. Write '0' has no effect.
+                REGION24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 25. Write '0' has no effect.
+                REGION25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 26. Write '0' has no effect.
+                REGION26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 27. Write '0' has no effect.
+                REGION27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 28. Write '0' has no effect.
+                REGION28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 29. Write '0' has no effect.
+                REGION29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 30. Write '0' has no effect.
+                REGION30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 31. Write '0' has no effect.
+                REGION31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enable
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            ///  Block protect configuration register 1
+            CONFIG1: mmio.Mmio(packed struct(u32) {
+                ///  Enable protection for region 32. Write '0' has no effect.
+                REGION32: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 33. Write '0' has no effect.
+                REGION33: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 34. Write '0' has no effect.
+                REGION34: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 35. Write '0' has no effect.
+                REGION35: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 36. Write '0' has no effect.
+                REGION36: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 37. Write '0' has no effect.
+                REGION37: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 38. Write '0' has no effect.
+                REGION38: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 39. Write '0' has no effect.
+                REGION39: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 40. Write '0' has no effect.
+                REGION40: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 41. Write '0' has no effect.
+                REGION41: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 42. Write '0' has no effect.
+                REGION42: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 43. Write '0' has no effect.
+                REGION43: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 44. Write '0' has no effect.
+                REGION44: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 45. Write '0' has no effect.
+                REGION45: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 46. Write '0' has no effect.
+                REGION46: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 47. Write '0' has no effect.
+                REGION47: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 48. Write '0' has no effect.
+                REGION48: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 49. Write '0' has no effect.
+                REGION49: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 50. Write '0' has no effect.
+                REGION50: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 51. Write '0' has no effect.
+                REGION51: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 52. Write '0' has no effect.
+                REGION52: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 53. Write '0' has no effect.
+                REGION53: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 54. Write '0' has no effect.
+                REGION54: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 55. Write '0' has no effect.
+                REGION55: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 56. Write '0' has no effect.
+                REGION56: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 57. Write '0' has no effect.
+                REGION57: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 58. Write '0' has no effect.
+                REGION58: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 59. Write '0' has no effect.
+                REGION59: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 60. Write '0' has no effect.
+                REGION60: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 61. Write '0' has no effect.
+                REGION61: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 62. Write '0' has no effect.
+                REGION62: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 63. Write '0' has no effect.
+                REGION63: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            ///  Disable protection mechanism in debug interface mode
+            DISABLEINDEBUG: mmio.Mmio(packed struct(u32) {
+                ///  Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode.
+                DISABLEINDEBUG: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable in debug
+                        Disabled = 0x1,
+                        ///  Enable in debug
+                        Enabled = 0x0,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Unspecified
+            UNUSED0: u32,
+            ///  Block protect configuration register 2
+            CONFIG2: mmio.Mmio(packed struct(u32) {
+                ///  Enable protection for region 64. Write '0' has no effect.
+                REGION64: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 65. Write '0' has no effect.
+                REGION65: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 66. Write '0' has no effect.
+                REGION66: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 67. Write '0' has no effect.
+                REGION67: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 68. Write '0' has no effect.
+                REGION68: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 69. Write '0' has no effect.
+                REGION69: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 70. Write '0' has no effect.
+                REGION70: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 71. Write '0' has no effect.
+                REGION71: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 72. Write '0' has no effect.
+                REGION72: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 73. Write '0' has no effect.
+                REGION73: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 74. Write '0' has no effect.
+                REGION74: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 75. Write '0' has no effect.
+                REGION75: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 76. Write '0' has no effect.
+                REGION76: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 77. Write '0' has no effect.
+                REGION77: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 78. Write '0' has no effect.
+                REGION78: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 79. Write '0' has no effect.
+                REGION79: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 80. Write '0' has no effect.
+                REGION80: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 81. Write '0' has no effect.
+                REGION81: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 82. Write '0' has no effect.
+                REGION82: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 83. Write '0' has no effect.
+                REGION83: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 84. Write '0' has no effect.
+                REGION84: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 85. Write '0' has no effect.
+                REGION85: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 86. Write '0' has no effect.
+                REGION86: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 87. Write '0' has no effect.
+                REGION87: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 88. Write '0' has no effect.
+                REGION88: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 89. Write '0' has no effect.
+                REGION89: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 90. Write '0' has no effect.
+                REGION90: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 91. Write '0' has no effect.
+                REGION91: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 92. Write '0' has no effect.
+                REGION92: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 93. Write '0' has no effect.
+                REGION93: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 94. Write '0' has no effect.
+                REGION94: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 95. Write '0' has no effect.
+                REGION95: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            ///  Block protect configuration register 3
+            CONFIG3: mmio.Mmio(packed struct(u32) {
+                ///  Enable protection for region 96. Write '0' has no effect.
+                REGION96: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 97. Write '0' has no effect.
+                REGION97: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 98. Write '0' has no effect.
+                REGION98: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 99. Write '0' has no effect.
+                REGION99: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 100. Write '0' has no effect.
+                REGION100: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 101. Write '0' has no effect.
+                REGION101: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 102. Write '0' has no effect.
+                REGION102: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 103. Write '0' has no effect.
+                REGION103: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 104. Write '0' has no effect.
+                REGION104: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 105. Write '0' has no effect.
+                REGION105: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 106. Write '0' has no effect.
+                REGION106: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 107. Write '0' has no effect.
+                REGION107: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 108. Write '0' has no effect.
+                REGION108: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 109. Write '0' has no effect.
+                REGION109: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 110. Write '0' has no effect.
+                REGION110: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 111. Write '0' has no effect.
+                REGION111: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 112. Write '0' has no effect.
+                REGION112: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 113. Write '0' has no effect.
+                REGION113: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 114. Write '0' has no effect.
+                REGION114: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 115. Write '0' has no effect.
+                REGION115: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 116. Write '0' has no effect.
+                REGION116: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 117. Write '0' has no effect.
+                REGION117: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 118. Write '0' has no effect.
+                REGION118: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 119. Write '0' has no effect.
+                REGION119: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 120. Write '0' has no effect.
+                REGION120: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 121. Write '0' has no effect.
+                REGION121: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 122. Write '0' has no effect.
+                REGION122: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 123. Write '0' has no effect.
+                REGION123: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 124. Write '0' has no effect.
+                REGION124: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 125. Write '0' has no effect.
+                REGION125: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 126. Write '0' has no effect.
+                REGION126: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable protection for region 127. Write '0' has no effect.
+                REGION127: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Protection disabled
+                        Disabled = 0x0,
+                        ///  Protection enabled
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+        };
+
+        ///  Power control
+        pub const POWER = extern struct {
+            reserved120: [120]u8,
+            ///  Enable constant latency mode
+            TASKS_CONSTLAT: u32,
+            ///  Enable low power mode (variable latency)
+            TASKS_LOWPWR: u32,
+            reserved264: [136]u8,
+            ///  Power failure warning
+            EVENTS_POFWARN: u32,
+            reserved276: [8]u8,
+            ///  CPU entered WFI/WFE sleep
+            EVENTS_SLEEPENTER: u32,
+            ///  CPU exited WFI/WFE sleep
+            EVENTS_SLEEPEXIT: u32,
+            reserved772: [488]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Write '1' to Enable interrupt for POFWARN event
+                POFWARN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved5: u2,
+                ///  Write '1' to Enable interrupt for SLEEPENTER event
+                SLEEPENTER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for SLEEPEXIT event
+                SLEEPEXIT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u25,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Write '1' to Disable interrupt for POFWARN event
+                POFWARN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved5: u2,
+                ///  Write '1' to Disable interrupt for SLEEPENTER event
+                SLEEPENTER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for SLEEPEXIT event
+                SLEEPEXIT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u25,
+            }),
+            reserved1024: [244]u8,
+            ///  Reset reason
+            RESETREAS: mmio.Mmio(packed struct(u32) {
+                ///  Reset from pin-reset detected
+                RESETPIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset from watchdog detected
+                DOG: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset from soft reset detected
+                SREQ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset from CPU lock-up detected
+                LOCKUP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                reserved16: u12,
+                ///  Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO
+                OFF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP
+                LPCOMP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode
+                DIF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset due to wake up from System OFF mode by NFC field detect
+                NFC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            reserved1064: [36]u8,
+            ///  Deprecated register - RAM status register
+            RAMSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  RAM block 0 is on or off/powering up
+                RAMBLOCK0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        Off = 0x0,
+                        ///  On
+                        On = 0x1,
+                    },
+                },
+                ///  RAM block 1 is on or off/powering up
+                RAMBLOCK1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        Off = 0x0,
+                        ///  On
+                        On = 0x1,
+                    },
+                },
+                ///  RAM block 2 is on or off/powering up
+                RAMBLOCK2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        Off = 0x0,
+                        ///  On
+                        On = 0x1,
+                    },
+                },
+                ///  RAM block 3 is on or off/powering up
+                RAMBLOCK3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        Off = 0x0,
+                        ///  On
+                        On = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1280: [212]u8,
+            ///  System OFF register
+            SYSTEMOFF: mmio.Mmio(packed struct(u32) {
+                ///  Enable System OFF mode
+                SYSTEMOFF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Enable System OFF mode
+                        Enter = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1296: [12]u8,
+            ///  Power failure comparator configuration
+            POFCON: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable power failure comparator
+                POF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Power failure comparator threshold setting
+                THRESHOLD: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Set threshold to 1.7 V
+                        V17 = 0x4,
+                        ///  Set threshold to 1.8 V
+                        V18 = 0x5,
+                        ///  Set threshold to 1.9 V
+                        V19 = 0x6,
+                        ///  Set threshold to 2.0 V
+                        V20 = 0x7,
+                        ///  Set threshold to 2.1 V
+                        V21 = 0x8,
+                        ///  Set threshold to 2.2 V
+                        V22 = 0x9,
+                        ///  Set threshold to 2.3 V
+                        V23 = 0xa,
+                        ///  Set threshold to 2.4 V
+                        V24 = 0xb,
+                        ///  Set threshold to 2.5 V
+                        V25 = 0xc,
+                        ///  Set threshold to 2.6 V
+                        V26 = 0xd,
+                        ///  Set threshold to 2.7 V
+                        V27 = 0xe,
+                        ///  Set threshold to 2.8 V
+                        V28 = 0xf,
+                        _,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved1308: [8]u8,
+            ///  General purpose retention register
+            GPREGRET: mmio.Mmio(packed struct(u32) {
+                ///  General purpose retention register
+                GPREGRET: u8,
+                padding: u24,
+            }),
+            ///  General purpose retention register
+            GPREGRET2: mmio.Mmio(packed struct(u32) {
+                ///  General purpose retention register
+                GPREGRET: u8,
+                padding: u24,
+            }),
+            ///  Deprecated register - RAM on/off register (this register is retained)
+            RAMON: mmio.Mmio(packed struct(u32) {
+                ///  Keep RAM block 0 on or off in system ON Mode
+                ONRAM0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        RAM0Off = 0x0,
+                        ///  On
+                        RAM0On = 0x1,
+                    },
+                },
+                ///  Keep RAM block 1 on or off in system ON Mode
+                ONRAM1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        RAM1Off = 0x0,
+                        ///  On
+                        RAM1On = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Keep retention on RAM block 0 when RAM block is switched off
+                OFFRAM0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        RAM0Off = 0x0,
+                        ///  On
+                        RAM0On = 0x1,
+                    },
+                },
+                ///  Keep retention on RAM block 1 when RAM block is switched off
+                OFFRAM1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        RAM1Off = 0x0,
+                        ///  On
+                        RAM1On = 0x1,
+                    },
+                },
+                padding: u14,
+            }),
+            reserved1364: [44]u8,
+            ///  Deprecated register - RAM on/off register (this register is retained)
+            RAMONB: mmio.Mmio(packed struct(u32) {
+                ///  Keep RAM block 2 on or off in system ON Mode
+                ONRAM2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        RAM2Off = 0x0,
+                        ///  On
+                        RAM2On = 0x1,
+                    },
+                },
+                ///  Keep RAM block 3 on or off in system ON Mode
+                ONRAM3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        RAM3Off = 0x0,
+                        ///  On
+                        RAM3On = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Keep retention on RAM block 2 when RAM block is switched off
+                OFFRAM2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        RAM2Off = 0x0,
+                        ///  On
+                        RAM2On = 0x1,
+                    },
+                },
+                ///  Keep retention on RAM block 3 when RAM block is switched off
+                OFFRAM3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        RAM3Off = 0x0,
+                        ///  On
+                        RAM3On = 0x1,
+                    },
+                },
+                padding: u14,
+            }),
+            reserved1400: [32]u8,
+            ///  DC/DC enable register
+            DCDCEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable DC/DC converter
+                DCDCEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  Clock control
+        pub const CLOCK = extern struct {
+            ///  Start HFCLK crystal oscillator
+            TASKS_HFCLKSTART: u32,
+            ///  Stop HFCLK crystal oscillator
+            TASKS_HFCLKSTOP: u32,
+            ///  Start LFCLK source
+            TASKS_LFCLKSTART: u32,
+            ///  Stop LFCLK source
+            TASKS_LFCLKSTOP: u32,
+            ///  Start calibration of LFRC oscillator
+            TASKS_CAL: u32,
+            ///  Start calibration timer
+            TASKS_CTSTART: u32,
+            ///  Stop calibration timer
+            TASKS_CTSTOP: u32,
+            reserved256: [228]u8,
+            ///  HFCLK oscillator started
+            EVENTS_HFCLKSTARTED: u32,
+            ///  LFCLK started
+            EVENTS_LFCLKSTARTED: u32,
+            reserved268: [4]u8,
+            ///  Calibration of LFCLK RC oscillator complete event
+            EVENTS_DONE: u32,
+            ///  Calibration timer timeout
+            EVENTS_CTTO: u32,
+            reserved772: [496]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for HFCLKSTARTED event
+                HFCLKSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for LFCLKSTARTED event
+                LFCLKSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved3: u1,
+                ///  Write '1' to Enable interrupt for DONE event
+                DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CTTO event
+                CTTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for HFCLKSTARTED event
+                HFCLKSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for LFCLKSTARTED event
+                LFCLKSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved3: u1,
+                ///  Write '1' to Disable interrupt for DONE event
+                DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CTTO event
+                CTTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved1032: [252]u8,
+            ///  Status indicating that HFCLKSTART task has been triggered
+            HFCLKRUN: mmio.Mmio(packed struct(u32) {
+                ///  HFCLKSTART task triggered or not
+                STATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Task not triggered
+                        NotTriggered = 0x0,
+                        ///  Task triggered
+                        Triggered = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  HFCLK status
+            HFCLKSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Source of HFCLK
+                SRC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  64 MHz internal oscillator (HFINT)
+                        RC = 0x0,
+                        ///  64 MHz crystal oscillator (HFXO)
+                        Xtal = 0x1,
+                    },
+                },
+                reserved16: u15,
+                ///  HFCLK state
+                STATE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  HFCLK not running
+                        NotRunning = 0x0,
+                        ///  HFCLK running
+                        Running = 0x1,
+                    },
+                },
+                padding: u15,
+            }),
+            reserved1044: [4]u8,
+            ///  Status indicating that LFCLKSTART task has been triggered
+            LFCLKRUN: mmio.Mmio(packed struct(u32) {
+                ///  LFCLKSTART task triggered or not
+                STATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Task not triggered
+                        NotTriggered = 0x0,
+                        ///  Task triggered
+                        Triggered = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  LFCLK status
+            LFCLKSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Source of LFCLK
+                SRC: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  32.768 kHz RC oscillator
+                        RC = 0x0,
+                        ///  32.768 kHz crystal oscillator
+                        Xtal = 0x1,
+                        ///  32.768 kHz synthesized from HFCLK
+                        Synth = 0x2,
+                        _,
+                    },
+                },
+                reserved16: u14,
+                ///  LFCLK state
+                STATE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  LFCLK not running
+                        NotRunning = 0x0,
+                        ///  LFCLK running
+                        Running = 0x1,
+                    },
+                },
+                padding: u15,
+            }),
+            ///  Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
+            LFCLKSRCCOPY: mmio.Mmio(packed struct(u32) {
+                ///  Clock source
+                SRC: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  32.768 kHz RC oscillator
+                        RC = 0x0,
+                        ///  32.768 kHz crystal oscillator
+                        Xtal = 0x1,
+                        ///  32.768 kHz synthesized from HFCLK
+                        Synth = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1304: [248]u8,
+            ///  Clock source for the LFCLK
+            LFCLKSRC: mmio.Mmio(packed struct(u32) {
+                ///  Clock source
+                SRC: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  32.768 kHz RC oscillator
+                        RC = 0x0,
+                        ///  32.768 kHz crystal oscillator
+                        Xtal = 0x1,
+                        ///  32.768 kHz synthesized from HFCLK
+                        Synth = 0x2,
+                        _,
+                    },
+                },
+                reserved16: u14,
+                ///  Enable or disable bypass of LFCLK crystal oscillator with external clock source
+                BYPASS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable (use with Xtal or low-swing external source)
+                        Disabled = 0x0,
+                        ///  Enable (use with rail-to-rail external source)
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable external source for LFCLK
+                EXTERNAL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable external source (use with Xtal)
+                        Disabled = 0x0,
+                        ///  Enable use of external source instead of Xtal (SRC needs to be set to Xtal)
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u14,
+            }),
+            reserved1336: [28]u8,
+            ///  Calibration timer interval
+            CTIV: mmio.Mmio(packed struct(u32) {
+                ///  Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.
+                CTIV: u7,
+                padding: u25,
+            }),
+            reserved1372: [32]u8,
+            ///  Clocking options for the Trace Port debug interface
+            TRACECONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two.
+                TRACEPORTSPEED: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  32 MHz Trace Port clock (TRACECLK = 16 MHz)
+                        @"32MHz" = 0x0,
+                        ///  16 MHz Trace Port clock (TRACECLK = 8 MHz)
+                        @"16MHz" = 0x1,
+                        ///  8 MHz Trace Port clock (TRACECLK = 4 MHz)
+                        @"8MHz" = 0x2,
+                        ///  4 MHz Trace Port clock (TRACECLK = 2 MHz)
+                        @"4MHz" = 0x3,
+                    },
+                },
+                reserved16: u14,
+                ///  Pin multiplexing of trace signals.
+                TRACEMUX: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  GPIOs multiplexed onto all trace-pins
+                        GPIO = 0x0,
+                        ///  SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins
+                        Serial = 0x1,
+                        ///  TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14.
+                        Parallel = 0x2,
+                        _,
+                    },
+                },
+                padding: u14,
+            }),
+        };
+
+        ///  2.4 GHz Radio
+        pub const RADIO = extern struct {
+            ///  Enable RADIO in TX mode
+            TASKS_TXEN: u32,
+            ///  Enable RADIO in RX mode
+            TASKS_RXEN: u32,
+            ///  Start RADIO
+            TASKS_START: u32,
+            ///  Stop RADIO
+            TASKS_STOP: u32,
+            ///  Disable RADIO
+            TASKS_DISABLE: u32,
+            ///  Start the RSSI and take one single sample of the receive signal strength.
+            TASKS_RSSISTART: u32,
+            ///  Stop the RSSI measurement
+            TASKS_RSSISTOP: u32,
+            ///  Start the bit counter
+            TASKS_BCSTART: u32,
+            ///  Stop the bit counter
+            TASKS_BCSTOP: u32,
+            reserved256: [220]u8,
+            ///  RADIO has ramped up and is ready to be started
+            EVENTS_READY: u32,
+            ///  Address sent or received
+            EVENTS_ADDRESS: u32,
+            ///  Packet payload sent or received
+            EVENTS_PAYLOAD: u32,
+            ///  Packet sent or received
+            EVENTS_END: u32,
+            ///  RADIO has been disabled
+            EVENTS_DISABLED: u32,
+            ///  A device address match occurred on the last received packet
+            EVENTS_DEVMATCH: u32,
+            ///  No device address match occurred on the last received packet
+            EVENTS_DEVMISS: u32,
+            ///  Sampling of receive signal strength complete.
+            EVENTS_RSSIEND: u32,
+            reserved296: [8]u8,
+            ///  Bit counter reached bit count value.
+            EVENTS_BCMATCH: u32,
+            reserved304: [4]u8,
+            ///  Packet received with CRC ok
+            EVENTS_CRCOK: u32,
+            ///  Packet received with CRC error
+            EVENTS_CRCERROR: u32,
+            reserved512: [200]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between READY event and START task
+                READY_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between END event and DISABLE task
+                END_DISABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between DISABLED event and TXEN task
+                DISABLED_TXEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between DISABLED event and RXEN task
+                DISABLED_RXEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between ADDRESS event and RSSISTART task
+                ADDRESS_RSSISTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between END event and START task
+                END_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between ADDRESS event and BCSTART task
+                ADDRESS_BCSTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                reserved8: u1,
+                ///  Shortcut between DISABLED event and RSSISTOP task
+                DISABLED_RSSISTOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for ADDRESS event
+                ADDRESS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for PAYLOAD event
+                PAYLOAD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for DISABLED event
+                DISABLED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for DEVMATCH event
+                DEVMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for DEVMISS event
+                DEVMISS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for RSSIEND event
+                RSSIEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u2,
+                ///  Write '1' to Enable interrupt for BCMATCH event
+                BCMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved12: u1,
+                ///  Write '1' to Enable interrupt for CRCOK event
+                CRCOK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CRCERROR event
+                CRCERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u18,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for ADDRESS event
+                ADDRESS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for PAYLOAD event
+                PAYLOAD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for DISABLED event
+                DISABLED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for DEVMATCH event
+                DEVMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for DEVMISS event
+                DEVMISS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for RSSIEND event
+                RSSIEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u2,
+                ///  Write '1' to Disable interrupt for BCMATCH event
+                BCMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved12: u1,
+                ///  Write '1' to Disable interrupt for CRCOK event
+                CRCOK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CRCERROR event
+                CRCERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u18,
+            }),
+            reserved1024: [244]u8,
+            ///  CRC status
+            CRCSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  CRC status of packet received
+                CRCSTATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Packet received with CRC error
+                        CRCError = 0x0,
+                        ///  Packet received with CRC ok
+                        CRCOk = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1032: [4]u8,
+            ///  Received address
+            RXMATCH: mmio.Mmio(packed struct(u32) {
+                ///  Received address
+                RXMATCH: u3,
+                padding: u29,
+            }),
+            ///  CRC field of previously received packet
+            RXCRC: mmio.Mmio(packed struct(u32) {
+                ///  CRC field of previously received packet
+                RXCRC: u24,
+                padding: u8,
+            }),
+            ///  Device address match index
+            DAI: mmio.Mmio(packed struct(u32) {
+                ///  Device address match index
+                DAI: u3,
+                padding: u29,
+            }),
+            reserved1284: [240]u8,
+            ///  Packet pointer
+            PACKETPTR: mmio.Mmio(packed struct(u32) {
+                ///  Packet pointer
+                PACKETPTR: u32,
+            }),
+            ///  Frequency
+            FREQUENCY: mmio.Mmio(packed struct(u32) {
+                ///  Radio channel frequency
+                FREQUENCY: u7,
+                reserved8: u1,
+                ///  Channel map selection.
+                MAP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Channel map between 2400 MHZ .. 2500 MHz
+                        Default = 0x0,
+                        ///  Channel map between 2360 MHZ .. 2460 MHz
+                        Low = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            ///  Output power
+            TXPOWER: mmio.Mmio(packed struct(u32) {
+                ///  RADIO output power.
+                TXPOWER: packed union {
+                    raw: u8,
+                    value: enum(u8) {
+                        ///  +4 dBm
+                        Pos4dBm = 0x4,
+                        ///  +3 dBm
+                        Pos3dBm = 0x3,
+                        ///  0 dBm
+                        @"0dBm" = 0x0,
+                        ///  -4 dBm
+                        Neg4dBm = 0xfc,
+                        ///  -8 dBm
+                        Neg8dBm = 0xf8,
+                        ///  -12 dBm
+                        Neg12dBm = 0xf4,
+                        ///  -16 dBm
+                        Neg16dBm = 0xf0,
+                        ///  -20 dBm
+                        Neg20dBm = 0xec,
+                        ///  Deprecated enumerator - -40 dBm
+                        Neg30dBm = 0xff,
+                        ///  -40 dBm
+                        Neg40dBm = 0xd8,
+                        _,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Data rate and modulation
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation.
+                MODE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  1 Mbit/s Nordic proprietary radio mode
+                        Nrf_1Mbit = 0x0,
+                        ///  2 Mbit/s Nordic proprietary radio mode
+                        Nrf_2Mbit = 0x1,
+                        ///  Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode
+                        Nrf_250Kbit = 0x2,
+                        ///  1 Mbit/s Bluetooth Low Energy
+                        Ble_1Mbit = 0x3,
+                        ///  2 Mbit/s Bluetooth Low Energy
+                        Ble_2Mbit = 0x4,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Packet configuration register 0
+            PCNF0: mmio.Mmio(packed struct(u32) {
+                ///  Length on air of LENGTH field in number of bits.
+                LFLEN: u4,
+                reserved8: u4,
+                ///  Length on air of S0 field in number of bytes.
+                S0LEN: u1,
+                reserved16: u7,
+                ///  Length on air of S1 field in number of bits.
+                S1LEN: u4,
+                ///  Include or exclude S1 field in RAM
+                S1INCL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Include S1 field in RAM only if S1LEN > 0
+                        Automatic = 0x0,
+                        ///  Always include S1 field in RAM independent of S1LEN
+                        Include = 0x1,
+                    },
+                },
+                reserved24: u3,
+                ///  Length of preamble on air. Decision point: TASKS_START task
+                PLEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  8-bit preamble
+                        @"8bit" = 0x0,
+                        ///  16-bit preamble
+                        @"16bit" = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            ///  Packet configuration register 1
+            PCNF1: mmio.Mmio(packed struct(u32) {
+                ///  Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.
+                MAXLEN: u8,
+                ///  Static length in number of bytes
+                STATLEN: u8,
+                ///  Base address length in number of bytes
+                BALEN: u3,
+                reserved24: u5,
+                ///  On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.
+                ENDIAN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Least Significant bit on air first
+                        Little = 0x0,
+                        ///  Most significant bit on air first
+                        Big = 0x1,
+                    },
+                },
+                ///  Enable or disable packet whitening
+                WHITEEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u6,
+            }),
+            ///  Base address 0
+            BASE0: mmio.Mmio(packed struct(u32) {
+                ///  Base address 0
+                BASE0: u32,
+            }),
+            ///  Base address 1
+            BASE1: mmio.Mmio(packed struct(u32) {
+                ///  Base address 1
+                BASE1: u32,
+            }),
+            ///  Prefixes bytes for logical addresses 0-3
+            PREFIX0: mmio.Mmio(packed struct(u32) {
+                ///  Address prefix 0.
+                AP0: u8,
+                ///  Address prefix 1.
+                AP1: u8,
+                ///  Address prefix 2.
+                AP2: u8,
+                ///  Address prefix 3.
+                AP3: u8,
+            }),
+            ///  Prefixes bytes for logical addresses 4-7
+            PREFIX1: mmio.Mmio(packed struct(u32) {
+                ///  Address prefix 4.
+                AP4: u8,
+                ///  Address prefix 5.
+                AP5: u8,
+                ///  Address prefix 6.
+                AP6: u8,
+                ///  Address prefix 7.
+                AP7: u8,
+            }),
+            ///  Transmit address select
+            TXADDRESS: mmio.Mmio(packed struct(u32) {
+                ///  Transmit address select
+                TXADDRESS: u3,
+                padding: u29,
+            }),
+            ///  Receive address select
+            RXADDRESSES: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable reception on logical address 0.
+                ADDR0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 1.
+                ADDR1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 2.
+                ADDR2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 3.
+                ADDR3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 4.
+                ADDR4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 5.
+                ADDR5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 6.
+                ADDR6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 7.
+                ADDR7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  CRC configuration
+            CRCCNF: mmio.Mmio(packed struct(u32) {
+                ///  CRC length in number of bytes.
+                LEN: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  CRC length is zero and CRC calculation is disabled
+                        Disabled = 0x0,
+                        ///  CRC length is one byte and CRC calculation is enabled
+                        One = 0x1,
+                        ///  CRC length is two bytes and CRC calculation is enabled
+                        Two = 0x2,
+                        ///  CRC length is three bytes and CRC calculation is enabled
+                        Three = 0x3,
+                    },
+                },
+                reserved8: u6,
+                ///  Include or exclude packet address field out of CRC calculation.
+                SKIPADDR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  CRC calculation includes address field
+                        Include = 0x0,
+                        ///  CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.
+                        Skip = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            ///  CRC polynomial
+            CRCPOLY: mmio.Mmio(packed struct(u32) {
+                ///  CRC polynomial
+                CRCPOLY: u24,
+                padding: u8,
+            }),
+            ///  CRC initial value
+            CRCINIT: mmio.Mmio(packed struct(u32) {
+                ///  CRC initial value
+                CRCINIT: u24,
+                padding: u8,
+            }),
+            ///  Unspecified
+            UNUSED0: u32,
+            ///  Inter Frame Spacing in us
+            TIFS: mmio.Mmio(packed struct(u32) {
+                ///  Inter Frame Spacing in us
+                TIFS: u8,
+                padding: u24,
+            }),
+            ///  RSSI sample
+            RSSISAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  RSSI sample
+                RSSISAMPLE: u7,
+                padding: u25,
+            }),
+            reserved1360: [4]u8,
+            ///  Current radio state
+            STATE: mmio.Mmio(packed struct(u32) {
+                ///  Current radio state
+                STATE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  RADIO is in the Disabled state
+                        Disabled = 0x0,
+                        ///  RADIO is in the RXRU state
+                        RxRu = 0x1,
+                        ///  RADIO is in the RXIDLE state
+                        RxIdle = 0x2,
+                        ///  RADIO is in the RX state
+                        Rx = 0x3,
+                        ///  RADIO is in the RXDISABLED state
+                        RxDisable = 0x4,
+                        ///  RADIO is in the TXRU state
+                        TxRu = 0x9,
+                        ///  RADIO is in the TXIDLE state
+                        TxIdle = 0xa,
+                        ///  RADIO is in the TX state
+                        Tx = 0xb,
+                        ///  RADIO is in the TXDISABLED state
+                        TxDisable = 0xc,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Data whitening initial value
+            DATAWHITEIV: mmio.Mmio(packed struct(u32) {
+                ///  Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.
+                DATAWHITEIV: u7,
+                padding: u25,
+            }),
+            reserved1376: [8]u8,
+            ///  Bit counter compare
+            BCC: mmio.Mmio(packed struct(u32) {
+                ///  Bit counter compare
+                BCC: u32,
+            }),
+            reserved1536: [156]u8,
+            ///  Description collection[0]: Device address base segment 0
+            DAB: [8]mmio.Mmio(packed struct(u32) {
+                ///  Device address base segment 0
+                DAB: u32,
+            }),
+            ///  Description collection[0]: Device address prefix 0
+            DAP: [8]mmio.Mmio(packed struct(u32) {
+                ///  Device address prefix 0
+                DAP: u16,
+                padding: u16,
+            }),
+            ///  Device address match configuration
+            DACNF: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable device address matching using device address 0
+                ENA0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 1
+                ENA1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 2
+                ENA2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 3
+                ENA3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 4
+                ENA4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 5
+                ENA5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 6
+                ENA6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 7
+                ENA7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  TxAdd for device address 0
+                TXADD0: u1,
+                ///  TxAdd for device address 1
+                TXADD1: u1,
+                ///  TxAdd for device address 2
+                TXADD2: u1,
+                ///  TxAdd for device address 3
+                TXADD3: u1,
+                ///  TxAdd for device address 4
+                TXADD4: u1,
+                ///  TxAdd for device address 5
+                TXADD5: u1,
+                ///  TxAdd for device address 6
+                TXADD6: u1,
+                ///  TxAdd for device address 7
+                TXADD7: u1,
+                padding: u16,
+            }),
+            reserved1616: [12]u8,
+            ///  Radio mode configuration register 0
+            MODECNF0: mmio.Mmio(packed struct(u32) {
+                ///  Radio ramp-up time
+                RU: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Default ramp-up time (tRXEN), compatible with firmware written for nRF51
+                        Default = 0x0,
+                        ///  Fast ramp-up (tRXEN,FAST), see electrical specification for more information
+                        Fast = 0x1,
+                    },
+                },
+                reserved8: u7,
+                ///  Default TX value
+                DTX: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Transmit '1'
+                        B1 = 0x0,
+                        ///  Transmit '0'
+                        B0 = 0x1,
+                        ///  Transmit center frequency
+                        Center = 0x2,
+                        _,
+                    },
+                },
+                padding: u22,
+            }),
+            reserved4092: [2472]u8,
+            ///  Peripheral power control
+            POWER: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.
+                POWER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Peripheral is powered off
+                        Disabled = 0x0,
+                        ///  Peripheral is powered on
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  UART with EasyDMA
+        pub const UARTE0 = extern struct {
+            ///  Start UART receiver
+            TASKS_STARTRX: u32,
+            ///  Stop UART receiver
+            TASKS_STOPRX: u32,
+            ///  Start UART transmitter
+            TASKS_STARTTX: u32,
+            ///  Stop UART transmitter
+            TASKS_STOPTX: u32,
+            reserved44: [28]u8,
+            ///  Flush RX FIFO into RX buffer
+            TASKS_FLUSHRX: u32,
+            reserved256: [208]u8,
+            ///  CTS is activated (set low). Clear To Send.
+            EVENTS_CTS: u32,
+            ///  CTS is deactivated (set high). Not Clear To Send.
+            EVENTS_NCTS: u32,
+            ///  Data received in RXD (but potentially not yet transferred to Data RAM)
+            EVENTS_RXDRDY: u32,
+            reserved272: [4]u8,
+            ///  Receive buffer is filled up
+            EVENTS_ENDRX: u32,
+            reserved284: [8]u8,
+            ///  Data sent from TXD
+            EVENTS_TXDRDY: u32,
+            ///  Last TX byte transmitted
+            EVENTS_ENDTX: u32,
+            ///  Error detected
+            EVENTS_ERROR: u32,
+            reserved324: [28]u8,
+            ///  Receiver timeout
+            EVENTS_RXTO: u32,
+            reserved332: [4]u8,
+            ///  UART receiver has started
+            EVENTS_RXSTARTED: u32,
+            ///  UART transmitter has started
+            EVENTS_TXSTARTED: u32,
+            reserved344: [4]u8,
+            ///  Transmitter stopped
+            EVENTS_TXSTOPPED: u32,
+            reserved512: [164]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved5: u5,
+                ///  Shortcut between ENDRX event and STARTRX task
+                ENDRX_STARTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between ENDRX event and STOPRX task
+                ENDRX_STOPRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u25,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for CTS event
+                CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for NCTS event
+                NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for RXDRDY event
+                RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u1,
+                ///  Enable or disable interrupt for ENDRX event
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u2,
+                ///  Enable or disable interrupt for TXDRDY event
+                TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for ENDTX event
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved17: u7,
+                ///  Enable or disable interrupt for RXTO event
+                RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u1,
+                ///  Enable or disable interrupt for RXSTARTED event
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TXSTARTED event
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved22: u1,
+                ///  Enable or disable interrupt for TXSTOPPED event
+                TXSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u9,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for CTS event
+                CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for NCTS event
+                NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for RXDRDY event
+                RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u1,
+                ///  Write '1' to Enable interrupt for ENDRX event
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u2,
+                ///  Write '1' to Enable interrupt for TXDRDY event
+                TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for ENDTX event
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved17: u7,
+                ///  Write '1' to Enable interrupt for RXTO event
+                RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u1,
+                ///  Write '1' to Enable interrupt for RXSTARTED event
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TXSTARTED event
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved22: u1,
+                ///  Write '1' to Enable interrupt for TXSTOPPED event
+                TXSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u9,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for CTS event
+                CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for NCTS event
+                NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for RXDRDY event
+                RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u1,
+                ///  Write '1' to Disable interrupt for ENDRX event
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u2,
+                ///  Write '1' to Disable interrupt for TXDRDY event
+                TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for ENDTX event
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved17: u7,
+                ///  Write '1' to Disable interrupt for RXTO event
+                RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u1,
+                ///  Write '1' to Disable interrupt for RXSTARTED event
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TXSTARTED event
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved22: u1,
+                ///  Write '1' to Disable interrupt for TXSTOPPED event
+                TXSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u9,
+            }),
+            reserved1152: [372]u8,
+            ///  Error source
+            ERRORSRC: mmio.Mmio(packed struct(u32) {
+                ///  Overrun error
+                OVERRUN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Parity error
+                PARITY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Framing error occurred
+                FRAMING: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Break condition
+                BREAK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1280: [124]u8,
+            ///  Enable UART
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable UARTE
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable UARTE
+                        Disabled = 0x0,
+                        ///  Enable UARTE
+                        Enabled = 0x8,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1316: [32]u8,
+            ///  Baud rate. Accuracy depends on the HFCLK source selected.
+            BAUDRATE: mmio.Mmio(packed struct(u32) {
+                ///  Baud rate
+                BAUDRATE: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  1200 baud (actual rate: 1205)
+                        Baud1200 = 0x4f000,
+                        ///  2400 baud (actual rate: 2396)
+                        Baud2400 = 0x9d000,
+                        ///  4800 baud (actual rate: 4808)
+                        Baud4800 = 0x13b000,
+                        ///  9600 baud (actual rate: 9598)
+                        Baud9600 = 0x275000,
+                        ///  14400 baud (actual rate: 14401)
+                        Baud14400 = 0x3af000,
+                        ///  19200 baud (actual rate: 19208)
+                        Baud19200 = 0x4ea000,
+                        ///  28800 baud (actual rate: 28777)
+                        Baud28800 = 0x75c000,
+                        ///  31250 baud
+                        Baud31250 = 0x800000,
+                        ///  38400 baud (actual rate: 38369)
+                        Baud38400 = 0x9d0000,
+                        ///  56000 baud (actual rate: 55944)
+                        Baud56000 = 0xe50000,
+                        ///  57600 baud (actual rate: 57554)
+                        Baud57600 = 0xeb0000,
+                        ///  76800 baud (actual rate: 76923)
+                        Baud76800 = 0x13a9000,
+                        ///  115200 baud (actual rate: 115108)
+                        Baud115200 = 0x1d60000,
+                        ///  230400 baud (actual rate: 231884)
+                        Baud230400 = 0x3b00000,
+                        ///  250000 baud
+                        Baud250000 = 0x4000000,
+                        ///  460800 baud (actual rate: 457143)
+                        Baud460800 = 0x7400000,
+                        ///  921600 baud (actual rate: 941176)
+                        Baud921600 = 0xf000000,
+                        ///  1Mega baud
+                        Baud1M = 0x10000000,
+                        _,
+                    },
+                },
+            }),
+            reserved1388: [68]u8,
+            ///  Configuration of parity and hardware flow control
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Hardware flow control
+                HWFC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Parity
+                PARITY: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Exclude parity bit
+                        Excluded = 0x0,
+                        ///  Include parity bit
+                        Included = 0x7,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+        };
+
+        ///  Universal Asynchronous Receiver/Transmitter
+        pub const UART0 = extern struct {
+            ///  Start UART receiver
+            TASKS_STARTRX: u32,
+            ///  Stop UART receiver
+            TASKS_STOPRX: u32,
+            ///  Start UART transmitter
+            TASKS_STARTTX: u32,
+            ///  Stop UART transmitter
+            TASKS_STOPTX: u32,
+            reserved28: [12]u8,
+            ///  Suspend UART
+            TASKS_SUSPEND: u32,
+            reserved256: [224]u8,
+            ///  CTS is activated (set low). Clear To Send.
+            EVENTS_CTS: u32,
+            ///  CTS is deactivated (set high). Not Clear To Send.
+            EVENTS_NCTS: u32,
+            ///  Data received in RXD
+            EVENTS_RXDRDY: u32,
+            reserved284: [16]u8,
+            ///  Data sent from TXD
+            EVENTS_TXDRDY: u32,
+            reserved292: [4]u8,
+            ///  Error detected
+            EVENTS_ERROR: u32,
+            reserved324: [28]u8,
+            ///  Receiver timeout
+            EVENTS_RXTO: u32,
+            reserved512: [184]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                ///  Shortcut between CTS event and STARTRX task
+                CTS_STARTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between NCTS event and STOPRX task
+                NCTS_STOPRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for CTS event
+                CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for NCTS event
+                NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for RXDRDY event
+                RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u4,
+                ///  Write '1' to Enable interrupt for TXDRDY event
+                TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u1,
+                ///  Write '1' to Enable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved17: u7,
+                ///  Write '1' to Enable interrupt for RXTO event
+                RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u14,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for CTS event
+                CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for NCTS event
+                NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for RXDRDY event
+                RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u4,
+                ///  Write '1' to Disable interrupt for TXDRDY event
+                TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u1,
+                ///  Write '1' to Disable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved17: u7,
+                ///  Write '1' to Disable interrupt for RXTO event
+                RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u14,
+            }),
+            reserved1152: [372]u8,
+            ///  Error source
+            ERRORSRC: mmio.Mmio(packed struct(u32) {
+                ///  Overrun error
+                OVERRUN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Parity error
+                PARITY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Framing error occurred
+                FRAMING: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Break condition
+                BREAK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1280: [124]u8,
+            ///  Enable UART
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable UART
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable UART
+                        Disabled = 0x0,
+                        ///  Enable UART
+                        Enabled = 0x4,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1288: [4]u8,
+            ///  Pin select for RTS
+            PSELRTS: mmio.Mmio(packed struct(u32) {
+                ///  Pin number configuration for UART RTS signal
+                PSELRTS: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  Disconnect
+                        Disconnected = 0xffffffff,
+                        _,
+                    },
+                },
+            }),
+            ///  Pin select for TXD
+            PSELTXD: mmio.Mmio(packed struct(u32) {
+                ///  Pin number configuration for UART TXD signal
+                PSELTXD: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  Disconnect
+                        Disconnected = 0xffffffff,
+                        _,
+                    },
+                },
+            }),
+            ///  Pin select for CTS
+            PSELCTS: mmio.Mmio(packed struct(u32) {
+                ///  Pin number configuration for UART CTS signal
+                PSELCTS: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  Disconnect
+                        Disconnected = 0xffffffff,
+                        _,
+                    },
+                },
+            }),
+            ///  Pin select for RXD
+            PSELRXD: mmio.Mmio(packed struct(u32) {
+                ///  Pin number configuration for UART RXD signal
+                PSELRXD: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  Disconnect
+                        Disconnected = 0xffffffff,
+                        _,
+                    },
+                },
+            }),
+            ///  RXD register
+            RXD: mmio.Mmio(packed struct(u32) {
+                ///  RX data received in previous transfers, double buffered
+                RXD: u8,
+                padding: u24,
+            }),
+            ///  TXD register
+            TXD: mmio.Mmio(packed struct(u32) {
+                ///  TX data to be transferred
+                TXD: u8,
+                padding: u24,
+            }),
+            reserved1316: [4]u8,
+            ///  Baud rate
+            BAUDRATE: mmio.Mmio(packed struct(u32) {
+                ///  Baud rate
+                BAUDRATE: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  1200 baud (actual rate: 1205)
+                        Baud1200 = 0x4f000,
+                        ///  2400 baud (actual rate: 2396)
+                        Baud2400 = 0x9d000,
+                        ///  4800 baud (actual rate: 4808)
+                        Baud4800 = 0x13b000,
+                        ///  9600 baud (actual rate: 9598)
+                        Baud9600 = 0x275000,
+                        ///  14400 baud (actual rate: 14414)
+                        Baud14400 = 0x3b0000,
+                        ///  19200 baud (actual rate: 19208)
+                        Baud19200 = 0x4ea000,
+                        ///  28800 baud (actual rate: 28829)
+                        Baud28800 = 0x75f000,
+                        ///  31250 baud
+                        Baud31250 = 0x800000,
+                        ///  38400 baud (actual rate: 38462)
+                        Baud38400 = 0x9d5000,
+                        ///  56000 baud (actual rate: 55944)
+                        Baud56000 = 0xe50000,
+                        ///  57600 baud (actual rate: 57762)
+                        Baud57600 = 0xebf000,
+                        ///  76800 baud (actual rate: 76923)
+                        Baud76800 = 0x13a9000,
+                        ///  115200 baud (actual rate: 115942)
+                        Baud115200 = 0x1d7e000,
+                        ///  230400 baud (actual rate: 231884)
+                        Baud230400 = 0x3afb000,
+                        ///  250000 baud
+                        Baud250000 = 0x4000000,
+                        ///  460800 baud (actual rate: 470588)
+                        Baud460800 = 0x75f7000,
+                        ///  921600 baud (actual rate: 941176)
+                        Baud921600 = 0xebed000,
+                        ///  1Mega baud
+                        Baud1M = 0x10000000,
+                        _,
+                    },
+                },
+            }),
+            reserved1388: [68]u8,
+            ///  Configuration of parity and hardware flow control
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Hardware flow control
+                HWFC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Parity
+                PARITY: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Exclude parity bit
+                        Excluded = 0x0,
+                        ///  Include parity bit
+                        Included = 0x7,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+        };
+
+        ///  Serial Peripheral Interface Master with EasyDMA 0
+        pub const SPIM0 = extern struct {
+            reserved16: [16]u8,
+            ///  Start SPI transaction
+            TASKS_START: u32,
+            ///  Stop SPI transaction
+            TASKS_STOP: u32,
+            reserved28: [4]u8,
+            ///  Suspend SPI transaction
+            TASKS_SUSPEND: u32,
+            ///  Resume SPI transaction
+            TASKS_RESUME: u32,
+            reserved260: [224]u8,
+            ///  SPI transaction has stopped
+            EVENTS_STOPPED: u32,
+            reserved272: [8]u8,
+            ///  End of RXD buffer reached
+            EVENTS_ENDRX: u32,
+            reserved280: [4]u8,
+            ///  End of RXD buffer and TXD buffer reached
+            EVENTS_END: u32,
+            reserved288: [4]u8,
+            ///  End of TXD buffer reached
+            EVENTS_ENDTX: u32,
+            reserved332: [40]u8,
+            ///  Transaction started
+            EVENTS_STARTED: u32,
+            reserved512: [176]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved17: u17,
+                ///  Shortcut between END event and START task
+                END_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u14,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Enable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u2,
+                ///  Write '1' to Enable interrupt for ENDRX event
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved6: u1,
+                ///  Write '1' to Enable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved8: u1,
+                ///  Write '1' to Enable interrupt for ENDTX event
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u10,
+                ///  Write '1' to Enable interrupt for STARTED event
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u2,
+                ///  Write '1' to Disable interrupt for ENDRX event
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved6: u1,
+                ///  Write '1' to Disable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved8: u1,
+                ///  Write '1' to Disable interrupt for ENDTX event
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u10,
+                ///  Write '1' to Disable interrupt for STARTED event
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            reserved1280: [500]u8,
+            ///  Enable SPIM
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable SPIM
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable SPIM
+                        Disabled = 0x0,
+                        ///  Enable SPIM
+                        Enabled = 0x7,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1316: [32]u8,
+            ///  SPI frequency. Accuracy depends on the HFCLK source selected.
+            FREQUENCY: mmio.Mmio(packed struct(u32) {
+                ///  SPI master data rate
+                FREQUENCY: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  125 kbps
+                        K125 = 0x2000000,
+                        ///  250 kbps
+                        K250 = 0x4000000,
+                        ///  500 kbps
+                        K500 = 0x8000000,
+                        ///  1 Mbps
+                        M1 = 0x10000000,
+                        ///  2 Mbps
+                        M2 = 0x20000000,
+                        ///  4 Mbps
+                        M4 = 0x40000000,
+                        ///  8 Mbps
+                        M8 = 0x80000000,
+                        _,
+                    },
+                },
+            }),
+            reserved1364: [44]u8,
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Bit order
+                ORDER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Most significant bit shifted out first
+                        MsbFirst = 0x0,
+                        ///  Least significant bit shifted out first
+                        LsbFirst = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) phase
+                CPHA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Sample on leading edge of clock, shift serial data on trailing edge
+                        Leading = 0x0,
+                        ///  Sample on trailing edge of clock, shift serial data on leading edge
+                        Trailing = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) polarity
+                CPOL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Active high
+                        ActiveHigh = 0x0,
+                        ///  Active low
+                        ActiveLow = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1472: [104]u8,
+            ///  Over-read character. Character clocked out in case and over-read of the TXD buffer.
+            ORC: mmio.Mmio(packed struct(u32) {
+                ///  Over-read character. Character clocked out in case and over-read of the TXD buffer.
+                ORC: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  SPI Slave 0
+        pub const SPIS0 = extern struct {
+            reserved36: [36]u8,
+            ///  Acquire SPI semaphore
+            TASKS_ACQUIRE: u32,
+            ///  Release SPI semaphore, enabling the SPI slave to acquire it
+            TASKS_RELEASE: u32,
+            reserved260: [216]u8,
+            ///  Granted transaction completed
+            EVENTS_END: u32,
+            reserved272: [8]u8,
+            ///  End of RXD buffer reached
+            EVENTS_ENDRX: u32,
+            reserved296: [20]u8,
+            ///  Semaphore acquired
+            EVENTS_ACQUIRED: u32,
+            reserved512: [212]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Shortcut between END event and ACQUIRE task
+                END_ACQUIRE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Enable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u2,
+                ///  Write '1' to Enable interrupt for ENDRX event
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u5,
+                ///  Write '1' to Enable interrupt for ACQUIRED event
+                ACQUIRED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u21,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Disable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u2,
+                ///  Write '1' to Disable interrupt for ENDRX event
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u5,
+                ///  Write '1' to Disable interrupt for ACQUIRED event
+                ACQUIRED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u21,
+            }),
+            reserved1024: [244]u8,
+            ///  Semaphore status register
+            SEMSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Semaphore status
+                SEMSTAT: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Semaphore is free
+                        Free = 0x0,
+                        ///  Semaphore is assigned to CPU
+                        CPU = 0x1,
+                        ///  Semaphore is assigned to SPI slave
+                        SPIS = 0x2,
+                        ///  Semaphore is assigned to SPI but a handover to the CPU is pending
+                        CPUPending = 0x3,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1088: [60]u8,
+            ///  Status from last transaction
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  TX buffer over-read detected, and prevented
+                OVERREAD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  RX buffer overflow detected, and prevented
+                OVERFLOW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1280: [188]u8,
+            ///  Enable SPI slave
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable SPI slave
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable SPI slave
+                        Disabled = 0x0,
+                        ///  Enable SPI slave
+                        Enabled = 0x2,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1364: [80]u8,
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Bit order
+                ORDER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Most significant bit shifted out first
+                        MsbFirst = 0x0,
+                        ///  Least significant bit shifted out first
+                        LsbFirst = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) phase
+                CPHA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Sample on leading edge of clock, shift serial data on trailing edge
+                        Leading = 0x0,
+                        ///  Sample on trailing edge of clock, shift serial data on leading edge
+                        Trailing = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) polarity
+                CPOL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Active high
+                        ActiveHigh = 0x0,
+                        ///  Active low
+                        ActiveLow = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1372: [4]u8,
+            ///  Default character. Character clocked out in case of an ignored transaction.
+            DEF: mmio.Mmio(packed struct(u32) {
+                ///  Default character. Character clocked out in case of an ignored transaction.
+                DEF: u8,
+                padding: u24,
+            }),
+            reserved1472: [96]u8,
+            ///  Over-read character
+            ORC: mmio.Mmio(packed struct(u32) {
+                ///  Over-read character. Character clocked out after an over-read of the transmit buffer.
+                ORC: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  I2C compatible Two-Wire Master Interface with EasyDMA 0
+        pub const TWIM0 = extern struct {
+            ///  Start TWI receive sequence
+            TASKS_STARTRX: u32,
+            reserved8: [4]u8,
+            ///  Start TWI transmit sequence
+            TASKS_STARTTX: u32,
+            reserved20: [8]u8,
+            ///  Stop TWI transaction. Must be issued while the TWI master is not suspended.
+            TASKS_STOP: u32,
+            reserved28: [4]u8,
+            ///  Suspend TWI transaction
+            TASKS_SUSPEND: u32,
+            ///  Resume TWI transaction
+            TASKS_RESUME: u32,
+            reserved260: [224]u8,
+            ///  TWI stopped
+            EVENTS_STOPPED: u32,
+            reserved292: [28]u8,
+            ///  TWI error
+            EVENTS_ERROR: u32,
+            reserved328: [32]u8,
+            ///  Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
+            EVENTS_SUSPENDED: u32,
+            ///  Receive sequence started
+            EVENTS_RXSTARTED: u32,
+            ///  Transmit sequence started
+            EVENTS_TXSTARTED: u32,
+            reserved348: [8]u8,
+            ///  Byte boundary, starting to receive the last byte
+            EVENTS_LASTRX: u32,
+            ///  Byte boundary, starting to transmit the last byte
+            EVENTS_LASTTX: u32,
+            reserved512: [156]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved7: u7,
+                ///  Shortcut between LASTTX event and STARTRX task
+                LASTTX_STARTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between LASTTX event and SUSPEND task
+                LASTTX_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between LASTTX event and STOP task
+                LASTTX_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between LASTRX event and STARTTX task
+                LASTRX_STARTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                reserved12: u1,
+                ///  Shortcut between LASTRX event and STOP task
+                LASTRX_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u19,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Enable or disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Enable or disable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u8,
+                ///  Enable or disable interrupt for SUSPENDED event
+                SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for RXSTARTED event
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TXSTARTED event
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved23: u2,
+                ///  Enable or disable interrupt for LASTRX event
+                LASTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for LASTTX event
+                LASTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Enable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Write '1' to Enable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u8,
+                ///  Write '1' to Enable interrupt for SUSPENDED event
+                SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for RXSTARTED event
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TXSTARTED event
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved23: u2,
+                ///  Write '1' to Enable interrupt for LASTRX event
+                LASTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for LASTTX event
+                LASTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Write '1' to Disable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u8,
+                ///  Write '1' to Disable interrupt for SUSPENDED event
+                SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for RXSTARTED event
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TXSTARTED event
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved23: u2,
+                ///  Write '1' to Disable interrupt for LASTRX event
+                LASTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for LASTTX event
+                LASTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            reserved1220: [440]u8,
+            ///  Error source
+            ERRORSRC: mmio.Mmio(packed struct(u32) {
+                ///  Overrun error
+                OVERRUN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotReceived = 0x0,
+                        ///  Error occurred
+                        Received = 0x1,
+                    },
+                },
+                ///  NACK received after sending the address (write '1' to clear)
+                ANACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotReceived = 0x0,
+                        ///  Error occurred
+                        Received = 0x1,
+                    },
+                },
+                ///  NACK received after sending a data byte (write '1' to clear)
+                DNACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotReceived = 0x0,
+                        ///  Error occurred
+                        Received = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1280: [56]u8,
+            ///  Enable TWIM
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable TWIM
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable TWIM
+                        Disabled = 0x0,
+                        ///  Enable TWIM
+                        Enabled = 0x6,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1316: [32]u8,
+            ///  TWI frequency
+            FREQUENCY: mmio.Mmio(packed struct(u32) {
+                ///  TWI master clock frequency
+                FREQUENCY: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  100 kbps
+                        K100 = 0x1980000,
+                        ///  250 kbps
+                        K250 = 0x4000000,
+                        ///  400 kbps
+                        K400 = 0x6400000,
+                        _,
+                    },
+                },
+            }),
+            reserved1416: [96]u8,
+            ///  Address used in the TWI transfer
+            ADDRESS: mmio.Mmio(packed struct(u32) {
+                ///  Address used in the TWI transfer
+                ADDRESS: u7,
+                padding: u25,
+            }),
+        };
+
+        ///  I2C compatible Two-Wire Slave Interface with EasyDMA 0
+        pub const TWIS0 = extern struct {
+            reserved20: [20]u8,
+            ///  Stop TWI transaction
+            TASKS_STOP: u32,
+            reserved28: [4]u8,
+            ///  Suspend TWI transaction
+            TASKS_SUSPEND: u32,
+            ///  Resume TWI transaction
+            TASKS_RESUME: u32,
+            reserved48: [12]u8,
+            ///  Prepare the TWI slave to respond to a write command
+            TASKS_PREPARERX: u32,
+            ///  Prepare the TWI slave to respond to a read command
+            TASKS_PREPARETX: u32,
+            reserved260: [204]u8,
+            ///  TWI stopped
+            EVENTS_STOPPED: u32,
+            reserved292: [28]u8,
+            ///  TWI error
+            EVENTS_ERROR: u32,
+            reserved332: [36]u8,
+            ///  Receive sequence started
+            EVENTS_RXSTARTED: u32,
+            ///  Transmit sequence started
+            EVENTS_TXSTARTED: u32,
+            reserved356: [16]u8,
+            ///  Write command received
+            EVENTS_WRITE: u32,
+            ///  Read command received
+            EVENTS_READ: u32,
+            reserved512: [148]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved13: u13,
+                ///  Shortcut between WRITE event and SUSPEND task
+                WRITE_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between READ event and SUSPEND task
+                READ_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u17,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Enable or disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Enable or disable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u9,
+                ///  Enable or disable interrupt for RXSTARTED event
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TXSTARTED event
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved25: u4,
+                ///  Enable or disable interrupt for WRITE event
+                WRITE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for READ event
+                READ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u5,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Enable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Write '1' to Enable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u9,
+                ///  Write '1' to Enable interrupt for RXSTARTED event
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TXSTARTED event
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved25: u4,
+                ///  Write '1' to Enable interrupt for WRITE event
+                WRITE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for READ event
+                READ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u5,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Write '1' to Disable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u9,
+                ///  Write '1' to Disable interrupt for RXSTARTED event
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TXSTARTED event
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved25: u4,
+                ///  Write '1' to Disable interrupt for WRITE event
+                WRITE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for READ event
+                READ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u5,
+            }),
+            reserved1232: [452]u8,
+            ///  Error source
+            ERRORSRC: mmio.Mmio(packed struct(u32) {
+                ///  RX buffer overflow detected, and prevented
+                OVERFLOW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotDetected = 0x0,
+                        ///  Error occurred
+                        Detected = 0x1,
+                    },
+                },
+                reserved2: u1,
+                ///  NACK sent after receiving a data byte
+                DNACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotReceived = 0x0,
+                        ///  Error occurred
+                        Received = 0x1,
+                    },
+                },
+                ///  TX buffer over-read detected, and prevented
+                OVERREAD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotDetected = 0x0,
+                        ///  Error occurred
+                        Detected = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Status register indicating which address had a match
+            MATCH: mmio.Mmio(packed struct(u32) {
+                ///  Which of the addresses in {ADDRESS} matched the incoming address
+                MATCH: u1,
+                padding: u31,
+            }),
+            reserved1280: [40]u8,
+            ///  Enable TWIS
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable TWIS
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable TWIS
+                        Disabled = 0x0,
+                        ///  Enable TWIS
+                        Enabled = 0x9,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1416: [132]u8,
+            ///  Description collection[0]: TWI slave address 0
+            ADDRESS: [2]mmio.Mmio(packed struct(u32) {
+                ///  TWI slave address
+                ADDRESS: u7,
+                padding: u25,
+            }),
+            reserved1428: [4]u8,
+            ///  Configuration register for the address match mechanism
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable address matching on ADDRESS[0]
+                ADDRESS0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable address matching on ADDRESS[1]
+                ADDRESS1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1472: [40]u8,
+            ///  Over-read character. Character sent out in case of an over-read of the transmit buffer.
+            ORC: mmio.Mmio(packed struct(u32) {
+                ///  Over-read character. Character sent out in case of an over-read of the transmit buffer.
+                ORC: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  Serial Peripheral Interface 0
+        pub const SPI0 = extern struct {
+            reserved264: [264]u8,
+            ///  TXD byte sent and RXD byte received
+            EVENTS_READY: u32,
+            reserved772: [504]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Write '1' to Enable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Write '1' to Disable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1280: [500]u8,
+            ///  Enable SPI
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable SPI
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable SPI
+                        Disabled = 0x0,
+                        ///  Enable SPI
+                        Enabled = 0x1,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1304: [20]u8,
+            ///  RXD register
+            RXD: mmio.Mmio(packed struct(u32) {
+                ///  RX data received. Double buffered
+                RXD: u8,
+                padding: u24,
+            }),
+            ///  TXD register
+            TXD: mmio.Mmio(packed struct(u32) {
+                ///  TX data to send. Double buffered
+                TXD: u8,
+                padding: u24,
+            }),
+            reserved1316: [4]u8,
+            ///  SPI frequency
+            FREQUENCY: mmio.Mmio(packed struct(u32) {
+                ///  SPI master data rate
+                FREQUENCY: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  125 kbps
+                        K125 = 0x2000000,
+                        ///  250 kbps
+                        K250 = 0x4000000,
+                        ///  500 kbps
+                        K500 = 0x8000000,
+                        ///  1 Mbps
+                        M1 = 0x10000000,
+                        ///  2 Mbps
+                        M2 = 0x20000000,
+                        ///  4 Mbps
+                        M4 = 0x40000000,
+                        ///  8 Mbps
+                        M8 = 0x80000000,
+                        _,
+                    },
+                },
+            }),
+            reserved1364: [44]u8,
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Bit order
+                ORDER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Most significant bit shifted out first
+                        MsbFirst = 0x0,
+                        ///  Least significant bit shifted out first
+                        LsbFirst = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) phase
+                CPHA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Sample on leading edge of clock, shift serial data on trailing edge
+                        Leading = 0x0,
+                        ///  Sample on trailing edge of clock, shift serial data on leading edge
+                        Trailing = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) polarity
+                CPOL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Active high
+                        ActiveHigh = 0x0,
+                        ///  Active low
+                        ActiveLow = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+        };
+
+        ///  I2C compatible Two-Wire Interface 0
+        pub const TWI0 = extern struct {
+            ///  Start TWI receive sequence
+            TASKS_STARTRX: u32,
+            reserved8: [4]u8,
+            ///  Start TWI transmit sequence
+            TASKS_STARTTX: u32,
+            reserved20: [8]u8,
+            ///  Stop TWI transaction
+            TASKS_STOP: u32,
+            reserved28: [4]u8,
+            ///  Suspend TWI transaction
+            TASKS_SUSPEND: u32,
+            ///  Resume TWI transaction
+            TASKS_RESUME: u32,
+            reserved260: [224]u8,
+            ///  TWI stopped
+            EVENTS_STOPPED: u32,
+            ///  TWI RXD byte received
+            EVENTS_RXDREADY: u32,
+            reserved284: [16]u8,
+            ///  TWI TXD byte sent
+            EVENTS_TXDSENT: u32,
+            reserved292: [4]u8,
+            ///  TWI error
+            EVENTS_ERROR: u32,
+            reserved312: [16]u8,
+            ///  TWI byte boundary, generated before each byte that is sent or received
+            EVENTS_BB: u32,
+            reserved328: [12]u8,
+            ///  TWI entered the suspended state
+            EVENTS_SUSPENDED: u32,
+            reserved512: [180]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between BB event and SUSPEND task
+                BB_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between BB event and STOP task
+                BB_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Enable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for RXDREADY event
+                RXDREADY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u4,
+                ///  Write '1' to Enable interrupt for TXDSENT event
+                TXDSENT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u1,
+                ///  Write '1' to Enable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved14: u4,
+                ///  Write '1' to Enable interrupt for BB event
+                BB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u3,
+                ///  Write '1' to Enable interrupt for SUSPENDED event
+                SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u13,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for RXDREADY event
+                RXDREADY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u4,
+                ///  Write '1' to Disable interrupt for TXDSENT event
+                TXDSENT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u1,
+                ///  Write '1' to Disable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved14: u4,
+                ///  Write '1' to Disable interrupt for BB event
+                BB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u3,
+                ///  Write '1' to Disable interrupt for SUSPENDED event
+                SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u13,
+            }),
+            reserved1220: [440]u8,
+            ///  Error source
+            ERRORSRC: mmio.Mmio(packed struct(u32) {
+                ///  Overrun error
+                OVERRUN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: no overrun occured
+                        NotPresent = 0x0,
+                        ///  Read: overrun occured
+                        Present = 0x1,
+                    },
+                },
+                ///  NACK received after sending the address (write '1' to clear)
+                ANACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  NACK received after sending a data byte (write '1' to clear)
+                DNACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1280: [56]u8,
+            ///  Enable TWI
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable TWI
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable TWI
+                        Disabled = 0x0,
+                        ///  Enable TWI
+                        Enabled = 0x5,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1288: [4]u8,
+            ///  Pin select for SCL
+            PSELSCL: mmio.Mmio(packed struct(u32) {
+                ///  Pin number configuration for TWI SCL signal
+                PSELSCL: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  Disconnect
+                        Disconnected = 0xffffffff,
+                        _,
+                    },
+                },
+            }),
+            ///  Pin select for SDA
+            PSELSDA: mmio.Mmio(packed struct(u32) {
+                ///  Pin number configuration for TWI SDA signal
+                PSELSDA: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  Disconnect
+                        Disconnected = 0xffffffff,
+                        _,
+                    },
+                },
+            }),
+            reserved1304: [8]u8,
+            ///  RXD register
+            RXD: mmio.Mmio(packed struct(u32) {
+                ///  RXD register
+                RXD: u8,
+                padding: u24,
+            }),
+            ///  TXD register
+            TXD: mmio.Mmio(packed struct(u32) {
+                ///  TXD register
+                TXD: u8,
+                padding: u24,
+            }),
+            reserved1316: [4]u8,
+            ///  TWI frequency
+            FREQUENCY: mmio.Mmio(packed struct(u32) {
+                ///  TWI master clock frequency
+                FREQUENCY: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  100 kbps
+                        K100 = 0x1980000,
+                        ///  250 kbps
+                        K250 = 0x4000000,
+                        ///  400 kbps (actual rate 410.256 kbps)
+                        K400 = 0x6680000,
+                        _,
+                    },
+                },
+            }),
+            reserved1416: [96]u8,
+            ///  Address used in the TWI transfer
+            ADDRESS: mmio.Mmio(packed struct(u32) {
+                ///  Address used in the TWI transfer
+                ADDRESS: u7,
+                padding: u25,
+            }),
+        };
+
+        ///  GPIO Port 1
+        pub const P0 = extern struct {
+            reserved1284: [1284]u8,
+            ///  Write GPIO port
+            OUT: mmio.Mmio(packed struct(u32) {
+                ///  Pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+            }),
+            ///  Set individual bits in GPIO port
+            OUTSET: mmio.Mmio(packed struct(u32) {
+                ///  Pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+            }),
+            ///  Clear individual bits in GPIO port
+            OUTCLR: mmio.Mmio(packed struct(u32) {
+                ///  Pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+            }),
+            ///  Read GPIO port
+            IN: mmio.Mmio(packed struct(u32) {
+                ///  Pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+            }),
+            ///  Direction of GPIO pins
+            DIR: mmio.Mmio(packed struct(u32) {
+                ///  Pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+            }),
+            ///  DIR set register
+            DIRSET: mmio.Mmio(packed struct(u32) {
+                ///  Set as output pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+            }),
+            ///  DIR clear register
+            DIRCLR: mmio.Mmio(packed struct(u32) {
+                ///  Set as input pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+            }),
+            ///  Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers
+            LATCH: mmio.Mmio(packed struct(u32) {
+                ///  Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+            }),
+            ///  Select between default DETECT signal behaviour and LDETECT mode
+            DETECTMODE: mmio.Mmio(packed struct(u32) {
+                ///  Select between default DETECT signal behaviour and LDETECT mode
+                DETECTMODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  DETECT directly connected to PIN DETECT signals
+                        Default = 0x0,
+                        ///  Use the latched LDETECT behaviour
+                        LDETECT = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1792: [472]u8,
+            ///  Description collection[0]: Configuration of GPIO pins
+            PIN_CNF: [32]mmio.Mmio(packed struct(u32) {
+                ///  Pin direction. Same physical register as DIR register
+                DIR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Configure pin as an input pin
+                        Input = 0x0,
+                        ///  Configure pin as an output pin
+                        Output = 0x1,
+                    },
+                },
+                ///  Connect or disconnect input buffer
+                INPUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Connect input buffer
+                        Connect = 0x0,
+                        ///  Disconnect input buffer
+                        Disconnect = 0x1,
+                    },
+                },
+                ///  Pull configuration
+                PULL: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  No pull
+                        Disabled = 0x0,
+                        ///  Pull down on pin
+                        Pulldown = 0x1,
+                        ///  Pull up on pin
+                        Pullup = 0x3,
+                        _,
+                    },
+                },
+                reserved8: u4,
+                ///  Drive configuration
+                DRIVE: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Standard '0', standard '1'
+                        S0S1 = 0x0,
+                        ///  High drive '0', standard '1'
+                        H0S1 = 0x1,
+                        ///  Standard '0', high drive '1'
+                        S0H1 = 0x2,
+                        ///  High drive '0', high 'drive '1''
+                        H0H1 = 0x3,
+                        ///  Disconnect '0' standard '1' (normally used for wired-or connections)
+                        D0S1 = 0x4,
+                        ///  Disconnect '0', high drive '1' (normally used for wired-or connections)
+                        D0H1 = 0x5,
+                        ///  Standard '0'. disconnect '1' (normally used for wired-and connections)
+                        S0D1 = 0x6,
+                        ///  High drive '0', disconnect '1' (normally used for wired-and connections)
+                        H0D1 = 0x7,
+                    },
+                },
+                reserved16: u5,
+                ///  Pin sensing mechanism
+                SENSE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Sense for high level
+                        High = 0x2,
+                        ///  Sense for low level
+                        Low = 0x3,
+                        _,
+                    },
+                },
+                padding: u14,
+            }),
+        };
+
+        ///  FPU
+        pub const FPU = extern struct {
+            ///  Unused.
+            UNUSED: u32,
+        };
+
+        ///  Inter-IC Sound
+        pub const I2S = extern struct {
+            ///  Starts continuous I2S transfer. Also starts MCK generator when this is enabled.
+            TASKS_START: u32,
+            ///  Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated.
+            TASKS_STOP: u32,
+            reserved260: [252]u8,
+            ///  The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.
+            EVENTS_RXPTRUPD: u32,
+            ///  I2S transfer stopped.
+            EVENTS_STOPPED: u32,
+            reserved276: [8]u8,
+            ///  The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
+            EVENTS_TXPTRUPD: u32,
+            reserved768: [488]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Enable or disable interrupt for RXPTRUPD event
+                RXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved5: u2,
+                ///  Enable or disable interrupt for TXPTRUPD event
+                TXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u26,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Enable interrupt for RXPTRUPD event
+                RXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved5: u2,
+                ///  Write '1' to Enable interrupt for TXPTRUPD event
+                TXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u26,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Disable interrupt for RXPTRUPD event
+                RXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved5: u2,
+                ///  Write '1' to Disable interrupt for TXPTRUPD event
+                TXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u26,
+            }),
+            reserved1280: [500]u8,
+            ///  Enable I2S module.
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable I2S module.
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  Event Generator Unit 0
+        pub const EGU0 = extern struct {
+            ///  Description collection[0]: Trigger 0 for triggering the corresponding TRIGGERED[0] event
+            TASKS_TRIGGER: [16]u32,
+            reserved256: [192]u8,
+            ///  Description collection[0]: Event number 0 generated by triggering the corresponding TRIGGER[0] task
+            EVENTS_TRIGGERED: [16]u32,
+            reserved768: [448]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for TRIGGERED[0] event
+                TRIGGERED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[1] event
+                TRIGGERED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[2] event
+                TRIGGERED2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[3] event
+                TRIGGERED3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[4] event
+                TRIGGERED4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[5] event
+                TRIGGERED5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[6] event
+                TRIGGERED6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[7] event
+                TRIGGERED7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[8] event
+                TRIGGERED8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[9] event
+                TRIGGERED9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[10] event
+                TRIGGERED10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[11] event
+                TRIGGERED11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[12] event
+                TRIGGERED12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[13] event
+                TRIGGERED13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[14] event
+                TRIGGERED14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TRIGGERED[15] event
+                TRIGGERED15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u16,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for TRIGGERED[0] event
+                TRIGGERED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[1] event
+                TRIGGERED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[2] event
+                TRIGGERED2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[3] event
+                TRIGGERED3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[4] event
+                TRIGGERED4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[5] event
+                TRIGGERED5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[6] event
+                TRIGGERED6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[7] event
+                TRIGGERED7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[8] event
+                TRIGGERED8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[9] event
+                TRIGGERED9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[10] event
+                TRIGGERED10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[11] event
+                TRIGGERED11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[12] event
+                TRIGGERED12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[13] event
+                TRIGGERED13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[14] event
+                TRIGGERED14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TRIGGERED[15] event
+                TRIGGERED15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u16,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for TRIGGERED[0] event
+                TRIGGERED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[1] event
+                TRIGGERED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[2] event
+                TRIGGERED2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[3] event
+                TRIGGERED3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[4] event
+                TRIGGERED4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[5] event
+                TRIGGERED5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[6] event
+                TRIGGERED6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[7] event
+                TRIGGERED7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[8] event
+                TRIGGERED8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[9] event
+                TRIGGERED9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[10] event
+                TRIGGERED10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[11] event
+                TRIGGERED11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[12] event
+                TRIGGERED12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[13] event
+                TRIGGERED13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[14] event
+                TRIGGERED14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TRIGGERED[15] event
+                TRIGGERED15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u16,
+            }),
+        };
+
+        ///  Memory Watch Unit
+        pub const MWU = extern struct {
+            reserved768: [768]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for REGION[0].WA event
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for REGION[0].RA event
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for REGION[1].WA event
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for REGION[1].RA event
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for REGION[2].WA event
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for REGION[2].RA event
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for REGION[3].WA event
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for REGION[3].RA event
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Enable or disable interrupt for PREGION[0].WA event
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for PREGION[0].RA event
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for PREGION[1].WA event
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for PREGION[1].RA event
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for REGION[0].WA event
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for REGION[0].RA event
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for REGION[1].WA event
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for REGION[1].RA event
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for REGION[2].WA event
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for REGION[2].RA event
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for REGION[3].WA event
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for REGION[3].RA event
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Write '1' to Enable interrupt for PREGION[0].WA event
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for PREGION[0].RA event
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for PREGION[1].WA event
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for PREGION[1].RA event
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for REGION[0].WA event
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for REGION[0].RA event
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for REGION[1].WA event
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for REGION[1].RA event
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for REGION[2].WA event
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for REGION[2].RA event
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for REGION[3].WA event
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for REGION[3].RA event
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Write '1' to Disable interrupt for PREGION[0].WA event
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for PREGION[0].RA event
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for PREGION[1].WA event
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for PREGION[1].RA event
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            reserved800: [20]u8,
+            ///  Enable or disable non-maskable interrupt
+            NMIEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable non-maskable interrupt for REGION[0].WA event
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable non-maskable interrupt for REGION[0].RA event
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable non-maskable interrupt for REGION[1].WA event
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable non-maskable interrupt for REGION[1].RA event
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable non-maskable interrupt for REGION[2].WA event
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable non-maskable interrupt for REGION[2].RA event
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable non-maskable interrupt for REGION[3].WA event
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable non-maskable interrupt for REGION[3].RA event
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Enable or disable non-maskable interrupt for PREGION[0].WA event
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable non-maskable interrupt for PREGION[0].RA event
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable non-maskable interrupt for PREGION[1].WA event
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable non-maskable interrupt for PREGION[1].RA event
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Enable non-maskable interrupt
+            NMIENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable non-maskable interrupt for REGION[0].WA event
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable non-maskable interrupt for REGION[0].RA event
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable non-maskable interrupt for REGION[1].WA event
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable non-maskable interrupt for REGION[1].RA event
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable non-maskable interrupt for REGION[2].WA event
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable non-maskable interrupt for REGION[2].RA event
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable non-maskable interrupt for REGION[3].WA event
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable non-maskable interrupt for REGION[3].RA event
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Write '1' to Enable non-maskable interrupt for PREGION[0].WA event
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable non-maskable interrupt for PREGION[0].RA event
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable non-maskable interrupt for PREGION[1].WA event
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable non-maskable interrupt for PREGION[1].RA event
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Disable non-maskable interrupt
+            NMIENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable non-maskable interrupt for REGION[0].WA event
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable non-maskable interrupt for REGION[0].RA event
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable non-maskable interrupt for REGION[1].WA event
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable non-maskable interrupt for REGION[1].RA event
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable non-maskable interrupt for REGION[2].WA event
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable non-maskable interrupt for REGION[2].RA event
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable non-maskable interrupt for REGION[3].WA event
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable non-maskable interrupt for REGION[3].RA event
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Write '1' to Disable non-maskable interrupt for PREGION[0].WA event
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable non-maskable interrupt for PREGION[0].RA event
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable non-maskable interrupt for PREGION[1].WA event
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable non-maskable interrupt for PREGION[1].RA event
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            reserved1296: [484]u8,
+            ///  Enable/disable regions watch
+            REGIONEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable/disable write access watch in region[0]
+                RGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this region
+                        Disable = 0x0,
+                        ///  Enable write access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in region[0]
+                RGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this region
+                        Disable = 0x0,
+                        ///  Enable read access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable write access watch in region[1]
+                RGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this region
+                        Disable = 0x0,
+                        ///  Enable write access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in region[1]
+                RGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this region
+                        Disable = 0x0,
+                        ///  Enable read access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable write access watch in region[2]
+                RGN2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this region
+                        Disable = 0x0,
+                        ///  Enable write access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in region[2]
+                RGN2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this region
+                        Disable = 0x0,
+                        ///  Enable read access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable write access watch in region[3]
+                RGN3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this region
+                        Disable = 0x0,
+                        ///  Enable write access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in region[3]
+                RGN3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this region
+                        Disable = 0x0,
+                        ///  Enable read access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Enable/disable write access watch in PREGION[0]
+                PRGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this PREGION
+                        Disable = 0x0,
+                        ///  Enable write access watch in this PREGION
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in PREGION[0]
+                PRGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this PREGION
+                        Disable = 0x0,
+                        ///  Enable read access watch in this PREGION
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable write access watch in PREGION[1]
+                PRGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this PREGION
+                        Disable = 0x0,
+                        ///  Enable write access watch in this PREGION
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in PREGION[1]
+                PRGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this PREGION
+                        Disable = 0x0,
+                        ///  Enable read access watch in this PREGION
+                        Enable = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Enable regions watch
+            REGIONENSET: mmio.Mmio(packed struct(u32) {
+                ///  Enable write access watch in region[0]
+                RGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in region[0]
+                RGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable write access watch in region[1]
+                RGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in region[1]
+                RGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable write access watch in region[2]
+                RGN2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in region[2]
+                RGN2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable write access watch in region[3]
+                RGN3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in region[3]
+                RGN3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Enable write access watch in PREGION[0]
+                PRGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in PREGION[0]
+                PRGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable write access watch in PREGION[1]
+                PRGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in PREGION[1]
+                PRGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Disable regions watch
+            REGIONENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Disable write access watch in region[0]
+                RGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in region[0]
+                RGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable write access watch in region[1]
+                RGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in region[1]
+                RGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable write access watch in region[2]
+                RGN2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in region[2]
+                RGN2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable write access watch in region[3]
+                RGN3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in region[3]
+                RGN3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Disable write access watch in PREGION[0]
+                PRGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in PREGION[0]
+                PRGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable write access watch in PREGION[1]
+                PRGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in PREGION[1]
+                PRGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+        };
+
+        ///  Programmable Peripheral Interconnect
+        pub const PPI = extern struct {
+            reserved1280: [1280]u8,
+            ///  Channel enable register
+            CHEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable channel 0
+                CH0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 1
+                CH1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 2
+                CH2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 3
+                CH3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 4
+                CH4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 5
+                CH5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 6
+                CH6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 7
+                CH7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 8
+                CH8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 9
+                CH9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 10
+                CH10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 11
+                CH11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 12
+                CH12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 13
+                CH13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 14
+                CH14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 15
+                CH15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 16
+                CH16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 17
+                CH17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 18
+                CH18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 19
+                CH19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 20
+                CH20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 21
+                CH21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 22
+                CH22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 23
+                CH23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 24
+                CH24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 25
+                CH25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 26
+                CH26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 27
+                CH27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 28
+                CH28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 29
+                CH29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 30
+                CH30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 31
+                CH31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            ///  Channel enable set register
+            CHENSET: mmio.Mmio(packed struct(u32) {
+                ///  Channel 0 enable set register. Writing '0' has no effect
+                CH0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 1 enable set register. Writing '0' has no effect
+                CH1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 2 enable set register. Writing '0' has no effect
+                CH2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 3 enable set register. Writing '0' has no effect
+                CH3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 4 enable set register. Writing '0' has no effect
+                CH4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 5 enable set register. Writing '0' has no effect
+                CH5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 6 enable set register. Writing '0' has no effect
+                CH6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 7 enable set register. Writing '0' has no effect
+                CH7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 8 enable set register. Writing '0' has no effect
+                CH8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 9 enable set register. Writing '0' has no effect
+                CH9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 10 enable set register. Writing '0' has no effect
+                CH10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 11 enable set register. Writing '0' has no effect
+                CH11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 12 enable set register. Writing '0' has no effect
+                CH12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 13 enable set register. Writing '0' has no effect
+                CH13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 14 enable set register. Writing '0' has no effect
+                CH14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 15 enable set register. Writing '0' has no effect
+                CH15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 16 enable set register. Writing '0' has no effect
+                CH16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 17 enable set register. Writing '0' has no effect
+                CH17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 18 enable set register. Writing '0' has no effect
+                CH18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 19 enable set register. Writing '0' has no effect
+                CH19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 20 enable set register. Writing '0' has no effect
+                CH20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 21 enable set register. Writing '0' has no effect
+                CH21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 22 enable set register. Writing '0' has no effect
+                CH22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 23 enable set register. Writing '0' has no effect
+                CH23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 24 enable set register. Writing '0' has no effect
+                CH24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 25 enable set register. Writing '0' has no effect
+                CH25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 26 enable set register. Writing '0' has no effect
+                CH26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 27 enable set register. Writing '0' has no effect
+                CH27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 28 enable set register. Writing '0' has no effect
+                CH28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 29 enable set register. Writing '0' has no effect
+                CH29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 30 enable set register. Writing '0' has no effect
+                CH30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 31 enable set register. Writing '0' has no effect
+                CH31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            ///  Channel enable clear register
+            CHENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Channel 0 enable clear register. Writing '0' has no effect
+                CH0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 1 enable clear register. Writing '0' has no effect
+                CH1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 2 enable clear register. Writing '0' has no effect
+                CH2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 3 enable clear register. Writing '0' has no effect
+                CH3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 4 enable clear register. Writing '0' has no effect
+                CH4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 5 enable clear register. Writing '0' has no effect
+                CH5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 6 enable clear register. Writing '0' has no effect
+                CH6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 7 enable clear register. Writing '0' has no effect
+                CH7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 8 enable clear register. Writing '0' has no effect
+                CH8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 9 enable clear register. Writing '0' has no effect
+                CH9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 10 enable clear register. Writing '0' has no effect
+                CH10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 11 enable clear register. Writing '0' has no effect
+                CH11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 12 enable clear register. Writing '0' has no effect
+                CH12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 13 enable clear register. Writing '0' has no effect
+                CH13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 14 enable clear register. Writing '0' has no effect
+                CH14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 15 enable clear register. Writing '0' has no effect
+                CH15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 16 enable clear register. Writing '0' has no effect
+                CH16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 17 enable clear register. Writing '0' has no effect
+                CH17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 18 enable clear register. Writing '0' has no effect
+                CH18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 19 enable clear register. Writing '0' has no effect
+                CH19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 20 enable clear register. Writing '0' has no effect
+                CH20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 21 enable clear register. Writing '0' has no effect
+                CH21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 22 enable clear register. Writing '0' has no effect
+                CH22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 23 enable clear register. Writing '0' has no effect
+                CH23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 24 enable clear register. Writing '0' has no effect
+                CH24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 25 enable clear register. Writing '0' has no effect
+                CH25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 26 enable clear register. Writing '0' has no effect
+                CH26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 27 enable clear register. Writing '0' has no effect
+                CH27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 28 enable clear register. Writing '0' has no effect
+                CH28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 29 enable clear register. Writing '0' has no effect
+                CH29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 30 enable clear register. Writing '0' has no effect
+                CH30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 31 enable clear register. Writing '0' has no effect
+                CH31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            reserved2048: [756]u8,
+            ///  Description collection[0]: Channel group 0
+            CHG: [6]mmio.Mmio(packed struct(u32) {
+                ///  Include or exclude channel 0
+                CH0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 1
+                CH1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 2
+                CH2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 3
+                CH3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 4
+                CH4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 5
+                CH5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 6
+                CH6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 7
+                CH7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 8
+                CH8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 9
+                CH9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 10
+                CH10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 11
+                CH11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 12
+                CH12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 13
+                CH13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 14
+                CH14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 15
+                CH15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 16
+                CH16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 17
+                CH17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 18
+                CH18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 19
+                CH19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 20
+                CH20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 21
+                CH21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 22
+                CH22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 23
+                CH23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 24
+                CH24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 25
+                CH25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 26
+                CH26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 27
+                CH27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 28
+                CH28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 29
+                CH29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 30
+                CH30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 31
+                CH31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+            }),
+        };
+
+        ///  NFC-A compatible radio
+        pub const NFCT = extern struct {
+            ///  Activate NFC peripheral for incoming and outgoing frames, change state to activated
+            TASKS_ACTIVATE: u32,
+            ///  Disable NFC peripheral
+            TASKS_DISABLE: u32,
+            ///  Enable NFC sense field mode, change state to sense mode
+            TASKS_SENSE: u32,
+            ///  Start transmission of a outgoing frame, change state to transmit
+            TASKS_STARTTX: u32,
+            reserved28: [12]u8,
+            ///  Initializes the EasyDMA for receive.
+            TASKS_ENABLERXDATA: u32,
+            reserved36: [4]u8,
+            ///  Force state machine to IDLE state
+            TASKS_GOIDLE: u32,
+            ///  Force state machine to SLEEP_A state
+            TASKS_GOSLEEP: u32,
+            reserved256: [212]u8,
+            ///  The NFC peripheral is ready to receive and send frames
+            EVENTS_READY: u32,
+            ///  Remote NFC field detected
+            EVENTS_FIELDDETECTED: u32,
+            ///  Remote NFC field lost
+            EVENTS_FIELDLOST: u32,
+            ///  Marks the start of the first symbol of a transmitted frame
+            EVENTS_TXFRAMESTART: u32,
+            ///  Marks the end of the last transmitted on-air symbol of a frame
+            EVENTS_TXFRAMEEND: u32,
+            ///  Marks the end of the first symbol of a received frame
+            EVENTS_RXFRAMESTART: u32,
+            ///  Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer
+            EVENTS_RXFRAMEEND: u32,
+            ///  NFC error reported. The ERRORSTATUS register contains details on the source of the error.
+            EVENTS_ERROR: u32,
+            reserved296: [8]u8,
+            ///  NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.
+            EVENTS_RXERROR: u32,
+            ///  RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.
+            EVENTS_ENDRX: u32,
+            ///  Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer
+            EVENTS_ENDTX: u32,
+            reserved312: [4]u8,
+            ///  Auto collision resolution process has started
+            EVENTS_AUTOCOLRESSTARTED: u32,
+            reserved328: [12]u8,
+            ///  NFC Auto collision resolution error reported.
+            EVENTS_COLLISION: u32,
+            ///  NFC Auto collision resolution successfully completed
+            EVENTS_SELECTED: u32,
+            ///  EasyDMA is ready to receive or send frames.
+            EVENTS_STARTED: u32,
+            reserved512: [172]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between FIELDDETECTED event and ACTIVATE task
+                FIELDDETECTED_ACTIVATE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between FIELDLOST event and SENSE task
+                FIELDLOST_SENSE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for FIELDDETECTED event
+                FIELDDETECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for FIELDLOST event
+                FIELDLOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TXFRAMESTART event
+                TXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for TXFRAMEEND event
+                TXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for RXFRAMESTART event
+                RXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for RXFRAMEEND event
+                RXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u2,
+                ///  Enable or disable interrupt for RXERROR event
+                RXERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for ENDRX event
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for ENDTX event
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved14: u1,
+                ///  Enable or disable interrupt for AUTOCOLRESSTARTED event
+                AUTOCOLRESSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u3,
+                ///  Enable or disable interrupt for COLLISION event
+                COLLISION: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for SELECTED event
+                SELECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for STARTED event
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u11,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for FIELDDETECTED event
+                FIELDDETECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for FIELDLOST event
+                FIELDLOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TXFRAMESTART event
+                TXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for TXFRAMEEND event
+                TXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for RXFRAMESTART event
+                RXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for RXFRAMEEND event
+                RXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u2,
+                ///  Write '1' to Enable interrupt for RXERROR event
+                RXERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for ENDRX event
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for ENDTX event
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved14: u1,
+                ///  Write '1' to Enable interrupt for AUTOCOLRESSTARTED event
+                AUTOCOLRESSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u3,
+                ///  Write '1' to Enable interrupt for COLLISION event
+                COLLISION: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for SELECTED event
+                SELECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for STARTED event
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u11,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for FIELDDETECTED event
+                FIELDDETECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for FIELDLOST event
+                FIELDLOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TXFRAMESTART event
+                TXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for TXFRAMEEND event
+                TXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for RXFRAMESTART event
+                RXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for RXFRAMEEND event
+                RXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u2,
+                ///  Write '1' to Disable interrupt for RXERROR event
+                RXERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for ENDRX event
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for ENDTX event
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved14: u1,
+                ///  Write '1' to Disable interrupt for AUTOCOLRESSTARTED event
+                AUTOCOLRESSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u3,
+                ///  Write '1' to Disable interrupt for COLLISION event
+                COLLISION: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for SELECTED event
+                SELECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for STARTED event
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u11,
+            }),
+            reserved1028: [248]u8,
+            ///  NFC Error Status register
+            ERRORSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX
+                FRAMEDELAYTIMEOUT: u1,
+                reserved2: u1,
+                ///  Field level is too high at max load resistance
+                NFCFIELDTOOSTRONG: u1,
+                ///  Field level is too low at min load resistance
+                NFCFIELDTOOWEAK: u1,
+                padding: u28,
+            }),
+            reserved1072: [40]u8,
+            ///  Current value driven to the NFC Load Control
+            CURRENTLOADCTRL: mmio.Mmio(packed struct(u32) {
+                ///  Current value driven to the NFC Load Control
+                CURRENTLOADCTRL: u6,
+                padding: u26,
+            }),
+            reserved1084: [8]u8,
+            ///  Indicates the presence or not of a valid field
+            FIELDPRESENT: mmio.Mmio(packed struct(u32) {
+                ///  Indicates the presence or not of a valid field. Available only in the activated state.
+                FIELDPRESENT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No valid field detected
+                        NoField = 0x0,
+                        ///  Valid field detected
+                        FieldPresent = 0x1,
+                    },
+                },
+                ///  Indicates if the low level has locked to the field
+                LOCKDETECT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not locked to field
+                        NotLocked = 0x0,
+                        ///  Locked to field
+                        Locked = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1284: [196]u8,
+            ///  Minimum frame delay
+            FRAMEDELAYMIN: mmio.Mmio(packed struct(u32) {
+                ///  Minimum frame delay in number of 13.56 MHz clocks
+                FRAMEDELAYMIN: u16,
+                padding: u16,
+            }),
+            ///  Maximum frame delay
+            FRAMEDELAYMAX: mmio.Mmio(packed struct(u32) {
+                ///  Maximum frame delay in number of 13.56 MHz clocks
+                FRAMEDELAYMAX: u16,
+                padding: u16,
+            }),
+            ///  Configuration register for the Frame Delay Timer
+            FRAMEDELAYMODE: mmio.Mmio(packed struct(u32) {
+                ///  Configuration register for the Frame Delay Timer
+                FRAMEDELAYMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout.
+                        FreeRun = 0x0,
+                        ///  Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX
+                        Window = 0x1,
+                        ///  Frame is transmitted exactly at FRAMEDELAYMAX
+                        ExactVal = 0x2,
+                        ///  Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX
+                        WindowGrid = 0x3,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Packet pointer for TXD and RXD data storage in Data RAM
+            PACKETPTR: mmio.Mmio(packed struct(u32) {
+                ///  Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address.
+                PTR: u32,
+            }),
+            ///  Size of allocated for TXD and RXD data storage buffer in Data RAM
+            MAXLEN: mmio.Mmio(packed struct(u32) {
+                ///  Size of allocated for TXD and RXD data storage buffer in Data RAM
+                MAXLEN: u9,
+                padding: u23,
+            }),
+            reserved1424: [120]u8,
+            ///  Last NFCID1 part (4, 7 or 10 bytes ID)
+            NFCID1_LAST: mmio.Mmio(packed struct(u32) {
+                ///  NFCID1 byte Z (very last byte sent)
+                NFCID1_Z: u8,
+                ///  NFCID1 byte Y
+                NFCID1_Y: u8,
+                ///  NFCID1 byte X
+                NFCID1_X: u8,
+                ///  NFCID1 byte W
+                NFCID1_W: u8,
+            }),
+            ///  Second last NFCID1 part (7 or 10 bytes ID)
+            NFCID1_2ND_LAST: mmio.Mmio(packed struct(u32) {
+                ///  NFCID1 byte V
+                NFCID1_V: u8,
+                ///  NFCID1 byte U
+                NFCID1_U: u8,
+                ///  NFCID1 byte T
+                NFCID1_T: u8,
+                padding: u8,
+            }),
+            ///  Third last NFCID1 part (10 bytes ID)
+            NFCID1_3RD_LAST: mmio.Mmio(packed struct(u32) {
+                ///  NFCID1 byte S
+                NFCID1_S: u8,
+                ///  NFCID1 byte R
+                NFCID1_R: u8,
+                ///  NFCID1 byte Q
+                NFCID1_Q: u8,
+                padding: u8,
+            }),
+            reserved1440: [4]u8,
+            ///  NFC-A SENS_RES auto-response settings
+            SENSRES: mmio.Mmio(packed struct(u32) {
+                ///  Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
+                BITFRAMESDD: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        ///  SDD pattern 00000
+                        SDD00000 = 0x0,
+                        ///  SDD pattern 00001
+                        SDD00001 = 0x1,
+                        ///  SDD pattern 00010
+                        SDD00010 = 0x2,
+                        ///  SDD pattern 00100
+                        SDD00100 = 0x4,
+                        ///  SDD pattern 01000
+                        SDD01000 = 0x8,
+                        ///  SDD pattern 10000
+                        SDD10000 = 0x10,
+                        _,
+                    },
+                },
+                ///  Reserved for future use. Shall be 0.
+                RFU5: u1,
+                ///  NFCID1 size. This value is used by the Auto collision resolution engine.
+                NFCIDSIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  NFCID1 size: single (4 bytes)
+                        NFCID1Single = 0x0,
+                        ///  NFCID1 size: double (7 bytes)
+                        NFCID1Double = 0x1,
+                        ///  NFCID1 size: triple (10 bytes)
+                        NFCID1Triple = 0x2,
+                        _,
+                    },
+                },
+                ///  Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
+                PLATFCONFIG: u4,
+                ///  Reserved for future use. Shall be 0.
+                RFU74: u4,
+                padding: u16,
+            }),
+            ///  NFC-A SEL_RES auto-response settings
+            SELRES: mmio.Mmio(packed struct(u32) {
+                ///  Reserved for future use. Shall be 0.
+                RFU10: u2,
+                ///  Cascade bit (controlled by hardware, write has no effect)
+                CASCADE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  NFCID1 complete
+                        Complete = 0x0,
+                        ///  NFCID1 not complete
+                        NotComplete = 0x1,
+                    },
+                },
+                ///  Reserved for future use. Shall be 0.
+                RFU43: u2,
+                ///  Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
+                PROTOCOL: u2,
+                ///  Reserved for future use. Shall be 0.
+                RFU7: u1,
+                padding: u24,
+            }),
+        };
+
+        ///  GPIO Tasks and Events
+        pub const GPIOTE = extern struct {
+            ///  Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY.
+            TASKS_OUT: [8]u32,
+            reserved48: [16]u8,
+            ///  Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high.
+            TASKS_SET: [8]u32,
+            reserved96: [16]u8,
+            ///  Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low.
+            TASKS_CLR: [8]u32,
+            reserved256: [128]u8,
+            ///  Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL
+            EVENTS_IN: [8]u32,
+            reserved380: [92]u8,
+            ///  Event generated from multiple input GPIO pins with SENSE mechanism enabled
+            EVENTS_PORT: u32,
+            reserved772: [388]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for IN[0] event
+                IN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for IN[1] event
+                IN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for IN[2] event
+                IN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for IN[3] event
+                IN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for IN[4] event
+                IN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for IN[5] event
+                IN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for IN[6] event
+                IN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for IN[7] event
+                IN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved31: u23,
+                ///  Write '1' to Enable interrupt for PORT event
+                PORT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for IN[0] event
+                IN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for IN[1] event
+                IN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for IN[2] event
+                IN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for IN[3] event
+                IN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for IN[4] event
+                IN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for IN[5] event
+                IN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for IN[6] event
+                IN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for IN[7] event
+                IN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved31: u23,
+                ///  Write '1' to Disable interrupt for PORT event
+                PORT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            reserved1296: [516]u8,
+            ///  Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
+            CONFIG: [8]mmio.Mmio(packed struct(u32) {
+                ///  Mode
+                MODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.
+                        Disabled = 0x0,
+                        ///  Event mode
+                        Event = 0x1,
+                        ///  Task mode
+                        Task = 0x3,
+                        _,
+                    },
+                },
+                reserved8: u6,
+                ///  GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event
+                PSEL: u5,
+                reserved16: u3,
+                ///  When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
+                POLARITY: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.
+                        None = 0x0,
+                        ///  Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.
+                        LoToHi = 0x1,
+                        ///  Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.
+                        HiToLo = 0x2,
+                        ///  Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.
+                        Toggle = 0x3,
+                    },
+                },
+                reserved20: u2,
+                ///  When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
+                OUTINIT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Task mode: Initial value of pin before task triggering is low
+                        Low = 0x0,
+                        ///  Task mode: Initial value of pin before task triggering is high
+                        High = 0x1,
+                    },
+                },
+                padding: u11,
+            }),
+        };
+
+        ///  Analog to Digital Converter
+        pub const SAADC = extern struct {
+            ///  Start the ADC and prepare the result buffer in RAM
+            TASKS_START: u32,
+            ///  Take one ADC sample, if scan is enabled all channels are sampled
+            TASKS_SAMPLE: u32,
+            ///  Stop the ADC and terminate any on-going conversion
+            TASKS_STOP: u32,
+            ///  Starts offset auto-calibration
+            TASKS_CALIBRATEOFFSET: u32,
+            reserved256: [240]u8,
+            ///  The ADC has started
+            EVENTS_STARTED: u32,
+            ///  The ADC has filled up the Result buffer
+            EVENTS_END: u32,
+            ///  A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.
+            EVENTS_DONE: u32,
+            ///  A result is ready to get transferred to RAM.
+            EVENTS_RESULTDONE: u32,
+            ///  Calibration is complete
+            EVENTS_CALIBRATEDONE: u32,
+            ///  The ADC has stopped
+            EVENTS_STOPPED: u32,
+            reserved768: [488]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for STARTED event
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for DONE event
+                DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for RESULTDONE event
+                RESULTDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CALIBRATEDONE event
+                CALIBRATEDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[0].LIMITH event
+                CH0LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[0].LIMITL event
+                CH0LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[1].LIMITH event
+                CH1LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[1].LIMITL event
+                CH1LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[2].LIMITH event
+                CH2LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[2].LIMITL event
+                CH2LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[3].LIMITH event
+                CH3LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[3].LIMITL event
+                CH3LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[4].LIMITH event
+                CH4LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[4].LIMITL event
+                CH4LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[5].LIMITH event
+                CH5LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[5].LIMITL event
+                CH5LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[6].LIMITH event
+                CH6LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[6].LIMITL event
+                CH6LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[7].LIMITH event
+                CH7LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CH[7].LIMITL event
+                CH7LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u10,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for STARTED event
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for DONE event
+                DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for RESULTDONE event
+                RESULTDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CALIBRATEDONE event
+                CALIBRATEDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[0].LIMITH event
+                CH0LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[0].LIMITL event
+                CH0LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[1].LIMITH event
+                CH1LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[1].LIMITL event
+                CH1LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[2].LIMITH event
+                CH2LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[2].LIMITL event
+                CH2LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[3].LIMITH event
+                CH3LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[3].LIMITL event
+                CH3LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[4].LIMITH event
+                CH4LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[4].LIMITL event
+                CH4LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[5].LIMITH event
+                CH5LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[5].LIMITL event
+                CH5LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[6].LIMITH event
+                CH6LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[6].LIMITL event
+                CH6LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[7].LIMITH event
+                CH7LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CH[7].LIMITL event
+                CH7LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u10,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for STARTED event
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for DONE event
+                DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for RESULTDONE event
+                RESULTDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CALIBRATEDONE event
+                CALIBRATEDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[0].LIMITH event
+                CH0LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[0].LIMITL event
+                CH0LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[1].LIMITH event
+                CH1LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[1].LIMITL event
+                CH1LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[2].LIMITH event
+                CH2LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[2].LIMITL event
+                CH2LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[3].LIMITH event
+                CH3LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[3].LIMITL event
+                CH3LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[4].LIMITH event
+                CH4LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[4].LIMITL event
+                CH4LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[5].LIMITH event
+                CH5LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[5].LIMITL event
+                CH5LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[6].LIMITH event
+                CH6LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[6].LIMITL event
+                CH6LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[7].LIMITH event
+                CH7LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CH[7].LIMITL event
+                CH7LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u10,
+            }),
+            reserved1024: [244]u8,
+            ///  Status
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  Status
+                STATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  ADC is ready. No on-going conversion.
+                        Ready = 0x0,
+                        ///  ADC is busy. Conversion in progress.
+                        Busy = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1280: [252]u8,
+            ///  Enable or disable ADC
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable ADC
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable ADC
+                        Disabled = 0x0,
+                        ///  Enable ADC
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1520: [236]u8,
+            ///  Resolution configuration
+            RESOLUTION: mmio.Mmio(packed struct(u32) {
+                ///  Set the resolution
+                VAL: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  8 bit
+                        @"8bit" = 0x0,
+                        ///  10 bit
+                        @"10bit" = 0x1,
+                        ///  12 bit
+                        @"12bit" = 0x2,
+                        ///  14 bit
+                        @"14bit" = 0x3,
+                        _,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.
+            OVERSAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  Oversample control
+                OVERSAMPLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Bypass oversampling
+                        Bypass = 0x0,
+                        ///  Oversample 2x
+                        Over2x = 0x1,
+                        ///  Oversample 4x
+                        Over4x = 0x2,
+                        ///  Oversample 8x
+                        Over8x = 0x3,
+                        ///  Oversample 16x
+                        Over16x = 0x4,
+                        ///  Oversample 32x
+                        Over32x = 0x5,
+                        ///  Oversample 64x
+                        Over64x = 0x6,
+                        ///  Oversample 128x
+                        Over128x = 0x7,
+                        ///  Oversample 256x
+                        Over256x = 0x8,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Controls normal or continuous sample rate
+            SAMPLERATE: mmio.Mmio(packed struct(u32) {
+                ///  Capture and compare value. Sample rate is 16 MHz/CC
+                CC: u11,
+                reserved12: u1,
+                ///  Select mode for sample rate control
+                MODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Rate is controlled from SAMPLE task
+                        Task = 0x0,
+                        ///  Rate is controlled from local timer (use CC to control the rate)
+                        Timers = 0x1,
+                    },
+                },
+                padding: u19,
+            }),
+        };
+
+        ///  Timer/Counter 0
+        pub const TIMER0 = extern struct {
+            ///  Start Timer
+            TASKS_START: u32,
+            ///  Stop Timer
+            TASKS_STOP: u32,
+            ///  Increment Timer (Counter mode only)
+            TASKS_COUNT: u32,
+            ///  Clear time
+            TASKS_CLEAR: u32,
+            ///  Deprecated register - Shut down timer
+            TASKS_SHUTDOWN: u32,
+            reserved64: [44]u8,
+            ///  Description collection[0]: Capture Timer value to CC[0] register
+            TASKS_CAPTURE: [6]u32,
+            reserved320: [232]u8,
+            ///  Description collection[0]: Compare event on CC[0] match
+            EVENTS_COMPARE: [6]u32,
+            reserved512: [168]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between COMPARE[0] event and CLEAR task
+                COMPARE0_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between COMPARE[1] event and CLEAR task
+                COMPARE1_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between COMPARE[2] event and CLEAR task
+                COMPARE2_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between COMPARE[3] event and CLEAR task
+                COMPARE3_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between COMPARE[4] event and CLEAR task
+                COMPARE4_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between COMPARE[5] event and CLEAR task
+                COMPARE5_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                reserved8: u2,
+                ///  Shortcut between COMPARE[0] event and STOP task
+                COMPARE0_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between COMPARE[1] event and STOP task
+                COMPARE1_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between COMPARE[2] event and STOP task
+                COMPARE2_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between COMPARE[3] event and STOP task
+                COMPARE3_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between COMPARE[4] event and STOP task
+                COMPARE4_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between COMPARE[5] event and STOP task
+                COMPARE5_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u18,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  Write '1' to Enable interrupt for COMPARE[0] event
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for COMPARE[1] event
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for COMPARE[2] event
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for COMPARE[3] event
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for COMPARE[4] event
+                COMPARE4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for COMPARE[5] event
+                COMPARE5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u10,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  Write '1' to Disable interrupt for COMPARE[0] event
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for COMPARE[1] event
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for COMPARE[2] event
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for COMPARE[3] event
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for COMPARE[4] event
+                COMPARE4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for COMPARE[5] event
+                COMPARE5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u10,
+            }),
+            reserved1284: [504]u8,
+            ///  Timer mode selection
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Timer mode
+                MODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Select Timer mode
+                        Timer = 0x0,
+                        ///  Deprecated enumerator - Select Counter mode
+                        Counter = 0x1,
+                        ///  Select Low Power Counter mode
+                        LowPowerCounter = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Configure the number of bits used by the TIMER
+            BITMODE: mmio.Mmio(packed struct(u32) {
+                ///  Timer bit width
+                BITMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  16 bit timer bit width
+                        @"16Bit" = 0x0,
+                        ///  8 bit timer bit width
+                        @"08Bit" = 0x1,
+                        ///  24 bit timer bit width
+                        @"24Bit" = 0x2,
+                        ///  32 bit timer bit width
+                        @"32Bit" = 0x3,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1296: [4]u8,
+            ///  Timer prescaler register
+            PRESCALER: mmio.Mmio(packed struct(u32) {
+                ///  Prescaler value
+                PRESCALER: u4,
+                padding: u28,
+            }),
+            reserved1344: [44]u8,
+            ///  Description collection[0]: Capture/Compare register 0
+            CC: [6]mmio.Mmio(packed struct(u32) {
+                ///  Capture/Compare value
+                CC: u32,
+            }),
+        };
+
+        ///  Non Volatile Memory Controller
+        pub const NVMC = extern struct {
+            reserved1024: [1024]u8,
+            ///  Ready flag
+            READY: mmio.Mmio(packed struct(u32) {
+                ///  NVMC is ready or busy
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  NVMC is busy (on-going write or erase operation)
+                        Busy = 0x0,
+                        ///  NVMC is ready
+                        Ready = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1284: [256]u8,
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.
+                WEN: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Read only access
+                        Ren = 0x0,
+                        ///  Write Enabled
+                        Wen = 0x1,
+                        ///  Erase enabled
+                        Een = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Register for erasing a page in Code area
+            ERASEPAGE: mmio.Mmio(packed struct(u32) {
+                ///  Register for starting erase of a page in Code area
+                ERASEPAGE: u32,
+            }),
+            ///  Register for erasing all non-volatile user memory
+            ERASEALL: mmio.Mmio(packed struct(u32) {
+                ///  Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.
+                ERASEALL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No operation
+                        NoOperation = 0x0,
+                        ///  Start chip erase
+                        Erase = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE.
+            ERASEPCR0: mmio.Mmio(packed struct(u32) {
+                ///  Register for starting erase of a page in Code area. Equivalent to ERASEPAGE.
+                ERASEPCR0: u32,
+            }),
+            ///  Register for erasing User Information Configuration Registers
+            ERASEUICR: mmio.Mmio(packed struct(u32) {
+                ///  Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.
+                ERASEUICR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No operation
+                        NoOperation = 0x0,
+                        ///  Start erase of UICR
+                        Erase = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1344: [40]u8,
+            ///  I-Code cache configuration register.
+            ICACHECNF: mmio.Mmio(packed struct(u32) {
+                ///  Cache enable
+                CACHEEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable cache. Invalidates all cache entries.
+                        Disabled = 0x0,
+                        ///  Enable cache
+                        Enabled = 0x1,
+                    },
+                },
+                reserved8: u7,
+                ///  Cache profiling enable
+                CACHEPROFEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable cache profiling
+                        Disabled = 0x0,
+                        ///  Enable cache profiling
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            reserved1352: [4]u8,
+            ///  I-Code cache hit counter.
+            IHIT: mmio.Mmio(packed struct(u32) {
+                ///  Number of cache hits
+                HITS: u32,
+            }),
+            ///  I-Code cache miss counter.
+            IMISS: mmio.Mmio(packed struct(u32) {
+                ///  Number of cache misses
+                MISSES: u32,
+            }),
+        };
+
+        ///  Pulse Density Modulation (Digital Microphone) Interface
+        pub const PDM = extern struct {
+            ///  Starts continuous PDM transfer
+            TASKS_START: u32,
+            ///  Stops PDM transfer
+            TASKS_STOP: u32,
+            reserved256: [248]u8,
+            ///  PDM transfer has started
+            EVENTS_STARTED: u32,
+            ///  PDM transfer has finished
+            EVENTS_STOPPED: u32,
+            ///  The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM
+            EVENTS_END: u32,
+            reserved768: [500]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for STARTED event
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for STARTED event
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for STARTED event
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1280: [500]u8,
+            ///  PDM module enable register
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable PDM module
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  PDM clock generator control
+            PDMCLKCTRL: mmio.Mmio(packed struct(u32) {
+                ///  PDM_CLK frequency
+                FREQ: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  PDM_CLK = 32 MHz / 32 = 1.000 MHz
+                        @"1000K" = 0x8000000,
+                        ///  PDM_CLK = 32 MHz / 31 = 1.032 MHz
+                        Default = 0x8400000,
+                        ///  PDM_CLK = 32 MHz / 30 = 1.067 MHz
+                        @"1067K" = 0x8800000,
+                        _,
+                    },
+                },
+            }),
+            ///  Defines the routing of the connected PDM microphones' signals
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Mono or stereo operation
+                OPERATION: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]
+                        Stereo = 0x0,
+                        ///  Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]
+                        Mono = 0x1,
+                    },
+                },
+                ///  Defines on which PDM_CLK edge Left (or mono) is sampled
+                EDGE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Left (or mono) is sampled on falling edge of PDM_CLK
+                        LeftFalling = 0x0,
+                        ///  Left (or mono) is sampled on rising edge of PDM_CLK
+                        LeftRising = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1304: [12]u8,
+            ///  Left output gain adjustment
+            GAINL: mmio.Mmio(packed struct(u32) {
+                ///  Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust
+                GAINL: packed union {
+                    raw: u7,
+                    value: enum(u7) {
+                        ///  -20dB gain adjustment (minimum)
+                        MinGain = 0x0,
+                        ///  0dB gain adjustment ('2500 RMS' requirement)
+                        DefaultGain = 0x28,
+                        ///  +20dB gain adjustment (maximum)
+                        MaxGain = 0x50,
+                        _,
+                    },
+                },
+                padding: u25,
+            }),
+            ///  Right output gain adjustment
+            GAINR: mmio.Mmio(packed struct(u32) {
+                ///  Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)
+                GAINR: packed union {
+                    raw: u8,
+                    value: enum(u8) {
+                        ///  -20dB gain adjustment (minimum)
+                        MinGain = 0x0,
+                        ///  0dB gain adjustment ('2500 RMS' requirement)
+                        DefaultGain = 0x28,
+                        ///  +20dB gain adjustment (maximum)
+                        MaxGain = 0x50,
+                        _,
+                    },
+                },
+                padding: u24,
+            }),
+        };
+
+        ///  Real time counter 0
+        pub const RTC0 = extern struct {
+            ///  Start RTC COUNTER
+            TASKS_START: u32,
+            ///  Stop RTC COUNTER
+            TASKS_STOP: u32,
+            ///  Clear RTC COUNTER
+            TASKS_CLEAR: u32,
+            ///  Set COUNTER to 0xFFFFF0
+            TASKS_TRIGOVRFLW: u32,
+            reserved256: [240]u8,
+            ///  Event on COUNTER increment
+            EVENTS_TICK: u32,
+            ///  Event on COUNTER overflow
+            EVENTS_OVRFLW: u32,
+            reserved320: [56]u8,
+            ///  Description collection[0]: Compare event on CC[0] match
+            EVENTS_COMPARE: [4]u32,
+            reserved772: [436]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for TICK event
+                TICK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for OVRFLW event
+                OVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Write '1' to Enable interrupt for COMPARE[0] event
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for COMPARE[1] event
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for COMPARE[2] event
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for COMPARE[3] event
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for TICK event
+                TICK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for OVRFLW event
+                OVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Write '1' to Disable interrupt for COMPARE[0] event
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for COMPARE[1] event
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for COMPARE[2] event
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for COMPARE[3] event
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            reserved832: [52]u8,
+            ///  Enable or disable event routing
+            EVTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable event routing for TICK event
+                TICK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable event routing for OVRFLW event
+                OVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Enable or disable event routing for COMPARE[0] event
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable event routing for COMPARE[1] event
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable event routing for COMPARE[2] event
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable event routing for COMPARE[3] event
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            ///  Enable event routing
+            EVTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable event routing for TICK event
+                TICK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable event routing for OVRFLW event
+                OVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Write '1' to Enable event routing for COMPARE[0] event
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable event routing for COMPARE[1] event
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable event routing for COMPARE[2] event
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable event routing for COMPARE[3] event
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            ///  Disable event routing
+            EVTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable event routing for TICK event
+                TICK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable event routing for OVRFLW event
+                OVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Write '1' to Disable event routing for COMPARE[0] event
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable event routing for COMPARE[1] event
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable event routing for COMPARE[2] event
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable event routing for COMPARE[3] event
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            reserved1284: [440]u8,
+            ///  Current COUNTER value
+            COUNTER: mmio.Mmio(packed struct(u32) {
+                ///  Counter value
+                COUNTER: u24,
+                padding: u8,
+            }),
+            ///  12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped
+            PRESCALER: mmio.Mmio(packed struct(u32) {
+                ///  Prescaler value
+                PRESCALER: u12,
+                padding: u20,
+            }),
+            reserved1344: [52]u8,
+            ///  Description collection[0]: Compare register 0
+            CC: [4]mmio.Mmio(packed struct(u32) {
+                ///  Compare value
+                COMPARE: u24,
+                padding: u8,
+            }),
+        };
+
+        ///  Temperature Sensor
+        pub const TEMP = extern struct {
+            ///  Start temperature measurement
+            TASKS_START: u32,
+            ///  Stop temperature measurement
+            TASKS_STOP: u32,
+            reserved256: [248]u8,
+            ///  Temperature measurement complete, data ready
+            EVENTS_DATARDY: u32,
+            reserved772: [512]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for DATARDY event
+                DATARDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for DATARDY event
+                DATARDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1288: [508]u8,
+            ///  Temperature in degC (0.25deg steps)
+            TEMP: mmio.Mmio(packed struct(u32) {
+                ///  Temperature in degC (0.25deg steps)
+                TEMP: u32,
+            }),
+            reserved1312: [20]u8,
+            ///  Slope of 1st piece wise linear function
+            A0: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 1st piece wise linear function
+                A0: u12,
+                padding: u20,
+            }),
+            ///  Slope of 2nd piece wise linear function
+            A1: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 2nd piece wise linear function
+                A1: u12,
+                padding: u20,
+            }),
+            ///  Slope of 3rd piece wise linear function
+            A2: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 3rd piece wise linear function
+                A2: u12,
+                padding: u20,
+            }),
+            ///  Slope of 4th piece wise linear function
+            A3: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 4th piece wise linear function
+                A3: u12,
+                padding: u20,
+            }),
+            ///  Slope of 5th piece wise linear function
+            A4: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 5th piece wise linear function
+                A4: u12,
+                padding: u20,
+            }),
+            ///  Slope of 6th piece wise linear function
+            A5: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 6th piece wise linear function
+                A5: u12,
+                padding: u20,
+            }),
+            reserved1344: [8]u8,
+            ///  y-intercept of 1st piece wise linear function
+            B0: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 1st piece wise linear function
+                B0: u14,
+                padding: u18,
+            }),
+            ///  y-intercept of 2nd piece wise linear function
+            B1: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 2nd piece wise linear function
+                B1: u14,
+                padding: u18,
+            }),
+            ///  y-intercept of 3rd piece wise linear function
+            B2: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 3rd piece wise linear function
+                B2: u14,
+                padding: u18,
+            }),
+            ///  y-intercept of 4th piece wise linear function
+            B3: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 4th piece wise linear function
+                B3: u14,
+                padding: u18,
+            }),
+            ///  y-intercept of 5th piece wise linear function
+            B4: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 5th piece wise linear function
+                B4: u14,
+                padding: u18,
+            }),
+            ///  y-intercept of 6th piece wise linear function
+            B5: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 6th piece wise linear function
+                B5: u14,
+                padding: u18,
+            }),
+            reserved1376: [8]u8,
+            ///  End point of 1st piece wise linear function
+            T0: mmio.Mmio(packed struct(u32) {
+                ///  End point of 1st piece wise linear function
+                T0: u8,
+                padding: u24,
+            }),
+            ///  End point of 2nd piece wise linear function
+            T1: mmio.Mmio(packed struct(u32) {
+                ///  End point of 2nd piece wise linear function
+                T1: u8,
+                padding: u24,
+            }),
+            ///  End point of 3rd piece wise linear function
+            T2: mmio.Mmio(packed struct(u32) {
+                ///  End point of 3rd piece wise linear function
+                T2: u8,
+                padding: u24,
+            }),
+            ///  End point of 4th piece wise linear function
+            T3: mmio.Mmio(packed struct(u32) {
+                ///  End point of 4th piece wise linear function
+                T3: u8,
+                padding: u24,
+            }),
+            ///  End point of 5th piece wise linear function
+            T4: mmio.Mmio(packed struct(u32) {
+                ///  End point of 5th piece wise linear function
+                T4: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  Random Number Generator
+        pub const RNG = extern struct {
+            ///  Task starting the random number generator
+            TASKS_START: u32,
+            ///  Task stopping the random number generator
+            TASKS_STOP: u32,
+            reserved256: [248]u8,
+            ///  Event being generated for every new random number written to the VALUE register
+            EVENTS_VALRDY: u32,
+            reserved512: [252]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between VALRDY event and STOP task
+                VALRDY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for VALRDY event
+                VALRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for VALRDY event
+                VALRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1284: [504]u8,
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Bias correction
+                DERCEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Output random number
+            VALUE: mmio.Mmio(packed struct(u32) {
+                ///  Generated random number
+                VALUE: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  AES ECB Mode Encryption
+        pub const ECB = extern struct {
+            ///  Start ECB block encrypt
+            TASKS_STARTECB: u32,
+            ///  Abort a possible executing ECB operation
+            TASKS_STOPECB: u32,
+            reserved256: [248]u8,
+            ///  ECB block encrypt complete
+            EVENTS_ENDECB: u32,
+            ///  ECB block encrypt aborted because of a STOPECB task or due to an error
+            EVENTS_ERRORECB: u32,
+            reserved772: [508]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for ENDECB event
+                ENDECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for ERRORECB event
+                ERRORECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for ENDECB event
+                ENDECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for ERRORECB event
+                ERRORECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1284: [504]u8,
+            ///  ECB block encrypt memory pointers
+            ECBDATAPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to the ECB data structure (see Table 1 ECB data structure overview)
+                ECBDATAPTR: u32,
+            }),
+        };
+
+        ///  AES CCM Mode Encryption
+        pub const CCM = extern struct {
+            ///  Start generation of key-stream. This operation will stop by itself when completed.
+            TASKS_KSGEN: u32,
+            ///  Start encryption/decryption. This operation will stop by itself when completed.
+            TASKS_CRYPT: u32,
+            ///  Stop encryption/decryption
+            TASKS_STOP: u32,
+            reserved256: [244]u8,
+            ///  Key-stream generation complete
+            EVENTS_ENDKSGEN: u32,
+            ///  Encrypt/decrypt complete
+            EVENTS_ENDCRYPT: u32,
+            ///  CCM error event
+            EVENTS_ERROR: u32,
+            reserved512: [244]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between ENDKSGEN event and CRYPT task
+                ENDKSGEN_CRYPT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for ENDKSGEN event
+                ENDKSGEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for ENDCRYPT event
+                ENDCRYPT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for ENDKSGEN event
+                ENDKSGEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for ENDCRYPT event
+                ENDCRYPT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for ERROR event
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1024: [244]u8,
+            ///  MIC check result
+            MICSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  The result of the MIC check performed during the previous decryption operation
+                MICSTATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  MIC check failed
+                        CheckFailed = 0x0,
+                        ///  MIC check passed
+                        CheckPassed = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1280: [252]u8,
+            ///  Enable
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable CCM
+                ENABLE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Operation mode
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  The mode of operation to be used
+                MODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  AES CCM packet encryption mode
+                        Encryption = 0x0,
+                        ///  AES CCM packet decryption mode
+                        Decryption = 0x1,
+                    },
+                },
+                reserved16: u15,
+                ///  Data rate that the CCM shall run in synch with
+                DATARATE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  In synch with 1 Mbit data rate
+                        @"1Mbit" = 0x0,
+                        ///  In synch with 2 Mbit data rate
+                        @"2Mbit" = 0x1,
+                    },
+                },
+                reserved24: u7,
+                ///  Packet length configuration
+                LENGTH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Default length. Effective length of LENGTH field is 5-bit
+                        Default = 0x0,
+                        ///  Extended length. Effective length of LENGTH field is 8-bit
+                        Extended = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            ///  Pointer to data structure holding AES key and NONCE vector
+            CNFPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)
+                CNFPTR: u32,
+            }),
+            ///  Input pointer
+            INPTR: mmio.Mmio(packed struct(u32) {
+                ///  Input pointer
+                INPTR: u32,
+            }),
+            ///  Output pointer
+            OUTPTR: mmio.Mmio(packed struct(u32) {
+                ///  Output pointer
+                OUTPTR: u32,
+            }),
+            ///  Pointer to data area used for temporary storage
+            SCRATCHPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.
+                SCRATCHPTR: u32,
+            }),
+        };
+
+        ///  Accelerated Address Resolver
+        pub const AAR = extern struct {
+            ///  Start resolving addresses based on IRKs specified in the IRK data structure
+            TASKS_START: u32,
+            reserved8: [4]u8,
+            ///  Stop resolving addresses
+            TASKS_STOP: u32,
+            reserved256: [244]u8,
+            ///  Address resolution procedure complete
+            EVENTS_END: u32,
+            ///  Address resolved
+            EVENTS_RESOLVED: u32,
+            ///  Address not resolved
+            EVENTS_NOTRESOLVED: u32,
+            reserved772: [504]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for RESOLVED event
+                RESOLVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for NOTRESOLVED event
+                NOTRESOLVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for END event
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for RESOLVED event
+                RESOLVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for NOTRESOLVED event
+                NOTRESOLVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1024: [244]u8,
+            ///  Resolution status
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  The IRK that was used last time an address was resolved
+                STATUS: u4,
+                padding: u28,
+            }),
+            reserved1280: [252]u8,
+            ///  Enable AAR
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable AAR
+                ENABLE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x3,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Number of IRKs
+            NIRK: mmio.Mmio(packed struct(u32) {
+                ///  Number of Identity root keys available in the IRK data structure
+                NIRK: u5,
+                padding: u27,
+            }),
+            ///  Pointer to IRK data structure
+            IRKPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to the IRK data structure
+                IRKPTR: u32,
+            }),
+            reserved1296: [4]u8,
+            ///  Pointer to the resolvable address
+            ADDRPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to the resolvable address (6-bytes)
+                ADDRPTR: u32,
+            }),
+            ///  Pointer to data area used for temporary storage
+            SCRATCHPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved.
+                SCRATCHPTR: u32,
+            }),
+        };
+
+        ///  Watchdog Timer
+        pub const WDT = extern struct {
+            ///  Start the watchdog
+            TASKS_START: u32,
+            reserved256: [252]u8,
+            ///  Watchdog timeout
+            EVENTS_TIMEOUT: u32,
+            reserved772: [512]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for TIMEOUT event
+                TIMEOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for TIMEOUT event
+                TIMEOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1024: [244]u8,
+            ///  Run status
+            RUNSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  Indicates whether or not the watchdog is running
+                RUNSTATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Watchdog not running
+                        NotRunning = 0x0,
+                        ///  Watchdog is running
+                        Running = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Request status
+            REQSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  Request status for RR[0] register
+                RR0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[0] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[0] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[1] register
+                RR1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[1] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[1] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[2] register
+                RR2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[2] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[2] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[3] register
+                RR3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[3] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[3] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[4] register
+                RR4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[4] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[4] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[5] register
+                RR5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[5] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[5] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[6] register
+                RR6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[6] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[6] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[7] register
+                RR7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[7] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[7] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            reserved1284: [252]u8,
+            ///  Counter reload value
+            CRV: mmio.Mmio(packed struct(u32) {
+                ///  Counter reload value in number of cycles of the 32.768 kHz clock
+                CRV: u32,
+            }),
+            ///  Enable register for reload request registers
+            RREN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable RR[0] register
+                RR0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[0] register
+                        Disabled = 0x0,
+                        ///  Enable RR[0] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[1] register
+                RR1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[1] register
+                        Disabled = 0x0,
+                        ///  Enable RR[1] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[2] register
+                RR2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[2] register
+                        Disabled = 0x0,
+                        ///  Enable RR[2] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[3] register
+                RR3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[3] register
+                        Disabled = 0x0,
+                        ///  Enable RR[3] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[4] register
+                RR4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[4] register
+                        Disabled = 0x0,
+                        ///  Enable RR[4] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[5] register
+                RR5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[5] register
+                        Disabled = 0x0,
+                        ///  Enable RR[5] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[6] register
+                RR6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[6] register
+                        Disabled = 0x0,
+                        ///  Enable RR[6] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[7] register
+                RR7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[7] register
+                        Disabled = 0x0,
+                        ///  Enable RR[7] register
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Configure the watchdog to either be paused, or kept running, while the CPU is sleeping
+                SLEEP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pause watchdog while the CPU is sleeping
+                        Pause = 0x0,
+                        ///  Keep the watchdog running while the CPU is sleeping
+                        Run = 0x1,
+                    },
+                },
+                reserved3: u2,
+                ///  Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger
+                HALT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pause watchdog while the CPU is halted by the debugger
+                        Pause = 0x0,
+                        ///  Keep the watchdog running while the CPU is halted by the debugger
+                        Run = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1536: [240]u8,
+            ///  Description collection[0]: Reload request 0
+            RR: [8]mmio.Mmio(packed struct(u32) {
+                ///  Reload request register
+                RR: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  Value to request a reload of the watchdog timer
+                        Reload = 0x6e524635,
+                        _,
+                    },
+                },
+            }),
+        };
+
+        ///  Pulse Width Modulation Unit 0
+        pub const PWM0 = extern struct {
+            reserved4: [4]u8,
+            ///  Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
+            TASKS_STOP: u32,
+            ///  Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running.
+            TASKS_SEQSTART: [2]u32,
+            ///  Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running.
+            TASKS_NEXTSTEP: u32,
+            reserved260: [240]u8,
+            ///  Response to STOP task, emitted when PWM pulses are no longer generated
+            EVENTS_STOPPED: u32,
+            ///  Description collection[0]: First PWM period started on sequence 0
+            EVENTS_SEQSTARTED: [2]u32,
+            ///  Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter
+            EVENTS_SEQEND: [2]u32,
+            ///  Emitted at the end of each PWM period
+            EVENTS_PWMPERIODEND: u32,
+            ///  Concatenated sequences have been played the amount of times defined in LOOP.CNT
+            EVENTS_LOOPSDONE: u32,
+            reserved512: [224]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between SEQEND[0] event and STOP task
+                SEQEND0_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between SEQEND[1] event and STOP task
+                SEQEND1_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between LOOPSDONE event and SEQSTART[0] task
+                LOOPSDONE_SEQSTART0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between LOOPSDONE event and SEQSTART[1] task
+                LOOPSDONE_SEQSTART1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between LOOPSDONE event and STOP task
+                LOOPSDONE_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Enable or disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for SEQSTARTED[0] event
+                SEQSTARTED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for SEQSTARTED[1] event
+                SEQSTARTED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for SEQEND[0] event
+                SEQEND0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for SEQEND[1] event
+                SEQEND1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for PWMPERIODEND event
+                PWMPERIODEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for LOOPSDONE event
+                LOOPSDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Enable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for SEQSTARTED[0] event
+                SEQSTARTED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for SEQSTARTED[1] event
+                SEQSTARTED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for SEQEND[0] event
+                SEQEND0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for SEQEND[1] event
+                SEQEND1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for PWMPERIODEND event
+                PWMPERIODEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for LOOPSDONE event
+                LOOPSDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to Disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for SEQSTARTED[0] event
+                SEQSTARTED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for SEQSTARTED[1] event
+                SEQSTARTED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for SEQEND[0] event
+                SEQEND0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for SEQEND[1] event
+                SEQEND1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for PWMPERIODEND event
+                PWMPERIODEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for LOOPSDONE event
+                LOOPSDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            reserved1280: [500]u8,
+            ///  PWM module enable register
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable PWM module
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Selects operating mode of the wave counter
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Selects up or up and down as wave counter mode
+                UPDOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Up counter - edge aligned PWM duty-cycle
+                        Up = 0x0,
+                        ///  Up and down counter - center aligned PWM duty cycle
+                        UpAndDown = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Value up to which the pulse generator counter counts
+            COUNTERTOP: mmio.Mmio(packed struct(u32) {
+                ///  Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used.
+                COUNTERTOP: u15,
+                padding: u17,
+            }),
+            ///  Configuration for PWM_CLK
+            PRESCALER: mmio.Mmio(packed struct(u32) {
+                ///  Pre-scaler of PWM_CLK
+                PRESCALER: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Divide by 1 (16MHz)
+                        DIV_1 = 0x0,
+                        ///  Divide by 2 ( 8MHz)
+                        DIV_2 = 0x1,
+                        ///  Divide by 4 ( 4MHz)
+                        DIV_4 = 0x2,
+                        ///  Divide by 8 ( 2MHz)
+                        DIV_8 = 0x3,
+                        ///  Divide by 16 ( 1MHz)
+                        DIV_16 = 0x4,
+                        ///  Divide by 32 ( 500kHz)
+                        DIV_32 = 0x5,
+                        ///  Divide by 64 ( 250kHz)
+                        DIV_64 = 0x6,
+                        ///  Divide by 128 ( 125kHz)
+                        DIV_128 = 0x7,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Configuration of the decoder
+            DECODER: mmio.Mmio(packed struct(u32) {
+                ///  How a sequence is read from RAM and spread to the compare register
+                LOAD: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  1st half word (16-bit) used in all PWM channels 0..3
+                        Common = 0x0,
+                        ///  1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3
+                        Grouped = 0x1,
+                        ///  1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3
+                        Individual = 0x2,
+                        ///  1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP
+                        WaveForm = 0x3,
+                    },
+                },
+                reserved8: u6,
+                ///  Selects source for advancing the active sequence
+                MODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  SEQ[n].REFRESH is used to determine loading internal compare registers
+                        RefreshCount = 0x0,
+                        ///  NEXTSTEP task causes a new value to be loaded to internal compare registers
+                        NextStep = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            ///  Amount of playback of a loop
+            LOOP: mmio.Mmio(packed struct(u32) {
+                ///  Amount of playback of pattern cycles
+                CNT: packed union {
+                    raw: u16,
+                    value: enum(u16) {
+                        ///  Looping disabled (stop at the end of the sequence)
+                        Disabled = 0x0,
+                        _,
+                    },
+                },
+                padding: u16,
+            }),
+        };
+
+        ///  Quadrature Decoder
+        pub const QDEC = extern struct {
+            ///  Task starting the quadrature decoder
+            TASKS_START: u32,
+            ///  Task stopping the quadrature decoder
+            TASKS_STOP: u32,
+            ///  Read and clear ACC and ACCDBL
+            TASKS_READCLRACC: u32,
+            ///  Read and clear ACC
+            TASKS_RDCLRACC: u32,
+            ///  Read and clear ACCDBL
+            TASKS_RDCLRDBL: u32,
+            reserved256: [236]u8,
+            ///  Event being generated for every new sample value written to the SAMPLE register
+            EVENTS_SAMPLERDY: u32,
+            ///  Non-null report ready
+            EVENTS_REPORTRDY: u32,
+            ///  ACC or ACCDBL register overflow
+            EVENTS_ACCOF: u32,
+            ///  Double displacement(s) detected
+            EVENTS_DBLRDY: u32,
+            ///  QDEC has been stopped
+            EVENTS_STOPPED: u32,
+            reserved512: [236]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between REPORTRDY event and READCLRACC task
+                REPORTRDY_READCLRACC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between SAMPLERDY event and STOP task
+                SAMPLERDY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between REPORTRDY event and RDCLRACC task
+                REPORTRDY_RDCLRACC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between REPORTRDY event and STOP task
+                REPORTRDY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between DBLRDY event and RDCLRDBL task
+                DBLRDY_RDCLRDBL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between DBLRDY event and STOP task
+                DBLRDY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between SAMPLERDY event and READCLRACC task
+                SAMPLERDY_READCLRACC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u25,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for SAMPLERDY event
+                SAMPLERDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for REPORTRDY event
+                REPORTRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for ACCOF event
+                ACCOF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for DBLRDY event
+                DBLRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for SAMPLERDY event
+                SAMPLERDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for REPORTRDY event
+                REPORTRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for ACCOF event
+                ACCOF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for DBLRDY event
+                DBLRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for STOPPED event
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved1280: [500]u8,
+            ///  Enable the quadrature decoder
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable the quadrature decoder
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  LED output pin polarity
+            LEDPOL: mmio.Mmio(packed struct(u32) {
+                ///  LED output pin polarity
+                LEDPOL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Led active on output pin low
+                        ActiveLow = 0x0,
+                        ///  Led active on output pin high
+                        ActiveHigh = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Sample period
+            SAMPLEPER: mmio.Mmio(packed struct(u32) {
+                ///  Sample period. The SAMPLE register will be updated for every new sample
+                SAMPLEPER: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  128 us
+                        @"128us" = 0x0,
+                        ///  256 us
+                        @"256us" = 0x1,
+                        ///  512 us
+                        @"512us" = 0x2,
+                        ///  1024 us
+                        @"1024us" = 0x3,
+                        ///  2048 us
+                        @"2048us" = 0x4,
+                        ///  4096 us
+                        @"4096us" = 0x5,
+                        ///  8192 us
+                        @"8192us" = 0x6,
+                        ///  16384 us
+                        @"16384us" = 0x7,
+                        ///  32768 us
+                        @"32ms" = 0x8,
+                        ///  65536 us
+                        @"65ms" = 0x9,
+                        ///  131072 us
+                        @"131ms" = 0xa,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Motion sample value
+            SAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  Last motion sample
+                SAMPLE: u32,
+            }),
+            ///  Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
+            REPORTPER: mmio.Mmio(packed struct(u32) {
+                ///  Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated
+                REPORTPER: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  10 samples / report
+                        @"10Smpl" = 0x0,
+                        ///  40 samples / report
+                        @"40Smpl" = 0x1,
+                        ///  80 samples / report
+                        @"80Smpl" = 0x2,
+                        ///  120 samples / report
+                        @"120Smpl" = 0x3,
+                        ///  160 samples / report
+                        @"160Smpl" = 0x4,
+                        ///  200 samples / report
+                        @"200Smpl" = 0x5,
+                        ///  240 samples / report
+                        @"240Smpl" = 0x6,
+                        ///  280 samples / report
+                        @"280Smpl" = 0x7,
+                        ///  1 sample / report
+                        @"1Smpl" = 0x8,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Register accumulating the valid transitions
+            ACC: mmio.Mmio(packed struct(u32) {
+                ///  Register accumulating all valid samples (not double transition) read from the SAMPLE register
+                ACC: u32,
+            }),
+            ///  Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
+            ACCREAD: mmio.Mmio(packed struct(u32) {
+                ///  Snapshot of the ACC register.
+                ACCREAD: u32,
+            }),
+            reserved1320: [12]u8,
+            ///  Enable input debounce filters
+            DBFEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable input debounce filters
+                DBFEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Debounce input filters disabled
+                        Disabled = 0x0,
+                        ///  Debounce input filters enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1344: [20]u8,
+            ///  Time period the LED is switched ON prior to sampling
+            LEDPRE: mmio.Mmio(packed struct(u32) {
+                ///  Period in us the LED is switched on prior to sampling
+                LEDPRE: u9,
+                padding: u23,
+            }),
+            ///  Register accumulating the number of detected double transitions
+            ACCDBL: mmio.Mmio(packed struct(u32) {
+                ///  Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).
+                ACCDBL: u4,
+                padding: u28,
+            }),
+            ///  Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
+            ACCDBLREAD: mmio.Mmio(packed struct(u32) {
+                ///  Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered.
+                ACCDBLREAD: u4,
+                padding: u28,
+            }),
+        };
+
+        ///  Comparator
+        pub const COMP = extern struct {
+            ///  Start comparator
+            TASKS_START: u32,
+            ///  Stop comparator
+            TASKS_STOP: u32,
+            ///  Sample comparator value
+            TASKS_SAMPLE: u32,
+            reserved256: [244]u8,
+            ///  COMP is ready and output is valid
+            EVENTS_READY: u32,
+            ///  Downward crossing
+            EVENTS_DOWN: u32,
+            ///  Upward crossing
+            EVENTS_UP: u32,
+            ///  Downward or upward crossing
+            EVENTS_CROSS: u32,
+            reserved512: [240]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between READY event and SAMPLE task
+                READY_SAMPLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between READY event and STOP task
+                READY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between DOWN event and STOP task
+                DOWN_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between UP event and STOP task
+                UP_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between CROSS event and STOP task
+                CROSS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for DOWN event
+                DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for UP event
+                UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for CROSS event
+                CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for DOWN event
+                DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for UP event
+                UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CROSS event
+                CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for DOWN event
+                DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for UP event
+                UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CROSS event
+                CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1024: [244]u8,
+            ///  Compare result
+            RESULT: mmio.Mmio(packed struct(u32) {
+                ///  Result of last compare. Decision point SAMPLE task.
+                RESULT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Input voltage is below the threshold (VIN+ < VIN-)
+                        Below = 0x0,
+                        ///  Input voltage is above the threshold (VIN+ > VIN-)
+                        Above = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1280: [252]u8,
+            ///  COMP enable
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable COMP
+                ENABLE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Pin select
+            PSEL: mmio.Mmio(packed struct(u32) {
+                ///  Analog pin select
+                PSEL: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  AIN0 selected as analog input
+                        AnalogInput0 = 0x0,
+                        ///  AIN1 selected as analog input
+                        AnalogInput1 = 0x1,
+                        ///  AIN2 selected as analog input
+                        AnalogInput2 = 0x2,
+                        ///  AIN3 selected as analog input
+                        AnalogInput3 = 0x3,
+                        ///  AIN4 selected as analog input
+                        AnalogInput4 = 0x4,
+                        ///  AIN5 selected as analog input
+                        AnalogInput5 = 0x5,
+                        ///  AIN6 selected as analog input
+                        AnalogInput6 = 0x6,
+                        ///  AIN7 selected as analog input
+                        AnalogInput7 = 0x7,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Reference source select for single-ended mode
+            REFSEL: mmio.Mmio(packed struct(u32) {
+                ///  Reference select
+                REFSEL: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  VREF = internal 1.2 V reference (VDD >= 1.7 V)
+                        Int1V2 = 0x0,
+                        ///  VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)
+                        Int1V8 = 0x1,
+                        ///  VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)
+                        Int2V4 = 0x2,
+                        ///  VREF = VDD
+                        VDD = 0x4,
+                        ///  VREF = AREF (VDD >= VREF >= AREFMIN)
+                        ARef = 0x7,
+                        _,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  External reference select
+            EXTREFSEL: mmio.Mmio(packed struct(u32) {
+                ///  External analog reference select
+                EXTREFSEL: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Use AIN0 as external analog reference
+                        AnalogReference0 = 0x0,
+                        ///  Use AIN1 as external analog reference
+                        AnalogReference1 = 0x1,
+                        ///  Use AIN2 as external analog reference
+                        AnalogReference2 = 0x2,
+                        ///  Use AIN3 as external analog reference
+                        AnalogReference3 = 0x3,
+                        ///  Use AIN4 as external analog reference
+                        AnalogReference4 = 0x4,
+                        ///  Use AIN5 as external analog reference
+                        AnalogReference5 = 0x5,
+                        ///  Use AIN6 as external analog reference
+                        AnalogReference6 = 0x6,
+                        ///  Use AIN7 as external analog reference
+                        AnalogReference7 = 0x7,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1328: [32]u8,
+            ///  Threshold configuration for hysteresis unit
+            TH: mmio.Mmio(packed struct(u32) {
+                ///  VDOWN = (THDOWN+1)/64*VREF
+                THDOWN: u6,
+                reserved8: u2,
+                ///  VUP = (THUP+1)/64*VREF
+                THUP: u6,
+                padding: u18,
+            }),
+            ///  Mode configuration
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Speed and power modes
+                SP: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Low-power mode
+                        Low = 0x0,
+                        ///  Normal mode
+                        Normal = 0x1,
+                        ///  High-speed mode
+                        High = 0x2,
+                        _,
+                    },
+                },
+                reserved8: u6,
+                ///  Main operation modes
+                MAIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Single-ended mode
+                        SE = 0x0,
+                        ///  Differential mode
+                        Diff = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            ///  Comparator hysteresis enable
+            HYST: mmio.Mmio(packed struct(u32) {
+                ///  Comparator hysteresis
+                HYST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Comparator hysteresis disabled
+                        NoHyst = 0x0,
+                        ///  Comparator hysteresis enabled
+                        Hyst50mV = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Current source select on analog input
+            ISOURCE: mmio.Mmio(packed struct(u32) {
+                ///  Comparator hysteresis
+                ISOURCE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Current source disabled
+                        Off = 0x0,
+                        ///  Current source enabled (+/- 2.5 uA)
+                        Ien2mA5 = 0x1,
+                        ///  Current source enabled (+/- 5 uA)
+                        Ien5mA = 0x2,
+                        ///  Current source enabled (+/- 10 uA)
+                        Ien10mA = 0x3,
+                    },
+                },
+                padding: u30,
+            }),
+        };
+
+        ///  Low Power Comparator
+        pub const LPCOMP = extern struct {
+            ///  Start comparator
+            TASKS_START: u32,
+            ///  Stop comparator
+            TASKS_STOP: u32,
+            ///  Sample comparator value
+            TASKS_SAMPLE: u32,
+            reserved256: [244]u8,
+            ///  LPCOMP is ready and output is valid
+            EVENTS_READY: u32,
+            ///  Downward crossing
+            EVENTS_DOWN: u32,
+            ///  Upward crossing
+            EVENTS_UP: u32,
+            ///  Downward or upward crossing
+            EVENTS_CROSS: u32,
+            reserved512: [240]u8,
+            ///  Shortcut register
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between READY event and SAMPLE task
+                READY_SAMPLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between READY event and STOP task
+                READY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between DOWN event and STOP task
+                DOWN_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between UP event and STOP task
+                UP_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between CROSS event and STOP task
+                CROSS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Enable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for DOWN event
+                DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for UP event
+                UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Enable interrupt for CROSS event
+                CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to Disable interrupt for READY event
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for DOWN event
+                DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for UP event
+                UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to Disable interrupt for CROSS event
+                CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1024: [244]u8,
+            ///  Compare result
+            RESULT: mmio.Mmio(packed struct(u32) {
+                ///  Result of last compare. Decision point SAMPLE task.
+                RESULT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Input voltage is below the reference threshold (VIN+ < VIN-).
+                        Below = 0x0,
+                        ///  Input voltage is above the reference threshold (VIN+ > VIN-).
+                        Above = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1280: [252]u8,
+            ///  Enable LPCOMP
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable LPCOMP
+                ENABLE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Input pin select
+            PSEL: mmio.Mmio(packed struct(u32) {
+                ///  Analog pin select
+                PSEL: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  AIN0 selected as analog input
+                        AnalogInput0 = 0x0,
+                        ///  AIN1 selected as analog input
+                        AnalogInput1 = 0x1,
+                        ///  AIN2 selected as analog input
+                        AnalogInput2 = 0x2,
+                        ///  AIN3 selected as analog input
+                        AnalogInput3 = 0x3,
+                        ///  AIN4 selected as analog input
+                        AnalogInput4 = 0x4,
+                        ///  AIN5 selected as analog input
+                        AnalogInput5 = 0x5,
+                        ///  AIN6 selected as analog input
+                        AnalogInput6 = 0x6,
+                        ///  AIN7 selected as analog input
+                        AnalogInput7 = 0x7,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Reference select
+            REFSEL: mmio.Mmio(packed struct(u32) {
+                ///  Reference select
+                REFSEL: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  VDD * 1/8 selected as reference
+                        Ref1_8Vdd = 0x0,
+                        ///  VDD * 2/8 selected as reference
+                        Ref2_8Vdd = 0x1,
+                        ///  VDD * 3/8 selected as reference
+                        Ref3_8Vdd = 0x2,
+                        ///  VDD * 4/8 selected as reference
+                        Ref4_8Vdd = 0x3,
+                        ///  VDD * 5/8 selected as reference
+                        Ref5_8Vdd = 0x4,
+                        ///  VDD * 6/8 selected as reference
+                        Ref6_8Vdd = 0x5,
+                        ///  VDD * 7/8 selected as reference
+                        Ref7_8Vdd = 0x6,
+                        ///  External analog reference selected
+                        ARef = 0x7,
+                        ///  VDD * 1/16 selected as reference
+                        Ref1_16Vdd = 0x8,
+                        ///  VDD * 3/16 selected as reference
+                        Ref3_16Vdd = 0x9,
+                        ///  VDD * 5/16 selected as reference
+                        Ref5_16Vdd = 0xa,
+                        ///  VDD * 7/16 selected as reference
+                        Ref7_16Vdd = 0xb,
+                        ///  VDD * 9/16 selected as reference
+                        Ref9_16Vdd = 0xc,
+                        ///  VDD * 11/16 selected as reference
+                        Ref11_16Vdd = 0xd,
+                        ///  VDD * 13/16 selected as reference
+                        Ref13_16Vdd = 0xe,
+                        ///  VDD * 15/16 selected as reference
+                        Ref15_16Vdd = 0xf,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  External reference select
+            EXTREFSEL: mmio.Mmio(packed struct(u32) {
+                ///  External analog reference select
+                EXTREFSEL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Use AIN0 as external analog reference
+                        AnalogReference0 = 0x0,
+                        ///  Use AIN1 as external analog reference
+                        AnalogReference1 = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1312: [16]u8,
+            ///  Analog detect configuration
+            ANADETECT: mmio.Mmio(packed struct(u32) {
+                ///  Analog detect configuration
+                ANADETECT: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Generate ANADETECT on crossing, both upward crossing and downward crossing
+                        Cross = 0x0,
+                        ///  Generate ANADETECT on upward crossing only
+                        Up = 0x1,
+                        ///  Generate ANADETECT on downward crossing only
+                        Down = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1336: [20]u8,
+            ///  Comparator hysteresis enable
+            HYST: mmio.Mmio(packed struct(u32) {
+                ///  Comparator hysteresis enable
+                HYST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Comparator hysteresis disabled
+                        NoHyst = 0x0,
+                        ///  Comparator hysteresis disabled (typ. 50 mV)
+                        Hyst50mV = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  Software interrupt 0
+        pub const SWI0 = extern struct {
+            ///  Unused.
+            UNUSED: u32,
+        };
+    };
+};
diff --git a/src/chips/nrf52840.json b/src/chips/nrf52840.json
new file mode 100644
index 000000000..a758e2107
--- /dev/null
+++ b/src/chips/nrf52840.json
@@ -0,0 +1,44867 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "SCS": {
+        "description": "System Control Space",
+        "children": {
+          "register_groups": {
+            "SysTick": {
+              "description": "System Tick Timer",
+              "children": {
+                "registers": {
+                  "CTRL": {
+                    "description": "SysTick Control and Status Register",
+                    "offset": 0,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "ENABLE": {
+                          "offset": 0,
+                          "size": 1
+                        },
+                        "TICKINT": {
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "CLKSOURCE": {
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "COUNTFLAG": {
+                          "offset": 16,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "LOAD": {
+                    "description": "SysTick Reload Value Register",
+                    "offset": 4,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "RELOAD": {
+                          "offset": 0,
+                          "size": 24
+                        }
+                      }
+                    }
+                  },
+                  "VAL": {
+                    "description": "SysTick Current Value Register",
+                    "offset": 8,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "CURRENT": {
+                          "offset": 0,
+                          "size": 24
+                        }
+                      }
+                    }
+                  },
+                  "CALIB": {
+                    "description": "SysTick Calibration Register",
+                    "offset": 12,
+                    "size": 32,
+                    "access": "read-only",
+                    "children": {
+                      "fields": {
+                        "TENMS": {
+                          "offset": 0,
+                          "size": 24
+                        },
+                        "SKEW": {
+                          "offset": 30,
+                          "size": 1
+                        },
+                        "NOREF": {
+                          "offset": 31,
+                          "size": 1
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FICR": {
+        "description": "Factory information configuration registers",
+        "children": {
+          "registers": {
+            "CODEPAGESIZE": {
+              "description": "Code memory page size",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CODEPAGESIZE": {
+                    "description": "Code memory page size",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CODESIZE": {
+              "description": "Code memory size",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CODESIZE": {
+                    "description": "Code memory size in number of pages",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DEVICEID": {
+              "description": "Description collection: Device identifier",
+              "offset": 96,
+              "size": 32,
+              "count": 2,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DEVICEID": {
+                    "description": "64 bit unique device identifier",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ER": {
+              "description": "Description collection: Encryption root, word n",
+              "offset": 128,
+              "size": 32,
+              "count": 4,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ER": {
+                    "description": "Encryption root, word n",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IR": {
+              "description": "Description collection: Identity Root, word n",
+              "offset": 144,
+              "size": 32,
+              "count": 4,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IR": {
+                    "description": "Identity Root, word n",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DEVICEADDRTYPE": {
+              "description": "Device address type",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DEVICEADDRTYPE": {
+                    "description": "Device address type",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Public": {
+                            "description": "Public address",
+                            "value": 0
+                          },
+                          "Random": {
+                            "description": "Random address",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DEVICEADDR": {
+              "description": "Description collection: Device address n",
+              "offset": 164,
+              "size": 32,
+              "count": 2,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DEVICEADDR": {
+                    "description": "48 bit device address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PRODTEST": {
+              "description": "Description collection: Production test signature n",
+              "offset": 848,
+              "size": 32,
+              "count": 3,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PRODTEST": {
+                    "description": "Production test signature n",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Done": {
+                            "description": "Production tests done",
+                            "value": 3141677471
+                          },
+                          "NotDone": {
+                            "description": "Production tests not done",
+                            "value": 4294967295
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UICR": {
+        "description": "User information configuration registers",
+        "children": {
+          "registers": {
+            "NRFFW": {
+              "description": "Description collection: Reserved for Nordic firmware design",
+              "offset": 20,
+              "size": 32,
+              "count": 13,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NRFFW": {
+                    "description": "Reserved for Nordic firmware design",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "NRFHW": {
+              "description": "Description collection: Reserved for Nordic hardware design",
+              "offset": 80,
+              "size": 32,
+              "count": 12,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NRFHW": {
+                    "description": "Reserved for Nordic hardware design",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CUSTOMER": {
+              "description": "Description collection: Reserved for customer",
+              "offset": 128,
+              "size": 32,
+              "count": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CUSTOMER": {
+                    "description": "Reserved for customer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PSELRESET": {
+              "description": "Description collection: Mapping of the nRESET function (see POWER chapter for details)",
+              "offset": 512,
+              "size": 32,
+              "count": 2,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN": {
+                    "description": "GPIO pin number onto which nRESET is exposed",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "PORT": {
+                    "description": "Port number onto which nRESET is exposed",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CONNECT": {
+                    "description": "Connection",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disconnected": {
+                            "description": "Disconnect",
+                            "value": 1
+                          },
+                          "Connected": {
+                            "description": "Connect",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "APPROTECT": {
+              "description": "Access port protection",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PALL": {
+                    "description": "Enable or disable access port protection.",
+                    "offset": 0,
+                    "size": 8,
+                    "enum": {
+                      "size": 8,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 255
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "NFCPINS": {
+              "description": "Setting of pins dedicated to NFC functionality: NFC antenna or GPIO",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PROTECT": {
+                    "description": "Setting of pins dedicated to NFC functionality",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Operation as GPIO pins. Same protection as normal GPIO pins",
+                            "value": 0
+                          },
+                          "NFC": {
+                            "description": "Operation as NFC antenna pins. Configures the protection for NFC operation",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DEBUGCTRL": {
+              "description": "Processor debug control",
+              "offset": 528,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPUNIDEN": {
+                    "description": "Configure CPU non-intrusive debug features",
+                    "offset": 0,
+                    "size": 8,
+                    "enum": {
+                      "size": 8,
+                      "children": {
+                        "enum_fields": {
+                          "Enabled": {
+                            "description": "Enable CPU ITM and ETM functionality (default behavior)",
+                            "value": 255
+                          },
+                          "Disabled": {
+                            "description": "Disable CPU ITM and ETM functionality",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPUFPBEN": {
+                    "description": "Configure CPU flash patch and breakpoint (FPB) unit behavior",
+                    "offset": 8,
+                    "size": 8,
+                    "enum": {
+                      "size": 8,
+                      "children": {
+                        "enum_fields": {
+                          "Enabled": {
+                            "description": "Enable CPU FPB unit (default behavior)",
+                            "value": 255
+                          },
+                          "Disabled": {
+                            "description": "Disable CPU FPB unit. Writes into the FPB registers will be ignored.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REGOUT0": {
+              "description": "GPIO reference voltage / external output supply voltage in high voltage mode",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VOUT": {
+                    "description": "Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF.",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "1V8": {
+                            "description": "1.8 V",
+                            "value": 0
+                          },
+                          "2V1": {
+                            "description": "2.1 V",
+                            "value": 1
+                          },
+                          "2V4": {
+                            "description": "2.4 V",
+                            "value": 2
+                          },
+                          "2V7": {
+                            "description": "2.7 V",
+                            "value": 3
+                          },
+                          "3V0": {
+                            "description": "3.0 V",
+                            "value": 4
+                          },
+                          "3V3": {
+                            "description": "3.3 V",
+                            "value": 5
+                          },
+                          "DEFAULT": {
+                            "description": "Default voltage: 1.8 V",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CLOCK": {
+        "description": "Clock control",
+        "children": {
+          "registers": {
+            "TASKS_HFCLKSTART": {
+              "description": "Start HFXO crystal oscillator",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_HFCLKSTART": {
+                    "description": "Start HFXO crystal oscillator",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_HFCLKSTOP": {
+              "description": "Stop HFXO crystal oscillator",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_HFCLKSTOP": {
+                    "description": "Stop HFXO crystal oscillator",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_LFCLKSTART": {
+              "description": "Start LFCLK",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_LFCLKSTART": {
+                    "description": "Start LFCLK",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_LFCLKSTOP": {
+              "description": "Stop LFCLK",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_LFCLKSTOP": {
+                    "description": "Stop LFCLK",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_CAL": {
+              "description": "Start calibration of LFRC",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CAL": {
+                    "description": "Start calibration of LFRC",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_CTSTART": {
+              "description": "Start calibration timer",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CTSTART": {
+                    "description": "Start calibration timer",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_CTSTOP": {
+              "description": "Stop calibration timer",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CTSTOP": {
+                    "description": "Stop calibration timer",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_HFCLKSTARTED": {
+              "description": "HFXO crystal oscillator started",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_HFCLKSTARTED": {
+                    "description": "HFXO crystal oscillator started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_LFCLKSTARTED": {
+              "description": "LFCLK started",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_LFCLKSTARTED": {
+                    "description": "LFCLK started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_DONE": {
+              "description": "Calibration of LFRC completed",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_DONE": {
+                    "description": "Calibration of LFRC completed",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CTTO": {
+              "description": "Calibration timer timeout",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CTTO": {
+                    "description": "Calibration timer timeout",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CTSTARTED": {
+              "description": "Calibration timer has been started and is ready to process new tasks",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CTSTARTED": {
+                    "description": "Calibration timer has been started and is ready to process new tasks",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CTSTOPPED": {
+              "description": "Calibration timer has been stopped and is ready to process new tasks",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CTSTOPPED": {
+                    "description": "Calibration timer has been stopped and is ready to process new tasks",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HFCLKSTARTED": {
+                    "description": "Write '1' to enable interrupt for event HFCLKSTARTED",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LFCLKSTARTED": {
+                    "description": "Write '1' to enable interrupt for event LFCLKSTARTED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DONE": {
+                    "description": "Write '1' to enable interrupt for event DONE",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CTTO": {
+                    "description": "Write '1' to enable interrupt for event CTTO",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CTSTARTED": {
+                    "description": "Write '1' to enable interrupt for event CTSTARTED",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CTSTOPPED": {
+                    "description": "Write '1' to enable interrupt for event CTSTOPPED",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HFCLKSTARTED": {
+                    "description": "Write '1' to disable interrupt for event HFCLKSTARTED",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LFCLKSTARTED": {
+                    "description": "Write '1' to disable interrupt for event LFCLKSTARTED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DONE": {
+                    "description": "Write '1' to disable interrupt for event DONE",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CTTO": {
+                    "description": "Write '1' to disable interrupt for event CTTO",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CTSTARTED": {
+                    "description": "Write '1' to disable interrupt for event CTSTARTED",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CTSTOPPED": {
+                    "description": "Write '1' to disable interrupt for event CTSTOPPED",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "HFCLKRUN": {
+              "description": "Status indicating that HFCLKSTART task has been triggered",
+              "offset": 1032,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STATUS": {
+                    "description": "HFCLKSTART task triggered or not",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotTriggered": {
+                            "description": "Task not triggered",
+                            "value": 0
+                          },
+                          "Triggered": {
+                            "description": "Task triggered",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "HFCLKSTAT": {
+              "description": "HFCLK status",
+              "offset": 1036,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SRC": {
+                    "description": "Source of HFCLK",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RC": {
+                            "description": "64 MHz internal oscillator (HFINT)",
+                            "value": 0
+                          },
+                          "Xtal": {
+                            "description": "64 MHz crystal oscillator (HFXO)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STATE": {
+                    "description": "HFCLK state",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotRunning": {
+                            "description": "HFCLK not running",
+                            "value": 0
+                          },
+                          "Running": {
+                            "description": "HFCLK running",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LFCLKRUN": {
+              "description": "Status indicating that LFCLKSTART task has been triggered",
+              "offset": 1044,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STATUS": {
+                    "description": "LFCLKSTART task triggered or not",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotTriggered": {
+                            "description": "Task not triggered",
+                            "value": 0
+                          },
+                          "Triggered": {
+                            "description": "Task triggered",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LFCLKSTAT": {
+              "description": "LFCLK status",
+              "offset": 1048,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SRC": {
+                    "description": "Source of LFCLK",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "RC": {
+                            "description": "32.768 kHz RC oscillator (LFRC)",
+                            "value": 0
+                          },
+                          "Xtal": {
+                            "description": "32.768 kHz crystal oscillator (LFXO)",
+                            "value": 1
+                          },
+                          "Synth": {
+                            "description": "32.768 kHz synthesized from HFCLK (LFSYNT)",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STATE": {
+                    "description": "LFCLK state",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotRunning": {
+                            "description": "LFCLK not running",
+                            "value": 0
+                          },
+                          "Running": {
+                            "description": "LFCLK running",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LFCLKSRCCOPY": {
+              "description": "Copy of LFCLKSRC register, set when LFCLKSTART task was triggered",
+              "offset": 1052,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SRC": {
+                    "description": "Clock source",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "RC": {
+                            "description": "32.768 kHz RC oscillator (LFRC)",
+                            "value": 0
+                          },
+                          "Xtal": {
+                            "description": "32.768 kHz crystal oscillator (LFXO)",
+                            "value": 1
+                          },
+                          "Synth": {
+                            "description": "32.768 kHz synthesized from HFCLK (LFSYNT)",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LFCLKSRC": {
+              "description": "Clock source for the LFCLK",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRC": {
+                    "description": "Clock source",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "RC": {
+                            "description": "32.768 kHz RC oscillator (LFRC)",
+                            "value": 0
+                          },
+                          "Xtal": {
+                            "description": "32.768 kHz crystal oscillator (LFXO)",
+                            "value": 1
+                          },
+                          "Synth": {
+                            "description": "32.768 kHz synthesized from HFCLK (LFSYNT)",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BYPASS": {
+                    "description": "Enable or disable bypass of LFCLK crystal oscillator with external clock source",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable (use with Xtal or low-swing external source)",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable (use with rail-to-rail external source)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EXTERNAL": {
+                    "description": "Enable or disable external source for LFCLK",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable external source (use with Xtal)",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable use of external source instead of Xtal (SRC needs to be set to Xtal)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "HFXODEBOUNCE": {
+              "description": "HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task.",
+              "offset": 1320,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HFXODEBOUNCE": {
+                    "description": "HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us.",
+                    "offset": 0,
+                    "size": 8,
+                    "enum": {
+                      "size": 8,
+                      "children": {
+                        "enum_fields": {
+                          "Db256us": {
+                            "description": "256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals.",
+                            "value": 16
+                          },
+                          "Db1024us": {
+                            "description": "1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals.",
+                            "value": 64
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CTIV": {
+              "description": "Calibration timer interval",
+              "offset": 1336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTIV": {
+                    "description": "Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "TRACECONFIG": {
+              "description": "Clocking options for the trace port debug interface",
+              "offset": 1372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRACEPORTSPEED": {
+                    "description": "Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "32MHz": {
+                            "description": "32 MHz trace port clock (TRACECLK = 16 MHz)",
+                            "value": 0
+                          },
+                          "16MHz": {
+                            "description": "16 MHz trace port clock (TRACECLK = 8 MHz)",
+                            "value": 1
+                          },
+                          "8MHz": {
+                            "description": "8 MHz trace port clock (TRACECLK = 4 MHz)",
+                            "value": 2
+                          },
+                          "4MHz": {
+                            "description": "4 MHz trace port clock (TRACECLK = 2 MHz)",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRACEMUX": {
+                    "description": "Pin multiplexing of trace signals. See pin assignment chapter for more details.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO": {
+                            "description": "No trace signals routed to pins. All pins can be used as regular GPIOs.",
+                            "value": 0
+                          },
+                          "Serial": {
+                            "description": "SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs.",
+                            "value": 1
+                          },
+                          "Parallel": {
+                            "description": "All trace signals (TRACECLK and TRACEDATA[n]) routed to pins.",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LFRCMODE": {
+              "description": "LFRC mode configuration",
+              "offset": 1460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Set LFRC mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Normal": {
+                            "description": "Normal mode",
+                            "value": 0
+                          },
+                          "ULP": {
+                            "description": "Ultra-low power mode (ULP)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STATUS": {
+                    "description": "Active LFRC mode. This field is read only.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Normal": {
+                            "description": "Normal mode",
+                            "value": 0
+                          },
+                          "ULP": {
+                            "description": "Ultra-low power mode (ULP)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "POWER": {
+        "description": "Power control",
+        "children": {
+          "registers": {
+            "TASKS_CONSTLAT": {
+              "description": "Enable Constant Latency mode",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CONSTLAT": {
+                    "description": "Enable Constant Latency mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_LOWPWR": {
+              "description": "Enable Low-power mode (variable latency)",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_LOWPWR": {
+                    "description": "Enable Low-power mode (variable latency)",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_POFWARN": {
+              "description": "Power failure warning",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_POFWARN": {
+                    "description": "Power failure warning",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_SLEEPENTER": {
+              "description": "CPU entered WFI/WFE sleep",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_SLEEPENTER": {
+                    "description": "CPU entered WFI/WFE sleep",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_SLEEPEXIT": {
+              "description": "CPU exited WFI/WFE sleep",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_SLEEPEXIT": {
+                    "description": "CPU exited WFI/WFE sleep",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_USBDETECTED": {
+              "description": "Voltage supply detected on VBUS",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_USBDETECTED": {
+                    "description": "Voltage supply detected on VBUS",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_USBREMOVED": {
+              "description": "Voltage supply removed from VBUS",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_USBREMOVED": {
+                    "description": "Voltage supply removed from VBUS",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_USBPWRRDY": {
+              "description": "USB 3.3 V supply ready",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_USBPWRRDY": {
+                    "description": "USB 3.3 V supply ready",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POFWARN": {
+                    "description": "Write '1' to enable interrupt for event POFWARN",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SLEEPENTER": {
+                    "description": "Write '1' to enable interrupt for event SLEEPENTER",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SLEEPEXIT": {
+                    "description": "Write '1' to enable interrupt for event SLEEPEXIT",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "USBDETECTED": {
+                    "description": "Write '1' to enable interrupt for event USBDETECTED",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "USBREMOVED": {
+                    "description": "Write '1' to enable interrupt for event USBREMOVED",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "USBPWRRDY": {
+                    "description": "Write '1' to enable interrupt for event USBPWRRDY",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POFWARN": {
+                    "description": "Write '1' to disable interrupt for event POFWARN",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SLEEPENTER": {
+                    "description": "Write '1' to disable interrupt for event SLEEPENTER",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SLEEPEXIT": {
+                    "description": "Write '1' to disable interrupt for event SLEEPEXIT",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "USBDETECTED": {
+                    "description": "Write '1' to disable interrupt for event USBDETECTED",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "USBREMOVED": {
+                    "description": "Write '1' to disable interrupt for event USBREMOVED",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "USBPWRRDY": {
+                    "description": "Write '1' to disable interrupt for event USBPWRRDY",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RESETREAS": {
+              "description": "Reset reason",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESETPIN": {
+                    "description": "Reset from pin-reset detected",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOG": {
+                    "description": "Reset from watchdog detected",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SREQ": {
+                    "description": "Reset from soft reset detected",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOCKUP": {
+                    "description": "Reset from CPU lock-up detected",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OFF": {
+                    "description": "Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LPCOMP": {
+                    "description": "Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DIF": {
+                    "description": "Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NFC": {
+                    "description": "Reset due to wake up from System OFF mode by NFC field detect",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "VBUS": {
+                    "description": "Reset due to wake up from System OFF mode by VBUS rising into valid range",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RAMSTATUS": {
+              "description": "Deprecated register - RAM status register",
+              "offset": 1064,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RAMBLOCK0": {
+                    "description": "RAM block 0 is on or off/powering up",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RAMBLOCK1": {
+                    "description": "RAM block 1 is on or off/powering up",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RAMBLOCK2": {
+                    "description": "RAM block 2 is on or off/powering up",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RAMBLOCK3": {
+                    "description": "RAM block 3 is on or off/powering up",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Off": {
+                            "description": "Off",
+                            "value": 0
+                          },
+                          "On": {
+                            "description": "On",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "USBREGSTATUS": {
+              "description": "USB supply status",
+              "offset": 1080,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "VBUSDETECT": {
+                    "description": "VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information)",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoVbus": {
+                            "description": "VBUS voltage below valid threshold",
+                            "value": 0
+                          },
+                          "VbusPresent": {
+                            "description": "VBUS voltage above valid threshold",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTPUTRDY": {
+                    "description": "USB supply output settling time elapsed",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotReady": {
+                            "description": "USBREG output settling time not elapsed",
+                            "value": 0
+                          },
+                          "Ready": {
+                            "description": "USBREG output settling time elapsed (same information as USBPWRRDY event)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SYSTEMOFF": {
+              "description": "System OFF register",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "SYSTEMOFF": {
+                    "description": "Enable System OFF mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Enter": {
+                            "description": "Enable System OFF mode",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "POFCON": {
+              "description": "Power-fail comparator configuration",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POF": {
+                    "description": "Enable or disable power failure warning",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "THRESHOLD": {
+                    "description": "Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages.",
+                    "offset": 1,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "V17": {
+                            "description": "Set threshold to 1.7 V",
+                            "value": 4
+                          },
+                          "V18": {
+                            "description": "Set threshold to 1.8 V",
+                            "value": 5
+                          },
+                          "V19": {
+                            "description": "Set threshold to 1.9 V",
+                            "value": 6
+                          },
+                          "V20": {
+                            "description": "Set threshold to 2.0 V",
+                            "value": 7
+                          },
+                          "V21": {
+                            "description": "Set threshold to 2.1 V",
+                            "value": 8
+                          },
+                          "V22": {
+                            "description": "Set threshold to 2.2 V",
+                            "value": 9
+                          },
+                          "V23": {
+                            "description": "Set threshold to 2.3 V",
+                            "value": 10
+                          },
+                          "V24": {
+                            "description": "Set threshold to 2.4 V",
+                            "value": 11
+                          },
+                          "V25": {
+                            "description": "Set threshold to 2.5 V",
+                            "value": 12
+                          },
+                          "V26": {
+                            "description": "Set threshold to 2.6 V",
+                            "value": 13
+                          },
+                          "V27": {
+                            "description": "Set threshold to 2.7 V",
+                            "value": 14
+                          },
+                          "V28": {
+                            "description": "Set threshold to 2.8 V",
+                            "value": 15
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "THRESHOLDVDDH": {
+                    "description": "Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH).",
+                    "offset": 8,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "V27": {
+                            "description": "Set threshold to 2.7 V",
+                            "value": 0
+                          },
+                          "V28": {
+                            "description": "Set threshold to 2.8 V",
+                            "value": 1
+                          },
+                          "V29": {
+                            "description": "Set threshold to 2.9 V",
+                            "value": 2
+                          },
+                          "V30": {
+                            "description": "Set threshold to 3.0 V",
+                            "value": 3
+                          },
+                          "V31": {
+                            "description": "Set threshold to 3.1 V",
+                            "value": 4
+                          },
+                          "V32": {
+                            "description": "Set threshold to 3.2 V",
+                            "value": 5
+                          },
+                          "V33": {
+                            "description": "Set threshold to 3.3 V",
+                            "value": 6
+                          },
+                          "V34": {
+                            "description": "Set threshold to 3.4 V",
+                            "value": 7
+                          },
+                          "V35": {
+                            "description": "Set threshold to 3.5 V",
+                            "value": 8
+                          },
+                          "V36": {
+                            "description": "Set threshold to 3.6 V",
+                            "value": 9
+                          },
+                          "V37": {
+                            "description": "Set threshold to 3.7 V",
+                            "value": 10
+                          },
+                          "V38": {
+                            "description": "Set threshold to 3.8 V",
+                            "value": 11
+                          },
+                          "V39": {
+                            "description": "Set threshold to 3.9 V",
+                            "value": 12
+                          },
+                          "V40": {
+                            "description": "Set threshold to 4.0 V",
+                            "value": 13
+                          },
+                          "V41": {
+                            "description": "Set threshold to 4.1 V",
+                            "value": 14
+                          },
+                          "V42": {
+                            "description": "Set threshold to 4.2 V",
+                            "value": 15
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPREGRET": {
+              "description": "General purpose retention register",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPREGRET": {
+                    "description": "General purpose retention register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "GPREGRET2": {
+              "description": "General purpose retention register",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPREGRET": {
+                    "description": "General purpose retention register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DCDCEN": {
+              "description": "Enable DC/DC converter for REG1 stage",
+              "offset": 1400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCDCEN": {
+                    "description": "Enable DC/DC converter for REG1 stage.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DCDCEN0": {
+              "description": "Enable DC/DC converter for REG0 stage",
+              "offset": 1408,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCDCEN": {
+                    "description": "Enable DC/DC converter for REG0 stage.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MAINREGSTATUS": {
+              "description": "Main supply status",
+              "offset": 1600,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "MAINREGSTATUS": {
+                    "description": "Main supply status",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Normal": {
+                            "description": "Normal voltage mode. Voltage supplied on VDD.",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "High voltage mode. Voltage supplied on VDDH.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "P0": {
+        "description": "GPIO Port 1",
+        "children": {
+          "registers": {
+            "OUT": {
+              "description": "Write GPIO port",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "OUTSET": {
+              "description": "Set individual bits in GPIO port",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "OUTCLR": {
+              "description": "Clear individual bits in GPIO port",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Read: pin driver is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Read: pin driver is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IN": {
+              "description": "Read GPIO port",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Pin input is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Pin input is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DIR": {
+              "description": "Direction of GPIO pins",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DIRSET": {
+              "description": "DIR set register",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Set as output pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Set as output pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Set as output pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Set as output pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Set as output pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Set as output pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Set as output pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Set as output pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Set as output pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Set as output pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Set as output pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Set as output pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Set as output pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Set as output pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Set as output pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Set as output pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Set as output pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Set as output pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Set as output pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Set as output pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Set as output pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Set as output pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Set as output pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Set as output pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Set as output pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Set as output pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Set as output pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Set as output pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Set as output pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Set as output pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Set as output pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Set as output pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DIRCLR": {
+              "description": "DIR clear register",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Set as input pin 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Set as input pin 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Set as input pin 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Set as input pin 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Set as input pin 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Set as input pin 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Set as input pin 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Set as input pin 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Set as input pin 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Set as input pin 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Set as input pin 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Set as input pin 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Set as input pin 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Set as input pin 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Set as input pin 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Set as input pin 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Set as input pin 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Set as input pin 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Set as input pin 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Set as input pin 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Set as input pin 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Set as input pin 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Set as input pin 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Set as input pin 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Set as input pin 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Set as input pin 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Set as input pin 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Set as input pin 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Set as input pin 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Set as input pin 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Set as input pin 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Set as input pin 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Read: pin set as input",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Read: pin set as output",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LATCH": {
+              "description": "Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN0": {
+                    "description": "Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN1": {
+                    "description": "Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN2": {
+                    "description": "Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN3": {
+                    "description": "Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN4": {
+                    "description": "Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN5": {
+                    "description": "Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN6": {
+                    "description": "Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN7": {
+                    "description": "Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN8": {
+                    "description": "Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN9": {
+                    "description": "Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN10": {
+                    "description": "Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN11": {
+                    "description": "Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN12": {
+                    "description": "Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN13": {
+                    "description": "Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN14": {
+                    "description": "Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN15": {
+                    "description": "Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN16": {
+                    "description": "Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN17": {
+                    "description": "Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN18": {
+                    "description": "Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN19": {
+                    "description": "Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN20": {
+                    "description": "Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN21": {
+                    "description": "Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN22": {
+                    "description": "Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN23": {
+                    "description": "Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN24": {
+                    "description": "Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN25": {
+                    "description": "Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN26": {
+                    "description": "Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN27": {
+                    "description": "Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN28": {
+                    "description": "Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN29": {
+                    "description": "Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN30": {
+                    "description": "Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PIN31": {
+                    "description": "Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLatched": {
+                            "description": "Criteria has not been met",
+                            "value": 0
+                          },
+                          "Latched": {
+                            "description": "Criteria has been met",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DETECTMODE": {
+              "description": "Select between default DETECT signal behaviour and LDETECT mode",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DETECTMODE": {
+                    "description": "Select between default DETECT signal behaviour and LDETECT mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Default": {
+                            "description": "DETECT directly connected to PIN DETECT signals",
+                            "value": 0
+                          },
+                          "LDETECT": {
+                            "description": "Use the latched LDETECT behaviour",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PIN_CNF": {
+              "description": "Description collection: Configuration of GPIO pins",
+              "offset": 1792,
+              "size": 32,
+              "count": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIR": {
+                    "description": "Pin direction. Same physical register as DIR register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Input": {
+                            "description": "Configure pin as an input pin",
+                            "value": 0
+                          },
+                          "Output": {
+                            "description": "Configure pin as an output pin",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INPUT": {
+                    "description": "Connect or disconnect input buffer",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Connect": {
+                            "description": "Connect input buffer",
+                            "value": 0
+                          },
+                          "Disconnect": {
+                            "description": "Disconnect input buffer",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PULL": {
+                    "description": "Pull configuration",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "No pull",
+                            "value": 0
+                          },
+                          "Pulldown": {
+                            "description": "Pull down on pin",
+                            "value": 1
+                          },
+                          "Pullup": {
+                            "description": "Pull up on pin",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DRIVE": {
+                    "description": "Drive configuration",
+                    "offset": 8,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "S0S1": {
+                            "description": "Standard '0', standard '1'",
+                            "value": 0
+                          },
+                          "H0S1": {
+                            "description": "High drive '0', standard '1'",
+                            "value": 1
+                          },
+                          "S0H1": {
+                            "description": "Standard '0', high drive '1'",
+                            "value": 2
+                          },
+                          "H0H1": {
+                            "description": "High drive '0', high 'drive '1''",
+                            "value": 3
+                          },
+                          "D0S1": {
+                            "description": "Disconnect '0' standard '1' (normally used for wired-or connections)",
+                            "value": 4
+                          },
+                          "D0H1": {
+                            "description": "Disconnect '0', high drive '1' (normally used for wired-or connections)",
+                            "value": 5
+                          },
+                          "S0D1": {
+                            "description": "Standard '0'. disconnect '1' (normally used for wired-and connections)",
+                            "value": 6
+                          },
+                          "H0D1": {
+                            "description": "High drive '0', disconnect '1' (normally used for wired-and connections)",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SENSE": {
+                    "description": "Pin sensing mechanism",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Sense for high level",
+                            "value": 2
+                          },
+                          "Low": {
+                            "description": "Sense for low level",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ACL": {
+        "description": "Access control lists"
+      },
+      "RADIO": {
+        "description": "2.4 GHz radio",
+        "children": {
+          "registers": {
+            "TASKS_TXEN": {
+              "description": "Enable RADIO in TX mode",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_TXEN": {
+                    "description": "Enable RADIO in TX mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_RXEN": {
+              "description": "Enable RADIO in RX mode",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_RXEN": {
+                    "description": "Enable RADIO in RX mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_START": {
+              "description": "Start RADIO",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Start RADIO",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stop RADIO",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop RADIO",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_DISABLE": {
+              "description": "Disable RADIO",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_DISABLE": {
+                    "description": "Disable RADIO",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_RSSISTART": {
+              "description": "Start the RSSI and take one single sample of the receive signal strength",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_RSSISTART": {
+                    "description": "Start the RSSI and take one single sample of the receive signal strength",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_RSSISTOP": {
+              "description": "Stop the RSSI measurement",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_RSSISTOP": {
+                    "description": "Stop the RSSI measurement",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_BCSTART": {
+              "description": "Start the bit counter",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_BCSTART": {
+                    "description": "Start the bit counter",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_BCSTOP": {
+              "description": "Stop the bit counter",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_BCSTOP": {
+                    "description": "Stop the bit counter",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_EDSTART": {
+              "description": "Start the energy detect measurement used in IEEE 802.15.4 mode",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_EDSTART": {
+                    "description": "Start the energy detect measurement used in IEEE 802.15.4 mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_EDSTOP": {
+              "description": "Stop the energy detect measurement",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_EDSTOP": {
+                    "description": "Stop the energy detect measurement",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_CCASTART": {
+              "description": "Start the clear channel assessment used in IEEE 802.15.4 mode",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CCASTART": {
+                    "description": "Start the clear channel assessment used in IEEE 802.15.4 mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_CCASTOP": {
+              "description": "Stop the clear channel assessment",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CCASTOP": {
+                    "description": "Stop the clear channel assessment",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_READY": {
+              "description": "RADIO has ramped up and is ready to be started",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_READY": {
+                    "description": "RADIO has ramped up and is ready to be started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ADDRESS": {
+              "description": "Address sent or received",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ADDRESS": {
+                    "description": "Address sent or received",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_PAYLOAD": {
+              "description": "Packet payload sent or received",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_PAYLOAD": {
+                    "description": "Packet payload sent or received",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_END": {
+              "description": "Packet sent or received",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_END": {
+                    "description": "Packet sent or received",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_DISABLED": {
+              "description": "RADIO has been disabled",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_DISABLED": {
+                    "description": "RADIO has been disabled",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_DEVMATCH": {
+              "description": "A device address match occurred on the last received packet",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_DEVMATCH": {
+                    "description": "A device address match occurred on the last received packet",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_DEVMISS": {
+              "description": "No device address match occurred on the last received packet",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_DEVMISS": {
+                    "description": "No device address match occurred on the last received packet",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RSSIEND": {
+              "description": "Sampling of receive signal strength complete",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RSSIEND": {
+                    "description": "Sampling of receive signal strength complete",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_BCMATCH": {
+              "description": "Bit counter reached bit count value",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_BCMATCH": {
+                    "description": "Bit counter reached bit count value",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CRCOK": {
+              "description": "Packet received with CRC ok",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CRCOK": {
+                    "description": "Packet received with CRC ok",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CRCERROR": {
+              "description": "Packet received with CRC error",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CRCERROR": {
+                    "description": "Packet received with CRC error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_FRAMESTART": {
+              "description": "IEEE 802.15.4 length field received",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_FRAMESTART": {
+                    "description": "IEEE 802.15.4 length field received",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_EDEND": {
+              "description": "Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_EDEND": {
+                    "description": "Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_EDSTOPPED": {
+              "description": "The sampling of energy detection has stopped",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_EDSTOPPED": {
+                    "description": "The sampling of energy detection has stopped",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CCAIDLE": {
+              "description": "Wireless medium in idle - clear to send",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CCAIDLE": {
+                    "description": "Wireless medium in idle - clear to send",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CCABUSY": {
+              "description": "Wireless medium busy - do not send",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CCABUSY": {
+                    "description": "Wireless medium busy - do not send",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CCASTOPPED": {
+              "description": "The CCA has stopped",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CCASTOPPED": {
+                    "description": "The CCA has stopped",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RATEBOOST": {
+              "description": "Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RATEBOOST": {
+                    "description": "Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TXREADY": {
+              "description": "RADIO has ramped up and is ready to be started TX path",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TXREADY": {
+                    "description": "RADIO has ramped up and is ready to be started TX path",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXREADY": {
+              "description": "RADIO has ramped up and is ready to be started RX path",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXREADY": {
+                    "description": "RADIO has ramped up and is ready to be started RX path",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_MHRMATCH": {
+              "description": "MAC header match found",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_MHRMATCH": {
+                    "description": "MAC header match found",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_SYNC": {
+              "description": "Preamble indicator.",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_SYNC": {
+                    "description": "Preamble indicator.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_PHYEND": {
+              "description": "Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air.",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_PHYEND": {
+                    "description": "Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY_START": {
+                    "description": "Shortcut between event READY and task START",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END_DISABLE": {
+                    "description": "Shortcut between event END and task DISABLE",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISABLED_TXEN": {
+                    "description": "Shortcut between event DISABLED and task TXEN",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISABLED_RXEN": {
+                    "description": "Shortcut between event DISABLED and task RXEN",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDRESS_RSSISTART": {
+                    "description": "Shortcut between event ADDRESS and task RSSISTART",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END_START": {
+                    "description": "Shortcut between event END and task START",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDRESS_BCSTART": {
+                    "description": "Shortcut between event ADDRESS and task BCSTART",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISABLED_RSSISTOP": {
+                    "description": "Shortcut between event DISABLED and task RSSISTOP",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXREADY_CCASTART": {
+                    "description": "Shortcut between event RXREADY and task CCASTART",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCAIDLE_TXEN": {
+                    "description": "Shortcut between event CCAIDLE and task TXEN",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCABUSY_DISABLE": {
+                    "description": "Shortcut between event CCABUSY and task DISABLE",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FRAMESTART_BCSTART": {
+                    "description": "Shortcut between event FRAMESTART and task BCSTART",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READY_EDSTART": {
+                    "description": "Shortcut between event READY and task EDSTART",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EDEND_DISABLE": {
+                    "description": "Shortcut between event EDEND and task DISABLE",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCAIDLE_STOP": {
+                    "description": "Shortcut between event CCAIDLE and task STOP",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXREADY_START": {
+                    "description": "Shortcut between event TXREADY and task START",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXREADY_START": {
+                    "description": "Shortcut between event RXREADY and task START",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PHYEND_DISABLE": {
+                    "description": "Shortcut between event PHYEND and task DISABLE",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PHYEND_START": {
+                    "description": "Shortcut between event PHYEND and task START",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to enable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDRESS": {
+                    "description": "Write '1' to enable interrupt for event ADDRESS",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PAYLOAD": {
+                    "description": "Write '1' to enable interrupt for event PAYLOAD",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to enable interrupt for event END",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISABLED": {
+                    "description": "Write '1' to enable interrupt for event DISABLED",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DEVMATCH": {
+                    "description": "Write '1' to enable interrupt for event DEVMATCH",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DEVMISS": {
+                    "description": "Write '1' to enable interrupt for event DEVMISS",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RSSIEND": {
+                    "description": "Write '1' to enable interrupt for event RSSIEND",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BCMATCH": {
+                    "description": "Write '1' to enable interrupt for event BCMATCH",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CRCOK": {
+                    "description": "Write '1' to enable interrupt for event CRCOK",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CRCERROR": {
+                    "description": "Write '1' to enable interrupt for event CRCERROR",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FRAMESTART": {
+                    "description": "Write '1' to enable interrupt for event FRAMESTART",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EDEND": {
+                    "description": "Write '1' to enable interrupt for event EDEND",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EDSTOPPED": {
+                    "description": "Write '1' to enable interrupt for event EDSTOPPED",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCAIDLE": {
+                    "description": "Write '1' to enable interrupt for event CCAIDLE",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCABUSY": {
+                    "description": "Write '1' to enable interrupt for event CCABUSY",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCASTOPPED": {
+                    "description": "Write '1' to enable interrupt for event CCASTOPPED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RATEBOOST": {
+                    "description": "Write '1' to enable interrupt for event RATEBOOST",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXREADY": {
+                    "description": "Write '1' to enable interrupt for event TXREADY",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXREADY": {
+                    "description": "Write '1' to enable interrupt for event RXREADY",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MHRMATCH": {
+                    "description": "Write '1' to enable interrupt for event MHRMATCH",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SYNC": {
+                    "description": "Write '1' to enable interrupt for event SYNC",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PHYEND": {
+                    "description": "Write '1' to enable interrupt for event PHYEND",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to disable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDRESS": {
+                    "description": "Write '1' to disable interrupt for event ADDRESS",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PAYLOAD": {
+                    "description": "Write '1' to disable interrupt for event PAYLOAD",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to disable interrupt for event END",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISABLED": {
+                    "description": "Write '1' to disable interrupt for event DISABLED",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DEVMATCH": {
+                    "description": "Write '1' to disable interrupt for event DEVMATCH",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DEVMISS": {
+                    "description": "Write '1' to disable interrupt for event DEVMISS",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RSSIEND": {
+                    "description": "Write '1' to disable interrupt for event RSSIEND",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BCMATCH": {
+                    "description": "Write '1' to disable interrupt for event BCMATCH",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CRCOK": {
+                    "description": "Write '1' to disable interrupt for event CRCOK",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CRCERROR": {
+                    "description": "Write '1' to disable interrupt for event CRCERROR",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FRAMESTART": {
+                    "description": "Write '1' to disable interrupt for event FRAMESTART",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EDEND": {
+                    "description": "Write '1' to disable interrupt for event EDEND",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EDSTOPPED": {
+                    "description": "Write '1' to disable interrupt for event EDSTOPPED",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCAIDLE": {
+                    "description": "Write '1' to disable interrupt for event CCAIDLE",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCABUSY": {
+                    "description": "Write '1' to disable interrupt for event CCABUSY",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCASTOPPED": {
+                    "description": "Write '1' to disable interrupt for event CCASTOPPED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RATEBOOST": {
+                    "description": "Write '1' to disable interrupt for event RATEBOOST",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXREADY": {
+                    "description": "Write '1' to disable interrupt for event TXREADY",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXREADY": {
+                    "description": "Write '1' to disable interrupt for event RXREADY",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MHRMATCH": {
+                    "description": "Write '1' to disable interrupt for event MHRMATCH",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SYNC": {
+                    "description": "Write '1' to disable interrupt for event SYNC",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PHYEND": {
+                    "description": "Write '1' to disable interrupt for event PHYEND",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CRCSTATUS": {
+              "description": "CRC status",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CRCSTATUS": {
+                    "description": "CRC status of packet received",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "CRCError": {
+                            "description": "Packet received with CRC error",
+                            "value": 0
+                          },
+                          "CRCOk": {
+                            "description": "Packet received with CRC ok",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RXMATCH": {
+              "description": "Received address",
+              "offset": 1032,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXMATCH": {
+                    "description": "Received address",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "RXCRC": {
+              "description": "CRC field of previously received packet",
+              "offset": 1036,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXCRC": {
+                    "description": "CRC field of previously received packet",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "DAI": {
+              "description": "Device address match index",
+              "offset": 1040,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DAI": {
+                    "description": "Device address match index",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "PDUSTAT": {
+              "description": "Payload status",
+              "offset": 1044,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PDUSTAT": {
+                    "description": "Status on payload length vs. PCNF1.MAXLEN",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LessThan": {
+                            "description": "Payload less than PCNF1.MAXLEN",
+                            "value": 0
+                          },
+                          "GreaterThan": {
+                            "description": "Payload greater than PCNF1.MAXLEN",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CISTAT": {
+                    "description": "Status on what rate packet is received with in Long Range",
+                    "offset": 1,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "LR125kbit": {
+                            "description": "Frame is received at 125kbps",
+                            "value": 0
+                          },
+                          "LR500kbit": {
+                            "description": "Frame is received at 500kbps",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PACKETPTR": {
+              "description": "Packet pointer",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PACKETPTR": {
+                    "description": "Packet pointer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FREQUENCY": {
+              "description": "Frequency",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQUENCY": {
+                    "description": "Radio channel frequency",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "MAP": {
+                    "description": "Channel map selection.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Default": {
+                            "description": "Channel map between 2400 MHZ .. 2500 MHz",
+                            "value": 0
+                          },
+                          "Low": {
+                            "description": "Channel map between 2360 MHZ .. 2460 MHz",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TXPOWER": {
+              "description": "Output power",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXPOWER": {
+                    "description": "RADIO output power",
+                    "offset": 0,
+                    "size": 8,
+                    "enum": {
+                      "size": 8,
+                      "children": {
+                        "enum_fields": {
+                          "Pos8dBm": {
+                            "description": "+8 dBm",
+                            "value": 8
+                          },
+                          "Pos7dBm": {
+                            "description": "+7 dBm",
+                            "value": 7
+                          },
+                          "Pos6dBm": {
+                            "description": "+6 dBm",
+                            "value": 6
+                          },
+                          "Pos5dBm": {
+                            "description": "+5 dBm",
+                            "value": 5
+                          },
+                          "Pos4dBm": {
+                            "description": "+4 dBm",
+                            "value": 4
+                          },
+                          "Pos3dBm": {
+                            "description": "+3 dBm",
+                            "value": 3
+                          },
+                          "Pos2dBm": {
+                            "description": "+2 dBm",
+                            "value": 2
+                          },
+                          "0dBm": {
+                            "description": "0 dBm",
+                            "value": 0
+                          },
+                          "Neg4dBm": {
+                            "description": "-4 dBm",
+                            "value": 252
+                          },
+                          "Neg8dBm": {
+                            "description": "-8 dBm",
+                            "value": 248
+                          },
+                          "Neg12dBm": {
+                            "description": "-12 dBm",
+                            "value": 244
+                          },
+                          "Neg16dBm": {
+                            "description": "-16 dBm",
+                            "value": 240
+                          },
+                          "Neg20dBm": {
+                            "description": "-20 dBm",
+                            "value": 236
+                          },
+                          "Neg30dBm": {
+                            "description": "Deprecated enumerator -  -40 dBm",
+                            "value": 226
+                          },
+                          "Neg40dBm": {
+                            "description": "-40 dBm",
+                            "value": 216
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Data rate and modulation",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation.",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Nrf_1Mbit": {
+                            "description": "1 Mbit/s Nordic proprietary radio mode",
+                            "value": 0
+                          },
+                          "Nrf_2Mbit": {
+                            "description": "2 Mbit/s Nordic proprietary radio mode",
+                            "value": 1
+                          },
+                          "Ble_1Mbit": {
+                            "description": "1 Mbit/s BLE",
+                            "value": 3
+                          },
+                          "Ble_2Mbit": {
+                            "description": "2 Mbit/s BLE",
+                            "value": 4
+                          },
+                          "Ble_LR125Kbit": {
+                            "description": "Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX",
+                            "value": 5
+                          },
+                          "Ble_LR500Kbit": {
+                            "description": "Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX",
+                            "value": 6
+                          },
+                          "Ieee802154_250Kbit": {
+                            "description": "IEEE 802.15.4-2006 250 kbit/s",
+                            "value": 15
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PCNF0": {
+              "description": "Packet configuration register 0",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LFLEN": {
+                    "description": "Length on air of LENGTH field in number of bits.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "S0LEN": {
+                    "description": "Length on air of S0 field in number of bytes.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "S1LEN": {
+                    "description": "Length on air of S1 field in number of bits.",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "S1INCL": {
+                    "description": "Include or exclude S1 field in RAM",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Automatic": {
+                            "description": "Include S1 field in RAM only if S1LEN > 0",
+                            "value": 0
+                          },
+                          "Include": {
+                            "description": "Always include S1 field in RAM independent of S1LEN",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CILEN": {
+                    "description": "Length of code indicator - long range",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "PLEN": {
+                    "description": "Length of preamble on air. Decision point: TASKS_START task",
+                    "offset": 24,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "8bit": {
+                            "description": "8-bit preamble",
+                            "value": 0
+                          },
+                          "16bit": {
+                            "description": "16-bit preamble",
+                            "value": 1
+                          },
+                          "32bitZero": {
+                            "description": "32-bit zero preamble - used for IEEE 802.15.4",
+                            "value": 2
+                          },
+                          "LongRange": {
+                            "description": "Preamble - used for BLE long range",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CRCINC": {
+                    "description": "Indicates if LENGTH field contains CRC or not",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Exclude": {
+                            "description": "LENGTH does not contain CRC",
+                            "value": 0
+                          },
+                          "Include": {
+                            "description": "LENGTH includes CRC",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TERMLEN": {
+                    "description": "Length of TERM field in Long Range operation",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PCNF1": {
+              "description": "Packet configuration register 1",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAXLEN": {
+                    "description": "Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "STATLEN": {
+                    "description": "Static length in number of bytes",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BALEN": {
+                    "description": "Base address length in number of bytes",
+                    "offset": 16,
+                    "size": 3
+                  },
+                  "ENDIAN": {
+                    "description": "On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Little": {
+                            "description": "Least significant bit on air first",
+                            "value": 0
+                          },
+                          "Big": {
+                            "description": "Most significant bit on air first",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WHITEEN": {
+                    "description": "Enable or disable packet whitening",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "BASE0": {
+              "description": "Base address 0",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BASE0": {
+                    "description": "Base address 0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BASE1": {
+              "description": "Base address 1",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BASE1": {
+                    "description": "Base address 1",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PREFIX0": {
+              "description": "Prefixes bytes for logical addresses 0-3",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AP0": {
+                    "description": "Address prefix 0.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "AP1": {
+                    "description": "Address prefix 1.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "AP2": {
+                    "description": "Address prefix 2.",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "AP3": {
+                    "description": "Address prefix 3.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PREFIX1": {
+              "description": "Prefixes bytes for logical addresses 4-7",
+              "offset": 1320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AP4": {
+                    "description": "Address prefix 4.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "AP5": {
+                    "description": "Address prefix 5.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "AP6": {
+                    "description": "Address prefix 6.",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "AP7": {
+                    "description": "Address prefix 7.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXADDRESS": {
+              "description": "Transmit address select",
+              "offset": 1324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXADDRESS": {
+                    "description": "Transmit address select",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "RXADDRESSES": {
+              "description": "Receive address select",
+              "offset": 1328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDR0": {
+                    "description": "Enable or disable reception on logical address 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR1": {
+                    "description": "Enable or disable reception on logical address 1.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR2": {
+                    "description": "Enable or disable reception on logical address 2.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR3": {
+                    "description": "Enable or disable reception on logical address 3.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR4": {
+                    "description": "Enable or disable reception on logical address 4.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR5": {
+                    "description": "Enable or disable reception on logical address 5.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR6": {
+                    "description": "Enable or disable reception on logical address 6.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR7": {
+                    "description": "Enable or disable reception on logical address 7.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CRCCNF": {
+              "description": "CRC configuration",
+              "offset": 1332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEN": {
+                    "description": "CRC length in number of bytes.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "CRC length is zero and CRC calculation is disabled",
+                            "value": 0
+                          },
+                          "One": {
+                            "description": "CRC length is one byte and CRC calculation is enabled",
+                            "value": 1
+                          },
+                          "Two": {
+                            "description": "CRC length is two bytes and CRC calculation is enabled",
+                            "value": 2
+                          },
+                          "Three": {
+                            "description": "CRC length is three bytes and CRC calculation is enabled",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SKIPADDR": {
+                    "description": "Include or exclude packet address field out of CRC calculation.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Include": {
+                            "description": "CRC calculation includes address field",
+                            "value": 0
+                          },
+                          "Skip": {
+                            "description": "CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.",
+                            "value": 1
+                          },
+                          "Ieee802154": {
+                            "description": "CRC calculation as per 802.15.4 standard. Starting at first byte after length field.",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CRCPOLY": {
+              "description": "CRC polynomial",
+              "offset": 1336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRCPOLY": {
+                    "description": "CRC polynomial",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "CRCINIT": {
+              "description": "CRC initial value",
+              "offset": 1340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRCINIT": {
+                    "description": "CRC initial value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "TIFS": {
+              "description": "Interframe spacing in us",
+              "offset": 1348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIFS": {
+                    "description": "Interframe spacing in us",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "RSSISAMPLE": {
+              "description": "RSSI sample",
+              "offset": 1352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RSSISAMPLE": {
+                    "description": "RSSI sample",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "STATE": {
+              "description": "Current radio state",
+              "offset": 1360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STATE": {
+                    "description": "Current radio state",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "RADIO is in the Disabled state",
+                            "value": 0
+                          },
+                          "RxRu": {
+                            "description": "RADIO is in the RXRU state",
+                            "value": 1
+                          },
+                          "RxIdle": {
+                            "description": "RADIO is in the RXIDLE state",
+                            "value": 2
+                          },
+                          "Rx": {
+                            "description": "RADIO is in the RX state",
+                            "value": 3
+                          },
+                          "RxDisable": {
+                            "description": "RADIO is in the RXDISABLED state",
+                            "value": 4
+                          },
+                          "TxRu": {
+                            "description": "RADIO is in the TXRU state",
+                            "value": 9
+                          },
+                          "TxIdle": {
+                            "description": "RADIO is in the TXIDLE state",
+                            "value": 10
+                          },
+                          "Tx": {
+                            "description": "RADIO is in the TX state",
+                            "value": 11
+                          },
+                          "TxDisable": {
+                            "description": "RADIO is in the TXDISABLED state",
+                            "value": 12
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DATAWHITEIV": {
+              "description": "Data whitening initial value",
+              "offset": 1364,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATAWHITEIV": {
+                    "description": "Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "BCC": {
+              "description": "Bit counter compare",
+              "offset": 1376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BCC": {
+                    "description": "Bit counter compare",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DAB": {
+              "description": "Description collection: Device address base segment n",
+              "offset": 1536,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAB": {
+                    "description": "Device address base segment n",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DAP": {
+              "description": "Description collection: Device address prefix n",
+              "offset": 1568,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAP": {
+                    "description": "Device address prefix n",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DACNF": {
+              "description": "Device address match configuration",
+              "offset": 1600,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENA0": {
+                    "description": "Enable or disable device address matching using device address 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA1": {
+                    "description": "Enable or disable device address matching using device address 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA2": {
+                    "description": "Enable or disable device address matching using device address 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA3": {
+                    "description": "Enable or disable device address matching using device address 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA4": {
+                    "description": "Enable or disable device address matching using device address 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA5": {
+                    "description": "Enable or disable device address matching using device address 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA6": {
+                    "description": "Enable or disable device address matching using device address 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA7": {
+                    "description": "Enable or disable device address matching using device address 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXADD0": {
+                    "description": "TxAdd for device address 0",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXADD1": {
+                    "description": "TxAdd for device address 1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TXADD2": {
+                    "description": "TxAdd for device address 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TXADD3": {
+                    "description": "TxAdd for device address 3",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TXADD4": {
+                    "description": "TxAdd for device address 4",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TXADD5": {
+                    "description": "TxAdd for device address 5",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TXADD6": {
+                    "description": "TxAdd for device address 6",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TXADD7": {
+                    "description": "TxAdd for device address 7",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MHRMATCHCONF": {
+              "description": "Search pattern configuration",
+              "offset": 1604,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MHRMATCHCONF": {
+                    "description": "Search pattern configuration",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MHRMATCHMAS": {
+              "description": "Pattern mask",
+              "offset": 1608,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MHRMATCHMAS": {
+                    "description": "Pattern mask",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MODECNF0": {
+              "description": "Radio mode configuration register 0",
+              "offset": 1616,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RU": {
+                    "description": "Radio ramp-up time",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Default": {
+                            "description": "Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51",
+                            "value": 0
+                          },
+                          "Fast": {
+                            "description": "Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DTX": {
+                    "description": "Default TX value",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "B1": {
+                            "description": "Transmit '1'",
+                            "value": 0
+                          },
+                          "B0": {
+                            "description": "Transmit '0'",
+                            "value": 1
+                          },
+                          "Center": {
+                            "description": "Transmit center frequency",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SFD": {
+              "description": "IEEE 802.15.4 start of frame delimiter",
+              "offset": 1632,
+              "size": 32,
+              "reset_value": 167,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SFD": {
+                    "description": "IEEE 802.15.4 start of frame delimiter",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "EDCNT": {
+              "description": "IEEE 802.15.4 energy detect loop count",
+              "offset": 1636,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EDCNT": {
+                    "description": "IEEE 802.15.4 energy detect loop count",
+                    "offset": 0,
+                    "size": 21
+                  }
+                }
+              }
+            },
+            "EDSAMPLE": {
+              "description": "IEEE 802.15.4 energy detect level",
+              "offset": 1640,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EDLVL": {
+                    "description": "IEEE 802.15.4 energy detect level",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CCACTRL": {
+              "description": "IEEE 802.15.4 clear channel assessment control",
+              "offset": 1644,
+              "size": 32,
+              "reset_value": 86835200,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCAMODE": {
+                    "description": "CCA mode of operation",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "EdMode": {
+                            "description": "Energy above threshold",
+                            "value": 0
+                          },
+                          "CarrierMode": {
+                            "description": "Carrier seen",
+                            "value": 1
+                          },
+                          "CarrierAndEdMode": {
+                            "description": "Energy above threshold AND carrier seen",
+                            "value": 2
+                          },
+                          "CarrierOrEdMode": {
+                            "description": "Energy above threshold OR carrier seen",
+                            "value": 3
+                          },
+                          "EdModeTest1": {
+                            "description": "Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging.",
+                            "value": 4
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCAEDTHRES": {
+                    "description": "CCA energy busy threshold. Used in all the CCA modes except CarrierMode.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "CCACORRTHRES": {
+                    "description": "CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode.",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "CCACORRCNT": {
+                    "description": "Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "POWER": {
+              "description": "Peripheral power control",
+              "offset": 4092,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POWER": {
+                    "description": "Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Peripheral is powered off",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Peripheral is powered on",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UART0": {
+        "description": "Universal Asynchronous Receiver/Transmitter",
+        "children": {
+          "registers": {
+            "TASKS_STARTRX": {
+              "description": "Start UART receiver",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTRX": {
+                    "description": "Start UART receiver",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOPRX": {
+              "description": "Stop UART receiver",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOPRX": {
+                    "description": "Stop UART receiver",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STARTTX": {
+              "description": "Start UART transmitter",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTTX": {
+                    "description": "Start UART transmitter",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOPTX": {
+              "description": "Stop UART transmitter",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOPTX": {
+                    "description": "Stop UART transmitter",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SUSPEND": {
+              "description": "Suspend UART",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SUSPEND": {
+                    "description": "Suspend UART",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CTS": {
+              "description": "CTS is activated (set low). Clear To Send.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CTS": {
+                    "description": "CTS is activated (set low). Clear To Send.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_NCTS": {
+              "description": "CTS is deactivated (set high). Not Clear To Send.",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_NCTS": {
+                    "description": "CTS is deactivated (set high). Not Clear To Send.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXDRDY": {
+              "description": "Data received in RXD",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXDRDY": {
+                    "description": "Data received in RXD",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TXDRDY": {
+              "description": "Data sent from TXD",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TXDRDY": {
+                    "description": "Data sent from TXD",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ERROR": {
+              "description": "Error detected",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ERROR": {
+                    "description": "Error detected",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXTO": {
+              "description": "Receiver timeout",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXTO": {
+                    "description": "Receiver timeout",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS_STARTRX": {
+                    "description": "Shortcut between event CTS and task STARTRX",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS_STOPRX": {
+                    "description": "Shortcut between event NCTS and task STOPRX",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "Write '1' to enable interrupt for event CTS",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS": {
+                    "description": "Write '1' to enable interrupt for event NCTS",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDRDY": {
+                    "description": "Write '1' to enable interrupt for event RXDRDY",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDRDY": {
+                    "description": "Write '1' to enable interrupt for event TXDRDY",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to enable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXTO": {
+                    "description": "Write '1' to enable interrupt for event RXTO",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "Write '1' to disable interrupt for event CTS",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS": {
+                    "description": "Write '1' to disable interrupt for event NCTS",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDRDY": {
+                    "description": "Write '1' to disable interrupt for event RXDRDY",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDRDY": {
+                    "description": "Write '1' to disable interrupt for event TXDRDY",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to disable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXTO": {
+                    "description": "Write '1' to disable interrupt for event RXTO",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSRC": {
+              "description": "Error source",
+              "offset": 1152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERRUN": {
+                    "description": "Overrun error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PARITY": {
+                    "description": "Parity error",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FRAMING": {
+                    "description": "Framing error occurred",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BREAK": {
+                    "description": "Break condition",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable UART",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable UART",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable UART",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable UART",
+                            "value": 4
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RXD": {
+              "description": "RXD register",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXD": {
+                    "description": "RX data received in previous transfers, double buffered",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXD": {
+              "description": "TXD register",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TXD": {
+                    "description": "TX data to be transferred",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BAUDRATE": {
+              "description": "Baud rate. Accuracy depends on the HFCLK source selected.",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BAUDRATE": {
+                    "description": "Baud rate",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Baud1200": {
+                            "description": "1200 baud (actual rate: 1205)",
+                            "value": 323584
+                          },
+                          "Baud2400": {
+                            "description": "2400 baud (actual rate: 2396)",
+                            "value": 643072
+                          },
+                          "Baud4800": {
+                            "description": "4800 baud (actual rate: 4808)",
+                            "value": 1290240
+                          },
+                          "Baud9600": {
+                            "description": "9600 baud (actual rate: 9598)",
+                            "value": 2576384
+                          },
+                          "Baud14400": {
+                            "description": "14400 baud (actual rate: 14414)",
+                            "value": 3866624
+                          },
+                          "Baud19200": {
+                            "description": "19200 baud (actual rate: 19208)",
+                            "value": 5152768
+                          },
+                          "Baud28800": {
+                            "description": "28800 baud (actual rate: 28829)",
+                            "value": 7729152
+                          },
+                          "Baud31250": {
+                            "description": "31250 baud",
+                            "value": 8388608
+                          },
+                          "Baud38400": {
+                            "description": "38400 baud (actual rate: 38462)",
+                            "value": 10309632
+                          },
+                          "Baud56000": {
+                            "description": "56000 baud (actual rate: 55944)",
+                            "value": 15007744
+                          },
+                          "Baud57600": {
+                            "description": "57600 baud (actual rate: 57762)",
+                            "value": 15462400
+                          },
+                          "Baud76800": {
+                            "description": "76800 baud (actual rate: 76923)",
+                            "value": 20615168
+                          },
+                          "Baud115200": {
+                            "description": "115200 baud (actual rate: 115942)",
+                            "value": 30924800
+                          },
+                          "Baud230400": {
+                            "description": "230400 baud (actual rate: 231884)",
+                            "value": 61845504
+                          },
+                          "Baud250000": {
+                            "description": "250000 baud",
+                            "value": 67108864
+                          },
+                          "Baud460800": {
+                            "description": "460800 baud (actual rate: 470588)",
+                            "value": 123695104
+                          },
+                          "Baud921600": {
+                            "description": "921600 baud (actual rate: 941176)",
+                            "value": 247386112
+                          },
+                          "Baud1M": {
+                            "description": "1Mega baud",
+                            "value": 268435456
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration of parity and hardware flow control",
+              "offset": 1388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HWFC": {
+                    "description": "Hardware flow control",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PARITY": {
+                    "description": "Parity",
+                    "offset": 1,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude parity bit",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include parity bit",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOP": {
+                    "description": "Stop bits",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "One": {
+                            "description": "One stop bit",
+                            "value": 0
+                          },
+                          "Two": {
+                            "description": "Two stop bits",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UARTE0": {
+        "description": "UART with EasyDMA 0",
+        "children": {
+          "registers": {
+            "TASKS_STARTRX": {
+              "description": "Start UART receiver",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTRX": {
+                    "description": "Start UART receiver",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOPRX": {
+              "description": "Stop UART receiver",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOPRX": {
+                    "description": "Stop UART receiver",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STARTTX": {
+              "description": "Start UART transmitter",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTTX": {
+                    "description": "Start UART transmitter",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOPTX": {
+              "description": "Stop UART transmitter",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOPTX": {
+                    "description": "Stop UART transmitter",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_FLUSHRX": {
+              "description": "Flush RX FIFO into RX buffer",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_FLUSHRX": {
+                    "description": "Flush RX FIFO into RX buffer",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CTS": {
+              "description": "CTS is activated (set low). Clear To Send.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CTS": {
+                    "description": "CTS is activated (set low). Clear To Send.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_NCTS": {
+              "description": "CTS is deactivated (set high). Not Clear To Send.",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_NCTS": {
+                    "description": "CTS is deactivated (set high). Not Clear To Send.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXDRDY": {
+              "description": "Data received in RXD (but potentially not yet transferred to Data RAM)",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXDRDY": {
+                    "description": "Data received in RXD (but potentially not yet transferred to Data RAM)",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDRX": {
+              "description": "Receive buffer is filled up",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDRX": {
+                    "description": "Receive buffer is filled up",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TXDRDY": {
+              "description": "Data sent from TXD",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TXDRDY": {
+                    "description": "Data sent from TXD",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDTX": {
+              "description": "Last TX byte transmitted",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDTX": {
+                    "description": "Last TX byte transmitted",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ERROR": {
+              "description": "Error detected",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ERROR": {
+                    "description": "Error detected",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXTO": {
+              "description": "Receiver timeout",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXTO": {
+                    "description": "Receiver timeout",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXSTARTED": {
+              "description": "UART receiver has started",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXSTARTED": {
+                    "description": "UART receiver has started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TXSTARTED": {
+              "description": "UART transmitter has started",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TXSTARTED": {
+                    "description": "UART transmitter has started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TXSTOPPED": {
+              "description": "Transmitter stopped",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TXSTOPPED": {
+                    "description": "Transmitter stopped",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDRX_STARTRX": {
+                    "description": "Shortcut between event ENDRX and task STARTRX",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX_STOPRX": {
+                    "description": "Shortcut between event ENDRX and task STOPRX",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "Enable or disable interrupt for event CTS",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS": {
+                    "description": "Enable or disable interrupt for event NCTS",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDRDY": {
+                    "description": "Enable or disable interrupt for event RXDRDY",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Enable or disable interrupt for event ENDRX",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDRDY": {
+                    "description": "Enable or disable interrupt for event TXDRDY",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Enable or disable interrupt for event ENDTX",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Enable or disable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXTO": {
+                    "description": "Enable or disable interrupt for event RXTO",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Enable or disable interrupt for event RXSTARTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Enable or disable interrupt for event TXSTARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTOPPED": {
+                    "description": "Enable or disable interrupt for event TXSTOPPED",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "Write '1' to enable interrupt for event CTS",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS": {
+                    "description": "Write '1' to enable interrupt for event NCTS",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDRDY": {
+                    "description": "Write '1' to enable interrupt for event RXDRDY",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to enable interrupt for event ENDRX",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDRDY": {
+                    "description": "Write '1' to enable interrupt for event TXDRDY",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to enable interrupt for event ENDTX",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to enable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXTO": {
+                    "description": "Write '1' to enable interrupt for event RXTO",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to enable interrupt for event RXSTARTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to enable interrupt for event TXSTARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTOPPED": {
+                    "description": "Write '1' to enable interrupt for event TXSTOPPED",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "Write '1' to disable interrupt for event CTS",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NCTS": {
+                    "description": "Write '1' to disable interrupt for event NCTS",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDRDY": {
+                    "description": "Write '1' to disable interrupt for event RXDRDY",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to disable interrupt for event ENDRX",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDRDY": {
+                    "description": "Write '1' to disable interrupt for event TXDRDY",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to disable interrupt for event ENDTX",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to disable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXTO": {
+                    "description": "Write '1' to disable interrupt for event RXTO",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to disable interrupt for event RXSTARTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to disable interrupt for event TXSTARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTOPPED": {
+                    "description": "Write '1' to disable interrupt for event TXSTOPPED",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSRC": {
+              "description": "Error source Note : this register is read / write one to clear.",
+              "offset": 1152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERRUN": {
+                    "description": "Overrun error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PARITY": {
+                    "description": "Parity error",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FRAMING": {
+                    "description": "Framing error occurred",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BREAK": {
+                    "description": "Break condition",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable UART",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable UARTE",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable UARTE",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable UARTE",
+                            "value": 8
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "BAUDRATE": {
+              "description": "Baud rate. Accuracy depends on the HFCLK source selected.",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BAUDRATE": {
+                    "description": "Baud rate",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Baud1200": {
+                            "description": "1200 baud (actual rate: 1205)",
+                            "value": 323584
+                          },
+                          "Baud2400": {
+                            "description": "2400 baud (actual rate: 2396)",
+                            "value": 643072
+                          },
+                          "Baud4800": {
+                            "description": "4800 baud (actual rate: 4808)",
+                            "value": 1290240
+                          },
+                          "Baud9600": {
+                            "description": "9600 baud (actual rate: 9598)",
+                            "value": 2576384
+                          },
+                          "Baud14400": {
+                            "description": "14400 baud (actual rate: 14401)",
+                            "value": 3862528
+                          },
+                          "Baud19200": {
+                            "description": "19200 baud (actual rate: 19208)",
+                            "value": 5152768
+                          },
+                          "Baud28800": {
+                            "description": "28800 baud (actual rate: 28777)",
+                            "value": 7716864
+                          },
+                          "Baud31250": {
+                            "description": "31250 baud",
+                            "value": 8388608
+                          },
+                          "Baud38400": {
+                            "description": "38400 baud (actual rate: 38369)",
+                            "value": 10289152
+                          },
+                          "Baud56000": {
+                            "description": "56000 baud (actual rate: 55944)",
+                            "value": 15007744
+                          },
+                          "Baud57600": {
+                            "description": "57600 baud (actual rate: 57554)",
+                            "value": 15400960
+                          },
+                          "Baud76800": {
+                            "description": "76800 baud (actual rate: 76923)",
+                            "value": 20615168
+                          },
+                          "Baud115200": {
+                            "description": "115200 baud (actual rate: 115108)",
+                            "value": 30801920
+                          },
+                          "Baud230400": {
+                            "description": "230400 baud (actual rate: 231884)",
+                            "value": 61865984
+                          },
+                          "Baud250000": {
+                            "description": "250000 baud",
+                            "value": 67108864
+                          },
+                          "Baud460800": {
+                            "description": "460800 baud (actual rate: 457143)",
+                            "value": 121634816
+                          },
+                          "Baud921600": {
+                            "description": "921600 baud (actual rate: 941176)",
+                            "value": 251658240
+                          },
+                          "Baud1M": {
+                            "description": "1Mega baud",
+                            "value": 268435456
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration of parity and hardware flow control",
+              "offset": 1388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HWFC": {
+                    "description": "Hardware flow control",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PARITY": {
+                    "description": "Parity",
+                    "offset": 1,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude parity bit",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include even parity bit",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOP": {
+                    "description": "Stop bits",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "One": {
+                            "description": "One stop bit",
+                            "value": 0
+                          },
+                          "Two": {
+                            "description": "Two stop bits",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI0": {
+        "description": "Serial Peripheral Interface 0",
+        "children": {
+          "registers": {
+            "EVENTS_READY": {
+              "description": "TXD byte sent and RXD byte received",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_READY": {
+                    "description": "TXD byte sent and RXD byte received",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to enable interrupt for event READY",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to disable interrupt for event READY",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable SPI",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable SPI",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable SPI",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable SPI",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RXD": {
+              "description": "RXD register",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXD": {
+                    "description": "RX data received. Double buffered",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXD": {
+              "description": "TXD register",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXD": {
+                    "description": "TX data to send. Double buffered",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "FREQUENCY": {
+              "description": "SPI frequency. Accuracy depends on the HFCLK source selected.",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQUENCY": {
+                    "description": "SPI master data rate",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "K125": {
+                            "description": "125 kbps",
+                            "value": 33554432
+                          },
+                          "K250": {
+                            "description": "250 kbps",
+                            "value": 67108864
+                          },
+                          "K500": {
+                            "description": "500 kbps",
+                            "value": 134217728
+                          },
+                          "M1": {
+                            "description": "1 Mbps",
+                            "value": 268435456
+                          },
+                          "M2": {
+                            "description": "2 Mbps",
+                            "value": 536870912
+                          },
+                          "M4": {
+                            "description": "4 Mbps",
+                            "value": 1073741824
+                          },
+                          "M8": {
+                            "description": "8 Mbps",
+                            "value": 2147483648
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORDER": {
+                    "description": "Bit order",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MsbFirst": {
+                            "description": "Most significant bit shifted out first",
+                            "value": 0
+                          },
+                          "LsbFirst": {
+                            "description": "Least significant bit shifted out first",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPHA": {
+                    "description": "Serial clock (SCK) phase",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Leading": {
+                            "description": "Sample on leading edge of clock, shift serial data on trailing edge",
+                            "value": 0
+                          },
+                          "Trailing": {
+                            "description": "Sample on trailing edge of clock, shift serial data on leading edge",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPOL": {
+                    "description": "Serial clock (SCK) polarity",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ActiveHigh": {
+                            "description": "Active high",
+                            "value": 0
+                          },
+                          "ActiveLow": {
+                            "description": "Active low",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPIM0": {
+        "description": "Serial Peripheral Interface Master with EasyDMA 0",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start SPI transaction",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Start SPI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stop SPI transaction",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop SPI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SUSPEND": {
+              "description": "Suspend SPI transaction",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SUSPEND": {
+                    "description": "Suspend SPI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_RESUME": {
+              "description": "Resume SPI transaction",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_RESUME": {
+                    "description": "Resume SPI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STOPPED": {
+              "description": "SPI transaction has stopped",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STOPPED": {
+                    "description": "SPI transaction has stopped",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDRX": {
+              "description": "End of RXD buffer reached",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDRX": {
+                    "description": "End of RXD buffer reached",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_END": {
+              "description": "End of RXD buffer and TXD buffer reached",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_END": {
+                    "description": "End of RXD buffer and TXD buffer reached",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDTX": {
+              "description": "End of TXD buffer reached",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDTX": {
+                    "description": "End of TXD buffer reached",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STARTED": {
+              "description": "Transaction started",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STARTED": {
+                    "description": "Transaction started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END_START": {
+                    "description": "Shortcut between event END and task START",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to enable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to enable interrupt for event ENDRX",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to enable interrupt for event END",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to enable interrupt for event ENDTX",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Write '1' to enable interrupt for event STARTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to disable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to disable interrupt for event ENDRX",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to disable interrupt for event END",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to disable interrupt for event ENDTX",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Write '1' to disable interrupt for event STARTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "STALLSTAT": {
+              "description": "Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU.",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX": {
+                    "description": "Stall status for EasyDMA RAM reads",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NOSTALL": {
+                            "description": "No stall",
+                            "value": 0
+                          },
+                          "STALL": {
+                            "description": "A stall has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RX": {
+                    "description": "Stall status for EasyDMA RAM writes",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NOSTALL": {
+                            "description": "No stall",
+                            "value": 0
+                          },
+                          "STALL": {
+                            "description": "A stall has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable SPIM",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable SPIM",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable SPIM",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable SPIM",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FREQUENCY": {
+              "description": "SPI frequency. Accuracy depends on the HFCLK source selected.",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQUENCY": {
+                    "description": "SPI master data rate",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "K125": {
+                            "description": "125 kbps",
+                            "value": 33554432
+                          },
+                          "K250": {
+                            "description": "250 kbps",
+                            "value": 67108864
+                          },
+                          "K500": {
+                            "description": "500 kbps",
+                            "value": 134217728
+                          },
+                          "M1": {
+                            "description": "1 Mbps",
+                            "value": 268435456
+                          },
+                          "M2": {
+                            "description": "2 Mbps",
+                            "value": 536870912
+                          },
+                          "M4": {
+                            "description": "4 Mbps",
+                            "value": 1073741824
+                          },
+                          "M8": {
+                            "description": "8 Mbps",
+                            "value": 2147483648
+                          },
+                          "M16": {
+                            "description": "16 Mbps",
+                            "value": 167772160
+                          },
+                          "M32": {
+                            "description": "32 Mbps",
+                            "value": 335544320
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORDER": {
+                    "description": "Bit order",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MsbFirst": {
+                            "description": "Most significant bit shifted out first",
+                            "value": 0
+                          },
+                          "LsbFirst": {
+                            "description": "Least significant bit shifted out first",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPHA": {
+                    "description": "Serial clock (SCK) phase",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Leading": {
+                            "description": "Sample on leading edge of clock, shift serial data on trailing edge",
+                            "value": 0
+                          },
+                          "Trailing": {
+                            "description": "Sample on trailing edge of clock, shift serial data on leading edge",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPOL": {
+                    "description": "Serial clock (SCK) polarity",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ActiveHigh": {
+                            "description": "Active high",
+                            "value": 0
+                          },
+                          "ActiveLow": {
+                            "description": "Active low",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CSNPOL": {
+              "description": "Polarity of CSN output",
+              "offset": 1384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSNPOL": {
+                    "description": "Polarity of CSN output",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LOW": {
+                            "description": "Active low (idle state high)",
+                            "value": 0
+                          },
+                          "HIGH": {
+                            "description": "Active high (idle state low)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PSELDCX": {
+              "description": "Pin select for DCX signal",
+              "offset": 1388,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN": {
+                    "description": "Pin number",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "PORT": {
+                    "description": "Port number",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CONNECT": {
+                    "description": "Connection",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disconnected": {
+                            "description": "Disconnect",
+                            "value": 1
+                          },
+                          "Connected": {
+                            "description": "Connect",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DCXCNT": {
+              "description": "DCX configuration",
+              "offset": 1392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCXCNT": {
+                    "description": "This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "ORC": {
+              "description": "Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT",
+              "offset": 1472,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORC": {
+                    "description": "Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPIS0": {
+        "description": "SPI Slave 0",
+        "children": {
+          "registers": {
+            "TASKS_ACQUIRE": {
+              "description": "Acquire SPI semaphore",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_ACQUIRE": {
+                    "description": "Acquire SPI semaphore",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_RELEASE": {
+              "description": "Release SPI semaphore, enabling the SPI slave to acquire it",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_RELEASE": {
+                    "description": "Release SPI semaphore, enabling the SPI slave to acquire it",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_END": {
+              "description": "Granted transaction completed",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_END": {
+                    "description": "Granted transaction completed",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDRX": {
+              "description": "End of RXD buffer reached",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDRX": {
+                    "description": "End of RXD buffer reached",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ACQUIRED": {
+              "description": "Semaphore acquired",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ACQUIRED": {
+                    "description": "Semaphore acquired",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END_ACQUIRE": {
+                    "description": "Shortcut between event END and task ACQUIRE",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END": {
+                    "description": "Write '1' to enable interrupt for event END",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to enable interrupt for event ENDRX",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ACQUIRED": {
+                    "description": "Write '1' to enable interrupt for event ACQUIRED",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END": {
+                    "description": "Write '1' to disable interrupt for event END",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to disable interrupt for event ENDRX",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ACQUIRED": {
+                    "description": "Write '1' to disable interrupt for event ACQUIRED",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SEMSTAT": {
+              "description": "Semaphore status register",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SEMSTAT": {
+                    "description": "Semaphore status",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Free": {
+                            "description": "Semaphore is free",
+                            "value": 0
+                          },
+                          "CPU": {
+                            "description": "Semaphore is assigned to CPU",
+                            "value": 1
+                          },
+                          "SPIS": {
+                            "description": "Semaphore is assigned to SPI slave",
+                            "value": 2
+                          },
+                          "CPUPending": {
+                            "description": "Semaphore is assigned to SPI but a handover to the CPU is pending",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Status from last transaction",
+              "offset": 1088,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERREAD": {
+                    "description": "TX buffer over-read detected, and prevented",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVERFLOW": {
+                    "description": "RX buffer overflow detected, and prevented",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable SPI slave",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable SPI slave",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable SPI slave",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable SPI slave",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORDER": {
+                    "description": "Bit order",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MsbFirst": {
+                            "description": "Most significant bit shifted out first",
+                            "value": 0
+                          },
+                          "LsbFirst": {
+                            "description": "Least significant bit shifted out first",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPHA": {
+                    "description": "Serial clock (SCK) phase",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Leading": {
+                            "description": "Sample on leading edge of clock, shift serial data on trailing edge",
+                            "value": 0
+                          },
+                          "Trailing": {
+                            "description": "Sample on trailing edge of clock, shift serial data on leading edge",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPOL": {
+                    "description": "Serial clock (SCK) polarity",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ActiveHigh": {
+                            "description": "Active high",
+                            "value": 0
+                          },
+                          "ActiveLow": {
+                            "description": "Active low",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DEF": {
+              "description": "Default character. Character clocked out in case of an ignored transaction.",
+              "offset": 1372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DEF": {
+                    "description": "Default character. Character clocked out in case of an ignored transaction.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ORC": {
+              "description": "Over-read character",
+              "offset": 1472,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORC": {
+                    "description": "Over-read character. Character clocked out after an over-read of the transmit buffer.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TWI0": {
+        "description": "I2C compatible Two-Wire Interface 0",
+        "children": {
+          "registers": {
+            "TASKS_STARTRX": {
+              "description": "Start TWI receive sequence",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTRX": {
+                    "description": "Start TWI receive sequence",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STARTTX": {
+              "description": "Start TWI transmit sequence",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTTX": {
+                    "description": "Start TWI transmit sequence",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stop TWI transaction",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop TWI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SUSPEND": {
+              "description": "Suspend TWI transaction",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SUSPEND": {
+                    "description": "Suspend TWI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_RESUME": {
+              "description": "Resume TWI transaction",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_RESUME": {
+                    "description": "Resume TWI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STOPPED": {
+              "description": "TWI stopped",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STOPPED": {
+                    "description": "TWI stopped",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXDREADY": {
+              "description": "TWI RXD byte received",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXDREADY": {
+                    "description": "TWI RXD byte received",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TXDSENT": {
+              "description": "TWI TXD byte sent",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TXDSENT": {
+                    "description": "TWI TXD byte sent",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ERROR": {
+              "description": "TWI error",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ERROR": {
+                    "description": "TWI error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_BB": {
+              "description": "TWI byte boundary, generated before each byte that is sent or received",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_BB": {
+                    "description": "TWI byte boundary, generated before each byte that is sent or received",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_SUSPENDED": {
+              "description": "TWI entered the suspended state",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_SUSPENDED": {
+                    "description": "TWI entered the suspended state",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BB_SUSPEND": {
+                    "description": "Shortcut between event BB and task SUSPEND",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BB_STOP": {
+                    "description": "Shortcut between event BB and task STOP",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to enable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDREADY": {
+                    "description": "Write '1' to enable interrupt for event RXDREADY",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDSENT": {
+                    "description": "Write '1' to enable interrupt for event TXDSENT",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to enable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BB": {
+                    "description": "Write '1' to enable interrupt for event BB",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SUSPENDED": {
+                    "description": "Write '1' to enable interrupt for event SUSPENDED",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to disable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDREADY": {
+                    "description": "Write '1' to disable interrupt for event RXDREADY",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXDSENT": {
+                    "description": "Write '1' to disable interrupt for event TXDSENT",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to disable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BB": {
+                    "description": "Write '1' to disable interrupt for event BB",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SUSPENDED": {
+                    "description": "Write '1' to disable interrupt for event SUSPENDED",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSRC": {
+              "description": "Error source",
+              "offset": 1220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERRUN": {
+                    "description": "Overrun error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: no overrun occured",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: overrun occured",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ANACK": {
+                    "description": "NACK received after sending the address (write '1' to clear)",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DNACK": {
+                    "description": "NACK received after sending a data byte (write '1' to clear)",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotPresent": {
+                            "description": "Read: error not present",
+                            "value": 0
+                          },
+                          "Present": {
+                            "description": "Read: error present",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable TWI",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable TWI",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable TWI",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable TWI",
+                            "value": 5
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RXD": {
+              "description": "RXD register",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXD": {
+                    "description": "RXD register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXD": {
+              "description": "TXD register",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXD": {
+                    "description": "TXD register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "FREQUENCY": {
+              "description": "TWI frequency. Accuracy depends on the HFCLK source selected.",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQUENCY": {
+                    "description": "TWI master clock frequency",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "K100": {
+                            "description": "100 kbps",
+                            "value": 26738688
+                          },
+                          "K250": {
+                            "description": "250 kbps",
+                            "value": 67108864
+                          },
+                          "K400": {
+                            "description": "400 kbps (actual rate 410.256 kbps)",
+                            "value": 107479040
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ADDRESS": {
+              "description": "Address used in the TWI transfer",
+              "offset": 1416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS": {
+                    "description": "Address used in the TWI transfer",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TWIM0": {
+        "description": "I2C compatible Two-Wire Master Interface with EasyDMA 0",
+        "children": {
+          "registers": {
+            "TASKS_STARTRX": {
+              "description": "Start TWI receive sequence",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTRX": {
+                    "description": "Start TWI receive sequence",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STARTTX": {
+              "description": "Start TWI transmit sequence",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTTX": {
+                    "description": "Start TWI transmit sequence",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stop TWI transaction. Must be issued while the TWI master is not suspended.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop TWI transaction. Must be issued while the TWI master is not suspended.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SUSPEND": {
+              "description": "Suspend TWI transaction",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SUSPEND": {
+                    "description": "Suspend TWI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_RESUME": {
+              "description": "Resume TWI transaction",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_RESUME": {
+                    "description": "Resume TWI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STOPPED": {
+              "description": "TWI stopped",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STOPPED": {
+                    "description": "TWI stopped",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ERROR": {
+              "description": "TWI error",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ERROR": {
+                    "description": "TWI error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_SUSPENDED": {
+              "description": "Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_SUSPENDED": {
+                    "description": "Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXSTARTED": {
+              "description": "Receive sequence started",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXSTARTED": {
+                    "description": "Receive sequence started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TXSTARTED": {
+              "description": "Transmit sequence started",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TXSTARTED": {
+                    "description": "Transmit sequence started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_LASTRX": {
+              "description": "Byte boundary, starting to receive the last byte",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_LASTRX": {
+                    "description": "Byte boundary, starting to receive the last byte",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_LASTTX": {
+              "description": "Byte boundary, starting to transmit the last byte",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_LASTTX": {
+                    "description": "Byte boundary, starting to transmit the last byte",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LASTTX_STARTRX": {
+                    "description": "Shortcut between event LASTTX and task STARTRX",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTTX_SUSPEND": {
+                    "description": "Shortcut between event LASTTX and task SUSPEND",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTTX_STOP": {
+                    "description": "Shortcut between event LASTTX and task STOP",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTRX_STARTTX": {
+                    "description": "Shortcut between event LASTRX and task STARTTX",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTRX_SUSPEND": {
+                    "description": "Shortcut between event LASTRX and task SUSPEND",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTRX_STOP": {
+                    "description": "Shortcut between event LASTRX and task STOP",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Enable or disable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SUSPENDED": {
+                    "description": "Enable or disable interrupt for event SUSPENDED",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Enable or disable interrupt for event RXSTARTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Enable or disable interrupt for event TXSTARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTRX": {
+                    "description": "Enable or disable interrupt for event LASTRX",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTTX": {
+                    "description": "Enable or disable interrupt for event LASTTX",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to enable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to enable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SUSPENDED": {
+                    "description": "Write '1' to enable interrupt for event SUSPENDED",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to enable interrupt for event RXSTARTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to enable interrupt for event TXSTARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTRX": {
+                    "description": "Write '1' to enable interrupt for event LASTRX",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTTX": {
+                    "description": "Write '1' to enable interrupt for event LASTTX",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to disable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to disable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SUSPENDED": {
+                    "description": "Write '1' to disable interrupt for event SUSPENDED",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to disable interrupt for event RXSTARTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to disable interrupt for event TXSTARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTRX": {
+                    "description": "Write '1' to disable interrupt for event LASTRX",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LASTTX": {
+                    "description": "Write '1' to disable interrupt for event LASTTX",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSRC": {
+              "description": "Error source",
+              "offset": 1220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERRUN": {
+                    "description": "Overrun error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotReceived": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Received": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ANACK": {
+                    "description": "NACK received after sending the address (write '1' to clear)",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotReceived": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Received": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DNACK": {
+                    "description": "NACK received after sending a data byte (write '1' to clear)",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotReceived": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Received": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable TWIM",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable TWIM",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable TWIM",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable TWIM",
+                            "value": 6
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FREQUENCY": {
+              "description": "TWI frequency. Accuracy depends on the HFCLK source selected.",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 67108864,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQUENCY": {
+                    "description": "TWI master clock frequency",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "K100": {
+                            "description": "100 kbps",
+                            "value": 26738688
+                          },
+                          "K250": {
+                            "description": "250 kbps",
+                            "value": 67108864
+                          },
+                          "K400": {
+                            "description": "400 kbps",
+                            "value": 104857600
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ADDRESS": {
+              "description": "Address used in the TWI transfer",
+              "offset": 1416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS": {
+                    "description": "Address used in the TWI transfer",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TWIS0": {
+        "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 0",
+        "children": {
+          "registers": {
+            "TASKS_STOP": {
+              "description": "Stop TWI transaction",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop TWI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SUSPEND": {
+              "description": "Suspend TWI transaction",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SUSPEND": {
+                    "description": "Suspend TWI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_RESUME": {
+              "description": "Resume TWI transaction",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_RESUME": {
+                    "description": "Resume TWI transaction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_PREPARERX": {
+              "description": "Prepare the TWI slave to respond to a write command",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_PREPARERX": {
+                    "description": "Prepare the TWI slave to respond to a write command",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_PREPARETX": {
+              "description": "Prepare the TWI slave to respond to a read command",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_PREPARETX": {
+                    "description": "Prepare the TWI slave to respond to a read command",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STOPPED": {
+              "description": "TWI stopped",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STOPPED": {
+                    "description": "TWI stopped",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ERROR": {
+              "description": "TWI error",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ERROR": {
+                    "description": "TWI error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXSTARTED": {
+              "description": "Receive sequence started",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXSTARTED": {
+                    "description": "Receive sequence started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TXSTARTED": {
+              "description": "Transmit sequence started",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TXSTARTED": {
+                    "description": "Transmit sequence started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_WRITE": {
+              "description": "Write command received",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_WRITE": {
+                    "description": "Write command received",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_READ": {
+              "description": "Read command received",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_READ": {
+                    "description": "Read command received",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WRITE_SUSPEND": {
+                    "description": "Shortcut between event WRITE and task SUSPEND",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READ_SUSPEND": {
+                    "description": "Shortcut between event READ and task SUSPEND",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Enable or disable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Enable or disable interrupt for event RXSTARTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Enable or disable interrupt for event TXSTARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WRITE": {
+                    "description": "Enable or disable interrupt for event WRITE",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READ": {
+                    "description": "Enable or disable interrupt for event READ",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to enable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to enable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to enable interrupt for event RXSTARTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to enable interrupt for event TXSTARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WRITE": {
+                    "description": "Write '1' to enable interrupt for event WRITE",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READ": {
+                    "description": "Write '1' to enable interrupt for event READ",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to disable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to disable interrupt for event ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXSTARTED": {
+                    "description": "Write '1' to disable interrupt for event RXSTARTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXSTARTED": {
+                    "description": "Write '1' to disable interrupt for event TXSTARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WRITE": {
+                    "description": "Write '1' to disable interrupt for event WRITE",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READ": {
+                    "description": "Write '1' to disable interrupt for event READ",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSRC": {
+              "description": "Error source",
+              "offset": 1232,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERFLOW": {
+                    "description": "RX buffer overflow detected, and prevented",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DNACK": {
+                    "description": "NACK sent after receiving a data byte",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotReceived": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Received": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVERREAD": {
+                    "description": "TX buffer over-read detected, and prevented",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Error did not occur",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Error occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MATCH": {
+              "description": "Status register indicating which address had a match",
+              "offset": 1236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "MATCH": {
+                    "description": "Which of the addresses in {ADDRESS} matched the incoming address",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable TWIS",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable TWIS",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable TWIS",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable TWIS",
+                            "value": 9
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ADDRESS": {
+              "description": "Description collection: TWI slave address n",
+              "offset": 1416,
+              "size": 32,
+              "count": 2,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS": {
+                    "description": "TWI slave address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register for the address match mechanism",
+              "offset": 1428,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS0": {
+                    "description": "Enable or disable address matching on ADDRESS[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDRESS1": {
+                    "description": "Enable or disable address matching on ADDRESS[1]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ORC": {
+              "description": "Over-read character. Character sent out in case of an over-read of the transmit buffer.",
+              "offset": 1472,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ORC": {
+                    "description": "Over-read character. Character sent out in case of an over-read of the transmit buffer.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PDM": {
+        "description": "Pulse Density Modulation (Digital Microphone) Interface",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Starts continuous PDM transfer",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Starts continuous PDM transfer",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stops PDM transfer",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stops PDM transfer",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STARTED": {
+              "description": "PDM transfer has started",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STARTED": {
+                    "description": "PDM transfer has started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STOPPED": {
+              "description": "PDM transfer has finished",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STOPPED": {
+                    "description": "PDM transfer has finished",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_END": {
+              "description": "The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_END": {
+                    "description": "The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Enable or disable interrupt for event STARTED",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Enable or disable interrupt for event END",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Write '1' to enable interrupt for event STARTED",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to enable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to enable interrupt for event END",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Write '1' to disable interrupt for event STARTED",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to disable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to disable interrupt for event END",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "PDM module enable register",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable PDM module",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PDMCLKCTRL": {
+              "description": "PDM clock generator control",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 138412032,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FREQ": {
+                    "description": "PDM_CLK frequency",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "1000K": {
+                            "description": "PDM_CLK = 32 MHz / 32 = 1.000 MHz",
+                            "value": 134217728
+                          },
+                          "Default": {
+                            "description": "PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64.",
+                            "value": 138412032
+                          },
+                          "1067K": {
+                            "description": "PDM_CLK = 32 MHz / 30 = 1.067 MHz",
+                            "value": 142606336
+                          },
+                          "1231K": {
+                            "description": "PDM_CLK = 32 MHz / 26 = 1.231 MHz",
+                            "value": 159383552
+                          },
+                          "1280K": {
+                            "description": "PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80.",
+                            "value": 167772160
+                          },
+                          "1333K": {
+                            "description": "PDM_CLK = 32 MHz / 24 = 1.333 MHz",
+                            "value": 176160768
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Defines the routing of the connected PDM microphones' signals",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OPERATION": {
+                    "description": "Mono or stereo operation",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Stereo": {
+                            "description": "Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]",
+                            "value": 0
+                          },
+                          "Mono": {
+                            "description": "Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EDGE": {
+                    "description": "Defines on which PDM_CLK edge Left (or mono) is sampled",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LeftFalling": {
+                            "description": "Left (or mono) is sampled on falling edge of PDM_CLK",
+                            "value": 0
+                          },
+                          "LeftRising": {
+                            "description": "Left (or mono) is sampled on rising edge of PDM_CLK",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GAINL": {
+              "description": "Left output gain adjustment",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 40,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GAINL": {
+                    "description": "Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust",
+                    "offset": 0,
+                    "size": 7,
+                    "enum": {
+                      "size": 7,
+                      "children": {
+                        "enum_fields": {
+                          "MinGain": {
+                            "description": "-20dB gain adjustment (minimum)",
+                            "value": 0
+                          },
+                          "DefaultGain": {
+                            "description": "0dB gain adjustment",
+                            "value": 40
+                          },
+                          "MaxGain": {
+                            "description": "+20dB gain adjustment (maximum)",
+                            "value": 80
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GAINR": {
+              "description": "Right output gain adjustment",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 40,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GAINR": {
+                    "description": "Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)",
+                    "offset": 0,
+                    "size": 7,
+                    "enum": {
+                      "size": 7,
+                      "children": {
+                        "enum_fields": {
+                          "MinGain": {
+                            "description": "-20dB gain adjustment (minimum)",
+                            "value": 0
+                          },
+                          "DefaultGain": {
+                            "description": "0dB gain adjustment",
+                            "value": 40
+                          },
+                          "MaxGain": {
+                            "description": "+20dB gain adjustment (maximum)",
+                            "value": 80
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RATIO": {
+              "description": "Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly.",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RATIO": {
+                    "description": "Selects the ratio between PDM_CLK and output sample rate",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Ratio64": {
+                            "description": "Ratio of 64",
+                            "value": 0
+                          },
+                          "Ratio80": {
+                            "description": "Ratio of 80",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CRYPTOCELL": {
+        "description": "ARM TrustZone CryptoCell register interface",
+        "children": {
+          "registers": {
+            "ENABLE": {
+              "description": "Enable CRYPTOCELL subsystem",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable the CRYPTOCELL subsystem",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "CRYPTOCELL subsystem disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "CRYPTOCELL subsystem enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CC_HOST_RGF": {
+        "description": "CRYPTOCELL HOST_RGF interface",
+        "children": {
+          "registers": {
+            "HOST_CRYPTOKEY_SEL": {
+              "description": "AES hardware key select",
+              "offset": 6712,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HOST_CRYPTOKEY_SEL": {
+                    "description": "Select the source of the HW key that is used by the AES engine",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "K_DR": {
+                            "description": "Use device root key K_DR from CRYPTOCELL AO power domain",
+                            "value": 0
+                          },
+                          "K_PRTL": {
+                            "description": "Use hard-coded RTL key K_PRTL",
+                            "value": 1
+                          },
+                          "Session": {
+                            "description": "Use provided session key",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "HOST_IOT_KPRTL_LOCK": {
+              "description": "This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.",
+              "offset": 6732,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HOST_IOT_KPRTL_LOCK": {
+                    "description": "This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "HOST_IOT_KDR0": {
+              "description": "This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained.",
+              "offset": 6736,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HOST_IOT_KDR0": {
+                    "description": "Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HOST_IOT_KDR1": {
+              "description": "This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.",
+              "offset": 6740,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "HOST_IOT_KDR1": {
+                    "description": "K_DR bits 63:32",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HOST_IOT_KDR2": {
+              "description": "This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.",
+              "offset": 6744,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "HOST_IOT_KDR2": {
+                    "description": "K_DR bits 95:64",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HOST_IOT_KDR3": {
+              "description": "This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.",
+              "offset": 6748,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "HOST_IOT_KDR3": {
+                    "description": "K_DR bits 127:96",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HOST_IOT_LCS": {
+              "description": "Controls lifecycle state (LCS) for CRYPTOCELL subsystem",
+              "offset": 6752,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LCS": {
+                    "description": "Lifecycle state value. This field is write-once per reset.",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "Debug": {
+                            "description": "CC310 operates in debug mode",
+                            "value": 0
+                          },
+                          "Secure": {
+                            "description": "CC310 operates in secure mode",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LCS_IS_VALID": {
+                    "description": "This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Invalid": {
+                            "description": "A valid LCS is not yet retained in the CRYPTOCELL AO power domain",
+                            "value": 0
+                          },
+                          "Valid": {
+                            "description": "A valid LCS is successfully retained in the CRYPTOCELL AO power domain",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "QSPI": {
+        "description": "External flash interface",
+        "children": {
+          "registers": {
+            "TASKS_ACTIVATE": {
+              "description": "Activate QSPI interface",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_ACTIVATE": {
+                    "description": "Activate QSPI interface",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_READSTART": {
+              "description": "Start transfer from external flash memory to internal RAM",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_READSTART": {
+                    "description": "Start transfer from external flash memory to internal RAM",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_WRITESTART": {
+              "description": "Start transfer from internal RAM to external flash memory",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_WRITESTART": {
+                    "description": "Start transfer from internal RAM to external flash memory",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_ERASESTART": {
+              "description": "Start external flash memory erase operation",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_ERASESTART": {
+                    "description": "Start external flash memory erase operation",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_DEACTIVATE": {
+              "description": "Deactivate QSPI interface",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_DEACTIVATE": {
+                    "description": "Deactivate QSPI interface",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_READY": {
+              "description": "QSPI peripheral is ready. This event will be generated as a response to any QSPI task.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_READY": {
+                    "description": "QSPI peripheral is ready. This event will be generated as a response to any QSPI task.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Enable or disable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to enable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to disable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable QSPI peripheral and acquire the pins selected in PSELn registers",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable QSPI",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable QSPI",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable QSPI",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "XIPOFFSET": {
+              "description": "Address offset into the external memory for Execute in Place operation.",
+              "offset": 1344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XIPOFFSET": {
+                    "description": "Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IFCONFIG0": {
+              "description": "Interface configuration.",
+              "offset": 1348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READOC": {
+                    "description": "Configure number of data lines and opcode used for reading.",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "FASTREAD": {
+                            "description": "Single data line SPI. FAST_READ (opcode 0x0B).",
+                            "value": 0
+                          },
+                          "READ2O": {
+                            "description": "Dual data line SPI. READ2O (opcode 0x3B).",
+                            "value": 1
+                          },
+                          "READ2IO": {
+                            "description": "Dual data line SPI. READ2IO (opcode 0xBB).",
+                            "value": 2
+                          },
+                          "READ4O": {
+                            "description": "Quad data line SPI. READ4O (opcode 0x6B).",
+                            "value": 3
+                          },
+                          "READ4IO": {
+                            "description": "Quad data line SPI. READ4IO (opcode 0xEB).",
+                            "value": 4
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WRITEOC": {
+                    "description": "Configure number of data lines and opcode used for writing.",
+                    "offset": 3,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "PP": {
+                            "description": "Single data line SPI. PP (opcode 0x02).",
+                            "value": 0
+                          },
+                          "PP2O": {
+                            "description": "Dual data line SPI. PP2O (opcode 0xA2).",
+                            "value": 1
+                          },
+                          "PP4O": {
+                            "description": "Quad data line SPI. PP4O (opcode 0x32).",
+                            "value": 2
+                          },
+                          "PP4IO": {
+                            "description": "Quad data line SPI. PP4IO (opcode 0x38).",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDRMODE": {
+                    "description": "Addressing mode.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "24BIT": {
+                            "description": "24-bit addressing.",
+                            "value": 0
+                          },
+                          "32BIT": {
+                            "description": "32-bit addressing.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DPMENABLE": {
+                    "description": "Enable deep power-down mode (DPM) feature.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable DPM feature.",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable DPM feature.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PPSIZE": {
+                    "description": "Page size for commands PP, PP2O, PP4O and PP4IO.",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "256Bytes": {
+                            "description": "256 bytes.",
+                            "value": 0
+                          },
+                          "512Bytes": {
+                            "description": "512 bytes.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IFCONFIG1": {
+              "description": "Interface configuration.",
+              "offset": 1536,
+              "size": 32,
+              "reset_value": 263296,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCKDELAY": {
+                    "description": "Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns).",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "DPMEN": {
+                    "description": "Enter/exit deep power-down mode (DPM) for external flash memory.",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Exit": {
+                            "description": "Exit DPM.",
+                            "value": 0
+                          },
+                          "Enter": {
+                            "description": "Enter DPM.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SPIMODE": {
+                    "description": "Select SPI mode.",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MODE0": {
+                            "description": "Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0).",
+                            "value": 0
+                          },
+                          "MODE3": {
+                            "description": "Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SCKFREQ": {
+                    "description": "SCK frequency is given as 32 MHz / (SCKFREQ + 1).",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Status register.",
+              "offset": 1540,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DPM": {
+                    "description": "Deep power-down mode (DPM) status of external flash.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "External flash is not in DPM.",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "External flash is in DPM.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READY": {
+                    "description": "Ready status.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "READY": {
+                            "description": "QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM.",
+                            "value": 1
+                          },
+                          "BUSY": {
+                            "description": "QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SREG": {
+                    "description": "Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DPMDUR": {
+              "description": "Set the duration required to enter/exit deep power-down mode (DPM).",
+              "offset": 1556,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENTER": {
+                    "description": "Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "EXIT": {
+                    "description": "Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ADDRCONF": {
+              "description": "Extended address configuration.",
+              "offset": 1572,
+              "size": 32,
+              "reset_value": 183,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OPCODE": {
+                    "description": "Opcode that enters the 32-bit addressing mode.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "BYTE0": {
+                    "description": "Byte 0 following opcode.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BYTE1": {
+                    "description": "Byte 1 following byte 0.",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MODE": {
+                    "description": "Extended addressing mode.",
+                    "offset": 24,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NoInstr": {
+                            "description": "Do not send any instruction.",
+                            "value": 0
+                          },
+                          "Opcode": {
+                            "description": "Send opcode.",
+                            "value": 1
+                          },
+                          "OpByte0": {
+                            "description": "Send opcode, byte0.",
+                            "value": 2
+                          },
+                          "All": {
+                            "description": "Send opcode, byte0, byte1.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WIPWAIT": {
+                    "description": "Wait for write complete before sending command.",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "No wait.",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Wait.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WREN": {
+                    "description": "Send WREN (write enable opcode 0x06) before instruction.",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Do not send WREN.",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Send WREN.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CINSTRCONF": {
+              "description": "Custom instruction configuration register.",
+              "offset": 1588,
+              "size": 32,
+              "reset_value": 8192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OPCODE": {
+                    "description": "Opcode of Custom instruction.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "LENGTH": {
+                    "description": "Length of custom instruction in number of bytes.",
+                    "offset": 8,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "1B": {
+                            "description": "Send opcode only.",
+                            "value": 1
+                          },
+                          "2B": {
+                            "description": "Send opcode, CINSTRDAT0.BYTE0.",
+                            "value": 2
+                          },
+                          "3B": {
+                            "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1.",
+                            "value": 3
+                          },
+                          "4B": {
+                            "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2.",
+                            "value": 4
+                          },
+                          "5B": {
+                            "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3.",
+                            "value": 5
+                          },
+                          "6B": {
+                            "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4.",
+                            "value": 6
+                          },
+                          "7B": {
+                            "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5.",
+                            "value": 7
+                          },
+                          "8B": {
+                            "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6.",
+                            "value": 8
+                          },
+                          "9B": {
+                            "description": "Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7.",
+                            "value": 9
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LIO2": {
+                    "description": "Level of the IO2 pin (if connected) during transmission of custom instruction.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LIO3": {
+                    "description": "Level of the IO3 pin (if connected) during transmission of custom instruction.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WIPWAIT": {
+                    "description": "Wait for write complete before sending command.",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "No wait.",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Wait.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WREN": {
+                    "description": "Send WREN (write enable opcode 0x06) before instruction.",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Do not send WREN.",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Send WREN.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LFEN": {
+                    "description": "Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Long frame mode disabled",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Long frame mode enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LFSTOP": {
+                    "description": "Stop (finalize) long frame transaction",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Stop": {
+                            "description": "Stop",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CINSTRDAT0": {
+              "description": "Custom instruction data register 0.",
+              "offset": 1592,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BYTE0": {
+                    "description": "Data byte 0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "BYTE1": {
+                    "description": "Data byte 1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BYTE2": {
+                    "description": "Data byte 2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "BYTE3": {
+                    "description": "Data byte 3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CINSTRDAT1": {
+              "description": "Custom instruction data register 1.",
+              "offset": 1596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BYTE4": {
+                    "description": "Data byte 4",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "BYTE5": {
+                    "description": "Data byte 5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BYTE6": {
+                    "description": "Data byte 6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "BYTE7": {
+                    "description": "Data byte 7",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IFTIMING": {
+              "description": "SPI interface timing.",
+              "offset": 1600,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDELAY": {
+                    "description": "Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK.",
+                    "offset": 8,
+                    "size": 3
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PWM0": {
+        "description": "Pulse width modulation unit 0",
+        "children": {
+          "registers": {
+            "TASKS_STOP": {
+              "description": "Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SEQSTART": {
+              "description": "Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.",
+              "offset": 8,
+              "size": 32,
+              "count": 2,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SEQSTART": {
+                    "description": "Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_NEXTSTEP": {
+              "description": "Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_NEXTSTEP": {
+                    "description": "Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STOPPED": {
+              "description": "Response to STOP task, emitted when PWM pulses are no longer generated",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STOPPED": {
+                    "description": "Response to STOP task, emitted when PWM pulses are no longer generated",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_SEQSTARTED": {
+              "description": "Description collection: First PWM period started on sequence n",
+              "offset": 264,
+              "size": 32,
+              "count": 2,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_SEQSTARTED": {
+                    "description": "First PWM period started on sequence n",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_SEQEND": {
+              "description": "Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter",
+              "offset": 272,
+              "size": 32,
+              "count": 2,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_SEQEND": {
+                    "description": "Emitted at end of every sequence n, when last value from RAM has been applied to wave counter",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_PWMPERIODEND": {
+              "description": "Emitted at the end of each PWM period",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_PWMPERIODEND": {
+                    "description": "Emitted at the end of each PWM period",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_LOOPSDONE": {
+              "description": "Concatenated sequences have been played the amount of times defined in LOOP.CNT",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_LOOPSDONE": {
+                    "description": "Concatenated sequences have been played the amount of times defined in LOOP.CNT",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEQEND0_STOP": {
+                    "description": "Shortcut between event SEQEND[0] and task STOP",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND1_STOP": {
+                    "description": "Shortcut between event SEQEND[1] and task STOP",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE_SEQSTART0": {
+                    "description": "Shortcut between event LOOPSDONE and task SEQSTART[0]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE_SEQSTART1": {
+                    "description": "Shortcut between event LOOPSDONE and task SEQSTART[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE_STOP": {
+                    "description": "Shortcut between event LOOPSDONE and task STOP",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED0": {
+                    "description": "Enable or disable interrupt for event SEQSTARTED[0]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED1": {
+                    "description": "Enable or disable interrupt for event SEQSTARTED[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND0": {
+                    "description": "Enable or disable interrupt for event SEQEND[0]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND1": {
+                    "description": "Enable or disable interrupt for event SEQEND[1]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMPERIODEND": {
+                    "description": "Enable or disable interrupt for event PWMPERIODEND",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE": {
+                    "description": "Enable or disable interrupt for event LOOPSDONE",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to enable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED0": {
+                    "description": "Write '1' to enable interrupt for event SEQSTARTED[0]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED1": {
+                    "description": "Write '1' to enable interrupt for event SEQSTARTED[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND0": {
+                    "description": "Write '1' to enable interrupt for event SEQEND[0]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND1": {
+                    "description": "Write '1' to enable interrupt for event SEQEND[1]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMPERIODEND": {
+                    "description": "Write '1' to enable interrupt for event PWMPERIODEND",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE": {
+                    "description": "Write '1' to enable interrupt for event LOOPSDONE",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STOPPED": {
+                    "description": "Write '1' to disable interrupt for event STOPPED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED0": {
+                    "description": "Write '1' to disable interrupt for event SEQSTARTED[0]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQSTARTED1": {
+                    "description": "Write '1' to disable interrupt for event SEQSTARTED[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND0": {
+                    "description": "Write '1' to disable interrupt for event SEQEND[0]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEQEND1": {
+                    "description": "Write '1' to disable interrupt for event SEQEND[1]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMPERIODEND": {
+                    "description": "Write '1' to disable interrupt for event PWMPERIODEND",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOOPSDONE": {
+                    "description": "Write '1' to disable interrupt for event LOOPSDONE",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "PWM module enable register",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable PWM module",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Selects operating mode of the wave counter",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UPDOWN": {
+                    "description": "Selects up mode or up-and-down mode for the counter",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Up": {
+                            "description": "Up counter, edge-aligned PWM duty cycle",
+                            "value": 0
+                          },
+                          "UpAndDown": {
+                            "description": "Up and down counter, center-aligned PWM duty cycle",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "COUNTERTOP": {
+              "description": "Value up to which the pulse generator counter counts",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 1023,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COUNTERTOP": {
+                    "description": "Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used.",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "PRESCALER": {
+              "description": "Configuration for PWM_CLK",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRESCALER": {
+                    "description": "Prescaler of PWM_CLK",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "DIV_1": {
+                            "description": "Divide by 1 (16 MHz)",
+                            "value": 0
+                          },
+                          "DIV_2": {
+                            "description": "Divide by 2 (8 MHz)",
+                            "value": 1
+                          },
+                          "DIV_4": {
+                            "description": "Divide by 4 (4 MHz)",
+                            "value": 2
+                          },
+                          "DIV_8": {
+                            "description": "Divide by 8 (2 MHz)",
+                            "value": 3
+                          },
+                          "DIV_16": {
+                            "description": "Divide by 16 (1 MHz)",
+                            "value": 4
+                          },
+                          "DIV_32": {
+                            "description": "Divide by 32 (500 kHz)",
+                            "value": 5
+                          },
+                          "DIV_64": {
+                            "description": "Divide by 64 (250 kHz)",
+                            "value": 6
+                          },
+                          "DIV_128": {
+                            "description": "Divide by 128 (125 kHz)",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DECODER": {
+              "description": "Configuration of the decoder",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOAD": {
+                    "description": "How a sequence is read from RAM and spread to the compare register",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Common": {
+                            "description": "1st half word (16-bit) used in all PWM channels 0..3",
+                            "value": 0
+                          },
+                          "Grouped": {
+                            "description": "1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3",
+                            "value": 1
+                          },
+                          "Individual": {
+                            "description": "1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3",
+                            "value": 2
+                          },
+                          "WaveForm": {
+                            "description": "1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MODE": {
+                    "description": "Selects source for advancing the active sequence",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RefreshCount": {
+                            "description": "SEQ[n].REFRESH is used to determine loading internal compare registers",
+                            "value": 0
+                          },
+                          "NextStep": {
+                            "description": "NEXTSTEP task causes a new value to be loaded to internal compare registers",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LOOP": {
+              "description": "Number of playbacks of a loop",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Number of playbacks of pattern cycles",
+                    "offset": 0,
+                    "size": 16,
+                    "enum": {
+                      "size": 16,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Looping disabled (stop at the end of the sequence)",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USBD": {
+        "description": "Universal serial bus device",
+        "children": {
+          "registers": {
+            "TASKS_STARTEPIN": {
+              "description": "Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host",
+              "offset": 4,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTEPIN": {
+                    "description": "Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STARTISOIN": {
+              "description": "Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTISOIN": {
+                    "description": "Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STARTEPOUT": {
+              "description": "Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host",
+              "offset": 40,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTEPOUT": {
+                    "description": "Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STARTISOOUT": {
+              "description": "Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTISOOUT": {
+                    "description": "Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_EP0RCVOUT": {
+              "description": "Allows OUT data stage on control endpoint 0",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_EP0RCVOUT": {
+                    "description": "Allows OUT data stage on control endpoint 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_EP0STATUS": {
+              "description": "Allows status stage on control endpoint 0",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_EP0STATUS": {
+                    "description": "Allows status stage on control endpoint 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_EP0STALL": {
+              "description": "Stalls data and status stage on control endpoint 0",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_EP0STALL": {
+                    "description": "Stalls data and status stage on control endpoint 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_DPDMDRIVE": {
+              "description": "Forces D+ and D- lines into the state defined in the DPDMVALUE register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_DPDMDRIVE": {
+                    "description": "Forces D+ and D- lines into the state defined in the DPDMVALUE register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_DPDMNODRIVE": {
+              "description": "Stops forcing D+ and D- lines into any state (USB engine takes control)",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_DPDMNODRIVE": {
+                    "description": "Stops forcing D+ and D- lines into any state (USB engine takes control)",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_USBRESET": {
+              "description": "Signals that a USB reset condition has been detected on USB lines",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_USBRESET": {
+                    "description": "Signals that a USB reset condition has been detected on USB lines",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STARTED": {
+              "description": "Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STARTED": {
+                    "description": "Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDEPIN": {
+              "description": "Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software.",
+              "offset": 264,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDEPIN": {
+                    "description": "The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_EP0DATADONE": {
+              "description": "An acknowledged data transfer has taken place on the control endpoint",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_EP0DATADONE": {
+                    "description": "An acknowledged data transfer has taken place on the control endpoint",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDISOIN": {
+              "description": "The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software.",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDISOIN": {
+                    "description": "The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDEPOUT": {
+              "description": "Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software.",
+              "offset": 304,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDEPOUT": {
+                    "description": "The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDISOOUT": {
+              "description": "The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software.",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDISOOUT": {
+                    "description": "The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_SOF": {
+              "description": "Signals that a SOF (start of frame) condition has been detected on USB lines",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_SOF": {
+                    "description": "Signals that a SOF (start of frame) condition has been detected on USB lines",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_USBEVENT": {
+              "description": "An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause.",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_USBEVENT": {
+                    "description": "An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_EP0SETUP": {
+              "description": "A valid SETUP token has been received (and acknowledged) on the control endpoint",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_EP0SETUP": {
+                    "description": "A valid SETUP token has been received (and acknowledged) on the control endpoint",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_EPDATA": {
+              "description": "A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_EPDATA": {
+                    "description": "A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EP0DATADONE_STARTEPIN0": {
+                    "description": "Shortcut between event EP0DATADONE and task STARTEPIN[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EP0DATADONE_STARTEPOUT0": {
+                    "description": "Shortcut between event EP0DATADONE and task STARTEPOUT[0]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EP0DATADONE_EP0STATUS": {
+                    "description": "Shortcut between event EP0DATADONE and task EP0STATUS",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT0_EP0STATUS": {
+                    "description": "Shortcut between event ENDEPOUT[0] and task EP0STATUS",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT0_EP0RCVOUT": {
+                    "description": "Shortcut between event ENDEPOUT[0] and task EP0RCVOUT",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USBRESET": {
+                    "description": "Enable or disable interrupt for event USBRESET",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Enable or disable interrupt for event STARTED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN0": {
+                    "description": "Enable or disable interrupt for event ENDEPIN[0]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN1": {
+                    "description": "Enable or disable interrupt for event ENDEPIN[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN2": {
+                    "description": "Enable or disable interrupt for event ENDEPIN[2]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN3": {
+                    "description": "Enable or disable interrupt for event ENDEPIN[3]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN4": {
+                    "description": "Enable or disable interrupt for event ENDEPIN[4]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN5": {
+                    "description": "Enable or disable interrupt for event ENDEPIN[5]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN6": {
+                    "description": "Enable or disable interrupt for event ENDEPIN[6]",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN7": {
+                    "description": "Enable or disable interrupt for event ENDEPIN[7]",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EP0DATADONE": {
+                    "description": "Enable or disable interrupt for event EP0DATADONE",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDISOIN": {
+                    "description": "Enable or disable interrupt for event ENDISOIN",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT0": {
+                    "description": "Enable or disable interrupt for event ENDEPOUT[0]",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT1": {
+                    "description": "Enable or disable interrupt for event ENDEPOUT[1]",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT2": {
+                    "description": "Enable or disable interrupt for event ENDEPOUT[2]",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT3": {
+                    "description": "Enable or disable interrupt for event ENDEPOUT[3]",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT4": {
+                    "description": "Enable or disable interrupt for event ENDEPOUT[4]",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT5": {
+                    "description": "Enable or disable interrupt for event ENDEPOUT[5]",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT6": {
+                    "description": "Enable or disable interrupt for event ENDEPOUT[6]",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT7": {
+                    "description": "Enable or disable interrupt for event ENDEPOUT[7]",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDISOOUT": {
+                    "description": "Enable or disable interrupt for event ENDISOOUT",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SOF": {
+                    "description": "Enable or disable interrupt for event SOF",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "USBEVENT": {
+                    "description": "Enable or disable interrupt for event USBEVENT",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EP0SETUP": {
+                    "description": "Enable or disable interrupt for event EP0SETUP",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPDATA": {
+                    "description": "Enable or disable interrupt for event EPDATA",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USBRESET": {
+                    "description": "Write '1' to enable interrupt for event USBRESET",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Write '1' to enable interrupt for event STARTED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN0": {
+                    "description": "Write '1' to enable interrupt for event ENDEPIN[0]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN1": {
+                    "description": "Write '1' to enable interrupt for event ENDEPIN[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN2": {
+                    "description": "Write '1' to enable interrupt for event ENDEPIN[2]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN3": {
+                    "description": "Write '1' to enable interrupt for event ENDEPIN[3]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN4": {
+                    "description": "Write '1' to enable interrupt for event ENDEPIN[4]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN5": {
+                    "description": "Write '1' to enable interrupt for event ENDEPIN[5]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN6": {
+                    "description": "Write '1' to enable interrupt for event ENDEPIN[6]",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN7": {
+                    "description": "Write '1' to enable interrupt for event ENDEPIN[7]",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EP0DATADONE": {
+                    "description": "Write '1' to enable interrupt for event EP0DATADONE",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDISOIN": {
+                    "description": "Write '1' to enable interrupt for event ENDISOIN",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT0": {
+                    "description": "Write '1' to enable interrupt for event ENDEPOUT[0]",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT1": {
+                    "description": "Write '1' to enable interrupt for event ENDEPOUT[1]",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT2": {
+                    "description": "Write '1' to enable interrupt for event ENDEPOUT[2]",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT3": {
+                    "description": "Write '1' to enable interrupt for event ENDEPOUT[3]",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT4": {
+                    "description": "Write '1' to enable interrupt for event ENDEPOUT[4]",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT5": {
+                    "description": "Write '1' to enable interrupt for event ENDEPOUT[5]",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT6": {
+                    "description": "Write '1' to enable interrupt for event ENDEPOUT[6]",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT7": {
+                    "description": "Write '1' to enable interrupt for event ENDEPOUT[7]",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDISOOUT": {
+                    "description": "Write '1' to enable interrupt for event ENDISOOUT",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SOF": {
+                    "description": "Write '1' to enable interrupt for event SOF",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "USBEVENT": {
+                    "description": "Write '1' to enable interrupt for event USBEVENT",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EP0SETUP": {
+                    "description": "Write '1' to enable interrupt for event EP0SETUP",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPDATA": {
+                    "description": "Write '1' to enable interrupt for event EPDATA",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USBRESET": {
+                    "description": "Write '1' to disable interrupt for event USBRESET",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Write '1' to disable interrupt for event STARTED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN0": {
+                    "description": "Write '1' to disable interrupt for event ENDEPIN[0]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN1": {
+                    "description": "Write '1' to disable interrupt for event ENDEPIN[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN2": {
+                    "description": "Write '1' to disable interrupt for event ENDEPIN[2]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN3": {
+                    "description": "Write '1' to disable interrupt for event ENDEPIN[3]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN4": {
+                    "description": "Write '1' to disable interrupt for event ENDEPIN[4]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN5": {
+                    "description": "Write '1' to disable interrupt for event ENDEPIN[5]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN6": {
+                    "description": "Write '1' to disable interrupt for event ENDEPIN[6]",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPIN7": {
+                    "description": "Write '1' to disable interrupt for event ENDEPIN[7]",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EP0DATADONE": {
+                    "description": "Write '1' to disable interrupt for event EP0DATADONE",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDISOIN": {
+                    "description": "Write '1' to disable interrupt for event ENDISOIN",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT0": {
+                    "description": "Write '1' to disable interrupt for event ENDEPOUT[0]",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT1": {
+                    "description": "Write '1' to disable interrupt for event ENDEPOUT[1]",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT2": {
+                    "description": "Write '1' to disable interrupt for event ENDEPOUT[2]",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT3": {
+                    "description": "Write '1' to disable interrupt for event ENDEPOUT[3]",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT4": {
+                    "description": "Write '1' to disable interrupt for event ENDEPOUT[4]",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT5": {
+                    "description": "Write '1' to disable interrupt for event ENDEPOUT[5]",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT6": {
+                    "description": "Write '1' to disable interrupt for event ENDEPOUT[6]",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDEPOUT7": {
+                    "description": "Write '1' to disable interrupt for event ENDEPOUT[7]",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDISOOUT": {
+                    "description": "Write '1' to disable interrupt for event ENDISOOUT",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SOF": {
+                    "description": "Write '1' to disable interrupt for event SOF",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "USBEVENT": {
+                    "description": "Write '1' to disable interrupt for event USBEVENT",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EP0SETUP": {
+                    "description": "Write '1' to disable interrupt for event EP0SETUP",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPDATA": {
+                    "description": "Write '1' to disable interrupt for event EPDATA",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTCAUSE": {
+              "description": "Details on what caused the USBEVENT event",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ISOOUTCRC": {
+                    "description": "CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "No error detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Error detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SUSPEND": {
+                    "description": "Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Suspend not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Suspend detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESUME": {
+                    "description": "Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "Resume not detected",
+                            "value": 0
+                          },
+                          "Detected": {
+                            "description": "Resume detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "USBWUALLOWED": {
+                    "description": "USB MAC has been woken up and operational. Write '1' to clear.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotAllowed": {
+                            "description": "Wake up not allowed",
+                            "value": 0
+                          },
+                          "Allowed": {
+                            "description": "Wake up allowed",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READY": {
+                    "description": "USB device is ready for normal operation. Write '1' to clear.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDetected": {
+                            "description": "USBEVENT was not issued due to USBD peripheral ready",
+                            "value": 0
+                          },
+                          "Ready": {
+                            "description": "USBD peripheral is ready",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EPSTATUS": {
+              "description": "Provides information on which endpoint's EasyDMA registers have been captured",
+              "offset": 1128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPIN0": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN1": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN2": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN3": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN4": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN5": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN6": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN7": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN8": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT0": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT1": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT2": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT3": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT4": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT5": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT6": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT7": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT8": {
+                    "description": "Captured state of endpoint's EasyDMA registers. Write '1' to clear.",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoData": {
+                            "description": "EasyDMA registers have not been captured for this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "EasyDMA registers have been captured for this endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EPDATASTATUS": {
+              "description": "Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event)",
+              "offset": 1132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPIN1": {
+                    "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDone": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN2": {
+                    "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDone": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN3": {
+                    "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDone": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN4": {
+                    "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDone": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN5": {
+                    "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDone": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN6": {
+                    "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDone": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPIN7": {
+                    "description": "Acknowledged data transfer on this IN endpoint. Write '1' to clear.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotDone": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "DataDone": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT1": {
+                    "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotStarted": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "Started": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT2": {
+                    "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotStarted": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "Started": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT3": {
+                    "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotStarted": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "Started": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT4": {
+                    "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotStarted": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "Started": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT5": {
+                    "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotStarted": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "Started": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT6": {
+                    "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotStarted": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "Started": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPOUT7": {
+                    "description": "Acknowledged data transfer on this OUT endpoint. Write '1' to clear.",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotStarted": {
+                            "description": "No acknowledged data transfer on this endpoint",
+                            "value": 0
+                          },
+                          "Started": {
+                            "description": "Acknowledged data transfer on this endpoint has occurred",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "USBADDR": {
+              "description": "Device USB address",
+              "offset": 1136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ADDR": {
+                    "description": "Device USB address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "BMREQUESTTYPE": {
+              "description": "SETUP data, byte 0, bmRequestType",
+              "offset": 1152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RECIPIENT": {
+                    "description": "Data transfer type",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "Device": {
+                            "description": "Device",
+                            "value": 0
+                          },
+                          "Interface": {
+                            "description": "Interface",
+                            "value": 1
+                          },
+                          "Endpoint": {
+                            "description": "Endpoint",
+                            "value": 2
+                          },
+                          "Other": {
+                            "description": "Other",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TYPE": {
+                    "description": "Data transfer type",
+                    "offset": 5,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Standard": {
+                            "description": "Standard",
+                            "value": 0
+                          },
+                          "Class": {
+                            "description": "Class",
+                            "value": 1
+                          },
+                          "Vendor": {
+                            "description": "Vendor",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DIRECTION": {
+                    "description": "Data transfer direction",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "HostToDevice": {
+                            "description": "Host-to-device",
+                            "value": 0
+                          },
+                          "DeviceToHost": {
+                            "description": "Device-to-host",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "BREQUEST": {
+              "description": "SETUP data, byte 1, bRequest",
+              "offset": 1156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "BREQUEST": {
+                    "description": "SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values.",
+                    "offset": 0,
+                    "size": 8,
+                    "enum": {
+                      "size": 8,
+                      "children": {
+                        "enum_fields": {
+                          "STD_GET_STATUS": {
+                            "description": "Standard request GET_STATUS",
+                            "value": 0
+                          },
+                          "STD_CLEAR_FEATURE": {
+                            "description": "Standard request CLEAR_FEATURE",
+                            "value": 1
+                          },
+                          "STD_SET_FEATURE": {
+                            "description": "Standard request SET_FEATURE",
+                            "value": 3
+                          },
+                          "STD_SET_ADDRESS": {
+                            "description": "Standard request SET_ADDRESS",
+                            "value": 5
+                          },
+                          "STD_GET_DESCRIPTOR": {
+                            "description": "Standard request GET_DESCRIPTOR",
+                            "value": 6
+                          },
+                          "STD_SET_DESCRIPTOR": {
+                            "description": "Standard request SET_DESCRIPTOR",
+                            "value": 7
+                          },
+                          "STD_GET_CONFIGURATION": {
+                            "description": "Standard request GET_CONFIGURATION",
+                            "value": 8
+                          },
+                          "STD_SET_CONFIGURATION": {
+                            "description": "Standard request SET_CONFIGURATION",
+                            "value": 9
+                          },
+                          "STD_GET_INTERFACE": {
+                            "description": "Standard request GET_INTERFACE",
+                            "value": 10
+                          },
+                          "STD_SET_INTERFACE": {
+                            "description": "Standard request SET_INTERFACE",
+                            "value": 11
+                          },
+                          "STD_SYNCH_FRAME": {
+                            "description": "Standard request SYNCH_FRAME",
+                            "value": 12
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "WVALUEL": {
+              "description": "SETUP data, byte 2, LSB of wValue",
+              "offset": 1160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WVALUEL": {
+                    "description": "SETUP data, byte 2, LSB of wValue",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "WVALUEH": {
+              "description": "SETUP data, byte 3, MSB of wValue",
+              "offset": 1164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WVALUEH": {
+                    "description": "SETUP data, byte 3, MSB of wValue",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "WINDEXL": {
+              "description": "SETUP data, byte 4, LSB of wIndex",
+              "offset": 1168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WINDEXL": {
+                    "description": "SETUP data, byte 4, LSB of wIndex",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "WINDEXH": {
+              "description": "SETUP data, byte 5, MSB of wIndex",
+              "offset": 1172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WINDEXH": {
+                    "description": "SETUP data, byte 5, MSB of wIndex",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "WLENGTHL": {
+              "description": "SETUP data, byte 6, LSB of wLength",
+              "offset": 1176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WLENGTHL": {
+                    "description": "SETUP data, byte 6, LSB of wLength",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "WLENGTHH": {
+              "description": "SETUP data, byte 7, MSB of wLength",
+              "offset": 1180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WLENGTHH": {
+                    "description": "SETUP data, byte 7, MSB of wLength",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable USB",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable USB",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "USB peripheral is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "USB peripheral is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "USBPULLUP": {
+              "description": "Control of the USB pull-up",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONNECT": {
+                    "description": "Control of the USB pull-up on the D+ line",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Pull-up is disconnected",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Pull-up is connected to D+",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DPDMVALUE": {
+              "description": "State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing).",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATE": {
+                    "description": "State D+ and D- lines will be forced into by the DPDMDRIVE task",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "Resume": {
+                            "description": "D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state)",
+                            "value": 1
+                          },
+                          "J": {
+                            "description": "D+ forced high, D- forced low (J state)",
+                            "value": 2
+                          },
+                          "K": {
+                            "description": "D+ forced low, D- forced high (K state)",
+                            "value": 4
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DTOGGLE": {
+              "description": "Data toggle control and status",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 256,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EP": {
+                    "description": "Select bulk endpoint number",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "IO": {
+                    "description": "Selects IN or OUT endpoint",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Out": {
+                            "description": "Selects OUT endpoint",
+                            "value": 0
+                          },
+                          "In": {
+                            "description": "Selects IN endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "VALUE": {
+                    "description": "Data toggle value",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Nop": {
+                            "description": "No action on data toggle when writing the register with this value",
+                            "value": 0
+                          },
+                          "Data0": {
+                            "description": "Data toggle is DATA0 on endpoint set by EP and IO",
+                            "value": 1
+                          },
+                          "Data1": {
+                            "description": "Data toggle is DATA1 on endpoint set by EP and IO",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EPINEN": {
+              "description": "Endpoint IN enable",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN0": {
+                    "description": "Enable IN endpoint 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint IN 0 (no response to IN tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint IN 0 (response to IN tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN1": {
+                    "description": "Enable IN endpoint 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint IN 1 (no response to IN tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint IN 1 (response to IN tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN2": {
+                    "description": "Enable IN endpoint 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint IN 2 (no response to IN tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint IN 2 (response to IN tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN3": {
+                    "description": "Enable IN endpoint 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint IN 3 (no response to IN tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint IN 3 (response to IN tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN4": {
+                    "description": "Enable IN endpoint 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint IN 4 (no response to IN tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint IN 4 (response to IN tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN5": {
+                    "description": "Enable IN endpoint 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint IN 5 (no response to IN tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint IN 5 (response to IN tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN6": {
+                    "description": "Enable IN endpoint 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint IN 6 (no response to IN tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint IN 6 (response to IN tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN7": {
+                    "description": "Enable IN endpoint 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint IN 7 (no response to IN tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint IN 7 (response to IN tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ISOIN": {
+                    "description": "Enable ISO IN endpoint",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable ISO IN endpoint 8",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable ISO IN endpoint 8",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EPOUTEN": {
+              "description": "Endpoint OUT enable",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT0": {
+                    "description": "Enable OUT endpoint 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint OUT 0 (no response to OUT tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint OUT 0 (response to OUT tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUT1": {
+                    "description": "Enable OUT endpoint 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint OUT 1 (no response to OUT tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint OUT 1 (response to OUT tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUT2": {
+                    "description": "Enable OUT endpoint 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint OUT 2 (no response to OUT tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint OUT 2 (response to OUT tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUT3": {
+                    "description": "Enable OUT endpoint 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint OUT 3 (no response to OUT tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint OUT 3 (response to OUT tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUT4": {
+                    "description": "Enable OUT endpoint 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint OUT 4 (no response to OUT tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint OUT 4 (response to OUT tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUT5": {
+                    "description": "Enable OUT endpoint 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint OUT 5 (no response to OUT tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint OUT 5 (response to OUT tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUT6": {
+                    "description": "Enable OUT endpoint 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint OUT 6 (no response to OUT tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint OUT 6 (response to OUT tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUT7": {
+                    "description": "Enable OUT endpoint 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable endpoint OUT 7 (no response to OUT tokens)",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable endpoint OUT 7 (response to OUT tokens)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ISOOUT": {
+                    "description": "Enable ISO OUT endpoint 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable ISO OUT endpoint 8",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable ISO OUT endpoint 8",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EPSTALL": {
+              "description": "STALL endpoints",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EP": {
+                    "description": "Select endpoint number",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "IO": {
+                    "description": "Selects IN or OUT endpoint",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Out": {
+                            "description": "Selects OUT endpoint",
+                            "value": 0
+                          },
+                          "In": {
+                            "description": "Selects IN endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STALL": {
+                    "description": "Stall selected endpoint",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "UnStall": {
+                            "description": "Don't stall selected endpoint",
+                            "value": 0
+                          },
+                          "Stall": {
+                            "description": "Stall selected endpoint",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ISOSPLIT": {
+              "description": "Controls the split of ISO buffers",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPLIT": {
+                    "description": "Controls the split of ISO buffers",
+                    "offset": 0,
+                    "size": 16,
+                    "enum": {
+                      "size": 16,
+                      "children": {
+                        "enum_fields": {
+                          "OneDir": {
+                            "description": "Full buffer dedicated to either iso IN or OUT",
+                            "value": 0
+                          },
+                          "HalfIN": {
+                            "description": "Lower half for IN, upper half for OUT",
+                            "value": 128
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FRAMECNTR": {
+              "description": "Returns the current value of the start of frame counter",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FRAMECNTR": {
+                    "description": "Returns the current value of the start of frame counter",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "LOWPOWER": {
+              "description": "Controls USBD peripheral low power mode during USB suspend",
+              "offset": 1324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOWPOWER": {
+                    "description": "Controls USBD peripheral low-power mode during USB suspend",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ForceNormal": {
+                            "description": "Software must write this value to exit low power mode and before performing a remote wake-up",
+                            "value": 0
+                          },
+                          "LowPower": {
+                            "description": "Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ISOINCONFIG": {
+              "description": "Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent",
+              "offset": 1328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESPONSE": {
+                    "description": "Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoResp": {
+                            "description": "Endpoint does not respond in that case",
+                            "value": 0
+                          },
+                          "ZeroData": {
+                            "description": "Endpoint responds with a zero-length data packet in that case",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NFCT": {
+        "description": "NFC-A compatible radio",
+        "children": {
+          "registers": {
+            "TASKS_ACTIVATE": {
+              "description": "Activate NFCT peripheral for incoming and outgoing frames, change state to activated",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_ACTIVATE": {
+                    "description": "Activate NFCT peripheral for incoming and outgoing frames, change state to activated",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_DISABLE": {
+              "description": "Disable NFCT peripheral",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_DISABLE": {
+                    "description": "Disable NFCT peripheral",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SENSE": {
+              "description": "Enable NFC sense field mode, change state to sense mode",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SENSE": {
+                    "description": "Enable NFC sense field mode, change state to sense mode",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STARTTX": {
+              "description": "Start transmission of an outgoing frame, change state to transmit",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTTX": {
+                    "description": "Start transmission of an outgoing frame, change state to transmit",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_ENABLERXDATA": {
+              "description": "Initializes the EasyDMA for receive.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_ENABLERXDATA": {
+                    "description": "Initializes the EasyDMA for receive.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_GOIDLE": {
+              "description": "Force state machine to IDLE state",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_GOIDLE": {
+                    "description": "Force state machine to IDLE state",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_GOSLEEP": {
+              "description": "Force state machine to SLEEP_A state",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_GOSLEEP": {
+                    "description": "Force state machine to SLEEP_A state",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_READY": {
+              "description": "The NFCT peripheral is ready to receive and send frames",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_READY": {
+                    "description": "The NFCT peripheral is ready to receive and send frames",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_FIELDDETECTED": {
+              "description": "Remote NFC field detected",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_FIELDDETECTED": {
+                    "description": "Remote NFC field detected",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_FIELDLOST": {
+              "description": "Remote NFC field lost",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_FIELDLOST": {
+                    "description": "Remote NFC field lost",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TXFRAMESTART": {
+              "description": "Marks the start of the first symbol of a transmitted frame",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TXFRAMESTART": {
+                    "description": "Marks the start of the first symbol of a transmitted frame",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TXFRAMEEND": {
+              "description": "Marks the end of the last transmitted on-air symbol of a frame",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TXFRAMEEND": {
+                    "description": "Marks the end of the last transmitted on-air symbol of a frame",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXFRAMESTART": {
+              "description": "Marks the end of the first symbol of a received frame",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXFRAMESTART": {
+                    "description": "Marks the end of the first symbol of a received frame",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXFRAMEEND": {
+              "description": "Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXFRAMEEND": {
+                    "description": "Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ERROR": {
+              "description": "NFC error reported. The ERRORSTATUS register contains details on the source of the error.",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ERROR": {
+                    "description": "NFC error reported. The ERRORSTATUS register contains details on the source of the error.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXERROR": {
+              "description": "NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXERROR": {
+                    "description": "NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDRX": {
+              "description": "RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDRX": {
+                    "description": "RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDTX": {
+              "description": "Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDTX": {
+                    "description": "Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_AUTOCOLRESSTARTED": {
+              "description": "Auto collision resolution process has started",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_AUTOCOLRESSTARTED": {
+                    "description": "Auto collision resolution process has started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_COLLISION": {
+              "description": "NFC auto collision resolution error reported.",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_COLLISION": {
+                    "description": "NFC auto collision resolution error reported.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_SELECTED": {
+              "description": "NFC auto collision resolution successfully completed",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_SELECTED": {
+                    "description": "NFC auto collision resolution successfully completed",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STARTED": {
+              "description": "EasyDMA is ready to receive or send frames.",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STARTED": {
+                    "description": "EasyDMA is ready to receive or send frames.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FIELDDETECTED_ACTIVATE": {
+                    "description": "Shortcut between event FIELDDETECTED and task ACTIVATE",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDLOST_SENSE": {
+                    "description": "Shortcut between event FIELDLOST and task SENSE",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMEEND_ENABLERXDATA": {
+                    "description": "Shortcut between event TXFRAMEEND and task ENABLERXDATA",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Enable or disable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDDETECTED": {
+                    "description": "Enable or disable interrupt for event FIELDDETECTED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDLOST": {
+                    "description": "Enable or disable interrupt for event FIELDLOST",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMESTART": {
+                    "description": "Enable or disable interrupt for event TXFRAMESTART",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMEEND": {
+                    "description": "Enable or disable interrupt for event TXFRAMEEND",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMESTART": {
+                    "description": "Enable or disable interrupt for event RXFRAMESTART",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMEEND": {
+                    "description": "Enable or disable interrupt for event RXFRAMEEND",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Enable or disable interrupt for event ERROR",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXERROR": {
+                    "description": "Enable or disable interrupt for event RXERROR",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Enable or disable interrupt for event ENDRX",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Enable or disable interrupt for event ENDTX",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AUTOCOLRESSTARTED": {
+                    "description": "Enable or disable interrupt for event AUTOCOLRESSTARTED",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COLLISION": {
+                    "description": "Enable or disable interrupt for event COLLISION",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SELECTED": {
+                    "description": "Enable or disable interrupt for event SELECTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Enable or disable interrupt for event STARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to enable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDDETECTED": {
+                    "description": "Write '1' to enable interrupt for event FIELDDETECTED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDLOST": {
+                    "description": "Write '1' to enable interrupt for event FIELDLOST",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMESTART": {
+                    "description": "Write '1' to enable interrupt for event TXFRAMESTART",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMEEND": {
+                    "description": "Write '1' to enable interrupt for event TXFRAMEEND",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMESTART": {
+                    "description": "Write '1' to enable interrupt for event RXFRAMESTART",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMEEND": {
+                    "description": "Write '1' to enable interrupt for event RXFRAMEEND",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to enable interrupt for event ERROR",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXERROR": {
+                    "description": "Write '1' to enable interrupt for event RXERROR",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to enable interrupt for event ENDRX",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to enable interrupt for event ENDTX",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AUTOCOLRESSTARTED": {
+                    "description": "Write '1' to enable interrupt for event AUTOCOLRESSTARTED",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COLLISION": {
+                    "description": "Write '1' to enable interrupt for event COLLISION",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SELECTED": {
+                    "description": "Write '1' to enable interrupt for event SELECTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Write '1' to enable interrupt for event STARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to disable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDDETECTED": {
+                    "description": "Write '1' to disable interrupt for event FIELDDETECTED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FIELDLOST": {
+                    "description": "Write '1' to disable interrupt for event FIELDLOST",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMESTART": {
+                    "description": "Write '1' to disable interrupt for event TXFRAMESTART",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFRAMEEND": {
+                    "description": "Write '1' to disable interrupt for event TXFRAMEEND",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMESTART": {
+                    "description": "Write '1' to disable interrupt for event RXFRAMESTART",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFRAMEEND": {
+                    "description": "Write '1' to disable interrupt for event RXFRAMEEND",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Write '1' to disable interrupt for event ERROR",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXERROR": {
+                    "description": "Write '1' to disable interrupt for event RXERROR",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDRX": {
+                    "description": "Write '1' to disable interrupt for event ENDRX",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDTX": {
+                    "description": "Write '1' to disable interrupt for event ENDTX",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AUTOCOLRESSTARTED": {
+                    "description": "Write '1' to disable interrupt for event AUTOCOLRESSTARTED",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COLLISION": {
+                    "description": "Write '1' to disable interrupt for event COLLISION",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SELECTED": {
+                    "description": "Write '1' to disable interrupt for event SELECTED",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STARTED": {
+                    "description": "Write '1' to disable interrupt for event STARTED",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERRORSTATUS": {
+              "description": "NFC Error Status register",
+              "offset": 1028,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRAMEDELAYTIMEOUT": {
+                    "description": "No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "NFCTAGSTATE": {
+              "description": "NfcTag state register",
+              "offset": 1040,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "NFCTAGSTATE": {
+                    "description": "NfcTag state",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled or sense",
+                            "value": 0
+                          },
+                          "RampUp": {
+                            "description": "RampUp",
+                            "value": 2
+                          },
+                          "Idle": {
+                            "description": "Idle",
+                            "value": 3
+                          },
+                          "Receive": {
+                            "description": "Receive",
+                            "value": 4
+                          },
+                          "FrameDelay": {
+                            "description": "FrameDelay",
+                            "value": 5
+                          },
+                          "Transmit": {
+                            "description": "Transmit",
+                            "value": 6
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SLEEPSTATE": {
+              "description": "Sleep state during automatic collision resolution",
+              "offset": 1056,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SLEEPSTATE": {
+                    "description": "Reflects the sleep state during automatic collision resolution. Set to IDLE \n        by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a \n        GOSLEEP task.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Idle": {
+                            "description": "State is IDLE.",
+                            "value": 0
+                          },
+                          "SleepA": {
+                            "description": "State is SLEEP_A.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FIELDPRESENT": {
+              "description": "Indicates the presence or not of a valid field",
+              "offset": 1084,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FIELDPRESENT": {
+                    "description": "Indicates if a valid field is present. Available only in the activated state.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoField": {
+                            "description": "No valid field detected",
+                            "value": 0
+                          },
+                          "FieldPresent": {
+                            "description": "Valid field detected",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOCKDETECT": {
+                    "description": "Indicates if the low level has locked to the field",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotLocked": {
+                            "description": "Not locked to field",
+                            "value": 0
+                          },
+                          "Locked": {
+                            "description": "Locked to field",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FRAMEDELAYMIN": {
+              "description": "Minimum frame delay",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 1152,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRAMEDELAYMIN": {
+                    "description": "Minimum frame delay in number of 13.56 MHz clocks",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FRAMEDELAYMAX": {
+              "description": "Maximum frame delay",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 4096,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRAMEDELAYMAX": {
+                    "description": "Maximum frame delay in number of 13.56 MHz clocks",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "FRAMEDELAYMODE": {
+              "description": "Configuration register for the Frame Delay Timer",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRAMEDELAYMODE": {
+                    "description": "Configuration register for the Frame Delay Timer",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "FreeRun": {
+                            "description": "Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout.",
+                            "value": 0
+                          },
+                          "Window": {
+                            "description": "Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX",
+                            "value": 1
+                          },
+                          "ExactVal": {
+                            "description": "Frame is transmitted exactly at FRAMEDELAYMAX",
+                            "value": 2
+                          },
+                          "WindowGrid": {
+                            "description": "Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PACKETPTR": {
+              "description": "Packet pointer for TXD and RXD data storage in Data RAM",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTR": {
+                    "description": "Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MAXLEN": {
+              "description": "Size of the RAM buffer allocated to TXD and RXD data storage each",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAXLEN": {
+                    "description": "Size of the RAM buffer allocated to TXD and RXD data storage each",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "NFCID1_LAST": {
+              "description": "Last NFCID1 part (4, 7 or 10 bytes ID)",
+              "offset": 1424,
+              "size": 32,
+              "reset_value": 25443,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NFCID1_Z": {
+                    "description": "NFCID1 byte Z (very last byte sent)",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "NFCID1_Y": {
+                    "description": "NFCID1 byte Y",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "NFCID1_X": {
+                    "description": "NFCID1 byte X",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "NFCID1_W": {
+                    "description": "NFCID1 byte W",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "NFCID1_2ND_LAST": {
+              "description": "Second last NFCID1 part (7 or 10 bytes ID)",
+              "offset": 1428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NFCID1_V": {
+                    "description": "NFCID1 byte V",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "NFCID1_U": {
+                    "description": "NFCID1 byte U",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "NFCID1_T": {
+                    "description": "NFCID1 byte T",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "NFCID1_3RD_LAST": {
+              "description": "Third last NFCID1 part (10 bytes ID)",
+              "offset": 1432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NFCID1_S": {
+                    "description": "NFCID1 byte S",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "NFCID1_R": {
+                    "description": "NFCID1 byte R",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "NFCID1_Q": {
+                    "description": "NFCID1 byte Q",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "AUTOCOLRESCONFIG": {
+              "description": "Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled.",
+              "offset": 1436,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Enables/disables auto collision resolution",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Enabled": {
+                            "description": "Auto collision resolution enabled",
+                            "value": 0
+                          },
+                          "Disabled": {
+                            "description": "Auto collision resolution disabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SENSRES": {
+              "description": "NFC-A SENS_RES auto-response settings",
+              "offset": 1440,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BITFRAMESDD": {
+                    "description": "Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "SDD00000": {
+                            "description": "SDD pattern 00000",
+                            "value": 0
+                          },
+                          "SDD00001": {
+                            "description": "SDD pattern 00001",
+                            "value": 1
+                          },
+                          "SDD00010": {
+                            "description": "SDD pattern 00010",
+                            "value": 2
+                          },
+                          "SDD00100": {
+                            "description": "SDD pattern 00100",
+                            "value": 4
+                          },
+                          "SDD01000": {
+                            "description": "SDD pattern 01000",
+                            "value": 8
+                          },
+                          "SDD10000": {
+                            "description": "SDD pattern 10000",
+                            "value": 16
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RFU5": {
+                    "description": "Reserved for future use. Shall be 0.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NFCIDSIZE": {
+                    "description": "NFCID1 size. This value is used by the auto collision resolution engine.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NFCID1Single": {
+                            "description": "NFCID1 size: single (4 bytes)",
+                            "value": 0
+                          },
+                          "NFCID1Double": {
+                            "description": "NFCID1 size: double (7 bytes)",
+                            "value": 1
+                          },
+                          "NFCID1Triple": {
+                            "description": "NFCID1 size: triple (10 bytes)",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PLATFCONFIG": {
+                    "description": "Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "RFU74": {
+                    "description": "Reserved for future use. Shall be 0.",
+                    "offset": 12,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SELRES": {
+              "description": "NFC-A SEL_RES auto-response settings",
+              "offset": 1444,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFU10": {
+                    "description": "Reserved for future use. Shall be 0.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CASCADE": {
+                    "description": "Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RFU43": {
+                    "description": "Reserved for future use. Shall be 0.",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "PROTOCOL": {
+                    "description": "Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "RFU7": {
+                    "description": "Reserved for future use. Shall be 0.",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOTE": {
+        "description": "GPIO Tasks and Events",
+        "children": {
+          "registers": {
+            "TASKS_OUT": {
+              "description": "Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.",
+              "offset": 0,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_OUT": {
+                    "description": "Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SET": {
+              "description": "Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.",
+              "offset": 48,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SET": {
+                    "description": "Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_CLR": {
+              "description": "Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.",
+              "offset": 96,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CLR": {
+                    "description": "Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_IN": {
+              "description": "Description collection: Event generated from pin specified in CONFIG[n].PSEL",
+              "offset": 256,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_IN": {
+                    "description": "Event generated from pin specified in CONFIG[n].PSEL",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_PORT": {
+              "description": "Event generated from multiple input GPIO pins with SENSE mechanism enabled",
+              "offset": 380,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_PORT": {
+                    "description": "Event generated from multiple input GPIO pins with SENSE mechanism enabled",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN0": {
+                    "description": "Write '1' to enable interrupt for event IN[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN1": {
+                    "description": "Write '1' to enable interrupt for event IN[1]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN2": {
+                    "description": "Write '1' to enable interrupt for event IN[2]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN3": {
+                    "description": "Write '1' to enable interrupt for event IN[3]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN4": {
+                    "description": "Write '1' to enable interrupt for event IN[4]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN5": {
+                    "description": "Write '1' to enable interrupt for event IN[5]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN6": {
+                    "description": "Write '1' to enable interrupt for event IN[6]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN7": {
+                    "description": "Write '1' to enable interrupt for event IN[7]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PORT": {
+                    "description": "Write '1' to enable interrupt for event PORT",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN0": {
+                    "description": "Write '1' to disable interrupt for event IN[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN1": {
+                    "description": "Write '1' to disable interrupt for event IN[1]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN2": {
+                    "description": "Write '1' to disable interrupt for event IN[2]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN3": {
+                    "description": "Write '1' to disable interrupt for event IN[3]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN4": {
+                    "description": "Write '1' to disable interrupt for event IN[4]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN5": {
+                    "description": "Write '1' to disable interrupt for event IN[5]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN6": {
+                    "description": "Write '1' to disable interrupt for event IN[6]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IN7": {
+                    "description": "Write '1' to disable interrupt for event IN[7]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PORT": {
+                    "description": "Write '1' to disable interrupt for event PORT",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event",
+              "offset": 1296,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Mode",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.",
+                            "value": 0
+                          },
+                          "Event": {
+                            "description": "Event mode",
+                            "value": 1
+                          },
+                          "Task": {
+                            "description": "Task mode",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PSEL": {
+                    "description": "GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "PORT": {
+                    "description": "Port number",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "POLARITY": {
+                    "description": "When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "None": {
+                            "description": "Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.",
+                            "value": 0
+                          },
+                          "LoToHi": {
+                            "description": "Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.",
+                            "value": 1
+                          },
+                          "HiToLo": {
+                            "description": "Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.",
+                            "value": 2
+                          },
+                          "Toggle": {
+                            "description": "Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTINIT": {
+                    "description": "When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Task mode: Initial value of pin before task triggering is low",
+                            "value": 0
+                          },
+                          "High": {
+                            "description": "Task mode: Initial value of pin before task triggering is high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SAADC": {
+        "description": "Successive approximation register (SAR) analog-to-digital converter",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Starts the SAADC and prepares the result buffer in RAM",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Starts the SAADC and prepares the result buffer in RAM",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SAMPLE": {
+              "description": "Takes one SAADC sample",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SAMPLE": {
+                    "description": "Takes one SAADC sample",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stops the SAADC and terminates all on-going conversions",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stops the SAADC and terminates all on-going conversions",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_CALIBRATEOFFSET": {
+              "description": "Starts offset auto-calibration",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CALIBRATEOFFSET": {
+                    "description": "Starts offset auto-calibration",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STARTED": {
+              "description": "The SAADC has started",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STARTED": {
+                    "description": "The SAADC has started",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_END": {
+              "description": "The SAADC has filled up the result buffer",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_END": {
+                    "description": "The SAADC has filled up the result buffer",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_DONE": {
+              "description": "A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_DONE": {
+                    "description": "A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RESULTDONE": {
+              "description": "Result ready for transfer to RAM",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RESULTDONE": {
+                    "description": "Result ready for transfer to RAM",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CALIBRATEDONE": {
+              "description": "Calibration is complete",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CALIBRATEDONE": {
+                    "description": "Calibration is complete",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STOPPED": {
+              "description": "The SAADC has stopped",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STOPPED": {
+                    "description": "The SAADC has stopped",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Enable or disable interrupt for event STARTED",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Enable or disable interrupt for event END",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DONE": {
+                    "description": "Enable or disable interrupt for event DONE",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESULTDONE": {
+                    "description": "Enable or disable interrupt for event RESULTDONE",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CALIBRATEDONE": {
+                    "description": "Enable or disable interrupt for event CALIBRATEDONE",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for event STOPPED",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITH": {
+                    "description": "Enable or disable interrupt for event CH0LIMITH",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITL": {
+                    "description": "Enable or disable interrupt for event CH0LIMITL",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITH": {
+                    "description": "Enable or disable interrupt for event CH1LIMITH",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITL": {
+                    "description": "Enable or disable interrupt for event CH1LIMITL",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITH": {
+                    "description": "Enable or disable interrupt for event CH2LIMITH",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITL": {
+                    "description": "Enable or disable interrupt for event CH2LIMITL",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITH": {
+                    "description": "Enable or disable interrupt for event CH3LIMITH",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITL": {
+                    "description": "Enable or disable interrupt for event CH3LIMITL",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITH": {
+                    "description": "Enable or disable interrupt for event CH4LIMITH",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITL": {
+                    "description": "Enable or disable interrupt for event CH4LIMITL",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITH": {
+                    "description": "Enable or disable interrupt for event CH5LIMITH",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITL": {
+                    "description": "Enable or disable interrupt for event CH5LIMITL",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITH": {
+                    "description": "Enable or disable interrupt for event CH6LIMITH",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITL": {
+                    "description": "Enable or disable interrupt for event CH6LIMITL",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITH": {
+                    "description": "Enable or disable interrupt for event CH7LIMITH",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITL": {
+                    "description": "Enable or disable interrupt for event CH7LIMITL",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Write '1' to enable interrupt for event STARTED",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to enable interrupt for event END",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DONE": {
+                    "description": "Write '1' to enable interrupt for event DONE",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESULTDONE": {
+                    "description": "Write '1' to enable interrupt for event RESULTDONE",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CALIBRATEDONE": {
+                    "description": "Write '1' to enable interrupt for event CALIBRATEDONE",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to enable interrupt for event STOPPED",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITH": {
+                    "description": "Write '1' to enable interrupt for event CH0LIMITH",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITL": {
+                    "description": "Write '1' to enable interrupt for event CH0LIMITL",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITH": {
+                    "description": "Write '1' to enable interrupt for event CH1LIMITH",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITL": {
+                    "description": "Write '1' to enable interrupt for event CH1LIMITL",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITH": {
+                    "description": "Write '1' to enable interrupt for event CH2LIMITH",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITL": {
+                    "description": "Write '1' to enable interrupt for event CH2LIMITL",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITH": {
+                    "description": "Write '1' to enable interrupt for event CH3LIMITH",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITL": {
+                    "description": "Write '1' to enable interrupt for event CH3LIMITL",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITH": {
+                    "description": "Write '1' to enable interrupt for event CH4LIMITH",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITL": {
+                    "description": "Write '1' to enable interrupt for event CH4LIMITL",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITH": {
+                    "description": "Write '1' to enable interrupt for event CH5LIMITH",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITL": {
+                    "description": "Write '1' to enable interrupt for event CH5LIMITL",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITH": {
+                    "description": "Write '1' to enable interrupt for event CH6LIMITH",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITL": {
+                    "description": "Write '1' to enable interrupt for event CH6LIMITL",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITH": {
+                    "description": "Write '1' to enable interrupt for event CH7LIMITH",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITL": {
+                    "description": "Write '1' to enable interrupt for event CH7LIMITL",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STARTED": {
+                    "description": "Write '1' to disable interrupt for event STARTED",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "END": {
+                    "description": "Write '1' to disable interrupt for event END",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DONE": {
+                    "description": "Write '1' to disable interrupt for event DONE",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESULTDONE": {
+                    "description": "Write '1' to disable interrupt for event RESULTDONE",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CALIBRATEDONE": {
+                    "description": "Write '1' to disable interrupt for event CALIBRATEDONE",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to disable interrupt for event STOPPED",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITH": {
+                    "description": "Write '1' to disable interrupt for event CH0LIMITH",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH0LIMITL": {
+                    "description": "Write '1' to disable interrupt for event CH0LIMITL",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITH": {
+                    "description": "Write '1' to disable interrupt for event CH1LIMITH",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1LIMITL": {
+                    "description": "Write '1' to disable interrupt for event CH1LIMITL",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITH": {
+                    "description": "Write '1' to disable interrupt for event CH2LIMITH",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2LIMITL": {
+                    "description": "Write '1' to disable interrupt for event CH2LIMITL",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITH": {
+                    "description": "Write '1' to disable interrupt for event CH3LIMITH",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3LIMITL": {
+                    "description": "Write '1' to disable interrupt for event CH3LIMITL",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITH": {
+                    "description": "Write '1' to disable interrupt for event CH4LIMITH",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4LIMITL": {
+                    "description": "Write '1' to disable interrupt for event CH4LIMITL",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITH": {
+                    "description": "Write '1' to disable interrupt for event CH5LIMITH",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5LIMITL": {
+                    "description": "Write '1' to disable interrupt for event CH5LIMITL",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITH": {
+                    "description": "Write '1' to disable interrupt for event CH6LIMITH",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6LIMITL": {
+                    "description": "Write '1' to disable interrupt for event CH6LIMITL",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITH": {
+                    "description": "Write '1' to disable interrupt for event CH7LIMITH",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7LIMITL": {
+                    "description": "Write '1' to disable interrupt for event CH7LIMITL",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Status",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STATUS": {
+                    "description": "Status",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Ready": {
+                            "description": "SAADC is ready. No on-going conversions.",
+                            "value": 0
+                          },
+                          "Busy": {
+                            "description": "SAADC is busy. Conversion in progress.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable or disable SAADC",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable SAADC",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable SAADC",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable SAADC",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RESOLUTION": {
+              "description": "Resolution configuration",
+              "offset": 1520,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VAL": {
+                    "description": "Set the resolution",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "8bit": {
+                            "description": "8 bits",
+                            "value": 0
+                          },
+                          "10bit": {
+                            "description": "10 bits",
+                            "value": 1
+                          },
+                          "12bit": {
+                            "description": "12 bits",
+                            "value": 2
+                          },
+                          "14bit": {
+                            "description": "14 bits",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "OVERSAMPLE": {
+              "description": "Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.",
+              "offset": 1524,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVERSAMPLE": {
+                    "description": "Oversample control",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Bypass": {
+                            "description": "Bypass oversampling",
+                            "value": 0
+                          },
+                          "Over2x": {
+                            "description": "Oversample 2x",
+                            "value": 1
+                          },
+                          "Over4x": {
+                            "description": "Oversample 4x",
+                            "value": 2
+                          },
+                          "Over8x": {
+                            "description": "Oversample 8x",
+                            "value": 3
+                          },
+                          "Over16x": {
+                            "description": "Oversample 16x",
+                            "value": 4
+                          },
+                          "Over32x": {
+                            "description": "Oversample 32x",
+                            "value": 5
+                          },
+                          "Over64x": {
+                            "description": "Oversample 64x",
+                            "value": 6
+                          },
+                          "Over128x": {
+                            "description": "Oversample 128x",
+                            "value": 7
+                          },
+                          "Over256x": {
+                            "description": "Oversample 256x",
+                            "value": 8
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SAMPLERATE": {
+              "description": "Controls normal or continuous sample rate",
+              "offset": 1528,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC": {
+                    "description": "Capture and compare value. Sample rate is 16 MHz/CC",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "MODE": {
+                    "description": "Select mode for sample rate control",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Task": {
+                            "description": "Rate is controlled from SAMPLE task",
+                            "value": 0
+                          },
+                          "Timers": {
+                            "description": "Rate is controlled from local timer (use CC to control the rate)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIMER0": {
+        "description": "Timer/Counter 0",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start Timer",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Start Timer",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stop Timer",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop Timer",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_COUNT": {
+              "description": "Increment Timer (Counter mode only)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_COUNT": {
+                    "description": "Increment Timer (Counter mode only)",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_CLEAR": {
+              "description": "Clear time",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CLEAR": {
+                    "description": "Clear time",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SHUTDOWN": {
+              "description": "Deprecated register - Shut down timer",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SHUTDOWN": {
+                    "description": "Deprecated field -  Shut down timer",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_CAPTURE": {
+              "description": "Description collection: Capture Timer value to CC[n] register",
+              "offset": 64,
+              "size": 32,
+              "count": 6,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CAPTURE": {
+                    "description": "Capture Timer value to CC[n] register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_COMPARE": {
+              "description": "Description collection: Compare event on CC[n] match",
+              "offset": 320,
+              "size": 32,
+              "count": 6,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_COMPARE": {
+                    "description": "Compare event on CC[n] match",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMPARE0_CLEAR": {
+                    "description": "Shortcut between event COMPARE[0] and task CLEAR",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1_CLEAR": {
+                    "description": "Shortcut between event COMPARE[1] and task CLEAR",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2_CLEAR": {
+                    "description": "Shortcut between event COMPARE[2] and task CLEAR",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3_CLEAR": {
+                    "description": "Shortcut between event COMPARE[3] and task CLEAR",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE4_CLEAR": {
+                    "description": "Shortcut between event COMPARE[4] and task CLEAR",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE5_CLEAR": {
+                    "description": "Shortcut between event COMPARE[5] and task CLEAR",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0_STOP": {
+                    "description": "Shortcut between event COMPARE[0] and task STOP",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1_STOP": {
+                    "description": "Shortcut between event COMPARE[1] and task STOP",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2_STOP": {
+                    "description": "Shortcut between event COMPARE[2] and task STOP",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3_STOP": {
+                    "description": "Shortcut between event COMPARE[3] and task STOP",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE4_STOP": {
+                    "description": "Shortcut between event COMPARE[4] and task STOP",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE5_STOP": {
+                    "description": "Shortcut between event COMPARE[5] and task STOP",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMPARE0": {
+                    "description": "Write '1' to enable interrupt for event COMPARE[0]",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to enable interrupt for event COMPARE[1]",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to enable interrupt for event COMPARE[2]",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to enable interrupt for event COMPARE[3]",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE4": {
+                    "description": "Write '1' to enable interrupt for event COMPARE[4]",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE5": {
+                    "description": "Write '1' to enable interrupt for event COMPARE[5]",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMPARE0": {
+                    "description": "Write '1' to disable interrupt for event COMPARE[0]",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to disable interrupt for event COMPARE[1]",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to disable interrupt for event COMPARE[2]",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to disable interrupt for event COMPARE[3]",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE4": {
+                    "description": "Write '1' to disable interrupt for event COMPARE[4]",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE5": {
+                    "description": "Write '1' to disable interrupt for event COMPARE[5]",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Timer mode selection",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Timer mode",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Timer": {
+                            "description": "Select Timer mode",
+                            "value": 0
+                          },
+                          "Counter": {
+                            "description": "Deprecated enumerator -  Select Counter mode",
+                            "value": 1
+                          },
+                          "LowPowerCounter": {
+                            "description": "Select Low Power Counter mode",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "BITMODE": {
+              "description": "Configure the number of bits used by the TIMER",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BITMODE": {
+                    "description": "Timer bit width",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "16Bit": {
+                            "description": "16 bit timer bit width",
+                            "value": 0
+                          },
+                          "08Bit": {
+                            "description": "8 bit timer bit width",
+                            "value": 1
+                          },
+                          "24Bit": {
+                            "description": "24 bit timer bit width",
+                            "value": 2
+                          },
+                          "32Bit": {
+                            "description": "32 bit timer bit width",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PRESCALER": {
+              "description": "Timer prescaler register",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRESCALER": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CC": {
+              "description": "Description collection: Capture/Compare register n",
+              "offset": 1344,
+              "size": 32,
+              "count": 6,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC": {
+                    "description": "Capture/Compare value",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FPU": {
+        "description": "FPU",
+        "children": {
+          "registers": {
+            "UNUSED": {
+              "description": "Unused.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only"
+            }
+          }
+        }
+      },
+      "I2S": {
+        "description": "Inter-IC Sound",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Starts continuous I2S transfer. Also starts MCK generator when this is enabled.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Starts continuous I2S transfer. Also starts MCK generator when this is enabled.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RXPTRUPD": {
+              "description": "The RXD.PTR register has been copied to internal double-buffers.\n      When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RXPTRUPD": {
+                    "description": "The RXD.PTR register has been copied to internal double-buffers.\n      When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STOPPED": {
+              "description": "I2S transfer stopped.",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STOPPED": {
+                    "description": "I2S transfer stopped.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TXPTRUPD": {
+              "description": "The TDX.PTR register has been copied to internal double-buffers.\n      When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TXPTRUPD": {
+                    "description": "The TDX.PTR register has been copied to internal double-buffers.\n      When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXPTRUPD": {
+                    "description": "Enable or disable interrupt for event RXPTRUPD",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Enable or disable interrupt for event STOPPED",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXPTRUPD": {
+                    "description": "Enable or disable interrupt for event TXPTRUPD",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXPTRUPD": {
+                    "description": "Write '1' to enable interrupt for event RXPTRUPD",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to enable interrupt for event STOPPED",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXPTRUPD": {
+                    "description": "Write '1' to enable interrupt for event TXPTRUPD",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXPTRUPD": {
+                    "description": "Write '1' to disable interrupt for event RXPTRUPD",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to disable interrupt for event STOPPED",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXPTRUPD": {
+                    "description": "Write '1' to disable interrupt for event TXPTRUPD",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable I2S module.",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable I2S module.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RTC0": {
+        "description": "Real time counter 0",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start RTC COUNTER",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Start RTC COUNTER",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stop RTC COUNTER",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop RTC COUNTER",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_CLEAR": {
+              "description": "Clear RTC COUNTER",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CLEAR": {
+                    "description": "Clear RTC COUNTER",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_TRIGOVRFLW": {
+              "description": "Set COUNTER to 0xFFFFF0",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_TRIGOVRFLW": {
+                    "description": "Set COUNTER to 0xFFFFF0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TICK": {
+              "description": "Event on COUNTER increment",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TICK": {
+                    "description": "Event on COUNTER increment",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_OVRFLW": {
+              "description": "Event on COUNTER overflow",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_OVRFLW": {
+                    "description": "Event on COUNTER overflow",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_COMPARE": {
+              "description": "Description collection: Compare event on CC[n] match",
+              "offset": 320,
+              "size": 32,
+              "count": 4,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_COMPARE": {
+                    "description": "Compare event on CC[n] match",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TICK": {
+                    "description": "Write '1' to enable interrupt for event TICK",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVRFLW": {
+                    "description": "Write '1' to enable interrupt for event OVRFLW",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0": {
+                    "description": "Write '1' to enable interrupt for event COMPARE[0]",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to enable interrupt for event COMPARE[1]",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to enable interrupt for event COMPARE[2]",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to enable interrupt for event COMPARE[3]",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TICK": {
+                    "description": "Write '1' to disable interrupt for event TICK",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVRFLW": {
+                    "description": "Write '1' to disable interrupt for event OVRFLW",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0": {
+                    "description": "Write '1' to disable interrupt for event COMPARE[0]",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to disable interrupt for event COMPARE[1]",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to disable interrupt for event COMPARE[2]",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to disable interrupt for event COMPARE[3]",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVTEN": {
+              "description": "Enable or disable event routing",
+              "offset": 832,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TICK": {
+                    "description": "Enable or disable event routing for event TICK",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Disable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVRFLW": {
+                    "description": "Enable or disable event routing for event OVRFLW",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Disable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0": {
+                    "description": "Enable or disable event routing for event COMPARE[0]",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Disable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Enable or disable event routing for event COMPARE[1]",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Disable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Enable or disable event routing for event COMPARE[2]",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Disable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Enable or disable event routing for event COMPARE[3]",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Disable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVTENSET": {
+              "description": "Enable event routing",
+              "offset": 836,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TICK": {
+                    "description": "Write '1' to enable event routing for event TICK",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVRFLW": {
+                    "description": "Write '1' to enable event routing for event OVRFLW",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0": {
+                    "description": "Write '1' to enable event routing for event COMPARE[0]",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to enable event routing for event COMPARE[1]",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to enable event routing for event COMPARE[2]",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to enable event routing for event COMPARE[3]",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVTENCLR": {
+              "description": "Disable event routing",
+              "offset": 840,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TICK": {
+                    "description": "Write '1' to disable event routing for event TICK",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OVRFLW": {
+                    "description": "Write '1' to disable event routing for event OVRFLW",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE0": {
+                    "description": "Write '1' to disable event routing for event COMPARE[0]",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE1": {
+                    "description": "Write '1' to disable event routing for event COMPARE[1]",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE2": {
+                    "description": "Write '1' to disable event routing for event COMPARE[2]",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "COMPARE3": {
+                    "description": "Write '1' to disable event routing for event COMPARE[3]",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "COUNTER": {
+              "description": "Current COUNTER value",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "COUNTER": {
+                    "description": "Counter value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "PRESCALER": {
+              "description": "12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRESCALER": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "CC": {
+              "description": "Description collection: Compare register n",
+              "offset": 1344,
+              "size": 32,
+              "count": 4,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMPARE": {
+                    "description": "Compare value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TEMP": {
+        "description": "Temperature Sensor",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start temperature measurement",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Start temperature measurement",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stop temperature measurement",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop temperature measurement",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_DATARDY": {
+              "description": "Temperature measurement complete, data ready",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_DATARDY": {
+                    "description": "Temperature measurement complete, data ready",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATARDY": {
+                    "description": "Write '1' to enable interrupt for event DATARDY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATARDY": {
+                    "description": "Write '1' to disable interrupt for event DATARDY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TEMP": {
+              "description": "Temperature in degC (0.25deg steps)",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TEMP": {
+                    "description": "Temperature in degC (0.25deg steps)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "A0": {
+              "description": "Slope of 1st piece wise linear function",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 806,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A0": {
+                    "description": "Slope of 1st piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "A1": {
+              "description": "Slope of 2nd piece wise linear function",
+              "offset": 1316,
+              "size": 32,
+              "reset_value": 840,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A1": {
+                    "description": "Slope of 2nd piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "A2": {
+              "description": "Slope of 3rd piece wise linear function",
+              "offset": 1320,
+              "size": 32,
+              "reset_value": 938,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A2": {
+                    "description": "Slope of 3rd piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "A3": {
+              "description": "Slope of 4th piece wise linear function",
+              "offset": 1324,
+              "size": 32,
+              "reset_value": 1038,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A3": {
+                    "description": "Slope of 4th piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "A4": {
+              "description": "Slope of 5th piece wise linear function",
+              "offset": 1328,
+              "size": 32,
+              "reset_value": 1213,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A4": {
+                    "description": "Slope of 5th piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "A5": {
+              "description": "Slope of 6th piece wise linear function",
+              "offset": 1332,
+              "size": 32,
+              "reset_value": 1443,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "A5": {
+                    "description": "Slope of 6th piece wise linear function",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "B0": {
+              "description": "y-intercept of 1st piece wise linear function",
+              "offset": 1344,
+              "size": 32,
+              "reset_value": 16367,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B0": {
+                    "description": "y-intercept of 1st piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "B1": {
+              "description": "y-intercept of 2nd piece wise linear function",
+              "offset": 1348,
+              "size": 32,
+              "reset_value": 16318,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B1": {
+                    "description": "y-intercept of 2nd piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "B2": {
+              "description": "y-intercept of 3rd piece wise linear function",
+              "offset": 1352,
+              "size": 32,
+              "reset_value": 16318,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2": {
+                    "description": "y-intercept of 3rd piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "B3": {
+              "description": "y-intercept of 4th piece wise linear function",
+              "offset": 1356,
+              "size": 32,
+              "reset_value": 18,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B3": {
+                    "description": "y-intercept of 4th piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "B4": {
+              "description": "y-intercept of 5th piece wise linear function",
+              "offset": 1360,
+              "size": 32,
+              "reset_value": 292,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B4": {
+                    "description": "y-intercept of 5th piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "B5": {
+              "description": "y-intercept of 6th piece wise linear function",
+              "offset": 1364,
+              "size": 32,
+              "reset_value": 636,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B5": {
+                    "description": "y-intercept of 6th piece wise linear function",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "T0": {
+              "description": "End point of 1st piece wise linear function",
+              "offset": 1376,
+              "size": 32,
+              "reset_value": 226,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0": {
+                    "description": "End point of 1st piece wise linear function",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "T1": {
+              "description": "End point of 2nd piece wise linear function",
+              "offset": 1380,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T1": {
+                    "description": "End point of 2nd piece wise linear function",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "T2": {
+              "description": "End point of 3rd piece wise linear function",
+              "offset": 1384,
+              "size": 32,
+              "reset_value": 25,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T2": {
+                    "description": "End point of 3rd piece wise linear function",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "T3": {
+              "description": "End point of 4th piece wise linear function",
+              "offset": 1388,
+              "size": 32,
+              "reset_value": 60,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T3": {
+                    "description": "End point of 4th piece wise linear function",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "T4": {
+              "description": "End point of 5th piece wise linear function",
+              "offset": 1392,
+              "size": 32,
+              "reset_value": 80,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T4": {
+                    "description": "End point of 5th piece wise linear function",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RNG": {
+        "description": "Random Number Generator",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Task starting the random number generator",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Task starting the random number generator",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Task stopping the random number generator",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Task stopping the random number generator",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_VALRDY": {
+              "description": "Event being generated for every new random number written to the VALUE register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_VALRDY": {
+                    "description": "Event being generated for every new random number written to the VALUE register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VALRDY_STOP": {
+                    "description": "Shortcut between event VALRDY and task STOP",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VALRDY": {
+                    "description": "Write '1' to enable interrupt for event VALRDY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VALRDY": {
+                    "description": "Write '1' to disable interrupt for event VALRDY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DERCEN": {
+                    "description": "Bias correction",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "VALUE": {
+              "description": "Output random number",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "VALUE": {
+                    "description": "Generated random number",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ECB": {
+        "description": "AES ECB Mode Encryption",
+        "children": {
+          "registers": {
+            "TASKS_STARTECB": {
+              "description": "Start ECB block encrypt",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STARTECB": {
+                    "description": "Start ECB block encrypt",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOPECB": {
+              "description": "Abort a possible executing ECB operation",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOPECB": {
+                    "description": "Abort a possible executing ECB operation",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDECB": {
+              "description": "ECB block encrypt complete",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDECB": {
+                    "description": "ECB block encrypt complete",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ERRORECB": {
+              "description": "ECB block encrypt aborted because of a STOPECB task or due to an error",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ERRORECB": {
+                    "description": "ECB block encrypt aborted because of a STOPECB task or due to an error",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDECB": {
+                    "description": "Write '1' to enable interrupt for event ENDECB",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERRORECB": {
+                    "description": "Write '1' to enable interrupt for event ERRORECB",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDECB": {
+                    "description": "Write '1' to disable interrupt for event ENDECB",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERRORECB": {
+                    "description": "Write '1' to disable interrupt for event ERRORECB",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ECBDATAPTR": {
+              "description": "ECB block encrypt memory pointers",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECBDATAPTR": {
+                    "description": "Pointer to the ECB data structure (see Table 1 ECB data structure overview)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "AAR": {
+        "description": "Accelerated Address Resolver",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start resolving addresses based on IRKs specified in the IRK data structure",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Start resolving addresses based on IRKs specified in the IRK data structure",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stop resolving addresses",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop resolving addresses",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_END": {
+              "description": "Address resolution procedure complete",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_END": {
+                    "description": "Address resolution procedure complete",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_RESOLVED": {
+              "description": "Address resolved",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_RESOLVED": {
+                    "description": "Address resolved",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_NOTRESOLVED": {
+              "description": "Address not resolved",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_NOTRESOLVED": {
+                    "description": "Address not resolved",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END": {
+                    "description": "Write '1' to enable interrupt for event END",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESOLVED": {
+                    "description": "Write '1' to enable interrupt for event RESOLVED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NOTRESOLVED": {
+                    "description": "Write '1' to enable interrupt for event NOTRESOLVED",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "END": {
+                    "description": "Write '1' to disable interrupt for event END",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESOLVED": {
+                    "description": "Write '1' to disable interrupt for event RESOLVED",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NOTRESOLVED": {
+                    "description": "Write '1' to disable interrupt for event NOTRESOLVED",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Resolution status",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STATUS": {
+                    "description": "The IRK that was used last time an address was resolved",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable AAR",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable AAR",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "NIRK": {
+              "description": "Number of IRKs",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NIRK": {
+                    "description": "Number of Identity root keys available in the IRK data structure",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "IRKPTR": {
+              "description": "Pointer to IRK data structure",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IRKPTR": {
+                    "description": "Pointer to the IRK data structure",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ADDRPTR": {
+              "description": "Pointer to the resolvable address",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRPTR": {
+                    "description": "Pointer to the resolvable address (6-bytes)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SCRATCHPTR": {
+              "description": "Pointer to data area used for temporary storage",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCRATCHPTR": {
+                    "description": "Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CCM": {
+        "description": "AES CCM Mode Encryption",
+        "children": {
+          "registers": {
+            "TASKS_KSGEN": {
+              "description": "Start generation of key-stream. This operation will stop by itself when completed.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_KSGEN": {
+                    "description": "Start generation of key-stream. This operation will stop by itself when completed.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_CRYPT": {
+              "description": "Start encryption/decryption. This operation will stop by itself when completed.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_CRYPT": {
+                    "description": "Start encryption/decryption. This operation will stop by itself when completed.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stop encryption/decryption",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop encryption/decryption",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_RATEOVERRIDE": {
+              "description": "Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_RATEOVERRIDE": {
+                    "description": "Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDKSGEN": {
+              "description": "Key-stream generation complete",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDKSGEN": {
+                    "description": "Key-stream generation complete",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ENDCRYPT": {
+              "description": "Encrypt/decrypt complete",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ENDCRYPT": {
+                    "description": "Encrypt/decrypt complete",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ERROR": {
+              "description": "Deprecated register - CCM error event",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ERROR": {
+                    "description": "Deprecated field -  CCM error event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDKSGEN_CRYPT": {
+                    "description": "Shortcut between event ENDKSGEN and task CRYPT",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDKSGEN": {
+                    "description": "Write '1' to enable interrupt for event ENDKSGEN",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDCRYPT": {
+                    "description": "Write '1' to enable interrupt for event ENDCRYPT",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Deprecated intsetfield -  Write '1' to enable interrupt for event ERROR",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDKSGEN": {
+                    "description": "Write '1' to disable interrupt for event ENDKSGEN",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENDCRYPT": {
+                    "description": "Write '1' to disable interrupt for event ENDCRYPT",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERROR": {
+                    "description": "Deprecated intclrfield -  Write '1' to disable interrupt for event ERROR",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MICSTATUS": {
+              "description": "MIC check result",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "MICSTATUS": {
+                    "description": "The result of the MIC check performed during the previous decryption operation",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "CheckFailed": {
+                            "description": "MIC check failed",
+                            "value": 0
+                          },
+                          "CheckPassed": {
+                            "description": "MIC check passed",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable CCM",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Operation mode",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Encryption": {
+                            "description": "AES CCM packet encryption mode",
+                            "value": 0
+                          },
+                          "Decryption": {
+                            "description": "AES CCM packet decryption mode",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DATARATE": {
+                    "description": "Radio data rate that the CCM shall run synchronous with",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "1Mbit": {
+                            "description": "1 Mbps",
+                            "value": 0
+                          },
+                          "2Mbit": {
+                            "description": "2 Mbps",
+                            "value": 1
+                          },
+                          "125Kbps": {
+                            "description": "125 Kbps",
+                            "value": 2
+                          },
+                          "500Kbps": {
+                            "description": "500 Kbps",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LENGTH": {
+                    "description": "Packet length configuration",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Default": {
+                            "description": "Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated.",
+                            "value": 0
+                          },
+                          "Extended": {
+                            "description": "Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CNFPTR": {
+              "description": "Pointer to data structure holding AES key and NONCE vector",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNFPTR": {
+                    "description": "Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "INPTR": {
+              "description": "Input pointer",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INPTR": {
+                    "description": "Input pointer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OUTPTR": {
+              "description": "Output pointer",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTPTR": {
+                    "description": "Output pointer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SCRATCHPTR": {
+              "description": "Pointer to data area used for temporary storage",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCRATCHPTR": {
+                    "description": "Pointer to a scratch data area used for temporary storage during key-stream generation,\n        MIC generation and encryption/decryption.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MAXPACKETSIZE": {
+              "description": "Length of key-stream generated when MODE.LENGTH = Extended.",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 251,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAXPACKETSIZE": {
+                    "description": "Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RATEOVERRIDE": {
+              "description": "Data rate override setting.",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RATEOVERRIDE": {
+                    "description": "Data rate override setting.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "1Mbit": {
+                            "description": "1 Mbps",
+                            "value": 0
+                          },
+                          "2Mbit": {
+                            "description": "2 Mbps",
+                            "value": 1
+                          },
+                          "125Kbps": {
+                            "description": "125 Kbps",
+                            "value": 2
+                          },
+                          "500Kbps": {
+                            "description": "500 Kbps",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "WDT": {
+        "description": "Watchdog Timer",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start the watchdog",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Start the watchdog",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TIMEOUT": {
+              "description": "Watchdog timeout",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TIMEOUT": {
+                    "description": "Watchdog timeout",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMEOUT": {
+                    "description": "Write '1' to enable interrupt for event TIMEOUT",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMEOUT": {
+                    "description": "Write '1' to disable interrupt for event TIMEOUT",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RUNSTATUS": {
+              "description": "Run status",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RUNSTATUS": {
+                    "description": "Indicates whether or not the watchdog is running",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotRunning": {
+                            "description": "Watchdog not running",
+                            "value": 0
+                          },
+                          "Running": {
+                            "description": "Watchdog is running",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REQSTATUS": {
+              "description": "Request status",
+              "offset": 1028,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RR0": {
+                    "description": "Request status for RR[0] register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[0] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[0] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR1": {
+                    "description": "Request status for RR[1] register",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[1] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[1] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR2": {
+                    "description": "Request status for RR[2] register",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[2] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[2] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR3": {
+                    "description": "Request status for RR[3] register",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[3] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[3] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR4": {
+                    "description": "Request status for RR[4] register",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[4] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[4] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR5": {
+                    "description": "Request status for RR[5] register",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[5] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[5] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR6": {
+                    "description": "Request status for RR[6] register",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[6] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[6] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR7": {
+                    "description": "Request status for RR[7] register",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DisabledOrRequested": {
+                            "description": "RR[7] register is not enabled, or are already requesting reload",
+                            "value": 0
+                          },
+                          "EnabledAndUnrequested": {
+                            "description": "RR[7] register is enabled, and are not yet requesting reload",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CRV": {
+              "description": "Counter reload value",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRV": {
+                    "description": "Counter reload value in number of cycles of the 32.768 kHz clock",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RREN": {
+              "description": "Enable register for reload request registers",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RR0": {
+                    "description": "Enable or disable RR[0] register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[0] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[0] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR1": {
+                    "description": "Enable or disable RR[1] register",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[1] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[1] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR2": {
+                    "description": "Enable or disable RR[2] register",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[2] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[2] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR3": {
+                    "description": "Enable or disable RR[3] register",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[3] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[3] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR4": {
+                    "description": "Enable or disable RR[4] register",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[4] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[4] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR5": {
+                    "description": "Enable or disable RR[5] register",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[5] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[5] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR6": {
+                    "description": "Enable or disable RR[6] register",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[6] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[6] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RR7": {
+                    "description": "Enable or disable RR[7] register",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable RR[7] register",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable RR[7] register",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLEEP": {
+                    "description": "Configure the watchdog to either be paused, or kept running, while the CPU is sleeping",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Pause": {
+                            "description": "Pause watchdog while the CPU is sleeping",
+                            "value": 0
+                          },
+                          "Run": {
+                            "description": "Keep the watchdog running while the CPU is sleeping",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HALT": {
+                    "description": "Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Pause": {
+                            "description": "Pause watchdog while the CPU is halted by the debugger",
+                            "value": 0
+                          },
+                          "Run": {
+                            "description": "Keep the watchdog running while the CPU is halted by the debugger",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RR": {
+              "description": "Description collection: Reload request n",
+              "offset": 1536,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "RR": {
+                    "description": "Reload request register",
+                    "offset": 0,
+                    "size": 32,
+                    "enum": {
+                      "size": 32,
+                      "children": {
+                        "enum_fields": {
+                          "Reload": {
+                            "description": "Value to request a reload of the watchdog timer",
+                            "value": 1850885685
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "MWU": {
+        "description": "Memory Watch Unit",
+        "children": {
+          "registers": {
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Enable or disable interrupt for event REGION0WA",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Enable or disable interrupt for event REGION0RA",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Enable or disable interrupt for event REGION1WA",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Enable or disable interrupt for event REGION1RA",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Enable or disable interrupt for event REGION2WA",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Enable or disable interrupt for event REGION2RA",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Enable or disable interrupt for event REGION3WA",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Enable or disable interrupt for event REGION3RA",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Enable or disable interrupt for event PREGION0WA",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Enable or disable interrupt for event PREGION0RA",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Enable or disable interrupt for event PREGION1WA",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Enable or disable interrupt for event PREGION1RA",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Write '1' to enable interrupt for event REGION0WA",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Write '1' to enable interrupt for event REGION0RA",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Write '1' to enable interrupt for event REGION1WA",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Write '1' to enable interrupt for event REGION1RA",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Write '1' to enable interrupt for event REGION2WA",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Write '1' to enable interrupt for event REGION2RA",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Write '1' to enable interrupt for event REGION3WA",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Write '1' to enable interrupt for event REGION3RA",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Write '1' to enable interrupt for event PREGION0WA",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Write '1' to enable interrupt for event PREGION0RA",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Write '1' to enable interrupt for event PREGION1WA",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Write '1' to enable interrupt for event PREGION1RA",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Write '1' to disable interrupt for event REGION0WA",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Write '1' to disable interrupt for event REGION0RA",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Write '1' to disable interrupt for event REGION1WA",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Write '1' to disable interrupt for event REGION1RA",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Write '1' to disable interrupt for event REGION2WA",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Write '1' to disable interrupt for event REGION2RA",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Write '1' to disable interrupt for event REGION3WA",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Write '1' to disable interrupt for event REGION3RA",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Write '1' to disable interrupt for event PREGION0WA",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Write '1' to disable interrupt for event PREGION0RA",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Write '1' to disable interrupt for event PREGION1WA",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Write '1' to disable interrupt for event PREGION1RA",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "NMIEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Enable or disable interrupt for event REGION0WA",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Enable or disable interrupt for event REGION0RA",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Enable or disable interrupt for event REGION1WA",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Enable or disable interrupt for event REGION1RA",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Enable or disable interrupt for event REGION2WA",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Enable or disable interrupt for event REGION2RA",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Enable or disable interrupt for event REGION3WA",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Enable or disable interrupt for event REGION3RA",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Enable or disable interrupt for event PREGION0WA",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Enable or disable interrupt for event PREGION0RA",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Enable or disable interrupt for event PREGION1WA",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Enable or disable interrupt for event PREGION1RA",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "NMIENSET": {
+              "description": "Enable interrupt",
+              "offset": 804,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Write '1' to enable interrupt for event REGION0WA",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Write '1' to enable interrupt for event REGION0RA",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Write '1' to enable interrupt for event REGION1WA",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Write '1' to enable interrupt for event REGION1RA",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Write '1' to enable interrupt for event REGION2WA",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Write '1' to enable interrupt for event REGION2RA",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Write '1' to enable interrupt for event REGION3WA",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Write '1' to enable interrupt for event REGION3RA",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Write '1' to enable interrupt for event PREGION0WA",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Write '1' to enable interrupt for event PREGION0RA",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Write '1' to enable interrupt for event PREGION1WA",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Write '1' to enable interrupt for event PREGION1RA",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "NMIENCLR": {
+              "description": "Disable interrupt",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION0WA": {
+                    "description": "Write '1' to disable interrupt for event REGION0WA",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION0RA": {
+                    "description": "Write '1' to disable interrupt for event REGION0RA",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1WA": {
+                    "description": "Write '1' to disable interrupt for event REGION1WA",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION1RA": {
+                    "description": "Write '1' to disable interrupt for event REGION1RA",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2WA": {
+                    "description": "Write '1' to disable interrupt for event REGION2WA",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION2RA": {
+                    "description": "Write '1' to disable interrupt for event REGION2RA",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3WA": {
+                    "description": "Write '1' to disable interrupt for event REGION3WA",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REGION3RA": {
+                    "description": "Write '1' to disable interrupt for event REGION3RA",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0WA": {
+                    "description": "Write '1' to disable interrupt for event PREGION0WA",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION0RA": {
+                    "description": "Write '1' to disable interrupt for event PREGION0RA",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1WA": {
+                    "description": "Write '1' to disable interrupt for event PREGION1WA",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PREGION1RA": {
+                    "description": "Write '1' to disable interrupt for event PREGION1RA",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REGIONEN": {
+              "description": "Enable/disable regions watch",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RGN0WA": {
+                    "description": "Enable/disable write access watch in region[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN0RA": {
+                    "description": "Enable/disable read access watch in region[0]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1WA": {
+                    "description": "Enable/disable write access watch in region[1]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1RA": {
+                    "description": "Enable/disable read access watch in region[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2WA": {
+                    "description": "Enable/disable write access watch in region[2]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2RA": {
+                    "description": "Enable/disable read access watch in region[2]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3WA": {
+                    "description": "Enable/disable write access watch in region[3]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3RA": {
+                    "description": "Enable/disable read access watch in region[3]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this region",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this region",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0WA": {
+                    "description": "Enable/disable write access watch in PREGION[0]",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this PREGION",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this PREGION",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0RA": {
+                    "description": "Enable/disable read access watch in PREGION[0]",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this PREGION",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this PREGION",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1WA": {
+                    "description": "Enable/disable write access watch in PREGION[1]",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable write access watch in this PREGION",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable write access watch in this PREGION",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1RA": {
+                    "description": "Enable/disable read access watch in PREGION[1]",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disable": {
+                            "description": "Disable read access watch in this PREGION",
+                            "value": 0
+                          },
+                          "Enable": {
+                            "description": "Enable read access watch in this PREGION",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REGIONENSET": {
+              "description": "Enable regions watch",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RGN0WA": {
+                    "description": "Enable write access watch in region[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN0RA": {
+                    "description": "Enable read access watch in region[0]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1WA": {
+                    "description": "Enable write access watch in region[1]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1RA": {
+                    "description": "Enable read access watch in region[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2WA": {
+                    "description": "Enable write access watch in region[2]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2RA": {
+                    "description": "Enable read access watch in region[2]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3WA": {
+                    "description": "Enable write access watch in region[3]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3RA": {
+                    "description": "Enable read access watch in region[3]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0WA": {
+                    "description": "Enable write access watch in PREGION[0]",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0RA": {
+                    "description": "Enable read access watch in PREGION[0]",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1WA": {
+                    "description": "Enable write access watch in PREGION[1]",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1RA": {
+                    "description": "Enable read access watch in PREGION[1]",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REGIONENCLR": {
+              "description": "Disable regions watch",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RGN0WA": {
+                    "description": "Disable write access watch in region[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN0RA": {
+                    "description": "Disable read access watch in region[0]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1WA": {
+                    "description": "Disable write access watch in region[1]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN1RA": {
+                    "description": "Disable read access watch in region[1]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2WA": {
+                    "description": "Disable write access watch in region[2]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN2RA": {
+                    "description": "Disable read access watch in region[2]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3WA": {
+                    "description": "Disable write access watch in region[3]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RGN3RA": {
+                    "description": "Disable read access watch in region[3]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this region is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this region is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0WA": {
+                    "description": "Disable write access watch in PREGION[0]",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN0RA": {
+                    "description": "Disable read access watch in PREGION[0]",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1WA": {
+                    "description": "Disable write access watch in PREGION[1]",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Write access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Write access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PRGN1RA": {
+                    "description": "Disable read access watch in PREGION[1]",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read access watch in this PREGION is disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read access watch in this PREGION is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "QDEC": {
+        "description": "Quadrature Decoder",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Task starting the quadrature decoder",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Task starting the quadrature decoder",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Task stopping the quadrature decoder",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Task stopping the quadrature decoder",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_READCLRACC": {
+              "description": "Read and clear ACC and ACCDBL",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_READCLRACC": {
+                    "description": "Read and clear ACC and ACCDBL",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_RDCLRACC": {
+              "description": "Read and clear ACC",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_RDCLRACC": {
+                    "description": "Read and clear ACC",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_RDCLRDBL": {
+              "description": "Read and clear ACCDBL",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_RDCLRDBL": {
+                    "description": "Read and clear ACCDBL",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_SAMPLERDY": {
+              "description": "Event being generated for every new sample value written to the SAMPLE register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_SAMPLERDY": {
+                    "description": "Event being generated for every new sample value written to the SAMPLE register",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_REPORTRDY": {
+              "description": "Non-null report ready",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_REPORTRDY": {
+                    "description": "Non-null report ready",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_ACCOF": {
+              "description": "ACC or ACCDBL register overflow",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_ACCOF": {
+                    "description": "ACC or ACCDBL register overflow",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_DBLRDY": {
+              "description": "Double displacement(s) detected",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_DBLRDY": {
+                    "description": "Double displacement(s) detected",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_STOPPED": {
+              "description": "QDEC has been stopped",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_STOPPED": {
+                    "description": "QDEC has been stopped",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REPORTRDY_READCLRACC": {
+                    "description": "Shortcut between event REPORTRDY and task READCLRACC",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SAMPLERDY_STOP": {
+                    "description": "Shortcut between event SAMPLERDY and task STOP",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REPORTRDY_RDCLRACC": {
+                    "description": "Shortcut between event REPORTRDY and task RDCLRACC",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REPORTRDY_STOP": {
+                    "description": "Shortcut between event REPORTRDY and task STOP",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DBLRDY_RDCLRDBL": {
+                    "description": "Shortcut between event DBLRDY and task RDCLRDBL",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DBLRDY_STOP": {
+                    "description": "Shortcut between event DBLRDY and task STOP",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SAMPLERDY_READCLRACC": {
+                    "description": "Shortcut between event SAMPLERDY and task READCLRACC",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SAMPLERDY": {
+                    "description": "Write '1' to enable interrupt for event SAMPLERDY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REPORTRDY": {
+                    "description": "Write '1' to enable interrupt for event REPORTRDY",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ACCOF": {
+                    "description": "Write '1' to enable interrupt for event ACCOF",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DBLRDY": {
+                    "description": "Write '1' to enable interrupt for event DBLRDY",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to enable interrupt for event STOPPED",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SAMPLERDY": {
+                    "description": "Write '1' to disable interrupt for event SAMPLERDY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REPORTRDY": {
+                    "description": "Write '1' to disable interrupt for event REPORTRDY",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ACCOF": {
+                    "description": "Write '1' to disable interrupt for event ACCOF",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DBLRDY": {
+                    "description": "Write '1' to disable interrupt for event DBLRDY",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOPPED": {
+                    "description": "Write '1' to disable interrupt for event STOPPED",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable the quadrature decoder",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable the quadrature decoder",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LEDPOL": {
+              "description": "LED output pin polarity",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEDPOL": {
+                    "description": "LED output pin polarity",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ActiveLow": {
+                            "description": "Led active on output pin low",
+                            "value": 0
+                          },
+                          "ActiveHigh": {
+                            "description": "Led active on output pin high",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SAMPLEPER": {
+              "description": "Sample period",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SAMPLEPER": {
+                    "description": "Sample period. The SAMPLE register will be updated for every new sample",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "128us": {
+                            "description": "128 us",
+                            "value": 0
+                          },
+                          "256us": {
+                            "description": "256 us",
+                            "value": 1
+                          },
+                          "512us": {
+                            "description": "512 us",
+                            "value": 2
+                          },
+                          "1024us": {
+                            "description": "1024 us",
+                            "value": 3
+                          },
+                          "2048us": {
+                            "description": "2048 us",
+                            "value": 4
+                          },
+                          "4096us": {
+                            "description": "4096 us",
+                            "value": 5
+                          },
+                          "8192us": {
+                            "description": "8192 us",
+                            "value": 6
+                          },
+                          "16384us": {
+                            "description": "16384 us",
+                            "value": 7
+                          },
+                          "32ms": {
+                            "description": "32768 us",
+                            "value": 8
+                          },
+                          "65ms": {
+                            "description": "65536 us",
+                            "value": 9
+                          },
+                          "131ms": {
+                            "description": "131072 us",
+                            "value": 10
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SAMPLE": {
+              "description": "Motion sample value",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SAMPLE": {
+                    "description": "Last motion sample",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REPORTPER": {
+              "description": "Number of samples to be taken before REPORTRDY and DBLRDY events can be generated",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REPORTPER": {
+                    "description": "Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "10Smpl": {
+                            "description": "10 samples / report",
+                            "value": 0
+                          },
+                          "40Smpl": {
+                            "description": "40 samples / report",
+                            "value": 1
+                          },
+                          "80Smpl": {
+                            "description": "80 samples / report",
+                            "value": 2
+                          },
+                          "120Smpl": {
+                            "description": "120 samples / report",
+                            "value": 3
+                          },
+                          "160Smpl": {
+                            "description": "160 samples / report",
+                            "value": 4
+                          },
+                          "200Smpl": {
+                            "description": "200 samples / report",
+                            "value": 5
+                          },
+                          "240Smpl": {
+                            "description": "240 samples / report",
+                            "value": 6
+                          },
+                          "280Smpl": {
+                            "description": "280 samples / report",
+                            "value": 7
+                          },
+                          "1Smpl": {
+                            "description": "1 sample / report",
+                            "value": 8
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ACC": {
+              "description": "Register accumulating the valid transitions",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACC": {
+                    "description": "Register accumulating all valid samples (not double transition) read from the SAMPLE register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ACCREAD": {
+              "description": "Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACCREAD": {
+                    "description": "Snapshot of the ACC register.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DBFEN": {
+              "description": "Enable input debounce filters",
+              "offset": 1320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBFEN": {
+                    "description": "Enable input debounce filters",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Debounce input filters disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Debounce input filters enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LEDPRE": {
+              "description": "Time period the LED is switched ON prior to sampling",
+              "offset": 1344,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEDPRE": {
+                    "description": "Period in us the LED is switched on prior to sampling",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "ACCDBL": {
+              "description": "Register accumulating the number of detected double transitions",
+              "offset": 1348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACCDBL": {
+                    "description": "Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "ACCDBLREAD": {
+              "description": "Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task",
+              "offset": 1352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACCDBLREAD": {
+                    "description": "Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "COMP": {
+        "description": "Comparator",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start comparator",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Start comparator",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stop comparator",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop comparator",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SAMPLE": {
+              "description": "Sample comparator value",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SAMPLE": {
+                    "description": "Sample comparator value",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_READY": {
+              "description": "COMP is ready and output is valid",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_READY": {
+                    "description": "COMP is ready and output is valid",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_DOWN": {
+              "description": "Downward crossing",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_DOWN": {
+                    "description": "Downward crossing",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_UP": {
+              "description": "Upward crossing",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_UP": {
+                    "description": "Upward crossing",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CROSS": {
+              "description": "Downward or upward crossing",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CROSS": {
+                    "description": "Downward or upward crossing",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY_SAMPLE": {
+                    "description": "Shortcut between event READY and task SAMPLE",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READY_STOP": {
+                    "description": "Shortcut between event READY and task STOP",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN_STOP": {
+                    "description": "Shortcut between event DOWN and task STOP",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP_STOP": {
+                    "description": "Shortcut between event UP and task STOP",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS_STOP": {
+                    "description": "Shortcut between event CROSS and task STOP",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Enable or disable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN": {
+                    "description": "Enable or disable interrupt for event DOWN",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP": {
+                    "description": "Enable or disable interrupt for event UP",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS": {
+                    "description": "Enable or disable interrupt for event CROSS",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to enable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN": {
+                    "description": "Write '1' to enable interrupt for event DOWN",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP": {
+                    "description": "Write '1' to enable interrupt for event UP",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS": {
+                    "description": "Write '1' to enable interrupt for event CROSS",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to disable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN": {
+                    "description": "Write '1' to disable interrupt for event DOWN",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP": {
+                    "description": "Write '1' to disable interrupt for event UP",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS": {
+                    "description": "Write '1' to disable interrupt for event CROSS",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RESULT": {
+              "description": "Compare result",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RESULT": {
+                    "description": "Result of last compare. Decision point SAMPLE task.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Below": {
+                            "description": "Input voltage is below the threshold (VIN+ < VIN-)",
+                            "value": 0
+                          },
+                          "Above": {
+                            "description": "Input voltage is above the threshold (VIN+ > VIN-)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "COMP enable",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable COMP",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PSEL": {
+              "description": "Pin select",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSEL": {
+                    "description": "Analog pin select",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "AnalogInput0": {
+                            "description": "AIN0 selected as analog input",
+                            "value": 0
+                          },
+                          "AnalogInput1": {
+                            "description": "AIN1 selected as analog input",
+                            "value": 1
+                          },
+                          "AnalogInput2": {
+                            "description": "AIN2 selected as analog input",
+                            "value": 2
+                          },
+                          "AnalogInput3": {
+                            "description": "AIN3 selected as analog input",
+                            "value": 3
+                          },
+                          "AnalogInput4": {
+                            "description": "AIN4 selected as analog input",
+                            "value": 4
+                          },
+                          "AnalogInput5": {
+                            "description": "AIN5 selected as analog input",
+                            "value": 5
+                          },
+                          "AnalogInput6": {
+                            "description": "AIN6 selected as analog input",
+                            "value": 6
+                          },
+                          "AnalogInput7": {
+                            "description": "AIN7 selected as analog input",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REFSEL": {
+              "description": "Reference source select for single-ended mode",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REFSEL": {
+                    "description": "Reference select",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "Int1V2": {
+                            "description": "VREF = internal 1.2 V reference (VDD >= 1.7 V)",
+                            "value": 0
+                          },
+                          "Int1V8": {
+                            "description": "VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)",
+                            "value": 1
+                          },
+                          "Int2V4": {
+                            "description": "VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)",
+                            "value": 2
+                          },
+                          "VDD": {
+                            "description": "VREF = VDD",
+                            "value": 4
+                          },
+                          "ARef": {
+                            "description": "VREF = AREF (VDD >= VREF >= AREFMIN)",
+                            "value": 5
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EXTREFSEL": {
+              "description": "External reference select",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTREFSEL": {
+                    "description": "External analog reference select",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "AnalogReference0": {
+                            "description": "Use AIN0 as external analog reference",
+                            "value": 0
+                          },
+                          "AnalogReference1": {
+                            "description": "Use AIN1 as external analog reference",
+                            "value": 1
+                          },
+                          "AnalogReference2": {
+                            "description": "Use AIN2 as external analog reference",
+                            "value": 2
+                          },
+                          "AnalogReference3": {
+                            "description": "Use AIN3 as external analog reference",
+                            "value": 3
+                          },
+                          "AnalogReference4": {
+                            "description": "Use AIN4 as external analog reference",
+                            "value": 4
+                          },
+                          "AnalogReference5": {
+                            "description": "Use AIN5 as external analog reference",
+                            "value": 5
+                          },
+                          "AnalogReference6": {
+                            "description": "Use AIN6 as external analog reference",
+                            "value": 6
+                          },
+                          "AnalogReference7": {
+                            "description": "Use AIN7 as external analog reference",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TH": {
+              "description": "Threshold configuration for hysteresis unit",
+              "offset": 1328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "THDOWN": {
+                    "description": "VDOWN = (THDOWN+1)/64*VREF",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "THUP": {
+                    "description": "VUP = (THUP+1)/64*VREF",
+                    "offset": 8,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "Mode configuration",
+              "offset": 1332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SP": {
+                    "description": "Speed and power modes",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Low": {
+                            "description": "Low-power mode",
+                            "value": 0
+                          },
+                          "Normal": {
+                            "description": "Normal mode",
+                            "value": 1
+                          },
+                          "High": {
+                            "description": "High-speed mode",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MAIN": {
+                    "description": "Main operation modes",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "SE": {
+                            "description": "Single-ended mode",
+                            "value": 0
+                          },
+                          "Diff": {
+                            "description": "Differential mode",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "HYST": {
+              "description": "Comparator hysteresis enable",
+              "offset": 1336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HYST": {
+                    "description": "Comparator hysteresis",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoHyst": {
+                            "description": "Comparator hysteresis disabled",
+                            "value": 0
+                          },
+                          "Hyst50mV": {
+                            "description": "Comparator hysteresis enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "LPCOMP": {
+        "description": "Low Power Comparator",
+        "children": {
+          "registers": {
+            "TASKS_START": {
+              "description": "Start comparator",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_START": {
+                    "description": "Start comparator",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_STOP": {
+              "description": "Stop comparator",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_STOP": {
+                    "description": "Stop comparator",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TASKS_SAMPLE": {
+              "description": "Sample comparator value",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_SAMPLE": {
+                    "description": "Sample comparator value",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_READY": {
+              "description": "LPCOMP is ready and output is valid",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_READY": {
+                    "description": "LPCOMP is ready and output is valid",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_DOWN": {
+              "description": "Downward crossing",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_DOWN": {
+                    "description": "Downward crossing",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_UP": {
+              "description": "Upward crossing",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_UP": {
+                    "description": "Upward crossing",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_CROSS": {
+              "description": "Downward or upward crossing",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_CROSS": {
+                    "description": "Downward or upward crossing",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SHORTS": {
+              "description": "Shortcuts between local events and tasks",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY_SAMPLE": {
+                    "description": "Shortcut between event READY and task SAMPLE",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "READY_STOP": {
+                    "description": "Shortcut between event READY and task STOP",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN_STOP": {
+                    "description": "Shortcut between event DOWN and task STOP",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP_STOP": {
+                    "description": "Shortcut between event UP and task STOP",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS_STOP": {
+                    "description": "Shortcut between event CROSS and task STOP",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable shortcut",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable shortcut",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to enable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN": {
+                    "description": "Write '1' to enable interrupt for event DOWN",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP": {
+                    "description": "Write '1' to enable interrupt for event UP",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS": {
+                    "description": "Write '1' to enable interrupt for event CROSS",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "Write '1' to disable interrupt for event READY",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOWN": {
+                    "description": "Write '1' to disable interrupt for event DOWN",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "UP": {
+                    "description": "Write '1' to disable interrupt for event UP",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CROSS": {
+                    "description": "Write '1' to disable interrupt for event CROSS",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RESULT": {
+              "description": "Compare result",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RESULT": {
+                    "description": "Result of last compare. Decision point SAMPLE task.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Below": {
+                            "description": "Input voltage is below the reference threshold (VIN+ < VIN-).",
+                            "value": 0
+                          },
+                          "Above": {
+                            "description": "Input voltage is above the reference threshold (VIN+ > VIN-).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "Enable LPCOMP",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable or disable LPCOMP",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PSEL": {
+              "description": "Input pin select",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSEL": {
+                    "description": "Analog pin select",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "AnalogInput0": {
+                            "description": "AIN0 selected as analog input",
+                            "value": 0
+                          },
+                          "AnalogInput1": {
+                            "description": "AIN1 selected as analog input",
+                            "value": 1
+                          },
+                          "AnalogInput2": {
+                            "description": "AIN2 selected as analog input",
+                            "value": 2
+                          },
+                          "AnalogInput3": {
+                            "description": "AIN3 selected as analog input",
+                            "value": 3
+                          },
+                          "AnalogInput4": {
+                            "description": "AIN4 selected as analog input",
+                            "value": 4
+                          },
+                          "AnalogInput5": {
+                            "description": "AIN5 selected as analog input",
+                            "value": 5
+                          },
+                          "AnalogInput6": {
+                            "description": "AIN6 selected as analog input",
+                            "value": 6
+                          },
+                          "AnalogInput7": {
+                            "description": "AIN7 selected as analog input",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "REFSEL": {
+              "description": "Reference select",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REFSEL": {
+                    "description": "Reference select",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "Ref1_8Vdd": {
+                            "description": "VDD * 1/8 selected as reference",
+                            "value": 0
+                          },
+                          "Ref2_8Vdd": {
+                            "description": "VDD * 2/8 selected as reference",
+                            "value": 1
+                          },
+                          "Ref3_8Vdd": {
+                            "description": "VDD * 3/8 selected as reference",
+                            "value": 2
+                          },
+                          "Ref4_8Vdd": {
+                            "description": "VDD * 4/8 selected as reference",
+                            "value": 3
+                          },
+                          "Ref5_8Vdd": {
+                            "description": "VDD * 5/8 selected as reference",
+                            "value": 4
+                          },
+                          "Ref6_8Vdd": {
+                            "description": "VDD * 6/8 selected as reference",
+                            "value": 5
+                          },
+                          "Ref7_8Vdd": {
+                            "description": "VDD * 7/8 selected as reference",
+                            "value": 6
+                          },
+                          "ARef": {
+                            "description": "External analog reference selected",
+                            "value": 7
+                          },
+                          "Ref1_16Vdd": {
+                            "description": "VDD * 1/16 selected as reference",
+                            "value": 8
+                          },
+                          "Ref3_16Vdd": {
+                            "description": "VDD * 3/16 selected as reference",
+                            "value": 9
+                          },
+                          "Ref5_16Vdd": {
+                            "description": "VDD * 5/16 selected as reference",
+                            "value": 10
+                          },
+                          "Ref7_16Vdd": {
+                            "description": "VDD * 7/16 selected as reference",
+                            "value": 11
+                          },
+                          "Ref9_16Vdd": {
+                            "description": "VDD * 9/16 selected as reference",
+                            "value": 12
+                          },
+                          "Ref11_16Vdd": {
+                            "description": "VDD * 11/16 selected as reference",
+                            "value": 13
+                          },
+                          "Ref13_16Vdd": {
+                            "description": "VDD * 13/16 selected as reference",
+                            "value": 14
+                          },
+                          "Ref15_16Vdd": {
+                            "description": "VDD * 15/16 selected as reference",
+                            "value": 15
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EXTREFSEL": {
+              "description": "External reference select",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTREFSEL": {
+                    "description": "External analog reference select",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "AnalogReference0": {
+                            "description": "Use AIN0 as external analog reference",
+                            "value": 0
+                          },
+                          "AnalogReference1": {
+                            "description": "Use AIN1 as external analog reference",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ANADETECT": {
+              "description": "Analog detect configuration",
+              "offset": 1312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ANADETECT": {
+                    "description": "Analog detect configuration",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Cross": {
+                            "description": "Generate ANADETECT on crossing, both upward crossing and downward crossing",
+                            "value": 0
+                          },
+                          "Up": {
+                            "description": "Generate ANADETECT on upward crossing only",
+                            "value": 1
+                          },
+                          "Down": {
+                            "description": "Generate ANADETECT on downward crossing only",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "HYST": {
+              "description": "Comparator hysteresis enable",
+              "offset": 1336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HYST": {
+                    "description": "Comparator hysteresis enable",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Comparator hysteresis disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Comparator hysteresis enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EGU0": {
+        "description": "Event Generator Unit 0",
+        "children": {
+          "registers": {
+            "TASKS_TRIGGER": {
+              "description": "Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event",
+              "offset": 0,
+              "size": 32,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TASKS_TRIGGER": {
+                    "description": "Trigger n for triggering the corresponding TRIGGERED[n] event",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Trigger": {
+                            "description": "Trigger task",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EVENTS_TRIGGERED": {
+              "description": "Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task",
+              "offset": 256,
+              "size": 32,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVENTS_TRIGGERED": {
+                    "description": "Event number n generated by triggering the corresponding TRIGGER[n] task",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NotGenerated": {
+                            "description": "Event not generated",
+                            "value": 0
+                          },
+                          "Generated": {
+                            "description": "Event generated",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Enable or disable interrupt",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRIGGERED0": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED1": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[1]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED2": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[2]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED3": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[3]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED4": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[4]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED5": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[5]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED6": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[6]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED7": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[7]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED8": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[8]",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED9": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[9]",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED10": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[10]",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED11": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[11]",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED12": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[12]",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED13": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[13]",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED14": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[14]",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED15": {
+                    "description": "Enable or disable interrupt for event TRIGGERED[15]",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENSET": {
+              "description": "Enable interrupt",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRIGGERED0": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED1": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[1]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED2": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[2]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED3": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[3]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED4": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[4]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED5": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[5]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED6": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[6]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED7": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[7]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED8": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[8]",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED9": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[9]",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED10": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[10]",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED11": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[11]",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED12": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[12]",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED13": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[13]",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED14": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[14]",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED15": {
+                    "description": "Write '1' to enable interrupt for event TRIGGERED[15]",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTENCLR": {
+              "description": "Disable interrupt",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRIGGERED0": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[0]",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED1": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[1]",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED2": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[2]",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED3": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[3]",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED4": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[4]",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED5": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[5]",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED6": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[6]",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED7": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[7]",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED8": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[8]",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED9": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[9]",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED10": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[10]",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED11": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[11]",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED12": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[12]",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED13": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[13]",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED14": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[14]",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TRIGGERED15": {
+                    "description": "Write '1' to disable interrupt for event TRIGGERED[15]",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: Disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: Enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SWI0": {
+        "description": "Software interrupt 0",
+        "children": {
+          "registers": {
+            "UNUSED": {
+              "description": "Unused.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only"
+            }
+          }
+        }
+      },
+      "PPI": {
+        "description": "Programmable Peripheral Interconnect",
+        "children": {
+          "registers": {
+            "CHEN": {
+              "description": "Channel enable register",
+              "offset": 1280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0": {
+                    "description": "Enable or disable channel 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1": {
+                    "description": "Enable or disable channel 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2": {
+                    "description": "Enable or disable channel 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3": {
+                    "description": "Enable or disable channel 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4": {
+                    "description": "Enable or disable channel 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5": {
+                    "description": "Enable or disable channel 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6": {
+                    "description": "Enable or disable channel 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7": {
+                    "description": "Enable or disable channel 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH8": {
+                    "description": "Enable or disable channel 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH9": {
+                    "description": "Enable or disable channel 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH10": {
+                    "description": "Enable or disable channel 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH11": {
+                    "description": "Enable or disable channel 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH12": {
+                    "description": "Enable or disable channel 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH13": {
+                    "description": "Enable or disable channel 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH14": {
+                    "description": "Enable or disable channel 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH15": {
+                    "description": "Enable or disable channel 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH16": {
+                    "description": "Enable or disable channel 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH17": {
+                    "description": "Enable or disable channel 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH18": {
+                    "description": "Enable or disable channel 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH19": {
+                    "description": "Enable or disable channel 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH20": {
+                    "description": "Enable or disable channel 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH21": {
+                    "description": "Enable or disable channel 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH22": {
+                    "description": "Enable or disable channel 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH23": {
+                    "description": "Enable or disable channel 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH24": {
+                    "description": "Enable or disable channel 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH25": {
+                    "description": "Enable or disable channel 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH26": {
+                    "description": "Enable or disable channel 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH27": {
+                    "description": "Enable or disable channel 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH28": {
+                    "description": "Enable or disable channel 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH29": {
+                    "description": "Enable or disable channel 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH30": {
+                    "description": "Enable or disable channel 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH31": {
+                    "description": "Enable or disable channel 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable channel",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable channel",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CHENSET": {
+              "description": "Channel enable set register",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0": {
+                    "description": "Channel 0 enable set register.  Writing '0' has no effect",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1": {
+                    "description": "Channel 1 enable set register.  Writing '0' has no effect",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2": {
+                    "description": "Channel 2 enable set register.  Writing '0' has no effect",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3": {
+                    "description": "Channel 3 enable set register.  Writing '0' has no effect",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4": {
+                    "description": "Channel 4 enable set register.  Writing '0' has no effect",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5": {
+                    "description": "Channel 5 enable set register.  Writing '0' has no effect",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6": {
+                    "description": "Channel 6 enable set register.  Writing '0' has no effect",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7": {
+                    "description": "Channel 7 enable set register.  Writing '0' has no effect",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH8": {
+                    "description": "Channel 8 enable set register.  Writing '0' has no effect",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH9": {
+                    "description": "Channel 9 enable set register.  Writing '0' has no effect",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH10": {
+                    "description": "Channel 10 enable set register.  Writing '0' has no effect",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH11": {
+                    "description": "Channel 11 enable set register.  Writing '0' has no effect",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH12": {
+                    "description": "Channel 12 enable set register.  Writing '0' has no effect",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH13": {
+                    "description": "Channel 13 enable set register.  Writing '0' has no effect",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH14": {
+                    "description": "Channel 14 enable set register.  Writing '0' has no effect",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH15": {
+                    "description": "Channel 15 enable set register.  Writing '0' has no effect",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH16": {
+                    "description": "Channel 16 enable set register.  Writing '0' has no effect",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH17": {
+                    "description": "Channel 17 enable set register.  Writing '0' has no effect",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH18": {
+                    "description": "Channel 18 enable set register.  Writing '0' has no effect",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH19": {
+                    "description": "Channel 19 enable set register.  Writing '0' has no effect",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH20": {
+                    "description": "Channel 20 enable set register.  Writing '0' has no effect",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH21": {
+                    "description": "Channel 21 enable set register.  Writing '0' has no effect",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH22": {
+                    "description": "Channel 22 enable set register.  Writing '0' has no effect",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH23": {
+                    "description": "Channel 23 enable set register.  Writing '0' has no effect",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH24": {
+                    "description": "Channel 24 enable set register.  Writing '0' has no effect",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH25": {
+                    "description": "Channel 25 enable set register.  Writing '0' has no effect",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH26": {
+                    "description": "Channel 26 enable set register.  Writing '0' has no effect",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH27": {
+                    "description": "Channel 27 enable set register.  Writing '0' has no effect",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH28": {
+                    "description": "Channel 28 enable set register.  Writing '0' has no effect",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH29": {
+                    "description": "Channel 29 enable set register.  Writing '0' has no effect",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH30": {
+                    "description": "Channel 30 enable set register.  Writing '0' has no effect",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH31": {
+                    "description": "Channel 31 enable set register.  Writing '0' has no effect",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CHENCLR": {
+              "description": "Channel enable clear register",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0": {
+                    "description": "Channel 0 enable clear register.  Writing '0' has no effect",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1": {
+                    "description": "Channel 1 enable clear register.  Writing '0' has no effect",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2": {
+                    "description": "Channel 2 enable clear register.  Writing '0' has no effect",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3": {
+                    "description": "Channel 3 enable clear register.  Writing '0' has no effect",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4": {
+                    "description": "Channel 4 enable clear register.  Writing '0' has no effect",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5": {
+                    "description": "Channel 5 enable clear register.  Writing '0' has no effect",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6": {
+                    "description": "Channel 6 enable clear register.  Writing '0' has no effect",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7": {
+                    "description": "Channel 7 enable clear register.  Writing '0' has no effect",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH8": {
+                    "description": "Channel 8 enable clear register.  Writing '0' has no effect",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH9": {
+                    "description": "Channel 9 enable clear register.  Writing '0' has no effect",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH10": {
+                    "description": "Channel 10 enable clear register.  Writing '0' has no effect",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH11": {
+                    "description": "Channel 11 enable clear register.  Writing '0' has no effect",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH12": {
+                    "description": "Channel 12 enable clear register.  Writing '0' has no effect",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH13": {
+                    "description": "Channel 13 enable clear register.  Writing '0' has no effect",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH14": {
+                    "description": "Channel 14 enable clear register.  Writing '0' has no effect",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH15": {
+                    "description": "Channel 15 enable clear register.  Writing '0' has no effect",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH16": {
+                    "description": "Channel 16 enable clear register.  Writing '0' has no effect",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH17": {
+                    "description": "Channel 17 enable clear register.  Writing '0' has no effect",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH18": {
+                    "description": "Channel 18 enable clear register.  Writing '0' has no effect",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH19": {
+                    "description": "Channel 19 enable clear register.  Writing '0' has no effect",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH20": {
+                    "description": "Channel 20 enable clear register.  Writing '0' has no effect",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH21": {
+                    "description": "Channel 21 enable clear register.  Writing '0' has no effect",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH22": {
+                    "description": "Channel 22 enable clear register.  Writing '0' has no effect",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH23": {
+                    "description": "Channel 23 enable clear register.  Writing '0' has no effect",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH24": {
+                    "description": "Channel 24 enable clear register.  Writing '0' has no effect",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH25": {
+                    "description": "Channel 25 enable clear register.  Writing '0' has no effect",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH26": {
+                    "description": "Channel 26 enable clear register.  Writing '0' has no effect",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH27": {
+                    "description": "Channel 27 enable clear register.  Writing '0' has no effect",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH28": {
+                    "description": "Channel 28 enable clear register.  Writing '0' has no effect",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH29": {
+                    "description": "Channel 29 enable clear register.  Writing '0' has no effect",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH30": {
+                    "description": "Channel 30 enable clear register.  Writing '0' has no effect",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH31": {
+                    "description": "Channel 31 enable clear register.  Writing '0' has no effect",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Read: channel disabled",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Read: channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CHG": {
+              "description": "Description collection: Channel group n",
+              "offset": 2048,
+              "size": 32,
+              "count": 6,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0": {
+                    "description": "Include or exclude channel 0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH1": {
+                    "description": "Include or exclude channel 1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH2": {
+                    "description": "Include or exclude channel 2",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH3": {
+                    "description": "Include or exclude channel 3",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH4": {
+                    "description": "Include or exclude channel 4",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH5": {
+                    "description": "Include or exclude channel 5",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH6": {
+                    "description": "Include or exclude channel 6",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH7": {
+                    "description": "Include or exclude channel 7",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH8": {
+                    "description": "Include or exclude channel 8",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH9": {
+                    "description": "Include or exclude channel 9",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH10": {
+                    "description": "Include or exclude channel 10",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH11": {
+                    "description": "Include or exclude channel 11",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH12": {
+                    "description": "Include or exclude channel 12",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH13": {
+                    "description": "Include or exclude channel 13",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH14": {
+                    "description": "Include or exclude channel 14",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH15": {
+                    "description": "Include or exclude channel 15",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH16": {
+                    "description": "Include or exclude channel 16",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH17": {
+                    "description": "Include or exclude channel 17",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH18": {
+                    "description": "Include or exclude channel 18",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH19": {
+                    "description": "Include or exclude channel 19",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH20": {
+                    "description": "Include or exclude channel 20",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH21": {
+                    "description": "Include or exclude channel 21",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH22": {
+                    "description": "Include or exclude channel 22",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH23": {
+                    "description": "Include or exclude channel 23",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH24": {
+                    "description": "Include or exclude channel 24",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH25": {
+                    "description": "Include or exclude channel 25",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH26": {
+                    "description": "Include or exclude channel 26",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH27": {
+                    "description": "Include or exclude channel 27",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH28": {
+                    "description": "Include or exclude channel 28",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH29": {
+                    "description": "Include or exclude channel 29",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH30": {
+                    "description": "Include or exclude channel 30",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CH31": {
+                    "description": "Include or exclude channel 31",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Excluded": {
+                            "description": "Exclude",
+                            "value": 0
+                          },
+                          "Included": {
+                            "description": "Include",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NVMC": {
+        "description": "Non Volatile Memory Controller",
+        "children": {
+          "registers": {
+            "READY": {
+              "description": "Ready flag",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "NVMC is ready or busy",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Busy": {
+                            "description": "NVMC is busy (on-going write or erase operation)",
+                            "value": 0
+                          },
+                          "Ready": {
+                            "description": "NVMC is ready",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "READYNEXT": {
+              "description": "Ready flag",
+              "offset": 1032,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "READYNEXT": {
+                    "description": "NVMC can accept a new write operation",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Busy": {
+                            "description": "NVMC cannot accept any write operation",
+                            "value": 0
+                          },
+                          "Ready": {
+                            "description": "NVMC is ready",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "Configuration register",
+              "offset": 1284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WEN": {
+                    "description": "Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Ren": {
+                            "description": "Read only access",
+                            "value": 0
+                          },
+                          "Wen": {
+                            "description": "Write enabled",
+                            "value": 1
+                          },
+                          "Een": {
+                            "description": "Erase enabled",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERASEPAGE": {
+              "description": "Register for erasing a page in code area",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERASEPAGE": {
+                    "description": "Register for starting erase of a page in code area",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ERASEPCR1": {
+              "description": "Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE.",
+              "offset": 1288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERASEPCR1": {
+                    "description": "Register for erasing a page in code area. Equivalent to ERASEPAGE.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ERASEALL": {
+              "description": "Register for erasing all non-volatile user memory",
+              "offset": 1292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERASEALL": {
+                    "description": "Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoOperation": {
+                            "description": "No operation",
+                            "value": 0
+                          },
+                          "Erase": {
+                            "description": "Start chip erase",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERASEPCR0": {
+              "description": "Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE.",
+              "offset": 1296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERASEPCR0": {
+                    "description": "Register for starting erase of a page in code area. Equivalent to ERASEPAGE.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ERASEUICR": {
+              "description": "Register for erasing user information configuration registers",
+              "offset": 1300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERASEUICR": {
+                    "description": "Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NoOperation": {
+                            "description": "No operation",
+                            "value": 0
+                          },
+                          "Erase": {
+                            "description": "Start erase of UICR",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "ERASEPAGEPARTIAL": {
+              "description": "Register for partial erase of a page in code area",
+              "offset": 1304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERASEPAGEPARTIAL": {
+                    "description": "Register for starting partial erase of a page in code area",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ERASEPAGEPARTIALCFG": {
+              "description": "Register for partial erase configuration",
+              "offset": 1308,
+              "size": 32,
+              "reset_value": 10,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DURATION": {
+                    "description": "Duration of the partial erase in milliseconds",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ICACHECNF": {
+              "description": "I-code cache configuration register.",
+              "offset": 1344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHEEN": {
+                    "description": "Cache enable",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable cache. Invalidates all cache entries.",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable cache",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CACHEPROFEN": {
+                    "description": "Cache profiling enable",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "Disabled": {
+                            "description": "Disable cache profiling",
+                            "value": 0
+                          },
+                          "Enabled": {
+                            "description": "Enable cache profiling",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IHIT": {
+              "description": "I-code cache hit counter.",
+              "offset": 1352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HITS": {
+                    "description": "Number of cache hits",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IMISS": {
+              "description": "I-code cache miss counter.",
+              "offset": 1356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MISSES": {
+                    "description": "Number of cache misses",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  },
+  "devices": {
+    "nrf52840": {
+      "arch": "cortex_m4",
+      "description": "nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller ",
+      "properties": {
+        "cpu.nvic_prio_bits": "3",
+        "cpu.mpu": "1",
+        "cpu.fpu": "1",
+        "cpu.revision": "r0p1",
+        "cpu.vendor_systick_config": "0",
+        "license": "\nCopyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\\n\n\\n\nRedistribution and use in source and binary forms, with or without\\n\nmodification, are permitted provided that the following conditions are met:\\n\n\\n\n1. Redistributions of source code must retain the above copyright notice, this\\n\n   list of conditions and the following disclaimer.\\n\n\\n\n2. Redistributions in binary form must reproduce the above copyright\\n\n   notice, this list of conditions and the following disclaimer in the\\n\n   documentation and/or other materials provided with the distribution.\\n\n\\n\n3. Neither the name of Nordic Semiconductor ASA nor the names of its\\n\n   contributors may be used to endorse or promote products derived from this\\n\n   software without specific prior written permission.\\n\n\\n\nTHIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS \"AS IS\"\\n\nAND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\\n\nIMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\\n\nARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\\n\nLIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\\n\nCONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\\n\nSUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\\n\nINTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\\n\nCONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\\n\nARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\\n\nPOSSIBILITY OF SUCH DAMAGE.\\n\n        ",
+        "cpu.name": "CM4",
+        "cpu.endian": "little"
+      },
+      "children": {
+        "interrupts": {
+          "MemManageFault": {
+            "index": -12
+          },
+          "BusFault": {
+            "index": -11
+          },
+          "UsageFault": {
+            "index": -10
+          },
+          "DebugMonitor": {
+            "index": -4
+          },
+          "NMI": {
+            "index": -14
+          },
+          "HardFault": {
+            "index": -13
+          },
+          "SVCall": {
+            "index": -5
+          },
+          "PendSV": {
+            "index": -2
+          },
+          "SysTick": {
+            "index": -1
+          },
+          "POWER_CLOCK": {
+            "index": 0
+          },
+          "RADIO": {
+            "index": 1
+          },
+          "UARTE0_UART0": {
+            "index": 2
+          },
+          "SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0": {
+            "index": 3
+          },
+          "SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1": {
+            "index": 4
+          },
+          "NFCT": {
+            "index": 5
+          },
+          "GPIOTE": {
+            "index": 6
+          },
+          "SAADC": {
+            "index": 7
+          },
+          "TIMER0": {
+            "index": 8
+          },
+          "TIMER1": {
+            "index": 9
+          },
+          "TIMER2": {
+            "index": 10
+          },
+          "RTC0": {
+            "index": 11
+          },
+          "TEMP": {
+            "index": 12
+          },
+          "RNG": {
+            "index": 13
+          },
+          "ECB": {
+            "index": 14
+          },
+          "CCM_AAR": {
+            "index": 15
+          },
+          "WDT": {
+            "index": 16
+          },
+          "RTC1": {
+            "index": 17
+          },
+          "QDEC": {
+            "index": 18
+          },
+          "COMP_LPCOMP": {
+            "index": 19
+          },
+          "SWI0_EGU0": {
+            "index": 20
+          },
+          "SWI1_EGU1": {
+            "index": 21
+          },
+          "SWI2_EGU2": {
+            "index": 22
+          },
+          "SWI3_EGU3": {
+            "index": 23
+          },
+          "SWI4_EGU4": {
+            "index": 24
+          },
+          "SWI5_EGU5": {
+            "index": 25
+          },
+          "TIMER3": {
+            "index": 26
+          },
+          "TIMER4": {
+            "index": 27
+          },
+          "PWM0": {
+            "index": 28
+          },
+          "PDM": {
+            "index": 29
+          },
+          "MWU": {
+            "index": 32
+          },
+          "PWM1": {
+            "index": 33
+          },
+          "PWM2": {
+            "index": 34
+          },
+          "SPIM2_SPIS2_SPI2": {
+            "index": 35
+          },
+          "RTC2": {
+            "index": 36
+          },
+          "I2S": {
+            "index": 37
+          },
+          "FPU": {
+            "index": 38
+          },
+          "USBD": {
+            "index": 39
+          },
+          "UARTE1": {
+            "index": 40
+          },
+          "QSPI": {
+            "index": 41
+          },
+          "CRYPTOCELL": {
+            "index": 42
+          },
+          "PWM3": {
+            "index": 45
+          },
+          "SPIM3": {
+            "index": 47
+          }
+        },
+        "peripheral_instances": {
+          "SysTick": {
+            "offset": 3758153744,
+            "type": "types.peripherals.SCS.children.register_groups.SysTick"
+          },
+          "FICR": {
+            "description": "Factory information configuration registers",
+            "offset": 268435456,
+            "type": "types.peripherals.FICR"
+          },
+          "UICR": {
+            "description": "User information configuration registers",
+            "offset": 268439552,
+            "type": "types.peripherals.UICR"
+          },
+          "CLOCK": {
+            "description": "Clock control",
+            "offset": 1073741824,
+            "type": "types.peripherals.CLOCK"
+          },
+          "POWER": {
+            "description": "Power control",
+            "offset": 1073741824,
+            "type": "types.peripherals.POWER"
+          },
+          "P0": {
+            "description": "GPIO Port 1",
+            "offset": 1342177280,
+            "type": "types.peripherals.P0"
+          },
+          "P1": {
+            "description": "GPIO Port 2",
+            "offset": 1342178048,
+            "type": "types.peripherals.P0"
+          },
+          "RADIO": {
+            "description": "2.4 GHz radio",
+            "offset": 1073745920,
+            "type": "types.peripherals.RADIO"
+          },
+          "UART0": {
+            "description": "Universal Asynchronous Receiver/Transmitter",
+            "offset": 1073750016,
+            "type": "types.peripherals.UART0"
+          },
+          "UARTE0": {
+            "description": "UART with EasyDMA 0",
+            "offset": 1073750016,
+            "type": "types.peripherals.UARTE0"
+          },
+          "SPI0": {
+            "description": "Serial Peripheral Interface 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.SPI0"
+          },
+          "SPIM0": {
+            "description": "Serial Peripheral Interface Master with EasyDMA 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.SPIM0"
+          },
+          "SPIS0": {
+            "description": "SPI Slave 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.SPIS0"
+          },
+          "TWI0": {
+            "description": "I2C compatible Two-Wire Interface 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.TWI0"
+          },
+          "TWIM0": {
+            "description": "I2C compatible Two-Wire Master Interface with EasyDMA 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.TWIM0"
+          },
+          "TWIS0": {
+            "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 0",
+            "offset": 1073754112,
+            "type": "types.peripherals.TWIS0"
+          },
+          "SPI1": {
+            "description": "Serial Peripheral Interface 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.SPI0"
+          },
+          "SPIM1": {
+            "description": "Serial Peripheral Interface Master with EasyDMA 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.SPIM0"
+          },
+          "SPIS1": {
+            "description": "SPI Slave 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.SPIS0"
+          },
+          "TWI1": {
+            "description": "I2C compatible Two-Wire Interface 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.TWI0"
+          },
+          "TWIM1": {
+            "description": "I2C compatible Two-Wire Master Interface with EasyDMA 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.TWIM0"
+          },
+          "TWIS1": {
+            "description": "I2C compatible Two-Wire Slave Interface with EasyDMA 1",
+            "offset": 1073758208,
+            "type": "types.peripherals.TWIS0"
+          },
+          "NFCT": {
+            "description": "NFC-A compatible radio",
+            "offset": 1073762304,
+            "type": "types.peripherals.NFCT"
+          },
+          "GPIOTE": {
+            "description": "GPIO Tasks and Events",
+            "offset": 1073766400,
+            "type": "types.peripherals.GPIOTE"
+          },
+          "SAADC": {
+            "description": "Successive approximation register (SAR) analog-to-digital converter",
+            "offset": 1073770496,
+            "type": "types.peripherals.SAADC"
+          },
+          "TIMER0": {
+            "description": "Timer/Counter 0",
+            "offset": 1073774592,
+            "type": "types.peripherals.TIMER0"
+          },
+          "TIMER1": {
+            "description": "Timer/Counter 1",
+            "offset": 1073778688,
+            "type": "types.peripherals.TIMER0"
+          },
+          "TIMER2": {
+            "description": "Timer/Counter 2",
+            "offset": 1073782784,
+            "type": "types.peripherals.TIMER0"
+          },
+          "RTC0": {
+            "description": "Real time counter 0",
+            "offset": 1073786880,
+            "type": "types.peripherals.RTC0"
+          },
+          "TEMP": {
+            "description": "Temperature Sensor",
+            "offset": 1073790976,
+            "type": "types.peripherals.TEMP"
+          },
+          "RNG": {
+            "description": "Random Number Generator",
+            "offset": 1073795072,
+            "type": "types.peripherals.RNG"
+          },
+          "ECB": {
+            "description": "AES ECB Mode Encryption",
+            "offset": 1073799168,
+            "type": "types.peripherals.ECB"
+          },
+          "AAR": {
+            "description": "Accelerated Address Resolver",
+            "offset": 1073803264,
+            "type": "types.peripherals.AAR"
+          },
+          "CCM": {
+            "description": "AES CCM Mode Encryption",
+            "offset": 1073803264,
+            "type": "types.peripherals.CCM"
+          },
+          "WDT": {
+            "description": "Watchdog Timer",
+            "offset": 1073807360,
+            "type": "types.peripherals.WDT"
+          },
+          "RTC1": {
+            "description": "Real time counter 1",
+            "offset": 1073811456,
+            "type": "types.peripherals.RTC0"
+          },
+          "QDEC": {
+            "description": "Quadrature Decoder",
+            "offset": 1073815552,
+            "type": "types.peripherals.QDEC"
+          },
+          "COMP": {
+            "description": "Comparator",
+            "offset": 1073819648,
+            "type": "types.peripherals.COMP"
+          },
+          "LPCOMP": {
+            "description": "Low Power Comparator",
+            "offset": 1073819648,
+            "type": "types.peripherals.LPCOMP"
+          },
+          "EGU0": {
+            "description": "Event Generator Unit 0",
+            "offset": 1073823744,
+            "type": "types.peripherals.EGU0"
+          },
+          "SWI0": {
+            "description": "Software interrupt 0",
+            "offset": 1073823744,
+            "type": "types.peripherals.SWI0"
+          },
+          "EGU1": {
+            "description": "Event Generator Unit 1",
+            "offset": 1073827840,
+            "type": "types.peripherals.EGU0"
+          },
+          "SWI1": {
+            "description": "Software interrupt 1",
+            "offset": 1073827840,
+            "type": "types.peripherals.SWI0"
+          },
+          "EGU2": {
+            "description": "Event Generator Unit 2",
+            "offset": 1073831936,
+            "type": "types.peripherals.EGU0"
+          },
+          "SWI2": {
+            "description": "Software interrupt 2",
+            "offset": 1073831936,
+            "type": "types.peripherals.SWI0"
+          },
+          "EGU3": {
+            "description": "Event Generator Unit 3",
+            "offset": 1073836032,
+            "type": "types.peripherals.EGU0"
+          },
+          "SWI3": {
+            "description": "Software interrupt 3",
+            "offset": 1073836032,
+            "type": "types.peripherals.SWI0"
+          },
+          "EGU4": {
+            "description": "Event Generator Unit 4",
+            "offset": 1073840128,
+            "type": "types.peripherals.EGU0"
+          },
+          "SWI4": {
+            "description": "Software interrupt 4",
+            "offset": 1073840128,
+            "type": "types.peripherals.SWI0"
+          },
+          "EGU5": {
+            "description": "Event Generator Unit 5",
+            "offset": 1073844224,
+            "type": "types.peripherals.EGU0"
+          },
+          "SWI5": {
+            "description": "Software interrupt 5",
+            "offset": 1073844224,
+            "type": "types.peripherals.SWI0"
+          },
+          "TIMER3": {
+            "description": "Timer/Counter 3",
+            "offset": 1073848320,
+            "type": "types.peripherals.TIMER0"
+          },
+          "TIMER4": {
+            "description": "Timer/Counter 4",
+            "offset": 1073852416,
+            "type": "types.peripherals.TIMER0"
+          },
+          "PWM0": {
+            "description": "Pulse width modulation unit 0",
+            "offset": 1073856512,
+            "type": "types.peripherals.PWM0"
+          },
+          "PDM": {
+            "description": "Pulse Density Modulation (Digital Microphone) Interface",
+            "offset": 1073860608,
+            "type": "types.peripherals.PDM"
+          },
+          "ACL": {
+            "description": "Access control lists",
+            "offset": 1073864704,
+            "type": "types.peripherals.ACL"
+          },
+          "NVMC": {
+            "description": "Non Volatile Memory Controller",
+            "offset": 1073864704,
+            "type": "types.peripherals.NVMC"
+          },
+          "PPI": {
+            "description": "Programmable Peripheral Interconnect",
+            "offset": 1073868800,
+            "type": "types.peripherals.PPI"
+          },
+          "MWU": {
+            "description": "Memory Watch Unit",
+            "offset": 1073872896,
+            "type": "types.peripherals.MWU"
+          },
+          "PWM1": {
+            "description": "Pulse width modulation unit 1",
+            "offset": 1073876992,
+            "type": "types.peripherals.PWM0"
+          },
+          "PWM2": {
+            "description": "Pulse width modulation unit 2",
+            "offset": 1073881088,
+            "type": "types.peripherals.PWM0"
+          },
+          "SPI2": {
+            "description": "Serial Peripheral Interface 2",
+            "offset": 1073885184,
+            "type": "types.peripherals.SPI0"
+          },
+          "SPIM2": {
+            "description": "Serial Peripheral Interface Master with EasyDMA 2",
+            "offset": 1073885184,
+            "type": "types.peripherals.SPIM0"
+          },
+          "SPIS2": {
+            "description": "SPI Slave 2",
+            "offset": 1073885184,
+            "type": "types.peripherals.SPIS0"
+          },
+          "RTC2": {
+            "description": "Real time counter 2",
+            "offset": 1073889280,
+            "type": "types.peripherals.RTC0"
+          },
+          "I2S": {
+            "description": "Inter-IC Sound",
+            "offset": 1073893376,
+            "type": "types.peripherals.I2S"
+          },
+          "FPU": {
+            "description": "FPU",
+            "offset": 1073897472,
+            "type": "types.peripherals.FPU"
+          },
+          "USBD": {
+            "description": "Universal serial bus device",
+            "offset": 1073901568,
+            "type": "types.peripherals.USBD"
+          },
+          "UARTE1": {
+            "description": "UART with EasyDMA 1",
+            "offset": 1073905664,
+            "type": "types.peripherals.UARTE0"
+          },
+          "QSPI": {
+            "description": "External flash interface",
+            "offset": 1073909760,
+            "type": "types.peripherals.QSPI"
+          },
+          "CC_HOST_RGF": {
+            "description": "CRYPTOCELL HOST_RGF interface",
+            "offset": 1342349312,
+            "type": "types.peripherals.CC_HOST_RGF"
+          },
+          "CRYPTOCELL": {
+            "description": "ARM TrustZone CryptoCell register interface",
+            "offset": 1342349312,
+            "type": "types.peripherals.CRYPTOCELL"
+          },
+          "PWM3": {
+            "description": "Pulse width modulation unit 3",
+            "offset": 1073926144,
+            "type": "types.peripherals.PWM0"
+          },
+          "SPIM3": {
+            "description": "Serial Peripheral Interface Master with EasyDMA 3",
+            "offset": 1073934336,
+            "type": "types.peripherals.SPIM0"
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/chips/nrf52840.zig b/src/chips/nrf52840.zig
new file mode 100644
index 000000000..8c1ffa2f4
--- /dev/null
+++ b/src/chips/nrf52840.zig
@@ -0,0 +1,21782 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    ///  nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller
+    pub const nrf52840 = struct {
+        pub const properties = struct {
+            pub const @"cpu.nvic_prio_bits" = "3";
+            pub const @"cpu.mpu" = "1";
+            pub const @"cpu.fpu" = "1";
+            pub const @"cpu.revision" = "r0p1";
+            pub const @"cpu.vendor_systick_config" = "0";
+            pub const license =
+                \\
+                \\Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n
+                \\\n
+                \\Redistribution and use in source and binary forms, with or without\n
+                \\modification, are permitted provided that the following conditions are met:\n
+                \\\n
+                \\1. Redistributions of source code must retain the above copyright notice, this\n
+                \\   list of conditions and the following disclaimer.\n
+                \\\n
+                \\2. Redistributions in binary form must reproduce the above copyright\n
+                \\   notice, this list of conditions and the following disclaimer in the\n
+                \\   documentation and/or other materials provided with the distribution.\n
+                \\\n
+                \\3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
+                \\   contributors may be used to endorse or promote products derived from this\n
+                \\   software without specific prior written permission.\n
+                \\\n
+                \\THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
+                \\AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
+                \\IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
+                \\ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
+                \\LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
+                \\CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
+                \\SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
+                \\INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
+                \\CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
+                \\ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
+                \\POSSIBILITY OF SUCH DAMAGE.\n
+                \\        
+            ;
+            pub const @"cpu.name" = "CM4";
+            pub const @"cpu.endian" = "little";
+        };
+
+        pub const VectorTable = extern struct {
+            const Handler = micro.interrupt.Handler;
+            const unhandled = micro.interrupt.unhandled;
+
+            initial_stack_pointer: u32,
+            Reset: Handler = unhandled,
+            NMI: Handler = unhandled,
+            HardFault: Handler = unhandled,
+            MemManageFault: Handler = unhandled,
+            BusFault: Handler = unhandled,
+            UsageFault: Handler = unhandled,
+            reserved5: [4]u32 = undefined,
+            SVCall: Handler = unhandled,
+            DebugMonitor: Handler = unhandled,
+            reserved11: [1]u32 = undefined,
+            PendSV: Handler = unhandled,
+            SysTick: Handler = unhandled,
+            POWER_CLOCK: Handler = unhandled,
+            RADIO: Handler = unhandled,
+            UARTE0_UART0: Handler = unhandled,
+            SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: Handler = unhandled,
+            SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: Handler = unhandled,
+            NFCT: Handler = unhandled,
+            GPIOTE: Handler = unhandled,
+            SAADC: Handler = unhandled,
+            TIMER0: Handler = unhandled,
+            TIMER1: Handler = unhandled,
+            TIMER2: Handler = unhandled,
+            RTC0: Handler = unhandled,
+            TEMP: Handler = unhandled,
+            RNG: Handler = unhandled,
+            ECB: Handler = unhandled,
+            CCM_AAR: Handler = unhandled,
+            WDT: Handler = unhandled,
+            RTC1: Handler = unhandled,
+            QDEC: Handler = unhandled,
+            COMP_LPCOMP: Handler = unhandled,
+            SWI0_EGU0: Handler = unhandled,
+            SWI1_EGU1: Handler = unhandled,
+            SWI2_EGU2: Handler = unhandled,
+            SWI3_EGU3: Handler = unhandled,
+            SWI4_EGU4: Handler = unhandled,
+            SWI5_EGU5: Handler = unhandled,
+            TIMER3: Handler = unhandled,
+            TIMER4: Handler = unhandled,
+            PWM0: Handler = unhandled,
+            PDM: Handler = unhandled,
+            reserved44: [2]u32 = undefined,
+            MWU: Handler = unhandled,
+            PWM1: Handler = unhandled,
+            PWM2: Handler = unhandled,
+            SPIM2_SPIS2_SPI2: Handler = unhandled,
+            RTC2: Handler = unhandled,
+            I2S: Handler = unhandled,
+            FPU: Handler = unhandled,
+            USBD: Handler = unhandled,
+            UARTE1: Handler = unhandled,
+            QSPI: Handler = unhandled,
+            CRYPTOCELL: Handler = unhandled,
+            reserved57: [2]u32 = undefined,
+            PWM3: Handler = unhandled,
+            reserved60: [1]u32 = undefined,
+            SPIM3: Handler = unhandled,
+        };
+
+        pub const peripherals = struct {
+            ///  Factory information configuration registers
+            pub const FICR = @intToPtr(*volatile types.peripherals.FICR, 0x10000000);
+            ///  User information configuration registers
+            pub const UICR = @intToPtr(*volatile types.peripherals.UICR, 0x10001000);
+            ///  Clock control
+            pub const CLOCK = @intToPtr(*volatile types.peripherals.CLOCK, 0x40000000);
+            ///  Power control
+            pub const POWER = @intToPtr(*volatile types.peripherals.POWER, 0x40000000);
+            ///  2.4 GHz radio
+            pub const RADIO = @intToPtr(*volatile types.peripherals.RADIO, 0x40001000);
+            ///  Universal Asynchronous Receiver/Transmitter
+            pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x40002000);
+            ///  UART with EasyDMA 0
+            pub const UARTE0 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40002000);
+            ///  Serial Peripheral Interface 0
+            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003000);
+            ///  Serial Peripheral Interface Master with EasyDMA 0
+            pub const SPIM0 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40003000);
+            ///  SPI Slave 0
+            pub const SPIS0 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40003000);
+            ///  I2C compatible Two-Wire Interface 0
+            pub const TWI0 = @intToPtr(*volatile types.peripherals.TWI0, 0x40003000);
+            ///  I2C compatible Two-Wire Master Interface with EasyDMA 0
+            pub const TWIM0 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40003000);
+            ///  I2C compatible Two-Wire Slave Interface with EasyDMA 0
+            pub const TWIS0 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40003000);
+            ///  Serial Peripheral Interface 1
+            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40004000);
+            ///  Serial Peripheral Interface Master with EasyDMA 1
+            pub const SPIM1 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40004000);
+            ///  SPI Slave 1
+            pub const SPIS1 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40004000);
+            ///  I2C compatible Two-Wire Interface 1
+            pub const TWI1 = @intToPtr(*volatile types.peripherals.TWI0, 0x40004000);
+            ///  I2C compatible Two-Wire Master Interface with EasyDMA 1
+            pub const TWIM1 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40004000);
+            ///  I2C compatible Two-Wire Slave Interface with EasyDMA 1
+            pub const TWIS1 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40004000);
+            ///  NFC-A compatible radio
+            pub const NFCT = @intToPtr(*volatile types.peripherals.NFCT, 0x40005000);
+            ///  GPIO Tasks and Events
+            pub const GPIOTE = @intToPtr(*volatile types.peripherals.GPIOTE, 0x40006000);
+            ///  Successive approximation register (SAR) analog-to-digital converter
+            pub const SAADC = @intToPtr(*volatile types.peripherals.SAADC, 0x40007000);
+            ///  Timer/Counter 0
+            pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40008000);
+            ///  Timer/Counter 1
+            pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40009000);
+            ///  Timer/Counter 2
+            pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4000a000);
+            ///  Real time counter 0
+            pub const RTC0 = @intToPtr(*volatile types.peripherals.RTC0, 0x4000b000);
+            ///  Temperature Sensor
+            pub const TEMP = @intToPtr(*volatile types.peripherals.TEMP, 0x4000c000);
+            ///  Random Number Generator
+            pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x4000d000);
+            ///  AES ECB Mode Encryption
+            pub const ECB = @intToPtr(*volatile types.peripherals.ECB, 0x4000e000);
+            ///  Accelerated Address Resolver
+            pub const AAR = @intToPtr(*volatile types.peripherals.AAR, 0x4000f000);
+            ///  AES CCM Mode Encryption
+            pub const CCM = @intToPtr(*volatile types.peripherals.CCM, 0x4000f000);
+            ///  Watchdog Timer
+            pub const WDT = @intToPtr(*volatile types.peripherals.WDT, 0x40010000);
+            ///  Real time counter 1
+            pub const RTC1 = @intToPtr(*volatile types.peripherals.RTC0, 0x40011000);
+            ///  Quadrature Decoder
+            pub const QDEC = @intToPtr(*volatile types.peripherals.QDEC, 0x40012000);
+            ///  Comparator
+            pub const COMP = @intToPtr(*volatile types.peripherals.COMP, 0x40013000);
+            ///  Low Power Comparator
+            pub const LPCOMP = @intToPtr(*volatile types.peripherals.LPCOMP, 0x40013000);
+            ///  Event Generator Unit 0
+            pub const EGU0 = @intToPtr(*volatile types.peripherals.EGU0, 0x40014000);
+            ///  Software interrupt 0
+            pub const SWI0 = @intToPtr(*volatile types.peripherals.SWI0, 0x40014000);
+            ///  Event Generator Unit 1
+            pub const EGU1 = @intToPtr(*volatile types.peripherals.EGU0, 0x40015000);
+            ///  Software interrupt 1
+            pub const SWI1 = @intToPtr(*volatile types.peripherals.SWI0, 0x40015000);
+            ///  Event Generator Unit 2
+            pub const EGU2 = @intToPtr(*volatile types.peripherals.EGU0, 0x40016000);
+            ///  Software interrupt 2
+            pub const SWI2 = @intToPtr(*volatile types.peripherals.SWI0, 0x40016000);
+            ///  Event Generator Unit 3
+            pub const EGU3 = @intToPtr(*volatile types.peripherals.EGU0, 0x40017000);
+            ///  Software interrupt 3
+            pub const SWI3 = @intToPtr(*volatile types.peripherals.SWI0, 0x40017000);
+            ///  Event Generator Unit 4
+            pub const EGU4 = @intToPtr(*volatile types.peripherals.EGU0, 0x40018000);
+            ///  Software interrupt 4
+            pub const SWI4 = @intToPtr(*volatile types.peripherals.SWI0, 0x40018000);
+            ///  Event Generator Unit 5
+            pub const EGU5 = @intToPtr(*volatile types.peripherals.EGU0, 0x40019000);
+            ///  Software interrupt 5
+            pub const SWI5 = @intToPtr(*volatile types.peripherals.SWI0, 0x40019000);
+            ///  Timer/Counter 3
+            pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001a000);
+            ///  Timer/Counter 4
+            pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001b000);
+            ///  Pulse width modulation unit 0
+            pub const PWM0 = @intToPtr(*volatile types.peripherals.PWM0, 0x4001c000);
+            ///  Pulse Density Modulation (Digital Microphone) Interface
+            pub const PDM = @intToPtr(*volatile types.peripherals.PDM, 0x4001d000);
+            ///  Access control lists
+            pub const ACL = @intToPtr(*volatile types.peripherals.ACL, 0x4001e000);
+            ///  Non Volatile Memory Controller
+            pub const NVMC = @intToPtr(*volatile types.peripherals.NVMC, 0x4001e000);
+            ///  Programmable Peripheral Interconnect
+            pub const PPI = @intToPtr(*volatile types.peripherals.PPI, 0x4001f000);
+            ///  Memory Watch Unit
+            pub const MWU = @intToPtr(*volatile types.peripherals.MWU, 0x40020000);
+            ///  Pulse width modulation unit 1
+            pub const PWM1 = @intToPtr(*volatile types.peripherals.PWM0, 0x40021000);
+            ///  Pulse width modulation unit 2
+            pub const PWM2 = @intToPtr(*volatile types.peripherals.PWM0, 0x40022000);
+            ///  Serial Peripheral Interface 2
+            pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40023000);
+            ///  Serial Peripheral Interface Master with EasyDMA 2
+            pub const SPIM2 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40023000);
+            ///  SPI Slave 2
+            pub const SPIS2 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40023000);
+            ///  Real time counter 2
+            pub const RTC2 = @intToPtr(*volatile types.peripherals.RTC0, 0x40024000);
+            ///  Inter-IC Sound
+            pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x40025000);
+            ///  FPU
+            pub const FPU = @intToPtr(*volatile types.peripherals.FPU, 0x40026000);
+            ///  Universal serial bus device
+            pub const USBD = @intToPtr(*volatile types.peripherals.USBD, 0x40027000);
+            ///  UART with EasyDMA 1
+            pub const UARTE1 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40028000);
+            ///  External flash interface
+            pub const QSPI = @intToPtr(*volatile types.peripherals.QSPI, 0x40029000);
+            ///  Pulse width modulation unit 3
+            pub const PWM3 = @intToPtr(*volatile types.peripherals.PWM0, 0x4002d000);
+            ///  Serial Peripheral Interface Master with EasyDMA 3
+            pub const SPIM3 = @intToPtr(*volatile types.peripherals.SPIM0, 0x4002f000);
+            ///  GPIO Port 1
+            pub const P0 = @intToPtr(*volatile types.peripherals.P0, 0x50000000);
+            ///  GPIO Port 2
+            pub const P1 = @intToPtr(*volatile types.peripherals.P0, 0x50000300);
+            ///  CRYPTOCELL HOST_RGF interface
+            pub const CC_HOST_RGF = @intToPtr(*volatile types.peripherals.CC_HOST_RGF, 0x5002a000);
+            ///  ARM TrustZone CryptoCell register interface
+            pub const CRYPTOCELL = @intToPtr(*volatile types.peripherals.CRYPTOCELL, 0x5002a000);
+            ///  System Tick Timer
+            pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010);
+        };
+    };
+};
+
+pub const types = struct {
+    pub const peripherals = struct {
+        ///  System Control Space
+        pub const SCS = struct {
+            ///  System Tick Timer
+            pub const SysTick = extern struct {
+                ///  SysTick Control and Status Register
+                CTRL: mmio.Mmio(packed struct(u32) {
+                    ENABLE: u1,
+                    TICKINT: u1,
+                    CLKSOURCE: u1,
+                    reserved16: u13,
+                    COUNTFLAG: u1,
+                    padding: u15,
+                }),
+                ///  SysTick Reload Value Register
+                LOAD: mmio.Mmio(packed struct(u32) {
+                    RELOAD: u24,
+                    padding: u8,
+                }),
+                ///  SysTick Current Value Register
+                VAL: mmio.Mmio(packed struct(u32) {
+                    CURRENT: u24,
+                    padding: u8,
+                }),
+                ///  SysTick Calibration Register
+                CALIB: mmio.Mmio(packed struct(u32) {
+                    TENMS: u24,
+                    reserved30: u6,
+                    SKEW: u1,
+                    NOREF: u1,
+                }),
+            };
+        };
+
+        ///  Factory information configuration registers
+        pub const FICR = extern struct {
+            reserved16: [16]u8,
+            ///  Code memory page size
+            CODEPAGESIZE: mmio.Mmio(packed struct(u32) {
+                ///  Code memory page size
+                CODEPAGESIZE: u32,
+            }),
+            ///  Code memory size
+            CODESIZE: mmio.Mmio(packed struct(u32) {
+                ///  Code memory size in number of pages
+                CODESIZE: u32,
+            }),
+            reserved96: [72]u8,
+            ///  Description collection: Device identifier
+            DEVICEID: [2]mmio.Mmio(packed struct(u32) {
+                ///  64 bit unique device identifier
+                DEVICEID: u32,
+            }),
+            reserved128: [24]u8,
+            ///  Description collection: Encryption root, word n
+            ER: [4]mmio.Mmio(packed struct(u32) {
+                ///  Encryption root, word n
+                ER: u32,
+            }),
+            ///  Description collection: Identity Root, word n
+            IR: [4]mmio.Mmio(packed struct(u32) {
+                ///  Identity Root, word n
+                IR: u32,
+            }),
+            ///  Device address type
+            DEVICEADDRTYPE: mmio.Mmio(packed struct(u32) {
+                ///  Device address type
+                DEVICEADDRTYPE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Public address
+                        Public = 0x0,
+                        ///  Random address
+                        Random = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Description collection: Device address n
+            DEVICEADDR: [2]mmio.Mmio(packed struct(u32) {
+                ///  48 bit device address
+                DEVICEADDR: u32,
+            }),
+            reserved848: [676]u8,
+            ///  Description collection: Production test signature n
+            PRODTEST: [3]mmio.Mmio(packed struct(u32) {
+                ///  Production test signature n
+                PRODTEST: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  Production tests done
+                        Done = 0xbb42319f,
+                        ///  Production tests not done
+                        NotDone = 0xffffffff,
+                        _,
+                    },
+                },
+            }),
+        };
+
+        ///  User information configuration registers
+        pub const UICR = extern struct {
+            reserved20: [20]u8,
+            ///  Description collection: Reserved for Nordic firmware design
+            NRFFW: [13]mmio.Mmio(packed struct(u32) {
+                ///  Reserved for Nordic firmware design
+                NRFFW: u32,
+            }),
+            reserved80: [8]u8,
+            ///  Description collection: Reserved for Nordic hardware design
+            NRFHW: [12]mmio.Mmio(packed struct(u32) {
+                ///  Reserved for Nordic hardware design
+                NRFHW: u32,
+            }),
+            ///  Description collection: Reserved for customer
+            CUSTOMER: [32]mmio.Mmio(packed struct(u32) {
+                ///  Reserved for customer
+                CUSTOMER: u32,
+            }),
+            reserved512: [256]u8,
+            ///  Description collection: Mapping of the nRESET function (see POWER chapter for details)
+            PSELRESET: [2]mmio.Mmio(packed struct(u32) {
+                ///  GPIO pin number onto which nRESET is exposed
+                PIN: u5,
+                ///  Port number onto which nRESET is exposed
+                PORT: u1,
+                reserved31: u25,
+                ///  Connection
+                CONNECT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disconnect
+                        Disconnected = 0x1,
+                        ///  Connect
+                        Connected = 0x0,
+                    },
+                },
+            }),
+            ///  Access port protection
+            APPROTECT: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable access port protection.
+                PALL: packed union {
+                    raw: u8,
+                    value: enum(u8) {
+                        ///  Disable
+                        Disabled = 0xff,
+                        ///  Enable
+                        Enabled = 0x0,
+                        _,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
+            NFCPINS: mmio.Mmio(packed struct(u32) {
+                ///  Setting of pins dedicated to NFC functionality
+                PROTECT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Operation as GPIO pins. Same protection as normal GPIO pins
+                        Disabled = 0x0,
+                        ///  Operation as NFC antenna pins. Configures the protection for NFC operation
+                        NFC = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Processor debug control
+            DEBUGCTRL: mmio.Mmio(packed struct(u32) {
+                ///  Configure CPU non-intrusive debug features
+                CPUNIDEN: packed union {
+                    raw: u8,
+                    value: enum(u8) {
+                        ///  Enable CPU ITM and ETM functionality (default behavior)
+                        Enabled = 0xff,
+                        ///  Disable CPU ITM and ETM functionality
+                        Disabled = 0x0,
+                        _,
+                    },
+                },
+                ///  Configure CPU flash patch and breakpoint (FPB) unit behavior
+                CPUFPBEN: packed union {
+                    raw: u8,
+                    value: enum(u8) {
+                        ///  Enable CPU FPB unit (default behavior)
+                        Enabled = 0xff,
+                        ///  Disable CPU FPB unit. Writes into the FPB registers will be ignored.
+                        Disabled = 0x0,
+                        _,
+                    },
+                },
+                padding: u16,
+            }),
+            reserved772: [240]u8,
+            ///  GPIO reference voltage / external output supply voltage in high voltage mode
+            REGOUT0: mmio.Mmio(packed struct(u32) {
+                ///  Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF.
+                VOUT: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  1.8 V
+                        @"1V8" = 0x0,
+                        ///  2.1 V
+                        @"2V1" = 0x1,
+                        ///  2.4 V
+                        @"2V4" = 0x2,
+                        ///  2.7 V
+                        @"2V7" = 0x3,
+                        ///  3.0 V
+                        @"3V0" = 0x4,
+                        ///  3.3 V
+                        @"3V3" = 0x5,
+                        ///  Default voltage: 1.8 V
+                        DEFAULT = 0x7,
+                        _,
+                    },
+                },
+                padding: u29,
+            }),
+        };
+
+        ///  Clock control
+        pub const CLOCK = extern struct {
+            ///  Start HFXO crystal oscillator
+            TASKS_HFCLKSTART: mmio.Mmio(packed struct(u32) {
+                ///  Start HFXO crystal oscillator
+                TASKS_HFCLKSTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop HFXO crystal oscillator
+            TASKS_HFCLKSTOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop HFXO crystal oscillator
+                TASKS_HFCLKSTOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start LFCLK
+            TASKS_LFCLKSTART: mmio.Mmio(packed struct(u32) {
+                ///  Start LFCLK
+                TASKS_LFCLKSTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop LFCLK
+            TASKS_LFCLKSTOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop LFCLK
+                TASKS_LFCLKSTOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start calibration of LFRC
+            TASKS_CAL: mmio.Mmio(packed struct(u32) {
+                ///  Start calibration of LFRC
+                TASKS_CAL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start calibration timer
+            TASKS_CTSTART: mmio.Mmio(packed struct(u32) {
+                ///  Start calibration timer
+                TASKS_CTSTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop calibration timer
+            TASKS_CTSTOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop calibration timer
+                TASKS_CTSTOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [228]u8,
+            ///  HFXO crystal oscillator started
+            EVENTS_HFCLKSTARTED: mmio.Mmio(packed struct(u32) {
+                ///  HFXO crystal oscillator started
+                EVENTS_HFCLKSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  LFCLK started
+            EVENTS_LFCLKSTARTED: mmio.Mmio(packed struct(u32) {
+                ///  LFCLK started
+                EVENTS_LFCLKSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved268: [4]u8,
+            ///  Calibration of LFRC completed
+            EVENTS_DONE: mmio.Mmio(packed struct(u32) {
+                ///  Calibration of LFRC completed
+                EVENTS_DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Calibration timer timeout
+            EVENTS_CTTO: mmio.Mmio(packed struct(u32) {
+                ///  Calibration timer timeout
+                EVENTS_CTTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved296: [20]u8,
+            ///  Calibration timer has been started and is ready to process new tasks
+            EVENTS_CTSTARTED: mmio.Mmio(packed struct(u32) {
+                ///  Calibration timer has been started and is ready to process new tasks
+                EVENTS_CTSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Calibration timer has been stopped and is ready to process new tasks
+            EVENTS_CTSTOPPED: mmio.Mmio(packed struct(u32) {
+                ///  Calibration timer has been stopped and is ready to process new tasks
+                EVENTS_CTSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [468]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event HFCLKSTARTED
+                HFCLKSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event LFCLKSTARTED
+                LFCLKSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved3: u1,
+                ///  Write '1' to enable interrupt for event DONE
+                DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CTTO
+                CTTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u5,
+                ///  Write '1' to enable interrupt for event CTSTARTED
+                CTSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CTSTOPPED
+                CTSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u20,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event HFCLKSTARTED
+                HFCLKSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event LFCLKSTARTED
+                LFCLKSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved3: u1,
+                ///  Write '1' to disable interrupt for event DONE
+                DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CTTO
+                CTTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u5,
+                ///  Write '1' to disable interrupt for event CTSTARTED
+                CTSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CTSTOPPED
+                CTSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u20,
+            }),
+            reserved1032: [252]u8,
+            ///  Status indicating that HFCLKSTART task has been triggered
+            HFCLKRUN: mmio.Mmio(packed struct(u32) {
+                ///  HFCLKSTART task triggered or not
+                STATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Task not triggered
+                        NotTriggered = 0x0,
+                        ///  Task triggered
+                        Triggered = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  HFCLK status
+            HFCLKSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Source of HFCLK
+                SRC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  64 MHz internal oscillator (HFINT)
+                        RC = 0x0,
+                        ///  64 MHz crystal oscillator (HFXO)
+                        Xtal = 0x1,
+                    },
+                },
+                reserved16: u15,
+                ///  HFCLK state
+                STATE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  HFCLK not running
+                        NotRunning = 0x0,
+                        ///  HFCLK running
+                        Running = 0x1,
+                    },
+                },
+                padding: u15,
+            }),
+            reserved1044: [4]u8,
+            ///  Status indicating that LFCLKSTART task has been triggered
+            LFCLKRUN: mmio.Mmio(packed struct(u32) {
+                ///  LFCLKSTART task triggered or not
+                STATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Task not triggered
+                        NotTriggered = 0x0,
+                        ///  Task triggered
+                        Triggered = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  LFCLK status
+            LFCLKSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Source of LFCLK
+                SRC: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  32.768 kHz RC oscillator (LFRC)
+                        RC = 0x0,
+                        ///  32.768 kHz crystal oscillator (LFXO)
+                        Xtal = 0x1,
+                        ///  32.768 kHz synthesized from HFCLK (LFSYNT)
+                        Synth = 0x2,
+                        _,
+                    },
+                },
+                reserved16: u14,
+                ///  LFCLK state
+                STATE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  LFCLK not running
+                        NotRunning = 0x0,
+                        ///  LFCLK running
+                        Running = 0x1,
+                    },
+                },
+                padding: u15,
+            }),
+            ///  Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
+            LFCLKSRCCOPY: mmio.Mmio(packed struct(u32) {
+                ///  Clock source
+                SRC: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  32.768 kHz RC oscillator (LFRC)
+                        RC = 0x0,
+                        ///  32.768 kHz crystal oscillator (LFXO)
+                        Xtal = 0x1,
+                        ///  32.768 kHz synthesized from HFCLK (LFSYNT)
+                        Synth = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1304: [248]u8,
+            ///  Clock source for the LFCLK
+            LFCLKSRC: mmio.Mmio(packed struct(u32) {
+                ///  Clock source
+                SRC: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  32.768 kHz RC oscillator (LFRC)
+                        RC = 0x0,
+                        ///  32.768 kHz crystal oscillator (LFXO)
+                        Xtal = 0x1,
+                        ///  32.768 kHz synthesized from HFCLK (LFSYNT)
+                        Synth = 0x2,
+                        _,
+                    },
+                },
+                reserved16: u14,
+                ///  Enable or disable bypass of LFCLK crystal oscillator with external clock source
+                BYPASS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable (use with Xtal or low-swing external source)
+                        Disabled = 0x0,
+                        ///  Enable (use with rail-to-rail external source)
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable external source for LFCLK
+                EXTERNAL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable external source (use with Xtal)
+                        Disabled = 0x0,
+                        ///  Enable use of external source instead of Xtal (SRC needs to be set to Xtal)
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u14,
+            }),
+            reserved1320: [12]u8,
+            ///  HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task.
+            HFXODEBOUNCE: mmio.Mmio(packed struct(u32) {
+                ///  HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us.
+                HFXODEBOUNCE: packed union {
+                    raw: u8,
+                    value: enum(u8) {
+                        ///  256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals.
+                        Db256us = 0x10,
+                        ///  1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals.
+                        Db1024us = 0x40,
+                        _,
+                    },
+                },
+                padding: u24,
+            }),
+            reserved1336: [12]u8,
+            ///  Calibration timer interval
+            CTIV: mmio.Mmio(packed struct(u32) {
+                ///  Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.
+                CTIV: u7,
+                padding: u25,
+            }),
+            reserved1372: [32]u8,
+            ///  Clocking options for the trace port debug interface
+            TRACECONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two.
+                TRACEPORTSPEED: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  32 MHz trace port clock (TRACECLK = 16 MHz)
+                        @"32MHz" = 0x0,
+                        ///  16 MHz trace port clock (TRACECLK = 8 MHz)
+                        @"16MHz" = 0x1,
+                        ///  8 MHz trace port clock (TRACECLK = 4 MHz)
+                        @"8MHz" = 0x2,
+                        ///  4 MHz trace port clock (TRACECLK = 2 MHz)
+                        @"4MHz" = 0x3,
+                    },
+                },
+                reserved16: u14,
+                ///  Pin multiplexing of trace signals. See pin assignment chapter for more details.
+                TRACEMUX: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  No trace signals routed to pins. All pins can be used as regular GPIOs.
+                        GPIO = 0x0,
+                        ///  SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs.
+                        Serial = 0x1,
+                        ///  All trace signals (TRACECLK and TRACEDATA[n]) routed to pins.
+                        Parallel = 0x2,
+                        _,
+                    },
+                },
+                padding: u14,
+            }),
+            reserved1460: [84]u8,
+            ///  LFRC mode configuration
+            LFRCMODE: mmio.Mmio(packed struct(u32) {
+                ///  Set LFRC mode
+                MODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Normal mode
+                        Normal = 0x0,
+                        ///  Ultra-low power mode (ULP)
+                        ULP = 0x1,
+                    },
+                },
+                reserved16: u15,
+                ///  Active LFRC mode. This field is read only.
+                STATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Normal mode
+                        Normal = 0x0,
+                        ///  Ultra-low power mode (ULP)
+                        ULP = 0x1,
+                    },
+                },
+                padding: u15,
+            }),
+        };
+
+        ///  Power control
+        pub const POWER = extern struct {
+            reserved120: [120]u8,
+            ///  Enable Constant Latency mode
+            TASKS_CONSTLAT: mmio.Mmio(packed struct(u32) {
+                ///  Enable Constant Latency mode
+                TASKS_CONSTLAT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Enable Low-power mode (variable latency)
+            TASKS_LOWPWR: mmio.Mmio(packed struct(u32) {
+                ///  Enable Low-power mode (variable latency)
+                TASKS_LOWPWR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved264: [136]u8,
+            ///  Power failure warning
+            EVENTS_POFWARN: mmio.Mmio(packed struct(u32) {
+                ///  Power failure warning
+                EVENTS_POFWARN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved276: [8]u8,
+            ///  CPU entered WFI/WFE sleep
+            EVENTS_SLEEPENTER: mmio.Mmio(packed struct(u32) {
+                ///  CPU entered WFI/WFE sleep
+                EVENTS_SLEEPENTER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  CPU exited WFI/WFE sleep
+            EVENTS_SLEEPEXIT: mmio.Mmio(packed struct(u32) {
+                ///  CPU exited WFI/WFE sleep
+                EVENTS_SLEEPEXIT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Voltage supply detected on VBUS
+            EVENTS_USBDETECTED: mmio.Mmio(packed struct(u32) {
+                ///  Voltage supply detected on VBUS
+                EVENTS_USBDETECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Voltage supply removed from VBUS
+            EVENTS_USBREMOVED: mmio.Mmio(packed struct(u32) {
+                ///  Voltage supply removed from VBUS
+                EVENTS_USBREMOVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  USB 3.3 V supply ready
+            EVENTS_USBPWRRDY: mmio.Mmio(packed struct(u32) {
+                ///  USB 3.3 V supply ready
+                EVENTS_USBPWRRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [476]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Write '1' to enable interrupt for event POFWARN
+                POFWARN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved5: u2,
+                ///  Write '1' to enable interrupt for event SLEEPENTER
+                SLEEPENTER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event SLEEPEXIT
+                SLEEPEXIT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event USBDETECTED
+                USBDETECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event USBREMOVED
+                USBREMOVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event USBPWRRDY
+                USBPWRRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u22,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Write '1' to disable interrupt for event POFWARN
+                POFWARN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved5: u2,
+                ///  Write '1' to disable interrupt for event SLEEPENTER
+                SLEEPENTER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event SLEEPEXIT
+                SLEEPEXIT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event USBDETECTED
+                USBDETECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event USBREMOVED
+                USBREMOVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event USBPWRRDY
+                USBPWRRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u22,
+            }),
+            reserved1024: [244]u8,
+            ///  Reset reason
+            RESETREAS: mmio.Mmio(packed struct(u32) {
+                ///  Reset from pin-reset detected
+                RESETPIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset from watchdog detected
+                DOG: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset from soft reset detected
+                SREQ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset from CPU lock-up detected
+                LOCKUP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                reserved16: u12,
+                ///  Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO
+                OFF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP
+                LPCOMP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode
+                DIF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset due to wake up from System OFF mode by NFC field detect
+                NFC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Reset due to wake up from System OFF mode by VBUS rising into valid range
+                VBUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not detected
+                        NotDetected = 0x0,
+                        ///  Detected
+                        Detected = 0x1,
+                    },
+                },
+                padding: u11,
+            }),
+            reserved1064: [36]u8,
+            ///  Deprecated register - RAM status register
+            RAMSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  RAM block 0 is on or off/powering up
+                RAMBLOCK0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        Off = 0x0,
+                        ///  On
+                        On = 0x1,
+                    },
+                },
+                ///  RAM block 1 is on or off/powering up
+                RAMBLOCK1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        Off = 0x0,
+                        ///  On
+                        On = 0x1,
+                    },
+                },
+                ///  RAM block 2 is on or off/powering up
+                RAMBLOCK2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        Off = 0x0,
+                        ///  On
+                        On = 0x1,
+                    },
+                },
+                ///  RAM block 3 is on or off/powering up
+                RAMBLOCK3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Off
+                        Off = 0x0,
+                        ///  On
+                        On = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1080: [12]u8,
+            ///  USB supply status
+            USBREGSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information)
+                VBUSDETECT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  VBUS voltage below valid threshold
+                        NoVbus = 0x0,
+                        ///  VBUS voltage above valid threshold
+                        VbusPresent = 0x1,
+                    },
+                },
+                ///  USB supply output settling time elapsed
+                OUTPUTRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  USBREG output settling time not elapsed
+                        NotReady = 0x0,
+                        ///  USBREG output settling time elapsed (same information as USBPWRRDY event)
+                        Ready = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1280: [196]u8,
+            ///  System OFF register
+            SYSTEMOFF: mmio.Mmio(packed struct(u32) {
+                ///  Enable System OFF mode
+                SYSTEMOFF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Enable System OFF mode
+                        Enter = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1296: [12]u8,
+            ///  Power-fail comparator configuration
+            POFCON: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable power failure warning
+                POF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages.
+                THRESHOLD: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Set threshold to 1.7 V
+                        V17 = 0x4,
+                        ///  Set threshold to 1.8 V
+                        V18 = 0x5,
+                        ///  Set threshold to 1.9 V
+                        V19 = 0x6,
+                        ///  Set threshold to 2.0 V
+                        V20 = 0x7,
+                        ///  Set threshold to 2.1 V
+                        V21 = 0x8,
+                        ///  Set threshold to 2.2 V
+                        V22 = 0x9,
+                        ///  Set threshold to 2.3 V
+                        V23 = 0xa,
+                        ///  Set threshold to 2.4 V
+                        V24 = 0xb,
+                        ///  Set threshold to 2.5 V
+                        V25 = 0xc,
+                        ///  Set threshold to 2.6 V
+                        V26 = 0xd,
+                        ///  Set threshold to 2.7 V
+                        V27 = 0xe,
+                        ///  Set threshold to 2.8 V
+                        V28 = 0xf,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                ///  Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH).
+                THRESHOLDVDDH: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Set threshold to 2.7 V
+                        V27 = 0x0,
+                        ///  Set threshold to 2.8 V
+                        V28 = 0x1,
+                        ///  Set threshold to 2.9 V
+                        V29 = 0x2,
+                        ///  Set threshold to 3.0 V
+                        V30 = 0x3,
+                        ///  Set threshold to 3.1 V
+                        V31 = 0x4,
+                        ///  Set threshold to 3.2 V
+                        V32 = 0x5,
+                        ///  Set threshold to 3.3 V
+                        V33 = 0x6,
+                        ///  Set threshold to 3.4 V
+                        V34 = 0x7,
+                        ///  Set threshold to 3.5 V
+                        V35 = 0x8,
+                        ///  Set threshold to 3.6 V
+                        V36 = 0x9,
+                        ///  Set threshold to 3.7 V
+                        V37 = 0xa,
+                        ///  Set threshold to 3.8 V
+                        V38 = 0xb,
+                        ///  Set threshold to 3.9 V
+                        V39 = 0xc,
+                        ///  Set threshold to 4.0 V
+                        V40 = 0xd,
+                        ///  Set threshold to 4.1 V
+                        V41 = 0xe,
+                        ///  Set threshold to 4.2 V
+                        V42 = 0xf,
+                    },
+                },
+                padding: u20,
+            }),
+            reserved1308: [8]u8,
+            ///  General purpose retention register
+            GPREGRET: mmio.Mmio(packed struct(u32) {
+                ///  General purpose retention register
+                GPREGRET: u8,
+                padding: u24,
+            }),
+            ///  General purpose retention register
+            GPREGRET2: mmio.Mmio(packed struct(u32) {
+                ///  General purpose retention register
+                GPREGRET: u8,
+                padding: u24,
+            }),
+            reserved1400: [84]u8,
+            ///  Enable DC/DC converter for REG1 stage
+            DCDCEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable DC/DC converter for REG1 stage.
+                DCDCEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1408: [4]u8,
+            ///  Enable DC/DC converter for REG0 stage
+            DCDCEN0: mmio.Mmio(packed struct(u32) {
+                ///  Enable DC/DC converter for REG0 stage.
+                DCDCEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1600: [188]u8,
+            ///  Main supply status
+            MAINREGSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  Main supply status
+                MAINREGSTATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Normal voltage mode. Voltage supplied on VDD.
+                        Normal = 0x0,
+                        ///  High voltage mode. Voltage supplied on VDDH.
+                        High = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  GPIO Port 1
+        pub const P0 = extern struct {
+            reserved1284: [1284]u8,
+            ///  Write GPIO port
+            OUT: mmio.Mmio(packed struct(u32) {
+                ///  Pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin driver is low
+                        Low = 0x0,
+                        ///  Pin driver is high
+                        High = 0x1,
+                    },
+                },
+            }),
+            ///  Set individual bits in GPIO port
+            OUTSET: mmio.Mmio(packed struct(u32) {
+                ///  Pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+            }),
+            ///  Clear individual bits in GPIO port
+            OUTCLR: mmio.Mmio(packed struct(u32) {
+                ///  Pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin driver is low
+                        Low = 0x0,
+                        ///  Read: pin driver is high
+                        High = 0x1,
+                    },
+                },
+            }),
+            ///  Read GPIO port
+            IN: mmio.Mmio(packed struct(u32) {
+                ///  Pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+                ///  Pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin input is low
+                        Low = 0x0,
+                        ///  Pin input is high
+                        High = 0x1,
+                    },
+                },
+            }),
+            ///  Direction of GPIO pins
+            DIR: mmio.Mmio(packed struct(u32) {
+                ///  Pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pin set as input
+                        Input = 0x0,
+                        ///  Pin set as output
+                        Output = 0x1,
+                    },
+                },
+            }),
+            ///  DIR set register
+            DIRSET: mmio.Mmio(packed struct(u32) {
+                ///  Set as output pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as output pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+            }),
+            ///  DIR clear register
+            DIRCLR: mmio.Mmio(packed struct(u32) {
+                ///  Set as input pin 0
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 1
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 2
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 3
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 4
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 5
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 6
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 7
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 8
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 9
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 10
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 11
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 12
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 13
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 14
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 15
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 16
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 17
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 18
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 19
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 20
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 21
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 22
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 23
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 24
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 25
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 26
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 27
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 28
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 29
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 30
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+                ///  Set as input pin 31
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: pin set as input
+                        Input = 0x0,
+                        ///  Read: pin set as output
+                        Output = 0x1,
+                    },
+                },
+            }),
+            ///  Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers
+            LATCH: mmio.Mmio(packed struct(u32) {
+                ///  Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.
+                PIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.
+                PIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.
+                PIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.
+                PIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.
+                PIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.
+                PIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.
+                PIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.
+                PIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.
+                PIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.
+                PIN9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.
+                PIN10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.
+                PIN11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.
+                PIN12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.
+                PIN13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.
+                PIN14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.
+                PIN15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.
+                PIN16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.
+                PIN17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.
+                PIN18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.
+                PIN19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.
+                PIN20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.
+                PIN21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.
+                PIN22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.
+                PIN23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.
+                PIN24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.
+                PIN25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.
+                PIN26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.
+                PIN27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.
+                PIN28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.
+                PIN29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.
+                PIN30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+                ///  Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.
+                PIN31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Criteria has not been met
+                        NotLatched = 0x0,
+                        ///  Criteria has been met
+                        Latched = 0x1,
+                    },
+                },
+            }),
+            ///  Select between default DETECT signal behaviour and LDETECT mode
+            DETECTMODE: mmio.Mmio(packed struct(u32) {
+                ///  Select between default DETECT signal behaviour and LDETECT mode
+                DETECTMODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  DETECT directly connected to PIN DETECT signals
+                        Default = 0x0,
+                        ///  Use the latched LDETECT behaviour
+                        LDETECT = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1792: [472]u8,
+            ///  Description collection: Configuration of GPIO pins
+            PIN_CNF: [32]mmio.Mmio(packed struct(u32) {
+                ///  Pin direction. Same physical register as DIR register
+                DIR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Configure pin as an input pin
+                        Input = 0x0,
+                        ///  Configure pin as an output pin
+                        Output = 0x1,
+                    },
+                },
+                ///  Connect or disconnect input buffer
+                INPUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Connect input buffer
+                        Connect = 0x0,
+                        ///  Disconnect input buffer
+                        Disconnect = 0x1,
+                    },
+                },
+                ///  Pull configuration
+                PULL: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  No pull
+                        Disabled = 0x0,
+                        ///  Pull down on pin
+                        Pulldown = 0x1,
+                        ///  Pull up on pin
+                        Pullup = 0x3,
+                        _,
+                    },
+                },
+                reserved8: u4,
+                ///  Drive configuration
+                DRIVE: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Standard '0', standard '1'
+                        S0S1 = 0x0,
+                        ///  High drive '0', standard '1'
+                        H0S1 = 0x1,
+                        ///  Standard '0', high drive '1'
+                        S0H1 = 0x2,
+                        ///  High drive '0', high 'drive '1''
+                        H0H1 = 0x3,
+                        ///  Disconnect '0' standard '1' (normally used for wired-or connections)
+                        D0S1 = 0x4,
+                        ///  Disconnect '0', high drive '1' (normally used for wired-or connections)
+                        D0H1 = 0x5,
+                        ///  Standard '0'. disconnect '1' (normally used for wired-and connections)
+                        S0D1 = 0x6,
+                        ///  High drive '0', disconnect '1' (normally used for wired-and connections)
+                        H0D1 = 0x7,
+                    },
+                },
+                reserved16: u5,
+                ///  Pin sensing mechanism
+                SENSE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Sense for high level
+                        High = 0x2,
+                        ///  Sense for low level
+                        Low = 0x3,
+                        _,
+                    },
+                },
+                padding: u14,
+            }),
+        };
+
+        ///  Access control lists
+        pub const ACL = struct {};
+
+        ///  2.4 GHz radio
+        pub const RADIO = extern struct {
+            ///  Enable RADIO in TX mode
+            TASKS_TXEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable RADIO in TX mode
+                TASKS_TXEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Enable RADIO in RX mode
+            TASKS_RXEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable RADIO in RX mode
+                TASKS_RXEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start RADIO
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Start RADIO
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop RADIO
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop RADIO
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Disable RADIO
+            TASKS_DISABLE: mmio.Mmio(packed struct(u32) {
+                ///  Disable RADIO
+                TASKS_DISABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start the RSSI and take one single sample of the receive signal strength
+            TASKS_RSSISTART: mmio.Mmio(packed struct(u32) {
+                ///  Start the RSSI and take one single sample of the receive signal strength
+                TASKS_RSSISTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop the RSSI measurement
+            TASKS_RSSISTOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop the RSSI measurement
+                TASKS_RSSISTOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start the bit counter
+            TASKS_BCSTART: mmio.Mmio(packed struct(u32) {
+                ///  Start the bit counter
+                TASKS_BCSTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop the bit counter
+            TASKS_BCSTOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop the bit counter
+                TASKS_BCSTOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start the energy detect measurement used in IEEE 802.15.4 mode
+            TASKS_EDSTART: mmio.Mmio(packed struct(u32) {
+                ///  Start the energy detect measurement used in IEEE 802.15.4 mode
+                TASKS_EDSTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop the energy detect measurement
+            TASKS_EDSTOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop the energy detect measurement
+                TASKS_EDSTOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start the clear channel assessment used in IEEE 802.15.4 mode
+            TASKS_CCASTART: mmio.Mmio(packed struct(u32) {
+                ///  Start the clear channel assessment used in IEEE 802.15.4 mode
+                TASKS_CCASTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop the clear channel assessment
+            TASKS_CCASTOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop the clear channel assessment
+                TASKS_CCASTOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [204]u8,
+            ///  RADIO has ramped up and is ready to be started
+            EVENTS_READY: mmio.Mmio(packed struct(u32) {
+                ///  RADIO has ramped up and is ready to be started
+                EVENTS_READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Address sent or received
+            EVENTS_ADDRESS: mmio.Mmio(packed struct(u32) {
+                ///  Address sent or received
+                EVENTS_ADDRESS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Packet payload sent or received
+            EVENTS_PAYLOAD: mmio.Mmio(packed struct(u32) {
+                ///  Packet payload sent or received
+                EVENTS_PAYLOAD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Packet sent or received
+            EVENTS_END: mmio.Mmio(packed struct(u32) {
+                ///  Packet sent or received
+                EVENTS_END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  RADIO has been disabled
+            EVENTS_DISABLED: mmio.Mmio(packed struct(u32) {
+                ///  RADIO has been disabled
+                EVENTS_DISABLED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  A device address match occurred on the last received packet
+            EVENTS_DEVMATCH: mmio.Mmio(packed struct(u32) {
+                ///  A device address match occurred on the last received packet
+                EVENTS_DEVMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  No device address match occurred on the last received packet
+            EVENTS_DEVMISS: mmio.Mmio(packed struct(u32) {
+                ///  No device address match occurred on the last received packet
+                EVENTS_DEVMISS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Sampling of receive signal strength complete
+            EVENTS_RSSIEND: mmio.Mmio(packed struct(u32) {
+                ///  Sampling of receive signal strength complete
+                EVENTS_RSSIEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved296: [8]u8,
+            ///  Bit counter reached bit count value
+            EVENTS_BCMATCH: mmio.Mmio(packed struct(u32) {
+                ///  Bit counter reached bit count value
+                EVENTS_BCMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved304: [4]u8,
+            ///  Packet received with CRC ok
+            EVENTS_CRCOK: mmio.Mmio(packed struct(u32) {
+                ///  Packet received with CRC ok
+                EVENTS_CRCOK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Packet received with CRC error
+            EVENTS_CRCERROR: mmio.Mmio(packed struct(u32) {
+                ///  Packet received with CRC error
+                EVENTS_CRCERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  IEEE 802.15.4 length field received
+            EVENTS_FRAMESTART: mmio.Mmio(packed struct(u32) {
+                ///  IEEE 802.15.4 length field received
+                EVENTS_FRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.
+            EVENTS_EDEND: mmio.Mmio(packed struct(u32) {
+                ///  Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.
+                EVENTS_EDEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  The sampling of energy detection has stopped
+            EVENTS_EDSTOPPED: mmio.Mmio(packed struct(u32) {
+                ///  The sampling of energy detection has stopped
+                EVENTS_EDSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Wireless medium in idle - clear to send
+            EVENTS_CCAIDLE: mmio.Mmio(packed struct(u32) {
+                ///  Wireless medium in idle - clear to send
+                EVENTS_CCAIDLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Wireless medium busy - do not send
+            EVENTS_CCABUSY: mmio.Mmio(packed struct(u32) {
+                ///  Wireless medium busy - do not send
+                EVENTS_CCABUSY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  The CCA has stopped
+            EVENTS_CCASTOPPED: mmio.Mmio(packed struct(u32) {
+                ///  The CCA has stopped
+                EVENTS_CCASTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
+            EVENTS_RATEBOOST: mmio.Mmio(packed struct(u32) {
+                ///  Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
+                EVENTS_RATEBOOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  RADIO has ramped up and is ready to be started TX path
+            EVENTS_TXREADY: mmio.Mmio(packed struct(u32) {
+                ///  RADIO has ramped up and is ready to be started TX path
+                EVENTS_TXREADY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  RADIO has ramped up and is ready to be started RX path
+            EVENTS_RXREADY: mmio.Mmio(packed struct(u32) {
+                ///  RADIO has ramped up and is ready to be started RX path
+                EVENTS_RXREADY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  MAC header match found
+            EVENTS_MHRMATCH: mmio.Mmio(packed struct(u32) {
+                ///  MAC header match found
+                EVENTS_MHRMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved360: [8]u8,
+            ///  Preamble indicator.
+            EVENTS_SYNC: mmio.Mmio(packed struct(u32) {
+                ///  Preamble indicator.
+                EVENTS_SYNC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air.
+            EVENTS_PHYEND: mmio.Mmio(packed struct(u32) {
+                ///  Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air.
+                EVENTS_PHYEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [144]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between event READY and task START
+                READY_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event END and task DISABLE
+                END_DISABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event DISABLED and task TXEN
+                DISABLED_TXEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event DISABLED and task RXEN
+                DISABLED_RXEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event ADDRESS and task RSSISTART
+                ADDRESS_RSSISTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event END and task START
+                END_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event ADDRESS and task BCSTART
+                ADDRESS_BCSTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                reserved8: u1,
+                ///  Shortcut between event DISABLED and task RSSISTOP
+                DISABLED_RSSISTOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                reserved11: u2,
+                ///  Shortcut between event RXREADY and task CCASTART
+                RXREADY_CCASTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event CCAIDLE and task TXEN
+                CCAIDLE_TXEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event CCABUSY and task DISABLE
+                CCABUSY_DISABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event FRAMESTART and task BCSTART
+                FRAMESTART_BCSTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event READY and task EDSTART
+                READY_EDSTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event EDEND and task DISABLE
+                EDEND_DISABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event CCAIDLE and task STOP
+                CCAIDLE_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event TXREADY and task START
+                TXREADY_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event RXREADY and task START
+                RXREADY_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event PHYEND and task DISABLE
+                PHYEND_DISABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event PHYEND and task START
+                PHYEND_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u10,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ADDRESS
+                ADDRESS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event PAYLOAD
+                PAYLOAD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event DISABLED
+                DISABLED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event DEVMATCH
+                DEVMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event DEVMISS
+                DEVMISS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event RSSIEND
+                RSSIEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u2,
+                ///  Write '1' to enable interrupt for event BCMATCH
+                BCMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved12: u1,
+                ///  Write '1' to enable interrupt for event CRCOK
+                CRCOK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CRCERROR
+                CRCERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event FRAMESTART
+                FRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event EDEND
+                EDEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event EDSTOPPED
+                EDSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CCAIDLE
+                CCAIDLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CCABUSY
+                CCABUSY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CCASTOPPED
+                CCASTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event RATEBOOST
+                RATEBOOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TXREADY
+                TXREADY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event RXREADY
+                RXREADY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event MHRMATCH
+                MHRMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved26: u2,
+                ///  Write '1' to enable interrupt for event SYNC
+                SYNC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event PHYEND
+                PHYEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ADDRESS
+                ADDRESS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event PAYLOAD
+                PAYLOAD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event DISABLED
+                DISABLED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event DEVMATCH
+                DEVMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event DEVMISS
+                DEVMISS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event RSSIEND
+                RSSIEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u2,
+                ///  Write '1' to disable interrupt for event BCMATCH
+                BCMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved12: u1,
+                ///  Write '1' to disable interrupt for event CRCOK
+                CRCOK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CRCERROR
+                CRCERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event FRAMESTART
+                FRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event EDEND
+                EDEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event EDSTOPPED
+                EDSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CCAIDLE
+                CCAIDLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CCABUSY
+                CCABUSY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CCASTOPPED
+                CCASTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event RATEBOOST
+                RATEBOOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TXREADY
+                TXREADY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event RXREADY
+                RXREADY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event MHRMATCH
+                MHRMATCH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved26: u2,
+                ///  Write '1' to disable interrupt for event SYNC
+                SYNC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event PHYEND
+                PHYEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            reserved1024: [244]u8,
+            ///  CRC status
+            CRCSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  CRC status of packet received
+                CRCSTATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Packet received with CRC error
+                        CRCError = 0x0,
+                        ///  Packet received with CRC ok
+                        CRCOk = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1032: [4]u8,
+            ///  Received address
+            RXMATCH: mmio.Mmio(packed struct(u32) {
+                ///  Received address
+                RXMATCH: u3,
+                padding: u29,
+            }),
+            ///  CRC field of previously received packet
+            RXCRC: mmio.Mmio(packed struct(u32) {
+                ///  CRC field of previously received packet
+                RXCRC: u24,
+                padding: u8,
+            }),
+            ///  Device address match index
+            DAI: mmio.Mmio(packed struct(u32) {
+                ///  Device address match index
+                DAI: u3,
+                padding: u29,
+            }),
+            ///  Payload status
+            PDUSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Status on payload length vs. PCNF1.MAXLEN
+                PDUSTAT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Payload less than PCNF1.MAXLEN
+                        LessThan = 0x0,
+                        ///  Payload greater than PCNF1.MAXLEN
+                        GreaterThan = 0x1,
+                    },
+                },
+                ///  Status on what rate packet is received with in Long Range
+                CISTAT: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Frame is received at 125kbps
+                        LR125kbit = 0x0,
+                        ///  Frame is received at 500kbps
+                        LR500kbit = 0x1,
+                        _,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1284: [236]u8,
+            ///  Packet pointer
+            PACKETPTR: mmio.Mmio(packed struct(u32) {
+                ///  Packet pointer
+                PACKETPTR: u32,
+            }),
+            ///  Frequency
+            FREQUENCY: mmio.Mmio(packed struct(u32) {
+                ///  Radio channel frequency
+                FREQUENCY: u7,
+                reserved8: u1,
+                ///  Channel map selection.
+                MAP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Channel map between 2400 MHZ .. 2500 MHz
+                        Default = 0x0,
+                        ///  Channel map between 2360 MHZ .. 2460 MHz
+                        Low = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            ///  Output power
+            TXPOWER: mmio.Mmio(packed struct(u32) {
+                ///  RADIO output power
+                TXPOWER: packed union {
+                    raw: u8,
+                    value: enum(u8) {
+                        ///  +8 dBm
+                        Pos8dBm = 0x8,
+                        ///  +7 dBm
+                        Pos7dBm = 0x7,
+                        ///  +6 dBm
+                        Pos6dBm = 0x6,
+                        ///  +5 dBm
+                        Pos5dBm = 0x5,
+                        ///  +4 dBm
+                        Pos4dBm = 0x4,
+                        ///  +3 dBm
+                        Pos3dBm = 0x3,
+                        ///  +2 dBm
+                        Pos2dBm = 0x2,
+                        ///  0 dBm
+                        @"0dBm" = 0x0,
+                        ///  -4 dBm
+                        Neg4dBm = 0xfc,
+                        ///  -8 dBm
+                        Neg8dBm = 0xf8,
+                        ///  -12 dBm
+                        Neg12dBm = 0xf4,
+                        ///  -16 dBm
+                        Neg16dBm = 0xf0,
+                        ///  -20 dBm
+                        Neg20dBm = 0xec,
+                        ///  Deprecated enumerator - -40 dBm
+                        Neg30dBm = 0xe2,
+                        ///  -40 dBm
+                        Neg40dBm = 0xd8,
+                        _,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Data rate and modulation
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation.
+                MODE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  1 Mbit/s Nordic proprietary radio mode
+                        Nrf_1Mbit = 0x0,
+                        ///  2 Mbit/s Nordic proprietary radio mode
+                        Nrf_2Mbit = 0x1,
+                        ///  1 Mbit/s BLE
+                        Ble_1Mbit = 0x3,
+                        ///  2 Mbit/s BLE
+                        Ble_2Mbit = 0x4,
+                        ///  Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX
+                        Ble_LR125Kbit = 0x5,
+                        ///  Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX
+                        Ble_LR500Kbit = 0x6,
+                        ///  IEEE 802.15.4-2006 250 kbit/s
+                        Ieee802154_250Kbit = 0xf,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Packet configuration register 0
+            PCNF0: mmio.Mmio(packed struct(u32) {
+                ///  Length on air of LENGTH field in number of bits.
+                LFLEN: u4,
+                reserved8: u4,
+                ///  Length on air of S0 field in number of bytes.
+                S0LEN: u1,
+                reserved16: u7,
+                ///  Length on air of S1 field in number of bits.
+                S1LEN: u4,
+                ///  Include or exclude S1 field in RAM
+                S1INCL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Include S1 field in RAM only if S1LEN > 0
+                        Automatic = 0x0,
+                        ///  Always include S1 field in RAM independent of S1LEN
+                        Include = 0x1,
+                    },
+                },
+                reserved22: u1,
+                ///  Length of code indicator - long range
+                CILEN: u2,
+                ///  Length of preamble on air. Decision point: TASKS_START task
+                PLEN: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  8-bit preamble
+                        @"8bit" = 0x0,
+                        ///  16-bit preamble
+                        @"16bit" = 0x1,
+                        ///  32-bit zero preamble - used for IEEE 802.15.4
+                        @"32bitZero" = 0x2,
+                        ///  Preamble - used for BLE long range
+                        LongRange = 0x3,
+                    },
+                },
+                ///  Indicates if LENGTH field contains CRC or not
+                CRCINC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  LENGTH does not contain CRC
+                        Exclude = 0x0,
+                        ///  LENGTH includes CRC
+                        Include = 0x1,
+                    },
+                },
+                reserved29: u2,
+                ///  Length of TERM field in Long Range operation
+                TERMLEN: u2,
+                padding: u1,
+            }),
+            ///  Packet configuration register 1
+            PCNF1: mmio.Mmio(packed struct(u32) {
+                ///  Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.
+                MAXLEN: u8,
+                ///  Static length in number of bytes
+                STATLEN: u8,
+                ///  Base address length in number of bytes
+                BALEN: u3,
+                reserved24: u5,
+                ///  On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.
+                ENDIAN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Least significant bit on air first
+                        Little = 0x0,
+                        ///  Most significant bit on air first
+                        Big = 0x1,
+                    },
+                },
+                ///  Enable or disable packet whitening
+                WHITEEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u6,
+            }),
+            ///  Base address 0
+            BASE0: mmio.Mmio(packed struct(u32) {
+                ///  Base address 0
+                BASE0: u32,
+            }),
+            ///  Base address 1
+            BASE1: mmio.Mmio(packed struct(u32) {
+                ///  Base address 1
+                BASE1: u32,
+            }),
+            ///  Prefixes bytes for logical addresses 0-3
+            PREFIX0: mmio.Mmio(packed struct(u32) {
+                ///  Address prefix 0.
+                AP0: u8,
+                ///  Address prefix 1.
+                AP1: u8,
+                ///  Address prefix 2.
+                AP2: u8,
+                ///  Address prefix 3.
+                AP3: u8,
+            }),
+            ///  Prefixes bytes for logical addresses 4-7
+            PREFIX1: mmio.Mmio(packed struct(u32) {
+                ///  Address prefix 4.
+                AP4: u8,
+                ///  Address prefix 5.
+                AP5: u8,
+                ///  Address prefix 6.
+                AP6: u8,
+                ///  Address prefix 7.
+                AP7: u8,
+            }),
+            ///  Transmit address select
+            TXADDRESS: mmio.Mmio(packed struct(u32) {
+                ///  Transmit address select
+                TXADDRESS: u3,
+                padding: u29,
+            }),
+            ///  Receive address select
+            RXADDRESSES: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable reception on logical address 0.
+                ADDR0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 1.
+                ADDR1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 2.
+                ADDR2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 3.
+                ADDR3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 4.
+                ADDR4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 5.
+                ADDR5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 6.
+                ADDR6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable reception on logical address 7.
+                ADDR7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  CRC configuration
+            CRCCNF: mmio.Mmio(packed struct(u32) {
+                ///  CRC length in number of bytes.
+                LEN: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  CRC length is zero and CRC calculation is disabled
+                        Disabled = 0x0,
+                        ///  CRC length is one byte and CRC calculation is enabled
+                        One = 0x1,
+                        ///  CRC length is two bytes and CRC calculation is enabled
+                        Two = 0x2,
+                        ///  CRC length is three bytes and CRC calculation is enabled
+                        Three = 0x3,
+                    },
+                },
+                reserved8: u6,
+                ///  Include or exclude packet address field out of CRC calculation.
+                SKIPADDR: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  CRC calculation includes address field
+                        Include = 0x0,
+                        ///  CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.
+                        Skip = 0x1,
+                        ///  CRC calculation as per 802.15.4 standard. Starting at first byte after length field.
+                        Ieee802154 = 0x2,
+                        _,
+                    },
+                },
+                padding: u22,
+            }),
+            ///  CRC polynomial
+            CRCPOLY: mmio.Mmio(packed struct(u32) {
+                ///  CRC polynomial
+                CRCPOLY: u24,
+                padding: u8,
+            }),
+            ///  CRC initial value
+            CRCINIT: mmio.Mmio(packed struct(u32) {
+                ///  CRC initial value
+                CRCINIT: u24,
+                padding: u8,
+            }),
+            reserved1348: [4]u8,
+            ///  Interframe spacing in us
+            TIFS: mmio.Mmio(packed struct(u32) {
+                ///  Interframe spacing in us
+                TIFS: u10,
+                padding: u22,
+            }),
+            ///  RSSI sample
+            RSSISAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  RSSI sample
+                RSSISAMPLE: u7,
+                padding: u25,
+            }),
+            reserved1360: [4]u8,
+            ///  Current radio state
+            STATE: mmio.Mmio(packed struct(u32) {
+                ///  Current radio state
+                STATE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  RADIO is in the Disabled state
+                        Disabled = 0x0,
+                        ///  RADIO is in the RXRU state
+                        RxRu = 0x1,
+                        ///  RADIO is in the RXIDLE state
+                        RxIdle = 0x2,
+                        ///  RADIO is in the RX state
+                        Rx = 0x3,
+                        ///  RADIO is in the RXDISABLED state
+                        RxDisable = 0x4,
+                        ///  RADIO is in the TXRU state
+                        TxRu = 0x9,
+                        ///  RADIO is in the TXIDLE state
+                        TxIdle = 0xa,
+                        ///  RADIO is in the TX state
+                        Tx = 0xb,
+                        ///  RADIO is in the TXDISABLED state
+                        TxDisable = 0xc,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Data whitening initial value
+            DATAWHITEIV: mmio.Mmio(packed struct(u32) {
+                ///  Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.
+                DATAWHITEIV: u7,
+                padding: u25,
+            }),
+            reserved1376: [8]u8,
+            ///  Bit counter compare
+            BCC: mmio.Mmio(packed struct(u32) {
+                ///  Bit counter compare
+                BCC: u32,
+            }),
+            reserved1536: [156]u8,
+            ///  Description collection: Device address base segment n
+            DAB: [8]mmio.Mmio(packed struct(u32) {
+                ///  Device address base segment n
+                DAB: u32,
+            }),
+            ///  Description collection: Device address prefix n
+            DAP: [8]mmio.Mmio(packed struct(u32) {
+                ///  Device address prefix n
+                DAP: u16,
+                padding: u16,
+            }),
+            ///  Device address match configuration
+            DACNF: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable device address matching using device address 0
+                ENA0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 1
+                ENA1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 2
+                ENA2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 3
+                ENA3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 4
+                ENA4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 5
+                ENA5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 6
+                ENA6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable device address matching using device address 7
+                ENA7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  TxAdd for device address 0
+                TXADD0: u1,
+                ///  TxAdd for device address 1
+                TXADD1: u1,
+                ///  TxAdd for device address 2
+                TXADD2: u1,
+                ///  TxAdd for device address 3
+                TXADD3: u1,
+                ///  TxAdd for device address 4
+                TXADD4: u1,
+                ///  TxAdd for device address 5
+                TXADD5: u1,
+                ///  TxAdd for device address 6
+                TXADD6: u1,
+                ///  TxAdd for device address 7
+                TXADD7: u1,
+                padding: u16,
+            }),
+            ///  Search pattern configuration
+            MHRMATCHCONF: mmio.Mmio(packed struct(u32) {
+                ///  Search pattern configuration
+                MHRMATCHCONF: u32,
+            }),
+            ///  Pattern mask
+            MHRMATCHMAS: mmio.Mmio(packed struct(u32) {
+                ///  Pattern mask
+                MHRMATCHMAS: u32,
+            }),
+            reserved1616: [4]u8,
+            ///  Radio mode configuration register 0
+            MODECNF0: mmio.Mmio(packed struct(u32) {
+                ///  Radio ramp-up time
+                RU: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51
+                        Default = 0x0,
+                        ///  Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information
+                        Fast = 0x1,
+                    },
+                },
+                reserved8: u7,
+                ///  Default TX value
+                DTX: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Transmit '1'
+                        B1 = 0x0,
+                        ///  Transmit '0'
+                        B0 = 0x1,
+                        ///  Transmit center frequency
+                        Center = 0x2,
+                        _,
+                    },
+                },
+                padding: u22,
+            }),
+            reserved1632: [12]u8,
+            ///  IEEE 802.15.4 start of frame delimiter
+            SFD: mmio.Mmio(packed struct(u32) {
+                ///  IEEE 802.15.4 start of frame delimiter
+                SFD: u8,
+                padding: u24,
+            }),
+            ///  IEEE 802.15.4 energy detect loop count
+            EDCNT: mmio.Mmio(packed struct(u32) {
+                ///  IEEE 802.15.4 energy detect loop count
+                EDCNT: u21,
+                padding: u11,
+            }),
+            ///  IEEE 802.15.4 energy detect level
+            EDSAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  IEEE 802.15.4 energy detect level
+                EDLVL: u8,
+                padding: u24,
+            }),
+            ///  IEEE 802.15.4 clear channel assessment control
+            CCACTRL: mmio.Mmio(packed struct(u32) {
+                ///  CCA mode of operation
+                CCAMODE: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Energy above threshold
+                        EdMode = 0x0,
+                        ///  Carrier seen
+                        CarrierMode = 0x1,
+                        ///  Energy above threshold AND carrier seen
+                        CarrierAndEdMode = 0x2,
+                        ///  Energy above threshold OR carrier seen
+                        CarrierOrEdMode = 0x3,
+                        ///  Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging.
+                        EdModeTest1 = 0x4,
+                        _,
+                    },
+                },
+                reserved8: u5,
+                ///  CCA energy busy threshold. Used in all the CCA modes except CarrierMode.
+                CCAEDTHRES: u8,
+                ///  CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode.
+                CCACORRTHRES: u8,
+                ///  Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled.
+                CCACORRCNT: u8,
+            }),
+            reserved4092: [2444]u8,
+            ///  Peripheral power control
+            POWER: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.
+                POWER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Peripheral is powered off
+                        Disabled = 0x0,
+                        ///  Peripheral is powered on
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  Universal Asynchronous Receiver/Transmitter
+        pub const UART0 = extern struct {
+            ///  Start UART receiver
+            TASKS_STARTRX: mmio.Mmio(packed struct(u32) {
+                ///  Start UART receiver
+                TASKS_STARTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop UART receiver
+            TASKS_STOPRX: mmio.Mmio(packed struct(u32) {
+                ///  Stop UART receiver
+                TASKS_STOPRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start UART transmitter
+            TASKS_STARTTX: mmio.Mmio(packed struct(u32) {
+                ///  Start UART transmitter
+                TASKS_STARTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop UART transmitter
+            TASKS_STOPTX: mmio.Mmio(packed struct(u32) {
+                ///  Stop UART transmitter
+                TASKS_STOPTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved28: [12]u8,
+            ///  Suspend UART
+            TASKS_SUSPEND: mmio.Mmio(packed struct(u32) {
+                ///  Suspend UART
+                TASKS_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [224]u8,
+            ///  CTS is activated (set low). Clear To Send.
+            EVENTS_CTS: mmio.Mmio(packed struct(u32) {
+                ///  CTS is activated (set low). Clear To Send.
+                EVENTS_CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  CTS is deactivated (set high). Not Clear To Send.
+            EVENTS_NCTS: mmio.Mmio(packed struct(u32) {
+                ///  CTS is deactivated (set high). Not Clear To Send.
+                EVENTS_NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Data received in RXD
+            EVENTS_RXDRDY: mmio.Mmio(packed struct(u32) {
+                ///  Data received in RXD
+                EVENTS_RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved284: [16]u8,
+            ///  Data sent from TXD
+            EVENTS_TXDRDY: mmio.Mmio(packed struct(u32) {
+                ///  Data sent from TXD
+                EVENTS_TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved292: [4]u8,
+            ///  Error detected
+            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
+                ///  Error detected
+                EVENTS_ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved324: [28]u8,
+            ///  Receiver timeout
+            EVENTS_RXTO: mmio.Mmio(packed struct(u32) {
+                ///  Receiver timeout
+                EVENTS_RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [184]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                ///  Shortcut between event CTS and task STARTRX
+                CTS_STARTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event NCTS and task STOPRX
+                NCTS_STOPRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event CTS
+                CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event NCTS
+                NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event RXDRDY
+                RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u4,
+                ///  Write '1' to enable interrupt for event TXDRDY
+                TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u1,
+                ///  Write '1' to enable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved17: u7,
+                ///  Write '1' to enable interrupt for event RXTO
+                RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u14,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event CTS
+                CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event NCTS
+                NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event RXDRDY
+                RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u4,
+                ///  Write '1' to disable interrupt for event TXDRDY
+                TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u1,
+                ///  Write '1' to disable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved17: u7,
+                ///  Write '1' to disable interrupt for event RXTO
+                RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u14,
+            }),
+            reserved1152: [372]u8,
+            ///  Error source
+            ERRORSRC: mmio.Mmio(packed struct(u32) {
+                ///  Overrun error
+                OVERRUN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Parity error
+                PARITY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Framing error occurred
+                FRAMING: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Break condition
+                BREAK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1280: [124]u8,
+            ///  Enable UART
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable UART
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable UART
+                        Disabled = 0x0,
+                        ///  Enable UART
+                        Enabled = 0x4,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1304: [20]u8,
+            ///  RXD register
+            RXD: mmio.Mmio(packed struct(u32) {
+                ///  RX data received in previous transfers, double buffered
+                RXD: u8,
+                padding: u24,
+            }),
+            ///  TXD register
+            TXD: mmio.Mmio(packed struct(u32) {
+                ///  TX data to be transferred
+                TXD: u8,
+                padding: u24,
+            }),
+            reserved1316: [4]u8,
+            ///  Baud rate. Accuracy depends on the HFCLK source selected.
+            BAUDRATE: mmio.Mmio(packed struct(u32) {
+                ///  Baud rate
+                BAUDRATE: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  1200 baud (actual rate: 1205)
+                        Baud1200 = 0x4f000,
+                        ///  2400 baud (actual rate: 2396)
+                        Baud2400 = 0x9d000,
+                        ///  4800 baud (actual rate: 4808)
+                        Baud4800 = 0x13b000,
+                        ///  9600 baud (actual rate: 9598)
+                        Baud9600 = 0x275000,
+                        ///  14400 baud (actual rate: 14414)
+                        Baud14400 = 0x3b0000,
+                        ///  19200 baud (actual rate: 19208)
+                        Baud19200 = 0x4ea000,
+                        ///  28800 baud (actual rate: 28829)
+                        Baud28800 = 0x75f000,
+                        ///  31250 baud
+                        Baud31250 = 0x800000,
+                        ///  38400 baud (actual rate: 38462)
+                        Baud38400 = 0x9d5000,
+                        ///  56000 baud (actual rate: 55944)
+                        Baud56000 = 0xe50000,
+                        ///  57600 baud (actual rate: 57762)
+                        Baud57600 = 0xebf000,
+                        ///  76800 baud (actual rate: 76923)
+                        Baud76800 = 0x13a9000,
+                        ///  115200 baud (actual rate: 115942)
+                        Baud115200 = 0x1d7e000,
+                        ///  230400 baud (actual rate: 231884)
+                        Baud230400 = 0x3afb000,
+                        ///  250000 baud
+                        Baud250000 = 0x4000000,
+                        ///  460800 baud (actual rate: 470588)
+                        Baud460800 = 0x75f7000,
+                        ///  921600 baud (actual rate: 941176)
+                        Baud921600 = 0xebed000,
+                        ///  1Mega baud
+                        Baud1M = 0x10000000,
+                        _,
+                    },
+                },
+            }),
+            reserved1388: [68]u8,
+            ///  Configuration of parity and hardware flow control
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Hardware flow control
+                HWFC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Parity
+                PARITY: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Exclude parity bit
+                        Excluded = 0x0,
+                        ///  Include parity bit
+                        Included = 0x7,
+                        _,
+                    },
+                },
+                ///  Stop bits
+                STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  One stop bit
+                        One = 0x0,
+                        ///  Two stop bits
+                        Two = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+        };
+
+        ///  UART with EasyDMA 0
+        pub const UARTE0 = extern struct {
+            ///  Start UART receiver
+            TASKS_STARTRX: mmio.Mmio(packed struct(u32) {
+                ///  Start UART receiver
+                TASKS_STARTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop UART receiver
+            TASKS_STOPRX: mmio.Mmio(packed struct(u32) {
+                ///  Stop UART receiver
+                TASKS_STOPRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start UART transmitter
+            TASKS_STARTTX: mmio.Mmio(packed struct(u32) {
+                ///  Start UART transmitter
+                TASKS_STARTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop UART transmitter
+            TASKS_STOPTX: mmio.Mmio(packed struct(u32) {
+                ///  Stop UART transmitter
+                TASKS_STOPTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved44: [28]u8,
+            ///  Flush RX FIFO into RX buffer
+            TASKS_FLUSHRX: mmio.Mmio(packed struct(u32) {
+                ///  Flush RX FIFO into RX buffer
+                TASKS_FLUSHRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [208]u8,
+            ///  CTS is activated (set low). Clear To Send.
+            EVENTS_CTS: mmio.Mmio(packed struct(u32) {
+                ///  CTS is activated (set low). Clear To Send.
+                EVENTS_CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  CTS is deactivated (set high). Not Clear To Send.
+            EVENTS_NCTS: mmio.Mmio(packed struct(u32) {
+                ///  CTS is deactivated (set high). Not Clear To Send.
+                EVENTS_NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Data received in RXD (but potentially not yet transferred to Data RAM)
+            EVENTS_RXDRDY: mmio.Mmio(packed struct(u32) {
+                ///  Data received in RXD (but potentially not yet transferred to Data RAM)
+                EVENTS_RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved272: [4]u8,
+            ///  Receive buffer is filled up
+            EVENTS_ENDRX: mmio.Mmio(packed struct(u32) {
+                ///  Receive buffer is filled up
+                EVENTS_ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved284: [8]u8,
+            ///  Data sent from TXD
+            EVENTS_TXDRDY: mmio.Mmio(packed struct(u32) {
+                ///  Data sent from TXD
+                EVENTS_TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Last TX byte transmitted
+            EVENTS_ENDTX: mmio.Mmio(packed struct(u32) {
+                ///  Last TX byte transmitted
+                EVENTS_ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Error detected
+            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
+                ///  Error detected
+                EVENTS_ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved324: [28]u8,
+            ///  Receiver timeout
+            EVENTS_RXTO: mmio.Mmio(packed struct(u32) {
+                ///  Receiver timeout
+                EVENTS_RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved332: [4]u8,
+            ///  UART receiver has started
+            EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) {
+                ///  UART receiver has started
+                EVENTS_RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  UART transmitter has started
+            EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) {
+                ///  UART transmitter has started
+                EVENTS_TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved344: [4]u8,
+            ///  Transmitter stopped
+            EVENTS_TXSTOPPED: mmio.Mmio(packed struct(u32) {
+                ///  Transmitter stopped
+                EVENTS_TXSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [164]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved5: u5,
+                ///  Shortcut between event ENDRX and task STARTRX
+                ENDRX_STARTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event ENDRX and task STOPRX
+                ENDRX_STOPRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u25,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for event CTS
+                CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event NCTS
+                NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event RXDRDY
+                RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u1,
+                ///  Enable or disable interrupt for event ENDRX
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u2,
+                ///  Enable or disable interrupt for event TXDRDY
+                TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDTX
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved17: u7,
+                ///  Enable or disable interrupt for event RXTO
+                RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u1,
+                ///  Enable or disable interrupt for event RXSTARTED
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TXSTARTED
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved22: u1,
+                ///  Enable or disable interrupt for event TXSTOPPED
+                TXSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u9,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event CTS
+                CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event NCTS
+                NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event RXDRDY
+                RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u1,
+                ///  Write '1' to enable interrupt for event ENDRX
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u2,
+                ///  Write '1' to enable interrupt for event TXDRDY
+                TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDTX
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved17: u7,
+                ///  Write '1' to enable interrupt for event RXTO
+                RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u1,
+                ///  Write '1' to enable interrupt for event RXSTARTED
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TXSTARTED
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved22: u1,
+                ///  Write '1' to enable interrupt for event TXSTOPPED
+                TXSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u9,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event CTS
+                CTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event NCTS
+                NCTS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event RXDRDY
+                RXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u1,
+                ///  Write '1' to disable interrupt for event ENDRX
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u2,
+                ///  Write '1' to disable interrupt for event TXDRDY
+                TXDRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDTX
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved17: u7,
+                ///  Write '1' to disable interrupt for event RXTO
+                RXTO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u1,
+                ///  Write '1' to disable interrupt for event RXSTARTED
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TXSTARTED
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved22: u1,
+                ///  Write '1' to disable interrupt for event TXSTOPPED
+                TXSTOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u9,
+            }),
+            reserved1152: [372]u8,
+            ///  Error source Note : this register is read / write one to clear.
+            ERRORSRC: mmio.Mmio(packed struct(u32) {
+                ///  Overrun error
+                OVERRUN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Parity error
+                PARITY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Framing error occurred
+                FRAMING: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  Break condition
+                BREAK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1280: [124]u8,
+            ///  Enable UART
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable UARTE
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable UARTE
+                        Disabled = 0x0,
+                        ///  Enable UARTE
+                        Enabled = 0x8,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1316: [32]u8,
+            ///  Baud rate. Accuracy depends on the HFCLK source selected.
+            BAUDRATE: mmio.Mmio(packed struct(u32) {
+                ///  Baud rate
+                BAUDRATE: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  1200 baud (actual rate: 1205)
+                        Baud1200 = 0x4f000,
+                        ///  2400 baud (actual rate: 2396)
+                        Baud2400 = 0x9d000,
+                        ///  4800 baud (actual rate: 4808)
+                        Baud4800 = 0x13b000,
+                        ///  9600 baud (actual rate: 9598)
+                        Baud9600 = 0x275000,
+                        ///  14400 baud (actual rate: 14401)
+                        Baud14400 = 0x3af000,
+                        ///  19200 baud (actual rate: 19208)
+                        Baud19200 = 0x4ea000,
+                        ///  28800 baud (actual rate: 28777)
+                        Baud28800 = 0x75c000,
+                        ///  31250 baud
+                        Baud31250 = 0x800000,
+                        ///  38400 baud (actual rate: 38369)
+                        Baud38400 = 0x9d0000,
+                        ///  56000 baud (actual rate: 55944)
+                        Baud56000 = 0xe50000,
+                        ///  57600 baud (actual rate: 57554)
+                        Baud57600 = 0xeb0000,
+                        ///  76800 baud (actual rate: 76923)
+                        Baud76800 = 0x13a9000,
+                        ///  115200 baud (actual rate: 115108)
+                        Baud115200 = 0x1d60000,
+                        ///  230400 baud (actual rate: 231884)
+                        Baud230400 = 0x3b00000,
+                        ///  250000 baud
+                        Baud250000 = 0x4000000,
+                        ///  460800 baud (actual rate: 457143)
+                        Baud460800 = 0x7400000,
+                        ///  921600 baud (actual rate: 941176)
+                        Baud921600 = 0xf000000,
+                        ///  1Mega baud
+                        Baud1M = 0x10000000,
+                        _,
+                    },
+                },
+            }),
+            reserved1388: [68]u8,
+            ///  Configuration of parity and hardware flow control
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Hardware flow control
+                HWFC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Parity
+                PARITY: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Exclude parity bit
+                        Excluded = 0x0,
+                        ///  Include even parity bit
+                        Included = 0x7,
+                        _,
+                    },
+                },
+                ///  Stop bits
+                STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  One stop bit
+                        One = 0x0,
+                        ///  Two stop bits
+                        Two = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+        };
+
+        ///  Serial Peripheral Interface 0
+        pub const SPI0 = extern struct {
+            reserved264: [264]u8,
+            ///  TXD byte sent and RXD byte received
+            EVENTS_READY: mmio.Mmio(packed struct(u32) {
+                ///  TXD byte sent and RXD byte received
+                EVENTS_READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [504]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Write '1' to enable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Write '1' to disable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1280: [500]u8,
+            ///  Enable SPI
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable SPI
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable SPI
+                        Disabled = 0x0,
+                        ///  Enable SPI
+                        Enabled = 0x1,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1304: [20]u8,
+            ///  RXD register
+            RXD: mmio.Mmio(packed struct(u32) {
+                ///  RX data received. Double buffered
+                RXD: u8,
+                padding: u24,
+            }),
+            ///  TXD register
+            TXD: mmio.Mmio(packed struct(u32) {
+                ///  TX data to send. Double buffered
+                TXD: u8,
+                padding: u24,
+            }),
+            reserved1316: [4]u8,
+            ///  SPI frequency. Accuracy depends on the HFCLK source selected.
+            FREQUENCY: mmio.Mmio(packed struct(u32) {
+                ///  SPI master data rate
+                FREQUENCY: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  125 kbps
+                        K125 = 0x2000000,
+                        ///  250 kbps
+                        K250 = 0x4000000,
+                        ///  500 kbps
+                        K500 = 0x8000000,
+                        ///  1 Mbps
+                        M1 = 0x10000000,
+                        ///  2 Mbps
+                        M2 = 0x20000000,
+                        ///  4 Mbps
+                        M4 = 0x40000000,
+                        ///  8 Mbps
+                        M8 = 0x80000000,
+                        _,
+                    },
+                },
+            }),
+            reserved1364: [44]u8,
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Bit order
+                ORDER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Most significant bit shifted out first
+                        MsbFirst = 0x0,
+                        ///  Least significant bit shifted out first
+                        LsbFirst = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) phase
+                CPHA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Sample on leading edge of clock, shift serial data on trailing edge
+                        Leading = 0x0,
+                        ///  Sample on trailing edge of clock, shift serial data on leading edge
+                        Trailing = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) polarity
+                CPOL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Active high
+                        ActiveHigh = 0x0,
+                        ///  Active low
+                        ActiveLow = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+        };
+
+        ///  Serial Peripheral Interface Master with EasyDMA 0
+        pub const SPIM0 = extern struct {
+            reserved16: [16]u8,
+            ///  Start SPI transaction
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Start SPI transaction
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop SPI transaction
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop SPI transaction
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved28: [4]u8,
+            ///  Suspend SPI transaction
+            TASKS_SUSPEND: mmio.Mmio(packed struct(u32) {
+                ///  Suspend SPI transaction
+                TASKS_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Resume SPI transaction
+            TASKS_RESUME: mmio.Mmio(packed struct(u32) {
+                ///  Resume SPI transaction
+                TASKS_RESUME: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved260: [224]u8,
+            ///  SPI transaction has stopped
+            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
+                ///  SPI transaction has stopped
+                EVENTS_STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved272: [8]u8,
+            ///  End of RXD buffer reached
+            EVENTS_ENDRX: mmio.Mmio(packed struct(u32) {
+                ///  End of RXD buffer reached
+                EVENTS_ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved280: [4]u8,
+            ///  End of RXD buffer and TXD buffer reached
+            EVENTS_END: mmio.Mmio(packed struct(u32) {
+                ///  End of RXD buffer and TXD buffer reached
+                EVENTS_END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved288: [4]u8,
+            ///  End of TXD buffer reached
+            EVENTS_ENDTX: mmio.Mmio(packed struct(u32) {
+                ///  End of TXD buffer reached
+                EVENTS_ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved332: [40]u8,
+            ///  Transaction started
+            EVENTS_STARTED: mmio.Mmio(packed struct(u32) {
+                ///  Transaction started
+                EVENTS_STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [176]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved17: u17,
+                ///  Shortcut between event END and task START
+                END_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u14,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to enable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u2,
+                ///  Write '1' to enable interrupt for event ENDRX
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved6: u1,
+                ///  Write '1' to enable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved8: u1,
+                ///  Write '1' to enable interrupt for event ENDTX
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u10,
+                ///  Write '1' to enable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u2,
+                ///  Write '1' to disable interrupt for event ENDRX
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved6: u1,
+                ///  Write '1' to disable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved8: u1,
+                ///  Write '1' to disable interrupt for event ENDTX
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u10,
+                ///  Write '1' to disable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            reserved1024: [244]u8,
+            ///  Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU.
+            STALLSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Stall status for EasyDMA RAM reads
+                TX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No stall
+                        NOSTALL = 0x0,
+                        ///  A stall has occurred
+                        STALL = 0x1,
+                    },
+                },
+                ///  Stall status for EasyDMA RAM writes
+                RX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No stall
+                        NOSTALL = 0x0,
+                        ///  A stall has occurred
+                        STALL = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1280: [252]u8,
+            ///  Enable SPIM
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable SPIM
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable SPIM
+                        Disabled = 0x0,
+                        ///  Enable SPIM
+                        Enabled = 0x7,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1316: [32]u8,
+            ///  SPI frequency. Accuracy depends on the HFCLK source selected.
+            FREQUENCY: mmio.Mmio(packed struct(u32) {
+                ///  SPI master data rate
+                FREQUENCY: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  125 kbps
+                        K125 = 0x2000000,
+                        ///  250 kbps
+                        K250 = 0x4000000,
+                        ///  500 kbps
+                        K500 = 0x8000000,
+                        ///  1 Mbps
+                        M1 = 0x10000000,
+                        ///  2 Mbps
+                        M2 = 0x20000000,
+                        ///  4 Mbps
+                        M4 = 0x40000000,
+                        ///  8 Mbps
+                        M8 = 0x80000000,
+                        ///  16 Mbps
+                        M16 = 0xa000000,
+                        ///  32 Mbps
+                        M32 = 0x14000000,
+                        _,
+                    },
+                },
+            }),
+            reserved1364: [44]u8,
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Bit order
+                ORDER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Most significant bit shifted out first
+                        MsbFirst = 0x0,
+                        ///  Least significant bit shifted out first
+                        LsbFirst = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) phase
+                CPHA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Sample on leading edge of clock, shift serial data on trailing edge
+                        Leading = 0x0,
+                        ///  Sample on trailing edge of clock, shift serial data on leading edge
+                        Trailing = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) polarity
+                CPOL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Active high
+                        ActiveHigh = 0x0,
+                        ///  Active low
+                        ActiveLow = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1384: [16]u8,
+            ///  Polarity of CSN output
+            CSNPOL: mmio.Mmio(packed struct(u32) {
+                ///  Polarity of CSN output
+                CSNPOL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Active low (idle state high)
+                        LOW = 0x0,
+                        ///  Active high (idle state low)
+                        HIGH = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Pin select for DCX signal
+            PSELDCX: mmio.Mmio(packed struct(u32) {
+                ///  Pin number
+                PIN: u5,
+                ///  Port number
+                PORT: u1,
+                reserved31: u25,
+                ///  Connection
+                CONNECT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disconnect
+                        Disconnected = 0x1,
+                        ///  Connect
+                        Connected = 0x0,
+                    },
+                },
+            }),
+            ///  DCX configuration
+            DCXCNT: mmio.Mmio(packed struct(u32) {
+                ///  This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes.
+                DCXCNT: u4,
+                padding: u28,
+            }),
+            reserved1472: [76]u8,
+            ///  Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT
+            ORC: mmio.Mmio(packed struct(u32) {
+                ///  Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT.
+                ORC: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  SPI Slave 0
+        pub const SPIS0 = extern struct {
+            reserved36: [36]u8,
+            ///  Acquire SPI semaphore
+            TASKS_ACQUIRE: mmio.Mmio(packed struct(u32) {
+                ///  Acquire SPI semaphore
+                TASKS_ACQUIRE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Release SPI semaphore, enabling the SPI slave to acquire it
+            TASKS_RELEASE: mmio.Mmio(packed struct(u32) {
+                ///  Release SPI semaphore, enabling the SPI slave to acquire it
+                TASKS_RELEASE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved260: [216]u8,
+            ///  Granted transaction completed
+            EVENTS_END: mmio.Mmio(packed struct(u32) {
+                ///  Granted transaction completed
+                EVENTS_END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved272: [8]u8,
+            ///  End of RXD buffer reached
+            EVENTS_ENDRX: mmio.Mmio(packed struct(u32) {
+                ///  End of RXD buffer reached
+                EVENTS_ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved296: [20]u8,
+            ///  Semaphore acquired
+            EVENTS_ACQUIRED: mmio.Mmio(packed struct(u32) {
+                ///  Semaphore acquired
+                EVENTS_ACQUIRED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [212]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Shortcut between event END and task ACQUIRE
+                END_ACQUIRE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to enable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u2,
+                ///  Write '1' to enable interrupt for event ENDRX
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u5,
+                ///  Write '1' to enable interrupt for event ACQUIRED
+                ACQUIRED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u21,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to disable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved4: u2,
+                ///  Write '1' to disable interrupt for event ENDRX
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u5,
+                ///  Write '1' to disable interrupt for event ACQUIRED
+                ACQUIRED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u21,
+            }),
+            reserved1024: [244]u8,
+            ///  Semaphore status register
+            SEMSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Semaphore status
+                SEMSTAT: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Semaphore is free
+                        Free = 0x0,
+                        ///  Semaphore is assigned to CPU
+                        CPU = 0x1,
+                        ///  Semaphore is assigned to SPI slave
+                        SPIS = 0x2,
+                        ///  Semaphore is assigned to SPI but a handover to the CPU is pending
+                        CPUPending = 0x3,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1088: [60]u8,
+            ///  Status from last transaction
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  TX buffer over-read detected, and prevented
+                OVERREAD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  RX buffer overflow detected, and prevented
+                OVERFLOW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1280: [188]u8,
+            ///  Enable SPI slave
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable SPI slave
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable SPI slave
+                        Disabled = 0x0,
+                        ///  Enable SPI slave
+                        Enabled = 0x2,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1364: [80]u8,
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Bit order
+                ORDER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Most significant bit shifted out first
+                        MsbFirst = 0x0,
+                        ///  Least significant bit shifted out first
+                        LsbFirst = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) phase
+                CPHA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Sample on leading edge of clock, shift serial data on trailing edge
+                        Leading = 0x0,
+                        ///  Sample on trailing edge of clock, shift serial data on leading edge
+                        Trailing = 0x1,
+                    },
+                },
+                ///  Serial clock (SCK) polarity
+                CPOL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Active high
+                        ActiveHigh = 0x0,
+                        ///  Active low
+                        ActiveLow = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1372: [4]u8,
+            ///  Default character. Character clocked out in case of an ignored transaction.
+            DEF: mmio.Mmio(packed struct(u32) {
+                ///  Default character. Character clocked out in case of an ignored transaction.
+                DEF: u8,
+                padding: u24,
+            }),
+            reserved1472: [96]u8,
+            ///  Over-read character
+            ORC: mmio.Mmio(packed struct(u32) {
+                ///  Over-read character. Character clocked out after an over-read of the transmit buffer.
+                ORC: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  I2C compatible Two-Wire Interface 0
+        pub const TWI0 = extern struct {
+            ///  Start TWI receive sequence
+            TASKS_STARTRX: mmio.Mmio(packed struct(u32) {
+                ///  Start TWI receive sequence
+                TASKS_STARTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved8: [4]u8,
+            ///  Start TWI transmit sequence
+            TASKS_STARTTX: mmio.Mmio(packed struct(u32) {
+                ///  Start TWI transmit sequence
+                TASKS_STARTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved20: [8]u8,
+            ///  Stop TWI transaction
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop TWI transaction
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved28: [4]u8,
+            ///  Suspend TWI transaction
+            TASKS_SUSPEND: mmio.Mmio(packed struct(u32) {
+                ///  Suspend TWI transaction
+                TASKS_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Resume TWI transaction
+            TASKS_RESUME: mmio.Mmio(packed struct(u32) {
+                ///  Resume TWI transaction
+                TASKS_RESUME: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved260: [224]u8,
+            ///  TWI stopped
+            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
+                ///  TWI stopped
+                EVENTS_STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  TWI RXD byte received
+            EVENTS_RXDREADY: mmio.Mmio(packed struct(u32) {
+                ///  TWI RXD byte received
+                EVENTS_RXDREADY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved284: [16]u8,
+            ///  TWI TXD byte sent
+            EVENTS_TXDSENT: mmio.Mmio(packed struct(u32) {
+                ///  TWI TXD byte sent
+                EVENTS_TXDSENT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved292: [4]u8,
+            ///  TWI error
+            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
+                ///  TWI error
+                EVENTS_ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved312: [16]u8,
+            ///  TWI byte boundary, generated before each byte that is sent or received
+            EVENTS_BB: mmio.Mmio(packed struct(u32) {
+                ///  TWI byte boundary, generated before each byte that is sent or received
+                EVENTS_BB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved328: [12]u8,
+            ///  TWI entered the suspended state
+            EVENTS_SUSPENDED: mmio.Mmio(packed struct(u32) {
+                ///  TWI entered the suspended state
+                EVENTS_SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [180]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between event BB and task SUSPEND
+                BB_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event BB and task STOP
+                BB_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to enable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event RXDREADY
+                RXDREADY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u4,
+                ///  Write '1' to enable interrupt for event TXDSENT
+                TXDSENT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u1,
+                ///  Write '1' to enable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved14: u4,
+                ///  Write '1' to enable interrupt for event BB
+                BB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u3,
+                ///  Write '1' to enable interrupt for event SUSPENDED
+                SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u13,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event RXDREADY
+                RXDREADY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved7: u4,
+                ///  Write '1' to disable interrupt for event TXDSENT
+                TXDSENT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u1,
+                ///  Write '1' to disable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved14: u4,
+                ///  Write '1' to disable interrupt for event BB
+                BB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u3,
+                ///  Write '1' to disable interrupt for event SUSPENDED
+                SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u13,
+            }),
+            reserved1220: [440]u8,
+            ///  Error source
+            ERRORSRC: mmio.Mmio(packed struct(u32) {
+                ///  Overrun error
+                OVERRUN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: no overrun occured
+                        NotPresent = 0x0,
+                        ///  Read: overrun occured
+                        Present = 0x1,
+                    },
+                },
+                ///  NACK received after sending the address (write '1' to clear)
+                ANACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                ///  NACK received after sending a data byte (write '1' to clear)
+                DNACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: error not present
+                        NotPresent = 0x0,
+                        ///  Read: error present
+                        Present = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1280: [56]u8,
+            ///  Enable TWI
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable TWI
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable TWI
+                        Disabled = 0x0,
+                        ///  Enable TWI
+                        Enabled = 0x5,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1304: [20]u8,
+            ///  RXD register
+            RXD: mmio.Mmio(packed struct(u32) {
+                ///  RXD register
+                RXD: u8,
+                padding: u24,
+            }),
+            ///  TXD register
+            TXD: mmio.Mmio(packed struct(u32) {
+                ///  TXD register
+                TXD: u8,
+                padding: u24,
+            }),
+            reserved1316: [4]u8,
+            ///  TWI frequency. Accuracy depends on the HFCLK source selected.
+            FREQUENCY: mmio.Mmio(packed struct(u32) {
+                ///  TWI master clock frequency
+                FREQUENCY: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  100 kbps
+                        K100 = 0x1980000,
+                        ///  250 kbps
+                        K250 = 0x4000000,
+                        ///  400 kbps (actual rate 410.256 kbps)
+                        K400 = 0x6680000,
+                        _,
+                    },
+                },
+            }),
+            reserved1416: [96]u8,
+            ///  Address used in the TWI transfer
+            ADDRESS: mmio.Mmio(packed struct(u32) {
+                ///  Address used in the TWI transfer
+                ADDRESS: u7,
+                padding: u25,
+            }),
+        };
+
+        ///  I2C compatible Two-Wire Master Interface with EasyDMA 0
+        pub const TWIM0 = extern struct {
+            ///  Start TWI receive sequence
+            TASKS_STARTRX: mmio.Mmio(packed struct(u32) {
+                ///  Start TWI receive sequence
+                TASKS_STARTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved8: [4]u8,
+            ///  Start TWI transmit sequence
+            TASKS_STARTTX: mmio.Mmio(packed struct(u32) {
+                ///  Start TWI transmit sequence
+                TASKS_STARTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved20: [8]u8,
+            ///  Stop TWI transaction. Must be issued while the TWI master is not suspended.
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop TWI transaction. Must be issued while the TWI master is not suspended.
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved28: [4]u8,
+            ///  Suspend TWI transaction
+            TASKS_SUSPEND: mmio.Mmio(packed struct(u32) {
+                ///  Suspend TWI transaction
+                TASKS_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Resume TWI transaction
+            TASKS_RESUME: mmio.Mmio(packed struct(u32) {
+                ///  Resume TWI transaction
+                TASKS_RESUME: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved260: [224]u8,
+            ///  TWI stopped
+            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
+                ///  TWI stopped
+                EVENTS_STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved292: [28]u8,
+            ///  TWI error
+            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
+                ///  TWI error
+                EVENTS_ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved328: [32]u8,
+            ///  Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
+            EVENTS_SUSPENDED: mmio.Mmio(packed struct(u32) {
+                ///  Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
+                EVENTS_SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Receive sequence started
+            EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) {
+                ///  Receive sequence started
+                EVENTS_RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Transmit sequence started
+            EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) {
+                ///  Transmit sequence started
+                EVENTS_TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved348: [8]u8,
+            ///  Byte boundary, starting to receive the last byte
+            EVENTS_LASTRX: mmio.Mmio(packed struct(u32) {
+                ///  Byte boundary, starting to receive the last byte
+                EVENTS_LASTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Byte boundary, starting to transmit the last byte
+            EVENTS_LASTTX: mmio.Mmio(packed struct(u32) {
+                ///  Byte boundary, starting to transmit the last byte
+                EVENTS_LASTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [156]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved7: u7,
+                ///  Shortcut between event LASTTX and task STARTRX
+                LASTTX_STARTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event LASTTX and task SUSPEND
+                LASTTX_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event LASTTX and task STOP
+                LASTTX_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event LASTRX and task STARTTX
+                LASTRX_STARTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event LASTRX and task SUSPEND
+                LASTRX_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event LASTRX and task STOP
+                LASTRX_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u19,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Enable or disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Enable or disable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u8,
+                ///  Enable or disable interrupt for event SUSPENDED
+                SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event RXSTARTED
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TXSTARTED
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved23: u2,
+                ///  Enable or disable interrupt for event LASTRX
+                LASTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event LASTTX
+                LASTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to enable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Write '1' to enable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u8,
+                ///  Write '1' to enable interrupt for event SUSPENDED
+                SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event RXSTARTED
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TXSTARTED
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved23: u2,
+                ///  Write '1' to enable interrupt for event LASTRX
+                LASTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event LASTTX
+                LASTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Write '1' to disable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u8,
+                ///  Write '1' to disable interrupt for event SUSPENDED
+                SUSPENDED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event RXSTARTED
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TXSTARTED
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved23: u2,
+                ///  Write '1' to disable interrupt for event LASTRX
+                LASTRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event LASTTX
+                LASTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            reserved1220: [440]u8,
+            ///  Error source
+            ERRORSRC: mmio.Mmio(packed struct(u32) {
+                ///  Overrun error
+                OVERRUN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotReceived = 0x0,
+                        ///  Error occurred
+                        Received = 0x1,
+                    },
+                },
+                ///  NACK received after sending the address (write '1' to clear)
+                ANACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotReceived = 0x0,
+                        ///  Error occurred
+                        Received = 0x1,
+                    },
+                },
+                ///  NACK received after sending a data byte (write '1' to clear)
+                DNACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotReceived = 0x0,
+                        ///  Error occurred
+                        Received = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1280: [56]u8,
+            ///  Enable TWIM
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable TWIM
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable TWIM
+                        Disabled = 0x0,
+                        ///  Enable TWIM
+                        Enabled = 0x6,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1316: [32]u8,
+            ///  TWI frequency. Accuracy depends on the HFCLK source selected.
+            FREQUENCY: mmio.Mmio(packed struct(u32) {
+                ///  TWI master clock frequency
+                FREQUENCY: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  100 kbps
+                        K100 = 0x1980000,
+                        ///  250 kbps
+                        K250 = 0x4000000,
+                        ///  400 kbps
+                        K400 = 0x6400000,
+                        _,
+                    },
+                },
+            }),
+            reserved1416: [96]u8,
+            ///  Address used in the TWI transfer
+            ADDRESS: mmio.Mmio(packed struct(u32) {
+                ///  Address used in the TWI transfer
+                ADDRESS: u7,
+                padding: u25,
+            }),
+        };
+
+        ///  I2C compatible Two-Wire Slave Interface with EasyDMA 0
+        pub const TWIS0 = extern struct {
+            reserved20: [20]u8,
+            ///  Stop TWI transaction
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop TWI transaction
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved28: [4]u8,
+            ///  Suspend TWI transaction
+            TASKS_SUSPEND: mmio.Mmio(packed struct(u32) {
+                ///  Suspend TWI transaction
+                TASKS_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Resume TWI transaction
+            TASKS_RESUME: mmio.Mmio(packed struct(u32) {
+                ///  Resume TWI transaction
+                TASKS_RESUME: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved48: [12]u8,
+            ///  Prepare the TWI slave to respond to a write command
+            TASKS_PREPARERX: mmio.Mmio(packed struct(u32) {
+                ///  Prepare the TWI slave to respond to a write command
+                TASKS_PREPARERX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Prepare the TWI slave to respond to a read command
+            TASKS_PREPARETX: mmio.Mmio(packed struct(u32) {
+                ///  Prepare the TWI slave to respond to a read command
+                TASKS_PREPARETX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved260: [204]u8,
+            ///  TWI stopped
+            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
+                ///  TWI stopped
+                EVENTS_STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved292: [28]u8,
+            ///  TWI error
+            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
+                ///  TWI error
+                EVENTS_ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved332: [36]u8,
+            ///  Receive sequence started
+            EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) {
+                ///  Receive sequence started
+                EVENTS_RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Transmit sequence started
+            EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) {
+                ///  Transmit sequence started
+                EVENTS_TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved356: [16]u8,
+            ///  Write command received
+            EVENTS_WRITE: mmio.Mmio(packed struct(u32) {
+                ///  Write command received
+                EVENTS_WRITE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Read command received
+            EVENTS_READ: mmio.Mmio(packed struct(u32) {
+                ///  Read command received
+                EVENTS_READ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [148]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                reserved13: u13,
+                ///  Shortcut between event WRITE and task SUSPEND
+                WRITE_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event READ and task SUSPEND
+                READ_SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u17,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Enable or disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Enable or disable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u9,
+                ///  Enable or disable interrupt for event RXSTARTED
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TXSTARTED
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved25: u4,
+                ///  Enable or disable interrupt for event WRITE
+                WRITE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event READ
+                READ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u5,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to enable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Write '1' to enable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u9,
+                ///  Write '1' to enable interrupt for event RXSTARTED
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TXSTARTED
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved25: u4,
+                ///  Write '1' to enable interrupt for event WRITE
+                WRITE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event READ
+                READ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u5,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved9: u7,
+                ///  Write '1' to disable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved19: u9,
+                ///  Write '1' to disable interrupt for event RXSTARTED
+                RXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TXSTARTED
+                TXSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved25: u4,
+                ///  Write '1' to disable interrupt for event WRITE
+                WRITE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event READ
+                READ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u5,
+            }),
+            reserved1232: [452]u8,
+            ///  Error source
+            ERRORSRC: mmio.Mmio(packed struct(u32) {
+                ///  RX buffer overflow detected, and prevented
+                OVERFLOW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotDetected = 0x0,
+                        ///  Error occurred
+                        Detected = 0x1,
+                    },
+                },
+                reserved2: u1,
+                ///  NACK sent after receiving a data byte
+                DNACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotReceived = 0x0,
+                        ///  Error occurred
+                        Received = 0x1,
+                    },
+                },
+                ///  TX buffer over-read detected, and prevented
+                OVERREAD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Error did not occur
+                        NotDetected = 0x0,
+                        ///  Error occurred
+                        Detected = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Status register indicating which address had a match
+            MATCH: mmio.Mmio(packed struct(u32) {
+                ///  Which of the addresses in {ADDRESS} matched the incoming address
+                MATCH: u1,
+                padding: u31,
+            }),
+            reserved1280: [40]u8,
+            ///  Enable TWIS
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable TWIS
+                ENABLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Disable TWIS
+                        Disabled = 0x0,
+                        ///  Enable TWIS
+                        Enabled = 0x9,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1416: [132]u8,
+            ///  Description collection: TWI slave address n
+            ADDRESS: [2]mmio.Mmio(packed struct(u32) {
+                ///  TWI slave address
+                ADDRESS: u7,
+                padding: u25,
+            }),
+            reserved1428: [4]u8,
+            ///  Configuration register for the address match mechanism
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable address matching on ADDRESS[0]
+                ADDRESS0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable address matching on ADDRESS[1]
+                ADDRESS1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1472: [40]u8,
+            ///  Over-read character. Character sent out in case of an over-read of the transmit buffer.
+            ORC: mmio.Mmio(packed struct(u32) {
+                ///  Over-read character. Character sent out in case of an over-read of the transmit buffer.
+                ORC: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  Pulse Density Modulation (Digital Microphone) Interface
+        pub const PDM = extern struct {
+            ///  Starts continuous PDM transfer
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Starts continuous PDM transfer
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stops PDM transfer
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stops PDM transfer
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [248]u8,
+            ///  PDM transfer has started
+            EVENTS_STARTED: mmio.Mmio(packed struct(u32) {
+                ///  PDM transfer has started
+                EVENTS_STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  PDM transfer has finished
+            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
+                ///  PDM transfer has finished
+                EVENTS_STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM
+            EVENTS_END: mmio.Mmio(packed struct(u32) {
+                ///  The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM
+                EVENTS_END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved768: [500]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1280: [500]u8,
+            ///  PDM module enable register
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable PDM module
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  PDM clock generator control
+            PDMCLKCTRL: mmio.Mmio(packed struct(u32) {
+                ///  PDM_CLK frequency
+                FREQ: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  PDM_CLK = 32 MHz / 32 = 1.000 MHz
+                        @"1000K" = 0x8000000,
+                        ///  PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64.
+                        Default = 0x8400000,
+                        ///  PDM_CLK = 32 MHz / 30 = 1.067 MHz
+                        @"1067K" = 0x8800000,
+                        ///  PDM_CLK = 32 MHz / 26 = 1.231 MHz
+                        @"1231K" = 0x9800000,
+                        ///  PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80.
+                        @"1280K" = 0xa000000,
+                        ///  PDM_CLK = 32 MHz / 24 = 1.333 MHz
+                        @"1333K" = 0xa800000,
+                        _,
+                    },
+                },
+            }),
+            ///  Defines the routing of the connected PDM microphones' signals
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Mono or stereo operation
+                OPERATION: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]
+                        Stereo = 0x0,
+                        ///  Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]
+                        Mono = 0x1,
+                    },
+                },
+                ///  Defines on which PDM_CLK edge Left (or mono) is sampled
+                EDGE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Left (or mono) is sampled on falling edge of PDM_CLK
+                        LeftFalling = 0x0,
+                        ///  Left (or mono) is sampled on rising edge of PDM_CLK
+                        LeftRising = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1304: [12]u8,
+            ///  Left output gain adjustment
+            GAINL: mmio.Mmio(packed struct(u32) {
+                ///  Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust
+                GAINL: packed union {
+                    raw: u7,
+                    value: enum(u7) {
+                        ///  -20dB gain adjustment (minimum)
+                        MinGain = 0x0,
+                        ///  0dB gain adjustment
+                        DefaultGain = 0x28,
+                        ///  +20dB gain adjustment (maximum)
+                        MaxGain = 0x50,
+                        _,
+                    },
+                },
+                padding: u25,
+            }),
+            ///  Right output gain adjustment
+            GAINR: mmio.Mmio(packed struct(u32) {
+                ///  Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)
+                GAINR: packed union {
+                    raw: u7,
+                    value: enum(u7) {
+                        ///  -20dB gain adjustment (minimum)
+                        MinGain = 0x0,
+                        ///  0dB gain adjustment
+                        DefaultGain = 0x28,
+                        ///  +20dB gain adjustment (maximum)
+                        MaxGain = 0x50,
+                        _,
+                    },
+                },
+                padding: u25,
+            }),
+            ///  Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly.
+            RATIO: mmio.Mmio(packed struct(u32) {
+                ///  Selects the ratio between PDM_CLK and output sample rate
+                RATIO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Ratio of 64
+                        Ratio64 = 0x0,
+                        ///  Ratio of 80
+                        Ratio80 = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  ARM TrustZone CryptoCell register interface
+        pub const CRYPTOCELL = extern struct {
+            reserved1280: [1280]u8,
+            ///  Enable CRYPTOCELL subsystem
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable the CRYPTOCELL subsystem
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  CRYPTOCELL subsystem disabled
+                        Disabled = 0x0,
+                        ///  CRYPTOCELL subsystem enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  CRYPTOCELL HOST_RGF interface
+        pub const CC_HOST_RGF = extern struct {
+            reserved6712: [6712]u8,
+            ///  AES hardware key select
+            HOST_CRYPTOKEY_SEL: mmio.Mmio(packed struct(u32) {
+                ///  Select the source of the HW key that is used by the AES engine
+                HOST_CRYPTOKEY_SEL: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Use device root key K_DR from CRYPTOCELL AO power domain
+                        K_DR = 0x0,
+                        ///  Use hard-coded RTL key K_PRTL
+                        K_PRTL = 0x1,
+                        ///  Use provided session key
+                        Session = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved6732: [16]u8,
+            ///  This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.
+            HOST_IOT_KPRTL_LOCK: mmio.Mmio(packed struct(u32) {
+                ///  This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.
+                HOST_IOT_KPRTL_LOCK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL
+                        Disabled = 0x0,
+                        ///  K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead.
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained.
+            HOST_IOT_KDR0: mmio.Mmio(packed struct(u32) {
+                ///  Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain
+                HOST_IOT_KDR0: u32,
+            }),
+            ///  This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.
+            HOST_IOT_KDR1: mmio.Mmio(packed struct(u32) {
+                ///  K_DR bits 63:32
+                HOST_IOT_KDR1: u32,
+            }),
+            ///  This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.
+            HOST_IOT_KDR2: mmio.Mmio(packed struct(u32) {
+                ///  K_DR bits 95:64
+                HOST_IOT_KDR2: u32,
+            }),
+            ///  This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.
+            HOST_IOT_KDR3: mmio.Mmio(packed struct(u32) {
+                ///  K_DR bits 127:96
+                HOST_IOT_KDR3: u32,
+            }),
+            ///  Controls lifecycle state (LCS) for CRYPTOCELL subsystem
+            HOST_IOT_LCS: mmio.Mmio(packed struct(u32) {
+                ///  Lifecycle state value. This field is write-once per reset.
+                LCS: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  CC310 operates in debug mode
+                        Debug = 0x0,
+                        ///  CC310 operates in secure mode
+                        Secure = 0x2,
+                        _,
+                    },
+                },
+                reserved8: u5,
+                ///  This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset
+                LCS_IS_VALID: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  A valid LCS is not yet retained in the CRYPTOCELL AO power domain
+                        Invalid = 0x0,
+                        ///  A valid LCS is successfully retained in the CRYPTOCELL AO power domain
+                        Valid = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+        };
+
+        ///  External flash interface
+        pub const QSPI = extern struct {
+            ///  Activate QSPI interface
+            TASKS_ACTIVATE: mmio.Mmio(packed struct(u32) {
+                ///  Activate QSPI interface
+                TASKS_ACTIVATE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start transfer from external flash memory to internal RAM
+            TASKS_READSTART: mmio.Mmio(packed struct(u32) {
+                ///  Start transfer from external flash memory to internal RAM
+                TASKS_READSTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start transfer from internal RAM to external flash memory
+            TASKS_WRITESTART: mmio.Mmio(packed struct(u32) {
+                ///  Start transfer from internal RAM to external flash memory
+                TASKS_WRITESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start external flash memory erase operation
+            TASKS_ERASESTART: mmio.Mmio(packed struct(u32) {
+                ///  Start external flash memory erase operation
+                TASKS_ERASESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Deactivate QSPI interface
+            TASKS_DEACTIVATE: mmio.Mmio(packed struct(u32) {
+                ///  Deactivate QSPI interface
+                TASKS_DEACTIVATE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [236]u8,
+            ///  QSPI peripheral is ready. This event will be generated as a response to any QSPI task.
+            EVENTS_READY: mmio.Mmio(packed struct(u32) {
+                ///  QSPI peripheral is ready. This event will be generated as a response to any QSPI task.
+                EVENTS_READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved768: [508]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1280: [500]u8,
+            ///  Enable QSPI peripheral and acquire the pins selected in PSELn registers
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable QSPI
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable QSPI
+                        Disabled = 0x0,
+                        ///  Enable QSPI
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1344: [60]u8,
+            ///  Address offset into the external memory for Execute in Place operation.
+            XIPOFFSET: mmio.Mmio(packed struct(u32) {
+                ///  Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4.
+                XIPOFFSET: u32,
+            }),
+            ///  Interface configuration.
+            IFCONFIG0: mmio.Mmio(packed struct(u32) {
+                ///  Configure number of data lines and opcode used for reading.
+                READOC: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Single data line SPI. FAST_READ (opcode 0x0B).
+                        FASTREAD = 0x0,
+                        ///  Dual data line SPI. READ2O (opcode 0x3B).
+                        READ2O = 0x1,
+                        ///  Dual data line SPI. READ2IO (opcode 0xBB).
+                        READ2IO = 0x2,
+                        ///  Quad data line SPI. READ4O (opcode 0x6B).
+                        READ4O = 0x3,
+                        ///  Quad data line SPI. READ4IO (opcode 0xEB).
+                        READ4IO = 0x4,
+                        _,
+                    },
+                },
+                ///  Configure number of data lines and opcode used for writing.
+                WRITEOC: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Single data line SPI. PP (opcode 0x02).
+                        PP = 0x0,
+                        ///  Dual data line SPI. PP2O (opcode 0xA2).
+                        PP2O = 0x1,
+                        ///  Quad data line SPI. PP4O (opcode 0x32).
+                        PP4O = 0x2,
+                        ///  Quad data line SPI. PP4IO (opcode 0x38).
+                        PP4IO = 0x3,
+                        _,
+                    },
+                },
+                ///  Addressing mode.
+                ADDRMODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  24-bit addressing.
+                        @"24BIT" = 0x0,
+                        ///  32-bit addressing.
+                        @"32BIT" = 0x1,
+                    },
+                },
+                ///  Enable deep power-down mode (DPM) feature.
+                DPMENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable DPM feature.
+                        Disable = 0x0,
+                        ///  Enable DPM feature.
+                        Enable = 0x1,
+                    },
+                },
+                reserved12: u4,
+                ///  Page size for commands PP, PP2O, PP4O and PP4IO.
+                PPSIZE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  256 bytes.
+                        @"256Bytes" = 0x0,
+                        ///  512 bytes.
+                        @"512Bytes" = 0x1,
+                    },
+                },
+                padding: u19,
+            }),
+            reserved1536: [184]u8,
+            ///  Interface configuration.
+            IFCONFIG1: mmio.Mmio(packed struct(u32) {
+                ///  Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns).
+                SCKDELAY: u8,
+                reserved24: u16,
+                ///  Enter/exit deep power-down mode (DPM) for external flash memory.
+                DPMEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exit DPM.
+                        Exit = 0x0,
+                        ///  Enter DPM.
+                        Enter = 0x1,
+                    },
+                },
+                ///  Select SPI mode.
+                SPIMODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0).
+                        MODE0 = 0x0,
+                        ///  Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1).
+                        MODE3 = 0x1,
+                    },
+                },
+                reserved28: u2,
+                ///  SCK frequency is given as 32 MHz / (SCKFREQ + 1).
+                SCKFREQ: u4,
+            }),
+            ///  Status register.
+            STATUS: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Deep power-down mode (DPM) status of external flash.
+                DPM: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  External flash is not in DPM.
+                        Disabled = 0x0,
+                        ///  External flash is in DPM.
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Ready status.
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM.
+                        READY = 0x1,
+                        ///  QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM.
+                        BUSY = 0x0,
+                    },
+                },
+                reserved24: u20,
+                ///  Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte.
+                SREG: u8,
+            }),
+            reserved1556: [12]u8,
+            ///  Set the duration required to enter/exit deep power-down mode (DPM).
+            DPMDUR: mmio.Mmio(packed struct(u32) {
+                ///  Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns.
+                ENTER: u16,
+                ///  Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns.
+                EXIT: u16,
+            }),
+            reserved1572: [12]u8,
+            ///  Extended address configuration.
+            ADDRCONF: mmio.Mmio(packed struct(u32) {
+                ///  Opcode that enters the 32-bit addressing mode.
+                OPCODE: u8,
+                ///  Byte 0 following opcode.
+                BYTE0: u8,
+                ///  Byte 1 following byte 0.
+                BYTE1: u8,
+                ///  Extended addressing mode.
+                MODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Do not send any instruction.
+                        NoInstr = 0x0,
+                        ///  Send opcode.
+                        Opcode = 0x1,
+                        ///  Send opcode, byte0.
+                        OpByte0 = 0x2,
+                        ///  Send opcode, byte0, byte1.
+                        All = 0x3,
+                    },
+                },
+                ///  Wait for write complete before sending command.
+                WIPWAIT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No wait.
+                        Disable = 0x0,
+                        ///  Wait.
+                        Enable = 0x1,
+                    },
+                },
+                ///  Send WREN (write enable opcode 0x06) before instruction.
+                WREN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Do not send WREN.
+                        Disable = 0x0,
+                        ///  Send WREN.
+                        Enable = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            reserved1588: [12]u8,
+            ///  Custom instruction configuration register.
+            CINSTRCONF: mmio.Mmio(packed struct(u32) {
+                ///  Opcode of Custom instruction.
+                OPCODE: u8,
+                ///  Length of custom instruction in number of bytes.
+                LENGTH: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Send opcode only.
+                        @"1B" = 0x1,
+                        ///  Send opcode, CINSTRDAT0.BYTE0.
+                        @"2B" = 0x2,
+                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1.
+                        @"3B" = 0x3,
+                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2.
+                        @"4B" = 0x4,
+                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3.
+                        @"5B" = 0x5,
+                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4.
+                        @"6B" = 0x6,
+                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5.
+                        @"7B" = 0x7,
+                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6.
+                        @"8B" = 0x8,
+                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7.
+                        @"9B" = 0x9,
+                        _,
+                    },
+                },
+                ///  Level of the IO2 pin (if connected) during transmission of custom instruction.
+                LIO2: u1,
+                ///  Level of the IO3 pin (if connected) during transmission of custom instruction.
+                LIO3: u1,
+                ///  Wait for write complete before sending command.
+                WIPWAIT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No wait.
+                        Disable = 0x0,
+                        ///  Wait.
+                        Enable = 0x1,
+                    },
+                },
+                ///  Send WREN (write enable opcode 0x06) before instruction.
+                WREN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Do not send WREN.
+                        Disable = 0x0,
+                        ///  Send WREN.
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field.
+                LFEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Long frame mode disabled
+                        Disable = 0x0,
+                        ///  Long frame mode enabled
+                        Enable = 0x1,
+                    },
+                },
+                ///  Stop (finalize) long frame transaction
+                LFSTOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Stop
+                        Stop = 0x1,
+                        _,
+                    },
+                },
+                padding: u14,
+            }),
+            ///  Custom instruction data register 0.
+            CINSTRDAT0: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 0
+                BYTE0: u8,
+                ///  Data byte 1
+                BYTE1: u8,
+                ///  Data byte 2
+                BYTE2: u8,
+                ///  Data byte 3
+                BYTE3: u8,
+            }),
+            ///  Custom instruction data register 1.
+            CINSTRDAT1: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 4
+                BYTE4: u8,
+                ///  Data byte 5
+                BYTE5: u8,
+                ///  Data byte 6
+                BYTE6: u8,
+                ///  Data byte 7
+                BYTE7: u8,
+            }),
+            ///  SPI interface timing.
+            IFTIMING: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK.
+                RXDELAY: u3,
+                padding: u21,
+            }),
+        };
+
+        ///  Pulse width modulation unit 0
+        pub const PWM0 = extern struct {
+            reserved4: [4]u8,
+            ///  Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.
+            TASKS_SEQSTART: [2]mmio.Mmio(packed struct(u32) {
+                ///  Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.
+                TASKS_SEQSTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.
+            TASKS_NEXTSTEP: mmio.Mmio(packed struct(u32) {
+                ///  Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.
+                TASKS_NEXTSTEP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved260: [240]u8,
+            ///  Response to STOP task, emitted when PWM pulses are no longer generated
+            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
+                ///  Response to STOP task, emitted when PWM pulses are no longer generated
+                EVENTS_STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Description collection: First PWM period started on sequence n
+            EVENTS_SEQSTARTED: [2]mmio.Mmio(packed struct(u32) {
+                ///  First PWM period started on sequence n
+                EVENTS_SEQSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter
+            EVENTS_SEQEND: [2]mmio.Mmio(packed struct(u32) {
+                ///  Emitted at end of every sequence n, when last value from RAM has been applied to wave counter
+                EVENTS_SEQEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Emitted at the end of each PWM period
+            EVENTS_PWMPERIODEND: mmio.Mmio(packed struct(u32) {
+                ///  Emitted at the end of each PWM period
+                EVENTS_PWMPERIODEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Concatenated sequences have been played the amount of times defined in LOOP.CNT
+            EVENTS_LOOPSDONE: mmio.Mmio(packed struct(u32) {
+                ///  Concatenated sequences have been played the amount of times defined in LOOP.CNT
+                EVENTS_LOOPSDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [224]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between event SEQEND[0] and task STOP
+                SEQEND0_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event SEQEND[1] and task STOP
+                SEQEND1_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event LOOPSDONE and task SEQSTART[0]
+                LOOPSDONE_SEQSTART0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event LOOPSDONE and task SEQSTART[1]
+                LOOPSDONE_SEQSTART1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event LOOPSDONE and task STOP
+                LOOPSDONE_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Enable or disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event SEQSTARTED[0]
+                SEQSTARTED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event SEQSTARTED[1]
+                SEQSTARTED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event SEQEND[0]
+                SEQEND0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event SEQEND[1]
+                SEQEND1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event PWMPERIODEND
+                PWMPERIODEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event LOOPSDONE
+                LOOPSDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to enable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event SEQSTARTED[0]
+                SEQSTARTED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event SEQSTARTED[1]
+                SEQSTARTED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event SEQEND[0]
+                SEQEND0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event SEQEND[1]
+                SEQEND1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event PWMPERIODEND
+                PWMPERIODEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event LOOPSDONE
+                LOOPSDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event SEQSTARTED[0]
+                SEQSTARTED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event SEQSTARTED[1]
+                SEQSTARTED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event SEQEND[0]
+                SEQEND0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event SEQEND[1]
+                SEQEND1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event PWMPERIODEND
+                PWMPERIODEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event LOOPSDONE
+                LOOPSDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            reserved1280: [500]u8,
+            ///  PWM module enable register
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable PWM module
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Selects operating mode of the wave counter
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Selects up mode or up-and-down mode for the counter
+                UPDOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Up counter, edge-aligned PWM duty cycle
+                        Up = 0x0,
+                        ///  Up and down counter, center-aligned PWM duty cycle
+                        UpAndDown = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Value up to which the pulse generator counter counts
+            COUNTERTOP: mmio.Mmio(packed struct(u32) {
+                ///  Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used.
+                COUNTERTOP: u15,
+                padding: u17,
+            }),
+            ///  Configuration for PWM_CLK
+            PRESCALER: mmio.Mmio(packed struct(u32) {
+                ///  Prescaler of PWM_CLK
+                PRESCALER: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Divide by 1 (16 MHz)
+                        DIV_1 = 0x0,
+                        ///  Divide by 2 (8 MHz)
+                        DIV_2 = 0x1,
+                        ///  Divide by 4 (4 MHz)
+                        DIV_4 = 0x2,
+                        ///  Divide by 8 (2 MHz)
+                        DIV_8 = 0x3,
+                        ///  Divide by 16 (1 MHz)
+                        DIV_16 = 0x4,
+                        ///  Divide by 32 (500 kHz)
+                        DIV_32 = 0x5,
+                        ///  Divide by 64 (250 kHz)
+                        DIV_64 = 0x6,
+                        ///  Divide by 128 (125 kHz)
+                        DIV_128 = 0x7,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Configuration of the decoder
+            DECODER: mmio.Mmio(packed struct(u32) {
+                ///  How a sequence is read from RAM and spread to the compare register
+                LOAD: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  1st half word (16-bit) used in all PWM channels 0..3
+                        Common = 0x0,
+                        ///  1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3
+                        Grouped = 0x1,
+                        ///  1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3
+                        Individual = 0x2,
+                        ///  1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP
+                        WaveForm = 0x3,
+                    },
+                },
+                reserved8: u6,
+                ///  Selects source for advancing the active sequence
+                MODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  SEQ[n].REFRESH is used to determine loading internal compare registers
+                        RefreshCount = 0x0,
+                        ///  NEXTSTEP task causes a new value to be loaded to internal compare registers
+                        NextStep = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            ///  Number of playbacks of a loop
+            LOOP: mmio.Mmio(packed struct(u32) {
+                ///  Number of playbacks of pattern cycles
+                CNT: packed union {
+                    raw: u16,
+                    value: enum(u16) {
+                        ///  Looping disabled (stop at the end of the sequence)
+                        Disabled = 0x0,
+                        _,
+                    },
+                },
+                padding: u16,
+            }),
+        };
+
+        ///  Universal serial bus device
+        pub const USBD = extern struct {
+            reserved4: [4]u8,
+            ///  Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host
+            TASKS_STARTEPIN: [8]mmio.Mmio(packed struct(u32) {
+                ///  Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host
+                TASKS_STARTEPIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint
+            TASKS_STARTISOIN: mmio.Mmio(packed struct(u32) {
+                ///  Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint
+                TASKS_STARTISOIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host
+            TASKS_STARTEPOUT: [8]mmio.Mmio(packed struct(u32) {
+                ///  Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host
+                TASKS_STARTEPOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint
+            TASKS_STARTISOOUT: mmio.Mmio(packed struct(u32) {
+                ///  Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint
+                TASKS_STARTISOOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Allows OUT data stage on control endpoint 0
+            TASKS_EP0RCVOUT: mmio.Mmio(packed struct(u32) {
+                ///  Allows OUT data stage on control endpoint 0
+                TASKS_EP0RCVOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Allows status stage on control endpoint 0
+            TASKS_EP0STATUS: mmio.Mmio(packed struct(u32) {
+                ///  Allows status stage on control endpoint 0
+                TASKS_EP0STATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stalls data and status stage on control endpoint 0
+            TASKS_EP0STALL: mmio.Mmio(packed struct(u32) {
+                ///  Stalls data and status stage on control endpoint 0
+                TASKS_EP0STALL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Forces D+ and D- lines into the state defined in the DPDMVALUE register
+            TASKS_DPDMDRIVE: mmio.Mmio(packed struct(u32) {
+                ///  Forces D+ and D- lines into the state defined in the DPDMVALUE register
+                TASKS_DPDMDRIVE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stops forcing D+ and D- lines into any state (USB engine takes control)
+            TASKS_DPDMNODRIVE: mmio.Mmio(packed struct(u32) {
+                ///  Stops forcing D+ and D- lines into any state (USB engine takes control)
+                TASKS_DPDMNODRIVE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [160]u8,
+            ///  Signals that a USB reset condition has been detected on USB lines
+            EVENTS_USBRESET: mmio.Mmio(packed struct(u32) {
+                ///  Signals that a USB reset condition has been detected on USB lines
+                EVENTS_USBRESET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register
+            EVENTS_STARTED: mmio.Mmio(packed struct(u32) {
+                ///  Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register
+                EVENTS_STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
+            EVENTS_ENDEPIN: [8]mmio.Mmio(packed struct(u32) {
+                ///  The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
+                EVENTS_ENDEPIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  An acknowledged data transfer has taken place on the control endpoint
+            EVENTS_EP0DATADONE: mmio.Mmio(packed struct(u32) {
+                ///  An acknowledged data transfer has taken place on the control endpoint
+                EVENTS_EP0DATADONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software.
+            EVENTS_ENDISOIN: mmio.Mmio(packed struct(u32) {
+                ///  The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software.
+                EVENTS_ENDISOIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
+            EVENTS_ENDEPOUT: [8]mmio.Mmio(packed struct(u32) {
+                ///  The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
+                EVENTS_ENDEPOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software.
+            EVENTS_ENDISOOUT: mmio.Mmio(packed struct(u32) {
+                ///  The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software.
+                EVENTS_ENDISOOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Signals that a SOF (start of frame) condition has been detected on USB lines
+            EVENTS_SOF: mmio.Mmio(packed struct(u32) {
+                ///  Signals that a SOF (start of frame) condition has been detected on USB lines
+                EVENTS_SOF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause.
+            EVENTS_USBEVENT: mmio.Mmio(packed struct(u32) {
+                ///  An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause.
+                EVENTS_USBEVENT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  A valid SETUP token has been received (and acknowledged) on the control endpoint
+            EVENTS_EP0SETUP: mmio.Mmio(packed struct(u32) {
+                ///  A valid SETUP token has been received (and acknowledged) on the control endpoint
+                EVENTS_EP0SETUP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register
+            EVENTS_EPDATA: mmio.Mmio(packed struct(u32) {
+                ///  A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register
+                EVENTS_EPDATA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [156]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between event EP0DATADONE and task STARTEPIN[0]
+                EP0DATADONE_STARTEPIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event EP0DATADONE and task STARTEPOUT[0]
+                EP0DATADONE_STARTEPOUT0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event EP0DATADONE and task EP0STATUS
+                EP0DATADONE_EP0STATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event ENDEPOUT[0] and task EP0STATUS
+                ENDEPOUT0_EP0STATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event ENDEPOUT[0] and task EP0RCVOUT
+                ENDEPOUT0_EP0RCVOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for event USBRESET
+                USBRESET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPIN[0]
+                ENDEPIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPIN[1]
+                ENDEPIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPIN[2]
+                ENDEPIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPIN[3]
+                ENDEPIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPIN[4]
+                ENDEPIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPIN[5]
+                ENDEPIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPIN[6]
+                ENDEPIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPIN[7]
+                ENDEPIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event EP0DATADONE
+                EP0DATADONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDISOIN
+                ENDISOIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPOUT[0]
+                ENDEPOUT0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPOUT[1]
+                ENDEPOUT1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPOUT[2]
+                ENDEPOUT2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPOUT[3]
+                ENDEPOUT3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPOUT[4]
+                ENDEPOUT4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPOUT[5]
+                ENDEPOUT5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPOUT[6]
+                ENDEPOUT6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDEPOUT[7]
+                ENDEPOUT7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDISOOUT
+                ENDISOOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event SOF
+                SOF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event USBEVENT
+                USBEVENT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event EP0SETUP
+                EP0SETUP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event EPDATA
+                EPDATA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event USBRESET
+                USBRESET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPIN[0]
+                ENDEPIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPIN[1]
+                ENDEPIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPIN[2]
+                ENDEPIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPIN[3]
+                ENDEPIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPIN[4]
+                ENDEPIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPIN[5]
+                ENDEPIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPIN[6]
+                ENDEPIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPIN[7]
+                ENDEPIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event EP0DATADONE
+                EP0DATADONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDISOIN
+                ENDISOIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPOUT[0]
+                ENDEPOUT0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPOUT[1]
+                ENDEPOUT1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPOUT[2]
+                ENDEPOUT2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPOUT[3]
+                ENDEPOUT3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPOUT[4]
+                ENDEPOUT4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPOUT[5]
+                ENDEPOUT5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPOUT[6]
+                ENDEPOUT6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDEPOUT[7]
+                ENDEPOUT7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDISOOUT
+                ENDISOOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event SOF
+                SOF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event USBEVENT
+                USBEVENT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event EP0SETUP
+                EP0SETUP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event EPDATA
+                EPDATA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event USBRESET
+                USBRESET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPIN[0]
+                ENDEPIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPIN[1]
+                ENDEPIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPIN[2]
+                ENDEPIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPIN[3]
+                ENDEPIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPIN[4]
+                ENDEPIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPIN[5]
+                ENDEPIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPIN[6]
+                ENDEPIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPIN[7]
+                ENDEPIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event EP0DATADONE
+                EP0DATADONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDISOIN
+                ENDISOIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPOUT[0]
+                ENDEPOUT0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPOUT[1]
+                ENDEPOUT1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPOUT[2]
+                ENDEPOUT2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPOUT[3]
+                ENDEPOUT3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPOUT[4]
+                ENDEPOUT4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPOUT[5]
+                ENDEPOUT5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPOUT[6]
+                ENDEPOUT6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDEPOUT[7]
+                ENDEPOUT7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDISOOUT
+                ENDISOOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event SOF
+                SOF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event USBEVENT
+                USBEVENT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event EP0SETUP
+                EP0SETUP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event EPDATA
+                EPDATA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            reserved1024: [244]u8,
+            ///  Details on what caused the USBEVENT event
+            EVENTCAUSE: mmio.Mmio(packed struct(u32) {
+                ///  CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear.
+                ISOOUTCRC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No error detected
+                        NotDetected = 0x0,
+                        ///  Error detected
+                        Detected = 0x1,
+                    },
+                },
+                reserved8: u7,
+                ///  Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear.
+                SUSPEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Suspend not detected
+                        NotDetected = 0x0,
+                        ///  Suspend detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear.
+                RESUME: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Resume not detected
+                        NotDetected = 0x0,
+                        ///  Resume detected
+                        Detected = 0x1,
+                    },
+                },
+                ///  USB MAC has been woken up and operational. Write '1' to clear.
+                USBWUALLOWED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Wake up not allowed
+                        NotAllowed = 0x0,
+                        ///  Wake up allowed
+                        Allowed = 0x1,
+                    },
+                },
+                ///  USB device is ready for normal operation. Write '1' to clear.
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  USBEVENT was not issued due to USBD peripheral ready
+                        NotDetected = 0x0,
+                        ///  USBD peripheral is ready
+                        Ready = 0x1,
+                    },
+                },
+                padding: u20,
+            }),
+            reserved1128: [100]u8,
+            ///  Provides information on which endpoint's EasyDMA registers have been captured
+            EPSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPIN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPIN8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                reserved16: u7,
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPOUT0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPOUT1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPOUT2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPOUT3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPOUT4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPOUT5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPOUT6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPOUT7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
+                EPOUT8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  EasyDMA registers have not been captured for this endpoint
+                        NoData = 0x0,
+                        ///  EasyDMA registers have been captured for this endpoint
+                        DataDone = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            ///  Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event)
+            EPDATASTATUS: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+                EPIN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotDone = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+                EPIN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotDone = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+                EPIN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotDone = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+                EPIN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotDone = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+                EPIN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotDone = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+                EPIN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotDone = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        DataDone = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
+                EPIN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotDone = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        DataDone = 0x1,
+                    },
+                },
+                reserved17: u9,
+                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+                EPOUT1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotStarted = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        Started = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+                EPOUT2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotStarted = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        Started = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+                EPOUT3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotStarted = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        Started = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+                EPOUT4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotStarted = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        Started = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+                EPOUT5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotStarted = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        Started = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+                EPOUT6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotStarted = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        Started = 0x1,
+                    },
+                },
+                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
+                EPOUT7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No acknowledged data transfer on this endpoint
+                        NotStarted = 0x0,
+                        ///  Acknowledged data transfer on this endpoint has occurred
+                        Started = 0x1,
+                    },
+                },
+                padding: u8,
+            }),
+            ///  Device USB address
+            USBADDR: mmio.Mmio(packed struct(u32) {
+                ///  Device USB address
+                ADDR: u7,
+                padding: u25,
+            }),
+            reserved1152: [12]u8,
+            ///  SETUP data, byte 0, bmRequestType
+            BMREQUESTTYPE: mmio.Mmio(packed struct(u32) {
+                ///  Data transfer type
+                RECIPIENT: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        ///  Device
+                        Device = 0x0,
+                        ///  Interface
+                        Interface = 0x1,
+                        ///  Endpoint
+                        Endpoint = 0x2,
+                        ///  Other
+                        Other = 0x3,
+                        _,
+                    },
+                },
+                ///  Data transfer type
+                TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Standard
+                        Standard = 0x0,
+                        ///  Class
+                        Class = 0x1,
+                        ///  Vendor
+                        Vendor = 0x2,
+                        _,
+                    },
+                },
+                ///  Data transfer direction
+                DIRECTION: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Host-to-device
+                        HostToDevice = 0x0,
+                        ///  Device-to-host
+                        DeviceToHost = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  SETUP data, byte 1, bRequest
+            BREQUEST: mmio.Mmio(packed struct(u32) {
+                ///  SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values.
+                BREQUEST: packed union {
+                    raw: u8,
+                    value: enum(u8) {
+                        ///  Standard request GET_STATUS
+                        STD_GET_STATUS = 0x0,
+                        ///  Standard request CLEAR_FEATURE
+                        STD_CLEAR_FEATURE = 0x1,
+                        ///  Standard request SET_FEATURE
+                        STD_SET_FEATURE = 0x3,
+                        ///  Standard request SET_ADDRESS
+                        STD_SET_ADDRESS = 0x5,
+                        ///  Standard request GET_DESCRIPTOR
+                        STD_GET_DESCRIPTOR = 0x6,
+                        ///  Standard request SET_DESCRIPTOR
+                        STD_SET_DESCRIPTOR = 0x7,
+                        ///  Standard request GET_CONFIGURATION
+                        STD_GET_CONFIGURATION = 0x8,
+                        ///  Standard request SET_CONFIGURATION
+                        STD_SET_CONFIGURATION = 0x9,
+                        ///  Standard request GET_INTERFACE
+                        STD_GET_INTERFACE = 0xa,
+                        ///  Standard request SET_INTERFACE
+                        STD_SET_INTERFACE = 0xb,
+                        ///  Standard request SYNCH_FRAME
+                        STD_SYNCH_FRAME = 0xc,
+                        _,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  SETUP data, byte 2, LSB of wValue
+            WVALUEL: mmio.Mmio(packed struct(u32) {
+                ///  SETUP data, byte 2, LSB of wValue
+                WVALUEL: u8,
+                padding: u24,
+            }),
+            ///  SETUP data, byte 3, MSB of wValue
+            WVALUEH: mmio.Mmio(packed struct(u32) {
+                ///  SETUP data, byte 3, MSB of wValue
+                WVALUEH: u8,
+                padding: u24,
+            }),
+            ///  SETUP data, byte 4, LSB of wIndex
+            WINDEXL: mmio.Mmio(packed struct(u32) {
+                ///  SETUP data, byte 4, LSB of wIndex
+                WINDEXL: u8,
+                padding: u24,
+            }),
+            ///  SETUP data, byte 5, MSB of wIndex
+            WINDEXH: mmio.Mmio(packed struct(u32) {
+                ///  SETUP data, byte 5, MSB of wIndex
+                WINDEXH: u8,
+                padding: u24,
+            }),
+            ///  SETUP data, byte 6, LSB of wLength
+            WLENGTHL: mmio.Mmio(packed struct(u32) {
+                ///  SETUP data, byte 6, LSB of wLength
+                WLENGTHL: u8,
+                padding: u24,
+            }),
+            ///  SETUP data, byte 7, MSB of wLength
+            WLENGTHH: mmio.Mmio(packed struct(u32) {
+                ///  SETUP data, byte 7, MSB of wLength
+                WLENGTHH: u8,
+                padding: u24,
+            }),
+            reserved1280: [96]u8,
+            ///  Enable USB
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable USB
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  USB peripheral is disabled
+                        Disabled = 0x0,
+                        ///  USB peripheral is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Control of the USB pull-up
+            USBPULLUP: mmio.Mmio(packed struct(u32) {
+                ///  Control of the USB pull-up on the D+ line
+                CONNECT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pull-up is disconnected
+                        Disabled = 0x0,
+                        ///  Pull-up is connected to D+
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing).
+            DPDMVALUE: mmio.Mmio(packed struct(u32) {
+                ///  State D+ and D- lines will be forced into by the DPDMDRIVE task
+                STATE: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        ///  D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state)
+                        Resume = 0x1,
+                        ///  D+ forced high, D- forced low (J state)
+                        J = 0x2,
+                        ///  D+ forced low, D- forced high (K state)
+                        K = 0x4,
+                        _,
+                    },
+                },
+                padding: u27,
+            }),
+            ///  Data toggle control and status
+            DTOGGLE: mmio.Mmio(packed struct(u32) {
+                ///  Select bulk endpoint number
+                EP: u3,
+                reserved7: u4,
+                ///  Selects IN or OUT endpoint
+                IO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Selects OUT endpoint
+                        Out = 0x0,
+                        ///  Selects IN endpoint
+                        In = 0x1,
+                    },
+                },
+                ///  Data toggle value
+                VALUE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  No action on data toggle when writing the register with this value
+                        Nop = 0x0,
+                        ///  Data toggle is DATA0 on endpoint set by EP and IO
+                        Data0 = 0x1,
+                        ///  Data toggle is DATA1 on endpoint set by EP and IO
+                        Data1 = 0x2,
+                        _,
+                    },
+                },
+                padding: u22,
+            }),
+            ///  Endpoint IN enable
+            EPINEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable IN endpoint 0
+                IN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint IN 0 (no response to IN tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint IN 0 (response to IN tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable IN endpoint 1
+                IN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint IN 1 (no response to IN tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint IN 1 (response to IN tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable IN endpoint 2
+                IN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint IN 2 (no response to IN tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint IN 2 (response to IN tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable IN endpoint 3
+                IN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint IN 3 (no response to IN tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint IN 3 (response to IN tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable IN endpoint 4
+                IN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint IN 4 (no response to IN tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint IN 4 (response to IN tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable IN endpoint 5
+                IN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint IN 5 (no response to IN tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint IN 5 (response to IN tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable IN endpoint 6
+                IN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint IN 6 (no response to IN tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint IN 6 (response to IN tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable IN endpoint 7
+                IN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint IN 7 (no response to IN tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint IN 7 (response to IN tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable ISO IN endpoint
+                ISOIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable ISO IN endpoint 8
+                        Disable = 0x0,
+                        ///  Enable ISO IN endpoint 8
+                        Enable = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            ///  Endpoint OUT enable
+            EPOUTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable OUT endpoint 0
+                OUT0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint OUT 0 (no response to OUT tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint OUT 0 (response to OUT tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable OUT endpoint 1
+                OUT1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint OUT 1 (no response to OUT tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint OUT 1 (response to OUT tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable OUT endpoint 2
+                OUT2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint OUT 2 (no response to OUT tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint OUT 2 (response to OUT tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable OUT endpoint 3
+                OUT3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint OUT 3 (no response to OUT tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint OUT 3 (response to OUT tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable OUT endpoint 4
+                OUT4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint OUT 4 (no response to OUT tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint OUT 4 (response to OUT tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable OUT endpoint 5
+                OUT5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint OUT 5 (no response to OUT tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint OUT 5 (response to OUT tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable OUT endpoint 6
+                OUT6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint OUT 6 (no response to OUT tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint OUT 6 (response to OUT tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable OUT endpoint 7
+                OUT7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable endpoint OUT 7 (no response to OUT tokens)
+                        Disable = 0x0,
+                        ///  Enable endpoint OUT 7 (response to OUT tokens)
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable ISO OUT endpoint 8
+                ISOOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable ISO OUT endpoint 8
+                        Disable = 0x0,
+                        ///  Enable ISO OUT endpoint 8
+                        Enable = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            ///  STALL endpoints
+            EPSTALL: mmio.Mmio(packed struct(u32) {
+                ///  Select endpoint number
+                EP: u3,
+                reserved7: u4,
+                ///  Selects IN or OUT endpoint
+                IO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Selects OUT endpoint
+                        Out = 0x0,
+                        ///  Selects IN endpoint
+                        In = 0x1,
+                    },
+                },
+                ///  Stall selected endpoint
+                STALL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Don't stall selected endpoint
+                        UnStall = 0x0,
+                        ///  Stall selected endpoint
+                        Stall = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            ///  Controls the split of ISO buffers
+            ISOSPLIT: mmio.Mmio(packed struct(u32) {
+                ///  Controls the split of ISO buffers
+                SPLIT: packed union {
+                    raw: u16,
+                    value: enum(u16) {
+                        ///  Full buffer dedicated to either iso IN or OUT
+                        OneDir = 0x0,
+                        ///  Lower half for IN, upper half for OUT
+                        HalfIN = 0x80,
+                        _,
+                    },
+                },
+                padding: u16,
+            }),
+            ///  Returns the current value of the start of frame counter
+            FRAMECNTR: mmio.Mmio(packed struct(u32) {
+                ///  Returns the current value of the start of frame counter
+                FRAMECNTR: u11,
+                padding: u21,
+            }),
+            reserved1324: [8]u8,
+            ///  Controls USBD peripheral low power mode during USB suspend
+            LOWPOWER: mmio.Mmio(packed struct(u32) {
+                ///  Controls USBD peripheral low-power mode during USB suspend
+                LOWPOWER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Software must write this value to exit low power mode and before performing a remote wake-up
+                        ForceNormal = 0x0,
+                        ///  Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral
+                        LowPower = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent
+            ISOINCONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent
+                RESPONSE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Endpoint does not respond in that case
+                        NoResp = 0x0,
+                        ///  Endpoint responds with a zero-length data packet in that case
+                        ZeroData = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  NFC-A compatible radio
+        pub const NFCT = extern struct {
+            ///  Activate NFCT peripheral for incoming and outgoing frames, change state to activated
+            TASKS_ACTIVATE: mmio.Mmio(packed struct(u32) {
+                ///  Activate NFCT peripheral for incoming and outgoing frames, change state to activated
+                TASKS_ACTIVATE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Disable NFCT peripheral
+            TASKS_DISABLE: mmio.Mmio(packed struct(u32) {
+                ///  Disable NFCT peripheral
+                TASKS_DISABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Enable NFC sense field mode, change state to sense mode
+            TASKS_SENSE: mmio.Mmio(packed struct(u32) {
+                ///  Enable NFC sense field mode, change state to sense mode
+                TASKS_SENSE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start transmission of an outgoing frame, change state to transmit
+            TASKS_STARTTX: mmio.Mmio(packed struct(u32) {
+                ///  Start transmission of an outgoing frame, change state to transmit
+                TASKS_STARTTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved28: [12]u8,
+            ///  Initializes the EasyDMA for receive.
+            TASKS_ENABLERXDATA: mmio.Mmio(packed struct(u32) {
+                ///  Initializes the EasyDMA for receive.
+                TASKS_ENABLERXDATA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved36: [4]u8,
+            ///  Force state machine to IDLE state
+            TASKS_GOIDLE: mmio.Mmio(packed struct(u32) {
+                ///  Force state machine to IDLE state
+                TASKS_GOIDLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Force state machine to SLEEP_A state
+            TASKS_GOSLEEP: mmio.Mmio(packed struct(u32) {
+                ///  Force state machine to SLEEP_A state
+                TASKS_GOSLEEP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [212]u8,
+            ///  The NFCT peripheral is ready to receive and send frames
+            EVENTS_READY: mmio.Mmio(packed struct(u32) {
+                ///  The NFCT peripheral is ready to receive and send frames
+                EVENTS_READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Remote NFC field detected
+            EVENTS_FIELDDETECTED: mmio.Mmio(packed struct(u32) {
+                ///  Remote NFC field detected
+                EVENTS_FIELDDETECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Remote NFC field lost
+            EVENTS_FIELDLOST: mmio.Mmio(packed struct(u32) {
+                ///  Remote NFC field lost
+                EVENTS_FIELDLOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Marks the start of the first symbol of a transmitted frame
+            EVENTS_TXFRAMESTART: mmio.Mmio(packed struct(u32) {
+                ///  Marks the start of the first symbol of a transmitted frame
+                EVENTS_TXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Marks the end of the last transmitted on-air symbol of a frame
+            EVENTS_TXFRAMEEND: mmio.Mmio(packed struct(u32) {
+                ///  Marks the end of the last transmitted on-air symbol of a frame
+                EVENTS_TXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Marks the end of the first symbol of a received frame
+            EVENTS_RXFRAMESTART: mmio.Mmio(packed struct(u32) {
+                ///  Marks the end of the first symbol of a received frame
+                EVENTS_RXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer
+            EVENTS_RXFRAMEEND: mmio.Mmio(packed struct(u32) {
+                ///  Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer
+                EVENTS_RXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  NFC error reported. The ERRORSTATUS register contains details on the source of the error.
+            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
+                ///  NFC error reported. The ERRORSTATUS register contains details on the source of the error.
+                EVENTS_ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved296: [8]u8,
+            ///  NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.
+            EVENTS_RXERROR: mmio.Mmio(packed struct(u32) {
+                ///  NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.
+                EVENTS_RXERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.
+            EVENTS_ENDRX: mmio.Mmio(packed struct(u32) {
+                ///  RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.
+                EVENTS_ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer
+            EVENTS_ENDTX: mmio.Mmio(packed struct(u32) {
+                ///  Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer
+                EVENTS_ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved312: [4]u8,
+            ///  Auto collision resolution process has started
+            EVENTS_AUTOCOLRESSTARTED: mmio.Mmio(packed struct(u32) {
+                ///  Auto collision resolution process has started
+                EVENTS_AUTOCOLRESSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved328: [12]u8,
+            ///  NFC auto collision resolution error reported.
+            EVENTS_COLLISION: mmio.Mmio(packed struct(u32) {
+                ///  NFC auto collision resolution error reported.
+                EVENTS_COLLISION: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  NFC auto collision resolution successfully completed
+            EVENTS_SELECTED: mmio.Mmio(packed struct(u32) {
+                ///  NFC auto collision resolution successfully completed
+                EVENTS_SELECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  EasyDMA is ready to receive or send frames.
+            EVENTS_STARTED: mmio.Mmio(packed struct(u32) {
+                ///  EasyDMA is ready to receive or send frames.
+                EVENTS_STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [172]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between event FIELDDETECTED and task ACTIVATE
+                FIELDDETECTED_ACTIVATE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event FIELDLOST and task SENSE
+                FIELDLOST_SENSE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                reserved5: u3,
+                ///  Shortcut between event TXFRAMEEND and task ENABLERXDATA
+                TXFRAMEEND_ENABLERXDATA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u26,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event FIELDDETECTED
+                FIELDDETECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event FIELDLOST
+                FIELDLOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TXFRAMESTART
+                TXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TXFRAMEEND
+                TXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event RXFRAMESTART
+                RXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event RXFRAMEEND
+                RXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u2,
+                ///  Enable or disable interrupt for event RXERROR
+                RXERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDRX
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event ENDTX
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved14: u1,
+                ///  Enable or disable interrupt for event AUTOCOLRESSTARTED
+                AUTOCOLRESSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u3,
+                ///  Enable or disable interrupt for event COLLISION
+                COLLISION: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event SELECTED
+                SELECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u11,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event FIELDDETECTED
+                FIELDDETECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event FIELDLOST
+                FIELDLOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TXFRAMESTART
+                TXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TXFRAMEEND
+                TXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event RXFRAMESTART
+                RXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event RXFRAMEEND
+                RXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u2,
+                ///  Write '1' to enable interrupt for event RXERROR
+                RXERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDRX
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDTX
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved14: u1,
+                ///  Write '1' to enable interrupt for event AUTOCOLRESSTARTED
+                AUTOCOLRESSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u3,
+                ///  Write '1' to enable interrupt for event COLLISION
+                COLLISION: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event SELECTED
+                SELECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u11,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event FIELDDETECTED
+                FIELDDETECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event FIELDLOST
+                FIELDLOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TXFRAMESTART
+                TXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TXFRAMEEND
+                TXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event RXFRAMESTART
+                RXFRAMESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event RXFRAMEEND
+                RXFRAMEEND: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved10: u2,
+                ///  Write '1' to disable interrupt for event RXERROR
+                RXERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDRX
+                ENDRX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDTX
+                ENDTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved14: u1,
+                ///  Write '1' to disable interrupt for event AUTOCOLRESSTARTED
+                AUTOCOLRESSTARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved18: u3,
+                ///  Write '1' to disable interrupt for event COLLISION
+                COLLISION: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event SELECTED
+                SELECTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u11,
+            }),
+            reserved1028: [248]u8,
+            ///  NFC Error Status register
+            ERRORSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX
+                FRAMEDELAYTIMEOUT: u1,
+                padding: u31,
+            }),
+            reserved1040: [8]u8,
+            ///  NfcTag state register
+            NFCTAGSTATE: mmio.Mmio(packed struct(u32) {
+                ///  NfcTag state
+                NFCTAGSTATE: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Disabled or sense
+                        Disabled = 0x0,
+                        ///  RampUp
+                        RampUp = 0x2,
+                        ///  Idle
+                        Idle = 0x3,
+                        ///  Receive
+                        Receive = 0x4,
+                        ///  FrameDelay
+                        FrameDelay = 0x5,
+                        ///  Transmit
+                        Transmit = 0x6,
+                        _,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1056: [12]u8,
+            ///  Sleep state during automatic collision resolution
+            SLEEPSTATE: mmio.Mmio(packed struct(u32) {
+                ///  Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task.
+                SLEEPSTATE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  State is IDLE.
+                        Idle = 0x0,
+                        ///  State is SLEEP_A.
+                        SleepA = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1084: [24]u8,
+            ///  Indicates the presence or not of a valid field
+            FIELDPRESENT: mmio.Mmio(packed struct(u32) {
+                ///  Indicates if a valid field is present. Available only in the activated state.
+                FIELDPRESENT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No valid field detected
+                        NoField = 0x0,
+                        ///  Valid field detected
+                        FieldPresent = 0x1,
+                    },
+                },
+                ///  Indicates if the low level has locked to the field
+                LOCKDETECT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Not locked to field
+                        NotLocked = 0x0,
+                        ///  Locked to field
+                        Locked = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1284: [196]u8,
+            ///  Minimum frame delay
+            FRAMEDELAYMIN: mmio.Mmio(packed struct(u32) {
+                ///  Minimum frame delay in number of 13.56 MHz clocks
+                FRAMEDELAYMIN: u16,
+                padding: u16,
+            }),
+            ///  Maximum frame delay
+            FRAMEDELAYMAX: mmio.Mmio(packed struct(u32) {
+                ///  Maximum frame delay in number of 13.56 MHz clocks
+                FRAMEDELAYMAX: u20,
+                padding: u12,
+            }),
+            ///  Configuration register for the Frame Delay Timer
+            FRAMEDELAYMODE: mmio.Mmio(packed struct(u32) {
+                ///  Configuration register for the Frame Delay Timer
+                FRAMEDELAYMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout.
+                        FreeRun = 0x0,
+                        ///  Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX
+                        Window = 0x1,
+                        ///  Frame is transmitted exactly at FRAMEDELAYMAX
+                        ExactVal = 0x2,
+                        ///  Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX
+                        WindowGrid = 0x3,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Packet pointer for TXD and RXD data storage in Data RAM
+            PACKETPTR: mmio.Mmio(packed struct(u32) {
+                ///  Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address.
+                PTR: u32,
+            }),
+            ///  Size of the RAM buffer allocated to TXD and RXD data storage each
+            MAXLEN: mmio.Mmio(packed struct(u32) {
+                ///  Size of the RAM buffer allocated to TXD and RXD data storage each
+                MAXLEN: u9,
+                padding: u23,
+            }),
+            reserved1424: [120]u8,
+            ///  Last NFCID1 part (4, 7 or 10 bytes ID)
+            NFCID1_LAST: mmio.Mmio(packed struct(u32) {
+                ///  NFCID1 byte Z (very last byte sent)
+                NFCID1_Z: u8,
+                ///  NFCID1 byte Y
+                NFCID1_Y: u8,
+                ///  NFCID1 byte X
+                NFCID1_X: u8,
+                ///  NFCID1 byte W
+                NFCID1_W: u8,
+            }),
+            ///  Second last NFCID1 part (7 or 10 bytes ID)
+            NFCID1_2ND_LAST: mmio.Mmio(packed struct(u32) {
+                ///  NFCID1 byte V
+                NFCID1_V: u8,
+                ///  NFCID1 byte U
+                NFCID1_U: u8,
+                ///  NFCID1 byte T
+                NFCID1_T: u8,
+                padding: u8,
+            }),
+            ///  Third last NFCID1 part (10 bytes ID)
+            NFCID1_3RD_LAST: mmio.Mmio(packed struct(u32) {
+                ///  NFCID1 byte S
+                NFCID1_S: u8,
+                ///  NFCID1 byte R
+                NFCID1_R: u8,
+                ///  NFCID1 byte Q
+                NFCID1_Q: u8,
+                padding: u8,
+            }),
+            ///  Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled.
+            AUTOCOLRESCONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Enables/disables auto collision resolution
+                MODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Auto collision resolution enabled
+                        Enabled = 0x0,
+                        ///  Auto collision resolution disabled
+                        Disabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  NFC-A SENS_RES auto-response settings
+            SENSRES: mmio.Mmio(packed struct(u32) {
+                ///  Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
+                BITFRAMESDD: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        ///  SDD pattern 00000
+                        SDD00000 = 0x0,
+                        ///  SDD pattern 00001
+                        SDD00001 = 0x1,
+                        ///  SDD pattern 00010
+                        SDD00010 = 0x2,
+                        ///  SDD pattern 00100
+                        SDD00100 = 0x4,
+                        ///  SDD pattern 01000
+                        SDD01000 = 0x8,
+                        ///  SDD pattern 10000
+                        SDD10000 = 0x10,
+                        _,
+                    },
+                },
+                ///  Reserved for future use. Shall be 0.
+                RFU5: u1,
+                ///  NFCID1 size. This value is used by the auto collision resolution engine.
+                NFCIDSIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  NFCID1 size: single (4 bytes)
+                        NFCID1Single = 0x0,
+                        ///  NFCID1 size: double (7 bytes)
+                        NFCID1Double = 0x1,
+                        ///  NFCID1 size: triple (10 bytes)
+                        NFCID1Triple = 0x2,
+                        _,
+                    },
+                },
+                ///  Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
+                PLATFCONFIG: u4,
+                ///  Reserved for future use. Shall be 0.
+                RFU74: u4,
+                padding: u16,
+            }),
+            ///  NFC-A SEL_RES auto-response settings
+            SELRES: mmio.Mmio(packed struct(u32) {
+                ///  Reserved for future use. Shall be 0.
+                RFU10: u2,
+                ///  Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0)
+                CASCADE: u1,
+                ///  Reserved for future use. Shall be 0.
+                RFU43: u2,
+                ///  Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
+                PROTOCOL: u2,
+                ///  Reserved for future use. Shall be 0.
+                RFU7: u1,
+                padding: u24,
+            }),
+        };
+
+        ///  GPIO Tasks and Events
+        pub const GPIOTE = extern struct {
+            ///  Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
+            TASKS_OUT: [8]mmio.Mmio(packed struct(u32) {
+                ///  Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
+                TASKS_OUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved48: [16]u8,
+            ///  Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
+            TASKS_SET: [8]mmio.Mmio(packed struct(u32) {
+                ///  Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
+                TASKS_SET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved96: [16]u8,
+            ///  Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
+            TASKS_CLR: [8]mmio.Mmio(packed struct(u32) {
+                ///  Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
+                TASKS_CLR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [128]u8,
+            ///  Description collection: Event generated from pin specified in CONFIG[n].PSEL
+            EVENTS_IN: [8]mmio.Mmio(packed struct(u32) {
+                ///  Event generated from pin specified in CONFIG[n].PSEL
+                EVENTS_IN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved380: [92]u8,
+            ///  Event generated from multiple input GPIO pins with SENSE mechanism enabled
+            EVENTS_PORT: mmio.Mmio(packed struct(u32) {
+                ///  Event generated from multiple input GPIO pins with SENSE mechanism enabled
+                EVENTS_PORT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [388]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event IN[0]
+                IN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event IN[1]
+                IN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event IN[2]
+                IN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event IN[3]
+                IN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event IN[4]
+                IN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event IN[5]
+                IN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event IN[6]
+                IN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event IN[7]
+                IN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved31: u23,
+                ///  Write '1' to enable interrupt for event PORT
+                PORT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event IN[0]
+                IN0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event IN[1]
+                IN1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event IN[2]
+                IN2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event IN[3]
+                IN3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event IN[4]
+                IN4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event IN[5]
+                IN5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event IN[6]
+                IN6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event IN[7]
+                IN7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved31: u23,
+                ///  Write '1' to disable interrupt for event PORT
+                PORT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            reserved1296: [516]u8,
+            ///  Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
+            CONFIG: [8]mmio.Mmio(packed struct(u32) {
+                ///  Mode
+                MODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.
+                        Disabled = 0x0,
+                        ///  Event mode
+                        Event = 0x1,
+                        ///  Task mode
+                        Task = 0x3,
+                        _,
+                    },
+                },
+                reserved8: u6,
+                ///  GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event
+                PSEL: u5,
+                ///  Port number
+                PORT: u1,
+                reserved16: u2,
+                ///  When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
+                POLARITY: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.
+                        None = 0x0,
+                        ///  Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.
+                        LoToHi = 0x1,
+                        ///  Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.
+                        HiToLo = 0x2,
+                        ///  Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.
+                        Toggle = 0x3,
+                    },
+                },
+                reserved20: u2,
+                ///  When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
+                OUTINIT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Task mode: Initial value of pin before task triggering is low
+                        Low = 0x0,
+                        ///  Task mode: Initial value of pin before task triggering is high
+                        High = 0x1,
+                    },
+                },
+                padding: u11,
+            }),
+        };
+
+        ///  Successive approximation register (SAR) analog-to-digital converter
+        pub const SAADC = extern struct {
+            ///  Starts the SAADC and prepares the result buffer in RAM
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Starts the SAADC and prepares the result buffer in RAM
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Takes one SAADC sample
+            TASKS_SAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  Takes one SAADC sample
+                TASKS_SAMPLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stops the SAADC and terminates all on-going conversions
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stops the SAADC and terminates all on-going conversions
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Starts offset auto-calibration
+            TASKS_CALIBRATEOFFSET: mmio.Mmio(packed struct(u32) {
+                ///  Starts offset auto-calibration
+                TASKS_CALIBRATEOFFSET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [240]u8,
+            ///  The SAADC has started
+            EVENTS_STARTED: mmio.Mmio(packed struct(u32) {
+                ///  The SAADC has started
+                EVENTS_STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  The SAADC has filled up the result buffer
+            EVENTS_END: mmio.Mmio(packed struct(u32) {
+                ///  The SAADC has filled up the result buffer
+                EVENTS_END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.
+            EVENTS_DONE: mmio.Mmio(packed struct(u32) {
+                ///  A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.
+                EVENTS_DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Result ready for transfer to RAM
+            EVENTS_RESULTDONE: mmio.Mmio(packed struct(u32) {
+                ///  Result ready for transfer to RAM
+                EVENTS_RESULTDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Calibration is complete
+            EVENTS_CALIBRATEDONE: mmio.Mmio(packed struct(u32) {
+                ///  Calibration is complete
+                EVENTS_CALIBRATEDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  The SAADC has stopped
+            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
+                ///  The SAADC has stopped
+                EVENTS_STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved768: [488]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event DONE
+                DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event RESULTDONE
+                RESULTDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CALIBRATEDONE
+                CALIBRATEDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH0LIMITH
+                CH0LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH0LIMITL
+                CH0LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH1LIMITH
+                CH1LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH1LIMITL
+                CH1LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH2LIMITH
+                CH2LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH2LIMITL
+                CH2LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH3LIMITH
+                CH3LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH3LIMITL
+                CH3LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH4LIMITH
+                CH4LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH4LIMITL
+                CH4LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH5LIMITH
+                CH5LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH5LIMITL
+                CH5LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH6LIMITH
+                CH6LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH6LIMITL
+                CH6LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH7LIMITH
+                CH7LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CH7LIMITL
+                CH7LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u10,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event DONE
+                DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event RESULTDONE
+                RESULTDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CALIBRATEDONE
+                CALIBRATEDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH0LIMITH
+                CH0LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH0LIMITL
+                CH0LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH1LIMITH
+                CH1LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH1LIMITL
+                CH1LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH2LIMITH
+                CH2LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH2LIMITL
+                CH2LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH3LIMITH
+                CH3LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH3LIMITL
+                CH3LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH4LIMITH
+                CH4LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH4LIMITL
+                CH4LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH5LIMITH
+                CH5LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH5LIMITL
+                CH5LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH6LIMITH
+                CH6LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH6LIMITL
+                CH6LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH7LIMITH
+                CH7LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CH7LIMITL
+                CH7LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u10,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event STARTED
+                STARTED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event DONE
+                DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event RESULTDONE
+                RESULTDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CALIBRATEDONE
+                CALIBRATEDONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH0LIMITH
+                CH0LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH0LIMITL
+                CH0LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH1LIMITH
+                CH1LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH1LIMITL
+                CH1LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH2LIMITH
+                CH2LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH2LIMITL
+                CH2LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH3LIMITH
+                CH3LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH3LIMITL
+                CH3LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH4LIMITH
+                CH4LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH4LIMITL
+                CH4LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH5LIMITH
+                CH5LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH5LIMITL
+                CH5LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH6LIMITH
+                CH6LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH6LIMITL
+                CH6LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH7LIMITH
+                CH7LIMITH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CH7LIMITL
+                CH7LIMITL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u10,
+            }),
+            reserved1024: [244]u8,
+            ///  Status
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  Status
+                STATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  SAADC is ready. No on-going conversions.
+                        Ready = 0x0,
+                        ///  SAADC is busy. Conversion in progress.
+                        Busy = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1280: [252]u8,
+            ///  Enable or disable SAADC
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable SAADC
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable SAADC
+                        Disabled = 0x0,
+                        ///  Enable SAADC
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1520: [236]u8,
+            ///  Resolution configuration
+            RESOLUTION: mmio.Mmio(packed struct(u32) {
+                ///  Set the resolution
+                VAL: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  8 bits
+                        @"8bit" = 0x0,
+                        ///  10 bits
+                        @"10bit" = 0x1,
+                        ///  12 bits
+                        @"12bit" = 0x2,
+                        ///  14 bits
+                        @"14bit" = 0x3,
+                        _,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.
+            OVERSAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  Oversample control
+                OVERSAMPLE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Bypass oversampling
+                        Bypass = 0x0,
+                        ///  Oversample 2x
+                        Over2x = 0x1,
+                        ///  Oversample 4x
+                        Over4x = 0x2,
+                        ///  Oversample 8x
+                        Over8x = 0x3,
+                        ///  Oversample 16x
+                        Over16x = 0x4,
+                        ///  Oversample 32x
+                        Over32x = 0x5,
+                        ///  Oversample 64x
+                        Over64x = 0x6,
+                        ///  Oversample 128x
+                        Over128x = 0x7,
+                        ///  Oversample 256x
+                        Over256x = 0x8,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Controls normal or continuous sample rate
+            SAMPLERATE: mmio.Mmio(packed struct(u32) {
+                ///  Capture and compare value. Sample rate is 16 MHz/CC
+                CC: u11,
+                reserved12: u1,
+                ///  Select mode for sample rate control
+                MODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Rate is controlled from SAMPLE task
+                        Task = 0x0,
+                        ///  Rate is controlled from local timer (use CC to control the rate)
+                        Timers = 0x1,
+                    },
+                },
+                padding: u19,
+            }),
+        };
+
+        ///  Timer/Counter 0
+        pub const TIMER0 = extern struct {
+            ///  Start Timer
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Start Timer
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop Timer
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop Timer
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Increment Timer (Counter mode only)
+            TASKS_COUNT: mmio.Mmio(packed struct(u32) {
+                ///  Increment Timer (Counter mode only)
+                TASKS_COUNT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Clear time
+            TASKS_CLEAR: mmio.Mmio(packed struct(u32) {
+                ///  Clear time
+                TASKS_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Deprecated register - Shut down timer
+            TASKS_SHUTDOWN: mmio.Mmio(packed struct(u32) {
+                ///  Deprecated field - Shut down timer
+                TASKS_SHUTDOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved64: [44]u8,
+            ///  Description collection: Capture Timer value to CC[n] register
+            TASKS_CAPTURE: [6]mmio.Mmio(packed struct(u32) {
+                ///  Capture Timer value to CC[n] register
+                TASKS_CAPTURE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved320: [232]u8,
+            ///  Description collection: Compare event on CC[n] match
+            EVENTS_COMPARE: [6]mmio.Mmio(packed struct(u32) {
+                ///  Compare event on CC[n] match
+                EVENTS_COMPARE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [168]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between event COMPARE[0] and task CLEAR
+                COMPARE0_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event COMPARE[1] and task CLEAR
+                COMPARE1_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event COMPARE[2] and task CLEAR
+                COMPARE2_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event COMPARE[3] and task CLEAR
+                COMPARE3_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event COMPARE[4] and task CLEAR
+                COMPARE4_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event COMPARE[5] and task CLEAR
+                COMPARE5_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                reserved8: u2,
+                ///  Shortcut between event COMPARE[0] and task STOP
+                COMPARE0_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event COMPARE[1] and task STOP
+                COMPARE1_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event COMPARE[2] and task STOP
+                COMPARE2_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event COMPARE[3] and task STOP
+                COMPARE3_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event COMPARE[4] and task STOP
+                COMPARE4_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event COMPARE[5] and task STOP
+                COMPARE5_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u18,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  Write '1' to enable interrupt for event COMPARE[0]
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event COMPARE[1]
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event COMPARE[2]
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event COMPARE[3]
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event COMPARE[4]
+                COMPARE4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event COMPARE[5]
+                COMPARE5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u10,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  Write '1' to disable interrupt for event COMPARE[0]
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event COMPARE[1]
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event COMPARE[2]
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event COMPARE[3]
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event COMPARE[4]
+                COMPARE4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event COMPARE[5]
+                COMPARE5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u10,
+            }),
+            reserved1284: [504]u8,
+            ///  Timer mode selection
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Timer mode
+                MODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Select Timer mode
+                        Timer = 0x0,
+                        ///  Deprecated enumerator - Select Counter mode
+                        Counter = 0x1,
+                        ///  Select Low Power Counter mode
+                        LowPowerCounter = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Configure the number of bits used by the TIMER
+            BITMODE: mmio.Mmio(packed struct(u32) {
+                ///  Timer bit width
+                BITMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  16 bit timer bit width
+                        @"16Bit" = 0x0,
+                        ///  8 bit timer bit width
+                        @"08Bit" = 0x1,
+                        ///  24 bit timer bit width
+                        @"24Bit" = 0x2,
+                        ///  32 bit timer bit width
+                        @"32Bit" = 0x3,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1296: [4]u8,
+            ///  Timer prescaler register
+            PRESCALER: mmio.Mmio(packed struct(u32) {
+                ///  Prescaler value
+                PRESCALER: u4,
+                padding: u28,
+            }),
+            reserved1344: [44]u8,
+            ///  Description collection: Capture/Compare register n
+            CC: [6]mmio.Mmio(packed struct(u32) {
+                ///  Capture/Compare value
+                CC: u32,
+            }),
+        };
+
+        ///  FPU
+        pub const FPU = extern struct {
+            ///  Unused.
+            UNUSED: u32,
+        };
+
+        ///  Inter-IC Sound
+        pub const I2S = extern struct {
+            ///  Starts continuous I2S transfer. Also starts MCK generator when this is enabled.
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Starts continuous I2S transfer. Also starts MCK generator when this is enabled.
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved260: [252]u8,
+            ///  The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.
+            EVENTS_RXPTRUPD: mmio.Mmio(packed struct(u32) {
+                ///  The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.
+                EVENTS_RXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  I2S transfer stopped.
+            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
+                ///  I2S transfer stopped.
+                EVENTS_STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved276: [8]u8,
+            ///  The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
+            EVENTS_TXPTRUPD: mmio.Mmio(packed struct(u32) {
+                ///  The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
+                EVENTS_TXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved768: [488]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Enable or disable interrupt for event RXPTRUPD
+                RXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved5: u2,
+                ///  Enable or disable interrupt for event TXPTRUPD
+                TXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u26,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to enable interrupt for event RXPTRUPD
+                RXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved5: u2,
+                ///  Write '1' to enable interrupt for event TXPTRUPD
+                TXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u26,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Write '1' to disable interrupt for event RXPTRUPD
+                RXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved5: u2,
+                ///  Write '1' to disable interrupt for event TXPTRUPD
+                TXPTRUPD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u26,
+            }),
+            reserved1280: [500]u8,
+            ///  Enable I2S module.
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable I2S module.
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  Real time counter 0
+        pub const RTC0 = extern struct {
+            ///  Start RTC COUNTER
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Start RTC COUNTER
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop RTC COUNTER
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop RTC COUNTER
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Clear RTC COUNTER
+            TASKS_CLEAR: mmio.Mmio(packed struct(u32) {
+                ///  Clear RTC COUNTER
+                TASKS_CLEAR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Set COUNTER to 0xFFFFF0
+            TASKS_TRIGOVRFLW: mmio.Mmio(packed struct(u32) {
+                ///  Set COUNTER to 0xFFFFF0
+                TASKS_TRIGOVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [240]u8,
+            ///  Event on COUNTER increment
+            EVENTS_TICK: mmio.Mmio(packed struct(u32) {
+                ///  Event on COUNTER increment
+                EVENTS_TICK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Event on COUNTER overflow
+            EVENTS_OVRFLW: mmio.Mmio(packed struct(u32) {
+                ///  Event on COUNTER overflow
+                EVENTS_OVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved320: [56]u8,
+            ///  Description collection: Compare event on CC[n] match
+            EVENTS_COMPARE: [4]mmio.Mmio(packed struct(u32) {
+                ///  Compare event on CC[n] match
+                EVENTS_COMPARE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [436]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event TICK
+                TICK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event OVRFLW
+                OVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Write '1' to enable interrupt for event COMPARE[0]
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event COMPARE[1]
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event COMPARE[2]
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event COMPARE[3]
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event TICK
+                TICK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event OVRFLW
+                OVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Write '1' to disable interrupt for event COMPARE[0]
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event COMPARE[1]
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event COMPARE[2]
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event COMPARE[3]
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            reserved832: [52]u8,
+            ///  Enable or disable event routing
+            EVTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable event routing for event TICK
+                TICK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Disable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable event routing for event OVRFLW
+                OVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Disable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Enable or disable event routing for event COMPARE[0]
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Disable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable event routing for event COMPARE[1]
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Disable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable event routing for event COMPARE[2]
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Disable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable event routing for event COMPARE[3]
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Disable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            ///  Enable event routing
+            EVTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable event routing for event TICK
+                TICK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable event routing for event OVRFLW
+                OVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Write '1' to enable event routing for event COMPARE[0]
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable event routing for event COMPARE[1]
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable event routing for event COMPARE[2]
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable event routing for event COMPARE[3]
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            ///  Disable event routing
+            EVTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable event routing for event TICK
+                TICK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable event routing for event OVRFLW
+                OVRFLW: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved16: u14,
+                ///  Write '1' to disable event routing for event COMPARE[0]
+                COMPARE0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable event routing for event COMPARE[1]
+                COMPARE1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable event routing for event COMPARE[2]
+                COMPARE2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable event routing for event COMPARE[3]
+                COMPARE3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u12,
+            }),
+            reserved1284: [440]u8,
+            ///  Current COUNTER value
+            COUNTER: mmio.Mmio(packed struct(u32) {
+                ///  Counter value
+                COUNTER: u24,
+                padding: u8,
+            }),
+            ///  12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped
+            PRESCALER: mmio.Mmio(packed struct(u32) {
+                ///  Prescaler value
+                PRESCALER: u12,
+                padding: u20,
+            }),
+            reserved1344: [52]u8,
+            ///  Description collection: Compare register n
+            CC: [4]mmio.Mmio(packed struct(u32) {
+                ///  Compare value
+                COMPARE: u24,
+                padding: u8,
+            }),
+        };
+
+        ///  Temperature Sensor
+        pub const TEMP = extern struct {
+            ///  Start temperature measurement
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Start temperature measurement
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop temperature measurement
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop temperature measurement
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [248]u8,
+            ///  Temperature measurement complete, data ready
+            EVENTS_DATARDY: mmio.Mmio(packed struct(u32) {
+                ///  Temperature measurement complete, data ready
+                EVENTS_DATARDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [512]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event DATARDY
+                DATARDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event DATARDY
+                DATARDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1288: [508]u8,
+            ///  Temperature in degC (0.25deg steps)
+            TEMP: mmio.Mmio(packed struct(u32) {
+                ///  Temperature in degC (0.25deg steps)
+                TEMP: u32,
+            }),
+            reserved1312: [20]u8,
+            ///  Slope of 1st piece wise linear function
+            A0: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 1st piece wise linear function
+                A0: u12,
+                padding: u20,
+            }),
+            ///  Slope of 2nd piece wise linear function
+            A1: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 2nd piece wise linear function
+                A1: u12,
+                padding: u20,
+            }),
+            ///  Slope of 3rd piece wise linear function
+            A2: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 3rd piece wise linear function
+                A2: u12,
+                padding: u20,
+            }),
+            ///  Slope of 4th piece wise linear function
+            A3: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 4th piece wise linear function
+                A3: u12,
+                padding: u20,
+            }),
+            ///  Slope of 5th piece wise linear function
+            A4: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 5th piece wise linear function
+                A4: u12,
+                padding: u20,
+            }),
+            ///  Slope of 6th piece wise linear function
+            A5: mmio.Mmio(packed struct(u32) {
+                ///  Slope of 6th piece wise linear function
+                A5: u12,
+                padding: u20,
+            }),
+            reserved1344: [8]u8,
+            ///  y-intercept of 1st piece wise linear function
+            B0: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 1st piece wise linear function
+                B0: u14,
+                padding: u18,
+            }),
+            ///  y-intercept of 2nd piece wise linear function
+            B1: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 2nd piece wise linear function
+                B1: u14,
+                padding: u18,
+            }),
+            ///  y-intercept of 3rd piece wise linear function
+            B2: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 3rd piece wise linear function
+                B2: u14,
+                padding: u18,
+            }),
+            ///  y-intercept of 4th piece wise linear function
+            B3: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 4th piece wise linear function
+                B3: u14,
+                padding: u18,
+            }),
+            ///  y-intercept of 5th piece wise linear function
+            B4: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 5th piece wise linear function
+                B4: u14,
+                padding: u18,
+            }),
+            ///  y-intercept of 6th piece wise linear function
+            B5: mmio.Mmio(packed struct(u32) {
+                ///  y-intercept of 6th piece wise linear function
+                B5: u14,
+                padding: u18,
+            }),
+            reserved1376: [8]u8,
+            ///  End point of 1st piece wise linear function
+            T0: mmio.Mmio(packed struct(u32) {
+                ///  End point of 1st piece wise linear function
+                T0: u8,
+                padding: u24,
+            }),
+            ///  End point of 2nd piece wise linear function
+            T1: mmio.Mmio(packed struct(u32) {
+                ///  End point of 2nd piece wise linear function
+                T1: u8,
+                padding: u24,
+            }),
+            ///  End point of 3rd piece wise linear function
+            T2: mmio.Mmio(packed struct(u32) {
+                ///  End point of 3rd piece wise linear function
+                T2: u8,
+                padding: u24,
+            }),
+            ///  End point of 4th piece wise linear function
+            T3: mmio.Mmio(packed struct(u32) {
+                ///  End point of 4th piece wise linear function
+                T3: u8,
+                padding: u24,
+            }),
+            ///  End point of 5th piece wise linear function
+            T4: mmio.Mmio(packed struct(u32) {
+                ///  End point of 5th piece wise linear function
+                T4: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  Random Number Generator
+        pub const RNG = extern struct {
+            ///  Task starting the random number generator
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Task starting the random number generator
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Task stopping the random number generator
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Task stopping the random number generator
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [248]u8,
+            ///  Event being generated for every new random number written to the VALUE register
+            EVENTS_VALRDY: mmio.Mmio(packed struct(u32) {
+                ///  Event being generated for every new random number written to the VALUE register
+                EVENTS_VALRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [252]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between event VALRDY and task STOP
+                VALRDY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event VALRDY
+                VALRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event VALRDY
+                VALRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1284: [504]u8,
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Bias correction
+                DERCEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disabled
+                        Disabled = 0x0,
+                        ///  Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Output random number
+            VALUE: mmio.Mmio(packed struct(u32) {
+                ///  Generated random number
+                VALUE: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  AES ECB Mode Encryption
+        pub const ECB = extern struct {
+            ///  Start ECB block encrypt
+            TASKS_STARTECB: mmio.Mmio(packed struct(u32) {
+                ///  Start ECB block encrypt
+                TASKS_STARTECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Abort a possible executing ECB operation
+            TASKS_STOPECB: mmio.Mmio(packed struct(u32) {
+                ///  Abort a possible executing ECB operation
+                TASKS_STOPECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [248]u8,
+            ///  ECB block encrypt complete
+            EVENTS_ENDECB: mmio.Mmio(packed struct(u32) {
+                ///  ECB block encrypt complete
+                EVENTS_ENDECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  ECB block encrypt aborted because of a STOPECB task or due to an error
+            EVENTS_ERRORECB: mmio.Mmio(packed struct(u32) {
+                ///  ECB block encrypt aborted because of a STOPECB task or due to an error
+                EVENTS_ERRORECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [508]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event ENDECB
+                ENDECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ERRORECB
+                ERRORECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event ENDECB
+                ENDECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ERRORECB
+                ERRORECB: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1284: [504]u8,
+            ///  ECB block encrypt memory pointers
+            ECBDATAPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to the ECB data structure (see Table 1 ECB data structure overview)
+                ECBDATAPTR: u32,
+            }),
+        };
+
+        ///  Accelerated Address Resolver
+        pub const AAR = extern struct {
+            ///  Start resolving addresses based on IRKs specified in the IRK data structure
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Start resolving addresses based on IRKs specified in the IRK data structure
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved8: [4]u8,
+            ///  Stop resolving addresses
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop resolving addresses
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [244]u8,
+            ///  Address resolution procedure complete
+            EVENTS_END: mmio.Mmio(packed struct(u32) {
+                ///  Address resolution procedure complete
+                EVENTS_END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Address resolved
+            EVENTS_RESOLVED: mmio.Mmio(packed struct(u32) {
+                ///  Address resolved
+                EVENTS_RESOLVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Address not resolved
+            EVENTS_NOTRESOLVED: mmio.Mmio(packed struct(u32) {
+                ///  Address not resolved
+                EVENTS_NOTRESOLVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [504]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event RESOLVED
+                RESOLVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event NOTRESOLVED
+                NOTRESOLVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event END
+                END: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event RESOLVED
+                RESOLVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event NOTRESOLVED
+                NOTRESOLVED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1024: [244]u8,
+            ///  Resolution status
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  The IRK that was used last time an address was resolved
+                STATUS: u4,
+                padding: u28,
+            }),
+            reserved1280: [252]u8,
+            ///  Enable AAR
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable AAR
+                ENABLE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x3,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Number of IRKs
+            NIRK: mmio.Mmio(packed struct(u32) {
+                ///  Number of Identity root keys available in the IRK data structure
+                NIRK: u5,
+                padding: u27,
+            }),
+            ///  Pointer to IRK data structure
+            IRKPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to the IRK data structure
+                IRKPTR: u32,
+            }),
+            reserved1296: [4]u8,
+            ///  Pointer to the resolvable address
+            ADDRPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to the resolvable address (6-bytes)
+                ADDRPTR: u32,
+            }),
+            ///  Pointer to data area used for temporary storage
+            SCRATCHPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved.
+                SCRATCHPTR: u32,
+            }),
+        };
+
+        ///  AES CCM Mode Encryption
+        pub const CCM = extern struct {
+            ///  Start generation of key-stream. This operation will stop by itself when completed.
+            TASKS_KSGEN: mmio.Mmio(packed struct(u32) {
+                ///  Start generation of key-stream. This operation will stop by itself when completed.
+                TASKS_KSGEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Start encryption/decryption. This operation will stop by itself when completed.
+            TASKS_CRYPT: mmio.Mmio(packed struct(u32) {
+                ///  Start encryption/decryption. This operation will stop by itself when completed.
+                TASKS_CRYPT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop encryption/decryption
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop encryption/decryption
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption
+            TASKS_RATEOVERRIDE: mmio.Mmio(packed struct(u32) {
+                ///  Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption
+                TASKS_RATEOVERRIDE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [240]u8,
+            ///  Key-stream generation complete
+            EVENTS_ENDKSGEN: mmio.Mmio(packed struct(u32) {
+                ///  Key-stream generation complete
+                EVENTS_ENDKSGEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Encrypt/decrypt complete
+            EVENTS_ENDCRYPT: mmio.Mmio(packed struct(u32) {
+                ///  Encrypt/decrypt complete
+                EVENTS_ENDCRYPT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Deprecated register - CCM error event
+            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
+                ///  Deprecated field - CCM error event
+                EVENTS_ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [244]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between event ENDKSGEN and task CRYPT
+                ENDKSGEN_CRYPT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event ENDKSGEN
+                ENDKSGEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ENDCRYPT
+                ENDCRYPT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Deprecated intsetfield - Write '1' to enable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event ENDKSGEN
+                ENDKSGEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ENDCRYPT
+                ENDCRYPT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Deprecated intclrfield - Write '1' to disable interrupt for event ERROR
+                ERROR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1024: [244]u8,
+            ///  MIC check result
+            MICSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  The result of the MIC check performed during the previous decryption operation
+                MICSTATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  MIC check failed
+                        CheckFailed = 0x0,
+                        ///  MIC check passed
+                        CheckPassed = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1280: [252]u8,
+            ///  Enable
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable CCM
+                ENABLE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Operation mode
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered.
+                MODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  AES CCM packet encryption mode
+                        Encryption = 0x0,
+                        ///  AES CCM packet decryption mode
+                        Decryption = 0x1,
+                    },
+                },
+                reserved16: u15,
+                ///  Radio data rate that the CCM shall run synchronous with
+                DATARATE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  1 Mbps
+                        @"1Mbit" = 0x0,
+                        ///  2 Mbps
+                        @"2Mbit" = 0x1,
+                        ///  125 Kbps
+                        @"125Kbps" = 0x2,
+                        ///  500 Kbps
+                        @"500Kbps" = 0x3,
+                    },
+                },
+                reserved24: u6,
+                ///  Packet length configuration
+                LENGTH: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated.
+                        Default = 0x0,
+                        ///  Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated.
+                        Extended = 0x1,
+                    },
+                },
+                padding: u7,
+            }),
+            ///  Pointer to data structure holding AES key and NONCE vector
+            CNFPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)
+                CNFPTR: u32,
+            }),
+            ///  Input pointer
+            INPTR: mmio.Mmio(packed struct(u32) {
+                ///  Input pointer
+                INPTR: u32,
+            }),
+            ///  Output pointer
+            OUTPTR: mmio.Mmio(packed struct(u32) {
+                ///  Output pointer
+                OUTPTR: u32,
+            }),
+            ///  Pointer to data area used for temporary storage
+            SCRATCHPTR: mmio.Mmio(packed struct(u32) {
+                ///  Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.
+                SCRATCHPTR: u32,
+            }),
+            ///  Length of key-stream generated when MODE.LENGTH = Extended.
+            MAXPACKETSIZE: mmio.Mmio(packed struct(u32) {
+                ///  Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted.
+                MAXPACKETSIZE: u8,
+                padding: u24,
+            }),
+            ///  Data rate override setting.
+            RATEOVERRIDE: mmio.Mmio(packed struct(u32) {
+                ///  Data rate override setting.
+                RATEOVERRIDE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  1 Mbps
+                        @"1Mbit" = 0x0,
+                        ///  2 Mbps
+                        @"2Mbit" = 0x1,
+                        ///  125 Kbps
+                        @"125Kbps" = 0x2,
+                        ///  500 Kbps
+                        @"500Kbps" = 0x3,
+                    },
+                },
+                padding: u30,
+            }),
+        };
+
+        ///  Watchdog Timer
+        pub const WDT = extern struct {
+            ///  Start the watchdog
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Start the watchdog
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [252]u8,
+            ///  Watchdog timeout
+            EVENTS_TIMEOUT: mmio.Mmio(packed struct(u32) {
+                ///  Watchdog timeout
+                EVENTS_TIMEOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved772: [512]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event TIMEOUT
+                TIMEOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event TIMEOUT
+                TIMEOUT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1024: [244]u8,
+            ///  Run status
+            RUNSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  Indicates whether or not the watchdog is running
+                RUNSTATUS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Watchdog not running
+                        NotRunning = 0x0,
+                        ///  Watchdog is running
+                        Running = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Request status
+            REQSTATUS: mmio.Mmio(packed struct(u32) {
+                ///  Request status for RR[0] register
+                RR0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[0] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[0] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[1] register
+                RR1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[1] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[1] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[2] register
+                RR2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[2] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[2] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[3] register
+                RR3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[3] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[3] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[4] register
+                RR4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[4] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[4] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[5] register
+                RR5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[5] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[5] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[6] register
+                RR6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[6] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[6] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                ///  Request status for RR[7] register
+                RR7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RR[7] register is not enabled, or are already requesting reload
+                        DisabledOrRequested = 0x0,
+                        ///  RR[7] register is enabled, and are not yet requesting reload
+                        EnabledAndUnrequested = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            reserved1284: [252]u8,
+            ///  Counter reload value
+            CRV: mmio.Mmio(packed struct(u32) {
+                ///  Counter reload value in number of cycles of the 32.768 kHz clock
+                CRV: u32,
+            }),
+            ///  Enable register for reload request registers
+            RREN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable RR[0] register
+                RR0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[0] register
+                        Disabled = 0x0,
+                        ///  Enable RR[0] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[1] register
+                RR1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[1] register
+                        Disabled = 0x0,
+                        ///  Enable RR[1] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[2] register
+                RR2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[2] register
+                        Disabled = 0x0,
+                        ///  Enable RR[2] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[3] register
+                RR3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[3] register
+                        Disabled = 0x0,
+                        ///  Enable RR[3] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[4] register
+                RR4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[4] register
+                        Disabled = 0x0,
+                        ///  Enable RR[4] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[5] register
+                RR5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[5] register
+                        Disabled = 0x0,
+                        ///  Enable RR[5] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[6] register
+                RR6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[6] register
+                        Disabled = 0x0,
+                        ///  Enable RR[6] register
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable RR[7] register
+                RR7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable RR[7] register
+                        Disabled = 0x0,
+                        ///  Enable RR[7] register
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Configure the watchdog to either be paused, or kept running, while the CPU is sleeping
+                SLEEP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pause watchdog while the CPU is sleeping
+                        Pause = 0x0,
+                        ///  Keep the watchdog running while the CPU is sleeping
+                        Run = 0x1,
+                    },
+                },
+                reserved3: u2,
+                ///  Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger
+                HALT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Pause watchdog while the CPU is halted by the debugger
+                        Pause = 0x0,
+                        ///  Keep the watchdog running while the CPU is halted by the debugger
+                        Run = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1536: [240]u8,
+            ///  Description collection: Reload request n
+            RR: [8]mmio.Mmio(packed struct(u32) {
+                ///  Reload request register
+                RR: packed union {
+                    raw: u32,
+                    value: enum(u32) {
+                        ///  Value to request a reload of the watchdog timer
+                        Reload = 0x6e524635,
+                        _,
+                    },
+                },
+            }),
+        };
+
+        ///  Memory Watch Unit
+        pub const MWU = extern struct {
+            reserved768: [768]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for event REGION0WA
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION0RA
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION1WA
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION1RA
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION2WA
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION2RA
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION3WA
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION3RA
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Enable or disable interrupt for event PREGION0WA
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event PREGION0RA
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event PREGION1WA
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event PREGION1RA
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event REGION0WA
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION0RA
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION1WA
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION1RA
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION2WA
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION2RA
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION3WA
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION3RA
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Write '1' to enable interrupt for event PREGION0WA
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event PREGION0RA
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event PREGION1WA
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event PREGION1RA
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event REGION0WA
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION0RA
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION1WA
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION1RA
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION2WA
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION2RA
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION3WA
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION3RA
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Write '1' to disable interrupt for event PREGION0WA
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event PREGION0RA
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event PREGION1WA
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event PREGION1RA
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            reserved800: [20]u8,
+            ///  Enable or disable interrupt
+            NMIEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for event REGION0WA
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION0RA
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION1WA
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION1RA
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION2WA
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION2RA
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION3WA
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event REGION3RA
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Enable or disable interrupt for event PREGION0WA
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event PREGION0RA
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event PREGION1WA
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event PREGION1RA
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Enable interrupt
+            NMIENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event REGION0WA
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION0RA
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION1WA
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION1RA
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION2WA
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION2RA
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION3WA
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REGION3RA
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Write '1' to enable interrupt for event PREGION0WA
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event PREGION0RA
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event PREGION1WA
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event PREGION1RA
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Disable interrupt
+            NMIENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event REGION0WA
+                REGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION0RA
+                REGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION1WA
+                REGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION1RA
+                REGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION2WA
+                REGION2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION2RA
+                REGION2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION3WA
+                REGION3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REGION3RA
+                REGION3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Write '1' to disable interrupt for event PREGION0WA
+                PREGION0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event PREGION0RA
+                PREGION0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event PREGION1WA
+                PREGION1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event PREGION1RA
+                PREGION1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            reserved1296: [484]u8,
+            ///  Enable/disable regions watch
+            REGIONEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable/disable write access watch in region[0]
+                RGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this region
+                        Disable = 0x0,
+                        ///  Enable write access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in region[0]
+                RGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this region
+                        Disable = 0x0,
+                        ///  Enable read access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable write access watch in region[1]
+                RGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this region
+                        Disable = 0x0,
+                        ///  Enable write access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in region[1]
+                RGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this region
+                        Disable = 0x0,
+                        ///  Enable read access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable write access watch in region[2]
+                RGN2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this region
+                        Disable = 0x0,
+                        ///  Enable write access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in region[2]
+                RGN2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this region
+                        Disable = 0x0,
+                        ///  Enable read access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable write access watch in region[3]
+                RGN3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this region
+                        Disable = 0x0,
+                        ///  Enable write access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in region[3]
+                RGN3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this region
+                        Disable = 0x0,
+                        ///  Enable read access watch in this region
+                        Enable = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Enable/disable write access watch in PREGION[0]
+                PRGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this PREGION
+                        Disable = 0x0,
+                        ///  Enable write access watch in this PREGION
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in PREGION[0]
+                PRGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this PREGION
+                        Disable = 0x0,
+                        ///  Enable read access watch in this PREGION
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable write access watch in PREGION[1]
+                PRGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable write access watch in this PREGION
+                        Disable = 0x0,
+                        ///  Enable write access watch in this PREGION
+                        Enable = 0x1,
+                    },
+                },
+                ///  Enable/disable read access watch in PREGION[1]
+                PRGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable read access watch in this PREGION
+                        Disable = 0x0,
+                        ///  Enable read access watch in this PREGION
+                        Enable = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Enable regions watch
+            REGIONENSET: mmio.Mmio(packed struct(u32) {
+                ///  Enable write access watch in region[0]
+                RGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in region[0]
+                RGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable write access watch in region[1]
+                RGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in region[1]
+                RGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable write access watch in region[2]
+                RGN2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in region[2]
+                RGN2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable write access watch in region[3]
+                RGN3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in region[3]
+                RGN3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Enable write access watch in PREGION[0]
+                PRGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in PREGION[0]
+                PRGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable write access watch in PREGION[1]
+                PRGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable read access watch in PREGION[1]
+                PRGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+            ///  Disable regions watch
+            REGIONENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Disable write access watch in region[0]
+                RGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in region[0]
+                RGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable write access watch in region[1]
+                RGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in region[1]
+                RGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable write access watch in region[2]
+                RGN2WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in region[2]
+                RGN2RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable write access watch in region[3]
+                RGN3WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in region[3]
+                RGN3RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this region is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this region is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                reserved24: u16,
+                ///  Disable write access watch in PREGION[0]
+                PRGN0WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in PREGION[0]
+                PRGN0RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable write access watch in PREGION[1]
+                PRGN1WA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Write access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Write access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Disable read access watch in PREGION[1]
+                PRGN1RA: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read access watch in this PREGION is disabled
+                        Disabled = 0x0,
+                        ///  Read access watch in this PREGION is enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u4,
+            }),
+        };
+
+        ///  Quadrature Decoder
+        pub const QDEC = extern struct {
+            ///  Task starting the quadrature decoder
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Task starting the quadrature decoder
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Task stopping the quadrature decoder
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Task stopping the quadrature decoder
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Read and clear ACC and ACCDBL
+            TASKS_READCLRACC: mmio.Mmio(packed struct(u32) {
+                ///  Read and clear ACC and ACCDBL
+                TASKS_READCLRACC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Read and clear ACC
+            TASKS_RDCLRACC: mmio.Mmio(packed struct(u32) {
+                ///  Read and clear ACC
+                TASKS_RDCLRACC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Read and clear ACCDBL
+            TASKS_RDCLRDBL: mmio.Mmio(packed struct(u32) {
+                ///  Read and clear ACCDBL
+                TASKS_RDCLRDBL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [236]u8,
+            ///  Event being generated for every new sample value written to the SAMPLE register
+            EVENTS_SAMPLERDY: mmio.Mmio(packed struct(u32) {
+                ///  Event being generated for every new sample value written to the SAMPLE register
+                EVENTS_SAMPLERDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Non-null report ready
+            EVENTS_REPORTRDY: mmio.Mmio(packed struct(u32) {
+                ///  Non-null report ready
+                EVENTS_REPORTRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  ACC or ACCDBL register overflow
+            EVENTS_ACCOF: mmio.Mmio(packed struct(u32) {
+                ///  ACC or ACCDBL register overflow
+                EVENTS_ACCOF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Double displacement(s) detected
+            EVENTS_DBLRDY: mmio.Mmio(packed struct(u32) {
+                ///  Double displacement(s) detected
+                EVENTS_DBLRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  QDEC has been stopped
+            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
+                ///  QDEC has been stopped
+                EVENTS_STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [236]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between event REPORTRDY and task READCLRACC
+                REPORTRDY_READCLRACC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event SAMPLERDY and task STOP
+                SAMPLERDY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event REPORTRDY and task RDCLRACC
+                REPORTRDY_RDCLRACC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event REPORTRDY and task STOP
+                REPORTRDY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event DBLRDY and task RDCLRDBL
+                DBLRDY_RDCLRDBL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event DBLRDY and task STOP
+                DBLRDY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event SAMPLERDY and task READCLRACC
+                SAMPLERDY_READCLRACC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u25,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event SAMPLERDY
+                SAMPLERDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event REPORTRDY
+                REPORTRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event ACCOF
+                ACCOF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event DBLRDY
+                DBLRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event SAMPLERDY
+                SAMPLERDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event REPORTRDY
+                REPORTRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event ACCOF
+                ACCOF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event DBLRDY
+                DBLRDY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event STOPPED
+                STOPPED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved1280: [500]u8,
+            ///  Enable the quadrature decoder
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable the quadrature decoder
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  LED output pin polarity
+            LEDPOL: mmio.Mmio(packed struct(u32) {
+                ///  LED output pin polarity
+                LEDPOL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Led active on output pin low
+                        ActiveLow = 0x0,
+                        ///  Led active on output pin high
+                        ActiveHigh = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Sample period
+            SAMPLEPER: mmio.Mmio(packed struct(u32) {
+                ///  Sample period. The SAMPLE register will be updated for every new sample
+                SAMPLEPER: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  128 us
+                        @"128us" = 0x0,
+                        ///  256 us
+                        @"256us" = 0x1,
+                        ///  512 us
+                        @"512us" = 0x2,
+                        ///  1024 us
+                        @"1024us" = 0x3,
+                        ///  2048 us
+                        @"2048us" = 0x4,
+                        ///  4096 us
+                        @"4096us" = 0x5,
+                        ///  8192 us
+                        @"8192us" = 0x6,
+                        ///  16384 us
+                        @"16384us" = 0x7,
+                        ///  32768 us
+                        @"32ms" = 0x8,
+                        ///  65536 us
+                        @"65ms" = 0x9,
+                        ///  131072 us
+                        @"131ms" = 0xa,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Motion sample value
+            SAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  Last motion sample
+                SAMPLE: u32,
+            }),
+            ///  Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
+            REPORTPER: mmio.Mmio(packed struct(u32) {
+                ///  Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated
+                REPORTPER: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  10 samples / report
+                        @"10Smpl" = 0x0,
+                        ///  40 samples / report
+                        @"40Smpl" = 0x1,
+                        ///  80 samples / report
+                        @"80Smpl" = 0x2,
+                        ///  120 samples / report
+                        @"120Smpl" = 0x3,
+                        ///  160 samples / report
+                        @"160Smpl" = 0x4,
+                        ///  200 samples / report
+                        @"200Smpl" = 0x5,
+                        ///  240 samples / report
+                        @"240Smpl" = 0x6,
+                        ///  280 samples / report
+                        @"280Smpl" = 0x7,
+                        ///  1 sample / report
+                        @"1Smpl" = 0x8,
+                        _,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Register accumulating the valid transitions
+            ACC: mmio.Mmio(packed struct(u32) {
+                ///  Register accumulating all valid samples (not double transition) read from the SAMPLE register
+                ACC: u32,
+            }),
+            ///  Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
+            ACCREAD: mmio.Mmio(packed struct(u32) {
+                ///  Snapshot of the ACC register.
+                ACCREAD: u32,
+            }),
+            reserved1320: [12]u8,
+            ///  Enable input debounce filters
+            DBFEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable input debounce filters
+                DBFEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Debounce input filters disabled
+                        Disabled = 0x0,
+                        ///  Debounce input filters enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1344: [20]u8,
+            ///  Time period the LED is switched ON prior to sampling
+            LEDPRE: mmio.Mmio(packed struct(u32) {
+                ///  Period in us the LED is switched on prior to sampling
+                LEDPRE: u9,
+                padding: u23,
+            }),
+            ///  Register accumulating the number of detected double transitions
+            ACCDBL: mmio.Mmio(packed struct(u32) {
+                ///  Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).
+                ACCDBL: u4,
+                padding: u28,
+            }),
+            ///  Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
+            ACCDBLREAD: mmio.Mmio(packed struct(u32) {
+                ///  Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered.
+                ACCDBLREAD: u4,
+                padding: u28,
+            }),
+        };
+
+        ///  Comparator
+        pub const COMP = extern struct {
+            ///  Start comparator
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Start comparator
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop comparator
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop comparator
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Sample comparator value
+            TASKS_SAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  Sample comparator value
+                TASKS_SAMPLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [244]u8,
+            ///  COMP is ready and output is valid
+            EVENTS_READY: mmio.Mmio(packed struct(u32) {
+                ///  COMP is ready and output is valid
+                EVENTS_READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Downward crossing
+            EVENTS_DOWN: mmio.Mmio(packed struct(u32) {
+                ///  Downward crossing
+                EVENTS_DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Upward crossing
+            EVENTS_UP: mmio.Mmio(packed struct(u32) {
+                ///  Upward crossing
+                EVENTS_UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Downward or upward crossing
+            EVENTS_CROSS: mmio.Mmio(packed struct(u32) {
+                ///  Downward or upward crossing
+                EVENTS_CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [240]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between event READY and task SAMPLE
+                READY_SAMPLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event READY and task STOP
+                READY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event DOWN and task STOP
+                DOWN_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event UP and task STOP
+                UP_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event CROSS and task STOP
+                CROSS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved768: [252]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event DOWN
+                DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event UP
+                UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event CROSS
+                CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event DOWN
+                DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event UP
+                UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CROSS
+                CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event DOWN
+                DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event UP
+                UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CROSS
+                CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1024: [244]u8,
+            ///  Compare result
+            RESULT: mmio.Mmio(packed struct(u32) {
+                ///  Result of last compare. Decision point SAMPLE task.
+                RESULT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Input voltage is below the threshold (VIN+ < VIN-)
+                        Below = 0x0,
+                        ///  Input voltage is above the threshold (VIN+ > VIN-)
+                        Above = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1280: [252]u8,
+            ///  COMP enable
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable COMP
+                ENABLE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Pin select
+            PSEL: mmio.Mmio(packed struct(u32) {
+                ///  Analog pin select
+                PSEL: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  AIN0 selected as analog input
+                        AnalogInput0 = 0x0,
+                        ///  AIN1 selected as analog input
+                        AnalogInput1 = 0x1,
+                        ///  AIN2 selected as analog input
+                        AnalogInput2 = 0x2,
+                        ///  AIN3 selected as analog input
+                        AnalogInput3 = 0x3,
+                        ///  AIN4 selected as analog input
+                        AnalogInput4 = 0x4,
+                        ///  AIN5 selected as analog input
+                        AnalogInput5 = 0x5,
+                        ///  AIN6 selected as analog input
+                        AnalogInput6 = 0x6,
+                        ///  AIN7 selected as analog input
+                        AnalogInput7 = 0x7,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Reference source select for single-ended mode
+            REFSEL: mmio.Mmio(packed struct(u32) {
+                ///  Reference select
+                REFSEL: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  VREF = internal 1.2 V reference (VDD >= 1.7 V)
+                        Int1V2 = 0x0,
+                        ///  VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)
+                        Int1V8 = 0x1,
+                        ///  VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)
+                        Int2V4 = 0x2,
+                        ///  VREF = VDD
+                        VDD = 0x4,
+                        ///  VREF = AREF (VDD >= VREF >= AREFMIN)
+                        ARef = 0x5,
+                        _,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  External reference select
+            EXTREFSEL: mmio.Mmio(packed struct(u32) {
+                ///  External analog reference select
+                EXTREFSEL: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  Use AIN0 as external analog reference
+                        AnalogReference0 = 0x0,
+                        ///  Use AIN1 as external analog reference
+                        AnalogReference1 = 0x1,
+                        ///  Use AIN2 as external analog reference
+                        AnalogReference2 = 0x2,
+                        ///  Use AIN3 as external analog reference
+                        AnalogReference3 = 0x3,
+                        ///  Use AIN4 as external analog reference
+                        AnalogReference4 = 0x4,
+                        ///  Use AIN5 as external analog reference
+                        AnalogReference5 = 0x5,
+                        ///  Use AIN6 as external analog reference
+                        AnalogReference6 = 0x6,
+                        ///  Use AIN7 as external analog reference
+                        AnalogReference7 = 0x7,
+                    },
+                },
+                padding: u29,
+            }),
+            reserved1328: [32]u8,
+            ///  Threshold configuration for hysteresis unit
+            TH: mmio.Mmio(packed struct(u32) {
+                ///  VDOWN = (THDOWN+1)/64*VREF
+                THDOWN: u6,
+                reserved8: u2,
+                ///  VUP = (THUP+1)/64*VREF
+                THUP: u6,
+                padding: u18,
+            }),
+            ///  Mode configuration
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Speed and power modes
+                SP: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Low-power mode
+                        Low = 0x0,
+                        ///  Normal mode
+                        Normal = 0x1,
+                        ///  High-speed mode
+                        High = 0x2,
+                        _,
+                    },
+                },
+                reserved8: u6,
+                ///  Main operation modes
+                MAIN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Single-ended mode
+                        SE = 0x0,
+                        ///  Differential mode
+                        Diff = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            ///  Comparator hysteresis enable
+            HYST: mmio.Mmio(packed struct(u32) {
+                ///  Comparator hysteresis
+                HYST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Comparator hysteresis disabled
+                        NoHyst = 0x0,
+                        ///  Comparator hysteresis enabled
+                        Hyst50mV = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  Low Power Comparator
+        pub const LPCOMP = extern struct {
+            ///  Start comparator
+            TASKS_START: mmio.Mmio(packed struct(u32) {
+                ///  Start comparator
+                TASKS_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Stop comparator
+            TASKS_STOP: mmio.Mmio(packed struct(u32) {
+                ///  Stop comparator
+                TASKS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Sample comparator value
+            TASKS_SAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  Sample comparator value
+                TASKS_SAMPLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [244]u8,
+            ///  LPCOMP is ready and output is valid
+            EVENTS_READY: mmio.Mmio(packed struct(u32) {
+                ///  LPCOMP is ready and output is valid
+                EVENTS_READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Downward crossing
+            EVENTS_DOWN: mmio.Mmio(packed struct(u32) {
+                ///  Downward crossing
+                EVENTS_DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Upward crossing
+            EVENTS_UP: mmio.Mmio(packed struct(u32) {
+                ///  Upward crossing
+                EVENTS_UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Downward or upward crossing
+            EVENTS_CROSS: mmio.Mmio(packed struct(u32) {
+                ///  Downward or upward crossing
+                EVENTS_CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved512: [240]u8,
+            ///  Shortcuts between local events and tasks
+            SHORTS: mmio.Mmio(packed struct(u32) {
+                ///  Shortcut between event READY and task SAMPLE
+                READY_SAMPLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event READY and task STOP
+                READY_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event DOWN and task STOP
+                DOWN_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event UP and task STOP
+                UP_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Shortcut between event CROSS and task STOP
+                CROSS_STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable shortcut
+                        Disabled = 0x0,
+                        ///  Enable shortcut
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u27,
+            }),
+            reserved772: [256]u8,
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event DOWN
+                DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event UP
+                UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event CROSS
+                CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event READY
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event DOWN
+                DOWN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event UP
+                UP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event CROSS
+                CROSS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u28,
+            }),
+            reserved1024: [244]u8,
+            ///  Compare result
+            RESULT: mmio.Mmio(packed struct(u32) {
+                ///  Result of last compare. Decision point SAMPLE task.
+                RESULT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Input voltage is below the reference threshold (VIN+ < VIN-).
+                        Below = 0x0,
+                        ///  Input voltage is above the reference threshold (VIN+ > VIN-).
+                        Above = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1280: [252]u8,
+            ///  Enable LPCOMP
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable LPCOMP
+                ENABLE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Input pin select
+            PSEL: mmio.Mmio(packed struct(u32) {
+                ///  Analog pin select
+                PSEL: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        ///  AIN0 selected as analog input
+                        AnalogInput0 = 0x0,
+                        ///  AIN1 selected as analog input
+                        AnalogInput1 = 0x1,
+                        ///  AIN2 selected as analog input
+                        AnalogInput2 = 0x2,
+                        ///  AIN3 selected as analog input
+                        AnalogInput3 = 0x3,
+                        ///  AIN4 selected as analog input
+                        AnalogInput4 = 0x4,
+                        ///  AIN5 selected as analog input
+                        AnalogInput5 = 0x5,
+                        ///  AIN6 selected as analog input
+                        AnalogInput6 = 0x6,
+                        ///  AIN7 selected as analog input
+                        AnalogInput7 = 0x7,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  Reference select
+            REFSEL: mmio.Mmio(packed struct(u32) {
+                ///  Reference select
+                REFSEL: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  VDD * 1/8 selected as reference
+                        Ref1_8Vdd = 0x0,
+                        ///  VDD * 2/8 selected as reference
+                        Ref2_8Vdd = 0x1,
+                        ///  VDD * 3/8 selected as reference
+                        Ref3_8Vdd = 0x2,
+                        ///  VDD * 4/8 selected as reference
+                        Ref4_8Vdd = 0x3,
+                        ///  VDD * 5/8 selected as reference
+                        Ref5_8Vdd = 0x4,
+                        ///  VDD * 6/8 selected as reference
+                        Ref6_8Vdd = 0x5,
+                        ///  VDD * 7/8 selected as reference
+                        Ref7_8Vdd = 0x6,
+                        ///  External analog reference selected
+                        ARef = 0x7,
+                        ///  VDD * 1/16 selected as reference
+                        Ref1_16Vdd = 0x8,
+                        ///  VDD * 3/16 selected as reference
+                        Ref3_16Vdd = 0x9,
+                        ///  VDD * 5/16 selected as reference
+                        Ref5_16Vdd = 0xa,
+                        ///  VDD * 7/16 selected as reference
+                        Ref7_16Vdd = 0xb,
+                        ///  VDD * 9/16 selected as reference
+                        Ref9_16Vdd = 0xc,
+                        ///  VDD * 11/16 selected as reference
+                        Ref11_16Vdd = 0xd,
+                        ///  VDD * 13/16 selected as reference
+                        Ref13_16Vdd = 0xe,
+                        ///  VDD * 15/16 selected as reference
+                        Ref15_16Vdd = 0xf,
+                    },
+                },
+                padding: u28,
+            }),
+            ///  External reference select
+            EXTREFSEL: mmio.Mmio(packed struct(u32) {
+                ///  External analog reference select
+                EXTREFSEL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Use AIN0 as external analog reference
+                        AnalogReference0 = 0x0,
+                        ///  Use AIN1 as external analog reference
+                        AnalogReference1 = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1312: [16]u8,
+            ///  Analog detect configuration
+            ANADETECT: mmio.Mmio(packed struct(u32) {
+                ///  Analog detect configuration
+                ANADETECT: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Generate ANADETECT on crossing, both upward crossing and downward crossing
+                        Cross = 0x0,
+                        ///  Generate ANADETECT on upward crossing only
+                        Up = 0x1,
+                        ///  Generate ANADETECT on downward crossing only
+                        Down = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            reserved1336: [20]u8,
+            ///  Comparator hysteresis enable
+            HYST: mmio.Mmio(packed struct(u32) {
+                ///  Comparator hysteresis enable
+                HYST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Comparator hysteresis disabled
+                        Disabled = 0x0,
+                        ///  Comparator hysteresis enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+        };
+
+        ///  Event Generator Unit 0
+        pub const EGU0 = extern struct {
+            ///  Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event
+            TASKS_TRIGGER: [16]mmio.Mmio(packed struct(u32) {
+                ///  Trigger n for triggering the corresponding TRIGGERED[n] event
+                TASKS_TRIGGER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Trigger task
+                        Trigger = 0x1,
+                        _,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved256: [192]u8,
+            ///  Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task
+            EVENTS_TRIGGERED: [16]mmio.Mmio(packed struct(u32) {
+                ///  Event number n generated by triggering the corresponding TRIGGER[n] task
+                EVENTS_TRIGGERED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Event not generated
+                        NotGenerated = 0x0,
+                        ///  Event generated
+                        Generated = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved768: [448]u8,
+            ///  Enable or disable interrupt
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable interrupt for event TRIGGERED[0]
+                TRIGGERED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[1]
+                TRIGGERED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[2]
+                TRIGGERED2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[3]
+                TRIGGERED3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[4]
+                TRIGGERED4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[5]
+                TRIGGERED5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[6]
+                TRIGGERED6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[7]
+                TRIGGERED7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[8]
+                TRIGGERED8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[9]
+                TRIGGERED9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[10]
+                TRIGGERED10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[11]
+                TRIGGERED11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[12]
+                TRIGGERED12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[13]
+                TRIGGERED13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[14]
+                TRIGGERED14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable interrupt for event TRIGGERED[15]
+                TRIGGERED15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable
+                        Disabled = 0x0,
+                        ///  Enable
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u16,
+            }),
+            ///  Enable interrupt
+            INTENSET: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to enable interrupt for event TRIGGERED[0]
+                TRIGGERED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[1]
+                TRIGGERED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[2]
+                TRIGGERED2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[3]
+                TRIGGERED3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[4]
+                TRIGGERED4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[5]
+                TRIGGERED5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[6]
+                TRIGGERED6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[7]
+                TRIGGERED7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[8]
+                TRIGGERED8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[9]
+                TRIGGERED9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[10]
+                TRIGGERED10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[11]
+                TRIGGERED11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[12]
+                TRIGGERED12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[13]
+                TRIGGERED13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[14]
+                TRIGGERED14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to enable interrupt for event TRIGGERED[15]
+                TRIGGERED15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u16,
+            }),
+            ///  Disable interrupt
+            INTENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Write '1' to disable interrupt for event TRIGGERED[0]
+                TRIGGERED0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[1]
+                TRIGGERED1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[2]
+                TRIGGERED2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[3]
+                TRIGGERED3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[4]
+                TRIGGERED4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[5]
+                TRIGGERED5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[6]
+                TRIGGERED6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[7]
+                TRIGGERED7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[8]
+                TRIGGERED8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[9]
+                TRIGGERED9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[10]
+                TRIGGERED10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[11]
+                TRIGGERED11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[12]
+                TRIGGERED12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[13]
+                TRIGGERED13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[14]
+                TRIGGERED14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Write '1' to disable interrupt for event TRIGGERED[15]
+                TRIGGERED15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: Disabled
+                        Disabled = 0x0,
+                        ///  Read: Enabled
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u16,
+            }),
+        };
+
+        ///  Software interrupt 0
+        pub const SWI0 = extern struct {
+            ///  Unused.
+            UNUSED: u32,
+        };
+
+        ///  Programmable Peripheral Interconnect
+        pub const PPI = extern struct {
+            reserved1280: [1280]u8,
+            ///  Channel enable register
+            CHEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable or disable channel 0
+                CH0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 1
+                CH1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 2
+                CH2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 3
+                CH3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 4
+                CH4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 5
+                CH5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 6
+                CH6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 7
+                CH7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 8
+                CH8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 9
+                CH9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 10
+                CH10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 11
+                CH11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 12
+                CH12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 13
+                CH13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 14
+                CH14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 15
+                CH15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 16
+                CH16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 17
+                CH17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 18
+                CH18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 19
+                CH19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 20
+                CH20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 21
+                CH21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 22
+                CH22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 23
+                CH23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 24
+                CH24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 25
+                CH25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 26
+                CH26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 27
+                CH27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 28
+                CH28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 29
+                CH29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 30
+                CH30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Enable or disable channel 31
+                CH31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable channel
+                        Disabled = 0x0,
+                        ///  Enable channel
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            ///  Channel enable set register
+            CHENSET: mmio.Mmio(packed struct(u32) {
+                ///  Channel 0 enable set register. Writing '0' has no effect
+                CH0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 1 enable set register. Writing '0' has no effect
+                CH1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 2 enable set register. Writing '0' has no effect
+                CH2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 3 enable set register. Writing '0' has no effect
+                CH3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 4 enable set register. Writing '0' has no effect
+                CH4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 5 enable set register. Writing '0' has no effect
+                CH5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 6 enable set register. Writing '0' has no effect
+                CH6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 7 enable set register. Writing '0' has no effect
+                CH7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 8 enable set register. Writing '0' has no effect
+                CH8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 9 enable set register. Writing '0' has no effect
+                CH9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 10 enable set register. Writing '0' has no effect
+                CH10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 11 enable set register. Writing '0' has no effect
+                CH11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 12 enable set register. Writing '0' has no effect
+                CH12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 13 enable set register. Writing '0' has no effect
+                CH13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 14 enable set register. Writing '0' has no effect
+                CH14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 15 enable set register. Writing '0' has no effect
+                CH15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 16 enable set register. Writing '0' has no effect
+                CH16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 17 enable set register. Writing '0' has no effect
+                CH17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 18 enable set register. Writing '0' has no effect
+                CH18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 19 enable set register. Writing '0' has no effect
+                CH19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 20 enable set register. Writing '0' has no effect
+                CH20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 21 enable set register. Writing '0' has no effect
+                CH21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 22 enable set register. Writing '0' has no effect
+                CH22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 23 enable set register. Writing '0' has no effect
+                CH23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 24 enable set register. Writing '0' has no effect
+                CH24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 25 enable set register. Writing '0' has no effect
+                CH25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 26 enable set register. Writing '0' has no effect
+                CH26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 27 enable set register. Writing '0' has no effect
+                CH27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 28 enable set register. Writing '0' has no effect
+                CH28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 29 enable set register. Writing '0' has no effect
+                CH29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 30 enable set register. Writing '0' has no effect
+                CH30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 31 enable set register. Writing '0' has no effect
+                CH31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            ///  Channel enable clear register
+            CHENCLR: mmio.Mmio(packed struct(u32) {
+                ///  Channel 0 enable clear register. Writing '0' has no effect
+                CH0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 1 enable clear register. Writing '0' has no effect
+                CH1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 2 enable clear register. Writing '0' has no effect
+                CH2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 3 enable clear register. Writing '0' has no effect
+                CH3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 4 enable clear register. Writing '0' has no effect
+                CH4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 5 enable clear register. Writing '0' has no effect
+                CH5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 6 enable clear register. Writing '0' has no effect
+                CH6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 7 enable clear register. Writing '0' has no effect
+                CH7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 8 enable clear register. Writing '0' has no effect
+                CH8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 9 enable clear register. Writing '0' has no effect
+                CH9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 10 enable clear register. Writing '0' has no effect
+                CH10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 11 enable clear register. Writing '0' has no effect
+                CH11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 12 enable clear register. Writing '0' has no effect
+                CH12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 13 enable clear register. Writing '0' has no effect
+                CH13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 14 enable clear register. Writing '0' has no effect
+                CH14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 15 enable clear register. Writing '0' has no effect
+                CH15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 16 enable clear register. Writing '0' has no effect
+                CH16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 17 enable clear register. Writing '0' has no effect
+                CH17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 18 enable clear register. Writing '0' has no effect
+                CH18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 19 enable clear register. Writing '0' has no effect
+                CH19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 20 enable clear register. Writing '0' has no effect
+                CH20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 21 enable clear register. Writing '0' has no effect
+                CH21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 22 enable clear register. Writing '0' has no effect
+                CH22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 23 enable clear register. Writing '0' has no effect
+                CH23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 24 enable clear register. Writing '0' has no effect
+                CH24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 25 enable clear register. Writing '0' has no effect
+                CH25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 26 enable clear register. Writing '0' has no effect
+                CH26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 27 enable clear register. Writing '0' has no effect
+                CH27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 28 enable clear register. Writing '0' has no effect
+                CH28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 29 enable clear register. Writing '0' has no effect
+                CH29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 30 enable clear register. Writing '0' has no effect
+                CH30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+                ///  Channel 31 enable clear register. Writing '0' has no effect
+                CH31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Read: channel disabled
+                        Disabled = 0x0,
+                        ///  Read: channel enabled
+                        Enabled = 0x1,
+                    },
+                },
+            }),
+            reserved2048: [756]u8,
+            ///  Description collection: Channel group n
+            CHG: [6]mmio.Mmio(packed struct(u32) {
+                ///  Include or exclude channel 0
+                CH0: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 1
+                CH1: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 2
+                CH2: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 3
+                CH3: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 4
+                CH4: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 5
+                CH5: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 6
+                CH6: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 7
+                CH7: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 8
+                CH8: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 9
+                CH9: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 10
+                CH10: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 11
+                CH11: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 12
+                CH12: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 13
+                CH13: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 14
+                CH14: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 15
+                CH15: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 16
+                CH16: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 17
+                CH17: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 18
+                CH18: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 19
+                CH19: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 20
+                CH20: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 21
+                CH21: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 22
+                CH22: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 23
+                CH23: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 24
+                CH24: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 25
+                CH25: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 26
+                CH26: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 27
+                CH27: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 28
+                CH28: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 29
+                CH29: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 30
+                CH30: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+                ///  Include or exclude channel 31
+                CH31: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Exclude
+                        Excluded = 0x0,
+                        ///  Include
+                        Included = 0x1,
+                    },
+                },
+            }),
+        };
+
+        ///  Non Volatile Memory Controller
+        pub const NVMC = extern struct {
+            reserved1024: [1024]u8,
+            ///  Ready flag
+            READY: mmio.Mmio(packed struct(u32) {
+                ///  NVMC is ready or busy
+                READY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  NVMC is busy (on-going write or erase operation)
+                        Busy = 0x0,
+                        ///  NVMC is ready
+                        Ready = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1032: [4]u8,
+            ///  Ready flag
+            READYNEXT: mmio.Mmio(packed struct(u32) {
+                ///  NVMC can accept a new write operation
+                READYNEXT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  NVMC cannot accept any write operation
+                        Busy = 0x0,
+                        ///  NVMC is ready
+                        Ready = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            reserved1284: [248]u8,
+            ///  Configuration register
+            CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.
+                WEN: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Read only access
+                        Ren = 0x0,
+                        ///  Write enabled
+                        Wen = 0x1,
+                        ///  Erase enabled
+                        Een = 0x2,
+                        _,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  Register for erasing a page in code area
+            ERASEPAGE: mmio.Mmio(packed struct(u32) {
+                ///  Register for starting erase of a page in code area
+                ERASEPAGE: u32,
+            }),
+            ///  Register for erasing all non-volatile user memory
+            ERASEALL: mmio.Mmio(packed struct(u32) {
+                ///  Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.
+                ERASEALL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No operation
+                        NoOperation = 0x0,
+                        ///  Start chip erase
+                        Erase = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE.
+            ERASEPCR0: mmio.Mmio(packed struct(u32) {
+                ///  Register for starting erase of a page in code area. Equivalent to ERASEPAGE.
+                ERASEPCR0: u32,
+            }),
+            ///  Register for erasing user information configuration registers
+            ERASEUICR: mmio.Mmio(packed struct(u32) {
+                ///  Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.
+                ERASEUICR: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  No operation
+                        NoOperation = 0x0,
+                        ///  Start erase of UICR
+                        Erase = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Register for partial erase of a page in code area
+            ERASEPAGEPARTIAL: mmio.Mmio(packed struct(u32) {
+                ///  Register for starting partial erase of a page in code area
+                ERASEPAGEPARTIAL: u32,
+            }),
+            ///  Register for partial erase configuration
+            ERASEPAGEPARTIALCFG: mmio.Mmio(packed struct(u32) {
+                ///  Duration of the partial erase in milliseconds
+                DURATION: u7,
+                padding: u25,
+            }),
+            reserved1344: [32]u8,
+            ///  I-code cache configuration register.
+            ICACHECNF: mmio.Mmio(packed struct(u32) {
+                ///  Cache enable
+                CACHEEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable cache. Invalidates all cache entries.
+                        Disabled = 0x0,
+                        ///  Enable cache
+                        Enabled = 0x1,
+                    },
+                },
+                reserved8: u7,
+                ///  Cache profiling enable
+                CACHEPROFEN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disable cache profiling
+                        Disabled = 0x0,
+                        ///  Enable cache profiling
+                        Enabled = 0x1,
+                    },
+                },
+                padding: u23,
+            }),
+            reserved1352: [4]u8,
+            ///  I-code cache hit counter.
+            IHIT: mmio.Mmio(packed struct(u32) {
+                ///  Number of cache hits
+                HITS: u32,
+            }),
+            ///  I-code cache miss counter.
+            IMISS: mmio.Mmio(packed struct(u32) {
+                ///  Number of cache misses
+                MISSES: u32,
+            }),
+        };
+    };
+};
diff --git a/test/nrf52840.robot b/test/nrf52840.robot
new file mode 100644
index 000000000..28c77fe96
--- /dev/null
+++ b/test/nrf52840.robot
@@ -0,0 +1,10 @@
+*** Settings ***
+Suite Setup     Setup
+Suite Teardown  Teardown
+Test Teardown   Test Teardown
+Resource        ${RENODEKEYWORDS}
+
+*** Test Cases ***
+Should Print Help
+    ${x}=  Execute Command     help
+           Should Contain      ${x}    Available commands:
diff --git a/test/programs/minimal.zig b/test/programs/minimal.zig
new file mode 100644
index 000000000..5258ce311
--- /dev/null
+++ b/test/programs/minimal.zig
@@ -0,0 +1,5 @@
+const micro = @import("microzig");
+
+pub fn main() void {
+    // This function will contain the application logic.
+}

From 4eba908bd2e18bb23a3112d95013a65628bbecd1 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 18 Feb 2023 11:54:04 -0500
Subject: [PATCH 039/286] migrate code from microzig repo (#1)

* migrate code from microzig repo

* move robot file

* add microzig submodule

* add chips to build

* add buildkite pipeline

* try listing boards

* change board names

* revert pipeline
---
 .buildkite/pipeline.yml            |     6 +
 .gitignore                         |     2 +
 .gitmodules                        |     3 +
 README.adoc                        |     2 +-
 build.zig                          |    35 +
 deps/microzig                      |     1 +
 src/boards.zig                     |    35 +
 src/boards/STM3240G_EVAL.zig       |    10 +
 src/boards/STM32F3DISCOVERY.zig    |    37 +
 src/boards/STM32F429IDISCOVERY.zig |    12 +
 src/boards/STM32F4DISCOVERY.zig    |    14 +
 src/chips.zig                      |    48 +
 src/chips/STM32F103.json           | 27474 ++++++++++++++
 src/chips/STM32F103.zig            | 10854 ++++++
 src/chips/STM32F303.json           | 33184 +++++++++++++++++
 src/chips/STM32F303.zig            | 13076 +++++++
 src/chips/STM32F407.json           | 50953 ++++++++++++++++++++++++++
 src/chips/STM32F407.zig            | 20004 ++++++++++
 src/chips/STM32F429.json           | 52094 +++++++++++++++++++++++++++
 src/chips/STM32F429.zig            | 20419 +++++++++++
 src/hals/stm32f103.zig             |     0
 src/hals/stm32f303.zig             |   602 +
 src/hals/stm32f407.zig             |   623 +
 src/hals/stm32f429.zig             |    92 +
 test/programs/minimal.zig          |     5 +
 {tests => test}/stm32f103.robot    |     0
 26 files changed, 229584 insertions(+), 1 deletion(-)
 create mode 100644 .buildkite/pipeline.yml
 create mode 100644 .gitignore
 create mode 100644 .gitmodules
 create mode 100644 build.zig
 create mode 160000 deps/microzig
 create mode 100644 src/boards.zig
 create mode 100644 src/boards/STM3240G_EVAL.zig
 create mode 100644 src/boards/STM32F3DISCOVERY.zig
 create mode 100644 src/boards/STM32F429IDISCOVERY.zig
 create mode 100644 src/boards/STM32F4DISCOVERY.zig
 create mode 100644 src/chips.zig
 create mode 100644 src/chips/STM32F103.json
 create mode 100644 src/chips/STM32F103.zig
 create mode 100644 src/chips/STM32F303.json
 create mode 100644 src/chips/STM32F303.zig
 create mode 100644 src/chips/STM32F407.json
 create mode 100644 src/chips/STM32F407.zig
 create mode 100644 src/chips/STM32F429.json
 create mode 100644 src/chips/STM32F429.zig
 create mode 100644 src/hals/stm32f103.zig
 create mode 100644 src/hals/stm32f303.zig
 create mode 100644 src/hals/stm32f407.zig
 create mode 100644 src/hals/stm32f429.zig
 create mode 100644 test/programs/minimal.zig
 rename {tests => test}/stm32f103.robot (100%)

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
new file mode 100644
index 000000000..ad6d38054
--- /dev/null
+++ b/.buildkite/pipeline.yml
@@ -0,0 +1,6 @@
+steps:
+  - group: Build and Test
+    steps:
+    - command: zig build
+    - label: 🔨 Test
+      command: renode-test test/stm32f103.robot
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 000000000..4c82b07c0
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+zig-cache
+zig-out
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 000000000..32e895ccb
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "deps/microzig"]
+	path = deps/microzig
+	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/README.adoc b/README.adoc
index d3f2f4097..fdee92cc1 100644
--- a/README.adoc
+++ b/README.adoc
@@ -1,6 +1,6 @@
 = stm32
 
-HAL for stm32 (STMicro) devices
+HALs and register definitions for stm32 (STMicro) devices
 
 == stm32 boards that renode supports:
 
diff --git a/build.zig b/build.zig
new file mode 100644
index 000000000..3b787fe3f
--- /dev/null
+++ b/build.zig
@@ -0,0 +1,35 @@
+const std = @import("std");
+const microzig = @import("deps/microzig/src/main.zig");
+const boards = @import("src/boards.zig");
+const chips = @import("src/chips.zig");
+
+pub fn build(b: *std.build.Builder) void {
+    const optimize = b.standardOptimizeOption(.{});
+    inline for (@typeInfo(boards).Struct.decls) |decl| {
+        if (!decl.is_pub)
+            continue;
+
+        const exe = microzig.addEmbeddedExecutable(
+            b,
+            @field(boards, decl.name).name ++ ".minimal",
+            "test/programs/minimal.zig",
+            .{ .board = @field(boards, decl.name) },
+            .{ .optimize = optimize },
+        );
+        exe.install();
+    }
+
+    inline for (@typeInfo(chips).Struct.decls) |decl| {
+        if (!decl.is_pub)
+            continue;
+
+        const exe = microzig.addEmbeddedExecutable(
+            b,
+            @field(chips, decl.name).name ++ ".minimal",
+            "test/programs/minimal.zig",
+            .{ .chip = @field(chips, decl.name) },
+            .{ .optimize = optimize },
+        );
+        exe.install();
+    }
+}
diff --git a/deps/microzig b/deps/microzig
new file mode 160000
index 000000000..97ca5497d
--- /dev/null
+++ b/deps/microzig
@@ -0,0 +1 @@
+Subproject commit 97ca5497da0f22d025e18bced9311efed088d893
diff --git a/src/boards.zig b/src/boards.zig
new file mode 100644
index 000000000..13f4c6156
--- /dev/null
+++ b/src/boards.zig
@@ -0,0 +1,35 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/src/main.zig");
+const Board = microzig.Board;
+
+const chips = @import("chips.zig");
+
+fn root() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse unreachable;
+}
+
+const root_path = root() ++ "/";
+
+pub const stm32f3discovery = Board{
+    .name = "STM32F3DISCOVERY",
+    .source = .{ .path = root_path ++ "boards/STM32F3DISCOVERY.zig" },
+    .chip = chips.stm32f303vc,
+};
+
+pub const stm32f4discovery = Board{
+    .name = "STM32F4DISCOVERY",
+    .source = .{ .path = root_path ++ "boards/STM32F4DISCOVERY.zig" },
+    .chip = chips.stm32f407vg,
+};
+
+pub const stm3240geval = Board{
+    .name = "STM3240G_EVAL",
+    .source = .{ .path = root_path ++ "boards/STM3240G_EVAL.zig" },
+    .chip = chips.stm32f407vg,
+};
+
+pub const stm32f429idiscovery = Board{
+    .name = "STM32F429IDISCOVERY",
+    .source = .{ .path = root_path ++ "boards/STM32F429IDISCOVERY.zig" },
+    .chip = chips.stm32f429zit6u,
+};
diff --git a/src/boards/STM3240G_EVAL.zig b/src/boards/STM3240G_EVAL.zig
new file mode 100644
index 000000000..62611421a
--- /dev/null
+++ b/src/boards/STM3240G_EVAL.zig
@@ -0,0 +1,10 @@
+pub const pin_map = .{
+    // LD1 green
+    .LD1 = "PG6",
+    // LD2 orange
+    .LD2 = "PG8",
+    // LD3 red
+    .LD3 = "PI9",
+    // LD4 blue
+    .LD4 = "PC7",
+};
diff --git a/src/boards/STM32F3DISCOVERY.zig b/src/boards/STM32F3DISCOVERY.zig
new file mode 100644
index 000000000..9394bb8df
--- /dev/null
+++ b/src/boards/STM32F3DISCOVERY.zig
@@ -0,0 +1,37 @@
+pub const micro = @import("microzig");
+
+pub const cpu_frequency = 8_000_000;
+
+pub const pin_map = .{
+    // circle of LEDs, connected to GPIOE bits 8..15
+
+    // NW blue
+    .LD4 = "PE8",
+    // N red
+    .LD3 = "PE9",
+    // NE orange
+    .LD5 = "PE10",
+    // E green
+    .LD7 = "PE11",
+    // SE blue
+    .LD9 = "PE12",
+    // S red
+    .LD10 = "PE13",
+    // SW orange
+    .LD8 = "PE14",
+    // W green
+    .LD6 = "PE15",
+};
+
+pub fn debug_write(string: []const u8) void {
+    const uart1 = micro.core.experimental.Uart(1, .{}).get_or_init(.{
+        .baud_rate = 9600,
+        .data_bits = .eight,
+        .parity = null,
+        .stop_bits = .one,
+    }) catch unreachable;
+
+    const writer = uart1.writer();
+    _ = writer.write(string) catch unreachable;
+    uart1.internal.txflush();
+}
diff --git a/src/boards/STM32F429IDISCOVERY.zig b/src/boards/STM32F429IDISCOVERY.zig
new file mode 100644
index 000000000..034295a13
--- /dev/null
+++ b/src/boards/STM32F429IDISCOVERY.zig
@@ -0,0 +1,12 @@
+pub const cpu_frequency = 16_000_000;
+
+pub const pin_map = .{
+    // LEDs, connected to GPIOG bits 13, 14
+    // green
+    .LD3 = "PG13",
+    // red
+    .LD4 = "PG14",
+
+    // User button
+    .B1 = "PA0",
+};
diff --git a/src/boards/STM32F4DISCOVERY.zig b/src/boards/STM32F4DISCOVERY.zig
new file mode 100644
index 000000000..062f334af
--- /dev/null
+++ b/src/boards/STM32F4DISCOVERY.zig
@@ -0,0 +1,14 @@
+pub const pin_map = .{
+    // LED cross, connected to GPIOD bits 12..15
+    // N orange
+    .LD3 = "PD13",
+    // E red
+    .LD5 = "PD14",
+    // S blue
+    .LD6 = "PD15",
+    // W green
+    .LD4 = "PD12",
+
+    // User button
+    .B2 = "PA0",
+};
diff --git a/src/chips.zig b/src/chips.zig
new file mode 100644
index 000000000..c492323bf
--- /dev/null
+++ b/src/chips.zig
@@ -0,0 +1,48 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/src/main.zig");
+const Chip = microzig.Chip;
+const MemoryRegion = microzig.MemoryRegion;
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse ".";
+}
+
+pub const stm32f103x8 = Chip.from_standard_paths(root_dir(), .{
+    .name = "STM32F103",
+    .cpu = microzig.cpus.cortex_m3,
+    .memory_regions = &.{
+        MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash },
+        MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram },
+    },
+});
+
+pub const stm32f303vc = Chip.from_standard_paths(root_dir(), .{
+    .name = "STM32F303",
+    .cpu = microzig.cpus.cortex_m4,
+    .memory_regions = &.{
+        MemoryRegion{ .offset = 0x08000000, .length = 256 * 1024, .kind = .flash },
+        MemoryRegion{ .offset = 0x20000000, .length = 40 * 1024, .kind = .ram },
+    },
+});
+
+pub const stm32f407vg = Chip.from_standard_paths(root_dir(), .{
+    .name = "STM32F407",
+    .cpu = microzig.cpus.cortex_m4,
+    .memory_regions = &.{
+        MemoryRegion{ .offset = 0x08000000, .length = 1024 * 1024, .kind = .flash },
+        MemoryRegion{ .offset = 0x20000000, .length = 128 * 1024, .kind = .ram },
+        // CCM RAM
+        MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram },
+    },
+});
+
+pub const stm32f429zit6u = Chip.from_standard_paths(root_dir(), .{
+    .name = "STM32F429",
+    .cpu = microzig.cpus.cortex_m4,
+    .memory_regions = &.{
+        MemoryRegion{ .offset = 0x08000000, .length = 2048 * 1024, .kind = .flash },
+        MemoryRegion{ .offset = 0x20000000, .length = 192 * 1024, .kind = .ram },
+        // CCM RAM
+        MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram },
+    },
+});
diff --git a/src/chips/STM32F103.json b/src/chips/STM32F103.json
new file mode 100644
index 000000000..45b99d177
--- /dev/null
+++ b/src/chips/STM32F103.json
@@ -0,0 +1,27474 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "FSMC": {
+        "description": "Flexible static memory controller",
+        "children": {
+          "registers": {
+            "BCR1": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR1": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR2": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          2",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR2": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR3": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          3",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR3": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR4": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          4",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR4": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          4",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "PCR2": {
+              "description": "PC Card/NAND Flash control register\n          2",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR2": {
+              "description": "FIFO status and interrupt register\n          2",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM2": {
+              "description": "Common memory space timing register\n          2",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT2": {
+              "description": "Attribute memory space timing register\n          2",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "Attribute memory x databus HiZ\n              time",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "Attribute memory x hold\n              time",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "Attribute memory x wait\n              time",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "Attribute memory x setup\n              time",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ECCR2": {
+              "description": "ECC result register 2",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ECCx": {
+                    "description": "ECC result",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PCR3": {
+              "description": "PC Card/NAND Flash control register\n          3",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR3": {
+              "description": "FIFO status and interrupt register\n          3",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM3": {
+              "description": "Common memory space timing register\n          3",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT3": {
+              "description": "Attribute memory space timing register\n          3",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "ATTHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "ATTHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "ATTWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "ATTSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ECCR3": {
+              "description": "ECC result register 3",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ECCx": {
+                    "description": "ECCx",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PCR4": {
+              "description": "PC Card/NAND Flash control register\n          4",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR4": {
+              "description": "FIFO status and interrupt register\n          4",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM4": {
+              "description": "Common memory space timing register\n          4",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT4": {
+              "description": "Attribute memory space timing register\n          4",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "ATTHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "ATTHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "ATTWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "ATTSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PIO4": {
+              "description": "I/O space timing register 4",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOHIZx": {
+                    "description": "IOHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "IOHOLDx": {
+                    "description": "IOHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IOWAITx": {
+                    "description": "IOWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IOSETx": {
+                    "description": "IOSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BWTR1": {
+              "description": "SRAM/NOR-Flash write timing registers\n          1",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR2": {
+              "description": "SRAM/NOR-Flash write timing registers\n          2",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR3": {
+              "description": "SRAM/NOR-Flash write timing registers\n          3",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR4": {
+              "description": "SRAM/NOR-Flash write timing registers\n          4",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PWR": {
+        "description": "Power control",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "Power control register\n          (PWR_CR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LPDS": {
+                    "description": "Low Power Deep Sleep",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PDDS": {
+                    "description": "Power Down Deep Sleep",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CWUF": {
+                    "description": "Clear Wake-up Flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CSBF": {
+                    "description": "Clear STANDBY Flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PVDE": {
+                    "description": "Power Voltage Detector\n              Enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PLS": {
+                    "description": "PVD Level Selection",
+                    "offset": 5,
+                    "size": 3
+                  },
+                  "DBP": {
+                    "description": "Disable Backup Domain write\n              protection",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CSR": {
+              "description": "Power control register\n          (PWR_CR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WUF": {
+                    "description": "Wake-Up Flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SBF": {
+                    "description": "STANDBY Flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PVDO": {
+                    "description": "PVD Output",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EWUP": {
+                    "description": "Enable WKUP pin",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RCC": {
+        "description": "Reset and clock control",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "Clock control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 131,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HSION": {
+                    "description": "Internal High Speed clock\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HSIRDY": {
+                    "description": "Internal High Speed clock ready\n              flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSITRIM": {
+                    "description": "Internal High Speed clock\n              trimming",
+                    "offset": 3,
+                    "size": 5
+                  },
+                  "HSICAL": {
+                    "description": "Internal High Speed clock\n              Calibration",
+                    "offset": 8,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "HSEON": {
+                    "description": "External High Speed clock\n              enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "HSERDY": {
+                    "description": "External High Speed clock ready\n              flag",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSEBYP": {
+                    "description": "External High Speed clock\n              Bypass",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CSSON": {
+                    "description": "Clock Security System\n              enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PLLON": {
+                    "description": "PLL enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PLLRDY": {
+                    "description": "PLL clock ready flag",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CFGR": {
+              "description": "Clock configuration register\n          (RCC_CFGR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SW": {
+                    "description": "System clock Switch",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SWS": {
+                    "description": "System Clock Switch Status",
+                    "offset": 2,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "HPRE": {
+                    "description": "AHB prescaler",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "PPRE1": {
+                    "description": "APB Low speed prescaler\n              (APB1)",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "PPRE2": {
+                    "description": "APB High speed prescaler\n              (APB2)",
+                    "offset": 11,
+                    "size": 3
+                  },
+                  "ADCPRE": {
+                    "description": "ADC prescaler",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "PLLSRC": {
+                    "description": "PLL entry clock source",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PLLXTPRE": {
+                    "description": "HSE divider for PLL entry",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PLLMUL": {
+                    "description": "PLL Multiplication Factor",
+                    "offset": 18,
+                    "size": 4
+                  },
+                  "OTGFSPRE": {
+                    "description": "USB OTG FS prescaler",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "MCO": {
+                    "description": "Microcontroller clock\n              output",
+                    "offset": 24,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "CIR": {
+              "description": "Clock interrupt register\n          (RCC_CIR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSIRDYF": {
+                    "description": "LSI Ready Interrupt flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSERDYF": {
+                    "description": "LSE Ready Interrupt flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSIRDYF": {
+                    "description": "HSI Ready Interrupt flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSERDYF": {
+                    "description": "HSE Ready Interrupt flag",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLLRDYF": {
+                    "description": "PLL Ready Interrupt flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CSSF": {
+                    "description": "Clock Security System Interrupt\n              flag",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSIRDYIE": {
+                    "description": "LSI Ready Interrupt Enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LSERDYIE": {
+                    "description": "LSE Ready Interrupt Enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HSIRDYIE": {
+                    "description": "HSI Ready Interrupt Enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "HSERDYIE": {
+                    "description": "HSE Ready Interrupt Enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PLLRDYIE": {
+                    "description": "PLL Ready Interrupt Enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LSIRDYC": {
+                    "description": "LSI Ready Interrupt Clear",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSERDYC": {
+                    "description": "LSE Ready Interrupt Clear",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "HSIRDYC": {
+                    "description": "HSI Ready Interrupt Clear",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "HSERDYC": {
+                    "description": "HSE Ready Interrupt Clear",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PLLRDYC": {
+                    "description": "PLL Ready Interrupt Clear",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CSSC": {
+                    "description": "Clock security system interrupt\n              clear",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "APB2RSTR": {
+              "description": "APB2 peripheral reset register\n          (RCC_APB2RSTR)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFIORST": {
+                    "description": "Alternate function I/O\n              reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IOPARST": {
+                    "description": "IO port A reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IOPBRST": {
+                    "description": "IO port B reset",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IOPCRST": {
+                    "description": "IO port C reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IOPDRST": {
+                    "description": "IO port D reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IOPERST": {
+                    "description": "IO port E reset",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IOPFRST": {
+                    "description": "IO port F reset",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IOPGRST": {
+                    "description": "IO port G reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ADC1RST": {
+                    "description": "ADC 1 interface reset",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ADC2RST": {
+                    "description": "ADC 2 interface reset",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TIM1RST": {
+                    "description": "TIM1 timer reset",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI1RST": {
+                    "description": "SPI 1 reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIM8RST": {
+                    "description": "TIM8 timer reset",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "USART1RST": {
+                    "description": "USART1 reset",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ADC3RST": {
+                    "description": "ADC 3 interface reset",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TIM9RST": {
+                    "description": "TIM9 timer reset",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TIM10RST": {
+                    "description": "TIM10 timer reset",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TIM11RST": {
+                    "description": "TIM11 timer reset",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1RSTR": {
+              "description": "APB1 peripheral reset register\n          (RCC_APB1RSTR)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM2RST": {
+                    "description": "Timer 2 reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM3RST": {
+                    "description": "Timer 3 reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM4RST": {
+                    "description": "Timer 4 reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIM5RST": {
+                    "description": "Timer 5 reset",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TIM6RST": {
+                    "description": "Timer 6 reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM7RST": {
+                    "description": "Timer 7 reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIM12RST": {
+                    "description": "Timer 12 reset",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TIM13RST": {
+                    "description": "Timer 13 reset",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIM14RST": {
+                    "description": "Timer 14 reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WWDGRST": {
+                    "description": "Window watchdog reset",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI2RST": {
+                    "description": "SPI2 reset",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI3RST": {
+                    "description": "SPI3 reset",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "USART2RST": {
+                    "description": "USART 2 reset",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USART3RST": {
+                    "description": "USART 3 reset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "UART4RST": {
+                    "description": "UART 4 reset",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UART5RST": {
+                    "description": "UART 5 reset",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2C1RST": {
+                    "description": "I2C1 reset",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "I2C2RST": {
+                    "description": "I2C2 reset",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CANRST": {
+                    "description": "CAN reset",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "BKPRST": {
+                    "description": "Backup interface reset",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PWRRST": {
+                    "description": "Power interface reset",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DACRST": {
+                    "description": "DAC interface reset",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHBENR": {
+              "description": "AHB Peripheral Clock enable register\n          (RCC_AHBENR)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 20,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA1EN": {
+                    "description": "DMA1 clock enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMA2EN": {
+                    "description": "DMA2 clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SRAMEN": {
+                    "description": "SRAM interface clock\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FLITFEN": {
+                    "description": "FLITF clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CRCEN": {
+                    "description": "CRC clock enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FSMCEN": {
+                    "description": "FSMC clock enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SDIOEN": {
+                    "description": "SDIO clock enable",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB2ENR": {
+              "description": "APB2 peripheral clock enable register\n          (RCC_APB2ENR)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFIOEN": {
+                    "description": "Alternate function I/O clock\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IOPAEN": {
+                    "description": "I/O port A clock enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IOPBEN": {
+                    "description": "I/O port B clock enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IOPCEN": {
+                    "description": "I/O port C clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IOPDEN": {
+                    "description": "I/O port D clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IOPEEN": {
+                    "description": "I/O port E clock enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IOPFEN": {
+                    "description": "I/O port F clock enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IOPGEN": {
+                    "description": "I/O port G clock enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ADC1EN": {
+                    "description": "ADC 1 interface clock\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ADC2EN": {
+                    "description": "ADC 2 interface clock\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TIM1EN": {
+                    "description": "TIM1 Timer clock enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI1EN": {
+                    "description": "SPI 1 clock enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIM8EN": {
+                    "description": "TIM8 Timer clock enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "USART1EN": {
+                    "description": "USART1 clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ADC3EN": {
+                    "description": "ADC3 interface clock\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TIM9EN": {
+                    "description": "TIM9 Timer clock enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TIM10EN": {
+                    "description": "TIM10 Timer clock enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TIM11EN": {
+                    "description": "TIM11 Timer clock enable",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1ENR": {
+              "description": "APB1 peripheral clock enable register\n          (RCC_APB1ENR)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM2EN": {
+                    "description": "Timer 2 clock enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM3EN": {
+                    "description": "Timer 3 clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM4EN": {
+                    "description": "Timer 4 clock enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIM5EN": {
+                    "description": "Timer 5 clock enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TIM6EN": {
+                    "description": "Timer 6 clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM7EN": {
+                    "description": "Timer 7 clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIM12EN": {
+                    "description": "Timer 12 clock enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TIM13EN": {
+                    "description": "Timer 13 clock enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIM14EN": {
+                    "description": "Timer 14 clock enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WWDGEN": {
+                    "description": "Window watchdog clock\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI2EN": {
+                    "description": "SPI 2 clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI3EN": {
+                    "description": "SPI 3 clock enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "USART2EN": {
+                    "description": "USART 2 clock enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USART3EN": {
+                    "description": "USART 3 clock enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "UART4EN": {
+                    "description": "UART 4 clock enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UART5EN": {
+                    "description": "UART 5 clock enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2C1EN": {
+                    "description": "I2C 1 clock enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "I2C2EN": {
+                    "description": "I2C 2 clock enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "USBEN": {
+                    "description": "USB clock enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CANEN": {
+                    "description": "CAN clock enable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "BKPEN": {
+                    "description": "Backup interface clock\n              enable",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PWREN": {
+                    "description": "Power interface clock\n              enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DACEN": {
+                    "description": "DAC interface clock enable",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BDCR": {
+              "description": "Backup domain control register\n          (RCC_BDCR)",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSEON": {
+                    "description": "External Low Speed oscillator\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LSERDY": {
+                    "description": "External Low Speed oscillator\n              ready",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSEBYP": {
+                    "description": "External Low Speed oscillator\n              bypass",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTCSEL": {
+                    "description": "RTC clock source selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "RTCEN": {
+                    "description": "RTC clock enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BDRST": {
+                    "description": "Backup domain software\n              reset",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CSR": {
+              "description": "Control/status register\n          (RCC_CSR)",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 201326592,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSION": {
+                    "description": "Internal low speed oscillator\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LSIRDY": {
+                    "description": "Internal low speed oscillator\n              ready",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RMVF": {
+                    "description": "Remove reset flag",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PINRSTF": {
+                    "description": "PIN reset flag",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PORRSTF": {
+                    "description": "POR/PDR reset flag",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "SFTRSTF": {
+                    "description": "Software reset flag",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "IWDGRSTF": {
+                    "description": "Independent watchdog reset\n              flag",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "WWDGRSTF": {
+                    "description": "Window watchdog reset flag",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "LPWRRSTF": {
+                    "description": "Low-power reset flag",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOA": {
+        "description": "General purpose I/O",
+        "children": {
+          "registers": {
+            "CRL": {
+              "description": "Port configuration register low\n          (GPIOn_CRL)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1145324612,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE0": {
+                    "description": "Port n.0 mode bits",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CNF0": {
+                    "description": "Port n.0 configuration\n              bits",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODE1": {
+                    "description": "Port n.1 mode bits",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CNF1": {
+                    "description": "Port n.1 configuration\n              bits",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MODE2": {
+                    "description": "Port n.2 mode bits",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CNF2": {
+                    "description": "Port n.2 configuration\n              bits",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MODE3": {
+                    "description": "Port n.3 mode bits",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CNF3": {
+                    "description": "Port n.3 configuration\n              bits",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MODE4": {
+                    "description": "Port n.4 mode bits",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CNF4": {
+                    "description": "Port n.4 configuration\n              bits",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MODE5": {
+                    "description": "Port n.5 mode bits",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "CNF5": {
+                    "description": "Port n.5 configuration\n              bits",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MODE6": {
+                    "description": "Port n.6 mode bits",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CNF6": {
+                    "description": "Port n.6 configuration\n              bits",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MODE7": {
+                    "description": "Port n.7 mode bits",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CNF7": {
+                    "description": "Port n.7 configuration\n              bits",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CRH": {
+              "description": "Port configuration register high\n          (GPIOn_CRL)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 1145324612,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE8": {
+                    "description": "Port n.8 mode bits",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CNF8": {
+                    "description": "Port n.8 configuration\n              bits",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODE9": {
+                    "description": "Port n.9 mode bits",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CNF9": {
+                    "description": "Port n.9 configuration\n              bits",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MODE10": {
+                    "description": "Port n.10 mode bits",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CNF10": {
+                    "description": "Port n.10 configuration\n              bits",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MODE11": {
+                    "description": "Port n.11 mode bits",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CNF11": {
+                    "description": "Port n.11 configuration\n              bits",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MODE12": {
+                    "description": "Port n.12 mode bits",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CNF12": {
+                    "description": "Port n.12 configuration\n              bits",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MODE13": {
+                    "description": "Port n.13 mode bits",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "CNF13": {
+                    "description": "Port n.13 configuration\n              bits",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MODE14": {
+                    "description": "Port n.14 mode bits",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CNF14": {
+                    "description": "Port n.14 configuration\n              bits",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MODE15": {
+                    "description": "Port n.15 mode bits",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CNF15": {
+                    "description": "Port n.15 configuration\n              bits",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "Port input data register\n          (GPIOn_IDR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDR0": {
+                    "description": "Port input data",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IDR1": {
+                    "description": "Port input data",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IDR2": {
+                    "description": "Port input data",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDR3": {
+                    "description": "Port input data",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IDR4": {
+                    "description": "Port input data",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDR5": {
+                    "description": "Port input data",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDR6": {
+                    "description": "Port input data",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IDR7": {
+                    "description": "Port input data",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IDR8": {
+                    "description": "Port input data",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IDR9": {
+                    "description": "Port input data",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IDR10": {
+                    "description": "Port input data",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IDR11": {
+                    "description": "Port input data",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IDR12": {
+                    "description": "Port input data",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IDR13": {
+                    "description": "Port input data",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "IDR14": {
+                    "description": "Port input data",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "IDR15": {
+                    "description": "Port input data",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ODR": {
+              "description": "Port output data register\n          (GPIOn_ODR)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ODR0": {
+                    "description": "Port output data",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ODR1": {
+                    "description": "Port output data",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ODR2": {
+                    "description": "Port output data",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ODR3": {
+                    "description": "Port output data",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ODR4": {
+                    "description": "Port output data",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ODR5": {
+                    "description": "Port output data",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ODR6": {
+                    "description": "Port output data",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ODR7": {
+                    "description": "Port output data",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ODR8": {
+                    "description": "Port output data",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ODR9": {
+                    "description": "Port output data",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODR10": {
+                    "description": "Port output data",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ODR11": {
+                    "description": "Port output data",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ODR12": {
+                    "description": "Port output data",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ODR13": {
+                    "description": "Port output data",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ODR14": {
+                    "description": "Port output data",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ODR15": {
+                    "description": "Port output data",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BSRR": {
+              "description": "Port bit set/reset register\n          (GPIOn_BSRR)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BS0": {
+                    "description": "Set bit 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BS1": {
+                    "description": "Set bit 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BS2": {
+                    "description": "Set bit 1",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BS3": {
+                    "description": "Set bit 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BS4": {
+                    "description": "Set bit 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BS5": {
+                    "description": "Set bit 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BS6": {
+                    "description": "Set bit 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BS7": {
+                    "description": "Set bit 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BS8": {
+                    "description": "Set bit 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BS9": {
+                    "description": "Set bit 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BS10": {
+                    "description": "Set bit 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BS11": {
+                    "description": "Set bit 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BS12": {
+                    "description": "Set bit 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BS13": {
+                    "description": "Set bit 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BS14": {
+                    "description": "Set bit 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BS15": {
+                    "description": "Set bit 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BR0": {
+                    "description": "Reset bit 0",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Reset bit 1",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Reset bit 2",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Reset bit 3",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Reset bit 4",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Reset bit 5",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Reset bit 6",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Reset bit 7",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Reset bit 8",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Reset bit 9",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Reset bit 10",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Reset bit 11",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Reset bit 12",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Reset bit 13",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Reset bit 14",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "BR15": {
+                    "description": "Reset bit 15",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BRR": {
+              "description": "Port bit reset register\n          (GPIOn_BRR)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BR0": {
+                    "description": "Reset bit 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Reset bit 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Reset bit 1",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Reset bit 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Reset bit 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Reset bit 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Reset bit 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Reset bit 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Reset bit 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Reset bit 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Reset bit 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Reset bit 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Reset bit 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Reset bit 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Reset bit 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BR15": {
+                    "description": "Reset bit 15",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LCKR": {
+              "description": "Port configuration lock\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LCK0": {
+                    "description": "Port A Lock bit 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LCK1": {
+                    "description": "Port A Lock bit 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LCK2": {
+                    "description": "Port A Lock bit 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LCK3": {
+                    "description": "Port A Lock bit 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LCK4": {
+                    "description": "Port A Lock bit 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "LCK5": {
+                    "description": "Port A Lock bit 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LCK6": {
+                    "description": "Port A Lock bit 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LCK7": {
+                    "description": "Port A Lock bit 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCK8": {
+                    "description": "Port A Lock bit 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LCK9": {
+                    "description": "Port A Lock bit 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LCK10": {
+                    "description": "Port A Lock bit 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LCK11": {
+                    "description": "Port A Lock bit 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LCK12": {
+                    "description": "Port A Lock bit 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LCK13": {
+                    "description": "Port A Lock bit 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LCK14": {
+                    "description": "Port A Lock bit 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "LCK15": {
+                    "description": "Port A Lock bit 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LCKK": {
+                    "description": "Lock key",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "STK": {
+        "description": "SysTick timer",
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "SysTick control and status\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TICKINT": {
+                    "description": "SysTick exception request\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CLKSOURCE": {
+                    "description": "Clock source selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "COUNTFLAG": {
+                    "description": "COUNTFLAG",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LOAD_": {
+              "description": "SysTick reload value register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RELOAD": {
+                    "description": "RELOAD value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "VAL": {
+              "description": "SysTick current value register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CURRENT": {
+                    "description": "Current counter value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "CALIB": {
+              "description": "SysTick calibration value\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TENMS": {
+                    "description": "Calibration value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SCB": {
+        "description": "System control block",
+        "children": {
+          "registers": {
+            "CPUID": {
+              "description": "CPUID base register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1091551809,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "Revision": {
+                    "description": "Revision number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "PartNo": {
+                    "description": "Part number of the\n              processor",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "Constant": {
+                    "description": "Reads as 0xF",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "Variant": {
+                    "description": "Variant number",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "Implementer": {
+                    "description": "Implementer code",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ICSR": {
+              "description": "Interrupt control and state\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTACTIVE": {
+                    "description": "Active vector",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "RETTOBASE": {
+                    "description": "Return to base level",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "VECTPENDING": {
+                    "description": "Pending vector",
+                    "offset": 12,
+                    "size": 7
+                  },
+                  "ISRPENDING": {
+                    "description": "Interrupt pending flag",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PENDSTCLR": {
+                    "description": "SysTick exception clear-pending\n              bit",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PENDSTSET": {
+                    "description": "SysTick exception set-pending\n              bit",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PENDSVCLR": {
+                    "description": "PendSV clear-pending bit",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PENDSVSET": {
+                    "description": "PendSV set-pending bit",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "NMIPENDSET": {
+                    "description": "NMI set-pending bit.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "VTOR": {
+              "description": "Vector table offset register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TBLOFF": {
+                    "description": "Vector table base offset\n              field",
+                    "offset": 9,
+                    "size": 21
+                  }
+                }
+              }
+            },
+            "AIRCR": {
+              "description": "Application interrupt and reset control\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTRESET": {
+                    "description": "VECTRESET",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "VECTCLRACTIVE": {
+                    "description": "VECTCLRACTIVE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SYSRESETREQ": {
+                    "description": "SYSRESETREQ",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PRIGROUP": {
+                    "description": "PRIGROUP",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "ENDIANESS": {
+                    "description": "ENDIANESS",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "VECTKEYSTAT": {
+                    "description": "Register key",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SCR": {
+              "description": "System control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLEEPONEXIT": {
+                    "description": "SLEEPONEXIT",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEEPDEEP": {
+                    "description": "SLEEPDEEP",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SEVEONPEND": {
+                    "description": "Send Event on Pending bit",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "Configuration and control\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NONBASETHRDENA": {
+                    "description": "Configures how the processor enters\n              Thread mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USERSETMPEND": {
+                    "description": "USERSETMPEND",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UNALIGN__TRP": {
+                    "description": "UNALIGN_ TRP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIV_0_TRP": {
+                    "description": "DIV_0_TRP",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BFHFNMIGN": {
+                    "description": "BFHFNMIGN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "STKALIGN": {
+                    "description": "STKALIGN",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SHPR1": {
+              "description": "System handler priority\n          registers",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_4": {
+                    "description": "Priority of system handler\n              4",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "PRI_5": {
+                    "description": "Priority of system handler\n              5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "PRI_6": {
+                    "description": "Priority of system handler\n              6",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHPR2": {
+              "description": "System handler priority\n          registers",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_11": {
+                    "description": "Priority of system handler\n              11",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHPR3": {
+              "description": "System handler priority\n          registers",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_14": {
+                    "description": "Priority of system handler\n              14",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "PRI_15": {
+                    "description": "Priority of system handler\n              15",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHCRS": {
+              "description": "System handler control and state\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMFAULTACT": {
+                    "description": "Memory management fault exception active\n              bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BUSFAULTACT": {
+                    "description": "Bus fault exception active\n              bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "USGFAULTACT": {
+                    "description": "Usage fault exception active\n              bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SVCALLACT": {
+                    "description": "SVC call active bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MONITORACT": {
+                    "description": "Debug monitor active bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PENDSVACT": {
+                    "description": "PendSV exception active\n              bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SYSTICKACT": {
+                    "description": "SysTick exception active\n              bit",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USGFAULTPENDED": {
+                    "description": "Usage fault exception pending\n              bit",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MEMFAULTPENDED": {
+                    "description": "Memory management fault exception\n              pending bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BUSFAULTPENDED": {
+                    "description": "Bus fault exception pending\n              bit",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SVCALLPENDED": {
+                    "description": "SVC call pending bit",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MEMFAULTENA": {
+                    "description": "Memory management fault enable\n              bit",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUSFAULTENA": {
+                    "description": "Bus fault enable bit",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USGFAULTENA": {
+                    "description": "Usage fault enable bit",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CFSR_UFSR_BFSR_MMFSR": {
+              "description": "Configurable fault status\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IACCVIOL": {
+                    "description": "IACCVIOL",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DACCVIOL": {
+                    "description": "DACCVIOL",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MUNSTKERR": {
+                    "description": "MUNSTKERR",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MSTKERR": {
+                    "description": "MSTKERR",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MLSPERR": {
+                    "description": "MLSPERR",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MMARVALID": {
+                    "description": "MMARVALID",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IBUSERR": {
+                    "description": "Instruction bus error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PRECISERR": {
+                    "description": "Precise data bus error",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IMPRECISERR": {
+                    "description": "Imprecise data bus error",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "UNSTKERR": {
+                    "description": "Bus fault on unstacking for a return\n              from exception",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STKERR": {
+                    "description": "Bus fault on stacking for exception\n              entry",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LSPERR": {
+                    "description": "Bus fault on floating-point lazy state\n              preservation",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BFARVALID": {
+                    "description": "Bus Fault Address Register (BFAR) valid\n              flag",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "UNDEFINSTR": {
+                    "description": "Undefined instruction usage\n              fault",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "INVSTATE": {
+                    "description": "Invalid state usage fault",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INVPC": {
+                    "description": "Invalid PC load usage\n              fault",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "NOCP": {
+                    "description": "No coprocessor usage\n              fault.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UNALIGNED": {
+                    "description": "Unaligned access usage\n              fault",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "DIVBYZERO": {
+                    "description": "Divide by zero usage fault",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HFSR": {
+              "description": "Hard fault status register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTTBL": {
+                    "description": "Vector table hard fault",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FORCED": {
+                    "description": "Forced hard fault",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DEBUG_VT": {
+                    "description": "Reserved for Debug use",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMFAR": {
+              "description": "Memory management fault address\n          register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMFAR": {
+                    "description": "Memory management fault\n              address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BFAR": {
+              "description": "Bus fault address register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BFAR": {
+                    "description": "Bus fault address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NVIC_STIR": {
+        "description": "Nested vectored interrupt\n      controller",
+        "children": {
+          "registers": {
+            "STIR": {
+              "description": "Software trigger interrupt\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTID": {
+                    "description": "Software generated interrupt\n              ID",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SCB_ACTRL": {
+        "description": "System control block ACTLR",
+        "children": {
+          "registers": {
+            "ACTRL": {
+              "description": "Auxiliary control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DISFOLD": {
+                    "description": "DISFOLD",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FPEXCODIS": {
+                    "description": "FPEXCODIS",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DISRAMODE": {
+                    "description": "DISRAMODE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DISITMATBFLUSH": {
+                    "description": "DISITMATBFLUSH",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "MPU": {
+        "description": "Memory protection unit",
+        "children": {
+          "registers": {
+            "MPU_TYPER": {
+              "description": "MPU type register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SEPARATE": {
+                    "description": "Separate flag",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DREGION": {
+                    "description": "Number of MPU data regions",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IREGION": {
+                    "description": "Number of MPU instruction\n              regions",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MPU_CTRL": {
+              "description": "MPU control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enables the MPU",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HFNMIENA": {
+                    "description": "Enables the operation of MPU during hard\n              fault",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PRIVDEFENA": {
+                    "description": "Enable priviliged software access to\n              default memory map",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MPU_RNR": {
+              "description": "MPU region number register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION": {
+                    "description": "MPU region",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MPU_RBAR": {
+              "description": "MPU region base address\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION": {
+                    "description": "MPU region field",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "VALID": {
+                    "description": "MPU region number valid",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ADDR": {
+                    "description": "Region base address field",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "MPU_RASR": {
+              "description": "MPU region attribute and size\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Region enable bit.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SIZE": {
+                    "description": "Size of the MPU protection\n              region",
+                    "offset": 1,
+                    "size": 5
+                  },
+                  "SRD": {
+                    "description": "Subregion disable bits",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "B": {
+                    "description": "memory attribute",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "C": {
+                    "description": "memory attribute",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "S": {
+                    "description": "Shareable memory attribute",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TEX": {
+                    "description": "memory attribute",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "AP": {
+                    "description": "Access permission",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "XN": {
+                    "description": "Instruction access disable\n              bit",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NVIC": {
+        "description": "Nested Vectored Interrupt\n      Controller",
+        "children": {
+          "registers": {
+            "ISER0": {
+              "description": "Interrupt Set-Enable Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "SETENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISER1": {
+              "description": "Interrupt Set-Enable Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "SETENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICER0": {
+              "description": "Interrupt Clear-Enable\n          Register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "CLRENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICER1": {
+              "description": "Interrupt Clear-Enable\n          Register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "CLRENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISPR0": {
+              "description": "Interrupt Set-Pending Register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "SETPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISPR1": {
+              "description": "Interrupt Set-Pending Register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "SETPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICPR0": {
+              "description": "Interrupt Clear-Pending\n          Register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "CLRPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICPR1": {
+              "description": "Interrupt Clear-Pending\n          Register",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "CLRPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IABR0": {
+              "description": "Interrupt Active Bit Register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACTIVE": {
+                    "description": "ACTIVE",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IABR1": {
+              "description": "Interrupt Active Bit Register",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACTIVE": {
+                    "description": "ACTIVE",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IPR0": {
+              "description": "Interrupt Priority Register",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR1": {
+              "description": "Interrupt Priority Register",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR2": {
+              "description": "Interrupt Priority Register",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR3": {
+              "description": "Interrupt Priority Register",
+              "offset": 780,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR4": {
+              "description": "Interrupt Priority Register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR5": {
+              "description": "Interrupt Priority Register",
+              "offset": 788,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR6": {
+              "description": "Interrupt Priority Register",
+              "offset": 792,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR7": {
+              "description": "Interrupt Priority Register",
+              "offset": 796,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR8": {
+              "description": "Interrupt Priority Register",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR9": {
+              "description": "Interrupt Priority Register",
+              "offset": 804,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR10": {
+              "description": "Interrupt Priority Register",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR11": {
+              "description": "Interrupt Priority Register",
+              "offset": 812,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR12": {
+              "description": "Interrupt Priority Register",
+              "offset": 816,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR13": {
+              "description": "Interrupt Priority Register",
+              "offset": 820,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR14": {
+              "description": "Interrupt Priority Register",
+              "offset": 824,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "AFIO": {
+        "description": "Alternate function I/O",
+        "children": {
+          "registers": {
+            "EVCR": {
+              "description": "Event Control Register\n          (AFIO_EVCR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN": {
+                    "description": "Pin selection",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "PORT": {
+                    "description": "Port selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "EVOE": {
+                    "description": "Event Output Enable",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MAPR": {
+              "description": "AF remap and debug I/O configuration\n          register (AFIO_MAPR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI1_REMAP": {
+                    "description": "SPI1 remapping",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "I2C1_REMAP": {
+                    "description": "I2C1 remapping",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "USART1_REMAP": {
+                    "description": "USART1 remapping",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "USART2_REMAP": {
+                    "description": "USART2 remapping",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "USART3_REMAP": {
+                    "description": "USART3 remapping",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "TIM1_REMAP": {
+                    "description": "TIM1 remapping",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "TIM2_REMAP": {
+                    "description": "TIM2 remapping",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "TIM3_REMAP": {
+                    "description": "TIM3 remapping",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "TIM4_REMAP": {
+                    "description": "TIM4 remapping",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CAN_REMAP": {
+                    "description": "CAN1 remapping",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PD01_REMAP": {
+                    "description": "Port D0/Port D1 mapping on\n              OSCIN/OSCOUT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TIM5CH4_IREMAP": {
+                    "description": "Set and cleared by\n              software",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ADC1_ETRGINJ_REMAP": {
+                    "description": "ADC 1 External trigger injected\n              conversion remapping",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ADC1_ETRGREG_REMAP": {
+                    "description": "ADC 1 external trigger regular\n              conversion remapping",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "ADC2_ETRGINJ_REMAP": {
+                    "description": "ADC 2 external trigger injected\n              conversion remapping",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ADC2_ETRGREG_REMAP": {
+                    "description": "ADC 2 external trigger regular\n              conversion remapping",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "SWJ_CFG": {
+                    "description": "Serial wire JTAG\n              configuration",
+                    "offset": 24,
+                    "size": 3,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "EXTICR1": {
+              "description": "External interrupt configuration register 1\n          (AFIO_EXTICR1)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI0": {
+                    "description": "EXTI0 configuration",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "EXTI1": {
+                    "description": "EXTI1 configuration",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI2": {
+                    "description": "EXTI2 configuration",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI3": {
+                    "description": "EXTI3 configuration",
+                    "offset": 12,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTICR2": {
+              "description": "External interrupt configuration register 2\n          (AFIO_EXTICR2)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI4": {
+                    "description": "EXTI4 configuration",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "EXTI5": {
+                    "description": "EXTI5 configuration",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI6": {
+                    "description": "EXTI6 configuration",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI7": {
+                    "description": "EXTI7 configuration",
+                    "offset": 12,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTICR3": {
+              "description": "External interrupt configuration register 3\n          (AFIO_EXTICR3)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI8": {
+                    "description": "EXTI8 configuration",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "EXTI9": {
+                    "description": "EXTI9 configuration",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI10": {
+                    "description": "EXTI10 configuration",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI11": {
+                    "description": "EXTI11 configuration",
+                    "offset": 12,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTICR4": {
+              "description": "External interrupt configuration register 4\n          (AFIO_EXTICR4)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI12": {
+                    "description": "EXTI12 configuration",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "EXTI13": {
+                    "description": "EXTI13 configuration",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI14": {
+                    "description": "EXTI14 configuration",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI15": {
+                    "description": "EXTI15 configuration",
+                    "offset": 12,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MAPR2": {
+              "description": "AF remap and debug I/O configuration\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM9_REMAP": {
+                    "description": "TIM9 remapping",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIM10_REMAP": {
+                    "description": "TIM10 remapping",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TIM11_REMAP": {
+                    "description": "TIM11 remapping",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIM13_REMAP": {
+                    "description": "TIM13 remapping",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIM14_REMAP": {
+                    "description": "TIM14 remapping",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FSMC_NADV": {
+                    "description": "NADV connect/disconnect",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EXTI": {
+        "description": "EXTI",
+        "children": {
+          "registers": {
+            "IMR": {
+              "description": "Interrupt mask register\n          (EXTI_IMR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR0": {
+                    "description": "Interrupt Mask on line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MR1": {
+                    "description": "Interrupt Mask on line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MR2": {
+                    "description": "Interrupt Mask on line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MR3": {
+                    "description": "Interrupt Mask on line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MR4": {
+                    "description": "Interrupt Mask on line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MR5": {
+                    "description": "Interrupt Mask on line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MR6": {
+                    "description": "Interrupt Mask on line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MR7": {
+                    "description": "Interrupt Mask on line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MR8": {
+                    "description": "Interrupt Mask on line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "MR9": {
+                    "description": "Interrupt Mask on line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "MR10": {
+                    "description": "Interrupt Mask on line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "MR11": {
+                    "description": "Interrupt Mask on line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "MR12": {
+                    "description": "Interrupt Mask on line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MR13": {
+                    "description": "Interrupt Mask on line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MR14": {
+                    "description": "Interrupt Mask on line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MR15": {
+                    "description": "Interrupt Mask on line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MR16": {
+                    "description": "Interrupt Mask on line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MR17": {
+                    "description": "Interrupt Mask on line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MR18": {
+                    "description": "Interrupt Mask on line 18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EMR": {
+              "description": "Event mask register (EXTI_EMR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR0": {
+                    "description": "Event Mask on line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MR1": {
+                    "description": "Event Mask on line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MR2": {
+                    "description": "Event Mask on line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MR3": {
+                    "description": "Event Mask on line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MR4": {
+                    "description": "Event Mask on line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MR5": {
+                    "description": "Event Mask on line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MR6": {
+                    "description": "Event Mask on line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MR7": {
+                    "description": "Event Mask on line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MR8": {
+                    "description": "Event Mask on line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "MR9": {
+                    "description": "Event Mask on line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "MR10": {
+                    "description": "Event Mask on line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "MR11": {
+                    "description": "Event Mask on line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "MR12": {
+                    "description": "Event Mask on line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MR13": {
+                    "description": "Event Mask on line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MR14": {
+                    "description": "Event Mask on line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MR15": {
+                    "description": "Event Mask on line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MR16": {
+                    "description": "Event Mask on line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MR17": {
+                    "description": "Event Mask on line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MR18": {
+                    "description": "Event Mask on line 18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RTSR": {
+              "description": "Rising Trigger selection register\n          (EXTI_RTSR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TR0": {
+                    "description": "Rising trigger event configuration of\n              line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TR1": {
+                    "description": "Rising trigger event configuration of\n              line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TR2": {
+                    "description": "Rising trigger event configuration of\n              line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TR3": {
+                    "description": "Rising trigger event configuration of\n              line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TR4": {
+                    "description": "Rising trigger event configuration of\n              line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TR5": {
+                    "description": "Rising trigger event configuration of\n              line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TR6": {
+                    "description": "Rising trigger event configuration of\n              line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TR7": {
+                    "description": "Rising trigger event configuration of\n              line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TR8": {
+                    "description": "Rising trigger event configuration of\n              line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TR9": {
+                    "description": "Rising trigger event configuration of\n              line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TR10": {
+                    "description": "Rising trigger event configuration of\n              line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TR11": {
+                    "description": "Rising trigger event configuration of\n              line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TR12": {
+                    "description": "Rising trigger event configuration of\n              line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TR13": {
+                    "description": "Rising trigger event configuration of\n              line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TR14": {
+                    "description": "Rising trigger event configuration of\n              line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TR15": {
+                    "description": "Rising trigger event configuration of\n              line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TR16": {
+                    "description": "Rising trigger event configuration of\n              line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TR17": {
+                    "description": "Rising trigger event configuration of\n              line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TR18": {
+                    "description": "Rising trigger event configuration of\n              line 18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FTSR": {
+              "description": "Falling Trigger selection register\n          (EXTI_FTSR)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TR0": {
+                    "description": "Falling trigger event configuration of\n              line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TR1": {
+                    "description": "Falling trigger event configuration of\n              line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TR2": {
+                    "description": "Falling trigger event configuration of\n              line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TR3": {
+                    "description": "Falling trigger event configuration of\n              line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TR4": {
+                    "description": "Falling trigger event configuration of\n              line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TR5": {
+                    "description": "Falling trigger event configuration of\n              line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TR6": {
+                    "description": "Falling trigger event configuration of\n              line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TR7": {
+                    "description": "Falling trigger event configuration of\n              line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TR8": {
+                    "description": "Falling trigger event configuration of\n              line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TR9": {
+                    "description": "Falling trigger event configuration of\n              line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TR10": {
+                    "description": "Falling trigger event configuration of\n              line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TR11": {
+                    "description": "Falling trigger event configuration of\n              line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TR12": {
+                    "description": "Falling trigger event configuration of\n              line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TR13": {
+                    "description": "Falling trigger event configuration of\n              line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TR14": {
+                    "description": "Falling trigger event configuration of\n              line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TR15": {
+                    "description": "Falling trigger event configuration of\n              line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TR16": {
+                    "description": "Falling trigger event configuration of\n              line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TR17": {
+                    "description": "Falling trigger event configuration of\n              line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TR18": {
+                    "description": "Falling trigger event configuration of\n              line 18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWIER": {
+              "description": "Software interrupt event register\n          (EXTI_SWIER)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWIER0": {
+                    "description": "Software Interrupt on line\n              0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SWIER1": {
+                    "description": "Software Interrupt on line\n              1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SWIER2": {
+                    "description": "Software Interrupt on line\n              2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SWIER3": {
+                    "description": "Software Interrupt on line\n              3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SWIER4": {
+                    "description": "Software Interrupt on line\n              4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SWIER5": {
+                    "description": "Software Interrupt on line\n              5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SWIER6": {
+                    "description": "Software Interrupt on line\n              6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SWIER7": {
+                    "description": "Software Interrupt on line\n              7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SWIER8": {
+                    "description": "Software Interrupt on line\n              8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SWIER9": {
+                    "description": "Software Interrupt on line\n              9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SWIER10": {
+                    "description": "Software Interrupt on line\n              10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SWIER11": {
+                    "description": "Software Interrupt on line\n              11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SWIER12": {
+                    "description": "Software Interrupt on line\n              12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SWIER13": {
+                    "description": "Software Interrupt on line\n              13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SWIER14": {
+                    "description": "Software Interrupt on line\n              14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SWIER15": {
+                    "description": "Software Interrupt on line\n              15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SWIER16": {
+                    "description": "Software Interrupt on line\n              16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SWIER17": {
+                    "description": "Software Interrupt on line\n              17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SWIER18": {
+                    "description": "Software Interrupt on line\n              18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PR": {
+              "description": "Pending register (EXTI_PR)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PR0": {
+                    "description": "Pending bit 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PR1": {
+                    "description": "Pending bit 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PR2": {
+                    "description": "Pending bit 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PR3": {
+                    "description": "Pending bit 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PR4": {
+                    "description": "Pending bit 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PR5": {
+                    "description": "Pending bit 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PR6": {
+                    "description": "Pending bit 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PR7": {
+                    "description": "Pending bit 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PR8": {
+                    "description": "Pending bit 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PR9": {
+                    "description": "Pending bit 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PR10": {
+                    "description": "Pending bit 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PR11": {
+                    "description": "Pending bit 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PR12": {
+                    "description": "Pending bit 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PR13": {
+                    "description": "Pending bit 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PR14": {
+                    "description": "Pending bit 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PR15": {
+                    "description": "Pending bit 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "PR16": {
+                    "description": "Pending bit 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PR17": {
+                    "description": "Pending bit 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PR18": {
+                    "description": "Pending bit 18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DMA1": {
+        "description": "DMA controller",
+        "children": {
+          "registers": {
+            "ISR": {
+              "description": "DMA interrupt status register\n          (DMA_ISR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "GIF1": {
+                    "description": "Channel 1 Global interrupt\n              flag",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIF1": {
+                    "description": "Channel 1 Transfer Complete\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIF1": {
+                    "description": "Channel 1 Half Transfer Complete\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIF1": {
+                    "description": "Channel 1 Transfer Error\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GIF2": {
+                    "description": "Channel 2 Global interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TCIF2": {
+                    "description": "Channel 2 Transfer Complete\n              flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HTIF2": {
+                    "description": "Channel 2 Half Transfer Complete\n              flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TEIF2": {
+                    "description": "Channel 2 Transfer Error\n              flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GIF3": {
+                    "description": "Channel 3 Global interrupt\n              flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TCIF3": {
+                    "description": "Channel 3 Transfer Complete\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HTIF3": {
+                    "description": "Channel 3 Half Transfer Complete\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TEIF3": {
+                    "description": "Channel 3 Transfer Error\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GIF4": {
+                    "description": "Channel 4 Global interrupt\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TCIF4": {
+                    "description": "Channel 4 Transfer Complete\n              flag",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "HTIF4": {
+                    "description": "Channel 4 Half Transfer Complete\n              flag",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TEIF4": {
+                    "description": "Channel 4 Transfer Error\n              flag",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GIF5": {
+                    "description": "Channel 5 Global interrupt\n              flag",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TCIF5": {
+                    "description": "Channel 5 Transfer Complete\n              flag",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "HTIF5": {
+                    "description": "Channel 5 Half Transfer Complete\n              flag",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TEIF5": {
+                    "description": "Channel 5 Transfer Error\n              flag",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GIF6": {
+                    "description": "Channel 6 Global interrupt\n              flag",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TCIF6": {
+                    "description": "Channel 6 Transfer Complete\n              flag",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HTIF6": {
+                    "description": "Channel 6 Half Transfer Complete\n              flag",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TEIF6": {
+                    "description": "Channel 6 Transfer Error\n              flag",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GIF7": {
+                    "description": "Channel 7 Global interrupt\n              flag",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "TCIF7": {
+                    "description": "Channel 7 Transfer Complete\n              flag",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "HTIF7": {
+                    "description": "Channel 7 Half Transfer Complete\n              flag",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TEIF7": {
+                    "description": "Channel 7 Transfer Error\n              flag",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IFCR": {
+              "description": "DMA interrupt flag clear register\n          (DMA_IFCR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CGIF1": {
+                    "description": "Channel 1 Global interrupt\n              clear",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CGIF2": {
+                    "description": "Channel 2 Global interrupt\n              clear",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CGIF3": {
+                    "description": "Channel 3 Global interrupt\n              clear",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CGIF4": {
+                    "description": "Channel 4 Global interrupt\n              clear",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CGIF5": {
+                    "description": "Channel 5 Global interrupt\n              clear",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CGIF6": {
+                    "description": "Channel 6 Global interrupt\n              clear",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CGIF7": {
+                    "description": "Channel 7 Global interrupt\n              clear",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "CTCIF1": {
+                    "description": "Channel 1 Transfer Complete\n              clear",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CTCIF2": {
+                    "description": "Channel 2 Transfer Complete\n              clear",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CTCIF3": {
+                    "description": "Channel 3 Transfer Complete\n              clear",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CTCIF4": {
+                    "description": "Channel 4 Transfer Complete\n              clear",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CTCIF5": {
+                    "description": "Channel 5 Transfer Complete\n              clear",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "CTCIF6": {
+                    "description": "Channel 6 Transfer Complete\n              clear",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CTCIF7": {
+                    "description": "Channel 7 Transfer Complete\n              clear",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CHTIF1": {
+                    "description": "Channel 1 Half Transfer\n              clear",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CHTIF2": {
+                    "description": "Channel 2 Half Transfer\n              clear",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CHTIF3": {
+                    "description": "Channel 3 Half Transfer\n              clear",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CHTIF4": {
+                    "description": "Channel 4 Half Transfer\n              clear",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CHTIF5": {
+                    "description": "Channel 5 Half Transfer\n              clear",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CHTIF6": {
+                    "description": "Channel 6 Half Transfer\n              clear",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CHTIF7": {
+                    "description": "Channel 7 Half Transfer\n              clear",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CTEIF1": {
+                    "description": "Channel 1 Transfer Error\n              clear",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CTEIF2": {
+                    "description": "Channel 2 Transfer Error\n              clear",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CTEIF3": {
+                    "description": "Channel 3 Transfer Error\n              clear",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CTEIF4": {
+                    "description": "Channel 4 Transfer Error\n              clear",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CTEIF5": {
+                    "description": "Channel 5 Transfer Error\n              clear",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "CTEIF6": {
+                    "description": "Channel 6 Transfer Error\n              clear",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CTEIF7": {
+                    "description": "Channel 7 Transfer Error\n              clear",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR1": {
+              "description": "DMA channel 1 number of data\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR1": {
+              "description": "DMA channel 1 peripheral address\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR1": {
+              "description": "DMA channel 1 memory address\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR2": {
+              "description": "DMA channel 2 number of data\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR2": {
+              "description": "DMA channel 2 peripheral address\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR2": {
+              "description": "DMA channel 2 memory address\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR3": {
+              "description": "DMA channel 3 number of data\n          register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR3": {
+              "description": "DMA channel 3 peripheral address\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR3": {
+              "description": "DMA channel 3 memory address\n          register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR4": {
+              "description": "DMA channel 4 number of data\n          register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR4": {
+              "description": "DMA channel 4 peripheral address\n          register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR4": {
+              "description": "DMA channel 4 memory address\n          register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR5": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR5": {
+              "description": "DMA channel 5 number of data\n          register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR5": {
+              "description": "DMA channel 5 peripheral address\n          register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR5": {
+              "description": "DMA channel 5 memory address\n          register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR6": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR6": {
+              "description": "DMA channel 6 number of data\n          register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR6": {
+              "description": "DMA channel 6 peripheral address\n          register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR6": {
+              "description": "DMA channel 6 memory address\n          register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR7": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR7": {
+              "description": "DMA channel 7 number of data\n          register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR7": {
+              "description": "DMA channel 7 peripheral address\n          register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR7": {
+              "description": "DMA channel 7 memory address\n          register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ETHERNET_DMA": {
+        "description": "Ethernet: DMA controller operation",
+        "children": {
+          "registers": {
+            "DMABMR": {
+              "description": "Ethernet DMA bus mode register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 131329,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SR": {
+                    "description": "Software reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DA": {
+                    "description": "DMA Arbitration",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DSL": {
+                    "description": "Descriptor skip length",
+                    "offset": 2,
+                    "size": 5
+                  },
+                  "PBL": {
+                    "description": "Programmable burst length",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "RTPR": {
+                    "description": "Rx Tx priority ratio",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "FB": {
+                    "description": "Fixed burst",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RDP": {
+                    "description": "Rx DMA PBL",
+                    "offset": 17,
+                    "size": 6
+                  },
+                  "USP": {
+                    "description": "Use separate PBL",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FPM": {
+                    "description": "4xPBL mode",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "AAB": {
+                    "description": "Address-aligned beats",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMATPDR": {
+              "description": "Ethernet DMA transmit poll demand\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TPD": {
+                    "description": "Transmit poll demand",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMARPDR": {
+              "description": "EHERNET DMA receive poll demand\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RPD": {
+                    "description": "Receive poll demand",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMARDLAR": {
+              "description": "Ethernet DMA receive descriptor list address\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRL": {
+                    "description": "Start of receive list",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMATDLAR": {
+              "description": "Ethernet DMA transmit descriptor list\n          address register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STL": {
+                    "description": "Start of transmit list",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMASR": {
+              "description": "Ethernet DMA status register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TS": {
+                    "description": "Transmit status",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TPSS": {
+                    "description": "Transmit process stopped\n              status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TBUS": {
+                    "description": "Transmit buffer unavailable\n              status",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TJTS": {
+                    "description": "Transmit jabber timeout\n              status",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ROS": {
+                    "description": "Receive overflow status",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TUS": {
+                    "description": "Transmit underflow status",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RS": {
+                    "description": "Receive status",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RBUS": {
+                    "description": "Receive buffer unavailable\n              status",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RPSS": {
+                    "description": "Receive process stopped\n              status",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PWTS": {
+                    "description": "Receive watchdog timeout\n              status",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ETS": {
+                    "description": "Early transmit status",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FBES": {
+                    "description": "Fatal bus error status",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ERS": {
+                    "description": "Early receive status",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "AIS": {
+                    "description": "Abnormal interrupt summary",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "NIS": {
+                    "description": "Normal interrupt summary",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RPS": {
+                    "description": "Receive process state",
+                    "offset": 17,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "TPS": {
+                    "description": "Transmit process state",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "EBS": {
+                    "description": "Error bits status",
+                    "offset": 23,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "MMCS": {
+                    "description": "MMC status",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PMTS": {
+                    "description": "PMT status",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TSTS": {
+                    "description": "Time stamp trigger status",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DMAOMR": {
+              "description": "Ethernet DMA operation mode\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SR": {
+                    "description": "SR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OSF": {
+                    "description": "OSF",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTC": {
+                    "description": "RTC",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "FUGF": {
+                    "description": "FUGF",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FEF": {
+                    "description": "FEF",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ST": {
+                    "description": "ST",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TTC": {
+                    "description": "TTC",
+                    "offset": 14,
+                    "size": 3
+                  },
+                  "FTF": {
+                    "description": "FTF",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TSF": {
+                    "description": "TSF",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "DFRF": {
+                    "description": "DFRF",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "RSF": {
+                    "description": "RSF",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DTCEFD": {
+                    "description": "DTCEFD",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMAIER": {
+              "description": "Ethernet DMA interrupt enable\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIE": {
+                    "description": "Transmit interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TPSIE": {
+                    "description": "Transmit process stopped interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TBUIE": {
+                    "description": "Transmit buffer unavailable interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TJTIE": {
+                    "description": "Transmit jabber timeout interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ROIE": {
+                    "description": "Overflow interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TUIE": {
+                    "description": "Underflow interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RIE": {
+                    "description": "Receive interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RBUIE": {
+                    "description": "Receive buffer unavailable interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RPSIE": {
+                    "description": "Receive process stopped interrupt\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RWTIE": {
+                    "description": "receive watchdog timeout interrupt\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ETIE": {
+                    "description": "Early transmit interrupt\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FBEIE": {
+                    "description": "Fatal bus error interrupt\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ERIE": {
+                    "description": "Early receive interrupt\n              enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "AISE": {
+                    "description": "Abnormal interrupt summary\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "NISE": {
+                    "description": "Normal interrupt summary\n              enable",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMAMFBOCR": {
+              "description": "Ethernet DMA missed frame and buffer\n          overflow counter register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "MFC": {
+                    "description": "Missed frames by the\n              controller",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OMFC": {
+                    "description": "Overflow bit for missed frame\n              counter",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MFA": {
+                    "description": "Missed frames by the\n              application",
+                    "offset": 17,
+                    "size": 11
+                  },
+                  "OFOC": {
+                    "description": "Overflow bit for FIFO overflow\n              counter",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMACHTDR": {
+              "description": "Ethernet DMA current host transmit\n          descriptor register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HTDAP": {
+                    "description": "Host transmit descriptor address\n              pointer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMACHRDR": {
+              "description": "Ethernet DMA current host receive descriptor\n          register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HRDAP": {
+                    "description": "Host receive descriptor address\n              pointer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMACHTBAR": {
+              "description": "Ethernet DMA current host transmit buffer\n          address register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HTBAP": {
+                    "description": "Host transmit buffer address\n              pointer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMACHRBAR": {
+              "description": "Ethernet DMA current host receive buffer\n          address register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HRBAP": {
+                    "description": "Host receive buffer address\n              pointer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SDIO": {
+        "description": "Secure digital input/output\n      interface",
+        "children": {
+          "registers": {
+            "POWER": {
+              "description": "Bits 1:0 = PWRCTRL: Power supply control\n          bits",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWRCTRL": {
+                    "description": "PWRCTRL",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLKCR": {
+              "description": "SDI clock control register\n          (SDIO_CLKCR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKDIV": {
+                    "description": "Clock divide factor",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CLKEN": {
+                    "description": "Clock enable bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PWRSAV": {
+                    "description": "Power saving configuration\n              bit",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BYPASS": {
+                    "description": "Clock divider bypass enable\n              bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WIDBUS": {
+                    "description": "Wide bus mode enable bit",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "NEGEDGE": {
+                    "description": "SDIO_CK dephasing selection\n              bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "HWFC_EN": {
+                    "description": "HW Flow Control enable",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ARG": {
+              "description": "Bits 31:0 = : Command argument",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CMDARG": {
+                    "description": "Command argument",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMD": {
+              "description": "SDIO command register\n          (SDIO_CMD)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CMDINDEX": {
+                    "description": "CMDINDEX",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "WAITRESP": {
+                    "description": "WAITRESP",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "WAITINT": {
+                    "description": "WAITINT",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WAITPEND": {
+                    "description": "WAITPEND",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CPSMEN": {
+                    "description": "CPSMEN",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SDIOSuspend": {
+                    "description": "SDIOSuspend",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ENCMDcompl": {
+                    "description": "ENCMDcompl",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "nIEN": {
+                    "description": "nIEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CE_ATACMD": {
+                    "description": "CE_ATACMD",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RESPCMD": {
+              "description": "SDIO command register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RESPCMD": {
+                    "description": "RESPCMD",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "RESPI1": {
+              "description": "Bits 31:0 = CARDSTATUS1",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS1": {
+                    "description": "CARDSTATUS1",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RESP2": {
+              "description": "Bits 31:0 = CARDSTATUS2",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS2": {
+                    "description": "CARDSTATUS2",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RESP3": {
+              "description": "Bits 31:0 = CARDSTATUS3",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS3": {
+                    "description": "CARDSTATUS3",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RESP4": {
+              "description": "Bits 31:0 = CARDSTATUS4",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS4": {
+                    "description": "CARDSTATUS4",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DTIMER": {
+              "description": "Bits 31:0 = DATATIME: Data timeout\n          period",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATATIME": {
+                    "description": "Data timeout period",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DLEN": {
+              "description": "Bits 24:0 = DATALENGTH: Data length\n          value",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATALENGTH": {
+                    "description": "Data length value",
+                    "offset": 0,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "DCTRL": {
+              "description": "SDIO data control register\n          (SDIO_DCTRL)",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DTEN": {
+                    "description": "DTEN",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DTDIR": {
+                    "description": "DTDIR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DTMODE": {
+                    "description": "DTMODE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMAEN": {
+                    "description": "DMAEN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DBLOCKSIZE": {
+                    "description": "DBLOCKSIZE",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "PWSTART": {
+                    "description": "PWSTART",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PWSTOP": {
+                    "description": "PWSTOP",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RWMOD": {
+                    "description": "RWMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SDIOEN": {
+                    "description": "SDIOEN",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DCOUNT": {
+              "description": "Bits 24:0 = DATACOUNT: Data count\n          value",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATACOUNT": {
+                    "description": "Data count value",
+                    "offset": 0,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "STA": {
+              "description": "SDIO status register\n          (SDIO_STA)",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CCRCFAIL": {
+                    "description": "CCRCFAIL",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DCRCFAIL": {
+                    "description": "DCRCFAIL",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CTIMEOUT": {
+                    "description": "CTIMEOUT",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DTIMEOUT": {
+                    "description": "DTIMEOUT",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXUNDERR": {
+                    "description": "TXUNDERR",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RXOVERR": {
+                    "description": "RXOVERR",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CMDREND": {
+                    "description": "CMDREND",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CMDSENT": {
+                    "description": "CMDSENT",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DATAEND": {
+                    "description": "DATAEND",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "STBITERR": {
+                    "description": "STBITERR",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DBCKEND": {
+                    "description": "DBCKEND",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CMDACT": {
+                    "description": "CMDACT",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TXACT": {
+                    "description": "TXACT",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RXACT": {
+                    "description": "RXACT",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TXFIFOHE": {
+                    "description": "TXFIFOHE",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RXFIFOHF": {
+                    "description": "RXFIFOHF",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TXFIFOF": {
+                    "description": "TXFIFOF",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RXFIFOF": {
+                    "description": "RXFIFOF",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TXFIFOE": {
+                    "description": "TXFIFOE",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RXFIFOE": {
+                    "description": "RXFIFOE",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TXDAVL": {
+                    "description": "TXDAVL",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RXDAVL": {
+                    "description": "RXDAVL",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SDIOIT": {
+                    "description": "SDIOIT",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CEATAEND": {
+                    "description": "CEATAEND",
+                    "offset": 23,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "SDIO interrupt clear register\n          (SDIO_ICR)",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCRCFAILC": {
+                    "description": "CCRCFAILC",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DCRCFAILC": {
+                    "description": "DCRCFAILC",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CTIMEOUTC": {
+                    "description": "CTIMEOUTC",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DTIMEOUTC": {
+                    "description": "DTIMEOUTC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXUNDERRC": {
+                    "description": "TXUNDERRC",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RXOVERRC": {
+                    "description": "RXOVERRC",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CMDRENDC": {
+                    "description": "CMDRENDC",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CMDSENTC": {
+                    "description": "CMDSENTC",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DATAENDC": {
+                    "description": "DATAENDC",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "STBITERRC": {
+                    "description": "STBITERRC",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DBCKENDC": {
+                    "description": "DBCKENDC",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SDIOITC": {
+                    "description": "SDIOITC",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CEATAENDC": {
+                    "description": "CEATAENDC",
+                    "offset": 23,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MASK": {
+              "description": "SDIO mask register (SDIO_MASK)",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCRCFAILIE": {
+                    "description": "CCRCFAILIE",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DCRCFAILIE": {
+                    "description": "DCRCFAILIE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CTIMEOUTIE": {
+                    "description": "CTIMEOUTIE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DTIMEOUTIE": {
+                    "description": "DTIMEOUTIE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXUNDERRIE": {
+                    "description": "TXUNDERRIE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RXOVERRIE": {
+                    "description": "RXOVERRIE",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CMDRENDIE": {
+                    "description": "CMDRENDIE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CMDSENTIE": {
+                    "description": "CMDSENTIE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DATAENDIE": {
+                    "description": "DATAENDIE",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "STBITERRIE": {
+                    "description": "STBITERRIE",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DBACKENDIE": {
+                    "description": "DBACKENDIE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CMDACTIE": {
+                    "description": "CMDACTIE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TXACTIE": {
+                    "description": "TXACTIE",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RXACTIE": {
+                    "description": "RXACTIE",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TXFIFOHEIE": {
+                    "description": "TXFIFOHEIE",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RXFIFOHFIE": {
+                    "description": "RXFIFOHFIE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TXFIFOFIE": {
+                    "description": "TXFIFOFIE",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RXFIFOFIE": {
+                    "description": "RXFIFOFIE",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TXFIFOEIE": {
+                    "description": "TXFIFOEIE",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RXFIFOEIE": {
+                    "description": "RXFIFOEIE",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TXDAVLIE": {
+                    "description": "TXDAVLIE",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RXDAVLIE": {
+                    "description": "RXDAVLIE",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SDIOITIE": {
+                    "description": "SDIOITIE",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CEATENDIE": {
+                    "description": "CEATENDIE",
+                    "offset": 23,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FIFOCNT": {
+              "description": "Bits 23:0 = FIFOCOUNT: Remaining number of\n          words to be written to or read from the\n          FIFO",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FIF0COUNT": {
+                    "description": "FIF0COUNT",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "FIFO": {
+              "description": "bits 31:0 = FIFOData: Receive and transmit\n          FIFO data",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FIFOData": {
+                    "description": "FIFOData",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RTC": {
+        "description": "Real time clock",
+        "children": {
+          "registers": {
+            "CRH": {
+              "description": "RTC Control Register High",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SECIE": {
+                    "description": "Second interrupt Enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ALRIE": {
+                    "description": "Alarm interrupt Enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OWIE": {
+                    "description": "Overflow interrupt Enable",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CRL": {
+              "description": "RTC Control Register Low",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 32,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SECF": {
+                    "description": "Second Flag",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ALRF": {
+                    "description": "Alarm Flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OWF": {
+                    "description": "Overflow Flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RSF": {
+                    "description": "Registers Synchronized\n              Flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CNF": {
+                    "description": "Configuration Flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RTOFF": {
+                    "description": "RTC operation OFF",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PRLH": {
+              "description": "RTC Prescaler Load Register\n          High",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "PRLH": {
+                    "description": "RTC Prescaler Load Register\n              High",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "PRLL": {
+              "description": "RTC Prescaler Load Register\n          Low",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "PRLL": {
+                    "description": "RTC Prescaler Divider Register\n              Low",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DIVH": {
+              "description": "RTC Prescaler Divider Register\n          High",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DIVH": {
+                    "description": "RTC prescaler divider register\n              high",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DIVL": {
+              "description": "RTC Prescaler Divider Register\n          Low",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DIVL": {
+                    "description": "RTC prescaler divider register\n              Low",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CNTH": {
+              "description": "RTC Counter Register High",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNTH": {
+                    "description": "RTC counter register high",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CNTL": {
+              "description": "RTC Counter Register Low",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNTL": {
+                    "description": "RTC counter register Low",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ALRH": {
+              "description": "RTC Alarm Register High",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "ALRH": {
+                    "description": "RTC alarm register high",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ALRL": {
+              "description": "RTC Alarm Register Low",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "ALRL": {
+                    "description": "RTC alarm register low",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "BKP": {
+        "description": "Backup registers",
+        "children": {
+          "registers": {
+            "DR1": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D1": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR2": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D2": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR3": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D3": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR4": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D4": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR5": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D5": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR6": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D6": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR7": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D7": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR8": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D8": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR9": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D9": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR10": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D10": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR11": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR11": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR12": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR12": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR13": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR13": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR14": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D14": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR15": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D15": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR16": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D16": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR17": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D17": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR18": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D18": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR19": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D19": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR20": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D20": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR21": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D21": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR22": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D22": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR23": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D23": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR24": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D24": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR25": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D25": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR26": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D26": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR27": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D27": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR28": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D28": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR29": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D29": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR30": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D30": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR31": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D31": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR32": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D32": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR33": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D33": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR34": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D34": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR35": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D35": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR36": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D36": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR37": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D37": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR38": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D38": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR39": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D39": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR40": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D40": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR41": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D41": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR42": {
+              "description": "Backup data register (BKP_DR)",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "D42": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RTCCR": {
+              "description": "RTC clock calibration register\n          (BKP_RTCCR)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CAL": {
+                    "description": "Calibration value",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "CCO": {
+                    "description": "Calibration Clock Output",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ASOE": {
+                    "description": "Alarm or second output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ASOS": {
+                    "description": "Alarm or second output\n              selection",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "Backup control register\n          (BKP_CR)",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TPE": {
+                    "description": "Tamper pin enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TPAL": {
+                    "description": "Tamper pin active level",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CSR": {
+              "description": "BKP_CSR control/status register\n          (BKP_CSR)",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTE": {
+                    "description": "Clear Tamper event",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CTI": {
+                    "description": "Clear Tamper Interrupt",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TPIE": {
+                    "description": "Tamper Pin interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEF": {
+                    "description": "Tamper Event Flag",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIF": {
+                    "description": "Tamper Interrupt Flag",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "IWDG": {
+        "description": "Independent watchdog",
+        "children": {
+          "registers": {
+            "KR": {
+              "description": "Key register (IWDG_KR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "KEY": {
+                    "description": "Key value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PR": {
+              "description": "Prescaler register (IWDG_PR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PR": {
+                    "description": "Prescaler divider",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "RLR": {
+              "description": "Reload register (IWDG_RLR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RL": {
+                    "description": "Watchdog counter reload\n              value",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register (IWDG_SR)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PVU": {
+                    "description": "Watchdog prescaler value\n              update",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RVU": {
+                    "description": "Watchdog counter reload value\n              update",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "WWDG": {
+        "description": "Window watchdog",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "Control register (WWDG_CR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 127,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T": {
+                    "description": "7-bit counter (MSB to LSB)",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "WDGA": {
+                    "description": "Activation bit",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CFR": {
+              "description": "Configuration register\n          (WWDG_CFR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 127,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "W": {
+                    "description": "7-bit window value",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "WDGTB": {
+                    "description": "Timer Base",
+                    "offset": 7,
+                    "size": 2
+                  },
+                  "EWI": {
+                    "description": "Early Wakeup Interrupt",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register (WWDG_SR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EWI": {
+                    "description": "Early Wakeup Interrupt",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM1": {
+        "description": "Advanced timer",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OIS4": {
+                    "description": "Output Idle state 4",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OIS3N": {
+                    "description": "Output Idle state 3",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OIS3": {
+                    "description": "Output Idle state 3",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OIS2N": {
+                    "description": "Output Idle state 2",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OIS2": {
+                    "description": "Output Idle state 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OIS1N": {
+                    "description": "Output Idle state 1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OIS1": {
+                    "description": "Output Idle state 1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CCUS": {
+                    "description": "Capture/compare control update\n              selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CCPC": {
+                    "description": "Capture/compare preloaded\n              control",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "COMDE": {
+                    "description": "COM DMA request enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BIE": {
+                    "description": "Break interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "COMIE": {
+                    "description": "COM interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BIF": {
+                    "description": "Break interrupt flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMIF": {
+                    "description": "COM interrupt flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BG": {
+                    "description": "Break generation",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMG": {
+                    "description": "Capture/Compare control update\n              generation",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "Output Compare 2 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "Output Compare 2 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "Output Compare 2 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "Output Compare 2 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "Output Compare 1 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC4CE": {
+                    "description": "Output compare 4 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "Output compare 4 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "Output compare 4 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "Output compare 4 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "Output compare 3 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "Output compare 3 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "Output compare 3 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "Output compare 3 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "Capture/Compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC3NE": {
+                    "description": "Capture/Compare 3 complementary output\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2NE": {
+                    "description": "Capture/Compare 2 complementary output\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1NE": {
+                    "description": "Capture/Compare 1 complementary output\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2": {
+                    "description": "Capture/Compare 2 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3": {
+                    "description": "Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4": {
+                    "description": "Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RCR": {
+              "description": "repetition counter register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REP": {
+                    "description": "Repetition counter value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BDTR": {
+              "description": "break and dead-time register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MOE": {
+                    "description": "Main output enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "AOE": {
+                    "description": "Automatic output enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BKP": {
+                    "description": "Break polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BKE": {
+                    "description": "Break enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OSSR": {
+                    "description": "Off-state selection for Run\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OSSI": {
+                    "description": "Off-state selection for Idle\n              mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LOCK": {
+                    "description": "Lock configuration",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "DTG": {
+                    "description": "Dead-time generator setup",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ETHERNET_PTP": {
+        "description": "Ethernet: Precision time protocol",
+        "children": {
+          "registers": {
+            "PTPTSCR": {
+              "description": "Ethernet PTP time stamp control register\n          (ETH_PTPTSCR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSE": {
+                    "description": "Time stamp enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TSFCU": {
+                    "description": "Time stamp fine or coarse\n              update",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TSSTI": {
+                    "description": "Time stamp system time\n              initialize",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TSSTU": {
+                    "description": "Time stamp system time\n              update",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TSITE": {
+                    "description": "Time stamp interrupt trigger\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TSARU": {
+                    "description": "Time stamp addend register\n              update",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PTPSSIR": {
+              "description": "Ethernet PTP subsecond increment\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STSSI": {
+                    "description": "System time subsecond\n              increment",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PTPTSHR": {
+              "description": "Ethernet PTP time stamp high\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STS": {
+                    "description": "System time second",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTSLR": {
+              "description": "Ethernet PTP time stamp low register\n          (ETH_PTPTSLR)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STSS": {
+                    "description": "System time subseconds",
+                    "offset": 0,
+                    "size": 31
+                  },
+                  "STPNS": {
+                    "description": "System time positive or negative\n              sign",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PTPTSHUR": {
+              "description": "Ethernet PTP time stamp high update\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSUS": {
+                    "description": "Time stamp update second",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTSLUR": {
+              "description": "Ethernet PTP time stamp low update register\n          (ETH_PTPTSLUR)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSUSS": {
+                    "description": "Time stamp update\n              subseconds",
+                    "offset": 0,
+                    "size": 31
+                  },
+                  "TSUPNS": {
+                    "description": "Time stamp update positive or negative\n              sign",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PTPTSAR": {
+              "description": "Ethernet PTP time stamp addend\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSA": {
+                    "description": "Time stamp addend",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTTHR": {
+              "description": "Ethernet PTP target time high\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TTSH": {
+                    "description": "Target time stamp high",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTTLR": {
+              "description": "Ethernet PTP target time low\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TTSL": {
+                    "description": "Target time stamp low",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM2": {
+        "description": "General purpose timer",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "Output compare 2 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "Output compare 2 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "Output compare 2 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "Output compare 2 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "Output compare 1 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "Output compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PSC": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC1PSC": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register 2 (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "O24CE": {
+                    "description": "Output compare 4 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "Output compare 4 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "Output compare 4 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "Output compare 4 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "Output compare 3 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "Output compare 3 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "Output compare 3 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "Output compare 3 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "Capture/Compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/Compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2": {
+                    "description": "Capture/Compare 2 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3": {
+                    "description": "Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4": {
+                    "description": "Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ETHERNET_MAC": {
+        "description": "Ethernet: media access control",
+        "children": {
+          "registers": {
+            "MACCR": {
+              "description": "Ethernet MAC configuration register\n          (ETH_MACCR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RE": {
+                    "description": "Receiver enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TE": {
+                    "description": "Transmitter enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DC": {
+                    "description": "Deferral check",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BL": {
+                    "description": "Back-off limit",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "APCS": {
+                    "description": "Automatic pad/CRC\n              stripping",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RD": {
+                    "description": "Retry disable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IPCO": {
+                    "description": "IPv4 checksum offload",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DM": {
+                    "description": "Duplex mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LM": {
+                    "description": "Loopback mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ROD": {
+                    "description": "Receive own disable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FES": {
+                    "description": "Fast Ethernet speed",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CSD": {
+                    "description": "Carrier sense disable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "IFG": {
+                    "description": "Interframe gap",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "JD": {
+                    "description": "Jabber disable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "WD": {
+                    "description": "Watchdog disable",
+                    "offset": 23,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACFFR": {
+              "description": "Ethernet MAC frame filter register\n          (ETH_MACCFFR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PM": {
+                    "description": "Promiscuous mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HU": {
+                    "description": "Hash unicast",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HM": {
+                    "description": "Hash multicast",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DAIF": {
+                    "description": "Destination address inverse\n              filtering",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PAM": {
+                    "description": "Pass all multicast",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BFD": {
+                    "description": "Broadcast frames disable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PCF": {
+                    "description": "Pass control frames",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "SAIF": {
+                    "description": "Source address inverse\n              filtering",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SAF": {
+                    "description": "Source address filter",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HPF": {
+                    "description": "Hash or perfect filter",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RA": {
+                    "description": "Receive all",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACHTHR": {
+              "description": "Ethernet MAC hash table high\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HTH": {
+                    "description": "Hash table high",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACHTLR": {
+              "description": "Ethernet MAC hash table low\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HTL": {
+                    "description": "Hash table low",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACMIIAR": {
+              "description": "Ethernet MAC MII address register\n          (ETH_MACMIIAR)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MB": {
+                    "description": "MII busy",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MW": {
+                    "description": "MII write",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CR": {
+                    "description": "Clock range",
+                    "offset": 2,
+                    "size": 3
+                  },
+                  "MR": {
+                    "description": "MII register",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "PA": {
+                    "description": "PHY address",
+                    "offset": 11,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "MACMIIDR": {
+              "description": "Ethernet MAC MII data register\n          (ETH_MACMIIDR)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MD": {
+                    "description": "MII data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "MACFCR": {
+              "description": "Ethernet MAC flow control register\n          (ETH_MACFCR)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FCB_BPA": {
+                    "description": "Flow control busy/back pressure\n              activate",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TFCE": {
+                    "description": "Transmit flow control\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RFCE": {
+                    "description": "Receive flow control\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UPFD": {
+                    "description": "Unicast pause frame detect",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PLT": {
+                    "description": "Pause low threshold",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "ZQPD": {
+                    "description": "Zero-quanta pause disable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PT": {
+                    "description": "Pass control frames",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "MACVLANTR": {
+              "description": "Ethernet MAC VLAN tag register\n          (ETH_MACVLANTR)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VLANTI": {
+                    "description": "VLAN tag identifier (for receive\n              frames)",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "VLANTC": {
+                    "description": "12-bit VLAN tag comparison",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACRWUFFR": {
+              "description": "Ethernet MAC remote wakeup frame filter\n          register (ETH_MACRWUFFR)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "MACPMTCSR": {
+              "description": "Ethernet MAC PMT control and status register\n          (ETH_MACPMTCSR)",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PD": {
+                    "description": "Power down",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MPE": {
+                    "description": "Magic Packet enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WFE": {
+                    "description": "Wakeup frame enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MPR": {
+                    "description": "Magic packet received",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WFR": {
+                    "description": "Wakeup frame received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GU": {
+                    "description": "Global unicast",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WFFRPR": {
+                    "description": "Wakeup frame filter register pointer\n              reset",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACSR": {
+              "description": "Ethernet MAC interrupt status register\n          (ETH_MACSR)",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PMTS": {
+                    "description": "PMT status",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MMCS": {
+                    "description": "MMC status",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MMCRS": {
+                    "description": "MMC receive status",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MMCTS": {
+                    "description": "MMC transmit status",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TSTS": {
+                    "description": "Time stamp trigger status",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACIMR": {
+              "description": "Ethernet MAC interrupt mask register\n          (ETH_MACIMR)",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PMTIM": {
+                    "description": "PMT interrupt mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TSTIM": {
+                    "description": "Time stamp trigger interrupt\n              mask",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA0HR": {
+              "description": "Ethernet MAC address 0 high register\n          (ETH_MACA0HR)",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 1114111,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA0H": {
+                    "description": "MAC address0 high",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MO": {
+                    "description": "Always 1",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MACA0LR": {
+              "description": "Ethernet MAC address 0 low\n          register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA0L": {
+                    "description": "MAC address0 low",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACA1HR": {
+              "description": "Ethernet MAC address 1 high register\n          (ETH_MACA1HR)",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA1H": {
+                    "description": "MAC address1 high",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MBC": {
+                    "description": "Mask byte control",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "SA": {
+                    "description": "Source address",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "AE": {
+                    "description": "Address enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA1LR": {
+              "description": "Ethernet MAC address1 low\n          register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA1L": {
+                    "description": "MAC address1 low",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACA2HR": {
+              "description": "Ethernet MAC address 2 high register\n          (ETH_MACA2HR)",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 80,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETH_MACA2HR": {
+                    "description": "Ethernet MAC address 2 high\n              register",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MBC": {
+                    "description": "Mask byte control",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "SA": {
+                    "description": "Source address",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "AE": {
+                    "description": "Address enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA2LR": {
+              "description": "Ethernet MAC address 2 low\n          register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA2L": {
+                    "description": "MAC address2 low",
+                    "offset": 0,
+                    "size": 31
+                  }
+                }
+              }
+            },
+            "MACA3HR": {
+              "description": "Ethernet MAC address 3 high register\n          (ETH_MACA3HR)",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA3H": {
+                    "description": "MAC address3 high",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MBC": {
+                    "description": "Mask byte control",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "SA": {
+                    "description": "Source address",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "AE": {
+                    "description": "Address enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA3LR": {
+              "description": "Ethernet MAC address 3 low\n          register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MBCA3L": {
+                    "description": "MAC address3 low",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ETHERNET_MMC": {
+        "description": "Ethernet: MAC management counters",
+        "children": {
+          "registers": {
+            "MMCCR": {
+              "description": "Ethernet MMC control register\n          (ETH_MMCCR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CR": {
+                    "description": "Counter reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CSR": {
+                    "description": "Counter stop rollover",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ROR": {
+                    "description": "Reset on read",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MCF": {
+                    "description": "MMC counter freeze",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCRIR": {
+              "description": "Ethernet MMC receive interrupt register\n          (ETH_MMCRIR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFCES": {
+                    "description": "Received frames CRC error\n              status",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RFAES": {
+                    "description": "Received frames alignment error\n              status",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RGUFS": {
+                    "description": "Received Good Unicast Frames\n              Status",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCTIR": {
+              "description": "Ethernet MMC transmit interrupt register\n          (ETH_MMCTIR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TGFSCS": {
+                    "description": "Transmitted good frames single collision\n              status",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TGFMSCS": {
+                    "description": "Transmitted good frames more single\n              collision status",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TGFS": {
+                    "description": "Transmitted good frames\n              status",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCRIMR": {
+              "description": "Ethernet MMC receive interrupt mask register\n          (ETH_MMCRIMR)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFCEM": {
+                    "description": "Received frame CRC error\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RFAEM": {
+                    "description": "Received frames alignment error\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RGUFM": {
+                    "description": "Received good unicast frames\n              mask",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCTIMR": {
+              "description": "Ethernet MMC transmit interrupt mask\n          register (ETH_MMCTIMR)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TGFSCM": {
+                    "description": "Transmitted good frames single collision\n              mask",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TGFMSCM": {
+                    "description": "Transmitted good frames more single\n              collision mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TGFM": {
+                    "description": "Transmitted good frames\n              mask",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCTGFSCCR": {
+              "description": "Ethernet MMC transmitted good frames after a\n          single collision counter",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TGFSCC": {
+                    "description": "Transmitted good frames after a single\n              collision counter",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCTGFMSCCR": {
+              "description": "Ethernet MMC transmitted good frames after\n          more than a single collision",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TGFMSCC": {
+                    "description": "Transmitted good frames after more than\n              a single collision counter",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCTGFCR": {
+              "description": "Ethernet MMC transmitted good frames counter\n          register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TGFC": {
+                    "description": "Transmitted good frames\n              counter",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCRFCECR": {
+              "description": "Ethernet MMC received frames with CRC error\n          counter register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RFCFC": {
+                    "description": "Received frames with CRC error\n              counter",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCRFAECR": {
+              "description": "Ethernet MMC received frames with alignment\n          error counter register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RFAEC": {
+                    "description": "Received frames with alignment error\n              counter",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCRGUFCR": {
+              "description": "MMC received good unicast frames counter\n          register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RGUFC": {
+                    "description": "Received good unicast frames\n              counter",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_PWRCLK": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_PCGCCTL": {
+              "description": "OTG_FS power and clock gating control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STPPCLK": {
+                    "description": "Stop PHY clock",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "GATEHCLK": {
+                    "description": "Gate HCLK",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PHYSUSP": {
+                    "description": "PHY Suspended",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM9": {
+        "description": "General purpose timer",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2M": {
+                    "description": "Output Compare 2 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "Output Compare 2 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "Output Compare 2 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PSC": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC1PSC": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2": {
+                    "description": "Capture/Compare 2 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_HOST": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_HCFG": {
+              "description": "OTG_FS host configuration register\n          (OTG_FS_HCFG)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSLSPCS": {
+                    "description": "FS/LS PHY clock select",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "FSLSS": {
+                    "description": "FS- and LS-only support",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "HFIR": {
+              "description": "OTG_FS Host frame interval\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 60000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRIVL": {
+                    "description": "Frame interval",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_HFNUM": {
+              "description": "OTG_FS host frame number/frame time\n          remaining register (OTG_FS_HFNUM)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 16383,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FRNUM": {
+                    "description": "Frame number",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "FTREM": {
+                    "description": "Frame time remaining",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_HPTXSTS": {
+              "description": "OTG_FS_Host periodic transmit FIFO/queue\n          status register (OTG_FS_HPTXSTS)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 524544,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTXFSAVL": {
+                    "description": "Periodic transmit data FIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PTXQSAV": {
+                    "description": "Periodic transmit request queue space\n              available",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "PTXQTOP": {
+                    "description": "Top of the periodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "HAINT": {
+              "description": "OTG_FS Host all channels interrupt\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HAINT": {
+                    "description": "Channel interrupts",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "HAINTMSK": {
+              "description": "OTG_FS host all channels interrupt mask\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HAINTM": {
+                    "description": "Channel interrupt mask",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_HPRT": {
+              "description": "OTG_FS host port control and status register\n          (OTG_FS_HPRT)",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCSTS": {
+                    "description": "Port connect status",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PCDET": {
+                    "description": "Port connect detected",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PENA": {
+                    "description": "Port enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PENCHNG": {
+                    "description": "Port enable/disable change",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "POCA": {
+                    "description": "Port overcurrent active",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "POCCHNG": {
+                    "description": "Port overcurrent change",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PRES": {
+                    "description": "Port resume",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PSUSP": {
+                    "description": "Port suspend",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PRST": {
+                    "description": "Port reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PLSTS": {
+                    "description": "Port line status",
+                    "offset": 10,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PPWR": {
+                    "description": "Port power",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PTCTL": {
+                    "description": "Port test control",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "PSPD": {
+                    "description": "Port speed",
+                    "offset": 17,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR0": {
+              "description": "OTG_FS host channel-0 characteristics\n          register (OTG_FS_HCCHAR0)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR1": {
+              "description": "OTG_FS host channel-1 characteristics\n          register (OTG_FS_HCCHAR1)",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR2": {
+              "description": "OTG_FS host channel-2 characteristics\n          register (OTG_FS_HCCHAR2)",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR3": {
+              "description": "OTG_FS host channel-3 characteristics\n          register (OTG_FS_HCCHAR3)",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR4": {
+              "description": "OTG_FS host channel-4 characteristics\n          register (OTG_FS_HCCHAR4)",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR5": {
+              "description": "OTG_FS host channel-5 characteristics\n          register (OTG_FS_HCCHAR5)",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR6": {
+              "description": "OTG_FS host channel-6 characteristics\n          register (OTG_FS_HCCHAR6)",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR7": {
+              "description": "OTG_FS host channel-7 characteristics\n          register (OTG_FS_HCCHAR7)",
+              "offset": 480,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT0": {
+              "description": "OTG_FS host channel-0 interrupt register\n          (OTG_FS_HCINT0)",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT1": {
+              "description": "OTG_FS host channel-1 interrupt register\n          (OTG_FS_HCINT1)",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT2": {
+              "description": "OTG_FS host channel-2 interrupt register\n          (OTG_FS_HCINT2)",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT3": {
+              "description": "OTG_FS host channel-3 interrupt register\n          (OTG_FS_HCINT3)",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT4": {
+              "description": "OTG_FS host channel-4 interrupt register\n          (OTG_FS_HCINT4)",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT5": {
+              "description": "OTG_FS host channel-5 interrupt register\n          (OTG_FS_HCINT5)",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT6": {
+              "description": "OTG_FS host channel-6 interrupt register\n          (OTG_FS_HCINT6)",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT7": {
+              "description": "OTG_FS host channel-7 interrupt register\n          (OTG_FS_HCINT7)",
+              "offset": 488,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK0": {
+              "description": "OTG_FS host channel-0 mask register\n          (OTG_FS_HCINTMSK0)",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK1": {
+              "description": "OTG_FS host channel-1 mask register\n          (OTG_FS_HCINTMSK1)",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK2": {
+              "description": "OTG_FS host channel-2 mask register\n          (OTG_FS_HCINTMSK2)",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK3": {
+              "description": "OTG_FS host channel-3 mask register\n          (OTG_FS_HCINTMSK3)",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK4": {
+              "description": "OTG_FS host channel-4 mask register\n          (OTG_FS_HCINTMSK4)",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK5": {
+              "description": "OTG_FS host channel-5 mask register\n          (OTG_FS_HCINTMSK5)",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK6": {
+              "description": "OTG_FS host channel-6 mask register\n          (OTG_FS_HCINTMSK6)",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK7": {
+              "description": "OTG_FS host channel-7 mask register\n          (OTG_FS_HCINTMSK7)",
+              "offset": 492,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ0": {
+              "description": "OTG_FS host channel-0 transfer size\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ1": {
+              "description": "OTG_FS host channel-1 transfer size\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ2": {
+              "description": "OTG_FS host channel-2 transfer size\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ3": {
+              "description": "OTG_FS host channel-3 transfer size\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ4": {
+              "description": "OTG_FS host channel-x transfer size\n          register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ5": {
+              "description": "OTG_FS host channel-5 transfer size\n          register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ6": {
+              "description": "OTG_FS host channel-6 transfer size\n          register",
+              "offset": 464,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ7": {
+              "description": "OTG_FS host channel-7 transfer size\n          register",
+              "offset": 496,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM10": {
+        "description": "General purpose timer",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC1PSC": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_GLOBAL": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_GOTGCTL": {
+              "description": "OTG_FS control and status register\n          (OTG_FS_GOTGCTL)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRQSCS": {
+                    "description": "Session request success",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SRQ": {
+                    "description": "Session request",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HNGSCS": {
+                    "description": "Host negotiation success",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HNPRQ": {
+                    "description": "HNP request",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HSHNPEN": {
+                    "description": "Host set HNP enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DHNPEN": {
+                    "description": "Device HNP enabled",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CIDSTS": {
+                    "description": "Connector ID status",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DBCT": {
+                    "description": "Long/short debounce time",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ASVLD": {
+                    "description": "A-session valid",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BSVLD": {
+                    "description": "B-session valid",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FS_GOTGINT": {
+              "description": "OTG_FS interrupt register\n          (OTG_FS_GOTGINT)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEDET": {
+                    "description": "Session end detected",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SRSSCHG": {
+                    "description": "Session request success status\n              change",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNSSCHG": {
+                    "description": "Host negotiation success status\n              change",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HNGDET": {
+                    "description": "Host negotiation detected",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ADTOCHG": {
+                    "description": "A-device timeout change",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DBCDNE": {
+                    "description": "Debounce done",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GAHBCFG": {
+              "description": "OTG_FS AHB configuration register\n          (OTG_FS_GAHBCFG)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GINT": {
+                    "description": "Global interrupt mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXFELVL": {
+                    "description": "TxFIFO empty level",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PTXFELVL": {
+                    "description": "Periodic TxFIFO empty\n              level",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GUSBCFG": {
+              "description": "OTG_FS USB configuration register\n          (OTG_FS_GUSBCFG)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 2560,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TOCAL": {
+                    "description": "FS timeout calibration",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "PHYSEL": {
+                    "description": "Full Speed serial transceiver\n              select",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SRPCAP": {
+                    "description": "SRP-capable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNPCAP": {
+                    "description": "HNP-capable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TRDT": {
+                    "description": "USB turnaround time",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "FHMOD": {
+                    "description": "Force host mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FDMOD": {
+                    "description": "Force device mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CTXPKT": {
+                    "description": "Corrupt Tx packet",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GRSTCTL": {
+              "description": "OTG_FS reset register\n          (OTG_FS_GRSTCTL)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 536870912,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSRST": {
+                    "description": "Core soft reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HSRST": {
+                    "description": "HCLK soft reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FCRST": {
+                    "description": "Host frame counter reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RXFFLSH": {
+                    "description": "RxFIFO flush",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TXFFLSH": {
+                    "description": "TxFIFO flush",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "AHBIDL": {
+                    "description": "AHB master idle",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FS_GINTSTS": {
+              "description": "OTG_FS core interrupt register\n          (OTG_FS_GINTSTS)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 67108896,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CMOD": {
+                    "description": "Current mode of operation",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMIS": {
+                    "description": "Mode mismatch interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGINT": {
+                    "description": "OTG interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOF": {
+                    "description": "Start of frame",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFLVL": {
+                    "description": "RxFIFO non-empty",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NPTXFE": {
+                    "description": "Non-periodic TxFIFO empty",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GINAKEFF": {
+                    "description": "Global IN non-periodic NAK\n              effective",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GOUTNAKEFF": {
+                    "description": "Global OUT NAK effective",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ESUSP": {
+                    "description": "Early suspend",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "USBSUSP": {
+                    "description": "USB suspend",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMDNE": {
+                    "description": "Enumeration done",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOODRP": {
+                    "description": "Isochronous OUT packet dropped\n              interrupt",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPF": {
+                    "description": "End of periodic frame\n              interrupt",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IEPINT": {
+                    "description": "IN endpoint interrupt",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IISOIXFR": {
+                    "description": "Incomplete isochronous IN\n              transfer",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "IPXFR_INCOMPISOOUT": {
+                    "description": "Incomplete periodic transfer(Host\n              mode)/Incomplete isochronous OUT transfer(Device\n              mode)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HPRTINT": {
+                    "description": "Host port interrupt",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCINT": {
+                    "description": "Host channels interrupt",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PTXFE": {
+                    "description": "Periodic TxFIFO empty",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CIDSCHG": {
+                    "description": "Connector ID status change",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCINT": {
+                    "description": "Disconnect detected\n              interrupt",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SRQINT": {
+                    "description": "Session request/new session detected\n              interrupt",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WKUPINT": {
+                    "description": "Resume/remote wakeup detected\n              interrupt",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GINTMSK": {
+              "description": "OTG_FS interrupt mask register\n          (OTG_FS_GINTMSK)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMISM": {
+                    "description": "Mode mismatch interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGINT": {
+                    "description": "OTG interrupt mask",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SOFM": {
+                    "description": "Start of frame mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFLVLM": {
+                    "description": "Receive FIFO non-empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "NPTXFEM": {
+                    "description": "Non-periodic TxFIFO empty\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GINAKEFFM": {
+                    "description": "Global non-periodic IN NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GONAKEFFM": {
+                    "description": "Global OUT NAK effective\n              mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ESUSPM": {
+                    "description": "Early suspend mask",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "USBSUSPM": {
+                    "description": "USB suspend mask",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset mask",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMDNEM": {
+                    "description": "Enumeration done mask",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOODRPM": {
+                    "description": "Isochronous OUT packet dropped interrupt\n              mask",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPFM": {
+                    "description": "End of periodic frame interrupt\n              mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPMISM": {
+                    "description": "Endpoint mismatch interrupt\n              mask",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "IEPINT": {
+                    "description": "IN endpoints interrupt\n              mask",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoints interrupt\n              mask",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IISOIXFRM": {
+                    "description": "Incomplete isochronous IN transfer\n              mask",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "IPXFRM_IISOOXFRM": {
+                    "description": "Incomplete periodic transfer mask(Host\n              mode)/Incomplete isochronous OUT transfer mask(Device\n              mode)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "PRTIM": {
+                    "description": "Host port interrupt mask",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCIM": {
+                    "description": "Host channels interrupt\n              mask",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PTXFEM": {
+                    "description": "Periodic TxFIFO empty mask",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CIDSCHGM": {
+                    "description": "Connector ID status change\n              mask",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCINT": {
+                    "description": "Disconnect detected interrupt\n              mask",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SRQIM": {
+                    "description": "Session request/new session detected\n              interrupt mask",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WUIM": {
+                    "description": "Resume/remote wakeup detected interrupt\n              mask",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GRXSTSR_Device": {
+              "description": "OTG_FS Receive status debug read(Device\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  },
+                  "FRMNUM": {
+                    "description": "Frame number",
+                    "offset": 21,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "FS_GRXSTSR_Host": {
+              "description": "OTG_FS Receive status debug read(Host\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  },
+                  "FRMNUM": {
+                    "description": "Frame number",
+                    "offset": 21,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "FS_GRXFSIZ": {
+              "description": "OTG_FS Receive FIFO size register\n          (OTG_FS_GRXFSIZ)",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFD": {
+                    "description": "RxFIFO depth",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_GNPTXFSIZ_Device": {
+              "description": "OTG_FS non-periodic transmit FIFO size\n          register (Device mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX0FSA": {
+                    "description": "Endpoint 0 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "TX0FD": {
+                    "description": "Endpoint 0 TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_GNPTXFSIZ_Host": {
+              "description": "OTG_FS non-periodic transmit FIFO size\n          register (Host mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NPTXFSA": {
+                    "description": "Non-periodic transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "NPTXFD": {
+                    "description": "Non-periodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_GNPTXSTS": {
+              "description": "OTG_FS non-periodic transmit FIFO/queue\n          status register (OTG_FS_GNPTXSTS)",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 524800,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "NPTXFSAV": {
+                    "description": "Non-periodic TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "NPTQXSAV": {
+                    "description": "Non-periodic transmit request queue\n              space available",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "NPTXQTOP": {
+                    "description": "Top of the non-periodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "FS_GCCFG": {
+              "description": "OTG_FS general core configuration register\n          (OTG_FS_GCCFG)",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWRDWN": {
+                    "description": "Power down",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "VBUSASEN": {
+                    "description": "Enable the VBUS sensing\n              device",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "VBUSBSEN": {
+                    "description": "Enable the VBUS sensing\n              device",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SOFOUTEN": {
+                    "description": "SOF output enable",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_CID": {
+              "description": "core ID register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 4096,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRODUCT_ID": {
+                    "description": "Product ID field",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FS_HPTXFSIZ": {
+              "description": "OTG_FS Host periodic transmit FIFO size\n          register (OTG_FS_HPTXFSIZ)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 33555968,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTXSA": {
+                    "description": "Host periodic TxFIFO start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PTXFSIZ": {
+                    "description": "Host periodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPTXF1": {
+              "description": "OTG_FS device IN endpoint transmit FIFO size\n          register (OTG_FS_DIEPTXF2)",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFO2 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPTXF2": {
+              "description": "OTG_FS device IN endpoint transmit FIFO size\n          register (OTG_FS_DIEPTXF3)",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFO3 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPTXF3": {
+              "description": "OTG_FS device IN endpoint transmit FIFO size\n          register (OTG_FS_DIEPTXF4)",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFO4 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_DEVICE": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_DCFG": {
+              "description": "OTG_FS device configuration register\n          (OTG_FS_DCFG)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 35651584,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DSPD": {
+                    "description": "Device speed",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "NZLSOHSK": {
+                    "description": "Non-zero-length status OUT\n              handshake",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 4,
+                    "size": 7
+                  },
+                  "PFIVL": {
+                    "description": "Periodic frame interval",
+                    "offset": 11,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_DCTL": {
+              "description": "OTG_FS device control register\n          (OTG_FS_DCTL)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWUSIG": {
+                    "description": "Remote wakeup signaling",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SDIS": {
+                    "description": "Soft disconnect",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GINSTS": {
+                    "description": "Global IN NAK status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GONSTS": {
+                    "description": "Global OUT NAK status",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TCTL": {
+                    "description": "Test control",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SGINAK": {
+                    "description": "Set global IN NAK",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CGINAK": {
+                    "description": "Clear global IN NAK",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SGONAK": {
+                    "description": "Set global OUT NAK",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CGONAK": {
+                    "description": "Clear global OUT NAK",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "POPRGDNE": {
+                    "description": "Power-on programming done",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_DSTS": {
+              "description": "OTG_FS device status register\n          (OTG_FS_DSTS)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SUSPSTS": {
+                    "description": "Suspend status",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ENUMSPD": {
+                    "description": "Enumerated speed",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "EERR": {
+                    "description": "Erratic error",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FNSOF": {
+                    "description": "Frame number of the received\n              SOF",
+                    "offset": 8,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "FS_DIEPMSK": {
+              "description": "OTG_FS device IN endpoint common interrupt\n          mask register (OTG_FS_DIEPMSK)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOM": {
+                    "description": "Timeout condition mask (Non-isochronous\n              endpoints)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFEMSK": {
+                    "description": "IN token received when TxFIFO empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNMM": {
+                    "description": "IN token received with EP mismatch\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INEPNEM": {
+                    "description": "IN endpoint NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_DOEPMSK": {
+              "description": "OTG_FS device OUT endpoint common interrupt\n          mask register (OTG_FS_DOEPMSK)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUPM": {
+                    "description": "SETUP phase done mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDM": {
+                    "description": "OUT token received when endpoint\n              disabled mask",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_DAINT": {
+              "description": "OTG_FS device all endpoints interrupt\n          register (OTG_FS_DAINT)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IEPINT": {
+                    "description": "IN endpoint interrupt bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt\n              bits",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DAINTMSK": {
+              "description": "OTG_FS all endpoints interrupt mask register\n          (OTG_FS_DAINTMSK)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEPM": {
+                    "description": "IN EP interrupt mask bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt\n              bits",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DVBUSDIS": {
+              "description": "OTG_FS device VBUS discharge time\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 6103,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VBUSDT": {
+                    "description": "Device VBUS discharge time",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DVBUSPULSE": {
+              "description": "OTG_FS device VBUS pulsing time\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 1464,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DVBUSP": {
+                    "description": "Device VBUS pulsing time",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DIEPEMPMSK": {
+              "description": "OTG_FS device IN endpoint FIFO empty\n          interrupt mask register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXFEM": {
+                    "description": "IN EP Tx FIFO empty interrupt mask\n              bits",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPCTL0": {
+              "description": "OTG_FS device control IN endpoint 0 control\n          register (OTG_FS_DIEPCTL0)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "STALL": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DIEPCTL1": {
+              "description": "OTG device endpoint-1 control\n          register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM_SD1PID": {
+                    "description": "SODDFRM/SD1PID",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "TXFNUM",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEPCTL2": {
+              "description": "OTG device endpoint-2 control\n          register",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "TXFNUM",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEPCTL3": {
+              "description": "OTG device endpoint-3 control\n          register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "TXFNUM",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEPCTL0": {
+              "description": "device endpoint-0 control\n          register",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DOEPCTL1": {
+              "description": "device endpoint-1 control\n          register",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEPCTL2": {
+              "description": "device endpoint-2 control\n          register",
+              "offset": 832,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEPCTL3": {
+              "description": "device endpoint-3 control\n          register",
+              "offset": 864,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEPINT0": {
+              "description": "device endpoint-x interrupt\n          register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPINT1": {
+              "description": "device endpoint-1 interrupt\n          register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPINT2": {
+              "description": "device endpoint-2 interrupt\n          register",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPINT3": {
+              "description": "device endpoint-3 interrupt\n          register",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT0": {
+              "description": "device endpoint-0 interrupt\n          register",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT1": {
+              "description": "device endpoint-1 interrupt\n          register",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT2": {
+              "description": "device endpoint-2 interrupt\n          register",
+              "offset": 840,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT3": {
+              "description": "device endpoint-3 interrupt\n          register",
+              "offset": 872,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ0": {
+              "description": "device endpoint-0 transfer size\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 2
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ0": {
+              "description": "device OUT endpoint-0 transfer size\n          register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STUPCNT": {
+                    "description": "SETUP packet count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ1": {
+              "description": "device endpoint-1 transfer size\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ2": {
+              "description": "device endpoint-2 transfer size\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ3": {
+              "description": "device endpoint-3 transfer size\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DTXFSTS0": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DTXFSTS1": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DTXFSTS2": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DTXFSTS3": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ1": {
+              "description": "device OUT endpoint-1 transfer size\n          register",
+              "offset": 816,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ2": {
+              "description": "device OUT endpoint-2 transfer size\n          register",
+              "offset": 848,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ3": {
+              "description": "device OUT endpoint-3 transfer size\n          register",
+              "offset": 880,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USB": {
+        "description": "Universal serial bus full-speed device\n      interface",
+        "children": {
+          "registers": {
+            "EP0R": {
+              "description": "endpoint 0 register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EP1R": {
+              "description": "endpoint 1 register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EP2R": {
+              "description": "endpoint 2 register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EP3R": {
+              "description": "endpoint 3 register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EP4R": {
+              "description": "endpoint 4 register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EP5R": {
+              "description": "endpoint 5 register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EP6R": {
+              "description": "endpoint 6 register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EP7R": {
+              "description": "endpoint 7 register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNTR": {
+              "description": "control register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRES": {
+                    "description": "Force USB Reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PDWN": {
+                    "description": "Power down",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LPMODE": {
+                    "description": "Low-power mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FSUSP": {
+                    "description": "Force suspend",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESUME": {
+                    "description": "Resume request",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ESOFM": {
+                    "description": "Expected start of frame interrupt\n              mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SOFM": {
+                    "description": "Start of frame interrupt\n              mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESETM": {
+                    "description": "USB reset interrupt mask",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SUSPM": {
+                    "description": "Suspend mode interrupt\n              mask",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WKUPM": {
+                    "description": "Wakeup interrupt mask",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ERRM": {
+                    "description": "Error interrupt mask",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PMAOVRM": {
+                    "description": "Packet memory area over / underrun\n              interrupt mask",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTRM": {
+                    "description": "Correct transfer interrupt\n              mask",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ISTR": {
+              "description": "interrupt status register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EP_ID": {
+                    "description": "Endpoint Identifier",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "DIR": {
+                    "description": "Direction of transaction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ESOF": {
+                    "description": "Expected start frame",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SOF": {
+                    "description": "start of frame",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "reset request",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SUSP": {
+                    "description": "Suspend mode request",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WKUP": {
+                    "description": "Wakeup",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ERR": {
+                    "description": "Error",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PMAOVR": {
+                    "description": "Packet memory area over /\n              underrun",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR": {
+                    "description": "Correct transfer",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FNR": {
+              "description": "frame number register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FN": {
+                    "description": "Frame number",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "LSOF": {
+                    "description": "Lost SOF",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "LCK": {
+                    "description": "Locked",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RXDM": {
+                    "description": "Receive data - line status",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RXDP": {
+                    "description": "Receive data + line status",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DADDR": {
+              "description": "device address",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADD": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "EF": {
+                    "description": "Enable function",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTABLE": {
+              "description": "Buffer table address",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BTABLE": {
+                    "description": "Buffer table",
+                    "offset": 3,
+                    "size": 13
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM6": {
+        "description": "Basic timer",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Low Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FLASH": {
+        "description": "FLASH",
+        "children": {
+          "registers": {
+            "ACR": {
+              "description": "Flash access control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 48,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LATENCY": {
+                    "description": "Latency",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "HLFCYA": {
+                    "description": "Flash half cycle access\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PRFTBE": {
+                    "description": "Prefetch buffer enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PRFTBS": {
+                    "description": "Prefetch buffer status",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "KEYR": {
+              "description": "Flash key register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "KEY": {
+                    "description": "FPEC key",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OPTKEYR": {
+              "description": "Flash option key register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "OPTKEY": {
+                    "description": "Option byte key",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EOP": {
+                    "description": "End of operation",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WRPRTERR": {
+                    "description": "Write protection error",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PGERR": {
+                    "description": "Programming error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BSY": {
+                    "description": "Busy",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "Control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PG": {
+                    "description": "Programming",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PER": {
+                    "description": "Page Erase",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MER": {
+                    "description": "Mass Erase",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OPTPG": {
+                    "description": "Option byte programming",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OPTER": {
+                    "description": "Option byte erase",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "STRT": {
+                    "description": "Start",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LOCK": {
+                    "description": "Lock",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OPTWRE": {
+                    "description": "Option bytes write enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EOPIE": {
+                    "description": "End of operation interrupt\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AR": {
+              "description": "Flash address register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "FAR": {
+                    "description": "Flash Address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OBR": {
+              "description": "Option byte register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 67108860,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "OPTERR": {
+                    "description": "Option byte error",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RDPRT": {
+                    "description": "Read protection",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WDG_SW": {
+                    "description": "WDG_SW",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "nRST_STOP": {
+                    "description": "nRST_STOP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "nRST_STDBY": {
+                    "description": "nRST_STDBY",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "Data0": {
+                    "description": "Data0",
+                    "offset": 10,
+                    "size": 8
+                  },
+                  "Data1": {
+                    "description": "Data1",
+                    "offset": 18,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "WRPR": {
+              "description": "Write protection register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WRP": {
+                    "description": "Write protect",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2C1": {
+        "description": "Inter integrated circuit",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "Control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWRST": {
+                    "description": "Software reset",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ALERT": {
+                    "description": "SMBus alert",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PEC": {
+                    "description": "Packet error checking",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "POS": {
+                    "description": "Acknowledge/PEC Position (for data\n              reception)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "Acknowledge enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "Stop generation",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "START": {
+                    "description": "Start generation",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "NOSTRETCH": {
+                    "description": "Clock stretching disable (Slave\n              mode)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ENGC": {
+                    "description": "General call enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ENPEC": {
+                    "description": "PEC enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ENARP": {
+                    "description": "ARP enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SMBTYPE": {
+                    "description": "SMBus type",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SMBUS": {
+                    "description": "SMBus mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PE": {
+                    "description": "Peripheral enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "Control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LAST": {
+                    "description": "DMA last transfer",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DMAEN": {
+                    "description": "DMA requests enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ITBUFEN": {
+                    "description": "Buffer interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ITEVTEN": {
+                    "description": "Event interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ITERREN": {
+                    "description": "Error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FREQ": {
+                    "description": "Peripheral clock frequency",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "OAR1": {
+              "description": "Own address register 1",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDMODE": {
+                    "description": "Addressing mode (slave\n              mode)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ADD10": {
+                    "description": "Interface address",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ADD7": {
+                    "description": "Interface address",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "ADD0": {
+                    "description": "Interface address",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OAR2": {
+              "description": "Own address register 2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADD2": {
+                    "description": "Interface address",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "ENDUAL": {
+                    "description": "Dual addressing mode\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "Data register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "8-bit data register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SR1": {
+              "description": "Status register 1",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMBALERT": {
+                    "description": "SMBus alert",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TIMEOUT": {
+                    "description": "Timeout or Tlow error",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PECERR": {
+                    "description": "PEC Error in reception",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OVR": {
+                    "description": "Overrun/Underrun",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AF": {
+                    "description": "Acknowledge failure",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ARLO": {
+                    "description": "Arbitration lost (master\n              mode)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Bus error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TxE": {
+                    "description": "Data register empty\n              (transmitters)",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RxNE": {
+                    "description": "Data register not empty\n              (receivers)",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STOPF": {
+                    "description": "Stop detection (slave\n              mode)",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ADD10": {
+                    "description": "10-bit header sent (Master\n              mode)",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BTF": {
+                    "description": "Byte transfer finished",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ADDR": {
+                    "description": "Address sent (master mode)/matched\n              (slave mode)",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SB": {
+                    "description": "Start bit (Master mode)",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SR2": {
+              "description": "Status register 2",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PEC": {
+                    "description": "acket error checking\n              register",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DUALF": {
+                    "description": "Dual flag (Slave mode)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SMBHOST": {
+                    "description": "SMBus host header (Slave\n              mode)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SMBDEFAULT": {
+                    "description": "SMBus device default address (Slave\n              mode)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GENCALL": {
+                    "description": "General call address (Slave\n              mode)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TRA": {
+                    "description": "Transmitter/receiver",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "Bus busy",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MSL": {
+                    "description": "Master/slave",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "Clock control register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "F_S": {
+                    "description": "I2C master mode selection",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "DUTY": {
+                    "description": "Fast mode duty cycle",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CCR": {
+                    "description": "Clock control register in Fast/Standard\n              mode (Master mode)",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "TRISE": {
+              "description": "TRISE register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRISE": {
+                    "description": "Maximum rise time in Fast/Standard mode\n              (Master mode)",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CRC": {
+        "description": "CRC calculation unit",
+        "children": {
+          "registers": {
+            "DR": {
+              "description": "Data register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data Register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "Independent Data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IDR": {
+                    "description": "Independent Data register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "Control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "RESET": {
+                    "description": "Reset bit",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI1": {
+        "description": "Serial peripheral interface",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BIDIMODE": {
+                    "description": "Bidirectional data mode\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BIDIOE": {
+                    "description": "Output enable in bidirectional\n              mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CRCEN": {
+                    "description": "Hardware CRC calculation\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CRCNEXT": {
+                    "description": "CRC transfer next",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DFF": {
+                    "description": "Data frame format",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RXONLY": {
+                    "description": "Receive only",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SSM": {
+                    "description": "Software slave management",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SSI": {
+                    "description": "Internal slave select",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LSBFIRST": {
+                    "description": "Frame format",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SPE": {
+                    "description": "SPI enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BR": {
+                    "description": "Baud rate control",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "MSTR": {
+                    "description": "Master selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CPOL": {
+                    "description": "Clock polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CPHA": {
+                    "description": "Clock phase",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXEIE": {
+                    "description": "Tx buffer empty interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RX buffer not empty interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SSOE": {
+                    "description": "SS output enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXDMAEN": {
+                    "description": "Tx buffer DMA enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXDMAEN": {
+                    "description": "Rx buffer DMA enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BSY": {
+                    "description": "Busy flag",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVR": {
+                    "description": "Overrun flag",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MODF": {
+                    "description": "Mode fault",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRCERR": {
+                    "description": "CRC error flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "UDR": {
+                    "description": "Underrun flag",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CHSIDE": {
+                    "description": "Channel side",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXE": {
+                    "description": "Transmit buffer empty",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXNE": {
+                    "description": "Receive buffer not empty",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "data register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CRCPR": {
+              "description": "CRC polynomial register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRCPOLY": {
+                    "description": "CRC polynomial register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RXCRCR": {
+              "description": "RX CRC register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RxCRC": {
+                    "description": "Rx CRC register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TXCRCR": {
+              "description": "TX CRC register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TxCRC": {
+                    "description": "Tx CRC register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "I2SCFGR": {
+              "description": "I2S configuration register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "I2SMOD": {
+                    "description": "I2S mode selection",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "I2SE": {
+                    "description": "I2S Enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "I2SCFG": {
+                    "description": "I2S configuration mode",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PCMSYNC": {
+                    "description": "PCM frame synchronization",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "I2SSTD": {
+                    "description": "I2S standard selection",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CKPOL": {
+                    "description": "Steady state clock\n              polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DATLEN": {
+                    "description": "Data length to be\n              transferred",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "CHLEN": {
+                    "description": "Channel length (number of bits per audio\n              channel)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "I2SPR": {
+              "description": "I2S prescaler register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 10,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCKOE": {
+                    "description": "Master clock output enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODD": {
+                    "description": "Odd factor for the\n              prescaler",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "I2SDIV": {
+                    "description": "I2S Linear prescaler",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UART5": {
+        "description": "Universal asynchronous receiver\n      transmitter",
+        "children": {
+          "registers": {
+            "SR": {
+              "description": "UART4_SR",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PE": {
+                    "description": "PE",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FE": {
+                    "description": "FE",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NE": {
+                    "description": "NE",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ORE": {
+                    "description": "ORE",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IDLE": {
+                    "description": "IDLE",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXNE": {
+                    "description": "RXNE",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TC": {
+                    "description": "TC",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXE": {
+                    "description": "TXE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LBD": {
+                    "description": "LBD",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "UART4_DR",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "DR",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "BRR": {
+              "description": "UART4_BRR",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIV_Fraction": {
+                    "description": "DIV_Fraction",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "DIV_Mantissa": {
+                    "description": "DIV_Mantissa",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "UART4_CR1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SBK": {
+                    "description": "SBK",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RWU": {
+                    "description": "RWU",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RE": {
+                    "description": "RE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TE": {
+                    "description": "TE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IDLEIE": {
+                    "description": "IDLEIE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RXNEIE",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "TCIE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXEIE": {
+                    "description": "TXEIE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PEIE": {
+                    "description": "PEIE",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PS": {
+                    "description": "PS",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PCE": {
+                    "description": "PCE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAKE": {
+                    "description": "WAKE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "M": {
+                    "description": "M",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "UE": {
+                    "description": "UE",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "UART4_CR2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADD": {
+                    "description": "ADD",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "LBDL": {
+                    "description": "LBDL",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LBDIE": {
+                    "description": "LBDIE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "STOP",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "LINEN": {
+                    "description": "LINEN",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR3": {
+              "description": "UART4_CR3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IrDA mode enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRLP": {
+                    "description": "IrDA low-power",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "HDSEL": {
+                    "description": "Half-duplex selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DMAT": {
+                    "description": "DMA enable transmitter",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UART4": {
+        "description": "Universal asynchronous receiver\n      transmitter",
+        "children": {
+          "registers": {
+            "SR": {
+              "description": "UART4_SR",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PE": {
+                    "description": "Parity error",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FE": {
+                    "description": "Framing error",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NE": {
+                    "description": "Noise error flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ORE": {
+                    "description": "Overrun error",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IDLE": {
+                    "description": "IDLE line detected",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXNE": {
+                    "description": "Read data register not\n              empty",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TC": {
+                    "description": "Transmission complete",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXE": {
+                    "description": "Transmit data register\n              empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LBD": {
+                    "description": "LIN break detection flag",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "UART4_DR",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "DR",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "BRR": {
+              "description": "UART4_BRR",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIV_Fraction": {
+                    "description": "DIV_Fraction",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "DIV_Mantissa": {
+                    "description": "DIV_Mantissa",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "UART4_CR1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SBK": {
+                    "description": "Send break",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RWU": {
+                    "description": "Receiver wakeup",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RE": {
+                    "description": "Receiver enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TE": {
+                    "description": "Transmitter enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IDLEIE": {
+                    "description": "IDLE interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RXNE interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transmission complete interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXEIE": {
+                    "description": "TXE interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PEIE": {
+                    "description": "PE interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PS": {
+                    "description": "Parity selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PCE": {
+                    "description": "Parity control enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAKE": {
+                    "description": "Wakeup method",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "M": {
+                    "description": "Word length",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "UE": {
+                    "description": "USART enable",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "UART4_CR2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADD": {
+                    "description": "Address of the USART node",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "LBDL": {
+                    "description": "lin break detection length",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LBDIE": {
+                    "description": "LIN break detection interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "STOP bits",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "LINEN": {
+                    "description": "LIN mode enable",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR3": {
+              "description": "UART4_CR3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IrDA mode enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRLP": {
+                    "description": "IrDA low-power",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "HDSEL": {
+                    "description": "Half-duplex selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DMAR": {
+                    "description": "DMA enable receiver",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DMAT": {
+                    "description": "DMA enable transmitter",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USART1": {
+        "description": "Universal synchronous asynchronous receiver\n      transmitter",
+        "children": {
+          "registers": {
+            "SR": {
+              "description": "Status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "CTS flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LBD": {
+                    "description": "LIN break detection flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXE": {
+                    "description": "Transmit data register\n              empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TC": {
+                    "description": "Transmission complete",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNE": {
+                    "description": "Read data register not\n              empty",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLE": {
+                    "description": "IDLE line detected",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ORE": {
+                    "description": "Overrun error",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NE": {
+                    "description": "Noise error flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FE": {
+                    "description": "Framing error",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PE": {
+                    "description": "Parity error",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "Data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data value",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "BRR": {
+              "description": "Baud rate register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIV_Mantissa": {
+                    "description": "mantissa of USARTDIV",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "DIV_Fraction": {
+                    "description": "fraction of USARTDIV",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "Control register 1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UE": {
+                    "description": "USART enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "M": {
+                    "description": "Word length",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAKE": {
+                    "description": "Wakeup method",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PCE": {
+                    "description": "Parity control enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PS": {
+                    "description": "Parity selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PEIE": {
+                    "description": "PE interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXEIE": {
+                    "description": "TXE interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transmission complete interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RXNE interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLEIE": {
+                    "description": "IDLE interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TE": {
+                    "description": "Transmitter enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RE": {
+                    "description": "Receiver enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RWU": {
+                    "description": "Receiver wakeup",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SBK": {
+                    "description": "Send break",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "Control register 2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LINEN": {
+                    "description": "LIN mode enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "STOP bits",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CLKEN": {
+                    "description": "Clock enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CPOL": {
+                    "description": "Clock polarity",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CPHA": {
+                    "description": "Clock phase",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LBCL": {
+                    "description": "Last bit clock pulse",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LBDIE": {
+                    "description": "LIN break detection interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LBDL": {
+                    "description": "lin break detection length",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADD": {
+                    "description": "Address of the USART node",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR3": {
+              "description": "Control register 3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTSIE": {
+                    "description": "CTS interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CTSE": {
+                    "description": "CTS enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RTSE": {
+                    "description": "RTS enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DMAT": {
+                    "description": "DMA enable transmitter",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DMAR": {
+                    "description": "DMA enable receiver",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SCEN": {
+                    "description": "Smartcard mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NACK": {
+                    "description": "Smartcard NACK enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HDSEL": {
+                    "description": "Half-duplex selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IRLP": {
+                    "description": "IrDA low-power",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IrDA mode enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GTPR": {
+              "description": "Guard time and prescaler\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GT": {
+                    "description": "Guard time value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DBG": {
+        "description": "Debug support",
+        "children": {
+          "registers": {
+            "IDCODE": {
+              "description": "DBGMCU_IDCODE",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DEV_ID": {
+                    "description": "DEV_ID",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "REV_ID": {
+                    "description": "REV_ID",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "DBGMCU_CR",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBG_SLEEP": {
+                    "description": "DBG_SLEEP",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DBG_STOP": {
+                    "description": "DBG_STOP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DBG_STANDBY": {
+                    "description": "DBG_STANDBY",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TRACE_IOEN": {
+                    "description": "TRACE_IOEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TRACE_MODE": {
+                    "description": "TRACE_MODE",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DBG_IWDG_STOP": {
+                    "description": "DBG_IWDG_STOP",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DBG_WWDG_STOP": {
+                    "description": "DBG_WWDG_STOP",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DBG_TIM1_STOP": {
+                    "description": "DBG_TIM1_STOP",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DBG_TIM2_STOP": {
+                    "description": "DBG_TIM2_STOP",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DBG_TIM3_STOP": {
+                    "description": "DBG_TIM3_STOP",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DBG_TIM4_STOP": {
+                    "description": "DBG_TIM4_STOP",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "DBG_CAN1_STOP": {
+                    "description": "DBG_CAN1_STOP",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "DBG_I2C1_SMBUS_TIMEOUT": {
+                    "description": "DBG_I2C1_SMBUS_TIMEOUT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "DBG_I2C2_SMBUS_TIMEOUT": {
+                    "description": "DBG_I2C2_SMBUS_TIMEOUT",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DBG_TIM8_STOP": {
+                    "description": "DBG_TIM8_STOP",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "DBG_TIM5_STOP": {
+                    "description": "DBG_TIM5_STOP",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DBG_TIM6_STOP": {
+                    "description": "DBG_TIM6_STOP",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBG_TIM7_STOP": {
+                    "description": "DBG_TIM7_STOP",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "DBG_CAN2_STOP": {
+                    "description": "DBG_CAN2_STOP",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DAC": {
+        "description": "Digital to analog converter",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "Control register (DAC_CR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN1": {
+                    "description": "DAC channel1 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BOFF1": {
+                    "description": "DAC channel1 output buffer\n              disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TEN1": {
+                    "description": "DAC channel1 trigger\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TSEL1": {
+                    "description": "DAC channel1 trigger\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "WAVE1": {
+                    "description": "DAC channel1 noise/triangle wave\n              generation enable",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MAMP1": {
+                    "description": "DAC channel1 mask/amplitude\n              selector",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "DMAEN1": {
+                    "description": "DAC channel1 DMA enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EN2": {
+                    "description": "DAC channel2 enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BOFF2": {
+                    "description": "DAC channel2 output buffer\n              disable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TEN2": {
+                    "description": "DAC channel2 trigger\n              enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TSEL2": {
+                    "description": "DAC channel2 trigger\n              selection",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "WAVE2": {
+                    "description": "DAC channel2 noise/triangle wave\n              generation enable",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MAMP2": {
+                    "description": "DAC channel2 mask/amplitude\n              selector",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "DMAEN2": {
+                    "description": "DAC channel2 DMA enable",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWTRIGR": {
+              "description": "DAC software trigger register\n          (DAC_SWTRIGR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "SWTRIG1": {
+                    "description": "DAC channel1 software\n              trigger",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SWTRIG2": {
+                    "description": "DAC channel2 software\n              trigger",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DHR12R1": {
+              "description": "DAC channel1 12-bit right-aligned data\n          holding register(DAC_DHR12R1)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12L1": {
+              "description": "DAC channel1 12-bit left aligned data\n          holding register (DAC_DHR12L1)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8R1": {
+              "description": "DAC channel1 8-bit right aligned data\n          holding register (DAC_DHR8R1)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DHR12R2": {
+              "description": "DAC channel2 12-bit right aligned data\n          holding register (DAC_DHR12R2)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12L2": {
+              "description": "DAC channel2 12-bit left aligned data\n          holding register (DAC_DHR12L2)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8R2": {
+              "description": "DAC channel2 8-bit right-aligned data\n          holding register (DAC_DHR8R2)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DHR12RD": {
+              "description": "Dual DAC 12-bit right-aligned data holding\n          register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12\n          Reserved",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit right-aligned\n              data",
+                    "offset": 16,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12LD": {
+              "description": "DUAL DAC 12-bit left aligned data holding\n          register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0\n          Reserved",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit right-aligned\n              data",
+                    "offset": 20,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8RD": {
+              "description": "DUAL DAC 8-bit right aligned data holding\n          register (DAC_DHR8RD), Bits 31:16 Reserved",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "DACC2DHR": {
+                    "description": "DAC channel2 8-bit right-aligned\n              data",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DOR1": {
+              "description": "DAC channel1 data output register\n          (DAC_DOR1)",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DACC1DOR": {
+                    "description": "DAC channel1 data output",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DOR2": {
+              "description": "DAC channel2 data output register\n          (DAC_DOR2)",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DACC2DOR": {
+                    "description": "DAC channel2 data output",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ADC1": {
+        "description": "Analog to digital converter",
+        "children": {
+          "registers": {
+            "SR": {
+              "description": "status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STRT": {
+                    "description": "Regular channel start flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "JSTRT": {
+                    "description": "Injected channel start\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "JEOC": {
+                    "description": "Injected channel end of\n              conversion",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EOC": {
+                    "description": "Regular channel end of\n              conversion",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AWD": {
+                    "description": "Analog watchdog flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "control register 1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AWDEN": {
+                    "description": "Analog watchdog enable on regular\n              channels",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "JAWDEN": {
+                    "description": "Analog watchdog enable on injected\n              channels",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DUALMOD": {
+                    "description": "Dual mode selection",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DISCNUM": {
+                    "description": "Discontinuous mode channel\n              count",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "JDISCEN": {
+                    "description": "Discontinuous mode on injected\n              channels",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DISCEN": {
+                    "description": "Discontinuous mode on regular\n              channels",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "JAUTO": {
+                    "description": "Automatic injected group\n              conversion",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AWDSGL": {
+                    "description": "Enable the watchdog on a single channel\n              in scan mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SCAN": {
+                    "description": "Scan mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "JEOCIE": {
+                    "description": "Interrupt enable for injected\n              channels",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "AWDIE": {
+                    "description": "Analog watchdog interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EOCIE": {
+                    "description": "Interrupt enable for EOC",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "AWDCH": {
+                    "description": "Analog watchdog channel select\n              bits",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSVREFE": {
+                    "description": "Temperature sensor and VREFINT\n              enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "SWSTART": {
+                    "description": "Start conversion of regular\n              channels",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "JSWSTART": {
+                    "description": "Start conversion of injected\n              channels",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EXTTRIG": {
+                    "description": "External trigger conversion mode for\n              regular channels",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EXTSEL": {
+                    "description": "External event select for regular\n              group",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "JEXTTRIG": {
+                    "description": "External trigger conversion mode for\n              injected channels",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "JEXTSEL": {
+                    "description": "External event select for injected\n              group",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "ALIGN": {
+                    "description": "Data alignment",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DMA": {
+                    "description": "Direct memory access mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RSTCAL": {
+                    "description": "Reset calibration",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CAL": {
+                    "description": "A/D calibration",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CONT": {
+                    "description": "Continuous conversion",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ADON": {
+                    "description": "A/D converter ON / OFF",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMPR1": {
+              "description": "sample time register 1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMP10": {
+                    "description": "Channel 10 sample time\n              selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "SMP11": {
+                    "description": "Channel 11 sample time\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "SMP12": {
+                    "description": "Channel 12 sample time\n              selection",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "SMP13": {
+                    "description": "Channel 13 sample time\n              selection",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "SMP14": {
+                    "description": "Channel 14 sample time\n              selection",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "SMP15": {
+                    "description": "Channel 15 sample time\n              selection",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SMP16": {
+                    "description": "Channel 16 sample time\n              selection",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "SMP17": {
+                    "description": "Channel 17 sample time\n              selection",
+                    "offset": 21,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "SMPR2": {
+              "description": "sample time register 2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMP0": {
+                    "description": "Channel 0 sample time\n              selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "SMP1": {
+                    "description": "Channel 1 sample time\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "SMP2": {
+                    "description": "Channel 2 sample time\n              selection",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "SMP3": {
+                    "description": "Channel 3 sample time\n              selection",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "SMP4": {
+                    "description": "Channel 4 sample time\n              selection",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "SMP5": {
+                    "description": "Channel 5 sample time\n              selection",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SMP6": {
+                    "description": "Channel 6 sample time\n              selection",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "SMP7": {
+                    "description": "Channel 7 sample time\n              selection",
+                    "offset": 21,
+                    "size": 3
+                  },
+                  "SMP8": {
+                    "description": "Channel 8 sample time\n              selection",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "SMP9": {
+                    "description": "Channel 9 sample time\n              selection",
+                    "offset": 27,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "JOFR1": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET1": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR2": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET2": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR3": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET3": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR4": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET4": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "HTR": {
+              "description": "watchdog higher threshold\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HT": {
+                    "description": "Analog watchdog higher\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "LTR": {
+              "description": "watchdog lower threshold\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LT": {
+                    "description": "Analog watchdog lower\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "SQR1": {
+              "description": "regular sequence register 1",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "L": {
+                    "description": "Regular channel sequence\n              length",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "SQ16": {
+                    "description": "16th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ15": {
+                    "description": "15th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ14": {
+                    "description": "14th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ13": {
+                    "description": "13th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SQR2": {
+              "description": "regular sequence register 2",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ12": {
+                    "description": "12th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "SQ11": {
+                    "description": "11th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "SQ10": {
+                    "description": "10th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ9": {
+                    "description": "9th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ8": {
+                    "description": "8th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ7": {
+                    "description": "7th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SQR3": {
+              "description": "regular sequence register 3",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ6": {
+                    "description": "6th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "SQ5": {
+                    "description": "5th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "SQ4": {
+                    "description": "4th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ3": {
+                    "description": "3rd conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ2": {
+                    "description": "2nd conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ1": {
+                    "description": "1st conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "JSQR": {
+              "description": "injected sequence register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JL": {
+                    "description": "Injected sequence length",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "JSQ4": {
+                    "description": "4th conversion in injected\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "JSQ3": {
+                    "description": "3rd conversion in injected\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "JSQ2": {
+                    "description": "2nd conversion in injected\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "JSQ1": {
+                    "description": "1st conversion in injected\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "JDR1": {
+              "description": "injected data register x",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR2": {
+              "description": "injected data register x",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR3": {
+              "description": "injected data register x",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR4": {
+              "description": "injected data register x",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "regular data register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Regular data",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "ADC2DATA": {
+                    "description": "ADC2 data",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ADC2": {
+        "description": "Analog to digital converter",
+        "children": {
+          "registers": {
+            "SR": {
+              "description": "status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STRT": {
+                    "description": "Regular channel start flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "JSTRT": {
+                    "description": "Injected channel start\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "JEOC": {
+                    "description": "Injected channel end of\n              conversion",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EOC": {
+                    "description": "Regular channel end of\n              conversion",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AWD": {
+                    "description": "Analog watchdog flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "control register 1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AWDEN": {
+                    "description": "Analog watchdog enable on regular\n              channels",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "JAWDEN": {
+                    "description": "Analog watchdog enable on injected\n              channels",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DISCNUM": {
+                    "description": "Discontinuous mode channel\n              count",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "JDISCEN": {
+                    "description": "Discontinuous mode on injected\n              channels",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DISCEN": {
+                    "description": "Discontinuous mode on regular\n              channels",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "JAUTO": {
+                    "description": "Automatic injected group\n              conversion",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AWDSGL": {
+                    "description": "Enable the watchdog on a single channel\n              in scan mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SCAN": {
+                    "description": "Scan mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "JEOCIE": {
+                    "description": "Interrupt enable for injected\n              channels",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "AWDIE": {
+                    "description": "Analog watchdog interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EOCIE": {
+                    "description": "Interrupt enable for EOC",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "AWDCH": {
+                    "description": "Analog watchdog channel select\n              bits",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSVREFE": {
+                    "description": "Temperature sensor and VREFINT\n              enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "SWSTART": {
+                    "description": "Start conversion of regular\n              channels",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "JSWSTART": {
+                    "description": "Start conversion of injected\n              channels",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EXTTRIG": {
+                    "description": "External trigger conversion mode for\n              regular channels",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EXTSEL": {
+                    "description": "External event select for regular\n              group",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "JEXTTRIG": {
+                    "description": "External trigger conversion mode for\n              injected channels",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "JEXTSEL": {
+                    "description": "External event select for injected\n              group",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "ALIGN": {
+                    "description": "Data alignment",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DMA": {
+                    "description": "Direct memory access mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RSTCAL": {
+                    "description": "Reset calibration",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CAL": {
+                    "description": "A/D calibration",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CONT": {
+                    "description": "Continuous conversion",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ADON": {
+                    "description": "A/D converter ON / OFF",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMPR1": {
+              "description": "sample time register 1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMP10": {
+                    "description": "Channel 10 sample time\n              selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "SMP11": {
+                    "description": "Channel 11 sample time\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "SMP12": {
+                    "description": "Channel 12 sample time\n              selection",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "SMP13": {
+                    "description": "Channel 13 sample time\n              selection",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "SMP14": {
+                    "description": "Channel 14 sample time\n              selection",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "SMP15": {
+                    "description": "Channel 15 sample time\n              selection",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SMP16": {
+                    "description": "Channel 16 sample time\n              selection",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "SMP17": {
+                    "description": "Channel 17 sample time\n              selection",
+                    "offset": 21,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "SMPR2": {
+              "description": "sample time register 2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMP0": {
+                    "description": "Channel 0 sample time\n              selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "SMP1": {
+                    "description": "Channel 1 sample time\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "SMP2": {
+                    "description": "Channel 2 sample time\n              selection",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "SMP3": {
+                    "description": "Channel 3 sample time\n              selection",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "SMP4": {
+                    "description": "Channel 4 sample time\n              selection",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "SMP5": {
+                    "description": "Channel 5 sample time\n              selection",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SMP6": {
+                    "description": "Channel 6 sample time\n              selection",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "SMP7": {
+                    "description": "Channel 7 sample time\n              selection",
+                    "offset": 21,
+                    "size": 3
+                  },
+                  "SMP8": {
+                    "description": "Channel 8 sample time\n              selection",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "SMP9": {
+                    "description": "Channel 9 sample time\n              selection",
+                    "offset": 27,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "JOFR1": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET1": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR2": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET2": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR3": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET3": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR4": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET4": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "HTR": {
+              "description": "watchdog higher threshold\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HT": {
+                    "description": "Analog watchdog higher\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "LTR": {
+              "description": "watchdog lower threshold\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LT": {
+                    "description": "Analog watchdog lower\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "SQR1": {
+              "description": "regular sequence register 1",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "L": {
+                    "description": "Regular channel sequence\n              length",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "SQ16": {
+                    "description": "16th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ15": {
+                    "description": "15th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ14": {
+                    "description": "14th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ13": {
+                    "description": "13th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SQR2": {
+              "description": "regular sequence register 2",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ12": {
+                    "description": "12th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "SQ11": {
+                    "description": "11th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "SQ10": {
+                    "description": "10th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ9": {
+                    "description": "9th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ8": {
+                    "description": "8th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ7": {
+                    "description": "7th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SQR3": {
+              "description": "regular sequence register 3",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ6": {
+                    "description": "6th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "SQ5": {
+                    "description": "5th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "SQ4": {
+                    "description": "4th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ3": {
+                    "description": "3rd conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ2": {
+                    "description": "2nd conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ1": {
+                    "description": "1st conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "JSQR": {
+              "description": "injected sequence register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JL": {
+                    "description": "Injected sequence length",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "JSQ4": {
+                    "description": "4th conversion in injected\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "JSQ3": {
+                    "description": "3rd conversion in injected\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "JSQ2": {
+                    "description": "2nd conversion in injected\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "JSQ1": {
+                    "description": "1st conversion in injected\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "JDR1": {
+              "description": "injected data register x",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR2": {
+              "description": "injected data register x",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR3": {
+              "description": "injected data register x",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR4": {
+              "description": "injected data register x",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "regular data register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Regular data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CAN1": {
+        "description": "Controller area network",
+        "children": {
+          "registers": {
+            "CAN_MCR": {
+              "description": "CAN_MCR",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBF": {
+                    "description": "DBF",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "RESET",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TTCM": {
+                    "description": "TTCM",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ABOM": {
+                    "description": "ABOM",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AWUM": {
+                    "description": "AWUM",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NART": {
+                    "description": "NART",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RFLM": {
+                    "description": "RFLM",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXFP": {
+                    "description": "TXFP",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLEEP": {
+                    "description": "SLEEP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INRQ": {
+                    "description": "INRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CAN_MSR": {
+              "description": "CAN_MSR",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX": {
+                    "description": "RX",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SAMP": {
+                    "description": "SAMP",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXM": {
+                    "description": "RXM",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXM": {
+                    "description": "TXM",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAKI": {
+                    "description": "SLAKI",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "WKUI": {
+                    "description": "WKUI",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERRI": {
+                    "description": "ERRI",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLAK": {
+                    "description": "SLAK",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INAK": {
+                    "description": "INAK",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CAN_TSR": {
+              "description": "CAN_TSR",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOW2": {
+                    "description": "Lowest priority flag for mailbox\n              2",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOW1": {
+                    "description": "Lowest priority flag for mailbox\n              1",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOW0": {
+                    "description": "Lowest priority flag for mailbox\n              0",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME2": {
+                    "description": "Lowest priority flag for mailbox\n              2",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME1": {
+                    "description": "Lowest priority flag for mailbox\n              1",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME0": {
+                    "description": "Lowest priority flag for mailbox\n              0",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CODE": {
+                    "description": "CODE",
+                    "offset": 24,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "ABRQ2": {
+                    "description": "ABRQ2",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TERR2": {
+                    "description": "TERR2",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ALST2": {
+                    "description": "ALST2",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TXOK2": {
+                    "description": "TXOK2",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RQCP2": {
+                    "description": "RQCP2",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ABRQ1": {
+                    "description": "ABRQ1",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TERR1": {
+                    "description": "TERR1",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ALST1": {
+                    "description": "ALST1",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TXOK1": {
+                    "description": "TXOK1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RQCP1": {
+                    "description": "RQCP1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ABRQ0": {
+                    "description": "ABRQ0",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TERR0": {
+                    "description": "TERR0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ALST0": {
+                    "description": "ALST0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXOK0": {
+                    "description": "TXOK0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RQCP0": {
+                    "description": "RQCP0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CAN_RF0R": {
+              "description": "CAN_RF0R",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFOM0": {
+                    "description": "RFOM0",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FOVR0": {
+                    "description": "FOVR0",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FULL0": {
+                    "description": "FULL0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FMP0": {
+                    "description": "FMP0",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CAN_RF1R": {
+              "description": "CAN_RF1R",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFOM1": {
+                    "description": "RFOM1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FOVR1": {
+                    "description": "FOVR1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FULL1": {
+                    "description": "FULL1",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FMP1": {
+                    "description": "FMP1",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CAN_IER": {
+              "description": "CAN_IER",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLKIE": {
+                    "description": "SLKIE",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WKUIE": {
+                    "description": "WKUIE",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "ERRIE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LECIE": {
+                    "description": "LECIE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BOFIE": {
+                    "description": "BOFIE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPVIE": {
+                    "description": "EPVIE",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EWGIE": {
+                    "description": "EWGIE",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FOVIE1": {
+                    "description": "FOVIE1",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FFIE1": {
+                    "description": "FFIE1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FMPIE1": {
+                    "description": "FMPIE1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FOVIE0": {
+                    "description": "FOVIE0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FFIE0": {
+                    "description": "FFIE0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FMPIE0": {
+                    "description": "FMPIE0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TMEIE": {
+                    "description": "TMEIE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CAN_ESR": {
+              "description": "CAN_ESR",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REC": {
+                    "description": "REC",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "TEC": {
+                    "description": "TEC",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "LEC": {
+                    "description": "LEC",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "BOFF": {
+                    "description": "BOFF",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPVF": {
+                    "description": "EPVF",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EWGF": {
+                    "description": "EWGF",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CAN_BTR": {
+              "description": "CAN_BTR",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SILM": {
+                    "description": "SILM",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LBKM": {
+                    "description": "LBKM",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SJW": {
+                    "description": "SJW",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "TS2": {
+                    "description": "TS2",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "TS1": {
+                    "description": "TS1",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "BRP": {
+                    "description": "BRP",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "CAN_TI0R": {
+              "description": "CAN_TI0R",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXRQ": {
+                    "description": "TXRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CAN_TDT0R": {
+              "description": "CAN_TDT0R",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TGT": {
+                    "description": "TGT",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CAN_TDL0R": {
+              "description": "CAN_TDL0R",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CAN_TDH0R": {
+              "description": "CAN_TDH0R",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CAN_TI1R": {
+              "description": "CAN_TI1R",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXRQ": {
+                    "description": "TXRQ",
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+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F0R2": {
+              "description": "Filter bank 0 register 2",
+              "offset": 580,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F1R1": {
+              "description": "Filter bank 1 register 1",
+              "offset": 584,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F1R2": {
+              "description": "Filter bank 1 register 2",
+              "offset": 588,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F2R1": {
+              "description": "Filter bank 2 register 1",
+              "offset": 592,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F2R2": {
+              "description": "Filter bank 2 register 2",
+              "offset": 596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F3R1": {
+              "description": "Filter bank 3 register 1",
+              "offset": 600,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F3R2": {
+              "description": "Filter bank 3 register 2",
+              "offset": 604,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F4R1": {
+              "description": "Filter bank 4 register 1",
+              "offset": 608,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F4R2": {
+              "description": "Filter bank 4 register 2",
+              "offset": 612,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F5R1": {
+              "description": "Filter bank 5 register 1",
+              "offset": 616,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F5R2": {
+              "description": "Filter bank 5 register 2",
+              "offset": 620,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F6R1": {
+              "description": "Filter bank 6 register 1",
+              "offset": 624,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F6R2": {
+              "description": "Filter bank 6 register 2",
+              "offset": 628,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F7R1": {
+              "description": "Filter bank 7 register 1",
+              "offset": 632,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F7R2": {
+              "description": "Filter bank 7 register 2",
+              "offset": 636,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F8R1": {
+              "description": "Filter bank 8 register 1",
+              "offset": 640,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F8R2": {
+              "description": "Filter bank 8 register 2",
+              "offset": 644,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F9R1": {
+              "description": "Filter bank 9 register 1",
+              "offset": 648,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F9R2": {
+              "description": "Filter bank 9 register 2",
+              "offset": 652,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F10R1": {
+              "description": "Filter bank 10 register 1",
+              "offset": 656,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F10R2": {
+              "description": "Filter bank 10 register 2",
+              "offset": 660,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F11R1": {
+              "description": "Filter bank 11 register 1",
+              "offset": 664,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F11R2": {
+              "description": "Filter bank 11 register 2",
+              "offset": 668,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F12R1": {
+              "description": "Filter bank 4 register 1",
+              "offset": 672,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F12R2": {
+              "description": "Filter bank 12 register 2",
+              "offset": 676,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F13R1": {
+              "description": "Filter bank 13 register 1",
+              "offset": 680,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F13R2": {
+              "description": "Filter bank 13 register 2",
+              "offset": 684,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  },
+  "devices": {
+    "STM32F103": {
+      "arch": "cortex_m3",
+      "description": "STM32F103",
+      "properties": {
+        "cpu.nvic_prio_bits": "4",
+        "cpu.mpu": "false",
+        "cpu.fpu": "false",
+        "cpu.revision": "r1p1",
+        "cpu.vendor_systick_config": "false",
+        "cpu.endian": "little",
+        "cpu.name": "CM3"
+      },
+      "children": {
+        "interrupts": {
+          "MemManageFault": {
+            "index": -12
+          },
+          "BusFault": {
+            "index": -11
+          },
+          "UsageFault": {
+            "index": -10
+          },
+          "DebugMonitor": {
+            "index": -4
+          },
+          "NMI": {
+            "index": -14
+          },
+          "HardFault": {
+            "index": -13
+          },
+          "SVCall": {
+            "index": -5
+          },
+          "PendSV": {
+            "index": -2
+          },
+          "SysTick": {
+            "index": -1
+          },
+          "FSMC": {
+            "index": 48,
+            "description": "FSMC global interrupt"
+          },
+          "PVD": {
+            "index": 1,
+            "description": "PVD through EXTI line detection\n        interrupt"
+          },
+          "RCC": {
+            "index": 5,
+            "description": "RCC global interrupt"
+          },
+          "TAMPER": {
+            "index": 2,
+            "description": "Tamper interrupt"
+          },
+          "DMA1_Channel1": {
+            "index": 11,
+            "description": "DMA1 Channel1 global interrupt"
+          },
+          "DMA2_Channel1": {
+            "index": 56,
+            "description": "DMA2 Channel1 global interrupt"
+          },
+          "SDIO": {
+            "index": 49,
+            "description": "SDIO global interrupt"
+          },
+          "RTC": {
+            "index": 3,
+            "description": "RTC global interrupt"
+          },
+          "WWDG": {
+            "index": 0,
+            "description": "Window Watchdog interrupt"
+          },
+          "TIM1_BRK": {
+            "index": 24,
+            "description": "TIM1 Break interrupt"
+          },
+          "TIM8_BRK": {
+            "index": 43,
+            "description": "TIM8 Break interrupt"
+          },
+          "TIM2": {
+            "index": 28,
+            "description": "TIM2 global interrupt"
+          },
+          "TIM3": {
+            "index": 29,
+            "description": "TIM3 global interrupt"
+          },
+          "TIM4": {
+            "index": 30,
+            "description": "TIM4 global interrupt"
+          },
+          "TIM5": {
+            "index": 50,
+            "description": "TIM5 global interrupt"
+          },
+          "TIM1_UP": {
+            "index": 25,
+            "description": "TIM1 Update interrupt"
+          },
+          "TIM1_TRG_COM": {
+            "index": 26,
+            "description": "TIM1 Trigger and Commutation\n        interrupts"
+          },
+          "TIM6": {
+            "index": 54,
+            "description": "TIM6 global interrupt"
+          },
+          "TIM7": {
+            "index": 55,
+            "description": "TIM7 global interrupt"
+          },
+          "I2C1_EV": {
+            "index": 31,
+            "description": "I2C1 event interrupt"
+          },
+          "I2C2_EV": {
+            "index": 33,
+            "description": "I2C2 event interrupt"
+          },
+          "SPI1": {
+            "index": 35,
+            "description": "SPI1 global interrupt"
+          },
+          "SPI2": {
+            "index": 36,
+            "description": "SPI2 global interrupt"
+          },
+          "SPI3": {
+            "index": 51,
+            "description": "SPI3 global interrupt"
+          },
+          "USART1": {
+            "index": 37,
+            "description": "USART1 global interrupt"
+          },
+          "USART2": {
+            "index": 38,
+            "description": "USART2 global interrupt"
+          },
+          "USART3": {
+            "index": 39,
+            "description": "USART3 global interrupt"
+          },
+          "ADC1_2": {
+            "index": 18,
+            "description": "ADC1 and ADC2 global interrupt"
+          },
+          "ADC3": {
+            "index": 47,
+            "description": "ADC3 global interrupt"
+          },
+          "CAN_RX1": {
+            "index": 21,
+            "description": "CAN RX1 interrupt"
+          },
+          "UART4": {
+            "index": 52,
+            "description": "UART4 global interrupt"
+          },
+          "UART5": {
+            "index": 53,
+            "description": "UART5 global interrupt"
+          },
+          "FLASH": {
+            "index": 4,
+            "description": "Flash global interrupt"
+          },
+          "USB_HP_CAN_TX": {
+            "index": 19,
+            "description": "USB High Priority or CAN TX\n        interrupts"
+          }
+        },
+        "peripheral_instances": {
+          "FSMC": {
+            "description": "Flexible static memory controller",
+            "offset": 2684354560,
+            "type": "types.peripherals.FSMC"
+          },
+          "PWR": {
+            "description": "Power control",
+            "offset": 1073770496,
+            "type": "types.peripherals.PWR"
+          },
+          "RCC": {
+            "description": "Reset and clock control",
+            "offset": 1073876992,
+            "type": "types.peripherals.RCC"
+          },
+          "GPIOA": {
+            "description": "General purpose I/O",
+            "offset": 1073809408,
+            "type": "types.peripherals.GPIOA"
+          },
+          "GPIOB": {
+            "offset": 1073810432,
+            "type": "types.peripherals.GPIOA"
+          },
+          "GPIOC": {
+            "offset": 1073811456,
+            "type": "types.peripherals.GPIOA"
+          },
+          "GPIOD": {
+            "offset": 1073812480,
+            "type": "types.peripherals.GPIOA"
+          },
+          "GPIOE": {
+            "offset": 1073813504,
+            "type": "types.peripherals.GPIOA"
+          },
+          "GPIOF": {
+            "offset": 1073814528,
+            "type": "types.peripherals.GPIOA"
+          },
+          "GPIOG": {
+            "offset": 1073815552,
+            "type": "types.peripherals.GPIOA"
+          },
+          "AFIO": {
+            "description": "Alternate function I/O",
+            "offset": 1073807360,
+            "type": "types.peripherals.AFIO"
+          },
+          "EXTI": {
+            "description": "EXTI",
+            "offset": 1073808384,
+            "type": "types.peripherals.EXTI"
+          },
+          "DMA1": {
+            "description": "DMA controller",
+            "offset": 1073872896,
+            "type": "types.peripherals.DMA1"
+          },
+          "DMA2": {
+            "offset": 1073873920,
+            "type": "types.peripherals.DMA1"
+          },
+          "SDIO": {
+            "description": "Secure digital input/output\n      interface",
+            "offset": 1073840128,
+            "type": "types.peripherals.SDIO"
+          },
+          "RTC": {
+            "description": "Real time clock",
+            "offset": 1073752064,
+            "type": "types.peripherals.RTC"
+          },
+          "BKP": {
+            "description": "Backup registers",
+            "offset": 1073769472,
+            "type": "types.peripherals.BKP"
+          },
+          "IWDG": {
+            "description": "Independent watchdog",
+            "offset": 1073754112,
+            "type": "types.peripherals.IWDG"
+          },
+          "WWDG": {
+            "description": "Window watchdog",
+            "offset": 1073753088,
+            "type": "types.peripherals.WWDG"
+          },
+          "TIM1": {
+            "description": "Advanced timer",
+            "offset": 1073818624,
+            "type": "types.peripherals.TIM1"
+          },
+          "TIM8": {
+            "offset": 1073820672,
+            "type": "types.peripherals.TIM1"
+          },
+          "TIM2": {
+            "description": "General purpose timer",
+            "offset": 1073741824,
+            "type": "types.peripherals.TIM2"
+          },
+          "TIM3": {
+            "offset": 1073742848,
+            "type": "types.peripherals.TIM2"
+          },
+          "TIM4": {
+            "offset": 1073743872,
+            "type": "types.peripherals.TIM2"
+          },
+          "TIM5": {
+            "offset": 1073744896,
+            "type": "types.peripherals.TIM2"
+          },
+          "TIM9": {
+            "description": "General purpose timer",
+            "offset": 1073826816,
+            "type": "types.peripherals.TIM9"
+          },
+          "TIM12": {
+            "offset": 1073747968,
+            "type": "types.peripherals.TIM9"
+          },
+          "TIM10": {
+            "description": "General purpose timer",
+            "offset": 1073827840,
+            "type": "types.peripherals.TIM10"
+          },
+          "TIM11": {
+            "offset": 1073828864,
+            "type": "types.peripherals.TIM10"
+          },
+          "TIM13": {
+            "offset": 1073748992,
+            "type": "types.peripherals.TIM10"
+          },
+          "TIM14": {
+            "offset": 1073750016,
+            "type": "types.peripherals.TIM10"
+          },
+          "TIM6": {
+            "description": "Basic timer",
+            "offset": 1073745920,
+            "type": "types.peripherals.TIM6"
+          },
+          "TIM7": {
+            "offset": 1073746944,
+            "type": "types.peripherals.TIM6"
+          },
+          "I2C1": {
+            "description": "Inter integrated circuit",
+            "offset": 1073763328,
+            "type": "types.peripherals.I2C1"
+          },
+          "I2C2": {
+            "offset": 1073764352,
+            "type": "types.peripherals.I2C1"
+          },
+          "SPI1": {
+            "description": "Serial peripheral interface",
+            "offset": 1073819648,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI2": {
+            "offset": 1073756160,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI3": {
+            "offset": 1073757184,
+            "type": "types.peripherals.SPI1"
+          },
+          "USART1": {
+            "description": "Universal synchronous asynchronous receiver\n      transmitter",
+            "offset": 1073821696,
+            "type": "types.peripherals.USART1"
+          },
+          "USART2": {
+            "offset": 1073759232,
+            "type": "types.peripherals.USART1"
+          },
+          "USART3": {
+            "offset": 1073760256,
+            "type": "types.peripherals.USART1"
+          },
+          "ADC1": {
+            "description": "Analog to digital converter",
+            "offset": 1073816576,
+            "type": "types.peripherals.ADC1"
+          },
+          "ADC2": {
+            "description": "Analog to digital converter",
+            "offset": 1073817600,
+            "type": "types.peripherals.ADC2"
+          },
+          "ADC3": {
+            "offset": 1073822720,
+            "type": "types.peripherals.ADC2"
+          },
+          "CAN1": {
+            "description": "Controller area network",
+            "offset": 1073767424,
+            "type": "types.peripherals.CAN1"
+          },
+          "CAN2": {
+            "offset": 1073768448,
+            "type": "types.peripherals.CAN1"
+          },
+          "DAC": {
+            "description": "Digital to analog converter",
+            "offset": 1073771520,
+            "type": "types.peripherals.DAC"
+          },
+          "DBG": {
+            "description": "Debug support",
+            "offset": 3758366720,
+            "type": "types.peripherals.DBG"
+          },
+          "UART4": {
+            "description": "Universal asynchronous receiver\n      transmitter",
+            "offset": 1073761280,
+            "type": "types.peripherals.UART4"
+          },
+          "UART5": {
+            "description": "Universal asynchronous receiver\n      transmitter",
+            "offset": 1073762304,
+            "type": "types.peripherals.UART5"
+          },
+          "CRC": {
+            "description": "CRC calculation unit",
+            "offset": 1073885184,
+            "type": "types.peripherals.CRC"
+          },
+          "FLASH": {
+            "description": "FLASH",
+            "offset": 1073881088,
+            "type": "types.peripherals.FLASH"
+          },
+          "USB": {
+            "description": "Universal serial bus full-speed device\n      interface",
+            "offset": 1073765376,
+            "type": "types.peripherals.USB"
+          },
+          "OTG_FS_DEVICE": {
+            "description": "USB on the go full speed",
+            "offset": 1342179328,
+            "type": "types.peripherals.OTG_FS_DEVICE"
+          },
+          "OTG_FS_GLOBAL": {
+            "description": "USB on the go full speed",
+            "offset": 1342177280,
+            "type": "types.peripherals.OTG_FS_GLOBAL"
+          },
+          "OTG_FS_HOST": {
+            "description": "USB on the go full speed",
+            "offset": 1342178304,
+            "type": "types.peripherals.OTG_FS_HOST"
+          },
+          "OTG_FS_PWRCLK": {
+            "description": "USB on the go full speed",
+            "offset": 1342180864,
+            "type": "types.peripherals.OTG_FS_PWRCLK"
+          },
+          "ETHERNET_MMC": {
+            "description": "Ethernet: MAC management counters",
+            "offset": 1073905920,
+            "type": "types.peripherals.ETHERNET_MMC"
+          },
+          "ETHERNET_MAC": {
+            "description": "Ethernet: media access control",
+            "offset": 1073905664,
+            "type": "types.peripherals.ETHERNET_MAC"
+          },
+          "ETHERNET_PTP": {
+            "description": "Ethernet: Precision time protocol",
+            "offset": 1073907456,
+            "type": "types.peripherals.ETHERNET_PTP"
+          },
+          "ETHERNET_DMA": {
+            "description": "Ethernet: DMA controller operation",
+            "offset": 1073909760,
+            "type": "types.peripherals.ETHERNET_DMA"
+          },
+          "NVIC": {
+            "description": "Nested Vectored Interrupt\n      Controller",
+            "offset": 3758153984,
+            "type": "types.peripherals.NVIC"
+          },
+          "MPU": {
+            "description": "Memory protection unit",
+            "offset": 3758157200,
+            "type": "types.peripherals.MPU"
+          },
+          "SCB_ACTRL": {
+            "description": "System control block ACTLR",
+            "offset": 3758153736,
+            "type": "types.peripherals.SCB_ACTRL"
+          },
+          "NVIC_STIR": {
+            "description": "Nested vectored interrupt\n      controller",
+            "offset": 3758157568,
+            "type": "types.peripherals.NVIC_STIR"
+          },
+          "SCB": {
+            "description": "System control block",
+            "offset": 3758157056,
+            "type": "types.peripherals.SCB"
+          },
+          "STK": {
+            "description": "SysTick timer",
+            "offset": 3758153744,
+            "type": "types.peripherals.STK"
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/chips/STM32F103.zig b/src/chips/STM32F103.zig
new file mode 100644
index 000000000..f29fded29
--- /dev/null
+++ b/src/chips/STM32F103.zig
@@ -0,0 +1,10854 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    ///  STM32F103
+    pub const STM32F103 = struct {
+        pub const properties = struct {
+            pub const @"cpu.nvic_prio_bits" = "4";
+            pub const @"cpu.mpu" = "false";
+            pub const @"cpu.fpu" = "false";
+            pub const @"cpu.revision" = "r1p1";
+            pub const @"cpu.vendor_systick_config" = "false";
+            pub const @"cpu.endian" = "little";
+            pub const @"cpu.name" = "CM3";
+        };
+
+        pub const VectorTable = extern struct {
+            const Handler = micro.interrupt.Handler;
+            const unhandled = micro.interrupt.unhandled;
+
+            initial_stack_pointer: u32,
+            Reset: Handler = unhandled,
+            NMI: Handler = unhandled,
+            HardFault: Handler = unhandled,
+            MemManageFault: Handler = unhandled,
+            BusFault: Handler = unhandled,
+            UsageFault: Handler = unhandled,
+            reserved5: [4]u32 = undefined,
+            SVCall: Handler = unhandled,
+            DebugMonitor: Handler = unhandled,
+            reserved11: [1]u32 = undefined,
+            PendSV: Handler = unhandled,
+            SysTick: Handler = unhandled,
+            ///  Window Watchdog interrupt
+            WWDG: Handler = unhandled,
+            ///  PVD through EXTI line detection interrupt
+            PVD: Handler = unhandled,
+            ///  Tamper interrupt
+            TAMPER: Handler = unhandled,
+            ///  RTC global interrupt
+            RTC: Handler = unhandled,
+            ///  Flash global interrupt
+            FLASH: Handler = unhandled,
+            ///  RCC global interrupt
+            RCC: Handler = unhandled,
+            reserved20: [5]u32 = undefined,
+            ///  DMA1 Channel1 global interrupt
+            DMA1_Channel1: Handler = unhandled,
+            reserved26: [6]u32 = undefined,
+            ///  ADC1 and ADC2 global interrupt
+            ADC1_2: Handler = unhandled,
+            ///  USB High Priority or CAN TX interrupts
+            USB_HP_CAN_TX: Handler = unhandled,
+            reserved34: [1]u32 = undefined,
+            ///  CAN RX1 interrupt
+            CAN_RX1: Handler = unhandled,
+            reserved36: [2]u32 = undefined,
+            ///  TIM1 Break interrupt
+            TIM1_BRK: Handler = unhandled,
+            ///  TIM1 Update interrupt
+            TIM1_UP: Handler = unhandled,
+            ///  TIM1 Trigger and Commutation interrupts
+            TIM1_TRG_COM: Handler = unhandled,
+            reserved41: [1]u32 = undefined,
+            ///  TIM2 global interrupt
+            TIM2: Handler = unhandled,
+            ///  TIM3 global interrupt
+            TIM3: Handler = unhandled,
+            ///  TIM4 global interrupt
+            TIM4: Handler = unhandled,
+            ///  I2C1 event interrupt
+            I2C1_EV: Handler = unhandled,
+            reserved46: [1]u32 = undefined,
+            ///  I2C2 event interrupt
+            I2C2_EV: Handler = unhandled,
+            reserved48: [1]u32 = undefined,
+            ///  SPI1 global interrupt
+            SPI1: Handler = unhandled,
+            ///  SPI2 global interrupt
+            SPI2: Handler = unhandled,
+            ///  USART1 global interrupt
+            USART1: Handler = unhandled,
+            ///  USART2 global interrupt
+            USART2: Handler = unhandled,
+            ///  USART3 global interrupt
+            USART3: Handler = unhandled,
+            reserved54: [3]u32 = undefined,
+            ///  TIM8 Break interrupt
+            TIM8_BRK: Handler = unhandled,
+            reserved58: [3]u32 = undefined,
+            ///  ADC3 global interrupt
+            ADC3: Handler = unhandled,
+            ///  FSMC global interrupt
+            FSMC: Handler = unhandled,
+            ///  SDIO global interrupt
+            SDIO: Handler = unhandled,
+            ///  TIM5 global interrupt
+            TIM5: Handler = unhandled,
+            ///  SPI3 global interrupt
+            SPI3: Handler = unhandled,
+            ///  UART4 global interrupt
+            UART4: Handler = unhandled,
+            ///  UART5 global interrupt
+            UART5: Handler = unhandled,
+            ///  TIM6 global interrupt
+            TIM6: Handler = unhandled,
+            ///  TIM7 global interrupt
+            TIM7: Handler = unhandled,
+            ///  DMA2 Channel1 global interrupt
+            DMA2_Channel1: Handler = unhandled,
+        };
+
+        pub const peripherals = struct {
+            ///  General purpose timer
+            pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000);
+            ///  General purpose timer
+            pub const TIM3 = @ptrCast(*volatile types.TIM2, 0x40000400);
+            ///  General purpose timer
+            pub const TIM4 = @ptrCast(*volatile types.TIM2, 0x40000800);
+            ///  General purpose timer
+            pub const TIM5 = @ptrCast(*volatile types.TIM2, 0x40000c00);
+            ///  Basic timer
+            pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000);
+            ///  Basic timer
+            pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400);
+            ///  General purpose timer
+            pub const TIM12 = @ptrCast(*volatile types.TIM9, 0x40001800);
+            ///  General purpose timer
+            pub const TIM13 = @ptrCast(*volatile types.TIM10, 0x40001c00);
+            ///  General purpose timer
+            pub const TIM14 = @ptrCast(*volatile types.TIM10, 0x40002000);
+            ///  Real time clock
+            pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800);
+            ///  Window watchdog
+            pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00);
+            ///  Independent watchdog
+            pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000);
+            ///  Serial peripheral interface
+            pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800);
+            ///  Serial peripheral interface
+            pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART2 = @ptrCast(*volatile types.USART1, 0x40004400);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART3 = @ptrCast(*volatile types.USART1, 0x40004800);
+            ///  Universal asynchronous receiver transmitter
+            pub const UART4 = @ptrCast(*volatile types.UART4, 0x40004c00);
+            ///  Universal asynchronous receiver transmitter
+            pub const UART5 = @ptrCast(*volatile types.UART5, 0x40005000);
+            ///  Inter integrated circuit
+            pub const I2C1 = @ptrCast(*volatile types.I2C1, 0x40005400);
+            ///  Inter integrated circuit
+            pub const I2C2 = @ptrCast(*volatile types.I2C1, 0x40005800);
+            ///  Universal serial bus full-speed device interface
+            pub const USB = @ptrCast(*volatile types.USB, 0x40005c00);
+            ///  Controller area network
+            pub const CAN1 = @ptrCast(*volatile types.CAN1, 0x40006400);
+            ///  Controller area network
+            pub const CAN2 = @ptrCast(*volatile types.CAN1, 0x40006800);
+            ///  Backup registers
+            pub const BKP = @ptrCast(*volatile types.BKP, 0x40006c00);
+            ///  Power control
+            pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000);
+            ///  Digital to analog converter
+            pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400);
+            ///  Alternate function I/O
+            pub const AFIO = @ptrCast(*volatile types.AFIO, 0x40010000);
+            ///  EXTI
+            pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40010400);
+            ///  General purpose I/O
+            pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x40010800);
+            ///  General purpose I/O
+            pub const GPIOB = @ptrCast(*volatile types.GPIOA, 0x40010c00);
+            ///  General purpose I/O
+            pub const GPIOC = @ptrCast(*volatile types.GPIOA, 0x40011000);
+            ///  General purpose I/O
+            pub const GPIOD = @ptrCast(*volatile types.GPIOA, 0x40011400);
+            ///  General purpose I/O
+            pub const GPIOE = @ptrCast(*volatile types.GPIOA, 0x40011800);
+            ///  General purpose I/O
+            pub const GPIOF = @ptrCast(*volatile types.GPIOA, 0x40011c00);
+            ///  General purpose I/O
+            pub const GPIOG = @ptrCast(*volatile types.GPIOA, 0x40012000);
+            ///  Analog to digital converter
+            pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x40012400);
+            ///  Analog to digital converter
+            pub const ADC2 = @ptrCast(*volatile types.ADC2, 0x40012800);
+            ///  Advanced timer
+            pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40012c00);
+            ///  Serial peripheral interface
+            pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000);
+            ///  Advanced timer
+            pub const TIM8 = @ptrCast(*volatile types.TIM1, 0x40013400);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART1 = @ptrCast(*volatile types.USART1, 0x40013800);
+            ///  Analog to digital converter
+            pub const ADC3 = @ptrCast(*volatile types.ADC2, 0x40013c00);
+            ///  General purpose timer
+            pub const TIM9 = @ptrCast(*volatile types.TIM9, 0x40014c00);
+            ///  General purpose timer
+            pub const TIM10 = @ptrCast(*volatile types.TIM10, 0x40015000);
+            ///  General purpose timer
+            pub const TIM11 = @ptrCast(*volatile types.TIM10, 0x40015400);
+            ///  Secure digital input/output interface
+            pub const SDIO = @ptrCast(*volatile types.SDIO, 0x40018000);
+            ///  DMA controller
+            pub const DMA1 = @ptrCast(*volatile types.DMA1, 0x40020000);
+            ///  DMA controller
+            pub const DMA2 = @ptrCast(*volatile types.DMA1, 0x40020400);
+            ///  Reset and clock control
+            pub const RCC = @ptrCast(*volatile types.RCC, 0x40021000);
+            ///  FLASH
+            pub const FLASH = @ptrCast(*volatile types.FLASH, 0x40022000);
+            ///  CRC calculation unit
+            pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000);
+            ///  Ethernet: media access control
+            pub const ETHERNET_MAC = @ptrCast(*volatile types.ETHERNET_MAC, 0x40028000);
+            ///  Ethernet: MAC management counters
+            pub const ETHERNET_MMC = @ptrCast(*volatile types.ETHERNET_MMC, 0x40028100);
+            ///  Ethernet: Precision time protocol
+            pub const ETHERNET_PTP = @ptrCast(*volatile types.ETHERNET_PTP, 0x40028700);
+            ///  Ethernet: DMA controller operation
+            pub const ETHERNET_DMA = @ptrCast(*volatile types.ETHERNET_DMA, 0x40029000);
+            ///  USB on the go full speed
+            pub const OTG_FS_GLOBAL = @ptrCast(*volatile types.OTG_FS_GLOBAL, 0x50000000);
+            ///  USB on the go full speed
+            pub const OTG_FS_HOST = @ptrCast(*volatile types.OTG_FS_HOST, 0x50000400);
+            ///  USB on the go full speed
+            pub const OTG_FS_DEVICE = @ptrCast(*volatile types.OTG_FS_DEVICE, 0x50000800);
+            ///  USB on the go full speed
+            pub const OTG_FS_PWRCLK = @ptrCast(*volatile types.OTG_FS_PWRCLK, 0x50000e00);
+            ///  Flexible static memory controller
+            pub const FSMC = @ptrCast(*volatile types.FSMC, 0xa0000000);
+            ///  System control block ACTLR
+            pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008);
+            ///  SysTick timer
+            pub const STK = @ptrCast(*volatile types.STK, 0xe000e010);
+            ///  Nested Vectored Interrupt Controller
+            pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100);
+            ///  System control block
+            pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00);
+            ///  Memory protection unit
+            pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90);
+            ///  Nested vectored interrupt controller
+            pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00);
+            ///  Debug support
+            pub const DBG = @ptrCast(*volatile types.DBG, 0xe0042000);
+        };
+    };
+};
+
+pub const types = struct {
+    ///  Flexible static memory controller
+    pub const FSMC = extern struct {
+        ///  SRAM/NOR-Flash chip-select control register 1
+        BCR1: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            reserved11: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 1
+        BTR1: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 2
+        BCR2: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 2
+        BTR2: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 3
+        BCR3: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 3
+        BTR3: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 4
+        BCR4: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 4
+        BTR4: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved96: [64]u8,
+        ///  PC Card/NAND Flash control register 2
+        PCR2: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 2
+        SR2: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 2
+        PMEM2: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 2
+        PATT2: mmio.Mmio(packed struct(u32) {
+            ///  Attribute memory x setup time
+            ATTSETx: u8,
+            ///  Attribute memory x wait time
+            ATTWAITx: u8,
+            ///  Attribute memory x hold time
+            ATTHOLDx: u8,
+            ///  Attribute memory x databus HiZ time
+            ATTHIZx: u8,
+        }),
+        reserved116: [4]u8,
+        ///  ECC result register 2
+        ECCR2: mmio.Mmio(packed struct(u32) {
+            ///  ECC result
+            ECCx: u32,
+        }),
+        reserved128: [8]u8,
+        ///  PC Card/NAND Flash control register 3
+        PCR3: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 3
+        SR3: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 3
+        PMEM3: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 3
+        PATT3: mmio.Mmio(packed struct(u32) {
+            ///  ATTSETx
+            ATTSETx: u8,
+            ///  ATTWAITx
+            ATTWAITx: u8,
+            ///  ATTHOLDx
+            ATTHOLDx: u8,
+            ///  ATTHIZx
+            ATTHIZx: u8,
+        }),
+        reserved148: [4]u8,
+        ///  ECC result register 3
+        ECCR3: mmio.Mmio(packed struct(u32) {
+            ///  ECCx
+            ECCx: u32,
+        }),
+        reserved160: [8]u8,
+        ///  PC Card/NAND Flash control register 4
+        PCR4: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 4
+        SR4: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 4
+        PMEM4: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 4
+        PATT4: mmio.Mmio(packed struct(u32) {
+            ///  ATTSETx
+            ATTSETx: u8,
+            ///  ATTWAITx
+            ATTWAITx: u8,
+            ///  ATTHOLDx
+            ATTHOLDx: u8,
+            ///  ATTHIZx
+            ATTHIZx: u8,
+        }),
+        ///  I/O space timing register 4
+        PIO4: mmio.Mmio(packed struct(u32) {
+            ///  IOSETx
+            IOSETx: u8,
+            ///  IOWAITx
+            IOWAITx: u8,
+            ///  IOHOLDx
+            IOHOLDx: u8,
+            ///  IOHIZx
+            IOHIZx: u8,
+        }),
+        reserved260: [80]u8,
+        ///  SRAM/NOR-Flash write timing registers 1
+        BWTR1: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            reserved20: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved268: [4]u8,
+        ///  SRAM/NOR-Flash write timing registers 2
+        BWTR2: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            reserved20: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved276: [4]u8,
+        ///  SRAM/NOR-Flash write timing registers 3
+        BWTR3: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            reserved20: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved284: [4]u8,
+        ///  SRAM/NOR-Flash write timing registers 4
+        BWTR4: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            reserved20: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+    };
+
+    ///  Power control
+    pub const PWR = extern struct {
+        ///  Power control register (PWR_CR)
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Low Power Deep Sleep
+            LPDS: u1,
+            ///  Power Down Deep Sleep
+            PDDS: u1,
+            ///  Clear Wake-up Flag
+            CWUF: u1,
+            ///  Clear STANDBY Flag
+            CSBF: u1,
+            ///  Power Voltage Detector Enable
+            PVDE: u1,
+            ///  PVD Level Selection
+            PLS: u3,
+            ///  Disable Backup Domain write protection
+            DBP: u1,
+            padding: u23,
+        }),
+        ///  Power control register (PWR_CR)
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  Wake-Up Flag
+            WUF: u1,
+            ///  STANDBY Flag
+            SBF: u1,
+            ///  PVD Output
+            PVDO: u1,
+            reserved8: u5,
+            ///  Enable WKUP pin
+            EWUP: u1,
+            padding: u23,
+        }),
+    };
+
+    ///  Reset and clock control
+    pub const RCC = extern struct {
+        ///  Clock control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Internal High Speed clock enable
+            HSION: u1,
+            ///  Internal High Speed clock ready flag
+            HSIRDY: u1,
+            reserved3: u1,
+            ///  Internal High Speed clock trimming
+            HSITRIM: u5,
+            ///  Internal High Speed clock Calibration
+            HSICAL: u8,
+            ///  External High Speed clock enable
+            HSEON: u1,
+            ///  External High Speed clock ready flag
+            HSERDY: u1,
+            ///  External High Speed clock Bypass
+            HSEBYP: u1,
+            ///  Clock Security System enable
+            CSSON: u1,
+            reserved24: u4,
+            ///  PLL enable
+            PLLON: u1,
+            ///  PLL clock ready flag
+            PLLRDY: u1,
+            padding: u6,
+        }),
+        ///  Clock configuration register (RCC_CFGR)
+        CFGR: mmio.Mmio(packed struct(u32) {
+            ///  System clock Switch
+            SW: u2,
+            ///  System Clock Switch Status
+            SWS: u2,
+            ///  AHB prescaler
+            HPRE: u4,
+            ///  APB Low speed prescaler (APB1)
+            PPRE1: u3,
+            ///  APB High speed prescaler (APB2)
+            PPRE2: u3,
+            ///  ADC prescaler
+            ADCPRE: u2,
+            ///  PLL entry clock source
+            PLLSRC: u1,
+            ///  HSE divider for PLL entry
+            PLLXTPRE: u1,
+            ///  PLL Multiplication Factor
+            PLLMUL: u4,
+            ///  USB OTG FS prescaler
+            OTGFSPRE: u1,
+            reserved24: u1,
+            ///  Microcontroller clock output
+            MCO: u3,
+            padding: u5,
+        }),
+        ///  Clock interrupt register (RCC_CIR)
+        CIR: mmio.Mmio(packed struct(u32) {
+            ///  LSI Ready Interrupt flag
+            LSIRDYF: u1,
+            ///  LSE Ready Interrupt flag
+            LSERDYF: u1,
+            ///  HSI Ready Interrupt flag
+            HSIRDYF: u1,
+            ///  HSE Ready Interrupt flag
+            HSERDYF: u1,
+            ///  PLL Ready Interrupt flag
+            PLLRDYF: u1,
+            reserved7: u2,
+            ///  Clock Security System Interrupt flag
+            CSSF: u1,
+            ///  LSI Ready Interrupt Enable
+            LSIRDYIE: u1,
+            ///  LSE Ready Interrupt Enable
+            LSERDYIE: u1,
+            ///  HSI Ready Interrupt Enable
+            HSIRDYIE: u1,
+            ///  HSE Ready Interrupt Enable
+            HSERDYIE: u1,
+            ///  PLL Ready Interrupt Enable
+            PLLRDYIE: u1,
+            reserved16: u3,
+            ///  LSI Ready Interrupt Clear
+            LSIRDYC: u1,
+            ///  LSE Ready Interrupt Clear
+            LSERDYC: u1,
+            ///  HSI Ready Interrupt Clear
+            HSIRDYC: u1,
+            ///  HSE Ready Interrupt Clear
+            HSERDYC: u1,
+            ///  PLL Ready Interrupt Clear
+            PLLRDYC: u1,
+            reserved23: u2,
+            ///  Clock security system interrupt clear
+            CSSC: u1,
+            padding: u8,
+        }),
+        ///  APB2 peripheral reset register (RCC_APB2RSTR)
+        APB2RSTR: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function I/O reset
+            AFIORST: u1,
+            reserved2: u1,
+            ///  IO port A reset
+            IOPARST: u1,
+            ///  IO port B reset
+            IOPBRST: u1,
+            ///  IO port C reset
+            IOPCRST: u1,
+            ///  IO port D reset
+            IOPDRST: u1,
+            ///  IO port E reset
+            IOPERST: u1,
+            ///  IO port F reset
+            IOPFRST: u1,
+            ///  IO port G reset
+            IOPGRST: u1,
+            ///  ADC 1 interface reset
+            ADC1RST: u1,
+            ///  ADC 2 interface reset
+            ADC2RST: u1,
+            ///  TIM1 timer reset
+            TIM1RST: u1,
+            ///  SPI 1 reset
+            SPI1RST: u1,
+            ///  TIM8 timer reset
+            TIM8RST: u1,
+            ///  USART1 reset
+            USART1RST: u1,
+            ///  ADC 3 interface reset
+            ADC3RST: u1,
+            reserved19: u3,
+            ///  TIM9 timer reset
+            TIM9RST: u1,
+            ///  TIM10 timer reset
+            TIM10RST: u1,
+            ///  TIM11 timer reset
+            TIM11RST: u1,
+            padding: u10,
+        }),
+        ///  APB1 peripheral reset register (RCC_APB1RSTR)
+        APB1RSTR: mmio.Mmio(packed struct(u32) {
+            ///  Timer 2 reset
+            TIM2RST: u1,
+            ///  Timer 3 reset
+            TIM3RST: u1,
+            ///  Timer 4 reset
+            TIM4RST: u1,
+            ///  Timer 5 reset
+            TIM5RST: u1,
+            ///  Timer 6 reset
+            TIM6RST: u1,
+            ///  Timer 7 reset
+            TIM7RST: u1,
+            ///  Timer 12 reset
+            TIM12RST: u1,
+            ///  Timer 13 reset
+            TIM13RST: u1,
+            ///  Timer 14 reset
+            TIM14RST: u1,
+            reserved11: u2,
+            ///  Window watchdog reset
+            WWDGRST: u1,
+            reserved14: u2,
+            ///  SPI2 reset
+            SPI2RST: u1,
+            ///  SPI3 reset
+            SPI3RST: u1,
+            reserved17: u1,
+            ///  USART 2 reset
+            USART2RST: u1,
+            ///  USART 3 reset
+            USART3RST: u1,
+            ///  UART 4 reset
+            UART4RST: u1,
+            ///  UART 5 reset
+            UART5RST: u1,
+            ///  I2C1 reset
+            I2C1RST: u1,
+            ///  I2C2 reset
+            I2C2RST: u1,
+            ///  USB reset
+            USBRST: u1,
+            reserved25: u1,
+            ///  CAN reset
+            CANRST: u1,
+            reserved27: u1,
+            ///  Backup interface reset
+            BKPRST: u1,
+            ///  Power interface reset
+            PWRRST: u1,
+            ///  DAC interface reset
+            DACRST: u1,
+            padding: u2,
+        }),
+        ///  AHB Peripheral Clock enable register (RCC_AHBENR)
+        AHBENR: mmio.Mmio(packed struct(u32) {
+            ///  DMA1 clock enable
+            DMA1EN: u1,
+            ///  DMA2 clock enable
+            DMA2EN: u1,
+            ///  SRAM interface clock enable
+            SRAMEN: u1,
+            reserved4: u1,
+            ///  FLITF clock enable
+            FLITFEN: u1,
+            reserved6: u1,
+            ///  CRC clock enable
+            CRCEN: u1,
+            reserved8: u1,
+            ///  FSMC clock enable
+            FSMCEN: u1,
+            reserved10: u1,
+            ///  SDIO clock enable
+            SDIOEN: u1,
+            padding: u21,
+        }),
+        ///  APB2 peripheral clock enable register (RCC_APB2ENR)
+        APB2ENR: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function I/O clock enable
+            AFIOEN: u1,
+            reserved2: u1,
+            ///  I/O port A clock enable
+            IOPAEN: u1,
+            ///  I/O port B clock enable
+            IOPBEN: u1,
+            ///  I/O port C clock enable
+            IOPCEN: u1,
+            ///  I/O port D clock enable
+            IOPDEN: u1,
+            ///  I/O port E clock enable
+            IOPEEN: u1,
+            ///  I/O port F clock enable
+            IOPFEN: u1,
+            ///  I/O port G clock enable
+            IOPGEN: u1,
+            ///  ADC 1 interface clock enable
+            ADC1EN: u1,
+            ///  ADC 2 interface clock enable
+            ADC2EN: u1,
+            ///  TIM1 Timer clock enable
+            TIM1EN: u1,
+            ///  SPI 1 clock enable
+            SPI1EN: u1,
+            ///  TIM8 Timer clock enable
+            TIM8EN: u1,
+            ///  USART1 clock enable
+            USART1EN: u1,
+            ///  ADC3 interface clock enable
+            ADC3EN: u1,
+            reserved19: u3,
+            ///  TIM9 Timer clock enable
+            TIM9EN: u1,
+            ///  TIM10 Timer clock enable
+            TIM10EN: u1,
+            ///  TIM11 Timer clock enable
+            TIM11EN: u1,
+            padding: u10,
+        }),
+        ///  APB1 peripheral clock enable register (RCC_APB1ENR)
+        APB1ENR: mmio.Mmio(packed struct(u32) {
+            ///  Timer 2 clock enable
+            TIM2EN: u1,
+            ///  Timer 3 clock enable
+            TIM3EN: u1,
+            ///  Timer 4 clock enable
+            TIM4EN: u1,
+            ///  Timer 5 clock enable
+            TIM5EN: u1,
+            ///  Timer 6 clock enable
+            TIM6EN: u1,
+            ///  Timer 7 clock enable
+            TIM7EN: u1,
+            ///  Timer 12 clock enable
+            TIM12EN: u1,
+            ///  Timer 13 clock enable
+            TIM13EN: u1,
+            ///  Timer 14 clock enable
+            TIM14EN: u1,
+            reserved11: u2,
+            ///  Window watchdog clock enable
+            WWDGEN: u1,
+            reserved14: u2,
+            ///  SPI 2 clock enable
+            SPI2EN: u1,
+            ///  SPI 3 clock enable
+            SPI3EN: u1,
+            reserved17: u1,
+            ///  USART 2 clock enable
+            USART2EN: u1,
+            ///  USART 3 clock enable
+            USART3EN: u1,
+            ///  UART 4 clock enable
+            UART4EN: u1,
+            ///  UART 5 clock enable
+            UART5EN: u1,
+            ///  I2C 1 clock enable
+            I2C1EN: u1,
+            ///  I2C 2 clock enable
+            I2C2EN: u1,
+            ///  USB clock enable
+            USBEN: u1,
+            reserved25: u1,
+            ///  CAN clock enable
+            CANEN: u1,
+            reserved27: u1,
+            ///  Backup interface clock enable
+            BKPEN: u1,
+            ///  Power interface clock enable
+            PWREN: u1,
+            ///  DAC interface clock enable
+            DACEN: u1,
+            padding: u2,
+        }),
+        ///  Backup domain control register (RCC_BDCR)
+        BDCR: mmio.Mmio(packed struct(u32) {
+            ///  External Low Speed oscillator enable
+            LSEON: u1,
+            ///  External Low Speed oscillator ready
+            LSERDY: u1,
+            ///  External Low Speed oscillator bypass
+            LSEBYP: u1,
+            reserved8: u5,
+            ///  RTC clock source selection
+            RTCSEL: u2,
+            reserved15: u5,
+            ///  RTC clock enable
+            RTCEN: u1,
+            ///  Backup domain software reset
+            BDRST: u1,
+            padding: u15,
+        }),
+        ///  Control/status register (RCC_CSR)
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  Internal low speed oscillator enable
+            LSION: u1,
+            ///  Internal low speed oscillator ready
+            LSIRDY: u1,
+            reserved24: u22,
+            ///  Remove reset flag
+            RMVF: u1,
+            reserved26: u1,
+            ///  PIN reset flag
+            PINRSTF: u1,
+            ///  POR/PDR reset flag
+            PORRSTF: u1,
+            ///  Software reset flag
+            SFTRSTF: u1,
+            ///  Independent watchdog reset flag
+            IWDGRSTF: u1,
+            ///  Window watchdog reset flag
+            WWDGRSTF: u1,
+            ///  Low-power reset flag
+            LPWRRSTF: u1,
+        }),
+    };
+
+    ///  General purpose I/O
+    pub const GPIOA = extern struct {
+        ///  Port configuration register low (GPIOn_CRL)
+        CRL: mmio.Mmio(packed struct(u32) {
+            ///  Port n.0 mode bits
+            MODE0: u2,
+            ///  Port n.0 configuration bits
+            CNF0: u2,
+            ///  Port n.1 mode bits
+            MODE1: u2,
+            ///  Port n.1 configuration bits
+            CNF1: u2,
+            ///  Port n.2 mode bits
+            MODE2: u2,
+            ///  Port n.2 configuration bits
+            CNF2: u2,
+            ///  Port n.3 mode bits
+            MODE3: u2,
+            ///  Port n.3 configuration bits
+            CNF3: u2,
+            ///  Port n.4 mode bits
+            MODE4: u2,
+            ///  Port n.4 configuration bits
+            CNF4: u2,
+            ///  Port n.5 mode bits
+            MODE5: u2,
+            ///  Port n.5 configuration bits
+            CNF5: u2,
+            ///  Port n.6 mode bits
+            MODE6: u2,
+            ///  Port n.6 configuration bits
+            CNF6: u2,
+            ///  Port n.7 mode bits
+            MODE7: u2,
+            ///  Port n.7 configuration bits
+            CNF7: u2,
+        }),
+        ///  Port configuration register high (GPIOn_CRL)
+        CRH: mmio.Mmio(packed struct(u32) {
+            ///  Port n.8 mode bits
+            MODE8: u2,
+            ///  Port n.8 configuration bits
+            CNF8: u2,
+            ///  Port n.9 mode bits
+            MODE9: u2,
+            ///  Port n.9 configuration bits
+            CNF9: u2,
+            ///  Port n.10 mode bits
+            MODE10: u2,
+            ///  Port n.10 configuration bits
+            CNF10: u2,
+            ///  Port n.11 mode bits
+            MODE11: u2,
+            ///  Port n.11 configuration bits
+            CNF11: u2,
+            ///  Port n.12 mode bits
+            MODE12: u2,
+            ///  Port n.12 configuration bits
+            CNF12: u2,
+            ///  Port n.13 mode bits
+            MODE13: u2,
+            ///  Port n.13 configuration bits
+            CNF13: u2,
+            ///  Port n.14 mode bits
+            MODE14: u2,
+            ///  Port n.14 configuration bits
+            CNF14: u2,
+            ///  Port n.15 mode bits
+            MODE15: u2,
+            ///  Port n.15 configuration bits
+            CNF15: u2,
+        }),
+        ///  Port input data register (GPIOn_IDR)
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Port input data
+            IDR0: u1,
+            ///  Port input data
+            IDR1: u1,
+            ///  Port input data
+            IDR2: u1,
+            ///  Port input data
+            IDR3: u1,
+            ///  Port input data
+            IDR4: u1,
+            ///  Port input data
+            IDR5: u1,
+            ///  Port input data
+            IDR6: u1,
+            ///  Port input data
+            IDR7: u1,
+            ///  Port input data
+            IDR8: u1,
+            ///  Port input data
+            IDR9: u1,
+            ///  Port input data
+            IDR10: u1,
+            ///  Port input data
+            IDR11: u1,
+            ///  Port input data
+            IDR12: u1,
+            ///  Port input data
+            IDR13: u1,
+            ///  Port input data
+            IDR14: u1,
+            ///  Port input data
+            IDR15: u1,
+            padding: u16,
+        }),
+        ///  Port output data register (GPIOn_ODR)
+        ODR: mmio.Mmio(packed struct(u32) {
+            ///  Port output data
+            ODR0: u1,
+            ///  Port output data
+            ODR1: u1,
+            ///  Port output data
+            ODR2: u1,
+            ///  Port output data
+            ODR3: u1,
+            ///  Port output data
+            ODR4: u1,
+            ///  Port output data
+            ODR5: u1,
+            ///  Port output data
+            ODR6: u1,
+            ///  Port output data
+            ODR7: u1,
+            ///  Port output data
+            ODR8: u1,
+            ///  Port output data
+            ODR9: u1,
+            ///  Port output data
+            ODR10: u1,
+            ///  Port output data
+            ODR11: u1,
+            ///  Port output data
+            ODR12: u1,
+            ///  Port output data
+            ODR13: u1,
+            ///  Port output data
+            ODR14: u1,
+            ///  Port output data
+            ODR15: u1,
+            padding: u16,
+        }),
+        ///  Port bit set/reset register (GPIOn_BSRR)
+        BSRR: mmio.Mmio(packed struct(u32) {
+            ///  Set bit 0
+            BS0: u1,
+            ///  Set bit 1
+            BS1: u1,
+            ///  Set bit 1
+            BS2: u1,
+            ///  Set bit 3
+            BS3: u1,
+            ///  Set bit 4
+            BS4: u1,
+            ///  Set bit 5
+            BS5: u1,
+            ///  Set bit 6
+            BS6: u1,
+            ///  Set bit 7
+            BS7: u1,
+            ///  Set bit 8
+            BS8: u1,
+            ///  Set bit 9
+            BS9: u1,
+            ///  Set bit 10
+            BS10: u1,
+            ///  Set bit 11
+            BS11: u1,
+            ///  Set bit 12
+            BS12: u1,
+            ///  Set bit 13
+            BS13: u1,
+            ///  Set bit 14
+            BS14: u1,
+            ///  Set bit 15
+            BS15: u1,
+            ///  Reset bit 0
+            BR0: u1,
+            ///  Reset bit 1
+            BR1: u1,
+            ///  Reset bit 2
+            BR2: u1,
+            ///  Reset bit 3
+            BR3: u1,
+            ///  Reset bit 4
+            BR4: u1,
+            ///  Reset bit 5
+            BR5: u1,
+            ///  Reset bit 6
+            BR6: u1,
+            ///  Reset bit 7
+            BR7: u1,
+            ///  Reset bit 8
+            BR8: u1,
+            ///  Reset bit 9
+            BR9: u1,
+            ///  Reset bit 10
+            BR10: u1,
+            ///  Reset bit 11
+            BR11: u1,
+            ///  Reset bit 12
+            BR12: u1,
+            ///  Reset bit 13
+            BR13: u1,
+            ///  Reset bit 14
+            BR14: u1,
+            ///  Reset bit 15
+            BR15: u1,
+        }),
+        ///  Port bit reset register (GPIOn_BRR)
+        BRR: mmio.Mmio(packed struct(u32) {
+            ///  Reset bit 0
+            BR0: u1,
+            ///  Reset bit 1
+            BR1: u1,
+            ///  Reset bit 1
+            BR2: u1,
+            ///  Reset bit 3
+            BR3: u1,
+            ///  Reset bit 4
+            BR4: u1,
+            ///  Reset bit 5
+            BR5: u1,
+            ///  Reset bit 6
+            BR6: u1,
+            ///  Reset bit 7
+            BR7: u1,
+            ///  Reset bit 8
+            BR8: u1,
+            ///  Reset bit 9
+            BR9: u1,
+            ///  Reset bit 10
+            BR10: u1,
+            ///  Reset bit 11
+            BR11: u1,
+            ///  Reset bit 12
+            BR12: u1,
+            ///  Reset bit 13
+            BR13: u1,
+            ///  Reset bit 14
+            BR14: u1,
+            ///  Reset bit 15
+            BR15: u1,
+            padding: u16,
+        }),
+        ///  Port configuration lock register
+        LCKR: mmio.Mmio(packed struct(u32) {
+            ///  Port A Lock bit 0
+            LCK0: u1,
+            ///  Port A Lock bit 1
+            LCK1: u1,
+            ///  Port A Lock bit 2
+            LCK2: u1,
+            ///  Port A Lock bit 3
+            LCK3: u1,
+            ///  Port A Lock bit 4
+            LCK4: u1,
+            ///  Port A Lock bit 5
+            LCK5: u1,
+            ///  Port A Lock bit 6
+            LCK6: u1,
+            ///  Port A Lock bit 7
+            LCK7: u1,
+            ///  Port A Lock bit 8
+            LCK8: u1,
+            ///  Port A Lock bit 9
+            LCK9: u1,
+            ///  Port A Lock bit 10
+            LCK10: u1,
+            ///  Port A Lock bit 11
+            LCK11: u1,
+            ///  Port A Lock bit 12
+            LCK12: u1,
+            ///  Port A Lock bit 13
+            LCK13: u1,
+            ///  Port A Lock bit 14
+            LCK14: u1,
+            ///  Port A Lock bit 15
+            LCK15: u1,
+            ///  Lock key
+            LCKK: u1,
+            padding: u15,
+        }),
+    };
+
+    ///  SysTick timer
+    pub const STK = extern struct {
+        ///  SysTick control and status register
+        CTRL: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            ENABLE: u1,
+            ///  SysTick exception request enable
+            TICKINT: u1,
+            ///  Clock source selection
+            CLKSOURCE: u1,
+            reserved16: u13,
+            ///  COUNTFLAG
+            COUNTFLAG: u1,
+            padding: u15,
+        }),
+        ///  SysTick reload value register
+        LOAD_: mmio.Mmio(packed struct(u32) {
+            ///  RELOAD value
+            RELOAD: u24,
+            padding: u8,
+        }),
+        ///  SysTick current value register
+        VAL: mmio.Mmio(packed struct(u32) {
+            ///  Current counter value
+            CURRENT: u24,
+            padding: u8,
+        }),
+        ///  SysTick calibration value register
+        CALIB: mmio.Mmio(packed struct(u32) {
+            ///  Calibration value
+            TENMS: u24,
+            padding: u8,
+        }),
+    };
+
+    ///  System control block
+    pub const SCB = extern struct {
+        ///  CPUID base register
+        CPUID: mmio.Mmio(packed struct(u32) {
+            ///  Revision number
+            Revision: u4,
+            ///  Part number of the processor
+            PartNo: u12,
+            ///  Reads as 0xF
+            Constant: u4,
+            ///  Variant number
+            Variant: u4,
+            ///  Implementer code
+            Implementer: u8,
+        }),
+        ///  Interrupt control and state register
+        ICSR: mmio.Mmio(packed struct(u32) {
+            ///  Active vector
+            VECTACTIVE: u9,
+            reserved11: u2,
+            ///  Return to base level
+            RETTOBASE: u1,
+            ///  Pending vector
+            VECTPENDING: u7,
+            reserved22: u3,
+            ///  Interrupt pending flag
+            ISRPENDING: u1,
+            reserved25: u2,
+            ///  SysTick exception clear-pending bit
+            PENDSTCLR: u1,
+            ///  SysTick exception set-pending bit
+            PENDSTSET: u1,
+            ///  PendSV clear-pending bit
+            PENDSVCLR: u1,
+            ///  PendSV set-pending bit
+            PENDSVSET: u1,
+            reserved31: u2,
+            ///  NMI set-pending bit.
+            NMIPENDSET: u1,
+        }),
+        ///  Vector table offset register
+        VTOR: mmio.Mmio(packed struct(u32) {
+            reserved9: u9,
+            ///  Vector table base offset field
+            TBLOFF: u21,
+            padding: u2,
+        }),
+        ///  Application interrupt and reset control register
+        AIRCR: mmio.Mmio(packed struct(u32) {
+            ///  VECTRESET
+            VECTRESET: u1,
+            ///  VECTCLRACTIVE
+            VECTCLRACTIVE: u1,
+            ///  SYSRESETREQ
+            SYSRESETREQ: u1,
+            reserved8: u5,
+            ///  PRIGROUP
+            PRIGROUP: u3,
+            reserved15: u4,
+            ///  ENDIANESS
+            ENDIANESS: u1,
+            ///  Register key
+            VECTKEYSTAT: u16,
+        }),
+        ///  System control register
+        SCR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  SLEEPONEXIT
+            SLEEPONEXIT: u1,
+            ///  SLEEPDEEP
+            SLEEPDEEP: u1,
+            reserved4: u1,
+            ///  Send Event on Pending bit
+            SEVEONPEND: u1,
+            padding: u27,
+        }),
+        ///  Configuration and control register
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Configures how the processor enters Thread mode
+            NONBASETHRDENA: u1,
+            ///  USERSETMPEND
+            USERSETMPEND: u1,
+            reserved3: u1,
+            ///  UNALIGN_ TRP
+            UNALIGN__TRP: u1,
+            ///  DIV_0_TRP
+            DIV_0_TRP: u1,
+            reserved8: u3,
+            ///  BFHFNMIGN
+            BFHFNMIGN: u1,
+            ///  STKALIGN
+            STKALIGN: u1,
+            padding: u22,
+        }),
+        ///  System handler priority registers
+        SHPR1: mmio.Mmio(packed struct(u32) {
+            ///  Priority of system handler 4
+            PRI_4: u8,
+            ///  Priority of system handler 5
+            PRI_5: u8,
+            ///  Priority of system handler 6
+            PRI_6: u8,
+            padding: u8,
+        }),
+        ///  System handler priority registers
+        SHPR2: mmio.Mmio(packed struct(u32) {
+            reserved24: u24,
+            ///  Priority of system handler 11
+            PRI_11: u8,
+        }),
+        ///  System handler priority registers
+        SHPR3: mmio.Mmio(packed struct(u32) {
+            reserved16: u16,
+            ///  Priority of system handler 14
+            PRI_14: u8,
+            ///  Priority of system handler 15
+            PRI_15: u8,
+        }),
+        ///  System handler control and state register
+        SHCRS: mmio.Mmio(packed struct(u32) {
+            ///  Memory management fault exception active bit
+            MEMFAULTACT: u1,
+            ///  Bus fault exception active bit
+            BUSFAULTACT: u1,
+            reserved3: u1,
+            ///  Usage fault exception active bit
+            USGFAULTACT: u1,
+            reserved7: u3,
+            ///  SVC call active bit
+            SVCALLACT: u1,
+            ///  Debug monitor active bit
+            MONITORACT: u1,
+            reserved10: u1,
+            ///  PendSV exception active bit
+            PENDSVACT: u1,
+            ///  SysTick exception active bit
+            SYSTICKACT: u1,
+            ///  Usage fault exception pending bit
+            USGFAULTPENDED: u1,
+            ///  Memory management fault exception pending bit
+            MEMFAULTPENDED: u1,
+            ///  Bus fault exception pending bit
+            BUSFAULTPENDED: u1,
+            ///  SVC call pending bit
+            SVCALLPENDED: u1,
+            ///  Memory management fault enable bit
+            MEMFAULTENA: u1,
+            ///  Bus fault enable bit
+            BUSFAULTENA: u1,
+            ///  Usage fault enable bit
+            USGFAULTENA: u1,
+            padding: u13,
+        }),
+        ///  Configurable fault status register
+        CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) {
+            ///  IACCVIOL
+            IACCVIOL: u1,
+            ///  DACCVIOL
+            DACCVIOL: u1,
+            reserved3: u1,
+            ///  MUNSTKERR
+            MUNSTKERR: u1,
+            ///  MSTKERR
+            MSTKERR: u1,
+            ///  MLSPERR
+            MLSPERR: u1,
+            reserved7: u1,
+            ///  MMARVALID
+            MMARVALID: u1,
+            ///  Instruction bus error
+            IBUSERR: u1,
+            ///  Precise data bus error
+            PRECISERR: u1,
+            ///  Imprecise data bus error
+            IMPRECISERR: u1,
+            ///  Bus fault on unstacking for a return from exception
+            UNSTKERR: u1,
+            ///  Bus fault on stacking for exception entry
+            STKERR: u1,
+            ///  Bus fault on floating-point lazy state preservation
+            LSPERR: u1,
+            reserved15: u1,
+            ///  Bus Fault Address Register (BFAR) valid flag
+            BFARVALID: u1,
+            ///  Undefined instruction usage fault
+            UNDEFINSTR: u1,
+            ///  Invalid state usage fault
+            INVSTATE: u1,
+            ///  Invalid PC load usage fault
+            INVPC: u1,
+            ///  No coprocessor usage fault.
+            NOCP: u1,
+            reserved24: u4,
+            ///  Unaligned access usage fault
+            UNALIGNED: u1,
+            ///  Divide by zero usage fault
+            DIVBYZERO: u1,
+            padding: u6,
+        }),
+        ///  Hard fault status register
+        HFSR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Vector table hard fault
+            VECTTBL: u1,
+            reserved30: u28,
+            ///  Forced hard fault
+            FORCED: u1,
+            ///  Reserved for Debug use
+            DEBUG_VT: u1,
+        }),
+        reserved52: [4]u8,
+        ///  Memory management fault address register
+        MMFAR: mmio.Mmio(packed struct(u32) {
+            ///  Memory management fault address
+            MMFAR: u32,
+        }),
+        ///  Bus fault address register
+        BFAR: mmio.Mmio(packed struct(u32) {
+            ///  Bus fault address
+            BFAR: u32,
+        }),
+    };
+
+    ///  Nested vectored interrupt controller
+    pub const NVIC_STIR = extern struct {
+        ///  Software trigger interrupt register
+        STIR: mmio.Mmio(packed struct(u32) {
+            ///  Software generated interrupt ID
+            INTID: u9,
+            padding: u23,
+        }),
+    };
+
+    ///  System control block ACTLR
+    pub const SCB_ACTRL = extern struct {
+        ///  Auxiliary control register
+        ACTRL: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  DISFOLD
+            DISFOLD: u1,
+            reserved10: u7,
+            ///  FPEXCODIS
+            FPEXCODIS: u1,
+            ///  DISRAMODE
+            DISRAMODE: u1,
+            ///  DISITMATBFLUSH
+            DISITMATBFLUSH: u1,
+            padding: u19,
+        }),
+    };
+
+    ///  Memory protection unit
+    pub const MPU = extern struct {
+        ///  MPU type register
+        MPU_TYPER: mmio.Mmio(packed struct(u32) {
+            ///  Separate flag
+            SEPARATE: u1,
+            reserved8: u7,
+            ///  Number of MPU data regions
+            DREGION: u8,
+            ///  Number of MPU instruction regions
+            IREGION: u8,
+            padding: u8,
+        }),
+        ///  MPU control register
+        MPU_CTRL: mmio.Mmio(packed struct(u32) {
+            ///  Enables the MPU
+            ENABLE: u1,
+            ///  Enables the operation of MPU during hard fault
+            HFNMIENA: u1,
+            ///  Enable priviliged software access to default memory map
+            PRIVDEFENA: u1,
+            padding: u29,
+        }),
+        ///  MPU region number register
+        MPU_RNR: mmio.Mmio(packed struct(u32) {
+            ///  MPU region
+            REGION: u8,
+            padding: u24,
+        }),
+        ///  MPU region base address register
+        MPU_RBAR: mmio.Mmio(packed struct(u32) {
+            ///  MPU region field
+            REGION: u4,
+            ///  MPU region number valid
+            VALID: u1,
+            ///  Region base address field
+            ADDR: u27,
+        }),
+        ///  MPU region attribute and size register
+        MPU_RASR: mmio.Mmio(packed struct(u32) {
+            ///  Region enable bit.
+            ENABLE: u1,
+            ///  Size of the MPU protection region
+            SIZE: u5,
+            reserved8: u2,
+            ///  Subregion disable bits
+            SRD: u8,
+            ///  memory attribute
+            B: u1,
+            ///  memory attribute
+            C: u1,
+            ///  Shareable memory attribute
+            S: u1,
+            ///  memory attribute
+            TEX: u3,
+            reserved24: u2,
+            ///  Access permission
+            AP: u3,
+            reserved28: u1,
+            ///  Instruction access disable bit
+            XN: u1,
+            padding: u3,
+        }),
+    };
+
+    ///  Nested Vectored Interrupt Controller
+    pub const NVIC = extern struct {
+        ///  Interrupt Set-Enable Register
+        ISER0: mmio.Mmio(packed struct(u32) {
+            ///  SETENA
+            SETENA: u32,
+        }),
+        ///  Interrupt Set-Enable Register
+        ISER1: mmio.Mmio(packed struct(u32) {
+            ///  SETENA
+            SETENA: u32,
+        }),
+        reserved128: [120]u8,
+        ///  Interrupt Clear-Enable Register
+        ICER0: mmio.Mmio(packed struct(u32) {
+            ///  CLRENA
+            CLRENA: u32,
+        }),
+        ///  Interrupt Clear-Enable Register
+        ICER1: mmio.Mmio(packed struct(u32) {
+            ///  CLRENA
+            CLRENA: u32,
+        }),
+        reserved256: [120]u8,
+        ///  Interrupt Set-Pending Register
+        ISPR0: mmio.Mmio(packed struct(u32) {
+            ///  SETPEND
+            SETPEND: u32,
+        }),
+        ///  Interrupt Set-Pending Register
+        ISPR1: mmio.Mmio(packed struct(u32) {
+            ///  SETPEND
+            SETPEND: u32,
+        }),
+        reserved384: [120]u8,
+        ///  Interrupt Clear-Pending Register
+        ICPR0: mmio.Mmio(packed struct(u32) {
+            ///  CLRPEND
+            CLRPEND: u32,
+        }),
+        ///  Interrupt Clear-Pending Register
+        ICPR1: mmio.Mmio(packed struct(u32) {
+            ///  CLRPEND
+            CLRPEND: u32,
+        }),
+        reserved512: [120]u8,
+        ///  Interrupt Active Bit Register
+        IABR0: mmio.Mmio(packed struct(u32) {
+            ///  ACTIVE
+            ACTIVE: u32,
+        }),
+        ///  Interrupt Active Bit Register
+        IABR1: mmio.Mmio(packed struct(u32) {
+            ///  ACTIVE
+            ACTIVE: u32,
+        }),
+        reserved768: [248]u8,
+        ///  Interrupt Priority Register
+        IPR0: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR1: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR2: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR3: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR4: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR5: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR6: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR7: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR8: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR9: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR10: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR11: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR12: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR13: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR14: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+    };
+
+    ///  Alternate function I/O
+    pub const AFIO = extern struct {
+        ///  Event Control Register (AFIO_EVCR)
+        EVCR: mmio.Mmio(packed struct(u32) {
+            ///  Pin selection
+            PIN: u4,
+            ///  Port selection
+            PORT: u3,
+            ///  Event Output Enable
+            EVOE: u1,
+            padding: u24,
+        }),
+        ///  AF remap and debug I/O configuration register (AFIO_MAPR)
+        MAPR: mmio.Mmio(packed struct(u32) {
+            ///  SPI1 remapping
+            SPI1_REMAP: u1,
+            ///  I2C1 remapping
+            I2C1_REMAP: u1,
+            ///  USART1 remapping
+            USART1_REMAP: u1,
+            ///  USART2 remapping
+            USART2_REMAP: u1,
+            ///  USART3 remapping
+            USART3_REMAP: u2,
+            ///  TIM1 remapping
+            TIM1_REMAP: u2,
+            ///  TIM2 remapping
+            TIM2_REMAP: u2,
+            ///  TIM3 remapping
+            TIM3_REMAP: u2,
+            ///  TIM4 remapping
+            TIM4_REMAP: u1,
+            ///  CAN1 remapping
+            CAN_REMAP: u2,
+            ///  Port D0/Port D1 mapping on OSCIN/OSCOUT
+            PD01_REMAP: u1,
+            ///  Set and cleared by software
+            TIM5CH4_IREMAP: u1,
+            ///  ADC 1 External trigger injected conversion remapping
+            ADC1_ETRGINJ_REMAP: u1,
+            ///  ADC 1 external trigger regular conversion remapping
+            ADC1_ETRGREG_REMAP: u1,
+            ///  ADC 2 external trigger injected conversion remapping
+            ADC2_ETRGINJ_REMAP: u1,
+            ///  ADC 2 external trigger regular conversion remapping
+            ADC2_ETRGREG_REMAP: u1,
+            reserved24: u3,
+            ///  Serial wire JTAG configuration
+            SWJ_CFG: u3,
+            padding: u5,
+        }),
+        ///  External interrupt configuration register 1 (AFIO_EXTICR1)
+        EXTICR1: mmio.Mmio(packed struct(u32) {
+            ///  EXTI0 configuration
+            EXTI0: u4,
+            ///  EXTI1 configuration
+            EXTI1: u4,
+            ///  EXTI2 configuration
+            EXTI2: u4,
+            ///  EXTI3 configuration
+            EXTI3: u4,
+            padding: u16,
+        }),
+        ///  External interrupt configuration register 2 (AFIO_EXTICR2)
+        EXTICR2: mmio.Mmio(packed struct(u32) {
+            ///  EXTI4 configuration
+            EXTI4: u4,
+            ///  EXTI5 configuration
+            EXTI5: u4,
+            ///  EXTI6 configuration
+            EXTI6: u4,
+            ///  EXTI7 configuration
+            EXTI7: u4,
+            padding: u16,
+        }),
+        ///  External interrupt configuration register 3 (AFIO_EXTICR3)
+        EXTICR3: mmio.Mmio(packed struct(u32) {
+            ///  EXTI8 configuration
+            EXTI8: u4,
+            ///  EXTI9 configuration
+            EXTI9: u4,
+            ///  EXTI10 configuration
+            EXTI10: u4,
+            ///  EXTI11 configuration
+            EXTI11: u4,
+            padding: u16,
+        }),
+        ///  External interrupt configuration register 4 (AFIO_EXTICR4)
+        EXTICR4: mmio.Mmio(packed struct(u32) {
+            ///  EXTI12 configuration
+            EXTI12: u4,
+            ///  EXTI13 configuration
+            EXTI13: u4,
+            ///  EXTI14 configuration
+            EXTI14: u4,
+            ///  EXTI15 configuration
+            EXTI15: u4,
+            padding: u16,
+        }),
+        reserved28: [4]u8,
+        ///  AF remap and debug I/O configuration register
+        MAPR2: mmio.Mmio(packed struct(u32) {
+            reserved5: u5,
+            ///  TIM9 remapping
+            TIM9_REMAP: u1,
+            ///  TIM10 remapping
+            TIM10_REMAP: u1,
+            ///  TIM11 remapping
+            TIM11_REMAP: u1,
+            ///  TIM13 remapping
+            TIM13_REMAP: u1,
+            ///  TIM14 remapping
+            TIM14_REMAP: u1,
+            ///  NADV connect/disconnect
+            FSMC_NADV: u1,
+            padding: u21,
+        }),
+    };
+
+    ///  EXTI
+    pub const EXTI = extern struct {
+        ///  Interrupt mask register (EXTI_IMR)
+        IMR: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt Mask on line 0
+            MR0: u1,
+            ///  Interrupt Mask on line 1
+            MR1: u1,
+            ///  Interrupt Mask on line 2
+            MR2: u1,
+            ///  Interrupt Mask on line 3
+            MR3: u1,
+            ///  Interrupt Mask on line 4
+            MR4: u1,
+            ///  Interrupt Mask on line 5
+            MR5: u1,
+            ///  Interrupt Mask on line 6
+            MR6: u1,
+            ///  Interrupt Mask on line 7
+            MR7: u1,
+            ///  Interrupt Mask on line 8
+            MR8: u1,
+            ///  Interrupt Mask on line 9
+            MR9: u1,
+            ///  Interrupt Mask on line 10
+            MR10: u1,
+            ///  Interrupt Mask on line 11
+            MR11: u1,
+            ///  Interrupt Mask on line 12
+            MR12: u1,
+            ///  Interrupt Mask on line 13
+            MR13: u1,
+            ///  Interrupt Mask on line 14
+            MR14: u1,
+            ///  Interrupt Mask on line 15
+            MR15: u1,
+            ///  Interrupt Mask on line 16
+            MR16: u1,
+            ///  Interrupt Mask on line 17
+            MR17: u1,
+            ///  Interrupt Mask on line 18
+            MR18: u1,
+            padding: u13,
+        }),
+        ///  Event mask register (EXTI_EMR)
+        EMR: mmio.Mmio(packed struct(u32) {
+            ///  Event Mask on line 0
+            MR0: u1,
+            ///  Event Mask on line 1
+            MR1: u1,
+            ///  Event Mask on line 2
+            MR2: u1,
+            ///  Event Mask on line 3
+            MR3: u1,
+            ///  Event Mask on line 4
+            MR4: u1,
+            ///  Event Mask on line 5
+            MR5: u1,
+            ///  Event Mask on line 6
+            MR6: u1,
+            ///  Event Mask on line 7
+            MR7: u1,
+            ///  Event Mask on line 8
+            MR8: u1,
+            ///  Event Mask on line 9
+            MR9: u1,
+            ///  Event Mask on line 10
+            MR10: u1,
+            ///  Event Mask on line 11
+            MR11: u1,
+            ///  Event Mask on line 12
+            MR12: u1,
+            ///  Event Mask on line 13
+            MR13: u1,
+            ///  Event Mask on line 14
+            MR14: u1,
+            ///  Event Mask on line 15
+            MR15: u1,
+            ///  Event Mask on line 16
+            MR16: u1,
+            ///  Event Mask on line 17
+            MR17: u1,
+            ///  Event Mask on line 18
+            MR18: u1,
+            padding: u13,
+        }),
+        ///  Rising Trigger selection register (EXTI_RTSR)
+        RTSR: mmio.Mmio(packed struct(u32) {
+            ///  Rising trigger event configuration of line 0
+            TR0: u1,
+            ///  Rising trigger event configuration of line 1
+            TR1: u1,
+            ///  Rising trigger event configuration of line 2
+            TR2: u1,
+            ///  Rising trigger event configuration of line 3
+            TR3: u1,
+            ///  Rising trigger event configuration of line 4
+            TR4: u1,
+            ///  Rising trigger event configuration of line 5
+            TR5: u1,
+            ///  Rising trigger event configuration of line 6
+            TR6: u1,
+            ///  Rising trigger event configuration of line 7
+            TR7: u1,
+            ///  Rising trigger event configuration of line 8
+            TR8: u1,
+            ///  Rising trigger event configuration of line 9
+            TR9: u1,
+            ///  Rising trigger event configuration of line 10
+            TR10: u1,
+            ///  Rising trigger event configuration of line 11
+            TR11: u1,
+            ///  Rising trigger event configuration of line 12
+            TR12: u1,
+            ///  Rising trigger event configuration of line 13
+            TR13: u1,
+            ///  Rising trigger event configuration of line 14
+            TR14: u1,
+            ///  Rising trigger event configuration of line 15
+            TR15: u1,
+            ///  Rising trigger event configuration of line 16
+            TR16: u1,
+            ///  Rising trigger event configuration of line 17
+            TR17: u1,
+            ///  Rising trigger event configuration of line 18
+            TR18: u1,
+            padding: u13,
+        }),
+        ///  Falling Trigger selection register (EXTI_FTSR)
+        FTSR: mmio.Mmio(packed struct(u32) {
+            ///  Falling trigger event configuration of line 0
+            TR0: u1,
+            ///  Falling trigger event configuration of line 1
+            TR1: u1,
+            ///  Falling trigger event configuration of line 2
+            TR2: u1,
+            ///  Falling trigger event configuration of line 3
+            TR3: u1,
+            ///  Falling trigger event configuration of line 4
+            TR4: u1,
+            ///  Falling trigger event configuration of line 5
+            TR5: u1,
+            ///  Falling trigger event configuration of line 6
+            TR6: u1,
+            ///  Falling trigger event configuration of line 7
+            TR7: u1,
+            ///  Falling trigger event configuration of line 8
+            TR8: u1,
+            ///  Falling trigger event configuration of line 9
+            TR9: u1,
+            ///  Falling trigger event configuration of line 10
+            TR10: u1,
+            ///  Falling trigger event configuration of line 11
+            TR11: u1,
+            ///  Falling trigger event configuration of line 12
+            TR12: u1,
+            ///  Falling trigger event configuration of line 13
+            TR13: u1,
+            ///  Falling trigger event configuration of line 14
+            TR14: u1,
+            ///  Falling trigger event configuration of line 15
+            TR15: u1,
+            ///  Falling trigger event configuration of line 16
+            TR16: u1,
+            ///  Falling trigger event configuration of line 17
+            TR17: u1,
+            ///  Falling trigger event configuration of line 18
+            TR18: u1,
+            padding: u13,
+        }),
+        ///  Software interrupt event register (EXTI_SWIER)
+        SWIER: mmio.Mmio(packed struct(u32) {
+            ///  Software Interrupt on line 0
+            SWIER0: u1,
+            ///  Software Interrupt on line 1
+            SWIER1: u1,
+            ///  Software Interrupt on line 2
+            SWIER2: u1,
+            ///  Software Interrupt on line 3
+            SWIER3: u1,
+            ///  Software Interrupt on line 4
+            SWIER4: u1,
+            ///  Software Interrupt on line 5
+            SWIER5: u1,
+            ///  Software Interrupt on line 6
+            SWIER6: u1,
+            ///  Software Interrupt on line 7
+            SWIER7: u1,
+            ///  Software Interrupt on line 8
+            SWIER8: u1,
+            ///  Software Interrupt on line 9
+            SWIER9: u1,
+            ///  Software Interrupt on line 10
+            SWIER10: u1,
+            ///  Software Interrupt on line 11
+            SWIER11: u1,
+            ///  Software Interrupt on line 12
+            SWIER12: u1,
+            ///  Software Interrupt on line 13
+            SWIER13: u1,
+            ///  Software Interrupt on line 14
+            SWIER14: u1,
+            ///  Software Interrupt on line 15
+            SWIER15: u1,
+            ///  Software Interrupt on line 16
+            SWIER16: u1,
+            ///  Software Interrupt on line 17
+            SWIER17: u1,
+            ///  Software Interrupt on line 18
+            SWIER18: u1,
+            padding: u13,
+        }),
+        ///  Pending register (EXTI_PR)
+        PR: mmio.Mmio(packed struct(u32) {
+            ///  Pending bit 0
+            PR0: u1,
+            ///  Pending bit 1
+            PR1: u1,
+            ///  Pending bit 2
+            PR2: u1,
+            ///  Pending bit 3
+            PR3: u1,
+            ///  Pending bit 4
+            PR4: u1,
+            ///  Pending bit 5
+            PR5: u1,
+            ///  Pending bit 6
+            PR6: u1,
+            ///  Pending bit 7
+            PR7: u1,
+            ///  Pending bit 8
+            PR8: u1,
+            ///  Pending bit 9
+            PR9: u1,
+            ///  Pending bit 10
+            PR10: u1,
+            ///  Pending bit 11
+            PR11: u1,
+            ///  Pending bit 12
+            PR12: u1,
+            ///  Pending bit 13
+            PR13: u1,
+            ///  Pending bit 14
+            PR14: u1,
+            ///  Pending bit 15
+            PR15: u1,
+            ///  Pending bit 16
+            PR16: u1,
+            ///  Pending bit 17
+            PR17: u1,
+            ///  Pending bit 18
+            PR18: u1,
+            padding: u13,
+        }),
+    };
+
+    ///  DMA controller
+    pub const DMA1 = extern struct {
+        ///  DMA interrupt status register (DMA_ISR)
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  Channel 1 Global interrupt flag
+            GIF1: u1,
+            ///  Channel 1 Transfer Complete flag
+            TCIF1: u1,
+            ///  Channel 1 Half Transfer Complete flag
+            HTIF1: u1,
+            ///  Channel 1 Transfer Error flag
+            TEIF1: u1,
+            ///  Channel 2 Global interrupt flag
+            GIF2: u1,
+            ///  Channel 2 Transfer Complete flag
+            TCIF2: u1,
+            ///  Channel 2 Half Transfer Complete flag
+            HTIF2: u1,
+            ///  Channel 2 Transfer Error flag
+            TEIF2: u1,
+            ///  Channel 3 Global interrupt flag
+            GIF3: u1,
+            ///  Channel 3 Transfer Complete flag
+            TCIF3: u1,
+            ///  Channel 3 Half Transfer Complete flag
+            HTIF3: u1,
+            ///  Channel 3 Transfer Error flag
+            TEIF3: u1,
+            ///  Channel 4 Global interrupt flag
+            GIF4: u1,
+            ///  Channel 4 Transfer Complete flag
+            TCIF4: u1,
+            ///  Channel 4 Half Transfer Complete flag
+            HTIF4: u1,
+            ///  Channel 4 Transfer Error flag
+            TEIF4: u1,
+            ///  Channel 5 Global interrupt flag
+            GIF5: u1,
+            ///  Channel 5 Transfer Complete flag
+            TCIF5: u1,
+            ///  Channel 5 Half Transfer Complete flag
+            HTIF5: u1,
+            ///  Channel 5 Transfer Error flag
+            TEIF5: u1,
+            ///  Channel 6 Global interrupt flag
+            GIF6: u1,
+            ///  Channel 6 Transfer Complete flag
+            TCIF6: u1,
+            ///  Channel 6 Half Transfer Complete flag
+            HTIF6: u1,
+            ///  Channel 6 Transfer Error flag
+            TEIF6: u1,
+            ///  Channel 7 Global interrupt flag
+            GIF7: u1,
+            ///  Channel 7 Transfer Complete flag
+            TCIF7: u1,
+            ///  Channel 7 Half Transfer Complete flag
+            HTIF7: u1,
+            ///  Channel 7 Transfer Error flag
+            TEIF7: u1,
+            padding: u4,
+        }),
+        ///  DMA interrupt flag clear register (DMA_IFCR)
+        IFCR: mmio.Mmio(packed struct(u32) {
+            ///  Channel 1 Global interrupt clear
+            CGIF1: u1,
+            ///  Channel 1 Transfer Complete clear
+            CTCIF1: u1,
+            ///  Channel 1 Half Transfer clear
+            CHTIF1: u1,
+            ///  Channel 1 Transfer Error clear
+            CTEIF1: u1,
+            ///  Channel 2 Global interrupt clear
+            CGIF2: u1,
+            ///  Channel 2 Transfer Complete clear
+            CTCIF2: u1,
+            ///  Channel 2 Half Transfer clear
+            CHTIF2: u1,
+            ///  Channel 2 Transfer Error clear
+            CTEIF2: u1,
+            ///  Channel 3 Global interrupt clear
+            CGIF3: u1,
+            ///  Channel 3 Transfer Complete clear
+            CTCIF3: u1,
+            ///  Channel 3 Half Transfer clear
+            CHTIF3: u1,
+            ///  Channel 3 Transfer Error clear
+            CTEIF3: u1,
+            ///  Channel 4 Global interrupt clear
+            CGIF4: u1,
+            ///  Channel 4 Transfer Complete clear
+            CTCIF4: u1,
+            ///  Channel 4 Half Transfer clear
+            CHTIF4: u1,
+            ///  Channel 4 Transfer Error clear
+            CTEIF4: u1,
+            ///  Channel 5 Global interrupt clear
+            CGIF5: u1,
+            ///  Channel 5 Transfer Complete clear
+            CTCIF5: u1,
+            ///  Channel 5 Half Transfer clear
+            CHTIF5: u1,
+            ///  Channel 5 Transfer Error clear
+            CTEIF5: u1,
+            ///  Channel 6 Global interrupt clear
+            CGIF6: u1,
+            ///  Channel 6 Transfer Complete clear
+            CTCIF6: u1,
+            ///  Channel 6 Half Transfer clear
+            CHTIF6: u1,
+            ///  Channel 6 Transfer Error clear
+            CTEIF6: u1,
+            ///  Channel 7 Global interrupt clear
+            CGIF7: u1,
+            ///  Channel 7 Transfer Complete clear
+            CTCIF7: u1,
+            ///  Channel 7 Half Transfer clear
+            CHTIF7: u1,
+            ///  Channel 7 Transfer Error clear
+            CTEIF7: u1,
+            padding: u4,
+        }),
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 1 number of data register
+        CNDTR1: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 1 peripheral address register
+        CPAR1: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 1 memory address register
+        CMAR1: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved28: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 2 number of data register
+        CNDTR2: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 2 peripheral address register
+        CPAR2: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 2 memory address register
+        CMAR2: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved48: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 3 number of data register
+        CNDTR3: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 3 peripheral address register
+        CPAR3: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 3 memory address register
+        CMAR3: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved68: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 4 number of data register
+        CNDTR4: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 4 peripheral address register
+        CPAR4: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 4 memory address register
+        CMAR4: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved88: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR5: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 5 number of data register
+        CNDTR5: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 5 peripheral address register
+        CPAR5: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 5 memory address register
+        CMAR5: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved108: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR6: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 6 number of data register
+        CNDTR6: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 6 peripheral address register
+        CPAR6: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 6 memory address register
+        CMAR6: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved128: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR7: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 7 number of data register
+        CNDTR7: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 7 peripheral address register
+        CPAR7: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 7 memory address register
+        CMAR7: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+    };
+
+    ///  Ethernet: DMA controller operation
+    pub const ETHERNET_DMA = extern struct {
+        ///  Ethernet DMA bus mode register
+        DMABMR: mmio.Mmio(packed struct(u32) {
+            ///  Software reset
+            SR: u1,
+            ///  DMA Arbitration
+            DA: u1,
+            ///  Descriptor skip length
+            DSL: u5,
+            reserved8: u1,
+            ///  Programmable burst length
+            PBL: u6,
+            ///  Rx Tx priority ratio
+            RTPR: u2,
+            ///  Fixed burst
+            FB: u1,
+            ///  Rx DMA PBL
+            RDP: u6,
+            ///  Use separate PBL
+            USP: u1,
+            ///  4xPBL mode
+            FPM: u1,
+            ///  Address-aligned beats
+            AAB: u1,
+            padding: u6,
+        }),
+        ///  Ethernet DMA transmit poll demand register
+        DMATPDR: mmio.Mmio(packed struct(u32) {
+            ///  Transmit poll demand
+            TPD: u32,
+        }),
+        ///  EHERNET DMA receive poll demand register
+        DMARPDR: mmio.Mmio(packed struct(u32) {
+            ///  Receive poll demand
+            RPD: u32,
+        }),
+        ///  Ethernet DMA receive descriptor list address register
+        DMARDLAR: mmio.Mmio(packed struct(u32) {
+            ///  Start of receive list
+            SRL: u32,
+        }),
+        ///  Ethernet DMA transmit descriptor list address register
+        DMATDLAR: mmio.Mmio(packed struct(u32) {
+            ///  Start of transmit list
+            STL: u32,
+        }),
+        ///  Ethernet DMA status register
+        DMASR: mmio.Mmio(packed struct(u32) {
+            ///  Transmit status
+            TS: u1,
+            ///  Transmit process stopped status
+            TPSS: u1,
+            ///  Transmit buffer unavailable status
+            TBUS: u1,
+            ///  Transmit jabber timeout status
+            TJTS: u1,
+            ///  Receive overflow status
+            ROS: u1,
+            ///  Transmit underflow status
+            TUS: u1,
+            ///  Receive status
+            RS: u1,
+            ///  Receive buffer unavailable status
+            RBUS: u1,
+            ///  Receive process stopped status
+            RPSS: u1,
+            ///  Receive watchdog timeout status
+            PWTS: u1,
+            ///  Early transmit status
+            ETS: u1,
+            reserved13: u2,
+            ///  Fatal bus error status
+            FBES: u1,
+            ///  Early receive status
+            ERS: u1,
+            ///  Abnormal interrupt summary
+            AIS: u1,
+            ///  Normal interrupt summary
+            NIS: u1,
+            ///  Receive process state
+            RPS: u3,
+            ///  Transmit process state
+            TPS: u3,
+            ///  Error bits status
+            EBS: u3,
+            reserved27: u1,
+            ///  MMC status
+            MMCS: u1,
+            ///  PMT status
+            PMTS: u1,
+            ///  Time stamp trigger status
+            TSTS: u1,
+            padding: u2,
+        }),
+        ///  Ethernet DMA operation mode register
+        DMAOMR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  SR
+            SR: u1,
+            ///  OSF
+            OSF: u1,
+            ///  RTC
+            RTC: u2,
+            reserved6: u1,
+            ///  FUGF
+            FUGF: u1,
+            ///  FEF
+            FEF: u1,
+            reserved13: u5,
+            ///  ST
+            ST: u1,
+            ///  TTC
+            TTC: u3,
+            reserved20: u3,
+            ///  FTF
+            FTF: u1,
+            ///  TSF
+            TSF: u1,
+            reserved24: u2,
+            ///  DFRF
+            DFRF: u1,
+            ///  RSF
+            RSF: u1,
+            ///  DTCEFD
+            DTCEFD: u1,
+            padding: u5,
+        }),
+        ///  Ethernet DMA interrupt enable register
+        DMAIER: mmio.Mmio(packed struct(u32) {
+            ///  Transmit interrupt enable
+            TIE: u1,
+            ///  Transmit process stopped interrupt enable
+            TPSIE: u1,
+            ///  Transmit buffer unavailable interrupt enable
+            TBUIE: u1,
+            ///  Transmit jabber timeout interrupt enable
+            TJTIE: u1,
+            ///  Overflow interrupt enable
+            ROIE: u1,
+            ///  Underflow interrupt enable
+            TUIE: u1,
+            ///  Receive interrupt enable
+            RIE: u1,
+            ///  Receive buffer unavailable interrupt enable
+            RBUIE: u1,
+            ///  Receive process stopped interrupt enable
+            RPSIE: u1,
+            ///  receive watchdog timeout interrupt enable
+            RWTIE: u1,
+            ///  Early transmit interrupt enable
+            ETIE: u1,
+            reserved13: u2,
+            ///  Fatal bus error interrupt enable
+            FBEIE: u1,
+            ///  Early receive interrupt enable
+            ERIE: u1,
+            ///  Abnormal interrupt summary enable
+            AISE: u1,
+            ///  Normal interrupt summary enable
+            NISE: u1,
+            padding: u15,
+        }),
+        ///  Ethernet DMA missed frame and buffer overflow counter register
+        DMAMFBOCR: mmio.Mmio(packed struct(u32) {
+            ///  Missed frames by the controller
+            MFC: u16,
+            ///  Overflow bit for missed frame counter
+            OMFC: u1,
+            ///  Missed frames by the application
+            MFA: u11,
+            ///  Overflow bit for FIFO overflow counter
+            OFOC: u1,
+            padding: u3,
+        }),
+        reserved72: [36]u8,
+        ///  Ethernet DMA current host transmit descriptor register
+        DMACHTDR: mmio.Mmio(packed struct(u32) {
+            ///  Host transmit descriptor address pointer
+            HTDAP: u32,
+        }),
+        ///  Ethernet DMA current host receive descriptor register
+        DMACHRDR: mmio.Mmio(packed struct(u32) {
+            ///  Host receive descriptor address pointer
+            HRDAP: u32,
+        }),
+        ///  Ethernet DMA current host transmit buffer address register
+        DMACHTBAR: mmio.Mmio(packed struct(u32) {
+            ///  Host transmit buffer address pointer
+            HTBAP: u32,
+        }),
+        ///  Ethernet DMA current host receive buffer address register
+        DMACHRBAR: mmio.Mmio(packed struct(u32) {
+            ///  Host receive buffer address pointer
+            HRBAP: u32,
+        }),
+    };
+
+    ///  Secure digital input/output interface
+    pub const SDIO = extern struct {
+        ///  Bits 1:0 = PWRCTRL: Power supply control bits
+        POWER: mmio.Mmio(packed struct(u32) {
+            ///  PWRCTRL
+            PWRCTRL: u2,
+            padding: u30,
+        }),
+        ///  SDI clock control register (SDIO_CLKCR)
+        CLKCR: mmio.Mmio(packed struct(u32) {
+            ///  Clock divide factor
+            CLKDIV: u8,
+            ///  Clock enable bit
+            CLKEN: u1,
+            ///  Power saving configuration bit
+            PWRSAV: u1,
+            ///  Clock divider bypass enable bit
+            BYPASS: u1,
+            ///  Wide bus mode enable bit
+            WIDBUS: u2,
+            ///  SDIO_CK dephasing selection bit
+            NEGEDGE: u1,
+            ///  HW Flow Control enable
+            HWFC_EN: u1,
+            padding: u17,
+        }),
+        ///  Bits 31:0 = : Command argument
+        ARG: mmio.Mmio(packed struct(u32) {
+            ///  Command argument
+            CMDARG: u32,
+        }),
+        ///  SDIO command register (SDIO_CMD)
+        CMD: mmio.Mmio(packed struct(u32) {
+            ///  CMDINDEX
+            CMDINDEX: u6,
+            ///  WAITRESP
+            WAITRESP: u2,
+            ///  WAITINT
+            WAITINT: u1,
+            ///  WAITPEND
+            WAITPEND: u1,
+            ///  CPSMEN
+            CPSMEN: u1,
+            ///  SDIOSuspend
+            SDIOSuspend: u1,
+            ///  ENCMDcompl
+            ENCMDcompl: u1,
+            ///  nIEN
+            nIEN: u1,
+            ///  CE_ATACMD
+            CE_ATACMD: u1,
+            padding: u17,
+        }),
+        ///  SDIO command register
+        RESPCMD: mmio.Mmio(packed struct(u32) {
+            ///  RESPCMD
+            RESPCMD: u6,
+            padding: u26,
+        }),
+        ///  Bits 31:0 = CARDSTATUS1
+        RESPI1: mmio.Mmio(packed struct(u32) {
+            ///  CARDSTATUS1
+            CARDSTATUS1: u32,
+        }),
+        ///  Bits 31:0 = CARDSTATUS2
+        RESP2: mmio.Mmio(packed struct(u32) {
+            ///  CARDSTATUS2
+            CARDSTATUS2: u32,
+        }),
+        ///  Bits 31:0 = CARDSTATUS3
+        RESP3: mmio.Mmio(packed struct(u32) {
+            ///  CARDSTATUS3
+            CARDSTATUS3: u32,
+        }),
+        ///  Bits 31:0 = CARDSTATUS4
+        RESP4: mmio.Mmio(packed struct(u32) {
+            ///  CARDSTATUS4
+            CARDSTATUS4: u32,
+        }),
+        ///  Bits 31:0 = DATATIME: Data timeout period
+        DTIMER: mmio.Mmio(packed struct(u32) {
+            ///  Data timeout period
+            DATATIME: u32,
+        }),
+        ///  Bits 24:0 = DATALENGTH: Data length value
+        DLEN: mmio.Mmio(packed struct(u32) {
+            ///  Data length value
+            DATALENGTH: u25,
+            padding: u7,
+        }),
+        ///  SDIO data control register (SDIO_DCTRL)
+        DCTRL: mmio.Mmio(packed struct(u32) {
+            ///  DTEN
+            DTEN: u1,
+            ///  DTDIR
+            DTDIR: u1,
+            ///  DTMODE
+            DTMODE: u1,
+            ///  DMAEN
+            DMAEN: u1,
+            ///  DBLOCKSIZE
+            DBLOCKSIZE: u4,
+            ///  PWSTART
+            PWSTART: u1,
+            ///  PWSTOP
+            PWSTOP: u1,
+            ///  RWMOD
+            RWMOD: u1,
+            ///  SDIOEN
+            SDIOEN: u1,
+            padding: u20,
+        }),
+        ///  Bits 24:0 = DATACOUNT: Data count value
+        DCOUNT: mmio.Mmio(packed struct(u32) {
+            ///  Data count value
+            DATACOUNT: u25,
+            padding: u7,
+        }),
+        ///  SDIO status register (SDIO_STA)
+        STA: mmio.Mmio(packed struct(u32) {
+            ///  CCRCFAIL
+            CCRCFAIL: u1,
+            ///  DCRCFAIL
+            DCRCFAIL: u1,
+            ///  CTIMEOUT
+            CTIMEOUT: u1,
+            ///  DTIMEOUT
+            DTIMEOUT: u1,
+            ///  TXUNDERR
+            TXUNDERR: u1,
+            ///  RXOVERR
+            RXOVERR: u1,
+            ///  CMDREND
+            CMDREND: u1,
+            ///  CMDSENT
+            CMDSENT: u1,
+            ///  DATAEND
+            DATAEND: u1,
+            ///  STBITERR
+            STBITERR: u1,
+            ///  DBCKEND
+            DBCKEND: u1,
+            ///  CMDACT
+            CMDACT: u1,
+            ///  TXACT
+            TXACT: u1,
+            ///  RXACT
+            RXACT: u1,
+            ///  TXFIFOHE
+            TXFIFOHE: u1,
+            ///  RXFIFOHF
+            RXFIFOHF: u1,
+            ///  TXFIFOF
+            TXFIFOF: u1,
+            ///  RXFIFOF
+            RXFIFOF: u1,
+            ///  TXFIFOE
+            TXFIFOE: u1,
+            ///  RXFIFOE
+            RXFIFOE: u1,
+            ///  TXDAVL
+            TXDAVL: u1,
+            ///  RXDAVL
+            RXDAVL: u1,
+            ///  SDIOIT
+            SDIOIT: u1,
+            ///  CEATAEND
+            CEATAEND: u1,
+            padding: u8,
+        }),
+        ///  SDIO interrupt clear register (SDIO_ICR)
+        ICR: mmio.Mmio(packed struct(u32) {
+            ///  CCRCFAILC
+            CCRCFAILC: u1,
+            ///  DCRCFAILC
+            DCRCFAILC: u1,
+            ///  CTIMEOUTC
+            CTIMEOUTC: u1,
+            ///  DTIMEOUTC
+            DTIMEOUTC: u1,
+            ///  TXUNDERRC
+            TXUNDERRC: u1,
+            ///  RXOVERRC
+            RXOVERRC: u1,
+            ///  CMDRENDC
+            CMDRENDC: u1,
+            ///  CMDSENTC
+            CMDSENTC: u1,
+            ///  DATAENDC
+            DATAENDC: u1,
+            ///  STBITERRC
+            STBITERRC: u1,
+            ///  DBCKENDC
+            DBCKENDC: u1,
+            reserved22: u11,
+            ///  SDIOITC
+            SDIOITC: u1,
+            ///  CEATAENDC
+            CEATAENDC: u1,
+            padding: u8,
+        }),
+        ///  SDIO mask register (SDIO_MASK)
+        MASK: mmio.Mmio(packed struct(u32) {
+            ///  CCRCFAILIE
+            CCRCFAILIE: u1,
+            ///  DCRCFAILIE
+            DCRCFAILIE: u1,
+            ///  CTIMEOUTIE
+            CTIMEOUTIE: u1,
+            ///  DTIMEOUTIE
+            DTIMEOUTIE: u1,
+            ///  TXUNDERRIE
+            TXUNDERRIE: u1,
+            ///  RXOVERRIE
+            RXOVERRIE: u1,
+            ///  CMDRENDIE
+            CMDRENDIE: u1,
+            ///  CMDSENTIE
+            CMDSENTIE: u1,
+            ///  DATAENDIE
+            DATAENDIE: u1,
+            ///  STBITERRIE
+            STBITERRIE: u1,
+            ///  DBACKENDIE
+            DBACKENDIE: u1,
+            ///  CMDACTIE
+            CMDACTIE: u1,
+            ///  TXACTIE
+            TXACTIE: u1,
+            ///  RXACTIE
+            RXACTIE: u1,
+            ///  TXFIFOHEIE
+            TXFIFOHEIE: u1,
+            ///  RXFIFOHFIE
+            RXFIFOHFIE: u1,
+            ///  TXFIFOFIE
+            TXFIFOFIE: u1,
+            ///  RXFIFOFIE
+            RXFIFOFIE: u1,
+            ///  TXFIFOEIE
+            TXFIFOEIE: u1,
+            ///  RXFIFOEIE
+            RXFIFOEIE: u1,
+            ///  TXDAVLIE
+            TXDAVLIE: u1,
+            ///  RXDAVLIE
+            RXDAVLIE: u1,
+            ///  SDIOITIE
+            SDIOITIE: u1,
+            ///  CEATENDIE
+            CEATENDIE: u1,
+            padding: u8,
+        }),
+        reserved72: [8]u8,
+        ///  Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO
+        FIFOCNT: mmio.Mmio(packed struct(u32) {
+            ///  FIF0COUNT
+            FIF0COUNT: u24,
+            padding: u8,
+        }),
+        reserved128: [52]u8,
+        ///  bits 31:0 = FIFOData: Receive and transmit FIFO data
+        FIFO: mmio.Mmio(packed struct(u32) {
+            ///  FIFOData
+            FIFOData: u32,
+        }),
+    };
+
+    ///  Real time clock
+    pub const RTC = extern struct {
+        ///  RTC Control Register High
+        CRH: mmio.Mmio(packed struct(u32) {
+            ///  Second interrupt Enable
+            SECIE: u1,
+            ///  Alarm interrupt Enable
+            ALRIE: u1,
+            ///  Overflow interrupt Enable
+            OWIE: u1,
+            padding: u29,
+        }),
+        ///  RTC Control Register Low
+        CRL: mmio.Mmio(packed struct(u32) {
+            ///  Second Flag
+            SECF: u1,
+            ///  Alarm Flag
+            ALRF: u1,
+            ///  Overflow Flag
+            OWF: u1,
+            ///  Registers Synchronized Flag
+            RSF: u1,
+            ///  Configuration Flag
+            CNF: u1,
+            ///  RTC operation OFF
+            RTOFF: u1,
+            padding: u26,
+        }),
+        ///  RTC Prescaler Load Register High
+        PRLH: mmio.Mmio(packed struct(u32) {
+            ///  RTC Prescaler Load Register High
+            PRLH: u4,
+            padding: u28,
+        }),
+        ///  RTC Prescaler Load Register Low
+        PRLL: mmio.Mmio(packed struct(u32) {
+            ///  RTC Prescaler Divider Register Low
+            PRLL: u16,
+            padding: u16,
+        }),
+        ///  RTC Prescaler Divider Register High
+        DIVH: mmio.Mmio(packed struct(u32) {
+            ///  RTC prescaler divider register high
+            DIVH: u4,
+            padding: u28,
+        }),
+        ///  RTC Prescaler Divider Register Low
+        DIVL: mmio.Mmio(packed struct(u32) {
+            ///  RTC prescaler divider register Low
+            DIVL: u16,
+            padding: u16,
+        }),
+        ///  RTC Counter Register High
+        CNTH: mmio.Mmio(packed struct(u32) {
+            ///  RTC counter register high
+            CNTH: u16,
+            padding: u16,
+        }),
+        ///  RTC Counter Register Low
+        CNTL: mmio.Mmio(packed struct(u32) {
+            ///  RTC counter register Low
+            CNTL: u16,
+            padding: u16,
+        }),
+        ///  RTC Alarm Register High
+        ALRH: mmio.Mmio(packed struct(u32) {
+            ///  RTC alarm register high
+            ALRH: u16,
+            padding: u16,
+        }),
+        ///  RTC Alarm Register Low
+        ALRL: mmio.Mmio(packed struct(u32) {
+            ///  RTC alarm register low
+            ALRL: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Backup registers
+    pub const BKP = extern struct {
+        ///  Backup data register (BKP_DR)
+        DR1: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D1: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR2: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D2: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR3: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D3: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR4: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D4: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR5: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D5: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR6: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D6: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR7: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D7: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR8: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D8: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR9: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D9: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR10: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D10: u16,
+            padding: u16,
+        }),
+        ///  RTC clock calibration register (BKP_RTCCR)
+        RTCCR: mmio.Mmio(packed struct(u32) {
+            ///  Calibration value
+            CAL: u7,
+            ///  Calibration Clock Output
+            CCO: u1,
+            ///  Alarm or second output enable
+            ASOE: u1,
+            ///  Alarm or second output selection
+            ASOS: u1,
+            padding: u22,
+        }),
+        ///  Backup control register (BKP_CR)
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Tamper pin enable
+            TPE: u1,
+            ///  Tamper pin active level
+            TPAL: u1,
+            padding: u30,
+        }),
+        ///  BKP_CSR control/status register (BKP_CSR)
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  Clear Tamper event
+            CTE: u1,
+            ///  Clear Tamper Interrupt
+            CTI: u1,
+            ///  Tamper Pin interrupt enable
+            TPIE: u1,
+            reserved8: u5,
+            ///  Tamper Event Flag
+            TEF: u1,
+            ///  Tamper Interrupt Flag
+            TIF: u1,
+            padding: u22,
+        }),
+        reserved60: [8]u8,
+        ///  Backup data register (BKP_DR)
+        DR11: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            DR11: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR12: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            DR12: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR13: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            DR13: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR14: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D14: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR15: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D15: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR16: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D16: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR17: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D17: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR18: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D18: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR19: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D19: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR20: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D20: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR21: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D21: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR22: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D22: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR23: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D23: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR24: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D24: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR25: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D25: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR26: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D26: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR27: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D27: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR28: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D28: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR29: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D29: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR30: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D30: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR31: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D31: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR32: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D32: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR33: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D33: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR34: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D34: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR35: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D35: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR36: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D36: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR37: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D37: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR38: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D38: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR39: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D39: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR40: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D40: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR41: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D41: u16,
+            padding: u16,
+        }),
+        ///  Backup data register (BKP_DR)
+        DR42: mmio.Mmio(packed struct(u32) {
+            ///  Backup data
+            D42: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Independent watchdog
+    pub const IWDG = extern struct {
+        ///  Key register (IWDG_KR)
+        KR: mmio.Mmio(packed struct(u32) {
+            ///  Key value
+            KEY: u16,
+            padding: u16,
+        }),
+        ///  Prescaler register (IWDG_PR)
+        PR: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler divider
+            PR: u3,
+            padding: u29,
+        }),
+        ///  Reload register (IWDG_RLR)
+        RLR: mmio.Mmio(packed struct(u32) {
+            ///  Watchdog counter reload value
+            RL: u12,
+            padding: u20,
+        }),
+        ///  Status register (IWDG_SR)
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Watchdog prescaler value update
+            PVU: u1,
+            ///  Watchdog counter reload value update
+            RVU: u1,
+            padding: u30,
+        }),
+    };
+
+    ///  Window watchdog
+    pub const WWDG = extern struct {
+        ///  Control register (WWDG_CR)
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  7-bit counter (MSB to LSB)
+            T: u7,
+            ///  Activation bit
+            WDGA: u1,
+            padding: u24,
+        }),
+        ///  Configuration register (WWDG_CFR)
+        CFR: mmio.Mmio(packed struct(u32) {
+            ///  7-bit window value
+            W: u7,
+            ///  Timer Base
+            WDGTB: u2,
+            ///  Early Wakeup Interrupt
+            EWI: u1,
+            padding: u22,
+        }),
+        ///  Status register (WWDG_SR)
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Early Wakeup Interrupt
+            EWI: u1,
+            padding: u31,
+        }),
+    };
+
+    ///  Advanced timer
+    pub const TIM1 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/compare preloaded control
+            CCPC: u1,
+            reserved2: u1,
+            ///  Capture/compare control update selection
+            CCUS: u1,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            ///  Output Idle state 1
+            OIS1: u1,
+            ///  Output Idle state 1
+            OIS1N: u1,
+            ///  Output Idle state 2
+            OIS2: u1,
+            ///  Output Idle state 2
+            OIS2N: u1,
+            ///  Output Idle state 3
+            OIS3: u1,
+            ///  Output Idle state 3
+            OIS3N: u1,
+            ///  Output Idle state 4
+            OIS4: u1,
+            padding: u17,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            padding: u16,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            ///  COM interrupt enable
+            COMIE: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            ///  Break interrupt enable
+            BIE: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            ///  COM DMA request enable
+            COMDE: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            ///  COM interrupt flag
+            COMIF: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            ///  Break interrupt flag
+            BIF: u1,
+            reserved9: u1,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            padding: u19,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            ///  Capture/Compare control update generation
+            COMG: u1,
+            ///  Trigger generation
+            TG: u1,
+            ///  Break generation
+            BG: u1,
+            padding: u24,
+        }),
+        ///  capture/compare mode register (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            ///  Output Compare 1 clear enable
+            OC1CE: u1,
+            ///  Capture/Compare 2 selection
+            CC2S: u2,
+            ///  Output Compare 2 fast enable
+            OC2FE: u1,
+            ///  Output Compare 2 preload enable
+            OC2PE: u1,
+            ///  Output Compare 2 mode
+            OC2M: u3,
+            ///  Output Compare 2 clear enable
+            OC2CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare mode register (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 3 selection
+            CC3S: u2,
+            ///  Output compare 3 fast enable
+            OC3FE: u1,
+            ///  Output compare 3 preload enable
+            OC3PE: u1,
+            ///  Output compare 3 mode
+            OC3M: u3,
+            ///  Output compare 3 clear enable
+            OC3CE: u1,
+            ///  Capture/Compare 4 selection
+            CC4S: u2,
+            ///  Output compare 4 fast enable
+            OC4FE: u1,
+            ///  Output compare 4 preload enable
+            OC4PE: u1,
+            ///  Output compare 4 mode
+            OC4M: u3,
+            ///  Output compare 4 clear enable
+            OC4CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            ///  Capture/Compare 1 complementary output enable
+            CC1NE: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            ///  Capture/Compare 2 complementary output enable
+            CC2NE: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            ///  Capture/Compare 3 complementary output enable
+            CC3NE: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            padding: u18,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        ///  repetition counter register
+        RCR: mmio.Mmio(packed struct(u32) {
+            ///  Repetition counter value
+            REP: u8,
+            padding: u24,
+        }),
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 2 value
+            CCR2: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare value
+            CCR3: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare value
+            CCR4: u16,
+            padding: u16,
+        }),
+        ///  break and dead-time register
+        BDTR: mmio.Mmio(packed struct(u32) {
+            ///  Dead-time generator setup
+            DTG: u8,
+            ///  Lock configuration
+            LOCK: u2,
+            ///  Off-state selection for Idle mode
+            OSSI: u1,
+            ///  Off-state selection for Run mode
+            OSSR: u1,
+            ///  Break enable
+            BKE: u1,
+            ///  Break polarity
+            BKP: u1,
+            ///  Automatic output enable
+            AOE: u1,
+            ///  Main output enable
+            MOE: u1,
+            padding: u16,
+        }),
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Ethernet: Precision time protocol
+    pub const ETHERNET_PTP = extern struct {
+        ///  Ethernet PTP time stamp control register (ETH_PTPTSCR)
+        PTPTSCR: mmio.Mmio(packed struct(u32) {
+            ///  Time stamp enable
+            TSE: u1,
+            ///  Time stamp fine or coarse update
+            TSFCU: u1,
+            ///  Time stamp system time initialize
+            TSSTI: u1,
+            ///  Time stamp system time update
+            TSSTU: u1,
+            ///  Time stamp interrupt trigger enable
+            TSITE: u1,
+            ///  Time stamp addend register update
+            TSARU: u1,
+            padding: u26,
+        }),
+        ///  Ethernet PTP subsecond increment register
+        PTPSSIR: mmio.Mmio(packed struct(u32) {
+            ///  System time subsecond increment
+            STSSI: u8,
+            padding: u24,
+        }),
+        ///  Ethernet PTP time stamp high register
+        PTPTSHR: mmio.Mmio(packed struct(u32) {
+            ///  System time second
+            STS: u32,
+        }),
+        ///  Ethernet PTP time stamp low register (ETH_PTPTSLR)
+        PTPTSLR: mmio.Mmio(packed struct(u32) {
+            ///  System time subseconds
+            STSS: u31,
+            ///  System time positive or negative sign
+            STPNS: u1,
+        }),
+        ///  Ethernet PTP time stamp high update register
+        PTPTSHUR: mmio.Mmio(packed struct(u32) {
+            ///  Time stamp update second
+            TSUS: u32,
+        }),
+        ///  Ethernet PTP time stamp low update register (ETH_PTPTSLUR)
+        PTPTSLUR: mmio.Mmio(packed struct(u32) {
+            ///  Time stamp update subseconds
+            TSUSS: u31,
+            ///  Time stamp update positive or negative sign
+            TSUPNS: u1,
+        }),
+        ///  Ethernet PTP time stamp addend register
+        PTPTSAR: mmio.Mmio(packed struct(u32) {
+            ///  Time stamp addend
+            TSA: u32,
+        }),
+        ///  Ethernet PTP target time high register
+        PTPTTHR: mmio.Mmio(packed struct(u32) {
+            ///  Target time stamp high
+            TTSH: u32,
+        }),
+        ///  Ethernet PTP target time low register
+        PTPTTLR: mmio.Mmio(packed struct(u32) {
+            ///  Target time stamp low
+            TTSL: u32,
+        }),
+    };
+
+    ///  General purpose timer
+    pub const TIM2 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            padding: u24,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            padding: u16,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            reserved6: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            reserved8: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            reserved14: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            reserved6: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            reserved9: u2,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            padding: u19,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            reserved6: u1,
+            ///  Trigger generation
+            TG: u1,
+            padding: u25,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output compare 1 fast enable
+            OC1FE: u1,
+            ///  Output compare 1 preload enable
+            OC1PE: u1,
+            ///  Output compare 1 mode
+            OC1M: u3,
+            ///  Output compare 1 clear enable
+            OC1CE: u1,
+            ///  Capture/Compare 2 selection
+            CC2S: u2,
+            ///  Output compare 2 fast enable
+            OC2FE: u1,
+            ///  Output compare 2 preload enable
+            OC2PE: u1,
+            ///  Output compare 2 mode
+            OC2M: u3,
+            ///  Output compare 2 clear enable
+            OC2CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare mode register 2 (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 3 selection
+            CC3S: u2,
+            ///  Output compare 3 fast enable
+            OC3FE: u1,
+            ///  Output compare 3 preload enable
+            OC3PE: u1,
+            ///  Output compare 3 mode
+            OC3M: u3,
+            ///  Output compare 3 clear enable
+            OC3CE: u1,
+            ///  Capture/Compare 4 selection
+            CC4S: u2,
+            ///  Output compare 4 fast enable
+            OC4FE: u1,
+            ///  Output compare 4 preload enable
+            OC4PE: u1,
+            ///  Output compare 4 mode
+            OC4M: u3,
+            ///  Output compare 4 clear enable
+            O24CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved4: u2,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved8: u2,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            reserved12: u2,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            padding: u18,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 2 value
+            CCR2: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare value
+            CCR3: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare value
+            CCR4: u16,
+            padding: u16,
+        }),
+        reserved72: [4]u8,
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Ethernet: media access control
+    pub const ETHERNET_MAC = extern struct {
+        ///  Ethernet MAC configuration register (ETH_MACCR)
+        MACCR: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Receiver enable
+            RE: u1,
+            ///  Transmitter enable
+            TE: u1,
+            ///  Deferral check
+            DC: u1,
+            ///  Back-off limit
+            BL: u2,
+            ///  Automatic pad/CRC stripping
+            APCS: u1,
+            reserved9: u1,
+            ///  Retry disable
+            RD: u1,
+            ///  IPv4 checksum offload
+            IPCO: u1,
+            ///  Duplex mode
+            DM: u1,
+            ///  Loopback mode
+            LM: u1,
+            ///  Receive own disable
+            ROD: u1,
+            ///  Fast Ethernet speed
+            FES: u1,
+            reserved16: u1,
+            ///  Carrier sense disable
+            CSD: u1,
+            ///  Interframe gap
+            IFG: u3,
+            reserved22: u2,
+            ///  Jabber disable
+            JD: u1,
+            ///  Watchdog disable
+            WD: u1,
+            padding: u8,
+        }),
+        ///  Ethernet MAC frame filter register (ETH_MACCFFR)
+        MACFFR: mmio.Mmio(packed struct(u32) {
+            ///  Promiscuous mode
+            PM: u1,
+            ///  Hash unicast
+            HU: u1,
+            ///  Hash multicast
+            HM: u1,
+            ///  Destination address inverse filtering
+            DAIF: u1,
+            ///  Pass all multicast
+            PAM: u1,
+            ///  Broadcast frames disable
+            BFD: u1,
+            ///  Pass control frames
+            PCF: u2,
+            ///  Source address inverse filtering
+            SAIF: u1,
+            ///  Source address filter
+            SAF: u1,
+            ///  Hash or perfect filter
+            HPF: u1,
+            reserved31: u20,
+            ///  Receive all
+            RA: u1,
+        }),
+        ///  Ethernet MAC hash table high register
+        MACHTHR: mmio.Mmio(packed struct(u32) {
+            ///  Hash table high
+            HTH: u32,
+        }),
+        ///  Ethernet MAC hash table low register
+        MACHTLR: mmio.Mmio(packed struct(u32) {
+            ///  Hash table low
+            HTL: u32,
+        }),
+        ///  Ethernet MAC MII address register (ETH_MACMIIAR)
+        MACMIIAR: mmio.Mmio(packed struct(u32) {
+            ///  MII busy
+            MB: u1,
+            ///  MII write
+            MW: u1,
+            ///  Clock range
+            CR: u3,
+            reserved6: u1,
+            ///  MII register
+            MR: u5,
+            ///  PHY address
+            PA: u5,
+            padding: u16,
+        }),
+        ///  Ethernet MAC MII data register (ETH_MACMIIDR)
+        MACMIIDR: mmio.Mmio(packed struct(u32) {
+            ///  MII data
+            MD: u16,
+            padding: u16,
+        }),
+        ///  Ethernet MAC flow control register (ETH_MACFCR)
+        MACFCR: mmio.Mmio(packed struct(u32) {
+            ///  Flow control busy/back pressure activate
+            FCB_BPA: u1,
+            ///  Transmit flow control enable
+            TFCE: u1,
+            ///  Receive flow control enable
+            RFCE: u1,
+            ///  Unicast pause frame detect
+            UPFD: u1,
+            ///  Pause low threshold
+            PLT: u2,
+            reserved7: u1,
+            ///  Zero-quanta pause disable
+            ZQPD: u1,
+            reserved16: u8,
+            ///  Pass control frames
+            PT: u16,
+        }),
+        ///  Ethernet MAC VLAN tag register (ETH_MACVLANTR)
+        MACVLANTR: mmio.Mmio(packed struct(u32) {
+            ///  VLAN tag identifier (for receive frames)
+            VLANTI: u16,
+            ///  12-bit VLAN tag comparison
+            VLANTC: u1,
+            padding: u15,
+        }),
+        reserved40: [8]u8,
+        ///  Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)
+        MACRWUFFR: u32,
+        ///  Ethernet MAC PMT control and status register (ETH_MACPMTCSR)
+        MACPMTCSR: mmio.Mmio(packed struct(u32) {
+            ///  Power down
+            PD: u1,
+            ///  Magic Packet enable
+            MPE: u1,
+            ///  Wakeup frame enable
+            WFE: u1,
+            reserved5: u2,
+            ///  Magic packet received
+            MPR: u1,
+            ///  Wakeup frame received
+            WFR: u1,
+            reserved9: u2,
+            ///  Global unicast
+            GU: u1,
+            reserved31: u21,
+            ///  Wakeup frame filter register pointer reset
+            WFFRPR: u1,
+        }),
+        reserved56: [8]u8,
+        ///  Ethernet MAC interrupt status register (ETH_MACSR)
+        MACSR: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  PMT status
+            PMTS: u1,
+            ///  MMC status
+            MMCS: u1,
+            ///  MMC receive status
+            MMCRS: u1,
+            ///  MMC transmit status
+            MMCTS: u1,
+            reserved9: u2,
+            ///  Time stamp trigger status
+            TSTS: u1,
+            padding: u22,
+        }),
+        ///  Ethernet MAC interrupt mask register (ETH_MACIMR)
+        MACIMR: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  PMT interrupt mask
+            PMTIM: u1,
+            reserved9: u5,
+            ///  Time stamp trigger interrupt mask
+            TSTIM: u1,
+            padding: u22,
+        }),
+        ///  Ethernet MAC address 0 high register (ETH_MACA0HR)
+        MACA0HR: mmio.Mmio(packed struct(u32) {
+            ///  MAC address0 high
+            MACA0H: u16,
+            reserved31: u15,
+            ///  Always 1
+            MO: u1,
+        }),
+        ///  Ethernet MAC address 0 low register
+        MACA0LR: mmio.Mmio(packed struct(u32) {
+            ///  MAC address0 low
+            MACA0L: u32,
+        }),
+        ///  Ethernet MAC address 1 high register (ETH_MACA1HR)
+        MACA1HR: mmio.Mmio(packed struct(u32) {
+            ///  MAC address1 high
+            MACA1H: u16,
+            reserved24: u8,
+            ///  Mask byte control
+            MBC: u6,
+            ///  Source address
+            SA: u1,
+            ///  Address enable
+            AE: u1,
+        }),
+        ///  Ethernet MAC address1 low register
+        MACA1LR: mmio.Mmio(packed struct(u32) {
+            ///  MAC address1 low
+            MACA1L: u32,
+        }),
+        ///  Ethernet MAC address 2 high register (ETH_MACA2HR)
+        MACA2HR: mmio.Mmio(packed struct(u32) {
+            ///  Ethernet MAC address 2 high register
+            ETH_MACA2HR: u16,
+            reserved24: u8,
+            ///  Mask byte control
+            MBC: u6,
+            ///  Source address
+            SA: u1,
+            ///  Address enable
+            AE: u1,
+        }),
+        ///  Ethernet MAC address 2 low register
+        MACA2LR: mmio.Mmio(packed struct(u32) {
+            ///  MAC address2 low
+            MACA2L: u31,
+            padding: u1,
+        }),
+        ///  Ethernet MAC address 3 high register (ETH_MACA3HR)
+        MACA3HR: mmio.Mmio(packed struct(u32) {
+            ///  MAC address3 high
+            MACA3H: u16,
+            reserved24: u8,
+            ///  Mask byte control
+            MBC: u6,
+            ///  Source address
+            SA: u1,
+            ///  Address enable
+            AE: u1,
+        }),
+        ///  Ethernet MAC address 3 low register
+        MACA3LR: mmio.Mmio(packed struct(u32) {
+            ///  MAC address3 low
+            MBCA3L: u32,
+        }),
+    };
+
+    ///  Ethernet: MAC management counters
+    pub const ETHERNET_MMC = extern struct {
+        ///  Ethernet MMC control register (ETH_MMCCR)
+        MMCCR: mmio.Mmio(packed struct(u32) {
+            ///  Counter reset
+            CR: u1,
+            ///  Counter stop rollover
+            CSR: u1,
+            ///  Reset on read
+            ROR: u1,
+            reserved31: u28,
+            ///  MMC counter freeze
+            MCF: u1,
+        }),
+        ///  Ethernet MMC receive interrupt register (ETH_MMCRIR)
+        MMCRIR: mmio.Mmio(packed struct(u32) {
+            reserved5: u5,
+            ///  Received frames CRC error status
+            RFCES: u1,
+            ///  Received frames alignment error status
+            RFAES: u1,
+            reserved17: u10,
+            ///  Received Good Unicast Frames Status
+            RGUFS: u1,
+            padding: u14,
+        }),
+        ///  Ethernet MMC transmit interrupt register (ETH_MMCTIR)
+        MMCTIR: mmio.Mmio(packed struct(u32) {
+            reserved14: u14,
+            ///  Transmitted good frames single collision status
+            TGFSCS: u1,
+            ///  Transmitted good frames more single collision status
+            TGFMSCS: u1,
+            reserved21: u5,
+            ///  Transmitted good frames status
+            TGFS: u1,
+            padding: u10,
+        }),
+        ///  Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
+        MMCRIMR: mmio.Mmio(packed struct(u32) {
+            reserved5: u5,
+            ///  Received frame CRC error mask
+            RFCEM: u1,
+            ///  Received frames alignment error mask
+            RFAEM: u1,
+            reserved17: u10,
+            ///  Received good unicast frames mask
+            RGUFM: u1,
+            padding: u14,
+        }),
+        ///  Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
+        MMCTIMR: mmio.Mmio(packed struct(u32) {
+            reserved14: u14,
+            ///  Transmitted good frames single collision mask
+            TGFSCM: u1,
+            ///  Transmitted good frames more single collision mask
+            TGFMSCM: u1,
+            reserved21: u5,
+            ///  Transmitted good frames mask
+            TGFM: u1,
+            padding: u10,
+        }),
+        reserved76: [56]u8,
+        ///  Ethernet MMC transmitted good frames after a single collision counter
+        MMCTGFSCCR: mmio.Mmio(packed struct(u32) {
+            ///  Transmitted good frames after a single collision counter
+            TGFSCC: u32,
+        }),
+        ///  Ethernet MMC transmitted good frames after more than a single collision
+        MMCTGFMSCCR: mmio.Mmio(packed struct(u32) {
+            ///  Transmitted good frames after more than a single collision counter
+            TGFMSCC: u32,
+        }),
+        reserved104: [20]u8,
+        ///  Ethernet MMC transmitted good frames counter register
+        MMCTGFCR: mmio.Mmio(packed struct(u32) {
+            ///  Transmitted good frames counter
+            TGFC: u32,
+        }),
+        reserved148: [40]u8,
+        ///  Ethernet MMC received frames with CRC error counter register
+        MMCRFCECR: mmio.Mmio(packed struct(u32) {
+            ///  Received frames with CRC error counter
+            RFCFC: u32,
+        }),
+        ///  Ethernet MMC received frames with alignment error counter register
+        MMCRFAECR: mmio.Mmio(packed struct(u32) {
+            ///  Received frames with alignment error counter
+            RFAEC: u32,
+        }),
+        reserved196: [40]u8,
+        ///  MMC received good unicast frames counter register
+        MMCRGUFCR: mmio.Mmio(packed struct(u32) {
+            ///  Received good unicast frames counter
+            RGUFC: u32,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_PWRCLK = extern struct {
+        ///  OTG_FS power and clock gating control register
+        FS_PCGCCTL: mmio.Mmio(packed struct(u32) {
+            ///  Stop PHY clock
+            STPPCLK: u1,
+            ///  Gate HCLK
+            GATEHCLK: u1,
+            reserved4: u2,
+            ///  PHY Suspended
+            PHYSUSP: u1,
+            padding: u27,
+        }),
+    };
+
+    ///  General purpose timer
+    pub const TIM9 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            reserved7: u3,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  Master mode selection
+            MMS: u3,
+            padding: u25,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            padding: u24,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            reserved6: u3,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            padding: u25,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            reserved6: u3,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            reserved9: u2,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            padding: u21,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            reserved6: u3,
+            ///  Trigger generation
+            TG: u1,
+            padding: u25,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            reserved8: u1,
+            ///  Capture/Compare 2 selection
+            CC2S: u2,
+            ///  Output Compare 2 fast enable
+            OC2FE: u1,
+            ///  Output Compare 2 preload enable
+            OC2PE: u1,
+            ///  Output Compare 2 mode
+            OC2M: u3,
+            padding: u17,
+        }),
+        reserved32: [4]u8,
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved7: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            padding: u24,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 2 value
+            CCR2: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_HOST = extern struct {
+        ///  OTG_FS host configuration register (OTG_FS_HCFG)
+        FS_HCFG: mmio.Mmio(packed struct(u32) {
+            ///  FS/LS PHY clock select
+            FSLSPCS: u2,
+            ///  FS- and LS-only support
+            FSLSS: u1,
+            padding: u29,
+        }),
+        ///  OTG_FS Host frame interval register
+        HFIR: mmio.Mmio(packed struct(u32) {
+            ///  Frame interval
+            FRIVL: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
+        FS_HFNUM: mmio.Mmio(packed struct(u32) {
+            ///  Frame number
+            FRNUM: u16,
+            ///  Frame time remaining
+            FTREM: u16,
+        }),
+        reserved16: [4]u8,
+        ///  OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
+        FS_HPTXSTS: mmio.Mmio(packed struct(u32) {
+            ///  Periodic transmit data FIFO space available
+            PTXFSAVL: u16,
+            ///  Periodic transmit request queue space available
+            PTXQSAV: u8,
+            ///  Top of the periodic transmit request queue
+            PTXQTOP: u8,
+        }),
+        ///  OTG_FS Host all channels interrupt register
+        HAINT: mmio.Mmio(packed struct(u32) {
+            ///  Channel interrupts
+            HAINT: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS host all channels interrupt mask register
+        HAINTMSK: mmio.Mmio(packed struct(u32) {
+            ///  Channel interrupt mask
+            HAINTM: u16,
+            padding: u16,
+        }),
+        reserved64: [36]u8,
+        ///  OTG_FS host port control and status register (OTG_FS_HPRT)
+        FS_HPRT: mmio.Mmio(packed struct(u32) {
+            ///  Port connect status
+            PCSTS: u1,
+            ///  Port connect detected
+            PCDET: u1,
+            ///  Port enable
+            PENA: u1,
+            ///  Port enable/disable change
+            PENCHNG: u1,
+            ///  Port overcurrent active
+            POCA: u1,
+            ///  Port overcurrent change
+            POCCHNG: u1,
+            ///  Port resume
+            PRES: u1,
+            ///  Port suspend
+            PSUSP: u1,
+            ///  Port reset
+            PRST: u1,
+            reserved10: u1,
+            ///  Port line status
+            PLSTS: u2,
+            ///  Port power
+            PPWR: u1,
+            ///  Port test control
+            PTCTL: u4,
+            ///  Port speed
+            PSPD: u2,
+            padding: u13,
+        }),
+        reserved256: [188]u8,
+        ///  OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
+        FS_HCCHAR0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved264: [4]u8,
+        ///  OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
+        FS_HCINT0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
+        FS_HCINTMSK0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-0 transfer size register
+        FS_HCTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved288: [12]u8,
+        ///  OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)
+        FS_HCCHAR1: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved296: [4]u8,
+        ///  OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)
+        FS_HCINT1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)
+        FS_HCINTMSK1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-1 transfer size register
+        FS_HCTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved320: [12]u8,
+        ///  OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)
+        FS_HCCHAR2: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved328: [4]u8,
+        ///  OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)
+        FS_HCINT2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)
+        FS_HCINTMSK2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-2 transfer size register
+        FS_HCTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved352: [12]u8,
+        ///  OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)
+        FS_HCCHAR3: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved360: [4]u8,
+        ///  OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)
+        FS_HCINT3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)
+        FS_HCINTMSK3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-3 transfer size register
+        FS_HCTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved384: [12]u8,
+        ///  OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)
+        FS_HCCHAR4: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved392: [4]u8,
+        ///  OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)
+        FS_HCINT4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)
+        FS_HCINTMSK4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-x transfer size register
+        FS_HCTSIZ4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved416: [12]u8,
+        ///  OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)
+        FS_HCCHAR5: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved424: [4]u8,
+        ///  OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)
+        FS_HCINT5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)
+        FS_HCINTMSK5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-5 transfer size register
+        FS_HCTSIZ5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved448: [12]u8,
+        ///  OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)
+        FS_HCCHAR6: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved456: [4]u8,
+        ///  OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)
+        FS_HCINT6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)
+        FS_HCINTMSK6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-6 transfer size register
+        FS_HCTSIZ6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved480: [12]u8,
+        ///  OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)
+        FS_HCCHAR7: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved488: [4]u8,
+        ///  OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)
+        FS_HCINT7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)
+        FS_HCINTMSK7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-7 transfer size register
+        FS_HCTSIZ7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+    };
+
+    ///  General purpose timer
+    pub const TIM10 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            reserved7: u4,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  Master mode selection
+            MMS: u3,
+            padding: u25,
+        }),
+        reserved12: [4]u8,
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            padding: u30,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            reserved9: u7,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            padding: u22,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            padding: u30,
+        }),
+        ///  capture/compare mode register (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            reserved3: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            padding: u25,
+        }),
+        reserved32: [4]u8,
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            padding: u28,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_GLOBAL = extern struct {
+        ///  OTG_FS control and status register (OTG_FS_GOTGCTL)
+        FS_GOTGCTL: mmio.Mmio(packed struct(u32) {
+            ///  Session request success
+            SRQSCS: u1,
+            ///  Session request
+            SRQ: u1,
+            reserved8: u6,
+            ///  Host negotiation success
+            HNGSCS: u1,
+            ///  HNP request
+            HNPRQ: u1,
+            ///  Host set HNP enable
+            HSHNPEN: u1,
+            ///  Device HNP enabled
+            DHNPEN: u1,
+            reserved16: u4,
+            ///  Connector ID status
+            CIDSTS: u1,
+            ///  Long/short debounce time
+            DBCT: u1,
+            ///  A-session valid
+            ASVLD: u1,
+            ///  B-session valid
+            BSVLD: u1,
+            padding: u12,
+        }),
+        ///  OTG_FS interrupt register (OTG_FS_GOTGINT)
+        FS_GOTGINT: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Session end detected
+            SEDET: u1,
+            reserved8: u5,
+            ///  Session request success status change
+            SRSSCHG: u1,
+            ///  Host negotiation success status change
+            HNSSCHG: u1,
+            reserved17: u7,
+            ///  Host negotiation detected
+            HNGDET: u1,
+            ///  A-device timeout change
+            ADTOCHG: u1,
+            ///  Debounce done
+            DBCDNE: u1,
+            padding: u12,
+        }),
+        ///  OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
+        FS_GAHBCFG: mmio.Mmio(packed struct(u32) {
+            ///  Global interrupt mask
+            GINT: u1,
+            reserved7: u6,
+            ///  TxFIFO empty level
+            TXFELVL: u1,
+            ///  Periodic TxFIFO empty level
+            PTXFELVL: u1,
+            padding: u23,
+        }),
+        ///  OTG_FS USB configuration register (OTG_FS_GUSBCFG)
+        FS_GUSBCFG: mmio.Mmio(packed struct(u32) {
+            ///  FS timeout calibration
+            TOCAL: u3,
+            reserved6: u3,
+            ///  Full Speed serial transceiver select
+            PHYSEL: u1,
+            reserved8: u1,
+            ///  SRP-capable
+            SRPCAP: u1,
+            ///  HNP-capable
+            HNPCAP: u1,
+            ///  USB turnaround time
+            TRDT: u4,
+            reserved29: u15,
+            ///  Force host mode
+            FHMOD: u1,
+            ///  Force device mode
+            FDMOD: u1,
+            ///  Corrupt Tx packet
+            CTXPKT: u1,
+        }),
+        ///  OTG_FS reset register (OTG_FS_GRSTCTL)
+        FS_GRSTCTL: mmio.Mmio(packed struct(u32) {
+            ///  Core soft reset
+            CSRST: u1,
+            ///  HCLK soft reset
+            HSRST: u1,
+            ///  Host frame counter reset
+            FCRST: u1,
+            reserved4: u1,
+            ///  RxFIFO flush
+            RXFFLSH: u1,
+            ///  TxFIFO flush
+            TXFFLSH: u1,
+            ///  TxFIFO number
+            TXFNUM: u5,
+            reserved31: u20,
+            ///  AHB master idle
+            AHBIDL: u1,
+        }),
+        ///  OTG_FS core interrupt register (OTG_FS_GINTSTS)
+        FS_GINTSTS: mmio.Mmio(packed struct(u32) {
+            ///  Current mode of operation
+            CMOD: u1,
+            ///  Mode mismatch interrupt
+            MMIS: u1,
+            ///  OTG interrupt
+            OTGINT: u1,
+            ///  Start of frame
+            SOF: u1,
+            ///  RxFIFO non-empty
+            RXFLVL: u1,
+            ///  Non-periodic TxFIFO empty
+            NPTXFE: u1,
+            ///  Global IN non-periodic NAK effective
+            GINAKEFF: u1,
+            ///  Global OUT NAK effective
+            GOUTNAKEFF: u1,
+            reserved10: u2,
+            ///  Early suspend
+            ESUSP: u1,
+            ///  USB suspend
+            USBSUSP: u1,
+            ///  USB reset
+            USBRST: u1,
+            ///  Enumeration done
+            ENUMDNE: u1,
+            ///  Isochronous OUT packet dropped interrupt
+            ISOODRP: u1,
+            ///  End of periodic frame interrupt
+            EOPF: u1,
+            reserved18: u2,
+            ///  IN endpoint interrupt
+            IEPINT: u1,
+            ///  OUT endpoint interrupt
+            OEPINT: u1,
+            ///  Incomplete isochronous IN transfer
+            IISOIXFR: u1,
+            ///  Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)
+            IPXFR_INCOMPISOOUT: u1,
+            reserved24: u2,
+            ///  Host port interrupt
+            HPRTINT: u1,
+            ///  Host channels interrupt
+            HCINT: u1,
+            ///  Periodic TxFIFO empty
+            PTXFE: u1,
+            reserved28: u1,
+            ///  Connector ID status change
+            CIDSCHG: u1,
+            ///  Disconnect detected interrupt
+            DISCINT: u1,
+            ///  Session request/new session detected interrupt
+            SRQINT: u1,
+            ///  Resume/remote wakeup detected interrupt
+            WKUPINT: u1,
+        }),
+        ///  OTG_FS interrupt mask register (OTG_FS_GINTMSK)
+        FS_GINTMSK: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Mode mismatch interrupt mask
+            MMISM: u1,
+            ///  OTG interrupt mask
+            OTGINT: u1,
+            ///  Start of frame mask
+            SOFM: u1,
+            ///  Receive FIFO non-empty mask
+            RXFLVLM: u1,
+            ///  Non-periodic TxFIFO empty mask
+            NPTXFEM: u1,
+            ///  Global non-periodic IN NAK effective mask
+            GINAKEFFM: u1,
+            ///  Global OUT NAK effective mask
+            GONAKEFFM: u1,
+            reserved10: u2,
+            ///  Early suspend mask
+            ESUSPM: u1,
+            ///  USB suspend mask
+            USBSUSPM: u1,
+            ///  USB reset mask
+            USBRST: u1,
+            ///  Enumeration done mask
+            ENUMDNEM: u1,
+            ///  Isochronous OUT packet dropped interrupt mask
+            ISOODRPM: u1,
+            ///  End of periodic frame interrupt mask
+            EOPFM: u1,
+            reserved17: u1,
+            ///  Endpoint mismatch interrupt mask
+            EPMISM: u1,
+            ///  IN endpoints interrupt mask
+            IEPINT: u1,
+            ///  OUT endpoints interrupt mask
+            OEPINT: u1,
+            ///  Incomplete isochronous IN transfer mask
+            IISOIXFRM: u1,
+            ///  Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)
+            IPXFRM_IISOOXFRM: u1,
+            reserved24: u2,
+            ///  Host port interrupt mask
+            PRTIM: u1,
+            ///  Host channels interrupt mask
+            HCIM: u1,
+            ///  Periodic TxFIFO empty mask
+            PTXFEM: u1,
+            reserved28: u1,
+            ///  Connector ID status change mask
+            CIDSCHGM: u1,
+            ///  Disconnect detected interrupt mask
+            DISCINT: u1,
+            ///  Session request/new session detected interrupt mask
+            SRQIM: u1,
+            ///  Resume/remote wakeup detected interrupt mask
+            WUIM: u1,
+        }),
+        ///  OTG_FS Receive status debug read(Device mode)
+        FS_GRXSTSR_Device: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Byte count
+            BCNT: u11,
+            ///  Data PID
+            DPID: u2,
+            ///  Packet status
+            PKTSTS: u4,
+            ///  Frame number
+            FRMNUM: u4,
+            padding: u7,
+        }),
+        reserved36: [4]u8,
+        ///  OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
+        FS_GRXFSIZ: mmio.Mmio(packed struct(u32) {
+            ///  RxFIFO depth
+            RXFD: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS non-periodic transmit FIFO size register (Device mode)
+        FS_GNPTXFSIZ_Device: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint 0 transmit RAM start address
+            TX0FSA: u16,
+            ///  Endpoint 0 TxFIFO depth
+            TX0FD: u16,
+        }),
+        ///  OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)
+        FS_GNPTXSTS: mmio.Mmio(packed struct(u32) {
+            ///  Non-periodic TxFIFO space available
+            NPTXFSAV: u16,
+            ///  Non-periodic transmit request queue space available
+            NPTQXSAV: u8,
+            ///  Top of the non-periodic transmit request queue
+            NPTXQTOP: u7,
+            padding: u1,
+        }),
+        reserved56: [8]u8,
+        ///  OTG_FS general core configuration register (OTG_FS_GCCFG)
+        FS_GCCFG: mmio.Mmio(packed struct(u32) {
+            reserved16: u16,
+            ///  Power down
+            PWRDWN: u1,
+            reserved18: u1,
+            ///  Enable the VBUS sensing device
+            VBUSASEN: u1,
+            ///  Enable the VBUS sensing device
+            VBUSBSEN: u1,
+            ///  SOF output enable
+            SOFOUTEN: u1,
+            padding: u11,
+        }),
+        ///  core ID register
+        FS_CID: mmio.Mmio(packed struct(u32) {
+            ///  Product ID field
+            PRODUCT_ID: u32,
+        }),
+        reserved256: [192]u8,
+        ///  OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
+        FS_HPTXFSIZ: mmio.Mmio(packed struct(u32) {
+            ///  Host periodic TxFIFO start address
+            PTXSA: u16,
+            ///  Host periodic TxFIFO depth
+            PTXFSIZ: u16,
+        }),
+        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)
+        FS_DIEPTXF1: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFO2 transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)
+        FS_DIEPTXF2: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFO3 transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)
+        FS_DIEPTXF3: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFO4 transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_DEVICE = extern struct {
+        ///  OTG_FS device configuration register (OTG_FS_DCFG)
+        FS_DCFG: mmio.Mmio(packed struct(u32) {
+            ///  Device speed
+            DSPD: u2,
+            ///  Non-zero-length status OUT handshake
+            NZLSOHSK: u1,
+            reserved4: u1,
+            ///  Device address
+            DAD: u7,
+            ///  Periodic frame interval
+            PFIVL: u2,
+            padding: u19,
+        }),
+        ///  OTG_FS device control register (OTG_FS_DCTL)
+        FS_DCTL: mmio.Mmio(packed struct(u32) {
+            ///  Remote wakeup signaling
+            RWUSIG: u1,
+            ///  Soft disconnect
+            SDIS: u1,
+            ///  Global IN NAK status
+            GINSTS: u1,
+            ///  Global OUT NAK status
+            GONSTS: u1,
+            ///  Test control
+            TCTL: u3,
+            ///  Set global IN NAK
+            SGINAK: u1,
+            ///  Clear global IN NAK
+            CGINAK: u1,
+            ///  Set global OUT NAK
+            SGONAK: u1,
+            ///  Clear global OUT NAK
+            CGONAK: u1,
+            ///  Power-on programming done
+            POPRGDNE: u1,
+            padding: u20,
+        }),
+        ///  OTG_FS device status register (OTG_FS_DSTS)
+        FS_DSTS: mmio.Mmio(packed struct(u32) {
+            ///  Suspend status
+            SUSPSTS: u1,
+            ///  Enumerated speed
+            ENUMSPD: u2,
+            ///  Erratic error
+            EERR: u1,
+            reserved8: u4,
+            ///  Frame number of the received SOF
+            FNSOF: u14,
+            padding: u10,
+        }),
+        reserved16: [4]u8,
+        ///  OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
+        FS_DIEPMSK: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  Timeout condition mask (Non-isochronous endpoints)
+            TOM: u1,
+            ///  IN token received when TxFIFO empty mask
+            ITTXFEMSK: u1,
+            ///  IN token received with EP mismatch mask
+            INEPNMM: u1,
+            ///  IN endpoint NAK effective mask
+            INEPNEM: u1,
+            padding: u25,
+        }),
+        ///  OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
+        FS_DOEPMSK: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  SETUP phase done mask
+            STUPM: u1,
+            ///  OUT token received when endpoint disabled mask
+            OTEPDM: u1,
+            padding: u27,
+        }),
+        ///  OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
+        FS_DAINT: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint interrupt bits
+            IEPINT: u16,
+            ///  OUT endpoint interrupt bits
+            OEPINT: u16,
+        }),
+        ///  OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
+        FS_DAINTMSK: mmio.Mmio(packed struct(u32) {
+            ///  IN EP interrupt mask bits
+            IEPM: u16,
+            ///  OUT endpoint interrupt bits
+            OEPINT: u16,
+        }),
+        reserved40: [8]u8,
+        ///  OTG_FS device VBUS discharge time register
+        DVBUSDIS: mmio.Mmio(packed struct(u32) {
+            ///  Device VBUS discharge time
+            VBUSDT: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS device VBUS pulsing time register
+        DVBUSPULSE: mmio.Mmio(packed struct(u32) {
+            ///  Device VBUS pulsing time
+            DVBUSP: u12,
+            padding: u20,
+        }),
+        reserved52: [4]u8,
+        ///  OTG_FS device IN endpoint FIFO empty interrupt mask register
+        DIEPEMPMSK: mmio.Mmio(packed struct(u32) {
+            ///  IN EP Tx FIFO empty interrupt mask bits
+            INEPTXFEM: u16,
+            padding: u16,
+        }),
+        reserved256: [200]u8,
+        ///  OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
+        FS_DIEPCTL0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u2,
+            reserved15: u13,
+            ///  USB active endpoint
+            USBAEP: u1,
+            reserved17: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            STALL: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            reserved30: u2,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved264: [4]u8,
+        ///  device endpoint-x interrupt register
+        DIEPINT0: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved272: [4]u8,
+        ///  device endpoint-0 transfer size register
+        DIEPTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u7,
+            reserved19: u12,
+            ///  Packet count
+            PKTCNT: u2,
+            padding: u11,
+        }),
+        reserved280: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS0: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved288: [4]u8,
+        ///  OTG device endpoint-1 control register
+        DIEPCTL1: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            reserved21: u1,
+            ///  Stall
+            Stall: u1,
+            ///  TXFNUM
+            TXFNUM: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM/SD1PID
+            SODDFRM_SD1PID: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved296: [4]u8,
+        ///  device endpoint-1 interrupt register
+        DIEPINT1: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved304: [4]u8,
+        ///  device endpoint-1 transfer size register
+        DIEPTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        reserved312: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS1: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved320: [4]u8,
+        ///  OTG device endpoint-2 control register
+        DIEPCTL2: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            reserved21: u1,
+            ///  Stall
+            Stall: u1,
+            ///  TXFNUM
+            TXFNUM: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved328: [4]u8,
+        ///  device endpoint-2 interrupt register
+        DIEPINT2: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved336: [4]u8,
+        ///  device endpoint-2 transfer size register
+        DIEPTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        reserved344: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS2: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved352: [4]u8,
+        ///  OTG device endpoint-3 control register
+        DIEPCTL3: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            reserved21: u1,
+            ///  Stall
+            Stall: u1,
+            ///  TXFNUM
+            TXFNUM: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved360: [4]u8,
+        ///  device endpoint-3 interrupt register
+        DIEPINT3: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved368: [4]u8,
+        ///  device endpoint-3 transfer size register
+        DIEPTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        reserved376: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS3: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved768: [388]u8,
+        ///  device endpoint-0 control register
+        DOEPCTL0: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u2,
+            reserved15: u13,
+            ///  USBAEP
+            USBAEP: u1,
+            reserved17: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            reserved30: u2,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved776: [4]u8,
+        ///  device endpoint-0 interrupt register
+        DOEPINT0: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved784: [4]u8,
+        ///  device OUT endpoint-0 transfer size register
+        DOEPTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u7,
+            reserved19: u12,
+            ///  Packet count
+            PKTCNT: u1,
+            reserved29: u9,
+            ///  SETUP packet count
+            STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved800: [12]u8,
+        ///  device endpoint-1 control register
+        DOEPCTL1: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved808: [4]u8,
+        ///  device endpoint-1 interrupt register
+        DOEPINT1: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved816: [4]u8,
+        ///  device OUT endpoint-1 transfer size register
+        DOEPTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved832: [12]u8,
+        ///  device endpoint-2 control register
+        DOEPCTL2: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved840: [4]u8,
+        ///  device endpoint-2 interrupt register
+        DOEPINT2: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved848: [4]u8,
+        ///  device OUT endpoint-2 transfer size register
+        DOEPTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved864: [12]u8,
+        ///  device endpoint-3 control register
+        DOEPCTL3: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved872: [4]u8,
+        ///  device endpoint-3 interrupt register
+        DOEPINT3: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved880: [4]u8,
+        ///  device OUT endpoint-3 transfer size register
+        DOEPTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+    };
+
+    ///  Universal serial bus full-speed device interface
+    pub const USB = extern struct {
+        ///  endpoint 0 register
+        EP0R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 1 register
+        EP1R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 2 register
+        EP2R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 3 register
+        EP3R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 4 register
+        EP4R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 5 register
+        EP5R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 6 register
+        EP6R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 7 register
+        EP7R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        reserved64: [32]u8,
+        ///  control register
+        CNTR: mmio.Mmio(packed struct(u32) {
+            ///  Force USB Reset
+            FRES: u1,
+            ///  Power down
+            PDWN: u1,
+            ///  Low-power mode
+            LPMODE: u1,
+            ///  Force suspend
+            FSUSP: u1,
+            ///  Resume request
+            RESUME: u1,
+            reserved8: u3,
+            ///  Expected start of frame interrupt mask
+            ESOFM: u1,
+            ///  Start of frame interrupt mask
+            SOFM: u1,
+            ///  USB reset interrupt mask
+            RESETM: u1,
+            ///  Suspend mode interrupt mask
+            SUSPM: u1,
+            ///  Wakeup interrupt mask
+            WKUPM: u1,
+            ///  Error interrupt mask
+            ERRM: u1,
+            ///  Packet memory area over / underrun interrupt mask
+            PMAOVRM: u1,
+            ///  Correct transfer interrupt mask
+            CTRM: u1,
+            padding: u16,
+        }),
+        ///  interrupt status register
+        ISTR: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint Identifier
+            EP_ID: u4,
+            ///  Direction of transaction
+            DIR: u1,
+            reserved8: u3,
+            ///  Expected start frame
+            ESOF: u1,
+            ///  start of frame
+            SOF: u1,
+            ///  reset request
+            RESET: u1,
+            ///  Suspend mode request
+            SUSP: u1,
+            ///  Wakeup
+            WKUP: u1,
+            ///  Error
+            ERR: u1,
+            ///  Packet memory area over / underrun
+            PMAOVR: u1,
+            ///  Correct transfer
+            CTR: u1,
+            padding: u16,
+        }),
+        ///  frame number register
+        FNR: mmio.Mmio(packed struct(u32) {
+            ///  Frame number
+            FN: u11,
+            ///  Lost SOF
+            LSOF: u2,
+            ///  Locked
+            LCK: u1,
+            ///  Receive data - line status
+            RXDM: u1,
+            ///  Receive data + line status
+            RXDP: u1,
+            padding: u16,
+        }),
+        ///  device address
+        DADDR: mmio.Mmio(packed struct(u32) {
+            ///  Device address
+            ADD: u7,
+            ///  Enable function
+            EF: u1,
+            padding: u24,
+        }),
+        ///  Buffer table address
+        BTABLE: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Buffer table
+            BTABLE: u13,
+            padding: u16,
+        }),
+    };
+
+    ///  Basic timer
+    pub const TIM6 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            reserved7: u3,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            padding: u24,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  Master mode selection
+            MMS: u3,
+            padding: u25,
+        }),
+        reserved12: [4]u8,
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            reserved8: u7,
+            ///  Update DMA request enable
+            UDE: u1,
+            padding: u23,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            padding: u31,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            padding: u31,
+        }),
+        reserved36: [12]u8,
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  Low counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Low Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  FLASH
+    pub const FLASH = extern struct {
+        ///  Flash access control register
+        ACR: mmio.Mmio(packed struct(u32) {
+            ///  Latency
+            LATENCY: u3,
+            ///  Flash half cycle access enable
+            HLFCYA: u1,
+            ///  Prefetch buffer enable
+            PRFTBE: u1,
+            ///  Prefetch buffer status
+            PRFTBS: u1,
+            padding: u26,
+        }),
+        ///  Flash key register
+        KEYR: mmio.Mmio(packed struct(u32) {
+            ///  FPEC key
+            KEY: u32,
+        }),
+        ///  Flash option key register
+        OPTKEYR: mmio.Mmio(packed struct(u32) {
+            ///  Option byte key
+            OPTKEY: u32,
+        }),
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Busy
+            BSY: u1,
+            reserved2: u1,
+            ///  Programming error
+            PGERR: u1,
+            reserved4: u1,
+            ///  Write protection error
+            WRPRTERR: u1,
+            ///  End of operation
+            EOP: u1,
+            padding: u26,
+        }),
+        ///  Control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Programming
+            PG: u1,
+            ///  Page Erase
+            PER: u1,
+            ///  Mass Erase
+            MER: u1,
+            reserved4: u1,
+            ///  Option byte programming
+            OPTPG: u1,
+            ///  Option byte erase
+            OPTER: u1,
+            ///  Start
+            STRT: u1,
+            ///  Lock
+            LOCK: u1,
+            reserved9: u1,
+            ///  Option bytes write enable
+            OPTWRE: u1,
+            ///  Error interrupt enable
+            ERRIE: u1,
+            reserved12: u1,
+            ///  End of operation interrupt enable
+            EOPIE: u1,
+            padding: u19,
+        }),
+        ///  Flash address register
+        AR: mmio.Mmio(packed struct(u32) {
+            ///  Flash Address
+            FAR: u32,
+        }),
+        reserved28: [4]u8,
+        ///  Option byte register
+        OBR: mmio.Mmio(packed struct(u32) {
+            ///  Option byte error
+            OPTERR: u1,
+            ///  Read protection
+            RDPRT: u1,
+            ///  WDG_SW
+            WDG_SW: u1,
+            ///  nRST_STOP
+            nRST_STOP: u1,
+            ///  nRST_STDBY
+            nRST_STDBY: u1,
+            reserved10: u5,
+            ///  Data0
+            Data0: u8,
+            ///  Data1
+            Data1: u8,
+            padding: u6,
+        }),
+        ///  Write protection register
+        WRPR: mmio.Mmio(packed struct(u32) {
+            ///  Write protect
+            WRP: u32,
+        }),
+    };
+
+    ///  Inter integrated circuit
+    pub const I2C1 = extern struct {
+        ///  Control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral enable
+            PE: u1,
+            ///  SMBus mode
+            SMBUS: u1,
+            reserved3: u1,
+            ///  SMBus type
+            SMBTYPE: u1,
+            ///  ARP enable
+            ENARP: u1,
+            ///  PEC enable
+            ENPEC: u1,
+            ///  General call enable
+            ENGC: u1,
+            ///  Clock stretching disable (Slave mode)
+            NOSTRETCH: u1,
+            ///  Start generation
+            START: u1,
+            ///  Stop generation
+            STOP: u1,
+            ///  Acknowledge enable
+            ACK: u1,
+            ///  Acknowledge/PEC Position (for data reception)
+            POS: u1,
+            ///  Packet error checking
+            PEC: u1,
+            ///  SMBus alert
+            ALERT: u1,
+            reserved15: u1,
+            ///  Software reset
+            SWRST: u1,
+            padding: u16,
+        }),
+        ///  Control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral clock frequency
+            FREQ: u6,
+            reserved8: u2,
+            ///  Error interrupt enable
+            ITERREN: u1,
+            ///  Event interrupt enable
+            ITEVTEN: u1,
+            ///  Buffer interrupt enable
+            ITBUFEN: u1,
+            ///  DMA requests enable
+            DMAEN: u1,
+            ///  DMA last transfer
+            LAST: u1,
+            padding: u19,
+        }),
+        ///  Own address register 1
+        OAR1: mmio.Mmio(packed struct(u32) {
+            ///  Interface address
+            ADD0: u1,
+            ///  Interface address
+            ADD7: u7,
+            ///  Interface address
+            ADD10: u2,
+            reserved15: u5,
+            ///  Addressing mode (slave mode)
+            ADDMODE: u1,
+            padding: u16,
+        }),
+        ///  Own address register 2
+        OAR2: mmio.Mmio(packed struct(u32) {
+            ///  Dual addressing mode enable
+            ENDUAL: u1,
+            ///  Interface address
+            ADD2: u7,
+            padding: u24,
+        }),
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  8-bit data register
+            DR: u8,
+            padding: u24,
+        }),
+        ///  Status register 1
+        SR1: mmio.Mmio(packed struct(u32) {
+            ///  Start bit (Master mode)
+            SB: u1,
+            ///  Address sent (master mode)/matched (slave mode)
+            ADDR: u1,
+            ///  Byte transfer finished
+            BTF: u1,
+            ///  10-bit header sent (Master mode)
+            ADD10: u1,
+            ///  Stop detection (slave mode)
+            STOPF: u1,
+            reserved6: u1,
+            ///  Data register not empty (receivers)
+            RxNE: u1,
+            ///  Data register empty (transmitters)
+            TxE: u1,
+            ///  Bus error
+            BERR: u1,
+            ///  Arbitration lost (master mode)
+            ARLO: u1,
+            ///  Acknowledge failure
+            AF: u1,
+            ///  Overrun/Underrun
+            OVR: u1,
+            ///  PEC Error in reception
+            PECERR: u1,
+            reserved14: u1,
+            ///  Timeout or Tlow error
+            TIMEOUT: u1,
+            ///  SMBus alert
+            SMBALERT: u1,
+            padding: u16,
+        }),
+        ///  Status register 2
+        SR2: mmio.Mmio(packed struct(u32) {
+            ///  Master/slave
+            MSL: u1,
+            ///  Bus busy
+            BUSY: u1,
+            ///  Transmitter/receiver
+            TRA: u1,
+            reserved4: u1,
+            ///  General call address (Slave mode)
+            GENCALL: u1,
+            ///  SMBus device default address (Slave mode)
+            SMBDEFAULT: u1,
+            ///  SMBus host header (Slave mode)
+            SMBHOST: u1,
+            ///  Dual flag (Slave mode)
+            DUALF: u1,
+            ///  acket error checking register
+            PEC: u8,
+            padding: u16,
+        }),
+        ///  Clock control register
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Clock control register in Fast/Standard mode (Master mode)
+            CCR: u12,
+            reserved14: u2,
+            ///  Fast mode duty cycle
+            DUTY: u1,
+            ///  I2C master mode selection
+            F_S: u1,
+            padding: u16,
+        }),
+        ///  TRISE register
+        TRISE: mmio.Mmio(packed struct(u32) {
+            ///  Maximum rise time in Fast/Standard mode (Master mode)
+            TRISE: u6,
+            padding: u26,
+        }),
+    };
+
+    ///  CRC calculation unit
+    pub const CRC = extern struct {
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data Register
+            DR: u32,
+        }),
+        ///  Independent Data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Independent Data register
+            IDR: u8,
+            padding: u24,
+        }),
+        ///  Control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Reset bit
+            RESET: u1,
+            padding: u31,
+        }),
+    };
+
+    ///  Serial peripheral interface
+    pub const SPI1 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Clock phase
+            CPHA: u1,
+            ///  Clock polarity
+            CPOL: u1,
+            ///  Master selection
+            MSTR: u1,
+            ///  Baud rate control
+            BR: u3,
+            ///  SPI enable
+            SPE: u1,
+            ///  Frame format
+            LSBFIRST: u1,
+            ///  Internal slave select
+            SSI: u1,
+            ///  Software slave management
+            SSM: u1,
+            ///  Receive only
+            RXONLY: u1,
+            ///  Data frame format
+            DFF: u1,
+            ///  CRC transfer next
+            CRCNEXT: u1,
+            ///  Hardware CRC calculation enable
+            CRCEN: u1,
+            ///  Output enable in bidirectional mode
+            BIDIOE: u1,
+            ///  Bidirectional data mode enable
+            BIDIMODE: u1,
+            padding: u16,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Rx buffer DMA enable
+            RXDMAEN: u1,
+            ///  Tx buffer DMA enable
+            TXDMAEN: u1,
+            ///  SS output enable
+            SSOE: u1,
+            reserved5: u2,
+            ///  Error interrupt enable
+            ERRIE: u1,
+            ///  RX buffer not empty interrupt enable
+            RXNEIE: u1,
+            ///  Tx buffer empty interrupt enable
+            TXEIE: u1,
+            padding: u24,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Receive buffer not empty
+            RXNE: u1,
+            ///  Transmit buffer empty
+            TXE: u1,
+            ///  Channel side
+            CHSIDE: u1,
+            ///  Underrun flag
+            UDR: u1,
+            ///  CRC error flag
+            CRCERR: u1,
+            ///  Mode fault
+            MODF: u1,
+            ///  Overrun flag
+            OVR: u1,
+            ///  Busy flag
+            BSY: u1,
+            padding: u24,
+        }),
+        ///  data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data register
+            DR: u16,
+            padding: u16,
+        }),
+        ///  CRC polynomial register
+        CRCPR: mmio.Mmio(packed struct(u32) {
+            ///  CRC polynomial register
+            CRCPOLY: u16,
+            padding: u16,
+        }),
+        ///  RX CRC register
+        RXCRCR: mmio.Mmio(packed struct(u32) {
+            ///  Rx CRC register
+            RxCRC: u16,
+            padding: u16,
+        }),
+        ///  TX CRC register
+        TXCRCR: mmio.Mmio(packed struct(u32) {
+            ///  Tx CRC register
+            TxCRC: u16,
+            padding: u16,
+        }),
+        ///  I2S configuration register
+        I2SCFGR: mmio.Mmio(packed struct(u32) {
+            ///  Channel length (number of bits per audio channel)
+            CHLEN: u1,
+            ///  Data length to be transferred
+            DATLEN: u2,
+            ///  Steady state clock polarity
+            CKPOL: u1,
+            ///  I2S standard selection
+            I2SSTD: u2,
+            reserved7: u1,
+            ///  PCM frame synchronization
+            PCMSYNC: u1,
+            ///  I2S configuration mode
+            I2SCFG: u2,
+            ///  I2S Enable
+            I2SE: u1,
+            ///  I2S mode selection
+            I2SMOD: u1,
+            padding: u20,
+        }),
+        ///  I2S prescaler register
+        I2SPR: mmio.Mmio(packed struct(u32) {
+            ///  I2S Linear prescaler
+            I2SDIV: u8,
+            ///  Odd factor for the prescaler
+            ODD: u1,
+            ///  Master clock output enable
+            MCKOE: u1,
+            padding: u22,
+        }),
+    };
+
+    ///  Universal asynchronous receiver transmitter
+    pub const UART5 = extern struct {
+        ///  UART4_SR
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  PE
+            PE: u1,
+            ///  FE
+            FE: u1,
+            ///  NE
+            NE: u1,
+            ///  ORE
+            ORE: u1,
+            ///  IDLE
+            IDLE: u1,
+            ///  RXNE
+            RXNE: u1,
+            ///  TC
+            TC: u1,
+            ///  TXE
+            TXE: u1,
+            ///  LBD
+            LBD: u1,
+            padding: u23,
+        }),
+        ///  UART4_DR
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  DR
+            DR: u9,
+            padding: u23,
+        }),
+        ///  UART4_BRR
+        BRR: mmio.Mmio(packed struct(u32) {
+            ///  DIV_Fraction
+            DIV_Fraction: u4,
+            ///  DIV_Mantissa
+            DIV_Mantissa: u12,
+            padding: u16,
+        }),
+        ///  UART4_CR1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  SBK
+            SBK: u1,
+            ///  RWU
+            RWU: u1,
+            ///  RE
+            RE: u1,
+            ///  TE
+            TE: u1,
+            ///  IDLEIE
+            IDLEIE: u1,
+            ///  RXNEIE
+            RXNEIE: u1,
+            ///  TCIE
+            TCIE: u1,
+            ///  TXEIE
+            TXEIE: u1,
+            ///  PEIE
+            PEIE: u1,
+            ///  PS
+            PS: u1,
+            ///  PCE
+            PCE: u1,
+            ///  WAKE
+            WAKE: u1,
+            ///  M
+            M: u1,
+            ///  UE
+            UE: u1,
+            padding: u18,
+        }),
+        ///  UART4_CR2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  ADD
+            ADD: u4,
+            reserved5: u1,
+            ///  LBDL
+            LBDL: u1,
+            ///  LBDIE
+            LBDIE: u1,
+            reserved12: u5,
+            ///  STOP
+            STOP: u2,
+            ///  LINEN
+            LINEN: u1,
+            padding: u17,
+        }),
+        ///  UART4_CR3
+        CR3: mmio.Mmio(packed struct(u32) {
+            ///  Error interrupt enable
+            EIE: u1,
+            ///  IrDA mode enable
+            IREN: u1,
+            ///  IrDA low-power
+            IRLP: u1,
+            ///  Half-duplex selection
+            HDSEL: u1,
+            reserved7: u3,
+            ///  DMA enable transmitter
+            DMAT: u1,
+            padding: u24,
+        }),
+    };
+
+    ///  Universal asynchronous receiver transmitter
+    pub const UART4 = extern struct {
+        ///  UART4_SR
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Parity error
+            PE: u1,
+            ///  Framing error
+            FE: u1,
+            ///  Noise error flag
+            NE: u1,
+            ///  Overrun error
+            ORE: u1,
+            ///  IDLE line detected
+            IDLE: u1,
+            ///  Read data register not empty
+            RXNE: u1,
+            ///  Transmission complete
+            TC: u1,
+            ///  Transmit data register empty
+            TXE: u1,
+            ///  LIN break detection flag
+            LBD: u1,
+            padding: u23,
+        }),
+        ///  UART4_DR
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  DR
+            DR: u9,
+            padding: u23,
+        }),
+        ///  UART4_BRR
+        BRR: mmio.Mmio(packed struct(u32) {
+            ///  DIV_Fraction
+            DIV_Fraction: u4,
+            ///  DIV_Mantissa
+            DIV_Mantissa: u12,
+            padding: u16,
+        }),
+        ///  UART4_CR1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Send break
+            SBK: u1,
+            ///  Receiver wakeup
+            RWU: u1,
+            ///  Receiver enable
+            RE: u1,
+            ///  Transmitter enable
+            TE: u1,
+            ///  IDLE interrupt enable
+            IDLEIE: u1,
+            ///  RXNE interrupt enable
+            RXNEIE: u1,
+            ///  Transmission complete interrupt enable
+            TCIE: u1,
+            ///  TXE interrupt enable
+            TXEIE: u1,
+            ///  PE interrupt enable
+            PEIE: u1,
+            ///  Parity selection
+            PS: u1,
+            ///  Parity control enable
+            PCE: u1,
+            ///  Wakeup method
+            WAKE: u1,
+            ///  Word length
+            M: u1,
+            ///  USART enable
+            UE: u1,
+            padding: u18,
+        }),
+        ///  UART4_CR2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Address of the USART node
+            ADD: u4,
+            reserved5: u1,
+            ///  lin break detection length
+            LBDL: u1,
+            ///  LIN break detection interrupt enable
+            LBDIE: u1,
+            reserved12: u5,
+            ///  STOP bits
+            STOP: u2,
+            ///  LIN mode enable
+            LINEN: u1,
+            padding: u17,
+        }),
+        ///  UART4_CR3
+        CR3: mmio.Mmio(packed struct(u32) {
+            ///  Error interrupt enable
+            EIE: u1,
+            ///  IrDA mode enable
+            IREN: u1,
+            ///  IrDA low-power
+            IRLP: u1,
+            ///  Half-duplex selection
+            HDSEL: u1,
+            reserved6: u2,
+            ///  DMA enable receiver
+            DMAR: u1,
+            ///  DMA enable transmitter
+            DMAT: u1,
+            padding: u24,
+        }),
+    };
+
+    ///  Universal synchronous asynchronous receiver transmitter
+    pub const USART1 = extern struct {
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Parity error
+            PE: u1,
+            ///  Framing error
+            FE: u1,
+            ///  Noise error flag
+            NE: u1,
+            ///  Overrun error
+            ORE: u1,
+            ///  IDLE line detected
+            IDLE: u1,
+            ///  Read data register not empty
+            RXNE: u1,
+            ///  Transmission complete
+            TC: u1,
+            ///  Transmit data register empty
+            TXE: u1,
+            ///  LIN break detection flag
+            LBD: u1,
+            ///  CTS flag
+            CTS: u1,
+            padding: u22,
+        }),
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data value
+            DR: u9,
+            padding: u23,
+        }),
+        ///  Baud rate register
+        BRR: mmio.Mmio(packed struct(u32) {
+            ///  fraction of USARTDIV
+            DIV_Fraction: u4,
+            ///  mantissa of USARTDIV
+            DIV_Mantissa: u12,
+            padding: u16,
+        }),
+        ///  Control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Send break
+            SBK: u1,
+            ///  Receiver wakeup
+            RWU: u1,
+            ///  Receiver enable
+            RE: u1,
+            ///  Transmitter enable
+            TE: u1,
+            ///  IDLE interrupt enable
+            IDLEIE: u1,
+            ///  RXNE interrupt enable
+            RXNEIE: u1,
+            ///  Transmission complete interrupt enable
+            TCIE: u1,
+            ///  TXE interrupt enable
+            TXEIE: u1,
+            ///  PE interrupt enable
+            PEIE: u1,
+            ///  Parity selection
+            PS: u1,
+            ///  Parity control enable
+            PCE: u1,
+            ///  Wakeup method
+            WAKE: u1,
+            ///  Word length
+            M: u1,
+            ///  USART enable
+            UE: u1,
+            padding: u18,
+        }),
+        ///  Control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Address of the USART node
+            ADD: u4,
+            reserved5: u1,
+            ///  lin break detection length
+            LBDL: u1,
+            ///  LIN break detection interrupt enable
+            LBDIE: u1,
+            reserved8: u1,
+            ///  Last bit clock pulse
+            LBCL: u1,
+            ///  Clock phase
+            CPHA: u1,
+            ///  Clock polarity
+            CPOL: u1,
+            ///  Clock enable
+            CLKEN: u1,
+            ///  STOP bits
+            STOP: u2,
+            ///  LIN mode enable
+            LINEN: u1,
+            padding: u17,
+        }),
+        ///  Control register 3
+        CR3: mmio.Mmio(packed struct(u32) {
+            ///  Error interrupt enable
+            EIE: u1,
+            ///  IrDA mode enable
+            IREN: u1,
+            ///  IrDA low-power
+            IRLP: u1,
+            ///  Half-duplex selection
+            HDSEL: u1,
+            ///  Smartcard NACK enable
+            NACK: u1,
+            ///  Smartcard mode enable
+            SCEN: u1,
+            ///  DMA enable receiver
+            DMAR: u1,
+            ///  DMA enable transmitter
+            DMAT: u1,
+            ///  RTS enable
+            RTSE: u1,
+            ///  CTS enable
+            CTSE: u1,
+            ///  CTS interrupt enable
+            CTSIE: u1,
+            padding: u21,
+        }),
+        ///  Guard time and prescaler register
+        GTPR: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u8,
+            ///  Guard time value
+            GT: u8,
+            padding: u16,
+        }),
+    };
+
+    ///  Debug support
+    pub const DBG = extern struct {
+        ///  DBGMCU_IDCODE
+        IDCODE: mmio.Mmio(packed struct(u32) {
+            ///  DEV_ID
+            DEV_ID: u12,
+            reserved16: u4,
+            ///  REV_ID
+            REV_ID: u16,
+        }),
+        ///  DBGMCU_CR
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  DBG_SLEEP
+            DBG_SLEEP: u1,
+            ///  DBG_STOP
+            DBG_STOP: u1,
+            ///  DBG_STANDBY
+            DBG_STANDBY: u1,
+            reserved5: u2,
+            ///  TRACE_IOEN
+            TRACE_IOEN: u1,
+            ///  TRACE_MODE
+            TRACE_MODE: u2,
+            ///  DBG_IWDG_STOP
+            DBG_IWDG_STOP: u1,
+            ///  DBG_WWDG_STOP
+            DBG_WWDG_STOP: u1,
+            ///  DBG_TIM1_STOP
+            DBG_TIM1_STOP: u1,
+            ///  DBG_TIM2_STOP
+            DBG_TIM2_STOP: u1,
+            ///  DBG_TIM3_STOP
+            DBG_TIM3_STOP: u1,
+            ///  DBG_TIM4_STOP
+            DBG_TIM4_STOP: u1,
+            ///  DBG_CAN1_STOP
+            DBG_CAN1_STOP: u1,
+            ///  DBG_I2C1_SMBUS_TIMEOUT
+            DBG_I2C1_SMBUS_TIMEOUT: u1,
+            ///  DBG_I2C2_SMBUS_TIMEOUT
+            DBG_I2C2_SMBUS_TIMEOUT: u1,
+            ///  DBG_TIM8_STOP
+            DBG_TIM8_STOP: u1,
+            ///  DBG_TIM5_STOP
+            DBG_TIM5_STOP: u1,
+            ///  DBG_TIM6_STOP
+            DBG_TIM6_STOP: u1,
+            ///  DBG_TIM7_STOP
+            DBG_TIM7_STOP: u1,
+            ///  DBG_CAN2_STOP
+            DBG_CAN2_STOP: u1,
+            padding: u10,
+        }),
+    };
+
+    ///  Digital to analog converter
+    pub const DAC = extern struct {
+        ///  Control register (DAC_CR)
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 enable
+            EN1: u1,
+            ///  DAC channel1 output buffer disable
+            BOFF1: u1,
+            ///  DAC channel1 trigger enable
+            TEN1: u1,
+            ///  DAC channel1 trigger selection
+            TSEL1: u3,
+            ///  DAC channel1 noise/triangle wave generation enable
+            WAVE1: u2,
+            ///  DAC channel1 mask/amplitude selector
+            MAMP1: u4,
+            ///  DAC channel1 DMA enable
+            DMAEN1: u1,
+            reserved16: u3,
+            ///  DAC channel2 enable
+            EN2: u1,
+            ///  DAC channel2 output buffer disable
+            BOFF2: u1,
+            ///  DAC channel2 trigger enable
+            TEN2: u1,
+            ///  DAC channel2 trigger selection
+            TSEL2: u3,
+            ///  DAC channel2 noise/triangle wave generation enable
+            WAVE2: u2,
+            ///  DAC channel2 mask/amplitude selector
+            MAMP2: u4,
+            ///  DAC channel2 DMA enable
+            DMAEN2: u1,
+            padding: u3,
+        }),
+        ///  DAC software trigger register (DAC_SWTRIGR)
+        SWTRIGR: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 software trigger
+            SWTRIG1: u1,
+            ///  DAC channel2 software trigger
+            SWTRIG2: u1,
+            padding: u30,
+        }),
+        ///  DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
+        DHR12R1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 12-bit right-aligned data
+            DACC1DHR: u12,
+            padding: u20,
+        }),
+        ///  DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
+        DHR12L1: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel1 12-bit left-aligned data
+            DACC1DHR: u12,
+            padding: u16,
+        }),
+        ///  DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
+        DHR8R1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 8-bit right-aligned data
+            DACC1DHR: u8,
+            padding: u24,
+        }),
+        ///  DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
+        DHR12R2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 12-bit right-aligned data
+            DACC2DHR: u12,
+            padding: u20,
+        }),
+        ///  DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
+        DHR12L2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel2 12-bit left-aligned data
+            DACC2DHR: u12,
+            padding: u16,
+        }),
+        ///  DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
+        DHR8R2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 8-bit right-aligned data
+            DACC2DHR: u8,
+            padding: u24,
+        }),
+        ///  Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
+        DHR12RD: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 12-bit right-aligned data
+            DACC1DHR: u12,
+            reserved16: u4,
+            ///  DAC channel2 12-bit right-aligned data
+            DACC2DHR: u12,
+            padding: u4,
+        }),
+        ///  DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
+        DHR12LD: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel1 12-bit left-aligned data
+            DACC1DHR: u12,
+            reserved20: u4,
+            ///  DAC channel2 12-bit right-aligned data
+            DACC2DHR: u12,
+        }),
+        ///  DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
+        DHR8RD: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 8-bit right-aligned data
+            DACC1DHR: u8,
+            ///  DAC channel2 8-bit right-aligned data
+            DACC2DHR: u8,
+            padding: u16,
+        }),
+        ///  DAC channel1 data output register (DAC_DOR1)
+        DOR1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 data output
+            DACC1DOR: u12,
+            padding: u20,
+        }),
+        ///  DAC channel2 data output register (DAC_DOR2)
+        DOR2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 data output
+            DACC2DOR: u12,
+            padding: u20,
+        }),
+    };
+
+    ///  Analog to digital converter
+    pub const ADC1 = extern struct {
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog flag
+            AWD: u1,
+            ///  Regular channel end of conversion
+            EOC: u1,
+            ///  Injected channel end of conversion
+            JEOC: u1,
+            ///  Injected channel start flag
+            JSTRT: u1,
+            ///  Regular channel start flag
+            STRT: u1,
+            padding: u27,
+        }),
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog channel select bits
+            AWDCH: u5,
+            ///  Interrupt enable for EOC
+            EOCIE: u1,
+            ///  Analog watchdog interrupt enable
+            AWDIE: u1,
+            ///  Interrupt enable for injected channels
+            JEOCIE: u1,
+            ///  Scan mode
+            SCAN: u1,
+            ///  Enable the watchdog on a single channel in scan mode
+            AWDSGL: u1,
+            ///  Automatic injected group conversion
+            JAUTO: u1,
+            ///  Discontinuous mode on regular channels
+            DISCEN: u1,
+            ///  Discontinuous mode on injected channels
+            JDISCEN: u1,
+            ///  Discontinuous mode channel count
+            DISCNUM: u3,
+            ///  Dual mode selection
+            DUALMOD: u4,
+            reserved22: u2,
+            ///  Analog watchdog enable on injected channels
+            JAWDEN: u1,
+            ///  Analog watchdog enable on regular channels
+            AWDEN: u1,
+            padding: u8,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  A/D converter ON / OFF
+            ADON: u1,
+            ///  Continuous conversion
+            CONT: u1,
+            ///  A/D calibration
+            CAL: u1,
+            ///  Reset calibration
+            RSTCAL: u1,
+            reserved8: u4,
+            ///  Direct memory access mode
+            DMA: u1,
+            reserved11: u2,
+            ///  Data alignment
+            ALIGN: u1,
+            ///  External event select for injected group
+            JEXTSEL: u3,
+            ///  External trigger conversion mode for injected channels
+            JEXTTRIG: u1,
+            reserved17: u1,
+            ///  External event select for regular group
+            EXTSEL: u3,
+            ///  External trigger conversion mode for regular channels
+            EXTTRIG: u1,
+            ///  Start conversion of injected channels
+            JSWSTART: u1,
+            ///  Start conversion of regular channels
+            SWSTART: u1,
+            ///  Temperature sensor and VREFINT enable
+            TSVREFE: u1,
+            padding: u8,
+        }),
+        ///  sample time register 1
+        SMPR1: mmio.Mmio(packed struct(u32) {
+            ///  Channel 10 sample time selection
+            SMP10: u3,
+            ///  Channel 11 sample time selection
+            SMP11: u3,
+            ///  Channel 12 sample time selection
+            SMP12: u3,
+            ///  Channel 13 sample time selection
+            SMP13: u3,
+            ///  Channel 14 sample time selection
+            SMP14: u3,
+            ///  Channel 15 sample time selection
+            SMP15: u3,
+            ///  Channel 16 sample time selection
+            SMP16: u3,
+            ///  Channel 17 sample time selection
+            SMP17: u3,
+            padding: u8,
+        }),
+        ///  sample time register 2
+        SMPR2: mmio.Mmio(packed struct(u32) {
+            ///  Channel 0 sample time selection
+            SMP0: u3,
+            ///  Channel 1 sample time selection
+            SMP1: u3,
+            ///  Channel 2 sample time selection
+            SMP2: u3,
+            ///  Channel 3 sample time selection
+            SMP3: u3,
+            ///  Channel 4 sample time selection
+            SMP4: u3,
+            ///  Channel 5 sample time selection
+            SMP5: u3,
+            ///  Channel 6 sample time selection
+            SMP6: u3,
+            ///  Channel 7 sample time selection
+            SMP7: u3,
+            ///  Channel 8 sample time selection
+            SMP8: u3,
+            ///  Channel 9 sample time selection
+            SMP9: u3,
+            padding: u2,
+        }),
+        ///  injected channel data offset register x
+        JOFR1: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET1: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR2: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET2: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR3: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET3: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR4: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET4: u12,
+            padding: u20,
+        }),
+        ///  watchdog higher threshold register
+        HTR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog higher threshold
+            HT: u12,
+            padding: u20,
+        }),
+        ///  watchdog lower threshold register
+        LTR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog lower threshold
+            LT: u12,
+            padding: u20,
+        }),
+        ///  regular sequence register 1
+        SQR1: mmio.Mmio(packed struct(u32) {
+            ///  13th conversion in regular sequence
+            SQ13: u5,
+            ///  14th conversion in regular sequence
+            SQ14: u5,
+            ///  15th conversion in regular sequence
+            SQ15: u5,
+            ///  16th conversion in regular sequence
+            SQ16: u5,
+            ///  Regular channel sequence length
+            L: u4,
+            padding: u8,
+        }),
+        ///  regular sequence register 2
+        SQR2: mmio.Mmio(packed struct(u32) {
+            ///  7th conversion in regular sequence
+            SQ7: u5,
+            ///  8th conversion in regular sequence
+            SQ8: u5,
+            ///  9th conversion in regular sequence
+            SQ9: u5,
+            ///  10th conversion in regular sequence
+            SQ10: u5,
+            ///  11th conversion in regular sequence
+            SQ11: u5,
+            ///  12th conversion in regular sequence
+            SQ12: u5,
+            padding: u2,
+        }),
+        ///  regular sequence register 3
+        SQR3: mmio.Mmio(packed struct(u32) {
+            ///  1st conversion in regular sequence
+            SQ1: u5,
+            ///  2nd conversion in regular sequence
+            SQ2: u5,
+            ///  3rd conversion in regular sequence
+            SQ3: u5,
+            ///  4th conversion in regular sequence
+            SQ4: u5,
+            ///  5th conversion in regular sequence
+            SQ5: u5,
+            ///  6th conversion in regular sequence
+            SQ6: u5,
+            padding: u2,
+        }),
+        ///  injected sequence register
+        JSQR: mmio.Mmio(packed struct(u32) {
+            ///  1st conversion in injected sequence
+            JSQ1: u5,
+            ///  2nd conversion in injected sequence
+            JSQ2: u5,
+            ///  3rd conversion in injected sequence
+            JSQ3: u5,
+            ///  4th conversion in injected sequence
+            JSQ4: u5,
+            ///  Injected sequence length
+            JL: u2,
+            padding: u10,
+        }),
+        ///  injected data register x
+        JDR1: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR2: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR3: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR4: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  regular data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Regular data
+            DATA: u16,
+            ///  ADC2 data
+            ADC2DATA: u16,
+        }),
+    };
+
+    ///  Analog to digital converter
+    pub const ADC2 = extern struct {
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog flag
+            AWD: u1,
+            ///  Regular channel end of conversion
+            EOC: u1,
+            ///  Injected channel end of conversion
+            JEOC: u1,
+            ///  Injected channel start flag
+            JSTRT: u1,
+            ///  Regular channel start flag
+            STRT: u1,
+            padding: u27,
+        }),
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog channel select bits
+            AWDCH: u5,
+            ///  Interrupt enable for EOC
+            EOCIE: u1,
+            ///  Analog watchdog interrupt enable
+            AWDIE: u1,
+            ///  Interrupt enable for injected channels
+            JEOCIE: u1,
+            ///  Scan mode
+            SCAN: u1,
+            ///  Enable the watchdog on a single channel in scan mode
+            AWDSGL: u1,
+            ///  Automatic injected group conversion
+            JAUTO: u1,
+            ///  Discontinuous mode on regular channels
+            DISCEN: u1,
+            ///  Discontinuous mode on injected channels
+            JDISCEN: u1,
+            ///  Discontinuous mode channel count
+            DISCNUM: u3,
+            reserved22: u6,
+            ///  Analog watchdog enable on injected channels
+            JAWDEN: u1,
+            ///  Analog watchdog enable on regular channels
+            AWDEN: u1,
+            padding: u8,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  A/D converter ON / OFF
+            ADON: u1,
+            ///  Continuous conversion
+            CONT: u1,
+            ///  A/D calibration
+            CAL: u1,
+            ///  Reset calibration
+            RSTCAL: u1,
+            reserved8: u4,
+            ///  Direct memory access mode
+            DMA: u1,
+            reserved11: u2,
+            ///  Data alignment
+            ALIGN: u1,
+            ///  External event select for injected group
+            JEXTSEL: u3,
+            ///  External trigger conversion mode for injected channels
+            JEXTTRIG: u1,
+            reserved17: u1,
+            ///  External event select for regular group
+            EXTSEL: u3,
+            ///  External trigger conversion mode for regular channels
+            EXTTRIG: u1,
+            ///  Start conversion of injected channels
+            JSWSTART: u1,
+            ///  Start conversion of regular channels
+            SWSTART: u1,
+            ///  Temperature sensor and VREFINT enable
+            TSVREFE: u1,
+            padding: u8,
+        }),
+        ///  sample time register 1
+        SMPR1: mmio.Mmio(packed struct(u32) {
+            ///  Channel 10 sample time selection
+            SMP10: u3,
+            ///  Channel 11 sample time selection
+            SMP11: u3,
+            ///  Channel 12 sample time selection
+            SMP12: u3,
+            ///  Channel 13 sample time selection
+            SMP13: u3,
+            ///  Channel 14 sample time selection
+            SMP14: u3,
+            ///  Channel 15 sample time selection
+            SMP15: u3,
+            ///  Channel 16 sample time selection
+            SMP16: u3,
+            ///  Channel 17 sample time selection
+            SMP17: u3,
+            padding: u8,
+        }),
+        ///  sample time register 2
+        SMPR2: mmio.Mmio(packed struct(u32) {
+            ///  Channel 0 sample time selection
+            SMP0: u3,
+            ///  Channel 1 sample time selection
+            SMP1: u3,
+            ///  Channel 2 sample time selection
+            SMP2: u3,
+            ///  Channel 3 sample time selection
+            SMP3: u3,
+            ///  Channel 4 sample time selection
+            SMP4: u3,
+            ///  Channel 5 sample time selection
+            SMP5: u3,
+            ///  Channel 6 sample time selection
+            SMP6: u3,
+            ///  Channel 7 sample time selection
+            SMP7: u3,
+            ///  Channel 8 sample time selection
+            SMP8: u3,
+            ///  Channel 9 sample time selection
+            SMP9: u3,
+            padding: u2,
+        }),
+        ///  injected channel data offset register x
+        JOFR1: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET1: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR2: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET2: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR3: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET3: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR4: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET4: u12,
+            padding: u20,
+        }),
+        ///  watchdog higher threshold register
+        HTR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog higher threshold
+            HT: u12,
+            padding: u20,
+        }),
+        ///  watchdog lower threshold register
+        LTR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog lower threshold
+            LT: u12,
+            padding: u20,
+        }),
+        ///  regular sequence register 1
+        SQR1: mmio.Mmio(packed struct(u32) {
+            ///  13th conversion in regular sequence
+            SQ13: u5,
+            ///  14th conversion in regular sequence
+            SQ14: u5,
+            ///  15th conversion in regular sequence
+            SQ15: u5,
+            ///  16th conversion in regular sequence
+            SQ16: u5,
+            ///  Regular channel sequence length
+            L: u4,
+            padding: u8,
+        }),
+        ///  regular sequence register 2
+        SQR2: mmio.Mmio(packed struct(u32) {
+            ///  7th conversion in regular sequence
+            SQ7: u5,
+            ///  8th conversion in regular sequence
+            SQ8: u5,
+            ///  9th conversion in regular sequence
+            SQ9: u5,
+            ///  10th conversion in regular sequence
+            SQ10: u5,
+            ///  11th conversion in regular sequence
+            SQ11: u5,
+            ///  12th conversion in regular sequence
+            SQ12: u5,
+            padding: u2,
+        }),
+        ///  regular sequence register 3
+        SQR3: mmio.Mmio(packed struct(u32) {
+            ///  1st conversion in regular sequence
+            SQ1: u5,
+            ///  2nd conversion in regular sequence
+            SQ2: u5,
+            ///  3rd conversion in regular sequence
+            SQ3: u5,
+            ///  4th conversion in regular sequence
+            SQ4: u5,
+            ///  5th conversion in regular sequence
+            SQ5: u5,
+            ///  6th conversion in regular sequence
+            SQ6: u5,
+            padding: u2,
+        }),
+        ///  injected sequence register
+        JSQR: mmio.Mmio(packed struct(u32) {
+            ///  1st conversion in injected sequence
+            JSQ1: u5,
+            ///  2nd conversion in injected sequence
+            JSQ2: u5,
+            ///  3rd conversion in injected sequence
+            JSQ3: u5,
+            ///  4th conversion in injected sequence
+            JSQ4: u5,
+            ///  Injected sequence length
+            JL: u2,
+            padding: u10,
+        }),
+        ///  injected data register x
+        JDR1: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR2: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR3: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR4: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  regular data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Regular data
+            DATA: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Controller area network
+    pub const CAN1 = extern struct {
+        ///  CAN_MCR
+        CAN_MCR: mmio.Mmio(packed struct(u32) {
+            ///  INRQ
+            INRQ: u1,
+            ///  SLEEP
+            SLEEP: u1,
+            ///  TXFP
+            TXFP: u1,
+            ///  RFLM
+            RFLM: u1,
+            ///  NART
+            NART: u1,
+            ///  AWUM
+            AWUM: u1,
+            ///  ABOM
+            ABOM: u1,
+            ///  TTCM
+            TTCM: u1,
+            reserved15: u7,
+            ///  RESET
+            RESET: u1,
+            ///  DBF
+            DBF: u1,
+            padding: u15,
+        }),
+        ///  CAN_MSR
+        CAN_MSR: mmio.Mmio(packed struct(u32) {
+            ///  INAK
+            INAK: u1,
+            ///  SLAK
+            SLAK: u1,
+            ///  ERRI
+            ERRI: u1,
+            ///  WKUI
+            WKUI: u1,
+            ///  SLAKI
+            SLAKI: u1,
+            reserved8: u3,
+            ///  TXM
+            TXM: u1,
+            ///  RXM
+            RXM: u1,
+            ///  SAMP
+            SAMP: u1,
+            ///  RX
+            RX: u1,
+            padding: u20,
+        }),
+        ///  CAN_TSR
+        CAN_TSR: mmio.Mmio(packed struct(u32) {
+            ///  RQCP0
+            RQCP0: u1,
+            ///  TXOK0
+            TXOK0: u1,
+            ///  ALST0
+            ALST0: u1,
+            ///  TERR0
+            TERR0: u1,
+            reserved7: u3,
+            ///  ABRQ0
+            ABRQ0: u1,
+            ///  RQCP1
+            RQCP1: u1,
+            ///  TXOK1
+            TXOK1: u1,
+            ///  ALST1
+            ALST1: u1,
+            ///  TERR1
+            TERR1: u1,
+            reserved15: u3,
+            ///  ABRQ1
+            ABRQ1: u1,
+            ///  RQCP2
+            RQCP2: u1,
+            ///  TXOK2
+            TXOK2: u1,
+            ///  ALST2
+            ALST2: u1,
+            ///  TERR2
+            TERR2: u1,
+            reserved23: u3,
+            ///  ABRQ2
+            ABRQ2: u1,
+            ///  CODE
+            CODE: u2,
+            ///  Lowest priority flag for mailbox 0
+            TME0: u1,
+            ///  Lowest priority flag for mailbox 1
+            TME1: u1,
+            ///  Lowest priority flag for mailbox 2
+            TME2: u1,
+            ///  Lowest priority flag for mailbox 0
+            LOW0: u1,
+            ///  Lowest priority flag for mailbox 1
+            LOW1: u1,
+            ///  Lowest priority flag for mailbox 2
+            LOW2: u1,
+        }),
+        ///  CAN_RF0R
+        CAN_RF0R: mmio.Mmio(packed struct(u32) {
+            ///  FMP0
+            FMP0: u2,
+            reserved3: u1,
+            ///  FULL0
+            FULL0: u1,
+            ///  FOVR0
+            FOVR0: u1,
+            ///  RFOM0
+            RFOM0: u1,
+            padding: u26,
+        }),
+        ///  CAN_RF1R
+        CAN_RF1R: mmio.Mmio(packed struct(u32) {
+            ///  FMP1
+            FMP1: u2,
+            reserved3: u1,
+            ///  FULL1
+            FULL1: u1,
+            ///  FOVR1
+            FOVR1: u1,
+            ///  RFOM1
+            RFOM1: u1,
+            padding: u26,
+        }),
+        ///  CAN_IER
+        CAN_IER: mmio.Mmio(packed struct(u32) {
+            ///  TMEIE
+            TMEIE: u1,
+            ///  FMPIE0
+            FMPIE0: u1,
+            ///  FFIE0
+            FFIE0: u1,
+            ///  FOVIE0
+            FOVIE0: u1,
+            ///  FMPIE1
+            FMPIE1: u1,
+            ///  FFIE1
+            FFIE1: u1,
+            ///  FOVIE1
+            FOVIE1: u1,
+            reserved8: u1,
+            ///  EWGIE
+            EWGIE: u1,
+            ///  EPVIE
+            EPVIE: u1,
+            ///  BOFIE
+            BOFIE: u1,
+            ///  LECIE
+            LECIE: u1,
+            reserved15: u3,
+            ///  ERRIE
+            ERRIE: u1,
+            ///  WKUIE
+            WKUIE: u1,
+            ///  SLKIE
+            SLKIE: u1,
+            padding: u14,
+        }),
+        ///  CAN_ESR
+        CAN_ESR: mmio.Mmio(packed struct(u32) {
+            ///  EWGF
+            EWGF: u1,
+            ///  EPVF
+            EPVF: u1,
+            ///  BOFF
+            BOFF: u1,
+            reserved4: u1,
+            ///  LEC
+            LEC: u3,
+            reserved16: u9,
+            ///  TEC
+            TEC: u8,
+            ///  REC
+            REC: u8,
+        }),
+        ///  CAN_BTR
+        CAN_BTR: mmio.Mmio(packed struct(u32) {
+            ///  BRP
+            BRP: u10,
+            reserved16: u6,
+            ///  TS1
+            TS1: u4,
+            ///  TS2
+            TS2: u3,
+            reserved24: u1,
+            ///  SJW
+            SJW: u2,
+            reserved30: u4,
+            ///  LBKM
+            LBKM: u1,
+            ///  SILM
+            SILM: u1,
+        }),
+        reserved384: [352]u8,
+        ///  CAN_TI0R
+        CAN_TI0R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  CAN_TDT0R
+        CAN_TDT0R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  CAN_TDL0R
+        CAN_TDL0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  CAN_TDH0R
+        CAN_TDH0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  CAN_TI1R
+        CAN_TI1R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  CAN_TDT1R
+        CAN_TDT1R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  CAN_TDL1R
+        CAN_TDL1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  CAN_TDH1R
+        CAN_TDH1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  CAN_TI2R
+        CAN_TI2R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  CAN_TDT2R
+        CAN_TDT2R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  CAN_TDL2R
+        CAN_TDL2R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  CAN_TDH2R
+        CAN_TDH2R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  CAN_RI0R
+        CAN_RI0R: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  CAN_RDT0R
+        CAN_RDT0R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  FMI
+            FMI: u8,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  CAN_RDL0R
+        CAN_RDL0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  CAN_RDH0R
+        CAN_RDH0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  CAN_RI1R
+        CAN_RI1R: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  CAN_RDT1R
+        CAN_RDT1R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  FMI
+            FMI: u8,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  CAN_RDL1R
+        CAN_RDL1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  CAN_RDH1R
+        CAN_RDH1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        reserved512: [48]u8,
+        ///  CAN_FMR
+        CAN_FMR: mmio.Mmio(packed struct(u32) {
+            ///  FINIT
+            FINIT: u1,
+            padding: u31,
+        }),
+        ///  CAN_FM1R
+        CAN_FM1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter mode
+            FBM0: u1,
+            ///  Filter mode
+            FBM1: u1,
+            ///  Filter mode
+            FBM2: u1,
+            ///  Filter mode
+            FBM3: u1,
+            ///  Filter mode
+            FBM4: u1,
+            ///  Filter mode
+            FBM5: u1,
+            ///  Filter mode
+            FBM6: u1,
+            ///  Filter mode
+            FBM7: u1,
+            ///  Filter mode
+            FBM8: u1,
+            ///  Filter mode
+            FBM9: u1,
+            ///  Filter mode
+            FBM10: u1,
+            ///  Filter mode
+            FBM11: u1,
+            ///  Filter mode
+            FBM12: u1,
+            ///  Filter mode
+            FBM13: u1,
+            padding: u18,
+        }),
+        reserved524: [4]u8,
+        ///  CAN_FS1R
+        CAN_FS1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter scale configuration
+            FSC0: u1,
+            ///  Filter scale configuration
+            FSC1: u1,
+            ///  Filter scale configuration
+            FSC2: u1,
+            ///  Filter scale configuration
+            FSC3: u1,
+            ///  Filter scale configuration
+            FSC4: u1,
+            ///  Filter scale configuration
+            FSC5: u1,
+            ///  Filter scale configuration
+            FSC6: u1,
+            ///  Filter scale configuration
+            FSC7: u1,
+            ///  Filter scale configuration
+            FSC8: u1,
+            ///  Filter scale configuration
+            FSC9: u1,
+            ///  Filter scale configuration
+            FSC10: u1,
+            ///  Filter scale configuration
+            FSC11: u1,
+            ///  Filter scale configuration
+            FSC12: u1,
+            ///  Filter scale configuration
+            FSC13: u1,
+            padding: u18,
+        }),
+        reserved532: [4]u8,
+        ///  CAN_FFA1R
+        CAN_FFA1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter FIFO assignment for filter 0
+            FFA0: u1,
+            ///  Filter FIFO assignment for filter 1
+            FFA1: u1,
+            ///  Filter FIFO assignment for filter 2
+            FFA2: u1,
+            ///  Filter FIFO assignment for filter 3
+            FFA3: u1,
+            ///  Filter FIFO assignment for filter 4
+            FFA4: u1,
+            ///  Filter FIFO assignment for filter 5
+            FFA5: u1,
+            ///  Filter FIFO assignment for filter 6
+            FFA6: u1,
+            ///  Filter FIFO assignment for filter 7
+            FFA7: u1,
+            ///  Filter FIFO assignment for filter 8
+            FFA8: u1,
+            ///  Filter FIFO assignment for filter 9
+            FFA9: u1,
+            ///  Filter FIFO assignment for filter 10
+            FFA10: u1,
+            ///  Filter FIFO assignment for filter 11
+            FFA11: u1,
+            ///  Filter FIFO assignment for filter 12
+            FFA12: u1,
+            ///  Filter FIFO assignment for filter 13
+            FFA13: u1,
+            padding: u18,
+        }),
+        reserved540: [4]u8,
+        ///  CAN_FA1R
+        CAN_FA1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter active
+            FACT0: u1,
+            ///  Filter active
+            FACT1: u1,
+            ///  Filter active
+            FACT2: u1,
+            ///  Filter active
+            FACT3: u1,
+            ///  Filter active
+            FACT4: u1,
+            ///  Filter active
+            FACT5: u1,
+            ///  Filter active
+            FACT6: u1,
+            ///  Filter active
+            FACT7: u1,
+            ///  Filter active
+            FACT8: u1,
+            ///  Filter active
+            FACT9: u1,
+            ///  Filter active
+            FACT10: u1,
+            ///  Filter active
+            FACT11: u1,
+            ///  Filter active
+            FACT12: u1,
+            ///  Filter active
+            FACT13: u1,
+            padding: u18,
+        }),
+        reserved576: [32]u8,
+        ///  Filter bank 0 register 1
+        F0R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 0 register 2
+        F0R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 1 register 1
+        F1R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 1 register 2
+        F1R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 2 register 1
+        F2R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 2 register 2
+        F2R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 3 register 1
+        F3R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 3 register 2
+        F3R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 1
+        F4R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 2
+        F4R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 5 register 1
+        F5R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 5 register 2
+        F5R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 6 register 1
+        F6R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 6 register 2
+        F6R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 7 register 1
+        F7R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 7 register 2
+        F7R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 8 register 1
+        F8R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 8 register 2
+        F8R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 9 register 1
+        F9R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 9 register 2
+        F9R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 10 register 1
+        F10R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 10 register 2
+        F10R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 11 register 1
+        F11R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 11 register 2
+        F11R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 1
+        F12R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 12 register 2
+        F12R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 13 register 1
+        F13R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 13 register 2
+        F13R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+    };
+};
diff --git a/src/chips/STM32F303.json b/src/chips/STM32F303.json
new file mode 100644
index 000000000..6468498cc
--- /dev/null
+++ b/src/chips/STM32F303.json
@@ -0,0 +1,33184 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "GPIOA": {
+        "description": "General-purpose I/Os",
+        "children": {
+          "registers": {
+            "MODER": {
+              "description": "GPIO port mode register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 671088640,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODER15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MODER14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "MODER13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MODER12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "MODER11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MODER10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "MODER9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MODER8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "MODER7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MODER6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MODER5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MODER4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MODER3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MODER2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MODER1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODER0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTYPER": {
+              "description": "GPIO port output type register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OT15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OT14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OT13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OT12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OT11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OT10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OT9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OT8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OT7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OT6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OT5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OT4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OT3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OT2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OT1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OT0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OSPEEDR": {
+              "description": "GPIO port output speed\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OSPEEDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "OSPEEDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "OSPEEDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "OSPEEDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "OSPEEDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "OSPEEDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "OSPEEDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "OSPEEDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "OSPEEDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "OSPEEDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "OSPEEDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "OSPEEDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSPEEDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "OSPEEDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "OSPEEDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "OSPEEDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PUPDR": {
+              "description": "GPIO port pull-up/pull-down\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 603979776,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PUPDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "PUPDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "PUPDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "PUPDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "PUPDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "PUPDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "PUPDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "PUPDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PUPDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "PUPDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PUPDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PUPDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PUPDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PUPDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PUPDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "PUPDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "GPIO port input data register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDR15": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IDR14": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "IDR13": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "IDR12": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IDR11": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IDR10": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IDR9": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IDR8": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IDR7": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IDR6": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IDR5": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDR4": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDR3": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IDR2": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDR1": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IDR0": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ODR": {
+              "description": "GPIO port output data register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ODR15": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ODR14": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ODR13": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ODR12": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ODR11": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ODR10": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ODR9": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODR8": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ODR7": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ODR6": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ODR5": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ODR4": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ODR3": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ODR2": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ODR1": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ODR0": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BSRR": {
+              "description": "GPIO port bit set/reset\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BR15": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BR0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BS15": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BS14": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BS13": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BS12": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BS11": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BS10": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BS9": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BS8": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BS7": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BS6": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BS5": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BS4": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BS3": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BS2": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BS1": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BS0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LCKR": {
+              "description": "GPIO port configuration lock\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LCKK": {
+                    "description": "Lok Key",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "LCK15": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LCK14": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "LCK13": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LCK12": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LCK11": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LCK10": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LCK9": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LCK8": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LCK7": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCK6": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LCK5": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LCK4": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "LCK3": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LCK2": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LCK1": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LCK0": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AFRL": {
+              "description": "GPIO alternate function low\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRL7": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRL6": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRL5": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRL4": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRL3": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRL2": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRL1": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRL0": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "AFRH": {
+              "description": "GPIO alternate function high\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRH15": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRH14": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRH13": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRH12": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRH11": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRH10": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRH9": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRH8": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BRR": {
+              "description": "Port bit reset register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BR0": {
+                    "description": "Port x Reset bit y",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Port x Reset bit y",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Port x Reset bit y",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Port x Reset bit y",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Port x Reset bit y",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Port x Reset bit y",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Port x Reset bit y",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Port x Reset bit y",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Port x Reset bit y",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Port x Reset bit y",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Port x Reset bit y",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Port x Reset bit y",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Port x Reset bit y",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Port x Reset bit y",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Port x Reset bit y",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BR15": {
+                    "description": "Port x Reset bit y",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOB": {
+        "description": "General-purpose I/Os",
+        "children": {
+          "registers": {
+            "MODER": {
+              "description": "GPIO port mode register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODER15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MODER14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "MODER13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MODER12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "MODER11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MODER10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "MODER9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MODER8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "MODER7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MODER6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MODER5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MODER4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MODER3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MODER2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MODER1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODER0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTYPER": {
+              "description": "GPIO port output type register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OT15": {
+                    "description": "Port x configuration bit\n              15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OT14": {
+                    "description": "Port x configuration bit\n              14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OT13": {
+                    "description": "Port x configuration bit\n              13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OT12": {
+                    "description": "Port x configuration bit\n              12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OT11": {
+                    "description": "Port x configuration bit\n              11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OT10": {
+                    "description": "Port x configuration bit\n              10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OT9": {
+                    "description": "Port x configuration bit 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OT8": {
+                    "description": "Port x configuration bit 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OT7": {
+                    "description": "Port x configuration bit 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OT6": {
+                    "description": "Port x configuration bit 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OT5": {
+                    "description": "Port x configuration bit 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OT4": {
+                    "description": "Port x configuration bit 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OT3": {
+                    "description": "Port x configuration bit 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OT2": {
+                    "description": "Port x configuration bit 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OT1": {
+                    "description": "Port x configuration bit 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OT0": {
+                    "description": "Port x configuration bit 0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OSPEEDR": {
+              "description": "GPIO port output speed\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OSPEEDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "OSPEEDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "OSPEEDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "OSPEEDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "OSPEEDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "OSPEEDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "OSPEEDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "OSPEEDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "OSPEEDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "OSPEEDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "OSPEEDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "OSPEEDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSPEEDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "OSPEEDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "OSPEEDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "OSPEEDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PUPDR": {
+              "description": "GPIO port pull-up/pull-down\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PUPDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "PUPDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "PUPDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "PUPDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "PUPDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "PUPDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "PUPDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "PUPDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PUPDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "PUPDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PUPDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PUPDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PUPDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PUPDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PUPDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "PUPDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "GPIO port input data register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDR15": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IDR14": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "IDR13": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "IDR12": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IDR11": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IDR10": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IDR9": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IDR8": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IDR7": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IDR6": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IDR5": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDR4": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDR3": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IDR2": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDR1": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IDR0": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ODR": {
+              "description": "GPIO port output data register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ODR15": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ODR14": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ODR13": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ODR12": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ODR11": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ODR10": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ODR9": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODR8": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ODR7": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ODR6": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ODR5": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ODR4": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ODR3": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ODR2": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ODR1": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ODR0": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BSRR": {
+              "description": "GPIO port bit set/reset\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BR15": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BR0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BS15": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BS14": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BS13": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BS12": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BS11": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BS10": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BS9": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BS8": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BS7": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BS6": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BS5": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BS4": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BS3": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BS2": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BS1": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BS0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LCKR": {
+              "description": "GPIO port configuration lock\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LCKK": {
+                    "description": "Lok Key",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "LCK15": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LCK14": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "LCK13": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LCK12": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LCK11": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LCK10": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LCK9": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LCK8": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LCK7": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCK6": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LCK5": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LCK4": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "LCK3": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LCK2": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LCK1": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LCK0": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AFRL": {
+              "description": "GPIO alternate function low\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRL7": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRL6": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRL5": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRL4": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRL3": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRL2": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRL1": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRL0": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "AFRH": {
+              "description": "GPIO alternate function high\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRH15": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRH14": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRH13": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRH12": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRH11": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRH10": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRH9": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRH8": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BRR": {
+              "description": "Port bit reset register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BR0": {
+                    "description": "Port x Reset bit y",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Port x Reset bit y",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Port x Reset bit y",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Port x Reset bit y",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Port x Reset bit y",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Port x Reset bit y",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Port x Reset bit y",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Port x Reset bit y",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Port x Reset bit y",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Port x Reset bit y",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Port x Reset bit y",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Port x Reset bit y",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Port x Reset bit y",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Port x Reset bit y",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Port x Reset bit y",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BR15": {
+                    "description": "Port x Reset bit y",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SCB_ACTRL": {
+        "description": "System control block ACTLR",
+        "children": {
+          "registers": {
+            "ACTRL": {
+              "description": "Auxiliary control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DISMCYCINT": {
+                    "description": "DISMCYCINT",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DISDEFWBUF": {
+                    "description": "DISDEFWBUF",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DISFOLD": {
+                    "description": "DISFOLD",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DISFPCA": {
+                    "description": "DISFPCA",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DISOOFP": {
+                    "description": "DISOOFP",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FPU_CPACR": {
+        "description": "Floating point unit CPACR",
+        "children": {
+          "registers": {
+            "CPACR": {
+              "description": "Coprocessor access control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CP": {
+                    "description": "CP",
+                    "offset": 20,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NVIC_STIR": {
+        "description": "Nested vectored interrupt\n      controller",
+        "children": {
+          "registers": {
+            "STIR": {
+              "description": "Software trigger interrupt\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTID": {
+                    "description": "Software generated interrupt\n              ID",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SCB": {
+        "description": "System control block",
+        "children": {
+          "registers": {
+            "CPUID": {
+              "description": "CPUID base register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1091551809,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "Revision": {
+                    "description": "Revision number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "PartNo": {
+                    "description": "Part number of the\n              processor",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "Constant": {
+                    "description": "Reads as 0xF",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "Variant": {
+                    "description": "Variant number",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "Implementer": {
+                    "description": "Implementer code",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ICSR": {
+              "description": "Interrupt control and state\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTACTIVE": {
+                    "description": "Active vector",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "RETTOBASE": {
+                    "description": "Return to base level",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "VECTPENDING": {
+                    "description": "Pending vector",
+                    "offset": 12,
+                    "size": 7
+                  },
+                  "ISRPENDING": {
+                    "description": "Interrupt pending flag",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PENDSTCLR": {
+                    "description": "SysTick exception clear-pending\n              bit",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PENDSTSET": {
+                    "description": "SysTick exception set-pending\n              bit",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PENDSVCLR": {
+                    "description": "PendSV clear-pending bit",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PENDSVSET": {
+                    "description": "PendSV set-pending bit",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "NMIPENDSET": {
+                    "description": "NMI set-pending bit.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "VTOR": {
+              "description": "Vector table offset register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TBLOFF": {
+                    "description": "Vector table base offset\n              field",
+                    "offset": 9,
+                    "size": 21
+                  }
+                }
+              }
+            },
+            "AIRCR": {
+              "description": "Application interrupt and reset control\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTRESET": {
+                    "description": "VECTRESET",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "VECTCLRACTIVE": {
+                    "description": "VECTCLRACTIVE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SYSRESETREQ": {
+                    "description": "SYSRESETREQ",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PRIGROUP": {
+                    "description": "PRIGROUP",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "ENDIANESS": {
+                    "description": "ENDIANESS",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "VECTKEYSTAT": {
+                    "description": "Register key",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SCR": {
+              "description": "System control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLEEPONEXIT": {
+                    "description": "SLEEPONEXIT",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEEPDEEP": {
+                    "description": "SLEEPDEEP",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SEVEONPEND": {
+                    "description": "Send Event on Pending bit",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "Configuration and control\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NONBASETHRDENA": {
+                    "description": "Configures how the processor enters\n              Thread mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USERSETMPEND": {
+                    "description": "USERSETMPEND",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UNALIGN__TRP": {
+                    "description": "UNALIGN_ TRP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIV_0_TRP": {
+                    "description": "DIV_0_TRP",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BFHFNMIGN": {
+                    "description": "BFHFNMIGN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "STKALIGN": {
+                    "description": "STKALIGN",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SHPR1": {
+              "description": "System handler priority\n          registers",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_4": {
+                    "description": "Priority of system handler\n              4",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "PRI_5": {
+                    "description": "Priority of system handler\n              5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "PRI_6": {
+                    "description": "Priority of system handler\n              6",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHPR2": {
+              "description": "System handler priority\n          registers",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_11": {
+                    "description": "Priority of system handler\n              11",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHPR3": {
+              "description": "System handler priority\n          registers",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_14": {
+                    "description": "Priority of system handler\n              14",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "PRI_15": {
+                    "description": "Priority of system handler\n              15",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHCRS": {
+              "description": "System handler control and state\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMFAULTACT": {
+                    "description": "Memory management fault exception active\n              bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BUSFAULTACT": {
+                    "description": "Bus fault exception active\n              bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "USGFAULTACT": {
+                    "description": "Usage fault exception active\n              bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SVCALLACT": {
+                    "description": "SVC call active bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MONITORACT": {
+                    "description": "Debug monitor active bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PENDSVACT": {
+                    "description": "PendSV exception active\n              bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SYSTICKACT": {
+                    "description": "SysTick exception active\n              bit",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USGFAULTPENDED": {
+                    "description": "Usage fault exception pending\n              bit",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MEMFAULTPENDED": {
+                    "description": "Memory management fault exception\n              pending bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BUSFAULTPENDED": {
+                    "description": "Bus fault exception pending\n              bit",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SVCALLPENDED": {
+                    "description": "SVC call pending bit",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MEMFAULTENA": {
+                    "description": "Memory management fault enable\n              bit",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUSFAULTENA": {
+                    "description": "Bus fault enable bit",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USGFAULTENA": {
+                    "description": "Usage fault enable bit",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CFSR_UFSR_BFSR_MMFSR": {
+              "description": "Configurable fault status\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IACCVIOL": {
+                    "description": "Instruction access violation\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MUNSTKERR": {
+                    "description": "Memory manager fault on unstacking for a\n              return from exception",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MSTKERR": {
+                    "description": "Memory manager fault on stacking for\n              exception entry.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MLSPERR": {
+                    "description": "MLSPERR",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MMARVALID": {
+                    "description": "Memory Management Fault Address Register\n              (MMAR) valid flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IBUSERR": {
+                    "description": "Instruction bus error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PRECISERR": {
+                    "description": "Precise data bus error",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IMPRECISERR": {
+                    "description": "Imprecise data bus error",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "UNSTKERR": {
+                    "description": "Bus fault on unstacking for a return\n              from exception",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STKERR": {
+                    "description": "Bus fault on stacking for exception\n              entry",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LSPERR": {
+                    "description": "Bus fault on floating-point lazy state\n              preservation",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BFARVALID": {
+                    "description": "Bus Fault Address Register (BFAR) valid\n              flag",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "UNDEFINSTR": {
+                    "description": "Undefined instruction usage\n              fault",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "INVSTATE": {
+                    "description": "Invalid state usage fault",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INVPC": {
+                    "description": "Invalid PC load usage\n              fault",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "NOCP": {
+                    "description": "No coprocessor usage\n              fault.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UNALIGNED": {
+                    "description": "Unaligned access usage\n              fault",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "DIVBYZERO": {
+                    "description": "Divide by zero usage fault",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HFSR": {
+              "description": "Hard fault status register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTTBL": {
+                    "description": "Vector table hard fault",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FORCED": {
+                    "description": "Forced hard fault",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DEBUG_VT": {
+                    "description": "Reserved for Debug use",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMFAR": {
+              "description": "Memory management fault address\n          register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMFAR": {
+                    "description": "Memory management fault\n              address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BFAR": {
+              "description": "Bus fault address register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BFAR": {
+                    "description": "Bus fault address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "AFSR": {
+              "description": "Auxiliary fault status\n          register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IMPDEF": {
+                    "description": "Implementation defined",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "STK": {
+        "description": "SysTick timer",
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "SysTick control and status\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TICKINT": {
+                    "description": "SysTick exception request\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CLKSOURCE": {
+                    "description": "Clock source selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "COUNTFLAG": {
+                    "description": "COUNTFLAG",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LOAD": {
+              "description": "SysTick reload value register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RELOAD": {
+                    "description": "RELOAD value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "VAL": {
+              "description": "SysTick current value register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CURRENT": {
+                    "description": "Current counter value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "CALIB": {
+              "description": "SysTick calibration value\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TENMS": {
+                    "description": "Calibration value",
+                    "offset": 0,
+                    "size": 24
+                  },
+                  "SKEW": {
+                    "description": "SKEW flag: Indicates whether the TENMS\n              value is exact",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "NOREF": {
+                    "description": "NOREF flag. Reads as zero",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "MPU": {
+        "description": "Memory protection unit",
+        "children": {
+          "registers": {
+            "MPU_TYPER": {
+              "description": "MPU type register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SEPARATE": {
+                    "description": "Separate flag",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DREGION": {
+                    "description": "Number of MPU data regions",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IREGION": {
+                    "description": "Number of MPU instruction\n              regions",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MPU_CTRL": {
+              "description": "MPU control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enables the MPU",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HFNMIENA": {
+                    "description": "Enables the operation of MPU during hard\n              fault",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PRIVDEFENA": {
+                    "description": "Enable priviliged software access to\n              default memory map",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MPU_RNR": {
+              "description": "MPU region number register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION": {
+                    "description": "MPU region",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MPU_RBAR": {
+              "description": "MPU region base address\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION": {
+                    "description": "MPU region field",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "VALID": {
+                    "description": "MPU region number valid",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ADDR": {
+                    "description": "Region base address field",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "MPU_RASR": {
+              "description": "MPU region attribute and size\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Region enable bit.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SIZE": {
+                    "description": "Size of the MPU protection\n              region",
+                    "offset": 1,
+                    "size": 5
+                  },
+                  "SRD": {
+                    "description": "Subregion disable bits",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "B": {
+                    "description": "memory attribute",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "C": {
+                    "description": "memory attribute",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "S": {
+                    "description": "Shareable memory attribute",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TEX": {
+                    "description": "memory attribute",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "AP": {
+                    "description": "Access permission",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "XN": {
+                    "description": "Instruction access disable\n              bit",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TSC": {
+        "description": "Touch sensing controller",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTPH": {
+                    "description": "Charge transfer pulse high",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "CTPL": {
+                    "description": "Charge transfer pulse low",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "SSD": {
+                    "description": "Spread spectrum deviation",
+                    "offset": 17,
+                    "size": 7
+                  },
+                  "SSE": {
+                    "description": "Spread spectrum enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SSPSC": {
+                    "description": "Spread spectrum prescaler",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "PGPSC": {
+                    "description": "pulse generator prescaler",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "MCV": {
+                    "description": "Max count value",
+                    "offset": 5,
+                    "size": 3
+                  },
+                  "IODEF": {
+                    "description": "I/O Default mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SYNCPOL": {
+                    "description": "Synchronization pin\n              polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "AM": {
+                    "description": "Acquisition mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "START": {
+                    "description": "Start a new acquisition",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TSCE": {
+                    "description": "Touch sensing controller\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "interrupt enable register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCEIE": {
+                    "description": "Max count error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EOAIE": {
+                    "description": "End of acquisition interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "interrupt clear register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCEIC": {
+                    "description": "Max count error interrupt\n              clear",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EOAIC": {
+                    "description": "End of acquisition interrupt\n              clear",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ISR": {
+              "description": "interrupt status register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCEF": {
+                    "description": "Max count error flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EOAF": {
+                    "description": "End of acquisition flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IOHCR": {
+              "description": "I/O hysteresis control\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "G1_IO1": {
+                    "description": "G1_IO1 Schmitt trigger hysteresis\n              mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "G1_IO2": {
+                    "description": "G1_IO2 Schmitt trigger hysteresis\n              mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "G1_IO3": {
+                    "description": "G1_IO3 Schmitt trigger hysteresis\n              mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "G1_IO4": {
+                    "description": "G1_IO4 Schmitt trigger hysteresis\n              mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "G2_IO1": {
+                    "description": "G2_IO1 Schmitt trigger hysteresis\n              mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "G2_IO2": {
+                    "description": "G2_IO2 Schmitt trigger hysteresis\n              mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "G2_IO3": {
+                    "description": "G2_IO3 Schmitt trigger hysteresis\n              mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "G2_IO4": {
+                    "description": "G2_IO4 Schmitt trigger hysteresis\n              mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "G3_IO1": {
+                    "description": "G3_IO1 Schmitt trigger hysteresis\n              mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "G3_IO2": {
+                    "description": "G3_IO2 Schmitt trigger hysteresis\n              mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "G3_IO3": {
+                    "description": "G3_IO3 Schmitt trigger hysteresis\n              mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "G3_IO4": {
+                    "description": "G3_IO4 Schmitt trigger hysteresis\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "G4_IO1": {
+                    "description": "G4_IO1 Schmitt trigger hysteresis\n              mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "G4_IO2": {
+                    "description": "G4_IO2 Schmitt trigger hysteresis\n              mode",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "G4_IO3": {
+                    "description": "G4_IO3 Schmitt trigger hysteresis\n              mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "G4_IO4": {
+                    "description": "G4_IO4 Schmitt trigger hysteresis\n              mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "G5_IO1": {
+                    "description": "G5_IO1 Schmitt trigger hysteresis\n              mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "G5_IO2": {
+                    "description": "G5_IO2 Schmitt trigger hysteresis\n              mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "G5_IO3": {
+                    "description": "G5_IO3 Schmitt trigger hysteresis\n              mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "G5_IO4": {
+                    "description": "G5_IO4 Schmitt trigger hysteresis\n              mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "G6_IO1": {
+                    "description": "G6_IO1 Schmitt trigger hysteresis\n              mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "G6_IO2": {
+                    "description": "G6_IO2 Schmitt trigger hysteresis\n              mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "G6_IO3": {
+                    "description": "G6_IO3 Schmitt trigger hysteresis\n              mode",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "G6_IO4": {
+                    "description": "G6_IO4 Schmitt trigger hysteresis\n              mode",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "G7_IO1": {
+                    "description": "G7_IO1 Schmitt trigger hysteresis\n              mode",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "G7_IO2": {
+                    "description": "G7_IO2 Schmitt trigger hysteresis\n              mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "G7_IO3": {
+                    "description": "G7_IO3 Schmitt trigger hysteresis\n              mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "G7_IO4": {
+                    "description": "G7_IO4 Schmitt trigger hysteresis\n              mode",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "G8_IO1": {
+                    "description": "G8_IO1 Schmitt trigger hysteresis\n              mode",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "G8_IO2": {
+                    "description": "G8_IO2 Schmitt trigger hysteresis\n              mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "G8_IO3": {
+                    "description": "G8_IO3 Schmitt trigger hysteresis\n              mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "G8_IO4": {
+                    "description": "G8_IO4 Schmitt trigger hysteresis\n              mode",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IOASCR": {
+              "description": "I/O analog switch control\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "G1_IO1": {
+                    "description": "G1_IO1 analog switch\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "G1_IO2": {
+                    "description": "G1_IO2 analog switch\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "G1_IO3": {
+                    "description": "G1_IO3 analog switch\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "G1_IO4": {
+                    "description": "G1_IO4 analog switch\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "G2_IO1": {
+                    "description": "G2_IO1 analog switch\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "G2_IO2": {
+                    "description": "G2_IO2 analog switch\n              enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "G2_IO3": {
+                    "description": "G2_IO3 analog switch\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "G2_IO4": {
+                    "description": "G2_IO4 analog switch\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "G3_IO1": {
+                    "description": "G3_IO1 analog switch\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "G3_IO2": {
+                    "description": "G3_IO2 analog switch\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "G3_IO3": {
+                    "description": "G3_IO3 analog switch\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "G3_IO4": {
+                    "description": "G3_IO4 analog switch\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "G4_IO1": {
+                    "description": "G4_IO1 analog switch\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "G4_IO2": {
+                    "description": "G4_IO2 analog switch\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "G4_IO3": {
+                    "description": "G4_IO3 analog switch\n              enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "G4_IO4": {
+                    "description": "G4_IO4 analog switch\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "G5_IO1": {
+                    "description": "G5_IO1 analog switch\n              enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "G5_IO2": {
+                    "description": "G5_IO2 analog switch\n              enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "G5_IO3": {
+                    "description": "G5_IO3 analog switch\n              enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "G5_IO4": {
+                    "description": "G5_IO4 analog switch\n              enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "G6_IO1": {
+                    "description": "G6_IO1 analog switch\n              enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "G6_IO2": {
+                    "description": "G6_IO2 analog switch\n              enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "G6_IO3": {
+                    "description": "G6_IO3 analog switch\n              enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "G6_IO4": {
+                    "description": "G6_IO4 analog switch\n              enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "G7_IO1": {
+                    "description": "G7_IO1 analog switch\n              enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "G7_IO2": {
+                    "description": "G7_IO2 analog switch\n              enable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "G7_IO3": {
+                    "description": "G7_IO3 analog switch\n              enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "G7_IO4": {
+                    "description": "G7_IO4 analog switch\n              enable",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "G8_IO1": {
+                    "description": "G8_IO1 analog switch\n              enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "G8_IO2": {
+                    "description": "G8_IO2 analog switch\n              enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "G8_IO3": {
+                    "description": "G8_IO3 analog switch\n              enable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "G8_IO4": {
+                    "description": "G8_IO4 analog switch\n              enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IOSCR": {
+              "description": "I/O sampling control register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "G1_IO1": {
+                    "description": "G1_IO1 sampling mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "G1_IO2": {
+                    "description": "G1_IO2 sampling mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "G1_IO3": {
+                    "description": "G1_IO3 sampling mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "G1_IO4": {
+                    "description": "G1_IO4 sampling mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "G2_IO1": {
+                    "description": "G2_IO1 sampling mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "G2_IO2": {
+                    "description": "G2_IO2 sampling mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "G2_IO3": {
+                    "description": "G2_IO3 sampling mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "G2_IO4": {
+                    "description": "G2_IO4 sampling mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "G3_IO1": {
+                    "description": "G3_IO1 sampling mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "G3_IO2": {
+                    "description": "G3_IO2 sampling mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "G3_IO3": {
+                    "description": "G3_IO3 sampling mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "G3_IO4": {
+                    "description": "G3_IO4 sampling mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "G4_IO1": {
+                    "description": "G4_IO1 sampling mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "G4_IO2": {
+                    "description": "G4_IO2 sampling mode",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "G4_IO3": {
+                    "description": "G4_IO3 sampling mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "G4_IO4": {
+                    "description": "G4_IO4 sampling mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "G5_IO1": {
+                    "description": "G5_IO1 sampling mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "G5_IO2": {
+                    "description": "G5_IO2 sampling mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "G5_IO3": {
+                    "description": "G5_IO3 sampling mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "G5_IO4": {
+                    "description": "G5_IO4 sampling mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "G6_IO1": {
+                    "description": "G6_IO1 sampling mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "G6_IO2": {
+                    "description": "G6_IO2 sampling mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "G6_IO3": {
+                    "description": "G6_IO3 sampling mode",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "G6_IO4": {
+                    "description": "G6_IO4 sampling mode",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "G7_IO1": {
+                    "description": "G7_IO1 sampling mode",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "G7_IO2": {
+                    "description": "G7_IO2 sampling mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "G7_IO3": {
+                    "description": "G7_IO3 sampling mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "G7_IO4": {
+                    "description": "G7_IO4 sampling mode",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "G8_IO1": {
+                    "description": "G8_IO1 sampling mode",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "G8_IO2": {
+                    "description": "G8_IO2 sampling mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "G8_IO3": {
+                    "description": "G8_IO3 sampling mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "G8_IO4": {
+                    "description": "G8_IO4 sampling mode",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IOCCR": {
+              "description": "I/O channel control register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "G1_IO1": {
+                    "description": "G1_IO1 channel mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "G1_IO2": {
+                    "description": "G1_IO2 channel mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "G1_IO3": {
+                    "description": "G1_IO3 channel mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "G1_IO4": {
+                    "description": "G1_IO4 channel mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "G2_IO1": {
+                    "description": "G2_IO1 channel mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "G2_IO2": {
+                    "description": "G2_IO2 channel mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "G2_IO3": {
+                    "description": "G2_IO3 channel mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "G2_IO4": {
+                    "description": "G2_IO4 channel mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "G3_IO1": {
+                    "description": "G3_IO1 channel mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "G3_IO2": {
+                    "description": "G3_IO2 channel mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "G3_IO3": {
+                    "description": "G3_IO3 channel mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "G3_IO4": {
+                    "description": "G3_IO4 channel mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "G4_IO1": {
+                    "description": "G4_IO1 channel mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "G4_IO2": {
+                    "description": "G4_IO2 channel mode",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "G4_IO3": {
+                    "description": "G4_IO3 channel mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "G4_IO4": {
+                    "description": "G4_IO4 channel mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "G5_IO1": {
+                    "description": "G5_IO1 channel mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "G5_IO2": {
+                    "description": "G5_IO2 channel mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "G5_IO3": {
+                    "description": "G5_IO3 channel mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "G5_IO4": {
+                    "description": "G5_IO4 channel mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "G6_IO1": {
+                    "description": "G6_IO1 channel mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "G6_IO2": {
+                    "description": "G6_IO2 channel mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "G6_IO3": {
+                    "description": "G6_IO3 channel mode",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "G6_IO4": {
+                    "description": "G6_IO4 channel mode",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "G7_IO1": {
+                    "description": "G7_IO1 channel mode",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "G7_IO2": {
+                    "description": "G7_IO2 channel mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "G7_IO3": {
+                    "description": "G7_IO3 channel mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "G7_IO4": {
+                    "description": "G7_IO4 channel mode",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "G8_IO1": {
+                    "description": "G8_IO1 channel mode",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "G8_IO2": {
+                    "description": "G8_IO2 channel mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "G8_IO3": {
+                    "description": "G8_IO3 channel mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "G8_IO4": {
+                    "description": "G8_IO4 channel mode",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IOGCSR": {
+              "description": "I/O group control status\n          register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "G8S": {
+                    "description": "Analog I/O group x status",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "G7S": {
+                    "description": "Analog I/O group x status",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "G6S": {
+                    "description": "Analog I/O group x status",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "G5S": {
+                    "description": "Analog I/O group x status",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "G4S": {
+                    "description": "Analog I/O group x status",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "G3S": {
+                    "description": "Analog I/O group x status",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "G2S": {
+                    "description": "Analog I/O group x status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "G1S": {
+                    "description": "Analog I/O group x status",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "G8E": {
+                    "description": "Analog I/O group x enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "G7E": {
+                    "description": "Analog I/O group x enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "G6E": {
+                    "description": "Analog I/O group x enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "G5E": {
+                    "description": "Analog I/O group x enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "G4E": {
+                    "description": "Analog I/O group x enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "G3E": {
+                    "description": "Analog I/O group x enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "G2E": {
+                    "description": "Analog I/O group x enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "G1E": {
+                    "description": "Analog I/O group x enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IOG1CR": {
+              "description": "I/O group x counter register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Counter value",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "IOG2CR": {
+              "description": "I/O group x counter register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Counter value",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "IOG3CR": {
+              "description": "I/O group x counter register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Counter value",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "IOG4CR": {
+              "description": "I/O group x counter register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Counter value",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "IOG5CR": {
+              "description": "I/O group x counter register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Counter value",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "IOG6CR": {
+              "description": "I/O group x counter register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Counter value",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "IOG7CR": {
+              "description": "I/O group x counter register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Counter value",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "IOG8CR": {
+              "description": "I/O group x counter register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Counter value",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CRC": {
+        "description": "cyclic redundancy check calculation\n      unit",
+        "children": {
+          "registers": {
+            "DR": {
+              "description": "Data register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data register bits",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "Independent data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IDR": {
+                    "description": "General-purpose 8-bit data register\n              bits",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "Control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESET": {
+                    "description": "reset bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "POLYSIZE": {
+                    "description": "Polynomial size",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "REV_IN": {
+                    "description": "Reverse input data",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "REV_OUT": {
+                    "description": "Reverse output data",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INIT": {
+              "description": "Initial CRC value",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INIT": {
+                    "description": "Programmable initial CRC\n              value",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "POL": {
+              "description": "CRC polynomial",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 79764919,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POL": {
+                    "description": "Programmable polynomial",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "Flash": {
+        "description": "Flash",
+        "children": {
+          "registers": {
+            "ACR": {
+              "description": "Flash access control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 48,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LATENCY": {
+                    "description": "LATENCY",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "PRFTBE": {
+                    "description": "PRFTBE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PRFTBS": {
+                    "description": "PRFTBS",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "KEYR": {
+              "description": "Flash key register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "FKEYR": {
+                    "description": "Flash Key",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OPTKEYR": {
+              "description": "Flash option key register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "OPTKEYR": {
+                    "description": "Option byte key",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Flash status register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EOP": {
+                    "description": "End of operation",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WRPRT": {
+                    "description": "Write protection error",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PGERR": {
+                    "description": "Programming error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BSY": {
+                    "description": "Busy",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "Flash control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FORCE_OPTLOAD": {
+                    "description": "Force option byte loading",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EOPIE": {
+                    "description": "End of operation interrupt\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OPTWRE": {
+                    "description": "Option bytes write enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LOCK": {
+                    "description": "Lock",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "STRT": {
+                    "description": "Start",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OPTER": {
+                    "description": "Option byte erase",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OPTPG": {
+                    "description": "Option byte programming",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MER": {
+                    "description": "Mass erase",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PER": {
+                    "description": "Page erase",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PG": {
+                    "description": "Programming",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AR": {
+              "description": "Flash address register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "FAR": {
+                    "description": "Flash address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OBR": {
+              "description": "Option byte register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 4294967042,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "OPTERR": {
+                    "description": "Option byte error",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LEVEL1_PROT": {
+                    "description": "Level 1 protection status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LEVEL2_PROT": {
+                    "description": "Level 2 protection status",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "WDG_SW": {
+                    "description": "WDG_SW",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "nRST_STOP": {
+                    "description": "nRST_STOP",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "nRST_STDBY": {
+                    "description": "nRST_STDBY",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BOOT1": {
+                    "description": "BOOT1",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "VDDA_MONITOR": {
+                    "description": "VDDA_MONITOR",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SRAM_PARITY_CHECK": {
+                    "description": "SRAM_PARITY_CHECK",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "Data0": {
+                    "description": "Data0",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "Data1": {
+                    "description": "Data1",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "WRPR": {
+              "description": "Write protection register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WRP": {
+                    "description": "Write protect",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RCC": {
+        "description": "Reset and clock control",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "Clock control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 131,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HSION": {
+                    "description": "Internal High Speed clock\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HSIRDY": {
+                    "description": "Internal High Speed clock ready\n              flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSITRIM": {
+                    "description": "Internal High Speed clock\n              trimming",
+                    "offset": 3,
+                    "size": 5
+                  },
+                  "HSICAL": {
+                    "description": "Internal High Speed clock\n              Calibration",
+                    "offset": 8,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "HSEON": {
+                    "description": "External High Speed clock\n              enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "HSERDY": {
+                    "description": "External High Speed clock ready\n              flag",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSEBYP": {
+                    "description": "External High Speed clock\n              Bypass",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CSSON": {
+                    "description": "Clock Security System\n              enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PLLON": {
+                    "description": "PLL enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PLLRDY": {
+                    "description": "PLL clock ready flag",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CFGR": {
+              "description": "Clock configuration register\n          (RCC_CFGR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SW": {
+                    "description": "System clock Switch",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SWS": {
+                    "description": "System Clock Switch Status",
+                    "offset": 2,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "HPRE": {
+                    "description": "AHB prescaler",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "PPRE1": {
+                    "description": "APB Low speed prescaler\n              (APB1)",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "PPRE2": {
+                    "description": "APB high speed prescaler\n              (APB2)",
+                    "offset": 11,
+                    "size": 3
+                  },
+                  "PLLSRC": {
+                    "description": "PLL entry clock source",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PLLXTPRE": {
+                    "description": "HSE divider for PLL entry",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PLLMUL": {
+                    "description": "PLL Multiplication Factor",
+                    "offset": 18,
+                    "size": 4
+                  },
+                  "USBPRES": {
+                    "description": "USB prescaler",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "MCO": {
+                    "description": "Microcontroller clock\n              output",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "MCOF": {
+                    "description": "Microcontroller Clock Output\n              Flag",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "I2SSRC": {
+                    "description": "I2S external clock source\n              selection",
+                    "offset": 23,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CIR": {
+              "description": "Clock interrupt register\n          (RCC_CIR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSIRDYF": {
+                    "description": "LSI Ready Interrupt flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSERDYF": {
+                    "description": "LSE Ready Interrupt flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSIRDYF": {
+                    "description": "HSI Ready Interrupt flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSERDYF": {
+                    "description": "HSE Ready Interrupt flag",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLLRDYF": {
+                    "description": "PLL Ready Interrupt flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CSSF": {
+                    "description": "Clock Security System Interrupt\n              flag",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSIRDYIE": {
+                    "description": "LSI Ready Interrupt Enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LSERDYIE": {
+                    "description": "LSE Ready Interrupt Enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HSIRDYIE": {
+                    "description": "HSI Ready Interrupt Enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "HSERDYIE": {
+                    "description": "HSE Ready Interrupt Enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PLLRDYIE": {
+                    "description": "PLL Ready Interrupt Enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LSIRDYC": {
+                    "description": "LSI Ready Interrupt Clear",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSERDYC": {
+                    "description": "LSE Ready Interrupt Clear",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "HSIRDYC": {
+                    "description": "HSI Ready Interrupt Clear",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "HSERDYC": {
+                    "description": "HSE Ready Interrupt Clear",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PLLRDYC": {
+                    "description": "PLL Ready Interrupt Clear",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CSSC": {
+                    "description": "Clock security system interrupt\n              clear",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "APB2RSTR": {
+              "description": "APB2 peripheral reset register\n          (RCC_APB2RSTR)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSCFGRST": {
+                    "description": "SYSCFG and COMP reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM1RST": {
+                    "description": "TIM1 timer reset",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI1RST": {
+                    "description": "SPI 1 reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIM8RST": {
+                    "description": "TIM8 timer reset",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "USART1RST": {
+                    "description": "USART1 reset",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TIM15RST": {
+                    "description": "TIM15 timer reset",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TIM16RST": {
+                    "description": "TIM16 timer reset",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TIM17RST": {
+                    "description": "TIM17 timer reset",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1RSTR": {
+              "description": "APB1 peripheral reset register\n          (RCC_APB1RSTR)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM2RST": {
+                    "description": "Timer 2 reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM3RST": {
+                    "description": "Timer 3 reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM4RST": {
+                    "description": "Timer 14 reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIM6RST": {
+                    "description": "Timer 6 reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM7RST": {
+                    "description": "Timer 7 reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WWDGRST": {
+                    "description": "Window watchdog reset",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI2RST": {
+                    "description": "SPI2 reset",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI3RST": {
+                    "description": "SPI3 reset",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "USART2RST": {
+                    "description": "USART 2 reset",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USART3RST": {
+                    "description": "USART3 reset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "UART4RST": {
+                    "description": "UART 4 reset",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UART5RST": {
+                    "description": "UART 5 reset",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2C1RST": {
+                    "description": "I2C1 reset",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "I2C2RST": {
+                    "description": "I2C2 reset",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CANRST": {
+                    "description": "CAN reset",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PWRRST": {
+                    "description": "Power interface reset",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DACRST": {
+                    "description": "DAC interface reset",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "I2C3RST": {
+                    "description": "I2C3 reset",
+                    "offset": 30,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHBENR": {
+              "description": "AHB Peripheral Clock enable register\n          (RCC_AHBENR)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 20,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAEN": {
+                    "description": "DMA1 clock enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMA2EN": {
+                    "description": "DMA2 clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SRAMEN": {
+                    "description": "SRAM interface clock\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FLITFEN": {
+                    "description": "FLITF clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FMCEN": {
+                    "description": "FMC clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CRCEN": {
+                    "description": "CRC clock enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IOPHEN": {
+                    "description": "IO port H clock enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "IOPAEN": {
+                    "description": "I/O port A clock enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "IOPBEN": {
+                    "description": "I/O port B clock enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "IOPCEN": {
+                    "description": "I/O port C clock enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IOPDEN": {
+                    "description": "I/O port D clock enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "IOPEEN": {
+                    "description": "I/O port E clock enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "IOPFEN": {
+                    "description": "I/O port F clock enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IOPGEN": {
+                    "description": "I/O port G clock enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TSCEN": {
+                    "description": "Touch sensing controller clock\n              enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "ADC12EN": {
+                    "description": "ADC1 and ADC2 clock enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ADC34EN": {
+                    "description": "ADC3 and ADC4 clock enable",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB2ENR": {
+              "description": "APB2 peripheral clock enable register\n          (RCC_APB2ENR)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSCFGEN": {
+                    "description": "SYSCFG clock enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM1EN": {
+                    "description": "TIM1 Timer clock enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI1EN": {
+                    "description": "SPI 1 clock enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIM8EN": {
+                    "description": "TIM8 Timer clock enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "USART1EN": {
+                    "description": "USART1 clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TIM15EN": {
+                    "description": "TIM15 timer clock enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TIM16EN": {
+                    "description": "TIM16 timer clock enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TIM17EN": {
+                    "description": "TIM17 timer clock enable",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1ENR": {
+              "description": "APB1 peripheral clock enable register\n          (RCC_APB1ENR)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM2EN": {
+                    "description": "Timer 2 clock enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM3EN": {
+                    "description": "Timer 3 clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM4EN": {
+                    "description": "Timer 4 clock enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIM6EN": {
+                    "description": "Timer 6 clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM7EN": {
+                    "description": "Timer 7 clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WWDGEN": {
+                    "description": "Window watchdog clock\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI2EN": {
+                    "description": "SPI 2 clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI3EN": {
+                    "description": "SPI 3 clock enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "USART2EN": {
+                    "description": "USART 2 clock enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USART3EN": {
+                    "description": "USART 3 clock enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "USART4EN": {
+                    "description": "USART 4 clock enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "USART5EN": {
+                    "description": "USART 5 clock enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2C1EN": {
+                    "description": "I2C 1 clock enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "I2C2EN": {
+                    "description": "I2C 2 clock enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "USBEN": {
+                    "description": "USB clock enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CANEN": {
+                    "description": "CAN clock enable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DAC2EN": {
+                    "description": "DAC2 interface clock\n              enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PWREN": {
+                    "description": "Power interface clock\n              enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DACEN": {
+                    "description": "DAC interface clock enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "I2C3EN": {
+                    "description": "I2C3 clock enable",
+                    "offset": 30,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BDCR": {
+              "description": "Backup domain control register\n          (RCC_BDCR)",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSEON": {
+                    "description": "External Low Speed oscillator\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LSERDY": {
+                    "description": "External Low Speed oscillator\n              ready",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSEBYP": {
+                    "description": "External Low Speed oscillator\n              bypass",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LSEDRV": {
+                    "description": "LSE oscillator drive\n              capability",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "RTCSEL": {
+                    "description": "RTC clock source selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "RTCEN": {
+                    "description": "RTC clock enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BDRST": {
+                    "description": "Backup domain software\n              reset",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CSR": {
+              "description": "Control/status register\n          (RCC_CSR)",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 201326592,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSION": {
+                    "description": "Internal low speed oscillator\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LSIRDY": {
+                    "description": "Internal low speed oscillator\n              ready",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RMVF": {
+                    "description": "Remove reset flag",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "OBLRSTF": {
+                    "description": "Option byte loader reset\n              flag",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PINRSTF": {
+                    "description": "PIN reset flag",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PORRSTF": {
+                    "description": "POR/PDR reset flag",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "SFTRSTF": {
+                    "description": "Software reset flag",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "IWDGRSTF": {
+                    "description": "Independent watchdog reset\n              flag",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "WWDGRSTF": {
+                    "description": "Window watchdog reset flag",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "LPWRRSTF": {
+                    "description": "Low-power reset flag",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHBRSTR": {
+              "description": "AHB peripheral reset register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FMCRST": {
+                    "description": "FMC reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IOPHRST": {
+                    "description": "I/O port H reset",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "IOPARST": {
+                    "description": "I/O port A reset",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "IOPBRST": {
+                    "description": "I/O port B reset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "IOPCRST": {
+                    "description": "I/O port C reset",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IOPDRST": {
+                    "description": "I/O port D reset",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "IOPERST": {
+                    "description": "I/O port E reset",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "IOPFRST": {
+                    "description": "I/O port F reset",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IOPGRST": {
+                    "description": "Touch sensing controller\n              reset",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TSCRST": {
+                    "description": "Touch sensing controller\n              reset",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "ADC12RST": {
+                    "description": "ADC1 and ADC2 reset",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ADC34RST": {
+                    "description": "ADC3 and ADC4 reset",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CFGR2": {
+              "description": "Clock configuration register 2",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PREDIV": {
+                    "description": "PREDIV division factor",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "ADC12PRES": {
+                    "description": "ADC1 and ADC2 prescaler",
+                    "offset": 4,
+                    "size": 5
+                  },
+                  "ADC34PRES": {
+                    "description": "ADC3 and ADC4 prescaler",
+                    "offset": 9,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CFGR3": {
+              "description": "Clock configuration register 3",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USART1SW": {
+                    "description": "USART1 clock source\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "I2C1SW": {
+                    "description": "I2C1 clock source\n              selection",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "I2C2SW": {
+                    "description": "I2C2 clock source\n              selection",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "I2C3SW": {
+                    "description": "I2C3 clock source\n              selection",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "USART2SW": {
+                    "description": "USART2 clock source\n              selection",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "USART3SW": {
+                    "description": "USART3 clock source\n              selection",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "TIM1SW": {
+                    "description": "Timer1 clock source\n              selection",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIM8SW": {
+                    "description": "Timer8 clock source\n              selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UART4SW": {
+                    "description": "UART4 clock source\n              selection",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "UART5SW": {
+                    "description": "UART5 clock source\n              selection",
+                    "offset": 22,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DMA1": {
+        "description": "DMA controller 1",
+        "children": {
+          "registers": {
+            "ISR": {
+              "description": "DMA interrupt status register\n          (DMA_ISR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "GIF1": {
+                    "description": "Channel 1 Global interrupt\n              flag",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIF1": {
+                    "description": "Channel 1 Transfer Complete\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIF1": {
+                    "description": "Channel 1 Half Transfer Complete\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIF1": {
+                    "description": "Channel 1 Transfer Error\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GIF2": {
+                    "description": "Channel 2 Global interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TCIF2": {
+                    "description": "Channel 2 Transfer Complete\n              flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HTIF2": {
+                    "description": "Channel 2 Half Transfer Complete\n              flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TEIF2": {
+                    "description": "Channel 2 Transfer Error\n              flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GIF3": {
+                    "description": "Channel 3 Global interrupt\n              flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TCIF3": {
+                    "description": "Channel 3 Transfer Complete\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HTIF3": {
+                    "description": "Channel 3 Half Transfer Complete\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TEIF3": {
+                    "description": "Channel 3 Transfer Error\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GIF4": {
+                    "description": "Channel 4 Global interrupt\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TCIF4": {
+                    "description": "Channel 4 Transfer Complete\n              flag",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "HTIF4": {
+                    "description": "Channel 4 Half Transfer Complete\n              flag",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TEIF4": {
+                    "description": "Channel 4 Transfer Error\n              flag",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GIF5": {
+                    "description": "Channel 5 Global interrupt\n              flag",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TCIF5": {
+                    "description": "Channel 5 Transfer Complete\n              flag",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "HTIF5": {
+                    "description": "Channel 5 Half Transfer Complete\n              flag",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TEIF5": {
+                    "description": "Channel 5 Transfer Error\n              flag",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GIF6": {
+                    "description": "Channel 6 Global interrupt\n              flag",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TCIF6": {
+                    "description": "Channel 6 Transfer Complete\n              flag",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HTIF6": {
+                    "description": "Channel 6 Half Transfer Complete\n              flag",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TEIF6": {
+                    "description": "Channel 6 Transfer Error\n              flag",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GIF7": {
+                    "description": "Channel 7 Global interrupt\n              flag",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "TCIF7": {
+                    "description": "Channel 7 Transfer Complete\n              flag",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "HTIF7": {
+                    "description": "Channel 7 Half Transfer Complete\n              flag",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TEIF7": {
+                    "description": "Channel 7 Transfer Error\n              flag",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IFCR": {
+              "description": "DMA interrupt flag clear register\n          (DMA_IFCR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CGIF1": {
+                    "description": "Channel 1 Global interrupt\n              clear",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CTCIF1": {
+                    "description": "Channel 1 Transfer Complete\n              clear",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CHTIF1": {
+                    "description": "Channel 1 Half Transfer\n              clear",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CTEIF1": {
+                    "description": "Channel 1 Transfer Error\n              clear",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CGIF2": {
+                    "description": "Channel 2 Global interrupt\n              clear",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CTCIF2": {
+                    "description": "Channel 2 Transfer Complete\n              clear",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CHTIF2": {
+                    "description": "Channel 2 Half Transfer\n              clear",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTEIF2": {
+                    "description": "Channel 2 Transfer Error\n              clear",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CGIF3": {
+                    "description": "Channel 3 Global interrupt\n              clear",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CTCIF3": {
+                    "description": "Channel 3 Transfer Complete\n              clear",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CHTIF3": {
+                    "description": "Channel 3 Half Transfer\n              clear",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CTEIF3": {
+                    "description": "Channel 3 Transfer Error\n              clear",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CGIF4": {
+                    "description": "Channel 4 Global interrupt\n              clear",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CTCIF4": {
+                    "description": "Channel 4 Transfer Complete\n              clear",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CHTIF4": {
+                    "description": "Channel 4 Half Transfer\n              clear",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTEIF4": {
+                    "description": "Channel 4 Transfer Error\n              clear",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CGIF5": {
+                    "description": "Channel 5 Global interrupt\n              clear",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CTCIF5": {
+                    "description": "Channel 5 Transfer Complete\n              clear",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "CHTIF5": {
+                    "description": "Channel 5 Half Transfer\n              clear",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CTEIF5": {
+                    "description": "Channel 5 Transfer Error\n              clear",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "CGIF6": {
+                    "description": "Channel 6 Global interrupt\n              clear",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CTCIF6": {
+                    "description": "Channel 6 Transfer Complete\n              clear",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CHTIF6": {
+                    "description": "Channel 6 Half Transfer\n              clear",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CTEIF6": {
+                    "description": "Channel 6 Transfer Error\n              clear",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CGIF7": {
+                    "description": "Channel 7 Global interrupt\n              clear",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "CTCIF7": {
+                    "description": "Channel 7 Transfer Complete\n              clear",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CHTIF7": {
+                    "description": "Channel 7 Half Transfer\n              clear",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CTEIF7": {
+                    "description": "Channel 7 Transfer Error\n              clear",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR1": {
+              "description": "DMA channel 1 number of data\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR1": {
+              "description": "DMA channel 1 peripheral address\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR1": {
+              "description": "DMA channel 1 memory address\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR2": {
+              "description": "DMA channel 2 number of data\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR2": {
+              "description": "DMA channel 2 peripheral address\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR2": {
+              "description": "DMA channel 2 memory address\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR3": {
+              "description": "DMA channel 3 number of data\n          register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR3": {
+              "description": "DMA channel 3 peripheral address\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR3": {
+              "description": "DMA channel 3 memory address\n          register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR4": {
+              "description": "DMA channel 4 number of data\n          register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR4": {
+              "description": "DMA channel 4 peripheral address\n          register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR4": {
+              "description": "DMA channel 4 memory address\n          register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR5": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR5": {
+              "description": "DMA channel 5 number of data\n          register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR5": {
+              "description": "DMA channel 5 peripheral address\n          register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR5": {
+              "description": "DMA channel 5 memory address\n          register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR6": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR6": {
+              "description": "DMA channel 6 number of data\n          register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR6": {
+              "description": "DMA channel 6 peripheral address\n          register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR6": {
+              "description": "DMA channel 6 memory address\n          register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CCR7": {
+              "description": "DMA channel configuration register\n          (DMA_CCR)",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half Transfer interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MSIZE": {
+                    "description": "Memory size",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PL": {
+                    "description": "Channel Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MEM2MEM": {
+                    "description": "Memory to memory mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNDTR7": {
+              "description": "DMA channel 7 number of data\n          register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data to transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CPAR7": {
+              "description": "DMA channel 7 peripheral address\n          register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMAR7": {
+              "description": "DMA channel 7 memory address\n          register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FPU": {
+        "description": "Floting point unit",
+        "children": {
+          "registers": {
+            "FPCCR": {
+              "description": "Floating-point context control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSPACT": {
+                    "description": "LSPACT",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USER": {
+                    "description": "USER",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "THREAD": {
+                    "description": "THREAD",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "HFRDY": {
+                    "description": "HFRDY",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MMRDY": {
+                    "description": "MMRDY",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BFRDY": {
+                    "description": "BFRDY",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MONRDY": {
+                    "description": "MONRDY",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LSPEN": {
+                    "description": "LSPEN",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "ASPEN": {
+                    "description": "ASPEN",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FPCAR": {
+              "description": "Floating-point context address\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS": {
+                    "description": "Location of unpopulated\n              floating-point",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            },
+            "FPSCR": {
+              "description": "Floating-point status control\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOC": {
+                    "description": "Invalid operation cumulative exception\n              bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DZC": {
+                    "description": "Division by zero cumulative exception\n              bit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OFC": {
+                    "description": "Overflow cumulative exception\n              bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UFC": {
+                    "description": "Underflow cumulative exception\n              bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IXC": {
+                    "description": "Inexact cumulative exception\n              bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDC": {
+                    "description": "Input denormal cumulative exception\n              bit.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RMode": {
+                    "description": "Rounding Mode control\n              field",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "FZ": {
+                    "description": "Flush-to-zero mode control\n              bit:",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "DN": {
+                    "description": "Default NaN mode control\n              bit",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "AHP": {
+                    "description": "Alternative half-precision control\n              bit",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "V": {
+                    "description": "Overflow condition code\n              flag",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "C": {
+                    "description": "Carry condition code flag",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "Z": {
+                    "description": "Zero condition code flag",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "N": {
+                    "description": "Negative condition code\n              flag",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM2": {
+        "description": "General purpose timer",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "UIFREMAP": {
+                    "description": "UIF status bit remapping",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "OCCS": {
+                    "description": "OCREF clear selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SMS_3": {
+                    "description": "Slave mode selection bit3",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "OC1FE": {
+                    "description": "Output compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OC1PE": {
+                    "description": "Output compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "Output compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1CE": {
+                    "description": "Output compare 1 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC2FE": {
+                    "description": "Output compare 2 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OC2PE": {
+                    "description": "Output compare 2 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "Output compare 2 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2CE": {
+                    "description": "Output compare 2 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC1M_3": {
+                    "description": "Output compare 1 mode bit\n              3",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OC2M_3": {
+                    "description": "Output compare 2 mode bit\n              3",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PSC": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC1PSC": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register 2 (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC3S": {
+                    "description": "Capture/Compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "OC3FE": {
+                    "description": "Output compare 3 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OC3PE": {
+                    "description": "Output compare 3 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "Output compare 3 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3CE": {
+                    "description": "Output compare 3 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC4FE": {
+                    "description": "Output compare 4 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OC4PE": {
+                    "description": "Output compare 4 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "Output compare 4 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "O24CE": {
+                    "description": "Output compare 4 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC3M_3": {
+                    "description": "Output compare 3 mode bit3",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OC4M_3": {
+                    "description": "Output compare 4 mode bit3",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/Compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNTL": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CNTH": {
+                    "description": "High counter value",
+                    "offset": 16,
+                    "size": 15
+                  },
+                  "CNT_or_UIFCPY": {
+                    "description": "if IUFREMAP=0 than CNT with read write\n              access else UIFCPY with read only\n              access",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARRL": {
+                    "description": "Low Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "ARRH": {
+                    "description": "High Auto-reload value",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1L": {
+                    "description": "Low Capture/Compare 1\n              value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CCR1H": {
+                    "description": "High Capture/Compare 1 value (on\n              TIM2)",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2L": {
+                    "description": "Low Capture/Compare 2\n              value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CCR2H": {
+                    "description": "High Capture/Compare 2 value (on\n              TIM2)",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CCR3H": {
+                    "description": "High Capture/Compare value (on\n              TIM2)",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CCR4H": {
+                    "description": "High Capture/Compare value (on\n              TIM2)",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NVIC": {
+        "description": "Nested Vectored Interrupt\n      Controller",
+        "children": {
+          "registers": {
+            "ISER0": {
+              "description": "Interrupt Set-Enable Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "SETENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISER1": {
+              "description": "Interrupt Set-Enable Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "SETENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISER2": {
+              "description": "Interrupt Set-Enable Register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "SETENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICER0": {
+              "description": "Interrupt Clear-Enable\n          Register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "CLRENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICER1": {
+              "description": "Interrupt Clear-Enable\n          Register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "CLRENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICER2": {
+              "description": "Interrupt Clear-Enable\n          Register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "CLRENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISPR0": {
+              "description": "Interrupt Set-Pending Register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "SETPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISPR1": {
+              "description": "Interrupt Set-Pending Register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "SETPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISPR2": {
+              "description": "Interrupt Set-Pending Register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "SETPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICPR0": {
+              "description": "Interrupt Clear-Pending\n          Register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "CLRPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICPR1": {
+              "description": "Interrupt Clear-Pending\n          Register",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "CLRPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICPR2": {
+              "description": "Interrupt Clear-Pending\n          Register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "CLRPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IABR0": {
+              "description": "Interrupt Active Bit Register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACTIVE": {
+                    "description": "ACTIVE",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IABR1": {
+              "description": "Interrupt Active Bit Register",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACTIVE": {
+                    "description": "ACTIVE",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IABR2": {
+              "description": "Interrupt Active Bit Register",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACTIVE": {
+                    "description": "ACTIVE",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IPR0": {
+              "description": "Interrupt Priority Register",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR1": {
+              "description": "Interrupt Priority Register",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR2": {
+              "description": "Interrupt Priority Register",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR3": {
+              "description": "Interrupt Priority Register",
+              "offset": 780,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR4": {
+              "description": "Interrupt Priority Register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR5": {
+              "description": "Interrupt Priority Register",
+              "offset": 788,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR6": {
+              "description": "Interrupt Priority Register",
+              "offset": 792,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR7": {
+              "description": "Interrupt Priority Register",
+              "offset": 796,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR8": {
+              "description": "Interrupt Priority Register",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR9": {
+              "description": "Interrupt Priority Register",
+              "offset": 804,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR10": {
+              "description": "Interrupt Priority Register",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR11": {
+              "description": "Interrupt Priority Register",
+              "offset": 812,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR12": {
+              "description": "Interrupt Priority Register",
+              "offset": 816,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR13": {
+              "description": "Interrupt Priority Register",
+              "offset": 820,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR14": {
+              "description": "Interrupt Priority Register",
+              "offset": 824,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR15": {
+              "description": "Interrupt Priority Register",
+              "offset": 828,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR16": {
+              "description": "Interrupt Priority Register",
+              "offset": 832,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR17": {
+              "description": "Interrupt Priority Register",
+              "offset": 836,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR18": {
+              "description": "Interrupt Priority Register",
+              "offset": 840,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR19": {
+              "description": "Interrupt Priority Register",
+              "offset": 844,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR20": {
+              "description": "Interrupt Priority Register",
+              "offset": 848,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FMC": {
+        "description": "Flexible memory controller",
+        "children": {
+          "registers": {
+            "BCR1": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCLKEN": {
+                    "description": "CCLKEN",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR1": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR2": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          2",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR2": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR3": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          3",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR3": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR4": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          4",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR4": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          4",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "PCR2": {
+              "description": "PC Card/NAND Flash control register\n          2",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR2": {
+              "description": "FIFO status and interrupt register\n          2",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM2": {
+              "description": "Common memory space timing register\n          2",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT2": {
+              "description": "Attribute memory space timing register\n          2",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "ATTHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "ATTHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "ATTWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "ATTSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ECCR2": {
+              "description": "ECC result register 2",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ECCx": {
+                    "description": "ECCx",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PCR3": {
+              "description": "PC Card/NAND Flash control register\n          3",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR3": {
+              "description": "FIFO status and interrupt register\n          3",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM3": {
+              "description": "Common memory space timing register\n          3",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT3": {
+              "description": "Attribute memory space timing register\n          3",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "ATTHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "ATTHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "ATTWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "ATTSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ECCR3": {
+              "description": "ECC result register 3",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ECCx": {
+                    "description": "ECCx",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PCR4": {
+              "description": "PC Card/NAND Flash control register\n          4",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR4": {
+              "description": "FIFO status and interrupt register\n          4",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM4": {
+              "description": "Common memory space timing register\n          4",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT4": {
+              "description": "Attribute memory space timing register\n          4",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "ATTHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "ATTHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "ATTWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "ATTSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PIO4": {
+              "description": "I/O space timing register 4",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOHIZx": {
+                    "description": "IOHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "IOHOLDx": {
+                    "description": "IOHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IOWAITx": {
+                    "description": "IOWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IOSETx": {
+                    "description": "IOSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BWTR1": {
+              "description": "SRAM/NOR-Flash write timing registers\n          1",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "Bus turnaround phase\n              duration",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR2": {
+              "description": "SRAM/NOR-Flash write timing registers\n          2",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "Bus turnaround phase\n              duration",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR3": {
+              "description": "SRAM/NOR-Flash write timing registers\n          3",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "Bus turnaround phase\n              duration",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR4": {
+              "description": "SRAM/NOR-Flash write timing registers\n          4",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "Bus turnaround phase\n              duration",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM15": {
+        "description": "General purpose timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "UIFREMAP": {
+                    "description": "UIF status bit remapping",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCPC": {
+                    "description": "Capture/compare preloaded\n              control",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CCUS": {
+                    "description": "Capture/compare control update\n              selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OIS1": {
+                    "description": "Output Idle state 1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OIS1N": {
+                    "description": "Output Idle state 1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OIS2": {
+                    "description": "Output Idle state 2",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SMS_3": {
+                    "description": "Slave mode selection bit 3",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "COMIE": {
+                    "description": "COM interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BIE": {
+                    "description": "Break interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "COMDE": {
+                    "description": "COM DMA request enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BIF": {
+                    "description": "Break interrupt flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMIF": {
+                    "description": "COM interrupt flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BG": {
+                    "description": "Break generation",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMG": {
+                    "description": "Capture/Compare control update\n              generation",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC2FE": {
+                    "description": "Output Compare 2 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OC2PE": {
+                    "description": "Output Compare 2 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "Output Compare 2 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC1M_3": {
+                    "description": "Output Compare 1 mode bit\n              3",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OC2M_3": {
+                    "description": "Output Compare 2 mode bit\n              3",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PSC": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC1PSC": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1NE": {
+                    "description": "Capture/Compare 1 complementary output\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "UIFCPY": {
+                    "description": "UIF copy",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RCR": {
+              "description": "repetition counter register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REP": {
+                    "description": "Repetition counter value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2": {
+                    "description": "Capture/Compare 2 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "BDTR": {
+              "description": "break and dead-time register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MOE": {
+                    "description": "Main output enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "AOE": {
+                    "description": "Automatic output enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BKP": {
+                    "description": "Break polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BKE": {
+                    "description": "Break enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OSSR": {
+                    "description": "Off-state selection for Run\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OSSI": {
+                    "description": "Off-state selection for Idle\n              mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LOCK": {
+                    "description": "Lock configuration",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "DTG": {
+                    "description": "Dead-time generator setup",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "BKF": {
+                    "description": "Break filter",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM16": {
+        "description": "General-purpose-timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "UIFREMAP": {
+                    "description": "UIF status bit remapping",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OIS1N": {
+                    "description": "Output Idle state 1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OIS1": {
+                    "description": "Output Idle state 1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CCUS": {
+                    "description": "Capture/compare control update\n              selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CCPC": {
+                    "description": "Capture/compare preloaded\n              control",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "COMIE": {
+                    "description": "COM interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BIE": {
+                    "description": "Break interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "COMDE": {
+                    "description": "COM DMA request enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BIF": {
+                    "description": "Break interrupt flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMIF": {
+                    "description": "COM interrupt flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BG": {
+                    "description": "Break generation",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMG": {
+                    "description": "Capture/Compare control update\n              generation",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1M_3": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC1PSC": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1NE": {
+                    "description": "Capture/Compare 1 complementary output\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "UIFCPY": {
+                    "description": "UIF Copy",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RCR": {
+              "description": "repetition counter register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REP": {
+                    "description": "Repetition counter value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "BDTR": {
+              "description": "break and dead-time register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DTG": {
+                    "description": "Dead-time generator setup",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "LOCK": {
+                    "description": "Lock configuration",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSSI": {
+                    "description": "Off-state selection for Idle\n              mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OSSR": {
+                    "description": "Off-state selection for Run\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BKE": {
+                    "description": "Break enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BKP": {
+                    "description": "Break polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "AOE": {
+                    "description": "Automatic output enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MOE": {
+                    "description": "Main output enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BKF": {
+                    "description": "Break filter",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OR": {
+              "description": "option register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            }
+          }
+        }
+      },
+      "TIM17": {
+        "description": "General purpose timer",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "UIFREMAP": {
+                    "description": "UIF status bit remapping",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OIS1N": {
+                    "description": "Output Idle state 1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OIS1": {
+                    "description": "Output Idle state 1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CCUS": {
+                    "description": "Capture/compare control update\n              selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CCPC": {
+                    "description": "Capture/compare preloaded\n              control",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "COMIE": {
+                    "description": "COM interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BIE": {
+                    "description": "Break interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "COMDE": {
+                    "description": "COM DMA request enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BIF": {
+                    "description": "Break interrupt flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMIF": {
+                    "description": "COM interrupt flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BG": {
+                    "description": "Break generation",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMG": {
+                    "description": "Capture/Compare control update\n              generation",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1M_3": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC1PSC": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1NE": {
+                    "description": "Capture/Compare 1 complementary output\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "UIFCPY": {
+                    "description": "UIF Copy",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RCR": {
+              "description": "repetition counter register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REP": {
+                    "description": "Repetition counter value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "BDTR": {
+              "description": "break and dead-time register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DTG": {
+                    "description": "Dead-time generator setup",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "LOCK": {
+                    "description": "Lock configuration",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSSI": {
+                    "description": "Off-state selection for Idle\n              mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OSSR": {
+                    "description": "Off-state selection for Run\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BKE": {
+                    "description": "Break enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BKP": {
+                    "description": "Break polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "AOE": {
+                    "description": "Automatic output enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MOE": {
+                    "description": "Main output enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BKF": {
+                    "description": "Break filter",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USART1": {
+        "description": "Universal synchronous asynchronous receiver\n      transmitter",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "Control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EOBIE": {
+                    "description": "End of Block interrupt\n              enable",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "RTOIE": {
+                    "description": "Receiver timeout interrupt\n              enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "DEAT": {
+                    "description": "Driver Enable assertion\n              time",
+                    "offset": 21,
+                    "size": 5
+                  },
+                  "DEDT": {
+                    "description": "Driver Enable deassertion\n              time",
+                    "offset": 16,
+                    "size": 5
+                  },
+                  "OVER8": {
+                    "description": "Oversampling mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CMIE": {
+                    "description": "Character match interrupt\n              enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MME": {
+                    "description": "Mute mode enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "M": {
+                    "description": "Word length",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAKE": {
+                    "description": "Receiver wakeup method",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PCE": {
+                    "description": "Parity control enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PS": {
+                    "description": "Parity selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PEIE": {
+                    "description": "PE interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXEIE": {
+                    "description": "interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transmission complete interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RXNE interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLEIE": {
+                    "description": "IDLE interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TE": {
+                    "description": "Transmitter enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RE": {
+                    "description": "Receiver enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UESM": {
+                    "description": "USART enable in Stop mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UE": {
+                    "description": "USART enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "Control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADD4": {
+                    "description": "Address of the USART node",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "ADD0": {
+                    "description": "Address of the USART node",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "RTOEN": {
+                    "description": "Receiver timeout enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "ABRMOD": {
+                    "description": "Auto baud rate mode",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ABREN": {
+                    "description": "Auto baud rate enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "MSBFIRST": {
+                    "description": "Most significant bit first",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DATAINV": {
+                    "description": "Binary data inversion",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TXINV": {
+                    "description": "TX pin active level\n              inversion",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RXINV": {
+                    "description": "RX pin active level\n              inversion",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SWAP": {
+                    "description": "Swap TX/RX pins",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LINEN": {
+                    "description": "LIN mode enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "STOP bits",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CLKEN": {
+                    "description": "Clock enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CPOL": {
+                    "description": "Clock polarity",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CPHA": {
+                    "description": "Clock phase",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LBCL": {
+                    "description": "Last bit clock pulse",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LBDIE": {
+                    "description": "LIN break detection interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LBDL": {
+                    "description": "LIN break detection length",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADDM7": {
+                    "description": "7-bit Address Detection/4-bit Address\n              Detection",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR3": {
+              "description": "Control register 3",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WUFIE": {
+                    "description": "Wakeup from Stop mode interrupt\n              enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "WUS": {
+                    "description": "Wakeup from Stop mode interrupt flag\n              selection",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "SCARCNT": {
+                    "description": "Smartcard auto-retry count",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "DEP": {
+                    "description": "Driver enable polarity\n              selection",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "DEM": {
+                    "description": "Driver enable mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "DDRE": {
+                    "description": "DMA Disable on Reception\n              Error",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OVRDIS": {
+                    "description": "Overrun Disable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ONEBIT": {
+                    "description": "One sample bit method\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CTSIE": {
+                    "description": "CTS interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CTSE": {
+                    "description": "CTS enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RTSE": {
+                    "description": "RTS enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DMAT": {
+                    "description": "DMA enable transmitter",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DMAR": {
+                    "description": "DMA enable receiver",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SCEN": {
+                    "description": "Smartcard mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NACK": {
+                    "description": "Smartcard NACK enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HDSEL": {
+                    "description": "Half-duplex selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IRLP": {
+                    "description": "IrDA low-power",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IrDA mode enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BRR": {
+              "description": "Baud rate register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIV_Mantissa": {
+                    "description": "mantissa of USARTDIV",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "DIV_Fraction": {
+                    "description": "fraction of USARTDIV",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "GTPR": {
+              "description": "Guard time and prescaler\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GT": {
+                    "description": "Guard time value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RTOR": {
+              "description": "Receiver timeout register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BLEN": {
+                    "description": "Block Length",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "RTO": {
+                    "description": "Receiver timeout value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "RQR": {
+              "description": "Request register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFRQ": {
+                    "description": "Transmit data flush\n              request",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RXFRQ": {
+                    "description": "Receive data flush request",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MMRQ": {
+                    "description": "Mute mode request",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SBKRQ": {
+                    "description": "Send break request",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ABRRQ": {
+                    "description": "Auto baud rate request",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ISR": {
+              "description": "Interrupt & status\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 192,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "REACK": {
+                    "description": "Receive enable acknowledge\n              flag",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TEACK": {
+                    "description": "Transmit enable acknowledge\n              flag",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "WUF": {
+                    "description": "Wakeup from Stop mode flag",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RWU": {
+                    "description": "Receiver wakeup from Mute\n              mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SBKF": {
+                    "description": "Send break flag",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CMF": {
+                    "description": "character match flag",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "Busy flag",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ABRF": {
+                    "description": "Auto baud rate flag",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ABRE": {
+                    "description": "Auto baud rate error",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOBF": {
+                    "description": "End of block flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RTOF": {
+                    "description": "Receiver timeout",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CTS": {
+                    "description": "CTS flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CTSIF": {
+                    "description": "CTS interrupt flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LBDF": {
+                    "description": "LIN break detection flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXE": {
+                    "description": "Transmit data register\n              empty",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TC": {
+                    "description": "Transmission complete",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNE": {
+                    "description": "Read data register not\n              empty",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLE": {
+                    "description": "Idle line detected",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ORE": {
+                    "description": "Overrun error",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NF": {
+                    "description": "Noise detected flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FE": {
+                    "description": "Framing error",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PE": {
+                    "description": "Parity error",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "Interrupt flag clear register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WUCF": {
+                    "description": "Wakeup from Stop mode clear\n              flag",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CMCF": {
+                    "description": "Character match clear flag",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EOBCF": {
+                    "description": "End of timeout clear flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RTOCF": {
+                    "description": "Receiver timeout clear\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CTSCF": {
+                    "description": "CTS clear flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LBDCF": {
+                    "description": "LIN break detection clear\n              flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TCCF": {
+                    "description": "Transmission complete clear\n              flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IDLECF": {
+                    "description": "Idle line detected clear\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ORECF": {
+                    "description": "Overrun error clear flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NCF": {
+                    "description": "Noise detected clear flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FECF": {
+                    "description": "Framing error clear flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PECF": {
+                    "description": "Parity error clear flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RDR": {
+              "description": "Receive data register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RDR": {
+                    "description": "Receive data value",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "TDR": {
+              "description": "Transmit data register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDR": {
+                    "description": "Transmit data value",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SYSCFG_COMP_OPAMP": {
+        "description": "System configuration controller _Comparator and\n      Operational amplifier",
+        "children": {
+          "registers": {
+            "SYSCFG_CFGR1": {
+              "description": "configuration register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_MODE": {
+                    "description": "Memory mapping selection\n              bits",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "USB_IT_RMP": {
+                    "description": "USB interrupt remap",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIM1_ITR_RMP": {
+                    "description": "Timer 1 ITR3 selection",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DAC_TRIG_RMP": {
+                    "description": "DAC trigger remap (when TSEL =\n              001)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ADC24_DMA_RMP": {
+                    "description": "ADC24 DMA remapping bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIM16_DMA_RMP": {
+                    "description": "TIM16 DMA request remapping\n              bit",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TIM17_DMA_RMP": {
+                    "description": "TIM17 DMA request remapping\n              bit",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIM6_DAC1_DMA_RMP": {
+                    "description": "TIM6 and DAC1 DMA request remapping\n              bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TIM7_DAC2_DMA_RMP": {
+                    "description": "TIM7 and DAC2 DMA request remapping\n              bit",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "I2C_PB6_FM": {
+                    "description": "Fast Mode Plus (FM+) driving capability\n              activation bits.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "I2C_PB7_FM": {
+                    "description": "Fast Mode Plus (FM+) driving capability\n              activation bits.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "I2C_PB8_FM": {
+                    "description": "Fast Mode Plus (FM+) driving capability\n              activation bits.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "I2C_PB9_FM": {
+                    "description": "Fast Mode Plus (FM+) driving capability\n              activation bits.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "I2C1_FM": {
+                    "description": "I2C1 Fast Mode Plus",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2C2_FM": {
+                    "description": "I2C2 Fast Mode Plus",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "ENCODER_MODE": {
+                    "description": "Encoder mode",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "FPU_IT": {
+                    "description": "Interrupt enable bits from\n              FPU",
+                    "offset": 26,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "SYSCFG_EXTICR1": {
+              "description": "external interrupt configuration register\n          1",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI3": {
+                    "description": "EXTI 3 configuration bits",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI2": {
+                    "description": "EXTI 2 configuration bits",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI1": {
+                    "description": "EXTI 1 configuration bits",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI0": {
+                    "description": "EXTI 0 configuration bits",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SYSCFG_EXTICR2": {
+              "description": "external interrupt configuration register\n          2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI7": {
+                    "description": "EXTI 7 configuration bits",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI6": {
+                    "description": "EXTI 6 configuration bits",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI5": {
+                    "description": "EXTI 5 configuration bits",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI4": {
+                    "description": "EXTI 4 configuration bits",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SYSCFG_EXTICR3": {
+              "description": "external interrupt configuration register\n          3",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI11": {
+                    "description": "EXTI 11 configuration bits",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI10": {
+                    "description": "EXTI 10 configuration bits",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI9": {
+                    "description": "EXTI 9 configuration bits",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI8": {
+                    "description": "EXTI 8 configuration bits",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SYSCFG_EXTICR4": {
+              "description": "external interrupt configuration register\n          4",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI15": {
+                    "description": "EXTI 15 configuration bits",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI14": {
+                    "description": "EXTI 14 configuration bits",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI13": {
+                    "description": "EXTI 13 configuration bits",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI12": {
+                    "description": "EXTI 12 configuration bits",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SYSCFG_CFGR2": {
+              "description": "configuration register 2",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOCUP_LOCK": {
+                    "description": "Cortex-M0 LOCKUP bit enable\n              bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SRAM_PARITY_LOCK": {
+                    "description": "SRAM parity lock bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PVD_LOCK": {
+                    "description": "PVD lock enable bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BYP_ADD_PAR": {
+                    "description": "Bypass address bit 29 in parity\n              calculation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SRAM_PEF": {
+                    "description": "SRAM parity flag",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SYSCFG_RCR": {
+              "description": "CCM SRAM protection register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PAGE0_WP": {
+                    "description": "CCM SRAM page write protection\n              bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PAGE1_WP": {
+                    "description": "CCM SRAM page write protection\n              bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PAGE2_WP": {
+                    "description": "CCM SRAM page write protection\n              bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PAGE3_WP": {
+                    "description": "CCM SRAM page write protection\n              bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PAGE4_WP": {
+                    "description": "CCM SRAM page write protection\n              bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PAGE5_WP": {
+                    "description": "CCM SRAM page write protection\n              bit",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PAGE6_WP": {
+                    "description": "CCM SRAM page write protection\n              bit",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PAGE7_WP": {
+                    "description": "CCM SRAM page write protection\n              bit",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMP1_CSR": {
+              "description": "control and status register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMP1EN": {
+                    "description": "Comparator 1 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "COMP1_INP_DAC": {
+                    "description": "COMP1_INP_DAC",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "COMP1MODE": {
+                    "description": "Comparator 1 mode",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "COMP1INSEL": {
+                    "description": "Comparator 1 inverting input\n              selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "COMP1_OUT_SEL": {
+                    "description": "Comparator 1 output\n              selection",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "COMP1POL": {
+                    "description": "Comparator 1 output\n              polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "COMP1HYST": {
+                    "description": "Comparator 1 hysteresis",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "COMP1_BLANKING": {
+                    "description": "Comparator 1 blanking\n              source",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "COMP1OUT": {
+                    "description": "Comparator 1 output",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "COMP1LOCK": {
+                    "description": "Comparator 1 lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMP2_CSR": {
+              "description": "control and status register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMP2EN": {
+                    "description": "Comparator 2 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "COMP2MODE": {
+                    "description": "Comparator 2 mode",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "COMP2INSEL": {
+                    "description": "Comparator 2 inverting input\n              selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "COMP2INPSEL": {
+                    "description": "Comparator 2 non inverted input\n              selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "COMP2INMSEL": {
+                    "description": "Comparator 1inverting input\n              selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "COMP2_OUT_SEL": {
+                    "description": "Comparator 2 output\n              selection",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "COMP2POL": {
+                    "description": "Comparator 2 output\n              polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "COMP2HYST": {
+                    "description": "Comparator 2 hysteresis",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "COMP2_BLANKING": {
+                    "description": "Comparator 2 blanking\n              source",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "COMP2LOCK": {
+                    "description": "Comparator 2 lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMP3_CSR": {
+              "description": "control and status register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMP3EN": {
+                    "description": "Comparator 3 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "COMP3MODE": {
+                    "description": "Comparator 3 mode",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "COMP3INSEL": {
+                    "description": "Comparator 3 inverting input\n              selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "COMP3INPSEL": {
+                    "description": "Comparator 3 non inverted input\n              selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "COMP3_OUT_SEL": {
+                    "description": "Comparator 3 output\n              selection",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "COMP3POL": {
+                    "description": "Comparator 3 output\n              polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "COMP3HYST": {
+                    "description": "Comparator 3 hysteresis",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "COMP3_BLANKING": {
+                    "description": "Comparator 3 blanking\n              source",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "COMP3OUT": {
+                    "description": "Comparator 3 output",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "COMP3LOCK": {
+                    "description": "Comparator 3 lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMP4_CSR": {
+              "description": "control and status register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMP4EN": {
+                    "description": "Comparator 4 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "COMP4MODE": {
+                    "description": "Comparator 4 mode",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "COMP4INSEL": {
+                    "description": "Comparator 4 inverting input\n              selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "COMP4INPSEL": {
+                    "description": "Comparator 4 non inverted input\n              selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "COM4WINMODE": {
+                    "description": "Comparator 4 window mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "COMP4_OUT_SEL": {
+                    "description": "Comparator 4 output\n              selection",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "COMP4POL": {
+                    "description": "Comparator 4 output\n              polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "COMP4HYST": {
+                    "description": "Comparator 4 hysteresis",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "COMP4_BLANKING": {
+                    "description": "Comparator 4 blanking\n              source",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "COMP4OUT": {
+                    "description": "Comparator 4 output",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "COMP4LOCK": {
+                    "description": "Comparator 4 lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMP5_CSR": {
+              "description": "control and status register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMP5EN": {
+                    "description": "Comparator 5 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "COMP5MODE": {
+                    "description": "Comparator 5 mode",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "COMP5INSEL": {
+                    "description": "Comparator 5 inverting input\n              selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "COMP5INPSEL": {
+                    "description": "Comparator 5 non inverted input\n              selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "COMP5_OUT_SEL": {
+                    "description": "Comparator 5 output\n              selection",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "COMP5POL": {
+                    "description": "Comparator 5 output\n              polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "COMP5HYST": {
+                    "description": "Comparator 5 hysteresis",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "COMP5_BLANKING": {
+                    "description": "Comparator 5 blanking\n              source",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "COMP5OUT": {
+                    "description": "Comparator51 output",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "COMP5LOCK": {
+                    "description": "Comparator 5 lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMP6_CSR": {
+              "description": "control and status register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMP6EN": {
+                    "description": "Comparator 6 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "COMP6MODE": {
+                    "description": "Comparator 6 mode",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "COMP6INSEL": {
+                    "description": "Comparator 6 inverting input\n              selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "COMP6INPSEL": {
+                    "description": "Comparator 6 non inverted input\n              selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "COM6WINMODE": {
+                    "description": "Comparator 6 window mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "COMP6_OUT_SEL": {
+                    "description": "Comparator 6 output\n              selection",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "COMP6POL": {
+                    "description": "Comparator 6 output\n              polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "COMP6HYST": {
+                    "description": "Comparator 6 hysteresis",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "COMP6_BLANKING": {
+                    "description": "Comparator 6 blanking\n              source",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "COMP6OUT": {
+                    "description": "Comparator 6 output",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "COMP6LOCK": {
+                    "description": "Comparator 6 lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMP7_CSR": {
+              "description": "control and status register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMP7EN": {
+                    "description": "Comparator 7 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "COMP7MODE": {
+                    "description": "Comparator 7 mode",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "COMP7INSEL": {
+                    "description": "Comparator 7 inverting input\n              selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "COMP7INPSEL": {
+                    "description": "Comparator 7 non inverted input\n              selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "COMP7_OUT_SEL": {
+                    "description": "Comparator 7 output\n              selection",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "COMP7POL": {
+                    "description": "Comparator 7 output\n              polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "COMP7HYST": {
+                    "description": "Comparator 7 hysteresis",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "COMP7_BLANKING": {
+                    "description": "Comparator 7 blanking\n              source",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "COMP7OUT": {
+                    "description": "Comparator 7 output",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "COMP7LOCK": {
+                    "description": "Comparator 7 lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OPAMP1_CSR": {
+              "description": "control register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OPAMP1_EN": {
+                    "description": "OPAMP1 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FORCE_VP": {
+                    "description": "FORCE_VP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VP_SEL": {
+                    "description": "OPAMP1 Non inverting input\n              selection",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "VM_SEL": {
+                    "description": "OPAMP1 inverting input\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "TCM_EN": {
+                    "description": "Timer controlled Mux mode\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "VMS_SEL": {
+                    "description": "OPAMP1 inverting input secondary\n              selection",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "VPS_SEL": {
+                    "description": "OPAMP1 Non inverting input secondary\n              selection",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "CALON": {
+                    "description": "Calibration mode enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CALSEL": {
+                    "description": "Calibration selection",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PGA_GAIN": {
+                    "description": "Gain in PGA mode",
+                    "offset": 14,
+                    "size": 4
+                  },
+                  "USER_TRIM": {
+                    "description": "User trimming enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TRIMOFFSETP": {
+                    "description": "Offset trimming value\n              (PMOS)",
+                    "offset": 19,
+                    "size": 5
+                  },
+                  "TRIMOFFSETN": {
+                    "description": "Offset trimming value\n              (NMOS)",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "TSTREF": {
+                    "description": "TSTREF",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "OUTCAL": {
+                    "description": "OPAMP 1 ouput status flag",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOCK": {
+                    "description": "OPAMP 1 lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OPAMP2_CSR": {
+              "description": "control register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OPAMP2EN": {
+                    "description": "OPAMP2 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FORCE_VP": {
+                    "description": "FORCE_VP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VP_SEL": {
+                    "description": "OPAMP2 Non inverting input\n              selection",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "VM_SEL": {
+                    "description": "OPAMP2 inverting input\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "TCM_EN": {
+                    "description": "Timer controlled Mux mode\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "VMS_SEL": {
+                    "description": "OPAMP2 inverting input secondary\n              selection",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "VPS_SEL": {
+                    "description": "OPAMP2 Non inverting input secondary\n              selection",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "CALON": {
+                    "description": "Calibration mode enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CAL_SEL": {
+                    "description": "Calibration selection",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PGA_GAIN": {
+                    "description": "Gain in PGA mode",
+                    "offset": 14,
+                    "size": 4
+                  },
+                  "USER_TRIM": {
+                    "description": "User trimming enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TRIMOFFSETP": {
+                    "description": "Offset trimming value\n              (PMOS)",
+                    "offset": 19,
+                    "size": 5
+                  },
+                  "TRIMOFFSETN": {
+                    "description": "Offset trimming value\n              (NMOS)",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "TSTREF": {
+                    "description": "TSTREF",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "OUTCAL": {
+                    "description": "OPAMP 2 ouput status flag",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOCK": {
+                    "description": "OPAMP 2 lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OPAMP3_CSR": {
+              "description": "control register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OPAMP3EN": {
+                    "description": "OPAMP3 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FORCE_VP": {
+                    "description": "FORCE_VP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VP_SEL": {
+                    "description": "OPAMP3 Non inverting input\n              selection",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "VM_SEL": {
+                    "description": "OPAMP3 inverting input\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "TCM_EN": {
+                    "description": "Timer controlled Mux mode\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "VMS_SEL": {
+                    "description": "OPAMP3 inverting input secondary\n              selection",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "VPS_SEL": {
+                    "description": "OPAMP3 Non inverting input secondary\n              selection",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "CALON": {
+                    "description": "Calibration mode enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CALSEL": {
+                    "description": "Calibration selection",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PGA_GAIN": {
+                    "description": "Gain in PGA mode",
+                    "offset": 14,
+                    "size": 4
+                  },
+                  "USER_TRIM": {
+                    "description": "User trimming enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TRIMOFFSETP": {
+                    "description": "Offset trimming value\n              (PMOS)",
+                    "offset": 19,
+                    "size": 5
+                  },
+                  "TRIMOFFSETN": {
+                    "description": "Offset trimming value\n              (NMOS)",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "TSTREF": {
+                    "description": "TSTREF",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "OUTCAL": {
+                    "description": "OPAMP 3 ouput status flag",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOCK": {
+                    "description": "OPAMP 3 lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OPAMP4_CSR": {
+              "description": "control register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OPAMP4EN": {
+                    "description": "OPAMP4 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FORCE_VP": {
+                    "description": "FORCE_VP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VP_SEL": {
+                    "description": "OPAMP4 Non inverting input\n              selection",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "VM_SEL": {
+                    "description": "OPAMP4 inverting input\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "TCM_EN": {
+                    "description": "Timer controlled Mux mode\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "VMS_SEL": {
+                    "description": "OPAMP4 inverting input secondary\n              selection",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "VPS_SEL": {
+                    "description": "OPAMP4 Non inverting input secondary\n              selection",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "CALON": {
+                    "description": "Calibration mode enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CALSEL": {
+                    "description": "Calibration selection",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PGA_GAIN": {
+                    "description": "Gain in PGA mode",
+                    "offset": 14,
+                    "size": 4
+                  },
+                  "USER_TRIM": {
+                    "description": "User trimming enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TRIMOFFSETP": {
+                    "description": "Offset trimming value\n              (PMOS)",
+                    "offset": 19,
+                    "size": 5
+                  },
+                  "TRIMOFFSETN": {
+                    "description": "Offset trimming value\n              (NMOS)",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "TSTREF": {
+                    "description": "TSTREF",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "OUTCAL": {
+                    "description": "OPAMP 4 ouput status flag",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOCK": {
+                    "description": "OPAMP 4 lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "IWDG": {
+        "description": "Independent watchdog",
+        "children": {
+          "registers": {
+            "KR": {
+              "description": "Key register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "KEY": {
+                    "description": "Key value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PR": {
+              "description": "Prescaler register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PR": {
+                    "description": "Prescaler divider",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "RLR": {
+              "description": "Reload register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RL": {
+                    "description": "Watchdog counter reload\n              value",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PVU": {
+                    "description": "Watchdog prescaler value\n              update",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RVU": {
+                    "description": "Watchdog counter reload value\n              update",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WVU": {
+                    "description": "Watchdog counter window value\n              update",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WINR": {
+              "description": "Window register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WIN": {
+                    "description": "Watchdog counter window\n              value",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ADC1_2": {
+        "description": "Analog-to-Digital Converter",
+        "children": {
+          "registers": {
+            "CSR": {
+              "description": "ADC Common status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ADDRDY_MST": {
+                    "description": "ADDRDY_MST",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EOSMP_MST": {
+                    "description": "EOSMP_MST",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EOC_MST": {
+                    "description": "EOC_MST",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EOS_MST": {
+                    "description": "EOS_MST",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OVR_MST": {
+                    "description": "OVR_MST",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "JEOC_MST": {
+                    "description": "JEOC_MST",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "JEOS_MST": {
+                    "description": "JEOS_MST",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AWD1_MST": {
+                    "description": "AWD1_MST",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "AWD2_MST": {
+                    "description": "AWD2_MST",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "AWD3_MST": {
+                    "description": "AWD3_MST",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "JQOVF_MST": {
+                    "description": "JQOVF_MST",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ADRDY_SLV": {
+                    "description": "ADRDY_SLV",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EOSMP_SLV": {
+                    "description": "EOSMP_SLV",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EOC_SLV": {
+                    "description": "End of regular conversion of the slave\n              ADC",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EOS_SLV": {
+                    "description": "End of regular sequence flag of the\n              slave ADC",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "OVR_SLV": {
+                    "description": "Overrun flag of the slave\n              ADC",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "JEOC_SLV": {
+                    "description": "End of injected conversion flag of the\n              slave ADC",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "JEOS_SLV": {
+                    "description": "End of injected sequence flag of the\n              slave ADC",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "AWD1_SLV": {
+                    "description": "Analog watchdog 1 flag of the slave\n              ADC",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "AWD2_SLV": {
+                    "description": "Analog watchdog 2 flag of the slave\n              ADC",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "AWD3_SLV": {
+                    "description": "Analog watchdog 3 flag of the slave\n              ADC",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "JQOVF_SLV": {
+                    "description": "Injected Context Queue Overflow flag of\n              the slave ADC",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "ADC common control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MULT": {
+                    "description": "Multi ADC mode selection",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "DELAY": {
+                    "description": "Delay between 2 sampling\n              phases",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "DMACFG": {
+                    "description": "DMA configuration (for multi-ADC\n              mode)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MDMA": {
+                    "description": "Direct memory access mode for multi ADC\n              mode",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CKMODE": {
+                    "description": "ADC clock mode",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "VREFEN": {
+                    "description": "VREFINT enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TSEN": {
+                    "description": "Temperature sensor enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "VBATEN": {
+                    "description": "VBAT enable",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CDR": {
+              "description": "ADC common regular data register for dual\n          and triple modes",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RDATA_SLV": {
+                    "description": "Regular data of the slave\n              ADC",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "RDATA_MST": {
+                    "description": "Regular data of the master\n              ADC",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "WWDG": {
+        "description": "Window watchdog",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "Control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 127,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T": {
+                    "description": "7-bit counter",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "WDGA": {
+                    "description": "Activation bit",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CFR": {
+              "description": "Configuration register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 127,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EWI": {
+                    "description": "Early wakeup interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WDGTB": {
+                    "description": "Timer base",
+                    "offset": 7,
+                    "size": 2
+                  },
+                  "W": {
+                    "description": "7-bit window value",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EWIF": {
+                    "description": "Early wakeup interrupt\n              flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI1": {
+        "description": "Serial peripheral interface/Inter-IC\n      sound",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BIDIMODE": {
+                    "description": "Bidirectional data mode\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BIDIOE": {
+                    "description": "Output enable in bidirectional\n              mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CRCEN": {
+                    "description": "Hardware CRC calculation\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CRCNEXT": {
+                    "description": "CRC transfer next",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CRCL": {
+                    "description": "CRC length",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RXONLY": {
+                    "description": "Receive only",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SSM": {
+                    "description": "Software slave management",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SSI": {
+                    "description": "Internal slave select",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LSBFIRST": {
+                    "description": "Frame format",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SPE": {
+                    "description": "SPI enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BR": {
+                    "description": "Baud rate control",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "MSTR": {
+                    "description": "Master selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CPOL": {
+                    "description": "Clock polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CPHA": {
+                    "description": "Clock phase",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDMAEN": {
+                    "description": "Rx buffer DMA enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXDMAEN": {
+                    "description": "Tx buffer DMA enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SSOE": {
+                    "description": "SS output enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "NSSP": {
+                    "description": "NSS pulse management",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FRF": {
+                    "description": "Frame format",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RX buffer not empty interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXEIE": {
+                    "description": "Tx buffer empty interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DS": {
+                    "description": "Data size",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "FRXTH": {
+                    "description": "FIFO reception threshold",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LDMA_RX": {
+                    "description": "Last DMA transfer for\n              reception",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LDMA_TX": {
+                    "description": "Last DMA transfer for\n              transmission",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXNE": {
+                    "description": "Receive buffer not empty",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXE": {
+                    "description": "Transmit buffer empty",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CHSIDE": {
+                    "description": "Channel side",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "UDR": {
+                    "description": "Underrun flag",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRCERR": {
+                    "description": "CRC error flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MODF": {
+                    "description": "Mode fault",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVR": {
+                    "description": "Overrun flag",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BSY": {
+                    "description": "Busy flag",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIFRFE": {
+                    "description": "TI frame format error",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FRLVL": {
+                    "description": "FIFO reception level",
+                    "offset": 9,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "FTLVL": {
+                    "description": "FIFO transmission level",
+                    "offset": 11,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "data register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CRCPR": {
+              "description": "CRC polynomial register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRCPOLY": {
+                    "description": "CRC polynomial register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RXCRCR": {
+              "description": "RX CRC register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RxCRC": {
+                    "description": "Rx CRC register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TXCRCR": {
+              "description": "TX CRC register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TxCRC": {
+                    "description": "Tx CRC register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "I2SCFGR": {
+              "description": "I2S configuration register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "I2SMOD": {
+                    "description": "I2S mode selection",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "I2SE": {
+                    "description": "I2S Enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "I2SCFG": {
+                    "description": "I2S configuration mode",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PCMSYNC": {
+                    "description": "PCM frame synchronization",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "I2SSTD": {
+                    "description": "I2S standard selection",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CKPOL": {
+                    "description": "Steady state clock\n              polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DATLEN": {
+                    "description": "Data length to be\n              transferred",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "CHLEN": {
+                    "description": "Channel length (number of bits per audio\n              channel)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "I2SPR": {
+              "description": "I2S prescaler register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCKOE": {
+                    "description": "Master clock output enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODD": {
+                    "description": "Odd factor for the\n              prescaler",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "I2SDIV": {
+                    "description": "I2S Linear prescaler",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RTC": {
+        "description": "Real-time clock",
+        "children": {
+          "registers": {
+            "TR": {
+              "description": "time register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PM": {
+                    "description": "AM/PM notation",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "HT": {
+                    "description": "Hour tens in BCD format",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "HU": {
+                    "description": "Hour units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "MNT": {
+                    "description": "Minute tens in BCD format",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "MNU": {
+                    "description": "Minute units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "ST": {
+                    "description": "Second tens in BCD format",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SU": {
+                    "description": "Second units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "date register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 8449,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "YT": {
+                    "description": "Year tens in BCD format",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "YU": {
+                    "description": "Year units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "WDU": {
+                    "description": "Week day units",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "MT": {
+                    "description": "Month tens in BCD format",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MU": {
+                    "description": "Month units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WCKSEL": {
+                    "description": "Wakeup clock selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "TSEDGE": {
+                    "description": "Time-stamp event active\n              edge",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "REFCKON": {
+                    "description": "Reference clock detection enable (50 or\n              60 Hz)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BYPSHAD": {
+                    "description": "Bypass the shadow\n              registers",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FMT": {
+                    "description": "Hour format",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ALRAE": {
+                    "description": "Alarm A enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ALRBE": {
+                    "description": "Alarm B enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WUTE": {
+                    "description": "Wakeup timer enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TSE": {
+                    "description": "Time stamp enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ALRAIE": {
+                    "description": "Alarm A interrupt enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ALRBIE": {
+                    "description": "Alarm B interrupt enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WUTIE": {
+                    "description": "Wakeup timer interrupt\n              enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TSIE": {
+                    "description": "Time-stamp interrupt\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ADD1H": {
+                    "description": "Add 1 hour (summer time\n              change)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SUB1H": {
+                    "description": "Subtract 1 hour (winter time\n              change)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BKP": {
+                    "description": "Backup",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "COSEL": {
+                    "description": "Calibration output\n              selection",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "POL": {
+                    "description": "Output polarity",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "OSEL": {
+                    "description": "Output selection",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "COE": {
+                    "description": "Calibration output enable",
+                    "offset": 23,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ISR": {
+              "description": "initialization and status\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ALRAWF": {
+                    "description": "Alarm A write flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ALRBWF": {
+                    "description": "Alarm B write flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WUTWF": {
+                    "description": "Wakeup timer write flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SHPF": {
+                    "description": "Shift operation pending",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "INITS": {
+                    "description": "Initialization status flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RSF": {
+                    "description": "Registers synchronization\n              flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INITF": {
+                    "description": "Initialization flag",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INIT": {
+                    "description": "Initialization mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ALRAF": {
+                    "description": "Alarm A flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ALRBF": {
+                    "description": "Alarm B flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WUTF": {
+                    "description": "Wakeup timer flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TSF": {
+                    "description": "Time-stamp flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TSOVF": {
+                    "description": "Time-stamp overflow flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TAMP1F": {
+                    "description": "Tamper detection flag",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TAMP2F": {
+                    "description": "RTC_TAMP2 detection flag",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TAMP3F": {
+                    "description": "RTC_TAMP3 detection flag",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RECALPF": {
+                    "description": "Recalibration pending Flag",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PRER": {
+              "description": "prescaler register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 8323327,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PREDIV_A": {
+                    "description": "Asynchronous prescaler\n              factor",
+                    "offset": 16,
+                    "size": 7
+                  },
+                  "PREDIV_S": {
+                    "description": "Synchronous prescaler\n              factor",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "WUTR": {
+              "description": "wakeup timer register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WUT": {
+                    "description": "Wakeup auto-reload value\n              bits",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ALRMAR": {
+              "description": "alarm A register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MSK4": {
+                    "description": "Alarm A date mask",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "WDSEL": {
+                    "description": "Week day selection",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units or day in BCD\n              format",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "MSK3": {
+                    "description": "Alarm A hours mask",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PM": {
+                    "description": "AM/PM notation",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "HT": {
+                    "description": "Hour tens in BCD format",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "HU": {
+                    "description": "Hour units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "MSK2": {
+                    "description": "Alarm A minutes mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MNT": {
+                    "description": "Minute tens in BCD format",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "MNU": {
+                    "description": "Minute units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSK1": {
+                    "description": "Alarm A seconds mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ST": {
+                    "description": "Second tens in BCD format",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SU": {
+                    "description": "Second units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "ALRMBR": {
+              "description": "alarm B register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MSK4": {
+                    "description": "Alarm B date mask",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "WDSEL": {
+                    "description": "Week day selection",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units or day in BCD\n              format",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "MSK3": {
+                    "description": "Alarm B hours mask",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PM": {
+                    "description": "AM/PM notation",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "HT": {
+                    "description": "Hour tens in BCD format",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "HU": {
+                    "description": "Hour units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "MSK2": {
+                    "description": "Alarm B minutes mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MNT": {
+                    "description": "Minute tens in BCD format",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "MNU": {
+                    "description": "Minute units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSK1": {
+                    "description": "Alarm B seconds mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ST": {
+                    "description": "Second tens in BCD format",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SU": {
+                    "description": "Second units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "WPR": {
+              "description": "write protection register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "KEY": {
+                    "description": "Write protection key",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SSR": {
+              "description": "sub second register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SS": {
+                    "description": "Sub second value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SHIFTR": {
+              "description": "shift control register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "ADD1S": {
+                    "description": "Add one second",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "SUBFS": {
+                    "description": "Subtract a fraction of a\n              second",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "TSTR": {
+              "description": "time stamp time register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SU": {
+                    "description": "Second units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "ST": {
+                    "description": "Second tens in BCD format",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "MNU": {
+                    "description": "Minute units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MNT": {
+                    "description": "Minute tens in BCD format",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "HU": {
+                    "description": "Hour units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "HT": {
+                    "description": "Hour tens in BCD format",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "PM": {
+                    "description": "AM/PM notation",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TSDR": {
+              "description": "time stamp date register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WDU": {
+                    "description": "Week day units",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "MT": {
+                    "description": "Month tens in BCD format",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MU": {
+                    "description": "Month units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TSSSR": {
+              "description": "timestamp sub second register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SS": {
+                    "description": "Sub second value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CALR": {
+              "description": "calibration register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CALP": {
+                    "description": "Increase frequency of RTC by 488.5\n              ppm",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CALW8": {
+                    "description": "Use an 8-second calibration cycle\n              period",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CALW16": {
+                    "description": "Use a 16-second calibration cycle\n              period",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CALM": {
+                    "description": "Calibration minus",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "TAFCR": {
+              "description": "tamper and alternate function configuration\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TAMP1E": {
+                    "description": "Tamper 1 detection enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TAMP1TRG": {
+                    "description": "Active level for tamper 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TAMPIE": {
+                    "description": "Tamper interrupt enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TAMP2E": {
+                    "description": "Tamper 2 detection enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TAMP2TRG": {
+                    "description": "Active level for tamper 2",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TAMP3E": {
+                    "description": "Tamper 3 detection enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TAMP3TRG": {
+                    "description": "Active level for tamper 3",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TAMPTS": {
+                    "description": "Activate timestamp on tamper detection\n              event",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TAMPFREQ": {
+                    "description": "Tamper sampling frequency",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "TAMPFLT": {
+                    "description": "Tamper filter count",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "TAMPPRCH": {
+                    "description": "Tamper precharge duration",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "TAMPPUDIS": {
+                    "description": "TAMPER pull-up disable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "PC13VALUE": {
+                    "description": "PC13 value",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PC13MODE": {
+                    "description": "PC13 mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PC14VALUE": {
+                    "description": "PC14 value",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PC14MODE": {
+                    "description": "PC 14 mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "PC15VALUE": {
+                    "description": "PC15 value",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PC15MODE": {
+                    "description": "PC15 mode",
+                    "offset": 23,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ALRMASSR": {
+              "description": "alarm A sub second register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MASKSS": {
+                    "description": "Mask the most-significant bits starting\n              at this bit",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "SS": {
+                    "description": "Sub seconds value",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "ALRMBSSR": {
+              "description": "alarm B sub second register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MASKSS": {
+                    "description": "Mask the most-significant bits starting\n              at this bit",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "SS": {
+                    "description": "Sub seconds value",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "BKP0R": {
+              "description": "backup register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP1R": {
+              "description": "backup register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP2R": {
+              "description": "backup register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP3R": {
+              "description": "backup register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP4R": {
+              "description": "backup register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP5R": {
+              "description": "backup register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP6R": {
+              "description": "backup register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP7R": {
+              "description": "backup register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP8R": {
+              "description": "backup register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP9R": {
+              "description": "backup register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP10R": {
+              "description": "backup register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP11R": {
+              "description": "backup register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP12R": {
+              "description": "backup register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP13R": {
+              "description": "backup register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP14R": {
+              "description": "backup register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP15R": {
+              "description": "backup register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP16R": {
+              "description": "backup register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP17R": {
+              "description": "backup register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP18R": {
+              "description": "backup register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP19R": {
+              "description": "backup register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP20R": {
+              "description": "backup register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP21R": {
+              "description": "backup register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP22R": {
+              "description": "backup register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP23R": {
+              "description": "backup register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP24R": {
+              "description": "backup register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP25R": {
+              "description": "backup register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP26R": {
+              "description": "backup register",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP27R": {
+              "description": "backup register",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP28R": {
+              "description": "backup register",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP29R": {
+              "description": "backup register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP30R": {
+              "description": "backup register",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP31R": {
+              "description": "backup register",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM6": {
+        "description": "Basic timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "UIFREMAP": {
+                    "description": "UIF status bit remapping",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "UIFCPY": {
+                    "description": "UIF Copy",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Low Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ADC1": {
+        "description": "Analog-to-Digital Converter",
+        "children": {
+          "registers": {
+            "ISR": {
+              "description": "interrupt and status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JQOVF": {
+                    "description": "JQOVF",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AWD3": {
+                    "description": "AWD3",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "AWD2": {
+                    "description": "AWD2",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "AWD1": {
+                    "description": "AWD1",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "JEOS": {
+                    "description": "JEOS",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "JEOC": {
+                    "description": "JEOC",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OVR": {
+                    "description": "OVR",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EOS": {
+                    "description": "EOS",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EOC": {
+                    "description": "EOC",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EOSMP": {
+                    "description": "EOSMP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ADRDY": {
+                    "description": "ADRDY",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "interrupt enable register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JQOVFIE": {
+                    "description": "JQOVFIE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AWD3IE": {
+                    "description": "AWD3IE",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "AWD2IE": {
+                    "description": "AWD2IE",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "AWD1IE": {
+                    "description": "AWD1IE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "JEOSIE": {
+                    "description": "JEOSIE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "JEOCIE": {
+                    "description": "JEOCIE",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OVRIE": {
+                    "description": "OVRIE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EOSIE": {
+                    "description": "EOSIE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EOCIE": {
+                    "description": "EOCIE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EOSMPIE": {
+                    "description": "EOSMPIE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ADRDYIE": {
+                    "description": "ADRDYIE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADCAL": {
+                    "description": "ADCAL",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "ADCALDIF": {
+                    "description": "ADCALDIF",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DEEPPWD": {
+                    "description": "DEEPPWD",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ADVREGEN": {
+                    "description": "ADVREGEN",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "JADSTP": {
+                    "description": "JADSTP",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADSTP": {
+                    "description": "ADSTP",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "JADSTART": {
+                    "description": "JADSTART",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ADSTART": {
+                    "description": "ADSTART",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ADDIS": {
+                    "description": "ADDIS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ADEN": {
+                    "description": "ADEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CFGR": {
+              "description": "configuration register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AWDCH1CH": {
+                    "description": "AWDCH1CH",
+                    "offset": 26,
+                    "size": 5
+                  },
+                  "JAUTO": {
+                    "description": "JAUTO",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "JAWD1EN": {
+                    "description": "JAWD1EN",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "AWD1EN": {
+                    "description": "AWD1EN",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "AWD1SGL": {
+                    "description": "AWD1SGL",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "JQM": {
+                    "description": "JQM",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "JDISCEN": {
+                    "description": "JDISCEN",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "DISCNUM": {
+                    "description": "DISCNUM",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "DISCEN": {
+                    "description": "DISCEN",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "AUTOFF": {
+                    "description": "AUTOFF",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "AUTDLY": {
+                    "description": "AUTDLY",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CONT": {
+                    "description": "CONT",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OVRMOD": {
+                    "description": "OVRMOD",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EXTEN": {
+                    "description": "EXTEN",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "EXTSEL": {
+                    "description": "EXTSEL",
+                    "offset": 6,
+                    "size": 4
+                  },
+                  "ALIGN": {
+                    "description": "ALIGN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RES": {
+                    "description": "RES",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "DMACFG": {
+                    "description": "DMACFG",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DMAEN": {
+                    "description": "DMAEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMPR1": {
+              "description": "sample time register 1",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMP9": {
+                    "description": "SMP9",
+                    "offset": 27,
+                    "size": 3
+                  },
+                  "SMP8": {
+                    "description": "SMP8",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "SMP7": {
+                    "description": "SMP7",
+                    "offset": 21,
+                    "size": 3
+                  },
+                  "SMP6": {
+                    "description": "SMP6",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "SMP5": {
+                    "description": "SMP5",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SMP4": {
+                    "description": "SMP4",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "SMP3": {
+                    "description": "SMP3",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "SMP2": {
+                    "description": "SMP2",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "SMP1": {
+                    "description": "SMP1",
+                    "offset": 3,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "SMPR2": {
+              "description": "sample time register 2",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMP18": {
+                    "description": "SMP18",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "SMP17": {
+                    "description": "SMP17",
+                    "offset": 21,
+                    "size": 3
+                  },
+                  "SMP16": {
+                    "description": "SMP16",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "SMP15": {
+                    "description": "SMP15",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SMP14": {
+                    "description": "SMP14",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "SMP13": {
+                    "description": "SMP13",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "SMP12": {
+                    "description": "SMP12",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "SMP11": {
+                    "description": "SMP11",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "SMP10": {
+                    "description": "SMP10",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "TR1": {
+              "description": "watchdog threshold register 1",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 268369920,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HT1": {
+                    "description": "HT1",
+                    "offset": 16,
+                    "size": 12
+                  },
+                  "LT1": {
+                    "description": "LT1",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "TR2": {
+              "description": "watchdog threshold register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 268369920,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HT2": {
+                    "description": "HT2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "LT2": {
+                    "description": "LT2",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TR3": {
+              "description": "watchdog threshold register 3",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 268369920,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HT3": {
+                    "description": "HT3",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "LT3": {
+                    "description": "LT3",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SQR1": {
+              "description": "regular sequence register 1",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ4": {
+                    "description": "SQ4",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "SQ3": {
+                    "description": "SQ3",
+                    "offset": 18,
+                    "size": 5
+                  },
+                  "SQ2": {
+                    "description": "SQ2",
+                    "offset": 12,
+                    "size": 5
+                  },
+                  "SQ1": {
+                    "description": "SQ1",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "L3": {
+                    "description": "L3",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SQR2": {
+              "description": "regular sequence register 2",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ9": {
+                    "description": "SQ9",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "SQ8": {
+                    "description": "SQ8",
+                    "offset": 18,
+                    "size": 5
+                  },
+                  "SQ7": {
+                    "description": "SQ7",
+                    "offset": 12,
+                    "size": 5
+                  },
+                  "SQ6": {
+                    "description": "SQ6",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "SQ5": {
+                    "description": "SQ5",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SQR3": {
+              "description": "regular sequence register 3",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ14": {
+                    "description": "SQ14",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "SQ13": {
+                    "description": "SQ13",
+                    "offset": 18,
+                    "size": 5
+                  },
+                  "SQ12": {
+                    "description": "SQ12",
+                    "offset": 12,
+                    "size": 5
+                  },
+                  "SQ11": {
+                    "description": "SQ11",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "SQ10": {
+                    "description": "SQ10",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SQR4": {
+              "description": "regular sequence register 4",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ16": {
+                    "description": "SQ16",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "SQ15": {
+                    "description": "SQ15",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "regular Data Register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "regularDATA": {
+                    "description": "regularDATA",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JSQR": {
+              "description": "injected sequence register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JSQ4": {
+                    "description": "JSQ4",
+                    "offset": 26,
+                    "size": 5
+                  },
+                  "JSQ3": {
+                    "description": "JSQ3",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "JSQ2": {
+                    "description": "JSQ2",
+                    "offset": 14,
+                    "size": 5
+                  },
+                  "JSQ1": {
+                    "description": "JSQ1",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "JEXTEN": {
+                    "description": "JEXTEN",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "JEXTSEL": {
+                    "description": "JEXTSEL",
+                    "offset": 2,
+                    "size": 4
+                  },
+                  "JL": {
+                    "description": "JL",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OFR1": {
+              "description": "offset register 1",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OFFSET1_EN": {
+                    "description": "OFFSET1_EN",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "OFFSET1_CH": {
+                    "description": "OFFSET1_CH",
+                    "offset": 26,
+                    "size": 5
+                  },
+                  "OFFSET1": {
+                    "description": "OFFSET1",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "OFR2": {
+              "description": "offset register 2",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OFFSET2_EN": {
+                    "description": "OFFSET2_EN",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "OFFSET2_CH": {
+                    "description": "OFFSET2_CH",
+                    "offset": 26,
+                    "size": 5
+                  },
+                  "OFFSET2": {
+                    "description": "OFFSET2",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "OFR3": {
+              "description": "offset register 3",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OFFSET3_EN": {
+                    "description": "OFFSET3_EN",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "OFFSET3_CH": {
+                    "description": "OFFSET3_CH",
+                    "offset": 26,
+                    "size": 5
+                  },
+                  "OFFSET3": {
+                    "description": "OFFSET3",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "OFR4": {
+              "description": "offset register 4",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OFFSET4_EN": {
+                    "description": "OFFSET4_EN",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "OFFSET4_CH": {
+                    "description": "OFFSET4_CH",
+                    "offset": 26,
+                    "size": 5
+                  },
+                  "OFFSET4": {
+                    "description": "OFFSET4",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JDR1": {
+              "description": "injected data register 1",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA1": {
+                    "description": "JDATA1",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR2": {
+              "description": "injected data register 2",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA2": {
+                    "description": "JDATA2",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR3": {
+              "description": "injected data register 3",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA3": {
+                    "description": "JDATA3",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR4": {
+              "description": "injected data register 4",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA4": {
+                    "description": "JDATA4",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "AWD2CR": {
+              "description": "Analog Watchdog 2 Configuration\n          Register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AWD2CH": {
+                    "description": "AWD2CH",
+                    "offset": 1,
+                    "size": 18
+                  }
+                }
+              }
+            },
+            "AWD3CR": {
+              "description": "Analog Watchdog 3 Configuration\n          Register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AWD3CH": {
+                    "description": "AWD3CH",
+                    "offset": 1,
+                    "size": 18
+                  }
+                }
+              }
+            },
+            "DIFSEL": {
+              "description": "Differential Mode Selection Register\n          2",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIFSEL_1_15": {
+                    "description": "Differential mode for channels 15 to\n              1",
+                    "offset": 1,
+                    "size": 15
+                  },
+                  "DIFSEL_16_18": {
+                    "description": "Differential mode for channels 18 to\n              16",
+                    "offset": 16,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CALFACT": {
+              "description": "Calibration Factors",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CALFACT_D": {
+                    "description": "CALFACT_D",
+                    "offset": 16,
+                    "size": 7
+                  },
+                  "CALFACT_S": {
+                    "description": "CALFACT_S",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM8": {
+        "description": "Advanced-timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "UIFREMAP": {
+                    "description": "UIF status bit remapping",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCPC": {
+                    "description": "Capture/compare preloaded\n              control",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CCUS": {
+                    "description": "Capture/compare control update\n              selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OIS1": {
+                    "description": "Output Idle state 1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OIS1N": {
+                    "description": "Output Idle state 1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OIS2": {
+                    "description": "Output Idle state 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OIS2N": {
+                    "description": "Output Idle state 2",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OIS3": {
+                    "description": "Output Idle state 3",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OIS3N": {
+                    "description": "Output Idle state 3",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OIS4": {
+                    "description": "Output Idle state 4",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OIS5": {
+                    "description": "Output Idle state 5",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OIS6": {
+                    "description": "Output Idle state 6",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "MMS2": {
+                    "description": "Master mode selection 2",
+                    "offset": 20,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "OCCS": {
+                    "description": "OCREF clear selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SMS3": {
+                    "description": "Slave mode selection bit 3",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "COMDE": {
+                    "description": "COM DMA request enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BIE": {
+                    "description": "Break interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMIE": {
+                    "description": "COM interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "COMIF": {
+                    "description": "COM interrupt flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BIF": {
+                    "description": "Break interrupt flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "B2IF": {
+                    "description": "Break 2 interrupt flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "C5IF": {
+                    "description": "Capture/Compare 5 interrupt\n              flag",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "C6IF": {
+                    "description": "Capture/Compare 6 interrupt\n              flag",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "COMG": {
+                    "description": "Capture/Compare control update\n              generation",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BG": {
+                    "description": "Break generation",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "B2G": {
+                    "description": "Break 2 generation",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "Output Compare 2 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "Output Compare 2 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "Output Compare 2 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "Output Compare 2 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "Output Compare 1 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "OC1M_3": {
+                    "description": "Output Compare 1 mode bit\n              3",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OC2M_3": {
+                    "description": "Output Compare 2 mode bit\n              3",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC1PCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC4CE": {
+                    "description": "Output compare 4 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "Output compare 4 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "Output compare 4 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "Output compare 4 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "Output compare 3 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "Output compare 3 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "Output compare 3 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "Output compare 3 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "Capture/Compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "OC3M_3": {
+                    "description": "Output Compare 3 mode bit\n              3",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OC4M_3": {
+                    "description": "Output Compare 4 mode bit\n              3",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1NE": {
+                    "description": "Capture/Compare 1 complementary output\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2NE": {
+                    "description": "Capture/Compare 2 complementary output\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3NE": {
+                    "description": "Capture/Compare 3 complementary output\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4NP": {
+                    "description": "Capture/Compare 4 output\n              Polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CC5E": {
+                    "description": "Capture/Compare 5 output\n              enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CC5P": {
+                    "description": "Capture/Compare 5 output\n              Polarity",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "CC6E": {
+                    "description": "Capture/Compare 6 output\n              enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CC6P": {
+                    "description": "Capture/Compare 6 output\n              Polarity",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "UIFCPY": {
+                    "description": "UIF copy",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RCR": {
+              "description": "repetition counter register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REP": {
+                    "description": "Repetition counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2": {
+                    "description": "Capture/Compare 2 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3": {
+                    "description": "Capture/Compare 3 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4": {
+                    "description": "Capture/Compare 3 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "BDTR": {
+              "description": "break and dead-time register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DTG": {
+                    "description": "Dead-time generator setup",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "LOCK": {
+                    "description": "Lock configuration",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSSI": {
+                    "description": "Off-state selection for Idle\n              mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OSSR": {
+                    "description": "Off-state selection for Run\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BKE": {
+                    "description": "Break enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BKP": {
+                    "description": "Break polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "AOE": {
+                    "description": "Automatic output enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MOE": {
+                    "description": "Main output enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BKF": {
+                    "description": "Break filter",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "BK2F": {
+                    "description": "Break 2 filter",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BK2E": {
+                    "description": "Break 2 enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BK2P": {
+                    "description": "Break 2 polarity",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCMR3_Output": {
+              "description": "capture/compare mode register 3 (output\n          mode)",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC5FE": {
+                    "description": "Output compare 5 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OC5PE": {
+                    "description": "Output compare 5 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC5M": {
+                    "description": "Output compare 5 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC5CE": {
+                    "description": "Output compare 5 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC6FE": {
+                    "description": "Output compare 6 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OC6PE": {
+                    "description": "Output compare 6 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC6M": {
+                    "description": "Output compare 6 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC6CE": {
+                    "description": "Output compare 6 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC5M_3": {
+                    "description": "Outout Compare 5 mode bit\n              3",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OC6M_3": {
+                    "description": "Outout Compare 6 mode bit\n              3",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR5": {
+              "description": "capture/compare register 5",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR5": {
+                    "description": "Capture/Compare 5 value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "GC5C1": {
+                    "description": "Group Channel 5 and Channel\n              1",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GC5C2": {
+                    "description": "Group Channel 5 and Channel\n              2",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GC5C3": {
+                    "description": "Group Channel 5 and Channel\n              3",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR6": {
+              "description": "capture/compare register 6",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR6": {
+                    "description": "Capture/Compare 6 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OR": {
+              "description": "option registers",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM8_ETR_ADC2_RMP": {
+                    "description": "TIM8_ETR_ADC2 remapping\n              capability",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "TIM8_ETR_ADC3_RMP": {
+                    "description": "TIM8_ETR_ADC3 remapping\n              capability",
+                    "offset": 2,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DAC": {
+        "description": "Digital-to-analog converter",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAUDRIE2": {
+                    "description": "DAC channel2 DMA underrun interrupt\n              enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DMAEN2": {
+                    "description": "DAC channel2 DMA enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "MAMP2": {
+                    "description": "DAC channel2 mask/amplitude\n              selector",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "WAVE2": {
+                    "description": "DAC channel2 noise/triangle wave\n              generation enable",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "TSEL2": {
+                    "description": "DAC channel2 trigger\n              selection",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "TEN2": {
+                    "description": "DAC channel2 trigger\n              enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BOFF2": {
+                    "description": "DAC channel2 output buffer\n              disable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EN2": {
+                    "description": "DAC channel2 enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DMAUDRIE1": {
+                    "description": "DAC channel1 DMA Underrun Interrupt\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "DMAEN1": {
+                    "description": "DAC channel1 DMA enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MAMP1": {
+                    "description": "DAC channel1 mask/amplitude\n              selector",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "WAVE1": {
+                    "description": "DAC channel1 noise/triangle wave\n              generation enable",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "TSEL1": {
+                    "description": "DAC channel1 trigger\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "TEN1": {
+                    "description": "DAC channel1 trigger\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BOFF1": {
+                    "description": "DAC channel1 output buffer\n              disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN1": {
+                    "description": "DAC channel1 enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWTRIGR": {
+              "description": "software trigger register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "SWTRIG2": {
+                    "description": "DAC channel2 software\n              trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SWTRIG1": {
+                    "description": "DAC channel1 software\n              trigger",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DHR12R1": {
+              "description": "channel1 12-bit right-aligned data holding\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12L1": {
+              "description": "channel1 12-bit left aligned data holding\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8R1": {
+              "description": "channel1 8-bit right aligned data holding\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DHR12R2": {
+              "description": "channel2 12-bit right aligned data holding\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12L2": {
+              "description": "channel2 12-bit left aligned data holding\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8R2": {
+              "description": "channel2 8-bit right-aligned data holding\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DHR12RD": {
+              "description": "Dual DAC 12-bit right-aligned data holding\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit right-aligned\n              data",
+                    "offset": 16,
+                    "size": 12
+                  },
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12LD": {
+              "description": "DUAL DAC 12-bit left aligned data holding\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit left-aligned\n              data",
+                    "offset": 20,
+                    "size": 12
+                  },
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8RD": {
+              "description": "DUAL DAC 8-bit right aligned data holding\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 8-bit right-aligned\n              data",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DACC1DHR": {
+                    "description": "DAC channel1 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DOR1": {
+              "description": "channel1 data output register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DACC1DOR": {
+                    "description": "DAC channel1 data output",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DOR2": {
+              "description": "channel2 data output register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DACC2DOR": {
+                    "description": "DAC channel2 data output",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAUDR2": {
+                    "description": "DAC channel2 DMA underrun\n              flag",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DMAUDR1": {
+                    "description": "DAC channel1 DMA underrun\n              flag",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EXTI": {
+        "description": "External interrupt/event\n      controller",
+        "children": {
+          "registers": {
+            "IMR1": {
+              "description": "Interrupt mask register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 528482304,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR0": {
+                    "description": "Interrupt Mask on line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MR1": {
+                    "description": "Interrupt Mask on line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MR2": {
+                    "description": "Interrupt Mask on line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MR3": {
+                    "description": "Interrupt Mask on line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MR4": {
+                    "description": "Interrupt Mask on line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MR5": {
+                    "description": "Interrupt Mask on line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MR6": {
+                    "description": "Interrupt Mask on line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MR7": {
+                    "description": "Interrupt Mask on line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MR8": {
+                    "description": "Interrupt Mask on line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "MR9": {
+                    "description": "Interrupt Mask on line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "MR10": {
+                    "description": "Interrupt Mask on line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "MR11": {
+                    "description": "Interrupt Mask on line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "MR12": {
+                    "description": "Interrupt Mask on line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MR13": {
+                    "description": "Interrupt Mask on line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MR14": {
+                    "description": "Interrupt Mask on line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MR15": {
+                    "description": "Interrupt Mask on line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MR16": {
+                    "description": "Interrupt Mask on line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MR17": {
+                    "description": "Interrupt Mask on line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MR18": {
+                    "description": "Interrupt Mask on line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "MR19": {
+                    "description": "Interrupt Mask on line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "MR20": {
+                    "description": "Interrupt Mask on line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "MR21": {
+                    "description": "Interrupt Mask on line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "MR22": {
+                    "description": "Interrupt Mask on line 22",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "MR23": {
+                    "description": "Interrupt Mask on line 23",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "MR24": {
+                    "description": "Interrupt Mask on line 24",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "MR25": {
+                    "description": "Interrupt Mask on line 25",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "MR26": {
+                    "description": "Interrupt Mask on line 26",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "MR27": {
+                    "description": "Interrupt Mask on line 27",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "MR28": {
+                    "description": "Interrupt Mask on line 28",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "MR29": {
+                    "description": "Interrupt Mask on line 29",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "MR30": {
+                    "description": "Interrupt Mask on line 30",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "MR31": {
+                    "description": "Interrupt Mask on line 31",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EMR1": {
+              "description": "Event mask register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR0": {
+                    "description": "Event Mask on line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MR1": {
+                    "description": "Event Mask on line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MR2": {
+                    "description": "Event Mask on line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MR3": {
+                    "description": "Event Mask on line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MR4": {
+                    "description": "Event Mask on line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MR5": {
+                    "description": "Event Mask on line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MR6": {
+                    "description": "Event Mask on line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MR7": {
+                    "description": "Event Mask on line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MR8": {
+                    "description": "Event Mask on line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "MR9": {
+                    "description": "Event Mask on line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "MR10": {
+                    "description": "Event Mask on line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "MR11": {
+                    "description": "Event Mask on line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "MR12": {
+                    "description": "Event Mask on line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MR13": {
+                    "description": "Event Mask on line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MR14": {
+                    "description": "Event Mask on line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MR15": {
+                    "description": "Event Mask on line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MR16": {
+                    "description": "Event Mask on line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MR17": {
+                    "description": "Event Mask on line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MR18": {
+                    "description": "Event Mask on line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "MR19": {
+                    "description": "Event Mask on line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "MR20": {
+                    "description": "Event Mask on line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "MR21": {
+                    "description": "Event Mask on line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "MR22": {
+                    "description": "Event Mask on line 22",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "MR23": {
+                    "description": "Event Mask on line 23",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "MR24": {
+                    "description": "Event Mask on line 24",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "MR25": {
+                    "description": "Event Mask on line 25",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "MR26": {
+                    "description": "Event Mask on line 26",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "MR27": {
+                    "description": "Event Mask on line 27",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "MR28": {
+                    "description": "Event Mask on line 28",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "MR29": {
+                    "description": "Event Mask on line 29",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "MR30": {
+                    "description": "Event Mask on line 30",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "MR31": {
+                    "description": "Event Mask on line 31",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RTSR1": {
+              "description": "Rising Trigger selection\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TR0": {
+                    "description": "Rising trigger event configuration of\n              line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TR1": {
+                    "description": "Rising trigger event configuration of\n              line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TR2": {
+                    "description": "Rising trigger event configuration of\n              line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TR3": {
+                    "description": "Rising trigger event configuration of\n              line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TR4": {
+                    "description": "Rising trigger event configuration of\n              line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TR5": {
+                    "description": "Rising trigger event configuration of\n              line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TR6": {
+                    "description": "Rising trigger event configuration of\n              line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TR7": {
+                    "description": "Rising trigger event configuration of\n              line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TR8": {
+                    "description": "Rising trigger event configuration of\n              line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TR9": {
+                    "description": "Rising trigger event configuration of\n              line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TR10": {
+                    "description": "Rising trigger event configuration of\n              line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TR11": {
+                    "description": "Rising trigger event configuration of\n              line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TR12": {
+                    "description": "Rising trigger event configuration of\n              line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TR13": {
+                    "description": "Rising trigger event configuration of\n              line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TR14": {
+                    "description": "Rising trigger event configuration of\n              line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TR15": {
+                    "description": "Rising trigger event configuration of\n              line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TR16": {
+                    "description": "Rising trigger event configuration of\n              line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TR17": {
+                    "description": "Rising trigger event configuration of\n              line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TR18": {
+                    "description": "Rising trigger event configuration of\n              line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TR19": {
+                    "description": "Rising trigger event configuration of\n              line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TR20": {
+                    "description": "Rising trigger event configuration of\n              line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TR21": {
+                    "description": "Rising trigger event configuration of\n              line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TR22": {
+                    "description": "Rising trigger event configuration of\n              line 22",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TR29": {
+                    "description": "Rising trigger event configuration of\n              line 29",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "TR30": {
+                    "description": "Rising trigger event configuration of\n              line 30",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "TR31": {
+                    "description": "Rising trigger event configuration of\n              line 31",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FTSR1": {
+              "description": "Falling Trigger selection\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TR0": {
+                    "description": "Falling trigger event configuration of\n              line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TR1": {
+                    "description": "Falling trigger event configuration of\n              line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TR2": {
+                    "description": "Falling trigger event configuration of\n              line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TR3": {
+                    "description": "Falling trigger event configuration of\n              line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TR4": {
+                    "description": "Falling trigger event configuration of\n              line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TR5": {
+                    "description": "Falling trigger event configuration of\n              line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TR6": {
+                    "description": "Falling trigger event configuration of\n              line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TR7": {
+                    "description": "Falling trigger event configuration of\n              line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TR8": {
+                    "description": "Falling trigger event configuration of\n              line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TR9": {
+                    "description": "Falling trigger event configuration of\n              line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TR10": {
+                    "description": "Falling trigger event configuration of\n              line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TR11": {
+                    "description": "Falling trigger event configuration of\n              line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TR12": {
+                    "description": "Falling trigger event configuration of\n              line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TR13": {
+                    "description": "Falling trigger event configuration of\n              line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TR14": {
+                    "description": "Falling trigger event configuration of\n              line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TR15": {
+                    "description": "Falling trigger event configuration of\n              line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TR16": {
+                    "description": "Falling trigger event configuration of\n              line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TR17": {
+                    "description": "Falling trigger event configuration of\n              line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TR18": {
+                    "description": "Falling trigger event configuration of\n              line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TR19": {
+                    "description": "Falling trigger event configuration of\n              line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TR20": {
+                    "description": "Falling trigger event configuration of\n              line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TR21": {
+                    "description": "Falling trigger event configuration of\n              line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TR22": {
+                    "description": "Falling trigger event configuration of\n              line 22",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TR29": {
+                    "description": "Falling trigger event configuration of\n              line 29",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "TR30": {
+                    "description": "Falling trigger event configuration of\n              line 30.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "TR31": {
+                    "description": "Falling trigger event configuration of\n              line 31",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWIER1": {
+              "description": "Software interrupt event\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWIER0": {
+                    "description": "Software Interrupt on line\n              0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SWIER1": {
+                    "description": "Software Interrupt on line\n              1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SWIER2": {
+                    "description": "Software Interrupt on line\n              2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SWIER3": {
+                    "description": "Software Interrupt on line\n              3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SWIER4": {
+                    "description": "Software Interrupt on line\n              4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SWIER5": {
+                    "description": "Software Interrupt on line\n              5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SWIER6": {
+                    "description": "Software Interrupt on line\n              6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SWIER7": {
+                    "description": "Software Interrupt on line\n              7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SWIER8": {
+                    "description": "Software Interrupt on line\n              8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SWIER9": {
+                    "description": "Software Interrupt on line\n              9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SWIER10": {
+                    "description": "Software Interrupt on line\n              10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SWIER11": {
+                    "description": "Software Interrupt on line\n              11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SWIER12": {
+                    "description": "Software Interrupt on line\n              12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SWIER13": {
+                    "description": "Software Interrupt on line\n              13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SWIER14": {
+                    "description": "Software Interrupt on line\n              14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SWIER15": {
+                    "description": "Software Interrupt on line\n              15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SWIER16": {
+                    "description": "Software Interrupt on line\n              16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SWIER17": {
+                    "description": "Software Interrupt on line\n              17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SWIER18": {
+                    "description": "Software Interrupt on line\n              18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "SWIER19": {
+                    "description": "Software Interrupt on line\n              19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SWIER20": {
+                    "description": "Software Interrupt on line\n              20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "SWIER21": {
+                    "description": "Software Interrupt on line\n              21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SWIER22": {
+                    "description": "Software Interrupt on line\n              22",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "SWIER29": {
+                    "description": "Software Interrupt on line\n              29",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SWIER30": {
+                    "description": "Software Interrupt on line\n              309",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SWIER31": {
+                    "description": "Software Interrupt on line\n              319",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PR1": {
+              "description": "Pending register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PR0": {
+                    "description": "Pending bit 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PR1": {
+                    "description": "Pending bit 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PR2": {
+                    "description": "Pending bit 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PR3": {
+                    "description": "Pending bit 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PR4": {
+                    "description": "Pending bit 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PR5": {
+                    "description": "Pending bit 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PR6": {
+                    "description": "Pending bit 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PR7": {
+                    "description": "Pending bit 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PR8": {
+                    "description": "Pending bit 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PR9": {
+                    "description": "Pending bit 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PR10": {
+                    "description": "Pending bit 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PR11": {
+                    "description": "Pending bit 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PR12": {
+                    "description": "Pending bit 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PR13": {
+                    "description": "Pending bit 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PR14": {
+                    "description": "Pending bit 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PR15": {
+                    "description": "Pending bit 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "PR16": {
+                    "description": "Pending bit 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PR17": {
+                    "description": "Pending bit 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PR18": {
+                    "description": "Pending bit 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PR19": {
+                    "description": "Pending bit 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PR20": {
+                    "description": "Pending bit 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PR21": {
+                    "description": "Pending bit 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "PR22": {
+                    "description": "Pending bit 22",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PR29": {
+                    "description": "Pending bit 29",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "PR30": {
+                    "description": "Pending bit 30",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PR31": {
+                    "description": "Pending bit 31",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IMR2": {
+              "description": "Interrupt mask register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 4294967292,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR32": {
+                    "description": "Interrupt Mask on external/internal line\n              32",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MR33": {
+                    "description": "Interrupt Mask on external/internal line\n              33",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MR34": {
+                    "description": "Interrupt Mask on external/internal line\n              34",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MR35": {
+                    "description": "Interrupt Mask on external/internal line\n              35",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EMR2": {
+              "description": "Event mask register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR32": {
+                    "description": "Event mask on external/internal line\n              32",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MR33": {
+                    "description": "Event mask on external/internal line\n              33",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MR34": {
+                    "description": "Event mask on external/internal line\n              34",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MR35": {
+                    "description": "Event mask on external/internal line\n              35",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RTSR2": {
+              "description": "Rising Trigger selection\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TR32": {
+                    "description": "Rising trigger event configuration bit\n              of line 32",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TR33": {
+                    "description": "Rising trigger event configuration bit\n              of line 33",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FTSR2": {
+              "description": "Falling Trigger selection\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TR32": {
+                    "description": "Falling trigger event configuration bit\n              of line 32",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TR33": {
+                    "description": "Falling trigger event configuration bit\n              of line 33",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWIER2": {
+              "description": "Software interrupt event\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWIER32": {
+                    "description": "Software interrupt on line\n              32",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SWIER33": {
+                    "description": "Software interrupt on line\n              33",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PR2": {
+              "description": "Pending register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PR32": {
+                    "description": "Pending bit on line 32",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PR33": {
+                    "description": "Pending bit on line 33",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PWR": {
+        "description": "Power control",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "power control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LPDS": {
+                    "description": "Low-power deep sleep",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PDDS": {
+                    "description": "Power down deepsleep",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CWUF": {
+                    "description": "Clear wakeup flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CSBF": {
+                    "description": "Clear standby flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PVDE": {
+                    "description": "Power voltage detector\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PLS": {
+                    "description": "PVD level selection",
+                    "offset": 5,
+                    "size": 3
+                  },
+                  "DBP": {
+                    "description": "Disable backup domain write\n              protection",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CSR": {
+              "description": "power control/status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WUF": {
+                    "description": "Wakeup flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SBF": {
+                    "description": "Standby flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PVDO": {
+                    "description": "PVD output",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EWUP1": {
+                    "description": "Enable WKUP1 pin",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EWUP2": {
+                    "description": "Enable WKUP2 pin",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CAN": {
+        "description": "Controller area network",
+        "children": {
+          "registers": {
+            "MCR": {
+              "description": "master control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 65538,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBF": {
+                    "description": "DBF",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "RESET",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TTCM": {
+                    "description": "TTCM",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ABOM": {
+                    "description": "ABOM",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AWUM": {
+                    "description": "AWUM",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NART": {
+                    "description": "NART",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RFLM": {
+                    "description": "RFLM",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXFP": {
+                    "description": "TXFP",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLEEP": {
+                    "description": "SLEEP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INRQ": {
+                    "description": "INRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MSR": {
+              "description": "master status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 3074,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX": {
+                    "description": "RX",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SAMP": {
+                    "description": "SAMP",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXM": {
+                    "description": "RXM",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXM": {
+                    "description": "TXM",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAKI": {
+                    "description": "SLAKI",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "WKUI": {
+                    "description": "WKUI",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERRI": {
+                    "description": "ERRI",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLAK": {
+                    "description": "SLAK",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INAK": {
+                    "description": "INAK",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TSR": {
+              "description": "transmit status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 469762048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOW2": {
+                    "description": "Lowest priority flag for mailbox\n              2",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOW1": {
+                    "description": "Lowest priority flag for mailbox\n              1",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOW0": {
+                    "description": "Lowest priority flag for mailbox\n              0",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME2": {
+                    "description": "Lowest priority flag for mailbox\n              2",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME1": {
+                    "description": "Lowest priority flag for mailbox\n              1",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME0": {
+                    "description": "Lowest priority flag for mailbox\n              0",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CODE": {
+                    "description": "CODE",
+                    "offset": 24,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "ABRQ2": {
+                    "description": "ABRQ2",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TERR2": {
+                    "description": "TERR2",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ALST2": {
+                    "description": "ALST2",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TXOK2": {
+                    "description": "TXOK2",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RQCP2": {
+                    "description": "RQCP2",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ABRQ1": {
+                    "description": "ABRQ1",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TERR1": {
+                    "description": "TERR1",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ALST1": {
+                    "description": "ALST1",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TXOK1": {
+                    "description": "TXOK1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RQCP1": {
+                    "description": "RQCP1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ABRQ0": {
+                    "description": "ABRQ0",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TERR0": {
+                    "description": "TERR0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ALST0": {
+                    "description": "ALST0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXOK0": {
+                    "description": "TXOK0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RQCP0": {
+                    "description": "RQCP0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RF0R": {
+              "description": "receive FIFO 0 register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFOM0": {
+                    "description": "RFOM0",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FOVR0": {
+                    "description": "FOVR0",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FULL0": {
+                    "description": "FULL0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FMP0": {
+                    "description": "FMP0",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RF1R": {
+              "description": "receive FIFO 1 register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFOM1": {
+                    "description": "RFOM1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FOVR1": {
+                    "description": "FOVR1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FULL1": {
+                    "description": "FULL1",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FMP1": {
+                    "description": "FMP1",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "interrupt enable register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLKIE": {
+                    "description": "SLKIE",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WKUIE": {
+                    "description": "WKUIE",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "ERRIE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LECIE": {
+                    "description": "LECIE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BOFIE": {
+                    "description": "BOFIE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPVIE": {
+                    "description": "EPVIE",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EWGIE": {
+                    "description": "EWGIE",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FOVIE1": {
+                    "description": "FOVIE1",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FFIE1": {
+                    "description": "FFIE1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FMPIE1": {
+                    "description": "FMPIE1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FOVIE0": {
+                    "description": "FOVIE0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FFIE0": {
+                    "description": "FFIE0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FMPIE0": {
+                    "description": "FMPIE0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TMEIE": {
+                    "description": "TMEIE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ESR": {
+              "description": "error status register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REC": {
+                    "description": "REC",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "TEC": {
+                    "description": "TEC",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "LEC": {
+                    "description": "LEC",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "BOFF": {
+                    "description": "BOFF",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPVF": {
+                    "description": "EPVF",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EWGF": {
+                    "description": "EWGF",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "BTR": {
+              "description": "bit timing register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 19070976,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SILM": {
+                    "description": "SILM",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LBKM": {
+                    "description": "LBKM",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SJW": {
+                    "description": "SJW",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "TS2": {
+                    "description": "TS2",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "TS1": {
+                    "description": "TS1",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "BRP": {
+                    "description": "BRP",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "TI0R": {
+              "description": "TX mailbox identifier register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXRQ": {
+                    "description": "TXRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TDT0R": {
+              "description": "mailbox data length control and time stamp\n          register",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TGT": {
+                    "description": "TGT",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TDL0R": {
+              "description": "mailbox data low register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TDH0R": {
+              "description": "mailbox data high register",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TI1R": {
+              "description": "TX mailbox identifier register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXRQ": {
+                    "description": "TXRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TDT1R": {
+              "description": "mailbox data length control and time stamp\n          register",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TGT": {
+                    "description": "TGT",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TDL1R": {
+              "description": "mailbox data low register",
+              "offset": 408,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TDH1R": {
+              "description": "mailbox data high register",
+              "offset": 412,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TI2R": {
+              "description": "TX mailbox identifier register",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXRQ": {
+                    "description": "TXRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TDT2R": {
+              "description": "mailbox data length control and time stamp\n          register",
+              "offset": 420,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TGT": {
+                    "description": "TGT",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TDL2R": {
+              "description": "mailbox data low register",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TDH2R": {
+              "description": "mailbox data high register",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RI0R": {
+              "description": "receive FIFO mailbox identifier\n          register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RDT0R": {
+              "description": "receive FIFO mailbox data length control and\n          time stamp register",
+              "offset": 436,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FMI": {
+                    "description": "FMI",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RDL0R": {
+              "description": "receive FIFO mailbox data low\n          register",
+              "offset": 440,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RDH0R": {
+              "description": "receive FIFO mailbox data high\n          register",
+              "offset": 444,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RI1R": {
+              "description": "receive FIFO mailbox identifier\n          register",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RDT1R": {
+              "description": "receive FIFO mailbox data length control and\n          time stamp register",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FMI": {
+                    "description": "FMI",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RDL1R": {
+              "description": "receive FIFO mailbox data low\n          register",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RDH1R": {
+              "description": "receive FIFO mailbox data high\n          register",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "FMR": {
+              "description": "filter master register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 706481665,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CAN2SB": {
+                    "description": "CAN2 start bank",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "FINIT": {
+                    "description": "Filter init mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FM1R": {
+              "description": "filter mode register",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FBM0": {
+                    "description": "Filter mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FBM1": {
+                    "description": "Filter mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FBM2": {
+                    "description": "Filter mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FBM3": {
+                    "description": "Filter mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FBM4": {
+                    "description": "Filter mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FBM5": {
+                    "description": "Filter mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FBM6": {
+                    "description": "Filter mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FBM7": {
+                    "description": "Filter mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FBM8": {
+                    "description": "Filter mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FBM9": {
+                    "description": "Filter mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FBM10": {
+                    "description": "Filter mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FBM11": {
+                    "description": "Filter mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FBM12": {
+                    "description": "Filter mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FBM13": {
+                    "description": "Filter mode",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FBM14": {
+                    "description": "Filter mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FBM15": {
+                    "description": "Filter mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FBM16": {
+                    "description": "Filter mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FBM17": {
+                    "description": "Filter mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FBM18": {
+                    "description": "Filter mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FBM19": {
+                    "description": "Filter mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FBM20": {
+                    "description": "Filter mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FBM21": {
+                    "description": "Filter mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FBM22": {
+                    "description": "Filter mode",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FBM23": {
+                    "description": "Filter mode",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FBM24": {
+                    "description": "Filter mode",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FBM25": {
+                    "description": "Filter mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FBM26": {
+                    "description": "Filter mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FBM27": {
+                    "description": "Filter mode",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS1R": {
+              "description": "filter scale register",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSC0": {
+                    "description": "Filter scale configuration",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FSC1": {
+                    "description": "Filter scale configuration",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FSC2": {
+                    "description": "Filter scale configuration",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FSC3": {
+                    "description": "Filter scale configuration",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FSC4": {
+                    "description": "Filter scale configuration",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FSC5": {
+                    "description": "Filter scale configuration",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FSC6": {
+                    "description": "Filter scale configuration",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FSC7": {
+                    "description": "Filter scale configuration",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FSC8": {
+                    "description": "Filter scale configuration",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FSC9": {
+                    "description": "Filter scale configuration",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FSC10": {
+                    "description": "Filter scale configuration",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FSC11": {
+                    "description": "Filter scale configuration",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FSC12": {
+                    "description": "Filter scale configuration",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FSC13": {
+                    "description": "Filter scale configuration",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FSC14": {
+                    "description": "Filter scale configuration",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FSC15": {
+                    "description": "Filter scale configuration",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FSC16": {
+                    "description": "Filter scale configuration",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FSC17": {
+                    "description": "Filter scale configuration",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FSC18": {
+                    "description": "Filter scale configuration",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FSC19": {
+                    "description": "Filter scale configuration",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FSC20": {
+                    "description": "Filter scale configuration",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FSC21": {
+                    "description": "Filter scale configuration",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FSC22": {
+                    "description": "Filter scale configuration",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FSC23": {
+                    "description": "Filter scale configuration",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FSC24": {
+                    "description": "Filter scale configuration",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FSC25": {
+                    "description": "Filter scale configuration",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FSC26": {
+                    "description": "Filter scale configuration",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FSC27": {
+                    "description": "Filter scale configuration",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FFA1R": {
+              "description": "filter FIFO assignment\n          register",
+              "offset": 532,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FFA0": {
+                    "description": "Filter FIFO assignment for filter\n              0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FFA1": {
+                    "description": "Filter FIFO assignment for filter\n              1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FFA2": {
+                    "description": "Filter FIFO assignment for filter\n              2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FFA3": {
+                    "description": "Filter FIFO assignment for filter\n              3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FFA4": {
+                    "description": "Filter FIFO assignment for filter\n              4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FFA5": {
+                    "description": "Filter FIFO assignment for filter\n              5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FFA6": {
+                    "description": "Filter FIFO assignment for filter\n              6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FFA7": {
+                    "description": "Filter FIFO assignment for filter\n              7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FFA8": {
+                    "description": "Filter FIFO assignment for filter\n              8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FFA9": {
+                    "description": "Filter FIFO assignment for filter\n              9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FFA10": {
+                    "description": "Filter FIFO assignment for filter\n              10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FFA11": {
+                    "description": "Filter FIFO assignment for filter\n              11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FFA12": {
+                    "description": "Filter FIFO assignment for filter\n              12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FFA13": {
+                    "description": "Filter FIFO assignment for filter\n              13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FFA14": {
+                    "description": "Filter FIFO assignment for filter\n              14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FFA15": {
+                    "description": "Filter FIFO assignment for filter\n              15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FFA16": {
+                    "description": "Filter FIFO assignment for filter\n              16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FFA17": {
+                    "description": "Filter FIFO assignment for filter\n              17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FFA18": {
+                    "description": "Filter FIFO assignment for filter\n              18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FFA19": {
+                    "description": "Filter FIFO assignment for filter\n              19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FFA20": {
+                    "description": "Filter FIFO assignment for filter\n              20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FFA21": {
+                    "description": "Filter FIFO assignment for filter\n              21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FFA22": {
+                    "description": "Filter FIFO assignment for filter\n              22",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FFA23": {
+                    "description": "Filter FIFO assignment for filter\n              23",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FFA24": {
+                    "description": "Filter FIFO assignment for filter\n              24",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FFA25": {
+                    "description": "Filter FIFO assignment for filter\n              25",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FFA26": {
+                    "description": "Filter FIFO assignment for filter\n              26",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FFA27": {
+                    "description": "Filter FIFO assignment for filter\n              27",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FA1R": {
+              "description": "CAN filter activation register",
+              "offset": 540,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FACT0": {
+                    "description": "Filter active",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FACT1": {
+                    "description": "Filter active",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FACT2": {
+                    "description": "Filter active",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FACT3": {
+                    "description": "Filter active",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FACT4": {
+                    "description": "Filter active",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FACT5": {
+                    "description": "Filter active",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FACT6": {
+                    "description": "Filter active",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FACT7": {
+                    "description": "Filter active",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FACT8": {
+                    "description": "Filter active",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACT9": {
+                    "description": "Filter active",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FACT10": {
+                    "description": "Filter active",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FACT11": {
+                    "description": "Filter active",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FACT12": {
+                    "description": "Filter active",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FACT13": {
+                    "description": "Filter active",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FACT14": {
+                    "description": "Filter active",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FACT15": {
+                    "description": "Filter active",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FACT16": {
+                    "description": "Filter active",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FACT17": {
+                    "description": "Filter active",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FACT18": {
+                    "description": "Filter active",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FACT19": {
+                    "description": "Filter active",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FACT20": {
+                    "description": "Filter active",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FACT21": {
+                    "description": "Filter active",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FACT22": {
+                    "description": "Filter active",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FACT23": {
+                    "description": "Filter active",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FACT24": {
+                    "description": "Filter active",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FACT25": {
+                    "description": "Filter active",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FACT26": {
+                    "description": "Filter active",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FACT27": {
+                    "description": "Filter active",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F0R1": {
+              "description": "Filter bank 0 register 1",
+              "offset": 576,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F0R2": {
+              "description": "Filter bank 0 register 2",
+              "offset": 580,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F1R1": {
+              "description": "Filter bank 1 register 1",
+              "offset": 584,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F1R2": {
+              "description": "Filter bank 1 register 2",
+              "offset": 588,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F2R1": {
+              "description": "Filter bank 2 register 1",
+              "offset": 592,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F2R2": {
+              "description": "Filter bank 2 register 2",
+              "offset": 596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F3R1": {
+              "description": "Filter bank 3 register 1",
+              "offset": 600,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F3R2": {
+              "description": "Filter bank 3 register 2",
+              "offset": 604,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F4R1": {
+              "description": "Filter bank 4 register 1",
+              "offset": 608,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F4R2": {
+              "description": "Filter bank 4 register 2",
+              "offset": 612,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F5R1": {
+              "description": "Filter bank 5 register 1",
+              "offset": 616,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F5R2": {
+              "description": "Filter bank 5 register 2",
+              "offset": 620,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F6R1": {
+              "description": "Filter bank 6 register 1",
+              "offset": 624,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F6R2": {
+              "description": "Filter bank 6 register 2",
+              "offset": 628,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F7R1": {
+              "description": "Filter bank 7 register 1",
+              "offset": 632,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F7R2": {
+              "description": "Filter bank 7 register 2",
+              "offset": 636,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F8R1": {
+              "description": "Filter bank 8 register 1",
+              "offset": 640,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F8R2": {
+              "description": "Filter bank 8 register 2",
+              "offset": 644,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F9R1": {
+              "description": "Filter bank 9 register 1",
+              "offset": 648,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F9R2": {
+              "description": "Filter bank 9 register 2",
+              "offset": 652,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F10R1": {
+              "description": "Filter bank 10 register 1",
+              "offset": 656,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F10R2": {
+              "description": "Filter bank 10 register 2",
+              "offset": 660,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F11R1": {
+              "description": "Filter bank 11 register 1",
+              "offset": 664,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F11R2": {
+              "description": "Filter bank 11 register 2",
+              "offset": 668,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F12R1": {
+              "description": "Filter bank 4 register 1",
+              "offset": 672,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F12R2": {
+              "description": "Filter bank 12 register 2",
+              "offset": 676,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F13R1": {
+              "description": "Filter bank 13 register 1",
+              "offset": 680,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F13R2": {
+              "description": "Filter bank 13 register 2",
+              "offset": 684,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F14R1": {
+              "description": "Filter bank 14 register 1",
+              "offset": 688,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F14R2": {
+              "description": "Filter bank 14 register 2",
+              "offset": 692,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F15R1": {
+              "description": "Filter bank 15 register 1",
+              "offset": 696,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F15R2": {
+              "description": "Filter bank 15 register 2",
+              "offset": 700,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F16R1": {
+              "description": "Filter bank 16 register 1",
+              "offset": 704,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F16R2": {
+              "description": "Filter bank 16 register 2",
+              "offset": 708,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F17R1": {
+              "description": "Filter bank 17 register 1",
+              "offset": 712,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F17R2": {
+              "description": "Filter bank 17 register 2",
+              "offset": 716,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F18R1": {
+              "description": "Filter bank 18 register 1",
+              "offset": 720,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F18R2": {
+              "description": "Filter bank 18 register 2",
+              "offset": 724,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F19R1": {
+              "description": "Filter bank 19 register 1",
+              "offset": 728,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F19R2": {
+              "description": "Filter bank 19 register 2",
+              "offset": 732,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F20R1": {
+              "description": "Filter bank 20 register 1",
+              "offset": 736,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F20R2": {
+              "description": "Filter bank 20 register 2",
+              "offset": 740,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F21R1": {
+              "description": "Filter bank 21 register 1",
+              "offset": 744,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F21R2": {
+              "description": "Filter bank 21 register 2",
+              "offset": 748,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F22R1": {
+              "description": "Filter bank 22 register 1",
+              "offset": 752,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F22R2": {
+              "description": "Filter bank 22 register 2",
+              "offset": 756,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F23R1": {
+              "description": "Filter bank 23 register 1",
+              "offset": 760,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F23R2": {
+              "description": "Filter bank 23 register 2",
+              "offset": 764,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F24R1": {
+              "description": "Filter bank 24 register 1",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F24R2": {
+              "description": "Filter bank 24 register 2",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F25R1": {
+              "description": "Filter bank 25 register 1",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F25R2": {
+              "description": "Filter bank 25 register 2",
+              "offset": 780,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F26R1": {
+              "description": "Filter bank 26 register 1",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F26R2": {
+              "description": "Filter bank 26 register 2",
+              "offset": 788,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F27R1": {
+              "description": "Filter bank 27 register 1",
+              "offset": 792,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F27R2": {
+              "description": "Filter bank 27 register 2",
+              "offset": 796,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USB_FS": {
+        "description": "Universal serial bus full-speed device\n      interface",
+        "children": {
+          "registers": {
+            "USB_EP0R": {
+              "description": "endpoint 0 register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USB_EP1R": {
+              "description": "endpoint 1 register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USB_EP2R": {
+              "description": "endpoint 2 register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USB_EP3R": {
+              "description": "endpoint 3 register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USB_EP4R": {
+              "description": "endpoint 4 register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USB_EP5R": {
+              "description": "endpoint 5 register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USB_EP6R": {
+              "description": "endpoint 6 register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USB_EP7R": {
+              "description": "endpoint 7 register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EA": {
+                    "description": "Endpoint address",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "STAT_TX": {
+                    "description": "Status bits, for transmission\n              transfers",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DTOG_TX": {
+                    "description": "Data Toggle, for transmission\n              transfers",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTR_TX": {
+                    "description": "Correct Transfer for\n              transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_KIND": {
+                    "description": "Endpoint kind",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_TYPE": {
+                    "description": "Endpoint type",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SETUP": {
+                    "description": "Setup transaction\n              completed",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STAT_RX": {
+                    "description": "Status bits, for reception\n              transfers",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DTOG_RX": {
+                    "description": "Data Toggle, for reception\n              transfers",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR_RX": {
+                    "description": "Correct transfer for\n              reception",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USB_CNTR": {
+              "description": "control register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRES": {
+                    "description": "Force USB Reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PDWN": {
+                    "description": "Power down",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LPMODE": {
+                    "description": "Low-power mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FSUSP": {
+                    "description": "Force suspend",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESUME": {
+                    "description": "Resume request",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ESOFM": {
+                    "description": "Expected start of frame interrupt\n              mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SOFM": {
+                    "description": "Start of frame interrupt\n              mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESETM": {
+                    "description": "USB reset interrupt mask",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SUSPM": {
+                    "description": "Suspend mode interrupt\n              mask",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WKUPM": {
+                    "description": "Wakeup interrupt mask",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ERRM": {
+                    "description": "Error interrupt mask",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PMAOVRM": {
+                    "description": "Packet memory area over / underrun\n              interrupt mask",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTRM": {
+                    "description": "Correct transfer interrupt\n              mask",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ISTR": {
+              "description": "interrupt status register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EP_ID": {
+                    "description": "Endpoint Identifier",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "DIR": {
+                    "description": "Direction of transaction",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ESOF": {
+                    "description": "Expected start frame",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SOF": {
+                    "description": "start of frame",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "reset request",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SUSP": {
+                    "description": "Suspend mode request",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WKUP": {
+                    "description": "Wakeup",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ERR": {
+                    "description": "Error",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PMAOVR": {
+                    "description": "Packet memory area over /\n              underrun",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CTR": {
+                    "description": "Correct transfer",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FNR": {
+              "description": "frame number register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FN": {
+                    "description": "Frame number",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "LSOF": {
+                    "description": "Lost SOF",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "LCK": {
+                    "description": "Locked",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RXDM": {
+                    "description": "Receive data - line status",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RXDP": {
+                    "description": "Receive data + line status",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DADDR": {
+              "description": "device address",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADD": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ADD1": {
+                    "description": "Device address",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ADD2": {
+                    "description": "Device address",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ADD3": {
+                    "description": "Device address",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ADD4": {
+                    "description": "Device address",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ADD5": {
+                    "description": "Device address",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADD6": {
+                    "description": "Device address",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EF": {
+                    "description": "Enable function",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTABLE": {
+              "description": "Buffer table address",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BTABLE": {
+                    "description": "Buffer table",
+                    "offset": 3,
+                    "size": 13
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2C1": {
+        "description": "Inter-integrated circuit",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "Control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PE": {
+                    "description": "Peripheral enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXIE": {
+                    "description": "TX Interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXIE": {
+                    "description": "RX Interrupt enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ADDRIE": {
+                    "description": "Address match interrupt enable (slave\n              only)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NACKIE": {
+                    "description": "Not acknowledge received interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STOPIE": {
+                    "description": "STOP detection Interrupt\n              enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer Complete interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupts enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DNF": {
+                    "description": "Digital noise filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "ANFOFF": {
+                    "description": "Analog noise filter OFF",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SWRST": {
+                    "description": "Software reset",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXDMAEN": {
+                    "description": "DMA transmission requests\n              enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RXDMAEN": {
+                    "description": "DMA reception requests\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SBC": {
+                    "description": "Slave byte control",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "NOSTRETCH": {
+                    "description": "Clock stretching disable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WUPEN": {
+                    "description": "Wakeup from STOP enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GCEN": {
+                    "description": "General call enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SMBHEN": {
+                    "description": "SMBus Host address enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "SMBDEN": {
+                    "description": "SMBus Device Default address\n              enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "ALERTEN": {
+                    "description": "SMBUS alert enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PECEN": {
+                    "description": "PEC enable",
+                    "offset": 23,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "Control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PECBYTE": {
+                    "description": "Packet error checking byte",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "AUTOEND": {
+                    "description": "Automatic end mode (master\n              mode)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "RELOAD": {
+                    "description": "NBYTES reload mode",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "NBYTES": {
+                    "description": "Number of bytes",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "NACK": {
+                    "description": "NACK generation (slave\n              mode)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "Stop generation (master\n              mode)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "START": {
+                    "description": "Start generation",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "HEAD10R": {
+                    "description": "10-bit address header only read\n              direction (master receiver mode)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ADD10": {
+                    "description": "10-bit addressing mode (master\n              mode)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RD_WRN": {
+                    "description": "Transfer direction (master\n              mode)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SADD8": {
+                    "description": "Slave address bit 9:8 (master\n              mode)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "SADD1": {
+                    "description": "Slave address bit 7:1 (master\n              mode)",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "SADD0": {
+                    "description": "Slave address bit 0 (master\n              mode)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OAR1": {
+              "description": "Own address register 1",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OA1_0": {
+                    "description": "Interface address",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "OA1_1": {
+                    "description": "Interface address",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "OA1_8": {
+                    "description": "Interface address",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OA1MODE": {
+                    "description": "Own Address 1 10-bit mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OA1EN": {
+                    "description": "Own Address 1 enable",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OAR2": {
+              "description": "Own address register 2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OA2": {
+                    "description": "Interface address",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "OA2MSK": {
+                    "description": "Own Address 2 masks",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "OA2EN": {
+                    "description": "Own Address 2 enable",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TIMINGR": {
+              "description": "Timing register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCLL": {
+                    "description": "SCL low period (master\n              mode)",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SCLH": {
+                    "description": "SCL high period (master\n              mode)",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "SDADEL": {
+                    "description": "Data hold time",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "SCLDEL": {
+                    "description": "Data setup time",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "PRESC": {
+                    "description": "Timing prescaler",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TIMEOUTR": {
+              "description": "Status register 1",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMEOUTA": {
+                    "description": "Bus timeout A",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "TIDLE": {
+                    "description": "Idle clock timeout\n              detection",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIMOUTEN": {
+                    "description": "Clock timeout enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TIMEOUTB": {
+                    "description": "Bus timeout B",
+                    "offset": 16,
+                    "size": 12
+                  },
+                  "TEXTEN": {
+                    "description": "Extended clock timeout\n              enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ISR": {
+              "description": "Interrupt and Status register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDCODE": {
+                    "description": "Address match code (Slave\n              mode)",
+                    "offset": 17,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "DIR": {
+                    "description": "Transfer direction (Slave\n              mode)",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUSY": {
+                    "description": "Bus busy",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ALERT": {
+                    "description": "SMBus alert",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIMEOUT": {
+                    "description": "Timeout or t_low detection\n              flag",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PECERR": {
+                    "description": "PEC Error in reception",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVR": {
+                    "description": "Overrun/Underrun (slave\n              mode)",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ARLO": {
+                    "description": "Arbitration lost",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BERR": {
+                    "description": "Bus error",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TCR": {
+                    "description": "Transfer Complete Reload",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TC": {
+                    "description": "Transfer Complete (master\n              mode)",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STOPF": {
+                    "description": "Stop detection flag",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NACKF": {
+                    "description": "Not acknowledge received\n              flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ADDR": {
+                    "description": "Address matched (slave\n              mode)",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXNE": {
+                    "description": "Receive data register not empty\n              (receivers)",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXIS": {
+                    "description": "Transmit interrupt status\n              (transmitters)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXE": {
+                    "description": "Transmit data register empty\n              (transmitters)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "Interrupt clear register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "ALERTCF": {
+                    "description": "Alert flag clear",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TIMOUTCF": {
+                    "description": "Timeout detection flag\n              clear",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PECCF": {
+                    "description": "PEC Error flag clear",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OVRCF": {
+                    "description": "Overrun/Underrun flag\n              clear",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ARLOCF": {
+                    "description": "Arbitration lost flag\n              clear",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BERRCF": {
+                    "description": "Bus error flag clear",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "STOPCF": {
+                    "description": "Stop detection flag clear",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NACKCF": {
+                    "description": "Not Acknowledge flag clear",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ADDRCF": {
+                    "description": "Address Matched flag clear",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PECR": {
+              "description": "PEC register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PEC": {
+                    "description": "Packet error checking\n              register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RXDR": {
+              "description": "Receive data register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXDATA": {
+                    "description": "8-bit receive data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXDR": {
+              "description": "Transmit data register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXDATA": {
+                    "description": "8-bit transmit data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM1": {
+        "description": "Advanced timer",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "UIFREMAP": {
+                    "description": "UIF status bit remapping",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCPC": {
+                    "description": "Capture/compare preloaded\n              control",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CCUS": {
+                    "description": "Capture/compare control update\n              selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OIS1": {
+                    "description": "Output Idle state 1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OIS1N": {
+                    "description": "Output Idle state 1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OIS2": {
+                    "description": "Output Idle state 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OIS2N": {
+                    "description": "Output Idle state 2",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OIS3": {
+                    "description": "Output Idle state 3",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OIS3N": {
+                    "description": "Output Idle state 3",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OIS4": {
+                    "description": "Output Idle state 4",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OIS5": {
+                    "description": "Output Idle state 5",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OIS6": {
+                    "description": "Output Idle state 6",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "MMS2": {
+                    "description": "Master mode selection 2",
+                    "offset": 20,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "OCCS": {
+                    "description": "OCREF clear selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SMS3": {
+                    "description": "Slave mode selection bit 3",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "COMDE": {
+                    "description": "COM DMA request enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BIE": {
+                    "description": "Break interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMIE": {
+                    "description": "COM interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "COMIF": {
+                    "description": "COM interrupt flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BIF": {
+                    "description": "Break interrupt flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "B2IF": {
+                    "description": "Break 2 interrupt flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "C5IF": {
+                    "description": "Capture/Compare 5 interrupt\n              flag",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "C6IF": {
+                    "description": "Capture/Compare 6 interrupt\n              flag",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "COMG": {
+                    "description": "Capture/Compare control update\n              generation",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BG": {
+                    "description": "Break generation",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "B2G": {
+                    "description": "Break 2 generation",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "Output Compare 2 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "Output Compare 2 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "Output Compare 2 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "Output Compare 2 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "Output Compare 1 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "OC1M_3": {
+                    "description": "Output Compare 1 mode bit\n              3",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OC2M_3": {
+                    "description": "Output Compare 2 mode bit\n              3",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC1PCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC4CE": {
+                    "description": "Output compare 4 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "Output compare 4 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "Output compare 4 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "Output compare 4 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "Output compare 3 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "Output compare 3 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "Output compare 3 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "Output compare 3 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "Capture/Compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "OC3M_3": {
+                    "description": "Output Compare 3 mode bit\n              3",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OC4M_3": {
+                    "description": "Output Compare 4 mode bit\n              3",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1NE": {
+                    "description": "Capture/Compare 1 complementary output\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2NE": {
+                    "description": "Capture/Compare 2 complementary output\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3NE": {
+                    "description": "Capture/Compare 3 complementary output\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4NP": {
+                    "description": "Capture/Compare 4 output\n              Polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CC5E": {
+                    "description": "Capture/Compare 5 output\n              enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CC5P": {
+                    "description": "Capture/Compare 5 output\n              Polarity",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "CC6E": {
+                    "description": "Capture/Compare 6 output\n              enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CC6P": {
+                    "description": "Capture/Compare 6 output\n              Polarity",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "UIFCPY": {
+                    "description": "UIF copy",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RCR": {
+              "description": "repetition counter register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REP": {
+                    "description": "Repetition counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2": {
+                    "description": "Capture/Compare 2 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3": {
+                    "description": "Capture/Compare 3 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4": {
+                    "description": "Capture/Compare 3 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "BDTR": {
+              "description": "break and dead-time register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DTG": {
+                    "description": "Dead-time generator setup",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "LOCK": {
+                    "description": "Lock configuration",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSSI": {
+                    "description": "Off-state selection for Idle\n              mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OSSR": {
+                    "description": "Off-state selection for Run\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BKE": {
+                    "description": "Break enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BKP": {
+                    "description": "Break polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "AOE": {
+                    "description": "Automatic output enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MOE": {
+                    "description": "Main output enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BKF": {
+                    "description": "Break filter",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "BK2F": {
+                    "description": "Break 2 filter",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BK2E": {
+                    "description": "Break 2 enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BK2P": {
+                    "description": "Break 2 polarity",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCMR3_Output": {
+              "description": "capture/compare mode register 3 (output\n          mode)",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC5FE": {
+                    "description": "Output compare 5 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OC5PE": {
+                    "description": "Output compare 5 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC5M": {
+                    "description": "Output compare 5 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC5CE": {
+                    "description": "Output compare 5 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC6FE": {
+                    "description": "Output compare 6 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OC6PE": {
+                    "description": "Output compare 6 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC6M": {
+                    "description": "Output compare 6 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC6CE": {
+                    "description": "Output compare 6 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC5M_3": {
+                    "description": "Outout Compare 5 mode bit\n              3",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OC6M_3": {
+                    "description": "Outout Compare 6 mode bit\n              3",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR5": {
+              "description": "capture/compare register 5",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR5": {
+                    "description": "Capture/Compare 5 value",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "GC5C1": {
+                    "description": "Group Channel 5 and Channel\n              1",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GC5C2": {
+                    "description": "Group Channel 5 and Channel\n              2",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GC5C3": {
+                    "description": "Group Channel 5 and Channel\n              3",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR6": {
+              "description": "capture/compare register 6",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR6": {
+                    "description": "Capture/Compare 6 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OR": {
+              "description": "option registers",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM1_ETR_ADC1_RMP": {
+                    "description": "TIM1_ETR_ADC1 remapping\n              capability",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "TIM1_ETR_ADC4_RMP": {
+                    "description": "TIM1_ETR_ADC4 remapping\n              capability",
+                    "offset": 2,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DBGMCU": {
+        "description": "Debug support",
+        "children": {
+          "registers": {
+            "IDCODE": {
+              "description": "MCU Device ID Code Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DEV_ID": {
+                    "description": "Device Identifier",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "REV_ID": {
+                    "description": "Revision Identifier",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "Debug MCU Configuration\n          Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBG_SLEEP": {
+                    "description": "Debug Sleep mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DBG_STOP": {
+                    "description": "Debug Stop Mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DBG_STANDBY": {
+                    "description": "Debug Standby Mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TRACE_IOEN": {
+                    "description": "Trace pin assignment\n              control",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TRACE_MODE": {
+                    "description": "Trace pin assignment\n              control",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "APB1FZ": {
+              "description": "APB Low Freeze Register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBG_TIM2_STOP": {
+                    "description": "Debug Timer 2 stopped when Core is\n              halted",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DBG_TIM3_STOP": {
+                    "description": "Debug Timer 3 stopped when Core is\n              halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DBG_TIM4_STOP": {
+                    "description": "Debug Timer 4 stopped when Core is\n              halted",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DBG_TIM5_STOP": {
+                    "description": "Debug Timer 5 stopped when Core is\n              halted",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DBG_TIM6_STOP": {
+                    "description": "Debug Timer 6 stopped when Core is\n              halted",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DBG_TIM7_STOP": {
+                    "description": "Debug Timer 7 stopped when Core is\n              halted",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DBG_TIM12_STOP": {
+                    "description": "Debug Timer 12 stopped when Core is\n              halted",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DBG_TIM13_STOP": {
+                    "description": "Debug Timer 13 stopped when Core is\n              halted",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DBG_TIMER14_STOP": {
+                    "description": "Debug Timer 14 stopped when Core is\n              halted",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DBG_TIM18_STOP": {
+                    "description": "Debug Timer 18 stopped when Core is\n              halted",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DBG_RTC_STOP": {
+                    "description": "Debug RTC stopped when Core is\n              halted",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DBG_WWDG_STOP": {
+                    "description": "Debug Window Wachdog stopped when Core\n              is halted",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DBG_IWDG_STOP": {
+                    "description": "Debug Independent Wachdog stopped when\n              Core is halted",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "I2C1_SMBUS_TIMEOUT": {
+                    "description": "SMBUS timeout mode stopped when Core is\n              halted",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "I2C2_SMBUS_TIMEOUT": {
+                    "description": "SMBUS timeout mode stopped when Core is\n              halted",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DBG_CAN_STOP": {
+                    "description": "Debug CAN stopped when core is\n              halted",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB2FZ": {
+              "description": "APB High Freeze Register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBG_TIM15_STOP": {
+                    "description": "Debug Timer 15 stopped when Core is\n              halted",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DBG_TIM16_STOP": {
+                    "description": "Debug Timer 16 stopped when Core is\n              halted",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DBG_TIM17_STO": {
+                    "description": "Debug Timer 17 stopped when Core is\n              halted",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DBG_TIM19_STOP": {
+                    "description": "Debug Timer 19 stopped when Core is\n              halted",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  },
+  "devices": {
+    "STM32F303": {
+      "arch": "cortex_m4",
+      "description": "STM32F303",
+      "properties": {
+        "cpu.nvic_prio_bits": "3",
+        "cpu.mpu": "false",
+        "cpu.fpu": "false",
+        "cpu.revision": "r1p0",
+        "cpu.vendor_systick_config": "false",
+        "cpu.endian": "little",
+        "cpu.name": "CM4"
+      },
+      "children": {
+        "interrupts": {
+          "MemManageFault": {
+            "index": -12
+          },
+          "BusFault": {
+            "index": -11
+          },
+          "UsageFault": {
+            "index": -10
+          },
+          "DebugMonitor": {
+            "index": -4
+          },
+          "NMI": {
+            "index": -14
+          },
+          "HardFault": {
+            "index": -13
+          },
+          "SVCall": {
+            "index": -5
+          },
+          "PendSV": {
+            "index": -2
+          },
+          "SysTick": {
+            "index": -1
+          },
+          "EXTI2_TSC": {
+            "index": 8,
+            "description": "EXTI Line2 and Touch sensing\n        interrupts"
+          },
+          "FLASH": {
+            "index": 4,
+            "description": "Flash global interrupt"
+          },
+          "RCC": {
+            "index": 5,
+            "description": "RCC global interrupt"
+          },
+          "DMA1_CH1": {
+            "index": 11,
+            "description": "DMA1 channel 1 interrupt"
+          },
+          "DMA2_CH1": {
+            "index": 56,
+            "description": "DMA2 channel1 global interrupt"
+          },
+          "TIM2": {
+            "index": 28,
+            "description": "TIM2 global interrupt"
+          },
+          "TIM3": {
+            "index": 29,
+            "description": "TIM3 global interrupt"
+          },
+          "TIM4": {
+            "index": 30,
+            "description": "TIM4 global interrupt"
+          },
+          "TIM1_BRK_TIM15": {
+            "index": 24,
+            "description": "TIM1 Break/TIM15 global\n        interruts"
+          },
+          "TIM1_UP_TIM16": {
+            "index": 25,
+            "description": "TIM1 Update/TIM16 global\n        interrupts"
+          },
+          "TIM1_TRG_COM_TIM17": {
+            "index": 26,
+            "description": "TIM1 trigger and commutation/TIM17\n        interrupts"
+          },
+          "USART1_EXTI25": {
+            "index": 37,
+            "description": "USART1 global interrupt and EXTI Line 25\n        interrupt"
+          },
+          "USART2_EXTI26": {
+            "index": 38,
+            "description": "USART2 global interrupt and EXTI Line 26\n        interrupt"
+          },
+          "USART3_EXTI28": {
+            "index": 39,
+            "description": "USART3 global interrupt and EXTI Line 28\n        interrupt"
+          },
+          "UART4_EXTI34": {
+            "index": 52,
+            "description": "UART4 global and EXTI Line 34\n        interrupts"
+          },
+          "UART5_EXTI35": {
+            "index": 53,
+            "description": "UART5 global and EXTI Line 35\n        interrupts"
+          },
+          "SPI1": {
+            "index": 35,
+            "description": "SPI1 global interrupt"
+          },
+          "SPI2": {
+            "index": 36,
+            "description": "SPI2 global interrupt"
+          },
+          "SPI3": {
+            "index": 51,
+            "description": "SPI3 global interrupt"
+          },
+          "TAMP_STAMP": {
+            "index": 2,
+            "description": "Tamper and TimeStamp interrupts"
+          },
+          "PVD": {
+            "index": 1,
+            "description": "PVD through EXTI line detection\n        interrupt"
+          },
+          "USB_HP_CAN_TX": {
+            "index": 19,
+            "description": "USB High Priority/CAN_TX\n        interrupts"
+          },
+          "USB_WKUP": {
+            "index": 42,
+            "description": "USB wakeup from Suspend"
+          },
+          "I2C1_EV_EXTI23": {
+            "index": 31,
+            "description": "I2C1 event interrupt and EXTI Line23\n        interrupt"
+          },
+          "I2C2_EV_EXTI24": {
+            "index": 33,
+            "description": "I2C2 event interrupt & EXTI Line24\n        interrupt"
+          },
+          "WWDG": {
+            "index": 0,
+            "description": "Window Watchdog interrupt"
+          },
+          "RTC_WKUP": {
+            "index": 3,
+            "description": "RTC Wakeup interrupt through the EXTI\n        line"
+          },
+          "TIM6_DACUNDER": {
+            "index": 54,
+            "description": "TIM6 global and DAC12 underrun\n        interrupts"
+          },
+          "TIM7": {
+            "index": 55,
+            "description": "TIM7 global interrupt"
+          },
+          "TIM1_CC": {
+            "index": 27,
+            "description": "TIM1 capture compare interrupt"
+          },
+          "TIM8_BRK": {
+            "index": 43,
+            "description": "TIM8 break interrupt"
+          },
+          "ADC1_2": {
+            "index": 18,
+            "description": "ADC1 and ADC2 global interrupt"
+          },
+          "ADC3": {
+            "index": 47,
+            "description": "ADC3 global interrupt"
+          },
+          "ADC4": {
+            "index": 61,
+            "description": "ADC4 global interrupt"
+          },
+          "COMP123": {
+            "index": 64,
+            "description": "COMP1 & COMP2 & COMP3 interrupts\n        combined with EXTI Lines 21, 22 and 29\n        interrupts"
+          },
+          "FMC": {
+            "index": 48,
+            "description": "FSMC global interrupt"
+          },
+          "FPU": {
+            "index": 81,
+            "description": "Floating point unit interrupt"
+          }
+        },
+        "peripheral_instances": {
+          "GPIOA": {
+            "description": "General-purpose I/Os",
+            "offset": 1207959552,
+            "type": "types.peripherals.GPIOA"
+          },
+          "GPIOB": {
+            "description": "General-purpose I/Os",
+            "offset": 1207960576,
+            "type": "types.peripherals.GPIOB"
+          },
+          "GPIOC": {
+            "offset": 1207961600,
+            "type": "types.peripherals.GPIOB"
+          },
+          "GPIOD": {
+            "offset": 1207962624,
+            "type": "types.peripherals.GPIOB"
+          },
+          "GPIOE": {
+            "offset": 1207963648,
+            "type": "types.peripherals.GPIOB"
+          },
+          "GPIOF": {
+            "offset": 1207964672,
+            "type": "types.peripherals.GPIOB"
+          },
+          "GPIOG": {
+            "offset": 1207965696,
+            "type": "types.peripherals.GPIOB"
+          },
+          "GPIOH": {
+            "offset": 1207966720,
+            "type": "types.peripherals.GPIOB"
+          },
+          "TSC": {
+            "description": "Touch sensing controller",
+            "offset": 1073889280,
+            "type": "types.peripherals.TSC"
+          },
+          "CRC": {
+            "description": "cyclic redundancy check calculation\n      unit",
+            "offset": 1073885184,
+            "type": "types.peripherals.CRC"
+          },
+          "Flash": {
+            "description": "Flash",
+            "offset": 1073881088,
+            "type": "types.peripherals.Flash"
+          },
+          "RCC": {
+            "description": "Reset and clock control",
+            "offset": 1073876992,
+            "type": "types.peripherals.RCC"
+          },
+          "DMA1": {
+            "description": "DMA controller 1",
+            "offset": 1073872896,
+            "type": "types.peripherals.DMA1"
+          },
+          "DMA2": {
+            "offset": 1073873920,
+            "type": "types.peripherals.DMA1"
+          },
+          "TIM2": {
+            "description": "General purpose timer",
+            "offset": 1073741824,
+            "type": "types.peripherals.TIM2"
+          },
+          "TIM3": {
+            "offset": 1073742848,
+            "type": "types.peripherals.TIM2"
+          },
+          "TIM4": {
+            "offset": 1073743872,
+            "type": "types.peripherals.TIM2"
+          },
+          "TIM15": {
+            "description": "General purpose timers",
+            "offset": 1073823744,
+            "type": "types.peripherals.TIM15"
+          },
+          "TIM16": {
+            "description": "General-purpose-timers",
+            "offset": 1073824768,
+            "type": "types.peripherals.TIM16"
+          },
+          "TIM17": {
+            "description": "General purpose timer",
+            "offset": 1073825792,
+            "type": "types.peripherals.TIM17"
+          },
+          "USART1": {
+            "description": "Universal synchronous asynchronous receiver\n      transmitter",
+            "offset": 1073821696,
+            "type": "types.peripherals.USART1"
+          },
+          "USART2": {
+            "offset": 1073759232,
+            "type": "types.peripherals.USART1"
+          },
+          "USART3": {
+            "offset": 1073760256,
+            "type": "types.peripherals.USART1"
+          },
+          "UART4": {
+            "offset": 1073761280,
+            "type": "types.peripherals.USART1"
+          },
+          "UART5": {
+            "offset": 1073762304,
+            "type": "types.peripherals.USART1"
+          },
+          "SPI1": {
+            "description": "Serial peripheral interface/Inter-IC\n      sound",
+            "offset": 1073819648,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI2": {
+            "offset": 1073756160,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI3": {
+            "offset": 1073757184,
+            "type": "types.peripherals.SPI1"
+          },
+          "I2S2ext": {
+            "offset": 1073755136,
+            "type": "types.peripherals.SPI1"
+          },
+          "I2S3ext": {
+            "offset": 1073758208,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI4": {
+            "offset": 1073822720,
+            "type": "types.peripherals.SPI1"
+          },
+          "EXTI": {
+            "description": "External interrupt/event\n      controller",
+            "offset": 1073808384,
+            "type": "types.peripherals.EXTI"
+          },
+          "PWR": {
+            "description": "Power control",
+            "offset": 1073770496,
+            "type": "types.peripherals.PWR"
+          },
+          "CAN": {
+            "description": "Controller area network",
+            "offset": 1073767424,
+            "type": "types.peripherals.CAN"
+          },
+          "USB_FS": {
+            "description": "Universal serial bus full-speed device\n      interface",
+            "offset": 1073765376,
+            "type": "types.peripherals.USB_FS"
+          },
+          "I2C1": {
+            "description": "Inter-integrated circuit",
+            "offset": 1073763328,
+            "type": "types.peripherals.I2C1"
+          },
+          "I2C2": {
+            "offset": 1073764352,
+            "type": "types.peripherals.I2C1"
+          },
+          "I2C3": {
+            "offset": 1073772544,
+            "type": "types.peripherals.I2C1"
+          },
+          "IWDG": {
+            "description": "Independent watchdog",
+            "offset": 1073754112,
+            "type": "types.peripherals.IWDG"
+          },
+          "WWDG": {
+            "description": "Window watchdog",
+            "offset": 1073753088,
+            "type": "types.peripherals.WWDG"
+          },
+          "RTC": {
+            "description": "Real-time clock",
+            "offset": 1073752064,
+            "type": "types.peripherals.RTC"
+          },
+          "TIM6": {
+            "description": "Basic timers",
+            "offset": 1073745920,
+            "type": "types.peripherals.TIM6"
+          },
+          "TIM7": {
+            "offset": 1073746944,
+            "type": "types.peripherals.TIM6"
+          },
+          "DAC": {
+            "description": "Digital-to-analog converter",
+            "offset": 1073771520,
+            "type": "types.peripherals.DAC"
+          },
+          "DBGMCU": {
+            "description": "Debug support",
+            "offset": 3758366720,
+            "type": "types.peripherals.DBGMCU"
+          },
+          "TIM1": {
+            "description": "Advanced timer",
+            "offset": 1073818624,
+            "type": "types.peripherals.TIM1"
+          },
+          "TIM20": {
+            "offset": 1073827840,
+            "type": "types.peripherals.TIM1"
+          },
+          "TIM8": {
+            "description": "Advanced-timers",
+            "offset": 1073820672,
+            "type": "types.peripherals.TIM8"
+          },
+          "ADC1": {
+            "description": "Analog-to-Digital Converter",
+            "offset": 1342177280,
+            "type": "types.peripherals.ADC1"
+          },
+          "ADC2": {
+            "offset": 1342177536,
+            "type": "types.peripherals.ADC1"
+          },
+          "ADC3": {
+            "offset": 1342178304,
+            "type": "types.peripherals.ADC1"
+          },
+          "ADC4": {
+            "offset": 1342178560,
+            "type": "types.peripherals.ADC1"
+          },
+          "ADC1_2": {
+            "description": "Analog-to-Digital Converter",
+            "offset": 1342178048,
+            "type": "types.peripherals.ADC1_2"
+          },
+          "ADC3_4": {
+            "offset": 1342179072,
+            "type": "types.peripherals.ADC1_2"
+          },
+          "SYSCFG_COMP_OPAMP": {
+            "description": "System configuration controller _Comparator and\n      Operational amplifier",
+            "offset": 1073807360,
+            "type": "types.peripherals.SYSCFG_COMP_OPAMP"
+          },
+          "FMC": {
+            "description": "Flexible memory controller",
+            "offset": 2684355584,
+            "type": "types.peripherals.FMC"
+          },
+          "NVIC": {
+            "description": "Nested Vectored Interrupt\n      Controller",
+            "offset": 3758153984,
+            "type": "types.peripherals.NVIC"
+          },
+          "FPU": {
+            "description": "Floting point unit",
+            "offset": 3758157620,
+            "type": "types.peripherals.FPU"
+          },
+          "MPU": {
+            "description": "Memory protection unit",
+            "offset": 3758157200,
+            "type": "types.peripherals.MPU"
+          },
+          "STK": {
+            "description": "SysTick timer",
+            "offset": 3758153744,
+            "type": "types.peripherals.STK"
+          },
+          "SCB": {
+            "description": "System control block",
+            "offset": 3758157056,
+            "type": "types.peripherals.SCB"
+          },
+          "NVIC_STIR": {
+            "description": "Nested vectored interrupt\n      controller",
+            "offset": 3758157568,
+            "type": "types.peripherals.NVIC_STIR"
+          },
+          "FPU_CPACR": {
+            "description": "Floating point unit CPACR",
+            "offset": 3758157192,
+            "type": "types.peripherals.FPU_CPACR"
+          },
+          "SCB_ACTRL": {
+            "description": "System control block ACTLR",
+            "offset": 3758153736,
+            "type": "types.peripherals.SCB_ACTRL"
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/chips/STM32F303.zig b/src/chips/STM32F303.zig
new file mode 100644
index 000000000..4bb914c29
--- /dev/null
+++ b/src/chips/STM32F303.zig
@@ -0,0 +1,13076 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    ///  STM32F303
+    pub const STM32F303 = struct {
+        pub const properties = struct {
+            pub const @"cpu.nvic_prio_bits" = "3";
+            pub const @"cpu.mpu" = "false";
+            pub const @"cpu.fpu" = "false";
+            pub const @"cpu.revision" = "r1p0";
+            pub const @"cpu.vendor_systick_config" = "false";
+            pub const @"cpu.endian" = "little";
+            pub const @"cpu.name" = "CM4";
+        };
+
+        pub const VectorTable = extern struct {
+            const Handler = micro.interrupt.Handler;
+            const unhandled = micro.interrupt.unhandled;
+
+            initial_stack_pointer: u32,
+            Reset: Handler = unhandled,
+            NMI: Handler = unhandled,
+            HardFault: Handler = unhandled,
+            MemManageFault: Handler = unhandled,
+            BusFault: Handler = unhandled,
+            UsageFault: Handler = unhandled,
+            reserved5: [4]u32 = undefined,
+            SVCall: Handler = unhandled,
+            DebugMonitor: Handler = unhandled,
+            reserved11: [1]u32 = undefined,
+            PendSV: Handler = unhandled,
+            SysTick: Handler = unhandled,
+            ///  Window Watchdog interrupt
+            WWDG: Handler = unhandled,
+            ///  PVD through EXTI line detection interrupt
+            PVD: Handler = unhandled,
+            ///  Tamper and TimeStamp interrupts
+            TAMP_STAMP: Handler = unhandled,
+            ///  RTC Wakeup interrupt through the EXTI line
+            RTC_WKUP: Handler = unhandled,
+            ///  Flash global interrupt
+            FLASH: Handler = unhandled,
+            ///  RCC global interrupt
+            RCC: Handler = unhandled,
+            reserved20: [2]u32 = undefined,
+            ///  EXTI Line2 and Touch sensing interrupts
+            EXTI2_TSC: Handler = unhandled,
+            reserved23: [2]u32 = undefined,
+            ///  DMA1 channel 1 interrupt
+            DMA1_CH1: Handler = unhandled,
+            reserved26: [6]u32 = undefined,
+            ///  ADC1 and ADC2 global interrupt
+            ADC1_2: Handler = unhandled,
+            ///  USB High Priority/CAN_TX interrupts
+            USB_HP_CAN_TX: Handler = unhandled,
+            reserved34: [4]u32 = undefined,
+            ///  TIM1 Break/TIM15 global interruts
+            TIM1_BRK_TIM15: Handler = unhandled,
+            ///  TIM1 Update/TIM16 global interrupts
+            TIM1_UP_TIM16: Handler = unhandled,
+            ///  TIM1 trigger and commutation/TIM17 interrupts
+            TIM1_TRG_COM_TIM17: Handler = unhandled,
+            ///  TIM1 capture compare interrupt
+            TIM1_CC: Handler = unhandled,
+            ///  TIM2 global interrupt
+            TIM2: Handler = unhandled,
+            ///  TIM3 global interrupt
+            TIM3: Handler = unhandled,
+            ///  TIM4 global interrupt
+            TIM4: Handler = unhandled,
+            ///  I2C1 event interrupt and EXTI Line23 interrupt
+            I2C1_EV_EXTI23: Handler = unhandled,
+            reserved46: [1]u32 = undefined,
+            ///  I2C2 event interrupt & EXTI Line24 interrupt
+            I2C2_EV_EXTI24: Handler = unhandled,
+            reserved48: [1]u32 = undefined,
+            ///  SPI1 global interrupt
+            SPI1: Handler = unhandled,
+            ///  SPI2 global interrupt
+            SPI2: Handler = unhandled,
+            ///  USART1 global interrupt and EXTI Line 25 interrupt
+            USART1_EXTI25: Handler = unhandled,
+            ///  USART2 global interrupt and EXTI Line 26 interrupt
+            USART2_EXTI26: Handler = unhandled,
+            ///  USART3 global interrupt and EXTI Line 28 interrupt
+            USART3_EXTI28: Handler = unhandled,
+            reserved54: [2]u32 = undefined,
+            ///  USB wakeup from Suspend
+            USB_WKUP: Handler = unhandled,
+            ///  TIM8 break interrupt
+            TIM8_BRK: Handler = unhandled,
+            reserved58: [3]u32 = undefined,
+            ///  ADC3 global interrupt
+            ADC3: Handler = unhandled,
+            ///  FSMC global interrupt
+            FMC: Handler = unhandled,
+            reserved63: [2]u32 = undefined,
+            ///  SPI3 global interrupt
+            SPI3: Handler = unhandled,
+            ///  UART4 global and EXTI Line 34 interrupts
+            UART4_EXTI34: Handler = unhandled,
+            ///  UART5 global and EXTI Line 35 interrupts
+            UART5_EXTI35: Handler = unhandled,
+            ///  TIM6 global and DAC12 underrun interrupts
+            TIM6_DACUNDER: Handler = unhandled,
+            ///  TIM7 global interrupt
+            TIM7: Handler = unhandled,
+            ///  DMA2 channel1 global interrupt
+            DMA2_CH1: Handler = unhandled,
+            reserved71: [4]u32 = undefined,
+            ///  ADC4 global interrupt
+            ADC4: Handler = unhandled,
+            reserved76: [2]u32 = undefined,
+            ///  COMP1 & COMP2 & COMP3 interrupts combined with EXTI Lines 21, 22 and 29 interrupts
+            COMP123: Handler = unhandled,
+            reserved79: [16]u32 = undefined,
+            ///  Floating point unit interrupt
+            FPU: Handler = unhandled,
+        };
+
+        pub const peripherals = struct {
+            ///  General purpose timer
+            pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000);
+            ///  General purpose timer
+            pub const TIM3 = @ptrCast(*volatile types.TIM2, 0x40000400);
+            ///  General purpose timer
+            pub const TIM4 = @ptrCast(*volatile types.TIM2, 0x40000800);
+            ///  Basic timers
+            pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000);
+            ///  Basic timers
+            pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400);
+            ///  Real-time clock
+            pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800);
+            ///  Window watchdog
+            pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00);
+            ///  Independent watchdog
+            pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000);
+            ///  Serial peripheral interface/Inter-IC sound
+            pub const I2S2ext = @ptrCast(*volatile types.SPI1, 0x40003400);
+            ///  Serial peripheral interface/Inter-IC sound
+            pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800);
+            ///  Serial peripheral interface/Inter-IC sound
+            pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00);
+            ///  Serial peripheral interface/Inter-IC sound
+            pub const I2S3ext = @ptrCast(*volatile types.SPI1, 0x40004000);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART2 = @ptrCast(*volatile types.USART1, 0x40004400);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART3 = @ptrCast(*volatile types.USART1, 0x40004800);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const UART4 = @ptrCast(*volatile types.USART1, 0x40004c00);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const UART5 = @ptrCast(*volatile types.USART1, 0x40005000);
+            ///  Inter-integrated circuit
+            pub const I2C1 = @ptrCast(*volatile types.I2C1, 0x40005400);
+            ///  Inter-integrated circuit
+            pub const I2C2 = @ptrCast(*volatile types.I2C1, 0x40005800);
+            ///  Universal serial bus full-speed device interface
+            pub const USB_FS = @ptrCast(*volatile types.USB_FS, 0x40005c00);
+            ///  Controller area network
+            pub const CAN = @ptrCast(*volatile types.CAN, 0x40006400);
+            ///  Power control
+            pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000);
+            ///  Digital-to-analog converter
+            pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400);
+            ///  Inter-integrated circuit
+            pub const I2C3 = @ptrCast(*volatile types.I2C1, 0x40007800);
+            ///  System configuration controller _Comparator and Operational amplifier
+            pub const SYSCFG_COMP_OPAMP = @ptrCast(*volatile types.SYSCFG_COMP_OPAMP, 0x40010000);
+            ///  External interrupt/event controller
+            pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40010400);
+            ///  Advanced timer
+            pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40012c00);
+            ///  Serial peripheral interface/Inter-IC sound
+            pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000);
+            ///  Advanced-timers
+            pub const TIM8 = @ptrCast(*volatile types.TIM8, 0x40013400);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART1 = @ptrCast(*volatile types.USART1, 0x40013800);
+            ///  Serial peripheral interface/Inter-IC sound
+            pub const SPI4 = @ptrCast(*volatile types.SPI1, 0x40013c00);
+            ///  General purpose timers
+            pub const TIM15 = @ptrCast(*volatile types.TIM15, 0x40014000);
+            ///  General-purpose-timers
+            pub const TIM16 = @ptrCast(*volatile types.TIM16, 0x40014400);
+            ///  General purpose timer
+            pub const TIM17 = @ptrCast(*volatile types.TIM17, 0x40014800);
+            ///  Advanced timer
+            pub const TIM20 = @ptrCast(*volatile types.TIM1, 0x40015000);
+            ///  DMA controller 1
+            pub const DMA1 = @ptrCast(*volatile types.DMA1, 0x40020000);
+            ///  DMA controller 1
+            pub const DMA2 = @ptrCast(*volatile types.DMA1, 0x40020400);
+            ///  Reset and clock control
+            pub const RCC = @ptrCast(*volatile types.RCC, 0x40021000);
+            ///  Flash
+            pub const Flash = @ptrCast(*volatile types.Flash, 0x40022000);
+            ///  cyclic redundancy check calculation unit
+            pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000);
+            ///  Touch sensing controller
+            pub const TSC = @ptrCast(*volatile types.TSC, 0x40024000);
+            ///  General-purpose I/Os
+            pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x48000000);
+            ///  General-purpose I/Os
+            pub const GPIOB = @ptrCast(*volatile types.GPIOB, 0x48000400);
+            ///  General-purpose I/Os
+            pub const GPIOC = @ptrCast(*volatile types.GPIOB, 0x48000800);
+            ///  General-purpose I/Os
+            pub const GPIOD = @ptrCast(*volatile types.GPIOB, 0x48000c00);
+            ///  General-purpose I/Os
+            pub const GPIOE = @ptrCast(*volatile types.GPIOB, 0x48001000);
+            ///  General-purpose I/Os
+            pub const GPIOF = @ptrCast(*volatile types.GPIOB, 0x48001400);
+            ///  General-purpose I/Os
+            pub const GPIOG = @ptrCast(*volatile types.GPIOB, 0x48001800);
+            ///  General-purpose I/Os
+            pub const GPIOH = @ptrCast(*volatile types.GPIOB, 0x48001c00);
+            ///  Analog-to-Digital Converter
+            pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x50000000);
+            ///  Analog-to-Digital Converter
+            pub const ADC2 = @ptrCast(*volatile types.ADC1, 0x50000100);
+            ///  Analog-to-Digital Converter
+            pub const ADC1_2 = @ptrCast(*volatile types.ADC1_2, 0x50000300);
+            ///  Analog-to-Digital Converter
+            pub const ADC3 = @ptrCast(*volatile types.ADC1, 0x50000400);
+            ///  Analog-to-Digital Converter
+            pub const ADC4 = @ptrCast(*volatile types.ADC1, 0x50000500);
+            ///  Analog-to-Digital Converter
+            pub const ADC3_4 = @ptrCast(*volatile types.ADC1_2, 0x50000700);
+            ///  Flexible memory controller
+            pub const FMC = @ptrCast(*volatile types.FMC, 0xa0000400);
+            ///  System control block ACTLR
+            pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008);
+            ///  SysTick timer
+            pub const STK = @ptrCast(*volatile types.STK, 0xe000e010);
+            ///  Nested Vectored Interrupt Controller
+            pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100);
+            ///  System control block
+            pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00);
+            ///  Floating point unit CPACR
+            pub const FPU_CPACR = @ptrCast(*volatile types.FPU_CPACR, 0xe000ed88);
+            ///  Memory protection unit
+            pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90);
+            ///  Nested vectored interrupt controller
+            pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00);
+            ///  Floting point unit
+            pub const FPU = @ptrCast(*volatile types.FPU, 0xe000ef34);
+            ///  Debug support
+            pub const DBGMCU = @ptrCast(*volatile types.DBGMCU, 0xe0042000);
+        };
+    };
+};
+
+pub const types = struct {
+    ///  General-purpose I/Os
+    pub const GPIOA = extern struct {
+        ///  GPIO port mode register
+        MODER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            MODER0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER15: u2,
+        }),
+        ///  GPIO port output type register
+        OTYPER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OT0: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT1: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT2: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT3: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT4: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT5: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT6: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT7: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT8: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT9: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT10: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT11: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT12: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT13: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT14: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output speed register
+        OSPEEDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR15: u2,
+        }),
+        ///  GPIO port pull-up/pull-down register
+        PUPDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR15: u2,
+        }),
+        ///  GPIO port input data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Port input data (y = 0..15)
+            IDR0: u1,
+            ///  Port input data (y = 0..15)
+            IDR1: u1,
+            ///  Port input data (y = 0..15)
+            IDR2: u1,
+            ///  Port input data (y = 0..15)
+            IDR3: u1,
+            ///  Port input data (y = 0..15)
+            IDR4: u1,
+            ///  Port input data (y = 0..15)
+            IDR5: u1,
+            ///  Port input data (y = 0..15)
+            IDR6: u1,
+            ///  Port input data (y = 0..15)
+            IDR7: u1,
+            ///  Port input data (y = 0..15)
+            IDR8: u1,
+            ///  Port input data (y = 0..15)
+            IDR9: u1,
+            ///  Port input data (y = 0..15)
+            IDR10: u1,
+            ///  Port input data (y = 0..15)
+            IDR11: u1,
+            ///  Port input data (y = 0..15)
+            IDR12: u1,
+            ///  Port input data (y = 0..15)
+            IDR13: u1,
+            ///  Port input data (y = 0..15)
+            IDR14: u1,
+            ///  Port input data (y = 0..15)
+            IDR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output data register
+        ODR: mmio.Mmio(packed struct(u32) {
+            ///  Port output data (y = 0..15)
+            ODR0: u1,
+            ///  Port output data (y = 0..15)
+            ODR1: u1,
+            ///  Port output data (y = 0..15)
+            ODR2: u1,
+            ///  Port output data (y = 0..15)
+            ODR3: u1,
+            ///  Port output data (y = 0..15)
+            ODR4: u1,
+            ///  Port output data (y = 0..15)
+            ODR5: u1,
+            ///  Port output data (y = 0..15)
+            ODR6: u1,
+            ///  Port output data (y = 0..15)
+            ODR7: u1,
+            ///  Port output data (y = 0..15)
+            ODR8: u1,
+            ///  Port output data (y = 0..15)
+            ODR9: u1,
+            ///  Port output data (y = 0..15)
+            ODR10: u1,
+            ///  Port output data (y = 0..15)
+            ODR11: u1,
+            ///  Port output data (y = 0..15)
+            ODR12: u1,
+            ///  Port output data (y = 0..15)
+            ODR13: u1,
+            ///  Port output data (y = 0..15)
+            ODR14: u1,
+            ///  Port output data (y = 0..15)
+            ODR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port bit set/reset register
+        BSRR: mmio.Mmio(packed struct(u32) {
+            ///  Port x set bit y (y= 0..15)
+            BS0: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS1: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS2: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS3: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS4: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS5: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS6: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS7: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS8: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS9: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS10: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS11: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS12: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS13: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS14: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS15: u1,
+            ///  Port x set bit y (y= 0..15)
+            BR0: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR1: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR2: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR3: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR4: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR5: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR6: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR7: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR8: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR9: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR10: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR11: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR12: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR13: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR14: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR15: u1,
+        }),
+        ///  GPIO port configuration lock register
+        LCKR: mmio.Mmio(packed struct(u32) {
+            ///  Port x lock bit y (y= 0..15)
+            LCK0: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK1: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK2: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK3: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK4: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK5: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK6: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK7: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK8: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK9: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK10: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK11: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK12: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK13: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK14: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK15: u1,
+            ///  Lok Key
+            LCKK: u1,
+            padding: u15,
+        }),
+        ///  GPIO alternate function low register
+        AFRL: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL0: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL1: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL2: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL3: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL4: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL5: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL6: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL7: u4,
+        }),
+        ///  GPIO alternate function high register
+        AFRH: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH8: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH9: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH10: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH11: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH12: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH13: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH14: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH15: u4,
+        }),
+        ///  Port bit reset register
+        BRR: mmio.Mmio(packed struct(u32) {
+            ///  Port x Reset bit y
+            BR0: u1,
+            ///  Port x Reset bit y
+            BR1: u1,
+            ///  Port x Reset bit y
+            BR2: u1,
+            ///  Port x Reset bit y
+            BR3: u1,
+            ///  Port x Reset bit y
+            BR4: u1,
+            ///  Port x Reset bit y
+            BR5: u1,
+            ///  Port x Reset bit y
+            BR6: u1,
+            ///  Port x Reset bit y
+            BR7: u1,
+            ///  Port x Reset bit y
+            BR8: u1,
+            ///  Port x Reset bit y
+            BR9: u1,
+            ///  Port x Reset bit y
+            BR10: u1,
+            ///  Port x Reset bit y
+            BR11: u1,
+            ///  Port x Reset bit y
+            BR12: u1,
+            ///  Port x Reset bit y
+            BR13: u1,
+            ///  Port x Reset bit y
+            BR14: u1,
+            ///  Port x Reset bit y
+            BR15: u1,
+            padding: u16,
+        }),
+    };
+
+    ///  General-purpose I/Os
+    pub const GPIOB = extern struct {
+        ///  GPIO port mode register
+        MODER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            MODER0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER15: u2,
+        }),
+        ///  GPIO port output type register
+        OTYPER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bit 0
+            OT0: u1,
+            ///  Port x configuration bit 1
+            OT1: u1,
+            ///  Port x configuration bit 2
+            OT2: u1,
+            ///  Port x configuration bit 3
+            OT3: u1,
+            ///  Port x configuration bit 4
+            OT4: u1,
+            ///  Port x configuration bit 5
+            OT5: u1,
+            ///  Port x configuration bit 6
+            OT6: u1,
+            ///  Port x configuration bit 7
+            OT7: u1,
+            ///  Port x configuration bit 8
+            OT8: u1,
+            ///  Port x configuration bit 9
+            OT9: u1,
+            ///  Port x configuration bit 10
+            OT10: u1,
+            ///  Port x configuration bit 11
+            OT11: u1,
+            ///  Port x configuration bit 12
+            OT12: u1,
+            ///  Port x configuration bit 13
+            OT13: u1,
+            ///  Port x configuration bit 14
+            OT14: u1,
+            ///  Port x configuration bit 15
+            OT15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output speed register
+        OSPEEDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR15: u2,
+        }),
+        ///  GPIO port pull-up/pull-down register
+        PUPDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR15: u2,
+        }),
+        ///  GPIO port input data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Port input data (y = 0..15)
+            IDR0: u1,
+            ///  Port input data (y = 0..15)
+            IDR1: u1,
+            ///  Port input data (y = 0..15)
+            IDR2: u1,
+            ///  Port input data (y = 0..15)
+            IDR3: u1,
+            ///  Port input data (y = 0..15)
+            IDR4: u1,
+            ///  Port input data (y = 0..15)
+            IDR5: u1,
+            ///  Port input data (y = 0..15)
+            IDR6: u1,
+            ///  Port input data (y = 0..15)
+            IDR7: u1,
+            ///  Port input data (y = 0..15)
+            IDR8: u1,
+            ///  Port input data (y = 0..15)
+            IDR9: u1,
+            ///  Port input data (y = 0..15)
+            IDR10: u1,
+            ///  Port input data (y = 0..15)
+            IDR11: u1,
+            ///  Port input data (y = 0..15)
+            IDR12: u1,
+            ///  Port input data (y = 0..15)
+            IDR13: u1,
+            ///  Port input data (y = 0..15)
+            IDR14: u1,
+            ///  Port input data (y = 0..15)
+            IDR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output data register
+        ODR: mmio.Mmio(packed struct(u32) {
+            ///  Port output data (y = 0..15)
+            ODR0: u1,
+            ///  Port output data (y = 0..15)
+            ODR1: u1,
+            ///  Port output data (y = 0..15)
+            ODR2: u1,
+            ///  Port output data (y = 0..15)
+            ODR3: u1,
+            ///  Port output data (y = 0..15)
+            ODR4: u1,
+            ///  Port output data (y = 0..15)
+            ODR5: u1,
+            ///  Port output data (y = 0..15)
+            ODR6: u1,
+            ///  Port output data (y = 0..15)
+            ODR7: u1,
+            ///  Port output data (y = 0..15)
+            ODR8: u1,
+            ///  Port output data (y = 0..15)
+            ODR9: u1,
+            ///  Port output data (y = 0..15)
+            ODR10: u1,
+            ///  Port output data (y = 0..15)
+            ODR11: u1,
+            ///  Port output data (y = 0..15)
+            ODR12: u1,
+            ///  Port output data (y = 0..15)
+            ODR13: u1,
+            ///  Port output data (y = 0..15)
+            ODR14: u1,
+            ///  Port output data (y = 0..15)
+            ODR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port bit set/reset register
+        BSRR: mmio.Mmio(packed struct(u32) {
+            ///  Port x set bit y (y= 0..15)
+            BS0: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS1: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS2: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS3: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS4: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS5: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS6: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS7: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS8: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS9: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS10: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS11: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS12: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS13: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS14: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS15: u1,
+            ///  Port x set bit y (y= 0..15)
+            BR0: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR1: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR2: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR3: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR4: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR5: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR6: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR7: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR8: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR9: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR10: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR11: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR12: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR13: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR14: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR15: u1,
+        }),
+        ///  GPIO port configuration lock register
+        LCKR: mmio.Mmio(packed struct(u32) {
+            ///  Port x lock bit y (y= 0..15)
+            LCK0: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK1: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK2: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK3: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK4: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK5: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK6: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK7: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK8: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK9: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK10: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK11: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK12: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK13: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK14: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK15: u1,
+            ///  Lok Key
+            LCKK: u1,
+            padding: u15,
+        }),
+        ///  GPIO alternate function low register
+        AFRL: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL0: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL1: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL2: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL3: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL4: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL5: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL6: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL7: u4,
+        }),
+        ///  GPIO alternate function high register
+        AFRH: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH8: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH9: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH10: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH11: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH12: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH13: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH14: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH15: u4,
+        }),
+        ///  Port bit reset register
+        BRR: mmio.Mmio(packed struct(u32) {
+            ///  Port x Reset bit y
+            BR0: u1,
+            ///  Port x Reset bit y
+            BR1: u1,
+            ///  Port x Reset bit y
+            BR2: u1,
+            ///  Port x Reset bit y
+            BR3: u1,
+            ///  Port x Reset bit y
+            BR4: u1,
+            ///  Port x Reset bit y
+            BR5: u1,
+            ///  Port x Reset bit y
+            BR6: u1,
+            ///  Port x Reset bit y
+            BR7: u1,
+            ///  Port x Reset bit y
+            BR8: u1,
+            ///  Port x Reset bit y
+            BR9: u1,
+            ///  Port x Reset bit y
+            BR10: u1,
+            ///  Port x Reset bit y
+            BR11: u1,
+            ///  Port x Reset bit y
+            BR12: u1,
+            ///  Port x Reset bit y
+            BR13: u1,
+            ///  Port x Reset bit y
+            BR14: u1,
+            ///  Port x Reset bit y
+            BR15: u1,
+            padding: u16,
+        }),
+    };
+
+    ///  System control block ACTLR
+    pub const SCB_ACTRL = extern struct {
+        ///  Auxiliary control register
+        ACTRL: mmio.Mmio(packed struct(u32) {
+            ///  DISMCYCINT
+            DISMCYCINT: u1,
+            ///  DISDEFWBUF
+            DISDEFWBUF: u1,
+            ///  DISFOLD
+            DISFOLD: u1,
+            reserved8: u5,
+            ///  DISFPCA
+            DISFPCA: u1,
+            ///  DISOOFP
+            DISOOFP: u1,
+            padding: u22,
+        }),
+    };
+
+    ///  Floating point unit CPACR
+    pub const FPU_CPACR = extern struct {
+        ///  Coprocessor access control register
+        CPACR: mmio.Mmio(packed struct(u32) {
+            reserved20: u20,
+            ///  CP
+            CP: u4,
+            padding: u8,
+        }),
+    };
+
+    ///  Nested vectored interrupt controller
+    pub const NVIC_STIR = extern struct {
+        ///  Software trigger interrupt register
+        STIR: mmio.Mmio(packed struct(u32) {
+            ///  Software generated interrupt ID
+            INTID: u9,
+            padding: u23,
+        }),
+    };
+
+    ///  System control block
+    pub const SCB = extern struct {
+        ///  CPUID base register
+        CPUID: mmio.Mmio(packed struct(u32) {
+            ///  Revision number
+            Revision: u4,
+            ///  Part number of the processor
+            PartNo: u12,
+            ///  Reads as 0xF
+            Constant: u4,
+            ///  Variant number
+            Variant: u4,
+            ///  Implementer code
+            Implementer: u8,
+        }),
+        ///  Interrupt control and state register
+        ICSR: mmio.Mmio(packed struct(u32) {
+            ///  Active vector
+            VECTACTIVE: u9,
+            reserved11: u2,
+            ///  Return to base level
+            RETTOBASE: u1,
+            ///  Pending vector
+            VECTPENDING: u7,
+            reserved22: u3,
+            ///  Interrupt pending flag
+            ISRPENDING: u1,
+            reserved25: u2,
+            ///  SysTick exception clear-pending bit
+            PENDSTCLR: u1,
+            ///  SysTick exception set-pending bit
+            PENDSTSET: u1,
+            ///  PendSV clear-pending bit
+            PENDSVCLR: u1,
+            ///  PendSV set-pending bit
+            PENDSVSET: u1,
+            reserved31: u2,
+            ///  NMI set-pending bit.
+            NMIPENDSET: u1,
+        }),
+        ///  Vector table offset register
+        VTOR: mmio.Mmio(packed struct(u32) {
+            reserved9: u9,
+            ///  Vector table base offset field
+            TBLOFF: u21,
+            padding: u2,
+        }),
+        ///  Application interrupt and reset control register
+        AIRCR: mmio.Mmio(packed struct(u32) {
+            ///  VECTRESET
+            VECTRESET: u1,
+            ///  VECTCLRACTIVE
+            VECTCLRACTIVE: u1,
+            ///  SYSRESETREQ
+            SYSRESETREQ: u1,
+            reserved8: u5,
+            ///  PRIGROUP
+            PRIGROUP: u3,
+            reserved15: u4,
+            ///  ENDIANESS
+            ENDIANESS: u1,
+            ///  Register key
+            VECTKEYSTAT: u16,
+        }),
+        ///  System control register
+        SCR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  SLEEPONEXIT
+            SLEEPONEXIT: u1,
+            ///  SLEEPDEEP
+            SLEEPDEEP: u1,
+            reserved4: u1,
+            ///  Send Event on Pending bit
+            SEVEONPEND: u1,
+            padding: u27,
+        }),
+        ///  Configuration and control register
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Configures how the processor enters Thread mode
+            NONBASETHRDENA: u1,
+            ///  USERSETMPEND
+            USERSETMPEND: u1,
+            reserved3: u1,
+            ///  UNALIGN_ TRP
+            UNALIGN__TRP: u1,
+            ///  DIV_0_TRP
+            DIV_0_TRP: u1,
+            reserved8: u3,
+            ///  BFHFNMIGN
+            BFHFNMIGN: u1,
+            ///  STKALIGN
+            STKALIGN: u1,
+            padding: u22,
+        }),
+        ///  System handler priority registers
+        SHPR1: mmio.Mmio(packed struct(u32) {
+            ///  Priority of system handler 4
+            PRI_4: u8,
+            ///  Priority of system handler 5
+            PRI_5: u8,
+            ///  Priority of system handler 6
+            PRI_6: u8,
+            padding: u8,
+        }),
+        ///  System handler priority registers
+        SHPR2: mmio.Mmio(packed struct(u32) {
+            reserved24: u24,
+            ///  Priority of system handler 11
+            PRI_11: u8,
+        }),
+        ///  System handler priority registers
+        SHPR3: mmio.Mmio(packed struct(u32) {
+            reserved16: u16,
+            ///  Priority of system handler 14
+            PRI_14: u8,
+            ///  Priority of system handler 15
+            PRI_15: u8,
+        }),
+        ///  System handler control and state register
+        SHCRS: mmio.Mmio(packed struct(u32) {
+            ///  Memory management fault exception active bit
+            MEMFAULTACT: u1,
+            ///  Bus fault exception active bit
+            BUSFAULTACT: u1,
+            reserved3: u1,
+            ///  Usage fault exception active bit
+            USGFAULTACT: u1,
+            reserved7: u3,
+            ///  SVC call active bit
+            SVCALLACT: u1,
+            ///  Debug monitor active bit
+            MONITORACT: u1,
+            reserved10: u1,
+            ///  PendSV exception active bit
+            PENDSVACT: u1,
+            ///  SysTick exception active bit
+            SYSTICKACT: u1,
+            ///  Usage fault exception pending bit
+            USGFAULTPENDED: u1,
+            ///  Memory management fault exception pending bit
+            MEMFAULTPENDED: u1,
+            ///  Bus fault exception pending bit
+            BUSFAULTPENDED: u1,
+            ///  SVC call pending bit
+            SVCALLPENDED: u1,
+            ///  Memory management fault enable bit
+            MEMFAULTENA: u1,
+            ///  Bus fault enable bit
+            BUSFAULTENA: u1,
+            ///  Usage fault enable bit
+            USGFAULTENA: u1,
+            padding: u13,
+        }),
+        ///  Configurable fault status register
+        CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Instruction access violation flag
+            IACCVIOL: u1,
+            reserved3: u1,
+            ///  Memory manager fault on unstacking for a return from exception
+            MUNSTKERR: u1,
+            ///  Memory manager fault on stacking for exception entry.
+            MSTKERR: u1,
+            ///  MLSPERR
+            MLSPERR: u1,
+            reserved7: u1,
+            ///  Memory Management Fault Address Register (MMAR) valid flag
+            MMARVALID: u1,
+            ///  Instruction bus error
+            IBUSERR: u1,
+            ///  Precise data bus error
+            PRECISERR: u1,
+            ///  Imprecise data bus error
+            IMPRECISERR: u1,
+            ///  Bus fault on unstacking for a return from exception
+            UNSTKERR: u1,
+            ///  Bus fault on stacking for exception entry
+            STKERR: u1,
+            ///  Bus fault on floating-point lazy state preservation
+            LSPERR: u1,
+            reserved15: u1,
+            ///  Bus Fault Address Register (BFAR) valid flag
+            BFARVALID: u1,
+            ///  Undefined instruction usage fault
+            UNDEFINSTR: u1,
+            ///  Invalid state usage fault
+            INVSTATE: u1,
+            ///  Invalid PC load usage fault
+            INVPC: u1,
+            ///  No coprocessor usage fault.
+            NOCP: u1,
+            reserved24: u4,
+            ///  Unaligned access usage fault
+            UNALIGNED: u1,
+            ///  Divide by zero usage fault
+            DIVBYZERO: u1,
+            padding: u6,
+        }),
+        ///  Hard fault status register
+        HFSR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Vector table hard fault
+            VECTTBL: u1,
+            reserved30: u28,
+            ///  Forced hard fault
+            FORCED: u1,
+            ///  Reserved for Debug use
+            DEBUG_VT: u1,
+        }),
+        reserved52: [4]u8,
+        ///  Memory management fault address register
+        MMFAR: mmio.Mmio(packed struct(u32) {
+            ///  Memory management fault address
+            MMFAR: u32,
+        }),
+        ///  Bus fault address register
+        BFAR: mmio.Mmio(packed struct(u32) {
+            ///  Bus fault address
+            BFAR: u32,
+        }),
+        ///  Auxiliary fault status register
+        AFSR: mmio.Mmio(packed struct(u32) {
+            ///  Implementation defined
+            IMPDEF: u32,
+        }),
+    };
+
+    ///  SysTick timer
+    pub const STK = extern struct {
+        ///  SysTick control and status register
+        CTRL: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            ENABLE: u1,
+            ///  SysTick exception request enable
+            TICKINT: u1,
+            ///  Clock source selection
+            CLKSOURCE: u1,
+            reserved16: u13,
+            ///  COUNTFLAG
+            COUNTFLAG: u1,
+            padding: u15,
+        }),
+        ///  SysTick reload value register
+        LOAD: mmio.Mmio(packed struct(u32) {
+            ///  RELOAD value
+            RELOAD: u24,
+            padding: u8,
+        }),
+        ///  SysTick current value register
+        VAL: mmio.Mmio(packed struct(u32) {
+            ///  Current counter value
+            CURRENT: u24,
+            padding: u8,
+        }),
+        ///  SysTick calibration value register
+        CALIB: mmio.Mmio(packed struct(u32) {
+            ///  Calibration value
+            TENMS: u24,
+            reserved30: u6,
+            ///  SKEW flag: Indicates whether the TENMS value is exact
+            SKEW: u1,
+            ///  NOREF flag. Reads as zero
+            NOREF: u1,
+        }),
+    };
+
+    ///  Memory protection unit
+    pub const MPU = extern struct {
+        ///  MPU type register
+        MPU_TYPER: mmio.Mmio(packed struct(u32) {
+            ///  Separate flag
+            SEPARATE: u1,
+            reserved8: u7,
+            ///  Number of MPU data regions
+            DREGION: u8,
+            ///  Number of MPU instruction regions
+            IREGION: u8,
+            padding: u8,
+        }),
+        ///  MPU control register
+        MPU_CTRL: mmio.Mmio(packed struct(u32) {
+            ///  Enables the MPU
+            ENABLE: u1,
+            ///  Enables the operation of MPU during hard fault
+            HFNMIENA: u1,
+            ///  Enable priviliged software access to default memory map
+            PRIVDEFENA: u1,
+            padding: u29,
+        }),
+        ///  MPU region number register
+        MPU_RNR: mmio.Mmio(packed struct(u32) {
+            ///  MPU region
+            REGION: u8,
+            padding: u24,
+        }),
+        ///  MPU region base address register
+        MPU_RBAR: mmio.Mmio(packed struct(u32) {
+            ///  MPU region field
+            REGION: u4,
+            ///  MPU region number valid
+            VALID: u1,
+            ///  Region base address field
+            ADDR: u27,
+        }),
+        ///  MPU region attribute and size register
+        MPU_RASR: mmio.Mmio(packed struct(u32) {
+            ///  Region enable bit.
+            ENABLE: u1,
+            ///  Size of the MPU protection region
+            SIZE: u5,
+            reserved8: u2,
+            ///  Subregion disable bits
+            SRD: u8,
+            ///  memory attribute
+            B: u1,
+            ///  memory attribute
+            C: u1,
+            ///  Shareable memory attribute
+            S: u1,
+            ///  memory attribute
+            TEX: u3,
+            reserved24: u2,
+            ///  Access permission
+            AP: u3,
+            reserved28: u1,
+            ///  Instruction access disable bit
+            XN: u1,
+            padding: u3,
+        }),
+    };
+
+    ///  Touch sensing controller
+    pub const TSC = extern struct {
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Touch sensing controller enable
+            TSCE: u1,
+            ///  Start a new acquisition
+            START: u1,
+            ///  Acquisition mode
+            AM: u1,
+            ///  Synchronization pin polarity
+            SYNCPOL: u1,
+            ///  I/O Default mode
+            IODEF: u1,
+            ///  Max count value
+            MCV: u3,
+            reserved12: u4,
+            ///  pulse generator prescaler
+            PGPSC: u3,
+            ///  Spread spectrum prescaler
+            SSPSC: u1,
+            ///  Spread spectrum enable
+            SSE: u1,
+            ///  Spread spectrum deviation
+            SSD: u7,
+            ///  Charge transfer pulse low
+            CTPL: u4,
+            ///  Charge transfer pulse high
+            CTPH: u4,
+        }),
+        ///  interrupt enable register
+        IER: mmio.Mmio(packed struct(u32) {
+            ///  End of acquisition interrupt enable
+            EOAIE: u1,
+            ///  Max count error interrupt enable
+            MCEIE: u1,
+            padding: u30,
+        }),
+        ///  interrupt clear register
+        ICR: mmio.Mmio(packed struct(u32) {
+            ///  End of acquisition interrupt clear
+            EOAIC: u1,
+            ///  Max count error interrupt clear
+            MCEIC: u1,
+            padding: u30,
+        }),
+        ///  interrupt status register
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  End of acquisition flag
+            EOAF: u1,
+            ///  Max count error flag
+            MCEF: u1,
+            padding: u30,
+        }),
+        ///  I/O hysteresis control register
+        IOHCR: mmio.Mmio(packed struct(u32) {
+            ///  G1_IO1 Schmitt trigger hysteresis mode
+            G1_IO1: u1,
+            ///  G1_IO2 Schmitt trigger hysteresis mode
+            G1_IO2: u1,
+            ///  G1_IO3 Schmitt trigger hysteresis mode
+            G1_IO3: u1,
+            ///  G1_IO4 Schmitt trigger hysteresis mode
+            G1_IO4: u1,
+            ///  G2_IO1 Schmitt trigger hysteresis mode
+            G2_IO1: u1,
+            ///  G2_IO2 Schmitt trigger hysteresis mode
+            G2_IO2: u1,
+            ///  G2_IO3 Schmitt trigger hysteresis mode
+            G2_IO3: u1,
+            ///  G2_IO4 Schmitt trigger hysteresis mode
+            G2_IO4: u1,
+            ///  G3_IO1 Schmitt trigger hysteresis mode
+            G3_IO1: u1,
+            ///  G3_IO2 Schmitt trigger hysteresis mode
+            G3_IO2: u1,
+            ///  G3_IO3 Schmitt trigger hysteresis mode
+            G3_IO3: u1,
+            ///  G3_IO4 Schmitt trigger hysteresis mode
+            G3_IO4: u1,
+            ///  G4_IO1 Schmitt trigger hysteresis mode
+            G4_IO1: u1,
+            ///  G4_IO2 Schmitt trigger hysteresis mode
+            G4_IO2: u1,
+            ///  G4_IO3 Schmitt trigger hysteresis mode
+            G4_IO3: u1,
+            ///  G4_IO4 Schmitt trigger hysteresis mode
+            G4_IO4: u1,
+            ///  G5_IO1 Schmitt trigger hysteresis mode
+            G5_IO1: u1,
+            ///  G5_IO2 Schmitt trigger hysteresis mode
+            G5_IO2: u1,
+            ///  G5_IO3 Schmitt trigger hysteresis mode
+            G5_IO3: u1,
+            ///  G5_IO4 Schmitt trigger hysteresis mode
+            G5_IO4: u1,
+            ///  G6_IO1 Schmitt trigger hysteresis mode
+            G6_IO1: u1,
+            ///  G6_IO2 Schmitt trigger hysteresis mode
+            G6_IO2: u1,
+            ///  G6_IO3 Schmitt trigger hysteresis mode
+            G6_IO3: u1,
+            ///  G6_IO4 Schmitt trigger hysteresis mode
+            G6_IO4: u1,
+            ///  G7_IO1 Schmitt trigger hysteresis mode
+            G7_IO1: u1,
+            ///  G7_IO2 Schmitt trigger hysteresis mode
+            G7_IO2: u1,
+            ///  G7_IO3 Schmitt trigger hysteresis mode
+            G7_IO3: u1,
+            ///  G7_IO4 Schmitt trigger hysteresis mode
+            G7_IO4: u1,
+            ///  G8_IO1 Schmitt trigger hysteresis mode
+            G8_IO1: u1,
+            ///  G8_IO2 Schmitt trigger hysteresis mode
+            G8_IO2: u1,
+            ///  G8_IO3 Schmitt trigger hysteresis mode
+            G8_IO3: u1,
+            ///  G8_IO4 Schmitt trigger hysteresis mode
+            G8_IO4: u1,
+        }),
+        reserved24: [4]u8,
+        ///  I/O analog switch control register
+        IOASCR: mmio.Mmio(packed struct(u32) {
+            ///  G1_IO1 analog switch enable
+            G1_IO1: u1,
+            ///  G1_IO2 analog switch enable
+            G1_IO2: u1,
+            ///  G1_IO3 analog switch enable
+            G1_IO3: u1,
+            ///  G1_IO4 analog switch enable
+            G1_IO4: u1,
+            ///  G2_IO1 analog switch enable
+            G2_IO1: u1,
+            ///  G2_IO2 analog switch enable
+            G2_IO2: u1,
+            ///  G2_IO3 analog switch enable
+            G2_IO3: u1,
+            ///  G2_IO4 analog switch enable
+            G2_IO4: u1,
+            ///  G3_IO1 analog switch enable
+            G3_IO1: u1,
+            ///  G3_IO2 analog switch enable
+            G3_IO2: u1,
+            ///  G3_IO3 analog switch enable
+            G3_IO3: u1,
+            ///  G3_IO4 analog switch enable
+            G3_IO4: u1,
+            ///  G4_IO1 analog switch enable
+            G4_IO1: u1,
+            ///  G4_IO2 analog switch enable
+            G4_IO2: u1,
+            ///  G4_IO3 analog switch enable
+            G4_IO3: u1,
+            ///  G4_IO4 analog switch enable
+            G4_IO4: u1,
+            ///  G5_IO1 analog switch enable
+            G5_IO1: u1,
+            ///  G5_IO2 analog switch enable
+            G5_IO2: u1,
+            ///  G5_IO3 analog switch enable
+            G5_IO3: u1,
+            ///  G5_IO4 analog switch enable
+            G5_IO4: u1,
+            ///  G6_IO1 analog switch enable
+            G6_IO1: u1,
+            ///  G6_IO2 analog switch enable
+            G6_IO2: u1,
+            ///  G6_IO3 analog switch enable
+            G6_IO3: u1,
+            ///  G6_IO4 analog switch enable
+            G6_IO4: u1,
+            ///  G7_IO1 analog switch enable
+            G7_IO1: u1,
+            ///  G7_IO2 analog switch enable
+            G7_IO2: u1,
+            ///  G7_IO3 analog switch enable
+            G7_IO3: u1,
+            ///  G7_IO4 analog switch enable
+            G7_IO4: u1,
+            ///  G8_IO1 analog switch enable
+            G8_IO1: u1,
+            ///  G8_IO2 analog switch enable
+            G8_IO2: u1,
+            ///  G8_IO3 analog switch enable
+            G8_IO3: u1,
+            ///  G8_IO4 analog switch enable
+            G8_IO4: u1,
+        }),
+        reserved32: [4]u8,
+        ///  I/O sampling control register
+        IOSCR: mmio.Mmio(packed struct(u32) {
+            ///  G1_IO1 sampling mode
+            G1_IO1: u1,
+            ///  G1_IO2 sampling mode
+            G1_IO2: u1,
+            ///  G1_IO3 sampling mode
+            G1_IO3: u1,
+            ///  G1_IO4 sampling mode
+            G1_IO4: u1,
+            ///  G2_IO1 sampling mode
+            G2_IO1: u1,
+            ///  G2_IO2 sampling mode
+            G2_IO2: u1,
+            ///  G2_IO3 sampling mode
+            G2_IO3: u1,
+            ///  G2_IO4 sampling mode
+            G2_IO4: u1,
+            ///  G3_IO1 sampling mode
+            G3_IO1: u1,
+            ///  G3_IO2 sampling mode
+            G3_IO2: u1,
+            ///  G3_IO3 sampling mode
+            G3_IO3: u1,
+            ///  G3_IO4 sampling mode
+            G3_IO4: u1,
+            ///  G4_IO1 sampling mode
+            G4_IO1: u1,
+            ///  G4_IO2 sampling mode
+            G4_IO2: u1,
+            ///  G4_IO3 sampling mode
+            G4_IO3: u1,
+            ///  G4_IO4 sampling mode
+            G4_IO4: u1,
+            ///  G5_IO1 sampling mode
+            G5_IO1: u1,
+            ///  G5_IO2 sampling mode
+            G5_IO2: u1,
+            ///  G5_IO3 sampling mode
+            G5_IO3: u1,
+            ///  G5_IO4 sampling mode
+            G5_IO4: u1,
+            ///  G6_IO1 sampling mode
+            G6_IO1: u1,
+            ///  G6_IO2 sampling mode
+            G6_IO2: u1,
+            ///  G6_IO3 sampling mode
+            G6_IO3: u1,
+            ///  G6_IO4 sampling mode
+            G6_IO4: u1,
+            ///  G7_IO1 sampling mode
+            G7_IO1: u1,
+            ///  G7_IO2 sampling mode
+            G7_IO2: u1,
+            ///  G7_IO3 sampling mode
+            G7_IO3: u1,
+            ///  G7_IO4 sampling mode
+            G7_IO4: u1,
+            ///  G8_IO1 sampling mode
+            G8_IO1: u1,
+            ///  G8_IO2 sampling mode
+            G8_IO2: u1,
+            ///  G8_IO3 sampling mode
+            G8_IO3: u1,
+            ///  G8_IO4 sampling mode
+            G8_IO4: u1,
+        }),
+        reserved40: [4]u8,
+        ///  I/O channel control register
+        IOCCR: mmio.Mmio(packed struct(u32) {
+            ///  G1_IO1 channel mode
+            G1_IO1: u1,
+            ///  G1_IO2 channel mode
+            G1_IO2: u1,
+            ///  G1_IO3 channel mode
+            G1_IO3: u1,
+            ///  G1_IO4 channel mode
+            G1_IO4: u1,
+            ///  G2_IO1 channel mode
+            G2_IO1: u1,
+            ///  G2_IO2 channel mode
+            G2_IO2: u1,
+            ///  G2_IO3 channel mode
+            G2_IO3: u1,
+            ///  G2_IO4 channel mode
+            G2_IO4: u1,
+            ///  G3_IO1 channel mode
+            G3_IO1: u1,
+            ///  G3_IO2 channel mode
+            G3_IO2: u1,
+            ///  G3_IO3 channel mode
+            G3_IO3: u1,
+            ///  G3_IO4 channel mode
+            G3_IO4: u1,
+            ///  G4_IO1 channel mode
+            G4_IO1: u1,
+            ///  G4_IO2 channel mode
+            G4_IO2: u1,
+            ///  G4_IO3 channel mode
+            G4_IO3: u1,
+            ///  G4_IO4 channel mode
+            G4_IO4: u1,
+            ///  G5_IO1 channel mode
+            G5_IO1: u1,
+            ///  G5_IO2 channel mode
+            G5_IO2: u1,
+            ///  G5_IO3 channel mode
+            G5_IO3: u1,
+            ///  G5_IO4 channel mode
+            G5_IO4: u1,
+            ///  G6_IO1 channel mode
+            G6_IO1: u1,
+            ///  G6_IO2 channel mode
+            G6_IO2: u1,
+            ///  G6_IO3 channel mode
+            G6_IO3: u1,
+            ///  G6_IO4 channel mode
+            G6_IO4: u1,
+            ///  G7_IO1 channel mode
+            G7_IO1: u1,
+            ///  G7_IO2 channel mode
+            G7_IO2: u1,
+            ///  G7_IO3 channel mode
+            G7_IO3: u1,
+            ///  G7_IO4 channel mode
+            G7_IO4: u1,
+            ///  G8_IO1 channel mode
+            G8_IO1: u1,
+            ///  G8_IO2 channel mode
+            G8_IO2: u1,
+            ///  G8_IO3 channel mode
+            G8_IO3: u1,
+            ///  G8_IO4 channel mode
+            G8_IO4: u1,
+        }),
+        reserved48: [4]u8,
+        ///  I/O group control status register
+        IOGCSR: mmio.Mmio(packed struct(u32) {
+            ///  Analog I/O group x enable
+            G1E: u1,
+            ///  Analog I/O group x enable
+            G2E: u1,
+            ///  Analog I/O group x enable
+            G3E: u1,
+            ///  Analog I/O group x enable
+            G4E: u1,
+            ///  Analog I/O group x enable
+            G5E: u1,
+            ///  Analog I/O group x enable
+            G6E: u1,
+            ///  Analog I/O group x enable
+            G7E: u1,
+            ///  Analog I/O group x enable
+            G8E: u1,
+            reserved16: u8,
+            ///  Analog I/O group x status
+            G1S: u1,
+            ///  Analog I/O group x status
+            G2S: u1,
+            ///  Analog I/O group x status
+            G3S: u1,
+            ///  Analog I/O group x status
+            G4S: u1,
+            ///  Analog I/O group x status
+            G5S: u1,
+            ///  Analog I/O group x status
+            G6S: u1,
+            ///  Analog I/O group x status
+            G7S: u1,
+            ///  Analog I/O group x status
+            G8S: u1,
+            padding: u8,
+        }),
+        ///  I/O group x counter register
+        IOG1CR: mmio.Mmio(packed struct(u32) {
+            ///  Counter value
+            CNT: u14,
+            padding: u18,
+        }),
+        ///  I/O group x counter register
+        IOG2CR: mmio.Mmio(packed struct(u32) {
+            ///  Counter value
+            CNT: u14,
+            padding: u18,
+        }),
+        ///  I/O group x counter register
+        IOG3CR: mmio.Mmio(packed struct(u32) {
+            ///  Counter value
+            CNT: u14,
+            padding: u18,
+        }),
+        ///  I/O group x counter register
+        IOG4CR: mmio.Mmio(packed struct(u32) {
+            ///  Counter value
+            CNT: u14,
+            padding: u18,
+        }),
+        ///  I/O group x counter register
+        IOG5CR: mmio.Mmio(packed struct(u32) {
+            ///  Counter value
+            CNT: u14,
+            padding: u18,
+        }),
+        ///  I/O group x counter register
+        IOG6CR: mmio.Mmio(packed struct(u32) {
+            ///  Counter value
+            CNT: u14,
+            padding: u18,
+        }),
+        ///  I/O group x counter register
+        IOG7CR: mmio.Mmio(packed struct(u32) {
+            ///  Counter value
+            CNT: u14,
+            padding: u18,
+        }),
+        ///  I/O group x counter register
+        IOG8CR: mmio.Mmio(packed struct(u32) {
+            ///  Counter value
+            CNT: u14,
+            padding: u18,
+        }),
+    };
+
+    ///  cyclic redundancy check calculation unit
+    pub const CRC = extern struct {
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data register bits
+            DR: u32,
+        }),
+        ///  Independent data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  General-purpose 8-bit data register bits
+            IDR: u8,
+            padding: u24,
+        }),
+        ///  Control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  reset bit
+            RESET: u1,
+            reserved3: u2,
+            ///  Polynomial size
+            POLYSIZE: u2,
+            ///  Reverse input data
+            REV_IN: u2,
+            ///  Reverse output data
+            REV_OUT: u1,
+            padding: u24,
+        }),
+        reserved16: [4]u8,
+        ///  Initial CRC value
+        INIT: mmio.Mmio(packed struct(u32) {
+            ///  Programmable initial CRC value
+            INIT: u32,
+        }),
+        ///  CRC polynomial
+        POL: mmio.Mmio(packed struct(u32) {
+            ///  Programmable polynomial
+            POL: u32,
+        }),
+    };
+
+    ///  Flash
+    pub const Flash = extern struct {
+        ///  Flash access control register
+        ACR: mmio.Mmio(packed struct(u32) {
+            ///  LATENCY
+            LATENCY: u3,
+            reserved4: u1,
+            ///  PRFTBE
+            PRFTBE: u1,
+            ///  PRFTBS
+            PRFTBS: u1,
+            padding: u26,
+        }),
+        ///  Flash key register
+        KEYR: mmio.Mmio(packed struct(u32) {
+            ///  Flash Key
+            FKEYR: u32,
+        }),
+        ///  Flash option key register
+        OPTKEYR: mmio.Mmio(packed struct(u32) {
+            ///  Option byte key
+            OPTKEYR: u32,
+        }),
+        ///  Flash status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Busy
+            BSY: u1,
+            reserved2: u1,
+            ///  Programming error
+            PGERR: u1,
+            reserved4: u1,
+            ///  Write protection error
+            WRPRT: u1,
+            ///  End of operation
+            EOP: u1,
+            padding: u26,
+        }),
+        ///  Flash control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Programming
+            PG: u1,
+            ///  Page erase
+            PER: u1,
+            ///  Mass erase
+            MER: u1,
+            reserved4: u1,
+            ///  Option byte programming
+            OPTPG: u1,
+            ///  Option byte erase
+            OPTER: u1,
+            ///  Start
+            STRT: u1,
+            ///  Lock
+            LOCK: u1,
+            reserved9: u1,
+            ///  Option bytes write enable
+            OPTWRE: u1,
+            ///  Error interrupt enable
+            ERRIE: u1,
+            reserved12: u1,
+            ///  End of operation interrupt enable
+            EOPIE: u1,
+            ///  Force option byte loading
+            FORCE_OPTLOAD: u1,
+            padding: u18,
+        }),
+        ///  Flash address register
+        AR: mmio.Mmio(packed struct(u32) {
+            ///  Flash address
+            FAR: u32,
+        }),
+        reserved28: [4]u8,
+        ///  Option byte register
+        OBR: mmio.Mmio(packed struct(u32) {
+            ///  Option byte error
+            OPTERR: u1,
+            ///  Level 1 protection status
+            LEVEL1_PROT: u1,
+            ///  Level 2 protection status
+            LEVEL2_PROT: u1,
+            reserved8: u5,
+            ///  WDG_SW
+            WDG_SW: u1,
+            ///  nRST_STOP
+            nRST_STOP: u1,
+            ///  nRST_STDBY
+            nRST_STDBY: u1,
+            reserved12: u1,
+            ///  BOOT1
+            BOOT1: u1,
+            ///  VDDA_MONITOR
+            VDDA_MONITOR: u1,
+            ///  SRAM_PARITY_CHECK
+            SRAM_PARITY_CHECK: u1,
+            reserved16: u1,
+            ///  Data0
+            Data0: u8,
+            ///  Data1
+            Data1: u8,
+        }),
+        ///  Write protection register
+        WRPR: mmio.Mmio(packed struct(u32) {
+            ///  Write protect
+            WRP: u32,
+        }),
+    };
+
+    ///  Reset and clock control
+    pub const RCC = extern struct {
+        ///  Clock control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Internal High Speed clock enable
+            HSION: u1,
+            ///  Internal High Speed clock ready flag
+            HSIRDY: u1,
+            reserved3: u1,
+            ///  Internal High Speed clock trimming
+            HSITRIM: u5,
+            ///  Internal High Speed clock Calibration
+            HSICAL: u8,
+            ///  External High Speed clock enable
+            HSEON: u1,
+            ///  External High Speed clock ready flag
+            HSERDY: u1,
+            ///  External High Speed clock Bypass
+            HSEBYP: u1,
+            ///  Clock Security System enable
+            CSSON: u1,
+            reserved24: u4,
+            ///  PLL enable
+            PLLON: u1,
+            ///  PLL clock ready flag
+            PLLRDY: u1,
+            padding: u6,
+        }),
+        ///  Clock configuration register (RCC_CFGR)
+        CFGR: mmio.Mmio(packed struct(u32) {
+            ///  System clock Switch
+            SW: u2,
+            ///  System Clock Switch Status
+            SWS: u2,
+            ///  AHB prescaler
+            HPRE: u4,
+            ///  APB Low speed prescaler (APB1)
+            PPRE1: u3,
+            ///  APB high speed prescaler (APB2)
+            PPRE2: u3,
+            reserved15: u1,
+            ///  PLL entry clock source
+            PLLSRC: u2,
+            ///  HSE divider for PLL entry
+            PLLXTPRE: u1,
+            ///  PLL Multiplication Factor
+            PLLMUL: u4,
+            ///  USB prescaler
+            USBPRES: u1,
+            ///  I2S external clock source selection
+            I2SSRC: u1,
+            ///  Microcontroller clock output
+            MCO: u3,
+            reserved28: u1,
+            ///  Microcontroller Clock Output Flag
+            MCOF: u1,
+            padding: u3,
+        }),
+        ///  Clock interrupt register (RCC_CIR)
+        CIR: mmio.Mmio(packed struct(u32) {
+            ///  LSI Ready Interrupt flag
+            LSIRDYF: u1,
+            ///  LSE Ready Interrupt flag
+            LSERDYF: u1,
+            ///  HSI Ready Interrupt flag
+            HSIRDYF: u1,
+            ///  HSE Ready Interrupt flag
+            HSERDYF: u1,
+            ///  PLL Ready Interrupt flag
+            PLLRDYF: u1,
+            reserved7: u2,
+            ///  Clock Security System Interrupt flag
+            CSSF: u1,
+            ///  LSI Ready Interrupt Enable
+            LSIRDYIE: u1,
+            ///  LSE Ready Interrupt Enable
+            LSERDYIE: u1,
+            ///  HSI Ready Interrupt Enable
+            HSIRDYIE: u1,
+            ///  HSE Ready Interrupt Enable
+            HSERDYIE: u1,
+            ///  PLL Ready Interrupt Enable
+            PLLRDYIE: u1,
+            reserved16: u3,
+            ///  LSI Ready Interrupt Clear
+            LSIRDYC: u1,
+            ///  LSE Ready Interrupt Clear
+            LSERDYC: u1,
+            ///  HSI Ready Interrupt Clear
+            HSIRDYC: u1,
+            ///  HSE Ready Interrupt Clear
+            HSERDYC: u1,
+            ///  PLL Ready Interrupt Clear
+            PLLRDYC: u1,
+            reserved23: u2,
+            ///  Clock security system interrupt clear
+            CSSC: u1,
+            padding: u8,
+        }),
+        ///  APB2 peripheral reset register (RCC_APB2RSTR)
+        APB2RSTR: mmio.Mmio(packed struct(u32) {
+            ///  SYSCFG and COMP reset
+            SYSCFGRST: u1,
+            reserved11: u10,
+            ///  TIM1 timer reset
+            TIM1RST: u1,
+            ///  SPI 1 reset
+            SPI1RST: u1,
+            ///  TIM8 timer reset
+            TIM8RST: u1,
+            ///  USART1 reset
+            USART1RST: u1,
+            reserved16: u1,
+            ///  TIM15 timer reset
+            TIM15RST: u1,
+            ///  TIM16 timer reset
+            TIM16RST: u1,
+            ///  TIM17 timer reset
+            TIM17RST: u1,
+            padding: u13,
+        }),
+        ///  APB1 peripheral reset register (RCC_APB1RSTR)
+        APB1RSTR: mmio.Mmio(packed struct(u32) {
+            ///  Timer 2 reset
+            TIM2RST: u1,
+            ///  Timer 3 reset
+            TIM3RST: u1,
+            ///  Timer 14 reset
+            TIM4RST: u1,
+            reserved4: u1,
+            ///  Timer 6 reset
+            TIM6RST: u1,
+            ///  Timer 7 reset
+            TIM7RST: u1,
+            reserved11: u5,
+            ///  Window watchdog reset
+            WWDGRST: u1,
+            reserved14: u2,
+            ///  SPI2 reset
+            SPI2RST: u1,
+            ///  SPI3 reset
+            SPI3RST: u1,
+            reserved17: u1,
+            ///  USART 2 reset
+            USART2RST: u1,
+            ///  USART3 reset
+            USART3RST: u1,
+            ///  UART 4 reset
+            UART4RST: u1,
+            ///  UART 5 reset
+            UART5RST: u1,
+            ///  I2C1 reset
+            I2C1RST: u1,
+            ///  I2C2 reset
+            I2C2RST: u1,
+            ///  USB reset
+            USBRST: u1,
+            reserved25: u1,
+            ///  CAN reset
+            CANRST: u1,
+            reserved28: u2,
+            ///  Power interface reset
+            PWRRST: u1,
+            ///  DAC interface reset
+            DACRST: u1,
+            ///  I2C3 reset
+            I2C3RST: u1,
+            padding: u1,
+        }),
+        ///  AHB Peripheral Clock enable register (RCC_AHBENR)
+        AHBENR: mmio.Mmio(packed struct(u32) {
+            ///  DMA1 clock enable
+            DMAEN: u1,
+            ///  DMA2 clock enable
+            DMA2EN: u1,
+            ///  SRAM interface clock enable
+            SRAMEN: u1,
+            reserved4: u1,
+            ///  FLITF clock enable
+            FLITFEN: u1,
+            ///  FMC clock enable
+            FMCEN: u1,
+            ///  CRC clock enable
+            CRCEN: u1,
+            reserved16: u9,
+            ///  IO port H clock enable
+            IOPHEN: u1,
+            ///  I/O port A clock enable
+            IOPAEN: u1,
+            ///  I/O port B clock enable
+            IOPBEN: u1,
+            ///  I/O port C clock enable
+            IOPCEN: u1,
+            ///  I/O port D clock enable
+            IOPDEN: u1,
+            ///  I/O port E clock enable
+            IOPEEN: u1,
+            ///  I/O port F clock enable
+            IOPFEN: u1,
+            ///  I/O port G clock enable
+            IOPGEN: u1,
+            ///  Touch sensing controller clock enable
+            TSCEN: u1,
+            reserved28: u3,
+            ///  ADC1 and ADC2 clock enable
+            ADC12EN: u1,
+            ///  ADC3 and ADC4 clock enable
+            ADC34EN: u1,
+            padding: u2,
+        }),
+        ///  APB2 peripheral clock enable register (RCC_APB2ENR)
+        APB2ENR: mmio.Mmio(packed struct(u32) {
+            ///  SYSCFG clock enable
+            SYSCFGEN: u1,
+            reserved11: u10,
+            ///  TIM1 Timer clock enable
+            TIM1EN: u1,
+            ///  SPI 1 clock enable
+            SPI1EN: u1,
+            ///  TIM8 Timer clock enable
+            TIM8EN: u1,
+            ///  USART1 clock enable
+            USART1EN: u1,
+            reserved16: u1,
+            ///  TIM15 timer clock enable
+            TIM15EN: u1,
+            ///  TIM16 timer clock enable
+            TIM16EN: u1,
+            ///  TIM17 timer clock enable
+            TIM17EN: u1,
+            padding: u13,
+        }),
+        ///  APB1 peripheral clock enable register (RCC_APB1ENR)
+        APB1ENR: mmio.Mmio(packed struct(u32) {
+            ///  Timer 2 clock enable
+            TIM2EN: u1,
+            ///  Timer 3 clock enable
+            TIM3EN: u1,
+            ///  Timer 4 clock enable
+            TIM4EN: u1,
+            reserved4: u1,
+            ///  Timer 6 clock enable
+            TIM6EN: u1,
+            ///  Timer 7 clock enable
+            TIM7EN: u1,
+            reserved11: u5,
+            ///  Window watchdog clock enable
+            WWDGEN: u1,
+            reserved14: u2,
+            ///  SPI 2 clock enable
+            SPI2EN: u1,
+            ///  SPI 3 clock enable
+            SPI3EN: u1,
+            reserved17: u1,
+            ///  USART 2 clock enable
+            USART2EN: u1,
+            ///  USART 3 clock enable
+            USART3EN: u1,
+            ///  USART 4 clock enable
+            USART4EN: u1,
+            ///  USART 5 clock enable
+            USART5EN: u1,
+            ///  I2C 1 clock enable
+            I2C1EN: u1,
+            ///  I2C 2 clock enable
+            I2C2EN: u1,
+            ///  USB clock enable
+            USBEN: u1,
+            reserved25: u1,
+            ///  CAN clock enable
+            CANEN: u1,
+            ///  DAC2 interface clock enable
+            DAC2EN: u1,
+            reserved28: u1,
+            ///  Power interface clock enable
+            PWREN: u1,
+            ///  DAC interface clock enable
+            DACEN: u1,
+            ///  I2C3 clock enable
+            I2C3EN: u1,
+            padding: u1,
+        }),
+        ///  Backup domain control register (RCC_BDCR)
+        BDCR: mmio.Mmio(packed struct(u32) {
+            ///  External Low Speed oscillator enable
+            LSEON: u1,
+            ///  External Low Speed oscillator ready
+            LSERDY: u1,
+            ///  External Low Speed oscillator bypass
+            LSEBYP: u1,
+            ///  LSE oscillator drive capability
+            LSEDRV: u2,
+            reserved8: u3,
+            ///  RTC clock source selection
+            RTCSEL: u2,
+            reserved15: u5,
+            ///  RTC clock enable
+            RTCEN: u1,
+            ///  Backup domain software reset
+            BDRST: u1,
+            padding: u15,
+        }),
+        ///  Control/status register (RCC_CSR)
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  Internal low speed oscillator enable
+            LSION: u1,
+            ///  Internal low speed oscillator ready
+            LSIRDY: u1,
+            reserved24: u22,
+            ///  Remove reset flag
+            RMVF: u1,
+            ///  Option byte loader reset flag
+            OBLRSTF: u1,
+            ///  PIN reset flag
+            PINRSTF: u1,
+            ///  POR/PDR reset flag
+            PORRSTF: u1,
+            ///  Software reset flag
+            SFTRSTF: u1,
+            ///  Independent watchdog reset flag
+            IWDGRSTF: u1,
+            ///  Window watchdog reset flag
+            WWDGRSTF: u1,
+            ///  Low-power reset flag
+            LPWRRSTF: u1,
+        }),
+        ///  AHB peripheral reset register
+        AHBRSTR: mmio.Mmio(packed struct(u32) {
+            reserved5: u5,
+            ///  FMC reset
+            FMCRST: u1,
+            reserved16: u10,
+            ///  I/O port H reset
+            IOPHRST: u1,
+            ///  I/O port A reset
+            IOPARST: u1,
+            ///  I/O port B reset
+            IOPBRST: u1,
+            ///  I/O port C reset
+            IOPCRST: u1,
+            ///  I/O port D reset
+            IOPDRST: u1,
+            ///  I/O port E reset
+            IOPERST: u1,
+            ///  I/O port F reset
+            IOPFRST: u1,
+            ///  Touch sensing controller reset
+            IOPGRST: u1,
+            ///  Touch sensing controller reset
+            TSCRST: u1,
+            reserved28: u3,
+            ///  ADC1 and ADC2 reset
+            ADC12RST: u1,
+            ///  ADC3 and ADC4 reset
+            ADC34RST: u1,
+            padding: u2,
+        }),
+        ///  Clock configuration register 2
+        CFGR2: mmio.Mmio(packed struct(u32) {
+            ///  PREDIV division factor
+            PREDIV: u4,
+            ///  ADC1 and ADC2 prescaler
+            ADC12PRES: u5,
+            ///  ADC3 and ADC4 prescaler
+            ADC34PRES: u5,
+            padding: u18,
+        }),
+        ///  Clock configuration register 3
+        CFGR3: mmio.Mmio(packed struct(u32) {
+            ///  USART1 clock source selection
+            USART1SW: u2,
+            reserved4: u2,
+            ///  I2C1 clock source selection
+            I2C1SW: u1,
+            ///  I2C2 clock source selection
+            I2C2SW: u1,
+            ///  I2C3 clock source selection
+            I2C3SW: u1,
+            reserved8: u1,
+            ///  Timer1 clock source selection
+            TIM1SW: u1,
+            ///  Timer8 clock source selection
+            TIM8SW: u1,
+            reserved16: u6,
+            ///  USART2 clock source selection
+            USART2SW: u2,
+            ///  USART3 clock source selection
+            USART3SW: u2,
+            ///  UART4 clock source selection
+            UART4SW: u2,
+            ///  UART5 clock source selection
+            UART5SW: u2,
+            padding: u8,
+        }),
+    };
+
+    ///  DMA controller 1
+    pub const DMA1 = extern struct {
+        ///  DMA interrupt status register (DMA_ISR)
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  Channel 1 Global interrupt flag
+            GIF1: u1,
+            ///  Channel 1 Transfer Complete flag
+            TCIF1: u1,
+            ///  Channel 1 Half Transfer Complete flag
+            HTIF1: u1,
+            ///  Channel 1 Transfer Error flag
+            TEIF1: u1,
+            ///  Channel 2 Global interrupt flag
+            GIF2: u1,
+            ///  Channel 2 Transfer Complete flag
+            TCIF2: u1,
+            ///  Channel 2 Half Transfer Complete flag
+            HTIF2: u1,
+            ///  Channel 2 Transfer Error flag
+            TEIF2: u1,
+            ///  Channel 3 Global interrupt flag
+            GIF3: u1,
+            ///  Channel 3 Transfer Complete flag
+            TCIF3: u1,
+            ///  Channel 3 Half Transfer Complete flag
+            HTIF3: u1,
+            ///  Channel 3 Transfer Error flag
+            TEIF3: u1,
+            ///  Channel 4 Global interrupt flag
+            GIF4: u1,
+            ///  Channel 4 Transfer Complete flag
+            TCIF4: u1,
+            ///  Channel 4 Half Transfer Complete flag
+            HTIF4: u1,
+            ///  Channel 4 Transfer Error flag
+            TEIF4: u1,
+            ///  Channel 5 Global interrupt flag
+            GIF5: u1,
+            ///  Channel 5 Transfer Complete flag
+            TCIF5: u1,
+            ///  Channel 5 Half Transfer Complete flag
+            HTIF5: u1,
+            ///  Channel 5 Transfer Error flag
+            TEIF5: u1,
+            ///  Channel 6 Global interrupt flag
+            GIF6: u1,
+            ///  Channel 6 Transfer Complete flag
+            TCIF6: u1,
+            ///  Channel 6 Half Transfer Complete flag
+            HTIF6: u1,
+            ///  Channel 6 Transfer Error flag
+            TEIF6: u1,
+            ///  Channel 7 Global interrupt flag
+            GIF7: u1,
+            ///  Channel 7 Transfer Complete flag
+            TCIF7: u1,
+            ///  Channel 7 Half Transfer Complete flag
+            HTIF7: u1,
+            ///  Channel 7 Transfer Error flag
+            TEIF7: u1,
+            padding: u4,
+        }),
+        ///  DMA interrupt flag clear register (DMA_IFCR)
+        IFCR: mmio.Mmio(packed struct(u32) {
+            ///  Channel 1 Global interrupt clear
+            CGIF1: u1,
+            ///  Channel 1 Transfer Complete clear
+            CTCIF1: u1,
+            ///  Channel 1 Half Transfer clear
+            CHTIF1: u1,
+            ///  Channel 1 Transfer Error clear
+            CTEIF1: u1,
+            ///  Channel 2 Global interrupt clear
+            CGIF2: u1,
+            ///  Channel 2 Transfer Complete clear
+            CTCIF2: u1,
+            ///  Channel 2 Half Transfer clear
+            CHTIF2: u1,
+            ///  Channel 2 Transfer Error clear
+            CTEIF2: u1,
+            ///  Channel 3 Global interrupt clear
+            CGIF3: u1,
+            ///  Channel 3 Transfer Complete clear
+            CTCIF3: u1,
+            ///  Channel 3 Half Transfer clear
+            CHTIF3: u1,
+            ///  Channel 3 Transfer Error clear
+            CTEIF3: u1,
+            ///  Channel 4 Global interrupt clear
+            CGIF4: u1,
+            ///  Channel 4 Transfer Complete clear
+            CTCIF4: u1,
+            ///  Channel 4 Half Transfer clear
+            CHTIF4: u1,
+            ///  Channel 4 Transfer Error clear
+            CTEIF4: u1,
+            ///  Channel 5 Global interrupt clear
+            CGIF5: u1,
+            ///  Channel 5 Transfer Complete clear
+            CTCIF5: u1,
+            ///  Channel 5 Half Transfer clear
+            CHTIF5: u1,
+            ///  Channel 5 Transfer Error clear
+            CTEIF5: u1,
+            ///  Channel 6 Global interrupt clear
+            CGIF6: u1,
+            ///  Channel 6 Transfer Complete clear
+            CTCIF6: u1,
+            ///  Channel 6 Half Transfer clear
+            CHTIF6: u1,
+            ///  Channel 6 Transfer Error clear
+            CTEIF6: u1,
+            ///  Channel 7 Global interrupt clear
+            CGIF7: u1,
+            ///  Channel 7 Transfer Complete clear
+            CTCIF7: u1,
+            ///  Channel 7 Half Transfer clear
+            CHTIF7: u1,
+            ///  Channel 7 Transfer Error clear
+            CTEIF7: u1,
+            padding: u4,
+        }),
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 1 number of data register
+        CNDTR1: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 1 peripheral address register
+        CPAR1: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 1 memory address register
+        CMAR1: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved28: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 2 number of data register
+        CNDTR2: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 2 peripheral address register
+        CPAR2: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 2 memory address register
+        CMAR2: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved48: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 3 number of data register
+        CNDTR3: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 3 peripheral address register
+        CPAR3: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 3 memory address register
+        CMAR3: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved68: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 4 number of data register
+        CNDTR4: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 4 peripheral address register
+        CPAR4: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 4 memory address register
+        CMAR4: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved88: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR5: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 5 number of data register
+        CNDTR5: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 5 peripheral address register
+        CPAR5: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 5 memory address register
+        CMAR5: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved108: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR6: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 6 number of data register
+        CNDTR6: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 6 peripheral address register
+        CPAR6: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 6 memory address register
+        CMAR6: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        reserved128: [4]u8,
+        ///  DMA channel configuration register (DMA_CCR)
+        CCR7: mmio.Mmio(packed struct(u32) {
+            ///  Channel enable
+            EN: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Half Transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Data transfer direction
+            DIR: u1,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral size
+            PSIZE: u2,
+            ///  Memory size
+            MSIZE: u2,
+            ///  Channel Priority level
+            PL: u2,
+            ///  Memory to memory mode
+            MEM2MEM: u1,
+            padding: u17,
+        }),
+        ///  DMA channel 7 number of data register
+        CNDTR7: mmio.Mmio(packed struct(u32) {
+            ///  Number of data to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  DMA channel 7 peripheral address register
+        CPAR7: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  DMA channel 7 memory address register
+        CMAR7: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+    };
+
+    ///  Floting point unit
+    pub const FPU = extern struct {
+        ///  Floating-point context control register
+        FPCCR: mmio.Mmio(packed struct(u32) {
+            ///  LSPACT
+            LSPACT: u1,
+            ///  USER
+            USER: u1,
+            reserved3: u1,
+            ///  THREAD
+            THREAD: u1,
+            ///  HFRDY
+            HFRDY: u1,
+            ///  MMRDY
+            MMRDY: u1,
+            ///  BFRDY
+            BFRDY: u1,
+            reserved8: u1,
+            ///  MONRDY
+            MONRDY: u1,
+            reserved30: u21,
+            ///  LSPEN
+            LSPEN: u1,
+            ///  ASPEN
+            ASPEN: u1,
+        }),
+        ///  Floating-point context address register
+        FPCAR: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Location of unpopulated floating-point
+            ADDRESS: u29,
+        }),
+        ///  Floating-point status control register
+        FPSCR: mmio.Mmio(packed struct(u32) {
+            ///  Invalid operation cumulative exception bit
+            IOC: u1,
+            ///  Division by zero cumulative exception bit.
+            DZC: u1,
+            ///  Overflow cumulative exception bit
+            OFC: u1,
+            ///  Underflow cumulative exception bit
+            UFC: u1,
+            ///  Inexact cumulative exception bit
+            IXC: u1,
+            reserved7: u2,
+            ///  Input denormal cumulative exception bit.
+            IDC: u1,
+            reserved22: u14,
+            ///  Rounding Mode control field
+            RMode: u2,
+            ///  Flush-to-zero mode control bit:
+            FZ: u1,
+            ///  Default NaN mode control bit
+            DN: u1,
+            ///  Alternative half-precision control bit
+            AHP: u1,
+            reserved28: u1,
+            ///  Overflow condition code flag
+            V: u1,
+            ///  Carry condition code flag
+            C: u1,
+            ///  Zero condition code flag
+            Z: u1,
+            ///  Negative condition code flag
+            N: u1,
+        }),
+    };
+
+    ///  General purpose timer
+    pub const TIM2 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            reserved11: u1,
+            ///  UIF status bit remapping
+            UIFREMAP: u1,
+            padding: u20,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            padding: u24,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            ///  OCREF clear selection
+            OCCS: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            ///  Slave mode selection bit3
+            SMS_3: u1,
+            padding: u15,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            reserved6: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            reserved8: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            reserved14: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            reserved6: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            reserved9: u2,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            padding: u19,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            reserved6: u1,
+            ///  Trigger generation
+            TG: u1,
+            padding: u25,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output compare 1 fast enable
+            OC1FE: u1,
+            ///  Output compare 1 preload enable
+            OC1PE: u1,
+            ///  Output compare 1 mode
+            OC1M: u3,
+            ///  Output compare 1 clear enable
+            OC1CE: u1,
+            ///  Capture/Compare 2 selection
+            CC2S: u2,
+            ///  Output compare 2 fast enable
+            OC2FE: u1,
+            ///  Output compare 2 preload enable
+            OC2PE: u1,
+            ///  Output compare 2 mode
+            OC2M: u3,
+            ///  Output compare 2 clear enable
+            OC2CE: u1,
+            ///  Output compare 1 mode bit 3
+            OC1M_3: u1,
+            reserved24: u7,
+            ///  Output compare 2 mode bit 3
+            OC2M_3: u1,
+            padding: u7,
+        }),
+        ///  capture/compare mode register 2 (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 3 selection
+            CC3S: u2,
+            ///  Output compare 3 fast enable
+            OC3FE: u1,
+            ///  Output compare 3 preload enable
+            OC3PE: u1,
+            ///  Output compare 3 mode
+            OC3M: u3,
+            ///  Output compare 3 clear enable
+            OC3CE: u1,
+            ///  Capture/Compare 4 selection
+            CC4S: u2,
+            ///  Output compare 4 fast enable
+            OC4FE: u1,
+            ///  Output compare 4 preload enable
+            OC4PE: u1,
+            ///  Output compare 4 mode
+            OC4M: u3,
+            ///  Output compare 4 clear enable
+            O24CE: u1,
+            ///  Output compare 3 mode bit3
+            OC3M_3: u1,
+            reserved24: u7,
+            ///  Output compare 4 mode bit3
+            OC4M_3: u1,
+            padding: u7,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved7: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            reserved11: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            reserved15: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4NP: u1,
+            padding: u16,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  Low counter value
+            CNTL: u16,
+            ///  High counter value
+            CNTH: u15,
+            ///  if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access
+            CNT_or_UIFCPY: u1,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Low Auto-reload value
+            ARRL: u16,
+            ///  High Auto-reload value
+            ARRH: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 1 value
+            CCR1L: u16,
+            ///  High Capture/Compare 1 value (on TIM2)
+            CCR1H: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 2 value
+            CCR2L: u16,
+            ///  High Capture/Compare 2 value (on TIM2)
+            CCR2H: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR3L: u16,
+            ///  High Capture/Compare value (on TIM2)
+            CCR3H: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR4L: u16,
+            ///  High Capture/Compare value (on TIM2)
+            CCR4H: u16,
+        }),
+        reserved72: [4]u8,
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Nested Vectored Interrupt Controller
+    pub const NVIC = extern struct {
+        ///  Interrupt Set-Enable Register
+        ISER0: mmio.Mmio(packed struct(u32) {
+            ///  SETENA
+            SETENA: u32,
+        }),
+        ///  Interrupt Set-Enable Register
+        ISER1: mmio.Mmio(packed struct(u32) {
+            ///  SETENA
+            SETENA: u32,
+        }),
+        ///  Interrupt Set-Enable Register
+        ISER2: mmio.Mmio(packed struct(u32) {
+            ///  SETENA
+            SETENA: u32,
+        }),
+        reserved128: [116]u8,
+        ///  Interrupt Clear-Enable Register
+        ICER0: mmio.Mmio(packed struct(u32) {
+            ///  CLRENA
+            CLRENA: u32,
+        }),
+        ///  Interrupt Clear-Enable Register
+        ICER1: mmio.Mmio(packed struct(u32) {
+            ///  CLRENA
+            CLRENA: u32,
+        }),
+        ///  Interrupt Clear-Enable Register
+        ICER2: mmio.Mmio(packed struct(u32) {
+            ///  CLRENA
+            CLRENA: u32,
+        }),
+        reserved256: [116]u8,
+        ///  Interrupt Set-Pending Register
+        ISPR0: mmio.Mmio(packed struct(u32) {
+            ///  SETPEND
+            SETPEND: u32,
+        }),
+        ///  Interrupt Set-Pending Register
+        ISPR1: mmio.Mmio(packed struct(u32) {
+            ///  SETPEND
+            SETPEND: u32,
+        }),
+        ///  Interrupt Set-Pending Register
+        ISPR2: mmio.Mmio(packed struct(u32) {
+            ///  SETPEND
+            SETPEND: u32,
+        }),
+        reserved384: [116]u8,
+        ///  Interrupt Clear-Pending Register
+        ICPR0: mmio.Mmio(packed struct(u32) {
+            ///  CLRPEND
+            CLRPEND: u32,
+        }),
+        ///  Interrupt Clear-Pending Register
+        ICPR1: mmio.Mmio(packed struct(u32) {
+            ///  CLRPEND
+            CLRPEND: u32,
+        }),
+        ///  Interrupt Clear-Pending Register
+        ICPR2: mmio.Mmio(packed struct(u32) {
+            ///  CLRPEND
+            CLRPEND: u32,
+        }),
+        reserved512: [116]u8,
+        ///  Interrupt Active Bit Register
+        IABR0: mmio.Mmio(packed struct(u32) {
+            ///  ACTIVE
+            ACTIVE: u32,
+        }),
+        ///  Interrupt Active Bit Register
+        IABR1: mmio.Mmio(packed struct(u32) {
+            ///  ACTIVE
+            ACTIVE: u32,
+        }),
+        ///  Interrupt Active Bit Register
+        IABR2: mmio.Mmio(packed struct(u32) {
+            ///  ACTIVE
+            ACTIVE: u32,
+        }),
+        reserved768: [244]u8,
+        ///  Interrupt Priority Register
+        IPR0: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR1: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR2: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR3: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR4: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR5: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR6: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR7: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR8: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR9: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR10: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR11: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR12: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR13: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR14: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR15: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR16: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR17: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR18: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR19: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR20: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+    };
+
+    ///  Flexible memory controller
+    pub const FMC = extern struct {
+        ///  SRAM/NOR-Flash chip-select control register 1
+        BCR1: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            reserved11: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            ///  CCLKEN
+            CCLKEN: u1,
+            padding: u11,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 1
+        BTR1: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 2
+        BCR2: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 2
+        BTR2: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 3
+        BCR3: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 3
+        BTR3: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 4
+        BCR4: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 4
+        BTR4: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved96: [64]u8,
+        ///  PC Card/NAND Flash control register 2
+        PCR2: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 2
+        SR2: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 2
+        PMEM2: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 2
+        PATT2: mmio.Mmio(packed struct(u32) {
+            ///  ATTSETx
+            ATTSETx: u8,
+            ///  ATTWAITx
+            ATTWAITx: u8,
+            ///  ATTHOLDx
+            ATTHOLDx: u8,
+            ///  ATTHIZx
+            ATTHIZx: u8,
+        }),
+        reserved116: [4]u8,
+        ///  ECC result register 2
+        ECCR2: mmio.Mmio(packed struct(u32) {
+            ///  ECCx
+            ECCx: u32,
+        }),
+        reserved128: [8]u8,
+        ///  PC Card/NAND Flash control register 3
+        PCR3: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 3
+        SR3: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 3
+        PMEM3: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 3
+        PATT3: mmio.Mmio(packed struct(u32) {
+            ///  ATTSETx
+            ATTSETx: u8,
+            ///  ATTWAITx
+            ATTWAITx: u8,
+            ///  ATTHOLDx
+            ATTHOLDx: u8,
+            ///  ATTHIZx
+            ATTHIZx: u8,
+        }),
+        reserved148: [4]u8,
+        ///  ECC result register 3
+        ECCR3: mmio.Mmio(packed struct(u32) {
+            ///  ECCx
+            ECCx: u32,
+        }),
+        reserved160: [8]u8,
+        ///  PC Card/NAND Flash control register 4
+        PCR4: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 4
+        SR4: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 4
+        PMEM4: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 4
+        PATT4: mmio.Mmio(packed struct(u32) {
+            ///  ATTSETx
+            ATTSETx: u8,
+            ///  ATTWAITx
+            ATTWAITx: u8,
+            ///  ATTHOLDx
+            ATTHOLDx: u8,
+            ///  ATTHIZx
+            ATTHIZx: u8,
+        }),
+        ///  I/O space timing register 4
+        PIO4: mmio.Mmio(packed struct(u32) {
+            ///  IOSETx
+            IOSETx: u8,
+            ///  IOWAITx
+            IOWAITx: u8,
+            ///  IOHOLDx
+            IOHOLDx: u8,
+            ///  IOHIZx
+            IOHIZx: u8,
+        }),
+        reserved260: [80]u8,
+        ///  SRAM/NOR-Flash write timing registers 1
+        BWTR1: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  Bus turnaround phase duration
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved268: [4]u8,
+        ///  SRAM/NOR-Flash write timing registers 2
+        BWTR2: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  Bus turnaround phase duration
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved276: [4]u8,
+        ///  SRAM/NOR-Flash write timing registers 3
+        BWTR3: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  Bus turnaround phase duration
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved284: [4]u8,
+        ///  SRAM/NOR-Flash write timing registers 4
+        BWTR4: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  Bus turnaround phase duration
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+    };
+
+    ///  General purpose timers
+    pub const TIM15 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            reserved7: u3,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            reserved11: u1,
+            ///  UIF status bit remapping
+            UIFREMAP: u1,
+            padding: u20,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/compare preloaded control
+            CCPC: u1,
+            reserved2: u1,
+            ///  Capture/compare control update selection
+            CCUS: u1,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            ///  Output Idle state 1
+            OIS1: u1,
+            ///  Output Idle state 1
+            OIS1N: u1,
+            ///  Output Idle state 2
+            OIS2: u1,
+            padding: u21,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            reserved16: u8,
+            ///  Slave mode selection bit 3
+            SMS_3: u1,
+            padding: u15,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            reserved5: u2,
+            ///  COM interrupt enable
+            COMIE: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            ///  Break interrupt enable
+            BIE: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            reserved13: u2,
+            ///  COM DMA request enable
+            COMDE: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            reserved5: u2,
+            ///  COM interrupt flag
+            COMIF: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            ///  Break interrupt flag
+            BIF: u1,
+            reserved9: u1,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            padding: u21,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            reserved5: u2,
+            ///  Capture/Compare control update generation
+            COMG: u1,
+            ///  Trigger generation
+            TG: u1,
+            ///  Break generation
+            BG: u1,
+            padding: u24,
+        }),
+        ///  capture/compare mode register (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            reserved8: u1,
+            ///  Capture/Compare 2 selection
+            CC2S: u2,
+            ///  Output Compare 2 fast enable
+            OC2FE: u1,
+            ///  Output Compare 2 preload enable
+            OC2PE: u1,
+            ///  Output Compare 2 mode
+            OC2M: u3,
+            reserved16: u1,
+            ///  Output Compare 1 mode bit 3
+            OC1M_3: u1,
+            reserved24: u7,
+            ///  Output Compare 2 mode bit 3
+            OC2M_3: u1,
+            padding: u7,
+        }),
+        reserved32: [4]u8,
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            ///  Capture/Compare 1 complementary output enable
+            CC1NE: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved7: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            padding: u24,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            reserved31: u15,
+            ///  UIF copy
+            UIFCPY: u1,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        ///  repetition counter register
+        RCR: mmio.Mmio(packed struct(u32) {
+            ///  Repetition counter value
+            REP: u8,
+            padding: u24,
+        }),
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 2 value
+            CCR2: u16,
+            padding: u16,
+        }),
+        reserved68: [8]u8,
+        ///  break and dead-time register
+        BDTR: mmio.Mmio(packed struct(u32) {
+            ///  Dead-time generator setup
+            DTG: u8,
+            ///  Lock configuration
+            LOCK: u2,
+            ///  Off-state selection for Idle mode
+            OSSI: u1,
+            ///  Off-state selection for Run mode
+            OSSR: u1,
+            ///  Break enable
+            BKE: u1,
+            ///  Break polarity
+            BKP: u1,
+            ///  Automatic output enable
+            AOE: u1,
+            ///  Main output enable
+            MOE: u1,
+            ///  Break filter
+            BKF: u4,
+            padding: u12,
+        }),
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  General-purpose-timers
+    pub const TIM16 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            reserved7: u3,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            reserved11: u1,
+            ///  UIF status bit remapping
+            UIFREMAP: u1,
+            padding: u20,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/compare preloaded control
+            CCPC: u1,
+            reserved2: u1,
+            ///  Capture/compare control update selection
+            CCUS: u1,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            reserved8: u4,
+            ///  Output Idle state 1
+            OIS1: u1,
+            ///  Output Idle state 1
+            OIS1N: u1,
+            padding: u22,
+        }),
+        reserved12: [4]u8,
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            reserved5: u3,
+            ///  COM interrupt enable
+            COMIE: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            ///  Break interrupt enable
+            BIE: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            reserved13: u3,
+            ///  COM DMA request enable
+            COMDE: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            reserved5: u3,
+            ///  COM interrupt flag
+            COMIF: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            ///  Break interrupt flag
+            BIF: u1,
+            reserved9: u1,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            padding: u22,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            reserved5: u3,
+            ///  Capture/Compare control update generation
+            COMG: u1,
+            ///  Trigger generation
+            TG: u1,
+            ///  Break generation
+            BG: u1,
+            padding: u24,
+        }),
+        ///  capture/compare mode register (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            reserved16: u9,
+            ///  Output Compare 1 mode
+            OC1M_3: u1,
+            padding: u15,
+        }),
+        reserved32: [4]u8,
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            ///  Capture/Compare 1 complementary output enable
+            CC1NE: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            padding: u28,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            reserved31: u15,
+            ///  UIF Copy
+            UIFCPY: u1,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        ///  repetition counter register
+        RCR: mmio.Mmio(packed struct(u32) {
+            ///  Repetition counter value
+            REP: u8,
+            padding: u24,
+        }),
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        reserved68: [12]u8,
+        ///  break and dead-time register
+        BDTR: mmio.Mmio(packed struct(u32) {
+            ///  Dead-time generator setup
+            DTG: u8,
+            ///  Lock configuration
+            LOCK: u2,
+            ///  Off-state selection for Idle mode
+            OSSI: u1,
+            ///  Off-state selection for Run mode
+            OSSR: u1,
+            ///  Break enable
+            BKE: u1,
+            ///  Break polarity
+            BKP: u1,
+            ///  Automatic output enable
+            AOE: u1,
+            ///  Main output enable
+            MOE: u1,
+            ///  Break filter
+            BKF: u4,
+            padding: u12,
+        }),
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+        ///  option register
+        OR: u32,
+    };
+
+    ///  General purpose timer
+    pub const TIM17 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            reserved7: u3,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            reserved11: u1,
+            ///  UIF status bit remapping
+            UIFREMAP: u1,
+            padding: u20,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/compare preloaded control
+            CCPC: u1,
+            reserved2: u1,
+            ///  Capture/compare control update selection
+            CCUS: u1,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            reserved8: u4,
+            ///  Output Idle state 1
+            OIS1: u1,
+            ///  Output Idle state 1
+            OIS1N: u1,
+            padding: u22,
+        }),
+        reserved12: [4]u8,
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            reserved5: u3,
+            ///  COM interrupt enable
+            COMIE: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            ///  Break interrupt enable
+            BIE: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            reserved13: u3,
+            ///  COM DMA request enable
+            COMDE: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            reserved5: u3,
+            ///  COM interrupt flag
+            COMIF: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            ///  Break interrupt flag
+            BIF: u1,
+            reserved9: u1,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            padding: u22,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            reserved5: u3,
+            ///  Capture/Compare control update generation
+            COMG: u1,
+            ///  Trigger generation
+            TG: u1,
+            ///  Break generation
+            BG: u1,
+            padding: u24,
+        }),
+        ///  capture/compare mode register (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            reserved16: u9,
+            ///  Output Compare 1 mode
+            OC1M_3: u1,
+            padding: u15,
+        }),
+        reserved32: [4]u8,
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            ///  Capture/Compare 1 complementary output enable
+            CC1NE: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            padding: u28,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            reserved31: u15,
+            ///  UIF Copy
+            UIFCPY: u1,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        ///  repetition counter register
+        RCR: mmio.Mmio(packed struct(u32) {
+            ///  Repetition counter value
+            REP: u8,
+            padding: u24,
+        }),
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        reserved68: [12]u8,
+        ///  break and dead-time register
+        BDTR: mmio.Mmio(packed struct(u32) {
+            ///  Dead-time generator setup
+            DTG: u8,
+            ///  Lock configuration
+            LOCK: u2,
+            ///  Off-state selection for Idle mode
+            OSSI: u1,
+            ///  Off-state selection for Run mode
+            OSSR: u1,
+            ///  Break enable
+            BKE: u1,
+            ///  Break polarity
+            BKP: u1,
+            ///  Automatic output enable
+            AOE: u1,
+            ///  Main output enable
+            MOE: u1,
+            ///  Break filter
+            BKF: u4,
+            padding: u12,
+        }),
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Universal synchronous asynchronous receiver transmitter
+    pub const USART1 = extern struct {
+        ///  Control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  USART enable
+            UE: u1,
+            ///  USART enable in Stop mode
+            UESM: u1,
+            ///  Receiver enable
+            RE: u1,
+            ///  Transmitter enable
+            TE: u1,
+            ///  IDLE interrupt enable
+            IDLEIE: u1,
+            ///  RXNE interrupt enable
+            RXNEIE: u1,
+            ///  Transmission complete interrupt enable
+            TCIE: u1,
+            ///  interrupt enable
+            TXEIE: u1,
+            ///  PE interrupt enable
+            PEIE: u1,
+            ///  Parity selection
+            PS: u1,
+            ///  Parity control enable
+            PCE: u1,
+            ///  Receiver wakeup method
+            WAKE: u1,
+            ///  Word length
+            M: u1,
+            ///  Mute mode enable
+            MME: u1,
+            ///  Character match interrupt enable
+            CMIE: u1,
+            ///  Oversampling mode
+            OVER8: u1,
+            ///  Driver Enable deassertion time
+            DEDT: u5,
+            ///  Driver Enable assertion time
+            DEAT: u5,
+            ///  Receiver timeout interrupt enable
+            RTOIE: u1,
+            ///  End of Block interrupt enable
+            EOBIE: u1,
+            padding: u4,
+        }),
+        ///  Control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  7-bit Address Detection/4-bit Address Detection
+            ADDM7: u1,
+            ///  LIN break detection length
+            LBDL: u1,
+            ///  LIN break detection interrupt enable
+            LBDIE: u1,
+            reserved8: u1,
+            ///  Last bit clock pulse
+            LBCL: u1,
+            ///  Clock phase
+            CPHA: u1,
+            ///  Clock polarity
+            CPOL: u1,
+            ///  Clock enable
+            CLKEN: u1,
+            ///  STOP bits
+            STOP: u2,
+            ///  LIN mode enable
+            LINEN: u1,
+            ///  Swap TX/RX pins
+            SWAP: u1,
+            ///  RX pin active level inversion
+            RXINV: u1,
+            ///  TX pin active level inversion
+            TXINV: u1,
+            ///  Binary data inversion
+            DATAINV: u1,
+            ///  Most significant bit first
+            MSBFIRST: u1,
+            ///  Auto baud rate enable
+            ABREN: u1,
+            ///  Auto baud rate mode
+            ABRMOD: u2,
+            ///  Receiver timeout enable
+            RTOEN: u1,
+            ///  Address of the USART node
+            ADD0: u4,
+            ///  Address of the USART node
+            ADD4: u4,
+        }),
+        ///  Control register 3
+        CR3: mmio.Mmio(packed struct(u32) {
+            ///  Error interrupt enable
+            EIE: u1,
+            ///  IrDA mode enable
+            IREN: u1,
+            ///  IrDA low-power
+            IRLP: u1,
+            ///  Half-duplex selection
+            HDSEL: u1,
+            ///  Smartcard NACK enable
+            NACK: u1,
+            ///  Smartcard mode enable
+            SCEN: u1,
+            ///  DMA enable receiver
+            DMAR: u1,
+            ///  DMA enable transmitter
+            DMAT: u1,
+            ///  RTS enable
+            RTSE: u1,
+            ///  CTS enable
+            CTSE: u1,
+            ///  CTS interrupt enable
+            CTSIE: u1,
+            ///  One sample bit method enable
+            ONEBIT: u1,
+            ///  Overrun Disable
+            OVRDIS: u1,
+            ///  DMA Disable on Reception Error
+            DDRE: u1,
+            ///  Driver enable mode
+            DEM: u1,
+            ///  Driver enable polarity selection
+            DEP: u1,
+            reserved17: u1,
+            ///  Smartcard auto-retry count
+            SCARCNT: u3,
+            ///  Wakeup from Stop mode interrupt flag selection
+            WUS: u2,
+            ///  Wakeup from Stop mode interrupt enable
+            WUFIE: u1,
+            padding: u9,
+        }),
+        ///  Baud rate register
+        BRR: mmio.Mmio(packed struct(u32) {
+            ///  fraction of USARTDIV
+            DIV_Fraction: u4,
+            ///  mantissa of USARTDIV
+            DIV_Mantissa: u12,
+            padding: u16,
+        }),
+        ///  Guard time and prescaler register
+        GTPR: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u8,
+            ///  Guard time value
+            GT: u8,
+            padding: u16,
+        }),
+        ///  Receiver timeout register
+        RTOR: mmio.Mmio(packed struct(u32) {
+            ///  Receiver timeout value
+            RTO: u24,
+            ///  Block Length
+            BLEN: u8,
+        }),
+        ///  Request register
+        RQR: mmio.Mmio(packed struct(u32) {
+            ///  Auto baud rate request
+            ABRRQ: u1,
+            ///  Send break request
+            SBKRQ: u1,
+            ///  Mute mode request
+            MMRQ: u1,
+            ///  Receive data flush request
+            RXFRQ: u1,
+            ///  Transmit data flush request
+            TXFRQ: u1,
+            padding: u27,
+        }),
+        ///  Interrupt & status register
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  Parity error
+            PE: u1,
+            ///  Framing error
+            FE: u1,
+            ///  Noise detected flag
+            NF: u1,
+            ///  Overrun error
+            ORE: u1,
+            ///  Idle line detected
+            IDLE: u1,
+            ///  Read data register not empty
+            RXNE: u1,
+            ///  Transmission complete
+            TC: u1,
+            ///  Transmit data register empty
+            TXE: u1,
+            ///  LIN break detection flag
+            LBDF: u1,
+            ///  CTS interrupt flag
+            CTSIF: u1,
+            ///  CTS flag
+            CTS: u1,
+            ///  Receiver timeout
+            RTOF: u1,
+            ///  End of block flag
+            EOBF: u1,
+            reserved14: u1,
+            ///  Auto baud rate error
+            ABRE: u1,
+            ///  Auto baud rate flag
+            ABRF: u1,
+            ///  Busy flag
+            BUSY: u1,
+            ///  character match flag
+            CMF: u1,
+            ///  Send break flag
+            SBKF: u1,
+            ///  Receiver wakeup from Mute mode
+            RWU: u1,
+            ///  Wakeup from Stop mode flag
+            WUF: u1,
+            ///  Transmit enable acknowledge flag
+            TEACK: u1,
+            ///  Receive enable acknowledge flag
+            REACK: u1,
+            padding: u9,
+        }),
+        ///  Interrupt flag clear register
+        ICR: mmio.Mmio(packed struct(u32) {
+            ///  Parity error clear flag
+            PECF: u1,
+            ///  Framing error clear flag
+            FECF: u1,
+            ///  Noise detected clear flag
+            NCF: u1,
+            ///  Overrun error clear flag
+            ORECF: u1,
+            ///  Idle line detected clear flag
+            IDLECF: u1,
+            reserved6: u1,
+            ///  Transmission complete clear flag
+            TCCF: u1,
+            reserved8: u1,
+            ///  LIN break detection clear flag
+            LBDCF: u1,
+            ///  CTS clear flag
+            CTSCF: u1,
+            reserved11: u1,
+            ///  Receiver timeout clear flag
+            RTOCF: u1,
+            ///  End of timeout clear flag
+            EOBCF: u1,
+            reserved17: u4,
+            ///  Character match clear flag
+            CMCF: u1,
+            reserved20: u2,
+            ///  Wakeup from Stop mode clear flag
+            WUCF: u1,
+            padding: u11,
+        }),
+        ///  Receive data register
+        RDR: mmio.Mmio(packed struct(u32) {
+            ///  Receive data value
+            RDR: u9,
+            padding: u23,
+        }),
+        ///  Transmit data register
+        TDR: mmio.Mmio(packed struct(u32) {
+            ///  Transmit data value
+            TDR: u9,
+            padding: u23,
+        }),
+    };
+
+    ///  System configuration controller _Comparator and Operational amplifier
+    pub const SYSCFG_COMP_OPAMP = extern struct {
+        ///  configuration register 1
+        SYSCFG_CFGR1: mmio.Mmio(packed struct(u32) {
+            ///  Memory mapping selection bits
+            MEM_MODE: u2,
+            reserved5: u3,
+            ///  USB interrupt remap
+            USB_IT_RMP: u1,
+            ///  Timer 1 ITR3 selection
+            TIM1_ITR_RMP: u1,
+            ///  DAC trigger remap (when TSEL = 001)
+            DAC_TRIG_RMP: u1,
+            ///  ADC24 DMA remapping bit
+            ADC24_DMA_RMP: u1,
+            reserved11: u2,
+            ///  TIM16 DMA request remapping bit
+            TIM16_DMA_RMP: u1,
+            ///  TIM17 DMA request remapping bit
+            TIM17_DMA_RMP: u1,
+            ///  TIM6 and DAC1 DMA request remapping bit
+            TIM6_DAC1_DMA_RMP: u1,
+            ///  TIM7 and DAC2 DMA request remapping bit
+            TIM7_DAC2_DMA_RMP: u1,
+            reserved16: u1,
+            ///  Fast Mode Plus (FM+) driving capability activation bits.
+            I2C_PB6_FM: u1,
+            ///  Fast Mode Plus (FM+) driving capability activation bits.
+            I2C_PB7_FM: u1,
+            ///  Fast Mode Plus (FM+) driving capability activation bits.
+            I2C_PB8_FM: u1,
+            ///  Fast Mode Plus (FM+) driving capability activation bits.
+            I2C_PB9_FM: u1,
+            ///  I2C1 Fast Mode Plus
+            I2C1_FM: u1,
+            ///  I2C2 Fast Mode Plus
+            I2C2_FM: u1,
+            ///  Encoder mode
+            ENCODER_MODE: u2,
+            reserved26: u2,
+            ///  Interrupt enable bits from FPU
+            FPU_IT: u6,
+        }),
+        ///  CCM SRAM protection register
+        SYSCFG_RCR: mmio.Mmio(packed struct(u32) {
+            ///  CCM SRAM page write protection bit
+            PAGE0_WP: u1,
+            ///  CCM SRAM page write protection bit
+            PAGE1_WP: u1,
+            ///  CCM SRAM page write protection bit
+            PAGE2_WP: u1,
+            ///  CCM SRAM page write protection bit
+            PAGE3_WP: u1,
+            ///  CCM SRAM page write protection bit
+            PAGE4_WP: u1,
+            ///  CCM SRAM page write protection bit
+            PAGE5_WP: u1,
+            ///  CCM SRAM page write protection bit
+            PAGE6_WP: u1,
+            ///  CCM SRAM page write protection bit
+            PAGE7_WP: u1,
+            padding: u24,
+        }),
+        ///  external interrupt configuration register 1
+        SYSCFG_EXTICR1: mmio.Mmio(packed struct(u32) {
+            ///  EXTI 0 configuration bits
+            EXTI0: u4,
+            ///  EXTI 1 configuration bits
+            EXTI1: u4,
+            ///  EXTI 2 configuration bits
+            EXTI2: u4,
+            ///  EXTI 3 configuration bits
+            EXTI3: u4,
+            padding: u16,
+        }),
+        ///  external interrupt configuration register 2
+        SYSCFG_EXTICR2: mmio.Mmio(packed struct(u32) {
+            ///  EXTI 4 configuration bits
+            EXTI4: u4,
+            ///  EXTI 5 configuration bits
+            EXTI5: u4,
+            ///  EXTI 6 configuration bits
+            EXTI6: u4,
+            ///  EXTI 7 configuration bits
+            EXTI7: u4,
+            padding: u16,
+        }),
+        ///  external interrupt configuration register 3
+        SYSCFG_EXTICR3: mmio.Mmio(packed struct(u32) {
+            ///  EXTI 8 configuration bits
+            EXTI8: u4,
+            ///  EXTI 9 configuration bits
+            EXTI9: u4,
+            ///  EXTI 10 configuration bits
+            EXTI10: u4,
+            ///  EXTI 11 configuration bits
+            EXTI11: u4,
+            padding: u16,
+        }),
+        ///  external interrupt configuration register 4
+        SYSCFG_EXTICR4: mmio.Mmio(packed struct(u32) {
+            ///  EXTI 12 configuration bits
+            EXTI12: u4,
+            ///  EXTI 13 configuration bits
+            EXTI13: u4,
+            ///  EXTI 14 configuration bits
+            EXTI14: u4,
+            ///  EXTI 15 configuration bits
+            EXTI15: u4,
+            padding: u16,
+        }),
+        ///  configuration register 2
+        SYSCFG_CFGR2: mmio.Mmio(packed struct(u32) {
+            ///  Cortex-M0 LOCKUP bit enable bit
+            LOCUP_LOCK: u1,
+            ///  SRAM parity lock bit
+            SRAM_PARITY_LOCK: u1,
+            ///  PVD lock enable bit
+            PVD_LOCK: u1,
+            reserved4: u1,
+            ///  Bypass address bit 29 in parity calculation
+            BYP_ADD_PAR: u1,
+            reserved8: u3,
+            ///  SRAM parity flag
+            SRAM_PEF: u1,
+            padding: u23,
+        }),
+        ///  control and status register
+        COMP1_CSR: mmio.Mmio(packed struct(u32) {
+            ///  Comparator 1 enable
+            COMP1EN: u1,
+            ///  COMP1_INP_DAC
+            COMP1_INP_DAC: u1,
+            ///  Comparator 1 mode
+            COMP1MODE: u2,
+            ///  Comparator 1 inverting input selection
+            COMP1INSEL: u3,
+            reserved10: u3,
+            ///  Comparator 1 output selection
+            COMP1_OUT_SEL: u4,
+            reserved15: u1,
+            ///  Comparator 1 output polarity
+            COMP1POL: u1,
+            ///  Comparator 1 hysteresis
+            COMP1HYST: u2,
+            ///  Comparator 1 blanking source
+            COMP1_BLANKING: u3,
+            reserved30: u9,
+            ///  Comparator 1 output
+            COMP1OUT: u1,
+            ///  Comparator 1 lock
+            COMP1LOCK: u1,
+        }),
+        ///  control and status register
+        COMP2_CSR: mmio.Mmio(packed struct(u32) {
+            ///  Comparator 2 enable
+            COMP2EN: u1,
+            reserved2: u1,
+            ///  Comparator 2 mode
+            COMP2MODE: u2,
+            ///  Comparator 2 inverting input selection
+            COMP2INSEL: u3,
+            ///  Comparator 2 non inverted input selection
+            COMP2INPSEL: u1,
+            reserved9: u1,
+            ///  Comparator 1inverting input selection
+            COMP2INMSEL: u1,
+            ///  Comparator 2 output selection
+            COMP2_OUT_SEL: u4,
+            reserved15: u1,
+            ///  Comparator 2 output polarity
+            COMP2POL: u1,
+            ///  Comparator 2 hysteresis
+            COMP2HYST: u2,
+            ///  Comparator 2 blanking source
+            COMP2_BLANKING: u3,
+            reserved31: u10,
+            ///  Comparator 2 lock
+            COMP2LOCK: u1,
+        }),
+        ///  control and status register
+        COMP3_CSR: mmio.Mmio(packed struct(u32) {
+            ///  Comparator 3 enable
+            COMP3EN: u1,
+            reserved2: u1,
+            ///  Comparator 3 mode
+            COMP3MODE: u2,
+            ///  Comparator 3 inverting input selection
+            COMP3INSEL: u3,
+            ///  Comparator 3 non inverted input selection
+            COMP3INPSEL: u1,
+            reserved10: u2,
+            ///  Comparator 3 output selection
+            COMP3_OUT_SEL: u4,
+            reserved15: u1,
+            ///  Comparator 3 output polarity
+            COMP3POL: u1,
+            ///  Comparator 3 hysteresis
+            COMP3HYST: u2,
+            ///  Comparator 3 blanking source
+            COMP3_BLANKING: u3,
+            reserved30: u9,
+            ///  Comparator 3 output
+            COMP3OUT: u1,
+            ///  Comparator 3 lock
+            COMP3LOCK: u1,
+        }),
+        ///  control and status register
+        COMP4_CSR: mmio.Mmio(packed struct(u32) {
+            ///  Comparator 4 enable
+            COMP4EN: u1,
+            reserved2: u1,
+            ///  Comparator 4 mode
+            COMP4MODE: u2,
+            ///  Comparator 4 inverting input selection
+            COMP4INSEL: u3,
+            ///  Comparator 4 non inverted input selection
+            COMP4INPSEL: u1,
+            reserved9: u1,
+            ///  Comparator 4 window mode
+            COM4WINMODE: u1,
+            ///  Comparator 4 output selection
+            COMP4_OUT_SEL: u4,
+            reserved15: u1,
+            ///  Comparator 4 output polarity
+            COMP4POL: u1,
+            ///  Comparator 4 hysteresis
+            COMP4HYST: u2,
+            ///  Comparator 4 blanking source
+            COMP4_BLANKING: u3,
+            reserved30: u9,
+            ///  Comparator 4 output
+            COMP4OUT: u1,
+            ///  Comparator 4 lock
+            COMP4LOCK: u1,
+        }),
+        ///  control and status register
+        COMP5_CSR: mmio.Mmio(packed struct(u32) {
+            ///  Comparator 5 enable
+            COMP5EN: u1,
+            reserved2: u1,
+            ///  Comparator 5 mode
+            COMP5MODE: u2,
+            ///  Comparator 5 inverting input selection
+            COMP5INSEL: u3,
+            ///  Comparator 5 non inverted input selection
+            COMP5INPSEL: u1,
+            reserved10: u2,
+            ///  Comparator 5 output selection
+            COMP5_OUT_SEL: u4,
+            reserved15: u1,
+            ///  Comparator 5 output polarity
+            COMP5POL: u1,
+            ///  Comparator 5 hysteresis
+            COMP5HYST: u2,
+            ///  Comparator 5 blanking source
+            COMP5_BLANKING: u3,
+            reserved30: u9,
+            ///  Comparator51 output
+            COMP5OUT: u1,
+            ///  Comparator 5 lock
+            COMP5LOCK: u1,
+        }),
+        ///  control and status register
+        COMP6_CSR: mmio.Mmio(packed struct(u32) {
+            ///  Comparator 6 enable
+            COMP6EN: u1,
+            reserved2: u1,
+            ///  Comparator 6 mode
+            COMP6MODE: u2,
+            ///  Comparator 6 inverting input selection
+            COMP6INSEL: u3,
+            ///  Comparator 6 non inverted input selection
+            COMP6INPSEL: u1,
+            reserved9: u1,
+            ///  Comparator 6 window mode
+            COM6WINMODE: u1,
+            ///  Comparator 6 output selection
+            COMP6_OUT_SEL: u4,
+            reserved15: u1,
+            ///  Comparator 6 output polarity
+            COMP6POL: u1,
+            ///  Comparator 6 hysteresis
+            COMP6HYST: u2,
+            ///  Comparator 6 blanking source
+            COMP6_BLANKING: u3,
+            reserved30: u9,
+            ///  Comparator 6 output
+            COMP6OUT: u1,
+            ///  Comparator 6 lock
+            COMP6LOCK: u1,
+        }),
+        ///  control and status register
+        COMP7_CSR: mmio.Mmio(packed struct(u32) {
+            ///  Comparator 7 enable
+            COMP7EN: u1,
+            reserved2: u1,
+            ///  Comparator 7 mode
+            COMP7MODE: u2,
+            ///  Comparator 7 inverting input selection
+            COMP7INSEL: u3,
+            ///  Comparator 7 non inverted input selection
+            COMP7INPSEL: u1,
+            reserved10: u2,
+            ///  Comparator 7 output selection
+            COMP7_OUT_SEL: u4,
+            reserved15: u1,
+            ///  Comparator 7 output polarity
+            COMP7POL: u1,
+            ///  Comparator 7 hysteresis
+            COMP7HYST: u2,
+            ///  Comparator 7 blanking source
+            COMP7_BLANKING: u3,
+            reserved30: u9,
+            ///  Comparator 7 output
+            COMP7OUT: u1,
+            ///  Comparator 7 lock
+            COMP7LOCK: u1,
+        }),
+        ///  control register
+        OPAMP1_CSR: mmio.Mmio(packed struct(u32) {
+            ///  OPAMP1 enable
+            OPAMP1_EN: u1,
+            ///  FORCE_VP
+            FORCE_VP: u1,
+            ///  OPAMP1 Non inverting input selection
+            VP_SEL: u2,
+            reserved5: u1,
+            ///  OPAMP1 inverting input selection
+            VM_SEL: u2,
+            ///  Timer controlled Mux mode enable
+            TCM_EN: u1,
+            ///  OPAMP1 inverting input secondary selection
+            VMS_SEL: u1,
+            ///  OPAMP1 Non inverting input secondary selection
+            VPS_SEL: u2,
+            ///  Calibration mode enable
+            CALON: u1,
+            ///  Calibration selection
+            CALSEL: u2,
+            ///  Gain in PGA mode
+            PGA_GAIN: u4,
+            ///  User trimming enable
+            USER_TRIM: u1,
+            ///  Offset trimming value (PMOS)
+            TRIMOFFSETP: u5,
+            ///  Offset trimming value (NMOS)
+            TRIMOFFSETN: u5,
+            ///  TSTREF
+            TSTREF: u1,
+            ///  OPAMP 1 ouput status flag
+            OUTCAL: u1,
+            ///  OPAMP 1 lock
+            LOCK: u1,
+        }),
+        ///  control register
+        OPAMP2_CSR: mmio.Mmio(packed struct(u32) {
+            ///  OPAMP2 enable
+            OPAMP2EN: u1,
+            ///  FORCE_VP
+            FORCE_VP: u1,
+            ///  OPAMP2 Non inverting input selection
+            VP_SEL: u2,
+            reserved5: u1,
+            ///  OPAMP2 inverting input selection
+            VM_SEL: u2,
+            ///  Timer controlled Mux mode enable
+            TCM_EN: u1,
+            ///  OPAMP2 inverting input secondary selection
+            VMS_SEL: u1,
+            ///  OPAMP2 Non inverting input secondary selection
+            VPS_SEL: u2,
+            ///  Calibration mode enable
+            CALON: u1,
+            ///  Calibration selection
+            CAL_SEL: u2,
+            ///  Gain in PGA mode
+            PGA_GAIN: u4,
+            ///  User trimming enable
+            USER_TRIM: u1,
+            ///  Offset trimming value (PMOS)
+            TRIMOFFSETP: u5,
+            ///  Offset trimming value (NMOS)
+            TRIMOFFSETN: u5,
+            ///  TSTREF
+            TSTREF: u1,
+            ///  OPAMP 2 ouput status flag
+            OUTCAL: u1,
+            ///  OPAMP 2 lock
+            LOCK: u1,
+        }),
+        ///  control register
+        OPAMP3_CSR: mmio.Mmio(packed struct(u32) {
+            ///  OPAMP3 enable
+            OPAMP3EN: u1,
+            ///  FORCE_VP
+            FORCE_VP: u1,
+            ///  OPAMP3 Non inverting input selection
+            VP_SEL: u2,
+            reserved5: u1,
+            ///  OPAMP3 inverting input selection
+            VM_SEL: u2,
+            ///  Timer controlled Mux mode enable
+            TCM_EN: u1,
+            ///  OPAMP3 inverting input secondary selection
+            VMS_SEL: u1,
+            ///  OPAMP3 Non inverting input secondary selection
+            VPS_SEL: u2,
+            ///  Calibration mode enable
+            CALON: u1,
+            ///  Calibration selection
+            CALSEL: u2,
+            ///  Gain in PGA mode
+            PGA_GAIN: u4,
+            ///  User trimming enable
+            USER_TRIM: u1,
+            ///  Offset trimming value (PMOS)
+            TRIMOFFSETP: u5,
+            ///  Offset trimming value (NMOS)
+            TRIMOFFSETN: u5,
+            ///  TSTREF
+            TSTREF: u1,
+            ///  OPAMP 3 ouput status flag
+            OUTCAL: u1,
+            ///  OPAMP 3 lock
+            LOCK: u1,
+        }),
+        ///  control register
+        OPAMP4_CSR: mmio.Mmio(packed struct(u32) {
+            ///  OPAMP4 enable
+            OPAMP4EN: u1,
+            ///  FORCE_VP
+            FORCE_VP: u1,
+            ///  OPAMP4 Non inverting input selection
+            VP_SEL: u2,
+            reserved5: u1,
+            ///  OPAMP4 inverting input selection
+            VM_SEL: u2,
+            ///  Timer controlled Mux mode enable
+            TCM_EN: u1,
+            ///  OPAMP4 inverting input secondary selection
+            VMS_SEL: u1,
+            ///  OPAMP4 Non inverting input secondary selection
+            VPS_SEL: u2,
+            ///  Calibration mode enable
+            CALON: u1,
+            ///  Calibration selection
+            CALSEL: u2,
+            ///  Gain in PGA mode
+            PGA_GAIN: u4,
+            ///  User trimming enable
+            USER_TRIM: u1,
+            ///  Offset trimming value (PMOS)
+            TRIMOFFSETP: u5,
+            ///  Offset trimming value (NMOS)
+            TRIMOFFSETN: u5,
+            ///  TSTREF
+            TSTREF: u1,
+            ///  OPAMP 4 ouput status flag
+            OUTCAL: u1,
+            ///  OPAMP 4 lock
+            LOCK: u1,
+        }),
+    };
+
+    ///  Independent watchdog
+    pub const IWDG = extern struct {
+        ///  Key register
+        KR: mmio.Mmio(packed struct(u32) {
+            ///  Key value
+            KEY: u16,
+            padding: u16,
+        }),
+        ///  Prescaler register
+        PR: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler divider
+            PR: u3,
+            padding: u29,
+        }),
+        ///  Reload register
+        RLR: mmio.Mmio(packed struct(u32) {
+            ///  Watchdog counter reload value
+            RL: u12,
+            padding: u20,
+        }),
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Watchdog prescaler value update
+            PVU: u1,
+            ///  Watchdog counter reload value update
+            RVU: u1,
+            ///  Watchdog counter window value update
+            WVU: u1,
+            padding: u29,
+        }),
+        ///  Window register
+        WINR: mmio.Mmio(packed struct(u32) {
+            ///  Watchdog counter window value
+            WIN: u12,
+            padding: u20,
+        }),
+    };
+
+    ///  Analog-to-Digital Converter
+    pub const ADC1_2 = extern struct {
+        ///  ADC Common status register
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  ADDRDY_MST
+            ADDRDY_MST: u1,
+            ///  EOSMP_MST
+            EOSMP_MST: u1,
+            ///  EOC_MST
+            EOC_MST: u1,
+            ///  EOS_MST
+            EOS_MST: u1,
+            ///  OVR_MST
+            OVR_MST: u1,
+            ///  JEOC_MST
+            JEOC_MST: u1,
+            ///  JEOS_MST
+            JEOS_MST: u1,
+            ///  AWD1_MST
+            AWD1_MST: u1,
+            ///  AWD2_MST
+            AWD2_MST: u1,
+            ///  AWD3_MST
+            AWD3_MST: u1,
+            ///  JQOVF_MST
+            JQOVF_MST: u1,
+            reserved16: u5,
+            ///  ADRDY_SLV
+            ADRDY_SLV: u1,
+            ///  EOSMP_SLV
+            EOSMP_SLV: u1,
+            ///  End of regular conversion of the slave ADC
+            EOC_SLV: u1,
+            ///  End of regular sequence flag of the slave ADC
+            EOS_SLV: u1,
+            ///  Overrun flag of the slave ADC
+            OVR_SLV: u1,
+            ///  End of injected conversion flag of the slave ADC
+            JEOC_SLV: u1,
+            ///  End of injected sequence flag of the slave ADC
+            JEOS_SLV: u1,
+            ///  Analog watchdog 1 flag of the slave ADC
+            AWD1_SLV: u1,
+            ///  Analog watchdog 2 flag of the slave ADC
+            AWD2_SLV: u1,
+            ///  Analog watchdog 3 flag of the slave ADC
+            AWD3_SLV: u1,
+            ///  Injected Context Queue Overflow flag of the slave ADC
+            JQOVF_SLV: u1,
+            padding: u5,
+        }),
+        reserved8: [4]u8,
+        ///  ADC common control register
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Multi ADC mode selection
+            MULT: u5,
+            reserved8: u3,
+            ///  Delay between 2 sampling phases
+            DELAY: u4,
+            reserved13: u1,
+            ///  DMA configuration (for multi-ADC mode)
+            DMACFG: u1,
+            ///  Direct memory access mode for multi ADC mode
+            MDMA: u2,
+            ///  ADC clock mode
+            CKMODE: u2,
+            reserved22: u4,
+            ///  VREFINT enable
+            VREFEN: u1,
+            ///  Temperature sensor enable
+            TSEN: u1,
+            ///  VBAT enable
+            VBATEN: u1,
+            padding: u7,
+        }),
+        ///  ADC common regular data register for dual and triple modes
+        CDR: mmio.Mmio(packed struct(u32) {
+            ///  Regular data of the master ADC
+            RDATA_MST: u16,
+            ///  Regular data of the slave ADC
+            RDATA_SLV: u16,
+        }),
+    };
+
+    ///  Window watchdog
+    pub const WWDG = extern struct {
+        ///  Control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  7-bit counter
+            T: u7,
+            ///  Activation bit
+            WDGA: u1,
+            padding: u24,
+        }),
+        ///  Configuration register
+        CFR: mmio.Mmio(packed struct(u32) {
+            ///  7-bit window value
+            W: u7,
+            ///  Timer base
+            WDGTB: u2,
+            ///  Early wakeup interrupt
+            EWI: u1,
+            padding: u22,
+        }),
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Early wakeup interrupt flag
+            EWIF: u1,
+            padding: u31,
+        }),
+    };
+
+    ///  Serial peripheral interface/Inter-IC sound
+    pub const SPI1 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Clock phase
+            CPHA: u1,
+            ///  Clock polarity
+            CPOL: u1,
+            ///  Master selection
+            MSTR: u1,
+            ///  Baud rate control
+            BR: u3,
+            ///  SPI enable
+            SPE: u1,
+            ///  Frame format
+            LSBFIRST: u1,
+            ///  Internal slave select
+            SSI: u1,
+            ///  Software slave management
+            SSM: u1,
+            ///  Receive only
+            RXONLY: u1,
+            ///  CRC length
+            CRCL: u1,
+            ///  CRC transfer next
+            CRCNEXT: u1,
+            ///  Hardware CRC calculation enable
+            CRCEN: u1,
+            ///  Output enable in bidirectional mode
+            BIDIOE: u1,
+            ///  Bidirectional data mode enable
+            BIDIMODE: u1,
+            padding: u16,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Rx buffer DMA enable
+            RXDMAEN: u1,
+            ///  Tx buffer DMA enable
+            TXDMAEN: u1,
+            ///  SS output enable
+            SSOE: u1,
+            ///  NSS pulse management
+            NSSP: u1,
+            ///  Frame format
+            FRF: u1,
+            ///  Error interrupt enable
+            ERRIE: u1,
+            ///  RX buffer not empty interrupt enable
+            RXNEIE: u1,
+            ///  Tx buffer empty interrupt enable
+            TXEIE: u1,
+            ///  Data size
+            DS: u4,
+            ///  FIFO reception threshold
+            FRXTH: u1,
+            ///  Last DMA transfer for reception
+            LDMA_RX: u1,
+            ///  Last DMA transfer for transmission
+            LDMA_TX: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Receive buffer not empty
+            RXNE: u1,
+            ///  Transmit buffer empty
+            TXE: u1,
+            ///  Channel side
+            CHSIDE: u1,
+            ///  Underrun flag
+            UDR: u1,
+            ///  CRC error flag
+            CRCERR: u1,
+            ///  Mode fault
+            MODF: u1,
+            ///  Overrun flag
+            OVR: u1,
+            ///  Busy flag
+            BSY: u1,
+            ///  TI frame format error
+            TIFRFE: u1,
+            ///  FIFO reception level
+            FRLVL: u2,
+            ///  FIFO transmission level
+            FTLVL: u2,
+            padding: u19,
+        }),
+        ///  data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data register
+            DR: u16,
+            padding: u16,
+        }),
+        ///  CRC polynomial register
+        CRCPR: mmio.Mmio(packed struct(u32) {
+            ///  CRC polynomial register
+            CRCPOLY: u16,
+            padding: u16,
+        }),
+        ///  RX CRC register
+        RXCRCR: mmio.Mmio(packed struct(u32) {
+            ///  Rx CRC register
+            RxCRC: u16,
+            padding: u16,
+        }),
+        ///  TX CRC register
+        TXCRCR: mmio.Mmio(packed struct(u32) {
+            ///  Tx CRC register
+            TxCRC: u16,
+            padding: u16,
+        }),
+        ///  I2S configuration register
+        I2SCFGR: mmio.Mmio(packed struct(u32) {
+            ///  Channel length (number of bits per audio channel)
+            CHLEN: u1,
+            ///  Data length to be transferred
+            DATLEN: u2,
+            ///  Steady state clock polarity
+            CKPOL: u1,
+            ///  I2S standard selection
+            I2SSTD: u2,
+            reserved7: u1,
+            ///  PCM frame synchronization
+            PCMSYNC: u1,
+            ///  I2S configuration mode
+            I2SCFG: u2,
+            ///  I2S Enable
+            I2SE: u1,
+            ///  I2S mode selection
+            I2SMOD: u1,
+            padding: u20,
+        }),
+        ///  I2S prescaler register
+        I2SPR: mmio.Mmio(packed struct(u32) {
+            ///  I2S Linear prescaler
+            I2SDIV: u8,
+            ///  Odd factor for the prescaler
+            ODD: u1,
+            ///  Master clock output enable
+            MCKOE: u1,
+            padding: u22,
+        }),
+    };
+
+    ///  Real-time clock
+    pub const RTC = extern struct {
+        ///  time register
+        TR: mmio.Mmio(packed struct(u32) {
+            ///  Second units in BCD format
+            SU: u4,
+            ///  Second tens in BCD format
+            ST: u3,
+            reserved8: u1,
+            ///  Minute units in BCD format
+            MNU: u4,
+            ///  Minute tens in BCD format
+            MNT: u3,
+            reserved16: u1,
+            ///  Hour units in BCD format
+            HU: u4,
+            ///  Hour tens in BCD format
+            HT: u2,
+            ///  AM/PM notation
+            PM: u1,
+            padding: u9,
+        }),
+        ///  date register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Date units in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            reserved8: u2,
+            ///  Month units in BCD format
+            MU: u4,
+            ///  Month tens in BCD format
+            MT: u1,
+            ///  Week day units
+            WDU: u3,
+            ///  Year units in BCD format
+            YU: u4,
+            ///  Year tens in BCD format
+            YT: u4,
+            padding: u8,
+        }),
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Wakeup clock selection
+            WCKSEL: u3,
+            ///  Time-stamp event active edge
+            TSEDGE: u1,
+            ///  Reference clock detection enable (50 or 60 Hz)
+            REFCKON: u1,
+            ///  Bypass the shadow registers
+            BYPSHAD: u1,
+            ///  Hour format
+            FMT: u1,
+            reserved8: u1,
+            ///  Alarm A enable
+            ALRAE: u1,
+            ///  Alarm B enable
+            ALRBE: u1,
+            ///  Wakeup timer enable
+            WUTE: u1,
+            ///  Time stamp enable
+            TSE: u1,
+            ///  Alarm A interrupt enable
+            ALRAIE: u1,
+            ///  Alarm B interrupt enable
+            ALRBIE: u1,
+            ///  Wakeup timer interrupt enable
+            WUTIE: u1,
+            ///  Time-stamp interrupt enable
+            TSIE: u1,
+            ///  Add 1 hour (summer time change)
+            ADD1H: u1,
+            ///  Subtract 1 hour (winter time change)
+            SUB1H: u1,
+            ///  Backup
+            BKP: u1,
+            ///  Calibration output selection
+            COSEL: u1,
+            ///  Output polarity
+            POL: u1,
+            ///  Output selection
+            OSEL: u2,
+            ///  Calibration output enable
+            COE: u1,
+            padding: u8,
+        }),
+        ///  initialization and status register
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  Alarm A write flag
+            ALRAWF: u1,
+            ///  Alarm B write flag
+            ALRBWF: u1,
+            ///  Wakeup timer write flag
+            WUTWF: u1,
+            ///  Shift operation pending
+            SHPF: u1,
+            ///  Initialization status flag
+            INITS: u1,
+            ///  Registers synchronization flag
+            RSF: u1,
+            ///  Initialization flag
+            INITF: u1,
+            ///  Initialization mode
+            INIT: u1,
+            ///  Alarm A flag
+            ALRAF: u1,
+            ///  Alarm B flag
+            ALRBF: u1,
+            ///  Wakeup timer flag
+            WUTF: u1,
+            ///  Time-stamp flag
+            TSF: u1,
+            ///  Time-stamp overflow flag
+            TSOVF: u1,
+            ///  Tamper detection flag
+            TAMP1F: u1,
+            ///  RTC_TAMP2 detection flag
+            TAMP2F: u1,
+            ///  RTC_TAMP3 detection flag
+            TAMP3F: u1,
+            ///  Recalibration pending Flag
+            RECALPF: u1,
+            padding: u15,
+        }),
+        ///  prescaler register
+        PRER: mmio.Mmio(packed struct(u32) {
+            ///  Synchronous prescaler factor
+            PREDIV_S: u15,
+            reserved16: u1,
+            ///  Asynchronous prescaler factor
+            PREDIV_A: u7,
+            padding: u9,
+        }),
+        ///  wakeup timer register
+        WUTR: mmio.Mmio(packed struct(u32) {
+            ///  Wakeup auto-reload value bits
+            WUT: u16,
+            padding: u16,
+        }),
+        reserved28: [4]u8,
+        ///  alarm A register
+        ALRMAR: mmio.Mmio(packed struct(u32) {
+            ///  Second units in BCD format
+            SU: u4,
+            ///  Second tens in BCD format
+            ST: u3,
+            ///  Alarm A seconds mask
+            MSK1: u1,
+            ///  Minute units in BCD format
+            MNU: u4,
+            ///  Minute tens in BCD format
+            MNT: u3,
+            ///  Alarm A minutes mask
+            MSK2: u1,
+            ///  Hour units in BCD format
+            HU: u4,
+            ///  Hour tens in BCD format
+            HT: u2,
+            ///  AM/PM notation
+            PM: u1,
+            ///  Alarm A hours mask
+            MSK3: u1,
+            ///  Date units or day in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            ///  Week day selection
+            WDSEL: u1,
+            ///  Alarm A date mask
+            MSK4: u1,
+        }),
+        ///  alarm B register
+        ALRMBR: mmio.Mmio(packed struct(u32) {
+            ///  Second units in BCD format
+            SU: u4,
+            ///  Second tens in BCD format
+            ST: u3,
+            ///  Alarm B seconds mask
+            MSK1: u1,
+            ///  Minute units in BCD format
+            MNU: u4,
+            ///  Minute tens in BCD format
+            MNT: u3,
+            ///  Alarm B minutes mask
+            MSK2: u1,
+            ///  Hour units in BCD format
+            HU: u4,
+            ///  Hour tens in BCD format
+            HT: u2,
+            ///  AM/PM notation
+            PM: u1,
+            ///  Alarm B hours mask
+            MSK3: u1,
+            ///  Date units or day in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            ///  Week day selection
+            WDSEL: u1,
+            ///  Alarm B date mask
+            MSK4: u1,
+        }),
+        ///  write protection register
+        WPR: mmio.Mmio(packed struct(u32) {
+            ///  Write protection key
+            KEY: u8,
+            padding: u24,
+        }),
+        ///  sub second register
+        SSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub second value
+            SS: u16,
+            padding: u16,
+        }),
+        ///  shift control register
+        SHIFTR: mmio.Mmio(packed struct(u32) {
+            ///  Subtract a fraction of a second
+            SUBFS: u15,
+            reserved31: u16,
+            ///  Add one second
+            ADD1S: u1,
+        }),
+        ///  time stamp time register
+        TSTR: mmio.Mmio(packed struct(u32) {
+            ///  Second units in BCD format
+            SU: u4,
+            ///  Second tens in BCD format
+            ST: u3,
+            reserved8: u1,
+            ///  Minute units in BCD format
+            MNU: u4,
+            ///  Minute tens in BCD format
+            MNT: u3,
+            reserved16: u1,
+            ///  Hour units in BCD format
+            HU: u4,
+            ///  Hour tens in BCD format
+            HT: u2,
+            ///  AM/PM notation
+            PM: u1,
+            padding: u9,
+        }),
+        ///  time stamp date register
+        TSDR: mmio.Mmio(packed struct(u32) {
+            ///  Date units in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            reserved8: u2,
+            ///  Month units in BCD format
+            MU: u4,
+            ///  Month tens in BCD format
+            MT: u1,
+            ///  Week day units
+            WDU: u3,
+            padding: u16,
+        }),
+        ///  timestamp sub second register
+        TSSSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub second value
+            SS: u16,
+            padding: u16,
+        }),
+        ///  calibration register
+        CALR: mmio.Mmio(packed struct(u32) {
+            ///  Calibration minus
+            CALM: u9,
+            reserved13: u4,
+            ///  Use a 16-second calibration cycle period
+            CALW16: u1,
+            ///  Use an 8-second calibration cycle period
+            CALW8: u1,
+            ///  Increase frequency of RTC by 488.5 ppm
+            CALP: u1,
+            padding: u16,
+        }),
+        ///  tamper and alternate function configuration register
+        TAFCR: mmio.Mmio(packed struct(u32) {
+            ///  Tamper 1 detection enable
+            TAMP1E: u1,
+            ///  Active level for tamper 1
+            TAMP1TRG: u1,
+            ///  Tamper interrupt enable
+            TAMPIE: u1,
+            ///  Tamper 2 detection enable
+            TAMP2E: u1,
+            ///  Active level for tamper 2
+            TAMP2TRG: u1,
+            ///  Tamper 3 detection enable
+            TAMP3E: u1,
+            ///  Active level for tamper 3
+            TAMP3TRG: u1,
+            ///  Activate timestamp on tamper detection event
+            TAMPTS: u1,
+            ///  Tamper sampling frequency
+            TAMPFREQ: u3,
+            ///  Tamper filter count
+            TAMPFLT: u2,
+            ///  Tamper precharge duration
+            TAMPPRCH: u2,
+            ///  TAMPER pull-up disable
+            TAMPPUDIS: u1,
+            reserved18: u2,
+            ///  PC13 value
+            PC13VALUE: u1,
+            ///  PC13 mode
+            PC13MODE: u1,
+            ///  PC14 value
+            PC14VALUE: u1,
+            ///  PC 14 mode
+            PC14MODE: u1,
+            ///  PC15 value
+            PC15VALUE: u1,
+            ///  PC15 mode
+            PC15MODE: u1,
+            padding: u8,
+        }),
+        ///  alarm A sub second register
+        ALRMASSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub seconds value
+            SS: u15,
+            reserved24: u9,
+            ///  Mask the most-significant bits starting at this bit
+            MASKSS: u4,
+            padding: u4,
+        }),
+        ///  alarm B sub second register
+        ALRMBSSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub seconds value
+            SS: u15,
+            reserved24: u9,
+            ///  Mask the most-significant bits starting at this bit
+            MASKSS: u4,
+            padding: u4,
+        }),
+        reserved80: [4]u8,
+        ///  backup register
+        BKP0R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP1R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP2R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP3R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP4R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP5R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP6R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP7R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP8R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP9R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP10R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP11R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP12R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP13R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP14R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP15R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP16R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP17R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP18R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP19R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP20R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP21R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP22R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP23R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP24R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP25R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP26R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP27R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP28R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP29R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP30R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP31R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+    };
+
+    ///  Basic timers
+    pub const TIM6 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            reserved7: u3,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            reserved11: u3,
+            ///  UIF status bit remapping
+            UIFREMAP: u1,
+            padding: u20,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  Master mode selection
+            MMS: u3,
+            padding: u25,
+        }),
+        reserved12: [4]u8,
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            reserved8: u7,
+            ///  Update DMA request enable
+            UDE: u1,
+            padding: u23,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            padding: u31,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            padding: u31,
+        }),
+        reserved36: [12]u8,
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  Low counter value
+            CNT: u16,
+            reserved31: u15,
+            ///  UIF Copy
+            UIFCPY: u1,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Low Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Analog-to-Digital Converter
+    pub const ADC1 = extern struct {
+        ///  interrupt and status register
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  ADRDY
+            ADRDY: u1,
+            ///  EOSMP
+            EOSMP: u1,
+            ///  EOC
+            EOC: u1,
+            ///  EOS
+            EOS: u1,
+            ///  OVR
+            OVR: u1,
+            ///  JEOC
+            JEOC: u1,
+            ///  JEOS
+            JEOS: u1,
+            ///  AWD1
+            AWD1: u1,
+            ///  AWD2
+            AWD2: u1,
+            ///  AWD3
+            AWD3: u1,
+            ///  JQOVF
+            JQOVF: u1,
+            padding: u21,
+        }),
+        ///  interrupt enable register
+        IER: mmio.Mmio(packed struct(u32) {
+            ///  ADRDYIE
+            ADRDYIE: u1,
+            ///  EOSMPIE
+            EOSMPIE: u1,
+            ///  EOCIE
+            EOCIE: u1,
+            ///  EOSIE
+            EOSIE: u1,
+            ///  OVRIE
+            OVRIE: u1,
+            ///  JEOCIE
+            JEOCIE: u1,
+            ///  JEOSIE
+            JEOSIE: u1,
+            ///  AWD1IE
+            AWD1IE: u1,
+            ///  AWD2IE
+            AWD2IE: u1,
+            ///  AWD3IE
+            AWD3IE: u1,
+            ///  JQOVFIE
+            JQOVFIE: u1,
+            padding: u21,
+        }),
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  ADEN
+            ADEN: u1,
+            ///  ADDIS
+            ADDIS: u1,
+            ///  ADSTART
+            ADSTART: u1,
+            ///  JADSTART
+            JADSTART: u1,
+            ///  ADSTP
+            ADSTP: u1,
+            ///  JADSTP
+            JADSTP: u1,
+            reserved28: u22,
+            ///  ADVREGEN
+            ADVREGEN: u1,
+            ///  DEEPPWD
+            DEEPPWD: u1,
+            ///  ADCALDIF
+            ADCALDIF: u1,
+            ///  ADCAL
+            ADCAL: u1,
+        }),
+        ///  configuration register
+        CFGR: mmio.Mmio(packed struct(u32) {
+            ///  DMAEN
+            DMAEN: u1,
+            ///  DMACFG
+            DMACFG: u1,
+            reserved3: u1,
+            ///  RES
+            RES: u2,
+            ///  ALIGN
+            ALIGN: u1,
+            ///  EXTSEL
+            EXTSEL: u4,
+            ///  EXTEN
+            EXTEN: u2,
+            ///  OVRMOD
+            OVRMOD: u1,
+            ///  CONT
+            CONT: u1,
+            ///  AUTDLY
+            AUTDLY: u1,
+            ///  AUTOFF
+            AUTOFF: u1,
+            ///  DISCEN
+            DISCEN: u1,
+            ///  DISCNUM
+            DISCNUM: u3,
+            ///  JDISCEN
+            JDISCEN: u1,
+            ///  JQM
+            JQM: u1,
+            ///  AWD1SGL
+            AWD1SGL: u1,
+            ///  AWD1EN
+            AWD1EN: u1,
+            ///  JAWD1EN
+            JAWD1EN: u1,
+            ///  JAUTO
+            JAUTO: u1,
+            ///  AWDCH1CH
+            AWDCH1CH: u5,
+            padding: u1,
+        }),
+        reserved20: [4]u8,
+        ///  sample time register 1
+        SMPR1: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  SMP1
+            SMP1: u3,
+            ///  SMP2
+            SMP2: u3,
+            ///  SMP3
+            SMP3: u3,
+            ///  SMP4
+            SMP4: u3,
+            ///  SMP5
+            SMP5: u3,
+            ///  SMP6
+            SMP6: u3,
+            ///  SMP7
+            SMP7: u3,
+            ///  SMP8
+            SMP8: u3,
+            ///  SMP9
+            SMP9: u3,
+            padding: u2,
+        }),
+        ///  sample time register 2
+        SMPR2: mmio.Mmio(packed struct(u32) {
+            ///  SMP10
+            SMP10: u3,
+            ///  SMP11
+            SMP11: u3,
+            ///  SMP12
+            SMP12: u3,
+            ///  SMP13
+            SMP13: u3,
+            ///  SMP14
+            SMP14: u3,
+            ///  SMP15
+            SMP15: u3,
+            ///  SMP16
+            SMP16: u3,
+            ///  SMP17
+            SMP17: u3,
+            ///  SMP18
+            SMP18: u3,
+            padding: u5,
+        }),
+        reserved32: [4]u8,
+        ///  watchdog threshold register 1
+        TR1: mmio.Mmio(packed struct(u32) {
+            ///  LT1
+            LT1: u12,
+            reserved16: u4,
+            ///  HT1
+            HT1: u12,
+            padding: u4,
+        }),
+        ///  watchdog threshold register
+        TR2: mmio.Mmio(packed struct(u32) {
+            ///  LT2
+            LT2: u8,
+            reserved16: u8,
+            ///  HT2
+            HT2: u8,
+            padding: u8,
+        }),
+        ///  watchdog threshold register 3
+        TR3: mmio.Mmio(packed struct(u32) {
+            ///  LT3
+            LT3: u8,
+            reserved16: u8,
+            ///  HT3
+            HT3: u8,
+            padding: u8,
+        }),
+        reserved48: [4]u8,
+        ///  regular sequence register 1
+        SQR1: mmio.Mmio(packed struct(u32) {
+            ///  L3
+            L3: u4,
+            reserved6: u2,
+            ///  SQ1
+            SQ1: u5,
+            reserved12: u1,
+            ///  SQ2
+            SQ2: u5,
+            reserved18: u1,
+            ///  SQ3
+            SQ3: u5,
+            reserved24: u1,
+            ///  SQ4
+            SQ4: u5,
+            padding: u3,
+        }),
+        ///  regular sequence register 2
+        SQR2: mmio.Mmio(packed struct(u32) {
+            ///  SQ5
+            SQ5: u5,
+            reserved6: u1,
+            ///  SQ6
+            SQ6: u5,
+            reserved12: u1,
+            ///  SQ7
+            SQ7: u5,
+            reserved18: u1,
+            ///  SQ8
+            SQ8: u5,
+            reserved24: u1,
+            ///  SQ9
+            SQ9: u5,
+            padding: u3,
+        }),
+        ///  regular sequence register 3
+        SQR3: mmio.Mmio(packed struct(u32) {
+            ///  SQ10
+            SQ10: u5,
+            reserved6: u1,
+            ///  SQ11
+            SQ11: u5,
+            reserved12: u1,
+            ///  SQ12
+            SQ12: u5,
+            reserved18: u1,
+            ///  SQ13
+            SQ13: u5,
+            reserved24: u1,
+            ///  SQ14
+            SQ14: u5,
+            padding: u3,
+        }),
+        ///  regular sequence register 4
+        SQR4: mmio.Mmio(packed struct(u32) {
+            ///  SQ15
+            SQ15: u5,
+            reserved6: u1,
+            ///  SQ16
+            SQ16: u5,
+            padding: u21,
+        }),
+        ///  regular Data Register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  regularDATA
+            regularDATA: u16,
+            padding: u16,
+        }),
+        reserved76: [8]u8,
+        ///  injected sequence register
+        JSQR: mmio.Mmio(packed struct(u32) {
+            ///  JL
+            JL: u2,
+            ///  JEXTSEL
+            JEXTSEL: u4,
+            ///  JEXTEN
+            JEXTEN: u2,
+            ///  JSQ1
+            JSQ1: u5,
+            reserved14: u1,
+            ///  JSQ2
+            JSQ2: u5,
+            reserved20: u1,
+            ///  JSQ3
+            JSQ3: u5,
+            reserved26: u1,
+            ///  JSQ4
+            JSQ4: u5,
+            padding: u1,
+        }),
+        reserved96: [16]u8,
+        ///  offset register 1
+        OFR1: mmio.Mmio(packed struct(u32) {
+            ///  OFFSET1
+            OFFSET1: u12,
+            reserved26: u14,
+            ///  OFFSET1_CH
+            OFFSET1_CH: u5,
+            ///  OFFSET1_EN
+            OFFSET1_EN: u1,
+        }),
+        ///  offset register 2
+        OFR2: mmio.Mmio(packed struct(u32) {
+            ///  OFFSET2
+            OFFSET2: u12,
+            reserved26: u14,
+            ///  OFFSET2_CH
+            OFFSET2_CH: u5,
+            ///  OFFSET2_EN
+            OFFSET2_EN: u1,
+        }),
+        ///  offset register 3
+        OFR3: mmio.Mmio(packed struct(u32) {
+            ///  OFFSET3
+            OFFSET3: u12,
+            reserved26: u14,
+            ///  OFFSET3_CH
+            OFFSET3_CH: u5,
+            ///  OFFSET3_EN
+            OFFSET3_EN: u1,
+        }),
+        ///  offset register 4
+        OFR4: mmio.Mmio(packed struct(u32) {
+            ///  OFFSET4
+            OFFSET4: u12,
+            reserved26: u14,
+            ///  OFFSET4_CH
+            OFFSET4_CH: u5,
+            ///  OFFSET4_EN
+            OFFSET4_EN: u1,
+        }),
+        reserved128: [16]u8,
+        ///  injected data register 1
+        JDR1: mmio.Mmio(packed struct(u32) {
+            ///  JDATA1
+            JDATA1: u16,
+            padding: u16,
+        }),
+        ///  injected data register 2
+        JDR2: mmio.Mmio(packed struct(u32) {
+            ///  JDATA2
+            JDATA2: u16,
+            padding: u16,
+        }),
+        ///  injected data register 3
+        JDR3: mmio.Mmio(packed struct(u32) {
+            ///  JDATA3
+            JDATA3: u16,
+            padding: u16,
+        }),
+        ///  injected data register 4
+        JDR4: mmio.Mmio(packed struct(u32) {
+            ///  JDATA4
+            JDATA4: u16,
+            padding: u16,
+        }),
+        reserved160: [16]u8,
+        ///  Analog Watchdog 2 Configuration Register
+        AWD2CR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  AWD2CH
+            AWD2CH: u18,
+            padding: u13,
+        }),
+        ///  Analog Watchdog 3 Configuration Register
+        AWD3CR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  AWD3CH
+            AWD3CH: u18,
+            padding: u13,
+        }),
+        reserved176: [8]u8,
+        ///  Differential Mode Selection Register 2
+        DIFSEL: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Differential mode for channels 15 to 1
+            DIFSEL_1_15: u15,
+            ///  Differential mode for channels 18 to 16
+            DIFSEL_16_18: u3,
+            padding: u13,
+        }),
+        ///  Calibration Factors
+        CALFACT: mmio.Mmio(packed struct(u32) {
+            ///  CALFACT_S
+            CALFACT_S: u7,
+            reserved16: u9,
+            ///  CALFACT_D
+            CALFACT_D: u7,
+            padding: u9,
+        }),
+    };
+
+    ///  Advanced-timers
+    pub const TIM8 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            reserved11: u1,
+            ///  UIF status bit remapping
+            UIFREMAP: u1,
+            padding: u20,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/compare preloaded control
+            CCPC: u1,
+            reserved2: u1,
+            ///  Capture/compare control update selection
+            CCUS: u1,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            ///  Output Idle state 1
+            OIS1: u1,
+            ///  Output Idle state 1
+            OIS1N: u1,
+            ///  Output Idle state 2
+            OIS2: u1,
+            ///  Output Idle state 2
+            OIS2N: u1,
+            ///  Output Idle state 3
+            OIS3: u1,
+            ///  Output Idle state 3
+            OIS3N: u1,
+            ///  Output Idle state 4
+            OIS4: u1,
+            reserved16: u1,
+            ///  Output Idle state 5
+            OIS5: u1,
+            reserved18: u1,
+            ///  Output Idle state 6
+            OIS6: u1,
+            reserved20: u1,
+            ///  Master mode selection 2
+            MMS2: u4,
+            padding: u8,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            ///  OCREF clear selection
+            OCCS: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            ///  Slave mode selection bit 3
+            SMS3: u1,
+            padding: u15,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            ///  COM interrupt enable
+            COMIE: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            ///  Break interrupt enable
+            BIE: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            ///  COM DMA request enable
+            COMDE: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            ///  COM interrupt flag
+            COMIF: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            ///  Break interrupt flag
+            BIF: u1,
+            ///  Break 2 interrupt flag
+            B2IF: u1,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            reserved16: u3,
+            ///  Capture/Compare 5 interrupt flag
+            C5IF: u1,
+            ///  Capture/Compare 6 interrupt flag
+            C6IF: u1,
+            padding: u14,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            ///  Capture/Compare control update generation
+            COMG: u1,
+            ///  Trigger generation
+            TG: u1,
+            ///  Break generation
+            BG: u1,
+            ///  Break 2 generation
+            B2G: u1,
+            padding: u23,
+        }),
+        ///  capture/compare mode register (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            ///  Output Compare 1 clear enable
+            OC1CE: u1,
+            ///  Capture/Compare 2 selection
+            CC2S: u2,
+            ///  Output Compare 2 fast enable
+            OC2FE: u1,
+            ///  Output Compare 2 preload enable
+            OC2PE: u1,
+            ///  Output Compare 2 mode
+            OC2M: u3,
+            ///  Output Compare 2 clear enable
+            OC2CE: u1,
+            ///  Output Compare 1 mode bit 3
+            OC1M_3: u1,
+            reserved24: u7,
+            ///  Output Compare 2 mode bit 3
+            OC2M_3: u1,
+            padding: u7,
+        }),
+        ///  capture/compare mode register (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 3 selection
+            CC3S: u2,
+            ///  Output compare 3 fast enable
+            OC3FE: u1,
+            ///  Output compare 3 preload enable
+            OC3PE: u1,
+            ///  Output compare 3 mode
+            OC3M: u3,
+            ///  Output compare 3 clear enable
+            OC3CE: u1,
+            ///  Capture/Compare 4 selection
+            CC4S: u2,
+            ///  Output compare 4 fast enable
+            OC4FE: u1,
+            ///  Output compare 4 preload enable
+            OC4PE: u1,
+            ///  Output compare 4 mode
+            OC4M: u3,
+            ///  Output compare 4 clear enable
+            OC4CE: u1,
+            ///  Output Compare 3 mode bit 3
+            OC3M_3: u1,
+            reserved24: u7,
+            ///  Output Compare 4 mode bit 3
+            OC4M_3: u1,
+            padding: u7,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            ///  Capture/Compare 1 complementary output enable
+            CC1NE: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            ///  Capture/Compare 2 complementary output enable
+            CC2NE: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            ///  Capture/Compare 3 complementary output enable
+            CC3NE: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            reserved15: u1,
+            ///  Capture/Compare 4 output Polarity
+            CC4NP: u1,
+            ///  Capture/Compare 5 output enable
+            CC5E: u1,
+            ///  Capture/Compare 5 output Polarity
+            CC5P: u1,
+            reserved20: u2,
+            ///  Capture/Compare 6 output enable
+            CC6E: u1,
+            ///  Capture/Compare 6 output Polarity
+            CC6P: u1,
+            padding: u10,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            reserved31: u15,
+            ///  UIF copy
+            UIFCPY: u1,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        ///  repetition counter register
+        RCR: mmio.Mmio(packed struct(u32) {
+            ///  Repetition counter value
+            REP: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 2 value
+            CCR2: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 3 value
+            CCR3: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 3 value
+            CCR4: u16,
+            padding: u16,
+        }),
+        ///  break and dead-time register
+        BDTR: mmio.Mmio(packed struct(u32) {
+            ///  Dead-time generator setup
+            DTG: u8,
+            ///  Lock configuration
+            LOCK: u2,
+            ///  Off-state selection for Idle mode
+            OSSI: u1,
+            ///  Off-state selection for Run mode
+            OSSR: u1,
+            ///  Break enable
+            BKE: u1,
+            ///  Break polarity
+            BKP: u1,
+            ///  Automatic output enable
+            AOE: u1,
+            ///  Main output enable
+            MOE: u1,
+            ///  Break filter
+            BKF: u4,
+            ///  Break 2 filter
+            BK2F: u4,
+            ///  Break 2 enable
+            BK2E: u1,
+            ///  Break 2 polarity
+            BK2P: u1,
+            padding: u6,
+        }),
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+        reserved84: [4]u8,
+        ///  capture/compare mode register 3 (output mode)
+        CCMR3_Output: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Output compare 5 fast enable
+            OC5FE: u1,
+            ///  Output compare 5 preload enable
+            OC5PE: u1,
+            ///  Output compare 5 mode
+            OC5M: u3,
+            ///  Output compare 5 clear enable
+            OC5CE: u1,
+            reserved10: u2,
+            ///  Output compare 6 fast enable
+            OC6FE: u1,
+            ///  Output compare 6 preload enable
+            OC6PE: u1,
+            ///  Output compare 6 mode
+            OC6M: u3,
+            ///  Output compare 6 clear enable
+            OC6CE: u1,
+            ///  Outout Compare 5 mode bit 3
+            OC5M_3: u1,
+            reserved24: u7,
+            ///  Outout Compare 6 mode bit 3
+            OC6M_3: u1,
+            padding: u7,
+        }),
+        ///  capture/compare register 5
+        CCR5: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 5 value
+            CCR5: u16,
+            reserved29: u13,
+            ///  Group Channel 5 and Channel 1
+            GC5C1: u1,
+            ///  Group Channel 5 and Channel 2
+            GC5C2: u1,
+            ///  Group Channel 5 and Channel 3
+            GC5C3: u1,
+        }),
+        ///  capture/compare register 6
+        CCR6: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 6 value
+            CCR6: u16,
+            padding: u16,
+        }),
+        ///  option registers
+        OR: mmio.Mmio(packed struct(u32) {
+            ///  TIM8_ETR_ADC2 remapping capability
+            TIM8_ETR_ADC2_RMP: u2,
+            ///  TIM8_ETR_ADC3 remapping capability
+            TIM8_ETR_ADC3_RMP: u2,
+            padding: u28,
+        }),
+    };
+
+    ///  Digital-to-analog converter
+    pub const DAC = extern struct {
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 enable
+            EN1: u1,
+            ///  DAC channel1 output buffer disable
+            BOFF1: u1,
+            ///  DAC channel1 trigger enable
+            TEN1: u1,
+            ///  DAC channel1 trigger selection
+            TSEL1: u3,
+            ///  DAC channel1 noise/triangle wave generation enable
+            WAVE1: u2,
+            ///  DAC channel1 mask/amplitude selector
+            MAMP1: u4,
+            ///  DAC channel1 DMA enable
+            DMAEN1: u1,
+            ///  DAC channel1 DMA Underrun Interrupt enable
+            DMAUDRIE1: u1,
+            reserved16: u2,
+            ///  DAC channel2 enable
+            EN2: u1,
+            ///  DAC channel2 output buffer disable
+            BOFF2: u1,
+            ///  DAC channel2 trigger enable
+            TEN2: u1,
+            ///  DAC channel2 trigger selection
+            TSEL2: u3,
+            ///  DAC channel2 noise/triangle wave generation enable
+            WAVE2: u2,
+            ///  DAC channel2 mask/amplitude selector
+            MAMP2: u4,
+            ///  DAC channel2 DMA enable
+            DMAEN2: u1,
+            ///  DAC channel2 DMA underrun interrupt enable
+            DMAUDRIE2: u1,
+            padding: u2,
+        }),
+        ///  software trigger register
+        SWTRIGR: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 software trigger
+            SWTRIG1: u1,
+            ///  DAC channel2 software trigger
+            SWTRIG2: u1,
+            padding: u30,
+        }),
+        ///  channel1 12-bit right-aligned data holding register
+        DHR12R1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 12-bit right-aligned data
+            DACC1DHR: u12,
+            padding: u20,
+        }),
+        ///  channel1 12-bit left aligned data holding register
+        DHR12L1: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel1 12-bit left-aligned data
+            DACC1DHR: u12,
+            padding: u16,
+        }),
+        ///  channel1 8-bit right aligned data holding register
+        DHR8R1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 8-bit right-aligned data
+            DACC1DHR: u8,
+            padding: u24,
+        }),
+        ///  channel2 12-bit right aligned data holding register
+        DHR12R2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 12-bit right-aligned data
+            DACC2DHR: u12,
+            padding: u20,
+        }),
+        ///  channel2 12-bit left aligned data holding register
+        DHR12L2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel2 12-bit left-aligned data
+            DACC2DHR: u12,
+            padding: u16,
+        }),
+        ///  channel2 8-bit right-aligned data holding register
+        DHR8R2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 8-bit right-aligned data
+            DACC2DHR: u8,
+            padding: u24,
+        }),
+        ///  Dual DAC 12-bit right-aligned data holding register
+        DHR12RD: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 12-bit right-aligned data
+            DACC1DHR: u12,
+            reserved16: u4,
+            ///  DAC channel2 12-bit right-aligned data
+            DACC2DHR: u12,
+            padding: u4,
+        }),
+        ///  DUAL DAC 12-bit left aligned data holding register
+        DHR12LD: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel1 12-bit left-aligned data
+            DACC1DHR: u12,
+            reserved20: u4,
+            ///  DAC channel2 12-bit left-aligned data
+            DACC2DHR: u12,
+        }),
+        ///  DUAL DAC 8-bit right aligned data holding register
+        DHR8RD: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 8-bit right-aligned data
+            DACC1DHR: u8,
+            ///  DAC channel2 8-bit right-aligned data
+            DACC2DHR: u8,
+            padding: u16,
+        }),
+        ///  channel1 data output register
+        DOR1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 data output
+            DACC1DOR: u12,
+            padding: u20,
+        }),
+        ///  channel2 data output register
+        DOR2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 data output
+            DACC2DOR: u12,
+            padding: u20,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            reserved13: u13,
+            ///  DAC channel1 DMA underrun flag
+            DMAUDR1: u1,
+            reserved29: u15,
+            ///  DAC channel2 DMA underrun flag
+            DMAUDR2: u1,
+            padding: u2,
+        }),
+    };
+
+    ///  External interrupt/event controller
+    pub const EXTI = extern struct {
+        ///  Interrupt mask register
+        IMR1: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt Mask on line 0
+            MR0: u1,
+            ///  Interrupt Mask on line 1
+            MR1: u1,
+            ///  Interrupt Mask on line 2
+            MR2: u1,
+            ///  Interrupt Mask on line 3
+            MR3: u1,
+            ///  Interrupt Mask on line 4
+            MR4: u1,
+            ///  Interrupt Mask on line 5
+            MR5: u1,
+            ///  Interrupt Mask on line 6
+            MR6: u1,
+            ///  Interrupt Mask on line 7
+            MR7: u1,
+            ///  Interrupt Mask on line 8
+            MR8: u1,
+            ///  Interrupt Mask on line 9
+            MR9: u1,
+            ///  Interrupt Mask on line 10
+            MR10: u1,
+            ///  Interrupt Mask on line 11
+            MR11: u1,
+            ///  Interrupt Mask on line 12
+            MR12: u1,
+            ///  Interrupt Mask on line 13
+            MR13: u1,
+            ///  Interrupt Mask on line 14
+            MR14: u1,
+            ///  Interrupt Mask on line 15
+            MR15: u1,
+            ///  Interrupt Mask on line 16
+            MR16: u1,
+            ///  Interrupt Mask on line 17
+            MR17: u1,
+            ///  Interrupt Mask on line 18
+            MR18: u1,
+            ///  Interrupt Mask on line 19
+            MR19: u1,
+            ///  Interrupt Mask on line 20
+            MR20: u1,
+            ///  Interrupt Mask on line 21
+            MR21: u1,
+            ///  Interrupt Mask on line 22
+            MR22: u1,
+            ///  Interrupt Mask on line 23
+            MR23: u1,
+            ///  Interrupt Mask on line 24
+            MR24: u1,
+            ///  Interrupt Mask on line 25
+            MR25: u1,
+            ///  Interrupt Mask on line 26
+            MR26: u1,
+            ///  Interrupt Mask on line 27
+            MR27: u1,
+            ///  Interrupt Mask on line 28
+            MR28: u1,
+            ///  Interrupt Mask on line 29
+            MR29: u1,
+            ///  Interrupt Mask on line 30
+            MR30: u1,
+            ///  Interrupt Mask on line 31
+            MR31: u1,
+        }),
+        ///  Event mask register
+        EMR1: mmio.Mmio(packed struct(u32) {
+            ///  Event Mask on line 0
+            MR0: u1,
+            ///  Event Mask on line 1
+            MR1: u1,
+            ///  Event Mask on line 2
+            MR2: u1,
+            ///  Event Mask on line 3
+            MR3: u1,
+            ///  Event Mask on line 4
+            MR4: u1,
+            ///  Event Mask on line 5
+            MR5: u1,
+            ///  Event Mask on line 6
+            MR6: u1,
+            ///  Event Mask on line 7
+            MR7: u1,
+            ///  Event Mask on line 8
+            MR8: u1,
+            ///  Event Mask on line 9
+            MR9: u1,
+            ///  Event Mask on line 10
+            MR10: u1,
+            ///  Event Mask on line 11
+            MR11: u1,
+            ///  Event Mask on line 12
+            MR12: u1,
+            ///  Event Mask on line 13
+            MR13: u1,
+            ///  Event Mask on line 14
+            MR14: u1,
+            ///  Event Mask on line 15
+            MR15: u1,
+            ///  Event Mask on line 16
+            MR16: u1,
+            ///  Event Mask on line 17
+            MR17: u1,
+            ///  Event Mask on line 18
+            MR18: u1,
+            ///  Event Mask on line 19
+            MR19: u1,
+            ///  Event Mask on line 20
+            MR20: u1,
+            ///  Event Mask on line 21
+            MR21: u1,
+            ///  Event Mask on line 22
+            MR22: u1,
+            ///  Event Mask on line 23
+            MR23: u1,
+            ///  Event Mask on line 24
+            MR24: u1,
+            ///  Event Mask on line 25
+            MR25: u1,
+            ///  Event Mask on line 26
+            MR26: u1,
+            ///  Event Mask on line 27
+            MR27: u1,
+            ///  Event Mask on line 28
+            MR28: u1,
+            ///  Event Mask on line 29
+            MR29: u1,
+            ///  Event Mask on line 30
+            MR30: u1,
+            ///  Event Mask on line 31
+            MR31: u1,
+        }),
+        ///  Rising Trigger selection register
+        RTSR1: mmio.Mmio(packed struct(u32) {
+            ///  Rising trigger event configuration of line 0
+            TR0: u1,
+            ///  Rising trigger event configuration of line 1
+            TR1: u1,
+            ///  Rising trigger event configuration of line 2
+            TR2: u1,
+            ///  Rising trigger event configuration of line 3
+            TR3: u1,
+            ///  Rising trigger event configuration of line 4
+            TR4: u1,
+            ///  Rising trigger event configuration of line 5
+            TR5: u1,
+            ///  Rising trigger event configuration of line 6
+            TR6: u1,
+            ///  Rising trigger event configuration of line 7
+            TR7: u1,
+            ///  Rising trigger event configuration of line 8
+            TR8: u1,
+            ///  Rising trigger event configuration of line 9
+            TR9: u1,
+            ///  Rising trigger event configuration of line 10
+            TR10: u1,
+            ///  Rising trigger event configuration of line 11
+            TR11: u1,
+            ///  Rising trigger event configuration of line 12
+            TR12: u1,
+            ///  Rising trigger event configuration of line 13
+            TR13: u1,
+            ///  Rising trigger event configuration of line 14
+            TR14: u1,
+            ///  Rising trigger event configuration of line 15
+            TR15: u1,
+            ///  Rising trigger event configuration of line 16
+            TR16: u1,
+            ///  Rising trigger event configuration of line 17
+            TR17: u1,
+            ///  Rising trigger event configuration of line 18
+            TR18: u1,
+            ///  Rising trigger event configuration of line 19
+            TR19: u1,
+            ///  Rising trigger event configuration of line 20
+            TR20: u1,
+            ///  Rising trigger event configuration of line 21
+            TR21: u1,
+            ///  Rising trigger event configuration of line 22
+            TR22: u1,
+            reserved29: u6,
+            ///  Rising trigger event configuration of line 29
+            TR29: u1,
+            ///  Rising trigger event configuration of line 30
+            TR30: u1,
+            ///  Rising trigger event configuration of line 31
+            TR31: u1,
+        }),
+        ///  Falling Trigger selection register
+        FTSR1: mmio.Mmio(packed struct(u32) {
+            ///  Falling trigger event configuration of line 0
+            TR0: u1,
+            ///  Falling trigger event configuration of line 1
+            TR1: u1,
+            ///  Falling trigger event configuration of line 2
+            TR2: u1,
+            ///  Falling trigger event configuration of line 3
+            TR3: u1,
+            ///  Falling trigger event configuration of line 4
+            TR4: u1,
+            ///  Falling trigger event configuration of line 5
+            TR5: u1,
+            ///  Falling trigger event configuration of line 6
+            TR6: u1,
+            ///  Falling trigger event configuration of line 7
+            TR7: u1,
+            ///  Falling trigger event configuration of line 8
+            TR8: u1,
+            ///  Falling trigger event configuration of line 9
+            TR9: u1,
+            ///  Falling trigger event configuration of line 10
+            TR10: u1,
+            ///  Falling trigger event configuration of line 11
+            TR11: u1,
+            ///  Falling trigger event configuration of line 12
+            TR12: u1,
+            ///  Falling trigger event configuration of line 13
+            TR13: u1,
+            ///  Falling trigger event configuration of line 14
+            TR14: u1,
+            ///  Falling trigger event configuration of line 15
+            TR15: u1,
+            ///  Falling trigger event configuration of line 16
+            TR16: u1,
+            ///  Falling trigger event configuration of line 17
+            TR17: u1,
+            ///  Falling trigger event configuration of line 18
+            TR18: u1,
+            ///  Falling trigger event configuration of line 19
+            TR19: u1,
+            ///  Falling trigger event configuration of line 20
+            TR20: u1,
+            ///  Falling trigger event configuration of line 21
+            TR21: u1,
+            ///  Falling trigger event configuration of line 22
+            TR22: u1,
+            reserved29: u6,
+            ///  Falling trigger event configuration of line 29
+            TR29: u1,
+            ///  Falling trigger event configuration of line 30.
+            TR30: u1,
+            ///  Falling trigger event configuration of line 31
+            TR31: u1,
+        }),
+        ///  Software interrupt event register
+        SWIER1: mmio.Mmio(packed struct(u32) {
+            ///  Software Interrupt on line 0
+            SWIER0: u1,
+            ///  Software Interrupt on line 1
+            SWIER1: u1,
+            ///  Software Interrupt on line 2
+            SWIER2: u1,
+            ///  Software Interrupt on line 3
+            SWIER3: u1,
+            ///  Software Interrupt on line 4
+            SWIER4: u1,
+            ///  Software Interrupt on line 5
+            SWIER5: u1,
+            ///  Software Interrupt on line 6
+            SWIER6: u1,
+            ///  Software Interrupt on line 7
+            SWIER7: u1,
+            ///  Software Interrupt on line 8
+            SWIER8: u1,
+            ///  Software Interrupt on line 9
+            SWIER9: u1,
+            ///  Software Interrupt on line 10
+            SWIER10: u1,
+            ///  Software Interrupt on line 11
+            SWIER11: u1,
+            ///  Software Interrupt on line 12
+            SWIER12: u1,
+            ///  Software Interrupt on line 13
+            SWIER13: u1,
+            ///  Software Interrupt on line 14
+            SWIER14: u1,
+            ///  Software Interrupt on line 15
+            SWIER15: u1,
+            ///  Software Interrupt on line 16
+            SWIER16: u1,
+            ///  Software Interrupt on line 17
+            SWIER17: u1,
+            ///  Software Interrupt on line 18
+            SWIER18: u1,
+            ///  Software Interrupt on line 19
+            SWIER19: u1,
+            ///  Software Interrupt on line 20
+            SWIER20: u1,
+            ///  Software Interrupt on line 21
+            SWIER21: u1,
+            ///  Software Interrupt on line 22
+            SWIER22: u1,
+            reserved29: u6,
+            ///  Software Interrupt on line 29
+            SWIER29: u1,
+            ///  Software Interrupt on line 309
+            SWIER30: u1,
+            ///  Software Interrupt on line 319
+            SWIER31: u1,
+        }),
+        ///  Pending register
+        PR1: mmio.Mmio(packed struct(u32) {
+            ///  Pending bit 0
+            PR0: u1,
+            ///  Pending bit 1
+            PR1: u1,
+            ///  Pending bit 2
+            PR2: u1,
+            ///  Pending bit 3
+            PR3: u1,
+            ///  Pending bit 4
+            PR4: u1,
+            ///  Pending bit 5
+            PR5: u1,
+            ///  Pending bit 6
+            PR6: u1,
+            ///  Pending bit 7
+            PR7: u1,
+            ///  Pending bit 8
+            PR8: u1,
+            ///  Pending bit 9
+            PR9: u1,
+            ///  Pending bit 10
+            PR10: u1,
+            ///  Pending bit 11
+            PR11: u1,
+            ///  Pending bit 12
+            PR12: u1,
+            ///  Pending bit 13
+            PR13: u1,
+            ///  Pending bit 14
+            PR14: u1,
+            ///  Pending bit 15
+            PR15: u1,
+            ///  Pending bit 16
+            PR16: u1,
+            ///  Pending bit 17
+            PR17: u1,
+            ///  Pending bit 18
+            PR18: u1,
+            ///  Pending bit 19
+            PR19: u1,
+            ///  Pending bit 20
+            PR20: u1,
+            ///  Pending bit 21
+            PR21: u1,
+            ///  Pending bit 22
+            PR22: u1,
+            reserved29: u6,
+            ///  Pending bit 29
+            PR29: u1,
+            ///  Pending bit 30
+            PR30: u1,
+            ///  Pending bit 31
+            PR31: u1,
+        }),
+        ///  Interrupt mask register
+        IMR2: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt Mask on external/internal line 32
+            MR32: u1,
+            ///  Interrupt Mask on external/internal line 33
+            MR33: u1,
+            ///  Interrupt Mask on external/internal line 34
+            MR34: u1,
+            ///  Interrupt Mask on external/internal line 35
+            MR35: u1,
+            padding: u28,
+        }),
+        ///  Event mask register
+        EMR2: mmio.Mmio(packed struct(u32) {
+            ///  Event mask on external/internal line 32
+            MR32: u1,
+            ///  Event mask on external/internal line 33
+            MR33: u1,
+            ///  Event mask on external/internal line 34
+            MR34: u1,
+            ///  Event mask on external/internal line 35
+            MR35: u1,
+            padding: u28,
+        }),
+        ///  Rising Trigger selection register
+        RTSR2: mmio.Mmio(packed struct(u32) {
+            ///  Rising trigger event configuration bit of line 32
+            TR32: u1,
+            ///  Rising trigger event configuration bit of line 33
+            TR33: u1,
+            padding: u30,
+        }),
+        ///  Falling Trigger selection register
+        FTSR2: mmio.Mmio(packed struct(u32) {
+            ///  Falling trigger event configuration bit of line 32
+            TR32: u1,
+            ///  Falling trigger event configuration bit of line 33
+            TR33: u1,
+            padding: u30,
+        }),
+        ///  Software interrupt event register
+        SWIER2: mmio.Mmio(packed struct(u32) {
+            ///  Software interrupt on line 32
+            SWIER32: u1,
+            ///  Software interrupt on line 33
+            SWIER33: u1,
+            padding: u30,
+        }),
+        ///  Pending register
+        PR2: mmio.Mmio(packed struct(u32) {
+            ///  Pending bit on line 32
+            PR32: u1,
+            ///  Pending bit on line 33
+            PR33: u1,
+            padding: u30,
+        }),
+    };
+
+    ///  Power control
+    pub const PWR = extern struct {
+        ///  power control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Low-power deep sleep
+            LPDS: u1,
+            ///  Power down deepsleep
+            PDDS: u1,
+            ///  Clear wakeup flag
+            CWUF: u1,
+            ///  Clear standby flag
+            CSBF: u1,
+            ///  Power voltage detector enable
+            PVDE: u1,
+            ///  PVD level selection
+            PLS: u3,
+            ///  Disable backup domain write protection
+            DBP: u1,
+            padding: u23,
+        }),
+        ///  power control/status register
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  Wakeup flag
+            WUF: u1,
+            ///  Standby flag
+            SBF: u1,
+            ///  PVD output
+            PVDO: u1,
+            reserved8: u5,
+            ///  Enable WKUP1 pin
+            EWUP1: u1,
+            ///  Enable WKUP2 pin
+            EWUP2: u1,
+            padding: u22,
+        }),
+    };
+
+    ///  Controller area network
+    pub const CAN = extern struct {
+        ///  master control register
+        MCR: mmio.Mmio(packed struct(u32) {
+            ///  INRQ
+            INRQ: u1,
+            ///  SLEEP
+            SLEEP: u1,
+            ///  TXFP
+            TXFP: u1,
+            ///  RFLM
+            RFLM: u1,
+            ///  NART
+            NART: u1,
+            ///  AWUM
+            AWUM: u1,
+            ///  ABOM
+            ABOM: u1,
+            ///  TTCM
+            TTCM: u1,
+            reserved15: u7,
+            ///  RESET
+            RESET: u1,
+            ///  DBF
+            DBF: u1,
+            padding: u15,
+        }),
+        ///  master status register
+        MSR: mmio.Mmio(packed struct(u32) {
+            ///  INAK
+            INAK: u1,
+            ///  SLAK
+            SLAK: u1,
+            ///  ERRI
+            ERRI: u1,
+            ///  WKUI
+            WKUI: u1,
+            ///  SLAKI
+            SLAKI: u1,
+            reserved8: u3,
+            ///  TXM
+            TXM: u1,
+            ///  RXM
+            RXM: u1,
+            ///  SAMP
+            SAMP: u1,
+            ///  RX
+            RX: u1,
+            padding: u20,
+        }),
+        ///  transmit status register
+        TSR: mmio.Mmio(packed struct(u32) {
+            ///  RQCP0
+            RQCP0: u1,
+            ///  TXOK0
+            TXOK0: u1,
+            ///  ALST0
+            ALST0: u1,
+            ///  TERR0
+            TERR0: u1,
+            reserved7: u3,
+            ///  ABRQ0
+            ABRQ0: u1,
+            ///  RQCP1
+            RQCP1: u1,
+            ///  TXOK1
+            TXOK1: u1,
+            ///  ALST1
+            ALST1: u1,
+            ///  TERR1
+            TERR1: u1,
+            reserved15: u3,
+            ///  ABRQ1
+            ABRQ1: u1,
+            ///  RQCP2
+            RQCP2: u1,
+            ///  TXOK2
+            TXOK2: u1,
+            ///  ALST2
+            ALST2: u1,
+            ///  TERR2
+            TERR2: u1,
+            reserved23: u3,
+            ///  ABRQ2
+            ABRQ2: u1,
+            ///  CODE
+            CODE: u2,
+            ///  Lowest priority flag for mailbox 0
+            TME0: u1,
+            ///  Lowest priority flag for mailbox 1
+            TME1: u1,
+            ///  Lowest priority flag for mailbox 2
+            TME2: u1,
+            ///  Lowest priority flag for mailbox 0
+            LOW0: u1,
+            ///  Lowest priority flag for mailbox 1
+            LOW1: u1,
+            ///  Lowest priority flag for mailbox 2
+            LOW2: u1,
+        }),
+        ///  receive FIFO 0 register
+        RF0R: mmio.Mmio(packed struct(u32) {
+            ///  FMP0
+            FMP0: u2,
+            reserved3: u1,
+            ///  FULL0
+            FULL0: u1,
+            ///  FOVR0
+            FOVR0: u1,
+            ///  RFOM0
+            RFOM0: u1,
+            padding: u26,
+        }),
+        ///  receive FIFO 1 register
+        RF1R: mmio.Mmio(packed struct(u32) {
+            ///  FMP1
+            FMP1: u2,
+            reserved3: u1,
+            ///  FULL1
+            FULL1: u1,
+            ///  FOVR1
+            FOVR1: u1,
+            ///  RFOM1
+            RFOM1: u1,
+            padding: u26,
+        }),
+        ///  interrupt enable register
+        IER: mmio.Mmio(packed struct(u32) {
+            ///  TMEIE
+            TMEIE: u1,
+            ///  FMPIE0
+            FMPIE0: u1,
+            ///  FFIE0
+            FFIE0: u1,
+            ///  FOVIE0
+            FOVIE0: u1,
+            ///  FMPIE1
+            FMPIE1: u1,
+            ///  FFIE1
+            FFIE1: u1,
+            ///  FOVIE1
+            FOVIE1: u1,
+            reserved8: u1,
+            ///  EWGIE
+            EWGIE: u1,
+            ///  EPVIE
+            EPVIE: u1,
+            ///  BOFIE
+            BOFIE: u1,
+            ///  LECIE
+            LECIE: u1,
+            reserved15: u3,
+            ///  ERRIE
+            ERRIE: u1,
+            ///  WKUIE
+            WKUIE: u1,
+            ///  SLKIE
+            SLKIE: u1,
+            padding: u14,
+        }),
+        ///  error status register
+        ESR: mmio.Mmio(packed struct(u32) {
+            ///  EWGF
+            EWGF: u1,
+            ///  EPVF
+            EPVF: u1,
+            ///  BOFF
+            BOFF: u1,
+            reserved4: u1,
+            ///  LEC
+            LEC: u3,
+            reserved16: u9,
+            ///  TEC
+            TEC: u8,
+            ///  REC
+            REC: u8,
+        }),
+        ///  bit timing register
+        BTR: mmio.Mmio(packed struct(u32) {
+            ///  BRP
+            BRP: u10,
+            reserved16: u6,
+            ///  TS1
+            TS1: u4,
+            ///  TS2
+            TS2: u3,
+            reserved24: u1,
+            ///  SJW
+            SJW: u2,
+            reserved30: u4,
+            ///  LBKM
+            LBKM: u1,
+            ///  SILM
+            SILM: u1,
+        }),
+        reserved384: [352]u8,
+        ///  TX mailbox identifier register
+        TI0R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data length control and time stamp register
+        TDT0R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data low register
+        TDL0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  mailbox data high register
+        TDH0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  TX mailbox identifier register
+        TI1R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data length control and time stamp register
+        TDT1R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data low register
+        TDL1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  mailbox data high register
+        TDH1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  TX mailbox identifier register
+        TI2R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data length control and time stamp register
+        TDT2R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data low register
+        TDL2R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  mailbox data high register
+        TDH2R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  receive FIFO mailbox identifier register
+        RI0R: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  receive FIFO mailbox data length control and time stamp register
+        RDT0R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  FMI
+            FMI: u8,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  receive FIFO mailbox data low register
+        RDL0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  receive FIFO mailbox data high register
+        RDH0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  receive FIFO mailbox identifier register
+        RI1R: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  receive FIFO mailbox data length control and time stamp register
+        RDT1R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  FMI
+            FMI: u8,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  receive FIFO mailbox data low register
+        RDL1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  receive FIFO mailbox data high register
+        RDH1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        reserved512: [48]u8,
+        ///  filter master register
+        FMR: mmio.Mmio(packed struct(u32) {
+            ///  Filter init mode
+            FINIT: u1,
+            reserved8: u7,
+            ///  CAN2 start bank
+            CAN2SB: u6,
+            padding: u18,
+        }),
+        ///  filter mode register
+        FM1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter mode
+            FBM0: u1,
+            ///  Filter mode
+            FBM1: u1,
+            ///  Filter mode
+            FBM2: u1,
+            ///  Filter mode
+            FBM3: u1,
+            ///  Filter mode
+            FBM4: u1,
+            ///  Filter mode
+            FBM5: u1,
+            ///  Filter mode
+            FBM6: u1,
+            ///  Filter mode
+            FBM7: u1,
+            ///  Filter mode
+            FBM8: u1,
+            ///  Filter mode
+            FBM9: u1,
+            ///  Filter mode
+            FBM10: u1,
+            ///  Filter mode
+            FBM11: u1,
+            ///  Filter mode
+            FBM12: u1,
+            ///  Filter mode
+            FBM13: u1,
+            ///  Filter mode
+            FBM14: u1,
+            ///  Filter mode
+            FBM15: u1,
+            ///  Filter mode
+            FBM16: u1,
+            ///  Filter mode
+            FBM17: u1,
+            ///  Filter mode
+            FBM18: u1,
+            ///  Filter mode
+            FBM19: u1,
+            ///  Filter mode
+            FBM20: u1,
+            ///  Filter mode
+            FBM21: u1,
+            ///  Filter mode
+            FBM22: u1,
+            ///  Filter mode
+            FBM23: u1,
+            ///  Filter mode
+            FBM24: u1,
+            ///  Filter mode
+            FBM25: u1,
+            ///  Filter mode
+            FBM26: u1,
+            ///  Filter mode
+            FBM27: u1,
+            padding: u4,
+        }),
+        reserved524: [4]u8,
+        ///  filter scale register
+        FS1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter scale configuration
+            FSC0: u1,
+            ///  Filter scale configuration
+            FSC1: u1,
+            ///  Filter scale configuration
+            FSC2: u1,
+            ///  Filter scale configuration
+            FSC3: u1,
+            ///  Filter scale configuration
+            FSC4: u1,
+            ///  Filter scale configuration
+            FSC5: u1,
+            ///  Filter scale configuration
+            FSC6: u1,
+            ///  Filter scale configuration
+            FSC7: u1,
+            ///  Filter scale configuration
+            FSC8: u1,
+            ///  Filter scale configuration
+            FSC9: u1,
+            ///  Filter scale configuration
+            FSC10: u1,
+            ///  Filter scale configuration
+            FSC11: u1,
+            ///  Filter scale configuration
+            FSC12: u1,
+            ///  Filter scale configuration
+            FSC13: u1,
+            ///  Filter scale configuration
+            FSC14: u1,
+            ///  Filter scale configuration
+            FSC15: u1,
+            ///  Filter scale configuration
+            FSC16: u1,
+            ///  Filter scale configuration
+            FSC17: u1,
+            ///  Filter scale configuration
+            FSC18: u1,
+            ///  Filter scale configuration
+            FSC19: u1,
+            ///  Filter scale configuration
+            FSC20: u1,
+            ///  Filter scale configuration
+            FSC21: u1,
+            ///  Filter scale configuration
+            FSC22: u1,
+            ///  Filter scale configuration
+            FSC23: u1,
+            ///  Filter scale configuration
+            FSC24: u1,
+            ///  Filter scale configuration
+            FSC25: u1,
+            ///  Filter scale configuration
+            FSC26: u1,
+            ///  Filter scale configuration
+            FSC27: u1,
+            padding: u4,
+        }),
+        reserved532: [4]u8,
+        ///  filter FIFO assignment register
+        FFA1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter FIFO assignment for filter 0
+            FFA0: u1,
+            ///  Filter FIFO assignment for filter 1
+            FFA1: u1,
+            ///  Filter FIFO assignment for filter 2
+            FFA2: u1,
+            ///  Filter FIFO assignment for filter 3
+            FFA3: u1,
+            ///  Filter FIFO assignment for filter 4
+            FFA4: u1,
+            ///  Filter FIFO assignment for filter 5
+            FFA5: u1,
+            ///  Filter FIFO assignment for filter 6
+            FFA6: u1,
+            ///  Filter FIFO assignment for filter 7
+            FFA7: u1,
+            ///  Filter FIFO assignment for filter 8
+            FFA8: u1,
+            ///  Filter FIFO assignment for filter 9
+            FFA9: u1,
+            ///  Filter FIFO assignment for filter 10
+            FFA10: u1,
+            ///  Filter FIFO assignment for filter 11
+            FFA11: u1,
+            ///  Filter FIFO assignment for filter 12
+            FFA12: u1,
+            ///  Filter FIFO assignment for filter 13
+            FFA13: u1,
+            ///  Filter FIFO assignment for filter 14
+            FFA14: u1,
+            ///  Filter FIFO assignment for filter 15
+            FFA15: u1,
+            ///  Filter FIFO assignment for filter 16
+            FFA16: u1,
+            ///  Filter FIFO assignment for filter 17
+            FFA17: u1,
+            ///  Filter FIFO assignment for filter 18
+            FFA18: u1,
+            ///  Filter FIFO assignment for filter 19
+            FFA19: u1,
+            ///  Filter FIFO assignment for filter 20
+            FFA20: u1,
+            ///  Filter FIFO assignment for filter 21
+            FFA21: u1,
+            ///  Filter FIFO assignment for filter 22
+            FFA22: u1,
+            ///  Filter FIFO assignment for filter 23
+            FFA23: u1,
+            ///  Filter FIFO assignment for filter 24
+            FFA24: u1,
+            ///  Filter FIFO assignment for filter 25
+            FFA25: u1,
+            ///  Filter FIFO assignment for filter 26
+            FFA26: u1,
+            ///  Filter FIFO assignment for filter 27
+            FFA27: u1,
+            padding: u4,
+        }),
+        reserved540: [4]u8,
+        ///  CAN filter activation register
+        FA1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter active
+            FACT0: u1,
+            ///  Filter active
+            FACT1: u1,
+            ///  Filter active
+            FACT2: u1,
+            ///  Filter active
+            FACT3: u1,
+            ///  Filter active
+            FACT4: u1,
+            ///  Filter active
+            FACT5: u1,
+            ///  Filter active
+            FACT6: u1,
+            ///  Filter active
+            FACT7: u1,
+            ///  Filter active
+            FACT8: u1,
+            ///  Filter active
+            FACT9: u1,
+            ///  Filter active
+            FACT10: u1,
+            ///  Filter active
+            FACT11: u1,
+            ///  Filter active
+            FACT12: u1,
+            ///  Filter active
+            FACT13: u1,
+            ///  Filter active
+            FACT14: u1,
+            ///  Filter active
+            FACT15: u1,
+            ///  Filter active
+            FACT16: u1,
+            ///  Filter active
+            FACT17: u1,
+            ///  Filter active
+            FACT18: u1,
+            ///  Filter active
+            FACT19: u1,
+            ///  Filter active
+            FACT20: u1,
+            ///  Filter active
+            FACT21: u1,
+            ///  Filter active
+            FACT22: u1,
+            ///  Filter active
+            FACT23: u1,
+            ///  Filter active
+            FACT24: u1,
+            ///  Filter active
+            FACT25: u1,
+            ///  Filter active
+            FACT26: u1,
+            ///  Filter active
+            FACT27: u1,
+            padding: u4,
+        }),
+        reserved576: [32]u8,
+        ///  Filter bank 0 register 1
+        F0R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 0 register 2
+        F0R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 1 register 1
+        F1R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 1 register 2
+        F1R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 2 register 1
+        F2R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 2 register 2
+        F2R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 3 register 1
+        F3R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 3 register 2
+        F3R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 1
+        F4R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 2
+        F4R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 5 register 1
+        F5R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 5 register 2
+        F5R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 6 register 1
+        F6R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 6 register 2
+        F6R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 7 register 1
+        F7R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 7 register 2
+        F7R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 8 register 1
+        F8R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 8 register 2
+        F8R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 9 register 1
+        F9R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 9 register 2
+        F9R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 10 register 1
+        F10R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 10 register 2
+        F10R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 11 register 1
+        F11R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 11 register 2
+        F11R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 1
+        F12R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 12 register 2
+        F12R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 13 register 1
+        F13R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 13 register 2
+        F13R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 14 register 1
+        F14R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 14 register 2
+        F14R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 15 register 1
+        F15R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 15 register 2
+        F15R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 16 register 1
+        F16R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 16 register 2
+        F16R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 17 register 1
+        F17R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 17 register 2
+        F17R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 18 register 1
+        F18R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 18 register 2
+        F18R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 19 register 1
+        F19R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 19 register 2
+        F19R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 20 register 1
+        F20R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 20 register 2
+        F20R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 21 register 1
+        F21R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 21 register 2
+        F21R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 22 register 1
+        F22R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 22 register 2
+        F22R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 23 register 1
+        F23R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 23 register 2
+        F23R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 24 register 1
+        F24R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 24 register 2
+        F24R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 25 register 1
+        F25R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 25 register 2
+        F25R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 26 register 1
+        F26R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 26 register 2
+        F26R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 27 register 1
+        F27R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 27 register 2
+        F27R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+    };
+
+    ///  Universal serial bus full-speed device interface
+    pub const USB_FS = extern struct {
+        ///  endpoint 0 register
+        USB_EP0R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 1 register
+        USB_EP1R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 2 register
+        USB_EP2R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 3 register
+        USB_EP3R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 4 register
+        USB_EP4R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 5 register
+        USB_EP5R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 6 register
+        USB_EP6R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        ///  endpoint 7 register
+        USB_EP7R: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint address
+            EA: u4,
+            ///  Status bits, for transmission transfers
+            STAT_TX: u2,
+            ///  Data Toggle, for transmission transfers
+            DTOG_TX: u1,
+            ///  Correct Transfer for transmission
+            CTR_TX: u1,
+            ///  Endpoint kind
+            EP_KIND: u1,
+            ///  Endpoint type
+            EP_TYPE: u2,
+            ///  Setup transaction completed
+            SETUP: u1,
+            ///  Status bits, for reception transfers
+            STAT_RX: u2,
+            ///  Data Toggle, for reception transfers
+            DTOG_RX: u1,
+            ///  Correct transfer for reception
+            CTR_RX: u1,
+            padding: u16,
+        }),
+        reserved64: [32]u8,
+        ///  control register
+        USB_CNTR: mmio.Mmio(packed struct(u32) {
+            ///  Force USB Reset
+            FRES: u1,
+            ///  Power down
+            PDWN: u1,
+            ///  Low-power mode
+            LPMODE: u1,
+            ///  Force suspend
+            FSUSP: u1,
+            ///  Resume request
+            RESUME: u1,
+            reserved8: u3,
+            ///  Expected start of frame interrupt mask
+            ESOFM: u1,
+            ///  Start of frame interrupt mask
+            SOFM: u1,
+            ///  USB reset interrupt mask
+            RESETM: u1,
+            ///  Suspend mode interrupt mask
+            SUSPM: u1,
+            ///  Wakeup interrupt mask
+            WKUPM: u1,
+            ///  Error interrupt mask
+            ERRM: u1,
+            ///  Packet memory area over / underrun interrupt mask
+            PMAOVRM: u1,
+            ///  Correct transfer interrupt mask
+            CTRM: u1,
+            padding: u16,
+        }),
+        ///  interrupt status register
+        ISTR: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint Identifier
+            EP_ID: u4,
+            ///  Direction of transaction
+            DIR: u1,
+            reserved8: u3,
+            ///  Expected start frame
+            ESOF: u1,
+            ///  start of frame
+            SOF: u1,
+            ///  reset request
+            RESET: u1,
+            ///  Suspend mode request
+            SUSP: u1,
+            ///  Wakeup
+            WKUP: u1,
+            ///  Error
+            ERR: u1,
+            ///  Packet memory area over / underrun
+            PMAOVR: u1,
+            ///  Correct transfer
+            CTR: u1,
+            padding: u16,
+        }),
+        ///  frame number register
+        FNR: mmio.Mmio(packed struct(u32) {
+            ///  Frame number
+            FN: u11,
+            ///  Lost SOF
+            LSOF: u2,
+            ///  Locked
+            LCK: u1,
+            ///  Receive data - line status
+            RXDM: u1,
+            ///  Receive data + line status
+            RXDP: u1,
+            padding: u16,
+        }),
+        ///  device address
+        DADDR: mmio.Mmio(packed struct(u32) {
+            ///  Device address
+            ADD: u1,
+            ///  Device address
+            ADD1: u1,
+            ///  Device address
+            ADD2: u1,
+            ///  Device address
+            ADD3: u1,
+            ///  Device address
+            ADD4: u1,
+            ///  Device address
+            ADD5: u1,
+            ///  Device address
+            ADD6: u1,
+            ///  Enable function
+            EF: u1,
+            padding: u24,
+        }),
+        ///  Buffer table address
+        BTABLE: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Buffer table
+            BTABLE: u13,
+            padding: u16,
+        }),
+    };
+
+    ///  Inter-integrated circuit
+    pub const I2C1 = extern struct {
+        ///  Control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral enable
+            PE: u1,
+            ///  TX Interrupt enable
+            TXIE: u1,
+            ///  RX Interrupt enable
+            RXIE: u1,
+            ///  Address match interrupt enable (slave only)
+            ADDRIE: u1,
+            ///  Not acknowledge received interrupt enable
+            NACKIE: u1,
+            ///  STOP detection Interrupt enable
+            STOPIE: u1,
+            ///  Transfer Complete interrupt enable
+            TCIE: u1,
+            ///  Error interrupts enable
+            ERRIE: u1,
+            ///  Digital noise filter
+            DNF: u4,
+            ///  Analog noise filter OFF
+            ANFOFF: u1,
+            ///  Software reset
+            SWRST: u1,
+            ///  DMA transmission requests enable
+            TXDMAEN: u1,
+            ///  DMA reception requests enable
+            RXDMAEN: u1,
+            ///  Slave byte control
+            SBC: u1,
+            ///  Clock stretching disable
+            NOSTRETCH: u1,
+            ///  Wakeup from STOP enable
+            WUPEN: u1,
+            ///  General call enable
+            GCEN: u1,
+            ///  SMBus Host address enable
+            SMBHEN: u1,
+            ///  SMBus Device Default address enable
+            SMBDEN: u1,
+            ///  SMBUS alert enable
+            ALERTEN: u1,
+            ///  PEC enable
+            PECEN: u1,
+            padding: u8,
+        }),
+        ///  Control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Slave address bit 0 (master mode)
+            SADD0: u1,
+            ///  Slave address bit 7:1 (master mode)
+            SADD1: u7,
+            ///  Slave address bit 9:8 (master mode)
+            SADD8: u2,
+            ///  Transfer direction (master mode)
+            RD_WRN: u1,
+            ///  10-bit addressing mode (master mode)
+            ADD10: u1,
+            ///  10-bit address header only read direction (master receiver mode)
+            HEAD10R: u1,
+            ///  Start generation
+            START: u1,
+            ///  Stop generation (master mode)
+            STOP: u1,
+            ///  NACK generation (slave mode)
+            NACK: u1,
+            ///  Number of bytes
+            NBYTES: u8,
+            ///  NBYTES reload mode
+            RELOAD: u1,
+            ///  Automatic end mode (master mode)
+            AUTOEND: u1,
+            ///  Packet error checking byte
+            PECBYTE: u1,
+            padding: u5,
+        }),
+        ///  Own address register 1
+        OAR1: mmio.Mmio(packed struct(u32) {
+            ///  Interface address
+            OA1_0: u1,
+            ///  Interface address
+            OA1_1: u7,
+            ///  Interface address
+            OA1_8: u2,
+            ///  Own Address 1 10-bit mode
+            OA1MODE: u1,
+            reserved15: u4,
+            ///  Own Address 1 enable
+            OA1EN: u1,
+            padding: u16,
+        }),
+        ///  Own address register 2
+        OAR2: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Interface address
+            OA2: u7,
+            ///  Own Address 2 masks
+            OA2MSK: u3,
+            reserved15: u4,
+            ///  Own Address 2 enable
+            OA2EN: u1,
+            padding: u16,
+        }),
+        ///  Timing register
+        TIMINGR: mmio.Mmio(packed struct(u32) {
+            ///  SCL low period (master mode)
+            SCLL: u8,
+            ///  SCL high period (master mode)
+            SCLH: u8,
+            ///  Data hold time
+            SDADEL: u4,
+            ///  Data setup time
+            SCLDEL: u4,
+            reserved28: u4,
+            ///  Timing prescaler
+            PRESC: u4,
+        }),
+        ///  Status register 1
+        TIMEOUTR: mmio.Mmio(packed struct(u32) {
+            ///  Bus timeout A
+            TIMEOUTA: u12,
+            ///  Idle clock timeout detection
+            TIDLE: u1,
+            reserved15: u2,
+            ///  Clock timeout enable
+            TIMOUTEN: u1,
+            ///  Bus timeout B
+            TIMEOUTB: u12,
+            reserved31: u3,
+            ///  Extended clock timeout enable
+            TEXTEN: u1,
+        }),
+        ///  Interrupt and Status register
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  Transmit data register empty (transmitters)
+            TXE: u1,
+            ///  Transmit interrupt status (transmitters)
+            TXIS: u1,
+            ///  Receive data register not empty (receivers)
+            RXNE: u1,
+            ///  Address matched (slave mode)
+            ADDR: u1,
+            ///  Not acknowledge received flag
+            NACKF: u1,
+            ///  Stop detection flag
+            STOPF: u1,
+            ///  Transfer Complete (master mode)
+            TC: u1,
+            ///  Transfer Complete Reload
+            TCR: u1,
+            ///  Bus error
+            BERR: u1,
+            ///  Arbitration lost
+            ARLO: u1,
+            ///  Overrun/Underrun (slave mode)
+            OVR: u1,
+            ///  PEC Error in reception
+            PECERR: u1,
+            ///  Timeout or t_low detection flag
+            TIMEOUT: u1,
+            ///  SMBus alert
+            ALERT: u1,
+            reserved15: u1,
+            ///  Bus busy
+            BUSY: u1,
+            ///  Transfer direction (Slave mode)
+            DIR: u1,
+            ///  Address match code (Slave mode)
+            ADDCODE: u7,
+            padding: u8,
+        }),
+        ///  Interrupt clear register
+        ICR: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Address Matched flag clear
+            ADDRCF: u1,
+            ///  Not Acknowledge flag clear
+            NACKCF: u1,
+            ///  Stop detection flag clear
+            STOPCF: u1,
+            reserved8: u2,
+            ///  Bus error flag clear
+            BERRCF: u1,
+            ///  Arbitration lost flag clear
+            ARLOCF: u1,
+            ///  Overrun/Underrun flag clear
+            OVRCF: u1,
+            ///  PEC Error flag clear
+            PECCF: u1,
+            ///  Timeout detection flag clear
+            TIMOUTCF: u1,
+            ///  Alert flag clear
+            ALERTCF: u1,
+            padding: u18,
+        }),
+        ///  PEC register
+        PECR: mmio.Mmio(packed struct(u32) {
+            ///  Packet error checking register
+            PEC: u8,
+            padding: u24,
+        }),
+        ///  Receive data register
+        RXDR: mmio.Mmio(packed struct(u32) {
+            ///  8-bit receive data
+            RXDATA: u8,
+            padding: u24,
+        }),
+        ///  Transmit data register
+        TXDR: mmio.Mmio(packed struct(u32) {
+            ///  8-bit transmit data
+            TXDATA: u8,
+            padding: u24,
+        }),
+    };
+
+    ///  Advanced timer
+    pub const TIM1 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            reserved11: u1,
+            ///  UIF status bit remapping
+            UIFREMAP: u1,
+            padding: u20,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/compare preloaded control
+            CCPC: u1,
+            reserved2: u1,
+            ///  Capture/compare control update selection
+            CCUS: u1,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            ///  Output Idle state 1
+            OIS1: u1,
+            ///  Output Idle state 1
+            OIS1N: u1,
+            ///  Output Idle state 2
+            OIS2: u1,
+            ///  Output Idle state 2
+            OIS2N: u1,
+            ///  Output Idle state 3
+            OIS3: u1,
+            ///  Output Idle state 3
+            OIS3N: u1,
+            ///  Output Idle state 4
+            OIS4: u1,
+            reserved16: u1,
+            ///  Output Idle state 5
+            OIS5: u1,
+            reserved18: u1,
+            ///  Output Idle state 6
+            OIS6: u1,
+            reserved20: u1,
+            ///  Master mode selection 2
+            MMS2: u4,
+            padding: u8,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            ///  OCREF clear selection
+            OCCS: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            ///  Slave mode selection bit 3
+            SMS3: u1,
+            padding: u15,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            ///  COM interrupt enable
+            COMIE: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            ///  Break interrupt enable
+            BIE: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            ///  COM DMA request enable
+            COMDE: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            ///  COM interrupt flag
+            COMIF: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            ///  Break interrupt flag
+            BIF: u1,
+            ///  Break 2 interrupt flag
+            B2IF: u1,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            reserved16: u3,
+            ///  Capture/Compare 5 interrupt flag
+            C5IF: u1,
+            ///  Capture/Compare 6 interrupt flag
+            C6IF: u1,
+            padding: u14,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            ///  Capture/Compare control update generation
+            COMG: u1,
+            ///  Trigger generation
+            TG: u1,
+            ///  Break generation
+            BG: u1,
+            ///  Break 2 generation
+            B2G: u1,
+            padding: u23,
+        }),
+        ///  capture/compare mode register (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            ///  Output Compare 1 clear enable
+            OC1CE: u1,
+            ///  Capture/Compare 2 selection
+            CC2S: u2,
+            ///  Output Compare 2 fast enable
+            OC2FE: u1,
+            ///  Output Compare 2 preload enable
+            OC2PE: u1,
+            ///  Output Compare 2 mode
+            OC2M: u3,
+            ///  Output Compare 2 clear enable
+            OC2CE: u1,
+            ///  Output Compare 1 mode bit 3
+            OC1M_3: u1,
+            reserved24: u7,
+            ///  Output Compare 2 mode bit 3
+            OC2M_3: u1,
+            padding: u7,
+        }),
+        ///  capture/compare mode register (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 3 selection
+            CC3S: u2,
+            ///  Output compare 3 fast enable
+            OC3FE: u1,
+            ///  Output compare 3 preload enable
+            OC3PE: u1,
+            ///  Output compare 3 mode
+            OC3M: u3,
+            ///  Output compare 3 clear enable
+            OC3CE: u1,
+            ///  Capture/Compare 4 selection
+            CC4S: u2,
+            ///  Output compare 4 fast enable
+            OC4FE: u1,
+            ///  Output compare 4 preload enable
+            OC4PE: u1,
+            ///  Output compare 4 mode
+            OC4M: u3,
+            ///  Output compare 4 clear enable
+            OC4CE: u1,
+            ///  Output Compare 3 mode bit 3
+            OC3M_3: u1,
+            reserved24: u7,
+            ///  Output Compare 4 mode bit 3
+            OC4M_3: u1,
+            padding: u7,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            ///  Capture/Compare 1 complementary output enable
+            CC1NE: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            ///  Capture/Compare 2 complementary output enable
+            CC2NE: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            ///  Capture/Compare 3 complementary output enable
+            CC3NE: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            reserved15: u1,
+            ///  Capture/Compare 4 output Polarity
+            CC4NP: u1,
+            ///  Capture/Compare 5 output enable
+            CC5E: u1,
+            ///  Capture/Compare 5 output Polarity
+            CC5P: u1,
+            reserved20: u2,
+            ///  Capture/Compare 6 output enable
+            CC6E: u1,
+            ///  Capture/Compare 6 output Polarity
+            CC6P: u1,
+            padding: u10,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            reserved31: u15,
+            ///  UIF copy
+            UIFCPY: u1,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        ///  repetition counter register
+        RCR: mmio.Mmio(packed struct(u32) {
+            ///  Repetition counter value
+            REP: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 2 value
+            CCR2: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 3 value
+            CCR3: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 3 value
+            CCR4: u16,
+            padding: u16,
+        }),
+        ///  break and dead-time register
+        BDTR: mmio.Mmio(packed struct(u32) {
+            ///  Dead-time generator setup
+            DTG: u8,
+            ///  Lock configuration
+            LOCK: u2,
+            ///  Off-state selection for Idle mode
+            OSSI: u1,
+            ///  Off-state selection for Run mode
+            OSSR: u1,
+            ///  Break enable
+            BKE: u1,
+            ///  Break polarity
+            BKP: u1,
+            ///  Automatic output enable
+            AOE: u1,
+            ///  Main output enable
+            MOE: u1,
+            ///  Break filter
+            BKF: u4,
+            ///  Break 2 filter
+            BK2F: u4,
+            ///  Break 2 enable
+            BK2E: u1,
+            ///  Break 2 polarity
+            BK2P: u1,
+            padding: u6,
+        }),
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+        reserved84: [4]u8,
+        ///  capture/compare mode register 3 (output mode)
+        CCMR3_Output: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Output compare 5 fast enable
+            OC5FE: u1,
+            ///  Output compare 5 preload enable
+            OC5PE: u1,
+            ///  Output compare 5 mode
+            OC5M: u3,
+            ///  Output compare 5 clear enable
+            OC5CE: u1,
+            reserved10: u2,
+            ///  Output compare 6 fast enable
+            OC6FE: u1,
+            ///  Output compare 6 preload enable
+            OC6PE: u1,
+            ///  Output compare 6 mode
+            OC6M: u3,
+            ///  Output compare 6 clear enable
+            OC6CE: u1,
+            ///  Outout Compare 5 mode bit 3
+            OC5M_3: u1,
+            reserved24: u7,
+            ///  Outout Compare 6 mode bit 3
+            OC6M_3: u1,
+            padding: u7,
+        }),
+        ///  capture/compare register 5
+        CCR5: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 5 value
+            CCR5: u16,
+            reserved29: u13,
+            ///  Group Channel 5 and Channel 1
+            GC5C1: u1,
+            ///  Group Channel 5 and Channel 2
+            GC5C2: u1,
+            ///  Group Channel 5 and Channel 3
+            GC5C3: u1,
+        }),
+        ///  capture/compare register 6
+        CCR6: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 6 value
+            CCR6: u16,
+            padding: u16,
+        }),
+        ///  option registers
+        OR: mmio.Mmio(packed struct(u32) {
+            ///  TIM1_ETR_ADC1 remapping capability
+            TIM1_ETR_ADC1_RMP: u2,
+            ///  TIM1_ETR_ADC4 remapping capability
+            TIM1_ETR_ADC4_RMP: u2,
+            padding: u28,
+        }),
+    };
+
+    ///  Debug support
+    pub const DBGMCU = extern struct {
+        ///  MCU Device ID Code Register
+        IDCODE: mmio.Mmio(packed struct(u32) {
+            ///  Device Identifier
+            DEV_ID: u12,
+            reserved16: u4,
+            ///  Revision Identifier
+            REV_ID: u16,
+        }),
+        ///  Debug MCU Configuration Register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Debug Sleep mode
+            DBG_SLEEP: u1,
+            ///  Debug Stop Mode
+            DBG_STOP: u1,
+            ///  Debug Standby Mode
+            DBG_STANDBY: u1,
+            reserved5: u2,
+            ///  Trace pin assignment control
+            TRACE_IOEN: u1,
+            ///  Trace pin assignment control
+            TRACE_MODE: u2,
+            padding: u24,
+        }),
+        ///  APB Low Freeze Register
+        APB1FZ: mmio.Mmio(packed struct(u32) {
+            ///  Debug Timer 2 stopped when Core is halted
+            DBG_TIM2_STOP: u1,
+            ///  Debug Timer 3 stopped when Core is halted
+            DBG_TIM3_STOP: u1,
+            ///  Debug Timer 4 stopped when Core is halted
+            DBG_TIM4_STOP: u1,
+            ///  Debug Timer 5 stopped when Core is halted
+            DBG_TIM5_STOP: u1,
+            ///  Debug Timer 6 stopped when Core is halted
+            DBG_TIM6_STOP: u1,
+            ///  Debug Timer 7 stopped when Core is halted
+            DBG_TIM7_STOP: u1,
+            ///  Debug Timer 12 stopped when Core is halted
+            DBG_TIM12_STOP: u1,
+            ///  Debug Timer 13 stopped when Core is halted
+            DBG_TIM13_STOP: u1,
+            ///  Debug Timer 14 stopped when Core is halted
+            DBG_TIMER14_STOP: u1,
+            ///  Debug Timer 18 stopped when Core is halted
+            DBG_TIM18_STOP: u1,
+            ///  Debug RTC stopped when Core is halted
+            DBG_RTC_STOP: u1,
+            ///  Debug Window Wachdog stopped when Core is halted
+            DBG_WWDG_STOP: u1,
+            ///  Debug Independent Wachdog stopped when Core is halted
+            DBG_IWDG_STOP: u1,
+            reserved21: u8,
+            ///  SMBUS timeout mode stopped when Core is halted
+            I2C1_SMBUS_TIMEOUT: u1,
+            ///  SMBUS timeout mode stopped when Core is halted
+            I2C2_SMBUS_TIMEOUT: u1,
+            reserved25: u2,
+            ///  Debug CAN stopped when core is halted
+            DBG_CAN_STOP: u1,
+            padding: u6,
+        }),
+        ///  APB High Freeze Register
+        APB2FZ: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Debug Timer 15 stopped when Core is halted
+            DBG_TIM15_STOP: u1,
+            ///  Debug Timer 16 stopped when Core is halted
+            DBG_TIM16_STOP: u1,
+            ///  Debug Timer 17 stopped when Core is halted
+            DBG_TIM17_STO: u1,
+            ///  Debug Timer 19 stopped when Core is halted
+            DBG_TIM19_STOP: u1,
+            padding: u26,
+        }),
+    };
+};
diff --git a/src/chips/STM32F407.json b/src/chips/STM32F407.json
new file mode 100644
index 000000000..7f592e5d0
--- /dev/null
+++ b/src/chips/STM32F407.json
@@ -0,0 +1,50953 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "RNG": {
+        "description": "Random number generator",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "Interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RNGEN": {
+                    "description": "Random number generator\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEIS": {
+                    "description": "Seed error interrupt\n              status",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CEIS": {
+                    "description": "Clock error interrupt\n              status",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SECS": {
+                    "description": "Seed error current status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CECS": {
+                    "description": "Clock error current status",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DRDY": {
+                    "description": "Data ready",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "data register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RNDATA": {
+                    "description": "Random data",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DCMI": {
+        "description": "Digital camera interface",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "DCMI enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EDM": {
+                    "description": "Extended data mode",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "FCRC": {
+                    "description": "Frame capture rate control",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "VSPOL": {
+                    "description": "Vertical synchronization\n              polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "HSPOL": {
+                    "description": "Horizontal synchronization\n              polarity",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PCKPOL": {
+                    "description": "Pixel clock polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ESS": {
+                    "description": "Embedded synchronization\n              select",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "JPEG": {
+                    "description": "JPEG format",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CROP": {
+                    "description": "Crop feature",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CM": {
+                    "description": "Capture mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CAPTURE": {
+                    "description": "Capture enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FNE": {
+                    "description": "FIFO not empty",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "VSYNC": {
+                    "description": "VSYNC",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HSYNC": {
+                    "description": "HSYNC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RIS": {
+              "description": "raw interrupt status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "LINE_RIS": {
+                    "description": "Line raw interrupt status",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "VSYNC_RIS": {
+                    "description": "VSYNC raw interrupt status",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_RIS": {
+                    "description": "Synchronization error raw interrupt\n              status",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OVR_RIS": {
+                    "description": "Overrun raw interrupt\n              status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FRAME_RIS": {
+                    "description": "Capture complete raw interrupt\n              status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LINE_IE": {
+                    "description": "Line interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "VSYNC_IE": {
+                    "description": "VSYNC interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_IE": {
+                    "description": "Synchronization error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OVR_IE": {
+                    "description": "Overrun interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FRAME_IE": {
+                    "description": "Capture complete interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MIS": {
+              "description": "masked interrupt status\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "LINE_MIS": {
+                    "description": "Line masked interrupt\n              status",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "VSYNC_MIS": {
+                    "description": "VSYNC masked interrupt\n              status",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_MIS": {
+                    "description": "Synchronization error masked interrupt\n              status",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OVR_MIS": {
+                    "description": "Overrun masked interrupt\n              status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FRAME_MIS": {
+                    "description": "Capture complete masked interrupt\n              status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "interrupt clear register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "LINE_ISC": {
+                    "description": "line interrupt status\n              clear",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "VSYNC_ISC": {
+                    "description": "Vertical synch interrupt status\n              clear",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_ISC": {
+                    "description": "Synchronization error interrupt status\n              clear",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OVR_ISC": {
+                    "description": "Overrun interrupt status\n              clear",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FRAME_ISC": {
+                    "description": "Capture complete interrupt status\n              clear",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ESCR": {
+              "description": "embedded synchronization code\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEC": {
+                    "description": "Frame end delimiter code",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "LEC": {
+                    "description": "Line end delimiter code",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "LSC": {
+                    "description": "Line start delimiter code",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "FSC": {
+                    "description": "Frame start delimiter code",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ESUR": {
+              "description": "embedded synchronization unmask\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEU": {
+                    "description": "Frame end delimiter unmask",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "LEU": {
+                    "description": "Line end delimiter unmask",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "LSU": {
+                    "description": "Line start delimiter\n              unmask",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "FSU": {
+                    "description": "Frame start delimiter\n              unmask",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CWSTRT": {
+              "description": "crop window start",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VST": {
+                    "description": "Vertical start line count",
+                    "offset": 16,
+                    "size": 13
+                  },
+                  "HOFFCNT": {
+                    "description": "Horizontal offset count",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "CWSIZE": {
+              "description": "crop window size",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VLINE": {
+                    "description": "Vertical line count",
+                    "offset": 16,
+                    "size": 14
+                  },
+                  "CAPCNT": {
+                    "description": "Capture count",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "data register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "Byte3": {
+                    "description": "Data byte 3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "Byte2": {
+                    "description": "Data byte 2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "Byte1": {
+                    "description": "Data byte 1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "Byte0": {
+                    "description": "Data byte 0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FSMC": {
+        "description": "Flexible static memory controller",
+        "children": {
+          "registers": {
+            "BCR1": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR1": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR2": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          2",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR2": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR3": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          3",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR3": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR4": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          4",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR4": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          4",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "PCR2": {
+              "description": "PC Card/NAND Flash control register\n          2",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR2": {
+              "description": "FIFO status and interrupt register\n          2",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM2": {
+              "description": "Common memory space timing register\n          2",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT2": {
+              "description": "Attribute memory space timing register\n          2",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "ATTHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "ATTHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "ATTWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "ATTSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ECCR2": {
+              "description": "ECC result register 2",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ECCx": {
+                    "description": "ECCx",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PCR3": {
+              "description": "PC Card/NAND Flash control register\n          3",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR3": {
+              "description": "FIFO status and interrupt register\n          3",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM3": {
+              "description": "Common memory space timing register\n          3",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT3": {
+              "description": "Attribute memory space timing register\n          3",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "ATTHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "ATTHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "ATTWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "ATTSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ECCR3": {
+              "description": "ECC result register 3",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ECCx": {
+                    "description": "ECCx",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PCR4": {
+              "description": "PC Card/NAND Flash control register\n          4",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR4": {
+              "description": "FIFO status and interrupt register\n          4",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM4": {
+              "description": "Common memory space timing register\n          4",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT4": {
+              "description": "Attribute memory space timing register\n          4",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "ATTHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "ATTHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "ATTWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "ATTSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PIO4": {
+              "description": "I/O space timing register 4",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOHIZx": {
+                    "description": "IOHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "IOHOLDx": {
+                    "description": "IOHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IOWAITx": {
+                    "description": "IOWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IOSETx": {
+                    "description": "IOSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BWTR1": {
+              "description": "SRAM/NOR-Flash write timing registers\n          1",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR2": {
+              "description": "SRAM/NOR-Flash write timing registers\n          2",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR3": {
+              "description": "SRAM/NOR-Flash write timing registers\n          3",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR4": {
+              "description": "SRAM/NOR-Flash write timing registers\n          4",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DBG": {
+        "description": "Debug support",
+        "children": {
+          "registers": {
+            "DBGMCU_IDCODE": {
+              "description": "IDCODE",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 268461073,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DEV_ID": {
+                    "description": "DEV_ID",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "REV_ID": {
+                    "description": "REV_ID",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DBGMCU_CR": {
+              "description": "Control Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBG_SLEEP": {
+                    "description": "DBG_SLEEP",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DBG_STOP": {
+                    "description": "DBG_STOP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DBG_STANDBY": {
+                    "description": "DBG_STANDBY",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TRACE_IOEN": {
+                    "description": "TRACE_IOEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TRACE_MODE": {
+                    "description": "TRACE_MODE",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DBG_I2C2_SMBUS_TIMEOUT": {
+                    "description": "DBG_I2C2_SMBUS_TIMEOUT",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DBG_TIM8_STOP": {
+                    "description": "DBG_TIM8_STOP",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "DBG_TIM5_STOP": {
+                    "description": "DBG_TIM5_STOP",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DBG_TIM6_STOP": {
+                    "description": "DBG_TIM6_STOP",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBG_TIM7_STOP": {
+                    "description": "DBG_TIM7_STOP",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DBGMCU_APB1_FZ": {
+              "description": "Debug MCU APB1 Freeze registe",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBG_TIM2_STOP": {
+                    "description": "DBG_TIM2_STOP",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DBG_TIM3_STOP": {
+                    "description": "DBG_TIM3 _STOP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DBG_TIM4_STOP": {
+                    "description": "DBG_TIM4_STOP",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DBG_TIM5_STOP": {
+                    "description": "DBG_TIM5_STOP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DBG_TIM6_STOP": {
+                    "description": "DBG_TIM6_STOP",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DBG_TIM7_STOP": {
+                    "description": "DBG_TIM7_STOP",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DBG_TIM12_STOP": {
+                    "description": "DBG_TIM12_STOP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DBG_TIM13_STOP": {
+                    "description": "DBG_TIM13_STOP",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DBG_TIM14_STOP": {
+                    "description": "DBG_TIM14_STOP",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DBG_WWDG_STOP": {
+                    "description": "DBG_WWDG_STOP",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DBG_IWDEG_STOP": {
+                    "description": "DBG_IWDEG_STOP",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DBG_J2C1_SMBUS_TIMEOUT": {
+                    "description": "DBG_J2C1_SMBUS_TIMEOUT",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "DBG_J2C2_SMBUS_TIMEOUT": {
+                    "description": "DBG_J2C2_SMBUS_TIMEOUT",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DBG_J2C3SMBUS_TIMEOUT": {
+                    "description": "DBG_J2C3SMBUS_TIMEOUT",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "DBG_CAN1_STOP": {
+                    "description": "DBG_CAN1_STOP",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DBG_CAN2_STOP": {
+                    "description": "DBG_CAN2_STOP",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DBGMCU_APB2_FZ": {
+              "description": "Debug MCU APB2 Freeze registe",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBG_TIM1_STOP": {
+                    "description": "TIM1 counter stopped when core is\n              halted",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DBG_TIM8_STOP": {
+                    "description": "TIM8 counter stopped when core is\n              halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DBG_TIM9_STOP": {
+                    "description": "TIM9 counter stopped when core is\n              halted",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DBG_TIM10_STOP": {
+                    "description": "TIM10 counter stopped when core is\n              halted",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "DBG_TIM11_STOP": {
+                    "description": "TIM11 counter stopped when core is\n              halted",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DMA2": {
+        "description": "DMA controller",
+        "children": {
+          "registers": {
+            "LISR": {
+              "description": "low interrupt status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TCIF3": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x = 3..0)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "HTIF3": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=3..0)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TEIF3": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=3..0)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DMEIF3": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=3..0)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FEIF3": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=3..0)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TCIF2": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x = 3..0)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HTIF2": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=3..0)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TEIF2": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=3..0)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DMEIF2": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=3..0)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FEIF2": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=3..0)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TCIF1": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x = 3..0)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "HTIF1": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=3..0)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TEIF1": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=3..0)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DMEIF1": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=3..0)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FEIF1": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=3..0)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TCIF0": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x = 3..0)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HTIF0": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=3..0)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TEIF0": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=3..0)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DMEIF0": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=3..0)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FEIF0": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=3..0)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HISR": {
+              "description": "high interrupt status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TCIF7": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x=7..4)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "HTIF7": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=7..4)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TEIF7": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=7..4)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DMEIF7": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=7..4)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FEIF7": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=7..4)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TCIF6": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x=7..4)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HTIF6": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=7..4)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TEIF6": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=7..4)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DMEIF6": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=7..4)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FEIF6": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=7..4)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TCIF5": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x=7..4)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "HTIF5": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=7..4)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TEIF5": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=7..4)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DMEIF5": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=7..4)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FEIF5": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=7..4)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TCIF4": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x=7..4)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HTIF4": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=7..4)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TEIF4": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=7..4)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DMEIF4": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=7..4)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FEIF4": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=7..4)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LIFCR": {
+              "description": "low interrupt flag clear\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTCIF3": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 3..0)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "CHTIF3": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 3..0)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CTEIF3": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 3..0)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CDMEIF3": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 3..0)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "CFEIF3": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 3..0)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CTCIF2": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 3..0)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CHTIF2": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 3..0)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CTEIF2": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 3..0)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "CDMEIF2": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 3..0)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CFEIF2": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 3..0)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CTCIF1": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 3..0)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CHTIF1": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 3..0)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CTEIF1": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 3..0)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CDMEIF1": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 3..0)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CFEIF1": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 3..0)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTCIF0": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 3..0)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CHTIF0": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 3..0)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CTEIF0": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 3..0)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CDMEIF0": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 3..0)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CFEIF0": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 3..0)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HIFCR": {
+              "description": "high interrupt flag clear\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTCIF7": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 7..4)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "CHTIF7": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 7..4)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CTEIF7": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 7..4)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CDMEIF7": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 7..4)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "CFEIF7": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 7..4)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CTCIF6": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 7..4)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CHTIF6": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 7..4)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CTEIF6": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 7..4)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "CDMEIF6": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 7..4)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CFEIF6": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 7..4)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CTCIF5": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 7..4)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CHTIF5": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 7..4)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CTEIF5": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 7..4)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CDMEIF5": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 7..4)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CFEIF5": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 7..4)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTCIF4": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 7..4)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CHTIF4": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 7..4)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CTEIF4": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 7..4)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CDMEIF4": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 7..4)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CFEIF4": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 7..4)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S0CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S0NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S0PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S0M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S0M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S0FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S1CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S1NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S1PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S1M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S1M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S1FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S2CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S2NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S2PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S2M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S2M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S2FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S3CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S3NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S3PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S3M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S3M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S3FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S4CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S4NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S4PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S4M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S4M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S4FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S5CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S5NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S5PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S5M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S5M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S5FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S6CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S6NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S6PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S6M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S6M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S6FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S7CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S7NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S7PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S7M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S7M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S7FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SCB_ACTRL": {
+        "description": "System control block ACTLR",
+        "children": {
+          "registers": {
+            "ACTRL": {
+              "description": "Auxiliary control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DISMCYCINT": {
+                    "description": "DISMCYCINT",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DISDEFWBUF": {
+                    "description": "DISDEFWBUF",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DISFOLD": {
+                    "description": "DISFOLD",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DISFPCA": {
+                    "description": "DISFPCA",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DISOOFP": {
+                    "description": "DISOOFP",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RCC": {
+        "description": "Reset and clock control",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "clock control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 131,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PLLI2SRDY": {
+                    "description": "PLLI2S clock ready flag",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLLI2SON": {
+                    "description": "PLLI2S enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PLLRDY": {
+                    "description": "Main PLL (PLL) clock ready\n              flag",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLLON": {
+                    "description": "Main PLL (PLL) enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "CSSON": {
+                    "description": "Clock security system\n              enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "HSEBYP": {
+                    "description": "HSE clock bypass",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "HSERDY": {
+                    "description": "HSE clock ready flag",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSEON": {
+                    "description": "HSE clock enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "HSICAL": {
+                    "description": "Internal high-speed clock\n              calibration",
+                    "offset": 8,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "HSITRIM": {
+                    "description": "Internal high-speed clock\n              trimming",
+                    "offset": 3,
+                    "size": 5
+                  },
+                  "HSIRDY": {
+                    "description": "Internal high-speed clock ready\n              flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSION": {
+                    "description": "Internal high-speed clock\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PLLCFGR": {
+              "description": "PLL configuration register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 603992080,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PLLQ3": {
+                    "description": "Main PLL (PLL) division factor for USB\n              OTG FS, SDIO and random number generator\n              clocks",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PLLQ2": {
+                    "description": "Main PLL (PLL) division factor for USB\n              OTG FS, SDIO and random number generator\n              clocks",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PLLQ1": {
+                    "description": "Main PLL (PLL) division factor for USB\n              OTG FS, SDIO and random number generator\n              clocks",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PLLQ0": {
+                    "description": "Main PLL (PLL) division factor for USB\n              OTG FS, SDIO and random number generator\n              clocks",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PLLSRC": {
+                    "description": "Main PLL(PLL) and audio PLL (PLLI2S)\n              entry clock source",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PLLP1": {
+                    "description": "Main PLL (PLL) division factor for main\n              system clock",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PLLP0": {
+                    "description": "Main PLL (PLL) division factor for main\n              system clock",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PLLN8": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PLLN7": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PLLN6": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PLLN5": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PLLN4": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PLLN3": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PLLN2": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PLLN1": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PLLN0": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PLLM5": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PLLM4": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PLLM3": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PLLM2": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PLLM1": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PLLM0": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CFGR": {
+              "description": "clock configuration register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCO2": {
+                    "description": "Microcontroller clock output\n              2",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MCO2PRE": {
+                    "description": "MCO2 prescaler",
+                    "offset": 27,
+                    "size": 3
+                  },
+                  "MCO1PRE": {
+                    "description": "MCO1 prescaler",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "I2SSRC": {
+                    "description": "I2S clock selection",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "MCO1": {
+                    "description": "Microcontroller clock output\n              1",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "RTCPRE": {
+                    "description": "HSE division factor for RTC\n              clock",
+                    "offset": 16,
+                    "size": 5
+                  },
+                  "PPRE2": {
+                    "description": "APB high-speed prescaler\n              (APB2)",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "PPRE1": {
+                    "description": "APB Low speed prescaler\n              (APB1)",
+                    "offset": 10,
+                    "size": 3
+                  },
+                  "HPRE": {
+                    "description": "AHB prescaler",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "SWS1": {
+                    "description": "System clock switch status",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SWS0": {
+                    "description": "System clock switch status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SW1": {
+                    "description": "System clock switch",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SW0": {
+                    "description": "System clock switch",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CIR": {
+              "description": "clock interrupt register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSSC": {
+                    "description": "Clock security system interrupt\n              clear",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PLLI2SRDYC": {
+                    "description": "PLLI2S ready interrupt\n              clear",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PLLRDYC": {
+                    "description": "Main PLL(PLL) ready interrupt\n              clear",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "HSERDYC": {
+                    "description": "HSE ready interrupt clear",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "HSIRDYC": {
+                    "description": "HSI ready interrupt clear",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSERDYC": {
+                    "description": "LSE ready interrupt clear",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSIRDYC": {
+                    "description": "LSI ready interrupt clear",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PLLI2SRDYIE": {
+                    "description": "PLLI2S ready interrupt\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PLLRDYIE": {
+                    "description": "Main PLL (PLL) ready interrupt\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "HSERDYIE": {
+                    "description": "HSE ready interrupt enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "HSIRDYIE": {
+                    "description": "HSI ready interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LSERDYIE": {
+                    "description": "LSE ready interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LSIRDYIE": {
+                    "description": "LSI ready interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CSSF": {
+                    "description": "Clock security system interrupt\n              flag",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLLI2SRDYF": {
+                    "description": "PLLI2S ready interrupt\n              flag",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLLRDYF": {
+                    "description": "Main PLL (PLL) ready interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSERDYF": {
+                    "description": "HSE ready interrupt flag",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSIRDYF": {
+                    "description": "HSI ready interrupt flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSERDYF": {
+                    "description": "LSE ready interrupt flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSIRDYF": {
+                    "description": "LSI ready interrupt flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "AHB1RSTR": {
+              "description": "AHB1 peripheral reset register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OTGHSRST": {
+                    "description": "USB OTG HS module reset",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ETHMACRST": {
+                    "description": "Ethernet MAC reset",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DMA2RST": {
+                    "description": "DMA2 reset",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DMA1RST": {
+                    "description": "DMA2 reset",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CRCRST": {
+                    "description": "CRC reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIOIRST": {
+                    "description": "IO port I reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIOHRST": {
+                    "description": "IO port H reset",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIOGRST": {
+                    "description": "IO port G reset",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIOFRST": {
+                    "description": "IO port F reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIOERST": {
+                    "description": "IO port E reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIODRST": {
+                    "description": "IO port D reset",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIOCRST": {
+                    "description": "IO port C reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIOBRST": {
+                    "description": "IO port B reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIOARST": {
+                    "description": "IO port A reset",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB2RSTR": {
+              "description": "AHB2 peripheral reset register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OTGFSRST": {
+                    "description": "USB OTG FS module reset",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RNGRST": {
+                    "description": "Random number generator module\n              reset",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DCMIRST": {
+                    "description": "Camera interface reset",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB3RSTR": {
+              "description": "AHB3 peripheral reset register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSMCRST": {
+                    "description": "Flexible static memory controller module\n              reset",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1RSTR": {
+              "description": "APB1 peripheral reset register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACRST": {
+                    "description": "DAC reset",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "PWRRST": {
+                    "description": "Power interface reset",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "CAN2RST": {
+                    "description": "CAN2 reset",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CAN1RST": {
+                    "description": "CAN1 reset",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "I2C3RST": {
+                    "description": "I2C3 reset",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "I2C2RST": {
+                    "description": "I2C 2 reset",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "I2C1RST": {
+                    "description": "I2C 1 reset",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "UART5RST": {
+                    "description": "USART 5 reset",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "UART4RST": {
+                    "description": "USART 4 reset",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UART3RST": {
+                    "description": "USART 3 reset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "UART2RST": {
+                    "description": "USART 2 reset",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SPI3RST": {
+                    "description": "SPI 3 reset",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SPI2RST": {
+                    "description": "SPI 2 reset",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WWDGRST": {
+                    "description": "Window watchdog reset",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TIM14RST": {
+                    "description": "TIM14 reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIM13RST": {
+                    "description": "TIM13 reset",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIM12RST": {
+                    "description": "TIM12 reset",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TIM7RST": {
+                    "description": "TIM7 reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIM6RST": {
+                    "description": "TIM6 reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM5RST": {
+                    "description": "TIM5 reset",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TIM4RST": {
+                    "description": "TIM4 reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIM3RST": {
+                    "description": "TIM3 reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM2RST": {
+                    "description": "TIM2 reset",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB2RSTR": {
+              "description": "APB2 peripheral reset register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM11RST": {
+                    "description": "TIM11 reset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TIM10RST": {
+                    "description": "TIM10 reset",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TIM9RST": {
+                    "description": "TIM9 reset",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SYSCFGRST": {
+                    "description": "System configuration controller\n              reset",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI1RST": {
+                    "description": "SPI 1 reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SDIORST": {
+                    "description": "SDIO reset",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ADCRST": {
+                    "description": "ADC interface reset (common to all\n              ADCs)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "USART6RST": {
+                    "description": "USART6 reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USART1RST": {
+                    "description": "USART1 reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM8RST": {
+                    "description": "TIM8 reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM1RST": {
+                    "description": "TIM1 reset",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB1ENR": {
+              "description": "AHB1 peripheral clock register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 1048576,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OTGHSULPIEN": {
+                    "description": "USB OTG HSULPI clock\n              enable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "OTGHSEN": {
+                    "description": "USB OTG HS clock enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ETHMACPTPEN": {
+                    "description": "Ethernet PTP clock enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ETHMACRXEN": {
+                    "description": "Ethernet Reception clock\n              enable",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "ETHMACTXEN": {
+                    "description": "Ethernet Transmission clock\n              enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "ETHMACEN": {
+                    "description": "Ethernet MAC clock enable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DMA2EN": {
+                    "description": "DMA2 clock enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DMA1EN": {
+                    "description": "DMA1 clock enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "BKPSRAMEN": {
+                    "description": "Backup SRAM interface clock\n              enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CRCEN": {
+                    "description": "CRC clock enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIOIEN": {
+                    "description": "IO port I clock enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIOHEN": {
+                    "description": "IO port H clock enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIOGEN": {
+                    "description": "IO port G clock enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIOFEN": {
+                    "description": "IO port F clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIOEEN": {
+                    "description": "IO port E clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIODEN": {
+                    "description": "IO port D clock enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIOCEN": {
+                    "description": "IO port C clock enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIOBEN": {
+                    "description": "IO port B clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIOAEN": {
+                    "description": "IO port A clock enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB2ENR": {
+              "description": "AHB2 peripheral clock enable\n          register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OTGFSEN": {
+                    "description": "USB OTG FS clock enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RNGEN": {
+                    "description": "Random number generator clock\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DCMIEN": {
+                    "description": "Camera interface enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB3ENR": {
+              "description": "AHB3 peripheral clock enable\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSMCEN": {
+                    "description": "Flexible static memory controller module\n              clock enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1ENR": {
+              "description": "APB1 peripheral clock enable\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACEN": {
+                    "description": "DAC interface clock enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "PWREN": {
+                    "description": "Power interface clock\n              enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "CAN2EN": {
+                    "description": "CAN 2 clock enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CAN1EN": {
+                    "description": "CAN 1 clock enable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "I2C3EN": {
+                    "description": "I2C3 clock enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "I2C2EN": {
+                    "description": "I2C2 clock enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "I2C1EN": {
+                    "description": "I2C1 clock enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "UART5EN": {
+                    "description": "UART5 clock enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "UART4EN": {
+                    "description": "UART4 clock enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "USART3EN": {
+                    "description": "USART3 clock enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "USART2EN": {
+                    "description": "USART 2 clock enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SPI3EN": {
+                    "description": "SPI3 clock enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SPI2EN": {
+                    "description": "SPI2 clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WWDGEN": {
+                    "description": "Window watchdog clock\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TIM14EN": {
+                    "description": "TIM14 clock enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIM13EN": {
+                    "description": "TIM13 clock enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIM12EN": {
+                    "description": "TIM12 clock enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TIM7EN": {
+                    "description": "TIM7 clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIM6EN": {
+                    "description": "TIM6 clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM5EN": {
+                    "description": "TIM5 clock enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TIM4EN": {
+                    "description": "TIM4 clock enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIM3EN": {
+                    "description": "TIM3 clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM2EN": {
+                    "description": "TIM2 clock enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB2ENR": {
+              "description": "APB2 peripheral clock enable\n          register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM11EN": {
+                    "description": "TIM11 clock enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TIM10EN": {
+                    "description": "TIM10 clock enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TIM9EN": {
+                    "description": "TIM9 clock enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SYSCFGEN": {
+                    "description": "System configuration controller clock\n              enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI1EN": {
+                    "description": "SPI1 clock enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SDIOEN": {
+                    "description": "SDIO clock enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ADC3EN": {
+                    "description": "ADC3 clock enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ADC2EN": {
+                    "description": "ADC2 clock enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ADC1EN": {
+                    "description": "ADC1 clock enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "USART6EN": {
+                    "description": "USART6 clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USART1EN": {
+                    "description": "USART1 clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM8EN": {
+                    "description": "TIM8 clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM1EN": {
+                    "description": "TIM1 clock enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB1LPENR": {
+              "description": "AHB1 peripheral clock enable in low power\n          mode register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 2120716799,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OTGHSULPILPEN": {
+                    "description": "USB OTG HS ULPI clock enable during\n              Sleep mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "OTGHSLPEN": {
+                    "description": "USB OTG HS clock enable during Sleep\n              mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ETHMACPTPLPEN": {
+                    "description": "Ethernet PTP clock enable during Sleep\n              mode",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ETHMACRXLPEN": {
+                    "description": "Ethernet reception clock enable during\n              Sleep mode",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "ETHMACTXLPEN": {
+                    "description": "Ethernet transmission clock enable\n              during Sleep mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "ETHMACLPEN": {
+                    "description": "Ethernet MAC clock enable during Sleep\n              mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DMA2LPEN": {
+                    "description": "DMA2 clock enable during Sleep\n              mode",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DMA1LPEN": {
+                    "description": "DMA1 clock enable during Sleep\n              mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "BKPSRAMLPEN": {
+                    "description": "Backup SRAM interface clock enable\n              during Sleep mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "SRAM2LPEN": {
+                    "description": "SRAM 2 interface clock enable during\n              Sleep mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SRAM1LPEN": {
+                    "description": "SRAM 1interface clock enable during\n              Sleep mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FLITFLPEN": {
+                    "description": "Flash interface clock enable during\n              Sleep mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CRCLPEN": {
+                    "description": "CRC clock enable during Sleep\n              mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIOILPEN": {
+                    "description": "IO port I clock enable during Sleep\n              mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIOHLPEN": {
+                    "description": "IO port H clock enable during Sleep\n              mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIOGLPEN": {
+                    "description": "IO port G clock enable during Sleep\n              mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIOFLPEN": {
+                    "description": "IO port F clock enable during Sleep\n              mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIOELPEN": {
+                    "description": "IO port E clock enable during Sleep\n              mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIODLPEN": {
+                    "description": "IO port D clock enable during Sleep\n              mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIOCLPEN": {
+                    "description": "IO port C clock enable during Sleep\n              mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIOBLPEN": {
+                    "description": "IO port B clock enable during Sleep\n              mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIOALPEN": {
+                    "description": "IO port A clock enable during sleep\n              mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB2LPENR": {
+              "description": "AHB2 peripheral clock enable in low power\n          mode register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 241,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OTGFSLPEN": {
+                    "description": "USB OTG FS clock enable during Sleep\n              mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RNGLPEN": {
+                    "description": "Random number generator clock enable\n              during Sleep mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DCMILPEN": {
+                    "description": "Camera interface enable during Sleep\n              mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB3LPENR": {
+              "description": "AHB3 peripheral clock enable in low power\n          mode register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSMCLPEN": {
+                    "description": "Flexible static memory controller module\n              clock enable during Sleep mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1LPENR": {
+              "description": "APB1 peripheral clock enable in low power\n          mode register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 922667519,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACLPEN": {
+                    "description": "DAC interface clock enable during Sleep\n              mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "PWRLPEN": {
+                    "description": "Power interface clock enable during\n              Sleep mode",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "CAN2LPEN": {
+                    "description": "CAN 2 clock enable during Sleep\n              mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CAN1LPEN": {
+                    "description": "CAN 1 clock enable during Sleep\n              mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "I2C3LPEN": {
+                    "description": "I2C3 clock enable during Sleep\n              mode",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "I2C2LPEN": {
+                    "description": "I2C2 clock enable during Sleep\n              mode",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "I2C1LPEN": {
+                    "description": "I2C1 clock enable during Sleep\n              mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "UART5LPEN": {
+                    "description": "UART5 clock enable during Sleep\n              mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "UART4LPEN": {
+                    "description": "UART4 clock enable during Sleep\n              mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "USART3LPEN": {
+                    "description": "USART3 clock enable during Sleep\n              mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "USART2LPEN": {
+                    "description": "USART2 clock enable during Sleep\n              mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SPI3LPEN": {
+                    "description": "SPI3 clock enable during Sleep\n              mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SPI2LPEN": {
+                    "description": "SPI2 clock enable during Sleep\n              mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WWDGLPEN": {
+                    "description": "Window watchdog clock enable during\n              Sleep mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TIM14LPEN": {
+                    "description": "TIM14 clock enable during Sleep\n              mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIM13LPEN": {
+                    "description": "TIM13 clock enable during Sleep\n              mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIM12LPEN": {
+                    "description": "TIM12 clock enable during Sleep\n              mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TIM7LPEN": {
+                    "description": "TIM7 clock enable during Sleep\n              mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIM6LPEN": {
+                    "description": "TIM6 clock enable during Sleep\n              mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM5LPEN": {
+                    "description": "TIM5 clock enable during Sleep\n              mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TIM4LPEN": {
+                    "description": "TIM4 clock enable during Sleep\n              mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIM3LPEN": {
+                    "description": "TIM3 clock enable during Sleep\n              mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM2LPEN": {
+                    "description": "TIM2 clock enable during Sleep\n              mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB2LPENR": {
+              "description": "APB2 peripheral clock enabled in low power\n          mode register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 483123,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM11LPEN": {
+                    "description": "TIM11 clock enable during Sleep\n              mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TIM10LPEN": {
+                    "description": "TIM10 clock enable during Sleep\n              mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TIM9LPEN": {
+                    "description": "TIM9 clock enable during sleep\n              mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SYSCFGLPEN": {
+                    "description": "System configuration controller clock\n              enable during Sleep mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI1LPEN": {
+                    "description": "SPI 1 clock enable during Sleep\n              mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SDIOLPEN": {
+                    "description": "SDIO clock enable during Sleep\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ADC3LPEN": {
+                    "description": "ADC 3 clock enable during Sleep\n              mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ADC2LPEN": {
+                    "description": "ADC2 clock enable during Sleep\n              mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ADC1LPEN": {
+                    "description": "ADC1 clock enable during Sleep\n              mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "USART6LPEN": {
+                    "description": "USART6 clock enable during Sleep\n              mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USART1LPEN": {
+                    "description": "USART1 clock enable during Sleep\n              mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM8LPEN": {
+                    "description": "TIM8 clock enable during Sleep\n              mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM1LPEN": {
+                    "description": "TIM1 clock enable during Sleep\n              mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BDCR": {
+              "description": "Backup domain control register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BDRST": {
+                    "description": "Backup domain software\n              reset",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RTCEN": {
+                    "description": "RTC clock enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RTCSEL1": {
+                    "description": "RTC clock source selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RTCSEL0": {
+                    "description": "RTC clock source selection",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LSEBYP": {
+                    "description": "External low-speed oscillator\n              bypass",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LSERDY": {
+                    "description": "External low-speed oscillator\n              ready",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSEON": {
+                    "description": "External low-speed oscillator\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CSR": {
+              "description": "clock control & status\n          register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 234881024,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LPWRRSTF": {
+                    "description": "Low-power reset flag",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "WWDGRSTF": {
+                    "description": "Window watchdog reset flag",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WDGRSTF": {
+                    "description": "Independent watchdog reset\n              flag",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SFTRSTF": {
+                    "description": "Software reset flag",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "PORRSTF": {
+                    "description": "POR/PDR reset flag",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PADRSTF": {
+                    "description": "PIN reset flag",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BORRSTF": {
+                    "description": "BOR reset flag",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "RMVF": {
+                    "description": "Remove reset flag",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LSIRDY": {
+                    "description": "Internal low-speed oscillator\n              ready",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSION": {
+                    "description": "Internal low-speed oscillator\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SSCGR": {
+              "description": "spread spectrum clock generation\n          register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SSCGEN": {
+                    "description": "Spread spectrum modulation\n              enable",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "SPREADSEL": {
+                    "description": "Spread Select",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INCSTEP": {
+                    "description": "Incrementation step",
+                    "offset": 13,
+                    "size": 15
+                  },
+                  "MODPER": {
+                    "description": "Modulation period",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "PLLI2SCFGR": {
+              "description": "PLLI2S configuration register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 536883200,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PLLI2SRx": {
+                    "description": "PLLI2S division factor for I2S\n              clocks",
+                    "offset": 28,
+                    "size": 3
+                  },
+                  "PLLI2SNx": {
+                    "description": "PLLI2S multiplication factor for\n              VCO",
+                    "offset": 6,
+                    "size": 9
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOI": {
+        "description": "General-purpose I/Os",
+        "children": {
+          "registers": {
+            "MODER": {
+              "description": "GPIO port mode register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODER15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MODER14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "MODER13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MODER12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "MODER11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MODER10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "MODER9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MODER8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "MODER7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MODER6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MODER5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MODER4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MODER3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MODER2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MODER1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODER0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTYPER": {
+              "description": "GPIO port output type register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OT15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OT14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OT13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OT12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OT11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OT10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OT9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OT8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OT7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OT6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OT5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OT4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OT3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OT2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OT1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OT0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OSPEEDR": {
+              "description": "GPIO port output speed\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OSPEEDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "OSPEEDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "OSPEEDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "OSPEEDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "OSPEEDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "OSPEEDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "OSPEEDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "OSPEEDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "OSPEEDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "OSPEEDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "OSPEEDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "OSPEEDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSPEEDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "OSPEEDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "OSPEEDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "OSPEEDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PUPDR": {
+              "description": "GPIO port pull-up/pull-down\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PUPDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "PUPDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "PUPDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "PUPDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "PUPDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "PUPDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "PUPDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "PUPDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PUPDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "PUPDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PUPDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PUPDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PUPDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PUPDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PUPDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "PUPDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "GPIO port input data register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDR15": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IDR14": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "IDR13": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "IDR12": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IDR11": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IDR10": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IDR9": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IDR8": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IDR7": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IDR6": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IDR5": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDR4": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDR3": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IDR2": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDR1": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IDR0": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ODR": {
+              "description": "GPIO port output data register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ODR15": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ODR14": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ODR13": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ODR12": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ODR11": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ODR10": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ODR9": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODR8": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ODR7": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ODR6": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ODR5": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ODR4": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ODR3": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ODR2": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ODR1": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ODR0": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BSRR": {
+              "description": "GPIO port bit set/reset\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BR15": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BR0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BS15": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BS14": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BS13": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BS12": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BS11": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BS10": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BS9": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BS8": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BS7": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BS6": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BS5": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BS4": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BS3": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BS2": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BS1": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BS0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LCKR": {
+              "description": "GPIO port configuration lock\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LCKK": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "LCK15": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LCK14": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "LCK13": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LCK12": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LCK11": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LCK10": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LCK9": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LCK8": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LCK7": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCK6": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LCK5": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LCK4": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "LCK3": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LCK2": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LCK1": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LCK0": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AFRL": {
+              "description": "GPIO alternate function low\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRL7": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRL6": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRL5": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRL4": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRL3": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRL2": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRL1": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRL0": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "AFRH": {
+              "description": "GPIO alternate function high\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRH15": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRH14": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRH13": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRH12": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRH11": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRH10": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRH9": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRH8": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FPU_CPACR": {
+        "description": "Floating point unit CPACR",
+        "children": {
+          "registers": {
+            "CPACR": {
+              "description": "Coprocessor access control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CP": {
+                    "description": "CP",
+                    "offset": 20,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NVIC_STIR": {
+        "description": "Nested vectored interrupt\n      controller",
+        "children": {
+          "registers": {
+            "STIR": {
+              "description": "Software trigger interrupt\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTID": {
+                    "description": "Software generated interrupt\n              ID",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SCB": {
+        "description": "System control block",
+        "children": {
+          "registers": {
+            "CPUID": {
+              "description": "CPUID base register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1091551809,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "Revision": {
+                    "description": "Revision number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "PartNo": {
+                    "description": "Part number of the\n              processor",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "Constant": {
+                    "description": "Reads as 0xF",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "Variant": {
+                    "description": "Variant number",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "Implementer": {
+                    "description": "Implementer code",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ICSR": {
+              "description": "Interrupt control and state\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTACTIVE": {
+                    "description": "Active vector",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "RETTOBASE": {
+                    "description": "Return to base level",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "VECTPENDING": {
+                    "description": "Pending vector",
+                    "offset": 12,
+                    "size": 7
+                  },
+                  "ISRPENDING": {
+                    "description": "Interrupt pending flag",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PENDSTCLR": {
+                    "description": "SysTick exception clear-pending\n              bit",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PENDSTSET": {
+                    "description": "SysTick exception set-pending\n              bit",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PENDSVCLR": {
+                    "description": "PendSV clear-pending bit",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PENDSVSET": {
+                    "description": "PendSV set-pending bit",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "NMIPENDSET": {
+                    "description": "NMI set-pending bit.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "VTOR": {
+              "description": "Vector table offset register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TBLOFF": {
+                    "description": "Vector table base offset\n              field",
+                    "offset": 9,
+                    "size": 21
+                  }
+                }
+              }
+            },
+            "AIRCR": {
+              "description": "Application interrupt and reset control\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTRESET": {
+                    "description": "VECTRESET",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "VECTCLRACTIVE": {
+                    "description": "VECTCLRACTIVE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SYSRESETREQ": {
+                    "description": "SYSRESETREQ",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PRIGROUP": {
+                    "description": "PRIGROUP",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "ENDIANESS": {
+                    "description": "ENDIANESS",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "VECTKEYSTAT": {
+                    "description": "Register key",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SCR": {
+              "description": "System control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLEEPONEXIT": {
+                    "description": "SLEEPONEXIT",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEEPDEEP": {
+                    "description": "SLEEPDEEP",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SEVEONPEND": {
+                    "description": "Send Event on Pending bit",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "Configuration and control\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NONBASETHRDENA": {
+                    "description": "Configures how the processor enters\n              Thread mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USERSETMPEND": {
+                    "description": "USERSETMPEND",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UNALIGN__TRP": {
+                    "description": "UNALIGN_ TRP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIV_0_TRP": {
+                    "description": "DIV_0_TRP",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BFHFNMIGN": {
+                    "description": "BFHFNMIGN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "STKALIGN": {
+                    "description": "STKALIGN",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SHPR1": {
+              "description": "System handler priority\n          registers",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_4": {
+                    "description": "Priority of system handler\n              4",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "PRI_5": {
+                    "description": "Priority of system handler\n              5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "PRI_6": {
+                    "description": "Priority of system handler\n              6",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHPR2": {
+              "description": "System handler priority\n          registers",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_11": {
+                    "description": "Priority of system handler\n              11",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHPR3": {
+              "description": "System handler priority\n          registers",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_14": {
+                    "description": "Priority of system handler\n              14",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "PRI_15": {
+                    "description": "Priority of system handler\n              15",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHCRS": {
+              "description": "System handler control and state\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMFAULTACT": {
+                    "description": "Memory management fault exception active\n              bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BUSFAULTACT": {
+                    "description": "Bus fault exception active\n              bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "USGFAULTACT": {
+                    "description": "Usage fault exception active\n              bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SVCALLACT": {
+                    "description": "SVC call active bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MONITORACT": {
+                    "description": "Debug monitor active bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PENDSVACT": {
+                    "description": "PendSV exception active\n              bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SYSTICKACT": {
+                    "description": "SysTick exception active\n              bit",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USGFAULTPENDED": {
+                    "description": "Usage fault exception pending\n              bit",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MEMFAULTPENDED": {
+                    "description": "Memory management fault exception\n              pending bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BUSFAULTPENDED": {
+                    "description": "Bus fault exception pending\n              bit",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SVCALLPENDED": {
+                    "description": "SVC call pending bit",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MEMFAULTENA": {
+                    "description": "Memory management fault enable\n              bit",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUSFAULTENA": {
+                    "description": "Bus fault enable bit",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USGFAULTENA": {
+                    "description": "Usage fault enable bit",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CFSR_UFSR_BFSR_MMFSR": {
+              "description": "Configurable fault status\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IACCVIOL": {
+                    "description": "Instruction access violation\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MUNSTKERR": {
+                    "description": "Memory manager fault on unstacking for a\n              return from exception",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MSTKERR": {
+                    "description": "Memory manager fault on stacking for\n              exception entry.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MLSPERR": {
+                    "description": "MLSPERR",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MMARVALID": {
+                    "description": "Memory Management Fault Address Register\n              (MMAR) valid flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IBUSERR": {
+                    "description": "Instruction bus error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PRECISERR": {
+                    "description": "Precise data bus error",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IMPRECISERR": {
+                    "description": "Imprecise data bus error",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "UNSTKERR": {
+                    "description": "Bus fault on unstacking for a return\n              from exception",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STKERR": {
+                    "description": "Bus fault on stacking for exception\n              entry",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LSPERR": {
+                    "description": "Bus fault on floating-point lazy state\n              preservation",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BFARVALID": {
+                    "description": "Bus Fault Address Register (BFAR) valid\n              flag",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "UNDEFINSTR": {
+                    "description": "Undefined instruction usage\n              fault",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "INVSTATE": {
+                    "description": "Invalid state usage fault",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INVPC": {
+                    "description": "Invalid PC load usage\n              fault",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "NOCP": {
+                    "description": "No coprocessor usage\n              fault.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UNALIGNED": {
+                    "description": "Unaligned access usage\n              fault",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "DIVBYZERO": {
+                    "description": "Divide by zero usage fault",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HFSR": {
+              "description": "Hard fault status register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTTBL": {
+                    "description": "Vector table hard fault",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FORCED": {
+                    "description": "Forced hard fault",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DEBUG_VT": {
+                    "description": "Reserved for Debug use",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMFAR": {
+              "description": "Memory management fault address\n          register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMFAR": {
+                    "description": "Memory management fault\n              address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BFAR": {
+              "description": "Bus fault address register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BFAR": {
+                    "description": "Bus fault address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "AFSR": {
+              "description": "Auxiliary fault status\n          register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IMPDEF": {
+                    "description": "Implementation defined",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "STK": {
+        "description": "SysTick timer",
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "SysTick control and status\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TICKINT": {
+                    "description": "SysTick exception request\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CLKSOURCE": {
+                    "description": "Clock source selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "COUNTFLAG": {
+                    "description": "COUNTFLAG",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LOAD": {
+              "description": "SysTick reload value register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RELOAD": {
+                    "description": "RELOAD value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "VAL": {
+              "description": "SysTick current value register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CURRENT": {
+                    "description": "Current counter value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "CALIB": {
+              "description": "SysTick calibration value\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TENMS": {
+                    "description": "Calibration value",
+                    "offset": 0,
+                    "size": 24
+                  },
+                  "SKEW": {
+                    "description": "SKEW flag: Indicates whether the TENMS\n              value is exact",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "NOREF": {
+                    "description": "NOREF flag. Reads as zero",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "MPU": {
+        "description": "Memory protection unit",
+        "children": {
+          "registers": {
+            "MPU_TYPER": {
+              "description": "MPU type register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SEPARATE": {
+                    "description": "Separate flag",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DREGION": {
+                    "description": "Number of MPU data regions",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IREGION": {
+                    "description": "Number of MPU instruction\n              regions",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MPU_CTRL": {
+              "description": "MPU control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enables the MPU",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HFNMIENA": {
+                    "description": "Enables the operation of MPU during hard\n              fault",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PRIVDEFENA": {
+                    "description": "Enable priviliged software access to\n              default memory map",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MPU_RNR": {
+              "description": "MPU region number register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION": {
+                    "description": "MPU region",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MPU_RBAR": {
+              "description": "MPU region base address\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION": {
+                    "description": "MPU region field",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "VALID": {
+                    "description": "MPU region number valid",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ADDR": {
+                    "description": "Region base address field",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "MPU_RASR": {
+              "description": "MPU region attribute and size\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Region enable bit.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SIZE": {
+                    "description": "Size of the MPU protection\n              region",
+                    "offset": 1,
+                    "size": 5
+                  },
+                  "SRD": {
+                    "description": "Subregion disable bits",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "B": {
+                    "description": "memory attribute",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "C": {
+                    "description": "memory attribute",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "S": {
+                    "description": "Shareable memory attribute",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TEX": {
+                    "description": "memory attribute",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "AP": {
+                    "description": "Access permission",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "XN": {
+                    "description": "Instruction access disable\n              bit",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FPU": {
+        "description": "Floting point unit",
+        "children": {
+          "registers": {
+            "FPCCR": {
+              "description": "Floating-point context control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSPACT": {
+                    "description": "LSPACT",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USER": {
+                    "description": "USER",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "THREAD": {
+                    "description": "THREAD",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "HFRDY": {
+                    "description": "HFRDY",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MMRDY": {
+                    "description": "MMRDY",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BFRDY": {
+                    "description": "BFRDY",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MONRDY": {
+                    "description": "MONRDY",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LSPEN": {
+                    "description": "LSPEN",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "ASPEN": {
+                    "description": "ASPEN",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FPCAR": {
+              "description": "Floating-point context address\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS": {
+                    "description": "Location of unpopulated\n              floating-point",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            },
+            "FPSCR": {
+              "description": "Floating-point status control\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOC": {
+                    "description": "Invalid operation cumulative exception\n              bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DZC": {
+                    "description": "Division by zero cumulative exception\n              bit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OFC": {
+                    "description": "Overflow cumulative exception\n              bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UFC": {
+                    "description": "Underflow cumulative exception\n              bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IXC": {
+                    "description": "Inexact cumulative exception\n              bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDC": {
+                    "description": "Input denormal cumulative exception\n              bit.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RMode": {
+                    "description": "Rounding Mode control\n              field",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "FZ": {
+                    "description": "Flush-to-zero mode control\n              bit:",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "DN": {
+                    "description": "Default NaN mode control\n              bit",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "AHP": {
+                    "description": "Alternative half-precision control\n              bit",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "V": {
+                    "description": "Overflow condition code\n              flag",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "C": {
+                    "description": "Carry condition code flag",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "Z": {
+                    "description": "Zero condition code flag",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "N": {
+                    "description": "Negative condition code\n              flag",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CRYP": {
+        "description": "Cryptographic processor",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ALGODIR": {
+                    "description": "Algorithm direction",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ALGOMODE0": {
+                    "description": "Algorithm mode",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "DATATYPE": {
+                    "description": "Data type selection",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "KEYSIZE": {
+                    "description": "Key size selection (AES mode\n              only)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "FFLUSH": {
+                    "description": "FIFO flush",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CRYPEN": {
+                    "description": "Cryptographic processor\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GCM_CCMPH": {
+                    "description": "GCM_CCMPH",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "ALGOMODE3": {
+                    "description": "ALGOMODE",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "BUSY": {
+                    "description": "Busy bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OFFU": {
+                    "description": "Output FIFO full",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OFNE": {
+                    "description": "Output FIFO not empty",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IFNF": {
+                    "description": "Input FIFO not full",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IFEM": {
+                    "description": "Input FIFO empty",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIN": {
+              "description": "data input register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATAIN": {
+                    "description": "Data input",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DOUT": {
+              "description": "data output register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATAOUT": {
+                    "description": "Data output",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMACR": {
+              "description": "DMA control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DOEN": {
+                    "description": "DMA output enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DIEN": {
+                    "description": "DMA input enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IMSCR": {
+              "description": "interrupt mask set/clear\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTIM": {
+                    "description": "Output FIFO service interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INIM": {
+                    "description": "Input FIFO service interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RISR": {
+              "description": "raw interrupt status register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "OUTRIS": {
+                    "description": "Output FIFO service raw interrupt\n              status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INRIS": {
+                    "description": "Input FIFO service raw interrupt\n              status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MISR": {
+              "description": "masked interrupt status\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "OUTMIS": {
+                    "description": "Output FIFO service masked interrupt\n              status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INMIS": {
+                    "description": "Input FIFO service masked interrupt\n              status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "K0LR": {
+              "description": "key registers",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "b224": {
+                    "description": "b224",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "b225": {
+                    "description": "b225",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "b226": {
+                    "description": "b226",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "b227": {
+                    "description": "b227",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "b228": {
+                    "description": "b228",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "b229": {
+                    "description": "b229",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "b230": {
+                    "description": "b230",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "b231": {
+                    "description": "b231",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "b232": {
+                    "description": "b232",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "b233": {
+                    "description": "b233",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "b234": {
+                    "description": "b234",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "b235": {
+                    "description": "b235",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "b236": {
+                    "description": "b236",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "b237": {
+                    "description": "b237",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "b238": {
+                    "description": "b238",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "b239": {
+                    "description": "b239",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "b240": {
+                    "description": "b240",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "b241": {
+                    "description": "b241",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "b242": {
+                    "description": "b242",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "b243": {
+                    "description": "b243",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "b244": {
+                    "description": "b244",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "b245": {
+                    "description": "b245",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "b246": {
+                    "description": "b246",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "b247": {
+                    "description": "b247",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "b248": {
+                    "description": "b248",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "b249": {
+                    "description": "b249",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "b250": {
+                    "description": "b250",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "b251": {
+                    "description": "b251",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "b252": {
+                    "description": "b252",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "b253": {
+                    "description": "b253",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "b254": {
+                    "description": "b254",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "b255": {
+                    "description": "b255",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "K0RR": {
+              "description": "key registers",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "b192": {
+                    "description": "b192",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "b193": {
+                    "description": "b193",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "b194": {
+                    "description": "b194",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "b195": {
+                    "description": "b195",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "b196": {
+                    "description": "b196",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "b197": {
+                    "description": "b197",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "b198": {
+                    "description": "b198",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "b199": {
+                    "description": "b199",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "b200": {
+                    "description": "b200",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "b201": {
+                    "description": "b201",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "b202": {
+                    "description": "b202",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "b203": {
+                    "description": "b203",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "b204": {
+                    "description": "b204",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "b205": {
+                    "description": "b205",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "b206": {
+                    "description": "b206",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "b207": {
+                    "description": "b207",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "b208": {
+                    "description": "b208",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "b209": {
+                    "description": "b209",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "b210": {
+                    "description": "b210",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "b211": {
+                    "description": "b211",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "b212": {
+                    "description": "b212",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "b213": {
+                    "description": "b213",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "b214": {
+                    "description": "b214",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "b215": {
+                    "description": "b215",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "b216": {
+                    "description": "b216",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "b217": {
+                    "description": "b217",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "b218": {
+                    "description": "b218",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "b219": {
+                    "description": "b219",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "b220": {
+                    "description": "b220",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "b221": {
+                    "description": "b221",
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+                    "size": 1
+                  },
+                  "b222": {
+                    "description": "b222",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "b223": {
+                    "description": "b223",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "K1LR": {
+              "description": "key registers",
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+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
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+                    "description": "b160",
+                    "offset": 0,
+                    "size": 1
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+                  "b161": {
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+                    "size": 1
+                  },
+                  "b162": {
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+                    "size": 1
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+                  "b163": {
+                    "description": "b163",
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+                    "size": 1
+                  },
+                  "b164": {
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+                    "size": 1
+                  },
+                  "b165": {
+                    "description": "b165",
+                    "offset": 5,
+                    "size": 1
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+                  "b166": {
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+                    "size": 1
+                  },
+                  "b167": {
+                    "description": "b167",
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+                    "size": 1
+                  },
+                  "b168": {
+                    "description": "b168",
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+                    "size": 1
+                  },
+                  "b169": {
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+                  "b170": {
+                    "description": "b170",
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+                    "size": 1
+                  },
+                  "b171": {
+                    "description": "b171",
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+                    "size": 1
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+                  "b172": {
+                    "description": "b172",
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+                    "size": 1
+                  },
+                  "b173": {
+                    "description": "b173",
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+                    "size": 1
+                  },
+                  "b174": {
+                    "description": "b174",
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+                    "size": 1
+                  },
+                  "b175": {
+                    "description": "b175",
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+                    "size": 1
+                  },
+                  "b176": {
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+                    "size": 1
+                  },
+                  "b177": {
+                    "description": "b177",
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+                  "b178": {
+                    "description": "b178",
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+                    "size": 1
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+                  "b179": {
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+                  "b180": {
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+                  "b186": {
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+                    "size": 1
+                  },
+                  "b187": {
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+                    "size": 1
+                  },
+                  "b188": {
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+                    "size": 1
+                  },
+                  "b189": {
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+                    "size": 1
+                  },
+                  "b190": {
+                    "description": "b190",
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+                    "size": 1
+                  },
+                  "b191": {
+                    "description": "b191",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "K1RR": {
+              "description": "key registers",
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+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
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+                  },
+                  "b157": {
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+                    "size": 1
+                  },
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+                    "size": 1
+                  },
+                  "b159": {
+                    "description": "b159",
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+                    "size": 1
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+              "description": "key registers",
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+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
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+                    "size": 1
+                  },
+                  "IV79": {
+                    "description": "IV79",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "IV78": {
+                    "description": "IV78",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "IV77": {
+                    "description": "IV77",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "IV76": {
+                    "description": "IV76",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IV75": {
+                    "description": "IV75",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "IV74": {
+                    "description": "IV74",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "IV73": {
+                    "description": "IV73",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IV72": {
+                    "description": "IV72",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "IV71": {
+                    "description": "IV71",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "IV70": {
+                    "description": "IV70",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "IV69": {
+                    "description": "IV69",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "IV68": {
+                    "description": "IV68",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "IV67": {
+                    "description": "IV67",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "IV66": {
+                    "description": "IV66",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "IV65": {
+                    "description": "IV65",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "IV64": {
+                    "description": "IV64",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IV1RR": {
+              "description": "initialization vector\n          registers",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IV127": {
+                    "description": "IV127",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IV126": {
+                    "description": "IV126",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IV125": {
+                    "description": "IV125",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IV124": {
+                    "description": "IV124",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IV123": {
+                    "description": "IV123",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IV122": {
+                    "description": "IV122",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IV121": {
+                    "description": "IV121",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IV120": {
+                    "description": "IV120",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IV119": {
+                    "description": "IV119",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IV118": {
+                    "description": "IV118",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IV117": {
+                    "description": "IV117",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IV116": {
+                    "description": "IV116",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IV115": {
+                    "description": "IV115",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IV114": {
+                    "description": "IV114",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "IV113": {
+                    "description": "IV113",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "IV112": {
+                    "description": "IV112",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IV111": {
+                    "description": "IV111",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "IV110": {
+                    "description": "IV110",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "IV109": {
+                    "description": "IV109",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "IV108": {
+                    "description": "IV108",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IV107": {
+                    "description": "IV107",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "IV106": {
+                    "description": "IV106",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "IV105": {
+                    "description": "IV105",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IV104": {
+                    "description": "IV104",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "IV103": {
+                    "description": "IV103",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "IV102": {
+                    "description": "IV102",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "IV101": {
+                    "description": "IV101",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "IV100": {
+                    "description": "IV100",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "IV99": {
+                    "description": "IV99",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "IV98": {
+                    "description": "IV98",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "IV97": {
+                    "description": "IV97",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "IV96": {
+                    "description": "IV96",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CSGCMCCM0R": {
+              "description": "context swap register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM0R": {
+                    "description": "CSGCMCCM0R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM1R": {
+              "description": "context swap register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM1R": {
+                    "description": "CSGCMCCM1R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM2R": {
+              "description": "context swap register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM2R": {
+                    "description": "CSGCMCCM2R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM3R": {
+              "description": "context swap register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM3R": {
+                    "description": "CSGCMCCM3R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM4R": {
+              "description": "context swap register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM4R": {
+                    "description": "CSGCMCCM4R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM5R": {
+              "description": "context swap register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM5R": {
+                    "description": "CSGCMCCM5R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM6R": {
+              "description": "context swap register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM6R": {
+                    "description": "CSGCMCCM6R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM7R": {
+              "description": "context swap register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM7R": {
+                    "description": "CSGCMCCM7R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM0R": {
+              "description": "context swap register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM0R": {
+                    "description": "CSGCM0R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM1R": {
+              "description": "context swap register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM1R": {
+                    "description": "CSGCM1R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM2R": {
+              "description": "context swap register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM2R": {
+                    "description": "CSGCM2R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM3R": {
+              "description": "context swap register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM3R": {
+                    "description": "CSGCM3R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM4R": {
+              "description": "context swap register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM4R": {
+                    "description": "CSGCM4R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM5R": {
+              "description": "context swap register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM5R": {
+                    "description": "CSGCM5R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM6R": {
+              "description": "context swap register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM6R": {
+                    "description": "CSGCM6R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM7R": {
+              "description": "context swap register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM7R": {
+                    "description": "CSGCM7R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "HASH": {
+        "description": "Hash processor",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INIT": {
+                    "description": "Initialize message digest\n              calculation",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DMAE": {
+                    "description": "DMA enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DATATYPE": {
+                    "description": "Data type selection",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MODE": {
+                    "description": "Mode selection",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ALGO0": {
+                    "description": "Algorithm selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "NBW": {
+                    "description": "Number of words already\n              pushed",
+                    "offset": 8,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "DINNE": {
+                    "description": "DIN not empty",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MDMAT": {
+                    "description": "Multiple DMA Transfers",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LKEY": {
+                    "description": "Long key selection",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ALGO1": {
+                    "description": "ALGO",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIN": {
+              "description": "data input register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATAIN": {
+                    "description": "Data input",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STR": {
+              "description": "start register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCAL": {
+                    "description": "Digest calculation",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "NBLW": {
+                    "description": "Number of valid bits in the last word of\n              the message",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "HR0": {
+              "description": "digest registers",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H0": {
+                    "description": "H0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HR1": {
+              "description": "digest registers",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H1": {
+                    "description": "H1",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HR2": {
+              "description": "digest registers",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H2": {
+                    "description": "H2",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HR3": {
+              "description": "digest registers",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H3": {
+                    "description": "H3",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HR4": {
+              "description": "digest registers",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H4": {
+                    "description": "H4",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IMR": {
+              "description": "interrupt enable register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCIE": {
+                    "description": "Digest calculation completion interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DINIE": {
+                    "description": "Data input interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUSY": {
+                    "description": "Busy bit",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DMAS": {
+                    "description": "DMA Status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DCIS": {
+                    "description": "Digest calculation completion interrupt\n              status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DINIS": {
+                    "description": "Data input interrupt\n              status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CSR0": {
+              "description": "context swap registers",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR0": {
+                    "description": "CSR0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR1": {
+              "description": "context swap registers",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR1": {
+                    "description": "CSR1",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR2": {
+              "description": "context swap registers",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR2": {
+                    "description": "CSR2",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR3": {
+              "description": "context swap registers",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR3": {
+                    "description": "CSR3",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR4": {
+              "description": "context swap registers",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR4": {
+                    "description": "CSR4",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR5": {
+              "description": "context swap registers",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR5": {
+                    "description": "CSR5",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR6": {
+              "description": "context swap registers",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR6": {
+                    "description": "CSR6",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR7": {
+              "description": "context swap registers",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR7": {
+                    "description": "CSR7",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR8": {
+              "description": "context swap registers",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR8": {
+                    "description": "CSR8",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR9": {
+              "description": "context swap registers",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR9": {
+                    "description": "CSR9",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR10": {
+              "description": "context swap registers",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR10": {
+                    "description": "CSR10",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR11": {
+              "description": "context swap registers",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR11": {
+                    "description": "CSR11",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR12": {
+              "description": "context swap registers",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR12": {
+                    "description": "CSR12",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR13": {
+              "description": "context swap registers",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR13": {
+                    "description": "CSR13",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR14": {
+              "description": "context swap registers",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR14": {
+                    "description": "CSR14",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR15": {
+              "description": "context swap registers",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR15": {
+                    "description": "CSR15",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR16": {
+              "description": "context swap registers",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR16": {
+                    "description": "CSR16",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR17": {
+              "description": "context swap registers",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR17": {
+                    "description": "CSR17",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR18": {
+              "description": "context swap registers",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR18": {
+                    "description": "CSR18",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR19": {
+              "description": "context swap registers",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR19": {
+                    "description": "CSR19",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR20": {
+              "description": "context swap registers",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR20": {
+                    "description": "CSR20",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR21": {
+              "description": "context swap registers",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR21": {
+                    "description": "CSR21",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR22": {
+              "description": "context swap registers",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR22": {
+                    "description": "CSR22",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR23": {
+              "description": "context swap registers",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR23": {
+                    "description": "CSR23",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR24": {
+              "description": "context swap registers",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR24": {
+                    "description": "CSR24",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR25": {
+              "description": "context swap registers",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR25": {
+                    "description": "CSR25",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR26": {
+              "description": "context swap registers",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR26": {
+                    "description": "CSR26",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR27": {
+              "description": "context swap registers",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR27": {
+                    "description": "CSR27",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR28": {
+              "description": "context swap registers",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR28": {
+                    "description": "CSR28",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR29": {
+              "description": "context swap registers",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR29": {
+                    "description": "CSR29",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR30": {
+              "description": "context swap registers",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR30": {
+                    "description": "CSR30",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR31": {
+              "description": "context swap registers",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR31": {
+                    "description": "CSR31",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR32": {
+              "description": "context swap registers",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR32": {
+                    "description": "CSR32",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR33": {
+              "description": "context swap registers",
+              "offset": 380,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR33": {
+                    "description": "CSR33",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR34": {
+              "description": "context swap registers",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR34": {
+                    "description": "CSR34",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR35": {
+              "description": "context swap registers",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR35": {
+                    "description": "CSR35",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR36": {
+              "description": "context swap registers",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR36": {
+                    "description": "CSR36",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR37": {
+              "description": "context swap registers",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR37": {
+                    "description": "CSR37",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR38": {
+              "description": "context swap registers",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR38": {
+                    "description": "CSR38",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR39": {
+              "description": "context swap registers",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR39": {
+                    "description": "CSR39",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR40": {
+              "description": "context swap registers",
+              "offset": 408,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR40": {
+                    "description": "CSR40",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR41": {
+              "description": "context swap registers",
+              "offset": 412,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR41": {
+                    "description": "CSR41",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR42": {
+              "description": "context swap registers",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR42": {
+                    "description": "CSR42",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR43": {
+              "description": "context swap registers",
+              "offset": 420,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR43": {
+                    "description": "CSR43",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR44": {
+              "description": "context swap registers",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR44": {
+                    "description": "CSR44",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR45": {
+              "description": "context swap registers",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR45": {
+                    "description": "CSR45",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR46": {
+              "description": "context swap registers",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR46": {
+                    "description": "CSR46",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR47": {
+              "description": "context swap registers",
+              "offset": 436,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR47": {
+                    "description": "CSR47",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR48": {
+              "description": "context swap registers",
+              "offset": 440,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR48": {
+                    "description": "CSR48",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR49": {
+              "description": "context swap registers",
+              "offset": 444,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR49": {
+                    "description": "CSR49",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR50": {
+              "description": "context swap registers",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR50": {
+                    "description": "CSR50",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR51": {
+              "description": "context swap registers",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR51": {
+                    "description": "CSR51",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR52": {
+              "description": "context swap registers",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR52": {
+                    "description": "CSR52",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR53": {
+              "description": "context swap registers",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR53": {
+                    "description": "CSR53",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR0": {
+              "description": "HASH digest register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H0": {
+                    "description": "H0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR1": {
+              "description": "read-only",
+              "offset": 788,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H1": {
+                    "description": "H1",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR2": {
+              "description": "read-only",
+              "offset": 792,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H2": {
+                    "description": "H2",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR3": {
+              "description": "read-only",
+              "offset": 796,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H3": {
+                    "description": "H3",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR4": {
+              "description": "read-only",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H4": {
+                    "description": "H4",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR5": {
+              "description": "read-only",
+              "offset": 804,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H5": {
+                    "description": "H5",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR6": {
+              "description": "read-only",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H6": {
+                    "description": "H6",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR7": {
+              "description": "read-only",
+              "offset": 812,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H7": {
+                    "description": "H7",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOB": {
+        "description": "General-purpose I/Os",
+        "children": {
+          "registers": {
+            "MODER": {
+              "description": "GPIO port mode register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 640,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODER15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MODER14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "MODER13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MODER12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "MODER11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MODER10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "MODER9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MODER8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "MODER7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MODER6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MODER5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MODER4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MODER3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MODER2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MODER1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODER0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTYPER": {
+              "description": "GPIO port output type register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OT15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OT14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OT13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OT12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OT11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OT10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OT9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OT8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OT7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OT6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OT5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OT4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OT3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OT2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OT1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OT0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OSPEEDR": {
+              "description": "GPIO port output speed\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OSPEEDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "OSPEEDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "OSPEEDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "OSPEEDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "OSPEEDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "OSPEEDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "OSPEEDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "OSPEEDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "OSPEEDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "OSPEEDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "OSPEEDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "OSPEEDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSPEEDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "OSPEEDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "OSPEEDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "OSPEEDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PUPDR": {
+              "description": "GPIO port pull-up/pull-down\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 256,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PUPDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "PUPDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "PUPDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "PUPDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "PUPDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "PUPDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "PUPDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "PUPDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PUPDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "PUPDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PUPDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PUPDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PUPDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PUPDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PUPDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "PUPDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "GPIO port input data register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDR15": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IDR14": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "IDR13": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "IDR12": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IDR11": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IDR10": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IDR9": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IDR8": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IDR7": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IDR6": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IDR5": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDR4": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDR3": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IDR2": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDR1": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IDR0": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ODR": {
+              "description": "GPIO port output data register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ODR15": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ODR14": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ODR13": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ODR12": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ODR11": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ODR10": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ODR9": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODR8": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ODR7": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ODR6": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ODR5": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ODR4": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ODR3": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ODR2": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ODR1": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ODR0": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BSRR": {
+              "description": "GPIO port bit set/reset\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BR15": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BR0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BS15": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BS14": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BS13": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BS12": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BS11": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BS10": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BS9": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BS8": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BS7": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BS6": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BS5": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BS4": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BS3": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BS2": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BS1": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BS0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LCKR": {
+              "description": "GPIO port configuration lock\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LCKK": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "LCK15": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LCK14": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "LCK13": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LCK12": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LCK11": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LCK10": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LCK9": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LCK8": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LCK7": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCK6": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LCK5": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LCK4": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "LCK3": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LCK2": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LCK1": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LCK0": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AFRL": {
+              "description": "GPIO alternate function low\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRL7": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRL6": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRL5": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRL4": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRL3": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRL2": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRL1": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRL0": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "AFRH": {
+              "description": "GPIO alternate function high\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRH15": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRH14": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRH13": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRH12": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRH11": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRH10": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRH9": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRH8": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOA": {
+        "description": "General-purpose I/Os",
+        "children": {
+          "registers": {
+            "MODER": {
+              "description": "GPIO port mode register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2818572288,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODER15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MODER14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "MODER13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MODER12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "MODER11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MODER10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "MODER9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MODER8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "MODER7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MODER6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MODER5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MODER4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MODER3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MODER2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MODER1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODER0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTYPER": {
+              "description": "GPIO port output type register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OT15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OT14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OT13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OT12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OT11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OT10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OT9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OT8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OT7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OT6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OT5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OT4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OT3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OT2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OT1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OT0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OSPEEDR": {
+              "description": "GPIO port output speed\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OSPEEDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "OSPEEDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "OSPEEDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "OSPEEDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "OSPEEDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "OSPEEDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "OSPEEDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "OSPEEDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "OSPEEDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "OSPEEDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "OSPEEDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "OSPEEDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSPEEDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "OSPEEDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "OSPEEDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "OSPEEDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PUPDR": {
+              "description": "GPIO port pull-up/pull-down\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 1677721600,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PUPDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "PUPDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "PUPDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "PUPDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "PUPDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "PUPDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "PUPDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "PUPDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PUPDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "PUPDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PUPDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PUPDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PUPDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PUPDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PUPDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "PUPDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "GPIO port input data register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDR15": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IDR14": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "IDR13": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "IDR12": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IDR11": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IDR10": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IDR9": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IDR8": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IDR7": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IDR6": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IDR5": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDR4": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDR3": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IDR2": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDR1": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IDR0": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ODR": {
+              "description": "GPIO port output data register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ODR15": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ODR14": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ODR13": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ODR12": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ODR11": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ODR10": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ODR9": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODR8": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ODR7": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ODR6": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ODR5": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ODR4": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ODR3": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ODR2": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ODR1": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ODR0": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BSRR": {
+              "description": "GPIO port bit set/reset\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BR15": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BR0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BS15": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BS14": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BS13": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BS12": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BS11": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BS10": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BS9": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BS8": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BS7": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BS6": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BS5": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BS4": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BS3": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BS2": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BS1": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BS0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LCKR": {
+              "description": "GPIO port configuration lock\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LCKK": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "LCK15": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LCK14": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "LCK13": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LCK12": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LCK11": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LCK10": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LCK9": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LCK8": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LCK7": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCK6": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LCK5": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LCK4": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "LCK3": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LCK2": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LCK1": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LCK0": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AFRL": {
+              "description": "GPIO alternate function low\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRL7": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRL6": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRL5": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRL4": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRL3": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRL2": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRL1": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRL0": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "AFRH": {
+              "description": "GPIO alternate function high\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRH15": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRH14": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRH13": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRH12": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRH11": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRH10": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRH9": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRH8": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SYSCFG": {
+        "description": "System configuration controller",
+        "children": {
+          "registers": {
+            "MEMRM": {
+              "description": "memory remap register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_MODE": {
+                    "description": "MEM_MODE",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PMC": {
+              "description": "peripheral mode configuration\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MII_RMII_SEL": {
+                    "description": "Ethernet PHY interface\n              selection",
+                    "offset": 23,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EXTICR1": {
+              "description": "external interrupt configuration register\n          1",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI3": {
+                    "description": "EXTI x configuration (x = 0 to\n              3)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI2": {
+                    "description": "EXTI x configuration (x = 0 to\n              3)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI1": {
+                    "description": "EXTI x configuration (x = 0 to\n              3)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI0": {
+                    "description": "EXTI x configuration (x = 0 to\n              3)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTICR2": {
+              "description": "external interrupt configuration register\n          2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI7": {
+                    "description": "EXTI x configuration (x = 4 to\n              7)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI6": {
+                    "description": "EXTI x configuration (x = 4 to\n              7)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI5": {
+                    "description": "EXTI x configuration (x = 4 to\n              7)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI4": {
+                    "description": "EXTI x configuration (x = 4 to\n              7)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTICR3": {
+              "description": "external interrupt configuration register\n          3",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI11": {
+                    "description": "EXTI x configuration (x = 8 to\n              11)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI10": {
+                    "description": "EXTI10",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI9": {
+                    "description": "EXTI x configuration (x = 8 to\n              11)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI8": {
+                    "description": "EXTI x configuration (x = 8 to\n              11)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTICR4": {
+              "description": "external interrupt configuration register\n          4",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI15": {
+                    "description": "EXTI x configuration (x = 12 to\n              15)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI14": {
+                    "description": "EXTI x configuration (x = 12 to\n              15)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI13": {
+                    "description": "EXTI x configuration (x = 12 to\n              15)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI12": {
+                    "description": "EXTI x configuration (x = 12 to\n              15)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CMPCR": {
+              "description": "Compensation cell control\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "READY",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CMP_PD": {
+                    "description": "Compensation cell\n              power-down",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI1": {
+        "description": "Serial peripheral interface",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BIDIMODE": {
+                    "description": "Bidirectional data mode\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BIDIOE": {
+                    "description": "Output enable in bidirectional\n              mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CRCEN": {
+                    "description": "Hardware CRC calculation\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CRCNEXT": {
+                    "description": "CRC transfer next",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DFF": {
+                    "description": "Data frame format",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RXONLY": {
+                    "description": "Receive only",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SSM": {
+                    "description": "Software slave management",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SSI": {
+                    "description": "Internal slave select",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LSBFIRST": {
+                    "description": "Frame format",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SPE": {
+                    "description": "SPI enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BR": {
+                    "description": "Baud rate control",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "MSTR": {
+                    "description": "Master selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CPOL": {
+                    "description": "Clock polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CPHA": {
+                    "description": "Clock phase",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXEIE": {
+                    "description": "Tx buffer empty interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RX buffer not empty interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FRF": {
+                    "description": "Frame format",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SSOE": {
+                    "description": "SS output enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXDMAEN": {
+                    "description": "Tx buffer DMA enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXDMAEN": {
+                    "description": "Rx buffer DMA enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIFRFE": {
+                    "description": "TI frame format error",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BSY": {
+                    "description": "Busy flag",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVR": {
+                    "description": "Overrun flag",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MODF": {
+                    "description": "Mode fault",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRCERR": {
+                    "description": "CRC error flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "UDR": {
+                    "description": "Underrun flag",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CHSIDE": {
+                    "description": "Channel side",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXE": {
+                    "description": "Transmit buffer empty",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXNE": {
+                    "description": "Receive buffer not empty",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "data register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CRCPR": {
+              "description": "CRC polynomial register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRCPOLY": {
+                    "description": "CRC polynomial register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RXCRCR": {
+              "description": "RX CRC register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RxCRC": {
+                    "description": "Rx CRC register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TXCRCR": {
+              "description": "TX CRC register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TxCRC": {
+                    "description": "Tx CRC register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "I2SCFGR": {
+              "description": "I2S configuration register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "I2SMOD": {
+                    "description": "I2S mode selection",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "I2SE": {
+                    "description": "I2S Enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "I2SCFG": {
+                    "description": "I2S configuration mode",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PCMSYNC": {
+                    "description": "PCM frame synchronization",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "I2SSTD": {
+                    "description": "I2S standard selection",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CKPOL": {
+                    "description": "Steady state clock\n              polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DATLEN": {
+                    "description": "Data length to be\n              transferred",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "CHLEN": {
+                    "description": "Channel length (number of bits per audio\n              channel)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "I2SPR": {
+              "description": "I2S prescaler register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 10,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCKOE": {
+                    "description": "Master clock output enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODD": {
+                    "description": "Odd factor for the\n              prescaler",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "I2SDIV": {
+                    "description": "I2S Linear prescaler",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "LTDC": {
+        "description": "LCD-TFT Controller",
+        "children": {
+          "registers": {
+            "SSCR": {
+              "description": "Synchronization Size Configuration\n          Register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HSW": {
+                    "description": "Horizontal Synchronization Width (in\n              units of pixel clock period)",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "VSH": {
+                    "description": "Vertical Synchronization Height (in\n              units of horizontal scan line)",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "BPCR": {
+              "description": "Back Porch Configuration\n          Register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AHBP": {
+                    "description": "Accumulated Horizontal back porch (in\n              units of pixel clock period)",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "AVBP": {
+                    "description": "Accumulated Vertical back porch (in\n              units of horizontal scan line)",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "AWCR": {
+              "description": "Active Width Configuration\n          Register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AAV": {
+                    "description": "AAV",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "AAH": {
+                    "description": "Accumulated Active Height (in units of\n              horizontal scan line)",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "TWCR": {
+              "description": "Total Width Configuration\n          Register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TOTALW": {
+                    "description": "Total Width (in units of pixel clock\n              period)",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "TOTALH": {
+                    "description": "Total Height (in units of horizontal\n              scan line)",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "GCR": {
+              "description": "Global Control Register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 8736,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HSPOL": {
+                    "description": "Horizontal Synchronization\n              Polarity",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "VSPOL": {
+                    "description": "Vertical Synchronization\n              Polarity",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DEPOL": {
+                    "description": "Data Enable Polarity",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "PCPOL": {
+                    "description": "Pixel Clock Polarity",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DEN": {
+                    "description": "Dither Enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DRW": {
+                    "description": "Dither Red Width",
+                    "offset": 12,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DGW": {
+                    "description": "Dither Green Width",
+                    "offset": 8,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DBW": {
+                    "description": "Dither Blue Width",
+                    "offset": 4,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "LTDCEN": {
+                    "description": "LCD-TFT controller enable\n              bit",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SRCR": {
+              "description": "Shadow Reload Configuration\n          Register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VBR": {
+                    "description": "Vertical Blanking Reload",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IMR": {
+                    "description": "Immediate Reload",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BCCR": {
+              "description": "Background Color Configuration\n          Register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BC": {
+                    "description": "Background Color Red value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "Interrupt Enable Register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RRIE": {
+                    "description": "Register Reload interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TERRIE": {
+                    "description": "Transfer Error Interrupt\n              Enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FUIE": {
+                    "description": "FIFO Underrun Interrupt\n              Enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LIE": {
+                    "description": "Line Interrupt Enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ISR": {
+              "description": "Interrupt Status Register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RRIF": {
+                    "description": "Register Reload Interrupt\n              Flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TERRIF": {
+                    "description": "Transfer Error interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FUIF": {
+                    "description": "FIFO Underrun Interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LIF": {
+                    "description": "Line Interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "Interrupt Clear Register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CRRIF": {
+                    "description": "Clears Register Reload Interrupt\n              Flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CTERRIF": {
+                    "description": "Clears the Transfer Error Interrupt\n              Flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CFUIF": {
+                    "description": "Clears the FIFO Underrun Interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CLIF": {
+                    "description": "Clears the Line Interrupt\n              Flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LIPCR": {
+              "description": "Line Interrupt Position Configuration\n          Register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LIPOS": {
+                    "description": "Line Interrupt Position",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "CPSR": {
+              "description": "Current Position Status\n          Register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CXPOS": {
+                    "description": "Current X Position",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CYPOS": {
+                    "description": "Current Y Position",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CDSR": {
+              "description": "Current Display Status\n          Register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 15,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HSYNCS": {
+                    "description": "Horizontal Synchronization display\n              Status",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "VSYNCS": {
+                    "description": "Vertical Synchronization display\n              Status",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "HDES": {
+                    "description": "Horizontal Data Enable display\n              Status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VDES": {
+                    "description": "Vertical Data Enable display\n              Status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "L1CR": {
+              "description": "Layerx Control Register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLUTEN": {
+                    "description": "Color Look-Up Table Enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "COLKEN": {
+                    "description": "Color Keying Enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LEN": {
+                    "description": "Layer Enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "L1WHPCR": {
+              "description": "Layerx Window Horizontal Position\n          Configuration Register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WHSPPOS": {
+                    "description": "Window Horizontal Stop\n              Position",
+                    "offset": 16,
+                    "size": 12
+                  },
+                  "WHSTPOS": {
+                    "description": "Window Horizontal Start\n              Position",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "L1WVPCR": {
+              "description": "Layerx Window Vertical Position\n          Configuration Register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WVSPPOS": {
+                    "description": "Window Vertical Stop\n              Position",
+                    "offset": 16,
+                    "size": 11
+                  },
+                  "WVSTPOS": {
+                    "description": "Window Vertical Start\n              Position",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "L1CKCR": {
+              "description": "Layerx Color Keying Configuration\n          Register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKRED": {
+                    "description": "Color Key Red value",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "CKGREEN": {
+                    "description": "Color Key Green value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "CKBLUE": {
+                    "description": "Color Key Blue value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L1PFCR": {
+              "description": "Layerx Pixel Format Configuration\n          Register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PF": {
+                    "description": "Pixel Format",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "L1CACR": {
+              "description": "Layerx Constant Alpha Configuration\n          Register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONSTA": {
+                    "description": "Constant Alpha",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L1DCCR": {
+              "description": "Layerx Default Color Configuration\n          Register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCALPHA": {
+                    "description": "Default Color Alpha",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DCRED": {
+                    "description": "Default Color Red",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DCGREEN": {
+                    "description": "Default Color Green",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DCBLUE": {
+                    "description": "Default Color Blue",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L1BFCR": {
+              "description": "Layerx Blending Factors Configuration\n          Register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 1543,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BF1": {
+                    "description": "Blending Factor 1",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "BF2": {
+                    "description": "Blending Factor 2",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "L1CFBAR": {
+              "description": "Layerx Color Frame Buffer Address\n          Register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBADD": {
+                    "description": "Color Frame Buffer Start\n              Address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "L1CFBLR": {
+              "description": "Layerx Color Frame Buffer Length\n          Register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBP": {
+                    "description": "Color Frame Buffer Pitch in\n              bytes",
+                    "offset": 16,
+                    "size": 13
+                  },
+                  "CFBLL": {
+                    "description": "Color Frame Buffer Line\n              Length",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "L1CFBLNR": {
+              "description": "Layerx ColorFrame Buffer Line Number\n          Register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBLNBR": {
+                    "description": "Frame Buffer Line Number",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "L1CLUTWR": {
+              "description": "Layerx CLUT Write Register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CLUTADD": {
+                    "description": "CLUT Address",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "RED": {
+                    "description": "Red value",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "GREEN": {
+                    "description": "Green value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BLUE": {
+                    "description": "Blue value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L2CR": {
+              "description": "Layerx Control Register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLUTEN": {
+                    "description": "Color Look-Up Table Enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "COLKEN": {
+                    "description": "Color Keying Enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LEN": {
+                    "description": "Layer Enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "L2WHPCR": {
+              "description": "Layerx Window Horizontal Position\n          Configuration Register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WHSPPOS": {
+                    "description": "Window Horizontal Stop\n              Position",
+                    "offset": 16,
+                    "size": 12
+                  },
+                  "WHSTPOS": {
+                    "description": "Window Horizontal Start\n              Position",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "L2WVPCR": {
+              "description": "Layerx Window Vertical Position\n          Configuration Register",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WVSPPOS": {
+                    "description": "Window Vertical Stop\n              Position",
+                    "offset": 16,
+                    "size": 11
+                  },
+                  "WVSTPOS": {
+                    "description": "Window Vertical Start\n              Position",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "L2CKCR": {
+              "description": "Layerx Color Keying Configuration\n          Register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKRED": {
+                    "description": "Color Key Red value",
+                    "offset": 15,
+                    "size": 9
+                  },
+                  "CKGREEN": {
+                    "description": "Color Key Green value",
+                    "offset": 8,
+                    "size": 7
+                  },
+                  "CKBLUE": {
+                    "description": "Color Key Blue value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L2PFCR": {
+              "description": "Layerx Pixel Format Configuration\n          Register",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PF": {
+                    "description": "Pixel Format",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "L2CACR": {
+              "description": "Layerx Constant Alpha Configuration\n          Register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONSTA": {
+                    "description": "Constant Alpha",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L2DCCR": {
+              "description": "Layerx Default Color Configuration\n          Register",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCALPHA": {
+                    "description": "Default Color Alpha",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DCRED": {
+                    "description": "Default Color Red",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DCGREEN": {
+                    "description": "Default Color Green",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DCBLUE": {
+                    "description": "Default Color Blue",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L2BFCR": {
+              "description": "Layerx Blending Factors Configuration\n          Register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 1543,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BF1": {
+                    "description": "Blending Factor 1",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "BF2": {
+                    "description": "Blending Factor 2",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "L2CFBAR": {
+              "description": "Layerx Color Frame Buffer Address\n          Register",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBADD": {
+                    "description": "Color Frame Buffer Start\n              Address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "L2CFBLR": {
+              "description": "Layerx Color Frame Buffer Length\n          Register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBP": {
+                    "description": "Color Frame Buffer Pitch in\n              bytes",
+                    "offset": 16,
+                    "size": 13
+                  },
+                  "CFBLL": {
+                    "description": "Color Frame Buffer Line\n              Length",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "L2CFBLNR": {
+              "description": "Layerx ColorFrame Buffer Line Number\n          Register",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBLNBR": {
+                    "description": "Frame Buffer Line Number",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "L2CLUTWR": {
+              "description": "Layerx CLUT Write Register",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CLUTADD": {
+                    "description": "CLUT Address",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "RED": {
+                    "description": "Red value",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "GREEN": {
+                    "description": "Green value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BLUE": {
+                    "description": "Blue value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SAI1": {
+        "description": "Serial audio interface",
+        "children": {
+          "registers": {
+            "SAI_ACR1": {
+              "description": "SAI AConfiguration register 1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCKDIV": {
+                    "description": "Master clock divider",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "MODE": {
+                    "description": "Audio block mode",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "PRTCFG": {
+                    "description": "Protocol configuration",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DS": {
+                    "description": "Data size",
+                    "offset": 5,
+                    "size": 3
+                  },
+                  "LSBFIRST": {
+                    "description": "Least significant bit\n              first",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CKSTR": {
+                    "description": "Clock strobing edge",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SYNCEN": {
+                    "description": "Synchronization enable",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MONO": {
+                    "description": "Mono mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OUTDRIV": {
+                    "description": "Output drive",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SAIAEN": {
+                    "description": "Audio block enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DMAEN": {
+                    "description": "DMA enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "NODIV": {
+                    "description": "No divider",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SAI_BCR1": {
+              "description": "SAI BConfiguration register 1",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Audio block mode",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "PRTCFG": {
+                    "description": "Protocol configuration",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DS": {
+                    "description": "Data size",
+                    "offset": 5,
+                    "size": 3
+                  },
+                  "LSBFIRST": {
+                    "description": "Least significant bit\n              first",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CKSTR": {
+                    "description": "Clock strobing edge",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SYNCEN": {
+                    "description": "Synchronization enable",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MONO": {
+                    "description": "Mono mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OUTDRIV": {
+                    "description": "Output drive",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SAIBEN": {
+                    "description": "Audio block enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DMAEN": {
+                    "description": "DMA enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "NODIV": {
+                    "description": "No divider",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "MCKDIV": {
+                    "description": "Master clock divider",
+                    "offset": 20,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SAI_ACR2": {
+              "description": "SAI AConfiguration register 2",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FTH": {
+                    "description": "FIFO threshold",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "FFLUSH": {
+                    "description": "FIFO flush",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TRIS": {
+                    "description": "Tristate management on data\n              line",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MUTE": {
+                    "description": "Mute",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MUTEVAL": {
+                    "description": "Mute value",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MUTECNT": {
+                    "description": "Mute counter",
+                    "offset": 7,
+                    "size": 6
+                  },
+                  "CPL": {
+                    "description": "Complement bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "COMP": {
+                    "description": "Companding mode",
+                    "offset": 14,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "SAI_BCR2": {
+              "description": "SAI BConfiguration register 2",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FTH": {
+                    "description": "FIFO threshold",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "FFLUSH": {
+                    "description": "FIFO flush",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TRIS": {
+                    "description": "Tristate management on data\n              line",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MUTE": {
+                    "description": "Mute",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MUTEVAL": {
+                    "description": "Mute value",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MUTECNT": {
+                    "description": "Mute counter",
+                    "offset": 7,
+                    "size": 6
+                  },
+                  "CPL": {
+                    "description": "Complement bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "COMP": {
+                    "description": "Companding mode",
+                    "offset": 14,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "SAI_AFRCR": {
+              "description": "SAI AFrame configuration\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRL": {
+                    "description": "Frame length",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "FSALL": {
+                    "description": "Frame synchronization active level\n              length",
+                    "offset": 8,
+                    "size": 7
+                  },
+                  "FSDEF": {
+                    "description": "Frame synchronization\n              definition",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FSPOL": {
+                    "description": "Frame synchronization\n              polarity",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FSOFF": {
+                    "description": "Frame synchronization\n              offset",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SAI_BFRCR": {
+              "description": "SAI BFrame configuration\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRL": {
+                    "description": "Frame length",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "FSALL": {
+                    "description": "Frame synchronization active level\n              length",
+                    "offset": 8,
+                    "size": 7
+                  },
+                  "FSDEF": {
+                    "description": "Frame synchronization\n              definition",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FSPOL": {
+                    "description": "Frame synchronization\n              polarity",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FSOFF": {
+                    "description": "Frame synchronization\n              offset",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SAI_ASLOTR": {
+              "description": "SAI ASlot register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FBOFF": {
+                    "description": "First bit offset",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "SLOTSZ": {
+                    "description": "Slot size",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "NBSLOT": {
+                    "description": "Number of slots in an audio\n              frame",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "SLOTEN": {
+                    "description": "Slot enable",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SAI_BSLOTR": {
+              "description": "SAI BSlot register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FBOFF": {
+                    "description": "First bit offset",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "SLOTSZ": {
+                    "description": "Slot size",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "NBSLOT": {
+                    "description": "Number of slots in an audio\n              frame",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "SLOTEN": {
+                    "description": "Slot enable",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SAI_AIM": {
+              "description": "SAI AInterrupt mask register2",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVRUDRIE": {
+                    "description": "Overrun/underrun interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MUTEDETIE": {
+                    "description": "Mute detection interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WCKCFGIE": {
+                    "description": "Wrong clock configuration interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FREQIE": {
+                    "description": "FIFO request interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CNRDYIE": {
+                    "description": "Codec not ready interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "AFSDETIE": {
+                    "description": "Anticipated frame synchronization\n              detection interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LFSDETIE": {
+                    "description": "Late frame synchronization detection\n              interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SAI_BIM": {
+              "description": "SAI BInterrupt mask register2",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVRUDRIE": {
+                    "description": "Overrun/underrun interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MUTEDETIE": {
+                    "description": "Mute detection interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WCKCFGIE": {
+                    "description": "Wrong clock configuration interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FREQIE": {
+                    "description": "FIFO request interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CNRDYIE": {
+                    "description": "Codec not ready interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "AFSDETIE": {
+                    "description": "Anticipated frame synchronization\n              detection interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LFSDETIE": {
+                    "description": "Late frame synchronization detection\n              interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SAI_ASR": {
+              "description": "SAI AStatus register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "OVRUDR": {
+                    "description": "Overrun / underrun",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MUTEDET": {
+                    "description": "Mute detection",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WCKCFG": {
+                    "description": "Wrong clock configuration\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FREQ": {
+                    "description": "FIFO request",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CNRDY": {
+                    "description": "Codec not ready",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "AFSDET": {
+                    "description": "Anticipated frame synchronization\n              detection",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LFSDET": {
+                    "description": "Late frame synchronization\n              detection",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FLTH": {
+                    "description": "FIFO level threshold",
+                    "offset": 16,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "SAI_BSR": {
+              "description": "SAI BStatus register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "OVRUDR": {
+                    "description": "Overrun / underrun",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MUTEDET": {
+                    "description": "Mute detection",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WCKCFG": {
+                    "description": "Wrong clock configuration\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FREQ": {
+                    "description": "FIFO request",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CNRDY": {
+                    "description": "Codec not ready",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "AFSDET": {
+                    "description": "Anticipated frame synchronization\n              detection",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LFSDET": {
+                    "description": "Late frame synchronization\n              detection",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FLTH": {
+                    "description": "FIFO level threshold",
+                    "offset": 16,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "SAI_ACLRFR": {
+              "description": "SAI AClear flag register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COVRUDR": {
+                    "description": "Clear overrun / underrun",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CMUTEDET": {
+                    "description": "Mute detection flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CWCKCFG": {
+                    "description": "Clear wrong clock configuration\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CCNRDY": {
+                    "description": "Clear codec not ready flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CAFSDET": {
+                    "description": "Clear anticipated frame synchronization\n              detection flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CLFSDET": {
+                    "description": "Clear late frame synchronization\n              detection flag",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SAI_BCLRFR": {
+              "description": "SAI BClear flag register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COVRUDR": {
+                    "description": "Clear overrun / underrun",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CMUTEDET": {
+                    "description": "Mute detection flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CWCKCFG": {
+                    "description": "Clear wrong clock configuration\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CCNRDY": {
+                    "description": "Clear codec not ready flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CAFSDET": {
+                    "description": "Clear anticipated frame synchronization\n              detection flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CLFSDET": {
+                    "description": "Clear late frame synchronization\n              detection flag",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SAI_ADR": {
+              "description": "SAI AData register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Data",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SAI_BDR": {
+              "description": "SAI BData register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Data",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NVIC": {
+        "description": "Nested Vectored Interrupt\n      Controller",
+        "children": {
+          "registers": {
+            "ISER0": {
+              "description": "Interrupt Set-Enable Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "SETENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISER1": {
+              "description": "Interrupt Set-Enable Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "SETENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISER2": {
+              "description": "Interrupt Set-Enable Register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "SETENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICER0": {
+              "description": "Interrupt Clear-Enable\n          Register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "CLRENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICER1": {
+              "description": "Interrupt Clear-Enable\n          Register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "CLRENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICER2": {
+              "description": "Interrupt Clear-Enable\n          Register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "CLRENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISPR0": {
+              "description": "Interrupt Set-Pending Register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "SETPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISPR1": {
+              "description": "Interrupt Set-Pending Register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "SETPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISPR2": {
+              "description": "Interrupt Set-Pending Register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "SETPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICPR0": {
+              "description": "Interrupt Clear-Pending\n          Register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "CLRPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICPR1": {
+              "description": "Interrupt Clear-Pending\n          Register",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "CLRPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICPR2": {
+              "description": "Interrupt Clear-Pending\n          Register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "CLRPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IABR0": {
+              "description": "Interrupt Active Bit Register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACTIVE": {
+                    "description": "ACTIVE",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IABR1": {
+              "description": "Interrupt Active Bit Register",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACTIVE": {
+                    "description": "ACTIVE",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IABR2": {
+              "description": "Interrupt Active Bit Register",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACTIVE": {
+                    "description": "ACTIVE",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IPR0": {
+              "description": "Interrupt Priority Register",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR1": {
+              "description": "Interrupt Priority Register",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR2": {
+              "description": "Interrupt Priority Register",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR3": {
+              "description": "Interrupt Priority Register",
+              "offset": 780,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR4": {
+              "description": "Interrupt Priority Register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR5": {
+              "description": "Interrupt Priority Register",
+              "offset": 788,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR6": {
+              "description": "Interrupt Priority Register",
+              "offset": 792,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR7": {
+              "description": "Interrupt Priority Register",
+              "offset": 796,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR8": {
+              "description": "Interrupt Priority Register",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR9": {
+              "description": "Interrupt Priority Register",
+              "offset": 804,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR10": {
+              "description": "Interrupt Priority Register",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR11": {
+              "description": "Interrupt Priority Register",
+              "offset": 812,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR12": {
+              "description": "Interrupt Priority Register",
+              "offset": 816,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR13": {
+              "description": "Interrupt Priority Register",
+              "offset": 820,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR14": {
+              "description": "Interrupt Priority Register",
+              "offset": 824,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR15": {
+              "description": "Interrupt Priority Register",
+              "offset": 828,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR16": {
+              "description": "Interrupt Priority Register",
+              "offset": 832,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR17": {
+              "description": "Interrupt Priority Register",
+              "offset": 836,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR18": {
+              "description": "Interrupt Priority Register",
+              "offset": 840,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR19": {
+              "description": "Interrupt Priority Register",
+              "offset": 844,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_HS_PWRCLK": {
+        "description": "USB on the go high speed",
+        "children": {
+          "registers": {
+            "OTG_HS_PCGCR": {
+              "description": "Power and clock gating control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STPPCLK": {
+                    "description": "Stop PHY clock",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "GATEHCLK": {
+                    "description": "Gate HCLK",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PHYSUSP": {
+                    "description": "PHY suspended",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_HS_DEVICE": {
+        "description": "USB on the go high speed",
+        "children": {
+          "registers": {
+            "OTG_HS_DCFG": {
+              "description": "OTG_HS device configuration\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 35651584,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DSPD": {
+                    "description": "Device speed",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "NZLSOHSK": {
+                    "description": "Nonzero-length status OUT\n              handshake",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 4,
+                    "size": 7
+                  },
+                  "PFIVL": {
+                    "description": "Periodic (micro)frame\n              interval",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "PERSCHIVL": {
+                    "description": "Periodic scheduling\n              interval",
+                    "offset": 24,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DCTL": {
+              "description": "OTG_HS device control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWUSIG": {
+                    "description": "Remote wakeup signaling",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SDIS": {
+                    "description": "Soft disconnect",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GINSTS": {
+                    "description": "Global IN NAK status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GONSTS": {
+                    "description": "Global OUT NAK status",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TCTL": {
+                    "description": "Test control",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SGINAK": {
+                    "description": "Set global IN NAK",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CGINAK": {
+                    "description": "Clear global IN NAK",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SGONAK": {
+                    "description": "Set global OUT NAK",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CGONAK": {
+                    "description": "Clear global OUT NAK",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "POPRGDNE": {
+                    "description": "Power-on programming done",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DSTS": {
+              "description": "OTG_HS device status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SUSPSTS": {
+                    "description": "Suspend status",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ENUMSPD": {
+                    "description": "Enumerated speed",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "EERR": {
+                    "description": "Erratic error",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FNSOF": {
+                    "description": "Frame number of the received\n              SOF",
+                    "offset": 8,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPMSK": {
+              "description": "OTG_HS device IN endpoint common interrupt\n          mask register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOM": {
+                    "description": "Timeout condition mask (nonisochronous\n              endpoints)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFEMSK": {
+                    "description": "IN token received when TxFIFO empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNMM": {
+                    "description": "IN token received with EP mismatch\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INEPNEM": {
+                    "description": "IN endpoint NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFURM": {
+                    "description": "FIFO underrun mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BIM": {
+                    "description": "BNA interrupt mask",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPMSK": {
+              "description": "OTG_HS device OUT endpoint common interrupt\n          mask register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUPM": {
+                    "description": "SETUP phase done mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDM": {
+                    "description": "OUT token received when endpoint\n              disabled mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets received\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OPEM": {
+                    "description": "OUT packet error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BOIM": {
+                    "description": "BNA interrupt mask",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DAINT": {
+              "description": "OTG_HS device all endpoints interrupt\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IEPINT": {
+                    "description": "IN endpoint interrupt bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt\n              bits",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DAINTMSK": {
+              "description": "OTG_HS all endpoints interrupt mask\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEPM": {
+                    "description": "IN EP interrupt mask bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OEPM": {
+                    "description": "OUT EP interrupt mask bits",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DVBUSDIS": {
+              "description": "OTG_HS device VBUS discharge time\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 6103,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VBUSDT": {
+                    "description": "Device VBUS discharge time",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DVBUSPULSE": {
+              "description": "OTG_HS device VBUS pulsing time\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 1464,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DVBUSP": {
+                    "description": "Device VBUS pulsing time",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTHRCTL": {
+              "description": "OTG_HS Device threshold control\n          register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NONISOTHREN": {
+                    "description": "Nonisochronous IN endpoints threshold\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ISOTHREN": {
+                    "description": "ISO IN endpoint threshold\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXTHRLEN": {
+                    "description": "Transmit threshold length",
+                    "offset": 2,
+                    "size": 9
+                  },
+                  "RXTHREN": {
+                    "description": "Receive threshold enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RXTHRLEN": {
+                    "description": "Receive threshold length",
+                    "offset": 17,
+                    "size": 9
+                  },
+                  "ARPEN": {
+                    "description": "Arbiter parking enable",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPEMPMSK": {
+              "description": "OTG_HS device IN endpoint FIFO empty\n          interrupt mask register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXFEM": {
+                    "description": "IN EP Tx FIFO empty interrupt mask\n              bits",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DEACHINT": {
+              "description": "OTG_HS device each endpoint interrupt\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEP1INT": {
+                    "description": "IN endpoint 1interrupt bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OEP1INT": {
+                    "description": "OUT endpoint 1 interrupt\n              bit",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DEACHINTMSK": {
+              "description": "OTG_HS device each endpoint interrupt\n          register mask",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEP1INTM": {
+                    "description": "IN Endpoint 1 interrupt mask\n              bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OEP1INTM": {
+                    "description": "OUT Endpoint 1 interrupt mask\n              bit",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPEACHMSK1": {
+              "description": "OTG_HS device each in endpoint-1 interrupt\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOM": {
+                    "description": "Timeout condition mask (nonisochronous\n              endpoints)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFEMSK": {
+                    "description": "IN token received when TxFIFO empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNMM": {
+                    "description": "IN token received with EP mismatch\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INEPNEM": {
+                    "description": "IN endpoint NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFURM": {
+                    "description": "FIFO underrun mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BIM": {
+                    "description": "BNA interrupt mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK interrupt mask",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPEACHMSK1": {
+              "description": "OTG_HS device each OUT endpoint-1 interrupt\n          register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOM": {
+                    "description": "Timeout condition mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFEMSK": {
+                    "description": "IN token received when TxFIFO empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNMM": {
+                    "description": "IN token received with EP mismatch\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INEPNEM": {
+                    "description": "IN endpoint NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFURM": {
+                    "description": "OUT packet error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BIM": {
+                    "description": "BNA interrupt mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BERRM": {
+                    "description": "Bubble error interrupt\n              mask",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK interrupt mask",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "NYETM": {
+                    "description": "NYET interrupt mask",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL0": {
+              "description": "OTG device endpoint-0 control\n          register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL1": {
+              "description": "OTG device endpoint-1 control\n          register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL2": {
+              "description": "OTG device endpoint-2 control\n          register",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL3": {
+              "description": "OTG device endpoint-3 control\n          register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL4": {
+              "description": "OTG device endpoint-4 control\n          register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL5": {
+              "description": "OTG device endpoint-5 control\n          register",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL6": {
+              "description": "OTG device endpoint-6 control\n          register",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL7": {
+              "description": "OTG device endpoint-7 control\n          register",
+              "offset": 480,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT0": {
+              "description": "OTG device endpoint-0 interrupt\n          register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT1": {
+              "description": "OTG device endpoint-1 interrupt\n          register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT2": {
+              "description": "OTG device endpoint-2 interrupt\n          register",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT3": {
+              "description": "OTG device endpoint-3 interrupt\n          register",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT4": {
+              "description": "OTG device endpoint-4 interrupt\n          register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT5": {
+              "description": "OTG device endpoint-5 interrupt\n          register",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT6": {
+              "description": "OTG device endpoint-6 interrupt\n          register",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT7": {
+              "description": "OTG device endpoint-7 interrupt\n          register",
+              "offset": 488,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ0": {
+              "description": "OTG_HS device IN endpoint 0 transfer size\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPDMA1": {
+              "description": "OTG_HS device endpoint-1 DMA address\n          register",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPDMA2": {
+              "description": "OTG_HS device endpoint-2 DMA address\n          register",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPDMA3": {
+              "description": "OTG_HS device endpoint-3 DMA address\n          register",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPDMA4": {
+              "description": "OTG_HS device endpoint-4 DMA address\n          register",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPDMA5": {
+              "description": "OTG_HS device endpoint-5 DMA address\n          register",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS0": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS1": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS2": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS3": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS4": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 408,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS5": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 440,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ1": {
+              "description": "OTG_HS device endpoint transfer size\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ2": {
+              "description": "OTG_HS device endpoint transfer size\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ3": {
+              "description": "OTG_HS device endpoint transfer size\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ4": {
+              "description": "OTG_HS device endpoint transfer size\n          register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ5": {
+              "description": "OTG_HS device endpoint transfer size\n          register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPCTL0": {
+              "description": "OTG_HS device control OUT endpoint 0 control\n          register",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "SNPM": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPCTL1": {
+              "description": "OTG device endpoint-1 control\n          register",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even odd frame/Endpoint data\n              PID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "SNPM": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID/Set even\n              frame",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPCTL2": {
+              "description": "OTG device endpoint-2 control\n          register",
+              "offset": 832,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even odd frame/Endpoint data\n              PID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "SNPM": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID/Set even\n              frame",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPCTL3": {
+              "description": "OTG device endpoint-3 control\n          register",
+              "offset": 864,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even odd frame/Endpoint data\n              PID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "SNPM": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID/Set even\n              frame",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT0": {
+              "description": "OTG_HS device endpoint-0 interrupt\n          register",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT1": {
+              "description": "OTG_HS device endpoint-1 interrupt\n          register",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT2": {
+              "description": "OTG_HS device endpoint-2 interrupt\n          register",
+              "offset": 840,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT3": {
+              "description": "OTG_HS device endpoint-3 interrupt\n          register",
+              "offset": 872,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT4": {
+              "description": "OTG_HS device endpoint-4 interrupt\n          register",
+              "offset": 904,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT5": {
+              "description": "OTG_HS device endpoint-5 interrupt\n          register",
+              "offset": 936,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT6": {
+              "description": "OTG_HS device endpoint-6 interrupt\n          register",
+              "offset": 968,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT7": {
+              "description": "OTG_HS device endpoint-7 interrupt\n          register",
+              "offset": 1000,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPTSIZ0": {
+              "description": "OTG_HS device endpoint-1 transfer size\n          register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "STUPCNT": {
+                    "description": "SETUP packet count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPTSIZ1": {
+              "description": "OTG_HS device endpoint-2 transfer size\n          register",
+              "offset": 816,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPTSIZ2": {
+              "description": "OTG_HS device endpoint-3 transfer size\n          register",
+              "offset": 848,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPTSIZ3": {
+              "description": "OTG_HS device endpoint-4 transfer size\n          register",
+              "offset": 880,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPTSIZ4": {
+              "description": "OTG_HS device endpoint-5 transfer size\n          register",
+              "offset": 912,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_HS_HOST": {
+        "description": "USB on the go high speed",
+        "children": {
+          "registers": {
+            "OTG_HS_HCFG": {
+              "description": "OTG_HS host configuration\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSLSPCS": {
+                    "description": "FS/LS PHY clock select",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "FSLSS": {
+                    "description": "FS- and LS-only support",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_HFIR": {
+              "description": "OTG_HS Host frame interval\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 60000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRIVL": {
+                    "description": "Frame interval",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_HFNUM": {
+              "description": "OTG_HS host frame number/frame time\n          remaining register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 16383,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FRNUM": {
+                    "description": "Frame number",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "FTREM": {
+                    "description": "Frame time remaining",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_HPTXSTS": {
+              "description": "OTG_HS_Host periodic transmit FIFO/queue\n          status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 524544,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTXFSAVL": {
+                    "description": "Periodic transmit data FIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PTXQSAV": {
+                    "description": "Periodic transmit request queue space\n              available",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "PTXQTOP": {
+                    "description": "Top of the periodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_HAINT": {
+              "description": "OTG_HS Host all channels interrupt\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HAINT": {
+                    "description": "Channel interrupts",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_HAINTMSK": {
+              "description": "OTG_HS host all channels interrupt mask\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HAINTM": {
+                    "description": "Channel interrupt mask",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_HPRT": {
+              "description": "OTG_HS host port control and status\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCSTS": {
+                    "description": "Port connect status",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PCDET": {
+                    "description": "Port connect detected",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PENA": {
+                    "description": "Port enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PENCHNG": {
+                    "description": "Port enable/disable change",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "POCA": {
+                    "description": "Port overcurrent active",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "POCCHNG": {
+                    "description": "Port overcurrent change",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PRES": {
+                    "description": "Port resume",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PSUSP": {
+                    "description": "Port suspend",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PRST": {
+                    "description": "Port reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PLSTS": {
+                    "description": "Port line status",
+                    "offset": 10,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PPWR": {
+                    "description": "Port power",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PTCTL": {
+                    "description": "Port test control",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "PSPD": {
+                    "description": "Port speed",
+                    "offset": 17,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR0": {
+              "description": "OTG_HS host channel-0 characteristics\n          register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR1": {
+              "description": "OTG_HS host channel-1 characteristics\n          register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR2": {
+              "description": "OTG_HS host channel-2 characteristics\n          register",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR3": {
+              "description": "OTG_HS host channel-3 characteristics\n          register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR4": {
+              "description": "OTG_HS host channel-4 characteristics\n          register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR5": {
+              "description": "OTG_HS host channel-5 characteristics\n          register",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR6": {
+              "description": "OTG_HS host channel-6 characteristics\n          register",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR7": {
+              "description": "OTG_HS host channel-7 characteristics\n          register",
+              "offset": 480,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR8": {
+              "description": "OTG_HS host channel-8 characteristics\n          register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR9": {
+              "description": "OTG_HS host channel-9 characteristics\n          register",
+              "offset": 544,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR10": {
+              "description": "OTG_HS host channel-10 characteristics\n          register",
+              "offset": 576,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR11": {
+              "description": "OTG_HS host channel-11 characteristics\n          register",
+              "offset": 608,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT0": {
+              "description": "OTG_HS host channel-0 split control\n          register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT1": {
+              "description": "OTG_HS host channel-1 split control\n          register",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT2": {
+              "description": "OTG_HS host channel-2 split control\n          register",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT3": {
+              "description": "OTG_HS host channel-3 split control\n          register",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT4": {
+              "description": "OTG_HS host channel-4 split control\n          register",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT5": {
+              "description": "OTG_HS host channel-5 split control\n          register",
+              "offset": 420,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT6": {
+              "description": "OTG_HS host channel-6 split control\n          register",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT7": {
+              "description": "OTG_HS host channel-7 split control\n          register",
+              "offset": 484,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT8": {
+              "description": "OTG_HS host channel-8 split control\n          register",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT9": {
+              "description": "OTG_HS host channel-9 split control\n          register",
+              "offset": 548,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT10": {
+              "description": "OTG_HS host channel-10 split control\n          register",
+              "offset": 580,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT11": {
+              "description": "OTG_HS host channel-11 split control\n          register",
+              "offset": 612,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT0": {
+              "description": "OTG_HS host channel-11 interrupt\n          register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT1": {
+              "description": "OTG_HS host channel-1 interrupt\n          register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT2": {
+              "description": "OTG_HS host channel-2 interrupt\n          register",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT3": {
+              "description": "OTG_HS host channel-3 interrupt\n          register",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT4": {
+              "description": "OTG_HS host channel-4 interrupt\n          register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT5": {
+              "description": "OTG_HS host channel-5 interrupt\n          register",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT6": {
+              "description": "OTG_HS host channel-6 interrupt\n          register",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT7": {
+              "description": "OTG_HS host channel-7 interrupt\n          register",
+              "offset": 488,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT8": {
+              "description": "OTG_HS host channel-8 interrupt\n          register",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT9": {
+              "description": "OTG_HS host channel-9 interrupt\n          register",
+              "offset": 552,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT10": {
+              "description": "OTG_HS host channel-10 interrupt\n          register",
+              "offset": 584,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT11": {
+              "description": "OTG_HS host channel-11 interrupt\n          register",
+              "offset": 616,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK0": {
+              "description": "OTG_HS host channel-11 interrupt mask\n          register",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK1": {
+              "description": "OTG_HS host channel-1 interrupt mask\n          register",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK2": {
+              "description": "OTG_HS host channel-2 interrupt mask\n          register",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK3": {
+              "description": "OTG_HS host channel-3 interrupt mask\n          register",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK4": {
+              "description": "OTG_HS host channel-4 interrupt mask\n          register",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK5": {
+              "description": "OTG_HS host channel-5 interrupt mask\n          register",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK6": {
+              "description": "OTG_HS host channel-6 interrupt mask\n          register",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK7": {
+              "description": "OTG_HS host channel-7 interrupt mask\n          register",
+              "offset": 492,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK8": {
+              "description": "OTG_HS host channel-8 interrupt mask\n          register",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK9": {
+              "description": "OTG_HS host channel-9 interrupt mask\n          register",
+              "offset": 556,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK10": {
+              "description": "OTG_HS host channel-10 interrupt mask\n          register",
+              "offset": 588,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK11": {
+              "description": "OTG_HS host channel-11 interrupt mask\n          register",
+              "offset": 620,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ0": {
+              "description": "OTG_HS host channel-11 transfer size\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ1": {
+              "description": "OTG_HS host channel-1 transfer size\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ2": {
+              "description": "OTG_HS host channel-2 transfer size\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ3": {
+              "description": "OTG_HS host channel-3 transfer size\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ4": {
+              "description": "OTG_HS host channel-4 transfer size\n          register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ5": {
+              "description": "OTG_HS host channel-5 transfer size\n          register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ6": {
+              "description": "OTG_HS host channel-6 transfer size\n          register",
+              "offset": 464,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ7": {
+              "description": "OTG_HS host channel-7 transfer size\n          register",
+              "offset": 496,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ8": {
+              "description": "OTG_HS host channel-8 transfer size\n          register",
+              "offset": 528,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ9": {
+              "description": "OTG_HS host channel-9 transfer size\n          register",
+              "offset": 560,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ10": {
+              "description": "OTG_HS host channel-10 transfer size\n          register",
+              "offset": 592,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ11": {
+              "description": "OTG_HS host channel-11 transfer size\n          register",
+              "offset": 624,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA0": {
+              "description": "OTG_HS host channel-0 DMA address\n          register",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA1": {
+              "description": "OTG_HS host channel-1 DMA address\n          register",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA2": {
+              "description": "OTG_HS host channel-2 DMA address\n          register",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA3": {
+              "description": "OTG_HS host channel-3 DMA address\n          register",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA4": {
+              "description": "OTG_HS host channel-4 DMA address\n          register",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA5": {
+              "description": "OTG_HS host channel-5 DMA address\n          register",
+              "offset": 436,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA6": {
+              "description": "OTG_HS host channel-6 DMA address\n          register",
+              "offset": 468,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA7": {
+              "description": "OTG_HS host channel-7 DMA address\n          register",
+              "offset": 500,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA8": {
+              "description": "OTG_HS host channel-8 DMA address\n          register",
+              "offset": 532,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA9": {
+              "description": "OTG_HS host channel-9 DMA address\n          register",
+              "offset": 564,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA10": {
+              "description": "OTG_HS host channel-10 DMA address\n          register",
+              "offset": 596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA11": {
+              "description": "OTG_HS host channel-11 DMA address\n          register",
+              "offset": 628,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_HS_GLOBAL": {
+        "description": "USB on the go high speed",
+        "children": {
+          "registers": {
+            "OTG_HS_GOTGCTL": {
+              "description": "OTG_HS control and status\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRQSCS": {
+                    "description": "Session request success",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SRQ": {
+                    "description": "Session request",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HNGSCS": {
+                    "description": "Host negotiation success",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HNPRQ": {
+                    "description": "HNP request",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HSHNPEN": {
+                    "description": "Host set HNP enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DHNPEN": {
+                    "description": "Device HNP enabled",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CIDSTS": {
+                    "description": "Connector ID status",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DBCT": {
+                    "description": "Long/short debounce time",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ASVLD": {
+                    "description": "A-session valid",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BSVLD": {
+                    "description": "B-session valid",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_GOTGINT": {
+              "description": "OTG_HS interrupt register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEDET": {
+                    "description": "Session end detected",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SRSSCHG": {
+                    "description": "Session request success status\n              change",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNSSCHG": {
+                    "description": "Host negotiation success status\n              change",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HNGDET": {
+                    "description": "Host negotiation detected",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ADTOCHG": {
+                    "description": "A-device timeout change",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DBCDNE": {
+                    "description": "Debounce done",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_GAHBCFG": {
+              "description": "OTG_HS AHB configuration\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GINT": {
+                    "description": "Global interrupt mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HBSTLEN": {
+                    "description": "Burst length/type",
+                    "offset": 1,
+                    "size": 4
+                  },
+                  "DMAEN": {
+                    "description": "DMA enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFELVL": {
+                    "description": "TxFIFO empty level",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PTXFELVL": {
+                    "description": "Periodic TxFIFO empty\n              level",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_GUSBCFG": {
+              "description": "OTG_HS USB configuration\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 2560,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TOCAL": {
+                    "description": "FS timeout calibration",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "PHYSEL": {
+                    "description": "USB 2.0 high-speed ULPI PHY or USB 1.1\n              full-speed serial transceiver select",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SRPCAP": {
+                    "description": "SRP-capable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNPCAP": {
+                    "description": "HNP-capable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TRDT": {
+                    "description": "USB turnaround time",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "PHYLPCS": {
+                    "description": "PHY Low-power clock select",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ULPIFSLS": {
+                    "description": "ULPI FS/LS select",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ULPIAR": {
+                    "description": "ULPI Auto-resume",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "ULPICSM": {
+                    "description": "ULPI Clock SuspendM",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ULPIEVBUSD": {
+                    "description": "ULPI External VBUS Drive",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "ULPIEVBUSI": {
+                    "description": "ULPI external VBUS\n              indicator",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TSDPS": {
+                    "description": "TermSel DLine pulsing\n              selection",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PCCI": {
+                    "description": "Indicator complement",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PTCI": {
+                    "description": "Indicator pass through",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "ULPIIPD": {
+                    "description": "ULPI interface protect\n              disable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FHMOD": {
+                    "description": "Forced host mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FDMOD": {
+                    "description": "Forced peripheral mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CTXPKT": {
+                    "description": "Corrupt Tx packet",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRSTCTL": {
+              "description": "OTG_HS reset register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 536870912,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSRST": {
+                    "description": "Core soft reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HSRST": {
+                    "description": "HCLK soft reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FCRST": {
+                    "description": "Host frame counter reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RXFFLSH": {
+                    "description": "RxFIFO flush",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TXFFLSH": {
+                    "description": "TxFIFO flush",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "DMAREQ": {
+                    "description": "DMA request signal",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "AHBIDL": {
+                    "description": "AHB master idle",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_GINTSTS": {
+              "description": "OTG_HS core interrupt register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 67108896,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CMOD": {
+                    "description": "Current mode of operation",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMIS": {
+                    "description": "Mode mismatch interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGINT": {
+                    "description": "OTG interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOF": {
+                    "description": "Start of frame",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFLVL": {
+                    "description": "RxFIFO nonempty",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NPTXFE": {
+                    "description": "Nonperiodic TxFIFO empty",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GINAKEFF": {
+                    "description": "Global IN nonperiodic NAK\n              effective",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BOUTNAKEFF": {
+                    "description": "Global OUT NAK effective",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ESUSP": {
+                    "description": "Early suspend",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "USBSUSP": {
+                    "description": "USB suspend",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMDNE": {
+                    "description": "Enumeration done",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOODRP": {
+                    "description": "Isochronous OUT packet dropped\n              interrupt",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPF": {
+                    "description": "End of periodic frame\n              interrupt",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IEPINT": {
+                    "description": "IN endpoint interrupt",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IISOIXFR": {
+                    "description": "Incomplete isochronous IN\n              transfer",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PXFR_INCOMPISOOUT": {
+                    "description": "Incomplete periodic\n              transfer",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "DATAFSUSP": {
+                    "description": "Data fetch suspended",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "HPRTINT": {
+                    "description": "Host port interrupt",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCINT": {
+                    "description": "Host channels interrupt",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PTXFE": {
+                    "description": "Periodic TxFIFO empty",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CIDSCHG": {
+                    "description": "Connector ID status change",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCINT": {
+                    "description": "Disconnect detected\n              interrupt",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SRQINT": {
+                    "description": "Session request/new session detected\n              interrupt",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WKUINT": {
+                    "description": "Resume/remote wakeup detected\n              interrupt",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_GINTMSK": {
+              "description": "OTG_HS interrupt mask register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMISM": {
+                    "description": "Mode mismatch interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGINT": {
+                    "description": "OTG interrupt mask",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SOFM": {
+                    "description": "Start of frame mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFLVLM": {
+                    "description": "Receive FIFO nonempty mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "NPTXFEM": {
+                    "description": "Nonperiodic TxFIFO empty\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GINAKEFFM": {
+                    "description": "Global nonperiodic IN NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GONAKEFFM": {
+                    "description": "Global OUT NAK effective\n              mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ESUSPM": {
+                    "description": "Early suspend mask",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "USBSUSPM": {
+                    "description": "USB suspend mask",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset mask",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMDNEM": {
+                    "description": "Enumeration done mask",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOODRPM": {
+                    "description": "Isochronous OUT packet dropped interrupt\n              mask",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPFM": {
+                    "description": "End of periodic frame interrupt\n              mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPMISM": {
+                    "description": "Endpoint mismatch interrupt\n              mask",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "IEPINT": {
+                    "description": "IN endpoints interrupt\n              mask",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoints interrupt\n              mask",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IISOIXFRM": {
+                    "description": "Incomplete isochronous IN transfer\n              mask",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PXFRM_IISOOXFRM": {
+                    "description": "Incomplete periodic transfer\n              mask",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FSUSPM": {
+                    "description": "Data fetch suspended mask",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PRTIM": {
+                    "description": "Host port interrupt mask",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCIM": {
+                    "description": "Host channels interrupt\n              mask",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PTXFEM": {
+                    "description": "Periodic TxFIFO empty mask",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CIDSCHGM": {
+                    "description": "Connector ID status change\n              mask",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCINT": {
+                    "description": "Disconnect detected interrupt\n              mask",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SRQIM": {
+                    "description": "Session request/new session detected\n              interrupt mask",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WUIM": {
+                    "description": "Resume/remote wakeup detected interrupt\n              mask",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRXSTSR_Host": {
+              "description": "OTG_HS Receive status debug read register\n          (host mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CHNUM": {
+                    "description": "Channel number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRXSTSP_Host": {
+              "description": "OTG_HS status read and pop register (host\n          mode)",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CHNUM": {
+                    "description": "Channel number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRXFSIZ": {
+              "description": "OTG_HS Receive FIFO size\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFD": {
+                    "description": "RxFIFO depth",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_GNPTXFSIZ_Host": {
+              "description": "OTG_HS nonperiodic transmit FIFO size\n          register (host mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NPTXFSA": {
+                    "description": "Nonperiodic transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "NPTXFD": {
+                    "description": "Nonperiodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_TX0FSIZ_Peripheral": {
+              "description": "Endpoint 0 transmit FIFO size (peripheral\n          mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX0FSA": {
+                    "description": "Endpoint 0 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "TX0FD": {
+                    "description": "Endpoint 0 TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_GNPTXSTS": {
+              "description": "OTG_HS nonperiodic transmit FIFO/queue\n          status register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 524800,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "NPTXFSAV": {
+                    "description": "Nonperiodic TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "NPTQXSAV": {
+                    "description": "Nonperiodic transmit request queue space\n              available",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "NPTXQTOP": {
+                    "description": "Top of the nonperiodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "OTG_HS_GCCFG": {
+              "description": "OTG_HS general core configuration\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWRDWN": {
+                    "description": "Power down",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "I2CPADEN": {
+                    "description": "Enable I2C bus connection for the\n              external I2C PHY interface",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "VBUSASEN": {
+                    "description": "Enable the VBUS sensing\n              device",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "VBUSBSEN": {
+                    "description": "Enable the VBUS sensing\n              device",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SOFOUTEN": {
+                    "description": "SOF output enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "NOVBUSSENS": {
+                    "description": "VBUS sensing disable\n              option",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_CID": {
+              "description": "OTG_HS core ID register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 4608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRODUCT_ID": {
+                    "description": "Product ID field",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HPTXFSIZ": {
+              "description": "OTG_HS Host periodic transmit FIFO size\n          register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 33555968,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTXSA": {
+                    "description": "Host periodic TxFIFO start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PTXFD": {
+                    "description": "Host periodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF1": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF2": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF3": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF4": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF5": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF6": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF7": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRXSTSR_Peripheral": {
+              "description": "OTG_HS Receive status debug read register\n          (peripheral mode mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  },
+                  "FRMNUM": {
+                    "description": "Frame number",
+                    "offset": 21,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRXSTSP_Peripheral": {
+              "description": "OTG_HS status read and pop register\n          (peripheral mode)",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  },
+                  "FRMNUM": {
+                    "description": "Frame number",
+                    "offset": 21,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SDIO": {
+        "description": "Secure digital input/output\n      interface",
+        "children": {
+          "registers": {
+            "POWER": {
+              "description": "power control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWRCTRL": {
+                    "description": "PWRCTRL",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLKCR": {
+              "description": "SDI clock control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HWFC_EN": {
+                    "description": "HW Flow Control enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "NEGEDGE": {
+                    "description": "SDIO_CK dephasing selection\n              bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WIDBUS": {
+                    "description": "Wide bus mode enable bit",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "BYPASS": {
+                    "description": "Clock divider bypass enable\n              bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PWRSAV": {
+                    "description": "Power saving configuration\n              bit",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CLKEN": {
+                    "description": "Clock enable bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CLKDIV": {
+                    "description": "Clock divide factor",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ARG": {
+              "description": "argument register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CMDARG": {
+                    "description": "Command argument",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMD": {
+              "description": "command register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CE_ATACMD": {
+                    "description": "CE-ATA command",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "nIEN": {
+                    "description": "not Interrupt Enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ENCMDcompl": {
+                    "description": "Enable CMD completion",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SDIOSuspend": {
+                    "description": "SD I/O suspend command",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CPSMEN": {
+                    "description": "Command path state machine (CPSM) Enable\n              bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPEND": {
+                    "description": "CPSM Waits for ends of data transfer\n              (CmdPend internal signal).",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WAITINT": {
+                    "description": "CPSM waits for interrupt\n              request",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WAITRESP": {
+                    "description": "Wait for response bits",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CMDINDEX": {
+                    "description": "Command index",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "RESPCMD": {
+              "description": "command response register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RESPCMD": {
+                    "description": "Response command index",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "RESP1": {
+              "description": "response 1..4 register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS1": {
+                    "description": "see Table 132.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RESP2": {
+              "description": "response 1..4 register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS2": {
+                    "description": "see Table 132.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RESP3": {
+              "description": "response 1..4 register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS3": {
+                    "description": "see Table 132.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RESP4": {
+              "description": "response 1..4 register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS4": {
+                    "description": "see Table 132.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DTIMER": {
+              "description": "data timer register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATATIME": {
+                    "description": "Data timeout period",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DLEN": {
+              "description": "data length register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATALENGTH": {
+                    "description": "Data length value",
+                    "offset": 0,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "DCTRL": {
+              "description": "data control register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDIOEN": {
+                    "description": "SD I/O enable functions",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RWMOD": {
+                    "description": "Read wait mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RWSTOP": {
+                    "description": "Read wait stop",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RWSTART": {
+                    "description": "Read wait start",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DBLOCKSIZE": {
+                    "description": "Data block size",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "DMAEN": {
+                    "description": "DMA enable bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DTMODE": {
+                    "description": "Data transfer mode selection 1: Stream\n              or SDIO multibyte data transfer.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DTDIR": {
+                    "description": "Data transfer direction\n              selection",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DTEN": {
+                    "description": "DTEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DCOUNT": {
+              "description": "data counter register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATACOUNT": {
+                    "description": "Data count value",
+                    "offset": 0,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "STA": {
+              "description": "status register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CEATAEND": {
+                    "description": "CE-ATA command completion signal\n              received for CMD61",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "SDIOIT": {
+                    "description": "SDIO interrupt received",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "RXDAVL": {
+                    "description": "Data available in receive\n              FIFO",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXDAVL": {
+                    "description": "Data available in transmit\n              FIFO",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RXFIFOE": {
+                    "description": "Receive FIFO empty",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TXFIFOE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RXFIFOF": {
+                    "description": "Receive FIFO full",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TXFIFOF": {
+                    "description": "Transmit FIFO full",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RXFIFOHF": {
+                    "description": "Receive FIFO half full: there are at\n              least 8 words in the FIFO",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TXFIFOHE": {
+                    "description": "Transmit FIFO half empty: at least 8\n              words can be written into the FIFO",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RXACT": {
+                    "description": "Data receive in progress",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TXACT": {
+                    "description": "Data transmit in progress",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CMDACT": {
+                    "description": "Command transfer in\n              progress",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DBCKEND": {
+                    "description": "Data block sent/received (CRC check\n              passed)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "STBITERR": {
+                    "description": "Start bit not detected on all data\n              signals in wide bus mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DATAEND": {
+                    "description": "Data end (data counter, SDIDCOUNT, is\n              zero)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CMDSENT": {
+                    "description": "Command sent (no response\n              required)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMDREND": {
+                    "description": "Command response received (CRC check\n              passed)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXOVERR": {
+                    "description": "Received FIFO overrun\n              error",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXUNDERR": {
+                    "description": "Transmit FIFO underrun\n              error",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DTIMEOUT": {
+                    "description": "Data timeout",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CTIMEOUT": {
+                    "description": "Command response timeout",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DCRCFAIL": {
+                    "description": "Data block sent/received (CRC check\n              failed)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CCRCFAIL": {
+                    "description": "Command response received (CRC check\n              failed)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "interrupt clear register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEATAENDC": {
+                    "description": "CEATAEND flag clear bit",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "SDIOITC": {
+                    "description": "SDIOIT flag clear bit",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DBCKENDC": {
+                    "description": "DBCKEND flag clear bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "STBITERRC": {
+                    "description": "STBITERR flag clear bit",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DATAENDC": {
+                    "description": "DATAEND flag clear bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CMDSENTC": {
+                    "description": "CMDSENT flag clear bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMDRENDC": {
+                    "description": "CMDREND flag clear bit",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXOVERRC": {
+                    "description": "RXOVERR flag clear bit",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXUNDERRC": {
+                    "description": "TXUNDERR flag clear bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DTIMEOUTC": {
+                    "description": "DTIMEOUT flag clear bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CTIMEOUTC": {
+                    "description": "CTIMEOUT flag clear bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DCRCFAILC": {
+                    "description": "DCRCFAIL flag clear bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CCRCFAILC": {
+                    "description": "CCRCFAIL flag clear bit",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MASK": {
+              "description": "mask register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEATAENDIE": {
+                    "description": "CE-ATA command completion signal\n              received interrupt enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "SDIOITIE": {
+                    "description": "SDIO mode interrupt received interrupt\n              enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "RXDAVLIE": {
+                    "description": "Data available in Rx FIFO interrupt\n              enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXDAVLIE": {
+                    "description": "Data available in Tx FIFO interrupt\n              enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RXFIFOEIE": {
+                    "description": "Rx FIFO empty interrupt\n              enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TXFIFOEIE": {
+                    "description": "Tx FIFO empty interrupt\n              enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RXFIFOFIE": {
+                    "description": "Rx FIFO full interrupt\n              enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TXFIFOFIE": {
+                    "description": "Tx FIFO full interrupt\n              enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RXFIFOHFIE": {
+                    "description": "Rx FIFO half full interrupt\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TXFIFOHEIE": {
+                    "description": "Tx FIFO half empty interrupt\n              enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RXACTIE": {
+                    "description": "Data receive acting interrupt\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TXACTIE": {
+                    "description": "Data transmit acting interrupt\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CMDACTIE": {
+                    "description": "Command acting interrupt\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DBCKENDIE": {
+                    "description": "Data block end interrupt\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "STBITERRIE": {
+                    "description": "Start bit error interrupt\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DATAENDIE": {
+                    "description": "Data end interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CMDSENTIE": {
+                    "description": "Command sent interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMDRENDIE": {
+                    "description": "Command response received interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXOVERRIE": {
+                    "description": "Rx FIFO overrun error interrupt\n              enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXUNDERRIE": {
+                    "description": "Tx FIFO underrun error interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DTIMEOUTIE": {
+                    "description": "Data timeout interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CTIMEOUTIE": {
+                    "description": "Command timeout interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DCRCFAILIE": {
+                    "description": "Data CRC fail interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CCRCFAILIE": {
+                    "description": "Command CRC fail interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FIFOCNT": {
+              "description": "FIFO counter register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FIFOCOUNT": {
+                    "description": "Remaining number of words to be written\n              to or read from the FIFO.",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "FIFO": {
+              "description": "data FIFO register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FIFOData": {
+                    "description": "Receive and transmit FIFO\n              data",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ADC1": {
+        "description": "Analog-to-digital converter",
+        "children": {
+          "registers": {
+            "SR": {
+              "description": "status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVR": {
+                    "description": "Overrun",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "STRT": {
+                    "description": "Regular channel start flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "JSTRT": {
+                    "description": "Injected channel start\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "JEOC": {
+                    "description": "Injected channel end of\n              conversion",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EOC": {
+                    "description": "Regular channel end of\n              conversion",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AWD": {
+                    "description": "Analog watchdog flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "control register 1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVRIE": {
+                    "description": "Overrun interrupt enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RES": {
+                    "description": "Resolution",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "AWDEN": {
+                    "description": "Analog watchdog enable on regular\n              channels",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "JAWDEN": {
+                    "description": "Analog watchdog enable on injected\n              channels",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DISCNUM": {
+                    "description": "Discontinuous mode channel\n              count",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "JDISCEN": {
+                    "description": "Discontinuous mode on injected\n              channels",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DISCEN": {
+                    "description": "Discontinuous mode on regular\n              channels",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "JAUTO": {
+                    "description": "Automatic injected group\n              conversion",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AWDSGL": {
+                    "description": "Enable the watchdog on a single channel\n              in scan mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SCAN": {
+                    "description": "Scan mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "JEOCIE": {
+                    "description": "Interrupt enable for injected\n              channels",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "AWDIE": {
+                    "description": "Analog watchdog interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EOCIE": {
+                    "description": "Interrupt enable for EOC",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "AWDCH": {
+                    "description": "Analog watchdog channel select\n              bits",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWSTART": {
+                    "description": "Start conversion of regular\n              channels",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EXTEN": {
+                    "description": "External trigger enable for regular\n              channels",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "EXTSEL": {
+                    "description": "External event select for regular\n              group",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "JSWSTART": {
+                    "description": "Start conversion of injected\n              channels",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "JEXTEN": {
+                    "description": "External trigger enable for injected\n              channels",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "JEXTSEL": {
+                    "description": "External event select for injected\n              group",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ALIGN": {
+                    "description": "Data alignment",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EOCS": {
+                    "description": "End of conversion\n              selection",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DDS": {
+                    "description": "DMA disable selection (for single ADC\n              mode)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DMA": {
+                    "description": "Direct memory access mode (for single\n              ADC mode)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CONT": {
+                    "description": "Continuous conversion",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ADON": {
+                    "description": "A/D Converter ON / OFF",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMPR1": {
+              "description": "sample time register 1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMPx_x": {
+                    "description": "Sample time bits",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SMPR2": {
+              "description": "sample time register 2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMPx_x": {
+                    "description": "Sample time bits",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "JOFR1": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET1": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR2": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET2": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR3": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET3": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR4": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET4": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "HTR": {
+              "description": "watchdog higher threshold\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HT": {
+                    "description": "Analog watchdog higher\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "LTR": {
+              "description": "watchdog lower threshold\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LT": {
+                    "description": "Analog watchdog lower\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "SQR1": {
+              "description": "regular sequence register 1",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "L": {
+                    "description": "Regular channel sequence\n              length",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "SQ16": {
+                    "description": "16th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ15": {
+                    "description": "15th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ14": {
+                    "description": "14th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ13": {
+                    "description": "13th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SQR2": {
+              "description": "regular sequence register 2",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ12": {
+                    "description": "12th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "SQ11": {
+                    "description": "11th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "SQ10": {
+                    "description": "10th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ9": {
+                    "description": "9th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ8": {
+                    "description": "8th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ7": {
+                    "description": "7th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SQR3": {
+              "description": "regular sequence register 3",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ6": {
+                    "description": "6th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "SQ5": {
+                    "description": "5th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "SQ4": {
+                    "description": "4th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ3": {
+                    "description": "3rd conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ2": {
+                    "description": "2nd conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ1": {
+                    "description": "1st conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "JSQR": {
+              "description": "injected sequence register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JL": {
+                    "description": "Injected sequence length",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "JSQ4": {
+                    "description": "4th conversion in injected\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "JSQ3": {
+                    "description": "3rd conversion in injected\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "JSQ2": {
+                    "description": "2nd conversion in injected\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "JSQ1": {
+                    "description": "1st conversion in injected\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "JDR1": {
+              "description": "injected data register x",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR2": {
+              "description": "injected data register x",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR3": {
+              "description": "injected data register x",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR4": {
+              "description": "injected data register x",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "regular data register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Regular data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EXTI": {
+        "description": "External interrupt/event\n      controller",
+        "children": {
+          "registers": {
+            "IMR": {
+              "description": "Interrupt mask register\n          (EXTI_IMR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR0": {
+                    "description": "Interrupt Mask on line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MR1": {
+                    "description": "Interrupt Mask on line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MR2": {
+                    "description": "Interrupt Mask on line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MR3": {
+                    "description": "Interrupt Mask on line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MR4": {
+                    "description": "Interrupt Mask on line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MR5": {
+                    "description": "Interrupt Mask on line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MR6": {
+                    "description": "Interrupt Mask on line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MR7": {
+                    "description": "Interrupt Mask on line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MR8": {
+                    "description": "Interrupt Mask on line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "MR9": {
+                    "description": "Interrupt Mask on line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "MR10": {
+                    "description": "Interrupt Mask on line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "MR11": {
+                    "description": "Interrupt Mask on line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "MR12": {
+                    "description": "Interrupt Mask on line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MR13": {
+                    "description": "Interrupt Mask on line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MR14": {
+                    "description": "Interrupt Mask on line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MR15": {
+                    "description": "Interrupt Mask on line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MR16": {
+                    "description": "Interrupt Mask on line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MR17": {
+                    "description": "Interrupt Mask on line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MR18": {
+                    "description": "Interrupt Mask on line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "MR19": {
+                    "description": "Interrupt Mask on line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "MR20": {
+                    "description": "Interrupt Mask on line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "MR21": {
+                    "description": "Interrupt Mask on line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "MR22": {
+                    "description": "Interrupt Mask on line 22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EMR": {
+              "description": "Event mask register (EXTI_EMR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR0": {
+                    "description": "Event Mask on line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MR1": {
+                    "description": "Event Mask on line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MR2": {
+                    "description": "Event Mask on line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MR3": {
+                    "description": "Event Mask on line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MR4": {
+                    "description": "Event Mask on line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MR5": {
+                    "description": "Event Mask on line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MR6": {
+                    "description": "Event Mask on line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MR7": {
+                    "description": "Event Mask on line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MR8": {
+                    "description": "Event Mask on line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "MR9": {
+                    "description": "Event Mask on line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "MR10": {
+                    "description": "Event Mask on line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "MR11": {
+                    "description": "Event Mask on line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "MR12": {
+                    "description": "Event Mask on line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MR13": {
+                    "description": "Event Mask on line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MR14": {
+                    "description": "Event Mask on line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MR15": {
+                    "description": "Event Mask on line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MR16": {
+                    "description": "Event Mask on line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MR17": {
+                    "description": "Event Mask on line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MR18": {
+                    "description": "Event Mask on line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "MR19": {
+                    "description": "Event Mask on line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "MR20": {
+                    "description": "Event Mask on line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "MR21": {
+                    "description": "Event Mask on line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "MR22": {
+                    "description": "Event Mask on line 22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RTSR": {
+              "description": "Rising Trigger selection register\n          (EXTI_RTSR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TR0": {
+                    "description": "Rising trigger event configuration of\n              line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TR1": {
+                    "description": "Rising trigger event configuration of\n              line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TR2": {
+                    "description": "Rising trigger event configuration of\n              line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TR3": {
+                    "description": "Rising trigger event configuration of\n              line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TR4": {
+                    "description": "Rising trigger event configuration of\n              line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TR5": {
+                    "description": "Rising trigger event configuration of\n              line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TR6": {
+                    "description": "Rising trigger event configuration of\n              line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TR7": {
+                    "description": "Rising trigger event configuration of\n              line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TR8": {
+                    "description": "Rising trigger event configuration of\n              line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TR9": {
+                    "description": "Rising trigger event configuration of\n              line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TR10": {
+                    "description": "Rising trigger event configuration of\n              line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TR11": {
+                    "description": "Rising trigger event configuration of\n              line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TR12": {
+                    "description": "Rising trigger event configuration of\n              line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TR13": {
+                    "description": "Rising trigger event configuration of\n              line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TR14": {
+                    "description": "Rising trigger event configuration of\n              line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TR15": {
+                    "description": "Rising trigger event configuration of\n              line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TR16": {
+                    "description": "Rising trigger event configuration of\n              line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TR17": {
+                    "description": "Rising trigger event configuration of\n              line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TR18": {
+                    "description": "Rising trigger event configuration of\n              line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TR19": {
+                    "description": "Rising trigger event configuration of\n              line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TR20": {
+                    "description": "Rising trigger event configuration of\n              line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TR21": {
+                    "description": "Rising trigger event configuration of\n              line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TR22": {
+                    "description": "Rising trigger event configuration of\n              line 22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FTSR": {
+              "description": "Falling Trigger selection register\n          (EXTI_FTSR)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TR0": {
+                    "description": "Falling trigger event configuration of\n              line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TR1": {
+                    "description": "Falling trigger event configuration of\n              line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TR2": {
+                    "description": "Falling trigger event configuration of\n              line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TR3": {
+                    "description": "Falling trigger event configuration of\n              line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TR4": {
+                    "description": "Falling trigger event configuration of\n              line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TR5": {
+                    "description": "Falling trigger event configuration of\n              line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TR6": {
+                    "description": "Falling trigger event configuration of\n              line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TR7": {
+                    "description": "Falling trigger event configuration of\n              line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TR8": {
+                    "description": "Falling trigger event configuration of\n              line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TR9": {
+                    "description": "Falling trigger event configuration of\n              line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TR10": {
+                    "description": "Falling trigger event configuration of\n              line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TR11": {
+                    "description": "Falling trigger event configuration of\n              line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TR12": {
+                    "description": "Falling trigger event configuration of\n              line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TR13": {
+                    "description": "Falling trigger event configuration of\n              line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TR14": {
+                    "description": "Falling trigger event configuration of\n              line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TR15": {
+                    "description": "Falling trigger event configuration of\n              line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TR16": {
+                    "description": "Falling trigger event configuration of\n              line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TR17": {
+                    "description": "Falling trigger event configuration of\n              line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TR18": {
+                    "description": "Falling trigger event configuration of\n              line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TR19": {
+                    "description": "Falling trigger event configuration of\n              line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TR20": {
+                    "description": "Falling trigger event configuration of\n              line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TR21": {
+                    "description": "Falling trigger event configuration of\n              line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TR22": {
+                    "description": "Falling trigger event configuration of\n              line 22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWIER": {
+              "description": "Software interrupt event register\n          (EXTI_SWIER)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWIER0": {
+                    "description": "Software Interrupt on line\n              0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SWIER1": {
+                    "description": "Software Interrupt on line\n              1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SWIER2": {
+                    "description": "Software Interrupt on line\n              2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SWIER3": {
+                    "description": "Software Interrupt on line\n              3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SWIER4": {
+                    "description": "Software Interrupt on line\n              4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SWIER5": {
+                    "description": "Software Interrupt on line\n              5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SWIER6": {
+                    "description": "Software Interrupt on line\n              6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SWIER7": {
+                    "description": "Software Interrupt on line\n              7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SWIER8": {
+                    "description": "Software Interrupt on line\n              8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SWIER9": {
+                    "description": "Software Interrupt on line\n              9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SWIER10": {
+                    "description": "Software Interrupt on line\n              10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SWIER11": {
+                    "description": "Software Interrupt on line\n              11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SWIER12": {
+                    "description": "Software Interrupt on line\n              12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SWIER13": {
+                    "description": "Software Interrupt on line\n              13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SWIER14": {
+                    "description": "Software Interrupt on line\n              14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SWIER15": {
+                    "description": "Software Interrupt on line\n              15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SWIER16": {
+                    "description": "Software Interrupt on line\n              16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SWIER17": {
+                    "description": "Software Interrupt on line\n              17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SWIER18": {
+                    "description": "Software Interrupt on line\n              18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "SWIER19": {
+                    "description": "Software Interrupt on line\n              19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SWIER20": {
+                    "description": "Software Interrupt on line\n              20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "SWIER21": {
+                    "description": "Software Interrupt on line\n              21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SWIER22": {
+                    "description": "Software Interrupt on line\n              22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PR": {
+              "description": "Pending register (EXTI_PR)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PR0": {
+                    "description": "Pending bit 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PR1": {
+                    "description": "Pending bit 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PR2": {
+                    "description": "Pending bit 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PR3": {
+                    "description": "Pending bit 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PR4": {
+                    "description": "Pending bit 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PR5": {
+                    "description": "Pending bit 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PR6": {
+                    "description": "Pending bit 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PR7": {
+                    "description": "Pending bit 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PR8": {
+                    "description": "Pending bit 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PR9": {
+                    "description": "Pending bit 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PR10": {
+                    "description": "Pending bit 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PR11": {
+                    "description": "Pending bit 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PR12": {
+                    "description": "Pending bit 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PR13": {
+                    "description": "Pending bit 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PR14": {
+                    "description": "Pending bit 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PR15": {
+                    "description": "Pending bit 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "PR16": {
+                    "description": "Pending bit 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PR17": {
+                    "description": "Pending bit 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PR18": {
+                    "description": "Pending bit 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PR19": {
+                    "description": "Pending bit 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PR20": {
+                    "description": "Pending bit 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PR21": {
+                    "description": "Pending bit 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "PR22": {
+                    "description": "Pending bit 22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FLASH": {
+        "description": "FLASH",
+        "children": {
+          "registers": {
+            "ACR": {
+              "description": "Flash access control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LATENCY": {
+                    "description": "Latency",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "PRFTEN": {
+                    "description": "Prefetch enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ICEN": {
+                    "description": "Instruction cache enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DCEN": {
+                    "description": "Data cache enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ICRST": {
+                    "description": "Instruction cache reset",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DCRST": {
+                    "description": "Data cache reset",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "KEYR": {
+              "description": "Flash key register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "KEY": {
+                    "description": "FPEC key",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OPTKEYR": {
+              "description": "Flash option key register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "OPTKEY": {
+                    "description": "Option byte key",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EOP": {
+                    "description": "End of operation",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "OPERR": {
+                    "description": "Operation error",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WRPERR": {
+                    "description": "Write protection error",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PGAERR": {
+                    "description": "Programming alignment\n              error",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PGPERR": {
+                    "description": "Programming parallelism\n              error",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PGSERR": {
+                    "description": "Programming sequence error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BSY": {
+                    "description": "Busy",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "Control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 2147483648,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PG": {
+                    "description": "Programming",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SER": {
+                    "description": "Sector Erase",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MER": {
+                    "description": "Mass Erase",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SNB": {
+                    "description": "Sector number",
+                    "offset": 3,
+                    "size": 4
+                  },
+                  "PSIZE": {
+                    "description": "Program size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "STRT": {
+                    "description": "Start",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EOPIE": {
+                    "description": "End of operation interrupt\n              enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "LOCK": {
+                    "description": "Lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OPTCR": {
+              "description": "Flash option control register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 20,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OPTLOCK": {
+                    "description": "Option lock",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "OPTSTRT": {
+                    "description": "Option start",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BOR_LEV": {
+                    "description": "BOR reset Level",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "WDG_SW": {
+                    "description": "WDG_SW User option bytes",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "nRST_STOP": {
+                    "description": "nRST_STOP User option\n              bytes",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "nRST_STDBY": {
+                    "description": "nRST_STDBY User option\n              bytes",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RDP": {
+                    "description": "Read protect",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "nWRP": {
+                    "description": "Not write protect",
+                    "offset": 16,
+                    "size": 12
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USART6": {
+        "description": "Universal synchronous asynchronous receiver\n      transmitter",
+        "children": {
+          "registers": {
+            "SR": {
+              "description": "Status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 12582912,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "CTS flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LBD": {
+                    "description": "LIN break detection flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXE": {
+                    "description": "Transmit data register\n              empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TC": {
+                    "description": "Transmission complete",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNE": {
+                    "description": "Read data register not\n              empty",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLE": {
+                    "description": "IDLE line detected",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ORE": {
+                    "description": "Overrun error",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NF": {
+                    "description": "Noise detected flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FE": {
+                    "description": "Framing error",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PE": {
+                    "description": "Parity error",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "Data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data value",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "BRR": {
+              "description": "Baud rate register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIV_Mantissa": {
+                    "description": "mantissa of USARTDIV",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "DIV_Fraction": {
+                    "description": "fraction of USARTDIV",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "Control register 1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVER8": {
+                    "description": "Oversampling mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "UE": {
+                    "description": "USART enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "M": {
+                    "description": "Word length",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAKE": {
+                    "description": "Wakeup method",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PCE": {
+                    "description": "Parity control enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PS": {
+                    "description": "Parity selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PEIE": {
+                    "description": "PE interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXEIE": {
+                    "description": "TXE interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transmission complete interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RXNE interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLEIE": {
+                    "description": "IDLE interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TE": {
+                    "description": "Transmitter enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RE": {
+                    "description": "Receiver enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RWU": {
+                    "description": "Receiver wakeup",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SBK": {
+                    "description": "Send break",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "Control register 2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LINEN": {
+                    "description": "LIN mode enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "STOP bits",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CLKEN": {
+                    "description": "Clock enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CPOL": {
+                    "description": "Clock polarity",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CPHA": {
+                    "description": "Clock phase",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LBCL": {
+                    "description": "Last bit clock pulse",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LBDIE": {
+                    "description": "LIN break detection interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LBDL": {
+                    "description": "lin break detection length",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADD": {
+                    "description": "Address of the USART node",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR3": {
+              "description": "Control register 3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ONEBIT": {
+                    "description": "One sample bit method\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CTSIE": {
+                    "description": "CTS interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CTSE": {
+                    "description": "CTS enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RTSE": {
+                    "description": "RTS enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DMAT": {
+                    "description": "DMA enable transmitter",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DMAR": {
+                    "description": "DMA enable receiver",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SCEN": {
+                    "description": "Smartcard mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NACK": {
+                    "description": "Smartcard NACK enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HDSEL": {
+                    "description": "Half-duplex selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IRLP": {
+                    "description": "IrDA low-power",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IrDA mode enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GTPR": {
+              "description": "Guard time and prescaler\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GT": {
+                    "description": "Guard time value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM6": {
+        "description": "Basic timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Low Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CAN1": {
+        "description": "Controller area network",
+        "children": {
+          "registers": {
+            "MCR": {
+              "description": "master control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 65538,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBF": {
+                    "description": "DBF",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "RESET",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TTCM": {
+                    "description": "TTCM",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ABOM": {
+                    "description": "ABOM",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AWUM": {
+                    "description": "AWUM",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NART": {
+                    "description": "NART",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RFLM": {
+                    "description": "RFLM",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXFP": {
+                    "description": "TXFP",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLEEP": {
+                    "description": "SLEEP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INRQ": {
+                    "description": "INRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MSR": {
+              "description": "master status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 3074,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX": {
+                    "description": "RX",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SAMP": {
+                    "description": "SAMP",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXM": {
+                    "description": "RXM",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXM": {
+                    "description": "TXM",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAKI": {
+                    "description": "SLAKI",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "WKUI": {
+                    "description": "WKUI",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERRI": {
+                    "description": "ERRI",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLAK": {
+                    "description": "SLAK",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INAK": {
+                    "description": "INAK",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TSR": {
+              "description": "transmit status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 469762048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOW2": {
+                    "description": "Lowest priority flag for mailbox\n              2",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOW1": {
+                    "description": "Lowest priority flag for mailbox\n              1",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOW0": {
+                    "description": "Lowest priority flag for mailbox\n              0",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME2": {
+                    "description": "Lowest priority flag for mailbox\n              2",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME1": {
+                    "description": "Lowest priority flag for mailbox\n              1",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME0": {
+                    "description": "Lowest priority flag for mailbox\n              0",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CODE": {
+                    "description": "CODE",
+                    "offset": 24,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "ABRQ2": {
+                    "description": "ABRQ2",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TERR2": {
+                    "description": "TERR2",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ALST2": {
+                    "description": "ALST2",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TXOK2": {
+                    "description": "TXOK2",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RQCP2": {
+                    "description": "RQCP2",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ABRQ1": {
+                    "description": "ABRQ1",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TERR1": {
+                    "description": "TERR1",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ALST1": {
+                    "description": "ALST1",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TXOK1": {
+                    "description": "TXOK1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RQCP1": {
+                    "description": "RQCP1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ABRQ0": {
+                    "description": "ABRQ0",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TERR0": {
+                    "description": "TERR0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ALST0": {
+                    "description": "ALST0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXOK0": {
+                    "description": "TXOK0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RQCP0": {
+                    "description": "RQCP0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RF0R": {
+              "description": "receive FIFO 0 register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFOM0": {
+                    "description": "RFOM0",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FOVR0": {
+                    "description": "FOVR0",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FULL0": {
+                    "description": "FULL0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FMP0": {
+                    "description": "FMP0",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RF1R": {
+              "description": "receive FIFO 1 register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFOM1": {
+                    "description": "RFOM1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FOVR1": {
+                    "description": "FOVR1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FULL1": {
+                    "description": "FULL1",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FMP1": {
+                    "description": "FMP1",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "interrupt enable register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLKIE": {
+                    "description": "SLKIE",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WKUIE": {
+                    "description": "WKUIE",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "ERRIE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LECIE": {
+                    "description": "LECIE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BOFIE": {
+                    "description": "BOFIE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPVIE": {
+                    "description": "EPVIE",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EWGIE": {
+                    "description": "EWGIE",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FOVIE1": {
+                    "description": "FOVIE1",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FFIE1": {
+                    "description": "FFIE1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FMPIE1": {
+                    "description": "FMPIE1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FOVIE0": {
+                    "description": "FOVIE0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FFIE0": {
+                    "description": "FFIE0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FMPIE0": {
+                    "description": "FMPIE0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TMEIE": {
+                    "description": "TMEIE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ESR": {
+              "description": "interrupt enable register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REC": {
+                    "description": "REC",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "TEC": {
+                    "description": "TEC",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "LEC": {
+                    "description": "LEC",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "BOFF": {
+                    "description": "BOFF",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPVF": {
+                    "description": "EPVF",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EWGF": {
+                    "description": "EWGF",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "BTR": {
+              "description": "bit timing register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SILM": {
+                    "description": "SILM",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LBKM": {
+                    "description": "LBKM",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SJW": {
+                    "description": "SJW",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "TS2": {
+                    "description": "TS2",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "TS1": {
+                    "description": "TS1",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "BRP": {
+                    "description": "BRP",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "TI0R": {
+              "description": "TX mailbox identifier register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXRQ": {
+                    "description": "TXRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TDT0R": {
+              "description": "mailbox data length control and time stamp\n          register",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TGT": {
+                    "description": "TGT",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TDL0R": {
+              "description": "mailbox data low register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TDH0R": {
+              "description": "mailbox data high register",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TI1R": {
+              "description": "mailbox identifier register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXRQ": {
+                    "description": "TXRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TDT1R": {
+              "description": "mailbox data length control and time stamp\n          register",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TGT": {
+                    "description": "TGT",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TDL1R": {
+              "description": "mailbox data low register",
+              "offset": 408,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TDH1R": {
+              "description": "mailbox data high register",
+              "offset": 412,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TI2R": {
+              "description": "mailbox identifier register",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXRQ": {
+                    "description": "TXRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TDT2R": {
+              "description": "mailbox data length control and time stamp\n          register",
+              "offset": 420,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TGT": {
+                    "description": "TGT",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TDL2R": {
+              "description": "mailbox data low register",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TDH2R": {
+              "description": "mailbox data high register",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RI0R": {
+              "description": "receive FIFO mailbox identifier\n          register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RDT0R": {
+              "description": "mailbox data high register",
+              "offset": 436,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FMI": {
+                    "description": "FMI",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RDL0R": {
+              "description": "mailbox data high register",
+              "offset": 440,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RDH0R": {
+              "description": "receive FIFO mailbox data high\n          register",
+              "offset": 444,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RI1R": {
+              "description": "mailbox data high register",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RDT1R": {
+              "description": "mailbox data high register",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FMI": {
+                    "description": "FMI",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RDL1R": {
+              "description": "mailbox data high register",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RDH1R": {
+              "description": "mailbox data high register",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "FMR": {
+              "description": "filter master register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 706481665,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CAN2SB": {
+                    "description": "CAN2SB",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "FINIT": {
+                    "description": "FINIT",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FM1R": {
+              "description": "filter mode register",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FBM0": {
+                    "description": "Filter mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FBM1": {
+                    "description": "Filter mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FBM2": {
+                    "description": "Filter mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FBM3": {
+                    "description": "Filter mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FBM4": {
+                    "description": "Filter mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FBM5": {
+                    "description": "Filter mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FBM6": {
+                    "description": "Filter mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FBM7": {
+                    "description": "Filter mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FBM8": {
+                    "description": "Filter mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FBM9": {
+                    "description": "Filter mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FBM10": {
+                    "description": "Filter mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FBM11": {
+                    "description": "Filter mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FBM12": {
+                    "description": "Filter mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FBM13": {
+                    "description": "Filter mode",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FBM14": {
+                    "description": "Filter mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FBM15": {
+                    "description": "Filter mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FBM16": {
+                    "description": "Filter mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FBM17": {
+                    "description": "Filter mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FBM18": {
+                    "description": "Filter mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FBM19": {
+                    "description": "Filter mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FBM20": {
+                    "description": "Filter mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FBM21": {
+                    "description": "Filter mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FBM22": {
+                    "description": "Filter mode",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FBM23": {
+                    "description": "Filter mode",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FBM24": {
+                    "description": "Filter mode",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FBM25": {
+                    "description": "Filter mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FBM26": {
+                    "description": "Filter mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FBM27": {
+                    "description": "Filter mode",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS1R": {
+              "description": "filter scale register",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSC0": {
+                    "description": "Filter scale configuration",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FSC1": {
+                    "description": "Filter scale configuration",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FSC2": {
+                    "description": "Filter scale configuration",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FSC3": {
+                    "description": "Filter scale configuration",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FSC4": {
+                    "description": "Filter scale configuration",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FSC5": {
+                    "description": "Filter scale configuration",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FSC6": {
+                    "description": "Filter scale configuration",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FSC7": {
+                    "description": "Filter scale configuration",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FSC8": {
+                    "description": "Filter scale configuration",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FSC9": {
+                    "description": "Filter scale configuration",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FSC10": {
+                    "description": "Filter scale configuration",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FSC11": {
+                    "description": "Filter scale configuration",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FSC12": {
+                    "description": "Filter scale configuration",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FSC13": {
+                    "description": "Filter scale configuration",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FSC14": {
+                    "description": "Filter scale configuration",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FSC15": {
+                    "description": "Filter scale configuration",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FSC16": {
+                    "description": "Filter scale configuration",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FSC17": {
+                    "description": "Filter scale configuration",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FSC18": {
+                    "description": "Filter scale configuration",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FSC19": {
+                    "description": "Filter scale configuration",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FSC20": {
+                    "description": "Filter scale configuration",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FSC21": {
+                    "description": "Filter scale configuration",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FSC22": {
+                    "description": "Filter scale configuration",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FSC23": {
+                    "description": "Filter scale configuration",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FSC24": {
+                    "description": "Filter scale configuration",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FSC25": {
+                    "description": "Filter scale configuration",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FSC26": {
+                    "description": "Filter scale configuration",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FSC27": {
+                    "description": "Filter scale configuration",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FFA1R": {
+              "description": "filter FIFO assignment\n          register",
+              "offset": 532,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FFA0": {
+                    "description": "Filter FIFO assignment for filter\n              0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FFA1": {
+                    "description": "Filter FIFO assignment for filter\n              1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FFA2": {
+                    "description": "Filter FIFO assignment for filter\n              2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FFA3": {
+                    "description": "Filter FIFO assignment for filter\n              3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FFA4": {
+                    "description": "Filter FIFO assignment for filter\n              4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FFA5": {
+                    "description": "Filter FIFO assignment for filter\n              5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FFA6": {
+                    "description": "Filter FIFO assignment for filter\n              6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FFA7": {
+                    "description": "Filter FIFO assignment for filter\n              7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FFA8": {
+                    "description": "Filter FIFO assignment for filter\n              8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FFA9": {
+                    "description": "Filter FIFO assignment for filter\n              9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FFA10": {
+                    "description": "Filter FIFO assignment for filter\n              10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FFA11": {
+                    "description": "Filter FIFO assignment for filter\n              11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FFA12": {
+                    "description": "Filter FIFO assignment for filter\n              12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FFA13": {
+                    "description": "Filter FIFO assignment for filter\n              13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FFA14": {
+                    "description": "Filter FIFO assignment for filter\n              14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FFA15": {
+                    "description": "Filter FIFO assignment for filter\n              15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FFA16": {
+                    "description": "Filter FIFO assignment for filter\n              16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FFA17": {
+                    "description": "Filter FIFO assignment for filter\n              17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FFA18": {
+                    "description": "Filter FIFO assignment for filter\n              18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FFA19": {
+                    "description": "Filter FIFO assignment for filter\n              19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FFA20": {
+                    "description": "Filter FIFO assignment for filter\n              20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FFA21": {
+                    "description": "Filter FIFO assignment for filter\n              21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FFA22": {
+                    "description": "Filter FIFO assignment for filter\n              22",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FFA23": {
+                    "description": "Filter FIFO assignment for filter\n              23",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FFA24": {
+                    "description": "Filter FIFO assignment for filter\n              24",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FFA25": {
+                    "description": "Filter FIFO assignment for filter\n              25",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FFA26": {
+                    "description": "Filter FIFO assignment for filter\n              26",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FFA27": {
+                    "description": "Filter FIFO assignment for filter\n              27",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FA1R": {
+              "description": "filter activation register",
+              "offset": 540,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FACT0": {
+                    "description": "Filter active",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FACT1": {
+                    "description": "Filter active",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FACT2": {
+                    "description": "Filter active",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FACT3": {
+                    "description": "Filter active",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FACT4": {
+                    "description": "Filter active",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FACT5": {
+                    "description": "Filter active",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FACT6": {
+                    "description": "Filter active",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FACT7": {
+                    "description": "Filter active",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FACT8": {
+                    "description": "Filter active",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACT9": {
+                    "description": "Filter active",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FACT10": {
+                    "description": "Filter active",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FACT11": {
+                    "description": "Filter active",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FACT12": {
+                    "description": "Filter active",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FACT13": {
+                    "description": "Filter active",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FACT14": {
+                    "description": "Filter active",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FACT15": {
+                    "description": "Filter active",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FACT16": {
+                    "description": "Filter active",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FACT17": {
+                    "description": "Filter active",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FACT18": {
+                    "description": "Filter active",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FACT19": {
+                    "description": "Filter active",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FACT20": {
+                    "description": "Filter active",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FACT21": {
+                    "description": "Filter active",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FACT22": {
+                    "description": "Filter active",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FACT23": {
+                    "description": "Filter active",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FACT24": {
+                    "description": "Filter active",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FACT25": {
+                    "description": "Filter active",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FACT26": {
+                    "description": "Filter active",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FACT27": {
+                    "description": "Filter active",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F0R1": {
+              "description": "Filter bank 0 register 1",
+              "offset": 576,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F0R2": {
+              "description": "Filter bank 0 register 2",
+              "offset": 580,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F1R1": {
+              "description": "Filter bank 1 register 1",
+              "offset": 584,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F1R2": {
+              "description": "Filter bank 1 register 2",
+              "offset": 588,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F2R1": {
+              "description": "Filter bank 2 register 1",
+              "offset": 592,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F2R2": {
+              "description": "Filter bank 2 register 2",
+              "offset": 596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F3R1": {
+              "description": "Filter bank 3 register 1",
+              "offset": 600,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F3R2": {
+              "description": "Filter bank 3 register 2",
+              "offset": 604,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F4R1": {
+              "description": "Filter bank 4 register 1",
+              "offset": 608,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F4R2": {
+              "description": "Filter bank 4 register 2",
+              "offset": 612,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F5R1": {
+              "description": "Filter bank 5 register 1",
+              "offset": 616,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F5R2": {
+              "description": "Filter bank 5 register 2",
+              "offset": 620,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F6R1": {
+              "description": "Filter bank 6 register 1",
+              "offset": 624,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F6R2": {
+              "description": "Filter bank 6 register 2",
+              "offset": 628,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F7R1": {
+              "description": "Filter bank 7 register 1",
+              "offset": 632,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F7R2": {
+              "description": "Filter bank 7 register 2",
+              "offset": 636,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F8R1": {
+              "description": "Filter bank 8 register 1",
+              "offset": 640,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F8R2": {
+              "description": "Filter bank 8 register 2",
+              "offset": 644,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F9R1": {
+              "description": "Filter bank 9 register 1",
+              "offset": 648,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F9R2": {
+              "description": "Filter bank 9 register 2",
+              "offset": 652,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F10R1": {
+              "description": "Filter bank 10 register 1",
+              "offset": 656,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F10R2": {
+              "description": "Filter bank 10 register 2",
+              "offset": 660,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F11R1": {
+              "description": "Filter bank 11 register 1",
+              "offset": 664,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F11R2": {
+              "description": "Filter bank 11 register 2",
+              "offset": 668,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F12R1": {
+              "description": "Filter bank 4 register 1",
+              "offset": 672,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F12R2": {
+              "description": "Filter bank 12 register 2",
+              "offset": 676,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F13R1": {
+              "description": "Filter bank 13 register 1",
+              "offset": 680,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F13R2": {
+              "description": "Filter bank 13 register 2",
+              "offset": 684,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F14R1": {
+              "description": "Filter bank 14 register 1",
+              "offset": 688,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F14R2": {
+              "description": "Filter bank 14 register 2",
+              "offset": 692,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F15R1": {
+              "description": "Filter bank 15 register 1",
+              "offset": 696,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F15R2": {
+              "description": "Filter bank 15 register 2",
+              "offset": 700,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F16R1": {
+              "description": "Filter bank 16 register 1",
+              "offset": 704,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F16R2": {
+              "description": "Filter bank 16 register 2",
+              "offset": 708,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F17R1": {
+              "description": "Filter bank 17 register 1",
+              "offset": 712,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F17R2": {
+              "description": "Filter bank 17 register 2",
+              "offset": 716,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F18R1": {
+              "description": "Filter bank 18 register 1",
+              "offset": 720,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F18R2": {
+              "description": "Filter bank 18 register 2",
+              "offset": 724,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F19R1": {
+              "description": "Filter bank 19 register 1",
+              "offset": 728,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F19R2": {
+              "description": "Filter bank 19 register 2",
+              "offset": 732,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F20R1": {
+              "description": "Filter bank 20 register 1",
+              "offset": 736,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F20R2": {
+              "description": "Filter bank 20 register 2",
+              "offset": 740,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F21R1": {
+              "description": "Filter bank 21 register 1",
+              "offset": 744,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F21R2": {
+              "description": "Filter bank 21 register 2",
+              "offset": 748,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F22R1": {
+              "description": "Filter bank 22 register 1",
+              "offset": 752,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F22R2": {
+              "description": "Filter bank 22 register 2",
+              "offset": 756,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F23R1": {
+              "description": "Filter bank 23 register 1",
+              "offset": 760,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F23R2": {
+              "description": "Filter bank 23 register 2",
+              "offset": 764,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F24R1": {
+              "description": "Filter bank 24 register 1",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F24R2": {
+              "description": "Filter bank 24 register 2",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F25R1": {
+              "description": "Filter bank 25 register 1",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F25R2": {
+              "description": "Filter bank 25 register 2",
+              "offset": 780,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F26R1": {
+              "description": "Filter bank 26 register 1",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F26R2": {
+              "description": "Filter bank 26 register 2",
+              "offset": 788,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F27R1": {
+              "description": "Filter bank 27 register 1",
+              "offset": 792,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F27R2": {
+              "description": "Filter bank 27 register 2",
+              "offset": 796,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_PWRCLK": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_PCGCCTL": {
+              "description": "OTG_FS power and clock gating control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STPPCLK": {
+                    "description": "Stop PHY clock",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "GATEHCLK": {
+                    "description": "Gate HCLK",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PHYSUSP": {
+                    "description": "PHY Suspended",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DAC": {
+        "description": "Digital-to-analog converter",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAUDRIE2": {
+                    "description": "DAC channel2 DMA underrun interrupt\n              enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DMAEN2": {
+                    "description": "DAC channel2 DMA enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "MAMP2": {
+                    "description": "DAC channel2 mask/amplitude\n              selector",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "WAVE2": {
+                    "description": "DAC channel2 noise/triangle wave\n              generation enable",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "TSEL2": {
+                    "description": "DAC channel2 trigger\n              selection",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "TEN2": {
+                    "description": "DAC channel2 trigger\n              enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BOFF2": {
+                    "description": "DAC channel2 output buffer\n              disable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EN2": {
+                    "description": "DAC channel2 enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DMAUDRIE1": {
+                    "description": "DAC channel1 DMA Underrun Interrupt\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "DMAEN1": {
+                    "description": "DAC channel1 DMA enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MAMP1": {
+                    "description": "DAC channel1 mask/amplitude\n              selector",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "WAVE1": {
+                    "description": "DAC channel1 noise/triangle wave\n              generation enable",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "TSEL1": {
+                    "description": "DAC channel1 trigger\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "TEN1": {
+                    "description": "DAC channel1 trigger\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BOFF1": {
+                    "description": "DAC channel1 output buffer\n              disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN1": {
+                    "description": "DAC channel1 enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWTRIGR": {
+              "description": "software trigger register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "SWTRIG2": {
+                    "description": "DAC channel2 software\n              trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SWTRIG1": {
+                    "description": "DAC channel1 software\n              trigger",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DHR12R1": {
+              "description": "channel1 12-bit right-aligned data holding\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12L1": {
+              "description": "channel1 12-bit left aligned data holding\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8R1": {
+              "description": "channel1 8-bit right aligned data holding\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DHR12R2": {
+              "description": "channel2 12-bit right aligned data holding\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12L2": {
+              "description": "channel2 12-bit left aligned data holding\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8R2": {
+              "description": "channel2 8-bit right-aligned data holding\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DHR12RD": {
+              "description": "Dual DAC 12-bit right-aligned data holding\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit right-aligned\n              data",
+                    "offset": 16,
+                    "size": 12
+                  },
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12LD": {
+              "description": "DUAL DAC 12-bit left aligned data holding\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit left-aligned\n              data",
+                    "offset": 20,
+                    "size": 12
+                  },
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8RD": {
+              "description": "DUAL DAC 8-bit right aligned data holding\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 8-bit right-aligned\n              data",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DACC1DHR": {
+                    "description": "DAC channel1 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DOR1": {
+              "description": "channel1 data output register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DACC1DOR": {
+                    "description": "DAC channel1 data output",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DOR2": {
+              "description": "channel2 data output register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DACC2DOR": {
+                    "description": "DAC channel2 data output",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAUDR2": {
+                    "description": "DAC channel2 DMA underrun\n              flag",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DMAUDR1": {
+                    "description": "DAC channel1 DMA underrun\n              flag",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PWR": {
+        "description": "Power control",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "power control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FPDS": {
+                    "description": "Flash power down in Stop\n              mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DBP": {
+                    "description": "Disable backup domain write\n              protection",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PLS": {
+                    "description": "PVD level selection",
+                    "offset": 5,
+                    "size": 3
+                  },
+                  "PVDE": {
+                    "description": "Power voltage detector\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CSBF": {
+                    "description": "Clear standby flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CWUF": {
+                    "description": "Clear wakeup flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PDDS": {
+                    "description": "Power down deepsleep",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LPDS": {
+                    "description": "Low-power deep sleep",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CSR": {
+              "description": "power control/status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WUF": {
+                    "description": "Wakeup flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SBF": {
+                    "description": "Standby flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PVDO": {
+                    "description": "PVD output",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BRR": {
+                    "description": "Backup regulator ready",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EWUP": {
+                    "description": "Enable WKUP pin",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BRE": {
+                    "description": "Backup regulator enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "VOSRDY": {
+                    "description": "Regulator voltage scaling output\n              selection ready bit",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2C3": {
+        "description": "Inter-integrated circuit",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "Control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWRST": {
+                    "description": "Software reset",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ALERT": {
+                    "description": "SMBus alert",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PEC": {
+                    "description": "Packet error checking",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "POS": {
+                    "description": "Acknowledge/PEC Position (for data\n              reception)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "Acknowledge enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "Stop generation",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "START": {
+                    "description": "Start generation",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "NOSTRETCH": {
+                    "description": "Clock stretching disable (Slave\n              mode)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ENGC": {
+                    "description": "General call enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ENPEC": {
+                    "description": "PEC enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ENARP": {
+                    "description": "ARP enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SMBTYPE": {
+                    "description": "SMBus type",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SMBUS": {
+                    "description": "SMBus mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PE": {
+                    "description": "Peripheral enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "Control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LAST": {
+                    "description": "DMA last transfer",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DMAEN": {
+                    "description": "DMA requests enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ITBUFEN": {
+                    "description": "Buffer interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ITEVTEN": {
+                    "description": "Event interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ITERREN": {
+                    "description": "Error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FREQ": {
+                    "description": "Peripheral clock frequency",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "OAR1": {
+              "description": "Own address register 1",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDMODE": {
+                    "description": "Addressing mode (slave\n              mode)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ADD10": {
+                    "description": "Interface address",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ADD7": {
+                    "description": "Interface address",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "ADD0": {
+                    "description": "Interface address",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OAR2": {
+              "description": "Own address register 2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADD2": {
+                    "description": "Interface address",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "ENDUAL": {
+                    "description": "Dual addressing mode\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "Data register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "8-bit data register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SR1": {
+              "description": "Status register 1",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMBALERT": {
+                    "description": "SMBus alert",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TIMEOUT": {
+                    "description": "Timeout or Tlow error",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PECERR": {
+                    "description": "PEC Error in reception",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OVR": {
+                    "description": "Overrun/Underrun",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AF": {
+                    "description": "Acknowledge failure",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ARLO": {
+                    "description": "Arbitration lost (master\n              mode)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Bus error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TxE": {
+                    "description": "Data register empty\n              (transmitters)",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RxNE": {
+                    "description": "Data register not empty\n              (receivers)",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STOPF": {
+                    "description": "Stop detection (slave\n              mode)",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ADD10": {
+                    "description": "10-bit header sent (Master\n              mode)",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BTF": {
+                    "description": "Byte transfer finished",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ADDR": {
+                    "description": "Address sent (master mode)/matched\n              (slave mode)",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SB": {
+                    "description": "Start bit (Master mode)",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SR2": {
+              "description": "Status register 2",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PEC": {
+                    "description": "acket error checking\n              register",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DUALF": {
+                    "description": "Dual flag (Slave mode)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SMBHOST": {
+                    "description": "SMBus host header (Slave\n              mode)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SMBDEFAULT": {
+                    "description": "SMBus device default address (Slave\n              mode)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GENCALL": {
+                    "description": "General call address (Slave\n              mode)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TRA": {
+                    "description": "Transmitter/receiver",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "Bus busy",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MSL": {
+                    "description": "Master/slave",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "Clock control register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "F_S": {
+                    "description": "I2C master mode selection",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "DUTY": {
+                    "description": "Fast mode duty cycle",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CCR": {
+                    "description": "Clock control register in Fast/Standard\n              mode (Master mode)",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "TRISE": {
+              "description": "TRISE register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRISE": {
+                    "description": "Maximum rise time in Fast/Standard mode\n              (Master mode)",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_DEVICE": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_DCFG": {
+              "description": "OTG_FS device configuration register\n          (OTG_FS_DCFG)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 35651584,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DSPD": {
+                    "description": "Device speed",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "NZLSOHSK": {
+                    "description": "Non-zero-length status OUT\n              handshake",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 4,
+                    "size": 7
+                  },
+                  "PFIVL": {
+                    "description": "Periodic frame interval",
+                    "offset": 11,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_DCTL": {
+              "description": "OTG_FS device control register\n          (OTG_FS_DCTL)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWUSIG": {
+                    "description": "Remote wakeup signaling",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SDIS": {
+                    "description": "Soft disconnect",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GINSTS": {
+                    "description": "Global IN NAK status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GONSTS": {
+                    "description": "Global OUT NAK status",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TCTL": {
+                    "description": "Test control",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SGINAK": {
+                    "description": "Set global IN NAK",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CGINAK": {
+                    "description": "Clear global IN NAK",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SGONAK": {
+                    "description": "Set global OUT NAK",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CGONAK": {
+                    "description": "Clear global OUT NAK",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "POPRGDNE": {
+                    "description": "Power-on programming done",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_DSTS": {
+              "description": "OTG_FS device status register\n          (OTG_FS_DSTS)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SUSPSTS": {
+                    "description": "Suspend status",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ENUMSPD": {
+                    "description": "Enumerated speed",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "EERR": {
+                    "description": "Erratic error",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FNSOF": {
+                    "description": "Frame number of the received\n              SOF",
+                    "offset": 8,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "FS_DIEPMSK": {
+              "description": "OTG_FS device IN endpoint common interrupt\n          mask register (OTG_FS_DIEPMSK)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOM": {
+                    "description": "Timeout condition mask (Non-isochronous\n              endpoints)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFEMSK": {
+                    "description": "IN token received when TxFIFO empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNMM": {
+                    "description": "IN token received with EP mismatch\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INEPNEM": {
+                    "description": "IN endpoint NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_DOEPMSK": {
+              "description": "OTG_FS device OUT endpoint common interrupt\n          mask register (OTG_FS_DOEPMSK)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUPM": {
+                    "description": "SETUP phase done mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDM": {
+                    "description": "OUT token received when endpoint\n              disabled mask",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_DAINT": {
+              "description": "OTG_FS device all endpoints interrupt\n          register (OTG_FS_DAINT)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IEPINT": {
+                    "description": "IN endpoint interrupt bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt\n              bits",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DAINTMSK": {
+              "description": "OTG_FS all endpoints interrupt mask register\n          (OTG_FS_DAINTMSK)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEPM": {
+                    "description": "IN EP interrupt mask bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt\n              bits",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DVBUSDIS": {
+              "description": "OTG_FS device VBUS discharge time\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 6103,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VBUSDT": {
+                    "description": "Device VBUS discharge time",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DVBUSPULSE": {
+              "description": "OTG_FS device VBUS pulsing time\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 1464,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DVBUSP": {
+                    "description": "Device VBUS pulsing time",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DIEPEMPMSK": {
+              "description": "OTG_FS device IN endpoint FIFO empty\n          interrupt mask register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXFEM": {
+                    "description": "IN EP Tx FIFO empty interrupt mask\n              bits",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPCTL0": {
+              "description": "OTG_FS device control IN endpoint 0 control\n          register (OTG_FS_DIEPCTL0)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "STALL": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DIEPCTL1": {
+              "description": "OTG device endpoint-1 control\n          register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM_SD1PID": {
+                    "description": "SODDFRM/SD1PID",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "TXFNUM",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEPCTL2": {
+              "description": "OTG device endpoint-2 control\n          register",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "TXFNUM",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEPCTL3": {
+              "description": "OTG device endpoint-3 control\n          register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "TXFNUM",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEPCTL0": {
+              "description": "device endpoint-0 control\n          register",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DOEPCTL1": {
+              "description": "device endpoint-1 control\n          register",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEPCTL2": {
+              "description": "device endpoint-2 control\n          register",
+              "offset": 832,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEPCTL3": {
+              "description": "device endpoint-3 control\n          register",
+              "offset": 864,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEPINT0": {
+              "description": "device endpoint-x interrupt\n          register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPINT1": {
+              "description": "device endpoint-1 interrupt\n          register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPINT2": {
+              "description": "device endpoint-2 interrupt\n          register",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPINT3": {
+              "description": "device endpoint-3 interrupt\n          register",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT0": {
+              "description": "device endpoint-0 interrupt\n          register",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT1": {
+              "description": "device endpoint-1 interrupt\n          register",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT2": {
+              "description": "device endpoint-2 interrupt\n          register",
+              "offset": 840,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT3": {
+              "description": "device endpoint-3 interrupt\n          register",
+              "offset": 872,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ0": {
+              "description": "device endpoint-0 transfer size\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 2
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ0": {
+              "description": "device OUT endpoint-0 transfer size\n          register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STUPCNT": {
+                    "description": "SETUP packet count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ1": {
+              "description": "device endpoint-1 transfer size\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ2": {
+              "description": "device endpoint-2 transfer size\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ3": {
+              "description": "device endpoint-3 transfer size\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DTXFSTS0": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DTXFSTS1": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DTXFSTS2": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DTXFSTS3": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ1": {
+              "description": "device OUT endpoint-1 transfer size\n          register",
+              "offset": 816,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ2": {
+              "description": "device OUT endpoint-2 transfer size\n          register",
+              "offset": 848,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ3": {
+              "description": "device OUT endpoint-3 transfer size\n          register",
+              "offset": 880,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_HOST": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_HCFG": {
+              "description": "OTG_FS host configuration register\n          (OTG_FS_HCFG)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSLSPCS": {
+                    "description": "FS/LS PHY clock select",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "FSLSS": {
+                    "description": "FS- and LS-only support",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "HFIR": {
+              "description": "OTG_FS Host frame interval\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 60000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRIVL": {
+                    "description": "Frame interval",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_HFNUM": {
+              "description": "OTG_FS host frame number/frame time\n          remaining register (OTG_FS_HFNUM)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 16383,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FRNUM": {
+                    "description": "Frame number",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "FTREM": {
+                    "description": "Frame time remaining",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_HPTXSTS": {
+              "description": "OTG_FS_Host periodic transmit FIFO/queue\n          status register (OTG_FS_HPTXSTS)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 524544,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTXFSAVL": {
+                    "description": "Periodic transmit data FIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PTXQSAV": {
+                    "description": "Periodic transmit request queue space\n              available",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "PTXQTOP": {
+                    "description": "Top of the periodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "HAINT": {
+              "description": "OTG_FS Host all channels interrupt\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HAINT": {
+                    "description": "Channel interrupts",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "HAINTMSK": {
+              "description": "OTG_FS host all channels interrupt mask\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HAINTM": {
+                    "description": "Channel interrupt mask",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_HPRT": {
+              "description": "OTG_FS host port control and status register\n          (OTG_FS_HPRT)",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCSTS": {
+                    "description": "Port connect status",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PCDET": {
+                    "description": "Port connect detected",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PENA": {
+                    "description": "Port enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PENCHNG": {
+                    "description": "Port enable/disable change",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "POCA": {
+                    "description": "Port overcurrent active",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "POCCHNG": {
+                    "description": "Port overcurrent change",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PRES": {
+                    "description": "Port resume",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PSUSP": {
+                    "description": "Port suspend",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PRST": {
+                    "description": "Port reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PLSTS": {
+                    "description": "Port line status",
+                    "offset": 10,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PPWR": {
+                    "description": "Port power",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PTCTL": {
+                    "description": "Port test control",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "PSPD": {
+                    "description": "Port speed",
+                    "offset": 17,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR0": {
+              "description": "OTG_FS host channel-0 characteristics\n          register (OTG_FS_HCCHAR0)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR1": {
+              "description": "OTG_FS host channel-1 characteristics\n          register (OTG_FS_HCCHAR1)",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR2": {
+              "description": "OTG_FS host channel-2 characteristics\n          register (OTG_FS_HCCHAR2)",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR3": {
+              "description": "OTG_FS host channel-3 characteristics\n          register (OTG_FS_HCCHAR3)",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR4": {
+              "description": "OTG_FS host channel-4 characteristics\n          register (OTG_FS_HCCHAR4)",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR5": {
+              "description": "OTG_FS host channel-5 characteristics\n          register (OTG_FS_HCCHAR5)",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR6": {
+              "description": "OTG_FS host channel-6 characteristics\n          register (OTG_FS_HCCHAR6)",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR7": {
+              "description": "OTG_FS host channel-7 characteristics\n          register (OTG_FS_HCCHAR7)",
+              "offset": 480,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT0": {
+              "description": "OTG_FS host channel-0 interrupt register\n          (OTG_FS_HCINT0)",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT1": {
+              "description": "OTG_FS host channel-1 interrupt register\n          (OTG_FS_HCINT1)",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT2": {
+              "description": "OTG_FS host channel-2 interrupt register\n          (OTG_FS_HCINT2)",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT3": {
+              "description": "OTG_FS host channel-3 interrupt register\n          (OTG_FS_HCINT3)",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT4": {
+              "description": "OTG_FS host channel-4 interrupt register\n          (OTG_FS_HCINT4)",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT5": {
+              "description": "OTG_FS host channel-5 interrupt register\n          (OTG_FS_HCINT5)",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT6": {
+              "description": "OTG_FS host channel-6 interrupt register\n          (OTG_FS_HCINT6)",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT7": {
+              "description": "OTG_FS host channel-7 interrupt register\n          (OTG_FS_HCINT7)",
+              "offset": 488,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK0": {
+              "description": "OTG_FS host channel-0 mask register\n          (OTG_FS_HCINTMSK0)",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK1": {
+              "description": "OTG_FS host channel-1 mask register\n          (OTG_FS_HCINTMSK1)",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK2": {
+              "description": "OTG_FS host channel-2 mask register\n          (OTG_FS_HCINTMSK2)",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK3": {
+              "description": "OTG_FS host channel-3 mask register\n          (OTG_FS_HCINTMSK3)",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK4": {
+              "description": "OTG_FS host channel-4 mask register\n          (OTG_FS_HCINTMSK4)",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK5": {
+              "description": "OTG_FS host channel-5 mask register\n          (OTG_FS_HCINTMSK5)",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK6": {
+              "description": "OTG_FS host channel-6 mask register\n          (OTG_FS_HCINTMSK6)",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK7": {
+              "description": "OTG_FS host channel-7 mask register\n          (OTG_FS_HCINTMSK7)",
+              "offset": 492,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ0": {
+              "description": "OTG_FS host channel-0 transfer size\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ1": {
+              "description": "OTG_FS host channel-1 transfer size\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ2": {
+              "description": "OTG_FS host channel-2 transfer size\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ3": {
+              "description": "OTG_FS host channel-3 transfer size\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ4": {
+              "description": "OTG_FS host channel-x transfer size\n          register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ5": {
+              "description": "OTG_FS host channel-5 transfer size\n          register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ6": {
+              "description": "OTG_FS host channel-6 transfer size\n          register",
+              "offset": 464,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ7": {
+              "description": "OTG_FS host channel-7 transfer size\n          register",
+              "offset": 496,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "IWDG": {
+        "description": "Independent watchdog",
+        "children": {
+          "registers": {
+            "KR": {
+              "description": "Key register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "KEY": {
+                    "description": "Key value (write only, read\n              0000h)",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PR": {
+              "description": "Prescaler register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PR": {
+                    "description": "Prescaler divider",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "RLR": {
+              "description": "Reload register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RL": {
+                    "description": "Watchdog counter reload\n              value",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RVU": {
+                    "description": "Watchdog counter reload value\n              update",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PVU": {
+                    "description": "Watchdog prescaler value\n              update",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "WWDG": {
+        "description": "Window watchdog",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "Control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 127,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDGA": {
+                    "description": "Activation bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "T": {
+                    "description": "7-bit counter (MSB to LSB)",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "CFR": {
+              "description": "Configuration register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 127,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EWI": {
+                    "description": "Early wakeup interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WDGTB1": {
+                    "description": "Timer base",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WDGTB0": {
+                    "description": "Timer base",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "W": {
+                    "description": "7-bit window value",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EWIF": {
+                    "description": "Early wakeup interrupt\n              flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RTC": {
+        "description": "Real-time clock",
+        "children": {
+          "registers": {
+            "TR": {
+              "description": "time register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PM": {
+                    "description": "AM/PM notation",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "HT": {
+                    "description": "Hour tens in BCD format",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "HU": {
+                    "description": "Hour units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "MNT": {
+                    "description": "Minute tens in BCD format",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "MNU": {
+                    "description": "Minute units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "ST": {
+                    "description": "Second tens in BCD format",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SU": {
+                    "description": "Second units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "date register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 8449,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "YT": {
+                    "description": "Year tens in BCD format",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "YU": {
+                    "description": "Year units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "WDU": {
+                    "description": "Week day units",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "MT": {
+                    "description": "Month tens in BCD format",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MU": {
+                    "description": "Month units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COE": {
+                    "description": "Calibration output enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "OSEL": {
+                    "description": "Output selection",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "POL": {
+                    "description": "Output polarity",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BKP": {
+                    "description": "Backup",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "SUB1H": {
+                    "description": "Subtract 1 hour (winter time\n              change)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ADD1H": {
+                    "description": "Add 1 hour (summer time\n              change)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TSIE": {
+                    "description": "Time-stamp interrupt\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "WUTIE": {
+                    "description": "Wakeup timer interrupt\n              enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ALRBIE": {
+                    "description": "Alarm B interrupt enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ALRAIE": {
+                    "description": "Alarm A interrupt enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TSE": {
+                    "description": "Time stamp enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WUTE": {
+                    "description": "Wakeup timer enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ALRBE": {
+                    "description": "Alarm B enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ALRAE": {
+                    "description": "Alarm A enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DCE": {
+                    "description": "Coarse digital calibration\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FMT": {
+                    "description": "Hour format",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "REFCKON": {
+                    "description": "Reference clock detection enable (50 or\n              60 Hz)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TSEDGE": {
+                    "description": "Time-stamp event active\n              edge",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "WCKSEL": {
+                    "description": "Wakeup clock selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "ISR": {
+              "description": "initialization and status\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ALRAWF": {
+                    "description": "Alarm A write flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ALRBWF": {
+                    "description": "Alarm B write flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WUTWF": {
+                    "description": "Wakeup timer write flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SHPF": {
+                    "description": "Shift operation pending",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "INITS": {
+                    "description": "Initialization status flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RSF": {
+                    "description": "Registers synchronization\n              flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INITF": {
+                    "description": "Initialization flag",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INIT": {
+                    "description": "Initialization mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ALRAF": {
+                    "description": "Alarm A flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ALRBF": {
+                    "description": "Alarm B flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WUTF": {
+                    "description": "Wakeup timer flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TSF": {
+                    "description": "Time-stamp flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TSOVF": {
+                    "description": "Time-stamp overflow flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TAMP1F": {
+                    "description": "Tamper detection flag",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TAMP2F": {
+                    "description": "TAMPER2 detection flag",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RECALPF": {
+                    "description": "Recalibration pending Flag",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PRER": {
+              "description": "prescaler register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 8323327,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PREDIV_A": {
+                    "description": "Asynchronous prescaler\n              factor",
+                    "offset": 16,
+                    "size": 7
+                  },
+                  "PREDIV_S": {
+                    "description": "Synchronous prescaler\n              factor",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "WUTR": {
+              "description": "wakeup timer register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WUT": {
+                    "description": "Wakeup auto-reload value\n              bits",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CALIBR": {
+              "description": "calibration register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCS": {
+                    "description": "Digital calibration sign",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DC": {
+                    "description": "Digital calibration",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "ALRMAR": {
+              "description": "alarm A register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MSK4": {
+                    "description": "Alarm A date mask",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "WDSEL": {
+                    "description": "Week day selection",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units or day in BCD\n              format",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "MSK3": {
+                    "description": "Alarm A hours mask",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PM": {
+                    "description": "AM/PM notation",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "HT": {
+                    "description": "Hour tens in BCD format",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "HU": {
+                    "description": "Hour units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "MSK2": {
+                    "description": "Alarm A minutes mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MNT": {
+                    "description": "Minute tens in BCD format",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "MNU": {
+                    "description": "Minute units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSK1": {
+                    "description": "Alarm A seconds mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ST": {
+                    "description": "Second tens in BCD format",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SU": {
+                    "description": "Second units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "ALRMBR": {
+              "description": "alarm B register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MSK4": {
+                    "description": "Alarm B date mask",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "WDSEL": {
+                    "description": "Week day selection",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units or day in BCD\n              format",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "MSK3": {
+                    "description": "Alarm B hours mask",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PM": {
+                    "description": "AM/PM notation",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "HT": {
+                    "description": "Hour tens in BCD format",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "HU": {
+                    "description": "Hour units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "MSK2": {
+                    "description": "Alarm B minutes mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MNT": {
+                    "description": "Minute tens in BCD format",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "MNU": {
+                    "description": "Minute units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSK1": {
+                    "description": "Alarm B seconds mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ST": {
+                    "description": "Second tens in BCD format",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SU": {
+                    "description": "Second units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "WPR": {
+              "description": "write protection register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "KEY": {
+                    "description": "Write protection key",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SSR": {
+              "description": "sub second register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SS": {
+                    "description": "Sub second value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SHIFTR": {
+              "description": "shift control register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "ADD1S": {
+                    "description": "Add one second",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "SUBFS": {
+                    "description": "Subtract a fraction of a\n              second",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "TSTR": {
+              "description": "time stamp time register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ALARMOUTTYPE": {
+                    "description": "AFO_ALARM output type",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TSINSEL": {
+                    "description": "TIMESTAMP mapping",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TAMP1INSEL": {
+                    "description": "TAMPER1 mapping",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TAMPIE": {
+                    "description": "Tamper interrupt enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TAMP1TRG": {
+                    "description": "Active level for tamper 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TAMP1E": {
+                    "description": "Tamper 1 detection enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TSDR": {
+              "description": "time stamp date register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WDU": {
+                    "description": "Week day units",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "MT": {
+                    "description": "Month tens in BCD format",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MU": {
+                    "description": "Month units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TSSSR": {
+              "description": "timestamp sub second register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SS": {
+                    "description": "Sub second value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CALR": {
+              "description": "calibration register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CALP": {
+                    "description": "Increase frequency of RTC by 488.5\n              ppm",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CALW8": {
+                    "description": "Use an 8-second calibration cycle\n              period",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CALW16": {
+                    "description": "Use a 16-second calibration cycle\n              period",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CALM": {
+                    "description": "Calibration minus",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "TAFCR": {
+              "description": "tamper and alternate function configuration\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ALARMOUTTYPE": {
+                    "description": "AFO_ALARM output type",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TSINSEL": {
+                    "description": "TIMESTAMP mapping",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TAMP1INSEL": {
+                    "description": "TAMPER1 mapping",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TAMPPUDIS": {
+                    "description": "TAMPER pull-up disable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TAMPPRCH": {
+                    "description": "Tamper precharge duration",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "TAMPFLT": {
+                    "description": "Tamper filter count",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "TAMPFREQ": {
+                    "description": "Tamper sampling frequency",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "TAMPTS": {
+                    "description": "Activate timestamp on tamper detection\n              event",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TAMP2TRG": {
+                    "description": "Active level for tamper 2",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TAMP2E": {
+                    "description": "Tamper 2 detection enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TAMPIE": {
+                    "description": "Tamper interrupt enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TAMP1TRG": {
+                    "description": "Active level for tamper 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TAMP1E": {
+                    "description": "Tamper 1 detection enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ALRMASSR": {
+              "description": "alarm A sub second register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MASKSS": {
+                    "description": "Mask the most-significant bits starting\n              at this bit",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "SS": {
+                    "description": "Sub seconds value",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "ALRMBSSR": {
+              "description": "alarm B sub second register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MASKSS": {
+                    "description": "Mask the most-significant bits starting\n              at this bit",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "SS": {
+                    "description": "Sub seconds value",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "BKP0R": {
+              "description": "backup register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP1R": {
+              "description": "backup register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP2R": {
+              "description": "backup register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP3R": {
+              "description": "backup register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP4R": {
+              "description": "backup register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP5R": {
+              "description": "backup register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP6R": {
+              "description": "backup register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP7R": {
+              "description": "backup register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP8R": {
+              "description": "backup register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP9R": {
+              "description": "backup register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP10R": {
+              "description": "backup register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP11R": {
+              "description": "backup register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP12R": {
+              "description": "backup register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP13R": {
+              "description": "backup register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP14R": {
+              "description": "backup register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP15R": {
+              "description": "backup register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP16R": {
+              "description": "backup register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP17R": {
+              "description": "backup register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP18R": {
+              "description": "backup register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP19R": {
+              "description": "backup register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UART4": {
+        "description": "Universal synchronous asynchronous receiver\n      transmitter",
+        "children": {
+          "registers": {
+            "SR": {
+              "description": "Status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 12582912,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LBD": {
+                    "description": "LIN break detection flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXE": {
+                    "description": "Transmit data register\n              empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TC": {
+                    "description": "Transmission complete",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNE": {
+                    "description": "Read data register not\n              empty",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLE": {
+                    "description": "IDLE line detected",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ORE": {
+                    "description": "Overrun error",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NF": {
+                    "description": "Noise detected flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FE": {
+                    "description": "Framing error",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PE": {
+                    "description": "Parity error",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "Data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data value",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "BRR": {
+              "description": "Baud rate register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIV_Mantissa": {
+                    "description": "mantissa of USARTDIV",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "DIV_Fraction": {
+                    "description": "fraction of USARTDIV",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "Control register 1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVER8": {
+                    "description": "Oversampling mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "UE": {
+                    "description": "USART enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "M": {
+                    "description": "Word length",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAKE": {
+                    "description": "Wakeup method",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PCE": {
+                    "description": "Parity control enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PS": {
+                    "description": "Parity selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PEIE": {
+                    "description": "PE interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXEIE": {
+                    "description": "TXE interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transmission complete interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RXNE interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLEIE": {
+                    "description": "IDLE interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TE": {
+                    "description": "Transmitter enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RE": {
+                    "description": "Receiver enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RWU": {
+                    "description": "Receiver wakeup",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SBK": {
+                    "description": "Send break",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "Control register 2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LINEN": {
+                    "description": "LIN mode enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "STOP bits",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "LBDIE": {
+                    "description": "LIN break detection interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LBDL": {
+                    "description": "lin break detection length",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADD": {
+                    "description": "Address of the USART node",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR3": {
+              "description": "Control register 3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ONEBIT": {
+                    "description": "One sample bit method\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DMAT": {
+                    "description": "DMA enable transmitter",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DMAR": {
+                    "description": "DMA enable receiver",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "HDSEL": {
+                    "description": "Half-duplex selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IRLP": {
+                    "description": "IrDA low-power",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IrDA mode enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_GLOBAL": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_GOTGCTL": {
+              "description": "OTG_FS control and status register\n          (OTG_FS_GOTGCTL)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRQSCS": {
+                    "description": "Session request success",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SRQ": {
+                    "description": "Session request",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HNGSCS": {
+                    "description": "Host negotiation success",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HNPRQ": {
+                    "description": "HNP request",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HSHNPEN": {
+                    "description": "Host set HNP enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DHNPEN": {
+                    "description": "Device HNP enabled",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CIDSTS": {
+                    "description": "Connector ID status",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DBCT": {
+                    "description": "Long/short debounce time",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ASVLD": {
+                    "description": "A-session valid",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BSVLD": {
+                    "description": "B-session valid",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FS_GOTGINT": {
+              "description": "OTG_FS interrupt register\n          (OTG_FS_GOTGINT)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEDET": {
+                    "description": "Session end detected",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SRSSCHG": {
+                    "description": "Session request success status\n              change",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNSSCHG": {
+                    "description": "Host negotiation success status\n              change",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HNGDET": {
+                    "description": "Host negotiation detected",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ADTOCHG": {
+                    "description": "A-device timeout change",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DBCDNE": {
+                    "description": "Debounce done",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GAHBCFG": {
+              "description": "OTG_FS AHB configuration register\n          (OTG_FS_GAHBCFG)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GINT": {
+                    "description": "Global interrupt mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXFELVL": {
+                    "description": "TxFIFO empty level",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PTXFELVL": {
+                    "description": "Periodic TxFIFO empty\n              level",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GUSBCFG": {
+              "description": "OTG_FS USB configuration register\n          (OTG_FS_GUSBCFG)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 2560,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TOCAL": {
+                    "description": "FS timeout calibration",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "PHYSEL": {
+                    "description": "Full Speed serial transceiver\n              select",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SRPCAP": {
+                    "description": "SRP-capable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNPCAP": {
+                    "description": "HNP-capable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TRDT": {
+                    "description": "USB turnaround time",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "FHMOD": {
+                    "description": "Force host mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FDMOD": {
+                    "description": "Force device mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CTXPKT": {
+                    "description": "Corrupt Tx packet",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GRSTCTL": {
+              "description": "OTG_FS reset register\n          (OTG_FS_GRSTCTL)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 536870912,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSRST": {
+                    "description": "Core soft reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HSRST": {
+                    "description": "HCLK soft reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FCRST": {
+                    "description": "Host frame counter reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RXFFLSH": {
+                    "description": "RxFIFO flush",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TXFFLSH": {
+                    "description": "TxFIFO flush",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "AHBIDL": {
+                    "description": "AHB master idle",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FS_GINTSTS": {
+              "description": "OTG_FS core interrupt register\n          (OTG_FS_GINTSTS)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 67108896,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CMOD": {
+                    "description": "Current mode of operation",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMIS": {
+                    "description": "Mode mismatch interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGINT": {
+                    "description": "OTG interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOF": {
+                    "description": "Start of frame",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFLVL": {
+                    "description": "RxFIFO non-empty",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NPTXFE": {
+                    "description": "Non-periodic TxFIFO empty",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GINAKEFF": {
+                    "description": "Global IN non-periodic NAK\n              effective",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GOUTNAKEFF": {
+                    "description": "Global OUT NAK effective",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ESUSP": {
+                    "description": "Early suspend",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "USBSUSP": {
+                    "description": "USB suspend",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMDNE": {
+                    "description": "Enumeration done",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOODRP": {
+                    "description": "Isochronous OUT packet dropped\n              interrupt",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPF": {
+                    "description": "End of periodic frame\n              interrupt",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IEPINT": {
+                    "description": "IN endpoint interrupt",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IISOIXFR": {
+                    "description": "Incomplete isochronous IN\n              transfer",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "IPXFR_INCOMPISOOUT": {
+                    "description": "Incomplete periodic transfer(Host\n              mode)/Incomplete isochronous OUT transfer(Device\n              mode)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HPRTINT": {
+                    "description": "Host port interrupt",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCINT": {
+                    "description": "Host channels interrupt",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PTXFE": {
+                    "description": "Periodic TxFIFO empty",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CIDSCHG": {
+                    "description": "Connector ID status change",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCINT": {
+                    "description": "Disconnect detected\n              interrupt",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SRQINT": {
+                    "description": "Session request/new session detected\n              interrupt",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WKUPINT": {
+                    "description": "Resume/remote wakeup detected\n              interrupt",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GINTMSK": {
+              "description": "OTG_FS interrupt mask register\n          (OTG_FS_GINTMSK)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMISM": {
+                    "description": "Mode mismatch interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGINT": {
+                    "description": "OTG interrupt mask",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SOFM": {
+                    "description": "Start of frame mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFLVLM": {
+                    "description": "Receive FIFO non-empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "NPTXFEM": {
+                    "description": "Non-periodic TxFIFO empty\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GINAKEFFM": {
+                    "description": "Global non-periodic IN NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GONAKEFFM": {
+                    "description": "Global OUT NAK effective\n              mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ESUSPM": {
+                    "description": "Early suspend mask",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "USBSUSPM": {
+                    "description": "USB suspend mask",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset mask",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMDNEM": {
+                    "description": "Enumeration done mask",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOODRPM": {
+                    "description": "Isochronous OUT packet dropped interrupt\n              mask",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPFM": {
+                    "description": "End of periodic frame interrupt\n              mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPMISM": {
+                    "description": "Endpoint mismatch interrupt\n              mask",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "IEPINT": {
+                    "description": "IN endpoints interrupt\n              mask",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoints interrupt\n              mask",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IISOIXFRM": {
+                    "description": "Incomplete isochronous IN transfer\n              mask",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "IPXFRM_IISOOXFRM": {
+                    "description": "Incomplete periodic transfer mask(Host\n              mode)/Incomplete isochronous OUT transfer mask(Device\n              mode)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "PRTIM": {
+                    "description": "Host port interrupt mask",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCIM": {
+                    "description": "Host channels interrupt\n              mask",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PTXFEM": {
+                    "description": "Periodic TxFIFO empty mask",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CIDSCHGM": {
+                    "description": "Connector ID status change\n              mask",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCINT": {
+                    "description": "Disconnect detected interrupt\n              mask",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SRQIM": {
+                    "description": "Session request/new session detected\n              interrupt mask",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WUIM": {
+                    "description": "Resume/remote wakeup detected interrupt\n              mask",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GRXSTSR_Device": {
+              "description": "OTG_FS Receive status debug read(Device\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  },
+                  "FRMNUM": {
+                    "description": "Frame number",
+                    "offset": 21,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "FS_GRXSTSR_Host": {
+              "description": "OTG_FS Receive status debug read(Host\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  },
+                  "FRMNUM": {
+                    "description": "Frame number",
+                    "offset": 21,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "FS_GRXFSIZ": {
+              "description": "OTG_FS Receive FIFO size register\n          (OTG_FS_GRXFSIZ)",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFD": {
+                    "description": "RxFIFO depth",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_GNPTXFSIZ_Device": {
+              "description": "OTG_FS non-periodic transmit FIFO size\n          register (Device mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX0FSA": {
+                    "description": "Endpoint 0 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "TX0FD": {
+                    "description": "Endpoint 0 TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_GNPTXFSIZ_Host": {
+              "description": "OTG_FS non-periodic transmit FIFO size\n          register (Host mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NPTXFSA": {
+                    "description": "Non-periodic transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "NPTXFD": {
+                    "description": "Non-periodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_GNPTXSTS": {
+              "description": "OTG_FS non-periodic transmit FIFO/queue\n          status register (OTG_FS_GNPTXSTS)",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 524800,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "NPTXFSAV": {
+                    "description": "Non-periodic TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "NPTQXSAV": {
+                    "description": "Non-periodic transmit request queue\n              space available",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "NPTXQTOP": {
+                    "description": "Top of the non-periodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "FS_GCCFG": {
+              "description": "OTG_FS general core configuration register\n          (OTG_FS_GCCFG)",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWRDWN": {
+                    "description": "Power down",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "VBUSASEN": {
+                    "description": "Enable the VBUS sensing\n              device",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "VBUSBSEN": {
+                    "description": "Enable the VBUS sensing\n              device",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SOFOUTEN": {
+                    "description": "SOF output enable",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_CID": {
+              "description": "core ID register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 4096,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRODUCT_ID": {
+                    "description": "Product ID field",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FS_HPTXFSIZ": {
+              "description": "OTG_FS Host periodic transmit FIFO size\n          register (OTG_FS_HPTXFSIZ)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 33555968,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTXSA": {
+                    "description": "Host periodic TxFIFO start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PTXFSIZ": {
+                    "description": "Host periodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPTXF1": {
+              "description": "OTG_FS device IN endpoint transmit FIFO size\n          register (OTG_FS_DIEPTXF2)",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFO2 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPTXF2": {
+              "description": "OTG_FS device IN endpoint transmit FIFO size\n          register (OTG_FS_DIEPTXF3)",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFO3 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPTXF3": {
+              "description": "OTG_FS device IN endpoint transmit FIFO size\n          register (OTG_FS_DIEPTXF4)",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFO4 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CRC": {
+        "description": "Cryptographic processor",
+        "children": {
+          "registers": {
+            "DR": {
+              "description": "Data register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data Register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "Independent Data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IDR": {
+                    "description": "Independent Data register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "Control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CR": {
+                    "description": "Control regidter",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "Ethernet_DMA": {
+        "description": "Ethernet: DMA controller operation",
+        "children": {
+          "registers": {
+            "DMABMR": {
+              "description": "Ethernet DMA bus mode register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 8449,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SR": {
+                    "description": "SR",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DA": {
+                    "description": "DA",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DSL": {
+                    "description": "DSL",
+                    "offset": 2,
+                    "size": 5
+                  },
+                  "EDFE": {
+                    "description": "EDFE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PBL": {
+                    "description": "PBL",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "RTPR": {
+                    "description": "RTPR",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "FB": {
+                    "description": "FB",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RDP": {
+                    "description": "RDP",
+                    "offset": 17,
+                    "size": 6
+                  },
+                  "USP": {
+                    "description": "USP",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FPM": {
+                    "description": "FPM",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "AAB": {
+                    "description": "AAB",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "MB": {
+                    "description": "MB",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMATPDR": {
+              "description": "Ethernet DMA transmit poll demand\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TPD": {
+                    "description": "TPD",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMARPDR": {
+              "description": "EHERNET DMA receive poll demand\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RPD": {
+                    "description": "RPD",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMARDLAR": {
+              "description": "Ethernet DMA receive descriptor list address\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRL": {
+                    "description": "SRL",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMATDLAR": {
+              "description": "Ethernet DMA transmit descriptor list\n          address register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STL": {
+                    "description": "STL",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMASR": {
+              "description": "Ethernet DMA status register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TS": {
+                    "description": "TS",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TPSS": {
+                    "description": "TPSS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TBUS": {
+                    "description": "TBUS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TJTS": {
+                    "description": "TJTS",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ROS": {
+                    "description": "ROS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TUS": {
+                    "description": "TUS",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RS": {
+                    "description": "RS",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RBUS": {
+                    "description": "RBUS",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RPSS": {
+                    "description": "RPSS",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PWTS": {
+                    "description": "PWTS",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ETS": {
+                    "description": "ETS",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FBES": {
+                    "description": "FBES",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ERS": {
+                    "description": "ERS",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "AIS": {
+                    "description": "AIS",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "NIS": {
+                    "description": "NIS",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RPS": {
+                    "description": "RPS",
+                    "offset": 17,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "TPS": {
+                    "description": "TPS",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "EBS": {
+                    "description": "EBS",
+                    "offset": 23,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "MMCS": {
+                    "description": "MMCS",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PMTS": {
+                    "description": "PMTS",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TSTS": {
+                    "description": "TSTS",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DMAOMR": {
+              "description": "Ethernet DMA operation mode\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SR": {
+                    "description": "SR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OSF": {
+                    "description": "OSF",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTC": {
+                    "description": "RTC",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "FUGF": {
+                    "description": "FUGF",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FEF": {
+                    "description": "FEF",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ST": {
+                    "description": "ST",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TTC": {
+                    "description": "TTC",
+                    "offset": 14,
+                    "size": 3
+                  },
+                  "FTF": {
+                    "description": "FTF",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TSF": {
+                    "description": "TSF",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "DFRF": {
+                    "description": "DFRF",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "RSF": {
+                    "description": "RSF",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DTCEFD": {
+                    "description": "DTCEFD",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMAIER": {
+              "description": "Ethernet DMA interrupt enable\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIE": {
+                    "description": "TIE",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TPSIE": {
+                    "description": "TPSIE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TBUIE": {
+                    "description": "TBUIE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TJTIE": {
+                    "description": "TJTIE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ROIE": {
+                    "description": "ROIE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TUIE": {
+                    "description": "TUIE",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RIE": {
+                    "description": "RIE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RBUIE": {
+                    "description": "RBUIE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RPSIE": {
+                    "description": "RPSIE",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RWTIE": {
+                    "description": "RWTIE",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ETIE": {
+                    "description": "ETIE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FBEIE": {
+                    "description": "FBEIE",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ERIE": {
+                    "description": "ERIE",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "AISE": {
+                    "description": "AISE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "NISE": {
+                    "description": "NISE",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMAMFBOCR": {
+              "description": "Ethernet DMA missed frame and buffer\n          overflow counter register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MFC": {
+                    "description": "MFC",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OMFC": {
+                    "description": "OMFC",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MFA": {
+                    "description": "MFA",
+                    "offset": 17,
+                    "size": 11
+                  },
+                  "OFOC": {
+                    "description": "OFOC",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMARSWTR": {
+              "description": "Ethernet DMA receive status watchdog timer\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RSWTC": {
+                    "description": "RSWTC",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DMACHTDR": {
+              "description": "Ethernet DMA current host transmit\n          descriptor register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HTDAP": {
+                    "description": "HTDAP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMACHRDR": {
+              "description": "Ethernet DMA current host receive descriptor\n          register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HRDAP": {
+                    "description": "HRDAP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMACHTBAR": {
+              "description": "Ethernet DMA current host transmit buffer\n          address register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HTBAP": {
+                    "description": "HTBAP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMACHRBAR": {
+              "description": "Ethernet DMA current host receive buffer\n          address register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HRBAP": {
+                    "description": "HRBAP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "C_ADC": {
+        "description": "Common ADC registers",
+        "children": {
+          "registers": {
+            "CSR": {
+              "description": "ADC Common status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "OVR3": {
+                    "description": "Overrun flag of ADC3",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "STRT3": {
+                    "description": "Regular channel Start flag of ADC\n              3",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "JSTRT3": {
+                    "description": "Injected channel Start flag of ADC\n              3",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "JEOC3": {
+                    "description": "Injected channel end of conversion of\n              ADC 3",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EOC3": {
+                    "description": "End of conversion of ADC 3",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "AWD3": {
+                    "description": "Analog watchdog flag of ADC\n              3",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OVR2": {
+                    "description": "Overrun flag of ADC 2",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "STRT2": {
+                    "description": "Regular channel Start flag of ADC\n              2",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "JSTRT2": {
+                    "description": "Injected channel Start flag of ADC\n              2",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "JEOC2": {
+                    "description": "Injected channel end of conversion of\n              ADC 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EOC2": {
+                    "description": "End of conversion of ADC 2",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "AWD2": {
+                    "description": "Analog watchdog flag of ADC\n              2",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OVR1": {
+                    "description": "Overrun flag of ADC 1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "STRT1": {
+                    "description": "Regular channel Start flag of ADC\n              1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "JSTRT1": {
+                    "description": "Injected channel Start flag of ADC\n              1",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "JEOC1": {
+                    "description": "Injected channel end of conversion of\n              ADC 1",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EOC1": {
+                    "description": "End of conversion of ADC 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AWD1": {
+                    "description": "Analog watchdog flag of ADC\n              1",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "ADC common control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSVREFE": {
+                    "description": "Temperature sensor and VREFINT\n              enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "VBATE": {
+                    "description": "VBAT enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "ADCPRE": {
+                    "description": "ADC prescaler",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA": {
+                    "description": "Direct memory access mode for multi ADC\n              mode",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DDS": {
+                    "description": "DMA disable selection for multi-ADC\n              mode",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "DELAY": {
+                    "description": "Delay between 2 sampling\n              phases",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MULT": {
+                    "description": "Multi ADC mode selection",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CDR": {
+              "description": "ADC common regular data register for dual\n          and triple modes",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA2": {
+                    "description": "2nd data item of a pair of regular\n              conversions",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "DATA1": {
+                    "description": "1st data item of a pair of regular\n              conversions",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM1": {
+        "description": "Advanced-timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OIS4": {
+                    "description": "Output Idle state 4",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OIS3N": {
+                    "description": "Output Idle state 3",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OIS3": {
+                    "description": "Output Idle state 3",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OIS2N": {
+                    "description": "Output Idle state 2",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OIS2": {
+                    "description": "Output Idle state 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OIS1N": {
+                    "description": "Output Idle state 1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OIS1": {
+                    "description": "Output Idle state 1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CCUS": {
+                    "description": "Capture/compare control update\n              selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CCPC": {
+                    "description": "Capture/compare preloaded\n              control",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "COMDE": {
+                    "description": "COM DMA request enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BIE": {
+                    "description": "Break interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "COMIE": {
+                    "description": "COM interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BIF": {
+                    "description": "Break interrupt flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMIF": {
+                    "description": "COM interrupt flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BG": {
+                    "description": "Break generation",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMG": {
+                    "description": "Capture/Compare control update\n              generation",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "Output Compare 2 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "Output Compare 2 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "Output Compare 2 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "Output Compare 2 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "Output Compare 1 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register 2 (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC4CE": {
+                    "description": "Output compare 4 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "Output compare 4 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "Output compare 4 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "Output compare 4 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "Output compare 3 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "Output compare 3 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "Output compare 3 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "Output compare 3 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "Capture/Compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC3NE": {
+                    "description": "Capture/Compare 3 complementary output\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2NE": {
+                    "description": "Capture/Compare 2 complementary output\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1NE": {
+                    "description": "Capture/Compare 1 complementary output\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2": {
+                    "description": "Capture/Compare 2 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3": {
+                    "description": "Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4": {
+                    "description": "Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RCR": {
+              "description": "repetition counter register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REP": {
+                    "description": "Repetition counter value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BDTR": {
+              "description": "break and dead-time register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MOE": {
+                    "description": "Main output enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "AOE": {
+                    "description": "Automatic output enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BKP": {
+                    "description": "Break polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BKE": {
+                    "description": "Break enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OSSR": {
+                    "description": "Off-state selection for Run\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OSSI": {
+                    "description": "Off-state selection for Idle\n              mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LOCK": {
+                    "description": "Lock configuration",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "DTG": {
+                    "description": "Dead-time generator setup",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "Ethernet_PTP": {
+        "description": "Ethernet: Precision time protocol",
+        "children": {
+          "registers": {
+            "PTPTSCR": {
+              "description": "Ethernet PTP time stamp control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 8192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSE": {
+                    "description": "TSE",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TSFCU": {
+                    "description": "TSFCU",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TSPTPPSV2E": {
+                    "description": "TSPTPPSV2E",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TSSPTPOEFE": {
+                    "description": "TSSPTPOEFE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TSSIPV6FE": {
+                    "description": "TSSIPV6FE",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TSSIPV4FE": {
+                    "description": "TSSIPV4FE",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TSSEME": {
+                    "description": "TSSEME",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TSSMRME": {
+                    "description": "TSSMRME",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TSCNT": {
+                    "description": "TSCNT",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "TSPFFMAE": {
+                    "description": "TSPFFMAE",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TSSTI": {
+                    "description": "TSSTI",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TSSTU": {
+                    "description": "TSSTU",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TSITE": {
+                    "description": "TSITE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TTSARU": {
+                    "description": "TTSARU",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TSSARFE": {
+                    "description": "TSSARFE",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TSSSR": {
+                    "description": "TSSSR",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PTPSSIR": {
+              "description": "Ethernet PTP subsecond increment\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STSSI": {
+                    "description": "STSSI",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PTPTSHR": {
+              "description": "Ethernet PTP time stamp high\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STS": {
+                    "description": "STS",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTSLR": {
+              "description": "Ethernet PTP time stamp low\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STSS": {
+                    "description": "STSS",
+                    "offset": 0,
+                    "size": 31
+                  },
+                  "STPNS": {
+                    "description": "STPNS",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PTPTSHUR": {
+              "description": "Ethernet PTP time stamp high update\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSUS": {
+                    "description": "TSUS",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTSLUR": {
+              "description": "Ethernet PTP time stamp low update\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSUSS": {
+                    "description": "TSUSS",
+                    "offset": 0,
+                    "size": 31
+                  },
+                  "TSUPNS": {
+                    "description": "TSUPNS",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PTPTSAR": {
+              "description": "Ethernet PTP time stamp addend\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSA": {
+                    "description": "TSA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTTHR": {
+              "description": "Ethernet PTP target time high\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TTSH": {
+                    "description": "0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTTLR": {
+              "description": "Ethernet PTP target time low\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TTSL": {
+                    "description": "TTSL",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTSSR": {
+              "description": "Ethernet PTP time stamp status\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TSSO": {
+                    "description": "TSSO",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TSTTR": {
+                    "description": "TSTTR",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PTPPPSCR": {
+              "description": "Ethernet PTP PPS control\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TSSO": {
+                    "description": "TSSO",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TSTTR": {
+                    "description": "TSTTR",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM2": {
+        "description": "General purpose timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "OC2CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "OC2M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "OC2PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "OC2FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "CC2S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "OC1CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "OC1M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "OC1PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "OC1FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "CC1S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register 2 (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "O24CE": {
+                    "description": "O24CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "OC4M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "OC4PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "OC4FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "CC4S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "OC3CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "OC3M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "OC3PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "OC3FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "CC3S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4NP": {
+                    "description": "Capture/Compare 4 output\n              Polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT_H": {
+                    "description": "High counter value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CNT_L": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR_H": {
+                    "description": "High Auto-reload value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ARR_L": {
+                    "description": "Low Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1_H": {
+                    "description": "High Capture/Compare 1\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR1_L": {
+                    "description": "Low Capture/Compare 1\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2_H": {
+                    "description": "High Capture/Compare 2\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR2_L": {
+                    "description": "Low Capture/Compare 2\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR3_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR4_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OR": {
+              "description": "TIM5 option register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ITR1_RMP": {
+                    "description": "Timer Input 4 remap",
+                    "offset": 10,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM3": {
+        "description": "General purpose timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "OC2CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "OC2M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "OC2PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "OC2FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "CC2S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "OC1CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "OC1M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "OC1PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "OC1FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "CC1S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register 2 (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "O24CE": {
+                    "description": "O24CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "OC4M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "OC4PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "OC4FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "CC4S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "OC3CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "OC3M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "OC3PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "OC3FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "CC3S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4NP": {
+                    "description": "Capture/Compare 4 output\n              Polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT_H": {
+                    "description": "High counter value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CNT_L": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR_H": {
+                    "description": "High Auto-reload value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ARR_L": {
+                    "description": "Low Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1_H": {
+                    "description": "High Capture/Compare 1\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR1_L": {
+                    "description": "Low Capture/Compare 1\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2_H": {
+                    "description": "High Capture/Compare 2\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR2_L": {
+                    "description": "Low Capture/Compare 2\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR3_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR4_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "Ethernet_MMC": {
+        "description": "Ethernet: MAC management counters",
+        "children": {
+          "registers": {
+            "MMCCR": {
+              "description": "Ethernet MMC control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CR": {
+                    "description": "CR",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CSR": {
+                    "description": "CSR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ROR": {
+                    "description": "ROR",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MCF": {
+                    "description": "MCF",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MCP": {
+                    "description": "MCP",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MCFHP": {
+                    "description": "MCFHP",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCRIR": {
+              "description": "Ethernet MMC receive interrupt\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFCES": {
+                    "description": "RFCES",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RFAES": {
+                    "description": "RFAES",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RGUFS": {
+                    "description": "RGUFS",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCTIR": {
+              "description": "Ethernet MMC transmit interrupt\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TGFSCS": {
+                    "description": "TGFSCS",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TGFMSCS": {
+                    "description": "TGFMSCS",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TGFS": {
+                    "description": "TGFS",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCRIMR": {
+              "description": "Ethernet MMC receive interrupt mask\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFCEM": {
+                    "description": "RFCEM",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RFAEM": {
+                    "description": "RFAEM",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RGUFM": {
+                    "description": "RGUFM",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCTIMR": {
+              "description": "Ethernet MMC transmit interrupt mask\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TGFSCM": {
+                    "description": "TGFSCM",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TGFMSCM": {
+                    "description": "TGFMSCM",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TGFM": {
+                    "description": "TGFM",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCTGFSCCR": {
+              "description": "Ethernet MMC transmitted good frames after a\n          single collision counter",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TGFSCC": {
+                    "description": "TGFSCC",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCTGFMSCCR": {
+              "description": "Ethernet MMC transmitted good frames after\n          more than a single collision",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TGFMSCC": {
+                    "description": "TGFMSCC",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCTGFCR": {
+              "description": "Ethernet MMC transmitted good frames counter\n          register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TGFC": {
+                    "description": "HTL",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCRFCECR": {
+              "description": "Ethernet MMC received frames with CRC error\n          counter register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RFCFC": {
+                    "description": "RFCFC",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCRFAECR": {
+              "description": "Ethernet MMC received frames with alignment\n          error counter register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RFAEC": {
+                    "description": "RFAEC",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCRGUFCR": {
+              "description": "MMC received good unicast frames counter\n          register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RGUFC": {
+                    "description": "RGUFC",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM5": {
+        "description": "General-purpose-timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "OC2CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "OC2M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "OC2PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "OC2FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "CC2S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "OC1CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "OC1M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "OC1PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "OC1FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "CC1S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register 2 (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "O24CE": {
+                    "description": "O24CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "OC4M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "OC4PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "OC4FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "CC4S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "OC3CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "OC3M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "OC3PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "OC3FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "CC3S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4NP": {
+                    "description": "Capture/Compare 4 output\n              Polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT_H": {
+                    "description": "High counter value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CNT_L": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR_H": {
+                    "description": "High Auto-reload value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ARR_L": {
+                    "description": "Low Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1_H": {
+                    "description": "High Capture/Compare 1\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR1_L": {
+                    "description": "Low Capture/Compare 1\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2_H": {
+                    "description": "High Capture/Compare 2\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR2_L": {
+                    "description": "Low Capture/Compare 2\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR3_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR4_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OR": {
+              "description": "TIM5 option register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IT4_RMP": {
+                    "description": "Timer Input 4 remap",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM9": {
+        "description": "General purpose timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2M": {
+                    "description": "Output Compare 2 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "Output Compare 2 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "Output Compare 2 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2": {
+                    "description": "Capture/Compare 2 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "Ethernet_MAC": {
+        "description": "Ethernet: media access control\n      (MAC)",
+        "children": {
+          "registers": {
+            "MACCR": {
+              "description": "Ethernet MAC configuration\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RE": {
+                    "description": "RE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TE": {
+                    "description": "TE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DC": {
+                    "description": "DC",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BL": {
+                    "description": "BL",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "APCS": {
+                    "description": "APCS",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RD": {
+                    "description": "RD",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IPCO": {
+                    "description": "IPCO",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DM": {
+                    "description": "DM",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LM": {
+                    "description": "LM",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ROD": {
+                    "description": "ROD",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FES": {
+                    "description": "FES",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CSD": {
+                    "description": "CSD",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "IFG": {
+                    "description": "IFG",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "JD": {
+                    "description": "JD",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "WD": {
+                    "description": "WD",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CSTF": {
+                    "description": "CSTF",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACFFR": {
+              "description": "Ethernet MAC frame filter\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PM": {
+                    "description": "PM",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HU": {
+                    "description": "HU",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HM": {
+                    "description": "HM",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DAIF": {
+                    "description": "DAIF",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RAM": {
+                    "description": "RAM",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BFD": {
+                    "description": "BFD",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PCF": {
+                    "description": "PCF",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SAIF": {
+                    "description": "SAIF",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SAF": {
+                    "description": "SAF",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HPF": {
+                    "description": "HPF",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RA": {
+                    "description": "RA",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACHTHR": {
+              "description": "Ethernet MAC hash table high\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HTH": {
+                    "description": "HTH",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACHTLR": {
+              "description": "Ethernet MAC hash table low\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HTL": {
+                    "description": "HTL",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACMIIAR": {
+              "description": "Ethernet MAC MII address\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MB": {
+                    "description": "MB",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MW": {
+                    "description": "MW",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CR": {
+                    "description": "CR",
+                    "offset": 2,
+                    "size": 3
+                  },
+                  "MR": {
+                    "description": "MR",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "PA": {
+                    "description": "PA",
+                    "offset": 11,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "MACMIIDR": {
+              "description": "Ethernet MAC MII data register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TD": {
+                    "description": "TD",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "MACFCR": {
+              "description": "Ethernet MAC flow control\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FCB": {
+                    "description": "FCB",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TFCE": {
+                    "description": "TFCE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RFCE": {
+                    "description": "RFCE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UPFD": {
+                    "description": "UPFD",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PLT": {
+                    "description": "PLT",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "ZQPD": {
+                    "description": "ZQPD",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PT": {
+                    "description": "PT",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "MACVLANTR": {
+              "description": "Ethernet MAC VLAN tag register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VLANTI": {
+                    "description": "VLANTI",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "VLANTC": {
+                    "description": "VLANTC",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACPMTCSR": {
+              "description": "Ethernet MAC PMT control and status\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PD": {
+                    "description": "PD",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MPE": {
+                    "description": "MPE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WFE": {
+                    "description": "WFE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MPR": {
+                    "description": "MPR",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WFR": {
+                    "description": "WFR",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GU": {
+                    "description": "GU",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WFFRPR": {
+                    "description": "WFFRPR",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACDBGR": {
+              "description": "Ethernet MAC debug register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CR": {
+                    "description": "CR",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CSR": {
+                    "description": "CSR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ROR": {
+                    "description": "ROR",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MCF": {
+                    "description": "MCF",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MCP": {
+                    "description": "MCP",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MCFHP": {
+                    "description": "MCFHP",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACSR": {
+              "description": "Ethernet MAC interrupt status\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PMTS": {
+                    "description": "PMTS",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMCS": {
+                    "description": "MMCS",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMCRS": {
+                    "description": "MMCRS",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMCTS": {
+                    "description": "MMCTS",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TSTS": {
+                    "description": "TSTS",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACIMR": {
+              "description": "Ethernet MAC interrupt mask\n          register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PMTIM": {
+                    "description": "PMTIM",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TSTIM": {
+                    "description": "TSTIM",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA0HR": {
+              "description": "Ethernet MAC address 0 high\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 1114111,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA0H": {
+                    "description": "MAC address0 high",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MO": {
+                    "description": "Always 1",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MACA0LR": {
+              "description": "Ethernet MAC address 0 low\n          register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA0L": {
+                    "description": "0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACA1HR": {
+              "description": "Ethernet MAC address 1 high\n          register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA1H": {
+                    "description": "MACA1H",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MBC": {
+                    "description": "MBC",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "SA": {
+                    "description": "SA",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "AE": {
+                    "description": "AE",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA1LR": {
+              "description": "Ethernet MAC address1 low\n          register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA1LR": {
+                    "description": "MACA1LR",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACA2HR": {
+              "description": "Ethernet MAC address 2 high\n          register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC2AH": {
+                    "description": "MAC2AH",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MBC": {
+                    "description": "MBC",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "SA": {
+                    "description": "SA",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "AE": {
+                    "description": "AE",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA2LR": {
+              "description": "Ethernet MAC address 2 low\n          register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA2L": {
+                    "description": "MACA2L",
+                    "offset": 0,
+                    "size": 31
+                  }
+                }
+              }
+            },
+            "MACA3HR": {
+              "description": "Ethernet MAC address 3 high\n          register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA3H": {
+                    "description": "MACA3H",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MBC": {
+                    "description": "MBC",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "SA": {
+                    "description": "SA",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "AE": {
+                    "description": "AE",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA3LR": {
+              "description": "Ethernet MAC address 3 low\n          register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MBCA3L": {
+                    "description": "MBCA3L",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM10": {
+        "description": "General-purpose-timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM11": {
+        "description": "General-purpose-timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OR": {
+              "description": "option register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RMP": {
+                    "description": "Input 1 remapping\n              capability",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  },
+  "devices": {
+    "STM32F407": {
+      "arch": "cortex_m4",
+      "description": "STM32F407",
+      "properties": {
+        "cpu.nvic_prio_bits": "3",
+        "cpu.mpu": "false",
+        "cpu.fpu": "false",
+        "cpu.revision": "r1p0",
+        "cpu.vendor_systick_config": "false",
+        "cpu.endian": "little",
+        "cpu.name": "CM4"
+      },
+      "children": {
+        "interrupts": {
+          "MemManageFault": {
+            "index": -12
+          },
+          "BusFault": {
+            "index": -11
+          },
+          "UsageFault": {
+            "index": -10
+          },
+          "DebugMonitor": {
+            "index": -4
+          },
+          "NMI": {
+            "index": -14
+          },
+          "HardFault": {
+            "index": -13
+          },
+          "SVCall": {
+            "index": -5
+          },
+          "PendSV": {
+            "index": -2
+          },
+          "SysTick": {
+            "index": -1
+          },
+          "FPU": {
+            "index": 81,
+            "description": "Floating point unit interrupt"
+          },
+          "DCMI": {
+            "index": 78,
+            "description": "DCMI global interrupt"
+          },
+          "FSMC": {
+            "index": 48,
+            "description": "FSMC global interrupt"
+          },
+          "DMA2_Stream0": {
+            "index": 56,
+            "description": "DMA2 Stream0 global interrupt"
+          },
+          "DMA1_Stream0": {
+            "index": 11,
+            "description": "DMA1 Stream0 global interrupt"
+          },
+          "RCC": {
+            "index": 5,
+            "description": "RCC global interrupt"
+          },
+          "SPI1": {
+            "index": 35,
+            "description": "SPI1 global interrupt"
+          },
+          "SPI2": {
+            "index": 36,
+            "description": "SPI2 global interrupt"
+          },
+          "SPI3": {
+            "index": 51,
+            "description": "SPI3 global interrupt"
+          },
+          "SDIO": {
+            "index": 49,
+            "description": "SDIO global interrupt"
+          },
+          "ADC": {
+            "index": 18,
+            "description": "ADC3 global interrupts"
+          },
+          "USART6": {
+            "index": 71,
+            "description": "USART6 global interrupt"
+          },
+          "USART1": {
+            "index": 37,
+            "description": "USART1 global interrupt"
+          },
+          "USART2": {
+            "index": 38,
+            "description": "USART2 global interrupt"
+          },
+          "USART3": {
+            "index": 39,
+            "description": "USART3 global interrupt"
+          },
+          "TIM6_DAC": {
+            "index": 54,
+            "description": "TIM6 global interrupt, DAC1 and DAC2 underrun\n        error interrupt"
+          },
+          "PVD": {
+            "index": 1,
+            "description": "PVD through EXTI line detection\n        interrupt"
+          },
+          "I2C3_EV": {
+            "index": 72,
+            "description": "I2C3 event interrupt"
+          },
+          "I2C2_EV": {
+            "index": 33,
+            "description": "I2C2 event interrupt"
+          },
+          "I2C1_EV": {
+            "index": 31,
+            "description": "I2C1 event interrupt"
+          },
+          "WWDG": {
+            "index": 0,
+            "description": "Window Watchdog interrupt"
+          },
+          "RTC_WKUP": {
+            "index": 3,
+            "description": "RTC Wakeup interrupt through the EXTI\n        line"
+          },
+          "UART4": {
+            "index": 52,
+            "description": "UART4 global interrupt"
+          },
+          "UART5": {
+            "index": 53,
+            "description": "UART5 global interrupt"
+          },
+          "TIM1_BRK_TIM9": {
+            "index": 24,
+            "description": "TIM1 Break interrupt and TIM9 global\n        interrupt"
+          },
+          "TIM8_BRK_TIM12": {
+            "index": 43,
+            "description": "TIM8 Break interrupt and TIM12 global\n        interrupt"
+          },
+          "TIM2": {
+            "index": 28,
+            "description": "TIM2 global interrupt"
+          },
+          "TIM3": {
+            "index": 29,
+            "description": "TIM3 global interrupt"
+          },
+          "TIM4": {
+            "index": 30,
+            "description": "TIM4 global interrupt"
+          },
+          "TIM5": {
+            "index": 50,
+            "description": "TIM5 global interrupt"
+          },
+          "TIM1_UP_TIM10": {
+            "index": 25,
+            "description": "TIM1 Update interrupt and TIM10 global\n        interrupt"
+          },
+          "TIM8_UP_TIM13": {
+            "index": 44,
+            "description": "TIM8 Update interrupt and TIM13 global\n        interrupt"
+          },
+          "TIM8_TRG_COM_TIM14": {
+            "index": 45,
+            "description": "TIM8 Trigger and Commutation interrupts and\n        TIM14 global interrupt"
+          },
+          "TIM1_TRG_COM_TIM11": {
+            "index": 26,
+            "description": "TIM1 Trigger and Commutation interrupts and\n        TIM11 global interrupt"
+          },
+          "TIM7": {
+            "index": 55,
+            "description": "TIM7 global interrupt"
+          },
+          "ETH": {
+            "index": 61,
+            "description": "Ethernet global interrupt"
+          },
+          "OTG_FS_WKUP": {
+            "index": 42,
+            "description": "USB On-The-Go FS Wakeup through EXTI line\n        interrupt"
+          },
+          "CAN1_TX": {
+            "index": 19,
+            "description": "CAN1 TX interrupts"
+          },
+          "CAN2_TX": {
+            "index": 63,
+            "description": "CAN2 TX interrupts"
+          },
+          "TAMP_STAMP": {
+            "index": 2,
+            "description": "Tamper and TimeStamp interrupts through the\n        EXTI line"
+          },
+          "OTG_HS_EP1_OUT": {
+            "index": 74,
+            "description": "USB On The Go HS End Point 1 Out global\n        interrupt"
+          },
+          "LCD_TFT": {
+            "index": 88,
+            "description": "LTDC global interrupt"
+          },
+          "HASH_RNG": {
+            "index": 80,
+            "description": "Hash and Rng global interrupt"
+          },
+          "CRYP": {
+            "index": 79,
+            "description": "CRYP crypto global interrupt"
+          }
+        },
+        "peripheral_instances": {
+          "RNG": {
+            "description": "Random number generator",
+            "offset": 1342572544,
+            "type": "types.peripherals.RNG"
+          },
+          "DCMI": {
+            "description": "Digital camera interface",
+            "offset": 1342504960,
+            "type": "types.peripherals.DCMI"
+          },
+          "FSMC": {
+            "description": "Flexible static memory controller",
+            "offset": 2684354560,
+            "type": "types.peripherals.FSMC"
+          },
+          "DBG": {
+            "description": "Debug support",
+            "offset": 3758366720,
+            "type": "types.peripherals.DBG"
+          },
+          "DMA2": {
+            "description": "DMA controller",
+            "offset": 1073898496,
+            "type": "types.peripherals.DMA2"
+          },
+          "DMA1": {
+            "offset": 1073897472,
+            "type": "types.peripherals.DMA2"
+          },
+          "RCC": {
+            "description": "Reset and clock control",
+            "offset": 1073887232,
+            "type": "types.peripherals.RCC"
+          },
+          "GPIOI": {
+            "description": "General-purpose I/Os",
+            "offset": 1073881088,
+            "type": "types.peripherals.GPIOI"
+          },
+          "GPIOH": {
+            "offset": 1073880064,
+            "type": "types.peripherals.GPIOI"
+          },
+          "GPIOG": {
+            "offset": 1073879040,
+            "type": "types.peripherals.GPIOI"
+          },
+          "GPIOF": {
+            "offset": 1073878016,
+            "type": "types.peripherals.GPIOI"
+          },
+          "GPIOE": {
+            "offset": 1073876992,
+            "type": "types.peripherals.GPIOI"
+          },
+          "GPIOD": {
+            "offset": 1073875968,
+            "type": "types.peripherals.GPIOI"
+          },
+          "GPIOC": {
+            "offset": 1073874944,
+            "type": "types.peripherals.GPIOI"
+          },
+          "GPIOJ": {
+            "offset": 1073882112,
+            "type": "types.peripherals.GPIOI"
+          },
+          "GPIOK": {
+            "offset": 1073883136,
+            "type": "types.peripherals.GPIOI"
+          },
+          "GPIOB": {
+            "description": "General-purpose I/Os",
+            "offset": 1073873920,
+            "type": "types.peripherals.GPIOB"
+          },
+          "GPIOA": {
+            "description": "General-purpose I/Os",
+            "offset": 1073872896,
+            "type": "types.peripherals.GPIOA"
+          },
+          "SYSCFG": {
+            "description": "System configuration controller",
+            "offset": 1073821696,
+            "type": "types.peripherals.SYSCFG"
+          },
+          "SPI1": {
+            "description": "Serial peripheral interface",
+            "offset": 1073819648,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI2": {
+            "offset": 1073756160,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI3": {
+            "offset": 1073757184,
+            "type": "types.peripherals.SPI1"
+          },
+          "I2S2ext": {
+            "offset": 1073755136,
+            "type": "types.peripherals.SPI1"
+          },
+          "I2S3ext": {
+            "offset": 1073758208,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI4": {
+            "offset": 1073820672,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI5": {
+            "offset": 1073827840,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI6": {
+            "offset": 1073828864,
+            "type": "types.peripherals.SPI1"
+          },
+          "SDIO": {
+            "description": "Secure digital input/output\n      interface",
+            "offset": 1073818624,
+            "type": "types.peripherals.SDIO"
+          },
+          "ADC1": {
+            "description": "Analog-to-digital converter",
+            "offset": 1073815552,
+            "type": "types.peripherals.ADC1"
+          },
+          "ADC2": {
+            "offset": 1073815808,
+            "type": "types.peripherals.ADC1"
+          },
+          "ADC3": {
+            "offset": 1073816064,
+            "type": "types.peripherals.ADC1"
+          },
+          "USART6": {
+            "description": "Universal synchronous asynchronous receiver\n      transmitter",
+            "offset": 1073812480,
+            "type": "types.peripherals.USART6"
+          },
+          "USART1": {
+            "offset": 1073811456,
+            "type": "types.peripherals.USART6"
+          },
+          "USART2": {
+            "offset": 1073759232,
+            "type": "types.peripherals.USART6"
+          },
+          "USART3": {
+            "offset": 1073760256,
+            "type": "types.peripherals.USART6"
+          },
+          "DAC": {
+            "description": "Digital-to-analog converter",
+            "offset": 1073771520,
+            "type": "types.peripherals.DAC"
+          },
+          "PWR": {
+            "description": "Power control",
+            "offset": 1073770496,
+            "type": "types.peripherals.PWR"
+          },
+          "I2C3": {
+            "description": "Inter-integrated circuit",
+            "offset": 1073765376,
+            "type": "types.peripherals.I2C3"
+          },
+          "I2C2": {
+            "offset": 1073764352,
+            "type": "types.peripherals.I2C3"
+          },
+          "I2C1": {
+            "offset": 1073763328,
+            "type": "types.peripherals.I2C3"
+          },
+          "IWDG": {
+            "description": "Independent watchdog",
+            "offset": 1073754112,
+            "type": "types.peripherals.IWDG"
+          },
+          "WWDG": {
+            "description": "Window watchdog",
+            "offset": 1073753088,
+            "type": "types.peripherals.WWDG"
+          },
+          "RTC": {
+            "description": "Real-time clock",
+            "offset": 1073752064,
+            "type": "types.peripherals.RTC"
+          },
+          "UART4": {
+            "description": "Universal synchronous asynchronous receiver\n      transmitter",
+            "offset": 1073761280,
+            "type": "types.peripherals.UART4"
+          },
+          "UART5": {
+            "offset": 1073762304,
+            "type": "types.peripherals.UART4"
+          },
+          "UART7": {
+            "offset": 1073772544,
+            "type": "types.peripherals.UART4"
+          },
+          "UART8": {
+            "offset": 1073773568,
+            "type": "types.peripherals.UART4"
+          },
+          "C_ADC": {
+            "description": "Common ADC registers",
+            "offset": 1073816320,
+            "type": "types.peripherals.C_ADC"
+          },
+          "TIM1": {
+            "description": "Advanced-timers",
+            "offset": 1073807360,
+            "type": "types.peripherals.TIM1"
+          },
+          "TIM8": {
+            "offset": 1073808384,
+            "type": "types.peripherals.TIM1"
+          },
+          "TIM2": {
+            "description": "General purpose timers",
+            "offset": 1073741824,
+            "type": "types.peripherals.TIM2"
+          },
+          "TIM3": {
+            "description": "General purpose timers",
+            "offset": 1073742848,
+            "type": "types.peripherals.TIM3"
+          },
+          "TIM4": {
+            "offset": 1073743872,
+            "type": "types.peripherals.TIM3"
+          },
+          "TIM5": {
+            "description": "General-purpose-timers",
+            "offset": 1073744896,
+            "type": "types.peripherals.TIM5"
+          },
+          "TIM9": {
+            "description": "General purpose timers",
+            "offset": 1073823744,
+            "type": "types.peripherals.TIM9"
+          },
+          "TIM12": {
+            "offset": 1073747968,
+            "type": "types.peripherals.TIM9"
+          },
+          "TIM10": {
+            "description": "General-purpose-timers",
+            "offset": 1073824768,
+            "type": "types.peripherals.TIM10"
+          },
+          "TIM13": {
+            "offset": 1073748992,
+            "type": "types.peripherals.TIM10"
+          },
+          "TIM14": {
+            "offset": 1073750016,
+            "type": "types.peripherals.TIM10"
+          },
+          "TIM11": {
+            "description": "General-purpose-timers",
+            "offset": 1073825792,
+            "type": "types.peripherals.TIM11"
+          },
+          "TIM6": {
+            "description": "Basic timers",
+            "offset": 1073745920,
+            "type": "types.peripherals.TIM6"
+          },
+          "TIM7": {
+            "offset": 1073746944,
+            "type": "types.peripherals.TIM6"
+          },
+          "Ethernet_MAC": {
+            "description": "Ethernet: media access control\n      (MAC)",
+            "offset": 1073905664,
+            "type": "types.peripherals.Ethernet_MAC"
+          },
+          "Ethernet_MMC": {
+            "description": "Ethernet: MAC management counters",
+            "offset": 1073905920,
+            "type": "types.peripherals.Ethernet_MMC"
+          },
+          "Ethernet_PTP": {
+            "description": "Ethernet: Precision time protocol",
+            "offset": 1073907456,
+            "type": "types.peripherals.Ethernet_PTP"
+          },
+          "Ethernet_DMA": {
+            "description": "Ethernet: DMA controller operation",
+            "offset": 1073909760,
+            "type": "types.peripherals.Ethernet_DMA"
+          },
+          "CRC": {
+            "description": "Cryptographic processor",
+            "offset": 1073885184,
+            "type": "types.peripherals.CRC"
+          },
+          "OTG_FS_GLOBAL": {
+            "description": "USB on the go full speed",
+            "offset": 1342177280,
+            "type": "types.peripherals.OTG_FS_GLOBAL"
+          },
+          "OTG_FS_HOST": {
+            "description": "USB on the go full speed",
+            "offset": 1342178304,
+            "type": "types.peripherals.OTG_FS_HOST"
+          },
+          "OTG_FS_DEVICE": {
+            "description": "USB on the go full speed",
+            "offset": 1342179328,
+            "type": "types.peripherals.OTG_FS_DEVICE"
+          },
+          "OTG_FS_PWRCLK": {
+            "description": "USB on the go full speed",
+            "offset": 1342180864,
+            "type": "types.peripherals.OTG_FS_PWRCLK"
+          },
+          "CAN1": {
+            "description": "Controller area network",
+            "offset": 1073767424,
+            "type": "types.peripherals.CAN1"
+          },
+          "CAN2": {
+            "offset": 1073768448,
+            "type": "types.peripherals.CAN1"
+          },
+          "FLASH": {
+            "description": "FLASH",
+            "offset": 1073888256,
+            "type": "types.peripherals.FLASH"
+          },
+          "EXTI": {
+            "description": "External interrupt/event\n      controller",
+            "offset": 1073822720,
+            "type": "types.peripherals.EXTI"
+          },
+          "OTG_HS_GLOBAL": {
+            "description": "USB on the go high speed",
+            "offset": 1074003968,
+            "type": "types.peripherals.OTG_HS_GLOBAL"
+          },
+          "OTG_HS_HOST": {
+            "description": "USB on the go high speed",
+            "offset": 1074004992,
+            "type": "types.peripherals.OTG_HS_HOST"
+          },
+          "OTG_HS_DEVICE": {
+            "description": "USB on the go high speed",
+            "offset": 1074006016,
+            "type": "types.peripherals.OTG_HS_DEVICE"
+          },
+          "OTG_HS_PWRCLK": {
+            "description": "USB on the go high speed",
+            "offset": 1074007552,
+            "type": "types.peripherals.OTG_HS_PWRCLK"
+          },
+          "NVIC": {
+            "description": "Nested Vectored Interrupt\n      Controller",
+            "offset": 3758153984,
+            "type": "types.peripherals.NVIC"
+          },
+          "SAI1": {
+            "description": "Serial audio interface",
+            "offset": 1073829888,
+            "type": "types.peripherals.SAI1"
+          },
+          "LTDC": {
+            "description": "LCD-TFT Controller",
+            "offset": 1073833984,
+            "type": "types.peripherals.LTDC"
+          },
+          "HASH": {
+            "description": "Hash processor",
+            "offset": 1342571520,
+            "type": "types.peripherals.HASH"
+          },
+          "CRYP": {
+            "description": "Cryptographic processor",
+            "offset": 1342570496,
+            "type": "types.peripherals.CRYP"
+          },
+          "FPU": {
+            "description": "Floting point unit",
+            "offset": 3758157620,
+            "type": "types.peripherals.FPU"
+          },
+          "MPU": {
+            "description": "Memory protection unit",
+            "offset": 3758157200,
+            "type": "types.peripherals.MPU"
+          },
+          "STK": {
+            "description": "SysTick timer",
+            "offset": 3758153744,
+            "type": "types.peripherals.STK"
+          },
+          "SCB": {
+            "description": "System control block",
+            "offset": 3758157056,
+            "type": "types.peripherals.SCB"
+          },
+          "NVIC_STIR": {
+            "description": "Nested vectored interrupt\n      controller",
+            "offset": 3758157568,
+            "type": "types.peripherals.NVIC_STIR"
+          },
+          "FPU_CPACR": {
+            "description": "Floating point unit CPACR",
+            "offset": 3758157192,
+            "type": "types.peripherals.FPU_CPACR"
+          },
+          "SCB_ACTRL": {
+            "description": "System control block ACTLR",
+            "offset": 3758153736,
+            "type": "types.peripherals.SCB_ACTRL"
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/chips/STM32F407.zig b/src/chips/STM32F407.zig
new file mode 100644
index 000000000..bf7ea6912
--- /dev/null
+++ b/src/chips/STM32F407.zig
@@ -0,0 +1,20004 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    ///  STM32F407
+    pub const STM32F407 = struct {
+        pub const properties = struct {
+            pub const @"cpu.nvic_prio_bits" = "3";
+            pub const @"cpu.mpu" = "false";
+            pub const @"cpu.fpu" = "false";
+            pub const @"cpu.revision" = "r1p0";
+            pub const @"cpu.vendor_systick_config" = "false";
+            pub const @"cpu.endian" = "little";
+            pub const @"cpu.name" = "CM4";
+        };
+
+        pub const VectorTable = extern struct {
+            const Handler = micro.interrupt.Handler;
+            const unhandled = micro.interrupt.unhandled;
+
+            initial_stack_pointer: u32,
+            Reset: Handler = unhandled,
+            NMI: Handler = unhandled,
+            HardFault: Handler = unhandled,
+            MemManageFault: Handler = unhandled,
+            BusFault: Handler = unhandled,
+            UsageFault: Handler = unhandled,
+            reserved5: [4]u32 = undefined,
+            SVCall: Handler = unhandled,
+            DebugMonitor: Handler = unhandled,
+            reserved11: [1]u32 = undefined,
+            PendSV: Handler = unhandled,
+            SysTick: Handler = unhandled,
+            ///  Window Watchdog interrupt
+            WWDG: Handler = unhandled,
+            ///  PVD through EXTI line detection interrupt
+            PVD: Handler = unhandled,
+            ///  Tamper and TimeStamp interrupts through the EXTI line
+            TAMP_STAMP: Handler = unhandled,
+            ///  RTC Wakeup interrupt through the EXTI line
+            RTC_WKUP: Handler = unhandled,
+            reserved18: [1]u32 = undefined,
+            ///  RCC global interrupt
+            RCC: Handler = unhandled,
+            reserved20: [5]u32 = undefined,
+            ///  DMA1 Stream0 global interrupt
+            DMA1_Stream0: Handler = unhandled,
+            reserved26: [6]u32 = undefined,
+            ///  ADC1 global interrupt
+            ADC: Handler = unhandled,
+            ///  CAN1 TX interrupts
+            CAN1_TX: Handler = unhandled,
+            reserved34: [4]u32 = undefined,
+            ///  TIM1 Break interrupt and TIM9 global interrupt
+            TIM1_BRK_TIM9: Handler = unhandled,
+            ///  TIM1 Update interrupt and TIM10 global interrupt
+            TIM1_UP_TIM10: Handler = unhandled,
+            ///  TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
+            TIM1_TRG_COM_TIM11: Handler = unhandled,
+            reserved41: [1]u32 = undefined,
+            ///  TIM2 global interrupt
+            TIM2: Handler = unhandled,
+            ///  TIM3 global interrupt
+            TIM3: Handler = unhandled,
+            ///  TIM4 global interrupt
+            TIM4: Handler = unhandled,
+            ///  I2C1 event interrupt
+            I2C1_EV: Handler = unhandled,
+            reserved46: [1]u32 = undefined,
+            ///  I2C2 event interrupt
+            I2C2_EV: Handler = unhandled,
+            reserved48: [1]u32 = undefined,
+            ///  SPI1 global interrupt
+            SPI1: Handler = unhandled,
+            ///  SPI2 global interrupt
+            SPI2: Handler = unhandled,
+            ///  USART1 global interrupt
+            USART1: Handler = unhandled,
+            ///  USART2 global interrupt
+            USART2: Handler = unhandled,
+            ///  USART3 global interrupt
+            USART3: Handler = unhandled,
+            reserved54: [2]u32 = undefined,
+            ///  USB On-The-Go FS Wakeup through EXTI line interrupt
+            OTG_FS_WKUP: Handler = unhandled,
+            ///  TIM8 Break interrupt and TIM12 global interrupt
+            TIM8_BRK_TIM12: Handler = unhandled,
+            ///  TIM8 Update interrupt and TIM13 global interrupt
+            TIM8_UP_TIM13: Handler = unhandled,
+            ///  TIM8 Trigger and Commutation interrupts and TIM14 global interrupt
+            TIM8_TRG_COM_TIM14: Handler = unhandled,
+            reserved60: [2]u32 = undefined,
+            ///  FSMC global interrupt
+            FSMC: Handler = unhandled,
+            ///  SDIO global interrupt
+            SDIO: Handler = unhandled,
+            ///  TIM5 global interrupt
+            TIM5: Handler = unhandled,
+            ///  SPI3 global interrupt
+            SPI3: Handler = unhandled,
+            ///  UART4 global interrupt
+            UART4: Handler = unhandled,
+            ///  UART5 global interrupt
+            UART5: Handler = unhandled,
+            ///  TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt
+            TIM6_DAC: Handler = unhandled,
+            ///  TIM7 global interrupt
+            TIM7: Handler = unhandled,
+            ///  DMA2 Stream0 global interrupt
+            DMA2_Stream0: Handler = unhandled,
+            reserved71: [4]u32 = undefined,
+            ///  Ethernet global interrupt
+            ETH: Handler = unhandled,
+            reserved76: [1]u32 = undefined,
+            ///  CAN2 TX interrupts
+            CAN2_TX: Handler = unhandled,
+            reserved78: [7]u32 = undefined,
+            ///  USART6 global interrupt
+            USART6: Handler = unhandled,
+            ///  I2C3 event interrupt
+            I2C3_EV: Handler = unhandled,
+            reserved87: [1]u32 = undefined,
+            ///  USB On The Go HS End Point 1 Out global interrupt
+            OTG_HS_EP1_OUT: Handler = unhandled,
+            reserved89: [3]u32 = undefined,
+            ///  DCMI global interrupt
+            DCMI: Handler = unhandled,
+            ///  CRYP crypto global interrupt
+            CRYP: Handler = unhandled,
+            ///  Hash and Rng global interrupt
+            HASH_RNG: Handler = unhandled,
+            ///  FPU interrupt
+            FPU: Handler = unhandled,
+            reserved96: [6]u32 = undefined,
+            ///  LTDC global interrupt
+            LCD_TFT: Handler = unhandled,
+        };
+
+        pub const peripherals = struct {
+            ///  General purpose timers
+            pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000);
+            ///  General purpose timers
+            pub const TIM3 = @ptrCast(*volatile types.TIM3, 0x40000400);
+            ///  General purpose timers
+            pub const TIM4 = @ptrCast(*volatile types.TIM3, 0x40000800);
+            ///  General-purpose-timers
+            pub const TIM5 = @ptrCast(*volatile types.TIM5, 0x40000c00);
+            ///  Basic timers
+            pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000);
+            ///  Basic timers
+            pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400);
+            ///  General purpose timers
+            pub const TIM12 = @ptrCast(*volatile types.TIM9, 0x40001800);
+            ///  General-purpose-timers
+            pub const TIM13 = @ptrCast(*volatile types.TIM10, 0x40001c00);
+            ///  General-purpose-timers
+            pub const TIM14 = @ptrCast(*volatile types.TIM10, 0x40002000);
+            ///  Real-time clock
+            pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800);
+            ///  Window watchdog
+            pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00);
+            ///  Independent watchdog
+            pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000);
+            ///  Serial peripheral interface
+            pub const I2S2ext = @ptrCast(*volatile types.SPI1, 0x40003400);
+            ///  Serial peripheral interface
+            pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800);
+            ///  Serial peripheral interface
+            pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00);
+            ///  Serial peripheral interface
+            pub const I2S3ext = @ptrCast(*volatile types.SPI1, 0x40004000);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART2 = @ptrCast(*volatile types.USART6, 0x40004400);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART3 = @ptrCast(*volatile types.USART6, 0x40004800);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const UART4 = @ptrCast(*volatile types.UART4, 0x40004c00);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const UART5 = @ptrCast(*volatile types.UART4, 0x40005000);
+            ///  Inter-integrated circuit
+            pub const I2C1 = @ptrCast(*volatile types.I2C3, 0x40005400);
+            ///  Inter-integrated circuit
+            pub const I2C2 = @ptrCast(*volatile types.I2C3, 0x40005800);
+            ///  Inter-integrated circuit
+            pub const I2C3 = @ptrCast(*volatile types.I2C3, 0x40005c00);
+            ///  Controller area network
+            pub const CAN1 = @ptrCast(*volatile types.CAN1, 0x40006400);
+            ///  Controller area network
+            pub const CAN2 = @ptrCast(*volatile types.CAN1, 0x40006800);
+            ///  Power control
+            pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000);
+            ///  Digital-to-analog converter
+            pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const UART7 = @ptrCast(*volatile types.UART4, 0x40007800);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const UART8 = @ptrCast(*volatile types.UART4, 0x40007c00);
+            ///  Advanced-timers
+            pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40010000);
+            ///  Advanced-timers
+            pub const TIM8 = @ptrCast(*volatile types.TIM1, 0x40010400);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART1 = @ptrCast(*volatile types.USART6, 0x40011000);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART6 = @ptrCast(*volatile types.USART6, 0x40011400);
+            ///  Analog-to-digital converter
+            pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x40012000);
+            ///  Analog-to-digital converter
+            pub const ADC2 = @ptrCast(*volatile types.ADC1, 0x40012100);
+            ///  Analog-to-digital converter
+            pub const ADC3 = @ptrCast(*volatile types.ADC1, 0x40012200);
+            ///  Common ADC registers
+            pub const C_ADC = @ptrCast(*volatile types.C_ADC, 0x40012300);
+            ///  Secure digital input/output interface
+            pub const SDIO = @ptrCast(*volatile types.SDIO, 0x40012c00);
+            ///  Serial peripheral interface
+            pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000);
+            ///  Serial peripheral interface
+            pub const SPI4 = @ptrCast(*volatile types.SPI1, 0x40013400);
+            ///  System configuration controller
+            pub const SYSCFG = @ptrCast(*volatile types.SYSCFG, 0x40013800);
+            ///  External interrupt/event controller
+            pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40013c00);
+            ///  General purpose timers
+            pub const TIM9 = @ptrCast(*volatile types.TIM9, 0x40014000);
+            ///  General-purpose-timers
+            pub const TIM10 = @ptrCast(*volatile types.TIM10, 0x40014400);
+            ///  General-purpose-timers
+            pub const TIM11 = @ptrCast(*volatile types.TIM11, 0x40014800);
+            ///  Serial peripheral interface
+            pub const SPI5 = @ptrCast(*volatile types.SPI1, 0x40015000);
+            ///  Serial peripheral interface
+            pub const SPI6 = @ptrCast(*volatile types.SPI1, 0x40015400);
+            ///  Serial audio interface
+            pub const SAI1 = @ptrCast(*volatile types.SAI1, 0x40015800);
+            ///  LCD-TFT Controller
+            pub const LTDC = @ptrCast(*volatile types.LTDC, 0x40016800);
+            ///  General-purpose I/Os
+            pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x40020000);
+            ///  General-purpose I/Os
+            pub const GPIOB = @ptrCast(*volatile types.GPIOB, 0x40020400);
+            ///  General-purpose I/Os
+            pub const GPIOC = @ptrCast(*volatile types.GPIOI, 0x40020800);
+            ///  General-purpose I/Os
+            pub const GPIOD = @ptrCast(*volatile types.GPIOI, 0x40020c00);
+            ///  General-purpose I/Os
+            pub const GPIOE = @ptrCast(*volatile types.GPIOI, 0x40021000);
+            ///  General-purpose I/Os
+            pub const GPIOF = @ptrCast(*volatile types.GPIOI, 0x40021400);
+            ///  General-purpose I/Os
+            pub const GPIOG = @ptrCast(*volatile types.GPIOI, 0x40021800);
+            ///  General-purpose I/Os
+            pub const GPIOH = @ptrCast(*volatile types.GPIOI, 0x40021c00);
+            ///  General-purpose I/Os
+            pub const GPIOI = @ptrCast(*volatile types.GPIOI, 0x40022000);
+            ///  General-purpose I/Os
+            pub const GPIOJ = @ptrCast(*volatile types.GPIOI, 0x40022400);
+            ///  General-purpose I/Os
+            pub const GPIOK = @ptrCast(*volatile types.GPIOI, 0x40022800);
+            ///  Cryptographic processor
+            pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000);
+            ///  Reset and clock control
+            pub const RCC = @ptrCast(*volatile types.RCC, 0x40023800);
+            ///  FLASH
+            pub const FLASH = @ptrCast(*volatile types.FLASH, 0x40023c00);
+            ///  DMA controller
+            pub const DMA1 = @ptrCast(*volatile types.DMA2, 0x40026000);
+            ///  DMA controller
+            pub const DMA2 = @ptrCast(*volatile types.DMA2, 0x40026400);
+            ///  Ethernet: media access control (MAC)
+            pub const Ethernet_MAC = @ptrCast(*volatile types.Ethernet_MAC, 0x40028000);
+            ///  Ethernet: MAC management counters
+            pub const Ethernet_MMC = @ptrCast(*volatile types.Ethernet_MMC, 0x40028100);
+            ///  Ethernet: Precision time protocol
+            pub const Ethernet_PTP = @ptrCast(*volatile types.Ethernet_PTP, 0x40028700);
+            ///  Ethernet: DMA controller operation
+            pub const Ethernet_DMA = @ptrCast(*volatile types.Ethernet_DMA, 0x40029000);
+            ///  USB on the go high speed
+            pub const OTG_HS_GLOBAL = @ptrCast(*volatile types.OTG_HS_GLOBAL, 0x40040000);
+            ///  USB on the go high speed
+            pub const OTG_HS_HOST = @ptrCast(*volatile types.OTG_HS_HOST, 0x40040400);
+            ///  USB on the go high speed
+            pub const OTG_HS_DEVICE = @ptrCast(*volatile types.OTG_HS_DEVICE, 0x40040800);
+            ///  USB on the go high speed
+            pub const OTG_HS_PWRCLK = @ptrCast(*volatile types.OTG_HS_PWRCLK, 0x40040e00);
+            ///  USB on the go full speed
+            pub const OTG_FS_GLOBAL = @ptrCast(*volatile types.OTG_FS_GLOBAL, 0x50000000);
+            ///  USB on the go full speed
+            pub const OTG_FS_HOST = @ptrCast(*volatile types.OTG_FS_HOST, 0x50000400);
+            ///  USB on the go full speed
+            pub const OTG_FS_DEVICE = @ptrCast(*volatile types.OTG_FS_DEVICE, 0x50000800);
+            ///  USB on the go full speed
+            pub const OTG_FS_PWRCLK = @ptrCast(*volatile types.OTG_FS_PWRCLK, 0x50000e00);
+            ///  Digital camera interface
+            pub const DCMI = @ptrCast(*volatile types.DCMI, 0x50050000);
+            ///  Cryptographic processor
+            pub const CRYP = @ptrCast(*volatile types.CRYP, 0x50060000);
+            ///  Hash processor
+            pub const HASH = @ptrCast(*volatile types.HASH, 0x50060400);
+            ///  Random number generator
+            pub const RNG = @ptrCast(*volatile types.RNG, 0x50060800);
+            ///  Flexible static memory controller
+            pub const FSMC = @ptrCast(*volatile types.FSMC, 0xa0000000);
+            ///  System control block ACTLR
+            pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008);
+            ///  SysTick timer
+            pub const STK = @ptrCast(*volatile types.STK, 0xe000e010);
+            ///  Nested Vectored Interrupt Controller
+            pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100);
+            ///  System control block
+            pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00);
+            ///  Floating point unit CPACR
+            pub const FPU_CPACR = @ptrCast(*volatile types.FPU_CPACR, 0xe000ed88);
+            ///  Memory protection unit
+            pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90);
+            ///  Nested vectored interrupt controller
+            pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00);
+            ///  Floting point unit
+            pub const FPU = @ptrCast(*volatile types.FPU, 0xe000ef34);
+            ///  Debug support
+            pub const DBG = @ptrCast(*volatile types.DBG, 0xe0042000);
+        };
+    };
+};
+
+pub const types = struct {
+    ///  Random number generator
+    pub const RNG = extern struct {
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Random number generator enable
+            RNGEN: u1,
+            ///  Interrupt enable
+            IE: u1,
+            padding: u28,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Data ready
+            DRDY: u1,
+            ///  Clock error current status
+            CECS: u1,
+            ///  Seed error current status
+            SECS: u1,
+            reserved5: u2,
+            ///  Clock error interrupt status
+            CEIS: u1,
+            ///  Seed error interrupt status
+            SEIS: u1,
+            padding: u25,
+        }),
+        ///  data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Random data
+            RNDATA: u32,
+        }),
+    };
+
+    ///  Digital camera interface
+    pub const DCMI = extern struct {
+        ///  control register 1
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Capture enable
+            CAPTURE: u1,
+            ///  Capture mode
+            CM: u1,
+            ///  Crop feature
+            CROP: u1,
+            ///  JPEG format
+            JPEG: u1,
+            ///  Embedded synchronization select
+            ESS: u1,
+            ///  Pixel clock polarity
+            PCKPOL: u1,
+            ///  Horizontal synchronization polarity
+            HSPOL: u1,
+            ///  Vertical synchronization polarity
+            VSPOL: u1,
+            ///  Frame capture rate control
+            FCRC: u2,
+            ///  Extended data mode
+            EDM: u2,
+            reserved14: u2,
+            ///  DCMI enable
+            ENABLE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  HSYNC
+            HSYNC: u1,
+            ///  VSYNC
+            VSYNC: u1,
+            ///  FIFO not empty
+            FNE: u1,
+            padding: u29,
+        }),
+        ///  raw interrupt status register
+        RIS: mmio.Mmio(packed struct(u32) {
+            ///  Capture complete raw interrupt status
+            FRAME_RIS: u1,
+            ///  Overrun raw interrupt status
+            OVR_RIS: u1,
+            ///  Synchronization error raw interrupt status
+            ERR_RIS: u1,
+            ///  VSYNC raw interrupt status
+            VSYNC_RIS: u1,
+            ///  Line raw interrupt status
+            LINE_RIS: u1,
+            padding: u27,
+        }),
+        ///  interrupt enable register
+        IER: mmio.Mmio(packed struct(u32) {
+            ///  Capture complete interrupt enable
+            FRAME_IE: u1,
+            ///  Overrun interrupt enable
+            OVR_IE: u1,
+            ///  Synchronization error interrupt enable
+            ERR_IE: u1,
+            ///  VSYNC interrupt enable
+            VSYNC_IE: u1,
+            ///  Line interrupt enable
+            LINE_IE: u1,
+            padding: u27,
+        }),
+        ///  masked interrupt status register
+        MIS: mmio.Mmio(packed struct(u32) {
+            ///  Capture complete masked interrupt status
+            FRAME_MIS: u1,
+            ///  Overrun masked interrupt status
+            OVR_MIS: u1,
+            ///  Synchronization error masked interrupt status
+            ERR_MIS: u1,
+            ///  VSYNC masked interrupt status
+            VSYNC_MIS: u1,
+            ///  Line masked interrupt status
+            LINE_MIS: u1,
+            padding: u27,
+        }),
+        ///  interrupt clear register
+        ICR: mmio.Mmio(packed struct(u32) {
+            ///  Capture complete interrupt status clear
+            FRAME_ISC: u1,
+            ///  Overrun interrupt status clear
+            OVR_ISC: u1,
+            ///  Synchronization error interrupt status clear
+            ERR_ISC: u1,
+            ///  Vertical synch interrupt status clear
+            VSYNC_ISC: u1,
+            ///  line interrupt status clear
+            LINE_ISC: u1,
+            padding: u27,
+        }),
+        ///  embedded synchronization code register
+        ESCR: mmio.Mmio(packed struct(u32) {
+            ///  Frame start delimiter code
+            FSC: u8,
+            ///  Line start delimiter code
+            LSC: u8,
+            ///  Line end delimiter code
+            LEC: u8,
+            ///  Frame end delimiter code
+            FEC: u8,
+        }),
+        ///  embedded synchronization unmask register
+        ESUR: mmio.Mmio(packed struct(u32) {
+            ///  Frame start delimiter unmask
+            FSU: u8,
+            ///  Line start delimiter unmask
+            LSU: u8,
+            ///  Line end delimiter unmask
+            LEU: u8,
+            ///  Frame end delimiter unmask
+            FEU: u8,
+        }),
+        ///  crop window start
+        CWSTRT: mmio.Mmio(packed struct(u32) {
+            ///  Horizontal offset count
+            HOFFCNT: u14,
+            reserved16: u2,
+            ///  Vertical start line count
+            VST: u13,
+            padding: u3,
+        }),
+        ///  crop window size
+        CWSIZE: mmio.Mmio(packed struct(u32) {
+            ///  Capture count
+            CAPCNT: u14,
+            reserved16: u2,
+            ///  Vertical line count
+            VLINE: u14,
+            padding: u2,
+        }),
+        ///  data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data byte 0
+            Byte0: u8,
+            ///  Data byte 1
+            Byte1: u8,
+            ///  Data byte 2
+            Byte2: u8,
+            ///  Data byte 3
+            Byte3: u8,
+        }),
+    };
+
+    ///  Flexible static memory controller
+    pub const FSMC = extern struct {
+        ///  SRAM/NOR-Flash chip-select control register 1
+        BCR1: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            reserved11: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 1
+        BTR1: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 2
+        BCR2: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 2
+        BTR2: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 3
+        BCR3: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 3
+        BTR3: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 4
+        BCR4: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 4
+        BTR4: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved96: [64]u8,
+        ///  PC Card/NAND Flash control register 2
+        PCR2: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 2
+        SR2: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 2
+        PMEM2: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 2
+        PATT2: mmio.Mmio(packed struct(u32) {
+            ///  ATTSETx
+            ATTSETx: u8,
+            ///  ATTWAITx
+            ATTWAITx: u8,
+            ///  ATTHOLDx
+            ATTHOLDx: u8,
+            ///  ATTHIZx
+            ATTHIZx: u8,
+        }),
+        reserved116: [4]u8,
+        ///  ECC result register 2
+        ECCR2: mmio.Mmio(packed struct(u32) {
+            ///  ECCx
+            ECCx: u32,
+        }),
+        reserved128: [8]u8,
+        ///  PC Card/NAND Flash control register 3
+        PCR3: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 3
+        SR3: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 3
+        PMEM3: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 3
+        PATT3: mmio.Mmio(packed struct(u32) {
+            ///  ATTSETx
+            ATTSETx: u8,
+            ///  ATTWAITx
+            ATTWAITx: u8,
+            ///  ATTHOLDx
+            ATTHOLDx: u8,
+            ///  ATTHIZx
+            ATTHIZx: u8,
+        }),
+        reserved148: [4]u8,
+        ///  ECC result register 3
+        ECCR3: mmio.Mmio(packed struct(u32) {
+            ///  ECCx
+            ECCx: u32,
+        }),
+        reserved160: [8]u8,
+        ///  PC Card/NAND Flash control register 4
+        PCR4: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 4
+        SR4: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 4
+        PMEM4: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 4
+        PATT4: mmio.Mmio(packed struct(u32) {
+            ///  ATTSETx
+            ATTSETx: u8,
+            ///  ATTWAITx
+            ATTWAITx: u8,
+            ///  ATTHOLDx
+            ATTHOLDx: u8,
+            ///  ATTHIZx
+            ATTHIZx: u8,
+        }),
+        ///  I/O space timing register 4
+        PIO4: mmio.Mmio(packed struct(u32) {
+            ///  IOSETx
+            IOSETx: u8,
+            ///  IOWAITx
+            IOWAITx: u8,
+            ///  IOHOLDx
+            IOHOLDx: u8,
+            ///  IOHIZx
+            IOHIZx: u8,
+        }),
+        reserved260: [80]u8,
+        ///  SRAM/NOR-Flash write timing registers 1
+        BWTR1: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            reserved20: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved268: [4]u8,
+        ///  SRAM/NOR-Flash write timing registers 2
+        BWTR2: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            reserved20: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved276: [4]u8,
+        ///  SRAM/NOR-Flash write timing registers 3
+        BWTR3: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            reserved20: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved284: [4]u8,
+        ///  SRAM/NOR-Flash write timing registers 4
+        BWTR4: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            reserved20: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+    };
+
+    ///  Debug support
+    pub const DBG = extern struct {
+        ///  IDCODE
+        DBGMCU_IDCODE: mmio.Mmio(packed struct(u32) {
+            ///  DEV_ID
+            DEV_ID: u12,
+            reserved16: u4,
+            ///  REV_ID
+            REV_ID: u16,
+        }),
+        ///  Control Register
+        DBGMCU_CR: mmio.Mmio(packed struct(u32) {
+            ///  DBG_SLEEP
+            DBG_SLEEP: u1,
+            ///  DBG_STOP
+            DBG_STOP: u1,
+            ///  DBG_STANDBY
+            DBG_STANDBY: u1,
+            reserved5: u2,
+            ///  TRACE_IOEN
+            TRACE_IOEN: u1,
+            ///  TRACE_MODE
+            TRACE_MODE: u2,
+            reserved16: u8,
+            ///  DBG_I2C2_SMBUS_TIMEOUT
+            DBG_I2C2_SMBUS_TIMEOUT: u1,
+            ///  DBG_TIM8_STOP
+            DBG_TIM8_STOP: u1,
+            ///  DBG_TIM5_STOP
+            DBG_TIM5_STOP: u1,
+            ///  DBG_TIM6_STOP
+            DBG_TIM6_STOP: u1,
+            ///  DBG_TIM7_STOP
+            DBG_TIM7_STOP: u1,
+            padding: u11,
+        }),
+        ///  Debug MCU APB1 Freeze registe
+        DBGMCU_APB1_FZ: mmio.Mmio(packed struct(u32) {
+            ///  DBG_TIM2_STOP
+            DBG_TIM2_STOP: u1,
+            ///  DBG_TIM3 _STOP
+            DBG_TIM3_STOP: u1,
+            ///  DBG_TIM4_STOP
+            DBG_TIM4_STOP: u1,
+            ///  DBG_TIM5_STOP
+            DBG_TIM5_STOP: u1,
+            ///  DBG_TIM6_STOP
+            DBG_TIM6_STOP: u1,
+            ///  DBG_TIM7_STOP
+            DBG_TIM7_STOP: u1,
+            ///  DBG_TIM12_STOP
+            DBG_TIM12_STOP: u1,
+            ///  DBG_TIM13_STOP
+            DBG_TIM13_STOP: u1,
+            ///  DBG_TIM14_STOP
+            DBG_TIM14_STOP: u1,
+            reserved11: u2,
+            ///  DBG_WWDG_STOP
+            DBG_WWDG_STOP: u1,
+            ///  DBG_IWDEG_STOP
+            DBG_IWDEG_STOP: u1,
+            reserved21: u8,
+            ///  DBG_J2C1_SMBUS_TIMEOUT
+            DBG_J2C1_SMBUS_TIMEOUT: u1,
+            ///  DBG_J2C2_SMBUS_TIMEOUT
+            DBG_J2C2_SMBUS_TIMEOUT: u1,
+            ///  DBG_J2C3SMBUS_TIMEOUT
+            DBG_J2C3SMBUS_TIMEOUT: u1,
+            reserved25: u1,
+            ///  DBG_CAN1_STOP
+            DBG_CAN1_STOP: u1,
+            ///  DBG_CAN2_STOP
+            DBG_CAN2_STOP: u1,
+            padding: u5,
+        }),
+        ///  Debug MCU APB2 Freeze registe
+        DBGMCU_APB2_FZ: mmio.Mmio(packed struct(u32) {
+            ///  TIM1 counter stopped when core is halted
+            DBG_TIM1_STOP: u1,
+            ///  TIM8 counter stopped when core is halted
+            DBG_TIM8_STOP: u1,
+            reserved16: u14,
+            ///  TIM9 counter stopped when core is halted
+            DBG_TIM9_STOP: u1,
+            ///  TIM10 counter stopped when core is halted
+            DBG_TIM10_STOP: u1,
+            ///  TIM11 counter stopped when core is halted
+            DBG_TIM11_STOP: u1,
+            padding: u13,
+        }),
+    };
+
+    ///  DMA controller
+    pub const DMA2 = extern struct {
+        ///  low interrupt status register
+        LISR: mmio.Mmio(packed struct(u32) {
+            ///  Stream x FIFO error interrupt flag (x=3..0)
+            FEIF0: u1,
+            reserved2: u1,
+            ///  Stream x direct mode error interrupt flag (x=3..0)
+            DMEIF0: u1,
+            ///  Stream x transfer error interrupt flag (x=3..0)
+            TEIF0: u1,
+            ///  Stream x half transfer interrupt flag (x=3..0)
+            HTIF0: u1,
+            ///  Stream x transfer complete interrupt flag (x = 3..0)
+            TCIF0: u1,
+            ///  Stream x FIFO error interrupt flag (x=3..0)
+            FEIF1: u1,
+            reserved8: u1,
+            ///  Stream x direct mode error interrupt flag (x=3..0)
+            DMEIF1: u1,
+            ///  Stream x transfer error interrupt flag (x=3..0)
+            TEIF1: u1,
+            ///  Stream x half transfer interrupt flag (x=3..0)
+            HTIF1: u1,
+            ///  Stream x transfer complete interrupt flag (x = 3..0)
+            TCIF1: u1,
+            reserved16: u4,
+            ///  Stream x FIFO error interrupt flag (x=3..0)
+            FEIF2: u1,
+            reserved18: u1,
+            ///  Stream x direct mode error interrupt flag (x=3..0)
+            DMEIF2: u1,
+            ///  Stream x transfer error interrupt flag (x=3..0)
+            TEIF2: u1,
+            ///  Stream x half transfer interrupt flag (x=3..0)
+            HTIF2: u1,
+            ///  Stream x transfer complete interrupt flag (x = 3..0)
+            TCIF2: u1,
+            ///  Stream x FIFO error interrupt flag (x=3..0)
+            FEIF3: u1,
+            reserved24: u1,
+            ///  Stream x direct mode error interrupt flag (x=3..0)
+            DMEIF3: u1,
+            ///  Stream x transfer error interrupt flag (x=3..0)
+            TEIF3: u1,
+            ///  Stream x half transfer interrupt flag (x=3..0)
+            HTIF3: u1,
+            ///  Stream x transfer complete interrupt flag (x = 3..0)
+            TCIF3: u1,
+            padding: u4,
+        }),
+        ///  high interrupt status register
+        HISR: mmio.Mmio(packed struct(u32) {
+            ///  Stream x FIFO error interrupt flag (x=7..4)
+            FEIF4: u1,
+            reserved2: u1,
+            ///  Stream x direct mode error interrupt flag (x=7..4)
+            DMEIF4: u1,
+            ///  Stream x transfer error interrupt flag (x=7..4)
+            TEIF4: u1,
+            ///  Stream x half transfer interrupt flag (x=7..4)
+            HTIF4: u1,
+            ///  Stream x transfer complete interrupt flag (x=7..4)
+            TCIF4: u1,
+            ///  Stream x FIFO error interrupt flag (x=7..4)
+            FEIF5: u1,
+            reserved8: u1,
+            ///  Stream x direct mode error interrupt flag (x=7..4)
+            DMEIF5: u1,
+            ///  Stream x transfer error interrupt flag (x=7..4)
+            TEIF5: u1,
+            ///  Stream x half transfer interrupt flag (x=7..4)
+            HTIF5: u1,
+            ///  Stream x transfer complete interrupt flag (x=7..4)
+            TCIF5: u1,
+            reserved16: u4,
+            ///  Stream x FIFO error interrupt flag (x=7..4)
+            FEIF6: u1,
+            reserved18: u1,
+            ///  Stream x direct mode error interrupt flag (x=7..4)
+            DMEIF6: u1,
+            ///  Stream x transfer error interrupt flag (x=7..4)
+            TEIF6: u1,
+            ///  Stream x half transfer interrupt flag (x=7..4)
+            HTIF6: u1,
+            ///  Stream x transfer complete interrupt flag (x=7..4)
+            TCIF6: u1,
+            ///  Stream x FIFO error interrupt flag (x=7..4)
+            FEIF7: u1,
+            reserved24: u1,
+            ///  Stream x direct mode error interrupt flag (x=7..4)
+            DMEIF7: u1,
+            ///  Stream x transfer error interrupt flag (x=7..4)
+            TEIF7: u1,
+            ///  Stream x half transfer interrupt flag (x=7..4)
+            HTIF7: u1,
+            ///  Stream x transfer complete interrupt flag (x=7..4)
+            TCIF7: u1,
+            padding: u4,
+        }),
+        ///  low interrupt flag clear register
+        LIFCR: mmio.Mmio(packed struct(u32) {
+            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
+            CFEIF0: u1,
+            reserved2: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
+            CDMEIF0: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 3..0)
+            CTEIF0: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 3..0)
+            CHTIF0: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
+            CTCIF0: u1,
+            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
+            CFEIF1: u1,
+            reserved8: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
+            CDMEIF1: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 3..0)
+            CTEIF1: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 3..0)
+            CHTIF1: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
+            CTCIF1: u1,
+            reserved16: u4,
+            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
+            CFEIF2: u1,
+            reserved18: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
+            CDMEIF2: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 3..0)
+            CTEIF2: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 3..0)
+            CHTIF2: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
+            CTCIF2: u1,
+            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
+            CFEIF3: u1,
+            reserved24: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
+            CDMEIF3: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 3..0)
+            CTEIF3: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 3..0)
+            CHTIF3: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
+            CTCIF3: u1,
+            padding: u4,
+        }),
+        ///  high interrupt flag clear register
+        HIFCR: mmio.Mmio(packed struct(u32) {
+            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
+            CFEIF4: u1,
+            reserved2: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
+            CDMEIF4: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 7..4)
+            CTEIF4: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 7..4)
+            CHTIF4: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
+            CTCIF4: u1,
+            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
+            CFEIF5: u1,
+            reserved8: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
+            CDMEIF5: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 7..4)
+            CTEIF5: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 7..4)
+            CHTIF5: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
+            CTCIF5: u1,
+            reserved16: u4,
+            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
+            CFEIF6: u1,
+            reserved18: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
+            CDMEIF6: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 7..4)
+            CTEIF6: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 7..4)
+            CHTIF6: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
+            CTCIF6: u1,
+            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
+            CFEIF7: u1,
+            reserved24: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
+            CDMEIF7: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 7..4)
+            CTEIF7: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 7..4)
+            CHTIF7: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
+            CTCIF7: u1,
+            padding: u4,
+        }),
+        ///  stream x configuration register
+        S0CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            reserved21: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S0NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S0PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S0M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S0M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S0FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S1CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S1NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S1PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S1M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S1M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S1FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S2CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S2NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S2PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S2M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S2M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S2FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S3CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S3NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S3PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S3M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S3M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S3FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S4CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S4NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S4PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S4M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S4M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S4FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S5CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S5NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S5PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S5M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S5M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S5FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S6CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S6NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S6PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S6M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S6M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S6FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S7CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S7NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S7PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S7M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S7M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S7FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+    };
+
+    ///  System control block ACTLR
+    pub const SCB_ACTRL = extern struct {
+        ///  Auxiliary control register
+        ACTRL: mmio.Mmio(packed struct(u32) {
+            ///  DISMCYCINT
+            DISMCYCINT: u1,
+            ///  DISDEFWBUF
+            DISDEFWBUF: u1,
+            ///  DISFOLD
+            DISFOLD: u1,
+            reserved8: u5,
+            ///  DISFPCA
+            DISFPCA: u1,
+            ///  DISOOFP
+            DISOOFP: u1,
+            padding: u22,
+        }),
+    };
+
+    ///  Reset and clock control
+    pub const RCC = extern struct {
+        ///  clock control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Internal high-speed clock enable
+            HSION: u1,
+            ///  Internal high-speed clock ready flag
+            HSIRDY: u1,
+            reserved3: u1,
+            ///  Internal high-speed clock trimming
+            HSITRIM: u5,
+            ///  Internal high-speed clock calibration
+            HSICAL: u8,
+            ///  HSE clock enable
+            HSEON: u1,
+            ///  HSE clock ready flag
+            HSERDY: u1,
+            ///  HSE clock bypass
+            HSEBYP: u1,
+            ///  Clock security system enable
+            CSSON: u1,
+            reserved24: u4,
+            ///  Main PLL (PLL) enable
+            PLLON: u1,
+            ///  Main PLL (PLL) clock ready flag
+            PLLRDY: u1,
+            ///  PLLI2S enable
+            PLLI2SON: u1,
+            ///  PLLI2S clock ready flag
+            PLLI2SRDY: u1,
+            padding: u4,
+        }),
+        ///  PLL configuration register
+        PLLCFGR: mmio.Mmio(packed struct(u32) {
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM0: u1,
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM1: u1,
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM2: u1,
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM3: u1,
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM4: u1,
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM5: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN0: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN1: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN2: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN3: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN4: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN5: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN6: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN7: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN8: u1,
+            reserved16: u1,
+            ///  Main PLL (PLL) division factor for main system clock
+            PLLP0: u1,
+            ///  Main PLL (PLL) division factor for main system clock
+            PLLP1: u1,
+            reserved22: u4,
+            ///  Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
+            PLLSRC: u1,
+            reserved24: u1,
+            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
+            PLLQ0: u1,
+            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
+            PLLQ1: u1,
+            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
+            PLLQ2: u1,
+            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
+            PLLQ3: u1,
+            padding: u4,
+        }),
+        ///  clock configuration register
+        CFGR: mmio.Mmio(packed struct(u32) {
+            ///  System clock switch
+            SW0: u1,
+            ///  System clock switch
+            SW1: u1,
+            ///  System clock switch status
+            SWS0: u1,
+            ///  System clock switch status
+            SWS1: u1,
+            ///  AHB prescaler
+            HPRE: u4,
+            reserved10: u2,
+            ///  APB Low speed prescaler (APB1)
+            PPRE1: u3,
+            ///  APB high-speed prescaler (APB2)
+            PPRE2: u3,
+            ///  HSE division factor for RTC clock
+            RTCPRE: u5,
+            ///  Microcontroller clock output 1
+            MCO1: u2,
+            ///  I2S clock selection
+            I2SSRC: u1,
+            ///  MCO1 prescaler
+            MCO1PRE: u3,
+            ///  MCO2 prescaler
+            MCO2PRE: u3,
+            ///  Microcontroller clock output 2
+            MCO2: u2,
+        }),
+        ///  clock interrupt register
+        CIR: mmio.Mmio(packed struct(u32) {
+            ///  LSI ready interrupt flag
+            LSIRDYF: u1,
+            ///  LSE ready interrupt flag
+            LSERDYF: u1,
+            ///  HSI ready interrupt flag
+            HSIRDYF: u1,
+            ///  HSE ready interrupt flag
+            HSERDYF: u1,
+            ///  Main PLL (PLL) ready interrupt flag
+            PLLRDYF: u1,
+            ///  PLLI2S ready interrupt flag
+            PLLI2SRDYF: u1,
+            reserved7: u1,
+            ///  Clock security system interrupt flag
+            CSSF: u1,
+            ///  LSI ready interrupt enable
+            LSIRDYIE: u1,
+            ///  LSE ready interrupt enable
+            LSERDYIE: u1,
+            ///  HSI ready interrupt enable
+            HSIRDYIE: u1,
+            ///  HSE ready interrupt enable
+            HSERDYIE: u1,
+            ///  Main PLL (PLL) ready interrupt enable
+            PLLRDYIE: u1,
+            ///  PLLI2S ready interrupt enable
+            PLLI2SRDYIE: u1,
+            reserved16: u2,
+            ///  LSI ready interrupt clear
+            LSIRDYC: u1,
+            ///  LSE ready interrupt clear
+            LSERDYC: u1,
+            ///  HSI ready interrupt clear
+            HSIRDYC: u1,
+            ///  HSE ready interrupt clear
+            HSERDYC: u1,
+            ///  Main PLL(PLL) ready interrupt clear
+            PLLRDYC: u1,
+            ///  PLLI2S ready interrupt clear
+            PLLI2SRDYC: u1,
+            reserved23: u1,
+            ///  Clock security system interrupt clear
+            CSSC: u1,
+            padding: u8,
+        }),
+        ///  AHB1 peripheral reset register
+        AHB1RSTR: mmio.Mmio(packed struct(u32) {
+            ///  IO port A reset
+            GPIOARST: u1,
+            ///  IO port B reset
+            GPIOBRST: u1,
+            ///  IO port C reset
+            GPIOCRST: u1,
+            ///  IO port D reset
+            GPIODRST: u1,
+            ///  IO port E reset
+            GPIOERST: u1,
+            ///  IO port F reset
+            GPIOFRST: u1,
+            ///  IO port G reset
+            GPIOGRST: u1,
+            ///  IO port H reset
+            GPIOHRST: u1,
+            ///  IO port I reset
+            GPIOIRST: u1,
+            reserved12: u3,
+            ///  CRC reset
+            CRCRST: u1,
+            reserved21: u8,
+            ///  DMA2 reset
+            DMA1RST: u1,
+            ///  DMA2 reset
+            DMA2RST: u1,
+            reserved25: u2,
+            ///  Ethernet MAC reset
+            ETHMACRST: u1,
+            reserved29: u3,
+            ///  USB OTG HS module reset
+            OTGHSRST: u1,
+            padding: u2,
+        }),
+        ///  AHB2 peripheral reset register
+        AHB2RSTR: mmio.Mmio(packed struct(u32) {
+            ///  Camera interface reset
+            DCMIRST: u1,
+            reserved6: u5,
+            ///  Random number generator module reset
+            RNGRST: u1,
+            ///  USB OTG FS module reset
+            OTGFSRST: u1,
+            padding: u24,
+        }),
+        ///  AHB3 peripheral reset register
+        AHB3RSTR: mmio.Mmio(packed struct(u32) {
+            ///  Flexible static memory controller module reset
+            FSMCRST: u1,
+            padding: u31,
+        }),
+        reserved32: [4]u8,
+        ///  APB1 peripheral reset register
+        APB1RSTR: mmio.Mmio(packed struct(u32) {
+            ///  TIM2 reset
+            TIM2RST: u1,
+            ///  TIM3 reset
+            TIM3RST: u1,
+            ///  TIM4 reset
+            TIM4RST: u1,
+            ///  TIM5 reset
+            TIM5RST: u1,
+            ///  TIM6 reset
+            TIM6RST: u1,
+            ///  TIM7 reset
+            TIM7RST: u1,
+            ///  TIM12 reset
+            TIM12RST: u1,
+            ///  TIM13 reset
+            TIM13RST: u1,
+            ///  TIM14 reset
+            TIM14RST: u1,
+            reserved11: u2,
+            ///  Window watchdog reset
+            WWDGRST: u1,
+            reserved14: u2,
+            ///  SPI 2 reset
+            SPI2RST: u1,
+            ///  SPI 3 reset
+            SPI3RST: u1,
+            reserved17: u1,
+            ///  USART 2 reset
+            UART2RST: u1,
+            ///  USART 3 reset
+            UART3RST: u1,
+            ///  USART 4 reset
+            UART4RST: u1,
+            ///  USART 5 reset
+            UART5RST: u1,
+            ///  I2C 1 reset
+            I2C1RST: u1,
+            ///  I2C 2 reset
+            I2C2RST: u1,
+            ///  I2C3 reset
+            I2C3RST: u1,
+            reserved25: u1,
+            ///  CAN1 reset
+            CAN1RST: u1,
+            ///  CAN2 reset
+            CAN2RST: u1,
+            reserved28: u1,
+            ///  Power interface reset
+            PWRRST: u1,
+            ///  DAC reset
+            DACRST: u1,
+            padding: u2,
+        }),
+        ///  APB2 peripheral reset register
+        APB2RSTR: mmio.Mmio(packed struct(u32) {
+            ///  TIM1 reset
+            TIM1RST: u1,
+            ///  TIM8 reset
+            TIM8RST: u1,
+            reserved4: u2,
+            ///  USART1 reset
+            USART1RST: u1,
+            ///  USART6 reset
+            USART6RST: u1,
+            reserved8: u2,
+            ///  ADC interface reset (common to all ADCs)
+            ADCRST: u1,
+            reserved11: u2,
+            ///  SDIO reset
+            SDIORST: u1,
+            ///  SPI 1 reset
+            SPI1RST: u1,
+            reserved14: u1,
+            ///  System configuration controller reset
+            SYSCFGRST: u1,
+            reserved16: u1,
+            ///  TIM9 reset
+            TIM9RST: u1,
+            ///  TIM10 reset
+            TIM10RST: u1,
+            ///  TIM11 reset
+            TIM11RST: u1,
+            padding: u13,
+        }),
+        reserved48: [8]u8,
+        ///  AHB1 peripheral clock register
+        AHB1ENR: mmio.Mmio(packed struct(u32) {
+            ///  IO port A clock enable
+            GPIOAEN: u1,
+            ///  IO port B clock enable
+            GPIOBEN: u1,
+            ///  IO port C clock enable
+            GPIOCEN: u1,
+            ///  IO port D clock enable
+            GPIODEN: u1,
+            ///  IO port E clock enable
+            GPIOEEN: u1,
+            ///  IO port F clock enable
+            GPIOFEN: u1,
+            ///  IO port G clock enable
+            GPIOGEN: u1,
+            ///  IO port H clock enable
+            GPIOHEN: u1,
+            ///  IO port I clock enable
+            GPIOIEN: u1,
+            reserved12: u3,
+            ///  CRC clock enable
+            CRCEN: u1,
+            reserved18: u5,
+            ///  Backup SRAM interface clock enable
+            BKPSRAMEN: u1,
+            reserved21: u2,
+            ///  DMA1 clock enable
+            DMA1EN: u1,
+            ///  DMA2 clock enable
+            DMA2EN: u1,
+            reserved25: u2,
+            ///  Ethernet MAC clock enable
+            ETHMACEN: u1,
+            ///  Ethernet Transmission clock enable
+            ETHMACTXEN: u1,
+            ///  Ethernet Reception clock enable
+            ETHMACRXEN: u1,
+            ///  Ethernet PTP clock enable
+            ETHMACPTPEN: u1,
+            ///  USB OTG HS clock enable
+            OTGHSEN: u1,
+            ///  USB OTG HSULPI clock enable
+            OTGHSULPIEN: u1,
+            padding: u1,
+        }),
+        ///  AHB2 peripheral clock enable register
+        AHB2ENR: mmio.Mmio(packed struct(u32) {
+            ///  Camera interface enable
+            DCMIEN: u1,
+            reserved6: u5,
+            ///  Random number generator clock enable
+            RNGEN: u1,
+            ///  USB OTG FS clock enable
+            OTGFSEN: u1,
+            padding: u24,
+        }),
+        ///  AHB3 peripheral clock enable register
+        AHB3ENR: mmio.Mmio(packed struct(u32) {
+            ///  Flexible static memory controller module clock enable
+            FSMCEN: u1,
+            padding: u31,
+        }),
+        reserved64: [4]u8,
+        ///  APB1 peripheral clock enable register
+        APB1ENR: mmio.Mmio(packed struct(u32) {
+            ///  TIM2 clock enable
+            TIM2EN: u1,
+            ///  TIM3 clock enable
+            TIM3EN: u1,
+            ///  TIM4 clock enable
+            TIM4EN: u1,
+            ///  TIM5 clock enable
+            TIM5EN: u1,
+            ///  TIM6 clock enable
+            TIM6EN: u1,
+            ///  TIM7 clock enable
+            TIM7EN: u1,
+            ///  TIM12 clock enable
+            TIM12EN: u1,
+            ///  TIM13 clock enable
+            TIM13EN: u1,
+            ///  TIM14 clock enable
+            TIM14EN: u1,
+            reserved11: u2,
+            ///  Window watchdog clock enable
+            WWDGEN: u1,
+            reserved14: u2,
+            ///  SPI2 clock enable
+            SPI2EN: u1,
+            ///  SPI3 clock enable
+            SPI3EN: u1,
+            reserved17: u1,
+            ///  USART 2 clock enable
+            USART2EN: u1,
+            ///  USART3 clock enable
+            USART3EN: u1,
+            ///  UART4 clock enable
+            UART4EN: u1,
+            ///  UART5 clock enable
+            UART5EN: u1,
+            ///  I2C1 clock enable
+            I2C1EN: u1,
+            ///  I2C2 clock enable
+            I2C2EN: u1,
+            ///  I2C3 clock enable
+            I2C3EN: u1,
+            reserved25: u1,
+            ///  CAN 1 clock enable
+            CAN1EN: u1,
+            ///  CAN 2 clock enable
+            CAN2EN: u1,
+            reserved28: u1,
+            ///  Power interface clock enable
+            PWREN: u1,
+            ///  DAC interface clock enable
+            DACEN: u1,
+            padding: u2,
+        }),
+        ///  APB2 peripheral clock enable register
+        APB2ENR: mmio.Mmio(packed struct(u32) {
+            ///  TIM1 clock enable
+            TIM1EN: u1,
+            ///  TIM8 clock enable
+            TIM8EN: u1,
+            reserved4: u2,
+            ///  USART1 clock enable
+            USART1EN: u1,
+            ///  USART6 clock enable
+            USART6EN: u1,
+            reserved8: u2,
+            ///  ADC1 clock enable
+            ADC1EN: u1,
+            ///  ADC2 clock enable
+            ADC2EN: u1,
+            ///  ADC3 clock enable
+            ADC3EN: u1,
+            ///  SDIO clock enable
+            SDIOEN: u1,
+            ///  SPI1 clock enable
+            SPI1EN: u1,
+            reserved14: u1,
+            ///  System configuration controller clock enable
+            SYSCFGEN: u1,
+            reserved16: u1,
+            ///  TIM9 clock enable
+            TIM9EN: u1,
+            ///  TIM10 clock enable
+            TIM10EN: u1,
+            ///  TIM11 clock enable
+            TIM11EN: u1,
+            padding: u13,
+        }),
+        reserved80: [8]u8,
+        ///  AHB1 peripheral clock enable in low power mode register
+        AHB1LPENR: mmio.Mmio(packed struct(u32) {
+            ///  IO port A clock enable during sleep mode
+            GPIOALPEN: u1,
+            ///  IO port B clock enable during Sleep mode
+            GPIOBLPEN: u1,
+            ///  IO port C clock enable during Sleep mode
+            GPIOCLPEN: u1,
+            ///  IO port D clock enable during Sleep mode
+            GPIODLPEN: u1,
+            ///  IO port E clock enable during Sleep mode
+            GPIOELPEN: u1,
+            ///  IO port F clock enable during Sleep mode
+            GPIOFLPEN: u1,
+            ///  IO port G clock enable during Sleep mode
+            GPIOGLPEN: u1,
+            ///  IO port H clock enable during Sleep mode
+            GPIOHLPEN: u1,
+            ///  IO port I clock enable during Sleep mode
+            GPIOILPEN: u1,
+            reserved12: u3,
+            ///  CRC clock enable during Sleep mode
+            CRCLPEN: u1,
+            reserved15: u2,
+            ///  Flash interface clock enable during Sleep mode
+            FLITFLPEN: u1,
+            ///  SRAM 1interface clock enable during Sleep mode
+            SRAM1LPEN: u1,
+            ///  SRAM 2 interface clock enable during Sleep mode
+            SRAM2LPEN: u1,
+            ///  Backup SRAM interface clock enable during Sleep mode
+            BKPSRAMLPEN: u1,
+            reserved21: u2,
+            ///  DMA1 clock enable during Sleep mode
+            DMA1LPEN: u1,
+            ///  DMA2 clock enable during Sleep mode
+            DMA2LPEN: u1,
+            reserved25: u2,
+            ///  Ethernet MAC clock enable during Sleep mode
+            ETHMACLPEN: u1,
+            ///  Ethernet transmission clock enable during Sleep mode
+            ETHMACTXLPEN: u1,
+            ///  Ethernet reception clock enable during Sleep mode
+            ETHMACRXLPEN: u1,
+            ///  Ethernet PTP clock enable during Sleep mode
+            ETHMACPTPLPEN: u1,
+            ///  USB OTG HS clock enable during Sleep mode
+            OTGHSLPEN: u1,
+            ///  USB OTG HS ULPI clock enable during Sleep mode
+            OTGHSULPILPEN: u1,
+            padding: u1,
+        }),
+        ///  AHB2 peripheral clock enable in low power mode register
+        AHB2LPENR: mmio.Mmio(packed struct(u32) {
+            ///  Camera interface enable during Sleep mode
+            DCMILPEN: u1,
+            reserved6: u5,
+            ///  Random number generator clock enable during Sleep mode
+            RNGLPEN: u1,
+            ///  USB OTG FS clock enable during Sleep mode
+            OTGFSLPEN: u1,
+            padding: u24,
+        }),
+        ///  AHB3 peripheral clock enable in low power mode register
+        AHB3LPENR: mmio.Mmio(packed struct(u32) {
+            ///  Flexible static memory controller module clock enable during Sleep mode
+            FSMCLPEN: u1,
+            padding: u31,
+        }),
+        reserved96: [4]u8,
+        ///  APB1 peripheral clock enable in low power mode register
+        APB1LPENR: mmio.Mmio(packed struct(u32) {
+            ///  TIM2 clock enable during Sleep mode
+            TIM2LPEN: u1,
+            ///  TIM3 clock enable during Sleep mode
+            TIM3LPEN: u1,
+            ///  TIM4 clock enable during Sleep mode
+            TIM4LPEN: u1,
+            ///  TIM5 clock enable during Sleep mode
+            TIM5LPEN: u1,
+            ///  TIM6 clock enable during Sleep mode
+            TIM6LPEN: u1,
+            ///  TIM7 clock enable during Sleep mode
+            TIM7LPEN: u1,
+            ///  TIM12 clock enable during Sleep mode
+            TIM12LPEN: u1,
+            ///  TIM13 clock enable during Sleep mode
+            TIM13LPEN: u1,
+            ///  TIM14 clock enable during Sleep mode
+            TIM14LPEN: u1,
+            reserved11: u2,
+            ///  Window watchdog clock enable during Sleep mode
+            WWDGLPEN: u1,
+            reserved14: u2,
+            ///  SPI2 clock enable during Sleep mode
+            SPI2LPEN: u1,
+            ///  SPI3 clock enable during Sleep mode
+            SPI3LPEN: u1,
+            reserved17: u1,
+            ///  USART2 clock enable during Sleep mode
+            USART2LPEN: u1,
+            ///  USART3 clock enable during Sleep mode
+            USART3LPEN: u1,
+            ///  UART4 clock enable during Sleep mode
+            UART4LPEN: u1,
+            ///  UART5 clock enable during Sleep mode
+            UART5LPEN: u1,
+            ///  I2C1 clock enable during Sleep mode
+            I2C1LPEN: u1,
+            ///  I2C2 clock enable during Sleep mode
+            I2C2LPEN: u1,
+            ///  I2C3 clock enable during Sleep mode
+            I2C3LPEN: u1,
+            reserved25: u1,
+            ///  CAN 1 clock enable during Sleep mode
+            CAN1LPEN: u1,
+            ///  CAN 2 clock enable during Sleep mode
+            CAN2LPEN: u1,
+            reserved28: u1,
+            ///  Power interface clock enable during Sleep mode
+            PWRLPEN: u1,
+            ///  DAC interface clock enable during Sleep mode
+            DACLPEN: u1,
+            padding: u2,
+        }),
+        ///  APB2 peripheral clock enabled in low power mode register
+        APB2LPENR: mmio.Mmio(packed struct(u32) {
+            ///  TIM1 clock enable during Sleep mode
+            TIM1LPEN: u1,
+            ///  TIM8 clock enable during Sleep mode
+            TIM8LPEN: u1,
+            reserved4: u2,
+            ///  USART1 clock enable during Sleep mode
+            USART1LPEN: u1,
+            ///  USART6 clock enable during Sleep mode
+            USART6LPEN: u1,
+            reserved8: u2,
+            ///  ADC1 clock enable during Sleep mode
+            ADC1LPEN: u1,
+            ///  ADC2 clock enable during Sleep mode
+            ADC2LPEN: u1,
+            ///  ADC 3 clock enable during Sleep mode
+            ADC3LPEN: u1,
+            ///  SDIO clock enable during Sleep mode
+            SDIOLPEN: u1,
+            ///  SPI 1 clock enable during Sleep mode
+            SPI1LPEN: u1,
+            reserved14: u1,
+            ///  System configuration controller clock enable during Sleep mode
+            SYSCFGLPEN: u1,
+            reserved16: u1,
+            ///  TIM9 clock enable during sleep mode
+            TIM9LPEN: u1,
+            ///  TIM10 clock enable during Sleep mode
+            TIM10LPEN: u1,
+            ///  TIM11 clock enable during Sleep mode
+            TIM11LPEN: u1,
+            padding: u13,
+        }),
+        reserved112: [8]u8,
+        ///  Backup domain control register
+        BDCR: mmio.Mmio(packed struct(u32) {
+            ///  External low-speed oscillator enable
+            LSEON: u1,
+            ///  External low-speed oscillator ready
+            LSERDY: u1,
+            ///  External low-speed oscillator bypass
+            LSEBYP: u1,
+            reserved8: u5,
+            ///  RTC clock source selection
+            RTCSEL0: u1,
+            ///  RTC clock source selection
+            RTCSEL1: u1,
+            reserved15: u5,
+            ///  RTC clock enable
+            RTCEN: u1,
+            ///  Backup domain software reset
+            BDRST: u1,
+            padding: u15,
+        }),
+        ///  clock control & status register
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  Internal low-speed oscillator enable
+            LSION: u1,
+            ///  Internal low-speed oscillator ready
+            LSIRDY: u1,
+            reserved24: u22,
+            ///  Remove reset flag
+            RMVF: u1,
+            ///  BOR reset flag
+            BORRSTF: u1,
+            ///  PIN reset flag
+            PADRSTF: u1,
+            ///  POR/PDR reset flag
+            PORRSTF: u1,
+            ///  Software reset flag
+            SFTRSTF: u1,
+            ///  Independent watchdog reset flag
+            WDGRSTF: u1,
+            ///  Window watchdog reset flag
+            WWDGRSTF: u1,
+            ///  Low-power reset flag
+            LPWRRSTF: u1,
+        }),
+        reserved128: [8]u8,
+        ///  spread spectrum clock generation register
+        SSCGR: mmio.Mmio(packed struct(u32) {
+            ///  Modulation period
+            MODPER: u13,
+            ///  Incrementation step
+            INCSTEP: u15,
+            reserved30: u2,
+            ///  Spread Select
+            SPREADSEL: u1,
+            ///  Spread spectrum modulation enable
+            SSCGEN: u1,
+        }),
+        ///  PLLI2S configuration register
+        PLLI2SCFGR: mmio.Mmio(packed struct(u32) {
+            reserved6: u6,
+            ///  PLLI2S multiplication factor for VCO
+            PLLI2SNx: u9,
+            reserved28: u13,
+            ///  PLLI2S division factor for I2S clocks
+            PLLI2SRx: u3,
+            padding: u1,
+        }),
+    };
+
+    ///  General-purpose I/Os
+    pub const GPIOI = extern struct {
+        ///  GPIO port mode register
+        MODER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            MODER0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER15: u2,
+        }),
+        ///  GPIO port output type register
+        OTYPER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OT0: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT1: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT2: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT3: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT4: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT5: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT6: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT7: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT8: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT9: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT10: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT11: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT12: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT13: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT14: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output speed register
+        OSPEEDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR15: u2,
+        }),
+        ///  GPIO port pull-up/pull-down register
+        PUPDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR15: u2,
+        }),
+        ///  GPIO port input data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Port input data (y = 0..15)
+            IDR0: u1,
+            ///  Port input data (y = 0..15)
+            IDR1: u1,
+            ///  Port input data (y = 0..15)
+            IDR2: u1,
+            ///  Port input data (y = 0..15)
+            IDR3: u1,
+            ///  Port input data (y = 0..15)
+            IDR4: u1,
+            ///  Port input data (y = 0..15)
+            IDR5: u1,
+            ///  Port input data (y = 0..15)
+            IDR6: u1,
+            ///  Port input data (y = 0..15)
+            IDR7: u1,
+            ///  Port input data (y = 0..15)
+            IDR8: u1,
+            ///  Port input data (y = 0..15)
+            IDR9: u1,
+            ///  Port input data (y = 0..15)
+            IDR10: u1,
+            ///  Port input data (y = 0..15)
+            IDR11: u1,
+            ///  Port input data (y = 0..15)
+            IDR12: u1,
+            ///  Port input data (y = 0..15)
+            IDR13: u1,
+            ///  Port input data (y = 0..15)
+            IDR14: u1,
+            ///  Port input data (y = 0..15)
+            IDR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output data register
+        ODR: mmio.Mmio(packed struct(u32) {
+            ///  Port output data (y = 0..15)
+            ODR0: u1,
+            ///  Port output data (y = 0..15)
+            ODR1: u1,
+            ///  Port output data (y = 0..15)
+            ODR2: u1,
+            ///  Port output data (y = 0..15)
+            ODR3: u1,
+            ///  Port output data (y = 0..15)
+            ODR4: u1,
+            ///  Port output data (y = 0..15)
+            ODR5: u1,
+            ///  Port output data (y = 0..15)
+            ODR6: u1,
+            ///  Port output data (y = 0..15)
+            ODR7: u1,
+            ///  Port output data (y = 0..15)
+            ODR8: u1,
+            ///  Port output data (y = 0..15)
+            ODR9: u1,
+            ///  Port output data (y = 0..15)
+            ODR10: u1,
+            ///  Port output data (y = 0..15)
+            ODR11: u1,
+            ///  Port output data (y = 0..15)
+            ODR12: u1,
+            ///  Port output data (y = 0..15)
+            ODR13: u1,
+            ///  Port output data (y = 0..15)
+            ODR14: u1,
+            ///  Port output data (y = 0..15)
+            ODR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port bit set/reset register
+        BSRR: mmio.Mmio(packed struct(u32) {
+            ///  Port x set bit y (y= 0..15)
+            BS0: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS1: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS2: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS3: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS4: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS5: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS6: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS7: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS8: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS9: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS10: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS11: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS12: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS13: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS14: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS15: u1,
+            ///  Port x set bit y (y= 0..15)
+            BR0: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR1: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR2: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR3: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR4: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR5: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR6: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR7: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR8: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR9: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR10: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR11: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR12: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR13: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR14: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR15: u1,
+        }),
+        ///  GPIO port configuration lock register
+        LCKR: mmio.Mmio(packed struct(u32) {
+            ///  Port x lock bit y (y= 0..15)
+            LCK0: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK1: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK2: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK3: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK4: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK5: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK6: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK7: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK8: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK9: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK10: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK11: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK12: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK13: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK14: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK15: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCKK: u1,
+            padding: u15,
+        }),
+        ///  GPIO alternate function low register
+        AFRL: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL0: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL1: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL2: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL3: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL4: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL5: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL6: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL7: u4,
+        }),
+        ///  GPIO alternate function high register
+        AFRH: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH8: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH9: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH10: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH11: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH12: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH13: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH14: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH15: u4,
+        }),
+    };
+
+    ///  Floating point unit CPACR
+    pub const FPU_CPACR = extern struct {
+        ///  Coprocessor access control register
+        CPACR: mmio.Mmio(packed struct(u32) {
+            reserved20: u20,
+            ///  CP
+            CP: u4,
+            padding: u8,
+        }),
+    };
+
+    ///  Nested vectored interrupt controller
+    pub const NVIC_STIR = extern struct {
+        ///  Software trigger interrupt register
+        STIR: mmio.Mmio(packed struct(u32) {
+            ///  Software generated interrupt ID
+            INTID: u9,
+            padding: u23,
+        }),
+    };
+
+    ///  System control block
+    pub const SCB = extern struct {
+        ///  CPUID base register
+        CPUID: mmio.Mmio(packed struct(u32) {
+            ///  Revision number
+            Revision: u4,
+            ///  Part number of the processor
+            PartNo: u12,
+            ///  Reads as 0xF
+            Constant: u4,
+            ///  Variant number
+            Variant: u4,
+            ///  Implementer code
+            Implementer: u8,
+        }),
+        ///  Interrupt control and state register
+        ICSR: mmio.Mmio(packed struct(u32) {
+            ///  Active vector
+            VECTACTIVE: u9,
+            reserved11: u2,
+            ///  Return to base level
+            RETTOBASE: u1,
+            ///  Pending vector
+            VECTPENDING: u7,
+            reserved22: u3,
+            ///  Interrupt pending flag
+            ISRPENDING: u1,
+            reserved25: u2,
+            ///  SysTick exception clear-pending bit
+            PENDSTCLR: u1,
+            ///  SysTick exception set-pending bit
+            PENDSTSET: u1,
+            ///  PendSV clear-pending bit
+            PENDSVCLR: u1,
+            ///  PendSV set-pending bit
+            PENDSVSET: u1,
+            reserved31: u2,
+            ///  NMI set-pending bit.
+            NMIPENDSET: u1,
+        }),
+        ///  Vector table offset register
+        VTOR: mmio.Mmio(packed struct(u32) {
+            reserved9: u9,
+            ///  Vector table base offset field
+            TBLOFF: u21,
+            padding: u2,
+        }),
+        ///  Application interrupt and reset control register
+        AIRCR: mmio.Mmio(packed struct(u32) {
+            ///  VECTRESET
+            VECTRESET: u1,
+            ///  VECTCLRACTIVE
+            VECTCLRACTIVE: u1,
+            ///  SYSRESETREQ
+            SYSRESETREQ: u1,
+            reserved8: u5,
+            ///  PRIGROUP
+            PRIGROUP: u3,
+            reserved15: u4,
+            ///  ENDIANESS
+            ENDIANESS: u1,
+            ///  Register key
+            VECTKEYSTAT: u16,
+        }),
+        ///  System control register
+        SCR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  SLEEPONEXIT
+            SLEEPONEXIT: u1,
+            ///  SLEEPDEEP
+            SLEEPDEEP: u1,
+            reserved4: u1,
+            ///  Send Event on Pending bit
+            SEVEONPEND: u1,
+            padding: u27,
+        }),
+        ///  Configuration and control register
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Configures how the processor enters Thread mode
+            NONBASETHRDENA: u1,
+            ///  USERSETMPEND
+            USERSETMPEND: u1,
+            reserved3: u1,
+            ///  UNALIGN_ TRP
+            UNALIGN__TRP: u1,
+            ///  DIV_0_TRP
+            DIV_0_TRP: u1,
+            reserved8: u3,
+            ///  BFHFNMIGN
+            BFHFNMIGN: u1,
+            ///  STKALIGN
+            STKALIGN: u1,
+            padding: u22,
+        }),
+        ///  System handler priority registers
+        SHPR1: mmio.Mmio(packed struct(u32) {
+            ///  Priority of system handler 4
+            PRI_4: u8,
+            ///  Priority of system handler 5
+            PRI_5: u8,
+            ///  Priority of system handler 6
+            PRI_6: u8,
+            padding: u8,
+        }),
+        ///  System handler priority registers
+        SHPR2: mmio.Mmio(packed struct(u32) {
+            reserved24: u24,
+            ///  Priority of system handler 11
+            PRI_11: u8,
+        }),
+        ///  System handler priority registers
+        SHPR3: mmio.Mmio(packed struct(u32) {
+            reserved16: u16,
+            ///  Priority of system handler 14
+            PRI_14: u8,
+            ///  Priority of system handler 15
+            PRI_15: u8,
+        }),
+        ///  System handler control and state register
+        SHCRS: mmio.Mmio(packed struct(u32) {
+            ///  Memory management fault exception active bit
+            MEMFAULTACT: u1,
+            ///  Bus fault exception active bit
+            BUSFAULTACT: u1,
+            reserved3: u1,
+            ///  Usage fault exception active bit
+            USGFAULTACT: u1,
+            reserved7: u3,
+            ///  SVC call active bit
+            SVCALLACT: u1,
+            ///  Debug monitor active bit
+            MONITORACT: u1,
+            reserved10: u1,
+            ///  PendSV exception active bit
+            PENDSVACT: u1,
+            ///  SysTick exception active bit
+            SYSTICKACT: u1,
+            ///  Usage fault exception pending bit
+            USGFAULTPENDED: u1,
+            ///  Memory management fault exception pending bit
+            MEMFAULTPENDED: u1,
+            ///  Bus fault exception pending bit
+            BUSFAULTPENDED: u1,
+            ///  SVC call pending bit
+            SVCALLPENDED: u1,
+            ///  Memory management fault enable bit
+            MEMFAULTENA: u1,
+            ///  Bus fault enable bit
+            BUSFAULTENA: u1,
+            ///  Usage fault enable bit
+            USGFAULTENA: u1,
+            padding: u13,
+        }),
+        ///  Configurable fault status register
+        CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Instruction access violation flag
+            IACCVIOL: u1,
+            reserved3: u1,
+            ///  Memory manager fault on unstacking for a return from exception
+            MUNSTKERR: u1,
+            ///  Memory manager fault on stacking for exception entry.
+            MSTKERR: u1,
+            ///  MLSPERR
+            MLSPERR: u1,
+            reserved7: u1,
+            ///  Memory Management Fault Address Register (MMAR) valid flag
+            MMARVALID: u1,
+            ///  Instruction bus error
+            IBUSERR: u1,
+            ///  Precise data bus error
+            PRECISERR: u1,
+            ///  Imprecise data bus error
+            IMPRECISERR: u1,
+            ///  Bus fault on unstacking for a return from exception
+            UNSTKERR: u1,
+            ///  Bus fault on stacking for exception entry
+            STKERR: u1,
+            ///  Bus fault on floating-point lazy state preservation
+            LSPERR: u1,
+            reserved15: u1,
+            ///  Bus Fault Address Register (BFAR) valid flag
+            BFARVALID: u1,
+            ///  Undefined instruction usage fault
+            UNDEFINSTR: u1,
+            ///  Invalid state usage fault
+            INVSTATE: u1,
+            ///  Invalid PC load usage fault
+            INVPC: u1,
+            ///  No coprocessor usage fault.
+            NOCP: u1,
+            reserved24: u4,
+            ///  Unaligned access usage fault
+            UNALIGNED: u1,
+            ///  Divide by zero usage fault
+            DIVBYZERO: u1,
+            padding: u6,
+        }),
+        ///  Hard fault status register
+        HFSR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Vector table hard fault
+            VECTTBL: u1,
+            reserved30: u28,
+            ///  Forced hard fault
+            FORCED: u1,
+            ///  Reserved for Debug use
+            DEBUG_VT: u1,
+        }),
+        reserved52: [4]u8,
+        ///  Memory management fault address register
+        MMFAR: mmio.Mmio(packed struct(u32) {
+            ///  Memory management fault address
+            MMFAR: u32,
+        }),
+        ///  Bus fault address register
+        BFAR: mmio.Mmio(packed struct(u32) {
+            ///  Bus fault address
+            BFAR: u32,
+        }),
+        ///  Auxiliary fault status register
+        AFSR: mmio.Mmio(packed struct(u32) {
+            ///  Implementation defined
+            IMPDEF: u32,
+        }),
+    };
+
+    ///  SysTick timer
+    pub const STK = extern struct {
+        ///  SysTick control and status register
+        CTRL: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            ENABLE: u1,
+            ///  SysTick exception request enable
+            TICKINT: u1,
+            ///  Clock source selection
+            CLKSOURCE: u1,
+            reserved16: u13,
+            ///  COUNTFLAG
+            COUNTFLAG: u1,
+            padding: u15,
+        }),
+        ///  SysTick reload value register
+        LOAD: mmio.Mmio(packed struct(u32) {
+            ///  RELOAD value
+            RELOAD: u24,
+            padding: u8,
+        }),
+        ///  SysTick current value register
+        VAL: mmio.Mmio(packed struct(u32) {
+            ///  Current counter value
+            CURRENT: u24,
+            padding: u8,
+        }),
+        ///  SysTick calibration value register
+        CALIB: mmio.Mmio(packed struct(u32) {
+            ///  Calibration value
+            TENMS: u24,
+            reserved30: u6,
+            ///  SKEW flag: Indicates whether the TENMS value is exact
+            SKEW: u1,
+            ///  NOREF flag. Reads as zero
+            NOREF: u1,
+        }),
+    };
+
+    ///  Memory protection unit
+    pub const MPU = extern struct {
+        ///  MPU type register
+        MPU_TYPER: mmio.Mmio(packed struct(u32) {
+            ///  Separate flag
+            SEPARATE: u1,
+            reserved8: u7,
+            ///  Number of MPU data regions
+            DREGION: u8,
+            ///  Number of MPU instruction regions
+            IREGION: u8,
+            padding: u8,
+        }),
+        ///  MPU control register
+        MPU_CTRL: mmio.Mmio(packed struct(u32) {
+            ///  Enables the MPU
+            ENABLE: u1,
+            ///  Enables the operation of MPU during hard fault
+            HFNMIENA: u1,
+            ///  Enable priviliged software access to default memory map
+            PRIVDEFENA: u1,
+            padding: u29,
+        }),
+        ///  MPU region number register
+        MPU_RNR: mmio.Mmio(packed struct(u32) {
+            ///  MPU region
+            REGION: u8,
+            padding: u24,
+        }),
+        ///  MPU region base address register
+        MPU_RBAR: mmio.Mmio(packed struct(u32) {
+            ///  MPU region field
+            REGION: u4,
+            ///  MPU region number valid
+            VALID: u1,
+            ///  Region base address field
+            ADDR: u27,
+        }),
+        ///  MPU region attribute and size register
+        MPU_RASR: mmio.Mmio(packed struct(u32) {
+            ///  Region enable bit.
+            ENABLE: u1,
+            ///  Size of the MPU protection region
+            SIZE: u5,
+            reserved8: u2,
+            ///  Subregion disable bits
+            SRD: u8,
+            ///  memory attribute
+            B: u1,
+            ///  memory attribute
+            C: u1,
+            ///  Shareable memory attribute
+            S: u1,
+            ///  memory attribute
+            TEX: u3,
+            reserved24: u2,
+            ///  Access permission
+            AP: u3,
+            reserved28: u1,
+            ///  Instruction access disable bit
+            XN: u1,
+            padding: u3,
+        }),
+    };
+
+    ///  Floting point unit
+    pub const FPU = extern struct {
+        ///  Floating-point context control register
+        FPCCR: mmio.Mmio(packed struct(u32) {
+            ///  LSPACT
+            LSPACT: u1,
+            ///  USER
+            USER: u1,
+            reserved3: u1,
+            ///  THREAD
+            THREAD: u1,
+            ///  HFRDY
+            HFRDY: u1,
+            ///  MMRDY
+            MMRDY: u1,
+            ///  BFRDY
+            BFRDY: u1,
+            reserved8: u1,
+            ///  MONRDY
+            MONRDY: u1,
+            reserved30: u21,
+            ///  LSPEN
+            LSPEN: u1,
+            ///  ASPEN
+            ASPEN: u1,
+        }),
+        ///  Floating-point context address register
+        FPCAR: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Location of unpopulated floating-point
+            ADDRESS: u29,
+        }),
+        ///  Floating-point status control register
+        FPSCR: mmio.Mmio(packed struct(u32) {
+            ///  Invalid operation cumulative exception bit
+            IOC: u1,
+            ///  Division by zero cumulative exception bit.
+            DZC: u1,
+            ///  Overflow cumulative exception bit
+            OFC: u1,
+            ///  Underflow cumulative exception bit
+            UFC: u1,
+            ///  Inexact cumulative exception bit
+            IXC: u1,
+            reserved7: u2,
+            ///  Input denormal cumulative exception bit.
+            IDC: u1,
+            reserved22: u14,
+            ///  Rounding Mode control field
+            RMode: u2,
+            ///  Flush-to-zero mode control bit:
+            FZ: u1,
+            ///  Default NaN mode control bit
+            DN: u1,
+            ///  Alternative half-precision control bit
+            AHP: u1,
+            reserved28: u1,
+            ///  Overflow condition code flag
+            V: u1,
+            ///  Carry condition code flag
+            C: u1,
+            ///  Zero condition code flag
+            Z: u1,
+            ///  Negative condition code flag
+            N: u1,
+        }),
+    };
+
+    ///  Cryptographic processor
+    pub const CRYP = extern struct {
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Algorithm direction
+            ALGODIR: u1,
+            ///  Algorithm mode
+            ALGOMODE0: u3,
+            ///  Data type selection
+            DATATYPE: u2,
+            ///  Key size selection (AES mode only)
+            KEYSIZE: u2,
+            reserved14: u4,
+            ///  FIFO flush
+            FFLUSH: u1,
+            ///  Cryptographic processor enable
+            CRYPEN: u1,
+            ///  GCM_CCMPH
+            GCM_CCMPH: u2,
+            reserved19: u1,
+            ///  ALGOMODE
+            ALGOMODE3: u1,
+            padding: u12,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Input FIFO empty
+            IFEM: u1,
+            ///  Input FIFO not full
+            IFNF: u1,
+            ///  Output FIFO not empty
+            OFNE: u1,
+            ///  Output FIFO full
+            OFFU: u1,
+            ///  Busy bit
+            BUSY: u1,
+            padding: u27,
+        }),
+        ///  data input register
+        DIN: mmio.Mmio(packed struct(u32) {
+            ///  Data input
+            DATAIN: u32,
+        }),
+        ///  data output register
+        DOUT: mmio.Mmio(packed struct(u32) {
+            ///  Data output
+            DATAOUT: u32,
+        }),
+        ///  DMA control register
+        DMACR: mmio.Mmio(packed struct(u32) {
+            ///  DMA input enable
+            DIEN: u1,
+            ///  DMA output enable
+            DOEN: u1,
+            padding: u30,
+        }),
+        ///  interrupt mask set/clear register
+        IMSCR: mmio.Mmio(packed struct(u32) {
+            ///  Input FIFO service interrupt mask
+            INIM: u1,
+            ///  Output FIFO service interrupt mask
+            OUTIM: u1,
+            padding: u30,
+        }),
+        ///  raw interrupt status register
+        RISR: mmio.Mmio(packed struct(u32) {
+            ///  Input FIFO service raw interrupt status
+            INRIS: u1,
+            ///  Output FIFO service raw interrupt status
+            OUTRIS: u1,
+            padding: u30,
+        }),
+        ///  masked interrupt status register
+        MISR: mmio.Mmio(packed struct(u32) {
+            ///  Input FIFO service masked interrupt status
+            INMIS: u1,
+            ///  Output FIFO service masked interrupt status
+            OUTMIS: u1,
+            padding: u30,
+        }),
+        ///  key registers
+        K0LR: mmio.Mmio(packed struct(u32) {
+            ///  b224
+            b224: u1,
+            ///  b225
+            b225: u1,
+            ///  b226
+            b226: u1,
+            ///  b227
+            b227: u1,
+            ///  b228
+            b228: u1,
+            ///  b229
+            b229: u1,
+            ///  b230
+            b230: u1,
+            ///  b231
+            b231: u1,
+            ///  b232
+            b232: u1,
+            ///  b233
+            b233: u1,
+            ///  b234
+            b234: u1,
+            ///  b235
+            b235: u1,
+            ///  b236
+            b236: u1,
+            ///  b237
+            b237: u1,
+            ///  b238
+            b238: u1,
+            ///  b239
+            b239: u1,
+            ///  b240
+            b240: u1,
+            ///  b241
+            b241: u1,
+            ///  b242
+            b242: u1,
+            ///  b243
+            b243: u1,
+            ///  b244
+            b244: u1,
+            ///  b245
+            b245: u1,
+            ///  b246
+            b246: u1,
+            ///  b247
+            b247: u1,
+            ///  b248
+            b248: u1,
+            ///  b249
+            b249: u1,
+            ///  b250
+            b250: u1,
+            ///  b251
+            b251: u1,
+            ///  b252
+            b252: u1,
+            ///  b253
+            b253: u1,
+            ///  b254
+            b254: u1,
+            ///  b255
+            b255: u1,
+        }),
+        ///  key registers
+        K0RR: mmio.Mmio(packed struct(u32) {
+            ///  b192
+            b192: u1,
+            ///  b193
+            b193: u1,
+            ///  b194
+            b194: u1,
+            ///  b195
+            b195: u1,
+            ///  b196
+            b196: u1,
+            ///  b197
+            b197: u1,
+            ///  b198
+            b198: u1,
+            ///  b199
+            b199: u1,
+            ///  b200
+            b200: u1,
+            ///  b201
+            b201: u1,
+            ///  b202
+            b202: u1,
+            ///  b203
+            b203: u1,
+            ///  b204
+            b204: u1,
+            ///  b205
+            b205: u1,
+            ///  b206
+            b206: u1,
+            ///  b207
+            b207: u1,
+            ///  b208
+            b208: u1,
+            ///  b209
+            b209: u1,
+            ///  b210
+            b210: u1,
+            ///  b211
+            b211: u1,
+            ///  b212
+            b212: u1,
+            ///  b213
+            b213: u1,
+            ///  b214
+            b214: u1,
+            ///  b215
+            b215: u1,
+            ///  b216
+            b216: u1,
+            ///  b217
+            b217: u1,
+            ///  b218
+            b218: u1,
+            ///  b219
+            b219: u1,
+            ///  b220
+            b220: u1,
+            ///  b221
+            b221: u1,
+            ///  b222
+            b222: u1,
+            ///  b223
+            b223: u1,
+        }),
+        ///  key registers
+        K1LR: mmio.Mmio(packed struct(u32) {
+            ///  b160
+            b160: u1,
+            ///  b161
+            b161: u1,
+            ///  b162
+            b162: u1,
+            ///  b163
+            b163: u1,
+            ///  b164
+            b164: u1,
+            ///  b165
+            b165: u1,
+            ///  b166
+            b166: u1,
+            ///  b167
+            b167: u1,
+            ///  b168
+            b168: u1,
+            ///  b169
+            b169: u1,
+            ///  b170
+            b170: u1,
+            ///  b171
+            b171: u1,
+            ///  b172
+            b172: u1,
+            ///  b173
+            b173: u1,
+            ///  b174
+            b174: u1,
+            ///  b175
+            b175: u1,
+            ///  b176
+            b176: u1,
+            ///  b177
+            b177: u1,
+            ///  b178
+            b178: u1,
+            ///  b179
+            b179: u1,
+            ///  b180
+            b180: u1,
+            ///  b181
+            b181: u1,
+            ///  b182
+            b182: u1,
+            ///  b183
+            b183: u1,
+            ///  b184
+            b184: u1,
+            ///  b185
+            b185: u1,
+            ///  b186
+            b186: u1,
+            ///  b187
+            b187: u1,
+            ///  b188
+            b188: u1,
+            ///  b189
+            b189: u1,
+            ///  b190
+            b190: u1,
+            ///  b191
+            b191: u1,
+        }),
+        ///  key registers
+        K1RR: mmio.Mmio(packed struct(u32) {
+            ///  b128
+            b128: u1,
+            ///  b129
+            b129: u1,
+            ///  b130
+            b130: u1,
+            ///  b131
+            b131: u1,
+            ///  b132
+            b132: u1,
+            ///  b133
+            b133: u1,
+            ///  b134
+            b134: u1,
+            ///  b135
+            b135: u1,
+            ///  b136
+            b136: u1,
+            ///  b137
+            b137: u1,
+            ///  b138
+            b138: u1,
+            ///  b139
+            b139: u1,
+            ///  b140
+            b140: u1,
+            ///  b141
+            b141: u1,
+            ///  b142
+            b142: u1,
+            ///  b143
+            b143: u1,
+            ///  b144
+            b144: u1,
+            ///  b145
+            b145: u1,
+            ///  b146
+            b146: u1,
+            ///  b147
+            b147: u1,
+            ///  b148
+            b148: u1,
+            ///  b149
+            b149: u1,
+            ///  b150
+            b150: u1,
+            ///  b151
+            b151: u1,
+            ///  b152
+            b152: u1,
+            ///  b153
+            b153: u1,
+            ///  b154
+            b154: u1,
+            ///  b155
+            b155: u1,
+            ///  b156
+            b156: u1,
+            ///  b157
+            b157: u1,
+            ///  b158
+            b158: u1,
+            ///  b159
+            b159: u1,
+        }),
+        ///  key registers
+        K2LR: mmio.Mmio(packed struct(u32) {
+            ///  b96
+            b96: u1,
+            ///  b97
+            b97: u1,
+            ///  b98
+            b98: u1,
+            ///  b99
+            b99: u1,
+            ///  b100
+            b100: u1,
+            ///  b101
+            b101: u1,
+            ///  b102
+            b102: u1,
+            ///  b103
+            b103: u1,
+            ///  b104
+            b104: u1,
+            ///  b105
+            b105: u1,
+            ///  b106
+            b106: u1,
+            ///  b107
+            b107: u1,
+            ///  b108
+            b108: u1,
+            ///  b109
+            b109: u1,
+            ///  b110
+            b110: u1,
+            ///  b111
+            b111: u1,
+            ///  b112
+            b112: u1,
+            ///  b113
+            b113: u1,
+            ///  b114
+            b114: u1,
+            ///  b115
+            b115: u1,
+            ///  b116
+            b116: u1,
+            ///  b117
+            b117: u1,
+            ///  b118
+            b118: u1,
+            ///  b119
+            b119: u1,
+            ///  b120
+            b120: u1,
+            ///  b121
+            b121: u1,
+            ///  b122
+            b122: u1,
+            ///  b123
+            b123: u1,
+            ///  b124
+            b124: u1,
+            ///  b125
+            b125: u1,
+            ///  b126
+            b126: u1,
+            ///  b127
+            b127: u1,
+        }),
+        ///  key registers
+        K2RR: mmio.Mmio(packed struct(u32) {
+            ///  b64
+            b64: u1,
+            ///  b65
+            b65: u1,
+            ///  b66
+            b66: u1,
+            ///  b67
+            b67: u1,
+            ///  b68
+            b68: u1,
+            ///  b69
+            b69: u1,
+            ///  b70
+            b70: u1,
+            ///  b71
+            b71: u1,
+            ///  b72
+            b72: u1,
+            ///  b73
+            b73: u1,
+            ///  b74
+            b74: u1,
+            ///  b75
+            b75: u1,
+            ///  b76
+            b76: u1,
+            ///  b77
+            b77: u1,
+            ///  b78
+            b78: u1,
+            ///  b79
+            b79: u1,
+            ///  b80
+            b80: u1,
+            ///  b81
+            b81: u1,
+            ///  b82
+            b82: u1,
+            ///  b83
+            b83: u1,
+            ///  b84
+            b84: u1,
+            ///  b85
+            b85: u1,
+            ///  b86
+            b86: u1,
+            ///  b87
+            b87: u1,
+            ///  b88
+            b88: u1,
+            ///  b89
+            b89: u1,
+            ///  b90
+            b90: u1,
+            ///  b91
+            b91: u1,
+            ///  b92
+            b92: u1,
+            ///  b93
+            b93: u1,
+            ///  b94
+            b94: u1,
+            ///  b95
+            b95: u1,
+        }),
+        ///  key registers
+        K3LR: mmio.Mmio(packed struct(u32) {
+            ///  b32
+            b32: u1,
+            ///  b33
+            b33: u1,
+            ///  b34
+            b34: u1,
+            ///  b35
+            b35: u1,
+            ///  b36
+            b36: u1,
+            ///  b37
+            b37: u1,
+            ///  b38
+            b38: u1,
+            ///  b39
+            b39: u1,
+            ///  b40
+            b40: u1,
+            ///  b41
+            b41: u1,
+            ///  b42
+            b42: u1,
+            ///  b43
+            b43: u1,
+            ///  b44
+            b44: u1,
+            ///  b45
+            b45: u1,
+            ///  b46
+            b46: u1,
+            ///  b47
+            b47: u1,
+            ///  b48
+            b48: u1,
+            ///  b49
+            b49: u1,
+            ///  b50
+            b50: u1,
+            ///  b51
+            b51: u1,
+            ///  b52
+            b52: u1,
+            ///  b53
+            b53: u1,
+            ///  b54
+            b54: u1,
+            ///  b55
+            b55: u1,
+            ///  b56
+            b56: u1,
+            ///  b57
+            b57: u1,
+            ///  b58
+            b58: u1,
+            ///  b59
+            b59: u1,
+            ///  b60
+            b60: u1,
+            ///  b61
+            b61: u1,
+            ///  b62
+            b62: u1,
+            ///  b63
+            b63: u1,
+        }),
+        ///  key registers
+        K3RR: mmio.Mmio(packed struct(u32) {
+            ///  b0
+            b0: u1,
+            ///  b1
+            b1: u1,
+            ///  b2
+            b2: u1,
+            ///  b3
+            b3: u1,
+            ///  b4
+            b4: u1,
+            ///  b5
+            b5: u1,
+            ///  b6
+            b6: u1,
+            ///  b7
+            b7: u1,
+            ///  b8
+            b8: u1,
+            ///  b9
+            b9: u1,
+            ///  b10
+            b10: u1,
+            ///  b11
+            b11: u1,
+            ///  b12
+            b12: u1,
+            ///  b13
+            b13: u1,
+            ///  b14
+            b14: u1,
+            ///  b15
+            b15: u1,
+            ///  b16
+            b16: u1,
+            ///  b17
+            b17: u1,
+            ///  b18
+            b18: u1,
+            ///  b19
+            b19: u1,
+            ///  b20
+            b20: u1,
+            ///  b21
+            b21: u1,
+            ///  b22
+            b22: u1,
+            ///  b23
+            b23: u1,
+            ///  b24
+            b24: u1,
+            ///  b25
+            b25: u1,
+            ///  b26
+            b26: u1,
+            ///  b27
+            b27: u1,
+            ///  b28
+            b28: u1,
+            ///  b29
+            b29: u1,
+            ///  b30
+            b30: u1,
+            ///  b31
+            b31: u1,
+        }),
+        ///  initialization vector registers
+        IV0LR: mmio.Mmio(packed struct(u32) {
+            ///  IV31
+            IV31: u1,
+            ///  IV30
+            IV30: u1,
+            ///  IV29
+            IV29: u1,
+            ///  IV28
+            IV28: u1,
+            ///  IV27
+            IV27: u1,
+            ///  IV26
+            IV26: u1,
+            ///  IV25
+            IV25: u1,
+            ///  IV24
+            IV24: u1,
+            ///  IV23
+            IV23: u1,
+            ///  IV22
+            IV22: u1,
+            ///  IV21
+            IV21: u1,
+            ///  IV20
+            IV20: u1,
+            ///  IV19
+            IV19: u1,
+            ///  IV18
+            IV18: u1,
+            ///  IV17
+            IV17: u1,
+            ///  IV16
+            IV16: u1,
+            ///  IV15
+            IV15: u1,
+            ///  IV14
+            IV14: u1,
+            ///  IV13
+            IV13: u1,
+            ///  IV12
+            IV12: u1,
+            ///  IV11
+            IV11: u1,
+            ///  IV10
+            IV10: u1,
+            ///  IV9
+            IV9: u1,
+            ///  IV8
+            IV8: u1,
+            ///  IV7
+            IV7: u1,
+            ///  IV6
+            IV6: u1,
+            ///  IV5
+            IV5: u1,
+            ///  IV4
+            IV4: u1,
+            ///  IV3
+            IV3: u1,
+            ///  IV2
+            IV2: u1,
+            ///  IV1
+            IV1: u1,
+            ///  IV0
+            IV0: u1,
+        }),
+        ///  initialization vector registers
+        IV0RR: mmio.Mmio(packed struct(u32) {
+            ///  IV63
+            IV63: u1,
+            ///  IV62
+            IV62: u1,
+            ///  IV61
+            IV61: u1,
+            ///  IV60
+            IV60: u1,
+            ///  IV59
+            IV59: u1,
+            ///  IV58
+            IV58: u1,
+            ///  IV57
+            IV57: u1,
+            ///  IV56
+            IV56: u1,
+            ///  IV55
+            IV55: u1,
+            ///  IV54
+            IV54: u1,
+            ///  IV53
+            IV53: u1,
+            ///  IV52
+            IV52: u1,
+            ///  IV51
+            IV51: u1,
+            ///  IV50
+            IV50: u1,
+            ///  IV49
+            IV49: u1,
+            ///  IV48
+            IV48: u1,
+            ///  IV47
+            IV47: u1,
+            ///  IV46
+            IV46: u1,
+            ///  IV45
+            IV45: u1,
+            ///  IV44
+            IV44: u1,
+            ///  IV43
+            IV43: u1,
+            ///  IV42
+            IV42: u1,
+            ///  IV41
+            IV41: u1,
+            ///  IV40
+            IV40: u1,
+            ///  IV39
+            IV39: u1,
+            ///  IV38
+            IV38: u1,
+            ///  IV37
+            IV37: u1,
+            ///  IV36
+            IV36: u1,
+            ///  IV35
+            IV35: u1,
+            ///  IV34
+            IV34: u1,
+            ///  IV33
+            IV33: u1,
+            ///  IV32
+            IV32: u1,
+        }),
+        ///  initialization vector registers
+        IV1LR: mmio.Mmio(packed struct(u32) {
+            ///  IV95
+            IV95: u1,
+            ///  IV94
+            IV94: u1,
+            ///  IV93
+            IV93: u1,
+            ///  IV92
+            IV92: u1,
+            ///  IV91
+            IV91: u1,
+            ///  IV90
+            IV90: u1,
+            ///  IV89
+            IV89: u1,
+            ///  IV88
+            IV88: u1,
+            ///  IV87
+            IV87: u1,
+            ///  IV86
+            IV86: u1,
+            ///  IV85
+            IV85: u1,
+            ///  IV84
+            IV84: u1,
+            ///  IV83
+            IV83: u1,
+            ///  IV82
+            IV82: u1,
+            ///  IV81
+            IV81: u1,
+            ///  IV80
+            IV80: u1,
+            ///  IV79
+            IV79: u1,
+            ///  IV78
+            IV78: u1,
+            ///  IV77
+            IV77: u1,
+            ///  IV76
+            IV76: u1,
+            ///  IV75
+            IV75: u1,
+            ///  IV74
+            IV74: u1,
+            ///  IV73
+            IV73: u1,
+            ///  IV72
+            IV72: u1,
+            ///  IV71
+            IV71: u1,
+            ///  IV70
+            IV70: u1,
+            ///  IV69
+            IV69: u1,
+            ///  IV68
+            IV68: u1,
+            ///  IV67
+            IV67: u1,
+            ///  IV66
+            IV66: u1,
+            ///  IV65
+            IV65: u1,
+            ///  IV64
+            IV64: u1,
+        }),
+        ///  initialization vector registers
+        IV1RR: mmio.Mmio(packed struct(u32) {
+            ///  IV127
+            IV127: u1,
+            ///  IV126
+            IV126: u1,
+            ///  IV125
+            IV125: u1,
+            ///  IV124
+            IV124: u1,
+            ///  IV123
+            IV123: u1,
+            ///  IV122
+            IV122: u1,
+            ///  IV121
+            IV121: u1,
+            ///  IV120
+            IV120: u1,
+            ///  IV119
+            IV119: u1,
+            ///  IV118
+            IV118: u1,
+            ///  IV117
+            IV117: u1,
+            ///  IV116
+            IV116: u1,
+            ///  IV115
+            IV115: u1,
+            ///  IV114
+            IV114: u1,
+            ///  IV113
+            IV113: u1,
+            ///  IV112
+            IV112: u1,
+            ///  IV111
+            IV111: u1,
+            ///  IV110
+            IV110: u1,
+            ///  IV109
+            IV109: u1,
+            ///  IV108
+            IV108: u1,
+            ///  IV107
+            IV107: u1,
+            ///  IV106
+            IV106: u1,
+            ///  IV105
+            IV105: u1,
+            ///  IV104
+            IV104: u1,
+            ///  IV103
+            IV103: u1,
+            ///  IV102
+            IV102: u1,
+            ///  IV101
+            IV101: u1,
+            ///  IV100
+            IV100: u1,
+            ///  IV99
+            IV99: u1,
+            ///  IV98
+            IV98: u1,
+            ///  IV97
+            IV97: u1,
+            ///  IV96
+            IV96: u1,
+        }),
+        ///  context swap register
+        CSGCMCCM0R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM0R
+            CSGCMCCM0R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM1R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM1R
+            CSGCMCCM1R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM2R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM2R
+            CSGCMCCM2R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM3R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM3R
+            CSGCMCCM3R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM4R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM4R
+            CSGCMCCM4R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM5R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM5R
+            CSGCMCCM5R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM6R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM6R
+            CSGCMCCM6R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM7R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM7R
+            CSGCMCCM7R: u32,
+        }),
+        ///  context swap register
+        CSGCM0R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM0R
+            CSGCM0R: u32,
+        }),
+        ///  context swap register
+        CSGCM1R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM1R
+            CSGCM1R: u32,
+        }),
+        ///  context swap register
+        CSGCM2R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM2R
+            CSGCM2R: u32,
+        }),
+        ///  context swap register
+        CSGCM3R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM3R
+            CSGCM3R: u32,
+        }),
+        ///  context swap register
+        CSGCM4R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM4R
+            CSGCM4R: u32,
+        }),
+        ///  context swap register
+        CSGCM5R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM5R
+            CSGCM5R: u32,
+        }),
+        ///  context swap register
+        CSGCM6R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM6R
+            CSGCM6R: u32,
+        }),
+        ///  context swap register
+        CSGCM7R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM7R
+            CSGCM7R: u32,
+        }),
+    };
+
+    ///  Hash processor
+    pub const HASH = extern struct {
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Initialize message digest calculation
+            INIT: u1,
+            ///  DMA enable
+            DMAE: u1,
+            ///  Data type selection
+            DATATYPE: u2,
+            ///  Mode selection
+            MODE: u1,
+            ///  Algorithm selection
+            ALGO0: u1,
+            ///  Number of words already pushed
+            NBW: u4,
+            ///  DIN not empty
+            DINNE: u1,
+            ///  Multiple DMA Transfers
+            MDMAT: u1,
+            reserved16: u2,
+            ///  Long key selection
+            LKEY: u1,
+            reserved18: u1,
+            ///  ALGO
+            ALGO1: u1,
+            padding: u13,
+        }),
+        ///  data input register
+        DIN: mmio.Mmio(packed struct(u32) {
+            ///  Data input
+            DATAIN: u32,
+        }),
+        ///  start register
+        STR: mmio.Mmio(packed struct(u32) {
+            ///  Number of valid bits in the last word of the message
+            NBLW: u5,
+            reserved8: u3,
+            ///  Digest calculation
+            DCAL: u1,
+            padding: u23,
+        }),
+        ///  digest registers
+        HR0: mmio.Mmio(packed struct(u32) {
+            ///  H0
+            H0: u32,
+        }),
+        ///  digest registers
+        HR1: mmio.Mmio(packed struct(u32) {
+            ///  H1
+            H1: u32,
+        }),
+        ///  digest registers
+        HR2: mmio.Mmio(packed struct(u32) {
+            ///  H2
+            H2: u32,
+        }),
+        ///  digest registers
+        HR3: mmio.Mmio(packed struct(u32) {
+            ///  H3
+            H3: u32,
+        }),
+        ///  digest registers
+        HR4: mmio.Mmio(packed struct(u32) {
+            ///  H4
+            H4: u32,
+        }),
+        ///  interrupt enable register
+        IMR: mmio.Mmio(packed struct(u32) {
+            ///  Data input interrupt enable
+            DINIE: u1,
+            ///  Digest calculation completion interrupt enable
+            DCIE: u1,
+            padding: u30,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Data input interrupt status
+            DINIS: u1,
+            ///  Digest calculation completion interrupt status
+            DCIS: u1,
+            ///  DMA Status
+            DMAS: u1,
+            ///  Busy bit
+            BUSY: u1,
+            padding: u28,
+        }),
+        reserved248: [208]u8,
+        ///  context swap registers
+        CSR0: mmio.Mmio(packed struct(u32) {
+            ///  CSR0
+            CSR0: u32,
+        }),
+        ///  context swap registers
+        CSR1: mmio.Mmio(packed struct(u32) {
+            ///  CSR1
+            CSR1: u32,
+        }),
+        ///  context swap registers
+        CSR2: mmio.Mmio(packed struct(u32) {
+            ///  CSR2
+            CSR2: u32,
+        }),
+        ///  context swap registers
+        CSR3: mmio.Mmio(packed struct(u32) {
+            ///  CSR3
+            CSR3: u32,
+        }),
+        ///  context swap registers
+        CSR4: mmio.Mmio(packed struct(u32) {
+            ///  CSR4
+            CSR4: u32,
+        }),
+        ///  context swap registers
+        CSR5: mmio.Mmio(packed struct(u32) {
+            ///  CSR5
+            CSR5: u32,
+        }),
+        ///  context swap registers
+        CSR6: mmio.Mmio(packed struct(u32) {
+            ///  CSR6
+            CSR6: u32,
+        }),
+        ///  context swap registers
+        CSR7: mmio.Mmio(packed struct(u32) {
+            ///  CSR7
+            CSR7: u32,
+        }),
+        ///  context swap registers
+        CSR8: mmio.Mmio(packed struct(u32) {
+            ///  CSR8
+            CSR8: u32,
+        }),
+        ///  context swap registers
+        CSR9: mmio.Mmio(packed struct(u32) {
+            ///  CSR9
+            CSR9: u32,
+        }),
+        ///  context swap registers
+        CSR10: mmio.Mmio(packed struct(u32) {
+            ///  CSR10
+            CSR10: u32,
+        }),
+        ///  context swap registers
+        CSR11: mmio.Mmio(packed struct(u32) {
+            ///  CSR11
+            CSR11: u32,
+        }),
+        ///  context swap registers
+        CSR12: mmio.Mmio(packed struct(u32) {
+            ///  CSR12
+            CSR12: u32,
+        }),
+        ///  context swap registers
+        CSR13: mmio.Mmio(packed struct(u32) {
+            ///  CSR13
+            CSR13: u32,
+        }),
+        ///  context swap registers
+        CSR14: mmio.Mmio(packed struct(u32) {
+            ///  CSR14
+            CSR14: u32,
+        }),
+        ///  context swap registers
+        CSR15: mmio.Mmio(packed struct(u32) {
+            ///  CSR15
+            CSR15: u32,
+        }),
+        ///  context swap registers
+        CSR16: mmio.Mmio(packed struct(u32) {
+            ///  CSR16
+            CSR16: u32,
+        }),
+        ///  context swap registers
+        CSR17: mmio.Mmio(packed struct(u32) {
+            ///  CSR17
+            CSR17: u32,
+        }),
+        ///  context swap registers
+        CSR18: mmio.Mmio(packed struct(u32) {
+            ///  CSR18
+            CSR18: u32,
+        }),
+        ///  context swap registers
+        CSR19: mmio.Mmio(packed struct(u32) {
+            ///  CSR19
+            CSR19: u32,
+        }),
+        ///  context swap registers
+        CSR20: mmio.Mmio(packed struct(u32) {
+            ///  CSR20
+            CSR20: u32,
+        }),
+        ///  context swap registers
+        CSR21: mmio.Mmio(packed struct(u32) {
+            ///  CSR21
+            CSR21: u32,
+        }),
+        ///  context swap registers
+        CSR22: mmio.Mmio(packed struct(u32) {
+            ///  CSR22
+            CSR22: u32,
+        }),
+        ///  context swap registers
+        CSR23: mmio.Mmio(packed struct(u32) {
+            ///  CSR23
+            CSR23: u32,
+        }),
+        ///  context swap registers
+        CSR24: mmio.Mmio(packed struct(u32) {
+            ///  CSR24
+            CSR24: u32,
+        }),
+        ///  context swap registers
+        CSR25: mmio.Mmio(packed struct(u32) {
+            ///  CSR25
+            CSR25: u32,
+        }),
+        ///  context swap registers
+        CSR26: mmio.Mmio(packed struct(u32) {
+            ///  CSR26
+            CSR26: u32,
+        }),
+        ///  context swap registers
+        CSR27: mmio.Mmio(packed struct(u32) {
+            ///  CSR27
+            CSR27: u32,
+        }),
+        ///  context swap registers
+        CSR28: mmio.Mmio(packed struct(u32) {
+            ///  CSR28
+            CSR28: u32,
+        }),
+        ///  context swap registers
+        CSR29: mmio.Mmio(packed struct(u32) {
+            ///  CSR29
+            CSR29: u32,
+        }),
+        ///  context swap registers
+        CSR30: mmio.Mmio(packed struct(u32) {
+            ///  CSR30
+            CSR30: u32,
+        }),
+        ///  context swap registers
+        CSR31: mmio.Mmio(packed struct(u32) {
+            ///  CSR31
+            CSR31: u32,
+        }),
+        ///  context swap registers
+        CSR32: mmio.Mmio(packed struct(u32) {
+            ///  CSR32
+            CSR32: u32,
+        }),
+        ///  context swap registers
+        CSR33: mmio.Mmio(packed struct(u32) {
+            ///  CSR33
+            CSR33: u32,
+        }),
+        ///  context swap registers
+        CSR34: mmio.Mmio(packed struct(u32) {
+            ///  CSR34
+            CSR34: u32,
+        }),
+        ///  context swap registers
+        CSR35: mmio.Mmio(packed struct(u32) {
+            ///  CSR35
+            CSR35: u32,
+        }),
+        ///  context swap registers
+        CSR36: mmio.Mmio(packed struct(u32) {
+            ///  CSR36
+            CSR36: u32,
+        }),
+        ///  context swap registers
+        CSR37: mmio.Mmio(packed struct(u32) {
+            ///  CSR37
+            CSR37: u32,
+        }),
+        ///  context swap registers
+        CSR38: mmio.Mmio(packed struct(u32) {
+            ///  CSR38
+            CSR38: u32,
+        }),
+        ///  context swap registers
+        CSR39: mmio.Mmio(packed struct(u32) {
+            ///  CSR39
+            CSR39: u32,
+        }),
+        ///  context swap registers
+        CSR40: mmio.Mmio(packed struct(u32) {
+            ///  CSR40
+            CSR40: u32,
+        }),
+        ///  context swap registers
+        CSR41: mmio.Mmio(packed struct(u32) {
+            ///  CSR41
+            CSR41: u32,
+        }),
+        ///  context swap registers
+        CSR42: mmio.Mmio(packed struct(u32) {
+            ///  CSR42
+            CSR42: u32,
+        }),
+        ///  context swap registers
+        CSR43: mmio.Mmio(packed struct(u32) {
+            ///  CSR43
+            CSR43: u32,
+        }),
+        ///  context swap registers
+        CSR44: mmio.Mmio(packed struct(u32) {
+            ///  CSR44
+            CSR44: u32,
+        }),
+        ///  context swap registers
+        CSR45: mmio.Mmio(packed struct(u32) {
+            ///  CSR45
+            CSR45: u32,
+        }),
+        ///  context swap registers
+        CSR46: mmio.Mmio(packed struct(u32) {
+            ///  CSR46
+            CSR46: u32,
+        }),
+        ///  context swap registers
+        CSR47: mmio.Mmio(packed struct(u32) {
+            ///  CSR47
+            CSR47: u32,
+        }),
+        ///  context swap registers
+        CSR48: mmio.Mmio(packed struct(u32) {
+            ///  CSR48
+            CSR48: u32,
+        }),
+        ///  context swap registers
+        CSR49: mmio.Mmio(packed struct(u32) {
+            ///  CSR49
+            CSR49: u32,
+        }),
+        ///  context swap registers
+        CSR50: mmio.Mmio(packed struct(u32) {
+            ///  CSR50
+            CSR50: u32,
+        }),
+        ///  context swap registers
+        CSR51: mmio.Mmio(packed struct(u32) {
+            ///  CSR51
+            CSR51: u32,
+        }),
+        ///  context swap registers
+        CSR52: mmio.Mmio(packed struct(u32) {
+            ///  CSR52
+            CSR52: u32,
+        }),
+        ///  context swap registers
+        CSR53: mmio.Mmio(packed struct(u32) {
+            ///  CSR53
+            CSR53: u32,
+        }),
+        reserved784: [320]u8,
+        ///  HASH digest register
+        HASH_HR0: mmio.Mmio(packed struct(u32) {
+            ///  H0
+            H0: u32,
+        }),
+        ///  read-only
+        HASH_HR1: mmio.Mmio(packed struct(u32) {
+            ///  H1
+            H1: u32,
+        }),
+        ///  read-only
+        HASH_HR2: mmio.Mmio(packed struct(u32) {
+            ///  H2
+            H2: u32,
+        }),
+        ///  read-only
+        HASH_HR3: mmio.Mmio(packed struct(u32) {
+            ///  H3
+            H3: u32,
+        }),
+        ///  read-only
+        HASH_HR4: mmio.Mmio(packed struct(u32) {
+            ///  H4
+            H4: u32,
+        }),
+        ///  read-only
+        HASH_HR5: mmio.Mmio(packed struct(u32) {
+            ///  H5
+            H5: u32,
+        }),
+        ///  read-only
+        HASH_HR6: mmio.Mmio(packed struct(u32) {
+            ///  H6
+            H6: u32,
+        }),
+        ///  read-only
+        HASH_HR7: mmio.Mmio(packed struct(u32) {
+            ///  H7
+            H7: u32,
+        }),
+    };
+
+    ///  General-purpose I/Os
+    pub const GPIOB = extern struct {
+        ///  GPIO port mode register
+        MODER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            MODER0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER15: u2,
+        }),
+        ///  GPIO port output type register
+        OTYPER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OT0: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT1: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT2: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT3: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT4: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT5: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT6: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT7: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT8: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT9: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT10: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT11: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT12: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT13: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT14: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output speed register
+        OSPEEDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR15: u2,
+        }),
+        ///  GPIO port pull-up/pull-down register
+        PUPDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR15: u2,
+        }),
+        ///  GPIO port input data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Port input data (y = 0..15)
+            IDR0: u1,
+            ///  Port input data (y = 0..15)
+            IDR1: u1,
+            ///  Port input data (y = 0..15)
+            IDR2: u1,
+            ///  Port input data (y = 0..15)
+            IDR3: u1,
+            ///  Port input data (y = 0..15)
+            IDR4: u1,
+            ///  Port input data (y = 0..15)
+            IDR5: u1,
+            ///  Port input data (y = 0..15)
+            IDR6: u1,
+            ///  Port input data (y = 0..15)
+            IDR7: u1,
+            ///  Port input data (y = 0..15)
+            IDR8: u1,
+            ///  Port input data (y = 0..15)
+            IDR9: u1,
+            ///  Port input data (y = 0..15)
+            IDR10: u1,
+            ///  Port input data (y = 0..15)
+            IDR11: u1,
+            ///  Port input data (y = 0..15)
+            IDR12: u1,
+            ///  Port input data (y = 0..15)
+            IDR13: u1,
+            ///  Port input data (y = 0..15)
+            IDR14: u1,
+            ///  Port input data (y = 0..15)
+            IDR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output data register
+        ODR: mmio.Mmio(packed struct(u32) {
+            ///  Port output data (y = 0..15)
+            ODR0: u1,
+            ///  Port output data (y = 0..15)
+            ODR1: u1,
+            ///  Port output data (y = 0..15)
+            ODR2: u1,
+            ///  Port output data (y = 0..15)
+            ODR3: u1,
+            ///  Port output data (y = 0..15)
+            ODR4: u1,
+            ///  Port output data (y = 0..15)
+            ODR5: u1,
+            ///  Port output data (y = 0..15)
+            ODR6: u1,
+            ///  Port output data (y = 0..15)
+            ODR7: u1,
+            ///  Port output data (y = 0..15)
+            ODR8: u1,
+            ///  Port output data (y = 0..15)
+            ODR9: u1,
+            ///  Port output data (y = 0..15)
+            ODR10: u1,
+            ///  Port output data (y = 0..15)
+            ODR11: u1,
+            ///  Port output data (y = 0..15)
+            ODR12: u1,
+            ///  Port output data (y = 0..15)
+            ODR13: u1,
+            ///  Port output data (y = 0..15)
+            ODR14: u1,
+            ///  Port output data (y = 0..15)
+            ODR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port bit set/reset register
+        BSRR: mmio.Mmio(packed struct(u32) {
+            ///  Port x set bit y (y= 0..15)
+            BS0: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS1: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS2: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS3: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS4: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS5: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS6: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS7: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS8: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS9: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS10: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS11: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS12: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS13: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS14: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS15: u1,
+            ///  Port x set bit y (y= 0..15)
+            BR0: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR1: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR2: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR3: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR4: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR5: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR6: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR7: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR8: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR9: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR10: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR11: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR12: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR13: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR14: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR15: u1,
+        }),
+        ///  GPIO port configuration lock register
+        LCKR: mmio.Mmio(packed struct(u32) {
+            ///  Port x lock bit y (y= 0..15)
+            LCK0: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK1: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK2: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK3: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK4: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK5: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK6: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK7: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK8: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK9: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK10: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK11: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK12: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK13: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK14: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK15: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCKK: u1,
+            padding: u15,
+        }),
+        ///  GPIO alternate function low register
+        AFRL: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL0: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL1: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL2: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL3: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL4: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL5: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL6: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL7: u4,
+        }),
+        ///  GPIO alternate function high register
+        AFRH: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH8: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH9: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH10: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH11: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH12: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH13: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH14: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH15: u4,
+        }),
+    };
+
+    ///  General-purpose I/Os
+    pub const GPIOA = extern struct {
+        ///  GPIO port mode register
+        MODER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            MODER0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER15: u2,
+        }),
+        ///  GPIO port output type register
+        OTYPER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OT0: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT1: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT2: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT3: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT4: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT5: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT6: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT7: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT8: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT9: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT10: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT11: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT12: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT13: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT14: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output speed register
+        OSPEEDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR15: u2,
+        }),
+        ///  GPIO port pull-up/pull-down register
+        PUPDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR15: u2,
+        }),
+        ///  GPIO port input data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Port input data (y = 0..15)
+            IDR0: u1,
+            ///  Port input data (y = 0..15)
+            IDR1: u1,
+            ///  Port input data (y = 0..15)
+            IDR2: u1,
+            ///  Port input data (y = 0..15)
+            IDR3: u1,
+            ///  Port input data (y = 0..15)
+            IDR4: u1,
+            ///  Port input data (y = 0..15)
+            IDR5: u1,
+            ///  Port input data (y = 0..15)
+            IDR6: u1,
+            ///  Port input data (y = 0..15)
+            IDR7: u1,
+            ///  Port input data (y = 0..15)
+            IDR8: u1,
+            ///  Port input data (y = 0..15)
+            IDR9: u1,
+            ///  Port input data (y = 0..15)
+            IDR10: u1,
+            ///  Port input data (y = 0..15)
+            IDR11: u1,
+            ///  Port input data (y = 0..15)
+            IDR12: u1,
+            ///  Port input data (y = 0..15)
+            IDR13: u1,
+            ///  Port input data (y = 0..15)
+            IDR14: u1,
+            ///  Port input data (y = 0..15)
+            IDR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output data register
+        ODR: mmio.Mmio(packed struct(u32) {
+            ///  Port output data (y = 0..15)
+            ODR0: u1,
+            ///  Port output data (y = 0..15)
+            ODR1: u1,
+            ///  Port output data (y = 0..15)
+            ODR2: u1,
+            ///  Port output data (y = 0..15)
+            ODR3: u1,
+            ///  Port output data (y = 0..15)
+            ODR4: u1,
+            ///  Port output data (y = 0..15)
+            ODR5: u1,
+            ///  Port output data (y = 0..15)
+            ODR6: u1,
+            ///  Port output data (y = 0..15)
+            ODR7: u1,
+            ///  Port output data (y = 0..15)
+            ODR8: u1,
+            ///  Port output data (y = 0..15)
+            ODR9: u1,
+            ///  Port output data (y = 0..15)
+            ODR10: u1,
+            ///  Port output data (y = 0..15)
+            ODR11: u1,
+            ///  Port output data (y = 0..15)
+            ODR12: u1,
+            ///  Port output data (y = 0..15)
+            ODR13: u1,
+            ///  Port output data (y = 0..15)
+            ODR14: u1,
+            ///  Port output data (y = 0..15)
+            ODR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port bit set/reset register
+        BSRR: mmio.Mmio(packed struct(u32) {
+            ///  Port x set bit y (y= 0..15)
+            BS0: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS1: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS2: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS3: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS4: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS5: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS6: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS7: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS8: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS9: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS10: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS11: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS12: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS13: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS14: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS15: u1,
+            ///  Port x set bit y (y= 0..15)
+            BR0: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR1: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR2: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR3: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR4: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR5: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR6: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR7: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR8: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR9: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR10: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR11: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR12: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR13: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR14: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR15: u1,
+        }),
+        ///  GPIO port configuration lock register
+        LCKR: mmio.Mmio(packed struct(u32) {
+            ///  Port x lock bit y (y= 0..15)
+            LCK0: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK1: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK2: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK3: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK4: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK5: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK6: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK7: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK8: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK9: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK10: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK11: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK12: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK13: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK14: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK15: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCKK: u1,
+            padding: u15,
+        }),
+        ///  GPIO alternate function low register
+        AFRL: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL0: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL1: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL2: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL3: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL4: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL5: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL6: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL7: u4,
+        }),
+        ///  GPIO alternate function high register
+        AFRH: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH8: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH9: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH10: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH11: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH12: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH13: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH14: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH15: u4,
+        }),
+    };
+
+    ///  System configuration controller
+    pub const SYSCFG = extern struct {
+        ///  memory remap register
+        MEMRM: mmio.Mmio(packed struct(u32) {
+            ///  MEM_MODE
+            MEM_MODE: u2,
+            padding: u30,
+        }),
+        ///  peripheral mode configuration register
+        PMC: mmio.Mmio(packed struct(u32) {
+            reserved23: u23,
+            ///  Ethernet PHY interface selection
+            MII_RMII_SEL: u1,
+            padding: u8,
+        }),
+        ///  external interrupt configuration register 1
+        EXTICR1: mmio.Mmio(packed struct(u32) {
+            ///  EXTI x configuration (x = 0 to 3)
+            EXTI0: u4,
+            ///  EXTI x configuration (x = 0 to 3)
+            EXTI1: u4,
+            ///  EXTI x configuration (x = 0 to 3)
+            EXTI2: u4,
+            ///  EXTI x configuration (x = 0 to 3)
+            EXTI3: u4,
+            padding: u16,
+        }),
+        ///  external interrupt configuration register 2
+        EXTICR2: mmio.Mmio(packed struct(u32) {
+            ///  EXTI x configuration (x = 4 to 7)
+            EXTI4: u4,
+            ///  EXTI x configuration (x = 4 to 7)
+            EXTI5: u4,
+            ///  EXTI x configuration (x = 4 to 7)
+            EXTI6: u4,
+            ///  EXTI x configuration (x = 4 to 7)
+            EXTI7: u4,
+            padding: u16,
+        }),
+        ///  external interrupt configuration register 3
+        EXTICR3: mmio.Mmio(packed struct(u32) {
+            ///  EXTI x configuration (x = 8 to 11)
+            EXTI8: u4,
+            ///  EXTI x configuration (x = 8 to 11)
+            EXTI9: u4,
+            ///  EXTI10
+            EXTI10: u4,
+            ///  EXTI x configuration (x = 8 to 11)
+            EXTI11: u4,
+            padding: u16,
+        }),
+        ///  external interrupt configuration register 4
+        EXTICR4: mmio.Mmio(packed struct(u32) {
+            ///  EXTI x configuration (x = 12 to 15)
+            EXTI12: u4,
+            ///  EXTI x configuration (x = 12 to 15)
+            EXTI13: u4,
+            ///  EXTI x configuration (x = 12 to 15)
+            EXTI14: u4,
+            ///  EXTI x configuration (x = 12 to 15)
+            EXTI15: u4,
+            padding: u16,
+        }),
+        reserved32: [8]u8,
+        ///  Compensation cell control register
+        CMPCR: mmio.Mmio(packed struct(u32) {
+            ///  Compensation cell power-down
+            CMP_PD: u1,
+            reserved8: u7,
+            ///  READY
+            READY: u1,
+            padding: u23,
+        }),
+    };
+
+    ///  Serial peripheral interface
+    pub const SPI1 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Clock phase
+            CPHA: u1,
+            ///  Clock polarity
+            CPOL: u1,
+            ///  Master selection
+            MSTR: u1,
+            ///  Baud rate control
+            BR: u3,
+            ///  SPI enable
+            SPE: u1,
+            ///  Frame format
+            LSBFIRST: u1,
+            ///  Internal slave select
+            SSI: u1,
+            ///  Software slave management
+            SSM: u1,
+            ///  Receive only
+            RXONLY: u1,
+            ///  Data frame format
+            DFF: u1,
+            ///  CRC transfer next
+            CRCNEXT: u1,
+            ///  Hardware CRC calculation enable
+            CRCEN: u1,
+            ///  Output enable in bidirectional mode
+            BIDIOE: u1,
+            ///  Bidirectional data mode enable
+            BIDIMODE: u1,
+            padding: u16,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Rx buffer DMA enable
+            RXDMAEN: u1,
+            ///  Tx buffer DMA enable
+            TXDMAEN: u1,
+            ///  SS output enable
+            SSOE: u1,
+            reserved4: u1,
+            ///  Frame format
+            FRF: u1,
+            ///  Error interrupt enable
+            ERRIE: u1,
+            ///  RX buffer not empty interrupt enable
+            RXNEIE: u1,
+            ///  Tx buffer empty interrupt enable
+            TXEIE: u1,
+            padding: u24,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Receive buffer not empty
+            RXNE: u1,
+            ///  Transmit buffer empty
+            TXE: u1,
+            ///  Channel side
+            CHSIDE: u1,
+            ///  Underrun flag
+            UDR: u1,
+            ///  CRC error flag
+            CRCERR: u1,
+            ///  Mode fault
+            MODF: u1,
+            ///  Overrun flag
+            OVR: u1,
+            ///  Busy flag
+            BSY: u1,
+            ///  TI frame format error
+            TIFRFE: u1,
+            padding: u23,
+        }),
+        ///  data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data register
+            DR: u16,
+            padding: u16,
+        }),
+        ///  CRC polynomial register
+        CRCPR: mmio.Mmio(packed struct(u32) {
+            ///  CRC polynomial register
+            CRCPOLY: u16,
+            padding: u16,
+        }),
+        ///  RX CRC register
+        RXCRCR: mmio.Mmio(packed struct(u32) {
+            ///  Rx CRC register
+            RxCRC: u16,
+            padding: u16,
+        }),
+        ///  TX CRC register
+        TXCRCR: mmio.Mmio(packed struct(u32) {
+            ///  Tx CRC register
+            TxCRC: u16,
+            padding: u16,
+        }),
+        ///  I2S configuration register
+        I2SCFGR: mmio.Mmio(packed struct(u32) {
+            ///  Channel length (number of bits per audio channel)
+            CHLEN: u1,
+            ///  Data length to be transferred
+            DATLEN: u2,
+            ///  Steady state clock polarity
+            CKPOL: u1,
+            ///  I2S standard selection
+            I2SSTD: u2,
+            reserved7: u1,
+            ///  PCM frame synchronization
+            PCMSYNC: u1,
+            ///  I2S configuration mode
+            I2SCFG: u2,
+            ///  I2S Enable
+            I2SE: u1,
+            ///  I2S mode selection
+            I2SMOD: u1,
+            padding: u20,
+        }),
+        ///  I2S prescaler register
+        I2SPR: mmio.Mmio(packed struct(u32) {
+            ///  I2S Linear prescaler
+            I2SDIV: u8,
+            ///  Odd factor for the prescaler
+            ODD: u1,
+            ///  Master clock output enable
+            MCKOE: u1,
+            padding: u22,
+        }),
+    };
+
+    ///  LCD-TFT Controller
+    pub const LTDC = extern struct {
+        reserved8: [8]u8,
+        ///  Synchronization Size Configuration Register
+        SSCR: mmio.Mmio(packed struct(u32) {
+            ///  Vertical Synchronization Height (in units of horizontal scan line)
+            VSH: u11,
+            reserved16: u5,
+            ///  Horizontal Synchronization Width (in units of pixel clock period)
+            HSW: u10,
+            padding: u6,
+        }),
+        ///  Back Porch Configuration Register
+        BPCR: mmio.Mmio(packed struct(u32) {
+            ///  Accumulated Vertical back porch (in units of horizontal scan line)
+            AVBP: u11,
+            reserved16: u5,
+            ///  Accumulated Horizontal back porch (in units of pixel clock period)
+            AHBP: u10,
+            padding: u6,
+        }),
+        ///  Active Width Configuration Register
+        AWCR: mmio.Mmio(packed struct(u32) {
+            ///  Accumulated Active Height (in units of horizontal scan line)
+            AAH: u11,
+            reserved16: u5,
+            ///  AAV
+            AAV: u10,
+            padding: u6,
+        }),
+        ///  Total Width Configuration Register
+        TWCR: mmio.Mmio(packed struct(u32) {
+            ///  Total Height (in units of horizontal scan line)
+            TOTALH: u11,
+            reserved16: u5,
+            ///  Total Width (in units of pixel clock period)
+            TOTALW: u10,
+            padding: u6,
+        }),
+        ///  Global Control Register
+        GCR: mmio.Mmio(packed struct(u32) {
+            ///  LCD-TFT controller enable bit
+            LTDCEN: u1,
+            reserved4: u3,
+            ///  Dither Blue Width
+            DBW: u3,
+            reserved8: u1,
+            ///  Dither Green Width
+            DGW: u3,
+            reserved12: u1,
+            ///  Dither Red Width
+            DRW: u3,
+            reserved16: u1,
+            ///  Dither Enable
+            DEN: u1,
+            reserved28: u11,
+            ///  Pixel Clock Polarity
+            PCPOL: u1,
+            ///  Data Enable Polarity
+            DEPOL: u1,
+            ///  Vertical Synchronization Polarity
+            VSPOL: u1,
+            ///  Horizontal Synchronization Polarity
+            HSPOL: u1,
+        }),
+        reserved36: [8]u8,
+        ///  Shadow Reload Configuration Register
+        SRCR: mmio.Mmio(packed struct(u32) {
+            ///  Immediate Reload
+            IMR: u1,
+            ///  Vertical Blanking Reload
+            VBR: u1,
+            padding: u30,
+        }),
+        reserved44: [4]u8,
+        ///  Background Color Configuration Register
+        BCCR: mmio.Mmio(packed struct(u32) {
+            ///  Background Color Red value
+            BC: u24,
+            padding: u8,
+        }),
+        reserved52: [4]u8,
+        ///  Interrupt Enable Register
+        IER: mmio.Mmio(packed struct(u32) {
+            ///  Line Interrupt Enable
+            LIE: u1,
+            ///  FIFO Underrun Interrupt Enable
+            FUIE: u1,
+            ///  Transfer Error Interrupt Enable
+            TERRIE: u1,
+            ///  Register Reload interrupt enable
+            RRIE: u1,
+            padding: u28,
+        }),
+        ///  Interrupt Status Register
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  Line Interrupt flag
+            LIF: u1,
+            ///  FIFO Underrun Interrupt flag
+            FUIF: u1,
+            ///  Transfer Error interrupt flag
+            TERRIF: u1,
+            ///  Register Reload Interrupt Flag
+            RRIF: u1,
+            padding: u28,
+        }),
+        ///  Interrupt Clear Register
+        ICR: mmio.Mmio(packed struct(u32) {
+            ///  Clears the Line Interrupt Flag
+            CLIF: u1,
+            ///  Clears the FIFO Underrun Interrupt flag
+            CFUIF: u1,
+            ///  Clears the Transfer Error Interrupt Flag
+            CTERRIF: u1,
+            ///  Clears Register Reload Interrupt Flag
+            CRRIF: u1,
+            padding: u28,
+        }),
+        ///  Line Interrupt Position Configuration Register
+        LIPCR: mmio.Mmio(packed struct(u32) {
+            ///  Line Interrupt Position
+            LIPOS: u11,
+            padding: u21,
+        }),
+        ///  Current Position Status Register
+        CPSR: mmio.Mmio(packed struct(u32) {
+            ///  Current Y Position
+            CYPOS: u16,
+            ///  Current X Position
+            CXPOS: u16,
+        }),
+        ///  Current Display Status Register
+        CDSR: mmio.Mmio(packed struct(u32) {
+            ///  Vertical Data Enable display Status
+            VDES: u1,
+            ///  Horizontal Data Enable display Status
+            HDES: u1,
+            ///  Vertical Synchronization display Status
+            VSYNCS: u1,
+            ///  Horizontal Synchronization display Status
+            HSYNCS: u1,
+            padding: u28,
+        }),
+        reserved132: [56]u8,
+        ///  Layerx Control Register
+        L1CR: mmio.Mmio(packed struct(u32) {
+            ///  Layer Enable
+            LEN: u1,
+            ///  Color Keying Enable
+            COLKEN: u1,
+            reserved4: u2,
+            ///  Color Look-Up Table Enable
+            CLUTEN: u1,
+            padding: u27,
+        }),
+        ///  Layerx Window Horizontal Position Configuration Register
+        L1WHPCR: mmio.Mmio(packed struct(u32) {
+            ///  Window Horizontal Start Position
+            WHSTPOS: u12,
+            reserved16: u4,
+            ///  Window Horizontal Stop Position
+            WHSPPOS: u12,
+            padding: u4,
+        }),
+        ///  Layerx Window Vertical Position Configuration Register
+        L1WVPCR: mmio.Mmio(packed struct(u32) {
+            ///  Window Vertical Start Position
+            WVSTPOS: u11,
+            reserved16: u5,
+            ///  Window Vertical Stop Position
+            WVSPPOS: u11,
+            padding: u5,
+        }),
+        ///  Layerx Color Keying Configuration Register
+        L1CKCR: mmio.Mmio(packed struct(u32) {
+            ///  Color Key Blue value
+            CKBLUE: u8,
+            ///  Color Key Green value
+            CKGREEN: u8,
+            ///  Color Key Red value
+            CKRED: u8,
+            padding: u8,
+        }),
+        ///  Layerx Pixel Format Configuration Register
+        L1PFCR: mmio.Mmio(packed struct(u32) {
+            ///  Pixel Format
+            PF: u3,
+            padding: u29,
+        }),
+        ///  Layerx Constant Alpha Configuration Register
+        L1CACR: mmio.Mmio(packed struct(u32) {
+            ///  Constant Alpha
+            CONSTA: u8,
+            padding: u24,
+        }),
+        ///  Layerx Default Color Configuration Register
+        L1DCCR: mmio.Mmio(packed struct(u32) {
+            ///  Default Color Blue
+            DCBLUE: u8,
+            ///  Default Color Green
+            DCGREEN: u8,
+            ///  Default Color Red
+            DCRED: u8,
+            ///  Default Color Alpha
+            DCALPHA: u8,
+        }),
+        ///  Layerx Blending Factors Configuration Register
+        L1BFCR: mmio.Mmio(packed struct(u32) {
+            ///  Blending Factor 2
+            BF2: u3,
+            reserved8: u5,
+            ///  Blending Factor 1
+            BF1: u3,
+            padding: u21,
+        }),
+        reserved172: [8]u8,
+        ///  Layerx Color Frame Buffer Address Register
+        L1CFBAR: mmio.Mmio(packed struct(u32) {
+            ///  Color Frame Buffer Start Address
+            CFBADD: u32,
+        }),
+        ///  Layerx Color Frame Buffer Length Register
+        L1CFBLR: mmio.Mmio(packed struct(u32) {
+            ///  Color Frame Buffer Line Length
+            CFBLL: u13,
+            reserved16: u3,
+            ///  Color Frame Buffer Pitch in bytes
+            CFBP: u13,
+            padding: u3,
+        }),
+        ///  Layerx ColorFrame Buffer Line Number Register
+        L1CFBLNR: mmio.Mmio(packed struct(u32) {
+            ///  Frame Buffer Line Number
+            CFBLNBR: u11,
+            padding: u21,
+        }),
+        reserved196: [12]u8,
+        ///  Layerx CLUT Write Register
+        L1CLUTWR: mmio.Mmio(packed struct(u32) {
+            ///  Blue value
+            BLUE: u8,
+            ///  Green value
+            GREEN: u8,
+            ///  Red value
+            RED: u8,
+            ///  CLUT Address
+            CLUTADD: u8,
+        }),
+        reserved260: [60]u8,
+        ///  Layerx Control Register
+        L2CR: mmio.Mmio(packed struct(u32) {
+            ///  Layer Enable
+            LEN: u1,
+            ///  Color Keying Enable
+            COLKEN: u1,
+            reserved4: u2,
+            ///  Color Look-Up Table Enable
+            CLUTEN: u1,
+            padding: u27,
+        }),
+        ///  Layerx Window Horizontal Position Configuration Register
+        L2WHPCR: mmio.Mmio(packed struct(u32) {
+            ///  Window Horizontal Start Position
+            WHSTPOS: u12,
+            reserved16: u4,
+            ///  Window Horizontal Stop Position
+            WHSPPOS: u12,
+            padding: u4,
+        }),
+        ///  Layerx Window Vertical Position Configuration Register
+        L2WVPCR: mmio.Mmio(packed struct(u32) {
+            ///  Window Vertical Start Position
+            WVSTPOS: u11,
+            reserved16: u5,
+            ///  Window Vertical Stop Position
+            WVSPPOS: u11,
+            padding: u5,
+        }),
+        ///  Layerx Color Keying Configuration Register
+        L2CKCR: mmio.Mmio(packed struct(u32) {
+            ///  Color Key Blue value
+            CKBLUE: u8,
+            ///  Color Key Green value
+            CKGREEN: u7,
+            ///  Color Key Red value
+            CKRED: u9,
+            padding: u8,
+        }),
+        ///  Layerx Pixel Format Configuration Register
+        L2PFCR: mmio.Mmio(packed struct(u32) {
+            ///  Pixel Format
+            PF: u3,
+            padding: u29,
+        }),
+        ///  Layerx Constant Alpha Configuration Register
+        L2CACR: mmio.Mmio(packed struct(u32) {
+            ///  Constant Alpha
+            CONSTA: u8,
+            padding: u24,
+        }),
+        ///  Layerx Default Color Configuration Register
+        L2DCCR: mmio.Mmio(packed struct(u32) {
+            ///  Default Color Blue
+            DCBLUE: u8,
+            ///  Default Color Green
+            DCGREEN: u8,
+            ///  Default Color Red
+            DCRED: u8,
+            ///  Default Color Alpha
+            DCALPHA: u8,
+        }),
+        ///  Layerx Blending Factors Configuration Register
+        L2BFCR: mmio.Mmio(packed struct(u32) {
+            ///  Blending Factor 2
+            BF2: u3,
+            reserved8: u5,
+            ///  Blending Factor 1
+            BF1: u3,
+            padding: u21,
+        }),
+        reserved300: [8]u8,
+        ///  Layerx Color Frame Buffer Address Register
+        L2CFBAR: mmio.Mmio(packed struct(u32) {
+            ///  Color Frame Buffer Start Address
+            CFBADD: u32,
+        }),
+        ///  Layerx Color Frame Buffer Length Register
+        L2CFBLR: mmio.Mmio(packed struct(u32) {
+            ///  Color Frame Buffer Line Length
+            CFBLL: u13,
+            reserved16: u3,
+            ///  Color Frame Buffer Pitch in bytes
+            CFBP: u13,
+            padding: u3,
+        }),
+        ///  Layerx ColorFrame Buffer Line Number Register
+        L2CFBLNR: mmio.Mmio(packed struct(u32) {
+            ///  Frame Buffer Line Number
+            CFBLNBR: u11,
+            padding: u21,
+        }),
+        reserved324: [12]u8,
+        ///  Layerx CLUT Write Register
+        L2CLUTWR: mmio.Mmio(packed struct(u32) {
+            ///  Blue value
+            BLUE: u8,
+            ///  Green value
+            GREEN: u8,
+            ///  Red value
+            RED: u8,
+            ///  CLUT Address
+            CLUTADD: u8,
+        }),
+    };
+
+    ///  Serial audio interface
+    pub const SAI1 = extern struct {
+        reserved4: [4]u8,
+        ///  SAI AConfiguration register 1
+        SAI_ACR1: mmio.Mmio(packed struct(u32) {
+            ///  Audio block mode
+            MODE: u2,
+            ///  Protocol configuration
+            PRTCFG: u2,
+            reserved5: u1,
+            ///  Data size
+            DS: u3,
+            ///  Least significant bit first
+            LSBFIRST: u1,
+            ///  Clock strobing edge
+            CKSTR: u1,
+            ///  Synchronization enable
+            SYNCEN: u2,
+            ///  Mono mode
+            MONO: u1,
+            ///  Output drive
+            OUTDRIV: u1,
+            reserved16: u2,
+            ///  Audio block enable
+            SAIAEN: u1,
+            ///  DMA enable
+            DMAEN: u1,
+            reserved19: u1,
+            ///  No divider
+            NODIV: u1,
+            ///  Master clock divider
+            MCKDIV: u4,
+            padding: u8,
+        }),
+        ///  SAI AConfiguration register 2
+        SAI_ACR2: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold
+            FTH: u3,
+            ///  FIFO flush
+            FFLUSH: u1,
+            ///  Tristate management on data line
+            TRIS: u1,
+            ///  Mute
+            MUTE: u1,
+            ///  Mute value
+            MUTEVAL: u1,
+            ///  Mute counter
+            MUTECNT: u6,
+            ///  Complement bit
+            CPL: u1,
+            ///  Companding mode
+            COMP: u2,
+            padding: u16,
+        }),
+        ///  SAI AFrame configuration register
+        SAI_AFRCR: mmio.Mmio(packed struct(u32) {
+            ///  Frame length
+            FRL: u8,
+            ///  Frame synchronization active level length
+            FSALL: u7,
+            reserved16: u1,
+            ///  Frame synchronization definition
+            FSDEF: u1,
+            ///  Frame synchronization polarity
+            FSPOL: u1,
+            ///  Frame synchronization offset
+            FSOFF: u1,
+            padding: u13,
+        }),
+        ///  SAI ASlot register
+        SAI_ASLOTR: mmio.Mmio(packed struct(u32) {
+            ///  First bit offset
+            FBOFF: u5,
+            reserved6: u1,
+            ///  Slot size
+            SLOTSZ: u2,
+            ///  Number of slots in an audio frame
+            NBSLOT: u4,
+            reserved16: u4,
+            ///  Slot enable
+            SLOTEN: u16,
+        }),
+        ///  SAI AInterrupt mask register2
+        SAI_AIM: mmio.Mmio(packed struct(u32) {
+            ///  Overrun/underrun interrupt enable
+            OVRUDRIE: u1,
+            ///  Mute detection interrupt enable
+            MUTEDETIE: u1,
+            ///  Wrong clock configuration interrupt enable
+            WCKCFGIE: u1,
+            ///  FIFO request interrupt enable
+            FREQIE: u1,
+            ///  Codec not ready interrupt enable
+            CNRDYIE: u1,
+            ///  Anticipated frame synchronization detection interrupt enable
+            AFSDETIE: u1,
+            ///  Late frame synchronization detection interrupt enable
+            LFSDETIE: u1,
+            padding: u25,
+        }),
+        ///  SAI AStatus register
+        SAI_ASR: mmio.Mmio(packed struct(u32) {
+            ///  Overrun / underrun
+            OVRUDR: u1,
+            ///  Mute detection
+            MUTEDET: u1,
+            ///  Wrong clock configuration flag
+            WCKCFG: u1,
+            ///  FIFO request
+            FREQ: u1,
+            ///  Codec not ready
+            CNRDY: u1,
+            ///  Anticipated frame synchronization detection
+            AFSDET: u1,
+            ///  Late frame synchronization detection
+            LFSDET: u1,
+            reserved16: u9,
+            ///  FIFO level threshold
+            FLTH: u3,
+            padding: u13,
+        }),
+        ///  SAI AClear flag register
+        SAI_ACLRFR: mmio.Mmio(packed struct(u32) {
+            ///  Clear overrun / underrun
+            COVRUDR: u1,
+            ///  Mute detection flag
+            CMUTEDET: u1,
+            ///  Clear wrong clock configuration flag
+            CWCKCFG: u1,
+            reserved4: u1,
+            ///  Clear codec not ready flag
+            CCNRDY: u1,
+            ///  Clear anticipated frame synchronization detection flag
+            CAFSDET: u1,
+            ///  Clear late frame synchronization detection flag
+            CLFSDET: u1,
+            padding: u25,
+        }),
+        ///  SAI AData register
+        SAI_ADR: mmio.Mmio(packed struct(u32) {
+            ///  Data
+            DATA: u32,
+        }),
+        ///  SAI BConfiguration register 1
+        SAI_BCR1: mmio.Mmio(packed struct(u32) {
+            ///  Audio block mode
+            MODE: u2,
+            ///  Protocol configuration
+            PRTCFG: u2,
+            reserved5: u1,
+            ///  Data size
+            DS: u3,
+            ///  Least significant bit first
+            LSBFIRST: u1,
+            ///  Clock strobing edge
+            CKSTR: u1,
+            ///  Synchronization enable
+            SYNCEN: u2,
+            ///  Mono mode
+            MONO: u1,
+            ///  Output drive
+            OUTDRIV: u1,
+            reserved16: u2,
+            ///  Audio block enable
+            SAIBEN: u1,
+            ///  DMA enable
+            DMAEN: u1,
+            reserved19: u1,
+            ///  No divider
+            NODIV: u1,
+            ///  Master clock divider
+            MCKDIV: u4,
+            padding: u8,
+        }),
+        ///  SAI BConfiguration register 2
+        SAI_BCR2: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold
+            FTH: u3,
+            ///  FIFO flush
+            FFLUSH: u1,
+            ///  Tristate management on data line
+            TRIS: u1,
+            ///  Mute
+            MUTE: u1,
+            ///  Mute value
+            MUTEVAL: u1,
+            ///  Mute counter
+            MUTECNT: u6,
+            ///  Complement bit
+            CPL: u1,
+            ///  Companding mode
+            COMP: u2,
+            padding: u16,
+        }),
+        ///  SAI BFrame configuration register
+        SAI_BFRCR: mmio.Mmio(packed struct(u32) {
+            ///  Frame length
+            FRL: u8,
+            ///  Frame synchronization active level length
+            FSALL: u7,
+            reserved16: u1,
+            ///  Frame synchronization definition
+            FSDEF: u1,
+            ///  Frame synchronization polarity
+            FSPOL: u1,
+            ///  Frame synchronization offset
+            FSOFF: u1,
+            padding: u13,
+        }),
+        ///  SAI BSlot register
+        SAI_BSLOTR: mmio.Mmio(packed struct(u32) {
+            ///  First bit offset
+            FBOFF: u5,
+            reserved6: u1,
+            ///  Slot size
+            SLOTSZ: u2,
+            ///  Number of slots in an audio frame
+            NBSLOT: u4,
+            reserved16: u4,
+            ///  Slot enable
+            SLOTEN: u16,
+        }),
+        ///  SAI BInterrupt mask register2
+        SAI_BIM: mmio.Mmio(packed struct(u32) {
+            ///  Overrun/underrun interrupt enable
+            OVRUDRIE: u1,
+            ///  Mute detection interrupt enable
+            MUTEDETIE: u1,
+            ///  Wrong clock configuration interrupt enable
+            WCKCFGIE: u1,
+            ///  FIFO request interrupt enable
+            FREQIE: u1,
+            ///  Codec not ready interrupt enable
+            CNRDYIE: u1,
+            ///  Anticipated frame synchronization detection interrupt enable
+            AFSDETIE: u1,
+            ///  Late frame synchronization detection interrupt enable
+            LFSDETIE: u1,
+            padding: u25,
+        }),
+        ///  SAI BStatus register
+        SAI_BSR: mmio.Mmio(packed struct(u32) {
+            ///  Overrun / underrun
+            OVRUDR: u1,
+            ///  Mute detection
+            MUTEDET: u1,
+            ///  Wrong clock configuration flag
+            WCKCFG: u1,
+            ///  FIFO request
+            FREQ: u1,
+            ///  Codec not ready
+            CNRDY: u1,
+            ///  Anticipated frame synchronization detection
+            AFSDET: u1,
+            ///  Late frame synchronization detection
+            LFSDET: u1,
+            reserved16: u9,
+            ///  FIFO level threshold
+            FLTH: u3,
+            padding: u13,
+        }),
+        ///  SAI BClear flag register
+        SAI_BCLRFR: mmio.Mmio(packed struct(u32) {
+            ///  Clear overrun / underrun
+            COVRUDR: u1,
+            ///  Mute detection flag
+            CMUTEDET: u1,
+            ///  Clear wrong clock configuration flag
+            CWCKCFG: u1,
+            reserved4: u1,
+            ///  Clear codec not ready flag
+            CCNRDY: u1,
+            ///  Clear anticipated frame synchronization detection flag
+            CAFSDET: u1,
+            ///  Clear late frame synchronization detection flag
+            CLFSDET: u1,
+            padding: u25,
+        }),
+        ///  SAI BData register
+        SAI_BDR: mmio.Mmio(packed struct(u32) {
+            ///  Data
+            DATA: u32,
+        }),
+    };
+
+    ///  Nested Vectored Interrupt Controller
+    pub const NVIC = extern struct {
+        ///  Interrupt Set-Enable Register
+        ISER0: mmio.Mmio(packed struct(u32) {
+            ///  SETENA
+            SETENA: u32,
+        }),
+        ///  Interrupt Set-Enable Register
+        ISER1: mmio.Mmio(packed struct(u32) {
+            ///  SETENA
+            SETENA: u32,
+        }),
+        ///  Interrupt Set-Enable Register
+        ISER2: mmio.Mmio(packed struct(u32) {
+            ///  SETENA
+            SETENA: u32,
+        }),
+        reserved128: [116]u8,
+        ///  Interrupt Clear-Enable Register
+        ICER0: mmio.Mmio(packed struct(u32) {
+            ///  CLRENA
+            CLRENA: u32,
+        }),
+        ///  Interrupt Clear-Enable Register
+        ICER1: mmio.Mmio(packed struct(u32) {
+            ///  CLRENA
+            CLRENA: u32,
+        }),
+        ///  Interrupt Clear-Enable Register
+        ICER2: mmio.Mmio(packed struct(u32) {
+            ///  CLRENA
+            CLRENA: u32,
+        }),
+        reserved256: [116]u8,
+        ///  Interrupt Set-Pending Register
+        ISPR0: mmio.Mmio(packed struct(u32) {
+            ///  SETPEND
+            SETPEND: u32,
+        }),
+        ///  Interrupt Set-Pending Register
+        ISPR1: mmio.Mmio(packed struct(u32) {
+            ///  SETPEND
+            SETPEND: u32,
+        }),
+        ///  Interrupt Set-Pending Register
+        ISPR2: mmio.Mmio(packed struct(u32) {
+            ///  SETPEND
+            SETPEND: u32,
+        }),
+        reserved384: [116]u8,
+        ///  Interrupt Clear-Pending Register
+        ICPR0: mmio.Mmio(packed struct(u32) {
+            ///  CLRPEND
+            CLRPEND: u32,
+        }),
+        ///  Interrupt Clear-Pending Register
+        ICPR1: mmio.Mmio(packed struct(u32) {
+            ///  CLRPEND
+            CLRPEND: u32,
+        }),
+        ///  Interrupt Clear-Pending Register
+        ICPR2: mmio.Mmio(packed struct(u32) {
+            ///  CLRPEND
+            CLRPEND: u32,
+        }),
+        reserved512: [116]u8,
+        ///  Interrupt Active Bit Register
+        IABR0: mmio.Mmio(packed struct(u32) {
+            ///  ACTIVE
+            ACTIVE: u32,
+        }),
+        ///  Interrupt Active Bit Register
+        IABR1: mmio.Mmio(packed struct(u32) {
+            ///  ACTIVE
+            ACTIVE: u32,
+        }),
+        ///  Interrupt Active Bit Register
+        IABR2: mmio.Mmio(packed struct(u32) {
+            ///  ACTIVE
+            ACTIVE: u32,
+        }),
+        reserved768: [244]u8,
+        ///  Interrupt Priority Register
+        IPR0: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR1: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR2: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR3: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR4: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR5: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR6: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR7: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR8: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR9: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR10: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR11: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR12: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR13: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR14: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR15: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR16: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR17: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR18: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR19: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+    };
+
+    ///  USB on the go high speed
+    pub const OTG_HS_PWRCLK = extern struct {
+        ///  Power and clock gating control register
+        OTG_HS_PCGCR: mmio.Mmio(packed struct(u32) {
+            ///  Stop PHY clock
+            STPPCLK: u1,
+            ///  Gate HCLK
+            GATEHCLK: u1,
+            reserved4: u2,
+            ///  PHY suspended
+            PHYSUSP: u1,
+            padding: u27,
+        }),
+    };
+
+    ///  USB on the go high speed
+    pub const OTG_HS_DEVICE = extern struct {
+        ///  OTG_HS device configuration register
+        OTG_HS_DCFG: mmio.Mmio(packed struct(u32) {
+            ///  Device speed
+            DSPD: u2,
+            ///  Nonzero-length status OUT handshake
+            NZLSOHSK: u1,
+            reserved4: u1,
+            ///  Device address
+            DAD: u7,
+            ///  Periodic (micro)frame interval
+            PFIVL: u2,
+            reserved24: u11,
+            ///  Periodic scheduling interval
+            PERSCHIVL: u2,
+            padding: u6,
+        }),
+        ///  OTG_HS device control register
+        OTG_HS_DCTL: mmio.Mmio(packed struct(u32) {
+            ///  Remote wakeup signaling
+            RWUSIG: u1,
+            ///  Soft disconnect
+            SDIS: u1,
+            ///  Global IN NAK status
+            GINSTS: u1,
+            ///  Global OUT NAK status
+            GONSTS: u1,
+            ///  Test control
+            TCTL: u3,
+            ///  Set global IN NAK
+            SGINAK: u1,
+            ///  Clear global IN NAK
+            CGINAK: u1,
+            ///  Set global OUT NAK
+            SGONAK: u1,
+            ///  Clear global OUT NAK
+            CGONAK: u1,
+            ///  Power-on programming done
+            POPRGDNE: u1,
+            padding: u20,
+        }),
+        ///  OTG_HS device status register
+        OTG_HS_DSTS: mmio.Mmio(packed struct(u32) {
+            ///  Suspend status
+            SUSPSTS: u1,
+            ///  Enumerated speed
+            ENUMSPD: u2,
+            ///  Erratic error
+            EERR: u1,
+            reserved8: u4,
+            ///  Frame number of the received SOF
+            FNSOF: u14,
+            padding: u10,
+        }),
+        reserved16: [4]u8,
+        ///  OTG_HS device IN endpoint common interrupt mask register
+        OTG_HS_DIEPMSK: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  Timeout condition mask (nonisochronous endpoints)
+            TOM: u1,
+            ///  IN token received when TxFIFO empty mask
+            ITTXFEMSK: u1,
+            ///  IN token received with EP mismatch mask
+            INEPNMM: u1,
+            ///  IN endpoint NAK effective mask
+            INEPNEM: u1,
+            reserved8: u1,
+            ///  FIFO underrun mask
+            TXFURM: u1,
+            ///  BNA interrupt mask
+            BIM: u1,
+            padding: u22,
+        }),
+        ///  OTG_HS device OUT endpoint common interrupt mask register
+        OTG_HS_DOEPMSK: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  SETUP phase done mask
+            STUPM: u1,
+            ///  OUT token received when endpoint disabled mask
+            OTEPDM: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received mask
+            B2BSTUP: u1,
+            reserved8: u1,
+            ///  OUT packet error mask
+            OPEM: u1,
+            ///  BNA interrupt mask
+            BOIM: u1,
+            padding: u22,
+        }),
+        ///  OTG_HS device all endpoints interrupt register
+        OTG_HS_DAINT: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint interrupt bits
+            IEPINT: u16,
+            ///  OUT endpoint interrupt bits
+            OEPINT: u16,
+        }),
+        ///  OTG_HS all endpoints interrupt mask register
+        OTG_HS_DAINTMSK: mmio.Mmio(packed struct(u32) {
+            ///  IN EP interrupt mask bits
+            IEPM: u16,
+            ///  OUT EP interrupt mask bits
+            OEPM: u16,
+        }),
+        reserved40: [8]u8,
+        ///  OTG_HS device VBUS discharge time register
+        OTG_HS_DVBUSDIS: mmio.Mmio(packed struct(u32) {
+            ///  Device VBUS discharge time
+            VBUSDT: u16,
+            padding: u16,
+        }),
+        ///  OTG_HS device VBUS pulsing time register
+        OTG_HS_DVBUSPULSE: mmio.Mmio(packed struct(u32) {
+            ///  Device VBUS pulsing time
+            DVBUSP: u12,
+            padding: u20,
+        }),
+        ///  OTG_HS Device threshold control register
+        OTG_HS_DTHRCTL: mmio.Mmio(packed struct(u32) {
+            ///  Nonisochronous IN endpoints threshold enable
+            NONISOTHREN: u1,
+            ///  ISO IN endpoint threshold enable
+            ISOTHREN: u1,
+            ///  Transmit threshold length
+            TXTHRLEN: u9,
+            reserved16: u5,
+            ///  Receive threshold enable
+            RXTHREN: u1,
+            ///  Receive threshold length
+            RXTHRLEN: u9,
+            reserved27: u1,
+            ///  Arbiter parking enable
+            ARPEN: u1,
+            padding: u4,
+        }),
+        ///  OTG_HS device IN endpoint FIFO empty interrupt mask register
+        OTG_HS_DIEPEMPMSK: mmio.Mmio(packed struct(u32) {
+            ///  IN EP Tx FIFO empty interrupt mask bits
+            INEPTXFEM: u16,
+            padding: u16,
+        }),
+        ///  OTG_HS device each endpoint interrupt register
+        OTG_HS_DEACHINT: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  IN endpoint 1interrupt bit
+            IEP1INT: u1,
+            reserved17: u15,
+            ///  OUT endpoint 1 interrupt bit
+            OEP1INT: u1,
+            padding: u14,
+        }),
+        ///  OTG_HS device each endpoint interrupt register mask
+        OTG_HS_DEACHINTMSK: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  IN Endpoint 1 interrupt mask bit
+            IEP1INTM: u1,
+            reserved17: u15,
+            ///  OUT Endpoint 1 interrupt mask bit
+            OEP1INTM: u1,
+            padding: u14,
+        }),
+        ///  OTG_HS device each in endpoint-1 interrupt register
+        OTG_HS_DIEPEACHMSK1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  Timeout condition mask (nonisochronous endpoints)
+            TOM: u1,
+            ///  IN token received when TxFIFO empty mask
+            ITTXFEMSK: u1,
+            ///  IN token received with EP mismatch mask
+            INEPNMM: u1,
+            ///  IN endpoint NAK effective mask
+            INEPNEM: u1,
+            reserved8: u1,
+            ///  FIFO underrun mask
+            TXFURM: u1,
+            ///  BNA interrupt mask
+            BIM: u1,
+            reserved13: u3,
+            ///  NAK interrupt mask
+            NAKM: u1,
+            padding: u18,
+        }),
+        reserved128: [60]u8,
+        ///  OTG_HS device each OUT endpoint-1 interrupt register
+        OTG_HS_DOEPEACHMSK1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  Timeout condition mask
+            TOM: u1,
+            ///  IN token received when TxFIFO empty mask
+            ITTXFEMSK: u1,
+            ///  IN token received with EP mismatch mask
+            INEPNMM: u1,
+            ///  IN endpoint NAK effective mask
+            INEPNEM: u1,
+            reserved8: u1,
+            ///  OUT packet error mask
+            TXFURM: u1,
+            ///  BNA interrupt mask
+            BIM: u1,
+            reserved12: u2,
+            ///  Bubble error interrupt mask
+            BERRM: u1,
+            ///  NAK interrupt mask
+            NAKM: u1,
+            ///  NYET interrupt mask
+            NYETM: u1,
+            padding: u17,
+        }),
+        reserved256: [124]u8,
+        ///  OTG device endpoint-0 control register
+        OTG_HS_DIEPCTL0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved264: [4]u8,
+        ///  OTG device endpoint-0 interrupt register
+        OTG_HS_DIEPINT0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved272: [4]u8,
+        ///  OTG_HS device IN endpoint 0 transfer size register
+        OTG_HS_DIEPTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u7,
+            reserved19: u12,
+            ///  Packet count
+            PKTCNT: u2,
+            padding: u11,
+        }),
+        ///  OTG_HS device endpoint-1 DMA address register
+        OTG_HS_DIEPDMA1: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS0: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved288: [4]u8,
+        ///  OTG device endpoint-1 control register
+        OTG_HS_DIEPCTL1: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved296: [4]u8,
+        ///  OTG device endpoint-1 interrupt register
+        OTG_HS_DIEPINT1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved304: [4]u8,
+        ///  OTG_HS device endpoint transfer size register
+        OTG_HS_DIEPTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS device endpoint-2 DMA address register
+        OTG_HS_DIEPDMA2: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS1: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved320: [4]u8,
+        ///  OTG device endpoint-2 control register
+        OTG_HS_DIEPCTL2: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved328: [4]u8,
+        ///  OTG device endpoint-2 interrupt register
+        OTG_HS_DIEPINT2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved336: [4]u8,
+        ///  OTG_HS device endpoint transfer size register
+        OTG_HS_DIEPTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS device endpoint-3 DMA address register
+        OTG_HS_DIEPDMA3: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS2: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved352: [4]u8,
+        ///  OTG device endpoint-3 control register
+        OTG_HS_DIEPCTL3: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved360: [4]u8,
+        ///  OTG device endpoint-3 interrupt register
+        OTG_HS_DIEPINT3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved368: [4]u8,
+        ///  OTG_HS device endpoint transfer size register
+        OTG_HS_DIEPTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS device endpoint-4 DMA address register
+        OTG_HS_DIEPDMA4: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS3: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved384: [4]u8,
+        ///  OTG device endpoint-4 control register
+        OTG_HS_DIEPCTL4: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved392: [4]u8,
+        ///  OTG device endpoint-4 interrupt register
+        OTG_HS_DIEPINT4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved400: [4]u8,
+        ///  OTG_HS device endpoint transfer size register
+        OTG_HS_DIEPTSIZ4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS device endpoint-5 DMA address register
+        OTG_HS_DIEPDMA5: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS4: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved416: [4]u8,
+        ///  OTG device endpoint-5 control register
+        OTG_HS_DIEPCTL5: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved424: [4]u8,
+        ///  OTG device endpoint-5 interrupt register
+        OTG_HS_DIEPINT5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved432: [4]u8,
+        ///  OTG_HS device endpoint transfer size register
+        OTG_HS_DIEPTSIZ5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        reserved440: [4]u8,
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS5: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved448: [4]u8,
+        ///  OTG device endpoint-6 control register
+        OTG_HS_DIEPCTL6: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved456: [4]u8,
+        ///  OTG device endpoint-6 interrupt register
+        OTG_HS_DIEPINT6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved480: [20]u8,
+        ///  OTG device endpoint-7 control register
+        OTG_HS_DIEPCTL7: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved488: [4]u8,
+        ///  OTG device endpoint-7 interrupt register
+        OTG_HS_DIEPINT7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved768: [276]u8,
+        ///  OTG_HS device control OUT endpoint 0 control register
+        OTG_HS_DOEPCTL0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u2,
+            reserved15: u13,
+            ///  USB active endpoint
+            USBAEP: u1,
+            reserved17: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Snoop mode
+            SNPM: u1,
+            ///  STALL handshake
+            Stall: u1,
+            reserved26: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            reserved30: u2,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved776: [4]u8,
+        ///  OTG_HS device endpoint-0 interrupt register
+        OTG_HS_DOEPINT0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved784: [4]u8,
+        ///  OTG_HS device endpoint-1 transfer size register
+        OTG_HS_DOEPTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u7,
+            reserved19: u12,
+            ///  Packet count
+            PKTCNT: u1,
+            reserved29: u9,
+            ///  SETUP packet count
+            STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved800: [12]u8,
+        ///  OTG device endpoint-1 control register
+        OTG_HS_DOEPCTL1: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even odd frame/Endpoint data PID
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Snoop mode
+            SNPM: u1,
+            ///  STALL handshake
+            Stall: u1,
+            reserved26: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID/Set even frame
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved808: [4]u8,
+        ///  OTG_HS device endpoint-1 interrupt register
+        OTG_HS_DOEPINT1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved816: [4]u8,
+        ///  OTG_HS device endpoint-2 transfer size register
+        OTG_HS_DOEPTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved832: [12]u8,
+        ///  OTG device endpoint-2 control register
+        OTG_HS_DOEPCTL2: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even odd frame/Endpoint data PID
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Snoop mode
+            SNPM: u1,
+            ///  STALL handshake
+            Stall: u1,
+            reserved26: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID/Set even frame
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved840: [4]u8,
+        ///  OTG_HS device endpoint-2 interrupt register
+        OTG_HS_DOEPINT2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved848: [4]u8,
+        ///  OTG_HS device endpoint-3 transfer size register
+        OTG_HS_DOEPTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved864: [12]u8,
+        ///  OTG device endpoint-3 control register
+        OTG_HS_DOEPCTL3: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even odd frame/Endpoint data PID
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Snoop mode
+            SNPM: u1,
+            ///  STALL handshake
+            Stall: u1,
+            reserved26: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID/Set even frame
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved872: [4]u8,
+        ///  OTG_HS device endpoint-3 interrupt register
+        OTG_HS_DOEPINT3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved880: [4]u8,
+        ///  OTG_HS device endpoint-4 transfer size register
+        OTG_HS_DOEPTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved904: [20]u8,
+        ///  OTG_HS device endpoint-4 interrupt register
+        OTG_HS_DOEPINT4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved912: [4]u8,
+        ///  OTG_HS device endpoint-5 transfer size register
+        OTG_HS_DOEPTSIZ4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved936: [20]u8,
+        ///  OTG_HS device endpoint-5 interrupt register
+        OTG_HS_DOEPINT5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved968: [28]u8,
+        ///  OTG_HS device endpoint-6 interrupt register
+        OTG_HS_DOEPINT6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved1000: [28]u8,
+        ///  OTG_HS device endpoint-7 interrupt register
+        OTG_HS_DOEPINT7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+    };
+
+    ///  USB on the go high speed
+    pub const OTG_HS_HOST = extern struct {
+        ///  OTG_HS host configuration register
+        OTG_HS_HCFG: mmio.Mmio(packed struct(u32) {
+            ///  FS/LS PHY clock select
+            FSLSPCS: u2,
+            ///  FS- and LS-only support
+            FSLSS: u1,
+            padding: u29,
+        }),
+        ///  OTG_HS Host frame interval register
+        OTG_HS_HFIR: mmio.Mmio(packed struct(u32) {
+            ///  Frame interval
+            FRIVL: u16,
+            padding: u16,
+        }),
+        ///  OTG_HS host frame number/frame time remaining register
+        OTG_HS_HFNUM: mmio.Mmio(packed struct(u32) {
+            ///  Frame number
+            FRNUM: u16,
+            ///  Frame time remaining
+            FTREM: u16,
+        }),
+        reserved16: [4]u8,
+        ///  OTG_HS_Host periodic transmit FIFO/queue status register
+        OTG_HS_HPTXSTS: mmio.Mmio(packed struct(u32) {
+            ///  Periodic transmit data FIFO space available
+            PTXFSAVL: u16,
+            ///  Periodic transmit request queue space available
+            PTXQSAV: u8,
+            ///  Top of the periodic transmit request queue
+            PTXQTOP: u8,
+        }),
+        ///  OTG_HS Host all channels interrupt register
+        OTG_HS_HAINT: mmio.Mmio(packed struct(u32) {
+            ///  Channel interrupts
+            HAINT: u16,
+            padding: u16,
+        }),
+        ///  OTG_HS host all channels interrupt mask register
+        OTG_HS_HAINTMSK: mmio.Mmio(packed struct(u32) {
+            ///  Channel interrupt mask
+            HAINTM: u16,
+            padding: u16,
+        }),
+        reserved64: [36]u8,
+        ///  OTG_HS host port control and status register
+        OTG_HS_HPRT: mmio.Mmio(packed struct(u32) {
+            ///  Port connect status
+            PCSTS: u1,
+            ///  Port connect detected
+            PCDET: u1,
+            ///  Port enable
+            PENA: u1,
+            ///  Port enable/disable change
+            PENCHNG: u1,
+            ///  Port overcurrent active
+            POCA: u1,
+            ///  Port overcurrent change
+            POCCHNG: u1,
+            ///  Port resume
+            PRES: u1,
+            ///  Port suspend
+            PSUSP: u1,
+            ///  Port reset
+            PRST: u1,
+            reserved10: u1,
+            ///  Port line status
+            PLSTS: u2,
+            ///  Port power
+            PPWR: u1,
+            ///  Port test control
+            PTCTL: u4,
+            ///  Port speed
+            PSPD: u2,
+            padding: u13,
+        }),
+        reserved256: [188]u8,
+        ///  OTG_HS host channel-0 characteristics register
+        OTG_HS_HCCHAR0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-0 split control register
+        OTG_HS_HCSPLT0: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-11 interrupt register
+        OTG_HS_HCINT0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-11 interrupt mask register
+        OTG_HS_HCINTMSK0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-11 transfer size register
+        OTG_HS_HCTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-0 DMA address register
+        OTG_HS_HCDMA0: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved288: [8]u8,
+        ///  OTG_HS host channel-1 characteristics register
+        OTG_HS_HCCHAR1: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-1 split control register
+        OTG_HS_HCSPLT1: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-1 interrupt register
+        OTG_HS_HCINT1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-1 interrupt mask register
+        OTG_HS_HCINTMSK1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-1 transfer size register
+        OTG_HS_HCTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-1 DMA address register
+        OTG_HS_HCDMA1: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved320: [8]u8,
+        ///  OTG_HS host channel-2 characteristics register
+        OTG_HS_HCCHAR2: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-2 split control register
+        OTG_HS_HCSPLT2: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-2 interrupt register
+        OTG_HS_HCINT2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-2 interrupt mask register
+        OTG_HS_HCINTMSK2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-2 transfer size register
+        OTG_HS_HCTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-2 DMA address register
+        OTG_HS_HCDMA2: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved352: [8]u8,
+        ///  OTG_HS host channel-3 characteristics register
+        OTG_HS_HCCHAR3: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-3 split control register
+        OTG_HS_HCSPLT3: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-3 interrupt register
+        OTG_HS_HCINT3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-3 interrupt mask register
+        OTG_HS_HCINTMSK3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-3 transfer size register
+        OTG_HS_HCTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-3 DMA address register
+        OTG_HS_HCDMA3: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved384: [8]u8,
+        ///  OTG_HS host channel-4 characteristics register
+        OTG_HS_HCCHAR4: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-4 split control register
+        OTG_HS_HCSPLT4: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-4 interrupt register
+        OTG_HS_HCINT4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-4 interrupt mask register
+        OTG_HS_HCINTMSK4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-4 transfer size register
+        OTG_HS_HCTSIZ4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-4 DMA address register
+        OTG_HS_HCDMA4: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved416: [8]u8,
+        ///  OTG_HS host channel-5 characteristics register
+        OTG_HS_HCCHAR5: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-5 split control register
+        OTG_HS_HCSPLT5: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-5 interrupt register
+        OTG_HS_HCINT5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-5 interrupt mask register
+        OTG_HS_HCINTMSK5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-5 transfer size register
+        OTG_HS_HCTSIZ5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-5 DMA address register
+        OTG_HS_HCDMA5: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved448: [8]u8,
+        ///  OTG_HS host channel-6 characteristics register
+        OTG_HS_HCCHAR6: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-6 split control register
+        OTG_HS_HCSPLT6: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-6 interrupt register
+        OTG_HS_HCINT6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-6 interrupt mask register
+        OTG_HS_HCINTMSK6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-6 transfer size register
+        OTG_HS_HCTSIZ6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-6 DMA address register
+        OTG_HS_HCDMA6: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved480: [8]u8,
+        ///  OTG_HS host channel-7 characteristics register
+        OTG_HS_HCCHAR7: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-7 split control register
+        OTG_HS_HCSPLT7: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-7 interrupt register
+        OTG_HS_HCINT7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-7 interrupt mask register
+        OTG_HS_HCINTMSK7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-7 transfer size register
+        OTG_HS_HCTSIZ7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-7 DMA address register
+        OTG_HS_HCDMA7: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved512: [8]u8,
+        ///  OTG_HS host channel-8 characteristics register
+        OTG_HS_HCCHAR8: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-8 split control register
+        OTG_HS_HCSPLT8: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-8 interrupt register
+        OTG_HS_HCINT8: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-8 interrupt mask register
+        OTG_HS_HCINTMSK8: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-8 transfer size register
+        OTG_HS_HCTSIZ8: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-8 DMA address register
+        OTG_HS_HCDMA8: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved544: [8]u8,
+        ///  OTG_HS host channel-9 characteristics register
+        OTG_HS_HCCHAR9: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-9 split control register
+        OTG_HS_HCSPLT9: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-9 interrupt register
+        OTG_HS_HCINT9: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-9 interrupt mask register
+        OTG_HS_HCINTMSK9: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-9 transfer size register
+        OTG_HS_HCTSIZ9: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-9 DMA address register
+        OTG_HS_HCDMA9: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved576: [8]u8,
+        ///  OTG_HS host channel-10 characteristics register
+        OTG_HS_HCCHAR10: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-10 split control register
+        OTG_HS_HCSPLT10: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-10 interrupt register
+        OTG_HS_HCINT10: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-10 interrupt mask register
+        OTG_HS_HCINTMSK10: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-10 transfer size register
+        OTG_HS_HCTSIZ10: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-10 DMA address register
+        OTG_HS_HCDMA10: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved608: [8]u8,
+        ///  OTG_HS host channel-11 characteristics register
+        OTG_HS_HCCHAR11: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-11 split control register
+        OTG_HS_HCSPLT11: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-11 interrupt register
+        OTG_HS_HCINT11: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-11 interrupt mask register
+        OTG_HS_HCINTMSK11: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-11 transfer size register
+        OTG_HS_HCTSIZ11: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-11 DMA address register
+        OTG_HS_HCDMA11: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+    };
+
+    ///  USB on the go high speed
+    pub const OTG_HS_GLOBAL = extern struct {
+        ///  OTG_HS control and status register
+        OTG_HS_GOTGCTL: mmio.Mmio(packed struct(u32) {
+            ///  Session request success
+            SRQSCS: u1,
+            ///  Session request
+            SRQ: u1,
+            reserved8: u6,
+            ///  Host negotiation success
+            HNGSCS: u1,
+            ///  HNP request
+            HNPRQ: u1,
+            ///  Host set HNP enable
+            HSHNPEN: u1,
+            ///  Device HNP enabled
+            DHNPEN: u1,
+            reserved16: u4,
+            ///  Connector ID status
+            CIDSTS: u1,
+            ///  Long/short debounce time
+            DBCT: u1,
+            ///  A-session valid
+            ASVLD: u1,
+            ///  B-session valid
+            BSVLD: u1,
+            padding: u12,
+        }),
+        ///  OTG_HS interrupt register
+        OTG_HS_GOTGINT: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Session end detected
+            SEDET: u1,
+            reserved8: u5,
+            ///  Session request success status change
+            SRSSCHG: u1,
+            ///  Host negotiation success status change
+            HNSSCHG: u1,
+            reserved17: u7,
+            ///  Host negotiation detected
+            HNGDET: u1,
+            ///  A-device timeout change
+            ADTOCHG: u1,
+            ///  Debounce done
+            DBCDNE: u1,
+            padding: u12,
+        }),
+        ///  OTG_HS AHB configuration register
+        OTG_HS_GAHBCFG: mmio.Mmio(packed struct(u32) {
+            ///  Global interrupt mask
+            GINT: u1,
+            ///  Burst length/type
+            HBSTLEN: u4,
+            ///  DMA enable
+            DMAEN: u1,
+            reserved7: u1,
+            ///  TxFIFO empty level
+            TXFELVL: u1,
+            ///  Periodic TxFIFO empty level
+            PTXFELVL: u1,
+            padding: u23,
+        }),
+        ///  OTG_HS USB configuration register
+        OTG_HS_GUSBCFG: mmio.Mmio(packed struct(u32) {
+            ///  FS timeout calibration
+            TOCAL: u3,
+            reserved6: u3,
+            ///  USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
+            PHYSEL: u1,
+            reserved8: u1,
+            ///  SRP-capable
+            SRPCAP: u1,
+            ///  HNP-capable
+            HNPCAP: u1,
+            ///  USB turnaround time
+            TRDT: u4,
+            reserved15: u1,
+            ///  PHY Low-power clock select
+            PHYLPCS: u1,
+            reserved17: u1,
+            ///  ULPI FS/LS select
+            ULPIFSLS: u1,
+            ///  ULPI Auto-resume
+            ULPIAR: u1,
+            ///  ULPI Clock SuspendM
+            ULPICSM: u1,
+            ///  ULPI External VBUS Drive
+            ULPIEVBUSD: u1,
+            ///  ULPI external VBUS indicator
+            ULPIEVBUSI: u1,
+            ///  TermSel DLine pulsing selection
+            TSDPS: u1,
+            ///  Indicator complement
+            PCCI: u1,
+            ///  Indicator pass through
+            PTCI: u1,
+            ///  ULPI interface protect disable
+            ULPIIPD: u1,
+            reserved29: u3,
+            ///  Forced host mode
+            FHMOD: u1,
+            ///  Forced peripheral mode
+            FDMOD: u1,
+            ///  Corrupt Tx packet
+            CTXPKT: u1,
+        }),
+        ///  OTG_HS reset register
+        OTG_HS_GRSTCTL: mmio.Mmio(packed struct(u32) {
+            ///  Core soft reset
+            CSRST: u1,
+            ///  HCLK soft reset
+            HSRST: u1,
+            ///  Host frame counter reset
+            FCRST: u1,
+            reserved4: u1,
+            ///  RxFIFO flush
+            RXFFLSH: u1,
+            ///  TxFIFO flush
+            TXFFLSH: u1,
+            ///  TxFIFO number
+            TXFNUM: u5,
+            reserved30: u19,
+            ///  DMA request signal
+            DMAREQ: u1,
+            ///  AHB master idle
+            AHBIDL: u1,
+        }),
+        ///  OTG_HS core interrupt register
+        OTG_HS_GINTSTS: mmio.Mmio(packed struct(u32) {
+            ///  Current mode of operation
+            CMOD: u1,
+            ///  Mode mismatch interrupt
+            MMIS: u1,
+            ///  OTG interrupt
+            OTGINT: u1,
+            ///  Start of frame
+            SOF: u1,
+            ///  RxFIFO nonempty
+            RXFLVL: u1,
+            ///  Nonperiodic TxFIFO empty
+            NPTXFE: u1,
+            ///  Global IN nonperiodic NAK effective
+            GINAKEFF: u1,
+            ///  Global OUT NAK effective
+            BOUTNAKEFF: u1,
+            reserved10: u2,
+            ///  Early suspend
+            ESUSP: u1,
+            ///  USB suspend
+            USBSUSP: u1,
+            ///  USB reset
+            USBRST: u1,
+            ///  Enumeration done
+            ENUMDNE: u1,
+            ///  Isochronous OUT packet dropped interrupt
+            ISOODRP: u1,
+            ///  End of periodic frame interrupt
+            EOPF: u1,
+            reserved18: u2,
+            ///  IN endpoint interrupt
+            IEPINT: u1,
+            ///  OUT endpoint interrupt
+            OEPINT: u1,
+            ///  Incomplete isochronous IN transfer
+            IISOIXFR: u1,
+            ///  Incomplete periodic transfer
+            PXFR_INCOMPISOOUT: u1,
+            ///  Data fetch suspended
+            DATAFSUSP: u1,
+            reserved24: u1,
+            ///  Host port interrupt
+            HPRTINT: u1,
+            ///  Host channels interrupt
+            HCINT: u1,
+            ///  Periodic TxFIFO empty
+            PTXFE: u1,
+            reserved28: u1,
+            ///  Connector ID status change
+            CIDSCHG: u1,
+            ///  Disconnect detected interrupt
+            DISCINT: u1,
+            ///  Session request/new session detected interrupt
+            SRQINT: u1,
+            ///  Resume/remote wakeup detected interrupt
+            WKUINT: u1,
+        }),
+        ///  OTG_HS interrupt mask register
+        OTG_HS_GINTMSK: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Mode mismatch interrupt mask
+            MMISM: u1,
+            ///  OTG interrupt mask
+            OTGINT: u1,
+            ///  Start of frame mask
+            SOFM: u1,
+            ///  Receive FIFO nonempty mask
+            RXFLVLM: u1,
+            ///  Nonperiodic TxFIFO empty mask
+            NPTXFEM: u1,
+            ///  Global nonperiodic IN NAK effective mask
+            GINAKEFFM: u1,
+            ///  Global OUT NAK effective mask
+            GONAKEFFM: u1,
+            reserved10: u2,
+            ///  Early suspend mask
+            ESUSPM: u1,
+            ///  USB suspend mask
+            USBSUSPM: u1,
+            ///  USB reset mask
+            USBRST: u1,
+            ///  Enumeration done mask
+            ENUMDNEM: u1,
+            ///  Isochronous OUT packet dropped interrupt mask
+            ISOODRPM: u1,
+            ///  End of periodic frame interrupt mask
+            EOPFM: u1,
+            reserved17: u1,
+            ///  Endpoint mismatch interrupt mask
+            EPMISM: u1,
+            ///  IN endpoints interrupt mask
+            IEPINT: u1,
+            ///  OUT endpoints interrupt mask
+            OEPINT: u1,
+            ///  Incomplete isochronous IN transfer mask
+            IISOIXFRM: u1,
+            ///  Incomplete periodic transfer mask
+            PXFRM_IISOOXFRM: u1,
+            ///  Data fetch suspended mask
+            FSUSPM: u1,
+            reserved24: u1,
+            ///  Host port interrupt mask
+            PRTIM: u1,
+            ///  Host channels interrupt mask
+            HCIM: u1,
+            ///  Periodic TxFIFO empty mask
+            PTXFEM: u1,
+            reserved28: u1,
+            ///  Connector ID status change mask
+            CIDSCHGM: u1,
+            ///  Disconnect detected interrupt mask
+            DISCINT: u1,
+            ///  Session request/new session detected interrupt mask
+            SRQIM: u1,
+            ///  Resume/remote wakeup detected interrupt mask
+            WUIM: u1,
+        }),
+        ///  OTG_HS Receive status debug read register (host mode)
+        OTG_HS_GRXSTSR_Host: mmio.Mmio(packed struct(u32) {
+            ///  Channel number
+            CHNUM: u4,
+            ///  Byte count
+            BCNT: u11,
+            ///  Data PID
+            DPID: u2,
+            ///  Packet status
+            PKTSTS: u4,
+            padding: u11,
+        }),
+        ///  OTG_HS status read and pop register (host mode)
+        OTG_HS_GRXSTSP_Host: mmio.Mmio(packed struct(u32) {
+            ///  Channel number
+            CHNUM: u4,
+            ///  Byte count
+            BCNT: u11,
+            ///  Data PID
+            DPID: u2,
+            ///  Packet status
+            PKTSTS: u4,
+            padding: u11,
+        }),
+        ///  OTG_HS Receive FIFO size register
+        OTG_HS_GRXFSIZ: mmio.Mmio(packed struct(u32) {
+            ///  RxFIFO depth
+            RXFD: u16,
+            padding: u16,
+        }),
+        ///  OTG_HS nonperiodic transmit FIFO size register (host mode)
+        OTG_HS_GNPTXFSIZ_Host: mmio.Mmio(packed struct(u32) {
+            ///  Nonperiodic transmit RAM start address
+            NPTXFSA: u16,
+            ///  Nonperiodic TxFIFO depth
+            NPTXFD: u16,
+        }),
+        ///  OTG_HS nonperiodic transmit FIFO/queue status register
+        OTG_HS_GNPTXSTS: mmio.Mmio(packed struct(u32) {
+            ///  Nonperiodic TxFIFO space available
+            NPTXFSAV: u16,
+            ///  Nonperiodic transmit request queue space available
+            NPTQXSAV: u8,
+            ///  Top of the nonperiodic transmit request queue
+            NPTXQTOP: u7,
+            padding: u1,
+        }),
+        reserved56: [8]u8,
+        ///  OTG_HS general core configuration register
+        OTG_HS_GCCFG: mmio.Mmio(packed struct(u32) {
+            reserved16: u16,
+            ///  Power down
+            PWRDWN: u1,
+            ///  Enable I2C bus connection for the external I2C PHY interface
+            I2CPADEN: u1,
+            ///  Enable the VBUS sensing device
+            VBUSASEN: u1,
+            ///  Enable the VBUS sensing device
+            VBUSBSEN: u1,
+            ///  SOF output enable
+            SOFOUTEN: u1,
+            ///  VBUS sensing disable option
+            NOVBUSSENS: u1,
+            padding: u10,
+        }),
+        ///  OTG_HS core ID register
+        OTG_HS_CID: mmio.Mmio(packed struct(u32) {
+            ///  Product ID field
+            PRODUCT_ID: u32,
+        }),
+        reserved256: [192]u8,
+        ///  OTG_HS Host periodic transmit FIFO size register
+        OTG_HS_HPTXFSIZ: mmio.Mmio(packed struct(u32) {
+            ///  Host periodic TxFIFO start address
+            PTXSA: u16,
+            ///  Host periodic TxFIFO depth
+            PTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF1: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF2: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        reserved284: [16]u8,
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF3: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF4: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF5: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF6: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF7: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+    };
+
+    ///  Secure digital input/output interface
+    pub const SDIO = extern struct {
+        ///  power control register
+        POWER: mmio.Mmio(packed struct(u32) {
+            ///  PWRCTRL
+            PWRCTRL: u2,
+            padding: u30,
+        }),
+        ///  SDI clock control register
+        CLKCR: mmio.Mmio(packed struct(u32) {
+            ///  Clock divide factor
+            CLKDIV: u8,
+            ///  Clock enable bit
+            CLKEN: u1,
+            ///  Power saving configuration bit
+            PWRSAV: u1,
+            ///  Clock divider bypass enable bit
+            BYPASS: u1,
+            ///  Wide bus mode enable bit
+            WIDBUS: u2,
+            ///  SDIO_CK dephasing selection bit
+            NEGEDGE: u1,
+            ///  HW Flow Control enable
+            HWFC_EN: u1,
+            padding: u17,
+        }),
+        ///  argument register
+        ARG: mmio.Mmio(packed struct(u32) {
+            ///  Command argument
+            CMDARG: u32,
+        }),
+        ///  command register
+        CMD: mmio.Mmio(packed struct(u32) {
+            ///  Command index
+            CMDINDEX: u6,
+            ///  Wait for response bits
+            WAITRESP: u2,
+            ///  CPSM waits for interrupt request
+            WAITINT: u1,
+            ///  CPSM Waits for ends of data transfer (CmdPend internal signal).
+            WAITPEND: u1,
+            ///  Command path state machine (CPSM) Enable bit
+            CPSMEN: u1,
+            ///  SD I/O suspend command
+            SDIOSuspend: u1,
+            ///  Enable CMD completion
+            ENCMDcompl: u1,
+            ///  not Interrupt Enable
+            nIEN: u1,
+            ///  CE-ATA command
+            CE_ATACMD: u1,
+            padding: u17,
+        }),
+        ///  command response register
+        RESPCMD: mmio.Mmio(packed struct(u32) {
+            ///  Response command index
+            RESPCMD: u6,
+            padding: u26,
+        }),
+        ///  response 1..4 register
+        RESP1: mmio.Mmio(packed struct(u32) {
+            ///  see Table 132.
+            CARDSTATUS1: u32,
+        }),
+        ///  response 1..4 register
+        RESP2: mmio.Mmio(packed struct(u32) {
+            ///  see Table 132.
+            CARDSTATUS2: u32,
+        }),
+        ///  response 1..4 register
+        RESP3: mmio.Mmio(packed struct(u32) {
+            ///  see Table 132.
+            CARDSTATUS3: u32,
+        }),
+        ///  response 1..4 register
+        RESP4: mmio.Mmio(packed struct(u32) {
+            ///  see Table 132.
+            CARDSTATUS4: u32,
+        }),
+        ///  data timer register
+        DTIMER: mmio.Mmio(packed struct(u32) {
+            ///  Data timeout period
+            DATATIME: u32,
+        }),
+        ///  data length register
+        DLEN: mmio.Mmio(packed struct(u32) {
+            ///  Data length value
+            DATALENGTH: u25,
+            padding: u7,
+        }),
+        ///  data control register
+        DCTRL: mmio.Mmio(packed struct(u32) {
+            ///  DTEN
+            DTEN: u1,
+            ///  Data transfer direction selection
+            DTDIR: u1,
+            ///  Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
+            DTMODE: u1,
+            ///  DMA enable bit
+            DMAEN: u1,
+            ///  Data block size
+            DBLOCKSIZE: u4,
+            ///  Read wait start
+            RWSTART: u1,
+            ///  Read wait stop
+            RWSTOP: u1,
+            ///  Read wait mode
+            RWMOD: u1,
+            ///  SD I/O enable functions
+            SDIOEN: u1,
+            padding: u20,
+        }),
+        ///  data counter register
+        DCOUNT: mmio.Mmio(packed struct(u32) {
+            ///  Data count value
+            DATACOUNT: u25,
+            padding: u7,
+        }),
+        ///  status register
+        STA: mmio.Mmio(packed struct(u32) {
+            ///  Command response received (CRC check failed)
+            CCRCFAIL: u1,
+            ///  Data block sent/received (CRC check failed)
+            DCRCFAIL: u1,
+            ///  Command response timeout
+            CTIMEOUT: u1,
+            ///  Data timeout
+            DTIMEOUT: u1,
+            ///  Transmit FIFO underrun error
+            TXUNDERR: u1,
+            ///  Received FIFO overrun error
+            RXOVERR: u1,
+            ///  Command response received (CRC check passed)
+            CMDREND: u1,
+            ///  Command sent (no response required)
+            CMDSENT: u1,
+            ///  Data end (data counter, SDIDCOUNT, is zero)
+            DATAEND: u1,
+            ///  Start bit not detected on all data signals in wide bus mode
+            STBITERR: u1,
+            ///  Data block sent/received (CRC check passed)
+            DBCKEND: u1,
+            ///  Command transfer in progress
+            CMDACT: u1,
+            ///  Data transmit in progress
+            TXACT: u1,
+            ///  Data receive in progress
+            RXACT: u1,
+            ///  Transmit FIFO half empty: at least 8 words can be written into the FIFO
+            TXFIFOHE: u1,
+            ///  Receive FIFO half full: there are at least 8 words in the FIFO
+            RXFIFOHF: u1,
+            ///  Transmit FIFO full
+            TXFIFOF: u1,
+            ///  Receive FIFO full
+            RXFIFOF: u1,
+            ///  Transmit FIFO empty
+            TXFIFOE: u1,
+            ///  Receive FIFO empty
+            RXFIFOE: u1,
+            ///  Data available in transmit FIFO
+            TXDAVL: u1,
+            ///  Data available in receive FIFO
+            RXDAVL: u1,
+            ///  SDIO interrupt received
+            SDIOIT: u1,
+            ///  CE-ATA command completion signal received for CMD61
+            CEATAEND: u1,
+            padding: u8,
+        }),
+        ///  interrupt clear register
+        ICR: mmio.Mmio(packed struct(u32) {
+            ///  CCRCFAIL flag clear bit
+            CCRCFAILC: u1,
+            ///  DCRCFAIL flag clear bit
+            DCRCFAILC: u1,
+            ///  CTIMEOUT flag clear bit
+            CTIMEOUTC: u1,
+            ///  DTIMEOUT flag clear bit
+            DTIMEOUTC: u1,
+            ///  TXUNDERR flag clear bit
+            TXUNDERRC: u1,
+            ///  RXOVERR flag clear bit
+            RXOVERRC: u1,
+            ///  CMDREND flag clear bit
+            CMDRENDC: u1,
+            ///  CMDSENT flag clear bit
+            CMDSENTC: u1,
+            ///  DATAEND flag clear bit
+            DATAENDC: u1,
+            ///  STBITERR flag clear bit
+            STBITERRC: u1,
+            ///  DBCKEND flag clear bit
+            DBCKENDC: u1,
+            reserved22: u11,
+            ///  SDIOIT flag clear bit
+            SDIOITC: u1,
+            ///  CEATAEND flag clear bit
+            CEATAENDC: u1,
+            padding: u8,
+        }),
+        ///  mask register
+        MASK: mmio.Mmio(packed struct(u32) {
+            ///  Command CRC fail interrupt enable
+            CCRCFAILIE: u1,
+            ///  Data CRC fail interrupt enable
+            DCRCFAILIE: u1,
+            ///  Command timeout interrupt enable
+            CTIMEOUTIE: u1,
+            ///  Data timeout interrupt enable
+            DTIMEOUTIE: u1,
+            ///  Tx FIFO underrun error interrupt enable
+            TXUNDERRIE: u1,
+            ///  Rx FIFO overrun error interrupt enable
+            RXOVERRIE: u1,
+            ///  Command response received interrupt enable
+            CMDRENDIE: u1,
+            ///  Command sent interrupt enable
+            CMDSENTIE: u1,
+            ///  Data end interrupt enable
+            DATAENDIE: u1,
+            ///  Start bit error interrupt enable
+            STBITERRIE: u1,
+            ///  Data block end interrupt enable
+            DBCKENDIE: u1,
+            ///  Command acting interrupt enable
+            CMDACTIE: u1,
+            ///  Data transmit acting interrupt enable
+            TXACTIE: u1,
+            ///  Data receive acting interrupt enable
+            RXACTIE: u1,
+            ///  Tx FIFO half empty interrupt enable
+            TXFIFOHEIE: u1,
+            ///  Rx FIFO half full interrupt enable
+            RXFIFOHFIE: u1,
+            ///  Tx FIFO full interrupt enable
+            TXFIFOFIE: u1,
+            ///  Rx FIFO full interrupt enable
+            RXFIFOFIE: u1,
+            ///  Tx FIFO empty interrupt enable
+            TXFIFOEIE: u1,
+            ///  Rx FIFO empty interrupt enable
+            RXFIFOEIE: u1,
+            ///  Data available in Tx FIFO interrupt enable
+            TXDAVLIE: u1,
+            ///  Data available in Rx FIFO interrupt enable
+            RXDAVLIE: u1,
+            ///  SDIO mode interrupt received interrupt enable
+            SDIOITIE: u1,
+            ///  CE-ATA command completion signal received interrupt enable
+            CEATAENDIE: u1,
+            padding: u8,
+        }),
+        reserved72: [8]u8,
+        ///  FIFO counter register
+        FIFOCNT: mmio.Mmio(packed struct(u32) {
+            ///  Remaining number of words to be written to or read from the FIFO.
+            FIFOCOUNT: u24,
+            padding: u8,
+        }),
+        reserved128: [52]u8,
+        ///  data FIFO register
+        FIFO: mmio.Mmio(packed struct(u32) {
+            ///  Receive and transmit FIFO data
+            FIFOData: u32,
+        }),
+    };
+
+    ///  Analog-to-digital converter
+    pub const ADC1 = extern struct {
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog flag
+            AWD: u1,
+            ///  Regular channel end of conversion
+            EOC: u1,
+            ///  Injected channel end of conversion
+            JEOC: u1,
+            ///  Injected channel start flag
+            JSTRT: u1,
+            ///  Regular channel start flag
+            STRT: u1,
+            ///  Overrun
+            OVR: u1,
+            padding: u26,
+        }),
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog channel select bits
+            AWDCH: u5,
+            ///  Interrupt enable for EOC
+            EOCIE: u1,
+            ///  Analog watchdog interrupt enable
+            AWDIE: u1,
+            ///  Interrupt enable for injected channels
+            JEOCIE: u1,
+            ///  Scan mode
+            SCAN: u1,
+            ///  Enable the watchdog on a single channel in scan mode
+            AWDSGL: u1,
+            ///  Automatic injected group conversion
+            JAUTO: u1,
+            ///  Discontinuous mode on regular channels
+            DISCEN: u1,
+            ///  Discontinuous mode on injected channels
+            JDISCEN: u1,
+            ///  Discontinuous mode channel count
+            DISCNUM: u3,
+            reserved22: u6,
+            ///  Analog watchdog enable on injected channels
+            JAWDEN: u1,
+            ///  Analog watchdog enable on regular channels
+            AWDEN: u1,
+            ///  Resolution
+            RES: u2,
+            ///  Overrun interrupt enable
+            OVRIE: u1,
+            padding: u5,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  A/D Converter ON / OFF
+            ADON: u1,
+            ///  Continuous conversion
+            CONT: u1,
+            reserved8: u6,
+            ///  Direct memory access mode (for single ADC mode)
+            DMA: u1,
+            ///  DMA disable selection (for single ADC mode)
+            DDS: u1,
+            ///  End of conversion selection
+            EOCS: u1,
+            ///  Data alignment
+            ALIGN: u1,
+            reserved16: u4,
+            ///  External event select for injected group
+            JEXTSEL: u4,
+            ///  External trigger enable for injected channels
+            JEXTEN: u2,
+            ///  Start conversion of injected channels
+            JSWSTART: u1,
+            reserved24: u1,
+            ///  External event select for regular group
+            EXTSEL: u4,
+            ///  External trigger enable for regular channels
+            EXTEN: u2,
+            ///  Start conversion of regular channels
+            SWSTART: u1,
+            padding: u1,
+        }),
+        ///  sample time register 1
+        SMPR1: mmio.Mmio(packed struct(u32) {
+            ///  Sample time bits
+            SMPx_x: u32,
+        }),
+        ///  sample time register 2
+        SMPR2: mmio.Mmio(packed struct(u32) {
+            ///  Sample time bits
+            SMPx_x: u32,
+        }),
+        ///  injected channel data offset register x
+        JOFR1: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET1: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR2: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET2: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR3: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET3: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR4: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET4: u12,
+            padding: u20,
+        }),
+        ///  watchdog higher threshold register
+        HTR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog higher threshold
+            HT: u12,
+            padding: u20,
+        }),
+        ///  watchdog lower threshold register
+        LTR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog lower threshold
+            LT: u12,
+            padding: u20,
+        }),
+        ///  regular sequence register 1
+        SQR1: mmio.Mmio(packed struct(u32) {
+            ///  13th conversion in regular sequence
+            SQ13: u5,
+            ///  14th conversion in regular sequence
+            SQ14: u5,
+            ///  15th conversion in regular sequence
+            SQ15: u5,
+            ///  16th conversion in regular sequence
+            SQ16: u5,
+            ///  Regular channel sequence length
+            L: u4,
+            padding: u8,
+        }),
+        ///  regular sequence register 2
+        SQR2: mmio.Mmio(packed struct(u32) {
+            ///  7th conversion in regular sequence
+            SQ7: u5,
+            ///  8th conversion in regular sequence
+            SQ8: u5,
+            ///  9th conversion in regular sequence
+            SQ9: u5,
+            ///  10th conversion in regular sequence
+            SQ10: u5,
+            ///  11th conversion in regular sequence
+            SQ11: u5,
+            ///  12th conversion in regular sequence
+            SQ12: u5,
+            padding: u2,
+        }),
+        ///  regular sequence register 3
+        SQR3: mmio.Mmio(packed struct(u32) {
+            ///  1st conversion in regular sequence
+            SQ1: u5,
+            ///  2nd conversion in regular sequence
+            SQ2: u5,
+            ///  3rd conversion in regular sequence
+            SQ3: u5,
+            ///  4th conversion in regular sequence
+            SQ4: u5,
+            ///  5th conversion in regular sequence
+            SQ5: u5,
+            ///  6th conversion in regular sequence
+            SQ6: u5,
+            padding: u2,
+        }),
+        ///  injected sequence register
+        JSQR: mmio.Mmio(packed struct(u32) {
+            ///  1st conversion in injected sequence
+            JSQ1: u5,
+            ///  2nd conversion in injected sequence
+            JSQ2: u5,
+            ///  3rd conversion in injected sequence
+            JSQ3: u5,
+            ///  4th conversion in injected sequence
+            JSQ4: u5,
+            ///  Injected sequence length
+            JL: u2,
+            padding: u10,
+        }),
+        ///  injected data register x
+        JDR1: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR2: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR3: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR4: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  regular data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Regular data
+            DATA: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  External interrupt/event controller
+    pub const EXTI = extern struct {
+        ///  Interrupt mask register (EXTI_IMR)
+        IMR: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt Mask on line 0
+            MR0: u1,
+            ///  Interrupt Mask on line 1
+            MR1: u1,
+            ///  Interrupt Mask on line 2
+            MR2: u1,
+            ///  Interrupt Mask on line 3
+            MR3: u1,
+            ///  Interrupt Mask on line 4
+            MR4: u1,
+            ///  Interrupt Mask on line 5
+            MR5: u1,
+            ///  Interrupt Mask on line 6
+            MR6: u1,
+            ///  Interrupt Mask on line 7
+            MR7: u1,
+            ///  Interrupt Mask on line 8
+            MR8: u1,
+            ///  Interrupt Mask on line 9
+            MR9: u1,
+            ///  Interrupt Mask on line 10
+            MR10: u1,
+            ///  Interrupt Mask on line 11
+            MR11: u1,
+            ///  Interrupt Mask on line 12
+            MR12: u1,
+            ///  Interrupt Mask on line 13
+            MR13: u1,
+            ///  Interrupt Mask on line 14
+            MR14: u1,
+            ///  Interrupt Mask on line 15
+            MR15: u1,
+            ///  Interrupt Mask on line 16
+            MR16: u1,
+            ///  Interrupt Mask on line 17
+            MR17: u1,
+            ///  Interrupt Mask on line 18
+            MR18: u1,
+            ///  Interrupt Mask on line 19
+            MR19: u1,
+            ///  Interrupt Mask on line 20
+            MR20: u1,
+            ///  Interrupt Mask on line 21
+            MR21: u1,
+            ///  Interrupt Mask on line 22
+            MR22: u1,
+            padding: u9,
+        }),
+        ///  Event mask register (EXTI_EMR)
+        EMR: mmio.Mmio(packed struct(u32) {
+            ///  Event Mask on line 0
+            MR0: u1,
+            ///  Event Mask on line 1
+            MR1: u1,
+            ///  Event Mask on line 2
+            MR2: u1,
+            ///  Event Mask on line 3
+            MR3: u1,
+            ///  Event Mask on line 4
+            MR4: u1,
+            ///  Event Mask on line 5
+            MR5: u1,
+            ///  Event Mask on line 6
+            MR6: u1,
+            ///  Event Mask on line 7
+            MR7: u1,
+            ///  Event Mask on line 8
+            MR8: u1,
+            ///  Event Mask on line 9
+            MR9: u1,
+            ///  Event Mask on line 10
+            MR10: u1,
+            ///  Event Mask on line 11
+            MR11: u1,
+            ///  Event Mask on line 12
+            MR12: u1,
+            ///  Event Mask on line 13
+            MR13: u1,
+            ///  Event Mask on line 14
+            MR14: u1,
+            ///  Event Mask on line 15
+            MR15: u1,
+            ///  Event Mask on line 16
+            MR16: u1,
+            ///  Event Mask on line 17
+            MR17: u1,
+            ///  Event Mask on line 18
+            MR18: u1,
+            ///  Event Mask on line 19
+            MR19: u1,
+            ///  Event Mask on line 20
+            MR20: u1,
+            ///  Event Mask on line 21
+            MR21: u1,
+            ///  Event Mask on line 22
+            MR22: u1,
+            padding: u9,
+        }),
+        ///  Rising Trigger selection register (EXTI_RTSR)
+        RTSR: mmio.Mmio(packed struct(u32) {
+            ///  Rising trigger event configuration of line 0
+            TR0: u1,
+            ///  Rising trigger event configuration of line 1
+            TR1: u1,
+            ///  Rising trigger event configuration of line 2
+            TR2: u1,
+            ///  Rising trigger event configuration of line 3
+            TR3: u1,
+            ///  Rising trigger event configuration of line 4
+            TR4: u1,
+            ///  Rising trigger event configuration of line 5
+            TR5: u1,
+            ///  Rising trigger event configuration of line 6
+            TR6: u1,
+            ///  Rising trigger event configuration of line 7
+            TR7: u1,
+            ///  Rising trigger event configuration of line 8
+            TR8: u1,
+            ///  Rising trigger event configuration of line 9
+            TR9: u1,
+            ///  Rising trigger event configuration of line 10
+            TR10: u1,
+            ///  Rising trigger event configuration of line 11
+            TR11: u1,
+            ///  Rising trigger event configuration of line 12
+            TR12: u1,
+            ///  Rising trigger event configuration of line 13
+            TR13: u1,
+            ///  Rising trigger event configuration of line 14
+            TR14: u1,
+            ///  Rising trigger event configuration of line 15
+            TR15: u1,
+            ///  Rising trigger event configuration of line 16
+            TR16: u1,
+            ///  Rising trigger event configuration of line 17
+            TR17: u1,
+            ///  Rising trigger event configuration of line 18
+            TR18: u1,
+            ///  Rising trigger event configuration of line 19
+            TR19: u1,
+            ///  Rising trigger event configuration of line 20
+            TR20: u1,
+            ///  Rising trigger event configuration of line 21
+            TR21: u1,
+            ///  Rising trigger event configuration of line 22
+            TR22: u1,
+            padding: u9,
+        }),
+        ///  Falling Trigger selection register (EXTI_FTSR)
+        FTSR: mmio.Mmio(packed struct(u32) {
+            ///  Falling trigger event configuration of line 0
+            TR0: u1,
+            ///  Falling trigger event configuration of line 1
+            TR1: u1,
+            ///  Falling trigger event configuration of line 2
+            TR2: u1,
+            ///  Falling trigger event configuration of line 3
+            TR3: u1,
+            ///  Falling trigger event configuration of line 4
+            TR4: u1,
+            ///  Falling trigger event configuration of line 5
+            TR5: u1,
+            ///  Falling trigger event configuration of line 6
+            TR6: u1,
+            ///  Falling trigger event configuration of line 7
+            TR7: u1,
+            ///  Falling trigger event configuration of line 8
+            TR8: u1,
+            ///  Falling trigger event configuration of line 9
+            TR9: u1,
+            ///  Falling trigger event configuration of line 10
+            TR10: u1,
+            ///  Falling trigger event configuration of line 11
+            TR11: u1,
+            ///  Falling trigger event configuration of line 12
+            TR12: u1,
+            ///  Falling trigger event configuration of line 13
+            TR13: u1,
+            ///  Falling trigger event configuration of line 14
+            TR14: u1,
+            ///  Falling trigger event configuration of line 15
+            TR15: u1,
+            ///  Falling trigger event configuration of line 16
+            TR16: u1,
+            ///  Falling trigger event configuration of line 17
+            TR17: u1,
+            ///  Falling trigger event configuration of line 18
+            TR18: u1,
+            ///  Falling trigger event configuration of line 19
+            TR19: u1,
+            ///  Falling trigger event configuration of line 20
+            TR20: u1,
+            ///  Falling trigger event configuration of line 21
+            TR21: u1,
+            ///  Falling trigger event configuration of line 22
+            TR22: u1,
+            padding: u9,
+        }),
+        ///  Software interrupt event register (EXTI_SWIER)
+        SWIER: mmio.Mmio(packed struct(u32) {
+            ///  Software Interrupt on line 0
+            SWIER0: u1,
+            ///  Software Interrupt on line 1
+            SWIER1: u1,
+            ///  Software Interrupt on line 2
+            SWIER2: u1,
+            ///  Software Interrupt on line 3
+            SWIER3: u1,
+            ///  Software Interrupt on line 4
+            SWIER4: u1,
+            ///  Software Interrupt on line 5
+            SWIER5: u1,
+            ///  Software Interrupt on line 6
+            SWIER6: u1,
+            ///  Software Interrupt on line 7
+            SWIER7: u1,
+            ///  Software Interrupt on line 8
+            SWIER8: u1,
+            ///  Software Interrupt on line 9
+            SWIER9: u1,
+            ///  Software Interrupt on line 10
+            SWIER10: u1,
+            ///  Software Interrupt on line 11
+            SWIER11: u1,
+            ///  Software Interrupt on line 12
+            SWIER12: u1,
+            ///  Software Interrupt on line 13
+            SWIER13: u1,
+            ///  Software Interrupt on line 14
+            SWIER14: u1,
+            ///  Software Interrupt on line 15
+            SWIER15: u1,
+            ///  Software Interrupt on line 16
+            SWIER16: u1,
+            ///  Software Interrupt on line 17
+            SWIER17: u1,
+            ///  Software Interrupt on line 18
+            SWIER18: u1,
+            ///  Software Interrupt on line 19
+            SWIER19: u1,
+            ///  Software Interrupt on line 20
+            SWIER20: u1,
+            ///  Software Interrupt on line 21
+            SWIER21: u1,
+            ///  Software Interrupt on line 22
+            SWIER22: u1,
+            padding: u9,
+        }),
+        ///  Pending register (EXTI_PR)
+        PR: mmio.Mmio(packed struct(u32) {
+            ///  Pending bit 0
+            PR0: u1,
+            ///  Pending bit 1
+            PR1: u1,
+            ///  Pending bit 2
+            PR2: u1,
+            ///  Pending bit 3
+            PR3: u1,
+            ///  Pending bit 4
+            PR4: u1,
+            ///  Pending bit 5
+            PR5: u1,
+            ///  Pending bit 6
+            PR6: u1,
+            ///  Pending bit 7
+            PR7: u1,
+            ///  Pending bit 8
+            PR8: u1,
+            ///  Pending bit 9
+            PR9: u1,
+            ///  Pending bit 10
+            PR10: u1,
+            ///  Pending bit 11
+            PR11: u1,
+            ///  Pending bit 12
+            PR12: u1,
+            ///  Pending bit 13
+            PR13: u1,
+            ///  Pending bit 14
+            PR14: u1,
+            ///  Pending bit 15
+            PR15: u1,
+            ///  Pending bit 16
+            PR16: u1,
+            ///  Pending bit 17
+            PR17: u1,
+            ///  Pending bit 18
+            PR18: u1,
+            ///  Pending bit 19
+            PR19: u1,
+            ///  Pending bit 20
+            PR20: u1,
+            ///  Pending bit 21
+            PR21: u1,
+            ///  Pending bit 22
+            PR22: u1,
+            padding: u9,
+        }),
+    };
+
+    ///  FLASH
+    pub const FLASH = extern struct {
+        ///  Flash access control register
+        ACR: mmio.Mmio(packed struct(u32) {
+            ///  Latency
+            LATENCY: u3,
+            reserved8: u5,
+            ///  Prefetch enable
+            PRFTEN: u1,
+            ///  Instruction cache enable
+            ICEN: u1,
+            ///  Data cache enable
+            DCEN: u1,
+            ///  Instruction cache reset
+            ICRST: u1,
+            ///  Data cache reset
+            DCRST: u1,
+            padding: u19,
+        }),
+        ///  Flash key register
+        KEYR: mmio.Mmio(packed struct(u32) {
+            ///  FPEC key
+            KEY: u32,
+        }),
+        ///  Flash option key register
+        OPTKEYR: mmio.Mmio(packed struct(u32) {
+            ///  Option byte key
+            OPTKEY: u32,
+        }),
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  End of operation
+            EOP: u1,
+            ///  Operation error
+            OPERR: u1,
+            reserved4: u2,
+            ///  Write protection error
+            WRPERR: u1,
+            ///  Programming alignment error
+            PGAERR: u1,
+            ///  Programming parallelism error
+            PGPERR: u1,
+            ///  Programming sequence error
+            PGSERR: u1,
+            reserved16: u8,
+            ///  Busy
+            BSY: u1,
+            padding: u15,
+        }),
+        ///  Control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Programming
+            PG: u1,
+            ///  Sector Erase
+            SER: u1,
+            ///  Mass Erase
+            MER: u1,
+            ///  Sector number
+            SNB: u4,
+            reserved8: u1,
+            ///  Program size
+            PSIZE: u2,
+            reserved16: u6,
+            ///  Start
+            STRT: u1,
+            reserved24: u7,
+            ///  End of operation interrupt enable
+            EOPIE: u1,
+            ///  Error interrupt enable
+            ERRIE: u1,
+            reserved31: u5,
+            ///  Lock
+            LOCK: u1,
+        }),
+        ///  Flash option control register
+        OPTCR: mmio.Mmio(packed struct(u32) {
+            ///  Option lock
+            OPTLOCK: u1,
+            ///  Option start
+            OPTSTRT: u1,
+            ///  BOR reset Level
+            BOR_LEV: u2,
+            reserved5: u1,
+            ///  WDG_SW User option bytes
+            WDG_SW: u1,
+            ///  nRST_STOP User option bytes
+            nRST_STOP: u1,
+            ///  nRST_STDBY User option bytes
+            nRST_STDBY: u1,
+            ///  Read protect
+            RDP: u8,
+            ///  Not write protect
+            nWRP: u12,
+            padding: u4,
+        }),
+    };
+
+    ///  Universal synchronous asynchronous receiver transmitter
+    pub const USART6 = extern struct {
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Parity error
+            PE: u1,
+            ///  Framing error
+            FE: u1,
+            ///  Noise detected flag
+            NF: u1,
+            ///  Overrun error
+            ORE: u1,
+            ///  IDLE line detected
+            IDLE: u1,
+            ///  Read data register not empty
+            RXNE: u1,
+            ///  Transmission complete
+            TC: u1,
+            ///  Transmit data register empty
+            TXE: u1,
+            ///  LIN break detection flag
+            LBD: u1,
+            ///  CTS flag
+            CTS: u1,
+            padding: u22,
+        }),
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data value
+            DR: u9,
+            padding: u23,
+        }),
+        ///  Baud rate register
+        BRR: mmio.Mmio(packed struct(u32) {
+            ///  fraction of USARTDIV
+            DIV_Fraction: u4,
+            ///  mantissa of USARTDIV
+            DIV_Mantissa: u12,
+            padding: u16,
+        }),
+        ///  Control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Send break
+            SBK: u1,
+            ///  Receiver wakeup
+            RWU: u1,
+            ///  Receiver enable
+            RE: u1,
+            ///  Transmitter enable
+            TE: u1,
+            ///  IDLE interrupt enable
+            IDLEIE: u1,
+            ///  RXNE interrupt enable
+            RXNEIE: u1,
+            ///  Transmission complete interrupt enable
+            TCIE: u1,
+            ///  TXE interrupt enable
+            TXEIE: u1,
+            ///  PE interrupt enable
+            PEIE: u1,
+            ///  Parity selection
+            PS: u1,
+            ///  Parity control enable
+            PCE: u1,
+            ///  Wakeup method
+            WAKE: u1,
+            ///  Word length
+            M: u1,
+            ///  USART enable
+            UE: u1,
+            reserved15: u1,
+            ///  Oversampling mode
+            OVER8: u1,
+            padding: u16,
+        }),
+        ///  Control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Address of the USART node
+            ADD: u4,
+            reserved5: u1,
+            ///  lin break detection length
+            LBDL: u1,
+            ///  LIN break detection interrupt enable
+            LBDIE: u1,
+            reserved8: u1,
+            ///  Last bit clock pulse
+            LBCL: u1,
+            ///  Clock phase
+            CPHA: u1,
+            ///  Clock polarity
+            CPOL: u1,
+            ///  Clock enable
+            CLKEN: u1,
+            ///  STOP bits
+            STOP: u2,
+            ///  LIN mode enable
+            LINEN: u1,
+            padding: u17,
+        }),
+        ///  Control register 3
+        CR3: mmio.Mmio(packed struct(u32) {
+            ///  Error interrupt enable
+            EIE: u1,
+            ///  IrDA mode enable
+            IREN: u1,
+            ///  IrDA low-power
+            IRLP: u1,
+            ///  Half-duplex selection
+            HDSEL: u1,
+            ///  Smartcard NACK enable
+            NACK: u1,
+            ///  Smartcard mode enable
+            SCEN: u1,
+            ///  DMA enable receiver
+            DMAR: u1,
+            ///  DMA enable transmitter
+            DMAT: u1,
+            ///  RTS enable
+            RTSE: u1,
+            ///  CTS enable
+            CTSE: u1,
+            ///  CTS interrupt enable
+            CTSIE: u1,
+            ///  One sample bit method enable
+            ONEBIT: u1,
+            padding: u20,
+        }),
+        ///  Guard time and prescaler register
+        GTPR: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u8,
+            ///  Guard time value
+            GT: u8,
+            padding: u16,
+        }),
+    };
+
+    ///  Basic timers
+    pub const TIM6 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            reserved7: u3,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            padding: u24,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  Master mode selection
+            MMS: u3,
+            padding: u25,
+        }),
+        reserved12: [4]u8,
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            reserved8: u7,
+            ///  Update DMA request enable
+            UDE: u1,
+            padding: u23,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            padding: u31,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            padding: u31,
+        }),
+        reserved36: [12]u8,
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  Low counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Low Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Controller area network
+    pub const CAN1 = extern struct {
+        ///  master control register
+        MCR: mmio.Mmio(packed struct(u32) {
+            ///  INRQ
+            INRQ: u1,
+            ///  SLEEP
+            SLEEP: u1,
+            ///  TXFP
+            TXFP: u1,
+            ///  RFLM
+            RFLM: u1,
+            ///  NART
+            NART: u1,
+            ///  AWUM
+            AWUM: u1,
+            ///  ABOM
+            ABOM: u1,
+            ///  TTCM
+            TTCM: u1,
+            reserved15: u7,
+            ///  RESET
+            RESET: u1,
+            ///  DBF
+            DBF: u1,
+            padding: u15,
+        }),
+        ///  master status register
+        MSR: mmio.Mmio(packed struct(u32) {
+            ///  INAK
+            INAK: u1,
+            ///  SLAK
+            SLAK: u1,
+            ///  ERRI
+            ERRI: u1,
+            ///  WKUI
+            WKUI: u1,
+            ///  SLAKI
+            SLAKI: u1,
+            reserved8: u3,
+            ///  TXM
+            TXM: u1,
+            ///  RXM
+            RXM: u1,
+            ///  SAMP
+            SAMP: u1,
+            ///  RX
+            RX: u1,
+            padding: u20,
+        }),
+        ///  transmit status register
+        TSR: mmio.Mmio(packed struct(u32) {
+            ///  RQCP0
+            RQCP0: u1,
+            ///  TXOK0
+            TXOK0: u1,
+            ///  ALST0
+            ALST0: u1,
+            ///  TERR0
+            TERR0: u1,
+            reserved7: u3,
+            ///  ABRQ0
+            ABRQ0: u1,
+            ///  RQCP1
+            RQCP1: u1,
+            ///  TXOK1
+            TXOK1: u1,
+            ///  ALST1
+            ALST1: u1,
+            ///  TERR1
+            TERR1: u1,
+            reserved15: u3,
+            ///  ABRQ1
+            ABRQ1: u1,
+            ///  RQCP2
+            RQCP2: u1,
+            ///  TXOK2
+            TXOK2: u1,
+            ///  ALST2
+            ALST2: u1,
+            ///  TERR2
+            TERR2: u1,
+            reserved23: u3,
+            ///  ABRQ2
+            ABRQ2: u1,
+            ///  CODE
+            CODE: u2,
+            ///  Lowest priority flag for mailbox 0
+            TME0: u1,
+            ///  Lowest priority flag for mailbox 1
+            TME1: u1,
+            ///  Lowest priority flag for mailbox 2
+            TME2: u1,
+            ///  Lowest priority flag for mailbox 0
+            LOW0: u1,
+            ///  Lowest priority flag for mailbox 1
+            LOW1: u1,
+            ///  Lowest priority flag for mailbox 2
+            LOW2: u1,
+        }),
+        ///  receive FIFO 0 register
+        RF0R: mmio.Mmio(packed struct(u32) {
+            ///  FMP0
+            FMP0: u2,
+            reserved3: u1,
+            ///  FULL0
+            FULL0: u1,
+            ///  FOVR0
+            FOVR0: u1,
+            ///  RFOM0
+            RFOM0: u1,
+            padding: u26,
+        }),
+        ///  receive FIFO 1 register
+        RF1R: mmio.Mmio(packed struct(u32) {
+            ///  FMP1
+            FMP1: u2,
+            reserved3: u1,
+            ///  FULL1
+            FULL1: u1,
+            ///  FOVR1
+            FOVR1: u1,
+            ///  RFOM1
+            RFOM1: u1,
+            padding: u26,
+        }),
+        ///  interrupt enable register
+        IER: mmio.Mmio(packed struct(u32) {
+            ///  TMEIE
+            TMEIE: u1,
+            ///  FMPIE0
+            FMPIE0: u1,
+            ///  FFIE0
+            FFIE0: u1,
+            ///  FOVIE0
+            FOVIE0: u1,
+            ///  FMPIE1
+            FMPIE1: u1,
+            ///  FFIE1
+            FFIE1: u1,
+            ///  FOVIE1
+            FOVIE1: u1,
+            reserved8: u1,
+            ///  EWGIE
+            EWGIE: u1,
+            ///  EPVIE
+            EPVIE: u1,
+            ///  BOFIE
+            BOFIE: u1,
+            ///  LECIE
+            LECIE: u1,
+            reserved15: u3,
+            ///  ERRIE
+            ERRIE: u1,
+            ///  WKUIE
+            WKUIE: u1,
+            ///  SLKIE
+            SLKIE: u1,
+            padding: u14,
+        }),
+        ///  interrupt enable register
+        ESR: mmio.Mmio(packed struct(u32) {
+            ///  EWGF
+            EWGF: u1,
+            ///  EPVF
+            EPVF: u1,
+            ///  BOFF
+            BOFF: u1,
+            reserved4: u1,
+            ///  LEC
+            LEC: u3,
+            reserved16: u9,
+            ///  TEC
+            TEC: u8,
+            ///  REC
+            REC: u8,
+        }),
+        ///  bit timing register
+        BTR: mmio.Mmio(packed struct(u32) {
+            ///  BRP
+            BRP: u10,
+            reserved16: u6,
+            ///  TS1
+            TS1: u4,
+            ///  TS2
+            TS2: u3,
+            reserved24: u1,
+            ///  SJW
+            SJW: u2,
+            reserved30: u4,
+            ///  LBKM
+            LBKM: u1,
+            ///  SILM
+            SILM: u1,
+        }),
+        reserved384: [352]u8,
+        ///  TX mailbox identifier register
+        TI0R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data length control and time stamp register
+        TDT0R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data low register
+        TDL0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  mailbox data high register
+        TDH0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  mailbox identifier register
+        TI1R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data length control and time stamp register
+        TDT1R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data low register
+        TDL1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  mailbox data high register
+        TDH1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  mailbox identifier register
+        TI2R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data length control and time stamp register
+        TDT2R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data low register
+        TDL2R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  mailbox data high register
+        TDH2R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  receive FIFO mailbox identifier register
+        RI0R: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data high register
+        RDT0R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  FMI
+            FMI: u8,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data high register
+        RDL0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  receive FIFO mailbox data high register
+        RDH0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  mailbox data high register
+        RI1R: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data high register
+        RDT1R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  FMI
+            FMI: u8,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data high register
+        RDL1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  mailbox data high register
+        RDH1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        reserved512: [48]u8,
+        ///  filter master register
+        FMR: mmio.Mmio(packed struct(u32) {
+            ///  FINIT
+            FINIT: u1,
+            reserved8: u7,
+            ///  CAN2SB
+            CAN2SB: u6,
+            padding: u18,
+        }),
+        ///  filter mode register
+        FM1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter mode
+            FBM0: u1,
+            ///  Filter mode
+            FBM1: u1,
+            ///  Filter mode
+            FBM2: u1,
+            ///  Filter mode
+            FBM3: u1,
+            ///  Filter mode
+            FBM4: u1,
+            ///  Filter mode
+            FBM5: u1,
+            ///  Filter mode
+            FBM6: u1,
+            ///  Filter mode
+            FBM7: u1,
+            ///  Filter mode
+            FBM8: u1,
+            ///  Filter mode
+            FBM9: u1,
+            ///  Filter mode
+            FBM10: u1,
+            ///  Filter mode
+            FBM11: u1,
+            ///  Filter mode
+            FBM12: u1,
+            ///  Filter mode
+            FBM13: u1,
+            ///  Filter mode
+            FBM14: u1,
+            ///  Filter mode
+            FBM15: u1,
+            ///  Filter mode
+            FBM16: u1,
+            ///  Filter mode
+            FBM17: u1,
+            ///  Filter mode
+            FBM18: u1,
+            ///  Filter mode
+            FBM19: u1,
+            ///  Filter mode
+            FBM20: u1,
+            ///  Filter mode
+            FBM21: u1,
+            ///  Filter mode
+            FBM22: u1,
+            ///  Filter mode
+            FBM23: u1,
+            ///  Filter mode
+            FBM24: u1,
+            ///  Filter mode
+            FBM25: u1,
+            ///  Filter mode
+            FBM26: u1,
+            ///  Filter mode
+            FBM27: u1,
+            padding: u4,
+        }),
+        reserved524: [4]u8,
+        ///  filter scale register
+        FS1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter scale configuration
+            FSC0: u1,
+            ///  Filter scale configuration
+            FSC1: u1,
+            ///  Filter scale configuration
+            FSC2: u1,
+            ///  Filter scale configuration
+            FSC3: u1,
+            ///  Filter scale configuration
+            FSC4: u1,
+            ///  Filter scale configuration
+            FSC5: u1,
+            ///  Filter scale configuration
+            FSC6: u1,
+            ///  Filter scale configuration
+            FSC7: u1,
+            ///  Filter scale configuration
+            FSC8: u1,
+            ///  Filter scale configuration
+            FSC9: u1,
+            ///  Filter scale configuration
+            FSC10: u1,
+            ///  Filter scale configuration
+            FSC11: u1,
+            ///  Filter scale configuration
+            FSC12: u1,
+            ///  Filter scale configuration
+            FSC13: u1,
+            ///  Filter scale configuration
+            FSC14: u1,
+            ///  Filter scale configuration
+            FSC15: u1,
+            ///  Filter scale configuration
+            FSC16: u1,
+            ///  Filter scale configuration
+            FSC17: u1,
+            ///  Filter scale configuration
+            FSC18: u1,
+            ///  Filter scale configuration
+            FSC19: u1,
+            ///  Filter scale configuration
+            FSC20: u1,
+            ///  Filter scale configuration
+            FSC21: u1,
+            ///  Filter scale configuration
+            FSC22: u1,
+            ///  Filter scale configuration
+            FSC23: u1,
+            ///  Filter scale configuration
+            FSC24: u1,
+            ///  Filter scale configuration
+            FSC25: u1,
+            ///  Filter scale configuration
+            FSC26: u1,
+            ///  Filter scale configuration
+            FSC27: u1,
+            padding: u4,
+        }),
+        reserved532: [4]u8,
+        ///  filter FIFO assignment register
+        FFA1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter FIFO assignment for filter 0
+            FFA0: u1,
+            ///  Filter FIFO assignment for filter 1
+            FFA1: u1,
+            ///  Filter FIFO assignment for filter 2
+            FFA2: u1,
+            ///  Filter FIFO assignment for filter 3
+            FFA3: u1,
+            ///  Filter FIFO assignment for filter 4
+            FFA4: u1,
+            ///  Filter FIFO assignment for filter 5
+            FFA5: u1,
+            ///  Filter FIFO assignment for filter 6
+            FFA6: u1,
+            ///  Filter FIFO assignment for filter 7
+            FFA7: u1,
+            ///  Filter FIFO assignment for filter 8
+            FFA8: u1,
+            ///  Filter FIFO assignment for filter 9
+            FFA9: u1,
+            ///  Filter FIFO assignment for filter 10
+            FFA10: u1,
+            ///  Filter FIFO assignment for filter 11
+            FFA11: u1,
+            ///  Filter FIFO assignment for filter 12
+            FFA12: u1,
+            ///  Filter FIFO assignment for filter 13
+            FFA13: u1,
+            ///  Filter FIFO assignment for filter 14
+            FFA14: u1,
+            ///  Filter FIFO assignment for filter 15
+            FFA15: u1,
+            ///  Filter FIFO assignment for filter 16
+            FFA16: u1,
+            ///  Filter FIFO assignment for filter 17
+            FFA17: u1,
+            ///  Filter FIFO assignment for filter 18
+            FFA18: u1,
+            ///  Filter FIFO assignment for filter 19
+            FFA19: u1,
+            ///  Filter FIFO assignment for filter 20
+            FFA20: u1,
+            ///  Filter FIFO assignment for filter 21
+            FFA21: u1,
+            ///  Filter FIFO assignment for filter 22
+            FFA22: u1,
+            ///  Filter FIFO assignment for filter 23
+            FFA23: u1,
+            ///  Filter FIFO assignment for filter 24
+            FFA24: u1,
+            ///  Filter FIFO assignment for filter 25
+            FFA25: u1,
+            ///  Filter FIFO assignment for filter 26
+            FFA26: u1,
+            ///  Filter FIFO assignment for filter 27
+            FFA27: u1,
+            padding: u4,
+        }),
+        reserved540: [4]u8,
+        ///  filter activation register
+        FA1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter active
+            FACT0: u1,
+            ///  Filter active
+            FACT1: u1,
+            ///  Filter active
+            FACT2: u1,
+            ///  Filter active
+            FACT3: u1,
+            ///  Filter active
+            FACT4: u1,
+            ///  Filter active
+            FACT5: u1,
+            ///  Filter active
+            FACT6: u1,
+            ///  Filter active
+            FACT7: u1,
+            ///  Filter active
+            FACT8: u1,
+            ///  Filter active
+            FACT9: u1,
+            ///  Filter active
+            FACT10: u1,
+            ///  Filter active
+            FACT11: u1,
+            ///  Filter active
+            FACT12: u1,
+            ///  Filter active
+            FACT13: u1,
+            ///  Filter active
+            FACT14: u1,
+            ///  Filter active
+            FACT15: u1,
+            ///  Filter active
+            FACT16: u1,
+            ///  Filter active
+            FACT17: u1,
+            ///  Filter active
+            FACT18: u1,
+            ///  Filter active
+            FACT19: u1,
+            ///  Filter active
+            FACT20: u1,
+            ///  Filter active
+            FACT21: u1,
+            ///  Filter active
+            FACT22: u1,
+            ///  Filter active
+            FACT23: u1,
+            ///  Filter active
+            FACT24: u1,
+            ///  Filter active
+            FACT25: u1,
+            ///  Filter active
+            FACT26: u1,
+            ///  Filter active
+            FACT27: u1,
+            padding: u4,
+        }),
+        reserved576: [32]u8,
+        ///  Filter bank 0 register 1
+        F0R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 0 register 2
+        F0R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 1 register 1
+        F1R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 1 register 2
+        F1R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 2 register 1
+        F2R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 2 register 2
+        F2R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 3 register 1
+        F3R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 3 register 2
+        F3R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 1
+        F4R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 2
+        F4R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 5 register 1
+        F5R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 5 register 2
+        F5R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 6 register 1
+        F6R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 6 register 2
+        F6R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 7 register 1
+        F7R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 7 register 2
+        F7R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 8 register 1
+        F8R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 8 register 2
+        F8R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 9 register 1
+        F9R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 9 register 2
+        F9R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 10 register 1
+        F10R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 10 register 2
+        F10R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 11 register 1
+        F11R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 11 register 2
+        F11R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 1
+        F12R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 12 register 2
+        F12R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 13 register 1
+        F13R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 13 register 2
+        F13R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 14 register 1
+        F14R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 14 register 2
+        F14R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 15 register 1
+        F15R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 15 register 2
+        F15R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 16 register 1
+        F16R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 16 register 2
+        F16R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 17 register 1
+        F17R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 17 register 2
+        F17R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 18 register 1
+        F18R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 18 register 2
+        F18R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 19 register 1
+        F19R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 19 register 2
+        F19R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 20 register 1
+        F20R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 20 register 2
+        F20R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 21 register 1
+        F21R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 21 register 2
+        F21R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 22 register 1
+        F22R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 22 register 2
+        F22R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 23 register 1
+        F23R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 23 register 2
+        F23R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 24 register 1
+        F24R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 24 register 2
+        F24R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 25 register 1
+        F25R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 25 register 2
+        F25R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 26 register 1
+        F26R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 26 register 2
+        F26R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 27 register 1
+        F27R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 27 register 2
+        F27R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_PWRCLK = extern struct {
+        ///  OTG_FS power and clock gating control register
+        FS_PCGCCTL: mmio.Mmio(packed struct(u32) {
+            ///  Stop PHY clock
+            STPPCLK: u1,
+            ///  Gate HCLK
+            GATEHCLK: u1,
+            reserved4: u2,
+            ///  PHY Suspended
+            PHYSUSP: u1,
+            padding: u27,
+        }),
+    };
+
+    ///  Digital-to-analog converter
+    pub const DAC = extern struct {
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 enable
+            EN1: u1,
+            ///  DAC channel1 output buffer disable
+            BOFF1: u1,
+            ///  DAC channel1 trigger enable
+            TEN1: u1,
+            ///  DAC channel1 trigger selection
+            TSEL1: u3,
+            ///  DAC channel1 noise/triangle wave generation enable
+            WAVE1: u2,
+            ///  DAC channel1 mask/amplitude selector
+            MAMP1: u4,
+            ///  DAC channel1 DMA enable
+            DMAEN1: u1,
+            ///  DAC channel1 DMA Underrun Interrupt enable
+            DMAUDRIE1: u1,
+            reserved16: u2,
+            ///  DAC channel2 enable
+            EN2: u1,
+            ///  DAC channel2 output buffer disable
+            BOFF2: u1,
+            ///  DAC channel2 trigger enable
+            TEN2: u1,
+            ///  DAC channel2 trigger selection
+            TSEL2: u3,
+            ///  DAC channel2 noise/triangle wave generation enable
+            WAVE2: u2,
+            ///  DAC channel2 mask/amplitude selector
+            MAMP2: u4,
+            ///  DAC channel2 DMA enable
+            DMAEN2: u1,
+            ///  DAC channel2 DMA underrun interrupt enable
+            DMAUDRIE2: u1,
+            padding: u2,
+        }),
+        ///  software trigger register
+        SWTRIGR: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 software trigger
+            SWTRIG1: u1,
+            ///  DAC channel2 software trigger
+            SWTRIG2: u1,
+            padding: u30,
+        }),
+        ///  channel1 12-bit right-aligned data holding register
+        DHR12R1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 12-bit right-aligned data
+            DACC1DHR: u12,
+            padding: u20,
+        }),
+        ///  channel1 12-bit left aligned data holding register
+        DHR12L1: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel1 12-bit left-aligned data
+            DACC1DHR: u12,
+            padding: u16,
+        }),
+        ///  channel1 8-bit right aligned data holding register
+        DHR8R1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 8-bit right-aligned data
+            DACC1DHR: u8,
+            padding: u24,
+        }),
+        ///  channel2 12-bit right aligned data holding register
+        DHR12R2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 12-bit right-aligned data
+            DACC2DHR: u12,
+            padding: u20,
+        }),
+        ///  channel2 12-bit left aligned data holding register
+        DHR12L2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel2 12-bit left-aligned data
+            DACC2DHR: u12,
+            padding: u16,
+        }),
+        ///  channel2 8-bit right-aligned data holding register
+        DHR8R2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 8-bit right-aligned data
+            DACC2DHR: u8,
+            padding: u24,
+        }),
+        ///  Dual DAC 12-bit right-aligned data holding register
+        DHR12RD: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 12-bit right-aligned data
+            DACC1DHR: u12,
+            reserved16: u4,
+            ///  DAC channel2 12-bit right-aligned data
+            DACC2DHR: u12,
+            padding: u4,
+        }),
+        ///  DUAL DAC 12-bit left aligned data holding register
+        DHR12LD: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel1 12-bit left-aligned data
+            DACC1DHR: u12,
+            reserved20: u4,
+            ///  DAC channel2 12-bit left-aligned data
+            DACC2DHR: u12,
+        }),
+        ///  DUAL DAC 8-bit right aligned data holding register
+        DHR8RD: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 8-bit right-aligned data
+            DACC1DHR: u8,
+            ///  DAC channel2 8-bit right-aligned data
+            DACC2DHR: u8,
+            padding: u16,
+        }),
+        ///  channel1 data output register
+        DOR1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 data output
+            DACC1DOR: u12,
+            padding: u20,
+        }),
+        ///  channel2 data output register
+        DOR2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 data output
+            DACC2DOR: u12,
+            padding: u20,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            reserved13: u13,
+            ///  DAC channel1 DMA underrun flag
+            DMAUDR1: u1,
+            reserved29: u15,
+            ///  DAC channel2 DMA underrun flag
+            DMAUDR2: u1,
+            padding: u2,
+        }),
+    };
+
+    ///  Power control
+    pub const PWR = extern struct {
+        ///  power control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Low-power deep sleep
+            LPDS: u1,
+            ///  Power down deepsleep
+            PDDS: u1,
+            ///  Clear wakeup flag
+            CWUF: u1,
+            ///  Clear standby flag
+            CSBF: u1,
+            ///  Power voltage detector enable
+            PVDE: u1,
+            ///  PVD level selection
+            PLS: u3,
+            ///  Disable backup domain write protection
+            DBP: u1,
+            ///  Flash power down in Stop mode
+            FPDS: u1,
+            padding: u22,
+        }),
+        ///  power control/status register
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  Wakeup flag
+            WUF: u1,
+            ///  Standby flag
+            SBF: u1,
+            ///  PVD output
+            PVDO: u1,
+            ///  Backup regulator ready
+            BRR: u1,
+            reserved8: u4,
+            ///  Enable WKUP pin
+            EWUP: u1,
+            ///  Backup regulator enable
+            BRE: u1,
+            reserved14: u4,
+            ///  Regulator voltage scaling output selection ready bit
+            VOSRDY: u1,
+            padding: u17,
+        }),
+    };
+
+    ///  Inter-integrated circuit
+    pub const I2C3 = extern struct {
+        ///  Control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral enable
+            PE: u1,
+            ///  SMBus mode
+            SMBUS: u1,
+            reserved3: u1,
+            ///  SMBus type
+            SMBTYPE: u1,
+            ///  ARP enable
+            ENARP: u1,
+            ///  PEC enable
+            ENPEC: u1,
+            ///  General call enable
+            ENGC: u1,
+            ///  Clock stretching disable (Slave mode)
+            NOSTRETCH: u1,
+            ///  Start generation
+            START: u1,
+            ///  Stop generation
+            STOP: u1,
+            ///  Acknowledge enable
+            ACK: u1,
+            ///  Acknowledge/PEC Position (for data reception)
+            POS: u1,
+            ///  Packet error checking
+            PEC: u1,
+            ///  SMBus alert
+            ALERT: u1,
+            reserved15: u1,
+            ///  Software reset
+            SWRST: u1,
+            padding: u16,
+        }),
+        ///  Control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral clock frequency
+            FREQ: u6,
+            reserved8: u2,
+            ///  Error interrupt enable
+            ITERREN: u1,
+            ///  Event interrupt enable
+            ITEVTEN: u1,
+            ///  Buffer interrupt enable
+            ITBUFEN: u1,
+            ///  DMA requests enable
+            DMAEN: u1,
+            ///  DMA last transfer
+            LAST: u1,
+            padding: u19,
+        }),
+        ///  Own address register 1
+        OAR1: mmio.Mmio(packed struct(u32) {
+            ///  Interface address
+            ADD0: u1,
+            ///  Interface address
+            ADD7: u7,
+            ///  Interface address
+            ADD10: u2,
+            reserved15: u5,
+            ///  Addressing mode (slave mode)
+            ADDMODE: u1,
+            padding: u16,
+        }),
+        ///  Own address register 2
+        OAR2: mmio.Mmio(packed struct(u32) {
+            ///  Dual addressing mode enable
+            ENDUAL: u1,
+            ///  Interface address
+            ADD2: u7,
+            padding: u24,
+        }),
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  8-bit data register
+            DR: u8,
+            padding: u24,
+        }),
+        ///  Status register 1
+        SR1: mmio.Mmio(packed struct(u32) {
+            ///  Start bit (Master mode)
+            SB: u1,
+            ///  Address sent (master mode)/matched (slave mode)
+            ADDR: u1,
+            ///  Byte transfer finished
+            BTF: u1,
+            ///  10-bit header sent (Master mode)
+            ADD10: u1,
+            ///  Stop detection (slave mode)
+            STOPF: u1,
+            reserved6: u1,
+            ///  Data register not empty (receivers)
+            RxNE: u1,
+            ///  Data register empty (transmitters)
+            TxE: u1,
+            ///  Bus error
+            BERR: u1,
+            ///  Arbitration lost (master mode)
+            ARLO: u1,
+            ///  Acknowledge failure
+            AF: u1,
+            ///  Overrun/Underrun
+            OVR: u1,
+            ///  PEC Error in reception
+            PECERR: u1,
+            reserved14: u1,
+            ///  Timeout or Tlow error
+            TIMEOUT: u1,
+            ///  SMBus alert
+            SMBALERT: u1,
+            padding: u16,
+        }),
+        ///  Status register 2
+        SR2: mmio.Mmio(packed struct(u32) {
+            ///  Master/slave
+            MSL: u1,
+            ///  Bus busy
+            BUSY: u1,
+            ///  Transmitter/receiver
+            TRA: u1,
+            reserved4: u1,
+            ///  General call address (Slave mode)
+            GENCALL: u1,
+            ///  SMBus device default address (Slave mode)
+            SMBDEFAULT: u1,
+            ///  SMBus host header (Slave mode)
+            SMBHOST: u1,
+            ///  Dual flag (Slave mode)
+            DUALF: u1,
+            ///  acket error checking register
+            PEC: u8,
+            padding: u16,
+        }),
+        ///  Clock control register
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Clock control register in Fast/Standard mode (Master mode)
+            CCR: u12,
+            reserved14: u2,
+            ///  Fast mode duty cycle
+            DUTY: u1,
+            ///  I2C master mode selection
+            F_S: u1,
+            padding: u16,
+        }),
+        ///  TRISE register
+        TRISE: mmio.Mmio(packed struct(u32) {
+            ///  Maximum rise time in Fast/Standard mode (Master mode)
+            TRISE: u6,
+            padding: u26,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_DEVICE = extern struct {
+        ///  OTG_FS device configuration register (OTG_FS_DCFG)
+        FS_DCFG: mmio.Mmio(packed struct(u32) {
+            ///  Device speed
+            DSPD: u2,
+            ///  Non-zero-length status OUT handshake
+            NZLSOHSK: u1,
+            reserved4: u1,
+            ///  Device address
+            DAD: u7,
+            ///  Periodic frame interval
+            PFIVL: u2,
+            padding: u19,
+        }),
+        ///  OTG_FS device control register (OTG_FS_DCTL)
+        FS_DCTL: mmio.Mmio(packed struct(u32) {
+            ///  Remote wakeup signaling
+            RWUSIG: u1,
+            ///  Soft disconnect
+            SDIS: u1,
+            ///  Global IN NAK status
+            GINSTS: u1,
+            ///  Global OUT NAK status
+            GONSTS: u1,
+            ///  Test control
+            TCTL: u3,
+            ///  Set global IN NAK
+            SGINAK: u1,
+            ///  Clear global IN NAK
+            CGINAK: u1,
+            ///  Set global OUT NAK
+            SGONAK: u1,
+            ///  Clear global OUT NAK
+            CGONAK: u1,
+            ///  Power-on programming done
+            POPRGDNE: u1,
+            padding: u20,
+        }),
+        ///  OTG_FS device status register (OTG_FS_DSTS)
+        FS_DSTS: mmio.Mmio(packed struct(u32) {
+            ///  Suspend status
+            SUSPSTS: u1,
+            ///  Enumerated speed
+            ENUMSPD: u2,
+            ///  Erratic error
+            EERR: u1,
+            reserved8: u4,
+            ///  Frame number of the received SOF
+            FNSOF: u14,
+            padding: u10,
+        }),
+        reserved16: [4]u8,
+        ///  OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
+        FS_DIEPMSK: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  Timeout condition mask (Non-isochronous endpoints)
+            TOM: u1,
+            ///  IN token received when TxFIFO empty mask
+            ITTXFEMSK: u1,
+            ///  IN token received with EP mismatch mask
+            INEPNMM: u1,
+            ///  IN endpoint NAK effective mask
+            INEPNEM: u1,
+            padding: u25,
+        }),
+        ///  OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
+        FS_DOEPMSK: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  SETUP phase done mask
+            STUPM: u1,
+            ///  OUT token received when endpoint disabled mask
+            OTEPDM: u1,
+            padding: u27,
+        }),
+        ///  OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
+        FS_DAINT: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint interrupt bits
+            IEPINT: u16,
+            ///  OUT endpoint interrupt bits
+            OEPINT: u16,
+        }),
+        ///  OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
+        FS_DAINTMSK: mmio.Mmio(packed struct(u32) {
+            ///  IN EP interrupt mask bits
+            IEPM: u16,
+            ///  OUT endpoint interrupt bits
+            OEPINT: u16,
+        }),
+        reserved40: [8]u8,
+        ///  OTG_FS device VBUS discharge time register
+        DVBUSDIS: mmio.Mmio(packed struct(u32) {
+            ///  Device VBUS discharge time
+            VBUSDT: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS device VBUS pulsing time register
+        DVBUSPULSE: mmio.Mmio(packed struct(u32) {
+            ///  Device VBUS pulsing time
+            DVBUSP: u12,
+            padding: u20,
+        }),
+        reserved52: [4]u8,
+        ///  OTG_FS device IN endpoint FIFO empty interrupt mask register
+        DIEPEMPMSK: mmio.Mmio(packed struct(u32) {
+            ///  IN EP Tx FIFO empty interrupt mask bits
+            INEPTXFEM: u16,
+            padding: u16,
+        }),
+        reserved256: [200]u8,
+        ///  OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
+        FS_DIEPCTL0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u2,
+            reserved15: u13,
+            ///  USB active endpoint
+            USBAEP: u1,
+            reserved17: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            STALL: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            reserved30: u2,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved264: [4]u8,
+        ///  device endpoint-x interrupt register
+        DIEPINT0: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved272: [4]u8,
+        ///  device endpoint-0 transfer size register
+        DIEPTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u7,
+            reserved19: u12,
+            ///  Packet count
+            PKTCNT: u2,
+            padding: u11,
+        }),
+        reserved280: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS0: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved288: [4]u8,
+        ///  OTG device endpoint-1 control register
+        DIEPCTL1: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            reserved21: u1,
+            ///  Stall
+            Stall: u1,
+            ///  TXFNUM
+            TXFNUM: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM/SD1PID
+            SODDFRM_SD1PID: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved296: [4]u8,
+        ///  device endpoint-1 interrupt register
+        DIEPINT1: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved304: [4]u8,
+        ///  device endpoint-1 transfer size register
+        DIEPTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        reserved312: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS1: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved320: [4]u8,
+        ///  OTG device endpoint-2 control register
+        DIEPCTL2: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            reserved21: u1,
+            ///  Stall
+            Stall: u1,
+            ///  TXFNUM
+            TXFNUM: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved328: [4]u8,
+        ///  device endpoint-2 interrupt register
+        DIEPINT2: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved336: [4]u8,
+        ///  device endpoint-2 transfer size register
+        DIEPTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        reserved344: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS2: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved352: [4]u8,
+        ///  OTG device endpoint-3 control register
+        DIEPCTL3: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            reserved21: u1,
+            ///  Stall
+            Stall: u1,
+            ///  TXFNUM
+            TXFNUM: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved360: [4]u8,
+        ///  device endpoint-3 interrupt register
+        DIEPINT3: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved368: [4]u8,
+        ///  device endpoint-3 transfer size register
+        DIEPTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        reserved376: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS3: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved768: [388]u8,
+        ///  device endpoint-0 control register
+        DOEPCTL0: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u2,
+            reserved15: u13,
+            ///  USBAEP
+            USBAEP: u1,
+            reserved17: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            reserved30: u2,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved776: [4]u8,
+        ///  device endpoint-0 interrupt register
+        DOEPINT0: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved784: [4]u8,
+        ///  device OUT endpoint-0 transfer size register
+        DOEPTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u7,
+            reserved19: u12,
+            ///  Packet count
+            PKTCNT: u1,
+            reserved29: u9,
+            ///  SETUP packet count
+            STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved800: [12]u8,
+        ///  device endpoint-1 control register
+        DOEPCTL1: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved808: [4]u8,
+        ///  device endpoint-1 interrupt register
+        DOEPINT1: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved816: [4]u8,
+        ///  device OUT endpoint-1 transfer size register
+        DOEPTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved832: [12]u8,
+        ///  device endpoint-2 control register
+        DOEPCTL2: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved840: [4]u8,
+        ///  device endpoint-2 interrupt register
+        DOEPINT2: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved848: [4]u8,
+        ///  device OUT endpoint-2 transfer size register
+        DOEPTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved864: [12]u8,
+        ///  device endpoint-3 control register
+        DOEPCTL3: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved872: [4]u8,
+        ///  device endpoint-3 interrupt register
+        DOEPINT3: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved880: [4]u8,
+        ///  device OUT endpoint-3 transfer size register
+        DOEPTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_HOST = extern struct {
+        ///  OTG_FS host configuration register (OTG_FS_HCFG)
+        FS_HCFG: mmio.Mmio(packed struct(u32) {
+            ///  FS/LS PHY clock select
+            FSLSPCS: u2,
+            ///  FS- and LS-only support
+            FSLSS: u1,
+            padding: u29,
+        }),
+        ///  OTG_FS Host frame interval register
+        HFIR: mmio.Mmio(packed struct(u32) {
+            ///  Frame interval
+            FRIVL: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
+        FS_HFNUM: mmio.Mmio(packed struct(u32) {
+            ///  Frame number
+            FRNUM: u16,
+            ///  Frame time remaining
+            FTREM: u16,
+        }),
+        reserved16: [4]u8,
+        ///  OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
+        FS_HPTXSTS: mmio.Mmio(packed struct(u32) {
+            ///  Periodic transmit data FIFO space available
+            PTXFSAVL: u16,
+            ///  Periodic transmit request queue space available
+            PTXQSAV: u8,
+            ///  Top of the periodic transmit request queue
+            PTXQTOP: u8,
+        }),
+        ///  OTG_FS Host all channels interrupt register
+        HAINT: mmio.Mmio(packed struct(u32) {
+            ///  Channel interrupts
+            HAINT: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS host all channels interrupt mask register
+        HAINTMSK: mmio.Mmio(packed struct(u32) {
+            ///  Channel interrupt mask
+            HAINTM: u16,
+            padding: u16,
+        }),
+        reserved64: [36]u8,
+        ///  OTG_FS host port control and status register (OTG_FS_HPRT)
+        FS_HPRT: mmio.Mmio(packed struct(u32) {
+            ///  Port connect status
+            PCSTS: u1,
+            ///  Port connect detected
+            PCDET: u1,
+            ///  Port enable
+            PENA: u1,
+            ///  Port enable/disable change
+            PENCHNG: u1,
+            ///  Port overcurrent active
+            POCA: u1,
+            ///  Port overcurrent change
+            POCCHNG: u1,
+            ///  Port resume
+            PRES: u1,
+            ///  Port suspend
+            PSUSP: u1,
+            ///  Port reset
+            PRST: u1,
+            reserved10: u1,
+            ///  Port line status
+            PLSTS: u2,
+            ///  Port power
+            PPWR: u1,
+            ///  Port test control
+            PTCTL: u4,
+            ///  Port speed
+            PSPD: u2,
+            padding: u13,
+        }),
+        reserved256: [188]u8,
+        ///  OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
+        FS_HCCHAR0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved264: [4]u8,
+        ///  OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
+        FS_HCINT0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
+        FS_HCINTMSK0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-0 transfer size register
+        FS_HCTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved288: [12]u8,
+        ///  OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)
+        FS_HCCHAR1: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved296: [4]u8,
+        ///  OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)
+        FS_HCINT1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)
+        FS_HCINTMSK1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-1 transfer size register
+        FS_HCTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved320: [12]u8,
+        ///  OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)
+        FS_HCCHAR2: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved328: [4]u8,
+        ///  OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)
+        FS_HCINT2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)
+        FS_HCINTMSK2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-2 transfer size register
+        FS_HCTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved352: [12]u8,
+        ///  OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)
+        FS_HCCHAR3: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved360: [4]u8,
+        ///  OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)
+        FS_HCINT3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)
+        FS_HCINTMSK3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-3 transfer size register
+        FS_HCTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved384: [12]u8,
+        ///  OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)
+        FS_HCCHAR4: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved392: [4]u8,
+        ///  OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)
+        FS_HCINT4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)
+        FS_HCINTMSK4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-x transfer size register
+        FS_HCTSIZ4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved416: [12]u8,
+        ///  OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)
+        FS_HCCHAR5: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved424: [4]u8,
+        ///  OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)
+        FS_HCINT5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)
+        FS_HCINTMSK5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-5 transfer size register
+        FS_HCTSIZ5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved448: [12]u8,
+        ///  OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)
+        FS_HCCHAR6: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved456: [4]u8,
+        ///  OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)
+        FS_HCINT6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)
+        FS_HCINTMSK6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-6 transfer size register
+        FS_HCTSIZ6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved480: [12]u8,
+        ///  OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)
+        FS_HCCHAR7: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved488: [4]u8,
+        ///  OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)
+        FS_HCINT7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)
+        FS_HCINTMSK7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-7 transfer size register
+        FS_HCTSIZ7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+    };
+
+    ///  Independent watchdog
+    pub const IWDG = extern struct {
+        ///  Key register
+        KR: mmio.Mmio(packed struct(u32) {
+            ///  Key value (write only, read 0000h)
+            KEY: u16,
+            padding: u16,
+        }),
+        ///  Prescaler register
+        PR: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler divider
+            PR: u3,
+            padding: u29,
+        }),
+        ///  Reload register
+        RLR: mmio.Mmio(packed struct(u32) {
+            ///  Watchdog counter reload value
+            RL: u12,
+            padding: u20,
+        }),
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Watchdog prescaler value update
+            PVU: u1,
+            ///  Watchdog counter reload value update
+            RVU: u1,
+            padding: u30,
+        }),
+    };
+
+    ///  Window watchdog
+    pub const WWDG = extern struct {
+        ///  Control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  7-bit counter (MSB to LSB)
+            T: u7,
+            ///  Activation bit
+            WDGA: u1,
+            padding: u24,
+        }),
+        ///  Configuration register
+        CFR: mmio.Mmio(packed struct(u32) {
+            ///  7-bit window value
+            W: u7,
+            ///  Timer base
+            WDGTB0: u1,
+            ///  Timer base
+            WDGTB1: u1,
+            ///  Early wakeup interrupt
+            EWI: u1,
+            padding: u22,
+        }),
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Early wakeup interrupt flag
+            EWIF: u1,
+            padding: u31,
+        }),
+    };
+
+    ///  Real-time clock
+    pub const RTC = extern struct {
+        ///  time register
+        TR: mmio.Mmio(packed struct(u32) {
+            ///  Second units in BCD format
+            SU: u4,
+            ///  Second tens in BCD format
+            ST: u3,
+            reserved8: u1,
+            ///  Minute units in BCD format
+            MNU: u4,
+            ///  Minute tens in BCD format
+            MNT: u3,
+            reserved16: u1,
+            ///  Hour units in BCD format
+            HU: u4,
+            ///  Hour tens in BCD format
+            HT: u2,
+            ///  AM/PM notation
+            PM: u1,
+            padding: u9,
+        }),
+        ///  date register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Date units in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            reserved8: u2,
+            ///  Month units in BCD format
+            MU: u4,
+            ///  Month tens in BCD format
+            MT: u1,
+            ///  Week day units
+            WDU: u3,
+            ///  Year units in BCD format
+            YU: u4,
+            ///  Year tens in BCD format
+            YT: u4,
+            padding: u8,
+        }),
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Wakeup clock selection
+            WCKSEL: u3,
+            ///  Time-stamp event active edge
+            TSEDGE: u1,
+            ///  Reference clock detection enable (50 or 60 Hz)
+            REFCKON: u1,
+            reserved6: u1,
+            ///  Hour format
+            FMT: u1,
+            ///  Coarse digital calibration enable
+            DCE: u1,
+            ///  Alarm A enable
+            ALRAE: u1,
+            ///  Alarm B enable
+            ALRBE: u1,
+            ///  Wakeup timer enable
+            WUTE: u1,
+            ///  Time stamp enable
+            TSE: u1,
+            ///  Alarm A interrupt enable
+            ALRAIE: u1,
+            ///  Alarm B interrupt enable
+            ALRBIE: u1,
+            ///  Wakeup timer interrupt enable
+            WUTIE: u1,
+            ///  Time-stamp interrupt enable
+            TSIE: u1,
+            ///  Add 1 hour (summer time change)
+            ADD1H: u1,
+            ///  Subtract 1 hour (winter time change)
+            SUB1H: u1,
+            ///  Backup
+            BKP: u1,
+            reserved20: u1,
+            ///  Output polarity
+            POL: u1,
+            ///  Output selection
+            OSEL: u2,
+            ///  Calibration output enable
+            COE: u1,
+            padding: u8,
+        }),
+        ///  initialization and status register
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  Alarm A write flag
+            ALRAWF: u1,
+            ///  Alarm B write flag
+            ALRBWF: u1,
+            ///  Wakeup timer write flag
+            WUTWF: u1,
+            ///  Shift operation pending
+            SHPF: u1,
+            ///  Initialization status flag
+            INITS: u1,
+            ///  Registers synchronization flag
+            RSF: u1,
+            ///  Initialization flag
+            INITF: u1,
+            ///  Initialization mode
+            INIT: u1,
+            ///  Alarm A flag
+            ALRAF: u1,
+            ///  Alarm B flag
+            ALRBF: u1,
+            ///  Wakeup timer flag
+            WUTF: u1,
+            ///  Time-stamp flag
+            TSF: u1,
+            ///  Time-stamp overflow flag
+            TSOVF: u1,
+            ///  Tamper detection flag
+            TAMP1F: u1,
+            ///  TAMPER2 detection flag
+            TAMP2F: u1,
+            reserved16: u1,
+            ///  Recalibration pending Flag
+            RECALPF: u1,
+            padding: u15,
+        }),
+        ///  prescaler register
+        PRER: mmio.Mmio(packed struct(u32) {
+            ///  Synchronous prescaler factor
+            PREDIV_S: u15,
+            reserved16: u1,
+            ///  Asynchronous prescaler factor
+            PREDIV_A: u7,
+            padding: u9,
+        }),
+        ///  wakeup timer register
+        WUTR: mmio.Mmio(packed struct(u32) {
+            ///  Wakeup auto-reload value bits
+            WUT: u16,
+            padding: u16,
+        }),
+        ///  calibration register
+        CALIBR: mmio.Mmio(packed struct(u32) {
+            ///  Digital calibration
+            DC: u5,
+            reserved7: u2,
+            ///  Digital calibration sign
+            DCS: u1,
+            padding: u24,
+        }),
+        ///  alarm A register
+        ALRMAR: mmio.Mmio(packed struct(u32) {
+            ///  Second units in BCD format
+            SU: u4,
+            ///  Second tens in BCD format
+            ST: u3,
+            ///  Alarm A seconds mask
+            MSK1: u1,
+            ///  Minute units in BCD format
+            MNU: u4,
+            ///  Minute tens in BCD format
+            MNT: u3,
+            ///  Alarm A minutes mask
+            MSK2: u1,
+            ///  Hour units in BCD format
+            HU: u4,
+            ///  Hour tens in BCD format
+            HT: u2,
+            ///  AM/PM notation
+            PM: u1,
+            ///  Alarm A hours mask
+            MSK3: u1,
+            ///  Date units or day in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            ///  Week day selection
+            WDSEL: u1,
+            ///  Alarm A date mask
+            MSK4: u1,
+        }),
+        ///  alarm B register
+        ALRMBR: mmio.Mmio(packed struct(u32) {
+            ///  Second units in BCD format
+            SU: u4,
+            ///  Second tens in BCD format
+            ST: u3,
+            ///  Alarm B seconds mask
+            MSK1: u1,
+            ///  Minute units in BCD format
+            MNU: u4,
+            ///  Minute tens in BCD format
+            MNT: u3,
+            ///  Alarm B minutes mask
+            MSK2: u1,
+            ///  Hour units in BCD format
+            HU: u4,
+            ///  Hour tens in BCD format
+            HT: u2,
+            ///  AM/PM notation
+            PM: u1,
+            ///  Alarm B hours mask
+            MSK3: u1,
+            ///  Date units or day in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            ///  Week day selection
+            WDSEL: u1,
+            ///  Alarm B date mask
+            MSK4: u1,
+        }),
+        ///  write protection register
+        WPR: mmio.Mmio(packed struct(u32) {
+            ///  Write protection key
+            KEY: u8,
+            padding: u24,
+        }),
+        ///  sub second register
+        SSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub second value
+            SS: u16,
+            padding: u16,
+        }),
+        ///  shift control register
+        SHIFTR: mmio.Mmio(packed struct(u32) {
+            ///  Subtract a fraction of a second
+            SUBFS: u15,
+            reserved31: u16,
+            ///  Add one second
+            ADD1S: u1,
+        }),
+        ///  time stamp time register
+        TSTR: mmio.Mmio(packed struct(u32) {
+            ///  Tamper 1 detection enable
+            TAMP1E: u1,
+            ///  Active level for tamper 1
+            TAMP1TRG: u1,
+            ///  Tamper interrupt enable
+            TAMPIE: u1,
+            reserved16: u13,
+            ///  TAMPER1 mapping
+            TAMP1INSEL: u1,
+            ///  TIMESTAMP mapping
+            TSINSEL: u1,
+            ///  AFO_ALARM output type
+            ALARMOUTTYPE: u1,
+            padding: u13,
+        }),
+        ///  time stamp date register
+        TSDR: mmio.Mmio(packed struct(u32) {
+            ///  Date units in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            reserved8: u2,
+            ///  Month units in BCD format
+            MU: u4,
+            ///  Month tens in BCD format
+            MT: u1,
+            ///  Week day units
+            WDU: u3,
+            padding: u16,
+        }),
+        ///  timestamp sub second register
+        TSSSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub second value
+            SS: u16,
+            padding: u16,
+        }),
+        ///  calibration register
+        CALR: mmio.Mmio(packed struct(u32) {
+            ///  Calibration minus
+            CALM: u9,
+            reserved13: u4,
+            ///  Use a 16-second calibration cycle period
+            CALW16: u1,
+            ///  Use an 8-second calibration cycle period
+            CALW8: u1,
+            ///  Increase frequency of RTC by 488.5 ppm
+            CALP: u1,
+            padding: u16,
+        }),
+        ///  tamper and alternate function configuration register
+        TAFCR: mmio.Mmio(packed struct(u32) {
+            ///  Tamper 1 detection enable
+            TAMP1E: u1,
+            ///  Active level for tamper 1
+            TAMP1TRG: u1,
+            ///  Tamper interrupt enable
+            TAMPIE: u1,
+            ///  Tamper 2 detection enable
+            TAMP2E: u1,
+            ///  Active level for tamper 2
+            TAMP2TRG: u1,
+            reserved7: u2,
+            ///  Activate timestamp on tamper detection event
+            TAMPTS: u1,
+            ///  Tamper sampling frequency
+            TAMPFREQ: u3,
+            ///  Tamper filter count
+            TAMPFLT: u2,
+            ///  Tamper precharge duration
+            TAMPPRCH: u2,
+            ///  TAMPER pull-up disable
+            TAMPPUDIS: u1,
+            ///  TAMPER1 mapping
+            TAMP1INSEL: u1,
+            ///  TIMESTAMP mapping
+            TSINSEL: u1,
+            ///  AFO_ALARM output type
+            ALARMOUTTYPE: u1,
+            padding: u13,
+        }),
+        ///  alarm A sub second register
+        ALRMASSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub seconds value
+            SS: u15,
+            reserved24: u9,
+            ///  Mask the most-significant bits starting at this bit
+            MASKSS: u4,
+            padding: u4,
+        }),
+        ///  alarm B sub second register
+        ALRMBSSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub seconds value
+            SS: u15,
+            reserved24: u9,
+            ///  Mask the most-significant bits starting at this bit
+            MASKSS: u4,
+            padding: u4,
+        }),
+        reserved80: [4]u8,
+        ///  backup register
+        BKP0R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP1R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP2R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP3R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP4R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP5R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP6R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP7R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP8R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP9R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP10R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP11R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP12R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP13R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP14R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP15R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP16R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP17R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP18R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP19R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+    };
+
+    ///  Universal synchronous asynchronous receiver transmitter
+    pub const UART4 = extern struct {
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Parity error
+            PE: u1,
+            ///  Framing error
+            FE: u1,
+            ///  Noise detected flag
+            NF: u1,
+            ///  Overrun error
+            ORE: u1,
+            ///  IDLE line detected
+            IDLE: u1,
+            ///  Read data register not empty
+            RXNE: u1,
+            ///  Transmission complete
+            TC: u1,
+            ///  Transmit data register empty
+            TXE: u1,
+            ///  LIN break detection flag
+            LBD: u1,
+            padding: u23,
+        }),
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data value
+            DR: u9,
+            padding: u23,
+        }),
+        ///  Baud rate register
+        BRR: mmio.Mmio(packed struct(u32) {
+            ///  fraction of USARTDIV
+            DIV_Fraction: u4,
+            ///  mantissa of USARTDIV
+            DIV_Mantissa: u12,
+            padding: u16,
+        }),
+        ///  Control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Send break
+            SBK: u1,
+            ///  Receiver wakeup
+            RWU: u1,
+            ///  Receiver enable
+            RE: u1,
+            ///  Transmitter enable
+            TE: u1,
+            ///  IDLE interrupt enable
+            IDLEIE: u1,
+            ///  RXNE interrupt enable
+            RXNEIE: u1,
+            ///  Transmission complete interrupt enable
+            TCIE: u1,
+            ///  TXE interrupt enable
+            TXEIE: u1,
+            ///  PE interrupt enable
+            PEIE: u1,
+            ///  Parity selection
+            PS: u1,
+            ///  Parity control enable
+            PCE: u1,
+            ///  Wakeup method
+            WAKE: u1,
+            ///  Word length
+            M: u1,
+            ///  USART enable
+            UE: u1,
+            reserved15: u1,
+            ///  Oversampling mode
+            OVER8: u1,
+            padding: u16,
+        }),
+        ///  Control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Address of the USART node
+            ADD: u4,
+            reserved5: u1,
+            ///  lin break detection length
+            LBDL: u1,
+            ///  LIN break detection interrupt enable
+            LBDIE: u1,
+            reserved12: u5,
+            ///  STOP bits
+            STOP: u2,
+            ///  LIN mode enable
+            LINEN: u1,
+            padding: u17,
+        }),
+        ///  Control register 3
+        CR3: mmio.Mmio(packed struct(u32) {
+            ///  Error interrupt enable
+            EIE: u1,
+            ///  IrDA mode enable
+            IREN: u1,
+            ///  IrDA low-power
+            IRLP: u1,
+            ///  Half-duplex selection
+            HDSEL: u1,
+            reserved6: u2,
+            ///  DMA enable receiver
+            DMAR: u1,
+            ///  DMA enable transmitter
+            DMAT: u1,
+            reserved11: u3,
+            ///  One sample bit method enable
+            ONEBIT: u1,
+            padding: u20,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_GLOBAL = extern struct {
+        ///  OTG_FS control and status register (OTG_FS_GOTGCTL)
+        FS_GOTGCTL: mmio.Mmio(packed struct(u32) {
+            ///  Session request success
+            SRQSCS: u1,
+            ///  Session request
+            SRQ: u1,
+            reserved8: u6,
+            ///  Host negotiation success
+            HNGSCS: u1,
+            ///  HNP request
+            HNPRQ: u1,
+            ///  Host set HNP enable
+            HSHNPEN: u1,
+            ///  Device HNP enabled
+            DHNPEN: u1,
+            reserved16: u4,
+            ///  Connector ID status
+            CIDSTS: u1,
+            ///  Long/short debounce time
+            DBCT: u1,
+            ///  A-session valid
+            ASVLD: u1,
+            ///  B-session valid
+            BSVLD: u1,
+            padding: u12,
+        }),
+        ///  OTG_FS interrupt register (OTG_FS_GOTGINT)
+        FS_GOTGINT: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Session end detected
+            SEDET: u1,
+            reserved8: u5,
+            ///  Session request success status change
+            SRSSCHG: u1,
+            ///  Host negotiation success status change
+            HNSSCHG: u1,
+            reserved17: u7,
+            ///  Host negotiation detected
+            HNGDET: u1,
+            ///  A-device timeout change
+            ADTOCHG: u1,
+            ///  Debounce done
+            DBCDNE: u1,
+            padding: u12,
+        }),
+        ///  OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
+        FS_GAHBCFG: mmio.Mmio(packed struct(u32) {
+            ///  Global interrupt mask
+            GINT: u1,
+            reserved7: u6,
+            ///  TxFIFO empty level
+            TXFELVL: u1,
+            ///  Periodic TxFIFO empty level
+            PTXFELVL: u1,
+            padding: u23,
+        }),
+        ///  OTG_FS USB configuration register (OTG_FS_GUSBCFG)
+        FS_GUSBCFG: mmio.Mmio(packed struct(u32) {
+            ///  FS timeout calibration
+            TOCAL: u3,
+            reserved6: u3,
+            ///  Full Speed serial transceiver select
+            PHYSEL: u1,
+            reserved8: u1,
+            ///  SRP-capable
+            SRPCAP: u1,
+            ///  HNP-capable
+            HNPCAP: u1,
+            ///  USB turnaround time
+            TRDT: u4,
+            reserved29: u15,
+            ///  Force host mode
+            FHMOD: u1,
+            ///  Force device mode
+            FDMOD: u1,
+            ///  Corrupt Tx packet
+            CTXPKT: u1,
+        }),
+        ///  OTG_FS reset register (OTG_FS_GRSTCTL)
+        FS_GRSTCTL: mmio.Mmio(packed struct(u32) {
+            ///  Core soft reset
+            CSRST: u1,
+            ///  HCLK soft reset
+            HSRST: u1,
+            ///  Host frame counter reset
+            FCRST: u1,
+            reserved4: u1,
+            ///  RxFIFO flush
+            RXFFLSH: u1,
+            ///  TxFIFO flush
+            TXFFLSH: u1,
+            ///  TxFIFO number
+            TXFNUM: u5,
+            reserved31: u20,
+            ///  AHB master idle
+            AHBIDL: u1,
+        }),
+        ///  OTG_FS core interrupt register (OTG_FS_GINTSTS)
+        FS_GINTSTS: mmio.Mmio(packed struct(u32) {
+            ///  Current mode of operation
+            CMOD: u1,
+            ///  Mode mismatch interrupt
+            MMIS: u1,
+            ///  OTG interrupt
+            OTGINT: u1,
+            ///  Start of frame
+            SOF: u1,
+            ///  RxFIFO non-empty
+            RXFLVL: u1,
+            ///  Non-periodic TxFIFO empty
+            NPTXFE: u1,
+            ///  Global IN non-periodic NAK effective
+            GINAKEFF: u1,
+            ///  Global OUT NAK effective
+            GOUTNAKEFF: u1,
+            reserved10: u2,
+            ///  Early suspend
+            ESUSP: u1,
+            ///  USB suspend
+            USBSUSP: u1,
+            ///  USB reset
+            USBRST: u1,
+            ///  Enumeration done
+            ENUMDNE: u1,
+            ///  Isochronous OUT packet dropped interrupt
+            ISOODRP: u1,
+            ///  End of periodic frame interrupt
+            EOPF: u1,
+            reserved18: u2,
+            ///  IN endpoint interrupt
+            IEPINT: u1,
+            ///  OUT endpoint interrupt
+            OEPINT: u1,
+            ///  Incomplete isochronous IN transfer
+            IISOIXFR: u1,
+            ///  Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)
+            IPXFR_INCOMPISOOUT: u1,
+            reserved24: u2,
+            ///  Host port interrupt
+            HPRTINT: u1,
+            ///  Host channels interrupt
+            HCINT: u1,
+            ///  Periodic TxFIFO empty
+            PTXFE: u1,
+            reserved28: u1,
+            ///  Connector ID status change
+            CIDSCHG: u1,
+            ///  Disconnect detected interrupt
+            DISCINT: u1,
+            ///  Session request/new session detected interrupt
+            SRQINT: u1,
+            ///  Resume/remote wakeup detected interrupt
+            WKUPINT: u1,
+        }),
+        ///  OTG_FS interrupt mask register (OTG_FS_GINTMSK)
+        FS_GINTMSK: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Mode mismatch interrupt mask
+            MMISM: u1,
+            ///  OTG interrupt mask
+            OTGINT: u1,
+            ///  Start of frame mask
+            SOFM: u1,
+            ///  Receive FIFO non-empty mask
+            RXFLVLM: u1,
+            ///  Non-periodic TxFIFO empty mask
+            NPTXFEM: u1,
+            ///  Global non-periodic IN NAK effective mask
+            GINAKEFFM: u1,
+            ///  Global OUT NAK effective mask
+            GONAKEFFM: u1,
+            reserved10: u2,
+            ///  Early suspend mask
+            ESUSPM: u1,
+            ///  USB suspend mask
+            USBSUSPM: u1,
+            ///  USB reset mask
+            USBRST: u1,
+            ///  Enumeration done mask
+            ENUMDNEM: u1,
+            ///  Isochronous OUT packet dropped interrupt mask
+            ISOODRPM: u1,
+            ///  End of periodic frame interrupt mask
+            EOPFM: u1,
+            reserved17: u1,
+            ///  Endpoint mismatch interrupt mask
+            EPMISM: u1,
+            ///  IN endpoints interrupt mask
+            IEPINT: u1,
+            ///  OUT endpoints interrupt mask
+            OEPINT: u1,
+            ///  Incomplete isochronous IN transfer mask
+            IISOIXFRM: u1,
+            ///  Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)
+            IPXFRM_IISOOXFRM: u1,
+            reserved24: u2,
+            ///  Host port interrupt mask
+            PRTIM: u1,
+            ///  Host channels interrupt mask
+            HCIM: u1,
+            ///  Periodic TxFIFO empty mask
+            PTXFEM: u1,
+            reserved28: u1,
+            ///  Connector ID status change mask
+            CIDSCHGM: u1,
+            ///  Disconnect detected interrupt mask
+            DISCINT: u1,
+            ///  Session request/new session detected interrupt mask
+            SRQIM: u1,
+            ///  Resume/remote wakeup detected interrupt mask
+            WUIM: u1,
+        }),
+        ///  OTG_FS Receive status debug read(Device mode)
+        FS_GRXSTSR_Device: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Byte count
+            BCNT: u11,
+            ///  Data PID
+            DPID: u2,
+            ///  Packet status
+            PKTSTS: u4,
+            ///  Frame number
+            FRMNUM: u4,
+            padding: u7,
+        }),
+        reserved36: [4]u8,
+        ///  OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
+        FS_GRXFSIZ: mmio.Mmio(packed struct(u32) {
+            ///  RxFIFO depth
+            RXFD: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS non-periodic transmit FIFO size register (Device mode)
+        FS_GNPTXFSIZ_Device: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint 0 transmit RAM start address
+            TX0FSA: u16,
+            ///  Endpoint 0 TxFIFO depth
+            TX0FD: u16,
+        }),
+        ///  OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)
+        FS_GNPTXSTS: mmio.Mmio(packed struct(u32) {
+            ///  Non-periodic TxFIFO space available
+            NPTXFSAV: u16,
+            ///  Non-periodic transmit request queue space available
+            NPTQXSAV: u8,
+            ///  Top of the non-periodic transmit request queue
+            NPTXQTOP: u7,
+            padding: u1,
+        }),
+        reserved56: [8]u8,
+        ///  OTG_FS general core configuration register (OTG_FS_GCCFG)
+        FS_GCCFG: mmio.Mmio(packed struct(u32) {
+            reserved16: u16,
+            ///  Power down
+            PWRDWN: u1,
+            reserved18: u1,
+            ///  Enable the VBUS sensing device
+            VBUSASEN: u1,
+            ///  Enable the VBUS sensing device
+            VBUSBSEN: u1,
+            ///  SOF output enable
+            SOFOUTEN: u1,
+            padding: u11,
+        }),
+        ///  core ID register
+        FS_CID: mmio.Mmio(packed struct(u32) {
+            ///  Product ID field
+            PRODUCT_ID: u32,
+        }),
+        reserved256: [192]u8,
+        ///  OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
+        FS_HPTXFSIZ: mmio.Mmio(packed struct(u32) {
+            ///  Host periodic TxFIFO start address
+            PTXSA: u16,
+            ///  Host periodic TxFIFO depth
+            PTXFSIZ: u16,
+        }),
+        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)
+        FS_DIEPTXF1: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFO2 transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)
+        FS_DIEPTXF2: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFO3 transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)
+        FS_DIEPTXF3: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFO4 transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+    };
+
+    ///  Cryptographic processor
+    pub const CRC = extern struct {
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data Register
+            DR: u32,
+        }),
+        ///  Independent Data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Independent Data register
+            IDR: u8,
+            padding: u24,
+        }),
+        ///  Control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Control regidter
+            CR: u1,
+            padding: u31,
+        }),
+    };
+
+    ///  Ethernet: DMA controller operation
+    pub const Ethernet_DMA = extern struct {
+        ///  Ethernet DMA bus mode register
+        DMABMR: mmio.Mmio(packed struct(u32) {
+            ///  SR
+            SR: u1,
+            ///  DA
+            DA: u1,
+            ///  DSL
+            DSL: u5,
+            ///  EDFE
+            EDFE: u1,
+            ///  PBL
+            PBL: u6,
+            ///  RTPR
+            RTPR: u2,
+            ///  FB
+            FB: u1,
+            ///  RDP
+            RDP: u6,
+            ///  USP
+            USP: u1,
+            ///  FPM
+            FPM: u1,
+            ///  AAB
+            AAB: u1,
+            ///  MB
+            MB: u1,
+            padding: u5,
+        }),
+        ///  Ethernet DMA transmit poll demand register
+        DMATPDR: mmio.Mmio(packed struct(u32) {
+            ///  TPD
+            TPD: u32,
+        }),
+        ///  EHERNET DMA receive poll demand register
+        DMARPDR: mmio.Mmio(packed struct(u32) {
+            ///  RPD
+            RPD: u32,
+        }),
+        ///  Ethernet DMA receive descriptor list address register
+        DMARDLAR: mmio.Mmio(packed struct(u32) {
+            ///  SRL
+            SRL: u32,
+        }),
+        ///  Ethernet DMA transmit descriptor list address register
+        DMATDLAR: mmio.Mmio(packed struct(u32) {
+            ///  STL
+            STL: u32,
+        }),
+        ///  Ethernet DMA status register
+        DMASR: mmio.Mmio(packed struct(u32) {
+            ///  TS
+            TS: u1,
+            ///  TPSS
+            TPSS: u1,
+            ///  TBUS
+            TBUS: u1,
+            ///  TJTS
+            TJTS: u1,
+            ///  ROS
+            ROS: u1,
+            ///  TUS
+            TUS: u1,
+            ///  RS
+            RS: u1,
+            ///  RBUS
+            RBUS: u1,
+            ///  RPSS
+            RPSS: u1,
+            ///  PWTS
+            PWTS: u1,
+            ///  ETS
+            ETS: u1,
+            reserved13: u2,
+            ///  FBES
+            FBES: u1,
+            ///  ERS
+            ERS: u1,
+            ///  AIS
+            AIS: u1,
+            ///  NIS
+            NIS: u1,
+            ///  RPS
+            RPS: u3,
+            ///  TPS
+            TPS: u3,
+            ///  EBS
+            EBS: u3,
+            reserved27: u1,
+            ///  MMCS
+            MMCS: u1,
+            ///  PMTS
+            PMTS: u1,
+            ///  TSTS
+            TSTS: u1,
+            padding: u2,
+        }),
+        ///  Ethernet DMA operation mode register
+        DMAOMR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  SR
+            SR: u1,
+            ///  OSF
+            OSF: u1,
+            ///  RTC
+            RTC: u2,
+            reserved6: u1,
+            ///  FUGF
+            FUGF: u1,
+            ///  FEF
+            FEF: u1,
+            reserved13: u5,
+            ///  ST
+            ST: u1,
+            ///  TTC
+            TTC: u3,
+            reserved20: u3,
+            ///  FTF
+            FTF: u1,
+            ///  TSF
+            TSF: u1,
+            reserved24: u2,
+            ///  DFRF
+            DFRF: u1,
+            ///  RSF
+            RSF: u1,
+            ///  DTCEFD
+            DTCEFD: u1,
+            padding: u5,
+        }),
+        ///  Ethernet DMA interrupt enable register
+        DMAIER: mmio.Mmio(packed struct(u32) {
+            ///  TIE
+            TIE: u1,
+            ///  TPSIE
+            TPSIE: u1,
+            ///  TBUIE
+            TBUIE: u1,
+            ///  TJTIE
+            TJTIE: u1,
+            ///  ROIE
+            ROIE: u1,
+            ///  TUIE
+            TUIE: u1,
+            ///  RIE
+            RIE: u1,
+            ///  RBUIE
+            RBUIE: u1,
+            ///  RPSIE
+            RPSIE: u1,
+            ///  RWTIE
+            RWTIE: u1,
+            ///  ETIE
+            ETIE: u1,
+            reserved13: u2,
+            ///  FBEIE
+            FBEIE: u1,
+            ///  ERIE
+            ERIE: u1,
+            ///  AISE
+            AISE: u1,
+            ///  NISE
+            NISE: u1,
+            padding: u15,
+        }),
+        ///  Ethernet DMA missed frame and buffer overflow counter register
+        DMAMFBOCR: mmio.Mmio(packed struct(u32) {
+            ///  MFC
+            MFC: u16,
+            ///  OMFC
+            OMFC: u1,
+            ///  MFA
+            MFA: u11,
+            ///  OFOC
+            OFOC: u1,
+            padding: u3,
+        }),
+        ///  Ethernet DMA receive status watchdog timer register
+        DMARSWTR: mmio.Mmio(packed struct(u32) {
+            ///  RSWTC
+            RSWTC: u8,
+            padding: u24,
+        }),
+        reserved72: [32]u8,
+        ///  Ethernet DMA current host transmit descriptor register
+        DMACHTDR: mmio.Mmio(packed struct(u32) {
+            ///  HTDAP
+            HTDAP: u32,
+        }),
+        ///  Ethernet DMA current host receive descriptor register
+        DMACHRDR: mmio.Mmio(packed struct(u32) {
+            ///  HRDAP
+            HRDAP: u32,
+        }),
+        ///  Ethernet DMA current host transmit buffer address register
+        DMACHTBAR: mmio.Mmio(packed struct(u32) {
+            ///  HTBAP
+            HTBAP: u32,
+        }),
+        ///  Ethernet DMA current host receive buffer address register
+        DMACHRBAR: mmio.Mmio(packed struct(u32) {
+            ///  HRBAP
+            HRBAP: u32,
+        }),
+    };
+
+    ///  Common ADC registers
+    pub const C_ADC = extern struct {
+        ///  ADC Common status register
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog flag of ADC 1
+            AWD1: u1,
+            ///  End of conversion of ADC 1
+            EOC1: u1,
+            ///  Injected channel end of conversion of ADC 1
+            JEOC1: u1,
+            ///  Injected channel Start flag of ADC 1
+            JSTRT1: u1,
+            ///  Regular channel Start flag of ADC 1
+            STRT1: u1,
+            ///  Overrun flag of ADC 1
+            OVR1: u1,
+            reserved8: u2,
+            ///  Analog watchdog flag of ADC 2
+            AWD2: u1,
+            ///  End of conversion of ADC 2
+            EOC2: u1,
+            ///  Injected channel end of conversion of ADC 2
+            JEOC2: u1,
+            ///  Injected channel Start flag of ADC 2
+            JSTRT2: u1,
+            ///  Regular channel Start flag of ADC 2
+            STRT2: u1,
+            ///  Overrun flag of ADC 2
+            OVR2: u1,
+            reserved16: u2,
+            ///  Analog watchdog flag of ADC 3
+            AWD3: u1,
+            ///  End of conversion of ADC 3
+            EOC3: u1,
+            ///  Injected channel end of conversion of ADC 3
+            JEOC3: u1,
+            ///  Injected channel Start flag of ADC 3
+            JSTRT3: u1,
+            ///  Regular channel Start flag of ADC 3
+            STRT3: u1,
+            ///  Overrun flag of ADC3
+            OVR3: u1,
+            padding: u10,
+        }),
+        ///  ADC common control register
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Multi ADC mode selection
+            MULT: u5,
+            reserved8: u3,
+            ///  Delay between 2 sampling phases
+            DELAY: u4,
+            reserved13: u1,
+            ///  DMA disable selection for multi-ADC mode
+            DDS: u1,
+            ///  Direct memory access mode for multi ADC mode
+            DMA: u2,
+            ///  ADC prescaler
+            ADCPRE: u2,
+            reserved22: u4,
+            ///  VBAT enable
+            VBATE: u1,
+            ///  Temperature sensor and VREFINT enable
+            TSVREFE: u1,
+            padding: u8,
+        }),
+        ///  ADC common regular data register for dual and triple modes
+        CDR: mmio.Mmio(packed struct(u32) {
+            ///  1st data item of a pair of regular conversions
+            DATA1: u16,
+            ///  2nd data item of a pair of regular conversions
+            DATA2: u16,
+        }),
+    };
+
+    ///  Advanced-timers
+    pub const TIM1 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/compare preloaded control
+            CCPC: u1,
+            reserved2: u1,
+            ///  Capture/compare control update selection
+            CCUS: u1,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            ///  Output Idle state 1
+            OIS1: u1,
+            ///  Output Idle state 1
+            OIS1N: u1,
+            ///  Output Idle state 2
+            OIS2: u1,
+            ///  Output Idle state 2
+            OIS2N: u1,
+            ///  Output Idle state 3
+            OIS3: u1,
+            ///  Output Idle state 3
+            OIS3N: u1,
+            ///  Output Idle state 4
+            OIS4: u1,
+            padding: u17,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            padding: u16,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            ///  COM interrupt enable
+            COMIE: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            ///  Break interrupt enable
+            BIE: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            ///  COM DMA request enable
+            COMDE: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            ///  COM interrupt flag
+            COMIF: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            ///  Break interrupt flag
+            BIF: u1,
+            reserved9: u1,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            padding: u19,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            ///  Capture/Compare control update generation
+            COMG: u1,
+            ///  Trigger generation
+            TG: u1,
+            ///  Break generation
+            BG: u1,
+            padding: u24,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            ///  Output Compare 1 clear enable
+            OC1CE: u1,
+            ///  Capture/Compare 2 selection
+            CC2S: u2,
+            ///  Output Compare 2 fast enable
+            OC2FE: u1,
+            ///  Output Compare 2 preload enable
+            OC2PE: u1,
+            ///  Output Compare 2 mode
+            OC2M: u3,
+            ///  Output Compare 2 clear enable
+            OC2CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare mode register 2 (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 3 selection
+            CC3S: u2,
+            ///  Output compare 3 fast enable
+            OC3FE: u1,
+            ///  Output compare 3 preload enable
+            OC3PE: u1,
+            ///  Output compare 3 mode
+            OC3M: u3,
+            ///  Output compare 3 clear enable
+            OC3CE: u1,
+            ///  Capture/Compare 4 selection
+            CC4S: u2,
+            ///  Output compare 4 fast enable
+            OC4FE: u1,
+            ///  Output compare 4 preload enable
+            OC4PE: u1,
+            ///  Output compare 4 mode
+            OC4M: u3,
+            ///  Output compare 4 clear enable
+            OC4CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            ///  Capture/Compare 1 complementary output enable
+            CC1NE: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            ///  Capture/Compare 2 complementary output enable
+            CC2NE: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            ///  Capture/Compare 3 complementary output enable
+            CC3NE: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            padding: u18,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        ///  repetition counter register
+        RCR: mmio.Mmio(packed struct(u32) {
+            ///  Repetition counter value
+            REP: u8,
+            padding: u24,
+        }),
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 2 value
+            CCR2: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare value
+            CCR3: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare value
+            CCR4: u16,
+            padding: u16,
+        }),
+        ///  break and dead-time register
+        BDTR: mmio.Mmio(packed struct(u32) {
+            ///  Dead-time generator setup
+            DTG: u8,
+            ///  Lock configuration
+            LOCK: u2,
+            ///  Off-state selection for Idle mode
+            OSSI: u1,
+            ///  Off-state selection for Run mode
+            OSSR: u1,
+            ///  Break enable
+            BKE: u1,
+            ///  Break polarity
+            BKP: u1,
+            ///  Automatic output enable
+            AOE: u1,
+            ///  Main output enable
+            MOE: u1,
+            padding: u16,
+        }),
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Ethernet: Precision time protocol
+    pub const Ethernet_PTP = extern struct {
+        ///  Ethernet PTP time stamp control register
+        PTPTSCR: mmio.Mmio(packed struct(u32) {
+            ///  TSE
+            TSE: u1,
+            ///  TSFCU
+            TSFCU: u1,
+            ///  TSSTI
+            TSSTI: u1,
+            ///  TSSTU
+            TSSTU: u1,
+            ///  TSITE
+            TSITE: u1,
+            ///  TTSARU
+            TTSARU: u1,
+            reserved8: u2,
+            ///  TSSARFE
+            TSSARFE: u1,
+            ///  TSSSR
+            TSSSR: u1,
+            ///  TSPTPPSV2E
+            TSPTPPSV2E: u1,
+            ///  TSSPTPOEFE
+            TSSPTPOEFE: u1,
+            ///  TSSIPV6FE
+            TSSIPV6FE: u1,
+            ///  TSSIPV4FE
+            TSSIPV4FE: u1,
+            ///  TSSEME
+            TSSEME: u1,
+            ///  TSSMRME
+            TSSMRME: u1,
+            ///  TSCNT
+            TSCNT: u2,
+            ///  TSPFFMAE
+            TSPFFMAE: u1,
+            padding: u13,
+        }),
+        ///  Ethernet PTP subsecond increment register
+        PTPSSIR: mmio.Mmio(packed struct(u32) {
+            ///  STSSI
+            STSSI: u8,
+            padding: u24,
+        }),
+        ///  Ethernet PTP time stamp high register
+        PTPTSHR: mmio.Mmio(packed struct(u32) {
+            ///  STS
+            STS: u32,
+        }),
+        ///  Ethernet PTP time stamp low register
+        PTPTSLR: mmio.Mmio(packed struct(u32) {
+            ///  STSS
+            STSS: u31,
+            ///  STPNS
+            STPNS: u1,
+        }),
+        ///  Ethernet PTP time stamp high update register
+        PTPTSHUR: mmio.Mmio(packed struct(u32) {
+            ///  TSUS
+            TSUS: u32,
+        }),
+        ///  Ethernet PTP time stamp low update register
+        PTPTSLUR: mmio.Mmio(packed struct(u32) {
+            ///  TSUSS
+            TSUSS: u31,
+            ///  TSUPNS
+            TSUPNS: u1,
+        }),
+        ///  Ethernet PTP time stamp addend register
+        PTPTSAR: mmio.Mmio(packed struct(u32) {
+            ///  TSA
+            TSA: u32,
+        }),
+        ///  Ethernet PTP target time high register
+        PTPTTHR: mmio.Mmio(packed struct(u32) {
+            ///  0
+            TTSH: u32,
+        }),
+        ///  Ethernet PTP target time low register
+        PTPTTLR: mmio.Mmio(packed struct(u32) {
+            ///  TTSL
+            TTSL: u32,
+        }),
+        reserved40: [4]u8,
+        ///  Ethernet PTP time stamp status register
+        PTPTSSR: mmio.Mmio(packed struct(u32) {
+            ///  TSSO
+            TSSO: u1,
+            ///  TSTTR
+            TSTTR: u1,
+            padding: u30,
+        }),
+        ///  Ethernet PTP PPS control register
+        PTPPPSCR: mmio.Mmio(packed struct(u32) {
+            ///  TSSO
+            TSSO: u1,
+            ///  TSTTR
+            TSTTR: u1,
+            padding: u30,
+        }),
+    };
+
+    ///  General purpose timers
+    pub const TIM2 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            padding: u24,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            padding: u16,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            reserved6: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            reserved8: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            reserved14: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            reserved6: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            reserved9: u2,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            padding: u19,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            reserved6: u1,
+            ///  Trigger generation
+            TG: u1,
+            padding: u25,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC1S
+            CC1S: u2,
+            ///  OC1FE
+            OC1FE: u1,
+            ///  OC1PE
+            OC1PE: u1,
+            ///  OC1M
+            OC1M: u3,
+            ///  OC1CE
+            OC1CE: u1,
+            ///  CC2S
+            CC2S: u2,
+            ///  OC2FE
+            OC2FE: u1,
+            ///  OC2PE
+            OC2PE: u1,
+            ///  OC2M
+            OC2M: u3,
+            ///  OC2CE
+            OC2CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare mode register 2 (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC3S
+            CC3S: u2,
+            ///  OC3FE
+            OC3FE: u1,
+            ///  OC3PE
+            OC3PE: u1,
+            ///  OC3M
+            OC3M: u3,
+            ///  OC3CE
+            OC3CE: u1,
+            ///  CC4S
+            CC4S: u2,
+            ///  OC4FE
+            OC4FE: u1,
+            ///  OC4PE
+            OC4PE: u1,
+            ///  OC4M
+            OC4M: u3,
+            ///  O24CE
+            O24CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved7: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            reserved11: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            reserved15: u1,
+            ///  Capture/Compare 4 output Polarity
+            CC4NP: u1,
+            padding: u16,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  Low counter value
+            CNT_L: u16,
+            ///  High counter value
+            CNT_H: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Low Auto-reload value
+            ARR_L: u16,
+            ///  High Auto-reload value
+            ARR_H: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 1 value
+            CCR1_L: u16,
+            ///  High Capture/Compare 1 value
+            CCR1_H: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 2 value
+            CCR2_L: u16,
+            ///  High Capture/Compare 2 value
+            CCR2_H: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR3_L: u16,
+            ///  High Capture/Compare value
+            CCR3_H: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR4_L: u16,
+            ///  High Capture/Compare value
+            CCR4_H: u16,
+        }),
+        reserved72: [4]u8,
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+        ///  TIM5 option register
+        OR: mmio.Mmio(packed struct(u32) {
+            reserved10: u10,
+            ///  Timer Input 4 remap
+            ITR1_RMP: u2,
+            padding: u20,
+        }),
+    };
+
+    ///  General purpose timers
+    pub const TIM3 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            padding: u24,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            padding: u16,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            reserved6: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            reserved8: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            reserved14: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            reserved6: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            reserved9: u2,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            padding: u19,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            reserved6: u1,
+            ///  Trigger generation
+            TG: u1,
+            padding: u25,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC1S
+            CC1S: u2,
+            ///  OC1FE
+            OC1FE: u1,
+            ///  OC1PE
+            OC1PE: u1,
+            ///  OC1M
+            OC1M: u3,
+            ///  OC1CE
+            OC1CE: u1,
+            ///  CC2S
+            CC2S: u2,
+            ///  OC2FE
+            OC2FE: u1,
+            ///  OC2PE
+            OC2PE: u1,
+            ///  OC2M
+            OC2M: u3,
+            ///  OC2CE
+            OC2CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare mode register 2 (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC3S
+            CC3S: u2,
+            ///  OC3FE
+            OC3FE: u1,
+            ///  OC3PE
+            OC3PE: u1,
+            ///  OC3M
+            OC3M: u3,
+            ///  OC3CE
+            OC3CE: u1,
+            ///  CC4S
+            CC4S: u2,
+            ///  OC4FE
+            OC4FE: u1,
+            ///  OC4PE
+            OC4PE: u1,
+            ///  OC4M
+            OC4M: u3,
+            ///  O24CE
+            O24CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved7: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            reserved11: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            reserved15: u1,
+            ///  Capture/Compare 4 output Polarity
+            CC4NP: u1,
+            padding: u16,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  Low counter value
+            CNT_L: u16,
+            ///  High counter value
+            CNT_H: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Low Auto-reload value
+            ARR_L: u16,
+            ///  High Auto-reload value
+            ARR_H: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 1 value
+            CCR1_L: u16,
+            ///  High Capture/Compare 1 value
+            CCR1_H: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 2 value
+            CCR2_L: u16,
+            ///  High Capture/Compare 2 value
+            CCR2_H: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR3_L: u16,
+            ///  High Capture/Compare value
+            CCR3_H: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR4_L: u16,
+            ///  High Capture/Compare value
+            CCR4_H: u16,
+        }),
+        reserved72: [4]u8,
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Ethernet: MAC management counters
+    pub const Ethernet_MMC = extern struct {
+        ///  Ethernet MMC control register
+        MMCCR: mmio.Mmio(packed struct(u32) {
+            ///  CR
+            CR: u1,
+            ///  CSR
+            CSR: u1,
+            ///  ROR
+            ROR: u1,
+            ///  MCF
+            MCF: u1,
+            ///  MCP
+            MCP: u1,
+            ///  MCFHP
+            MCFHP: u1,
+            padding: u26,
+        }),
+        ///  Ethernet MMC receive interrupt register
+        MMCRIR: mmio.Mmio(packed struct(u32) {
+            reserved5: u5,
+            ///  RFCES
+            RFCES: u1,
+            ///  RFAES
+            RFAES: u1,
+            reserved17: u10,
+            ///  RGUFS
+            RGUFS: u1,
+            padding: u14,
+        }),
+        ///  Ethernet MMC transmit interrupt register
+        MMCTIR: mmio.Mmio(packed struct(u32) {
+            reserved14: u14,
+            ///  TGFSCS
+            TGFSCS: u1,
+            ///  TGFMSCS
+            TGFMSCS: u1,
+            reserved21: u5,
+            ///  TGFS
+            TGFS: u1,
+            padding: u10,
+        }),
+        ///  Ethernet MMC receive interrupt mask register
+        MMCRIMR: mmio.Mmio(packed struct(u32) {
+            reserved5: u5,
+            ///  RFCEM
+            RFCEM: u1,
+            ///  RFAEM
+            RFAEM: u1,
+            reserved17: u10,
+            ///  RGUFM
+            RGUFM: u1,
+            padding: u14,
+        }),
+        ///  Ethernet MMC transmit interrupt mask register
+        MMCTIMR: mmio.Mmio(packed struct(u32) {
+            reserved14: u14,
+            ///  TGFSCM
+            TGFSCM: u1,
+            ///  TGFMSCM
+            TGFMSCM: u1,
+            ///  TGFM
+            TGFM: u1,
+            padding: u15,
+        }),
+        reserved76: [56]u8,
+        ///  Ethernet MMC transmitted good frames after a single collision counter
+        MMCTGFSCCR: mmio.Mmio(packed struct(u32) {
+            ///  TGFSCC
+            TGFSCC: u32,
+        }),
+        ///  Ethernet MMC transmitted good frames after more than a single collision
+        MMCTGFMSCCR: mmio.Mmio(packed struct(u32) {
+            ///  TGFMSCC
+            TGFMSCC: u32,
+        }),
+        reserved104: [20]u8,
+        ///  Ethernet MMC transmitted good frames counter register
+        MMCTGFCR: mmio.Mmio(packed struct(u32) {
+            ///  HTL
+            TGFC: u32,
+        }),
+        reserved148: [40]u8,
+        ///  Ethernet MMC received frames with CRC error counter register
+        MMCRFCECR: mmio.Mmio(packed struct(u32) {
+            ///  RFCFC
+            RFCFC: u32,
+        }),
+        ///  Ethernet MMC received frames with alignment error counter register
+        MMCRFAECR: mmio.Mmio(packed struct(u32) {
+            ///  RFAEC
+            RFAEC: u32,
+        }),
+        reserved196: [40]u8,
+        ///  MMC received good unicast frames counter register
+        MMCRGUFCR: mmio.Mmio(packed struct(u32) {
+            ///  RGUFC
+            RGUFC: u32,
+        }),
+    };
+
+    ///  General-purpose-timers
+    pub const TIM5 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            padding: u24,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            padding: u16,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            reserved6: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            reserved8: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            reserved14: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            reserved6: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            reserved9: u2,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            padding: u19,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            reserved6: u1,
+            ///  Trigger generation
+            TG: u1,
+            padding: u25,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC1S
+            CC1S: u2,
+            ///  OC1FE
+            OC1FE: u1,
+            ///  OC1PE
+            OC1PE: u1,
+            ///  OC1M
+            OC1M: u3,
+            ///  OC1CE
+            OC1CE: u1,
+            ///  CC2S
+            CC2S: u2,
+            ///  OC2FE
+            OC2FE: u1,
+            ///  OC2PE
+            OC2PE: u1,
+            ///  OC2M
+            OC2M: u3,
+            ///  OC2CE
+            OC2CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare mode register 2 (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC3S
+            CC3S: u2,
+            ///  OC3FE
+            OC3FE: u1,
+            ///  OC3PE
+            OC3PE: u1,
+            ///  OC3M
+            OC3M: u3,
+            ///  OC3CE
+            OC3CE: u1,
+            ///  CC4S
+            CC4S: u2,
+            ///  OC4FE
+            OC4FE: u1,
+            ///  OC4PE
+            OC4PE: u1,
+            ///  OC4M
+            OC4M: u3,
+            ///  O24CE
+            O24CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved7: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            reserved11: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            reserved15: u1,
+            ///  Capture/Compare 4 output Polarity
+            CC4NP: u1,
+            padding: u16,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  Low counter value
+            CNT_L: u16,
+            ///  High counter value
+            CNT_H: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Low Auto-reload value
+            ARR_L: u16,
+            ///  High Auto-reload value
+            ARR_H: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 1 value
+            CCR1_L: u16,
+            ///  High Capture/Compare 1 value
+            CCR1_H: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 2 value
+            CCR2_L: u16,
+            ///  High Capture/Compare 2 value
+            CCR2_H: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR3_L: u16,
+            ///  High Capture/Compare value
+            CCR3_H: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR4_L: u16,
+            ///  High Capture/Compare value
+            CCR4_H: u16,
+        }),
+        reserved72: [4]u8,
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+        ///  TIM5 option register
+        OR: mmio.Mmio(packed struct(u32) {
+            reserved6: u6,
+            ///  Timer Input 4 remap
+            IT4_RMP: u2,
+            padding: u24,
+        }),
+    };
+
+    ///  General purpose timers
+    pub const TIM9 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            reserved7: u3,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  Master mode selection
+            MMS: u3,
+            padding: u25,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            padding: u24,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            reserved6: u3,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            padding: u25,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            reserved6: u3,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            reserved9: u2,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            padding: u21,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            reserved6: u3,
+            ///  Trigger generation
+            TG: u1,
+            padding: u25,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            reserved8: u1,
+            ///  Capture/Compare 2 selection
+            CC2S: u2,
+            ///  Output Compare 2 fast enable
+            OC2FE: u1,
+            ///  Output Compare 2 preload enable
+            OC2PE: u1,
+            ///  Output Compare 2 mode
+            OC2M: u3,
+            padding: u17,
+        }),
+        reserved32: [4]u8,
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved7: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            padding: u24,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 2 value
+            CCR2: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Ethernet: media access control (MAC)
+    pub const Ethernet_MAC = extern struct {
+        ///  Ethernet MAC configuration register
+        MACCR: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  RE
+            RE: u1,
+            ///  TE
+            TE: u1,
+            ///  DC
+            DC: u1,
+            ///  BL
+            BL: u2,
+            ///  APCS
+            APCS: u1,
+            reserved9: u1,
+            ///  RD
+            RD: u1,
+            ///  IPCO
+            IPCO: u1,
+            ///  DM
+            DM: u1,
+            ///  LM
+            LM: u1,
+            ///  ROD
+            ROD: u1,
+            ///  FES
+            FES: u1,
+            reserved16: u1,
+            ///  CSD
+            CSD: u1,
+            ///  IFG
+            IFG: u3,
+            reserved22: u2,
+            ///  JD
+            JD: u1,
+            ///  WD
+            WD: u1,
+            reserved25: u1,
+            ///  CSTF
+            CSTF: u1,
+            padding: u6,
+        }),
+        ///  Ethernet MAC frame filter register
+        MACFFR: mmio.Mmio(packed struct(u32) {
+            ///  PM
+            PM: u1,
+            ///  HU
+            HU: u1,
+            ///  HM
+            HM: u1,
+            ///  DAIF
+            DAIF: u1,
+            ///  RAM
+            RAM: u1,
+            ///  BFD
+            BFD: u1,
+            ///  PCF
+            PCF: u1,
+            ///  SAIF
+            SAIF: u1,
+            ///  SAF
+            SAF: u1,
+            ///  HPF
+            HPF: u1,
+            reserved31: u21,
+            ///  RA
+            RA: u1,
+        }),
+        ///  Ethernet MAC hash table high register
+        MACHTHR: mmio.Mmio(packed struct(u32) {
+            ///  HTH
+            HTH: u32,
+        }),
+        ///  Ethernet MAC hash table low register
+        MACHTLR: mmio.Mmio(packed struct(u32) {
+            ///  HTL
+            HTL: u32,
+        }),
+        ///  Ethernet MAC MII address register
+        MACMIIAR: mmio.Mmio(packed struct(u32) {
+            ///  MB
+            MB: u1,
+            ///  MW
+            MW: u1,
+            ///  CR
+            CR: u3,
+            reserved6: u1,
+            ///  MR
+            MR: u5,
+            ///  PA
+            PA: u5,
+            padding: u16,
+        }),
+        ///  Ethernet MAC MII data register
+        MACMIIDR: mmio.Mmio(packed struct(u32) {
+            ///  TD
+            TD: u16,
+            padding: u16,
+        }),
+        ///  Ethernet MAC flow control register
+        MACFCR: mmio.Mmio(packed struct(u32) {
+            ///  FCB
+            FCB: u1,
+            ///  TFCE
+            TFCE: u1,
+            ///  RFCE
+            RFCE: u1,
+            ///  UPFD
+            UPFD: u1,
+            ///  PLT
+            PLT: u2,
+            reserved7: u1,
+            ///  ZQPD
+            ZQPD: u1,
+            reserved16: u8,
+            ///  PT
+            PT: u16,
+        }),
+        ///  Ethernet MAC VLAN tag register
+        MACVLANTR: mmio.Mmio(packed struct(u32) {
+            ///  VLANTI
+            VLANTI: u16,
+            ///  VLANTC
+            VLANTC: u1,
+            padding: u15,
+        }),
+        reserved44: [12]u8,
+        ///  Ethernet MAC PMT control and status register
+        MACPMTCSR: mmio.Mmio(packed struct(u32) {
+            ///  PD
+            PD: u1,
+            ///  MPE
+            MPE: u1,
+            ///  WFE
+            WFE: u1,
+            reserved5: u2,
+            ///  MPR
+            MPR: u1,
+            ///  WFR
+            WFR: u1,
+            reserved9: u2,
+            ///  GU
+            GU: u1,
+            reserved31: u21,
+            ///  WFFRPR
+            WFFRPR: u1,
+        }),
+        reserved52: [4]u8,
+        ///  Ethernet MAC debug register
+        MACDBGR: mmio.Mmio(packed struct(u32) {
+            ///  CR
+            CR: u1,
+            ///  CSR
+            CSR: u1,
+            ///  ROR
+            ROR: u1,
+            ///  MCF
+            MCF: u1,
+            ///  MCP
+            MCP: u1,
+            ///  MCFHP
+            MCFHP: u1,
+            padding: u26,
+        }),
+        ///  Ethernet MAC interrupt status register
+        MACSR: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  PMTS
+            PMTS: u1,
+            ///  MMCS
+            MMCS: u1,
+            ///  MMCRS
+            MMCRS: u1,
+            ///  MMCTS
+            MMCTS: u1,
+            reserved9: u2,
+            ///  TSTS
+            TSTS: u1,
+            padding: u22,
+        }),
+        ///  Ethernet MAC interrupt mask register
+        MACIMR: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  PMTIM
+            PMTIM: u1,
+            reserved9: u5,
+            ///  TSTIM
+            TSTIM: u1,
+            padding: u22,
+        }),
+        ///  Ethernet MAC address 0 high register
+        MACA0HR: mmio.Mmio(packed struct(u32) {
+            ///  MAC address0 high
+            MACA0H: u16,
+            reserved31: u15,
+            ///  Always 1
+            MO: u1,
+        }),
+        ///  Ethernet MAC address 0 low register
+        MACA0LR: mmio.Mmio(packed struct(u32) {
+            ///  0
+            MACA0L: u32,
+        }),
+        ///  Ethernet MAC address 1 high register
+        MACA1HR: mmio.Mmio(packed struct(u32) {
+            ///  MACA1H
+            MACA1H: u16,
+            reserved24: u8,
+            ///  MBC
+            MBC: u6,
+            ///  SA
+            SA: u1,
+            ///  AE
+            AE: u1,
+        }),
+        ///  Ethernet MAC address1 low register
+        MACA1LR: mmio.Mmio(packed struct(u32) {
+            ///  MACA1LR
+            MACA1LR: u32,
+        }),
+        ///  Ethernet MAC address 2 high register
+        MACA2HR: mmio.Mmio(packed struct(u32) {
+            ///  MAC2AH
+            MAC2AH: u16,
+            reserved24: u8,
+            ///  MBC
+            MBC: u6,
+            ///  SA
+            SA: u1,
+            ///  AE
+            AE: u1,
+        }),
+        ///  Ethernet MAC address 2 low register
+        MACA2LR: mmio.Mmio(packed struct(u32) {
+            ///  MACA2L
+            MACA2L: u31,
+            padding: u1,
+        }),
+        ///  Ethernet MAC address 3 high register
+        MACA3HR: mmio.Mmio(packed struct(u32) {
+            ///  MACA3H
+            MACA3H: u16,
+            reserved24: u8,
+            ///  MBC
+            MBC: u6,
+            ///  SA
+            SA: u1,
+            ///  AE
+            AE: u1,
+        }),
+        ///  Ethernet MAC address 3 low register
+        MACA3LR: mmio.Mmio(packed struct(u32) {
+            ///  MBCA3L
+            MBCA3L: u32,
+        }),
+    };
+
+    ///  General-purpose-timers
+    pub const TIM10 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            reserved7: u4,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        reserved12: [8]u8,
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            padding: u30,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            reserved9: u7,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            padding: u22,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            padding: u30,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            padding: u25,
+        }),
+        reserved32: [4]u8,
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            padding: u28,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  General-purpose-timers
+    pub const TIM11 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            reserved7: u4,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        reserved12: [8]u8,
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            padding: u30,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            reserved9: u7,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            padding: u22,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            padding: u30,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            padding: u25,
+        }),
+        reserved32: [4]u8,
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            padding: u28,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        reserved80: [24]u8,
+        ///  option register
+        OR: mmio.Mmio(packed struct(u32) {
+            ///  Input 1 remapping capability
+            RMP: u2,
+            padding: u30,
+        }),
+    };
+};
diff --git a/src/chips/STM32F429.json b/src/chips/STM32F429.json
new file mode 100644
index 000000000..efbd77556
--- /dev/null
+++ b/src/chips/STM32F429.json
@@ -0,0 +1,52094 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "RNG": {
+        "description": "Random number generator",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "Interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RNGEN": {
+                    "description": "Random number generator\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEIS": {
+                    "description": "Seed error interrupt\n              status",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CEIS": {
+                    "description": "Clock error interrupt\n              status",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SECS": {
+                    "description": "Seed error current status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CECS": {
+                    "description": "Clock error current status",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DRDY": {
+                    "description": "Data ready",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "data register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RNDATA": {
+                    "description": "Random data",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "HASH": {
+        "description": "Hash processor",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INIT": {
+                    "description": "Initialize message digest\n              calculation",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DMAE": {
+                    "description": "DMA enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DATATYPE": {
+                    "description": "Data type selection",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MODE": {
+                    "description": "Mode selection",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ALGO0": {
+                    "description": "Algorithm selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "NBW": {
+                    "description": "Number of words already\n              pushed",
+                    "offset": 8,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "DINNE": {
+                    "description": "DIN not empty",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MDMAT": {
+                    "description": "Multiple DMA Transfers",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LKEY": {
+                    "description": "Long key selection",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ALGO1": {
+                    "description": "ALGO",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIN": {
+              "description": "data input register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATAIN": {
+                    "description": "Data input",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STR": {
+              "description": "start register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCAL": {
+                    "description": "Digest calculation",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "NBLW": {
+                    "description": "Number of valid bits in the last word of\n              the message",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "HR0": {
+              "description": "digest registers",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H0": {
+                    "description": "H0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HR1": {
+              "description": "digest registers",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H1": {
+                    "description": "H1",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HR2": {
+              "description": "digest registers",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H2": {
+                    "description": "H2",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HR3": {
+              "description": "digest registers",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H3": {
+                    "description": "H3",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HR4": {
+              "description": "digest registers",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H4": {
+                    "description": "H4",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IMR": {
+              "description": "interrupt enable register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCIE": {
+                    "description": "Digest calculation completion interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DINIE": {
+                    "description": "Data input interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUSY": {
+                    "description": "Busy bit",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DMAS": {
+                    "description": "DMA Status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DCIS": {
+                    "description": "Digest calculation completion interrupt\n              status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DINIS": {
+                    "description": "Data input interrupt\n              status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CSR0": {
+              "description": "context swap registers",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR0": {
+                    "description": "CSR0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR1": {
+              "description": "context swap registers",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR1": {
+                    "description": "CSR1",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR2": {
+              "description": "context swap registers",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR2": {
+                    "description": "CSR2",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR3": {
+              "description": "context swap registers",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR3": {
+                    "description": "CSR3",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR4": {
+              "description": "context swap registers",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR4": {
+                    "description": "CSR4",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR5": {
+              "description": "context swap registers",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR5": {
+                    "description": "CSR5",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR6": {
+              "description": "context swap registers",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR6": {
+                    "description": "CSR6",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR7": {
+              "description": "context swap registers",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR7": {
+                    "description": "CSR7",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR8": {
+              "description": "context swap registers",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR8": {
+                    "description": "CSR8",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR9": {
+              "description": "context swap registers",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR9": {
+                    "description": "CSR9",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR10": {
+              "description": "context swap registers",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR10": {
+                    "description": "CSR10",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR11": {
+              "description": "context swap registers",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR11": {
+                    "description": "CSR11",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR12": {
+              "description": "context swap registers",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR12": {
+                    "description": "CSR12",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR13": {
+              "description": "context swap registers",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR13": {
+                    "description": "CSR13",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR14": {
+              "description": "context swap registers",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR14": {
+                    "description": "CSR14",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR15": {
+              "description": "context swap registers",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR15": {
+                    "description": "CSR15",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR16": {
+              "description": "context swap registers",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR16": {
+                    "description": "CSR16",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR17": {
+              "description": "context swap registers",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR17": {
+                    "description": "CSR17",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR18": {
+              "description": "context swap registers",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR18": {
+                    "description": "CSR18",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR19": {
+              "description": "context swap registers",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR19": {
+                    "description": "CSR19",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR20": {
+              "description": "context swap registers",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR20": {
+                    "description": "CSR20",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR21": {
+              "description": "context swap registers",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR21": {
+                    "description": "CSR21",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR22": {
+              "description": "context swap registers",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR22": {
+                    "description": "CSR22",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR23": {
+              "description": "context swap registers",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR23": {
+                    "description": "CSR23",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR24": {
+              "description": "context swap registers",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR24": {
+                    "description": "CSR24",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR25": {
+              "description": "context swap registers",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR25": {
+                    "description": "CSR25",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR26": {
+              "description": "context swap registers",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR26": {
+                    "description": "CSR26",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR27": {
+              "description": "context swap registers",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR27": {
+                    "description": "CSR27",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR28": {
+              "description": "context swap registers",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR28": {
+                    "description": "CSR28",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR29": {
+              "description": "context swap registers",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR29": {
+                    "description": "CSR29",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR30": {
+              "description": "context swap registers",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR30": {
+                    "description": "CSR30",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR31": {
+              "description": "context swap registers",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR31": {
+                    "description": "CSR31",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR32": {
+              "description": "context swap registers",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR32": {
+                    "description": "CSR32",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR33": {
+              "description": "context swap registers",
+              "offset": 380,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR33": {
+                    "description": "CSR33",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR34": {
+              "description": "context swap registers",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR34": {
+                    "description": "CSR34",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR35": {
+              "description": "context swap registers",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR35": {
+                    "description": "CSR35",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR36": {
+              "description": "context swap registers",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR36": {
+                    "description": "CSR36",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR37": {
+              "description": "context swap registers",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR37": {
+                    "description": "CSR37",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR38": {
+              "description": "context swap registers",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR38": {
+                    "description": "CSR38",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR39": {
+              "description": "context swap registers",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR39": {
+                    "description": "CSR39",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR40": {
+              "description": "context swap registers",
+              "offset": 408,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR40": {
+                    "description": "CSR40",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR41": {
+              "description": "context swap registers",
+              "offset": 412,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR41": {
+                    "description": "CSR41",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR42": {
+              "description": "context swap registers",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR42": {
+                    "description": "CSR42",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR43": {
+              "description": "context swap registers",
+              "offset": 420,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR43": {
+                    "description": "CSR43",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR44": {
+              "description": "context swap registers",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR44": {
+                    "description": "CSR44",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR45": {
+              "description": "context swap registers",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR45": {
+                    "description": "CSR45",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR46": {
+              "description": "context swap registers",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR46": {
+                    "description": "CSR46",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR47": {
+              "description": "context swap registers",
+              "offset": 436,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR47": {
+                    "description": "CSR47",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR48": {
+              "description": "context swap registers",
+              "offset": 440,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR48": {
+                    "description": "CSR48",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR49": {
+              "description": "context swap registers",
+              "offset": 444,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR49": {
+                    "description": "CSR49",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR50": {
+              "description": "context swap registers",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR50": {
+                    "description": "CSR50",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR51": {
+              "description": "context swap registers",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR51": {
+                    "description": "CSR51",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR52": {
+              "description": "context swap registers",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR52": {
+                    "description": "CSR52",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSR53": {
+              "description": "context swap registers",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSR53": {
+                    "description": "CSR53",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR0": {
+              "description": "HASH digest register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H0": {
+                    "description": "H0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR1": {
+              "description": "read-only",
+              "offset": 788,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H1": {
+                    "description": "H1",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR2": {
+              "description": "read-only",
+              "offset": 792,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H2": {
+                    "description": "H2",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR3": {
+              "description": "read-only",
+              "offset": 796,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H3": {
+                    "description": "H3",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR4": {
+              "description": "read-only",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H4": {
+                    "description": "H4",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR5": {
+              "description": "read-only",
+              "offset": 804,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H5": {
+                    "description": "H5",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR6": {
+              "description": "read-only",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H6": {
+                    "description": "H6",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASH_HR7": {
+              "description": "read-only",
+              "offset": 812,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "H7": {
+                    "description": "H7",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CRYP": {
+        "description": "Cryptographic processor",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ALGODIR": {
+                    "description": "Algorithm direction",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ALGOMODE0": {
+                    "description": "Algorithm mode",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "DATATYPE": {
+                    "description": "Data type selection",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "KEYSIZE": {
+                    "description": "Key size selection (AES mode\n              only)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "FFLUSH": {
+                    "description": "FIFO flush",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CRYPEN": {
+                    "description": "Cryptographic processor\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GCM_CCMPH": {
+                    "description": "GCM_CCMPH",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "ALGOMODE3": {
+                    "description": "ALGOMODE",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "BUSY": {
+                    "description": "Busy bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OFFU": {
+                    "description": "Output FIFO full",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OFNE": {
+                    "description": "Output FIFO not empty",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IFNF": {
+                    "description": "Input FIFO not full",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IFEM": {
+                    "description": "Input FIFO empty",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIN": {
+              "description": "data input register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATAIN": {
+                    "description": "Data input",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DOUT": {
+              "description": "data output register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATAOUT": {
+                    "description": "Data output",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMACR": {
+              "description": "DMA control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DOEN": {
+                    "description": "DMA output enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DIEN": {
+                    "description": "DMA input enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IMSCR": {
+              "description": "interrupt mask set/clear\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTIM": {
+                    "description": "Output FIFO service interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INIM": {
+                    "description": "Input FIFO service interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RISR": {
+              "description": "raw interrupt status register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "OUTRIS": {
+                    "description": "Output FIFO service raw interrupt\n              status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INRIS": {
+                    "description": "Input FIFO service raw interrupt\n              status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MISR": {
+              "description": "masked interrupt status\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "OUTMIS": {
+                    "description": "Output FIFO service masked interrupt\n              status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INMIS": {
+                    "description": "Input FIFO service masked interrupt\n              status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "K0LR": {
+              "description": "key registers",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "b224": {
+                    "description": "b224",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "b225": {
+                    "description": "b225",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "b226": {
+                    "description": "b226",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "b227": {
+                    "description": "b227",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "b228": {
+                    "description": "b228",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "b229": {
+                    "description": "b229",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "b230": {
+                    "description": "b230",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "b231": {
+                    "description": "b231",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "b232": {
+                    "description": "b232",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "b233": {
+                    "description": "b233",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "b234": {
+                    "description": "b234",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "b235": {
+                    "description": "b235",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "b236": {
+                    "description": "b236",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "b237": {
+                    "description": "b237",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "b238": {
+                    "description": "b238",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "b239": {
+                    "description": "b239",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "b240": {
+                    "description": "b240",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "b241": {
+                    "description": "b241",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "b242": {
+                    "description": "b242",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "b243": {
+                    "description": "b243",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "b244": {
+                    "description": "b244",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "b245": {
+                    "description": "b245",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "b246": {
+                    "description": "b246",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "b247": {
+                    "description": "b247",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "b248": {
+                    "description": "b248",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "b249": {
+                    "description": "b249",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "b250": {
+                    "description": "b250",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "b251": {
+                    "description": "b251",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "b252": {
+                    "description": "b252",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "b253": {
+                    "description": "b253",
+                    "offset": 29,
+                    "size": 1
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+              }
+            },
+            "CSGCMCCM2R": {
+              "description": "context swap register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM2R": {
+                    "description": "CSGCMCCM2R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM3R": {
+              "description": "context swap register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM3R": {
+                    "description": "CSGCMCCM3R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM4R": {
+              "description": "context swap register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM4R": {
+                    "description": "CSGCMCCM4R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM5R": {
+              "description": "context swap register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM5R": {
+                    "description": "CSGCMCCM5R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM6R": {
+              "description": "context swap register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM6R": {
+                    "description": "CSGCMCCM6R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCMCCM7R": {
+              "description": "context swap register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCMCCM7R": {
+                    "description": "CSGCMCCM7R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM0R": {
+              "description": "context swap register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM0R": {
+                    "description": "CSGCM0R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM1R": {
+              "description": "context swap register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM1R": {
+                    "description": "CSGCM1R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM2R": {
+              "description": "context swap register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM2R": {
+                    "description": "CSGCM2R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM3R": {
+              "description": "context swap register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM3R": {
+                    "description": "CSGCM3R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM4R": {
+              "description": "context swap register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM4R": {
+                    "description": "CSGCM4R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM5R": {
+              "description": "context swap register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM5R": {
+                    "description": "CSGCM5R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM6R": {
+              "description": "context swap register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM6R": {
+                    "description": "CSGCM6R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CSGCM7R": {
+              "description": "context swap register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSGCM7R": {
+                    "description": "CSGCM7R",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DCMI": {
+        "description": "Digital camera interface",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "DCMI enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EDM": {
+                    "description": "Extended data mode",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "FCRC": {
+                    "description": "Frame capture rate control",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "VSPOL": {
+                    "description": "Vertical synchronization\n              polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "HSPOL": {
+                    "description": "Horizontal synchronization\n              polarity",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PCKPOL": {
+                    "description": "Pixel clock polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ESS": {
+                    "description": "Embedded synchronization\n              select",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "JPEG": {
+                    "description": "JPEG format",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CROP": {
+                    "description": "Crop feature",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CM": {
+                    "description": "Capture mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CAPTURE": {
+                    "description": "Capture enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FNE": {
+                    "description": "FIFO not empty",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "VSYNC": {
+                    "description": "VSYNC",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HSYNC": {
+                    "description": "HSYNC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RIS": {
+              "description": "raw interrupt status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "LINE_RIS": {
+                    "description": "Line raw interrupt status",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "VSYNC_RIS": {
+                    "description": "VSYNC raw interrupt status",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_RIS": {
+                    "description": "Synchronization error raw interrupt\n              status",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OVR_RIS": {
+                    "description": "Overrun raw interrupt\n              status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FRAME_RIS": {
+                    "description": "Capture complete raw interrupt\n              status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LINE_IE": {
+                    "description": "Line interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "VSYNC_IE": {
+                    "description": "VSYNC interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_IE": {
+                    "description": "Synchronization error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OVR_IE": {
+                    "description": "Overrun interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FRAME_IE": {
+                    "description": "Capture complete interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MIS": {
+              "description": "masked interrupt status\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "LINE_MIS": {
+                    "description": "Line masked interrupt\n              status",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "VSYNC_MIS": {
+                    "description": "VSYNC masked interrupt\n              status",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_MIS": {
+                    "description": "Synchronization error masked interrupt\n              status",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OVR_MIS": {
+                    "description": "Overrun masked interrupt\n              status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FRAME_MIS": {
+                    "description": "Capture complete masked interrupt\n              status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "interrupt clear register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "LINE_ISC": {
+                    "description": "line interrupt status\n              clear",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "VSYNC_ISC": {
+                    "description": "Vertical synch interrupt status\n              clear",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_ISC": {
+                    "description": "Synchronization error interrupt status\n              clear",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OVR_ISC": {
+                    "description": "Overrun interrupt status\n              clear",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FRAME_ISC": {
+                    "description": "Capture complete interrupt status\n              clear",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ESCR": {
+              "description": "embedded synchronization code\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEC": {
+                    "description": "Frame end delimiter code",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "LEC": {
+                    "description": "Line end delimiter code",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "LSC": {
+                    "description": "Line start delimiter code",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "FSC": {
+                    "description": "Frame start delimiter code",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ESUR": {
+              "description": "embedded synchronization unmask\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEU": {
+                    "description": "Frame end delimiter unmask",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "LEU": {
+                    "description": "Line end delimiter unmask",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "LSU": {
+                    "description": "Line start delimiter\n              unmask",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "FSU": {
+                    "description": "Frame start delimiter\n              unmask",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CWSTRT": {
+              "description": "crop window start",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VST": {
+                    "description": "Vertical start line count",
+                    "offset": 16,
+                    "size": 13
+                  },
+                  "HOFFCNT": {
+                    "description": "Horizontal offset count",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "CWSIZE": {
+              "description": "crop window size",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VLINE": {
+                    "description": "Vertical line count",
+                    "offset": 16,
+                    "size": 14
+                  },
+                  "CAPCNT": {
+                    "description": "Capture count",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "data register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "Byte3": {
+                    "description": "Data byte 3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "Byte2": {
+                    "description": "Data byte 2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "Byte1": {
+                    "description": "Data byte 1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "Byte0": {
+                    "description": "Data byte 0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FMC": {
+        "description": "Flexible memory controller",
+        "children": {
+          "registers": {
+            "BCR1": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCLKEN": {
+                    "description": "CCLKEN",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR1": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR2": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          2",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR2": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR3": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          3",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR3": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BCR4": {
+              "description": "SRAM/NOR-Flash chip-select control register\n          4",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 12496,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CBURSTRW": {
+                    "description": "CBURSTRW",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ASYNCWAIT": {
+                    "description": "ASYNCWAIT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EXTMOD": {
+                    "description": "EXTMOD",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WAITEN": {
+                    "description": "WAITEN",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "WREN",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAITCFG": {
+                    "description": "WAITCFG",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WRAPMOD": {
+                    "description": "WRAPMOD",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPOL": {
+                    "description": "WAITPOL",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BURSTEN": {
+                    "description": "BURSTEN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACCEN": {
+                    "description": "FACCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MWID": {
+                    "description": "MWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MTYP": {
+                    "description": "MTYP",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MUXEN": {
+                    "description": "MUXEN",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MBKEN": {
+                    "description": "MBKEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BTR4": {
+              "description": "SRAM/NOR-Flash chip-select timing register\n          4",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "BUSTURN": {
+                    "description": "BUSTURN",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "PCR2": {
+              "description": "PC Card/NAND Flash control register\n          2",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR2": {
+              "description": "FIFO status and interrupt register\n          2",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM2": {
+              "description": "Common memory space timing register\n          2",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT2": {
+              "description": "Attribute memory space timing register\n          2",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "ATTHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "ATTHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "ATTWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "ATTSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ECCR2": {
+              "description": "ECC result register 2",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ECCx": {
+                    "description": "ECCx",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PCR3": {
+              "description": "PC Card/NAND Flash control register\n          3",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR3": {
+              "description": "FIFO status and interrupt register\n          3",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM3": {
+              "description": "Common memory space timing register\n          3",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT3": {
+              "description": "Attribute memory space timing register\n          3",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "ATTHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "ATTHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "ATTWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "ATTSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ECCR3": {
+              "description": "ECC result register 3",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ECCx": {
+                    "description": "ECCx",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PCR4": {
+              "description": "PC Card/NAND Flash control register\n          4",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECCPS": {
+                    "description": "ECCPS",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "TAR": {
+                    "description": "TAR",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "TCLR": {
+                    "description": "TCLR",
+                    "offset": 9,
+                    "size": 4
+                  },
+                  "ECCEN": {
+                    "description": "ECCEN",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PWID": {
+                    "description": "PWID",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PTYP": {
+                    "description": "PTYP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PBKEN": {
+                    "description": "PBKEN",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWAITEN": {
+                    "description": "PWAITEN",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR4": {
+              "description": "FIFO status and interrupt register\n          4",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEMPT": {
+                    "description": "FEMPT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IFEN": {
+                    "description": "IFEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ILEN": {
+                    "description": "ILEN",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IREN",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IFS": {
+                    "description": "IFS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ILS": {
+                    "description": "ILS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IRS": {
+                    "description": "IRS",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PMEM4": {
+              "description": "Common memory space timing register\n          4",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMHIZx": {
+                    "description": "MEMHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "MEMHOLDx": {
+                    "description": "MEMHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "MEMWAITx": {
+                    "description": "MEMWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "MEMSETx": {
+                    "description": "MEMSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PATT4": {
+              "description": "Attribute memory space timing register\n          4",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ATTHIZx": {
+                    "description": "ATTHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "ATTHOLDx": {
+                    "description": "ATTHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "ATTWAITx": {
+                    "description": "ATTWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ATTSETx": {
+                    "description": "ATTSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PIO4": {
+              "description": "I/O space timing register 4",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 4244438268,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOHIZx": {
+                    "description": "IOHIZx",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "IOHOLDx": {
+                    "description": "IOHOLDx",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IOWAITx": {
+                    "description": "IOWAITx",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IOSETx": {
+                    "description": "IOSETx",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BWTR1": {
+              "description": "SRAM/NOR-Flash write timing registers\n          1",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR2": {
+              "description": "SRAM/NOR-Flash write timing registers\n          2",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR3": {
+              "description": "SRAM/NOR-Flash write timing registers\n          3",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BWTR4": {
+              "description": "SRAM/NOR-Flash write timing registers\n          4",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACCMOD": {
+                    "description": "ACCMOD",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DATLAT": {
+                    "description": "DATLAT",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "CLKDIV": {
+                    "description": "CLKDIV",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "DATAST": {
+                    "description": "DATAST",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "ADDHLD": {
+                    "description": "ADDHLD",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ADDSET": {
+                    "description": "ADDSET",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SDCR1": {
+              "description": "SDRAM Control Register 1",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 720,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NC": {
+                    "description": "Number of column address\n              bits",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "NR": {
+                    "description": "Number of row address bits",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MWID": {
+                    "description": "Memory data bus width",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "NB": {
+                    "description": "Number of internal banks",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CAS": {
+                    "description": "CAS latency",
+                    "offset": 7,
+                    "size": 2
+                  },
+                  "WP": {
+                    "description": "Write protection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SDCLK": {
+                    "description": "SDRAM clock configuration",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "RBURST": {
+                    "description": "Burst read",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RPIPE": {
+                    "description": "Read pipe",
+                    "offset": 13,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "SDCR2": {
+              "description": "SDRAM Control Register 2",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 720,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NC": {
+                    "description": "Number of column address\n              bits",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "NR": {
+                    "description": "Number of row address bits",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MWID": {
+                    "description": "Memory data bus width",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "NB": {
+                    "description": "Number of internal banks",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CAS": {
+                    "description": "CAS latency",
+                    "offset": 7,
+                    "size": 2
+                  },
+                  "WP": {
+                    "description": "Write protection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SDCLK": {
+                    "description": "SDRAM clock configuration",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "RBURST": {
+                    "description": "Burst read",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RPIPE": {
+                    "description": "Read pipe",
+                    "offset": 13,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "SDTR1": {
+              "description": "SDRAM Timing register 1",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TMRD": {
+                    "description": "Load Mode Register to\n              Active",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "TXSR": {
+                    "description": "Exit self-refresh delay",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "TRAS": {
+                    "description": "Self refresh time",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "TRC": {
+                    "description": "Row cycle delay",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "TWR": {
+                    "description": "Recovery delay",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "TRP": {
+                    "description": "Row precharge delay",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "TRCD": {
+                    "description": "Row to column delay",
+                    "offset": 24,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SDTR2": {
+              "description": "SDRAM Timing register 2",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TMRD": {
+                    "description": "Load Mode Register to\n              Active",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "TXSR": {
+                    "description": "Exit self-refresh delay",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "TRAS": {
+                    "description": "Self refresh time",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "TRC": {
+                    "description": "Row cycle delay",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "TWR": {
+                    "description": "Recovery delay",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "TRP": {
+                    "description": "Row precharge delay",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "TRCD": {
+                    "description": "Row to column delay",
+                    "offset": 24,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SDCMR": {
+              "description": "SDRAM Command Mode register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Command mode",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "write-only"
+                  },
+                  "CTB2": {
+                    "description": "Command target bank 2",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CTB1": {
+                    "description": "Command target bank 1",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "NRFS": {
+                    "description": "Number of Auto-refresh",
+                    "offset": 5,
+                    "size": 4
+                  },
+                  "MRD": {
+                    "description": "Mode Register definition",
+                    "offset": 9,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "SDRTR": {
+              "description": "SDRAM Refresh Timer register",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRE": {
+                    "description": "Clear Refresh error flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "COUNT": {
+                    "description": "Refresh Timer Count",
+                    "offset": 1,
+                    "size": 13
+                  },
+                  "REIE": {
+                    "description": "RES Interrupt Enable",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SDSR": {
+              "description": "SDRAM Status register",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RE": {
+                    "description": "Refresh error flag",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MODES1": {
+                    "description": "Status Mode for Bank 1",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "MODES2": {
+                    "description": "Status Mode for Bank 2",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "BUSY": {
+                    "description": "Busy status",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DBG": {
+        "description": "Debug support",
+        "children": {
+          "registers": {
+            "DBGMCU_IDCODE": {
+              "description": "IDCODE",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 268461073,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DEV_ID": {
+                    "description": "DEV_ID",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "REV_ID": {
+                    "description": "REV_ID",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DBGMCU_CR": {
+              "description": "Control Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBG_SLEEP": {
+                    "description": "DBG_SLEEP",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DBG_STOP": {
+                    "description": "DBG_STOP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DBG_STANDBY": {
+                    "description": "DBG_STANDBY",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TRACE_IOEN": {
+                    "description": "TRACE_IOEN",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TRACE_MODE": {
+                    "description": "TRACE_MODE",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DBGMCU_APB1_FZ": {
+              "description": "Debug MCU APB1 Freeze registe",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBG_TIM2_STOP": {
+                    "description": "DBG_TIM2_STOP",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DBG_TIM3_STOP": {
+                    "description": "DBG_TIM3 _STOP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DBG_TIM4_STOP": {
+                    "description": "DBG_TIM4_STOP",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DBG_TIM5_STOP": {
+                    "description": "DBG_TIM5_STOP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DBG_TIM6_STOP": {
+                    "description": "DBG_TIM6_STOP",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DBG_TIM7_STOP": {
+                    "description": "DBG_TIM7_STOP",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DBG_TIM12_STOP": {
+                    "description": "DBG_TIM12_STOP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DBG_TIM13_STOP": {
+                    "description": "DBG_TIM13_STOP",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DBG_TIM14_STOP": {
+                    "description": "DBG_TIM14_STOP",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DBG_WWDG_STOP": {
+                    "description": "DBG_WWDG_STOP",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DBG_IWDEG_STOP": {
+                    "description": "DBG_IWDEG_STOP",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DBG_J2C1_SMBUS_TIMEOUT": {
+                    "description": "DBG_J2C1_SMBUS_TIMEOUT",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "DBG_J2C2_SMBUS_TIMEOUT": {
+                    "description": "DBG_J2C2_SMBUS_TIMEOUT",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DBG_J2C3SMBUS_TIMEOUT": {
+                    "description": "DBG_J2C3SMBUS_TIMEOUT",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "DBG_CAN1_STOP": {
+                    "description": "DBG_CAN1_STOP",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DBG_CAN2_STOP": {
+                    "description": "DBG_CAN2_STOP",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DBGMCU_APB2_FZ": {
+              "description": "Debug MCU APB2 Freeze registe",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBG_TIM1_STOP": {
+                    "description": "TIM1 counter stopped when core is\n              halted",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DBG_TIM8_STOP": {
+                    "description": "TIM8 counter stopped when core is\n              halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DBG_TIM9_STOP": {
+                    "description": "TIM9 counter stopped when core is\n              halted",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DBG_TIM10_STOP": {
+                    "description": "TIM10 counter stopped when core is\n              halted",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "DBG_TIM11_STOP": {
+                    "description": "TIM11 counter stopped when core is\n              halted",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DMA2": {
+        "description": "DMA controller",
+        "children": {
+          "registers": {
+            "LISR": {
+              "description": "low interrupt status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TCIF3": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x = 3..0)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "HTIF3": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=3..0)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TEIF3": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=3..0)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DMEIF3": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=3..0)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FEIF3": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=3..0)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TCIF2": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x = 3..0)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HTIF2": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=3..0)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TEIF2": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=3..0)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DMEIF2": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=3..0)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FEIF2": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=3..0)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TCIF1": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x = 3..0)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "HTIF1": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=3..0)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TEIF1": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=3..0)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DMEIF1": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=3..0)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FEIF1": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=3..0)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TCIF0": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x = 3..0)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HTIF0": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=3..0)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TEIF0": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=3..0)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DMEIF0": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=3..0)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FEIF0": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=3..0)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HISR": {
+              "description": "high interrupt status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TCIF7": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x=7..4)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "HTIF7": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=7..4)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TEIF7": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=7..4)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DMEIF7": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=7..4)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FEIF7": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=7..4)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TCIF6": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x=7..4)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HTIF6": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=7..4)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TEIF6": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=7..4)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DMEIF6": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=7..4)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FEIF6": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=7..4)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TCIF5": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x=7..4)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "HTIF5": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=7..4)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TEIF5": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=7..4)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DMEIF5": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=7..4)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FEIF5": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=7..4)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TCIF4": {
+                    "description": "Stream x transfer complete interrupt\n              flag (x=7..4)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HTIF4": {
+                    "description": "Stream x half transfer interrupt flag\n              (x=7..4)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TEIF4": {
+                    "description": "Stream x transfer error interrupt flag\n              (x=7..4)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DMEIF4": {
+                    "description": "Stream x direct mode error interrupt\n              flag (x=7..4)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FEIF4": {
+                    "description": "Stream x FIFO error interrupt flag\n              (x=7..4)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LIFCR": {
+              "description": "low interrupt flag clear\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTCIF3": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 3..0)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "CHTIF3": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 3..0)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CTEIF3": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 3..0)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CDMEIF3": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 3..0)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "CFEIF3": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 3..0)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CTCIF2": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 3..0)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CHTIF2": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 3..0)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CTEIF2": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 3..0)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "CDMEIF2": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 3..0)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CFEIF2": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 3..0)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CTCIF1": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 3..0)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CHTIF1": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 3..0)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CTEIF1": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 3..0)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CDMEIF1": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 3..0)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CFEIF1": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 3..0)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTCIF0": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 3..0)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CHTIF0": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 3..0)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CTEIF0": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 3..0)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CDMEIF0": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 3..0)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CFEIF0": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 3..0)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HIFCR": {
+              "description": "high interrupt flag clear\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTCIF7": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 7..4)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "CHTIF7": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 7..4)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CTEIF7": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 7..4)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CDMEIF7": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 7..4)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "CFEIF7": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 7..4)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CTCIF6": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 7..4)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CHTIF6": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 7..4)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CTEIF6": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 7..4)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "CDMEIF6": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 7..4)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CFEIF6": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 7..4)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CTCIF5": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 7..4)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CHTIF5": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 7..4)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CTEIF5": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 7..4)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CDMEIF5": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 7..4)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CFEIF5": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 7..4)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CTCIF4": {
+                    "description": "Stream x clear transfer complete\n              interrupt flag (x = 7..4)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CHTIF4": {
+                    "description": "Stream x clear half transfer interrupt\n              flag (x = 7..4)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CTEIF4": {
+                    "description": "Stream x clear transfer error interrupt\n              flag (x = 7..4)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CDMEIF4": {
+                    "description": "Stream x clear direct mode error\n              interrupt flag (x = 7..4)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CFEIF4": {
+                    "description": "Stream x clear FIFO error interrupt flag\n              (x = 7..4)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S0CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S0NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S0PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S0M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S0M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S0FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S1CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S1NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S1PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S1M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S1M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S1FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S2CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S2NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S2PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S2M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S2M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S2FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S3CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S3NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S3PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S3M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S3M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S3FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S4CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S4NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S4PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S4M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S4M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S4FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S5CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S5NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S5PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S5M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S5M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S5FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S6CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S6NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S6PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S6M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S6M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S6FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "S7CR": {
+              "description": "stream x configuration\n          register",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHSEL": {
+                    "description": "Channel selection",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "MBURST": {
+                    "description": "Memory burst transfer\n              configuration",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "PBURST": {
+                    "description": "Peripheral burst transfer\n              configuration",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "ACK": {
+                    "description": "ACK",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CT": {
+                    "description": "Current target (only in double buffer\n              mode)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DBM": {
+                    "description": "Double buffer mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PL": {
+                    "description": "Priority level",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PINCOS": {
+                    "description": "Peripheral increment offset\n              size",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MSIZE": {
+                    "description": "Memory data size",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "PSIZE": {
+                    "description": "Peripheral data size",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "MINC": {
+                    "description": "Memory increment mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PINC": {
+                    "description": "Peripheral increment mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CIRC": {
+                    "description": "Circular mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Data transfer direction",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PFCTRL": {
+                    "description": "Peripheral flow controller",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HTIE": {
+                    "description": "Half transfer interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMEIE": {
+                    "description": "Direct mode error interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Stream enable / flag stream ready when\n              read low",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "S7NDTR": {
+              "description": "stream x number of data\n          register",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NDT": {
+                    "description": "Number of data items to\n              transfer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "S7PAR": {
+              "description": "stream x peripheral address\n          register",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PA": {
+                    "description": "Peripheral address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S7M0AR": {
+              "description": "stream x memory 0 address\n          register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M0A": {
+                    "description": "Memory 0 address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S7M1AR": {
+              "description": "stream x memory 1 address\n          register",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M1A": {
+                    "description": "Memory 1 address (used in case of Double\n              buffer mode)",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "S7FCR": {
+              "description": "stream x FIFO control register",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FEIE": {
+                    "description": "FIFO error interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS": {
+                    "description": "FIFO status",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DMDIS": {
+                    "description": "Direct mode disable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SCB_ACTRL": {
+        "description": "System control block ACTLR",
+        "children": {
+          "registers": {
+            "ACTRL": {
+              "description": "Auxiliary control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DISMCYCINT": {
+                    "description": "DISMCYCINT",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DISDEFWBUF": {
+                    "description": "DISDEFWBUF",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DISFOLD": {
+                    "description": "DISFOLD",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DISFPCA": {
+                    "description": "DISFPCA",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DISOOFP": {
+                    "description": "DISOOFP",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RCC": {
+        "description": "Reset and clock control",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "clock control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 131,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PLLI2SRDY": {
+                    "description": "PLLI2S clock ready flag",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLLI2SON": {
+                    "description": "PLLI2S enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PLLRDY": {
+                    "description": "Main PLL (PLL) clock ready\n              flag",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLLON": {
+                    "description": "Main PLL (PLL) enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "CSSON": {
+                    "description": "Clock security system\n              enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "HSEBYP": {
+                    "description": "HSE clock bypass",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "HSERDY": {
+                    "description": "HSE clock ready flag",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSEON": {
+                    "description": "HSE clock enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "HSICAL": {
+                    "description": "Internal high-speed clock\n              calibration",
+                    "offset": 8,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "HSITRIM": {
+                    "description": "Internal high-speed clock\n              trimming",
+                    "offset": 3,
+                    "size": 5
+                  },
+                  "HSIRDY": {
+                    "description": "Internal high-speed clock ready\n              flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSION": {
+                    "description": "Internal high-speed clock\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PLLCFGR": {
+              "description": "PLL configuration register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 603992080,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PLLQ3": {
+                    "description": "Main PLL (PLL) division factor for USB\n              OTG FS, SDIO and random number generator\n              clocks",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PLLQ2": {
+                    "description": "Main PLL (PLL) division factor for USB\n              OTG FS, SDIO and random number generator\n              clocks",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PLLQ1": {
+                    "description": "Main PLL (PLL) division factor for USB\n              OTG FS, SDIO and random number generator\n              clocks",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PLLQ0": {
+                    "description": "Main PLL (PLL) division factor for USB\n              OTG FS, SDIO and random number generator\n              clocks",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PLLSRC": {
+                    "description": "Main PLL(PLL) and audio PLL (PLLI2S)\n              entry clock source",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PLLP1": {
+                    "description": "Main PLL (PLL) division factor for main\n              system clock",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PLLP0": {
+                    "description": "Main PLL (PLL) division factor for main\n              system clock",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PLLN8": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PLLN7": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PLLN6": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PLLN5": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PLLN4": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PLLN3": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PLLN2": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PLLN1": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PLLN0": {
+                    "description": "Main PLL (PLL) multiplication factor for\n              VCO",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PLLM5": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PLLM4": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PLLM3": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PLLM2": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PLLM1": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PLLM0": {
+                    "description": "Division factor for the main PLL (PLL)\n              and audio PLL (PLLI2S) input clock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CFGR": {
+              "description": "clock configuration register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCO2": {
+                    "description": "Microcontroller clock output\n              2",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MCO2PRE": {
+                    "description": "MCO2 prescaler",
+                    "offset": 27,
+                    "size": 3
+                  },
+                  "MCO1PRE": {
+                    "description": "MCO1 prescaler",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "I2SSRC": {
+                    "description": "I2S clock selection",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "MCO1": {
+                    "description": "Microcontroller clock output\n              1",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "RTCPRE": {
+                    "description": "HSE division factor for RTC\n              clock",
+                    "offset": 16,
+                    "size": 5
+                  },
+                  "PPRE2": {
+                    "description": "APB high-speed prescaler\n              (APB2)",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "PPRE1": {
+                    "description": "APB Low speed prescaler\n              (APB1)",
+                    "offset": 10,
+                    "size": 3
+                  },
+                  "HPRE": {
+                    "description": "AHB prescaler",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "SWS1": {
+                    "description": "System clock switch status",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SWS0": {
+                    "description": "System clock switch status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SW1": {
+                    "description": "System clock switch",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SW0": {
+                    "description": "System clock switch",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CIR": {
+              "description": "clock interrupt register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSSC": {
+                    "description": "Clock security system interrupt\n              clear",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PLLI2SRDYC": {
+                    "description": "PLLI2S ready interrupt\n              clear",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PLLRDYC": {
+                    "description": "Main PLL(PLL) ready interrupt\n              clear",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "HSERDYC": {
+                    "description": "HSE ready interrupt clear",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "HSIRDYC": {
+                    "description": "HSI ready interrupt clear",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSERDYC": {
+                    "description": "LSE ready interrupt clear",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSIRDYC": {
+                    "description": "LSI ready interrupt clear",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PLLI2SRDYIE": {
+                    "description": "PLLI2S ready interrupt\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PLLRDYIE": {
+                    "description": "Main PLL (PLL) ready interrupt\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "HSERDYIE": {
+                    "description": "HSE ready interrupt enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "HSIRDYIE": {
+                    "description": "HSI ready interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LSERDYIE": {
+                    "description": "LSE ready interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LSIRDYIE": {
+                    "description": "LSI ready interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CSSF": {
+                    "description": "Clock security system interrupt\n              flag",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLLI2SRDYF": {
+                    "description": "PLLI2S ready interrupt\n              flag",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLLRDYF": {
+                    "description": "Main PLL (PLL) ready interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSERDYF": {
+                    "description": "HSE ready interrupt flag",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HSIRDYF": {
+                    "description": "HSI ready interrupt flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSERDYF": {
+                    "description": "LSE ready interrupt flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSIRDYF": {
+                    "description": "LSI ready interrupt flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "AHB1RSTR": {
+              "description": "AHB1 peripheral reset register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OTGHSRST": {
+                    "description": "USB OTG HS module reset",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ETHMACRST": {
+                    "description": "Ethernet MAC reset",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DMA2RST": {
+                    "description": "DMA2 reset",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DMA1RST": {
+                    "description": "DMA2 reset",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CRCRST": {
+                    "description": "CRC reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIOIRST": {
+                    "description": "IO port I reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIOHRST": {
+                    "description": "IO port H reset",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIOGRST": {
+                    "description": "IO port G reset",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIOFRST": {
+                    "description": "IO port F reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIOERST": {
+                    "description": "IO port E reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIODRST": {
+                    "description": "IO port D reset",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIOCRST": {
+                    "description": "IO port C reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIOBRST": {
+                    "description": "IO port B reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIOARST": {
+                    "description": "IO port A reset",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB2RSTR": {
+              "description": "AHB2 peripheral reset register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OTGFSRST": {
+                    "description": "USB OTG FS module reset",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RNGRST": {
+                    "description": "Random number generator module\n              reset",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "HSAHRST": {
+                    "description": "Hash module reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CRYPRST": {
+                    "description": "Cryptographic module reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DCMIRST": {
+                    "description": "Camera interface reset",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB3RSTR": {
+              "description": "AHB3 peripheral reset register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FMCRST": {
+                    "description": "Flexible memory controller module\n              reset",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1RSTR": {
+              "description": "APB1 peripheral reset register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM2RST": {
+                    "description": "TIM2 reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM3RST": {
+                    "description": "TIM3 reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM4RST": {
+                    "description": "TIM4 reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIM5RST": {
+                    "description": "TIM5 reset",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TIM6RST": {
+                    "description": "TIM6 reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM7RST": {
+                    "description": "TIM7 reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIM12RST": {
+                    "description": "TIM12 reset",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TIM13RST": {
+                    "description": "TIM13 reset",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIM14RST": {
+                    "description": "TIM14 reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WWDGRST": {
+                    "description": "Window watchdog reset",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI2RST": {
+                    "description": "SPI 2 reset",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI3RST": {
+                    "description": "SPI 3 reset",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "UART2RST": {
+                    "description": "USART 2 reset",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "UART3RST": {
+                    "description": "USART 3 reset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "UART4RST": {
+                    "description": "USART 4 reset",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UART5RST": {
+                    "description": "USART 5 reset",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2C1RST": {
+                    "description": "I2C 1 reset",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "I2C2RST": {
+                    "description": "I2C 2 reset",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "I2C3RST": {
+                    "description": "I2C3 reset",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CAN1RST": {
+                    "description": "CAN1 reset",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CAN2RST": {
+                    "description": "CAN2 reset",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PWRRST": {
+                    "description": "Power interface reset",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DACRST": {
+                    "description": "DAC reset",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB2RSTR": {
+              "description": "APB2 peripheral reset register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM1RST": {
+                    "description": "TIM1 reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM8RST": {
+                    "description": "TIM8 reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "USART1RST": {
+                    "description": "USART1 reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "USART6RST": {
+                    "description": "USART6 reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADCRST": {
+                    "description": "ADC interface reset (common to all\n              ADCs)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SDIORST": {
+                    "description": "SDIO reset",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI1RST": {
+                    "description": "SPI 1 reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SYSCFGRST": {
+                    "description": "System configuration controller\n              reset",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TIM9RST": {
+                    "description": "TIM9 reset",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TIM10RST": {
+                    "description": "TIM10 reset",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TIM11RST": {
+                    "description": "TIM11 reset",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB1ENR": {
+              "description": "AHB1 peripheral clock register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 1048576,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OTGHSULPIEN": {
+                    "description": "USB OTG HSULPI clock\n              enable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "OTGHSEN": {
+                    "description": "USB OTG HS clock enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ETHMACPTPEN": {
+                    "description": "Ethernet PTP clock enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ETHMACRXEN": {
+                    "description": "Ethernet Reception clock\n              enable",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "ETHMACTXEN": {
+                    "description": "Ethernet Transmission clock\n              enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "ETHMACEN": {
+                    "description": "Ethernet MAC clock enable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DMA2EN": {
+                    "description": "DMA2 clock enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DMA1EN": {
+                    "description": "DMA1 clock enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CCMDATARAMEN": {
+                    "description": "CCM data RAM clock enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BKPSRAMEN": {
+                    "description": "Backup SRAM interface clock\n              enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CRCEN": {
+                    "description": "CRC clock enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIOIEN": {
+                    "description": "IO port I clock enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIOHEN": {
+                    "description": "IO port H clock enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIOGEN": {
+                    "description": "IO port G clock enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIOFEN": {
+                    "description": "IO port F clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIOEEN": {
+                    "description": "IO port E clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIODEN": {
+                    "description": "IO port D clock enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIOCEN": {
+                    "description": "IO port C clock enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIOBEN": {
+                    "description": "IO port B clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIOAEN": {
+                    "description": "IO port A clock enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB2ENR": {
+              "description": "AHB2 peripheral clock enable\n          register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OTGFSEN": {
+                    "description": "USB OTG FS clock enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RNGEN": {
+                    "description": "Random number generator clock\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "HASHEN": {
+                    "description": "Hash modules clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CRYPEN": {
+                    "description": "Cryptographic modules clock\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DCMIEN": {
+                    "description": "Camera interface enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB3ENR": {
+              "description": "AHB3 peripheral clock enable\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FMCEN": {
+                    "description": "Flexible memory controller module clock\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1ENR": {
+              "description": "APB1 peripheral clock enable\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM2EN": {
+                    "description": "TIM2 clock enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM3EN": {
+                    "description": "TIM3 clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM4EN": {
+                    "description": "TIM4 clock enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIM5EN": {
+                    "description": "TIM5 clock enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TIM6EN": {
+                    "description": "TIM6 clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM7EN": {
+                    "description": "TIM7 clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIM12EN": {
+                    "description": "TIM12 clock enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TIM13EN": {
+                    "description": "TIM13 clock enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIM14EN": {
+                    "description": "TIM14 clock enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WWDGEN": {
+                    "description": "Window watchdog clock\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI2EN": {
+                    "description": "SPI2 clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI3EN": {
+                    "description": "SPI3 clock enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "USART2EN": {
+                    "description": "USART 2 clock enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USART3EN": {
+                    "description": "USART3 clock enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "UART4EN": {
+                    "description": "UART4 clock enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UART5EN": {
+                    "description": "UART5 clock enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2C1EN": {
+                    "description": "I2C1 clock enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "I2C2EN": {
+                    "description": "I2C2 clock enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "I2C3EN": {
+                    "description": "I2C3 clock enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CAN1EN": {
+                    "description": "CAN 1 clock enable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CAN2EN": {
+                    "description": "CAN 2 clock enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PWREN": {
+                    "description": "Power interface clock\n              enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DACEN": {
+                    "description": "DAC interface clock enable",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB2ENR": {
+              "description": "APB2 peripheral clock enable\n          register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM1EN": {
+                    "description": "TIM1 clock enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM8EN": {
+                    "description": "TIM8 clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "USART1EN": {
+                    "description": "USART1 clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "USART6EN": {
+                    "description": "USART6 clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADC1EN": {
+                    "description": "ADC1 clock enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ADC2EN": {
+                    "description": "ADC2 clock enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ADC3EN": {
+                    "description": "ADC3 clock enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SDIOEN": {
+                    "description": "SDIO clock enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI1EN": {
+                    "description": "SPI1 clock enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SYSCFGEN": {
+                    "description": "System configuration controller clock\n              enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TIM9EN": {
+                    "description": "TIM9 clock enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TIM10EN": {
+                    "description": "TIM10 clock enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TIM11EN": {
+                    "description": "TIM11 clock enable",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB1LPENR": {
+              "description": "AHB1 peripheral clock enable in low power\n          mode register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 2120716799,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPIOALPEN": {
+                    "description": "IO port A clock enable during sleep\n              mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "GPIOBLPEN": {
+                    "description": "IO port B clock enable during Sleep\n              mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIOCLPEN": {
+                    "description": "IO port C clock enable during Sleep\n              mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIODLPEN": {
+                    "description": "IO port D clock enable during Sleep\n              mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIOELPEN": {
+                    "description": "IO port E clock enable during Sleep\n              mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIOFLPEN": {
+                    "description": "IO port F clock enable during Sleep\n              mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIOGLPEN": {
+                    "description": "IO port G clock enable during Sleep\n              mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIOHLPEN": {
+                    "description": "IO port H clock enable during Sleep\n              mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIOILPEN": {
+                    "description": "IO port I clock enable during Sleep\n              mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CRCLPEN": {
+                    "description": "CRC clock enable during Sleep\n              mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FLITFLPEN": {
+                    "description": "Flash interface clock enable during\n              Sleep mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SRAM1LPEN": {
+                    "description": "SRAM 1interface clock enable during\n              Sleep mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SRAM2LPEN": {
+                    "description": "SRAM 2 interface clock enable during\n              Sleep mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BKPSRAMLPEN": {
+                    "description": "Backup SRAM interface clock enable\n              during Sleep mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DMA1LPEN": {
+                    "description": "DMA1 clock enable during Sleep\n              mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "DMA2LPEN": {
+                    "description": "DMA2 clock enable during Sleep\n              mode",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "ETHMACLPEN": {
+                    "description": "Ethernet MAC clock enable during Sleep\n              mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ETHMACTXLPEN": {
+                    "description": "Ethernet transmission clock enable\n              during Sleep mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "ETHMACRXLPEN": {
+                    "description": "Ethernet reception clock enable during\n              Sleep mode",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "ETHMACPTPLPEN": {
+                    "description": "Ethernet PTP clock enable during Sleep\n              mode",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "OTGHSLPEN": {
+                    "description": "USB OTG HS clock enable during Sleep\n              mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "OTGHSULPILPEN": {
+                    "description": "USB OTG HS ULPI clock enable during\n              Sleep mode",
+                    "offset": 30,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB2LPENR": {
+              "description": "AHB2 peripheral clock enable in low power\n          mode register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 241,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OTGFSLPEN": {
+                    "description": "USB OTG FS clock enable during Sleep\n              mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RNGLPEN": {
+                    "description": "Random number generator clock enable\n              during Sleep mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "HASHLPEN": {
+                    "description": "Hash modules clock enable during Sleep\n              mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CRYPLPEN": {
+                    "description": "Cryptography modules clock enable during\n              Sleep mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DCMILPEN": {
+                    "description": "Camera interface enable during Sleep\n              mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHB3LPENR": {
+              "description": "AHB3 peripheral clock enable in low power\n          mode register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FMCLPEN": {
+                    "description": "Flexible memory controller module clock\n              enable during Sleep mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1LPENR": {
+              "description": "APB1 peripheral clock enable in low power\n          mode register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 922667519,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM2LPEN": {
+                    "description": "TIM2 clock enable during Sleep\n              mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM3LPEN": {
+                    "description": "TIM3 clock enable during Sleep\n              mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIM4LPEN": {
+                    "description": "TIM4 clock enable during Sleep\n              mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIM5LPEN": {
+                    "description": "TIM5 clock enable during Sleep\n              mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TIM6LPEN": {
+                    "description": "TIM6 clock enable during Sleep\n              mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIM7LPEN": {
+                    "description": "TIM7 clock enable during Sleep\n              mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TIM12LPEN": {
+                    "description": "TIM12 clock enable during Sleep\n              mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TIM13LPEN": {
+                    "description": "TIM13 clock enable during Sleep\n              mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIM14LPEN": {
+                    "description": "TIM14 clock enable during Sleep\n              mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WWDGLPEN": {
+                    "description": "Window watchdog clock enable during\n              Sleep mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI2LPEN": {
+                    "description": "SPI2 clock enable during Sleep\n              mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI3LPEN": {
+                    "description": "SPI3 clock enable during Sleep\n              mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "USART2LPEN": {
+                    "description": "USART2 clock enable during Sleep\n              mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USART3LPEN": {
+                    "description": "USART3 clock enable during Sleep\n              mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "UART4LPEN": {
+                    "description": "UART4 clock enable during Sleep\n              mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UART5LPEN": {
+                    "description": "UART5 clock enable during Sleep\n              mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2C1LPEN": {
+                    "description": "I2C1 clock enable during Sleep\n              mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "I2C2LPEN": {
+                    "description": "I2C2 clock enable during Sleep\n              mode",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "I2C3LPEN": {
+                    "description": "I2C3 clock enable during Sleep\n              mode",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CAN1LPEN": {
+                    "description": "CAN 1 clock enable during Sleep\n              mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CAN2LPEN": {
+                    "description": "CAN 2 clock enable during Sleep\n              mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PWRLPEN": {
+                    "description": "Power interface clock enable during\n              Sleep mode",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DACLPEN": {
+                    "description": "DAC interface clock enable during Sleep\n              mode",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB2LPENR": {
+              "description": "APB2 peripheral clock enabled in low power\n          mode register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 483123,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIM1LPEN": {
+                    "description": "TIM1 clock enable during Sleep\n              mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM8LPEN": {
+                    "description": "TIM8 clock enable during Sleep\n              mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "USART1LPEN": {
+                    "description": "USART1 clock enable during Sleep\n              mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "USART6LPEN": {
+                    "description": "USART6 clock enable during Sleep\n              mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADC1LPEN": {
+                    "description": "ADC1 clock enable during Sleep\n              mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ADC2LPEN": {
+                    "description": "ADC2 clock enable during Sleep\n              mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ADC3LPEN": {
+                    "description": "ADC 3 clock enable during Sleep\n              mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SDIOLPEN": {
+                    "description": "SDIO clock enable during Sleep\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI1LPEN": {
+                    "description": "SPI 1 clock enable during Sleep\n              mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SYSCFGLPEN": {
+                    "description": "System configuration controller clock\n              enable during Sleep mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TIM9LPEN": {
+                    "description": "TIM9 clock enable during sleep\n              mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TIM10LPEN": {
+                    "description": "TIM10 clock enable during Sleep\n              mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TIM11LPEN": {
+                    "description": "TIM11 clock enable during Sleep\n              mode",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BDCR": {
+              "description": "Backup domain control register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BDRST": {
+                    "description": "Backup domain software\n              reset",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RTCEN": {
+                    "description": "RTC clock enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RTCSEL1": {
+                    "description": "RTC clock source selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RTCSEL0": {
+                    "description": "RTC clock source selection",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LSEBYP": {
+                    "description": "External low-speed oscillator\n              bypass",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LSERDY": {
+                    "description": "External low-speed oscillator\n              ready",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSEON": {
+                    "description": "External low-speed oscillator\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CSR": {
+              "description": "clock control & status\n          register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 234881024,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LPWRRSTF": {
+                    "description": "Low-power reset flag",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "WWDGRSTF": {
+                    "description": "Window watchdog reset flag",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WDGRSTF": {
+                    "description": "Independent watchdog reset\n              flag",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SFTRSTF": {
+                    "description": "Software reset flag",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "PORRSTF": {
+                    "description": "POR/PDR reset flag",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PADRSTF": {
+                    "description": "PIN reset flag",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BORRSTF": {
+                    "description": "BOR reset flag",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "RMVF": {
+                    "description": "Remove reset flag",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LSIRDY": {
+                    "description": "Internal low-speed oscillator\n              ready",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSION": {
+                    "description": "Internal low-speed oscillator\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SSCGR": {
+              "description": "spread spectrum clock generation\n          register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SSCGEN": {
+                    "description": "Spread spectrum modulation\n              enable",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "SPREADSEL": {
+                    "description": "Spread Select",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INCSTEP": {
+                    "description": "Incrementation step",
+                    "offset": 13,
+                    "size": 15
+                  },
+                  "MODPER": {
+                    "description": "Modulation period",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "PLLI2SCFGR": {
+              "description": "PLLI2S configuration register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 536883200,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PLLI2SR": {
+                    "description": "PLLI2S division factor for I2S\n              clocks",
+                    "offset": 28,
+                    "size": 3
+                  },
+                  "PLLI2SQ": {
+                    "description": "PLLI2S division factor for SAI1\n              clock",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "PLLI2SN": {
+                    "description": "PLLI2S multiplication factor for\n              VCO",
+                    "offset": 6,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "DCKCFGR": {
+              "description": "RCC Dedicated Clock Configuration\n          Register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PLLI2SDIVQ": {
+                    "description": "PLLI2S division factor for SAI1\n              clock",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "PLLSAIDIVQ": {
+                    "description": "PLLSAI division factor for SAI1\n              clock",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "PLLSAIDIVR": {
+                    "description": "division factor for\n              LCD_CLK",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "SAI1ASRC": {
+                    "description": "SAI1-A clock source\n              selection",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "SAI1BSRC": {
+                    "description": "SAI1-B clock source\n              selection",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "TIMPRE": {
+                    "description": "Timers clocks prescalers\n              selection",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PLLSAICFGR": {
+              "description": "RCC PLL configuration register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 603992064,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PLLSAIR": {
+                    "description": "PLLSAI division factor for LCD\n              clock",
+                    "offset": 28,
+                    "size": 3
+                  },
+                  "PLLSAIQ": {
+                    "description": "PLLSAI division factor for SAI1\n              clock",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "PLLSAIN": {
+                    "description": "PLLSAI division factor for\n              VCO",
+                    "offset": 6,
+                    "size": 9
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOK": {
+        "description": "General-purpose I/Os",
+        "children": {
+          "registers": {
+            "MODER": {
+              "description": "GPIO port mode register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODER15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MODER14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "MODER13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MODER12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "MODER11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MODER10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "MODER9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MODER8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "MODER7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MODER6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MODER5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MODER4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MODER3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MODER2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MODER1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODER0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTYPER": {
+              "description": "GPIO port output type register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OT15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OT14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OT13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OT12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OT11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OT10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OT9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OT8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OT7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OT6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OT5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OT4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OT3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OT2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OT1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OT0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OSPEEDR": {
+              "description": "GPIO port output speed\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OSPEEDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "OSPEEDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "OSPEEDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "OSPEEDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "OSPEEDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "OSPEEDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "OSPEEDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "OSPEEDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "OSPEEDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "OSPEEDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "OSPEEDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "OSPEEDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSPEEDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "OSPEEDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "OSPEEDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "OSPEEDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PUPDR": {
+              "description": "GPIO port pull-up/pull-down\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PUPDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "PUPDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "PUPDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "PUPDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "PUPDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "PUPDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "PUPDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "PUPDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PUPDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "PUPDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PUPDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PUPDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PUPDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PUPDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PUPDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "PUPDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "GPIO port input data register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDR15": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IDR14": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "IDR13": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "IDR12": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IDR11": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IDR10": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IDR9": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IDR8": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IDR7": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IDR6": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IDR5": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDR4": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDR3": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IDR2": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDR1": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IDR0": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ODR": {
+              "description": "GPIO port output data register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ODR15": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ODR14": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ODR13": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ODR12": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ODR11": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ODR10": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ODR9": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODR8": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ODR7": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ODR6": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ODR5": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ODR4": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ODR3": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ODR2": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ODR1": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ODR0": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BSRR": {
+              "description": "GPIO port bit set/reset\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BR15": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BR0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BS15": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BS14": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BS13": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BS12": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BS11": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BS10": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BS9": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BS8": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BS7": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BS6": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BS5": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BS4": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BS3": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BS2": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BS1": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BS0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LCKR": {
+              "description": "GPIO port configuration lock\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LCKK": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "LCK15": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LCK14": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "LCK13": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LCK12": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LCK11": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LCK10": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LCK9": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LCK8": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LCK7": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCK6": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LCK5": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LCK4": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "LCK3": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LCK2": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LCK1": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LCK0": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AFRL": {
+              "description": "GPIO alternate function low\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRL7": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRL6": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRL5": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRL4": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRL3": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRL2": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRL1": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRL0": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "AFRH": {
+              "description": "GPIO alternate function high\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRH15": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRH14": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRH13": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRH12": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRH11": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRH10": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRH9": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRH8": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FPU_CPACR": {
+        "description": "Floating point unit CPACR",
+        "children": {
+          "registers": {
+            "CPACR": {
+              "description": "Coprocessor access control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CP": {
+                    "description": "CP",
+                    "offset": 20,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NVIC_STIR": {
+        "description": "Nested vectored interrupt\n      controller",
+        "children": {
+          "registers": {
+            "STIR": {
+              "description": "Software trigger interrupt\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTID": {
+                    "description": "Software generated interrupt\n              ID",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SCB": {
+        "description": "System control block",
+        "children": {
+          "registers": {
+            "CPUID": {
+              "description": "CPUID base register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1091551809,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "Revision": {
+                    "description": "Revision number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "PartNo": {
+                    "description": "Part number of the\n              processor",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "Constant": {
+                    "description": "Reads as 0xF",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "Variant": {
+                    "description": "Variant number",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "Implementer": {
+                    "description": "Implementer code",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ICSR": {
+              "description": "Interrupt control and state\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTACTIVE": {
+                    "description": "Active vector",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "RETTOBASE": {
+                    "description": "Return to base level",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "VECTPENDING": {
+                    "description": "Pending vector",
+                    "offset": 12,
+                    "size": 7
+                  },
+                  "ISRPENDING": {
+                    "description": "Interrupt pending flag",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PENDSTCLR": {
+                    "description": "SysTick exception clear-pending\n              bit",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PENDSTSET": {
+                    "description": "SysTick exception set-pending\n              bit",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PENDSVCLR": {
+                    "description": "PendSV clear-pending bit",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PENDSVSET": {
+                    "description": "PendSV set-pending bit",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "NMIPENDSET": {
+                    "description": "NMI set-pending bit.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "VTOR": {
+              "description": "Vector table offset register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TBLOFF": {
+                    "description": "Vector table base offset\n              field",
+                    "offset": 9,
+                    "size": 21
+                  }
+                }
+              }
+            },
+            "AIRCR": {
+              "description": "Application interrupt and reset control\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTRESET": {
+                    "description": "VECTRESET",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "VECTCLRACTIVE": {
+                    "description": "VECTCLRACTIVE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SYSRESETREQ": {
+                    "description": "SYSRESETREQ",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PRIGROUP": {
+                    "description": "PRIGROUP",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "ENDIANESS": {
+                    "description": "ENDIANESS",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "VECTKEYSTAT": {
+                    "description": "Register key",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SCR": {
+              "description": "System control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLEEPONEXIT": {
+                    "description": "SLEEPONEXIT",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEEPDEEP": {
+                    "description": "SLEEPDEEP",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SEVEONPEND": {
+                    "description": "Send Event on Pending bit",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "Configuration and control\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NONBASETHRDENA": {
+                    "description": "Configures how the processor enters\n              Thread mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USERSETMPEND": {
+                    "description": "USERSETMPEND",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UNALIGN__TRP": {
+                    "description": "UNALIGN_ TRP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIV_0_TRP": {
+                    "description": "DIV_0_TRP",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BFHFNMIGN": {
+                    "description": "BFHFNMIGN",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "STKALIGN": {
+                    "description": "STKALIGN",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SHPR1": {
+              "description": "System handler priority\n          registers",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_4": {
+                    "description": "Priority of system handler\n              4",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "PRI_5": {
+                    "description": "Priority of system handler\n              5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "PRI_6": {
+                    "description": "Priority of system handler\n              6",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHPR2": {
+              "description": "System handler priority\n          registers",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_11": {
+                    "description": "Priority of system handler\n              11",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHPR3": {
+              "description": "System handler priority\n          registers",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRI_14": {
+                    "description": "Priority of system handler\n              14",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "PRI_15": {
+                    "description": "Priority of system handler\n              15",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SHCRS": {
+              "description": "System handler control and state\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEMFAULTACT": {
+                    "description": "Memory management fault exception active\n              bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BUSFAULTACT": {
+                    "description": "Bus fault exception active\n              bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "USGFAULTACT": {
+                    "description": "Usage fault exception active\n              bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SVCALLACT": {
+                    "description": "SVC call active bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MONITORACT": {
+                    "description": "Debug monitor active bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PENDSVACT": {
+                    "description": "PendSV exception active\n              bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SYSTICKACT": {
+                    "description": "SysTick exception active\n              bit",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USGFAULTPENDED": {
+                    "description": "Usage fault exception pending\n              bit",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MEMFAULTPENDED": {
+                    "description": "Memory management fault exception\n              pending bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BUSFAULTPENDED": {
+                    "description": "Bus fault exception pending\n              bit",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SVCALLPENDED": {
+                    "description": "SVC call pending bit",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MEMFAULTENA": {
+                    "description": "Memory management fault enable\n              bit",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUSFAULTENA": {
+                    "description": "Bus fault enable bit",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USGFAULTENA": {
+                    "description": "Usage fault enable bit",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CFSR_UFSR_BFSR_MMFSR": {
+              "description": "Configurable fault status\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IACCVIOL": {
+                    "description": "Instruction access violation\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MUNSTKERR": {
+                    "description": "Memory manager fault on unstacking for a\n              return from exception",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MSTKERR": {
+                    "description": "Memory manager fault on stacking for\n              exception entry.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MLSPERR": {
+                    "description": "MLSPERR",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MMARVALID": {
+                    "description": "Memory Management Fault Address Register\n              (MMAR) valid flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IBUSERR": {
+                    "description": "Instruction bus error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PRECISERR": {
+                    "description": "Precise data bus error",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IMPRECISERR": {
+                    "description": "Imprecise data bus error",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "UNSTKERR": {
+                    "description": "Bus fault on unstacking for a return\n              from exception",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STKERR": {
+                    "description": "Bus fault on stacking for exception\n              entry",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LSPERR": {
+                    "description": "Bus fault on floating-point lazy state\n              preservation",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BFARVALID": {
+                    "description": "Bus Fault Address Register (BFAR) valid\n              flag",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "UNDEFINSTR": {
+                    "description": "Undefined instruction usage\n              fault",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "INVSTATE": {
+                    "description": "Invalid state usage fault",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INVPC": {
+                    "description": "Invalid PC load usage\n              fault",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "NOCP": {
+                    "description": "No coprocessor usage\n              fault.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UNALIGNED": {
+                    "description": "Unaligned access usage\n              fault",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "DIVBYZERO": {
+                    "description": "Divide by zero usage fault",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HFSR": {
+              "description": "Hard fault status register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VECTTBL": {
+                    "description": "Vector table hard fault",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FORCED": {
+                    "description": "Forced hard fault",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DEBUG_VT": {
+                    "description": "Reserved for Debug use",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMFAR": {
+              "description": "Memory management fault address\n          register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMFAR": {
+                    "description": "Memory management fault\n              address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BFAR": {
+              "description": "Bus fault address register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BFAR": {
+                    "description": "Bus fault address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "AFSR": {
+              "description": "Auxiliary fault status\n          register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IMPDEF": {
+                    "description": "Implementation defined",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "STK": {
+        "description": "SysTick timer",
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "SysTick control and status\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TICKINT": {
+                    "description": "SysTick exception request\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CLKSOURCE": {
+                    "description": "Clock source selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "COUNTFLAG": {
+                    "description": "COUNTFLAG",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LOAD": {
+              "description": "SysTick reload value register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RELOAD": {
+                    "description": "RELOAD value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "VAL": {
+              "description": "SysTick current value register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CURRENT": {
+                    "description": "Current counter value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "CALIB": {
+              "description": "SysTick calibration value\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TENMS": {
+                    "description": "Calibration value",
+                    "offset": 0,
+                    "size": 24
+                  },
+                  "SKEW": {
+                    "description": "SKEW flag: Indicates whether the TENMS\n              value is exact",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "NOREF": {
+                    "description": "NOREF flag. Reads as zero",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "MPU": {
+        "description": "Memory protection unit",
+        "children": {
+          "registers": {
+            "MPU_TYPER": {
+              "description": "MPU type register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SEPARATE": {
+                    "description": "Separate flag",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DREGION": {
+                    "description": "Number of MPU data regions",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IREGION": {
+                    "description": "Number of MPU instruction\n              regions",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MPU_CTRL": {
+              "description": "MPU control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enables the MPU",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HFNMIENA": {
+                    "description": "Enables the operation of MPU during hard\n              fault",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PRIVDEFENA": {
+                    "description": "Enable priviliged software access to\n              default memory map",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MPU_RNR": {
+              "description": "MPU region number register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION": {
+                    "description": "MPU region",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MPU_RBAR": {
+              "description": "MPU region base address\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION": {
+                    "description": "MPU region field",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "VALID": {
+                    "description": "MPU region number valid",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ADDR": {
+                    "description": "Region base address field",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "MPU_RASR": {
+              "description": "MPU region attribute and size\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Region enable bit.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SIZE": {
+                    "description": "Size of the MPU protection\n              region",
+                    "offset": 1,
+                    "size": 5
+                  },
+                  "SRD": {
+                    "description": "Subregion disable bits",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "B": {
+                    "description": "memory attribute",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "C": {
+                    "description": "memory attribute",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "S": {
+                    "description": "Shareable memory attribute",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TEX": {
+                    "description": "memory attribute",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "AP": {
+                    "description": "Access permission",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "XN": {
+                    "description": "Instruction access disable\n              bit",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FPU": {
+        "description": "Floting point unit",
+        "children": {
+          "registers": {
+            "FPCCR": {
+              "description": "Floating-point context control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSPACT": {
+                    "description": "LSPACT",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USER": {
+                    "description": "USER",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "THREAD": {
+                    "description": "THREAD",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "HFRDY": {
+                    "description": "HFRDY",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MMRDY": {
+                    "description": "MMRDY",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BFRDY": {
+                    "description": "BFRDY",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MONRDY": {
+                    "description": "MONRDY",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LSPEN": {
+                    "description": "LSPEN",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "ASPEN": {
+                    "description": "ASPEN",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FPCAR": {
+              "description": "Floating-point context address\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS": {
+                    "description": "Location of unpopulated\n              floating-point",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            },
+            "FPSCR": {
+              "description": "Floating-point status control\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOC": {
+                    "description": "Invalid operation cumulative exception\n              bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DZC": {
+                    "description": "Division by zero cumulative exception\n              bit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OFC": {
+                    "description": "Overflow cumulative exception\n              bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UFC": {
+                    "description": "Underflow cumulative exception\n              bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IXC": {
+                    "description": "Inexact cumulative exception\n              bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDC": {
+                    "description": "Input denormal cumulative exception\n              bit.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RMode": {
+                    "description": "Rounding Mode control\n              field",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "FZ": {
+                    "description": "Flush-to-zero mode control\n              bit:",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "DN": {
+                    "description": "Default NaN mode control\n              bit",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "AHP": {
+                    "description": "Alternative half-precision control\n              bit",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "V": {
+                    "description": "Overflow condition code\n              flag",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "C": {
+                    "description": "Carry condition code flag",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "Z": {
+                    "description": "Zero condition code flag",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "N": {
+                    "description": "Negative condition code\n              flag",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM6": {
+        "description": "Basic timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Low Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "Ethernet_MMC": {
+        "description": "Ethernet: MAC management counters",
+        "children": {
+          "registers": {
+            "MMCCR": {
+              "description": "Ethernet MMC control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CR": {
+                    "description": "CR",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CSR": {
+                    "description": "CSR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ROR": {
+                    "description": "ROR",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MCF": {
+                    "description": "MCF",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MCP": {
+                    "description": "MCP",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MCFHP": {
+                    "description": "MCFHP",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCRIR": {
+              "description": "Ethernet MMC receive interrupt\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFCES": {
+                    "description": "RFCES",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RFAES": {
+                    "description": "RFAES",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RGUFS": {
+                    "description": "RGUFS",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCTIR": {
+              "description": "Ethernet MMC transmit interrupt\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TGFSCS": {
+                    "description": "TGFSCS",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TGFMSCS": {
+                    "description": "TGFMSCS",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TGFS": {
+                    "description": "TGFS",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCRIMR": {
+              "description": "Ethernet MMC receive interrupt mask\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFCEM": {
+                    "description": "RFCEM",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RFAEM": {
+                    "description": "RFAEM",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RGUFM": {
+                    "description": "RGUFM",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCTIMR": {
+              "description": "Ethernet MMC transmit interrupt mask\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TGFSCM": {
+                    "description": "TGFSCM",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TGFMSCM": {
+                    "description": "TGFMSCM",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TGFM": {
+                    "description": "TGFM",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCTGFSCCR": {
+              "description": "Ethernet MMC transmitted good frames after a\n          single collision counter",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TGFSCC": {
+                    "description": "TGFSCC",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCTGFMSCCR": {
+              "description": "Ethernet MMC transmitted good frames after\n          more than a single collision",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TGFMSCC": {
+                    "description": "TGFMSCC",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCTGFCR": {
+              "description": "Ethernet MMC transmitted good frames counter\n          register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TGFC": {
+                    "description": "HTL",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCRFCECR": {
+              "description": "Ethernet MMC received frames with CRC error\n          counter register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RFCFC": {
+                    "description": "RFCFC",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCRFAECR": {
+              "description": "Ethernet MMC received frames with alignment\n          error counter register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RFAEC": {
+                    "description": "RFAEC",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MMCRGUFCR": {
+              "description": "MMC received good unicast frames counter\n          register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RGUFC": {
+                    "description": "RGUFC",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOB": {
+        "description": "General-purpose I/Os",
+        "children": {
+          "registers": {
+            "MODER": {
+              "description": "GPIO port mode register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 640,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODER15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MODER14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "MODER13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MODER12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "MODER11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MODER10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "MODER9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MODER8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "MODER7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MODER6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MODER5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MODER4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MODER3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MODER2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MODER1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODER0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTYPER": {
+              "description": "GPIO port output type register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OT15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OT14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OT13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OT12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OT11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OT10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OT9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OT8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OT7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OT6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OT5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OT4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OT3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OT2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OT1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OT0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OSPEEDR": {
+              "description": "GPIO port output speed\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OSPEEDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "OSPEEDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "OSPEEDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "OSPEEDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "OSPEEDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "OSPEEDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "OSPEEDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "OSPEEDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "OSPEEDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "OSPEEDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "OSPEEDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "OSPEEDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSPEEDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "OSPEEDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "OSPEEDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "OSPEEDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PUPDR": {
+              "description": "GPIO port pull-up/pull-down\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 256,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PUPDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "PUPDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "PUPDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "PUPDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "PUPDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "PUPDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "PUPDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "PUPDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PUPDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "PUPDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PUPDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PUPDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PUPDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PUPDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PUPDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "PUPDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "GPIO port input data register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDR15": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IDR14": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "IDR13": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "IDR12": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IDR11": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IDR10": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IDR9": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IDR8": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IDR7": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IDR6": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IDR5": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDR4": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDR3": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IDR2": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDR1": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IDR0": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ODR": {
+              "description": "GPIO port output data register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ODR15": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ODR14": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ODR13": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ODR12": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ODR11": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ODR10": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ODR9": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODR8": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ODR7": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ODR6": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ODR5": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ODR4": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ODR3": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ODR2": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ODR1": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ODR0": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BSRR": {
+              "description": "GPIO port bit set/reset\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BR15": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BR0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BS15": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BS14": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BS13": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BS12": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BS11": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BS10": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BS9": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BS8": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BS7": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BS6": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BS5": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BS4": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BS3": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BS2": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BS1": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BS0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LCKR": {
+              "description": "GPIO port configuration lock\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LCKK": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "LCK15": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LCK14": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "LCK13": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LCK12": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LCK11": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LCK10": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LCK9": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LCK8": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LCK7": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCK6": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LCK5": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LCK4": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "LCK3": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LCK2": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LCK1": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LCK0": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AFRL": {
+              "description": "GPIO alternate function low\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRL7": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRL6": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRL5": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRL4": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRL3": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRL2": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRL1": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRL0": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "AFRH": {
+              "description": "GPIO alternate function high\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRH15": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRH14": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRH13": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRH12": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRH11": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRH10": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRH9": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRH8": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOA": {
+        "description": "General-purpose I/Os",
+        "children": {
+          "registers": {
+            "MODER": {
+              "description": "GPIO port mode register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2818572288,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODER15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MODER14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "MODER13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MODER12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "MODER11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MODER10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "MODER9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MODER8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "MODER7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MODER6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "MODER5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MODER4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MODER3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MODER2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "MODER1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODER0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTYPER": {
+              "description": "GPIO port output type register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OT15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OT14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OT13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OT12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OT11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OT10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OT9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OT8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OT7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OT6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OT5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OT4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OT3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OT2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OT1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OT0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OSPEEDR": {
+              "description": "GPIO port output speed\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OSPEEDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "OSPEEDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "OSPEEDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "OSPEEDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "OSPEEDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "OSPEEDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "OSPEEDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "OSPEEDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "OSPEEDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "OSPEEDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "OSPEEDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "OSPEEDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OSPEEDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "OSPEEDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "OSPEEDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "OSPEEDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PUPDR": {
+              "description": "GPIO port pull-up/pull-down\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 1677721600,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PUPDR15": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "PUPDR14": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "PUPDR13": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "PUPDR12": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "PUPDR11": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "PUPDR10": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "PUPDR9": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "PUPDR8": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "PUPDR7": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "PUPDR6": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "PUPDR5": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PUPDR4": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PUPDR3": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "PUPDR2": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "PUPDR1": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "PUPDR0": {
+                    "description": "Port x configuration bits (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "GPIO port input data register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDR15": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IDR14": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "IDR13": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "IDR12": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IDR11": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IDR10": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IDR9": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IDR8": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IDR7": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IDR6": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IDR5": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDR4": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IDR3": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IDR2": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDR1": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IDR0": {
+                    "description": "Port input data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ODR": {
+              "description": "GPIO port output data register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ODR15": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ODR14": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ODR13": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ODR12": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ODR11": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ODR10": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ODR9": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODR8": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ODR7": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ODR6": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ODR5": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ODR4": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ODR3": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ODR2": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ODR1": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ODR0": {
+                    "description": "Port output data (y =\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BSRR": {
+              "description": "GPIO port bit set/reset\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BR15": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "BR14": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "BR13": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BR12": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "BR11": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "BR10": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BR9": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "BR8": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BR7": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BR6": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BR5": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "BR4": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BR3": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "BR2": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BR1": {
+                    "description": "Port x reset bit y (y =\n              0..15)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "BR0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BS15": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BS14": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BS13": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BS12": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BS11": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BS10": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BS9": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BS8": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BS7": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BS6": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BS5": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BS4": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BS3": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BS2": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BS1": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BS0": {
+                    "description": "Port x set bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LCKR": {
+              "description": "GPIO port configuration lock\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LCKK": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "LCK15": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LCK14": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "LCK13": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LCK12": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LCK11": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LCK10": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LCK9": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LCK8": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LCK7": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCK6": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LCK5": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LCK4": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "LCK3": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LCK2": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LCK1": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LCK0": {
+                    "description": "Port x lock bit y (y=\n              0..15)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AFRL": {
+              "description": "GPIO alternate function low\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRL7": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRL6": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRL5": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRL4": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRL3": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRL2": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRL1": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRL0": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 0..7)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "AFRH": {
+              "description": "GPIO alternate function high\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRH15": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "AFRH14": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "AFRH13": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "AFRH12": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "AFRH11": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "AFRH10": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "AFRH9": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "AFRH8": {
+                    "description": "Alternate function selection for port x\n              bit y (y = 8..15)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SYSCFG": {
+        "description": "System configuration controller",
+        "children": {
+          "registers": {
+            "MEMRM": {
+              "description": "memory remap register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_MODE": {
+                    "description": "Memory mapping selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "FB_MODE": {
+                    "description": "Flash bank mode selection",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SWP_FMC": {
+                    "description": "FMC memory mapping swap",
+                    "offset": 10,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PMC": {
+              "description": "peripheral mode configuration\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MII_RMII_SEL": {
+                    "description": "Ethernet PHY interface\n              selection",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "ADC1DC2": {
+                    "description": "ADC1DC2",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ADC2DC2": {
+                    "description": "ADC2DC2",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ADC3DC2": {
+                    "description": "ADC3DC2",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EXTICR1": {
+              "description": "external interrupt configuration register\n          1",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI3": {
+                    "description": "EXTI x configuration (x = 0 to\n              3)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI2": {
+                    "description": "EXTI x configuration (x = 0 to\n              3)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI1": {
+                    "description": "EXTI x configuration (x = 0 to\n              3)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI0": {
+                    "description": "EXTI x configuration (x = 0 to\n              3)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTICR2": {
+              "description": "external interrupt configuration register\n          2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI7": {
+                    "description": "EXTI x configuration (x = 4 to\n              7)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI6": {
+                    "description": "EXTI x configuration (x = 4 to\n              7)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI5": {
+                    "description": "EXTI x configuration (x = 4 to\n              7)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI4": {
+                    "description": "EXTI x configuration (x = 4 to\n              7)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTICR3": {
+              "description": "external interrupt configuration register\n          3",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI11": {
+                    "description": "EXTI x configuration (x = 8 to\n              11)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI10": {
+                    "description": "EXTI10",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI9": {
+                    "description": "EXTI x configuration (x = 8 to\n              11)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI8": {
+                    "description": "EXTI x configuration (x = 8 to\n              11)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTICR4": {
+              "description": "external interrupt configuration register\n          4",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI15": {
+                    "description": "EXTI x configuration (x = 12 to\n              15)",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI14": {
+                    "description": "EXTI x configuration (x = 12 to\n              15)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI13": {
+                    "description": "EXTI x configuration (x = 12 to\n              15)",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI12": {
+                    "description": "EXTI x configuration (x = 12 to\n              15)",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CMPCR": {
+              "description": "Compensation cell control\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "READY": {
+                    "description": "READY",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CMP_PD": {
+                    "description": "Compensation cell\n              power-down",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI1": {
+        "description": "Serial peripheral interface",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BIDIMODE": {
+                    "description": "Bidirectional data mode\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BIDIOE": {
+                    "description": "Output enable in bidirectional\n              mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CRCEN": {
+                    "description": "Hardware CRC calculation\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CRCNEXT": {
+                    "description": "CRC transfer next",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DFF": {
+                    "description": "Data frame format",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RXONLY": {
+                    "description": "Receive only",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SSM": {
+                    "description": "Software slave management",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SSI": {
+                    "description": "Internal slave select",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LSBFIRST": {
+                    "description": "Frame format",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SPE": {
+                    "description": "SPI enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BR": {
+                    "description": "Baud rate control",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "MSTR": {
+                    "description": "Master selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CPOL": {
+                    "description": "Clock polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CPHA": {
+                    "description": "Clock phase",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXEIE": {
+                    "description": "Tx buffer empty interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RX buffer not empty interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FRF": {
+                    "description": "Frame format",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SSOE": {
+                    "description": "SS output enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXDMAEN": {
+                    "description": "Tx buffer DMA enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXDMAEN": {
+                    "description": "Rx buffer DMA enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIFRFE": {
+                    "description": "TI frame format error",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BSY": {
+                    "description": "Busy flag",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVR": {
+                    "description": "Overrun flag",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MODF": {
+                    "description": "Mode fault",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRCERR": {
+                    "description": "CRC error flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "UDR": {
+                    "description": "Underrun flag",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CHSIDE": {
+                    "description": "Channel side",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXE": {
+                    "description": "Transmit buffer empty",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXNE": {
+                    "description": "Receive buffer not empty",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "data register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CRCPR": {
+              "description": "CRC polynomial register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRCPOLY": {
+                    "description": "CRC polynomial register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RXCRCR": {
+              "description": "RX CRC register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RxCRC": {
+                    "description": "Rx CRC register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TXCRCR": {
+              "description": "TX CRC register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TxCRC": {
+                    "description": "Tx CRC register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "I2SCFGR": {
+              "description": "I2S configuration register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "I2SMOD": {
+                    "description": "I2S mode selection",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "I2SE": {
+                    "description": "I2S Enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "I2SCFG": {
+                    "description": "I2S configuration mode",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PCMSYNC": {
+                    "description": "PCM frame synchronization",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "I2SSTD": {
+                    "description": "I2S standard selection",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CKPOL": {
+                    "description": "Steady state clock\n              polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DATLEN": {
+                    "description": "Data length to be\n              transferred",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "CHLEN": {
+                    "description": "Channel length (number of bits per audio\n              channel)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "I2SPR": {
+              "description": "I2S prescaler register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 10,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCKOE": {
+                    "description": "Master clock output enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ODD": {
+                    "description": "Odd factor for the\n              prescaler",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "I2SDIV": {
+                    "description": "I2S Linear prescaler",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2C3": {
+        "description": "Inter-integrated circuit",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "Control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWRST": {
+                    "description": "Software reset",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ALERT": {
+                    "description": "SMBus alert",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PEC": {
+                    "description": "Packet error checking",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "POS": {
+                    "description": "Acknowledge/PEC Position (for data\n              reception)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "Acknowledge enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "Stop generation",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "START": {
+                    "description": "Start generation",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "NOSTRETCH": {
+                    "description": "Clock stretching disable (Slave\n              mode)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ENGC": {
+                    "description": "General call enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ENPEC": {
+                    "description": "PEC enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ENARP": {
+                    "description": "ARP enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SMBTYPE": {
+                    "description": "SMBus type",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SMBUS": {
+                    "description": "SMBus mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PE": {
+                    "description": "Peripheral enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "Control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LAST": {
+                    "description": "DMA last transfer",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DMAEN": {
+                    "description": "DMA requests enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ITBUFEN": {
+                    "description": "Buffer interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ITEVTEN": {
+                    "description": "Event interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ITERREN": {
+                    "description": "Error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FREQ": {
+                    "description": "Peripheral clock frequency",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "OAR1": {
+              "description": "Own address register 1",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDMODE": {
+                    "description": "Addressing mode (slave\n              mode)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ADD10": {
+                    "description": "Interface address",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ADD7": {
+                    "description": "Interface address",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "ADD0": {
+                    "description": "Interface address",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OAR2": {
+              "description": "Own address register 2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADD2": {
+                    "description": "Interface address",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "ENDUAL": {
+                    "description": "Dual addressing mode\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "Data register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "8-bit data register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SR1": {
+              "description": "Status register 1",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMBALERT": {
+                    "description": "SMBus alert",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TIMEOUT": {
+                    "description": "Timeout or Tlow error",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PECERR": {
+                    "description": "PEC Error in reception",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OVR": {
+                    "description": "Overrun/Underrun",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AF": {
+                    "description": "Acknowledge failure",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ARLO": {
+                    "description": "Arbitration lost (master\n              mode)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Bus error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TxE": {
+                    "description": "Data register empty\n              (transmitters)",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RxNE": {
+                    "description": "Data register not empty\n              (receivers)",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STOPF": {
+                    "description": "Stop detection (slave\n              mode)",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ADD10": {
+                    "description": "10-bit header sent (Master\n              mode)",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BTF": {
+                    "description": "Byte transfer finished",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ADDR": {
+                    "description": "Address sent (master mode)/matched\n              (slave mode)",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SB": {
+                    "description": "Start bit (Master mode)",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SR2": {
+              "description": "Status register 2",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PEC": {
+                    "description": "acket error checking\n              register",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DUALF": {
+                    "description": "Dual flag (Slave mode)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SMBHOST": {
+                    "description": "SMBus host header (Slave\n              mode)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SMBDEFAULT": {
+                    "description": "SMBus device default address (Slave\n              mode)",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GENCALL": {
+                    "description": "General call address (Slave\n              mode)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TRA": {
+                    "description": "Transmitter/receiver",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "Bus busy",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MSL": {
+                    "description": "Master/slave",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "Clock control register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "F_S": {
+                    "description": "I2C master mode selection",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "DUTY": {
+                    "description": "Fast mode duty cycle",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CCR": {
+                    "description": "Clock control register in Fast/Standard\n              mode (Master mode)",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "TRISE": {
+              "description": "TRISE register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRISE": {
+                    "description": "Maximum rise time in Fast/Standard mode\n              (Master mode)",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "FLTR": {
+              "description": "I2C FLTR register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DNF": {
+                    "description": "Digital noise filter",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "ANOFF": {
+                    "description": "Analog noise filter OFF",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DMA2D": {
+        "description": "DMA2D controller",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "DMA2D mode",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CEIE": {
+                    "description": "Configuration Error Interrupt\n              Enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CTCIE": {
+                    "description": "CLUT transfer complete interrupt\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CAEIE": {
+                    "description": "CLUT access error interrupt\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TWIE": {
+                    "description": "Transfer watermark interrupt\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transfer complete interrupt\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TEIE": {
+                    "description": "Transfer error interrupt\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ABORT": {
+                    "description": "Abort",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SUSP": {
+                    "description": "Suspend",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "START": {
+                    "description": "Start",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ISR": {
+              "description": "Interrupt Status Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CEIF": {
+                    "description": "Configuration error interrupt\n              flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CTCIF": {
+                    "description": "CLUT transfer complete interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CAEIF": {
+                    "description": "CLUT access error interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TWIF": {
+                    "description": "Transfer watermark interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TCIF": {
+                    "description": "Transfer complete interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TEIF": {
+                    "description": "Transfer error interrupt\n              flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IFCR": {
+              "description": "interrupt flag clear register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCEIF": {
+                    "description": "Clear configuration error interrupt\n              flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CCTCIF": {
+                    "description": "Clear CLUT transfer complete interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CAECIF": {
+                    "description": "Clear CLUT access error interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CTWIF": {
+                    "description": "Clear transfer watermark interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CTCIF": {
+                    "description": "Clear transfer complete interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CTEIF": {
+                    "description": "Clear Transfer error interrupt\n              flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FGMAR": {
+              "description": "foreground memory address\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FGOR": {
+              "description": "foreground offset register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LO": {
+                    "description": "Line offset",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "BGMAR": {
+              "description": "background memory address\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BGOR": {
+              "description": "background offset register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LO": {
+                    "description": "Line offset",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "FGPFCCR": {
+              "description": "foreground PFC control\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ALPHA": {
+                    "description": "Alpha value",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "AM": {
+                    "description": "Alpha mode",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CS": {
+                    "description": "CLUT size",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "START": {
+                    "description": "Start",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CCM": {
+                    "description": "CLUT color mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CM": {
+                    "description": "Color mode",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "FGCOLR": {
+              "description": "foreground color register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RED": {
+                    "description": "Red Value",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "GREEN": {
+                    "description": "Green Value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BLUE": {
+                    "description": "Blue Value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BGPFCCR": {
+              "description": "background PFC control\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ALPHA": {
+                    "description": "Alpha value",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "AM": {
+                    "description": "Alpha mode",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CS": {
+                    "description": "CLUT size",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "START": {
+                    "description": "Start",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CCM": {
+                    "description": "CLUT Color mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CM": {
+                    "description": "Color mode",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "BGCOLR": {
+              "description": "background color register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RED": {
+                    "description": "Red Value",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "GREEN": {
+                    "description": "Green Value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BLUE": {
+                    "description": "Blue Value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "FGCMAR": {
+              "description": "foreground CLUT memory address\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory Address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BGCMAR": {
+              "description": "background CLUT memory address\n          register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OPFCCR": {
+              "description": "output PFC control register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CM": {
+                    "description": "Color mode",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "OCOLR": {
+              "description": "output color register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APLHA": {
+                    "description": "Alpha Channel Value",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "RED": {
+                    "description": "Red Value",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "GREEN": {
+                    "description": "Green Value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BLUE": {
+                    "description": "Blue Value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "OMAR": {
+              "description": "output memory address register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MA": {
+                    "description": "Memory Address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OOR": {
+              "description": "output offset register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LO": {
+                    "description": "Line Offset",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "NLR": {
+              "description": "number of line register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PL": {
+                    "description": "Pixel per lines",
+                    "offset": 16,
+                    "size": 14
+                  },
+                  "NL": {
+                    "description": "Number of lines",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "LWR": {
+              "description": "line watermark register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LW": {
+                    "description": "Line watermark",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "AMTCR": {
+              "description": "AHB master timer configuration\n          register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DT": {
+                    "description": "Dead Time",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "EN": {
+                    "description": "Enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FGCLUT": {
+              "description": "FGCLUT",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APLHA": {
+                    "description": "APLHA",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "RED": {
+                    "description": "RED",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "GREEN": {
+                    "description": "GREEN",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BLUE": {
+                    "description": "BLUE",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BGCLUT": {
+              "description": "BGCLUT",
+              "offset": 2048,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APLHA": {
+                    "description": "APLHA",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "RED": {
+                    "description": "RED",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "GREEN": {
+                    "description": "GREEN",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BLUE": {
+                    "description": "BLUE",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SAI": {
+        "description": "Serial audio interface",
+        "children": {
+          "registers": {
+            "BCR1": {
+              "description": "BConfiguration register 1",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCJDIV": {
+                    "description": "Master clock divider",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "NODIV": {
+                    "description": "No divider",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DMAEN": {
+                    "description": "DMA enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SAIBEN": {
+                    "description": "Audio block B enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OutDri": {
+                    "description": "Output drive",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MONO": {
+                    "description": "Mono mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SYNCEN": {
+                    "description": "Synchronization enable",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CKSTR": {
+                    "description": "Clock strobing edge",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LSBFIRST": {
+                    "description": "Least significant bit\n              first",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DS": {
+                    "description": "Data size",
+                    "offset": 5,
+                    "size": 3
+                  },
+                  "PRTCFG": {
+                    "description": "Protocol configuration",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODE": {
+                    "description": "Audio block mode",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "BCR2": {
+              "description": "BConfiguration register 2",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMP": {
+                    "description": "Companding mode",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CPL": {
+                    "description": "Complement bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MUTECN": {
+                    "description": "Mute counter",
+                    "offset": 7,
+                    "size": 6
+                  },
+                  "MUTEVAL": {
+                    "description": "Mute value",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MUTE": {
+                    "description": "Mute",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TRIS": {
+                    "description": "Tristate management on data\n              line",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FFLUS": {
+                    "description": "FIFO flush",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "BFRCR": {
+              "description": "BFRCR",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSOFF": {
+                    "description": "Frame synchronization\n              offset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FSPOL": {
+                    "description": "Frame synchronization\n              polarity",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FSDEF": {
+                    "description": "Frame synchronization\n              definition",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FSALL": {
+                    "description": "Frame synchronization active level\n              length",
+                    "offset": 8,
+                    "size": 7
+                  },
+                  "FRL": {
+                    "description": "Frame length",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BSLOTR": {
+              "description": "BSlot register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLOTEN": {
+                    "description": "Slot enable",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "NBSLOT": {
+                    "description": "Number of slots in an audio\n              frame",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "SLOTSZ": {
+                    "description": "Slot size",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "FBOFF": {
+                    "description": "First bit offset",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "BIM": {
+              "description": "BInterrupt mask register2",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LFSDETIE": {
+                    "description": "Late frame synchronization detection\n              interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AFSDETIE": {
+                    "description": "Anticipated frame synchronization\n              detection interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CNRDYIE": {
+                    "description": "Codec not ready interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FREQIE": {
+                    "description": "FIFO request interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "WCKCFG": {
+                    "description": "Wrong clock configuration interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MUTEDET": {
+                    "description": "Mute detection interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OVRUDRIE": {
+                    "description": "Overrun/underrun interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BSR": {
+              "description": "BStatus register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FLVL": {
+                    "description": "FIFO level threshold",
+                    "offset": 16,
+                    "size": 3
+                  },
+                  "LFSDET": {
+                    "description": "Late frame synchronization\n              detection",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AFSDET": {
+                    "description": "Anticipated frame synchronization\n              detection",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CNRDY": {
+                    "description": "Codec not ready",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FREQ": {
+                    "description": "FIFO request",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "WCKCFG": {
+                    "description": "Wrong clock configuration\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MUTEDET": {
+                    "description": "Mute detection",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OVRUDR": {
+                    "description": "Overrun / underrun",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BCLRFR": {
+              "description": "BClear flag register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "LFSDET": {
+                    "description": "Clear late frame synchronization\n              detection flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CAFSDET": {
+                    "description": "Clear anticipated frame synchronization\n              detection flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CNRDY": {
+                    "description": "Clear codec not ready flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "WCKCFG": {
+                    "description": "Clear wrong clock configuration\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MUTEDET": {
+                    "description": "Mute detection flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OVRUDR": {
+                    "description": "Clear overrun / underrun",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BDR": {
+              "description": "BData register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Data",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ACR1": {
+              "description": "AConfiguration register 1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCJDIV": {
+                    "description": "Master clock divider",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "NODIV": {
+                    "description": "No divider",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DMAEN": {
+                    "description": "DMA enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SAIAEN": {
+                    "description": "Audio block A enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OutDri": {
+                    "description": "Output drive",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MONO": {
+                    "description": "Mono mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SYNCEN": {
+                    "description": "Synchronization enable",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CKSTR": {
+                    "description": "Clock strobing edge",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LSBFIRST": {
+                    "description": "Least significant bit\n              first",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DS": {
+                    "description": "Data size",
+                    "offset": 5,
+                    "size": 3
+                  },
+                  "PRTCFG": {
+                    "description": "Protocol configuration",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MODE": {
+                    "description": "Audio block mode",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "ACR2": {
+              "description": "AConfiguration register 2",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMP": {
+                    "description": "Companding mode",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CPL": {
+                    "description": "Complement bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MUTECN": {
+                    "description": "Mute counter",
+                    "offset": 7,
+                    "size": 6
+                  },
+                  "MUTEVAL": {
+                    "description": "Mute value",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MUTE": {
+                    "description": "Mute",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TRIS": {
+                    "description": "Tristate management on data\n              line",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FFLUS": {
+                    "description": "FIFO flush",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FTH": {
+                    "description": "FIFO threshold",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "AFRCR": {
+              "description": "AFRCR",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSOFF": {
+                    "description": "Frame synchronization\n              offset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FSPOL": {
+                    "description": "Frame synchronization\n              polarity",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FSDEF": {
+                    "description": "Frame synchronization\n              definition",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FSALL": {
+                    "description": "Frame synchronization active level\n              length",
+                    "offset": 8,
+                    "size": 7
+                  },
+                  "FRL": {
+                    "description": "Frame length",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ASLOTR": {
+              "description": "ASlot register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLOTEN": {
+                    "description": "Slot enable",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "NBSLOT": {
+                    "description": "Number of slots in an audio\n              frame",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "SLOTSZ": {
+                    "description": "Slot size",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "FBOFF": {
+                    "description": "First bit offset",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "AIM": {
+              "description": "AInterrupt mask register2",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LFSDET": {
+                    "description": "Late frame synchronization detection\n              interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AFSDETIE": {
+                    "description": "Anticipated frame synchronization\n              detection interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CNRDYIE": {
+                    "description": "Codec not ready interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FREQIE": {
+                    "description": "FIFO request interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "WCKCFG": {
+                    "description": "Wrong clock configuration interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MUTEDET": {
+                    "description": "Mute detection interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OVRUDRIE": {
+                    "description": "Overrun/underrun interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ASR": {
+              "description": "AStatus register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLVL": {
+                    "description": "FIFO level threshold",
+                    "offset": 16,
+                    "size": 3
+                  },
+                  "LFSDET": {
+                    "description": "Late frame synchronization\n              detection",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AFSDET": {
+                    "description": "Anticipated frame synchronization\n              detection",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CNRDY": {
+                    "description": "Codec not ready",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FREQ": {
+                    "description": "FIFO request",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "WCKCFG": {
+                    "description": "Wrong clock configuration flag. This bit\n              is read only.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MUTEDET": {
+                    "description": "Mute detection",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OVRUDR": {
+                    "description": "Overrun / underrun",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ACLRFR": {
+              "description": "AClear flag register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LFSDET": {
+                    "description": "Clear late frame synchronization\n              detection flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CAFSDET": {
+                    "description": "Clear anticipated frame synchronization\n              detection flag.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CNRDY": {
+                    "description": "Clear codec not ready flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "WCKCFG": {
+                    "description": "Clear wrong clock configuration\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MUTEDET": {
+                    "description": "Mute detection flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OVRUDR": {
+                    "description": "Clear overrun / underrun",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ADR": {
+              "description": "AData register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Data",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "LTDC": {
+        "description": "LCD-TFT Controller",
+        "children": {
+          "registers": {
+            "SSCR": {
+              "description": "Synchronization Size Configuration\n          Register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HSW": {
+                    "description": "Horizontal Synchronization Width (in\n              units of pixel clock period)",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "VSH": {
+                    "description": "Vertical Synchronization Height (in\n              units of horizontal scan line)",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "BPCR": {
+              "description": "Back Porch Configuration\n          Register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AHBP": {
+                    "description": "Accumulated Horizontal back porch (in\n              units of pixel clock period)",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "AVBP": {
+                    "description": "Accumulated Vertical back porch (in\n              units of horizontal scan line)",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "AWCR": {
+              "description": "Active Width Configuration\n          Register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AAV": {
+                    "description": "AAV",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "AAH": {
+                    "description": "Accumulated Active Height (in units of\n              horizontal scan line)",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "TWCR": {
+              "description": "Total Width Configuration\n          Register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TOTALW": {
+                    "description": "Total Width (in units of pixel clock\n              period)",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "TOTALH": {
+                    "description": "Total Height (in units of horizontal\n              scan line)",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "GCR": {
+              "description": "Global Control Register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 8736,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HSPOL": {
+                    "description": "Horizontal Synchronization\n              Polarity",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "VSPOL": {
+                    "description": "Vertical Synchronization\n              Polarity",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DEPOL": {
+                    "description": "Data Enable Polarity",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "PCPOL": {
+                    "description": "Pixel Clock Polarity",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DEN": {
+                    "description": "Dither Enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DRW": {
+                    "description": "Dither Red Width",
+                    "offset": 12,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DGW": {
+                    "description": "Dither Green Width",
+                    "offset": 8,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DBW": {
+                    "description": "Dither Blue Width",
+                    "offset": 4,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "LTDCEN": {
+                    "description": "LCD-TFT controller enable\n              bit",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SRCR": {
+              "description": "Shadow Reload Configuration\n          Register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VBR": {
+                    "description": "Vertical Blanking Reload",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IMR": {
+                    "description": "Immediate Reload",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BCCR": {
+              "description": "Background Color Configuration\n          Register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BC": {
+                    "description": "Background Color Red value",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "Interrupt Enable Register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RRIE": {
+                    "description": "Register Reload interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TERRIE": {
+                    "description": "Transfer Error Interrupt\n              Enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FUIE": {
+                    "description": "FIFO Underrun Interrupt\n              Enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LIE": {
+                    "description": "Line Interrupt Enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ISR": {
+              "description": "Interrupt Status Register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RRIF": {
+                    "description": "Register Reload Interrupt\n              Flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TERRIF": {
+                    "description": "Transfer Error interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FUIF": {
+                    "description": "FIFO Underrun Interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LIF": {
+                    "description": "Line Interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "Interrupt Clear Register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CRRIF": {
+                    "description": "Clears Register Reload Interrupt\n              Flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CTERRIF": {
+                    "description": "Clears the Transfer Error Interrupt\n              Flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CFUIF": {
+                    "description": "Clears the FIFO Underrun Interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CLIF": {
+                    "description": "Clears the Line Interrupt\n              Flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LIPCR": {
+              "description": "Line Interrupt Position Configuration\n          Register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LIPOS": {
+                    "description": "Line Interrupt Position",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "CPSR": {
+              "description": "Current Position Status\n          Register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CXPOS": {
+                    "description": "Current X Position",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CYPOS": {
+                    "description": "Current Y Position",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CDSR": {
+              "description": "Current Display Status\n          Register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 15,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HSYNCS": {
+                    "description": "Horizontal Synchronization display\n              Status",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "VSYNCS": {
+                    "description": "Vertical Synchronization display\n              Status",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "HDES": {
+                    "description": "Horizontal Data Enable display\n              Status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VDES": {
+                    "description": "Vertical Data Enable display\n              Status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "L1CR": {
+              "description": "Layerx Control Register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLUTEN": {
+                    "description": "Color Look-Up Table Enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "COLKEN": {
+                    "description": "Color Keying Enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LEN": {
+                    "description": "Layer Enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "L1WHPCR": {
+              "description": "Layerx Window Horizontal Position\n          Configuration Register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WHSPPOS": {
+                    "description": "Window Horizontal Stop\n              Position",
+                    "offset": 16,
+                    "size": 12
+                  },
+                  "WHSTPOS": {
+                    "description": "Window Horizontal Start\n              Position",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "L1WVPCR": {
+              "description": "Layerx Window Vertical Position\n          Configuration Register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WVSPPOS": {
+                    "description": "Window Vertical Stop\n              Position",
+                    "offset": 16,
+                    "size": 11
+                  },
+                  "WVSTPOS": {
+                    "description": "Window Vertical Start\n              Position",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "L1CKCR": {
+              "description": "Layerx Color Keying Configuration\n          Register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKRED": {
+                    "description": "Color Key Red value",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "CKGREEN": {
+                    "description": "Color Key Green value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "CKBLUE": {
+                    "description": "Color Key Blue value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L1PFCR": {
+              "description": "Layerx Pixel Format Configuration\n          Register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PF": {
+                    "description": "Pixel Format",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "L1CACR": {
+              "description": "Layerx Constant Alpha Configuration\n          Register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONSTA": {
+                    "description": "Constant Alpha",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L1DCCR": {
+              "description": "Layerx Default Color Configuration\n          Register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCALPHA": {
+                    "description": "Default Color Alpha",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DCRED": {
+                    "description": "Default Color Red",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DCGREEN": {
+                    "description": "Default Color Green",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DCBLUE": {
+                    "description": "Default Color Blue",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L1BFCR": {
+              "description": "Layerx Blending Factors Configuration\n          Register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 1543,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BF1": {
+                    "description": "Blending Factor 1",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "BF2": {
+                    "description": "Blending Factor 2",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "L1CFBAR": {
+              "description": "Layerx Color Frame Buffer Address\n          Register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBADD": {
+                    "description": "Color Frame Buffer Start\n              Address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "L1CFBLR": {
+              "description": "Layerx Color Frame Buffer Length\n          Register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBP": {
+                    "description": "Color Frame Buffer Pitch in\n              bytes",
+                    "offset": 16,
+                    "size": 13
+                  },
+                  "CFBLL": {
+                    "description": "Color Frame Buffer Line\n              Length",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "L1CFBLNR": {
+              "description": "Layerx ColorFrame Buffer Line Number\n          Register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBLNBR": {
+                    "description": "Frame Buffer Line Number",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "L1CLUTWR": {
+              "description": "Layerx CLUT Write Register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CLUTADD": {
+                    "description": "CLUT Address",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "RED": {
+                    "description": "Red value",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "GREEN": {
+                    "description": "Green value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BLUE": {
+                    "description": "Blue value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L2CR": {
+              "description": "Layerx Control Register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLUTEN": {
+                    "description": "Color Look-Up Table Enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "COLKEN": {
+                    "description": "Color Keying Enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LEN": {
+                    "description": "Layer Enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "L2WHPCR": {
+              "description": "Layerx Window Horizontal Position\n          Configuration Register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WHSPPOS": {
+                    "description": "Window Horizontal Stop\n              Position",
+                    "offset": 16,
+                    "size": 12
+                  },
+                  "WHSTPOS": {
+                    "description": "Window Horizontal Start\n              Position",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "L2WVPCR": {
+              "description": "Layerx Window Vertical Position\n          Configuration Register",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WVSPPOS": {
+                    "description": "Window Vertical Stop\n              Position",
+                    "offset": 16,
+                    "size": 11
+                  },
+                  "WVSTPOS": {
+                    "description": "Window Vertical Start\n              Position",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "L2CKCR": {
+              "description": "Layerx Color Keying Configuration\n          Register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKRED": {
+                    "description": "Color Key Red value",
+                    "offset": 15,
+                    "size": 9
+                  },
+                  "CKGREEN": {
+                    "description": "Color Key Green value",
+                    "offset": 8,
+                    "size": 7
+                  },
+                  "CKBLUE": {
+                    "description": "Color Key Blue value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L2PFCR": {
+              "description": "Layerx Pixel Format Configuration\n          Register",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PF": {
+                    "description": "Pixel Format",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "L2CACR": {
+              "description": "Layerx Constant Alpha Configuration\n          Register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONSTA": {
+                    "description": "Constant Alpha",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L2DCCR": {
+              "description": "Layerx Default Color Configuration\n          Register",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCALPHA": {
+                    "description": "Default Color Alpha",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DCRED": {
+                    "description": "Default Color Red",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DCGREEN": {
+                    "description": "Default Color Green",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DCBLUE": {
+                    "description": "Default Color Blue",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "L2BFCR": {
+              "description": "Layerx Blending Factors Configuration\n          Register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 1543,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BF1": {
+                    "description": "Blending Factor 1",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "BF2": {
+                    "description": "Blending Factor 2",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "L2CFBAR": {
+              "description": "Layerx Color Frame Buffer Address\n          Register",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBADD": {
+                    "description": "Color Frame Buffer Start\n              Address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "L2CFBLR": {
+              "description": "Layerx Color Frame Buffer Length\n          Register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBP": {
+                    "description": "Color Frame Buffer Pitch in\n              bytes",
+                    "offset": 16,
+                    "size": 13
+                  },
+                  "CFBLL": {
+                    "description": "Color Frame Buffer Line\n              Length",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "L2CFBLNR": {
+              "description": "Layerx ColorFrame Buffer Line Number\n          Register",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CFBLNBR": {
+                    "description": "Frame Buffer Line Number",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "L2CLUTWR": {
+              "description": "Layerx CLUT Write Register",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CLUTADD": {
+                    "description": "CLUT Address",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "RED": {
+                    "description": "Red value",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "GREEN": {
+                    "description": "Green value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BLUE": {
+                    "description": "Blue value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_HS_PWRCLK": {
+        "description": "USB on the go high speed",
+        "children": {
+          "registers": {
+            "OTG_HS_PCGCR": {
+              "description": "Power and clock gating control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STPPCLK": {
+                    "description": "Stop PHY clock",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "GATEHCLK": {
+                    "description": "Gate HCLK",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PHYSUSP": {
+                    "description": "PHY suspended",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_HS_DEVICE": {
+        "description": "USB on the go high speed",
+        "children": {
+          "registers": {
+            "OTG_HS_DCFG": {
+              "description": "OTG_HS device configuration\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 35651584,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DSPD": {
+                    "description": "Device speed",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "NZLSOHSK": {
+                    "description": "Nonzero-length status OUT\n              handshake",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 4,
+                    "size": 7
+                  },
+                  "PFIVL": {
+                    "description": "Periodic (micro)frame\n              interval",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "PERSCHIVL": {
+                    "description": "Periodic scheduling\n              interval",
+                    "offset": 24,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DCTL": {
+              "description": "OTG_HS device control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWUSIG": {
+                    "description": "Remote wakeup signaling",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SDIS": {
+                    "description": "Soft disconnect",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GINSTS": {
+                    "description": "Global IN NAK status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GONSTS": {
+                    "description": "Global OUT NAK status",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TCTL": {
+                    "description": "Test control",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SGINAK": {
+                    "description": "Set global IN NAK",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CGINAK": {
+                    "description": "Clear global IN NAK",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SGONAK": {
+                    "description": "Set global OUT NAK",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CGONAK": {
+                    "description": "Clear global OUT NAK",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "POPRGDNE": {
+                    "description": "Power-on programming done",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DSTS": {
+              "description": "OTG_HS device status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SUSPSTS": {
+                    "description": "Suspend status",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ENUMSPD": {
+                    "description": "Enumerated speed",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "EERR": {
+                    "description": "Erratic error",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FNSOF": {
+                    "description": "Frame number of the received\n              SOF",
+                    "offset": 8,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPMSK": {
+              "description": "OTG_HS device IN endpoint common interrupt\n          mask register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOM": {
+                    "description": "Timeout condition mask (nonisochronous\n              endpoints)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFEMSK": {
+                    "description": "IN token received when TxFIFO empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNMM": {
+                    "description": "IN token received with EP mismatch\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INEPNEM": {
+                    "description": "IN endpoint NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFURM": {
+                    "description": "FIFO underrun mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BIM": {
+                    "description": "BNA interrupt mask",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPMSK": {
+              "description": "OTG_HS device OUT endpoint common interrupt\n          mask register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUPM": {
+                    "description": "SETUP phase done mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDM": {
+                    "description": "OUT token received when endpoint\n              disabled mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets received\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OPEM": {
+                    "description": "OUT packet error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BOIM": {
+                    "description": "BNA interrupt mask",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DAINT": {
+              "description": "OTG_HS device all endpoints interrupt\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IEPINT": {
+                    "description": "IN endpoint interrupt bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt\n              bits",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DAINTMSK": {
+              "description": "OTG_HS all endpoints interrupt mask\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEPM": {
+                    "description": "IN EP interrupt mask bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OEPM": {
+                    "description": "OUT EP interrupt mask bits",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DVBUSDIS": {
+              "description": "OTG_HS device VBUS discharge time\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 6103,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VBUSDT": {
+                    "description": "Device VBUS discharge time",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DVBUSPULSE": {
+              "description": "OTG_HS device VBUS pulsing time\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 1464,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DVBUSP": {
+                    "description": "Device VBUS pulsing time",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTHRCTL": {
+              "description": "OTG_HS Device threshold control\n          register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NONISOTHREN": {
+                    "description": "Nonisochronous IN endpoints threshold\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ISOTHREN": {
+                    "description": "ISO IN endpoint threshold\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXTHRLEN": {
+                    "description": "Transmit threshold length",
+                    "offset": 2,
+                    "size": 9
+                  },
+                  "RXTHREN": {
+                    "description": "Receive threshold enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RXTHRLEN": {
+                    "description": "Receive threshold length",
+                    "offset": 17,
+                    "size": 9
+                  },
+                  "ARPEN": {
+                    "description": "Arbiter parking enable",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPEMPMSK": {
+              "description": "OTG_HS device IN endpoint FIFO empty\n          interrupt mask register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXFEM": {
+                    "description": "IN EP Tx FIFO empty interrupt mask\n              bits",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DEACHINT": {
+              "description": "OTG_HS device each endpoint interrupt\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEP1INT": {
+                    "description": "IN endpoint 1interrupt bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OEP1INT": {
+                    "description": "OUT endpoint 1 interrupt\n              bit",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DEACHINTMSK": {
+              "description": "OTG_HS device each endpoint interrupt\n          register mask",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEP1INTM": {
+                    "description": "IN Endpoint 1 interrupt mask\n              bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OEP1INTM": {
+                    "description": "OUT Endpoint 1 interrupt mask\n              bit",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPEACHMSK1": {
+              "description": "OTG_HS device each in endpoint-1 interrupt\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOM": {
+                    "description": "Timeout condition mask (nonisochronous\n              endpoints)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFEMSK": {
+                    "description": "IN token received when TxFIFO empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNMM": {
+                    "description": "IN token received with EP mismatch\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INEPNEM": {
+                    "description": "IN endpoint NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFURM": {
+                    "description": "FIFO underrun mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BIM": {
+                    "description": "BNA interrupt mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK interrupt mask",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPEACHMSK1": {
+              "description": "OTG_HS device each OUT endpoint-1 interrupt\n          register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOM": {
+                    "description": "Timeout condition mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFEMSK": {
+                    "description": "IN token received when TxFIFO empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNMM": {
+                    "description": "IN token received with EP mismatch\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INEPNEM": {
+                    "description": "IN endpoint NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFURM": {
+                    "description": "OUT packet error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BIM": {
+                    "description": "BNA interrupt mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BERRM": {
+                    "description": "Bubble error interrupt\n              mask",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK interrupt mask",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "NYETM": {
+                    "description": "NYET interrupt mask",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL0": {
+              "description": "OTG device endpoint-0 control\n          register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL1": {
+              "description": "OTG device endpoint-1 control\n          register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL2": {
+              "description": "OTG device endpoint-2 control\n          register",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL3": {
+              "description": "OTG device endpoint-3 control\n          register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL4": {
+              "description": "OTG device endpoint-4 control\n          register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL5": {
+              "description": "OTG device endpoint-5 control\n          register",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL6": {
+              "description": "OTG device endpoint-6 control\n          register",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPCTL7": {
+              "description": "OTG device endpoint-7 control\n          register",
+              "offset": 480,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even/odd frame",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT0": {
+              "description": "OTG device endpoint-0 interrupt\n          register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT1": {
+              "description": "OTG device endpoint-1 interrupt\n          register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT2": {
+              "description": "OTG device endpoint-2 interrupt\n          register",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT3": {
+              "description": "OTG device endpoint-3 interrupt\n          register",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT4": {
+              "description": "OTG device endpoint-4 interrupt\n          register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT5": {
+              "description": "OTG device endpoint-5 interrupt\n          register",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT6": {
+              "description": "OTG device endpoint-6 interrupt\n          register",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPINT7": {
+              "description": "OTG device endpoint-7 interrupt\n          register",
+              "offset": 488,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "Timeout condition",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "IN token received when TxFIFO is\n              empty",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFOUDRN": {
+                    "description": "Transmit Fifo Underrun",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BNA": {
+                    "description": "Buffer not available\n              interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PKTDRPSTS": {
+                    "description": "Packet dropped status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "Babble error interrupt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK interrupt",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ0": {
+              "description": "OTG_HS device IN endpoint 0 transfer size\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPDMA1": {
+              "description": "OTG_HS device endpoint-1 DMA address\n          register",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPDMA2": {
+              "description": "OTG_HS device endpoint-2 DMA address\n          register",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPDMA3": {
+              "description": "OTG_HS device endpoint-3 DMA address\n          register",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPDMA4": {
+              "description": "OTG_HS device endpoint-4 DMA address\n          register",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPDMA5": {
+              "description": "OTG_HS device endpoint-5 DMA address\n          register",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS0": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS1": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS2": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS3": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS4": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 408,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DTXFSTS5": {
+              "description": "OTG_HS device IN endpoint transmit FIFO\n          status register",
+              "offset": 440,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              avail",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ1": {
+              "description": "OTG_HS device endpoint transfer size\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ2": {
+              "description": "OTG_HS device endpoint transfer size\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ3": {
+              "description": "OTG_HS device endpoint transfer size\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ4": {
+              "description": "OTG_HS device endpoint transfer size\n          register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTSIZ5": {
+              "description": "OTG_HS device endpoint transfer size\n          register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPCTL0": {
+              "description": "OTG_HS device control OUT endpoint 0 control\n          register",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "SNPM": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPCTL1": {
+              "description": "OTG device endpoint-1 control\n          register",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even odd frame/Endpoint data\n              PID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "SNPM": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID/Set even\n              frame",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPCTL2": {
+              "description": "OTG device endpoint-2 control\n          register",
+              "offset": 832,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even odd frame/Endpoint data\n              PID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "SNPM": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID/Set even\n              frame",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPCTL3": {
+              "description": "OTG device endpoint-3 control\n          register",
+              "offset": 864,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EONUM_DPID": {
+                    "description": "Even odd frame/Endpoint data\n              PID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "SNPM": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "Stall": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "Set DATA0 PID/Set even\n              frame",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SODDFRM": {
+                    "description": "Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT0": {
+              "description": "OTG_HS device endpoint-0 interrupt\n          register",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT1": {
+              "description": "OTG_HS device endpoint-1 interrupt\n          register",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT2": {
+              "description": "OTG_HS device endpoint-2 interrupt\n          register",
+              "offset": 840,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT3": {
+              "description": "OTG_HS device endpoint-3 interrupt\n          register",
+              "offset": 872,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT4": {
+              "description": "OTG_HS device endpoint-4 interrupt\n          register",
+              "offset": 904,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT5": {
+              "description": "OTG_HS device endpoint-5 interrupt\n          register",
+              "offset": 936,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT6": {
+              "description": "OTG_HS device endpoint-6 interrupt\n          register",
+              "offset": 968,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPINT7": {
+              "description": "OTG_HS device endpoint-7 interrupt\n          register",
+              "offset": 1000,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed\n              interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "Endpoint disabled\n              interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "SETUP phase done",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OUT token received when endpoint\n              disabled",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "B2BSTUP": {
+                    "description": "Back-to-back SETUP packets\n              received",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "NYET interrupt",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPTSIZ0": {
+              "description": "OTG_HS device endpoint-1 transfer size\n          register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "STUPCNT": {
+                    "description": "SETUP packet count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPTSIZ1": {
+              "description": "OTG_HS device endpoint-2 transfer size\n          register",
+              "offset": 816,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPTSIZ2": {
+              "description": "OTG_HS device endpoint-3 transfer size\n          register",
+              "offset": 848,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPTSIZ3": {
+              "description": "OTG_HS device endpoint-4 transfer size\n          register",
+              "offset": 880,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_DOEPTSIZ4": {
+              "description": "OTG_HS device endpoint-5 transfer size\n          register",
+              "offset": 912,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_HS_HOST": {
+        "description": "USB on the go high speed",
+        "children": {
+          "registers": {
+            "OTG_HS_HCFG": {
+              "description": "OTG_HS host configuration\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSLSPCS": {
+                    "description": "FS/LS PHY clock select",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "FSLSS": {
+                    "description": "FS- and LS-only support",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_HFIR": {
+              "description": "OTG_HS Host frame interval\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 60000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRIVL": {
+                    "description": "Frame interval",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_HFNUM": {
+              "description": "OTG_HS host frame number/frame time\n          remaining register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 16383,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FRNUM": {
+                    "description": "Frame number",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "FTREM": {
+                    "description": "Frame time remaining",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_HPTXSTS": {
+              "description": "OTG_HS_Host periodic transmit FIFO/queue\n          status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 524544,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTXFSAVL": {
+                    "description": "Periodic transmit data FIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PTXQSAV": {
+                    "description": "Periodic transmit request queue space\n              available",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "PTXQTOP": {
+                    "description": "Top of the periodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_HAINT": {
+              "description": "OTG_HS Host all channels interrupt\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HAINT": {
+                    "description": "Channel interrupts",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_HAINTMSK": {
+              "description": "OTG_HS host all channels interrupt mask\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HAINTM": {
+                    "description": "Channel interrupt mask",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_HPRT": {
+              "description": "OTG_HS host port control and status\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCSTS": {
+                    "description": "Port connect status",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PCDET": {
+                    "description": "Port connect detected",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PENA": {
+                    "description": "Port enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PENCHNG": {
+                    "description": "Port enable/disable change",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "POCA": {
+                    "description": "Port overcurrent active",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "POCCHNG": {
+                    "description": "Port overcurrent change",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PRES": {
+                    "description": "Port resume",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PSUSP": {
+                    "description": "Port suspend",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PRST": {
+                    "description": "Port reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PLSTS": {
+                    "description": "Port line status",
+                    "offset": 10,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PPWR": {
+                    "description": "Port power",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PTCTL": {
+                    "description": "Port test control",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "PSPD": {
+                    "description": "Port speed",
+                    "offset": 17,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR0": {
+              "description": "OTG_HS host channel-0 characteristics\n          register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR1": {
+              "description": "OTG_HS host channel-1 characteristics\n          register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR2": {
+              "description": "OTG_HS host channel-2 characteristics\n          register",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR3": {
+              "description": "OTG_HS host channel-3 characteristics\n          register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR4": {
+              "description": "OTG_HS host channel-4 characteristics\n          register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR5": {
+              "description": "OTG_HS host channel-5 characteristics\n          register",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR6": {
+              "description": "OTG_HS host channel-6 characteristics\n          register",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR7": {
+              "description": "OTG_HS host channel-7 characteristics\n          register",
+              "offset": 480,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR8": {
+              "description": "OTG_HS host channel-8 characteristics\n          register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR9": {
+              "description": "OTG_HS host channel-9 characteristics\n          register",
+              "offset": 544,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR10": {
+              "description": "OTG_HS host channel-10 characteristics\n          register",
+              "offset": 576,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCCHAR11": {
+              "description": "OTG_HS host channel-11 characteristics\n          register",
+              "offset": 608,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MC": {
+                    "description": "Multi Count (MC) / Error Count\n              (EC)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT0": {
+              "description": "OTG_HS host channel-0 split control\n          register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT1": {
+              "description": "OTG_HS host channel-1 split control\n          register",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT2": {
+              "description": "OTG_HS host channel-2 split control\n          register",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT3": {
+              "description": "OTG_HS host channel-3 split control\n          register",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT4": {
+              "description": "OTG_HS host channel-4 split control\n          register",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT5": {
+              "description": "OTG_HS host channel-5 split control\n          register",
+              "offset": 420,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT6": {
+              "description": "OTG_HS host channel-6 split control\n          register",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT7": {
+              "description": "OTG_HS host channel-7 split control\n          register",
+              "offset": 484,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT8": {
+              "description": "OTG_HS host channel-8 split control\n          register",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT9": {
+              "description": "OTG_HS host channel-9 split control\n          register",
+              "offset": 548,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT10": {
+              "description": "OTG_HS host channel-10 split control\n          register",
+              "offset": 580,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCSPLT11": {
+              "description": "OTG_HS host channel-11 split control\n          register",
+              "offset": 612,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRTADDR": {
+                    "description": "Port address",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "HUBADDR": {
+                    "description": "Hub address",
+                    "offset": 7,
+                    "size": 7
+                  },
+                  "XACTPOS": {
+                    "description": "XACTPOS",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "COMPLSPLT": {
+                    "description": "Do complete split",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SPLITEN": {
+                    "description": "Split enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT0": {
+              "description": "OTG_HS host channel-11 interrupt\n          register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT1": {
+              "description": "OTG_HS host channel-1 interrupt\n          register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT2": {
+              "description": "OTG_HS host channel-2 interrupt\n          register",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT3": {
+              "description": "OTG_HS host channel-3 interrupt\n          register",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT4": {
+              "description": "OTG_HS host channel-4 interrupt\n          register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT5": {
+              "description": "OTG_HS host channel-5 interrupt\n          register",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT6": {
+              "description": "OTG_HS host channel-6 interrupt\n          register",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT7": {
+              "description": "OTG_HS host channel-7 interrupt\n          register",
+              "offset": 488,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT8": {
+              "description": "OTG_HS host channel-8 interrupt\n          register",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT9": {
+              "description": "OTG_HS host channel-9 interrupt\n          register",
+              "offset": 552,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT10": {
+              "description": "OTG_HS host channel-10 interrupt\n          register",
+              "offset": 584,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINT11": {
+              "description": "OTG_HS host channel-11 interrupt\n          register",
+              "offset": 616,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "Response received\n              interrupt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK0": {
+              "description": "OTG_HS host channel-11 interrupt mask\n          register",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK1": {
+              "description": "OTG_HS host channel-1 interrupt mask\n          register",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK2": {
+              "description": "OTG_HS host channel-2 interrupt mask\n          register",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK3": {
+              "description": "OTG_HS host channel-3 interrupt mask\n          register",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK4": {
+              "description": "OTG_HS host channel-4 interrupt mask\n          register",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK5": {
+              "description": "OTG_HS host channel-5 interrupt mask\n          register",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK6": {
+              "description": "OTG_HS host channel-6 interrupt mask\n          register",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK7": {
+              "description": "OTG_HS host channel-7 interrupt mask\n          register",
+              "offset": 492,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK8": {
+              "description": "OTG_HS host channel-8 interrupt mask\n          register",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK9": {
+              "description": "OTG_HS host channel-9 interrupt mask\n          register",
+              "offset": 556,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK10": {
+              "description": "OTG_HS host channel-10 interrupt mask\n          register",
+              "offset": 588,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCINTMSK11": {
+              "description": "OTG_HS host channel-11 interrupt mask\n          register",
+              "offset": 620,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AHBERR": {
+                    "description": "AHB error",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ0": {
+              "description": "OTG_HS host channel-11 transfer size\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ1": {
+              "description": "OTG_HS host channel-1 transfer size\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ2": {
+              "description": "OTG_HS host channel-2 transfer size\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ3": {
+              "description": "OTG_HS host channel-3 transfer size\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ4": {
+              "description": "OTG_HS host channel-4 transfer size\n          register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ5": {
+              "description": "OTG_HS host channel-5 transfer size\n          register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ6": {
+              "description": "OTG_HS host channel-6 transfer size\n          register",
+              "offset": 464,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ7": {
+              "description": "OTG_HS host channel-7 transfer size\n          register",
+              "offset": 496,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ8": {
+              "description": "OTG_HS host channel-8 transfer size\n          register",
+              "offset": 528,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ9": {
+              "description": "OTG_HS host channel-9 transfer size\n          register",
+              "offset": 560,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ10": {
+              "description": "OTG_HS host channel-10 transfer size\n          register",
+              "offset": 592,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCTSIZ11": {
+              "description": "OTG_HS host channel-11 transfer size\n          register",
+              "offset": 624,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA0": {
+              "description": "OTG_HS host channel-0 DMA address\n          register",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA1": {
+              "description": "OTG_HS host channel-1 DMA address\n          register",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA2": {
+              "description": "OTG_HS host channel-2 DMA address\n          register",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA3": {
+              "description": "OTG_HS host channel-3 DMA address\n          register",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA4": {
+              "description": "OTG_HS host channel-4 DMA address\n          register",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA5": {
+              "description": "OTG_HS host channel-5 DMA address\n          register",
+              "offset": 436,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA6": {
+              "description": "OTG_HS host channel-6 DMA address\n          register",
+              "offset": 468,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA7": {
+              "description": "OTG_HS host channel-7 DMA address\n          register",
+              "offset": 500,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA8": {
+              "description": "OTG_HS host channel-8 DMA address\n          register",
+              "offset": 532,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA9": {
+              "description": "OTG_HS host channel-9 DMA address\n          register",
+              "offset": 564,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA10": {
+              "description": "OTG_HS host channel-10 DMA address\n          register",
+              "offset": 596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HCDMA11": {
+              "description": "OTG_HS host channel-11 DMA address\n          register",
+              "offset": 628,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAADDR": {
+                    "description": "DMA address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SDIO": {
+        "description": "Secure digital input/output\n      interface",
+        "children": {
+          "registers": {
+            "POWER": {
+              "description": "power control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWRCTRL": {
+                    "description": "PWRCTRL",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLKCR": {
+              "description": "SDI clock control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HWFC_EN": {
+                    "description": "HW Flow Control enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "NEGEDGE": {
+                    "description": "SDIO_CK dephasing selection\n              bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WIDBUS": {
+                    "description": "Wide bus mode enable bit",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "BYPASS": {
+                    "description": "Clock divider bypass enable\n              bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PWRSAV": {
+                    "description": "Power saving configuration\n              bit",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CLKEN": {
+                    "description": "Clock enable bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CLKDIV": {
+                    "description": "Clock divide factor",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ARG": {
+              "description": "argument register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CMDARG": {
+                    "description": "Command argument",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMD": {
+              "description": "command register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CE_ATACMD": {
+                    "description": "CE-ATA command",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "nIEN": {
+                    "description": "not Interrupt Enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ENCMDcompl": {
+                    "description": "Enable CMD completion",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SDIOSuspend": {
+                    "description": "SD I/O suspend command",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CPSMEN": {
+                    "description": "Command path state machine (CPSM) Enable\n              bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WAITPEND": {
+                    "description": "CPSM Waits for ends of data transfer\n              (CmdPend internal signal).",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WAITINT": {
+                    "description": "CPSM waits for interrupt\n              request",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WAITRESP": {
+                    "description": "Wait for response bits",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CMDINDEX": {
+                    "description": "Command index",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "RESPCMD": {
+              "description": "command response register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RESPCMD": {
+                    "description": "Response command index",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "RESP1": {
+              "description": "response 1..4 register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS1": {
+                    "description": "see Table 132.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RESP2": {
+              "description": "response 1..4 register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS2": {
+                    "description": "see Table 132.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RESP3": {
+              "description": "response 1..4 register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS3": {
+                    "description": "see Table 132.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RESP4": {
+              "description": "response 1..4 register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CARDSTATUS4": {
+                    "description": "see Table 132.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DTIMER": {
+              "description": "data timer register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATATIME": {
+                    "description": "Data timeout period",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DLEN": {
+              "description": "data length register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATALENGTH": {
+                    "description": "Data length value",
+                    "offset": 0,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "DCTRL": {
+              "description": "data control register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDIOEN": {
+                    "description": "SD I/O enable functions",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RWMOD": {
+                    "description": "Read wait mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RWSTOP": {
+                    "description": "Read wait stop",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RWSTART": {
+                    "description": "Read wait start",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DBLOCKSIZE": {
+                    "description": "Data block size",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "DMAEN": {
+                    "description": "DMA enable bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DTMODE": {
+                    "description": "Data transfer mode selection 1: Stream\n              or SDIO multibyte data transfer.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DTDIR": {
+                    "description": "Data transfer direction\n              selection",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DTEN": {
+                    "description": "DTEN",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DCOUNT": {
+              "description": "data counter register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATACOUNT": {
+                    "description": "Data count value",
+                    "offset": 0,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "STA": {
+              "description": "status register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CEATAEND": {
+                    "description": "CE-ATA command completion signal\n              received for CMD61",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "SDIOIT": {
+                    "description": "SDIO interrupt received",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "RXDAVL": {
+                    "description": "Data available in receive\n              FIFO",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXDAVL": {
+                    "description": "Data available in transmit\n              FIFO",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RXFIFOE": {
+                    "description": "Receive FIFO empty",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TXFIFOE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RXFIFOF": {
+                    "description": "Receive FIFO full",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TXFIFOF": {
+                    "description": "Transmit FIFO full",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RXFIFOHF": {
+                    "description": "Receive FIFO half full: there are at\n              least 8 words in the FIFO",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TXFIFOHE": {
+                    "description": "Transmit FIFO half empty: at least 8\n              words can be written into the FIFO",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RXACT": {
+                    "description": "Data receive in progress",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TXACT": {
+                    "description": "Data transmit in progress",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CMDACT": {
+                    "description": "Command transfer in\n              progress",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DBCKEND": {
+                    "description": "Data block sent/received (CRC check\n              passed)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "STBITERR": {
+                    "description": "Start bit not detected on all data\n              signals in wide bus mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DATAEND": {
+                    "description": "Data end (data counter, SDIDCOUNT, is\n              zero)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CMDSENT": {
+                    "description": "Command sent (no response\n              required)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMDREND": {
+                    "description": "Command response received (CRC check\n              passed)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXOVERR": {
+                    "description": "Received FIFO overrun\n              error",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXUNDERR": {
+                    "description": "Transmit FIFO underrun\n              error",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DTIMEOUT": {
+                    "description": "Data timeout",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CTIMEOUT": {
+                    "description": "Command response timeout",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DCRCFAIL": {
+                    "description": "Data block sent/received (CRC check\n              failed)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CCRCFAIL": {
+                    "description": "Command response received (CRC check\n              failed)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "interrupt clear register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEATAENDC": {
+                    "description": "CEATAEND flag clear bit",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "SDIOITC": {
+                    "description": "SDIOIT flag clear bit",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DBCKENDC": {
+                    "description": "DBCKEND flag clear bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "STBITERRC": {
+                    "description": "STBITERR flag clear bit",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DATAENDC": {
+                    "description": "DATAEND flag clear bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CMDSENTC": {
+                    "description": "CMDSENT flag clear bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMDRENDC": {
+                    "description": "CMDREND flag clear bit",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXOVERRC": {
+                    "description": "RXOVERR flag clear bit",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXUNDERRC": {
+                    "description": "TXUNDERR flag clear bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DTIMEOUTC": {
+                    "description": "DTIMEOUT flag clear bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CTIMEOUTC": {
+                    "description": "CTIMEOUT flag clear bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DCRCFAILC": {
+                    "description": "DCRCFAIL flag clear bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CCRCFAILC": {
+                    "description": "CCRCFAIL flag clear bit",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MASK": {
+              "description": "mask register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEATAENDIE": {
+                    "description": "CE-ATA command completion signal\n              received interrupt enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "SDIOITIE": {
+                    "description": "SDIO mode interrupt received interrupt\n              enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "RXDAVLIE": {
+                    "description": "Data available in Rx FIFO interrupt\n              enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXDAVLIE": {
+                    "description": "Data available in Tx FIFO interrupt\n              enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RXFIFOEIE": {
+                    "description": "Rx FIFO empty interrupt\n              enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TXFIFOEIE": {
+                    "description": "Tx FIFO empty interrupt\n              enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RXFIFOFIE": {
+                    "description": "Rx FIFO full interrupt\n              enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TXFIFOFIE": {
+                    "description": "Tx FIFO full interrupt\n              enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RXFIFOHFIE": {
+                    "description": "Rx FIFO half full interrupt\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TXFIFOHEIE": {
+                    "description": "Tx FIFO half empty interrupt\n              enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RXACTIE": {
+                    "description": "Data receive acting interrupt\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TXACTIE": {
+                    "description": "Data transmit acting interrupt\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CMDACTIE": {
+                    "description": "Command acting interrupt\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DBCKENDIE": {
+                    "description": "Data block end interrupt\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "STBITERRIE": {
+                    "description": "Start bit error interrupt\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DATAENDIE": {
+                    "description": "Data end interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CMDSENTIE": {
+                    "description": "Command sent interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMDRENDIE": {
+                    "description": "Command response received interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXOVERRIE": {
+                    "description": "Rx FIFO overrun error interrupt\n              enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXUNDERRIE": {
+                    "description": "Tx FIFO underrun error interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DTIMEOUTIE": {
+                    "description": "Data timeout interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CTIMEOUTIE": {
+                    "description": "Command timeout interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DCRCFAILIE": {
+                    "description": "Data CRC fail interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CCRCFAILIE": {
+                    "description": "Command CRC fail interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FIFOCNT": {
+              "description": "FIFO counter register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FIFOCOUNT": {
+                    "description": "Remaining number of words to be written\n              to or read from the FIFO.",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "FIFO": {
+              "description": "data FIFO register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FIFOData": {
+                    "description": "Receive and transmit FIFO\n              data",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ADC1": {
+        "description": "Analog-to-digital converter",
+        "children": {
+          "registers": {
+            "SR": {
+              "description": "status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVR": {
+                    "description": "Overrun",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "STRT": {
+                    "description": "Regular channel start flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "JSTRT": {
+                    "description": "Injected channel start\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "JEOC": {
+                    "description": "Injected channel end of\n              conversion",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EOC": {
+                    "description": "Regular channel end of\n              conversion",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AWD": {
+                    "description": "Analog watchdog flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "control register 1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVRIE": {
+                    "description": "Overrun interrupt enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RES": {
+                    "description": "Resolution",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "AWDEN": {
+                    "description": "Analog watchdog enable on regular\n              channels",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "JAWDEN": {
+                    "description": "Analog watchdog enable on injected\n              channels",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DISCNUM": {
+                    "description": "Discontinuous mode channel\n              count",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "JDISCEN": {
+                    "description": "Discontinuous mode on injected\n              channels",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DISCEN": {
+                    "description": "Discontinuous mode on regular\n              channels",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "JAUTO": {
+                    "description": "Automatic injected group\n              conversion",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AWDSGL": {
+                    "description": "Enable the watchdog on a single channel\n              in scan mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SCAN": {
+                    "description": "Scan mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "JEOCIE": {
+                    "description": "Interrupt enable for injected\n              channels",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "AWDIE": {
+                    "description": "Analog watchdog interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EOCIE": {
+                    "description": "Interrupt enable for EOC",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "AWDCH": {
+                    "description": "Analog watchdog channel select\n              bits",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWSTART": {
+                    "description": "Start conversion of regular\n              channels",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EXTEN": {
+                    "description": "External trigger enable for regular\n              channels",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "EXTSEL": {
+                    "description": "External event select for regular\n              group",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "JSWSTART": {
+                    "description": "Start conversion of injected\n              channels",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "JEXTEN": {
+                    "description": "External trigger enable for injected\n              channels",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "JEXTSEL": {
+                    "description": "External event select for injected\n              group",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ALIGN": {
+                    "description": "Data alignment",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EOCS": {
+                    "description": "End of conversion\n              selection",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DDS": {
+                    "description": "DMA disable selection (for single ADC\n              mode)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DMA": {
+                    "description": "Direct memory access mode (for single\n              ADC mode)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CONT": {
+                    "description": "Continuous conversion",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ADON": {
+                    "description": "A/D Converter ON / OFF",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMPR1": {
+              "description": "sample time register 1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMPx_x": {
+                    "description": "Sample time bits",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SMPR2": {
+              "description": "sample time register 2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMPx_x": {
+                    "description": "Sample time bits",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "JOFR1": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET1": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR2": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET2": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR3": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET3": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "JOFR4": {
+              "description": "injected channel data offset register\n          x",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JOFFSET4": {
+                    "description": "Data offset for injected channel\n              x",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "HTR": {
+              "description": "watchdog higher threshold\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HT": {
+                    "description": "Analog watchdog higher\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "LTR": {
+              "description": "watchdog lower threshold\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LT": {
+                    "description": "Analog watchdog lower\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "SQR1": {
+              "description": "regular sequence register 1",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "L": {
+                    "description": "Regular channel sequence\n              length",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "SQ16": {
+                    "description": "16th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ15": {
+                    "description": "15th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ14": {
+                    "description": "14th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ13": {
+                    "description": "13th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SQR2": {
+              "description": "regular sequence register 2",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ12": {
+                    "description": "12th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "SQ11": {
+                    "description": "11th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "SQ10": {
+                    "description": "10th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ9": {
+                    "description": "9th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ8": {
+                    "description": "8th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ7": {
+                    "description": "7th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SQR3": {
+              "description": "regular sequence register 3",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SQ6": {
+                    "description": "6th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "SQ5": {
+                    "description": "5th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "SQ4": {
+                    "description": "4th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SQ3": {
+                    "description": "3rd conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SQ2": {
+                    "description": "2nd conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SQ1": {
+                    "description": "1st conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "JSQR": {
+              "description": "injected sequence register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JL": {
+                    "description": "Injected sequence length",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "JSQ4": {
+                    "description": "4th conversion in injected\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "JSQ3": {
+                    "description": "3rd conversion in injected\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "JSQ2": {
+                    "description": "2nd conversion in injected\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "JSQ1": {
+                    "description": "1st conversion in injected\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "JDR1": {
+              "description": "injected data register x",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR2": {
+              "description": "injected data register x",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR3": {
+              "description": "injected data register x",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "JDR4": {
+              "description": "injected data register x",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "JDATA": {
+                    "description": "Injected data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "regular data register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Regular data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_HS_GLOBAL": {
+        "description": "USB on the go high speed",
+        "children": {
+          "registers": {
+            "OTG_HS_GOTGCTL": {
+              "description": "OTG_HS control and status\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRQSCS": {
+                    "description": "Session request success",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SRQ": {
+                    "description": "Session request",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HNGSCS": {
+                    "description": "Host negotiation success",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HNPRQ": {
+                    "description": "HNP request",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HSHNPEN": {
+                    "description": "Host set HNP enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DHNPEN": {
+                    "description": "Device HNP enabled",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CIDSTS": {
+                    "description": "Connector ID status",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DBCT": {
+                    "description": "Long/short debounce time",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ASVLD": {
+                    "description": "A-session valid",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BSVLD": {
+                    "description": "B-session valid",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_GOTGINT": {
+              "description": "OTG_HS interrupt register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEDET": {
+                    "description": "Session end detected",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SRSSCHG": {
+                    "description": "Session request success status\n              change",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNSSCHG": {
+                    "description": "Host negotiation success status\n              change",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HNGDET": {
+                    "description": "Host negotiation detected",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ADTOCHG": {
+                    "description": "A-device timeout change",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DBCDNE": {
+                    "description": "Debounce done",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_GAHBCFG": {
+              "description": "OTG_HS AHB configuration\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GINT": {
+                    "description": "Global interrupt mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HBSTLEN": {
+                    "description": "Burst length/type",
+                    "offset": 1,
+                    "size": 4
+                  },
+                  "DMAEN": {
+                    "description": "DMA enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFELVL": {
+                    "description": "TxFIFO empty level",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PTXFELVL": {
+                    "description": "Periodic TxFIFO empty\n              level",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_GUSBCFG": {
+              "description": "OTG_HS USB configuration\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 2560,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TOCAL": {
+                    "description": "FS timeout calibration",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "PHYSEL": {
+                    "description": "USB 2.0 high-speed ULPI PHY or USB 1.1\n              full-speed serial transceiver select",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SRPCAP": {
+                    "description": "SRP-capable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNPCAP": {
+                    "description": "HNP-capable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TRDT": {
+                    "description": "USB turnaround time",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "PHYLPCS": {
+                    "description": "PHY Low-power clock select",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ULPIFSLS": {
+                    "description": "ULPI FS/LS select",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ULPIAR": {
+                    "description": "ULPI Auto-resume",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "ULPICSM": {
+                    "description": "ULPI Clock SuspendM",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ULPIEVBUSD": {
+                    "description": "ULPI External VBUS Drive",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "ULPIEVBUSI": {
+                    "description": "ULPI external VBUS\n              indicator",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TSDPS": {
+                    "description": "TermSel DLine pulsing\n              selection",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PCCI": {
+                    "description": "Indicator complement",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PTCI": {
+                    "description": "Indicator pass through",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "ULPIIPD": {
+                    "description": "ULPI interface protect\n              disable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FHMOD": {
+                    "description": "Forced host mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FDMOD": {
+                    "description": "Forced peripheral mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CTXPKT": {
+                    "description": "Corrupt Tx packet",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRSTCTL": {
+              "description": "OTG_HS reset register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 536870912,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSRST": {
+                    "description": "Core soft reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HSRST": {
+                    "description": "HCLK soft reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FCRST": {
+                    "description": "Host frame counter reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RXFFLSH": {
+                    "description": "RxFIFO flush",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TXFFLSH": {
+                    "description": "TxFIFO flush",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "DMAREQ": {
+                    "description": "DMA request signal",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "AHBIDL": {
+                    "description": "AHB master idle",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OTG_HS_GINTSTS": {
+              "description": "OTG_HS core interrupt register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 67108896,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CMOD": {
+                    "description": "Current mode of operation",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMIS": {
+                    "description": "Mode mismatch interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGINT": {
+                    "description": "OTG interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOF": {
+                    "description": "Start of frame",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFLVL": {
+                    "description": "RxFIFO nonempty",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NPTXFE": {
+                    "description": "Nonperiodic TxFIFO empty",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GINAKEFF": {
+                    "description": "Global IN nonperiodic NAK\n              effective",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BOUTNAKEFF": {
+                    "description": "Global OUT NAK effective",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ESUSP": {
+                    "description": "Early suspend",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "USBSUSP": {
+                    "description": "USB suspend",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMDNE": {
+                    "description": "Enumeration done",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOODRP": {
+                    "description": "Isochronous OUT packet dropped\n              interrupt",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPF": {
+                    "description": "End of periodic frame\n              interrupt",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IEPINT": {
+                    "description": "IN endpoint interrupt",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IISOIXFR": {
+                    "description": "Incomplete isochronous IN\n              transfer",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PXFR_INCOMPISOOUT": {
+                    "description": "Incomplete periodic\n              transfer",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "DATAFSUSP": {
+                    "description": "Data fetch suspended",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "HPRTINT": {
+                    "description": "Host port interrupt",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCINT": {
+                    "description": "Host channels interrupt",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PTXFE": {
+                    "description": "Periodic TxFIFO empty",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CIDSCHG": {
+                    "description": "Connector ID status change",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCINT": {
+                    "description": "Disconnect detected\n              interrupt",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SRQINT": {
+                    "description": "Session request/new session detected\n              interrupt",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WKUINT": {
+                    "description": "Resume/remote wakeup detected\n              interrupt",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_GINTMSK": {
+              "description": "OTG_HS interrupt mask register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMISM": {
+                    "description": "Mode mismatch interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGINT": {
+                    "description": "OTG interrupt mask",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SOFM": {
+                    "description": "Start of frame mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFLVLM": {
+                    "description": "Receive FIFO nonempty mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "NPTXFEM": {
+                    "description": "Nonperiodic TxFIFO empty\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GINAKEFFM": {
+                    "description": "Global nonperiodic IN NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GONAKEFFM": {
+                    "description": "Global OUT NAK effective\n              mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ESUSPM": {
+                    "description": "Early suspend mask",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "USBSUSPM": {
+                    "description": "USB suspend mask",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset mask",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMDNEM": {
+                    "description": "Enumeration done mask",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOODRPM": {
+                    "description": "Isochronous OUT packet dropped interrupt\n              mask",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPFM": {
+                    "description": "End of periodic frame interrupt\n              mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPMISM": {
+                    "description": "Endpoint mismatch interrupt\n              mask",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "IEPINT": {
+                    "description": "IN endpoints interrupt\n              mask",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoints interrupt\n              mask",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IISOIXFRM": {
+                    "description": "Incomplete isochronous IN transfer\n              mask",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PXFRM_IISOOXFRM": {
+                    "description": "Incomplete periodic transfer\n              mask",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FSUSPM": {
+                    "description": "Data fetch suspended mask",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PRTIM": {
+                    "description": "Host port interrupt mask",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCIM": {
+                    "description": "Host channels interrupt\n              mask",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PTXFEM": {
+                    "description": "Periodic TxFIFO empty mask",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CIDSCHGM": {
+                    "description": "Connector ID status change\n              mask",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCINT": {
+                    "description": "Disconnect detected interrupt\n              mask",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SRQIM": {
+                    "description": "Session request/new session detected\n              interrupt mask",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WUIM": {
+                    "description": "Resume/remote wakeup detected interrupt\n              mask",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRXSTSR_Host": {
+              "description": "OTG_HS Receive status debug read register\n          (host mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CHNUM": {
+                    "description": "Channel number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRXSTSP_Host": {
+              "description": "OTG_HS status read and pop register (host\n          mode)",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CHNUM": {
+                    "description": "Channel number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRXFSIZ": {
+              "description": "OTG_HS Receive FIFO size\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFD": {
+                    "description": "RxFIFO depth",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_GNPTXFSIZ_Host": {
+              "description": "OTG_HS nonperiodic transmit FIFO size\n          register (host mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NPTXFSA": {
+                    "description": "Nonperiodic transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "NPTXFD": {
+                    "description": "Nonperiodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_TX0FSIZ_Peripheral": {
+              "description": "Endpoint 0 transmit FIFO size (peripheral\n          mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX0FSA": {
+                    "description": "Endpoint 0 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "TX0FD": {
+                    "description": "Endpoint 0 TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_GNPTXSTS": {
+              "description": "OTG_HS nonperiodic transmit FIFO/queue\n          status register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 524800,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "NPTXFSAV": {
+                    "description": "Nonperiodic TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "NPTQXSAV": {
+                    "description": "Nonperiodic transmit request queue space\n              available",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "NPTXQTOP": {
+                    "description": "Top of the nonperiodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "OTG_HS_GCCFG": {
+              "description": "OTG_HS general core configuration\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWRDWN": {
+                    "description": "Power down",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "I2CPADEN": {
+                    "description": "Enable I2C bus connection for the\n              external I2C PHY interface",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "VBUSASEN": {
+                    "description": "Enable the VBUS sensing\n              device",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "VBUSBSEN": {
+                    "description": "Enable the VBUS sensing\n              device",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SOFOUTEN": {
+                    "description": "SOF output enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "NOVBUSSENS": {
+                    "description": "VBUS sensing disable\n              option",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTG_HS_CID": {
+              "description": "OTG_HS core ID register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 4608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRODUCT_ID": {
+                    "description": "Product ID field",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OTG_HS_HPTXFSIZ": {
+              "description": "OTG_HS Host periodic transmit FIFO size\n          register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 33555968,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTXSA": {
+                    "description": "Host periodic TxFIFO start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PTXFD": {
+                    "description": "Host periodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF1": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF2": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF3": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF4": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF5": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF6": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_DIEPTXF7": {
+              "description": "OTG_HS device IN endpoint transmit FIFO size\n          register",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFOx transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRXSTSR_Peripheral": {
+              "description": "OTG_HS Receive status debug read register\n          (peripheral mode mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  },
+                  "FRMNUM": {
+                    "description": "Frame number",
+                    "offset": 21,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OTG_HS_GRXSTSP_Peripheral": {
+              "description": "OTG_HS status read and pop register\n          (peripheral mode)",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  },
+                  "FRMNUM": {
+                    "description": "Frame number",
+                    "offset": 21,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EXTI": {
+        "description": "External interrupt/event\n      controller",
+        "children": {
+          "registers": {
+            "IMR": {
+              "description": "Interrupt mask register\n          (EXTI_IMR)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR0": {
+                    "description": "Interrupt Mask on line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MR1": {
+                    "description": "Interrupt Mask on line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MR2": {
+                    "description": "Interrupt Mask on line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MR3": {
+                    "description": "Interrupt Mask on line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MR4": {
+                    "description": "Interrupt Mask on line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MR5": {
+                    "description": "Interrupt Mask on line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MR6": {
+                    "description": "Interrupt Mask on line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MR7": {
+                    "description": "Interrupt Mask on line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MR8": {
+                    "description": "Interrupt Mask on line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "MR9": {
+                    "description": "Interrupt Mask on line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "MR10": {
+                    "description": "Interrupt Mask on line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "MR11": {
+                    "description": "Interrupt Mask on line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "MR12": {
+                    "description": "Interrupt Mask on line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MR13": {
+                    "description": "Interrupt Mask on line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MR14": {
+                    "description": "Interrupt Mask on line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MR15": {
+                    "description": "Interrupt Mask on line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MR16": {
+                    "description": "Interrupt Mask on line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MR17": {
+                    "description": "Interrupt Mask on line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MR18": {
+                    "description": "Interrupt Mask on line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "MR19": {
+                    "description": "Interrupt Mask on line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "MR20": {
+                    "description": "Interrupt Mask on line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "MR21": {
+                    "description": "Interrupt Mask on line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "MR22": {
+                    "description": "Interrupt Mask on line 22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EMR": {
+              "description": "Event mask register (EXTI_EMR)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR0": {
+                    "description": "Event Mask on line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MR1": {
+                    "description": "Event Mask on line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MR2": {
+                    "description": "Event Mask on line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MR3": {
+                    "description": "Event Mask on line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MR4": {
+                    "description": "Event Mask on line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MR5": {
+                    "description": "Event Mask on line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MR6": {
+                    "description": "Event Mask on line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MR7": {
+                    "description": "Event Mask on line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MR8": {
+                    "description": "Event Mask on line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "MR9": {
+                    "description": "Event Mask on line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "MR10": {
+                    "description": "Event Mask on line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "MR11": {
+                    "description": "Event Mask on line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "MR12": {
+                    "description": "Event Mask on line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MR13": {
+                    "description": "Event Mask on line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "MR14": {
+                    "description": "Event Mask on line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MR15": {
+                    "description": "Event Mask on line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MR16": {
+                    "description": "Event Mask on line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MR17": {
+                    "description": "Event Mask on line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MR18": {
+                    "description": "Event Mask on line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "MR19": {
+                    "description": "Event Mask on line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "MR20": {
+                    "description": "Event Mask on line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "MR21": {
+                    "description": "Event Mask on line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "MR22": {
+                    "description": "Event Mask on line 22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RTSR": {
+              "description": "Rising Trigger selection register\n          (EXTI_RTSR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TR0": {
+                    "description": "Rising trigger event configuration of\n              line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TR1": {
+                    "description": "Rising trigger event configuration of\n              line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TR2": {
+                    "description": "Rising trigger event configuration of\n              line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TR3": {
+                    "description": "Rising trigger event configuration of\n              line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TR4": {
+                    "description": "Rising trigger event configuration of\n              line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TR5": {
+                    "description": "Rising trigger event configuration of\n              line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TR6": {
+                    "description": "Rising trigger event configuration of\n              line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TR7": {
+                    "description": "Rising trigger event configuration of\n              line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TR8": {
+                    "description": "Rising trigger event configuration of\n              line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TR9": {
+                    "description": "Rising trigger event configuration of\n              line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TR10": {
+                    "description": "Rising trigger event configuration of\n              line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TR11": {
+                    "description": "Rising trigger event configuration of\n              line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TR12": {
+                    "description": "Rising trigger event configuration of\n              line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TR13": {
+                    "description": "Rising trigger event configuration of\n              line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TR14": {
+                    "description": "Rising trigger event configuration of\n              line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TR15": {
+                    "description": "Rising trigger event configuration of\n              line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TR16": {
+                    "description": "Rising trigger event configuration of\n              line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TR17": {
+                    "description": "Rising trigger event configuration of\n              line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TR18": {
+                    "description": "Rising trigger event configuration of\n              line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TR19": {
+                    "description": "Rising trigger event configuration of\n              line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TR20": {
+                    "description": "Rising trigger event configuration of\n              line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TR21": {
+                    "description": "Rising trigger event configuration of\n              line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TR22": {
+                    "description": "Rising trigger event configuration of\n              line 22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FTSR": {
+              "description": "Falling Trigger selection register\n          (EXTI_FTSR)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TR0": {
+                    "description": "Falling trigger event configuration of\n              line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TR1": {
+                    "description": "Falling trigger event configuration of\n              line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TR2": {
+                    "description": "Falling trigger event configuration of\n              line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TR3": {
+                    "description": "Falling trigger event configuration of\n              line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TR4": {
+                    "description": "Falling trigger event configuration of\n              line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TR5": {
+                    "description": "Falling trigger event configuration of\n              line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TR6": {
+                    "description": "Falling trigger event configuration of\n              line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TR7": {
+                    "description": "Falling trigger event configuration of\n              line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TR8": {
+                    "description": "Falling trigger event configuration of\n              line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TR9": {
+                    "description": "Falling trigger event configuration of\n              line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TR10": {
+                    "description": "Falling trigger event configuration of\n              line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TR11": {
+                    "description": "Falling trigger event configuration of\n              line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TR12": {
+                    "description": "Falling trigger event configuration of\n              line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TR13": {
+                    "description": "Falling trigger event configuration of\n              line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TR14": {
+                    "description": "Falling trigger event configuration of\n              line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TR15": {
+                    "description": "Falling trigger event configuration of\n              line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TR16": {
+                    "description": "Falling trigger event configuration of\n              line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TR17": {
+                    "description": "Falling trigger event configuration of\n              line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TR18": {
+                    "description": "Falling trigger event configuration of\n              line 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TR19": {
+                    "description": "Falling trigger event configuration of\n              line 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TR20": {
+                    "description": "Falling trigger event configuration of\n              line 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TR21": {
+                    "description": "Falling trigger event configuration of\n              line 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TR22": {
+                    "description": "Falling trigger event configuration of\n              line 22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWIER": {
+              "description": "Software interrupt event register\n          (EXTI_SWIER)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWIER0": {
+                    "description": "Software Interrupt on line\n              0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SWIER1": {
+                    "description": "Software Interrupt on line\n              1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SWIER2": {
+                    "description": "Software Interrupt on line\n              2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SWIER3": {
+                    "description": "Software Interrupt on line\n              3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SWIER4": {
+                    "description": "Software Interrupt on line\n              4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SWIER5": {
+                    "description": "Software Interrupt on line\n              5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SWIER6": {
+                    "description": "Software Interrupt on line\n              6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SWIER7": {
+                    "description": "Software Interrupt on line\n              7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SWIER8": {
+                    "description": "Software Interrupt on line\n              8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SWIER9": {
+                    "description": "Software Interrupt on line\n              9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SWIER10": {
+                    "description": "Software Interrupt on line\n              10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SWIER11": {
+                    "description": "Software Interrupt on line\n              11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SWIER12": {
+                    "description": "Software Interrupt on line\n              12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SWIER13": {
+                    "description": "Software Interrupt on line\n              13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SWIER14": {
+                    "description": "Software Interrupt on line\n              14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SWIER15": {
+                    "description": "Software Interrupt on line\n              15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SWIER16": {
+                    "description": "Software Interrupt on line\n              16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SWIER17": {
+                    "description": "Software Interrupt on line\n              17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SWIER18": {
+                    "description": "Software Interrupt on line\n              18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "SWIER19": {
+                    "description": "Software Interrupt on line\n              19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SWIER20": {
+                    "description": "Software Interrupt on line\n              20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "SWIER21": {
+                    "description": "Software Interrupt on line\n              21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SWIER22": {
+                    "description": "Software Interrupt on line\n              22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PR": {
+              "description": "Pending register (EXTI_PR)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PR0": {
+                    "description": "Pending bit 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PR1": {
+                    "description": "Pending bit 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PR2": {
+                    "description": "Pending bit 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PR3": {
+                    "description": "Pending bit 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PR4": {
+                    "description": "Pending bit 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PR5": {
+                    "description": "Pending bit 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PR6": {
+                    "description": "Pending bit 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PR7": {
+                    "description": "Pending bit 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PR8": {
+                    "description": "Pending bit 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PR9": {
+                    "description": "Pending bit 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PR10": {
+                    "description": "Pending bit 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PR11": {
+                    "description": "Pending bit 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PR12": {
+                    "description": "Pending bit 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PR13": {
+                    "description": "Pending bit 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PR14": {
+                    "description": "Pending bit 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PR15": {
+                    "description": "Pending bit 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "PR16": {
+                    "description": "Pending bit 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PR17": {
+                    "description": "Pending bit 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PR18": {
+                    "description": "Pending bit 18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PR19": {
+                    "description": "Pending bit 19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PR20": {
+                    "description": "Pending bit 20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PR21": {
+                    "description": "Pending bit 21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "PR22": {
+                    "description": "Pending bit 22",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USART6": {
+        "description": "Universal synchronous asynchronous receiver\n      transmitter",
+        "children": {
+          "registers": {
+            "SR": {
+              "description": "Status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 12582912,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTS": {
+                    "description": "CTS flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LBD": {
+                    "description": "LIN break detection flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXE": {
+                    "description": "Transmit data register\n              empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TC": {
+                    "description": "Transmission complete",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNE": {
+                    "description": "Read data register not\n              empty",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLE": {
+                    "description": "IDLE line detected",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ORE": {
+                    "description": "Overrun error",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NF": {
+                    "description": "Noise detected flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FE": {
+                    "description": "Framing error",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PE": {
+                    "description": "Parity error",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "Data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data value",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "BRR": {
+              "description": "Baud rate register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIV_Mantissa": {
+                    "description": "mantissa of USARTDIV",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "DIV_Fraction": {
+                    "description": "fraction of USARTDIV",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "Control register 1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVER8": {
+                    "description": "Oversampling mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "UE": {
+                    "description": "USART enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "M": {
+                    "description": "Word length",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAKE": {
+                    "description": "Wakeup method",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PCE": {
+                    "description": "Parity control enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PS": {
+                    "description": "Parity selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PEIE": {
+                    "description": "PE interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXEIE": {
+                    "description": "TXE interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transmission complete interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RXNE interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLEIE": {
+                    "description": "IDLE interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TE": {
+                    "description": "Transmitter enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RE": {
+                    "description": "Receiver enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RWU": {
+                    "description": "Receiver wakeup",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SBK": {
+                    "description": "Send break",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "Control register 2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LINEN": {
+                    "description": "LIN mode enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "STOP bits",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CLKEN": {
+                    "description": "Clock enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CPOL": {
+                    "description": "Clock polarity",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CPHA": {
+                    "description": "Clock phase",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LBCL": {
+                    "description": "Last bit clock pulse",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LBDIE": {
+                    "description": "LIN break detection interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LBDL": {
+                    "description": "lin break detection length",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADD": {
+                    "description": "Address of the USART node",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR3": {
+              "description": "Control register 3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ONEBIT": {
+                    "description": "One sample bit method\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CTSIE": {
+                    "description": "CTS interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CTSE": {
+                    "description": "CTS enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RTSE": {
+                    "description": "RTS enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DMAT": {
+                    "description": "DMA enable transmitter",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DMAR": {
+                    "description": "DMA enable receiver",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SCEN": {
+                    "description": "Smartcard mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NACK": {
+                    "description": "Smartcard NACK enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HDSEL": {
+                    "description": "Half-duplex selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IRLP": {
+                    "description": "IrDA low-power",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IrDA mode enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GTPR": {
+              "description": "Guard time and prescaler\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GT": {
+                    "description": "Guard time value",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FLASH": {
+        "description": "FLASH",
+        "children": {
+          "registers": {
+            "ACR": {
+              "description": "Flash access control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LATENCY": {
+                    "description": "Latency",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "PRFTEN": {
+                    "description": "Prefetch enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ICEN": {
+                    "description": "Instruction cache enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DCEN": {
+                    "description": "Data cache enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ICRST": {
+                    "description": "Instruction cache reset",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DCRST": {
+                    "description": "Data cache reset",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "KEYR": {
+              "description": "Flash key register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "KEY": {
+                    "description": "FPEC key",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OPTKEYR": {
+              "description": "Flash option key register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "OPTKEY": {
+                    "description": "Option byte key",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EOP": {
+                    "description": "End of operation",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "OPERR": {
+                    "description": "Operation error",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WRPERR": {
+                    "description": "Write protection error",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PGAERR": {
+                    "description": "Programming alignment\n              error",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PGPERR": {
+                    "description": "Programming parallelism\n              error",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PGSERR": {
+                    "description": "Programming sequence error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BSY": {
+                    "description": "Busy",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "Control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 2147483648,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PG": {
+                    "description": "Programming",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SER": {
+                    "description": "Sector Erase",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MER": {
+                    "description": "Mass Erase of sectors 0 to\n              11",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SNB": {
+                    "description": "Sector number",
+                    "offset": 3,
+                    "size": 5
+                  },
+                  "PSIZE": {
+                    "description": "Program size",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MER1": {
+                    "description": "Mass Erase of sectors 12 to\n              23",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "STRT": {
+                    "description": "Start",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EOPIE": {
+                    "description": "End of operation interrupt\n              enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "LOCK": {
+                    "description": "Lock",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OPTCR": {
+              "description": "Flash option control register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 268413677,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OPTLOCK": {
+                    "description": "Option lock",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "OPTSTRT": {
+                    "description": "Option start",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BOR_LEV": {
+                    "description": "BOR reset Level",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "WDG_SW": {
+                    "description": "WDG_SW User option bytes",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "nRST_STOP": {
+                    "description": "nRST_STOP User option\n              bytes",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "nRST_STDBY": {
+                    "description": "nRST_STDBY User option\n              bytes",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RDP": {
+                    "description": "Read protect",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "nWRP": {
+                    "description": "Not write protect",
+                    "offset": 16,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "OPTCR1": {
+              "description": "Flash option control register\n          1",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 268369920,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "nWRP": {
+                    "description": "Not write protect",
+                    "offset": 16,
+                    "size": 12
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "NVIC": {
+        "description": "Nested Vectored Interrupt\n      Controller",
+        "children": {
+          "registers": {
+            "ISER0": {
+              "description": "Interrupt Set-Enable Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "SETENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISER1": {
+              "description": "Interrupt Set-Enable Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "SETENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISER2": {
+              "description": "Interrupt Set-Enable Register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "SETENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICER0": {
+              "description": "Interrupt Clear-Enable\n          Register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "CLRENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICER1": {
+              "description": "Interrupt Clear-Enable\n          Register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "CLRENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICER2": {
+              "description": "Interrupt Clear-Enable\n          Register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "CLRENA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISPR0": {
+              "description": "Interrupt Set-Pending Register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "SETPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISPR1": {
+              "description": "Interrupt Set-Pending Register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "SETPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ISPR2": {
+              "description": "Interrupt Set-Pending Register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "SETPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICPR0": {
+              "description": "Interrupt Clear-Pending\n          Register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "CLRPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICPR1": {
+              "description": "Interrupt Clear-Pending\n          Register",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "CLRPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICPR2": {
+              "description": "Interrupt Clear-Pending\n          Register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "CLRPEND",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IABR0": {
+              "description": "Interrupt Active Bit Register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACTIVE": {
+                    "description": "ACTIVE",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IABR1": {
+              "description": "Interrupt Active Bit Register",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACTIVE": {
+                    "description": "ACTIVE",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IABR2": {
+              "description": "Interrupt Active Bit Register",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ACTIVE": {
+                    "description": "ACTIVE",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IPR0": {
+              "description": "Interrupt Priority Register",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR1": {
+              "description": "Interrupt Priority Register",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR2": {
+              "description": "Interrupt Priority Register",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR3": {
+              "description": "Interrupt Priority Register",
+              "offset": 780,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR4": {
+              "description": "Interrupt Priority Register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR5": {
+              "description": "Interrupt Priority Register",
+              "offset": 788,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR6": {
+              "description": "Interrupt Priority Register",
+              "offset": 792,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR7": {
+              "description": "Interrupt Priority Register",
+              "offset": 796,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR8": {
+              "description": "Interrupt Priority Register",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR9": {
+              "description": "Interrupt Priority Register",
+              "offset": 804,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR10": {
+              "description": "Interrupt Priority Register",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR11": {
+              "description": "Interrupt Priority Register",
+              "offset": 812,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR12": {
+              "description": "Interrupt Priority Register",
+              "offset": 816,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR13": {
+              "description": "Interrupt Priority Register",
+              "offset": 820,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR14": {
+              "description": "Interrupt Priority Register",
+              "offset": 824,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR15": {
+              "description": "Interrupt Priority Register",
+              "offset": 828,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR16": {
+              "description": "Interrupt Priority Register",
+              "offset": 832,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR17": {
+              "description": "Interrupt Priority Register",
+              "offset": 836,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR18": {
+              "description": "Interrupt Priority Register",
+              "offset": 840,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR19": {
+              "description": "Interrupt Priority Register",
+              "offset": 844,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IPR20": {
+              "description": "Interrupt Priority Register",
+              "offset": 848,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IPR_N0": {
+                    "description": "IPR_N0",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "IPR_N1": {
+                    "description": "IPR_N1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "IPR_N2": {
+                    "description": "IPR_N2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IPR_N3": {
+                    "description": "IPR_N3",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "Ethernet_MAC": {
+        "description": "Ethernet: media access control\n      (MAC)",
+        "children": {
+          "registers": {
+            "MACCR": {
+              "description": "Ethernet MAC configuration\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RE": {
+                    "description": "RE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TE": {
+                    "description": "TE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DC": {
+                    "description": "DC",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BL": {
+                    "description": "BL",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "APCS": {
+                    "description": "APCS",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RD": {
+                    "description": "RD",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IPCO": {
+                    "description": "IPCO",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DM": {
+                    "description": "DM",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LM": {
+                    "description": "LM",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ROD": {
+                    "description": "ROD",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FES": {
+                    "description": "FES",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CSD": {
+                    "description": "CSD",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "IFG": {
+                    "description": "IFG",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "JD": {
+                    "description": "JD",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "WD": {
+                    "description": "WD",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CSTF": {
+                    "description": "CSTF",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACFFR": {
+              "description": "Ethernet MAC frame filter\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PM": {
+                    "description": "PM",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HU": {
+                    "description": "HU",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HM": {
+                    "description": "HM",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DAIF": {
+                    "description": "DAIF",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RAM": {
+                    "description": "RAM",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BFD": {
+                    "description": "BFD",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PCF": {
+                    "description": "PCF",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SAIF": {
+                    "description": "SAIF",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SAF": {
+                    "description": "SAF",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HPF": {
+                    "description": "HPF",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RA": {
+                    "description": "RA",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACHTHR": {
+              "description": "Ethernet MAC hash table high\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HTH": {
+                    "description": "HTH",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACHTLR": {
+              "description": "Ethernet MAC hash table low\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HTL": {
+                    "description": "HTL",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACMIIAR": {
+              "description": "Ethernet MAC MII address\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MB": {
+                    "description": "MB",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MW": {
+                    "description": "MW",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CR": {
+                    "description": "CR",
+                    "offset": 2,
+                    "size": 3
+                  },
+                  "MR": {
+                    "description": "MR",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "PA": {
+                    "description": "PA",
+                    "offset": 11,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "MACMIIDR": {
+              "description": "Ethernet MAC MII data register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TD": {
+                    "description": "TD",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "MACFCR": {
+              "description": "Ethernet MAC flow control\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FCB": {
+                    "description": "FCB",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TFCE": {
+                    "description": "TFCE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RFCE": {
+                    "description": "RFCE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UPFD": {
+                    "description": "UPFD",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PLT": {
+                    "description": "PLT",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "ZQPD": {
+                    "description": "ZQPD",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PT": {
+                    "description": "PT",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "MACVLANTR": {
+              "description": "Ethernet MAC VLAN tag register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VLANTI": {
+                    "description": "VLANTI",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "VLANTC": {
+                    "description": "VLANTC",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACPMTCSR": {
+              "description": "Ethernet MAC PMT control and status\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PD": {
+                    "description": "PD",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MPE": {
+                    "description": "MPE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WFE": {
+                    "description": "WFE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MPR": {
+                    "description": "MPR",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WFR": {
+                    "description": "WFR",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GU": {
+                    "description": "GU",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WFFRPR": {
+                    "description": "WFFRPR",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACDBGR": {
+              "description": "Ethernet MAC debug register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CR": {
+                    "description": "CR",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CSR": {
+                    "description": "CSR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ROR": {
+                    "description": "ROR",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MCF": {
+                    "description": "MCF",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MCP": {
+                    "description": "MCP",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MCFHP": {
+                    "description": "MCFHP",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACSR": {
+              "description": "Ethernet MAC interrupt status\n          register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PMTS": {
+                    "description": "PMTS",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMCS": {
+                    "description": "MMCS",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMCRS": {
+                    "description": "MMCRS",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMCTS": {
+                    "description": "MMCTS",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TSTS": {
+                    "description": "TSTS",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACIMR": {
+              "description": "Ethernet MAC interrupt mask\n          register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PMTIM": {
+                    "description": "PMTIM",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TSTIM": {
+                    "description": "TSTIM",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA0HR": {
+              "description": "Ethernet MAC address 0 high\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 1114111,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA0H": {
+                    "description": "MAC address0 high",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MO": {
+                    "description": "Always 1",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MACA0LR": {
+              "description": "Ethernet MAC address 0 low\n          register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA0L": {
+                    "description": "0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACA1HR": {
+              "description": "Ethernet MAC address 1 high\n          register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA1H": {
+                    "description": "MACA1H",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MBC": {
+                    "description": "MBC",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "SA": {
+                    "description": "SA",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "AE": {
+                    "description": "AE",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA1LR": {
+              "description": "Ethernet MAC address1 low\n          register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA1LR": {
+                    "description": "MACA1LR",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MACA2HR": {
+              "description": "Ethernet MAC address 2 high\n          register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC2AH": {
+                    "description": "MAC2AH",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MBC": {
+                    "description": "MBC",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "SA": {
+                    "description": "SA",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "AE": {
+                    "description": "AE",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA2LR": {
+              "description": "Ethernet MAC address 2 low\n          register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA2L": {
+                    "description": "MACA2L",
+                    "offset": 0,
+                    "size": 31
+                  }
+                }
+              }
+            },
+            "MACA3HR": {
+              "description": "Ethernet MAC address 3 high\n          register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MACA3H": {
+                    "description": "MACA3H",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MBC": {
+                    "description": "MBC",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "SA": {
+                    "description": "SA",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "AE": {
+                    "description": "AE",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MACA3LR": {
+              "description": "Ethernet MAC address 3 low\n          register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MBCA3L": {
+                    "description": "MBCA3L",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CAN1": {
+        "description": "Controller area network",
+        "children": {
+          "registers": {
+            "MCR": {
+              "description": "master control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 65538,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBF": {
+                    "description": "DBF",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "RESET",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TTCM": {
+                    "description": "TTCM",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ABOM": {
+                    "description": "ABOM",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AWUM": {
+                    "description": "AWUM",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NART": {
+                    "description": "NART",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RFLM": {
+                    "description": "RFLM",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXFP": {
+                    "description": "TXFP",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLEEP": {
+                    "description": "SLEEP",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INRQ": {
+                    "description": "INRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MSR": {
+              "description": "master status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 3074,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX": {
+                    "description": "RX",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SAMP": {
+                    "description": "SAMP",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXM": {
+                    "description": "RXM",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXM": {
+                    "description": "TXM",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAKI": {
+                    "description": "SLAKI",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "WKUI": {
+                    "description": "WKUI",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERRI": {
+                    "description": "ERRI",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLAK": {
+                    "description": "SLAK",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INAK": {
+                    "description": "INAK",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TSR": {
+              "description": "transmit status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 469762048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOW2": {
+                    "description": "Lowest priority flag for mailbox\n              2",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOW1": {
+                    "description": "Lowest priority flag for mailbox\n              1",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LOW0": {
+                    "description": "Lowest priority flag for mailbox\n              0",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME2": {
+                    "description": "Lowest priority flag for mailbox\n              2",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME1": {
+                    "description": "Lowest priority flag for mailbox\n              1",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME0": {
+                    "description": "Lowest priority flag for mailbox\n              0",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CODE": {
+                    "description": "CODE",
+                    "offset": 24,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "ABRQ2": {
+                    "description": "ABRQ2",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TERR2": {
+                    "description": "TERR2",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ALST2": {
+                    "description": "ALST2",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TXOK2": {
+                    "description": "TXOK2",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RQCP2": {
+                    "description": "RQCP2",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ABRQ1": {
+                    "description": "ABRQ1",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TERR1": {
+                    "description": "TERR1",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ALST1": {
+                    "description": "ALST1",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TXOK1": {
+                    "description": "TXOK1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RQCP1": {
+                    "description": "RQCP1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ABRQ0": {
+                    "description": "ABRQ0",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TERR0": {
+                    "description": "TERR0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ALST0": {
+                    "description": "ALST0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXOK0": {
+                    "description": "TXOK0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RQCP0": {
+                    "description": "RQCP0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RF0R": {
+              "description": "receive FIFO 0 register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFOM0": {
+                    "description": "RFOM0",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FOVR0": {
+                    "description": "FOVR0",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FULL0": {
+                    "description": "FULL0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FMP0": {
+                    "description": "FMP0",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RF1R": {
+              "description": "receive FIFO 1 register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFOM1": {
+                    "description": "RFOM1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FOVR1": {
+                    "description": "FOVR1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FULL1": {
+                    "description": "FULL1",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FMP1": {
+                    "description": "FMP1",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "interrupt enable register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLKIE": {
+                    "description": "SLKIE",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WKUIE": {
+                    "description": "WKUIE",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "ERRIE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LECIE": {
+                    "description": "LECIE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BOFIE": {
+                    "description": "BOFIE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPVIE": {
+                    "description": "EPVIE",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EWGIE": {
+                    "description": "EWGIE",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FOVIE1": {
+                    "description": "FOVIE1",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FFIE1": {
+                    "description": "FFIE1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FMPIE1": {
+                    "description": "FMPIE1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FOVIE0": {
+                    "description": "FOVIE0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FFIE0": {
+                    "description": "FFIE0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FMPIE0": {
+                    "description": "FMPIE0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TMEIE": {
+                    "description": "TMEIE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ESR": {
+              "description": "interrupt enable register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REC": {
+                    "description": "REC",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "TEC": {
+                    "description": "TEC",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "LEC": {
+                    "description": "LEC",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "BOFF": {
+                    "description": "BOFF",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPVF": {
+                    "description": "EPVF",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EWGF": {
+                    "description": "EWGF",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "BTR": {
+              "description": "bit timing register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SILM": {
+                    "description": "SILM",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LBKM": {
+                    "description": "LBKM",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SJW": {
+                    "description": "SJW",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "TS2": {
+                    "description": "TS2",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "TS1": {
+                    "description": "TS1",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "BRP": {
+                    "description": "BRP",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "TI0R": {
+              "description": "TX mailbox identifier register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXRQ": {
+                    "description": "TXRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TDT0R": {
+              "description": "mailbox data length control and time stamp\n          register",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TGT": {
+                    "description": "TGT",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TDL0R": {
+              "description": "mailbox data low register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TDH0R": {
+              "description": "mailbox data high register",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TI1R": {
+              "description": "mailbox identifier register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXRQ": {
+                    "description": "TXRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TDT1R": {
+              "description": "mailbox data length control and time stamp\n          register",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TGT": {
+                    "description": "TGT",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TDL1R": {
+              "description": "mailbox data low register",
+              "offset": 408,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TDH1R": {
+              "description": "mailbox data high register",
+              "offset": 412,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TI2R": {
+              "description": "mailbox identifier register",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXRQ": {
+                    "description": "TXRQ",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TDT2R": {
+              "description": "mailbox data length control and time stamp\n          register",
+              "offset": 420,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TGT": {
+                    "description": "TGT",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TDL2R": {
+              "description": "mailbox data low register",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TDH2R": {
+              "description": "mailbox data high register",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RI0R": {
+              "description": "receive FIFO mailbox identifier\n          register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RDT0R": {
+              "description": "mailbox data high register",
+              "offset": 436,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FMI": {
+                    "description": "FMI",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RDL0R": {
+              "description": "mailbox data high register",
+              "offset": 440,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RDH0R": {
+              "description": "receive FIFO mailbox data high\n          register",
+              "offset": 444,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RI1R": {
+              "description": "mailbox data high register",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STID": {
+                    "description": "STID",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EXID": {
+                    "description": "EXID",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "IDE": {
+                    "description": "IDE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTR": {
+                    "description": "RTR",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RDT1R": {
+              "description": "mailbox data high register",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "TIME",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FMI": {
+                    "description": "FMI",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DLC": {
+                    "description": "DLC",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RDL1R": {
+              "description": "mailbox data high register",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA3": {
+                    "description": "DATA3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "DATA2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA1": {
+                    "description": "DATA1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA0": {
+                    "description": "DATA0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RDH1R": {
+              "description": "mailbox data high register",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA7": {
+                    "description": "DATA7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "DATA6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA5": {
+                    "description": "DATA5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "DATA4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "FMR": {
+              "description": "filter master register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 706481665,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CAN2SB": {
+                    "description": "CAN2SB",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "FINIT": {
+                    "description": "FINIT",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FM1R": {
+              "description": "filter mode register",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FBM0": {
+                    "description": "Filter mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FBM1": {
+                    "description": "Filter mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FBM2": {
+                    "description": "Filter mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FBM3": {
+                    "description": "Filter mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FBM4": {
+                    "description": "Filter mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FBM5": {
+                    "description": "Filter mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FBM6": {
+                    "description": "Filter mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FBM7": {
+                    "description": "Filter mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FBM8": {
+                    "description": "Filter mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FBM9": {
+                    "description": "Filter mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FBM10": {
+                    "description": "Filter mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FBM11": {
+                    "description": "Filter mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FBM12": {
+                    "description": "Filter mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FBM13": {
+                    "description": "Filter mode",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FBM14": {
+                    "description": "Filter mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FBM15": {
+                    "description": "Filter mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FBM16": {
+                    "description": "Filter mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FBM17": {
+                    "description": "Filter mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FBM18": {
+                    "description": "Filter mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FBM19": {
+                    "description": "Filter mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FBM20": {
+                    "description": "Filter mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FBM21": {
+                    "description": "Filter mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FBM22": {
+                    "description": "Filter mode",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FBM23": {
+                    "description": "Filter mode",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FBM24": {
+                    "description": "Filter mode",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FBM25": {
+                    "description": "Filter mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FBM26": {
+                    "description": "Filter mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FBM27": {
+                    "description": "Filter mode",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS1R": {
+              "description": "filter scale register",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSC0": {
+                    "description": "Filter scale configuration",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FSC1": {
+                    "description": "Filter scale configuration",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FSC2": {
+                    "description": "Filter scale configuration",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FSC3": {
+                    "description": "Filter scale configuration",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FSC4": {
+                    "description": "Filter scale configuration",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FSC5": {
+                    "description": "Filter scale configuration",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FSC6": {
+                    "description": "Filter scale configuration",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FSC7": {
+                    "description": "Filter scale configuration",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FSC8": {
+                    "description": "Filter scale configuration",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FSC9": {
+                    "description": "Filter scale configuration",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FSC10": {
+                    "description": "Filter scale configuration",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FSC11": {
+                    "description": "Filter scale configuration",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FSC12": {
+                    "description": "Filter scale configuration",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FSC13": {
+                    "description": "Filter scale configuration",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FSC14": {
+                    "description": "Filter scale configuration",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FSC15": {
+                    "description": "Filter scale configuration",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FSC16": {
+                    "description": "Filter scale configuration",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FSC17": {
+                    "description": "Filter scale configuration",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FSC18": {
+                    "description": "Filter scale configuration",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FSC19": {
+                    "description": "Filter scale configuration",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FSC20": {
+                    "description": "Filter scale configuration",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FSC21": {
+                    "description": "Filter scale configuration",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FSC22": {
+                    "description": "Filter scale configuration",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FSC23": {
+                    "description": "Filter scale configuration",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FSC24": {
+                    "description": "Filter scale configuration",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FSC25": {
+                    "description": "Filter scale configuration",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FSC26": {
+                    "description": "Filter scale configuration",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FSC27": {
+                    "description": "Filter scale configuration",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FFA1R": {
+              "description": "filter FIFO assignment\n          register",
+              "offset": 532,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FFA0": {
+                    "description": "Filter FIFO assignment for filter\n              0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FFA1": {
+                    "description": "Filter FIFO assignment for filter\n              1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FFA2": {
+                    "description": "Filter FIFO assignment for filter\n              2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FFA3": {
+                    "description": "Filter FIFO assignment for filter\n              3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FFA4": {
+                    "description": "Filter FIFO assignment for filter\n              4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FFA5": {
+                    "description": "Filter FIFO assignment for filter\n              5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FFA6": {
+                    "description": "Filter FIFO assignment for filter\n              6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FFA7": {
+                    "description": "Filter FIFO assignment for filter\n              7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FFA8": {
+                    "description": "Filter FIFO assignment for filter\n              8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FFA9": {
+                    "description": "Filter FIFO assignment for filter\n              9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FFA10": {
+                    "description": "Filter FIFO assignment for filter\n              10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FFA11": {
+                    "description": "Filter FIFO assignment for filter\n              11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FFA12": {
+                    "description": "Filter FIFO assignment for filter\n              12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FFA13": {
+                    "description": "Filter FIFO assignment for filter\n              13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FFA14": {
+                    "description": "Filter FIFO assignment for filter\n              14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FFA15": {
+                    "description": "Filter FIFO assignment for filter\n              15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FFA16": {
+                    "description": "Filter FIFO assignment for filter\n              16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FFA17": {
+                    "description": "Filter FIFO assignment for filter\n              17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FFA18": {
+                    "description": "Filter FIFO assignment for filter\n              18",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FFA19": {
+                    "description": "Filter FIFO assignment for filter\n              19",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FFA20": {
+                    "description": "Filter FIFO assignment for filter\n              20",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FFA21": {
+                    "description": "Filter FIFO assignment for filter\n              21",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FFA22": {
+                    "description": "Filter FIFO assignment for filter\n              22",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FFA23": {
+                    "description": "Filter FIFO assignment for filter\n              23",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FFA24": {
+                    "description": "Filter FIFO assignment for filter\n              24",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FFA25": {
+                    "description": "Filter FIFO assignment for filter\n              25",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FFA26": {
+                    "description": "Filter FIFO assignment for filter\n              26",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FFA27": {
+                    "description": "Filter FIFO assignment for filter\n              27",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FA1R": {
+              "description": "filter activation register",
+              "offset": 540,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FACT0": {
+                    "description": "Filter active",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FACT1": {
+                    "description": "Filter active",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FACT2": {
+                    "description": "Filter active",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FACT3": {
+                    "description": "Filter active",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FACT4": {
+                    "description": "Filter active",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FACT5": {
+                    "description": "Filter active",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FACT6": {
+                    "description": "Filter active",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FACT7": {
+                    "description": "Filter active",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FACT8": {
+                    "description": "Filter active",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FACT9": {
+                    "description": "Filter active",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FACT10": {
+                    "description": "Filter active",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FACT11": {
+                    "description": "Filter active",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FACT12": {
+                    "description": "Filter active",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FACT13": {
+                    "description": "Filter active",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FACT14": {
+                    "description": "Filter active",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FACT15": {
+                    "description": "Filter active",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FACT16": {
+                    "description": "Filter active",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FACT17": {
+                    "description": "Filter active",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FACT18": {
+                    "description": "Filter active",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FACT19": {
+                    "description": "Filter active",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FACT20": {
+                    "description": "Filter active",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FACT21": {
+                    "description": "Filter active",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FACT22": {
+                    "description": "Filter active",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FACT23": {
+                    "description": "Filter active",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FACT24": {
+                    "description": "Filter active",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FACT25": {
+                    "description": "Filter active",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FACT26": {
+                    "description": "Filter active",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FACT27": {
+                    "description": "Filter active",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F0R1": {
+              "description": "Filter bank 0 register 1",
+              "offset": 576,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F0R2": {
+              "description": "Filter bank 0 register 2",
+              "offset": 580,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F1R1": {
+              "description": "Filter bank 1 register 1",
+              "offset": 584,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F1R2": {
+              "description": "Filter bank 1 register 2",
+              "offset": 588,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F2R1": {
+              "description": "Filter bank 2 register 1",
+              "offset": 592,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F2R2": {
+              "description": "Filter bank 2 register 2",
+              "offset": 596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F3R1": {
+              "description": "Filter bank 3 register 1",
+              "offset": 600,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F3R2": {
+              "description": "Filter bank 3 register 2",
+              "offset": 604,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F4R1": {
+              "description": "Filter bank 4 register 1",
+              "offset": 608,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F4R2": {
+              "description": "Filter bank 4 register 2",
+              "offset": 612,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F5R1": {
+              "description": "Filter bank 5 register 1",
+              "offset": 616,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F5R2": {
+              "description": "Filter bank 5 register 2",
+              "offset": 620,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F6R1": {
+              "description": "Filter bank 6 register 1",
+              "offset": 624,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F6R2": {
+              "description": "Filter bank 6 register 2",
+              "offset": 628,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F7R1": {
+              "description": "Filter bank 7 register 1",
+              "offset": 632,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F7R2": {
+              "description": "Filter bank 7 register 2",
+              "offset": 636,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F8R1": {
+              "description": "Filter bank 8 register 1",
+              "offset": 640,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F8R2": {
+              "description": "Filter bank 8 register 2",
+              "offset": 644,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F9R1": {
+              "description": "Filter bank 9 register 1",
+              "offset": 648,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F9R2": {
+              "description": "Filter bank 9 register 2",
+              "offset": 652,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F10R1": {
+              "description": "Filter bank 10 register 1",
+              "offset": 656,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F10R2": {
+              "description": "Filter bank 10 register 2",
+              "offset": 660,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F11R1": {
+              "description": "Filter bank 11 register 1",
+              "offset": 664,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F11R2": {
+              "description": "Filter bank 11 register 2",
+              "offset": 668,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F12R1": {
+              "description": "Filter bank 4 register 1",
+              "offset": 672,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F12R2": {
+              "description": "Filter bank 12 register 2",
+              "offset": 676,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F13R1": {
+              "description": "Filter bank 13 register 1",
+              "offset": 680,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F13R2": {
+              "description": "Filter bank 13 register 2",
+              "offset": 684,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F14R1": {
+              "description": "Filter bank 14 register 1",
+              "offset": 688,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F14R2": {
+              "description": "Filter bank 14 register 2",
+              "offset": 692,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F15R1": {
+              "description": "Filter bank 15 register 1",
+              "offset": 696,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F15R2": {
+              "description": "Filter bank 15 register 2",
+              "offset": 700,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F16R1": {
+              "description": "Filter bank 16 register 1",
+              "offset": 704,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F16R2": {
+              "description": "Filter bank 16 register 2",
+              "offset": 708,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F17R1": {
+              "description": "Filter bank 17 register 1",
+              "offset": 712,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F17R2": {
+              "description": "Filter bank 17 register 2",
+              "offset": 716,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F18R1": {
+              "description": "Filter bank 18 register 1",
+              "offset": 720,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F18R2": {
+              "description": "Filter bank 18 register 2",
+              "offset": 724,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F19R1": {
+              "description": "Filter bank 19 register 1",
+              "offset": 728,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F19R2": {
+              "description": "Filter bank 19 register 2",
+              "offset": 732,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F20R1": {
+              "description": "Filter bank 20 register 1",
+              "offset": 736,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F20R2": {
+              "description": "Filter bank 20 register 2",
+              "offset": 740,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F21R1": {
+              "description": "Filter bank 21 register 1",
+              "offset": 744,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F21R2": {
+              "description": "Filter bank 21 register 2",
+              "offset": 748,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F22R1": {
+              "description": "Filter bank 22 register 1",
+              "offset": 752,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F22R2": {
+              "description": "Filter bank 22 register 2",
+              "offset": 756,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F23R1": {
+              "description": "Filter bank 23 register 1",
+              "offset": 760,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F23R2": {
+              "description": "Filter bank 23 register 2",
+              "offset": 764,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F24R1": {
+              "description": "Filter bank 24 register 1",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F24R2": {
+              "description": "Filter bank 24 register 2",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F25R1": {
+              "description": "Filter bank 25 register 1",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F25R2": {
+              "description": "Filter bank 25 register 2",
+              "offset": 780,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F26R1": {
+              "description": "Filter bank 26 register 1",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F26R2": {
+              "description": "Filter bank 26 register 2",
+              "offset": 788,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F27R1": {
+              "description": "Filter bank 27 register 1",
+              "offset": 792,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F27R2": {
+              "description": "Filter bank 27 register 2",
+              "offset": 796,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FB0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FB1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FB2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FB3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FB4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FB5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FB6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FB7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FB8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FB9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FB10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FB11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FB12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FB13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FB14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FB15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FB16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FB17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FB18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FB19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FB20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FB21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FB22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FB23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FB24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FB25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FB26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FB27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FB28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FB29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FB30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FB31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_PWRCLK": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_PCGCCTL": {
+              "description": "OTG_FS power and clock gating control\n          register (OTG_FS_PCGCCTL)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STPPCLK": {
+                    "description": "Stop PHY clock",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "GATEHCLK": {
+                    "description": "Gate HCLK",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PHYSUSP": {
+                    "description": "PHY Suspended",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DAC": {
+        "description": "Digital-to-analog converter",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAUDRIE2": {
+                    "description": "DAC channel2 DMA underrun interrupt\n              enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DMAEN2": {
+                    "description": "DAC channel2 DMA enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "MAMP2": {
+                    "description": "DAC channel2 mask/amplitude\n              selector",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "WAVE2": {
+                    "description": "DAC channel2 noise/triangle wave\n              generation enable",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "TSEL2": {
+                    "description": "DAC channel2 trigger\n              selection",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "TEN2": {
+                    "description": "DAC channel2 trigger\n              enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "BOFF2": {
+                    "description": "DAC channel2 output buffer\n              disable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EN2": {
+                    "description": "DAC channel2 enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DMAUDRIE1": {
+                    "description": "DAC channel1 DMA Underrun Interrupt\n              enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "DMAEN1": {
+                    "description": "DAC channel1 DMA enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MAMP1": {
+                    "description": "DAC channel1 mask/amplitude\n              selector",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "WAVE1": {
+                    "description": "DAC channel1 noise/triangle wave\n              generation enable",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "TSEL1": {
+                    "description": "DAC channel1 trigger\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "TEN1": {
+                    "description": "DAC channel1 trigger\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BOFF1": {
+                    "description": "DAC channel1 output buffer\n              disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN1": {
+                    "description": "DAC channel1 enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWTRIGR": {
+              "description": "software trigger register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "SWTRIG2": {
+                    "description": "DAC channel2 software\n              trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SWTRIG1": {
+                    "description": "DAC channel1 software\n              trigger",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DHR12R1": {
+              "description": "channel1 12-bit right-aligned data holding\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12L1": {
+              "description": "channel1 12-bit left aligned data holding\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8R1": {
+              "description": "channel1 8-bit right aligned data holding\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC1DHR": {
+                    "description": "DAC channel1 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DHR12R2": {
+              "description": "channel2 12-bit right aligned data holding\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12L2": {
+              "description": "channel2 12-bit left aligned data holding\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8R2": {
+              "description": "channel2 8-bit right-aligned data holding\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DHR12RD": {
+              "description": "Dual DAC 12-bit right-aligned data holding\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit right-aligned\n              data",
+                    "offset": 16,
+                    "size": 12
+                  },
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR12LD": {
+              "description": "DUAL DAC 12-bit left aligned data holding\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 12-bit left-aligned\n              data",
+                    "offset": 20,
+                    "size": 12
+                  },
+                  "DACC1DHR": {
+                    "description": "DAC channel1 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DHR8RD": {
+              "description": "DUAL DAC 8-bit right aligned data holding\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DACC2DHR": {
+                    "description": "DAC channel2 8-bit right-aligned\n              data",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DACC1DHR": {
+                    "description": "DAC channel1 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DOR1": {
+              "description": "channel1 data output register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DACC1DOR": {
+                    "description": "DAC channel1 data output",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DOR2": {
+              "description": "channel2 data output register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DACC2DOR": {
+                    "description": "DAC channel2 data output",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAUDR2": {
+                    "description": "DAC channel2 DMA underrun\n              flag",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DMAUDR1": {
+                    "description": "DAC channel1 DMA underrun\n              flag",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PWR": {
+        "description": "Power control",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "power control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 49152,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LPDS": {
+                    "description": "Low-power deep sleep",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PDDS": {
+                    "description": "Power down deepsleep",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CWUF": {
+                    "description": "Clear wakeup flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CSBF": {
+                    "description": "Clear standby flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PVDE": {
+                    "description": "Power voltage detector\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PLS": {
+                    "description": "PVD level selection",
+                    "offset": 5,
+                    "size": 3
+                  },
+                  "DBP": {
+                    "description": "Disable backup domain write\n              protection",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FPDS": {
+                    "description": "Flash power down in Stop\n              mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LPLVDS": {
+                    "description": "Low-Power Regulator Low Voltage in\n              deepsleep",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "MRLVDS": {
+                    "description": "Main regulator low voltage in deepsleep\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "VOS": {
+                    "description": "Regulator voltage scaling output\n              selection",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "ODEN": {
+                    "description": "Over-drive enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ODSWEN": {
+                    "description": "Over-drive switching\n              enabled",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "UDEN": {
+                    "description": "Under-drive enable in stop\n              mode",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CSR": {
+              "description": "power control/status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WUF": {
+                    "description": "Wakeup flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SBF": {
+                    "description": "Standby flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PVDO": {
+                    "description": "PVD output",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BRR": {
+                    "description": "Backup regulator ready",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EWUP": {
+                    "description": "Enable WKUP pin",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BRE": {
+                    "description": "Backup regulator enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "VOSRDY": {
+                    "description": "Regulator voltage scaling output\n              selection ready bit",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ODRDY": {
+                    "description": "Over-drive mode ready",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ODSWRDY": {
+                    "description": "Over-drive mode switching\n              ready",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "UDRDY": {
+                    "description": "Under-drive ready flag",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "IWDG": {
+        "description": "Independent watchdog",
+        "children": {
+          "registers": {
+            "KR": {
+              "description": "Key register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "KEY": {
+                    "description": "Key value (write only, read\n              0000h)",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PR": {
+              "description": "Prescaler register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PR": {
+                    "description": "Prescaler divider",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "RLR": {
+              "description": "Reload register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RL": {
+                    "description": "Watchdog counter reload\n              value",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RVU": {
+                    "description": "Watchdog counter reload value\n              update",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PVU": {
+                    "description": "Watchdog prescaler value\n              update",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "WWDG": {
+        "description": "Window watchdog",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "Control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 127,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDGA": {
+                    "description": "Activation bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "T": {
+                    "description": "7-bit counter (MSB to LSB)",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "CFR": {
+              "description": "Configuration register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 127,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EWI": {
+                    "description": "Early wakeup interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WDGTB1": {
+                    "description": "Timer base",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WDGTB0": {
+                    "description": "Timer base",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "W": {
+                    "description": "7-bit window value",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EWIF": {
+                    "description": "Early wakeup interrupt\n              flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RTC": {
+        "description": "Real-time clock",
+        "children": {
+          "registers": {
+            "TR": {
+              "description": "time register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PM": {
+                    "description": "AM/PM notation",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "HT": {
+                    "description": "Hour tens in BCD format",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "HU": {
+                    "description": "Hour units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "MNT": {
+                    "description": "Minute tens in BCD format",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "MNU": {
+                    "description": "Minute units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "ST": {
+                    "description": "Second tens in BCD format",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SU": {
+                    "description": "Second units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "date register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 8449,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "YT": {
+                    "description": "Year tens in BCD format",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "YU": {
+                    "description": "Year units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "WDU": {
+                    "description": "Week day units",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "MT": {
+                    "description": "Month tens in BCD format",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MU": {
+                    "description": "Month units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COE": {
+                    "description": "Calibration output enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "OSEL": {
+                    "description": "Output selection",
+                    "offset": 21,
+                    "size": 2
+                  },
+                  "POL": {
+                    "description": "Output polarity",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "BKP": {
+                    "description": "Backup",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "SUB1H": {
+                    "description": "Subtract 1 hour (winter time\n              change)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ADD1H": {
+                    "description": "Add 1 hour (summer time\n              change)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TSIE": {
+                    "description": "Time-stamp interrupt\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "WUTIE": {
+                    "description": "Wakeup timer interrupt\n              enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ALRBIE": {
+                    "description": "Alarm B interrupt enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ALRAIE": {
+                    "description": "Alarm A interrupt enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TSE": {
+                    "description": "Time stamp enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WUTE": {
+                    "description": "Wakeup timer enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ALRBE": {
+                    "description": "Alarm B enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ALRAE": {
+                    "description": "Alarm A enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DCE": {
+                    "description": "Coarse digital calibration\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FMT": {
+                    "description": "Hour format",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "REFCKON": {
+                    "description": "Reference clock detection enable (50 or\n              60 Hz)",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TSEDGE": {
+                    "description": "Time-stamp event active\n              edge",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "WCKSEL": {
+                    "description": "Wakeup clock selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "ISR": {
+              "description": "initialization and status\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ALRAWF": {
+                    "description": "Alarm A write flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ALRBWF": {
+                    "description": "Alarm B write flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WUTWF": {
+                    "description": "Wakeup timer write flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SHPF": {
+                    "description": "Shift operation pending",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "INITS": {
+                    "description": "Initialization status flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RSF": {
+                    "description": "Registers synchronization\n              flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INITF": {
+                    "description": "Initialization flag",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INIT": {
+                    "description": "Initialization mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ALRAF": {
+                    "description": "Alarm A flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ALRBF": {
+                    "description": "Alarm B flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WUTF": {
+                    "description": "Wakeup timer flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TSF": {
+                    "description": "Time-stamp flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TSOVF": {
+                    "description": "Time-stamp overflow flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TAMP1F": {
+                    "description": "Tamper detection flag",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TAMP2F": {
+                    "description": "TAMPER2 detection flag",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RECALPF": {
+                    "description": "Recalibration pending Flag",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PRER": {
+              "description": "prescaler register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 8323327,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PREDIV_A": {
+                    "description": "Asynchronous prescaler\n              factor",
+                    "offset": 16,
+                    "size": 7
+                  },
+                  "PREDIV_S": {
+                    "description": "Synchronous prescaler\n              factor",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "WUTR": {
+              "description": "wakeup timer register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WUT": {
+                    "description": "Wakeup auto-reload value\n              bits",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CALIBR": {
+              "description": "calibration register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DCS": {
+                    "description": "Digital calibration sign",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DC": {
+                    "description": "Digital calibration",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "ALRMAR": {
+              "description": "alarm A register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MSK4": {
+                    "description": "Alarm A date mask",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "WDSEL": {
+                    "description": "Week day selection",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units or day in BCD\n              format",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "MSK3": {
+                    "description": "Alarm A hours mask",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PM": {
+                    "description": "AM/PM notation",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "HT": {
+                    "description": "Hour tens in BCD format",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "HU": {
+                    "description": "Hour units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "MSK2": {
+                    "description": "Alarm A minutes mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MNT": {
+                    "description": "Minute tens in BCD format",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "MNU": {
+                    "description": "Minute units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSK1": {
+                    "description": "Alarm A seconds mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ST": {
+                    "description": "Second tens in BCD format",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SU": {
+                    "description": "Second units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "ALRMBR": {
+              "description": "alarm B register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MSK4": {
+                    "description": "Alarm B date mask",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "WDSEL": {
+                    "description": "Week day selection",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units or day in BCD\n              format",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "MSK3": {
+                    "description": "Alarm B hours mask",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PM": {
+                    "description": "AM/PM notation",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "HT": {
+                    "description": "Hour tens in BCD format",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "HU": {
+                    "description": "Hour units in BCD format",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "MSK2": {
+                    "description": "Alarm B minutes mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MNT": {
+                    "description": "Minute tens in BCD format",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "MNU": {
+                    "description": "Minute units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSK1": {
+                    "description": "Alarm B seconds mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ST": {
+                    "description": "Second tens in BCD format",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SU": {
+                    "description": "Second units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "WPR": {
+              "description": "write protection register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "KEY": {
+                    "description": "Write protection key",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SSR": {
+              "description": "sub second register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SS": {
+                    "description": "Sub second value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SHIFTR": {
+              "description": "shift control register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "ADD1S": {
+                    "description": "Add one second",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "SUBFS": {
+                    "description": "Subtract a fraction of a\n              second",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "TSTR": {
+              "description": "time stamp time register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ALARMOUTTYPE": {
+                    "description": "AFO_ALARM output type",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TSINSEL": {
+                    "description": "TIMESTAMP mapping",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TAMP1INSEL": {
+                    "description": "TAMPER1 mapping",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TAMPIE": {
+                    "description": "Tamper interrupt enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TAMP1TRG": {
+                    "description": "Active level for tamper 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TAMP1E": {
+                    "description": "Tamper 1 detection enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TSDR": {
+              "description": "time stamp date register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WDU": {
+                    "description": "Week day units",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "MT": {
+                    "description": "Month tens in BCD format",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "MU": {
+                    "description": "Month units in BCD format",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "DT": {
+                    "description": "Date tens in BCD format",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DU": {
+                    "description": "Date units in BCD format",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TSSSR": {
+              "description": "timestamp sub second register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SS": {
+                    "description": "Sub second value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CALR": {
+              "description": "calibration register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CALP": {
+                    "description": "Increase frequency of RTC by 488.5\n              ppm",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CALW8": {
+                    "description": "Use an 8-second calibration cycle\n              period",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CALW16": {
+                    "description": "Use a 16-second calibration cycle\n              period",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CALM": {
+                    "description": "Calibration minus",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "TAFCR": {
+              "description": "tamper and alternate function configuration\n          register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ALARMOUTTYPE": {
+                    "description": "AFO_ALARM output type",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TSINSEL": {
+                    "description": "TIMESTAMP mapping",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TAMP1INSEL": {
+                    "description": "TAMPER1 mapping",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TAMPPUDIS": {
+                    "description": "TAMPER pull-up disable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TAMPPRCH": {
+                    "description": "Tamper precharge duration",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "TAMPFLT": {
+                    "description": "Tamper filter count",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "TAMPFREQ": {
+                    "description": "Tamper sampling frequency",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "TAMPTS": {
+                    "description": "Activate timestamp on tamper detection\n              event",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TAMP2TRG": {
+                    "description": "Active level for tamper 2",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TAMP2E": {
+                    "description": "Tamper 2 detection enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TAMPIE": {
+                    "description": "Tamper interrupt enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TAMP1TRG": {
+                    "description": "Active level for tamper 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TAMP1E": {
+                    "description": "Tamper 1 detection enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ALRMASSR": {
+              "description": "alarm A sub second register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MASKSS": {
+                    "description": "Mask the most-significant bits starting\n              at this bit",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "SS": {
+                    "description": "Sub seconds value",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "ALRMBSSR": {
+              "description": "alarm B sub second register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MASKSS": {
+                    "description": "Mask the most-significant bits starting\n              at this bit",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "SS": {
+                    "description": "Sub seconds value",
+                    "offset": 0,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "BKP0R": {
+              "description": "backup register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP1R": {
+              "description": "backup register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP2R": {
+              "description": "backup register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP3R": {
+              "description": "backup register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP4R": {
+              "description": "backup register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP5R": {
+              "description": "backup register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP6R": {
+              "description": "backup register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP7R": {
+              "description": "backup register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP8R": {
+              "description": "backup register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP9R": {
+              "description": "backup register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP10R": {
+              "description": "backup register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP11R": {
+              "description": "backup register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP12R": {
+              "description": "backup register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP13R": {
+              "description": "backup register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP14R": {
+              "description": "backup register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP15R": {
+              "description": "backup register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP16R": {
+              "description": "backup register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP17R": {
+              "description": "backup register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP18R": {
+              "description": "backup register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BKP19R": {
+              "description": "backup register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKP": {
+                    "description": "BKP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UART4": {
+        "description": "Universal synchronous asynchronous receiver\n      transmitter",
+        "children": {
+          "registers": {
+            "SR": {
+              "description": "Status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 12582912,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LBD": {
+                    "description": "LIN break detection flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXE": {
+                    "description": "Transmit data register\n              empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TC": {
+                    "description": "Transmission complete",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNE": {
+                    "description": "Read data register not\n              empty",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLE": {
+                    "description": "IDLE line detected",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ORE": {
+                    "description": "Overrun error",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NF": {
+                    "description": "Noise detected flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FE": {
+                    "description": "Framing error",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PE": {
+                    "description": "Parity error",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "Data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data value",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "BRR": {
+              "description": "Baud rate register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIV_Mantissa": {
+                    "description": "mantissa of USARTDIV",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "DIV_Fraction": {
+                    "description": "fraction of USARTDIV",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "Control register 1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVER8": {
+                    "description": "Oversampling mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "UE": {
+                    "description": "USART enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "M": {
+                    "description": "Word length",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAKE": {
+                    "description": "Wakeup method",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PCE": {
+                    "description": "Parity control enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PS": {
+                    "description": "Parity selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PEIE": {
+                    "description": "PE interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TXEIE": {
+                    "description": "TXE interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transmission complete interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RXNEIE": {
+                    "description": "RXNE interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLEIE": {
+                    "description": "IDLE interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TE": {
+                    "description": "Transmitter enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RE": {
+                    "description": "Receiver enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RWU": {
+                    "description": "Receiver wakeup",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SBK": {
+                    "description": "Send break",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "Control register 2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LINEN": {
+                    "description": "LIN mode enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "STOP bits",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "LBDIE": {
+                    "description": "LIN break detection interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LBDL": {
+                    "description": "lin break detection length",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADD": {
+                    "description": "Address of the USART node",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CR3": {
+              "description": "Control register 3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ONEBIT": {
+                    "description": "One sample bit method\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DMAT": {
+                    "description": "DMA enable transmitter",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DMAR": {
+                    "description": "DMA enable receiver",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "HDSEL": {
+                    "description": "Half-duplex selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IRLP": {
+                    "description": "IrDA low-power",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IrDA mode enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_DEVICE": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_DCFG": {
+              "description": "OTG_FS device configuration register\n          (OTG_FS_DCFG)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 35651584,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DSPD": {
+                    "description": "Device speed",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "NZLSOHSK": {
+                    "description": "Non-zero-length status OUT\n              handshake",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 4,
+                    "size": 7
+                  },
+                  "PFIVL": {
+                    "description": "Periodic frame interval",
+                    "offset": 11,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_DCTL": {
+              "description": "OTG_FS device control register\n          (OTG_FS_DCTL)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWUSIG": {
+                    "description": "Remote wakeup signaling",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SDIS": {
+                    "description": "Soft disconnect",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GINSTS": {
+                    "description": "Global IN NAK status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GONSTS": {
+                    "description": "Global OUT NAK status",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TCTL": {
+                    "description": "Test control",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SGINAK": {
+                    "description": "Set global IN NAK",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CGINAK": {
+                    "description": "Clear global IN NAK",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SGONAK": {
+                    "description": "Set global OUT NAK",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CGONAK": {
+                    "description": "Clear global OUT NAK",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "POPRGDNE": {
+                    "description": "Power-on programming done",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_DSTS": {
+              "description": "OTG_FS device status register\n          (OTG_FS_DSTS)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SUSPSTS": {
+                    "description": "Suspend status",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ENUMSPD": {
+                    "description": "Enumerated speed",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "EERR": {
+                    "description": "Erratic error",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FNSOF": {
+                    "description": "Frame number of the received\n              SOF",
+                    "offset": 8,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "FS_DIEPMSK": {
+              "description": "OTG_FS device IN endpoint common interrupt\n          mask register (OTG_FS_DIEPMSK)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TOM": {
+                    "description": "Timeout condition mask (Non-isochronous\n              endpoints)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ITTXFEMSK": {
+                    "description": "IN token received when TxFIFO empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INEPNMM": {
+                    "description": "IN token received with EP mismatch\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INEPNEM": {
+                    "description": "IN endpoint NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_DOEPMSK": {
+              "description": "OTG_FS device OUT endpoint common interrupt\n          mask register (OTG_FS_DOEPMSK)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed interrupt\n              mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDM": {
+                    "description": "Endpoint disabled interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STUPM": {
+                    "description": "SETUP phase done mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OTEPDM": {
+                    "description": "OUT token received when endpoint\n              disabled mask",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_DAINT": {
+              "description": "OTG_FS device all endpoints interrupt\n          register (OTG_FS_DAINT)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IEPINT": {
+                    "description": "IN endpoint interrupt bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt\n              bits",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DAINTMSK": {
+              "description": "OTG_FS all endpoints interrupt mask register\n          (OTG_FS_DAINTMSK)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEPM": {
+                    "description": "IN EP interrupt mask bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt\n              bits",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DVBUSDIS": {
+              "description": "OTG_FS device VBUS discharge time\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 6103,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VBUSDT": {
+                    "description": "Device VBUS discharge time",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DVBUSPULSE": {
+              "description": "OTG_FS device VBUS pulsing time\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 1464,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DVBUSP": {
+                    "description": "Device VBUS pulsing time",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DIEPEMPMSK": {
+              "description": "OTG_FS device IN endpoint FIFO empty\n          interrupt mask register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXFEM": {
+                    "description": "IN EP Tx FIFO empty interrupt mask\n              bits",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPCTL0": {
+              "description": "OTG_FS device control IN endpoint 0 control\n          register (OTG_FS_DIEPCTL0)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "USBAEP": {
+                    "description": "USB active endpoint",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "STALL": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPENA": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DIEPCTL1": {
+              "description": "OTG device endpoint-1 control\n          register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM_SD1PID": {
+                    "description": "SODDFRM/SD1PID",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "TXFNUM",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEPCTL2": {
+              "description": "OTG device endpoint-2 control\n          register",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "TXFNUM",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEPCTL3": {
+              "description": "OTG device endpoint-3 control\n          register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "TXFNUM",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEPCTL0": {
+              "description": "device endpoint-0 control\n          register",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DOEPCTL1": {
+              "description": "device endpoint-1 control\n          register",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEPCTL2": {
+              "description": "device endpoint-2 control\n          register",
+              "offset": 832,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEPCTL3": {
+              "description": "device endpoint-3 control\n          register",
+              "offset": 864,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPENA": {
+                    "description": "EPENA",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "EPDIS",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SODDFRM": {
+                    "description": "SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVNFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "SNAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "CNAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "Stall": {
+                    "description": "Stall",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNPM": {
+                    "description": "SNPM",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "EPTYP",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKSTS": {
+                    "description": "NAKSTS",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EONUM_DPID": {
+                    "description": "EONUM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USBAEP": {
+                    "description": "USBAEP",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPSIZ": {
+                    "description": "MPSIZ",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEPINT0": {
+              "description": "device endpoint-x interrupt\n          register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPINT1": {
+              "description": "device endpoint-1 interrupt\n          register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPINT2": {
+              "description": "device endpoint-2 interrupt\n          register",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPINT3": {
+              "description": "device endpoint-3 interrupt\n          register",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "TXFE",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INEPNE": {
+                    "description": "INEPNE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ITTXFE": {
+                    "description": "ITTXFE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TOC": {
+                    "description": "TOC",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT0": {
+              "description": "device endpoint-0 interrupt\n          register",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT1": {
+              "description": "device endpoint-1 interrupt\n          register",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT2": {
+              "description": "device endpoint-2 interrupt\n          register",
+              "offset": 840,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINT3": {
+              "description": "device endpoint-3 interrupt\n          register",
+              "offset": 872,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "B2BSTUP": {
+                    "description": "B2BSTUP",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OTEPDIS": {
+                    "description": "OTEPDIS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STUP": {
+                    "description": "STUP",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDISD": {
+                    "description": "EPDISD",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XFRC": {
+                    "description": "XFRC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ0": {
+              "description": "device endpoint-0 transfer size\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 2
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ0": {
+              "description": "device OUT endpoint-0 transfer size\n          register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STUPCNT": {
+                    "description": "SETUP packet count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ1": {
+              "description": "device endpoint-1 transfer size\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ2": {
+              "description": "device endpoint-2 transfer size\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DIEPTSIZ3": {
+              "description": "device endpoint-3 transfer size\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCNT": {
+                    "description": "Multi count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DTXFSTS0": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DTXFSTS1": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DTXFSTS2": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DTXFSTS3": {
+              "description": "OTG_FS device IN endpoint transmit FIFO\n          status register",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INEPTFSAV": {
+                    "description": "IN endpoint TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ1": {
+              "description": "device OUT endpoint-1 transfer size\n          register",
+              "offset": 816,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ2": {
+              "description": "device OUT endpoint-2 transfer size\n          register",
+              "offset": 848,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DOEPTSIZ3": {
+              "description": "device OUT endpoint-3 transfer size\n          register",
+              "offset": 880,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDPID_STUPCNT": {
+                    "description": "Received data PID/SETUP packet\n              count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "C_ADC": {
+        "description": "Common ADC registers",
+        "children": {
+          "registers": {
+            "CSR": {
+              "description": "ADC Common status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "OVR3": {
+                    "description": "Overrun flag of ADC3",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "STRT3": {
+                    "description": "Regular channel Start flag of ADC\n              3",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "JSTRT3": {
+                    "description": "Injected channel Start flag of ADC\n              3",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "JEOC3": {
+                    "description": "Injected channel end of conversion of\n              ADC 3",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EOC3": {
+                    "description": "End of conversion of ADC 3",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "AWD3": {
+                    "description": "Analog watchdog flag of ADC\n              3",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "OVR2": {
+                    "description": "Overrun flag of ADC 2",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "STRT2": {
+                    "description": "Regular channel Start flag of ADC\n              2",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "JSTRT2": {
+                    "description": "Injected channel Start flag of ADC\n              2",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "JEOC2": {
+                    "description": "Injected channel end of conversion of\n              ADC 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EOC2": {
+                    "description": "End of conversion of ADC 2",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "AWD2": {
+                    "description": "Analog watchdog flag of ADC\n              2",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OVR1": {
+                    "description": "Overrun flag of ADC 1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "STRT1": {
+                    "description": "Regular channel Start flag of ADC\n              1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "JSTRT1": {
+                    "description": "Injected channel Start flag of ADC\n              1",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "JEOC1": {
+                    "description": "Injected channel end of conversion of\n              ADC 1",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EOC1": {
+                    "description": "End of conversion of ADC 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AWD1": {
+                    "description": "Analog watchdog flag of ADC\n              1",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "ADC common control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSVREFE": {
+                    "description": "Temperature sensor and VREFINT\n              enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "VBATE": {
+                    "description": "VBAT enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "ADCPRE": {
+                    "description": "ADC prescaler",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA": {
+                    "description": "Direct memory access mode for multi ADC\n              mode",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DDS": {
+                    "description": "DMA disable selection for multi-ADC\n              mode",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "DELAY": {
+                    "description": "Delay between 2 sampling\n              phases",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MULT": {
+                    "description": "Multi ADC mode selection",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CDR": {
+              "description": "ADC common regular data register for dual\n          and triple modes",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DATA2": {
+                    "description": "2nd data item of a pair of regular\n              conversions",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "DATA1": {
+                    "description": "1st data item of a pair of regular\n              conversions",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM1": {
+        "description": "Advanced-timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OIS4": {
+                    "description": "Output Idle state 4",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OIS3N": {
+                    "description": "Output Idle state 3",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OIS3": {
+                    "description": "Output Idle state 3",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OIS2N": {
+                    "description": "Output Idle state 2",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OIS2": {
+                    "description": "Output Idle state 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OIS1N": {
+                    "description": "Output Idle state 1",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OIS1": {
+                    "description": "Output Idle state 1",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CCUS": {
+                    "description": "Capture/compare control update\n              selection",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CCPC": {
+                    "description": "Capture/compare preloaded\n              control",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "COMDE": {
+                    "description": "COM DMA request enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BIE": {
+                    "description": "Break interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "COMIE": {
+                    "description": "COM interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BIF": {
+                    "description": "Break interrupt flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMIF": {
+                    "description": "COM interrupt flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BG": {
+                    "description": "Break generation",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "COMG": {
+                    "description": "Capture/Compare control update\n              generation",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "Output Compare 2 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "Output Compare 2 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "Output Compare 2 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "Output Compare 2 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "Output Compare 1 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register 2 (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC4CE": {
+                    "description": "Output compare 4 clear\n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "Output compare 4 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "Output compare 4 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "Output compare 4 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "Output compare 3 clear\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "Output compare 3 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "Output compare 3 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "Output compare 3 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "Capture/Compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC3NE": {
+                    "description": "Capture/Compare 3 complementary output\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2NE": {
+                    "description": "Capture/Compare 2 complementary output\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1NE": {
+                    "description": "Capture/Compare 1 complementary output\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2": {
+                    "description": "Capture/Compare 2 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3": {
+                    "description": "Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4": {
+                    "description": "Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RCR": {
+              "description": "repetition counter register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REP": {
+                    "description": "Repetition counter value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "BDTR": {
+              "description": "break and dead-time register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MOE": {
+                    "description": "Main output enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "AOE": {
+                    "description": "Automatic output enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BKP": {
+                    "description": "Break polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BKE": {
+                    "description": "Break enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OSSR": {
+                    "description": "Off-state selection for Run\n              mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OSSI": {
+                    "description": "Off-state selection for Idle\n              mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LOCK": {
+                    "description": "Lock configuration",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "DTG": {
+                    "description": "Dead-time generator setup",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_HOST": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_HCFG": {
+              "description": "OTG_FS host configuration register\n          (OTG_FS_HCFG)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FSLSPCS": {
+                    "description": "FS/LS PHY clock select",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "FSLSS": {
+                    "description": "FS- and LS-only support",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "HFIR": {
+              "description": "OTG_FS Host frame interval\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 60000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRIVL": {
+                    "description": "Frame interval",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_HFNUM": {
+              "description": "OTG_FS host frame number/frame time\n          remaining register (OTG_FS_HFNUM)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 16383,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FRNUM": {
+                    "description": "Frame number",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "FTREM": {
+                    "description": "Frame time remaining",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_HPTXSTS": {
+              "description": "OTG_FS_Host periodic transmit FIFO/queue\n          status register (OTG_FS_HPTXSTS)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 524544,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTXFSAVL": {
+                    "description": "Periodic transmit data FIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PTXQSAV": {
+                    "description": "Periodic transmit request queue space\n              available",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "PTXQTOP": {
+                    "description": "Top of the periodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "HAINT": {
+              "description": "OTG_FS Host all channels interrupt\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HAINT": {
+                    "description": "Channel interrupts",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "HAINTMSK": {
+              "description": "OTG_FS host all channels interrupt mask\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HAINTM": {
+                    "description": "Channel interrupt mask",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_HPRT": {
+              "description": "OTG_FS host port control and status register\n          (OTG_FS_HPRT)",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCSTS": {
+                    "description": "Port connect status",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PCDET": {
+                    "description": "Port connect detected",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PENA": {
+                    "description": "Port enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PENCHNG": {
+                    "description": "Port enable/disable change",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "POCA": {
+                    "description": "Port overcurrent active",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "POCCHNG": {
+                    "description": "Port overcurrent change",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PRES": {
+                    "description": "Port resume",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PSUSP": {
+                    "description": "Port suspend",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PRST": {
+                    "description": "Port reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PLSTS": {
+                    "description": "Port line status",
+                    "offset": 10,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PPWR": {
+                    "description": "Port power",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PTCTL": {
+                    "description": "Port test control",
+                    "offset": 13,
+                    "size": 4
+                  },
+                  "PSPD": {
+                    "description": "Port speed",
+                    "offset": 17,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR0": {
+              "description": "OTG_FS host channel-0 characteristics\n          register (OTG_FS_HCCHAR0)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR1": {
+              "description": "OTG_FS host channel-1 characteristics\n          register (OTG_FS_HCCHAR1)",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR2": {
+              "description": "OTG_FS host channel-2 characteristics\n          register (OTG_FS_HCCHAR2)",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR3": {
+              "description": "OTG_FS host channel-3 characteristics\n          register (OTG_FS_HCCHAR3)",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR4": {
+              "description": "OTG_FS host channel-4 characteristics\n          register (OTG_FS_HCCHAR4)",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR5": {
+              "description": "OTG_FS host channel-5 characteristics\n          register (OTG_FS_HCCHAR5)",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR6": {
+              "description": "OTG_FS host channel-6 characteristics\n          register (OTG_FS_HCCHAR6)",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCCHAR7": {
+              "description": "OTG_FS host channel-7 characteristics\n          register (OTG_FS_HCCHAR7)",
+              "offset": 480,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPSIZ": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSDEV": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYP": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MCNT": {
+                    "description": "Multicount",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "DAD": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CHDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CHENA": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT0": {
+              "description": "OTG_FS host channel-0 interrupt register\n          (OTG_FS_HCINT0)",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT1": {
+              "description": "OTG_FS host channel-1 interrupt register\n          (OTG_FS_HCINT1)",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT2": {
+              "description": "OTG_FS host channel-2 interrupt register\n          (OTG_FS_HCINT2)",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT3": {
+              "description": "OTG_FS host channel-3 interrupt register\n          (OTG_FS_HCINT3)",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT4": {
+              "description": "OTG_FS host channel-4 interrupt register\n          (OTG_FS_HCINT4)",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT5": {
+              "description": "OTG_FS host channel-5 interrupt register\n          (OTG_FS_HCINT5)",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT6": {
+              "description": "OTG_FS host channel-6 interrupt register\n          (OTG_FS_HCINT6)",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINT7": {
+              "description": "OTG_FS host channel-7 interrupt register\n          (OTG_FS_HCINT7)",
+              "offset": 488,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRC": {
+                    "description": "Transfer completed",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXERR": {
+                    "description": "Transaction error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERR": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMOR": {
+                    "description": "Frame overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERR": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK0": {
+              "description": "OTG_FS host channel-0 mask register\n          (OTG_FS_HCINTMSK0)",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK1": {
+              "description": "OTG_FS host channel-1 mask register\n          (OTG_FS_HCINTMSK1)",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK2": {
+              "description": "OTG_FS host channel-2 mask register\n          (OTG_FS_HCINTMSK2)",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK3": {
+              "description": "OTG_FS host channel-3 mask register\n          (OTG_FS_HCINTMSK3)",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK4": {
+              "description": "OTG_FS host channel-4 mask register\n          (OTG_FS_HCINTMSK4)",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK5": {
+              "description": "OTG_FS host channel-5 mask register\n          (OTG_FS_HCINTMSK5)",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK6": {
+              "description": "OTG_FS host channel-6 mask register\n          (OTG_FS_HCINTMSK6)",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCINTMSK7": {
+              "description": "OTG_FS host channel-7 mask register\n          (OTG_FS_HCINTMSK7)",
+              "offset": 492,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRCM": {
+                    "description": "Transfer completed mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHHM": {
+                    "description": "Channel halted mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLM": {
+                    "description": "STALL response received interrupt\n              mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKM": {
+                    "description": "NAK response received interrupt\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKM": {
+                    "description": "ACK response received/transmitted\n              interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NYET": {
+                    "description": "response received interrupt\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXERRM": {
+                    "description": "Transaction error mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERRM": {
+                    "description": "Babble error mask",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FRMORM": {
+                    "description": "Frame overrun mask",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERRM": {
+                    "description": "Data toggle error mask",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ0": {
+              "description": "OTG_FS host channel-0 transfer size\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ1": {
+              "description": "OTG_FS host channel-1 transfer size\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ2": {
+              "description": "OTG_FS host channel-2 transfer size\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ3": {
+              "description": "OTG_FS host channel-3 transfer size\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ4": {
+              "description": "OTG_FS host channel-x transfer size\n          register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ5": {
+              "description": "OTG_FS host channel-5 transfer size\n          register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ6": {
+              "description": "OTG_FS host channel-6 transfer size\n          register",
+              "offset": 464,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FS_HCTSIZ7": {
+              "description": "OTG_FS host channel-7 transfer size\n          register",
+              "offset": 496,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XFRSIZ": {
+                    "description": "Transfer size",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PKTCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM2": {
+        "description": "General purpose timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "OC2CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "OC2M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "OC2PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "OC2FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "CC2S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "OC1CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "OC1M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "OC1PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "OC1FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "CC1S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register 2 (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "O24CE": {
+                    "description": "O24CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "OC4M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "OC4PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "OC4FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "CC4S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "OC3CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "OC3M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "OC3PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "OC3FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "CC3S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4NP": {
+                    "description": "Capture/Compare 4 output\n              Polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT_H": {
+                    "description": "High counter value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CNT_L": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR_H": {
+                    "description": "High Auto-reload value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ARR_L": {
+                    "description": "Low Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1_H": {
+                    "description": "High Capture/Compare 1\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR1_L": {
+                    "description": "Low Capture/Compare 1\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2_H": {
+                    "description": "High Capture/Compare 2\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR2_L": {
+                    "description": "Low Capture/Compare 2\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR3_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR4_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OR": {
+              "description": "TIM5 option register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ITR1_RMP": {
+                    "description": "Timer Input 4 remap",
+                    "offset": 10,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM3": {
+        "description": "General purpose timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "OC2CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "OC2M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "OC2PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "OC2FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "CC2S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "OC1CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "OC1M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "OC1PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "OC1FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "CC1S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register 2 (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "O24CE": {
+                    "description": "O24CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "OC4M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "OC4PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "OC4FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "CC4S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "OC3CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "OC3M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "OC3PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "OC3FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "CC3S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4NP": {
+                    "description": "Capture/Compare 4 output\n              Polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT_H": {
+                    "description": "High counter value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CNT_L": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR_H": {
+                    "description": "High Auto-reload value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ARR_L": {
+                    "description": "Low Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1_H": {
+                    "description": "High Capture/Compare 1\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR1_L": {
+                    "description": "Low Capture/Compare 1\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2_H": {
+                    "description": "High Capture/Compare 2\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR2_L": {
+                    "description": "Low Capture/Compare 2\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR3_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR4_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "OTG_FS_GLOBAL": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "FS_GOTGCTL": {
+              "description": "OTG_FS control and status register\n          (OTG_FS_GOTGCTL)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRQSCS": {
+                    "description": "Session request success",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SRQ": {
+                    "description": "Session request",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HNGSCS": {
+                    "description": "Host negotiation success",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HNPRQ": {
+                    "description": "HNP request",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HSHNPEN": {
+                    "description": "Host set HNP enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DHNPEN": {
+                    "description": "Device HNP enabled",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CIDSTS": {
+                    "description": "Connector ID status",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DBCT": {
+                    "description": "Long/short debounce time",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ASVLD": {
+                    "description": "A-session valid",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BSVLD": {
+                    "description": "B-session valid",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FS_GOTGINT": {
+              "description": "OTG_FS interrupt register\n          (OTG_FS_GOTGINT)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEDET": {
+                    "description": "Session end detected",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SRSSCHG": {
+                    "description": "Session request success status\n              change",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNSSCHG": {
+                    "description": "Host negotiation success status\n              change",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HNGDET": {
+                    "description": "Host negotiation detected",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ADTOCHG": {
+                    "description": "A-device timeout change",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DBCDNE": {
+                    "description": "Debounce done",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GAHBCFG": {
+              "description": "OTG_FS AHB configuration register\n          (OTG_FS_GAHBCFG)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GINT": {
+                    "description": "Global interrupt mask",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXFELVL": {
+                    "description": "TxFIFO empty level",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PTXFELVL": {
+                    "description": "Periodic TxFIFO empty\n              level",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GUSBCFG": {
+              "description": "OTG_FS USB configuration register\n          (OTG_FS_GUSBCFG)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 2560,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TOCAL": {
+                    "description": "FS timeout calibration",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "PHYSEL": {
+                    "description": "Full Speed serial transceiver\n              select",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SRPCAP": {
+                    "description": "SRP-capable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNPCAP": {
+                    "description": "HNP-capable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TRDT": {
+                    "description": "USB turnaround time",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "FHMOD": {
+                    "description": "Force host mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FDMOD": {
+                    "description": "Force device mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CTXPKT": {
+                    "description": "Corrupt Tx packet",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GRSTCTL": {
+              "description": "OTG_FS reset register\n          (OTG_FS_GRSTCTL)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 536870912,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSRST": {
+                    "description": "Core soft reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HSRST": {
+                    "description": "HCLK soft reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FCRST": {
+                    "description": "Host frame counter reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RXFFLSH": {
+                    "description": "RxFIFO flush",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TXFFLSH": {
+                    "description": "TxFIFO flush",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 6,
+                    "size": 5
+                  },
+                  "AHBIDL": {
+                    "description": "AHB master idle",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FS_GINTSTS": {
+              "description": "OTG_FS core interrupt register\n          (OTG_FS_GINTSTS)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 67108896,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CMOD": {
+                    "description": "Current mode of operation",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMIS": {
+                    "description": "Mode mismatch interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGINT": {
+                    "description": "OTG interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOF": {
+                    "description": "Start of frame",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFLVL": {
+                    "description": "RxFIFO non-empty",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NPTXFE": {
+                    "description": "Non-periodic TxFIFO empty",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GINAKEFF": {
+                    "description": "Global IN non-periodic NAK\n              effective",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GOUTNAKEFF": {
+                    "description": "Global OUT NAK effective",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ESUSP": {
+                    "description": "Early suspend",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "USBSUSP": {
+                    "description": "USB suspend",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMDNE": {
+                    "description": "Enumeration done",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOODRP": {
+                    "description": "Isochronous OUT packet dropped\n              interrupt",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPF": {
+                    "description": "End of periodic frame\n              interrupt",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IEPINT": {
+                    "description": "IN endpoint interrupt",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoint interrupt",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IISOIXFR": {
+                    "description": "Incomplete isochronous IN\n              transfer",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "IPXFR_INCOMPISOOUT": {
+                    "description": "Incomplete periodic transfer(Host\n              mode)/Incomplete isochronous OUT transfer(Device\n              mode)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HPRTINT": {
+                    "description": "Host port interrupt",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCINT": {
+                    "description": "Host channels interrupt",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PTXFE": {
+                    "description": "Periodic TxFIFO empty",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CIDSCHG": {
+                    "description": "Connector ID status change",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCINT": {
+                    "description": "Disconnect detected\n              interrupt",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SRQINT": {
+                    "description": "Session request/new session detected\n              interrupt",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WKUPINT": {
+                    "description": "Resume/remote wakeup detected\n              interrupt",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GINTMSK": {
+              "description": "OTG_FS interrupt mask register\n          (OTG_FS_GINTMSK)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMISM": {
+                    "description": "Mode mismatch interrupt\n              mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGINT": {
+                    "description": "OTG interrupt mask",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SOFM": {
+                    "description": "Start of frame mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFLVLM": {
+                    "description": "Receive FIFO non-empty\n              mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "NPTXFEM": {
+                    "description": "Non-periodic TxFIFO empty\n              mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GINAKEFFM": {
+                    "description": "Global non-periodic IN NAK effective\n              mask",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GONAKEFFM": {
+                    "description": "Global OUT NAK effective\n              mask",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ESUSPM": {
+                    "description": "Early suspend mask",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "USBSUSPM": {
+                    "description": "USB suspend mask",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "USBRST": {
+                    "description": "USB reset mask",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMDNEM": {
+                    "description": "Enumeration done mask",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOODRPM": {
+                    "description": "Isochronous OUT packet dropped interrupt\n              mask",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPFM": {
+                    "description": "End of periodic frame interrupt\n              mask",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPMISM": {
+                    "description": "Endpoint mismatch interrupt\n              mask",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "IEPINT": {
+                    "description": "IN endpoints interrupt\n              mask",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OEPINT": {
+                    "description": "OUT endpoints interrupt\n              mask",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IISOIXFRM": {
+                    "description": "Incomplete isochronous IN transfer\n              mask",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "IPXFRM_IISOOXFRM": {
+                    "description": "Incomplete periodic transfer mask(Host\n              mode)/Incomplete isochronous OUT transfer mask(Device\n              mode)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "PRTIM": {
+                    "description": "Host port interrupt mask",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCIM": {
+                    "description": "Host channels interrupt\n              mask",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PTXFEM": {
+                    "description": "Periodic TxFIFO empty mask",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CIDSCHGM": {
+                    "description": "Connector ID status change\n              mask",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCINT": {
+                    "description": "Disconnect detected interrupt\n              mask",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SRQIM": {
+                    "description": "Session request/new session detected\n              interrupt mask",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WUIM": {
+                    "description": "Resume/remote wakeup detected interrupt\n              mask",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_GRXSTSR_Device": {
+              "description": "OTG_FS Receive status debug read(Device\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  },
+                  "FRMNUM": {
+                    "description": "Frame number",
+                    "offset": 21,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "FS_GRXSTSR_Host": {
+              "description": "OTG_FS Receive status debug\n          read(Hostmode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "PKTSTS": {
+                    "description": "Packet status",
+                    "offset": 17,
+                    "size": 4
+                  },
+                  "FRMNUM": {
+                    "description": "Frame number",
+                    "offset": 21,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "FS_GRXFSIZ": {
+              "description": "OTG_FS Receive FIFO size register\n          (OTG_FS_GRXFSIZ)",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFD": {
+                    "description": "RxFIFO depth",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_GNPTXFSIZ_Device": {
+              "description": "OTG_FS non-periodic transmit FIFO size\n          register (Device mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX0FSA": {
+                    "description": "Endpoint 0 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "TX0FD": {
+                    "description": "Endpoint 0 TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_GNPTXFSIZ_Host": {
+              "description": "OTG_FS non-periodic transmit FIFO size\n          register (Host mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NPTXFSA": {
+                    "description": "Non-periodic transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "NPTXFD": {
+                    "description": "Non-periodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_GNPTXSTS": {
+              "description": "OTG_FS non-periodic transmit FIFO/queue\n          status register (OTG_FS_GNPTXSTS)",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 524800,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "NPTXFSAV": {
+                    "description": "Non-periodic TxFIFO space\n              available",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "NPTQXSAV": {
+                    "description": "Non-periodic transmit request queue\n              space available",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "NPTXQTOP": {
+                    "description": "Top of the non-periodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "FS_GCCFG": {
+              "description": "OTG_FS general core configuration register\n          (OTG_FS_GCCFG)",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWRDWN": {
+                    "description": "Power down",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "VBUSASEN": {
+                    "description": "Enable the VBUS sensing\n              device",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "VBUSBSEN": {
+                    "description": "Enable the VBUS sensing\n              device",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SOFOUTEN": {
+                    "description": "SOF output enable",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FS_CID": {
+              "description": "core ID register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 4096,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRODUCT_ID": {
+                    "description": "Product ID field",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FS_HPTXFSIZ": {
+              "description": "OTG_FS Host periodic transmit FIFO size\n          register (OTG_FS_HPTXFSIZ)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 33555968,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTXSA": {
+                    "description": "Host periodic TxFIFO start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PTXFSIZ": {
+                    "description": "Host periodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPTXF1": {
+              "description": "OTG_FS device IN endpoint transmit FIFO size\n          register (OTG_FS_DIEPTXF2)",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFO2 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPTXF2": {
+              "description": "OTG_FS device IN endpoint transmit FIFO size\n          register (OTG_FS_DIEPTXF3)",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFO3 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FS_DIEPTXF3": {
+              "description": "OTG_FS device IN endpoint transmit FIFO size\n          register (OTG_FS_DIEPTXF4)",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INEPTXSA": {
+                    "description": "IN endpoint FIFO4 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "INEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM5": {
+        "description": "General-purpose-timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CMS": {
+                    "description": "Center-aligned mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TI1S": {
+                    "description": "TI1 selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CCDS": {
+                    "description": "Capture/compare DMA\n              selection",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ECE": {
+                    "description": "External clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPS": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETF": {
+                    "description": "External trigger filter",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CC4DE": {
+                    "description": "Capture/Compare 4 DMA request\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3DE": {
+                    "description": "Capture/Compare 3 DMA request\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2DE": {
+                    "description": "Capture/Compare 2 DMA request\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1DE": {
+                    "description": "Capture/Compare 1 DMA request\n              enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UDE": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IE": {
+                    "description": "Capture/Compare 4 interrupt\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IE": {
+                    "description": "Capture/Compare 3 interrupt\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4OF": {
+                    "description": "Capture/Compare 4 overcapture\n              flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3OF": {
+                    "description": "Capture/Compare 3 overcapture\n              flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4IF": {
+                    "description": "Capture/Compare 4 interrupt\n              flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3IF": {
+                    "description": "Capture/Compare 3 interrupt\n              flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC4G": {
+                    "description": "Capture/compare 4\n              generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC3G": {
+                    "description": "Capture/compare 3\n              generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2CE": {
+                    "description": "OC2CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC2M": {
+                    "description": "OC2M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "OC2PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "OC2FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "CC2S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1CE": {
+                    "description": "OC1CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC1M": {
+                    "description": "OC1M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "OC1PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "OC1FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "CC1S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Output": {
+              "description": "capture/compare mode register 2 (output\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "O24CE": {
+                    "description": "O24CE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OC4M": {
+                    "description": "OC4M",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC4PE": {
+                    "description": "OC4PE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC4FE": {
+                    "description": "OC4FE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC4S": {
+                    "description": "CC4S",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC3CE": {
+                    "description": "OC3CE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OC3M": {
+                    "description": "OC3M",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC3PE": {
+                    "description": "OC3PE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC3FE": {
+                    "description": "OC3FE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC3S": {
+                    "description": "CC3S",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR2_Input": {
+              "description": "capture/compare mode register 2 (input\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC4F": {
+                    "description": "Input capture 4 filter",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "IC4PSC": {
+                    "description": "Input capture 4 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC4S": {
+                    "description": "Capture/Compare 4\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC3F": {
+                    "description": "Input capture 3 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "IC3PSC": {
+                    "description": "Input capture 3 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC3S": {
+                    "description": "Capture/compare 3\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC4NP": {
+                    "description": "Capture/Compare 4 output\n              Polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CC4P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CC4E": {
+                    "description": "Capture/Compare 4 output\n              enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CC3NP": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CC3P": {
+                    "description": "Capture/Compare 3 output\n              Polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC3E": {
+                    "description": "Capture/Compare 3 output\n              enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT_H": {
+                    "description": "High counter value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CNT_L": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR_H": {
+                    "description": "High Auto-reload value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ARR_L": {
+                    "description": "Low Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1_H": {
+                    "description": "High Capture/Compare 1\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR1_L": {
+                    "description": "Low Capture/Compare 1\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2_H": {
+                    "description": "High Capture/Compare 2\n              value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR2_L": {
+                    "description": "Low Capture/Compare 2\n              value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR3": {
+              "description": "capture/compare register 3",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR3_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR3_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR4": {
+              "description": "capture/compare register 4",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR4_H": {
+                    "description": "High Capture/Compare value",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "CCR4_L": {
+                    "description": "Low Capture/Compare value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DCR": {
+              "description": "DMA control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBL": {
+                    "description": "DMA burst length",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DBA": {
+                    "description": "DMA base address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMAR": {
+              "description": "DMA address for full transfer",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMAB": {
+                    "description": "DMA register for burst\n              accesses",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OR": {
+              "description": "TIM5 option register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IT4_RMP": {
+                    "description": "Timer Input 4 remap",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM9": {
+        "description": "General purpose timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OPM": {
+                    "description": "One-pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CR2": {
+              "description": "control register 2",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMS": {
+                    "description": "Master mode selection",
+                    "offset": 4,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMS": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2IE": {
+                    "description": "Capture/Compare 2 interrupt\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC2OF": {
+                    "description": "Capture/compare 2 overcapture\n              flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2IF": {
+                    "description": "Capture/Compare 2 interrupt\n              flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TG": {
+                    "description": "Trigger generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CC2G": {
+                    "description": "Capture/compare 2\n              generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC2M": {
+                    "description": "Output Compare 2 mode",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "OC2PE": {
+                    "description": "Output Compare 2 preload\n              enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OC2FE": {
+                    "description": "Output Compare 2 fast\n              enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC2F": {
+                    "description": "Input capture 2 filter",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "IC2PCS": {
+                    "description": "Input capture 2 prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CC2S": {
+                    "description": "Capture/Compare 2\n              selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC2NP": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CC2P": {
+                    "description": "Capture/Compare 2 output\n              Polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CC2E": {
+                    "description": "Capture/Compare 2 output\n              enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR2": {
+              "description": "capture/compare register 2",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR2": {
+                    "description": "Capture/Compare 2 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CRC": {
+        "description": "Cryptographic processor",
+        "children": {
+          "registers": {
+            "DR": {
+              "description": "Data register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "Data Register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "Independent Data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IDR": {
+                    "description": "Independent Data register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CR": {
+              "description": "Control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CR": {
+                    "description": "Control regidter",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM10": {
+        "description": "General-purpose-timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "Ethernet_DMA": {
+        "description": "Ethernet: DMA controller operation",
+        "children": {
+          "registers": {
+            "DMABMR": {
+              "description": "Ethernet DMA bus mode register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 8449,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SR": {
+                    "description": "SR",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DA": {
+                    "description": "DA",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DSL": {
+                    "description": "DSL",
+                    "offset": 2,
+                    "size": 5
+                  },
+                  "EDFE": {
+                    "description": "EDFE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PBL": {
+                    "description": "PBL",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "RTPR": {
+                    "description": "RTPR",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "FB": {
+                    "description": "FB",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RDP": {
+                    "description": "RDP",
+                    "offset": 17,
+                    "size": 6
+                  },
+                  "USP": {
+                    "description": "USP",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FPM": {
+                    "description": "FPM",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "AAB": {
+                    "description": "AAB",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "MB": {
+                    "description": "MB",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMATPDR": {
+              "description": "Ethernet DMA transmit poll demand\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TPD": {
+                    "description": "TPD",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMARPDR": {
+              "description": "EHERNET DMA receive poll demand\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RPD": {
+                    "description": "RPD",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMARDLAR": {
+              "description": "Ethernet DMA receive descriptor list address\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRL": {
+                    "description": "SRL",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMATDLAR": {
+              "description": "Ethernet DMA transmit descriptor list\n          address register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STL": {
+                    "description": "STL",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMASR": {
+              "description": "Ethernet DMA status register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TS": {
+                    "description": "TS",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TPSS": {
+                    "description": "TPSS",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TBUS": {
+                    "description": "TBUS",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TJTS": {
+                    "description": "TJTS",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ROS": {
+                    "description": "ROS",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TUS": {
+                    "description": "TUS",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RS": {
+                    "description": "RS",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RBUS": {
+                    "description": "RBUS",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RPSS": {
+                    "description": "RPSS",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PWTS": {
+                    "description": "PWTS",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ETS": {
+                    "description": "ETS",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FBES": {
+                    "description": "FBES",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ERS": {
+                    "description": "ERS",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "AIS": {
+                    "description": "AIS",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "NIS": {
+                    "description": "NIS",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RPS": {
+                    "description": "RPS",
+                    "offset": 17,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "TPS": {
+                    "description": "TPS",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "EBS": {
+                    "description": "EBS",
+                    "offset": 23,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "MMCS": {
+                    "description": "MMCS",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PMTS": {
+                    "description": "PMTS",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TSTS": {
+                    "description": "TSTS",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DMAOMR": {
+              "description": "Ethernet DMA operation mode\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SR": {
+                    "description": "SR",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OSF": {
+                    "description": "OSF",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTC": {
+                    "description": "RTC",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "FUGF": {
+                    "description": "FUGF",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FEF": {
+                    "description": "FEF",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ST": {
+                    "description": "ST",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TTC": {
+                    "description": "TTC",
+                    "offset": 14,
+                    "size": 3
+                  },
+                  "FTF": {
+                    "description": "FTF",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TSF": {
+                    "description": "TSF",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "DFRF": {
+                    "description": "DFRF",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "RSF": {
+                    "description": "RSF",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DTCEFD": {
+                    "description": "DTCEFD",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMAIER": {
+              "description": "Ethernet DMA interrupt enable\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIE": {
+                    "description": "TIE",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TPSIE": {
+                    "description": "TPSIE",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TBUIE": {
+                    "description": "TBUIE",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TJTIE": {
+                    "description": "TJTIE",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ROIE": {
+                    "description": "ROIE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TUIE": {
+                    "description": "TUIE",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RIE": {
+                    "description": "RIE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RBUIE": {
+                    "description": "RBUIE",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RPSIE": {
+                    "description": "RPSIE",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RWTIE": {
+                    "description": "RWTIE",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ETIE": {
+                    "description": "ETIE",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FBEIE": {
+                    "description": "FBEIE",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ERIE": {
+                    "description": "ERIE",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "AISE": {
+                    "description": "AISE",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "NISE": {
+                    "description": "NISE",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMAMFBOCR": {
+              "description": "Ethernet DMA missed frame and buffer\n          overflow counter register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MFC": {
+                    "description": "MFC",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "OMFC": {
+                    "description": "OMFC",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MFA": {
+                    "description": "MFA",
+                    "offset": 17,
+                    "size": 11
+                  },
+                  "OFOC": {
+                    "description": "OFOC",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMARSWTR": {
+              "description": "Ethernet DMA receive status watchdog timer\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RSWTC": {
+                    "description": "RSWTC",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DMACHTDR": {
+              "description": "Ethernet DMA current host transmit\n          descriptor register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HTDAP": {
+                    "description": "HTDAP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMACHRDR": {
+              "description": "Ethernet DMA current host receive descriptor\n          register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HRDAP": {
+                    "description": "HRDAP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMACHTBAR": {
+              "description": "Ethernet DMA current host transmit buffer\n          address register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HTBAP": {
+                    "description": "HTBAP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DMACHRBAR": {
+              "description": "Ethernet DMA current host receive buffer\n          address register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HRBAP": {
+                    "description": "HRBAP",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "Ethernet_PTP": {
+        "description": "Ethernet: Precision time protocol",
+        "children": {
+          "registers": {
+            "PTPTSCR": {
+              "description": "Ethernet PTP time stamp control\n          register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 8192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSE": {
+                    "description": "TSE",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TSFCU": {
+                    "description": "TSFCU",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TSPTPPSV2E": {
+                    "description": "TSPTPPSV2E",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TSSPTPOEFE": {
+                    "description": "TSSPTPOEFE",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TSSIPV6FE": {
+                    "description": "TSSIPV6FE",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TSSIPV4FE": {
+                    "description": "TSSIPV4FE",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TSSEME": {
+                    "description": "TSSEME",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TSSMRME": {
+                    "description": "TSSMRME",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TSCNT": {
+                    "description": "TSCNT",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "TSPFFMAE": {
+                    "description": "TSPFFMAE",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TSSTI": {
+                    "description": "TSSTI",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TSSTU": {
+                    "description": "TSSTU",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TSITE": {
+                    "description": "TSITE",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TTSARU": {
+                    "description": "TTSARU",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TSSARFE": {
+                    "description": "TSSARFE",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TSSSR": {
+                    "description": "TSSSR",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PTPSSIR": {
+              "description": "Ethernet PTP subsecond increment\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STSSI": {
+                    "description": "STSSI",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PTPTSHR": {
+              "description": "Ethernet PTP time stamp high\n          register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STS": {
+                    "description": "STS",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTSLR": {
+              "description": "Ethernet PTP time stamp low\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "STSS": {
+                    "description": "STSS",
+                    "offset": 0,
+                    "size": 31
+                  },
+                  "STPNS": {
+                    "description": "STPNS",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PTPTSHUR": {
+              "description": "Ethernet PTP time stamp high update\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSUS": {
+                    "description": "TSUS",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTSLUR": {
+              "description": "Ethernet PTP time stamp low update\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSUSS": {
+                    "description": "TSUSS",
+                    "offset": 0,
+                    "size": 31
+                  },
+                  "TSUPNS": {
+                    "description": "TSUSS",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PTPTSAR": {
+              "description": "Ethernet PTP time stamp addend\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSA": {
+                    "description": "TSA",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTTHR": {
+              "description": "Ethernet PTP target time high\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TTSH": {
+                    "description": "0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTTLR": {
+              "description": "Ethernet PTP target time low\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TTSL": {
+                    "description": "TTSL",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PTPTSSR": {
+              "description": "Ethernet PTP time stamp status\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TSSO": {
+                    "description": "TSSO",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TSTTR": {
+                    "description": "TSTTR",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PTPPPSCR": {
+              "description": "Ethernet PTP PPS control\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TSSO": {
+                    "description": "TSSO",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TSTTR": {
+                    "description": "TSTTR",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIM11": {
+        "description": "General-purpose-timers",
+        "children": {
+          "registers": {
+            "CR1": {
+              "description": "control register 1",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKD": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARPE": {
+                    "description": "Auto-reload preload enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "URS": {
+                    "description": "Update request source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIER": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1IE": {
+                    "description": "Capture/Compare 1 interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "status register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1OF": {
+                    "description": "Capture/Compare 1 overcapture\n              flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CC1IF": {
+                    "description": "Capture/compare 1 interrupt\n              flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EGR": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CC1G": {
+                    "description": "Capture/compare 1\n              generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCMR1_Output": {
+              "description": "capture/compare mode register 1 (output\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OC1M": {
+                    "description": "Output Compare 1 mode",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "OC1PE": {
+                    "description": "Output Compare 1 preload\n              enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OC1FE": {
+                    "description": "Output Compare 1 fast\n              enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCMR1_Input": {
+              "description": "capture/compare mode register 1 (input\n          mode)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IC1F": {
+                    "description": "Input capture 1 filter",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ICPCS": {
+                    "description": "Input capture 1 prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CC1S": {
+                    "description": "Capture/Compare 1\n              selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CCER": {
+              "description": "capture/compare enable\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CC1NP": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CC1P": {
+                    "description": "Capture/Compare 1 output\n              Polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CC1E": {
+                    "description": "Capture/Compare 1 output\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ARR": {
+              "description": "auto-reload register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARR": {
+                    "description": "Auto-reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR1": {
+              "description": "capture/compare register 1",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCR1": {
+                    "description": "Capture/Compare 1 value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OR": {
+              "description": "option register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RMP": {
+                    "description": "Input 1 remapping\n              capability",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  },
+  "devices": {
+    "STM32F429": {
+      "arch": "cortex_m4",
+      "description": "STM32F429",
+      "properties": {
+        "cpu.nvic_prio_bits": "3",
+        "cpu.mpu": "false",
+        "cpu.fpu": "false",
+        "cpu.revision": "r1p0",
+        "cpu.vendor_systick_config": "false",
+        "cpu.endian": "little",
+        "cpu.name": "CM4"
+      },
+      "children": {
+        "interrupts": {
+          "MemManageFault": {
+            "index": -12
+          },
+          "BusFault": {
+            "index": -11
+          },
+          "UsageFault": {
+            "index": -10
+          },
+          "DebugMonitor": {
+            "index": -4
+          },
+          "NMI": {
+            "index": -14
+          },
+          "HardFault": {
+            "index": -13
+          },
+          "SVCall": {
+            "index": -5
+          },
+          "PendSV": {
+            "index": -2
+          },
+          "SysTick": {
+            "index": -1
+          },
+          "FPU": {
+            "index": 81,
+            "description": "Floating point unit interrupt"
+          },
+          "HASH_RNG": {
+            "index": 80,
+            "description": "Hash and Rng global interrupt"
+          },
+          "CRYP": {
+            "index": 79,
+            "description": "CRYP crypto global interrupt"
+          },
+          "DCMI": {
+            "index": 78,
+            "description": "DCMI global interrupt"
+          },
+          "FMC": {
+            "index": 48,
+            "description": "FMC global interrupt"
+          },
+          "DMA2_Stream0": {
+            "index": 56,
+            "description": "DMA2 Stream0 global interrupt"
+          },
+          "DMA1_Stream0": {
+            "index": 11,
+            "description": "DMA1 Stream0 global interrupt"
+          },
+          "RCC": {
+            "index": 5,
+            "description": "RCC global interrupt"
+          },
+          "SPI1": {
+            "index": 35,
+            "description": "SPI1 global interrupt"
+          },
+          "SPI2": {
+            "index": 36,
+            "description": "SPI2 global interrupt"
+          },
+          "SPI3": {
+            "index": 51,
+            "description": "SPI3 global interrupt"
+          },
+          "SPI4": {
+            "index": 84,
+            "description": "SPI 4 global interrupt"
+          },
+          "SPI5": {
+            "index": 85,
+            "description": "SPI 5 global interrupt"
+          },
+          "SPI6": {
+            "index": 86,
+            "description": "SPI 6 global interrupt"
+          },
+          "SDIO": {
+            "index": 49,
+            "description": "SDIO global interrupt"
+          },
+          "ADC": {
+            "index": 18,
+            "description": "ADC2 global interrupts"
+          },
+          "USART6": {
+            "index": 71,
+            "description": "USART6 global interrupt"
+          },
+          "USART1": {
+            "index": 37,
+            "description": "USART1 global interrupt"
+          },
+          "USART2": {
+            "index": 38,
+            "description": "USART2 global interrupt"
+          },
+          "USART3": {
+            "index": 39,
+            "description": "USART3 global interrupt"
+          },
+          "UART7": {
+            "index": 82,
+            "description": "UART 7 global interrupt"
+          },
+          "UART8": {
+            "index": 83,
+            "description": "UART 8 global interrupt"
+          },
+          "TIM6_DAC": {
+            "index": 54,
+            "description": "TIM6 global interrupt, DAC1 and DAC2 underrun\n        error interrupt"
+          },
+          "PVD": {
+            "index": 1,
+            "description": "PVD through EXTI line detection\n        interrupt"
+          },
+          "WWDG": {
+            "index": 0,
+            "description": "Window Watchdog interrupt"
+          },
+          "RTC_WKUP": {
+            "index": 3,
+            "description": "RTC Wakeup interrupt through the EXTI\n        line"
+          },
+          "UART4": {
+            "index": 52,
+            "description": "UART4 global interrupt"
+          },
+          "UART5": {
+            "index": 53,
+            "description": "UART5 global interrupt"
+          },
+          "TIM1_BRK_TIM9": {
+            "index": 24,
+            "description": "TIM1 Break interrupt and TIM9 global\n        interrupt"
+          },
+          "TIM8_BRK_TIM12": {
+            "index": 43,
+            "description": "TIM8 Break interrupt and TIM12 global\n        interrupt"
+          },
+          "TIM2": {
+            "index": 28,
+            "description": "TIM2 global interrupt"
+          },
+          "TIM3": {
+            "index": 29,
+            "description": "TIM3 global interrupt"
+          },
+          "TIM4": {
+            "index": 30,
+            "description": "TIM4 global interrupt"
+          },
+          "TIM5": {
+            "index": 50,
+            "description": "TIM5 global interrupt"
+          },
+          "TIM8_UP_TIM13": {
+            "index": 44,
+            "description": "TIM8 Update interrupt and TIM13 global\n        interrupt"
+          },
+          "TIM8_TRG_COM_TIM14": {
+            "index": 45,
+            "description": "TIM8 Trigger and Commutation interrupts and\n        TIM14 global interrupt"
+          },
+          "TIM7": {
+            "index": 55,
+            "description": "TIM7 global interrupt"
+          },
+          "ETH": {
+            "index": 61,
+            "description": "Ethernet global interrupt"
+          },
+          "OTG_FS_WKUP": {
+            "index": 42,
+            "description": "USB On-The-Go FS Wakeup through EXTI line\n        interrupt"
+          },
+          "CAN1_TX": {
+            "index": 19,
+            "description": "CAN1 TX interrupts"
+          },
+          "CAN2_TX": {
+            "index": 63,
+            "description": "CAN2 TX interrupts"
+          },
+          "FLASH": {
+            "index": 4,
+            "description": "Flash global interrupt"
+          },
+          "TAMP_STAMP": {
+            "index": 2,
+            "description": "Tamper and TimeStamp interrupts through the\n        EXTI line"
+          },
+          "OTG_HS_EP1_OUT": {
+            "index": 74,
+            "description": "USB On The Go HS End Point 1 Out global\n        interrupt"
+          },
+          "LCD_TFT": {
+            "index": 88,
+            "description": "LTDC global interrupt"
+          },
+          "SAI1": {
+            "index": 87,
+            "description": "SAI1 global interrupt"
+          },
+          "DMA2D": {
+            "index": 90,
+            "description": "DMA2D global interrupt"
+          },
+          "I2C3_EV": {
+            "index": 72,
+            "description": "I2C3 event interrupt"
+          },
+          "I2C2_EV": {
+            "index": 33,
+            "description": "I2C2 event interrupt"
+          },
+          "I2C1_EV": {
+            "index": 31,
+            "description": "I2C1 event interrupt"
+          }
+        },
+        "peripheral_instances": {
+          "RNG": {
+            "description": "Random number generator",
+            "offset": 1342572544,
+            "type": "types.peripherals.RNG"
+          },
+          "HASH": {
+            "description": "Hash processor",
+            "offset": 1342571520,
+            "type": "types.peripherals.HASH"
+          },
+          "CRYP": {
+            "description": "Cryptographic processor",
+            "offset": 1342570496,
+            "type": "types.peripherals.CRYP"
+          },
+          "DCMI": {
+            "description": "Digital camera interface",
+            "offset": 1342504960,
+            "type": "types.peripherals.DCMI"
+          },
+          "FMC": {
+            "description": "Flexible memory controller",
+            "offset": 2684354560,
+            "type": "types.peripherals.FMC"
+          },
+          "DBG": {
+            "description": "Debug support",
+            "offset": 3758366720,
+            "type": "types.peripherals.DBG"
+          },
+          "DMA2": {
+            "description": "DMA controller",
+            "offset": 1073898496,
+            "type": "types.peripherals.DMA2"
+          },
+          "DMA1": {
+            "offset": 1073897472,
+            "type": "types.peripherals.DMA2"
+          },
+          "RCC": {
+            "description": "Reset and clock control",
+            "offset": 1073887232,
+            "type": "types.peripherals.RCC"
+          },
+          "GPIOK": {
+            "description": "General-purpose I/Os",
+            "offset": 1073883136,
+            "type": "types.peripherals.GPIOK"
+          },
+          "GPIOJ": {
+            "offset": 1073882112,
+            "type": "types.peripherals.GPIOK"
+          },
+          "GPIOI": {
+            "offset": 1073881088,
+            "type": "types.peripherals.GPIOK"
+          },
+          "GPIOH": {
+            "offset": 1073880064,
+            "type": "types.peripherals.GPIOK"
+          },
+          "GPIOG": {
+            "offset": 1073879040,
+            "type": "types.peripherals.GPIOK"
+          },
+          "GPIOF": {
+            "offset": 1073878016,
+            "type": "types.peripherals.GPIOK"
+          },
+          "GPIOE": {
+            "offset": 1073876992,
+            "type": "types.peripherals.GPIOK"
+          },
+          "GPIOD": {
+            "offset": 1073875968,
+            "type": "types.peripherals.GPIOK"
+          },
+          "GPIOC": {
+            "offset": 1073874944,
+            "type": "types.peripherals.GPIOK"
+          },
+          "GPIOB": {
+            "description": "General-purpose I/Os",
+            "offset": 1073873920,
+            "type": "types.peripherals.GPIOB"
+          },
+          "GPIOA": {
+            "description": "General-purpose I/Os",
+            "offset": 1073872896,
+            "type": "types.peripherals.GPIOA"
+          },
+          "SYSCFG": {
+            "description": "System configuration controller",
+            "offset": 1073821696,
+            "type": "types.peripherals.SYSCFG"
+          },
+          "SPI1": {
+            "description": "Serial peripheral interface",
+            "offset": 1073819648,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI2": {
+            "offset": 1073756160,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI3": {
+            "offset": 1073757184,
+            "type": "types.peripherals.SPI1"
+          },
+          "I2S2ext": {
+            "offset": 1073755136,
+            "type": "types.peripherals.SPI1"
+          },
+          "I2S3ext": {
+            "offset": 1073758208,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI4": {
+            "offset": 1073820672,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI5": {
+            "offset": 1073827840,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI6": {
+            "offset": 1073828864,
+            "type": "types.peripherals.SPI1"
+          },
+          "SDIO": {
+            "description": "Secure digital input/output\n      interface",
+            "offset": 1073818624,
+            "type": "types.peripherals.SDIO"
+          },
+          "ADC1": {
+            "description": "Analog-to-digital converter",
+            "offset": 1073815552,
+            "type": "types.peripherals.ADC1"
+          },
+          "ADC2": {
+            "offset": 1073815808,
+            "type": "types.peripherals.ADC1"
+          },
+          "ADC3": {
+            "offset": 1073816064,
+            "type": "types.peripherals.ADC1"
+          },
+          "USART6": {
+            "description": "Universal synchronous asynchronous receiver\n      transmitter",
+            "offset": 1073812480,
+            "type": "types.peripherals.USART6"
+          },
+          "USART1": {
+            "offset": 1073811456,
+            "type": "types.peripherals.USART6"
+          },
+          "USART2": {
+            "offset": 1073759232,
+            "type": "types.peripherals.USART6"
+          },
+          "USART3": {
+            "offset": 1073760256,
+            "type": "types.peripherals.USART6"
+          },
+          "UART7": {
+            "offset": 1073772544,
+            "type": "types.peripherals.USART6"
+          },
+          "UART8": {
+            "offset": 1073773568,
+            "type": "types.peripherals.USART6"
+          },
+          "DAC": {
+            "description": "Digital-to-analog converter",
+            "offset": 1073771520,
+            "type": "types.peripherals.DAC"
+          },
+          "PWR": {
+            "description": "Power control",
+            "offset": 1073770496,
+            "type": "types.peripherals.PWR"
+          },
+          "IWDG": {
+            "description": "Independent watchdog",
+            "offset": 1073754112,
+            "type": "types.peripherals.IWDG"
+          },
+          "WWDG": {
+            "description": "Window watchdog",
+            "offset": 1073753088,
+            "type": "types.peripherals.WWDG"
+          },
+          "RTC": {
+            "description": "Real-time clock",
+            "offset": 1073752064,
+            "type": "types.peripherals.RTC"
+          },
+          "UART4": {
+            "description": "Universal synchronous asynchronous receiver\n      transmitter",
+            "offset": 1073761280,
+            "type": "types.peripherals.UART4"
+          },
+          "UART5": {
+            "offset": 1073762304,
+            "type": "types.peripherals.UART4"
+          },
+          "C_ADC": {
+            "description": "Common ADC registers",
+            "offset": 1073816320,
+            "type": "types.peripherals.C_ADC"
+          },
+          "TIM1": {
+            "description": "Advanced-timers",
+            "offset": 1073807360,
+            "type": "types.peripherals.TIM1"
+          },
+          "TIM8": {
+            "offset": 1073808384,
+            "type": "types.peripherals.TIM1"
+          },
+          "TIM2": {
+            "description": "General purpose timers",
+            "offset": 1073741824,
+            "type": "types.peripherals.TIM2"
+          },
+          "TIM3": {
+            "description": "General purpose timers",
+            "offset": 1073742848,
+            "type": "types.peripherals.TIM3"
+          },
+          "TIM4": {
+            "offset": 1073743872,
+            "type": "types.peripherals.TIM3"
+          },
+          "TIM5": {
+            "description": "General-purpose-timers",
+            "offset": 1073744896,
+            "type": "types.peripherals.TIM5"
+          },
+          "TIM9": {
+            "description": "General purpose timers",
+            "offset": 1073823744,
+            "type": "types.peripherals.TIM9"
+          },
+          "TIM12": {
+            "offset": 1073747968,
+            "type": "types.peripherals.TIM9"
+          },
+          "TIM10": {
+            "description": "General-purpose-timers",
+            "offset": 1073824768,
+            "type": "types.peripherals.TIM10"
+          },
+          "TIM13": {
+            "offset": 1073748992,
+            "type": "types.peripherals.TIM10"
+          },
+          "TIM14": {
+            "offset": 1073750016,
+            "type": "types.peripherals.TIM10"
+          },
+          "TIM11": {
+            "description": "General-purpose-timers",
+            "offset": 1073825792,
+            "type": "types.peripherals.TIM11"
+          },
+          "TIM6": {
+            "description": "Basic timers",
+            "offset": 1073745920,
+            "type": "types.peripherals.TIM6"
+          },
+          "TIM7": {
+            "offset": 1073746944,
+            "type": "types.peripherals.TIM6"
+          },
+          "Ethernet_MAC": {
+            "description": "Ethernet: media access control\n      (MAC)",
+            "offset": 1073905664,
+            "type": "types.peripherals.Ethernet_MAC"
+          },
+          "Ethernet_MMC": {
+            "description": "Ethernet: MAC management counters",
+            "offset": 1073905920,
+            "type": "types.peripherals.Ethernet_MMC"
+          },
+          "Ethernet_PTP": {
+            "description": "Ethernet: Precision time protocol",
+            "offset": 1073907456,
+            "type": "types.peripherals.Ethernet_PTP"
+          },
+          "Ethernet_DMA": {
+            "description": "Ethernet: DMA controller operation",
+            "offset": 1073909760,
+            "type": "types.peripherals.Ethernet_DMA"
+          },
+          "CRC": {
+            "description": "Cryptographic processor",
+            "offset": 1073885184,
+            "type": "types.peripherals.CRC"
+          },
+          "OTG_FS_GLOBAL": {
+            "description": "USB on the go full speed",
+            "offset": 1342177280,
+            "type": "types.peripherals.OTG_FS_GLOBAL"
+          },
+          "OTG_FS_HOST": {
+            "description": "USB on the go full speed",
+            "offset": 1342178304,
+            "type": "types.peripherals.OTG_FS_HOST"
+          },
+          "OTG_FS_DEVICE": {
+            "description": "USB on the go full speed",
+            "offset": 1342179328,
+            "type": "types.peripherals.OTG_FS_DEVICE"
+          },
+          "OTG_FS_PWRCLK": {
+            "description": "USB on the go full speed",
+            "offset": 1342180864,
+            "type": "types.peripherals.OTG_FS_PWRCLK"
+          },
+          "CAN1": {
+            "description": "Controller area network",
+            "offset": 1073767424,
+            "type": "types.peripherals.CAN1"
+          },
+          "CAN2": {
+            "offset": 1073768448,
+            "type": "types.peripherals.CAN1"
+          },
+          "NVIC": {
+            "description": "Nested Vectored Interrupt\n      Controller",
+            "offset": 3758153984,
+            "type": "types.peripherals.NVIC"
+          },
+          "FLASH": {
+            "description": "FLASH",
+            "offset": 1073888256,
+            "type": "types.peripherals.FLASH"
+          },
+          "EXTI": {
+            "description": "External interrupt/event\n      controller",
+            "offset": 1073822720,
+            "type": "types.peripherals.EXTI"
+          },
+          "OTG_HS_GLOBAL": {
+            "description": "USB on the go high speed",
+            "offset": 1074003968,
+            "type": "types.peripherals.OTG_HS_GLOBAL"
+          },
+          "OTG_HS_HOST": {
+            "description": "USB on the go high speed",
+            "offset": 1074004992,
+            "type": "types.peripherals.OTG_HS_HOST"
+          },
+          "OTG_HS_DEVICE": {
+            "description": "USB on the go high speed",
+            "offset": 1074006016,
+            "type": "types.peripherals.OTG_HS_DEVICE"
+          },
+          "OTG_HS_PWRCLK": {
+            "description": "USB on the go high speed",
+            "offset": 1074007552,
+            "type": "types.peripherals.OTG_HS_PWRCLK"
+          },
+          "LTDC": {
+            "description": "LCD-TFT Controller",
+            "offset": 1073833984,
+            "type": "types.peripherals.LTDC"
+          },
+          "SAI": {
+            "description": "Serial audio interface",
+            "offset": 1073829888,
+            "type": "types.peripherals.SAI"
+          },
+          "DMA2D": {
+            "description": "DMA2D controller",
+            "offset": 1073917952,
+            "type": "types.peripherals.DMA2D"
+          },
+          "I2C3": {
+            "description": "Inter-integrated circuit",
+            "offset": 1073765376,
+            "type": "types.peripherals.I2C3"
+          },
+          "I2C2": {
+            "offset": 1073764352,
+            "type": "types.peripherals.I2C3"
+          },
+          "I2C1": {
+            "offset": 1073763328,
+            "type": "types.peripherals.I2C3"
+          },
+          "FPU": {
+            "description": "Floting point unit",
+            "offset": 3758157620,
+            "type": "types.peripherals.FPU"
+          },
+          "MPU": {
+            "description": "Memory protection unit",
+            "offset": 3758157200,
+            "type": "types.peripherals.MPU"
+          },
+          "STK": {
+            "description": "SysTick timer",
+            "offset": 3758153744,
+            "type": "types.peripherals.STK"
+          },
+          "SCB": {
+            "description": "System control block",
+            "offset": 3758157056,
+            "type": "types.peripherals.SCB"
+          },
+          "NVIC_STIR": {
+            "description": "Nested vectored interrupt\n      controller",
+            "offset": 3758157568,
+            "type": "types.peripherals.NVIC_STIR"
+          },
+          "FPU_CPACR": {
+            "description": "Floating point unit CPACR",
+            "offset": 3758157192,
+            "type": "types.peripherals.FPU_CPACR"
+          },
+          "SCB_ACTRL": {
+            "description": "System control block ACTLR",
+            "offset": 3758153736,
+            "type": "types.peripherals.SCB_ACTRL"
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/chips/STM32F429.zig b/src/chips/STM32F429.zig
new file mode 100644
index 000000000..73b943659
--- /dev/null
+++ b/src/chips/STM32F429.zig
@@ -0,0 +1,20419 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    ///  STM32F429
+    pub const STM32F429 = struct {
+        pub const properties = struct {
+            pub const @"cpu.nvic_prio_bits" = "3";
+            pub const @"cpu.mpu" = "false";
+            pub const @"cpu.fpu" = "false";
+            pub const @"cpu.revision" = "r1p0";
+            pub const @"cpu.vendor_systick_config" = "false";
+            pub const @"cpu.endian" = "little";
+            pub const @"cpu.name" = "CM4";
+        };
+
+        pub const VectorTable = extern struct {
+            const Handler = micro.interrupt.Handler;
+            const unhandled = micro.interrupt.unhandled;
+
+            initial_stack_pointer: u32,
+            Reset: Handler = unhandled,
+            NMI: Handler = unhandled,
+            HardFault: Handler = unhandled,
+            MemManageFault: Handler = unhandled,
+            BusFault: Handler = unhandled,
+            UsageFault: Handler = unhandled,
+            reserved5: [4]u32 = undefined,
+            SVCall: Handler = unhandled,
+            DebugMonitor: Handler = unhandled,
+            reserved11: [1]u32 = undefined,
+            PendSV: Handler = unhandled,
+            SysTick: Handler = unhandled,
+            ///  Window Watchdog interrupt
+            WWDG: Handler = unhandled,
+            ///  PVD through EXTI line detection interrupt
+            PVD: Handler = unhandled,
+            ///  Tamper and TimeStamp interrupts through the EXTI line
+            TAMP_STAMP: Handler = unhandled,
+            ///  RTC Wakeup interrupt through the EXTI line
+            RTC_WKUP: Handler = unhandled,
+            ///  Flash global interrupt
+            FLASH: Handler = unhandled,
+            ///  RCC global interrupt
+            RCC: Handler = unhandled,
+            reserved20: [5]u32 = undefined,
+            ///  DMA1 Stream0 global interrupt
+            DMA1_Stream0: Handler = unhandled,
+            reserved26: [6]u32 = undefined,
+            ///  ADC2 global interrupts
+            ADC: Handler = unhandled,
+            ///  CAN1 TX interrupts
+            CAN1_TX: Handler = unhandled,
+            reserved34: [4]u32 = undefined,
+            ///  TIM1 Break interrupt and TIM9 global interrupt
+            TIM1_BRK_TIM9: Handler = unhandled,
+            reserved39: [3]u32 = undefined,
+            ///  TIM2 global interrupt
+            TIM2: Handler = unhandled,
+            ///  TIM3 global interrupt
+            TIM3: Handler = unhandled,
+            ///  TIM4 global interrupt
+            TIM4: Handler = unhandled,
+            ///  I2C1 event interrupt
+            I2C1_EV: Handler = unhandled,
+            reserved46: [1]u32 = undefined,
+            ///  I2C2 event interrupt
+            I2C2_EV: Handler = unhandled,
+            reserved48: [1]u32 = undefined,
+            ///  SPI1 global interrupt
+            SPI1: Handler = unhandled,
+            ///  SPI2 global interrupt
+            SPI2: Handler = unhandled,
+            ///  USART1 global interrupt
+            USART1: Handler = unhandled,
+            ///  USART2 global interrupt
+            USART2: Handler = unhandled,
+            ///  USART3 global interrupt
+            USART3: Handler = unhandled,
+            reserved54: [2]u32 = undefined,
+            ///  USB On-The-Go FS Wakeup through EXTI line interrupt
+            OTG_FS_WKUP: Handler = unhandled,
+            ///  TIM8 Break interrupt and TIM12 global interrupt
+            TIM8_BRK_TIM12: Handler = unhandled,
+            ///  TIM8 Update interrupt and TIM13 global interrupt
+            TIM8_UP_TIM13: Handler = unhandled,
+            ///  TIM8 Trigger and Commutation interrupts and TIM14 global interrupt
+            TIM8_TRG_COM_TIM14: Handler = unhandled,
+            reserved60: [2]u32 = undefined,
+            ///  FMC global interrupt
+            FMC: Handler = unhandled,
+            ///  SDIO global interrupt
+            SDIO: Handler = unhandled,
+            ///  TIM5 global interrupt
+            TIM5: Handler = unhandled,
+            ///  SPI3 global interrupt
+            SPI3: Handler = unhandled,
+            ///  UART4 global interrupt
+            UART4: Handler = unhandled,
+            ///  UART5 global interrupt
+            UART5: Handler = unhandled,
+            ///  TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt
+            TIM6_DAC: Handler = unhandled,
+            ///  TIM7 global interrupt
+            TIM7: Handler = unhandled,
+            ///  DMA2 Stream0 global interrupt
+            DMA2_Stream0: Handler = unhandled,
+            reserved71: [4]u32 = undefined,
+            ///  Ethernet global interrupt
+            ETH: Handler = unhandled,
+            reserved76: [1]u32 = undefined,
+            ///  CAN2 TX interrupts
+            CAN2_TX: Handler = unhandled,
+            reserved78: [7]u32 = undefined,
+            ///  USART6 global interrupt
+            USART6: Handler = unhandled,
+            ///  I2C3 event interrupt
+            I2C3_EV: Handler = unhandled,
+            reserved87: [1]u32 = undefined,
+            ///  USB On The Go HS End Point 1 Out global interrupt
+            OTG_HS_EP1_OUT: Handler = unhandled,
+            reserved89: [3]u32 = undefined,
+            ///  DCMI global interrupt
+            DCMI: Handler = unhandled,
+            ///  CRYP crypto global interrupt
+            CRYP: Handler = unhandled,
+            ///  Hash and Rng global interrupt
+            HASH_RNG: Handler = unhandled,
+            ///  FPU interrupt
+            FPU: Handler = unhandled,
+            ///  UART 7 global interrupt
+            UART7: Handler = unhandled,
+            ///  UART 8 global interrupt
+            UART8: Handler = unhandled,
+            ///  SPI 4 global interrupt
+            SPI4: Handler = unhandled,
+            ///  SPI 5 global interrupt
+            SPI5: Handler = unhandled,
+            ///  SPI 6 global interrupt
+            SPI6: Handler = unhandled,
+            ///  SAI1 global interrupt
+            SAI1: Handler = unhandled,
+            ///  LTDC global interrupt
+            LCD_TFT: Handler = unhandled,
+            reserved103: [1]u32 = undefined,
+            ///  DMA2D global interrupt
+            DMA2D: Handler = unhandled,
+        };
+
+        pub const peripherals = struct {
+            ///  General purpose timers
+            pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000);
+            ///  General purpose timers
+            pub const TIM3 = @ptrCast(*volatile types.TIM3, 0x40000400);
+            ///  General purpose timers
+            pub const TIM4 = @ptrCast(*volatile types.TIM3, 0x40000800);
+            ///  General-purpose-timers
+            pub const TIM5 = @ptrCast(*volatile types.TIM5, 0x40000c00);
+            ///  Basic timers
+            pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000);
+            ///  Basic timers
+            pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400);
+            ///  General purpose timers
+            pub const TIM12 = @ptrCast(*volatile types.TIM9, 0x40001800);
+            ///  General-purpose-timers
+            pub const TIM13 = @ptrCast(*volatile types.TIM10, 0x40001c00);
+            ///  General-purpose-timers
+            pub const TIM14 = @ptrCast(*volatile types.TIM10, 0x40002000);
+            ///  Real-time clock
+            pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800);
+            ///  Window watchdog
+            pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00);
+            ///  Independent watchdog
+            pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000);
+            ///  Serial peripheral interface
+            pub const I2S2ext = @ptrCast(*volatile types.SPI1, 0x40003400);
+            ///  Serial peripheral interface
+            pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800);
+            ///  Serial peripheral interface
+            pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00);
+            ///  Serial peripheral interface
+            pub const I2S3ext = @ptrCast(*volatile types.SPI1, 0x40004000);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART2 = @ptrCast(*volatile types.USART6, 0x40004400);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART3 = @ptrCast(*volatile types.USART6, 0x40004800);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const UART4 = @ptrCast(*volatile types.UART4, 0x40004c00);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const UART5 = @ptrCast(*volatile types.UART4, 0x40005000);
+            ///  Inter-integrated circuit
+            pub const I2C1 = @ptrCast(*volatile types.I2C3, 0x40005400);
+            ///  Inter-integrated circuit
+            pub const I2C2 = @ptrCast(*volatile types.I2C3, 0x40005800);
+            ///  Inter-integrated circuit
+            pub const I2C3 = @ptrCast(*volatile types.I2C3, 0x40005c00);
+            ///  Controller area network
+            pub const CAN1 = @ptrCast(*volatile types.CAN1, 0x40006400);
+            ///  Controller area network
+            pub const CAN2 = @ptrCast(*volatile types.CAN1, 0x40006800);
+            ///  Power control
+            pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000);
+            ///  Digital-to-analog converter
+            pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const UART7 = @ptrCast(*volatile types.USART6, 0x40007800);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const UART8 = @ptrCast(*volatile types.USART6, 0x40007c00);
+            ///  Advanced-timers
+            pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40010000);
+            ///  Advanced-timers
+            pub const TIM8 = @ptrCast(*volatile types.TIM1, 0x40010400);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART1 = @ptrCast(*volatile types.USART6, 0x40011000);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART6 = @ptrCast(*volatile types.USART6, 0x40011400);
+            ///  Analog-to-digital converter
+            pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x40012000);
+            ///  Analog-to-digital converter
+            pub const ADC2 = @ptrCast(*volatile types.ADC1, 0x40012100);
+            ///  Analog-to-digital converter
+            pub const ADC3 = @ptrCast(*volatile types.ADC1, 0x40012200);
+            ///  Common ADC registers
+            pub const C_ADC = @ptrCast(*volatile types.C_ADC, 0x40012300);
+            ///  Secure digital input/output interface
+            pub const SDIO = @ptrCast(*volatile types.SDIO, 0x40012c00);
+            ///  Serial peripheral interface
+            pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000);
+            ///  Serial peripheral interface
+            pub const SPI4 = @ptrCast(*volatile types.SPI1, 0x40013400);
+            ///  System configuration controller
+            pub const SYSCFG = @ptrCast(*volatile types.SYSCFG, 0x40013800);
+            ///  External interrupt/event controller
+            pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40013c00);
+            ///  General purpose timers
+            pub const TIM9 = @ptrCast(*volatile types.TIM9, 0x40014000);
+            ///  General-purpose-timers
+            pub const TIM10 = @ptrCast(*volatile types.TIM10, 0x40014400);
+            ///  General-purpose-timers
+            pub const TIM11 = @ptrCast(*volatile types.TIM11, 0x40014800);
+            ///  Serial peripheral interface
+            pub const SPI5 = @ptrCast(*volatile types.SPI1, 0x40015000);
+            ///  Serial peripheral interface
+            pub const SPI6 = @ptrCast(*volatile types.SPI1, 0x40015400);
+            ///  Serial audio interface
+            pub const SAI = @ptrCast(*volatile types.SAI, 0x40015800);
+            ///  LCD-TFT Controller
+            pub const LTDC = @ptrCast(*volatile types.LTDC, 0x40016800);
+            ///  General-purpose I/Os
+            pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x40020000);
+            ///  General-purpose I/Os
+            pub const GPIOB = @ptrCast(*volatile types.GPIOB, 0x40020400);
+            ///  General-purpose I/Os
+            pub const GPIOC = @ptrCast(*volatile types.GPIOK, 0x40020800);
+            ///  General-purpose I/Os
+            pub const GPIOD = @ptrCast(*volatile types.GPIOK, 0x40020c00);
+            ///  General-purpose I/Os
+            pub const GPIOE = @ptrCast(*volatile types.GPIOK, 0x40021000);
+            ///  General-purpose I/Os
+            pub const GPIOF = @ptrCast(*volatile types.GPIOK, 0x40021400);
+            ///  General-purpose I/Os
+            pub const GPIOG = @ptrCast(*volatile types.GPIOK, 0x40021800);
+            ///  General-purpose I/Os
+            pub const GPIOH = @ptrCast(*volatile types.GPIOK, 0x40021c00);
+            ///  General-purpose I/Os
+            pub const GPIOI = @ptrCast(*volatile types.GPIOK, 0x40022000);
+            ///  General-purpose I/Os
+            pub const GPIOJ = @ptrCast(*volatile types.GPIOK, 0x40022400);
+            ///  General-purpose I/Os
+            pub const GPIOK = @ptrCast(*volatile types.GPIOK, 0x40022800);
+            ///  Cryptographic processor
+            pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000);
+            ///  Reset and clock control
+            pub const RCC = @ptrCast(*volatile types.RCC, 0x40023800);
+            ///  FLASH
+            pub const FLASH = @ptrCast(*volatile types.FLASH, 0x40023c00);
+            ///  DMA controller
+            pub const DMA1 = @ptrCast(*volatile types.DMA2, 0x40026000);
+            ///  DMA controller
+            pub const DMA2 = @ptrCast(*volatile types.DMA2, 0x40026400);
+            ///  Ethernet: media access control (MAC)
+            pub const Ethernet_MAC = @ptrCast(*volatile types.Ethernet_MAC, 0x40028000);
+            ///  Ethernet: MAC management counters
+            pub const Ethernet_MMC = @ptrCast(*volatile types.Ethernet_MMC, 0x40028100);
+            ///  Ethernet: Precision time protocol
+            pub const Ethernet_PTP = @ptrCast(*volatile types.Ethernet_PTP, 0x40028700);
+            ///  Ethernet: DMA controller operation
+            pub const Ethernet_DMA = @ptrCast(*volatile types.Ethernet_DMA, 0x40029000);
+            ///  DMA2D controller
+            pub const DMA2D = @ptrCast(*volatile types.DMA2D, 0x4002b000);
+            ///  USB on the go high speed
+            pub const OTG_HS_GLOBAL = @ptrCast(*volatile types.OTG_HS_GLOBAL, 0x40040000);
+            ///  USB on the go high speed
+            pub const OTG_HS_HOST = @ptrCast(*volatile types.OTG_HS_HOST, 0x40040400);
+            ///  USB on the go high speed
+            pub const OTG_HS_DEVICE = @ptrCast(*volatile types.OTG_HS_DEVICE, 0x40040800);
+            ///  USB on the go high speed
+            pub const OTG_HS_PWRCLK = @ptrCast(*volatile types.OTG_HS_PWRCLK, 0x40040e00);
+            ///  USB on the go full speed
+            pub const OTG_FS_GLOBAL = @ptrCast(*volatile types.OTG_FS_GLOBAL, 0x50000000);
+            ///  USB on the go full speed
+            pub const OTG_FS_HOST = @ptrCast(*volatile types.OTG_FS_HOST, 0x50000400);
+            ///  USB on the go full speed
+            pub const OTG_FS_DEVICE = @ptrCast(*volatile types.OTG_FS_DEVICE, 0x50000800);
+            ///  USB on the go full speed
+            pub const OTG_FS_PWRCLK = @ptrCast(*volatile types.OTG_FS_PWRCLK, 0x50000e00);
+            ///  Digital camera interface
+            pub const DCMI = @ptrCast(*volatile types.DCMI, 0x50050000);
+            ///  Cryptographic processor
+            pub const CRYP = @ptrCast(*volatile types.CRYP, 0x50060000);
+            ///  Hash processor
+            pub const HASH = @ptrCast(*volatile types.HASH, 0x50060400);
+            ///  Random number generator
+            pub const RNG = @ptrCast(*volatile types.RNG, 0x50060800);
+            ///  Flexible memory controller
+            pub const FMC = @ptrCast(*volatile types.FMC, 0xa0000000);
+            ///  System control block ACTLR
+            pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008);
+            ///  SysTick timer
+            pub const STK = @ptrCast(*volatile types.STK, 0xe000e010);
+            ///  Nested Vectored Interrupt Controller
+            pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100);
+            ///  System control block
+            pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00);
+            ///  Floating point unit CPACR
+            pub const FPU_CPACR = @ptrCast(*volatile types.FPU_CPACR, 0xe000ed88);
+            ///  Memory protection unit
+            pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90);
+            ///  Nested vectored interrupt controller
+            pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00);
+            ///  Floting point unit
+            pub const FPU = @ptrCast(*volatile types.FPU, 0xe000ef34);
+            ///  Debug support
+            pub const DBG = @ptrCast(*volatile types.DBG, 0xe0042000);
+        };
+    };
+};
+
+pub const types = struct {
+    ///  Random number generator
+    pub const RNG = extern struct {
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Random number generator enable
+            RNGEN: u1,
+            ///  Interrupt enable
+            IE: u1,
+            padding: u28,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Data ready
+            DRDY: u1,
+            ///  Clock error current status
+            CECS: u1,
+            ///  Seed error current status
+            SECS: u1,
+            reserved5: u2,
+            ///  Clock error interrupt status
+            CEIS: u1,
+            ///  Seed error interrupt status
+            SEIS: u1,
+            padding: u25,
+        }),
+        ///  data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Random data
+            RNDATA: u32,
+        }),
+    };
+
+    ///  Hash processor
+    pub const HASH = extern struct {
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Initialize message digest calculation
+            INIT: u1,
+            ///  DMA enable
+            DMAE: u1,
+            ///  Data type selection
+            DATATYPE: u2,
+            ///  Mode selection
+            MODE: u1,
+            ///  Algorithm selection
+            ALGO0: u1,
+            ///  Number of words already pushed
+            NBW: u4,
+            ///  DIN not empty
+            DINNE: u1,
+            ///  Multiple DMA Transfers
+            MDMAT: u1,
+            reserved16: u2,
+            ///  Long key selection
+            LKEY: u1,
+            reserved18: u1,
+            ///  ALGO
+            ALGO1: u1,
+            padding: u13,
+        }),
+        ///  data input register
+        DIN: mmio.Mmio(packed struct(u32) {
+            ///  Data input
+            DATAIN: u32,
+        }),
+        ///  start register
+        STR: mmio.Mmio(packed struct(u32) {
+            ///  Number of valid bits in the last word of the message
+            NBLW: u5,
+            reserved8: u3,
+            ///  Digest calculation
+            DCAL: u1,
+            padding: u23,
+        }),
+        ///  digest registers
+        HR0: mmio.Mmio(packed struct(u32) {
+            ///  H0
+            H0: u32,
+        }),
+        ///  digest registers
+        HR1: mmio.Mmio(packed struct(u32) {
+            ///  H1
+            H1: u32,
+        }),
+        ///  digest registers
+        HR2: mmio.Mmio(packed struct(u32) {
+            ///  H2
+            H2: u32,
+        }),
+        ///  digest registers
+        HR3: mmio.Mmio(packed struct(u32) {
+            ///  H3
+            H3: u32,
+        }),
+        ///  digest registers
+        HR4: mmio.Mmio(packed struct(u32) {
+            ///  H4
+            H4: u32,
+        }),
+        ///  interrupt enable register
+        IMR: mmio.Mmio(packed struct(u32) {
+            ///  Data input interrupt enable
+            DINIE: u1,
+            ///  Digest calculation completion interrupt enable
+            DCIE: u1,
+            padding: u30,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Data input interrupt status
+            DINIS: u1,
+            ///  Digest calculation completion interrupt status
+            DCIS: u1,
+            ///  DMA Status
+            DMAS: u1,
+            ///  Busy bit
+            BUSY: u1,
+            padding: u28,
+        }),
+        reserved248: [208]u8,
+        ///  context swap registers
+        CSR0: mmio.Mmio(packed struct(u32) {
+            ///  CSR0
+            CSR0: u32,
+        }),
+        ///  context swap registers
+        CSR1: mmio.Mmio(packed struct(u32) {
+            ///  CSR1
+            CSR1: u32,
+        }),
+        ///  context swap registers
+        CSR2: mmio.Mmio(packed struct(u32) {
+            ///  CSR2
+            CSR2: u32,
+        }),
+        ///  context swap registers
+        CSR3: mmio.Mmio(packed struct(u32) {
+            ///  CSR3
+            CSR3: u32,
+        }),
+        ///  context swap registers
+        CSR4: mmio.Mmio(packed struct(u32) {
+            ///  CSR4
+            CSR4: u32,
+        }),
+        ///  context swap registers
+        CSR5: mmio.Mmio(packed struct(u32) {
+            ///  CSR5
+            CSR5: u32,
+        }),
+        ///  context swap registers
+        CSR6: mmio.Mmio(packed struct(u32) {
+            ///  CSR6
+            CSR6: u32,
+        }),
+        ///  context swap registers
+        CSR7: mmio.Mmio(packed struct(u32) {
+            ///  CSR7
+            CSR7: u32,
+        }),
+        ///  context swap registers
+        CSR8: mmio.Mmio(packed struct(u32) {
+            ///  CSR8
+            CSR8: u32,
+        }),
+        ///  context swap registers
+        CSR9: mmio.Mmio(packed struct(u32) {
+            ///  CSR9
+            CSR9: u32,
+        }),
+        ///  context swap registers
+        CSR10: mmio.Mmio(packed struct(u32) {
+            ///  CSR10
+            CSR10: u32,
+        }),
+        ///  context swap registers
+        CSR11: mmio.Mmio(packed struct(u32) {
+            ///  CSR11
+            CSR11: u32,
+        }),
+        ///  context swap registers
+        CSR12: mmio.Mmio(packed struct(u32) {
+            ///  CSR12
+            CSR12: u32,
+        }),
+        ///  context swap registers
+        CSR13: mmio.Mmio(packed struct(u32) {
+            ///  CSR13
+            CSR13: u32,
+        }),
+        ///  context swap registers
+        CSR14: mmio.Mmio(packed struct(u32) {
+            ///  CSR14
+            CSR14: u32,
+        }),
+        ///  context swap registers
+        CSR15: mmio.Mmio(packed struct(u32) {
+            ///  CSR15
+            CSR15: u32,
+        }),
+        ///  context swap registers
+        CSR16: mmio.Mmio(packed struct(u32) {
+            ///  CSR16
+            CSR16: u32,
+        }),
+        ///  context swap registers
+        CSR17: mmio.Mmio(packed struct(u32) {
+            ///  CSR17
+            CSR17: u32,
+        }),
+        ///  context swap registers
+        CSR18: mmio.Mmio(packed struct(u32) {
+            ///  CSR18
+            CSR18: u32,
+        }),
+        ///  context swap registers
+        CSR19: mmio.Mmio(packed struct(u32) {
+            ///  CSR19
+            CSR19: u32,
+        }),
+        ///  context swap registers
+        CSR20: mmio.Mmio(packed struct(u32) {
+            ///  CSR20
+            CSR20: u32,
+        }),
+        ///  context swap registers
+        CSR21: mmio.Mmio(packed struct(u32) {
+            ///  CSR21
+            CSR21: u32,
+        }),
+        ///  context swap registers
+        CSR22: mmio.Mmio(packed struct(u32) {
+            ///  CSR22
+            CSR22: u32,
+        }),
+        ///  context swap registers
+        CSR23: mmio.Mmio(packed struct(u32) {
+            ///  CSR23
+            CSR23: u32,
+        }),
+        ///  context swap registers
+        CSR24: mmio.Mmio(packed struct(u32) {
+            ///  CSR24
+            CSR24: u32,
+        }),
+        ///  context swap registers
+        CSR25: mmio.Mmio(packed struct(u32) {
+            ///  CSR25
+            CSR25: u32,
+        }),
+        ///  context swap registers
+        CSR26: mmio.Mmio(packed struct(u32) {
+            ///  CSR26
+            CSR26: u32,
+        }),
+        ///  context swap registers
+        CSR27: mmio.Mmio(packed struct(u32) {
+            ///  CSR27
+            CSR27: u32,
+        }),
+        ///  context swap registers
+        CSR28: mmio.Mmio(packed struct(u32) {
+            ///  CSR28
+            CSR28: u32,
+        }),
+        ///  context swap registers
+        CSR29: mmio.Mmio(packed struct(u32) {
+            ///  CSR29
+            CSR29: u32,
+        }),
+        ///  context swap registers
+        CSR30: mmio.Mmio(packed struct(u32) {
+            ///  CSR30
+            CSR30: u32,
+        }),
+        ///  context swap registers
+        CSR31: mmio.Mmio(packed struct(u32) {
+            ///  CSR31
+            CSR31: u32,
+        }),
+        ///  context swap registers
+        CSR32: mmio.Mmio(packed struct(u32) {
+            ///  CSR32
+            CSR32: u32,
+        }),
+        ///  context swap registers
+        CSR33: mmio.Mmio(packed struct(u32) {
+            ///  CSR33
+            CSR33: u32,
+        }),
+        ///  context swap registers
+        CSR34: mmio.Mmio(packed struct(u32) {
+            ///  CSR34
+            CSR34: u32,
+        }),
+        ///  context swap registers
+        CSR35: mmio.Mmio(packed struct(u32) {
+            ///  CSR35
+            CSR35: u32,
+        }),
+        ///  context swap registers
+        CSR36: mmio.Mmio(packed struct(u32) {
+            ///  CSR36
+            CSR36: u32,
+        }),
+        ///  context swap registers
+        CSR37: mmio.Mmio(packed struct(u32) {
+            ///  CSR37
+            CSR37: u32,
+        }),
+        ///  context swap registers
+        CSR38: mmio.Mmio(packed struct(u32) {
+            ///  CSR38
+            CSR38: u32,
+        }),
+        ///  context swap registers
+        CSR39: mmio.Mmio(packed struct(u32) {
+            ///  CSR39
+            CSR39: u32,
+        }),
+        ///  context swap registers
+        CSR40: mmio.Mmio(packed struct(u32) {
+            ///  CSR40
+            CSR40: u32,
+        }),
+        ///  context swap registers
+        CSR41: mmio.Mmio(packed struct(u32) {
+            ///  CSR41
+            CSR41: u32,
+        }),
+        ///  context swap registers
+        CSR42: mmio.Mmio(packed struct(u32) {
+            ///  CSR42
+            CSR42: u32,
+        }),
+        ///  context swap registers
+        CSR43: mmio.Mmio(packed struct(u32) {
+            ///  CSR43
+            CSR43: u32,
+        }),
+        ///  context swap registers
+        CSR44: mmio.Mmio(packed struct(u32) {
+            ///  CSR44
+            CSR44: u32,
+        }),
+        ///  context swap registers
+        CSR45: mmio.Mmio(packed struct(u32) {
+            ///  CSR45
+            CSR45: u32,
+        }),
+        ///  context swap registers
+        CSR46: mmio.Mmio(packed struct(u32) {
+            ///  CSR46
+            CSR46: u32,
+        }),
+        ///  context swap registers
+        CSR47: mmio.Mmio(packed struct(u32) {
+            ///  CSR47
+            CSR47: u32,
+        }),
+        ///  context swap registers
+        CSR48: mmio.Mmio(packed struct(u32) {
+            ///  CSR48
+            CSR48: u32,
+        }),
+        ///  context swap registers
+        CSR49: mmio.Mmio(packed struct(u32) {
+            ///  CSR49
+            CSR49: u32,
+        }),
+        ///  context swap registers
+        CSR50: mmio.Mmio(packed struct(u32) {
+            ///  CSR50
+            CSR50: u32,
+        }),
+        ///  context swap registers
+        CSR51: mmio.Mmio(packed struct(u32) {
+            ///  CSR51
+            CSR51: u32,
+        }),
+        ///  context swap registers
+        CSR52: mmio.Mmio(packed struct(u32) {
+            ///  CSR52
+            CSR52: u32,
+        }),
+        ///  context swap registers
+        CSR53: mmio.Mmio(packed struct(u32) {
+            ///  CSR53
+            CSR53: u32,
+        }),
+        reserved784: [320]u8,
+        ///  HASH digest register
+        HASH_HR0: mmio.Mmio(packed struct(u32) {
+            ///  H0
+            H0: u32,
+        }),
+        ///  read-only
+        HASH_HR1: mmio.Mmio(packed struct(u32) {
+            ///  H1
+            H1: u32,
+        }),
+        ///  read-only
+        HASH_HR2: mmio.Mmio(packed struct(u32) {
+            ///  H2
+            H2: u32,
+        }),
+        ///  read-only
+        HASH_HR3: mmio.Mmio(packed struct(u32) {
+            ///  H3
+            H3: u32,
+        }),
+        ///  read-only
+        HASH_HR4: mmio.Mmio(packed struct(u32) {
+            ///  H4
+            H4: u32,
+        }),
+        ///  read-only
+        HASH_HR5: mmio.Mmio(packed struct(u32) {
+            ///  H5
+            H5: u32,
+        }),
+        ///  read-only
+        HASH_HR6: mmio.Mmio(packed struct(u32) {
+            ///  H6
+            H6: u32,
+        }),
+        ///  read-only
+        HASH_HR7: mmio.Mmio(packed struct(u32) {
+            ///  H7
+            H7: u32,
+        }),
+    };
+
+    ///  Cryptographic processor
+    pub const CRYP = extern struct {
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Algorithm direction
+            ALGODIR: u1,
+            ///  Algorithm mode
+            ALGOMODE0: u3,
+            ///  Data type selection
+            DATATYPE: u2,
+            ///  Key size selection (AES mode only)
+            KEYSIZE: u2,
+            reserved14: u4,
+            ///  FIFO flush
+            FFLUSH: u1,
+            ///  Cryptographic processor enable
+            CRYPEN: u1,
+            ///  GCM_CCMPH
+            GCM_CCMPH: u2,
+            reserved19: u1,
+            ///  ALGOMODE
+            ALGOMODE3: u1,
+            padding: u12,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Input FIFO empty
+            IFEM: u1,
+            ///  Input FIFO not full
+            IFNF: u1,
+            ///  Output FIFO not empty
+            OFNE: u1,
+            ///  Output FIFO full
+            OFFU: u1,
+            ///  Busy bit
+            BUSY: u1,
+            padding: u27,
+        }),
+        ///  data input register
+        DIN: mmio.Mmio(packed struct(u32) {
+            ///  Data input
+            DATAIN: u32,
+        }),
+        ///  data output register
+        DOUT: mmio.Mmio(packed struct(u32) {
+            ///  Data output
+            DATAOUT: u32,
+        }),
+        ///  DMA control register
+        DMACR: mmio.Mmio(packed struct(u32) {
+            ///  DMA input enable
+            DIEN: u1,
+            ///  DMA output enable
+            DOEN: u1,
+            padding: u30,
+        }),
+        ///  interrupt mask set/clear register
+        IMSCR: mmio.Mmio(packed struct(u32) {
+            ///  Input FIFO service interrupt mask
+            INIM: u1,
+            ///  Output FIFO service interrupt mask
+            OUTIM: u1,
+            padding: u30,
+        }),
+        ///  raw interrupt status register
+        RISR: mmio.Mmio(packed struct(u32) {
+            ///  Input FIFO service raw interrupt status
+            INRIS: u1,
+            ///  Output FIFO service raw interrupt status
+            OUTRIS: u1,
+            padding: u30,
+        }),
+        ///  masked interrupt status register
+        MISR: mmio.Mmio(packed struct(u32) {
+            ///  Input FIFO service masked interrupt status
+            INMIS: u1,
+            ///  Output FIFO service masked interrupt status
+            OUTMIS: u1,
+            padding: u30,
+        }),
+        ///  key registers
+        K0LR: mmio.Mmio(packed struct(u32) {
+            ///  b224
+            b224: u1,
+            ///  b225
+            b225: u1,
+            ///  b226
+            b226: u1,
+            ///  b227
+            b227: u1,
+            ///  b228
+            b228: u1,
+            ///  b229
+            b229: u1,
+            ///  b230
+            b230: u1,
+            ///  b231
+            b231: u1,
+            ///  b232
+            b232: u1,
+            ///  b233
+            b233: u1,
+            ///  b234
+            b234: u1,
+            ///  b235
+            b235: u1,
+            ///  b236
+            b236: u1,
+            ///  b237
+            b237: u1,
+            ///  b238
+            b238: u1,
+            ///  b239
+            b239: u1,
+            ///  b240
+            b240: u1,
+            ///  b241
+            b241: u1,
+            ///  b242
+            b242: u1,
+            ///  b243
+            b243: u1,
+            ///  b244
+            b244: u1,
+            ///  b245
+            b245: u1,
+            ///  b246
+            b246: u1,
+            ///  b247
+            b247: u1,
+            ///  b248
+            b248: u1,
+            ///  b249
+            b249: u1,
+            ///  b250
+            b250: u1,
+            ///  b251
+            b251: u1,
+            ///  b252
+            b252: u1,
+            ///  b253
+            b253: u1,
+            ///  b254
+            b254: u1,
+            ///  b255
+            b255: u1,
+        }),
+        ///  key registers
+        K0RR: mmio.Mmio(packed struct(u32) {
+            ///  b192
+            b192: u1,
+            ///  b193
+            b193: u1,
+            ///  b194
+            b194: u1,
+            ///  b195
+            b195: u1,
+            ///  b196
+            b196: u1,
+            ///  b197
+            b197: u1,
+            ///  b198
+            b198: u1,
+            ///  b199
+            b199: u1,
+            ///  b200
+            b200: u1,
+            ///  b201
+            b201: u1,
+            ///  b202
+            b202: u1,
+            ///  b203
+            b203: u1,
+            ///  b204
+            b204: u1,
+            ///  b205
+            b205: u1,
+            ///  b206
+            b206: u1,
+            ///  b207
+            b207: u1,
+            ///  b208
+            b208: u1,
+            ///  b209
+            b209: u1,
+            ///  b210
+            b210: u1,
+            ///  b211
+            b211: u1,
+            ///  b212
+            b212: u1,
+            ///  b213
+            b213: u1,
+            ///  b214
+            b214: u1,
+            ///  b215
+            b215: u1,
+            ///  b216
+            b216: u1,
+            ///  b217
+            b217: u1,
+            ///  b218
+            b218: u1,
+            ///  b219
+            b219: u1,
+            ///  b220
+            b220: u1,
+            ///  b221
+            b221: u1,
+            ///  b222
+            b222: u1,
+            ///  b223
+            b223: u1,
+        }),
+        ///  key registers
+        K1LR: mmio.Mmio(packed struct(u32) {
+            ///  b160
+            b160: u1,
+            ///  b161
+            b161: u1,
+            ///  b162
+            b162: u1,
+            ///  b163
+            b163: u1,
+            ///  b164
+            b164: u1,
+            ///  b165
+            b165: u1,
+            ///  b166
+            b166: u1,
+            ///  b167
+            b167: u1,
+            ///  b168
+            b168: u1,
+            ///  b169
+            b169: u1,
+            ///  b170
+            b170: u1,
+            ///  b171
+            b171: u1,
+            ///  b172
+            b172: u1,
+            ///  b173
+            b173: u1,
+            ///  b174
+            b174: u1,
+            ///  b175
+            b175: u1,
+            ///  b176
+            b176: u1,
+            ///  b177
+            b177: u1,
+            ///  b178
+            b178: u1,
+            ///  b179
+            b179: u1,
+            ///  b180
+            b180: u1,
+            ///  b181
+            b181: u1,
+            ///  b182
+            b182: u1,
+            ///  b183
+            b183: u1,
+            ///  b184
+            b184: u1,
+            ///  b185
+            b185: u1,
+            ///  b186
+            b186: u1,
+            ///  b187
+            b187: u1,
+            ///  b188
+            b188: u1,
+            ///  b189
+            b189: u1,
+            ///  b190
+            b190: u1,
+            ///  b191
+            b191: u1,
+        }),
+        ///  key registers
+        K1RR: mmio.Mmio(packed struct(u32) {
+            ///  b128
+            b128: u1,
+            ///  b129
+            b129: u1,
+            ///  b130
+            b130: u1,
+            ///  b131
+            b131: u1,
+            ///  b132
+            b132: u1,
+            ///  b133
+            b133: u1,
+            ///  b134
+            b134: u1,
+            ///  b135
+            b135: u1,
+            ///  b136
+            b136: u1,
+            ///  b137
+            b137: u1,
+            ///  b138
+            b138: u1,
+            ///  b139
+            b139: u1,
+            ///  b140
+            b140: u1,
+            ///  b141
+            b141: u1,
+            ///  b142
+            b142: u1,
+            ///  b143
+            b143: u1,
+            ///  b144
+            b144: u1,
+            ///  b145
+            b145: u1,
+            ///  b146
+            b146: u1,
+            ///  b147
+            b147: u1,
+            ///  b148
+            b148: u1,
+            ///  b149
+            b149: u1,
+            ///  b150
+            b150: u1,
+            ///  b151
+            b151: u1,
+            ///  b152
+            b152: u1,
+            ///  b153
+            b153: u1,
+            ///  b154
+            b154: u1,
+            ///  b155
+            b155: u1,
+            ///  b156
+            b156: u1,
+            ///  b157
+            b157: u1,
+            ///  b158
+            b158: u1,
+            ///  b159
+            b159: u1,
+        }),
+        ///  key registers
+        K2LR: mmio.Mmio(packed struct(u32) {
+            ///  b96
+            b96: u1,
+            ///  b97
+            b97: u1,
+            ///  b98
+            b98: u1,
+            ///  b99
+            b99: u1,
+            ///  b100
+            b100: u1,
+            ///  b101
+            b101: u1,
+            ///  b102
+            b102: u1,
+            ///  b103
+            b103: u1,
+            ///  b104
+            b104: u1,
+            ///  b105
+            b105: u1,
+            ///  b106
+            b106: u1,
+            ///  b107
+            b107: u1,
+            ///  b108
+            b108: u1,
+            ///  b109
+            b109: u1,
+            ///  b110
+            b110: u1,
+            ///  b111
+            b111: u1,
+            ///  b112
+            b112: u1,
+            ///  b113
+            b113: u1,
+            ///  b114
+            b114: u1,
+            ///  b115
+            b115: u1,
+            ///  b116
+            b116: u1,
+            ///  b117
+            b117: u1,
+            ///  b118
+            b118: u1,
+            ///  b119
+            b119: u1,
+            ///  b120
+            b120: u1,
+            ///  b121
+            b121: u1,
+            ///  b122
+            b122: u1,
+            ///  b123
+            b123: u1,
+            ///  b124
+            b124: u1,
+            ///  b125
+            b125: u1,
+            ///  b126
+            b126: u1,
+            ///  b127
+            b127: u1,
+        }),
+        ///  key registers
+        K2RR: mmio.Mmio(packed struct(u32) {
+            ///  b64
+            b64: u1,
+            ///  b65
+            b65: u1,
+            ///  b66
+            b66: u1,
+            ///  b67
+            b67: u1,
+            ///  b68
+            b68: u1,
+            ///  b69
+            b69: u1,
+            ///  b70
+            b70: u1,
+            ///  b71
+            b71: u1,
+            ///  b72
+            b72: u1,
+            ///  b73
+            b73: u1,
+            ///  b74
+            b74: u1,
+            ///  b75
+            b75: u1,
+            ///  b76
+            b76: u1,
+            ///  b77
+            b77: u1,
+            ///  b78
+            b78: u1,
+            ///  b79
+            b79: u1,
+            ///  b80
+            b80: u1,
+            ///  b81
+            b81: u1,
+            ///  b82
+            b82: u1,
+            ///  b83
+            b83: u1,
+            ///  b84
+            b84: u1,
+            ///  b85
+            b85: u1,
+            ///  b86
+            b86: u1,
+            ///  b87
+            b87: u1,
+            ///  b88
+            b88: u1,
+            ///  b89
+            b89: u1,
+            ///  b90
+            b90: u1,
+            ///  b91
+            b91: u1,
+            ///  b92
+            b92: u1,
+            ///  b93
+            b93: u1,
+            ///  b94
+            b94: u1,
+            ///  b95
+            b95: u1,
+        }),
+        ///  key registers
+        K3LR: mmio.Mmio(packed struct(u32) {
+            ///  b32
+            b32: u1,
+            ///  b33
+            b33: u1,
+            ///  b34
+            b34: u1,
+            ///  b35
+            b35: u1,
+            ///  b36
+            b36: u1,
+            ///  b37
+            b37: u1,
+            ///  b38
+            b38: u1,
+            ///  b39
+            b39: u1,
+            ///  b40
+            b40: u1,
+            ///  b41
+            b41: u1,
+            ///  b42
+            b42: u1,
+            ///  b43
+            b43: u1,
+            ///  b44
+            b44: u1,
+            ///  b45
+            b45: u1,
+            ///  b46
+            b46: u1,
+            ///  b47
+            b47: u1,
+            ///  b48
+            b48: u1,
+            ///  b49
+            b49: u1,
+            ///  b50
+            b50: u1,
+            ///  b51
+            b51: u1,
+            ///  b52
+            b52: u1,
+            ///  b53
+            b53: u1,
+            ///  b54
+            b54: u1,
+            ///  b55
+            b55: u1,
+            ///  b56
+            b56: u1,
+            ///  b57
+            b57: u1,
+            ///  b58
+            b58: u1,
+            ///  b59
+            b59: u1,
+            ///  b60
+            b60: u1,
+            ///  b61
+            b61: u1,
+            ///  b62
+            b62: u1,
+            ///  b63
+            b63: u1,
+        }),
+        ///  key registers
+        K3RR: mmio.Mmio(packed struct(u32) {
+            ///  b0
+            b0: u1,
+            ///  b1
+            b1: u1,
+            ///  b2
+            b2: u1,
+            ///  b3
+            b3: u1,
+            ///  b4
+            b4: u1,
+            ///  b5
+            b5: u1,
+            ///  b6
+            b6: u1,
+            ///  b7
+            b7: u1,
+            ///  b8
+            b8: u1,
+            ///  b9
+            b9: u1,
+            ///  b10
+            b10: u1,
+            ///  b11
+            b11: u1,
+            ///  b12
+            b12: u1,
+            ///  b13
+            b13: u1,
+            ///  b14
+            b14: u1,
+            ///  b15
+            b15: u1,
+            ///  b16
+            b16: u1,
+            ///  b17
+            b17: u1,
+            ///  b18
+            b18: u1,
+            ///  b19
+            b19: u1,
+            ///  b20
+            b20: u1,
+            ///  b21
+            b21: u1,
+            ///  b22
+            b22: u1,
+            ///  b23
+            b23: u1,
+            ///  b24
+            b24: u1,
+            ///  b25
+            b25: u1,
+            ///  b26
+            b26: u1,
+            ///  b27
+            b27: u1,
+            ///  b28
+            b28: u1,
+            ///  b29
+            b29: u1,
+            ///  b30
+            b30: u1,
+            ///  b31
+            b31: u1,
+        }),
+        ///  initialization vector registers
+        IV0LR: mmio.Mmio(packed struct(u32) {
+            ///  IV31
+            IV31: u1,
+            ///  IV30
+            IV30: u1,
+            ///  IV29
+            IV29: u1,
+            ///  IV28
+            IV28: u1,
+            ///  IV27
+            IV27: u1,
+            ///  IV26
+            IV26: u1,
+            ///  IV25
+            IV25: u1,
+            ///  IV24
+            IV24: u1,
+            ///  IV23
+            IV23: u1,
+            ///  IV22
+            IV22: u1,
+            ///  IV21
+            IV21: u1,
+            ///  IV20
+            IV20: u1,
+            ///  IV19
+            IV19: u1,
+            ///  IV18
+            IV18: u1,
+            ///  IV17
+            IV17: u1,
+            ///  IV16
+            IV16: u1,
+            ///  IV15
+            IV15: u1,
+            ///  IV14
+            IV14: u1,
+            ///  IV13
+            IV13: u1,
+            ///  IV12
+            IV12: u1,
+            ///  IV11
+            IV11: u1,
+            ///  IV10
+            IV10: u1,
+            ///  IV9
+            IV9: u1,
+            ///  IV8
+            IV8: u1,
+            ///  IV7
+            IV7: u1,
+            ///  IV6
+            IV6: u1,
+            ///  IV5
+            IV5: u1,
+            ///  IV4
+            IV4: u1,
+            ///  IV3
+            IV3: u1,
+            ///  IV2
+            IV2: u1,
+            ///  IV1
+            IV1: u1,
+            ///  IV0
+            IV0: u1,
+        }),
+        ///  initialization vector registers
+        IV0RR: mmio.Mmio(packed struct(u32) {
+            ///  IV63
+            IV63: u1,
+            ///  IV62
+            IV62: u1,
+            ///  IV61
+            IV61: u1,
+            ///  IV60
+            IV60: u1,
+            ///  IV59
+            IV59: u1,
+            ///  IV58
+            IV58: u1,
+            ///  IV57
+            IV57: u1,
+            ///  IV56
+            IV56: u1,
+            ///  IV55
+            IV55: u1,
+            ///  IV54
+            IV54: u1,
+            ///  IV53
+            IV53: u1,
+            ///  IV52
+            IV52: u1,
+            ///  IV51
+            IV51: u1,
+            ///  IV50
+            IV50: u1,
+            ///  IV49
+            IV49: u1,
+            ///  IV48
+            IV48: u1,
+            ///  IV47
+            IV47: u1,
+            ///  IV46
+            IV46: u1,
+            ///  IV45
+            IV45: u1,
+            ///  IV44
+            IV44: u1,
+            ///  IV43
+            IV43: u1,
+            ///  IV42
+            IV42: u1,
+            ///  IV41
+            IV41: u1,
+            ///  IV40
+            IV40: u1,
+            ///  IV39
+            IV39: u1,
+            ///  IV38
+            IV38: u1,
+            ///  IV37
+            IV37: u1,
+            ///  IV36
+            IV36: u1,
+            ///  IV35
+            IV35: u1,
+            ///  IV34
+            IV34: u1,
+            ///  IV33
+            IV33: u1,
+            ///  IV32
+            IV32: u1,
+        }),
+        ///  initialization vector registers
+        IV1LR: mmio.Mmio(packed struct(u32) {
+            ///  IV95
+            IV95: u1,
+            ///  IV94
+            IV94: u1,
+            ///  IV93
+            IV93: u1,
+            ///  IV92
+            IV92: u1,
+            ///  IV91
+            IV91: u1,
+            ///  IV90
+            IV90: u1,
+            ///  IV89
+            IV89: u1,
+            ///  IV88
+            IV88: u1,
+            ///  IV87
+            IV87: u1,
+            ///  IV86
+            IV86: u1,
+            ///  IV85
+            IV85: u1,
+            ///  IV84
+            IV84: u1,
+            ///  IV83
+            IV83: u1,
+            ///  IV82
+            IV82: u1,
+            ///  IV81
+            IV81: u1,
+            ///  IV80
+            IV80: u1,
+            ///  IV79
+            IV79: u1,
+            ///  IV78
+            IV78: u1,
+            ///  IV77
+            IV77: u1,
+            ///  IV76
+            IV76: u1,
+            ///  IV75
+            IV75: u1,
+            ///  IV74
+            IV74: u1,
+            ///  IV73
+            IV73: u1,
+            ///  IV72
+            IV72: u1,
+            ///  IV71
+            IV71: u1,
+            ///  IV70
+            IV70: u1,
+            ///  IV69
+            IV69: u1,
+            ///  IV68
+            IV68: u1,
+            ///  IV67
+            IV67: u1,
+            ///  IV66
+            IV66: u1,
+            ///  IV65
+            IV65: u1,
+            ///  IV64
+            IV64: u1,
+        }),
+        ///  initialization vector registers
+        IV1RR: mmio.Mmio(packed struct(u32) {
+            ///  IV127
+            IV127: u1,
+            ///  IV126
+            IV126: u1,
+            ///  IV125
+            IV125: u1,
+            ///  IV124
+            IV124: u1,
+            ///  IV123
+            IV123: u1,
+            ///  IV122
+            IV122: u1,
+            ///  IV121
+            IV121: u1,
+            ///  IV120
+            IV120: u1,
+            ///  IV119
+            IV119: u1,
+            ///  IV118
+            IV118: u1,
+            ///  IV117
+            IV117: u1,
+            ///  IV116
+            IV116: u1,
+            ///  IV115
+            IV115: u1,
+            ///  IV114
+            IV114: u1,
+            ///  IV113
+            IV113: u1,
+            ///  IV112
+            IV112: u1,
+            ///  IV111
+            IV111: u1,
+            ///  IV110
+            IV110: u1,
+            ///  IV109
+            IV109: u1,
+            ///  IV108
+            IV108: u1,
+            ///  IV107
+            IV107: u1,
+            ///  IV106
+            IV106: u1,
+            ///  IV105
+            IV105: u1,
+            ///  IV104
+            IV104: u1,
+            ///  IV103
+            IV103: u1,
+            ///  IV102
+            IV102: u1,
+            ///  IV101
+            IV101: u1,
+            ///  IV100
+            IV100: u1,
+            ///  IV99
+            IV99: u1,
+            ///  IV98
+            IV98: u1,
+            ///  IV97
+            IV97: u1,
+            ///  IV96
+            IV96: u1,
+        }),
+        ///  context swap register
+        CSGCMCCM0R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM0R
+            CSGCMCCM0R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM1R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM1R
+            CSGCMCCM1R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM2R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM2R
+            CSGCMCCM2R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM3R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM3R
+            CSGCMCCM3R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM4R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM4R
+            CSGCMCCM4R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM5R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM5R
+            CSGCMCCM5R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM6R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM6R
+            CSGCMCCM6R: u32,
+        }),
+        ///  context swap register
+        CSGCMCCM7R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCMCCM7R
+            CSGCMCCM7R: u32,
+        }),
+        ///  context swap register
+        CSGCM0R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM0R
+            CSGCM0R: u32,
+        }),
+        ///  context swap register
+        CSGCM1R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM1R
+            CSGCM1R: u32,
+        }),
+        ///  context swap register
+        CSGCM2R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM2R
+            CSGCM2R: u32,
+        }),
+        ///  context swap register
+        CSGCM3R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM3R
+            CSGCM3R: u32,
+        }),
+        ///  context swap register
+        CSGCM4R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM4R
+            CSGCM4R: u32,
+        }),
+        ///  context swap register
+        CSGCM5R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM5R
+            CSGCM5R: u32,
+        }),
+        ///  context swap register
+        CSGCM6R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM6R
+            CSGCM6R: u32,
+        }),
+        ///  context swap register
+        CSGCM7R: mmio.Mmio(packed struct(u32) {
+            ///  CSGCM7R
+            CSGCM7R: u32,
+        }),
+    };
+
+    ///  Digital camera interface
+    pub const DCMI = extern struct {
+        ///  control register 1
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Capture enable
+            CAPTURE: u1,
+            ///  Capture mode
+            CM: u1,
+            ///  Crop feature
+            CROP: u1,
+            ///  JPEG format
+            JPEG: u1,
+            ///  Embedded synchronization select
+            ESS: u1,
+            ///  Pixel clock polarity
+            PCKPOL: u1,
+            ///  Horizontal synchronization polarity
+            HSPOL: u1,
+            ///  Vertical synchronization polarity
+            VSPOL: u1,
+            ///  Frame capture rate control
+            FCRC: u2,
+            ///  Extended data mode
+            EDM: u2,
+            reserved14: u2,
+            ///  DCMI enable
+            ENABLE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  HSYNC
+            HSYNC: u1,
+            ///  VSYNC
+            VSYNC: u1,
+            ///  FIFO not empty
+            FNE: u1,
+            padding: u29,
+        }),
+        ///  raw interrupt status register
+        RIS: mmio.Mmio(packed struct(u32) {
+            ///  Capture complete raw interrupt status
+            FRAME_RIS: u1,
+            ///  Overrun raw interrupt status
+            OVR_RIS: u1,
+            ///  Synchronization error raw interrupt status
+            ERR_RIS: u1,
+            ///  VSYNC raw interrupt status
+            VSYNC_RIS: u1,
+            ///  Line raw interrupt status
+            LINE_RIS: u1,
+            padding: u27,
+        }),
+        ///  interrupt enable register
+        IER: mmio.Mmio(packed struct(u32) {
+            ///  Capture complete interrupt enable
+            FRAME_IE: u1,
+            ///  Overrun interrupt enable
+            OVR_IE: u1,
+            ///  Synchronization error interrupt enable
+            ERR_IE: u1,
+            ///  VSYNC interrupt enable
+            VSYNC_IE: u1,
+            ///  Line interrupt enable
+            LINE_IE: u1,
+            padding: u27,
+        }),
+        ///  masked interrupt status register
+        MIS: mmio.Mmio(packed struct(u32) {
+            ///  Capture complete masked interrupt status
+            FRAME_MIS: u1,
+            ///  Overrun masked interrupt status
+            OVR_MIS: u1,
+            ///  Synchronization error masked interrupt status
+            ERR_MIS: u1,
+            ///  VSYNC masked interrupt status
+            VSYNC_MIS: u1,
+            ///  Line masked interrupt status
+            LINE_MIS: u1,
+            padding: u27,
+        }),
+        ///  interrupt clear register
+        ICR: mmio.Mmio(packed struct(u32) {
+            ///  Capture complete interrupt status clear
+            FRAME_ISC: u1,
+            ///  Overrun interrupt status clear
+            OVR_ISC: u1,
+            ///  Synchronization error interrupt status clear
+            ERR_ISC: u1,
+            ///  Vertical synch interrupt status clear
+            VSYNC_ISC: u1,
+            ///  line interrupt status clear
+            LINE_ISC: u1,
+            padding: u27,
+        }),
+        ///  embedded synchronization code register
+        ESCR: mmio.Mmio(packed struct(u32) {
+            ///  Frame start delimiter code
+            FSC: u8,
+            ///  Line start delimiter code
+            LSC: u8,
+            ///  Line end delimiter code
+            LEC: u8,
+            ///  Frame end delimiter code
+            FEC: u8,
+        }),
+        ///  embedded synchronization unmask register
+        ESUR: mmio.Mmio(packed struct(u32) {
+            ///  Frame start delimiter unmask
+            FSU: u8,
+            ///  Line start delimiter unmask
+            LSU: u8,
+            ///  Line end delimiter unmask
+            LEU: u8,
+            ///  Frame end delimiter unmask
+            FEU: u8,
+        }),
+        ///  crop window start
+        CWSTRT: mmio.Mmio(packed struct(u32) {
+            ///  Horizontal offset count
+            HOFFCNT: u14,
+            reserved16: u2,
+            ///  Vertical start line count
+            VST: u13,
+            padding: u3,
+        }),
+        ///  crop window size
+        CWSIZE: mmio.Mmio(packed struct(u32) {
+            ///  Capture count
+            CAPCNT: u14,
+            reserved16: u2,
+            ///  Vertical line count
+            VLINE: u14,
+            padding: u2,
+        }),
+        ///  data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data byte 0
+            Byte0: u8,
+            ///  Data byte 1
+            Byte1: u8,
+            ///  Data byte 2
+            Byte2: u8,
+            ///  Data byte 3
+            Byte3: u8,
+        }),
+    };
+
+    ///  Flexible memory controller
+    pub const FMC = extern struct {
+        ///  SRAM/NOR-Flash chip-select control register 1
+        BCR1: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            reserved11: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            ///  CCLKEN
+            CCLKEN: u1,
+            padding: u11,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 1
+        BTR1: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 2
+        BCR2: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 2
+        BTR2: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 3
+        BCR3: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 3
+        BTR3: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        ///  SRAM/NOR-Flash chip-select control register 4
+        BCR4: mmio.Mmio(packed struct(u32) {
+            ///  MBKEN
+            MBKEN: u1,
+            ///  MUXEN
+            MUXEN: u1,
+            ///  MTYP
+            MTYP: u2,
+            ///  MWID
+            MWID: u2,
+            ///  FACCEN
+            FACCEN: u1,
+            reserved8: u1,
+            ///  BURSTEN
+            BURSTEN: u1,
+            ///  WAITPOL
+            WAITPOL: u1,
+            ///  WRAPMOD
+            WRAPMOD: u1,
+            ///  WAITCFG
+            WAITCFG: u1,
+            ///  WREN
+            WREN: u1,
+            ///  WAITEN
+            WAITEN: u1,
+            ///  EXTMOD
+            EXTMOD: u1,
+            ///  ASYNCWAIT
+            ASYNCWAIT: u1,
+            reserved19: u3,
+            ///  CBURSTRW
+            CBURSTRW: u1,
+            padding: u12,
+        }),
+        ///  SRAM/NOR-Flash chip-select timing register 4
+        BTR4: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            ///  BUSTURN
+            BUSTURN: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved96: [64]u8,
+        ///  PC Card/NAND Flash control register 2
+        PCR2: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 2
+        SR2: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 2
+        PMEM2: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 2
+        PATT2: mmio.Mmio(packed struct(u32) {
+            ///  ATTSETx
+            ATTSETx: u8,
+            ///  ATTWAITx
+            ATTWAITx: u8,
+            ///  ATTHOLDx
+            ATTHOLDx: u8,
+            ///  ATTHIZx
+            ATTHIZx: u8,
+        }),
+        reserved116: [4]u8,
+        ///  ECC result register 2
+        ECCR2: mmio.Mmio(packed struct(u32) {
+            ///  ECCx
+            ECCx: u32,
+        }),
+        reserved128: [8]u8,
+        ///  PC Card/NAND Flash control register 3
+        PCR3: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 3
+        SR3: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 3
+        PMEM3: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 3
+        PATT3: mmio.Mmio(packed struct(u32) {
+            ///  ATTSETx
+            ATTSETx: u8,
+            ///  ATTWAITx
+            ATTWAITx: u8,
+            ///  ATTHOLDx
+            ATTHOLDx: u8,
+            ///  ATTHIZx
+            ATTHIZx: u8,
+        }),
+        reserved148: [4]u8,
+        ///  ECC result register 3
+        ECCR3: mmio.Mmio(packed struct(u32) {
+            ///  ECCx
+            ECCx: u32,
+        }),
+        reserved160: [8]u8,
+        ///  PC Card/NAND Flash control register 4
+        PCR4: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  PWAITEN
+            PWAITEN: u1,
+            ///  PBKEN
+            PBKEN: u1,
+            ///  PTYP
+            PTYP: u1,
+            ///  PWID
+            PWID: u2,
+            ///  ECCEN
+            ECCEN: u1,
+            reserved9: u2,
+            ///  TCLR
+            TCLR: u4,
+            ///  TAR
+            TAR: u4,
+            ///  ECCPS
+            ECCPS: u3,
+            padding: u12,
+        }),
+        ///  FIFO status and interrupt register 4
+        SR4: mmio.Mmio(packed struct(u32) {
+            ///  IRS
+            IRS: u1,
+            ///  ILS
+            ILS: u1,
+            ///  IFS
+            IFS: u1,
+            ///  IREN
+            IREN: u1,
+            ///  ILEN
+            ILEN: u1,
+            ///  IFEN
+            IFEN: u1,
+            ///  FEMPT
+            FEMPT: u1,
+            padding: u25,
+        }),
+        ///  Common memory space timing register 4
+        PMEM4: mmio.Mmio(packed struct(u32) {
+            ///  MEMSETx
+            MEMSETx: u8,
+            ///  MEMWAITx
+            MEMWAITx: u8,
+            ///  MEMHOLDx
+            MEMHOLDx: u8,
+            ///  MEMHIZx
+            MEMHIZx: u8,
+        }),
+        ///  Attribute memory space timing register 4
+        PATT4: mmio.Mmio(packed struct(u32) {
+            ///  ATTSETx
+            ATTSETx: u8,
+            ///  ATTWAITx
+            ATTWAITx: u8,
+            ///  ATTHOLDx
+            ATTHOLDx: u8,
+            ///  ATTHIZx
+            ATTHIZx: u8,
+        }),
+        ///  I/O space timing register 4
+        PIO4: mmio.Mmio(packed struct(u32) {
+            ///  IOSETx
+            IOSETx: u8,
+            ///  IOWAITx
+            IOWAITx: u8,
+            ///  IOHOLDx
+            IOHOLDx: u8,
+            ///  IOHIZx
+            IOHIZx: u8,
+        }),
+        reserved260: [80]u8,
+        ///  SRAM/NOR-Flash write timing registers 1
+        BWTR1: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            reserved20: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved268: [4]u8,
+        ///  SRAM/NOR-Flash write timing registers 2
+        BWTR2: mmio.Mmio(packed struct(u32) {
+            ///  ADDSET
+            ADDSET: u4,
+            ///  ADDHLD
+            ADDHLD: u4,
+            ///  DATAST
+            DATAST: u8,
+            reserved20: u4,
+            ///  CLKDIV
+            CLKDIV: u4,
+            ///  DATLAT
+            DATLAT: u4,
+            ///  ACCMOD
+            ACCMOD: u2,
+            padding: u2,
+        }),
+        reserved320: [48]u8,
+        ///  SDRAM Control Register 1
+        SDCR1: mmio.Mmio(packed struct(u32) {
+            ///  Number of column address bits
+            NC: u2,
+            ///  Number of row address bits
+            NR: u2,
+            ///  Memory data bus width
+            MWID: u2,
+            ///  Number of internal banks
+            NB: u1,
+            ///  CAS latency
+            CAS: u2,
+            ///  Write protection
+            WP: u1,
+            ///  SDRAM clock configuration
+            SDCLK: u2,
+            ///  Burst read
+            RBURST: u1,
+            ///  Read pipe
+            RPIPE: u2,
+            padding: u17,
+        }),
+        ///  SDRAM Control Register 2
+        SDCR2: mmio.Mmio(packed struct(u32) {
+            ///  Number of column address bits
+            NC: u2,
+            ///  Number of row address bits
+            NR: u2,
+            ///  Memory data bus width
+            MWID: u2,
+            ///  Number of internal banks
+            NB: u1,
+            ///  CAS latency
+            CAS: u2,
+            ///  Write protection
+            WP: u1,
+            ///  SDRAM clock configuration
+            SDCLK: u2,
+            ///  Burst read
+            RBURST: u1,
+            ///  Read pipe
+            RPIPE: u2,
+            padding: u17,
+        }),
+        ///  SDRAM Timing register 1
+        SDTR1: mmio.Mmio(packed struct(u32) {
+            ///  Load Mode Register to Active
+            TMRD: u4,
+            ///  Exit self-refresh delay
+            TXSR: u4,
+            ///  Self refresh time
+            TRAS: u4,
+            ///  Row cycle delay
+            TRC: u4,
+            ///  Recovery delay
+            TWR: u4,
+            ///  Row precharge delay
+            TRP: u4,
+            ///  Row to column delay
+            TRCD: u4,
+            padding: u4,
+        }),
+        ///  SDRAM Timing register 2
+        SDTR2: mmio.Mmio(packed struct(u32) {
+            ///  Load Mode Register to Active
+            TMRD: u4,
+            ///  Exit self-refresh delay
+            TXSR: u4,
+            ///  Self refresh time
+            TRAS: u4,
+            ///  Row cycle delay
+            TRC: u4,
+            ///  Recovery delay
+            TWR: u4,
+            ///  Row precharge delay
+            TRP: u4,
+            ///  Row to column delay
+            TRCD: u4,
+            padding: u4,
+        }),
+        ///  SDRAM Command Mode register
+        SDCMR: mmio.Mmio(packed struct(u32) {
+            ///  Command mode
+            MODE: u3,
+            ///  Command target bank 2
+            CTB2: u1,
+            ///  Command target bank 1
+            CTB1: u1,
+            ///  Number of Auto-refresh
+            NRFS: u4,
+            ///  Mode Register definition
+            MRD: u13,
+            padding: u10,
+        }),
+        ///  SDRAM Refresh Timer register
+        SDRTR: mmio.Mmio(packed struct(u32) {
+            ///  Clear Refresh error flag
+            CRE: u1,
+            ///  Refresh Timer Count
+            COUNT: u13,
+            ///  RES Interrupt Enable
+            REIE: u1,
+            padding: u17,
+        }),
+        ///  SDRAM Status register
+        SDSR: mmio.Mmio(packed struct(u32) {
+            ///  Refresh error flag
+            RE: u1,
+            ///  Status Mode for Bank 1
+            MODES1: u2,
+            ///  Status Mode for Bank 2
+            MODES2: u2,
+            ///  Busy status
+            BUSY: u1,
+            padding: u26,
+        }),
+    };
+
+    ///  Debug support
+    pub const DBG = extern struct {
+        ///  IDCODE
+        DBGMCU_IDCODE: mmio.Mmio(packed struct(u32) {
+            ///  DEV_ID
+            DEV_ID: u12,
+            reserved16: u4,
+            ///  REV_ID
+            REV_ID: u16,
+        }),
+        ///  Control Register
+        DBGMCU_CR: mmio.Mmio(packed struct(u32) {
+            ///  DBG_SLEEP
+            DBG_SLEEP: u1,
+            ///  DBG_STOP
+            DBG_STOP: u1,
+            ///  DBG_STANDBY
+            DBG_STANDBY: u1,
+            reserved5: u2,
+            ///  TRACE_IOEN
+            TRACE_IOEN: u1,
+            ///  TRACE_MODE
+            TRACE_MODE: u2,
+            padding: u24,
+        }),
+        ///  Debug MCU APB1 Freeze registe
+        DBGMCU_APB1_FZ: mmio.Mmio(packed struct(u32) {
+            ///  DBG_TIM2_STOP
+            DBG_TIM2_STOP: u1,
+            ///  DBG_TIM3 _STOP
+            DBG_TIM3_STOP: u1,
+            ///  DBG_TIM4_STOP
+            DBG_TIM4_STOP: u1,
+            ///  DBG_TIM5_STOP
+            DBG_TIM5_STOP: u1,
+            ///  DBG_TIM6_STOP
+            DBG_TIM6_STOP: u1,
+            ///  DBG_TIM7_STOP
+            DBG_TIM7_STOP: u1,
+            ///  DBG_TIM12_STOP
+            DBG_TIM12_STOP: u1,
+            ///  DBG_TIM13_STOP
+            DBG_TIM13_STOP: u1,
+            ///  DBG_TIM14_STOP
+            DBG_TIM14_STOP: u1,
+            reserved11: u2,
+            ///  DBG_WWDG_STOP
+            DBG_WWDG_STOP: u1,
+            ///  DBG_IWDEG_STOP
+            DBG_IWDEG_STOP: u1,
+            reserved21: u8,
+            ///  DBG_J2C1_SMBUS_TIMEOUT
+            DBG_J2C1_SMBUS_TIMEOUT: u1,
+            ///  DBG_J2C2_SMBUS_TIMEOUT
+            DBG_J2C2_SMBUS_TIMEOUT: u1,
+            ///  DBG_J2C3SMBUS_TIMEOUT
+            DBG_J2C3SMBUS_TIMEOUT: u1,
+            reserved25: u1,
+            ///  DBG_CAN1_STOP
+            DBG_CAN1_STOP: u1,
+            ///  DBG_CAN2_STOP
+            DBG_CAN2_STOP: u1,
+            padding: u5,
+        }),
+        ///  Debug MCU APB2 Freeze registe
+        DBGMCU_APB2_FZ: mmio.Mmio(packed struct(u32) {
+            ///  TIM1 counter stopped when core is halted
+            DBG_TIM1_STOP: u1,
+            ///  TIM8 counter stopped when core is halted
+            DBG_TIM8_STOP: u1,
+            reserved16: u14,
+            ///  TIM9 counter stopped when core is halted
+            DBG_TIM9_STOP: u1,
+            ///  TIM10 counter stopped when core is halted
+            DBG_TIM10_STOP: u1,
+            ///  TIM11 counter stopped when core is halted
+            DBG_TIM11_STOP: u1,
+            padding: u13,
+        }),
+    };
+
+    ///  DMA controller
+    pub const DMA2 = extern struct {
+        ///  low interrupt status register
+        LISR: mmio.Mmio(packed struct(u32) {
+            ///  Stream x FIFO error interrupt flag (x=3..0)
+            FEIF0: u1,
+            reserved2: u1,
+            ///  Stream x direct mode error interrupt flag (x=3..0)
+            DMEIF0: u1,
+            ///  Stream x transfer error interrupt flag (x=3..0)
+            TEIF0: u1,
+            ///  Stream x half transfer interrupt flag (x=3..0)
+            HTIF0: u1,
+            ///  Stream x transfer complete interrupt flag (x = 3..0)
+            TCIF0: u1,
+            ///  Stream x FIFO error interrupt flag (x=3..0)
+            FEIF1: u1,
+            reserved8: u1,
+            ///  Stream x direct mode error interrupt flag (x=3..0)
+            DMEIF1: u1,
+            ///  Stream x transfer error interrupt flag (x=3..0)
+            TEIF1: u1,
+            ///  Stream x half transfer interrupt flag (x=3..0)
+            HTIF1: u1,
+            ///  Stream x transfer complete interrupt flag (x = 3..0)
+            TCIF1: u1,
+            reserved16: u4,
+            ///  Stream x FIFO error interrupt flag (x=3..0)
+            FEIF2: u1,
+            reserved18: u1,
+            ///  Stream x direct mode error interrupt flag (x=3..0)
+            DMEIF2: u1,
+            ///  Stream x transfer error interrupt flag (x=3..0)
+            TEIF2: u1,
+            ///  Stream x half transfer interrupt flag (x=3..0)
+            HTIF2: u1,
+            ///  Stream x transfer complete interrupt flag (x = 3..0)
+            TCIF2: u1,
+            ///  Stream x FIFO error interrupt flag (x=3..0)
+            FEIF3: u1,
+            reserved24: u1,
+            ///  Stream x direct mode error interrupt flag (x=3..0)
+            DMEIF3: u1,
+            ///  Stream x transfer error interrupt flag (x=3..0)
+            TEIF3: u1,
+            ///  Stream x half transfer interrupt flag (x=3..0)
+            HTIF3: u1,
+            ///  Stream x transfer complete interrupt flag (x = 3..0)
+            TCIF3: u1,
+            padding: u4,
+        }),
+        ///  high interrupt status register
+        HISR: mmio.Mmio(packed struct(u32) {
+            ///  Stream x FIFO error interrupt flag (x=7..4)
+            FEIF4: u1,
+            reserved2: u1,
+            ///  Stream x direct mode error interrupt flag (x=7..4)
+            DMEIF4: u1,
+            ///  Stream x transfer error interrupt flag (x=7..4)
+            TEIF4: u1,
+            ///  Stream x half transfer interrupt flag (x=7..4)
+            HTIF4: u1,
+            ///  Stream x transfer complete interrupt flag (x=7..4)
+            TCIF4: u1,
+            ///  Stream x FIFO error interrupt flag (x=7..4)
+            FEIF5: u1,
+            reserved8: u1,
+            ///  Stream x direct mode error interrupt flag (x=7..4)
+            DMEIF5: u1,
+            ///  Stream x transfer error interrupt flag (x=7..4)
+            TEIF5: u1,
+            ///  Stream x half transfer interrupt flag (x=7..4)
+            HTIF5: u1,
+            ///  Stream x transfer complete interrupt flag (x=7..4)
+            TCIF5: u1,
+            reserved16: u4,
+            ///  Stream x FIFO error interrupt flag (x=7..4)
+            FEIF6: u1,
+            reserved18: u1,
+            ///  Stream x direct mode error interrupt flag (x=7..4)
+            DMEIF6: u1,
+            ///  Stream x transfer error interrupt flag (x=7..4)
+            TEIF6: u1,
+            ///  Stream x half transfer interrupt flag (x=7..4)
+            HTIF6: u1,
+            ///  Stream x transfer complete interrupt flag (x=7..4)
+            TCIF6: u1,
+            ///  Stream x FIFO error interrupt flag (x=7..4)
+            FEIF7: u1,
+            reserved24: u1,
+            ///  Stream x direct mode error interrupt flag (x=7..4)
+            DMEIF7: u1,
+            ///  Stream x transfer error interrupt flag (x=7..4)
+            TEIF7: u1,
+            ///  Stream x half transfer interrupt flag (x=7..4)
+            HTIF7: u1,
+            ///  Stream x transfer complete interrupt flag (x=7..4)
+            TCIF7: u1,
+            padding: u4,
+        }),
+        ///  low interrupt flag clear register
+        LIFCR: mmio.Mmio(packed struct(u32) {
+            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
+            CFEIF0: u1,
+            reserved2: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
+            CDMEIF0: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 3..0)
+            CTEIF0: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 3..0)
+            CHTIF0: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
+            CTCIF0: u1,
+            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
+            CFEIF1: u1,
+            reserved8: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
+            CDMEIF1: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 3..0)
+            CTEIF1: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 3..0)
+            CHTIF1: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
+            CTCIF1: u1,
+            reserved16: u4,
+            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
+            CFEIF2: u1,
+            reserved18: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
+            CDMEIF2: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 3..0)
+            CTEIF2: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 3..0)
+            CHTIF2: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
+            CTCIF2: u1,
+            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
+            CFEIF3: u1,
+            reserved24: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
+            CDMEIF3: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 3..0)
+            CTEIF3: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 3..0)
+            CHTIF3: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
+            CTCIF3: u1,
+            padding: u4,
+        }),
+        ///  high interrupt flag clear register
+        HIFCR: mmio.Mmio(packed struct(u32) {
+            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
+            CFEIF4: u1,
+            reserved2: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
+            CDMEIF4: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 7..4)
+            CTEIF4: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 7..4)
+            CHTIF4: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
+            CTCIF4: u1,
+            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
+            CFEIF5: u1,
+            reserved8: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
+            CDMEIF5: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 7..4)
+            CTEIF5: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 7..4)
+            CHTIF5: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
+            CTCIF5: u1,
+            reserved16: u4,
+            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
+            CFEIF6: u1,
+            reserved18: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
+            CDMEIF6: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 7..4)
+            CTEIF6: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 7..4)
+            CHTIF6: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
+            CTCIF6: u1,
+            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
+            CFEIF7: u1,
+            reserved24: u1,
+            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
+            CDMEIF7: u1,
+            ///  Stream x clear transfer error interrupt flag (x = 7..4)
+            CTEIF7: u1,
+            ///  Stream x clear half transfer interrupt flag (x = 7..4)
+            CHTIF7: u1,
+            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
+            CTCIF7: u1,
+            padding: u4,
+        }),
+        ///  stream x configuration register
+        S0CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            reserved21: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S0NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S0PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S0M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S0M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S0FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S1CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S1NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S1PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S1M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S1M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S1FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S2CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S2NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S2PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S2M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S2M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S2FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S3CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S3NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S3PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S3M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S3M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S3FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S4CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S4NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S4PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S4M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S4M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S4FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S5CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S5NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S5PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S5M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S5M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S5FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S6CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S6NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S6PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S6M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S6M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S6FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+        ///  stream x configuration register
+        S7CR: mmio.Mmio(packed struct(u32) {
+            ///  Stream enable / flag stream ready when read low
+            EN: u1,
+            ///  Direct mode error interrupt enable
+            DMEIE: u1,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Half transfer interrupt enable
+            HTIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Peripheral flow controller
+            PFCTRL: u1,
+            ///  Data transfer direction
+            DIR: u2,
+            ///  Circular mode
+            CIRC: u1,
+            ///  Peripheral increment mode
+            PINC: u1,
+            ///  Memory increment mode
+            MINC: u1,
+            ///  Peripheral data size
+            PSIZE: u2,
+            ///  Memory data size
+            MSIZE: u2,
+            ///  Peripheral increment offset size
+            PINCOS: u1,
+            ///  Priority level
+            PL: u2,
+            ///  Double buffer mode
+            DBM: u1,
+            ///  Current target (only in double buffer mode)
+            CT: u1,
+            ///  ACK
+            ACK: u1,
+            ///  Peripheral burst transfer configuration
+            PBURST: u2,
+            ///  Memory burst transfer configuration
+            MBURST: u2,
+            ///  Channel selection
+            CHSEL: u3,
+            padding: u4,
+        }),
+        ///  stream x number of data register
+        S7NDTR: mmio.Mmio(packed struct(u32) {
+            ///  Number of data items to transfer
+            NDT: u16,
+            padding: u16,
+        }),
+        ///  stream x peripheral address register
+        S7PAR: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral address
+            PA: u32,
+        }),
+        ///  stream x memory 0 address register
+        S7M0AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 0 address
+            M0A: u32,
+        }),
+        ///  stream x memory 1 address register
+        S7M1AR: mmio.Mmio(packed struct(u32) {
+            ///  Memory 1 address (used in case of Double buffer mode)
+            M1A: u32,
+        }),
+        ///  stream x FIFO control register
+        S7FCR: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold selection
+            FTH: u2,
+            ///  Direct mode disable
+            DMDIS: u1,
+            ///  FIFO status
+            FS: u3,
+            reserved7: u1,
+            ///  FIFO error interrupt enable
+            FEIE: u1,
+            padding: u24,
+        }),
+    };
+
+    ///  System control block ACTLR
+    pub const SCB_ACTRL = extern struct {
+        ///  Auxiliary control register
+        ACTRL: mmio.Mmio(packed struct(u32) {
+            ///  DISMCYCINT
+            DISMCYCINT: u1,
+            ///  DISDEFWBUF
+            DISDEFWBUF: u1,
+            ///  DISFOLD
+            DISFOLD: u1,
+            reserved8: u5,
+            ///  DISFPCA
+            DISFPCA: u1,
+            ///  DISOOFP
+            DISOOFP: u1,
+            padding: u22,
+        }),
+    };
+
+    ///  Reset and clock control
+    pub const RCC = extern struct {
+        ///  clock control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Internal high-speed clock enable
+            HSION: u1,
+            ///  Internal high-speed clock ready flag
+            HSIRDY: u1,
+            reserved3: u1,
+            ///  Internal high-speed clock trimming
+            HSITRIM: u5,
+            ///  Internal high-speed clock calibration
+            HSICAL: u8,
+            ///  HSE clock enable
+            HSEON: u1,
+            ///  HSE clock ready flag
+            HSERDY: u1,
+            ///  HSE clock bypass
+            HSEBYP: u1,
+            ///  Clock security system enable
+            CSSON: u1,
+            reserved24: u4,
+            ///  Main PLL (PLL) enable
+            PLLON: u1,
+            ///  Main PLL (PLL) clock ready flag
+            PLLRDY: u1,
+            ///  PLLI2S enable
+            PLLI2SON: u1,
+            ///  PLLI2S clock ready flag
+            PLLI2SRDY: u1,
+            padding: u4,
+        }),
+        ///  PLL configuration register
+        PLLCFGR: mmio.Mmio(packed struct(u32) {
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM0: u1,
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM1: u1,
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM2: u1,
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM3: u1,
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM4: u1,
+            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
+            PLLM5: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN0: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN1: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN2: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN3: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN4: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN5: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN6: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN7: u1,
+            ///  Main PLL (PLL) multiplication factor for VCO
+            PLLN8: u1,
+            reserved16: u1,
+            ///  Main PLL (PLL) division factor for main system clock
+            PLLP0: u1,
+            ///  Main PLL (PLL) division factor for main system clock
+            PLLP1: u1,
+            reserved22: u4,
+            ///  Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
+            PLLSRC: u1,
+            reserved24: u1,
+            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
+            PLLQ0: u1,
+            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
+            PLLQ1: u1,
+            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
+            PLLQ2: u1,
+            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
+            PLLQ3: u1,
+            padding: u4,
+        }),
+        ///  clock configuration register
+        CFGR: mmio.Mmio(packed struct(u32) {
+            ///  System clock switch
+            SW0: u1,
+            ///  System clock switch
+            SW1: u1,
+            ///  System clock switch status
+            SWS0: u1,
+            ///  System clock switch status
+            SWS1: u1,
+            ///  AHB prescaler
+            HPRE: u4,
+            reserved10: u2,
+            ///  APB Low speed prescaler (APB1)
+            PPRE1: u3,
+            ///  APB high-speed prescaler (APB2)
+            PPRE2: u3,
+            ///  HSE division factor for RTC clock
+            RTCPRE: u5,
+            ///  Microcontroller clock output 1
+            MCO1: u2,
+            ///  I2S clock selection
+            I2SSRC: u1,
+            ///  MCO1 prescaler
+            MCO1PRE: u3,
+            ///  MCO2 prescaler
+            MCO2PRE: u3,
+            ///  Microcontroller clock output 2
+            MCO2: u2,
+        }),
+        ///  clock interrupt register
+        CIR: mmio.Mmio(packed struct(u32) {
+            ///  LSI ready interrupt flag
+            LSIRDYF: u1,
+            ///  LSE ready interrupt flag
+            LSERDYF: u1,
+            ///  HSI ready interrupt flag
+            HSIRDYF: u1,
+            ///  HSE ready interrupt flag
+            HSERDYF: u1,
+            ///  Main PLL (PLL) ready interrupt flag
+            PLLRDYF: u1,
+            ///  PLLI2S ready interrupt flag
+            PLLI2SRDYF: u1,
+            reserved7: u1,
+            ///  Clock security system interrupt flag
+            CSSF: u1,
+            ///  LSI ready interrupt enable
+            LSIRDYIE: u1,
+            ///  LSE ready interrupt enable
+            LSERDYIE: u1,
+            ///  HSI ready interrupt enable
+            HSIRDYIE: u1,
+            ///  HSE ready interrupt enable
+            HSERDYIE: u1,
+            ///  Main PLL (PLL) ready interrupt enable
+            PLLRDYIE: u1,
+            ///  PLLI2S ready interrupt enable
+            PLLI2SRDYIE: u1,
+            reserved16: u2,
+            ///  LSI ready interrupt clear
+            LSIRDYC: u1,
+            ///  LSE ready interrupt clear
+            LSERDYC: u1,
+            ///  HSI ready interrupt clear
+            HSIRDYC: u1,
+            ///  HSE ready interrupt clear
+            HSERDYC: u1,
+            ///  Main PLL(PLL) ready interrupt clear
+            PLLRDYC: u1,
+            ///  PLLI2S ready interrupt clear
+            PLLI2SRDYC: u1,
+            reserved23: u1,
+            ///  Clock security system interrupt clear
+            CSSC: u1,
+            padding: u8,
+        }),
+        ///  AHB1 peripheral reset register
+        AHB1RSTR: mmio.Mmio(packed struct(u32) {
+            ///  IO port A reset
+            GPIOARST: u1,
+            ///  IO port B reset
+            GPIOBRST: u1,
+            ///  IO port C reset
+            GPIOCRST: u1,
+            ///  IO port D reset
+            GPIODRST: u1,
+            ///  IO port E reset
+            GPIOERST: u1,
+            ///  IO port F reset
+            GPIOFRST: u1,
+            ///  IO port G reset
+            GPIOGRST: u1,
+            ///  IO port H reset
+            GPIOHRST: u1,
+            ///  IO port I reset
+            GPIOIRST: u1,
+            reserved12: u3,
+            ///  CRC reset
+            CRCRST: u1,
+            reserved21: u8,
+            ///  DMA2 reset
+            DMA1RST: u1,
+            ///  DMA2 reset
+            DMA2RST: u1,
+            reserved25: u2,
+            ///  Ethernet MAC reset
+            ETHMACRST: u1,
+            reserved29: u3,
+            ///  USB OTG HS module reset
+            OTGHSRST: u1,
+            padding: u2,
+        }),
+        ///  AHB2 peripheral reset register
+        AHB2RSTR: mmio.Mmio(packed struct(u32) {
+            ///  Camera interface reset
+            DCMIRST: u1,
+            reserved4: u3,
+            ///  Cryptographic module reset
+            CRYPRST: u1,
+            ///  Hash module reset
+            HSAHRST: u1,
+            ///  Random number generator module reset
+            RNGRST: u1,
+            ///  USB OTG FS module reset
+            OTGFSRST: u1,
+            padding: u24,
+        }),
+        ///  AHB3 peripheral reset register
+        AHB3RSTR: mmio.Mmio(packed struct(u32) {
+            ///  Flexible memory controller module reset
+            FMCRST: u1,
+            padding: u31,
+        }),
+        reserved32: [4]u8,
+        ///  APB1 peripheral reset register
+        APB1RSTR: mmio.Mmio(packed struct(u32) {
+            ///  TIM2 reset
+            TIM2RST: u1,
+            ///  TIM3 reset
+            TIM3RST: u1,
+            ///  TIM4 reset
+            TIM4RST: u1,
+            ///  TIM5 reset
+            TIM5RST: u1,
+            ///  TIM6 reset
+            TIM6RST: u1,
+            ///  TIM7 reset
+            TIM7RST: u1,
+            ///  TIM12 reset
+            TIM12RST: u1,
+            ///  TIM13 reset
+            TIM13RST: u1,
+            ///  TIM14 reset
+            TIM14RST: u1,
+            reserved11: u2,
+            ///  Window watchdog reset
+            WWDGRST: u1,
+            reserved14: u2,
+            ///  SPI 2 reset
+            SPI2RST: u1,
+            ///  SPI 3 reset
+            SPI3RST: u1,
+            reserved17: u1,
+            ///  USART 2 reset
+            UART2RST: u1,
+            ///  USART 3 reset
+            UART3RST: u1,
+            ///  USART 4 reset
+            UART4RST: u1,
+            ///  USART 5 reset
+            UART5RST: u1,
+            ///  I2C 1 reset
+            I2C1RST: u1,
+            ///  I2C 2 reset
+            I2C2RST: u1,
+            ///  I2C3 reset
+            I2C3RST: u1,
+            reserved25: u1,
+            ///  CAN1 reset
+            CAN1RST: u1,
+            ///  CAN2 reset
+            CAN2RST: u1,
+            reserved28: u1,
+            ///  Power interface reset
+            PWRRST: u1,
+            ///  DAC reset
+            DACRST: u1,
+            padding: u2,
+        }),
+        ///  APB2 peripheral reset register
+        APB2RSTR: mmio.Mmio(packed struct(u32) {
+            ///  TIM1 reset
+            TIM1RST: u1,
+            ///  TIM8 reset
+            TIM8RST: u1,
+            reserved4: u2,
+            ///  USART1 reset
+            USART1RST: u1,
+            ///  USART6 reset
+            USART6RST: u1,
+            reserved8: u2,
+            ///  ADC interface reset (common to all ADCs)
+            ADCRST: u1,
+            reserved11: u2,
+            ///  SDIO reset
+            SDIORST: u1,
+            ///  SPI 1 reset
+            SPI1RST: u1,
+            reserved14: u1,
+            ///  System configuration controller reset
+            SYSCFGRST: u1,
+            reserved16: u1,
+            ///  TIM9 reset
+            TIM9RST: u1,
+            ///  TIM10 reset
+            TIM10RST: u1,
+            ///  TIM11 reset
+            TIM11RST: u1,
+            padding: u13,
+        }),
+        reserved48: [8]u8,
+        ///  AHB1 peripheral clock register
+        AHB1ENR: mmio.Mmio(packed struct(u32) {
+            ///  IO port A clock enable
+            GPIOAEN: u1,
+            ///  IO port B clock enable
+            GPIOBEN: u1,
+            ///  IO port C clock enable
+            GPIOCEN: u1,
+            ///  IO port D clock enable
+            GPIODEN: u1,
+            ///  IO port E clock enable
+            GPIOEEN: u1,
+            ///  IO port F clock enable
+            GPIOFEN: u1,
+            ///  IO port G clock enable
+            GPIOGEN: u1,
+            ///  IO port H clock enable
+            GPIOHEN: u1,
+            ///  IO port I clock enable
+            GPIOIEN: u1,
+            reserved12: u3,
+            ///  CRC clock enable
+            CRCEN: u1,
+            reserved18: u5,
+            ///  Backup SRAM interface clock enable
+            BKPSRAMEN: u1,
+            reserved20: u1,
+            ///  CCM data RAM clock enable
+            CCMDATARAMEN: u1,
+            ///  DMA1 clock enable
+            DMA1EN: u1,
+            ///  DMA2 clock enable
+            DMA2EN: u1,
+            reserved25: u2,
+            ///  Ethernet MAC clock enable
+            ETHMACEN: u1,
+            ///  Ethernet Transmission clock enable
+            ETHMACTXEN: u1,
+            ///  Ethernet Reception clock enable
+            ETHMACRXEN: u1,
+            ///  Ethernet PTP clock enable
+            ETHMACPTPEN: u1,
+            ///  USB OTG HS clock enable
+            OTGHSEN: u1,
+            ///  USB OTG HSULPI clock enable
+            OTGHSULPIEN: u1,
+            padding: u1,
+        }),
+        ///  AHB2 peripheral clock enable register
+        AHB2ENR: mmio.Mmio(packed struct(u32) {
+            ///  Camera interface enable
+            DCMIEN: u1,
+            reserved4: u3,
+            ///  Cryptographic modules clock enable
+            CRYPEN: u1,
+            ///  Hash modules clock enable
+            HASHEN: u1,
+            ///  Random number generator clock enable
+            RNGEN: u1,
+            ///  USB OTG FS clock enable
+            OTGFSEN: u1,
+            padding: u24,
+        }),
+        ///  AHB3 peripheral clock enable register
+        AHB3ENR: mmio.Mmio(packed struct(u32) {
+            ///  Flexible memory controller module clock enable
+            FMCEN: u1,
+            padding: u31,
+        }),
+        reserved64: [4]u8,
+        ///  APB1 peripheral clock enable register
+        APB1ENR: mmio.Mmio(packed struct(u32) {
+            ///  TIM2 clock enable
+            TIM2EN: u1,
+            ///  TIM3 clock enable
+            TIM3EN: u1,
+            ///  TIM4 clock enable
+            TIM4EN: u1,
+            ///  TIM5 clock enable
+            TIM5EN: u1,
+            ///  TIM6 clock enable
+            TIM6EN: u1,
+            ///  TIM7 clock enable
+            TIM7EN: u1,
+            ///  TIM12 clock enable
+            TIM12EN: u1,
+            ///  TIM13 clock enable
+            TIM13EN: u1,
+            ///  TIM14 clock enable
+            TIM14EN: u1,
+            reserved11: u2,
+            ///  Window watchdog clock enable
+            WWDGEN: u1,
+            reserved14: u2,
+            ///  SPI2 clock enable
+            SPI2EN: u1,
+            ///  SPI3 clock enable
+            SPI3EN: u1,
+            reserved17: u1,
+            ///  USART 2 clock enable
+            USART2EN: u1,
+            ///  USART3 clock enable
+            USART3EN: u1,
+            ///  UART4 clock enable
+            UART4EN: u1,
+            ///  UART5 clock enable
+            UART5EN: u1,
+            ///  I2C1 clock enable
+            I2C1EN: u1,
+            ///  I2C2 clock enable
+            I2C2EN: u1,
+            ///  I2C3 clock enable
+            I2C3EN: u1,
+            reserved25: u1,
+            ///  CAN 1 clock enable
+            CAN1EN: u1,
+            ///  CAN 2 clock enable
+            CAN2EN: u1,
+            reserved28: u1,
+            ///  Power interface clock enable
+            PWREN: u1,
+            ///  DAC interface clock enable
+            DACEN: u1,
+            padding: u2,
+        }),
+        ///  APB2 peripheral clock enable register
+        APB2ENR: mmio.Mmio(packed struct(u32) {
+            ///  TIM1 clock enable
+            TIM1EN: u1,
+            ///  TIM8 clock enable
+            TIM8EN: u1,
+            reserved4: u2,
+            ///  USART1 clock enable
+            USART1EN: u1,
+            ///  USART6 clock enable
+            USART6EN: u1,
+            reserved8: u2,
+            ///  ADC1 clock enable
+            ADC1EN: u1,
+            ///  ADC2 clock enable
+            ADC2EN: u1,
+            ///  ADC3 clock enable
+            ADC3EN: u1,
+            ///  SDIO clock enable
+            SDIOEN: u1,
+            ///  SPI1 clock enable
+            SPI1EN: u1,
+            reserved14: u1,
+            ///  System configuration controller clock enable
+            SYSCFGEN: u1,
+            reserved16: u1,
+            ///  TIM9 clock enable
+            TIM9EN: u1,
+            ///  TIM10 clock enable
+            TIM10EN: u1,
+            ///  TIM11 clock enable
+            TIM11EN: u1,
+            padding: u13,
+        }),
+        reserved80: [8]u8,
+        ///  AHB1 peripheral clock enable in low power mode register
+        AHB1LPENR: mmio.Mmio(packed struct(u32) {
+            ///  IO port A clock enable during sleep mode
+            GPIOALPEN: u1,
+            ///  IO port B clock enable during Sleep mode
+            GPIOBLPEN: u1,
+            ///  IO port C clock enable during Sleep mode
+            GPIOCLPEN: u1,
+            ///  IO port D clock enable during Sleep mode
+            GPIODLPEN: u1,
+            ///  IO port E clock enable during Sleep mode
+            GPIOELPEN: u1,
+            ///  IO port F clock enable during Sleep mode
+            GPIOFLPEN: u1,
+            ///  IO port G clock enable during Sleep mode
+            GPIOGLPEN: u1,
+            ///  IO port H clock enable during Sleep mode
+            GPIOHLPEN: u1,
+            ///  IO port I clock enable during Sleep mode
+            GPIOILPEN: u1,
+            reserved12: u3,
+            ///  CRC clock enable during Sleep mode
+            CRCLPEN: u1,
+            reserved15: u2,
+            ///  Flash interface clock enable during Sleep mode
+            FLITFLPEN: u1,
+            ///  SRAM 1interface clock enable during Sleep mode
+            SRAM1LPEN: u1,
+            ///  SRAM 2 interface clock enable during Sleep mode
+            SRAM2LPEN: u1,
+            ///  Backup SRAM interface clock enable during Sleep mode
+            BKPSRAMLPEN: u1,
+            reserved21: u2,
+            ///  DMA1 clock enable during Sleep mode
+            DMA1LPEN: u1,
+            ///  DMA2 clock enable during Sleep mode
+            DMA2LPEN: u1,
+            reserved25: u2,
+            ///  Ethernet MAC clock enable during Sleep mode
+            ETHMACLPEN: u1,
+            ///  Ethernet transmission clock enable during Sleep mode
+            ETHMACTXLPEN: u1,
+            ///  Ethernet reception clock enable during Sleep mode
+            ETHMACRXLPEN: u1,
+            ///  Ethernet PTP clock enable during Sleep mode
+            ETHMACPTPLPEN: u1,
+            ///  USB OTG HS clock enable during Sleep mode
+            OTGHSLPEN: u1,
+            ///  USB OTG HS ULPI clock enable during Sleep mode
+            OTGHSULPILPEN: u1,
+            padding: u1,
+        }),
+        ///  AHB2 peripheral clock enable in low power mode register
+        AHB2LPENR: mmio.Mmio(packed struct(u32) {
+            ///  Camera interface enable during Sleep mode
+            DCMILPEN: u1,
+            reserved4: u3,
+            ///  Cryptography modules clock enable during Sleep mode
+            CRYPLPEN: u1,
+            ///  Hash modules clock enable during Sleep mode
+            HASHLPEN: u1,
+            ///  Random number generator clock enable during Sleep mode
+            RNGLPEN: u1,
+            ///  USB OTG FS clock enable during Sleep mode
+            OTGFSLPEN: u1,
+            padding: u24,
+        }),
+        ///  AHB3 peripheral clock enable in low power mode register
+        AHB3LPENR: mmio.Mmio(packed struct(u32) {
+            ///  Flexible memory controller module clock enable during Sleep mode
+            FMCLPEN: u1,
+            padding: u31,
+        }),
+        reserved96: [4]u8,
+        ///  APB1 peripheral clock enable in low power mode register
+        APB1LPENR: mmio.Mmio(packed struct(u32) {
+            ///  TIM2 clock enable during Sleep mode
+            TIM2LPEN: u1,
+            ///  TIM3 clock enable during Sleep mode
+            TIM3LPEN: u1,
+            ///  TIM4 clock enable during Sleep mode
+            TIM4LPEN: u1,
+            ///  TIM5 clock enable during Sleep mode
+            TIM5LPEN: u1,
+            ///  TIM6 clock enable during Sleep mode
+            TIM6LPEN: u1,
+            ///  TIM7 clock enable during Sleep mode
+            TIM7LPEN: u1,
+            ///  TIM12 clock enable during Sleep mode
+            TIM12LPEN: u1,
+            ///  TIM13 clock enable during Sleep mode
+            TIM13LPEN: u1,
+            ///  TIM14 clock enable during Sleep mode
+            TIM14LPEN: u1,
+            reserved11: u2,
+            ///  Window watchdog clock enable during Sleep mode
+            WWDGLPEN: u1,
+            reserved14: u2,
+            ///  SPI2 clock enable during Sleep mode
+            SPI2LPEN: u1,
+            ///  SPI3 clock enable during Sleep mode
+            SPI3LPEN: u1,
+            reserved17: u1,
+            ///  USART2 clock enable during Sleep mode
+            USART2LPEN: u1,
+            ///  USART3 clock enable during Sleep mode
+            USART3LPEN: u1,
+            ///  UART4 clock enable during Sleep mode
+            UART4LPEN: u1,
+            ///  UART5 clock enable during Sleep mode
+            UART5LPEN: u1,
+            ///  I2C1 clock enable during Sleep mode
+            I2C1LPEN: u1,
+            ///  I2C2 clock enable during Sleep mode
+            I2C2LPEN: u1,
+            ///  I2C3 clock enable during Sleep mode
+            I2C3LPEN: u1,
+            reserved25: u1,
+            ///  CAN 1 clock enable during Sleep mode
+            CAN1LPEN: u1,
+            ///  CAN 2 clock enable during Sleep mode
+            CAN2LPEN: u1,
+            reserved28: u1,
+            ///  Power interface clock enable during Sleep mode
+            PWRLPEN: u1,
+            ///  DAC interface clock enable during Sleep mode
+            DACLPEN: u1,
+            padding: u2,
+        }),
+        ///  APB2 peripheral clock enabled in low power mode register
+        APB2LPENR: mmio.Mmio(packed struct(u32) {
+            ///  TIM1 clock enable during Sleep mode
+            TIM1LPEN: u1,
+            ///  TIM8 clock enable during Sleep mode
+            TIM8LPEN: u1,
+            reserved4: u2,
+            ///  USART1 clock enable during Sleep mode
+            USART1LPEN: u1,
+            ///  USART6 clock enable during Sleep mode
+            USART6LPEN: u1,
+            reserved8: u2,
+            ///  ADC1 clock enable during Sleep mode
+            ADC1LPEN: u1,
+            ///  ADC2 clock enable during Sleep mode
+            ADC2LPEN: u1,
+            ///  ADC 3 clock enable during Sleep mode
+            ADC3LPEN: u1,
+            ///  SDIO clock enable during Sleep mode
+            SDIOLPEN: u1,
+            ///  SPI 1 clock enable during Sleep mode
+            SPI1LPEN: u1,
+            reserved14: u1,
+            ///  System configuration controller clock enable during Sleep mode
+            SYSCFGLPEN: u1,
+            reserved16: u1,
+            ///  TIM9 clock enable during sleep mode
+            TIM9LPEN: u1,
+            ///  TIM10 clock enable during Sleep mode
+            TIM10LPEN: u1,
+            ///  TIM11 clock enable during Sleep mode
+            TIM11LPEN: u1,
+            padding: u13,
+        }),
+        reserved112: [8]u8,
+        ///  Backup domain control register
+        BDCR: mmio.Mmio(packed struct(u32) {
+            ///  External low-speed oscillator enable
+            LSEON: u1,
+            ///  External low-speed oscillator ready
+            LSERDY: u1,
+            ///  External low-speed oscillator bypass
+            LSEBYP: u1,
+            reserved8: u5,
+            ///  RTC clock source selection
+            RTCSEL0: u1,
+            ///  RTC clock source selection
+            RTCSEL1: u1,
+            reserved15: u5,
+            ///  RTC clock enable
+            RTCEN: u1,
+            ///  Backup domain software reset
+            BDRST: u1,
+            padding: u15,
+        }),
+        ///  clock control & status register
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  Internal low-speed oscillator enable
+            LSION: u1,
+            ///  Internal low-speed oscillator ready
+            LSIRDY: u1,
+            reserved24: u22,
+            ///  Remove reset flag
+            RMVF: u1,
+            ///  BOR reset flag
+            BORRSTF: u1,
+            ///  PIN reset flag
+            PADRSTF: u1,
+            ///  POR/PDR reset flag
+            PORRSTF: u1,
+            ///  Software reset flag
+            SFTRSTF: u1,
+            ///  Independent watchdog reset flag
+            WDGRSTF: u1,
+            ///  Window watchdog reset flag
+            WWDGRSTF: u1,
+            ///  Low-power reset flag
+            LPWRRSTF: u1,
+        }),
+        reserved128: [8]u8,
+        ///  spread spectrum clock generation register
+        SSCGR: mmio.Mmio(packed struct(u32) {
+            ///  Modulation period
+            MODPER: u13,
+            ///  Incrementation step
+            INCSTEP: u15,
+            reserved30: u2,
+            ///  Spread Select
+            SPREADSEL: u1,
+            ///  Spread spectrum modulation enable
+            SSCGEN: u1,
+        }),
+        ///  PLLI2S configuration register
+        PLLI2SCFGR: mmio.Mmio(packed struct(u32) {
+            reserved6: u6,
+            ///  PLLI2S multiplication factor for VCO
+            PLLI2SN: u9,
+            reserved24: u9,
+            ///  PLLI2S division factor for SAI1 clock
+            PLLI2SQ: u4,
+            ///  PLLI2S division factor for I2S clocks
+            PLLI2SR: u3,
+            padding: u1,
+        }),
+        ///  RCC PLL configuration register
+        PLLSAICFGR: mmio.Mmio(packed struct(u32) {
+            reserved6: u6,
+            ///  PLLSAI division factor for VCO
+            PLLSAIN: u9,
+            reserved24: u9,
+            ///  PLLSAI division factor for SAI1 clock
+            PLLSAIQ: u4,
+            ///  PLLSAI division factor for LCD clock
+            PLLSAIR: u3,
+            padding: u1,
+        }),
+        ///  RCC Dedicated Clock Configuration Register
+        DCKCFGR: mmio.Mmio(packed struct(u32) {
+            ///  PLLI2S division factor for SAI1 clock
+            PLLI2SDIVQ: u5,
+            reserved8: u3,
+            ///  PLLSAI division factor for SAI1 clock
+            PLLSAIDIVQ: u5,
+            reserved16: u3,
+            ///  division factor for LCD_CLK
+            PLLSAIDIVR: u2,
+            reserved20: u2,
+            ///  SAI1-A clock source selection
+            SAI1ASRC: u2,
+            ///  SAI1-B clock source selection
+            SAI1BSRC: u2,
+            ///  Timers clocks prescalers selection
+            TIMPRE: u1,
+            padding: u7,
+        }),
+    };
+
+    ///  General-purpose I/Os
+    pub const GPIOK = extern struct {
+        ///  GPIO port mode register
+        MODER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            MODER0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER15: u2,
+        }),
+        ///  GPIO port output type register
+        OTYPER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OT0: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT1: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT2: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT3: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT4: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT5: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT6: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT7: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT8: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT9: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT10: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT11: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT12: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT13: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT14: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output speed register
+        OSPEEDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR15: u2,
+        }),
+        ///  GPIO port pull-up/pull-down register
+        PUPDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR15: u2,
+        }),
+        ///  GPIO port input data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Port input data (y = 0..15)
+            IDR0: u1,
+            ///  Port input data (y = 0..15)
+            IDR1: u1,
+            ///  Port input data (y = 0..15)
+            IDR2: u1,
+            ///  Port input data (y = 0..15)
+            IDR3: u1,
+            ///  Port input data (y = 0..15)
+            IDR4: u1,
+            ///  Port input data (y = 0..15)
+            IDR5: u1,
+            ///  Port input data (y = 0..15)
+            IDR6: u1,
+            ///  Port input data (y = 0..15)
+            IDR7: u1,
+            ///  Port input data (y = 0..15)
+            IDR8: u1,
+            ///  Port input data (y = 0..15)
+            IDR9: u1,
+            ///  Port input data (y = 0..15)
+            IDR10: u1,
+            ///  Port input data (y = 0..15)
+            IDR11: u1,
+            ///  Port input data (y = 0..15)
+            IDR12: u1,
+            ///  Port input data (y = 0..15)
+            IDR13: u1,
+            ///  Port input data (y = 0..15)
+            IDR14: u1,
+            ///  Port input data (y = 0..15)
+            IDR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output data register
+        ODR: mmio.Mmio(packed struct(u32) {
+            ///  Port output data (y = 0..15)
+            ODR0: u1,
+            ///  Port output data (y = 0..15)
+            ODR1: u1,
+            ///  Port output data (y = 0..15)
+            ODR2: u1,
+            ///  Port output data (y = 0..15)
+            ODR3: u1,
+            ///  Port output data (y = 0..15)
+            ODR4: u1,
+            ///  Port output data (y = 0..15)
+            ODR5: u1,
+            ///  Port output data (y = 0..15)
+            ODR6: u1,
+            ///  Port output data (y = 0..15)
+            ODR7: u1,
+            ///  Port output data (y = 0..15)
+            ODR8: u1,
+            ///  Port output data (y = 0..15)
+            ODR9: u1,
+            ///  Port output data (y = 0..15)
+            ODR10: u1,
+            ///  Port output data (y = 0..15)
+            ODR11: u1,
+            ///  Port output data (y = 0..15)
+            ODR12: u1,
+            ///  Port output data (y = 0..15)
+            ODR13: u1,
+            ///  Port output data (y = 0..15)
+            ODR14: u1,
+            ///  Port output data (y = 0..15)
+            ODR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port bit set/reset register
+        BSRR: mmio.Mmio(packed struct(u32) {
+            ///  Port x set bit y (y= 0..15)
+            BS0: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS1: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS2: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS3: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS4: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS5: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS6: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS7: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS8: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS9: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS10: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS11: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS12: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS13: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS14: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS15: u1,
+            ///  Port x set bit y (y= 0..15)
+            BR0: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR1: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR2: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR3: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR4: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR5: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR6: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR7: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR8: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR9: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR10: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR11: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR12: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR13: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR14: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR15: u1,
+        }),
+        ///  GPIO port configuration lock register
+        LCKR: mmio.Mmio(packed struct(u32) {
+            ///  Port x lock bit y (y= 0..15)
+            LCK0: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK1: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK2: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK3: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK4: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK5: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK6: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK7: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK8: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK9: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK10: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK11: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK12: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK13: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK14: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK15: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCKK: u1,
+            padding: u15,
+        }),
+        ///  GPIO alternate function low register
+        AFRL: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL0: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL1: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL2: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL3: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL4: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL5: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL6: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL7: u4,
+        }),
+        ///  GPIO alternate function high register
+        AFRH: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH8: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH9: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH10: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH11: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH12: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH13: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH14: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH15: u4,
+        }),
+    };
+
+    ///  Floating point unit CPACR
+    pub const FPU_CPACR = extern struct {
+        ///  Coprocessor access control register
+        CPACR: mmio.Mmio(packed struct(u32) {
+            reserved20: u20,
+            ///  CP
+            CP: u4,
+            padding: u8,
+        }),
+    };
+
+    ///  Nested vectored interrupt controller
+    pub const NVIC_STIR = extern struct {
+        ///  Software trigger interrupt register
+        STIR: mmio.Mmio(packed struct(u32) {
+            ///  Software generated interrupt ID
+            INTID: u9,
+            padding: u23,
+        }),
+    };
+
+    ///  System control block
+    pub const SCB = extern struct {
+        ///  CPUID base register
+        CPUID: mmio.Mmio(packed struct(u32) {
+            ///  Revision number
+            Revision: u4,
+            ///  Part number of the processor
+            PartNo: u12,
+            ///  Reads as 0xF
+            Constant: u4,
+            ///  Variant number
+            Variant: u4,
+            ///  Implementer code
+            Implementer: u8,
+        }),
+        ///  Interrupt control and state register
+        ICSR: mmio.Mmio(packed struct(u32) {
+            ///  Active vector
+            VECTACTIVE: u9,
+            reserved11: u2,
+            ///  Return to base level
+            RETTOBASE: u1,
+            ///  Pending vector
+            VECTPENDING: u7,
+            reserved22: u3,
+            ///  Interrupt pending flag
+            ISRPENDING: u1,
+            reserved25: u2,
+            ///  SysTick exception clear-pending bit
+            PENDSTCLR: u1,
+            ///  SysTick exception set-pending bit
+            PENDSTSET: u1,
+            ///  PendSV clear-pending bit
+            PENDSVCLR: u1,
+            ///  PendSV set-pending bit
+            PENDSVSET: u1,
+            reserved31: u2,
+            ///  NMI set-pending bit.
+            NMIPENDSET: u1,
+        }),
+        ///  Vector table offset register
+        VTOR: mmio.Mmio(packed struct(u32) {
+            reserved9: u9,
+            ///  Vector table base offset field
+            TBLOFF: u21,
+            padding: u2,
+        }),
+        ///  Application interrupt and reset control register
+        AIRCR: mmio.Mmio(packed struct(u32) {
+            ///  VECTRESET
+            VECTRESET: u1,
+            ///  VECTCLRACTIVE
+            VECTCLRACTIVE: u1,
+            ///  SYSRESETREQ
+            SYSRESETREQ: u1,
+            reserved8: u5,
+            ///  PRIGROUP
+            PRIGROUP: u3,
+            reserved15: u4,
+            ///  ENDIANESS
+            ENDIANESS: u1,
+            ///  Register key
+            VECTKEYSTAT: u16,
+        }),
+        ///  System control register
+        SCR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  SLEEPONEXIT
+            SLEEPONEXIT: u1,
+            ///  SLEEPDEEP
+            SLEEPDEEP: u1,
+            reserved4: u1,
+            ///  Send Event on Pending bit
+            SEVEONPEND: u1,
+            padding: u27,
+        }),
+        ///  Configuration and control register
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Configures how the processor enters Thread mode
+            NONBASETHRDENA: u1,
+            ///  USERSETMPEND
+            USERSETMPEND: u1,
+            reserved3: u1,
+            ///  UNALIGN_ TRP
+            UNALIGN__TRP: u1,
+            ///  DIV_0_TRP
+            DIV_0_TRP: u1,
+            reserved8: u3,
+            ///  BFHFNMIGN
+            BFHFNMIGN: u1,
+            ///  STKALIGN
+            STKALIGN: u1,
+            padding: u22,
+        }),
+        ///  System handler priority registers
+        SHPR1: mmio.Mmio(packed struct(u32) {
+            ///  Priority of system handler 4
+            PRI_4: u8,
+            ///  Priority of system handler 5
+            PRI_5: u8,
+            ///  Priority of system handler 6
+            PRI_6: u8,
+            padding: u8,
+        }),
+        ///  System handler priority registers
+        SHPR2: mmio.Mmio(packed struct(u32) {
+            reserved24: u24,
+            ///  Priority of system handler 11
+            PRI_11: u8,
+        }),
+        ///  System handler priority registers
+        SHPR3: mmio.Mmio(packed struct(u32) {
+            reserved16: u16,
+            ///  Priority of system handler 14
+            PRI_14: u8,
+            ///  Priority of system handler 15
+            PRI_15: u8,
+        }),
+        ///  System handler control and state register
+        SHCRS: mmio.Mmio(packed struct(u32) {
+            ///  Memory management fault exception active bit
+            MEMFAULTACT: u1,
+            ///  Bus fault exception active bit
+            BUSFAULTACT: u1,
+            reserved3: u1,
+            ///  Usage fault exception active bit
+            USGFAULTACT: u1,
+            reserved7: u3,
+            ///  SVC call active bit
+            SVCALLACT: u1,
+            ///  Debug monitor active bit
+            MONITORACT: u1,
+            reserved10: u1,
+            ///  PendSV exception active bit
+            PENDSVACT: u1,
+            ///  SysTick exception active bit
+            SYSTICKACT: u1,
+            ///  Usage fault exception pending bit
+            USGFAULTPENDED: u1,
+            ///  Memory management fault exception pending bit
+            MEMFAULTPENDED: u1,
+            ///  Bus fault exception pending bit
+            BUSFAULTPENDED: u1,
+            ///  SVC call pending bit
+            SVCALLPENDED: u1,
+            ///  Memory management fault enable bit
+            MEMFAULTENA: u1,
+            ///  Bus fault enable bit
+            BUSFAULTENA: u1,
+            ///  Usage fault enable bit
+            USGFAULTENA: u1,
+            padding: u13,
+        }),
+        ///  Configurable fault status register
+        CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Instruction access violation flag
+            IACCVIOL: u1,
+            reserved3: u1,
+            ///  Memory manager fault on unstacking for a return from exception
+            MUNSTKERR: u1,
+            ///  Memory manager fault on stacking for exception entry.
+            MSTKERR: u1,
+            ///  MLSPERR
+            MLSPERR: u1,
+            reserved7: u1,
+            ///  Memory Management Fault Address Register (MMAR) valid flag
+            MMARVALID: u1,
+            ///  Instruction bus error
+            IBUSERR: u1,
+            ///  Precise data bus error
+            PRECISERR: u1,
+            ///  Imprecise data bus error
+            IMPRECISERR: u1,
+            ///  Bus fault on unstacking for a return from exception
+            UNSTKERR: u1,
+            ///  Bus fault on stacking for exception entry
+            STKERR: u1,
+            ///  Bus fault on floating-point lazy state preservation
+            LSPERR: u1,
+            reserved15: u1,
+            ///  Bus Fault Address Register (BFAR) valid flag
+            BFARVALID: u1,
+            ///  Undefined instruction usage fault
+            UNDEFINSTR: u1,
+            ///  Invalid state usage fault
+            INVSTATE: u1,
+            ///  Invalid PC load usage fault
+            INVPC: u1,
+            ///  No coprocessor usage fault.
+            NOCP: u1,
+            reserved24: u4,
+            ///  Unaligned access usage fault
+            UNALIGNED: u1,
+            ///  Divide by zero usage fault
+            DIVBYZERO: u1,
+            padding: u6,
+        }),
+        ///  Hard fault status register
+        HFSR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Vector table hard fault
+            VECTTBL: u1,
+            reserved30: u28,
+            ///  Forced hard fault
+            FORCED: u1,
+            ///  Reserved for Debug use
+            DEBUG_VT: u1,
+        }),
+        reserved52: [4]u8,
+        ///  Memory management fault address register
+        MMFAR: mmio.Mmio(packed struct(u32) {
+            ///  Memory management fault address
+            MMFAR: u32,
+        }),
+        ///  Bus fault address register
+        BFAR: mmio.Mmio(packed struct(u32) {
+            ///  Bus fault address
+            BFAR: u32,
+        }),
+        ///  Auxiliary fault status register
+        AFSR: mmio.Mmio(packed struct(u32) {
+            ///  Implementation defined
+            IMPDEF: u32,
+        }),
+    };
+
+    ///  SysTick timer
+    pub const STK = extern struct {
+        ///  SysTick control and status register
+        CTRL: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            ENABLE: u1,
+            ///  SysTick exception request enable
+            TICKINT: u1,
+            ///  Clock source selection
+            CLKSOURCE: u1,
+            reserved16: u13,
+            ///  COUNTFLAG
+            COUNTFLAG: u1,
+            padding: u15,
+        }),
+        ///  SysTick reload value register
+        LOAD: mmio.Mmio(packed struct(u32) {
+            ///  RELOAD value
+            RELOAD: u24,
+            padding: u8,
+        }),
+        ///  SysTick current value register
+        VAL: mmio.Mmio(packed struct(u32) {
+            ///  Current counter value
+            CURRENT: u24,
+            padding: u8,
+        }),
+        ///  SysTick calibration value register
+        CALIB: mmio.Mmio(packed struct(u32) {
+            ///  Calibration value
+            TENMS: u24,
+            reserved30: u6,
+            ///  SKEW flag: Indicates whether the TENMS value is exact
+            SKEW: u1,
+            ///  NOREF flag. Reads as zero
+            NOREF: u1,
+        }),
+    };
+
+    ///  Memory protection unit
+    pub const MPU = extern struct {
+        ///  MPU type register
+        MPU_TYPER: mmio.Mmio(packed struct(u32) {
+            ///  Separate flag
+            SEPARATE: u1,
+            reserved8: u7,
+            ///  Number of MPU data regions
+            DREGION: u8,
+            ///  Number of MPU instruction regions
+            IREGION: u8,
+            padding: u8,
+        }),
+        ///  MPU control register
+        MPU_CTRL: mmio.Mmio(packed struct(u32) {
+            ///  Enables the MPU
+            ENABLE: u1,
+            ///  Enables the operation of MPU during hard fault
+            HFNMIENA: u1,
+            ///  Enable priviliged software access to default memory map
+            PRIVDEFENA: u1,
+            padding: u29,
+        }),
+        ///  MPU region number register
+        MPU_RNR: mmio.Mmio(packed struct(u32) {
+            ///  MPU region
+            REGION: u8,
+            padding: u24,
+        }),
+        ///  MPU region base address register
+        MPU_RBAR: mmio.Mmio(packed struct(u32) {
+            ///  MPU region field
+            REGION: u4,
+            ///  MPU region number valid
+            VALID: u1,
+            ///  Region base address field
+            ADDR: u27,
+        }),
+        ///  MPU region attribute and size register
+        MPU_RASR: mmio.Mmio(packed struct(u32) {
+            ///  Region enable bit.
+            ENABLE: u1,
+            ///  Size of the MPU protection region
+            SIZE: u5,
+            reserved8: u2,
+            ///  Subregion disable bits
+            SRD: u8,
+            ///  memory attribute
+            B: u1,
+            ///  memory attribute
+            C: u1,
+            ///  Shareable memory attribute
+            S: u1,
+            ///  memory attribute
+            TEX: u3,
+            reserved24: u2,
+            ///  Access permission
+            AP: u3,
+            reserved28: u1,
+            ///  Instruction access disable bit
+            XN: u1,
+            padding: u3,
+        }),
+    };
+
+    ///  Floting point unit
+    pub const FPU = extern struct {
+        ///  Floating-point context control register
+        FPCCR: mmio.Mmio(packed struct(u32) {
+            ///  LSPACT
+            LSPACT: u1,
+            ///  USER
+            USER: u1,
+            reserved3: u1,
+            ///  THREAD
+            THREAD: u1,
+            ///  HFRDY
+            HFRDY: u1,
+            ///  MMRDY
+            MMRDY: u1,
+            ///  BFRDY
+            BFRDY: u1,
+            reserved8: u1,
+            ///  MONRDY
+            MONRDY: u1,
+            reserved30: u21,
+            ///  LSPEN
+            LSPEN: u1,
+            ///  ASPEN
+            ASPEN: u1,
+        }),
+        ///  Floating-point context address register
+        FPCAR: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Location of unpopulated floating-point
+            ADDRESS: u29,
+        }),
+        ///  Floating-point status control register
+        FPSCR: mmio.Mmio(packed struct(u32) {
+            ///  Invalid operation cumulative exception bit
+            IOC: u1,
+            ///  Division by zero cumulative exception bit.
+            DZC: u1,
+            ///  Overflow cumulative exception bit
+            OFC: u1,
+            ///  Underflow cumulative exception bit
+            UFC: u1,
+            ///  Inexact cumulative exception bit
+            IXC: u1,
+            reserved7: u2,
+            ///  Input denormal cumulative exception bit.
+            IDC: u1,
+            reserved22: u14,
+            ///  Rounding Mode control field
+            RMode: u2,
+            ///  Flush-to-zero mode control bit:
+            FZ: u1,
+            ///  Default NaN mode control bit
+            DN: u1,
+            ///  Alternative half-precision control bit
+            AHP: u1,
+            reserved28: u1,
+            ///  Overflow condition code flag
+            V: u1,
+            ///  Carry condition code flag
+            C: u1,
+            ///  Zero condition code flag
+            Z: u1,
+            ///  Negative condition code flag
+            N: u1,
+        }),
+    };
+
+    ///  Basic timers
+    pub const TIM6 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            reserved7: u3,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            padding: u24,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  Master mode selection
+            MMS: u3,
+            padding: u25,
+        }),
+        reserved12: [4]u8,
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            reserved8: u7,
+            ///  Update DMA request enable
+            UDE: u1,
+            padding: u23,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            padding: u31,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            padding: u31,
+        }),
+        reserved36: [12]u8,
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  Low counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Low Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Ethernet: MAC management counters
+    pub const Ethernet_MMC = extern struct {
+        ///  Ethernet MMC control register
+        MMCCR: mmio.Mmio(packed struct(u32) {
+            ///  CR
+            CR: u1,
+            ///  CSR
+            CSR: u1,
+            ///  ROR
+            ROR: u1,
+            ///  MCF
+            MCF: u1,
+            ///  MCP
+            MCP: u1,
+            ///  MCFHP
+            MCFHP: u1,
+            padding: u26,
+        }),
+        ///  Ethernet MMC receive interrupt register
+        MMCRIR: mmio.Mmio(packed struct(u32) {
+            reserved5: u5,
+            ///  RFCES
+            RFCES: u1,
+            ///  RFAES
+            RFAES: u1,
+            reserved17: u10,
+            ///  RGUFS
+            RGUFS: u1,
+            padding: u14,
+        }),
+        ///  Ethernet MMC transmit interrupt register
+        MMCTIR: mmio.Mmio(packed struct(u32) {
+            reserved14: u14,
+            ///  TGFSCS
+            TGFSCS: u1,
+            ///  TGFMSCS
+            TGFMSCS: u1,
+            reserved21: u5,
+            ///  TGFS
+            TGFS: u1,
+            padding: u10,
+        }),
+        ///  Ethernet MMC receive interrupt mask register
+        MMCRIMR: mmio.Mmio(packed struct(u32) {
+            reserved5: u5,
+            ///  RFCEM
+            RFCEM: u1,
+            ///  RFAEM
+            RFAEM: u1,
+            reserved17: u10,
+            ///  RGUFM
+            RGUFM: u1,
+            padding: u14,
+        }),
+        ///  Ethernet MMC transmit interrupt mask register
+        MMCTIMR: mmio.Mmio(packed struct(u32) {
+            reserved14: u14,
+            ///  TGFSCM
+            TGFSCM: u1,
+            ///  TGFMSCM
+            TGFMSCM: u1,
+            ///  TGFM
+            TGFM: u1,
+            padding: u15,
+        }),
+        reserved76: [56]u8,
+        ///  Ethernet MMC transmitted good frames after a single collision counter
+        MMCTGFSCCR: mmio.Mmio(packed struct(u32) {
+            ///  TGFSCC
+            TGFSCC: u32,
+        }),
+        ///  Ethernet MMC transmitted good frames after more than a single collision
+        MMCTGFMSCCR: mmio.Mmio(packed struct(u32) {
+            ///  TGFMSCC
+            TGFMSCC: u32,
+        }),
+        reserved104: [20]u8,
+        ///  Ethernet MMC transmitted good frames counter register
+        MMCTGFCR: mmio.Mmio(packed struct(u32) {
+            ///  HTL
+            TGFC: u32,
+        }),
+        reserved148: [40]u8,
+        ///  Ethernet MMC received frames with CRC error counter register
+        MMCRFCECR: mmio.Mmio(packed struct(u32) {
+            ///  RFCFC
+            RFCFC: u32,
+        }),
+        ///  Ethernet MMC received frames with alignment error counter register
+        MMCRFAECR: mmio.Mmio(packed struct(u32) {
+            ///  RFAEC
+            RFAEC: u32,
+        }),
+        reserved196: [40]u8,
+        ///  MMC received good unicast frames counter register
+        MMCRGUFCR: mmio.Mmio(packed struct(u32) {
+            ///  RGUFC
+            RGUFC: u32,
+        }),
+    };
+
+    ///  General-purpose I/Os
+    pub const GPIOB = extern struct {
+        ///  GPIO port mode register
+        MODER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            MODER0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER15: u2,
+        }),
+        ///  GPIO port output type register
+        OTYPER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OT0: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT1: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT2: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT3: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT4: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT5: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT6: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT7: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT8: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT9: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT10: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT11: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT12: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT13: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT14: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output speed register
+        OSPEEDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR15: u2,
+        }),
+        ///  GPIO port pull-up/pull-down register
+        PUPDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR15: u2,
+        }),
+        ///  GPIO port input data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Port input data (y = 0..15)
+            IDR0: u1,
+            ///  Port input data (y = 0..15)
+            IDR1: u1,
+            ///  Port input data (y = 0..15)
+            IDR2: u1,
+            ///  Port input data (y = 0..15)
+            IDR3: u1,
+            ///  Port input data (y = 0..15)
+            IDR4: u1,
+            ///  Port input data (y = 0..15)
+            IDR5: u1,
+            ///  Port input data (y = 0..15)
+            IDR6: u1,
+            ///  Port input data (y = 0..15)
+            IDR7: u1,
+            ///  Port input data (y = 0..15)
+            IDR8: u1,
+            ///  Port input data (y = 0..15)
+            IDR9: u1,
+            ///  Port input data (y = 0..15)
+            IDR10: u1,
+            ///  Port input data (y = 0..15)
+            IDR11: u1,
+            ///  Port input data (y = 0..15)
+            IDR12: u1,
+            ///  Port input data (y = 0..15)
+            IDR13: u1,
+            ///  Port input data (y = 0..15)
+            IDR14: u1,
+            ///  Port input data (y = 0..15)
+            IDR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output data register
+        ODR: mmio.Mmio(packed struct(u32) {
+            ///  Port output data (y = 0..15)
+            ODR0: u1,
+            ///  Port output data (y = 0..15)
+            ODR1: u1,
+            ///  Port output data (y = 0..15)
+            ODR2: u1,
+            ///  Port output data (y = 0..15)
+            ODR3: u1,
+            ///  Port output data (y = 0..15)
+            ODR4: u1,
+            ///  Port output data (y = 0..15)
+            ODR5: u1,
+            ///  Port output data (y = 0..15)
+            ODR6: u1,
+            ///  Port output data (y = 0..15)
+            ODR7: u1,
+            ///  Port output data (y = 0..15)
+            ODR8: u1,
+            ///  Port output data (y = 0..15)
+            ODR9: u1,
+            ///  Port output data (y = 0..15)
+            ODR10: u1,
+            ///  Port output data (y = 0..15)
+            ODR11: u1,
+            ///  Port output data (y = 0..15)
+            ODR12: u1,
+            ///  Port output data (y = 0..15)
+            ODR13: u1,
+            ///  Port output data (y = 0..15)
+            ODR14: u1,
+            ///  Port output data (y = 0..15)
+            ODR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port bit set/reset register
+        BSRR: mmio.Mmio(packed struct(u32) {
+            ///  Port x set bit y (y= 0..15)
+            BS0: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS1: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS2: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS3: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS4: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS5: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS6: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS7: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS8: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS9: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS10: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS11: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS12: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS13: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS14: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS15: u1,
+            ///  Port x set bit y (y= 0..15)
+            BR0: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR1: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR2: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR3: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR4: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR5: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR6: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR7: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR8: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR9: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR10: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR11: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR12: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR13: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR14: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR15: u1,
+        }),
+        ///  GPIO port configuration lock register
+        LCKR: mmio.Mmio(packed struct(u32) {
+            ///  Port x lock bit y (y= 0..15)
+            LCK0: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK1: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK2: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK3: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK4: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK5: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK6: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK7: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK8: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK9: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK10: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK11: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK12: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK13: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK14: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK15: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCKK: u1,
+            padding: u15,
+        }),
+        ///  GPIO alternate function low register
+        AFRL: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL0: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL1: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL2: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL3: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL4: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL5: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL6: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL7: u4,
+        }),
+        ///  GPIO alternate function high register
+        AFRH: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH8: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH9: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH10: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH11: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH12: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH13: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH14: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH15: u4,
+        }),
+    };
+
+    ///  General-purpose I/Os
+    pub const GPIOA = extern struct {
+        ///  GPIO port mode register
+        MODER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            MODER0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            MODER15: u2,
+        }),
+        ///  GPIO port output type register
+        OTYPER: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OT0: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT1: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT2: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT3: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT4: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT5: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT6: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT7: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT8: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT9: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT10: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT11: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT12: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT13: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT14: u1,
+            ///  Port x configuration bits (y = 0..15)
+            OT15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output speed register
+        OSPEEDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            OSPEEDR15: u2,
+        }),
+        ///  GPIO port pull-up/pull-down register
+        PUPDR: mmio.Mmio(packed struct(u32) {
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR0: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR1: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR2: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR3: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR4: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR5: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR6: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR7: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR8: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR9: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR10: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR11: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR12: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR13: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR14: u2,
+            ///  Port x configuration bits (y = 0..15)
+            PUPDR15: u2,
+        }),
+        ///  GPIO port input data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Port input data (y = 0..15)
+            IDR0: u1,
+            ///  Port input data (y = 0..15)
+            IDR1: u1,
+            ///  Port input data (y = 0..15)
+            IDR2: u1,
+            ///  Port input data (y = 0..15)
+            IDR3: u1,
+            ///  Port input data (y = 0..15)
+            IDR4: u1,
+            ///  Port input data (y = 0..15)
+            IDR5: u1,
+            ///  Port input data (y = 0..15)
+            IDR6: u1,
+            ///  Port input data (y = 0..15)
+            IDR7: u1,
+            ///  Port input data (y = 0..15)
+            IDR8: u1,
+            ///  Port input data (y = 0..15)
+            IDR9: u1,
+            ///  Port input data (y = 0..15)
+            IDR10: u1,
+            ///  Port input data (y = 0..15)
+            IDR11: u1,
+            ///  Port input data (y = 0..15)
+            IDR12: u1,
+            ///  Port input data (y = 0..15)
+            IDR13: u1,
+            ///  Port input data (y = 0..15)
+            IDR14: u1,
+            ///  Port input data (y = 0..15)
+            IDR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port output data register
+        ODR: mmio.Mmio(packed struct(u32) {
+            ///  Port output data (y = 0..15)
+            ODR0: u1,
+            ///  Port output data (y = 0..15)
+            ODR1: u1,
+            ///  Port output data (y = 0..15)
+            ODR2: u1,
+            ///  Port output data (y = 0..15)
+            ODR3: u1,
+            ///  Port output data (y = 0..15)
+            ODR4: u1,
+            ///  Port output data (y = 0..15)
+            ODR5: u1,
+            ///  Port output data (y = 0..15)
+            ODR6: u1,
+            ///  Port output data (y = 0..15)
+            ODR7: u1,
+            ///  Port output data (y = 0..15)
+            ODR8: u1,
+            ///  Port output data (y = 0..15)
+            ODR9: u1,
+            ///  Port output data (y = 0..15)
+            ODR10: u1,
+            ///  Port output data (y = 0..15)
+            ODR11: u1,
+            ///  Port output data (y = 0..15)
+            ODR12: u1,
+            ///  Port output data (y = 0..15)
+            ODR13: u1,
+            ///  Port output data (y = 0..15)
+            ODR14: u1,
+            ///  Port output data (y = 0..15)
+            ODR15: u1,
+            padding: u16,
+        }),
+        ///  GPIO port bit set/reset register
+        BSRR: mmio.Mmio(packed struct(u32) {
+            ///  Port x set bit y (y= 0..15)
+            BS0: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS1: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS2: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS3: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS4: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS5: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS6: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS7: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS8: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS9: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS10: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS11: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS12: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS13: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS14: u1,
+            ///  Port x set bit y (y= 0..15)
+            BS15: u1,
+            ///  Port x set bit y (y= 0..15)
+            BR0: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR1: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR2: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR3: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR4: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR5: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR6: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR7: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR8: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR9: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR10: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR11: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR12: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR13: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR14: u1,
+            ///  Port x reset bit y (y = 0..15)
+            BR15: u1,
+        }),
+        ///  GPIO port configuration lock register
+        LCKR: mmio.Mmio(packed struct(u32) {
+            ///  Port x lock bit y (y= 0..15)
+            LCK0: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK1: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK2: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK3: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK4: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK5: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK6: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK7: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK8: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK9: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK10: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK11: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK12: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK13: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK14: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCK15: u1,
+            ///  Port x lock bit y (y= 0..15)
+            LCKK: u1,
+            padding: u15,
+        }),
+        ///  GPIO alternate function low register
+        AFRL: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL0: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL1: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL2: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL3: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL4: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL5: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL6: u4,
+            ///  Alternate function selection for port x bit y (y = 0..7)
+            AFRL7: u4,
+        }),
+        ///  GPIO alternate function high register
+        AFRH: mmio.Mmio(packed struct(u32) {
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH8: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH9: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH10: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH11: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH12: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH13: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH14: u4,
+            ///  Alternate function selection for port x bit y (y = 8..15)
+            AFRH15: u4,
+        }),
+    };
+
+    ///  System configuration controller
+    pub const SYSCFG = extern struct {
+        ///  memory remap register
+        MEMRM: mmio.Mmio(packed struct(u32) {
+            ///  Memory mapping selection
+            MEM_MODE: u3,
+            reserved8: u5,
+            ///  Flash bank mode selection
+            FB_MODE: u1,
+            reserved10: u1,
+            ///  FMC memory mapping swap
+            SWP_FMC: u2,
+            padding: u20,
+        }),
+        ///  peripheral mode configuration register
+        PMC: mmio.Mmio(packed struct(u32) {
+            reserved16: u16,
+            ///  ADC1DC2
+            ADC1DC2: u1,
+            ///  ADC2DC2
+            ADC2DC2: u1,
+            ///  ADC3DC2
+            ADC3DC2: u1,
+            reserved23: u4,
+            ///  Ethernet PHY interface selection
+            MII_RMII_SEL: u1,
+            padding: u8,
+        }),
+        ///  external interrupt configuration register 1
+        EXTICR1: mmio.Mmio(packed struct(u32) {
+            ///  EXTI x configuration (x = 0 to 3)
+            EXTI0: u4,
+            ///  EXTI x configuration (x = 0 to 3)
+            EXTI1: u4,
+            ///  EXTI x configuration (x = 0 to 3)
+            EXTI2: u4,
+            ///  EXTI x configuration (x = 0 to 3)
+            EXTI3: u4,
+            padding: u16,
+        }),
+        ///  external interrupt configuration register 2
+        EXTICR2: mmio.Mmio(packed struct(u32) {
+            ///  EXTI x configuration (x = 4 to 7)
+            EXTI4: u4,
+            ///  EXTI x configuration (x = 4 to 7)
+            EXTI5: u4,
+            ///  EXTI x configuration (x = 4 to 7)
+            EXTI6: u4,
+            ///  EXTI x configuration (x = 4 to 7)
+            EXTI7: u4,
+            padding: u16,
+        }),
+        ///  external interrupt configuration register 3
+        EXTICR3: mmio.Mmio(packed struct(u32) {
+            ///  EXTI x configuration (x = 8 to 11)
+            EXTI8: u4,
+            ///  EXTI x configuration (x = 8 to 11)
+            EXTI9: u4,
+            ///  EXTI10
+            EXTI10: u4,
+            ///  EXTI x configuration (x = 8 to 11)
+            EXTI11: u4,
+            padding: u16,
+        }),
+        ///  external interrupt configuration register 4
+        EXTICR4: mmio.Mmio(packed struct(u32) {
+            ///  EXTI x configuration (x = 12 to 15)
+            EXTI12: u4,
+            ///  EXTI x configuration (x = 12 to 15)
+            EXTI13: u4,
+            ///  EXTI x configuration (x = 12 to 15)
+            EXTI14: u4,
+            ///  EXTI x configuration (x = 12 to 15)
+            EXTI15: u4,
+            padding: u16,
+        }),
+        reserved32: [8]u8,
+        ///  Compensation cell control register
+        CMPCR: mmio.Mmio(packed struct(u32) {
+            ///  Compensation cell power-down
+            CMP_PD: u1,
+            reserved8: u7,
+            ///  READY
+            READY: u1,
+            padding: u23,
+        }),
+    };
+
+    ///  Serial peripheral interface
+    pub const SPI1 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Clock phase
+            CPHA: u1,
+            ///  Clock polarity
+            CPOL: u1,
+            ///  Master selection
+            MSTR: u1,
+            ///  Baud rate control
+            BR: u3,
+            ///  SPI enable
+            SPE: u1,
+            ///  Frame format
+            LSBFIRST: u1,
+            ///  Internal slave select
+            SSI: u1,
+            ///  Software slave management
+            SSM: u1,
+            ///  Receive only
+            RXONLY: u1,
+            ///  Data frame format
+            DFF: u1,
+            ///  CRC transfer next
+            CRCNEXT: u1,
+            ///  Hardware CRC calculation enable
+            CRCEN: u1,
+            ///  Output enable in bidirectional mode
+            BIDIOE: u1,
+            ///  Bidirectional data mode enable
+            BIDIMODE: u1,
+            padding: u16,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Rx buffer DMA enable
+            RXDMAEN: u1,
+            ///  Tx buffer DMA enable
+            TXDMAEN: u1,
+            ///  SS output enable
+            SSOE: u1,
+            reserved4: u1,
+            ///  Frame format
+            FRF: u1,
+            ///  Error interrupt enable
+            ERRIE: u1,
+            ///  RX buffer not empty interrupt enable
+            RXNEIE: u1,
+            ///  Tx buffer empty interrupt enable
+            TXEIE: u1,
+            padding: u24,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Receive buffer not empty
+            RXNE: u1,
+            ///  Transmit buffer empty
+            TXE: u1,
+            ///  Channel side
+            CHSIDE: u1,
+            ///  Underrun flag
+            UDR: u1,
+            ///  CRC error flag
+            CRCERR: u1,
+            ///  Mode fault
+            MODF: u1,
+            ///  Overrun flag
+            OVR: u1,
+            ///  Busy flag
+            BSY: u1,
+            ///  TI frame format error
+            TIFRFE: u1,
+            padding: u23,
+        }),
+        ///  data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data register
+            DR: u16,
+            padding: u16,
+        }),
+        ///  CRC polynomial register
+        CRCPR: mmio.Mmio(packed struct(u32) {
+            ///  CRC polynomial register
+            CRCPOLY: u16,
+            padding: u16,
+        }),
+        ///  RX CRC register
+        RXCRCR: mmio.Mmio(packed struct(u32) {
+            ///  Rx CRC register
+            RxCRC: u16,
+            padding: u16,
+        }),
+        ///  TX CRC register
+        TXCRCR: mmio.Mmio(packed struct(u32) {
+            ///  Tx CRC register
+            TxCRC: u16,
+            padding: u16,
+        }),
+        ///  I2S configuration register
+        I2SCFGR: mmio.Mmio(packed struct(u32) {
+            ///  Channel length (number of bits per audio channel)
+            CHLEN: u1,
+            ///  Data length to be transferred
+            DATLEN: u2,
+            ///  Steady state clock polarity
+            CKPOL: u1,
+            ///  I2S standard selection
+            I2SSTD: u2,
+            reserved7: u1,
+            ///  PCM frame synchronization
+            PCMSYNC: u1,
+            ///  I2S configuration mode
+            I2SCFG: u2,
+            ///  I2S Enable
+            I2SE: u1,
+            ///  I2S mode selection
+            I2SMOD: u1,
+            padding: u20,
+        }),
+        ///  I2S prescaler register
+        I2SPR: mmio.Mmio(packed struct(u32) {
+            ///  I2S Linear prescaler
+            I2SDIV: u8,
+            ///  Odd factor for the prescaler
+            ODD: u1,
+            ///  Master clock output enable
+            MCKOE: u1,
+            padding: u22,
+        }),
+    };
+
+    ///  Inter-integrated circuit
+    pub const I2C3 = extern struct {
+        ///  Control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral enable
+            PE: u1,
+            ///  SMBus mode
+            SMBUS: u1,
+            reserved3: u1,
+            ///  SMBus type
+            SMBTYPE: u1,
+            ///  ARP enable
+            ENARP: u1,
+            ///  PEC enable
+            ENPEC: u1,
+            ///  General call enable
+            ENGC: u1,
+            ///  Clock stretching disable (Slave mode)
+            NOSTRETCH: u1,
+            ///  Start generation
+            START: u1,
+            ///  Stop generation
+            STOP: u1,
+            ///  Acknowledge enable
+            ACK: u1,
+            ///  Acknowledge/PEC Position (for data reception)
+            POS: u1,
+            ///  Packet error checking
+            PEC: u1,
+            ///  SMBus alert
+            ALERT: u1,
+            reserved15: u1,
+            ///  Software reset
+            SWRST: u1,
+            padding: u16,
+        }),
+        ///  Control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral clock frequency
+            FREQ: u6,
+            reserved8: u2,
+            ///  Error interrupt enable
+            ITERREN: u1,
+            ///  Event interrupt enable
+            ITEVTEN: u1,
+            ///  Buffer interrupt enable
+            ITBUFEN: u1,
+            ///  DMA requests enable
+            DMAEN: u1,
+            ///  DMA last transfer
+            LAST: u1,
+            padding: u19,
+        }),
+        ///  Own address register 1
+        OAR1: mmio.Mmio(packed struct(u32) {
+            ///  Interface address
+            ADD0: u1,
+            ///  Interface address
+            ADD7: u7,
+            ///  Interface address
+            ADD10: u2,
+            reserved15: u5,
+            ///  Addressing mode (slave mode)
+            ADDMODE: u1,
+            padding: u16,
+        }),
+        ///  Own address register 2
+        OAR2: mmio.Mmio(packed struct(u32) {
+            ///  Dual addressing mode enable
+            ENDUAL: u1,
+            ///  Interface address
+            ADD2: u7,
+            padding: u24,
+        }),
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  8-bit data register
+            DR: u8,
+            padding: u24,
+        }),
+        ///  Status register 1
+        SR1: mmio.Mmio(packed struct(u32) {
+            ///  Start bit (Master mode)
+            SB: u1,
+            ///  Address sent (master mode)/matched (slave mode)
+            ADDR: u1,
+            ///  Byte transfer finished
+            BTF: u1,
+            ///  10-bit header sent (Master mode)
+            ADD10: u1,
+            ///  Stop detection (slave mode)
+            STOPF: u1,
+            reserved6: u1,
+            ///  Data register not empty (receivers)
+            RxNE: u1,
+            ///  Data register empty (transmitters)
+            TxE: u1,
+            ///  Bus error
+            BERR: u1,
+            ///  Arbitration lost (master mode)
+            ARLO: u1,
+            ///  Acknowledge failure
+            AF: u1,
+            ///  Overrun/Underrun
+            OVR: u1,
+            ///  PEC Error in reception
+            PECERR: u1,
+            reserved14: u1,
+            ///  Timeout or Tlow error
+            TIMEOUT: u1,
+            ///  SMBus alert
+            SMBALERT: u1,
+            padding: u16,
+        }),
+        ///  Status register 2
+        SR2: mmio.Mmio(packed struct(u32) {
+            ///  Master/slave
+            MSL: u1,
+            ///  Bus busy
+            BUSY: u1,
+            ///  Transmitter/receiver
+            TRA: u1,
+            reserved4: u1,
+            ///  General call address (Slave mode)
+            GENCALL: u1,
+            ///  SMBus device default address (Slave mode)
+            SMBDEFAULT: u1,
+            ///  SMBus host header (Slave mode)
+            SMBHOST: u1,
+            ///  Dual flag (Slave mode)
+            DUALF: u1,
+            ///  acket error checking register
+            PEC: u8,
+            padding: u16,
+        }),
+        ///  Clock control register
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Clock control register in Fast/Standard mode (Master mode)
+            CCR: u12,
+            reserved14: u2,
+            ///  Fast mode duty cycle
+            DUTY: u1,
+            ///  I2C master mode selection
+            F_S: u1,
+            padding: u16,
+        }),
+        ///  TRISE register
+        TRISE: mmio.Mmio(packed struct(u32) {
+            ///  Maximum rise time in Fast/Standard mode (Master mode)
+            TRISE: u6,
+            padding: u26,
+        }),
+        ///  I2C FLTR register
+        FLTR: mmio.Mmio(packed struct(u32) {
+            ///  Digital noise filter
+            DNF: u4,
+            ///  Analog noise filter OFF
+            ANOFF: u1,
+            padding: u27,
+        }),
+    };
+
+    ///  DMA2D controller
+    pub const DMA2D = extern struct {
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Start
+            START: u1,
+            ///  Suspend
+            SUSP: u1,
+            ///  Abort
+            ABORT: u1,
+            reserved8: u5,
+            ///  Transfer error interrupt enable
+            TEIE: u1,
+            ///  Transfer complete interrupt enable
+            TCIE: u1,
+            ///  Transfer watermark interrupt enable
+            TWIE: u1,
+            ///  CLUT access error interrupt enable
+            CAEIE: u1,
+            ///  CLUT transfer complete interrupt enable
+            CTCIE: u1,
+            ///  Configuration Error Interrupt Enable
+            CEIE: u1,
+            reserved16: u2,
+            ///  DMA2D mode
+            MODE: u2,
+            padding: u14,
+        }),
+        ///  Interrupt Status Register
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  Transfer error interrupt flag
+            TEIF: u1,
+            ///  Transfer complete interrupt flag
+            TCIF: u1,
+            ///  Transfer watermark interrupt flag
+            TWIF: u1,
+            ///  CLUT access error interrupt flag
+            CAEIF: u1,
+            ///  CLUT transfer complete interrupt flag
+            CTCIF: u1,
+            ///  Configuration error interrupt flag
+            CEIF: u1,
+            padding: u26,
+        }),
+        ///  interrupt flag clear register
+        IFCR: mmio.Mmio(packed struct(u32) {
+            ///  Clear Transfer error interrupt flag
+            CTEIF: u1,
+            ///  Clear transfer complete interrupt flag
+            CTCIF: u1,
+            ///  Clear transfer watermark interrupt flag
+            CTWIF: u1,
+            ///  Clear CLUT access error interrupt flag
+            CAECIF: u1,
+            ///  Clear CLUT transfer complete interrupt flag
+            CCTCIF: u1,
+            ///  Clear configuration error interrupt flag
+            CCEIF: u1,
+            padding: u26,
+        }),
+        ///  foreground memory address register
+        FGMAR: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        ///  foreground offset register
+        FGOR: mmio.Mmio(packed struct(u32) {
+            ///  Line offset
+            LO: u14,
+            padding: u18,
+        }),
+        ///  background memory address register
+        BGMAR: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        ///  background offset register
+        BGOR: mmio.Mmio(packed struct(u32) {
+            ///  Line offset
+            LO: u14,
+            padding: u18,
+        }),
+        ///  foreground PFC control register
+        FGPFCCR: mmio.Mmio(packed struct(u32) {
+            ///  Color mode
+            CM: u4,
+            ///  CLUT color mode
+            CCM: u1,
+            ///  Start
+            START: u1,
+            reserved8: u2,
+            ///  CLUT size
+            CS: u8,
+            ///  Alpha mode
+            AM: u2,
+            reserved24: u6,
+            ///  Alpha value
+            ALPHA: u8,
+        }),
+        ///  foreground color register
+        FGCOLR: mmio.Mmio(packed struct(u32) {
+            ///  Blue Value
+            BLUE: u8,
+            ///  Green Value
+            GREEN: u8,
+            ///  Red Value
+            RED: u8,
+            padding: u8,
+        }),
+        ///  background PFC control register
+        BGPFCCR: mmio.Mmio(packed struct(u32) {
+            ///  Color mode
+            CM: u4,
+            ///  CLUT Color mode
+            CCM: u1,
+            ///  Start
+            START: u1,
+            reserved8: u2,
+            ///  CLUT size
+            CS: u8,
+            ///  Alpha mode
+            AM: u2,
+            reserved24: u6,
+            ///  Alpha value
+            ALPHA: u8,
+        }),
+        ///  background color register
+        BGCOLR: mmio.Mmio(packed struct(u32) {
+            ///  Blue Value
+            BLUE: u8,
+            ///  Green Value
+            GREEN: u8,
+            ///  Red Value
+            RED: u8,
+            padding: u8,
+        }),
+        ///  foreground CLUT memory address register
+        FGCMAR: mmio.Mmio(packed struct(u32) {
+            ///  Memory Address
+            MA: u32,
+        }),
+        ///  background CLUT memory address register
+        BGCMAR: mmio.Mmio(packed struct(u32) {
+            ///  Memory address
+            MA: u32,
+        }),
+        ///  output PFC control register
+        OPFCCR: mmio.Mmio(packed struct(u32) {
+            ///  Color mode
+            CM: u3,
+            padding: u29,
+        }),
+        ///  output color register
+        OCOLR: mmio.Mmio(packed struct(u32) {
+            ///  Blue Value
+            BLUE: u8,
+            ///  Green Value
+            GREEN: u8,
+            ///  Red Value
+            RED: u8,
+            ///  Alpha Channel Value
+            APLHA: u8,
+        }),
+        ///  output memory address register
+        OMAR: mmio.Mmio(packed struct(u32) {
+            ///  Memory Address
+            MA: u32,
+        }),
+        ///  output offset register
+        OOR: mmio.Mmio(packed struct(u32) {
+            ///  Line Offset
+            LO: u14,
+            padding: u18,
+        }),
+        ///  number of line register
+        NLR: mmio.Mmio(packed struct(u32) {
+            ///  Number of lines
+            NL: u16,
+            ///  Pixel per lines
+            PL: u14,
+            padding: u2,
+        }),
+        ///  line watermark register
+        LWR: mmio.Mmio(packed struct(u32) {
+            ///  Line watermark
+            LW: u16,
+            padding: u16,
+        }),
+        ///  AHB master timer configuration register
+        AMTCR: mmio.Mmio(packed struct(u32) {
+            ///  Enable
+            EN: u1,
+            reserved8: u7,
+            ///  Dead Time
+            DT: u8,
+            padding: u16,
+        }),
+        reserved1024: [944]u8,
+        ///  FGCLUT
+        FGCLUT: mmio.Mmio(packed struct(u32) {
+            ///  BLUE
+            BLUE: u8,
+            ///  GREEN
+            GREEN: u8,
+            ///  RED
+            RED: u8,
+            ///  APLHA
+            APLHA: u8,
+        }),
+        reserved2048: [1020]u8,
+        ///  BGCLUT
+        BGCLUT: mmio.Mmio(packed struct(u32) {
+            ///  BLUE
+            BLUE: u8,
+            ///  GREEN
+            GREEN: u8,
+            ///  RED
+            RED: u8,
+            ///  APLHA
+            APLHA: u8,
+        }),
+    };
+
+    ///  Serial audio interface
+    pub const SAI = extern struct {
+        reserved4: [4]u8,
+        ///  AConfiguration register 1
+        ACR1: mmio.Mmio(packed struct(u32) {
+            ///  Audio block mode
+            MODE: u2,
+            ///  Protocol configuration
+            PRTCFG: u2,
+            reserved5: u1,
+            ///  Data size
+            DS: u3,
+            ///  Least significant bit first
+            LSBFIRST: u1,
+            ///  Clock strobing edge
+            CKSTR: u1,
+            ///  Synchronization enable
+            SYNCEN: u2,
+            ///  Mono mode
+            MONO: u1,
+            ///  Output drive
+            OutDri: u1,
+            reserved16: u2,
+            ///  Audio block A enable
+            SAIAEN: u1,
+            ///  DMA enable
+            DMAEN: u1,
+            reserved19: u1,
+            ///  No divider
+            NODIV: u1,
+            ///  Master clock divider
+            MCJDIV: u4,
+            padding: u8,
+        }),
+        ///  AConfiguration register 2
+        ACR2: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold
+            FTH: u3,
+            ///  FIFO flush
+            FFLUS: u1,
+            ///  Tristate management on data line
+            TRIS: u1,
+            ///  Mute
+            MUTE: u1,
+            ///  Mute value
+            MUTEVAL: u1,
+            ///  Mute counter
+            MUTECN: u6,
+            ///  Complement bit
+            CPL: u1,
+            ///  Companding mode
+            COMP: u2,
+            padding: u16,
+        }),
+        ///  AFRCR
+        AFRCR: mmio.Mmio(packed struct(u32) {
+            ///  Frame length
+            FRL: u8,
+            ///  Frame synchronization active level length
+            FSALL: u7,
+            reserved16: u1,
+            ///  Frame synchronization definition
+            FSDEF: u1,
+            ///  Frame synchronization polarity
+            FSPOL: u1,
+            ///  Frame synchronization offset
+            FSOFF: u1,
+            padding: u13,
+        }),
+        ///  ASlot register
+        ASLOTR: mmio.Mmio(packed struct(u32) {
+            ///  First bit offset
+            FBOFF: u5,
+            reserved6: u1,
+            ///  Slot size
+            SLOTSZ: u2,
+            ///  Number of slots in an audio frame
+            NBSLOT: u4,
+            reserved16: u4,
+            ///  Slot enable
+            SLOTEN: u16,
+        }),
+        ///  AInterrupt mask register2
+        AIM: mmio.Mmio(packed struct(u32) {
+            ///  Overrun/underrun interrupt enable
+            OVRUDRIE: u1,
+            ///  Mute detection interrupt enable
+            MUTEDET: u1,
+            ///  Wrong clock configuration interrupt enable
+            WCKCFG: u1,
+            ///  FIFO request interrupt enable
+            FREQIE: u1,
+            ///  Codec not ready interrupt enable
+            CNRDYIE: u1,
+            ///  Anticipated frame synchronization detection interrupt enable
+            AFSDETIE: u1,
+            ///  Late frame synchronization detection interrupt enable
+            LFSDET: u1,
+            padding: u25,
+        }),
+        ///  AStatus register
+        ASR: mmio.Mmio(packed struct(u32) {
+            ///  Overrun / underrun
+            OVRUDR: u1,
+            ///  Mute detection
+            MUTEDET: u1,
+            ///  Wrong clock configuration flag. This bit is read only.
+            WCKCFG: u1,
+            ///  FIFO request
+            FREQ: u1,
+            ///  Codec not ready
+            CNRDY: u1,
+            ///  Anticipated frame synchronization detection
+            AFSDET: u1,
+            ///  Late frame synchronization detection
+            LFSDET: u1,
+            reserved16: u9,
+            ///  FIFO level threshold
+            FLVL: u3,
+            padding: u13,
+        }),
+        ///  AClear flag register
+        ACLRFR: mmio.Mmio(packed struct(u32) {
+            ///  Clear overrun / underrun
+            OVRUDR: u1,
+            ///  Mute detection flag
+            MUTEDET: u1,
+            ///  Clear wrong clock configuration flag
+            WCKCFG: u1,
+            reserved4: u1,
+            ///  Clear codec not ready flag
+            CNRDY: u1,
+            ///  Clear anticipated frame synchronization detection flag.
+            CAFSDET: u1,
+            ///  Clear late frame synchronization detection flag
+            LFSDET: u1,
+            padding: u25,
+        }),
+        ///  AData register
+        ADR: mmio.Mmio(packed struct(u32) {
+            ///  Data
+            DATA: u32,
+        }),
+        ///  BConfiguration register 1
+        BCR1: mmio.Mmio(packed struct(u32) {
+            ///  Audio block mode
+            MODE: u2,
+            ///  Protocol configuration
+            PRTCFG: u2,
+            reserved5: u1,
+            ///  Data size
+            DS: u3,
+            ///  Least significant bit first
+            LSBFIRST: u1,
+            ///  Clock strobing edge
+            CKSTR: u1,
+            ///  Synchronization enable
+            SYNCEN: u2,
+            ///  Mono mode
+            MONO: u1,
+            ///  Output drive
+            OutDri: u1,
+            reserved16: u2,
+            ///  Audio block B enable
+            SAIBEN: u1,
+            ///  DMA enable
+            DMAEN: u1,
+            reserved19: u1,
+            ///  No divider
+            NODIV: u1,
+            ///  Master clock divider
+            MCJDIV: u4,
+            padding: u8,
+        }),
+        ///  BConfiguration register 2
+        BCR2: mmio.Mmio(packed struct(u32) {
+            ///  FIFO threshold
+            FTH: u3,
+            ///  FIFO flush
+            FFLUS: u1,
+            ///  Tristate management on data line
+            TRIS: u1,
+            ///  Mute
+            MUTE: u1,
+            ///  Mute value
+            MUTEVAL: u1,
+            ///  Mute counter
+            MUTECN: u6,
+            ///  Complement bit
+            CPL: u1,
+            ///  Companding mode
+            COMP: u2,
+            padding: u16,
+        }),
+        ///  BFRCR
+        BFRCR: mmio.Mmio(packed struct(u32) {
+            ///  Frame length
+            FRL: u8,
+            ///  Frame synchronization active level length
+            FSALL: u7,
+            reserved16: u1,
+            ///  Frame synchronization definition
+            FSDEF: u1,
+            ///  Frame synchronization polarity
+            FSPOL: u1,
+            ///  Frame synchronization offset
+            FSOFF: u1,
+            padding: u13,
+        }),
+        ///  BSlot register
+        BSLOTR: mmio.Mmio(packed struct(u32) {
+            ///  First bit offset
+            FBOFF: u5,
+            reserved6: u1,
+            ///  Slot size
+            SLOTSZ: u2,
+            ///  Number of slots in an audio frame
+            NBSLOT: u4,
+            reserved16: u4,
+            ///  Slot enable
+            SLOTEN: u16,
+        }),
+        ///  BInterrupt mask register2
+        BIM: mmio.Mmio(packed struct(u32) {
+            ///  Overrun/underrun interrupt enable
+            OVRUDRIE: u1,
+            ///  Mute detection interrupt enable
+            MUTEDET: u1,
+            ///  Wrong clock configuration interrupt enable
+            WCKCFG: u1,
+            ///  FIFO request interrupt enable
+            FREQIE: u1,
+            ///  Codec not ready interrupt enable
+            CNRDYIE: u1,
+            ///  Anticipated frame synchronization detection interrupt enable
+            AFSDETIE: u1,
+            ///  Late frame synchronization detection interrupt enable
+            LFSDETIE: u1,
+            padding: u25,
+        }),
+        ///  BStatus register
+        BSR: mmio.Mmio(packed struct(u32) {
+            ///  Overrun / underrun
+            OVRUDR: u1,
+            ///  Mute detection
+            MUTEDET: u1,
+            ///  Wrong clock configuration flag
+            WCKCFG: u1,
+            ///  FIFO request
+            FREQ: u1,
+            ///  Codec not ready
+            CNRDY: u1,
+            ///  Anticipated frame synchronization detection
+            AFSDET: u1,
+            ///  Late frame synchronization detection
+            LFSDET: u1,
+            reserved16: u9,
+            ///  FIFO level threshold
+            FLVL: u3,
+            padding: u13,
+        }),
+        ///  BClear flag register
+        BCLRFR: mmio.Mmio(packed struct(u32) {
+            ///  Clear overrun / underrun
+            OVRUDR: u1,
+            ///  Mute detection flag
+            MUTEDET: u1,
+            ///  Clear wrong clock configuration flag
+            WCKCFG: u1,
+            reserved4: u1,
+            ///  Clear codec not ready flag
+            CNRDY: u1,
+            ///  Clear anticipated frame synchronization detection flag
+            CAFSDET: u1,
+            ///  Clear late frame synchronization detection flag
+            LFSDET: u1,
+            padding: u25,
+        }),
+        ///  BData register
+        BDR: mmio.Mmio(packed struct(u32) {
+            ///  Data
+            DATA: u32,
+        }),
+    };
+
+    ///  LCD-TFT Controller
+    pub const LTDC = extern struct {
+        reserved8: [8]u8,
+        ///  Synchronization Size Configuration Register
+        SSCR: mmio.Mmio(packed struct(u32) {
+            ///  Vertical Synchronization Height (in units of horizontal scan line)
+            VSH: u11,
+            reserved16: u5,
+            ///  Horizontal Synchronization Width (in units of pixel clock period)
+            HSW: u10,
+            padding: u6,
+        }),
+        ///  Back Porch Configuration Register
+        BPCR: mmio.Mmio(packed struct(u32) {
+            ///  Accumulated Vertical back porch (in units of horizontal scan line)
+            AVBP: u11,
+            reserved16: u5,
+            ///  Accumulated Horizontal back porch (in units of pixel clock period)
+            AHBP: u10,
+            padding: u6,
+        }),
+        ///  Active Width Configuration Register
+        AWCR: mmio.Mmio(packed struct(u32) {
+            ///  Accumulated Active Height (in units of horizontal scan line)
+            AAH: u11,
+            reserved16: u5,
+            ///  AAV
+            AAV: u10,
+            padding: u6,
+        }),
+        ///  Total Width Configuration Register
+        TWCR: mmio.Mmio(packed struct(u32) {
+            ///  Total Height (in units of horizontal scan line)
+            TOTALH: u11,
+            reserved16: u5,
+            ///  Total Width (in units of pixel clock period)
+            TOTALW: u10,
+            padding: u6,
+        }),
+        ///  Global Control Register
+        GCR: mmio.Mmio(packed struct(u32) {
+            ///  LCD-TFT controller enable bit
+            LTDCEN: u1,
+            reserved4: u3,
+            ///  Dither Blue Width
+            DBW: u3,
+            reserved8: u1,
+            ///  Dither Green Width
+            DGW: u3,
+            reserved12: u1,
+            ///  Dither Red Width
+            DRW: u3,
+            reserved16: u1,
+            ///  Dither Enable
+            DEN: u1,
+            reserved28: u11,
+            ///  Pixel Clock Polarity
+            PCPOL: u1,
+            ///  Data Enable Polarity
+            DEPOL: u1,
+            ///  Vertical Synchronization Polarity
+            VSPOL: u1,
+            ///  Horizontal Synchronization Polarity
+            HSPOL: u1,
+        }),
+        reserved36: [8]u8,
+        ///  Shadow Reload Configuration Register
+        SRCR: mmio.Mmio(packed struct(u32) {
+            ///  Immediate Reload
+            IMR: u1,
+            ///  Vertical Blanking Reload
+            VBR: u1,
+            padding: u30,
+        }),
+        reserved44: [4]u8,
+        ///  Background Color Configuration Register
+        BCCR: mmio.Mmio(packed struct(u32) {
+            ///  Background Color Red value
+            BC: u24,
+            padding: u8,
+        }),
+        reserved52: [4]u8,
+        ///  Interrupt Enable Register
+        IER: mmio.Mmio(packed struct(u32) {
+            ///  Line Interrupt Enable
+            LIE: u1,
+            ///  FIFO Underrun Interrupt Enable
+            FUIE: u1,
+            ///  Transfer Error Interrupt Enable
+            TERRIE: u1,
+            ///  Register Reload interrupt enable
+            RRIE: u1,
+            padding: u28,
+        }),
+        ///  Interrupt Status Register
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  Line Interrupt flag
+            LIF: u1,
+            ///  FIFO Underrun Interrupt flag
+            FUIF: u1,
+            ///  Transfer Error interrupt flag
+            TERRIF: u1,
+            ///  Register Reload Interrupt Flag
+            RRIF: u1,
+            padding: u28,
+        }),
+        ///  Interrupt Clear Register
+        ICR: mmio.Mmio(packed struct(u32) {
+            ///  Clears the Line Interrupt Flag
+            CLIF: u1,
+            ///  Clears the FIFO Underrun Interrupt flag
+            CFUIF: u1,
+            ///  Clears the Transfer Error Interrupt Flag
+            CTERRIF: u1,
+            ///  Clears Register Reload Interrupt Flag
+            CRRIF: u1,
+            padding: u28,
+        }),
+        ///  Line Interrupt Position Configuration Register
+        LIPCR: mmio.Mmio(packed struct(u32) {
+            ///  Line Interrupt Position
+            LIPOS: u11,
+            padding: u21,
+        }),
+        ///  Current Position Status Register
+        CPSR: mmio.Mmio(packed struct(u32) {
+            ///  Current Y Position
+            CYPOS: u16,
+            ///  Current X Position
+            CXPOS: u16,
+        }),
+        ///  Current Display Status Register
+        CDSR: mmio.Mmio(packed struct(u32) {
+            ///  Vertical Data Enable display Status
+            VDES: u1,
+            ///  Horizontal Data Enable display Status
+            HDES: u1,
+            ///  Vertical Synchronization display Status
+            VSYNCS: u1,
+            ///  Horizontal Synchronization display Status
+            HSYNCS: u1,
+            padding: u28,
+        }),
+        reserved132: [56]u8,
+        ///  Layerx Control Register
+        L1CR: mmio.Mmio(packed struct(u32) {
+            ///  Layer Enable
+            LEN: u1,
+            ///  Color Keying Enable
+            COLKEN: u1,
+            reserved4: u2,
+            ///  Color Look-Up Table Enable
+            CLUTEN: u1,
+            padding: u27,
+        }),
+        ///  Layerx Window Horizontal Position Configuration Register
+        L1WHPCR: mmio.Mmio(packed struct(u32) {
+            ///  Window Horizontal Start Position
+            WHSTPOS: u12,
+            reserved16: u4,
+            ///  Window Horizontal Stop Position
+            WHSPPOS: u12,
+            padding: u4,
+        }),
+        ///  Layerx Window Vertical Position Configuration Register
+        L1WVPCR: mmio.Mmio(packed struct(u32) {
+            ///  Window Vertical Start Position
+            WVSTPOS: u11,
+            reserved16: u5,
+            ///  Window Vertical Stop Position
+            WVSPPOS: u11,
+            padding: u5,
+        }),
+        ///  Layerx Color Keying Configuration Register
+        L1CKCR: mmio.Mmio(packed struct(u32) {
+            ///  Color Key Blue value
+            CKBLUE: u8,
+            ///  Color Key Green value
+            CKGREEN: u8,
+            ///  Color Key Red value
+            CKRED: u8,
+            padding: u8,
+        }),
+        ///  Layerx Pixel Format Configuration Register
+        L1PFCR: mmio.Mmio(packed struct(u32) {
+            ///  Pixel Format
+            PF: u3,
+            padding: u29,
+        }),
+        ///  Layerx Constant Alpha Configuration Register
+        L1CACR: mmio.Mmio(packed struct(u32) {
+            ///  Constant Alpha
+            CONSTA: u8,
+            padding: u24,
+        }),
+        ///  Layerx Default Color Configuration Register
+        L1DCCR: mmio.Mmio(packed struct(u32) {
+            ///  Default Color Blue
+            DCBLUE: u8,
+            ///  Default Color Green
+            DCGREEN: u8,
+            ///  Default Color Red
+            DCRED: u8,
+            ///  Default Color Alpha
+            DCALPHA: u8,
+        }),
+        ///  Layerx Blending Factors Configuration Register
+        L1BFCR: mmio.Mmio(packed struct(u32) {
+            ///  Blending Factor 2
+            BF2: u3,
+            reserved8: u5,
+            ///  Blending Factor 1
+            BF1: u3,
+            padding: u21,
+        }),
+        reserved172: [8]u8,
+        ///  Layerx Color Frame Buffer Address Register
+        L1CFBAR: mmio.Mmio(packed struct(u32) {
+            ///  Color Frame Buffer Start Address
+            CFBADD: u32,
+        }),
+        ///  Layerx Color Frame Buffer Length Register
+        L1CFBLR: mmio.Mmio(packed struct(u32) {
+            ///  Color Frame Buffer Line Length
+            CFBLL: u13,
+            reserved16: u3,
+            ///  Color Frame Buffer Pitch in bytes
+            CFBP: u13,
+            padding: u3,
+        }),
+        ///  Layerx ColorFrame Buffer Line Number Register
+        L1CFBLNR: mmio.Mmio(packed struct(u32) {
+            ///  Frame Buffer Line Number
+            CFBLNBR: u11,
+            padding: u21,
+        }),
+        reserved196: [12]u8,
+        ///  Layerx CLUT Write Register
+        L1CLUTWR: mmio.Mmio(packed struct(u32) {
+            ///  Blue value
+            BLUE: u8,
+            ///  Green value
+            GREEN: u8,
+            ///  Red value
+            RED: u8,
+            ///  CLUT Address
+            CLUTADD: u8,
+        }),
+        reserved260: [60]u8,
+        ///  Layerx Control Register
+        L2CR: mmio.Mmio(packed struct(u32) {
+            ///  Layer Enable
+            LEN: u1,
+            ///  Color Keying Enable
+            COLKEN: u1,
+            reserved4: u2,
+            ///  Color Look-Up Table Enable
+            CLUTEN: u1,
+            padding: u27,
+        }),
+        ///  Layerx Window Horizontal Position Configuration Register
+        L2WHPCR: mmio.Mmio(packed struct(u32) {
+            ///  Window Horizontal Start Position
+            WHSTPOS: u12,
+            reserved16: u4,
+            ///  Window Horizontal Stop Position
+            WHSPPOS: u12,
+            padding: u4,
+        }),
+        ///  Layerx Window Vertical Position Configuration Register
+        L2WVPCR: mmio.Mmio(packed struct(u32) {
+            ///  Window Vertical Start Position
+            WVSTPOS: u11,
+            reserved16: u5,
+            ///  Window Vertical Stop Position
+            WVSPPOS: u11,
+            padding: u5,
+        }),
+        ///  Layerx Color Keying Configuration Register
+        L2CKCR: mmio.Mmio(packed struct(u32) {
+            ///  Color Key Blue value
+            CKBLUE: u8,
+            ///  Color Key Green value
+            CKGREEN: u7,
+            ///  Color Key Red value
+            CKRED: u9,
+            padding: u8,
+        }),
+        ///  Layerx Pixel Format Configuration Register
+        L2PFCR: mmio.Mmio(packed struct(u32) {
+            ///  Pixel Format
+            PF: u3,
+            padding: u29,
+        }),
+        ///  Layerx Constant Alpha Configuration Register
+        L2CACR: mmio.Mmio(packed struct(u32) {
+            ///  Constant Alpha
+            CONSTA: u8,
+            padding: u24,
+        }),
+        ///  Layerx Default Color Configuration Register
+        L2DCCR: mmio.Mmio(packed struct(u32) {
+            ///  Default Color Blue
+            DCBLUE: u8,
+            ///  Default Color Green
+            DCGREEN: u8,
+            ///  Default Color Red
+            DCRED: u8,
+            ///  Default Color Alpha
+            DCALPHA: u8,
+        }),
+        ///  Layerx Blending Factors Configuration Register
+        L2BFCR: mmio.Mmio(packed struct(u32) {
+            ///  Blending Factor 2
+            BF2: u3,
+            reserved8: u5,
+            ///  Blending Factor 1
+            BF1: u3,
+            padding: u21,
+        }),
+        reserved300: [8]u8,
+        ///  Layerx Color Frame Buffer Address Register
+        L2CFBAR: mmio.Mmio(packed struct(u32) {
+            ///  Color Frame Buffer Start Address
+            CFBADD: u32,
+        }),
+        ///  Layerx Color Frame Buffer Length Register
+        L2CFBLR: mmio.Mmio(packed struct(u32) {
+            ///  Color Frame Buffer Line Length
+            CFBLL: u13,
+            reserved16: u3,
+            ///  Color Frame Buffer Pitch in bytes
+            CFBP: u13,
+            padding: u3,
+        }),
+        ///  Layerx ColorFrame Buffer Line Number Register
+        L2CFBLNR: mmio.Mmio(packed struct(u32) {
+            ///  Frame Buffer Line Number
+            CFBLNBR: u11,
+            padding: u21,
+        }),
+        reserved324: [12]u8,
+        ///  Layerx CLUT Write Register
+        L2CLUTWR: mmio.Mmio(packed struct(u32) {
+            ///  Blue value
+            BLUE: u8,
+            ///  Green value
+            GREEN: u8,
+            ///  Red value
+            RED: u8,
+            ///  CLUT Address
+            CLUTADD: u8,
+        }),
+    };
+
+    ///  USB on the go high speed
+    pub const OTG_HS_PWRCLK = extern struct {
+        ///  Power and clock gating control register
+        OTG_HS_PCGCR: mmio.Mmio(packed struct(u32) {
+            ///  Stop PHY clock
+            STPPCLK: u1,
+            ///  Gate HCLK
+            GATEHCLK: u1,
+            reserved4: u2,
+            ///  PHY suspended
+            PHYSUSP: u1,
+            padding: u27,
+        }),
+    };
+
+    ///  USB on the go high speed
+    pub const OTG_HS_DEVICE = extern struct {
+        ///  OTG_HS device configuration register
+        OTG_HS_DCFG: mmio.Mmio(packed struct(u32) {
+            ///  Device speed
+            DSPD: u2,
+            ///  Nonzero-length status OUT handshake
+            NZLSOHSK: u1,
+            reserved4: u1,
+            ///  Device address
+            DAD: u7,
+            ///  Periodic (micro)frame interval
+            PFIVL: u2,
+            reserved24: u11,
+            ///  Periodic scheduling interval
+            PERSCHIVL: u2,
+            padding: u6,
+        }),
+        ///  OTG_HS device control register
+        OTG_HS_DCTL: mmio.Mmio(packed struct(u32) {
+            ///  Remote wakeup signaling
+            RWUSIG: u1,
+            ///  Soft disconnect
+            SDIS: u1,
+            ///  Global IN NAK status
+            GINSTS: u1,
+            ///  Global OUT NAK status
+            GONSTS: u1,
+            ///  Test control
+            TCTL: u3,
+            ///  Set global IN NAK
+            SGINAK: u1,
+            ///  Clear global IN NAK
+            CGINAK: u1,
+            ///  Set global OUT NAK
+            SGONAK: u1,
+            ///  Clear global OUT NAK
+            CGONAK: u1,
+            ///  Power-on programming done
+            POPRGDNE: u1,
+            padding: u20,
+        }),
+        ///  OTG_HS device status register
+        OTG_HS_DSTS: mmio.Mmio(packed struct(u32) {
+            ///  Suspend status
+            SUSPSTS: u1,
+            ///  Enumerated speed
+            ENUMSPD: u2,
+            ///  Erratic error
+            EERR: u1,
+            reserved8: u4,
+            ///  Frame number of the received SOF
+            FNSOF: u14,
+            padding: u10,
+        }),
+        reserved16: [4]u8,
+        ///  OTG_HS device IN endpoint common interrupt mask register
+        OTG_HS_DIEPMSK: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  Timeout condition mask (nonisochronous endpoints)
+            TOM: u1,
+            ///  IN token received when TxFIFO empty mask
+            ITTXFEMSK: u1,
+            ///  IN token received with EP mismatch mask
+            INEPNMM: u1,
+            ///  IN endpoint NAK effective mask
+            INEPNEM: u1,
+            reserved8: u1,
+            ///  FIFO underrun mask
+            TXFURM: u1,
+            ///  BNA interrupt mask
+            BIM: u1,
+            padding: u22,
+        }),
+        ///  OTG_HS device OUT endpoint common interrupt mask register
+        OTG_HS_DOEPMSK: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  SETUP phase done mask
+            STUPM: u1,
+            ///  OUT token received when endpoint disabled mask
+            OTEPDM: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received mask
+            B2BSTUP: u1,
+            reserved8: u1,
+            ///  OUT packet error mask
+            OPEM: u1,
+            ///  BNA interrupt mask
+            BOIM: u1,
+            padding: u22,
+        }),
+        ///  OTG_HS device all endpoints interrupt register
+        OTG_HS_DAINT: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint interrupt bits
+            IEPINT: u16,
+            ///  OUT endpoint interrupt bits
+            OEPINT: u16,
+        }),
+        ///  OTG_HS all endpoints interrupt mask register
+        OTG_HS_DAINTMSK: mmio.Mmio(packed struct(u32) {
+            ///  IN EP interrupt mask bits
+            IEPM: u16,
+            ///  OUT EP interrupt mask bits
+            OEPM: u16,
+        }),
+        reserved40: [8]u8,
+        ///  OTG_HS device VBUS discharge time register
+        OTG_HS_DVBUSDIS: mmio.Mmio(packed struct(u32) {
+            ///  Device VBUS discharge time
+            VBUSDT: u16,
+            padding: u16,
+        }),
+        ///  OTG_HS device VBUS pulsing time register
+        OTG_HS_DVBUSPULSE: mmio.Mmio(packed struct(u32) {
+            ///  Device VBUS pulsing time
+            DVBUSP: u12,
+            padding: u20,
+        }),
+        ///  OTG_HS Device threshold control register
+        OTG_HS_DTHRCTL: mmio.Mmio(packed struct(u32) {
+            ///  Nonisochronous IN endpoints threshold enable
+            NONISOTHREN: u1,
+            ///  ISO IN endpoint threshold enable
+            ISOTHREN: u1,
+            ///  Transmit threshold length
+            TXTHRLEN: u9,
+            reserved16: u5,
+            ///  Receive threshold enable
+            RXTHREN: u1,
+            ///  Receive threshold length
+            RXTHRLEN: u9,
+            reserved27: u1,
+            ///  Arbiter parking enable
+            ARPEN: u1,
+            padding: u4,
+        }),
+        ///  OTG_HS device IN endpoint FIFO empty interrupt mask register
+        OTG_HS_DIEPEMPMSK: mmio.Mmio(packed struct(u32) {
+            ///  IN EP Tx FIFO empty interrupt mask bits
+            INEPTXFEM: u16,
+            padding: u16,
+        }),
+        ///  OTG_HS device each endpoint interrupt register
+        OTG_HS_DEACHINT: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  IN endpoint 1interrupt bit
+            IEP1INT: u1,
+            reserved17: u15,
+            ///  OUT endpoint 1 interrupt bit
+            OEP1INT: u1,
+            padding: u14,
+        }),
+        ///  OTG_HS device each endpoint interrupt register mask
+        OTG_HS_DEACHINTMSK: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  IN Endpoint 1 interrupt mask bit
+            IEP1INTM: u1,
+            reserved17: u15,
+            ///  OUT Endpoint 1 interrupt mask bit
+            OEP1INTM: u1,
+            padding: u14,
+        }),
+        ///  OTG_HS device each in endpoint-1 interrupt register
+        OTG_HS_DIEPEACHMSK1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  Timeout condition mask (nonisochronous endpoints)
+            TOM: u1,
+            ///  IN token received when TxFIFO empty mask
+            ITTXFEMSK: u1,
+            ///  IN token received with EP mismatch mask
+            INEPNMM: u1,
+            ///  IN endpoint NAK effective mask
+            INEPNEM: u1,
+            reserved8: u1,
+            ///  FIFO underrun mask
+            TXFURM: u1,
+            ///  BNA interrupt mask
+            BIM: u1,
+            reserved13: u3,
+            ///  NAK interrupt mask
+            NAKM: u1,
+            padding: u18,
+        }),
+        reserved128: [60]u8,
+        ///  OTG_HS device each OUT endpoint-1 interrupt register
+        OTG_HS_DOEPEACHMSK1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  Timeout condition mask
+            TOM: u1,
+            ///  IN token received when TxFIFO empty mask
+            ITTXFEMSK: u1,
+            ///  IN token received with EP mismatch mask
+            INEPNMM: u1,
+            ///  IN endpoint NAK effective mask
+            INEPNEM: u1,
+            reserved8: u1,
+            ///  OUT packet error mask
+            TXFURM: u1,
+            ///  BNA interrupt mask
+            BIM: u1,
+            reserved12: u2,
+            ///  Bubble error interrupt mask
+            BERRM: u1,
+            ///  NAK interrupt mask
+            NAKM: u1,
+            ///  NYET interrupt mask
+            NYETM: u1,
+            padding: u17,
+        }),
+        reserved256: [124]u8,
+        ///  OTG device endpoint-0 control register
+        OTG_HS_DIEPCTL0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved264: [4]u8,
+        ///  OTG device endpoint-0 interrupt register
+        OTG_HS_DIEPINT0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved272: [4]u8,
+        ///  OTG_HS device IN endpoint 0 transfer size register
+        OTG_HS_DIEPTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u7,
+            reserved19: u12,
+            ///  Packet count
+            PKTCNT: u2,
+            padding: u11,
+        }),
+        ///  OTG_HS device endpoint-1 DMA address register
+        OTG_HS_DIEPDMA1: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS0: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved288: [4]u8,
+        ///  OTG device endpoint-1 control register
+        OTG_HS_DIEPCTL1: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved296: [4]u8,
+        ///  OTG device endpoint-1 interrupt register
+        OTG_HS_DIEPINT1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved304: [4]u8,
+        ///  OTG_HS device endpoint transfer size register
+        OTG_HS_DIEPTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS device endpoint-2 DMA address register
+        OTG_HS_DIEPDMA2: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS1: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved320: [4]u8,
+        ///  OTG device endpoint-2 control register
+        OTG_HS_DIEPCTL2: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved328: [4]u8,
+        ///  OTG device endpoint-2 interrupt register
+        OTG_HS_DIEPINT2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved336: [4]u8,
+        ///  OTG_HS device endpoint transfer size register
+        OTG_HS_DIEPTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS device endpoint-3 DMA address register
+        OTG_HS_DIEPDMA3: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS2: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved352: [4]u8,
+        ///  OTG device endpoint-3 control register
+        OTG_HS_DIEPCTL3: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved360: [4]u8,
+        ///  OTG device endpoint-3 interrupt register
+        OTG_HS_DIEPINT3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved368: [4]u8,
+        ///  OTG_HS device endpoint transfer size register
+        OTG_HS_DIEPTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS device endpoint-4 DMA address register
+        OTG_HS_DIEPDMA4: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS3: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved384: [4]u8,
+        ///  OTG device endpoint-4 control register
+        OTG_HS_DIEPCTL4: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved392: [4]u8,
+        ///  OTG device endpoint-4 interrupt register
+        OTG_HS_DIEPINT4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved400: [4]u8,
+        ///  OTG_HS device endpoint transfer size register
+        OTG_HS_DIEPTSIZ4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS device endpoint-5 DMA address register
+        OTG_HS_DIEPDMA5: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS4: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved416: [4]u8,
+        ///  OTG device endpoint-5 control register
+        OTG_HS_DIEPCTL5: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved424: [4]u8,
+        ///  OTG device endpoint-5 interrupt register
+        OTG_HS_DIEPINT5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved432: [4]u8,
+        ///  OTG_HS device endpoint transfer size register
+        OTG_HS_DIEPTSIZ5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        reserved440: [4]u8,
+        ///  OTG_HS device IN endpoint transmit FIFO status register
+        OTG_HS_DTXFSTS5: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space avail
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved448: [4]u8,
+        ///  OTG device endpoint-6 control register
+        OTG_HS_DIEPCTL6: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved456: [4]u8,
+        ///  OTG device endpoint-6 interrupt register
+        OTG_HS_DIEPINT6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved480: [20]u8,
+        ///  OTG device endpoint-7 control register
+        OTG_HS_DIEPCTL7: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even/odd frame
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            Stall: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved488: [4]u8,
+        ///  OTG device endpoint-7 interrupt register
+        OTG_HS_DIEPINT7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  Timeout condition
+            TOC: u1,
+            ///  IN token received when TxFIFO is empty
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  IN endpoint NAK effective
+            INEPNE: u1,
+            ///  Transmit FIFO empty
+            TXFE: u1,
+            ///  Transmit Fifo Underrun
+            TXFIFOUDRN: u1,
+            ///  Buffer not available interrupt
+            BNA: u1,
+            reserved11: u1,
+            ///  Packet dropped status
+            PKTDRPSTS: u1,
+            ///  Babble error interrupt
+            BERR: u1,
+            ///  NAK interrupt
+            NAK: u1,
+            padding: u18,
+        }),
+        reserved768: [276]u8,
+        ///  OTG_HS device control OUT endpoint 0 control register
+        OTG_HS_DOEPCTL0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u2,
+            reserved15: u13,
+            ///  USB active endpoint
+            USBAEP: u1,
+            reserved17: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Snoop mode
+            SNPM: u1,
+            ///  STALL handshake
+            Stall: u1,
+            reserved26: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            reserved30: u2,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved776: [4]u8,
+        ///  OTG_HS device endpoint-0 interrupt register
+        OTG_HS_DOEPINT0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved784: [4]u8,
+        ///  OTG_HS device endpoint-1 transfer size register
+        OTG_HS_DOEPTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u7,
+            reserved19: u12,
+            ///  Packet count
+            PKTCNT: u1,
+            reserved29: u9,
+            ///  SETUP packet count
+            STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved800: [12]u8,
+        ///  OTG device endpoint-1 control register
+        OTG_HS_DOEPCTL1: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even odd frame/Endpoint data PID
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Snoop mode
+            SNPM: u1,
+            ///  STALL handshake
+            Stall: u1,
+            reserved26: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID/Set even frame
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved808: [4]u8,
+        ///  OTG_HS device endpoint-1 interrupt register
+        OTG_HS_DOEPINT1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved816: [4]u8,
+        ///  OTG_HS device endpoint-2 transfer size register
+        OTG_HS_DOEPTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved832: [12]u8,
+        ///  OTG device endpoint-2 control register
+        OTG_HS_DOEPCTL2: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even odd frame/Endpoint data PID
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Snoop mode
+            SNPM: u1,
+            ///  STALL handshake
+            Stall: u1,
+            reserved26: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID/Set even frame
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved840: [4]u8,
+        ///  OTG_HS device endpoint-2 interrupt register
+        OTG_HS_DOEPINT2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved848: [4]u8,
+        ///  OTG_HS device endpoint-3 transfer size register
+        OTG_HS_DOEPTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved864: [12]u8,
+        ///  OTG device endpoint-3 control register
+        OTG_HS_DOEPCTL3: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USB active endpoint
+            USBAEP: u1,
+            ///  Even odd frame/Endpoint data PID
+            EONUM_DPID: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Snoop mode
+            SNPM: u1,
+            ///  STALL handshake
+            Stall: u1,
+            reserved26: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            ///  Set DATA0 PID/Set even frame
+            SD0PID_SEVNFRM: u1,
+            ///  Set odd frame
+            SODDFRM: u1,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved872: [4]u8,
+        ///  OTG_HS device endpoint-3 interrupt register
+        OTG_HS_DOEPINT3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved880: [4]u8,
+        ///  OTG_HS device endpoint-4 transfer size register
+        OTG_HS_DOEPTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved904: [20]u8,
+        ///  OTG_HS device endpoint-4 interrupt register
+        OTG_HS_DOEPINT4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved912: [4]u8,
+        ///  OTG_HS device endpoint-5 transfer size register
+        OTG_HS_DOEPTSIZ4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved936: [20]u8,
+        ///  OTG_HS device endpoint-5 interrupt register
+        OTG_HS_DOEPINT5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved968: [28]u8,
+        ///  OTG_HS device endpoint-6 interrupt register
+        OTG_HS_DOEPINT6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+        reserved1000: [28]u8,
+        ///  OTG_HS device endpoint-7 interrupt register
+        OTG_HS_DOEPINT7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt
+            XFRC: u1,
+            ///  Endpoint disabled interrupt
+            EPDISD: u1,
+            reserved3: u1,
+            ///  SETUP phase done
+            STUP: u1,
+            ///  OUT token received when endpoint disabled
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  Back-to-back SETUP packets received
+            B2BSTUP: u1,
+            reserved14: u7,
+            ///  NYET interrupt
+            NYET: u1,
+            padding: u17,
+        }),
+    };
+
+    ///  USB on the go high speed
+    pub const OTG_HS_HOST = extern struct {
+        ///  OTG_HS host configuration register
+        OTG_HS_HCFG: mmio.Mmio(packed struct(u32) {
+            ///  FS/LS PHY clock select
+            FSLSPCS: u2,
+            ///  FS- and LS-only support
+            FSLSS: u1,
+            padding: u29,
+        }),
+        ///  OTG_HS Host frame interval register
+        OTG_HS_HFIR: mmio.Mmio(packed struct(u32) {
+            ///  Frame interval
+            FRIVL: u16,
+            padding: u16,
+        }),
+        ///  OTG_HS host frame number/frame time remaining register
+        OTG_HS_HFNUM: mmio.Mmio(packed struct(u32) {
+            ///  Frame number
+            FRNUM: u16,
+            ///  Frame time remaining
+            FTREM: u16,
+        }),
+        reserved16: [4]u8,
+        ///  OTG_HS_Host periodic transmit FIFO/queue status register
+        OTG_HS_HPTXSTS: mmio.Mmio(packed struct(u32) {
+            ///  Periodic transmit data FIFO space available
+            PTXFSAVL: u16,
+            ///  Periodic transmit request queue space available
+            PTXQSAV: u8,
+            ///  Top of the periodic transmit request queue
+            PTXQTOP: u8,
+        }),
+        ///  OTG_HS Host all channels interrupt register
+        OTG_HS_HAINT: mmio.Mmio(packed struct(u32) {
+            ///  Channel interrupts
+            HAINT: u16,
+            padding: u16,
+        }),
+        ///  OTG_HS host all channels interrupt mask register
+        OTG_HS_HAINTMSK: mmio.Mmio(packed struct(u32) {
+            ///  Channel interrupt mask
+            HAINTM: u16,
+            padding: u16,
+        }),
+        reserved64: [36]u8,
+        ///  OTG_HS host port control and status register
+        OTG_HS_HPRT: mmio.Mmio(packed struct(u32) {
+            ///  Port connect status
+            PCSTS: u1,
+            ///  Port connect detected
+            PCDET: u1,
+            ///  Port enable
+            PENA: u1,
+            ///  Port enable/disable change
+            PENCHNG: u1,
+            ///  Port overcurrent active
+            POCA: u1,
+            ///  Port overcurrent change
+            POCCHNG: u1,
+            ///  Port resume
+            PRES: u1,
+            ///  Port suspend
+            PSUSP: u1,
+            ///  Port reset
+            PRST: u1,
+            reserved10: u1,
+            ///  Port line status
+            PLSTS: u2,
+            ///  Port power
+            PPWR: u1,
+            ///  Port test control
+            PTCTL: u4,
+            ///  Port speed
+            PSPD: u2,
+            padding: u13,
+        }),
+        reserved256: [188]u8,
+        ///  OTG_HS host channel-0 characteristics register
+        OTG_HS_HCCHAR0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-0 split control register
+        OTG_HS_HCSPLT0: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-11 interrupt register
+        OTG_HS_HCINT0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-11 interrupt mask register
+        OTG_HS_HCINTMSK0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-11 transfer size register
+        OTG_HS_HCTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-0 DMA address register
+        OTG_HS_HCDMA0: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved288: [8]u8,
+        ///  OTG_HS host channel-1 characteristics register
+        OTG_HS_HCCHAR1: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-1 split control register
+        OTG_HS_HCSPLT1: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-1 interrupt register
+        OTG_HS_HCINT1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-1 interrupt mask register
+        OTG_HS_HCINTMSK1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-1 transfer size register
+        OTG_HS_HCTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-1 DMA address register
+        OTG_HS_HCDMA1: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved320: [8]u8,
+        ///  OTG_HS host channel-2 characteristics register
+        OTG_HS_HCCHAR2: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-2 split control register
+        OTG_HS_HCSPLT2: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-2 interrupt register
+        OTG_HS_HCINT2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-2 interrupt mask register
+        OTG_HS_HCINTMSK2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-2 transfer size register
+        OTG_HS_HCTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-2 DMA address register
+        OTG_HS_HCDMA2: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved352: [8]u8,
+        ///  OTG_HS host channel-3 characteristics register
+        OTG_HS_HCCHAR3: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-3 split control register
+        OTG_HS_HCSPLT3: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-3 interrupt register
+        OTG_HS_HCINT3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-3 interrupt mask register
+        OTG_HS_HCINTMSK3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-3 transfer size register
+        OTG_HS_HCTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-3 DMA address register
+        OTG_HS_HCDMA3: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved384: [8]u8,
+        ///  OTG_HS host channel-4 characteristics register
+        OTG_HS_HCCHAR4: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-4 split control register
+        OTG_HS_HCSPLT4: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-4 interrupt register
+        OTG_HS_HCINT4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-4 interrupt mask register
+        OTG_HS_HCINTMSK4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-4 transfer size register
+        OTG_HS_HCTSIZ4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-4 DMA address register
+        OTG_HS_HCDMA4: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved416: [8]u8,
+        ///  OTG_HS host channel-5 characteristics register
+        OTG_HS_HCCHAR5: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-5 split control register
+        OTG_HS_HCSPLT5: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-5 interrupt register
+        OTG_HS_HCINT5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-5 interrupt mask register
+        OTG_HS_HCINTMSK5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-5 transfer size register
+        OTG_HS_HCTSIZ5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-5 DMA address register
+        OTG_HS_HCDMA5: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved448: [8]u8,
+        ///  OTG_HS host channel-6 characteristics register
+        OTG_HS_HCCHAR6: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-6 split control register
+        OTG_HS_HCSPLT6: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-6 interrupt register
+        OTG_HS_HCINT6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-6 interrupt mask register
+        OTG_HS_HCINTMSK6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-6 transfer size register
+        OTG_HS_HCTSIZ6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-6 DMA address register
+        OTG_HS_HCDMA6: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved480: [8]u8,
+        ///  OTG_HS host channel-7 characteristics register
+        OTG_HS_HCCHAR7: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-7 split control register
+        OTG_HS_HCSPLT7: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-7 interrupt register
+        OTG_HS_HCINT7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-7 interrupt mask register
+        OTG_HS_HCINTMSK7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-7 transfer size register
+        OTG_HS_HCTSIZ7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-7 DMA address register
+        OTG_HS_HCDMA7: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved512: [8]u8,
+        ///  OTG_HS host channel-8 characteristics register
+        OTG_HS_HCCHAR8: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-8 split control register
+        OTG_HS_HCSPLT8: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-8 interrupt register
+        OTG_HS_HCINT8: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-8 interrupt mask register
+        OTG_HS_HCINTMSK8: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-8 transfer size register
+        OTG_HS_HCTSIZ8: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-8 DMA address register
+        OTG_HS_HCDMA8: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved544: [8]u8,
+        ///  OTG_HS host channel-9 characteristics register
+        OTG_HS_HCCHAR9: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-9 split control register
+        OTG_HS_HCSPLT9: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-9 interrupt register
+        OTG_HS_HCINT9: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-9 interrupt mask register
+        OTG_HS_HCINTMSK9: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-9 transfer size register
+        OTG_HS_HCTSIZ9: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-9 DMA address register
+        OTG_HS_HCDMA9: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved576: [8]u8,
+        ///  OTG_HS host channel-10 characteristics register
+        OTG_HS_HCCHAR10: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-10 split control register
+        OTG_HS_HCSPLT10: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-10 interrupt register
+        OTG_HS_HCINT10: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-10 interrupt mask register
+        OTG_HS_HCINTMSK10: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-10 transfer size register
+        OTG_HS_HCTSIZ10: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-10 DMA address register
+        OTG_HS_HCDMA10: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+        reserved608: [8]u8,
+        ///  OTG_HS host channel-11 characteristics register
+        OTG_HS_HCCHAR11: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multi Count (MC) / Error Count (EC)
+            MC: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        ///  OTG_HS host channel-11 split control register
+        OTG_HS_HCSPLT11: mmio.Mmio(packed struct(u32) {
+            ///  Port address
+            PRTADDR: u7,
+            ///  Hub address
+            HUBADDR: u7,
+            ///  XACTPOS
+            XACTPOS: u2,
+            ///  Do complete split
+            COMPLSPLT: u1,
+            reserved31: u14,
+            ///  Split enable
+            SPLITEN: u1,
+        }),
+        ///  OTG_HS host channel-11 interrupt register
+        OTG_HS_HCINT11: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            ///  Response received interrupt
+            NYET: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-11 interrupt mask register
+        OTG_HS_HCINTMSK11: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            ///  AHB error
+            AHBERR: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_HS host channel-11 transfer size register
+        OTG_HS_HCTSIZ11: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        ///  OTG_HS host channel-11 DMA address register
+        OTG_HS_HCDMA11: mmio.Mmio(packed struct(u32) {
+            ///  DMA address
+            DMAADDR: u32,
+        }),
+    };
+
+    ///  Secure digital input/output interface
+    pub const SDIO = extern struct {
+        ///  power control register
+        POWER: mmio.Mmio(packed struct(u32) {
+            ///  PWRCTRL
+            PWRCTRL: u2,
+            padding: u30,
+        }),
+        ///  SDI clock control register
+        CLKCR: mmio.Mmio(packed struct(u32) {
+            ///  Clock divide factor
+            CLKDIV: u8,
+            ///  Clock enable bit
+            CLKEN: u1,
+            ///  Power saving configuration bit
+            PWRSAV: u1,
+            ///  Clock divider bypass enable bit
+            BYPASS: u1,
+            ///  Wide bus mode enable bit
+            WIDBUS: u2,
+            ///  SDIO_CK dephasing selection bit
+            NEGEDGE: u1,
+            ///  HW Flow Control enable
+            HWFC_EN: u1,
+            padding: u17,
+        }),
+        ///  argument register
+        ARG: mmio.Mmio(packed struct(u32) {
+            ///  Command argument
+            CMDARG: u32,
+        }),
+        ///  command register
+        CMD: mmio.Mmio(packed struct(u32) {
+            ///  Command index
+            CMDINDEX: u6,
+            ///  Wait for response bits
+            WAITRESP: u2,
+            ///  CPSM waits for interrupt request
+            WAITINT: u1,
+            ///  CPSM Waits for ends of data transfer (CmdPend internal signal).
+            WAITPEND: u1,
+            ///  Command path state machine (CPSM) Enable bit
+            CPSMEN: u1,
+            ///  SD I/O suspend command
+            SDIOSuspend: u1,
+            ///  Enable CMD completion
+            ENCMDcompl: u1,
+            ///  not Interrupt Enable
+            nIEN: u1,
+            ///  CE-ATA command
+            CE_ATACMD: u1,
+            padding: u17,
+        }),
+        ///  command response register
+        RESPCMD: mmio.Mmio(packed struct(u32) {
+            ///  Response command index
+            RESPCMD: u6,
+            padding: u26,
+        }),
+        ///  response 1..4 register
+        RESP1: mmio.Mmio(packed struct(u32) {
+            ///  see Table 132.
+            CARDSTATUS1: u32,
+        }),
+        ///  response 1..4 register
+        RESP2: mmio.Mmio(packed struct(u32) {
+            ///  see Table 132.
+            CARDSTATUS2: u32,
+        }),
+        ///  response 1..4 register
+        RESP3: mmio.Mmio(packed struct(u32) {
+            ///  see Table 132.
+            CARDSTATUS3: u32,
+        }),
+        ///  response 1..4 register
+        RESP4: mmio.Mmio(packed struct(u32) {
+            ///  see Table 132.
+            CARDSTATUS4: u32,
+        }),
+        ///  data timer register
+        DTIMER: mmio.Mmio(packed struct(u32) {
+            ///  Data timeout period
+            DATATIME: u32,
+        }),
+        ///  data length register
+        DLEN: mmio.Mmio(packed struct(u32) {
+            ///  Data length value
+            DATALENGTH: u25,
+            padding: u7,
+        }),
+        ///  data control register
+        DCTRL: mmio.Mmio(packed struct(u32) {
+            ///  DTEN
+            DTEN: u1,
+            ///  Data transfer direction selection
+            DTDIR: u1,
+            ///  Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
+            DTMODE: u1,
+            ///  DMA enable bit
+            DMAEN: u1,
+            ///  Data block size
+            DBLOCKSIZE: u4,
+            ///  Read wait start
+            RWSTART: u1,
+            ///  Read wait stop
+            RWSTOP: u1,
+            ///  Read wait mode
+            RWMOD: u1,
+            ///  SD I/O enable functions
+            SDIOEN: u1,
+            padding: u20,
+        }),
+        ///  data counter register
+        DCOUNT: mmio.Mmio(packed struct(u32) {
+            ///  Data count value
+            DATACOUNT: u25,
+            padding: u7,
+        }),
+        ///  status register
+        STA: mmio.Mmio(packed struct(u32) {
+            ///  Command response received (CRC check failed)
+            CCRCFAIL: u1,
+            ///  Data block sent/received (CRC check failed)
+            DCRCFAIL: u1,
+            ///  Command response timeout
+            CTIMEOUT: u1,
+            ///  Data timeout
+            DTIMEOUT: u1,
+            ///  Transmit FIFO underrun error
+            TXUNDERR: u1,
+            ///  Received FIFO overrun error
+            RXOVERR: u1,
+            ///  Command response received (CRC check passed)
+            CMDREND: u1,
+            ///  Command sent (no response required)
+            CMDSENT: u1,
+            ///  Data end (data counter, SDIDCOUNT, is zero)
+            DATAEND: u1,
+            ///  Start bit not detected on all data signals in wide bus mode
+            STBITERR: u1,
+            ///  Data block sent/received (CRC check passed)
+            DBCKEND: u1,
+            ///  Command transfer in progress
+            CMDACT: u1,
+            ///  Data transmit in progress
+            TXACT: u1,
+            ///  Data receive in progress
+            RXACT: u1,
+            ///  Transmit FIFO half empty: at least 8 words can be written into the FIFO
+            TXFIFOHE: u1,
+            ///  Receive FIFO half full: there are at least 8 words in the FIFO
+            RXFIFOHF: u1,
+            ///  Transmit FIFO full
+            TXFIFOF: u1,
+            ///  Receive FIFO full
+            RXFIFOF: u1,
+            ///  Transmit FIFO empty
+            TXFIFOE: u1,
+            ///  Receive FIFO empty
+            RXFIFOE: u1,
+            ///  Data available in transmit FIFO
+            TXDAVL: u1,
+            ///  Data available in receive FIFO
+            RXDAVL: u1,
+            ///  SDIO interrupt received
+            SDIOIT: u1,
+            ///  CE-ATA command completion signal received for CMD61
+            CEATAEND: u1,
+            padding: u8,
+        }),
+        ///  interrupt clear register
+        ICR: mmio.Mmio(packed struct(u32) {
+            ///  CCRCFAIL flag clear bit
+            CCRCFAILC: u1,
+            ///  DCRCFAIL flag clear bit
+            DCRCFAILC: u1,
+            ///  CTIMEOUT flag clear bit
+            CTIMEOUTC: u1,
+            ///  DTIMEOUT flag clear bit
+            DTIMEOUTC: u1,
+            ///  TXUNDERR flag clear bit
+            TXUNDERRC: u1,
+            ///  RXOVERR flag clear bit
+            RXOVERRC: u1,
+            ///  CMDREND flag clear bit
+            CMDRENDC: u1,
+            ///  CMDSENT flag clear bit
+            CMDSENTC: u1,
+            ///  DATAEND flag clear bit
+            DATAENDC: u1,
+            ///  STBITERR flag clear bit
+            STBITERRC: u1,
+            ///  DBCKEND flag clear bit
+            DBCKENDC: u1,
+            reserved22: u11,
+            ///  SDIOIT flag clear bit
+            SDIOITC: u1,
+            ///  CEATAEND flag clear bit
+            CEATAENDC: u1,
+            padding: u8,
+        }),
+        ///  mask register
+        MASK: mmio.Mmio(packed struct(u32) {
+            ///  Command CRC fail interrupt enable
+            CCRCFAILIE: u1,
+            ///  Data CRC fail interrupt enable
+            DCRCFAILIE: u1,
+            ///  Command timeout interrupt enable
+            CTIMEOUTIE: u1,
+            ///  Data timeout interrupt enable
+            DTIMEOUTIE: u1,
+            ///  Tx FIFO underrun error interrupt enable
+            TXUNDERRIE: u1,
+            ///  Rx FIFO overrun error interrupt enable
+            RXOVERRIE: u1,
+            ///  Command response received interrupt enable
+            CMDRENDIE: u1,
+            ///  Command sent interrupt enable
+            CMDSENTIE: u1,
+            ///  Data end interrupt enable
+            DATAENDIE: u1,
+            ///  Start bit error interrupt enable
+            STBITERRIE: u1,
+            ///  Data block end interrupt enable
+            DBCKENDIE: u1,
+            ///  Command acting interrupt enable
+            CMDACTIE: u1,
+            ///  Data transmit acting interrupt enable
+            TXACTIE: u1,
+            ///  Data receive acting interrupt enable
+            RXACTIE: u1,
+            ///  Tx FIFO half empty interrupt enable
+            TXFIFOHEIE: u1,
+            ///  Rx FIFO half full interrupt enable
+            RXFIFOHFIE: u1,
+            ///  Tx FIFO full interrupt enable
+            TXFIFOFIE: u1,
+            ///  Rx FIFO full interrupt enable
+            RXFIFOFIE: u1,
+            ///  Tx FIFO empty interrupt enable
+            TXFIFOEIE: u1,
+            ///  Rx FIFO empty interrupt enable
+            RXFIFOEIE: u1,
+            ///  Data available in Tx FIFO interrupt enable
+            TXDAVLIE: u1,
+            ///  Data available in Rx FIFO interrupt enable
+            RXDAVLIE: u1,
+            ///  SDIO mode interrupt received interrupt enable
+            SDIOITIE: u1,
+            ///  CE-ATA command completion signal received interrupt enable
+            CEATAENDIE: u1,
+            padding: u8,
+        }),
+        reserved72: [8]u8,
+        ///  FIFO counter register
+        FIFOCNT: mmio.Mmio(packed struct(u32) {
+            ///  Remaining number of words to be written to or read from the FIFO.
+            FIFOCOUNT: u24,
+            padding: u8,
+        }),
+        reserved128: [52]u8,
+        ///  data FIFO register
+        FIFO: mmio.Mmio(packed struct(u32) {
+            ///  Receive and transmit FIFO data
+            FIFOData: u32,
+        }),
+    };
+
+    ///  Analog-to-digital converter
+    pub const ADC1 = extern struct {
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog flag
+            AWD: u1,
+            ///  Regular channel end of conversion
+            EOC: u1,
+            ///  Injected channel end of conversion
+            JEOC: u1,
+            ///  Injected channel start flag
+            JSTRT: u1,
+            ///  Regular channel start flag
+            STRT: u1,
+            ///  Overrun
+            OVR: u1,
+            padding: u26,
+        }),
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog channel select bits
+            AWDCH: u5,
+            ///  Interrupt enable for EOC
+            EOCIE: u1,
+            ///  Analog watchdog interrupt enable
+            AWDIE: u1,
+            ///  Interrupt enable for injected channels
+            JEOCIE: u1,
+            ///  Scan mode
+            SCAN: u1,
+            ///  Enable the watchdog on a single channel in scan mode
+            AWDSGL: u1,
+            ///  Automatic injected group conversion
+            JAUTO: u1,
+            ///  Discontinuous mode on regular channels
+            DISCEN: u1,
+            ///  Discontinuous mode on injected channels
+            JDISCEN: u1,
+            ///  Discontinuous mode channel count
+            DISCNUM: u3,
+            reserved22: u6,
+            ///  Analog watchdog enable on injected channels
+            JAWDEN: u1,
+            ///  Analog watchdog enable on regular channels
+            AWDEN: u1,
+            ///  Resolution
+            RES: u2,
+            ///  Overrun interrupt enable
+            OVRIE: u1,
+            padding: u5,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  A/D Converter ON / OFF
+            ADON: u1,
+            ///  Continuous conversion
+            CONT: u1,
+            reserved8: u6,
+            ///  Direct memory access mode (for single ADC mode)
+            DMA: u1,
+            ///  DMA disable selection (for single ADC mode)
+            DDS: u1,
+            ///  End of conversion selection
+            EOCS: u1,
+            ///  Data alignment
+            ALIGN: u1,
+            reserved16: u4,
+            ///  External event select for injected group
+            JEXTSEL: u4,
+            ///  External trigger enable for injected channels
+            JEXTEN: u2,
+            ///  Start conversion of injected channels
+            JSWSTART: u1,
+            reserved24: u1,
+            ///  External event select for regular group
+            EXTSEL: u4,
+            ///  External trigger enable for regular channels
+            EXTEN: u2,
+            ///  Start conversion of regular channels
+            SWSTART: u1,
+            padding: u1,
+        }),
+        ///  sample time register 1
+        SMPR1: mmio.Mmio(packed struct(u32) {
+            ///  Sample time bits
+            SMPx_x: u32,
+        }),
+        ///  sample time register 2
+        SMPR2: mmio.Mmio(packed struct(u32) {
+            ///  Sample time bits
+            SMPx_x: u32,
+        }),
+        ///  injected channel data offset register x
+        JOFR1: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET1: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR2: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET2: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR3: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET3: u12,
+            padding: u20,
+        }),
+        ///  injected channel data offset register x
+        JOFR4: mmio.Mmio(packed struct(u32) {
+            ///  Data offset for injected channel x
+            JOFFSET4: u12,
+            padding: u20,
+        }),
+        ///  watchdog higher threshold register
+        HTR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog higher threshold
+            HT: u12,
+            padding: u20,
+        }),
+        ///  watchdog lower threshold register
+        LTR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog lower threshold
+            LT: u12,
+            padding: u20,
+        }),
+        ///  regular sequence register 1
+        SQR1: mmio.Mmio(packed struct(u32) {
+            ///  13th conversion in regular sequence
+            SQ13: u5,
+            ///  14th conversion in regular sequence
+            SQ14: u5,
+            ///  15th conversion in regular sequence
+            SQ15: u5,
+            ///  16th conversion in regular sequence
+            SQ16: u5,
+            ///  Regular channel sequence length
+            L: u4,
+            padding: u8,
+        }),
+        ///  regular sequence register 2
+        SQR2: mmio.Mmio(packed struct(u32) {
+            ///  7th conversion in regular sequence
+            SQ7: u5,
+            ///  8th conversion in regular sequence
+            SQ8: u5,
+            ///  9th conversion in regular sequence
+            SQ9: u5,
+            ///  10th conversion in regular sequence
+            SQ10: u5,
+            ///  11th conversion in regular sequence
+            SQ11: u5,
+            ///  12th conversion in regular sequence
+            SQ12: u5,
+            padding: u2,
+        }),
+        ///  regular sequence register 3
+        SQR3: mmio.Mmio(packed struct(u32) {
+            ///  1st conversion in regular sequence
+            SQ1: u5,
+            ///  2nd conversion in regular sequence
+            SQ2: u5,
+            ///  3rd conversion in regular sequence
+            SQ3: u5,
+            ///  4th conversion in regular sequence
+            SQ4: u5,
+            ///  5th conversion in regular sequence
+            SQ5: u5,
+            ///  6th conversion in regular sequence
+            SQ6: u5,
+            padding: u2,
+        }),
+        ///  injected sequence register
+        JSQR: mmio.Mmio(packed struct(u32) {
+            ///  1st conversion in injected sequence
+            JSQ1: u5,
+            ///  2nd conversion in injected sequence
+            JSQ2: u5,
+            ///  3rd conversion in injected sequence
+            JSQ3: u5,
+            ///  4th conversion in injected sequence
+            JSQ4: u5,
+            ///  Injected sequence length
+            JL: u2,
+            padding: u10,
+        }),
+        ///  injected data register x
+        JDR1: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR2: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR3: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  injected data register x
+        JDR4: mmio.Mmio(packed struct(u32) {
+            ///  Injected data
+            JDATA: u16,
+            padding: u16,
+        }),
+        ///  regular data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Regular data
+            DATA: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  USB on the go high speed
+    pub const OTG_HS_GLOBAL = extern struct {
+        ///  OTG_HS control and status register
+        OTG_HS_GOTGCTL: mmio.Mmio(packed struct(u32) {
+            ///  Session request success
+            SRQSCS: u1,
+            ///  Session request
+            SRQ: u1,
+            reserved8: u6,
+            ///  Host negotiation success
+            HNGSCS: u1,
+            ///  HNP request
+            HNPRQ: u1,
+            ///  Host set HNP enable
+            HSHNPEN: u1,
+            ///  Device HNP enabled
+            DHNPEN: u1,
+            reserved16: u4,
+            ///  Connector ID status
+            CIDSTS: u1,
+            ///  Long/short debounce time
+            DBCT: u1,
+            ///  A-session valid
+            ASVLD: u1,
+            ///  B-session valid
+            BSVLD: u1,
+            padding: u12,
+        }),
+        ///  OTG_HS interrupt register
+        OTG_HS_GOTGINT: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Session end detected
+            SEDET: u1,
+            reserved8: u5,
+            ///  Session request success status change
+            SRSSCHG: u1,
+            ///  Host negotiation success status change
+            HNSSCHG: u1,
+            reserved17: u7,
+            ///  Host negotiation detected
+            HNGDET: u1,
+            ///  A-device timeout change
+            ADTOCHG: u1,
+            ///  Debounce done
+            DBCDNE: u1,
+            padding: u12,
+        }),
+        ///  OTG_HS AHB configuration register
+        OTG_HS_GAHBCFG: mmio.Mmio(packed struct(u32) {
+            ///  Global interrupt mask
+            GINT: u1,
+            ///  Burst length/type
+            HBSTLEN: u4,
+            ///  DMA enable
+            DMAEN: u1,
+            reserved7: u1,
+            ///  TxFIFO empty level
+            TXFELVL: u1,
+            ///  Periodic TxFIFO empty level
+            PTXFELVL: u1,
+            padding: u23,
+        }),
+        ///  OTG_HS USB configuration register
+        OTG_HS_GUSBCFG: mmio.Mmio(packed struct(u32) {
+            ///  FS timeout calibration
+            TOCAL: u3,
+            reserved6: u3,
+            ///  USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
+            PHYSEL: u1,
+            reserved8: u1,
+            ///  SRP-capable
+            SRPCAP: u1,
+            ///  HNP-capable
+            HNPCAP: u1,
+            ///  USB turnaround time
+            TRDT: u4,
+            reserved15: u1,
+            ///  PHY Low-power clock select
+            PHYLPCS: u1,
+            reserved17: u1,
+            ///  ULPI FS/LS select
+            ULPIFSLS: u1,
+            ///  ULPI Auto-resume
+            ULPIAR: u1,
+            ///  ULPI Clock SuspendM
+            ULPICSM: u1,
+            ///  ULPI External VBUS Drive
+            ULPIEVBUSD: u1,
+            ///  ULPI external VBUS indicator
+            ULPIEVBUSI: u1,
+            ///  TermSel DLine pulsing selection
+            TSDPS: u1,
+            ///  Indicator complement
+            PCCI: u1,
+            ///  Indicator pass through
+            PTCI: u1,
+            ///  ULPI interface protect disable
+            ULPIIPD: u1,
+            reserved29: u3,
+            ///  Forced host mode
+            FHMOD: u1,
+            ///  Forced peripheral mode
+            FDMOD: u1,
+            ///  Corrupt Tx packet
+            CTXPKT: u1,
+        }),
+        ///  OTG_HS reset register
+        OTG_HS_GRSTCTL: mmio.Mmio(packed struct(u32) {
+            ///  Core soft reset
+            CSRST: u1,
+            ///  HCLK soft reset
+            HSRST: u1,
+            ///  Host frame counter reset
+            FCRST: u1,
+            reserved4: u1,
+            ///  RxFIFO flush
+            RXFFLSH: u1,
+            ///  TxFIFO flush
+            TXFFLSH: u1,
+            ///  TxFIFO number
+            TXFNUM: u5,
+            reserved30: u19,
+            ///  DMA request signal
+            DMAREQ: u1,
+            ///  AHB master idle
+            AHBIDL: u1,
+        }),
+        ///  OTG_HS core interrupt register
+        OTG_HS_GINTSTS: mmio.Mmio(packed struct(u32) {
+            ///  Current mode of operation
+            CMOD: u1,
+            ///  Mode mismatch interrupt
+            MMIS: u1,
+            ///  OTG interrupt
+            OTGINT: u1,
+            ///  Start of frame
+            SOF: u1,
+            ///  RxFIFO nonempty
+            RXFLVL: u1,
+            ///  Nonperiodic TxFIFO empty
+            NPTXFE: u1,
+            ///  Global IN nonperiodic NAK effective
+            GINAKEFF: u1,
+            ///  Global OUT NAK effective
+            BOUTNAKEFF: u1,
+            reserved10: u2,
+            ///  Early suspend
+            ESUSP: u1,
+            ///  USB suspend
+            USBSUSP: u1,
+            ///  USB reset
+            USBRST: u1,
+            ///  Enumeration done
+            ENUMDNE: u1,
+            ///  Isochronous OUT packet dropped interrupt
+            ISOODRP: u1,
+            ///  End of periodic frame interrupt
+            EOPF: u1,
+            reserved18: u2,
+            ///  IN endpoint interrupt
+            IEPINT: u1,
+            ///  OUT endpoint interrupt
+            OEPINT: u1,
+            ///  Incomplete isochronous IN transfer
+            IISOIXFR: u1,
+            ///  Incomplete periodic transfer
+            PXFR_INCOMPISOOUT: u1,
+            ///  Data fetch suspended
+            DATAFSUSP: u1,
+            reserved24: u1,
+            ///  Host port interrupt
+            HPRTINT: u1,
+            ///  Host channels interrupt
+            HCINT: u1,
+            ///  Periodic TxFIFO empty
+            PTXFE: u1,
+            reserved28: u1,
+            ///  Connector ID status change
+            CIDSCHG: u1,
+            ///  Disconnect detected interrupt
+            DISCINT: u1,
+            ///  Session request/new session detected interrupt
+            SRQINT: u1,
+            ///  Resume/remote wakeup detected interrupt
+            WKUINT: u1,
+        }),
+        ///  OTG_HS interrupt mask register
+        OTG_HS_GINTMSK: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Mode mismatch interrupt mask
+            MMISM: u1,
+            ///  OTG interrupt mask
+            OTGINT: u1,
+            ///  Start of frame mask
+            SOFM: u1,
+            ///  Receive FIFO nonempty mask
+            RXFLVLM: u1,
+            ///  Nonperiodic TxFIFO empty mask
+            NPTXFEM: u1,
+            ///  Global nonperiodic IN NAK effective mask
+            GINAKEFFM: u1,
+            ///  Global OUT NAK effective mask
+            GONAKEFFM: u1,
+            reserved10: u2,
+            ///  Early suspend mask
+            ESUSPM: u1,
+            ///  USB suspend mask
+            USBSUSPM: u1,
+            ///  USB reset mask
+            USBRST: u1,
+            ///  Enumeration done mask
+            ENUMDNEM: u1,
+            ///  Isochronous OUT packet dropped interrupt mask
+            ISOODRPM: u1,
+            ///  End of periodic frame interrupt mask
+            EOPFM: u1,
+            reserved17: u1,
+            ///  Endpoint mismatch interrupt mask
+            EPMISM: u1,
+            ///  IN endpoints interrupt mask
+            IEPINT: u1,
+            ///  OUT endpoints interrupt mask
+            OEPINT: u1,
+            ///  Incomplete isochronous IN transfer mask
+            IISOIXFRM: u1,
+            ///  Incomplete periodic transfer mask
+            PXFRM_IISOOXFRM: u1,
+            ///  Data fetch suspended mask
+            FSUSPM: u1,
+            reserved24: u1,
+            ///  Host port interrupt mask
+            PRTIM: u1,
+            ///  Host channels interrupt mask
+            HCIM: u1,
+            ///  Periodic TxFIFO empty mask
+            PTXFEM: u1,
+            reserved28: u1,
+            ///  Connector ID status change mask
+            CIDSCHGM: u1,
+            ///  Disconnect detected interrupt mask
+            DISCINT: u1,
+            ///  Session request/new session detected interrupt mask
+            SRQIM: u1,
+            ///  Resume/remote wakeup detected interrupt mask
+            WUIM: u1,
+        }),
+        ///  OTG_HS Receive status debug read register (host mode)
+        OTG_HS_GRXSTSR_Host: mmio.Mmio(packed struct(u32) {
+            ///  Channel number
+            CHNUM: u4,
+            ///  Byte count
+            BCNT: u11,
+            ///  Data PID
+            DPID: u2,
+            ///  Packet status
+            PKTSTS: u4,
+            padding: u11,
+        }),
+        ///  OTG_HS status read and pop register (host mode)
+        OTG_HS_GRXSTSP_Host: mmio.Mmio(packed struct(u32) {
+            ///  Channel number
+            CHNUM: u4,
+            ///  Byte count
+            BCNT: u11,
+            ///  Data PID
+            DPID: u2,
+            ///  Packet status
+            PKTSTS: u4,
+            padding: u11,
+        }),
+        ///  OTG_HS Receive FIFO size register
+        OTG_HS_GRXFSIZ: mmio.Mmio(packed struct(u32) {
+            ///  RxFIFO depth
+            RXFD: u16,
+            padding: u16,
+        }),
+        ///  OTG_HS nonperiodic transmit FIFO size register (host mode)
+        OTG_HS_GNPTXFSIZ_Host: mmio.Mmio(packed struct(u32) {
+            ///  Nonperiodic transmit RAM start address
+            NPTXFSA: u16,
+            ///  Nonperiodic TxFIFO depth
+            NPTXFD: u16,
+        }),
+        ///  OTG_HS nonperiodic transmit FIFO/queue status register
+        OTG_HS_GNPTXSTS: mmio.Mmio(packed struct(u32) {
+            ///  Nonperiodic TxFIFO space available
+            NPTXFSAV: u16,
+            ///  Nonperiodic transmit request queue space available
+            NPTQXSAV: u8,
+            ///  Top of the nonperiodic transmit request queue
+            NPTXQTOP: u7,
+            padding: u1,
+        }),
+        reserved56: [8]u8,
+        ///  OTG_HS general core configuration register
+        OTG_HS_GCCFG: mmio.Mmio(packed struct(u32) {
+            reserved16: u16,
+            ///  Power down
+            PWRDWN: u1,
+            ///  Enable I2C bus connection for the external I2C PHY interface
+            I2CPADEN: u1,
+            ///  Enable the VBUS sensing device
+            VBUSASEN: u1,
+            ///  Enable the VBUS sensing device
+            VBUSBSEN: u1,
+            ///  SOF output enable
+            SOFOUTEN: u1,
+            ///  VBUS sensing disable option
+            NOVBUSSENS: u1,
+            padding: u10,
+        }),
+        ///  OTG_HS core ID register
+        OTG_HS_CID: mmio.Mmio(packed struct(u32) {
+            ///  Product ID field
+            PRODUCT_ID: u32,
+        }),
+        reserved256: [192]u8,
+        ///  OTG_HS Host periodic transmit FIFO size register
+        OTG_HS_HPTXFSIZ: mmio.Mmio(packed struct(u32) {
+            ///  Host periodic TxFIFO start address
+            PTXSA: u16,
+            ///  Host periodic TxFIFO depth
+            PTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF1: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF2: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        reserved284: [16]u8,
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF3: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF4: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF5: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF6: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_HS device IN endpoint transmit FIFO size register
+        OTG_HS_DIEPTXF7: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFOx transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+    };
+
+    ///  External interrupt/event controller
+    pub const EXTI = extern struct {
+        ///  Interrupt mask register (EXTI_IMR)
+        IMR: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt Mask on line 0
+            MR0: u1,
+            ///  Interrupt Mask on line 1
+            MR1: u1,
+            ///  Interrupt Mask on line 2
+            MR2: u1,
+            ///  Interrupt Mask on line 3
+            MR3: u1,
+            ///  Interrupt Mask on line 4
+            MR4: u1,
+            ///  Interrupt Mask on line 5
+            MR5: u1,
+            ///  Interrupt Mask on line 6
+            MR6: u1,
+            ///  Interrupt Mask on line 7
+            MR7: u1,
+            ///  Interrupt Mask on line 8
+            MR8: u1,
+            ///  Interrupt Mask on line 9
+            MR9: u1,
+            ///  Interrupt Mask on line 10
+            MR10: u1,
+            ///  Interrupt Mask on line 11
+            MR11: u1,
+            ///  Interrupt Mask on line 12
+            MR12: u1,
+            ///  Interrupt Mask on line 13
+            MR13: u1,
+            ///  Interrupt Mask on line 14
+            MR14: u1,
+            ///  Interrupt Mask on line 15
+            MR15: u1,
+            ///  Interrupt Mask on line 16
+            MR16: u1,
+            ///  Interrupt Mask on line 17
+            MR17: u1,
+            ///  Interrupt Mask on line 18
+            MR18: u1,
+            ///  Interrupt Mask on line 19
+            MR19: u1,
+            ///  Interrupt Mask on line 20
+            MR20: u1,
+            ///  Interrupt Mask on line 21
+            MR21: u1,
+            ///  Interrupt Mask on line 22
+            MR22: u1,
+            padding: u9,
+        }),
+        ///  Event mask register (EXTI_EMR)
+        EMR: mmio.Mmio(packed struct(u32) {
+            ///  Event Mask on line 0
+            MR0: u1,
+            ///  Event Mask on line 1
+            MR1: u1,
+            ///  Event Mask on line 2
+            MR2: u1,
+            ///  Event Mask on line 3
+            MR3: u1,
+            ///  Event Mask on line 4
+            MR4: u1,
+            ///  Event Mask on line 5
+            MR5: u1,
+            ///  Event Mask on line 6
+            MR6: u1,
+            ///  Event Mask on line 7
+            MR7: u1,
+            ///  Event Mask on line 8
+            MR8: u1,
+            ///  Event Mask on line 9
+            MR9: u1,
+            ///  Event Mask on line 10
+            MR10: u1,
+            ///  Event Mask on line 11
+            MR11: u1,
+            ///  Event Mask on line 12
+            MR12: u1,
+            ///  Event Mask on line 13
+            MR13: u1,
+            ///  Event Mask on line 14
+            MR14: u1,
+            ///  Event Mask on line 15
+            MR15: u1,
+            ///  Event Mask on line 16
+            MR16: u1,
+            ///  Event Mask on line 17
+            MR17: u1,
+            ///  Event Mask on line 18
+            MR18: u1,
+            ///  Event Mask on line 19
+            MR19: u1,
+            ///  Event Mask on line 20
+            MR20: u1,
+            ///  Event Mask on line 21
+            MR21: u1,
+            ///  Event Mask on line 22
+            MR22: u1,
+            padding: u9,
+        }),
+        ///  Rising Trigger selection register (EXTI_RTSR)
+        RTSR: mmio.Mmio(packed struct(u32) {
+            ///  Rising trigger event configuration of line 0
+            TR0: u1,
+            ///  Rising trigger event configuration of line 1
+            TR1: u1,
+            ///  Rising trigger event configuration of line 2
+            TR2: u1,
+            ///  Rising trigger event configuration of line 3
+            TR3: u1,
+            ///  Rising trigger event configuration of line 4
+            TR4: u1,
+            ///  Rising trigger event configuration of line 5
+            TR5: u1,
+            ///  Rising trigger event configuration of line 6
+            TR6: u1,
+            ///  Rising trigger event configuration of line 7
+            TR7: u1,
+            ///  Rising trigger event configuration of line 8
+            TR8: u1,
+            ///  Rising trigger event configuration of line 9
+            TR9: u1,
+            ///  Rising trigger event configuration of line 10
+            TR10: u1,
+            ///  Rising trigger event configuration of line 11
+            TR11: u1,
+            ///  Rising trigger event configuration of line 12
+            TR12: u1,
+            ///  Rising trigger event configuration of line 13
+            TR13: u1,
+            ///  Rising trigger event configuration of line 14
+            TR14: u1,
+            ///  Rising trigger event configuration of line 15
+            TR15: u1,
+            ///  Rising trigger event configuration of line 16
+            TR16: u1,
+            ///  Rising trigger event configuration of line 17
+            TR17: u1,
+            ///  Rising trigger event configuration of line 18
+            TR18: u1,
+            ///  Rising trigger event configuration of line 19
+            TR19: u1,
+            ///  Rising trigger event configuration of line 20
+            TR20: u1,
+            ///  Rising trigger event configuration of line 21
+            TR21: u1,
+            ///  Rising trigger event configuration of line 22
+            TR22: u1,
+            padding: u9,
+        }),
+        ///  Falling Trigger selection register (EXTI_FTSR)
+        FTSR: mmio.Mmio(packed struct(u32) {
+            ///  Falling trigger event configuration of line 0
+            TR0: u1,
+            ///  Falling trigger event configuration of line 1
+            TR1: u1,
+            ///  Falling trigger event configuration of line 2
+            TR2: u1,
+            ///  Falling trigger event configuration of line 3
+            TR3: u1,
+            ///  Falling trigger event configuration of line 4
+            TR4: u1,
+            ///  Falling trigger event configuration of line 5
+            TR5: u1,
+            ///  Falling trigger event configuration of line 6
+            TR6: u1,
+            ///  Falling trigger event configuration of line 7
+            TR7: u1,
+            ///  Falling trigger event configuration of line 8
+            TR8: u1,
+            ///  Falling trigger event configuration of line 9
+            TR9: u1,
+            ///  Falling trigger event configuration of line 10
+            TR10: u1,
+            ///  Falling trigger event configuration of line 11
+            TR11: u1,
+            ///  Falling trigger event configuration of line 12
+            TR12: u1,
+            ///  Falling trigger event configuration of line 13
+            TR13: u1,
+            ///  Falling trigger event configuration of line 14
+            TR14: u1,
+            ///  Falling trigger event configuration of line 15
+            TR15: u1,
+            ///  Falling trigger event configuration of line 16
+            TR16: u1,
+            ///  Falling trigger event configuration of line 17
+            TR17: u1,
+            ///  Falling trigger event configuration of line 18
+            TR18: u1,
+            ///  Falling trigger event configuration of line 19
+            TR19: u1,
+            ///  Falling trigger event configuration of line 20
+            TR20: u1,
+            ///  Falling trigger event configuration of line 21
+            TR21: u1,
+            ///  Falling trigger event configuration of line 22
+            TR22: u1,
+            padding: u9,
+        }),
+        ///  Software interrupt event register (EXTI_SWIER)
+        SWIER: mmio.Mmio(packed struct(u32) {
+            ///  Software Interrupt on line 0
+            SWIER0: u1,
+            ///  Software Interrupt on line 1
+            SWIER1: u1,
+            ///  Software Interrupt on line 2
+            SWIER2: u1,
+            ///  Software Interrupt on line 3
+            SWIER3: u1,
+            ///  Software Interrupt on line 4
+            SWIER4: u1,
+            ///  Software Interrupt on line 5
+            SWIER5: u1,
+            ///  Software Interrupt on line 6
+            SWIER6: u1,
+            ///  Software Interrupt on line 7
+            SWIER7: u1,
+            ///  Software Interrupt on line 8
+            SWIER8: u1,
+            ///  Software Interrupt on line 9
+            SWIER9: u1,
+            ///  Software Interrupt on line 10
+            SWIER10: u1,
+            ///  Software Interrupt on line 11
+            SWIER11: u1,
+            ///  Software Interrupt on line 12
+            SWIER12: u1,
+            ///  Software Interrupt on line 13
+            SWIER13: u1,
+            ///  Software Interrupt on line 14
+            SWIER14: u1,
+            ///  Software Interrupt on line 15
+            SWIER15: u1,
+            ///  Software Interrupt on line 16
+            SWIER16: u1,
+            ///  Software Interrupt on line 17
+            SWIER17: u1,
+            ///  Software Interrupt on line 18
+            SWIER18: u1,
+            ///  Software Interrupt on line 19
+            SWIER19: u1,
+            ///  Software Interrupt on line 20
+            SWIER20: u1,
+            ///  Software Interrupt on line 21
+            SWIER21: u1,
+            ///  Software Interrupt on line 22
+            SWIER22: u1,
+            padding: u9,
+        }),
+        ///  Pending register (EXTI_PR)
+        PR: mmio.Mmio(packed struct(u32) {
+            ///  Pending bit 0
+            PR0: u1,
+            ///  Pending bit 1
+            PR1: u1,
+            ///  Pending bit 2
+            PR2: u1,
+            ///  Pending bit 3
+            PR3: u1,
+            ///  Pending bit 4
+            PR4: u1,
+            ///  Pending bit 5
+            PR5: u1,
+            ///  Pending bit 6
+            PR6: u1,
+            ///  Pending bit 7
+            PR7: u1,
+            ///  Pending bit 8
+            PR8: u1,
+            ///  Pending bit 9
+            PR9: u1,
+            ///  Pending bit 10
+            PR10: u1,
+            ///  Pending bit 11
+            PR11: u1,
+            ///  Pending bit 12
+            PR12: u1,
+            ///  Pending bit 13
+            PR13: u1,
+            ///  Pending bit 14
+            PR14: u1,
+            ///  Pending bit 15
+            PR15: u1,
+            ///  Pending bit 16
+            PR16: u1,
+            ///  Pending bit 17
+            PR17: u1,
+            ///  Pending bit 18
+            PR18: u1,
+            ///  Pending bit 19
+            PR19: u1,
+            ///  Pending bit 20
+            PR20: u1,
+            ///  Pending bit 21
+            PR21: u1,
+            ///  Pending bit 22
+            PR22: u1,
+            padding: u9,
+        }),
+    };
+
+    ///  Universal synchronous asynchronous receiver transmitter
+    pub const USART6 = extern struct {
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Parity error
+            PE: u1,
+            ///  Framing error
+            FE: u1,
+            ///  Noise detected flag
+            NF: u1,
+            ///  Overrun error
+            ORE: u1,
+            ///  IDLE line detected
+            IDLE: u1,
+            ///  Read data register not empty
+            RXNE: u1,
+            ///  Transmission complete
+            TC: u1,
+            ///  Transmit data register empty
+            TXE: u1,
+            ///  LIN break detection flag
+            LBD: u1,
+            ///  CTS flag
+            CTS: u1,
+            padding: u22,
+        }),
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data value
+            DR: u9,
+            padding: u23,
+        }),
+        ///  Baud rate register
+        BRR: mmio.Mmio(packed struct(u32) {
+            ///  fraction of USARTDIV
+            DIV_Fraction: u4,
+            ///  mantissa of USARTDIV
+            DIV_Mantissa: u12,
+            padding: u16,
+        }),
+        ///  Control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Send break
+            SBK: u1,
+            ///  Receiver wakeup
+            RWU: u1,
+            ///  Receiver enable
+            RE: u1,
+            ///  Transmitter enable
+            TE: u1,
+            ///  IDLE interrupt enable
+            IDLEIE: u1,
+            ///  RXNE interrupt enable
+            RXNEIE: u1,
+            ///  Transmission complete interrupt enable
+            TCIE: u1,
+            ///  TXE interrupt enable
+            TXEIE: u1,
+            ///  PE interrupt enable
+            PEIE: u1,
+            ///  Parity selection
+            PS: u1,
+            ///  Parity control enable
+            PCE: u1,
+            ///  Wakeup method
+            WAKE: u1,
+            ///  Word length
+            M: u1,
+            ///  USART enable
+            UE: u1,
+            reserved15: u1,
+            ///  Oversampling mode
+            OVER8: u1,
+            padding: u16,
+        }),
+        ///  Control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Address of the USART node
+            ADD: u4,
+            reserved5: u1,
+            ///  lin break detection length
+            LBDL: u1,
+            ///  LIN break detection interrupt enable
+            LBDIE: u1,
+            reserved8: u1,
+            ///  Last bit clock pulse
+            LBCL: u1,
+            ///  Clock phase
+            CPHA: u1,
+            ///  Clock polarity
+            CPOL: u1,
+            ///  Clock enable
+            CLKEN: u1,
+            ///  STOP bits
+            STOP: u2,
+            ///  LIN mode enable
+            LINEN: u1,
+            padding: u17,
+        }),
+        ///  Control register 3
+        CR3: mmio.Mmio(packed struct(u32) {
+            ///  Error interrupt enable
+            EIE: u1,
+            ///  IrDA mode enable
+            IREN: u1,
+            ///  IrDA low-power
+            IRLP: u1,
+            ///  Half-duplex selection
+            HDSEL: u1,
+            ///  Smartcard NACK enable
+            NACK: u1,
+            ///  Smartcard mode enable
+            SCEN: u1,
+            ///  DMA enable receiver
+            DMAR: u1,
+            ///  DMA enable transmitter
+            DMAT: u1,
+            ///  RTS enable
+            RTSE: u1,
+            ///  CTS enable
+            CTSE: u1,
+            ///  CTS interrupt enable
+            CTSIE: u1,
+            ///  One sample bit method enable
+            ONEBIT: u1,
+            padding: u20,
+        }),
+        ///  Guard time and prescaler register
+        GTPR: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u8,
+            ///  Guard time value
+            GT: u8,
+            padding: u16,
+        }),
+    };
+
+    ///  FLASH
+    pub const FLASH = extern struct {
+        ///  Flash access control register
+        ACR: mmio.Mmio(packed struct(u32) {
+            ///  Latency
+            LATENCY: u3,
+            reserved8: u5,
+            ///  Prefetch enable
+            PRFTEN: u1,
+            ///  Instruction cache enable
+            ICEN: u1,
+            ///  Data cache enable
+            DCEN: u1,
+            ///  Instruction cache reset
+            ICRST: u1,
+            ///  Data cache reset
+            DCRST: u1,
+            padding: u19,
+        }),
+        ///  Flash key register
+        KEYR: mmio.Mmio(packed struct(u32) {
+            ///  FPEC key
+            KEY: u32,
+        }),
+        ///  Flash option key register
+        OPTKEYR: mmio.Mmio(packed struct(u32) {
+            ///  Option byte key
+            OPTKEY: u32,
+        }),
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  End of operation
+            EOP: u1,
+            ///  Operation error
+            OPERR: u1,
+            reserved4: u2,
+            ///  Write protection error
+            WRPERR: u1,
+            ///  Programming alignment error
+            PGAERR: u1,
+            ///  Programming parallelism error
+            PGPERR: u1,
+            ///  Programming sequence error
+            PGSERR: u1,
+            reserved16: u8,
+            ///  Busy
+            BSY: u1,
+            padding: u15,
+        }),
+        ///  Control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Programming
+            PG: u1,
+            ///  Sector Erase
+            SER: u1,
+            ///  Mass Erase of sectors 0 to 11
+            MER: u1,
+            ///  Sector number
+            SNB: u5,
+            ///  Program size
+            PSIZE: u2,
+            reserved15: u5,
+            ///  Mass Erase of sectors 12 to 23
+            MER1: u1,
+            ///  Start
+            STRT: u1,
+            reserved24: u7,
+            ///  End of operation interrupt enable
+            EOPIE: u1,
+            ///  Error interrupt enable
+            ERRIE: u1,
+            reserved31: u5,
+            ///  Lock
+            LOCK: u1,
+        }),
+        ///  Flash option control register
+        OPTCR: mmio.Mmio(packed struct(u32) {
+            ///  Option lock
+            OPTLOCK: u1,
+            ///  Option start
+            OPTSTRT: u1,
+            ///  BOR reset Level
+            BOR_LEV: u2,
+            reserved5: u1,
+            ///  WDG_SW User option bytes
+            WDG_SW: u1,
+            ///  nRST_STOP User option bytes
+            nRST_STOP: u1,
+            ///  nRST_STDBY User option bytes
+            nRST_STDBY: u1,
+            ///  Read protect
+            RDP: u8,
+            ///  Not write protect
+            nWRP: u12,
+            padding: u4,
+        }),
+        ///  Flash option control register 1
+        OPTCR1: mmio.Mmio(packed struct(u32) {
+            reserved16: u16,
+            ///  Not write protect
+            nWRP: u12,
+            padding: u4,
+        }),
+    };
+
+    ///  Nested Vectored Interrupt Controller
+    pub const NVIC = extern struct {
+        ///  Interrupt Set-Enable Register
+        ISER0: mmio.Mmio(packed struct(u32) {
+            ///  SETENA
+            SETENA: u32,
+        }),
+        ///  Interrupt Set-Enable Register
+        ISER1: mmio.Mmio(packed struct(u32) {
+            ///  SETENA
+            SETENA: u32,
+        }),
+        ///  Interrupt Set-Enable Register
+        ISER2: mmio.Mmio(packed struct(u32) {
+            ///  SETENA
+            SETENA: u32,
+        }),
+        reserved128: [116]u8,
+        ///  Interrupt Clear-Enable Register
+        ICER0: mmio.Mmio(packed struct(u32) {
+            ///  CLRENA
+            CLRENA: u32,
+        }),
+        ///  Interrupt Clear-Enable Register
+        ICER1: mmio.Mmio(packed struct(u32) {
+            ///  CLRENA
+            CLRENA: u32,
+        }),
+        ///  Interrupt Clear-Enable Register
+        ICER2: mmio.Mmio(packed struct(u32) {
+            ///  CLRENA
+            CLRENA: u32,
+        }),
+        reserved256: [116]u8,
+        ///  Interrupt Set-Pending Register
+        ISPR0: mmio.Mmio(packed struct(u32) {
+            ///  SETPEND
+            SETPEND: u32,
+        }),
+        ///  Interrupt Set-Pending Register
+        ISPR1: mmio.Mmio(packed struct(u32) {
+            ///  SETPEND
+            SETPEND: u32,
+        }),
+        ///  Interrupt Set-Pending Register
+        ISPR2: mmio.Mmio(packed struct(u32) {
+            ///  SETPEND
+            SETPEND: u32,
+        }),
+        reserved384: [116]u8,
+        ///  Interrupt Clear-Pending Register
+        ICPR0: mmio.Mmio(packed struct(u32) {
+            ///  CLRPEND
+            CLRPEND: u32,
+        }),
+        ///  Interrupt Clear-Pending Register
+        ICPR1: mmio.Mmio(packed struct(u32) {
+            ///  CLRPEND
+            CLRPEND: u32,
+        }),
+        ///  Interrupt Clear-Pending Register
+        ICPR2: mmio.Mmio(packed struct(u32) {
+            ///  CLRPEND
+            CLRPEND: u32,
+        }),
+        reserved512: [116]u8,
+        ///  Interrupt Active Bit Register
+        IABR0: mmio.Mmio(packed struct(u32) {
+            ///  ACTIVE
+            ACTIVE: u32,
+        }),
+        ///  Interrupt Active Bit Register
+        IABR1: mmio.Mmio(packed struct(u32) {
+            ///  ACTIVE
+            ACTIVE: u32,
+        }),
+        ///  Interrupt Active Bit Register
+        IABR2: mmio.Mmio(packed struct(u32) {
+            ///  ACTIVE
+            ACTIVE: u32,
+        }),
+        reserved768: [244]u8,
+        ///  Interrupt Priority Register
+        IPR0: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR1: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR2: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR3: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR4: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR5: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR6: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR7: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR8: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR9: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR10: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR11: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR12: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR13: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR14: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR15: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR16: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR17: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR18: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR19: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+        ///  Interrupt Priority Register
+        IPR20: mmio.Mmio(packed struct(u32) {
+            ///  IPR_N0
+            IPR_N0: u8,
+            ///  IPR_N1
+            IPR_N1: u8,
+            ///  IPR_N2
+            IPR_N2: u8,
+            ///  IPR_N3
+            IPR_N3: u8,
+        }),
+    };
+
+    ///  Ethernet: media access control (MAC)
+    pub const Ethernet_MAC = extern struct {
+        ///  Ethernet MAC configuration register
+        MACCR: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  RE
+            RE: u1,
+            ///  TE
+            TE: u1,
+            ///  DC
+            DC: u1,
+            ///  BL
+            BL: u2,
+            ///  APCS
+            APCS: u1,
+            reserved9: u1,
+            ///  RD
+            RD: u1,
+            ///  IPCO
+            IPCO: u1,
+            ///  DM
+            DM: u1,
+            ///  LM
+            LM: u1,
+            ///  ROD
+            ROD: u1,
+            ///  FES
+            FES: u1,
+            reserved16: u1,
+            ///  CSD
+            CSD: u1,
+            ///  IFG
+            IFG: u3,
+            reserved22: u2,
+            ///  JD
+            JD: u1,
+            ///  WD
+            WD: u1,
+            reserved25: u1,
+            ///  CSTF
+            CSTF: u1,
+            padding: u6,
+        }),
+        ///  Ethernet MAC frame filter register
+        MACFFR: mmio.Mmio(packed struct(u32) {
+            ///  PM
+            PM: u1,
+            ///  HU
+            HU: u1,
+            ///  HM
+            HM: u1,
+            ///  DAIF
+            DAIF: u1,
+            ///  RAM
+            RAM: u1,
+            ///  BFD
+            BFD: u1,
+            ///  PCF
+            PCF: u1,
+            ///  SAIF
+            SAIF: u1,
+            ///  SAF
+            SAF: u1,
+            ///  HPF
+            HPF: u1,
+            reserved31: u21,
+            ///  RA
+            RA: u1,
+        }),
+        ///  Ethernet MAC hash table high register
+        MACHTHR: mmio.Mmio(packed struct(u32) {
+            ///  HTH
+            HTH: u32,
+        }),
+        ///  Ethernet MAC hash table low register
+        MACHTLR: mmio.Mmio(packed struct(u32) {
+            ///  HTL
+            HTL: u32,
+        }),
+        ///  Ethernet MAC MII address register
+        MACMIIAR: mmio.Mmio(packed struct(u32) {
+            ///  MB
+            MB: u1,
+            ///  MW
+            MW: u1,
+            ///  CR
+            CR: u3,
+            reserved6: u1,
+            ///  MR
+            MR: u5,
+            ///  PA
+            PA: u5,
+            padding: u16,
+        }),
+        ///  Ethernet MAC MII data register
+        MACMIIDR: mmio.Mmio(packed struct(u32) {
+            ///  TD
+            TD: u16,
+            padding: u16,
+        }),
+        ///  Ethernet MAC flow control register
+        MACFCR: mmio.Mmio(packed struct(u32) {
+            ///  FCB
+            FCB: u1,
+            ///  TFCE
+            TFCE: u1,
+            ///  RFCE
+            RFCE: u1,
+            ///  UPFD
+            UPFD: u1,
+            ///  PLT
+            PLT: u2,
+            reserved7: u1,
+            ///  ZQPD
+            ZQPD: u1,
+            reserved16: u8,
+            ///  PT
+            PT: u16,
+        }),
+        ///  Ethernet MAC VLAN tag register
+        MACVLANTR: mmio.Mmio(packed struct(u32) {
+            ///  VLANTI
+            VLANTI: u16,
+            ///  VLANTC
+            VLANTC: u1,
+            padding: u15,
+        }),
+        reserved44: [12]u8,
+        ///  Ethernet MAC PMT control and status register
+        MACPMTCSR: mmio.Mmio(packed struct(u32) {
+            ///  PD
+            PD: u1,
+            ///  MPE
+            MPE: u1,
+            ///  WFE
+            WFE: u1,
+            reserved5: u2,
+            ///  MPR
+            MPR: u1,
+            ///  WFR
+            WFR: u1,
+            reserved9: u2,
+            ///  GU
+            GU: u1,
+            reserved31: u21,
+            ///  WFFRPR
+            WFFRPR: u1,
+        }),
+        reserved52: [4]u8,
+        ///  Ethernet MAC debug register
+        MACDBGR: mmio.Mmio(packed struct(u32) {
+            ///  CR
+            CR: u1,
+            ///  CSR
+            CSR: u1,
+            ///  ROR
+            ROR: u1,
+            ///  MCF
+            MCF: u1,
+            ///  MCP
+            MCP: u1,
+            ///  MCFHP
+            MCFHP: u1,
+            padding: u26,
+        }),
+        ///  Ethernet MAC interrupt status register
+        MACSR: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  PMTS
+            PMTS: u1,
+            ///  MMCS
+            MMCS: u1,
+            ///  MMCRS
+            MMCRS: u1,
+            ///  MMCTS
+            MMCTS: u1,
+            reserved9: u2,
+            ///  TSTS
+            TSTS: u1,
+            padding: u22,
+        }),
+        ///  Ethernet MAC interrupt mask register
+        MACIMR: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  PMTIM
+            PMTIM: u1,
+            reserved9: u5,
+            ///  TSTIM
+            TSTIM: u1,
+            padding: u22,
+        }),
+        ///  Ethernet MAC address 0 high register
+        MACA0HR: mmio.Mmio(packed struct(u32) {
+            ///  MAC address0 high
+            MACA0H: u16,
+            reserved31: u15,
+            ///  Always 1
+            MO: u1,
+        }),
+        ///  Ethernet MAC address 0 low register
+        MACA0LR: mmio.Mmio(packed struct(u32) {
+            ///  0
+            MACA0L: u32,
+        }),
+        ///  Ethernet MAC address 1 high register
+        MACA1HR: mmio.Mmio(packed struct(u32) {
+            ///  MACA1H
+            MACA1H: u16,
+            reserved24: u8,
+            ///  MBC
+            MBC: u6,
+            ///  SA
+            SA: u1,
+            ///  AE
+            AE: u1,
+        }),
+        ///  Ethernet MAC address1 low register
+        MACA1LR: mmio.Mmio(packed struct(u32) {
+            ///  MACA1LR
+            MACA1LR: u32,
+        }),
+        ///  Ethernet MAC address 2 high register
+        MACA2HR: mmio.Mmio(packed struct(u32) {
+            ///  MAC2AH
+            MAC2AH: u16,
+            reserved24: u8,
+            ///  MBC
+            MBC: u6,
+            ///  SA
+            SA: u1,
+            ///  AE
+            AE: u1,
+        }),
+        ///  Ethernet MAC address 2 low register
+        MACA2LR: mmio.Mmio(packed struct(u32) {
+            ///  MACA2L
+            MACA2L: u31,
+            padding: u1,
+        }),
+        ///  Ethernet MAC address 3 high register
+        MACA3HR: mmio.Mmio(packed struct(u32) {
+            ///  MACA3H
+            MACA3H: u16,
+            reserved24: u8,
+            ///  MBC
+            MBC: u6,
+            ///  SA
+            SA: u1,
+            ///  AE
+            AE: u1,
+        }),
+        ///  Ethernet MAC address 3 low register
+        MACA3LR: mmio.Mmio(packed struct(u32) {
+            ///  MBCA3L
+            MBCA3L: u32,
+        }),
+    };
+
+    ///  Controller area network
+    pub const CAN1 = extern struct {
+        ///  master control register
+        MCR: mmio.Mmio(packed struct(u32) {
+            ///  INRQ
+            INRQ: u1,
+            ///  SLEEP
+            SLEEP: u1,
+            ///  TXFP
+            TXFP: u1,
+            ///  RFLM
+            RFLM: u1,
+            ///  NART
+            NART: u1,
+            ///  AWUM
+            AWUM: u1,
+            ///  ABOM
+            ABOM: u1,
+            ///  TTCM
+            TTCM: u1,
+            reserved15: u7,
+            ///  RESET
+            RESET: u1,
+            ///  DBF
+            DBF: u1,
+            padding: u15,
+        }),
+        ///  master status register
+        MSR: mmio.Mmio(packed struct(u32) {
+            ///  INAK
+            INAK: u1,
+            ///  SLAK
+            SLAK: u1,
+            ///  ERRI
+            ERRI: u1,
+            ///  WKUI
+            WKUI: u1,
+            ///  SLAKI
+            SLAKI: u1,
+            reserved8: u3,
+            ///  TXM
+            TXM: u1,
+            ///  RXM
+            RXM: u1,
+            ///  SAMP
+            SAMP: u1,
+            ///  RX
+            RX: u1,
+            padding: u20,
+        }),
+        ///  transmit status register
+        TSR: mmio.Mmio(packed struct(u32) {
+            ///  RQCP0
+            RQCP0: u1,
+            ///  TXOK0
+            TXOK0: u1,
+            ///  ALST0
+            ALST0: u1,
+            ///  TERR0
+            TERR0: u1,
+            reserved7: u3,
+            ///  ABRQ0
+            ABRQ0: u1,
+            ///  RQCP1
+            RQCP1: u1,
+            ///  TXOK1
+            TXOK1: u1,
+            ///  ALST1
+            ALST1: u1,
+            ///  TERR1
+            TERR1: u1,
+            reserved15: u3,
+            ///  ABRQ1
+            ABRQ1: u1,
+            ///  RQCP2
+            RQCP2: u1,
+            ///  TXOK2
+            TXOK2: u1,
+            ///  ALST2
+            ALST2: u1,
+            ///  TERR2
+            TERR2: u1,
+            reserved23: u3,
+            ///  ABRQ2
+            ABRQ2: u1,
+            ///  CODE
+            CODE: u2,
+            ///  Lowest priority flag for mailbox 0
+            TME0: u1,
+            ///  Lowest priority flag for mailbox 1
+            TME1: u1,
+            ///  Lowest priority flag for mailbox 2
+            TME2: u1,
+            ///  Lowest priority flag for mailbox 0
+            LOW0: u1,
+            ///  Lowest priority flag for mailbox 1
+            LOW1: u1,
+            ///  Lowest priority flag for mailbox 2
+            LOW2: u1,
+        }),
+        ///  receive FIFO 0 register
+        RF0R: mmio.Mmio(packed struct(u32) {
+            ///  FMP0
+            FMP0: u2,
+            reserved3: u1,
+            ///  FULL0
+            FULL0: u1,
+            ///  FOVR0
+            FOVR0: u1,
+            ///  RFOM0
+            RFOM0: u1,
+            padding: u26,
+        }),
+        ///  receive FIFO 1 register
+        RF1R: mmio.Mmio(packed struct(u32) {
+            ///  FMP1
+            FMP1: u2,
+            reserved3: u1,
+            ///  FULL1
+            FULL1: u1,
+            ///  FOVR1
+            FOVR1: u1,
+            ///  RFOM1
+            RFOM1: u1,
+            padding: u26,
+        }),
+        ///  interrupt enable register
+        IER: mmio.Mmio(packed struct(u32) {
+            ///  TMEIE
+            TMEIE: u1,
+            ///  FMPIE0
+            FMPIE0: u1,
+            ///  FFIE0
+            FFIE0: u1,
+            ///  FOVIE0
+            FOVIE0: u1,
+            ///  FMPIE1
+            FMPIE1: u1,
+            ///  FFIE1
+            FFIE1: u1,
+            ///  FOVIE1
+            FOVIE1: u1,
+            reserved8: u1,
+            ///  EWGIE
+            EWGIE: u1,
+            ///  EPVIE
+            EPVIE: u1,
+            ///  BOFIE
+            BOFIE: u1,
+            ///  LECIE
+            LECIE: u1,
+            reserved15: u3,
+            ///  ERRIE
+            ERRIE: u1,
+            ///  WKUIE
+            WKUIE: u1,
+            ///  SLKIE
+            SLKIE: u1,
+            padding: u14,
+        }),
+        ///  interrupt enable register
+        ESR: mmio.Mmio(packed struct(u32) {
+            ///  EWGF
+            EWGF: u1,
+            ///  EPVF
+            EPVF: u1,
+            ///  BOFF
+            BOFF: u1,
+            reserved4: u1,
+            ///  LEC
+            LEC: u3,
+            reserved16: u9,
+            ///  TEC
+            TEC: u8,
+            ///  REC
+            REC: u8,
+        }),
+        ///  bit timing register
+        BTR: mmio.Mmio(packed struct(u32) {
+            ///  BRP
+            BRP: u10,
+            reserved16: u6,
+            ///  TS1
+            TS1: u4,
+            ///  TS2
+            TS2: u3,
+            reserved24: u1,
+            ///  SJW
+            SJW: u2,
+            reserved30: u4,
+            ///  LBKM
+            LBKM: u1,
+            ///  SILM
+            SILM: u1,
+        }),
+        reserved384: [352]u8,
+        ///  TX mailbox identifier register
+        TI0R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data length control and time stamp register
+        TDT0R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data low register
+        TDL0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  mailbox data high register
+        TDH0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  mailbox identifier register
+        TI1R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data length control and time stamp register
+        TDT1R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data low register
+        TDL1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  mailbox data high register
+        TDH1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  mailbox identifier register
+        TI2R: mmio.Mmio(packed struct(u32) {
+            ///  TXRQ
+            TXRQ: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data length control and time stamp register
+        TDT2R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  TGT
+            TGT: u1,
+            reserved16: u7,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data low register
+        TDL2R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  mailbox data high register
+        TDH2R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  receive FIFO mailbox identifier register
+        RI0R: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data high register
+        RDT0R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  FMI
+            FMI: u8,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data high register
+        RDL0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  receive FIFO mailbox data high register
+        RDH0R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        ///  mailbox data high register
+        RI1R: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  RTR
+            RTR: u1,
+            ///  IDE
+            IDE: u1,
+            ///  EXID
+            EXID: u18,
+            ///  STID
+            STID: u11,
+        }),
+        ///  mailbox data high register
+        RDT1R: mmio.Mmio(packed struct(u32) {
+            ///  DLC
+            DLC: u4,
+            reserved8: u4,
+            ///  FMI
+            FMI: u8,
+            ///  TIME
+            TIME: u16,
+        }),
+        ///  mailbox data high register
+        RDL1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA0
+            DATA0: u8,
+            ///  DATA1
+            DATA1: u8,
+            ///  DATA2
+            DATA2: u8,
+            ///  DATA3
+            DATA3: u8,
+        }),
+        ///  mailbox data high register
+        RDH1R: mmio.Mmio(packed struct(u32) {
+            ///  DATA4
+            DATA4: u8,
+            ///  DATA5
+            DATA5: u8,
+            ///  DATA6
+            DATA6: u8,
+            ///  DATA7
+            DATA7: u8,
+        }),
+        reserved512: [48]u8,
+        ///  filter master register
+        FMR: mmio.Mmio(packed struct(u32) {
+            ///  FINIT
+            FINIT: u1,
+            reserved8: u7,
+            ///  CAN2SB
+            CAN2SB: u6,
+            padding: u18,
+        }),
+        ///  filter mode register
+        FM1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter mode
+            FBM0: u1,
+            ///  Filter mode
+            FBM1: u1,
+            ///  Filter mode
+            FBM2: u1,
+            ///  Filter mode
+            FBM3: u1,
+            ///  Filter mode
+            FBM4: u1,
+            ///  Filter mode
+            FBM5: u1,
+            ///  Filter mode
+            FBM6: u1,
+            ///  Filter mode
+            FBM7: u1,
+            ///  Filter mode
+            FBM8: u1,
+            ///  Filter mode
+            FBM9: u1,
+            ///  Filter mode
+            FBM10: u1,
+            ///  Filter mode
+            FBM11: u1,
+            ///  Filter mode
+            FBM12: u1,
+            ///  Filter mode
+            FBM13: u1,
+            ///  Filter mode
+            FBM14: u1,
+            ///  Filter mode
+            FBM15: u1,
+            ///  Filter mode
+            FBM16: u1,
+            ///  Filter mode
+            FBM17: u1,
+            ///  Filter mode
+            FBM18: u1,
+            ///  Filter mode
+            FBM19: u1,
+            ///  Filter mode
+            FBM20: u1,
+            ///  Filter mode
+            FBM21: u1,
+            ///  Filter mode
+            FBM22: u1,
+            ///  Filter mode
+            FBM23: u1,
+            ///  Filter mode
+            FBM24: u1,
+            ///  Filter mode
+            FBM25: u1,
+            ///  Filter mode
+            FBM26: u1,
+            ///  Filter mode
+            FBM27: u1,
+            padding: u4,
+        }),
+        reserved524: [4]u8,
+        ///  filter scale register
+        FS1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter scale configuration
+            FSC0: u1,
+            ///  Filter scale configuration
+            FSC1: u1,
+            ///  Filter scale configuration
+            FSC2: u1,
+            ///  Filter scale configuration
+            FSC3: u1,
+            ///  Filter scale configuration
+            FSC4: u1,
+            ///  Filter scale configuration
+            FSC5: u1,
+            ///  Filter scale configuration
+            FSC6: u1,
+            ///  Filter scale configuration
+            FSC7: u1,
+            ///  Filter scale configuration
+            FSC8: u1,
+            ///  Filter scale configuration
+            FSC9: u1,
+            ///  Filter scale configuration
+            FSC10: u1,
+            ///  Filter scale configuration
+            FSC11: u1,
+            ///  Filter scale configuration
+            FSC12: u1,
+            ///  Filter scale configuration
+            FSC13: u1,
+            ///  Filter scale configuration
+            FSC14: u1,
+            ///  Filter scale configuration
+            FSC15: u1,
+            ///  Filter scale configuration
+            FSC16: u1,
+            ///  Filter scale configuration
+            FSC17: u1,
+            ///  Filter scale configuration
+            FSC18: u1,
+            ///  Filter scale configuration
+            FSC19: u1,
+            ///  Filter scale configuration
+            FSC20: u1,
+            ///  Filter scale configuration
+            FSC21: u1,
+            ///  Filter scale configuration
+            FSC22: u1,
+            ///  Filter scale configuration
+            FSC23: u1,
+            ///  Filter scale configuration
+            FSC24: u1,
+            ///  Filter scale configuration
+            FSC25: u1,
+            ///  Filter scale configuration
+            FSC26: u1,
+            ///  Filter scale configuration
+            FSC27: u1,
+            padding: u4,
+        }),
+        reserved532: [4]u8,
+        ///  filter FIFO assignment register
+        FFA1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter FIFO assignment for filter 0
+            FFA0: u1,
+            ///  Filter FIFO assignment for filter 1
+            FFA1: u1,
+            ///  Filter FIFO assignment for filter 2
+            FFA2: u1,
+            ///  Filter FIFO assignment for filter 3
+            FFA3: u1,
+            ///  Filter FIFO assignment for filter 4
+            FFA4: u1,
+            ///  Filter FIFO assignment for filter 5
+            FFA5: u1,
+            ///  Filter FIFO assignment for filter 6
+            FFA6: u1,
+            ///  Filter FIFO assignment for filter 7
+            FFA7: u1,
+            ///  Filter FIFO assignment for filter 8
+            FFA8: u1,
+            ///  Filter FIFO assignment for filter 9
+            FFA9: u1,
+            ///  Filter FIFO assignment for filter 10
+            FFA10: u1,
+            ///  Filter FIFO assignment for filter 11
+            FFA11: u1,
+            ///  Filter FIFO assignment for filter 12
+            FFA12: u1,
+            ///  Filter FIFO assignment for filter 13
+            FFA13: u1,
+            ///  Filter FIFO assignment for filter 14
+            FFA14: u1,
+            ///  Filter FIFO assignment for filter 15
+            FFA15: u1,
+            ///  Filter FIFO assignment for filter 16
+            FFA16: u1,
+            ///  Filter FIFO assignment for filter 17
+            FFA17: u1,
+            ///  Filter FIFO assignment for filter 18
+            FFA18: u1,
+            ///  Filter FIFO assignment for filter 19
+            FFA19: u1,
+            ///  Filter FIFO assignment for filter 20
+            FFA20: u1,
+            ///  Filter FIFO assignment for filter 21
+            FFA21: u1,
+            ///  Filter FIFO assignment for filter 22
+            FFA22: u1,
+            ///  Filter FIFO assignment for filter 23
+            FFA23: u1,
+            ///  Filter FIFO assignment for filter 24
+            FFA24: u1,
+            ///  Filter FIFO assignment for filter 25
+            FFA25: u1,
+            ///  Filter FIFO assignment for filter 26
+            FFA26: u1,
+            ///  Filter FIFO assignment for filter 27
+            FFA27: u1,
+            padding: u4,
+        }),
+        reserved540: [4]u8,
+        ///  filter activation register
+        FA1R: mmio.Mmio(packed struct(u32) {
+            ///  Filter active
+            FACT0: u1,
+            ///  Filter active
+            FACT1: u1,
+            ///  Filter active
+            FACT2: u1,
+            ///  Filter active
+            FACT3: u1,
+            ///  Filter active
+            FACT4: u1,
+            ///  Filter active
+            FACT5: u1,
+            ///  Filter active
+            FACT6: u1,
+            ///  Filter active
+            FACT7: u1,
+            ///  Filter active
+            FACT8: u1,
+            ///  Filter active
+            FACT9: u1,
+            ///  Filter active
+            FACT10: u1,
+            ///  Filter active
+            FACT11: u1,
+            ///  Filter active
+            FACT12: u1,
+            ///  Filter active
+            FACT13: u1,
+            ///  Filter active
+            FACT14: u1,
+            ///  Filter active
+            FACT15: u1,
+            ///  Filter active
+            FACT16: u1,
+            ///  Filter active
+            FACT17: u1,
+            ///  Filter active
+            FACT18: u1,
+            ///  Filter active
+            FACT19: u1,
+            ///  Filter active
+            FACT20: u1,
+            ///  Filter active
+            FACT21: u1,
+            ///  Filter active
+            FACT22: u1,
+            ///  Filter active
+            FACT23: u1,
+            ///  Filter active
+            FACT24: u1,
+            ///  Filter active
+            FACT25: u1,
+            ///  Filter active
+            FACT26: u1,
+            ///  Filter active
+            FACT27: u1,
+            padding: u4,
+        }),
+        reserved576: [32]u8,
+        ///  Filter bank 0 register 1
+        F0R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 0 register 2
+        F0R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 1 register 1
+        F1R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 1 register 2
+        F1R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 2 register 1
+        F2R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 2 register 2
+        F2R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 3 register 1
+        F3R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 3 register 2
+        F3R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 1
+        F4R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 2
+        F4R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 5 register 1
+        F5R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 5 register 2
+        F5R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 6 register 1
+        F6R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 6 register 2
+        F6R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 7 register 1
+        F7R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 7 register 2
+        F7R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 8 register 1
+        F8R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 8 register 2
+        F8R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 9 register 1
+        F9R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 9 register 2
+        F9R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 10 register 1
+        F10R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 10 register 2
+        F10R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 11 register 1
+        F11R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 11 register 2
+        F11R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 4 register 1
+        F12R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 12 register 2
+        F12R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 13 register 1
+        F13R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 13 register 2
+        F13R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 14 register 1
+        F14R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 14 register 2
+        F14R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 15 register 1
+        F15R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 15 register 2
+        F15R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 16 register 1
+        F16R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 16 register 2
+        F16R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 17 register 1
+        F17R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 17 register 2
+        F17R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 18 register 1
+        F18R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 18 register 2
+        F18R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 19 register 1
+        F19R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 19 register 2
+        F19R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 20 register 1
+        F20R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 20 register 2
+        F20R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 21 register 1
+        F21R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 21 register 2
+        F21R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 22 register 1
+        F22R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 22 register 2
+        F22R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 23 register 1
+        F23R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 23 register 2
+        F23R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 24 register 1
+        F24R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 24 register 2
+        F24R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 25 register 1
+        F25R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 25 register 2
+        F25R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 26 register 1
+        F26R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 26 register 2
+        F26R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 27 register 1
+        F27R1: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+        ///  Filter bank 27 register 2
+        F27R2: mmio.Mmio(packed struct(u32) {
+            ///  Filter bits
+            FB0: u1,
+            ///  Filter bits
+            FB1: u1,
+            ///  Filter bits
+            FB2: u1,
+            ///  Filter bits
+            FB3: u1,
+            ///  Filter bits
+            FB4: u1,
+            ///  Filter bits
+            FB5: u1,
+            ///  Filter bits
+            FB6: u1,
+            ///  Filter bits
+            FB7: u1,
+            ///  Filter bits
+            FB8: u1,
+            ///  Filter bits
+            FB9: u1,
+            ///  Filter bits
+            FB10: u1,
+            ///  Filter bits
+            FB11: u1,
+            ///  Filter bits
+            FB12: u1,
+            ///  Filter bits
+            FB13: u1,
+            ///  Filter bits
+            FB14: u1,
+            ///  Filter bits
+            FB15: u1,
+            ///  Filter bits
+            FB16: u1,
+            ///  Filter bits
+            FB17: u1,
+            ///  Filter bits
+            FB18: u1,
+            ///  Filter bits
+            FB19: u1,
+            ///  Filter bits
+            FB20: u1,
+            ///  Filter bits
+            FB21: u1,
+            ///  Filter bits
+            FB22: u1,
+            ///  Filter bits
+            FB23: u1,
+            ///  Filter bits
+            FB24: u1,
+            ///  Filter bits
+            FB25: u1,
+            ///  Filter bits
+            FB26: u1,
+            ///  Filter bits
+            FB27: u1,
+            ///  Filter bits
+            FB28: u1,
+            ///  Filter bits
+            FB29: u1,
+            ///  Filter bits
+            FB30: u1,
+            ///  Filter bits
+            FB31: u1,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_PWRCLK = extern struct {
+        ///  OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)
+        FS_PCGCCTL: mmio.Mmio(packed struct(u32) {
+            ///  Stop PHY clock
+            STPPCLK: u1,
+            ///  Gate HCLK
+            GATEHCLK: u1,
+            reserved4: u2,
+            ///  PHY Suspended
+            PHYSUSP: u1,
+            padding: u27,
+        }),
+    };
+
+    ///  Digital-to-analog converter
+    pub const DAC = extern struct {
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 enable
+            EN1: u1,
+            ///  DAC channel1 output buffer disable
+            BOFF1: u1,
+            ///  DAC channel1 trigger enable
+            TEN1: u1,
+            ///  DAC channel1 trigger selection
+            TSEL1: u3,
+            ///  DAC channel1 noise/triangle wave generation enable
+            WAVE1: u2,
+            ///  DAC channel1 mask/amplitude selector
+            MAMP1: u4,
+            ///  DAC channel1 DMA enable
+            DMAEN1: u1,
+            ///  DAC channel1 DMA Underrun Interrupt enable
+            DMAUDRIE1: u1,
+            reserved16: u2,
+            ///  DAC channel2 enable
+            EN2: u1,
+            ///  DAC channel2 output buffer disable
+            BOFF2: u1,
+            ///  DAC channel2 trigger enable
+            TEN2: u1,
+            ///  DAC channel2 trigger selection
+            TSEL2: u3,
+            ///  DAC channel2 noise/triangle wave generation enable
+            WAVE2: u2,
+            ///  DAC channel2 mask/amplitude selector
+            MAMP2: u4,
+            ///  DAC channel2 DMA enable
+            DMAEN2: u1,
+            ///  DAC channel2 DMA underrun interrupt enable
+            DMAUDRIE2: u1,
+            padding: u2,
+        }),
+        ///  software trigger register
+        SWTRIGR: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 software trigger
+            SWTRIG1: u1,
+            ///  DAC channel2 software trigger
+            SWTRIG2: u1,
+            padding: u30,
+        }),
+        ///  channel1 12-bit right-aligned data holding register
+        DHR12R1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 12-bit right-aligned data
+            DACC1DHR: u12,
+            padding: u20,
+        }),
+        ///  channel1 12-bit left aligned data holding register
+        DHR12L1: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel1 12-bit left-aligned data
+            DACC1DHR: u12,
+            padding: u16,
+        }),
+        ///  channel1 8-bit right aligned data holding register
+        DHR8R1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 8-bit right-aligned data
+            DACC1DHR: u8,
+            padding: u24,
+        }),
+        ///  channel2 12-bit right aligned data holding register
+        DHR12R2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 12-bit right-aligned data
+            DACC2DHR: u12,
+            padding: u20,
+        }),
+        ///  channel2 12-bit left aligned data holding register
+        DHR12L2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel2 12-bit left-aligned data
+            DACC2DHR: u12,
+            padding: u16,
+        }),
+        ///  channel2 8-bit right-aligned data holding register
+        DHR8R2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 8-bit right-aligned data
+            DACC2DHR: u8,
+            padding: u24,
+        }),
+        ///  Dual DAC 12-bit right-aligned data holding register
+        DHR12RD: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 12-bit right-aligned data
+            DACC1DHR: u12,
+            reserved16: u4,
+            ///  DAC channel2 12-bit right-aligned data
+            DACC2DHR: u12,
+            padding: u4,
+        }),
+        ///  DUAL DAC 12-bit left aligned data holding register
+        DHR12LD: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  DAC channel1 12-bit left-aligned data
+            DACC1DHR: u12,
+            reserved20: u4,
+            ///  DAC channel2 12-bit left-aligned data
+            DACC2DHR: u12,
+        }),
+        ///  DUAL DAC 8-bit right aligned data holding register
+        DHR8RD: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 8-bit right-aligned data
+            DACC1DHR: u8,
+            ///  DAC channel2 8-bit right-aligned data
+            DACC2DHR: u8,
+            padding: u16,
+        }),
+        ///  channel1 data output register
+        DOR1: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel1 data output
+            DACC1DOR: u12,
+            padding: u20,
+        }),
+        ///  channel2 data output register
+        DOR2: mmio.Mmio(packed struct(u32) {
+            ///  DAC channel2 data output
+            DACC2DOR: u12,
+            padding: u20,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            reserved13: u13,
+            ///  DAC channel1 DMA underrun flag
+            DMAUDR1: u1,
+            reserved29: u15,
+            ///  DAC channel2 DMA underrun flag
+            DMAUDR2: u1,
+            padding: u2,
+        }),
+    };
+
+    ///  Power control
+    pub const PWR = extern struct {
+        ///  power control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Low-power deep sleep
+            LPDS: u1,
+            ///  Power down deepsleep
+            PDDS: u1,
+            ///  Clear wakeup flag
+            CWUF: u1,
+            ///  Clear standby flag
+            CSBF: u1,
+            ///  Power voltage detector enable
+            PVDE: u1,
+            ///  PVD level selection
+            PLS: u3,
+            ///  Disable backup domain write protection
+            DBP: u1,
+            ///  Flash power down in Stop mode
+            FPDS: u1,
+            ///  Low-Power Regulator Low Voltage in deepsleep
+            LPLVDS: u1,
+            ///  Main regulator low voltage in deepsleep mode
+            MRLVDS: u1,
+            reserved14: u2,
+            ///  Regulator voltage scaling output selection
+            VOS: u2,
+            ///  Over-drive enable
+            ODEN: u1,
+            ///  Over-drive switching enabled
+            ODSWEN: u1,
+            ///  Under-drive enable in stop mode
+            UDEN: u2,
+            padding: u12,
+        }),
+        ///  power control/status register
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  Wakeup flag
+            WUF: u1,
+            ///  Standby flag
+            SBF: u1,
+            ///  PVD output
+            PVDO: u1,
+            ///  Backup regulator ready
+            BRR: u1,
+            reserved8: u4,
+            ///  Enable WKUP pin
+            EWUP: u1,
+            ///  Backup regulator enable
+            BRE: u1,
+            reserved14: u4,
+            ///  Regulator voltage scaling output selection ready bit
+            VOSRDY: u1,
+            reserved16: u1,
+            ///  Over-drive mode ready
+            ODRDY: u1,
+            ///  Over-drive mode switching ready
+            ODSWRDY: u1,
+            ///  Under-drive ready flag
+            UDRDY: u2,
+            padding: u12,
+        }),
+    };
+
+    ///  Independent watchdog
+    pub const IWDG = extern struct {
+        ///  Key register
+        KR: mmio.Mmio(packed struct(u32) {
+            ///  Key value (write only, read 0000h)
+            KEY: u16,
+            padding: u16,
+        }),
+        ///  Prescaler register
+        PR: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler divider
+            PR: u3,
+            padding: u29,
+        }),
+        ///  Reload register
+        RLR: mmio.Mmio(packed struct(u32) {
+            ///  Watchdog counter reload value
+            RL: u12,
+            padding: u20,
+        }),
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Watchdog prescaler value update
+            PVU: u1,
+            ///  Watchdog counter reload value update
+            RVU: u1,
+            padding: u30,
+        }),
+    };
+
+    ///  Window watchdog
+    pub const WWDG = extern struct {
+        ///  Control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  7-bit counter (MSB to LSB)
+            T: u7,
+            ///  Activation bit
+            WDGA: u1,
+            padding: u24,
+        }),
+        ///  Configuration register
+        CFR: mmio.Mmio(packed struct(u32) {
+            ///  7-bit window value
+            W: u7,
+            ///  Timer base
+            WDGTB0: u1,
+            ///  Timer base
+            WDGTB1: u1,
+            ///  Early wakeup interrupt
+            EWI: u1,
+            padding: u22,
+        }),
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Early wakeup interrupt flag
+            EWIF: u1,
+            padding: u31,
+        }),
+    };
+
+    ///  Real-time clock
+    pub const RTC = extern struct {
+        ///  time register
+        TR: mmio.Mmio(packed struct(u32) {
+            ///  Second units in BCD format
+            SU: u4,
+            ///  Second tens in BCD format
+            ST: u3,
+            reserved8: u1,
+            ///  Minute units in BCD format
+            MNU: u4,
+            ///  Minute tens in BCD format
+            MNT: u3,
+            reserved16: u1,
+            ///  Hour units in BCD format
+            HU: u4,
+            ///  Hour tens in BCD format
+            HT: u2,
+            ///  AM/PM notation
+            PM: u1,
+            padding: u9,
+        }),
+        ///  date register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Date units in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            reserved8: u2,
+            ///  Month units in BCD format
+            MU: u4,
+            ///  Month tens in BCD format
+            MT: u1,
+            ///  Week day units
+            WDU: u3,
+            ///  Year units in BCD format
+            YU: u4,
+            ///  Year tens in BCD format
+            YT: u4,
+            padding: u8,
+        }),
+        ///  control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Wakeup clock selection
+            WCKSEL: u3,
+            ///  Time-stamp event active edge
+            TSEDGE: u1,
+            ///  Reference clock detection enable (50 or 60 Hz)
+            REFCKON: u1,
+            reserved6: u1,
+            ///  Hour format
+            FMT: u1,
+            ///  Coarse digital calibration enable
+            DCE: u1,
+            ///  Alarm A enable
+            ALRAE: u1,
+            ///  Alarm B enable
+            ALRBE: u1,
+            ///  Wakeup timer enable
+            WUTE: u1,
+            ///  Time stamp enable
+            TSE: u1,
+            ///  Alarm A interrupt enable
+            ALRAIE: u1,
+            ///  Alarm B interrupt enable
+            ALRBIE: u1,
+            ///  Wakeup timer interrupt enable
+            WUTIE: u1,
+            ///  Time-stamp interrupt enable
+            TSIE: u1,
+            ///  Add 1 hour (summer time change)
+            ADD1H: u1,
+            ///  Subtract 1 hour (winter time change)
+            SUB1H: u1,
+            ///  Backup
+            BKP: u1,
+            reserved20: u1,
+            ///  Output polarity
+            POL: u1,
+            ///  Output selection
+            OSEL: u2,
+            ///  Calibration output enable
+            COE: u1,
+            padding: u8,
+        }),
+        ///  initialization and status register
+        ISR: mmio.Mmio(packed struct(u32) {
+            ///  Alarm A write flag
+            ALRAWF: u1,
+            ///  Alarm B write flag
+            ALRBWF: u1,
+            ///  Wakeup timer write flag
+            WUTWF: u1,
+            ///  Shift operation pending
+            SHPF: u1,
+            ///  Initialization status flag
+            INITS: u1,
+            ///  Registers synchronization flag
+            RSF: u1,
+            ///  Initialization flag
+            INITF: u1,
+            ///  Initialization mode
+            INIT: u1,
+            ///  Alarm A flag
+            ALRAF: u1,
+            ///  Alarm B flag
+            ALRBF: u1,
+            ///  Wakeup timer flag
+            WUTF: u1,
+            ///  Time-stamp flag
+            TSF: u1,
+            ///  Time-stamp overflow flag
+            TSOVF: u1,
+            ///  Tamper detection flag
+            TAMP1F: u1,
+            ///  TAMPER2 detection flag
+            TAMP2F: u1,
+            reserved16: u1,
+            ///  Recalibration pending Flag
+            RECALPF: u1,
+            padding: u15,
+        }),
+        ///  prescaler register
+        PRER: mmio.Mmio(packed struct(u32) {
+            ///  Synchronous prescaler factor
+            PREDIV_S: u15,
+            reserved16: u1,
+            ///  Asynchronous prescaler factor
+            PREDIV_A: u7,
+            padding: u9,
+        }),
+        ///  wakeup timer register
+        WUTR: mmio.Mmio(packed struct(u32) {
+            ///  Wakeup auto-reload value bits
+            WUT: u16,
+            padding: u16,
+        }),
+        ///  calibration register
+        CALIBR: mmio.Mmio(packed struct(u32) {
+            ///  Digital calibration
+            DC: u5,
+            reserved7: u2,
+            ///  Digital calibration sign
+            DCS: u1,
+            padding: u24,
+        }),
+        ///  alarm A register
+        ALRMAR: mmio.Mmio(packed struct(u32) {
+            ///  Second units in BCD format
+            SU: u4,
+            ///  Second tens in BCD format
+            ST: u3,
+            ///  Alarm A seconds mask
+            MSK1: u1,
+            ///  Minute units in BCD format
+            MNU: u4,
+            ///  Minute tens in BCD format
+            MNT: u3,
+            ///  Alarm A minutes mask
+            MSK2: u1,
+            ///  Hour units in BCD format
+            HU: u4,
+            ///  Hour tens in BCD format
+            HT: u2,
+            ///  AM/PM notation
+            PM: u1,
+            ///  Alarm A hours mask
+            MSK3: u1,
+            ///  Date units or day in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            ///  Week day selection
+            WDSEL: u1,
+            ///  Alarm A date mask
+            MSK4: u1,
+        }),
+        ///  alarm B register
+        ALRMBR: mmio.Mmio(packed struct(u32) {
+            ///  Second units in BCD format
+            SU: u4,
+            ///  Second tens in BCD format
+            ST: u3,
+            ///  Alarm B seconds mask
+            MSK1: u1,
+            ///  Minute units in BCD format
+            MNU: u4,
+            ///  Minute tens in BCD format
+            MNT: u3,
+            ///  Alarm B minutes mask
+            MSK2: u1,
+            ///  Hour units in BCD format
+            HU: u4,
+            ///  Hour tens in BCD format
+            HT: u2,
+            ///  AM/PM notation
+            PM: u1,
+            ///  Alarm B hours mask
+            MSK3: u1,
+            ///  Date units or day in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            ///  Week day selection
+            WDSEL: u1,
+            ///  Alarm B date mask
+            MSK4: u1,
+        }),
+        ///  write protection register
+        WPR: mmio.Mmio(packed struct(u32) {
+            ///  Write protection key
+            KEY: u8,
+            padding: u24,
+        }),
+        ///  sub second register
+        SSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub second value
+            SS: u16,
+            padding: u16,
+        }),
+        ///  shift control register
+        SHIFTR: mmio.Mmio(packed struct(u32) {
+            ///  Subtract a fraction of a second
+            SUBFS: u15,
+            reserved31: u16,
+            ///  Add one second
+            ADD1S: u1,
+        }),
+        ///  time stamp time register
+        TSTR: mmio.Mmio(packed struct(u32) {
+            ///  Tamper 1 detection enable
+            TAMP1E: u1,
+            ///  Active level for tamper 1
+            TAMP1TRG: u1,
+            ///  Tamper interrupt enable
+            TAMPIE: u1,
+            reserved16: u13,
+            ///  TAMPER1 mapping
+            TAMP1INSEL: u1,
+            ///  TIMESTAMP mapping
+            TSINSEL: u1,
+            ///  AFO_ALARM output type
+            ALARMOUTTYPE: u1,
+            padding: u13,
+        }),
+        ///  time stamp date register
+        TSDR: mmio.Mmio(packed struct(u32) {
+            ///  Date units in BCD format
+            DU: u4,
+            ///  Date tens in BCD format
+            DT: u2,
+            reserved8: u2,
+            ///  Month units in BCD format
+            MU: u4,
+            ///  Month tens in BCD format
+            MT: u1,
+            ///  Week day units
+            WDU: u3,
+            padding: u16,
+        }),
+        ///  timestamp sub second register
+        TSSSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub second value
+            SS: u16,
+            padding: u16,
+        }),
+        ///  calibration register
+        CALR: mmio.Mmio(packed struct(u32) {
+            ///  Calibration minus
+            CALM: u9,
+            reserved13: u4,
+            ///  Use a 16-second calibration cycle period
+            CALW16: u1,
+            ///  Use an 8-second calibration cycle period
+            CALW8: u1,
+            ///  Increase frequency of RTC by 488.5 ppm
+            CALP: u1,
+            padding: u16,
+        }),
+        ///  tamper and alternate function configuration register
+        TAFCR: mmio.Mmio(packed struct(u32) {
+            ///  Tamper 1 detection enable
+            TAMP1E: u1,
+            ///  Active level for tamper 1
+            TAMP1TRG: u1,
+            ///  Tamper interrupt enable
+            TAMPIE: u1,
+            ///  Tamper 2 detection enable
+            TAMP2E: u1,
+            ///  Active level for tamper 2
+            TAMP2TRG: u1,
+            reserved7: u2,
+            ///  Activate timestamp on tamper detection event
+            TAMPTS: u1,
+            ///  Tamper sampling frequency
+            TAMPFREQ: u3,
+            ///  Tamper filter count
+            TAMPFLT: u2,
+            ///  Tamper precharge duration
+            TAMPPRCH: u2,
+            ///  TAMPER pull-up disable
+            TAMPPUDIS: u1,
+            ///  TAMPER1 mapping
+            TAMP1INSEL: u1,
+            ///  TIMESTAMP mapping
+            TSINSEL: u1,
+            ///  AFO_ALARM output type
+            ALARMOUTTYPE: u1,
+            padding: u13,
+        }),
+        ///  alarm A sub second register
+        ALRMASSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub seconds value
+            SS: u15,
+            reserved24: u9,
+            ///  Mask the most-significant bits starting at this bit
+            MASKSS: u4,
+            padding: u4,
+        }),
+        ///  alarm B sub second register
+        ALRMBSSR: mmio.Mmio(packed struct(u32) {
+            ///  Sub seconds value
+            SS: u15,
+            reserved24: u9,
+            ///  Mask the most-significant bits starting at this bit
+            MASKSS: u4,
+            padding: u4,
+        }),
+        reserved80: [4]u8,
+        ///  backup register
+        BKP0R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP1R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP2R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP3R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP4R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP5R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP6R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP7R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP8R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP9R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP10R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP11R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP12R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP13R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP14R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP15R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP16R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP17R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP18R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+        ///  backup register
+        BKP19R: mmio.Mmio(packed struct(u32) {
+            ///  BKP
+            BKP: u32,
+        }),
+    };
+
+    ///  Universal synchronous asynchronous receiver transmitter
+    pub const UART4 = extern struct {
+        ///  Status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Parity error
+            PE: u1,
+            ///  Framing error
+            FE: u1,
+            ///  Noise detected flag
+            NF: u1,
+            ///  Overrun error
+            ORE: u1,
+            ///  IDLE line detected
+            IDLE: u1,
+            ///  Read data register not empty
+            RXNE: u1,
+            ///  Transmission complete
+            TC: u1,
+            ///  Transmit data register empty
+            TXE: u1,
+            ///  LIN break detection flag
+            LBD: u1,
+            padding: u23,
+        }),
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data value
+            DR: u9,
+            padding: u23,
+        }),
+        ///  Baud rate register
+        BRR: mmio.Mmio(packed struct(u32) {
+            ///  fraction of USARTDIV
+            DIV_Fraction: u4,
+            ///  mantissa of USARTDIV
+            DIV_Mantissa: u12,
+            padding: u16,
+        }),
+        ///  Control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Send break
+            SBK: u1,
+            ///  Receiver wakeup
+            RWU: u1,
+            ///  Receiver enable
+            RE: u1,
+            ///  Transmitter enable
+            TE: u1,
+            ///  IDLE interrupt enable
+            IDLEIE: u1,
+            ///  RXNE interrupt enable
+            RXNEIE: u1,
+            ///  Transmission complete interrupt enable
+            TCIE: u1,
+            ///  TXE interrupt enable
+            TXEIE: u1,
+            ///  PE interrupt enable
+            PEIE: u1,
+            ///  Parity selection
+            PS: u1,
+            ///  Parity control enable
+            PCE: u1,
+            ///  Wakeup method
+            WAKE: u1,
+            ///  Word length
+            M: u1,
+            ///  USART enable
+            UE: u1,
+            reserved15: u1,
+            ///  Oversampling mode
+            OVER8: u1,
+            padding: u16,
+        }),
+        ///  Control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Address of the USART node
+            ADD: u4,
+            reserved5: u1,
+            ///  lin break detection length
+            LBDL: u1,
+            ///  LIN break detection interrupt enable
+            LBDIE: u1,
+            reserved12: u5,
+            ///  STOP bits
+            STOP: u2,
+            ///  LIN mode enable
+            LINEN: u1,
+            padding: u17,
+        }),
+        ///  Control register 3
+        CR3: mmio.Mmio(packed struct(u32) {
+            ///  Error interrupt enable
+            EIE: u1,
+            ///  IrDA mode enable
+            IREN: u1,
+            ///  IrDA low-power
+            IRLP: u1,
+            ///  Half-duplex selection
+            HDSEL: u1,
+            reserved6: u2,
+            ///  DMA enable receiver
+            DMAR: u1,
+            ///  DMA enable transmitter
+            DMAT: u1,
+            reserved11: u3,
+            ///  One sample bit method enable
+            ONEBIT: u1,
+            padding: u20,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_DEVICE = extern struct {
+        ///  OTG_FS device configuration register (OTG_FS_DCFG)
+        FS_DCFG: mmio.Mmio(packed struct(u32) {
+            ///  Device speed
+            DSPD: u2,
+            ///  Non-zero-length status OUT handshake
+            NZLSOHSK: u1,
+            reserved4: u1,
+            ///  Device address
+            DAD: u7,
+            ///  Periodic frame interval
+            PFIVL: u2,
+            padding: u19,
+        }),
+        ///  OTG_FS device control register (OTG_FS_DCTL)
+        FS_DCTL: mmio.Mmio(packed struct(u32) {
+            ///  Remote wakeup signaling
+            RWUSIG: u1,
+            ///  Soft disconnect
+            SDIS: u1,
+            ///  Global IN NAK status
+            GINSTS: u1,
+            ///  Global OUT NAK status
+            GONSTS: u1,
+            ///  Test control
+            TCTL: u3,
+            ///  Set global IN NAK
+            SGINAK: u1,
+            ///  Clear global IN NAK
+            CGINAK: u1,
+            ///  Set global OUT NAK
+            SGONAK: u1,
+            ///  Clear global OUT NAK
+            CGONAK: u1,
+            ///  Power-on programming done
+            POPRGDNE: u1,
+            padding: u20,
+        }),
+        ///  OTG_FS device status register (OTG_FS_DSTS)
+        FS_DSTS: mmio.Mmio(packed struct(u32) {
+            ///  Suspend status
+            SUSPSTS: u1,
+            ///  Enumerated speed
+            ENUMSPD: u2,
+            ///  Erratic error
+            EERR: u1,
+            reserved8: u4,
+            ///  Frame number of the received SOF
+            FNSOF: u14,
+            padding: u10,
+        }),
+        reserved16: [4]u8,
+        ///  OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
+        FS_DIEPMSK: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  Timeout condition mask (Non-isochronous endpoints)
+            TOM: u1,
+            ///  IN token received when TxFIFO empty mask
+            ITTXFEMSK: u1,
+            ///  IN token received with EP mismatch mask
+            INEPNMM: u1,
+            ///  IN endpoint NAK effective mask
+            INEPNEM: u1,
+            padding: u25,
+        }),
+        ///  OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
+        FS_DOEPMSK: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed interrupt mask
+            XFRCM: u1,
+            ///  Endpoint disabled interrupt mask
+            EPDM: u1,
+            reserved3: u1,
+            ///  SETUP phase done mask
+            STUPM: u1,
+            ///  OUT token received when endpoint disabled mask
+            OTEPDM: u1,
+            padding: u27,
+        }),
+        ///  OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
+        FS_DAINT: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint interrupt bits
+            IEPINT: u16,
+            ///  OUT endpoint interrupt bits
+            OEPINT: u16,
+        }),
+        ///  OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
+        FS_DAINTMSK: mmio.Mmio(packed struct(u32) {
+            ///  IN EP interrupt mask bits
+            IEPM: u16,
+            ///  OUT endpoint interrupt bits
+            OEPINT: u16,
+        }),
+        reserved40: [8]u8,
+        ///  OTG_FS device VBUS discharge time register
+        DVBUSDIS: mmio.Mmio(packed struct(u32) {
+            ///  Device VBUS discharge time
+            VBUSDT: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS device VBUS pulsing time register
+        DVBUSPULSE: mmio.Mmio(packed struct(u32) {
+            ///  Device VBUS pulsing time
+            DVBUSP: u12,
+            padding: u20,
+        }),
+        reserved52: [4]u8,
+        ///  OTG_FS device IN endpoint FIFO empty interrupt mask register
+        DIEPEMPMSK: mmio.Mmio(packed struct(u32) {
+            ///  IN EP Tx FIFO empty interrupt mask bits
+            INEPTXFEM: u16,
+            padding: u16,
+        }),
+        reserved256: [200]u8,
+        ///  OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
+        FS_DIEPCTL0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u2,
+            reserved15: u13,
+            ///  USB active endpoint
+            USBAEP: u1,
+            reserved17: u1,
+            ///  NAK status
+            NAKSTS: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            reserved21: u1,
+            ///  STALL handshake
+            STALL: u1,
+            ///  TxFIFO number
+            TXFNUM: u4,
+            ///  Clear NAK
+            CNAK: u1,
+            ///  Set NAK
+            SNAK: u1,
+            reserved30: u2,
+            ///  Endpoint disable
+            EPDIS: u1,
+            ///  Endpoint enable
+            EPENA: u1,
+        }),
+        reserved264: [4]u8,
+        ///  device endpoint-x interrupt register
+        DIEPINT0: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved272: [4]u8,
+        ///  device endpoint-0 transfer size register
+        DIEPTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u7,
+            reserved19: u12,
+            ///  Packet count
+            PKTCNT: u2,
+            padding: u11,
+        }),
+        reserved280: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS0: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved288: [4]u8,
+        ///  OTG device endpoint-1 control register
+        DIEPCTL1: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            reserved21: u1,
+            ///  Stall
+            Stall: u1,
+            ///  TXFNUM
+            TXFNUM: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM/SD1PID
+            SODDFRM_SD1PID: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved296: [4]u8,
+        ///  device endpoint-1 interrupt register
+        DIEPINT1: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved304: [4]u8,
+        ///  device endpoint-1 transfer size register
+        DIEPTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        reserved312: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS1: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved320: [4]u8,
+        ///  OTG device endpoint-2 control register
+        DIEPCTL2: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            reserved21: u1,
+            ///  Stall
+            Stall: u1,
+            ///  TXFNUM
+            TXFNUM: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved328: [4]u8,
+        ///  device endpoint-2 interrupt register
+        DIEPINT2: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved336: [4]u8,
+        ///  device endpoint-2 transfer size register
+        DIEPTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        reserved344: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS2: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved352: [4]u8,
+        ///  OTG device endpoint-3 control register
+        DIEPCTL3: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            reserved21: u1,
+            ///  Stall
+            Stall: u1,
+            ///  TXFNUM
+            TXFNUM: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved360: [4]u8,
+        ///  device endpoint-3 interrupt register
+        DIEPINT3: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  TOC
+            TOC: u1,
+            ///  ITTXFE
+            ITTXFE: u1,
+            reserved6: u1,
+            ///  INEPNE
+            INEPNE: u1,
+            ///  TXFE
+            TXFE: u1,
+            padding: u24,
+        }),
+        reserved368: [4]u8,
+        ///  device endpoint-3 transfer size register
+        DIEPTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Multi count
+            MCNT: u2,
+            padding: u1,
+        }),
+        reserved376: [4]u8,
+        ///  OTG_FS device IN endpoint transmit FIFO status register
+        DTXFSTS3: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint TxFIFO space available
+            INEPTFSAV: u16,
+            padding: u16,
+        }),
+        reserved768: [388]u8,
+        ///  device endpoint-0 control register
+        DOEPCTL0: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u2,
+            reserved15: u13,
+            ///  USBAEP
+            USBAEP: u1,
+            reserved17: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            reserved30: u2,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved776: [4]u8,
+        ///  device endpoint-0 interrupt register
+        DOEPINT0: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved784: [4]u8,
+        ///  device OUT endpoint-0 transfer size register
+        DOEPTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u7,
+            reserved19: u12,
+            ///  Packet count
+            PKTCNT: u1,
+            reserved29: u9,
+            ///  SETUP packet count
+            STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved800: [12]u8,
+        ///  device endpoint-1 control register
+        DOEPCTL1: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved808: [4]u8,
+        ///  device endpoint-1 interrupt register
+        DOEPINT1: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved816: [4]u8,
+        ///  device OUT endpoint-1 transfer size register
+        DOEPTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved832: [12]u8,
+        ///  device endpoint-2 control register
+        DOEPCTL2: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved840: [4]u8,
+        ///  device endpoint-2 interrupt register
+        DOEPINT2: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved848: [4]u8,
+        ///  device OUT endpoint-2 transfer size register
+        DOEPTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+        reserved864: [12]u8,
+        ///  device endpoint-3 control register
+        DOEPCTL3: mmio.Mmio(packed struct(u32) {
+            ///  MPSIZ
+            MPSIZ: u11,
+            reserved15: u4,
+            ///  USBAEP
+            USBAEP: u1,
+            ///  EONUM/DPID
+            EONUM_DPID: u1,
+            ///  NAKSTS
+            NAKSTS: u1,
+            ///  EPTYP
+            EPTYP: u2,
+            ///  SNPM
+            SNPM: u1,
+            ///  Stall
+            Stall: u1,
+            reserved26: u4,
+            ///  CNAK
+            CNAK: u1,
+            ///  SNAK
+            SNAK: u1,
+            ///  SD0PID/SEVNFRM
+            SD0PID_SEVNFRM: u1,
+            ///  SODDFRM
+            SODDFRM: u1,
+            ///  EPDIS
+            EPDIS: u1,
+            ///  EPENA
+            EPENA: u1,
+        }),
+        reserved872: [4]u8,
+        ///  device endpoint-3 interrupt register
+        DOEPINT3: mmio.Mmio(packed struct(u32) {
+            ///  XFRC
+            XFRC: u1,
+            ///  EPDISD
+            EPDISD: u1,
+            reserved3: u1,
+            ///  STUP
+            STUP: u1,
+            ///  OTEPDIS
+            OTEPDIS: u1,
+            reserved6: u1,
+            ///  B2BSTUP
+            B2BSTUP: u1,
+            padding: u25,
+        }),
+        reserved880: [4]u8,
+        ///  device OUT endpoint-3 transfer size register
+        DOEPTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Received data PID/SETUP packet count
+            RXDPID_STUPCNT: u2,
+            padding: u1,
+        }),
+    };
+
+    ///  Common ADC registers
+    pub const C_ADC = extern struct {
+        ///  ADC Common status register
+        CSR: mmio.Mmio(packed struct(u32) {
+            ///  Analog watchdog flag of ADC 1
+            AWD1: u1,
+            ///  End of conversion of ADC 1
+            EOC1: u1,
+            ///  Injected channel end of conversion of ADC 1
+            JEOC1: u1,
+            ///  Injected channel Start flag of ADC 1
+            JSTRT1: u1,
+            ///  Regular channel Start flag of ADC 1
+            STRT1: u1,
+            ///  Overrun flag of ADC 1
+            OVR1: u1,
+            reserved8: u2,
+            ///  Analog watchdog flag of ADC 2
+            AWD2: u1,
+            ///  End of conversion of ADC 2
+            EOC2: u1,
+            ///  Injected channel end of conversion of ADC 2
+            JEOC2: u1,
+            ///  Injected channel Start flag of ADC 2
+            JSTRT2: u1,
+            ///  Regular channel Start flag of ADC 2
+            STRT2: u1,
+            ///  Overrun flag of ADC 2
+            OVR2: u1,
+            reserved16: u2,
+            ///  Analog watchdog flag of ADC 3
+            AWD3: u1,
+            ///  End of conversion of ADC 3
+            EOC3: u1,
+            ///  Injected channel end of conversion of ADC 3
+            JEOC3: u1,
+            ///  Injected channel Start flag of ADC 3
+            JSTRT3: u1,
+            ///  Regular channel Start flag of ADC 3
+            STRT3: u1,
+            ///  Overrun flag of ADC3
+            OVR3: u1,
+            padding: u10,
+        }),
+        ///  ADC common control register
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Multi ADC mode selection
+            MULT: u5,
+            reserved8: u3,
+            ///  Delay between 2 sampling phases
+            DELAY: u4,
+            reserved13: u1,
+            ///  DMA disable selection for multi-ADC mode
+            DDS: u1,
+            ///  Direct memory access mode for multi ADC mode
+            DMA: u2,
+            ///  ADC prescaler
+            ADCPRE: u2,
+            reserved22: u4,
+            ///  VBAT enable
+            VBATE: u1,
+            ///  Temperature sensor and VREFINT enable
+            TSVREFE: u1,
+            padding: u8,
+        }),
+        ///  ADC common regular data register for dual and triple modes
+        CDR: mmio.Mmio(packed struct(u32) {
+            ///  1st data item of a pair of regular conversions
+            DATA1: u16,
+            ///  2nd data item of a pair of regular conversions
+            DATA2: u16,
+        }),
+    };
+
+    ///  Advanced-timers
+    pub const TIM1 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/compare preloaded control
+            CCPC: u1,
+            reserved2: u1,
+            ///  Capture/compare control update selection
+            CCUS: u1,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            ///  Output Idle state 1
+            OIS1: u1,
+            ///  Output Idle state 1
+            OIS1N: u1,
+            ///  Output Idle state 2
+            OIS2: u1,
+            ///  Output Idle state 2
+            OIS2N: u1,
+            ///  Output Idle state 3
+            OIS3: u1,
+            ///  Output Idle state 3
+            OIS3N: u1,
+            ///  Output Idle state 4
+            OIS4: u1,
+            padding: u17,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            padding: u16,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            ///  COM interrupt enable
+            COMIE: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            ///  Break interrupt enable
+            BIE: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            ///  COM DMA request enable
+            COMDE: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            ///  COM interrupt flag
+            COMIF: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            ///  Break interrupt flag
+            BIF: u1,
+            reserved9: u1,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            padding: u19,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            ///  Capture/Compare control update generation
+            COMG: u1,
+            ///  Trigger generation
+            TG: u1,
+            ///  Break generation
+            BG: u1,
+            padding: u24,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            ///  Output Compare 1 clear enable
+            OC1CE: u1,
+            ///  Capture/Compare 2 selection
+            CC2S: u2,
+            ///  Output Compare 2 fast enable
+            OC2FE: u1,
+            ///  Output Compare 2 preload enable
+            OC2PE: u1,
+            ///  Output Compare 2 mode
+            OC2M: u3,
+            ///  Output Compare 2 clear enable
+            OC2CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare mode register 2 (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 3 selection
+            CC3S: u2,
+            ///  Output compare 3 fast enable
+            OC3FE: u1,
+            ///  Output compare 3 preload enable
+            OC3PE: u1,
+            ///  Output compare 3 mode
+            OC3M: u3,
+            ///  Output compare 3 clear enable
+            OC3CE: u1,
+            ///  Capture/Compare 4 selection
+            CC4S: u2,
+            ///  Output compare 4 fast enable
+            OC4FE: u1,
+            ///  Output compare 4 preload enable
+            OC4PE: u1,
+            ///  Output compare 4 mode
+            OC4M: u3,
+            ///  Output compare 4 clear enable
+            OC4CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            ///  Capture/Compare 1 complementary output enable
+            CC1NE: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            ///  Capture/Compare 2 complementary output enable
+            CC2NE: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            ///  Capture/Compare 3 complementary output enable
+            CC3NE: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            padding: u18,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        ///  repetition counter register
+        RCR: mmio.Mmio(packed struct(u32) {
+            ///  Repetition counter value
+            REP: u8,
+            padding: u24,
+        }),
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 2 value
+            CCR2: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare value
+            CCR3: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare value
+            CCR4: u16,
+            padding: u16,
+        }),
+        ///  break and dead-time register
+        BDTR: mmio.Mmio(packed struct(u32) {
+            ///  Dead-time generator setup
+            DTG: u8,
+            ///  Lock configuration
+            LOCK: u2,
+            ///  Off-state selection for Idle mode
+            OSSI: u1,
+            ///  Off-state selection for Run mode
+            OSSR: u1,
+            ///  Break enable
+            BKE: u1,
+            ///  Break polarity
+            BKP: u1,
+            ///  Automatic output enable
+            AOE: u1,
+            ///  Main output enable
+            MOE: u1,
+            padding: u16,
+        }),
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_HOST = extern struct {
+        ///  OTG_FS host configuration register (OTG_FS_HCFG)
+        FS_HCFG: mmio.Mmio(packed struct(u32) {
+            ///  FS/LS PHY clock select
+            FSLSPCS: u2,
+            ///  FS- and LS-only support
+            FSLSS: u1,
+            padding: u29,
+        }),
+        ///  OTG_FS Host frame interval register
+        HFIR: mmio.Mmio(packed struct(u32) {
+            ///  Frame interval
+            FRIVL: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
+        FS_HFNUM: mmio.Mmio(packed struct(u32) {
+            ///  Frame number
+            FRNUM: u16,
+            ///  Frame time remaining
+            FTREM: u16,
+        }),
+        reserved16: [4]u8,
+        ///  OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
+        FS_HPTXSTS: mmio.Mmio(packed struct(u32) {
+            ///  Periodic transmit data FIFO space available
+            PTXFSAVL: u16,
+            ///  Periodic transmit request queue space available
+            PTXQSAV: u8,
+            ///  Top of the periodic transmit request queue
+            PTXQTOP: u8,
+        }),
+        ///  OTG_FS Host all channels interrupt register
+        HAINT: mmio.Mmio(packed struct(u32) {
+            ///  Channel interrupts
+            HAINT: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS host all channels interrupt mask register
+        HAINTMSK: mmio.Mmio(packed struct(u32) {
+            ///  Channel interrupt mask
+            HAINTM: u16,
+            padding: u16,
+        }),
+        reserved64: [36]u8,
+        ///  OTG_FS host port control and status register (OTG_FS_HPRT)
+        FS_HPRT: mmio.Mmio(packed struct(u32) {
+            ///  Port connect status
+            PCSTS: u1,
+            ///  Port connect detected
+            PCDET: u1,
+            ///  Port enable
+            PENA: u1,
+            ///  Port enable/disable change
+            PENCHNG: u1,
+            ///  Port overcurrent active
+            POCA: u1,
+            ///  Port overcurrent change
+            POCCHNG: u1,
+            ///  Port resume
+            PRES: u1,
+            ///  Port suspend
+            PSUSP: u1,
+            ///  Port reset
+            PRST: u1,
+            reserved10: u1,
+            ///  Port line status
+            PLSTS: u2,
+            ///  Port power
+            PPWR: u1,
+            ///  Port test control
+            PTCTL: u4,
+            ///  Port speed
+            PSPD: u2,
+            padding: u13,
+        }),
+        reserved256: [188]u8,
+        ///  OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
+        FS_HCCHAR0: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved264: [4]u8,
+        ///  OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
+        FS_HCINT0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
+        FS_HCINTMSK0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-0 transfer size register
+        FS_HCTSIZ0: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved288: [12]u8,
+        ///  OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)
+        FS_HCCHAR1: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved296: [4]u8,
+        ///  OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)
+        FS_HCINT1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)
+        FS_HCINTMSK1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-1 transfer size register
+        FS_HCTSIZ1: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved320: [12]u8,
+        ///  OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)
+        FS_HCCHAR2: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved328: [4]u8,
+        ///  OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)
+        FS_HCINT2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)
+        FS_HCINTMSK2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-2 transfer size register
+        FS_HCTSIZ2: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved352: [12]u8,
+        ///  OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)
+        FS_HCCHAR3: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved360: [4]u8,
+        ///  OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)
+        FS_HCINT3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)
+        FS_HCINTMSK3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-3 transfer size register
+        FS_HCTSIZ3: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved384: [12]u8,
+        ///  OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)
+        FS_HCCHAR4: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved392: [4]u8,
+        ///  OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)
+        FS_HCINT4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)
+        FS_HCINTMSK4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-x transfer size register
+        FS_HCTSIZ4: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved416: [12]u8,
+        ///  OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)
+        FS_HCCHAR5: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved424: [4]u8,
+        ///  OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)
+        FS_HCINT5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)
+        FS_HCINTMSK5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-5 transfer size register
+        FS_HCTSIZ5: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved448: [12]u8,
+        ///  OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)
+        FS_HCCHAR6: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved456: [4]u8,
+        ///  OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)
+        FS_HCINT6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)
+        FS_HCINTMSK6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-6 transfer size register
+        FS_HCTSIZ6: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+        reserved480: [12]u8,
+        ///  OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)
+        FS_HCCHAR7: mmio.Mmio(packed struct(u32) {
+            ///  Maximum packet size
+            MPSIZ: u11,
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Endpoint direction
+            EPDIR: u1,
+            reserved17: u1,
+            ///  Low-speed device
+            LSDEV: u1,
+            ///  Endpoint type
+            EPTYP: u2,
+            ///  Multicount
+            MCNT: u2,
+            ///  Device address
+            DAD: u7,
+            ///  Odd frame
+            ODDFRM: u1,
+            ///  Channel disable
+            CHDIS: u1,
+            ///  Channel enable
+            CHENA: u1,
+        }),
+        reserved488: [4]u8,
+        ///  OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)
+        FS_HCINT7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed
+            XFRC: u1,
+            ///  Channel halted
+            CHH: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt
+            STALL: u1,
+            ///  NAK response received interrupt
+            NAK: u1,
+            ///  ACK response received/transmitted interrupt
+            ACK: u1,
+            reserved7: u1,
+            ///  Transaction error
+            TXERR: u1,
+            ///  Babble error
+            BBERR: u1,
+            ///  Frame overrun
+            FRMOR: u1,
+            ///  Data toggle error
+            DTERR: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)
+        FS_HCINTMSK7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer completed mask
+            XFRCM: u1,
+            ///  Channel halted mask
+            CHHM: u1,
+            reserved3: u1,
+            ///  STALL response received interrupt mask
+            STALLM: u1,
+            ///  NAK response received interrupt mask
+            NAKM: u1,
+            ///  ACK response received/transmitted interrupt mask
+            ACKM: u1,
+            ///  response received interrupt mask
+            NYET: u1,
+            ///  Transaction error mask
+            TXERRM: u1,
+            ///  Babble error mask
+            BBERRM: u1,
+            ///  Frame overrun mask
+            FRMORM: u1,
+            ///  Data toggle error mask
+            DTERRM: u1,
+            padding: u21,
+        }),
+        ///  OTG_FS host channel-7 transfer size register
+        FS_HCTSIZ7: mmio.Mmio(packed struct(u32) {
+            ///  Transfer size
+            XFRSIZ: u19,
+            ///  Packet count
+            PKTCNT: u10,
+            ///  Data PID
+            DPID: u2,
+            padding: u1,
+        }),
+    };
+
+    ///  General purpose timers
+    pub const TIM2 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            padding: u24,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            padding: u16,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            reserved6: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            reserved8: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            reserved14: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            reserved6: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            reserved9: u2,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            padding: u19,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            reserved6: u1,
+            ///  Trigger generation
+            TG: u1,
+            padding: u25,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC1S
+            CC1S: u2,
+            ///  OC1FE
+            OC1FE: u1,
+            ///  OC1PE
+            OC1PE: u1,
+            ///  OC1M
+            OC1M: u3,
+            ///  OC1CE
+            OC1CE: u1,
+            ///  CC2S
+            CC2S: u2,
+            ///  OC2FE
+            OC2FE: u1,
+            ///  OC2PE
+            OC2PE: u1,
+            ///  OC2M
+            OC2M: u3,
+            ///  OC2CE
+            OC2CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare mode register 2 (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC3S
+            CC3S: u2,
+            ///  OC3FE
+            OC3FE: u1,
+            ///  OC3PE
+            OC3PE: u1,
+            ///  OC3M
+            OC3M: u3,
+            ///  OC3CE
+            OC3CE: u1,
+            ///  CC4S
+            CC4S: u2,
+            ///  OC4FE
+            OC4FE: u1,
+            ///  OC4PE
+            OC4PE: u1,
+            ///  OC4M
+            OC4M: u3,
+            ///  O24CE
+            O24CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved7: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            reserved11: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            reserved15: u1,
+            ///  Capture/Compare 4 output Polarity
+            CC4NP: u1,
+            padding: u16,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  Low counter value
+            CNT_L: u16,
+            ///  High counter value
+            CNT_H: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Low Auto-reload value
+            ARR_L: u16,
+            ///  High Auto-reload value
+            ARR_H: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 1 value
+            CCR1_L: u16,
+            ///  High Capture/Compare 1 value
+            CCR1_H: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 2 value
+            CCR2_L: u16,
+            ///  High Capture/Compare 2 value
+            CCR2_H: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR3_L: u16,
+            ///  High Capture/Compare value
+            CCR3_H: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR4_L: u16,
+            ///  High Capture/Compare value
+            CCR4_H: u16,
+        }),
+        reserved72: [4]u8,
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+        ///  TIM5 option register
+        OR: mmio.Mmio(packed struct(u32) {
+            reserved10: u10,
+            ///  Timer Input 4 remap
+            ITR1_RMP: u2,
+            padding: u20,
+        }),
+    };
+
+    ///  General purpose timers
+    pub const TIM3 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            padding: u24,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            padding: u16,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            reserved6: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            reserved8: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            reserved14: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            reserved6: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            reserved9: u2,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            padding: u19,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            reserved6: u1,
+            ///  Trigger generation
+            TG: u1,
+            padding: u25,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC1S
+            CC1S: u2,
+            ///  OC1FE
+            OC1FE: u1,
+            ///  OC1PE
+            OC1PE: u1,
+            ///  OC1M
+            OC1M: u3,
+            ///  OC1CE
+            OC1CE: u1,
+            ///  CC2S
+            CC2S: u2,
+            ///  OC2FE
+            OC2FE: u1,
+            ///  OC2PE
+            OC2PE: u1,
+            ///  OC2M
+            OC2M: u3,
+            ///  OC2CE
+            OC2CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare mode register 2 (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC3S
+            CC3S: u2,
+            ///  OC3FE
+            OC3FE: u1,
+            ///  OC3PE
+            OC3PE: u1,
+            ///  OC3M
+            OC3M: u3,
+            ///  OC3CE
+            OC3CE: u1,
+            ///  CC4S
+            CC4S: u2,
+            ///  OC4FE
+            OC4FE: u1,
+            ///  OC4PE
+            OC4PE: u1,
+            ///  OC4M
+            OC4M: u3,
+            ///  O24CE
+            O24CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved7: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            reserved11: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            reserved15: u1,
+            ///  Capture/Compare 4 output Polarity
+            CC4NP: u1,
+            padding: u16,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  Low counter value
+            CNT_L: u16,
+            ///  High counter value
+            CNT_H: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Low Auto-reload value
+            ARR_L: u16,
+            ///  High Auto-reload value
+            ARR_H: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 1 value
+            CCR1_L: u16,
+            ///  High Capture/Compare 1 value
+            CCR1_H: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 2 value
+            CCR2_L: u16,
+            ///  High Capture/Compare 2 value
+            CCR2_H: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR3_L: u16,
+            ///  High Capture/Compare value
+            CCR3_H: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR4_L: u16,
+            ///  High Capture/Compare value
+            CCR4_H: u16,
+        }),
+        reserved72: [4]u8,
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  USB on the go full speed
+    pub const OTG_FS_GLOBAL = extern struct {
+        ///  OTG_FS control and status register (OTG_FS_GOTGCTL)
+        FS_GOTGCTL: mmio.Mmio(packed struct(u32) {
+            ///  Session request success
+            SRQSCS: u1,
+            ///  Session request
+            SRQ: u1,
+            reserved8: u6,
+            ///  Host negotiation success
+            HNGSCS: u1,
+            ///  HNP request
+            HNPRQ: u1,
+            ///  Host set HNP enable
+            HSHNPEN: u1,
+            ///  Device HNP enabled
+            DHNPEN: u1,
+            reserved16: u4,
+            ///  Connector ID status
+            CIDSTS: u1,
+            ///  Long/short debounce time
+            DBCT: u1,
+            ///  A-session valid
+            ASVLD: u1,
+            ///  B-session valid
+            BSVLD: u1,
+            padding: u12,
+        }),
+        ///  OTG_FS interrupt register (OTG_FS_GOTGINT)
+        FS_GOTGINT: mmio.Mmio(packed struct(u32) {
+            reserved2: u2,
+            ///  Session end detected
+            SEDET: u1,
+            reserved8: u5,
+            ///  Session request success status change
+            SRSSCHG: u1,
+            ///  Host negotiation success status change
+            HNSSCHG: u1,
+            reserved17: u7,
+            ///  Host negotiation detected
+            HNGDET: u1,
+            ///  A-device timeout change
+            ADTOCHG: u1,
+            ///  Debounce done
+            DBCDNE: u1,
+            padding: u12,
+        }),
+        ///  OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
+        FS_GAHBCFG: mmio.Mmio(packed struct(u32) {
+            ///  Global interrupt mask
+            GINT: u1,
+            reserved7: u6,
+            ///  TxFIFO empty level
+            TXFELVL: u1,
+            ///  Periodic TxFIFO empty level
+            PTXFELVL: u1,
+            padding: u23,
+        }),
+        ///  OTG_FS USB configuration register (OTG_FS_GUSBCFG)
+        FS_GUSBCFG: mmio.Mmio(packed struct(u32) {
+            ///  FS timeout calibration
+            TOCAL: u3,
+            reserved6: u3,
+            ///  Full Speed serial transceiver select
+            PHYSEL: u1,
+            reserved8: u1,
+            ///  SRP-capable
+            SRPCAP: u1,
+            ///  HNP-capable
+            HNPCAP: u1,
+            ///  USB turnaround time
+            TRDT: u4,
+            reserved29: u15,
+            ///  Force host mode
+            FHMOD: u1,
+            ///  Force device mode
+            FDMOD: u1,
+            ///  Corrupt Tx packet
+            CTXPKT: u1,
+        }),
+        ///  OTG_FS reset register (OTG_FS_GRSTCTL)
+        FS_GRSTCTL: mmio.Mmio(packed struct(u32) {
+            ///  Core soft reset
+            CSRST: u1,
+            ///  HCLK soft reset
+            HSRST: u1,
+            ///  Host frame counter reset
+            FCRST: u1,
+            reserved4: u1,
+            ///  RxFIFO flush
+            RXFFLSH: u1,
+            ///  TxFIFO flush
+            TXFFLSH: u1,
+            ///  TxFIFO number
+            TXFNUM: u5,
+            reserved31: u20,
+            ///  AHB master idle
+            AHBIDL: u1,
+        }),
+        ///  OTG_FS core interrupt register (OTG_FS_GINTSTS)
+        FS_GINTSTS: mmio.Mmio(packed struct(u32) {
+            ///  Current mode of operation
+            CMOD: u1,
+            ///  Mode mismatch interrupt
+            MMIS: u1,
+            ///  OTG interrupt
+            OTGINT: u1,
+            ///  Start of frame
+            SOF: u1,
+            ///  RxFIFO non-empty
+            RXFLVL: u1,
+            ///  Non-periodic TxFIFO empty
+            NPTXFE: u1,
+            ///  Global IN non-periodic NAK effective
+            GINAKEFF: u1,
+            ///  Global OUT NAK effective
+            GOUTNAKEFF: u1,
+            reserved10: u2,
+            ///  Early suspend
+            ESUSP: u1,
+            ///  USB suspend
+            USBSUSP: u1,
+            ///  USB reset
+            USBRST: u1,
+            ///  Enumeration done
+            ENUMDNE: u1,
+            ///  Isochronous OUT packet dropped interrupt
+            ISOODRP: u1,
+            ///  End of periodic frame interrupt
+            EOPF: u1,
+            reserved18: u2,
+            ///  IN endpoint interrupt
+            IEPINT: u1,
+            ///  OUT endpoint interrupt
+            OEPINT: u1,
+            ///  Incomplete isochronous IN transfer
+            IISOIXFR: u1,
+            ///  Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)
+            IPXFR_INCOMPISOOUT: u1,
+            reserved24: u2,
+            ///  Host port interrupt
+            HPRTINT: u1,
+            ///  Host channels interrupt
+            HCINT: u1,
+            ///  Periodic TxFIFO empty
+            PTXFE: u1,
+            reserved28: u1,
+            ///  Connector ID status change
+            CIDSCHG: u1,
+            ///  Disconnect detected interrupt
+            DISCINT: u1,
+            ///  Session request/new session detected interrupt
+            SRQINT: u1,
+            ///  Resume/remote wakeup detected interrupt
+            WKUPINT: u1,
+        }),
+        ///  OTG_FS interrupt mask register (OTG_FS_GINTMSK)
+        FS_GINTMSK: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Mode mismatch interrupt mask
+            MMISM: u1,
+            ///  OTG interrupt mask
+            OTGINT: u1,
+            ///  Start of frame mask
+            SOFM: u1,
+            ///  Receive FIFO non-empty mask
+            RXFLVLM: u1,
+            ///  Non-periodic TxFIFO empty mask
+            NPTXFEM: u1,
+            ///  Global non-periodic IN NAK effective mask
+            GINAKEFFM: u1,
+            ///  Global OUT NAK effective mask
+            GONAKEFFM: u1,
+            reserved10: u2,
+            ///  Early suspend mask
+            ESUSPM: u1,
+            ///  USB suspend mask
+            USBSUSPM: u1,
+            ///  USB reset mask
+            USBRST: u1,
+            ///  Enumeration done mask
+            ENUMDNEM: u1,
+            ///  Isochronous OUT packet dropped interrupt mask
+            ISOODRPM: u1,
+            ///  End of periodic frame interrupt mask
+            EOPFM: u1,
+            reserved17: u1,
+            ///  Endpoint mismatch interrupt mask
+            EPMISM: u1,
+            ///  IN endpoints interrupt mask
+            IEPINT: u1,
+            ///  OUT endpoints interrupt mask
+            OEPINT: u1,
+            ///  Incomplete isochronous IN transfer mask
+            IISOIXFRM: u1,
+            ///  Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)
+            IPXFRM_IISOOXFRM: u1,
+            reserved24: u2,
+            ///  Host port interrupt mask
+            PRTIM: u1,
+            ///  Host channels interrupt mask
+            HCIM: u1,
+            ///  Periodic TxFIFO empty mask
+            PTXFEM: u1,
+            reserved28: u1,
+            ///  Connector ID status change mask
+            CIDSCHGM: u1,
+            ///  Disconnect detected interrupt mask
+            DISCINT: u1,
+            ///  Session request/new session detected interrupt mask
+            SRQIM: u1,
+            ///  Resume/remote wakeup detected interrupt mask
+            WUIM: u1,
+        }),
+        ///  OTG_FS Receive status debug read(Device mode)
+        FS_GRXSTSR_Device: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint number
+            EPNUM: u4,
+            ///  Byte count
+            BCNT: u11,
+            ///  Data PID
+            DPID: u2,
+            ///  Packet status
+            PKTSTS: u4,
+            ///  Frame number
+            FRMNUM: u4,
+            padding: u7,
+        }),
+        reserved36: [4]u8,
+        ///  OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
+        FS_GRXFSIZ: mmio.Mmio(packed struct(u32) {
+            ///  RxFIFO depth
+            RXFD: u16,
+            padding: u16,
+        }),
+        ///  OTG_FS non-periodic transmit FIFO size register (Device mode)
+        FS_GNPTXFSIZ_Device: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint 0 transmit RAM start address
+            TX0FSA: u16,
+            ///  Endpoint 0 TxFIFO depth
+            TX0FD: u16,
+        }),
+        ///  OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)
+        FS_GNPTXSTS: mmio.Mmio(packed struct(u32) {
+            ///  Non-periodic TxFIFO space available
+            NPTXFSAV: u16,
+            ///  Non-periodic transmit request queue space available
+            NPTQXSAV: u8,
+            ///  Top of the non-periodic transmit request queue
+            NPTXQTOP: u7,
+            padding: u1,
+        }),
+        reserved56: [8]u8,
+        ///  OTG_FS general core configuration register (OTG_FS_GCCFG)
+        FS_GCCFG: mmio.Mmio(packed struct(u32) {
+            reserved16: u16,
+            ///  Power down
+            PWRDWN: u1,
+            reserved18: u1,
+            ///  Enable the VBUS sensing device
+            VBUSASEN: u1,
+            ///  Enable the VBUS sensing device
+            VBUSBSEN: u1,
+            ///  SOF output enable
+            SOFOUTEN: u1,
+            padding: u11,
+        }),
+        ///  core ID register
+        FS_CID: mmio.Mmio(packed struct(u32) {
+            ///  Product ID field
+            PRODUCT_ID: u32,
+        }),
+        reserved256: [192]u8,
+        ///  OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
+        FS_HPTXFSIZ: mmio.Mmio(packed struct(u32) {
+            ///  Host periodic TxFIFO start address
+            PTXSA: u16,
+            ///  Host periodic TxFIFO depth
+            PTXFSIZ: u16,
+        }),
+        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)
+        FS_DIEPTXF1: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFO2 transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)
+        FS_DIEPTXF2: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFO3 transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)
+        FS_DIEPTXF3: mmio.Mmio(packed struct(u32) {
+            ///  IN endpoint FIFO4 transmit RAM start address
+            INEPTXSA: u16,
+            ///  IN endpoint TxFIFO depth
+            INEPTXFD: u16,
+        }),
+    };
+
+    ///  General-purpose-timers
+    pub const TIM5 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            ///  Direction
+            DIR: u1,
+            ///  Center-aligned mode selection
+            CMS: u2,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved3: u3,
+            ///  Capture/compare DMA selection
+            CCDS: u1,
+            ///  Master mode selection
+            MMS: u3,
+            ///  TI1 selection
+            TI1S: u1,
+            padding: u24,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            ///  External trigger filter
+            ETF: u4,
+            ///  External trigger prescaler
+            ETPS: u2,
+            ///  External clock enable
+            ECE: u1,
+            ///  External trigger polarity
+            ETP: u1,
+            padding: u16,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            ///  Capture/Compare 3 interrupt enable
+            CC3IE: u1,
+            ///  Capture/Compare 4 interrupt enable
+            CC4IE: u1,
+            reserved6: u1,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            reserved8: u1,
+            ///  Update DMA request enable
+            UDE: u1,
+            ///  Capture/Compare 1 DMA request enable
+            CC1DE: u1,
+            ///  Capture/Compare 2 DMA request enable
+            CC2DE: u1,
+            ///  Capture/Compare 3 DMA request enable
+            CC3DE: u1,
+            ///  Capture/Compare 4 DMA request enable
+            CC4DE: u1,
+            reserved14: u1,
+            ///  Trigger DMA request enable
+            TDE: u1,
+            padding: u17,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            ///  Capture/Compare 3 interrupt flag
+            CC3IF: u1,
+            ///  Capture/Compare 4 interrupt flag
+            CC4IF: u1,
+            reserved6: u1,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            reserved9: u2,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            ///  Capture/Compare 3 overcapture flag
+            CC3OF: u1,
+            ///  Capture/Compare 4 overcapture flag
+            CC4OF: u1,
+            padding: u19,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            ///  Capture/compare 3 generation
+            CC3G: u1,
+            ///  Capture/compare 4 generation
+            CC4G: u1,
+            reserved6: u1,
+            ///  Trigger generation
+            TG: u1,
+            padding: u25,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC1S
+            CC1S: u2,
+            ///  OC1FE
+            OC1FE: u1,
+            ///  OC1PE
+            OC1PE: u1,
+            ///  OC1M
+            OC1M: u3,
+            ///  OC1CE
+            OC1CE: u1,
+            ///  CC2S
+            CC2S: u2,
+            ///  OC2FE
+            OC2FE: u1,
+            ///  OC2PE
+            OC2PE: u1,
+            ///  OC2M
+            OC2M: u3,
+            ///  OC2CE
+            OC2CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare mode register 2 (output mode)
+        CCMR2_Output: mmio.Mmio(packed struct(u32) {
+            ///  CC3S
+            CC3S: u2,
+            ///  OC3FE
+            OC3FE: u1,
+            ///  OC3PE
+            OC3PE: u1,
+            ///  OC3M
+            OC3M: u3,
+            ///  OC3CE
+            OC3CE: u1,
+            ///  CC4S
+            CC4S: u2,
+            ///  OC4FE
+            OC4FE: u1,
+            ///  OC4PE
+            OC4PE: u1,
+            ///  OC4M
+            OC4M: u3,
+            ///  O24CE
+            O24CE: u1,
+            padding: u16,
+        }),
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved7: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            ///  Capture/Compare 3 output enable
+            CC3E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3P: u1,
+            reserved11: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC3NP: u1,
+            ///  Capture/Compare 4 output enable
+            CC4E: u1,
+            ///  Capture/Compare 3 output Polarity
+            CC4P: u1,
+            reserved15: u1,
+            ///  Capture/Compare 4 output Polarity
+            CC4NP: u1,
+            padding: u16,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  Low counter value
+            CNT_L: u16,
+            ///  High counter value
+            CNT_H: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Low Auto-reload value
+            ARR_L: u16,
+            ///  High Auto-reload value
+            ARR_H: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 1 value
+            CCR1_L: u16,
+            ///  High Capture/Compare 1 value
+            CCR1_H: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare 2 value
+            CCR2_L: u16,
+            ///  High Capture/Compare 2 value
+            CCR2_H: u16,
+        }),
+        ///  capture/compare register 3
+        CCR3: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR3_L: u16,
+            ///  High Capture/Compare value
+            CCR3_H: u16,
+        }),
+        ///  capture/compare register 4
+        CCR4: mmio.Mmio(packed struct(u32) {
+            ///  Low Capture/Compare value
+            CCR4_L: u16,
+            ///  High Capture/Compare value
+            CCR4_H: u16,
+        }),
+        reserved72: [4]u8,
+        ///  DMA control register
+        DCR: mmio.Mmio(packed struct(u32) {
+            ///  DMA base address
+            DBA: u5,
+            reserved8: u3,
+            ///  DMA burst length
+            DBL: u5,
+            padding: u19,
+        }),
+        ///  DMA address for full transfer
+        DMAR: mmio.Mmio(packed struct(u32) {
+            ///  DMA register for burst accesses
+            DMAB: u16,
+            padding: u16,
+        }),
+        ///  TIM5 option register
+        OR: mmio.Mmio(packed struct(u32) {
+            reserved6: u6,
+            ///  Timer Input 4 remap
+            IT4_RMP: u2,
+            padding: u24,
+        }),
+    };
+
+    ///  General purpose timers
+    pub const TIM9 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            ///  One-pulse mode
+            OPM: u1,
+            reserved7: u3,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        ///  control register 2
+        CR2: mmio.Mmio(packed struct(u32) {
+            reserved4: u4,
+            ///  Master mode selection
+            MMS: u3,
+            padding: u25,
+        }),
+        ///  slave mode control register
+        SMCR: mmio.Mmio(packed struct(u32) {
+            ///  Slave mode selection
+            SMS: u3,
+            reserved4: u1,
+            ///  Trigger selection
+            TS: u3,
+            ///  Master/Slave mode
+            MSM: u1,
+            padding: u24,
+        }),
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            ///  Capture/Compare 2 interrupt enable
+            CC2IE: u1,
+            reserved6: u3,
+            ///  Trigger interrupt enable
+            TIE: u1,
+            padding: u25,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            ///  Capture/Compare 2 interrupt flag
+            CC2IF: u1,
+            reserved6: u3,
+            ///  Trigger interrupt flag
+            TIF: u1,
+            reserved9: u2,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            ///  Capture/compare 2 overcapture flag
+            CC2OF: u1,
+            padding: u21,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            ///  Capture/compare 2 generation
+            CC2G: u1,
+            reserved6: u3,
+            ///  Trigger generation
+            TG: u1,
+            padding: u25,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            reserved8: u1,
+            ///  Capture/Compare 2 selection
+            CC2S: u2,
+            ///  Output Compare 2 fast enable
+            OC2FE: u1,
+            ///  Output Compare 2 preload enable
+            OC2PE: u1,
+            ///  Output Compare 2 mode
+            OC2M: u3,
+            padding: u17,
+        }),
+        reserved32: [4]u8,
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            ///  Capture/Compare 2 output enable
+            CC2E: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2P: u1,
+            reserved7: u1,
+            ///  Capture/Compare 2 output Polarity
+            CC2NP: u1,
+            padding: u24,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        ///  capture/compare register 2
+        CCR2: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 2 value
+            CCR2: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Cryptographic processor
+    pub const CRC = extern struct {
+        ///  Data register
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Data Register
+            DR: u32,
+        }),
+        ///  Independent Data register
+        IDR: mmio.Mmio(packed struct(u32) {
+            ///  Independent Data register
+            IDR: u8,
+            padding: u24,
+        }),
+        ///  Control register
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Control regidter
+            CR: u1,
+            padding: u31,
+        }),
+    };
+
+    ///  General-purpose-timers
+    pub const TIM10 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            reserved7: u4,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        reserved12: [8]u8,
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            padding: u30,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            reserved9: u7,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            padding: u22,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            padding: u30,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            padding: u25,
+        }),
+        reserved32: [4]u8,
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            padding: u28,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+    };
+
+    ///  Ethernet: DMA controller operation
+    pub const Ethernet_DMA = extern struct {
+        ///  Ethernet DMA bus mode register
+        DMABMR: mmio.Mmio(packed struct(u32) {
+            ///  SR
+            SR: u1,
+            ///  DA
+            DA: u1,
+            ///  DSL
+            DSL: u5,
+            ///  EDFE
+            EDFE: u1,
+            ///  PBL
+            PBL: u6,
+            ///  RTPR
+            RTPR: u2,
+            ///  FB
+            FB: u1,
+            ///  RDP
+            RDP: u6,
+            ///  USP
+            USP: u1,
+            ///  FPM
+            FPM: u1,
+            ///  AAB
+            AAB: u1,
+            ///  MB
+            MB: u1,
+            padding: u5,
+        }),
+        ///  Ethernet DMA transmit poll demand register
+        DMATPDR: mmio.Mmio(packed struct(u32) {
+            ///  TPD
+            TPD: u32,
+        }),
+        ///  EHERNET DMA receive poll demand register
+        DMARPDR: mmio.Mmio(packed struct(u32) {
+            ///  RPD
+            RPD: u32,
+        }),
+        ///  Ethernet DMA receive descriptor list address register
+        DMARDLAR: mmio.Mmio(packed struct(u32) {
+            ///  SRL
+            SRL: u32,
+        }),
+        ///  Ethernet DMA transmit descriptor list address register
+        DMATDLAR: mmio.Mmio(packed struct(u32) {
+            ///  STL
+            STL: u32,
+        }),
+        ///  Ethernet DMA status register
+        DMASR: mmio.Mmio(packed struct(u32) {
+            ///  TS
+            TS: u1,
+            ///  TPSS
+            TPSS: u1,
+            ///  TBUS
+            TBUS: u1,
+            ///  TJTS
+            TJTS: u1,
+            ///  ROS
+            ROS: u1,
+            ///  TUS
+            TUS: u1,
+            ///  RS
+            RS: u1,
+            ///  RBUS
+            RBUS: u1,
+            ///  RPSS
+            RPSS: u1,
+            ///  PWTS
+            PWTS: u1,
+            ///  ETS
+            ETS: u1,
+            reserved13: u2,
+            ///  FBES
+            FBES: u1,
+            ///  ERS
+            ERS: u1,
+            ///  AIS
+            AIS: u1,
+            ///  NIS
+            NIS: u1,
+            ///  RPS
+            RPS: u3,
+            ///  TPS
+            TPS: u3,
+            ///  EBS
+            EBS: u3,
+            reserved27: u1,
+            ///  MMCS
+            MMCS: u1,
+            ///  PMTS
+            PMTS: u1,
+            ///  TSTS
+            TSTS: u1,
+            padding: u2,
+        }),
+        ///  Ethernet DMA operation mode register
+        DMAOMR: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  SR
+            SR: u1,
+            ///  OSF
+            OSF: u1,
+            ///  RTC
+            RTC: u2,
+            reserved6: u1,
+            ///  FUGF
+            FUGF: u1,
+            ///  FEF
+            FEF: u1,
+            reserved13: u5,
+            ///  ST
+            ST: u1,
+            ///  TTC
+            TTC: u3,
+            reserved20: u3,
+            ///  FTF
+            FTF: u1,
+            ///  TSF
+            TSF: u1,
+            reserved24: u2,
+            ///  DFRF
+            DFRF: u1,
+            ///  RSF
+            RSF: u1,
+            ///  DTCEFD
+            DTCEFD: u1,
+            padding: u5,
+        }),
+        ///  Ethernet DMA interrupt enable register
+        DMAIER: mmio.Mmio(packed struct(u32) {
+            ///  TIE
+            TIE: u1,
+            ///  TPSIE
+            TPSIE: u1,
+            ///  TBUIE
+            TBUIE: u1,
+            ///  TJTIE
+            TJTIE: u1,
+            ///  ROIE
+            ROIE: u1,
+            ///  TUIE
+            TUIE: u1,
+            ///  RIE
+            RIE: u1,
+            ///  RBUIE
+            RBUIE: u1,
+            ///  RPSIE
+            RPSIE: u1,
+            ///  RWTIE
+            RWTIE: u1,
+            ///  ETIE
+            ETIE: u1,
+            reserved13: u2,
+            ///  FBEIE
+            FBEIE: u1,
+            ///  ERIE
+            ERIE: u1,
+            ///  AISE
+            AISE: u1,
+            ///  NISE
+            NISE: u1,
+            padding: u15,
+        }),
+        ///  Ethernet DMA missed frame and buffer overflow counter register
+        DMAMFBOCR: mmio.Mmio(packed struct(u32) {
+            ///  MFC
+            MFC: u16,
+            ///  OMFC
+            OMFC: u1,
+            ///  MFA
+            MFA: u11,
+            ///  OFOC
+            OFOC: u1,
+            padding: u3,
+        }),
+        ///  Ethernet DMA receive status watchdog timer register
+        DMARSWTR: mmio.Mmio(packed struct(u32) {
+            ///  RSWTC
+            RSWTC: u8,
+            padding: u24,
+        }),
+        reserved72: [32]u8,
+        ///  Ethernet DMA current host transmit descriptor register
+        DMACHTDR: mmio.Mmio(packed struct(u32) {
+            ///  HTDAP
+            HTDAP: u32,
+        }),
+        ///  Ethernet DMA current host receive descriptor register
+        DMACHRDR: mmio.Mmio(packed struct(u32) {
+            ///  HRDAP
+            HRDAP: u32,
+        }),
+        ///  Ethernet DMA current host transmit buffer address register
+        DMACHTBAR: mmio.Mmio(packed struct(u32) {
+            ///  HTBAP
+            HTBAP: u32,
+        }),
+        ///  Ethernet DMA current host receive buffer address register
+        DMACHRBAR: mmio.Mmio(packed struct(u32) {
+            ///  HRBAP
+            HRBAP: u32,
+        }),
+    };
+
+    ///  Ethernet: Precision time protocol
+    pub const Ethernet_PTP = extern struct {
+        ///  Ethernet PTP time stamp control register
+        PTPTSCR: mmio.Mmio(packed struct(u32) {
+            ///  TSE
+            TSE: u1,
+            ///  TSFCU
+            TSFCU: u1,
+            ///  TSSTI
+            TSSTI: u1,
+            ///  TSSTU
+            TSSTU: u1,
+            ///  TSITE
+            TSITE: u1,
+            ///  TTSARU
+            TTSARU: u1,
+            reserved8: u2,
+            ///  TSSARFE
+            TSSARFE: u1,
+            ///  TSSSR
+            TSSSR: u1,
+            ///  TSPTPPSV2E
+            TSPTPPSV2E: u1,
+            ///  TSSPTPOEFE
+            TSSPTPOEFE: u1,
+            ///  TSSIPV6FE
+            TSSIPV6FE: u1,
+            ///  TSSIPV4FE
+            TSSIPV4FE: u1,
+            ///  TSSEME
+            TSSEME: u1,
+            ///  TSSMRME
+            TSSMRME: u1,
+            ///  TSCNT
+            TSCNT: u2,
+            ///  TSPFFMAE
+            TSPFFMAE: u1,
+            padding: u13,
+        }),
+        ///  Ethernet PTP subsecond increment register
+        PTPSSIR: mmio.Mmio(packed struct(u32) {
+            ///  STSSI
+            STSSI: u8,
+            padding: u24,
+        }),
+        ///  Ethernet PTP time stamp high register
+        PTPTSHR: mmio.Mmio(packed struct(u32) {
+            ///  STS
+            STS: u32,
+        }),
+        ///  Ethernet PTP time stamp low register
+        PTPTSLR: mmio.Mmio(packed struct(u32) {
+            ///  STSS
+            STSS: u31,
+            ///  STPNS
+            STPNS: u1,
+        }),
+        ///  Ethernet PTP time stamp high update register
+        PTPTSHUR: mmio.Mmio(packed struct(u32) {
+            ///  TSUS
+            TSUS: u32,
+        }),
+        ///  Ethernet PTP time stamp low update register
+        PTPTSLUR: mmio.Mmio(packed struct(u32) {
+            ///  TSUSS
+            TSUSS: u31,
+            ///  TSUSS
+            TSUPNS: u1,
+        }),
+        ///  Ethernet PTP time stamp addend register
+        PTPTSAR: mmio.Mmio(packed struct(u32) {
+            ///  TSA
+            TSA: u32,
+        }),
+        ///  Ethernet PTP target time high register
+        PTPTTHR: mmio.Mmio(packed struct(u32) {
+            ///  0
+            TTSH: u32,
+        }),
+        ///  Ethernet PTP target time low register
+        PTPTTLR: mmio.Mmio(packed struct(u32) {
+            ///  TTSL
+            TTSL: u32,
+        }),
+        reserved40: [4]u8,
+        ///  Ethernet PTP time stamp status register
+        PTPTSSR: mmio.Mmio(packed struct(u32) {
+            ///  TSSO
+            TSSO: u1,
+            ///  TSTTR
+            TSTTR: u1,
+            padding: u30,
+        }),
+        ///  Ethernet PTP PPS control register
+        PTPPPSCR: mmio.Mmio(packed struct(u32) {
+            ///  TSSO
+            TSSO: u1,
+            ///  TSTTR
+            TSTTR: u1,
+            padding: u30,
+        }),
+    };
+
+    ///  General-purpose-timers
+    pub const TIM11 = extern struct {
+        ///  control register 1
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Counter enable
+            CEN: u1,
+            ///  Update disable
+            UDIS: u1,
+            ///  Update request source
+            URS: u1,
+            reserved7: u4,
+            ///  Auto-reload preload enable
+            ARPE: u1,
+            ///  Clock division
+            CKD: u2,
+            padding: u22,
+        }),
+        reserved12: [8]u8,
+        ///  DMA/Interrupt enable register
+        DIER: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt enable
+            UIE: u1,
+            ///  Capture/Compare 1 interrupt enable
+            CC1IE: u1,
+            padding: u30,
+        }),
+        ///  status register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Update interrupt flag
+            UIF: u1,
+            ///  Capture/compare 1 interrupt flag
+            CC1IF: u1,
+            reserved9: u7,
+            ///  Capture/Compare 1 overcapture flag
+            CC1OF: u1,
+            padding: u22,
+        }),
+        ///  event generation register
+        EGR: mmio.Mmio(packed struct(u32) {
+            ///  Update generation
+            UG: u1,
+            ///  Capture/compare 1 generation
+            CC1G: u1,
+            padding: u30,
+        }),
+        ///  capture/compare mode register 1 (output mode)
+        CCMR1_Output: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 selection
+            CC1S: u2,
+            ///  Output Compare 1 fast enable
+            OC1FE: u1,
+            ///  Output Compare 1 preload enable
+            OC1PE: u1,
+            ///  Output Compare 1 mode
+            OC1M: u3,
+            padding: u25,
+        }),
+        reserved32: [4]u8,
+        ///  capture/compare enable register
+        CCER: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 output enable
+            CC1E: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1P: u1,
+            reserved3: u1,
+            ///  Capture/Compare 1 output Polarity
+            CC1NP: u1,
+            padding: u28,
+        }),
+        ///  counter
+        CNT: mmio.Mmio(packed struct(u32) {
+            ///  counter value
+            CNT: u16,
+            padding: u16,
+        }),
+        ///  prescaler
+        PSC: mmio.Mmio(packed struct(u32) {
+            ///  Prescaler value
+            PSC: u16,
+            padding: u16,
+        }),
+        ///  auto-reload register
+        ARR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-reload value
+            ARR: u16,
+            padding: u16,
+        }),
+        reserved52: [4]u8,
+        ///  capture/compare register 1
+        CCR1: mmio.Mmio(packed struct(u32) {
+            ///  Capture/Compare 1 value
+            CCR1: u16,
+            padding: u16,
+        }),
+        reserved80: [24]u8,
+        ///  option register
+        OR: mmio.Mmio(packed struct(u32) {
+            ///  Input 1 remapping capability
+            RMP: u2,
+            padding: u30,
+        }),
+    };
+};
diff --git a/src/hals/stm32f103.zig b/src/hals/stm32f103.zig
new file mode 100644
index 000000000..e69de29bb
diff --git a/src/hals/stm32f303.zig b/src/hals/stm32f303.zig
new file mode 100644
index 000000000..272e8b1d7
--- /dev/null
+++ b/src/hals/stm32f303.zig
@@ -0,0 +1,602 @@
+//! For now we keep all clock settings on the chip defaults.
+//! This code currently assumes the STM32F303xB / STM32F303xC clock configuration.
+//! TODO: Do something useful for other STM32f30x chips.
+//!
+//! Specifically, TIM6 is running on an 8 MHz clock,
+//! HSI = 8 MHz is the SYSCLK after reset
+//! default AHB prescaler = /1 (= values 0..7):
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .HPRE = 0 });
+//! ```
+//!
+//! so also HCLK = 8 MHz.
+//! And with the default APB1 prescaler = /2:
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .PPRE1 = 4 });
+//! ```
+//!
+//! results in PCLK1,
+//! and the resulting implicit factor *2 for TIM2/3/4/6/7
+//! makes TIM6 run at 8MHz/2*2 = 8 MHz.
+//!
+//! The above default configuration makes U(S)ART2..5
+//! (which use PCLK1 without that implicit *2 factor)
+//! run at 4 MHz by default.
+//!
+//! USART1 uses PCLK2, which uses the APB2 prescaler on HCLK,
+//! default APB2 prescaler = /1:
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .PPRE2 = 0 });
+//! ```
+//!
+//! and therefore USART1 runs on 8 MHz.
+
+const std = @import("std");
+const runtime_safety = std.debug.runtime_safety;
+
+const micro = @import("microzig");
+const SPI1 = micro.peripherals.SPI1;
+const RCC = micro.peripherals.RCC;
+const USART1 = micro.peripherals.USART1;
+const GPIOA = micro.peripherals.GPIOA;
+const GPIOB = micro.peripherals.GPIOB;
+const GPIOC = micro.peripherals.GPIOC;
+const I2C1 = micro.peripherals.I2C1;
+
+pub const cpu = @import("cpu");
+
+pub const clock = struct {
+    pub const Domain = enum {
+        cpu,
+        ahb,
+        apb1,
+        apb2,
+    };
+};
+
+// Default clock frequencies after reset, see top comment for calculation
+pub const clock_frequencies = .{
+    .cpu = 8_000_000,
+    .ahb = 8_000_000,
+    .apb1 = 8_000_000,
+    .apb2 = 8_000_000,
+};
+
+pub fn parse_pin(comptime spec: []const u8) type {
+    const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme.";
+
+    if (spec[0] != 'P')
+        @compileError(invalid_format_msg);
+    if (spec[1] < 'A' or spec[1] > 'H')
+        @compileError(invalid_format_msg);
+
+    const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg);
+
+    return struct {
+        /// 'A'...'H'
+        const gpio_port_name = spec[1..2];
+        const gpio_port = @field(micro.peripherals, "GPIO" ++ gpio_port_name);
+        const suffix = std.fmt.comptimePrint("{d}", .{pin_number});
+    };
+}
+
+fn set_reg_field(reg: anytype, comptime field_name: anytype, value: anytype) void {
+    var temp = reg.read();
+    @field(temp, field_name) = value;
+    reg.write(temp);
+}
+
+pub const gpio = struct {
+    pub fn set_output(comptime pin: type) void {
+        set_reg_field(RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1);
+        set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01);
+    }
+
+    pub fn set_input(comptime pin: type) void {
+        set_reg_field(RCC.AHBENR, "IOP" ++ pin.gpio_port_name ++ "EN", 1);
+        set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00);
+    }
+
+    pub fn read(comptime pin: type) micro.gpio.State {
+        const idr_reg = pin.gpio_port.IDR;
+        const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()?
+        return @intToEnum(micro.gpio.State, reg_value);
+    }
+
+    pub fn write(comptime pin: type, state: micro.gpio.State) void {
+        switch (state) {
+            .low => set_reg_field(pin.gpio_port.BRR, "BR" ++ pin.suffix, 1),
+            .high => set_reg_field(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1),
+        }
+    }
+};
+
+pub const uart = struct {
+    pub const DataBits = enum(u4) {
+        seven = 7,
+        eight = 8,
+    };
+
+    /// uses the values of USART_CR2.STOP
+    pub const StopBits = enum(u2) {
+        one = 0b00,
+        half = 0b01,
+        two = 0b10,
+        one_and_half = 0b11,
+    };
+
+    /// uses the values of USART_CR1.PS
+    pub const Parity = enum(u1) {
+        even = 0,
+        odd = 1,
+    };
+};
+
+pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
+    if (!(index == 1)) @compileError("TODO: only USART1 is currently supported");
+    if (pins.tx != null or pins.rx != null)
+        @compileError("TODO: custom pins are not currently supported");
+
+    return struct {
+        parity_read_mask: u8,
+
+        const Self = @This();
+
+        pub fn init(config: micro.uart.Config) !Self {
+            // The following must all be written when the USART is disabled (UE=0).
+            if (USART1.CR1.read().UE == 1)
+                @panic("Trying to initialize USART1 while it is already enabled");
+            // LATER: Alternatively, set UE=0 at this point?  Then wait for something?
+            // Or add a destroy() function which disables the USART?
+
+            // enable the USART1 clock
+            RCC.APB2ENR.modify(.{ .USART1EN = 1 });
+            // enable GPIOC clock
+            RCC.AHBENR.modify(.{ .IOPCEN = 1 });
+            // set PC4+PC5 to alternate function 7, USART1_TX + USART1_RX
+            GPIOC.MODER.modify(.{ .MODER4 = 0b10, .MODER5 = 0b10 });
+            GPIOC.AFRL.modify(.{ .AFRL4 = 7, .AFRL5 = 7 });
+
+            // clear USART1 configuration to its default
+            USART1.CR1.raw = 0;
+            USART1.CR2.raw = 0;
+            USART1.CR3.raw = 0;
+
+            // set word length
+            // Per the reference manual, M[1:0] means
+            // - 00: 8 bits (7 data + 1 parity, or 8 data), probably the chip default
+            // - 01: 9 bits (8 data + 1 parity)
+            // - 10: 7 bits (7 data)
+            // So M1==1 means "7-bit mode" (in which
+            // "the Smartcard mode, LIN master mode and Auto baud rate [...] are not supported");
+            // and M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'.
+            const m1: u1 = if (config.data_bits == .seven and config.parity == null) 1 else 0;
+            const m0: u1 = if (config.data_bits == .eight and config.parity != null) 1 else 0;
+            // Note that .padding0 = bit 28 = .M1 (.svd file bug?), and .M == .M0.
+            USART1.CR1.modify(.{ .padding0 = m1, .M = m0 });
+
+            // set parity
+            if (config.parity) |parity| {
+                USART1.CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) });
+            } else USART1.CR1.modify(.{ .PCE = 0 }); // no parity, probably the chip default
+
+            // set number of stop bits
+            USART1.CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) });
+
+            // set the baud rate
+            // TODO: Do not use the _board_'s frequency, but the _U(S)ARTx_ frequency
+            // from the chip, which can be affected by how the board configures the chip.
+            // In our case, these are accidentally the same at chip reset,
+            // if the board doesn't configure e.g. an HSE external crystal.
+            // TODO: Do some checks to see if the baud rate is too high (or perhaps too low)
+            // TODO: Do a rounding div, instead of a truncating div?
+            const usartdiv = @intCast(u16, @divTrunc(micro.clock.get().apb1, config.baud_rate));
+            USART1.BRR.raw = usartdiv;
+            // Above, ignore the BRR struct fields DIV_Mantissa and DIV_Fraction,
+            // those seem to be for another chipset; .svd file bug?
+            // TODO: We assume the default OVER8=0 configuration above.
+
+            // enable USART1, and its transmitter and receiver
+            USART1.CR1.modify(.{ .UE = 1 });
+            USART1.CR1.modify(.{ .TE = 1 });
+            USART1.CR1.modify(.{ .RE = 1 });
+
+            // For code simplicity, at cost of one or more register reads,
+            // we read back the actual configuration from the registers,
+            // instead of using the `config` values.
+            return read_from_registers();
+        }
+
+        pub fn get_or_init(config: micro.uart.Config) !Self {
+            if (USART1.CR1.read().UE == 1) {
+                // UART1 already enabled, don't reinitialize and disturb things;
+                // instead read and use the actual configuration.
+                return read_from_registers();
+            } else return init(config);
+        }
+
+        fn read_from_registers() Self {
+            const cr1 = USART1.CR1.read();
+            // As documented in `init()`, M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'.
+            // So we always mask away the 9th bit, and if parity is enabled and it is in the 8th bit,
+            // then we also mask away the 8th bit.
+            return Self{ .parity_read_mask = if (cr1.PCE == 1 and cr1.M == 0) 0x7F else 0xFF };
+        }
+
+        pub fn can_write(self: Self) bool {
+            _ = self;
+            return switch (USART1.ISR.read().TXE) {
+                1 => true,
+                0 => false,
+            };
+        }
+
+        pub fn tx(self: Self, ch: u8) void {
+            while (!self.can_write()) {} // Wait for Previous transmission
+            USART1.TDR.modify(ch);
+        }
+
+        pub fn txflush(_: Self) void {
+            while (USART1.ISR.read().TC == 0) {}
+        }
+
+        pub fn can_read(self: Self) bool {
+            _ = self;
+            return switch (USART1.ISR.read().RXNE) {
+                1 => true,
+                0 => false,
+            };
+        }
+
+        pub fn rx(self: Self) u8 {
+            while (!self.can_read()) {} // Wait till the data is received
+            const data_with_parity_bit: u9 = USART1.RDR.read().RDR;
+            return @intCast(u8, data_with_parity_bit & self.parity_read_mask);
+        }
+    };
+}
+
+const enable_stm32f303_debug = false;
+
+fn debug_print(comptime format: []const u8, args: anytype) void {
+    if (enable_stm32f303_debug) {
+        micro.debug.writer().print(format, args) catch {};
+    }
+}
+
+/// This implementation does not use AUTOEND=1
+pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type {
+    if (!(index == 1)) @compileError("TODO: only I2C1 is currently supported");
+    if (pins.scl != null or pins.sda != null)
+        @compileError("TODO: custom pins are not currently supported");
+
+    return struct {
+        const Self = @This();
+
+        pub fn init(config: micro.i2c.Config) !Self {
+            // CONFIGURE I2C1
+            // connected to APB1, MCU pins PB6 + PB7 = I2C1_SCL + I2C1_SDA,
+            // if GPIO port B is configured for alternate function 4 for these PB pins.
+
+            // 1. Enable the I2C CLOCK and GPIO CLOCK
+            RCC.APB1ENR.modify(.{ .I2C1EN = 1 });
+            RCC.AHBENR.modify(.{ .IOPBEN = 1 });
+            debug_print("I2C1 configuration step 1 complete\r\n", .{});
+            // 2. Configure the I2C PINs for ALternate Functions
+            // 	a) Select Alternate Function in MODER Register
+            GPIOB.MODER.modify(.{ .MODER6 = 0b10, .MODER7 = 0b10 });
+            // 	b) Select Open Drain Output
+            GPIOB.OTYPER.modify(.{ .OT6 = 1, .OT7 = 1 });
+            // 	c) Select High SPEED for the PINs
+            GPIOB.OSPEEDR.modify(.{ .OSPEEDR6 = 0b11, .OSPEEDR7 = 0b11 });
+            // 	d) Select Pull-up for both the Pins
+            GPIOB.PUPDR.modify(.{ .PUPDR6 = 0b01, .PUPDR7 = 0b01 });
+            // 	e) Configure the Alternate Function in AFR Register
+            GPIOB.AFRL.modify(.{ .AFRL6 = 4, .AFRL7 = 4 });
+            debug_print("I2C1 configuration step 2 complete\r\n", .{});
+
+            // 3. Reset the I2C
+            I2C1.CR1.modify(.{ .PE = 0 });
+            while (I2C1.CR1.read().PE == 1) {}
+            // DO NOT RCC.APB1RSTR.modify(.{ .I2C1RST = 1 });
+            debug_print("I2C1 configuration step 3 complete\r\n", .{});
+
+            // 4-6. Configure I2C1 timing, based on 8 MHz I2C clock, run at 100 kHz
+            // (Not using https://controllerstech.com/stm32-i2c-configuration-using-registers/
+            // but copying an example from the reference manual, RM0316 section 28.4.9.)
+            if (config.target_speed != 100_000) @panic("TODO: Support speeds other than 100 kHz");
+            I2C1.TIMINGR.modify(.{
+                .PRESC = 1,
+                .SCLL = 0x13,
+                .SCLH = 0xF,
+                .SDADEL = 0x2,
+                .SCLDEL = 0x4,
+            });
+            debug_print("I2C1 configuration steps 4-6 complete\r\n", .{});
+
+            // 7. Program the I2C_CR1 register to enable the peripheral
+            I2C1.CR1.modify(.{ .PE = 1 });
+            debug_print("I2C1 configuration step 7 complete\r\n", .{});
+
+            return Self{};
+        }
+
+        pub const WriteState = struct {
+            address: u7,
+            buffer: [255]u8 = undefined,
+            buffer_size: u8 = 0,
+
+            pub fn start(address: u7) !WriteState {
+                return WriteState{ .address = address };
+            }
+
+            pub fn write_all(self: *WriteState, bytes: []const u8) !void {
+                debug_print("I2C1 writeAll() with {d} byte(s); buffer={any}\r\n", .{ bytes.len, self.buffer[0..self.buffer_size] });
+
+                std.debug.assert(self.buffer_size < 255);
+                for (bytes) |b| {
+                    self.buffer[self.buffer_size] = b;
+                    self.buffer_size += 1;
+                    if (self.buffer_size == 255) {
+                        try self.send_buffer(1);
+                    }
+                }
+            }
+
+            fn send_buffer(self: *WriteState, reload: u1) !void {
+                debug_print("I2C1 sendBuffer() with {d} byte(s); RELOAD={d}; buffer={any}\r\n", .{ self.buffer_size, reload, self.buffer[0..self.buffer_size] });
+                if (self.buffer_size == 0) @panic("write of 0 bytes not supported");
+
+                std.debug.assert(reload == 0 or self.buffer_size == 255); // see TODOs below
+
+                // As master, initiate write from address, 7 bit address
+                I2C1.CR2.modify(.{
+                    .ADD10 = 0,
+                    .SADD1 = self.address,
+                    .RD_WRN = 0, // write
+                    .NBYTES = self.buffer_size,
+                    .RELOAD = reload,
+                });
+                if (reload == 0) {
+                    I2C1.CR2.modify(.{ .START = 1 });
+                } else {
+                    // TODO: The RELOAD=1 path is untested but doesn't seem to work yet,
+                    // even though we make sure that we set NBYTES=255 per the docs.
+                }
+                for (self.buffer[0..self.buffer_size]) |b| {
+                    // wait for empty transmit buffer
+                    while (I2C1.ISR.read().TXE == 0) {
+                        debug_print("I2C1 waiting for ready to send (TXE=0)\r\n", .{});
+                    }
+                    debug_print("I2C1 ready to send (TXE=1)\r\n", .{});
+                    // Write data byte
+                    I2C1.TXDR.modify(.{ .TXDATA = b });
+                }
+                self.buffer_size = 0;
+                debug_print("I2C1 data written\r\n", .{});
+                if (reload == 1) {
+                    // TODO: The RELOAD=1 path is untested but doesn't seem to work yet,
+                    // the following loop never seems to finish.
+                    while (I2C1.ISR.read().TCR == 0) {
+                        debug_print("I2C1 waiting transmit complete (TCR=0)\r\n", .{});
+                    }
+                    debug_print("I2C1 transmit complete (TCR=1)\r\n", .{});
+                } else {
+                    while (I2C1.ISR.read().TC == 0) {
+                        debug_print("I2C1 waiting for transmit complete (TC=0)\r\n", .{});
+                    }
+                    debug_print("I2C1 transmit complete (TC=1)\r\n", .{});
+                }
+            }
+
+            pub fn stop(self: *WriteState) !void {
+                try self.send_buffer(0);
+                // Communication STOP
+                debug_print("I2C1 STOPping\r\n", .{});
+                I2C1.CR2.modify(.{ .STOP = 1 });
+                while (I2C1.ISR.read().BUSY == 1) {}
+                debug_print("I2C1 STOPped\r\n", .{});
+            }
+
+            pub fn restart_read(self: *WriteState) !ReadState {
+                try self.send_buffer(0);
+                return ReadState{ .address = self.address };
+            }
+            pub fn restart_write(self: *WriteState) !WriteState {
+                try self.send_buffer(0);
+                return WriteState{ .address = self.address };
+            }
+        };
+
+        pub const ReadState = struct {
+            address: u7,
+            read_allowed: if (runtime_safety) bool else void = if (runtime_safety) true else {},
+
+            pub fn start(address: u7) !ReadState {
+                return ReadState{ .address = address };
+            }
+
+            /// Fails with ReadError if incorrect number of bytes is received.
+            pub fn read_no_eof(self: *ReadState, buffer: []u8) !void {
+                if (runtime_safety and !self.read_allowed) @panic("second read call not allowed");
+                std.debug.assert(buffer.len < 256); // TODO: use RELOAD to read more data
+
+                // As master, initiate read from accelerometer, 7 bit address
+                I2C1.CR2.modify(.{
+                    .ADD10 = 0,
+                    .SADD1 = self.address,
+                    .RD_WRN = 1, // read
+                    .NBYTES = @intCast(u8, buffer.len),
+                });
+                debug_print("I2C1 prepared for read of {} byte(s) from 0b{b:0<7}\r\n", .{ buffer.len, self.address });
+
+                // Communication START
+                I2C1.CR2.modify(.{ .START = 1 });
+                debug_print("I2C1 RXNE={}\r\n", .{I2C1.ISR.read().RXNE});
+                debug_print("I2C1 STARTed\r\n", .{});
+                debug_print("I2C1 RXNE={}\r\n", .{I2C1.ISR.read().RXNE});
+
+                if (runtime_safety) self.read_allowed = false;
+
+                for (buffer) |_, i| {
+                    // Wait for data to be received
+                    while (I2C1.ISR.read().RXNE == 0) {
+                        debug_print("I2C1 waiting for data (RXNE=0)\r\n", .{});
+                    }
+                    debug_print("I2C1 data ready (RXNE=1)\r\n", .{});
+
+                    // Read first data byte
+                    buffer[i] = I2C1.RXDR.read().RXDATA;
+                }
+                debug_print("I2C1 data: {any}\r\n", .{buffer});
+            }
+
+            pub fn stop(_: *ReadState) !void {
+                // Communication STOP
+                I2C1.CR2.modify(.{ .STOP = 1 });
+                while (I2C1.ISR.read().BUSY == 1) {}
+                debug_print("I2C1 STOPped\r\n", .{});
+            }
+
+            pub fn restart_read(self: *ReadState) !ReadState {
+                debug_print("I2C1 no action for restart\r\n", .{});
+                return ReadState{ .address = self.address };
+            }
+            pub fn restart_write(self: *ReadState) !WriteState {
+                debug_print("I2C1 no action for restart\r\n", .{});
+                return WriteState{ .address = self.address };
+            }
+        };
+    };
+}
+
+/// An STM32F303 SPI bus
+pub fn SpiBus(comptime index: usize) type {
+    if (!(index == 1)) @compileError("TODO: only SPI1 is currently supported");
+
+    return struct {
+        const Self = @This();
+
+        /// Initialize and enable the bus.
+        pub fn init(config: micro.spi.BusConfig) !Self {
+            _ = config; // unused for now
+
+            // CONFIGURE SPI1
+            // connected to APB2, MCU pins PA5 + PA7 + PA6 = SPC + SDI + SDO,
+            // if GPIO port A is configured for alternate function 5 for these PA pins.
+
+            // Enable the GPIO CLOCK
+            RCC.AHBENR.modify(.{ .IOPAEN = 1 });
+
+            // Configure the I2C PINs for ALternate Functions
+            // 	- Select Alternate Function in MODER Register
+            GPIOA.MODER.modify(.{ .MODER5 = 0b10, .MODER6 = 0b10, .MODER7 = 0b10 });
+            // 	- Select High SPEED for the PINs
+            GPIOA.OSPEEDR.modify(.{ .OSPEEDR5 = 0b11, .OSPEEDR6 = 0b11, .OSPEEDR7 = 0b11 });
+            // 	- Configure the Alternate Function in AFR Register
+            GPIOA.AFRL.modify(.{ .AFRL5 = 5, .AFRL6 = 5, .AFRL7 = 5 });
+
+            // Enable the SPI1 CLOCK
+            RCC.APB2ENR.modify(.{ .SPI1EN = 1 });
+
+            SPI1.CR1.modify(.{
+                .MSTR = 1,
+                .SSM = 1,
+                .SSI = 1,
+                .RXONLY = 0,
+                .SPE = 1,
+            });
+            // the following configuration is assumed in `transceiveByte()`
+            SPI1.CR2.raw = 0;
+            SPI1.CR2.modify(.{
+                .DS = 0b0111, // 8-bit data frames, seems default via '0b0000 is interpreted as 0b0111'
+                .FRXTH = 1, // RXNE event after 1 byte received
+            });
+
+            return Self{};
+        }
+
+        /// Switch this SPI bus to the given device.
+        pub fn switch_to_device(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void {
+            _ = config; // for future use
+
+            SPI1.CR1.modify(.{
+                .CPOL = 1, // TODO: make configurable
+                .CPHA = 1, // TODO: make configurable
+                .BR = 0b111, // 1/256 the of PCLK TODO: make configurable
+                .LSBFIRST = 0, // MSB first TODO: make configurable
+            });
+            gpio.set_output(cs_pin);
+        }
+
+        /// Begin a transfer to the given device.  (Assumes `switchToDevice()` was called.)
+        pub fn begin_transfer(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void {
+            _ = config; // for future use
+            gpio.write(cs_pin, .low); // select the given device, TODO: support inverse CS devices
+            debug_print("enabled SPI1\r\n", .{});
+        }
+
+        /// The basic operation in the current simplistic implementation:
+        /// send+receive a single byte.
+        /// Writing `null` writes an arbitrary byte (`undefined`), and
+        /// reading into `null` ignores the value received.
+        pub fn transceive_byte(_: Self, optional_write_byte: ?u8, optional_read_pointer: ?*u8) !void {
+
+            // SPIx_DR's least significant byte is `@bitCast([dr_byte_size]u8, ...)[0]`
+            const dr_byte_size = @sizeOf(@TypeOf(SPI1.DR.raw));
+
+            // wait unril ready for write
+            while (SPI1.SR.read().TXE == 0) {
+                debug_print("SPI1 TXE == 0\r\n", .{});
+            }
+            debug_print("SPI1 TXE == 1\r\n", .{});
+
+            // write
+            const write_byte = if (optional_write_byte) |b| b else undefined; // dummy value
+            @bitCast([dr_byte_size]u8, SPI1.DR.*)[0] = write_byte;
+            debug_print("Sent: {X:2}.\r\n", .{write_byte});
+
+            // wait until read processed
+            while (SPI1.SR.read().RXNE == 0) {
+                debug_print("SPI1 RXNE == 0\r\n", .{});
+            }
+            debug_print("SPI1 RXNE == 1\r\n", .{});
+
+            // read
+            var data_read = SPI1.DR.raw;
+            _ = SPI1.SR.read(); // clear overrun flag
+            const dr_lsb = @bitCast([dr_byte_size]u8, data_read)[0];
+            debug_print("Received: {X:2} (DR = {X:8}).\r\n", .{ dr_lsb, data_read });
+            if (optional_read_pointer) |read_pointer| read_pointer.* = dr_lsb;
+        }
+
+        /// Write all given bytes on the bus, not reading anything back.
+        pub fn write_all(self: Self, bytes: []const u8) !void {
+            for (bytes) |b| {
+                try self.transceive_byte(b, null);
+            }
+        }
+
+        /// Read bytes to fill the given buffer exactly, writing arbitrary bytes (`undefined`).
+        pub fn read_into(self: Self, buffer: []u8) !void {
+            for (buffer) |_, i| {
+                try self.transceive_byte(null, &buffer[i]);
+            }
+        }
+
+        pub fn end_transfer(_: Self, comptime cs_pin: type, config: micro.spi.DeviceConfig) void {
+            _ = config; // for future use
+            // no delay should be needed here, since we know SPIx_SR's TXE is 1
+            debug_print("(disabling SPI1)\r\n", .{});
+            gpio.write(cs_pin, .high); // deselect the given device, TODO: support inverse CS devices
+            // HACK: wait long enough to make any device end an ongoing transfer
+            var i: u8 = 255; // with the default clock, this seems to delay ~185 microseconds
+            while (i > 0) : (i -= 1) {
+                asm volatile ("nop");
+            }
+        }
+    };
+}
diff --git a/src/hals/stm32f407.zig b/src/hals/stm32f407.zig
new file mode 100644
index 000000000..6461bd899
--- /dev/null
+++ b/src/hals/stm32f407.zig
@@ -0,0 +1,623 @@
+//! For now we keep all clock settings on the chip defaults.
+//! This code currently assumes the STM32F405xx / STM32F407xx clock configuration.
+//! TODO: Do something useful for other STM32F40x chips.
+//!
+//! Specifically, TIM6 is running on a 16 MHz clock,
+//! HSI = 16 MHz is the SYSCLK after reset
+//! default AHB prescaler = /1 (= values 0..7):
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .HPRE = 0 });
+//! ```
+//!
+//! so also HCLK = 16 MHz.
+//! And with the default APB1 prescaler = /1:
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .PPRE1 = 0 });
+//! ```
+//!
+//! results in PCLK1 = 16 MHz.
+//!
+//! The above default configuration makes U(S)ART2..5
+//! receive a 16 MHz clock by default.
+//!
+//! USART1 and USART6 use PCLK2, which uses the APB2 prescaler on HCLK,
+//! default APB2 prescaler = /1:
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .PPRE2 = 0 });
+//! ```
+//!
+//! and therefore USART1 and USART6 receive a 16 MHz clock.
+//!
+
+const std = @import("std");
+const micro = @import("microzig");
+const peripherals = micro.peripherals;
+const RCC = peripherals.RCC;
+
+pub const clock = struct {
+    pub const Domain = enum {
+        cpu,
+        ahb,
+        apb1,
+        apb2,
+    };
+};
+
+// Default clock frequencies after reset, see top comment for calculation
+pub const clock_frequencies = .{
+    .cpu = 16_000_000,
+    .ahb = 16_000_000,
+    .apb1 = 16_000_000,
+    .apb2 = 16_000_000,
+};
+
+pub fn parse_pin(comptime spec: []const u8) type {
+    const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme.";
+
+    if (spec[0] != 'P')
+        @compileError(invalid_format_msg);
+    if (spec[1] < 'A' or spec[1] > 'I')
+        @compileError(invalid_format_msg);
+
+    return struct {
+        const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg);
+        /// 'A'...'I'
+        const gpio_port_name = spec[1..2];
+        const gpio_port = @field(peripherals, "GPIO" ++ gpio_port_name);
+        const suffix = std.fmt.comptimePrint("{d}", .{pin_number});
+    };
+}
+
+fn set_reg_field(reg: anytype, comptime field_name: anytype, value: anytype) void {
+    var temp = reg.read();
+    @field(temp, field_name) = value;
+    reg.write(temp);
+}
+
+pub const gpio = struct {
+    pub const AlternateFunction = enum(u4) {
+        af0,
+        af1,
+        af2,
+        af3,
+        af4,
+        af5,
+        af6,
+        af7,
+        af8,
+        af9,
+        af10,
+        af11,
+        af12,
+        af13,
+        af14,
+        af15,
+    };
+
+    pub fn set_output(comptime pin: type) void {
+        set_reg_field(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
+        set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01);
+    }
+
+    pub fn set_input(comptime pin: type) void {
+        set_reg_field(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
+        set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00);
+    }
+
+    pub fn set_alternate_function(comptime pin: type, af: AlternateFunction) void {
+        set_reg_field(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
+        set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b10);
+        if (pin.pin_number < 8) {
+            set_reg_field(@field(pin.gpio_port, "AFRL"), "AFRL" ++ pin.suffix, @enumToInt(af));
+        } else {
+            set_reg_field(@field(pin.gpio_port, "AFRH"), "AFRH" ++ pin.suffix, @enumToInt(af));
+        }
+    }
+
+    pub fn read(comptime pin: type) micro.gpio.State {
+        const idr_reg = pin.gpio_port.IDR;
+        const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()?
+        return @intToEnum(micro.gpio.State, reg_value);
+    }
+
+    pub fn write(comptime pin: type, state: micro.gpio.State) void {
+        switch (state) {
+            .low => set_reg_field(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1),
+            .high => set_reg_field(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1),
+        }
+    }
+};
+
+pub const uart = struct {
+    pub const DataBits = enum {
+        seven,
+        eight,
+        nine,
+    };
+
+    /// uses the values of USART_CR2.STOP
+    pub const StopBits = enum(u2) {
+        one = 0b00,
+        half = 0b01,
+        two = 0b10,
+        one_and_half = 0b11,
+    };
+
+    /// uses the values of USART_CR1.PS
+    pub const Parity = enum(u1) {
+        even = 0,
+        odd = 1,
+    };
+
+    const PinDirection = std.meta.FieldEnum(micro.uart.Pins);
+
+    /// Checks if a pin is valid for a given uart index and direction
+    pub fn is_valid_pin(comptime pin: type, comptime index: usize, comptime direction: PinDirection) bool {
+        const pin_name = pin.name;
+
+        return switch (direction) {
+            .tx => switch (index) {
+                1 => std.mem.eql(u8, pin_name, "PA9") or std.mem.eql(u8, pin_name, "PB6"),
+                2 => std.mem.eql(u8, pin_name, "PA2") or std.mem.eql(u8, pin_name, "PD5"),
+                3 => std.mem.eql(u8, pin_name, "PB10") or std.mem.eql(u8, pin_name, "PC10") or std.mem.eql(u8, pin_name, "PD8"),
+                4 => std.mem.eql(u8, pin_name, "PA0") or std.mem.eql(u8, pin_name, "PC10"),
+                5 => std.mem.eql(u8, pin_name, "PC12"),
+                6 => std.mem.eql(u8, pin_name, "PC6") or std.mem.eql(u8, pin_name, "PG14"),
+                else => unreachable,
+            },
+            // Valid RX pins for the UARTs
+            .rx => switch (index) {
+                1 => std.mem.eql(u8, pin_name, "PA10") or std.mem.eql(u8, pin_name, "PB7"),
+                2 => std.mem.eql(u8, pin_name, "PA3") or std.mem.eql(u8, pin_name, "PD6"),
+                3 => std.mem.eql(u8, pin_name, "PB11") or std.mem.eql(u8, pin_name, "PC11") or std.mem.eql(u8, pin_name, "PD9"),
+                4 => std.mem.eql(u8, pin_name, "PA1") or std.mem.eql(u8, pin_name, "PC11"),
+                5 => std.mem.eql(u8, pin_name, "PD2"),
+                6 => std.mem.eql(u8, pin_name, "PC7") or std.mem.eql(u8, pin_name, "PG9"),
+                else => unreachable,
+            },
+        };
+    }
+};
+
+pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
+    if (index < 1 or index > 6) @compileError("Valid USART index are 1..6");
+
+    const usart_name = std.fmt.comptimePrint("USART{d}", .{index});
+    const tx_pin =
+        if (pins.tx) |tx|
+        if (uart.is_valid_pin(tx, index, .tx))
+            tx
+        else
+            @compileError(std.fmt.comptimePrint("Tx pin {s} is not valid for UART{}", .{ tx.name, index }))
+    else switch (index) {
+        // Provide default tx pins if no pin is specified
+        1 => micro.Pin("PA9"),
+        2 => micro.Pin("PA2"),
+        3 => micro.Pin("PB10"),
+        4 => micro.Pin("PA0"),
+        5 => micro.Pin("PC12"),
+        6 => micro.Pin("PC6"),
+        else => unreachable,
+    };
+
+    const rx_pin =
+        if (pins.rx) |rx|
+        if (uart.is_valid_pin(rx, index, .rx))
+            rx
+        else
+            @compileError(std.fmt.comptimePrint("Rx pin {s} is not valid for UART{}", .{ rx.name, index }))
+    else switch (index) {
+        // Provide default rx pins if no pin is specified
+        1 => micro.Pin("PA10"),
+        2 => micro.Pin("PA3"),
+        3 => micro.Pin("PB11"),
+        4 => micro.Pin("PA1"),
+        5 => micro.Pin("PD2"),
+        6 => micro.Pin("PC7"),
+        else => unreachable,
+    };
+
+    // USART1..3 are AF7, USART 4..6 are AF8
+    const alternate_function = if (index <= 3) .af7 else .af8;
+
+    const tx_gpio = micro.Gpio(tx_pin, .{
+        .mode = .alternate_function,
+        .alternate_function = alternate_function,
+    });
+    const rx_gpio = micro.Gpio(rx_pin, .{
+        .mode = .alternate_function,
+        .alternate_function = alternate_function,
+    });
+
+    return struct {
+        parity_read_mask: u8,
+
+        const Self = @This();
+
+        pub fn init(config: micro.uart.Config) !Self {
+            // The following must all be written when the USART is disabled (UE=0).
+            if (@field(peripherals, usart_name).CR1.read().UE == 1)
+                @panic("Trying to initialize " ++ usart_name ++ " while it is already enabled");
+            // LATER: Alternatively, set UE=0 at this point?  Then wait for something?
+            // Or add a destroy() function which disables the USART?
+
+            // enable the USART clock
+            const clk_enable_reg = switch (index) {
+                1, 6 => RCC.APB2ENR,
+                2...5 => RCC.APB1ENR,
+                else => unreachable,
+            };
+            set_reg_field(clk_enable_reg, usart_name ++ "EN", 1);
+
+            tx_gpio.init();
+            rx_gpio.init();
+
+            // clear USART configuration to its default
+            @field(peripherals, usart_name).CR1.raw = 0;
+            @field(peripherals, usart_name).CR2.raw = 0;
+            @field(peripherals, usart_name).CR3.raw = 0;
+
+            // Return error for unsupported combinations
+            if (config.data_bits == .nine and config.parity != null) {
+                // TODO: should we consider this an unsupported word size or unsupported parity?
+                return error.UnsupportedWordSize;
+            } else if (config.data_bits == .seven and config.parity == null) {
+                // TODO: should we consider this an unsupported word size or unsupported parity?
+                return error.UnsupportedWordSize;
+            }
+
+            // set word length
+            // Per the reference manual, M means
+            // - 0: 1 start bit, 8 data bits (7 data + 1 parity, or 8 data), n stop bits, the chip default
+            // - 1: 1 start bit, 9 data bits (8 data + 1 parity, or 9 data), n stop bits
+            const m: u1 = if (config.data_bits == .nine or (config.data_bits == .eight and config.parity != null)) 1 else 0;
+            @field(peripherals, usart_name).CR1.modify(.{ .M = m });
+
+            // set parity
+            if (config.parity) |parity| {
+                @field(peripherals, usart_name).CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) });
+            } // otherwise, no need to set no parity since we reset Control Registers above, and it's the default
+
+            // set number of stop bits
+            @field(peripherals, usart_name).CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) });
+
+            // set the baud rate
+            // Despite the reference manual talking about fractional calculation and other buzzwords,
+            // it is actually just a simple divider. Just ignore DIV_Mantissa and DIV_Fraction and
+            // set the result of the division as the lower 16 bits of BRR.
+            // TODO: We assume the default OVER8=0 configuration above (i.e. 16x oversampling).
+            // TODO: Do some checks to see if the baud rate is too high (or perhaps too low)
+            // TODO: Do a rounding div, instead of a truncating div?
+            const clocks = micro.clock.get();
+            const bus_frequency = switch (index) {
+                1, 6 => clocks.apb2,
+                2...5 => clocks.apb1,
+                else => unreachable,
+            };
+            const usartdiv = @intCast(u16, @divTrunc(bus_frequency, config.baud_rate));
+            @field(peripherals, usart_name).BRR.raw = usartdiv;
+
+            // enable USART, and its transmitter and receiver
+            @field(peripherals, usart_name).CR1.modify(.{ .UE = 1 });
+            @field(peripherals, usart_name).CR1.modify(.{ .TE = 1 });
+            @field(peripherals, usart_name).CR1.modify(.{ .RE = 1 });
+
+            // For code simplicity, at cost of one or more register reads,
+            // we read back the actual configuration from the registers,
+            // instead of using the `config` values.
+            return read_from_registers();
+        }
+
+        pub fn get_or_init(config: micro.uart.Config) !Self {
+            if (@field(peripherals, usart_name).CR1.read().UE == 1) {
+                // UART1 already enabled, don't reinitialize and disturb things;
+                // instead read and use the actual configuration.
+                return read_from_registers();
+            } else return init(config);
+        }
+
+        fn read_from_registers() Self {
+            const cr1 = @field(peripherals, usart_name).CR1.read();
+            // As documented in `init()`, M0==1 means 'the 9th bit (not the 8th bit) is the parity bit'.
+            // So we always mask away the 9th bit, and if parity is enabled and it is in the 8th bit,
+            // then we also mask away the 8th bit.
+            return Self{ .parity_read_mask = if (cr1.PCE == 1 and cr1.M == 0) 0x7F else 0xFF };
+        }
+
+        pub fn can_write(self: Self) bool {
+            _ = self;
+            return switch (@field(peripherals, usart_name).SR.read().TXE) {
+                1 => true,
+                0 => false,
+            };
+        }
+
+        pub fn tx(self: Self, ch: u8) void {
+            while (!self.can_write()) {} // Wait for Previous transmission
+            @field(peripherals, usart_name).DR.modify(ch);
+        }
+
+        pub fn txflush(_: Self) void {
+            while (@field(peripherals, usart_name).SR.read().TC == 0) {}
+        }
+
+        pub fn can_read(self: Self) bool {
+            _ = self;
+            return switch (@field(peripherals, usart_name).SR.read().RXNE) {
+                1 => true,
+                0 => false,
+            };
+        }
+
+        pub fn rx(self: Self) u8 {
+            while (!self.can_read()) {} // Wait till the data is received
+            const data_with_parity_bit: u9 = @field(peripherals, usart_name).DR.read();
+            return @intCast(u8, data_with_parity_bit & self.parity_read_mask);
+        }
+    };
+}
+
+pub const i2c = struct {
+    const PinLine = std.meta.FieldEnum(micro.i2c.Pins);
+
+    /// Checks if a pin is valid for a given i2c index and line
+    pub fn is_valid_pin(comptime pin: type, comptime index: usize, comptime line: PinLine) bool {
+        const pin_name = pin.name;
+
+        return switch (line) {
+            .scl => switch (index) {
+                1 => std.mem.eql(u8, pin_name, "PB6") or std.mem.eql(u8, pin_name, "PB8"),
+                2 => std.mem.eql(u8, pin_name, "PB10") or std.mem.eql(u8, pin_name, "PF1") or std.mem.eql(u8, pin_name, "PH4"),
+                3 => std.mem.eql(u8, pin_name, "PA8") or std.mem.eql(u8, pin_name, "PH7"),
+                else => unreachable,
+            },
+            // Valid RX pins for the UARTs
+            .sda => switch (index) {
+                1 => std.mem.eql(u8, pin_name, "PB7") or std.mem.eql(u8, pin_name, "PB9"),
+                2 => std.mem.eql(u8, pin_name, "PB11") or std.mem.eql(u8, pin_name, "PF0") or std.mem.eql(u8, pin_name, "PH5"),
+                3 => std.mem.eql(u8, pin_name, "PC9") or std.mem.eql(u8, pin_name, "PH8"),
+                else => unreachable,
+            },
+        };
+    }
+};
+
+pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type {
+    if (index < 1 or index > 3) @compileError("Valid I2C index are 1..3");
+
+    const i2c_name = std.fmt.comptimePrint("I2C{d}", .{index});
+    const scl_pin =
+        if (pins.scl) |scl|
+        if (uart.is_valid_pin(scl, index, .scl))
+            scl
+        else
+            @compileError(std.fmt.comptimePrint("SCL pin {s} is not valid for I2C{}", .{ scl.name, index }))
+    else switch (index) {
+        // Provide default scl pins if no pin is specified
+        1 => micro.Pin("PB6"),
+        2 => micro.Pin("PB10"),
+        3 => micro.Pin("PA8"),
+        else => unreachable,
+    };
+
+    const sda_pin =
+        if (pins.sda) |sda|
+        if (uart.is_valid_pin(sda, index, .sda))
+            sda
+        else
+            @compileError(std.fmt.comptimePrint("SDA pin {s} is not valid for UART{}", .{ sda.name, index }))
+    else switch (index) {
+        // Provide default sda pins if no pin is specified
+        1 => micro.Pin("PB7"),
+        2 => micro.Pin("PB11"),
+        3 => micro.Pin("PC9"),
+        else => unreachable,
+    };
+
+    const scl_gpio = micro.Gpio(scl_pin, .{
+        .mode = .alternate_function,
+        .alternate_function = .af4,
+    });
+    const sda_gpio = micro.Gpio(sda_pin, .{
+        .mode = .alternate_function,
+        .alternate_function = .af4,
+    });
+
+    // Base field of the specific I2C peripheral
+    const i2c_base = @field(peripherals, i2c_name);
+
+    return struct {
+        const Self = @This();
+
+        pub fn init(config: micro.i2c.Config) !Self {
+            // Configure I2C
+
+            // 1. Enable the I2C CLOCK and GPIO CLOCK
+            RCC.APB1ENR.modify(.{ .I2C1EN = 1 });
+            RCC.AHB1ENR.modify(.{ .GPIOBEN = 1 });
+
+            // 2. Configure the I2C PINs
+            // This takes care of setting them alternate function mode with the correct AF
+            scl_gpio.init();
+            sda_gpio.init();
+
+            // TODO: the stuff below will probably use the microzig gpio API in the future
+            const scl = scl_pin.source_pin;
+            const sda = sda_pin.source_pin;
+            // Select Open Drain Output
+            set_reg_field(@field(scl.gpio_port, "OTYPER"), "OT" ++ scl.suffix, 1);
+            set_reg_field(@field(sda.gpio_port, "OTYPER"), "OT" ++ sda.suffix, 1);
+            // Select High Speed
+            set_reg_field(@field(scl.gpio_port, "OSPEEDR"), "OSPEEDR" ++ scl.suffix, 0b10);
+            set_reg_field(@field(sda.gpio_port, "OSPEEDR"), "OSPEEDR" ++ sda.suffix, 0b10);
+            // Activate Pull-up
+            set_reg_field(@field(scl.gpio_port, "PUPDR"), "PUPDR" ++ scl.suffix, 0b01);
+            set_reg_field(@field(sda.gpio_port, "PUPDR"), "PUPDR" ++ sda.suffix, 0b01);
+
+            // 3. Reset the I2C
+            i2c_base.CR1.modify(.{ .PE = 0 });
+            while (i2c_base.CR1.read().PE == 1) {}
+
+            // 4. Configure I2C timing
+            const bus_frequency_hz = micro.clock.get().apb1;
+            const bus_frequency_mhz: u6 = @intCast(u6, @divExact(bus_frequency_hz, 1_000_000));
+
+            if (bus_frequency_mhz < 2 or bus_frequency_mhz > 50) {
+                return error.InvalidBusFrequency;
+            }
+
+            // .FREQ is set to the bus frequency in Mhz
+            i2c_base.CR2.modify(.{ .FREQ = bus_frequency_mhz });
+
+            switch (config.target_speed) {
+                10_000...100_000 => {
+                    // CCR is bus_freq / (target_speed * 2). We use floor to avoid exceeding the target speed.
+                    const ccr = @intCast(u12, @divFloor(bus_frequency_hz, config.target_speed * 2));
+                    i2c_base.CCR.modify(.{ .CCR = ccr });
+                    // Trise is bus frequency in Mhz + 1
+                    i2c_base.TRISE.modify(bus_frequency_mhz + 1);
+                },
+                100_001...400_000 => {
+                    // TODO: handle fast mode
+                    return error.InvalidSpeed;
+                },
+                else => return error.InvalidSpeed,
+            }
+
+            // 5. Program the I2C_CR1 register to enable the peripheral
+            i2c_base.CR1.modify(.{ .PE = 1 });
+
+            return Self{};
+        }
+
+        pub const WriteState = struct {
+            address: u7,
+            buffer: [255]u8 = undefined,
+            buffer_size: u8 = 0,
+
+            pub fn start(address: u7) !WriteState {
+                return WriteState{ .address = address };
+            }
+
+            pub fn write_all(self: *WriteState, bytes: []const u8) !void {
+                std.debug.assert(self.buffer_size < 255);
+                for (bytes) |b| {
+                    self.buffer[self.buffer_size] = b;
+                    self.buffer_size += 1;
+                    if (self.buffer_size == 255) {
+                        try self.send_buffer();
+                    }
+                }
+            }
+
+            fn send_buffer(self: *WriteState) !void {
+                if (self.buffer_size == 0) @panic("write of 0 bytes not supported");
+
+                // Wait for the bus to be free
+                while (i2c_base.SR2.read().BUSY == 1) {}
+
+                // Send start
+                i2c_base.CR1.modify(.{ .START = 1 });
+
+                // Wait for the end of the start condition, master mode selected, and BUSY bit set
+                while ((i2c_base.SR1.read().SB == 0 or
+                    i2c_base.SR2.read().MSL == 0 or
+                    i2c_base.SR2.read().BUSY == 0))
+                {}
+
+                // Write the address to bits 7..1, bit 0 stays at 0 to indicate write operation
+                i2c_base.DR.modify(@intCast(u8, self.address) << 1);
+
+                // Wait for address confirmation
+                while (i2c_base.SR1.read().ADDR == 0) {}
+
+                // Read SR2 to clear address condition
+                _ = i2c_base.SR2.read();
+
+                for (self.buffer[0..self.buffer_size]) |b| {
+                    // Write data byte
+                    i2c_base.DR.modify(b);
+                    // Wait for transfer finished
+                    while (i2c_base.SR1.read().BTF == 0) {}
+                }
+                self.buffer_size = 0;
+            }
+
+            pub fn stop(self: *WriteState) !void {
+                try self.send_buffer();
+                // Communication STOP
+                i2c_base.CR1.modify(.{ .STOP = 1 });
+                while (i2c_base.SR2.read().BUSY == 1) {}
+            }
+
+            pub fn restart_read(self: *WriteState) !ReadState {
+                try self.send_buffer();
+                return ReadState{ .address = self.address };
+            }
+            pub fn restart_write(self: *WriteState) !WriteState {
+                try self.send_buffer();
+                return WriteState{ .address = self.address };
+            }
+        };
+
+        pub const ReadState = struct {
+            address: u7,
+
+            pub fn start(address: u7) !ReadState {
+                return ReadState{ .address = address };
+            }
+
+            /// Fails with ReadError if incorrect number of bytes is received.
+            pub fn read_no_eof(self: *ReadState, buffer: []u8) !void {
+                std.debug.assert(buffer.len < 256);
+
+                // Send start and enable ACK
+                i2c_base.CR1.modify(.{ .START = 1, .ACK = 1 });
+
+                // Wait for the end of the start condition, master mode selected, and BUSY bit set
+                while ((i2c_base.SR1.read().SB == 0 or
+                    i2c_base.SR2.read().MSL == 0 or
+                    i2c_base.SR2.read().BUSY == 0))
+                {}
+
+                // Write the address to bits 7..1, bit 0 set to 1 to indicate read operation
+                i2c_base.DR.modify((@intCast(u8, self.address) << 1) | 1);
+
+                // Wait for address confirmation
+                while (i2c_base.SR1.read().ADDR == 0) {}
+
+                // Read SR2 to clear address condition
+                _ = i2c_base.SR2.read();
+
+                for (buffer) |_, i| {
+                    if (i == buffer.len - 1) {
+                        // Disable ACK
+                        i2c_base.CR1.modify(.{ .ACK = 0 });
+                    }
+
+                    // Wait for data to be received
+                    while (i2c_base.SR1.read().RxNE == 0) {}
+
+                    // Read data byte
+                    buffer[i] = i2c_base.DR.read();
+                }
+            }
+
+            pub fn stop(_: *ReadState) !void {
+                // Communication STOP
+                i2c_base.CR1.modify(.{ .STOP = 1 });
+                while (i2c_base.SR2.read().BUSY == 1) {}
+            }
+
+            pub fn restart_read(self: *ReadState) !ReadState {
+                return ReadState{ .address = self.address };
+            }
+            pub fn restart_write(self: *ReadState) !WriteState {
+                return WriteState{ .address = self.address };
+            }
+        };
+    };
+}
diff --git a/src/hals/stm32f429.zig b/src/hals/stm32f429.zig
new file mode 100644
index 000000000..3aed96341
--- /dev/null
+++ b/src/hals/stm32f429.zig
@@ -0,0 +1,92 @@
+//! For now we keep all clock settings on the chip defaults.
+//! This code should work with all the STM32F42xx line
+//!
+//! Specifically, TIM6 is running on a 16 MHz clock,
+//! HSI = 16 MHz is the SYSCLK after reset
+//! default AHB prescaler = /1 (= values 0..7):
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .HPRE = 0 });
+//! ```
+//!
+//! so also HCLK = 16 MHz.
+//! And with the default APB1 prescaler = /1:
+//!
+//! ```
+//! RCC.CFGR.modify(.{ .PPRE1 = 0 });
+//! ```
+//!
+//! results in PCLK1 = 16 MHz.
+//!
+//! TODO: add more clock calculations when adding Uart
+
+const std = @import("std");
+const micro = @import("microzig");
+const peripherals = micro.peripherals;
+const RCC = peripherals.RCC;
+
+pub const clock = struct {
+    pub const Domain = enum {
+        cpu,
+        ahb,
+        apb1,
+        apb2,
+    };
+};
+
+// Default clock frequencies after reset, see top comment for calculation
+pub const clock_frequencies = .{
+    .cpu = 16_000_000,
+    .ahb = 16_000_000,
+    .apb1 = 16_000_000,
+    .apb2 = 16_000_000,
+};
+
+pub fn parsePin(comptime spec: []const u8) type {
+    const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme.";
+
+    if (spec[0] != 'P')
+        @compileError(invalid_format_msg);
+    if (spec[1] < 'A' or spec[1] > 'K')
+        @compileError(invalid_format_msg);
+
+    const pin_number: comptime_int = std.fmt.parseInt(u4, spec[2..], 10) catch @compileError(invalid_format_msg);
+
+    return struct {
+        /// 'A'...'K'
+        const gpio_port_name = spec[1..2];
+        const gpio_port = @field(peripherals, "GPIO" ++ gpio_port_name);
+        const suffix = std.fmt.comptimePrint("{d}", .{pin_number});
+    };
+}
+
+fn setRegField(reg: anytype, comptime field_name: anytype, value: anytype) void {
+    var temp = reg.read();
+    @field(temp, field_name) = value;
+    reg.write(temp);
+}
+
+pub const gpio = struct {
+    pub fn setOutput(comptime pin: type) void {
+        setRegField(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
+        setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b01);
+    }
+
+    pub fn setInput(comptime pin: type) void {
+        setRegField(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
+        setRegField(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b00);
+    }
+
+    pub fn read(comptime pin: type) micro.gpio.State {
+        const idr_reg = pin.gpio_port.IDR;
+        const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()?
+        return @intToEnum(micro.gpio.State, reg_value);
+    }
+
+    pub fn write(comptime pin: type, state: micro.gpio.State) void {
+        switch (state) {
+            .low => setRegField(pin.gpio_port.BSRR, "BR" ++ pin.suffix, 1),
+            .high => setRegField(pin.gpio_port.BSRR, "BS" ++ pin.suffix, 1),
+        }
+    }
+};
diff --git a/test/programs/minimal.zig b/test/programs/minimal.zig
new file mode 100644
index 000000000..5258ce311
--- /dev/null
+++ b/test/programs/minimal.zig
@@ -0,0 +1,5 @@
+const micro = @import("microzig");
+
+pub fn main() void {
+    // This function will contain the application logic.
+}
diff --git a/tests/stm32f103.robot b/test/stm32f103.robot
similarity index 100%
rename from tests/stm32f103.robot
rename to test/stm32f103.robot

From 470cd86348977833936a477bccded645743ff444 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 18 Feb 2023 12:01:58 -0500
Subject: [PATCH 040/286] add microzig submodule and buildkite pipeline file
 (#1)

---
 .buildkite/pipeline.yml | 6 ++++++
 .gitmodules             | 3 +++
 deps/microzig           | 1 +
 3 files changed, 10 insertions(+)
 create mode 100644 .buildkite/pipeline.yml
 create mode 100644 .gitmodules
 create mode 160000 deps/microzig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
new file mode 100644
index 000000000..5fd8795bc
--- /dev/null
+++ b/.buildkite/pipeline.yml
@@ -0,0 +1,6 @@
+steps:
+  - group: Build and Test
+    steps:
+    - command: zig build
+    - label: 🔨 Test
+      command: renode-test test/nrf52840.robot
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 000000000..32e895ccb
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "deps/microzig"]
+	path = deps/microzig
+	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/deps/microzig b/deps/microzig
new file mode 160000
index 000000000..97ca5497d
--- /dev/null
+++ b/deps/microzig
@@ -0,0 +1 @@
+Subproject commit 97ca5497da0f22d025e18bced9311efed088d893

From 42c7a62a3f76d07086e506398f670b04e88fe618 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 18 Feb 2023 16:37:02 -0500
Subject: [PATCH 041/286] Initial commit

---
 .buildkite/pipeline.yml   |  4 ++++
 .gitignore                |  2 ++
 .gitmodules               |  3 +++
 LICENSE                   | 19 +++++++++++++++++++
 README.adoc               |  6 ++++++
 build.zig                 | 35 +++++++++++++++++++++++++++++++++++
 deps/microzig             |  1 +
 src/boards.zig            |  6 ++++++
 src/chips.zig             |  6 ++++++
 test/programs/minimal.zig |  5 +++++
 10 files changed, 87 insertions(+)
 create mode 100644 .buildkite/pipeline.yml
 create mode 100644 .gitignore
 create mode 100644 .gitmodules
 create mode 100644 LICENSE
 create mode 100644 README.adoc
 create mode 100644 build.zig
 create mode 160000 deps/microzig
 create mode 100644 src/boards.zig
 create mode 100644 src/chips.zig
 create mode 100644 test/programs/minimal.zig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
new file mode 100644
index 000000000..7767bbb66
--- /dev/null
+++ b/.buildkite/pipeline.yml
@@ -0,0 +1,4 @@
+steps:
+  - group: Build
+    steps:
+    - command: zig build
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 000000000..4c82b07c0
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+zig-cache
+zig-out
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 000000000..32e895ccb
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "deps/microzig"]
+	path = deps/microzig
+	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 000000000..c1cc5ecad
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,19 @@
+Copyright (c) 2022 
+
+This software is provided 'as-is', without any express or implied warranty. In
+no event will the authors be held liable for any damages arising from the use
+of this software.
+
+Permission is granted to anyone to use this software for any purpose, including
+commercial applications, and to alter it and redistribute it freely, subject to
+the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must not claim
+that you wrote the original software. If you use this software in a product, an
+acknowledgment in the product documentation would be appreciated but is not
+required.
+
+2. Altered source versions must be plainly marked as such, and must not be
+misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source distribution.
diff --git a/README.adoc b/README.adoc
new file mode 100644
index 000000000..46ca05775
--- /dev/null
+++ b/README.adoc
@@ -0,0 +1,6 @@
+= Hardware Support Package Template
+
+1. Update LICENSE file
+2. Update `microzig` submodule under `deps/`
+3. Add chips/boards/hals
+4. Set up buildkite pipeline
diff --git a/build.zig b/build.zig
new file mode 100644
index 000000000..3b787fe3f
--- /dev/null
+++ b/build.zig
@@ -0,0 +1,35 @@
+const std = @import("std");
+const microzig = @import("deps/microzig/src/main.zig");
+const boards = @import("src/boards.zig");
+const chips = @import("src/chips.zig");
+
+pub fn build(b: *std.build.Builder) void {
+    const optimize = b.standardOptimizeOption(.{});
+    inline for (@typeInfo(boards).Struct.decls) |decl| {
+        if (!decl.is_pub)
+            continue;
+
+        const exe = microzig.addEmbeddedExecutable(
+            b,
+            @field(boards, decl.name).name ++ ".minimal",
+            "test/programs/minimal.zig",
+            .{ .board = @field(boards, decl.name) },
+            .{ .optimize = optimize },
+        );
+        exe.install();
+    }
+
+    inline for (@typeInfo(chips).Struct.decls) |decl| {
+        if (!decl.is_pub)
+            continue;
+
+        const exe = microzig.addEmbeddedExecutable(
+            b,
+            @field(chips, decl.name).name ++ ".minimal",
+            "test/programs/minimal.zig",
+            .{ .chip = @field(chips, decl.name) },
+            .{ .optimize = optimize },
+        );
+        exe.install();
+    }
+}
diff --git a/deps/microzig b/deps/microzig
new file mode 160000
index 000000000..97ca5497d
--- /dev/null
+++ b/deps/microzig
@@ -0,0 +1 @@
+Subproject commit 97ca5497da0f22d025e18bced9311efed088d893
diff --git a/src/boards.zig b/src/boards.zig
new file mode 100644
index 000000000..2cb647a34
--- /dev/null
+++ b/src/boards.zig
@@ -0,0 +1,6 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/src/main.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse ".";
+}
diff --git a/src/chips.zig b/src/chips.zig
new file mode 100644
index 000000000..2cb647a34
--- /dev/null
+++ b/src/chips.zig
@@ -0,0 +1,6 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/src/main.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse ".";
+}
diff --git a/test/programs/minimal.zig b/test/programs/minimal.zig
new file mode 100644
index 000000000..5258ce311
--- /dev/null
+++ b/test/programs/minimal.zig
@@ -0,0 +1,5 @@
+const micro = @import("microzig");
+
+pub fn main() void {
+    // This function will contain the application logic.
+}

From fe247e6669a5e7fb56fd74c1c70453bc5c8fcdac Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 18 Feb 2023 17:01:25 -0500
Subject: [PATCH 042/286] add chip and board definitions (#1)

---
 LICENSE                     |     2 +-
 README.adoc                 |     7 +-
 src/boards.zig              |     9 +-
 src/boards/mbed_LPC1768.zig |    84 +
 src/chips.zig               |    16 +-
 src/chips/LPC176x5x.json    | 29776 ++++++++++++++++++++++++++++++++++
 src/chips/LPC176x5x.zig     | 12741 +++++++++++++++
 src/hals/LPC176x5x.zig      |   205 +
 8 files changed, 42831 insertions(+), 9 deletions(-)
 create mode 100644 src/boards/mbed_LPC1768.zig
 create mode 100644 src/chips/LPC176x5x.json
 create mode 100644 src/chips/LPC176x5x.zig
 create mode 100644 src/hals/LPC176x5x.zig

diff --git a/LICENSE b/LICENSE
index c1cc5ecad..bcb425d88 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,4 +1,4 @@
-Copyright (c) 2022 
+Copyright (c) 2022 Zig Embedded Group Contributors
 
 This software is provided 'as-is', without any express or implied warranty. In
 no event will the authors be held liable for any damages arising from the use
diff --git a/README.adoc b/README.adoc
index 46ca05775..6e0fc7d9c 100644
--- a/README.adoc
+++ b/README.adoc
@@ -1,6 +1,3 @@
-= Hardware Support Package Template
+= NXP LPC Hardware Support Package
 
-1. Update LICENSE file
-2. Update `microzig` submodule under `deps/`
-3. Add chips/boards/hals
-4. Set up buildkite pipeline
+Please see https://github.com/ZigEmbeddedGroup/lpcboot[lpcboot] as well
diff --git a/src/boards.zig b/src/boards.zig
index 2cb647a34..1690f0d93 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -1,6 +1,13 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/src/main.zig");
+const chips = @import("chips.zig");
 
 fn root_dir() []const u8 {
     return std.fs.path.dirname(@src().file) orelse ".";
 }
+
+pub const mbed_lpc1768 = micro.Board{
+    .name = "mbed LPC1768",
+    .source = .{ .path = root_dir() ++ "/boards/mbed_LPC1768.zig" },
+    .chip = chips.lpc176x5x,
+};
diff --git a/src/boards/mbed_LPC1768.zig b/src/boards/mbed_LPC1768.zig
new file mode 100644
index 000000000..5cf0bd09e
--- /dev/null
+++ b/src/boards/mbed_LPC1768.zig
@@ -0,0 +1,84 @@
+pub const chip = @import("chip");
+pub const micro = @import("microzig");
+
+pub const clock_frequencies = .{
+    .cpu = 100_000_000, // 100 Mhz
+};
+
+pub fn debug_write(string: []const u8) void {
+    const clk_pin = micro.Pin("DIP5");
+    const dat_pin = micro.Pin("DIP6");
+
+    const clk = micro.core.experimental.Gpio(clk_pin, .{ .mode = .output, .initial_state = .low });
+    const dat = micro.core.experimental.Gpio(dat_pin, .{ .mode = .output, .initial_state = .low });
+
+    clk.init();
+    dat.init();
+
+    micro.debug.busy_sleep(1_000);
+
+    for (string) |c| {
+        comptime var i: usize = 128;
+        inline while (i > 0) : (i = i >> 1) {
+            if ((c & i) != 0) {
+                dat.write(.high);
+            } else {
+                dat.write(.low);
+            }
+            clk.write(.high);
+            micro.debug.busy_sleep(1_000);
+            clk.write(.low);
+            micro.debug.busy_sleep(1_000);
+        }
+    }
+    dat.write(.low);
+    clk.write(.low);
+}
+
+pub const pin_map = .{
+    // Onboard-LEDs
+    .@"LED-1" = "P1.18",
+    .@"LED-2" = "P1.20",
+    .@"LED-3" = "P1.21",
+    .@"LED-4" = "P1.23",
+    .LED_LINK = "P1.25",
+    .LED_SPEED = "P1.26",
+
+    // Ethernet
+    .@"TD+" = "P1.0",
+    .@"TD-" = "P1.1",
+    .@"RD+" = "P1.9",
+    .@"RD-" = "P1.10",
+
+    // USB
+    .@"D+" = "P0.29",
+    .@"D-" = "P0.30",
+
+    // GPIO pins
+    .DIP5 = "P0.9",
+    .DIP6 = "P0.8",
+    .DIP7 = "P0.7",
+    .DIP8 = "P0.6",
+    .DIP9 = "P0.0",
+    .DIP10 = "P0.1",
+    .DIP11 = "P0.18",
+    .DIP12 = "P0.17",
+    .DIP13 = "P0.15",
+    .DIP14 = "P0.16",
+    .DIP15 = "P0.23",
+    .DIP16 = "P0.24",
+    .DIP17 = "P0.25",
+    .DIP18 = "P0.26",
+    .DIP19 = "P1.30",
+    .DIP20 = "P1.31",
+    .DIP21 = "P2.5",
+    .DIP22 = "P2.4",
+    .DIP23 = "P2.3",
+    .DIP24 = "P2.2",
+    .DIP25 = "P2.1",
+    .DIP26 = "P2.0",
+    .DIP27 = "P0.11",
+    .DIP28 = "P0.10",
+    .DIP29 = "P0.5",
+    .DIP30 = "P0.4",
+};
diff --git a/src/chips.zig b/src/chips.zig
index 2cb647a34..0e8592591 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,6 +1,18 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/src/main.zig");
+const Chip = micro.Chip;
+const MemoryRegion = micro.MemoryRegion;
 
 fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse ".";
+    return std.fs.path.dirname(@src().file) orelse unreachable;
 }
+
+pub const lpc176x5x = Chip.from_standard_paths(root_dir(), .{
+    .name = "LPC176x5x",
+    .cpu = micro.cpus.cortex_m3,
+    .memory_regions = &.{
+        MemoryRegion{ .offset = 0x00000000, .length = 512 * 1024, .kind = .flash },
+        MemoryRegion{ .offset = 0x10000000, .length = 32 * 1024, .kind = .ram },
+        MemoryRegion{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram },
+    },
+});
diff --git a/src/chips/LPC176x5x.json b/src/chips/LPC176x5x.json
new file mode 100644
index 000000000..5b179895a
--- /dev/null
+++ b/src/chips/LPC176x5x.json
@@ -0,0 +1,29776 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "WDT": {
+        "description": "Watchdog Timer (WDT) ",
+        "children": {
+          "registers": {
+            "MOD": {
+              "description": "Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDEN": {
+                    "description": "Watchdog enable bit. This bit is Set Only.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "STOP": {
+                            "description": "The watchdog timer is stopped.",
+                            "value": 0
+                          },
+                          "RUN": {
+                            "description": "The watchdog timer is running.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WDRESET": {
+                    "description": "Watchdog reset enable bit. This bit is Set Only. See Table 652.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORESET": {
+                            "description": "A watchdog timeout will not cause a chip reset.",
+                            "value": 0
+                          },
+                          "RESET": {
+                            "description": "A watchdog timeout will cause a chip reset.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WDTOF": {
+                    "description": "Watchdog time-out flag. Set when the watchdog timer times out, cleared by software.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "WDINT": {
+                    "description": "Watchdog interrupt flag.  Cleared by software.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "TC": {
+              "description": "Watchdog timer constant register. The value in this register determines the time-out value.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 255,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "Count": {
+                    "description": "Watchdog time-out interval.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FEED": {
+              "description": "Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "Feed": {
+                    "description": "Feed value should be 0xAA followed by 0x55.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TV": {
+              "description": "Watchdog timer value register. This register reads out the current value of the Watchdog timer.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 255,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "Count": {
+                    "description": "Counter timer value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CLKSEL": {
+              "description": "Watchdog clock select register.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 1,
+                    "size": 30
+                  },
+                  "LOCK": {
+                    "description": "If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0.",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "UNLOCKED": {
+                            "description": "This bit is set to 0 on any reset. It cannot be cleared by software.",
+                            "value": 0
+                          },
+                          "LOCKED": {
+                            "description": "Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register\n\t\t\t\t\t\t\t\t\t\tcannot be modified.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIMER0": {
+        "description": "Timer0/1/2/3  ",
+        "children": {
+          "registers": {
+            "IR": {
+              "description": "Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR0INT": {
+                    "description": "Interrupt flag for match channel 0.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MR1INT": {
+                    "description": "Interrupt flag for match channel 1.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MR2INT": {
+                    "description": "Interrupt flag for match channel 2.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MR3INT": {
+                    "description": "Interrupt flag for match channel 3.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CR0INT": {
+                    "description": "Interrupt flag for capture channel 0 event.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CR1INT": {
+                    "description": "Interrupt flag for capture channel 1 event.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "TCR": {
+              "description": "Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CEN": {
+                    "description": "When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CRST": {
+                    "description": "When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "TC": {
+              "description": "Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TC": {
+                    "description": "Timer counter value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PR": {
+              "description": "Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PM": {
+                    "description": "Prescale counter maximum value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PC": {
+              "description": "Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PC": {
+                    "description": "Prescale counter value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MCR": {
+              "description": "Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MR0I": {
+                    "description": "Interrupt on MR0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_IS_GENERAT": {
+                            "description": "Interrupt is generated when MR0 matches the value in the TC.",
+                            "value": 1
+                          },
+                          "INTERRUPT_IS_DISABLE": {
+                            "description": "Interrupt is disabled",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MR0R": {
+                    "description": "Reset on MR0",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TC_WILL_BE_RESET_IF_": {
+                            "description": "TC will be reset if MR0 matches it.",
+                            "value": 1
+                          },
+                          "FEATURE_DISABLED_": {
+                            "description": "Feature disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MR0S": {
+                    "description": "Stop on MR0",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TC_AND_PC_WILL_BE_ST": {
+                            "description": "TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.",
+                            "value": 1
+                          },
+                          "FEATURE_DISABLED_": {
+                            "description": "Feature disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MR1I": {
+                    "description": "Interrupt on MR1",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_IS_GENERAT": {
+                            "description": "Interrupt is generated when MR1 matches the value in the TC.",
+                            "value": 1
+                          },
+                          "INTERRUPT_IS_DISABLE": {
+                            "description": "Interrupt is disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MR1R": {
+                    "description": "Reset on MR1",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TC_WILL_BE_RESET_IF_": {
+                            "description": "TC will be reset if MR1 matches it.",
+                            "value": 1
+                          },
+                          "FEATURE_DISABLED_": {
+                            "description": "Feature disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MR1S": {
+                    "description": "Stop on MR1",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TC_AND_PC_WILL_BE_ST": {
+                            "description": "TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.",
+                            "value": 1
+                          },
+                          "FEATURE_DISABLED_": {
+                            "description": "Feature disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MR2I": {
+                    "description": "Interrupt on MR2",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_IS_GENERAT": {
+                            "description": "Interrupt is generated when MR2 matches the value in the TC.",
+                            "value": 1
+                          },
+                          "INTERRUPT_IS_DISABLE": {
+                            "description": "Interrupt is disabled",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MR2R": {
+                    "description": "Reset on MR2",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TC_WILL_BE_RESET_IF_": {
+                            "description": "TC will be reset if MR2 matches it.",
+                            "value": 1
+                          },
+                          "FEATURE_DISABLED_": {
+                            "description": "Feature disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MR2S": {
+                    "description": "Stop on MR2.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TC_AND_PC_WILL_BE_ST": {
+                            "description": "TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC",
+                            "value": 1
+                          },
+                          "FEATURE_DISABLED_": {
+                            "description": "Feature disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MR3I": {
+                    "description": "Interrupt on MR3",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_IS_GENERAT": {
+                            "description": "Interrupt is generated when MR3 matches the value in the TC.",
+                            "value": 1
+                          },
+                          "THIS_INTERRUPT_IS_DI": {
+                            "description": "This interrupt is disabled",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MR3R": {
+                    "description": "Reset on MR3",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TC_WILL_BE_RESET_IF_": {
+                            "description": "TC will be reset if MR3 matches it.",
+                            "value": 1
+                          },
+                          "FEATURE_DISABLED_": {
+                            "description": "Feature disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MR3S": {
+                    "description": "Stop on MR3",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TC_AND_PC_WILL_BE_ST": {
+                            "description": "TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.",
+                            "value": 1
+                          },
+                          "FEATURE_DISABLED_": {
+                            "description": "Feature disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 12,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CAP0RE": {
+                    "description": "Capture on CAPn.0 rising edge",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLE": {
+                            "description": "A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC.",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "This feature is disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CAP0FE": {
+                    "description": "Capture on CAPn.0 falling edge",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLE": {
+                            "description": "A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC.",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "This feature is disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CAP0I": {
+                    "description": "Interrupt on CAPn.0 event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLE": {
+                            "description": "A CR0 load due to a CAPn.0 event will generate an interrupt.",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "This feature is disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CAP1RE": {
+                    "description": "Capture on CAPn.1 rising edge",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLE": {
+                            "description": "A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC.",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "This feature is disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CAP1FE": {
+                    "description": "Capture on CAPn.1 falling edge",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLE": {
+                            "description": "A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC.",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "This feature is disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CAP1I": {
+                    "description": "Interrupt on CAPn.1 event",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLE": {
+                            "description": "A CR1 load due to a CAPn.1 event will generate an interrupt.",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "This feature is disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "EMR": {
+              "description": "External Match Register. The EMR controls the external match pins.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EM0": {
+                    "description": "External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EM1": {
+                    "description": "External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EM2": {
+                    "description": "External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EM3": {
+                    "description": "External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EMC0": {
+                    "description": "External Match Control 0. Determines the functionality of External Match 0.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "DO_NOTHING_": {
+                            "description": "Do Nothing.",
+                            "value": 0
+                          },
+                          "CLEAR_THE_CORRESPOND": {
+                            "description": "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).",
+                            "value": 1
+                          },
+                          "SET_THE_CORRESPONDIN": {
+                            "description": "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).",
+                            "value": 2
+                          },
+                          "TOGGLE_THE_CORRESPON": {
+                            "description": "Toggle the corresponding External Match bit/output.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EMC1": {
+                    "description": "External Match Control 1. Determines the functionality of External Match 1.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "DO_NOTHING_": {
+                            "description": "Do Nothing.",
+                            "value": 0
+                          },
+                          "CLEAR_THE_CORRESPOND": {
+                            "description": "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).",
+                            "value": 1
+                          },
+                          "SET_THE_CORRESPONDIN": {
+                            "description": "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).",
+                            "value": 2
+                          },
+                          "TOGGLE_THE_CORRESPON": {
+                            "description": "Toggle the corresponding External Match bit/output.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EMC2": {
+                    "description": "External Match Control 2. Determines the functionality of External Match 2.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "DO_NOTHING_": {
+                            "description": "Do Nothing.",
+                            "value": 0
+                          },
+                          "CLEAR_THE_CORRESPOND": {
+                            "description": "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).",
+                            "value": 1
+                          },
+                          "SET_THE_CORRESPONDIN": {
+                            "description": "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).",
+                            "value": 2
+                          },
+                          "TOGGLE_THE_CORRESPON": {
+                            "description": "Toggle the corresponding External Match bit/output.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EMC3": {
+                    "description": "External Match Control 3. Determines the functionality of External Match 3.",
+                    "offset": 10,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "DO_NOTHING_": {
+                            "description": "Do Nothing.",
+                            "value": 0
+                          },
+                          "CLEAR_THE_CORRESPOND": {
+                            "description": "Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).",
+                            "value": 1
+                          },
+                          "SET_THE_CORRESPONDIN": {
+                            "description": "Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).",
+                            "value": 2
+                          },
+                          "TOGGLE_THE_CORRESPON": {
+                            "description": "Toggle the corresponding External Match bit/output.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 12,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "CTCR": {
+              "description": "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTMODE": {
+                    "description": "Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER_MODE_EVERY_RI": {
+                            "description": "Timer Mode: every rising PCLK edge",
+                            "value": 0
+                          },
+                          "RISING": {
+                            "description": "Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.",
+                            "value": 1
+                          },
+                          "FALLING": {
+                            "description": "Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.",
+                            "value": 2
+                          },
+                          "DUALEDGE": {
+                            "description": "Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CINSEL": {
+                    "description": "Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CAPN_0_FOR_TIMERN": {
+                            "description": "CAPn.0 for TIMERn",
+                            "value": 0
+                          },
+                          "CAPN_1_FOR_TIMERN": {
+                            "description": "CAPn.1 for TIMERn",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIO": {
+        "description": "General Purpose I/O "
+      },
+      "UART0": {
+        "description": "UART0/2/3  ",
+        "children": {
+          "registers": {
+            "RBR": {
+              "description": "Receiver Buffer Register. Contains the next received character to be read (DLAB =0).",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RBR": {
+                    "description": "The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, the value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "THR": {
+              "description": "Transmit Holding Regiter. The next character to be transmitted is written here (DLAB =0).",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "THR": {
+                    "description": "Writing to the UARTn Transmit Holding Register causes the data to be stored in the UARTn transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "DLL": {
+              "description": "Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DLLSB": {
+                    "description": "The UARTn Divisor Latch LSB Register, along with the UnDLM register, determines the baud rate of the UARTn.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "DLM": {
+              "description": "Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DLMSB": {
+                    "description": "The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART interrupts (DLAB =0).",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RBRIE": {
+                    "description": "RBR Interrupt Enable. Enables the Receive Data Available interrupt for UARTn. It also controls the Character Receive Time-out interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_RDA_INTE": {
+                            "description": "Disable the RDA interrupts.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_RDA_INTER": {
+                            "description": "Enable the RDA interrupts.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "THREIE": {
+                    "description": "THRE Interrupt Enable. Enables the THRE interrupt for UARTn. The status of this can be read from UnLSR[5].",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_THRE_INT": {
+                            "description": "Disable the THRE interrupts.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_THRE_INTE": {
+                            "description": "Enable the THRE interrupts.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXIE": {
+                    "description": "RX Line Status Interrupt Enable. Enables the UARTn RX line status interrupts. The status of this interrupt can be read from UnLSR[4:1].",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_RX_LINE_": {
+                            "description": "Disable the RX line status interrupts.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_RX_LINE_S": {
+                            "description": "Enable the RX line status interrupts.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 10,
+                    "size": 22
+                  },
+                  "ABEOINTEN": {
+                    "description": "Enables the end of auto-baud interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_END_OF_AUTO_": {
+                            "description": "Disable end of auto-baud Interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE_END_OF_AUTO_B": {
+                            "description": "Enable end of auto-baud Interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABTOINTEN": {
+                    "description": "Enables the auto-baud time-out interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_AUTO_BAUD_TI": {
+                            "description": "Disable auto-baud time-out Interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE_AUTO_BAUD_TIM": {
+                            "description": "Enable auto-baud time-out Interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IIR": {
+              "description": "Interrupt ID Register. Identifies which interrupt(s) are pending.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INTSTATUS": {
+                    "description": "Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "AT_LEAST_ONE_INTERRU": {
+                            "description": "At least one interrupt is pending.",
+                            "value": 0
+                          },
+                          "NO_INTERRUPT_IS_PEND": {
+                            "description": "No interrupt is pending.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTID": {
+                    "description": "Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).",
+                    "offset": 1,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "1_RECEIVE_LINE_S": {
+                            "description": "1   - Receive Line Status (RLS).",
+                            "value": 3
+                          },
+                          "2A__RECEIVE_DATA_AV": {
+                            "description": "2a - Receive Data Available (RDA).",
+                            "value": 2
+                          },
+                          "2B__CHARACTER_TIME_": {
+                            "description": "2b - Character Time-out Indicator (CTI).",
+                            "value": 6
+                          },
+                          "3_THRE_INTERRUPT": {
+                            "description": "3   - THRE Interrupt",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 10,
+                    "size": 22
+                  },
+                  "FIFOENABLE": {
+                    "description": "Copies of UnFCR[0].",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "ABEOINT": {
+                    "description": "End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ABTOINT": {
+                    "description": "Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FCR": {
+              "description": "FIFO Control Register. Controls UART FIFO usage and modes.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "FIFOEN": {
+                    "description": "FIFO Enable.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "UARTN_FIFOS_ARE_DISA": {
+                            "description": "UARTn FIFOs are disabled. Must not be used in the application.",
+                            "value": 0
+                          },
+                          "ACTIVE_HIGH_ENABLE_F": {
+                            "description": "Active high enable for both UARTn Rx and TX FIFOs and UnFCR[7:1] access. This bit must be set for proper UART operation. Any transition on this bit will automatically clear the related UART FIFOs.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFIFORES": {
+                    "description": "RX FIFO Reset.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_IMPACT_ON_EITHER_": {
+                            "description": "No impact on either of UARTn FIFOs.",
+                            "value": 0
+                          },
+                          "WRITING_A_LOGIC_1_TO": {
+                            "description": "Writing a logic 1 to UnFCR[1] will clear all bytes in UARTn Rx FIFO, reset the pointer logic. This bit is self-clearing.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFIFORES": {
+                    "description": "TX FIFO Reset.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_IMPACT_ON_EITHER_": {
+                            "description": "No impact on either of UARTn FIFOs.",
+                            "value": 0
+                          },
+                          "WRITING_A_LOGIC_1_TO": {
+                            "description": "Writing a logic 1 to UnFCR[2] will clear all bytes in UARTn TX FIFO, reset the pointer logic. This bit is self-clearing.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DMAMODE": {
+                    "description": "DMA Mode Select. When the FIFO enable (bit 0 of this register) is set, this bit selects the DMA mode. See Section 18.6.6.1.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "RXTRIGLVL": {
+                    "description": "RX Trigger Level. These two bits determine how many receiver UARTn FIFO characters must be written before an interrupt or DMA request is activated.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "TRIGGER_LEVEL_0_1_C": {
+                            "description": "Trigger level 0 (1 character or 0x01).",
+                            "value": 0
+                          },
+                          "TRIGGER_LEVEL_1_4_C": {
+                            "description": "Trigger level 1 (4 characters or 0x04).",
+                            "value": 1
+                          },
+                          "TRIGGER_LEVEL_2_8_C": {
+                            "description": "Trigger level 2 (8 characters or 0x08).",
+                            "value": 2
+                          },
+                          "TRIGGER_LEVEL_3_14_": {
+                            "description": "Trigger level 3 (14 characters or 0x0E).",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LCR": {
+              "description": "Line Control Register. Contains controls for frame formatting and break generation.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WLS": {
+                    "description": "Word Length Select.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "5_BIT_CHARACTER_LENG": {
+                            "description": "5-bit character length",
+                            "value": 0
+                          },
+                          "6_BIT_CHARACTER_LENG": {
+                            "description": "6-bit character length",
+                            "value": 1
+                          },
+                          "7_BIT_CHARACTER_LENG": {
+                            "description": "7-bit character length",
+                            "value": 2
+                          },
+                          "8_BIT_CHARACTER_LENG": {
+                            "description": "8-bit character length",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SBS": {
+                    "description": "Stop Bit Select",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "1_STOP_BIT_": {
+                            "description": "1 stop bit.",
+                            "value": 0
+                          },
+                          "2_STOP_BITS_1_5_IF_": {
+                            "description": "2 stop bits (1.5 if UnLCR[1:0]=00).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PE": {
+                    "description": "Parity Enable.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_PARITY_GENER": {
+                            "description": "Disable parity generation and checking.",
+                            "value": 0
+                          },
+                          "ENABLE_PARITY_GENERA": {
+                            "description": "Enable parity generation and checking.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PS": {
+                    "description": "Parity Select",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "ODD_PARITY_NUMBER_O": {
+                            "description": "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.",
+                            "value": 0
+                          },
+                          "EVEN_PARITY_NUMBER_": {
+                            "description": "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.",
+                            "value": 1
+                          },
+                          "FORCED_1_STICK_PARIT": {
+                            "description": "Forced 1 stick parity.",
+                            "value": 2
+                          },
+                          "FORCED_0_STICK_PARIT": {
+                            "description": "Forced 0 stick parity.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BC": {
+                    "description": "Break Control",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_BREAK_TRANSM": {
+                            "description": "Disable break transmission.",
+                            "value": 0
+                          },
+                          "ENABLE_BREAK_TRANSMI": {
+                            "description": "Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DLAB": {
+                    "description": "Divisor Latch Access Bit",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_ACCESS_TO_DI": {
+                            "description": "Disable access to Divisor Latches.",
+                            "value": 0
+                          },
+                          "ENABLE_ACCESS_TO_DIV": {
+                            "description": "Enable access to Divisor Latches.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "LSR": {
+              "description": "Line Status Register. Contains flags for transmit and receive status, including line errors.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 96,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RDR": {
+                    "description": "Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "EMPTY": {
+                            "description": "The UARTn receiver FIFO is empty.",
+                            "value": 0
+                          },
+                          "NOTEMPTY": {
+                            "description": "The UARTn receiver FIFO is not empty.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OE": {
+                    "description": "Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "Overrun error status is inactive.",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Overrun error status is active.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PE": {
+                    "description": "Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "Parity error status is inactive.",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Parity error status is active.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FE": {
+                    "description": "Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "Framing error status is inactive.",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Framing error status is active.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BI": {
+                    "description": "Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "Break interrupt status is inactive.",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Break interrupt status is active.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "THRE": {
+                    "description": "Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "VALIDDATA": {
+                            "description": "UnTHR contains valid data.",
+                            "value": 0
+                          },
+                          "EMPTY": {
+                            "description": "UnTHR is empty.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TEMT": {
+                    "description": "Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "VALIDDATA": {
+                            "description": "UnTHR and/or the UnTSR contains valid data.",
+                            "value": 0
+                          },
+                          "EMPTY": {
+                            "description": "UnTHR and the UnTSR are empty.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFE": {
+                    "description": "Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NOERROR": {
+                            "description": "UnRBR contains no UARTn RX errors or UnFCR[0]=0.",
+                            "value": 0
+                          },
+                          "ERRORS": {
+                            "description": "UARTn RBR contains at least one UARTn RX error.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "SCR": {
+              "description": "Scratch Pad Register. 8-bit temporary storage for software.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PAD": {
+                    "description": "A readable, writable byte.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "ACR": {
+              "description": "Auto-baud Control Register. Contains controls for the auto-baud feature.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "START": {
+                    "description": "Start bit. This bit is automatically cleared after auto-baud completion.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "AUTO_BAUD_STOP_AUTO": {
+                            "description": "Auto-baud stop (auto-baud is not running).",
+                            "value": 0
+                          },
+                          "AUTO_BAUD_START_AUT": {
+                            "description": "Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MODE": {
+                    "description": "Auto-baud mode select bit.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MODE_0_": {
+                            "description": "Mode 0.",
+                            "value": 0
+                          },
+                          "MODE_1_": {
+                            "description": "Mode 1.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AUTORESTART": {
+                    "description": "Restart bit.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_RESTART_": {
+                            "description": "No restart.",
+                            "value": 0
+                          },
+                          "RESTART_IN_CASE_OF_T": {
+                            "description": "Restart in case of time-out (counter restarts at next UARTn Rx falling edge)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 10,
+                    "size": 22
+                  },
+                  "ABEOINTCLR": {
+                    "description": "End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_IMPACT_": {
+                            "description": "No impact.",
+                            "value": 0
+                          },
+                          "CLEAR_THE_CORRESPOND": {
+                            "description": "Clear the corresponding interrupt in the IIR.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABTOINTCLR": {
+                    "description": "Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_IMPACT_": {
+                            "description": "No impact.",
+                            "value": 0
+                          },
+                          "CLEAR_THE_CORRESPOND": {
+                            "description": "Clear the corresponding interrupt in the IIR.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FDR": {
+              "description": "Fractional Divider Register. Generates a clock input for the baud rate divider.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIVADDVAL": {
+                    "description": "Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "MULVAL": {
+                    "description": "Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not.",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "TER": {
+              "description": "Transmit Enable Register. Turns off UART transmitter for use with software flow control.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "TXEN": {
+                    "description": "When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character.",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RS485CTRL": {
+              "description": "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NMMEN": {
+                    "description": "NMM enable.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDIS": {
+                    "description": "Receiver enable.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "The receiver is enabled.",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "The receiver is disabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AADEN": {
+                    "description": "AAD enable.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Auto Address Detect (AAD) is disabled.",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Auto Address Detect (AAD) is enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 6,
+                    "size": 26
+                  },
+                  "DCTRL": {
+                    "description": "Direction control enable.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_AUTO_DIRECTI": {
+                            "description": "Disable Auto Direction Control.",
+                            "value": 0
+                          },
+                          "ENABLE_AUTO_DIRECTIO": {
+                            "description": "Enable Auto Direction Control.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OINV": {
+                    "description": "Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DIRLOW": {
+                            "description": "The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.",
+                            "value": 0
+                          },
+                          "DIRHIGH": {
+                            "description": "The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RS485ADRMATCH": {
+              "description": "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADRMATCH": {
+                    "description": "Contains the address match value.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "RS485DLY": {
+              "description": "RS-485/EIA-485 direction control delay.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DLY": {
+                    "description": "Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UART1": {
+        "description": "UART1  ",
+        "children": {
+          "registers": {
+            "RBR": {
+              "description": "DLAB =0 Receiver Buffer Register. Contains the next received character to be read.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RBR": {
+                    "description": "The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, the value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "THR": {
+              "description": "DLAB =0. Transmit Holding Register. The next character to be transmitted is written here.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "THR": {
+                    "description": "Writing to the UART1 Transmit Holding Register causes the data to be stored in the UART1 transmit FIFO. The byte will be sent when it reaches the bottom of the FIFO and the transmitter is available.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "DLL": {
+              "description": "DLAB =1. Divisor Latch LSB. Least significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DLLSB": {
+                    "description": "The UART1 Divisor Latch LSB Register, along with the U1DLM register, determines the baud rate of the UART1.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "DLM": {
+              "description": "DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DLMSB": {
+                    "description": "The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "DLAB =0. Interrupt Enable Register. Contains individual interrupt enable bits for the 7 potential UART1 interrupts.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RBRIE": {
+                    "description": "RBR Interrupt Enable. Enables the Receive Data Available interrupt for UART1. It also controls the Character Receive Time-out interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_RDA_INTE": {
+                            "description": "Disable the RDA interrupts.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_RDA_INTER": {
+                            "description": "Enable the RDA interrupts.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "THREIE": {
+                    "description": "THRE Interrupt Enable. Enables the THRE interrupt for UART1. The status of this interrupt can be read from LSR[5].",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_THRE_INT": {
+                            "description": "Disable the THRE interrupts.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_THRE_INTE": {
+                            "description": "Enable the THRE interrupts.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXIE": {
+                    "description": "RX Line Interrupt Enable. Enables the UART1 RX line status interrupts. The status of this interrupt can be read from LSR[4:1].",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_RX_LINE_": {
+                            "description": "Disable the RX line status interrupts.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_RX_LINE_S": {
+                            "description": "Enable the RX line status interrupts.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MSIE": {
+                    "description": "Modem Status Interrupt Enable. Enables the modem interrupt. The status of this interrupt can be read from MSR[3:0].",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_MODEM_IN": {
+                            "description": "Disable the modem interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_MODEM_INT": {
+                            "description": "Enable the modem interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 10,
+                    "size": 22
+                  },
+                  "CTSIE": {
+                    "description": "CTS Interrupt Enable. If auto-cts mode is enabled this bit enables/disables the modem status interrupt generation on a CTS1 signal transition. If auto-cts mode is disabled a CTS1 transition will generate an interrupt if Modem Status Interrupt Enable (IER[3]) is set. In normal operation a CTS1 signal transition will generate a Modem Status Interrupt unless the interrupt has been disabled by clearing the IER[3] bit in the IER register. In auto-cts mode a transition on the CTS1 bit will trigger an interrupt only if both the IER[3] and IER[7] bits are set.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_CTS_INTE": {
+                            "description": "Disable the CTS interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_CTS_INTER": {
+                            "description": "Enable the CTS interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABEOIE": {
+                    "description": "Enables the end of auto-baud interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_END_OF_AUTO_": {
+                            "description": "Disable end of auto-baud Interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE_END_OF_AUTO_B": {
+                            "description": "Enable end of auto-baud Interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABTOIE": {
+                    "description": "Enables the auto-baud time-out interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_AUTO_BAUD_TI": {
+                            "description": "Disable auto-baud time-out Interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE_AUTO_BAUD_TIM": {
+                            "description": "Enable auto-baud time-out Interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IIR": {
+              "description": "Interrupt ID Register. Identifies which interrupt(s) are pending.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INTSTATUS": {
+                    "description": "Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "AT_LEAST_ONE_INTERRU": {
+                            "description": "At least one interrupt is pending.",
+                            "value": 0
+                          },
+                          "NO_INTERRUPT_IS_PEND": {
+                            "description": "No interrupt is pending.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTID": {
+                    "description": "Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).",
+                    "offset": 1,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "RLS": {
+                            "description": "1   - Receive Line Status (RLS).",
+                            "value": 3
+                          },
+                          "RDA": {
+                            "description": "2a - Receive Data Available (RDA).",
+                            "value": 2
+                          },
+                          "CTI": {
+                            "description": "2b - Character Time-out Indicator (CTI).",
+                            "value": 6
+                          },
+                          "THRE": {
+                            "description": "3   - THRE Interrupt.",
+                            "value": 1
+                          },
+                          "MODEM": {
+                            "description": "4   - Modem Interrupt.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, the value read from a reserved bit is not defined.",
+                    "offset": 10,
+                    "size": 22
+                  },
+                  "FIFOENABLE": {
+                    "description": "Copies of FCR[0].",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "ABEOINT": {
+                    "description": "End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ABTOINT": {
+                    "description": "Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FCR": {
+              "description": "FIFO Control Register. Controls UART1 FIFO usage and modes.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "FIFOEN": {
+                    "description": "FIFO enable.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MUST_NOT_BE_USED_IN_": {
+                            "description": "Must not be used in the application.",
+                            "value": 0
+                          },
+                          "ACTIVE_HIGH_ENABLE_F": {
+                            "description": "Active high enable for both UART1 Rx and TX FIFOs and FCR[7:1] access. This bit must be set for proper UART1 operation. Any transition on this bit will automatically clear the UART1 FIFOs.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFIFORES": {
+                    "description": "RX FIFO Reset.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_IMPACT_ON_EITHER_": {
+                            "description": "No impact on either of UART1 FIFOs.",
+                            "value": 0
+                          },
+                          "WRITING_A_LOGIC_1_TO": {
+                            "description": "Writing a logic 1 to FCR[1] will clear all bytes in UART1 Rx FIFO, reset the pointer logic. This bit is self-clearing.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TXFIFORES": {
+                    "description": "TX FIFO Reset.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_IMPACT_ON_EITHER_": {
+                            "description": "No impact on either of UART1 FIFOs.",
+                            "value": 0
+                          },
+                          "WRITING_A_LOGIC_1_TO": {
+                            "description": "Writing a logic 1 to FCR[2] will clear all bytes in UART1 TX FIFO, reset the pointer logic. This bit is self-clearing.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DMAMODE": {
+                    "description": "DMA Mode Select. When the FIFO enable bit (bit 0 of this register) is set, this bit selects the DMA mode. See Section 36.6.6.1.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits.",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "RXTRIGLVL": {
+                    "description": "RX Trigger Level. These two bits determine how many receiver UART1 FIFO characters must be written before an interrupt is activated.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "TRIGGER_LEVEL_0_1_C": {
+                            "description": "Trigger level 0 (1 character or 0x01).",
+                            "value": 0
+                          },
+                          "TRIGGER_LEVEL_1_4_C": {
+                            "description": "Trigger level 1 (4 characters or 0x04).",
+                            "value": 1
+                          },
+                          "TRIGGER_LEVEL_2_8_C": {
+                            "description": "Trigger level 2 (8 characters or 0x08).",
+                            "value": 2
+                          },
+                          "TRIGGER_LEVEL_3_14_": {
+                            "description": "Trigger level 3 (14 characters or 0x0E).",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LCR": {
+              "description": "Line Control Register. Contains controls for frame formatting and break generation.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WLS": {
+                    "description": "Word Length Select.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "5_BIT_CHARACTER_LENG": {
+                            "description": "5-bit character length.",
+                            "value": 0
+                          },
+                          "6_BIT_CHARACTER_LENG": {
+                            "description": "6-bit character length.",
+                            "value": 1
+                          },
+                          "7_BIT_CHARACTER_LENG": {
+                            "description": "7-bit character length.",
+                            "value": 2
+                          },
+                          "8_BIT_CHARACTER_LENG": {
+                            "description": "8-bit character length.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SBS": {
+                    "description": "Stop Bit Select.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "1_STOP_BIT_": {
+                            "description": "1 stop bit.",
+                            "value": 0
+                          },
+                          "2_STOP_BITS_1_5_IF_": {
+                            "description": "2 stop bits (1.5 if LCR[1:0]=00).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PE": {
+                    "description": "Parity Enable.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_PARITY_GENER": {
+                            "description": "Disable parity generation and checking.",
+                            "value": 0
+                          },
+                          "ENABLE_PARITY_GENERA": {
+                            "description": "Enable parity generation and checking.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PS": {
+                    "description": "Parity Select.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "ODD_PARITY_NUMBER_O": {
+                            "description": "Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.",
+                            "value": 0
+                          },
+                          "EVEN_PARITY_NUMBER_": {
+                            "description": "Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.",
+                            "value": 1
+                          },
+                          "FORCED1STICK_PAR": {
+                            "description": "Forced 1 stick parity.",
+                            "value": 2
+                          },
+                          "FORCED0STICK_PAR": {
+                            "description": "Forced 0 stick parity.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BC": {
+                    "description": "Break Control.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_BREAK_TRANSM": {
+                            "description": "Disable break transmission.",
+                            "value": 0
+                          },
+                          "ENABLE_BREAK_TRANSMI": {
+                            "description": "Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DLAB": {
+                    "description": "Divisor Latch Access Bit (DLAB)",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_ACCESS_TO_DI": {
+                            "description": "Disable access to Divisor Latches.",
+                            "value": 0
+                          },
+                          "ENABLE_ACCESS_TO_DIV": {
+                            "description": "Enable access to Divisor Latches.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "MCR": {
+              "description": "Modem Control Register. Contains controls for flow control handshaking and loopback mode.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DTRCTRL": {
+                    "description": "DTR Control.  Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RTSCTRL": {
+                    "description": "RTS Control.  Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "LMS": {
+                    "description": "Loopback Mode Select.  The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_MODEM_LOOPBA": {
+                            "description": "Disable modem loopback mode.",
+                            "value": 0
+                          },
+                          "ENABLE_MODEM_LOOPBAC": {
+                            "description": "Enable modem loopback mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RTSEN": {
+                    "description": "RTS enable.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_AUTO_RTS_FLO": {
+                            "description": "Disable auto-rts flow control.",
+                            "value": 0
+                          },
+                          "ENABLE_AUTO_RTS_FLOW": {
+                            "description": "Enable auto-rts flow control.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CTSEN": {
+                    "description": "CTS enable.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_AUTO_CTS_FLO": {
+                            "description": "Disable auto-cts flow control.",
+                            "value": 0
+                          },
+                          "ENABLE_AUTO_CTS_FLOW": {
+                            "description": "Enable auto-cts flow control.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LSR": {
+              "description": "Line Status Register. Contains flags for transmit and receive status, including line errors.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 96,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RDR": {
+                    "description": "Receiver Data Ready.  LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "EMPTY": {
+                            "description": "The UART1 receiver FIFO is empty.",
+                            "value": 0
+                          },
+                          "NOTEMPTY": {
+                            "description": "The UART1 receiver FIFO is not empty.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OE": {
+                    "description": "Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "Overrun error status is inactive.",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Overrun error status is active.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PE": {
+                    "description": "Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "Parity error status is inactive.",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Parity error status is active.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FE": {
+                    "description": "Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "Framing error status is inactive.",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Framing error status is active.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BI": {
+                    "description": "Break Interrupt.  When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "Break interrupt status is inactive.",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Break interrupt status is active.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "THRE": {
+                    "description": "Transmitter Holding Register Empty.  THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "VALID": {
+                            "description": "THR contains valid data.",
+                            "value": 0
+                          },
+                          "THR_IS_EMPTY_": {
+                            "description": "THR is empty.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TEMT": {
+                    "description": "Transmitter Empty.  TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "VALID": {
+                            "description": "THR and/or the TSR contains valid data.",
+                            "value": 0
+                          },
+                          "EMPTY": {
+                            "description": "THR and the TSR are empty.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXFE": {
+                    "description": "Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NOERROR": {
+                            "description": "RBR contains no UART1 RX errors or FCR[0]=0.",
+                            "value": 0
+                          },
+                          "ERRORS": {
+                            "description": "UART1 RBR contains at least one UART1 RX error.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, the value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "MSR": {
+              "description": "Modem Status Register. Contains handshake signal status flags.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DCTS": {
+                    "description": "Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_CHANGE_DETECTED_O": {
+                            "description": "No change detected on modem input, CTS.",
+                            "value": 0
+                          },
+                          "STATE_CHANGE_DETECTE": {
+                            "description": "State change detected on modem input, CTS.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DDSR": {
+                    "description": "Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_CHANGE_DETECTED_O": {
+                            "description": "No change detected on modem input, DSR.",
+                            "value": 0
+                          },
+                          "STATE_CHANGE_DETECTE": {
+                            "description": "State change detected on modem input, DSR.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TERI": {
+                    "description": "Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_CHANGE_DETECTED_O": {
+                            "description": "No change detected on modem input, RI.",
+                            "value": 0
+                          },
+                          "LOW_TO_HIGH_TRANSITI": {
+                            "description": "Low-to-high transition detected on RI.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DDCD": {
+                    "description": "Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_CHANGE_DETECTED_O": {
+                            "description": "No change detected on modem input, DCD.",
+                            "value": 0
+                          },
+                          "STATE_CHANGE_DETECTE": {
+                            "description": "State change detected on modem input, DCD.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CTS": {
+                    "description": "Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DSR": {
+                    "description": "Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RI": {
+                    "description": "Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DCD": {
+                    "description": "Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, the value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "SCR": {
+              "description": "Scratch Pad Register. 8-bit temporary storage for software.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "Pad": {
+                    "description": "A readable, writable byte.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "ACR": {
+              "description": "Auto-baud Control Register. Contains controls for the auto-baud feature.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "START": {
+                    "description": "Auto-baud start bit. This bit is automatically cleared after auto-baud completion.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "STOP": {
+                            "description": "Auto-baud stop (auto-baud is not running).",
+                            "value": 0
+                          },
+                          "START": {
+                            "description": "Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MODE": {
+                    "description": "Auto-baud mode select bit.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MODE_0_": {
+                            "description": "Mode 0.",
+                            "value": 0
+                          },
+                          "MODE_1_": {
+                            "description": "Mode 1.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AUTORESTART": {
+                    "description": "Auto-baud restart bit.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_RESTART": {
+                            "description": "No restart",
+                            "value": 0
+                          },
+                          "RESTART_IN_CASE_OF_T": {
+                            "description": "Restart in case of time-out (counter restarts at next UART1 Rx falling edge)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 10,
+                    "size": 22
+                  },
+                  "ABEOINTCLR": {
+                    "description": "End of auto-baud interrupt clear bit (write-only).",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "WRITING_A_0_HAS_NO_I": {
+                            "description": "Writing a 0 has no impact.",
+                            "value": 0
+                          },
+                          "WRITING_A_1_WILL_CLE": {
+                            "description": "Writing a 1 will clear the corresponding interrupt in the IIR.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABTOINTCLR": {
+                    "description": "Auto-baud time-out interrupt clear bit (write-only).",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "WRITING_A_0_HAS_NO_I": {
+                            "description": "Writing a 0 has no impact.",
+                            "value": 0
+                          },
+                          "WRITING_A_1_WILL_CLE": {
+                            "description": "Writing a 1 will clear the corresponding interrupt in the IIR.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FDR": {
+              "description": "Fractional Divider Register. Generates a clock input for the baud rate divider.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIVADDVAL": {
+                    "description": "Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "MULVAL": {
+                    "description": "Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not.",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "TER": {
+              "description": "Transmit Enable Register. Turns off UART transmitter for use with software flow control.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "TXEN": {
+                    "description": "When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RS485CTRL": {
+              "description": "RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NMMEN": {
+                    "description": "RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "ENABLED_IN_THIS_MOD": {
+                            "description": "Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RXDIS": {
+                    "description": "Receive enable.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED_": {
+                            "description": "Enabled.",
+                            "value": 0
+                          },
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AADEN": {
+                    "description": "Auto Address Detect (AAD) enable.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "ENABLED_": {
+                            "description": "Enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SEL": {
+                    "description": "Direction control.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RTS_IF_DIRECTION_CO": {
+                            "description": "RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.",
+                            "value": 0
+                          },
+                          "DTR_IF_DIRECTION_CO": {
+                            "description": "DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DCTRL": {
+                    "description": "Direction control enable.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_AUTO_DIRECTI": {
+                            "description": "Disable Auto Direction Control.",
+                            "value": 0
+                          },
+                          "ENABLE_AUTO_DIRECTIO": {
+                            "description": "Enable Auto Direction Control.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OINV": {
+                    "description": "Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LOW_THE_DIRECTION_C": {
+                            "description": "LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.",
+                            "value": 0
+                          },
+                          "HIGH_THE_DIRECTION_": {
+                            "description": "HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "RS485ADRMATCH": {
+              "description": "RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADRMATCH": {
+                    "description": "Contains the address match value.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "RS485DLY": {
+              "description": "RS-485/EIA-485 direction control delay.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DLY": {
+                    "description": "Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PWM1": {
+        "description": "Pulse Width Modulators (PWM1) ",
+        "children": {
+          "registers": {
+            "IR": {
+              "description": "Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWMMR0INT": {
+                    "description": "Interrupt flag for PWM match channel 0.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PWMMR1INT": {
+                    "description": "Interrupt flag for PWM match channel 1.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PWMMR2INT": {
+                    "description": "Interrupt flag for PWM match channel 2.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PWMMR3INT": {
+                    "description": "Interrupt flag for PWM match channel 3.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PWMCAP0INT": {
+                    "description": "Interrupt flag for capture input 0",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PWMCAP1INT": {
+                    "description": "Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR).",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 11,
+                    "size": 21
+                  },
+                  "PWMMR4INT": {
+                    "description": "Interrupt flag for PWM match channel 4.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PWMMR5INT": {
+                    "description": "Interrupt flag for PWM match channel 5.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PWMMR6INT": {
+                    "description": "Interrupt flag for PWM match channel 6.",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TCR": {
+              "description": "Timer Control Register. The TCR is used to control the Timer Counter functions.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CE": {
+                    "description": "Counter Enable",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_PWM_TIMER_COUNTE": {
+                            "description": "The PWM Timer Counter and PWM Prescale Counter are enabled for counting.",
+                            "value": 1
+                          },
+                          "THE_COUNTERS_ARE_DIS": {
+                            "description": "The counters are disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CR": {
+                    "description": "Counter Reset",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_PWM_TIMER_COUNTE": {
+                            "description": "The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero.",
+                            "value": 1
+                          },
+                          "CLEAR_RESET_": {
+                            "description": "Clear reset.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 5,
+                    "size": 27
+                  },
+                  "PWMEN": {
+                    "description": "PWM Enable",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "PWM_MODE_IS_ENABLED_": {
+                            "description": "PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective.",
+                            "value": 1
+                          },
+                          "TIMER_MODE_IS_ENABLE": {
+                            "description": "Timer mode is enabled (counter resets to 0).",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MDIS": {
+                    "description": "Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141.  This bit has no function in the Slave PWM (PWM1).",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MASTER_USE_PWM0_IS_": {
+                            "description": "Master use. PWM0 is the master, and both PWMs are enabled for counting.",
+                            "value": 1
+                          },
+                          "INDIVIDUAL_USE_THE_": {
+                            "description": "Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TC": {
+              "description": "Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TC": {
+                    "description": "Timer counter value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PR": {
+              "description": "Prescale Register. Determines how often the PWM counter is incremented.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PM": {
+                    "description": "Prescale counter maximum value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PC": {
+              "description": "Prescale Counter. Prescaler for the main PWM counter.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PC": {
+                    "description": "Prescale counter value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MCR": {
+              "description": "Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWMMR0I": {
+                    "description": "Interrupt PWM0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ON_PWMMR0": {
+                            "description": "Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR0R": {
+                    "description": "Reset PWM0",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "RESET_ON_PWMMR0_THE": {
+                            "description": "Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR0S": {
+                    "description": "Stop PWM0",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "STOP_ON_PWMMR0_THE_": {
+                            "description": "Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR1I": {
+                    "description": "Interrupt PWM1",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ON_PWMMR1": {
+                            "description": "Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR1R": {
+                    "description": "Reset PWM1",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "RESET_ON_PWMMR1_THE": {
+                            "description": "Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR1S": {
+                    "description": "Stop PWM1",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "STOP_ON_PWMMR1_THE_": {
+                            "description": "Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR2I": {
+                    "description": "Interrupt PWM0",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ON_PWMMR2": {
+                            "description": "Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR2R": {
+                    "description": "Reset PWM0",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "RESET_ON_PWMMR2_THE": {
+                            "description": "Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR2S": {
+                    "description": "Stop PWM0",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "STOP_ON_PWMMR2_THE_": {
+                            "description": "Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR3I": {
+                    "description": "Interrupt PWM3",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ON_PWMMR3": {
+                            "description": "Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR3R": {
+                    "description": "Reset PWM3",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "RESET_ON_PWMMR3_THE": {
+                            "description": "Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR3S": {
+                    "description": "Stop PWM0",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "STOP_ON_PWMMR3_THE_": {
+                            "description": "Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR4I": {
+                    "description": "Interrupt PWM4",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ON_PWMMR4": {
+                            "description": "Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR4R": {
+                    "description": "Reset PWM4",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "RESET_ON_PWMMR4_THE": {
+                            "description": "Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR4S": {
+                    "description": "Stop PWM4",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "STOP_ON_PWMMR4_THE_": {
+                            "description": "Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR5I": {
+                    "description": "Interrupt PWM5",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ON_PWMMR5": {
+                            "description": "Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR5R": {
+                    "description": "Reset PWM5",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "RESET_ON_PWMMR5_THE": {
+                            "description": "Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR5S": {
+                    "description": "Stop PWM5",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "STOP_ON_PWMMR5_THE_": {
+                            "description": "Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR6I": {
+                    "description": "Interrupt PWM6",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ON_PWMMR6": {
+                            "description": "Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR6R": {
+                    "description": "Reset PWM6",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "RESET_ON_PWMMR6_THE": {
+                            "description": "Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMMR6S": {
+                    "description": "Stop PWM6",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Disabled",
+                            "value": 0
+                          },
+                          "STOP_ON_PWMMR6_THE_": {
+                            "description": "Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 21,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CAP0_R": {
+                    "description": "Capture on PWMn_CAP0 rising edge",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_THIS_FEATU": {
+                            "description": "Disabled. This feature is disabled.",
+                            "value": 0
+                          },
+                          "RISING_EDGE_A_SYNCH": {
+                            "description": "Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CAP0_F": {
+                    "description": "Capture on PWMn_CAP0 falling edge",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_THIS_FEATU": {
+                            "description": "Disabled. This feature is disabled.",
+                            "value": 0
+                          },
+                          "FALLING_EDGE_A_SYNC": {
+                            "description": "Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CAP0_I": {
+                    "description": "Interrupt on PWMn_CAP0 event",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_THIS_FEATU": {
+                            "description": "Disabled. This feature is disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_A_CR0_LOA": {
+                            "description": "Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CAP1_R": {
+                    "description": "Capture on PWMn_CAP1 rising edge. Reserved for PWM0.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_THIS_FEATU": {
+                            "description": "Disabled. This feature is disabled.",
+                            "value": 0
+                          },
+                          "RISING_EDGE_A_SYNCH": {
+                            "description": "Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CAP1_F": {
+                    "description": "Capture on PWMn_CAP1 falling edge. Reserved for PWM0.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_THIS_FEATU": {
+                            "description": "Disabled. This feature is disabled.",
+                            "value": 0
+                          },
+                          "FALLING_EDGE_A_SYNC": {
+                            "description": "Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CAP1_I": {
+                    "description": "Interrupt on PWMn_CAP1 event. Reserved for PWM0.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_THIS_FEATU": {
+                            "description": "Disabled. This feature is disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_A_CR1_LOA": {
+                            "description": "Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "PCR": {
+              "description": "PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Unused, always zero.",
+                    "offset": 15,
+                    "size": 17
+                  },
+                  "PWMSEL2": {
+                    "description": "PWM[2] output single/double edge mode control.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "SINGLE_EDGE_CONTROLL": {
+                            "description": "Single edge controlled mode is selected.",
+                            "value": 0
+                          },
+                          "DOUBLE_EDGE_CONTROLL": {
+                            "description": "Double edge controlled mode is selected.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMSEL3": {
+                    "description": "PWM[3] output edge control.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "SINGLE_EDGE_CONTROLL": {
+                            "description": "Single edge controlled mode is selected.",
+                            "value": 0
+                          },
+                          "DOUBLE_EDGE_CONTROLL": {
+                            "description": "Double edge controlled mode is selected.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMSEL4": {
+                    "description": "PWM[4] output edge control.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "SINGLE_EDGE_CONTROLL": {
+                            "description": "Single edge controlled mode is selected.",
+                            "value": 0
+                          },
+                          "DOUBLE_EDGE_CONTROLL": {
+                            "description": "Double edge controlled mode is selected.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMSEL5": {
+                    "description": "PWM[5] output edge control.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "SINGLE_EDGE_CONTROLL": {
+                            "description": "Single edge controlled mode is selected.",
+                            "value": 0
+                          },
+                          "DOUBLE_EDGE_CONTROLL": {
+                            "description": "Double edge controlled mode is selected.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMSEL6": {
+                    "description": "PWM[6] output edge control.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "SINGLE_EDGE_CONTROLL": {
+                            "description": "Single edge controlled mode is selected.",
+                            "value": 0
+                          },
+                          "DOUBLE_EDGE_CONTROLL": {
+                            "description": "Double edge controlled mode is selected.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMENA1": {
+                    "description": "PWM[1] output enable control.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_PWM_OUTPUT_IS_DI": {
+                            "description": "The PWM output is disabled.",
+                            "value": 0
+                          },
+                          "THE_PWM_OUTPUT_IS_EN": {
+                            "description": "The PWM output is enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMENA2": {
+                    "description": "PWM[2] output enable control.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_PWM_OUTPUT_IS_DI": {
+                            "description": "The PWM output is disabled.",
+                            "value": 0
+                          },
+                          "THE_PWM_OUTPUT_IS_EN": {
+                            "description": "The PWM output is enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMENA3": {
+                    "description": "PWM[3] output enable control.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_PWM_OUTPUT_IS_DI": {
+                            "description": "The PWM output is disabled.",
+                            "value": 0
+                          },
+                          "THE_PWM_OUTPUT_IS_EN": {
+                            "description": "The PWM output is enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMENA4": {
+                    "description": "PWM[4] output enable control.",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_PWM_OUTPUT_IS_DI": {
+                            "description": "The PWM output is disabled.",
+                            "value": 0
+                          },
+                          "THE_PWM_OUTPUT_IS_EN": {
+                            "description": "The PWM output is enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMENA5": {
+                    "description": "PWM[5] output enable control.",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_PWM_OUTPUT_IS_DI": {
+                            "description": "The PWM output is disabled.",
+                            "value": 0
+                          },
+                          "THE_PWM_OUTPUT_IS_EN": {
+                            "description": "The PWM output is enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PWMENA6": {
+                    "description": "PWM[6] output enable control. See PWMENA1 for details.",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_PWM_OUTPUT_IS_DI": {
+                            "description": "The PWM output is disabled.",
+                            "value": 0
+                          },
+                          "THE_PWM_OUTPUT_IS_EN": {
+                            "description": "The PWM output is enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "LER": {
+              "description": "Load Enable Register. Enables use of updated PWM match values.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAT0LATCHEN": {
+                    "description": "Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MAT1LATCHEN": {
+                    "description": "Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MAT2LATCHEN": {
+                    "description": "Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MAT3LATCHEN": {
+                    "description": "Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MAT4LATCHEN": {
+                    "description": "Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MAT5LATCHEN": {
+                    "description": "Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MAT6LATCHEN": {
+                    "description": "Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 7,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "CTCR": {
+              "description": "Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MOD": {
+                    "description": "Counter/  Timer Mode",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER_MODE_THE_TC_I": {
+                            "description": "Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register.",
+                            "value": 0
+                          },
+                          "RISING_EDGE_COUNTER_": {
+                            "description": "Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2.",
+                            "value": 1
+                          },
+                          "FALLING_EDGE_COUNTER": {
+                            "description": "Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2.",
+                            "value": 2
+                          },
+                          "DUAL_EDGE_COUNTER_MO": {
+                            "description": "Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CIS": {
+                    "description": "Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "FOR_PWM0_00_EQ_PWM0_": {
+                            "description": "For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2C0": {
+        "description": "I2C bus interface",
+        "children": {
+          "registers": {
+            "CONSET": {
+              "description": "I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 7,
+                    "size": 25
+                  },
+                  "AA": {
+                    "description": "Assert acknowledge flag.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SI": {
+                    "description": "I2C interrupt flag.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "STO": {
+                    "description": "STOP flag.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STA": {
+                    "description": "START flag.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "I2EN": {
+                    "description": "I2C interface enable.",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "STAT": {
+              "description": "I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 248,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "Status": {
+                    "description": "These bits give the actual status information about the I 2C interface.",
+                    "offset": 3,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DAT": {
+              "description": "I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "Data": {
+                    "description": "This register holds data values that have been received or are to be transmitted.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "ADR0": {
+              "description": "I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GC": {
+                    "description": "General Call enable bit.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "Address": {
+                    "description": "The I2C device address for slave mode.",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "SCLH": {
+              "description": "SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCLH": {
+                    "description": "Count for SCL HIGH time period selection.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SCLL": {
+              "description": "SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCLL": {
+                    "description": "Count for SCL low time period selection.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CONCLR": {
+              "description": "I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "AAC": {
+                    "description": "Assert acknowledge Clear bit.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SIC": {
+                    "description": "I2C interrupt Clear bit.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "STAC": {
+                    "description": "START flag Clear bit.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "I2ENC": {
+                    "description": "I2C interface Disable bit.",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MMCTRL": {
+              "description": "Monitor mode control register.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MM_ENA": {
+                    "description": "Monitor mode enable.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MONITOR_MODE_DISABLE": {
+                            "description": "Monitor mode disabled.",
+                            "value": 0
+                          },
+                          "THE_I_2C_MODULE_WILL": {
+                            "description": "The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENA_SCL": {
+                    "description": "SCL output enable.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "WHEN_THIS_BIT_IS_CLE": {
+                            "description": "When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.",
+                            "value": 0
+                          },
+                          "WHEN_THIS_BIT_IS_SET": {
+                            "description": "When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MATCH_ALL": {
+                    "description": "Select interrupt register match.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "WHEN_THIS_BIT_IS_CLE": {
+                            "description": "When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above.   That is, the module will respond as a normal slave as far as address-recognition is concerned.",
+                            "value": 0
+                          },
+                          "WHEN_THIS_BIT_IS_SET": {
+                            "description": "When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from reserved bits is not defined.",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            },
+            "DATA_BUFFER": {
+              "description": "Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "Data": {
+                    "description": "This register holds contents of the 8 MSBs of the DAT shift register.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI": {
+        "description": "SPI ",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "SPI Control Register. This register controls the operation of the SPI.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 12,
+                    "size": 20
+                  },
+                  "BITENABLE": {
+                    "description": "The SPI controller sends and receives 8 bits of data per transfer.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_SPI_CONTROLLER_S": {
+                            "description": "The SPI controller sends and receives the number of bits selected by bits 11:8.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPHA": {
+                    "description": "Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "FIRST_EDGE": {
+                            "description": "Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal.",
+                            "value": 0
+                          },
+                          "SECOND_EDGE": {
+                            "description": "Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPOL": {
+                    "description": "Clock polarity control.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "SCK_IS_ACTIVE_HIGH_": {
+                            "description": "SCK is active high.",
+                            "value": 0
+                          },
+                          "SCK_IS_ACTIVE_LOW_": {
+                            "description": "SCK is active low.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MSTR": {
+                    "description": "Master mode select.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "SLAVE": {
+                            "description": "The SPI operates in Slave mode.",
+                            "value": 0
+                          },
+                          "MASTER": {
+                            "description": "The SPI operates in Master mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LSBF": {
+                    "description": "LSB First controls which direction each byte is shifted when transferred.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MSB": {
+                            "description": "SPI data is transferred MSB (bit 7) first.",
+                            "value": 0
+                          },
+                          "LSB": {
+                            "description": "SPI data is transferred LSB (bit 0) first.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SPIE": {
+                    "description": "Serial peripheral interrupt enable.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTBLOCK": {
+                            "description": "SPI interrupts are inhibited.",
+                            "value": 0
+                          },
+                          "HWINT": {
+                            "description": "A hardware interrupt is generated each time the SPIF or MODF bits are activated.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BITS": {
+                    "description": "When bit 2 of this register is 1, this field controls the number of bits per transfer:",
+                    "offset": 8,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "8_BITS_PER_TRANSFER": {
+                            "description": "8 bits per transfer",
+                            "value": 8
+                          },
+                          "9_BITS_PER_TRANSFER": {
+                            "description": "9 bits per transfer",
+                            "value": 9
+                          },
+                          "10_BITS_PER_TRANSFER": {
+                            "description": "10 bits per transfer",
+                            "value": 10
+                          },
+                          "11_BITS_PER_TRANSFER": {
+                            "description": "11 bits per transfer",
+                            "value": 11
+                          },
+                          "12_BITS_PER_TRANSFER": {
+                            "description": "12 bits per transfer",
+                            "value": 12
+                          },
+                          "13_BITS_PER_TRANSFER": {
+                            "description": "13 bits per transfer",
+                            "value": 13
+                          },
+                          "14_BITS_PER_TRANSFER": {
+                            "description": "14 bits per transfer",
+                            "value": 14
+                          },
+                          "15_BITS_PER_TRANSFER": {
+                            "description": "15 bits per transfer",
+                            "value": 15
+                          },
+                          "16_BITS_PER_TRANSFER": {
+                            "description": "16 bits per transfer",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "SPI Status Register. This register shows the status of the SPI.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "ABRT": {
+                    "description": "Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MODF": {
+                    "description": "Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ROVR": {
+                    "description": "Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WCOL": {
+                    "description": "Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SPIF": {
+                    "description": "SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register.",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATALOW": {
+                    "description": "SPI Bi-directional data port.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "DATAHIGH": {
+                    "description": "If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "SPI Clock Counter Register. This register controls the frequency of a master's SCK0.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COUNTER": {
+                    "description": "SPI0 Clock counter setting.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "INT": {
+              "description": "SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPIF": {
+                    "description": "SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RTC": {
+        "description": " Real Time Clock (RTC)  ",
+        "children": {
+          "registers": {
+            "ILR": {
+              "description": "Interrupt Location Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTCCIF": {
+                    "description": "When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RTCALF": {
+                    "description": "When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 21,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "Clock Control Register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "CLKEN": {
+                    "description": "Clock Enable.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_TIME_COUNTERS_AR": {
+                            "description": "The time counters are disabled so that they may be initialized.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CTCRST": {
+                    "description": "CTC Reset.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software.",
+                            "value": 1
+                          },
+                          "NO_EFFECT_": {
+                            "description": "No effect.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 5,
+                    "size": 27
+                  },
+                  "CCALEN": {
+                    "description": "Calibration counter enable.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_CALIBRATION_COUN": {
+                            "description": "The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and  Section 30.6.5.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CIIR": {
+              "description": "Counter Increment Interrupt Register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IMSEC": {
+                    "description": "When 1, an increment of the Second value generates an interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IMMIN": {
+                    "description": "When 1, an increment of the Minute value generates an interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IMHOUR": {
+                    "description": "When 1, an increment of the Hour value generates an interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IMDOM": {
+                    "description": "When 1, an increment of the Day of Month value generates an interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IMDOW": {
+                    "description": "When 1, an increment of the Day of Week value generates an interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IMDOY": {
+                    "description": "When 1, an increment of the Day of Year value generates an interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IMMON": {
+                    "description": "When 1, an increment of the Month value generates an interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IMYEAR": {
+                    "description": "When 1, an increment of the Year value generates an interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "AMR": {
+              "description": "Alarm Mask Register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AMRSEC": {
+                    "description": "When 1, the Second value is not compared for the alarm.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "AMRMIN": {
+                    "description": "When 1, the Minutes value is not compared for the alarm.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AMRHOUR": {
+                    "description": "When 1, the Hour value is not compared for the alarm.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "AMRDOM": {
+                    "description": "When 1, the Day of Month value is not compared for the alarm.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "AMRDOW": {
+                    "description": "When 1, the Day of Week value is not compared for the alarm.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "AMRDOY": {
+                    "description": "When 1, the Day of Year value is not compared for the alarm.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "AMRMON": {
+                    "description": "When 1, the Month value is not compared for the alarm.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AMRYEAR": {
+                    "description": "When 1, the Year value is not compared for the alarm.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "CTIME0": {
+              "description": "Consolidated Time Register 0",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SECONDS": {
+                    "description": "Seconds value in the range of 0 to 59",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 27,
+                    "size": 5
+                  },
+                  "MINUTES": {
+                    "description": "Minutes value in the range of 0 to 59",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "HOURS": {
+                    "description": "Hours value in the range of 0 to 23",
+                    "offset": 16,
+                    "size": 5
+                  },
+                  "DOW": {
+                    "description": "Day of week value in the range of 0 to 6",
+                    "offset": 24,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "CTIME1": {
+              "description": "Consolidated Time Register 1",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DOM": {
+                    "description": "Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "MONTH": {
+                    "description": "Month value in the range of 1 to 12.",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "YEAR": {
+                    "description": "Year value in the range of 0 to 4095.",
+                    "offset": 16,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "CTIME2": {
+              "description": "Consolidated Time Register 2",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DOY": {
+                    "description": "Day of year value in the range of 1 to 365 (366 for leap years).",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 12,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "SEC": {
+              "description": "Seconds Counter",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "SECONDS": {
+                    "description": "Seconds value in the range of 0 to 59",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "MIN": {
+              "description": "Minutes Register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "MINUTES": {
+                    "description": "Minutes value in the range of 0 to 59",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "HRS": {
+              "description": "Hours Register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "HOURS": {
+                    "description": "Hours value in the range of 0 to 23",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "DOM": {
+              "description": "Day of Month Register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "DOM": {
+                    "description": "Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "DOW": {
+              "description": "Day of Week Register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "DOW": {
+                    "description": "Day of week value in the range of 0 to 6.",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            },
+            "DOY": {
+              "description": "Day of Year Register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "DOY": {
+                    "description": "Day of year value in the range of 1 to 365 (366 for leap years).",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 9,
+                    "size": 23
+                  }
+                }
+              }
+            },
+            "MONTH": {
+              "description": "Months Register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "MONTH": {
+                    "description": "Month value in the range of 1 to 12.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "YEAR": {
+              "description": "Years Register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "YEAR": {
+                    "description": "Year value in the range of 0 to 4095.",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 12,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "CALIBRATION": {
+              "description": "Calibration Value Register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "CALVAL": {
+                    "description": "If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0.",
+                    "offset": 0,
+                    "size": 17
+                  },
+                  "CALDIR": {
+                    "description": "Calibration direction",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "BACKWARD_CALIBRATION": {
+                            "description": "Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second.",
+                            "value": 1
+                          },
+                          "FORWARD_CALIBRATION_": {
+                            "description": "Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "RTC_AUX": {
+              "description": "RTC Auxiliary control register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 7,
+                    "size": 25
+                  },
+                  "RTC_OSCF": {
+                    "description": "RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RTC_PDOUT": {
+                    "description": "When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode.",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RTC_AUXEN": {
+              "description": "RTC Auxiliary Enable register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 5,
+                    "size": 27
+                  },
+                  "RTC_OSCFEN": {
+                    "description": "Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5.",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ASEC": {
+              "description": "Alarm value for Seconds",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "SECONDS": {
+                    "description": "Seconds value in the range of 0 to 59",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "AMIN": {
+              "description": "Alarm value for Minutes",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "MINUTES": {
+                    "description": "Minutes value in the range of 0 to 59",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "AHRS": {
+              "description": "Alarm value for Hours",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "HOURS": {
+                    "description": "Hours value in the range of 0 to 23",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "ADOM": {
+              "description": "Alarm value for Day of Month",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "DOM": {
+                    "description": "Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "ADOW": {
+              "description": "Alarm value for Day of Week",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "DOW": {
+                    "description": "Day of week value in the range of 0 to 6.",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            },
+            "ADOY": {
+              "description": "Alarm value for Day of Year",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "DOY": {
+                    "description": "Day of year value in the range of 1 to 365 (366 for leap years).",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 9,
+                    "size": 23
+                  }
+                }
+              }
+            },
+            "AMON": {
+              "description": "Alarm value for Months",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "MONTH": {
+                    "description": "Month value in the range of 1 to 12.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "AYRS": {
+              "description": "Alarm value for Year",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "YEAR": {
+                    "description": "Year value in the range of 0 to 4095.",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 12,
+                    "size": 20
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOINT": {
+        "description": "GPIO",
+        "children": {
+          "registers": {
+            "STATUS": {
+              "description": "GPIO overall Interrupt Status.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "P0INT": {
+                    "description": "Port 0 GPIO interrupt pending.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_PENDING_INTERRUPT": {
+                            "description": "No pending interrupts on Port 0.",
+                            "value": 0
+                          },
+                          "AT_LEAST_ONE_PENDING": {
+                            "description": "At least one pending interrupt on Port 0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 2,
+                    "size": 30
+                  },
+                  "P2INT": {
+                    "description": "Port 2 GPIO interrupt pending.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_PENDING_INTERRUPT": {
+                            "description": "No pending interrupts on Port 2.",
+                            "value": 0
+                          },
+                          "AT_LEAST_ONE_PENDING": {
+                            "description": "At least one pending interrupt on Port 2.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "STATR0": {
+              "description": "GPIO Interrupt Status for Rising edge for Port 0.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "P0_0REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "P0_1REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "P0_2REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "P0_3REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "P0_4REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "P0_5REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "P0_6REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "P0_7REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "P0_8REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "P0_9REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "P0_10REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "P0_11REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "P0_12REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "P0_13REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "P0_14REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "P0_15REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "P0_16REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "P0_17REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "P0_18REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "P0_19REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "P0_20REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "P0_21REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "P0_22REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "P0_23REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "P0_24REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "P0_25REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "P0_26REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "P0_27REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "P0_28REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "P0_29REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "P0_30REI": {
+                    "description": "Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "STATF0": {
+              "description": "GPIO Interrupt Status for Falling edge for Port 0.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "P0_0FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "P0_1FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "P0_2FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "P0_3FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "P0_4FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "P0_5FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "P0_6FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "P0_7FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "P0_8FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "P0_9FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "P0_10FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "P0_11FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "P0_12FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "P0_13FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "P0_14FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "P0_15FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "P0_16FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "P0_17FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "P0_18FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "P0_19FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "P0_20FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "P0_21FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "P0_22FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "P0_23FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "P0_24FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "P0_25FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "P0_26FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "P0_27FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "P0_28FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "P0_29FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "P0_30FEI": {
+                    "description": "Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLR0": {
+              "description": "GPIO Interrupt Clear.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "P0_0CI": {
+                    "description": "Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "P0_1CI": {
+                    "description": "Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "P0_2CI": {
+                    "description": "Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "P0_3CI": {
+                    "description": "Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "P0_4CI": {
+                    "description": "Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "P0_5CI": {
+                    "description": "Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "P0_6CI": {
+                    "description": "Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "P0_7CI": {
+                    "description": "Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "P0_8CI": {
+                    "description": "Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "P0_9CI": {
+                    "description": "Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "P0_10CI": {
+                    "description": "Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "P0_11CI": {
+                    "description": "Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "P0_12CI": {
+                    "description": "Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "P0_13CI": {
+                    "description": "Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "P0_14CI": {
+                    "description": "Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "P0_15CI": {
+                    "description": "Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "P0_16CI": {
+                    "description": "Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "P0_17CI": {
+                    "description": "Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "P0_18CI": {
+                    "description": "Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "P0_19CI": {
+                    "description": "Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "P0_20CI": {
+                    "description": "Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "P0_21CI": {
+                    "description": "Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "P0_22CI": {
+                    "description": "Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "P0_23CI": {
+                    "description": "Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "P0_24CI": {
+                    "description": "Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "P0_25CI": {
+                    "description": "Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "P0_26CI": {
+                    "description": "Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "P0_27CI": {
+                    "description": "Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "P0_28CI": {
+                    "description": "Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "P0_29CI": {
+                    "description": "Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "P0_30CI": {
+                    "description": "Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ENR0": {
+              "description": "GPIO Interrupt Enable for Rising edge for Port 0.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P0_0ER": {
+                    "description": "Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "P0_1ER": {
+                    "description": "Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "P0_2ER": {
+                    "description": "Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "P0_3ER": {
+                    "description": "Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "P0_4ER": {
+                    "description": "Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "P0_5ER": {
+                    "description": "Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "P0_6ER": {
+                    "description": "Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "P0_7ER": {
+                    "description": "Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "P0_8ER": {
+                    "description": "Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "P0_9ER": {
+                    "description": "Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "P0_10ER": {
+                    "description": "Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "P0_11ER": {
+                    "description": "Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "P0_12ER": {
+                    "description": "Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "P0_13ER": {
+                    "description": "Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "P0_14ER": {
+                    "description": "Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "P0_15ER": {
+                    "description": "Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "P0_16ER": {
+                    "description": "Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "P0_17ER": {
+                    "description": "Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "P0_18ER": {
+                    "description": "Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "P0_19ER": {
+                    "description": "Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "P0_20ER": {
+                    "description": "Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "P0_21ER": {
+                    "description": "Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "P0_22ER": {
+                    "description": "Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "P0_23ER": {
+                    "description": "Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "P0_24ER": {
+                    "description": "Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "P0_25ER": {
+                    "description": "Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "P0_26ER": {
+                    "description": "Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "P0_27ER": {
+                    "description": "Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "P0_28ER": {
+                    "description": "Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "P0_29ER": {
+                    "description": "Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "P0_30ER": {
+                    "description": "Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ENF0": {
+              "description": "GPIO Interrupt Enable for Falling edge for Port 0.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P0_0EF": {
+                    "description": "Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "P0_1EF": {
+                    "description": "Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "P0_2EF": {
+                    "description": "Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "P0_3EF": {
+                    "description": "Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "P0_4EF": {
+                    "description": "Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "P0_5EF": {
+                    "description": "Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "P0_6EF": {
+                    "description": "Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "P0_7EF": {
+                    "description": "Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "P0_8EF": {
+                    "description": "Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "P0_9EF": {
+                    "description": "Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "P0_10EF": {
+                    "description": "Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "P0_11EF": {
+                    "description": "Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "P0_12EF": {
+                    "description": "Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "P0_13EF": {
+                    "description": "Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "P0_14EF": {
+                    "description": "Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "P0_15EF": {
+                    "description": "Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "P0_16EF": {
+                    "description": "Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "P0_17EF": {
+                    "description": "Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "P0_18EF": {
+                    "description": "Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "P0_19EF": {
+                    "description": "Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "P0_20EF": {
+                    "description": "Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "P0_21EF": {
+                    "description": "Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "P0_22EF": {
+                    "description": "Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "P0_23EF": {
+                    "description": "Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "P0_24EF": {
+                    "description": "Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "P0_25EF": {
+                    "description": "Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "P0_26EF": {
+                    "description": "Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "P0_27EF": {
+                    "description": "Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "P0_28EF": {
+                    "description": "Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "P0_29EF": {
+                    "description": "Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "P0_30EF": {
+                    "description": "Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "STATR2": {
+              "description": "GPIO Interrupt Status for Rising edge for Port 0.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "P2_0REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "P2_1REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "P2_2REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "P2_3REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "P2_4REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "P2_5REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "P2_6REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "P2_7REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "P2_8REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "P2_9REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "P2_10REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "P2_11REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "P2_12REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "P2_13REI": {
+                    "description": "Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 14,
+                    "size": 18
+                  }
+                }
+              }
+            },
+            "STATF2": {
+              "description": "GPIO Interrupt Status for Falling edge for Port 0.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "P2_0FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "P2_1FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "P2_2FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "P2_3FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "P2_4FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "P2_5FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "P2_6FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "P2_7FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "P2_8FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "P2_9FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "P2_10FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "P2_11FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "P2_12FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "P2_13FEI": {
+                    "description": "Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 14,
+                    "size": 18
+                  }
+                }
+              }
+            },
+            "CLR2": {
+              "description": "GPIO Interrupt Clear.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "P2_0CI": {
+                    "description": "Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "P2_1CI": {
+                    "description": "Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "P2_2CI": {
+                    "description": "Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "P2_3CI": {
+                    "description": "Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "P2_4CI": {
+                    "description": "Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "P2_5CI": {
+                    "description": "Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "P2_6CI": {
+                    "description": "Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "P2_7CI": {
+                    "description": "Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "P2_8CI": {
+                    "description": "Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "P2_9CI": {
+                    "description": "Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "P2_10CI": {
+                    "description": "Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "P2_11CI": {
+                    "description": "Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "P2_12CI": {
+                    "description": "Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "P2_13CI": {
+                    "description": "Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 14,
+                    "size": 18
+                  }
+                }
+              }
+            },
+            "ENR2": {
+              "description": "GPIO Interrupt Enable for Rising edge for Port 0.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P2_0ER": {
+                    "description": "Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "P2_1ER": {
+                    "description": "Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "P2_2ER": {
+                    "description": "Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "P2_3ER": {
+                    "description": "Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "P2_4ER": {
+                    "description": "Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "P2_5ER": {
+                    "description": "Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "P2_6ER": {
+                    "description": "Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "P2_7ER": {
+                    "description": "Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "P2_8ER": {
+                    "description": "Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "P2_9ER": {
+                    "description": "Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "P2_10ER": {
+                    "description": "Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "P2_11ER": {
+                    "description": "Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "P2_12ER": {
+                    "description": "Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "P2_13ER": {
+                    "description": "Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 14,
+                    "size": 18
+                  }
+                }
+              }
+            },
+            "ENF2": {
+              "description": "GPIO Interrupt Enable for Falling edge for Port 0.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P2_0EF": {
+                    "description": "Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "P2_1EF": {
+                    "description": "Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "P2_2EF": {
+                    "description": "Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "P2_3EF": {
+                    "description": "Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "P2_4EF": {
+                    "description": "Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "P2_5EF": {
+                    "description": "Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "P2_6EF": {
+                    "description": "Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "P2_7EF": {
+                    "description": "Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "P2_8EF": {
+                    "description": "Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "P2_9EF": {
+                    "description": "Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "P2_10EF": {
+                    "description": "Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "P2_11EF": {
+                    "description": "Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "P2_12EF": {
+                    "description": "Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "P2_13EF": {
+                    "description": "Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 14,
+                    "size": 18
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PINCONNECT": {
+        "description": "Pin connect block",
+        "children": {
+          "registers": {
+            "PINSEL0": {
+              "description": "Pin function select register 0.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P0_0": {
+                    "description": "Pin function select P0.0.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.0",
+                            "value": 0
+                          },
+                          "RD1": {
+                            "description": "RD1",
+                            "value": 1
+                          },
+                          "TXD3": {
+                            "description": "TXD3",
+                            "value": 2
+                          },
+                          "SDA1": {
+                            "description": "SDA1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_1": {
+                    "description": "Pin function select P0.1.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.1",
+                            "value": 0
+                          },
+                          "TD1": {
+                            "description": "TD1",
+                            "value": 1
+                          },
+                          "RXD3": {
+                            "description": "RXD3",
+                            "value": 2
+                          },
+                          "SCL1": {
+                            "description": "SCL1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_2": {
+                    "description": "Pin function select P0.2.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.2",
+                            "value": 0
+                          },
+                          "TXD0": {
+                            "description": "TXD0",
+                            "value": 1
+                          },
+                          "AD0": {
+                            "description": "AD0.7",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_3": {
+                    "description": "Pin function select P0.3.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.3.",
+                            "value": 0
+                          },
+                          "RXD0": {
+                            "description": "RXD0",
+                            "value": 1
+                          },
+                          "AD0": {
+                            "description": "AD0.6",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_4": {
+                    "description": "Pin function select P0.4.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.4.",
+                            "value": 0
+                          },
+                          "I2SRX_CLK": {
+                            "description": "I2SRX_CLK",
+                            "value": 1
+                          },
+                          "RD2": {
+                            "description": "RD2",
+                            "value": 2
+                          },
+                          "CAP2": {
+                            "description": "CAP2.0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_5": {
+                    "description": "Pin function select P0.5.",
+                    "offset": 10,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.5.",
+                            "value": 0
+                          },
+                          "I2SRX_WS": {
+                            "description": "I2SRX_WS",
+                            "value": 1
+                          },
+                          "TD2": {
+                            "description": "TD2",
+                            "value": 2
+                          },
+                          "CAP2": {
+                            "description": "CAP2.1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_6": {
+                    "description": "Pin function select P0.6.",
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.6.",
+                            "value": 0
+                          },
+                          "I2SRX_SDA": {
+                            "description": "I2SRX_SDA",
+                            "value": 1
+                          },
+                          "SSEL1": {
+                            "description": "SSEL1",
+                            "value": 2
+                          },
+                          "MAT2": {
+                            "description": "MAT2.0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_7": {
+                    "description": "Pin function select P0.7.",
+                    "offset": 14,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.7.",
+                            "value": 0
+                          },
+                          "I2STX_CLK": {
+                            "description": "I2STX_CLK",
+                            "value": 1
+                          },
+                          "SCK1": {
+                            "description": "SCK1",
+                            "value": 2
+                          },
+                          "MAT2": {
+                            "description": "MAT2.1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_8": {
+                    "description": "Pin function select P0.8.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.8.",
+                            "value": 0
+                          },
+                          "I2STX_WS": {
+                            "description": "I2STX_WS",
+                            "value": 1
+                          },
+                          "MISO1": {
+                            "description": "MISO1",
+                            "value": 2
+                          },
+                          "MAT2": {
+                            "description": "MAT2.2",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_9": {
+                    "description": "Pin function select P0.9.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.9",
+                            "value": 0
+                          },
+                          "I2STX_SDA": {
+                            "description": "I2STX_SDA",
+                            "value": 1
+                          },
+                          "MOSI1": {
+                            "description": "MOSI1",
+                            "value": 2
+                          },
+                          "MAT2": {
+                            "description": "MAT2.3",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_10": {
+                    "description": "Pin function select P0.10.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.10",
+                            "value": 0
+                          },
+                          "TXD2": {
+                            "description": "TXD2",
+                            "value": 1
+                          },
+                          "SDA2": {
+                            "description": "SDA2",
+                            "value": 2
+                          },
+                          "MAT3": {
+                            "description": "MAT3.0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_11": {
+                    "description": "Pin function select P0.11.",
+                    "offset": 22,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.11",
+                            "value": 0
+                          },
+                          "RXD2": {
+                            "description": "RXD2",
+                            "value": 1
+                          },
+                          "SCL2": {
+                            "description": "SCL2",
+                            "value": 2
+                          },
+                          "MAT3": {
+                            "description": "MAT3.1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "P0_15": {
+                    "description": "Pin function select P0.15.",
+                    "offset": 30,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.15",
+                            "value": 0
+                          },
+                          "TXD1": {
+                            "description": "TXD1",
+                            "value": 1
+                          },
+                          "SCK0": {
+                            "description": "SCK0",
+                            "value": 2
+                          },
+                          "SCK": {
+                            "description": "SCK",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINSEL1": {
+              "description": "Pin function select register 1.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P0_16": {
+                    "description": "Pin function select P0.16.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.16",
+                            "value": 0
+                          },
+                          "RXD1": {
+                            "description": "RXD1",
+                            "value": 1
+                          },
+                          "SSEL0": {
+                            "description": "SSEL0",
+                            "value": 2
+                          },
+                          "SSEL": {
+                            "description": "SSEL",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_17": {
+                    "description": "Pin function select P0.17.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.17",
+                            "value": 0
+                          },
+                          "CTS1": {
+                            "description": "CTS1",
+                            "value": 1
+                          },
+                          "MISO0": {
+                            "description": "MISO0",
+                            "value": 2
+                          },
+                          "MISO": {
+                            "description": "MISO",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_18": {
+                    "description": "Pin function select P0.18.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.18",
+                            "value": 0
+                          },
+                          "DCD1": {
+                            "description": "DCD1",
+                            "value": 1
+                          },
+                          "MOSI0": {
+                            "description": "MOSI0",
+                            "value": 2
+                          },
+                          "MOSI": {
+                            "description": "MOSI",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_19": {
+                    "description": "Pin function select P019.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.19.",
+                            "value": 0
+                          },
+                          "DSR1": {
+                            "description": "DSR1",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 2
+                          },
+                          "SDA1": {
+                            "description": "SDA1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_20": {
+                    "description": "Pin function select P0.20.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.20.",
+                            "value": 0
+                          },
+                          "DTR1": {
+                            "description": "DTR1",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 2
+                          },
+                          "SCL1": {
+                            "description": "SCL1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_21": {
+                    "description": "Pin function select P0.21.",
+                    "offset": 10,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_PORT_0": {
+                            "description": "GPIO Port 0.21.",
+                            "value": 0
+                          },
+                          "RI1": {
+                            "description": "RI1",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 2
+                          },
+                          "RD1": {
+                            "description": "RD1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_22": {
+                    "description": "Pin function select P022",
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.22.",
+                            "value": 0
+                          },
+                          "RTS1": {
+                            "description": "RTS1",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 2
+                          },
+                          "TD1": {
+                            "description": "TD1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_23": {
+                    "description": "Pin function select P023.",
+                    "offset": 14,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.23.",
+                            "value": 0
+                          },
+                          "AD0": {
+                            "description": "AD0.0",
+                            "value": 1
+                          },
+                          "I2SRX_CLK": {
+                            "description": "I2SRX_CLK",
+                            "value": 2
+                          },
+                          "CAP3": {
+                            "description": "CAP3.0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_24": {
+                    "description": "Pin function select P0.24.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.24.",
+                            "value": 0
+                          },
+                          "AD0": {
+                            "description": "AD0.1",
+                            "value": 1
+                          },
+                          "I2SRX_WS": {
+                            "description": "I2SRX_WS",
+                            "value": 2
+                          },
+                          "CAP3": {
+                            "description": "CAP3.1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_25": {
+                    "description": "Pin function select P0.25.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.25",
+                            "value": 0
+                          },
+                          "AD0": {
+                            "description": "AD0.2",
+                            "value": 1
+                          },
+                          "I2SRX_SDA": {
+                            "description": "I2SRX_SDA",
+                            "value": 2
+                          },
+                          "TXD3": {
+                            "description": "TXD3",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_26": {
+                    "description": "Pin function select P0.26.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.26",
+                            "value": 0
+                          },
+                          "AD0": {
+                            "description": "AD0.3",
+                            "value": 1
+                          },
+                          "AOUT": {
+                            "description": "AOUT",
+                            "value": 2
+                          },
+                          "RXD3": {
+                            "description": "RXD3",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_27": {
+                    "description": "Pin function select P0.27.",
+                    "offset": 22,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.27",
+                            "value": 0
+                          },
+                          "SDA0": {
+                            "description": "SDA0",
+                            "value": 1
+                          },
+                          "USB_SDA": {
+                            "description": "USB_SDA",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_28": {
+                    "description": "Pin function select P0.28.",
+                    "offset": 24,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.28",
+                            "value": 0
+                          },
+                          "SCL0": {
+                            "description": "SCL0",
+                            "value": 1
+                          },
+                          "USB_SCL": {
+                            "description": "USB_SCL",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_29": {
+                    "description": "Pin function select P0.29",
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.29",
+                            "value": 0
+                          },
+                          "USB_DP": {
+                            "description": "USB_D+",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_30": {
+                    "description": "Pin function select P0.30.",
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P0": {
+                            "description": "GPIO P0.30",
+                            "value": 0
+                          },
+                          "USB_DM": {
+                            "description": "USB_D-",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PINSEL2": {
+              "description": "Pin function select register 2.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P1_0": {
+                    "description": "Pin function select P1.0.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.0",
+                            "value": 0
+                          },
+                          "ENET_TXD0": {
+                            "description": "ENET_TXD0",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_1": {
+                    "description": "Pin function select P1.1.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.1",
+                            "value": 0
+                          },
+                          "ENET_TXD1": {
+                            "description": "ENET_TXD1",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "P1_4": {
+                    "description": "Pin function select P1.4.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.4.",
+                            "value": 0
+                          },
+                          "ENET_TX_EN": {
+                            "description": "ENET_TX_EN",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_8": {
+                    "description": "Pin function select P1.8.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.8.",
+                            "value": 0
+                          },
+                          "ENET_CRS": {
+                            "description": "ENET_CRS",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_9": {
+                    "description": "Pin function select P1.9.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_PORT_1": {
+                            "description": "GPIO Port 1.9",
+                            "value": 0
+                          },
+                          "ENET_RXD0": {
+                            "description": "ENET_RXD0",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_10": {
+                    "description": "Pin function select P1.10.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.10",
+                            "value": 0
+                          },
+                          "ENET_RXD1": {
+                            "description": "ENET_RXD1",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_14": {
+                    "description": "Pin function select P1.14.",
+                    "offset": 22,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.14",
+                            "value": 0
+                          },
+                          "ENET_RX_ER": {
+                            "description": "ENET_RX_ER",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_15": {
+                    "description": "Pin function select P1.15.",
+                    "offset": 30,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.15",
+                            "value": 0
+                          },
+                          "ENET_REF_CLK": {
+                            "description": "ENET_REF_CLK",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINSEL3": {
+              "description": "Pin function select register 3.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P1_16": {
+                    "description": "Pin function select P1.16.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.16",
+                            "value": 0
+                          },
+                          "ENET_MDC": {
+                            "description": "ENET_MDC",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_17": {
+                    "description": "Pin function select P1.17.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.17",
+                            "value": 0
+                          },
+                          "ENET_MDIO": {
+                            "description": "ENET_MDIO",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_18": {
+                    "description": "Pin function select P1.18.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.18",
+                            "value": 0
+                          },
+                          "USB_UP_LED": {
+                            "description": "USB_UP_LED",
+                            "value": 1
+                          },
+                          "PWM1": {
+                            "description": "PWM1.1",
+                            "value": 2
+                          },
+                          "CAP1": {
+                            "description": "CAP1.0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_19": {
+                    "description": "Pin function select P1.19.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.19.",
+                            "value": 0
+                          },
+                          "MCOA0": {
+                            "description": "MCOA0",
+                            "value": 1
+                          },
+                          "USB_PPWR": {
+                            "description": "USB_PPWR",
+                            "value": 2
+                          },
+                          "CAP1": {
+                            "description": "CAP1.1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_20": {
+                    "description": "Pin function select P1.20.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.20.",
+                            "value": 0
+                          },
+                          "MCI0": {
+                            "description": "MCI0",
+                            "value": 1
+                          },
+                          "PWM1": {
+                            "description": "PWM1.2",
+                            "value": 2
+                          },
+                          "SCK0": {
+                            "description": "SCK0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_21": {
+                    "description": "Pin function select P1.21.",
+                    "offset": 10,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.21.",
+                            "value": 0
+                          },
+                          "MCABORT": {
+                            "description": "MCABORT",
+                            "value": 1
+                          },
+                          "PWM1": {
+                            "description": "PWM1.3",
+                            "value": 2
+                          },
+                          "SSEL0": {
+                            "description": "SSEL0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_22": {
+                    "description": "Pin function select P1.22",
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.22.",
+                            "value": 0
+                          },
+                          "MCOB0": {
+                            "description": "MCOB0",
+                            "value": 1
+                          },
+                          "USB_PWRD": {
+                            "description": "USB_PWRD",
+                            "value": 2
+                          },
+                          "MAT1": {
+                            "description": "MAT1.0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_23": {
+                    "description": "Pin function select P1.23.",
+                    "offset": 14,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.23.",
+                            "value": 0
+                          },
+                          "MCI1": {
+                            "description": "MCI1",
+                            "value": 1
+                          },
+                          "PWM1": {
+                            "description": "PWM1.4",
+                            "value": 2
+                          },
+                          "MISO0": {
+                            "description": "MISO0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_24": {
+                    "description": "Pin function select P1.24.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.24.",
+                            "value": 0
+                          },
+                          "MCI2": {
+                            "description": "MCI2",
+                            "value": 1
+                          },
+                          "PWM1": {
+                            "description": "PWM1.5",
+                            "value": 2
+                          },
+                          "MOSI0": {
+                            "description": "MOSI0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_25": {
+                    "description": "Pin function select P1.25.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.25",
+                            "value": 0
+                          },
+                          "MCOA1": {
+                            "description": "MCOA1",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 2
+                          },
+                          "MAT1": {
+                            "description": "MAT1.1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_26": {
+                    "description": "Pin function select P1.26.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.26",
+                            "value": 0
+                          },
+                          "MCOB1": {
+                            "description": "MCOB1",
+                            "value": 1
+                          },
+                          "PWM1": {
+                            "description": "PWM1.6",
+                            "value": 2
+                          },
+                          "CAP0": {
+                            "description": "CAP0.0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_27": {
+                    "description": "Pin function select P1.27.",
+                    "offset": 22,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.27",
+                            "value": 0
+                          },
+                          "CLKOUT": {
+                            "description": "CLKOUT",
+                            "value": 1
+                          },
+                          "USB_OVRCR": {
+                            "description": "USB_OVRCR",
+                            "value": 2
+                          },
+                          "CAP0": {
+                            "description": "CAP0.1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_28": {
+                    "description": "Pin function select P1.28.",
+                    "offset": 24,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.28",
+                            "value": 0
+                          },
+                          "MCOA2": {
+                            "description": "MCOA2",
+                            "value": 1
+                          },
+                          "PCAP1": {
+                            "description": "PCAP1.0",
+                            "value": 2
+                          },
+                          "MAT0": {
+                            "description": "MAT0.0",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_29": {
+                    "description": "Pin function select P1.29",
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.29",
+                            "value": 0
+                          },
+                          "MCOB2": {
+                            "description": "MCOB2",
+                            "value": 1
+                          },
+                          "PCAP1": {
+                            "description": "PCAP1.1",
+                            "value": 2
+                          },
+                          "MAT0": {
+                            "description": "MAT0.1",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_30": {
+                    "description": "Pin function select P1.30.",
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P1": {
+                            "description": "GPIO P1.30",
+                            "value": 0
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 1
+                          },
+                          "VBUS": {
+                            "description": "VBUS",
+                            "value": 2
+                          },
+                          "AD0": {
+                            "description": "AD0.4",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_31": {
+                    "description": "Pin function select P1.31.",
+                    "offset": 30,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_PORT_1": {
+                            "description": "GPIO Port 1.31",
+                            "value": 0
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 1
+                          },
+                          "SCK1": {
+                            "description": "SCK1",
+                            "value": 2
+                          },
+                          "AD0": {
+                            "description": "AD0.5",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINSEL4": {
+              "description": "Pin function select register 4",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P2_0": {
+                    "description": "Pin function select P2.0.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.0",
+                            "value": 0
+                          },
+                          "PWM1": {
+                            "description": "PWM1.1",
+                            "value": 1
+                          },
+                          "TXD1": {
+                            "description": "TXD1",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_1": {
+                    "description": "Pin function select P2.1.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.1",
+                            "value": 0
+                          },
+                          "PWM1": {
+                            "description": "PWM1.2",
+                            "value": 1
+                          },
+                          "RXD1": {
+                            "description": "RXD1",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_2": {
+                    "description": "Pin function select P2.2.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.2",
+                            "value": 0
+                          },
+                          "PWM1": {
+                            "description": "PWM1.3",
+                            "value": 1
+                          },
+                          "CTS1": {
+                            "description": "CTS1",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_3": {
+                    "description": "Pin function select P2.3.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.3.",
+                            "value": 0
+                          },
+                          "PWM1": {
+                            "description": "PWM1.4",
+                            "value": 1
+                          },
+                          "DCD1": {
+                            "description": "DCD1",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_4": {
+                    "description": "Pin function select P2.4.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.4.",
+                            "value": 0
+                          },
+                          "PWM1": {
+                            "description": "PWM1.5",
+                            "value": 1
+                          },
+                          "DSR1": {
+                            "description": "DSR1",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_5": {
+                    "description": "Pin function select P2.5.",
+                    "offset": 10,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.5.",
+                            "value": 0
+                          },
+                          "PWM1": {
+                            "description": "PWM1.6",
+                            "value": 1
+                          },
+                          "DTR1": {
+                            "description": "DTR1",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_6": {
+                    "description": "Pin function select P2.6.",
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.6.",
+                            "value": 0
+                          },
+                          "PCAP1": {
+                            "description": "PCAP1.0",
+                            "value": 1
+                          },
+                          "RI1": {
+                            "description": "RI1",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_7": {
+                    "description": "Pin function select P2.7.",
+                    "offset": 14,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.7.",
+                            "value": 0
+                          },
+                          "RD2": {
+                            "description": "RD2",
+                            "value": 1
+                          },
+                          "RTS1": {
+                            "description": "RTS1",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_8": {
+                    "description": "Pin function select P2.8.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.8.",
+                            "value": 0
+                          },
+                          "TD2": {
+                            "description": "TD2",
+                            "value": 1
+                          },
+                          "TXD2": {
+                            "description": "TXD2",
+                            "value": 2
+                          },
+                          "ENET_MDC": {
+                            "description": "ENET_MDC",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_9": {
+                    "description": "Pin function select P2.9.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.9",
+                            "value": 0
+                          },
+                          "USB_CONNECT": {
+                            "description": "USB_CONNECT",
+                            "value": 1
+                          },
+                          "RXD2": {
+                            "description": "RXD2",
+                            "value": 2
+                          },
+                          "ENET_MDIO": {
+                            "description": "ENET_MDIO",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_10": {
+                    "description": "Pin function select P2.10.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.10",
+                            "value": 0
+                          },
+                          "EINT0": {
+                            "description": "EINT0",
+                            "value": 1
+                          },
+                          "NMI": {
+                            "description": "NMI",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_11": {
+                    "description": "Pin function select P2.11.",
+                    "offset": 22,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.11",
+                            "value": 0
+                          },
+                          "EINT1": {
+                            "description": "EINT1",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 2
+                          },
+                          "I2STX_CLK": {
+                            "description": "I2STX_CLK",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_12": {
+                    "description": "Pin function select P2.12.",
+                    "offset": 24,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.12",
+                            "value": 0
+                          },
+                          "EINT2": {
+                            "description": "EINT2",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 2
+                          },
+                          "I2STX_WS": {
+                            "description": "I2STX_WS",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_13": {
+                    "description": "Pin function select P2.13.",
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P2": {
+                            "description": "GPIO P2.13",
+                            "value": 0
+                          },
+                          "EINT3": {
+                            "description": "EINT3",
+                            "value": 1
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 2
+                          },
+                          "I2STX_SDA": {
+                            "description": "I2STX_SDA",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "PINSEL7": {
+              "description": "Pin function select register 7",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 22,
+                    "size": 10
+                  },
+                  "P3_25": {
+                    "description": "Pin function select P3.25.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P3": {
+                            "description": "GPIO P3.25",
+                            "value": 0
+                          },
+                          "RESERVED": {
+                            "description": "Reserved",
+                            "value": 1
+                          },
+                          "MAT0": {
+                            "description": "MAT0.0",
+                            "value": 2
+                          },
+                          "PWM1": {
+                            "description": "PWM1.2",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P3_26": {
+                    "description": "Pin function select P3.26.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P3": {
+                            "description": "GPIO P3.26",
+                            "value": 0
+                          },
+                          "STCLK": {
+                            "description": "STCLK",
+                            "value": 1
+                          },
+                          "MAT0": {
+                            "description": "MAT0.1",
+                            "value": 2
+                          },
+                          "PWM1": {
+                            "description": "PWM1.3",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINSEL9": {
+              "description": "Pin function select register 9",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "P4_28": {
+                    "description": "Pin function select P4.28.",
+                    "offset": 24,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P4": {
+                            "description": "GPIO P4.28",
+                            "value": 0
+                          },
+                          "RX_MCLK": {
+                            "description": "RX_MCLK",
+                            "value": 1
+                          },
+                          "MAT2": {
+                            "description": "MAT2.0",
+                            "value": 2
+                          },
+                          "TXD3": {
+                            "description": "TXD3",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P4_29": {
+                    "description": "Pin function select P4.29.",
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "GPIO_P4": {
+                            "description": "GPIO P4.29",
+                            "value": 0
+                          },
+                          "TX_MCLK": {
+                            "description": "TX_MCLK",
+                            "value": 1
+                          },
+                          "MAT2": {
+                            "description": "MAT2.1",
+                            "value": 2
+                          },
+                          "RXD3": {
+                            "description": "RXD3",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINSEL10": {
+              "description": "Pin function select register 10",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Software should not write 1 to these bits.",
+                    "offset": 4,
+                    "size": 28
+                  },
+                  "TPIUCTRL": {
+                    "description": "TPIU interface pins control.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Disabled. TPIU interface is disabled.",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINMODE0": {
+              "description": "Pin mode select register 0",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P0_00MODE": {
+                    "description": "Port 0 pin 0 on-chip pull-up/down resistor control.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.0 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.0 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.0 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.0 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_01MODE": {
+                    "description": "Port 0 pin 1 control.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.1 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.1 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.1 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.1 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_02MODE": {
+                    "description": "Port 0 pin 2 control.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.2 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.2 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.2 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.2 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_03MODE": {
+                    "description": "Port 0 pin 3 control.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.3 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.3 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.3 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.3 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_04MODE": {
+                    "description": "Port 0 pin 4 control.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.4 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.4 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.4 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.4 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_05MODE": {
+                    "description": "Port 0 pin 5 control.",
+                    "offset": 10,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.5 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.5 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.5 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.5 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_06MODE": {
+                    "description": "Port 0 pin 6 control.",
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.6 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.6 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.6 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_07MODE": {
+                    "description": "Port 0 pin 7 control.",
+                    "offset": 14,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.7 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.7 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.7 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.7 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_08MODE": {
+                    "description": "Port 0 pin 8 control.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.8 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.8 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.8 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.8 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_09MODE": {
+                    "description": "Port 0 pin 9 control.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.9 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.9 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.9 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.9 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_10MODE": {
+                    "description": "Port 0 pin 10 control.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.10 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.10 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.10 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.10 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_11MODE": {
+                    "description": "Port 0 pin 11 control.",
+                    "offset": 22,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.11 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.11 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.11 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.11 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 24,
+                    "size": 6
+                  },
+                  "P0_15MODE": {
+                    "description": "Port 0 pin 15 control.",
+                    "offset": 30,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.15 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.15 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.15 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.15 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINMODE1": {
+              "description": "Pin mode select register 1",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P0_16MODE": {
+                    "description": "Port 1 pin 16 control.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.16 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.16 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.16 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.16 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_17MODE": {
+                    "description": "Port 1 pin 17 control.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.17 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.17 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.17 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.17 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_18MODE": {
+                    "description": "Port 1 pin 18 control.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.18 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.18 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.18 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.18 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_19MODE": {
+                    "description": "Port 1 pin 19 control.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.19 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.19 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.19 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.19 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_20MODE": {
+                    "description": "Port 1 pin 20 control.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.20 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.20 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.20 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.20 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_21MODE": {
+                    "description": "Port 1 pin 21 control.",
+                    "offset": 10,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.21 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.21 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.21 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.21 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_22MODE": {
+                    "description": "Port 1 pin 22 control.",
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.22 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.22 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.22 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.22 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_23MODE": {
+                    "description": "Port 1 pin 23 control.",
+                    "offset": 14,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.23 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.23 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.23 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.23 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_24MODE": {
+                    "description": "Port 1 pin 24 control.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.24 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.24 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.24 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.24 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_25MODE": {
+                    "description": "Port 1 pin 25 control.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.25 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.25 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.25 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.25 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_26MODE": {
+                    "description": "Port 1 pin 26 control.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P0.26 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P0.26 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P0.26 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P0.26 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PINMODE2": {
+              "description": "Pin mode select register 2",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P1_00MODE": {
+                    "description": "Port 1 pin 0 control.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.0 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.0 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.0 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.0 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_01MODE": {
+                    "description": "Port 1 pin 1 control.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.1 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.1 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.1 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.1 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 22,
+                    "size": 6
+                  },
+                  "P1_04MODE": {
+                    "description": "Port 1 pin 4 control.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.4 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.4 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.4 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.4 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_08MODE": {
+                    "description": "Port 1 pin 8 control.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.8 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.8 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.8 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.8 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_09MODE": {
+                    "description": "Port 1 pin 9 control.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.9 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.9 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.9 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.9 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_10MODE": {
+                    "description": "Port 1 pin 10 control.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.10 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.10 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.10 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.10 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_14MODE": {
+                    "description": "Port 1 pin 14 control.",
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.14 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.14 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.14 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.14 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_15MODE": {
+                    "description": "Port 1 pin 15 control.",
+                    "offset": 30,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.15 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.15 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.15 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.15 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINMODE3": {
+              "description": "Pin mode select register 3.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P1_16MODE": {
+                    "description": "Port 1 pin 16 control.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.16 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.16 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.16 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.16 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_17MODE": {
+                    "description": "Port 1 pin 17 control.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.17 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.17 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.17 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.17 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_18MODE": {
+                    "description": "Port 1 pin 18 control.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.18 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.18 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.18 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.18 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_19MODE": {
+                    "description": "Port 1 pin 19 control.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.19 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.19 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.19 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.19 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_20MODE": {
+                    "description": "Port 1 pin 20 control.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.20 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.20 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.20 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.20 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_21MODE": {
+                    "description": "Port 1 pin 21 control.",
+                    "offset": 10,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.21 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.21 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.21 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.21 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_22MODE": {
+                    "description": "Port 1 pin 22 control.",
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.22 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.22 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.22 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.22 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_23MODE": {
+                    "description": "Port 1 pin 23 control.",
+                    "offset": 14,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.23 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.23 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.23 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.23 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_24MODE": {
+                    "description": "Port 1 pin 24 control.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.24 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.24 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.24 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.24 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_25MODE": {
+                    "description": "Port 1 pin 25 control.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.25 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.25 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.25 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.25 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_26MODE": {
+                    "description": "Port 1 pin 26 control.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.26 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.26 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.26 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.26 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_27MODE": {
+                    "description": "Port 1 pin 27 control.",
+                    "offset": 22,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.27 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.27 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.27 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.27 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_28MODE": {
+                    "description": "Port 1 pin 28 control.",
+                    "offset": 24,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.28 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.28 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.28 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.28 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_29MODE": {
+                    "description": "Port 1 pin 29 control.",
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.29 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.29 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.29 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.29 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_30MODE": {
+                    "description": "Port 1 pin 30 control.",
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.30 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.30 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.30 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.30 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_31MODE": {
+                    "description": "Port 1 pin 31 control.",
+                    "offset": 30,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P1.31 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P1.31 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P1.31 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P1.31 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINMODE4": {
+              "description": "Pin mode select register 4",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P2_00MODE": {
+                    "description": "Port 2 pin 0 control.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.0 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.0 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.0 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.0 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_01MODE": {
+                    "description": "Port 2 pin 1 control.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.1 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.1 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.1 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.1 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_02MODE": {
+                    "description": "Port 2 pin 2 control.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.2 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.2 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.2 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.2 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_03MODE": {
+                    "description": "Port 2 pin 3 control.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.3 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.3 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.3 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.3 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_04MODE": {
+                    "description": "Port 2 pin 4 control.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.4 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.4 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.4 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.4 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_05MODE": {
+                    "description": "Port 2 pin 5 control.",
+                    "offset": 10,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.5 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.5 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.5 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.5 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_06MODE": {
+                    "description": "Port 2 pin 6 control.",
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.6 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.6 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.6 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.6 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_07MODE": {
+                    "description": "Port 2 pin 7 control.",
+                    "offset": 14,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.7 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.7 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.7 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.7 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_08MODE": {
+                    "description": "Port 2 pin 8 control.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.8 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.8 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.8 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.8 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_09MODE": {
+                    "description": "Port 2 pin 9 control.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.9 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.9 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.9 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.9 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_10MODE": {
+                    "description": "Port 2 pin 10 control.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.10 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.10 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.10 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.10 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_11MODE": {
+                    "description": "Port 2 pin 11 control.",
+                    "offset": 22,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.11 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.11 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.11 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.11 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_12MODE": {
+                    "description": "Port 2 pin 12 control.",
+                    "offset": 24,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.12 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.12 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.12 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.12 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_13MODE": {
+                    "description": "Port 2 pin 13 control.",
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P2.13 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P2.13 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P2.13 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P2.13 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "PINMODE7": {
+              "description": "Pin mode select register 7",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 22,
+                    "size": 10
+                  },
+                  "P3_25MODE": {
+                    "description": "Port 3 pin 25 control.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P3.25 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P3.25 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P3.25 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P3.25 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P3_26MODE": {
+                    "description": "Port 3 pin 26 control.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P3.26 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P3.26 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P3.26 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P3.26 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINMODE9": {
+              "description": "Pin mode select register 9",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "P4_28MODE": {
+                    "description": "Port 4 pin 28 control.",
+                    "offset": 24,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P4.28 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P4.28 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P4.28 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P4.28 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P4_29MODE": {
+                    "description": "Port 4 pin 29 control.",
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "PULL_UP": {
+                            "description": "Pull-up. P4.29 pin has a pull-up resistor enabled.",
+                            "value": 0
+                          },
+                          "REPEATER": {
+                            "description": "Repeater. P4.29 pin has repeater mode enabled.",
+                            "value": 1
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. P4.29 pin has neither pull-up nor pull-down.",
+                            "value": 2
+                          },
+                          "PULL_DOWN": {
+                            "description": "Pull-down. P4.29 has a pull-down resistor enabled.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINMODE_OD0": {
+              "description": "Open drain mode control register 0",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P0_00OD": {
+                    "description": "Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.0 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.0 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_01OD": {
+                    "description": "Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.1 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.1 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_02OD": {
+                    "description": "Port 0 pin 2 open drain mode control",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.2 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.2 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_03OD": {
+                    "description": "Port 0 pin 3 open drain mode control",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.3 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.3 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_04OD": {
+                    "description": "Port 0 pin 4 open drain mode control",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.4 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.4 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_05OD": {
+                    "description": "Port 0 pin 5 open drain mode control",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.5 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.5 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_06OD": {
+                    "description": "Port 0 pin 6 open drain mode control",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.6 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.6 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_07OD": {
+                    "description": "Port 0 pin 7 open drain mode control",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.7 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.7 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_08OD": {
+                    "description": "Port 0 pin 8 open drain mode control",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.8 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.8 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_09OD": {
+                    "description": "Port 0 pin 9 open drain mode control",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.9 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.9 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_10OD": {
+                    "description": "Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.10 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.10 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_11OD": {
+                    "description": "Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.11 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.11 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "P0_15OD": {
+                    "description": "Port 0 pin 15 open drain mode control",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.15 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.15 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_16OD": {
+                    "description": "Port 0 pin 16 open drain mode control",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.16 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.16 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_17OD": {
+                    "description": "Port 0 pin 17 open drain mode control",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.17 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.17 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_18OD": {
+                    "description": "Port 0 pin 18 open drain mode control",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.18 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.18 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_19OD": {
+                    "description": "Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.19 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.19 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_20OD": {
+                    "description": "Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.20 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.20 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_21OD": {
+                    "description": "Port 0 pin 21 open drain mode control",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.21 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.21 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_22OD": {
+                    "description": "Port 0 pin 22 open drain mode control",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.22 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.22 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_23OD": {
+                    "description": "Port 0 pin 23 open drain mode control",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.23 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.23 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_24OD": {
+                    "description": "Port 0 pin 24open drain mode control",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.23 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.23 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_25OD": {
+                    "description": "Port 0 pin 25 open drain mode control",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.25 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.25 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_26OD": {
+                    "description": "Port 0 pin 26 open drain mode control",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.26 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.26 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_29OD": {
+                    "description": "Port 0 pin 29 open drain mode control",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.29 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.29 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P0_30OD": {
+                    "description": "Port 0 pin 30 open drain mode control",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P0.30 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P0.30 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINMODE_OD1": {
+              "description": "Open drain mode control register 1",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P1_00OD": {
+                    "description": "Port 1 pin 0 open drain mode control.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.0 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.0 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_01OD": {
+                    "description": "Port 1 pin 1 open drain mode control, see P1.00OD",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.1 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.1 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 11,
+                    "size": 3
+                  },
+                  "P1_04OD": {
+                    "description": "Port 1 pin 4 open drain mode control, see P1.00OD",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.4 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.4 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_08OD": {
+                    "description": "Port 1 pin 8 open drain mode control, see P1.00OD",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.8 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.8 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_09OD": {
+                    "description": "Port 1 pin 9 open drain mode control, see P1.00OD",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.9 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.9 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_10OD": {
+                    "description": "Port 1 pin 10 open drain mode control, see P1.00OD",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.10 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.10 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_14OD": {
+                    "description": "Port 1 pin 14 open drain mode control, see P1.00OD",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.14 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.14 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_15OD": {
+                    "description": "Port 1 pin 15 open drain mode control, see P1.00OD",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.15 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.15 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_16OD": {
+                    "description": "Port 1 pin 16 open drain mode control, see P1.00OD",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.16 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.16 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_17OD": {
+                    "description": "Port 1 pin 17 open drain mode control, see P1.00OD",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.17 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.17 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_18OD": {
+                    "description": "Port 1 pin 18 open drain mode control, see P1.00OD",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.18 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.18 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_19OD": {
+                    "description": "Port 1 pin 19 open drain mode control, see P1.00OD",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.19 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.19 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_20OD": {
+                    "description": "Port 1 pin 20open drain mode control, see P1.00OD",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.20 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.20 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_21OD": {
+                    "description": "Port 1 pin 21 open drain mode control, see P1.00OD",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.21 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.21 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_22OD": {
+                    "description": "Port 1 pin 22 open drain mode control, see P1.00OD",
+                    "offset": 22,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.22 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.22 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_23OD": {
+                    "description": "Port 1 pin 23 open drain mode control, see P1.00OD",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.23 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.23 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_24OD": {
+                    "description": "Port 1 pin 24open drain mode control, see P1.00OD",
+                    "offset": 24,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.24 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.24 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_25OD": {
+                    "description": "Port 1 pin 25 open drain mode control, see P1.00OD",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.25 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.25 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_26OD": {
+                    "description": "Port 1 pin 26 open drain mode control, see P1.00OD",
+                    "offset": 26,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.26 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.26 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_27OD": {
+                    "description": "Port 1 pin 27 open drain mode control, see P1.00OD",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.27 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.27 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_28OD": {
+                    "description": "Port 1 pin 28 open drain mode control, see P1.00OD",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.28 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.28 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_29OD": {
+                    "description": "Port 1 pin 29 open drain mode control, see P1.00OD",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.29 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.29 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_30OD": {
+                    "description": "Port 1 pin 30 open drain mode control, see P1.00OD",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.30 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.30 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P1_31OD": {
+                    "description": "Port 1 pin 31 open drain mode control.",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P1.31 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P1.31 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PINMODE_OD2": {
+              "description": "Open drain mode control register 2",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "P2_00OD": {
+                    "description": "Port 2 pin 0 open drain mode control.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.0 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.0 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_01OD": {
+                    "description": "Port 2 pin 1 open drain mode control, see P2.00OD",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.1 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.1p in is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_02OD": {
+                    "description": "Port 2 pin 2 open drain mode control, see P2.00OD",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.2 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.2 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_03OD": {
+                    "description": "Port 2 pin 3 open drain mode control, see P2.00OD",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.3 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.3 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_04OD": {
+                    "description": "Port 2 pin 4 open drain mode control, see P2.00OD",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.4 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.4 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_05OD": {
+                    "description": "Port 2 pin 5 open drain mode control, see P2.00OD",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.5 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.5 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_06OD": {
+                    "description": "Port 2 pin 6 open drain mode control, see P2.00OD",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.6 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.6 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_07OD": {
+                    "description": "Port 2 pin 7 open drain mode control, see P2.00OD",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.7 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.7 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_08OD": {
+                    "description": "Port 2 pin 8 open drain mode control, see P2.00OD",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.8 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.8 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_09OD": {
+                    "description": "Port 2 pin 9 open drain mode control, see P2.00OD",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.9 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.9 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_10OD": {
+                    "description": "Port 2 pin 10 open drain mode control, see P2.00OD",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.10 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.10 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_11OD": {
+                    "description": "Port 2 pin 11 open drain mode control, see P2.00OD",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.11 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.11 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_12OD": {
+                    "description": "Port 2 pin 12 open drain mode control, see P2.00OD",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.12 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.12 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P2_13OD": {
+                    "description": "Port 2 pin 13 open drain mode control, see P2.00OD",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P2.13 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P2.13 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 14,
+                    "size": 18
+                  }
+                }
+              }
+            },
+            "PINMODE_OD3": {
+              "description": "Open drain mode control register 3",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 27,
+                    "size": 5
+                  },
+                  "P3_25OD": {
+                    "description": "Port 3 pin 25 open drain mode control.",
+                    "offset": 25,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P3.25 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P3.25 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P3_26OD": {
+                    "description": "Port 3 pin 26 open drain mode control, see P3.25OD",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PINMODE_OD4": {
+              "description": "Open drain mode control register 4",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "P4_28OD": {
+                    "description": "Port 4 pin 28 open drain mode control.",
+                    "offset": 28,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "Normal. P4.28 pin is in the normal (not open drain) mode.",
+                            "value": 0
+                          },
+                          "OPEN_DRAIN": {
+                            "description": "Open-drain. P4.28 pin is in the open drain mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "P4_29OD": {
+                    "description": "Port 4 pin 29 open drain mode control, see P4.28OD",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "I2CPADCFG": {
+              "description": "I2C Pin Configuration register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDADRV0": {
+                    "description": "Drive mode control for the SDA0 pin, P0.27.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "STANDARD": {
+                            "description": "Standard. The SDA0 pin is in the standard drive mode.",
+                            "value": 0
+                          },
+                          "FAST_MODE_PLUS": {
+                            "description": "Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SDAI2C0": {
+                    "description": "I 2C filter mode control for the SDA0 pin, P0.27.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled.",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SCLDRV0": {
+                    "description": "Drive mode control for the SCL0 pin, P0.28.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "STANDARD": {
+                            "description": "Standard. The SCL0 pin is in the standard drive mode.",
+                            "value": 0
+                          },
+                          "FAST_MODE_PLUS": {
+                            "description": "Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SCLI2C0": {
+                    "description": "I 2C filter mode control for the SCL0 pin, P0.28.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled.",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SSP1": {
+        "description": "SSP1 controller",
+        "children": {
+          "registers": {
+            "CR0": {
+              "description": "Control Register 0. Selects the serial clock rate, bus type, and data size.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DSS": {
+                    "description": "Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "4_BIT_TRANSFER": {
+                            "description": "4-bit transfer",
+                            "value": 3
+                          },
+                          "5_BIT_TRANSFER": {
+                            "description": "5-bit transfer",
+                            "value": 4
+                          },
+                          "6_BIT_TRANSFER": {
+                            "description": "6-bit transfer",
+                            "value": 5
+                          },
+                          "7_BIT_TRANSFER": {
+                            "description": "7-bit transfer",
+                            "value": 6
+                          },
+                          "8_BIT_TRANSFER": {
+                            "description": "8-bit transfer",
+                            "value": 7
+                          },
+                          "9_BIT_TRANSFER": {
+                            "description": "9-bit transfer",
+                            "value": 8
+                          },
+                          "10_BIT_TRANSFER": {
+                            "description": "10-bit transfer",
+                            "value": 9
+                          },
+                          "11_BIT_TRANSFER": {
+                            "description": "11-bit transfer",
+                            "value": 10
+                          },
+                          "12_BIT_TRANSFER": {
+                            "description": "12-bit transfer",
+                            "value": 11
+                          },
+                          "13_BIT_TRANSFER": {
+                            "description": "13-bit transfer",
+                            "value": 12
+                          },
+                          "14_BIT_TRANSFER": {
+                            "description": "14-bit transfer",
+                            "value": 13
+                          },
+                          "15_BIT_TRANSFER": {
+                            "description": "15-bit transfer",
+                            "value": 14
+                          },
+                          "16_BIT_TRANSFER": {
+                            "description": "16-bit transfer",
+                            "value": 15
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FRF": {
+                    "description": "Frame Format.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SPI": {
+                            "description": "SPI",
+                            "value": 0
+                          },
+                          "TI": {
+                            "description": "TI",
+                            "value": 1
+                          },
+                          "MICROWIRE": {
+                            "description": "Microwire",
+                            "value": 2
+                          },
+                          "THIS_COMBINATION_IS_": {
+                            "description": "This combination is not supported and should not be used.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPOL": {
+                    "description": "Clock Out Polarity. This bit is only used in SPI mode.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "BUS_LOW": {
+                            "description": "SSP controller maintains the bus clock low between frames.",
+                            "value": 0
+                          },
+                          "BUS_HIGH": {
+                            "description": "SSP controller maintains the bus clock high between frames.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CPHA": {
+                    "description": "Clock Out Phase. This bit is only used in SPI mode.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "FIRST_CLOCK": {
+                            "description": "SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.",
+                            "value": 0
+                          },
+                          "SECOND_CLOCK": {
+                            "description": "SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SCR": {
+                    "description": "Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CR1": {
+              "description": "Control Register 1. Selects master/slave and other modes.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LBM": {
+                    "description": "Loop Back Mode.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "During normal operation.",
+                            "value": 0
+                          },
+                          "OUPTU": {
+                            "description": "Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SSE": {
+                    "description": "SSP Enable.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "The SSP controller is disabled.",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MS": {
+                    "description": "Master/Slave Mode.This bit can only be written when the SSE bit is 0.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MASTER": {
+                            "description": "The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.",
+                            "value": 0
+                          },
+                          "SLAVE": {
+                            "description": "The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SOD": {
+                    "description": "Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO).",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "DR": {
+              "description": "Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status Register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TFE": {
+                    "description": "Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TNF": {
+                    "description": "Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RNE": {
+                    "description": "Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RFF": {
+                    "description": "Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BSY": {
+                    "description": "Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "CPSR": {
+              "description": "Clock Prescale Register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPSDVSR": {
+                    "description": "This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "IMSC": {
+              "description": "Interrupt Mask Set and Clear Register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RORIM": {
+                    "description": "Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RTIM": {
+                    "description": "Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXIM": {
+                    "description": "Software should set this bit to enable interrupt when the Rx FIFO is at least half full.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXIM": {
+                    "description": "Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "RIS": {
+              "description": "Raw Interrupt Status Register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RORRIS": {
+                    "description": "This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RTRIS": {
+                    "description": "This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXRIS": {
+                    "description": "This bit is 1 if the Rx FIFO is at least half full.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXRIS": {
+                    "description": "This bit is 1 if the Tx FIFO is at least half empty.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "MIS": {
+              "description": "Masked Interrupt Status Register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RORMIS": {
+                    "description": "This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RTMIS": {
+                    "description": "This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXMIS": {
+                    "description": "This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXMIS": {
+                    "description": "This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "SSPICR Interrupt Clear Register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "RORIC": {
+                    "description": "Writing a 1 to this bit clears the   frame was received when RxFIFO was full interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RTIC": {
+                    "description": "Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "DMACR": {
+              "description": "SSP0 DMA control register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDMAE": {
+                    "description": "Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXDMAE": {
+                    "description": "Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ADC": {
+        "description": "Analog-to-Digital Converter (ADC) ",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "SEL": {
+                    "description": "Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CLKDIV": {
+                    "description": "The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BURST": {
+                    "description": "Burst mode",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "BURST": {
+                            "description": "The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start.",
+                            "value": 1
+                          },
+                          "SW": {
+                            "description": "Conversions are software controlled and require 31 clocks.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "PDN": {
+                    "description": "Power down mode",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "POWERED": {
+                            "description": "The A/D converter is operational.",
+                            "value": 1
+                          },
+                          "POWERDOWN": {
+                            "description": "The A/D converter is in power-down mode.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "START": {
+                    "description": "When the BURST bit is 0, these bits control whether and when an A/D conversion is started:",
+                    "offset": 24,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "NO_START_THIS_VALUE": {
+                            "description": "No start (this value should be used when clearing PDN to 0).",
+                            "value": 0
+                          },
+                          "START_CONVERSION_NOW": {
+                            "description": "Start conversion now.",
+                            "value": 1
+                          },
+                          "P2_10": {
+                            "description": "Start conversion when the edge selected by bit 27 occurs on the P2[10] pin.",
+                            "value": 2
+                          },
+                          "P1_27": {
+                            "description": "Start conversion when the edge selected by bit 27 occurs on the P1[27] pin.",
+                            "value": 3
+                          },
+                          "MAT0_1": {
+                            "description": "Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin.",
+                            "value": 4
+                          },
+                          "MAT0_3": {
+                            "description": "Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin.",
+                            "value": 5
+                          },
+                          "MAT1_0": {
+                            "description": "Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin.",
+                            "value": 6
+                          },
+                          "MAT1_1": {
+                            "description": "Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin.",
+                            "value": 7
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EDGE": {
+                    "description": "This bit is significant only when the START field contains 010-111. In these cases:",
+                    "offset": 27,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "FALLLING": {
+                            "description": "Start conversion on a falling edge on the selected CAP/MAT signal.",
+                            "value": 1
+                          },
+                          "RISING": {
+                            "description": "Start conversion on a rising edge on the selected CAP/MAT signal.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GDR": {
+              "description": "A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 27,
+                    "size": 3
+                  },
+                  "RESULT": {
+                    "description": "When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "CHN": {
+                    "description": "These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...).",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "OVERRUN": {
+                    "description": "This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DONE": {
+                    "description": "This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 256,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADINTEN0": {
+                    "description": "Interrupt enable",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Completion of a conversion on ADC channel 0 will not generate an interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE": {
+                            "description": "Completion of a conversion on ADC channel 0 will generate an interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADINTEN1": {
+                    "description": "Interrupt enable",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Completion of a conversion on ADC channel 1 will not generate an interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE": {
+                            "description": "Completion of a conversion on ADC channel 1 will generate an interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADINTEN2": {
+                    "description": "Interrupt enable",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Completion of a conversion on ADC channel 2 will not generate an interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE": {
+                            "description": "Completion of a conversion on ADC channel 2 will generate an interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADINTEN3": {
+                    "description": "Interrupt enable",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Completion of a conversion on ADC channel 3 will not generate an interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE": {
+                            "description": "Completion of a conversion on ADC channel 3 will generate an interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADINTEN4": {
+                    "description": "Interrupt enable",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Completion of a conversion on ADC channel 4 will not generate an interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE": {
+                            "description": "Completion of a conversion on ADC channel 4 will generate an interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADINTEN5": {
+                    "description": "Interrupt enable",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Completion of a conversion on ADC channel 5 will not generate an interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE": {
+                            "description": "Completion of a conversion on ADC channel 5 will generate an interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADINTEN6": {
+                    "description": "Interrupt enable",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Completion of a conversion on ADC channel 6 will not generate an interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE": {
+                            "description": "Completion of a conversion on ADC channel 6 will generate an interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADINTEN7": {
+                    "description": "Interrupt enable",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Completion of a conversion on ADC channel 7 will not generate an interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE": {
+                            "description": "Completion of a conversion on ADC channel 7 will generate an interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADGINTEN": {
+                    "description": "Interrupt enable",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "CHANNELS": {
+                            "description": "Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts.",
+                            "value": 0
+                          },
+                          "GLOBAL": {
+                            "description": "The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 9,
+                    "size": 23
+                  }
+                }
+              }
+            },
+            "STAT": {
+              "description": "A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DONE0": {
+                    "description": "This bit mirrors the DONE status flag from the result register for A/D channel 0.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DONE1": {
+                    "description": "This bit mirrors the DONE status flag from the result register for A/D channel 1.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DONE2": {
+                    "description": "This bit mirrors the DONE status flag from the result register for A/D channel 2.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DONE3": {
+                    "description": "This bit mirrors the DONE status flag from the result register for A/D channel 3.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DONE4": {
+                    "description": "This bit mirrors the DONE status flag from the result register for A/D channel 4.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DONE5": {
+                    "description": "This bit mirrors the DONE status flag from the result register for A/D channel 5.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DONE6": {
+                    "description": "This bit mirrors the DONE status flag from the result register for A/D channel 6.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DONE7": {
+                    "description": "This bit mirrors the DONE status flag from the result register for A/D channel 7.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OVERRUN0": {
+                    "description": "This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OVERRUN1": {
+                    "description": "This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OVERRUN2": {
+                    "description": "This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OVERRUN3": {
+                    "description": "This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OVERRUN4": {
+                    "description": "This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OVERRUN5": {
+                    "description": "This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OVERRUN6": {
+                    "description": "This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OVERRUN7": {
+                    "description": "This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ADINT": {
+                    "description": "This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 17,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "TRM": {
+              "description": "ADC trim register.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 12,
+                    "size": 20
+                  },
+                  "ADCOFFS": {
+                    "description": "Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user.",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "TRIM": {
+                    "description": "written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write.",
+                    "offset": 8,
+                    "size": 4
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CANAFRAM": {
+        "description": "CAN acceptance filter RAM"
+      },
+      "CANAF": {
+        "description": " CAN controller acceptance filter ",
+        "children": {
+          "registers": {
+            "AFMR": {
+              "description": "Acceptance Filter Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "ACCOFF": {
+                    "description": "if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ACCBP": {
+                    "description": "All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EFCAN": {
+                    "description": "FullCAN mode",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "SOFTWARE_MUST_READ_A": {
+                            "description": "Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers.",
+                            "value": 0
+                          },
+                          "THE_ACCEPTANCE_FILTE": {
+                            "description": "The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            },
+            "SFF_SA": {
+              "description": "Standard Frame Individual Start Address Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 11,
+                    "size": 21
+                  },
+                  "SFF_SA": {
+                    "description": "The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM.",
+                    "offset": 2,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "SFF_GRP_SA": {
+              "description": "Standard Frame Group Start Address Register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 12,
+                    "size": 20
+                  },
+                  "SFF_GRP_SA": {
+                    "description": "The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.",
+                    "offset": 2,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EFF_SA": {
+              "description": "Extended Frame Start Address Register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 11,
+                    "size": 21
+                  },
+                  "EFF_SA": {
+                    "description": "The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register.",
+                    "offset": 2,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "EFF_GRP_SA": {
+              "description": "Extended Frame Group Start Address Register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 12,
+                    "size": 20
+                  },
+                  "EFF_GRP_SA": {
+                    "description": "The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.",
+                    "offset": 2,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "ENDOFTABLE": {
+              "description": "End of AF Tables register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 12,
+                    "size": 20
+                  },
+                  "ENDOFTABLE": {
+                    "description": "The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table.",
+                    "offset": 2,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "LUTERRAD": {
+              "description": "LUT Error Address register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 11,
+                    "size": 21
+                  },
+                  "LUTERRAD": {
+                    "description": "It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables.",
+                    "offset": 2,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "LUTERR": {
+              "description": "LUT Error Register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "LUTERR": {
+                    "description": "This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, the value read from a reserved bit is not defined.",
+                    "offset": 1,
+                    "size": 31
+                  }
+                }
+              }
+            },
+            "FCANIE": {
+              "description": "FullCAN interrupt enable register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FCANIE": {
+                    "description": "Global FullCAN Interrupt Enable. When 1, this interrupt is enabled.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 1,
+                    "size": 31
+                  }
+                }
+              }
+            },
+            "FCANIC0": {
+              "description": "FullCAN interrupt and capture register0",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTPND": {
+                    "description": "FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FCANIC1": {
+              "description": "FullCAN interrupt and capture register1",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IntPnd32": {
+                    "description": "FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CCAN": {
+        "description": "Central CAN controller ",
+        "children": {
+          "registers": {
+            "TXSR": {
+              "description": "CAN Central Transmit Status Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 197376,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TS1": {
+                    "description": "When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR).",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TS2": {
+                    "description": "When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, the value read from a reserved bit is not defined.",
+                    "offset": 18,
+                    "size": 14
+                  },
+                  "TBS1": {
+                    "description": "When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR).",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TBS2": {
+                    "description": "When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR).",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TCS1": {
+                    "description": "When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR).",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TCS2": {
+                    "description": "When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR).",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RXSR": {
+              "description": "CAN Central Receive Status Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RS1": {
+                    "description": "When 1, CAN1 is receiving a message (same as RS in CAN1GSR).",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RS2": {
+                    "description": "When 1, CAN2 is receiving a message (same as RS in CAN2GSR).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, the value read from a reserved bit is not defined.",
+                    "offset": 18,
+                    "size": 14
+                  },
+                  "RB1": {
+                    "description": "When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR).",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RB2": {
+                    "description": "When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR).",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DOS1": {
+                    "description": "When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR).",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DOS2": {
+                    "description": "When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR).",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MSR": {
+              "description": "CAN Central Miscellaneous Register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "E1": {
+                    "description": "When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "E2": {
+                    "description": "When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, the value read from a reserved bit is not defined.",
+                    "offset": 10,
+                    "size": 22
+                  },
+                  "BS1": {
+                    "description": "When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR).",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BS2": {
+                    "description": "When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR).",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CAN1": {
+        "description": "CAN1 controller ",
+        "children": {
+          "registers": {
+            "MOD": {
+              "description": "Controls the operating mode of the CAN Controller.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "RM": {
+                    "description": "Reset Mode.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL_THE_CAN_CONTR": {
+                            "description": "Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written.",
+                            "value": 0
+                          },
+                          "RESET_CAN_OPERATION": {
+                            "description": "Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOM": {
+                    "description": "Listen Only Mode.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL_THE_CAN_CONT": {
+                            "description": "Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value.",
+                            "value": 0
+                          },
+                          "LISTEN_ONLY_THE_CON": {
+                            "description": "Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STM": {
+                    "description": "Self Test Mode.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL_A_TRANSMITTE": {
+                            "description": "Normal. A transmitted message must be acknowledged to be considered successful.",
+                            "value": 0
+                          },
+                          "SELF_TEST_THE_CONTR": {
+                            "description": "Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TPM": {
+                    "description": "Transmit Priority Mode.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "CAN_ID_THE_TRANSMIT": {
+                            "description": "CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.",
+                            "value": 0
+                          },
+                          "LOCAL_PRIORITY_THE_": {
+                            "description": "Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SM": {
+                    "description": "Sleep Mode.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "WAKE_UP_NORMAL_OPER": {
+                            "description": "Wake-up. Normal operation.",
+                            "value": 0
+                          },
+                          "SLEEP_THE_CAN_CONTR": {
+                            "description": "Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RPM": {
+                    "description": "Receive Polarity Mode.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LOW_ACTIVE_RD_INPUT": {
+                            "description": "Low active. RD input is active Low (dominant bit = 0).",
+                            "value": 0
+                          },
+                          "HIGH_ACTIVE_RD_INPU": {
+                            "description": "High active. RD input is active High (dominant bit = 1) -- reverse polarity.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "TM": {
+                    "description": "Test Mode.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_NORMAL_OPE": {
+                            "description": "Disabled. Normal operation.",
+                            "value": 0
+                          },
+                          "ENABLED_THE_TD_PIN_": {
+                            "description": "Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CMR": {
+              "description": "Command bits that affect the state of the CAN Controller",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TR": {
+                    "description": "Transmission Request.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABSENT_NO_TRANSMISSI": {
+                            "description": "Absent.No transmission request.",
+                            "value": 0
+                          },
+                          "PRESENT_THE_MESSAGE": {
+                            "description": "Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AT": {
+                    "description": "Abort Transmission.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_ACTION_DO_NOT_AB": {
+                            "description": "No action. Do not abort the transmission.",
+                            "value": 0
+                          },
+                          "PRESENT_IF_NOT_ALRE": {
+                            "description": "Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RRB": {
+                    "description": "Release Receive Buffer.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_ACTION_DO_NOT_RE": {
+                            "description": "No action. Do not release the receive buffer.",
+                            "value": 0
+                          },
+                          "RELEASED_THE_INFORM": {
+                            "description": "Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CDO": {
+                    "description": "Clear Data Overrun.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_ACTION_DO_NOT_CL": {
+                            "description": "No action. Do not clear the data overrun bit.",
+                            "value": 0
+                          },
+                          "CLEAR_THE_DATA_OVER": {
+                            "description": "Clear. The Data Overrun bit in Status Register(s) is cleared.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SRR": {
+                    "description": "Self Reception Request.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABSENT_NO_SELF_RECE": {
+                            "description": "Absent. No self reception request.",
+                            "value": 0
+                          },
+                          "PRESENT_THE_MESSAGE": {
+                            "description": "Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STB1": {
+                    "description": "Select Tx Buffer 1.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NOT_SELECTED_TX_BUF": {
+                            "description": "Not selected. Tx Buffer 1 is not selected for transmission.",
+                            "value": 0
+                          },
+                          "SELECTED_TX_BUFFER_": {
+                            "description": "Selected. Tx Buffer 1 is selected for transmission.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STB2": {
+                    "description": "Select Tx Buffer 2.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NOT_SELECTED_TX_BUF": {
+                            "description": "Not selected. Tx Buffer 2 is not selected for transmission.",
+                            "value": 0
+                          },
+                          "SELECTED_TX_BUFFER_": {
+                            "description": "Selected. Tx Buffer 2 is selected for transmission.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STB3": {
+                    "description": "Select Tx Buffer 3.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NOT_SELECTED_TX_BUF": {
+                            "description": "Not selected. Tx Buffer 3 is not selected for transmission.",
+                            "value": 0
+                          },
+                          "SELECTED_TX_BUFFER_": {
+                            "description": "Selected. Tx Buffer 3 is selected for transmission.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "GSR": {
+              "description": "Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 60,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RBS": {
+                    "description": "Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "EMPTY_NO_MESSAGE_IS": {
+                            "description": "Empty. No message is available.",
+                            "value": 0
+                          },
+                          "FULL_AT_LEAST_ONE_C": {
+                            "description": "Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOS": {
+                    "description": "Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABSENT_NO_DATA_OVER": {
+                            "description": "Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset).",
+                            "value": 0
+                          },
+                          "OVERRUN_A_MESSAGE_W": {
+                            "description": "Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TBS": {
+                    "description": "Transmit Buffer Status.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LOCKED_AT_LEAST_ONE": {
+                            "description": "Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s).",
+                            "value": 0
+                          },
+                          "RELEASED_ALL_THREE_": {
+                            "description": "Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TCS": {
+                    "description": "Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INCOMPLETE_AT_LEAST": {
+                            "description": "Incomplete. At least one requested transmission has not been successfully completed yet.",
+                            "value": 0
+                          },
+                          "COMPLETE_ALL_REQUES": {
+                            "description": "Complete. All requested transmission(s) has (have) been successfully completed.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RS": {
+                    "description": "Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "IDLE_THE_CAN_CONTRO": {
+                            "description": "Idle. The CAN controller is idle.",
+                            "value": 0
+                          },
+                          "RECEIVE_THE_CAN_CON": {
+                            "description": "Receive. The CAN controller is receiving a message.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TS": {
+                    "description": "Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "IDLE_THE_CAN_CONTRO": {
+                            "description": "Idle. The CAN controller is idle.",
+                            "value": 0
+                          },
+                          "TRANSMIT_THE_CAN_CO": {
+                            "description": "Transmit. The CAN controller is sending a message.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ES": {
+                    "description": "Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "OK_BOTH_ERROR_COUNT": {
+                            "description": "OK. Both error counters are below the Error Warning Limit.",
+                            "value": 0
+                          },
+                          "ERROR_ONE_OR_BOTH_O": {
+                            "description": "Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BS": {
+                    "description": "Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "BUS_ON_THE_CAN_CONT": {
+                            "description": "Bus-on. The CAN Controller is involved in bus activities",
+                            "value": 0
+                          },
+                          "BUS_OFF_THE_CAN_CON": {
+                            "description": "Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "RXERR": {
+                    "description": "The current value of the Rx Error Counter (an 8-bit value).",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "TXERR": {
+                    "description": "The current value of the Tx Error Counter (an 8-bit value).",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "Interrupt status, Arbitration Lost Capture, Error Code Capture",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RI": {
+                    "description": "Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "Reset",
+                            "value": 0
+                          },
+                          "SET": {
+                            "description": "Set",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TI1": {
+                    "description": "Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "Reset",
+                            "value": 0
+                          },
+                          "SET": {
+                            "description": "Set",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EI": {
+                    "description": "Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "Reset",
+                            "value": 0
+                          },
+                          "SET": {
+                            "description": "Set",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DOI": {
+                    "description": "Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "Reset",
+                            "value": 0
+                          },
+                          "SET": {
+                            "description": "Set",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WUI": {
+                    "description": "Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "Reset",
+                            "value": 0
+                          },
+                          "SET": {
+                            "description": "Set",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EPI": {
+                    "description": "Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "Reset",
+                            "value": 0
+                          },
+                          "SET": {
+                            "description": "Set",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ALI": {
+                    "description": "Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "Reset",
+                            "value": 0
+                          },
+                          "SET": {
+                            "description": "Set",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "BEI": {
+                    "description": "Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "Reset",
+                            "value": 0
+                          },
+                          "SET": {
+                            "description": "Set",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IDI": {
+                    "description": "ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "Reset",
+                            "value": 0
+                          },
+                          "SET": {
+                            "description": "Set",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TI2": {
+                    "description": "Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "Reset",
+                            "value": 0
+                          },
+                          "SET": {
+                            "description": "Set",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TI3": {
+                    "description": "Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RESET": {
+                            "description": "Reset",
+                            "value": 0
+                          },
+                          "SET": {
+                            "description": "Set",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 11,
+                    "size": 5
+                  },
+                  "ERRBIT4_0": {
+                    "description": "Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt.",
+                    "offset": 16,
+                    "size": 5
+                  },
+                  "ERRDIR": {
+                    "description": "When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ERROR_OCCURRED_DURIN": {
+                            "description": "Error occurred during receiving.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERRC1_0": {
+                    "description": "When the CAN controller detects a bus error, the type of error is captured in this field:",
+                    "offset": 22,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "BIT_ERROR": {
+                            "description": "Bit error",
+                            "value": 0
+                          },
+                          "FORM_ERROR": {
+                            "description": "Form error",
+                            "value": 1
+                          },
+                          "STUFF_ERROR": {
+                            "description": "Stuff error",
+                            "value": 2
+                          },
+                          "OTHER_ERROR": {
+                            "description": "Other error",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ALCBIT": {
+                    "description": "Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IER": {
+              "description": "Interrupt Enable",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RIE": {
+                    "description": "Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIE1": {
+                    "description": "Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EIE": {
+                    "description": "Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DOIE": {
+                    "description": "Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "WUIE": {
+                    "description": "Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPIE": {
+                    "description": "Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ALIE": {
+                    "description": "Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BEIE": {
+                    "description": "Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IDIE": {
+                    "description": "ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIE2": {
+                    "description": "Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIE3": {
+                    "description": "Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 11,
+                    "size": 21
+                  }
+                }
+              }
+            },
+            "BTR": {
+              "description": "Bus Timing. Can only be written when RM in CANMOD is 1.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 1835008,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BRP": {
+                    "description": "Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "SJW": {
+                    "description": "The Synchronization Jump Width is (this value plus one) CAN clocks.",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "TESG1": {
+                    "description": "The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks.",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "TESG2": {
+                    "description": "The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks.",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "SAM": {
+                    "description": "Sampling",
+                    "offset": 23,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_BUS_IS_SAMPLED_O": {
+                            "description": "The bus is sampled once (recommended for high speed buses)",
+                            "value": 0
+                          },
+                          "THE_BUS_IS_SAMPLED_3": {
+                            "description": "The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "EWL": {
+              "description": "Error Warning Limit. Can only be written when RM in CANMOD is 1.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 96,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EWL": {
+                    "description": "During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status Register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 3947580,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RBS_1": {
+                    "description": "Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DOS_1": {
+                    "description": "Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TBS1_1": {
+                    "description": "Transmit Buffer Status 1.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LOCKED_SOFTWARE_CAN": {
+                            "description": "Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.",
+                            "value": 0
+                          },
+                          "RELEASED_SOFTWARE_M": {
+                            "description": "Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TCS1_1": {
+                    "description": "Transmission Complete Status.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INCOMPLETE_THE_PREV": {
+                            "description": "Incomplete. The previously requested transmission for Tx Buffer 1 is not complete.",
+                            "value": 0
+                          },
+                          "COMPLETE_THE_PREVIO": {
+                            "description": "Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RS_1": {
+                    "description": "Receive Status. This bit is identical to the RS bit in the GSR.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TS1_1": {
+                    "description": "Transmit Status 1.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "IDLE_THERE_IS_NO_TR": {
+                            "description": "Idle. There is no transmission from Tx Buffer 1.",
+                            "value": 0
+                          },
+                          "TRANSMIT_THE_CAN_CO": {
+                            "description": "Transmit. The CAN Controller is transmitting a message from Tx Buffer 1.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ES_1": {
+                    "description": "Error Status. This bit is identical to the ES bit in the CANxGSR.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BS_1": {
+                    "description": "Bus Status. This bit is identical to the BS bit in the CANxGSR.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RBS_2": {
+                    "description": "Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DOS_2": {
+                    "description": "Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TBS2_2": {
+                    "description": "Transmit Buffer Status 2.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LOCKED_SOFTWARE_CAN": {
+                            "description": "Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.",
+                            "value": 0
+                          },
+                          "RELEASED_SOFTWARE_M": {
+                            "description": "Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TCS2_2": {
+                    "description": "Transmission Complete Status.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INCOMPLETE_THE_PREV": {
+                            "description": "Incomplete. The previously requested transmission for Tx Buffer 2 is not complete.",
+                            "value": 0
+                          },
+                          "COMPLETE_THE_PREVIO": {
+                            "description": "Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RS_2": {
+                    "description": "Receive Status. This bit is identical to the RS bit in the GSR.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TS2_2": {
+                    "description": "Transmit Status 2.",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "IDLE_THERE_IS_NO_TR": {
+                            "description": "Idle. There is no transmission from Tx Buffer 2.",
+                            "value": 0
+                          },
+                          "TRANSMIT_THE_CAN_CO": {
+                            "description": "Transmit. The CAN Controller is transmitting a message from Tx Buffer 2.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ES_2": {
+                    "description": "Error Status. This bit is identical to the ES bit in the CANxGSR.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BS_2": {
+                    "description": "Bus Status. This bit is identical to the BS bit in the CANxGSR.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RBS_3": {
+                    "description": "Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DOS_3": {
+                    "description": "Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TBS3_3": {
+                    "description": "Transmit Buffer Status 3.",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LOCKED_SOFTWARE_CAN": {
+                            "description": "Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.",
+                            "value": 0
+                          },
+                          "RELEASED_SOFTWARE_M": {
+                            "description": "Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TCS3_3": {
+                    "description": "Transmission Complete Status.",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INCOMPLETE_THE_PREV": {
+                            "description": "Incomplete. The previously requested transmission for Tx Buffer 3 is not complete.",
+                            "value": 0
+                          },
+                          "COMPLETE_THE_PREVIO": {
+                            "description": "Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RS_3": {
+                    "description": "Receive Status. This bit is identical to the RS bit in the GSR.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TS3_3": {
+                    "description": "Transmit Status 3.",
+                    "offset": 21,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "IDLE_THERE_IS_NO_TR": {
+                            "description": "Idle. There is no transmission from Tx Buffer 3.",
+                            "value": 0
+                          },
+                          "TRANSMIT_THE_CAN_CO": {
+                            "description": "Transmit. The CAN Controller is transmitting a message from Tx Buffer 3.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ES_3": {
+                    "description": "Error Status. This bit is identical to the ES bit in the CANxGSR.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BS_3": {
+                    "description": "Bus Status. This bit is identical to the BS bit in the CANxGSR.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, the value read from a reserved bit is not defined.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RFS": {
+              "description": "Receive frame status. Can only be written when RM in CANMOD is 1.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IDINDEX": {
+                    "description": "ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "BP": {
+                    "description": "If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DLC": {
+                    "description": "The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding.",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "RTR": {
+                    "description": "This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FF": {
+                    "description": "A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RID": {
+              "description": "Received Identifier. Can only be written when RM in CANMOD is 1.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ID": {
+                    "description": "The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18.",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 11,
+                    "size": 21
+                  }
+                }
+              }
+            },
+            "RDA": {
+              "description": "Received data bytes 1-4. Can only be written when RM in CANMOD is 1.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA1": {
+                    "description": "Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "DATA2": {
+                    "description": "Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA3": {
+                    "description": "Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message.",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA4": {
+                    "description": "Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RDB": {
+              "description": "Received data bytes 5-8. Can only be written when RM in CANMOD is 1.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA5": {
+                    "description": "Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "DATA6": {
+                    "description": "Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DATA7": {
+                    "description": "Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message.",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DATA8": {
+                    "description": "Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USB": {
+        "description": "USB device/host/OTG controller",
+        "children": {
+          "registers": {
+            "INTST": {
+              "description": "OTG Interrupt Status",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TMR": {
+                    "description": "Timer time-out.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "REMOVE_PU": {
+                    "description": "Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HNP_FAILURE": {
+                    "description": "HNP failed. This bit is set by hardware to indicate that the HNP switching has failed.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "HNP_SUCCESS": {
+                    "description": "HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "OTG Interrupt Enable",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TMR_EN": {
+                    "description": "1 = enable the corresponding bit in the IntSt register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "REMOVE_PU_EN": {
+                    "description": "1 = enable the corresponding bit in the IntSt register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HNP_FAILURE_EN": {
+                    "description": "1 = enable the corresponding bit in the IntSt register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "HNP_SUCCES_EN": {
+                    "description": "1 = enable the corresponding bit in the IntSt register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "INTSET": {
+              "description": "OTG Interrupt Set",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TMR_SET": {
+                    "description": "0 = no effect. 1 = set the corresponding bit in the IntSt register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "REMOVE_PU_SET": {
+                    "description": "0 = no effect. 1 = set the corresponding bit in the IntSt register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HNP_FAILURE_SET": {
+                    "description": "0 = no effect. 1 = set the corresponding bit in the IntSt register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "HNP_SUCCES_SET": {
+                    "description": "0 = no effect. 1 = set the corresponding bit in the IntSt register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "INTCLR": {
+              "description": "OTG Interrupt Clear",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TMR_CLR": {
+                    "description": "0 = no effect. 1 = clear the corresponding bit in the IntSt register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "REMOVE_PU_CLR": {
+                    "description": "0 = no effect. 1 = clear the corresponding bit in the IntSt register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HNP_FAILURE_CLR": {
+                    "description": "0 = no effect. 1 = clear the corresponding bit in the IntSt register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "HNP_SUCCES_CLR": {
+                    "description": "0 = no effect. 1 = clear the corresponding bit in the IntSt register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "STCTRL": {
+              "description": "OTG Status and Control and USB port select",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PORT_FUNC": {
+                    "description": "Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "TMR_SCALE": {
+                    "description": "Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "TMR_MODE": {
+                    "description": "Timer mode selection. 0: monoshot 1: free running",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TMR_EN": {
+                    "description": "Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TMR_RST": {
+                    "description": "Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 11,
+                    "size": 5
+                  },
+                  "B_HNP_TRACK": {
+                    "description": "Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "A_HNP_TRACK": {
+                    "description": "Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PU_REMOVED": {
+                    "description": "When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TMR_CNT": {
+                    "description": "Current timer count value.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TMR": {
+              "description": "OTG Timer",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMEOUT_CNT": {
+                    "description": "The TMR interrupt is set when TMR_CNT reaches this value.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DEVINTST": {
+              "description": "USB Device Interrupt Status",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FRAME": {
+                    "description": "The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EP_FAST": {
+                    "description": "Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP_SLOW": {
+                    "description": "Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DEV_STAT": {
+                    "description": "Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CCEMPTY": {
+                    "description": "The command code register (USBCmdCode) is empty (New command can be written).",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CDFULL": {
+                    "description": "Command data register (USBCmdData) is full (Data can be read now).",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RxENDPKT": {
+                    "description": "The current packet in the endpoint buffer is transferred to the CPU.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TxENDPKT": {
+                    "description": "The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen).",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_RLZED": {
+                    "description": "Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ERR_INT": {
+                    "description": "Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 10,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "DEVINTEN": {
+              "description": "USB Device Interrupt Enable",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRAMEEN": {
+                    "description": "0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EP_FASTEN": {
+                    "description": "0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP_SLOWEN": {
+                    "description": "0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DEV_STATEN": {
+                    "description": "0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CCEMPTYEN": {
+                    "description": "0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CDFULLEN": {
+                    "description": "0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RxENDPKTEN": {
+                    "description": "0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TxENDPKTEN": {
+                    "description": "0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_RLZEDEN": {
+                    "description": "0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ERR_INTEN": {
+                    "description": "0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved",
+                    "offset": 10,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "DEVINTCLR": {
+              "description": "USB Device Interrupt Clear",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "FRAMECLR": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EP_FASTCLR": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP_SLOWCLR": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DEV_STATCLR": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CCEMPTYCLR": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CDFULLCLR": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RxENDPKTCLR": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TxENDPKTCLR": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_RLZEDCLR": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ERR_INTCLR": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved",
+                    "offset": 10,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "DEVINTSET": {
+              "description": "USB Device Interrupt Set",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "FRAMESET": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EP_FASTSET": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP_SLOWSET": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DEV_STATSET": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CCEMPTYSET": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CDFULLSET": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RxENDPKTSET": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TxENDPKTSET": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_RLZEDSET": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ERR_INTSET": {
+                    "description": "0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved",
+                    "offset": 10,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "CMDCODE": {
+              "description": "USB Command Code",
+              "offset": 528,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "CMD_PHASE": {
+                    "description": "The command phase:",
+                    "offset": 8,
+                    "size": 8,
+                    "enum": {
+                      "size": 8,
+                      "children": {
+                        "enum_fields": {
+                          "READ": {
+                            "description": "Read",
+                            "value": 2
+                          },
+                          "WRITE": {
+                            "description": "Write",
+                            "value": 1
+                          },
+                          "COMMAND": {
+                            "description": "Command",
+                            "value": 5
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CMD_CODE_WDATA": {
+                    "description": "This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA).",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CMDDATA": {
+              "description": "USB Command Data",
+              "offset": 532,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CMD_RDATA": {
+                    "description": "Command Read Data.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "RXDATA": {
+              "description": "USB Receive Data",
+              "offset": 536,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RX_DATA": {
+                    "description": "Data received.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TXDATA": {
+              "description": "USB Transmit Data",
+              "offset": 540,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TX_DATA": {
+                    "description": "Transmit Data.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RXPLEN": {
+              "description": "USB Receive Packet Length",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PKT_LNGTH": {
+                    "description": "The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DV": {
+                    "description": "Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DATA_IS_INVALID_": {
+                            "description": "Data is invalid.",
+                            "value": 0
+                          },
+                          "DATA_IS_VALID_": {
+                            "description": "Data is valid.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PKT_RDY": {
+                    "description": "The PKT_LNGTH field is valid and the packet is ready for reading.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 12,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "TXPLEN": {
+              "description": "USB Transmit Packet Length",
+              "offset": 548,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "PKT_LNGTH": {
+                    "description": "The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 10,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "CTRL": {
+              "description": "USB Control",
+              "offset": 552,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RD_EN": {
+                    "description": "Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "ENABLED_": {
+                            "description": "Enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "WR_EN": {
+                    "description": "Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "ENABLED_": {
+                            "description": "Enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "LOG_ENDPOINT": {
+                    "description": "Logical Endpoint number.",
+                    "offset": 2,
+                    "size": 4
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "DEVINTPRI": {
+              "description": "USB Device Interrupt Priority",
+              "offset": 556,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "FRAME": {
+                    "description": "Frame interrupt routing",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LP": {
+                            "description": "FRAME interrupt is routed to USB_INT_REQ_LP.",
+                            "value": 0
+                          },
+                          "HP": {
+                            "description": "FRAME interrupt is routed to USB_INT_REQ_HP.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EP_FAST": {
+                    "description": "Fast endpoint interrupt routing",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LP": {
+                            "description": "EP_FAST interrupt is routed to USB_INT_REQ_LP.",
+                            "value": 0
+                          },
+                          "HP": {
+                            "description": "EP_FAST interrupt is routed to USB_INT_REQ_HP.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "EPINTST": {
+              "description": "USB Endpoint Interrupt Status",
+              "offset": 560,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPST0": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPST1": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPST2": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPST3": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPST4": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPST5": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPST6": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPST7": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPST8": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPST9": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPST10": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPST11": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPST12": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPST13": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPST14": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPST15": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPST16": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPST17": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPST18": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPST19": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPST20": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPST21": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPST22": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPST23": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPST24": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPST25": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPST26": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPST27": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPST28": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPST29": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPST30": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPST31": {
+                    "description": "1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EPINTEN": {
+              "description": "USB Endpoint Interrupt Enable",
+              "offset": 564,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPEN0": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPEN1": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPEN2": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPEN3": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPEN4": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPEN5": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPEN6": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPEN7": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPEN8": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPEN9": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPEN10": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPEN11": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPEN12": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPEN13": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPEN14": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPEN15": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPEN16": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPEN17": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPEN18": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPEN19": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPEN20": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPEN21": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPEN22": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPEN23": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPEN24": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPEN25": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPEN26": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPEN27": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPEN28": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPEN29": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPEN30": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPEN31": {
+                    "description": "0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EPINTCLR": {
+              "description": "USB Endpoint Interrupt Clear",
+              "offset": 568,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EPCLR0": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPCLR1": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPCLR2": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPCLR3": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPCLR4": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPCLR5": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPCLR6": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPCLR7": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPCLR8": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPCLR9": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPCLR10": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPCLR11": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPCLR12": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPCLR13": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPCLR14": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPCLR15": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPCLR16": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPCLR17": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPCLR18": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPCLR19": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPCLR20": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPCLR21": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPCLR22": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPCLR23": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPCLR24": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPCLR25": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPCLR26": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPCLR27": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPCLR28": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPCLR29": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPCLR30": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPCLR31": {
+                    "description": "0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EPINTSET": {
+              "description": "USB Endpoint Interrupt Set",
+              "offset": 572,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EPSET0": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPSET1": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPSET2": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPSET3": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPSET4": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPSET5": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPSET6": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPSET7": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPSET8": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPSET9": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPSET10": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPSET11": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPSET12": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPSET13": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPSET14": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPSET15": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPSET16": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPSET17": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPSET18": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPSET19": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPSET20": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPSET21": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPSET22": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPSET23": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPSET24": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPSET25": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPSET26": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPSET27": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPSET28": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPSET29": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPSET30": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPSET31": {
+                    "description": "0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EPINTPRI": {
+              "description": "USB Endpoint Priority",
+              "offset": 576,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EPPRI0": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPPRI1": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPPRI2": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPPRI3": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPPRI4": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPPRI5": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPPRI6": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPPRI7": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPPRI8": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPPRI9": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPPRI10": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPPRI11": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPPRI12": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPPRI13": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPPRI14": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPPRI15": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPPRI16": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPPRI17": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPPRI18": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPPRI19": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPPRI20": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPPRI21": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPPRI22": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPPRI23": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPPRI24": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPPRI25": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPPRI26": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPPRI27": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPPRI28": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPPRI29": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPPRI30": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPPRI31": {
+                    "description": "0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REEP": {
+              "description": "USB Realize Endpoint",
+              "offset": 580,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPR0": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPR1": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPR2": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPR3": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPR4": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPR5": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPR6": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPR7": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPR8": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPR9": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPR10": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPR11": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPR12": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPR13": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPR14": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPR15": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPR16": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPR17": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPR18": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPR19": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPR20": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPR21": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPR22": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPR23": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPR24": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPR25": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPR26": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPR27": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPR28": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPR29": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPR30": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPR31": {
+                    "description": "0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EPIND": {
+              "description": "USB Endpoint Index",
+              "offset": 584,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "PHY_EP": {
+                    "description": "Physical endpoint number (0-31)",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "MAXPSIZE": {
+              "description": "USB MaxPacketSize",
+              "offset": 588,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPS": {
+                    "description": "The maximum packet size value.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 10,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "DMARST": {
+              "description": "USB DMA Request Status",
+              "offset": 592,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPRST0": {
+                    "description": "Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0).",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPRST1": {
+                    "description": "Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPRST2": {
+                    "description": "Endpoint xx (2 <=  xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPRST3": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPRST4": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPRST5": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPRST6": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPRST7": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPRST8": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPRST9": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPRST10": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPRST11": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPRST12": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPRST13": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPRST14": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPRST15": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPRST16": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPRST17": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPRST18": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPRST19": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPRST20": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPRST21": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPRST22": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPRST23": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPRST24": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPRST25": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPRST26": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPRST27": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPRST28": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPRST29": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPRST30": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPRST31": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMARCLR": {
+              "description": "USB DMA Request Clear",
+              "offset": 596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EPRCLR0": {
+                    "description": "Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPRCLR1": {
+                    "description": "Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPRCLR2": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPRCLR3": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPRCLR4": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPRCLR5": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPRCLR6": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPRCLR7": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPRCLR8": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPRCLR9": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPRCLR10": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPRCLR11": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPRCLR12": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPRCLR13": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPRCLR14": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPRCLR15": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPRCLR16": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPRCLR17": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPRCLR18": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPRCLR19": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPRCLR20": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPRCLR21": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPRCLR22": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPRCLR23": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPRCLR24": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPRCLR25": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPRCLR26": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPRCLR27": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPRCLR28": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPRCLR29": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPRCLR30": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPRCLR31": {
+                    "description": "Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMARSET": {
+              "description": "USB DMA Request Set",
+              "offset": 600,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EPRSET0": {
+                    "description": "Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPRSET1": {
+                    "description": "Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPRSET2": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPRSET3": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPRSET4": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPRSET5": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPRSET6": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPRSET7": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPRSET8": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPRSET9": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPRSET10": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPRSET11": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPRSET12": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPRSET13": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPRSET14": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPRSET15": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPRSET16": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPRSET17": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPRSET18": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPRSET19": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPRSET20": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPRSET21": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPRSET22": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPRSET23": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPRSET24": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPRSET25": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPRSET26": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPRSET27": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPRSET28": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPRSET29": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPRSET30": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPRSET31": {
+                    "description": "Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "UDCAH": {
+              "description": "USB UDCA Head",
+              "offset": 640,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries.",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "UDCA_ADDR": {
+                    "description": "Start address of the UDCA.",
+                    "offset": 7,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "EPDMAST": {
+              "description": "USB Endpoint DMA Status",
+              "offset": 644,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EP_DMA_ST0": {
+                    "description": "Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0).",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EP_DMA_ST1": {
+                    "description": "Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP_DMA_ST2": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EP_DMA_ST3": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EP_DMA_ST4": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EP_DMA_ST5": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EP_DMA_ST6": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EP_DMA_ST7": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_DMA_ST8": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_DMA_ST9": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EP_DMA_ST10": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EP_DMA_ST11": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EP_DMA_ST12": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EP_DMA_ST13": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EP_DMA_ST14": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EP_DMA_ST15": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EP_DMA_ST16": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EP_DMA_ST17": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EP_DMA_ST18": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EP_DMA_ST19": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EP_DMA_ST20": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EP_DMA_ST21": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EP_DMA_ST22": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EP_DMA_ST23": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EP_DMA_ST24": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EP_DMA_ST25": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EP_DMA_ST26": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EP_DMA_ST27": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EP_DMA_ST28": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EP_DMA_ST29": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EP_DMA_ST30": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EP_DMA_ST31": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EPDMAEN": {
+              "description": "USB Endpoint DMA Enable",
+              "offset": 648,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EP_DMA_EN0": {
+                    "description": "Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0).",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EP_DMA_EN1": {
+                    "description": "Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP_DMA_EN": {
+                    "description": "Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "EPDMADIS": {
+              "description": "USB Endpoint DMA Disable",
+              "offset": 652,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EP_DMA_DIS0": {
+                    "description": "Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0).",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS1": {
+                    "description": "Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0).",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS2": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS3": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS4": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS5": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS6": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS7": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS8": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS9": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS10": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS11": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS12": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS13": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS14": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS15": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS16": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS17": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS18": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS19": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS20": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS21": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS22": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS23": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS24": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS25": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS26": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS27": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS28": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS29": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS30": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EP_DMA_DIS31": {
+                    "description": "Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMAINTST": {
+              "description": "USB DMA Interrupt Status",
+              "offset": 656,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EOT": {
+                    "description": "End of Transfer Interrupt bit.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ALL_BITS_IN_THE_USBE": {
+                            "description": "All bits in the USBEoTIntSt register are 0.",
+                            "value": 0
+                          },
+                          "AT_LEAST_ONE_BIT_IN_": {
+                            "description": "At least one bit in the USBEoTIntSt is set.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NDDR": {
+                    "description": "New DD Request Interrupt bit.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ALL_BITS_IN_THE_USBN": {
+                            "description": "All bits in the USBNDDRIntSt register are 0.",
+                            "value": 0
+                          },
+                          "AT_LEAST_ONE_BIT_IN_": {
+                            "description": "At least one bit in the USBNDDRIntSt is set.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERR": {
+                    "description": "System Error Interrupt bit.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ALL_BITS_IN_THE_USBS": {
+                            "description": "All bits in the USBSysErrIntSt register are 0.",
+                            "value": 0
+                          },
+                          "AT_LEAST_ONE_BIT_IN_": {
+                            "description": "At least one bit in the USBSysErrIntSt is set.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            },
+            "DMAINTEN": {
+              "description": "USB DMA Interrupt Enable",
+              "offset": 660,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EOT": {
+                    "description": "End of Transfer Interrupt enable bit.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "ENABLED_": {
+                            "description": "Enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NDDR": {
+                    "description": "New DD Request Interrupt enable bit.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "ENABLED_": {
+                            "description": "Enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ERR": {
+                    "description": "System Error Interrupt enable bit.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED_": {
+                            "description": "Disabled.",
+                            "value": 0
+                          },
+                          "ENABLED_": {
+                            "description": "Enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            },
+            "EOTINTST": {
+              "description": "USB End of Transfer Interrupt Status",
+              "offset": 672,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPTXINTST0": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPTXINTST1": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPTXINTST2": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPTXINTST3": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPTXINTST4": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPTXINTST5": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPTXINTST6": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPTXINTST7": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPTXINTST8": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPTXINTST9": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPTXINTST10": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPTXINTST11": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPTXINTST12": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPTXINTST13": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPTXINTST14": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPTXINTST15": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPTXINTST16": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPTXINTST17": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTXINTST18": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPTXINTST19": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPTXINTST20": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTXINTST21": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTXINTST22": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPTXINTST23": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPTXINTST24": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPTXINTST25": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPTXINTST26": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPTXINTST27": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPTXINTST28": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPTXINTST29": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPTXINTST30": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPTXINTST31": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EOTINTCLR": {
+              "description": "USB End of Transfer Interrupt Clear",
+              "offset": 676,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EPTXINTCLR0": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPTXINTCLR1": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPTXINTCLR2": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPTXINTCLR3": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPTXINTCLR4": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPTXINTCLR5": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPTXINTCLR6": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPTXINTCLR7": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPTXINTCLR8": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPTXINTCLR9": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPTXINTCLR10": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPTXINTCLR11": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPTXINTCLR12": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPTXINTCLR13": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPTXINTCLR14": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPTXINTCLR15": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPTXINTCLR16": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPTXINTCLR17": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTXINTCLR18": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPTXINTCLR19": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPTXINTCLR20": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTXINTCLR21": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTXINTCLR22": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPTXINTCLR23": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPTXINTCLR24": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPTXINTCLR25": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPTXINTCLR26": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPTXINTCLR27": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPTXINTCLR28": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPTXINTCLR29": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPTXINTCLR30": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPTXINTCLR31": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EOTINTSET": {
+              "description": "USB End of Transfer Interrupt Set",
+              "offset": 680,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EPTXINTSET0": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPTXINTSET1": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPTXINTSET2": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPTXINTSET3": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPTXINTSET4": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPTXINTSET5": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPTXINTSET6": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPTXINTSET7": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPTXINTSET8": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPTXINTSET9": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPTXINTSET10": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPTXINTSET11": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPTXINTSET12": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPTXINTSET13": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPTXINTSET14": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPTXINTSET15": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPTXINTSET16": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPTXINTSET17": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTXINTSET18": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPTXINTSET19": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPTXINTSET20": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTXINTSET21": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTXINTSET22": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPTXINTSET23": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPTXINTSET24": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPTXINTSET25": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPTXINTSET26": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPTXINTSET27": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPTXINTSET28": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPTXINTSET29": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPTXINTSET30": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPTXINTSET31": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "NDDRINTST": {
+              "description": "USB New DD Request Interrupt Status",
+              "offset": 684,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNDDINTST0": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPNDDINTST1": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPNDDINTST2": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPNDDINTST3": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPNDDINTST4": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPNDDINTST5": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPNDDINTST6": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPNDDINTST7": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPNDDINTST8": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPNDDINTST9": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPNDDINTST10": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPNDDINTST11": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPNDDINTST12": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPNDDINTST13": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPNDDINTST14": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPNDDINTST15": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPNDDINTST16": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPNDDINTST17": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPNDDINTST18": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPNDDINTST19": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPNDDINTST20": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPNDDINTST21": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPNDDINTST22": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPNDDINTST23": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPNDDINTST24": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPNDDINTST25": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPNDDINTST26": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPNDDINTST27": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPNDDINTST28": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPNDDINTST29": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPNDDINTST30": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPNDDINTST31": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "NDDRINTCLR": {
+              "description": "USB New DD Request Interrupt Clear",
+              "offset": 688,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EPNDDINTCLR0": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR1": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR2": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR3": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR4": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR5": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR6": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR7": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR8": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR9": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR10": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR11": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR12": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR13": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR14": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR15": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR16": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR17": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR18": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR19": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR20": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR21": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR22": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR23": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR24": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR25": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR26": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR27": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR28": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR29": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR30": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPNDDINTCLR31": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "NDDRINTSET": {
+              "description": "USB New DD Request Interrupt Set",
+              "offset": 692,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EPNDDINTSET0": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPNDDINTSET1": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPNDDINTSET2": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPNDDINTSET3": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPNDDINTSET4": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPNDDINTSET5": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPNDDINTSET6": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPNDDINTSET7": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPNDDINTSET8": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPNDDINTSET9": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPNDDINTSET10": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPNDDINTSET11": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPNDDINTSET12": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPNDDINTSET13": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPNDDINTSET14": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPNDDINTSET15": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPNDDINTSET16": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPNDDINTSET17": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPNDDINTSET18": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPNDDINTSET19": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPNDDINTSET20": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPNDDINTSET21": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPNDDINTSET22": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPNDDINTSET23": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPNDDINTSET24": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPNDDINTSET25": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPNDDINTSET26": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPNDDINTSET27": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPNDDINTSET28": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPNDDINTSET29": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPNDDINTSET30": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPNDDINTSET31": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SYSERRINTST": {
+              "description": "USB System Error Interrupt Status",
+              "offset": 696,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPERRINTST0": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPERRINTST1": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPERRINTST2": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPERRINTST3": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPERRINTST4": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPERRINTST5": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPERRINTST6": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPERRINTST7": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPERRINTST8": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPERRINTST9": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPERRINTST10": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPERRINTST11": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPERRINTST12": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPERRINTST13": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPERRINTST14": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPERRINTST15": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPERRINTST16": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPERRINTST17": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPERRINTST18": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPERRINTST19": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPERRINTST20": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPERRINTST21": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPERRINTST22": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPERRINTST23": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPERRINTST24": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPERRINTST25": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPERRINTST26": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPERRINTST27": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPERRINTST28": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPERRINTST29": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPERRINTST30": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPERRINTST31": {
+                    "description": "Endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SYSERRINTCLR": {
+              "description": "USB System Error Interrupt Clear",
+              "offset": 700,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EPERRINTCLR0": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPERRINTCLR1": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPERRINTCLR2": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPERRINTCLR3": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPERRINTCLR4": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPERRINTCLR5": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPERRINTCLR6": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPERRINTCLR7": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPERRINTCLR8": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPERRINTCLR9": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPERRINTCLR10": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPERRINTCLR11": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPERRINTCLR12": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPERRINTCLR13": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPERRINTCLR14": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPERRINTCLR15": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPERRINTCLR16": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPERRINTCLR17": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPERRINTCLR18": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPERRINTCLR19": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPERRINTCLR20": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPERRINTCLR21": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPERRINTCLR22": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPERRINTCLR23": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPERRINTCLR24": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPERRINTCLR25": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPERRINTCLR26": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPERRINTCLR27": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPERRINTCLR28": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPERRINTCLR29": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPERRINTCLR30": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPERRINTCLR31": {
+                    "description": "Clear endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SYSERRINTSET": {
+              "description": "USB System Error Interrupt Set",
+              "offset": 704,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "EPERRINTSET0": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPERRINTSET1": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EPERRINTSET2": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EPERRINTSET3": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPERRINTSET4": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EPERRINTSET5": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EPERRINTSET6": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPERRINTSET7": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EPERRINTSET8": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EPERRINTSET9": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EPERRINTSET10": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EPERRINTSET11": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EPERRINTSET12": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EPERRINTSET13": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EPERRINTSET14": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EPERRINTSET15": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EPERRINTSET16": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EPERRINTSET17": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPERRINTSET18": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EPERRINTSET19": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EPERRINTSET20": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPERRINTSET21": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPERRINTSET22": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EPERRINTSET23": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EPERRINTSET24": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPERRINTSET25": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EPERRINTSET26": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EPERRINTSET27": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EPERRINTSET28": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EPERRINTSET29": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EPERRINTSET30": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPERRINTSET31": {
+                    "description": "Set endpoint xx (2 <= xx  <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "I2C_RX": {
+              "description": "I2C Receive",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXDATA": {
+                    "description": "Receive data.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "I2C_WO": {
+              "description": "I2C Transmit",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TXDATA": {
+                    "description": "Transmit data.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "START": {
+                    "description": "When 1, issue a START condition before transmitting this byte.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "When 1, issue a STOP condition after transmitting this byte.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 10,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "I2C_STS": {
+              "description": "I2C Status",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 2560,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TDI": {
+                    "description": "Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NOT_COMPLETE": {
+                            "description": "Transaction has not completed.",
+                            "value": 0
+                          },
+                          "COMPLETE": {
+                            "description": "Transaction completed.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AFI": {
+                    "description": "Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_ARBITRATION_FAILU": {
+                            "description": "No arbitration failure on last transmission.",
+                            "value": 0
+                          },
+                          "ARBITRATION_FAILURE_": {
+                            "description": "Arbitration failure occurred on last transmission.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NAI": {
+                    "description": "No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ACKNOWLEDGE_RCVD": {
+                            "description": "Last transmission received an acknowledge.",
+                            "value": 0
+                          },
+                          "NO_ACKNOWLEDGE_RCVD": {
+                            "description": "Last transmission did not receive an acknowledge.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DRMI": {
+                    "description": "Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "BUSY": {
+                            "description": "Master transmitter does not need data.",
+                            "value": 0
+                          },
+                          "NEED_DATA": {
+                            "description": "Master transmitter needs data.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DRSI": {
+                    "description": "Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "BUSY": {
+                            "description": "Slave transmitter does not need data.",
+                            "value": 0
+                          },
+                          "NEED_DATA": {
+                            "description": "Slave transmitter needs data.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "Active": {
+                    "description": "Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen..",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SCL": {
+                    "description": "The current value of the SCL signal.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SDA": {
+                    "description": "The current value of the SDA signal.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RFF": {
+                    "description": "Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "RX_FIFO_IS_NOT_FULL": {
+                            "description": "RX FIFO is not full",
+                            "value": 0
+                          },
+                          "RX_FIFO_IS_FULL": {
+                            "description": "RX FIFO is full",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RFE": {
+                    "description": "Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DATA": {
+                            "description": "RX FIFO contains data.",
+                            "value": 0
+                          },
+                          "EMPTY": {
+                            "description": "RX FIFO is empty",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TFF": {
+                    "description": "Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TX_FIFO_IS_NOT_FULL_": {
+                            "description": "TX FIFO is not full.",
+                            "value": 0
+                          },
+                          "TX_FIFO_IS_FULL": {
+                            "description": "TX FIFO is full",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TFE": {
+                    "description": "Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "VALID_DATA": {
+                            "description": "TX FIFO contains valid data.",
+                            "value": 0
+                          },
+                          "EMPTY": {
+                            "description": "TX FIFO is empty",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 12,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "I2C_CTL": {
+              "description": "I2C Control",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TDIE": {
+                    "description": "Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_TDI_INTE": {
+                            "description": "Disable the TDI interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_TDI_INTER": {
+                            "description": "Enable the TDI interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AFIE": {
+                    "description": "Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_AFI_": {
+                            "description": "Disable the AFI.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_AFI_": {
+                            "description": "Enable the AFI.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "NAIE": {
+                    "description": "Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_NAI_": {
+                            "description": "Disable the NAI.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_NAI_": {
+                            "description": "Enable the NAI.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DRMIE": {
+                    "description": "Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_DRMI_INT": {
+                            "description": "Disable the DRMI interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_DRMI_INTE": {
+                            "description": "Enable the DRMI interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DRSIE": {
+                    "description": "Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_DRSI_INT": {
+                            "description": "Disable the DRSI interrupt.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_DRSI_INTE": {
+                            "description": "Enable the DRSI interrupt.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "REFIE": {
+                    "description": "Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_RFFI_": {
+                            "description": "Disable the RFFI.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_RFFI_": {
+                            "description": "Enable the RFFI.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RFDAIE": {
+                    "description": "Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_DAI_": {
+                            "description": "Disable the DAI.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_DAI_": {
+                            "description": "Enable the DAI.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TFFIE": {
+                    "description": "Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_TFFI_": {
+                            "description": "Disable the TFFI.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_TFFI_": {
+                            "description": "Enable the TFFI.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SRST": {
+                    "description": "Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NO_RESET": {
+                            "description": "No reset.",
+                            "value": 0
+                          },
+                          "RESET": {
+                            "description": "Reset the I2C to idle state. Self clearing.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 9,
+                    "size": 23
+                  }
+                }
+              }
+            },
+            "I2C_CLKHI": {
+              "description": "I2C Clock High",
+              "offset": 780,
+              "size": 32,
+              "reset_value": 185,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CDHI": {
+                    "description": "Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "I2C_CLKLO": {
+              "description": "I2C Clock Low",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 185,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CDLO": {
+                    "description": "Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "USBCLKCTRL": {
+              "description": "USB Clock Control",
+              "offset": 4084,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 5,
+                    "size": 27
+                  },
+                  "DEV_CLK_EN": {
+                    "description": "Device clock enable.   Enables the usbclk input to the device controller",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PORTSEL_CLK_EN": {
+                    "description": "Port select register clock enable.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "AHB_CLK_EN": {
+                    "description": "AHB clock enable",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTGCLKCTRL": {
+              "description": "OTG clock controller",
+              "offset": 4084,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HOST_CLK_EN": {
+                    "description": "Host clock enable",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_HOST_CLO": {
+                            "description": "Disable the Host clock.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_HOST_CLOC": {
+                            "description": "Enable the Host clock.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DEV_CLK_EN": {
+                    "description": "Device clock enable",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_DEVICE_C": {
+                            "description": "Disable the Device clock.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_DEVICE_CL": {
+                            "description": "Enable the Device clock.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "I2C_CLK_EN": {
+                    "description": "I2C clock enable",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_I2C_CLOC": {
+                            "description": "Disable the I2C clock.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_I2C_CLOCK": {
+                            "description": "Enable the I2C clock.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OTG_CLK_EN": {
+                    "description": "OTG clock enable. In device-only applications, this bit enables access to the PORTSEL register.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_OTG_CLOC": {
+                            "description": "Disable the OTG clock.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_OTG_CLOCK": {
+                            "description": "Enable the OTG clock.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AHB_CLK_EN": {
+                    "description": "AHB master clock enable",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE_THE_AHB_CLOC": {
+                            "description": "Disable the AHB clock.",
+                            "value": 0
+                          },
+                          "ENABLE_THE_AHB_CLOCK": {
+                            "description": "Enable the AHB clock.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "USBCLKST": {
+              "description": "USB Clock Status",
+              "offset": 4088,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 5,
+                    "size": 27
+                  },
+                  "DEV_CLK_ON": {
+                    "description": "Device clock on. The usbclk input to the device controller is active\t.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PORTSEL_CLK_ON": {
+                    "description": "Port select register clock on.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "AHB_CLK_ON": {
+                    "description": "AHB clock on.",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OTGCLKST": {
+              "description": "OTG clock status",
+              "offset": 4088,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HOST_CLK_ON": {
+                    "description": "Host clock status.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "HOST_CLOCK_IS_NOT_AV": {
+                            "description": "Host clock is not available.",
+                            "value": 0
+                          },
+                          "HOST_CLOCK_IS_AVAILA": {
+                            "description": "Host clock is available.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DEV_CLK_ON": {
+                    "description": "Device clock status.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DEVICE_CLOCK_IS_NOT_": {
+                            "description": "Device clock is not available.",
+                            "value": 0
+                          },
+                          "DEVICE_CLOCK_IS_AVAI": {
+                            "description": "Device clock is available.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "I2C_CLK_ON": {
+                    "description": "I2C clock status.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "I2C_CLOCK_IS_NOT_AVA": {
+                            "description": "I2C clock is not available.",
+                            "value": 0
+                          },
+                          "I2C_CLOCK_IS_AVAILAB": {
+                            "description": "I2C clock is available.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OTG_CLK_ON": {
+                    "description": "OTG clock status.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "OTG_CLOCK_IS_NOT_AVA": {
+                            "description": "OTG clock is not available.",
+                            "value": 0
+                          },
+                          "OTG_CLOCK_IS_AVAILAB": {
+                            "description": "OTG clock is available.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AHB_CLK_ON": {
+                    "description": "AHB master clock status.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "AHB_CLOCK_IS_NOT_AVA": {
+                            "description": "AHB clock is not available.",
+                            "value": 0
+                          },
+                          "AHB_CLOCK_IS_AVAILAB": {
+                            "description": "AHB clock is available.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 5,
+                    "size": 27
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPDMA": {
+        "description": "General purpose DMA controller",
+        "children": {
+          "registers": {
+            "INTSTAT": {
+              "description": "DMA Interrupt Status Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INTSTAT0": {
+                    "description": "Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "INTSTAT1": {
+                    "description": "Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INTSTAT2": {
+                    "description": "Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "INTSTAT3": {
+                    "description": "Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "INTSTAT4": {
+                    "description": "Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INTSTAT5": {
+                    "description": "Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INTSTAT6": {
+                    "description": "Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "INTSTAT7": {
+                    "description": "Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "INTTCSTAT": {
+              "description": "DMA Interrupt Terminal Count Request Status Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INTTCSTAT0": {
+                    "description": "Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "INTTCSTAT1": {
+                    "description": "Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INTTCSTAT2": {
+                    "description": "Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "INTTCSTAT3": {
+                    "description": "Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "INTTCSTAT4": {
+                    "description": "Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INTTCSTAT5": {
+                    "description": "Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INTTCSTAT6": {
+                    "description": "Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "INTTCSTAT7": {
+                    "description": "Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "INTTCCLEAR": {
+              "description": "DMA Interrupt Terminal Count Request Clear Register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "INTTCCLEAR0": {
+                    "description": "Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "INTTCCLEAR1": {
+                    "description": "Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INTTCCLEAR2": {
+                    "description": "Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "INTTCCLEAR3": {
+                    "description": "Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "INTTCCLEAR4": {
+                    "description": "Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INTTCCLEAR5": {
+                    "description": "Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INTTCCLEAR6": {
+                    "description": "Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "INTTCCLEAR7": {
+                    "description": "Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "INTERRSTAT": {
+              "description": "DMA Interrupt Error Status Register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INTERRSTAT0": {
+                    "description": "Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "INTERRSTAT1": {
+                    "description": "Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INTERRSTAT2": {
+                    "description": "Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "INTERRSTAT3": {
+                    "description": "Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "INTERRSTAT4": {
+                    "description": "Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INTERRSTAT5": {
+                    "description": "Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INTERRSTAT6": {
+                    "description": "Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "INTERRSTAT7": {
+                    "description": "Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "INTERRCLR": {
+              "description": "DMA Interrupt Error Clear Register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "INTERRCLR0": {
+                    "description": "Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "INTERRCLR1": {
+                    "description": "Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INTERRCLR2": {
+                    "description": "Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "INTERRCLR3": {
+                    "description": "Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "INTERRCLR4": {
+                    "description": "Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INTERRCLR5": {
+                    "description": "Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INTERRCLR6": {
+                    "description": "Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "INTERRCLR7": {
+                    "description": "Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "RAWINTTCSTAT": {
+              "description": "DMA Raw Interrupt Terminal Count Status Register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RAWINTTCSTAT0": {
+                    "description": "Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RAWINTTCSTAT1": {
+                    "description": "Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RAWINTTCSTAT2": {
+                    "description": "Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RAWINTTCSTAT3": {
+                    "description": "Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RAWINTTCSTAT4": {
+                    "description": "Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RAWINTTCSTAT5": {
+                    "description": "Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RAWINTTCSTAT6": {
+                    "description": "Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RAWINTTCSTAT7": {
+                    "description": "Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "RAWINTERRSTAT": {
+              "description": "DMA Raw Error Interrupt Status Register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RAWINTERRSTAT0": {
+                    "description": "Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RAWINTERRSTAT1": {
+                    "description": "Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RAWINTERRSTAT2": {
+                    "description": "Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RAWINTERRSTAT3": {
+                    "description": "Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RAWINTERRSTAT4": {
+                    "description": "Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RAWINTERRSTAT5": {
+                    "description": "Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RAWINTERRSTAT6": {
+                    "description": "Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RAWINTERRSTAT7": {
+                    "description": "Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "ENBLDCHNS": {
+              "description": "DMA Enabled Channel Register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ENABLEDCHANNELS0": {
+                    "description": "Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ENABLEDCHANNELS1": {
+                    "description": "Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ENABLEDCHANNELS2": {
+                    "description": "Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ENABLEDCHANNELS3": {
+                    "description": "Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ENABLEDCHANNELS4": {
+                    "description": "Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ENABLEDCHANNELS5": {
+                    "description": "Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ENABLEDCHANNELS6": {
+                    "description": "Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ENABLEDCHANNELS7": {
+                    "description": "Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "SOFTBREQ": {
+              "description": "DMA Software Burst Request Register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SOFTBREQ0": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SOFTBREQ1": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SOFTBREQ2": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SOFTBREQ3": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SOFTBREQ4": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SOFTBREQ5": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SOFTBREQ6": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SOFTBREQ7": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SOFTBREQ8": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SOFTBREQ9": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SOFTBREQ10": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SOFTBREQ11": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SOFTBREQ12": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SOFTBREQ13": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SOFTBREQ14": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SOFTBREQ15": {
+                    "description": "Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SOFTSREQ": {
+              "description": "DMA Software Single Request Register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SOFTSREQ0": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SOFTSREQ1": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SOFTSREQ2": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SOFTSREQ3": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SOFTSREQ4": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SOFTSREQ5": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SOFTSREQ6": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SOFTSREQ7": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SOFTSREQ8": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SOFTSREQ9": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SOFTSREQ10": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SOFTSREQ11": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SOFTSREQ12": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SOFTSREQ13": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SOFTSREQ14": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SOFTSREQ15": {
+                    "description": "Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read undefined. Write reserved bits as zero.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SOFTLBREQ": {
+              "description": "DMA Software Last Burst Request Register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SOFTLBREQ0": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SOFTLBREQ1": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SOFTLBREQ2": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SOFTLBREQ3": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SOFTLBREQ4": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SOFTLBREQ5": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SOFTLBREQ6": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SOFTLBREQ7": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SOFTLBREQ8": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SOFTLBREQ9": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SOFTLBREQ10": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SOFTLBREQ11": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SOFTLBREQ12": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SOFTLBREQ13": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SOFTLBREQ14": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SOFTLBREQ15": {
+                    "description": "Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SOFTLSREQ": {
+              "description": "DMA Software Last Single Request Register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SOFTLSREQ0": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SOFTLSREQ1": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SOFTLSREQ2": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SOFTLSREQ3": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SOFTLSREQ4": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SOFTLSREQ5": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SOFTLSREQ6": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SOFTLSREQ7": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SOFTLSREQ8": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SOFTLSREQ9": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SOFTLSREQ10": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SOFTLSREQ11": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SOFTLSREQ12": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SOFTLSREQ13": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SOFTLSREQ14": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SOFTLSREQ15": {
+                    "description": "Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CONFIG": {
+              "description": "DMA Configuration Register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "E": {
+                    "description": "DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "M": {
+                    "description": "AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "SYNC": {
+              "description": "DMA Synchronization Register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMACSYNC0": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMACSYNC1": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DMACSYNC2": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMACSYNC3": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DMACSYNC4": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DMACSYNC5": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DMACSYNC6": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DMACSYNC7": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DMACSYNC8": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DMACSYNC9": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DMACSYNC10": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DMACSYNC11": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DMACSYNC12": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DMACSYNC13": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "DMACSYNC14": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "DMACSYNC15": {
+                    "description": "Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EMAC": {
+        "description": "Ethernet",
+        "children": {
+          "registers": {
+            "MAC1": {
+              "description": "MAC configuration register 1.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXENABLE": {
+                    "description": "RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PARF": {
+                    "description": "PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXFLOWCTRL": {
+                    "description": "RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXFLOWCTRL": {
+                    "description": "TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LOOPBACK": {
+                    "description": "Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "RESETTX": {
+                    "description": "Setting this bit will put the Transmit Function logic in reset.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RESETMCSTX": {
+                    "description": "Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESETRX": {
+                    "description": "Setting this bit will put the Ethernet receive logic in reset.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RESETMCSRX": {
+                    "description": "Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SIMRESET": {
+                    "description": "SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SOFTRESET": {
+                    "description": "SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface.",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MAC2": {
+              "description": "MAC configuration register 2.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FULLDUPLEX": {
+                    "description": "When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FLC": {
+                    "description": "FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HFEN": {
+                    "description": "HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DELAYEDCRC": {
+                    "description": "DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CRCEN": {
+                    "description": "CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PADCRCEN": {
+                    "description": "PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "VLANPADEN": {
+                    "description": "VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AUTODETPADEN": {
+                    "description": "AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PPENF": {
+                    "description": "PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LPENF": {
+                    "description": "LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 15,
+                    "size": 17
+                  },
+                  "NOBACKOFF": {
+                    "description": "When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BP_NOBACKOFF": {
+                    "description": "BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EXCESSDEFER": {
+                    "description": "When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached.",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IPGT": {
+              "description": "Back-to-Back Inter-Packet-Gap register.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BTOBINTEGAP": {
+                    "description": "BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode).",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 7,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "IPGR": {
+              "description": "Non Back-to-Back Inter-Packet-Gap register.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NBTOBINTEGAP2": {
+                    "description": "NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode).",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 15,
+                    "size": 17
+                  },
+                  "NBTOBINTEGAP1": {
+                    "description": "NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)",
+                    "offset": 8,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "CLRT": {
+              "description": "Collision window / Retry register.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 14095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RETRANSMAX": {
+                    "description": "RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 14,
+                    "size": 18
+                  },
+                  "COLLWIN": {
+                    "description": "COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD.",
+                    "offset": 8,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "MAXF": {
+              "description": "Maximum Frame register.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 1536,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAXFLEN": {
+                    "description": "MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SUPP": {
+              "description": "PHY Support register.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 9,
+                    "size": 23
+                  },
+                  "SPEED": {
+                    "description": "This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TEST": {
+              "description": "Test register.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCPQ": {
+                    "description": "SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TESTPAUSE": {
+                    "description": "This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TESTBP": {
+                    "description": "TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            },
+            "MCFG": {
+              "description": "MII Mgmt Configuration register.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCANINC": {
+                    "description": "SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SUPPPREAMBLE": {
+                    "description": "SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CLOCKSEL": {
+                    "description": "CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field.",
+                    "offset": 2,
+                    "size": 4
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "RESETMIIMGMT": {
+                    "description": "RESET MII MGMT. This bit resets the MII Management hardware.",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MCMD": {
+              "description": "MII Mgmt Command register.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ": {
+                    "description": "This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data).",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SCAN": {
+                    "description": "This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "MADR": {
+              "description": "MII Mgmt Address register.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGADDR": {
+                    "description": "REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed.",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 13,
+                    "size": 19
+                  },
+                  "PHYADDR": {
+                    "description": "PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved).",
+                    "offset": 8,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "MWTD": {
+              "description": "MII Mgmt Write Data register.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "WRITEDATA": {
+                    "description": "WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR).",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "MRDD": {
+              "description": "MII Mgmt Read Data register.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "READDATA": {
+                    "description": "READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "MIND": {
+              "description": "MII Mgmt Indicators register.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "BUSY": {
+                    "description": "When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SCANNING": {
+                    "description": "When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "NOTVALID": {
+                    "description": "When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MIILINKFAIL": {
+                    "description": "When 1 is returned - indicates that an MII Mgmt link fail has occurred.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "SA0": {
+              "description": "Station Address 0 register.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SADDR2": {
+                    "description": "STATION ADDRESS, 2nd octet. This field holds the second octet of the station address.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SADDR1": {
+                    "description": "STATION ADDRESS, 1st octet. This field holds the first octet of the station address.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SA1": {
+              "description": "Station Address 1 register.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SADDR4": {
+                    "description": "STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SADDR3": {
+                    "description": "STATION ADDRESS, 3rd octet. This field holds the third octet of the station address.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SA2": {
+              "description": "Station Address 2 register.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SADDR6": {
+                    "description": "STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SADDR5": {
+                    "description": "STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "COMMAND": {
+              "description": "Command register.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXENABLE": {
+                    "description": "Enable receive.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXENABLE": {
+                    "description": "Enable transmit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 11,
+                    "size": 21
+                  },
+                  "REGRESET": {
+                    "description": "When a  1  is written, all datapaths and the host registers are reset. The MAC needs to be reset separately.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXRESET": {
+                    "description": "When a  1  is written, the transmit datapath is reset.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RXRESET": {
+                    "description": "When a  1  is written, the receive datapath is reset.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PASSRUNTFRAME": {
+                    "description": "When set to  1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PASSRXFILTER": {
+                    "description": "When set to  1 , disables receive filtering i.e. all frames received are written to memory.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TXFLOWCONTROL": {
+                    "description": "Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RMII": {
+                    "description": "When set to  1 , RMII mode is selected; if 0, MII mode is selected.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FULLDUPLEX": {
+                    "description": "When set to  1 , indicates full duplex operation.",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Status register.",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXSTATUS": {
+                    "description": "If 1, the receive channel is active. If 0, the receive channel is inactive.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXSTATUS": {
+                    "description": "If 1, the transmit channel is active. If 0, the transmit channel is inactive.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "RXDESCRIPTOR": {
+              "description": "Receive descriptor base address register.",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Fixed to 00",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "RXDESCRIPTOR": {
+                    "description": "MSBs of receive descriptor base address.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "RXSTATUS": {
+              "description": "Receive status base address register.",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Fixed to 000",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "RXSTATUS": {
+                    "description": "MSBs of receive status base address.",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            },
+            "RXDESCRIPTORNUMBER": {
+              "description": "Receive number of descriptors register.",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXDESCRIPTORN": {
+                    "description": "RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RXPRODUCEINDEX": {
+              "description": "Receive produce index register.",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXPRODUCEIX": {
+                    "description": "Index of the descriptor that is going to be filled next by the receive datapath.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RXCONSUMEINDEX": {
+              "description": "Receive consume index register.",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXCONSUMEIX": {
+                    "description": "Index of the descriptor that is going to be processed next by the receive",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TXDESCRIPTOR": {
+              "description": "Transmit descriptor base address register.",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Fixed to 00",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "TXD": {
+                    "description": "TxDescriptor. MSBs of transmit descriptor base address.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "TXSTATUS": {
+              "description": "Transmit status base address register.",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Fixed to 00",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "TXSTAT": {
+                    "description": "TxStatus. MSBs of transmit status base address.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "TXDESCRIPTORNUMBER": {
+              "description": "Transmit number of descriptors register.",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXDN": {
+                    "description": "TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TXPRODUCEINDEX": {
+              "description": "Transmit produce index register.",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXPI": {
+                    "description": "TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TXCONSUMEINDEX": {
+              "description": "Transmit consume index register.",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TXCI": {
+                    "description": "TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TSV0": {
+              "description": "Transmit status vector 0 register.",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CRCERR": {
+                    "description": "CRC error. The attached CRC in the packet did not match the internally generated CRC.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LCE": {
+                    "description": "Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LOR": {
+                    "description": "Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the \"Length out of range\" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DONE": {
+                    "description": "Transmission of packet was completed.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MULTICAST": {
+                    "description": "Packet's destination was a multicast address.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BROADCAST": {
+                    "description": "Packet's destination was a broadcast address.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PACKETDEFER": {
+                    "description": "Packet was deferred for at least one attempt, but less than an excessive defer.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EXDF": {
+                    "description": "Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EXCOL": {
+                    "description": "Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LCOL": {
+                    "description": "Late Collision. Collision occurred beyond collision window, 512 bit times.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GIANT": {
+                    "description": "Byte count in frame was greater than can be represented in the transmit byte count field in TSV1.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "UNDERRUN": {
+                    "description": "Host side caused buffer underrun.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TOTALBYTES": {
+                    "description": "The total number of bytes transferred including collided attempts.",
+                    "offset": 12,
+                    "size": 16
+                  },
+                  "CONTROLFRAME": {
+                    "description": "The frame was a control frame.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "PAUSE": {
+                    "description": "The frame was a control frame with a valid PAUSE opcode.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BACKPRESSURE": {
+                    "description": "Carrier-sense method backpressure was previously applied.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "VLAN": {
+                    "description": "Frame's length/type field contained 0x8100 which is the VLAN protocol identifier.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TSV1": {
+              "description": "Transmit status vector 1 register.",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TBC": {
+                    "description": "Transmit byte count. The total number of bytes in the frame, not counting the collided bytes.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "TCC": {
+                    "description": "Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented.",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 20,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "RSV": {
+              "description": "Receive status vector register.",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RBC": {
+                    "description": "Received byte count. Indicates length of received frame.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PPI": {
+                    "description": "Packet previously ignored. Indicates that a packet was dropped.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RXDVSEEN": {
+                    "description": "RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "CESEEN": {
+                    "description": "Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RCV": {
+                    "description": "Receive code violation. Indicates that received PHY data does not represent a valid receive code.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "CRCERR": {
+                    "description": "CRC error. The attached CRC in the packet did not match the internally generated CRC.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "LCERR": {
+                    "description": "Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "LOR": {
+                    "description": "Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the \"Length out of range\" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "ROK": {
+                    "description": "Receive OK. The packet had valid CRC and no symbol errors.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "MULTICAST": {
+                    "description": "The packet destination was a multicast address.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BROADCAST": {
+                    "description": "The packet destination was a broadcast address.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DRIBBLENIBBLE": {
+                    "description": "Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CONTROLFRAME": {
+                    "description": "The frame was a control frame.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PAUSE": {
+                    "description": "The frame was a control frame with a valid PAUSE opcode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "UO": {
+                    "description": "Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "VLAN": {
+                    "description": "Frame's length/type field contained 0x8100 which is the VLAN protocol identifier.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FLOWCONTROLCOUNTER": {
+              "description": "Flow control counter register.",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MC": {
+                    "description": "MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "PT": {
+                    "description": "PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "FLOWCONTROLSTATUS": {
+              "description": "Flow control status register.",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "MCC": {
+                    "description": "MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RXFILTERCTRL": {
+              "description": "Receive filter control register.",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AUE": {
+                    "description": "AcceptUnicastEn. When set to 1, all unicast frames are accepted.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ABE": {
+                    "description": "AcceptBroadcastEn. When set to 1, all broadcast frames are accepted.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AME": {
+                    "description": "AcceptMulticastEn. When set to 1, all multicast frames are accepted.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "AUHE": {
+                    "description": "AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "AMHE": {
+                    "description": "AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "APE": {
+                    "description": "AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 14,
+                    "size": 18
+                  },
+                  "MPEW": {
+                    "description": "MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RFEW": {
+                    "description": "RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match.",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RXFILTERWOLSTATUS": {
+              "description": "Receive filter WoL status register.",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "AUW": {
+                    "description": "AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ABW": {
+                    "description": "AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AMW": {
+                    "description": "AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "AUHW": {
+                    "description": "AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "AMHW": {
+                    "description": "AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "APW": {
+                    "description": "AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 9,
+                    "size": 23
+                  },
+                  "RFW": {
+                    "description": "RxFilterWoL. When the value is 1, the receive filter caused WoL.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MPW": {
+                    "description": "MagicPacketWoL. When the value is 1, the magic packet filter caused WoL.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RXFILTERWOLCLEAR": {
+              "description": "Receive filter WoL clear register.",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "AUWCLR": {
+                    "description": "AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ABWCLR": {
+                    "description": "AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AMWCLR": {
+                    "description": "AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "AUHWCLR": {
+                    "description": "AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "AMHWCLR": {
+                    "description": "AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "APWCLR": {
+                    "description": "AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 9,
+                    "size": 23
+                  },
+                  "RFWCLR": {
+                    "description": "RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MPWCLR": {
+                    "description": "MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HASHFILTERL": {
+              "description": "Hash filter table LSBs register.",
+              "offset": 528,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HFL": {
+                    "description": "HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HASHFILTERH": {
+              "description": "Hash filter table MSBs register.",
+              "offset": 532,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HFH": {
+                    "description": "Bits 63:32 of the imperfect filter hash table for receive filtering.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "INTSTATUS": {
+              "description": "Interrupt status register.",
+              "offset": 4064,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RXOVERRUNINT": {
+                    "description": "Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RXERRORINT": {
+                    "description": "Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXFINISHEDINT": {
+                    "description": "Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RXDONEINT": {
+                    "description": "Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXUNDERRUNINT": {
+                    "description": "Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TXERRORINT": {
+                    "description": "Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFINISHEDINT": {
+                    "description": "Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXDONEINT": {
+                    "description": "Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 14,
+                    "size": 18
+                  },
+                  "SOFTINT": {
+                    "description": "Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAKEUPINT": {
+                    "description": "Interrupt triggered by a Wake-up event detected by the receive filter.",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTENABLE": {
+              "description": "Interrupt enable register.",
+              "offset": 4068,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXOVERRUNINTEN": {
+                    "description": "Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RXERRORINTEN": {
+                    "description": "Enable for interrupt trigger on receive errors.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXFINISHEDINTEN": {
+                    "description": "Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RXDONEINTEN": {
+                    "description": "Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXUNDERRUNINTEN": {
+                    "description": "Enable for interrupt trigger on transmit buffer or descriptor underrun situations.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TXERRORINTEN": {
+                    "description": "Enable for interrupt trigger on transmit errors.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFINISHEDINTEN": {
+                    "description": "Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXDONEINTEN": {
+                    "description": "Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 14,
+                    "size": 18
+                  },
+                  "SOFTINTEN": {
+                    "description": "Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAKEUPINTEN": {
+                    "description": "Enable for interrupt triggered by a Wake-up event detected by the receive filter.",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTCLEAR": {
+              "description": "Interrupt clear register.",
+              "offset": 4072,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "RXOVERRUNINTCLR": {
+                    "description": "Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RXERRORINTCLR": {
+                    "description": "Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXFINISHEDINTCLR": {
+                    "description": "Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RXDONEINTCLR": {
+                    "description": "Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXUNDERRUNINTCLR": {
+                    "description": "Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TXERRORINTCLR": {
+                    "description": "Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFINISHEDINTCLR": {
+                    "description": "Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXDONEINTCLR": {
+                    "description": "Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 14,
+                    "size": 18
+                  },
+                  "SOFTINTCLR": {
+                    "description": "Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAKEUPINTCLR": {
+                    "description": "Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTSET": {
+              "description": "Interrupt set register.",
+              "offset": 4076,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "RXOVERRUNINTSET": {
+                    "description": "Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RXERRORINTSET": {
+                    "description": "Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXFINISHEDINTSET": {
+                    "description": "Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RXDONEINTSET": {
+                    "description": "Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TXUNDERRUNINTSET": {
+                    "description": "Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TXERRORINTSET": {
+                    "description": "Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFINISHEDINTSET": {
+                    "description": "Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXDONEINTSET": {
+                    "description": "Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 14,
+                    "size": 18
+                  },
+                  "SOFTINTSET": {
+                    "description": "Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WAKEUPINTSET": {
+                    "description": "Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "POWERDOWN": {
+              "description": "Power-down register.",
+              "offset": 4084,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Unused",
+                    "offset": 0,
+                    "size": 31
+                  },
+                  "PD": {
+                    "description": "PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DAC": {
+        "description": " Digital-to-Analog Converter (DAC) ",
+        "children": {
+          "registers": {
+            "CR": {
+              "description": "D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 17,
+                    "size": 15
+                  },
+                  "VALUE": {
+                    "description": "After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE  x ((VREFP - V REFN)/1024) + VREFN.",
+                    "offset": 6,
+                    "size": 10
+                  },
+                  "BIAS": {
+                    "description": "Settling time  The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "FAST": {
+                            "description": "The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.",
+                            "value": 0
+                          },
+                          "SLOW": {
+                            "description": "The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CTRL": {
+              "description": "DAC Control register. This register controls DMA and timer operation.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INT_DMA_REQ": {
+                    "description": "DMA interrupt request",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "CLEAR_ON_ANY_WRITE_T": {
+                            "description": "Clear on any write to the DACR register.",
+                            "value": 0
+                          },
+                          "SET_BY_HARDWARE_WHEN": {
+                            "description": "Set by hardware when the timer times out.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DBLBUF_ENA": {
+                    "description": "Double buffering",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "ENABLE_WHEN_THIS_BI": {
+                            "description": "Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CNT_ENA": {
+                    "description": "Time-out counter operation",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "ENABLE": {
+                            "description": "Enable",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DMA_ENA": {
+                    "description": "DMA access",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Disable",
+                            "value": 0
+                          },
+                          "ENABLE_DMA_BURST_RE": {
+                            "description": "Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "CNTVAL": {
+              "description": "DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VALUE": {
+                    "description": "16-bit reload value for the DAC interrupt/DMA timer.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RESERVED": {
+                    "description": "Reserved",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SYSCON": {
+        "description": "System and clock control",
+        "children": {
+          "registers": {
+            "FLASHCFG": {
+              "description": "Flash Accelerator Configuration Register. Controls flash access timing.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 12346,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. The value read from a reserved bit is not defined.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FLASHTIM": {
+                    "description": "Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved.",
+                    "offset": 12,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "1CLK": {
+                            "description": "Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock.",
+                            "value": 0
+                          },
+                          "2CLK": {
+                            "description": "Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock.",
+                            "value": 1
+                          },
+                          "3CLK": {
+                            "description": "Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock.",
+                            "value": 2
+                          },
+                          "4CLK": {
+                            "description": "Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock.",
+                            "value": 3
+                          },
+                          "5CLK": {
+                            "description": "Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only.",
+                            "value": 4
+                          },
+                          "6CLK": {
+                            "description": "Flash accesses use 6 CPU clocks. This safe setting will work under any conditions.",
+                            "value": 5
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PLL0CON": {
+              "description": "PLL0 Control Register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PLLE0": {
+                    "description": "PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PLLC0": {
+                    "description": "PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "PLL0CFG": {
+              "description": "PLL0 Configuration Register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MSEL0": {
+                    "description": "PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1.  Note: Not all values of M are needed, and therefore some are not supported by hardware.",
+                    "offset": 0,
+                    "size": 15
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "NSEL0": {
+                    "description": "PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32.",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PLL0STAT": {
+              "description": "PLL0 Status Register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "MSEL0": {
+                    "description": "Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier.",
+                    "offset": 0,
+                    "size": 15
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 27,
+                    "size": 5
+                  },
+                  "NSEL0": {
+                    "description": "Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider.",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "PLLE0_STAT": {
+                    "description": "Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PLLC0_STAT": {
+                    "description": "Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PLOCK0": {
+                    "description": "Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details.",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PLL0FEED": {
+              "description": "PLL0 Feed Register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "PLL0FEED": {
+                    "description": "The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "PLL1CON": {
+              "description": "PLL1 Control Register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PLLE1": {
+                    "description": "PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PLLC1": {
+                    "description": "PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "PLL1CFG": {
+              "description": "PLL1 Configuration Register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MSEL1": {
+                    "description": "PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations.",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "PSEL1": {
+                    "description": "PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations.",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 7,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "PLL1STAT": {
+              "description": "PLL1 Status Register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "MSEL1": {
+                    "description": "Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1.",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "PSEL1": {
+                    "description": "Read-back for the PLL1 Divider value. This is the value currently used by PLL1.",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 11,
+                    "size": 21
+                  },
+                  "PLLE1_STAT": {
+                    "description": "Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PLLC1_STAT": {
+                    "description": "Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PLOCK1": {
+                    "description": "Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency.",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PLL1FEED": {
+              "description": "PLL1 Feed Register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "PLL1FEED": {
+                    "description": "The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "PCON": {
+              "description": "Power Control Register",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PM0": {
+                    "description": "Power mode control bit 0. This bit controls entry to the Power-down mode.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PM1": {
+                    "description": "Power mode control bit 1. This bit controls entry to the Deep Power-down mode.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BODRPM": {
+                    "description": "Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BOGD": {
+                    "description": "Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BORD": {
+                    "description": "Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 12,
+                    "size": 20
+                  },
+                  "SMFLAG": {
+                    "description": "Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DSFLAG": {
+                    "description": "Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PDFLAG": {
+                    "description": "Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DPDFLAG": {
+                    "description": "Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit.",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PCONP": {
+              "description": "Power Control for Peripherals Register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 958,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "PCTIM0": {
+                    "description": "Timer/Counter 0 power/clock control bit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PCTIM1": {
+                    "description": "Timer/Counter 1 power/clock control bit.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PCUART0": {
+                    "description": "UART0 power/clock control bit.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PCUART1": {
+                    "description": "UART1 power/clock control bit.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PCPWM1": {
+                    "description": "PWM1 power/clock control bit.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PCI2C0": {
+                    "description": "The I2C0 interface power/clock control bit.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PCSPI": {
+                    "description": "The SPI interface power/clock control bit.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PCRTC": {
+                    "description": "The RTC power/clock control bit.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PCSSP1": {
+                    "description": "The SSP 1 interface power/clock control bit.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PCADC": {
+                    "description": "A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PCCAN1": {
+                    "description": "CAN Controller 1 power/clock control bit.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PCCAN2": {
+                    "description": "CAN Controller 2 power/clock control bit.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PCGPIO": {
+                    "description": "Power/clock control bit for IOCON, GPIO, and GPIO interrupts.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "PCRIT": {
+                    "description": "Repetitive Interrupt Timer power/clock control bit.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PCMCPWM": {
+                    "description": "Motor Control PWM",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PCQEI": {
+                    "description": "Quadrature Encoder Interface power/clock control bit.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "PCI2C1": {
+                    "description": "The I2C1 interface power/clock control bit.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PCSSP0": {
+                    "description": "The SSP0 interface power/clock control bit.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "PCTIM2": {
+                    "description": "Timer 2 power/clock control bit.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PCTIM3": {
+                    "description": "Timer 3 power/clock control bit.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PCUART2": {
+                    "description": "UART 2 power/clock control bit.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PCUART3": {
+                    "description": "UART 3 power/clock control bit.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PCI2C2": {
+                    "description": "I2C interface 2 power/clock control bit.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PCI2S": {
+                    "description": "I2S interface power/clock control bit.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PCGPDMA": {
+                    "description": "GPDMA function power/clock control bit.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "PCENET": {
+                    "description": "Ethernet block power/clock control bit.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PCUSB": {
+                    "description": "USB interface power/clock control bit.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCLKCFG": {
+              "description": "CPU Clock Configuration Register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCLKSEL": {
+                    "description": "Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "USBCLKCFG": {
+              "description": "USB Clock Configuration Register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USBSEL": {
+                    "description": "Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output.  Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "CLKSRCSEL": {
+              "description": "Clock Source Select Register",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKSRC": {
+                    "description": "Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SELECTS_THE_INTERNAL": {
+                            "description": "Selects the Internal RC oscillator as the PLL0 clock source (default).",
+                            "value": 0
+                          },
+                          "SELECTS_THE_MAIN_OSC": {
+                            "description": "Selects the main oscillator as the PLL0 clock source.  Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s.",
+                            "value": 1
+                          },
+                          "SELECTS_THE_RTC_OSCI": {
+                            "description": "Selects the RTC oscillator as the PLL0 clock source.",
+                            "value": 2
+                          },
+                          "RESERVED": {
+                            "description": "Reserved, do not use this setting.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "CANSLEEPCLR": {
+              "description": "Allows clearing the current CAN channel sleep state as well as reading that state.",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 3,
+                    "size": 29
+                  },
+                  "CAN1SLEEP": {
+                    "description": "Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CAN2SLEEP": {
+                    "description": "Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CANWAKEFLAGS": {
+              "description": "Allows reading the wake-up state of the CAN channels.",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 3,
+                    "size": 29
+                  },
+                  "CAN1WAKE": {
+                    "description": "Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CAN2WAKE": {
+                    "description": "Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EXTINT": {
+              "description": "External Interrupt Flag Register",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EINT0": {
+                    "description": "In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EINT1": {
+                    "description": "In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EINT2": {
+                    "description": "In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EINT3": {
+                    "description": "In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "EXTMODE": {
+              "description": "External Interrupt Mode register",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTMODE0": {
+                    "description": "External interrupt 0 EINT0 mode.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LEVEL_SENSITIVE": {
+                            "description": "Level-sensitive. Level-sensitivity is selected for EINT0.",
+                            "value": 0
+                          },
+                          "EDGE_SENSITIVE": {
+                            "description": "Edge-sensitive. EINT0 is edge sensitive.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EXTMODE1": {
+                    "description": "External interrupt 1 EINT1 mode.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LEVEL_SENSITIVE": {
+                            "description": "Level-sensitive. Level-sensitivity is selected for EINT1.",
+                            "value": 0
+                          },
+                          "EDGE_SENSITIVE": {
+                            "description": "Edge-sensitive. EINT1 is edge sensitive.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EXTMODE2": {
+                    "description": "External interrupt 2 EINT2 mode.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LEVEL_SENSITIVE": {
+                            "description": "Level-sensitive. Level-sensitivity is selected for EINT2.",
+                            "value": 0
+                          },
+                          "EDGE_SENSITIVE": {
+                            "description": "Edge-sensitive. EINT2 is edge sensitive.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EXTMODE3": {
+                    "description": "External interrupt 3 EINT3 mode.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LEVEL_SENSITIVE": {
+                            "description": "Level-sensitive. Level-sensitivity is selected for EINT3.",
+                            "value": 0
+                          },
+                          "EDGE_SENSITIVE": {
+                            "description": "Edge-sensitive. EINT3 is edge sensitive.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "EXTPOLAR": {
+              "description": "External Interrupt Polarity Register",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTPOLAR0": {
+                    "description": "External interrupt 0 EINT0 polarity.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "FALLING_EDGE": {
+                            "description": "Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0).",
+                            "value": 0
+                          },
+                          "RISING_EDGE": {
+                            "description": "Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EXTPOLAR1": {
+                    "description": "External interrupt 1 EINT1 polarity.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "FALLING_EDGE": {
+                            "description": "Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1).",
+                            "value": 0
+                          },
+                          "RISING_EDGE": {
+                            "description": "Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EXTPOLAR2": {
+                    "description": "External interrupt 2 EINT2 polarity.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "FALLING_EDGE": {
+                            "description": "Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2).",
+                            "value": 0
+                          },
+                          "RISING_EDGE": {
+                            "description": "Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "EXTPOLAR3": {
+                    "description": "External interrupt 3 EINT3 polarity.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "FALLING_EDGE": {
+                            "description": "Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3).",
+                            "value": 0
+                          },
+                          "RISING_EDGE": {
+                            "description": "Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3).",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "RSID": {
+              "description": "Reset Source Identification Register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "children": {
+                "fields": {
+                  "POR": {
+                    "description": "Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EXTR": {
+                    "description": "Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WDTR": {
+                    "description": "This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BODR": {
+                    "description": "This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "SCS": {
+              "description": "System control and status",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESERVED": {
+                    "description": "Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 7,
+                    "size": 25
+                  },
+                  "OSCRANGE": {
+                    "description": "Main oscillator range select.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "LOW": {
+                            "description": "Low. The frequency range of the main oscillator is 1 MHz to 20 MHz.",
+                            "value": 0
+                          },
+                          "HIGH": {
+                            "description": "High. The frequency range of the main oscillator is 15 MHz to 25 MHz.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OSCEN": {
+                    "description": "Main oscillator enable.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Disabled. The main oscillator is disabled.",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OSCSTAT": {
+                    "description": "Main oscillator status.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NOT_READY": {
+                            "description": "Not ready. The main oscillator is not ready to be used as a clock source.",
+                            "value": 0
+                          },
+                          "READY": {
+                            "description": "Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PCLKSEL0": {
+              "description": "Peripheral Clock Selection register 0.",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCLK_WDT": {
+                    "description": "Peripheral clock selection for WDT.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_TIMER0": {
+                    "description": "Peripheral clock selection for TIMER0.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_TIMER1": {
+                    "description": "Peripheral clock selection for TIMER1.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_UART0": {
+                    "description": "Peripheral clock selection for UART0.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_UART1": {
+                    "description": "Peripheral clock selection for UART1.",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "PCLK_PWM1": {
+                    "description": "Peripheral clock selection for PWM1.",
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_I2C0": {
+                    "description": "Peripheral clock selection for I2C0.",
+                    "offset": 14,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_SPI": {
+                    "description": "Peripheral clock selection for SPI.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_SSP1": {
+                    "description": "Peripheral clock selection for SSP1.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_DAC": {
+                    "description": "Peripheral clock selection for DAC.",
+                    "offset": 22,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_ADC": {
+                    "description": "Peripheral clock selection for ADC.",
+                    "offset": 24,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_CAN1": {
+                    "description": "Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.",
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_6": {
+                            "description": "CCLK div 6. PCLK_peripheral = CCLK/6.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_CAN2": {
+                    "description": "Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.",
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_6": {
+                            "description": "CCLK div 6. PCLK_peripheral = CCLK/6,",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_ACF": {
+                    "description": "Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.",
+                    "offset": 30,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_6": {
+                            "description": "CCLK div 6. PCLK_peripheral = CCLK/6",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PCLKSEL1": {
+              "description": "Peripheral Clock Selection register 1.",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCLK_QEI": {
+                    "description": "Peripheral clock selection for the Quadrature Encoder Interface.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_GPIOINT": {
+                    "description": "Peripheral clock selection for GPIO interrupts.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_PCB": {
+                    "description": "Peripheral clock selection for the Pin Connect block.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_I2C1": {
+                    "description": "Peripheral clock selection for I2C1.",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "PCLK_SSP0": {
+                    "description": "Peripheral clock selection for SSP0.",
+                    "offset": 10,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_TIMER2": {
+                    "description": "Peripheral clock selection for TIMER2.",
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_TIMER3": {
+                    "description": "Peripheral clock selection for TIMER3.",
+                    "offset": 14,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_UART2": {
+                    "description": "Peripheral clock selection for UART2.",
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_UART3": {
+                    "description": "Peripheral clock selection for UART3.",
+                    "offset": 18,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_I2C2": {
+                    "description": "Peripheral clock selection for I2C2.",
+                    "offset": 20,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_I2S": {
+                    "description": "Peripheral clock selection for I2S.",
+                    "offset": 22,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_RIT": {
+                    "description": "Peripheral clock selection for Repetitive Interrupt Timer.",
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_SYSCON": {
+                    "description": "Peripheral clock selection for the System Control block.",
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PCLK_MC": {
+                    "description": "Peripheral clock selection for the Motor Control PWM.",
+                    "offset": 30,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "CCLK_DIV_4": {
+                            "description": "CCLK div 4. PCLK_peripheral = CCLK/4",
+                            "value": 0
+                          },
+                          "CCLK": {
+                            "description": "CCLK. PCLK_peripheral = CCLK",
+                            "value": 1
+                          },
+                          "CCLK_DIV_2": {
+                            "description": "CCLK div 2. PCLK_peripheral = CCLK/2",
+                            "value": 2
+                          },
+                          "CCLK_DIV_8": {
+                            "description": "CCLK div 8. PCLK_peripheral = CCLK/8",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "USBINTST": {
+              "description": "USB Interrupt Status",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 2147483648,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USB_INT_REQ_LP": {
+                    "description": "Low priority interrupt line status. This bit is read-only.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USB_INT_REQ_HP": {
+                    "description": "High priority interrupt line status. This bit is read-only.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "USB_INT_REQ_DMA": {
+                    "description": "DMA interrupt line status. This bit is read-only.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "USB_HOST_INT": {
+                    "description": "USB host interrupt line status. This bit is read-only.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "USB_ATX_INT": {
+                    "description": "External ATX interrupt line status. This bit is read-only.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "USB_OTG_INT": {
+                    "description": "OTG interrupt line status. This bit is read-only.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USB_I2C_INT": {
+                    "description": "I2C module interrupt line status. This bit is read-only.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 9,
+                    "size": 22
+                  },
+                  "USB_NEED_CLK": {
+                    "description": "USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EN_USB_INTS": {
+                    "description": "Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMACREQSEL": {
+              "description": "Selects between alternative requests on DMA channels 0 through 7 and 10 through 15",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMASEL08": {
+                    "description": "Selects the DMA request for GPDMA input 8: 0 - uart0 tx  1 - Timer 0 match 0 is selected.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMASEL09": {
+                    "description": "Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DMASEL10": {
+                    "description": "Selects the DMA request for GPDMA input 10: 0 - uart1 tx  is selected. 1 - Timer 1 match 0 is selected.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMASEL11": {
+                    "description": "Selects the DMA request for GPDMA input 11: 0 - uart1 rx  is selected. 1 - Timer 1 match 1 is selected.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DMASEL12": {
+                    "description": "Selects the DMA request for GPDMA input 12: 0 - uart2 tx  is selected. 1 - Timer 2 match 0 is selected.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DMASEL13": {
+                    "description": "Selects the DMA request for GPDMA input 13: 0 - uart2 rx  is selected. 1 - Timer 2 match 1 is selected.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DMASEL14": {
+                    "description": "Selects the DMA request for GPDMA input 14: 0 - uart3 tx  is selected. 1 - I2S channel 0 is selected.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DMASEL15": {
+                    "description": "Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "CLKOUTCFG": {
+              "description": "Clock Output Configuration Register",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKOUTSEL": {
+                    "description": "Selects the clock source for the CLKOUT function. Other values are reserved. Do not use.",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "SELECTS_THE_CPU_CLOC": {
+                            "description": "Selects the CPU clock as the CLKOUT source.",
+                            "value": 0
+                          },
+                          "SELECTS_THE_MAIN_OSC": {
+                            "description": "Selects the main oscillator as the CLKOUT source.",
+                            "value": 1
+                          },
+                          "SELECTS_THE_INTERNAL": {
+                            "description": "Selects the Internal RC oscillator as the CLKOUT source.",
+                            "value": 2
+                          },
+                          "SELECTS_THE_USB_CLOC": {
+                            "description": "Selects the USB clock as the CLKOUT source.",
+                            "value": 3
+                          },
+                          "SELECTS_THE_RTC_OSCI": {
+                            "description": "Selects the RTC oscillator as the CLKOUT source.",
+                            "value": 4
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CLKOUTDIV": {
+                    "description": "Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16.",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "CLKOUT_EN": {
+                    "description": "CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CLKOUT_ACT": {
+                    "description": "CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 10,
+                    "size": 22
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "QEI": {
+        "description": "Quadrature Encoder Interface (QEI) ",
+        "children": {
+          "registers": {
+            "CON": {
+              "description": "Control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "RESP": {
+                    "description": "Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RESPI": {
+                    "description": "Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESV": {
+                    "description": "Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RESI": {
+                    "description": "Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "CONF": {
+              "description": "Configuration register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIRINV": {
+                    "description": "Direction invert. When 1, complements the DIR bit.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SIGMODE": {
+                    "description": "Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CAPMODE": {
+                    "description": "Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "INVINX": {
+                    "description": "Invert Index. When 1, inverts the sense of the index input.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CRESPI": {
+                    "description": "Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration).",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 20,
+                    "size": 12
+                  },
+                  "INXGATE": {
+                    "description": "Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index.",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "STAT": {
+              "description": "Status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DIR": {
+                    "description": "Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 1,
+                    "size": 31
+                  }
+                }
+              }
+            },
+            "POS": {
+              "description": "Position register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "POS": {
+                    "description": "Current position value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MAXPOS": {
+              "description": "Maximum position register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAXPOS": {
+                    "description": "Current maximum position value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMPOS0": {
+              "description": "Position compare register 0",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCMP0": {
+                    "description": "Position compare value 0.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMPOS1": {
+              "description": "Position compare register 1",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCMP1": {
+                    "description": "Position compare value 1.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CMPOS2": {
+              "description": "Position compare register 2",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCMP2": {
+                    "description": "Position compare value 2.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "INXCNT": {
+              "description": "Index count register 0",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ENCPOS": {
+                    "description": "Current index counter value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "INXCMP0": {
+              "description": "Index compare register 0",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICMP0": {
+                    "description": "Index compare value 0.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOAD": {
+              "description": "Velocity timer reload register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VELLOAD": {
+                    "description": "Current velocity timer load value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TIME": {
+              "description": "Velocity timer register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "VELVAL": {
+                    "description": "Current velocity timer value.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "VEL": {
+              "description": "Velocity counter register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "VELPC": {
+                    "description": "Current velocity pulse count.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CAP": {
+              "description": "Velocity capture register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "VELCAP": {
+                    "description": "Last velocity capture.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "VELCOMP": {
+              "description": "Velocity compare register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VELPC": {
+                    "description": "Compare velocity pulse count.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FILTER": {
+              "description": "Digital filter register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FILTA": {
+                    "description": "Digital filter sampling delay.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "INTSTAT": {
+              "description": "Interrupt status register",
+              "offset": 4064,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INX_INT": {
+                    "description": "Indicates that an index pulse was detected.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM_INT": {
+                    "description": "Indicates that a velocity timer overflow occurred",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VELC_INT": {
+                    "description": "Indicates that captured velocity is less than compare velocity.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DIR_INT": {
+                    "description": "Indicates that a change of direction was detected.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_INT": {
+                    "description": "Indicates that an encoder phase error was detected.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ENCLK_INT": {
+                    "description": "Indicates that and encoder clock pulse was detected.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "POS0_INT": {
+                    "description": "Indicates that the position 0 compare value is equal to the current position.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "POS1_INT": {
+                    "description": "Indicates that the position 1compare value is equal to the current position.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "POS2_INT": {
+                    "description": "Indicates that the position 2 compare value is equal to the current position.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REV0_INT": {
+                    "description": "Indicates that the index compare 0 value is equal to the current index count.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "POS0REV_INT": {
+                    "description": "Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "POS1REV_INT": {
+                    "description": "Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "POS2REV_INT": {
+                    "description": "Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "REV1_INT": {
+                    "description": "Indicates that the index compare 1value is equal to the current index count.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "REV2_INT": {
+                    "description": "Indicates that the index compare 2 value is equal to the current index count.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MAXPOS_INT": {
+                    "description": "Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SET": {
+              "description": "Interrupt status set register",
+              "offset": 4076,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "INX_INT": {
+                    "description": "Writing a 1 sets the INX_Int bit in QEIINTSTAT.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM_INT": {
+                    "description": "Writing a 1 sets the TIN_Int bit in QEIINTSTAT.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VELC_INT": {
+                    "description": "Writing a 1 sets the VELC_Int bit in QEIINTSTAT.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DIR_INT": {
+                    "description": "Writing a 1 sets the DIR_Int bit in QEIINTSTAT.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_INT": {
+                    "description": "Writing a 1 sets the ERR_Int bit in QEIINTSTAT.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ENCLK_INT": {
+                    "description": "Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "POS0_INT": {
+                    "description": "Writing a 1 sets the POS0_Int bit in QEIINTSTAT.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "POS1_INT": {
+                    "description": "Writing a 1 sets the POS1_Int bit in QEIINTSTAT.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "POS2_INT": {
+                    "description": "Writing a 1 sets the POS2_Int bit in QEIINTSTAT.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REV0_INT": {
+                    "description": "Writing a 1 sets the REV0_Int bit in QEIINTSTAT.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "POS0REV_INT": {
+                    "description": "Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "POS1REV_INT": {
+                    "description": "Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "POS2REV_INT": {
+                    "description": "Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "REV1_INT": {
+                    "description": "Writing a 1 sets the REV1_Int bit in QEIINTSTAT.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "REV2_INT": {
+                    "description": "Writing a 1 sets the REV2_Int bit in QEIINTSTAT.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MAXPOS_INT": {
+                    "description": "Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CLR": {
+              "description": "Interrupt status clear register",
+              "offset": 4072,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "INX_INT": {
+                    "description": "Writing a 1 clears the INX_Int bit in QEIINTSTAT.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM_INT": {
+                    "description": "Writing a 1 clears the TIN_Int bit in QEIINTSTAT.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VELC_INT": {
+                    "description": "Writing a 1 clears the VELC_Int bit in QEIINTSTAT.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DIR_INT": {
+                    "description": "Writing a 1 clears the DIR_Int bit in QEIINTSTAT.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_INT": {
+                    "description": "Writing a 1 clears the ERR_Int bit in QEIINTSTAT.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ENCLK_INT": {
+                    "description": "Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "POS0_INT": {
+                    "description": "Writing a 1 clears the POS0_Int bit in QEIINTSTAT.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "POS1_INT": {
+                    "description": "Writing a 1 clears the POS1_Int bit in QEIINTSTAT.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "POS2_INT": {
+                    "description": "Writing a 1 clears the POS2_Int bit in QEIINTSTAT.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REV0_INT": {
+                    "description": "Writing a 1 clears the REV0_Int bit in QEIINTSTAT.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "POS0REV_INT": {
+                    "description": "Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "POS1REV_INT": {
+                    "description": "Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "POS2REV_INT": {
+                    "description": "Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "REV1_INT": {
+                    "description": "Writing a 1 clears the REV1_Int bit in QEIINTSTAT.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "REV2_INT": {
+                    "description": "Writing a 1 clears the REV2_Int bit in QEIINTSTAT.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MAXPOS_INT": {
+                    "description": "Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IE": {
+              "description": "Interrupt enable register",
+              "offset": 4068,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "INX_INT": {
+                    "description": "When 1, the INX_Int interrupt is enabled.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM_INT": {
+                    "description": "When 1, the TIN_Int interrupt is enabled.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VELC_INT": {
+                    "description": "When 1, the VELC_Int interrupt is enabled.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DIR_INT": {
+                    "description": "When 1, the DIR_Int interrupt is enabled.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_INT": {
+                    "description": "When 1, the ERR_Int interrupt is enabled.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ENCLK_INT": {
+                    "description": "When 1, the ENCLK_Int interrupt is enabled.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "POS0_INT": {
+                    "description": "When 1, the POS0_Int interrupt is enabled.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "POS1_INT": {
+                    "description": "When 1, the POS1_Int interrupt is enabled.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "POS2_INT": {
+                    "description": "When 1, the POS2_Int interrupt is enabled.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REV0_INT": {
+                    "description": "When 1, the REV0_Int interrupt is enabled.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "POS0REV_INT": {
+                    "description": "When 1, the POS0REV_Int interrupt is enabled.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "POS1REV_INT": {
+                    "description": "When 1, the POS1REV_Int interrupt is enabled.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "POS2REV_INT": {
+                    "description": "When 1, the POS2REV_Int interrupt is enabled.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "REV1_INT": {
+                    "description": "When 1, the REV1_Int interrupt is enabled.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "REV2_INT": {
+                    "description": "When 1, the REV2_Int interrupt is enabled.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MAXPOS_INT": {
+                    "description": "When 1, the MAXPOS_Int interrupt is enabled.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IES": {
+              "description": "Interrupt enable set register",
+              "offset": 4060,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "INX_INT": {
+                    "description": "Writing a 1 enables the INX_Int interrupt in the QEIIE register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM_INT": {
+                    "description": "Writing a 1 enables the TIN_Int interrupt in the QEIIE register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VELC_INT": {
+                    "description": "Writing a 1 enables the VELC_Int interrupt in the QEIIE register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DIR_INT": {
+                    "description": "Writing a 1 enables the DIR_Int interrupt in the QEIIE register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_INT": {
+                    "description": "Writing a 1 enables the ERR_Int interrupt in the QEIIE register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ENCLK_INT": {
+                    "description": "Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "POS0_INT": {
+                    "description": "Writing a 1 enables the POS0_Int interrupt in the QEIIE register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "POS1_INT": {
+                    "description": "Writing a 1 enables the POS1_Int interrupt in the QEIIE register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "POS2_INT": {
+                    "description": "Writing a 1 enables the POS2_Int interrupt in the QEIIE register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REV0_INT": {
+                    "description": "Writing a 1 enables the REV0_Int interrupt in the QEIIE register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "POS0REV_INT": {
+                    "description": "Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "POS1REV_INT": {
+                    "description": "Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "POS2REV_INT": {
+                    "description": "Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "REV1_INT": {
+                    "description": "Writing a 1 enables the REV1_Int interrupt in the QEIIE register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "REV2_INT": {
+                    "description": "Writing a 1 enables the REV2_Int interrupt in the QEIIE register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MAXPOS_INT": {
+                    "description": "Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IEC": {
+              "description": "Interrupt enable clear register",
+              "offset": 4056,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "INX_INT": {
+                    "description": "Writing a 1 disables the INX_Int interrupt in the QEIIE register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIM_INT": {
+                    "description": "Writing a 1 disables the TIN_Int interrupt in the QEIIE register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VELC_INT": {
+                    "description": "Writing a 1 disables the VELC_Int interrupt in the QEIIE register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DIR_INT": {
+                    "description": "Writing a 1 disables the DIR_Int interrupt in the QEIIE register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_INT": {
+                    "description": "Writing a 1 disables the ERR_Int interrupt in the QEIIE register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ENCLK_INT": {
+                    "description": "Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "POS0_INT": {
+                    "description": "Writing a 1 disables the POS0_Int interrupt in the QEIIE register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "POS1_INT": {
+                    "description": "Writing a 1 disables the POS1_Int interrupt in the QEIIE register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "POS2_INT": {
+                    "description": "Writing a 1 disables the POS2_Int interrupt in the QEIIE register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REV0_INT": {
+                    "description": "Writing a 1 disables the REV0_Int interrupt in the QEIIE register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "POS0REV_INT": {
+                    "description": "Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "POS1REV_INT": {
+                    "description": "Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "POS2REV_INT": {
+                    "description": "Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "REV1_INT": {
+                    "description": "Writing a 1 disables the REV1_Int interrupt in the QEIIE register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "REV2_INT": {
+                    "description": "Writing a 1 disables the REV2_Int interrupt in the QEIIE register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "MAXPOS_INT": {
+                    "description": "Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved. Read value is undefined, only zero should be written.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "MCPWM": {
+        "description": "Motor Control PWM",
+        "children": {
+          "registers": {
+            "CON": {
+              "description": "PWM Control read address",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RUN0": {
+                    "description": "Stops/starts timer channel 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "STOP_": {
+                            "description": "Stop.",
+                            "value": 0
+                          },
+                          "RUN_": {
+                            "description": "Run.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CENTER0": {
+                    "description": "Edge/center aligned operation for channel 0.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "EDGE_ALIGNED_": {
+                            "description": "Edge-aligned.",
+                            "value": 0
+                          },
+                          "CENTER_ALIGNED_": {
+                            "description": "Center-aligned.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "POLA0": {
+                    "description": "Selects polarity of the MCOA0 and MCOB0 pins.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "PASSIVE_STATE_IS_LOW": {
+                            "description": "Passive state is LOW, active state is HIGH.",
+                            "value": 0
+                          },
+                          "PASSIVE_STATE_IS_HIG": {
+                            "description": "Passive state is HIGH, active state is LOW.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DTE0": {
+                    "description": "Controls the dead-time feature for channel 0.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DEAD_TIME_DISABLED_": {
+                            "description": "Dead-time disabled.",
+                            "value": 0
+                          },
+                          "DEAD_TIME_ENABLED_": {
+                            "description": "Dead-time enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISUP0": {
+                    "description": "Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "UPDATE": {
+                            "description": "Functional registers are updated from the write registers at the end of each PWM cycle.",
+                            "value": 0
+                          },
+                          "NOUPDATE": {
+                            "description": "Functional registers remain the same as long as the timer is running.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 21,
+                    "size": 8
+                  },
+                  "RUN1": {
+                    "description": "Stops/starts timer channel 1.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "STOP_": {
+                            "description": "Stop.",
+                            "value": 0
+                          },
+                          "RUN_": {
+                            "description": "Run.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CENTER1": {
+                    "description": "Edge/center aligned operation for channel 1.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "EDGE_ALIGNED_": {
+                            "description": "Edge-aligned.",
+                            "value": 0
+                          },
+                          "CENTER_ALIGNED_": {
+                            "description": "Center-aligned.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "POLA1": {
+                    "description": "Selects polarity of the MCOA1 and MCOB1 pins.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "PASSIVE_STATE_IS_LOW": {
+                            "description": "Passive state is LOW, active state is HIGH.",
+                            "value": 0
+                          },
+                          "PASSIVE_STATE_IS_HIG": {
+                            "description": "Passive state is HIGH, active state is LOW.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DTE1": {
+                    "description": "Controls the dead-time feature for channel 1.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DEAD_TIME_DISABLED_": {
+                            "description": "Dead-time disabled.",
+                            "value": 0
+                          },
+                          "DEAD_TIME_ENABLED_": {
+                            "description": "Dead-time enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISUP1": {
+                    "description": "Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "UPDATE": {
+                            "description": "Functional registers are updated from the write registers at the end of each PWM cycle.",
+                            "value": 0
+                          },
+                          "NOUPDATE": {
+                            "description": "Functional registers remain the same as long as the timer is running.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RUN2": {
+                    "description": "Stops/starts timer channel 2.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "STOP_": {
+                            "description": "Stop.",
+                            "value": 0
+                          },
+                          "RUN_": {
+                            "description": "Run.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CENTER2": {
+                    "description": "Edge/center aligned operation for channel 2.",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "EDGE_ALIGNED_": {
+                            "description": "Edge-aligned.",
+                            "value": 0
+                          },
+                          "CENTER_ALIGNED_": {
+                            "description": "Center-aligned.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "POLA2": {
+                    "description": "Selects polarity of the MCOA2 and MCOB2 pins.",
+                    "offset": 18,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "PASSIVE_STATE_IS_LOW": {
+                            "description": "Passive state is LOW, active state is HIGH.",
+                            "value": 0
+                          },
+                          "PASSIVE_STATE_IS_HIG": {
+                            "description": "Passive state is HIGH, active state is LOW.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DTE2": {
+                    "description": "Controls the dead-time feature for channel 1.",
+                    "offset": 19,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DEAD_TIME_DISABLED_": {
+                            "description": "Dead-time disabled.",
+                            "value": 0
+                          },
+                          "DEAD_TIME_ENABLED_": {
+                            "description": "Dead-time enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DISUP2": {
+                    "description": "Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).",
+                    "offset": 20,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "UPDATE": {
+                            "description": "Functional registers are updated from the write registers at the end of each PWM cycle.",
+                            "value": 0
+                          },
+                          "NOUPDATE": {
+                            "description": "Functional registers remain the same as long as the timer is running.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INVBDC": {
+                    "description": "Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "OPPOSITE": {
+                            "description": "The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time).",
+                            "value": 0
+                          },
+                          "SAME": {
+                            "description": "The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ACMODE": {
+                    "description": "3-phase AC mode select (see Section 24.8.7).",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "3_PHASE_AC_MODE_OFF": {
+                            "description": "3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register.",
+                            "value": 0
+                          },
+                          "3_PHASE_AC_MODE_ON_": {
+                            "description": "3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DCMODE": {
+                    "description": "3-phase DC mode select (see Section 24.8.6).",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "3_PHASE_DC_MODE_OFF": {
+                            "description": "3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)",
+                            "value": 0
+                          },
+                          "3_PHASE_DC_MODE_ON_": {
+                            "description": "3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CON_SET": {
+              "description": "PWM Control set address",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "RUN0_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CENTER0_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "POLA0_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DTE0_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DISUP0_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 21,
+                    "size": 8
+                  },
+                  "RUN1_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CENTER1_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "POLA1_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DTE1_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DISUP1_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RUN2_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CENTER2_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "POLA2_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DTE2_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DISUP2_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "INVBDC_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ACMODE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DCMODE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CON register.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CON_CLR": {
+              "description": "PWM Control clear address",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "RUN0_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CENTER0_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "POLA0_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DTE0_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DISUP0_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 21,
+                    "size": 8
+                  },
+                  "RUN1_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CENTER1_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "POLA1_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DTE1_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DISUP1_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RUN2_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CENTER2_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "POLA2_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DTE2_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DISUP2_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "INVBDC_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ACMOD_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DCMODE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CON register.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CAPCON": {
+              "description": "Capture Control read address",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CAP0MCI0_RE": {
+                    "description": "A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CAP0MCI0_FE": {
+                    "description": "A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CAP0MCI1_RE": {
+                    "description": "A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CAP0MCI1_FE": {
+                    "description": "A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CAP0MCI2_RE": {
+                    "description": "A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CAP0MCI2_FE": {
+                    "description": "A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CAP1MCI0_RE": {
+                    "description": "A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CAP1MCI0_FE": {
+                    "description": "A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CAP1MCI1_RE": {
+                    "description": "A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CAP1MCI1_FE": {
+                    "description": "A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CAP1MCI2_RE": {
+                    "description": "A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CAP1MCI2_FE": {
+                    "description": "A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CAP2MCI0_RE": {
+                    "description": "A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CAP2MCI0_FE": {
+                    "description": "A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CAP2MCI1_RE": {
+                    "description": "A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CAP2MCI1_FE": {
+                    "description": "A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CAP2MCI2_RE": {
+                    "description": "A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CAP2MCI2_FE": {
+                    "description": "A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RT0": {
+                    "description": "If this bit is 1, TC0 is reset by a channel 0 capture event.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RT1": {
+                    "description": "If this bit is 1, TC1 is reset by a channel 1 capture event.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "RT2": {
+                    "description": "If this bit is 1, TC2 is reset by a channel 2 capture event.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 21,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "CAPCON_SET": {
+              "description": "Capture Control set address",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CAP0MCI0_RE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CAP0MCI0_FE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CAP0MCI1_RE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CAP0MCI1_FE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CAP0MCI2_RE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CAP0MCI2_FE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CAP1MCI0_RE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CAP1MCI0_FE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CAP1MCI1_RE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CAP1MCI1_FE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CAP1MCI2_RE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CAP1MCI2_FE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CAP2MCI0_RE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CAP2MCI0_FE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CAP2MCI1_RE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CAP2MCI1_FE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CAP2MCI2_RE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CAP2MCI2_FE_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RT0_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RT1_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "RT2_SET": {
+                    "description": "Writing a one sets the corresponding bits in the CAPCON register.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 21,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "CAPCON_CLR": {
+              "description": "Event Control clear address",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CAP0MCI0_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CAP0MCI0_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CAP0MCI1_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CAP0MCI1_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CAP0MCI2_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CAP0MCI2_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CAP1MCI0_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CAP1MCI0_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CAP1MCI1_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CAP1MCI1_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CAP1MCI2_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CAP1MCI2_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CAP2MCI0_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CAP2MCI0_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CAP2MCI1_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CAP2MCI1_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CAP2MCI2_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CAP2MCI2_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RT0_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RT1_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "RT2_CLR": {
+                    "description": "Writing a one clears the corresponding bits in the CAPCON register.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 21,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DT": {
+              "description": "Dead time register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 1073741823,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DT0": {
+                    "description": "Dead time for channel 0.[1]",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DT1": {
+                    "description": "Dead time for channel 1.[2]",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DT2": {
+                    "description": "Dead time for channel 2.[2]",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "RESERVED": {
+                    "description": "reserved",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CP": {
+              "description": "Communication Pattern register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CCPA0": {
+                    "description": "Communication pattern output A, channel 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MCOA0_PASSIVE_": {
+                            "description": "MCOA0 passive.",
+                            "value": 0
+                          },
+                          "INTERNAL_MCOA0_": {
+                            "description": "internal MCOA0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCPB0": {
+                    "description": "Communication pattern output B, channel 0.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MCOB0_PASSIVE_": {
+                            "description": "MCOB0 passive.",
+                            "value": 0
+                          },
+                          "MCOB0_TRACKS_INTERNA": {
+                            "description": "MCOB0 tracks internal MCOA0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCPA1": {
+                    "description": "Communication pattern output A, channel 1.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MCOA1_PASSIVE_": {
+                            "description": "MCOA1 passive.",
+                            "value": 0
+                          },
+                          "MCOA1_TRACKS_INTERNA": {
+                            "description": "MCOA1 tracks internal MCOA0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCPB1": {
+                    "description": "Communication pattern output B, channel 1.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MCOB1_PASSIVE_": {
+                            "description": "MCOB1 passive.",
+                            "value": 0
+                          },
+                          "MCOB1_TRACKS_INTERNA": {
+                            "description": "MCOB1 tracks internal MCOA0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCPA2": {
+                    "description": "Communication pattern output A, channel 2.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MCOA2_PASSIVE_": {
+                            "description": "MCOA2 passive.",
+                            "value": 0
+                          },
+                          "MCOA2_TRACKS_INTERNA": {
+                            "description": "MCOA2 tracks internal MCOA0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CCPB2": {
+                    "description": "Communication pattern output B, channel 2.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "MCOB2_PASSIVE_": {
+                            "description": "MCOB2 passive.",
+                            "value": 0
+                          },
+                          "MCOB2_TRACKS_INTERNA": {
+                            "description": "MCOB2 tracks internal MCOA0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Interrupt Enable read address",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ILIM0": {
+                    "description": "Limit interrupt for channel 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_DISABLED_": {
+                            "description": "Interrupt disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ENABLED_": {
+                            "description": "Interrupt enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IMAT0": {
+                    "description": "Match interrupt for channel 0.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_DISABLED_": {
+                            "description": "Interrupt disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ENABLED_": {
+                            "description": "Interrupt enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ICAP0": {
+                    "description": "Capture interrupt for channel 0.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_DISABLED_": {
+                            "description": "Interrupt disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ENABLED_": {
+                            "description": "Interrupt enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ILIM1": {
+                    "description": "Limit interrupt for channel 1.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_DISABLED_": {
+                            "description": "Interrupt disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ENABLED_": {
+                            "description": "Interrupt enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IMAT1": {
+                    "description": "Match interrupt for channel 1.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_DISABLED_": {
+                            "description": "Interrupt disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ENABLED_": {
+                            "description": "Interrupt enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ICAP1": {
+                    "description": "Capture interrupt for channel 1.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_DISABLED_": {
+                            "description": "Interrupt disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ENABLED_": {
+                            "description": "Interrupt enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ILIM2": {
+                    "description": "Limit interrupt for channel 2.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_DISABLED_": {
+                            "description": "Interrupt disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ENABLED_": {
+                            "description": "Interrupt enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IMAT2": {
+                    "description": "Match interrupt for channel 2.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_DISABLED_": {
+                            "description": "Interrupt disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ENABLED_": {
+                            "description": "Interrupt enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ICAP2": {
+                    "description": "Capture interrupt for channel 2.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_DISABLED_": {
+                            "description": "Interrupt disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ENABLED_": {
+                            "description": "Interrupt enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABORT": {
+                    "description": "Fast abort interrupt.",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INTERRUPT_DISABLED_": {
+                            "description": "Interrupt disabled.",
+                            "value": 0
+                          },
+                          "INTERRUPT_ENABLED_": {
+                            "description": "Interrupt enabled.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTEN_SET": {
+              "description": "Interrupt Enable set address",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "ILIM0_SET": {
+                    "description": "Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IMAT0_SET": {
+                    "description": "Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICAP0_SET": {
+                    "description": "Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ILIM1_SET": {
+                    "description": "Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IMAT1_SET": {
+                    "description": "Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ICAP1_SET": {
+                    "description": "Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ILIM2_SET": {
+                    "description": "Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IMAT2_SET": {
+                    "description": "Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ICAP2_SET": {
+                    "description": "Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ABORT_SET": {
+                    "description": "Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTEN_CLR": {
+              "description": "Interrupt Enable clear address",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "ILIM0_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IMAT0_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICAP0_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ILIM1_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IMAT1_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ICAP1_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ILIM2_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IMAT2_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ICAP2_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ABORT_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTF": {
+              "description": "Interrupt flags read address",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ILIM0_F": {
+                    "description": "Limit interrupt flag for channel 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THIS_INTERRUPT_SOURC": {
+                            "description": "This interrupt source is not contributing to the MCPWM interrupt request.",
+                            "value": 0
+                          },
+                          "IF_THE_CORRESPONDING": {
+                            "description": "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IMAT0_F": {
+                    "description": "Match interrupt flag for channel 0.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THIS_INTERRUPT_SOURC": {
+                            "description": "This interrupt source is not contributing to the MCPWM interrupt request.",
+                            "value": 0
+                          },
+                          "IF_THE_CORRESPONDING": {
+                            "description": "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ICAP0_F": {
+                    "description": "Capture interrupt flag for channel 0.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THIS_INTERRUPT_SOURC": {
+                            "description": "This interrupt source is not contributing to the MCPWM interrupt request.",
+                            "value": 0
+                          },
+                          "IF_THE_CORRESPONDING": {
+                            "description": "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ILIM1_F": {
+                    "description": "Limit interrupt flag for channel 1.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THIS_INTERRUPT_SOURC": {
+                            "description": "This interrupt source is not contributing to the MCPWM interrupt request.",
+                            "value": 0
+                          },
+                          "IF_THE_CORRESPONDING": {
+                            "description": "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IMAT1_F": {
+                    "description": "Match interrupt flag for channel 1.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THIS_INTERRUPT_SOURC": {
+                            "description": "This interrupt source is not contributing to the MCPWM interrupt request.",
+                            "value": 0
+                          },
+                          "IF_THE_CORRESPONDING": {
+                            "description": "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ICAP1_F": {
+                    "description": "Capture interrupt flag for channel 1.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THIS_INTERRUPT_SOURC": {
+                            "description": "This interrupt source is not contributing to the MCPWM interrupt request.",
+                            "value": 0
+                          },
+                          "IF_THE_CORRESPONDING": {
+                            "description": "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ILIM2_F": {
+                    "description": "Limit interrupt flag for channel 2.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THIS_INTERRUPT_SOURC": {
+                            "description": "This interrupt source is not contributing to the MCPWM interrupt request.",
+                            "value": 0
+                          },
+                          "IF_THE_CORRESPONDING": {
+                            "description": "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IMAT2_F": {
+                    "description": "Match interrupt flag for channel 2.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THIS_INTERRUPT_SOURC": {
+                            "description": "This interrupt source is not contributing to the MCPWM interrupt request.",
+                            "value": 0
+                          },
+                          "IF_THE_CORRESPONDING": {
+                            "description": "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ICAP2_F": {
+                    "description": "Capture interrupt flag for channel 2.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THIS_INTERRUPT_SOURC": {
+                            "description": "This interrupt source is not contributing to the MCPWM interrupt request.",
+                            "value": 0
+                          },
+                          "IF_THE_CORRESPONDING": {
+                            "description": "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABORT_F": {
+                    "description": "Fast abort interrupt flag.",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THIS_INTERRUPT_SOURC": {
+                            "description": "This interrupt source is not contributing to the MCPWM interrupt request.",
+                            "value": 0
+                          },
+                          "IF_THE_CORRESPONDING": {
+                            "description": "If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTF_SET": {
+              "description": "Interrupt flags set address",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "ILIM0_F_SET": {
+                    "description": "Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IMAT0_F_SET": {
+                    "description": "Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICAP0_F_SET": {
+                    "description": "Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ILIM1_F_SET": {
+                    "description": "Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IMAT1_F_SET": {
+                    "description": "Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ICAP1_F_SET": {
+                    "description": "Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ILIM2_F_SET": {
+                    "description": "Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IMAT2_F_SET": {
+                    "description": "Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ICAP2_F_SET": {
+                    "description": "Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ABORT_F_SET": {
+                    "description": "Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTF_CLR": {
+              "description": "Interrupt flags clear address",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "ILIM0_F_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IMAT0_F_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICAP0_F_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ILIM1_F_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IMAT1_F_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ICAP1_F_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ILIM2_F_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IMAT2_F_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ICAP2_F_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ABORT_F_CLR": {
+                    "description": "Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNTCON": {
+              "description": "Count Control read address",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TC0MCI0_RE": {
+                    "description": "Counter 0 rising edge mode, channel 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_RISING_EDGE_ON_MCI": {
+                            "description": "A rising edge on MCI0 does not affect counter 0.",
+                            "value": 0
+                          },
+                          "RISING": {
+                            "description": "If MODE0 is 1, counter 0 advances on a rising edge on MCI0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC0MCI0_FE": {
+                    "description": "Counter 0 falling edge mode, channel 0.",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_FALLING_EDGE_ON_MC": {
+                            "description": "A falling edge on MCI0 does not affect counter 0.",
+                            "value": 0
+                          },
+                          "FALLING": {
+                            "description": "If MODE0 is 1, counter 0 advances on a falling edge on MCI0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC0MCI1_RE": {
+                    "description": "Counter 0 rising edge mode, channel 1.",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_RISING_EDGE_ON_MCI": {
+                            "description": "A rising edge on MCI1 does not affect counter 0.",
+                            "value": 0
+                          },
+                          "RISING": {
+                            "description": "If MODE0 is 1, counter 0 advances on a rising edge on MCI1.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC0MCI1_FE": {
+                    "description": "Counter 0 falling edge mode, channel 1.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_FALLING_EDGE_ON_MC": {
+                            "description": "A falling edge on MCI1 does not affect counter 0.",
+                            "value": 0
+                          },
+                          "FALLING": {
+                            "description": "If MODE0 is 1, counter 0 advances on a falling edge on MCI1.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC0MCI2_RE": {
+                    "description": "Counter 0 rising edge mode, channel 2.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_RISING_EDGE_ON_MCI": {
+                            "description": "A rising edge on MCI0 does not affect counter 0.",
+                            "value": 0
+                          },
+                          "RISING": {
+                            "description": "If MODE0 is 1, counter 0 advances on a rising edge on MCI2.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC0MCI2_FE": {
+                    "description": "Counter 0 falling edge mode, channel 2.",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_FALLING_EDGE_ON_MC": {
+                            "description": "A falling edge on MCI0 does not affect counter 0.",
+                            "value": 0
+                          },
+                          "FALLLING": {
+                            "description": "If MODE0 is 1, counter 0 advances on a falling edge on MCI2.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC1MCI0_RE": {
+                    "description": "Counter 1 rising edge mode, channel 0.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_RISING_EDGE_ON_MCI": {
+                            "description": "A rising edge on MCI0 does not affect counter 1.",
+                            "value": 0
+                          },
+                          "RISING": {
+                            "description": "If MODE1 is 1, counter 1 advances on a rising edge on MCI0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC1MCI0_FE": {
+                    "description": "Counter 1 falling edge mode, channel 0.",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_FALLING_EDGE_ON_MC": {
+                            "description": "A falling edge on MCI0 does not affect counter 1.",
+                            "value": 0
+                          },
+                          "FALLING": {
+                            "description": "If MODE1 is 1, counter 1 advances on a falling edge on MCI0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC1MCI1_RE": {
+                    "description": "Counter 1 rising edge mode, channel 1.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_RISING_EDGE_ON_MCI": {
+                            "description": "A rising edge on MCI1 does not affect counter 1.",
+                            "value": 0
+                          },
+                          "RISING": {
+                            "description": "If MODE1 is 1, counter 1 advances on a rising edge on MCI1.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC1MCI1_FE": {
+                    "description": "Counter 1 falling edge mode, channel 1.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_FALLING_EDGE_ON_MC": {
+                            "description": "A falling edge on MCI0 does not affect counter 1.",
+                            "value": 0
+                          },
+                          "FALLING": {
+                            "description": "If MODE1 is 1, counter 1 advances on a falling edge on MCI1.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC1MCI2_RE": {
+                    "description": "Counter 1 rising edge mode, channel 2.",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_RISING_EDGE_ON_MCI": {
+                            "description": "A rising edge on MCI2 does not affect counter 1.",
+                            "value": 0
+                          },
+                          "RISING": {
+                            "description": "If MODE1 is 1, counter 1 advances on a rising edge on MCI2.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC1MCI2_FE": {
+                    "description": "Counter 1 falling edge mode, channel 2.",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_FALLING_EDGE_ON_MC": {
+                            "description": "A falling edge on MCI2 does not affect counter 1.",
+                            "value": 0
+                          },
+                          "FALLING": {
+                            "description": "If MODE1 is 1, counter 1 advances on a falling edge on MCI2.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC2MCI0_RE": {
+                    "description": "Counter 2 rising edge mode, channel 0.",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_RISING_EDGE_ON_MCI": {
+                            "description": "A rising edge on MCI0 does not affect counter 2.",
+                            "value": 0
+                          },
+                          "RISING": {
+                            "description": "If MODE2 is 1, counter 2 advances on a rising edge on MCI0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC2MCI0_FE": {
+                    "description": "Counter 2 falling edge mode, channel 0.",
+                    "offset": 13,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_FALLING_EDGE_ON_MC": {
+                            "description": "A falling edge on MCI0 does not affect counter 2.",
+                            "value": 0
+                          },
+                          "FALLING": {
+                            "description": "If MODE2 is 1, counter 2 advances on a falling edge on MCI0.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC2MCI1_RE": {
+                    "description": "Counter 2 rising edge mode, channel 1.",
+                    "offset": 14,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_RISING_EDGE_ON_MCI": {
+                            "description": "A rising edge on MCI1 does not affect counter 2.",
+                            "value": 0
+                          },
+                          "RISING": {
+                            "description": "If MODE2 is 1, counter 2 advances on a rising edge on MCI1.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC2MCI1_FE": {
+                    "description": "Counter 2 falling edge mode, channel 1.",
+                    "offset": 15,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_FALLING_EDGE_ON_MC": {
+                            "description": "A falling edge on MCI1 does not affect counter 2.",
+                            "value": 0
+                          },
+                          "FALLING": {
+                            "description": "If MODE2 is 1, counter 2 advances on a falling edge on MCI1.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC2MCI2_RE": {
+                    "description": "Counter 2 rising edge mode, channel 2.",
+                    "offset": 16,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_RISING_EDGE_ON_MCI": {
+                            "description": "A rising edge on MCI2 does not affect counter 2.",
+                            "value": 0
+                          },
+                          "RISIING": {
+                            "description": "If MODE2 is 1, counter 2 advances on a rising edge on MCI2.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TC2MCI2_FE": {
+                    "description": "Counter 2 falling edge mode, channel 2.",
+                    "offset": 17,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "A_FALLING_EDGE_ON_MC": {
+                            "description": "A falling edge on MCI2 does not affect counter 2.",
+                            "value": 0
+                          },
+                          "FALLING": {
+                            "description": "If MODE2 is 1, counter 2 advances on a falling edge on MCI2.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 18,
+                    "size": 11
+                  },
+                  "CNTR0": {
+                    "description": "Channel 0 counter/timer mode.",
+                    "offset": 29,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "CHANNEL_0_IS_IN_TIME": {
+                            "description": "Channel 0 is in timer mode.",
+                            "value": 0
+                          },
+                          "CHANNEL_0_IS_IN_COUN": {
+                            "description": "Channel 0 is in counter mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CNTR1": {
+                    "description": "Channel 1 counter/timer mode.",
+                    "offset": 30,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "CHANNEL_1_IS_IN_TIME": {
+                            "description": "Channel 1 is in timer mode.",
+                            "value": 0
+                          },
+                          "CHANNEL_1_IS_IN_COUN": {
+                            "description": "Channel 1 is in counter mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CNTR2": {
+                    "description": "Channel 2 counter/timer mode.",
+                    "offset": 31,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "CHANNEL_2_IS_IN_TIME": {
+                            "description": "Channel 2 is in timer mode.",
+                            "value": 0
+                          },
+                          "CHANNEL_2_IS_IN_COUN": {
+                            "description": "Channel 2 is in counter mode.",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CNTCON_SET": {
+              "description": "Count Control set address",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TC0MCI0_RE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TC0MCI0_FE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TC0MCI1_RE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TC0MCI1_FE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TC0MCI2_RE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TC0MCI2_FE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TC1MCI0_RE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TC1MCI0_FE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TC1MCI1_RE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TC1MCI1_FE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TC1MCI2_RE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TC1MCI2_FE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TC2MCI0_RE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TC2MCI0_FE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TC2MCI1_RE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TC2MCI1_FE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TC2MCI2_RE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TC2MCI2_FE_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 18,
+                    "size": 11
+                  },
+                  "CNTR0_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CNTR1_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CNTR2_SET": {
+                    "description": "Writing a one sets the corresponding bit in the CNTCON register.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNTCON_CLR": {
+              "description": "Count Control clear address",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TC0MCI0_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TC0MCI0_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TC0MCI1_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TC0MCI1_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TC0MCI2_RE": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TC0MCI2_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TC1MCI0_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TC1MCI0_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TC1MCI1_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TC1MCI1_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TC1MCI2_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TC1MCI2_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TC2MCI0_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TC2MCI0_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TC2MCI1_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TC2MCI1_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TC2MCI2_RE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TC2MCI2_FE_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved.",
+                    "offset": 18,
+                    "size": 11
+                  },
+                  "CNTR0_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CNTR1_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CNTR2_CLR": {
+                    "description": "Writing a one clears the corresponding bit in the CNTCON register.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CAP_CLR": {
+              "description": "Capture clear address",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 0,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CAP_CLR0": {
+                    "description": "Writing a 1 to this bit clears the CAP0 register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CAP_CLR1": {
+                    "description": "Writing a 1 to this bit clears the CAP1 register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CAP_CLR2": {
+                    "description": "Writing a 1 to this bit clears the CAP2 register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved",
+                    "offset": 3,
+                    "size": 29
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RITIMER": {
+        "description": "Repetitive Interrupt Timer (RIT) ",
+        "children": {
+          "registers": {
+            "COMPVAL": {
+              "description": "Compare register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RICOMP": {
+                    "description": "Compare register. Holds the compare value which is compared to the counter.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MASK": {
+              "description": "Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RIMASK": {
+                    "description": "Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CTRL": {
+              "description": "Control register.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 12,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RITINT": {
+                    "description": "Interrupt flag",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THIS_BIT_IS_SET_TO_1": {
+                            "description": "This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect.",
+                            "value": 1
+                          },
+                          "THE_COUNTER_VALUE_DO": {
+                            "description": "The counter value does not equal the masked compare value.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RITENCLR": {
+                    "description": "Timer enable clear",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_TIMER_WILL_BE_CL": {
+                            "description": "The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag.",
+                            "value": 1
+                          },
+                          "THE_TIMER_WILL_NOT_B": {
+                            "description": "The timer will not be cleared to 0.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RITENBR": {
+                    "description": "Timer enable for debug",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "THE_TIMER_IS_HALTED_": {
+                            "description": "The timer is halted when the processor is halted for debugging.",
+                            "value": 1
+                          },
+                          "DEBUG_HAS_NO_EFFECT_": {
+                            "description": "Debug has no effect on the timer operation.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RITEN": {
+                    "description": "Timer enable.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER_ENABLED_THIS_": {
+                            "description": "Timer enabled. This can be overruled by a debug halt if enabled in bit 2.",
+                            "value": 1
+                          },
+                          "TIMER_DISABLED_": {
+                            "description": "Timer disabled.",
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "COUNTER": {
+              "description": "32-bit counter",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RICOUNTER": {
+                    "description": "32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2S": {
+        "description": "I2S interface",
+        "children": {
+          "registers": {
+            "DAO": {
+              "description": "I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 34785,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WORDWIDTH": {
+                    "description": "Selects the number of bytes in data as follows:",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "8_BIT_DATA": {
+                            "description": "8-bit data",
+                            "value": 0
+                          },
+                          "16_BIT_DATA": {
+                            "description": "16-bit data",
+                            "value": 1
+                          },
+                          "32_BIT_DATA": {
+                            "description": "32-bit data",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MONO": {
+                    "description": "When 1, data is of monaural format. When 0, the data is in stereo format.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "When 1, disables accesses on FIFOs, places the transmit channel in mute mode.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "When 1, asynchronously resets the transmit channel and FIFO.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "WS_SEL": {
+                    "description": "When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WS_HALFPERIOD": {
+                    "description": "Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",
+                    "offset": 6,
+                    "size": 9
+                  },
+                  "MUTE": {
+                    "description": "When 1, the transmit channel sends only zeroes.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DAI": {
+              "description": "I2S Digital Audio Input Register. Contains control bits for the I2S receive channel.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 2017,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WORDWIDTH": {
+                    "description": "Selects the number of bytes in data as follows:",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "8_BIT_DATA": {
+                            "description": "8-bit data",
+                            "value": 0
+                          },
+                          "16_BIT_DATA": {
+                            "description": "16-bit data",
+                            "value": 1
+                          },
+                          "32_BIT_DATA": {
+                            "description": "32-bit data",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MONO": {
+                    "description": "When 1, data is of monaural format. When 0, the data is in stereo format.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "When 1, disables accesses on FIFOs, places the transmit channel in mute mode.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "When 1, asynchronously reset the transmit channel and FIFO.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "WS_SEL": {
+                    "description": "When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WS_HALFPERIOD": {
+                    "description": "Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.",
+                    "offset": 6,
+                    "size": 9
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 15,
+                    "size": 17
+                  }
+                }
+              }
+            },
+            "TXFIFO": {
+              "description": "I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "I2STXFIFO": {
+                    "description": "8 x 32-bit transmit FIFO.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RXFIFO": {
+              "description": "I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "I2SRXFIFO": {
+                    "description": "8 x 32-bit transmit FIFO.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STATE": {
+              "description": "I2S Status Feedback Register. Contains status information about the I2S interface.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IRQ": {
+                    "description": "This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMAREQ1": {
+                    "description": "This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DMAREQ2": {
+                    "description": "This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 20,
+                    "size": 12
+                  },
+                  "RX_LEVEL": {
+                    "description": "Reflects the current level of the Receive FIFO.",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "TX_LEVEL": {
+                    "description": "Reflects the current level of the Transmit FIFO.",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DMA1": {
+              "description": "I2S DMA Configuration Register 1. Contains control information for DMA request 1.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_DMA1_ENABLE": {
+                    "description": "When 1, enables DMA1 for I2S receive.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_DMA1_ENABLE": {
+                    "description": "When 1, enables DMA1 for I2S transmit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 20,
+                    "size": 12
+                  },
+                  "RX_DEPTH_DMA1": {
+                    "description": "Set the FIFO level that triggers a receive DMA request on DMA1.",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "TX_DEPTH_DMA1": {
+                    "description": "Set the FIFO level that triggers a transmit DMA request on DMA1.",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DMA2": {
+              "description": "I2S DMA Configuration Register 2. Contains control information for DMA request 2.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_DMA2_ENABLE": {
+                    "description": "When 1, enables DMA1 for I2S receive.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_DMA2_ENABLE": {
+                    "description": "When 1, enables DMA1 for I2S transmit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 20,
+                    "size": 12
+                  },
+                  "RX_DEPTH_DMA2": {
+                    "description": "Set the FIFO level that triggers a receive DMA request on DMA2.",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "TX_DEPTH_DMA2": {
+                    "description": "Set the FIFO level that triggers a transmit DMA request on DMA2.",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "IRQ": {
+              "description": "I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_IRQ_ENABLE": {
+                    "description": "When 1, enables I2S receive interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_IRQ_ENABLE": {
+                    "description": "When 1, enables I2S transmit interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 20,
+                    "size": 12
+                  },
+                  "RX_DEPTH_IRQ": {
+                    "description": "Set the FIFO level on which to create an irq request.",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "TX_DEPTH_IRQ": {
+                    "description": "Set the FIFO level on which to create an irq request.",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TXRATE": {
+              "description": "I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "Y_DIVIDER": {
+                    "description": "I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "X_DIVIDER": {
+                    "description": "I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RXRATE": {
+              "description": "I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "Y_DIVIDER": {
+                    "description": "I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "X_DIVIDER": {
+                    "description": "I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TXBITRATE": {
+              "description": "I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BITRATE": {
+                    "description": "I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock.",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "RXBITRATE": {
+              "description": "I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_BITRATE": {
+                    "description": "I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock.",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 6,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "TXMODE": {
+              "description": "I2S Transmit mode control.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXCLKSEL": {
+                    "description": "Clock source selection for the transmit bit clock divider.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SELECT_THE_TX_FRACTI": {
+                            "description": "Select the TX fractional rate divider clock output as the source",
+                            "value": 0
+                          },
+                          "SELECT_THE_RX_MCLK_S": {
+                            "description": "Select the RX_MCLK signal as the TX_MCLK clock source",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TX4PIN": {
+                    "description": "Transmit 4-pin mode selection. When 1, enables 4-pin mode.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXMCENA": {
+                    "description": "Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "RXMODE": {
+              "description": "I2S Receive mode control.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXCLKSEL": {
+                    "description": "Clock source selection for the receive bit clock divider.",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SELECT_THE_RX_FRACTI": {
+                            "description": "Select the RX fractional rate divider clock output as the source",
+                            "value": 0
+                          },
+                          "SELECT_THE_TX_MCLK_S": {
+                            "description": "Select the TX_MCLK signal as the RX_MCLK clock source",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RX4PIN": {
+                    "description": "Receive 4-pin mode selection. When 1, enables 4-pin mode.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RXMCENA": {
+                    "description": "Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.",
+                    "offset": 4,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  },
+  "devices": {
+    "LPC176x5x": {
+      "arch": "cortex_m3",
+      "description": "LPC176x/LPC175x M3",
+      "properties": {
+        "cpu.nvic_prio_bits": "5",
+        "cpu.mpu": "1",
+        "cpu.fpu": "0",
+        "cpu.revision": "r0p0",
+        "cpu.vendor_systick_config": "0",
+        "cpu.endian": "little",
+        "cpu.name": "CM3"
+      },
+      "children": {
+        "interrupts": {
+          "MemManageFault": {
+            "index": -12
+          },
+          "BusFault": {
+            "index": -11
+          },
+          "UsageFault": {
+            "index": -10
+          },
+          "DebugMonitor": {
+            "index": -4
+          },
+          "NMI": {
+            "index": -14
+          },
+          "HardFault": {
+            "index": -13
+          },
+          "SVCall": {
+            "index": -5
+          },
+          "PendSV": {
+            "index": -2
+          },
+          "SysTick": {
+            "index": -1
+          },
+          "WDT": {
+            "index": 0
+          },
+          "TIMER0": {
+            "index": 1
+          },
+          "TIMER1": {
+            "index": 2
+          },
+          "UART0": {
+            "index": 5
+          },
+          "UART1": {
+            "index": 6
+          },
+          "PWM1": {
+            "index": 9
+          },
+          "I2C0": {
+            "index": 10
+          },
+          "SPI": {
+            "index": 13
+          },
+          "RTC": {
+            "index": 17
+          },
+          "SSP1": {
+            "index": 15
+          },
+          "ADC": {
+            "index": 22
+          },
+          "CANActivity": {
+            "index": 34
+          },
+          "CAN": {
+            "index": 25
+          },
+          "I2C1": {
+            "index": 11
+          },
+          "SSP0": {
+            "index": 14
+          },
+          "TIMER2": {
+            "index": 3
+          },
+          "TIMER3": {
+            "index": 4
+          },
+          "UART2": {
+            "index": 7
+          },
+          "UART3": {
+            "index": 8
+          },
+          "I2C2": {
+            "index": 12
+          },
+          "I2S": {
+            "index": 27
+          },
+          "RIT": {
+            "index": 29
+          },
+          "MCPWM": {
+            "index": 30
+          },
+          "QEI": {
+            "index": 31
+          },
+          "EINT0": {
+            "index": 18
+          },
+          "ENET": {
+            "index": 28
+          },
+          "DMA": {
+            "index": 26
+          },
+          "USB": {
+            "index": 24
+          }
+        },
+        "peripheral_instances": {
+          "WDT": {
+            "description": "Watchdog Timer (WDT) ",
+            "offset": 1073741824,
+            "type": "types.peripherals.WDT"
+          },
+          "TIMER0": {
+            "description": "Timer0/1/2/3  ",
+            "offset": 1073758208,
+            "type": "types.peripherals.TIMER0"
+          },
+          "TIMER1": {
+            "offset": 1073774592,
+            "type": "types.peripherals.TIMER0"
+          },
+          "UART0": {
+            "description": "UART0/2/3  ",
+            "offset": 1073790976,
+            "type": "types.peripherals.UART0"
+          },
+          "UART1": {
+            "description": "UART1  ",
+            "offset": 1073807360,
+            "type": "types.peripherals.UART1"
+          },
+          "PWM1": {
+            "description": "Pulse Width Modulators (PWM1) ",
+            "offset": 1073840128,
+            "type": "types.peripherals.PWM1"
+          },
+          "I2C0": {
+            "description": "I2C bus interface",
+            "offset": 1073856512,
+            "type": "types.peripherals.I2C0"
+          },
+          "SPI": {
+            "description": "SPI ",
+            "offset": 1073872896,
+            "type": "types.peripherals.SPI"
+          },
+          "RTC": {
+            "description": " Real Time Clock (RTC)  ",
+            "offset": 1073889280,
+            "type": "types.peripherals.RTC"
+          },
+          "GPIOINT": {
+            "description": "GPIO",
+            "offset": 1073905792,
+            "type": "types.peripherals.GPIOINT"
+          },
+          "PINCONNECT": {
+            "description": "Pin connect block",
+            "offset": 1073922048,
+            "type": "types.peripherals.PINCONNECT"
+          },
+          "SSP1": {
+            "description": "SSP1 controller",
+            "offset": 1073938432,
+            "type": "types.peripherals.SSP1"
+          },
+          "ADC": {
+            "description": "Analog-to-Digital Converter (ADC) ",
+            "offset": 1073954816,
+            "type": "types.peripherals.ADC"
+          },
+          "CANAFRAM": {
+            "description": "CAN acceptance filter RAM",
+            "offset": 1073971200,
+            "type": "types.peripherals.CANAFRAM"
+          },
+          "CANAF": {
+            "description": " CAN controller acceptance filter ",
+            "offset": 1073987584,
+            "type": "types.peripherals.CANAF"
+          },
+          "CCAN": {
+            "description": "Central CAN controller ",
+            "offset": 1074003968,
+            "type": "types.peripherals.CCAN"
+          },
+          "CAN1": {
+            "description": "CAN1 controller ",
+            "offset": 1074020352,
+            "type": "types.peripherals.CAN1"
+          },
+          "CAN2": {
+            "offset": 1074036736,
+            "type": "types.peripherals.CAN1"
+          },
+          "I2C1": {
+            "offset": 1074118656,
+            "type": "types.peripherals.I2C0"
+          },
+          "SSP0": {
+            "description": "SSP controller",
+            "offset": 1074298880,
+            "type": "types.peripherals.SSP1"
+          },
+          "DAC": {
+            "description": " Digital-to-Analog Converter (DAC) ",
+            "offset": 1074315264,
+            "type": "types.peripherals.DAC"
+          },
+          "TIMER2": {
+            "offset": 1074331648,
+            "type": "types.peripherals.TIMER0"
+          },
+          "TIMER3": {
+            "offset": 1074348032,
+            "type": "types.peripherals.TIMER0"
+          },
+          "UART2": {
+            "offset": 1074364416,
+            "type": "types.peripherals.UART0"
+          },
+          "UART3": {
+            "offset": 1074380800,
+            "type": "types.peripherals.UART0"
+          },
+          "I2C2": {
+            "offset": 1074397184,
+            "type": "types.peripherals.I2C0"
+          },
+          "I2S": {
+            "description": "I2S interface",
+            "offset": 1074429952,
+            "type": "types.peripherals.I2S"
+          },
+          "RITIMER": {
+            "description": "Repetitive Interrupt Timer (RIT) ",
+            "offset": 1074462720,
+            "type": "types.peripherals.RITIMER"
+          },
+          "MCPWM": {
+            "description": "Motor Control PWM",
+            "offset": 1074495488,
+            "type": "types.peripherals.MCPWM"
+          },
+          "QEI": {
+            "description": "Quadrature Encoder Interface (QEI) ",
+            "offset": 1074511872,
+            "type": "types.peripherals.QEI"
+          },
+          "SYSCON": {
+            "description": "System and clock control",
+            "offset": 1074774016,
+            "type": "types.peripherals.SYSCON"
+          },
+          "EMAC": {
+            "description": "Ethernet",
+            "offset": 1342177280,
+            "type": "types.peripherals.EMAC"
+          },
+          "GPDMA": {
+            "description": "General purpose DMA controller",
+            "offset": 1342193664,
+            "type": "types.peripherals.GPDMA"
+          },
+          "USB": {
+            "description": "USB device/host/OTG controller",
+            "offset": 1342210048,
+            "type": "types.peripherals.USB"
+          },
+          "GPIO": {
+            "description": "General Purpose I/O ",
+            "offset": 537509888,
+            "type": "types.peripherals.GPIO"
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/chips/LPC176x5x.zig b/src/chips/LPC176x5x.zig
new file mode 100644
index 000000000..34e166cb0
--- /dev/null
+++ b/src/chips/LPC176x5x.zig
@@ -0,0 +1,12741 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    ///  LPC176x/LPC175x M3
+    pub const LPC176x5x = struct {
+        pub const properties = struct {
+            pub const @"cpu.nvic_prio_bits" = "5";
+            pub const @"cpu.mpu" = "1";
+            pub const @"cpu.fpu" = "0";
+            pub const @"cpu.revision" = "r0p0";
+            pub const @"cpu.vendor_systick_config" = "0";
+            pub const @"cpu.endian" = "little";
+            pub const @"cpu.name" = "CM3";
+        };
+
+        pub const VectorTable = extern struct {
+            const Handler = micro.interrupt.Handler;
+            const unhandled = micro.interrupt.unhandled;
+
+            initial_stack_pointer: u32,
+            Reset: Handler = unhandled,
+            NMI: Handler = unhandled,
+            HardFault: Handler = unhandled,
+            MemManageFault: Handler = unhandled,
+            BusFault: Handler = unhandled,
+            UsageFault: Handler = unhandled,
+            reserved5: [4]u32 = undefined,
+            SVCall: Handler = unhandled,
+            DebugMonitor: Handler = unhandled,
+            reserved11: [1]u32 = undefined,
+            PendSV: Handler = unhandled,
+            SysTick: Handler = unhandled,
+            WDT: Handler = unhandled,
+            TIMER0: Handler = unhandled,
+            TIMER1: Handler = unhandled,
+            TIMER2: Handler = unhandled,
+            TIMER3: Handler = unhandled,
+            UART0: Handler = unhandled,
+            UART1: Handler = unhandled,
+            UART2: Handler = unhandled,
+            UART3: Handler = unhandled,
+            PWM1: Handler = unhandled,
+            I2C0: Handler = unhandled,
+            I2C1: Handler = unhandled,
+            I2C2: Handler = unhandled,
+            SPI: Handler = unhandled,
+            SSP0: Handler = unhandled,
+            SSP1: Handler = unhandled,
+            reserved30: [1]u32 = undefined,
+            RTC: Handler = unhandled,
+            EINT0: Handler = unhandled,
+            reserved33: [3]u32 = undefined,
+            ADC: Handler = unhandled,
+            reserved37: [1]u32 = undefined,
+            USB: Handler = unhandled,
+            CAN: Handler = unhandled,
+            DMA: Handler = unhandled,
+            I2S: Handler = unhandled,
+            ENET: Handler = unhandled,
+            RIT: Handler = unhandled,
+            MCPWM: Handler = unhandled,
+            QEI: Handler = unhandled,
+            reserved46: [2]u32 = undefined,
+            CANActivity: Handler = unhandled,
+        };
+
+        pub const peripherals = struct {
+            ///  General Purpose I/O
+            pub const GPIO = @ptrCast(*volatile types.GPIO, 0x2009c000);
+            ///  Watchdog Timer (WDT)
+            pub const WDT = @ptrCast(*volatile types.WDT, 0x40000000);
+            ///  Timer0/1/2/3
+            pub const TIMER0 = @ptrCast(*volatile types.TIMER0, 0x40004000);
+            ///  Timer0/1/2/3
+            pub const TIMER1 = @ptrCast(*volatile types.TIMER0, 0x40008000);
+            ///  UART0/2/3
+            pub const UART0 = @ptrCast(*volatile types.UART0, 0x4000c000);
+            ///  UART1
+            pub const UART1 = @ptrCast(*volatile types.UART1, 0x40010000);
+            ///  Pulse Width Modulators (PWM1)
+            pub const PWM1 = @ptrCast(*volatile types.PWM1, 0x40018000);
+            ///  I2C bus interface
+            pub const I2C0 = @ptrCast(*volatile types.I2C0, 0x4001c000);
+            ///  SPI
+            pub const SPI = @ptrCast(*volatile types.SPI, 0x40020000);
+            ///  Real Time Clock (RTC)
+            pub const RTC = @ptrCast(*volatile types.RTC, 0x40024000);
+            ///  GPIO
+            pub const GPIOINT = @ptrCast(*volatile types.GPIOINT, 0x40028080);
+            ///  Pin connect block
+            pub const PINCONNECT = @ptrCast(*volatile types.PINCONNECT, 0x4002c000);
+            ///  SSP1 controller
+            pub const SSP1 = @ptrCast(*volatile types.SSP1, 0x40030000);
+            ///  Analog-to-Digital Converter (ADC)
+            pub const ADC = @ptrCast(*volatile types.ADC, 0x40034000);
+            ///  CAN acceptance filter RAM
+            pub const CANAFRAM = @ptrCast(*volatile types.CANAFRAM, 0x40038000);
+            ///  CAN controller acceptance filter
+            pub const CANAF = @ptrCast(*volatile types.CANAF, 0x4003c000);
+            ///  Central CAN controller
+            pub const CCAN = @ptrCast(*volatile types.CCAN, 0x40040000);
+            ///  CAN1 controller
+            pub const CAN1 = @ptrCast(*volatile types.CAN1, 0x40044000);
+            ///  CAN1 controller
+            pub const CAN2 = @ptrCast(*volatile types.CAN1, 0x40048000);
+            ///  I2C bus interface
+            pub const I2C1 = @ptrCast(*volatile types.I2C0, 0x4005c000);
+            ///  SSP controller
+            pub const SSP0 = @ptrCast(*volatile types.SSP1, 0x40088000);
+            ///  Digital-to-Analog Converter (DAC)
+            pub const DAC = @ptrCast(*volatile types.DAC, 0x4008c000);
+            ///  Timer0/1/2/3
+            pub const TIMER2 = @ptrCast(*volatile types.TIMER0, 0x40090000);
+            ///  Timer0/1/2/3
+            pub const TIMER3 = @ptrCast(*volatile types.TIMER0, 0x40094000);
+            ///  UART0/2/3
+            pub const UART2 = @ptrCast(*volatile types.UART0, 0x40098000);
+            ///  UART0/2/3
+            pub const UART3 = @ptrCast(*volatile types.UART0, 0x4009c000);
+            ///  I2C bus interface
+            pub const I2C2 = @ptrCast(*volatile types.I2C0, 0x400a0000);
+            ///  I2S interface
+            pub const I2S = @ptrCast(*volatile types.I2S, 0x400a8000);
+            ///  Repetitive Interrupt Timer (RIT)
+            pub const RITIMER = @ptrCast(*volatile types.RITIMER, 0x400b0000);
+            ///  Motor Control PWM
+            pub const MCPWM = @ptrCast(*volatile types.MCPWM, 0x400b8000);
+            ///  Quadrature Encoder Interface (QEI)
+            pub const QEI = @ptrCast(*volatile types.QEI, 0x400bc000);
+            ///  System and clock control
+            pub const SYSCON = @ptrCast(*volatile types.SYSCON, 0x400fc000);
+            ///  Ethernet
+            pub const EMAC = @ptrCast(*volatile types.EMAC, 0x50000000);
+            ///  General purpose DMA controller
+            pub const GPDMA = @ptrCast(*volatile types.GPDMA, 0x50004000);
+            ///  USB device/host/OTG controller
+            pub const USB = @ptrCast(*volatile types.USB, 0x50008000);
+        };
+    };
+};
+
+pub const types = struct {
+    ///  Watchdog Timer (WDT)
+    pub const WDT = extern struct {
+        ///  Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer.
+        MOD: mmio.Mmio(packed struct(u32) {
+            ///  Watchdog enable bit. This bit is Set Only.
+            WDEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The watchdog timer is stopped.
+                    STOP = 0x0,
+                    ///  The watchdog timer is running.
+                    RUN = 0x1,
+                },
+            },
+            ///  Watchdog reset enable bit. This bit is Set Only. See Table 652.
+            WDRESET: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A watchdog timeout will not cause a chip reset.
+                    NORESET = 0x0,
+                    ///  A watchdog timeout will cause a chip reset.
+                    RESET = 0x1,
+                },
+            },
+            ///  Watchdog time-out flag. Set when the watchdog timer times out, cleared by software.
+            WDTOF: u1,
+            ///  Watchdog interrupt flag. Cleared by software.
+            WDINT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u28,
+        }),
+        ///  Watchdog timer constant register. The value in this register determines the time-out value.
+        TC: mmio.Mmio(packed struct(u32) {
+            ///  Watchdog time-out interval.
+            Count: u32,
+        }),
+        ///  Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.
+        FEED: mmio.Mmio(packed struct(u32) {
+            ///  Feed value should be 0xAA followed by 0x55.
+            Feed: u8,
+            padding: u24,
+        }),
+        ///  Watchdog timer value register. This register reads out the current value of the Watchdog timer.
+        TV: mmio.Mmio(packed struct(u32) {
+            ///  Counter timer value.
+            Count: u32,
+        }),
+        ///  Watchdog clock select register.
+        CLKSEL: mmio.Mmio(packed struct(u32) {
+            reserved1: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u30,
+            ///  If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0.
+            LOCK: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This bit is set to 0 on any reset. It cannot be cleared by software.
+                    UNLOCKED = 0x0,
+                    ///  Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register cannot be modified.
+                    LOCKED = 0x1,
+                },
+            },
+        }),
+    };
+
+    ///  Timer0/1/2/3
+    pub const TIMER0 = extern struct {
+        ///  Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
+        IR: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt flag for match channel 0.
+            MR0INT: u1,
+            ///  Interrupt flag for match channel 1.
+            MR1INT: u1,
+            ///  Interrupt flag for match channel 2.
+            MR2INT: u1,
+            ///  Interrupt flag for match channel 3.
+            MR3INT: u1,
+            ///  Interrupt flag for capture channel 0 event.
+            CR0INT: u1,
+            ///  Interrupt flag for capture channel 1 event.
+            CR1INT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u26,
+        }),
+        ///  Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
+        TCR: mmio.Mmio(packed struct(u32) {
+            ///  When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
+            CEN: u1,
+            ///  When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
+            CRST: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u30,
+        }),
+        ///  Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
+        TC: mmio.Mmio(packed struct(u32) {
+            ///  Timer counter value.
+            TC: u32,
+        }),
+        ///  Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.
+        PR: mmio.Mmio(packed struct(u32) {
+            ///  Prescale counter maximum value.
+            PM: u32,
+        }),
+        ///  Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
+        PC: mmio.Mmio(packed struct(u32) {
+            ///  Prescale counter value.
+            PC: u32,
+        }),
+        ///  Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
+        MCR: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt on MR0
+            MR0I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt is generated when MR0 matches the value in the TC.
+                    INTERRUPT_IS_GENERAT = 0x1,
+                    ///  Interrupt is disabled
+                    INTERRUPT_IS_DISABLE = 0x0,
+                },
+            },
+            ///  Reset on MR0
+            MR0R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  TC will be reset if MR0 matches it.
+                    TC_WILL_BE_RESET_IF_ = 0x1,
+                    ///  Feature disabled.
+                    FEATURE_DISABLED_ = 0x0,
+                },
+            },
+            ///  Stop on MR0
+            MR0S: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
+                    TC_AND_PC_WILL_BE_ST = 0x1,
+                    ///  Feature disabled.
+                    FEATURE_DISABLED_ = 0x0,
+                },
+            },
+            ///  Interrupt on MR1
+            MR1I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt is generated when MR1 matches the value in the TC.
+                    INTERRUPT_IS_GENERAT = 0x1,
+                    ///  Interrupt is disabled.
+                    INTERRUPT_IS_DISABLE = 0x0,
+                },
+            },
+            ///  Reset on MR1
+            MR1R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  TC will be reset if MR1 matches it.
+                    TC_WILL_BE_RESET_IF_ = 0x1,
+                    ///  Feature disabled.
+                    FEATURE_DISABLED_ = 0x0,
+                },
+            },
+            ///  Stop on MR1
+            MR1S: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
+                    TC_AND_PC_WILL_BE_ST = 0x1,
+                    ///  Feature disabled.
+                    FEATURE_DISABLED_ = 0x0,
+                },
+            },
+            ///  Interrupt on MR2
+            MR2I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt is generated when MR2 matches the value in the TC.
+                    INTERRUPT_IS_GENERAT = 0x1,
+                    ///  Interrupt is disabled
+                    INTERRUPT_IS_DISABLE = 0x0,
+                },
+            },
+            ///  Reset on MR2
+            MR2R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  TC will be reset if MR2 matches it.
+                    TC_WILL_BE_RESET_IF_ = 0x1,
+                    ///  Feature disabled.
+                    FEATURE_DISABLED_ = 0x0,
+                },
+            },
+            ///  Stop on MR2.
+            MR2S: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC
+                    TC_AND_PC_WILL_BE_ST = 0x1,
+                    ///  Feature disabled.
+                    FEATURE_DISABLED_ = 0x0,
+                },
+            },
+            ///  Interrupt on MR3
+            MR3I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt is generated when MR3 matches the value in the TC.
+                    INTERRUPT_IS_GENERAT = 0x1,
+                    ///  This interrupt is disabled
+                    THIS_INTERRUPT_IS_DI = 0x0,
+                },
+            },
+            ///  Reset on MR3
+            MR3R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  TC will be reset if MR3 matches it.
+                    TC_WILL_BE_RESET_IF_ = 0x1,
+                    ///  Feature disabled.
+                    FEATURE_DISABLED_ = 0x0,
+                },
+            },
+            ///  Stop on MR3
+            MR3S: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
+                    TC_AND_PC_WILL_BE_ST = 0x1,
+                    ///  Feature disabled.
+                    FEATURE_DISABLED_ = 0x0,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u20,
+        }),
+        reserved40: [16]u8,
+        ///  Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Capture on CAPn.0 rising edge
+            CAP0RE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC.
+                    ENABLE = 0x1,
+                    ///  This feature is disabled.
+                    DISABLE = 0x0,
+                },
+            },
+            ///  Capture on CAPn.0 falling edge
+            CAP0FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC.
+                    ENABLE = 0x1,
+                    ///  This feature is disabled.
+                    DISABLE = 0x0,
+                },
+            },
+            ///  Interrupt on CAPn.0 event
+            CAP0I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A CR0 load due to a CAPn.0 event will generate an interrupt.
+                    ENABLE = 0x1,
+                    ///  This feature is disabled.
+                    DISABLE = 0x0,
+                },
+            },
+            ///  Capture on CAPn.1 rising edge
+            CAP1RE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC.
+                    ENABLE = 0x1,
+                    ///  This feature is disabled.
+                    DISABLE = 0x0,
+                },
+            },
+            ///  Capture on CAPn.1 falling edge
+            CAP1FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC.
+                    ENABLE = 0x1,
+                    ///  This feature is disabled.
+                    DISABLE = 0x0,
+                },
+            },
+            ///  Interrupt on CAPn.1 event
+            CAP1I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A CR1 load due to a CAPn.1 event will generate an interrupt.
+                    ENABLE = 0x1,
+                    ///  This feature is disabled.
+                    DISABLE = 0x0,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u26,
+        }),
+        reserved60: [16]u8,
+        ///  External Match Register. The EMR controls the external match pins.
+        EMR: mmio.Mmio(packed struct(u32) {
+            ///  External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).
+            EM0: u1,
+            ///  External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high).
+            EM1: u1,
+            ///  External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).
+            EM2: u1,
+            ///  External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).
+            EM3: u1,
+            ///  External Match Control 0. Determines the functionality of External Match 0.
+            EMC0: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Do Nothing.
+                    DO_NOTHING_ = 0x0,
+                    ///  Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
+                    CLEAR_THE_CORRESPOND = 0x1,
+                    ///  Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
+                    SET_THE_CORRESPONDIN = 0x2,
+                    ///  Toggle the corresponding External Match bit/output.
+                    TOGGLE_THE_CORRESPON = 0x3,
+                },
+            },
+            ///  External Match Control 1. Determines the functionality of External Match 1.
+            EMC1: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Do Nothing.
+                    DO_NOTHING_ = 0x0,
+                    ///  Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
+                    CLEAR_THE_CORRESPOND = 0x1,
+                    ///  Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
+                    SET_THE_CORRESPONDIN = 0x2,
+                    ///  Toggle the corresponding External Match bit/output.
+                    TOGGLE_THE_CORRESPON = 0x3,
+                },
+            },
+            ///  External Match Control 2. Determines the functionality of External Match 2.
+            EMC2: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Do Nothing.
+                    DO_NOTHING_ = 0x0,
+                    ///  Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
+                    CLEAR_THE_CORRESPOND = 0x1,
+                    ///  Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
+                    SET_THE_CORRESPONDIN = 0x2,
+                    ///  Toggle the corresponding External Match bit/output.
+                    TOGGLE_THE_CORRESPON = 0x3,
+                },
+            },
+            ///  External Match Control 3. Determines the functionality of External Match 3.
+            EMC3: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Do Nothing.
+                    DO_NOTHING_ = 0x0,
+                    ///  Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
+                    CLEAR_THE_CORRESPOND = 0x1,
+                    ///  Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
+                    SET_THE_CORRESPONDIN = 0x2,
+                    ///  Toggle the corresponding External Match bit/output.
+                    TOGGLE_THE_CORRESPON = 0x3,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u20,
+        }),
+        reserved112: [48]u8,
+        ///  Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
+        CTCR: mmio.Mmio(packed struct(u32) {
+            ///  Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
+            CTMODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Timer Mode: every rising PCLK edge
+                    TIMER_MODE_EVERY_RI = 0x0,
+                    ///  Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.
+                    RISING = 0x1,
+                    ///  Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.
+                    FALLING = 0x2,
+                    ///  Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.
+                    DUALEDGE = 0x3,
+                },
+            },
+            ///  Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
+            CINSEL: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CAPn.0 for TIMERn
+                    CAPN_0_FOR_TIMERN = 0x0,
+                    ///  CAPn.1 for TIMERn
+                    CAPN_1_FOR_TIMERN = 0x1,
+                    _,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u28,
+        }),
+    };
+
+    ///  General Purpose I/O
+    pub const GPIO = struct {};
+
+    ///  UART0/2/3
+    pub const UART0 = extern struct {
+        ///  Receiver Buffer Register. Contains the next received character to be read (DLAB =0).
+        RBR: mmio.Mmio(packed struct(u32) {
+            ///  The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO.
+            RBR: u8,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).
+        DLM: mmio.Mmio(packed struct(u32) {
+            ///  The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn.
+            DLMSB: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  Interrupt ID Register. Identifies which interrupt(s) are pending.
+        IIR: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].
+            INTSTATUS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  At least one interrupt is pending.
+                    AT_LEAST_ONE_INTERRU = 0x0,
+                    ///  No interrupt is pending.
+                    NO_INTERRUPT_IS_PEND = 0x1,
+                },
+            },
+            ///  Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).
+            INTID: packed union {
+                raw: u3,
+                value: enum(u3) {
+                    ///  1 - Receive Line Status (RLS).
+                    @"1_RECEIVE_LINE_S" = 0x3,
+                    ///  2a - Receive Data Available (RDA).
+                    @"2A__RECEIVE_DATA_AV" = 0x2,
+                    ///  2b - Character Time-out Indicator (CTI).
+                    @"2B__CHARACTER_TIME_" = 0x6,
+                    ///  3 - THRE Interrupt
+                    @"3_THRE_INTERRUPT" = 0x1,
+                    _,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  Copies of UnFCR[0].
+            FIFOENABLE: u2,
+            ///  End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
+            ABEOINT: u1,
+            ///  Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.
+            ABTOINT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u22,
+        }),
+        ///  Line Control Register. Contains controls for frame formatting and break generation.
+        LCR: mmio.Mmio(packed struct(u32) {
+            ///  Word Length Select.
+            WLS: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  5-bit character length
+                    @"5_BIT_CHARACTER_LENG" = 0x0,
+                    ///  6-bit character length
+                    @"6_BIT_CHARACTER_LENG" = 0x1,
+                    ///  7-bit character length
+                    @"7_BIT_CHARACTER_LENG" = 0x2,
+                    ///  8-bit character length
+                    @"8_BIT_CHARACTER_LENG" = 0x3,
+                },
+            },
+            ///  Stop Bit Select
+            SBS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  1 stop bit.
+                    @"1_STOP_BIT_" = 0x0,
+                    ///  2 stop bits (1.5 if UnLCR[1:0]=00).
+                    @"2_STOP_BITS_1_5_IF_" = 0x1,
+                },
+            },
+            ///  Parity Enable.
+            PE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable parity generation and checking.
+                    DISABLE_PARITY_GENER = 0x0,
+                    ///  Enable parity generation and checking.
+                    ENABLE_PARITY_GENERA = 0x1,
+                },
+            },
+            ///  Parity Select
+            PS: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
+                    ODD_PARITY_NUMBER_O = 0x0,
+                    ///  Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.
+                    EVEN_PARITY_NUMBER_ = 0x1,
+                    ///  Forced 1 stick parity.
+                    FORCED_1_STICK_PARIT = 0x2,
+                    ///  Forced 0 stick parity.
+                    FORCED_0_STICK_PARIT = 0x3,
+                },
+            },
+            ///  Break Control
+            BC: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable break transmission.
+                    DISABLE_BREAK_TRANSM = 0x0,
+                    ///  Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high.
+                    ENABLE_BREAK_TRANSMI = 0x1,
+                },
+            },
+            ///  Divisor Latch Access Bit
+            DLAB: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable access to Divisor Latches.
+                    DISABLE_ACCESS_TO_DI = 0x0,
+                    ///  Enable access to Divisor Latches.
+                    ENABLE_ACCESS_TO_DIV = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        reserved20: [4]u8,
+        ///  Line Status Register. Contains flags for transmit and receive status, including line errors.
+        LSR: mmio.Mmio(packed struct(u32) {
+            ///  Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.
+            RDR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The UARTn receiver FIFO is empty.
+                    EMPTY = 0x0,
+                    ///  The UARTn receiver FIFO is not empty.
+                    NOTEMPTY = 0x1,
+                },
+            },
+            ///  Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.
+            OE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Overrun error status is inactive.
+                    INACTIVE = 0x0,
+                    ///  Overrun error status is active.
+                    ACTIVE = 0x1,
+                },
+            },
+            ///  Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.
+            PE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Parity error status is inactive.
+                    INACTIVE = 0x0,
+                    ///  Parity error status is active.
+                    ACTIVE = 0x1,
+                },
+            },
+            ///  Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.
+            FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Framing error status is inactive.
+                    INACTIVE = 0x0,
+                    ///  Framing error status is active.
+                    ACTIVE = 0x1,
+                },
+            },
+            ///  Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.
+            BI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Break interrupt status is inactive.
+                    INACTIVE = 0x0,
+                    ///  Break interrupt status is active.
+                    ACTIVE = 0x1,
+                },
+            },
+            ///  Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.
+            THRE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  UnTHR contains valid data.
+                    VALIDDATA = 0x0,
+                    ///  UnTHR is empty.
+                    EMPTY = 0x1,
+                },
+            },
+            ///  Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.
+            TEMT: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  UnTHR and/or the UnTSR contains valid data.
+                    VALIDDATA = 0x0,
+                    ///  UnTHR and the UnTSR are empty.
+                    EMPTY = 0x1,
+                },
+            },
+            ///  Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.
+            RXFE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  UnRBR contains no UARTn RX errors or UnFCR[0]=0.
+                    NOERROR = 0x0,
+                    ///  UARTn RBR contains at least one UARTn RX error.
+                    ERRORS = 0x1,
+                },
+            },
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        reserved28: [4]u8,
+        ///  Scratch Pad Register. 8-bit temporary storage for software.
+        SCR: mmio.Mmio(packed struct(u32) {
+            ///  A readable, writable byte.
+            PAD: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  Auto-baud Control Register. Contains controls for the auto-baud feature.
+        ACR: mmio.Mmio(packed struct(u32) {
+            ///  Start bit. This bit is automatically cleared after auto-baud completion.
+            START: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Auto-baud stop (auto-baud is not running).
+                    AUTO_BAUD_STOP_AUTO = 0x0,
+                    ///  Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.
+                    AUTO_BAUD_START_AUT = 0x1,
+                },
+            },
+            ///  Auto-baud mode select bit.
+            MODE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Mode 0.
+                    MODE_0_ = 0x0,
+                    ///  Mode 1.
+                    MODE_1_ = 0x1,
+                },
+            },
+            ///  Restart bit.
+            AUTORESTART: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No restart.
+                    NO_RESTART_ = 0x0,
+                    ///  Restart in case of time-out (counter restarts at next UARTn Rx falling edge)
+                    RESTART_IN_CASE_OF_T = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u5,
+            ///  End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.
+            ABEOINTCLR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No impact.
+                    NO_IMPACT_ = 0x0,
+                    ///  Clear the corresponding interrupt in the IIR.
+                    CLEAR_THE_CORRESPOND = 0x1,
+                },
+            },
+            ///  Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.
+            ABTOINTCLR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No impact.
+                    NO_IMPACT_ = 0x0,
+                    ///  Clear the corresponding interrupt in the IIR.
+                    CLEAR_THE_CORRESPOND = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u22,
+        }),
+        reserved40: [4]u8,
+        ///  Fractional Divider Register. Generates a clock input for the baud rate divider.
+        FDR: mmio.Mmio(packed struct(u32) {
+            ///  Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.
+            DIVADDVAL: u4,
+            ///  Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not.
+            MULVAL: u4,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        reserved48: [4]u8,
+        ///  Transmit Enable Register. Turns off UART transmitter for use with software flow control.
+        TER: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u7,
+            ///  When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character.
+            TXEN: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        reserved76: [24]u8,
+        ///  RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
+        RS485CTRL: mmio.Mmio(packed struct(u32) {
+            ///  NMM enable.
+            NMMEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.
+                    DISABLED = 0x0,
+                    ///  RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation.
+                    ENABLED = 0x1,
+                },
+            },
+            ///  Receiver enable.
+            RXDIS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The receiver is enabled.
+                    ENABLED = 0x0,
+                    ///  The receiver is disabled.
+                    DISABLED = 0x1,
+                },
+            },
+            ///  AAD enable.
+            AADEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Auto Address Detect (AAD) is disabled.
+                    DISABLED = 0x0,
+                    ///  Auto Address Detect (AAD) is enabled.
+                    ENABLED = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  Direction control enable.
+            DCTRL: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable Auto Direction Control.
+                    DISABLE_AUTO_DIRECTI = 0x0,
+                    ///  Enable Auto Direction Control.
+                    ENABLE_AUTO_DIRECTIO = 0x1,
+                },
+            },
+            ///  Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.
+            OINV: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.
+                    DIRLOW = 0x0,
+                    ///  The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.
+                    DIRHIGH = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u26,
+        }),
+        ///  RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
+        RS485ADRMATCH: mmio.Mmio(packed struct(u32) {
+            ///  Contains the address match value.
+            ADRMATCH: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  RS-485/EIA-485 direction control delay.
+        RS485DLY: mmio.Mmio(packed struct(u32) {
+            ///  Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter.
+            DLY: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+    };
+
+    ///  UART1
+    pub const UART1 = extern struct {
+        ///  DLAB =0 Receiver Buffer Register. Contains the next received character to be read.
+        RBR: mmio.Mmio(packed struct(u32) {
+            ///  The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO.
+            RBR: u8,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.
+        DLM: mmio.Mmio(packed struct(u32) {
+            ///  The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1.
+            DLMSB: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  Interrupt ID Register. Identifies which interrupt(s) are pending.
+        IIR: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].
+            INTSTATUS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  At least one interrupt is pending.
+                    AT_LEAST_ONE_INTERRU = 0x0,
+                    ///  No interrupt is pending.
+                    NO_INTERRUPT_IS_PEND = 0x1,
+                },
+            },
+            ///  Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).
+            INTID: packed union {
+                raw: u3,
+                value: enum(u3) {
+                    ///  1 - Receive Line Status (RLS).
+                    RLS = 0x3,
+                    ///  2a - Receive Data Available (RDA).
+                    RDA = 0x2,
+                    ///  2b - Character Time-out Indicator (CTI).
+                    CTI = 0x6,
+                    ///  3 - THRE Interrupt.
+                    THRE = 0x1,
+                    ///  4 - Modem Interrupt.
+                    MODEM = 0x0,
+                    _,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u2,
+            ///  Copies of FCR[0].
+            FIFOENABLE: u2,
+            ///  End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
+            ABEOINT: u1,
+            ///  Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.
+            ABTOINT: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u22,
+        }),
+        ///  Line Control Register. Contains controls for frame formatting and break generation.
+        LCR: mmio.Mmio(packed struct(u32) {
+            ///  Word Length Select.
+            WLS: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  5-bit character length.
+                    @"5_BIT_CHARACTER_LENG" = 0x0,
+                    ///  6-bit character length.
+                    @"6_BIT_CHARACTER_LENG" = 0x1,
+                    ///  7-bit character length.
+                    @"7_BIT_CHARACTER_LENG" = 0x2,
+                    ///  8-bit character length.
+                    @"8_BIT_CHARACTER_LENG" = 0x3,
+                },
+            },
+            ///  Stop Bit Select.
+            SBS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  1 stop bit.
+                    @"1_STOP_BIT_" = 0x0,
+                    ///  2 stop bits (1.5 if LCR[1:0]=00).
+                    @"2_STOP_BITS_1_5_IF_" = 0x1,
+                },
+            },
+            ///  Parity Enable.
+            PE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable parity generation and checking.
+                    DISABLE_PARITY_GENER = 0x0,
+                    ///  Enable parity generation and checking.
+                    ENABLE_PARITY_GENERA = 0x1,
+                },
+            },
+            ///  Parity Select.
+            PS: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
+                    ODD_PARITY_NUMBER_O = 0x0,
+                    ///  Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.
+                    EVEN_PARITY_NUMBER_ = 0x1,
+                    ///  Forced 1 stick parity.
+                    FORCED1STICK_PAR = 0x2,
+                    ///  Forced 0 stick parity.
+                    FORCED0STICK_PAR = 0x3,
+                },
+            },
+            ///  Break Control.
+            BC: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable break transmission.
+                    DISABLE_BREAK_TRANSM = 0x0,
+                    ///  Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high.
+                    ENABLE_BREAK_TRANSMI = 0x1,
+                },
+            },
+            ///  Divisor Latch Access Bit (DLAB)
+            DLAB: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable access to Divisor Latches.
+                    DISABLE_ACCESS_TO_DI = 0x0,
+                    ///  Enable access to Divisor Latches.
+                    ENABLE_ACCESS_TO_DIV = 0x1,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  Modem Control Register. Contains controls for flow control handshaking and loopback mode.
+        MCR: mmio.Mmio(packed struct(u32) {
+            ///  DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.
+            DTRCTRL: u1,
+            ///  RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.
+            RTSCTRL: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u2,
+            ///  Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.
+            LMS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable modem loopback mode.
+                    DISABLE_MODEM_LOOPBA = 0x0,
+                    ///  Enable modem loopback mode.
+                    ENABLE_MODEM_LOOPBAC = 0x1,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u1,
+            ///  RTS enable.
+            RTSEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable auto-rts flow control.
+                    DISABLE_AUTO_RTS_FLO = 0x0,
+                    ///  Enable auto-rts flow control.
+                    ENABLE_AUTO_RTS_FLOW = 0x1,
+                },
+            },
+            ///  CTS enable.
+            CTSEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable auto-cts flow control.
+                    DISABLE_AUTO_CTS_FLO = 0x0,
+                    ///  Enable auto-cts flow control.
+                    ENABLE_AUTO_CTS_FLOW = 0x1,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  Line Status Register. Contains flags for transmit and receive status, including line errors.
+        LSR: mmio.Mmio(packed struct(u32) {
+            ///  Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.
+            RDR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The UART1 receiver FIFO is empty.
+                    EMPTY = 0x0,
+                    ///  The UART1 receiver FIFO is not empty.
+                    NOTEMPTY = 0x1,
+                },
+            },
+            ///  Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.
+            OE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Overrun error status is inactive.
+                    INACTIVE = 0x0,
+                    ///  Overrun error status is active.
+                    ACTIVE = 0x1,
+                },
+            },
+            ///  Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.
+            PE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Parity error status is inactive.
+                    INACTIVE = 0x0,
+                    ///  Parity error status is active.
+                    ACTIVE = 0x1,
+                },
+            },
+            ///  Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.
+            FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Framing error status is inactive.
+                    INACTIVE = 0x0,
+                    ///  Framing error status is active.
+                    ACTIVE = 0x1,
+                },
+            },
+            ///  Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.
+            BI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Break interrupt status is inactive.
+                    INACTIVE = 0x0,
+                    ///  Break interrupt status is active.
+                    ACTIVE = 0x1,
+                },
+            },
+            ///  Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.
+            THRE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  THR contains valid data.
+                    VALID = 0x0,
+                    ///  THR is empty.
+                    THR_IS_EMPTY_ = 0x1,
+                },
+            },
+            ///  Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.
+            TEMT: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  THR and/or the TSR contains valid data.
+                    VALID = 0x0,
+                    ///  THR and the TSR are empty.
+                    EMPTY = 0x1,
+                },
+            },
+            ///  Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.
+            RXFE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  RBR contains no UART1 RX errors or FCR[0]=0.
+                    NOERROR = 0x0,
+                    ///  UART1 RBR contains at least one UART1 RX error.
+                    ERRORS = 0x1,
+                },
+            },
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  Modem Status Register. Contains handshake signal status flags.
+        MSR: mmio.Mmio(packed struct(u32) {
+            ///  Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.
+            DCTS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No change detected on modem input, CTS.
+                    NO_CHANGE_DETECTED_O = 0x0,
+                    ///  State change detected on modem input, CTS.
+                    STATE_CHANGE_DETECTE = 0x1,
+                },
+            },
+            ///  Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.
+            DDSR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No change detected on modem input, DSR.
+                    NO_CHANGE_DETECTED_O = 0x0,
+                    ///  State change detected on modem input, DSR.
+                    STATE_CHANGE_DETECTE = 0x1,
+                },
+            },
+            ///  Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.
+            TERI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No change detected on modem input, RI.
+                    NO_CHANGE_DETECTED_O = 0x0,
+                    ///  Low-to-high transition detected on RI.
+                    LOW_TO_HIGH_TRANSITI = 0x1,
+                },
+            },
+            ///  Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.
+            DDCD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No change detected on modem input, DCD.
+                    NO_CHANGE_DETECTED_O = 0x0,
+                    ///  State change detected on modem input, DCD.
+                    STATE_CHANGE_DETECTE = 0x1,
+                },
+            },
+            ///  Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.
+            CTS: u1,
+            ///  Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.
+            DSR: u1,
+            ///  Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.
+            RI: u1,
+            ///  Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.
+            DCD: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  Scratch Pad Register. 8-bit temporary storage for software.
+        SCR: mmio.Mmio(packed struct(u32) {
+            ///  A readable, writable byte.
+            Pad: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  Auto-baud Control Register. Contains controls for the auto-baud feature.
+        ACR: mmio.Mmio(packed struct(u32) {
+            ///  Auto-baud start bit. This bit is automatically cleared after auto-baud completion.
+            START: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Auto-baud stop (auto-baud is not running).
+                    STOP = 0x0,
+                    ///  Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.
+                    START = 0x1,
+                },
+            },
+            ///  Auto-baud mode select bit.
+            MODE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Mode 0.
+                    MODE_0_ = 0x0,
+                    ///  Mode 1.
+                    MODE_1_ = 0x1,
+                },
+            },
+            ///  Auto-baud restart bit.
+            AUTORESTART: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No restart
+                    NO_RESTART = 0x0,
+                    ///  Restart in case of time-out (counter restarts at next UART1 Rx falling edge)
+                    RESTART_IN_CASE_OF_T = 0x1,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u5,
+            ///  End of auto-baud interrupt clear bit (write-only).
+            ABEOINTCLR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Writing a 0 has no impact.
+                    WRITING_A_0_HAS_NO_I = 0x0,
+                    ///  Writing a 1 will clear the corresponding interrupt in the IIR.
+                    WRITING_A_1_WILL_CLE = 0x1,
+                },
+            },
+            ///  Auto-baud time-out interrupt clear bit (write-only).
+            ABTOINTCLR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Writing a 0 has no impact.
+                    WRITING_A_0_HAS_NO_I = 0x0,
+                    ///  Writing a 1 will clear the corresponding interrupt in the IIR.
+                    WRITING_A_1_WILL_CLE = 0x1,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u22,
+        }),
+        reserved40: [4]u8,
+        ///  Fractional Divider Register. Generates a clock input for the baud rate divider.
+        FDR: mmio.Mmio(packed struct(u32) {
+            ///  Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate.
+            DIVADDVAL: u4,
+            ///  Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not.
+            MULVAL: u4,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        reserved48: [4]u8,
+        ///  Transmit Enable Register. Turns off UART transmitter for use with software flow control.
+        TER: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u7,
+            ///  When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.
+            TXEN: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        reserved76: [24]u8,
+        ///  RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
+        RS485CTRL: mmio.Mmio(packed struct(u32) {
+            ///  RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.
+            NMMEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.
+                    ENABLED_IN_THIS_MOD = 0x1,
+                },
+            },
+            ///  Receive enable.
+            RXDIS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Enabled.
+                    ENABLED_ = 0x0,
+                    ///  Disabled.
+                    DISABLED_ = 0x1,
+                },
+            },
+            ///  Auto Address Detect (AAD) enable.
+            AADEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Enabled.
+                    ENABLED_ = 0x1,
+                },
+            },
+            ///  Direction control.
+            SEL: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.
+                    RTS_IF_DIRECTION_CO = 0x0,
+                    ///  DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.
+                    DTR_IF_DIRECTION_CO = 0x1,
+                },
+            },
+            ///  Direction control enable.
+            DCTRL: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable Auto Direction Control.
+                    DISABLE_AUTO_DIRECTI = 0x0,
+                    ///  Enable Auto Direction Control.
+                    ENABLE_AUTO_DIRECTIO = 0x1,
+                },
+            },
+            ///  Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
+            OINV: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.
+                    LOW_THE_DIRECTION_C = 0x0,
+                    ///  HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.
+                    HIGH_THE_DIRECTION_ = 0x1,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u26,
+        }),
+        ///  RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
+        RS485ADRMATCH: mmio.Mmio(packed struct(u32) {
+            ///  Contains the address match value.
+            ADRMATCH: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  RS-485/EIA-485 direction control delay.
+        RS485DLY: mmio.Mmio(packed struct(u32) {
+            ///  Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.
+            DLY: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+    };
+
+    ///  Pulse Width Modulators (PWM1)
+    pub const PWM1 = extern struct {
+        ///  Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending.
+        IR: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt flag for PWM match channel 0.
+            PWMMR0INT: u1,
+            ///  Interrupt flag for PWM match channel 1.
+            PWMMR1INT: u1,
+            ///  Interrupt flag for PWM match channel 2.
+            PWMMR2INT: u1,
+            ///  Interrupt flag for PWM match channel 3.
+            PWMMR3INT: u1,
+            ///  Interrupt flag for capture input 0
+            PWMCAP0INT: u1,
+            ///  Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR).
+            PWMCAP1INT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  Interrupt flag for PWM match channel 4.
+            PWMMR4INT: u1,
+            ///  Interrupt flag for PWM match channel 5.
+            PWMMR5INT: u1,
+            ///  Interrupt flag for PWM match channel 6.
+            PWMMR6INT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u21,
+        }),
+        ///  Timer Control Register. The TCR is used to control the Timer Counter functions.
+        TCR: mmio.Mmio(packed struct(u32) {
+            ///  Counter Enable
+            CE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The PWM Timer Counter and PWM Prescale Counter are enabled for counting.
+                    THE_PWM_TIMER_COUNTE = 0x1,
+                    ///  The counters are disabled.
+                    THE_COUNTERS_ARE_DIS = 0x0,
+                },
+            },
+            ///  Counter Reset
+            CR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero.
+                    THE_PWM_TIMER_COUNTE = 0x1,
+                    ///  Clear reset.
+                    CLEAR_RESET_ = 0x0,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  PWM Enable
+            PWMEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective.
+                    PWM_MODE_IS_ENABLED_ = 0x1,
+                    ///  Timer mode is enabled (counter resets to 0).
+                    TIMER_MODE_IS_ENABLE = 0x0,
+                },
+            },
+            ///  Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1).
+            MDIS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Master use. PWM0 is the master, and both PWMs are enabled for counting.
+                    MASTER_USE_PWM0_IS_ = 0x1,
+                    ///  Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs.
+                    INDIVIDUAL_USE_THE_ = 0x0,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u27,
+        }),
+        ///  Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
+        TC: mmio.Mmio(packed struct(u32) {
+            ///  Timer counter value.
+            TC: u32,
+        }),
+        ///  Prescale Register. Determines how often the PWM counter is incremented.
+        PR: mmio.Mmio(packed struct(u32) {
+            ///  Prescale counter maximum value.
+            PM: u32,
+        }),
+        ///  Prescale Counter. Prescaler for the main PWM counter.
+        PC: mmio.Mmio(packed struct(u32) {
+            ///  Prescale counter value.
+            PC: u32,
+        }),
+        ///  Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs.
+        MCR: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt PWM0
+            PWMMR0I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC.
+                    INTERRUPT_ON_PWMMR0 = 0x1,
+                },
+            },
+            ///  Reset PWM0
+            PWMMR0R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it.
+                    RESET_ON_PWMMR0_THE = 0x1,
+                },
+            },
+            ///  Stop PWM0
+            PWMMR0S: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled
+                    DISABLED = 0x0,
+                    ///  Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.
+                    STOP_ON_PWMMR0_THE_ = 0x1,
+                },
+            },
+            ///  Interrupt PWM1
+            PWMMR1I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC.
+                    INTERRUPT_ON_PWMMR1 = 0x1,
+                },
+            },
+            ///  Reset PWM1
+            PWMMR1R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it.
+                    RESET_ON_PWMMR1_THE = 0x1,
+                },
+            },
+            ///  Stop PWM1
+            PWMMR1S: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled
+                    DISABLED = 0x0,
+                    ///  Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC.
+                    STOP_ON_PWMMR1_THE_ = 0x1,
+                },
+            },
+            ///  Interrupt PWM0
+            PWMMR2I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC.
+                    INTERRUPT_ON_PWMMR2 = 0x1,
+                },
+            },
+            ///  Reset PWM0
+            PWMMR2R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it.
+                    RESET_ON_PWMMR2_THE = 0x1,
+                },
+            },
+            ///  Stop PWM0
+            PWMMR2S: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled
+                    DISABLED = 0x0,
+                    ///  Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.
+                    STOP_ON_PWMMR2_THE_ = 0x1,
+                },
+            },
+            ///  Interrupt PWM3
+            PWMMR3I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC.
+                    INTERRUPT_ON_PWMMR3 = 0x1,
+                },
+            },
+            ///  Reset PWM3
+            PWMMR3R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it.
+                    RESET_ON_PWMMR3_THE = 0x1,
+                },
+            },
+            ///  Stop PWM0
+            PWMMR3S: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled
+                    DISABLED = 0x0,
+                    ///  Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.
+                    STOP_ON_PWMMR3_THE_ = 0x1,
+                },
+            },
+            ///  Interrupt PWM4
+            PWMMR4I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC.
+                    INTERRUPT_ON_PWMMR4 = 0x1,
+                },
+            },
+            ///  Reset PWM4
+            PWMMR4R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it.
+                    RESET_ON_PWMMR4_THE = 0x1,
+                },
+            },
+            ///  Stop PWM4
+            PWMMR4S: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled
+                    DISABLED = 0x0,
+                    ///  Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC.
+                    STOP_ON_PWMMR4_THE_ = 0x1,
+                },
+            },
+            ///  Interrupt PWM5
+            PWMMR5I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC.
+                    INTERRUPT_ON_PWMMR5 = 0x1,
+                },
+            },
+            ///  Reset PWM5
+            PWMMR5R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it.
+                    RESET_ON_PWMMR5_THE = 0x1,
+                },
+            },
+            ///  Stop PWM5
+            PWMMR5S: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled
+                    DISABLED = 0x0,
+                    ///  Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC.
+                    STOP_ON_PWMMR5_THE_ = 0x1,
+                },
+            },
+            ///  Interrupt PWM6
+            PWMMR6I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC.
+                    INTERRUPT_ON_PWMMR6 = 0x1,
+                },
+            },
+            ///  Reset PWM6
+            PWMMR6R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it.
+                    RESET_ON_PWMMR6_THE = 0x1,
+                },
+            },
+            ///  Stop PWM6
+            PWMMR6S: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled
+                    DISABLED = 0x0,
+                    ///  Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC.
+                    STOP_ON_PWMMR6_THE_ = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u11,
+        }),
+        reserved40: [16]u8,
+        ///  Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event.
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Capture on PWMn_CAP0 rising edge
+            CAP0_R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled. This feature is disabled.
+                    DISABLED_THIS_FEATU = 0x0,
+                    ///  Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC.
+                    RISING_EDGE_A_SYNCH = 0x1,
+                },
+            },
+            ///  Capture on PWMn_CAP0 falling edge
+            CAP0_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled. This feature is disabled.
+                    DISABLED_THIS_FEATU = 0x0,
+                    ///  Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC.
+                    FALLING_EDGE_A_SYNC = 0x1,
+                },
+            },
+            ///  Interrupt on PWMn_CAP0 event
+            CAP0_I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled. This feature is disabled.
+                    DISABLED_THIS_FEATU = 0x0,
+                    ///  Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt.
+                    INTERRUPT_A_CR0_LOA = 0x1,
+                },
+            },
+            ///  Capture on PWMn_CAP1 rising edge. Reserved for PWM0.
+            CAP1_R: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled. This feature is disabled.
+                    DISABLED_THIS_FEATU = 0x0,
+                    ///  Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC.
+                    RISING_EDGE_A_SYNCH = 0x1,
+                },
+            },
+            ///  Capture on PWMn_CAP1 falling edge. Reserved for PWM0.
+            CAP1_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled. This feature is disabled.
+                    DISABLED_THIS_FEATU = 0x0,
+                    ///  Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC.
+                    FALLING_EDGE_A_SYNC = 0x1,
+                },
+            },
+            ///  Interrupt on PWMn_CAP1 event. Reserved for PWM0.
+            CAP1_I: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled. This feature is disabled.
+                    DISABLED_THIS_FEATU = 0x0,
+                    ///  Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt.
+                    INTERRUPT_A_CR1_LOA = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u26,
+        }),
+        reserved76: [32]u8,
+        ///  PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs.
+        PCR: mmio.Mmio(packed struct(u32) {
+            ///  Reserved.
+            RESERVED: u2,
+            ///  PWM[2] output single/double edge mode control.
+            PWMSEL2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Single edge controlled mode is selected.
+                    SINGLE_EDGE_CONTROLL = 0x0,
+                    ///  Double edge controlled mode is selected.
+                    DOUBLE_EDGE_CONTROLL = 0x1,
+                },
+            },
+            ///  PWM[3] output edge control.
+            PWMSEL3: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Single edge controlled mode is selected.
+                    SINGLE_EDGE_CONTROLL = 0x0,
+                    ///  Double edge controlled mode is selected.
+                    DOUBLE_EDGE_CONTROLL = 0x1,
+                },
+            },
+            ///  PWM[4] output edge control.
+            PWMSEL4: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Single edge controlled mode is selected.
+                    SINGLE_EDGE_CONTROLL = 0x0,
+                    ///  Double edge controlled mode is selected.
+                    DOUBLE_EDGE_CONTROLL = 0x1,
+                },
+            },
+            ///  PWM[5] output edge control.
+            PWMSEL5: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Single edge controlled mode is selected.
+                    SINGLE_EDGE_CONTROLL = 0x0,
+                    ///  Double edge controlled mode is selected.
+                    DOUBLE_EDGE_CONTROLL = 0x1,
+                },
+            },
+            ///  PWM[6] output edge control.
+            PWMSEL6: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Single edge controlled mode is selected.
+                    SINGLE_EDGE_CONTROLL = 0x0,
+                    ///  Double edge controlled mode is selected.
+                    DOUBLE_EDGE_CONTROLL = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  PWM[1] output enable control.
+            PWMENA1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The PWM output is disabled.
+                    THE_PWM_OUTPUT_IS_DI = 0x0,
+                    ///  The PWM output is enabled.
+                    THE_PWM_OUTPUT_IS_EN = 0x1,
+                },
+            },
+            ///  PWM[2] output enable control.
+            PWMENA2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The PWM output is disabled.
+                    THE_PWM_OUTPUT_IS_DI = 0x0,
+                    ///  The PWM output is enabled.
+                    THE_PWM_OUTPUT_IS_EN = 0x1,
+                },
+            },
+            ///  PWM[3] output enable control.
+            PWMENA3: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The PWM output is disabled.
+                    THE_PWM_OUTPUT_IS_DI = 0x0,
+                    ///  The PWM output is enabled.
+                    THE_PWM_OUTPUT_IS_EN = 0x1,
+                },
+            },
+            ///  PWM[4] output enable control.
+            PWMENA4: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The PWM output is disabled.
+                    THE_PWM_OUTPUT_IS_DI = 0x0,
+                    ///  The PWM output is enabled.
+                    THE_PWM_OUTPUT_IS_EN = 0x1,
+                },
+            },
+            ///  PWM[5] output enable control.
+            PWMENA5: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The PWM output is disabled.
+                    THE_PWM_OUTPUT_IS_DI = 0x0,
+                    ///  The PWM output is enabled.
+                    THE_PWM_OUTPUT_IS_EN = 0x1,
+                },
+            },
+            ///  PWM[6] output enable control. See PWMENA1 for details.
+            PWMENA6: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The PWM output is disabled.
+                    THE_PWM_OUTPUT_IS_DI = 0x0,
+                    ///  The PWM output is enabled.
+                    THE_PWM_OUTPUT_IS_EN = 0x1,
+                },
+            },
+            ///  Unused, always zero.
+            RESERVED: u17,
+        }),
+        ///  Load Enable Register. Enables use of updated PWM match values.
+        LER: mmio.Mmio(packed struct(u32) {
+            ///  Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7.
+            MAT0LATCHEN: u1,
+            ///  Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details.
+            MAT1LATCHEN: u1,
+            ///  Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details.
+            MAT2LATCHEN: u1,
+            ///  Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details.
+            MAT3LATCHEN: u1,
+            ///  Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details.
+            MAT4LATCHEN: u1,
+            ///  Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details.
+            MAT5LATCHEN: u1,
+            ///  Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details.
+            MAT6LATCHEN: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u25,
+        }),
+        reserved112: [28]u8,
+        ///  Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
+        CTCR: mmio.Mmio(packed struct(u32) {
+            ///  Counter/ Timer Mode
+            MOD: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register.
+                    TIMER_MODE_THE_TC_I = 0x0,
+                    ///  Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2.
+                    RISING_EDGE_COUNTER_ = 0x1,
+                    ///  Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2.
+                    FALLING_EDGE_COUNTER = 0x2,
+                    ///  Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2.
+                    DUAL_EDGE_COUNTER_MO = 0x3,
+                },
+            },
+            ///  Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.
+            CIS: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)
+                    FOR_PWM0_00_EQ_PWM0_ = 0x0,
+                    _,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u28,
+        }),
+    };
+
+    ///  I2C bus interface
+    pub const I2C0 = extern struct {
+        ///  I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.
+        CONSET: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u2,
+            ///  Assert acknowledge flag.
+            AA: u1,
+            ///  I2C interrupt flag.
+            SI: u1,
+            ///  STOP flag.
+            STO: u1,
+            ///  START flag.
+            STA: u1,
+            ///  I2C interface enable.
+            I2EN: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u25,
+        }),
+        ///  I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.
+        STAT: mmio.Mmio(packed struct(u32) {
+            ///  These bits are unused and are always 0.
+            RESERVED: u3,
+            ///  These bits give the actual status information about the I 2C interface.
+            Status: u5,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.
+        DAT: mmio.Mmio(packed struct(u32) {
+            ///  This register holds data values that have been received or are to be transmitted.
+            Data: u8,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
+        ADR0: mmio.Mmio(packed struct(u32) {
+            ///  General Call enable bit.
+            GC: u1,
+            ///  The I2C device address for slave mode.
+            Address: u7,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.
+        SCLH: mmio.Mmio(packed struct(u32) {
+            ///  Count for SCL HIGH time period selection.
+            SCLH: u16,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u16,
+        }),
+        ///  SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.
+        SCLL: mmio.Mmio(packed struct(u32) {
+            ///  Count for SCL low time period selection.
+            SCLL: u16,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u16,
+        }),
+        ///  I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.
+        CONCLR: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u2,
+            ///  Assert acknowledge Clear bit.
+            AAC: u1,
+            ///  I2C interrupt Clear bit.
+            SIC: u1,
+            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u1,
+            ///  START flag Clear bit.
+            STAC: u1,
+            ///  I2C interface Disable bit.
+            I2ENC: u1,
+            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  Monitor mode control register.
+        MMCTRL: mmio.Mmio(packed struct(u32) {
+            ///  Monitor mode enable.
+            MM_ENA: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Monitor mode disabled.
+                    MONITOR_MODE_DISABLE = 0x0,
+                    ///  The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.
+                    THE_I_2C_MODULE_WILL = 0x1,
+                },
+            },
+            ///  SCL output enable.
+            ENA_SCL: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.
+                    WHEN_THIS_BIT_IS_CLE = 0x0,
+                    ///  When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]
+                    WHEN_THIS_BIT_IS_SET = 0x1,
+                },
+            },
+            ///  Select interrupt register match.
+            MATCH_ALL: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.
+                    WHEN_THIS_BIT_IS_CLE = 0x0,
+                    ///  When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.
+                    WHEN_THIS_BIT_IS_SET = 0x1,
+                },
+            },
+            ///  Reserved. The value read from reserved bits is not defined.
+            RESERVED: u29,
+        }),
+        reserved44: [12]u8,
+        ///  Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.
+        DATA_BUFFER: mmio.Mmio(packed struct(u32) {
+            ///  This register holds contents of the 8 MSBs of the DAT shift register.
+            Data: u8,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+    };
+
+    ///  SPI
+    pub const SPI = extern struct {
+        ///  SPI Control Register. This register controls the operation of the SPI.
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u2,
+            ///  The SPI controller sends and receives 8 bits of data per transfer.
+            BITENABLE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The SPI controller sends and receives the number of bits selected by bits 11:8.
+                    THE_SPI_CONTROLLER_S = 0x1,
+                    _,
+                },
+            },
+            ///  Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.
+            CPHA: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal.
+                    FIRST_EDGE = 0x0,
+                    ///  Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active.
+                    SECOND_EDGE = 0x1,
+                },
+            },
+            ///  Clock polarity control.
+            CPOL: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  SCK is active high.
+                    SCK_IS_ACTIVE_HIGH_ = 0x0,
+                    ///  SCK is active low.
+                    SCK_IS_ACTIVE_LOW_ = 0x1,
+                },
+            },
+            ///  Master mode select.
+            MSTR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The SPI operates in Slave mode.
+                    SLAVE = 0x0,
+                    ///  The SPI operates in Master mode.
+                    MASTER = 0x1,
+                },
+            },
+            ///  LSB First controls which direction each byte is shifted when transferred.
+            LSBF: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  SPI data is transferred MSB (bit 7) first.
+                    MSB = 0x0,
+                    ///  SPI data is transferred LSB (bit 0) first.
+                    LSB = 0x1,
+                },
+            },
+            ///  Serial peripheral interrupt enable.
+            SPIE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  SPI interrupts are inhibited.
+                    INTBLOCK = 0x0,
+                    ///  A hardware interrupt is generated each time the SPIF or MODF bits are activated.
+                    HWINT = 0x1,
+                },
+            },
+            ///  When bit 2 of this register is 1, this field controls the number of bits per transfer:
+            BITS: packed union {
+                raw: u4,
+                value: enum(u4) {
+                    ///  8 bits per transfer
+                    @"8_BITS_PER_TRANSFER" = 0x8,
+                    ///  9 bits per transfer
+                    @"9_BITS_PER_TRANSFER" = 0x9,
+                    ///  10 bits per transfer
+                    @"10_BITS_PER_TRANSFER" = 0xa,
+                    ///  11 bits per transfer
+                    @"11_BITS_PER_TRANSFER" = 0xb,
+                    ///  12 bits per transfer
+                    @"12_BITS_PER_TRANSFER" = 0xc,
+                    ///  13 bits per transfer
+                    @"13_BITS_PER_TRANSFER" = 0xd,
+                    ///  14 bits per transfer
+                    @"14_BITS_PER_TRANSFER" = 0xe,
+                    ///  15 bits per transfer
+                    @"15_BITS_PER_TRANSFER" = 0xf,
+                    ///  16 bits per transfer
+                    @"16_BITS_PER_TRANSFER" = 0x0,
+                    _,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u20,
+        }),
+        ///  SPI Status Register. This register shows the status of the SPI.
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u3,
+            ///  Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register.
+            ABRT: u1,
+            ///  Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register.
+            MODF: u1,
+            ///  Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register.
+            ROVR: u1,
+            ///  Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register.
+            WCOL: u1,
+            ///  SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register.
+            SPIF: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register.
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  SPI Bi-directional data port.
+            DATALOW: u8,
+            ///  If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes.
+            DATAHIGH: u8,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u16,
+        }),
+        ///  SPI Clock Counter Register. This register controls the frequency of a master's SCK0.
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  SPI0 Clock counter setting.
+            COUNTER: u8,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        reserved28: [12]u8,
+        ///  SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface.
+        INT: mmio.Mmio(packed struct(u32) {
+            ///  SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software.
+            SPIF: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u7,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+    };
+
+    ///  Real Time Clock (RTC)
+    pub const RTC = extern struct {
+        ///  Interrupt Location Register
+        ILR: mmio.Mmio(packed struct(u32) {
+            ///  When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt.
+            RTCCIF: u1,
+            ///  When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt.
+            RTCALF: u1,
+            reserved21: u19,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u11,
+        }),
+        reserved8: [4]u8,
+        ///  Clock Control Register
+        CCR: mmio.Mmio(packed struct(u32) {
+            ///  Clock Enable.
+            CLKEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The time counters are enabled.
+                    THE_TIME_COUNTERS_AR = 0x1,
+                    ///  The time counters are disabled so that they may be initialized.
+                    THE_TIME_COUNTERS_AR = 0x0,
+                },
+            },
+            ///  CTC Reset.
+            CTCRST: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software.
+                    RESET = 0x1,
+                    ///  No effect.
+                    NO_EFFECT_ = 0x0,
+                },
+            },
+            ///  Internal test mode controls. These bits must be 0 for normal RTC operation.
+            RESERVED: u2,
+            ///  Calibration counter enable.
+            CCALEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The calibration counter is disabled and reset to zero.
+                    THE_CALIBRATION_COUN = 0x1,
+                    ///  The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5.
+                    THE_CALIBRATION_COUN = 0x0,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u27,
+        }),
+        ///  Counter Increment Interrupt Register
+        CIIR: mmio.Mmio(packed struct(u32) {
+            ///  When 1, an increment of the Second value generates an interrupt.
+            IMSEC: u1,
+            ///  When 1, an increment of the Minute value generates an interrupt.
+            IMMIN: u1,
+            ///  When 1, an increment of the Hour value generates an interrupt.
+            IMHOUR: u1,
+            ///  When 1, an increment of the Day of Month value generates an interrupt.
+            IMDOM: u1,
+            ///  When 1, an increment of the Day of Week value generates an interrupt.
+            IMDOW: u1,
+            ///  When 1, an increment of the Day of Year value generates an interrupt.
+            IMDOY: u1,
+            ///  When 1, an increment of the Month value generates an interrupt.
+            IMMON: u1,
+            ///  When 1, an increment of the Year value generates an interrupt.
+            IMYEAR: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  Alarm Mask Register
+        AMR: mmio.Mmio(packed struct(u32) {
+            ///  When 1, the Second value is not compared for the alarm.
+            AMRSEC: u1,
+            ///  When 1, the Minutes value is not compared for the alarm.
+            AMRMIN: u1,
+            ///  When 1, the Hour value is not compared for the alarm.
+            AMRHOUR: u1,
+            ///  When 1, the Day of Month value is not compared for the alarm.
+            AMRDOM: u1,
+            ///  When 1, the Day of Week value is not compared for the alarm.
+            AMRDOW: u1,
+            ///  When 1, the Day of Year value is not compared for the alarm.
+            AMRDOY: u1,
+            ///  When 1, the Month value is not compared for the alarm.
+            AMRMON: u1,
+            ///  When 1, the Year value is not compared for the alarm.
+            AMRYEAR: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  Consolidated Time Register 0
+        CTIME0: mmio.Mmio(packed struct(u32) {
+            ///  Seconds value in the range of 0 to 59
+            SECONDS: u6,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u2,
+            ///  Minutes value in the range of 0 to 59
+            MINUTES: u6,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u2,
+            ///  Hours value in the range of 0 to 23
+            HOURS: u5,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u3,
+            ///  Day of week value in the range of 0 to 6
+            DOW: u3,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u5,
+        }),
+        ///  Consolidated Time Register 1
+        CTIME1: mmio.Mmio(packed struct(u32) {
+            ///  Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).
+            DOM: u5,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u3,
+            ///  Month value in the range of 1 to 12.
+            MONTH: u4,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u4,
+            ///  Year value in the range of 0 to 4095.
+            YEAR: u12,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u4,
+        }),
+        ///  Consolidated Time Register 2
+        CTIME2: mmio.Mmio(packed struct(u32) {
+            ///  Day of year value in the range of 1 to 365 (366 for leap years).
+            DOY: u12,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u20,
+        }),
+        ///  Seconds Counter
+        SEC: mmio.Mmio(packed struct(u32) {
+            ///  Seconds value in the range of 0 to 59
+            SECONDS: u6,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u26,
+        }),
+        ///  Minutes Register
+        MIN: mmio.Mmio(packed struct(u32) {
+            ///  Minutes value in the range of 0 to 59
+            MINUTES: u6,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u26,
+        }),
+        ///  Hours Register
+        HRS: mmio.Mmio(packed struct(u32) {
+            ///  Hours value in the range of 0 to 23
+            HOURS: u5,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u27,
+        }),
+        ///  Day of Month Register
+        DOM: mmio.Mmio(packed struct(u32) {
+            ///  Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).
+            DOM: u5,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u27,
+        }),
+        ///  Day of Week Register
+        DOW: mmio.Mmio(packed struct(u32) {
+            ///  Day of week value in the range of 0 to 6.
+            DOW: u3,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u29,
+        }),
+        ///  Day of Year Register
+        DOY: mmio.Mmio(packed struct(u32) {
+            ///  Day of year value in the range of 1 to 365 (366 for leap years).
+            DOY: u9,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u23,
+        }),
+        ///  Months Register
+        MONTH: mmio.Mmio(packed struct(u32) {
+            ///  Month value in the range of 1 to 12.
+            MONTH: u4,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        ///  Years Register
+        YEAR: mmio.Mmio(packed struct(u32) {
+            ///  Year value in the range of 0 to 4095.
+            YEAR: u12,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u20,
+        }),
+        ///  Calibration Value Register
+        CALIBRATION: mmio.Mmio(packed struct(u32) {
+            ///  If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0.
+            CALVAL: u17,
+            ///  Calibration direction
+            CALDIR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second.
+                    BACKWARD_CALIBRATION = 0x1,
+                    ///  Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds.
+                    FORWARD_CALIBRATION_ = 0x0,
+                },
+            },
+            padding: u14,
+        }),
+        reserved88: [20]u8,
+        ///  RTC Auxiliary Enable register
+        RTC_AUXEN: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u4,
+            ///  Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5.
+            RTC_OSCFEN: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u27,
+        }),
+        ///  RTC Auxiliary control register
+        RTC_AUX: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u4,
+            ///  RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag.
+            RTC_OSCF: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode.
+            RTC_PDOUT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u25,
+        }),
+        ///  Alarm value for Seconds
+        ASEC: mmio.Mmio(packed struct(u32) {
+            ///  Seconds value in the range of 0 to 59
+            SECONDS: u6,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u26,
+        }),
+        ///  Alarm value for Minutes
+        AMIN: mmio.Mmio(packed struct(u32) {
+            ///  Minutes value in the range of 0 to 59
+            MINUTES: u6,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u26,
+        }),
+        ///  Alarm value for Hours
+        AHRS: mmio.Mmio(packed struct(u32) {
+            ///  Hours value in the range of 0 to 23
+            HOURS: u5,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u27,
+        }),
+        ///  Alarm value for Day of Month
+        ADOM: mmio.Mmio(packed struct(u32) {
+            ///  Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).
+            DOM: u5,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u27,
+        }),
+        ///  Alarm value for Day of Week
+        ADOW: mmio.Mmio(packed struct(u32) {
+            ///  Day of week value in the range of 0 to 6.
+            DOW: u3,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u29,
+        }),
+        ///  Alarm value for Day of Year
+        ADOY: mmio.Mmio(packed struct(u32) {
+            ///  Day of year value in the range of 1 to 365 (366 for leap years).
+            DOY: u9,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u23,
+        }),
+        ///  Alarm value for Months
+        AMON: mmio.Mmio(packed struct(u32) {
+            ///  Month value in the range of 1 to 12.
+            MONTH: u4,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        ///  Alarm value for Year
+        AYRS: mmio.Mmio(packed struct(u32) {
+            ///  Year value in the range of 0 to 4095.
+            YEAR: u12,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u20,
+        }),
+    };
+
+    ///  GPIO
+    pub const GPIOINT = extern struct {
+        ///  GPIO overall Interrupt Status.
+        STATUS: mmio.Mmio(packed struct(u32) {
+            ///  Port 0 GPIO interrupt pending.
+            P0INT: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No pending interrupts on Port 0.
+                    NO_PENDING_INTERRUPT = 0x0,
+                    ///  At least one pending interrupt on Port 0.
+                    AT_LEAST_ONE_PENDING = 0x1,
+                },
+            },
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u1,
+            ///  Port 2 GPIO interrupt pending.
+            P2INT: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No pending interrupts on Port 2.
+                    NO_PENDING_INTERRUPT = 0x0,
+                    ///  At least one pending interrupt on Port 2.
+                    AT_LEAST_ONE_PENDING = 0x1,
+                },
+            },
+            padding: u29,
+        }),
+        ///  GPIO Interrupt Status for Rising edge for Port 0.
+        STATR0: mmio.Mmio(packed struct(u32) {
+            ///  Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_0REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_1REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_2REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_3REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_4REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_5REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_6REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_7REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_8REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_9REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_10REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_11REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_12REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_13REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_14REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_15REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_16REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_17REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_18REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_19REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_20REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_21REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_22REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_23REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_24REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_25REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_26REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_27REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_28REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_29REI: u1,
+            ///  Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P0_30REI: u1,
+            ///  Reserved.
+            RESERVED: u1,
+        }),
+        ///  GPIO Interrupt Status for Falling edge for Port 0.
+        STATF0: mmio.Mmio(packed struct(u32) {
+            ///  Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_0FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_1FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_2FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_3FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_4FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_5FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_6FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_7FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_8FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_9FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_10FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_11FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_12FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_13FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_14FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_15FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_16FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_17FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_18FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_19FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_20FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_21FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_22FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_23FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_24FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_25FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_26FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_27FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_28FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_29FEI: u1,
+            ///  Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P0_30FEI: u1,
+            ///  Reserved.
+            RESERVED: u1,
+        }),
+        ///  GPIO Interrupt Clear.
+        CLR0: mmio.Mmio(packed struct(u32) {
+            ///  Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_0CI: u1,
+            ///  Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_1CI: u1,
+            ///  Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_2CI: u1,
+            ///  Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_3CI: u1,
+            ///  Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_4CI: u1,
+            ///  Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_5CI: u1,
+            ///  Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_6CI: u1,
+            ///  Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_7CI: u1,
+            ///  Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_8CI: u1,
+            ///  Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_9CI: u1,
+            ///  Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_10CI: u1,
+            ///  Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_11CI: u1,
+            ///  Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_12CI: u1,
+            ///  Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_13CI: u1,
+            ///  Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_14CI: u1,
+            ///  Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_15CI: u1,
+            ///  Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_16CI: u1,
+            ///  Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_17CI: u1,
+            ///  Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_18CI: u1,
+            ///  Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_19CI: u1,
+            ///  Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_20CI: u1,
+            ///  Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_21CI: u1,
+            ///  Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_22CI: u1,
+            ///  Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_23CI: u1,
+            ///  Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_24CI: u1,
+            ///  Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_25CI: u1,
+            ///  Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_26CI: u1,
+            ///  Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_27CI: u1,
+            ///  Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_28CI: u1,
+            ///  Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_29CI: u1,
+            ///  Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P0_30CI: u1,
+            ///  Reserved.
+            RESERVED: u1,
+        }),
+        ///  GPIO Interrupt Enable for Rising edge for Port 0.
+        ENR0: mmio.Mmio(packed struct(u32) {
+            ///  Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_0ER: u1,
+            ///  Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_1ER: u1,
+            ///  Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_2ER: u1,
+            ///  Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_3ER: u1,
+            ///  Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_4ER: u1,
+            ///  Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_5ER: u1,
+            ///  Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_6ER: u1,
+            ///  Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_7ER: u1,
+            ///  Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_8ER: u1,
+            ///  Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_9ER: u1,
+            ///  Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_10ER: u1,
+            ///  Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_11ER: u1,
+            ///  Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_12ER: u1,
+            ///  Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_13ER: u1,
+            ///  Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_14ER: u1,
+            ///  Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_15ER: u1,
+            ///  Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_16ER: u1,
+            ///  Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_17ER: u1,
+            ///  Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_18ER: u1,
+            ///  Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_19ER: u1,
+            ///  Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_20ER: u1,
+            ///  Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_21ER: u1,
+            ///  Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_22ER: u1,
+            ///  Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_23ER: u1,
+            ///  Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_24ER: u1,
+            ///  Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_25ER: u1,
+            ///  Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_26ER: u1,
+            ///  Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_27ER: u1,
+            ///  Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_28ER: u1,
+            ///  Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_29ER: u1,
+            ///  Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P0_30ER: u1,
+            ///  Reserved.
+            RESERVED: u1,
+        }),
+        ///  GPIO Interrupt Enable for Falling edge for Port 0.
+        ENF0: mmio.Mmio(packed struct(u32) {
+            ///  Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_0EF: u1,
+            ///  Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_1EF: u1,
+            ///  Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_2EF: u1,
+            ///  Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_3EF: u1,
+            ///  Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_4EF: u1,
+            ///  Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_5EF: u1,
+            ///  Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_6EF: u1,
+            ///  Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_7EF: u1,
+            ///  Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_8EF: u1,
+            ///  Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_9EF: u1,
+            ///  Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_10EF: u1,
+            ///  Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_11EF: u1,
+            ///  Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_12EF: u1,
+            ///  Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_13EF: u1,
+            ///  Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_14EF: u1,
+            ///  Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_15EF: u1,
+            ///  Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_16EF: u1,
+            ///  Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_17EF: u1,
+            ///  Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_18EF: u1,
+            ///  Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_19EF: u1,
+            ///  Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_20EF: u1,
+            ///  Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_21EF: u1,
+            ///  Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_22EF: u1,
+            ///  Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_23EF: u1,
+            ///  Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_24EF: u1,
+            ///  Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_25EF: u1,
+            ///  Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_26EF: u1,
+            ///  Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_27EF: u1,
+            ///  Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_28EF: u1,
+            ///  Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_29EF: u1,
+            ///  Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P0_30EF: u1,
+            ///  Reserved.
+            RESERVED: u1,
+        }),
+        reserved36: [12]u8,
+        ///  GPIO Interrupt Status for Rising edge for Port 0.
+        STATR2: mmio.Mmio(packed struct(u32) {
+            ///  Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_0REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_1REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_2REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_3REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_4REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_5REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_6REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_7REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_8REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_9REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_10REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_11REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_12REI: u1,
+            ///  Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
+            P2_13REI: u1,
+            ///  Reserved.
+            RESERVED: u18,
+        }),
+        ///  GPIO Interrupt Status for Falling edge for Port 0.
+        STATF2: mmio.Mmio(packed struct(u32) {
+            ///  Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_0FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_1FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_2FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_3FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_4FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_5FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_6FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_7FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_8FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_9FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_10FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_11FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_12FEI: u1,
+            ///  Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
+            P2_13FEI: u1,
+            ///  Reserved.
+            RESERVED: u18,
+        }),
+        ///  GPIO Interrupt Clear.
+        CLR2: mmio.Mmio(packed struct(u32) {
+            ///  Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_0CI: u1,
+            ///  Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_1CI: u1,
+            ///  Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_2CI: u1,
+            ///  Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_3CI: u1,
+            ///  Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_4CI: u1,
+            ///  Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_5CI: u1,
+            ///  Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_6CI: u1,
+            ///  Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_7CI: u1,
+            ///  Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_8CI: u1,
+            ///  Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_9CI: u1,
+            ///  Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_10CI: u1,
+            ///  Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_11CI: u1,
+            ///  Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_12CI: u1,
+            ///  Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
+            P2_13CI: u1,
+            ///  Reserved.
+            RESERVED: u18,
+        }),
+        ///  GPIO Interrupt Enable for Rising edge for Port 0.
+        ENR2: mmio.Mmio(packed struct(u32) {
+            ///  Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_0ER: u1,
+            ///  Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_1ER: u1,
+            ///  Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_2ER: u1,
+            ///  Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_3ER: u1,
+            ///  Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_4ER: u1,
+            ///  Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_5ER: u1,
+            ///  Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_6ER: u1,
+            ///  Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_7ER: u1,
+            ///  Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_8ER: u1,
+            ///  Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_9ER: u1,
+            ///  Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_10ER: u1,
+            ///  Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_11ER: u1,
+            ///  Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_12ER: u1,
+            ///  Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
+            P2_13ER: u1,
+            ///  Reserved.
+            RESERVED: u18,
+        }),
+        ///  GPIO Interrupt Enable for Falling edge for Port 0.
+        ENF2: mmio.Mmio(packed struct(u32) {
+            ///  Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_0EF: u1,
+            ///  Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_1EF: u1,
+            ///  Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_2EF: u1,
+            ///  Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_3EF: u1,
+            ///  Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_4EF: u1,
+            ///  Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_5EF: u1,
+            ///  Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_6EF: u1,
+            ///  Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_7EF: u1,
+            ///  Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_8EF: u1,
+            ///  Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_9EF: u1,
+            ///  Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_10EF: u1,
+            ///  Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_11EF: u1,
+            ///  Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_12EF: u1,
+            ///  Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
+            P2_13EF: u1,
+            ///  Reserved.
+            RESERVED: u18,
+        }),
+    };
+
+    ///  Pin connect block
+    pub const PINCONNECT = extern struct {
+        ///  Pin function select register 0.
+        PINSEL0: mmio.Mmio(packed struct(u32) {
+            ///  Pin function select P0.0.
+            P0_0: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.0
+                    GPIO_P0 = 0x0,
+                    ///  RD1
+                    RD1 = 0x1,
+                    ///  TXD3
+                    TXD3 = 0x2,
+                    ///  SDA1
+                    SDA1 = 0x3,
+                },
+            },
+            ///  Pin function select P0.1.
+            P0_1: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.1
+                    GPIO_P0 = 0x0,
+                    ///  TD1
+                    TD1 = 0x1,
+                    ///  RXD3
+                    RXD3 = 0x2,
+                    ///  SCL1
+                    SCL1 = 0x3,
+                },
+            },
+            ///  Pin function select P0.2.
+            P0_2: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.2
+                    GPIO_P0 = 0x0,
+                    ///  TXD0
+                    TXD0 = 0x1,
+                    ///  AD0.7
+                    AD0 = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P0.3.
+            P0_3: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.3.
+                    GPIO_P0 = 0x0,
+                    ///  RXD0
+                    RXD0 = 0x1,
+                    ///  AD0.6
+                    AD0 = 0x2,
+                    ///  Reserved.
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P0.4.
+            P0_4: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.4.
+                    GPIO_P0 = 0x0,
+                    ///  I2SRX_CLK
+                    I2SRX_CLK = 0x1,
+                    ///  RD2
+                    RD2 = 0x2,
+                    ///  CAP2.0
+                    CAP2 = 0x3,
+                },
+            },
+            ///  Pin function select P0.5.
+            P0_5: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.5.
+                    GPIO_P0 = 0x0,
+                    ///  I2SRX_WS
+                    I2SRX_WS = 0x1,
+                    ///  TD2
+                    TD2 = 0x2,
+                    ///  CAP2.1
+                    CAP2 = 0x3,
+                },
+            },
+            ///  Pin function select P0.6.
+            P0_6: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.6.
+                    GPIO_P0 = 0x0,
+                    ///  I2SRX_SDA
+                    I2SRX_SDA = 0x1,
+                    ///  SSEL1
+                    SSEL1 = 0x2,
+                    ///  MAT2.0
+                    MAT2 = 0x3,
+                },
+            },
+            ///  Pin function select P0.7.
+            P0_7: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.7.
+                    GPIO_P0 = 0x0,
+                    ///  I2STX_CLK
+                    I2STX_CLK = 0x1,
+                    ///  SCK1
+                    SCK1 = 0x2,
+                    ///  MAT2.1
+                    MAT2 = 0x3,
+                },
+            },
+            ///  Pin function select P0.8.
+            P0_8: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.8.
+                    GPIO_P0 = 0x0,
+                    ///  I2STX_WS
+                    I2STX_WS = 0x1,
+                    ///  MISO1
+                    MISO1 = 0x2,
+                    ///  MAT2.2
+                    MAT2 = 0x3,
+                },
+            },
+            ///  Pin function select P0.9.
+            P0_9: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.9
+                    GPIO_P0 = 0x0,
+                    ///  I2STX_SDA
+                    I2STX_SDA = 0x1,
+                    ///  MOSI1
+                    MOSI1 = 0x2,
+                    ///  MAT2.3
+                    MAT2 = 0x3,
+                },
+            },
+            ///  Pin function select P0.10.
+            P0_10: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.10
+                    GPIO_P0 = 0x0,
+                    ///  TXD2
+                    TXD2 = 0x1,
+                    ///  SDA2
+                    SDA2 = 0x2,
+                    ///  MAT3.0
+                    MAT3 = 0x3,
+                },
+            },
+            ///  Pin function select P0.11.
+            P0_11: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.11
+                    GPIO_P0 = 0x0,
+                    ///  RXD2
+                    RXD2 = 0x1,
+                    ///  SCL2
+                    SCL2 = 0x2,
+                    ///  MAT3.1
+                    MAT3 = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u6,
+            ///  Pin function select P0.15.
+            P0_15: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.15
+                    GPIO_P0 = 0x0,
+                    ///  TXD1
+                    TXD1 = 0x1,
+                    ///  SCK0
+                    SCK0 = 0x2,
+                    ///  SCK
+                    SCK = 0x3,
+                },
+            },
+        }),
+        ///  Pin function select register 1.
+        PINSEL1: mmio.Mmio(packed struct(u32) {
+            ///  Pin function select P0.16.
+            P0_16: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.16
+                    GPIO_P0 = 0x0,
+                    ///  RXD1
+                    RXD1 = 0x1,
+                    ///  SSEL0
+                    SSEL0 = 0x2,
+                    ///  SSEL
+                    SSEL = 0x3,
+                },
+            },
+            ///  Pin function select P0.17.
+            P0_17: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.17
+                    GPIO_P0 = 0x0,
+                    ///  CTS1
+                    CTS1 = 0x1,
+                    ///  MISO0
+                    MISO0 = 0x2,
+                    ///  MISO
+                    MISO = 0x3,
+                },
+            },
+            ///  Pin function select P0.18.
+            P0_18: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.18
+                    GPIO_P0 = 0x0,
+                    ///  DCD1
+                    DCD1 = 0x1,
+                    ///  MOSI0
+                    MOSI0 = 0x2,
+                    ///  MOSI
+                    MOSI = 0x3,
+                },
+            },
+            ///  Pin function select P019.
+            P0_19: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.19.
+                    GPIO_P0 = 0x0,
+                    ///  DSR1
+                    DSR1 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  SDA1
+                    SDA1 = 0x3,
+                },
+            },
+            ///  Pin function select P0.20.
+            P0_20: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.20.
+                    GPIO_P0 = 0x0,
+                    ///  DTR1
+                    DTR1 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  SCL1
+                    SCL1 = 0x3,
+                },
+            },
+            ///  Pin function select P0.21.
+            P0_21: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO Port 0.21.
+                    GPIO_PORT_0 = 0x0,
+                    ///  RI1
+                    RI1 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  RD1
+                    RD1 = 0x3,
+                },
+            },
+            ///  Pin function select P022
+            P0_22: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.22.
+                    GPIO_P0 = 0x0,
+                    ///  RTS1
+                    RTS1 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  TD1
+                    TD1 = 0x3,
+                },
+            },
+            ///  Pin function select P023.
+            P0_23: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.23.
+                    GPIO_P0 = 0x0,
+                    ///  AD0.0
+                    AD0 = 0x1,
+                    ///  I2SRX_CLK
+                    I2SRX_CLK = 0x2,
+                    ///  CAP3.0
+                    CAP3 = 0x3,
+                },
+            },
+            ///  Pin function select P0.24.
+            P0_24: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.24.
+                    GPIO_P0 = 0x0,
+                    ///  AD0.1
+                    AD0 = 0x1,
+                    ///  I2SRX_WS
+                    I2SRX_WS = 0x2,
+                    ///  CAP3.1
+                    CAP3 = 0x3,
+                },
+            },
+            ///  Pin function select P0.25.
+            P0_25: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.25
+                    GPIO_P0 = 0x0,
+                    ///  AD0.2
+                    AD0 = 0x1,
+                    ///  I2SRX_SDA
+                    I2SRX_SDA = 0x2,
+                    ///  TXD3
+                    TXD3 = 0x3,
+                },
+            },
+            ///  Pin function select P0.26.
+            P0_26: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.26
+                    GPIO_P0 = 0x0,
+                    ///  AD0.3
+                    AD0 = 0x1,
+                    ///  AOUT
+                    AOUT = 0x2,
+                    ///  RXD3
+                    RXD3 = 0x3,
+                },
+            },
+            ///  Pin function select P0.27.
+            P0_27: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.27
+                    GPIO_P0 = 0x0,
+                    ///  SDA0
+                    SDA0 = 0x1,
+                    ///  USB_SDA
+                    USB_SDA = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P0.28.
+            P0_28: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.28
+                    GPIO_P0 = 0x0,
+                    ///  SCL0
+                    SCL0 = 0x1,
+                    ///  USB_SCL
+                    USB_SCL = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P0.29
+            P0_29: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.29
+                    GPIO_P0 = 0x0,
+                    ///  USB_D+
+                    USB_DP = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P0.30.
+            P0_30: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P0.30
+                    GPIO_P0 = 0x0,
+                    ///  USB_D-
+                    USB_DM = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Reserved
+            RESERVED: u2,
+        }),
+        ///  Pin function select register 2.
+        PINSEL2: mmio.Mmio(packed struct(u32) {
+            ///  Pin function select P1.0.
+            P1_0: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.0
+                    GPIO_P1 = 0x0,
+                    ///  ENET_TXD0
+                    ENET_TXD0 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P1.1.
+            P1_1: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.1
+                    GPIO_P1 = 0x0,
+                    ///  ENET_TXD1
+                    ENET_TXD1 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u4,
+            ///  Pin function select P1.4.
+            P1_4: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.4.
+                    GPIO_P1 = 0x0,
+                    ///  ENET_TX_EN
+                    ENET_TX_EN = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u6,
+            ///  Pin function select P1.8.
+            P1_8: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.8.
+                    GPIO_P1 = 0x0,
+                    ///  ENET_CRS
+                    ENET_CRS = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P1.9.
+            P1_9: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO Port 1.9
+                    GPIO_PORT_1 = 0x0,
+                    ///  ENET_RXD0
+                    ENET_RXD0 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P1.10.
+            P1_10: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.10
+                    GPIO_P1 = 0x0,
+                    ///  ENET_RXD1
+                    ENET_RXD1 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P1.14.
+            P1_14: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.14
+                    GPIO_P1 = 0x0,
+                    ///  ENET_RX_ER
+                    ENET_RX_ER = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u6,
+            ///  Pin function select P1.15.
+            P1_15: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.15
+                    GPIO_P1 = 0x0,
+                    ///  ENET_REF_CLK
+                    ENET_REF_CLK = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+        }),
+        ///  Pin function select register 3.
+        PINSEL3: mmio.Mmio(packed struct(u32) {
+            ///  Pin function select P1.16.
+            P1_16: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.16
+                    GPIO_P1 = 0x0,
+                    ///  ENET_MDC
+                    ENET_MDC = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P1.17.
+            P1_17: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.17
+                    GPIO_P1 = 0x0,
+                    ///  ENET_MDIO
+                    ENET_MDIO = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P1.18.
+            P1_18: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.18
+                    GPIO_P1 = 0x0,
+                    ///  USB_UP_LED
+                    USB_UP_LED = 0x1,
+                    ///  PWM1.1
+                    PWM1 = 0x2,
+                    ///  CAP1.0
+                    CAP1 = 0x3,
+                },
+            },
+            ///  Pin function select P1.19.
+            P1_19: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.19.
+                    GPIO_P1 = 0x0,
+                    ///  MCOA0
+                    MCOA0 = 0x1,
+                    ///  USB_PPWR
+                    USB_PPWR = 0x2,
+                    ///  CAP1.1
+                    CAP1 = 0x3,
+                },
+            },
+            ///  Pin function select P1.20.
+            P1_20: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.20.
+                    GPIO_P1 = 0x0,
+                    ///  MCI0
+                    MCI0 = 0x1,
+                    ///  PWM1.2
+                    PWM1 = 0x2,
+                    ///  SCK0
+                    SCK0 = 0x3,
+                },
+            },
+            ///  Pin function select P1.21.
+            P1_21: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.21.
+                    GPIO_P1 = 0x0,
+                    ///  MCABORT
+                    MCABORT = 0x1,
+                    ///  PWM1.3
+                    PWM1 = 0x2,
+                    ///  SSEL0
+                    SSEL0 = 0x3,
+                },
+            },
+            ///  Pin function select P1.22
+            P1_22: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.22.
+                    GPIO_P1 = 0x0,
+                    ///  MCOB0
+                    MCOB0 = 0x1,
+                    ///  USB_PWRD
+                    USB_PWRD = 0x2,
+                    ///  MAT1.0
+                    MAT1 = 0x3,
+                },
+            },
+            ///  Pin function select P1.23.
+            P1_23: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.23.
+                    GPIO_P1 = 0x0,
+                    ///  MCI1
+                    MCI1 = 0x1,
+                    ///  PWM1.4
+                    PWM1 = 0x2,
+                    ///  MISO0
+                    MISO0 = 0x3,
+                },
+            },
+            ///  Pin function select P1.24.
+            P1_24: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.24.
+                    GPIO_P1 = 0x0,
+                    ///  MCI2
+                    MCI2 = 0x1,
+                    ///  PWM1.5
+                    PWM1 = 0x2,
+                    ///  MOSI0
+                    MOSI0 = 0x3,
+                },
+            },
+            ///  Pin function select P1.25.
+            P1_25: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.25
+                    GPIO_P1 = 0x0,
+                    ///  MCOA1
+                    MCOA1 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  MAT1.1
+                    MAT1 = 0x3,
+                },
+            },
+            ///  Pin function select P1.26.
+            P1_26: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.26
+                    GPIO_P1 = 0x0,
+                    ///  MCOB1
+                    MCOB1 = 0x1,
+                    ///  PWM1.6
+                    PWM1 = 0x2,
+                    ///  CAP0.0
+                    CAP0 = 0x3,
+                },
+            },
+            ///  Pin function select P1.27.
+            P1_27: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.27
+                    GPIO_P1 = 0x0,
+                    ///  CLKOUT
+                    CLKOUT = 0x1,
+                    ///  USB_OVRCR
+                    USB_OVRCR = 0x2,
+                    ///  CAP0.1
+                    CAP0 = 0x3,
+                },
+            },
+            ///  Pin function select P1.28.
+            P1_28: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.28
+                    GPIO_P1 = 0x0,
+                    ///  MCOA2
+                    MCOA2 = 0x1,
+                    ///  PCAP1.0
+                    PCAP1 = 0x2,
+                    ///  MAT0.0
+                    MAT0 = 0x3,
+                },
+            },
+            ///  Pin function select P1.29
+            P1_29: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.29
+                    GPIO_P1 = 0x0,
+                    ///  MCOB2
+                    MCOB2 = 0x1,
+                    ///  PCAP1.1
+                    PCAP1 = 0x2,
+                    ///  MAT0.1
+                    MAT0 = 0x3,
+                },
+            },
+            ///  Pin function select P1.30.
+            P1_30: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P1.30
+                    GPIO_P1 = 0x0,
+                    ///  Reserved
+                    RESERVED = 0x1,
+                    ///  VBUS
+                    VBUS = 0x2,
+                    ///  AD0.4
+                    AD0 = 0x3,
+                },
+            },
+            ///  Pin function select P1.31.
+            P1_31: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO Port 1.31
+                    GPIO_PORT_1 = 0x0,
+                    ///  Reserved
+                    RESERVED = 0x1,
+                    ///  SCK1
+                    SCK1 = 0x2,
+                    ///  AD0.5
+                    AD0 = 0x3,
+                },
+            },
+        }),
+        ///  Pin function select register 4
+        PINSEL4: mmio.Mmio(packed struct(u32) {
+            ///  Pin function select P2.0.
+            P2_0: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.0
+                    GPIO_P2 = 0x0,
+                    ///  PWM1.1
+                    PWM1 = 0x1,
+                    ///  TXD1
+                    TXD1 = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P2.1.
+            P2_1: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.1
+                    GPIO_P2 = 0x0,
+                    ///  PWM1.2
+                    PWM1 = 0x1,
+                    ///  RXD1
+                    RXD1 = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P2.2.
+            P2_2: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.2
+                    GPIO_P2 = 0x0,
+                    ///  PWM1.3
+                    PWM1 = 0x1,
+                    ///  CTS1
+                    CTS1 = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P2.3.
+            P2_3: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.3.
+                    GPIO_P2 = 0x0,
+                    ///  PWM1.4
+                    PWM1 = 0x1,
+                    ///  DCD1
+                    DCD1 = 0x2,
+                    ///  Reserved.
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P2.4.
+            P2_4: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.4.
+                    GPIO_P2 = 0x0,
+                    ///  PWM1.5
+                    PWM1 = 0x1,
+                    ///  DSR1
+                    DSR1 = 0x2,
+                    ///  Reserved.
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P2.5.
+            P2_5: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.5.
+                    GPIO_P2 = 0x0,
+                    ///  PWM1.6
+                    PWM1 = 0x1,
+                    ///  DTR1
+                    DTR1 = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P2.6.
+            P2_6: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.6.
+                    GPIO_P2 = 0x0,
+                    ///  PCAP1.0
+                    PCAP1 = 0x1,
+                    ///  RI1
+                    RI1 = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P2.7.
+            P2_7: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.7.
+                    GPIO_P2 = 0x0,
+                    ///  RD2
+                    RD2 = 0x1,
+                    ///  RTS1
+                    RTS1 = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P2.8.
+            P2_8: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.8.
+                    GPIO_P2 = 0x0,
+                    ///  TD2
+                    TD2 = 0x1,
+                    ///  TXD2
+                    TXD2 = 0x2,
+                    ///  ENET_MDC
+                    ENET_MDC = 0x3,
+                },
+            },
+            ///  Pin function select P2.9.
+            P2_9: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.9
+                    GPIO_P2 = 0x0,
+                    ///  USB_CONNECT
+                    USB_CONNECT = 0x1,
+                    ///  RXD2
+                    RXD2 = 0x2,
+                    ///  ENET_MDIO
+                    ENET_MDIO = 0x3,
+                },
+            },
+            ///  Pin function select P2.10.
+            P2_10: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.10
+                    GPIO_P2 = 0x0,
+                    ///  EINT0
+                    EINT0 = 0x1,
+                    ///  NMI
+                    NMI = 0x2,
+                    ///  Reserved
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Pin function select P2.11.
+            P2_11: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.11
+                    GPIO_P2 = 0x0,
+                    ///  EINT1
+                    EINT1 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  I2STX_CLK
+                    I2STX_CLK = 0x3,
+                },
+            },
+            ///  Pin function select P2.12.
+            P2_12: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.12
+                    GPIO_P2 = 0x0,
+                    ///  EINT2
+                    EINT2 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  I2STX_WS
+                    I2STX_WS = 0x3,
+                },
+            },
+            ///  Pin function select P2.13.
+            P2_13: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P2.13
+                    GPIO_P2 = 0x0,
+                    ///  EINT3
+                    EINT3 = 0x1,
+                    ///  Reserved
+                    RESERVED = 0x2,
+                    ///  I2STX_SDA
+                    I2STX_SDA = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u4,
+        }),
+        reserved28: [8]u8,
+        ///  Pin function select register 7
+        PINSEL7: mmio.Mmio(packed struct(u32) {
+            ///  Reserved.
+            RESERVED: u18,
+            ///  Pin function select P3.25.
+            P3_25: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P3.25
+                    GPIO_P3 = 0x0,
+                    ///  Reserved
+                    RESERVED = 0x1,
+                    ///  MAT0.0
+                    MAT0 = 0x2,
+                    ///  PWM1.2
+                    PWM1 = 0x3,
+                },
+            },
+            ///  Pin function select P3.26.
+            P3_26: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P3.26
+                    GPIO_P3 = 0x0,
+                    ///  STCLK
+                    STCLK = 0x1,
+                    ///  MAT0.1
+                    MAT0 = 0x2,
+                    ///  PWM1.3
+                    PWM1 = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u10,
+        }),
+        reserved36: [4]u8,
+        ///  Pin function select register 9
+        PINSEL9: mmio.Mmio(packed struct(u32) {
+            ///  Reserved.
+            RESERVED: u24,
+            ///  Pin function select P4.28.
+            P4_28: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P4.28
+                    GPIO_P4 = 0x0,
+                    ///  RX_MCLK
+                    RX_MCLK = 0x1,
+                    ///  MAT2.0
+                    MAT2 = 0x2,
+                    ///  TXD3
+                    TXD3 = 0x3,
+                },
+            },
+            ///  Pin function select P4.29.
+            P4_29: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  GPIO P4.29
+                    GPIO_P4 = 0x0,
+                    ///  TX_MCLK
+                    TX_MCLK = 0x1,
+                    ///  MAT2.1
+                    MAT2 = 0x2,
+                    ///  RXD3
+                    RXD3 = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u4,
+        }),
+        ///  Pin function select register 10
+        PINSEL10: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Software should not write 1 to these bits.
+            RESERVED: u3,
+            ///  TPIU interface pins control.
+            TPIUCTRL: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled. TPIU interface is disabled.
+                    DISABLED = 0x0,
+                    ///  Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content.
+                    ENABLED = 0x1,
+                },
+            },
+            ///  Reserved. Software should not write 1 to these bits.
+            RESERVED: u28,
+        }),
+        reserved64: [20]u8,
+        ///  Pin mode select register 0
+        PINMODE0: mmio.Mmio(packed struct(u32) {
+            ///  Port 0 pin 0 on-chip pull-up/down resistor control.
+            P0_00MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.0 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.0 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.0 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.0 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 0 pin 1 control.
+            P0_01MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.1 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.1 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.1 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.1 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 0 pin 2 control.
+            P0_02MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.2 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.2 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.2 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.2 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 0 pin 3 control.
+            P0_03MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.3 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.3 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.3 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.3 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 0 pin 4 control.
+            P0_04MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.4 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.4 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.4 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.4 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 0 pin 5 control.
+            P0_05MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.5 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.5 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.5 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.5 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 0 pin 6 control.
+            P0_06MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.6 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Disabled. Repeater. P0.6 pin has repeater mode enabled.
+                    DISABLED = 0x1,
+                    ///  Disabled. P0.6 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.6 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 0 pin 7 control.
+            P0_07MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.7 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.7 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.7 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.7 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 0 pin 8 control.
+            P0_08MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.8 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.8 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.8 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.8 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 0 pin 9 control.
+            P0_09MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.9 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.9 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.9 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.9 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 0 pin 10 control.
+            P0_10MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.10 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.10 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.10 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.10 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 0 pin 11 control.
+            P0_11MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.11 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.11 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.11 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.11 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u6,
+            ///  Port 0 pin 15 control.
+            P0_15MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.15 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.15 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.15 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.15 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+        }),
+        ///  Pin mode select register 1
+        PINMODE1: mmio.Mmio(packed struct(u32) {
+            ///  Port 1 pin 16 control.
+            P0_16MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.16 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.16 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.16 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.16 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 17 control.
+            P0_17MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.17 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.17 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.17 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.17 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 18 control.
+            P0_18MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.18 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.18 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.18 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.18 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 19 control.
+            P0_19MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.19 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.19 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.19 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.19 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 20 control.
+            P0_20MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.20 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.20 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.20 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.20 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 21 control.
+            P0_21MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.21 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.21 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.21 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.21 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 22 control.
+            P0_22MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.22 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.22 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.22 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.22 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 23 control.
+            P0_23MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.23 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.23 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.23 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.23 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 24 control.
+            P0_24MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.24 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.24 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.24 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.24 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 25 control.
+            P0_25MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.25 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.25 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.25 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.25 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 26 control.
+            P0_26MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P0.26 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P0.26 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P0.26 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P0.26 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u8,
+            ///  Reserved.
+            RESERVED: u2,
+        }),
+        ///  Pin mode select register 2
+        PINMODE2: mmio.Mmio(packed struct(u32) {
+            ///  Port 1 pin 0 control.
+            P1_00MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.0 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.0 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.0 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.0 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 1 control.
+            P1_01MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.1 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.1 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.1 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.1 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u4,
+            ///  Port 1 pin 4 control.
+            P1_04MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.4 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.4 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.4 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.4 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u6,
+            ///  Port 1 pin 8 control.
+            P1_08MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.8 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.8 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.8 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.8 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 9 control.
+            P1_09MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.9 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.9 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.9 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.9 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 10 control.
+            P1_10MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.10 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.10 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.10 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.10 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u6,
+            ///  Port 1 pin 14 control.
+            P1_14MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.14 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.14 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.14 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.14 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 15 control.
+            P1_15MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.15 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.15 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.15 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.15 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+        }),
+        ///  Pin mode select register 3.
+        PINMODE3: mmio.Mmio(packed struct(u32) {
+            ///  Port 1 pin 16 control.
+            P1_16MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.16 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.16 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.16 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.16 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 17 control.
+            P1_17MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.17 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.17 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.17 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.17 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 18 control.
+            P1_18MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.18 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.18 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.18 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.18 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 19 control.
+            P1_19MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.19 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.19 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.19 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.19 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 20 control.
+            P1_20MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.20 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.20 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.20 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.20 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 21 control.
+            P1_21MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.21 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.21 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.21 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.21 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 22 control.
+            P1_22MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.22 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.22 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.22 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.22 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 23 control.
+            P1_23MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.23 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.23 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.23 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.23 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 24 control.
+            P1_24MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.24 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.24 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.24 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.24 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 25 control.
+            P1_25MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.25 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.25 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.25 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.25 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 26 control.
+            P1_26MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.26 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.26 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.26 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.26 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 27 control.
+            P1_27MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.27 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.27 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.27 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.27 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 28 control.
+            P1_28MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.28 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.28 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.28 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.28 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 29 control.
+            P1_29MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.29 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.29 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.29 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.29 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 30 control.
+            P1_30MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.30 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.30 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.30 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.30 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 1 pin 31 control.
+            P1_31MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P1.31 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P1.31 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P1.31 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P1.31 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+        }),
+        ///  Pin mode select register 4
+        PINMODE4: mmio.Mmio(packed struct(u32) {
+            ///  Port 2 pin 0 control.
+            P2_00MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.0 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.0 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.0 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.0 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 1 control.
+            P2_01MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.1 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.1 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.1 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.1 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 2 control.
+            P2_02MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.2 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.2 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.2 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.2 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 3 control.
+            P2_03MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.3 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.3 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.3 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.3 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 4 control.
+            P2_04MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.4 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.4 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.4 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.4 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 5 control.
+            P2_05MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.5 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.5 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.5 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.5 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 6 control.
+            P2_06MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.6 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.6 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.6 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.6 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 7 control.
+            P2_07MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.7 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.7 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.7 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.7 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 8 control.
+            P2_08MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.8 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.8 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.8 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.8 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 9 control.
+            P2_09MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.9 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.9 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.9 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.9 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 10 control.
+            P2_10MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.10 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.10 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.10 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.10 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 11 control.
+            P2_11MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.11 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.11 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.11 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.11 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 12 control.
+            P2_12MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.12 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.12 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.12 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.12 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 2 pin 13 control.
+            P2_13MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P2.13 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P2.13 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P2.13 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P2.13 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u4,
+        }),
+        reserved92: [8]u8,
+        ///  Pin mode select register 7
+        PINMODE7: mmio.Mmio(packed struct(u32) {
+            ///  Reserved
+            RESERVED: u18,
+            ///  Port 3 pin 25 control.
+            P3_25MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P3.25 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P3.25 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P3.25 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P3.25 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 3 pin 26 control.
+            P3_26MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P3.26 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P3.26 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P3.26 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P3.26 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u10,
+        }),
+        reserved100: [4]u8,
+        ///  Pin mode select register 9
+        PINMODE9: mmio.Mmio(packed struct(u32) {
+            ///  Reserved.
+            RESERVED: u24,
+            ///  Port 4 pin 28 control.
+            P4_28MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P4.28 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P4.28 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P4.28 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P4.28 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Port 4 pin 29 control.
+            P4_29MODE: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Pull-up. P4.29 pin has a pull-up resistor enabled.
+                    PULL_UP = 0x0,
+                    ///  Repeater. P4.29 pin has repeater mode enabled.
+                    REPEATER = 0x1,
+                    ///  Disabled. P4.29 pin has neither pull-up nor pull-down.
+                    DISABLED = 0x2,
+                    ///  Pull-down. P4.29 has a pull-down resistor enabled.
+                    PULL_DOWN = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u4,
+        }),
+        ///  Open drain mode control register 0
+        PINMODE_OD0: mmio.Mmio(packed struct(u32) {
+            ///  Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
+            P0_00OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.0 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.0 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
+            P0_01OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.1 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.1 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 2 open drain mode control
+            P0_02OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.2 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.2 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 3 open drain mode control
+            P0_03OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.3 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.3 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 4 open drain mode control
+            P0_04OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.4 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.4 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 5 open drain mode control
+            P0_05OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.5 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.5 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 6 open drain mode control
+            P0_06OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.6 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.6 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 7 open drain mode control
+            P0_07OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.7 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.7 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 8 open drain mode control
+            P0_08OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.8 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.8 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 9 open drain mode control
+            P0_09OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.9 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.9 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
+            P0_10OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.10 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.10 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
+            P0_11OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.11 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.11 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u3,
+            ///  Port 0 pin 15 open drain mode control
+            P0_15OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.15 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.15 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 16 open drain mode control
+            P0_16OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.16 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.16 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 17 open drain mode control
+            P0_17OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.17 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.17 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 18 open drain mode control
+            P0_18OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.18 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.18 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
+            P0_19OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.19 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.19 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
+            P0_20OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.20 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.20 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 21 open drain mode control
+            P0_21OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.21 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.21 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 22 open drain mode control
+            P0_22OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.22 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.22 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 23 open drain mode control
+            P0_23OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.23 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.23 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 24open drain mode control
+            P0_24OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.23 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.23 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 25 open drain mode control
+            P0_25OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.25 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.25 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 26 open drain mode control
+            P0_26OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.26 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.26 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u2,
+            ///  Port 0 pin 29 open drain mode control
+            P0_29OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.29 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.29 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 0 pin 30 open drain mode control
+            P0_30OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P0.30 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P0.30 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u1,
+        }),
+        ///  Open drain mode control register 1
+        PINMODE_OD1: mmio.Mmio(packed struct(u32) {
+            ///  Port 1 pin 0 open drain mode control.
+            P1_00OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.0 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.0 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 1 open drain mode control, see P1.00OD
+            P1_01OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.1 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.1 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u2,
+            ///  Port 1 pin 4 open drain mode control, see P1.00OD
+            P1_04OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.4 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.4 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u3,
+            ///  Port 1 pin 8 open drain mode control, see P1.00OD
+            P1_08OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.8 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.8 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 9 open drain mode control, see P1.00OD
+            P1_09OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.9 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.9 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 10 open drain mode control, see P1.00OD
+            P1_10OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.10 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.10 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u3,
+            ///  Port 1 pin 14 open drain mode control, see P1.00OD
+            P1_14OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.14 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.14 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 15 open drain mode control, see P1.00OD
+            P1_15OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.15 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.15 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 16 open drain mode control, see P1.00OD
+            P1_16OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.16 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.16 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 17 open drain mode control, see P1.00OD
+            P1_17OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.17 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.17 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 18 open drain mode control, see P1.00OD
+            P1_18OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.18 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.18 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 19 open drain mode control, see P1.00OD
+            P1_19OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.19 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.19 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 20open drain mode control, see P1.00OD
+            P1_20OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.20 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.20 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 21 open drain mode control, see P1.00OD
+            P1_21OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.21 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.21 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 22 open drain mode control, see P1.00OD
+            P1_22OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.22 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.22 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 23 open drain mode control, see P1.00OD
+            P1_23OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.23 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.23 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 24open drain mode control, see P1.00OD
+            P1_24OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.24 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.24 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 25 open drain mode control, see P1.00OD
+            P1_25OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.25 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.25 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 26 open drain mode control, see P1.00OD
+            P1_26OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.26 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.26 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 27 open drain mode control, see P1.00OD
+            P1_27OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.27 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.27 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 28 open drain mode control, see P1.00OD
+            P1_28OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.28 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.28 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 29 open drain mode control, see P1.00OD
+            P1_29OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.29 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.29 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 30 open drain mode control, see P1.00OD
+            P1_30OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.30 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.30 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 1 pin 31 open drain mode control.
+            P1_31OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P1.31 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P1.31 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+        }),
+        ///  Open drain mode control register 2
+        PINMODE_OD2: mmio.Mmio(packed struct(u32) {
+            ///  Port 2 pin 0 open drain mode control.
+            P2_00OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.0 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.0 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 1 open drain mode control, see P2.00OD
+            P2_01OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.1 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.1p in is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 2 open drain mode control, see P2.00OD
+            P2_02OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.2 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.2 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 3 open drain mode control, see P2.00OD
+            P2_03OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.3 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.3 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 4 open drain mode control, see P2.00OD
+            P2_04OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.4 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.4 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 5 open drain mode control, see P2.00OD
+            P2_05OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.5 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.5 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 6 open drain mode control, see P2.00OD
+            P2_06OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.6 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.6 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 7 open drain mode control, see P2.00OD
+            P2_07OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.7 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.7 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 8 open drain mode control, see P2.00OD
+            P2_08OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.8 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.8 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 9 open drain mode control, see P2.00OD
+            P2_09OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.9 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.9 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 10 open drain mode control, see P2.00OD
+            P2_10OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.10 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.10 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 11 open drain mode control, see P2.00OD
+            P2_11OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.11 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.11 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 12 open drain mode control, see P2.00OD
+            P2_12OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.12 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.12 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 2 pin 13 open drain mode control, see P2.00OD
+            P2_13OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P2.13 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P2.13 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u18,
+        }),
+        ///  Open drain mode control register 3
+        PINMODE_OD3: mmio.Mmio(packed struct(u32) {
+            ///  Reserved.
+            RESERVED: u25,
+            ///  Port 3 pin 25 open drain mode control.
+            P3_25OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P3.25 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P3.25 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 3 pin 26 open drain mode control, see P3.25OD
+            P3_26OD: u1,
+            ///  Reserved.
+            RESERVED: u5,
+        }),
+        ///  Open drain mode control register 4
+        PINMODE_OD4: mmio.Mmio(packed struct(u32) {
+            ///  Reserved.
+            RESERVED: u28,
+            ///  Port 4 pin 28 open drain mode control.
+            P4_28OD: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. P4.28 pin is in the normal (not open drain) mode.
+                    NORMAL = 0x0,
+                    ///  Open-drain. P4.28 pin is in the open drain mode.
+                    OPEN_DRAIN = 0x1,
+                },
+            },
+            ///  Port 4 pin 29 open drain mode control, see P4.28OD
+            P4_29OD: u1,
+            ///  Reserved.
+            RESERVED: u2,
+        }),
+        ///  I2C Pin Configuration register
+        I2CPADCFG: mmio.Mmio(packed struct(u32) {
+            ///  Drive mode control for the SDA0 pin, P0.27.
+            SDADRV0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Standard. The SDA0 pin is in the standard drive mode.
+                    STANDARD = 0x0,
+                    ///  Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode.
+                    FAST_MODE_PLUS = 0x1,
+                },
+            },
+            ///  I 2C filter mode control for the SDA0 pin, P0.27.
+            SDAI2C0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled.
+                    ENABLED = 0x0,
+                    ///  Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled.
+                    DISABLED = 0x1,
+                },
+            },
+            ///  Drive mode control for the SCL0 pin, P0.28.
+            SCLDRV0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Standard. The SCL0 pin is in the standard drive mode.
+                    STANDARD = 0x0,
+                    ///  Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode.
+                    FAST_MODE_PLUS = 0x1,
+                },
+            },
+            ///  I 2C filter mode control for the SCL0 pin, P0.28.
+            SCLI2C0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled.
+                    ENABLED = 0x0,
+                    ///  Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled.
+                    DISABLED = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u28,
+        }),
+    };
+
+    ///  SSP1 controller
+    pub const SSP1 = extern struct {
+        ///  Control Register 0. Selects the serial clock rate, bus type, and data size.
+        CR0: mmio.Mmio(packed struct(u32) {
+            ///  Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
+            DSS: packed union {
+                raw: u4,
+                value: enum(u4) {
+                    ///  4-bit transfer
+                    @"4_BIT_TRANSFER" = 0x3,
+                    ///  5-bit transfer
+                    @"5_BIT_TRANSFER" = 0x4,
+                    ///  6-bit transfer
+                    @"6_BIT_TRANSFER" = 0x5,
+                    ///  7-bit transfer
+                    @"7_BIT_TRANSFER" = 0x6,
+                    ///  8-bit transfer
+                    @"8_BIT_TRANSFER" = 0x7,
+                    ///  9-bit transfer
+                    @"9_BIT_TRANSFER" = 0x8,
+                    ///  10-bit transfer
+                    @"10_BIT_TRANSFER" = 0x9,
+                    ///  11-bit transfer
+                    @"11_BIT_TRANSFER" = 0xa,
+                    ///  12-bit transfer
+                    @"12_BIT_TRANSFER" = 0xb,
+                    ///  13-bit transfer
+                    @"13_BIT_TRANSFER" = 0xc,
+                    ///  14-bit transfer
+                    @"14_BIT_TRANSFER" = 0xd,
+                    ///  15-bit transfer
+                    @"15_BIT_TRANSFER" = 0xe,
+                    ///  16-bit transfer
+                    @"16_BIT_TRANSFER" = 0xf,
+                    _,
+                },
+            },
+            ///  Frame Format.
+            FRF: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  SPI
+                    SPI = 0x0,
+                    ///  TI
+                    TI = 0x1,
+                    ///  Microwire
+                    MICROWIRE = 0x2,
+                    ///  This combination is not supported and should not be used.
+                    THIS_COMBINATION_IS_ = 0x3,
+                },
+            },
+            ///  Clock Out Polarity. This bit is only used in SPI mode.
+            CPOL: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  SSP controller maintains the bus clock low between frames.
+                    BUS_LOW = 0x0,
+                    ///  SSP controller maintains the bus clock high between frames.
+                    BUS_HIGH = 0x1,
+                },
+            },
+            ///  Clock Out Phase. This bit is only used in SPI mode.
+            CPHA: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.
+                    FIRST_CLOCK = 0x0,
+                    ///  SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.
+                    SECOND_CLOCK = 0x1,
+                },
+            },
+            ///  Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).
+            SCR: u8,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u16,
+        }),
+        ///  Control Register 1. Selects master/slave and other modes.
+        CR1: mmio.Mmio(packed struct(u32) {
+            ///  Loop Back Mode.
+            LBM: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  During normal operation.
+                    NORMAL = 0x0,
+                    ///  Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).
+                    OUPTU = 0x1,
+                },
+            },
+            ///  SSP Enable.
+            SSE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The SSP controller is disabled.
+                    DISABLED = 0x0,
+                    ///  The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit.
+                    ENABLED = 0x1,
+                },
+            },
+            ///  Master/Slave Mode.This bit can only be written when the SSE bit is 0.
+            MS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.
+                    MASTER = 0x0,
+                    ///  The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.
+                    SLAVE = 0x1,
+                },
+            },
+            ///  Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO).
+            SOD: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        ///  Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.
+        DR: mmio.Mmio(packed struct(u32) {
+            ///  Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s.
+            DATA: u16,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u16,
+        }),
+        ///  Status Register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
+            TFE: u1,
+            ///  Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.
+            TNF: u1,
+            ///  Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
+            RNE: u1,
+            ///  Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
+            RFF: u1,
+            ///  Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
+            BSY: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u27,
+        }),
+        ///  Clock Prescale Register
+        CPSR: mmio.Mmio(packed struct(u32) {
+            ///  This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.
+            CPSDVSR: u8,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  Interrupt Mask Set and Clear Register
+        IMSC: mmio.Mmio(packed struct(u32) {
+            ///  Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
+            RORIM: u1,
+            ///  Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
+            RTIM: u1,
+            ///  Software should set this bit to enable interrupt when the Rx FIFO is at least half full.
+            RXIM: u1,
+            ///  Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.
+            TXIM: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        ///  Raw Interrupt Status Register
+        RIS: mmio.Mmio(packed struct(u32) {
+            ///  This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
+            RORRIS: u1,
+            ///  This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
+            RTRIS: u1,
+            ///  This bit is 1 if the Rx FIFO is at least half full.
+            RXRIS: u1,
+            ///  This bit is 1 if the Tx FIFO is at least half empty.
+            TXRIS: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        ///  Masked Interrupt Status Register
+        MIS: mmio.Mmio(packed struct(u32) {
+            ///  This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
+            RORMIS: u1,
+            ///  This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
+            RTMIS: u1,
+            ///  This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.
+            RXMIS: u1,
+            ///  This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
+            TXMIS: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        ///  SSPICR Interrupt Clear Register
+        ICR: mmio.Mmio(packed struct(u32) {
+            ///  Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.
+            RORIC: u1,
+            ///  Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]).
+            RTIC: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u30,
+        }),
+        ///  SSP0 DMA control register
+        DMACR: mmio.Mmio(packed struct(u32) {
+            ///  Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled.
+            RXDMAE: u1,
+            ///  Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled
+            TXDMAE: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u30,
+        }),
+    };
+
+    ///  Analog-to-Digital Converter (ADC)
+    pub const ADC = extern struct {
+        ///  A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01.
+            SEL: u8,
+            ///  The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
+            CLKDIV: u8,
+            ///  Burst mode
+            BURST: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start.
+                    BURST = 0x1,
+                    ///  Conversions are software controlled and require 31 clocks.
+                    SW = 0x0,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u4,
+            ///  Power down mode
+            PDN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The A/D converter is operational.
+                    POWERED = 0x1,
+                    ///  The A/D converter is in power-down mode.
+                    POWERDOWN = 0x0,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  When the BURST bit is 0, these bits control whether and when an A/D conversion is started:
+            START: packed union {
+                raw: u3,
+                value: enum(u3) {
+                    ///  No start (this value should be used when clearing PDN to 0).
+                    NO_START_THIS_VALUE = 0x0,
+                    ///  Start conversion now.
+                    START_CONVERSION_NOW = 0x1,
+                    ///  Start conversion when the edge selected by bit 27 occurs on the P2[10] pin.
+                    P2_10 = 0x2,
+                    ///  Start conversion when the edge selected by bit 27 occurs on the P1[27] pin.
+                    P1_27 = 0x3,
+                    ///  Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin.
+                    MAT0_1 = 0x4,
+                    ///  Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin.
+                    MAT0_3 = 0x5,
+                    ///  Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin.
+                    MAT1_0 = 0x6,
+                    ///  Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin.
+                    MAT1_1 = 0x7,
+                },
+            },
+            ///  This bit is significant only when the START field contains 010-111. In these cases:
+            EDGE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Start conversion on a falling edge on the selected CAP/MAT signal.
+                    FALLLING = 0x1,
+                    ///  Start conversion on a rising edge on the selected CAP/MAT signal.
+                    RISING = 0x0,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u4,
+        }),
+        ///  A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion.
+        GDR: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u4,
+            ///  When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
+            RESULT: u12,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u8,
+            ///  These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...).
+            CHN: u3,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u3,
+            ///  This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register.
+            OVERRUN: u1,
+            ///  This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
+            DONE: u1,
+        }),
+        reserved12: [4]u8,
+        ///  A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.
+        INTEN: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt enable
+            ADINTEN0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Completion of a conversion on ADC channel 0 will not generate an interrupt.
+                    DISABLE = 0x0,
+                    ///  Completion of a conversion on ADC channel 0 will generate an interrupt.
+                    ENABLE = 0x1,
+                },
+            },
+            ///  Interrupt enable
+            ADINTEN1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Completion of a conversion on ADC channel 1 will not generate an interrupt.
+                    DISABLE = 0x0,
+                    ///  Completion of a conversion on ADC channel 1 will generate an interrupt.
+                    ENABLE = 0x1,
+                },
+            },
+            ///  Interrupt enable
+            ADINTEN2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Completion of a conversion on ADC channel 2 will not generate an interrupt.
+                    DISABLE = 0x0,
+                    ///  Completion of a conversion on ADC channel 2 will generate an interrupt.
+                    ENABLE = 0x1,
+                },
+            },
+            ///  Interrupt enable
+            ADINTEN3: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Completion of a conversion on ADC channel 3 will not generate an interrupt.
+                    DISABLE = 0x0,
+                    ///  Completion of a conversion on ADC channel 3 will generate an interrupt.
+                    ENABLE = 0x1,
+                },
+            },
+            ///  Interrupt enable
+            ADINTEN4: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Completion of a conversion on ADC channel 4 will not generate an interrupt.
+                    DISABLE = 0x0,
+                    ///  Completion of a conversion on ADC channel 4 will generate an interrupt.
+                    ENABLE = 0x1,
+                },
+            },
+            ///  Interrupt enable
+            ADINTEN5: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Completion of a conversion on ADC channel 5 will not generate an interrupt.
+                    DISABLE = 0x0,
+                    ///  Completion of a conversion on ADC channel 5 will generate an interrupt.
+                    ENABLE = 0x1,
+                },
+            },
+            ///  Interrupt enable
+            ADINTEN6: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Completion of a conversion on ADC channel 6 will not generate an interrupt.
+                    DISABLE = 0x0,
+                    ///  Completion of a conversion on ADC channel 6 will generate an interrupt.
+                    ENABLE = 0x1,
+                },
+            },
+            ///  Interrupt enable
+            ADINTEN7: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Completion of a conversion on ADC channel 7 will not generate an interrupt.
+                    DISABLE = 0x0,
+                    ///  Completion of a conversion on ADC channel 7 will generate an interrupt.
+                    ENABLE = 0x1,
+                },
+            },
+            ///  Interrupt enable
+            ADGINTEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts.
+                    CHANNELS = 0x0,
+                    ///  The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts.
+                    GLOBAL = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u23,
+        }),
+        reserved48: [32]u8,
+        ///  A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag.
+        STAT: mmio.Mmio(packed struct(u32) {
+            ///  This bit mirrors the DONE status flag from the result register for A/D channel 0.
+            DONE0: u1,
+            ///  This bit mirrors the DONE status flag from the result register for A/D channel 1.
+            DONE1: u1,
+            ///  This bit mirrors the DONE status flag from the result register for A/D channel 2.
+            DONE2: u1,
+            ///  This bit mirrors the DONE status flag from the result register for A/D channel 3.
+            DONE3: u1,
+            ///  This bit mirrors the DONE status flag from the result register for A/D channel 4.
+            DONE4: u1,
+            ///  This bit mirrors the DONE status flag from the result register for A/D channel 5.
+            DONE5: u1,
+            ///  This bit mirrors the DONE status flag from the result register for A/D channel 6.
+            DONE6: u1,
+            ///  This bit mirrors the DONE status flag from the result register for A/D channel 7.
+            DONE7: u1,
+            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0.
+            OVERRUN0: u1,
+            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1.
+            OVERRUN1: u1,
+            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2.
+            OVERRUN2: u1,
+            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3.
+            OVERRUN3: u1,
+            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4.
+            OVERRUN4: u1,
+            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5.
+            OVERRUN5: u1,
+            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6.
+            OVERRUN6: u1,
+            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7.
+            OVERRUN7: u1,
+            ///  This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.
+            ADINT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u15,
+        }),
+        ///  ADC trim register.
+        TRM: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u4,
+            ///  Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user.
+            ADCOFFS: u4,
+            ///  written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write.
+            TRIM: u4,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u20,
+        }),
+    };
+
+    ///  CAN acceptance filter RAM
+    pub const CANAFRAM = struct {};
+
+    ///  CAN controller acceptance filter
+    pub const CANAF = extern struct {
+        ///  Acceptance Filter Register
+        AFMR: mmio.Mmio(packed struct(u32) {
+            ///  if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored.
+            ACCOFF: u1,
+            ///  All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers.
+            ACCBP: u1,
+            ///  FullCAN mode
+            EFCAN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers.
+                    SOFTWARE_MUST_READ_A = 0x0,
+                    ///  The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576.
+                    THE_ACCEPTANCE_FILTE = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u29,
+        }),
+        ///  Standard Frame Individual Start Address Register
+        SFF_SA: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM.
+            SFF_SA: u9,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u21,
+        }),
+        ///  Standard Frame Group Start Address Register
+        SFF_GRP_SA: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.
+            SFF_GRP_SA: u10,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u20,
+        }),
+        ///  Extended Frame Start Address Register
+        EFF_SA: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register.
+            EFF_SA: u9,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u21,
+        }),
+        ///  Extended Frame Group Start Address Register
+        EFF_GRP_SA: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.
+            EFF_GRP_SA: u10,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u20,
+        }),
+        ///  End of AF Tables register
+        ENDOFTABLE: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table.
+            ENDOFTABLE: u10,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u20,
+        }),
+        ///  LUT Error Address register
+        LUTERRAD: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables.
+            LUTERRAD: u9,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u21,
+        }),
+        ///  LUT Error Register
+        LUTERR: mmio.Mmio(packed struct(u32) {
+            ///  This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC.
+            LUTERR: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u31,
+        }),
+        ///  FullCAN interrupt enable register
+        FCANIE: mmio.Mmio(packed struct(u32) {
+            ///  Global FullCAN Interrupt Enable. When 1, this interrupt is enabled.
+            FCANIE: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u31,
+        }),
+        ///  FullCAN interrupt and capture register0
+        FCANIC0: mmio.Mmio(packed struct(u32) {
+            ///  FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31.
+            INTPND: u32,
+        }),
+        ///  FullCAN interrupt and capture register1
+        FCANIC1: mmio.Mmio(packed struct(u32) {
+            ///  FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63.
+            IntPnd32: u32,
+        }),
+    };
+
+    ///  Central CAN controller
+    pub const CCAN = extern struct {
+        ///  CAN Central Transmit Status Register
+        TXSR: mmio.Mmio(packed struct(u32) {
+            ///  When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR).
+            TS1: u1,
+            ///  When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)
+            TS2: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u6,
+            ///  When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR).
+            TBS1: u1,
+            ///  When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR).
+            TBS2: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u6,
+            ///  When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR).
+            TCS1: u1,
+            ///  When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR).
+            TCS2: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u14,
+        }),
+        ///  CAN Central Receive Status Register
+        RXSR: mmio.Mmio(packed struct(u32) {
+            ///  When 1, CAN1 is receiving a message (same as RS in CAN1GSR).
+            RS1: u1,
+            ///  When 1, CAN2 is receiving a message (same as RS in CAN2GSR).
+            RS2: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u6,
+            ///  When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR).
+            RB1: u1,
+            ///  When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR).
+            RB2: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u6,
+            ///  When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR).
+            DOS1: u1,
+            ///  When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR).
+            DOS2: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u14,
+        }),
+        ///  CAN Central Miscellaneous Register
+        MSR: mmio.Mmio(packed struct(u32) {
+            ///  When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)
+            E1: u1,
+            ///  When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)
+            E2: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u6,
+            ///  When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR).
+            BS1: u1,
+            ///  When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR).
+            BS2: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u22,
+        }),
+    };
+
+    ///  CAN1 controller
+    pub const CAN1 = extern struct {
+        ///  Controls the operating mode of the CAN Controller.
+        MOD: mmio.Mmio(packed struct(u32) {
+            ///  Reset Mode.
+            RM: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written.
+                    NORMAL_THE_CAN_CONTR = 0x0,
+                    ///  Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted.
+                    RESET_CAN_OPERATION = 0x1,
+                },
+            },
+            ///  Listen Only Mode.
+            LOM: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value.
+                    NORMAL_THE_CAN_CONT = 0x0,
+                    ///  Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging.
+                    LISTEN_ONLY_THE_CON = 0x1,
+                },
+            },
+            ///  Self Test Mode.
+            STM: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Normal. A transmitted message must be acknowledged to be considered successful.
+                    NORMAL_A_TRANSMITTE = 0x0,
+                    ///  Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR.
+                    SELF_TEST_THE_CONTR = 0x1,
+                },
+            },
+            ///  Transmit Priority Mode.
+            TPM: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.
+                    CAN_ID_THE_TRANSMIT = 0x0,
+                    ///  Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer.
+                    LOCAL_PRIORITY_THE_ = 0x1,
+                },
+            },
+            ///  Sleep Mode.
+            SM: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Wake-up. Normal operation.
+                    WAKE_UP_NORMAL_OPER = 0x0,
+                    ///  Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565.
+                    SLEEP_THE_CAN_CONTR = 0x1,
+                },
+            },
+            ///  Receive Polarity Mode.
+            RPM: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Low active. RD input is active Low (dominant bit = 0).
+                    LOW_ACTIVE_RD_INPUT = 0x0,
+                    ///  High active. RD input is active High (dominant bit = 1) -- reverse polarity.
+                    HIGH_ACTIVE_RD_INPU = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  Test Mode.
+            TM: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled. Normal operation.
+                    DISABLED_NORMAL_OPE = 0x0,
+                    ///  Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock.
+                    ENABLED_THE_TD_PIN_ = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  Command bits that affect the state of the CAN Controller
+        CMR: mmio.Mmio(packed struct(u32) {
+            ///  Transmission Request.
+            TR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Absent.No transmission request.
+                    ABSENT_NO_TRANSMISSI = 0x0,
+                    ///  Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))
+                    PRESENT_THE_MESSAGE = 0x1,
+                },
+            },
+            ///  Abort Transmission.
+            AT: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No action. Do not abort the transmission.
+                    NO_ACTION_DO_NOT_AB = 0x0,
+                    ///  Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled.
+                    PRESENT_IF_NOT_ALRE = 0x1,
+                },
+            },
+            ///  Release Receive Buffer.
+            RRB: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No action. Do not release the receive buffer.
+                    NO_ACTION_DO_NOT_RE = 0x0,
+                    ///  Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s).
+                    RELEASED_THE_INFORM = 0x1,
+                },
+            },
+            ///  Clear Data Overrun.
+            CDO: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No action. Do not clear the data overrun bit.
+                    NO_ACTION_DO_NOT_CL = 0x0,
+                    ///  Clear. The Data Overrun bit in Status Register(s) is cleared.
+                    CLEAR_THE_DATA_OVER = 0x1,
+                },
+            },
+            ///  Self Reception Request.
+            SRR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Absent. No self reception request.
+                    ABSENT_NO_SELF_RECE = 0x0,
+                    ///  Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter.
+                    PRESENT_THE_MESSAGE = 0x1,
+                },
+            },
+            ///  Select Tx Buffer 1.
+            STB1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Not selected. Tx Buffer 1 is not selected for transmission.
+                    NOT_SELECTED_TX_BUF = 0x0,
+                    ///  Selected. Tx Buffer 1 is selected for transmission.
+                    SELECTED_TX_BUFFER_ = 0x1,
+                },
+            },
+            ///  Select Tx Buffer 2.
+            STB2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Not selected. Tx Buffer 2 is not selected for transmission.
+                    NOT_SELECTED_TX_BUF = 0x0,
+                    ///  Selected. Tx Buffer 2 is selected for transmission.
+                    SELECTED_TX_BUFFER_ = 0x1,
+                },
+            },
+            ///  Select Tx Buffer 3.
+            STB3: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Not selected. Tx Buffer 3 is not selected for transmission.
+                    NOT_SELECTED_TX_BUF = 0x0,
+                    ///  Selected. Tx Buffer 3 is selected for transmission.
+                    SELECTED_TX_BUFFER_ = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1.
+        GSR: mmio.Mmio(packed struct(u32) {
+            ///  Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.
+            RBS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Empty. No message is available.
+                    EMPTY_NO_MESSAGE_IS = 0x0,
+                    ///  Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available.
+                    FULL_AT_LEAST_ONE_C = 0x1,
+                },
+            },
+            ///  Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.
+            DOS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset).
+                    ABSENT_NO_DATA_OVER = 0x0,
+                    ///  Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer).
+                    OVERRUN_A_MESSAGE_W = 0x1,
+                },
+            },
+            ///  Transmit Buffer Status.
+            TBS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s).
+                    LOCKED_AT_LEAST_ONE = 0x0,
+                    ///  Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.
+                    RELEASED_ALL_THREE_ = 0x1,
+                },
+            },
+            ///  Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.
+            TCS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Incomplete. At least one requested transmission has not been successfully completed yet.
+                    INCOMPLETE_AT_LEAST = 0x0,
+                    ///  Complete. All requested transmission(s) has (have) been successfully completed.
+                    COMPLETE_ALL_REQUES = 0x1,
+                },
+            },
+            ///  Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.
+            RS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Idle. The CAN controller is idle.
+                    IDLE_THE_CAN_CONTRO = 0x0,
+                    ///  Receive. The CAN controller is receiving a message.
+                    RECEIVE_THE_CAN_CON = 0x1,
+                },
+            },
+            ///  Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.
+            TS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Idle. The CAN controller is idle.
+                    IDLE_THE_CAN_CONTRO = 0x0,
+                    ///  Transmit. The CAN controller is sending a message.
+                    TRANSMIT_THE_CAN_CO = 0x1,
+                },
+            },
+            ///  Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).
+            ES: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  OK. Both error counters are below the Error Warning Limit.
+                    OK_BOTH_ERROR_COUNT = 0x0,
+                    ///  Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register.
+                    ERROR_ONE_OR_BOTH_O = 0x1,
+                },
+            },
+            ///  Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.
+            BS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Bus-on. The CAN Controller is involved in bus activities
+                    BUS_ON_THE_CAN_CONT = 0x0,
+                    ///  Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255.
+                    BUS_OFF_THE_CAN_CON = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u8,
+            ///  The current value of the Rx Error Counter (an 8-bit value).
+            RXERR: u8,
+            ///  The current value of the Tx Error Counter (an 8-bit value).
+            TXERR: u8,
+        }),
+        ///  Interrupt status, Arbitration Lost Capture, Error Code Capture
+        ICR: mmio.Mmio(packed struct(u32) {
+            ///  Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.
+            RI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Reset
+                    RESET = 0x0,
+                    ///  Set
+                    SET = 0x1,
+                },
+            },
+            ///  Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.
+            TI1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Reset
+                    RESET = 0x0,
+                    ///  Set
+                    SET = 0x1,
+                },
+            },
+            ///  Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.
+            EI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Reset
+                    RESET = 0x0,
+                    ///  Set
+                    SET = 0x1,
+                },
+            },
+            ///  Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.
+            DOI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Reset
+                    RESET = 0x0,
+                    ///  Set
+                    SET = 0x1,
+                },
+            },
+            ///  Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.
+            WUI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Reset
+                    RESET = 0x0,
+                    ///  Set
+                    SET = 0x1,
+                },
+            },
+            ///  Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.
+            EPI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Reset
+                    RESET = 0x0,
+                    ///  Set
+                    SET = 0x1,
+                },
+            },
+            ///  Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.
+            ALI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Reset
+                    RESET = 0x0,
+                    ///  Set
+                    SET = 0x1,
+                },
+            },
+            ///  Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.
+            BEI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Reset
+                    RESET = 0x0,
+                    ///  Set
+                    SET = 0x1,
+                },
+            },
+            ///  ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.
+            IDI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Reset
+                    RESET = 0x0,
+                    ///  Set
+                    SET = 0x1,
+                },
+            },
+            ///  Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.
+            TI2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Reset
+                    RESET = 0x0,
+                    ///  Set
+                    SET = 0x1,
+                },
+            },
+            ///  Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.
+            TI3: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Reset
+                    RESET = 0x0,
+                    ///  Set
+                    SET = 0x1,
+                },
+            },
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u5,
+            ///  Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt.
+            ERRBIT4_0: u5,
+            ///  When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.
+            ERRDIR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Error occurred during transmitting.
+                    ERROR_OCCURRED_DURIN = 0x0,
+                    ///  Error occurred during receiving.
+                    ERROR_OCCURRED_DURIN = 0x1,
+                },
+            },
+            ///  When the CAN controller detects a bus error, the type of error is captured in this field:
+            ERRC1_0: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Bit error
+                    BIT_ERROR = 0x0,
+                    ///  Form error
+                    FORM_ERROR = 0x1,
+                    ///  Stuff error
+                    STUFF_ERROR = 0x2,
+                    ///  Other error
+                    OTHER_ERROR = 0x3,
+                },
+            },
+            ///  Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again.
+            ALCBIT: u8,
+        }),
+        ///  Interrupt Enable
+        IER: mmio.Mmio(packed struct(u32) {
+            ///  Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt.
+            RIE: u1,
+            ///  Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.
+            TIE1: u1,
+            ///  Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt.
+            EIE: u1,
+            ///  Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt.
+            DOIE: u1,
+            ///  Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested.
+            WUIE: u1,
+            ///  Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested.
+            EPIE: u1,
+            ///  Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested.
+            ALIE: u1,
+            ///  Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt.
+            BEIE: u1,
+            ///  ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt.
+            IDIE: u1,
+            ///  Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.
+            TIE2: u1,
+            ///  Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.
+            TIE3: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u21,
+        }),
+        ///  Bus Timing. Can only be written when RM in CANMOD is 1.
+        BTR: mmio.Mmio(packed struct(u32) {
+            ///  Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock.
+            BRP: u10,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u4,
+            ///  The Synchronization Jump Width is (this value plus one) CAN clocks.
+            SJW: u2,
+            ///  The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks.
+            TESG1: u4,
+            ///  The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks.
+            TESG2: u3,
+            ///  Sampling
+            SAM: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The bus is sampled once (recommended for high speed buses)
+                    THE_BUS_IS_SAMPLED_O = 0x0,
+                    ///  The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)
+                    THE_BUS_IS_SAMPLED_3 = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u8,
+        }),
+        ///  Error Warning Limit. Can only be written when RM in CANMOD is 1.
+        EWL: mmio.Mmio(packed struct(u32) {
+            ///  During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set.
+            EWL: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  Status Register
+        SR: mmio.Mmio(packed struct(u32) {
+            ///  Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
+            RBS_1: u1,
+            ///  Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
+            DOS_1: u1,
+            ///  Transmit Buffer Status 1.
+            TBS1_1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.
+                    LOCKED_SOFTWARE_CAN = 0x0,
+                    ///  Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.
+                    RELEASED_SOFTWARE_M = 0x1,
+                },
+            },
+            ///  Transmission Complete Status.
+            TCS1_1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Incomplete. The previously requested transmission for Tx Buffer 1 is not complete.
+                    INCOMPLETE_THE_PREV = 0x0,
+                    ///  Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed.
+                    COMPLETE_THE_PREVIO = 0x1,
+                },
+            },
+            ///  Receive Status. This bit is identical to the RS bit in the GSR.
+            RS_1: u1,
+            ///  Transmit Status 1.
+            TS1_1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Idle. There is no transmission from Tx Buffer 1.
+                    IDLE_THERE_IS_NO_TR = 0x0,
+                    ///  Transmit. The CAN Controller is transmitting a message from Tx Buffer 1.
+                    TRANSMIT_THE_CAN_CO = 0x1,
+                },
+            },
+            ///  Error Status. This bit is identical to the ES bit in the CANxGSR.
+            ES_1: u1,
+            ///  Bus Status. This bit is identical to the BS bit in the CANxGSR.
+            BS_1: u1,
+            ///  Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
+            RBS_2: u1,
+            ///  Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
+            DOS_2: u1,
+            ///  Transmit Buffer Status 2.
+            TBS2_2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.
+                    LOCKED_SOFTWARE_CAN = 0x0,
+                    ///  Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.
+                    RELEASED_SOFTWARE_M = 0x1,
+                },
+            },
+            ///  Transmission Complete Status.
+            TCS2_2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Incomplete. The previously requested transmission for Tx Buffer 2 is not complete.
+                    INCOMPLETE_THE_PREV = 0x0,
+                    ///  Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed.
+                    COMPLETE_THE_PREVIO = 0x1,
+                },
+            },
+            ///  Receive Status. This bit is identical to the RS bit in the GSR.
+            RS_2: u1,
+            ///  Transmit Status 2.
+            TS2_2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Idle. There is no transmission from Tx Buffer 2.
+                    IDLE_THERE_IS_NO_TR = 0x0,
+                    ///  Transmit. The CAN Controller is transmitting a message from Tx Buffer 2.
+                    TRANSMIT_THE_CAN_CO = 0x1,
+                },
+            },
+            ///  Error Status. This bit is identical to the ES bit in the CANxGSR.
+            ES_2: u1,
+            ///  Bus Status. This bit is identical to the BS bit in the CANxGSR.
+            BS_2: u1,
+            ///  Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
+            RBS_3: u1,
+            ///  Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
+            DOS_3: u1,
+            ///  Transmit Buffer Status 3.
+            TBS3_3: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.
+                    LOCKED_SOFTWARE_CAN = 0x0,
+                    ///  Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.
+                    RELEASED_SOFTWARE_M = 0x1,
+                },
+            },
+            ///  Transmission Complete Status.
+            TCS3_3: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Incomplete. The previously requested transmission for Tx Buffer 3 is not complete.
+                    INCOMPLETE_THE_PREV = 0x0,
+                    ///  Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed.
+                    COMPLETE_THE_PREVIO = 0x1,
+                },
+            },
+            ///  Receive Status. This bit is identical to the RS bit in the GSR.
+            RS_3: u1,
+            ///  Transmit Status 3.
+            TS3_3: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Idle. There is no transmission from Tx Buffer 3.
+                    IDLE_THERE_IS_NO_TR = 0x0,
+                    ///  Transmit. The CAN Controller is transmitting a message from Tx Buffer 3.
+                    TRANSMIT_THE_CAN_CO = 0x1,
+                },
+            },
+            ///  Error Status. This bit is identical to the ES bit in the CANxGSR.
+            ES_3: u1,
+            ///  Bus Status. This bit is identical to the BS bit in the CANxGSR.
+            BS_3: u1,
+            ///  Reserved, the value read from a reserved bit is not defined.
+            RESERVED: u8,
+        }),
+        ///  Receive frame status. Can only be written when RM in CANMOD is 1.
+        RFS: mmio.Mmio(packed struct(u32) {
+            ///  ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values.
+            IDINDEX: u10,
+            ///  If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless.
+            BP: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u5,
+            ///  The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding.
+            DLC: u4,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u10,
+            ///  This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier.
+            RTR: u1,
+            ///  A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below.
+            FF: u1,
+        }),
+        ///  Received Identifier. Can only be written when RM in CANMOD is 1.
+        RID: mmio.Mmio(packed struct(u32) {
+            ///  The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18.
+            ID: u11,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u21,
+        }),
+        ///  Received data bytes 1-4. Can only be written when RM in CANMOD is 1.
+        RDA: mmio.Mmio(packed struct(u32) {
+            ///  Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message.
+            DATA1: u8,
+            ///  Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message.
+            DATA2: u8,
+            ///  Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message.
+            DATA3: u8,
+            ///  Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message.
+            DATA4: u8,
+        }),
+        ///  Received data bytes 5-8. Can only be written when RM in CANMOD is 1.
+        RDB: mmio.Mmio(packed struct(u32) {
+            ///  Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message.
+            DATA5: u8,
+            ///  Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message.
+            DATA6: u8,
+            ///  Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message.
+            DATA7: u8,
+            ///  Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message.
+            DATA8: u8,
+        }),
+    };
+
+    ///  USB device/host/OTG controller
+    pub const USB = extern struct {
+        reserved220: [220]u8,
+        ///  USB Receive Packet Length
+        RXPLEN: mmio.Mmio(packed struct(u32) {
+            ///  The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt.
+            PKT_LNGTH: u10,
+            ///  Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.
+            DV: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Data is invalid.
+                    DATA_IS_INVALID_ = 0x0,
+                    ///  Data is valid.
+                    DATA_IS_VALID_ = 0x1,
+                },
+            },
+            ///  The PKT_LNGTH field is valid and the packet is ready for reading.
+            PKT_RDY: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u20,
+        }),
+        reserved256: [32]u8,
+        ///  OTG Interrupt Status
+        INTST: mmio.Mmio(packed struct(u32) {
+            ///  Timer time-out.
+            TMR: u1,
+            ///  Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor.
+            REMOVE_PU: u1,
+            ///  HNP failed. This bit is set by hardware to indicate that the HNP switching has failed.
+            HNP_FAILURE: u1,
+            ///  HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded.
+            HNP_SUCCESS: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u28,
+        }),
+        ///  OTG Interrupt Enable
+        INTEN: mmio.Mmio(packed struct(u32) {
+            ///  1 = enable the corresponding bit in the IntSt register.
+            TMR_EN: u1,
+            ///  1 = enable the corresponding bit in the IntSt register.
+            REMOVE_PU_EN: u1,
+            ///  1 = enable the corresponding bit in the IntSt register.
+            HNP_FAILURE_EN: u1,
+            ///  1 = enable the corresponding bit in the IntSt register.
+            HNP_SUCCES_EN: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u28,
+        }),
+        ///  OTG Interrupt Set
+        INTSET: mmio.Mmio(packed struct(u32) {
+            ///  0 = no effect. 1 = set the corresponding bit in the IntSt register.
+            TMR_SET: u1,
+            ///  0 = no effect. 1 = set the corresponding bit in the IntSt register.
+            REMOVE_PU_SET: u1,
+            ///  0 = no effect. 1 = set the corresponding bit in the IntSt register.
+            HNP_FAILURE_SET: u1,
+            ///  0 = no effect. 1 = set the corresponding bit in the IntSt register.
+            HNP_SUCCES_SET: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u28,
+        }),
+        ///  OTG Interrupt Clear
+        INTCLR: mmio.Mmio(packed struct(u32) {
+            ///  0 = no effect. 1 = clear the corresponding bit in the IntSt register.
+            TMR_CLR: u1,
+            ///  0 = no effect. 1 = clear the corresponding bit in the IntSt register.
+            REMOVE_PU_CLR: u1,
+            ///  0 = no effect. 1 = clear the corresponding bit in the IntSt register.
+            HNP_FAILURE_CLR: u1,
+            ///  0 = no effect. 1 = clear the corresponding bit in the IntSt register.
+            HNP_SUCCES_CLR: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u28,
+        }),
+        ///  OTG Status and Control and USB port select
+        STCTRL: mmio.Mmio(packed struct(u32) {
+            ///  Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2.
+            PORT_FUNC: u2,
+            ///  Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved
+            TMR_SCALE: u2,
+            ///  Timer mode selection. 0: monoshot 1: free running
+            TMR_MODE: u1,
+            ///  Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0.
+            TMR_EN: u1,
+            ///  Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled.
+            TMR_RST: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.
+            B_HNP_TRACK: u1,
+            ///  Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.
+            A_HNP_TRACK: u1,
+            ///  When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.
+            PU_REMOVED: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u5,
+            ///  Current timer count value.
+            TMR_CNT: u16,
+        }),
+        ///  OTG Timer
+        TMR: mmio.Mmio(packed struct(u32) {
+            ///  The TMR interrupt is set when TMR_CNT reaches this value.
+            TIMEOUT_CNT: u16,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+        reserved512: [232]u8,
+        ///  USB Device Interrupt Status
+        DEVINTST: mmio.Mmio(packed struct(u32) {
+            ///  The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers.
+            FRAME: u1,
+            ///  Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit.
+            EP_FAST: u1,
+            ///  Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit.
+            EP_SLOW: u1,
+            ///  Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366.
+            DEV_STAT: u1,
+            ///  The command code register (USBCmdCode) is empty (New command can be written).
+            CCEMPTY: u1,
+            ///  Command data register (USBCmdData) is full (Data can be read now).
+            CDFULL: u1,
+            ///  The current packet in the endpoint buffer is transferred to the CPU.
+            RxENDPKT: u1,
+            ///  The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen).
+            TxENDPKT: u1,
+            ///  Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed.
+            EP_RLZED: u1,
+            ///  Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368
+            ERR_INT: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u22,
+        }),
+        ///  USB Device Interrupt Enable
+        DEVINTEN: mmio.Mmio(packed struct(u32) {
+            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
+            FRAMEEN: u1,
+            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
+            EP_FASTEN: u1,
+            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
+            EP_SLOWEN: u1,
+            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
+            DEV_STATEN: u1,
+            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
+            CCEMPTYEN: u1,
+            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
+            CDFULLEN: u1,
+            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
+            RxENDPKTEN: u1,
+            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
+            TxENDPKTEN: u1,
+            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
+            EP_RLZEDEN: u1,
+            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
+            ERR_INTEN: u1,
+            ///  Reserved
+            RESERVED: u22,
+        }),
+        ///  USB Device Interrupt Clear
+        DEVINTCLR: mmio.Mmio(packed struct(u32) {
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
+            FRAMECLR: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
+            EP_FASTCLR: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
+            EP_SLOWCLR: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
+            DEV_STATCLR: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
+            CCEMPTYCLR: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
+            CDFULLCLR: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
+            RxENDPKTCLR: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
+            TxENDPKTCLR: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
+            EP_RLZEDCLR: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
+            ERR_INTCLR: u1,
+            ///  Reserved
+            RESERVED: u22,
+        }),
+        ///  USB Device Interrupt Set
+        DEVINTSET: mmio.Mmio(packed struct(u32) {
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
+            FRAMESET: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
+            EP_FASTSET: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
+            EP_SLOWSET: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
+            DEV_STATSET: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
+            CCEMPTYSET: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
+            CDFULLSET: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
+            RxENDPKTSET: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
+            TxENDPKTSET: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
+            EP_RLZEDSET: u1,
+            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
+            ERR_INTSET: u1,
+            ///  Reserved
+            RESERVED: u22,
+        }),
+        ///  USB Command Code
+        CMDCODE: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u8,
+            ///  The command phase:
+            CMD_PHASE: packed union {
+                raw: u8,
+                value: enum(u8) {
+                    ///  Read
+                    READ = 0x2,
+                    ///  Write
+                    WRITE = 0x1,
+                    ///  Command
+                    COMMAND = 0x5,
+                    _,
+                },
+            },
+            ///  This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA).
+            CMD_CODE_WDATA: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u8,
+        }),
+        ///  USB Command Data
+        CMDDATA: mmio.Mmio(packed struct(u32) {
+            ///  Command Read Data.
+            CMD_RDATA: u8,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  USB Receive Data
+        RXDATA: mmio.Mmio(packed struct(u32) {
+            ///  Data received.
+            RX_DATA: u32,
+        }),
+        ///  USB Transmit Data
+        TXDATA: mmio.Mmio(packed struct(u32) {
+            ///  Transmit Data.
+            TX_DATA: u32,
+        }),
+        reserved548: [4]u8,
+        ///  USB Transmit Packet Length
+        TXPLEN: mmio.Mmio(packed struct(u32) {
+            ///  The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt.
+            PKT_LNGTH: u10,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u22,
+        }),
+        ///  USB Control
+        CTRL: mmio.Mmio(packed struct(u32) {
+            ///  Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.
+            RD_EN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Enabled.
+                    ENABLED_ = 0x1,
+                },
+            },
+            ///  Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.
+            WR_EN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Enabled.
+                    ENABLED_ = 0x1,
+                },
+            },
+            ///  Logical Endpoint number.
+            LOG_ENDPOINT: u4,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u26,
+        }),
+        ///  USB Device Interrupt Priority
+        DEVINTPRI: mmio.Mmio(packed struct(u32) {
+            ///  Frame interrupt routing
+            FRAME: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  FRAME interrupt is routed to USB_INT_REQ_LP.
+                    LP = 0x0,
+                    ///  FRAME interrupt is routed to USB_INT_REQ_HP.
+                    HP = 0x1,
+                },
+            },
+            ///  Fast endpoint interrupt routing
+            EP_FAST: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  EP_FAST interrupt is routed to USB_INT_REQ_LP.
+                    LP = 0x0,
+                    ///  EP_FAST interrupt is routed to USB_INT_REQ_HP.
+                    HP = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u30,
+        }),
+        ///  USB Endpoint Interrupt Status
+        EPINTST: mmio.Mmio(packed struct(u32) {
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST0: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST1: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST2: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST3: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST4: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST5: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST6: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST7: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST8: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST9: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST10: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST11: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST12: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST13: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST14: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST15: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST16: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST17: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST18: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST19: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST20: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST21: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST22: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST23: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST24: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST25: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST26: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST27: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST28: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST29: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST30: u1,
+            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
+            EPST31: u1,
+        }),
+        ///  USB Endpoint Interrupt Enable
+        EPINTEN: mmio.Mmio(packed struct(u32) {
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN0: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN1: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN2: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN3: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN4: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN5: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN6: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN7: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN8: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN9: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN10: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN11: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN12: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN13: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN14: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN15: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN16: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN17: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN18: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN19: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN20: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN21: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN22: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN23: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN24: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN25: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN26: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN27: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN28: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN29: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN30: u1,
+            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
+            EPEN31: u1,
+        }),
+        ///  USB Endpoint Interrupt Clear
+        EPINTCLR: mmio.Mmio(packed struct(u32) {
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR0: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR1: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR2: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR3: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR4: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR5: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR6: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR7: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR8: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR9: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR10: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR11: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR12: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR13: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR14: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR15: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR16: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR17: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR18: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR19: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR20: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR21: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR22: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR23: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR24: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR25: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR26: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR27: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR28: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR29: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR30: u1,
+            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
+            EPCLR31: u1,
+        }),
+        ///  USB Endpoint Interrupt Set
+        EPINTSET: mmio.Mmio(packed struct(u32) {
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET0: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET1: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET2: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET3: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET4: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET5: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET6: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET7: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET8: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET9: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET10: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET11: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET12: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET13: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET14: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET15: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET16: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET17: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET18: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET19: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET20: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET21: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET22: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET23: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET24: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET25: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET26: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET27: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET28: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET29: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET30: u1,
+            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
+            EPSET31: u1,
+        }),
+        ///  USB Endpoint Priority
+        EPINTPRI: mmio.Mmio(packed struct(u32) {
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI0: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI1: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI2: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI3: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI4: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI5: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI6: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI7: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI8: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI9: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI10: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI11: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI12: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI13: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI14: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI15: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI16: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI17: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI18: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI19: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI20: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI21: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI22: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI23: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI24: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI25: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI26: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI27: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI28: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI29: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI30: u1,
+            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
+            EPPRI31: u1,
+        }),
+        ///  USB Realize Endpoint
+        REEP: mmio.Mmio(packed struct(u32) {
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR0: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR1: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR2: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR3: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR4: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR5: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR6: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR7: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR8: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR9: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR10: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR11: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR12: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR13: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR14: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR15: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR16: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR17: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR18: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR19: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR20: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR21: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR22: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR23: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR24: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR25: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR26: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR27: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR28: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR29: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR30: u1,
+            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
+            EPR31: u1,
+        }),
+        ///  USB Endpoint Index
+        EPIND: mmio.Mmio(packed struct(u32) {
+            ///  Physical endpoint number (0-31)
+            PHY_EP: u5,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u27,
+        }),
+        ///  USB MaxPacketSize
+        MAXPSIZE: mmio.Mmio(packed struct(u32) {
+            ///  The maximum packet size value.
+            MPS: u10,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u22,
+        }),
+        ///  USB DMA Request Status
+        DMARST: mmio.Mmio(packed struct(u32) {
+            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0).
+            EPRST0: u1,
+            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0).
+            EPRST1: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST2: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST3: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST4: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST5: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST6: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST7: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST8: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST9: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST10: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST11: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST12: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST13: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST14: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST15: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST16: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST17: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST18: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST19: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST20: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST21: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST22: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST23: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST24: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST25: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST26: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST27: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST28: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST29: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST30: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
+            EPRST31: u1,
+        }),
+        ///  USB DMA Request Clear
+        DMARCLR: mmio.Mmio(packed struct(u32) {
+            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).
+            EPRCLR0: u1,
+            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).
+            EPRCLR1: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR2: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR3: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR4: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR5: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR6: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR7: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR8: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR9: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR10: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR11: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR12: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR13: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR14: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR15: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR16: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR17: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR18: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR19: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR20: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR21: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR22: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR23: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR24: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR25: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR26: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR27: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR28: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR29: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR30: u1,
+            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
+            EPRCLR31: u1,
+        }),
+        ///  USB DMA Request Set
+        DMARSET: mmio.Mmio(packed struct(u32) {
+            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).
+            EPRSET0: u1,
+            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).
+            EPRSET1: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET2: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET3: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET4: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET5: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET6: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET7: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET8: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET9: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET10: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET11: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET12: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET13: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET14: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET15: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET16: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET17: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET18: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET19: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET20: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET21: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET22: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET23: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET24: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET25: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET26: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET27: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET28: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET29: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET30: u1,
+            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
+            EPRSET31: u1,
+        }),
+        reserved640: [36]u8,
+        ///  USB UDCA Head
+        UDCAH: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries.
+            RESERVED: u7,
+            ///  Start address of the UDCA.
+            UDCA_ADDR: u25,
+        }),
+        ///  USB Endpoint DMA Status
+        EPDMAST: mmio.Mmio(packed struct(u32) {
+            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0).
+            EP_DMA_ST0: u1,
+            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).
+            EP_DMA_ST1: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST2: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST3: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST4: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST5: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST6: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST7: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST8: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST9: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST10: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST11: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST12: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST13: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST14: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST15: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST16: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST17: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST18: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST19: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST20: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST21: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST22: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST23: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST24: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST25: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST26: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST27: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST28: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST29: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST30: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
+            EP_DMA_ST31: u1,
+        }),
+        ///  USB Endpoint DMA Enable
+        EPDMAEN: mmio.Mmio(packed struct(u32) {
+            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0).
+            EP_DMA_EN0: u1,
+            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).
+            EP_DMA_EN1: u1,
+            ///  Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx.
+            EP_DMA_EN: u30,
+        }),
+        ///  USB Endpoint DMA Disable
+        EPDMADIS: mmio.Mmio(packed struct(u32) {
+            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0).
+            EP_DMA_DIS0: u1,
+            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0).
+            EP_DMA_DIS1: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS2: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS3: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS4: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS5: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS6: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS7: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS8: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS9: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS10: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS11: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS12: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS13: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS14: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS15: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS16: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS17: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS18: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS19: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS20: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS21: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS22: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS23: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS24: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS25: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS26: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS27: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS28: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS29: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS30: u1,
+            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
+            EP_DMA_DIS31: u1,
+        }),
+        ///  USB DMA Interrupt Status
+        DMAINTST: mmio.Mmio(packed struct(u32) {
+            ///  End of Transfer Interrupt bit.
+            EOT: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  All bits in the USBEoTIntSt register are 0.
+                    ALL_BITS_IN_THE_USBE = 0x0,
+                    ///  At least one bit in the USBEoTIntSt is set.
+                    AT_LEAST_ONE_BIT_IN_ = 0x1,
+                },
+            },
+            ///  New DD Request Interrupt bit.
+            NDDR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  All bits in the USBNDDRIntSt register are 0.
+                    ALL_BITS_IN_THE_USBN = 0x0,
+                    ///  At least one bit in the USBNDDRIntSt is set.
+                    AT_LEAST_ONE_BIT_IN_ = 0x1,
+                },
+            },
+            ///  System Error Interrupt bit.
+            ERR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  All bits in the USBSysErrIntSt register are 0.
+                    ALL_BITS_IN_THE_USBS = 0x0,
+                    ///  At least one bit in the USBSysErrIntSt is set.
+                    AT_LEAST_ONE_BIT_IN_ = 0x1,
+                },
+            },
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u29,
+        }),
+        ///  USB DMA Interrupt Enable
+        DMAINTEN: mmio.Mmio(packed struct(u32) {
+            ///  End of Transfer Interrupt enable bit.
+            EOT: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Enabled.
+                    ENABLED_ = 0x1,
+                },
+            },
+            ///  New DD Request Interrupt enable bit.
+            NDDR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Enabled.
+                    ENABLED_ = 0x1,
+                },
+            },
+            ///  System Error Interrupt enable bit.
+            ERR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled.
+                    DISABLED_ = 0x0,
+                    ///  Enabled.
+                    ENABLED_ = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u29,
+        }),
+        reserved672: [8]u8,
+        ///  USB End of Transfer Interrupt Status
+        EOTINTST: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST0: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST1: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST2: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST3: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST4: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST5: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST6: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST7: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST8: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST9: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST10: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST11: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST12: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST13: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST14: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST15: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST16: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST17: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST18: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST19: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST20: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST21: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST22: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST23: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST24: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST25: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST26: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST27: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST28: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST29: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST30: u1,
+            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
+            EPTXINTST31: u1,
+        }),
+        ///  USB End of Transfer Interrupt Clear
+        EOTINTCLR: mmio.Mmio(packed struct(u32) {
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR0: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR1: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR2: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR3: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR4: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR5: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR6: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR7: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR8: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR9: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR10: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR11: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR12: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR13: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR14: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR15: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR16: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR17: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR18: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR19: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR20: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR21: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR22: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR23: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR24: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR25: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR26: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR27: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR28: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR29: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR30: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTCLR31: u1,
+        }),
+        ///  USB End of Transfer Interrupt Set
+        EOTINTSET: mmio.Mmio(packed struct(u32) {
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET0: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET1: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET2: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET3: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET4: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET5: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET6: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET7: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET8: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET9: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET10: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET11: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET12: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET13: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET14: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET15: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET16: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET17: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET18: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET19: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET20: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET21: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET22: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET23: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET24: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET25: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET26: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET27: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET28: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET29: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET30: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
+            EPTXINTSET31: u1,
+        }),
+        ///  USB New DD Request Interrupt Status
+        NDDRINTST: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST0: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST1: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST2: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST3: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST4: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST5: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST6: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST7: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST8: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST9: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST10: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST11: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST12: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST13: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST14: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST15: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST16: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST17: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST18: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST19: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST20: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST21: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST22: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST23: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST24: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST25: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST26: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST27: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST28: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST29: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST30: u1,
+            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
+            EPNDDINTST31: u1,
+        }),
+        ///  USB New DD Request Interrupt Clear
+        NDDRINTCLR: mmio.Mmio(packed struct(u32) {
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR0: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR1: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR2: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR3: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR4: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR5: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR6: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR7: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR8: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR9: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR10: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR11: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR12: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR13: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR14: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR15: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR16: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR17: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR18: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR19: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR20: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR21: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR22: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR23: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR24: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR25: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR26: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR27: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR28: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR29: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR30: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTCLR31: u1,
+        }),
+        ///  USB New DD Request Interrupt Set
+        NDDRINTSET: mmio.Mmio(packed struct(u32) {
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET0: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET1: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET2: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET3: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET4: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET5: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET6: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET7: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET8: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET9: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET10: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET11: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET12: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET13: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET14: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET15: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET16: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET17: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET18: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET19: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET20: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET21: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET22: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET23: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET24: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET25: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET26: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET27: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET28: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET29: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET30: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
+            EPNDDINTSET31: u1,
+        }),
+        ///  USB System Error Interrupt Status
+        SYSERRINTST: mmio.Mmio(packed struct(u32) {
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST0: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST1: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST2: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST3: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST4: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST5: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST6: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST7: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST8: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST9: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST10: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST11: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST12: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST13: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST14: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST15: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST16: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST17: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST18: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST19: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST20: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST21: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST22: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST23: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST24: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST25: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST26: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST27: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST28: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST29: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST30: u1,
+            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
+            EPERRINTST31: u1,
+        }),
+        ///  USB System Error Interrupt Clear
+        SYSERRINTCLR: mmio.Mmio(packed struct(u32) {
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR0: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR1: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR2: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR3: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR4: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR5: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR6: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR7: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR8: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR9: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR10: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR11: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR12: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR13: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR14: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR15: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR16: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR17: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR18: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR19: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR20: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR21: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR22: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR23: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR24: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR25: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR26: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR27: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR28: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR29: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR30: u1,
+            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTCLR31: u1,
+        }),
+        ///  USB System Error Interrupt Set
+        SYSERRINTSET: mmio.Mmio(packed struct(u32) {
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET0: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET1: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET2: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET3: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET4: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET5: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET6: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET7: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET8: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET9: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET10: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET11: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET12: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET13: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET14: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET15: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET16: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET17: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET18: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET19: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET20: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET21: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET22: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET23: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET24: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET25: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET26: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET27: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET28: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET29: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET30: u1,
+            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
+            EPERRINTSET31: u1,
+        }),
+        reserved768: [60]u8,
+        ///  I2C Receive
+        I2C_RX: mmio.Mmio(packed struct(u32) {
+            ///  Receive data.
+            RXDATA: u8,
+            padding: u24,
+        }),
+        ///  I2C Status
+        I2C_STS: mmio.Mmio(packed struct(u32) {
+            ///  Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.
+            TDI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Transaction has not completed.
+                    NOT_COMPLETE = 0x0,
+                    ///  Transaction completed.
+                    COMPLETE = 0x1,
+                },
+            },
+            ///  Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.
+            AFI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No arbitration failure on last transmission.
+                    NO_ARBITRATION_FAILU = 0x0,
+                    ///  Arbitration failure occurred on last transmission.
+                    ARBITRATION_FAILURE_ = 0x1,
+                },
+            },
+            ///  No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.
+            NAI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Last transmission received an acknowledge.
+                    ACKNOWLEDGE_RCVD = 0x0,
+                    ///  Last transmission did not receive an acknowledge.
+                    NO_ACKNOWLEDGE_RCVD = 0x1,
+                },
+            },
+            ///  Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.
+            DRMI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Master transmitter does not need data.
+                    BUSY = 0x0,
+                    ///  Master transmitter needs data.
+                    NEED_DATA = 0x1,
+                },
+            },
+            ///  Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.
+            DRSI: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Slave transmitter does not need data.
+                    BUSY = 0x0,
+                    ///  Slave transmitter needs data.
+                    NEED_DATA = 0x1,
+                },
+            },
+            ///  Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen..
+            Active: u1,
+            ///  The current value of the SCL signal.
+            SCL: u1,
+            ///  The current value of the SDA signal.
+            SDA: u1,
+            ///  Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.
+            RFF: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  RX FIFO is not full
+                    RX_FIFO_IS_NOT_FULL = 0x0,
+                    ///  RX FIFO is full
+                    RX_FIFO_IS_FULL = 0x1,
+                },
+            },
+            ///  Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.
+            RFE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  RX FIFO contains data.
+                    DATA = 0x0,
+                    ///  RX FIFO is empty
+                    EMPTY = 0x1,
+                },
+            },
+            ///  Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.
+            TFF: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  TX FIFO is not full.
+                    TX_FIFO_IS_NOT_FULL_ = 0x0,
+                    ///  TX FIFO is full
+                    TX_FIFO_IS_FULL = 0x1,
+                },
+            },
+            ///  Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.
+            TFE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  TX FIFO contains valid data.
+                    VALID_DATA = 0x0,
+                    ///  TX FIFO is empty
+                    EMPTY = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u20,
+        }),
+        ///  I2C Control
+        I2C_CTL: mmio.Mmio(packed struct(u32) {
+            ///  Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.
+            TDIE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable the TDI interrupt.
+                    DISABLE_THE_TDI_INTE = 0x0,
+                    ///  Enable the TDI interrupt.
+                    ENABLE_THE_TDI_INTER = 0x1,
+                },
+            },
+            ///  Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.
+            AFIE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable the AFI.
+                    DISABLE_THE_AFI_ = 0x0,
+                    ///  Enable the AFI.
+                    ENABLE_THE_AFI_ = 0x1,
+                },
+            },
+            ///  Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.
+            NAIE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable the NAI.
+                    DISABLE_THE_NAI_ = 0x0,
+                    ///  Enable the NAI.
+                    ENABLE_THE_NAI_ = 0x1,
+                },
+            },
+            ///  Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.
+            DRMIE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable the DRMI interrupt.
+                    DISABLE_THE_DRMI_INT = 0x0,
+                    ///  Enable the DRMI interrupt.
+                    ENABLE_THE_DRMI_INTE = 0x1,
+                },
+            },
+            ///  Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.
+            DRSIE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable the DRSI interrupt.
+                    DISABLE_THE_DRSI_INT = 0x0,
+                    ///  Enable the DRSI interrupt.
+                    ENABLE_THE_DRSI_INTE = 0x1,
+                },
+            },
+            ///  Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.
+            REFIE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable the RFFI.
+                    DISABLE_THE_RFFI_ = 0x0,
+                    ///  Enable the RFFI.
+                    ENABLE_THE_RFFI_ = 0x1,
+                },
+            },
+            ///  Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).
+            RFDAIE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable the DAI.
+                    DISABLE_THE_DAI_ = 0x0,
+                    ///  Enable the DAI.
+                    ENABLE_THE_DAI_ = 0x1,
+                },
+            },
+            ///  Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.
+            TFFIE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable the TFFI.
+                    DISABLE_THE_TFFI_ = 0x0,
+                    ///  Enable the TFFI.
+                    ENABLE_THE_TFFI_ = 0x1,
+                },
+            },
+            ///  Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.
+            SRST: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  No reset.
+                    NO_RESET = 0x0,
+                    ///  Reset the I2C to idle state. Self clearing.
+                    RESET = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u23,
+        }),
+        ///  I2C Clock High
+        I2C_CLKHI: mmio.Mmio(packed struct(u32) {
+            ///  Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high.
+            CDHI: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  I2C Clock Low
+        I2C_CLKLO: mmio.Mmio(packed struct(u32) {
+            ///  Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low.
+            CDLO: u8,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        reserved4084: [3296]u8,
+        ///  USB Clock Control
+        USBCLKCTRL: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  Device clock enable. Enables the usbclk input to the device controller
+            DEV_CLK_EN: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  Port select register clock enable.
+            PORTSEL_CLK_EN: u1,
+            ///  AHB clock enable
+            AHB_CLK_EN: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u27,
+        }),
+        ///  USB Clock Status
+        USBCLKST: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  Device clock on. The usbclk input to the device controller is active .
+            DEV_CLK_ON: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  Port select register clock on.
+            PORTSEL_CLK_ON: u1,
+            ///  AHB clock on.
+            AHB_CLK_ON: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u27,
+        }),
+    };
+
+    ///  General purpose DMA controller
+    pub const GPDMA = extern struct {
+        ///  DMA Interrupt Status Register
+        INTSTAT: mmio.Mmio(packed struct(u32) {
+            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
+            INTSTAT0: u1,
+            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
+            INTSTAT1: u1,
+            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
+            INTSTAT2: u1,
+            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
+            INTSTAT3: u1,
+            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
+            INTSTAT4: u1,
+            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
+            INTSTAT5: u1,
+            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
+            INTSTAT6: u1,
+            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
+            INTSTAT7: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  DMA Interrupt Terminal Count Request Status Register
+        INTTCSTAT: mmio.Mmio(packed struct(u32) {
+            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            INTTCSTAT0: u1,
+            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            INTTCSTAT1: u1,
+            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            INTTCSTAT2: u1,
+            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            INTTCSTAT3: u1,
+            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            INTTCSTAT4: u1,
+            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            INTTCSTAT5: u1,
+            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            INTTCSTAT6: u1,
+            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            INTTCSTAT7: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  DMA Interrupt Terminal Count Request Clear Register
+        INTTCCLEAR: mmio.Mmio(packed struct(u32) {
+            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
+            INTTCCLEAR0: u1,
+            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
+            INTTCCLEAR1: u1,
+            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
+            INTTCCLEAR2: u1,
+            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
+            INTTCCLEAR3: u1,
+            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
+            INTTCCLEAR4: u1,
+            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
+            INTTCCLEAR5: u1,
+            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
+            INTTCCLEAR6: u1,
+            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
+            INTTCCLEAR7: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  DMA Interrupt Error Status Register
+        INTERRSTAT: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            INTERRSTAT0: u1,
+            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            INTERRSTAT1: u1,
+            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            INTERRSTAT2: u1,
+            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            INTERRSTAT3: u1,
+            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            INTERRSTAT4: u1,
+            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            INTERRSTAT5: u1,
+            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            INTERRSTAT6: u1,
+            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            INTERRSTAT7: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  DMA Interrupt Error Clear Register
+        INTERRCLR: mmio.Mmio(packed struct(u32) {
+            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
+            INTERRCLR0: u1,
+            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
+            INTERRCLR1: u1,
+            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
+            INTERRCLR2: u1,
+            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
+            INTERRCLR3: u1,
+            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
+            INTERRCLR4: u1,
+            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
+            INTERRCLR5: u1,
+            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
+            INTERRCLR6: u1,
+            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
+            INTERRCLR7: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  DMA Raw Interrupt Terminal Count Status Register
+        RAWINTTCSTAT: mmio.Mmio(packed struct(u32) {
+            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            RAWINTTCSTAT0: u1,
+            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            RAWINTTCSTAT1: u1,
+            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            RAWINTTCSTAT2: u1,
+            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            RAWINTTCSTAT3: u1,
+            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            RAWINTTCSTAT4: u1,
+            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            RAWINTTCSTAT5: u1,
+            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            RAWINTTCSTAT6: u1,
+            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
+            RAWINTTCSTAT7: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  DMA Raw Error Interrupt Status Register
+        RAWINTERRSTAT: mmio.Mmio(packed struct(u32) {
+            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            RAWINTERRSTAT0: u1,
+            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            RAWINTERRSTAT1: u1,
+            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            RAWINTERRSTAT2: u1,
+            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            RAWINTERRSTAT3: u1,
+            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            RAWINTERRSTAT4: u1,
+            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            RAWINTERRSTAT5: u1,
+            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            RAWINTERRSTAT6: u1,
+            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
+            RAWINTERRSTAT7: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  DMA Enabled Channel Register
+        ENBLDCHNS: mmio.Mmio(packed struct(u32) {
+            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
+            ENABLEDCHANNELS0: u1,
+            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
+            ENABLEDCHANNELS1: u1,
+            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
+            ENABLEDCHANNELS2: u1,
+            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
+            ENABLEDCHANNELS3: u1,
+            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
+            ENABLEDCHANNELS4: u1,
+            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
+            ENABLEDCHANNELS5: u1,
+            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
+            ENABLEDCHANNELS6: u1,
+            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
+            ENABLEDCHANNELS7: u1,
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  DMA Software Burst Request Register
+        SOFTBREQ: mmio.Mmio(packed struct(u32) {
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ0: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ1: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ2: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ3: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ4: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ5: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ6: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ7: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ8: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ9: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ10: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ11: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ12: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ13: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ14: u1,
+            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
+            SOFTBREQ15: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+        ///  DMA Software Single Request Register
+        SOFTSREQ: mmio.Mmio(packed struct(u32) {
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ0: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ1: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ2: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ3: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ4: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ5: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ6: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ7: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ8: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ9: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ10: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ11: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ12: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ13: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ14: u1,
+            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
+            SOFTSREQ15: u1,
+            ///  Reserved. Read undefined. Write reserved bits as zero.
+            RESERVED: u16,
+        }),
+        ///  DMA Software Last Burst Request Register
+        SOFTLBREQ: mmio.Mmio(packed struct(u32) {
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ0: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ1: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ2: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ3: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ4: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ5: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ6: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ7: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ8: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ9: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ10: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ11: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ12: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ13: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ14: u1,
+            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
+            SOFTLBREQ15: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+        ///  DMA Software Last Single Request Register
+        SOFTLSREQ: mmio.Mmio(packed struct(u32) {
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ0: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ1: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ2: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ3: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ4: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ5: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ6: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ7: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ8: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ9: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ10: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ11: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ12: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ13: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ14: u1,
+            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
+            SOFTLSREQ15: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+        ///  DMA Configuration Register
+        CONFIG: mmio.Mmio(packed struct(u32) {
+            ///  DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled.
+            E: u1,
+            ///  AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode.
+            M: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u30,
+        }),
+        ///  DMA Synchronization Register
+        SYNC: mmio.Mmio(packed struct(u32) {
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC0: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC1: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC2: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC3: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC4: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC5: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC6: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC7: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC8: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC9: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC10: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC11: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC12: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC13: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC14: u1,
+            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
+            DMACSYNC15: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+    };
+
+    ///  Ethernet
+    pub const EMAC = extern struct {
+        ///  MAC configuration register 1.
+        MAC1: mmio.Mmio(packed struct(u32) {
+            ///  RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream.
+            RXENABLE: u1,
+            ///  PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames.
+            PARF: u1,
+            ///  RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored.
+            RXFLOWCTRL: u1,
+            ///  TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked.
+            TXFLOWCTRL: u1,
+            ///  Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation.
+            LOOPBACK: u1,
+            ///  Unused
+            RESERVED: u3,
+            ///  Setting this bit will put the Transmit Function logic in reset.
+            RESETTX: u1,
+            ///  Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control.
+            RESETMCSTX: u1,
+            ///  Setting this bit will put the Ethernet receive logic in reset.
+            RESETRX: u1,
+            ///  Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control.
+            RESETMCSRX: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function.
+            SIMRESET: u1,
+            ///  SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface.
+            SOFTRESET: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+        ///  MAC configuration register 2.
+        MAC2: mmio.Mmio(packed struct(u32) {
+            ///  When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode.
+            FULLDUPLEX: u1,
+            ///  FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame.
+            FLC: u1,
+            ///  HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received.
+            HFEN: u1,
+            ///  DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header.
+            DELAYEDCRC: u1,
+            ///  CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC.
+            CRCEN: u1,
+            ///  PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function.
+            PADCRCEN: u1,
+            ///  VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared.
+            VLANPADEN: u1,
+            ///  AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared.
+            AUTODETPADEN: u1,
+            ///  PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed.
+            PPENF: u1,
+            ///  LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard.
+            LPENF: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u2,
+            ///  When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard.
+            NOBACKOFF: u1,
+            ///  BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent.
+            BP_NOBACKOFF: u1,
+            ///  When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached.
+            EXCESSDEFER: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u17,
+        }),
+        ///  Back-to-Back Inter-Packet-Gap register.
+        IPGT: mmio.Mmio(packed struct(u32) {
+            ///  BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode).
+            BTOBINTEGAP: u7,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u25,
+        }),
+        ///  Non Back-to-Back Inter-Packet-Gap register.
+        IPGR: mmio.Mmio(packed struct(u32) {
+            ///  NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode).
+            NBTOBINTEGAP2: u7,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)
+            NBTOBINTEGAP1: u7,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u17,
+        }),
+        ///  Collision window / Retry register.
+        CLRT: mmio.Mmio(packed struct(u32) {
+            ///  RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5.
+            RETRANSMAX: u4,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u4,
+            ///  COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD.
+            COLLWIN: u6,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u18,
+        }),
+        ///  Maximum Frame register.
+        MAXF: mmio.Mmio(packed struct(u32) {
+            ///  MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field.
+            MAXFLEN: u16,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        ///  PHY Support register.
+        SUPP: mmio.Mmio(packed struct(u32) {
+            ///  Unused
+            RESERVED: u8,
+            ///  This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.
+            SPEED: u1,
+            ///  Unused
+            RESERVED: u23,
+        }),
+        ///  Test register.
+        TEST: mmio.Mmio(packed struct(u32) {
+            ///  SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time.
+            SCPQ: u1,
+            ///  This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received.
+            TESTPAUSE: u1,
+            ///  TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure.
+            TESTBP: u1,
+            ///  Unused
+            RESERVED: u29,
+        }),
+        ///  MII Mgmt Configuration register.
+        MCFG: mmio.Mmio(packed struct(u32) {
+            ///  SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY.
+            SCANINC: u1,
+            ///  SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble.
+            SUPPPREAMBLE: u1,
+            ///  CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field.
+            CLOCKSEL: u4,
+            ///  Unused
+            RESERVED: u9,
+            ///  RESET MII MGMT. This bit resets the MII Management hardware.
+            RESETMIIMGMT: u1,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        ///  MII Mgmt Command register.
+        MCMD: mmio.Mmio(packed struct(u32) {
+            ///  This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data).
+            READ: u1,
+            ///  This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example.
+            SCAN: u1,
+            ///  Unused
+            RESERVED: u30,
+        }),
+        ///  MII Mgmt Address register.
+        MADR: mmio.Mmio(packed struct(u32) {
+            ///  REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed.
+            REGADDR: u5,
+            ///  Unused
+            RESERVED: u3,
+            ///  PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved).
+            PHYADDR: u5,
+            ///  Unused
+            RESERVED: u19,
+        }),
+        ///  MII Mgmt Write Data register.
+        MWTD: mmio.Mmio(packed struct(u32) {
+            ///  WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR).
+            WRITEDATA: u16,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        ///  MII Mgmt Read Data register.
+        MRDD: mmio.Mmio(packed struct(u32) {
+            ///  READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location.
+            READDATA: u16,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        ///  MII Mgmt Indicators register.
+        MIND: mmio.Mmio(packed struct(u32) {
+            ///  When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle.
+            BUSY: u1,
+            ///  When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress.
+            SCANNING: u1,
+            ///  When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid.
+            NOTVALID: u1,
+            ///  When 1 is returned - indicates that an MII Mgmt link fail has occurred.
+            MIILINKFAIL: u1,
+            ///  Unused
+            RESERVED: u28,
+        }),
+        reserved64: [8]u8,
+        ///  Station Address 0 register.
+        SA0: mmio.Mmio(packed struct(u32) {
+            ///  STATION ADDRESS, 2nd octet. This field holds the second octet of the station address.
+            SADDR2: u8,
+            ///  STATION ADDRESS, 1st octet. This field holds the first octet of the station address.
+            SADDR1: u8,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        ///  Station Address 1 register.
+        SA1: mmio.Mmio(packed struct(u32) {
+            ///  STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address.
+            SADDR4: u8,
+            ///  STATION ADDRESS, 3rd octet. This field holds the third octet of the station address.
+            SADDR3: u8,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        ///  Station Address 2 register.
+        SA2: mmio.Mmio(packed struct(u32) {
+            ///  STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address.
+            SADDR6: u8,
+            ///  STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address.
+            SADDR5: u8,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        reserved256: [180]u8,
+        ///  Command register.
+        COMMAND: mmio.Mmio(packed struct(u32) {
+            ///  Enable receive.
+            RXENABLE: u1,
+            ///  Enable transmit.
+            TXENABLE: u1,
+            ///  Unused
+            RESERVED: u1,
+            ///  When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately.
+            REGRESET: u1,
+            ///  When a 1 is written, the transmit datapath is reset.
+            TXRESET: u1,
+            ///  When a 1 is written, the receive datapath is reset.
+            RXRESET: u1,
+            ///  When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out.
+            PASSRUNTFRAME: u1,
+            ///  When set to 1 , disables receive filtering i.e. all frames received are written to memory.
+            PASSRXFILTER: u1,
+            ///  Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex.
+            TXFLOWCONTROL: u1,
+            ///  When set to 1 , RMII mode is selected; if 0, MII mode is selected.
+            RMII: u1,
+            ///  When set to 1 , indicates full duplex operation.
+            FULLDUPLEX: u1,
+            ///  Unused
+            RESERVED: u21,
+        }),
+        ///  Status register.
+        STATUS: mmio.Mmio(packed struct(u32) {
+            ///  If 1, the receive channel is active. If 0, the receive channel is inactive.
+            RXSTATUS: u1,
+            ///  If 1, the transmit channel is active. If 0, the transmit channel is inactive.
+            TXSTATUS: u1,
+            ///  Unused
+            RESERVED: u30,
+        }),
+        ///  Receive descriptor base address register.
+        RXDESCRIPTOR: mmio.Mmio(packed struct(u32) {
+            ///  Fixed to 00
+            RESERVED: u2,
+            ///  MSBs of receive descriptor base address.
+            RXDESCRIPTOR: u30,
+        }),
+        ///  Receive status base address register.
+        RXSTATUS: mmio.Mmio(packed struct(u32) {
+            ///  Fixed to 000
+            RESERVED: u3,
+            ///  MSBs of receive status base address.
+            RXSTATUS: u29,
+        }),
+        ///  Receive number of descriptors register.
+        RXDESCRIPTORNUMBER: mmio.Mmio(packed struct(u32) {
+            ///  RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded.
+            RXDESCRIPTORN: u16,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        ///  Receive produce index register.
+        RXPRODUCEINDEX: mmio.Mmio(packed struct(u32) {
+            ///  Index of the descriptor that is going to be filled next by the receive datapath.
+            RXPRODUCEIX: u16,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        ///  Receive consume index register.
+        RXCONSUMEINDEX: mmio.Mmio(packed struct(u32) {
+            ///  Index of the descriptor that is going to be processed next by the receive
+            RXCONSUMEIX: u16,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        ///  Transmit descriptor base address register.
+        TXDESCRIPTOR: mmio.Mmio(packed struct(u32) {
+            ///  Fixed to 00
+            RESERVED: u2,
+            ///  TxDescriptor. MSBs of transmit descriptor base address.
+            TXD: u30,
+        }),
+        ///  Transmit status base address register.
+        TXSTATUS: mmio.Mmio(packed struct(u32) {
+            ///  Fixed to 00
+            RESERVED: u2,
+            ///  TxStatus. MSBs of transmit status base address.
+            TXSTAT: u30,
+        }),
+        ///  Transmit number of descriptors register.
+        TXDESCRIPTORNUMBER: mmio.Mmio(packed struct(u32) {
+            ///  TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded.
+            TXDN: u16,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        ///  Transmit produce index register.
+        TXPRODUCEINDEX: mmio.Mmio(packed struct(u32) {
+            ///  TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver.
+            TXPI: u16,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        ///  Transmit consume index register.
+        TXCONSUMEINDEX: mmio.Mmio(packed struct(u32) {
+            ///  TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath.
+            TXCI: u16,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        reserved344: [40]u8,
+        ///  Transmit status vector 0 register.
+        TSV0: mmio.Mmio(packed struct(u32) {
+            ///  CRC error. The attached CRC in the packet did not match the internally generated CRC.
+            CRCERR: u1,
+            ///  Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field.
+            LCE: u1,
+            ///  Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.
+            LOR: u1,
+            ///  Transmission of packet was completed.
+            DONE: u1,
+            ///  Packet's destination was a multicast address.
+            MULTICAST: u1,
+            ///  Packet's destination was a broadcast address.
+            BROADCAST: u1,
+            ///  Packet was deferred for at least one attempt, but less than an excessive defer.
+            PACKETDEFER: u1,
+            ///  Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode.
+            EXDF: u1,
+            ///  Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions.
+            EXCOL: u1,
+            ///  Late Collision. Collision occurred beyond collision window, 512 bit times.
+            LCOL: u1,
+            ///  Byte count in frame was greater than can be represented in the transmit byte count field in TSV1.
+            GIANT: u1,
+            ///  Host side caused buffer underrun.
+            UNDERRUN: u1,
+            ///  The total number of bytes transferred including collided attempts.
+            TOTALBYTES: u16,
+            ///  The frame was a control frame.
+            CONTROLFRAME: u1,
+            ///  The frame was a control frame with a valid PAUSE opcode.
+            PAUSE: u1,
+            ///  Carrier-sense method backpressure was previously applied.
+            BACKPRESSURE: u1,
+            ///  Frame's length/type field contained 0x8100 which is the VLAN protocol identifier.
+            VLAN: u1,
+        }),
+        ///  Transmit status vector 1 register.
+        TSV1: mmio.Mmio(packed struct(u32) {
+            ///  Transmit byte count. The total number of bytes in the frame, not counting the collided bytes.
+            TBC: u16,
+            ///  Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented.
+            TCC: u4,
+            ///  Unused
+            RESERVED: u12,
+        }),
+        ///  Receive status vector register.
+        RSV: mmio.Mmio(packed struct(u32) {
+            ///  Received byte count. Indicates length of received frame.
+            RBC: u16,
+            ///  Packet previously ignored. Indicates that a packet was dropped.
+            PPI: u1,
+            ///  RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet.
+            RXDVSEEN: u1,
+            ///  Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected.
+            CESEEN: u1,
+            ///  Receive code violation. Indicates that received PHY data does not represent a valid receive code.
+            RCV: u1,
+            ///  CRC error. The attached CRC in the packet did not match the internally generated CRC.
+            CRCERR: u1,
+            ///  Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field.
+            LCERR: u1,
+            ///  Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.
+            LOR: u1,
+            ///  Receive OK. The packet had valid CRC and no symbol errors.
+            ROK: u1,
+            ///  The packet destination was a multicast address.
+            MULTICAST: u1,
+            ///  The packet destination was a broadcast address.
+            BROADCAST: u1,
+            ///  Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out.
+            DRIBBLENIBBLE: u1,
+            ///  The frame was a control frame.
+            CONTROLFRAME: u1,
+            ///  The frame was a control frame with a valid PAUSE opcode.
+            PAUSE: u1,
+            ///  Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode.
+            UO: u1,
+            ///  Frame's length/type field contained 0x8100 which is the VLAN protocol identifier.
+            VLAN: u1,
+            ///  Unused
+            RESERVED: u1,
+        }),
+        reserved368: [12]u8,
+        ///  Flow control counter register.
+        FLOWCONTROLCOUNTER: mmio.Mmio(packed struct(u32) {
+            ///  MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame.
+            MC: u16,
+            ///  PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles.
+            PT: u16,
+        }),
+        ///  Flow control status register.
+        FLOWCONTROLSTATUS: mmio.Mmio(packed struct(u32) {
+            ///  MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register.
+            MCC: u16,
+            ///  Unused
+            RESERVED: u16,
+        }),
+        reserved512: [136]u8,
+        ///  Receive filter control register.
+        RXFILTERCTRL: mmio.Mmio(packed struct(u32) {
+            ///  AcceptUnicastEn. When set to 1, all unicast frames are accepted.
+            AUE: u1,
+            ///  AcceptBroadcastEn. When set to 1, all broadcast frames are accepted.
+            ABE: u1,
+            ///  AcceptMulticastEn. When set to 1, all multicast frames are accepted.
+            AME: u1,
+            ///  AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted.
+            AUHE: u1,
+            ///  AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted.
+            AMHE: u1,
+            ///  AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted.
+            APE: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u6,
+            ///  MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match.
+            MPEW: u1,
+            ///  RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match.
+            RFEW: u1,
+            ///  Unused
+            RESERVED: u18,
+        }),
+        ///  Receive filter WoL status register.
+        RXFILTERWOLSTATUS: mmio.Mmio(packed struct(u32) {
+            ///  AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL.
+            AUW: u1,
+            ///  AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL.
+            ABW: u1,
+            ///  AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL.
+            AMW: u1,
+            ///  AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL.
+            AUHW: u1,
+            ///  AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL.
+            AMHW: u1,
+            ///  AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL.
+            APW: u1,
+            ///  Unused
+            RESERVED: u1,
+            ///  RxFilterWoL. When the value is 1, the receive filter caused WoL.
+            RFW: u1,
+            ///  MagicPacketWoL. When the value is 1, the magic packet filter caused WoL.
+            MPW: u1,
+            ///  Unused
+            RESERVED: u23,
+        }),
+        ///  Receive filter WoL clear register.
+        RXFILTERWOLCLEAR: mmio.Mmio(packed struct(u32) {
+            ///  AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
+            AUWCLR: u1,
+            ///  AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
+            ABWCLR: u1,
+            ///  AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
+            AMWCLR: u1,
+            ///  AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
+            AUHWCLR: u1,
+            ///  AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
+            AMHWCLR: u1,
+            ///  AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
+            APWCLR: u1,
+            ///  Unused
+            RESERVED: u1,
+            ///  RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
+            RFWCLR: u1,
+            ///  MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
+            MPWCLR: u1,
+            ///  Unused
+            RESERVED: u23,
+        }),
+        reserved528: [4]u8,
+        ///  Hash filter table LSBs register.
+        HASHFILTERL: mmio.Mmio(packed struct(u32) {
+            ///  HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering.
+            HFL: u32,
+        }),
+        ///  Hash filter table MSBs register.
+        HASHFILTERH: mmio.Mmio(packed struct(u32) {
+            ///  Bits 63:32 of the imperfect filter hash table for receive filtering.
+            HFH: u32,
+        }),
+        reserved4064: [3528]u8,
+        ///  Interrupt status register.
+        INTSTATUS: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error.
+            RXOVERRUNINT: u1,
+            ///  Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun.
+            RXERRORINT: u1,
+            ///  Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.
+            RXFINISHEDINT: u1,
+            ///  Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set.
+            RXDONEINT: u1,
+            ///  Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error.
+            TXUNDERRUNINT: u1,
+            ///  Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun.
+            TXERRORINT: u1,
+            ///  Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.
+            TXFINISHEDINT: u1,
+            ///  Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set.
+            TXDONEINT: u1,
+            ///  Unused
+            RESERVED: u4,
+            ///  Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register.
+            SOFTINT: u1,
+            ///  Interrupt triggered by a Wake-up event detected by the receive filter.
+            WAKEUPINT: u1,
+            ///  Unused
+            RESERVED: u18,
+        }),
+        ///  Interrupt enable register.
+        INTENABLE: mmio.Mmio(packed struct(u32) {
+            ///  Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations.
+            RXOVERRUNINTEN: u1,
+            ///  Enable for interrupt trigger on receive errors.
+            RXERRORINTEN: u1,
+            ///  Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.
+            RXFINISHEDINTEN: u1,
+            ///  Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set.
+            RXDONEINTEN: u1,
+            ///  Enable for interrupt trigger on transmit buffer or descriptor underrun situations.
+            TXUNDERRUNINTEN: u1,
+            ///  Enable for interrupt trigger on transmit errors.
+            TXERRORINTEN: u1,
+            ///  Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.
+            TXFINISHEDINTEN: u1,
+            ///  Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set.
+            TXDONEINTEN: u1,
+            ///  Unused
+            RESERVED: u4,
+            ///  Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register.
+            SOFTINTEN: u1,
+            ///  Enable for interrupt triggered by a Wake-up event detected by the receive filter.
+            WAKEUPINTEN: u1,
+            ///  Unused
+            RESERVED: u18,
+        }),
+        ///  Interrupt clear register.
+        INTCLEAR: mmio.Mmio(packed struct(u32) {
+            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
+            RXOVERRUNINTCLR: u1,
+            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
+            RXERRORINTCLR: u1,
+            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
+            RXFINISHEDINTCLR: u1,
+            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
+            RXDONEINTCLR: u1,
+            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
+            TXUNDERRUNINTCLR: u1,
+            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
+            TXERRORINTCLR: u1,
+            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
+            TXFINISHEDINTCLR: u1,
+            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
+            TXDONEINTCLR: u1,
+            ///  Unused
+            RESERVED: u4,
+            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
+            SOFTINTCLR: u1,
+            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
+            WAKEUPINTCLR: u1,
+            ///  Unused
+            RESERVED: u18,
+        }),
+        ///  Interrupt set register.
+        INTSET: mmio.Mmio(packed struct(u32) {
+            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
+            RXOVERRUNINTSET: u1,
+            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
+            RXERRORINTSET: u1,
+            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
+            RXFINISHEDINTSET: u1,
+            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
+            RXDONEINTSET: u1,
+            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
+            TXUNDERRUNINTSET: u1,
+            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
+            TXERRORINTSET: u1,
+            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
+            TXFINISHEDINTSET: u1,
+            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
+            TXDONEINTSET: u1,
+            ///  Unused
+            RESERVED: u4,
+            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
+            SOFTINTSET: u1,
+            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
+            WAKEUPINTSET: u1,
+            ///  Unused
+            RESERVED: u18,
+        }),
+        reserved4084: [4]u8,
+        ///  Power-down register.
+        POWERDOWN: mmio.Mmio(packed struct(u32) {
+            ///  Unused
+            RESERVED: u31,
+            ///  PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register.
+            PD: u1,
+        }),
+    };
+
+    ///  Digital-to-Analog Converter (DAC)
+    pub const DAC = extern struct {
+        ///  D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit.
+        CR: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u6,
+            ///  After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN.
+            VALUE: u10,
+            ///  Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.
+            BIAS: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.
+                    FAST = 0x0,
+                    ///  The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.
+                    SLOW = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u15,
+        }),
+        ///  DAC Control register. This register controls DMA and timer operation.
+        CTRL: mmio.Mmio(packed struct(u32) {
+            ///  DMA interrupt request
+            INT_DMA_REQ: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Clear on any write to the DACR register.
+                    CLEAR_ON_ANY_WRITE_T = 0x0,
+                    ///  Set by hardware when the timer times out.
+                    SET_BY_HARDWARE_WHEN = 0x1,
+                },
+            },
+            ///  Double buffering
+            DBLBUF_ENA: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable
+                    DISABLE = 0x0,
+                    ///  Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter.
+                    ENABLE_WHEN_THIS_BI = 0x1,
+                },
+            },
+            ///  Time-out counter operation
+            CNT_ENA: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable
+                    DISABLE = 0x0,
+                    ///  Enable
+                    ENABLE = 0x1,
+                },
+            },
+            ///  DMA access
+            DMA_ENA: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disable
+                    DISABLE = 0x0,
+                    ///  Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672).
+                    ENABLE_DMA_BURST_RE = 0x1,
+                },
+            },
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u28,
+        }),
+        ///  DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer.
+        CNTVAL: mmio.Mmio(packed struct(u32) {
+            ///  16-bit reload value for the DAC interrupt/DMA timer.
+            VALUE: u16,
+            ///  Reserved
+            RESERVED: u16,
+        }),
+    };
+
+    ///  System and clock control
+    pub const SYSCON = extern struct {
+        ///  Flash Accelerator Configuration Register. Controls flash access timing.
+        FLASHCFG: mmio.Mmio(packed struct(u32) {
+            ///  Reserved, user software should not change these bits from the reset value.
+            RESERVED: u12,
+            ///  Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved.
+            FLASHTIM: packed union {
+                raw: u4,
+                value: enum(u4) {
+                    ///  Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock.
+                    @"1CLK" = 0x0,
+                    ///  Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock.
+                    @"2CLK" = 0x1,
+                    ///  Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock.
+                    @"3CLK" = 0x2,
+                    ///  Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock.
+                    @"4CLK" = 0x3,
+                    ///  Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only.
+                    @"5CLK" = 0x4,
+                    ///  Flash accesses use 6 CPU clocks. This safe setting will work under any conditions.
+                    @"6CLK" = 0x5,
+                    _,
+                },
+            },
+            ///  Reserved. The value read from a reserved bit is not defined.
+            RESERVED: u16,
+        }),
+        reserved128: [124]u8,
+        ///  PLL0 Control Register
+        PLL0CON: mmio.Mmio(packed struct(u32) {
+            ///  PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register.
+            PLLE0: u1,
+            ///  PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register.
+            PLLC0: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u30,
+        }),
+        ///  PLL0 Configuration Register
+        PLL0CFG: mmio.Mmio(packed struct(u32) {
+            ///  PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware.
+            MSEL0: u15,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u1,
+            ///  PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32.
+            NSEL0: u8,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u8,
+        }),
+        ///  PLL0 Status Register
+        PLL0STAT: mmio.Mmio(packed struct(u32) {
+            ///  Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier.
+            MSEL0: u15,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u1,
+            ///  Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider.
+            NSEL0: u8,
+            ///  Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered.
+            PLLE0_STAT: u1,
+            ///  Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered.
+            PLLC0_STAT: u1,
+            ///  Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details.
+            PLOCK0: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u5,
+        }),
+        ///  PLL0 Feed Register
+        PLL0FEED: mmio.Mmio(packed struct(u32) {
+            ///  The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect.
+            PLL0FEED: u8,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        reserved160: [16]u8,
+        ///  PLL1 Control Register
+        PLL1CON: mmio.Mmio(packed struct(u32) {
+            ///  PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency.
+            PLLE1: u1,
+            ///  PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register.
+            PLLC1: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u30,
+        }),
+        ///  PLL1 Configuration Register
+        PLL1CFG: mmio.Mmio(packed struct(u32) {
+            ///  PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations.
+            MSEL1: u5,
+            ///  PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations.
+            PSEL1: u2,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u25,
+        }),
+        ///  PLL1 Status Register
+        PLL1STAT: mmio.Mmio(packed struct(u32) {
+            ///  Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1.
+            MSEL1: u5,
+            ///  Read-back for the PLL1 Divider value. This is the value currently used by PLL1.
+            PSEL1: u2,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u1,
+            ///  Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated.
+            PLLE1_STAT: u1,
+            ///  Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated.
+            PLLC1_STAT: u1,
+            ///  Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency.
+            PLOCK1: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u21,
+        }),
+        ///  PLL1 Feed Register
+        PLL1FEED: mmio.Mmio(packed struct(u32) {
+            ///  The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect.
+            PLL1FEED: u8,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        reserved192: [16]u8,
+        ///  Power Control Register
+        PCON: mmio.Mmio(packed struct(u32) {
+            ///  Power mode control bit 0. This bit controls entry to the Power-down mode.
+            PM0: u1,
+            ///  Power mode control bit 1. This bit controls entry to the Deep Power-down mode.
+            PM1: u1,
+            ///  Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection.
+            BODRPM: u1,
+            ///  Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit.
+            BOGD: u1,
+            ///  Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled.
+            BORD: u1,
+            reserved8: u3,
+            ///  Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit.
+            SMFLAG: u1,
+            ///  Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit.
+            DSFLAG: u1,
+            ///  Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit.
+            PDFLAG: u1,
+            ///  Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit.
+            DPDFLAG: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u20,
+        }),
+        ///  Power Control for Peripherals Register
+        PCONP: mmio.Mmio(packed struct(u32) {
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Timer/Counter 0 power/clock control bit.
+            PCTIM0: u1,
+            ///  Timer/Counter 1 power/clock control bit.
+            PCTIM1: u1,
+            ///  UART0 power/clock control bit.
+            PCUART0: u1,
+            ///  UART1 power/clock control bit.
+            PCUART1: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            ///  PWM1 power/clock control bit.
+            PCPWM1: u1,
+            ///  The I2C0 interface power/clock control bit.
+            PCI2C0: u1,
+            ///  The SPI interface power/clock control bit.
+            PCSPI: u1,
+            ///  The RTC power/clock control bit.
+            PCRTC: u1,
+            ///  The SSP 1 interface power/clock control bit.
+            PCSSP1: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            ///  A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN.
+            PCADC: u1,
+            ///  CAN Controller 1 power/clock control bit.
+            PCCAN1: u1,
+            ///  CAN Controller 2 power/clock control bit.
+            PCCAN2: u1,
+            ///  Power/clock control bit for IOCON, GPIO, and GPIO interrupts.
+            PCGPIO: u1,
+            ///  Repetitive Interrupt Timer power/clock control bit.
+            PCRIT: u1,
+            ///  Motor Control PWM
+            PCMCPWM: u1,
+            ///  Quadrature Encoder Interface power/clock control bit.
+            PCQEI: u1,
+            ///  The I2C1 interface power/clock control bit.
+            PCI2C1: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            ///  The SSP0 interface power/clock control bit.
+            PCSSP0: u1,
+            ///  Timer 2 power/clock control bit.
+            PCTIM2: u1,
+            ///  Timer 3 power/clock control bit.
+            PCTIM3: u1,
+            ///  UART 2 power/clock control bit.
+            PCUART2: u1,
+            ///  UART 3 power/clock control bit.
+            PCUART3: u1,
+            ///  I2C interface 2 power/clock control bit.
+            PCI2C2: u1,
+            ///  I2S interface power/clock control bit.
+            PCI2S: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            ///  GPDMA function power/clock control bit.
+            PCGPDMA: u1,
+            ///  Ethernet block power/clock control bit.
+            PCENET: u1,
+            ///  USB interface power/clock control bit.
+            PCUSB: u1,
+        }),
+        reserved260: [60]u8,
+        ///  CPU Clock Configuration Register
+        CCLKCFG: mmio.Mmio(packed struct(u32) {
+            ///  Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock.
+            CCLKSEL: u8,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u24,
+        }),
+        ///  USB Clock Configuration Register
+        USBCLKCFG: mmio.Mmio(packed struct(u32) {
+            ///  Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz.
+            USBSEL: u4,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        ///  Clock Source Select Register
+        CLKSRCSEL: mmio.Mmio(packed struct(u32) {
+            ///  Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device.
+            CLKSRC: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Selects the Internal RC oscillator as the PLL0 clock source (default).
+                    SELECTS_THE_INTERNAL = 0x0,
+                    ///  Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s.
+                    SELECTS_THE_MAIN_OSC = 0x1,
+                    ///  Selects the RTC oscillator as the PLL0 clock source.
+                    SELECTS_THE_RTC_OSCI = 0x2,
+                    ///  Reserved, do not use this setting.
+                    RESERVED = 0x3,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u30,
+        }),
+        ///  Allows clearing the current CAN channel sleep state as well as reading that state.
+        CANSLEEPCLR: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1.
+            CAN1SLEEP: u1,
+            ///  Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2.
+            CAN2SLEEP: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u29,
+        }),
+        ///  Allows reading the wake-up state of the CAN channels.
+        CANWAKEFLAGS: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit.
+            CAN1WAKE: u1,
+            ///  Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit.
+            CAN2WAKE: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u29,
+        }),
+        reserved320: [40]u8,
+        ///  External Interrupt Flag Register
+        EXTINT: mmio.Mmio(packed struct(u32) {
+            ///  In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.
+            EINT0: u1,
+            ///  In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.
+            EINT1: u1,
+            ///  In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.
+            EINT2: u1,
+            ///  In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.
+            EINT3: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        reserved328: [4]u8,
+        ///  External Interrupt Mode register
+        EXTMODE: mmio.Mmio(packed struct(u32) {
+            ///  External interrupt 0 EINT0 mode.
+            EXTMODE0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Level-sensitive. Level-sensitivity is selected for EINT0.
+                    LEVEL_SENSITIVE = 0x0,
+                    ///  Edge-sensitive. EINT0 is edge sensitive.
+                    EDGE_SENSITIVE = 0x1,
+                },
+            },
+            ///  External interrupt 1 EINT1 mode.
+            EXTMODE1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Level-sensitive. Level-sensitivity is selected for EINT1.
+                    LEVEL_SENSITIVE = 0x0,
+                    ///  Edge-sensitive. EINT1 is edge sensitive.
+                    EDGE_SENSITIVE = 0x1,
+                },
+            },
+            ///  External interrupt 2 EINT2 mode.
+            EXTMODE2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Level-sensitive. Level-sensitivity is selected for EINT2.
+                    LEVEL_SENSITIVE = 0x0,
+                    ///  Edge-sensitive. EINT2 is edge sensitive.
+                    EDGE_SENSITIVE = 0x1,
+                },
+            },
+            ///  External interrupt 3 EINT3 mode.
+            EXTMODE3: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Level-sensitive. Level-sensitivity is selected for EINT3.
+                    LEVEL_SENSITIVE = 0x0,
+                    ///  Edge-sensitive. EINT3 is edge sensitive.
+                    EDGE_SENSITIVE = 0x1,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        ///  External Interrupt Polarity Register
+        EXTPOLAR: mmio.Mmio(packed struct(u32) {
+            ///  External interrupt 0 EINT0 polarity.
+            EXTPOLAR0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0).
+                    FALLING_EDGE = 0x0,
+                    ///  Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0).
+                    RISING_EDGE = 0x1,
+                },
+            },
+            ///  External interrupt 1 EINT1 polarity.
+            EXTPOLAR1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1).
+                    FALLING_EDGE = 0x0,
+                    ///  Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1).
+                    RISING_EDGE = 0x1,
+                },
+            },
+            ///  External interrupt 2 EINT2 polarity.
+            EXTPOLAR2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2).
+                    FALLING_EDGE = 0x0,
+                    ///  Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2).
+                    RISING_EDGE = 0x1,
+                },
+            },
+            ///  External interrupt 3 EINT3 polarity.
+            EXTPOLAR3: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3).
+                    FALLING_EDGE = 0x0,
+                    ///  Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3).
+                    RISING_EDGE = 0x1,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        reserved384: [48]u8,
+        ///  Reset Source Identification Register
+        RSID: mmio.Mmio(packed struct(u32) {
+            ///  Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset.
+            POR: u1,
+            ///  Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR.
+            EXTR: u1,
+            ///  This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR.
+            WDTR: u1,
+            ///  This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not.
+            BODR: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        reserved416: [28]u8,
+        ///  System control and status
+        SCS: mmio.Mmio(packed struct(u32) {
+            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u4,
+            ///  Main oscillator range select.
+            OSCRANGE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Low. The frequency range of the main oscillator is 1 MHz to 20 MHz.
+                    LOW = 0x0,
+                    ///  High. The frequency range of the main oscillator is 15 MHz to 25 MHz.
+                    HIGH = 0x1,
+                },
+            },
+            ///  Main oscillator enable.
+            OSCEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Disabled. The main oscillator is disabled.
+                    DISABLED = 0x0,
+                    ///  Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins.
+                    ENABLED = 0x1,
+                },
+            },
+            ///  Main oscillator status.
+            OSCSTAT: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Not ready. The main oscillator is not ready to be used as a clock source.
+                    NOT_READY = 0x0,
+                    ///  Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit.
+                    READY = 0x1,
+                },
+            },
+            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u25,
+        }),
+        reserved424: [4]u8,
+        ///  Peripheral Clock Selection register 0.
+        PCLKSEL0: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral clock selection for WDT.
+            PCLK_WDT: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for TIMER0.
+            PCLK_TIMER0: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for TIMER1.
+            PCLK_TIMER1: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for UART0.
+            PCLK_UART0: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for UART1.
+            PCLK_UART1: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u2,
+            ///  Peripheral clock selection for PWM1.
+            PCLK_PWM1: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for I2C0.
+            PCLK_I2C0: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for SPI.
+            PCLK_SPI: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u2,
+            ///  Peripheral clock selection for SSP1.
+            PCLK_SSP1: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for DAC.
+            PCLK_DAC: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for ADC.
+            PCLK_ADC: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.
+            PCLK_CAN1: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 6. PCLK_peripheral = CCLK/6.
+                    CCLK_DIV_6 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.
+            PCLK_CAN2: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 6. PCLK_peripheral = CCLK/6,
+                    CCLK_DIV_6 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.
+            PCLK_ACF: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 6. PCLK_peripheral = CCLK/6
+                    CCLK_DIV_6 = 0x3,
+                },
+            },
+        }),
+        ///  Peripheral Clock Selection register 1.
+        PCLKSEL1: mmio.Mmio(packed struct(u32) {
+            ///  Peripheral clock selection for the Quadrature Encoder Interface.
+            PCLK_QEI: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for GPIO interrupts.
+            PCLK_GPIOINT: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for the Pin Connect block.
+            PCLK_PCB: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for I2C1.
+            PCLK_I2C1: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u2,
+            ///  Peripheral clock selection for SSP0.
+            PCLK_SSP0: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for TIMER2.
+            PCLK_TIMER2: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for TIMER3.
+            PCLK_TIMER3: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for UART2.
+            PCLK_UART2: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for UART3.
+            PCLK_UART3: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for I2C2.
+            PCLK_I2C2: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for I2S.
+            PCLK_I2S: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u2,
+            ///  Peripheral clock selection for Repetitive Interrupt Timer.
+            PCLK_RIT: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for the System Control block.
+            PCLK_SYSCON: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+            ///  Peripheral clock selection for the Motor Control PWM.
+            PCLK_MC: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
+                    CCLK_DIV_4 = 0x0,
+                    ///  CCLK. PCLK_peripheral = CCLK
+                    CCLK = 0x1,
+                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
+                    CCLK_DIV_2 = 0x2,
+                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
+                    CCLK_DIV_8 = 0x3,
+                },
+            },
+        }),
+        reserved448: [16]u8,
+        ///  USB Interrupt Status
+        USBINTST: mmio.Mmio(packed struct(u32) {
+            ///  Low priority interrupt line status. This bit is read-only.
+            USB_INT_REQ_LP: u1,
+            ///  High priority interrupt line status. This bit is read-only.
+            USB_INT_REQ_HP: u1,
+            ///  DMA interrupt line status. This bit is read-only.
+            USB_INT_REQ_DMA: u1,
+            ///  USB host interrupt line status. This bit is read-only.
+            USB_HOST_INT: u1,
+            ///  External ATX interrupt line status. This bit is read-only.
+            USB_ATX_INT: u1,
+            ///  OTG interrupt line status. This bit is read-only.
+            USB_OTG_INT: u1,
+            ///  I2C module interrupt line status. This bit is read-only.
+            USB_I2C_INT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u1,
+            ///  USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only.
+            USB_NEED_CLK: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u22,
+            ///  Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines.
+            EN_USB_INTS: u1,
+        }),
+        ///  Selects between alternative requests on DMA channels 0 through 7 and 10 through 15
+        DMACREQSEL: mmio.Mmio(packed struct(u32) {
+            ///  Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected.
+            DMASEL08: u1,
+            ///  Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected.
+            DMASEL09: u1,
+            ///  Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected.
+            DMASEL10: u1,
+            ///  Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected.
+            DMASEL11: u1,
+            ///  Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected.
+            DMASEL12: u1,
+            ///  Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected.
+            DMASEL13: u1,
+            ///  Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected.
+            DMASEL14: u1,
+            ///  Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected.
+            DMASEL15: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u24,
+        }),
+        ///  Clock Output Configuration Register
+        CLKOUTCFG: mmio.Mmio(packed struct(u32) {
+            ///  Selects the clock source for the CLKOUT function. Other values are reserved. Do not use.
+            CLKOUTSEL: packed union {
+                raw: u4,
+                value: enum(u4) {
+                    ///  Selects the CPU clock as the CLKOUT source.
+                    SELECTS_THE_CPU_CLOC = 0x0,
+                    ///  Selects the main oscillator as the CLKOUT source.
+                    SELECTS_THE_MAIN_OSC = 0x1,
+                    ///  Selects the Internal RC oscillator as the CLKOUT source.
+                    SELECTS_THE_INTERNAL = 0x2,
+                    ///  Selects the USB clock as the CLKOUT source.
+                    SELECTS_THE_USB_CLOC = 0x3,
+                    ///  Selects the RTC oscillator as the CLKOUT source.
+                    SELECTS_THE_RTC_OSCI = 0x4,
+                    _,
+                },
+            },
+            ///  Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16.
+            CLKOUTDIV: u4,
+            ///  CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT.
+            CLKOUT_EN: u1,
+            ///  CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped.
+            CLKOUT_ACT: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u22,
+        }),
+    };
+
+    ///  Quadrature Encoder Interface (QEI)
+    pub const QEI = extern struct {
+        ///  Control register
+        CON: mmio.Mmio(packed struct(u32) {
+            ///  Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared.
+            RESP: u1,
+            ///  Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared.
+            RESPI: u1,
+            ///  Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared.
+            RESV: u1,
+            ///  Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared.
+            RESI: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u28,
+        }),
+        ///  Status register
+        STAT: mmio.Mmio(packed struct(u32) {
+            ///  Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597.
+            DIR: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u31,
+        }),
+        ///  Configuration register
+        CONF: mmio.Mmio(packed struct(u32) {
+            ///  Direction invert. When 1, complements the DIR bit.
+            DIRINV: u1,
+            ///  Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal.
+            SIGMODE: u1,
+            ///  Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range.
+            CAPMODE: u1,
+            ///  Invert Index. When 1, inverts the sense of the index input.
+            INVINX: u1,
+            ///  Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration).
+            CRESPI: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u11,
+            ///  Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index.
+            INXGATE: u4,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u12,
+        }),
+        ///  Position register
+        POS: mmio.Mmio(packed struct(u32) {
+            ///  Current position value.
+            POS: u32,
+        }),
+        ///  Maximum position register
+        MAXPOS: mmio.Mmio(packed struct(u32) {
+            ///  Current maximum position value.
+            MAXPOS: u32,
+        }),
+        ///  Position compare register 0
+        CMPOS0: mmio.Mmio(packed struct(u32) {
+            ///  Position compare value 0.
+            PCMP0: u32,
+        }),
+        ///  Position compare register 1
+        CMPOS1: mmio.Mmio(packed struct(u32) {
+            ///  Position compare value 1.
+            PCMP1: u32,
+        }),
+        ///  Position compare register 2
+        CMPOS2: mmio.Mmio(packed struct(u32) {
+            ///  Position compare value 2.
+            PCMP2: u32,
+        }),
+        ///  Index count register 0
+        INXCNT: mmio.Mmio(packed struct(u32) {
+            ///  Current index counter value.
+            ENCPOS: u32,
+        }),
+        ///  Index compare register 0
+        INXCMP0: mmio.Mmio(packed struct(u32) {
+            ///  Index compare value 0.
+            ICMP0: u32,
+        }),
+        ///  Velocity timer reload register
+        LOAD: mmio.Mmio(packed struct(u32) {
+            ///  Current velocity timer load value.
+            VELLOAD: u32,
+        }),
+        ///  Velocity timer register
+        TIME: mmio.Mmio(packed struct(u32) {
+            ///  Current velocity timer value.
+            VELVAL: u32,
+        }),
+        ///  Velocity counter register
+        VEL: mmio.Mmio(packed struct(u32) {
+            ///  Current velocity pulse count.
+            VELPC: u32,
+        }),
+        ///  Velocity capture register
+        CAP: mmio.Mmio(packed struct(u32) {
+            ///  Last velocity capture.
+            VELCAP: u32,
+        }),
+        ///  Velocity compare register
+        VELCOMP: mmio.Mmio(packed struct(u32) {
+            ///  Compare velocity pulse count.
+            VELPC: u32,
+        }),
+        ///  Digital filter register
+        FILTER: mmio.Mmio(packed struct(u32) {
+            ///  Digital filter sampling delay.
+            FILTA: u32,
+        }),
+        reserved4056: [3992]u8,
+        ///  Interrupt enable clear register
+        IEC: mmio.Mmio(packed struct(u32) {
+            ///  Writing a 1 disables the INX_Int interrupt in the QEIIE register.
+            INX_INT: u1,
+            ///  Writing a 1 disables the TIN_Int interrupt in the QEIIE register.
+            TIM_INT: u1,
+            ///  Writing a 1 disables the VELC_Int interrupt in the QEIIE register.
+            VELC_INT: u1,
+            ///  Writing a 1 disables the DIR_Int interrupt in the QEIIE register.
+            DIR_INT: u1,
+            ///  Writing a 1 disables the ERR_Int interrupt in the QEIIE register.
+            ERR_INT: u1,
+            ///  Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register.
+            ENCLK_INT: u1,
+            ///  Writing a 1 disables the POS0_Int interrupt in the QEIIE register.
+            POS0_INT: u1,
+            ///  Writing a 1 disables the POS1_Int interrupt in the QEIIE register.
+            POS1_INT: u1,
+            ///  Writing a 1 disables the POS2_Int interrupt in the QEIIE register.
+            POS2_INT: u1,
+            ///  Writing a 1 disables the REV0_Int interrupt in the QEIIE register.
+            REV0_INT: u1,
+            ///  Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register.
+            POS0REV_INT: u1,
+            ///  Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register.
+            POS1REV_INT: u1,
+            ///  Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register.
+            POS2REV_INT: u1,
+            ///  Writing a 1 disables the REV1_Int interrupt in the QEIIE register.
+            REV1_INT: u1,
+            ///  Writing a 1 disables the REV2_Int interrupt in the QEIIE register.
+            REV2_INT: u1,
+            ///  Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register.
+            MAXPOS_INT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+        ///  Interrupt enable set register
+        IES: mmio.Mmio(packed struct(u32) {
+            ///  Writing a 1 enables the INX_Int interrupt in the QEIIE register.
+            INX_INT: u1,
+            ///  Writing a 1 enables the TIN_Int interrupt in the QEIIE register.
+            TIM_INT: u1,
+            ///  Writing a 1 enables the VELC_Int interrupt in the QEIIE register.
+            VELC_INT: u1,
+            ///  Writing a 1 enables the DIR_Int interrupt in the QEIIE register.
+            DIR_INT: u1,
+            ///  Writing a 1 enables the ERR_Int interrupt in the QEIIE register.
+            ERR_INT: u1,
+            ///  Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register.
+            ENCLK_INT: u1,
+            ///  Writing a 1 enables the POS0_Int interrupt in the QEIIE register.
+            POS0_INT: u1,
+            ///  Writing a 1 enables the POS1_Int interrupt in the QEIIE register.
+            POS1_INT: u1,
+            ///  Writing a 1 enables the POS2_Int interrupt in the QEIIE register.
+            POS2_INT: u1,
+            ///  Writing a 1 enables the REV0_Int interrupt in the QEIIE register.
+            REV0_INT: u1,
+            ///  Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register.
+            POS0REV_INT: u1,
+            ///  Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register.
+            POS1REV_INT: u1,
+            ///  Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register.
+            POS2REV_INT: u1,
+            ///  Writing a 1 enables the REV1_Int interrupt in the QEIIE register.
+            REV1_INT: u1,
+            ///  Writing a 1 enables the REV2_Int interrupt in the QEIIE register.
+            REV2_INT: u1,
+            ///  Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register.
+            MAXPOS_INT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+        ///  Interrupt status register
+        INTSTAT: mmio.Mmio(packed struct(u32) {
+            ///  Indicates that an index pulse was detected.
+            INX_INT: u1,
+            ///  Indicates that a velocity timer overflow occurred
+            TIM_INT: u1,
+            ///  Indicates that captured velocity is less than compare velocity.
+            VELC_INT: u1,
+            ///  Indicates that a change of direction was detected.
+            DIR_INT: u1,
+            ///  Indicates that an encoder phase error was detected.
+            ERR_INT: u1,
+            ///  Indicates that and encoder clock pulse was detected.
+            ENCLK_INT: u1,
+            ///  Indicates that the position 0 compare value is equal to the current position.
+            POS0_INT: u1,
+            ///  Indicates that the position 1compare value is equal to the current position.
+            POS1_INT: u1,
+            ///  Indicates that the position 2 compare value is equal to the current position.
+            POS2_INT: u1,
+            ///  Indicates that the index compare 0 value is equal to the current index count.
+            REV0_INT: u1,
+            ///  Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set.
+            POS0REV_INT: u1,
+            ///  Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set.
+            POS1REV_INT: u1,
+            ///  Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set.
+            POS2REV_INT: u1,
+            ///  Indicates that the index compare 1value is equal to the current index count.
+            REV1_INT: u1,
+            ///  Indicates that the index compare 2 value is equal to the current index count.
+            REV2_INT: u1,
+            ///  Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction.
+            MAXPOS_INT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+        ///  Interrupt enable register
+        IE: mmio.Mmio(packed struct(u32) {
+            ///  When 1, the INX_Int interrupt is enabled.
+            INX_INT: u1,
+            ///  When 1, the TIN_Int interrupt is enabled.
+            TIM_INT: u1,
+            ///  When 1, the VELC_Int interrupt is enabled.
+            VELC_INT: u1,
+            ///  When 1, the DIR_Int interrupt is enabled.
+            DIR_INT: u1,
+            ///  When 1, the ERR_Int interrupt is enabled.
+            ERR_INT: u1,
+            ///  When 1, the ENCLK_Int interrupt is enabled.
+            ENCLK_INT: u1,
+            ///  When 1, the POS0_Int interrupt is enabled.
+            POS0_INT: u1,
+            ///  When 1, the POS1_Int interrupt is enabled.
+            POS1_INT: u1,
+            ///  When 1, the POS2_Int interrupt is enabled.
+            POS2_INT: u1,
+            ///  When 1, the REV0_Int interrupt is enabled.
+            REV0_INT: u1,
+            ///  When 1, the POS0REV_Int interrupt is enabled.
+            POS0REV_INT: u1,
+            ///  When 1, the POS1REV_Int interrupt is enabled.
+            POS1REV_INT: u1,
+            ///  When 1, the POS2REV_Int interrupt is enabled.
+            POS2REV_INT: u1,
+            ///  When 1, the REV1_Int interrupt is enabled.
+            REV1_INT: u1,
+            ///  When 1, the REV2_Int interrupt is enabled.
+            REV2_INT: u1,
+            ///  When 1, the MAXPOS_Int interrupt is enabled.
+            MAXPOS_INT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+        ///  Interrupt status clear register
+        CLR: mmio.Mmio(packed struct(u32) {
+            ///  Writing a 1 clears the INX_Int bit in QEIINTSTAT.
+            INX_INT: u1,
+            ///  Writing a 1 clears the TIN_Int bit in QEIINTSTAT.
+            TIM_INT: u1,
+            ///  Writing a 1 clears the VELC_Int bit in QEIINTSTAT.
+            VELC_INT: u1,
+            ///  Writing a 1 clears the DIR_Int bit in QEIINTSTAT.
+            DIR_INT: u1,
+            ///  Writing a 1 clears the ERR_Int bit in QEIINTSTAT.
+            ERR_INT: u1,
+            ///  Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT.
+            ENCLK_INT: u1,
+            ///  Writing a 1 clears the POS0_Int bit in QEIINTSTAT.
+            POS0_INT: u1,
+            ///  Writing a 1 clears the POS1_Int bit in QEIINTSTAT.
+            POS1_INT: u1,
+            ///  Writing a 1 clears the POS2_Int bit in QEIINTSTAT.
+            POS2_INT: u1,
+            ///  Writing a 1 clears the REV0_Int bit in QEIINTSTAT.
+            REV0_INT: u1,
+            ///  Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT.
+            POS0REV_INT: u1,
+            ///  Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT.
+            POS1REV_INT: u1,
+            ///  Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT.
+            POS2REV_INT: u1,
+            ///  Writing a 1 clears the REV1_Int bit in QEIINTSTAT.
+            REV1_INT: u1,
+            ///  Writing a 1 clears the REV2_Int bit in QEIINTSTAT.
+            REV2_INT: u1,
+            ///  Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT.
+            MAXPOS_INT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+        ///  Interrupt status set register
+        SET: mmio.Mmio(packed struct(u32) {
+            ///  Writing a 1 sets the INX_Int bit in QEIINTSTAT.
+            INX_INT: u1,
+            ///  Writing a 1 sets the TIN_Int bit in QEIINTSTAT.
+            TIM_INT: u1,
+            ///  Writing a 1 sets the VELC_Int bit in QEIINTSTAT.
+            VELC_INT: u1,
+            ///  Writing a 1 sets the DIR_Int bit in QEIINTSTAT.
+            DIR_INT: u1,
+            ///  Writing a 1 sets the ERR_Int bit in QEIINTSTAT.
+            ERR_INT: u1,
+            ///  Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT.
+            ENCLK_INT: u1,
+            ///  Writing a 1 sets the POS0_Int bit in QEIINTSTAT.
+            POS0_INT: u1,
+            ///  Writing a 1 sets the POS1_Int bit in QEIINTSTAT.
+            POS1_INT: u1,
+            ///  Writing a 1 sets the POS2_Int bit in QEIINTSTAT.
+            POS2_INT: u1,
+            ///  Writing a 1 sets the REV0_Int bit in QEIINTSTAT.
+            REV0_INT: u1,
+            ///  Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT.
+            POS0REV_INT: u1,
+            ///  Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT.
+            POS1REV_INT: u1,
+            ///  Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT.
+            POS2REV_INT: u1,
+            ///  Writing a 1 sets the REV1_Int bit in QEIINTSTAT.
+            REV1_INT: u1,
+            ///  Writing a 1 sets the REV2_Int bit in QEIINTSTAT.
+            REV2_INT: u1,
+            ///  Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT.
+            MAXPOS_INT: u1,
+            ///  Reserved. Read value is undefined, only zero should be written.
+            RESERVED: u16,
+        }),
+    };
+
+    ///  Motor Control PWM
+    pub const MCPWM = extern struct {
+        ///  PWM Control read address
+        CON: mmio.Mmio(packed struct(u32) {
+            ///  Stops/starts timer channel 0.
+            RUN0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Stop.
+                    STOP_ = 0x0,
+                    ///  Run.
+                    RUN_ = 0x1,
+                },
+            },
+            ///  Edge/center aligned operation for channel 0.
+            CENTER0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Edge-aligned.
+                    EDGE_ALIGNED_ = 0x0,
+                    ///  Center-aligned.
+                    CENTER_ALIGNED_ = 0x1,
+                },
+            },
+            ///  Selects polarity of the MCOA0 and MCOB0 pins.
+            POLA0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Passive state is LOW, active state is HIGH.
+                    PASSIVE_STATE_IS_LOW = 0x0,
+                    ///  Passive state is HIGH, active state is LOW.
+                    PASSIVE_STATE_IS_HIG = 0x1,
+                },
+            },
+            ///  Controls the dead-time feature for channel 0.
+            DTE0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Dead-time disabled.
+                    DEAD_TIME_DISABLED_ = 0x0,
+                    ///  Dead-time enabled.
+                    DEAD_TIME_ENABLED_ = 0x1,
+                },
+            },
+            ///  Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).
+            DISUP0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Functional registers are updated from the write registers at the end of each PWM cycle.
+                    UPDATE = 0x0,
+                    ///  Functional registers remain the same as long as the timer is running.
+                    NOUPDATE = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u3,
+            ///  Stops/starts timer channel 1.
+            RUN1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Stop.
+                    STOP_ = 0x0,
+                    ///  Run.
+                    RUN_ = 0x1,
+                },
+            },
+            ///  Edge/center aligned operation for channel 1.
+            CENTER1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Edge-aligned.
+                    EDGE_ALIGNED_ = 0x0,
+                    ///  Center-aligned.
+                    CENTER_ALIGNED_ = 0x1,
+                },
+            },
+            ///  Selects polarity of the MCOA1 and MCOB1 pins.
+            POLA1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Passive state is LOW, active state is HIGH.
+                    PASSIVE_STATE_IS_LOW = 0x0,
+                    ///  Passive state is HIGH, active state is LOW.
+                    PASSIVE_STATE_IS_HIG = 0x1,
+                },
+            },
+            ///  Controls the dead-time feature for channel 1.
+            DTE1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Dead-time disabled.
+                    DEAD_TIME_DISABLED_ = 0x0,
+                    ///  Dead-time enabled.
+                    DEAD_TIME_ENABLED_ = 0x1,
+                },
+            },
+            ///  Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).
+            DISUP1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Functional registers are updated from the write registers at the end of each PWM cycle.
+                    UPDATE = 0x0,
+                    ///  Functional registers remain the same as long as the timer is running.
+                    NOUPDATE = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u3,
+            ///  Stops/starts timer channel 2.
+            RUN2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Stop.
+                    STOP_ = 0x0,
+                    ///  Run.
+                    RUN_ = 0x1,
+                },
+            },
+            ///  Edge/center aligned operation for channel 2.
+            CENTER2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Edge-aligned.
+                    EDGE_ALIGNED_ = 0x0,
+                    ///  Center-aligned.
+                    CENTER_ALIGNED_ = 0x1,
+                },
+            },
+            ///  Selects polarity of the MCOA2 and MCOB2 pins.
+            POLA2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Passive state is LOW, active state is HIGH.
+                    PASSIVE_STATE_IS_LOW = 0x0,
+                    ///  Passive state is HIGH, active state is LOW.
+                    PASSIVE_STATE_IS_HIG = 0x1,
+                },
+            },
+            ///  Controls the dead-time feature for channel 1.
+            DTE2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Dead-time disabled.
+                    DEAD_TIME_DISABLED_ = 0x0,
+                    ///  Dead-time enabled.
+                    DEAD_TIME_ENABLED_ = 0x1,
+                },
+            },
+            ///  Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).
+            DISUP2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Functional registers are updated from the write registers at the end of each PWM cycle.
+                    UPDATE = 0x0,
+                    ///  Functional registers remain the same as long as the timer is running.
+                    NOUPDATE = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u8,
+            ///  Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.
+            INVBDC: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time).
+                    OPPOSITE = 0x0,
+                    ///  The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)
+                    SAME = 0x1,
+                },
+            },
+            ///  3-phase AC mode select (see Section 24.8.7).
+            ACMODE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register.
+                    @"3_PHASE_AC_MODE_OFF" = 0x0,
+                    ///  3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0.
+                    @"3_PHASE_AC_MODE_ON_" = 0x1,
+                },
+            },
+            ///  3-phase DC mode select (see Section 24.8.6).
+            DCMODE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)
+                    @"3_PHASE_DC_MODE_OFF" = 0x0,
+                    ///  3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs.
+                    @"3_PHASE_DC_MODE_ON_" = 0x1,
+                },
+            },
+        }),
+        ///  PWM Control set address
+        CON_SET: mmio.Mmio(packed struct(u32) {
+            ///  Writing a one sets the corresponding bit in the CON register.
+            RUN0_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            CENTER0_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            POLA0_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            DTE0_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            DISUP0_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            RESERVED: u3,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            RUN1_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            CENTER1_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            POLA1_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            DTE1_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            DISUP1_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            RESERVED: u3,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            RUN2_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            CENTER2_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            POLA2_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            DTE2_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            DISUP2_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            RESERVED: u8,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            INVBDC_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            ACMODE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CON register.
+            DCMODE_SET: u1,
+        }),
+        ///  PWM Control clear address
+        CON_CLR: mmio.Mmio(packed struct(u32) {
+            ///  Writing a one clears the corresponding bit in the CON register.
+            RUN0_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            CENTER0_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            POLA0_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            DTE0_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            DISUP0_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            RESERVED: u3,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            RUN1_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            CENTER1_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            POLA1_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            DTE1_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            DISUP1_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            RESERVED: u3,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            RUN2_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            CENTER2_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            POLA2_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            DTE2_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            DISUP2_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            RESERVED: u8,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            INVBDC_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            ACMOD_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CON register.
+            DCMODE_CLR: u1,
+        }),
+        ///  Capture Control read address
+        CAPCON: mmio.Mmio(packed struct(u32) {
+            ///  A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.
+            CAP0MCI0_RE: u1,
+            ///  A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.
+            CAP0MCI0_FE: u1,
+            ///  A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.
+            CAP0MCI1_RE: u1,
+            ///  A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.
+            CAP0MCI1_FE: u1,
+            ///  A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.
+            CAP0MCI2_RE: u1,
+            ///  A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.
+            CAP0MCI2_FE: u1,
+            ///  A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.
+            CAP1MCI0_RE: u1,
+            ///  A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.
+            CAP1MCI0_FE: u1,
+            ///  A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.
+            CAP1MCI1_RE: u1,
+            ///  A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.
+            CAP1MCI1_FE: u1,
+            ///  A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.
+            CAP1MCI2_RE: u1,
+            ///  A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.
+            CAP1MCI2_FE: u1,
+            ///  A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.
+            CAP2MCI0_RE: u1,
+            ///  A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.
+            CAP2MCI0_FE: u1,
+            ///  A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.
+            CAP2MCI1_RE: u1,
+            ///  A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.
+            CAP2MCI1_FE: u1,
+            ///  A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.
+            CAP2MCI2_RE: u1,
+            ///  A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.
+            CAP2MCI2_FE: u1,
+            ///  If this bit is 1, TC0 is reset by a channel 0 capture event.
+            RT0: u1,
+            ///  If this bit is 1, TC1 is reset by a channel 1 capture event.
+            RT1: u1,
+            ///  If this bit is 1, TC2 is reset by a channel 2 capture event.
+            RT2: u1,
+            ///  Reserved.
+            RESERVED: u11,
+        }),
+        ///  Capture Control set address
+        CAPCON_SET: mmio.Mmio(packed struct(u32) {
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP0MCI0_RE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP0MCI0_FE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP0MCI1_RE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP0MCI1_FE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP0MCI2_RE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP0MCI2_FE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP1MCI0_RE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP1MCI0_FE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP1MCI1_RE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP1MCI1_FE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP1MCI2_RE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP1MCI2_FE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP2MCI0_RE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP2MCI0_FE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP2MCI1_RE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP2MCI1_FE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP2MCI2_RE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            CAP2MCI2_FE_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            RT0_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            RT1_SET: u1,
+            ///  Writing a one sets the corresponding bits in the CAPCON register.
+            RT2_SET: u1,
+            ///  Reserved.
+            RESERVED: u11,
+        }),
+        ///  Event Control clear address
+        CAPCON_CLR: mmio.Mmio(packed struct(u32) {
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP0MCI0_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP0MCI0_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP0MCI1_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP0MCI1_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP0MCI2_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP0MCI2_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP1MCI0_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP1MCI0_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP1MCI1_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP1MCI1_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP1MCI2_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP1MCI2_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP2MCI0_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP2MCI0_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP2MCI1_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP2MCI1_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP2MCI2_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            CAP2MCI2_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            RT0_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            RT1_CLR: u1,
+            ///  Writing a one clears the corresponding bits in the CAPCON register.
+            RT2_CLR: u1,
+            ///  Reserved.
+            RESERVED: u11,
+        }),
+        reserved60: [36]u8,
+        ///  Dead time register
+        DT: mmio.Mmio(packed struct(u32) {
+            ///  Dead time for channel 0.[1]
+            DT0: u10,
+            ///  Dead time for channel 1.[2]
+            DT1: u10,
+            ///  Dead time for channel 2.[2]
+            DT2: u10,
+            ///  reserved
+            RESERVED: u2,
+        }),
+        ///  Communication Pattern register
+        CP: mmio.Mmio(packed struct(u32) {
+            ///  Communication pattern output A, channel 0.
+            CCPA0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  MCOA0 passive.
+                    MCOA0_PASSIVE_ = 0x0,
+                    ///  internal MCOA0.
+                    INTERNAL_MCOA0_ = 0x1,
+                },
+            },
+            ///  Communication pattern output B, channel 0.
+            CCPB0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  MCOB0 passive.
+                    MCOB0_PASSIVE_ = 0x0,
+                    ///  MCOB0 tracks internal MCOA0.
+                    MCOB0_TRACKS_INTERNA = 0x1,
+                },
+            },
+            ///  Communication pattern output A, channel 1.
+            CCPA1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  MCOA1 passive.
+                    MCOA1_PASSIVE_ = 0x0,
+                    ///  MCOA1 tracks internal MCOA0.
+                    MCOA1_TRACKS_INTERNA = 0x1,
+                },
+            },
+            ///  Communication pattern output B, channel 1.
+            CCPB1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  MCOB1 passive.
+                    MCOB1_PASSIVE_ = 0x0,
+                    ///  MCOB1 tracks internal MCOA0.
+                    MCOB1_TRACKS_INTERNA = 0x1,
+                },
+            },
+            ///  Communication pattern output A, channel 2.
+            CCPA2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  MCOA2 passive.
+                    MCOA2_PASSIVE_ = 0x0,
+                    ///  MCOA2 tracks internal MCOA0.
+                    MCOA2_TRACKS_INTERNA = 0x1,
+                },
+            },
+            ///  Communication pattern output B, channel 2.
+            CCPB2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  MCOB2 passive.
+                    MCOB2_PASSIVE_ = 0x0,
+                    ///  MCOB2 tracks internal MCOA0.
+                    MCOB2_TRACKS_INTERNA = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u26,
+        }),
+        reserved80: [12]u8,
+        ///  Interrupt Enable read address
+        INTEN: mmio.Mmio(packed struct(u32) {
+            ///  Limit interrupt for channel 0.
+            ILIM0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt disabled.
+                    INTERRUPT_DISABLED_ = 0x0,
+                    ///  Interrupt enabled.
+                    INTERRUPT_ENABLED_ = 0x1,
+                },
+            },
+            ///  Match interrupt for channel 0.
+            IMAT0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt disabled.
+                    INTERRUPT_DISABLED_ = 0x0,
+                    ///  Interrupt enabled.
+                    INTERRUPT_ENABLED_ = 0x1,
+                },
+            },
+            ///  Capture interrupt for channel 0.
+            ICAP0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt disabled.
+                    INTERRUPT_DISABLED_ = 0x0,
+                    ///  Interrupt enabled.
+                    INTERRUPT_ENABLED_ = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Limit interrupt for channel 1.
+            ILIM1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt disabled.
+                    INTERRUPT_DISABLED_ = 0x0,
+                    ///  Interrupt enabled.
+                    INTERRUPT_ENABLED_ = 0x1,
+                },
+            },
+            ///  Match interrupt for channel 1.
+            IMAT1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt disabled.
+                    INTERRUPT_DISABLED_ = 0x0,
+                    ///  Interrupt enabled.
+                    INTERRUPT_ENABLED_ = 0x1,
+                },
+            },
+            ///  Capture interrupt for channel 1.
+            ICAP1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt disabled.
+                    INTERRUPT_DISABLED_ = 0x0,
+                    ///  Interrupt enabled.
+                    INTERRUPT_ENABLED_ = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Limit interrupt for channel 2.
+            ILIM2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt disabled.
+                    INTERRUPT_DISABLED_ = 0x0,
+                    ///  Interrupt enabled.
+                    INTERRUPT_ENABLED_ = 0x1,
+                },
+            },
+            ///  Match interrupt for channel 2.
+            IMAT2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt disabled.
+                    INTERRUPT_DISABLED_ = 0x0,
+                    ///  Interrupt enabled.
+                    INTERRUPT_ENABLED_ = 0x1,
+                },
+            },
+            ///  Capture interrupt for channel 2.
+            ICAP2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt disabled.
+                    INTERRUPT_DISABLED_ = 0x0,
+                    ///  Interrupt enabled.
+                    INTERRUPT_ENABLED_ = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u4,
+            ///  Fast abort interrupt.
+            ABORT: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Interrupt disabled.
+                    INTERRUPT_DISABLED_ = 0x0,
+                    ///  Interrupt enabled.
+                    INTERRUPT_ENABLED_ = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u16,
+        }),
+        ///  Interrupt Enable set address
+        INTEN_SET: mmio.Mmio(packed struct(u32) {
+            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
+            ILIM0_SET: u1,
+            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
+            IMAT0_SET: u1,
+            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
+            ICAP0_SET: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
+            ILIM1_SET: u1,
+            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
+            IMAT1_SET: u1,
+            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
+            ICAP1_SET: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            reserved9: u1,
+            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
+            ILIM2_SET: u1,
+            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
+            IMAT2_SET: u1,
+            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
+            ICAP2_SET: u1,
+            ///  Reserved.
+            RESERVED: u3,
+            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
+            ABORT_SET: u1,
+            ///  Reserved.
+            RESERVED: u16,
+        }),
+        ///  Interrupt Enable clear address
+        INTEN_CLR: mmio.Mmio(packed struct(u32) {
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ILIM0_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            IMAT0_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ICAP0_CLR: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ILIM1_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            IMAT1_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ICAP1_CLR: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ILIM2_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            IMAT2_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ICAP2_CLR: u1,
+            ///  Reserved.
+            RESERVED: u4,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ABORT_CLR: u1,
+            ///  Reserved.
+            RESERVED: u16,
+        }),
+        ///  Count Control read address
+        CNTCON: mmio.Mmio(packed struct(u32) {
+            ///  Counter 0 rising edge mode, channel 0.
+            TC0MCI0_RE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A rising edge on MCI0 does not affect counter 0.
+                    A_RISING_EDGE_ON_MCI = 0x0,
+                    ///  If MODE0 is 1, counter 0 advances on a rising edge on MCI0.
+                    RISING = 0x1,
+                },
+            },
+            ///  Counter 0 falling edge mode, channel 0.
+            TC0MCI0_FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A falling edge on MCI0 does not affect counter 0.
+                    A_FALLING_EDGE_ON_MC = 0x0,
+                    ///  If MODE0 is 1, counter 0 advances on a falling edge on MCI0.
+                    FALLING = 0x1,
+                },
+            },
+            ///  Counter 0 rising edge mode, channel 1.
+            TC0MCI1_RE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A rising edge on MCI1 does not affect counter 0.
+                    A_RISING_EDGE_ON_MCI = 0x0,
+                    ///  If MODE0 is 1, counter 0 advances on a rising edge on MCI1.
+                    RISING = 0x1,
+                },
+            },
+            ///  Counter 0 falling edge mode, channel 1.
+            TC0MCI1_FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A falling edge on MCI1 does not affect counter 0.
+                    A_FALLING_EDGE_ON_MC = 0x0,
+                    ///  If MODE0 is 1, counter 0 advances on a falling edge on MCI1.
+                    FALLING = 0x1,
+                },
+            },
+            ///  Counter 0 rising edge mode, channel 2.
+            TC0MCI2_RE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A rising edge on MCI0 does not affect counter 0.
+                    A_RISING_EDGE_ON_MCI = 0x0,
+                    ///  If MODE0 is 1, counter 0 advances on a rising edge on MCI2.
+                    RISING = 0x1,
+                },
+            },
+            ///  Counter 0 falling edge mode, channel 2.
+            TC0MCI2_FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A falling edge on MCI0 does not affect counter 0.
+                    A_FALLING_EDGE_ON_MC = 0x0,
+                    ///  If MODE0 is 1, counter 0 advances on a falling edge on MCI2.
+                    FALLLING = 0x1,
+                },
+            },
+            ///  Counter 1 rising edge mode, channel 0.
+            TC1MCI0_RE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A rising edge on MCI0 does not affect counter 1.
+                    A_RISING_EDGE_ON_MCI = 0x0,
+                    ///  If MODE1 is 1, counter 1 advances on a rising edge on MCI0.
+                    RISING = 0x1,
+                },
+            },
+            ///  Counter 1 falling edge mode, channel 0.
+            TC1MCI0_FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A falling edge on MCI0 does not affect counter 1.
+                    A_FALLING_EDGE_ON_MC = 0x0,
+                    ///  If MODE1 is 1, counter 1 advances on a falling edge on MCI0.
+                    FALLING = 0x1,
+                },
+            },
+            ///  Counter 1 rising edge mode, channel 1.
+            TC1MCI1_RE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A rising edge on MCI1 does not affect counter 1.
+                    A_RISING_EDGE_ON_MCI = 0x0,
+                    ///  If MODE1 is 1, counter 1 advances on a rising edge on MCI1.
+                    RISING = 0x1,
+                },
+            },
+            ///  Counter 1 falling edge mode, channel 1.
+            TC1MCI1_FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A falling edge on MCI0 does not affect counter 1.
+                    A_FALLING_EDGE_ON_MC = 0x0,
+                    ///  If MODE1 is 1, counter 1 advances on a falling edge on MCI1.
+                    FALLING = 0x1,
+                },
+            },
+            ///  Counter 1 rising edge mode, channel 2.
+            TC1MCI2_RE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A rising edge on MCI2 does not affect counter 1.
+                    A_RISING_EDGE_ON_MCI = 0x0,
+                    ///  If MODE1 is 1, counter 1 advances on a rising edge on MCI2.
+                    RISING = 0x1,
+                },
+            },
+            ///  Counter 1 falling edge mode, channel 2.
+            TC1MCI2_FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A falling edge on MCI2 does not affect counter 1.
+                    A_FALLING_EDGE_ON_MC = 0x0,
+                    ///  If MODE1 is 1, counter 1 advances on a falling edge on MCI2.
+                    FALLING = 0x1,
+                },
+            },
+            ///  Counter 2 rising edge mode, channel 0.
+            TC2MCI0_RE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A rising edge on MCI0 does not affect counter 2.
+                    A_RISING_EDGE_ON_MCI = 0x0,
+                    ///  If MODE2 is 1, counter 2 advances on a rising edge on MCI0.
+                    RISING = 0x1,
+                },
+            },
+            ///  Counter 2 falling edge mode, channel 0.
+            TC2MCI0_FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A falling edge on MCI0 does not affect counter 2.
+                    A_FALLING_EDGE_ON_MC = 0x0,
+                    ///  If MODE2 is 1, counter 2 advances on a falling edge on MCI0.
+                    FALLING = 0x1,
+                },
+            },
+            ///  Counter 2 rising edge mode, channel 1.
+            TC2MCI1_RE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A rising edge on MCI1 does not affect counter 2.
+                    A_RISING_EDGE_ON_MCI = 0x0,
+                    ///  If MODE2 is 1, counter 2 advances on a rising edge on MCI1.
+                    RISING = 0x1,
+                },
+            },
+            ///  Counter 2 falling edge mode, channel 1.
+            TC2MCI1_FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A falling edge on MCI1 does not affect counter 2.
+                    A_FALLING_EDGE_ON_MC = 0x0,
+                    ///  If MODE2 is 1, counter 2 advances on a falling edge on MCI1.
+                    FALLING = 0x1,
+                },
+            },
+            ///  Counter 2 rising edge mode, channel 2.
+            TC2MCI2_RE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A rising edge on MCI2 does not affect counter 2.
+                    A_RISING_EDGE_ON_MCI = 0x0,
+                    ///  If MODE2 is 1, counter 2 advances on a rising edge on MCI2.
+                    RISIING = 0x1,
+                },
+            },
+            ///  Counter 2 falling edge mode, channel 2.
+            TC2MCI2_FE: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  A falling edge on MCI2 does not affect counter 2.
+                    A_FALLING_EDGE_ON_MC = 0x0,
+                    ///  If MODE2 is 1, counter 2 advances on a falling edge on MCI2.
+                    FALLING = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u11,
+            ///  Channel 0 counter/timer mode.
+            CNTR0: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Channel 0 is in timer mode.
+                    CHANNEL_0_IS_IN_TIME = 0x0,
+                    ///  Channel 0 is in counter mode.
+                    CHANNEL_0_IS_IN_COUN = 0x1,
+                },
+            },
+            ///  Channel 1 counter/timer mode.
+            CNTR1: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Channel 1 is in timer mode.
+                    CHANNEL_1_IS_IN_TIME = 0x0,
+                    ///  Channel 1 is in counter mode.
+                    CHANNEL_1_IS_IN_COUN = 0x1,
+                },
+            },
+            ///  Channel 2 counter/timer mode.
+            CNTR2: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Channel 2 is in timer mode.
+                    CHANNEL_2_IS_IN_TIME = 0x0,
+                    ///  Channel 2 is in counter mode.
+                    CHANNEL_2_IS_IN_COUN = 0x1,
+                },
+            },
+        }),
+        ///  Count Control set address
+        CNTCON_SET: mmio.Mmio(packed struct(u32) {
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC0MCI0_RE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC0MCI0_FE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC0MCI1_RE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC0MCI1_FE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC0MCI2_RE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC0MCI2_FE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC1MCI0_RE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC1MCI0_FE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC1MCI1_RE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC1MCI1_FE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC1MCI2_RE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC1MCI2_FE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC2MCI0_RE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC2MCI0_FE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC2MCI1_RE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC2MCI1_FE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC2MCI2_RE_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            TC2MCI2_FE_SET: u1,
+            ///  Reserved.
+            RESERVED: u11,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            CNTR0_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            CNTR1_SET: u1,
+            ///  Writing a one sets the corresponding bit in the CNTCON register.
+            CNTR2_SET: u1,
+        }),
+        ///  Count Control clear address
+        CNTCON_CLR: mmio.Mmio(packed struct(u32) {
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC0MCI0_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC0MCI0_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC0MCI1_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC0MCI1_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC0MCI2_RE: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC0MCI2_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC1MCI0_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC1MCI0_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC1MCI1_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC1MCI1_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC1MCI2_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC1MCI2_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC2MCI0_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC2MCI0_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC2MCI1_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC2MCI1_FE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC2MCI2_RE_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            TC2MCI2_FE_CLR: u1,
+            ///  Reserved.
+            RESERVED: u11,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            CNTR0_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            CNTR1_CLR: u1,
+            ///  Writing a one clears the corresponding bit in the CNTCON register.
+            CNTR2_CLR: u1,
+        }),
+        ///  Interrupt flags read address
+        INTF: mmio.Mmio(packed struct(u32) {
+            ///  Limit interrupt flag for channel 0.
+            ILIM0_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
+                    THIS_INTERRUPT_SOURC = 0x0,
+                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
+                    IF_THE_CORRESPONDING = 0x1,
+                },
+            },
+            ///  Match interrupt flag for channel 0.
+            IMAT0_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
+                    THIS_INTERRUPT_SOURC = 0x0,
+                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
+                    IF_THE_CORRESPONDING = 0x1,
+                },
+            },
+            ///  Capture interrupt flag for channel 0.
+            ICAP0_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
+                    THIS_INTERRUPT_SOURC = 0x0,
+                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
+                    IF_THE_CORRESPONDING = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Limit interrupt flag for channel 1.
+            ILIM1_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
+                    THIS_INTERRUPT_SOURC = 0x0,
+                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
+                    IF_THE_CORRESPONDING = 0x1,
+                },
+            },
+            ///  Match interrupt flag for channel 1.
+            IMAT1_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
+                    THIS_INTERRUPT_SOURC = 0x0,
+                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
+                    IF_THE_CORRESPONDING = 0x1,
+                },
+            },
+            ///  Capture interrupt flag for channel 1.
+            ICAP1_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
+                    THIS_INTERRUPT_SOURC = 0x0,
+                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
+                    IF_THE_CORRESPONDING = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Limit interrupt flag for channel 2.
+            ILIM2_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
+                    THIS_INTERRUPT_SOURC = 0x0,
+                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
+                    IF_THE_CORRESPONDING = 0x1,
+                },
+            },
+            ///  Match interrupt flag for channel 2.
+            IMAT2_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
+                    THIS_INTERRUPT_SOURC = 0x0,
+                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
+                    IF_THE_CORRESPONDING = 0x1,
+                },
+            },
+            ///  Capture interrupt flag for channel 2.
+            ICAP2_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
+                    THIS_INTERRUPT_SOURC = 0x0,
+                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
+                    IF_THE_CORRESPONDING = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u4,
+            ///  Fast abort interrupt flag.
+            ABORT_F: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
+                    THIS_INTERRUPT_SOURC = 0x0,
+                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
+                    IF_THE_CORRESPONDING = 0x1,
+                },
+            },
+            ///  Reserved.
+            RESERVED: u16,
+        }),
+        ///  Interrupt flags set address
+        INTF_SET: mmio.Mmio(packed struct(u32) {
+            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
+            ILIM0_F_SET: u1,
+            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
+            IMAT0_F_SET: u1,
+            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
+            ICAP0_F_SET: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
+            ILIM1_F_SET: u1,
+            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
+            IMAT1_F_SET: u1,
+            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
+            ICAP1_F_SET: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
+            ILIM2_F_SET: u1,
+            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
+            IMAT2_F_SET: u1,
+            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
+            ICAP2_F_SET: u1,
+            ///  Reserved.
+            RESERVED: u4,
+            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
+            ABORT_F_SET: u1,
+            ///  Reserved.
+            RESERVED: u16,
+        }),
+        ///  Interrupt flags clear address
+        INTF_CLR: mmio.Mmio(packed struct(u32) {
+            ///  Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request.
+            ILIM0_F_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            IMAT0_F_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ICAP0_F_CLR: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ILIM1_F_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            IMAT1_F_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ICAP1_F_CLR: u1,
+            ///  Reserved.
+            RESERVED: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ILIM2_F_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            IMAT2_F_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ICAP2_F_CLR: u1,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            RESERVED: u4,
+            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
+            ABORT_F_CLR: u1,
+            ///  Reserved.
+            RESERVED: u16,
+        }),
+        ///  Capture clear address
+        CAP_CLR: mmio.Mmio(packed struct(u32) {
+            ///  Writing a 1 to this bit clears the CAP0 register.
+            CAP_CLR0: u1,
+            ///  Writing a 1 to this bit clears the CAP1 register.
+            CAP_CLR1: u1,
+            ///  Writing a 1 to this bit clears the CAP2 register.
+            CAP_CLR2: u1,
+            ///  Reserved
+            RESERVED: u29,
+        }),
+    };
+
+    ///  Repetitive Interrupt Timer (RIT)
+    pub const RITIMER = extern struct {
+        ///  Compare register
+        COMPVAL: mmio.Mmio(packed struct(u32) {
+            ///  Compare register. Holds the compare value which is compared to the counter.
+            RICOMP: u32,
+        }),
+        ///  Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register.
+        MASK: mmio.Mmio(packed struct(u32) {
+            ///  Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).
+            RIMASK: u32,
+        }),
+        ///  Control register.
+        CTRL: mmio.Mmio(packed struct(u32) {
+            ///  Interrupt flag
+            RITINT: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect.
+                    THIS_BIT_IS_SET_TO_1 = 0x1,
+                    ///  The counter value does not equal the masked compare value.
+                    THE_COUNTER_VALUE_DO = 0x0,
+                },
+            },
+            ///  Timer enable clear
+            RITENCLR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag.
+                    THE_TIMER_WILL_BE_CL = 0x1,
+                    ///  The timer will not be cleared to 0.
+                    THE_TIMER_WILL_NOT_B = 0x0,
+                },
+            },
+            ///  Timer enable for debug
+            RITENBR: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  The timer is halted when the processor is halted for debugging.
+                    THE_TIMER_IS_HALTED_ = 0x1,
+                    ///  Debug has no effect on the timer operation.
+                    DEBUG_HAS_NO_EFFECT_ = 0x0,
+                },
+            },
+            ///  Timer enable.
+            RITEN: packed union {
+                raw: u1,
+                value: enum(u1) {
+                    ///  Timer enabled. This can be overruled by a debug halt if enabled in bit 2.
+                    TIMER_ENABLED_THIS_ = 0x1,
+                    ///  Timer disabled.
+                    TIMER_DISABLED_ = 0x0,
+                },
+            },
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        ///  32-bit counter
+        COUNTER: mmio.Mmio(packed struct(u32) {
+            ///  32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.
+            RICOUNTER: u32,
+        }),
+    };
+
+    ///  I2S interface
+    pub const I2S = extern struct {
+        ///  I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel.
+        DAO: mmio.Mmio(packed struct(u32) {
+            ///  Selects the number of bytes in data as follows:
+            WORDWIDTH: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  8-bit data
+                    @"8_BIT_DATA" = 0x0,
+                    ///  16-bit data
+                    @"16_BIT_DATA" = 0x1,
+                    ///  32-bit data
+                    @"32_BIT_DATA" = 0x3,
+                    _,
+                },
+            },
+            ///  When 1, data is of monaural format. When 0, the data is in stereo format.
+            MONO: u1,
+            ///  When 1, disables accesses on FIFOs, places the transmit channel in mute mode.
+            STOP: u1,
+            ///  When 1, asynchronously resets the transmit channel and FIFO.
+            RESET: u1,
+            ///  When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE.
+            WS_SEL: u1,
+            ///  Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.
+            WS_HALFPERIOD: u9,
+            ///  When 1, the transmit channel sends only zeroes.
+            MUTE: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u16,
+        }),
+        ///  I2S Digital Audio Input Register. Contains control bits for the I2S receive channel.
+        DAI: mmio.Mmio(packed struct(u32) {
+            ///  Selects the number of bytes in data as follows:
+            WORDWIDTH: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  8-bit data
+                    @"8_BIT_DATA" = 0x0,
+                    ///  16-bit data
+                    @"16_BIT_DATA" = 0x1,
+                    ///  32-bit data
+                    @"32_BIT_DATA" = 0x3,
+                    _,
+                },
+            },
+            ///  When 1, data is of monaural format. When 0, the data is in stereo format.
+            MONO: u1,
+            ///  When 1, disables accesses on FIFOs, places the transmit channel in mute mode.
+            STOP: u1,
+            ///  When 1, asynchronously reset the transmit channel and FIFO.
+            RESET: u1,
+            ///  When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE.
+            WS_SEL: u1,
+            ///  Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.
+            WS_HALFPERIOD: u9,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u17,
+        }),
+        ///  I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO.
+        TXFIFO: mmio.Mmio(packed struct(u32) {
+            ///  8 x 32-bit transmit FIFO.
+            I2STXFIFO: u32,
+        }),
+        ///  I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO.
+        RXFIFO: mmio.Mmio(packed struct(u32) {
+            ///  8 x 32-bit transmit FIFO.
+            I2SRXFIFO: u32,
+        }),
+        ///  I2S Status Feedback Register. Contains status information about the I2S interface.
+        STATE: mmio.Mmio(packed struct(u32) {
+            ///  This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register.
+            IRQ: u1,
+            ///  This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register.
+            DMAREQ1: u1,
+            ///  This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register.
+            DMAREQ2: u1,
+            ///  Reserved.
+            RESERVED: u5,
+            ///  Reflects the current level of the Receive FIFO.
+            RX_LEVEL: u4,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u4,
+            ///  Reflects the current level of the Transmit FIFO.
+            TX_LEVEL: u4,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u12,
+        }),
+        ///  I2S DMA Configuration Register 1. Contains control information for DMA request 1.
+        DMA1: mmio.Mmio(packed struct(u32) {
+            ///  When 1, enables DMA1 for I2S receive.
+            RX_DMA1_ENABLE: u1,
+            ///  When 1, enables DMA1 for I2S transmit.
+            TX_DMA1_ENABLE: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u6,
+            ///  Set the FIFO level that triggers a receive DMA request on DMA1.
+            RX_DEPTH_DMA1: u4,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u4,
+            ///  Set the FIFO level that triggers a transmit DMA request on DMA1.
+            TX_DEPTH_DMA1: u4,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u12,
+        }),
+        ///  I2S DMA Configuration Register 2. Contains control information for DMA request 2.
+        DMA2: mmio.Mmio(packed struct(u32) {
+            ///  When 1, enables DMA1 for I2S receive.
+            RX_DMA2_ENABLE: u1,
+            ///  When 1, enables DMA1 for I2S transmit.
+            TX_DMA2_ENABLE: u1,
+            ///  Reserved.
+            RESERVED: u6,
+            ///  Set the FIFO level that triggers a receive DMA request on DMA2.
+            RX_DEPTH_DMA2: u4,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u4,
+            ///  Set the FIFO level that triggers a transmit DMA request on DMA2.
+            TX_DEPTH_DMA2: u4,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u12,
+        }),
+        ///  I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated.
+        IRQ: mmio.Mmio(packed struct(u32) {
+            ///  When 1, enables I2S receive interrupt.
+            RX_IRQ_ENABLE: u1,
+            ///  When 1, enables I2S transmit interrupt.
+            TX_IRQ_ENABLE: u1,
+            ///  Reserved.
+            RESERVED: u6,
+            ///  Set the FIFO level on which to create an irq request.
+            RX_DEPTH_IRQ: u4,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u4,
+            ///  Set the FIFO level on which to create an irq request.
+            TX_DEPTH_IRQ: u4,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u12,
+        }),
+        ///  I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.
+        TXRATE: mmio.Mmio(packed struct(u32) {
+            ///  I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.
+            Y_DIVIDER: u8,
+            ///  I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.
+            X_DIVIDER: u8,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u16,
+        }),
+        ///  I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.
+        RXRATE: mmio.Mmio(packed struct(u32) {
+            ///  I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.
+            Y_DIVIDER: u8,
+            ///  I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.
+            X_DIVIDER: u8,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u16,
+        }),
+        ///  I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock.
+        TXBITRATE: mmio.Mmio(packed struct(u32) {
+            ///  I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock.
+            TX_BITRATE: u6,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u26,
+        }),
+        ///  I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock.
+        RXBITRATE: mmio.Mmio(packed struct(u32) {
+            ///  I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock.
+            RX_BITRATE: u6,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u26,
+        }),
+        ///  I2S Transmit mode control.
+        TXMODE: mmio.Mmio(packed struct(u32) {
+            ///  Clock source selection for the transmit bit clock divider.
+            TXCLKSEL: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Select the TX fractional rate divider clock output as the source
+                    SELECT_THE_TX_FRACTI = 0x0,
+                    ///  Select the RX_MCLK signal as the TX_MCLK clock source
+                    SELECT_THE_RX_MCLK_S = 0x2,
+                    _,
+                },
+            },
+            ///  Transmit 4-pin mode selection. When 1, enables 4-pin mode.
+            TX4PIN: u1,
+            ///  Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled.
+            TXMCENA: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+        ///  I2S Receive mode control.
+        RXMODE: mmio.Mmio(packed struct(u32) {
+            ///  Clock source selection for the receive bit clock divider.
+            RXCLKSEL: packed union {
+                raw: u2,
+                value: enum(u2) {
+                    ///  Select the RX fractional rate divider clock output as the source
+                    SELECT_THE_RX_FRACTI = 0x0,
+                    ///  Select the TX_MCLK signal as the RX_MCLK clock source
+                    SELECT_THE_TX_MCLK_S = 0x2,
+                    _,
+                },
+            },
+            ///  Receive 4-pin mode selection. When 1, enables 4-pin mode.
+            RX4PIN: u1,
+            ///  Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled.
+            RXMCENA: u1,
+            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
+            RESERVED: u28,
+        }),
+    };
+};
diff --git a/src/hals/LPC176x5x.zig b/src/hals/LPC176x5x.zig
new file mode 100644
index 000000000..3db032e0e
--- /dev/null
+++ b/src/hals/LPC176x5x.zig
@@ -0,0 +1,205 @@
+const std = @import("std");
+const micro = @import("microzig");
+const chip = @import("registers.zig");
+const regs = chip.registers;
+
+pub usingnamespace chip;
+
+pub const clock = struct {
+    pub const Domain = enum {
+        cpu,
+    };
+};
+
+pub const clock_frequencies = .{
+    .cpu = 100_000_000, // 100 Mhz
+};
+
+pub const PinTarget = enum(u2) {
+    func00 = 0b00,
+    func01 = 0b01,
+    func10 = 0b10,
+    func11 = 0b11,
+};
+
+pub fn parse_pin(comptime spec: []const u8) type {
+    const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}.{Pin}\" scheme.";
+    if (spec[0] != 'P')
+        @compileError(invalid_format_msg);
+
+    const index = std.mem.indexOfScalar(u8, spec, '.') orelse @compileError(invalid_format_msg);
+
+    const _port: comptime_int = std.fmt.parseInt(u3, spec[1..index], 10) catch @compileError(invalid_format_msg);
+    const _pin: comptime_int = std.fmt.parseInt(u5, spec[index + 1 ..], 10) catch @compileError(invalid_format_msg);
+
+    const sel_reg_name = std.fmt.comptimePrint("PINSEL{d}", .{(2 * _port + _pin / 16)});
+
+    const _regs = struct {
+        const name_suffix = std.fmt.comptimePrint("{d}", .{_port});
+
+        const pinsel_reg = @field(regs.PINCONNECT, sel_reg_name);
+        const pinsel_field = std.fmt.comptimePrint("P{d}_{d}", .{ _port, _pin });
+
+        const dir = @field(regs.GPIO, "DIR" ++ name_suffix);
+        const pin = @field(regs.GPIO, "PIN" ++ name_suffix);
+        const set = @field(regs.GPIO, "SET" ++ name_suffix);
+        const clr = @field(regs.GPIO, "CLR" ++ name_suffix);
+        const mask = @field(regs.GPIO, "MASK" ++ name_suffix);
+    };
+
+    return struct {
+        pub const port: u3 = _port;
+        pub const pin: u5 = _pin;
+        pub const regs = _regs;
+        const gpio_mask: u32 = (1 << pin);
+
+        pub const Targets = PinTarget;
+    };
+}
+
+pub fn route_pin(comptime pin: type, function: PinTarget) void {
+    var val = pin.regs.pinsel_reg.read();
+    @field(val, pin.regs.pinsel_field) = @enumToInt(function);
+    pin.regs.pinsel_reg.write(val);
+}
+
+pub const gpio = struct {
+    pub fn set_output(comptime pin: type) void {
+        pin.regs.dir.raw |= pin.gpio_mask;
+    }
+    pub fn set_input(comptime pin: type) void {
+        pin.regs.dir.raw &= ~pin.gpio_mask;
+    }
+
+    pub fn read(comptime pin: type) micro.gpio.State {
+        return if ((pin.regs.pin.raw & pin.gpio_mask) != 0)
+            micro.gpio.State.high
+        else
+            micro.gpio.State.low;
+    }
+
+    pub fn write(comptime pin: type, state: micro.gpio.State) void {
+        if (state == .high) {
+            pin.regs.set.raw = pin.gpio_mask;
+        } else {
+            pin.regs.clr.raw = pin.gpio_mask;
+        }
+    }
+};
+
+pub const uart = struct {
+    pub const DataBits = enum(u2) {
+        five = 0,
+        six = 1,
+        seven = 2,
+        eight = 3,
+    };
+
+    pub const StopBits = enum(u1) {
+        one = 0,
+        two = 1,
+    };
+
+    pub const Parity = enum(u2) {
+        odd = 0,
+        even = 1,
+        mark = 2,
+        space = 3,
+    };
+
+    pub const CClkDiv = enum(u2) {
+        four = 0,
+        one = 1,
+        two = 2,
+        eight = 3,
+    };
+};
+
+pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
+    if (pins.tx != null or pins.rx != null)
+        @compileError("TODO: custom pins are not currently supported");
+
+    return struct {
+        const UARTn = switch (index) {
+            0 => regs.UART0,
+            1 => regs.UART1,
+            2 => regs.UART2,
+            3 => regs.UART3,
+            else => @compileError("LPC1768 has 4 UARTs available."),
+        };
+        const Self = @This();
+
+        pub fn init(config: micro.uart.Config) !Self {
+            micro.debug.write("0");
+            switch (index) {
+                0 => {
+                    regs.SYSCON.PCONP.modify(.{ .PCUART0 = 1 });
+                    regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = @enumToInt(uart.CClkDiv.four) });
+                },
+                1 => {
+                    regs.SYSCON.PCONP.modify(.{ .PCUART1 = 1 });
+                    regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = @enumToInt(uart.CClkDiv.four) });
+                },
+                2 => {
+                    regs.SYSCON.PCONP.modify(.{ .PCUART2 = 1 });
+                    regs.SYSCON.PCLKSEL1.modify(.{ .PCLK_UART2 = @enumToInt(uart.CClkDiv.four) });
+                },
+                3 => {
+                    regs.SYSCON.PCONP.modify(.{ .PCUART3 = 1 });
+                    regs.SYSCON.PCLKSEL1.modify(.{ .PCLK_UART3 = @enumToInt(uart.CClkDiv.four) });
+                },
+                else => unreachable,
+            }
+            micro.debug.write("1");
+
+            UARTn.LCR.modify(.{
+                // 8N1
+                .WLS = @enumToInt(config.data_bits),
+                .SBS = @enumToInt(config.stop_bits),
+                .PE = if (config.parity != null) @as(u1, 1) else @as(u1, 0),
+                .PS = if (config.parity) |p| @enumToInt(p) else @enumToInt(uart.Parity.odd),
+                .BC = 0,
+                .DLAB = 1,
+            });
+            micro.debug.write("2");
+
+            // TODO: UARTN_FIFOS_ARE_DISA is not available in all uarts
+            //UARTn.FCR.modify(.{ .FIFOEN = .UARTN_FIFOS_ARE_DISA });
+
+            micro.debug.writer().print("clock: {} baud: {} ", .{
+                micro.clock.get().cpu,
+                config.baud_rate,
+            }) catch {};
+
+            const pclk = micro.clock.get().cpu / 4;
+            const divider = (pclk / (16 * config.baud_rate));
+
+            const regval = std.math.cast(u16, divider) orelse return error.UnsupportedBaudRate;
+
+            UARTn.DLL.modify(.{ .DLLSB = @truncate(u8, regval >> 0x00) });
+            UARTn.DLM.modify(.{ .DLMSB = @truncate(u8, regval >> 0x08) });
+
+            UARTn.LCR.modify(.{ .DLAB = 0 });
+
+            return Self{};
+        }
+
+        pub fn can_write(self: Self) bool {
+            _ = self;
+            return (UARTn.LSR.read().THRE == 1);
+        }
+        pub fn tx(self: Self, ch: u8) void {
+            while (!self.can_write()) {} // Wait for Previous transmission
+            UARTn.THR.raw = ch; // Load the data to be transmitted
+        }
+
+        pub fn can_read(self: Self) bool {
+            _ = self;
+            return (UARTn.LSR.read().RDR == 1);
+        }
+        pub fn rx(self: Self) u8 {
+            while (!self.can_read()) {} // Wait till the data is received
+            return UARTn.RBR.read().RBR; // Read received data
+        }
+    };
+}

From 488cb11650bea6350ddc2ffe6a0db15a89627ae0 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 18 Feb 2023 17:06:25 -0500
Subject: [PATCH 043/286] Initial commit

---
 .buildkite/pipeline.yml   |  4 ++++
 .gitignore                |  2 ++
 .gitmodules               |  3 +++
 LICENSE                   | 19 +++++++++++++++++++
 README.adoc               |  6 ++++++
 build.zig                 | 35 +++++++++++++++++++++++++++++++++++
 deps/microzig             |  1 +
 src/boards.zig            |  6 ++++++
 src/chips.zig             |  6 ++++++
 test/programs/minimal.zig |  5 +++++
 10 files changed, 87 insertions(+)
 create mode 100644 .buildkite/pipeline.yml
 create mode 100644 .gitignore
 create mode 100644 .gitmodules
 create mode 100644 LICENSE
 create mode 100644 README.adoc
 create mode 100644 build.zig
 create mode 160000 deps/microzig
 create mode 100644 src/boards.zig
 create mode 100644 src/chips.zig
 create mode 100644 test/programs/minimal.zig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
new file mode 100644
index 000000000..7767bbb66
--- /dev/null
+++ b/.buildkite/pipeline.yml
@@ -0,0 +1,4 @@
+steps:
+  - group: Build
+    steps:
+    - command: zig build
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 000000000..4c82b07c0
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+zig-cache
+zig-out
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 000000000..32e895ccb
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "deps/microzig"]
+	path = deps/microzig
+	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 000000000..c1cc5ecad
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,19 @@
+Copyright (c) 2022 
+
+This software is provided 'as-is', without any express or implied warranty. In
+no event will the authors be held liable for any damages arising from the use
+of this software.
+
+Permission is granted to anyone to use this software for any purpose, including
+commercial applications, and to alter it and redistribute it freely, subject to
+the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must not claim
+that you wrote the original software. If you use this software in a product, an
+acknowledgment in the product documentation would be appreciated but is not
+required.
+
+2. Altered source versions must be plainly marked as such, and must not be
+misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source distribution.
diff --git a/README.adoc b/README.adoc
new file mode 100644
index 000000000..46ca05775
--- /dev/null
+++ b/README.adoc
@@ -0,0 +1,6 @@
+= Hardware Support Package Template
+
+1. Update LICENSE file
+2. Update `microzig` submodule under `deps/`
+3. Add chips/boards/hals
+4. Set up buildkite pipeline
diff --git a/build.zig b/build.zig
new file mode 100644
index 000000000..3b787fe3f
--- /dev/null
+++ b/build.zig
@@ -0,0 +1,35 @@
+const std = @import("std");
+const microzig = @import("deps/microzig/src/main.zig");
+const boards = @import("src/boards.zig");
+const chips = @import("src/chips.zig");
+
+pub fn build(b: *std.build.Builder) void {
+    const optimize = b.standardOptimizeOption(.{});
+    inline for (@typeInfo(boards).Struct.decls) |decl| {
+        if (!decl.is_pub)
+            continue;
+
+        const exe = microzig.addEmbeddedExecutable(
+            b,
+            @field(boards, decl.name).name ++ ".minimal",
+            "test/programs/minimal.zig",
+            .{ .board = @field(boards, decl.name) },
+            .{ .optimize = optimize },
+        );
+        exe.install();
+    }
+
+    inline for (@typeInfo(chips).Struct.decls) |decl| {
+        if (!decl.is_pub)
+            continue;
+
+        const exe = microzig.addEmbeddedExecutable(
+            b,
+            @field(chips, decl.name).name ++ ".minimal",
+            "test/programs/minimal.zig",
+            .{ .chip = @field(chips, decl.name) },
+            .{ .optimize = optimize },
+        );
+        exe.install();
+    }
+}
diff --git a/deps/microzig b/deps/microzig
new file mode 160000
index 000000000..97ca5497d
--- /dev/null
+++ b/deps/microzig
@@ -0,0 +1 @@
+Subproject commit 97ca5497da0f22d025e18bced9311efed088d893
diff --git a/src/boards.zig b/src/boards.zig
new file mode 100644
index 000000000..2cb647a34
--- /dev/null
+++ b/src/boards.zig
@@ -0,0 +1,6 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/src/main.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse ".";
+}
diff --git a/src/chips.zig b/src/chips.zig
new file mode 100644
index 000000000..2cb647a34
--- /dev/null
+++ b/src/chips.zig
@@ -0,0 +1,6 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/src/main.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse ".";
+}
diff --git a/test/programs/minimal.zig b/test/programs/minimal.zig
new file mode 100644
index 000000000..5258ce311
--- /dev/null
+++ b/test/programs/minimal.zig
@@ -0,0 +1,5 @@
+const micro = @import("microzig");
+
+pub fn main() void {
+    // This function will contain the application logic.
+}

From 29221c27f54ba440e632620ffd3241d74a1ff3b2 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 18 Feb 2023 17:10:04 -0500
Subject: [PATCH 044/286] Initial commit

---
 .buildkite/pipeline.yml   |  4 ++++
 .gitignore                |  2 ++
 .gitmodules               |  3 +++
 LICENSE                   | 19 +++++++++++++++++++
 README.adoc               |  6 ++++++
 build.zig                 | 35 +++++++++++++++++++++++++++++++++++
 deps/microzig             |  1 +
 src/boards.zig            |  6 ++++++
 src/chips.zig             |  6 ++++++
 test/programs/minimal.zig |  5 +++++
 10 files changed, 87 insertions(+)
 create mode 100644 .buildkite/pipeline.yml
 create mode 100644 .gitignore
 create mode 100644 .gitmodules
 create mode 100644 LICENSE
 create mode 100644 README.adoc
 create mode 100644 build.zig
 create mode 160000 deps/microzig
 create mode 100644 src/boards.zig
 create mode 100644 src/chips.zig
 create mode 100644 test/programs/minimal.zig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
new file mode 100644
index 000000000..7767bbb66
--- /dev/null
+++ b/.buildkite/pipeline.yml
@@ -0,0 +1,4 @@
+steps:
+  - group: Build
+    steps:
+    - command: zig build
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 000000000..4c82b07c0
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+zig-cache
+zig-out
diff --git a/.gitmodules b/.gitmodules
new file mode 100644
index 000000000..32e895ccb
--- /dev/null
+++ b/.gitmodules
@@ -0,0 +1,3 @@
+[submodule "deps/microzig"]
+	path = deps/microzig
+	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 000000000..c1cc5ecad
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,19 @@
+Copyright (c) 2022 
+
+This software is provided 'as-is', without any express or implied warranty. In
+no event will the authors be held liable for any damages arising from the use
+of this software.
+
+Permission is granted to anyone to use this software for any purpose, including
+commercial applications, and to alter it and redistribute it freely, subject to
+the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must not claim
+that you wrote the original software. If you use this software in a product, an
+acknowledgment in the product documentation would be appreciated but is not
+required.
+
+2. Altered source versions must be plainly marked as such, and must not be
+misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source distribution.
diff --git a/README.adoc b/README.adoc
new file mode 100644
index 000000000..46ca05775
--- /dev/null
+++ b/README.adoc
@@ -0,0 +1,6 @@
+= Hardware Support Package Template
+
+1. Update LICENSE file
+2. Update `microzig` submodule under `deps/`
+3. Add chips/boards/hals
+4. Set up buildkite pipeline
diff --git a/build.zig b/build.zig
new file mode 100644
index 000000000..3b787fe3f
--- /dev/null
+++ b/build.zig
@@ -0,0 +1,35 @@
+const std = @import("std");
+const microzig = @import("deps/microzig/src/main.zig");
+const boards = @import("src/boards.zig");
+const chips = @import("src/chips.zig");
+
+pub fn build(b: *std.build.Builder) void {
+    const optimize = b.standardOptimizeOption(.{});
+    inline for (@typeInfo(boards).Struct.decls) |decl| {
+        if (!decl.is_pub)
+            continue;
+
+        const exe = microzig.addEmbeddedExecutable(
+            b,
+            @field(boards, decl.name).name ++ ".minimal",
+            "test/programs/minimal.zig",
+            .{ .board = @field(boards, decl.name) },
+            .{ .optimize = optimize },
+        );
+        exe.install();
+    }
+
+    inline for (@typeInfo(chips).Struct.decls) |decl| {
+        if (!decl.is_pub)
+            continue;
+
+        const exe = microzig.addEmbeddedExecutable(
+            b,
+            @field(chips, decl.name).name ++ ".minimal",
+            "test/programs/minimal.zig",
+            .{ .chip = @field(chips, decl.name) },
+            .{ .optimize = optimize },
+        );
+        exe.install();
+    }
+}
diff --git a/deps/microzig b/deps/microzig
new file mode 160000
index 000000000..97ca5497d
--- /dev/null
+++ b/deps/microzig
@@ -0,0 +1 @@
+Subproject commit 97ca5497da0f22d025e18bced9311efed088d893
diff --git a/src/boards.zig b/src/boards.zig
new file mode 100644
index 000000000..2cb647a34
--- /dev/null
+++ b/src/boards.zig
@@ -0,0 +1,6 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/src/main.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse ".";
+}
diff --git a/src/chips.zig b/src/chips.zig
new file mode 100644
index 000000000..2cb647a34
--- /dev/null
+++ b/src/chips.zig
@@ -0,0 +1,6 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/src/main.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse ".";
+}
diff --git a/test/programs/minimal.zig b/test/programs/minimal.zig
new file mode 100644
index 000000000..5258ce311
--- /dev/null
+++ b/test/programs/minimal.zig
@@ -0,0 +1,5 @@
+const micro = @import("microzig");
+
+pub fn main() void {
+    // This function will contain the application logic.
+}

From 5fb80ada81470de26b3cdb99707d62fd5c68c027 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 18 Feb 2023 17:48:31 -0500
Subject: [PATCH 045/286] add chips and boards (#1)

---
 .buildkite/pipeline.yml     |    2 +-
 LICENSE                     |    2 +-
 README.adoc                 |   22 +-
 deps/microzig               |    2 +-
 src/boards.zig              |   17 +-
 src/boards/arduino_nano.zig |   33 +
 src/boards/arduino_uno.zig  |   32 +
 src/chips.zig               |   13 +-
 src/chips/ATmega328P.json   | 2947 +++++++++++++++++++++++++++++++++++
 src/chips/ATmega328P.zig    | 1388 +++++++++++++++++
 src/hals/ATmega328P.zig     |  191 +++
 11 files changed, 4638 insertions(+), 11 deletions(-)
 create mode 100644 src/boards/arduino_nano.zig
 create mode 100644 src/boards/arduino_uno.zig
 create mode 100644 src/chips/ATmega328P.json
 create mode 100644 src/chips/ATmega328P.zig
 create mode 100644 src/hals/ATmega328P.zig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
index 7767bbb66..24d964669 100644
--- a/.buildkite/pipeline.yml
+++ b/.buildkite/pipeline.yml
@@ -1,4 +1,4 @@
 steps:
   - group: Build
     steps:
-    - command: zig build
+    - command: zig build -Doptimize=ReleaseSmall
diff --git a/LICENSE b/LICENSE
index c1cc5ecad..bcb425d88 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,4 +1,4 @@
-Copyright (c) 2022 
+Copyright (c) 2022 Zig Embedded Group Contributors
 
 This software is provided 'as-is', without any express or implied warranty. In
 no event will the authors be held liable for any damages arising from the use
diff --git a/README.adoc b/README.adoc
index 46ca05775..f4214f4b0 100644
--- a/README.adoc
+++ b/README.adoc
@@ -1,6 +1,18 @@
-= Hardware Support Package Template
+= Microchip ATmega Hardware Support Package
 
-1. Update LICENSE file
-2. Update `microzig` submodule under `deps/`
-3. Add chips/boards/hals
-4. Set up buildkite pipeline
+Note: for testing, renode supports arduino nano 33 BLE
+
+Currently LLVM is having trouble lowering AVR when this is built in debug mode:
+
+[source]
+----
+LLVM Emit Object... Don't know how to custom lower this!
+UNREACHABLE executed at /Users/mattnite/code/llvm-project-15/llvm/lib/Target/AVR/AVRISelLowering.cpp:842!
+----
+
+for now always build in release small:
+
+[source]
+----
+zig build -Doptimize=ReleaseSmall
+----
diff --git a/deps/microzig b/deps/microzig
index 97ca5497d..2d0ee5c47 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 97ca5497da0f22d025e18bced9311efed088d893
+Subproject commit 2d0ee5c4731de1d81afb9c8e08ba4e8c2c2cfbf3
diff --git a/src/boards.zig b/src/boards.zig
index 2cb647a34..928877039 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -1,6 +1,19 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/src/main.zig");
+const chips = @import("chips.zig");
 
 fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse ".";
+    return std.fs.path.dirname(@src().file) orelse unreachable;
 }
+
+pub const arduino_nano = micro.Board{
+    .name = "Arduino Nano",
+    .source = .{ .path = root_dir() ++ "/boards/arduino_nano.zig" },
+    .chip = chips.atmega328p,
+};
+
+pub const arduino_uno = micro.Board{
+    .name = "Arduino Uno",
+    .source = .{ .path = root_dir() ++ "/boards/arduino_uno.zig" },
+    .chip = chips.atmega328p,
+};
diff --git a/src/boards/arduino_nano.zig b/src/boards/arduino_nano.zig
new file mode 100644
index 000000000..96490f87a
--- /dev/null
+++ b/src/boards/arduino_nano.zig
@@ -0,0 +1,33 @@
+pub const chip = @import("chip");
+
+pub const clock_frequencies = .{
+    .cpu = 16_000_000,
+};
+
+pub const pin_map = .{
+    // Port A
+    .D0 = "PD0",
+    .D1 = "PD1",
+    .D2 = "PD2",
+    .D3 = "PD3",
+    .D4 = "PD4",
+    .D5 = "PD5",
+    .D6 = "PD6",
+    .D7 = "PD7",
+    // Port B
+    .D8 = "PB0",
+    .D9 = "PB1",
+    .D10 = "PB2",
+    .D11 = "PB3",
+    .D12 = "PB4",
+    .D13 = "PB5",
+    // Port C (Analog)
+    .A0 = "PC0",
+    .A1 = "PC1",
+    .A2 = "PC2",
+    .A3 = "PC3",
+    .A4 = "PC4",
+    .A5 = "PC5",
+    .A6 = "ADC6",
+    .A7 = "ADC7",
+};
diff --git a/src/boards/arduino_uno.zig b/src/boards/arduino_uno.zig
new file mode 100644
index 000000000..9dd729c0d
--- /dev/null
+++ b/src/boards/arduino_uno.zig
@@ -0,0 +1,32 @@
+pub const chip = @import("chip");
+
+pub const clock_frequencies = .{
+    .cpu = 16_000_000,
+};
+
+pub const pin_map = .{
+    // Port D
+    .D0 = "PD0",
+    .D1 = "PD1",
+    .D2 = "PD2",
+    .D3 = "PD3",
+    .D4 = "PD4",
+    .D5 = "PD5",
+    .D6 = "PD6",
+    .D7 = "PD7",
+    // Port B
+    .D8 = "PB0",
+    .D9 = "PB1",
+    .D10 = "PB2",
+    .D11 = "PB3",
+    .D12 = "PB4",
+    // LED_BUILTIN
+    .D13 = "PB5",
+    // Port C (Analog)
+    .A0 = "PC0",
+    .A1 = "PC1",
+    .A2 = "PC2",
+    .A3 = "PC3",
+    .A4 = "PC4",
+    .A5 = "PC5",
+};
diff --git a/src/chips.zig b/src/chips.zig
index 2cb647a34..b47fe15ec 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,6 +1,17 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/src/main.zig");
+const Chip = micro.Chip;
+const MemoryRegion = micro.MemoryRegion;
 
 fn root_dir() []const u8 {
     return std.fs.path.dirname(@src().file) orelse ".";
 }
+
+pub const atmega328p = Chip.from_standard_paths(root_dir(), .{
+    .name = "ATmega328P",
+    .cpu = micro.cpus.avr5,
+    .memory_regions = &.{
+        MemoryRegion{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash },
+        MemoryRegion{ .offset = 0x800100, .length = 2048, .kind = .ram },
+    },
+});
diff --git a/src/chips/ATmega328P.json b/src/chips/ATmega328P.json
new file mode 100644
index 000000000..7baa55cae
--- /dev/null
+++ b/src/chips/ATmega328P.json
@@ -0,0 +1,2947 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "FUSE": {
+        "description": "Fuses",
+        "children": {
+          "registers": {
+            "EXTENDED": {
+              "offset": 2,
+              "size": 8,
+              "reset_value": 255,
+              "children": {
+                "fields": {
+                  "BODLEVEL": {
+                    "description": "Brown-out Detector trigger level",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": "types.peripherals.FUSE.children.enums.ENUM_BODLEVEL"
+                  }
+                }
+              }
+            },
+            "HIGH": {
+              "offset": 1,
+              "size": 8,
+              "reset_value": 217,
+              "children": {
+                "fields": {
+                  "RSTDISBL": {
+                    "description": "Reset Disabled (Enable PC6 as i/o pin)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DWEN": {
+                    "description": "Debug Wire enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SPIEN": {
+                    "description": "Serial program downloading (SPI) enabled",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WDTON": {
+                    "description": "Watch-dog Timer always on",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EESAVE": {
+                    "description": "Preserve EEPROM through the Chip Erase cycle",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BOOTSZ": {
+                    "description": "Select boot size",
+                    "offset": 1,
+                    "size": 2,
+                    "enum": "types.peripherals.FUSE.children.enums.ENUM_BOOTSZ"
+                  },
+                  "BOOTRST": {
+                    "description": "Boot Reset vector Enabled",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LOW": {
+              "offset": 0,
+              "size": 8,
+              "reset_value": 98,
+              "children": {
+                "fields": {
+                  "CKDIV8": {
+                    "description": "Divide clock by 8 internally",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CKOUT": {
+                    "description": "Clock output on PORTB0",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SUT_CKSEL": {
+                    "description": "Select Clock Source",
+                    "offset": 0,
+                    "size": 6,
+                    "enum": "types.peripherals.FUSE.children.enums.ENUM_SUT_CKSEL"
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "ENUM_SUT_CKSEL": {
+              "size": 6,
+              "children": {
+                "enum_fields": {
+                  "EXTCLK_6CK_14CK_0MS": {
+                    "description": "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms",
+                    "value": 0
+                  },
+                  "EXTCLK_6CK_14CK_4MS1": {
+                    "description": "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms",
+                    "value": 16
+                  },
+                  "EXTCLK_6CK_14CK_65MS": {
+                    "description": "Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms",
+                    "value": 32
+                  },
+                  "INTRCOSC_8MHZ_6CK_14CK_0MS": {
+                    "description": "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms",
+                    "value": 2
+                  },
+                  "INTRCOSC_8MHZ_6CK_14CK_4MS1": {
+                    "description": "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms",
+                    "value": 18
+                  },
+                  "INTRCOSC_8MHZ_6CK_14CK_65MS": {
+                    "description": "Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms",
+                    "value": 34
+                  },
+                  "INTRCOSC_128KHZ_6CK_14CK_0MS": {
+                    "description": "Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms",
+                    "value": 3
+                  },
+                  "INTRCOSC_128KHZ_6CK_14CK_4MS1": {
+                    "description": "Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms",
+                    "value": 19
+                  },
+                  "INTRCOSC_128KHZ_6CK_14CK_65MS": {
+                    "description": "Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms",
+                    "value": 35
+                  },
+                  "EXTLOFXTAL_1KCK_14CK_0MS": {
+                    "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms",
+                    "value": 4
+                  },
+                  "EXTLOFXTAL_1KCK_14CK_4MS1": {
+                    "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms",
+                    "value": 20
+                  },
+                  "EXTLOFXTAL_1KCK_14CK_65MS": {
+                    "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms",
+                    "value": 36
+                  },
+                  "EXTLOFXTAL_32KCK_14CK_0MS": {
+                    "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms",
+                    "value": 5
+                  },
+                  "EXTLOFXTAL_32KCK_14CK_4MS1": {
+                    "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms",
+                    "value": 21
+                  },
+                  "EXTLOFXTAL_32KCK_14CK_65MS": {
+                    "description": "Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms",
+                    "value": 37
+                  },
+                  "EXTFSXTAL_258CK_14CK_4MS1": {
+                    "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms",
+                    "value": 6
+                  },
+                  "EXTFSXTAL_258CK_14CK_65MS": {
+                    "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms",
+                    "value": 22
+                  },
+                  "EXTFSXTAL_1KCK_14CK_0MS": {
+                    "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms",
+                    "value": 38
+                  },
+                  "EXTFSXTAL_1KCK_14CK_4MS1": {
+                    "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms",
+                    "value": 54
+                  },
+                  "EXTFSXTAL_1KCK_14CK_65MS": {
+                    "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms",
+                    "value": 7
+                  },
+                  "EXTFSXTAL_16KCK_14CK_0MS": {
+                    "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms",
+                    "value": 23
+                  },
+                  "EXTFSXTAL_16KCK_14CK_4MS1": {
+                    "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms",
+                    "value": 39
+                  },
+                  "EXTFSXTAL_16KCK_14CK_65MS": {
+                    "description": "Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms",
+                    "value": 55
+                  },
+                  "EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms",
+                    "value": 8
+                  },
+                  "EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms",
+                    "value": 24
+                  },
+                  "EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS": {
+                    "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms",
+                    "value": 40
+                  },
+                  "EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms",
+                    "value": 56
+                  },
+                  "EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms",
+                    "value": 9
+                  },
+                  "EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS": {
+                    "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms",
+                    "value": 25
+                  },
+                  "EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms",
+                    "value": 41
+                  },
+                  "EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms",
+                    "value": 57
+                  },
+                  "EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms",
+                    "value": 10
+                  },
+                  "EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms",
+                    "value": 26
+                  },
+                  "EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS": {
+                    "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms",
+                    "value": 42
+                  },
+                  "EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms",
+                    "value": 58
+                  },
+                  "EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms",
+                    "value": 11
+                  },
+                  "EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS": {
+                    "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms",
+                    "value": 27
+                  },
+                  "EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms",
+                    "value": 43
+                  },
+                  "EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms",
+                    "value": 59
+                  },
+                  "EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms",
+                    "value": 12
+                  },
+                  "EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms",
+                    "value": 28
+                  },
+                  "EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS": {
+                    "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms",
+                    "value": 44
+                  },
+                  "EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms",
+                    "value": 60
+                  },
+                  "EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms",
+                    "value": 13
+                  },
+                  "EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS": {
+                    "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms",
+                    "value": 29
+                  },
+                  "EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms",
+                    "value": 45
+                  },
+                  "EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms",
+                    "value": 61
+                  },
+                  "EXTXOSC_8MHZ_XX_258CK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 8.0-    MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms",
+                    "value": 14
+                  },
+                  "EXTXOSC_8MHZ_XX_258CK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 8.0-    MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms",
+                    "value": 30
+                  },
+                  "EXTXOSC_8MHZ_XX_1KCK_14CK_0MS": {
+                    "description": "Ext. Crystal Osc. 8.0-    MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms",
+                    "value": 46
+                  },
+                  "EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 8.0-    MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms",
+                    "value": 62
+                  },
+                  "EXTXOSC_8MHZ_XX_1KCK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 8.0-    MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms",
+                    "value": 15
+                  },
+                  "EXTXOSC_8MHZ_XX_16KCK_14CK_0MS": {
+                    "description": "Ext. Crystal Osc. 8.0-    MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms",
+                    "value": 31
+                  },
+                  "EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1": {
+                    "description": "Ext. Crystal Osc. 8.0-    MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms",
+                    "value": 47
+                  },
+                  "EXTXOSC_8MHZ_XX_16KCK_14CK_65MS": {
+                    "description": "Ext. Crystal Osc. 8.0-    MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms",
+                    "value": 63
+                  }
+                }
+              }
+            },
+            "ENUM_BODLEVEL": {
+              "size": 3,
+              "children": {
+                "enum_fields": {
+                  "4V3": {
+                    "description": "Brown-out detection at VCC=4.3 V",
+                    "value": 4
+                  },
+                  "2V7": {
+                    "description": "Brown-out detection at VCC=2.7 V",
+                    "value": 5
+                  },
+                  "1V8": {
+                    "description": "Brown-out detection at VCC=1.8 V",
+                    "value": 6
+                  },
+                  "DISABLED": {
+                    "description": "Brown-out detection disabled",
+                    "value": 7
+                  }
+                }
+              }
+            },
+            "ENUM_BOOTSZ": {
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "256W_3F00": {
+                    "description": "Boot Flash size=256 words start address=$3F00",
+                    "value": 3
+                  },
+                  "512W_3E00": {
+                    "description": "Boot Flash size=512 words start address=$3E00",
+                    "value": 2
+                  },
+                  "1024W_3C00": {
+                    "description": "Boot Flash size=1024 words start address=$3C00",
+                    "value": 1
+                  },
+                  "2048W_3800": {
+                    "description": "Boot Flash size=2048 words start address=$3800",
+                    "value": 0
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "LOCKBIT": {
+        "description": "Lockbits",
+        "children": {
+          "registers": {
+            "LOCKBIT": {
+              "offset": 0,
+              "size": 8,
+              "reset_value": 255,
+              "children": {
+                "fields": {
+                  "LB": {
+                    "description": "Memory Lock",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": "types.peripherals.LOCKBIT.children.enums.ENUM_LB"
+                  },
+                  "BLB0": {
+                    "description": "Boot Loader Protection Mode",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": "types.peripherals.LOCKBIT.children.enums.ENUM_BLB"
+                  },
+                  "BLB1": {
+                    "description": "Boot Loader Protection Mode",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": "types.peripherals.LOCKBIT.children.enums.ENUM_BLB2"
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "ENUM_LB": {
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "PROG_VER_DISABLED": {
+                    "description": "Further programming and verification disabled",
+                    "value": 0
+                  },
+                  "PROG_DISABLED": {
+                    "description": "Further programming disabled",
+                    "value": 2
+                  },
+                  "NO_LOCK": {
+                    "description": "No memory lock features enabled",
+                    "value": 3
+                  }
+                }
+              }
+            },
+            "ENUM_BLB": {
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "LPM_SPM_DISABLE": {
+                    "description": "LPM and SPM prohibited in Application Section",
+                    "value": 0
+                  },
+                  "LPM_DISABLE": {
+                    "description": "LPM prohibited in Application Section",
+                    "value": 1
+                  },
+                  "SPM_DISABLE": {
+                    "description": "SPM prohibited in Application Section",
+                    "value": 2
+                  },
+                  "NO_LOCK": {
+                    "description": "No lock on SPM and LPM in Application Section",
+                    "value": 3
+                  }
+                }
+              }
+            },
+            "ENUM_BLB2": {
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "LPM_SPM_DISABLE": {
+                    "description": "LPM and SPM prohibited in Boot Section",
+                    "value": 0
+                  },
+                  "LPM_DISABLE": {
+                    "description": "LPM prohibited in Boot Section",
+                    "value": 1
+                  },
+                  "SPM_DISABLE": {
+                    "description": "SPM prohibited in Boot Section",
+                    "value": 2
+                  },
+                  "NO_LOCK": {
+                    "description": "No lock on SPM and LPM in Boot Section",
+                    "value": 3
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USART": {
+        "description": "USART",
+        "children": {
+          "register_groups": {
+            "USART0": {
+              "description": "USART",
+              "children": {
+                "registers": {
+                  "UDR0": {
+                    "description": "USART I/O Data Register",
+                    "offset": 6,
+                    "size": 8
+                  },
+                  "UCSR0A": {
+                    "description": "USART Control and Status Register A",
+                    "offset": 0,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "RXC0": {
+                          "description": "USART Receive Complete",
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "TXC0": {
+                          "description": "USART Transmitt Complete",
+                          "offset": 6,
+                          "size": 1
+                        },
+                        "UDRE0": {
+                          "description": "USART Data Register Empty",
+                          "offset": 5,
+                          "size": 1
+                        },
+                        "FE0": {
+                          "description": "Framing Error",
+                          "offset": 4,
+                          "size": 1
+                        },
+                        "DOR0": {
+                          "description": "Data overRun",
+                          "offset": 3,
+                          "size": 1
+                        },
+                        "UPE0": {
+                          "description": "Parity Error",
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "U2X0": {
+                          "description": "Double the USART transmission speed",
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "MPCM0": {
+                          "description": "Multi-processor Communication Mode",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "UCSR0B": {
+                    "description": "USART Control and Status Register B",
+                    "offset": 1,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "RXCIE0": {
+                          "description": "RX Complete Interrupt Enable",
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "TXCIE0": {
+                          "description": "TX Complete Interrupt Enable",
+                          "offset": 6,
+                          "size": 1
+                        },
+                        "UDRIE0": {
+                          "description": "USART Data register Empty Interrupt Enable",
+                          "offset": 5,
+                          "size": 1
+                        },
+                        "RXEN0": {
+                          "description": "Receiver Enable",
+                          "offset": 4,
+                          "size": 1
+                        },
+                        "TXEN0": {
+                          "description": "Transmitter Enable",
+                          "offset": 3,
+                          "size": 1
+                        },
+                        "UCSZ02": {
+                          "description": "Character Size - together with UCSZ0 in UCSR0C",
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "RXB80": {
+                          "description": "Receive Data Bit 8",
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TXB80": {
+                          "description": "Transmit Data Bit 8",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "UCSR0C": {
+                    "description": "USART Control and Status Register C",
+                    "offset": 2,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "UMSEL0": {
+                          "description": "USART Mode Select",
+                          "offset": 6,
+                          "size": 2,
+                          "enum": "types.peripherals.USART.children.enums.COMM_USART_MODE_2BIT"
+                        },
+                        "UPM0": {
+                          "description": "Parity Mode Bits",
+                          "offset": 4,
+                          "size": 2,
+                          "enum": "types.peripherals.USART.children.enums.COMM_UPM_PARITY_MODE"
+                        },
+                        "USBS0": {
+                          "description": "Stop Bit Select",
+                          "offset": 3,
+                          "size": 1,
+                          "enum": "types.peripherals.USART.children.enums.COMM_STOP_BIT_SEL"
+                        },
+                        "UCSZ0": {
+                          "description": "Character Size - together with UCSZ2 in UCSR0B",
+                          "offset": 1,
+                          "size": 2
+                        },
+                        "UCPOL0": {
+                          "description": "Clock Polarity",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "UBRR0": {
+                    "description": "USART Baud Rate Register Bytes",
+                    "offset": 4,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "COMM_USART_MODE_2BIT": {
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "ASYNCHRONOUS_USART": {
+                    "description": "Asynchronous USART",
+                    "value": 0
+                  },
+                  "SYNCHRONOUS_USART": {
+                    "description": "Synchronous USART",
+                    "value": 1
+                  },
+                  "MASTER_SPI": {
+                    "description": "Master SPI",
+                    "value": 3
+                  }
+                }
+              }
+            },
+            "COMM_UPM_PARITY_MODE": {
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "DISABLED": {
+                    "description": "Disabled",
+                    "value": 0
+                  },
+                  "RESERVED": {
+                    "description": "Reserved",
+                    "value": 1
+                  },
+                  "ENABLED_EVEN_PARITY": {
+                    "description": "Enabled, Even Parity",
+                    "value": 2
+                  },
+                  "ENABLED_ODD_PARITY": {
+                    "description": "Enabled, Odd Parity",
+                    "value": 3
+                  }
+                }
+              }
+            },
+            "COMM_STOP_BIT_SEL": {
+              "size": 1,
+              "children": {
+                "enum_fields": {
+                  "1_BIT": {
+                    "description": "1-bit",
+                    "value": 0
+                  },
+                  "2_BIT": {
+                    "description": "2-bit",
+                    "value": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TWI": {
+        "description": "Two Wire Serial Interface",
+        "children": {
+          "registers": {
+            "TWAMR": {
+              "description": "TWI (Slave) Address Mask Register",
+              "offset": 5,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "TWAM": {
+                    "offset": 1,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "TWBR": {
+              "description": "TWI Bit Rate register",
+              "offset": 0,
+              "size": 8
+            },
+            "TWCR": {
+              "description": "TWI Control Register",
+              "offset": 4,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "TWINT": {
+                    "description": "TWI Interrupt Flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TWEA": {
+                    "description": "TWI Enable Acknowledge Bit",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TWSTA": {
+                    "description": "TWI Start Condition Bit",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TWSTO": {
+                    "description": "TWI Stop Condition Bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TWWC": {
+                    "description": "TWI Write Collition Flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TWEN": {
+                    "description": "TWI Enable Bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TWIE": {
+                    "description": "TWI Interrupt Enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TWSR": {
+              "description": "TWI Status Register",
+              "offset": 1,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "TWS": {
+                    "description": "TWI Status",
+                    "offset": 3,
+                    "size": 5
+                  },
+                  "TWPS": {
+                    "description": "TWI Prescaler",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": "types.peripherals.TWI.children.enums.COMM_TWI_PRESACLE"
+                  }
+                }
+              }
+            },
+            "TWDR": {
+              "description": "TWI Data register",
+              "offset": 3,
+              "size": 8
+            },
+            "TWAR": {
+              "description": "TWI (Slave) Address register",
+              "offset": 2,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "TWA": {
+                    "description": "TWI (Slave) Address register Bits",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "TWGCE": {
+                    "description": "TWI General Call Recognition Enable Bit",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "COMM_TWI_PRESACLE": {
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "1": {
+                    "description": "1",
+                    "value": 0
+                  },
+                  "4": {
+                    "description": "4",
+                    "value": 1
+                  },
+                  "16": {
+                    "description": "16",
+                    "value": 2
+                  },
+                  "64": {
+                    "description": "64",
+                    "value": 3
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TC16": {
+        "description": "Timer/Counter, 16-bit",
+        "children": {
+          "register_groups": {
+            "TC1": {
+              "description": "Timer/Counter, 16-bit",
+              "children": {
+                "registers": {
+                  "TIMSK1": {
+                    "description": "Timer/Counter Interrupt Mask Register",
+                    "offset": 57,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "ICIE1": {
+                          "description": "Timer/Counter1 Input Capture Interrupt Enable",
+                          "offset": 5,
+                          "size": 1
+                        },
+                        "OCIE1B": {
+                          "description": "Timer/Counter1 Output CompareB Match Interrupt Enable",
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "OCIE1A": {
+                          "description": "Timer/Counter1 Output CompareA Match Interrupt Enable",
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TOIE1": {
+                          "description": "Timer/Counter1 Overflow Interrupt Enable",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "TIFR1": {
+                    "description": "Timer/Counter Interrupt Flag register",
+                    "offset": 0,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "ICF1": {
+                          "description": "Input Capture Flag 1",
+                          "offset": 5,
+                          "size": 1
+                        },
+                        "OCF1B": {
+                          "description": "Output Compare Flag 1B",
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "OCF1A": {
+                          "description": "Output Compare Flag 1A",
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TOV1": {
+                          "description": "Timer/Counter1 Overflow Flag",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "TCCR1A": {
+                    "description": "Timer/Counter1 Control Register A",
+                    "offset": 74,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "COM1A": {
+                          "description": "Compare Output Mode 1A, bits",
+                          "offset": 6,
+                          "size": 2
+                        },
+                        "COM1B": {
+                          "description": "Compare Output Mode 1B, bits",
+                          "offset": 4,
+                          "size": 2
+                        },
+                        "WGM1": {
+                          "description": "Waveform Generation Mode",
+                          "offset": 0,
+                          "size": 2
+                        }
+                      }
+                    }
+                  },
+                  "TCCR1B": {
+                    "description": "Timer/Counter1 Control Register B",
+                    "offset": 75,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "ICNC1": {
+                          "description": "Input Capture 1 Noise Canceler",
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "ICES1": {
+                          "description": "Input Capture 1 Edge Select",
+                          "offset": 6,
+                          "size": 1
+                        },
+                        "WGM1": {
+                          "description": "Waveform Generation Mode",
+                          "offset": 3,
+                          "size": 2
+                        },
+                        "CS1": {
+                          "description": "Prescaler source of Timer/Counter 1",
+                          "offset": 0,
+                          "size": 3,
+                          "enum": "types.peripherals.TC16.children.enums.CLK_SEL_3BIT_EXT"
+                        }
+                      }
+                    }
+                  },
+                  "TCCR1C": {
+                    "description": "Timer/Counter1 Control Register C",
+                    "offset": 76,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "FOC1A": {
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "FOC1B": {
+                          "offset": 6,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "TCNT1": {
+                    "description": "Timer/Counter1  Bytes",
+                    "offset": 78,
+                    "size": 16
+                  },
+                  "OCR1A": {
+                    "description": "Timer/Counter1 Output Compare Register  Bytes",
+                    "offset": 82,
+                    "size": 16
+                  },
+                  "OCR1B": {
+                    "description": "Timer/Counter1 Output Compare Register  Bytes",
+                    "offset": 84,
+                    "size": 16
+                  },
+                  "ICR1": {
+                    "description": "Timer/Counter1 Input Capture Register  Bytes",
+                    "offset": 80,
+                    "size": 16
+                  },
+                  "GTCCR": {
+                    "description": "General Timer/Counter Control Register",
+                    "offset": 13,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "TSM": {
+                          "description": "Timer/Counter Synchronization Mode",
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "PSRSYNC": {
+                          "description": "Prescaler Reset Timer/Counter1 and Timer/Counter0",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "CLK_SEL_3BIT_EXT": {
+              "size": 3,
+              "children": {
+                "enum_fields": {
+                  "NO_CLOCK_SOURCE_STOPPED": {
+                    "description": "No Clock Source (Stopped)",
+                    "value": 0
+                  },
+                  "RUNNING_NO_PRESCALING": {
+                    "description": "Running, No Prescaling",
+                    "value": 1
+                  },
+                  "RUNNING_CLK_8": {
+                    "description": "Running, CLK/8",
+                    "value": 2
+                  },
+                  "RUNNING_CLK_64": {
+                    "description": "Running, CLK/64",
+                    "value": 3
+                  },
+                  "RUNNING_CLK_256": {
+                    "description": "Running, CLK/256",
+                    "value": 4
+                  },
+                  "RUNNING_CLK_1024": {
+                    "description": "Running, CLK/1024",
+                    "value": 5
+                  },
+                  "RUNNING_EXTCLK_TN_FALLING_EDGE": {
+                    "description": "Running, ExtClk Tn Falling Edge",
+                    "value": 6
+                  },
+                  "RUNNING_EXTCLK_TN_RISING_EDGE": {
+                    "description": "Running, ExtClk Tn Rising Edge",
+                    "value": 7
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TC8_ASYNC": {
+        "description": "Timer/Counter, 8-bit Async",
+        "children": {
+          "register_groups": {
+            "TC2": {
+              "description": "Timer/Counter, 8-bit Async",
+              "children": {
+                "registers": {
+                  "TIMSK2": {
+                    "description": "Timer/Counter Interrupt Mask register",
+                    "offset": 57,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "OCIE2B": {
+                          "description": "Timer/Counter2 Output Compare Match B Interrupt Enable",
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "OCIE2A": {
+                          "description": "Timer/Counter2 Output Compare Match A Interrupt Enable",
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TOIE2": {
+                          "description": "Timer/Counter2 Overflow Interrupt Enable",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "TIFR2": {
+                    "description": "Timer/Counter Interrupt Flag Register",
+                    "offset": 0,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "OCF2B": {
+                          "description": "Output Compare Flag 2B",
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "OCF2A": {
+                          "description": "Output Compare Flag 2A",
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TOV2": {
+                          "description": "Timer/Counter2 Overflow Flag",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "TCCR2A": {
+                    "description": "Timer/Counter2 Control Register A",
+                    "offset": 121,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "COM2A": {
+                          "description": "Compare Output Mode bits",
+                          "offset": 6,
+                          "size": 2
+                        },
+                        "COM2B": {
+                          "description": "Compare Output Mode bits",
+                          "offset": 4,
+                          "size": 2
+                        },
+                        "WGM2": {
+                          "description": "Waveform Genration Mode",
+                          "offset": 0,
+                          "size": 2
+                        }
+                      }
+                    }
+                  },
+                  "TCCR2B": {
+                    "description": "Timer/Counter2 Control Register B",
+                    "offset": 122,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "FOC2A": {
+                          "description": "Force Output Compare A",
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "FOC2B": {
+                          "description": "Force Output Compare B",
+                          "offset": 6,
+                          "size": 1
+                        },
+                        "WGM22": {
+                          "description": "Waveform Generation Mode",
+                          "offset": 3,
+                          "size": 1
+                        },
+                        "CS2": {
+                          "description": "Clock Select bits",
+                          "offset": 0,
+                          "size": 3,
+                          "enum": "types.peripherals.TC8_ASYNC.children.enums.CLK_SEL_3BIT"
+                        }
+                      }
+                    }
+                  },
+                  "TCNT2": {
+                    "description": "Timer/Counter2",
+                    "offset": 123,
+                    "size": 8
+                  },
+                  "OCR2B": {
+                    "description": "Timer/Counter2 Output Compare Register B",
+                    "offset": 125,
+                    "size": 8
+                  },
+                  "OCR2A": {
+                    "description": "Timer/Counter2 Output Compare Register A",
+                    "offset": 124,
+                    "size": 8
+                  },
+                  "ASSR": {
+                    "description": "Asynchronous Status Register",
+                    "offset": 127,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "EXCLK": {
+                          "description": "Enable External Clock Input",
+                          "offset": 6,
+                          "size": 1
+                        },
+                        "AS2": {
+                          "description": "Asynchronous Timer/Counter2",
+                          "offset": 5,
+                          "size": 1
+                        },
+                        "TCN2UB": {
+                          "description": "Timer/Counter2 Update Busy",
+                          "offset": 4,
+                          "size": 1
+                        },
+                        "OCR2AUB": {
+                          "description": "Output Compare Register2 Update Busy",
+                          "offset": 3,
+                          "size": 1
+                        },
+                        "OCR2BUB": {
+                          "description": "Output Compare Register 2 Update Busy",
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "TCR2AUB": {
+                          "description": "Timer/Counter Control Register2 Update Busy",
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TCR2BUB": {
+                          "description": "Timer/Counter Control Register2 Update Busy",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "GTCCR": {
+                    "description": "General Timer Counter Control register",
+                    "offset": 12,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "TSM": {
+                          "description": "Timer/Counter Synchronization Mode",
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "PSRASY": {
+                          "description": "Prescaler Reset Timer/Counter2",
+                          "offset": 1,
+                          "size": 1
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "CLK_SEL_3BIT": {
+              "size": 3,
+              "children": {
+                "enum_fields": {
+                  "NO_CLOCK_SOURCE_STOPPED": {
+                    "description": "No Clock Source (Stopped)",
+                    "value": 0
+                  },
+                  "RUNNING_NO_PRESCALING": {
+                    "description": "Running, No Prescaling",
+                    "value": 1
+                  },
+                  "RUNNING_CLK_8": {
+                    "description": "Running, CLK/8",
+                    "value": 2
+                  },
+                  "RUNNING_CLK_32": {
+                    "description": "Running, CLK/32",
+                    "value": 3
+                  },
+                  "RUNNING_CLK_64": {
+                    "description": "Running, CLK/64",
+                    "value": 4
+                  },
+                  "RUNNING_CLK_128": {
+                    "description": "Running, CLK/128",
+                    "value": 5
+                  },
+                  "RUNNING_CLK_256": {
+                    "description": "Running, CLK/256",
+                    "value": 6
+                  },
+                  "RUNNING_CLK_1024": {
+                    "description": "Running, CLK/1024",
+                    "value": 7
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ADC": {
+        "description": "Analog-to-Digital Converter",
+        "children": {
+          "registers": {
+            "ADMUX": {
+              "description": "The ADC multiplexer Selection Register",
+              "offset": 4,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "REFS": {
+                    "description": "Reference Selection Bits",
+                    "offset": 6,
+                    "size": 2,
+                    "enum": "types.peripherals.ADC.children.enums.ANALOG_ADC_V_REF3"
+                  },
+                  "ADLAR": {
+                    "description": "Left Adjust Result",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MUX": {
+                    "description": "Analog Channel Selection Bits",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": "types.peripherals.ADC.children.enums.ADC_MUX_SINGLE"
+                  }
+                }
+              }
+            },
+            "ADC": {
+              "description": "ADC Data Register  Bytes",
+              "offset": 0,
+              "size": 16
+            },
+            "ADCSRA": {
+              "description": "The ADC Control and Status register A",
+              "offset": 2,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "ADEN": {
+                    "description": "ADC Enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ADSC": {
+                    "description": "ADC Start Conversion",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ADATE": {
+                    "description": "ADC  Auto Trigger Enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADIF": {
+                    "description": "ADC Interrupt Flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ADIE": {
+                    "description": "ADC Interrupt Enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ADPS": {
+                    "description": "ADC  Prescaler Select Bits",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": "types.peripherals.ADC.children.enums.ANALOG_ADC_PRESCALER"
+                  }
+                }
+              }
+            },
+            "ADCSRB": {
+              "description": "The ADC Control and Status register B",
+              "offset": 3,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "ACME": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ADTS": {
+                    "description": "ADC Auto Trigger Source bits",
+                    "offset": 0,
+                    "size": 3,
+                    "enum": "types.peripherals.ADC.children.enums.ANALOG_ADC_AUTO_TRIGGER"
+                  }
+                }
+              }
+            },
+            "DIDR0": {
+              "description": "Digital Input Disable Register",
+              "offset": 6,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "ADC5D": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADC4D": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ADC3D": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ADC2D": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ADC1D": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ADC0D": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "ANALOG_ADC_V_REF3": {
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "AREF_INTERNAL_VREF_TURNED_OFF": {
+                    "description": "AREF, Internal Vref turned off",
+                    "value": 0
+                  },
+                  "AVCC_WITH_EXTERNAL_CAPACITOR_AT_AREF_PIN": {
+                    "description": "AVCC with external capacitor at AREF pin",
+                    "value": 1
+                  },
+                  "RESERVED": {
+                    "description": "Reserved",
+                    "value": 2
+                  },
+                  "INTERNAL_1_1V_VOLTAGE_REFERENCE_WITH_EXTERNAL_CAPACITOR_AT_AREF_PIN": {
+                    "description": "Internal 1.1V Voltage Reference with external capacitor at AREF pin",
+                    "value": 3
+                  }
+                }
+              }
+            },
+            "ADC_MUX_SINGLE": {
+              "size": 4,
+              "children": {
+                "enum_fields": {
+                  "ADC0": {
+                    "description": "ADC Single Ended Input pin 0",
+                    "value": 0
+                  },
+                  "ADC1": {
+                    "description": "ADC Single Ended Input pin 1",
+                    "value": 1
+                  },
+                  "ADC2": {
+                    "description": "ADC Single Ended Input pin 2",
+                    "value": 2
+                  },
+                  "ADC3": {
+                    "description": "ADC Single Ended Input pin 3",
+                    "value": 3
+                  },
+                  "ADC4": {
+                    "description": "ADC Single Ended Input pin 4",
+                    "value": 4
+                  },
+                  "ADC5": {
+                    "description": "ADC Single Ended Input pin 5",
+                    "value": 5
+                  },
+                  "ADC6": {
+                    "description": "ADC Single Ended Input pin 6",
+                    "value": 6
+                  },
+                  "ADC7": {
+                    "description": "ADC Single Ended Input pin 7",
+                    "value": 7
+                  },
+                  "TEMPSENS": {
+                    "description": "Temperature sensor",
+                    "value": 8
+                  },
+                  "ADC_VBG": {
+                    "description": "Internal Reference (VBG)",
+                    "value": 14
+                  },
+                  "ADC_GND": {
+                    "description": "0V (GND)",
+                    "value": 15
+                  }
+                }
+              }
+            },
+            "ANALOG_ADC_PRESCALER": {
+              "size": 3,
+              "children": {
+                "enum_fields": {
+                  "2": {
+                    "description": "2",
+                    "value": 1
+                  },
+                  "4": {
+                    "description": "4",
+                    "value": 2
+                  },
+                  "8": {
+                    "description": "8",
+                    "value": 3
+                  },
+                  "16": {
+                    "description": "16",
+                    "value": 4
+                  },
+                  "32": {
+                    "description": "32",
+                    "value": 5
+                  },
+                  "64": {
+                    "description": "64",
+                    "value": 6
+                  },
+                  "128": {
+                    "description": "128",
+                    "value": 7
+                  }
+                }
+              }
+            },
+            "ANALOG_ADC_AUTO_TRIGGER": {
+              "size": 3,
+              "children": {
+                "enum_fields": {
+                  "FREE_RUNNING_MODE": {
+                    "description": "Free Running mode",
+                    "value": 0
+                  },
+                  "ANALOG_COMPARATOR": {
+                    "description": "Analog Comparator",
+                    "value": 1
+                  },
+                  "EXTERNAL_INTERRUPT_REQUEST_0": {
+                    "description": "External Interrupt Request 0",
+                    "value": 2
+                  },
+                  "TIMER_COUNTER0_COMPARE_MATCH_A": {
+                    "description": "Timer/Counter0 Compare Match A",
+                    "value": 3
+                  },
+                  "TIMER_COUNTER0_OVERFLOW": {
+                    "description": "Timer/Counter0 Overflow",
+                    "value": 4
+                  },
+                  "TIMER_COUNTER1_COMPARE_MATCH_B": {
+                    "description": "Timer/Counter1 Compare Match B",
+                    "value": 5
+                  },
+                  "TIMER_COUNTER1_OVERFLOW": {
+                    "description": "Timer/Counter1 Overflow",
+                    "value": 6
+                  },
+                  "TIMER_COUNTER1_CAPTURE_EVENT": {
+                    "description": "Timer/Counter1 Capture Event",
+                    "value": 7
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "AC": {
+        "description": "Analog Comparator",
+        "children": {
+          "registers": {
+            "ACSR": {
+              "description": "Analog Comparator Control And Status Register",
+              "offset": 0,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "ACD": {
+                    "description": "Analog Comparator Disable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ACBG": {
+                    "description": "Analog Comparator Bandgap Select",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ACO": {
+                    "description": "Analog Compare Output",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ACI": {
+                    "description": "Analog Comparator Interrupt Flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACIE": {
+                    "description": "Analog Comparator Interrupt Enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ACIC": {
+                    "description": "Analog Comparator Input Capture Enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ACIS": {
+                    "description": "Analog Comparator Interrupt Mode Select bits",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": "types.peripherals.AC.children.enums.ANALOG_COMP_INTERRUPT"
+                  }
+                }
+              }
+            },
+            "DIDR1": {
+              "description": "Digital Input Disable Register 1",
+              "offset": 47,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "AIN1D": {
+                    "description": "AIN1 Digital Input Disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "AIN0D": {
+                    "description": "AIN0 Digital Input Disable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "ANALOG_COMP_INTERRUPT": {
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "INTERRUPT_ON_TOGGLE": {
+                    "description": "Interrupt on Toggle",
+                    "value": 0
+                  },
+                  "RESERVED": {
+                    "description": "Reserved",
+                    "value": 1
+                  },
+                  "INTERRUPT_ON_FALLING_EDGE": {
+                    "description": "Interrupt on Falling Edge",
+                    "value": 2
+                  },
+                  "INTERRUPT_ON_RISING_EDGE": {
+                    "description": "Interrupt on Rising Edge",
+                    "value": 3
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PORT": {
+        "description": "I/O Port",
+        "children": {
+          "register_groups": {
+            "PORTB": {
+              "description": "I/O Port",
+              "children": {
+                "registers": {
+                  "PORTB": {
+                    "description": "Port B Data Register",
+                    "offset": 2,
+                    "size": 8
+                  },
+                  "DDRB": {
+                    "description": "Port B Data Direction Register",
+                    "offset": 1,
+                    "size": 8
+                  },
+                  "PINB": {
+                    "description": "Port B Input Pins",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PORTC": {
+              "description": "I/O Port",
+              "children": {
+                "registers": {
+                  "PORTC": {
+                    "description": "Port C Data Register",
+                    "offset": 2,
+                    "size": 8
+                  },
+                  "DDRC": {
+                    "description": "Port C Data Direction Register",
+                    "offset": 1,
+                    "size": 8
+                  },
+                  "PINC": {
+                    "description": "Port C Input Pins",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PORTD": {
+              "description": "I/O Port",
+              "children": {
+                "registers": {
+                  "PORTD": {
+                    "description": "Port D Data Register",
+                    "offset": 2,
+                    "size": 8
+                  },
+                  "DDRD": {
+                    "description": "Port D Data Direction Register",
+                    "offset": 1,
+                    "size": 8
+                  },
+                  "PIND": {
+                    "description": "Port D Input Pins",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TC8": {
+        "description": "Timer/Counter, 8-bit",
+        "children": {
+          "register_groups": {
+            "TC0": {
+              "description": "Timer/Counter, 8-bit",
+              "children": {
+                "registers": {
+                  "OCR0B": {
+                    "description": "Timer/Counter0 Output Compare Register",
+                    "offset": 19,
+                    "size": 8
+                  },
+                  "OCR0A": {
+                    "description": "Timer/Counter0 Output Compare Register",
+                    "offset": 18,
+                    "size": 8
+                  },
+                  "TCNT0": {
+                    "description": "Timer/Counter0",
+                    "offset": 17,
+                    "size": 8
+                  },
+                  "TCCR0B": {
+                    "description": "Timer/Counter Control Register B",
+                    "offset": 16,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "FOC0A": {
+                          "description": "Force Output Compare A",
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "FOC0B": {
+                          "description": "Force Output Compare B",
+                          "offset": 6,
+                          "size": 1
+                        },
+                        "WGM02": {
+                          "offset": 3,
+                          "size": 1
+                        },
+                        "CS0": {
+                          "description": "Clock Select",
+                          "offset": 0,
+                          "size": 3,
+                          "enum": "types.peripherals.TC16.children.enums.CLK_SEL_3BIT_EXT"
+                        }
+                      }
+                    }
+                  },
+                  "TCCR0A": {
+                    "description": "Timer/Counter  Control Register A",
+                    "offset": 15,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "COM0A": {
+                          "description": "Compare Output Mode, Phase Correct PWM Mode",
+                          "offset": 6,
+                          "size": 2
+                        },
+                        "COM0B": {
+                          "description": "Compare Output Mode, Fast PWm",
+                          "offset": 4,
+                          "size": 2
+                        },
+                        "WGM0": {
+                          "description": "Waveform Generation Mode",
+                          "offset": 0,
+                          "size": 2
+                        }
+                      }
+                    }
+                  },
+                  "TIMSK0": {
+                    "description": "Timer/Counter0 Interrupt Mask Register",
+                    "offset": 57,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "OCIE0B": {
+                          "description": "Timer/Counter0 Output Compare Match B Interrupt Enable",
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "OCIE0A": {
+                          "description": "Timer/Counter0 Output Compare Match A Interrupt Enable",
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TOIE0": {
+                          "description": "Timer/Counter0 Overflow Interrupt Enable",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "TIFR0": {
+                    "description": "Timer/Counter0 Interrupt Flag register",
+                    "offset": 0,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "OCF0B": {
+                          "description": "Timer/Counter0 Output Compare Flag 0B",
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "OCF0A": {
+                          "description": "Timer/Counter0 Output Compare Flag 0A",
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TOV0": {
+                          "description": "Timer/Counter0 Overflow Flag",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "GTCCR": {
+                    "description": "General Timer/Counter Control Register",
+                    "offset": 14,
+                    "size": 8,
+                    "children": {
+                      "fields": {
+                        "TSM": {
+                          "description": "Timer/Counter Synchronization Mode",
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "PSRSYNC": {
+                          "description": "Prescaler Reset Timer/Counter1 and Timer/Counter0",
+                          "offset": 0,
+                          "size": 1
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "CLK_SEL_3BIT_EXT": {
+              "size": 3,
+              "children": {
+                "enum_fields": {
+                  "NO_CLOCK_SOURCE_STOPPED": {
+                    "description": "No Clock Source (Stopped)",
+                    "value": 0
+                  },
+                  "RUNNING_NO_PRESCALING": {
+                    "description": "Running, No Prescaling",
+                    "value": 1
+                  },
+                  "RUNNING_CLK_8": {
+                    "description": "Running, CLK/8",
+                    "value": 2
+                  },
+                  "RUNNING_CLK_64": {
+                    "description": "Running, CLK/64",
+                    "value": 3
+                  },
+                  "RUNNING_CLK_256": {
+                    "description": "Running, CLK/256",
+                    "value": 4
+                  },
+                  "RUNNING_CLK_1024": {
+                    "description": "Running, CLK/1024",
+                    "value": 5
+                  },
+                  "RUNNING_EXTCLK_TN_FALLING_EDGE": {
+                    "description": "Running, ExtClk Tn Falling Edge",
+                    "value": 6
+                  },
+                  "RUNNING_EXTCLK_TN_RISING_EDGE": {
+                    "description": "Running, ExtClk Tn Rising Edge",
+                    "value": 7
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EXINT": {
+        "description": "External Interrupts",
+        "children": {
+          "registers": {
+            "EICRA": {
+              "description": "External Interrupt Control Register",
+              "offset": 46,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "ISC1": {
+                    "description": "External Interrupt Sense Control 1 Bits",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL"
+                  },
+                  "ISC0": {
+                    "description": "External Interrupt Sense Control 0 Bits",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": "types.peripherals.EXINT.children.enums.INTERRUPT_SENSE_CONTROL"
+                  }
+                }
+              }
+            },
+            "EIMSK": {
+              "description": "External Interrupt Mask Register",
+              "offset": 2,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "External Interrupt Request 1 Enable",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "EIFR": {
+              "description": "External Interrupt Flag Register",
+              "offset": 1,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "INTF": {
+                    "description": "External Interrupt Flags",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "PCICR": {
+              "description": "Pin Change Interrupt Control Register",
+              "offset": 45,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "PCIE": {
+                    "description": "Pin Change Interrupt Enables",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "PCMSK2": {
+              "description": "Pin Change Mask Register 2",
+              "offset": 50,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "PCINT": {
+                    "description": "Pin Change Enable Masks",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PCMSK1": {
+              "description": "Pin Change Mask Register 1",
+              "offset": 49,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "PCINT": {
+                    "description": "Pin Change Enable Masks",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "PCMSK0": {
+              "description": "Pin Change Mask Register 0",
+              "offset": 48,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "PCINT": {
+                    "description": "Pin Change Enable Masks",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "PCIFR": {
+              "description": "Pin Change Interrupt Flag Register",
+              "offset": 0,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "PCIF": {
+                    "description": "Pin Change Interrupt Flags",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "INTERRUPT_SENSE_CONTROL": {
+              "description": "Interrupt Sense Control",
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "LOW_LEVEL_OF_INTX": {
+                    "description": "Low Level of INTX",
+                    "value": 0
+                  },
+                  "ANY_LOGICAL_CHANGE_OF_INTX": {
+                    "description": "Any Logical Change of INTX",
+                    "value": 1
+                  },
+                  "FALLING_EDGE_OF_INTX": {
+                    "description": "Falling Edge of INTX",
+                    "value": 2
+                  },
+                  "RISING_EDGE_OF_INTX": {
+                    "description": "Rising Edge of INTX",
+                    "value": 3
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI": {
+        "description": "Serial Peripheral Interface",
+        "children": {
+          "registers": {
+            "SPDR": {
+              "description": "SPI Data Register",
+              "offset": 2,
+              "size": 8
+            },
+            "SPSR": {
+              "description": "SPI Status Register",
+              "offset": 1,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "SPIF": {
+                    "description": "SPI Interrupt Flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "WCOL": {
+                    "description": "Write Collision Flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SPI2X": {
+                    "description": "Double SPI Speed Bit",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SPCR": {
+              "description": "SPI Control Register",
+              "offset": 0,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "SPIE": {
+                    "description": "SPI Interrupt Enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SPE": {
+                    "description": "SPI Enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DORD": {
+                    "description": "Data Order",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MSTR": {
+                    "description": "Master/Slave Select",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CPOL": {
+                    "description": "Clock polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CPHA": {
+                    "description": "Clock Phase",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SPR": {
+                    "description": "SPI Clock Rate Selects",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": "types.peripherals.SPI.children.enums.COMM_SCK_RATE_3BIT"
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "COMM_SCK_RATE_3BIT": {
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "FOSC_2_OR_FOSC_4": {
+                    "description": "fosc/2 or fosc/4",
+                    "value": 0
+                  },
+                  "FOSC_8_OR_FOSC_16": {
+                    "description": "fosc/8 or fosc/16",
+                    "value": 1
+                  },
+                  "FOSC_32_OR_FOSC_64": {
+                    "description": "fosc/32 or fosc/64",
+                    "value": 2
+                  },
+                  "FOSC_64_OR_FOSC_128": {
+                    "description": "fosc/64 or fosc/128",
+                    "value": 3
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "WDT": {
+        "description": "Watchdog Timer",
+        "children": {
+          "registers": {
+            "WDTCSR": {
+              "description": "Watchdog Timer Control Register",
+              "offset": 0,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "WDIF": {
+                    "description": "Watchdog Timeout Interrupt Flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "WDIE": {
+                    "description": "Watchdog Timeout Interrupt Enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "WDP_bit0": {
+                    "description": "Watchdog Timer Prescaler Bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "WDP_bit1": {
+                    "description": "Watchdog Timer Prescaler Bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WDP_bit2": {
+                    "description": "Watchdog Timer Prescaler Bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "WDP_bit3": {
+                    "description": "Watchdog Timer Prescaler Bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WDCE": {
+                    "description": "Watchdog Change Enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "WDE": {
+                    "description": "Watch Dog Enable",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "WDOG_TIMER_PRESCALE_4BITS": {
+              "size": 4,
+              "children": {
+                "enum_fields": {
+                  "OSCILLATOR_CYCLES_2K": {
+                    "description": "Oscillator Cycles 2K",
+                    "value": 0
+                  },
+                  "OSCILLATOR_CYCLES_4K": {
+                    "description": "Oscillator Cycles 4K",
+                    "value": 1
+                  },
+                  "OSCILLATOR_CYCLES_8K": {
+                    "description": "Oscillator Cycles 8K",
+                    "value": 2
+                  },
+                  "OSCILLATOR_CYCLES_16K": {
+                    "description": "Oscillator Cycles 16K",
+                    "value": 3
+                  },
+                  "OSCILLATOR_CYCLES_32K": {
+                    "description": "Oscillator Cycles 32K",
+                    "value": 4
+                  },
+                  "OSCILLATOR_CYCLES_64K": {
+                    "description": "Oscillator Cycles 64K",
+                    "value": 5
+                  },
+                  "OSCILLATOR_CYCLES_128K": {
+                    "description": "Oscillator Cycles 128K",
+                    "value": 6
+                  },
+                  "OSCILLATOR_CYCLES_256K": {
+                    "description": "Oscillator Cycles 256K",
+                    "value": 7
+                  },
+                  "OSCILLATOR_CYCLES_512K": {
+                    "description": "Oscillator Cycles 512K",
+                    "value": 8
+                  },
+                  "OSCILLATOR_CYCLES_1024K": {
+                    "description": "Oscillator Cycles 1024K",
+                    "value": 9
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CPU": {
+        "description": "CPU Registers",
+        "children": {
+          "registers": {
+            "PRR": {
+              "description": "Power Reduction Register",
+              "offset": 38,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "PRTWI": {
+                    "description": "Power Reduction TWI",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PRTIM2": {
+                    "description": "Power Reduction Timer/Counter2",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PRTIM0": {
+                    "description": "Power Reduction Timer/Counter0",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PRTIM1": {
+                    "description": "Power Reduction Timer/Counter1",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PRSPI": {
+                    "description": "Power Reduction Serial Peripheral Interface",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PRUSART0": {
+                    "description": "Power Reduction USART",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PRADC": {
+                    "description": "Power Reduction ADC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OSCCAL": {
+              "description": "Oscillator Calibration Value",
+              "offset": 40,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "OSCCAL": {
+                    "description": "Oscillator Calibration ",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLKPR": {
+              "description": "Clock Prescale Register",
+              "offset": 35,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "CLKPCE": {
+                    "description": "Clock Prescaler Change Enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CLKPS": {
+                    "description": "Clock Prescaler Select Bits",
+                    "offset": 0,
+                    "size": 4,
+                    "enum": "types.peripherals.CPU.children.enums.CPU_CLK_PRESCALE_4_BITS_SMALL"
+                  }
+                }
+              }
+            },
+            "SREG": {
+              "description": "Status Register",
+              "offset": 33,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "I": {
+                    "description": "Global Interrupt Enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "T": {
+                    "description": "Bit Copy Storage",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "H": {
+                    "description": "Half Carry Flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "S": {
+                    "description": "Sign Bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "V": {
+                    "description": "Two's Complement Overflow Flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "N": {
+                    "description": "Negative Flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "Z": {
+                    "description": "Zero Flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "C": {
+                    "description": "Carry Flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SP": {
+              "description": "Stack Pointer ",
+              "offset": 31,
+              "size": 16
+            },
+            "SPMCSR": {
+              "description": "Store Program Memory Control and Status Register",
+              "offset": 25,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "SPMIE": {
+                    "description": "SPM Interrupt Enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RWWSB": {
+                    "description": "Read-While-Write Section Busy",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SIGRD": {
+                    "description": "Signature Row Read",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RWWSRE": {
+                    "description": "Read-While-Write section read enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BLBSET": {
+                    "description": "Boot Lock Bit Set",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PGWRT": {
+                    "description": "Page Write",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PGERS": {
+                    "description": "Page Erase",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SPMEN": {
+                    "description": "Store Program Memory",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MCUCR": {
+              "description": "MCU Control Register",
+              "offset": 23,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "BODS": {
+                    "description": "BOD Sleep",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BODSE": {
+                    "description": "BOD Sleep Enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PUD": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IVSEL": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IVCE": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MCUSR": {
+              "description": "MCU Status Register",
+              "offset": 22,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "WDRF": {
+                    "description": "Watchdog Reset Flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BORF": {
+                    "description": "Brown-out Reset Flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EXTRF": {
+                    "description": "External Reset Flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PORF": {
+                    "description": "Power-on reset flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCR": {
+              "description": "Sleep Mode Control Register",
+              "offset": 21,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "SM": {
+                    "description": "Sleep Mode Select Bits",
+                    "offset": 1,
+                    "size": 3,
+                    "enum": "types.peripherals.CPU.children.enums.CPU_SLEEP_MODE_3BITS2"
+                  },
+                  "SE": {
+                    "description": "Sleep Enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIOR2": {
+              "description": "General Purpose I/O Register 2",
+              "offset": 13,
+              "size": 8
+            },
+            "GPIOR1": {
+              "description": "General Purpose I/O Register 1",
+              "offset": 12,
+              "size": 8
+            },
+            "GPIOR0": {
+              "description": "General Purpose I/O Register 0",
+              "offset": 0,
+              "size": 8
+            }
+          },
+          "enums": {
+            "CPU_CLK_PRESCALE_4_BITS_SMALL": {
+              "size": 4,
+              "children": {
+                "enum_fields": {
+                  "1": {
+                    "description": "1",
+                    "value": 0
+                  },
+                  "2": {
+                    "description": "2",
+                    "value": 1
+                  },
+                  "4": {
+                    "description": "4",
+                    "value": 2
+                  },
+                  "8": {
+                    "description": "8",
+                    "value": 3
+                  },
+                  "16": {
+                    "description": "16",
+                    "value": 4
+                  },
+                  "32": {
+                    "description": "32",
+                    "value": 5
+                  },
+                  "64": {
+                    "description": "64",
+                    "value": 6
+                  },
+                  "128": {
+                    "description": "128",
+                    "value": 7
+                  },
+                  "256": {
+                    "description": "256",
+                    "value": 8
+                  }
+                }
+              }
+            },
+            "CPU_SLEEP_MODE_3BITS2": {
+              "size": 3,
+              "children": {
+                "enum_fields": {
+                  "IDLE": {
+                    "description": "Idle",
+                    "value": 0
+                  },
+                  "ADC": {
+                    "description": "ADC Noise Reduction (If Available)",
+                    "value": 1
+                  },
+                  "PDOWN": {
+                    "description": "Power Down",
+                    "value": 2
+                  },
+                  "PSAVE": {
+                    "description": "Power Save",
+                    "value": 3
+                  },
+                  "VAL_0x04": {
+                    "description": "Reserved",
+                    "value": 4
+                  },
+                  "VAL_0x05": {
+                    "description": "Reserved",
+                    "value": 5
+                  },
+                  "STDBY": {
+                    "description": "Standby",
+                    "value": 6
+                  },
+                  "ESTDBY": {
+                    "description": "Extended Standby",
+                    "value": 7
+                  }
+                }
+              }
+            },
+            "OSCCAL_VALUE_ADDRESSES": {
+              "description": "Oscillator Calibration Values",
+              "size": 1,
+              "children": {
+                "enum_fields": {
+                  "8_0_MHz": {
+                    "description": "8.0 MHz",
+                    "value": 0
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EEPROM": {
+        "description": "EEPROM",
+        "children": {
+          "registers": {
+            "EEAR": {
+              "description": "EEPROM Address Register  Bytes",
+              "offset": 2,
+              "size": 16
+            },
+            "EEDR": {
+              "description": "EEPROM Data Register",
+              "offset": 1,
+              "size": 8
+            },
+            "EECR": {
+              "description": "EEPROM Control Register",
+              "offset": 0,
+              "size": 8,
+              "children": {
+                "fields": {
+                  "EEPM": {
+                    "description": "EEPROM Programming Mode Bits",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": "types.peripherals.EEPROM.children.enums.EEP_MODE"
+                  },
+                  "EERIE": {
+                    "description": "EEPROM Ready Interrupt Enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EEMPE": {
+                    "description": "EEPROM Master Write Enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EEPE": {
+                    "description": "EEPROM Write Enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EERE": {
+                    "description": "EEPROM Read Enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          },
+          "enums": {
+            "EEP_MODE": {
+              "size": 2,
+              "children": {
+                "enum_fields": {
+                  "ERASE_AND_WRITE_IN_ONE_OPERATION": {
+                    "description": "Erase and Write in one operation",
+                    "value": 0
+                  },
+                  "ERASE_ONLY": {
+                    "description": "Erase Only",
+                    "value": 1
+                  },
+                  "WRITE_ONLY": {
+                    "description": "Write Only",
+                    "value": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  },
+  "devices": {
+    "ATmega328P": {
+      "arch": "avr8",
+      "properties": {
+        "family": "megaAVR",
+        "arch": "AVR8"
+      },
+      "children": {
+        "interrupts": {
+          "RESET": {
+            "index": 0,
+            "description": "External Pin, Power-on Reset, Brown-out Reset and Watchdog Reset"
+          },
+          "INT0": {
+            "index": 1,
+            "description": "External Interrupt Request 0"
+          },
+          "INT1": {
+            "index": 2,
+            "description": "External Interrupt Request 1"
+          },
+          "PCINT0": {
+            "index": 3,
+            "description": "Pin Change Interrupt Request 0"
+          },
+          "PCINT1": {
+            "index": 4,
+            "description": "Pin Change Interrupt Request 1"
+          },
+          "PCINT2": {
+            "index": 5,
+            "description": "Pin Change Interrupt Request 2"
+          },
+          "WDT": {
+            "index": 6,
+            "description": "Watchdog Time-out Interrupt"
+          },
+          "TIMER2_COMPA": {
+            "index": 7,
+            "description": "Timer/Counter2 Compare Match A"
+          },
+          "TIMER2_COMPB": {
+            "index": 8,
+            "description": "Timer/Counter2 Compare Match B"
+          },
+          "TIMER2_OVF": {
+            "index": 9,
+            "description": "Timer/Counter2 Overflow"
+          },
+          "TIMER1_CAPT": {
+            "index": 10,
+            "description": "Timer/Counter1 Capture Event"
+          },
+          "TIMER1_COMPA": {
+            "index": 11,
+            "description": "Timer/Counter1 Compare Match A"
+          },
+          "TIMER1_COMPB": {
+            "index": 12,
+            "description": "Timer/Counter1 Compare Match B"
+          },
+          "TIMER1_OVF": {
+            "index": 13,
+            "description": "Timer/Counter1 Overflow"
+          },
+          "TIMER0_COMPA": {
+            "index": 14,
+            "description": "TimerCounter0 Compare Match A"
+          },
+          "TIMER0_COMPB": {
+            "index": 15,
+            "description": "TimerCounter0 Compare Match B"
+          },
+          "TIMER0_OVF": {
+            "index": 16,
+            "description": "Timer/Couner0 Overflow"
+          },
+          "SPI_STC": {
+            "index": 17,
+            "description": "SPI Serial Transfer Complete"
+          },
+          "USART_RX": {
+            "index": 18,
+            "description": "USART Rx Complete"
+          },
+          "USART_UDRE": {
+            "index": 19,
+            "description": "USART, Data Register Empty"
+          },
+          "USART_TX": {
+            "index": 20,
+            "description": "USART Tx Complete"
+          },
+          "ADC": {
+            "index": 21,
+            "description": "ADC Conversion Complete"
+          },
+          "EE_READY": {
+            "index": 22,
+            "description": "EEPROM Ready"
+          },
+          "ANALOG_COMP": {
+            "index": 23,
+            "description": "Analog Comparator"
+          },
+          "TWI": {
+            "index": 24,
+            "description": "Two-wire Serial Interface"
+          },
+          "SPM_Ready": {
+            "index": 25,
+            "description": "Store Program Memory Read"
+          }
+        },
+        "peripheral_instances": {
+          "USART0": {
+            "description": "USART",
+            "offset": 192,
+            "type": "types.peripherals.USART.children.register_groups.USART0"
+          },
+          "TWI": {
+            "description": "Two Wire Serial Interface",
+            "offset": 184,
+            "type": "types.peripherals.TWI"
+          },
+          "TC1": {
+            "description": "Timer/Counter, 16-bit",
+            "offset": 54,
+            "type": "types.peripherals.TC16.children.register_groups.TC1"
+          },
+          "TC2": {
+            "description": "Timer/Counter, 8-bit Async",
+            "offset": 55,
+            "type": "types.peripherals.TC8_ASYNC.children.register_groups.TC2"
+          },
+          "ADC": {
+            "description": "Analog-to-Digital Converter",
+            "offset": 120,
+            "type": "types.peripherals.ADC"
+          },
+          "AC": {
+            "description": "Analog Comparator",
+            "offset": 80,
+            "type": "types.peripherals.AC"
+          },
+          "PORTB": {
+            "description": "I/O Port",
+            "offset": 35,
+            "type": "types.peripherals.PORT.children.register_groups.PORTB"
+          },
+          "PORTC": {
+            "description": "I/O Port",
+            "offset": 38,
+            "type": "types.peripherals.PORT.children.register_groups.PORTC"
+          },
+          "PORTD": {
+            "description": "I/O Port",
+            "offset": 41,
+            "type": "types.peripherals.PORT.children.register_groups.PORTD"
+          },
+          "TC0": {
+            "description": "Timer/Counter, 8-bit",
+            "offset": 53,
+            "type": "types.peripherals.TC8.children.register_groups.TC0"
+          },
+          "EXINT": {
+            "description": "External Interrupts",
+            "offset": 59,
+            "type": "types.peripherals.EXINT"
+          },
+          "SPI": {
+            "description": "Serial Peripheral Interface",
+            "offset": 76,
+            "type": "types.peripherals.SPI"
+          },
+          "WDT": {
+            "description": "Watchdog Timer",
+            "offset": 96,
+            "type": "types.peripherals.WDT"
+          },
+          "EEPROM": {
+            "description": "EEPROM",
+            "offset": 63,
+            "type": "types.peripherals.EEPROM"
+          },
+          "CPU": {
+            "description": "CPU Registers",
+            "offset": 62,
+            "type": "types.peripherals.CPU"
+          },
+          "FUSE": {
+            "description": "Fuses",
+            "offset": 0,
+            "type": "types.peripherals.FUSE"
+          },
+          "LOCKBIT": {
+            "description": "Lockbits",
+            "offset": 0,
+            "type": "types.peripherals.LOCKBIT"
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/chips/ATmega328P.zig b/src/chips/ATmega328P.zig
new file mode 100644
index 000000000..604b37fec
--- /dev/null
+++ b/src/chips/ATmega328P.zig
@@ -0,0 +1,1388 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    pub const ATmega328P = struct {
+        pub const properties = struct {
+            pub const family = "megaAVR";
+            pub const arch = "AVR8";
+        };
+
+        pub const VectorTable = extern struct {
+            const Handler = micro.interrupt.Handler;
+            const unhandled = micro.interrupt.unhandled;
+
+            RESET: Handler = unhandled,
+            ///  External Interrupt Request 0
+            INT0: Handler = unhandled,
+            ///  External Interrupt Request 1
+            INT1: Handler = unhandled,
+            ///  Pin Change Interrupt Request 0
+            PCINT0: Handler = unhandled,
+            ///  Pin Change Interrupt Request 1
+            PCINT1: Handler = unhandled,
+            ///  Pin Change Interrupt Request 2
+            PCINT2: Handler = unhandled,
+            ///  Watchdog Time-out Interrupt
+            WDT: Handler = unhandled,
+            ///  Timer/Counter2 Compare Match A
+            TIMER2_COMPA: Handler = unhandled,
+            ///  Timer/Counter2 Compare Match B
+            TIMER2_COMPB: Handler = unhandled,
+            ///  Timer/Counter2 Overflow
+            TIMER2_OVF: Handler = unhandled,
+            ///  Timer/Counter1 Capture Event
+            TIMER1_CAPT: Handler = unhandled,
+            ///  Timer/Counter1 Compare Match A
+            TIMER1_COMPA: Handler = unhandled,
+            ///  Timer/Counter1 Compare Match B
+            TIMER1_COMPB: Handler = unhandled,
+            ///  Timer/Counter1 Overflow
+            TIMER1_OVF: Handler = unhandled,
+            ///  TimerCounter0 Compare Match A
+            TIMER0_COMPA: Handler = unhandled,
+            ///  TimerCounter0 Compare Match B
+            TIMER0_COMPB: Handler = unhandled,
+            ///  Timer/Couner0 Overflow
+            TIMER0_OVF: Handler = unhandled,
+            ///  SPI Serial Transfer Complete
+            SPI_STC: Handler = unhandled,
+            ///  USART Rx Complete
+            USART_RX: Handler = unhandled,
+            ///  USART, Data Register Empty
+            USART_UDRE: Handler = unhandled,
+            ///  USART Tx Complete
+            USART_TX: Handler = unhandled,
+            ///  ADC Conversion Complete
+            ADC: Handler = unhandled,
+            ///  EEPROM Ready
+            EE_READY: Handler = unhandled,
+            ///  Analog Comparator
+            ANALOG_COMP: Handler = unhandled,
+            ///  Two-wire Serial Interface
+            TWI: Handler = unhandled,
+            ///  Store Program Memory Read
+            SPM_Ready: Handler = unhandled,
+        };
+
+        pub const peripherals = struct {
+            ///  Fuses
+            pub const FUSE = @intToPtr(*volatile types.peripherals.FUSE, 0x0);
+            ///  Lockbits
+            pub const LOCKBIT = @intToPtr(*volatile types.peripherals.LOCKBIT, 0x0);
+            ///  I/O Port
+            pub const PORTB = @intToPtr(*volatile types.peripherals.PORT.PORTB, 0x23);
+            ///  I/O Port
+            pub const PORTC = @intToPtr(*volatile types.peripherals.PORT.PORTC, 0x26);
+            ///  I/O Port
+            pub const PORTD = @intToPtr(*volatile types.peripherals.PORT.PORTD, 0x29);
+            ///  Timer/Counter, 8-bit
+            pub const TC0 = @intToPtr(*volatile types.peripherals.TC8.TC0, 0x35);
+            ///  Timer/Counter, 16-bit
+            pub const TC1 = @intToPtr(*volatile types.peripherals.TC16.TC1, 0x36);
+            ///  Timer/Counter, 8-bit Async
+            pub const TC2 = @intToPtr(*volatile types.peripherals.TC8_ASYNC.TC2, 0x37);
+            ///  External Interrupts
+            pub const EXINT = @intToPtr(*volatile types.peripherals.EXINT, 0x3b);
+            ///  CPU Registers
+            pub const CPU = @intToPtr(*volatile types.peripherals.CPU, 0x3e);
+            ///  EEPROM
+            pub const EEPROM = @intToPtr(*volatile types.peripherals.EEPROM, 0x3f);
+            ///  Serial Peripheral Interface
+            pub const SPI = @intToPtr(*volatile types.peripherals.SPI, 0x4c);
+            ///  Analog Comparator
+            pub const AC = @intToPtr(*volatile types.peripherals.AC, 0x50);
+            ///  Watchdog Timer
+            pub const WDT = @intToPtr(*volatile types.peripherals.WDT, 0x60);
+            ///  Analog-to-Digital Converter
+            pub const ADC = @intToPtr(*volatile types.peripherals.ADC, 0x78);
+            ///  Two Wire Serial Interface
+            pub const TWI = @intToPtr(*volatile types.peripherals.TWI, 0xb8);
+            ///  USART
+            pub const USART0 = @intToPtr(*volatile types.peripherals.USART.USART0, 0xc0);
+        };
+    };
+};
+
+pub const types = struct {
+    pub const peripherals = struct {
+        ///  Fuses
+        pub const FUSE = extern struct {
+            pub const ENUM_SUT_CKSEL = enum(u6) {
+                ///  Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
+                EXTCLK_6CK_14CK_0MS = 0x0,
+                ///  Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
+                EXTCLK_6CK_14CK_4MS1 = 0x10,
+                ///  Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
+                EXTCLK_6CK_14CK_65MS = 0x20,
+                ///  Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
+                INTRCOSC_8MHZ_6CK_14CK_0MS = 0x2,
+                ///  Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
+                INTRCOSC_8MHZ_6CK_14CK_4MS1 = 0x12,
+                ///  Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
+                INTRCOSC_8MHZ_6CK_14CK_65MS = 0x22,
+                ///  Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
+                INTRCOSC_128KHZ_6CK_14CK_0MS = 0x3,
+                ///  Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
+                INTRCOSC_128KHZ_6CK_14CK_4MS1 = 0x13,
+                ///  Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
+                INTRCOSC_128KHZ_6CK_14CK_65MS = 0x23,
+                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms
+                EXTLOFXTAL_1KCK_14CK_0MS = 0x4,
+                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms
+                EXTLOFXTAL_1KCK_14CK_4MS1 = 0x14,
+                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms
+                EXTLOFXTAL_1KCK_14CK_65MS = 0x24,
+                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms
+                EXTLOFXTAL_32KCK_14CK_0MS = 0x5,
+                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms
+                EXTLOFXTAL_32KCK_14CK_4MS1 = 0x15,
+                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms
+                EXTLOFXTAL_32KCK_14CK_65MS = 0x25,
+                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
+                EXTFSXTAL_258CK_14CK_4MS1 = 0x6,
+                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
+                EXTFSXTAL_258CK_14CK_65MS = 0x16,
+                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
+                EXTFSXTAL_1KCK_14CK_0MS = 0x26,
+                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
+                EXTFSXTAL_1KCK_14CK_4MS1 = 0x36,
+                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
+                EXTFSXTAL_1KCK_14CK_65MS = 0x7,
+                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
+                EXTFSXTAL_16KCK_14CK_0MS = 0x17,
+                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
+                EXTFSXTAL_16KCK_14CK_4MS1 = 0x27,
+                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
+                EXTFSXTAL_16KCK_14CK_65MS = 0x37,
+                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
+                EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 = 0x8,
+                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
+                EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS = 0x18,
+                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
+                EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS = 0x28,
+                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
+                EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 = 0x38,
+                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
+                EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS = 0x9,
+                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
+                EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS = 0x19,
+                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
+                EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 = 0x29,
+                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
+                EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS = 0x39,
+                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
+                EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 = 0xa,
+                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
+                EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS = 0x1a,
+                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
+                EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS = 0x2a,
+                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
+                EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 = 0x3a,
+                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
+                EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS = 0xb,
+                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
+                EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS = 0x1b,
+                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
+                EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 = 0x2b,
+                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
+                EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS = 0x3b,
+                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
+                EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 = 0xc,
+                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
+                EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS = 0x1c,
+                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
+                EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS = 0x2c,
+                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
+                EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 = 0x3c,
+                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
+                EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS = 0xd,
+                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
+                EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS = 0x1d,
+                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
+                EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 = 0x2d,
+                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
+                EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS = 0x3d,
+                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
+                EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 = 0xe,
+                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
+                EXTXOSC_8MHZ_XX_258CK_14CK_65MS = 0x1e,
+                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
+                EXTXOSC_8MHZ_XX_1KCK_14CK_0MS = 0x2e,
+                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
+                EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 = 0x3e,
+                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
+                EXTXOSC_8MHZ_XX_1KCK_14CK_65MS = 0xf,
+                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
+                EXTXOSC_8MHZ_XX_16KCK_14CK_0MS = 0x1f,
+                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
+                EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 = 0x2f,
+                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
+                EXTXOSC_8MHZ_XX_16KCK_14CK_65MS = 0x3f,
+                _,
+            };
+
+            pub const ENUM_BODLEVEL = enum(u3) {
+                ///  Brown-out detection at VCC=4.3 V
+                @"4V3" = 0x4,
+                ///  Brown-out detection at VCC=2.7 V
+                @"2V7" = 0x5,
+                ///  Brown-out detection at VCC=1.8 V
+                @"1V8" = 0x6,
+                ///  Brown-out detection disabled
+                DISABLED = 0x7,
+                _,
+            };
+
+            pub const ENUM_BOOTSZ = enum(u2) {
+                ///  Boot Flash size=256 words start address=$3F00
+                @"256W_3F00" = 0x3,
+                ///  Boot Flash size=512 words start address=$3E00
+                @"512W_3E00" = 0x2,
+                ///  Boot Flash size=1024 words start address=$3C00
+                @"1024W_3C00" = 0x1,
+                ///  Boot Flash size=2048 words start address=$3800
+                @"2048W_3800" = 0x0,
+            };
+
+            LOW: mmio.Mmio(packed struct(u8) {
+                ///  Select Clock Source
+                SUT_CKSEL: packed union {
+                    raw: u6,
+                    value: ENUM_SUT_CKSEL,
+                },
+                ///  Clock output on PORTB0
+                CKOUT: u1,
+                ///  Divide clock by 8 internally
+                CKDIV8: u1,
+            }),
+            HIGH: mmio.Mmio(packed struct(u8) {
+                ///  Boot Reset vector Enabled
+                BOOTRST: u1,
+                ///  Select boot size
+                BOOTSZ: packed union {
+                    raw: u2,
+                    value: ENUM_BOOTSZ,
+                },
+                ///  Preserve EEPROM through the Chip Erase cycle
+                EESAVE: u1,
+                ///  Watch-dog Timer always on
+                WDTON: u1,
+                ///  Serial program downloading (SPI) enabled
+                SPIEN: u1,
+                ///  Debug Wire enable
+                DWEN: u1,
+                ///  Reset Disabled (Enable PC6 as i/o pin)
+                RSTDISBL: u1,
+            }),
+            EXTENDED: mmio.Mmio(packed struct(u8) {
+                ///  Brown-out Detector trigger level
+                BODLEVEL: packed union {
+                    raw: u3,
+                    value: ENUM_BODLEVEL,
+                },
+                padding: u5,
+            }),
+        };
+
+        ///  Lockbits
+        pub const LOCKBIT = extern struct {
+            pub const ENUM_LB = enum(u2) {
+                ///  Further programming and verification disabled
+                PROG_VER_DISABLED = 0x0,
+                ///  Further programming disabled
+                PROG_DISABLED = 0x2,
+                ///  No memory lock features enabled
+                NO_LOCK = 0x3,
+                _,
+            };
+
+            pub const ENUM_BLB = enum(u2) {
+                ///  LPM and SPM prohibited in Application Section
+                LPM_SPM_DISABLE = 0x0,
+                ///  LPM prohibited in Application Section
+                LPM_DISABLE = 0x1,
+                ///  SPM prohibited in Application Section
+                SPM_DISABLE = 0x2,
+                ///  No lock on SPM and LPM in Application Section
+                NO_LOCK = 0x3,
+            };
+
+            pub const ENUM_BLB2 = enum(u2) {
+                ///  LPM and SPM prohibited in Boot Section
+                LPM_SPM_DISABLE = 0x0,
+                ///  LPM prohibited in Boot Section
+                LPM_DISABLE = 0x1,
+                ///  SPM prohibited in Boot Section
+                SPM_DISABLE = 0x2,
+                ///  No lock on SPM and LPM in Boot Section
+                NO_LOCK = 0x3,
+            };
+
+            LOCKBIT: mmio.Mmio(packed struct(u8) {
+                ///  Memory Lock
+                LB: packed union {
+                    raw: u2,
+                    value: ENUM_LB,
+                },
+                ///  Boot Loader Protection Mode
+                BLB0: packed union {
+                    raw: u2,
+                    value: ENUM_BLB,
+                },
+                ///  Boot Loader Protection Mode
+                BLB1: packed union {
+                    raw: u2,
+                    value: ENUM_BLB2,
+                },
+                padding: u2,
+            }),
+        };
+
+        ///  USART
+        pub const USART = struct {
+            pub const COMM_USART_MODE_2BIT = enum(u2) {
+                ///  Asynchronous USART
+                ASYNCHRONOUS_USART = 0x0,
+                ///  Synchronous USART
+                SYNCHRONOUS_USART = 0x1,
+                ///  Master SPI
+                MASTER_SPI = 0x3,
+                _,
+            };
+
+            pub const COMM_UPM_PARITY_MODE = enum(u2) {
+                ///  Disabled
+                DISABLED = 0x0,
+                ///  Reserved
+                RESERVED = 0x1,
+                ///  Enabled, Even Parity
+                ENABLED_EVEN_PARITY = 0x2,
+                ///  Enabled, Odd Parity
+                ENABLED_ODD_PARITY = 0x3,
+            };
+
+            pub const COMM_STOP_BIT_SEL = enum(u1) {
+                ///  1-bit
+                @"1_BIT" = 0x0,
+                ///  2-bit
+                @"2_BIT" = 0x1,
+            };
+
+            ///  USART
+            pub const USART0 = extern struct {
+                ///  USART Control and Status Register A
+                UCSR0A: mmio.Mmio(packed struct(u8) {
+                    ///  Multi-processor Communication Mode
+                    MPCM0: u1,
+                    ///  Double the USART transmission speed
+                    U2X0: u1,
+                    ///  Parity Error
+                    UPE0: u1,
+                    ///  Data overRun
+                    DOR0: u1,
+                    ///  Framing Error
+                    FE0: u1,
+                    ///  USART Data Register Empty
+                    UDRE0: u1,
+                    ///  USART Transmitt Complete
+                    TXC0: u1,
+                    ///  USART Receive Complete
+                    RXC0: u1,
+                }),
+                ///  USART Control and Status Register B
+                UCSR0B: mmio.Mmio(packed struct(u8) {
+                    ///  Transmit Data Bit 8
+                    TXB80: u1,
+                    ///  Receive Data Bit 8
+                    RXB80: u1,
+                    ///  Character Size - together with UCSZ0 in UCSR0C
+                    UCSZ02: u1,
+                    ///  Transmitter Enable
+                    TXEN0: u1,
+                    ///  Receiver Enable
+                    RXEN0: u1,
+                    ///  USART Data register Empty Interrupt Enable
+                    UDRIE0: u1,
+                    ///  TX Complete Interrupt Enable
+                    TXCIE0: u1,
+                    ///  RX Complete Interrupt Enable
+                    RXCIE0: u1,
+                }),
+                ///  USART Control and Status Register C
+                UCSR0C: mmio.Mmio(packed struct(u8) {
+                    ///  Clock Polarity
+                    UCPOL0: u1,
+                    ///  Character Size - together with UCSZ2 in UCSR0B
+                    UCSZ0: u2,
+                    ///  Stop Bit Select
+                    USBS0: packed union {
+                        raw: u1,
+                        value: COMM_STOP_BIT_SEL,
+                    },
+                    ///  Parity Mode Bits
+                    UPM0: packed union {
+                        raw: u2,
+                        value: COMM_UPM_PARITY_MODE,
+                    },
+                    ///  USART Mode Select
+                    UMSEL0: packed union {
+                        raw: u2,
+                        value: COMM_USART_MODE_2BIT,
+                    },
+                }),
+                reserved4: [1]u8,
+                ///  USART Baud Rate Register Bytes
+                UBRR0: u16,
+                ///  USART I/O Data Register
+                UDR0: u8,
+            };
+        };
+
+        ///  Two Wire Serial Interface
+        pub const TWI = extern struct {
+            pub const COMM_TWI_PRESACLE = enum(u2) {
+                ///  1
+                @"1" = 0x0,
+                ///  4
+                @"4" = 0x1,
+                ///  16
+                @"16" = 0x2,
+                ///  64
+                @"64" = 0x3,
+            };
+
+            ///  TWI Bit Rate register
+            TWBR: u8,
+            ///  TWI Status Register
+            TWSR: mmio.Mmio(packed struct(u8) {
+                ///  TWI Prescaler
+                TWPS: packed union {
+                    raw: u2,
+                    value: COMM_TWI_PRESACLE,
+                },
+                reserved3: u1,
+                ///  TWI Status
+                TWS: u5,
+            }),
+            ///  TWI (Slave) Address register
+            TWAR: mmio.Mmio(packed struct(u8) {
+                ///  TWI General Call Recognition Enable Bit
+                TWGCE: u1,
+                ///  TWI (Slave) Address register Bits
+                TWA: u7,
+            }),
+            ///  TWI Data register
+            TWDR: u8,
+            ///  TWI Control Register
+            TWCR: mmio.Mmio(packed struct(u8) {
+                ///  TWI Interrupt Enable
+                TWIE: u1,
+                reserved2: u1,
+                ///  TWI Enable Bit
+                TWEN: u1,
+                ///  TWI Write Collition Flag
+                TWWC: u1,
+                ///  TWI Stop Condition Bit
+                TWSTO: u1,
+                ///  TWI Start Condition Bit
+                TWSTA: u1,
+                ///  TWI Enable Acknowledge Bit
+                TWEA: u1,
+                ///  TWI Interrupt Flag
+                TWINT: u1,
+            }),
+            ///  TWI (Slave) Address Mask Register
+            TWAMR: mmio.Mmio(packed struct(u8) {
+                reserved1: u1,
+                TWAM: u7,
+            }),
+        };
+
+        ///  Timer/Counter, 16-bit
+        pub const TC16 = struct {
+            pub const CLK_SEL_3BIT_EXT = enum(u3) {
+                ///  No Clock Source (Stopped)
+                NO_CLOCK_SOURCE_STOPPED = 0x0,
+                ///  Running, No Prescaling
+                RUNNING_NO_PRESCALING = 0x1,
+                ///  Running, CLK/8
+                RUNNING_CLK_8 = 0x2,
+                ///  Running, CLK/64
+                RUNNING_CLK_64 = 0x3,
+                ///  Running, CLK/256
+                RUNNING_CLK_256 = 0x4,
+                ///  Running, CLK/1024
+                RUNNING_CLK_1024 = 0x5,
+                ///  Running, ExtClk Tn Falling Edge
+                RUNNING_EXTCLK_TN_FALLING_EDGE = 0x6,
+                ///  Running, ExtClk Tn Rising Edge
+                RUNNING_EXTCLK_TN_RISING_EDGE = 0x7,
+            };
+
+            ///  Timer/Counter, 16-bit
+            pub const TC1 = extern struct {
+                ///  Timer/Counter Interrupt Flag register
+                TIFR1: mmio.Mmio(packed struct(u8) {
+                    ///  Timer/Counter1 Overflow Flag
+                    TOV1: u1,
+                    ///  Output Compare Flag 1A
+                    OCF1A: u1,
+                    ///  Output Compare Flag 1B
+                    OCF1B: u1,
+                    reserved5: u2,
+                    ///  Input Capture Flag 1
+                    ICF1: u1,
+                    padding: u2,
+                }),
+                reserved13: [12]u8,
+                ///  General Timer/Counter Control Register
+                GTCCR: mmio.Mmio(packed struct(u8) {
+                    ///  Prescaler Reset Timer/Counter1 and Timer/Counter0
+                    PSRSYNC: u1,
+                    reserved7: u6,
+                    ///  Timer/Counter Synchronization Mode
+                    TSM: u1,
+                }),
+                reserved57: [43]u8,
+                ///  Timer/Counter Interrupt Mask Register
+                TIMSK1: mmio.Mmio(packed struct(u8) {
+                    ///  Timer/Counter1 Overflow Interrupt Enable
+                    TOIE1: u1,
+                    ///  Timer/Counter1 Output CompareA Match Interrupt Enable
+                    OCIE1A: u1,
+                    ///  Timer/Counter1 Output CompareB Match Interrupt Enable
+                    OCIE1B: u1,
+                    reserved5: u2,
+                    ///  Timer/Counter1 Input Capture Interrupt Enable
+                    ICIE1: u1,
+                    padding: u2,
+                }),
+                reserved74: [16]u8,
+                ///  Timer/Counter1 Control Register A
+                TCCR1A: mmio.Mmio(packed struct(u8) {
+                    ///  Waveform Generation Mode
+                    WGM1: u2,
+                    reserved4: u2,
+                    ///  Compare Output Mode 1B, bits
+                    COM1B: u2,
+                    ///  Compare Output Mode 1A, bits
+                    COM1A: u2,
+                }),
+                ///  Timer/Counter1 Control Register B
+                TCCR1B: mmio.Mmio(packed struct(u8) {
+                    ///  Prescaler source of Timer/Counter 1
+                    CS1: packed union {
+                        raw: u3,
+                        value: CLK_SEL_3BIT_EXT,
+                    },
+                    ///  Waveform Generation Mode
+                    WGM1: u2,
+                    reserved6: u1,
+                    ///  Input Capture 1 Edge Select
+                    ICES1: u1,
+                    ///  Input Capture 1 Noise Canceler
+                    ICNC1: u1,
+                }),
+                ///  Timer/Counter1 Control Register C
+                TCCR1C: mmio.Mmio(packed struct(u8) {
+                    reserved6: u6,
+                    FOC1B: u1,
+                    FOC1A: u1,
+                }),
+                reserved78: [1]u8,
+                ///  Timer/Counter1 Bytes
+                TCNT1: u16,
+                ///  Timer/Counter1 Input Capture Register Bytes
+                ICR1: u16,
+                ///  Timer/Counter1 Output Compare Register Bytes
+                OCR1A: u16,
+                ///  Timer/Counter1 Output Compare Register Bytes
+                OCR1B: u16,
+            };
+        };
+
+        ///  Timer/Counter, 8-bit Async
+        pub const TC8_ASYNC = struct {
+            pub const CLK_SEL_3BIT = enum(u3) {
+                ///  No Clock Source (Stopped)
+                NO_CLOCK_SOURCE_STOPPED = 0x0,
+                ///  Running, No Prescaling
+                RUNNING_NO_PRESCALING = 0x1,
+                ///  Running, CLK/8
+                RUNNING_CLK_8 = 0x2,
+                ///  Running, CLK/32
+                RUNNING_CLK_32 = 0x3,
+                ///  Running, CLK/64
+                RUNNING_CLK_64 = 0x4,
+                ///  Running, CLK/128
+                RUNNING_CLK_128 = 0x5,
+                ///  Running, CLK/256
+                RUNNING_CLK_256 = 0x6,
+                ///  Running, CLK/1024
+                RUNNING_CLK_1024 = 0x7,
+            };
+
+            ///  Timer/Counter, 8-bit Async
+            pub const TC2 = extern struct {
+                ///  Timer/Counter Interrupt Flag Register
+                TIFR2: mmio.Mmio(packed struct(u8) {
+                    ///  Timer/Counter2 Overflow Flag
+                    TOV2: u1,
+                    ///  Output Compare Flag 2A
+                    OCF2A: u1,
+                    ///  Output Compare Flag 2B
+                    OCF2B: u1,
+                    padding: u5,
+                }),
+                reserved12: [11]u8,
+                ///  General Timer Counter Control register
+                GTCCR: mmio.Mmio(packed struct(u8) {
+                    reserved1: u1,
+                    ///  Prescaler Reset Timer/Counter2
+                    PSRASY: u1,
+                    reserved7: u5,
+                    ///  Timer/Counter Synchronization Mode
+                    TSM: u1,
+                }),
+                reserved57: [44]u8,
+                ///  Timer/Counter Interrupt Mask register
+                TIMSK2: mmio.Mmio(packed struct(u8) {
+                    ///  Timer/Counter2 Overflow Interrupt Enable
+                    TOIE2: u1,
+                    ///  Timer/Counter2 Output Compare Match A Interrupt Enable
+                    OCIE2A: u1,
+                    ///  Timer/Counter2 Output Compare Match B Interrupt Enable
+                    OCIE2B: u1,
+                    padding: u5,
+                }),
+                reserved121: [63]u8,
+                ///  Timer/Counter2 Control Register A
+                TCCR2A: mmio.Mmio(packed struct(u8) {
+                    ///  Waveform Genration Mode
+                    WGM2: u2,
+                    reserved4: u2,
+                    ///  Compare Output Mode bits
+                    COM2B: u2,
+                    ///  Compare Output Mode bits
+                    COM2A: u2,
+                }),
+                ///  Timer/Counter2 Control Register B
+                TCCR2B: mmio.Mmio(packed struct(u8) {
+                    ///  Clock Select bits
+                    CS2: packed union {
+                        raw: u3,
+                        value: CLK_SEL_3BIT,
+                    },
+                    ///  Waveform Generation Mode
+                    WGM22: u1,
+                    reserved6: u2,
+                    ///  Force Output Compare B
+                    FOC2B: u1,
+                    ///  Force Output Compare A
+                    FOC2A: u1,
+                }),
+                ///  Timer/Counter2
+                TCNT2: u8,
+                ///  Timer/Counter2 Output Compare Register A
+                OCR2A: u8,
+                ///  Timer/Counter2 Output Compare Register B
+                OCR2B: u8,
+                reserved127: [1]u8,
+                ///  Asynchronous Status Register
+                ASSR: mmio.Mmio(packed struct(u8) {
+                    ///  Timer/Counter Control Register2 Update Busy
+                    TCR2BUB: u1,
+                    ///  Timer/Counter Control Register2 Update Busy
+                    TCR2AUB: u1,
+                    ///  Output Compare Register 2 Update Busy
+                    OCR2BUB: u1,
+                    ///  Output Compare Register2 Update Busy
+                    OCR2AUB: u1,
+                    ///  Timer/Counter2 Update Busy
+                    TCN2UB: u1,
+                    ///  Asynchronous Timer/Counter2
+                    AS2: u1,
+                    ///  Enable External Clock Input
+                    EXCLK: u1,
+                    padding: u1,
+                }),
+            };
+        };
+
+        ///  Analog-to-Digital Converter
+        pub const ADC = extern struct {
+            pub const ANALOG_ADC_V_REF3 = enum(u2) {
+                ///  AREF, Internal Vref turned off
+                AREF_INTERNAL_VREF_TURNED_OFF = 0x0,
+                ///  AVCC with external capacitor at AREF pin
+                AVCC_WITH_EXTERNAL_CAPACITOR_AT_AREF_PIN = 0x1,
+                ///  Reserved
+                RESERVED = 0x2,
+                ///  Internal 1.1V Voltage Reference with external capacitor at AREF pin
+                INTERNAL_1_1V_VOLTAGE_REFERENCE_WITH_EXTERNAL_CAPACITOR_AT_AREF_PIN = 0x3,
+            };
+
+            pub const ADC_MUX_SINGLE = enum(u4) {
+                ///  ADC Single Ended Input pin 0
+                ADC0 = 0x0,
+                ///  ADC Single Ended Input pin 1
+                ADC1 = 0x1,
+                ///  ADC Single Ended Input pin 2
+                ADC2 = 0x2,
+                ///  ADC Single Ended Input pin 3
+                ADC3 = 0x3,
+                ///  ADC Single Ended Input pin 4
+                ADC4 = 0x4,
+                ///  ADC Single Ended Input pin 5
+                ADC5 = 0x5,
+                ///  ADC Single Ended Input pin 6
+                ADC6 = 0x6,
+                ///  ADC Single Ended Input pin 7
+                ADC7 = 0x7,
+                ///  Temperature sensor
+                TEMPSENS = 0x8,
+                ///  Internal Reference (VBG)
+                ADC_VBG = 0xe,
+                ///  0V (GND)
+                ADC_GND = 0xf,
+                _,
+            };
+
+            pub const ANALOG_ADC_PRESCALER = enum(u3) {
+                ///  2
+                @"2" = 0x0,
+                ///  2
+                @"2" = 0x1,
+                ///  4
+                @"4" = 0x2,
+                ///  8
+                @"8" = 0x3,
+                ///  16
+                @"16" = 0x4,
+                ///  32
+                @"32" = 0x5,
+                ///  64
+                @"64" = 0x6,
+                ///  128
+                @"128" = 0x7,
+            };
+
+            pub const ANALOG_ADC_AUTO_TRIGGER = enum(u3) {
+                ///  Free Running mode
+                FREE_RUNNING_MODE = 0x0,
+                ///  Analog Comparator
+                ANALOG_COMPARATOR = 0x1,
+                ///  External Interrupt Request 0
+                EXTERNAL_INTERRUPT_REQUEST_0 = 0x2,
+                ///  Timer/Counter0 Compare Match A
+                TIMER_COUNTER0_COMPARE_MATCH_A = 0x3,
+                ///  Timer/Counter0 Overflow
+                TIMER_COUNTER0_OVERFLOW = 0x4,
+                ///  Timer/Counter1 Compare Match B
+                TIMER_COUNTER1_COMPARE_MATCH_B = 0x5,
+                ///  Timer/Counter1 Overflow
+                TIMER_COUNTER1_OVERFLOW = 0x6,
+                ///  Timer/Counter1 Capture Event
+                TIMER_COUNTER1_CAPTURE_EVENT = 0x7,
+            };
+
+            ///  ADC Data Register Bytes
+            ADC: u16,
+            ///  The ADC Control and Status register A
+            ADCSRA: mmio.Mmio(packed struct(u8) {
+                ///  ADC Prescaler Select Bits
+                ADPS: packed union {
+                    raw: u3,
+                    value: ANALOG_ADC_PRESCALER,
+                },
+                ///  ADC Interrupt Enable
+                ADIE: u1,
+                ///  ADC Interrupt Flag
+                ADIF: u1,
+                ///  ADC Auto Trigger Enable
+                ADATE: u1,
+                ///  ADC Start Conversion
+                ADSC: u1,
+                ///  ADC Enable
+                ADEN: u1,
+            }),
+            ///  The ADC Control and Status register B
+            ADCSRB: mmio.Mmio(packed struct(u8) {
+                ///  ADC Auto Trigger Source bits
+                ADTS: packed union {
+                    raw: u3,
+                    value: ANALOG_ADC_AUTO_TRIGGER,
+                },
+                reserved6: u3,
+                ACME: u1,
+                padding: u1,
+            }),
+            ///  The ADC multiplexer Selection Register
+            ADMUX: mmio.Mmio(packed struct(u8) {
+                ///  Analog Channel Selection Bits
+                MUX: packed union {
+                    raw: u4,
+                    value: ADC_MUX_SINGLE,
+                },
+                reserved5: u1,
+                ///  Left Adjust Result
+                ADLAR: u1,
+                ///  Reference Selection Bits
+                REFS: packed union {
+                    raw: u2,
+                    value: ANALOG_ADC_V_REF3,
+                },
+            }),
+            reserved6: [1]u8,
+            ///  Digital Input Disable Register
+            DIDR0: mmio.Mmio(packed struct(u8) {
+                ADC0D: u1,
+                ADC1D: u1,
+                ADC2D: u1,
+                ADC3D: u1,
+                ADC4D: u1,
+                ADC5D: u1,
+                padding: u2,
+            }),
+        };
+
+        ///  Analog Comparator
+        pub const AC = extern struct {
+            pub const ANALOG_COMP_INTERRUPT = enum(u2) {
+                ///  Interrupt on Toggle
+                INTERRUPT_ON_TOGGLE = 0x0,
+                ///  Reserved
+                RESERVED = 0x1,
+                ///  Interrupt on Falling Edge
+                INTERRUPT_ON_FALLING_EDGE = 0x2,
+                ///  Interrupt on Rising Edge
+                INTERRUPT_ON_RISING_EDGE = 0x3,
+            };
+
+            ///  Analog Comparator Control And Status Register
+            ACSR: mmio.Mmio(packed struct(u8) {
+                ///  Analog Comparator Interrupt Mode Select bits
+                ACIS: packed union {
+                    raw: u2,
+                    value: ANALOG_COMP_INTERRUPT,
+                },
+                ///  Analog Comparator Input Capture Enable
+                ACIC: u1,
+                ///  Analog Comparator Interrupt Enable
+                ACIE: u1,
+                ///  Analog Comparator Interrupt Flag
+                ACI: u1,
+                ///  Analog Compare Output
+                ACO: u1,
+                ///  Analog Comparator Bandgap Select
+                ACBG: u1,
+                ///  Analog Comparator Disable
+                ACD: u1,
+            }),
+            reserved47: [46]u8,
+            ///  Digital Input Disable Register 1
+            DIDR1: mmio.Mmio(packed struct(u8) {
+                ///  AIN0 Digital Input Disable
+                AIN0D: u1,
+                ///  AIN1 Digital Input Disable
+                AIN1D: u1,
+                padding: u6,
+            }),
+        };
+
+        ///  I/O Port
+        pub const PORT = struct {
+            ///  I/O Port
+            pub const PORTB = extern struct {
+                ///  Port B Input Pins
+                PINB: u8,
+                ///  Port B Data Direction Register
+                DDRB: u8,
+                ///  Port B Data Register
+                PORTB: u8,
+            };
+
+            ///  I/O Port
+            pub const PORTC = extern struct {
+                ///  Port C Input Pins
+                PINC: u8,
+                ///  Port C Data Direction Register
+                DDRC: u8,
+                ///  Port C Data Register
+                PORTC: u8,
+            };
+
+            ///  I/O Port
+            pub const PORTD = extern struct {
+                ///  Port D Input Pins
+                PIND: u8,
+                ///  Port D Data Direction Register
+                DDRD: u8,
+                ///  Port D Data Register
+                PORTD: u8,
+            };
+        };
+
+        ///  Timer/Counter, 8-bit
+        pub const TC8 = struct {
+            pub const CLK_SEL_3BIT_EXT = enum(u3) {
+                ///  No Clock Source (Stopped)
+                NO_CLOCK_SOURCE_STOPPED = 0x0,
+                ///  Running, No Prescaling
+                RUNNING_NO_PRESCALING = 0x1,
+                ///  Running, CLK/8
+                RUNNING_CLK_8 = 0x2,
+                ///  Running, CLK/64
+                RUNNING_CLK_64 = 0x3,
+                ///  Running, CLK/256
+                RUNNING_CLK_256 = 0x4,
+                ///  Running, CLK/1024
+                RUNNING_CLK_1024 = 0x5,
+                ///  Running, ExtClk Tn Falling Edge
+                RUNNING_EXTCLK_TN_FALLING_EDGE = 0x6,
+                ///  Running, ExtClk Tn Rising Edge
+                RUNNING_EXTCLK_TN_RISING_EDGE = 0x7,
+            };
+
+            ///  Timer/Counter, 8-bit
+            pub const TC0 = extern struct {
+                ///  Timer/Counter0 Interrupt Flag register
+                TIFR0: mmio.Mmio(packed struct(u8) {
+                    ///  Timer/Counter0 Overflow Flag
+                    TOV0: u1,
+                    ///  Timer/Counter0 Output Compare Flag 0A
+                    OCF0A: u1,
+                    ///  Timer/Counter0 Output Compare Flag 0B
+                    OCF0B: u1,
+                    padding: u5,
+                }),
+                reserved14: [13]u8,
+                ///  General Timer/Counter Control Register
+                GTCCR: mmio.Mmio(packed struct(u8) {
+                    ///  Prescaler Reset Timer/Counter1 and Timer/Counter0
+                    PSRSYNC: u1,
+                    reserved7: u6,
+                    ///  Timer/Counter Synchronization Mode
+                    TSM: u1,
+                }),
+                ///  Timer/Counter Control Register A
+                TCCR0A: mmio.Mmio(packed struct(u8) {
+                    ///  Waveform Generation Mode
+                    WGM0: u2,
+                    reserved4: u2,
+                    ///  Compare Output Mode, Fast PWm
+                    COM0B: u2,
+                    ///  Compare Output Mode, Phase Correct PWM Mode
+                    COM0A: u2,
+                }),
+                ///  Timer/Counter Control Register B
+                TCCR0B: mmio.Mmio(packed struct(u8) {
+                    ///  Clock Select
+                    CS0: packed union {
+                        raw: u3,
+                        value: CLK_SEL_3BIT_EXT,
+                    },
+                    WGM02: u1,
+                    reserved6: u2,
+                    ///  Force Output Compare B
+                    FOC0B: u1,
+                    ///  Force Output Compare A
+                    FOC0A: u1,
+                }),
+                ///  Timer/Counter0
+                TCNT0: u8,
+                ///  Timer/Counter0 Output Compare Register
+                OCR0A: u8,
+                ///  Timer/Counter0 Output Compare Register
+                OCR0B: u8,
+                reserved57: [37]u8,
+                ///  Timer/Counter0 Interrupt Mask Register
+                TIMSK0: mmio.Mmio(packed struct(u8) {
+                    ///  Timer/Counter0 Overflow Interrupt Enable
+                    TOIE0: u1,
+                    ///  Timer/Counter0 Output Compare Match A Interrupt Enable
+                    OCIE0A: u1,
+                    ///  Timer/Counter0 Output Compare Match B Interrupt Enable
+                    OCIE0B: u1,
+                    padding: u5,
+                }),
+            };
+        };
+
+        ///  External Interrupts
+        pub const EXINT = extern struct {
+            ///  Interrupt Sense Control
+            pub const INTERRUPT_SENSE_CONTROL = enum(u2) {
+                ///  Low Level of INTX
+                LOW_LEVEL_OF_INTX = 0x0,
+                ///  Any Logical Change of INTX
+                ANY_LOGICAL_CHANGE_OF_INTX = 0x1,
+                ///  Falling Edge of INTX
+                FALLING_EDGE_OF_INTX = 0x2,
+                ///  Rising Edge of INTX
+                RISING_EDGE_OF_INTX = 0x3,
+            };
+
+            ///  Pin Change Interrupt Flag Register
+            PCIFR: mmio.Mmio(packed struct(u8) {
+                ///  Pin Change Interrupt Flags
+                PCIF: u3,
+                padding: u5,
+            }),
+            ///  External Interrupt Flag Register
+            EIFR: mmio.Mmio(packed struct(u8) {
+                ///  External Interrupt Flags
+                INTF: u2,
+                padding: u6,
+            }),
+            ///  External Interrupt Mask Register
+            EIMSK: mmio.Mmio(packed struct(u8) {
+                ///  External Interrupt Request 1 Enable
+                INT: u2,
+                padding: u6,
+            }),
+            reserved45: [42]u8,
+            ///  Pin Change Interrupt Control Register
+            PCICR: mmio.Mmio(packed struct(u8) {
+                ///  Pin Change Interrupt Enables
+                PCIE: u3,
+                padding: u5,
+            }),
+            ///  External Interrupt Control Register
+            EICRA: mmio.Mmio(packed struct(u8) {
+                ///  External Interrupt Sense Control 0 Bits
+                ISC0: packed union {
+                    raw: u2,
+                    value: INTERRUPT_SENSE_CONTROL,
+                },
+                ///  External Interrupt Sense Control 1 Bits
+                ISC1: packed union {
+                    raw: u2,
+                    value: INTERRUPT_SENSE_CONTROL,
+                },
+                padding: u4,
+            }),
+            reserved48: [1]u8,
+            ///  Pin Change Mask Register 0
+            PCMSK0: mmio.Mmio(packed struct(u8) {
+                ///  Pin Change Enable Masks
+                PCINT: u8,
+            }),
+            ///  Pin Change Mask Register 1
+            PCMSK1: mmio.Mmio(packed struct(u8) {
+                ///  Pin Change Enable Masks
+                PCINT: u7,
+                padding: u1,
+            }),
+            ///  Pin Change Mask Register 2
+            PCMSK2: mmio.Mmio(packed struct(u8) {
+                ///  Pin Change Enable Masks
+                PCINT: u8,
+            }),
+        };
+
+        ///  Serial Peripheral Interface
+        pub const SPI = extern struct {
+            pub const COMM_SCK_RATE_3BIT = enum(u2) {
+                ///  fosc/2 or fosc/4
+                FOSC_2_OR_FOSC_4 = 0x0,
+                ///  fosc/8 or fosc/16
+                FOSC_8_OR_FOSC_16 = 0x1,
+                ///  fosc/32 or fosc/64
+                FOSC_32_OR_FOSC_64 = 0x2,
+                ///  fosc/64 or fosc/128
+                FOSC_64_OR_FOSC_128 = 0x3,
+            };
+
+            ///  SPI Control Register
+            SPCR: mmio.Mmio(packed struct(u8) {
+                ///  SPI Clock Rate Selects
+                SPR: packed union {
+                    raw: u2,
+                    value: COMM_SCK_RATE_3BIT,
+                },
+                ///  Clock Phase
+                CPHA: u1,
+                ///  Clock polarity
+                CPOL: u1,
+                ///  Master/Slave Select
+                MSTR: u1,
+                ///  Data Order
+                DORD: u1,
+                ///  SPI Enable
+                SPE: u1,
+                ///  SPI Interrupt Enable
+                SPIE: u1,
+            }),
+            ///  SPI Status Register
+            SPSR: mmio.Mmio(packed struct(u8) {
+                ///  Double SPI Speed Bit
+                SPI2X: u1,
+                reserved6: u5,
+                ///  Write Collision Flag
+                WCOL: u1,
+                ///  SPI Interrupt Flag
+                SPIF: u1,
+            }),
+            ///  SPI Data Register
+            SPDR: u8,
+        };
+
+        ///  Watchdog Timer
+        pub const WDT = extern struct {
+            pub const WDOG_TIMER_PRESCALE_4BITS = enum(u4) {
+                ///  Oscillator Cycles 2K
+                OSCILLATOR_CYCLES_2K = 0x0,
+                ///  Oscillator Cycles 4K
+                OSCILLATOR_CYCLES_4K = 0x1,
+                ///  Oscillator Cycles 8K
+                OSCILLATOR_CYCLES_8K = 0x2,
+                ///  Oscillator Cycles 16K
+                OSCILLATOR_CYCLES_16K = 0x3,
+                ///  Oscillator Cycles 32K
+                OSCILLATOR_CYCLES_32K = 0x4,
+                ///  Oscillator Cycles 64K
+                OSCILLATOR_CYCLES_64K = 0x5,
+                ///  Oscillator Cycles 128K
+                OSCILLATOR_CYCLES_128K = 0x6,
+                ///  Oscillator Cycles 256K
+                OSCILLATOR_CYCLES_256K = 0x7,
+                ///  Oscillator Cycles 512K
+                OSCILLATOR_CYCLES_512K = 0x8,
+                ///  Oscillator Cycles 1024K
+                OSCILLATOR_CYCLES_1024K = 0x9,
+                _,
+            };
+
+            ///  Watchdog Timer Control Register
+            WDTCSR: mmio.Mmio(packed struct(u8) {
+                ///  Watchdog Timer Prescaler Bits
+                WDP_bit0: u1,
+                ///  Watchdog Timer Prescaler Bits
+                WDP_bit1: u1,
+                ///  Watchdog Timer Prescaler Bits
+                WDP_bit2: u1,
+                ///  Watch Dog Enable
+                WDE: u1,
+                ///  Watchdog Change Enable
+                WDCE: u1,
+                ///  Watchdog Timer Prescaler Bits
+                WDP_bit3: u1,
+                ///  Watchdog Timeout Interrupt Enable
+                WDIE: u1,
+                ///  Watchdog Timeout Interrupt Flag
+                WDIF: u1,
+            }),
+        };
+
+        ///  CPU Registers
+        pub const CPU = extern struct {
+            pub const CPU_CLK_PRESCALE_4_BITS_SMALL = enum(u4) {
+                ///  1
+                @"1" = 0x0,
+                ///  2
+                @"2" = 0x1,
+                ///  4
+                @"4" = 0x2,
+                ///  8
+                @"8" = 0x3,
+                ///  16
+                @"16" = 0x4,
+                ///  32
+                @"32" = 0x5,
+                ///  64
+                @"64" = 0x6,
+                ///  128
+                @"128" = 0x7,
+                ///  256
+                @"256" = 0x8,
+                _,
+            };
+
+            pub const CPU_SLEEP_MODE_3BITS2 = enum(u3) {
+                ///  Idle
+                IDLE = 0x0,
+                ///  ADC Noise Reduction (If Available)
+                ADC = 0x1,
+                ///  Power Down
+                PDOWN = 0x2,
+                ///  Power Save
+                PSAVE = 0x3,
+                ///  Reserved
+                VAL_0x04 = 0x4,
+                ///  Reserved
+                VAL_0x05 = 0x5,
+                ///  Standby
+                STDBY = 0x6,
+                ///  Extended Standby
+                ESTDBY = 0x7,
+            };
+
+            ///  Oscillator Calibration Values
+            pub const OSCCAL_VALUE_ADDRESSES = enum(u1) {
+                ///  8.0 MHz
+                @"8_0_MHz" = 0x0,
+                _,
+            };
+
+            ///  General Purpose I/O Register 0
+            GPIOR0: u8,
+            reserved12: [11]u8,
+            ///  General Purpose I/O Register 1
+            GPIOR1: u8,
+            ///  General Purpose I/O Register 2
+            GPIOR2: u8,
+            reserved21: [7]u8,
+            ///  Sleep Mode Control Register
+            SMCR: mmio.Mmio(packed struct(u8) {
+                ///  Sleep Enable
+                SE: u1,
+                ///  Sleep Mode Select Bits
+                SM: packed union {
+                    raw: u3,
+                    value: CPU_SLEEP_MODE_3BITS2,
+                },
+                padding: u4,
+            }),
+            ///  MCU Status Register
+            MCUSR: mmio.Mmio(packed struct(u8) {
+                ///  Power-on reset flag
+                PORF: u1,
+                ///  External Reset Flag
+                EXTRF: u1,
+                ///  Brown-out Reset Flag
+                BORF: u1,
+                ///  Watchdog Reset Flag
+                WDRF: u1,
+                padding: u4,
+            }),
+            ///  MCU Control Register
+            MCUCR: mmio.Mmio(packed struct(u8) {
+                IVCE: u1,
+                IVSEL: u1,
+                reserved4: u2,
+                PUD: u1,
+                ///  BOD Sleep Enable
+                BODSE: u1,
+                ///  BOD Sleep
+                BODS: u1,
+                padding: u1,
+            }),
+            reserved25: [1]u8,
+            ///  Store Program Memory Control and Status Register
+            SPMCSR: mmio.Mmio(packed struct(u8) {
+                ///  Store Program Memory
+                SPMEN: u1,
+                ///  Page Erase
+                PGERS: u1,
+                ///  Page Write
+                PGWRT: u1,
+                ///  Boot Lock Bit Set
+                BLBSET: u1,
+                ///  Read-While-Write section read enable
+                RWWSRE: u1,
+                ///  Signature Row Read
+                SIGRD: u1,
+                ///  Read-While-Write Section Busy
+                RWWSB: u1,
+                ///  SPM Interrupt Enable
+                SPMIE: u1,
+            }),
+            reserved31: [5]u8,
+            ///  Stack Pointer
+            SP: u16,
+            ///  Status Register
+            SREG: mmio.Mmio(packed struct(u8) {
+                ///  Carry Flag
+                C: u1,
+                ///  Zero Flag
+                Z: u1,
+                ///  Negative Flag
+                N: u1,
+                ///  Two's Complement Overflow Flag
+                V: u1,
+                ///  Sign Bit
+                S: u1,
+                ///  Half Carry Flag
+                H: u1,
+                ///  Bit Copy Storage
+                T: u1,
+                ///  Global Interrupt Enable
+                I: u1,
+            }),
+            reserved35: [1]u8,
+            ///  Clock Prescale Register
+            CLKPR: mmio.Mmio(packed struct(u8) {
+                ///  Clock Prescaler Select Bits
+                CLKPS: packed union {
+                    raw: u4,
+                    value: CPU_CLK_PRESCALE_4_BITS_SMALL,
+                },
+                reserved7: u3,
+                ///  Clock Prescaler Change Enable
+                CLKPCE: u1,
+            }),
+            reserved38: [2]u8,
+            ///  Power Reduction Register
+            PRR: mmio.Mmio(packed struct(u8) {
+                ///  Power Reduction ADC
+                PRADC: u1,
+                ///  Power Reduction USART
+                PRUSART0: u1,
+                ///  Power Reduction Serial Peripheral Interface
+                PRSPI: u1,
+                ///  Power Reduction Timer/Counter1
+                PRTIM1: u1,
+                reserved5: u1,
+                ///  Power Reduction Timer/Counter0
+                PRTIM0: u1,
+                ///  Power Reduction Timer/Counter2
+                PRTIM2: u1,
+                ///  Power Reduction TWI
+                PRTWI: u1,
+            }),
+            reserved40: [1]u8,
+            ///  Oscillator Calibration Value
+            OSCCAL: mmio.Mmio(packed struct(u8) {
+                ///  Oscillator Calibration
+                OSCCAL: u8,
+            }),
+        };
+
+        ///  EEPROM
+        pub const EEPROM = extern struct {
+            pub const EEP_MODE = enum(u2) {
+                ///  Erase and Write in one operation
+                ERASE_AND_WRITE_IN_ONE_OPERATION = 0x0,
+                ///  Erase Only
+                ERASE_ONLY = 0x1,
+                ///  Write Only
+                WRITE_ONLY = 0x2,
+                _,
+            };
+
+            ///  EEPROM Control Register
+            EECR: mmio.Mmio(packed struct(u8) {
+                ///  EEPROM Read Enable
+                EERE: u1,
+                ///  EEPROM Write Enable
+                EEPE: u1,
+                ///  EEPROM Master Write Enable
+                EEMPE: u1,
+                ///  EEPROM Ready Interrupt Enable
+                EERIE: u1,
+                ///  EEPROM Programming Mode Bits
+                EEPM: packed union {
+                    raw: u2,
+                    value: EEP_MODE,
+                },
+                padding: u2,
+            }),
+            ///  EEPROM Data Register
+            EEDR: u8,
+            ///  EEPROM Address Register Bytes
+            EEAR: u16,
+        };
+    };
+};
diff --git a/src/hals/ATmega328P.zig b/src/hals/ATmega328P.zig
new file mode 100644
index 000000000..b836c651c
--- /dev/null
+++ b/src/hals/ATmega328P.zig
@@ -0,0 +1,191 @@
+const std = @import("std");
+const micro = @import("microzig");
+
+pub usingnamespace @import("registers.zig");
+const regz = @import("registers.zig").registers;
+
+pub const cpu = micro.cpu;
+const Port = enum(u8) {
+    B = 1,
+    C = 2,
+    D = 3,
+};
+
+pub const clock = struct {
+    pub const Domain = enum {
+        cpu,
+    };
+};
+
+pub fn parsePin(comptime spec: []const u8) type {
+    const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme.";
+
+    if (spec.len != 3)
+        @compileError(invalid_format_msg);
+    if (spec[0] != 'P')
+        @compileError(invalid_format_msg);
+
+    return struct {
+        pub const port: Port = std.meta.stringToEnum(Port, spec[1..2]) orelse @compileError(invalid_format_msg);
+        pub const pin: u3 = std.fmt.parseInt(u3, spec[2..3], 10) catch @compileError(invalid_format_msg);
+    };
+}
+
+pub const gpio = struct {
+    fn regs(comptime desc: type) type {
+        return struct {
+            // io address
+            const pin_addr: u5 = 3 * @enumToInt(desc.port) + 0x00;
+            const dir_addr: u5 = 3 * @enumToInt(desc.port) + 0x01;
+            const port_addr: u5 = 3 * @enumToInt(desc.port) + 0x02;
+
+            // ram mapping
+            const pin = @intToPtr(*volatile u8, 0x20 + @as(usize, pin_addr));
+            const dir = @intToPtr(*volatile u8, 0x20 + @as(usize, dir_addr));
+            const port = @intToPtr(*volatile u8, 0x20 + @as(usize, port_addr));
+        };
+    }
+
+    pub fn setOutput(comptime pin: type) void {
+        cpu.sbi(regs(pin).dir_addr, pin.pin);
+    }
+
+    pub fn setInput(comptime pin: type) void {
+        cpu.cbi(regs(pin).dir_addr, pin.pin);
+    }
+
+    pub fn read(comptime pin: type) micro.gpio.State {
+        return if ((regs(pin).pin.* & (1 << pin.pin)) != 0)
+            .high
+        else
+            .low;
+    }
+
+    pub fn write(comptime pin: type, state: micro.gpio.State) void {
+        if (state == .high) {
+            cpu.sbi(regs(pin).port_addr, pin.pin);
+        } else {
+            cpu.cbi(regs(pin).port_addr, pin.pin);
+        }
+    }
+
+    pub fn toggle(comptime pin: type) void {
+        cpu.sbi(regs(pin).pin_addr, pin.pin);
+    }
+};
+
+pub const uart = struct {
+    pub const DataBits = enum {
+        five,
+        six,
+        seven,
+        eight,
+        nine,
+    };
+
+    pub const StopBits = enum {
+        one,
+        two,
+    };
+
+    pub const Parity = enum {
+        odd,
+        even,
+    };
+};
+
+pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
+    if (index != 0) @compileError("Atmega328p only has a single uart!");
+    if (pins.tx != null or pins.rx != null)
+        @compileError("Atmega328p has fixed pins for uart!");
+
+    return struct {
+        const Self = @This();
+
+        fn computeDivider(baud_rate: u32) !u12 {
+            const pclk = micro.clock.get().cpu;
+            const divider = ((pclk + (8 * baud_rate)) / (16 * baud_rate)) - 1;
+
+            return std.math.cast(u12, divider) orelse return error.UnsupportedBaudRate;
+        }
+
+        fn computeBaudRate(divider: u12) u32 {
+            return micro.clock.get().cpu / (16 * @as(u32, divider) + 1);
+        }
+
+        pub fn init(config: micro.uart.Config) !Self {
+            const ucsz: u3 = switch (config.data_bits) {
+                .five => 0b000,
+                .six => 0b001,
+                .seven => 0b010,
+                .eight => 0b011,
+                .nine => return error.UnsupportedWordSize, // 0b111
+            };
+
+            const upm: u2 = if (config.parity) |parity| switch (parity) {
+                .even => @as(u2, 0b10), // even
+                .odd => @as(u2, 0b11), // odd
+            } else 0b00; // parity disabled
+
+            const usbs: u1 = switch (config.stop_bits) {
+                .one => 0b0,
+                .two => 0b1,
+            };
+
+            const umsel: u2 = 0b00; // Asynchronous USART
+
+            // baud is computed like this:
+            //             f(osc)
+            // BAUD = ----------------
+            //        16 * (UBRRn + 1)
+
+            const ubrr_val = try computeDivider(config.baud_rate);
+
+            regz.USART0.UCSR0A.modify(.{
+                .MPCM0 = 0,
+                .U2X0 = 0,
+            });
+            regz.USART0.UCSR0B.write(.{
+                .TXB80 = 0, // we don't care about these btw
+                .RXB80 = 0, // we don't care about these btw
+                .UCSZ02 = @truncate(u1, (ucsz & 0x04) >> 2),
+                .TXEN0 = 1,
+                .RXEN0 = 1,
+                .UDRIE0 = 0, // no interrupts
+                .TXCIE0 = 0, // no interrupts
+                .RXCIE0 = 0, // no interrupts
+            });
+            regz.USART0.UCSR0C.write(.{
+                .UCPOL0 = 0, // async mode
+                .UCSZ0 = @truncate(u2, (ucsz & 0x03) >> 0),
+                .USBS0 = usbs,
+                .UPM0 = upm,
+                .UMSEL0 = umsel,
+            });
+
+            regz.USART0.UBRR0.modify(ubrr_val);
+
+            return Self{};
+        }
+
+        pub fn canWrite(self: Self) bool {
+            _ = self;
+            return (regz.USART0.UCSR0A.read().UDRE0 == 1);
+        }
+
+        pub fn tx(self: Self, ch: u8) void {
+            while (!self.canWrite()) {} // Wait for Previous transmission
+            regz.USART0.UDR0.* = ch; // Load the data to be transmitted
+        }
+
+        pub fn canRead(self: Self) bool {
+            _ = self;
+            return (regz.USART0.UCSR0A.read().RXC0 == 1);
+        }
+
+        pub fn rx(self: Self) u8 {
+            while (!self.canRead()) {} // Wait till the data is received
+            return regz.USART0.UDR0.*; // Read received data
+        }
+    };
+}

From 56e3d88bc0a0ebda41588f906a25437592d7f3a9 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sat, 18 Feb 2023 18:06:45 -0500
Subject: [PATCH 046/286] add chips and board (#1)

* add chips and board

* fix up hal
---
 LICENSE                    |     2 +-
 README.adoc                |     7 +-
 src/boards.zig             |     9 +-
 src/boards/longan_nano.zig |   112 +
 src/chips.zig              |    24 +-
 src/chips/GD32VF103.json   | 32957 +++++++++++++++++++++++++++++++++++
 src/chips/GD32VF103.zig    | 12849 ++++++++++++++
 src/hals/GD32VF103.zig     |   112 +
 8 files changed, 46062 insertions(+), 10 deletions(-)
 create mode 100644 src/boards/longan_nano.zig
 create mode 100644 src/chips/GD32VF103.json
 create mode 100644 src/chips/GD32VF103.zig
 create mode 100644 src/hals/GD32VF103.zig

diff --git a/LICENSE b/LICENSE
index c1cc5ecad..bcb425d88 100644
--- a/LICENSE
+++ b/LICENSE
@@ -1,4 +1,4 @@
-Copyright (c) 2022 
+Copyright (c) 2022 Zig Embedded Group Contributors
 
 This software is provided 'as-is', without any express or implied warranty. In
 no event will the authors be held liable for any damages arising from the use
diff --git a/README.adoc b/README.adoc
index 46ca05775..f23b1bfb8 100644
--- a/README.adoc
+++ b/README.adoc
@@ -1,6 +1 @@
-= Hardware Support Package Template
-
-1. Update LICENSE file
-2. Update `microzig` submodule under `deps/`
-3. Add chips/boards/hals
-4. Set up buildkite pipeline
+= GigaDevice GD32 Hardware Support Package
diff --git a/src/boards.zig b/src/boards.zig
index 2cb647a34..d9a73b5f4 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -1,6 +1,13 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/src/main.zig");
+const chips = @import("chips.zig");
 
 fn root_dir() []const u8 {
     return std.fs.path.dirname(@src().file) orelse ".";
 }
+
+pub const longan_nano = micro.Board{
+    .name = "Longan Nano",
+    .source = .{ .path = root_dir() ++ "/boards/longan_nano.zig" },
+    .chip = chips.gd32vf103xb,
+};
diff --git a/src/boards/longan_nano.zig b/src/boards/longan_nano.zig
new file mode 100644
index 000000000..e042be11b
--- /dev/null
+++ b/src/boards/longan_nano.zig
@@ -0,0 +1,112 @@
+pub const chip = @import("chip");
+pub const micro = @import("microzig");
+
+pub const cpu_frequency = 8_000_000; // 8 MHz
+
+pub const pin_map = .{
+
+    // Port A
+    .PA0 = "PA0",
+    .PA1 = "PA1",
+    .PA2 = "PA2",
+    .PA3 = "PA3",
+    .PA4 = "PA4",
+    .PA5 = "PA5",
+    .PA6 = "PA6",
+    .PA7 = "PA7",
+    .PA8 = "PA8",
+    .PA9 = "PA9",
+    .PA10 = "PA10",
+    .PA11 = "PA11",
+    .PA12 = "PA12",
+    .PA13 = "PA13",
+
+    // Port B
+    .PB0 = "PB0",
+    .PB1 = "PB1",
+    .PB2 = "PB2",
+    .PB3 = "PB3",
+    .PB4 = "PB4",
+    .PB5 = "PB5",
+    .PB6 = "PB6",
+    .PB7 = "PB7",
+    .PB8 = "PB8",
+    .PB9 = "PB9",
+    .PB10 = "PB10",
+    .PB11 = "PB11",
+    .PB12 = "PB12",
+    .PB13 = "PB13",
+    .PB14 = "PB14",
+    .PB15 = "PB15",
+
+    // Port C
+    .PC0 = "PC0",
+    .PC1 = "PC1",
+    .PC2 = "PC2",
+    .PC3 = "PC3",
+    .PC4 = "PC4",
+    .PC5 = "PC5",
+    .PC6 = "PC6",
+    .PC7 = "PC7",
+    .PC8 = "PC8",
+    .PC9 = "PC9",
+    .PC10 = "PC10",
+    .PC11 = "PC11",
+    .PC12 = "PC12",
+    .PC13 = "PC13",
+    .PC14 = "PC14",
+    .PC15 = "PC15",
+
+    // Port D
+    .PD0 = "PD0",
+    .PD1 = "PD1",
+    .PD2 = "PD2",
+    .PD3 = "PD3",
+    .PD4 = "PD4",
+    .PD5 = "PD5",
+    .PD6 = "PD6",
+    .PD7 = "PD7",
+    .PD8 = "PD8",
+    .PD9 = "PD9",
+    .PD10 = "PD10",
+    .PD11 = "PD11",
+    .PD12 = "PD12",
+    .PD13 = "PD13",
+    .PD14 = "PD14",
+    .PD15 = "PD15",
+
+    // Port E
+    .PE0 = "PE0",
+    .PE1 = "PE1",
+    .PE2 = "PE2",
+    .PE3 = "PE3",
+    .PE4 = "PE4",
+    .PE5 = "PE5",
+    .PE6 = "PE6",
+    .PE7 = "PE7",
+    .PE8 = "PE8",
+    .PE9 = "PE9",
+    .PE10 = "PE10",
+    .PE11 = "PE11",
+    .PE12 = "PE12",
+    .PE13 = "PE13",
+    .PE14 = "PE14",
+    .PE15 = "PE15",
+
+    // Colors LED
+    // LCD_COLOR_WHITE     0xFFFF
+    // LCD_COLOR_BLACK     0x0000
+    // LCD_COLOR_GREY      0xF7DE
+    // LCD_COLOR_BLUE      0x001F
+    // LCD_COLOR_BLUE2     0x051F
+    // LCD_COLOR_RED       0xF800
+    // LCD_COLOR_MAGENTA   0xF81F
+    // LCD_COLOR_GREEN     0x07E0
+    // LCD_COLOR_CYAN      0x7FFF
+    // LCD_COLOR_YELLOW    0xFFE0
+};
+
+pub fn debugWrite(string: []const u8) void {
+    _ = string;
+    // TODO: implement
+}
diff --git a/src/chips.zig b/src/chips.zig
index 2cb647a34..ac1beefb0 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,6 +1,26 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/src/main.zig");
+const Chip = micro.Chip;
+const MemoryRegion = micro.MemoryRegion;
 
 fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse ".";
+    return std.fs.path.dirname(@src().file) orelse unreachable;
 }
+
+pub const gd32vf103xb = Chip.from_standard_paths(root_dir(), .{
+    .name = "GD32VF103",
+    .cpu = micro.cpus.riscv32_imac,
+    .memory_regions = &.{
+        MemoryRegion{ .offset = 0x08000000, .length = 128 * 1024, .kind = .flash },
+        MemoryRegion{ .offset = 0x20000000, .length = 32 * 1024, .kind = .ram },
+    },
+});
+
+pub const gd32vf103x8 = Chip.from_standard_paths(root_dir(), .{
+    .name = "GD32VF103",
+    .cpu = micro.cpus.riscv32_imac,
+    .memory_regions = &.{
+        MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash },
+        MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram },
+    },
+});
diff --git a/src/chips/GD32VF103.json b/src/chips/GD32VF103.json
new file mode 100644
index 000000000..7b949cf6e
--- /dev/null
+++ b/src/chips/GD32VF103.json
@@ -0,0 +1,32957 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "SCS": {
+        "description": "System Control Space",
+        "children": {
+          "register_groups": {
+            "SysTick": {
+              "description": "System Tick Timer",
+              "children": {
+                "registers": {
+                  "CTRL": {
+                    "description": "SysTick Control and Status Register",
+                    "offset": 0,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "ENABLE": {
+                          "offset": 0,
+                          "size": 1
+                        },
+                        "TICKINT": {
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "CLKSOURCE": {
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "COUNTFLAG": {
+                          "offset": 16,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "LOAD": {
+                    "description": "SysTick Reload Value Register",
+                    "offset": 4,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "RELOAD": {
+                          "offset": 0,
+                          "size": 24
+                        }
+                      }
+                    }
+                  },
+                  "VAL": {
+                    "description": "SysTick Current Value Register",
+                    "offset": 8,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "CURRENT": {
+                          "offset": 0,
+                          "size": 24
+                        }
+                      }
+                    }
+                  },
+                  "CALIB": {
+                    "description": "SysTick Calibration Register",
+                    "offset": 12,
+                    "size": 32,
+                    "access": "read-only",
+                    "children": {
+                      "fields": {
+                        "TENMS": {
+                          "offset": 0,
+                          "size": 24
+                        },
+                        "SKEW": {
+                          "offset": 30,
+                          "size": 1
+                        },
+                        "NOREF": {
+                          "offset": 31,
+                          "size": 1
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ADC0": {
+        "description": "Analog to digital converter",
+        "children": {
+          "registers": {
+            "STAT": {
+              "description": "status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STRC": {
+                    "description": "Start flag of regular channel group",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STIC": {
+                    "description": "Start flag of inserted channel group",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EOIC": {
+                    "description": "End of inserted group conversion flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EOC": {
+                    "description": "End of group conversion flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WDE": {
+                    "description": "Analog watchdog event flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTL0": {
+              "description": "control register 0",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWDEN": {
+                    "description": "Regular channel analog watchdog  enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "IWDEN": {
+                    "description": "Inserted channel analog watchdog \n\t     enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "SYNCM": {
+                    "description": "sync mode selection",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DISNUM": {
+                    "description": "Number of conversions in \n\t     discontinuous mode",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "DISIC": {
+                    "description": "Discontinuous mode on \n\t     inserted channels",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DISRC": {
+                    "description": "Discontinuous mode on regular\n              channels",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ICA": {
+                    "description": "Inserted channel group convert \n\t     automatically",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WDSC": {
+                    "description": "When in scan mode, analog watchdog\n\t     is effective on a single channel",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SM": {
+                    "description": "Scan mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EOICIE": {
+                    "description": "Interrupt enable for EOIC",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "WDEIE": {
+                    "description": "Interrupt enable for WDE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EOCIE": {
+                    "description": "Interrupt enable for EOC",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WDCHSEL": {
+                    "description": "Analog watchdog channel select",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CTL1": {
+              "description": "control register 1",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSVREN": {
+                    "description": "Channel 16 and 17 enable of ADC0",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "SWRCST": {
+                    "description": "Start on regular channel",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "SWICST": {
+                    "description": "Start on inserted channel",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "ETERC": {
+                    "description": "External trigger enable for regular channel",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "ETSRC": {
+                    "description": "External trigger select for regular channel",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "ETEIC": {
+                    "description": "External trigger select for inserted channel",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ETSIC": {
+                    "description": "External trigger select for inserted channel",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "DAL": {
+                    "description": "Data alignment",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DMA": {
+                    "description": "DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RSTCLB": {
+                    "description": "Reset calibration",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CLB": {
+                    "description": "ADC calibration",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CTN": {
+                    "description": "Continuous mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ADCON": {
+                    "description": "ADC on",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SAMPT0": {
+              "description": "Sample time register 0",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPT10": {
+                    "description": "Channel 10 sample time\n              selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "SPT11": {
+                    "description": "Channel 11 sample time\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "SPT12": {
+                    "description": "Channel 12 sample time\n              selection",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "SPT13": {
+                    "description": "Channel 13 sample time\n              selection",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "SPT14": {
+                    "description": "Channel 14 sample time\n              selection",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "SPT15": {
+                    "description": "Channel 15 sample time\n              selection",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SPT16": {
+                    "description": "Channel 16 sample time\n              selection",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "SPT17": {
+                    "description": "Channel 17 sample time\n              selection",
+                    "offset": 21,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "SAMPT1": {
+              "description": "Sample time register 1",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPT0": {
+                    "description": "Channel 0 sample time\n              selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "SPT1": {
+                    "description": "Channel 1 sample time\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "SPT2": {
+                    "description": "Channel 2 sample time\n              selection",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "SPT3": {
+                    "description": "Channel 3 sample time\n              selection",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "SPT4": {
+                    "description": "Channel 4 sample time\n              selection",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "SPT5": {
+                    "description": "Channel 5 sample time\n              selection",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SPT6": {
+                    "description": "Channel 6 sample time\n              selection",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "SPT7": {
+                    "description": "Channel 7 sample time\n              selection",
+                    "offset": 21,
+                    "size": 3
+                  },
+                  "SPT8": {
+                    "description": "Channel 8 sample time\n              selection",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "SPT9": {
+                    "description": "Channel 9 sample time\n              selection",
+                    "offset": 27,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "IOFF0": {
+              "description": "Inserted channel data offset register\n          0",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOFF": {
+                    "description": "Data offset for inserted channel\n              0",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IOFF1": {
+              "description": "Inserted channel data offset register\n          1",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOFF": {
+                    "description": "Data offset for inserted channel\n              1",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IOFF2": {
+              "description": "Inserted channel data offset register\n          2",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOFF": {
+                    "description": "Data offset for inserted channel\n              2",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IOFF3": {
+              "description": "Inserted channel data offset register\n          3",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOFF": {
+                    "description": "Data offset for inserted channel\n              3",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "WDHT": {
+              "description": "watchdog higher threshold\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDHT": {
+                    "description": "Analog watchdog higher\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "WDLT": {
+              "description": "watchdog lower threshold\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDLT": {
+                    "description": "Analog watchdog lower\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "RSQ0": {
+              "description": "regular sequence register 0",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RL": {
+                    "description": "Regular channel group\n              length",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "RSQ15": {
+                    "description": "16th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "RSQ14": {
+                    "description": "15th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "RSQ13": {
+                    "description": "14th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "RSQ12": {
+                    "description": "13th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RSQ1": {
+              "description": "regular sequence register 1",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RSQ11": {
+                    "description": "12th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "RSQ10": {
+                    "description": "11th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "RSQ9": {
+                    "description": "10th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "RSQ8": {
+                    "description": "9th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "RSQ7": {
+                    "description": "8th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "RSQ6": {
+                    "description": "7th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RSQ2": {
+              "description": "regular sequence register 2",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RSQ5": {
+                    "description": "6th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "RSQ4": {
+                    "description": "5th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "RSQ3": {
+                    "description": "4th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "RSQ2": {
+                    "description": "3rd conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "RSQ1": {
+                    "description": "2nd conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "RSQ0": {
+                    "description": "1st conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "ISQ": {
+              "description": "Inserted sequence register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IL": {
+                    "description": "Inserted channel group length",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "ISQ3": {
+                    "description": "4th conversion in inserted\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "ISQ2": {
+                    "description": "3rd conversion in inserted\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "ISQ1": {
+                    "description": "2nd conversion in inserted\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "ISQ0": {
+                    "description": "1st conversion in inserted\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "IDATA0": {
+              "description": "Inserted data register 0",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDATAn": {
+                    "description": "Inserted number n conversion data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IDATA1": {
+              "description": "Inserted data register 1",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDATAn": {
+                    "description": "Inserted number n conversion data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IDATA2": {
+              "description": "Inserted data register 2",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDATAn": {
+                    "description": "Inserted number n conversion data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IDATA3": {
+              "description": "Inserted data register 3",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDATAn": {
+                    "description": "Inserted number n conversion data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RDATA": {
+              "description": "regular data register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ADC1RDTR": {
+                    "description": "ADC regular channel data",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "RDATA": {
+                    "description": "Regular channel data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OVSAMPCTL": {
+              "description": "Oversample control register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DRES": {
+                    "description": "ADC resolution",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "TOVS": {
+                    "description": "Triggered Oversampling",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OVSS": {
+                    "description": "Oversampling shift",
+                    "offset": 5,
+                    "size": 4
+                  },
+                  "OVSR": {
+                    "description": "Oversampling ratio",
+                    "offset": 2,
+                    "size": 3
+                  },
+                  "OVSEN": {
+                    "description": "Oversampler Enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ADC1": {
+        "description": "Analog to digital converter",
+        "children": {
+          "registers": {
+            "STAT": {
+              "description": "status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STRC": {
+                    "description": "Start flag of regular channel group",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STIC": {
+                    "description": "Start flag of inserted channel group",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EOIC": {
+                    "description": "End of inserted group conversion flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EOC": {
+                    "description": "End of group conversion flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WDE": {
+                    "description": "Analog watchdog event flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTL0": {
+              "description": "control register 0",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWDEN": {
+                    "description": "Regular channel analog watchdog \n\t     enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "IWDEN": {
+                    "description": "Inserted channel analog watchdog \n\t     enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "DISNUM": {
+                    "description": "Number of conversions in \n\t     discontinuous mode",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "DISIC": {
+                    "description": "Discontinuous mode on \n\t     inserted channels",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DISRC": {
+                    "description": "Discontinuous mode on regular\n              channels",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ICA": {
+                    "description": "Inserted channel group convert \n\t     automatically",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WDSC": {
+                    "description": "When in scan mode, analog watchdog\n\t     is effective on a single channel",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SM": {
+                    "description": "Scan mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EOICIE": {
+                    "description": "Interrupt enable for EOIC",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "WDEIE": {
+                    "description": "Interrupt enable for WDE",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EOCIE": {
+                    "description": "Interrupt enable for EOC",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WDCHSEL": {
+                    "description": "Analog watchdog channel select",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CTL1": {
+              "description": "control register 1",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWRCST": {
+                    "description": "Start on regular channel",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "SWICST": {
+                    "description": "Start on inserted channel",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "ETERC": {
+                    "description": "External trigger enable for regular channel",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "ETSRC": {
+                    "description": "External trigger select for regular channel",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "ETEIC": {
+                    "description": "External trigger enable for inserted channel",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ETSIC": {
+                    "description": "External trigger select for inserted channel",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "DAL": {
+                    "description": "Data alignment",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DMA": {
+                    "description": "DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RSTCLB": {
+                    "description": "Reset calibration",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CLB": {
+                    "description": "ADC calibration",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CTN": {
+                    "description": "Continuous mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ADCON": {
+                    "description": "ADC on",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SAMPT0": {
+              "description": "Sample time register 0",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPT10": {
+                    "description": "Channel 10 sample time\n              selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "SPT11": {
+                    "description": "Channel 11 sample time\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "SPT12": {
+                    "description": "Channel 12 sample time\n              selection",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "SPT13": {
+                    "description": "Channel 13 sample time\n              selection",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "SPT14": {
+                    "description": "Channel 14 sample time\n              selection",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "SPT15": {
+                    "description": "Channel 15 sample time\n              selection",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SPT16": {
+                    "description": "Channel 16 sample time\n              selection",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "SPT17": {
+                    "description": "Channel 17 sample time\n              selection",
+                    "offset": 21,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "SAMPT1": {
+              "description": "Sample time register 1",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPT0": {
+                    "description": "Channel 0 sample time\n              selection",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "SPT1": {
+                    "description": "Channel 1 sample time\n              selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "SPT2": {
+                    "description": "Channel 2 sample time\n              selection",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "SPT3": {
+                    "description": "Channel 3 sample time\n              selection",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "SPT4": {
+                    "description": "Channel 4 sample time\n              selection",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "SPT5": {
+                    "description": "Channel 5 sample time\n              selection",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SPT6": {
+                    "description": "Channel 6 sample time\n              selection",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "SPT7": {
+                    "description": "Channel 7 sample time\n              selection",
+                    "offset": 21,
+                    "size": 3
+                  },
+                  "SPT8": {
+                    "description": "Channel 8 sample time\n              selection",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "SPT9": {
+                    "description": "Channel 9 sample time\n              selection",
+                    "offset": 27,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "IOFF0": {
+              "description": "Inserted channel data offset register\n          0",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOFF": {
+                    "description": "Data offset for inserted channel\n              0",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IOFF1": {
+              "description": "Inserted channel data offset register\n          1",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOFF": {
+                    "description": "Data offset for inserted channel\n              1",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IOFF2": {
+              "description": "Inserted channel data offset register\n          2",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOFF": {
+                    "description": "Data offset for inserted channel\n              2",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IOFF3": {
+              "description": "Inserted channel data offset register\n          3",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IOFF": {
+                    "description": "Data offset for inserted channel\n              3",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "WDHT": {
+              "description": "watchdog higher threshold\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDHT": {
+                    "description": "Analog watchdog higher\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "WDLT": {
+              "description": "watchdog lower threshold\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDLT": {
+                    "description": "Analog watchdog lower\n              threshold",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "RSQ0": {
+              "description": "regular sequence register 0",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RL": {
+                    "description": "Regular channel group\n              length",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "RSQ15": {
+                    "description": "16th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "RSQ14": {
+                    "description": "15th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "RSQ13": {
+                    "description": "14th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "RSQ12": {
+                    "description": "13th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RSQ1": {
+              "description": "regular sequence register 1",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RSQ11": {
+                    "description": "12th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "RSQ10": {
+                    "description": "11th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "RSQ9": {
+                    "description": "10th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "RSQ8": {
+                    "description": "9th conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "RSQ7": {
+                    "description": "8th conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "RSQ6": {
+                    "description": "7th conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RSQ2": {
+              "description": "regular sequence register 2",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RSQ5": {
+                    "description": "6th conversion in regular\n              sequence",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "RSQ4": {
+                    "description": "5th conversion in regular\n              sequence",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "RSQ3": {
+                    "description": "4th conversion in regular\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "RSQ2": {
+                    "description": "3rd conversion in regular\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "RSQ1": {
+                    "description": "2nd conversion in regular\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "RSQ0": {
+                    "description": "1st conversion in regular\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "ISQ": {
+              "description": "Inserted sequence register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IL": {
+                    "description": "Inserted channel group length",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "ISQ3": {
+                    "description": "4th conversion in inserted\n              sequence",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "ISQ2": {
+                    "description": "3rd conversion in inserted\n              sequence",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "ISQ1": {
+                    "description": "2nd conversion in inserted\n              sequence",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "ISQ0": {
+                    "description": "1st conversion in inserted\n              sequence",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "IDATA0": {
+              "description": "Inserted data register 0",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDATAn": {
+                    "description": "Inserted number n conversion data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IDATA1": {
+              "description": "Inserted data register 1",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDATAn": {
+                    "description": "Inserted number n conversion data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IDATA2": {
+              "description": "Inserted data register 2",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDATAn": {
+                    "description": "Inserted number n conversion data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IDATA3": {
+              "description": "Inserted data register 3",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IDATAn": {
+                    "description": "Inserted number n conversion data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RDATA": {
+              "description": "regular data register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RDATA": {
+                    "description": "Regular channel data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "AFIO": {
+        "description": "Alternate-function I/Os",
+        "children": {
+          "registers": {
+            "EC": {
+              "description": "Event control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EOE": {
+                    "description": "Event output enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PORT": {
+                    "description": "Event output port selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "PIN": {
+                    "description": "Event output pin selection",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "PCF0": {
+              "description": "AFIO port configuration register 0",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER1ITI1_REMAP": {
+                    "description": "TIMER1 internal trigger 1 remapping",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SPI2_REMAP": {
+                    "description": " SPI2/I2S2 remapping",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "SWJ_CFG": {
+                    "description": "Serial wire JTAG configuration",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "CAN1_REMAP": {
+                    "description": "CAN1 I/O remapping",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TIMER4CH3_IREMAP": {
+                    "description": "TIMER4 channel3 internal remapping",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PD01_REMAP": {
+                    "description": "Port D0/Port D1 mapping on OSC_IN/OSC_OUT",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CAN0_REMAP": {
+                    "description": "CAN0 alternate interface remapping",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "TIMER3_REMAP": {
+                    "description": "TIMER3 remapping",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIMER2_REMAP": {
+                    "description": "TIMER2 remapping",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "TIMER1_REMAP": {
+                    "description": "TIMER1 remapping",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "TIMER0_REMAP": {
+                    "description": "TIMER0 remapping",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "USART2_REMAP": {
+                    "description": "USART2 remapping",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "USART1_REMAP": {
+                    "description": "USART1 remapping",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "USART0_REMAP": {
+                    "description": "USART0 remapping",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "I2C0_REMAP": {
+                    "description": "I2C0 remapping",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SPI0_REMAP": {
+                    "description": "SPI0 remapping",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EXTISS0": {
+              "description": "EXTI sources selection register 0",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI3_SS": {
+                    "description": "EXTI 3 sources selection",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI2_SS": {
+                    "description": "EXTI 2 sources selection",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI1_SS": {
+                    "description": "EXTI 1 sources selection",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI0_SS": {
+                    "description": "EXTI 0 sources selection",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTISS1": {
+              "description": "EXTI sources selection register 1",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI7_SS": {
+                    "description": "EXTI 7 sources selection",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI6_SS": {
+                    "description": "EXTI 6 sources selection",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI5_SS": {
+                    "description": "EXTI 5 sources selection",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI4_SS": {
+                    "description": "EXTI 4 sources selection",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTISS2": {
+              "description": "EXTI sources selection register 2",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI11_SS": {
+                    "description": "EXTI 11 sources selection",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI10_SS": {
+                    "description": "EXTI 10 sources selection",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI9_SS": {
+                    "description": "EXTI 9 sources selection",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI8_SS": {
+                    "description": "EXTI 8 sources selection",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "EXTISS3": {
+              "description": "EXTI sources selection register 3",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXTI15_SS": {
+                    "description": "EXTI 15 sources selection",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "EXTI14_SS": {
+                    "description": "EXTI 14 sources selection",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "EXTI13_SS": {
+                    "description": "EXTI 13 sources selection",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EXTI12_SS": {
+                    "description": "EXTI 12 sources selection",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "PCF1": {
+              "description": "AFIO port configuration register 1",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXMC_NADV": {
+                    "description": "EXMC_NADV connect/disconnect",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "BKP": {
+        "description": "Backup registers",
+        "children": {
+          "registers": {
+            "DATA0": {
+              "description": "Backup data register 0",
+              "offset": 4,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA1": {
+              "description": "Backup data register 1",
+              "offset": 8,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA2": {
+              "description": "Backup data register 2",
+              "offset": 12,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA3": {
+              "description": "Backup data register 3",
+              "offset": 16,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA4": {
+              "description": "Backup data register 4",
+              "offset": 20,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA5": {
+              "description": "Backup data register 5",
+              "offset": 24,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA6": {
+              "description": "Backup data register 6",
+              "offset": 28,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA7": {
+              "description": "Backup data register 7",
+              "offset": 32,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA8": {
+              "description": "Backup data register 8",
+              "offset": 36,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA9": {
+              "description": "Backup data register 9",
+              "offset": 40,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA10": {
+              "description": "Backup data register 10",
+              "offset": 64,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA11": {
+              "description": "Backup data register 11",
+              "offset": 68,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA12": {
+              "description": "Backup data register 12",
+              "offset": 72,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA13": {
+              "description": "Backup data register 13",
+              "offset": 76,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA14": {
+              "description": "Backup data register 14",
+              "offset": 80,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA15": {
+              "description": "Backup data register 15",
+              "offset": 84,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA16": {
+              "description": "Backup data register 16",
+              "offset": 88,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA17": {
+              "description": "Backup data register 17",
+              "offset": 92,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA18": {
+              "description": "Backup data register 18",
+              "offset": 96,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA19": {
+              "description": "Backup data register 19",
+              "offset": 100,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA20": {
+              "description": "Backup data register 20",
+              "offset": 104,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA21": {
+              "description": "Backup data register 21",
+              "offset": 108,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA22": {
+              "description": "Backup data register 22",
+              "offset": 112,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA23": {
+              "description": "Backup data register 23",
+              "offset": 116,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA24": {
+              "description": "Backup data register 24",
+              "offset": 120,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA25": {
+              "description": "Backup data register 25",
+              "offset": 124,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA26": {
+              "description": "Backup data register 26",
+              "offset": 128,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA27": {
+              "description": "Backup data register 27",
+              "offset": 132,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA28": {
+              "description": "Backup data register 28",
+              "offset": 136,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA29": {
+              "description": "Backup data register 29",
+              "offset": 140,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA30": {
+              "description": "Backup data register 30",
+              "offset": 144,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA31": {
+              "description": "Backup data register 31",
+              "offset": 148,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA32": {
+              "description": "Backup data register 32",
+              "offset": 152,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA33": {
+              "description": "Backup data register 33",
+              "offset": 156,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA34": {
+              "description": "Backup data register 34",
+              "offset": 160,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA35": {
+              "description": "Backup data register 35",
+              "offset": 164,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA36": {
+              "description": "Backup data register 36",
+              "offset": 168,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA37": {
+              "description": "Backup data register 37",
+              "offset": 172,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA38": {
+              "description": "Backup data register 38",
+              "offset": 176,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA39": {
+              "description": "Backup data register 39",
+              "offset": 180,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA40": {
+              "description": "Backup data register 40",
+              "offset": 184,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATA41": {
+              "description": "Backup data register 41",
+              "offset": 188,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Backup data",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "OCTL": {
+              "description": "RTC signal output control register",
+              "offset": 44,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ROSEL": {
+                    "description": "RTC output selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ASOEN": {
+                    "description": "RTC alarm or second signal output enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "COEN": {
+                    "description": "RTC clock calibration output enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RCCV": {
+                    "description": "RTC clock calibration value",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "TPCTL": {
+              "description": "Tamper pin control register",
+              "offset": 48,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TPAL": {
+                    "description": "TAMPER pin active level",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TPEN": {
+                    "description": "TAMPER detection enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TPCS": {
+              "description": "Tamper control and status register",
+              "offset": 52,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIF": {
+                    "description": "Tamper interrupt flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TEF": {
+                    "description": "Tamper event flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TPIE": {
+                    "description": "Tamper interrupt enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIR": {
+                    "description": "Tamper interrupt reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TER": {
+                    "description": "Tamper event reset",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CAN0": {
+        "description": "Controller area network",
+        "children": {
+          "registers": {
+            "CTL": {
+              "description": "Control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 65538,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DFZ": {
+                    "description": "Debug freeze",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SWRST": {
+                    "description": "Software reset",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TTC": {
+                    "description": "Time-triggered communication",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ABOR": {
+                    "description": "Automatic bus-off recovery",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "AWU": {
+                    "description": "Automatic wakeup",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ARD": {
+                    "description": "Automatic retransmission disable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RFOD": {
+                    "description": "Receive FIFO overwrite disable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TFO": {
+                    "description": "Transmit FIFO order",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLPWMOD": {
+                    "description": "Sleep working mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IWMOD": {
+                    "description": "Initial working mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "STAT": {
+              "description": "Status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 3074,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXL": {
+                    "description": "RX level",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LASTRX": {
+                    "description": "Last sample value of RX pin",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS": {
+                    "description": "Receiving state",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TS": {
+                    "description": "Transmitting state",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLPIF": {
+                    "description": "Status change interrupt flag of sleep \n\t     working mode entering",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "WUIF": {
+                    "description": "Status change interrupt flag of wakeup \n\t     from sleep working mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERRIF": {
+                    "description": "Error interrupt flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLPWS": {
+                    "description": "Sleep working state",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IWS": {
+                    "description": "Initial working state",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TSTAT": {
+              "description": "Transmit status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 469762048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TMLS2": {
+                    "description": "Transmit mailbox 2 last sending \n\t     in transmit FIFO",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TMLS1": {
+                    "description": "Transmit mailbox 1 last sending \n\t     in transmit FIFO",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TMLS0": {
+                    "description": "Transmit mailbox 0 last sending \n\t     in transmit FIFO",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME2": {
+                    "description": "Transmit mailbox 2 empty",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME1": {
+                    "description": "Transmit mailbox 1 empty",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TME0": {
+                    "description": "Transmit mailbox 0 empty",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NUM": {
+                    "description": "number of the transmit FIFO mailbox in \n\t     which the frame will be transmitted if at least one mailbox is empty",
+                    "offset": 24,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "MST2": {
+                    "description": "Mailbox 2 stop transmitting",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "MTE2": {
+                    "description": "Mailbox 2 transmit error",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "MAL2": {
+                    "description": "Mailbox 2 arbitration lost",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "MTFNERR2": {
+                    "description": "Mailbox 2 transmit finished and no error",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MTF2": {
+                    "description": "Mailbox 2 transmit finished",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MST1": {
+                    "description": "Mailbox 1 stop transmitting",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MTE1": {
+                    "description": "Mailbox 1 transmit error",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "MAL1": {
+                    "description": "Mailbox 1 arbitration lost",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "MTFNERR1": {
+                    "description": "Mailbox 1 transmit finished and no error",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "MTF1": {
+                    "description": "Mailbox 1 transmit finished",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "MST0": {
+                    "description": "Mailbox 0 stop transmitting",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MTE0": {
+                    "description": "Mailbox 0 transmit error",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MAL0": {
+                    "description": "Mailbox 0 arbitration lost",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MTFNERR0": {
+                    "description": "Mailbox 0 transmit finished and no error",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MTF0": {
+                    "description": "Mailbox 0 transmit finished",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RFIFO0": {
+              "description": "Receive message FIFO0 register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFD0": {
+                    "description": "Receive FIFO0 dequeue",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RFO0": {
+                    "description": "Receive FIFO0 overfull",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RFF0": {
+                    "description": "Receive FIFO0 full",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RFL0": {
+                    "description": "Receive FIFO0 length",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RFIFO1": {
+              "description": "Receive message FIFO1 register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RFD1": {
+                    "description": "Receive FIFO1 dequeue",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RFO1": {
+                    "description": "Receive FIFO1 overfull",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RFF1": {
+                    "description": "Receive FIFO1 full",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RFL1": {
+                    "description": "Receive FIFO1 length",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTEN": {
+              "description": "Interrupt enable register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLPWIE": {
+                    "description": "Sleep working interrupt enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WIE": {
+                    "description": "Wakeup interrupt enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ERRNIE": {
+                    "description": "Error number interrupt enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BOIE": {
+                    "description": "Bus-off interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PERRIE": {
+                    "description": "Passive error interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WERRIE": {
+                    "description": "Warning error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RFOIE1": {
+                    "description": "Receive FIFO1 overfull interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RFFIE1": {
+                    "description": "Receive FIFO1 full interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RFNEIE1": {
+                    "description": "Receive FIFO1 not empty interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RFOIE0": {
+                    "description": "Receive FIFO0 overfull interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RFFIE0": {
+                    "description": "Receive FIFO0 full interrupt enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RFNEIE0": {
+                    "description": "Receive FIFO0 not empty interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TMEIE": {
+                    "description": "Transmit mailbox empty interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ERR": {
+              "description": "Error register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RECNT": {
+                    "description": "Receive Error Count defined \n\t     by the CAN standard",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "TECNT": {
+                    "description": "Transmit Error Count defined \n\t     by the CAN standard",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "ERRN": {
+                    "description": "Error number",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "BOERR": {
+                    "description": "Bus-off error",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PERR": {
+                    "description": "Passive error",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WERR": {
+                    "description": "Warning error",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "BT": {
+              "description": "Bit timing register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 19070976,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCMOD": {
+                    "description": "Silent communication mode",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LCMOD": {
+                    "description": "Loopback communication mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SJW": {
+                    "description": "Resynchronization jump width",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "BS2": {
+                    "description": "Bit segment 2",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "BS1": {
+                    "description": "Bit segment 1",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "BAUDPSC": {
+                    "description": "Baud rate prescaler",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "TMI0": {
+              "description": "Transmit mailbox identifier register 0",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SFID_EFID": {
+                    "description": "The frame identifier",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EFID": {
+                    "description": "The frame identifier",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "FF": {
+                    "description": "Frame format",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FT": {
+                    "description": "Frame type",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TEN": {
+                    "description": "Transmit enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TMP0": {
+              "description": "Transmit mailbox property register 0",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TS": {
+                    "description": "Time stamp",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TSEN": {
+                    "description": "Time stamp enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLENC": {
+                    "description": "Data length code",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TMDATA00": {
+              "description": "Transmit mailbox data0 register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DB3": {
+                    "description": "Data byte 3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DB2": {
+                    "description": "Data byte 2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DB1": {
+                    "description": "Data byte 1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DB0": {
+                    "description": "Data byte 0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TMDATA10": {
+              "description": "Transmit mailbox data1 register",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DB7": {
+                    "description": "Data byte 7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DB6": {
+                    "description": "Data byte 6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DB5": {
+                    "description": "Data byte 5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DB4": {
+                    "description": "Data byte 4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TMI1": {
+              "description": "Transmit mailbox identifier register 1",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SFID_EFID": {
+                    "description": "The frame identifier",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EFID": {
+                    "description": "The frame identifier",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "FF": {
+                    "description": "Frame format",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FT": {
+                    "description": "Frame type",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TEN": {
+                    "description": "Transmit enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TMP1": {
+              "description": "Transmit mailbox property register 1",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TS": {
+                    "description": "Time stamp",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TSEN": {
+                    "description": "Time stamp enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLENC": {
+                    "description": "Data length code",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TMDATA01": {
+              "description": "Transmit mailbox data0 register",
+              "offset": 408,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DB3": {
+                    "description": "Data byte 3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DB2": {
+                    "description": "Data byte 2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DB1": {
+                    "description": "Data byte 1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DB0": {
+                    "description": "Data byte 0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TMDATA11": {
+              "description": "Transmit mailbox data1 register",
+              "offset": 412,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DB7": {
+                    "description": "Data byte 7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DB6": {
+                    "description": "Data byte 6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DB5": {
+                    "description": "Data byte 5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DB4": {
+                    "description": "Data byte 4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TMI2": {
+              "description": "Transmit mailbox identifier register 2",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SFID_EFID": {
+                    "description": "The frame identifier",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EFID": {
+                    "description": "The frame identifier",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "FF": {
+                    "description": "Frame format",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FT": {
+                    "description": "Frame type",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TEN": {
+                    "description": "Transmit enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TMP2": {
+              "description": "Transmit mailbox property register 2",
+              "offset": 420,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TS": {
+                    "description": "Time stamp",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "TSEN": {
+                    "description": "Time stamp enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DLENC": {
+                    "description": "Data length code",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TMDATA02": {
+              "description": "Transmit mailbox data0 register",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DB3": {
+                    "description": "Data byte 3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DB2": {
+                    "description": "Data byte 2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DB1": {
+                    "description": "Data byte 1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DB0": {
+                    "description": "Data byte 0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TMDATA12": {
+              "description": "Transmit mailbox data1 register",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DB7": {
+                    "description": "Data byte 7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DB6": {
+                    "description": "Data byte 6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DB5": {
+                    "description": "Data byte 5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DB4": {
+                    "description": "Data byte 4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RFIFOMI0": {
+              "description": "Receive FIFO mailbox identifier register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SFID_EFID": {
+                    "description": "The frame identifier",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EFID": {
+                    "description": "The frame identifier",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "FF": {
+                    "description": "Frame format",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FT": {
+                    "description": "Frame type",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RFIFOMP0": {
+              "description": "Receive FIFO0 mailbox property register",
+              "offset": 436,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TS": {
+                    "description": "Time stamp",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FI": {
+                    "description": "Filtering index",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DLENC": {
+                    "description": "Data length code",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RFIFOMDATA00": {
+              "description": "Receive FIFO0 mailbox data0 register",
+              "offset": 440,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DB3": {
+                    "description": "Data byte 3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DB2": {
+                    "description": "Data byte 2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DB1": {
+                    "description": "Data byte 1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DB0": {
+                    "description": "Data byte 0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RFIFOMDATA10": {
+              "description": "Receive FIFO0 mailbox data1 register",
+              "offset": 444,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DB7": {
+                    "description": "Data byte 7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DB6": {
+                    "description": "Data byte 6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DB5": {
+                    "description": "Data byte 5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DB4": {
+                    "description": "Data byte 4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RFIFOMI1": {
+              "description": "Receive FIFO1 mailbox identifier register",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SFID_EFID": {
+                    "description": "The frame identifier",
+                    "offset": 21,
+                    "size": 11
+                  },
+                  "EFID": {
+                    "description": "The frame identifier",
+                    "offset": 3,
+                    "size": 18
+                  },
+                  "FF": {
+                    "description": "Frame format",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FT": {
+                    "description": "Frame type",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RFIFOMP1": {
+              "description": "Receive FIFO1 mailbox property register",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TS": {
+                    "description": "Time stamp",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FI": {
+                    "description": "Filtering index",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DLENC": {
+                    "description": "Data length code",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RFIFOMDATA01": {
+              "description": "Receive FIFO1 mailbox data0 register",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DB3": {
+                    "description": "Data byte 3",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DB2": {
+                    "description": "Data byte 2",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DB1": {
+                    "description": "Data byte 1",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DB0": {
+                    "description": "Data byte 0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RFIFOMDATA11": {
+              "description": "Receive FIFO1 mailbox data1 register",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DB7": {
+                    "description": "Data byte 7",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "DB6": {
+                    "description": "Data byte 6",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "DB5": {
+                    "description": "Data byte 5",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DB4": {
+                    "description": "Data byte 4",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "FCTL": {
+              "description": "Filter control register",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 706481665,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HBC1F": {
+                    "description": "Header bank of CAN1 filter",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "FLD": {
+                    "description": "Filter lock disable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FMCFG": {
+              "description": "Filter mode configuration register",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FMOD27": {
+                    "description": "Filter mode",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FMOD26": {
+                    "description": "Filter mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FMOD25": {
+                    "description": "Filter mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FMOD24": {
+                    "description": "Filter mode",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FMOD23": {
+                    "description": "Filter mode",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FMOD22": {
+                    "description": "Filter mode",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FMOD21": {
+                    "description": "Filter mode",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FMOD20": {
+                    "description": "Filter mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FMOD19": {
+                    "description": "Filter mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FMOD18": {
+                    "description": "Filter mode",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FMOD17": {
+                    "description": "Filter mode",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FMOD16": {
+                    "description": "Filter mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FMOD15": {
+                    "description": "Filter mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FMOD14": {
+                    "description": "Filter mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FMOD13": {
+                    "description": "Filter mode",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FMOD12": {
+                    "description": "Filter mode",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FMOD11": {
+                    "description": "Filter mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FMOD10": {
+                    "description": "Filter mode",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FMOD9": {
+                    "description": "Filter mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FMOD8": {
+                    "description": "Filter mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FMOD7": {
+                    "description": "Filter mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FMOD6": {
+                    "description": "Filter mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FMOD5": {
+                    "description": "Filter mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FMOD4": {
+                    "description": "Filter mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FMOD3": {
+                    "description": "Filter mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FMOD2": {
+                    "description": "Filter mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FMOD1": {
+                    "description": "Filter mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FMOD0": {
+                    "description": "Filter mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FSCFG": {
+              "description": "Filter scale configuration register",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FS0": {
+                    "description": "Filter scale configuration",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FS1": {
+                    "description": "Filter scale configuration",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FS2": {
+                    "description": "Filter scale configuration",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FS3": {
+                    "description": "Filter scale configuration",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FS4": {
+                    "description": "Filter scale configuration",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FS5": {
+                    "description": "Filter scale configuration",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FS6": {
+                    "description": "Filter scale configuration",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FS7": {
+                    "description": "Filter scale configuration",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FS8": {
+                    "description": "Filter scale configuration",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FS9": {
+                    "description": "Filter scale configuration",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FS10": {
+                    "description": "Filter scale configuration",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FS11": {
+                    "description": "Filter scale configuration",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FS12": {
+                    "description": "Filter scale configuration",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FS13": {
+                    "description": "Filter scale configuration",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FS14": {
+                    "description": "Filter scale configuration",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FS15": {
+                    "description": "Filter scale configuration",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FS16": {
+                    "description": "Filter scale configuration",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FS17": {
+                    "description": "Filter scale configuration",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FS18": {
+                    "description": "Filter scale configuration",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FS19": {
+                    "description": "Filter scale configuration",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FS20": {
+                    "description": "Filter scale configuration",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FS21": {
+                    "description": "Filter scale configuration",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FS22": {
+                    "description": "Filter scale configuration",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FS23": {
+                    "description": "Filter scale configuration",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FS24": {
+                    "description": "Filter scale configuration",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FS25": {
+                    "description": "Filter scale configuration",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FS26": {
+                    "description": "Filter scale configuration",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FS27": {
+                    "description": "Filter scale configuration",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FAFIFO": {
+              "description": "Filter associated FIFO register",
+              "offset": 532,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FAF0": {
+                    "description": "Filter 0 associated with FIFO",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FAF1": {
+                    "description": "Filter 1 associated with FIFO",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FAF2": {
+                    "description": "Filter 2 associated with FIFO",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FAF3": {
+                    "description": "Filter 3 associated with FIFO",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FAF4": {
+                    "description": "Filter 4 associated with FIFO",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FAF5": {
+                    "description": "Filter 5 associated with FIFO",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FAF6": {
+                    "description": "Filter 6 associated with FIFO",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FAF7": {
+                    "description": "Filter 7 associated with FIFO",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FAF8": {
+                    "description": "Filter 8 associated with FIFO",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FAF9": {
+                    "description": "Filter 9 associated with FIFO",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FAF10": {
+                    "description": "Filter 10 associated with FIFO",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FAF11": {
+                    "description": "Filter 11 associated with FIFO",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FAF12": {
+                    "description": "Filter 12 associated with FIFO",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FAF13": {
+                    "description": "Filter 13 associated with FIFO",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FAF14": {
+                    "description": "Filter 14 associated with FIFO",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FAF15": {
+                    "description": "Filter 15 associated with FIFO",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FAF16": {
+                    "description": "Filter 16 associated with FIFO",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FAF17": {
+                    "description": "Filter 17 associated with FIFO",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FAF18": {
+                    "description": "Filter 18 associated with FIFO",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FAF19": {
+                    "description": "Filter 19 associated with FIFO",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FAF20": {
+                    "description": "Filter 20 associated with FIFO",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FAF21": {
+                    "description": "Filter 21 associated with FIFO",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FAF22": {
+                    "description": "Filter 22 associated with FIFO",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FAF23": {
+                    "description": "Filter 23 associated with FIFO",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FAF24": {
+                    "description": "Filter 24 associated with FIFO",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FAF25": {
+                    "description": "Filter 25 associated with FIFO",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FAF26": {
+                    "description": "Filter 26 associated with FIFO",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FAF27": {
+                    "description": "Filter 27 associated with FIFO",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FW": {
+              "description": "Filter working register",
+              "offset": 540,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FW0": {
+                    "description": "Filter working",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FW1": {
+                    "description": "Filter working",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FW2": {
+                    "description": "Filter working",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FW3": {
+                    "description": "Filter working",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FW4": {
+                    "description": "Filter working",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FW5": {
+                    "description": "Filter working",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FW6": {
+                    "description": "Filter working",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FW7": {
+                    "description": "Filter working",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FW8": {
+                    "description": "Filter working",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FW9": {
+                    "description": "Filter working",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FW10": {
+                    "description": "Filter working",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FW11": {
+                    "description": "Filter working",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FW12": {
+                    "description": "Filter working",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FW13": {
+                    "description": "Filter working",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FW14": {
+                    "description": "Filter working",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FW15": {
+                    "description": "Filter working",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FW16": {
+                    "description": "Filter working",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FW17": {
+                    "description": "Filter working",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FW18": {
+                    "description": "Filter working",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FW19": {
+                    "description": "Filter working",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FW20": {
+                    "description": "Filter working",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FW21": {
+                    "description": "Filter working",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FW22": {
+                    "description": "Filter working",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FW23": {
+                    "description": "Filter working",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FW24": {
+                    "description": "Filter working",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FW25": {
+                    "description": "Filter working",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FW26": {
+                    "description": "Filter working",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FW27": {
+                    "description": "Filter working",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F0DATA0": {
+              "description": "Filter 0 data 0 register",
+              "offset": 576,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F0DATA1": {
+              "description": "Filter 0 data 1 register",
+              "offset": 580,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F1DATA0": {
+              "description": "Filter 1 data 0 register",
+              "offset": 584,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F1DATA1": {
+              "description": "Filter 1 data 1 register",
+              "offset": 588,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F2DATA0": {
+              "description": "Filter 2 data 0 register",
+              "offset": 592,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F2DATA1": {
+              "description": "Filter 2 data 1 register",
+              "offset": 596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F3DATA0": {
+              "description": "Filter 3 data 0 register",
+              "offset": 600,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F3DATA1": {
+              "description": "Filter 3 data 1 register",
+              "offset": 604,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F4DATA0": {
+              "description": "Filter 4 data 0 register",
+              "offset": 608,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F4DATA1": {
+              "description": "Filter 4 data 1 register",
+              "offset": 612,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F5DATA0": {
+              "description": "Filter 5 data 0 register",
+              "offset": 616,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F5DATA1": {
+              "description": "Filter 5 data 1 register",
+              "offset": 620,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F6DATA0": {
+              "description": "Filter 6 data 0 register",
+              "offset": 624,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F6DATA1": {
+              "description": "Filter 6 data 1 register",
+              "offset": 628,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F7DATA0": {
+              "description": "Filter 7 data 0 register",
+              "offset": 632,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F7DATA1": {
+              "description": "Filter 7 data 1 register",
+              "offset": 636,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F8DATA0": {
+              "description": "Filter 8 data 0 register",
+              "offset": 640,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F8DATA1": {
+              "description": "Filter 8 data 1 register",
+              "offset": 644,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F9DATA0": {
+              "description": "Filter 9 data 0 register",
+              "offset": 648,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F9DATA1": {
+              "description": "Filter 9 data 1 register",
+              "offset": 652,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F10DATA0": {
+              "description": "Filter 10 data 0 register",
+              "offset": 656,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F10DATA1": {
+              "description": "Filter 10 data 1 register",
+              "offset": 660,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F11DATA0": {
+              "description": "Filter 11 data 0 register",
+              "offset": 664,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F11DATA1": {
+              "description": "Filter 11 data 1 register",
+              "offset": 668,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F12DATA0": {
+              "description": "Filter 12 data 0 register",
+              "offset": 672,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F12DATA1": {
+              "description": "Filter 12 data 1 register",
+              "offset": 676,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F13DATA0": {
+              "description": "Filter 13 data 0 register",
+              "offset": 680,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F13DATA1": {
+              "description": "Filter 13 data 1 register",
+              "offset": 684,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F14DATA0": {
+              "description": "Filter 14 data 0 register",
+              "offset": 688,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F14DATA1": {
+              "description": "Filter 14 data 1 register",
+              "offset": 692,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F15DATA0": {
+              "description": "Filter 15 data 0 register",
+              "offset": 696,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F15DATA1": {
+              "description": "Filter 15 data 1 register",
+              "offset": 700,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F16DATA0": {
+              "description": "Filter 16 data 0 register",
+              "offset": 704,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F16DATA1": {
+              "description": "Filter 16 data 1 register",
+              "offset": 708,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F17DATA0": {
+              "description": "Filter 17 data 0 register",
+              "offset": 712,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F17DATA1": {
+              "description": "Filter 17 data 1 register",
+              "offset": 716,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F18DATA0": {
+              "description": "Filter 18 data 0 register",
+              "offset": 720,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F18DATA1": {
+              "description": "Filter 18 data 1 register",
+              "offset": 724,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F19DATA0": {
+              "description": "Filter 19 data 0 register",
+              "offset": 728,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F19DATA1": {
+              "description": "Filter 19 data 1 register",
+              "offset": 732,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F20DATA0": {
+              "description": "Filter 20 data 0 register",
+              "offset": 736,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F20DATA1": {
+              "description": "Filter 20 data 1 register",
+              "offset": 740,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F21DATA0": {
+              "description": "Filter 21 data 0 register",
+              "offset": 744,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F21DATA1": {
+              "description": "Filter 21 data 1 register",
+              "offset": 748,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F22DATA0": {
+              "description": "Filter 22 data 0 register",
+              "offset": 752,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F22DATA1": {
+              "description": "Filter 22 data 1 register",
+              "offset": 756,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F23DATA0": {
+              "description": "Filter 23 data 0 register",
+              "offset": 760,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F23DATA1": {
+              "description": "Filter 23 data 1 register",
+              "offset": 764,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F24DATA0": {
+              "description": "Filter 24 data 0 register",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F24DATA1": {
+              "description": "Filter 24 data 1 register",
+              "offset": 772,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F25DATA0": {
+              "description": "Filter 25 data 0 register",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F25DATA1": {
+              "description": "Filter 25 data 1 register",
+              "offset": 780,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F26DATA0": {
+              "description": "Filter 26 data 0 register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F26DATA1": {
+              "description": "Filter 26 data 1 register",
+              "offset": 788,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F27DATA0": {
+              "description": "Filter 27 data 0 register",
+              "offset": 792,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "F27DATA1": {
+              "description": "Filter 27 data 1 register",
+              "offset": 796,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FD0": {
+                    "description": "Filter bits",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FD1": {
+                    "description": "Filter bits",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FD2": {
+                    "description": "Filter bits",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FD3": {
+                    "description": "Filter bits",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FD4": {
+                    "description": "Filter bits",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FD5": {
+                    "description": "Filter bits",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FD6": {
+                    "description": "Filter bits",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FD7": {
+                    "description": "Filter bits",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FD8": {
+                    "description": "Filter bits",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FD9": {
+                    "description": "Filter bits",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FD10": {
+                    "description": "Filter bits",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FD11": {
+                    "description": "Filter bits",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FD12": {
+                    "description": "Filter bits",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FD13": {
+                    "description": "Filter bits",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FD14": {
+                    "description": "Filter bits",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FD15": {
+                    "description": "Filter bits",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FD16": {
+                    "description": "Filter bits",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FD17": {
+                    "description": "Filter bits",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FD18": {
+                    "description": "Filter bits",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FD19": {
+                    "description": "Filter bits",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FD20": {
+                    "description": "Filter bits",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FD21": {
+                    "description": "Filter bits",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FD22": {
+                    "description": "Filter bits",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FD23": {
+                    "description": "Filter bits",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FD24": {
+                    "description": "Filter bits",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FD25": {
+                    "description": "Filter bits",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FD26": {
+                    "description": "Filter bits",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FD27": {
+                    "description": "Filter bits",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FD28": {
+                    "description": "Filter bits",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FD29": {
+                    "description": "Filter bits",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FD30": {
+                    "description": "Filter bits",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FD31": {
+                    "description": "Filter bits",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "WWDGT": {
+        "description": "Window watchdog timer",
+        "children": {
+          "registers": {
+            "CTL": {
+              "description": "Control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 127,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDGTEN": {
+                    "description": "Activation bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CNT": {
+                    "description": "7-bit counter",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "CFG": {
+              "description": "Configuration register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 127,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EWIE": {
+                    "description": "Early wakeup interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PSC": {
+                    "description": "Prescaler",
+                    "offset": 7,
+                    "size": 2
+                  },
+                  "WIN": {
+                    "description": "7-bit window value",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "STAT": {
+              "description": "Status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EWIF": {
+                    "description": "Early wakeup interrupt\n              flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CRC": {
+        "description": "cyclic redundancy check calculation unit",
+        "children": {
+          "registers": {
+            "DATA": {
+              "description": "Data register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "CRC calculation result bits",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FDATA": {
+              "description": "Free data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FDATA": {
+                    "description": "Free Data Register bits",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CTL": {
+              "description": "Control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RST": {
+                    "description": "reset bit",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DAC": {
+        "description": "Digital-to-analog converter",
+        "children": {
+          "registers": {
+            "CTL": {
+              "description": "control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DEN0": {
+                    "description": "DAC0 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DBOFF0": {
+                    "description": "DAC0 output buffer turn off",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DTEN0": {
+                    "description": "DAC0 trigger enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DTSEL0": {
+                    "description": "DAC0 trigger selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "DWM0": {
+                    "description": "DAC0 noise wave mode",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DWBW0": {
+                    "description": "DAC0 noise wave bit width",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "DDMAEN0": {
+                    "description": "DAC0 DMA enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DEN1": {
+                    "description": "DAC1 enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DBOFF1": {
+                    "description": "DAC1 output buffer turn off",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "DTEN1": {
+                    "description": "DAC1 trigger enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DTSEL1": {
+                    "description": "DAC1 trigger selection",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "DWM1": {
+                    "description": "DAC1 noise wave mode",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "DWBW1": {
+                    "description": "DAC1 noise wave bit width",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "DDMAEN1": {
+                    "description": "DAC1 DMA enable",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWT": {
+              "description": "software trigger register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "SWTR0": {
+                    "description": "DAC0 software trigger",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SWTR1": {
+                    "description": "DAC1 software trigger",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DAC0_R12DH": {
+              "description": "DAC0 12-bit right-aligned data holding register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAC0_DH": {
+                    "description": "DAC0 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DAC0_L12DH": {
+              "description": "DAC0 12-bit left-aligned data holding register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAC0_DH": {
+                    "description": "DAC0 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DAC0_R8DH": {
+              "description": "DAC0 8-bit right aligned data holding\n          register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAC0_DH": {
+                    "description": "DAC0 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DAC1_R12DH": {
+              "description": "DAC1 12-bit right-aligned data holding\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAC1_DH": {
+                    "description": "DAC1 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DAC1_L12DH": {
+              "description": "DAC1 12-bit left aligned data holding\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAC1_DH": {
+                    "description": "DAC1 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DAC1_R8DH": {
+              "description": "DAC1 8-bit right aligned data holding\n          register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAC1_DH": {
+                    "description": "DAC1 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DACC_R12DH": {
+              "description": "DAC concurrent mode 12-bit right-aligned data holding\n          register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAC0_DH": {
+                    "description": "DAC0 12-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "DAC1_DH": {
+                    "description": "DAC1 12-bit right-aligned\n              data",
+                    "offset": 16,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DACC_L12DH": {
+              "description": "DAC concurrent mode 12-bit left aligned data holding\n          register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAC0_DH": {
+                    "description": "DAC0 12-bit left-aligned\n              data",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "DAC1_DH": {
+                    "description": "DAC1 12-bit left-aligned\n              data",
+                    "offset": 20,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DACC_R8DH": {
+              "description": "DAC concurrent mode 8-bit right aligned data holding\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAC0_DH": {
+                    "description": "DAC0 8-bit right-aligned\n              data",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "DAC1_DH": {
+                    "description": "DAC1 8-bit right-aligned\n              data",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DAC0_DO": {
+              "description": "DAC0 data output register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DAC0_DO": {
+                    "description": "DAC0 data output",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DAC1_DO": {
+              "description": "DAC1 data output register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DAC1_DO": {
+                    "description": "DAC1 data output",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DBG": {
+        "description": "Debug support",
+        "children": {
+          "registers": {
+            "ID": {
+              "description": "ID code register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ID_CODE": {
+                    "description": "DBG ID code register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CTL": {
+              "description": "Control register 0",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_HOLD": {
+                    "description": "Sleep mode hold register",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DSLP_HOLD": {
+                    "description": "Deep-sleep mode hold register",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STB_HOLD": {
+                    "description": "Standby mode hold register",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FWDGT_HOLD": {
+                    "description": "FWDGT hold bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WWDGT_HOLD": {
+                    "description": "WWDGT hold bit",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TIMER0_HOLD": {
+                    "description": "TIMER 0 hold bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TIMER1_HOLD": {
+                    "description": "TIMER 1 hold bit",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TIMER2_HOLD": {
+                    "description": "TIMER 2 hold bit",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIMER3_HOLD": {
+                    "description": "TIMER 23 hold bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CAN0_HOLD": {
+                    "description": "CAN0 hold bit",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "I2C0_HOLD": {
+                    "description": "I2C0 hold bit",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "I2C1_HOLD": {
+                    "description": "I2C1 hold bit",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TIMER4_HOLD": {
+                    "description": "TIMER4_HOLD",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TIMER5_HOLD": {
+                    "description": "TIMER 5 hold bit",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TIMER6_HOLD": {
+                    "description": "TIMER 6 hold bit",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CAN1_HOLD": {
+                    "description": "CAN1 hold bit",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DMA0": {
+        "description": "DMA controller",
+        "children": {
+          "registers": {
+            "INTF": {
+              "description": "Interrupt flag register ",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "GIF0": {
+                    "description": "Global interrupt flag of channel 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIF0": {
+                    "description": "Full Transfer finish flag of channe 0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIF0": {
+                    "description": "Half transfer finish flag of channel 0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIF0": {
+                    "description": "Error flag of channel 0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GIF1": {
+                    "description": "Global interrupt flag of channel 1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FTFIF1": {
+                    "description": "Full Transfer finish flag of channe 1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HTFIF1": {
+                    "description": "Half transfer finish flag of channel 1",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ERRIF1": {
+                    "description": "Error flag of channel 1",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GIF2": {
+                    "description": "Global interrupt flag of channel 2",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FTFIF2": {
+                    "description": "Full Transfer finish flag of channe 2",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HTFIF2": {
+                    "description": "Half transfer finish flag of channel 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ERRIF2": {
+                    "description": "Error flag of channel 2",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GIF3": {
+                    "description": "Global interrupt flag of channel 3",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FTFIF3": {
+                    "description": "Full Transfer finish flag of channe 3",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "HTFIF3": {
+                    "description": "Half transfer finish flag of channel 3",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ERRIF3": {
+                    "description": "Error flag of channel 3",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GIF4": {
+                    "description": "Global interrupt flag of channel 4",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FTFIF4": {
+                    "description": "Full Transfer finish flag of channe 4",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "HTFIF4": {
+                    "description": "Half transfer finish flag of channel 4",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "ERRIF4": {
+                    "description": "Error flag of channel 4",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GIF5": {
+                    "description": "Global interrupt flag of channel 5",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FTFIF5": {
+                    "description": "Full Transfer finish flag of channe 5",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HTFIF5": {
+                    "description": "Half transfer finish flag of channel 5",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "ERRIF5": {
+                    "description": "Error flag of channel 5",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GIF6": {
+                    "description": "Global interrupt flag of channel 6",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FTFIF6": {
+                    "description": "Full Transfer finish flag of channe 6",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "HTFIF6": {
+                    "description": "Half transfer finish flag of channel 6",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "ERRIF6": {
+                    "description": "Error flag of channel 6",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTC": {
+              "description": "Interrupt flag clear register ",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "GIFC0": {
+                    "description": "Clear global interrupt flag of channel 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIFC0": {
+                    "description": "Clear bit for full transfer finish flag of channel 0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIFC0": {
+                    "description": "Clear bit for half transfer finish flag of channel 0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIFC0": {
+                    "description": "Clear bit for error flag of channel 0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GIFC1": {
+                    "description": "Clear global interrupt flag of channel 1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FTFIFC1": {
+                    "description": "Clear bit for full transfer finish flag of channel 1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HTFIFC1": {
+                    "description": "Clear bit for half transfer finish flag of channel 1",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ERRIFC1": {
+                    "description": "Clear bit for error flag of channel 1",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GIFC2": {
+                    "description": "Clear global interrupt flag of channel 2",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FTFIFC2": {
+                    "description": "Clear bit for full transfer finish flag of channel 2",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HTFIFC2": {
+                    "description": "Clear bit for half transfer finish flag of channel 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ERRIFC2": {
+                    "description": "Clear bit for error flag of channel 2",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GIFC3": {
+                    "description": "Clear global interrupt flag of channel 3",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FTFIFC3": {
+                    "description": "Clear bit for full transfer finish flag of channel 3",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "HTFIFC3": {
+                    "description": "Clear bit for half transfer finish flag of channel 3",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ERRIFC3": {
+                    "description": "Clear bit for error flag of channel 3",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GIFC4": {
+                    "description": "Clear global interrupt flag of channel 4",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FTFIFC4": {
+                    "description": "Clear bit for full transfer finish flag of channel 4",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "HTFIFC4": {
+                    "description": "Clear bit for half transfer finish flag of channel 4",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "ERRIFC4": {
+                    "description": "Clear bit for error flag of channel 4",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GIFC5": {
+                    "description": "Clear global interrupt flag of channel 5",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FTFIFC5": {
+                    "description": "Clear bit for full transfer finish flag of channel 5",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HTFIFC5": {
+                    "description": "Clear bit for half transfer finish flag of channel 5",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "ERRIFC5": {
+                    "description": "Clear bit for error flag of channel 5",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GIFC6": {
+                    "description": "Clear global interrupt flag of channel 6",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FTFIFC6": {
+                    "description": "Clear bit for full transfer finish flag of channel 6",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "HTFIFC6": {
+                    "description": "Clear bit for half transfer finish flag of channel 6",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "ERRIFC6": {
+                    "description": "Clear bit for error flag of channel 6",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH0CTL": {
+              "description": "Channel 0 control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH0CNT": {
+              "description": "Channel 0 counter register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH0PADDR": {
+              "description": "Channel 0 peripheral base address register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH0MADDR": {
+              "description": "Channel 0 memory base address register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH1CTL": {
+              "description": "Channel 1 control register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH1CNT": {
+              "description": "Channel 1 counter register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH1PADDR": {
+              "description": "Channel 1 peripheral base address register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH1MADDR": {
+              "description": "Channel 1 memory base address register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH2CTL": {
+              "description": "Channel 2 control register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH2CNT": {
+              "description": "Channel 2 counter register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH2PADDR": {
+              "description": "Channel 2 peripheral base address register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH2MADDR": {
+              "description": "Channel 2 memory base address register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH3CTL": {
+              "description": "Channel 3 control register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH3CNT": {
+              "description": "Channel 3 counter register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH3PADDR": {
+              "description": "Channel 3 peripheral base address register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH3MADDR": {
+              "description": "Channel 3 memory base address register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH4CTL": {
+              "description": "Channel 4 control register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH4CNT": {
+              "description": "Channel 4 counter register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH4PADDR": {
+              "description": "Channel 4 peripheral base address register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH4MADDR": {
+              "description": "Channel 4 memory base address register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH5CTL": {
+              "description": "Channel 5 control register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH5CNT": {
+              "description": "Channel 5 counter register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH5PADDR": {
+              "description": "Channel 5 peripheral base address register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH5MADDR": {
+              "description": "Channel 5 memory base address register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH6CTL": {
+              "description": "Channel 6 control register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH6CNT": {
+              "description": "Channel 6 counter register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH6PADDR": {
+              "description": "Channel 6 peripheral base address register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH6MADDR": {
+              "description": "Channel 6 memory base address register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DMA1": {
+        "description": "Direct memory access controller",
+        "children": {
+          "registers": {
+            "INTF": {
+              "description": "Interrupt flag register ",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "GIF0": {
+                    "description": "Global interrupt flag of channel 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIF0": {
+                    "description": "Full Transfer finish flag of channe 0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIF0": {
+                    "description": "Half transfer finish flag of channel 0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIF0": {
+                    "description": "Error flag of channel 0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GIF1": {
+                    "description": "Global interrupt flag of channel 1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FTFIF1": {
+                    "description": "Full Transfer finish flag of channe 1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HTFIF1": {
+                    "description": "Half transfer finish flag of channel 1",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ERRIF1": {
+                    "description": "Error flag of channel 1",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GIF2": {
+                    "description": "Global interrupt flag of channel 2",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FTFIF2": {
+                    "description": "Full Transfer finish flag of channe 2",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HTFIF2": {
+                    "description": "Half transfer finish flag of channel 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ERRIF2": {
+                    "description": "Error flag of channel 2",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GIF3": {
+                    "description": "Global interrupt flag of channel 3",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FTFIF3": {
+                    "description": "Full Transfer finish flag of channe 3",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "HTFIF3": {
+                    "description": "Half transfer finish flag of channel 3",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ERRIF3": {
+                    "description": "Error flag of channel 3",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GIF4": {
+                    "description": "Global interrupt flag of channel 4",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FTFIF4": {
+                    "description": "Full Transfer finish flag of channe 4",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "HTFIF4": {
+                    "description": "Half transfer finish flag of channel 4",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "ERRIF4": {
+                    "description": "Error flag of channel 4",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTC": {
+              "description": "Interrupt flag clear register ",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "GIFC0": {
+                    "description": "Clear global interrupt flag of channel 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIFC0": {
+                    "description": "Clear bit for full transfer finish flag of channel 0",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIFC0": {
+                    "description": "Clear bit for half transfer finish flag of channel 0",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIFC0": {
+                    "description": "Clear bit for error flag of channel 0",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GIFC1": {
+                    "description": "Clear global interrupt flag of channel 1",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FTFIFC1": {
+                    "description": "Clear bit for full transfer finish flag of channel 1",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HTFIFC1": {
+                    "description": "Clear bit for half transfer finish flag of channel 1",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ERRIFC1": {
+                    "description": "Clear bit for error flag of channel 1",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GIFC2": {
+                    "description": "Clear global interrupt flag of channel 2",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FTFIFC2": {
+                    "description": "Clear bit for full transfer finish flag of channel 2",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HTFIFC2": {
+                    "description": "Clear bit for half transfer finish flag of channel 2",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ERRIFC2": {
+                    "description": "Clear bit for error flag of channel 2",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GIFC3": {
+                    "description": "Clear global interrupt flag of channel 3",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FTFIFC3": {
+                    "description": "Clear bit for full transfer finish flag of channel 3",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "HTFIFC3": {
+                    "description": "Clear bit for half transfer finish flag of channel 3",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ERRIFC3": {
+                    "description": "Clear bit for error flag of channel 3",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GIFC4": {
+                    "description": "Clear global interrupt flag of channel 4",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FTFIFC4": {
+                    "description": "Clear bit for full transfer finish flag of channel 4",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "HTFIFC4": {
+                    "description": "Clear bit for half transfer finish flag of channel 4",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "ERRIFC4": {
+                    "description": "Clear bit for error flag of channel 4",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH0CTL": {
+              "description": "Channel 0 control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH0CNT": {
+              "description": "Channel 0 counter register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH0PADDR": {
+              "description": "Channel 0 peripheral base address register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH0MADDR": {
+              "description": "Channel 0 memory base address register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH1CTL": {
+              "description": "Channel 1 control register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH1CNT": {
+              "description": "Channel 1 counter register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH1PADDR": {
+              "description": "Channel 1 peripheral base address register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH1MADDR": {
+              "description": "Channel 1 memory base address register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH2CTL": {
+              "description": "Channel 2 control register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH2CNT": {
+              "description": "Channel 2 counter register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH2PADDR": {
+              "description": "Channel 2 peripheral base address register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH2MADDR": {
+              "description": "Channel 2 memory base address register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH3CTL": {
+              "description": "Channel 3 control register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH3CNT": {
+              "description": "Channel 3 counter register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH3PADDR": {
+              "description": "Channel 3 peripheral base address register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH3MADDR": {
+              "description": "Channel 3 memory base address register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH4CTL": {
+              "description": "Channel 4 control register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CHEN": {
+                    "description": "Channel enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTFIE": {
+                    "description": "Enable bit for channel full transfer finish interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HTFIE": {
+                    "description": "Enable bit for channel half transfer finish interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Enable bit for channel error interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DIR": {
+                    "description": "Transfer direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CMEN": {
+                    "description": "Circular mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PNAGA": {
+                    "description": "Next address generation algorithm of peripheral",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MNAGA": {
+                    "description": "Next address generation algorithm of memory",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PWIDTH": {
+                    "description": "Transfer data size of peripheral",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "MWIDTH": {
+                    "description": "Transfer data size of memory",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "PRIO": {
+                    "description": "Priority level",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "M2M": {
+                    "description": "Memory to Memory Mode",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH4CNT": {
+              "description": "Channel 4 counter register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Transfer counter",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH4PADDR": {
+              "description": "Channel 4 peripheral base address register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PADDR": {
+                    "description": "Peripheral base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH4MADDR": {
+              "description": "Channel 4 memory base address register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MADDR": {
+                    "description": "Memory base address",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EXMC": {
+        "description": "External memory controller",
+        "children": {
+          "registers": {
+            "SNCTL0": {
+              "description": "SRAM/NOR flash control register 0",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 12506,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ASYNCWAIT": {
+                    "description": "Asynchronous wait",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "NRWTEN": {
+                    "description": "NWAIT signal enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "Write enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NRWTPOL": {
+                    "description": "NWAIT signal polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "NREN": {
+                    "description": "NOR Flash access enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NRW": {
+                    "description": "NOR bank memory data bus width",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "NRTP": {
+                    "description": "NOR bank memory type",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "NRMUX": {
+                    "description": "NOR bank memory address/data multiplexing",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "NRBKEN": {
+                    "description": "NOR bank enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SNTCFG0": {
+              "description": "SRAM/NOR flash timing configuration register 0",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 268435455,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUSLAT": {
+                    "description": "Bus latency",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "DSET": {
+                    "description": "Data setup time",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "AHLD": {
+                    "description": "Address hold time",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "ASET": {
+                    "description": "Address setup time",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SNCTL1": {
+              "description": "SRAM/NOR flash control register 1",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 12506,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ASYNCWAIT": {
+                    "description": "Asynchronous wait",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "NRWTEN": {
+                    "description": "NWAIT signal enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WREN": {
+                    "description": "Write enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "NRWTPOL": {
+                    "description": "NWAIT signal polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "NREN": {
+                    "description": "NOR Flash access enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "NRW": {
+                    "description": "NOR bank memory data bus width",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "NRTP": {
+                    "description": "NOR bank memory type",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "NRMUX": {
+                    "description": "NOR bank memory address/data multiplexing",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "NRBKEN": {
+                    "description": "NOR bank enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EXTI": {
+        "description": "External interrupt/event\n      controller",
+        "children": {
+          "registers": {
+            "INTEN": {
+              "description": "Interrupt enable register\n          (EXTI_INTEN)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTEN0": {
+                    "description": "Enable Interrupt on line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "INTEN1": {
+                    "description": "Enable Interrupt on line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INTEN2": {
+                    "description": "Enable Interrupt on line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "INTEN3": {
+                    "description": "Enable Interrupt on line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "INTEN4": {
+                    "description": "Enable Interrupt on line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "INTEN5": {
+                    "description": "Enable Interrupt on line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INTEN6": {
+                    "description": "Enable Interrupt on line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "INTEN7": {
+                    "description": "Enable Interrupt on line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "INTEN8": {
+                    "description": "Enable Interrupt on line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "INTEN9": {
+                    "description": "Enable Interrupt on line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "INTEN10": {
+                    "description": "Enable Interrupt on line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "INTEN11": {
+                    "description": "Enable Interrupt on line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "INTEN12": {
+                    "description": "Enable Interrupt on line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "INTEN13": {
+                    "description": "Enable Interrupt on line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "INTEN14": {
+                    "description": "Enable Interrupt on line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "INTEN15": {
+                    "description": "Enable Interrupt on line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "INTEN16": {
+                    "description": "Enable Interrupt on line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "INTEN17": {
+                    "description": "Enable Interrupt on line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTEN18": {
+                    "description": "Enable Interrupt on line 18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EVEN": {
+              "description": "Event enable register (EXTI_EVEN)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EVEN0": {
+                    "description": "Enable Event on line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EVEN1": {
+                    "description": "Enable Event on line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EVEN2": {
+                    "description": "Enable Event on line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EVEN3": {
+                    "description": "Enable Event on line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EVEN4": {
+                    "description": "Enable Event on line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EVEN5": {
+                    "description": "Enable Event on line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EVEN6": {
+                    "description": "Enable Event on line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EVEN7": {
+                    "description": "Enable Event on line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EVEN8": {
+                    "description": "Enable Event on line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EVEN9": {
+                    "description": "Enable Event on line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EVEN10": {
+                    "description": "Enable Event on line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EVEN11": {
+                    "description": "Enable Event on line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EVEN12": {
+                    "description": "Enable Event on line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EVEN13": {
+                    "description": "Enable Event on line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EVEN14": {
+                    "description": "Enable Event on line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EVEN15": {
+                    "description": "Enable Event on line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EVEN16": {
+                    "description": "Enable Event on line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EVEN17": {
+                    "description": "Enable Event on line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EVEN18": {
+                    "description": "Enable Event on line 18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RTEN": {
+              "description": "Rising Edge Trigger Enable register\n          (EXTI_RTEN)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTEN0": {
+                    "description": "Rising edge trigger enable of\n              line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RTEN1": {
+                    "description": "Rising edge trigger enable of\n              line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RTEN2": {
+                    "description": "Rising edge trigger enable of\n              line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTEN3": {
+                    "description": "Rising edge trigger enable of\n              line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RTEN4": {
+                    "description": "Rising edge trigger enable of\n              line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RTEN5": {
+                    "description": "Rising edge trigger enable of\n              line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RTEN6": {
+                    "description": "Rising edge trigger enable of\n              line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RTEN7": {
+                    "description": "Rising edge trigger enable of\n              line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RTEN8": {
+                    "description": "Rising edge trigger enable of\n              line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RTEN9": {
+                    "description": "Rising edge trigger enable of\n              line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RTEN10": {
+                    "description": "Rising edge trigger enable of\n              line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RTEN11": {
+                    "description": "Rising edge trigger enable of\n              line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RTEN12": {
+                    "description": "Rising edge trigger enable of\n              line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RTEN13": {
+                    "description": "Rising edge trigger enable of\n              line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RTEN14": {
+                    "description": "Rising edge trigger enable of\n              line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RTEN15": {
+                    "description": "Rising edge trigger enable of\n              line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RTEN16": {
+                    "description": "Rising edge trigger enable of\n              line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RTEN17": {
+                    "description": "Rising edge trigger enable of\n              line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RTEN18": {
+                    "description": "Rising edge trigger enable of\n              line 18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FTEN": {
+              "description": "Falling Egde Trigger Enable register\n          (EXTI_FTEN)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FTEN0": {
+                    "description": "Falling edge trigger enable of\n              line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FTEN1": {
+                    "description": "Falling edge trigger enable of\n              line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FTEN2": {
+                    "description": "Falling edge trigger enable of\n              line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FTEN3": {
+                    "description": "Falling edge trigger enable of\n              line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FTEN4": {
+                    "description": "Falling edge trigger enable of\n              line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FTEN5": {
+                    "description": "Falling edge trigger enable of\n              line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FTEN6": {
+                    "description": "Falling edge trigger enable of\n              line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FTEN7": {
+                    "description": "Falling edge trigger enable of\n              line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FTEN8": {
+                    "description": "Falling edge trigger enable of\n              line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FTEN9": {
+                    "description": "Falling edge trigger enable of\n              line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FTEN10": {
+                    "description": "Falling edge trigger enable of\n              line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FTEN11": {
+                    "description": "Falling edge trigger enable of\n              line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FTEN12": {
+                    "description": "Falling edge trigger enable of\n              line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FTEN13": {
+                    "description": "Falling edge trigger enable of\n              line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FTEN14": {
+                    "description": "Falling edge trigger enable of\n              line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FTEN15": {
+                    "description": "Falling edge trigger enable of\n              line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "FTEN16": {
+                    "description": "Falling edge trigger enable of\n              line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FTEN17": {
+                    "description": "Falling edge trigger enable of\n              line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "FTEN18": {
+                    "description": "Falling edge trigger enable of\n              line 18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWIEV": {
+              "description": "Software interrupt event register\n          (EXTI_SWIEV)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWIEV0": {
+                    "description": "Interrupt/Event software trigger on line\n              0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SWIEV1": {
+                    "description": "Interrupt/Event software trigger on line\n              1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SWIEV2": {
+                    "description": "Interrupt/Event software trigger on line\n              2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SWIEV3": {
+                    "description": "Interrupt/Event software trigger on line\n              3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SWIEV4": {
+                    "description": "Interrupt/Event software trigger on line\n              4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SWIEV5": {
+                    "description": "Interrupt/Event software trigger on line\n              5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SWIEV6": {
+                    "description": "Interrupt/Event software trigger on line\n              6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SWIEV7": {
+                    "description": "Interrupt/Event software trigger on line\n              7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SWIEV8": {
+                    "description": "Interrupt/Event software trigger on line\n              8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SWIEV9": {
+                    "description": "Interrupt/Event software trigger on line\n              9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SWIEV10": {
+                    "description": "Interrupt/Event software trigger on line\n              10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SWIEV11": {
+                    "description": "Interrupt/Event software trigger on line\n              11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SWIEV12": {
+                    "description": "Interrupt/Event software trigger on line\n              12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SWIEV13": {
+                    "description": "Interrupt/Event software trigger on line\n              13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SWIEV14": {
+                    "description": "Interrupt/Event software trigger on line\n              14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SWIEV15": {
+                    "description": "Interrupt/Event software trigger on line\n              15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SWIEV16": {
+                    "description": "Interrupt/Event software trigger on line\n              16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SWIEV17": {
+                    "description": "Interrupt/Event software trigger on line\n              17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SWIEV18": {
+                    "description": "Interrupt/Event software trigger on line\n              18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PD": {
+              "description": "Pending register (EXTI_PD)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PD0": {
+                    "description": "Interrupt pending status of line 0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PD1": {
+                    "description": "Interrupt pending status of line 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PD2": {
+                    "description": "Interrupt pending status of line 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PD3": {
+                    "description": "Interrupt pending status of line 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PD4": {
+                    "description": "Interrupt pending status of line 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PD5": {
+                    "description": "Interrupt pending status of line 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PD6": {
+                    "description": "Interrupt pending status of line 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PD7": {
+                    "description": "Interrupt pending status of line 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PD8": {
+                    "description": "Interrupt pending status of line 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PD9": {
+                    "description": "Interrupt pending status of line 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PD10": {
+                    "description": "Interrupt pending status of line 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PD11": {
+                    "description": "Interrupt pending status of line 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PD12": {
+                    "description": "Interrupt pending status of line 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PD13": {
+                    "description": "Interrupt pending status of line 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PD14": {
+                    "description": "Interrupt pending status of line 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PD15": {
+                    "description": "Interrupt pending status of line 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "PD16": {
+                    "description": "Interrupt pending status of line 16",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PD17": {
+                    "description": "Interrupt pending status of line 17",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PD18": {
+                    "description": "Interrupt pending status of line 18",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FMC": {
+        "description": "FMC",
+        "children": {
+          "registers": {
+            "WS": {
+              "description": "wait state counter register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WSCNT": {
+                    "description": "wait state counter register",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "KEY0": {
+              "description": "Unlock key register 0",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "KEY": {
+                    "description": "FMC_CTL0 unlock key",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OBKEY": {
+              "description": "Option byte unlock key register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "OBKEY": {
+                    "description": "FMC_ CTL0 option byte operation unlock register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STAT0": {
+              "description": "Status register 0",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDF": {
+                    "description": "End of operation flag bit",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WPERR": {
+                    "description": "Erase/Program protection error flag bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PGERR": {
+                    "description": "Program error flag bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "The flash is busy bit",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CTL0": {
+              "description": "Control register 0",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDIE": {
+                    "description": "End of operation interrupt enable bit",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OBWEN": {
+                    "description": "Option byte erase/program enable bit",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LK": {
+                    "description": "FMC_CTL0 lock bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "START": {
+                    "description": "Send erase command to FMC bit",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OBER": {
+                    "description": "Option bytes erase command bit",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OBPG": {
+                    "description": "Option bytes program command bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "MER": {
+                    "description": "Main flash mass erase for bank0 command bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PER": {
+                    "description": "Main flash page erase for bank0 command bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PG": {
+                    "description": "Main flash program for bank0 command bit",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ADDR0": {
+              "description": "Address register 0",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "ADDR": {
+                    "description": "Flash erase/program command address bits",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OBSTAT": {
+              "description": "Option byte status register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "OBERR": {
+                    "description": "Option bytes read error bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SPC": {
+                    "description": "Option bytes security protection code",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "USER": {
+                    "description": "Store USER of option bytes block after system reset",
+                    "offset": 2,
+                    "size": 8
+                  },
+                  "DATA": {
+                    "description": "Store DATA[15:0] of option bytes block after system reset",
+                    "offset": 10,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "WP": {
+              "description": "Erase/Program Protection register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "WP": {
+                    "description": "Store WP[31:0] of option bytes block after system reset",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PID": {
+              "description": "Product ID register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PID": {
+                    "description": "Product reserved ID code register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "FWDGT": {
+        "description": "free watchdog timer",
+        "children": {
+          "registers": {
+            "CTL": {
+              "description": "Control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CMD": {
+                    "description": "Key value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "Prescaler register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Free watchdog timer prescaler selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "RLD": {
+              "description": "Reload register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RLD": {
+                    "description": "Free watchdog timer counter reload value",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "STAT": {
+              "description": "Status register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PUD": {
+                    "description": "Free watchdog timer prescaler value update",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RUD": {
+                    "description": "Free watchdog timer counter reload value update",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOA": {
+        "description": "General-purpose I/Os",
+        "children": {
+          "registers": {
+            "CTL0": {
+              "description": "port control register 0",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1145324612,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTL7": {
+                    "description": "Port x configuration bits (x =\n              7)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MD7": {
+                    "description": "Port x mode bits (x =\n              7)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CTL6": {
+                    "description": "Port x configuration bits (x =\n              6)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MD6": {
+                    "description": "Port x mode bits (x =\n              6)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CTL5": {
+                    "description": "Port x configuration bits (x =\n              5)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MD5": {
+                    "description": "Port x mode bits (x =\n              5)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "CTL4": {
+                    "description": "Port x configuration bits (x =\n              4)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MD4": {
+                    "description": "Port x mode bits (x =\n              4)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CTL3": {
+                    "description": "Port x configuration bits (x =\n              3)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MD3": {
+                    "description": "Port x mode bits (x =\n             3 )",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CTL2": {
+                    "description": "Port x configuration bits (x =\n              2)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MD2": {
+                    "description": "Port x mode bits (x =\n             2 )",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CTL1": {
+                    "description": "Port x configuration bits (x =\n              1)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MD1": {
+                    "description": "Port x mode bits (x =\n              1)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CTL0": {
+                    "description": "Port x configuration bits (x =\n              0)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MD0": {
+                    "description": "Port x mode bits (x =\n              0)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CTL1": {
+              "description": "port control register 1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 1145324612,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTL15": {
+                    "description": "Port x configuration bits (x =\n              15)",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "MD15": {
+                    "description": "Port x mode bits (x =\n              15)",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CTL14": {
+                    "description": "Port x configuration bits (x =\n              14)",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "MD14": {
+                    "description": "Port x mode bits (x =\n              14)",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CTL13": {
+                    "description": "Port x configuration bits (x =\n              13)",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "MD13": {
+                    "description": "Port x mode bits (x =\n              13)",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "CTL12": {
+                    "description": "Port x configuration bits (x =\n              12)",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "MD12": {
+                    "description": "Port x mode bits (x =\n              12)",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CTL11": {
+                    "description": "Port x configuration bits (x =\n              11)",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "MD11": {
+                    "description": "Port x mode bits (x =\n             11 )",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CTL10": {
+                    "description": "Port x configuration bits (x =\n              10)",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MD10": {
+                    "description": "Port x mode bits (x =\n             10 )",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CTL9": {
+                    "description": "Port x configuration bits (x =\n              9)",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "MD9": {
+                    "description": "Port x mode bits (x =\n              9)",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CTL8": {
+                    "description": "Port x configuration bits (x =\n              8)",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "MD8": {
+                    "description": "Port x mode bits (x =\n              8)",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "ISTAT": {
+              "description": "Port input status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "ISTAT15": {
+                    "description": "Port input status",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ISTAT14": {
+                    "description": "Port input status",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ISTAT13": {
+                    "description": "Port input status",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISTAT12": {
+                    "description": "Port input status",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ISTAT11": {
+                    "description": "Port input status",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ISTAT10": {
+                    "description": "Port input status",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ISTAT9": {
+                    "description": "Port input status",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ISTAT8": {
+                    "description": "Port input status",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ISTAT7": {
+                    "description": "Port input status",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ISTAT6": {
+                    "description": "Port input status",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ISTAT5": {
+                    "description": "Port input status",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ISTAT4": {
+                    "description": "Port input status",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ISTAT3": {
+                    "description": "Port input status",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ISTAT2": {
+                    "description": "Port input status",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ISTAT1": {
+                    "description": "Port input status",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ISTAT0": {
+                    "description": "Port input status",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OCTL": {
+              "description": "Port output control register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OCTL15": {
+                    "description": "Port output control",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OCTL14": {
+                    "description": "Port output control",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OCTL13": {
+                    "description": "Port output control",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OCTL12": {
+                    "description": "Port output control",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OCTL11": {
+                    "description": "Port output control",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OCTL10": {
+                    "description": "Port output control",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OCTL9": {
+                    "description": "Port output control",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OCTL8": {
+                    "description": "Port output control",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OCTL7": {
+                    "description": "Port output control",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OCTL6": {
+                    "description": "Port output control",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "OCTL5": {
+                    "description": "Port output control",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OCTL4": {
+                    "description": "Port output control",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OCTL3": {
+                    "description": "Port output control",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OCTL2": {
+                    "description": "Port output control",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OCTL1": {
+                    "description": "Port output control",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OCTL0": {
+                    "description": "Port output control",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BOP": {
+              "description": "Port bit operate register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CR15": {
+                    "description": "Port 15 Clear bit",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "CR14": {
+                    "description": "Port 14 Clear bit",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CR13": {
+                    "description": "Port 13 Clear bit",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CR12": {
+                    "description": "Port 12 Clear bit",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "CR11": {
+                    "description": "Port 11 Clear bit",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "CR10": {
+                    "description": "Port 10 Clear bit",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CR9": {
+                    "description": "Port 9 Clear bit",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CR8": {
+                    "description": "Port 8 Clear bit",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "CR7": {
+                    "description": "Port 7 Clear bit",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CR6": {
+                    "description": "Port 6 Clear bit",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CR5": {
+                    "description": "Port 5 Clear bit",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CR4": {
+                    "description": "Port 4 Clear bit",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CR3": {
+                    "description": "Port 3 Clear bit",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "CR2": {
+                    "description": "Port 2 Clear bit",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CR1": {
+                    "description": "Port 1 Clear bit",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "CR0": {
+                    "description": "Port 0 Clear bit",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BOP15": {
+                    "description": "Port 15 Set bit",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BOP14": {
+                    "description": "Port 14 Set bit",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BOP13": {
+                    "description": "Port 13 Set bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BOP12": {
+                    "description": "Port 12 Set bit",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BOP11": {
+                    "description": "Port 11 Set bit",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BOP10": {
+                    "description": "Port 10 Set bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BOP9": {
+                    "description": "Port 9 Set bit",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BOP8": {
+                    "description": "Port 8 Set bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BOP7": {
+                    "description": "Port 7 Set bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BOP6": {
+                    "description": "Port 6 Set bit",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BOP5": {
+                    "description": "Port 5 Set bit",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BOP4": {
+                    "description": "Port 4 Set bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BOP3": {
+                    "description": "Port 3 Set bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BOP2": {
+                    "description": "Port 2 Set bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "BOP1": {
+                    "description": "Port 1 Set bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BOP0": {
+                    "description": "Port 0 Set bit",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BC": {
+              "description": "Port bit clear register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "CR15": {
+                    "description": "Port 15 Clear bit",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CR14": {
+                    "description": "Port 14 Clear bit",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CR13": {
+                    "description": "Port 13 Clear bit",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CR12": {
+                    "description": "Port 12 Clear bit",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CR11": {
+                    "description": "Port 11 Clear bit",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CR10": {
+                    "description": "Port 10 Clear bit",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CR9": {
+                    "description": "Port 9 Clear bit",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CR8": {
+                    "description": "Port 8 Clear bit",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CR7": {
+                    "description": "Port 7 Clear bit",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CR6": {
+                    "description": "Port 6 Clear bit",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CR5": {
+                    "description": "Port 5 Clear bit",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CR4": {
+                    "description": "Port 4 Clear bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CR3": {
+                    "description": "Port 3 Clear bit",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CR2": {
+                    "description": "Port 2 Clear bit",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CR1": {
+                    "description": "Port 1 Clear bit",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CR0": {
+                    "description": "Port 0 Clear bit",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LOCK": {
+              "description": "GPIO port configuration lock\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LKK": {
+                    "description": "Lock sequence key\n              ",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "LK15": {
+                    "description": "Port Lock bit 15",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LK14": {
+                    "description": "Port Lock bit 14",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "LK13": {
+                    "description": "Port Lock bit 13",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LK12": {
+                    "description": "Port Lock bit 12",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "LK11": {
+                    "description": "Port Lock bit 11",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "LK10": {
+                    "description": "Port Lock bit 10",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LK9": {
+                    "description": "Port Lock bit 9",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LK8": {
+                    "description": "Port Lock bit 8",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LK7": {
+                    "description": "Port Lock bit 7",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LK6": {
+                    "description": "Port Lock bit 6",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LK5": {
+                    "description": "Port Lock bit 5",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "LK4": {
+                    "description": "Port Lock bit 4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "LK3": {
+                    "description": "Port Lock bit 3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LK2": {
+                    "description": "Port Lock bit 2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LK1": {
+                    "description": "Port Lock bit 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LK0": {
+                    "description": "Port Lock bit 0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USBFS_PWRCLK": {
+        "description": "USB on the go full speed",
+        "children": {
+          "registers": {
+            "PWRCLKCTL": {
+              "description": "power and clock gating control\n          register (PWRCLKCTL)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SUCLK": {
+                    "description": "Stop the USB clock",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SHCLK": {
+                    "description": "Stop HCLK",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USBFS_DEVICE": {
+        "description": "USB on the go full speed device",
+        "children": {
+          "registers": {
+            "DCFG": {
+              "description": "device configuration register\n          (DCFG)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DS": {
+                    "description": "Device speed",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "NZLSOH": {
+                    "description": "Non-zero-length status OUT\n              handshake",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DAR": {
+                    "description": "Device address",
+                    "offset": 4,
+                    "size": 7
+                  },
+                  "EOPFT": {
+                    "description": "end of periodic frame time",
+                    "offset": 11,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DCTL": {
+              "description": "device control register\n          (DCTL)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWKUP": {
+                    "description": "Remote wakeup",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SD": {
+                    "description": "Soft disconnect",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GINS": {
+                    "description": "Global IN NAK status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GONS": {
+                    "description": "Global OUT NAK status",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SGINAK": {
+                    "description": "Set global IN NAK",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CGINAK": {
+                    "description": "Clear global IN NAK",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SGONAK": {
+                    "description": "Set global OUT NAK",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CGONAK": {
+                    "description": "Clear global OUT NAK",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "POIF": {
+                    "description": "Power-on initialization flag",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DSTAT": {
+              "description": "device status register\n          (DSTAT)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "SPST": {
+                    "description": "Suspend status",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ES": {
+                    "description": "Enumerated speed",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "FNRSOF": {
+                    "description": "Frame number of the received\n              SOF",
+                    "offset": 8,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "DIEPINTEN": {
+              "description": "device IN endpoint common interrupt\n          mask register (DIEPINTEN)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TFEN": {
+                    "description": "Transfer finished interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISEN": {
+                    "description": "Endpoint disabled interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CITOEN": {
+                    "description": "Control IN timeout condition interrupt enable (Non-isochronous\n              endpoints)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPTXFUDEN": {
+                    "description": "Endpoint Tx FIFO underrun interrupt enable bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IEPNEEN": {
+                    "description": "IN endpoint NAK effective\n              interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEPINTEN": {
+              "description": "device OUT endpoint common interrupt\n          enable register (DOEPINTEN)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TFEN": {
+                    "description": "Transfer finished interrupt\n              enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EPDISEN": {
+                    "description": "Endpoint disabled interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STPFEN": {
+                    "description": "SETUP phase finished interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPRXFOVREN": {
+                    "description": " Endpoint Rx FIFO overrun interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BTBSTPEN": {
+                    "description": " Back-to-back SETUP packets\n               interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DAEPINT": {
+              "description": "device all endpoints interrupt\n          register (DAEPINT)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IEPITB": {
+                    "description": "Device all IN endpoint interrupt bits",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "OEPITB": {
+                    "description": "Device all OUT endpoint interrupt bits",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DAEPINTEN": {
+              "description": "Device all endpoints interrupt enable register\n          (DAEPINTEN)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEPIE": {
+                    "description": "IN EP interrupt interrupt enable bits",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "OEPIE": {
+                    "description": "OUT endpoint interrupt enable bits",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DVBUSDT": {
+              "description": "device VBUS discharge time\n          register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 6103,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DVBUSDT": {
+                    "description": "Device VBUS discharge time",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DVBUSPT": {
+              "description": "device VBUS pulsing time\n          register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 1464,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DVBUSPT": {
+                    "description": "Device VBUS pulsing time",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DIEPFEINTEN": {
+              "description": "device IN endpoint FIFO empty\n          interrupt enable register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEPTXFEIE": {
+                    "description": "IN EP Tx FIFO empty interrupt enable\n              bits",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DIEP0CTL": {
+              "description": "device IN endpoint 0 control\n          register (DIEP0CTL)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPL": {
+                    "description": "Maximum packet length",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "EPACT": {
+                    "description": "endpoint active",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NAKS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "STALL": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "EPD": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EPEN": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEP1CTL": {
+              "description": "device in endpoint-1 control\n          register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPEN": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPD": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SD1PID_SODDFRM": {
+                    "description": "Set DATA1 PID/Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVENFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "Tx FIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "STALL": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EOFRM_DPID": {
+                    "description": "EOFRM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPACT": {
+                    "description": "Endpoint active",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPL": {
+                    "description": "maximum packet length",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEP2CTL": {
+              "description": "device endpoint-2 control\n          register",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPEN": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPD": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SD1PID_SODDFRM": {
+                    "description": "Set DATA1 PID/Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVENFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "Tx FIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "STALL": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EOFRM_DPID": {
+                    "description": "EOFRM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPACT": {
+                    "description": "Endpoint active",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPL": {
+                    "description": "maximum packet length",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEP3CTL": {
+              "description": "device endpoint-3 control\n          register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPEN": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPD": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SD1PID_SODDFRM": {
+                    "description": "Set DATA1 PID/Set odd frame",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVENFRM": {
+                    "description": "SD0PID/SEVNFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFNUM": {
+                    "description": "Tx FIFO number",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "STALL": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EOFRM_DPID": {
+                    "description": "EOFRM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPACT": {
+                    "description": "Endpoint active",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPL": {
+                    "description": "maximum packet length",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEP0CTL": {
+              "description": "device endpoint-0 control\n          register",
+              "offset": 768,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPEN": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPD": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "STALL": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNOOP": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "NAKS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPACT": {
+                    "description": "Endpoint active",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MPL": {
+                    "description": "Maximum packet length",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DOEP1CTL": {
+              "description": "device endpoint-1 control\n          register",
+              "offset": 800,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPEN": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPD": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SD1PID_SODDFRM": {
+                    "description": "SD1PID/SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVENFRM": {
+                    "description": "SD0PID/SEVENFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "STALL": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNOOP": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EOFRM_DPID": {
+                    "description": "EOFRM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPACT": {
+                    "description": "Endpoint active",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPL": {
+                    "description": "maximum packet length",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEP2CTL": {
+              "description": "device endpoint-2 control\n          register",
+              "offset": 832,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPEN": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPD": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SD1PID_SODDFRM": {
+                    "description": "SD1PID/SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVENFRM": {
+                    "description": "SD0PID/SEVENFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "STALL": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNOOP": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EOFRM_DPID": {
+                    "description": "EOFRM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPACT": {
+                    "description": "Endpoint active",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPL": {
+                    "description": "maximum packet length",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DOEP3CTL": {
+              "description": "device endpoint-3 control\n          register",
+              "offset": 864,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EPEN": {
+                    "description": "Endpoint enable",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EPD": {
+                    "description": "Endpoint disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SD1PID_SODDFRM": {
+                    "description": "SD1PID/SODDFRM",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SD0PID_SEVENFRM": {
+                    "description": "SD0PID/SEVENFRM",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SNAK": {
+                    "description": "Set NAK",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CNAK": {
+                    "description": "Clear NAK",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "STALL": {
+                    "description": "STALL handshake",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SNOOP": {
+                    "description": "Snoop mode",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "NAKS": {
+                    "description": "NAK status",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EOFRM_DPID": {
+                    "description": "EOFRM/DPID",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EPACT": {
+                    "description": "Endpoint active",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MPL": {
+                    "description": "maximum packet length",
+                    "offset": 0,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "DIEP0INTF": {
+              "description": "device endpoint-0 interrupt\n          register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPTXFUD": {
+                    "description": "Endpoint Tx FIFO underrun",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CITO": {
+                    "description": "Control in timeout interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint finished",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEP1INTF": {
+              "description": "device endpoint-1 interrupt\n          register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPTXFUD": {
+                    "description": "Endpoint Tx FIFO underrun",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CITO": {
+                    "description": "Control in timeout interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint finished",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEP2INTF": {
+              "description": "device endpoint-2 interrupt\n          register",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPTXFUD": {
+                    "description": "Endpoint Tx FIFO underrun",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CITO": {
+                    "description": "Control in timeout interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint finished",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEP3INTF": {
+              "description": "device endpoint-3 interrupt\n          register",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IEPNE": {
+                    "description": "IN endpoint NAK effective",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPTXFUD": {
+                    "description": "Endpoint Tx FIFO underrun",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CITO": {
+                    "description": "Control in timeout interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint finished",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEP0INTF": {
+              "description": "device out endpoint-0 interrupt flag \n          register",
+              "offset": 776,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BTBSTP": {
+                    "description": "Back-to-back SETUP packets",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPRXFOVR": {
+                    "description": "Endpoint Rx FIFO overrun",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STPF": {
+                    "description": "Setup phase finished",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disabled",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEP1INTF": {
+              "description": "device out endpoint-1 interrupt flag \n          register",
+              "offset": 808,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BTBSTP": {
+                    "description": "Back-to-back SETUP packets",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPRXFOVR": {
+                    "description": "Endpoint Rx FIFO overrun",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STPF": {
+                    "description": "Setup phase finished",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disabled",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEP2INTF": {
+              "description": "device out endpoint-2 interrupt flag \n          register",
+              "offset": 840,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BTBSTP": {
+                    "description": "Back-to-back SETUP packets",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPRXFOVR": {
+                    "description": "Endpoint Rx FIFO overrun",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STPF": {
+                    "description": "Setup phase finished",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disabled",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DOEP3INTF": {
+              "description": "device out endpoint-3 interrupt flag \n          register",
+              "offset": 872,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BTBSTP": {
+                    "description": "Back-to-back SETUP packets",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EPRXFOVR": {
+                    "description": "Endpoint Rx FIFO overrun",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STPF": {
+                    "description": "Setup phase finished",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPDIS": {
+                    "description": "Endpoint disabled",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIEP0LEN": {
+              "description": "device IN endpoint-0 transfer length\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 2
+                  },
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "DOEP0LEN": {
+              "description": "device OUT endpoint-0 transfer length\n          register",
+              "offset": 784,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STPCNT": {
+                    "description": "SETUP packet count",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "DIEP1LEN": {
+              "description": "device IN endpoint-1 transfer length\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCPF": {
+                    "description": "Multi packet count per frame",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DIEP2LEN": {
+              "description": "device IN endpoint-2 transfer length\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCPF": {
+                    "description": "Multi packet count per frame",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DIEP3LEN": {
+              "description": "device IN endpoint-3 transfer length\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCPF": {
+                    "description": "Multi packet count per frame",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DOEP1LEN": {
+              "description": "device OUT endpoint-1 transfer length\n          register",
+              "offset": 816,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STPCNT_RXDPID": {
+                    "description": "SETUP packet count/Received data PID",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DOEP2LEN": {
+              "description": "device OUT endpoint-2 transfer length\n          register",
+              "offset": 848,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STPCNT_RXDPID": {
+                    "description": "SETUP packet count/Received data PID",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DOEP3LEN": {
+              "description": "device OUT endpoint-3 transfer length\n          register",
+              "offset": 880,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STPCNT_RXDPID": {
+                    "description": "SETUP packet count/Received data PID",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "DIEP0TFSTAT": {
+              "description": "device IN endpoint  0 transmit FIFO\n          status register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IEPTFS": {
+                    "description": "IN endpoint TxFIFO space\n              remaining",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DIEP1TFSTAT": {
+              "description": "device IN endpoint 1 transmit FIFO\n          status register",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IEPTFS": {
+                    "description": "IN endpoint TxFIFO space\n              remaining",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DIEP2TFSTAT": {
+              "description": "device IN endpoint  2 transmit FIFO\n          status register",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IEPTFS": {
+                    "description": "IN endpoint TxFIFO space\n              remaining",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DIEP3TFSTAT": {
+              "description": "device IN endpoint  3 transmit FIFO\n          status register",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "IEPTFS": {
+                    "description": "IN endpoint TxFIFO space\n              remaining",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USBFS_HOST": {
+        "description": "USB on the go full speed host",
+        "children": {
+          "registers": {
+            "HCTL": {
+              "description": "host configuration register\n          (HCTL)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKSEL": {
+                    "description": "clock select for USB clock",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "HFT": {
+              "description": "Host frame interval\n          register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 48000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FRI": {
+                    "description": "Frame interval",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "HFINFR": {
+              "description": "FS host frame number/frame time\n          remaining register (HFINFR)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 3145728000,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "FRNUM": {
+                    "description": "Frame number",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "FRT": {
+                    "description": "Frame remaining time",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "HPTFQSTAT": {
+              "description": "Host periodic transmit FIFO/queue\n          status register (HPTFQSTAT)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 524800,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PTXFS": {
+                    "description": "Periodic transmit data FIFO space\n              available",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "PTXREQS": {
+                    "description": "Periodic transmit request queue space\n              available",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "PTXREQT": {
+                    "description": "Top of the periodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "HACHINT": {
+              "description": " Host all channels interrupt\n          register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "HACHINT": {
+                    "description": "Host all channel interrupts",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "HACHINTEN": {
+              "description": "host all channels interrupt mask\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CINTEN": {
+                    "description": "Channel interrupt enable",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "HPCS": {
+              "description": "Host port control and status register (USBFS_HPCS)",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PCST": {
+                    "description": "Port connect status",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PCD": {
+                    "description": "Port connect detected",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PE": {
+                    "description": "Port enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PEDC": {
+                    "description": "Port enable/disable change",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PREM": {
+                    "description": "Port resume",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PSP": {
+                    "description": "Port suspend",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PRST": {
+                    "description": "Port reset",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PLST": {
+                    "description": "Port line status",
+                    "offset": 10,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PP": {
+                    "description": "Port power",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PS": {
+                    "description": "Port speed",
+                    "offset": 17,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "HCH0CTL": {
+              "description": "host channel-0 characteristics\n          register (HCH0CTL)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPL": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSD": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "DAR": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH1CTL": {
+              "description": " host channel-1 characteristics\n          register (HCH1CTL)",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPL": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSD": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "DAR": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH2CTL": {
+              "description": "host channel-2 characteristics\n          register (HCH2CTL)",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPL": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSD": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "DAR": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH3CTL": {
+              "description": "host channel-3 characteristics\n          register (HCH3CTL)",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPL": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSD": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "DAR": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH4CTL": {
+              "description": " host channel-4 characteristics\n          register (HCH4CTL)",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPL": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSD": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "DAR": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH5CTL": {
+              "description": "host channel-5 characteristics\n          register (HCH5CTL)",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPL": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSD": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "DAR": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH6CTL": {
+              "description": "host channel-6 characteristics\n          register (HCH6CTL)",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPL": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSD": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "DAR": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH7CTL": {
+              "description": "host channel-7 characteristics\n          register (HCH7CTL)",
+              "offset": 480,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MPL": {
+                    "description": "Maximum packet size",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "EPDIR": {
+                    "description": "Endpoint direction",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LSD": {
+                    "description": "Low-speed device",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EPTYPE": {
+                    "description": "Endpoint type",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "DAR": {
+                    "description": "Device address",
+                    "offset": 22,
+                    "size": 7
+                  },
+                  "ODDFRM": {
+                    "description": "Odd frame",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CDIS": {
+                    "description": "Channel disable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Channel enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH0INTF": {
+              "description": "host channel-0 interrupt register\n          (USBFS_HCHxINTF)",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBER": {
+                    "description": "USB bus error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBER": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVR": {
+                    "description": "Request queue overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTER": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH1INTF": {
+              "description": "host channel-1 interrupt register\n          (HCH1INTF)",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBER": {
+                    "description": "USB bus error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBER": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVR": {
+                    "description": "Request queue overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTER": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH2INTF": {
+              "description": "host channel-2 interrupt register\n          (HCH2INTF)",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBER": {
+                    "description": "USB bus error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBER": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVR": {
+                    "description": "Request queue overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTER": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH3INTF": {
+              "description": "host channel-3 interrupt register\n          (HCH3INTF)",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBER": {
+                    "description": "USB bus error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBER": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVR": {
+                    "description": "Request queue overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTER": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH4INTF": {
+              "description": "host channel-4 interrupt register\n          (HCH4INTF)",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBER": {
+                    "description": "USB bus error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBER": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVR": {
+                    "description": "Request queue overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTER": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH5INTF": {
+              "description": "host channel-5 interrupt register\n          (HCH5INTF)",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBER": {
+                    "description": "USB bus error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBER": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVR": {
+                    "description": "Request queue overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTER": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH6INTF": {
+              "description": "host channel-6 interrupt register\n          (HCH6INTF)",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBER": {
+                    "description": "USB bus error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBER": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVR": {
+                    "description": "Request queue overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTER": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH7INTF": {
+              "description": "host channel-7 interrupt register\n          (HCH7INTF)",
+              "offset": 488,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TF": {
+                    "description": "Transfer finished",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CH": {
+                    "description": "Channel halted",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "STALL response received\n              interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAK": {
+                    "description": "NAK response received\n              interrupt",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACK": {
+                    "description": "ACK response received/transmitted\n              interrupt",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBER": {
+                    "description": "USB bus error",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBER": {
+                    "description": "Babble error",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVR": {
+                    "description": "Request queue overrun",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTER": {
+                    "description": "Data toggle error",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH0INTEN": {
+              "description": "host channel-0 interrupt enable register\n          (HCH0INTEN)",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TFIE": {
+                    "description": "Transfer completed interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHIE": {
+                    "description": "Channel halted interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLIE": {
+                    "description": "STALL interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKIE": {
+                    "description": "NAK interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKIE": {
+                    "description": "ACK interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBERIE": {
+                    "description": "USB bus error interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERIE": {
+                    "description": "Babble error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVRIE": {
+                    "description": "request queue overrun interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERIE": {
+                    "description": "Data toggle error interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH1INTEN": {
+              "description": "host channel-1 interrupt enable register\n          (HCH1INTEN)",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TFIE": {
+                    "description": "Transfer completed interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHIE": {
+                    "description": "Channel halted interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLIE": {
+                    "description": "STALL interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKIE": {
+                    "description": "NAK interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKIE": {
+                    "description": "ACK interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBERIE": {
+                    "description": "USB bus error interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERIE": {
+                    "description": "Babble error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVRIE": {
+                    "description": "request queue overrun interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERIE": {
+                    "description": "Data toggle error interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH2INTEN": {
+              "description": "host channel-2 interrupt enable register\n          (HCH2INTEN)",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TFIE": {
+                    "description": "Transfer completed interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHIE": {
+                    "description": "Channel halted interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLIE": {
+                    "description": "STALL interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKIE": {
+                    "description": "NAK interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKIE": {
+                    "description": "ACK interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBERIE": {
+                    "description": "USB bus error interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERIE": {
+                    "description": "Babble error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVRIE": {
+                    "description": "request queue overrun interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERIE": {
+                    "description": "Data toggle error interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH3INTEN": {
+              "description": "host channel-3 interrupt enable register\n          (HCH3INTEN)",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TFIE": {
+                    "description": "Transfer completed interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHIE": {
+                    "description": "Channel halted interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLIE": {
+                    "description": "STALL interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKIE": {
+                    "description": "NAK interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKIE": {
+                    "description": "ACK interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBERIE": {
+                    "description": "USB bus error interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERIE": {
+                    "description": "Babble error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVRIE": {
+                    "description": "request queue overrun interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERIE": {
+                    "description": "Data toggle error interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH4INTEN": {
+              "description": "host channel-4 interrupt enable register\n          (HCH4INTEN)",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TFIE": {
+                    "description": "Transfer completed interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHIE": {
+                    "description": "Channel halted interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLIE": {
+                    "description": "STALL interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKIE": {
+                    "description": "NAK interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKIE": {
+                    "description": "ACK interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBERIE": {
+                    "description": "USB bus error interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERIE": {
+                    "description": "Babble error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVRIE": {
+                    "description": "request queue overrun interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERIE": {
+                    "description": "Data toggle error interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH5INTEN": {
+              "description": "host channel-5 interrupt enable register\n          (HCH5INTEN)",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TFIE": {
+                    "description": "Transfer completed interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHIE": {
+                    "description": "Channel halted interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLIE": {
+                    "description": "STALL interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKIE": {
+                    "description": "NAK interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKIE": {
+                    "description": "ACK interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBERIE": {
+                    "description": "USB bus error interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERIE": {
+                    "description": "Babble error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVRIE": {
+                    "description": "request queue overrun interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERIE": {
+                    "description": "Data toggle error interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH6INTEN": {
+              "description": "host channel-6 interrupt enable register\n          (HCH6INTEN)",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TFIE": {
+                    "description": "Transfer completed interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHIE": {
+                    "description": "Channel halted interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLIE": {
+                    "description": "STALL interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKIE": {
+                    "description": "NAK interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKIE": {
+                    "description": "ACK interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBERIE": {
+                    "description": "USB bus error interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERIE": {
+                    "description": "Babble error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVRIE": {
+                    "description": "request queue overrun interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERIE": {
+                    "description": "Data toggle error interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH7INTEN": {
+              "description": "host channel-7 interrupt enable register\n          (HCH7INTEN)",
+              "offset": 492,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TFIE": {
+                    "description": "Transfer completed interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CHIE": {
+                    "description": "Channel halted interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "STALLIE": {
+                    "description": "STALL interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NAKIE": {
+                    "description": "NAK interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ACKIE": {
+                    "description": "ACK interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "USBERIE": {
+                    "description": "USB bus error interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBERIE": {
+                    "description": "Babble error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REQOVRIE": {
+                    "description": "request queue overrun interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DTERIE": {
+                    "description": "Data toggle error interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "HCH0LEN": {
+              "description": "host channel-0 transfer length\n          register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "HCH1LEN": {
+              "description": "host channel-1 transfer length\n          register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "HCH2LEN": {
+              "description": " host channel-2 transfer length\n          register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "HCH3LEN": {
+              "description": " host channel-3 transfer length\n          register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "HCH4LEN": {
+              "description": "host channel-4 transfer length\n          register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "HCH5LEN": {
+              "description": "host channel-5 transfer length\n          register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "HCH6LEN": {
+              "description": "host channel-6 transfer length\n          register",
+              "offset": 464,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "HCH7LEN": {
+              "description": "host channel-7 transfer length\n          register",
+              "offset": 496,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TLEN": {
+                    "description": "Transfer length",
+                    "offset": 0,
+                    "size": 19
+                  },
+                  "PCNT": {
+                    "description": "Packet count",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 29,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USBFS_GLOBAL": {
+        "description": "USB full speed global registers",
+        "children": {
+          "registers": {
+            "GOTGCS": {
+              "description": "Global OTG control and status register \n          (USBFS_GOTGCS)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRPS": {
+                    "description": "SRP success",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SRPREQ": {
+                    "description": "SRP request",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HNPS": {
+                    "description": "Host success",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HNPREQ": {
+                    "description": "HNP request",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HHNPEN": {
+                    "description": "Host HNP enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DHNPEN": {
+                    "description": "Device HNP enabled",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IDPS": {
+                    "description": "ID pin status",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DI": {
+                    "description": "Debounce interval",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ASV": {
+                    "description": "A-session valid",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BSV": {
+                    "description": "B-session valid",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GOTGINTF": {
+              "description": "Global OTG interrupt flag register\n          (USBFS_GOTGINTF)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SESEND": {
+                    "description": "Session end ",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SRPEND": {
+                    "description": "Session request success status\n              change",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNPEND": {
+                    "description": "HNP end",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "HNPDET": {
+                    "description": "Host negotiation request detected",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "ADTO": {
+                    "description": "A-device timeout",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DF": {
+                    "description": "Debounce finish",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GAHBCS": {
+              "description": "Global AHB control and status register\n          (USBFS_GAHBCS)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GINTEN": {
+                    "description": "Global interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXFTH": {
+                    "description": "Tx FIFO threshold",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PTXFTH": {
+                    "description": "Periodic Tx FIFO threshold",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GUSBCS": {
+              "description": "Global USB control and status register\n          (USBFS_GUSBCSR)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 2688,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TOC": {
+                    "description": "Timeout calibration",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "SRPCEN": {
+                    "description": "SRP capability enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "HNPCEN": {
+                    "description": "HNP capability enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UTT": {
+                    "description": "USB turnaround time",
+                    "offset": 10,
+                    "size": 4
+                  },
+                  "FHM": {
+                    "description": "Force host mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FDM": {
+                    "description": "Force device mode",
+                    "offset": 30,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GRSTCTL": {
+              "description": "Global reset control register (USBFS_GRSTCTL)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 2147483648,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSRST": {
+                    "description": "Core soft reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "HCSRST": {
+                    "description": "HCLK soft reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HFCRST": {
+                    "description": "Host frame counter reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RXFF": {
+                    "description": "RxFIFO flush",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TXFF": {
+                    "description": "TxFIFO flush",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TXFNUM": {
+                    "description": "TxFIFO number",
+                    "offset": 6,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "GINTF": {
+              "description": "Global interrupt flag register (USBFS_GINTF)",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 67108897,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COPM": {
+                    "description": "Current operation mode",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MFIF": {
+                    "description": "Mode fault interrupt flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGIF": {
+                    "description": "OTG interrupt flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOF": {
+                    "description": "Start of frame",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFNEIF": {
+                    "description": "RxFIFO non-empty interrupt flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NPTXFEIF": {
+                    "description": "Non-periodic TxFIFO empty interrupt flag",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GNPINAK": {
+                    "description": "Global Non-Periodic IN NAK effective",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GONAK": {
+                    "description": "Global OUT NAK effective",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ESP": {
+                    "description": "Early suspend",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SP": {
+                    "description": "USB suspend",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RST": {
+                    "description": "USB reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMF": {
+                    "description": "Enumeration finished",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOOPDIF": {
+                    "description": "Isochronous OUT packet dropped\n              interrupt",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPFIF": {
+                    "description": "End of periodic frame\n              interrupt flag",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IEPIF": {
+                    "description": "IN endpoint interrupt flag",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEPIF": {
+                    "description": "OUT endpoint interrupt flag",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ISOINCIF": {
+                    "description": "Isochronous IN transfer Not Complete Interrupt Flag",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PXNCIF_ISOONCIF": {
+                    "description": "periodic transfer not complete interrupt flag(Host\n              mode)/isochronous OUT transfer not complete interrupt flag(Device\n              mode)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HPIF": {
+                    "description": "Host port interrupt flag",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCIF": {
+                    "description": "Host channels interrupt flag",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PTXFEIF": {
+                    "description": "Periodic TxFIFO empty interrupt flag",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IDPSC": {
+                    "description": "ID pin status change",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCIF": {
+                    "description": "Disconnect interrupt flag",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SESIF": {
+                    "description": "Session interrupt flag",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WKUPIF": {
+                    "description": "Wakeup interrupt flag",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GINTEN": {
+              "description": "Global interrupt enable register\n          (USBFS_GINTEN)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MFIE": {
+                    "description": "Mode fault interrupt\n              enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OTGIE": {
+                    "description": "OTG interrupt enable ",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SOFIE": {
+                    "description": "Start of frame interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFNEIE": {
+                    "description": "Receive FIFO non-empty\n              interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "NPTXFEIE": {
+                    "description": "Non-periodic TxFIFO empty\n              interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GNPINAKIE": {
+                    "description": "Global non-periodic IN NAK effective interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GONAKIE": {
+                    "description": "Global OUT NAK effective\n              interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ESPIE": {
+                    "description": "Early suspend interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SPIE": {
+                    "description": "USB suspend interrupt enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RSTIE": {
+                    "description": "USB reset interrupt enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENUMFIE": {
+                    "description": "Enumeration finish interrupt enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISOOPDIE": {
+                    "description": "Isochronous OUT packet dropped interrupt enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EOPFIE": {
+                    "description": "End of periodic frame interrupt enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IEPIE": {
+                    "description": "IN endpoints interrupt enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OEPIE": {
+                    "description": "OUT endpoints interrupt enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ISOINCIE": {
+                    "description": "isochronous IN transfer not complete\n              interrupt enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PXNCIE_ISOONCIE": {
+                    "description": "periodic transfer not compelete Interrupt enable(Host\n              mode)/isochronous OUT transfer not complete interrupt enable(Device\n              mode)",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "HPIE": {
+                    "description": "Host port interrupt enable",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HCIE": {
+                    "description": "Host channels interrupt enable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PTXFEIE": {
+                    "description": "Periodic TxFIFO empty interrupt enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "IDPSCIE": {
+                    "description": "ID pin status change interrupt enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DISCIE": {
+                    "description": "Disconnect interrupt enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SESIE": {
+                    "description": "Session interrupt enable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WKUPIE": {
+                    "description": "Wakeup interrupt enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GRSTATR_Device": {
+              "description": "Global Receive status read(Device\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCOUNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "RPCKST": {
+                    "description": "Recieve packet status",
+                    "offset": 17,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "GRSTATR_Host": {
+              "description": "Global Receive status read(Host\n          mode)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CNUM": {
+                    "description": "Channel number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCOUNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "RPCKST": {
+                    "description": "Reivece packet status",
+                    "offset": 17,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "GRSTATP_Device": {
+              "description": "Global Receive status pop(Device\n          mode)",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "EPNUM": {
+                    "description": "Endpoint number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCOUNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "RPCKST": {
+                    "description": "Recieve packet status",
+                    "offset": 17,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "GRSTATP_Host": {
+              "description": "Global Receive status pop(Host\n          mode)",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "CNUM": {
+                    "description": "Channel number",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "BCOUNT": {
+                    "description": "Byte count",
+                    "offset": 4,
+                    "size": 11
+                  },
+                  "DPID": {
+                    "description": "Data PID",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "RPCKST": {
+                    "description": "Reivece packet status",
+                    "offset": 17,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "GRFLEN": {
+              "description": "Global Receive FIFO size register\n          (USBFS_GRFLEN)",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFD": {
+                    "description": "Rx FIFO depth",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "HNPTFLEN": {
+              "description": "Host non-periodic transmit FIFO length register\n          (Host mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 33554944,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HNPTXRSAR": {
+                    "description": "host non-periodic transmit Tx RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "HNPTXFD": {
+                    "description": "host non-periodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DIEP0TFLEN": {
+              "description": "Device IN endpoint 0 transmit FIFO length\n          (Device mode)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 33554944,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEP0TXFD": {
+                    "description": "in endpoint 0 Tx FIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "IEP0TXRSAR": {
+                    "description": "in endpoint 0 Tx RAM start address",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "HNPTFQSTAT": {
+              "description": "Host non-periodic transmit FIFO/queue\n          status register (HNPTFQSTAT)",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 524800,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "NPTXFS": {
+                    "description": "Non-periodic TxFIFO space",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "NPTXRQS": {
+                    "description": "Non-periodic transmit request queue\n              space ",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "NPTXRQTOP": {
+                    "description": "Top of the non-periodic transmit request\n              queue",
+                    "offset": 24,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "GCCFG": {
+              "description": "Global core configuration register (USBFS_GCCFG)",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWRON": {
+                    "description": "Power on",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "VBUSACEN": {
+                    "description": "The VBUS A-device Comparer enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "VBUSBCEN": {
+                    "description": "The VBUS B-device Comparer enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SOFOEN": {
+                    "description": "SOF output enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "VBUSIG": {
+                    "description": "VBUS ignored",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CID": {
+              "description": "core ID register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 4096,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CID": {
+                    "description": "Core ID",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HPTFLEN": {
+              "description": "Host periodic transmit FIFO length register (HPTFLEN)",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 33555968,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPTXFSAR": {
+                    "description": "Host periodic TxFIFO start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "HPTXFD": {
+                    "description": "Host periodic TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DIEP1TFLEN": {
+              "description": "device IN endpoint transmit FIFO size\n          register (DIEP1TFLEN)",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEPTXRSAR": {
+                    "description": "IN endpoint FIFO transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "IEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DIEP2TFLEN": {
+              "description": "device IN endpoint transmit FIFO size\n          register (DIEP2TFLEN)",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEPTXRSAR": {
+                    "description": "IN endpoint FIFO transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "IEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DIEP3TFLEN": {
+              "description": "device IN endpoint transmit FIFO size\n          register (FS_DIEP3TXFLEN)",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 33555456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IEPTXRSAR": {
+                    "description": "IN endpoint FIFO4 transmit RAM start\n              address",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "IEPTXFD": {
+                    "description": "IN endpoint TxFIFO depth",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2C0": {
+        "description": "Inter integrated circuit",
+        "children": {
+          "registers": {
+            "CTL0": {
+              "description": "Control register 0",
+              "offset": 0,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SRESET": {
+                    "description": "Software reset",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SALT": {
+                    "description": "SMBus alert",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PECTRANS": {
+                    "description": "PEC Transfer",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "POAP": {
+                    "description": "Position of ACK and PEC when receiving",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ACKEN": {
+                    "description": "Whether or not to send an ACK",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "STOP": {
+                    "description": "Generate a STOP condition on I2C bus",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "START": {
+                    "description": "Generate a START condition on I2C bus",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SS": {
+                    "description": "Whether to stretch SCL low when data is not ready in slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GCEN": {
+                    "description": "Whether or not to response to a General Call (0x00)",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PECEN": {
+                    "description": "PEC Calculation Switch",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ARPEN": {
+                    "description": "ARP protocol in SMBus switch",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SMBSEL": {
+                    "description": "SMBusType Selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SMBEN": {
+                    "description": "SMBus/I2C mode switch",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "I2CEN": {
+                    "description": "I2C peripheral enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTL1": {
+              "description": "Control register 1",
+              "offset": 4,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMALST": {
+                    "description": "Flag indicating DMA last transfer",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DMAON": {
+                    "description": "DMA mode switch",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BUFIE": {
+                    "description": "Buffer interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EVIE": {
+                    "description": "Event interrupt enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "I2CCLK": {
+                    "description": "I2C Peripheral clock frequency",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "SADDR0": {
+              "description": "Slave address register 0",
+              "offset": 8,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDFORMAT": {
+                    "description": "Address mode for the I2C slave",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "ADDRESS9_8": {
+                    "description": "Highest two bits of a 10-bit address",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ADDRESS7_1": {
+                    "description": "7-bit address or bits 7:1 of a 10-bit address",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "ADDRESS0": {
+                    "description": "Bit 0 of a 10-bit address",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SADDR1": {
+              "description": "Slave address register 1",
+              "offset": 12,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADDRESS2": {
+                    "description": "Second I2C address for the slave in Dual-Address mode",
+                    "offset": 1,
+                    "size": 7
+                  },
+                  "DUADEN": {
+                    "description": "Dual-Address mode switch",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATA": {
+              "description": "Transfer buffer register",
+              "offset": 16,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRB": {
+                    "description": "Transmission or reception data buffer register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "STAT0": {
+              "description": "Transfer status register 0",
+              "offset": 20,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SMBALT": {
+                    "description": "SMBus Alert status",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SMBTO": {
+                    "description": "Timeout signal in SMBus mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PECERR": {
+                    "description": "PEC error when receiving data",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OUERR": {
+                    "description": "Over-run or under-run situation occurs in slave mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AERR": {
+                    "description": "Acknowledge error",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LOSTARB": {
+                    "description": "Arbitration Lost in master mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BERR": {
+                    "description": "A bus error occurs indication a unexpected START or STOP condition on I2C bus",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TBE": {
+                    "description": "I2C_DATA is Empty during transmitting",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RBNE": {
+                    "description": "I2C_DATA is not Empty during receiving",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STPDET": {
+                    "description": "STOP condition detected in slave mode",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ADD10SEND": {
+                    "description": "Header of 10-bit address is sent in master mode",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BTC": {
+                    "description": "Byte transmission completed",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ADDSEND": {
+                    "description": "Address is sent in master mode or received and matches in slave mode",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SBSEND": {
+                    "description": "START condition sent out in master mode",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "STAT1": {
+              "description": "Transfer status register 1",
+              "offset": 24,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "PECV": {
+                    "description": "Packet Error Checking Value that calculated by hardware when PEC is enabled",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "DUMODF": {
+                    "description": "Dual Flag in slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "HSTSMB": {
+                    "description": "SMBus Host Header detected in slave mode",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DEFSMB": {
+                    "description": "Default address of SMBusDevice",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RXGC": {
+                    "description": "General call address (00h) received",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TR": {
+                    "description": "Whether the I2C is a transmitter or a receiver",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "I2CBSY": {
+                    "description": "Busy flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MASTER": {
+                    "description": "A flag indicating whether I2C block is in master or slave mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CKCFG": {
+              "description": "Clock configure register",
+              "offset": 28,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FAST": {
+                    "description": "I2C speed selection in master mode",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "DTCY": {
+                    "description": "Duty cycle in fast mode",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CLKC": {
+                    "description": "I2C Clock control in master mode",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "RT": {
+              "description": "Rise time register",
+              "offset": 32,
+              "size": 16,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RISETIME": {
+                    "description": "Maximum rise time in master mode",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIMER5": {
+        "description": "Basic-timers",
+        "children": {
+          "registers": {
+            "CTL0": {
+              "description": "control register 0",
+              "offset": 0,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARSE": {
+                    "description": "Auto-reload shadow enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SPM": {
+                    "description": "Single pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "UPS": {
+                    "description": "Update source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UPDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTL1": {
+              "description": "control register 1",
+              "offset": 4,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MMC": {
+                    "description": "Master mode control",
+                    "offset": 4,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DMAINTEN": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UPDEN": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "UPIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTF": {
+              "description": "Interrupt flag register",
+              "offset": 16,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UPIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWEVG": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "UPG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "Counter register",
+              "offset": 36,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "Low counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "Prescaler register",
+              "offset": 40,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value of the counter clock",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CAR": {
+              "description": "Counter auto reload register",
+              "offset": 44,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CARL": {
+                    "description": "Counter auto reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ECLIC": {
+        "description": "Enhanced Core Local Interrupt Controller",
+        "children": {
+          "registers": {
+            "CLICCFG": {
+              "description": "cliccfg Register",
+              "offset": 0,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NLBITS": {
+                    "description": "NLBITS",
+                    "offset": 1,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CLICINFO": {
+              "description": "clicinfo Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "NUM_INTERRUPT": {
+                    "description": "NUM_INTERRUPT",
+                    "offset": 0,
+                    "size": 13
+                  },
+                  "VERSION": {
+                    "description": "VERSION",
+                    "offset": 13,
+                    "size": 8
+                  },
+                  "CLICINTCTLBITS": {
+                    "description": "CLICINTCTLBITS",
+                    "offset": 21,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MTH": {
+              "description": "MTH Register",
+              "offset": 11,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MTH": {
+                    "description": "MTH",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTIP_0": {
+              "description": "clicintip  Register",
+              "offset": 4096,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_1": {
+              "description": "clicintip  Register",
+              "offset": 4100,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_2": {
+              "description": "clicintip  Register",
+              "offset": 4104,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_3": {
+              "description": "clicintip  Register",
+              "offset": 4108,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_4": {
+              "description": "clicintip  Register",
+              "offset": 4112,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_5": {
+              "description": "clicintip  Register",
+              "offset": 4116,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_6": {
+              "description": "clicintip  Register",
+              "offset": 4120,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_7": {
+              "description": "clicintip  Register",
+              "offset": 4124,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_8": {
+              "description": "clicintip  Register",
+              "offset": 4128,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_9": {
+              "description": "clicintip  Register",
+              "offset": 4132,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_10": {
+              "description": "clicintip  Register",
+              "offset": 4136,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_11": {
+              "description": "clicintip  Register",
+              "offset": 4140,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_12": {
+              "description": "clicintip  Register",
+              "offset": 4144,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_13": {
+              "description": "clicintip  Register",
+              "offset": 4148,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_14": {
+              "description": "clicintip  Register",
+              "offset": 4152,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_15": {
+              "description": "clicintip  Register",
+              "offset": 4156,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_16": {
+              "description": "clicintip  Register",
+              "offset": 4160,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_17": {
+              "description": "clicintip  Register",
+              "offset": 4164,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_18": {
+              "description": "clicintip  Register",
+              "offset": 4168,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_19": {
+              "description": "clicintip  Register",
+              "offset": 4172,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_20": {
+              "description": "clicintip  Register",
+              "offset": 4176,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_21": {
+              "description": "clicintip  Register",
+              "offset": 4180,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_22": {
+              "description": "clicintip  Register",
+              "offset": 4184,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_23": {
+              "description": "clicintip  Register",
+              "offset": 4188,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_24": {
+              "description": "clicintip  Register",
+              "offset": 4192,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_25": {
+              "description": "clicintip  Register",
+              "offset": 4196,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_26": {
+              "description": "clicintip  Register",
+              "offset": 4200,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_27": {
+              "description": "clicintip  Register",
+              "offset": 4204,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_28": {
+              "description": "clicintip  Register",
+              "offset": 4208,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_29": {
+              "description": "clicintip  Register",
+              "offset": 4212,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_30": {
+              "description": "clicintip  Register",
+              "offset": 4216,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_31": {
+              "description": "clicintip  Register",
+              "offset": 4220,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_32": {
+              "description": "clicintip  Register",
+              "offset": 4224,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_33": {
+              "description": "clicintip  Register",
+              "offset": 4228,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_34": {
+              "description": "clicintip  Register",
+              "offset": 4232,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_35": {
+              "description": "clicintip  Register",
+              "offset": 4236,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_36": {
+              "description": "clicintip  Register",
+              "offset": 4240,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_37": {
+              "description": "clicintip  Register",
+              "offset": 4244,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_38": {
+              "description": "clicintip  Register",
+              "offset": 4248,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_39": {
+              "description": "clicintip  Register",
+              "offset": 4252,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_40": {
+              "description": "clicintip  Register",
+              "offset": 4256,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_41": {
+              "description": "clicintip  Register",
+              "offset": 4260,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_42": {
+              "description": "clicintip  Register",
+              "offset": 4264,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_43": {
+              "description": "clicintip  Register",
+              "offset": 4268,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_44": {
+              "description": "clicintip  Register",
+              "offset": 4272,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_45": {
+              "description": "clicintip  Register",
+              "offset": 4276,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_46": {
+              "description": "clicintip  Register",
+              "offset": 4280,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_47": {
+              "description": "clicintip  Register",
+              "offset": 4284,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_48": {
+              "description": "clicintip  Register",
+              "offset": 4288,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_49": {
+              "description": "clicintip  Register",
+              "offset": 4292,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_50": {
+              "description": "clicintip  Register",
+              "offset": 4296,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_51": {
+              "description": "clicintip  Register",
+              "offset": 4300,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_52": {
+              "description": "clicintip  Register",
+              "offset": 4304,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_53": {
+              "description": "clicintip  Register",
+              "offset": 4308,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_54": {
+              "description": "clicintip  Register",
+              "offset": 4312,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_55": {
+              "description": "clicintip  Register",
+              "offset": 4316,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_56": {
+              "description": "clicintip  Register",
+              "offset": 4320,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_57": {
+              "description": "clicintip  Register",
+              "offset": 4324,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_58": {
+              "description": "clicintip  Register",
+              "offset": 4328,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_59": {
+              "description": "clicintip  Register",
+              "offset": 4332,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_60": {
+              "description": "clicintip  Register",
+              "offset": 4336,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_61": {
+              "description": "clicintip  Register",
+              "offset": 4340,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_62": {
+              "description": "clicintip  Register",
+              "offset": 4344,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_63": {
+              "description": "clicintip  Register",
+              "offset": 4348,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_64": {
+              "description": "clicintip  Register",
+              "offset": 4352,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_65": {
+              "description": "clicintip  Register",
+              "offset": 4356,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_66": {
+              "description": "clicintip  Register",
+              "offset": 4360,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_67": {
+              "description": "clicintip  Register",
+              "offset": 4364,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_68": {
+              "description": "clicintip  Register",
+              "offset": 4368,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_69": {
+              "description": "clicintip  Register",
+              "offset": 4372,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_70": {
+              "description": "clicintip  Register",
+              "offset": 4376,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_71": {
+              "description": "clicintip  Register",
+              "offset": 4380,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_72": {
+              "description": "clicintip  Register",
+              "offset": 4384,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_73": {
+              "description": "clicintip  Register",
+              "offset": 4388,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_74": {
+              "description": "clicintip  Register",
+              "offset": 4392,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_75": {
+              "description": "clicintip  Register",
+              "offset": 4396,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_76": {
+              "description": "clicintip  Register",
+              "offset": 4400,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_77": {
+              "description": "clicintip  Register",
+              "offset": 4404,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_78": {
+              "description": "clicintip  Register",
+              "offset": 4408,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_79": {
+              "description": "clicintip  Register",
+              "offset": 4412,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_80": {
+              "description": "clicintip  Register",
+              "offset": 4416,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_81": {
+              "description": "clicintip  Register",
+              "offset": 4420,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_82": {
+              "description": "clicintip  Register",
+              "offset": 4424,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_83": {
+              "description": "clicintip  Register",
+              "offset": 4428,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_84": {
+              "description": "clicintip  Register",
+              "offset": 4432,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_85": {
+              "description": "clicintip  Register",
+              "offset": 4440,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIP_86": {
+              "description": "clicintip  Register",
+              "offset": 4444,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IP": {
+                    "description": "IP",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_0": {
+              "description": "clicintie Register",
+              "offset": 4097,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_1": {
+              "description": "clicintie Register",
+              "offset": 4101,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_2": {
+              "description": "clicintie Register",
+              "offset": 4105,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_3": {
+              "description": "clicintie Register",
+              "offset": 4109,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_4": {
+              "description": "clicintie Register",
+              "offset": 4113,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_5": {
+              "description": "clicintie Register",
+              "offset": 4117,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_6": {
+              "description": "clicintie Register",
+              "offset": 4121,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_7": {
+              "description": "clicintie Register",
+              "offset": 4125,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_8": {
+              "description": "clicintie Register",
+              "offset": 4129,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_9": {
+              "description": "clicintie Register",
+              "offset": 4133,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_10": {
+              "description": "clicintie Register",
+              "offset": 4137,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_11": {
+              "description": "clicintie Register",
+              "offset": 4141,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_12": {
+              "description": "clicintie Register",
+              "offset": 4145,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_13": {
+              "description": "clicintie Register",
+              "offset": 4149,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_14": {
+              "description": "clicintie Register",
+              "offset": 4153,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_15": {
+              "description": "clicintie Register",
+              "offset": 4157,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_16": {
+              "description": "clicintie Register",
+              "offset": 4161,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_17": {
+              "description": "clicintie Register",
+              "offset": 4165,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_18": {
+              "description": "clicintie Register",
+              "offset": 4169,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_19": {
+              "description": "clicintie Register",
+              "offset": 4173,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_20": {
+              "description": "clicintie Register",
+              "offset": 4177,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_21": {
+              "description": "clicintie Register",
+              "offset": 4181,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_22": {
+              "description": "clicintie Register",
+              "offset": 4185,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_23": {
+              "description": "clicintie Register",
+              "offset": 4189,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_24": {
+              "description": "clicintie Register",
+              "offset": 4193,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_25": {
+              "description": "clicintie Register",
+              "offset": 4197,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_26": {
+              "description": "clicintie Register",
+              "offset": 4201,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_27": {
+              "description": "clicintie Register",
+              "offset": 4205,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_28": {
+              "description": "clicintie Register",
+              "offset": 4209,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_29": {
+              "description": "clicintie Register",
+              "offset": 4213,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_30": {
+              "description": "clicintie Register",
+              "offset": 4217,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_31": {
+              "description": "clicintie Register",
+              "offset": 4221,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_32": {
+              "description": "clicintie Register",
+              "offset": 4225,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_33": {
+              "description": "clicintie Register",
+              "offset": 4229,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_34": {
+              "description": "clicintie Register",
+              "offset": 4233,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_35": {
+              "description": "clicintie Register",
+              "offset": 4237,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_36": {
+              "description": "clicintie Register",
+              "offset": 4241,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_37": {
+              "description": "clicintie Register",
+              "offset": 4245,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_38": {
+              "description": "clicintie Register",
+              "offset": 4249,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_39": {
+              "description": "clicintie Register",
+              "offset": 4253,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_40": {
+              "description": "clicintie Register",
+              "offset": 4257,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_41": {
+              "description": "clicintie Register",
+              "offset": 4261,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_42": {
+              "description": "clicintie Register",
+              "offset": 4265,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_43": {
+              "description": "clicintie Register",
+              "offset": 4269,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_44": {
+              "description": "clicintie Register",
+              "offset": 4273,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_45": {
+              "description": "clicintie Register",
+              "offset": 4277,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_46": {
+              "description": "clicintie Register",
+              "offset": 4281,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_47": {
+              "description": "clicintie Register",
+              "offset": 4285,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_48": {
+              "description": "clicintie Register",
+              "offset": 4289,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_49": {
+              "description": "clicintie Register",
+              "offset": 4293,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_50": {
+              "description": "clicintie Register",
+              "offset": 4297,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_51": {
+              "description": "clicintie Register",
+              "offset": 4301,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_52": {
+              "description": "clicintie Register",
+              "offset": 4305,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_53": {
+              "description": "clicintie Register",
+              "offset": 4309,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_54": {
+              "description": "clicintie Register",
+              "offset": 4313,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_55": {
+              "description": "clicintie Register",
+              "offset": 4317,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_56": {
+              "description": "clicintie Register",
+              "offset": 4321,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_57": {
+              "description": "clicintie Register",
+              "offset": 4325,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_58": {
+              "description": "clicintie Register",
+              "offset": 4329,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_59": {
+              "description": "clicintie Register",
+              "offset": 4333,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_60": {
+              "description": "clicintie Register",
+              "offset": 4337,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_61": {
+              "description": "clicintie Register",
+              "offset": 4341,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_62": {
+              "description": "clicintie Register",
+              "offset": 4345,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_63": {
+              "description": "clicintie Register",
+              "offset": 4349,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_64": {
+              "description": "clicintie Register",
+              "offset": 4353,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_65": {
+              "description": "clicintie Register",
+              "offset": 4357,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_66": {
+              "description": "clicintie Register",
+              "offset": 4361,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_67": {
+              "description": "clicintie Register",
+              "offset": 4365,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_68": {
+              "description": "clicintie Register",
+              "offset": 4369,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_69": {
+              "description": "clicintie Register",
+              "offset": 4373,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_70": {
+              "description": "clicintie Register",
+              "offset": 4377,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_71": {
+              "description": "clicintie Register",
+              "offset": 4381,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_72": {
+              "description": "clicintie Register",
+              "offset": 4385,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_73": {
+              "description": "clicintie Register",
+              "offset": 4389,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_74": {
+              "description": "clicintie Register",
+              "offset": 4393,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_75": {
+              "description": "clicintie Register",
+              "offset": 4397,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_76": {
+              "description": "clicintie Register",
+              "offset": 4401,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_77": {
+              "description": "clicintie Register",
+              "offset": 4405,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_78": {
+              "description": "clicintie Register",
+              "offset": 4409,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_79": {
+              "description": "clicintie Register",
+              "offset": 4413,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_80": {
+              "description": "clicintie Register",
+              "offset": 4417,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_81": {
+              "description": "clicintie Register",
+              "offset": 4421,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_82": {
+              "description": "clicintie Register",
+              "offset": 4425,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_83": {
+              "description": "clicintie Register",
+              "offset": 4429,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_84": {
+              "description": "clicintie Register",
+              "offset": 4433,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_85": {
+              "description": "clicintie Register",
+              "offset": 4437,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTIE_86": {
+              "description": "clicintie Register",
+              "offset": 4441,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IE": {
+                    "description": "IE",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_0": {
+              "description": "clicintattr Register",
+              "offset": 4098,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_1": {
+              "description": "clicintattr Register",
+              "offset": 4102,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_2": {
+              "description": "clicintattr Register",
+              "offset": 4106,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_3": {
+              "description": "clicintattr Register",
+              "offset": 4110,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_4": {
+              "description": "clicintattr Register",
+              "offset": 4114,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_5": {
+              "description": "clicintattr Register",
+              "offset": 4118,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_6": {
+              "description": "clicintattr Register",
+              "offset": 4122,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_7": {
+              "description": "clicintattr Register",
+              "offset": 4126,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_8": {
+              "description": "clicintattr Register",
+              "offset": 4130,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_9": {
+              "description": "clicintattr Register",
+              "offset": 4134,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_10": {
+              "description": "clicintattr Register",
+              "offset": 4138,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_11": {
+              "description": "clicintattr Register",
+              "offset": 4142,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_12": {
+              "description": "clicintattr Register",
+              "offset": 4146,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_13": {
+              "description": "clicintattr Register",
+              "offset": 4150,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_14": {
+              "description": "clicintattr Register",
+              "offset": 4154,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_15": {
+              "description": "clicintattr Register",
+              "offset": 4158,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_16": {
+              "description": "clicintattr Register",
+              "offset": 4162,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_17": {
+              "description": "clicintattr Register",
+              "offset": 4166,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_18": {
+              "description": "clicintattr Register",
+              "offset": 4170,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_19": {
+              "description": "clicintattr Register",
+              "offset": 4174,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_20": {
+              "description": "clicintattr Register",
+              "offset": 4178,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_21": {
+              "description": "clicintattr Register",
+              "offset": 4182,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_22": {
+              "description": "clicintattr Register",
+              "offset": 4186,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_23": {
+              "description": "clicintattr Register",
+              "offset": 4190,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_24": {
+              "description": "clicintattr Register",
+              "offset": 4194,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_25": {
+              "description": "clicintattr Register",
+              "offset": 4198,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_26": {
+              "description": "clicintattr Register",
+              "offset": 4202,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_27": {
+              "description": "clicintattr Register",
+              "offset": 4206,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_28": {
+              "description": "clicintattr Register",
+              "offset": 4210,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_29": {
+              "description": "clicintattr Register",
+              "offset": 4214,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_30": {
+              "description": "clicintattr Register",
+              "offset": 4218,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_31": {
+              "description": "clicintattr Register",
+              "offset": 4222,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_32": {
+              "description": "clicintattr Register",
+              "offset": 4226,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_33": {
+              "description": "clicintattr Register",
+              "offset": 4230,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_34": {
+              "description": "clicintattr Register",
+              "offset": 4234,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_35": {
+              "description": "clicintattr Register",
+              "offset": 4238,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_36": {
+              "description": "clicintattr Register",
+              "offset": 4242,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_37": {
+              "description": "clicintattr Register",
+              "offset": 4246,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_38": {
+              "description": "clicintattr Register",
+              "offset": 4250,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_39": {
+              "description": "clicintattr Register",
+              "offset": 4254,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_40": {
+              "description": "clicintattr Register",
+              "offset": 4258,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_41": {
+              "description": "clicintattr Register",
+              "offset": 4262,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_42": {
+              "description": "clicintattr Register",
+              "offset": 4266,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_43": {
+              "description": "clicintattr Register",
+              "offset": 4270,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_44": {
+              "description": "clicintattr Register",
+              "offset": 4274,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_45": {
+              "description": "clicintattr Register",
+              "offset": 4278,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_46": {
+              "description": "clicintattr Register",
+              "offset": 4282,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_47": {
+              "description": "clicintattr Register",
+              "offset": 4286,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_48": {
+              "description": "clicintattr Register",
+              "offset": 4290,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_49": {
+              "description": "clicintattr Register",
+              "offset": 4294,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_50": {
+              "description": "clicintattr Register",
+              "offset": 4298,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_51": {
+              "description": "clicintattr Register",
+              "offset": 4302,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_52": {
+              "description": "clicintattr Register",
+              "offset": 4306,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_53": {
+              "description": "clicintattr Register",
+              "offset": 4310,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_54": {
+              "description": "clicintattr Register",
+              "offset": 4314,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_55": {
+              "description": "clicintattr Register",
+              "offset": 4318,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_56": {
+              "description": "clicintattr Register",
+              "offset": 4322,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_57": {
+              "description": "clicintattr Register",
+              "offset": 4326,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_58": {
+              "description": "clicintattr Register",
+              "offset": 4330,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_59": {
+              "description": "clicintattr Register",
+              "offset": 4334,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_60": {
+              "description": "clicintattr Register",
+              "offset": 4338,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_61": {
+              "description": "clicintattr Register",
+              "offset": 4342,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_62": {
+              "description": "clicintattr Register",
+              "offset": 4346,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_63": {
+              "description": "clicintattr Register",
+              "offset": 4350,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_64": {
+              "description": "clicintattr Register",
+              "offset": 4354,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_65": {
+              "description": "clicintattr Register",
+              "offset": 4358,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_66": {
+              "description": "clicintattr Register",
+              "offset": 4362,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_67": {
+              "description": "clicintattr Register",
+              "offset": 4366,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_68": {
+              "description": "clicintattr Register",
+              "offset": 4370,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_69": {
+              "description": "clicintattr Register",
+              "offset": 4374,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_70": {
+              "description": "clicintattr Register",
+              "offset": 4378,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_71": {
+              "description": "clicintattr Register",
+              "offset": 4382,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_72": {
+              "description": "clicintattr Register",
+              "offset": 4386,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_73": {
+              "description": "clicintattr Register",
+              "offset": 4390,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_74": {
+              "description": "clicintattr Register",
+              "offset": 4394,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_75": {
+              "description": "clicintattr Register",
+              "offset": 4398,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_76": {
+              "description": "clicintattr Register",
+              "offset": 4402,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_77": {
+              "description": "clicintattr Register",
+              "offset": 4406,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_78": {
+              "description": "clicintattr Register",
+              "offset": 4410,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_79": {
+              "description": "clicintattr Register",
+              "offset": 4414,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_80": {
+              "description": "clicintattr Register",
+              "offset": 4418,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_81": {
+              "description": "clicintattr Register",
+              "offset": 4422,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_82": {
+              "description": "clicintattr Register",
+              "offset": 4426,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_83": {
+              "description": "clicintattr Register",
+              "offset": 4430,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_84": {
+              "description": "clicintattr Register",
+              "offset": 4434,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_85": {
+              "description": "clicintattr Register",
+              "offset": 4438,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTATTR_86": {
+              "description": "clicintattr Register",
+              "offset": 4442,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHV": {
+                    "description": "SHV",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TRIG": {
+                    "description": "TRIG",
+                    "offset": 1,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_0": {
+              "description": "clicintctl Register",
+              "offset": 4099,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_1": {
+              "description": "clicintctl Register",
+              "offset": 4103,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_2": {
+              "description": "clicintctl Register",
+              "offset": 4107,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_3": {
+              "description": "clicintctl Register",
+              "offset": 4111,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_4": {
+              "description": "clicintctl Register",
+              "offset": 4115,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_5": {
+              "description": "clicintctl Register",
+              "offset": 4119,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_6": {
+              "description": "clicintctl Register",
+              "offset": 4123,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_7": {
+              "description": "clicintctl Register",
+              "offset": 4127,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_8": {
+              "description": "clicintctl Register",
+              "offset": 4131,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_9": {
+              "description": "clicintctl Register",
+              "offset": 4135,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_10": {
+              "description": "clicintctl Register",
+              "offset": 4139,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_11": {
+              "description": "clicintctl Register",
+              "offset": 4143,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_12": {
+              "description": "clicintctl Register",
+              "offset": 4147,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_13": {
+              "description": "clicintctl Register",
+              "offset": 4151,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_14": {
+              "description": "clicintctl Register",
+              "offset": 4155,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_15": {
+              "description": "clicintctl Register",
+              "offset": 4159,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_16": {
+              "description": "clicintctl Register",
+              "offset": 4163,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_17": {
+              "description": "clicintctl Register",
+              "offset": 4167,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_18": {
+              "description": "clicintctl Register",
+              "offset": 4171,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_19": {
+              "description": "clicintctl Register",
+              "offset": 4175,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_20": {
+              "description": "clicintctl Register",
+              "offset": 4179,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_21": {
+              "description": "clicintctl Register",
+              "offset": 4183,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_22": {
+              "description": "clicintctl Register",
+              "offset": 4187,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_23": {
+              "description": "clicintctl Register",
+              "offset": 4191,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_24": {
+              "description": "clicintctl Register",
+              "offset": 4195,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_25": {
+              "description": "clicintctl Register",
+              "offset": 4199,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_26": {
+              "description": "clicintctl Register",
+              "offset": 4203,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_27": {
+              "description": "clicintctl Register",
+              "offset": 4207,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_28": {
+              "description": "clicintctl Register",
+              "offset": 4211,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_29": {
+              "description": "clicintctl Register",
+              "offset": 4215,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_30": {
+              "description": "clicintctl Register",
+              "offset": 4219,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_31": {
+              "description": "clicintctl Register",
+              "offset": 4223,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_32": {
+              "description": "clicintctl Register",
+              "offset": 4227,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_33": {
+              "description": "clicintctl Register",
+              "offset": 4231,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_34": {
+              "description": "clicintctl Register",
+              "offset": 4235,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_35": {
+              "description": "clicintctl Register",
+              "offset": 4239,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_36": {
+              "description": "clicintctl Register",
+              "offset": 4243,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_37": {
+              "description": "clicintctl Register",
+              "offset": 4247,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_38": {
+              "description": "clicintctl Register",
+              "offset": 4251,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_39": {
+              "description": "clicintctl Register",
+              "offset": 4255,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_40": {
+              "description": "clicintctl Register",
+              "offset": 4259,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_41": {
+              "description": "clicintctl Register",
+              "offset": 4263,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_42": {
+              "description": "clicintctl Register",
+              "offset": 4267,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_43": {
+              "description": "clicintctl Register",
+              "offset": 4271,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_44": {
+              "description": "clicintctl Register",
+              "offset": 4275,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_45": {
+              "description": "clicintctl Register",
+              "offset": 4279,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_46": {
+              "description": "clicintctl Register",
+              "offset": 4283,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_47": {
+              "description": "clicintctl Register",
+              "offset": 4287,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_48": {
+              "description": "clicintctl Register",
+              "offset": 4291,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_49": {
+              "description": "clicintctl Register",
+              "offset": 4295,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_50": {
+              "description": "clicintctl Register",
+              "offset": 4299,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_51": {
+              "description": "clicintctl Register",
+              "offset": 4303,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_52": {
+              "description": "clicintctl Register",
+              "offset": 4307,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_53": {
+              "description": "clicintctl Register",
+              "offset": 4311,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_54": {
+              "description": "clicintctl Register",
+              "offset": 4315,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_55": {
+              "description": "clicintctl Register",
+              "offset": 4319,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_56": {
+              "description": "clicintctl Register",
+              "offset": 4323,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_57": {
+              "description": "clicintctl Register",
+              "offset": 4327,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_58": {
+              "description": "clicintctl Register",
+              "offset": 4331,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_59": {
+              "description": "clicintctl Register",
+              "offset": 4335,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_60": {
+              "description": "clicintctl Register",
+              "offset": 4339,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_61": {
+              "description": "clicintctl Register",
+              "offset": 4343,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_62": {
+              "description": "clicintctl Register",
+              "offset": 4347,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_63": {
+              "description": "clicintctl Register",
+              "offset": 4351,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_64": {
+              "description": "clicintctl Register",
+              "offset": 4355,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_65": {
+              "description": "clicintctl Register",
+              "offset": 4359,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_66": {
+              "description": "clicintctl Register",
+              "offset": 4363,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_67": {
+              "description": "clicintctl Register",
+              "offset": 4367,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_68": {
+              "description": "clicintctl Register",
+              "offset": 4371,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_69": {
+              "description": "clicintctl Register",
+              "offset": 4375,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_70": {
+              "description": "clicintctl Register",
+              "offset": 4379,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_71": {
+              "description": "clicintctl Register",
+              "offset": 4383,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_72": {
+              "description": "clicintctl Register",
+              "offset": 4387,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_73": {
+              "description": "clicintctl Register",
+              "offset": 4391,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_74": {
+              "description": "clicintctl Register",
+              "offset": 4395,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_75": {
+              "description": "clicintctl Register",
+              "offset": 4399,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_76": {
+              "description": "clicintctl Register",
+              "offset": 4403,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_77": {
+              "description": "clicintctl Register",
+              "offset": 4407,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_78": {
+              "description": "clicintctl Register",
+              "offset": 4411,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_79": {
+              "description": "clicintctl Register",
+              "offset": 4415,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_80": {
+              "description": "clicintctl Register",
+              "offset": 4419,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_81": {
+              "description": "clicintctl Register",
+              "offset": 4423,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_82": {
+              "description": "clicintctl Register",
+              "offset": 4427,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_83": {
+              "description": "clicintctl Register",
+              "offset": 4431,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_84": {
+              "description": "clicintctl Register",
+              "offset": 4435,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_85": {
+              "description": "clicintctl Register",
+              "offset": 4439,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLICINTCTL_86": {
+              "description": "clicintctl Register",
+              "offset": 4443,
+              "size": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEVEL_PRIORITY": {
+                    "description": "LEVEL_PRIORITY",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PMU": {
+        "description": "Power management unit",
+        "children": {
+          "registers": {
+            "CTL": {
+              "description": "power control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BKPWEN": {
+                    "description": "Backup Domain Write Enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LVDT": {
+                    "description": "Low Voltage Detector Threshold",
+                    "offset": 5,
+                    "size": 3
+                  },
+                  "LVDEN": {
+                    "description": "Low Voltage Detector Enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STBRST": {
+                    "description": "Standby Flag Reset",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "WURST": {
+                    "description": "Wakeup Flag Reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "STBMOD": {
+                    "description": "Standby Mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LDOLP": {
+                    "description": "LDO Low Power Mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CS": {
+              "description": "power control/status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WUPEN": {
+                    "description": "Enable WKUP pin",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LVDF": {
+                    "description": "Low Voltage Detector Status Flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STBF": {
+                    "description": "Standby flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WUF": {
+                    "description": "Wakeup flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RCU": {
+        "description": "Reset and clock unit",
+        "children": {
+          "registers": {
+            "CTL": {
+              "description": "Control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 131,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IRC8MEN": {
+                    "description": "Internal 8MHz RC oscillator Enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IRC8MSTB": {
+                    "description": "IRC8M Internal 8MHz RC Oscillator stabilization Flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRC8MADJ": {
+                    "description": "Internal 8MHz RC Oscillator clock trim adjust value",
+                    "offset": 3,
+                    "size": 5
+                  },
+                  "IRC8MCALIB": {
+                    "description": "Internal 8MHz RC Oscillator calibration value register",
+                    "offset": 8,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "HXTALEN": {
+                    "description": "External High Speed oscillator Enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "HXTALSTB": {
+                    "description": "External crystal oscillator (HXTAL) clock stabilization flag",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HXTALBPS": {
+                    "description": "External crystal oscillator (HXTAL) clock bypass mode enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CKMEN": {
+                    "description": "HXTAL Clock Monitor Enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PLLEN": {
+                    "description": "PLL enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PLLSTB": {
+                    "description": "PLL Clock Stabilization Flag",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLL1EN": {
+                    "description": "PLL1 enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PLL1STB": {
+                    "description": "PLL1 Clock Stabilization Flag",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLL2EN": {
+                    "description": "PLL2 enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "PLL2STB": {
+                    "description": "PLL2 Clock Stabilization Flag",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CFG0": {
+              "description": "Clock configuration register 0\n          (RCU_CFG0)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCS": {
+                    "description": "System clock switch",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SCSS": {
+                    "description": "System clock switch status",
+                    "offset": 2,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "AHBPSC": {
+                    "description": "AHB prescaler selection",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "APB1PSC": {
+                    "description": "APB1 prescaler selection",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "APB2PSC": {
+                    "description": "APB2 prescaler selection",
+                    "offset": 11,
+                    "size": 3
+                  },
+                  "ADCPSC_1_0": {
+                    "description": "ADC clock prescaler selection",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "PLLSEL": {
+                    "description": "PLL Clock Source Selection",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PREDV0_LSB": {
+                    "description": "The LSB of PREDV0 division factor",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PLLMF_3_0": {
+                    "description": "The PLL clock multiplication factor",
+                    "offset": 18,
+                    "size": 4
+                  },
+                  "USBFSPSC": {
+                    "description": "USBFS clock prescaler selection",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CKOUT0SEL": {
+                    "description": "CKOUT0 Clock Source Selection",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "ADCPSC_2": {
+                    "description": "Bit 2 of ADCPSC",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "PLLMF_4": {
+                    "description": "Bit 4 of PLLMF",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT": {
+              "description": "Clock interrupt register\n          (RCU_INT)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IRC40KSTBIF": {
+                    "description": "IRC40K stabilization interrupt flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LXTALSTBIF": {
+                    "description": "LXTAL stabilization interrupt flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRC8MSTBIF": {
+                    "description": "IRC8M stabilization interrupt flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HXTALSTBIF": {
+                    "description": "HXTAL stabilization interrupt flag",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLLSTBIF": {
+                    "description": "PLL stabilization interrupt flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLL1STBIF": {
+                    "description": "PLL1 stabilization interrupt flag",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PLL2STBIF": {
+                    "description": "PLL2 stabilization interrupt flag",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CKMIF": {
+                    "description": "HXTAL Clock Stuck Interrupt Flag",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRC40KSTBIE": {
+                    "description": "IRC40K Stabilization interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LXTALSTBIE": {
+                    "description": "LXTAL Stabilization Interrupt Enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IRC8MSTBIE": {
+                    "description": "IRC8M Stabilization Interrupt Enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "HXTALSTBIE": {
+                    "description": "HXTAL Stabilization Interrupt Enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PLLSTBIE": {
+                    "description": "PLL Stabilization Interrupt Enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PLL1STBIE": {
+                    "description": "PLL1 Stabilization Interrupt Enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PLL2STBIE": {
+                    "description": "PLL2 Stabilization Interrupt Enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "IRC40KSTBIC": {
+                    "description": "IRC40K Stabilization Interrupt Clear",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LXTALSTBIC": {
+                    "description": "LXTAL Stabilization Interrupt Clear",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IRC8MSTBIC": {
+                    "description": "IRC8M Stabilization Interrupt Clear",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "HXTALSTBIC": {
+                    "description": "HXTAL Stabilization Interrupt Clear",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PLLSTBIC": {
+                    "description": "PLL stabilization Interrupt Clear",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PLL1STBIC": {
+                    "description": "PLL1 stabilization Interrupt Clear",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PLL2STBIC": {
+                    "description": "PLL2 stabilization Interrupt Clear",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CKMIC": {
+                    "description": "HXTAL Clock Stuck Interrupt Clear",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "APB2RST": {
+              "description": "APB2 reset register\n          (RCU_APB2RST)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFRST": {
+                    "description": "Alternate function I/O reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PARST": {
+                    "description": "GPIO port A reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PBRST": {
+                    "description": "GPIO port B reset",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PCRST": {
+                    "description": "GPIO port C reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PDRST": {
+                    "description": "GPIO port D reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PERST": {
+                    "description": "GPIO port E reset",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ADC0RST": {
+                    "description": "ADC0 reset",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ADC1RST": {
+                    "description": "ADC1 reset",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TIMER0RST": {
+                    "description": "Timer 0 reset",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI0RST": {
+                    "description": "SPI0 reset",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "USART0RST": {
+                    "description": "USART0 Reset",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1RST": {
+              "description": "APB1 reset register\n          (RCU_APB1RST)",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER1RST": {
+                    "description": "TIMER1 timer reset",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIMER2RST": {
+                    "description": "TIMER2 timer reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIMER3RST": {
+                    "description": "TIMER3 timer reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIMER4RST": {
+                    "description": "TIMER4 timer reset",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TIMER5RST": {
+                    "description": "TIMER5 timer reset",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIMER6RST": {
+                    "description": "TIMER6 timer reset",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WWDGTRST": {
+                    "description": "Window watchdog timer reset",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI1RST": {
+                    "description": "SPI1 reset",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI2RST": {
+                    "description": "SPI2 reset",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "USART1RST": {
+                    "description": "USART1 reset",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USART2RST": {
+                    "description": "USART2 reset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "UART3RST": {
+                    "description": "UART3 reset",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UART4RST": {
+                    "description": "UART4 reset",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2C0RST": {
+                    "description": "I2C0 reset",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "I2C1RST": {
+                    "description": "I2C1 reset",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CAN0RST": {
+                    "description": "CAN0 reset",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CAN1RST": {
+                    "description": "CAN1 reset",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BKPIRST": {
+                    "description": "Backup interface reset",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PMURST": {
+                    "description": "Power control reset",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DACRST": {
+                    "description": "DAC reset",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AHBEN": {
+              "description": "AHB enable register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 20,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA0EN": {
+                    "description": "DMA0 clock enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMA1EN": {
+                    "description": "DMA1 clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SRAMSPEN": {
+                    "description": "SRAM interface clock enable when sleep mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FMCSPEN": {
+                    "description": "FMC clock enable when sleep mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CRCEN": {
+                    "description": "CRC clock enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EXMCEN": {
+                    "description": "EXMC clock enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "USBFSEN": {
+                    "description": "USBFS clock enable",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB2EN": {
+              "description": "APB2 clock enable register\n          (RCU_APB2EN)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AFEN": {
+                    "description": "Alternate function IO clock enable ",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PAEN": {
+                    "description": "GPIO port A clock enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PBEN": {
+                    "description": "GPIO port B clock enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PCEN": {
+                    "description": "GPIO port C clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PDEN": {
+                    "description": "GPIO port D clock enable ",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PEEN": {
+                    "description": "GPIO port E clock enable ",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ADC0EN": {
+                    "description": "ADC0 clock enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ADC1EN": {
+                    "description": "ADC1 clock enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TIMER0EN": {
+                    "description": "TIMER0 clock enable ",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI0EN": {
+                    "description": "SPI0 clock enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "USART0EN": {
+                    "description": "USART0 clock enable",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB1EN": {
+              "description": "APB1 clock enable register\n          (RCU_APB1EN)",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER1EN": {
+                    "description": "TIMER1 timer clock enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIMER2EN": {
+                    "description": "TIMER2 timer clock enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TIMER3EN": {
+                    "description": "TIMER3 timer clock enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TIMER4EN": {
+                    "description": "TIMER4 timer clock enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TIMER5EN": {
+                    "description": "TIMER5 timer clock enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TIMER6EN": {
+                    "description": "TIMER6 timer clock enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "WWDGTEN": {
+                    "description": "Window watchdog timer clock enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SPI1EN": {
+                    "description": "SPI1 clock enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SPI2EN": {
+                    "description": "SPI2 clock enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "USART1EN": {
+                    "description": "USART1 clock enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USART2EN": {
+                    "description": "USART2 clock enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "UART3EN": {
+                    "description": "UART3 clock enable",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "UART4EN": {
+                    "description": "UART4 clock enable",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2C0EN": {
+                    "description": "I2C0 clock enable",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "I2C1EN": {
+                    "description": "I2C1 clock enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "CAN0EN": {
+                    "description": "CAN0 clock enable",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CAN1EN": {
+                    "description": "CAN1 clock enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BKPIEN": {
+                    "description": "Backup interface clock enable ",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PMUEN": {
+                    "description": "Power control clock enable ",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DACEN": {
+                    "description": "DAC clock enable",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BDCTL": {
+              "description": "Backup domain control register\n          (RCU_BDCTL)",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 24,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LXTALEN": {
+                    "description": "LXTAL enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LXTALSTB": {
+                    "description": "External low-speed oscillator stabilization",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LXTALBPS": {
+                    "description": "LXTAL bypass mode enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTCSRC": {
+                    "description": "RTC clock entry selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "RTCEN": {
+                    "description": "RTC clock enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BKPRST": {
+                    "description": "Backup domain reset",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RSTSCK": {
+              "description": "Reset source /clock register\n          (RCU_RSTSCK)",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 201326592,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IRC40KEN": {
+                    "description": "IRC40K enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IRC40KSTB": {
+                    "description": "IRC40K stabilization",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RSTFC": {
+                    "description": "Reset flag clear",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EPRSTF": {
+                    "description": "External PIN reset flag",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PORRSTF": {
+                    "description": "Power reset flag",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SWRSTF": {
+                    "description": "Software reset flag",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FWDGTRSTF": {
+                    "description": "Free Watchdog timer reset flag",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WWDGTRSTF": {
+                    "description": "Window watchdog timer reset flag",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LPRSTF": {
+                    "description": "Low-power reset flag",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "AHBRST": {
+              "description": "AHB reset register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USBFSRST": {
+                    "description": "USBFS reset",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CFG1": {
+              "description": "Clock Configuration register 1",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PREDV0": {
+                    "description": "PREDV0 division factor",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "PREDV1": {
+                    "description": "PREDV1 division factor",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "PLL1MF": {
+                    "description": "The PLL1 clock multiplication factor",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "PLL2MF": {
+                    "description": "The PLL2 clock multiplication factor",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "PREDV0SEL": {
+                    "description": "PREDV0 input Clock Source Selection",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "I2S1SEL": {
+                    "description": "I2S1 Clock Source Selection",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "I2S2SEL": {
+                    "description": "I2S2 Clock Source Selection",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DSV": {
+              "description": "Deep sleep mode Voltage register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DSLPVS": {
+                    "description": "Deep-sleep mode voltage select",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RTC": {
+        "description": "Real-time clock",
+        "children": {
+          "registers": {
+            "INTEN": {
+              "description": "RTC interrupt enable register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OVIE": {
+                    "description": "Overflow interrupt enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ALRMIE": {
+                    "description": "Alarm interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SCIE": {
+                    "description": "Second interrupt",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTL": {
+              "description": "control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 32,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LWOFF": {
+                    "description": "Last write operation finished flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CMF": {
+                    "description": "Configuration mode flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RSYNF": {
+                    "description": "Registers synchronized flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OVIF": {
+                    "description": "Overflow interrupt flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ALRMIF": {
+                    "description": "Alarm interrupt flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SCIF": {
+                    "description": "Sencond interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PSCH": {
+              "description": "RTC prescaler high register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "PSCL": {
+              "description": " RTC prescaler low\n          register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295
+            },
+            "DIVH": {
+              "description": "RTC divider high register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DIV": {
+                    "description": "RTC divider value high",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DIVL": {
+              "description": "RTC divider low register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "DIV": {
+                    "description": "RTC divider value low",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CNTH": {
+              "description": "RTC counter high register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "RTC counter value high",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CNTL": {
+              "description": "RTC counter low register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "RTC counter value low",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI0": {
+        "description": "Serial peripheral interface",
+        "children": {
+          "registers": {
+            "CTL0": {
+              "description": "control register 0",
+              "offset": 0,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BDEN": {
+                    "description": "Bidirectional \n              enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BDOEN": {
+                    "description": "Bidirectional Transmit output enable\n              ",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CRCEN": {
+                    "description": "CRC Calculation Enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CRCNT": {
+                    "description": "CRC Next Transfer",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FF16": {
+                    "description": "Data frame format",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RO": {
+                    "description": "Receive only",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SWNSSEN": {
+                    "description": "NSS Software Mode Selection",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SWNSS": {
+                    "description": "NSS Pin Selection In NSS Software Mode",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LF": {
+                    "description": "LSB First Mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SPIEN": {
+                    "description": "SPI enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PSC": {
+                    "description": "Master Clock Prescaler Selection",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "MSTMOD": {
+                    "description": "Master Mode Enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CKPL": {
+                    "description": "Clock polarity Selection",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CKPH": {
+                    "description": "Clock Phase Selection",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTL1": {
+              "description": "control register 1",
+              "offset": 4,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TBEIE": {
+                    "description": "Tx buffer empty interrupt\n              enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RBNEIE": {
+                    "description": "RX buffer not empty interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TMOD": {
+                    "description": "SPI TI mode enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "NSSP": {
+                    "description": "SPI NSS pulse mode enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "NSSDRV": {
+                    "description": "Drive NSS Output",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DMATEN": {
+                    "description": "Transmit Buffer DMA Enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DMAREN": {
+                    "description": "Rx buffer DMA enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "STAT": {
+              "description": "status register",
+              "offset": 8,
+              "size": 16,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FERR": {
+                    "description": "Format error",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS": {
+                    "description": "Transmitting On-going Bit",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXORERR": {
+                    "description": "Reception Overrun Error Bit",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CONFERR": {
+                    "description": "SPI Configuration error",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRCERR": {
+                    "description": "SPI CRC Error Bit",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TXURERR": {
+                    "description": "Transmission underrun error bit",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "I2SCH": {
+                    "description": "I2S channel side",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TBE": {
+                    "description": "Transmit Buffer Empty",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RBNE": {
+                    "description": "Receive Buffer Not Empty",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATA": {
+              "description": "data register",
+              "offset": 12,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_DATA": {
+                    "description": "Data transfer register",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CRCPOLY": {
+              "description": "CRC polynomial register",
+              "offset": 16,
+              "size": 16,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRCPOLY": {
+                    "description": "CRC polynomial value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "RCRC": {
+              "description": "RX CRC register",
+              "offset": 20,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "RCRC": {
+                    "description": "RX CRC value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TCRC": {
+              "description": "TX CRC register",
+              "offset": 24,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "read-only",
+              "children": {
+                "fields": {
+                  "TCRC": {
+                    "description": "Tx CRC value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "I2SCTL": {
+              "description": "I2S control register",
+              "offset": 28,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "I2SSEL": {
+                    "description": "I2S mode selection",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "I2SEN": {
+                    "description": "I2S Enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "I2SOPMOD": {
+                    "description": "I2S operation mode",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "PCMSMOD": {
+                    "description": "PCM frame synchronization mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "I2SSTD": {
+                    "description": "I2S standard selection",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CKPL": {
+                    "description": "Idle state clock polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DTLEN": {
+                    "description": "Data length",
+                    "offset": 1,
+                    "size": 2
+                  },
+                  "CHLEN": {
+                    "description": "Channel length (number of bits per audio\n              channel)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "I2SPSC": {
+              "description": "I2S prescaler register",
+              "offset": 32,
+              "size": 16,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCKOEN": {
+                    "description": "I2S_MCK output enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OF": {
+                    "description": "Odd factor for the\n              prescaler",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIV": {
+                    "description": "Dividing factor for the prescaler",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UART3": {
+        "description": "Universal  asynchronous receiver\n      transmitter",
+        "children": {
+          "registers": {
+            "STAT": {
+              "description": "Status register ",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LBDF": {
+                    "description": "LIN break detection flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TBE": {
+                    "description": "Transmit data buffer empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TC": {
+                    "description": "Transmission complete",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RBNE": {
+                    "description": "Read data buffer not empty",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLEF": {
+                    "description": "IDLE frame detected flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ORERR": {
+                    "description": "Overrun error",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NERR": {
+                    "description": "Noise error flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FERR": {
+                    "description": "Frame error flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PERR": {
+                    "description": "Parity error flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATA": {
+              "description": "Data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Transmit or read data value",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "BAUD": {
+              "description": "Baud rate register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTDIV": {
+                    "description": "Integer part of baud-rate divider",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "FRADIV": {
+                    "description": "Fraction part of baud-rate divider",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CTL0": {
+              "description": "Control register 0",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UEN": {
+                    "description": "USART enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WL": {
+                    "description": "Word length",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WM": {
+                    "description": "Wakeup method in mute mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PCEN": {
+                    "description": "Parity check function enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PM": {
+                    "description": "Parity mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PERRIE": {
+                    "description": "Parity error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TBEIE": {
+                    "description": "Transmitter buffer empty interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transmission complete interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RBNEIE": {
+                    "description": "Read data buffer not empty interrupt and overrun error interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLEIE": {
+                    "description": "IDLE line detected interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TEN": {
+                    "description": "Transmitter enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "REN": {
+                    "description": "Receiver enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RWU": {
+                    "description": "Receiver wakeup from mute mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SBKCMD": {
+                    "description": "Send break command",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTL1": {
+              "description": "Control register 1",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LMEN": {
+                    "description": "LIN mode enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "STB": {
+                    "description": "STOP bits length",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "LBDIE": {
+                    "description": "LIN break detection interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LBLEN": {
+                    "description": "LIN break frame length",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADDR": {
+                    "description": "Address of the USART",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CTL2": {
+              "description": "Control register 2",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DENT": {
+                    "description": "DMA request enable for transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DENR": {
+                    "description": "DMA request enable for reception",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "HDEN": {
+                    "description": "Half-duplex selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IRLP": {
+                    "description": "IrDA low-power",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IrDA mode enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GP": {
+              "description": "Guard time and prescaler\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USART0": {
+        "description": "Universal synchronous asynchronous receiver\n      transmitter",
+        "children": {
+          "registers": {
+            "STAT": {
+              "description": "Status register ",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTSF": {
+                    "description": "CTS change flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "LBDF": {
+                    "description": "LIN break detection flag",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TBE": {
+                    "description": "Transmit data buffer empty",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TC": {
+                    "description": "Transmission complete",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RBNE": {
+                    "description": "Read data buffer not empty",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLEF": {
+                    "description": "IDLE frame detected flag",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ORERR": {
+                    "description": "Overrun error",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NERR": {
+                    "description": "Noise error flag",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FERR": {
+                    "description": "Frame error flag",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PERR": {
+                    "description": "Parity error flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATA": {
+              "description": "Data register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Transmit or read data value",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "BAUD": {
+              "description": "Baud rate register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTDIV": {
+                    "description": "Integer part of baud-rate divider",
+                    "offset": 4,
+                    "size": 12
+                  },
+                  "FRADIV": {
+                    "description": "Fraction part of baud-rate divider",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CTL0": {
+              "description": "Control register 0",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UEN": {
+                    "description": "USART enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WL": {
+                    "description": "Word length",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WM": {
+                    "description": "Wakeup method in mute mode",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "PCEN": {
+                    "description": "Parity check function enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PM": {
+                    "description": "Parity mode",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PERRIE": {
+                    "description": "Parity error interrupt enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TBEIE": {
+                    "description": "Transmitter buffer empty interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TCIE": {
+                    "description": "Transmission complete interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RBNEIE": {
+                    "description": "Read data buffer not empty interrupt and overrun error interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IDLEIE": {
+                    "description": "IDLE line detected interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TEN": {
+                    "description": "Transmitter enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "REN": {
+                    "description": "Receiver enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RWU": {
+                    "description": "Receiver wakeup from mute mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SBKCMD": {
+                    "description": "Send break command",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTL1": {
+              "description": "Control register 1",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LMEN": {
+                    "description": "LIN mode enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "STB": {
+                    "description": "STOP bits length",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CKEN": {
+                    "description": "CK pin enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CPL": {
+                    "description": "Clock polarity",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CPH": {
+                    "description": "Clock phase",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CLEN": {
+                    "description": "CK Length",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LBDIE": {
+                    "description": "LIN break detection interrupt\n              enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "LBLEN": {
+                    "description": "LIN break frame length",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADDR": {
+                    "description": "Address of the USART",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CTL2": {
+              "description": "Control register 2",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CTSIE": {
+                    "description": "CTS interrupt enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CTSEN": {
+                    "description": "CTS enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RTSEN": {
+                    "description": "RTS enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DENT": {
+                    "description": "DMA request enable for transmission",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DENR": {
+                    "description": "DMA request enable for reception",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SCEN": {
+                    "description": "Smartcard mode enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "NKEN": {
+                    "description": "Smartcard NACK enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "HDEN": {
+                    "description": "Half-duplex selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "IRLP": {
+                    "description": "IrDA low-power",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IREN": {
+                    "description": "IrDA mode enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ERRIE": {
+                    "description": "Error interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GP": {
+              "description": "Guard time and prescaler\n          register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GUAT": {
+                    "description": "Guard time value in Smartcard mode",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "PSC": {
+                    "description": "Prescaler value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIMER0": {
+        "description": "Advanced-timers",
+        "children": {
+          "registers": {
+            "CTL0": {
+              "description": "control register 0",
+              "offset": 0,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKDIV": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARSE": {
+                    "description": "Auto-reload shadow enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CAM": {
+                    "description": "Counter aligns mode\n              selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SPM": {
+                    "description": "Single pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "UPS": {
+                    "description": "Update source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UPDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTL1": {
+              "description": "control register 1",
+              "offset": 4,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ISO3": {
+                    "description": "Idle state of channel 3 output",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ISO2N": {
+                    "description": "Idle state of channel 2 complementary output",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ISO2": {
+                    "description": "Idle state of channel 2 output",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ISO1N": {
+                    "description": "Idle state of channel 1 complementary output",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "ISO1": {
+                    "description": "Idle state of channel 1 output",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ISO0N": {
+                    "description": "Idle state of channel 0 complementary output",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ISO0": {
+                    "description": "Idle state of channel 0 output",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TI0S": {
+                    "description": "Channel 0 trigger input selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMC": {
+                    "description": "Master mode control",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "DMAS": {
+                    "description": "DMA request source selection",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CCUC": {
+                    "description": "Commutation control shadow register update control",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CCSE": {
+                    "description": "Commutation control shadow enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCFG": {
+              "description": "slave mode configuration register",
+              "offset": 8,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SMC1": {
+                    "description": "Part of SMC for enable External clock mode1",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPSC": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETFC": {
+                    "description": "External trigger filter control",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master/Slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TRGS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMC": {
+                    "description": "Slave mode selection",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DMAINTEN": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRGDEN": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CMTDEN": {
+                    "description": "Commutation DMA request enable",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CH3DEN": {
+                    "description": "Channel 3 capture/compare DMA request enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CH2DEN": {
+                    "description": "Channel 2 capture/compare DMA request enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CH1DEN": {
+                    "description": "Channel 1 capture/compare DMA request enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CH0DEN": {
+                    "description": "Channel 0 capture/compare DMA request enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UPDEN": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BRKIE": {
+                    "description": "Break interrupt enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TRGIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CMTIE": {
+                    "description": "commutation interrupt enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CH3IE": {
+                    "description": "Channel 3 capture/compare interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH2IE": {
+                    "description": "Channel 2 capture/compare interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH1IE": {
+                    "description": "Channel 1 capture/compare interrupt enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH0IE": {
+                    "description": "Channel 0 capture/compare interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UPIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTF": {
+              "description": "Interrupt flag register",
+              "offset": 16,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH3OF": {
+                    "description": "Channel 3 over capture flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CH2OF": {
+                    "description": "Channel 2 over capture flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CH1OF": {
+                    "description": "Channel 1 over capture flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CH0OF": {
+                    "description": "Channel 0 over capture flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BRKIF": {
+                    "description": "Break interrupt flag",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TRGIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CMTIF": {
+                    "description": "Channel commutation interrupt flag",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CH3IF": {
+                    "description": "Channel 3 capture/compare interrupt flag",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH2IF": {
+                    "description": " Channel 2 capture/compare interrupt flag",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH1IF": {
+                    "description": "Channel 1  capture/compare interrupt flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH0IF": {
+                    "description": "Channel 0  capture/compare interrupt flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UPIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWEVG": {
+              "description": "Software event generation register",
+              "offset": 20,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "BRKG": {
+                    "description": "Break event generation",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TRGG": {
+                    "description": "Trigger event generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CMTG": {
+                    "description": "Channel commutation event generation",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CH3G": {
+                    "description": "Channel  3 capture or compare event generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH2G": {
+                    "description": "Channel 2 capture or compare event generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH1G": {
+                    "description": "Channel 1 capture or compare event generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH0G": {
+                    "description": "Channel 0 capture or compare event generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UPG": {
+                    "description": "Update event generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CHCTL0_Output": {
+              "description": "Channel control register 0 (output\n          mode)",
+              "offset": 24,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH1COMCEN": {
+                    "description": "Channel 1 output compare clear enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CH1COMCTL": {
+                    "description": "Channel 1 compare output control",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "CH1COMSEN": {
+                    "description": "Channel 1 output compare shadow enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CH1COMFEN": {
+                    "description": "Channel 1 output compare fast enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CH1MS": {
+                    "description": "Channel 1 mode selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CH0COMCEN": {
+                    "description": "Channel 0 output compare clear enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CH0COMCTL": {
+                    "description": "Channel 0 compare output control",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CH0COMSEN": {
+                    "description": "Channel 0 compare output shadow enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH0COMFEN": {
+                    "description": "Channel 0 output compare fast enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH0MS": {
+                    "description": "Channel 0 I/O mode selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CHCTL0_Input": {
+              "description": "Channel control register 0 (input\n          mode)",
+              "offset": 24,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH1CAPFLT": {
+                    "description": "Channel 1 input capture filter control",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "CH1CAPPSC": {
+                    "description": "Channel 1 input capture prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CH1MS": {
+                    "description": "Channel 1 mode selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CH0CAPFLT": {
+                    "description": "Channel 0 input capture filter control",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "CH0CAPPSC": {
+                    "description": "Channel 0 input capture prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CH0MS": {
+                    "description": "Channel 0 mode selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CHCTL1_Output": {
+              "description": "Channel control register 1 (output\n          mode)",
+              "offset": 28,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH3COMCEN": {
+                    "description": "Channel 3 output compare clear enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CH3COMCTL": {
+                    "description": "Channel 3 compare output control",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "CH3COMSEN": {
+                    "description": "Channel 3 output compare shadow enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CH3COMFEN": {
+                    "description": "Channel 3 output compare fast enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CH3MS": {
+                    "description": "Channel 3 mode selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CH2COMCEN": {
+                    "description": "Channel 2 output compare clear enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CH2COMCTL": {
+                    "description": "Channel 2 compare output control",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CH2COMSEN": {
+                    "description": "Channel 2 compare output shadow enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH2COMFEN": {
+                    "description": "Channel 2 output compare fast enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH2MS": {
+                    "description": "Channel 2 I/O mode selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CHCTL1_Input": {
+              "description": "Channel control register 1 (input\n          mode)",
+              "offset": 28,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH3CAPFLT": {
+                    "description": "Channel 3 input capture filter control",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "CH3CAPPSC": {
+                    "description": "Channel 3 input capture prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CH3MS": {
+                    "description": "Channel 3 mode selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CH2CAPFLT": {
+                    "description": "Channel 2 input capture filter control",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "CH2CAPPSC": {
+                    "description": "Channel 2 input capture prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CH2MS": {
+                    "description": "Channel 2 mode selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CHCTL2": {
+              "description": "Channel control register 2",
+              "offset": 32,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH3P": {
+                    "description": "Channel 3 capture/compare function polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CH3EN": {
+                    "description": "Channel 3 capture/compare function enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CH2NP": {
+                    "description": "Channel 2 complementary output polarity",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CH2NEN": {
+                    "description": "Channel 2 complementary output enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CH2P": {
+                    "description": "Channel 2 capture/compare function polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CH2EN": {
+                    "description": "Channel 2 capture/compare function enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CH1NP": {
+                    "description": "Channel 1 complementary output polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CH1NEN": {
+                    "description": "Channel 1 complementary output enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CH1P": {
+                    "description": "Channel 1 capture/compare function polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CH1EN": {
+                    "description": "Channel 1 capture/compare function enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH0NP": {
+                    "description": "Channel 0 complementary output polarity",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH0NEN": {
+                    "description": "Channel 0 complementary output enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH0P": {
+                    "description": "Channel 0 capture/compare function polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CH0EN": {
+                    "description": "Channel 0 capture/compare function enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "counter",
+              "offset": 36,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "current counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "prescaler",
+              "offset": 40,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value of the counter clock",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CAR": {
+              "description": "Counter auto reload register",
+              "offset": 44,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CARL": {
+                    "description": "Counter auto reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CREP": {
+              "description": "Counter repetition register",
+              "offset": 48,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CREP": {
+                    "description": "Counter repetition value",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CH0CV": {
+              "description": "Channel 0 capture/compare value register",
+              "offset": 52,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0VAL": {
+                    "description": "Capture or compare value of channel0",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH1CV": {
+              "description": "Channel 1 capture/compare value register",
+              "offset": 56,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH1VAL": {
+                    "description": "Capture or compare value of channel1",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH2CV": {
+              "description": "Channel 2 capture/compare value register",
+              "offset": 60,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH2VAL": {
+                    "description": "Capture or compare value of channel 2",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH3CV": {
+              "description": "Channel 3 capture/compare value register",
+              "offset": 64,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH3VAL": {
+                    "description": "Capture or compare value of channel 3",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CCHP": {
+              "description": "channel complementary protection register",
+              "offset": 68,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POEN": {
+                    "description": "Primary output enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OAEN": {
+                    "description": "Output automatic enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "BRKP": {
+                    "description": "Break polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BRKEN": {
+                    "description": "Break enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ROS": {
+                    "description": "Run mode off-state configure",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IOS": {
+                    "description": "Idle mode off-state configure",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PROT": {
+                    "description": "Complementary register protect control",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "DTCFG": {
+                    "description": "Dead time configure",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DMACFG": {
+              "description": "DMA configuration register",
+              "offset": 72,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMATC": {
+                    "description": "DMA transfer count",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DMATA": {
+                    "description": "DMA transfer access start address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMATB": {
+              "description": "DMA transfer buffer register",
+              "offset": 76,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMATB": {
+                    "description": "DMA transfer buffer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIMER1": {
+        "description": "General-purpose-timers",
+        "children": {
+          "registers": {
+            "CTL0": {
+              "description": "control register 0",
+              "offset": 0,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CKDIV": {
+                    "description": "Clock division",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ARSE": {
+                    "description": "Auto-reload shadow enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CAM": {
+                    "description": "Counter aligns mode selection",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "DIR": {
+                    "description": "Direction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SPM": {
+                    "description": "Single pulse mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "UPS": {
+                    "description": "Update source",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UPDIS": {
+                    "description": "Update disable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CEN": {
+                    "description": "Counter enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTL1": {
+              "description": "control register 1",
+              "offset": 4,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TI0S": {
+                    "description": "Channel 0 trigger input selection",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "MMC": {
+                    "description": "Master mode control",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "DMAS": {
+                    "description": "DMA request source selection",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SMCFG": {
+              "description": "slave mode control register",
+              "offset": 8,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ETP": {
+                    "description": "External trigger polarity",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SMC1": {
+                    "description": "Part of SMC for enable External clock mode1",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "ETPSC": {
+                    "description": "External trigger prescaler",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "ETFC": {
+                    "description": "External trigger filter control",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "MSM": {
+                    "description": "Master-slave mode",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TRGS": {
+                    "description": "Trigger selection",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "SMC": {
+                    "description": "Slave mode control",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DMAINTEN": {
+              "description": "DMA/Interrupt enable register",
+              "offset": 12,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRGDEN": {
+                    "description": "Trigger DMA request enable",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "CH3DEN": {
+                    "description": "Channel 3 capture/compare DMA request enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CH2DEN": {
+                    "description": "Channel 2 capture/compare DMA request enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CH1DEN": {
+                    "description": "Channel 1 capture/compare DMA request enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CH0DEN": {
+                    "description": "Channel 0 capture/compare DMA request enable",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "UPDEN": {
+                    "description": "Update DMA request enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TRGIE": {
+                    "description": "Trigger interrupt enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CH3IE": {
+                    "description": "Channel 3 capture/compare interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH2IE": {
+                    "description": "Channel 2 capture/compare interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH1IE": {
+                    "description": "Channel 1 capture/compare interrupt enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH0IE": {
+                    "description": "Channel 0 capture/compare interrupt enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UPIE": {
+                    "description": "Update interrupt enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTF": {
+              "description": "interrupt flag register",
+              "offset": 16,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH3OF": {
+                    "description": "Channel 3 over capture flag",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CH2OF": {
+                    "description": "Channel 2 over capture flag",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CH1OF": {
+                    "description": "Channel 1 over capture flag",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CH0OF": {
+                    "description": "Channel 0 over capture flag",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TRGIF": {
+                    "description": "Trigger interrupt flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CH3IF": {
+                    "description": "Channel 3  capture/compare interrupt enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH2IF": {
+                    "description": "Channel 2  capture/compare interrupt enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH1IF": {
+                    "description": "Channel 1  capture/compare interrupt flag",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH0IF": {
+                    "description": "Channel 0  capture/compare interrupt flag",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UPIF": {
+                    "description": "Update interrupt flag",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWEVG": {
+              "description": "event generation register",
+              "offset": 20,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "access": "write-only",
+              "children": {
+                "fields": {
+                  "TRGG": {
+                    "description": "Trigger event generation",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CH3G": {
+                    "description": "Channel 3 capture or compare event generation",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH2G": {
+                    "description": "Channel 2 capture or compare event generation",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH1G": {
+                    "description": "Channel 1 capture or compare event generation",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH0G": {
+                    "description": "Channel 0 capture or compare event generation",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UPG": {
+                    "description": "Update generation",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CHCTL0_Output": {
+              "description": "Channel control register 0 (output\n          mode)",
+              "offset": 24,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH1COMCEN": {
+                    "description": "Channel 1 output compare clear enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CH1COMCTL": {
+                    "description": "Channel 1 compare output control",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "CH1COMSEN": {
+                    "description": "Channel 1 output compare shadow enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CH1COMFEN": {
+                    "description": "Channel 1 output compare fast enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CH1MS": {
+                    "description": "Channel 1 mode selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CH0COMCEN": {
+                    "description": "Channel 0 output compare clear enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CH0COMCTL": {
+                    "description": " Channel 0 compare output control",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CH0COMSEN": {
+                    "description": "Channel 0 compare output shadow enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH0COMFEN": {
+                    "description": "Channel 0 output compare fast enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH0MS": {
+                    "description": "Channel 0 I/O mode selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CHCTL0_Input": {
+              "description": "Channel control register 0 (input\n          mode)",
+              "offset": 24,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH1CAPFLT": {
+                    "description": "Channel 1 input capture filter control",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "CH1CAPPSC": {
+                    "description": "Channel 1 input capture prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CH1MS": {
+                    "description": "Channel 1 mode selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CH0CAPFLT": {
+                    "description": "Channel 0 input capture filter control",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "CH0CAPPSC": {
+                    "description": "Channel 0 input capture prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CH0MS": {
+                    "description": "Channel 0 mode selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CHCTL1_Output": {
+              "description": "Channel control register 1 (output mode)",
+              "offset": 28,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH3COMCEN": {
+                    "description": "Channel 3 output compare clear enable",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CH3COMCTL": {
+                    "description": "Channel 3 compare output control",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "CH3COMSEN": {
+                    "description": "Channel 3 output compare shadow enable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "CH3COMFEN": {
+                    "description": "Channel 3 output compare fast enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CH3MS": {
+                    "description": "Channel 3 mode selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CH2COMCEN": {
+                    "description": "Channel 2 output compare clear enable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CH2COMCTL": {
+                    "description": "Channel 2 compare output control",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "CH2COMSEN": {
+                    "description": "Channel 2 compare output shadow enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH2COMFEN": {
+                    "description": "Channel 2 output compare fast enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH2MS": {
+                    "description": "Channel 2 I/O mode selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CHCTL1_Input": {
+              "description": "Channel control register 1 (input\n          mode)",
+              "offset": 28,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH3CAPFLT": {
+                    "description": "Channel 3 input capture filter control",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "CH3CAPPSC": {
+                    "description": "Channel 3 input capture prescaler",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CH3MS": {
+                    "description": "Channel 3 mode selection",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CH2CAPFLT": {
+                    "description": "Channel 2 input capture filter control",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "CH2CAPPSC": {
+                    "description": "Channel 2 input capture prescaler",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CH2MS": {
+                    "description": "Channel 2 mode selection",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CHCTL2": {
+              "description": "Channel control register 2",
+              "offset": 32,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH3P": {
+                    "description": "Channel 3 capture/compare function polarity",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "CH3EN": {
+                    "description": "Channel 3 capture/compare function enable",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "CH2P": {
+                    "description": "Channel 2 capture/compare function polarity",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CH2EN": {
+                    "description": "Channel 2 capture/compare function enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CH1P": {
+                    "description": "Channel 1 capture/compare function polarity",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CH1EN": {
+                    "description": "Channel 1 capture/compare function enable",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH0P": {
+                    "description": "Channel 0 capture/compare function polarity",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CH0EN": {
+                    "description": "Channel 0 capture/compare function enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CNT": {
+              "description": "Counter register",
+              "offset": 36,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CNT": {
+                    "description": "counter value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "PSC": {
+              "description": "Prescaler register",
+              "offset": 40,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PSC": {
+                    "description": "Prescaler value of the counter clock",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CAR": {
+              "description": "Counter auto reload register",
+              "offset": 44,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CARL": {
+                    "description": "Counter auto reload value",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH0CV": {
+              "description": "Channel 0 capture/compare value register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0VAL": {
+                    "description": "Capture or compare value of channel 0",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH1CV": {
+              "description": "Channel 1 capture/compare value register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH1VAL": {
+                    "description": "Capture or compare value of channel1",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH2CV": {
+              "description": "Channel 2 capture/compare value register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH2VAL": {
+                    "description": "Capture or compare value of channel 2",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH3CV": {
+              "description": "Channel 3 capture/compare value register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH3VAL": {
+                    "description": "Capture or compare value of channel 3",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DMACFG": {
+              "description": "DMA configuration register",
+              "offset": 72,
+              "size": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMATC": {
+                    "description": "DMA transfer count",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DMATA": {
+                    "description": "DMA transfer access start address",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMATB": {
+              "description": "DMA transfer buffer register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMATB": {
+                    "description": "DMA transfer buffer",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  },
+  "devices": {
+    "GD32VF103": {
+      "arch": "cortex_m3",
+      "description": "GD32VF103 RISC-V Microcontroller based device",
+      "properties": {
+        "cpu.nvic_prio_bits": "4",
+        "cpu.mpu": "0",
+        "cpu.fpu": "0",
+        "cpu.revision": "r2p1",
+        "cpu.vendor_systick_config": "0",
+        "license": "\n    Copyright 2019 Sipeed Co.,Ltd.\n  \n    Licensed under the Apache License, Version 2.0 (the \"License\");\n    you may not use this file except in compliance with the License.\n    You may obtain a copy of the License at\n\n        http://www.apache.org/licenses/LICENSE-2.0\n\n    Unless required by applicable law or agreed to in writing, software\n    distributed under the License is distributed on an \"AS IS\" BASIS,\n    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n    See the License for the specific language governing permissions and\n    limitations under the License.\n",
+        "cpu.name": "CM3",
+        "cpu.endian": "little"
+      },
+      "children": {
+        "interrupts": {
+          "MemManageFault": {
+            "index": -12
+          },
+          "BusFault": {
+            "index": -11
+          },
+          "UsageFault": {
+            "index": -10
+          },
+          "DebugMonitor": {
+            "index": -4
+          },
+          "NMI": {
+            "index": -14
+          },
+          "HardFault": {
+            "index": -13
+          },
+          "SVCall": {
+            "index": -5
+          },
+          "PendSV": {
+            "index": -2
+          },
+          "SysTick": {
+            "index": -1
+          },
+          "ADC0_1": {
+            "index": 37
+          },
+          "Tamper": {
+            "index": 21
+          },
+          "CAN0_TX": {
+            "index": 38
+          },
+          "CAN0_RX0": {
+            "index": 39
+          },
+          "CAN0_RX1": {
+            "index": 40
+          },
+          "CAN0_EWMC": {
+            "index": 41
+          },
+          "CAN1_TX": {
+            "index": 82
+          },
+          "CAN1_RX0": {
+            "index": 83
+          },
+          "CAN1_RX1": {
+            "index": 84
+          },
+          "CAN1_EWMC": {
+            "index": 85
+          },
+          "DMA0_Channel0": {
+            "index": 30
+          },
+          "DMA0_Channel1": {
+            "index": 31
+          },
+          "DMA0_Channel2": {
+            "index": 32
+          },
+          "DMA0_Channel3": {
+            "index": 33
+          },
+          "DMA0_Channel4": {
+            "index": 34
+          },
+          "DMA0_Channel5": {
+            "index": 35
+          },
+          "DMA0_Channel6": {
+            "index": 36
+          },
+          "DMA1_Channel0": {
+            "index": 75
+          },
+          "DMA1_Channel1": {
+            "index": 76
+          },
+          "DMA1_Channel2": {
+            "index": 77
+          },
+          "DMA1_Channel3": {
+            "index": 78
+          },
+          "DMA1_Channel4": {
+            "index": 79
+          },
+          "EXTI_Line0": {
+            "index": 25
+          },
+          "EXTI_Line1": {
+            "index": 26
+          },
+          "EXTI_Line2": {
+            "index": 27
+          },
+          "EXTI_Line3": {
+            "index": 28
+          },
+          "EXTI_Line4": {
+            "index": 29
+          },
+          "EXTI_line9_5": {
+            "index": 42
+          },
+          "EXTI_line15_10": {
+            "index": 59
+          },
+          "FMC": {
+            "index": 23
+          },
+          "I2C0_EV": {
+            "index": 50
+          },
+          "I2C0_ER": {
+            "index": 51
+          },
+          "I2C1_EV": {
+            "index": 52
+          },
+          "I2C1_ER": {
+            "index": 53
+          },
+          "RCU": {
+            "index": 24
+          },
+          "RTC": {
+            "index": 22
+          },
+          "RTC_Alarm": {
+            "index": 60
+          },
+          "SPI0": {
+            "index": 54
+          },
+          "SPI1": {
+            "index": 55
+          },
+          "SPI2": {
+            "index": 70
+          },
+          "TIMER0_BRK": {
+            "index": 43
+          },
+          "TIMER0_UP": {
+            "index": 44
+          },
+          "TIMER0_TRG_CMT": {
+            "index": 45
+          },
+          "TIMER0_Channel": {
+            "index": 46
+          },
+          "TIMER1": {
+            "index": 47
+          },
+          "TIMER2": {
+            "index": 48
+          },
+          "TIMER3": {
+            "index": 49
+          },
+          "TIMER4": {
+            "index": 69
+          },
+          "TIMER5": {
+            "index": 73
+          },
+          "TIMER6": {
+            "index": 74
+          },
+          "USART0": {
+            "index": 56
+          },
+          "USART1": {
+            "index": 57
+          },
+          "USART2": {
+            "index": 58
+          },
+          "UART3": {
+            "index": 71
+          },
+          "UART4": {
+            "index": 72
+          },
+          "USBFS_WKUP": {
+            "index": 61
+          },
+          "USBFS": {
+            "index": 86
+          },
+          "WWDGT": {
+            "index": 0
+          }
+        },
+        "peripheral_instances": {
+          "SysTick": {
+            "offset": 3758153744,
+            "type": "types.peripherals.SCS.children.register_groups.SysTick"
+          },
+          "ADC0": {
+            "description": "Analog to digital converter",
+            "offset": 1073816576,
+            "type": "types.peripherals.ADC0"
+          },
+          "ADC1": {
+            "description": "Analog to digital converter",
+            "offset": 1073817600,
+            "type": "types.peripherals.ADC1"
+          },
+          "AFIO": {
+            "description": "Alternate-function I/Os",
+            "offset": 1073807360,
+            "type": "types.peripherals.AFIO"
+          },
+          "BKP": {
+            "description": "Backup registers",
+            "offset": 1073769472,
+            "type": "types.peripherals.BKP"
+          },
+          "CAN0": {
+            "description": "Controller area network",
+            "offset": 1073767424,
+            "type": "types.peripherals.CAN0"
+          },
+          "CAN1": {
+            "offset": 1073768448,
+            "type": "types.peripherals.CAN0"
+          },
+          "CRC": {
+            "description": "cyclic redundancy check calculation unit",
+            "offset": 1073885184,
+            "type": "types.peripherals.CRC"
+          },
+          "DAC": {
+            "description": "Digital-to-analog converter",
+            "offset": 1073771520,
+            "type": "types.peripherals.DAC"
+          },
+          "DBG": {
+            "description": "Debug support",
+            "offset": 3758366720,
+            "type": "types.peripherals.DBG"
+          },
+          "DMA0": {
+            "description": "DMA controller",
+            "offset": 1073872896,
+            "type": "types.peripherals.DMA0"
+          },
+          "DMA1": {
+            "description": "Direct memory access controller",
+            "offset": 1073872896,
+            "type": "types.peripherals.DMA1"
+          },
+          "EXMC": {
+            "description": "External memory controller",
+            "offset": 2684354560,
+            "type": "types.peripherals.EXMC"
+          },
+          "EXTI": {
+            "description": "External interrupt/event\n      controller",
+            "offset": 1073808384,
+            "type": "types.peripherals.EXTI"
+          },
+          "FMC": {
+            "description": "FMC",
+            "offset": 1073881088,
+            "type": "types.peripherals.FMC"
+          },
+          "FWDGT": {
+            "description": "free watchdog timer",
+            "offset": 1073754112,
+            "type": "types.peripherals.FWDGT"
+          },
+          "GPIOA": {
+            "description": "General-purpose I/Os",
+            "offset": 1073809408,
+            "type": "types.peripherals.GPIOA"
+          },
+          "GPIOB": {
+            "offset": 1073810432,
+            "type": "types.peripherals.GPIOA"
+          },
+          "GPIOC": {
+            "offset": 1073811456,
+            "type": "types.peripherals.GPIOA"
+          },
+          "GPIOD": {
+            "offset": 1073812480,
+            "type": "types.peripherals.GPIOA"
+          },
+          "GPIOE": {
+            "offset": 1073813504,
+            "type": "types.peripherals.GPIOA"
+          },
+          "I2C0": {
+            "description": "Inter integrated circuit",
+            "offset": 1073763328,
+            "type": "types.peripherals.I2C0"
+          },
+          "I2C1": {
+            "offset": 1073764352,
+            "type": "types.peripherals.I2C0"
+          },
+          "ECLIC": {
+            "description": "Enhanced Core Local Interrupt Controller",
+            "offset": 3523215360,
+            "type": "types.peripherals.ECLIC"
+          },
+          "PMU": {
+            "description": "Power management unit",
+            "offset": 1073770496,
+            "type": "types.peripherals.PMU"
+          },
+          "RCU": {
+            "description": "Reset and clock unit",
+            "offset": 1073876992,
+            "type": "types.peripherals.RCU"
+          },
+          "RTC": {
+            "description": "Real-time clock",
+            "offset": 1073752064,
+            "type": "types.peripherals.RTC"
+          },
+          "SPI0": {
+            "description": "Serial peripheral interface",
+            "offset": 1073819648,
+            "type": "types.peripherals.SPI0"
+          },
+          "SPI1": {
+            "offset": 1073756160,
+            "type": "types.peripherals.SPI0"
+          },
+          "SPI2": {
+            "offset": 1073757184,
+            "type": "types.peripherals.SPI0"
+          },
+          "TIMER0": {
+            "description": "Advanced-timers",
+            "offset": 1073818624,
+            "type": "types.peripherals.TIMER0"
+          },
+          "TIMER1": {
+            "description": "General-purpose-timers",
+            "offset": 1073741824,
+            "type": "types.peripherals.TIMER1"
+          },
+          "TIMER2": {
+            "offset": 1073742848,
+            "type": "types.peripherals.TIMER1"
+          },
+          "TIMER3": {
+            "offset": 1073743872,
+            "type": "types.peripherals.TIMER1"
+          },
+          "TIMER4": {
+            "offset": 1073744896,
+            "type": "types.peripherals.TIMER1"
+          },
+          "TIMER5": {
+            "description": "Basic-timers",
+            "offset": 1073745920,
+            "type": "types.peripherals.TIMER5"
+          },
+          "TIMER6": {
+            "offset": 1073746944,
+            "type": "types.peripherals.TIMER5"
+          },
+          "USART0": {
+            "description": "Universal synchronous asynchronous receiver\n      transmitter",
+            "offset": 1073821696,
+            "type": "types.peripherals.USART0"
+          },
+          "USART1": {
+            "offset": 1073759232,
+            "type": "types.peripherals.USART0"
+          },
+          "USART2": {
+            "offset": 1073760256,
+            "type": "types.peripherals.USART0"
+          },
+          "UART3": {
+            "description": "Universal  asynchronous receiver\n      transmitter",
+            "offset": 1073761280,
+            "type": "types.peripherals.UART3"
+          },
+          "UART4": {
+            "offset": 1073762304,
+            "type": "types.peripherals.UART3"
+          },
+          "USBFS_GLOBAL": {
+            "description": "USB full speed global registers",
+            "offset": 1342177280,
+            "type": "types.peripherals.USBFS_GLOBAL"
+          },
+          "USBFS_HOST": {
+            "description": "USB on the go full speed host",
+            "offset": 1342178304,
+            "type": "types.peripherals.USBFS_HOST"
+          },
+          "USBFS_DEVICE": {
+            "description": "USB on the go full speed device",
+            "offset": 1342179328,
+            "type": "types.peripherals.USBFS_DEVICE"
+          },
+          "USBFS_PWRCLK": {
+            "description": "USB on the go full speed",
+            "offset": 1342180864,
+            "type": "types.peripherals.USBFS_PWRCLK"
+          },
+          "WWDGT": {
+            "description": "Window watchdog timer",
+            "offset": 1073753088,
+            "type": "types.peripherals.WWDGT"
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/chips/GD32VF103.zig b/src/chips/GD32VF103.zig
new file mode 100644
index 000000000..77618b43e
--- /dev/null
+++ b/src/chips/GD32VF103.zig
@@ -0,0 +1,12849 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    ///  GD32VF103 RISC-V Microcontroller based device
+    pub const GD32VF103 = struct {
+        pub const properties = struct {
+            pub const @"cpu.nvic_prio_bits" = "4";
+            pub const @"cpu.mpu" = "0";
+            pub const @"cpu.fpu" = "0";
+            pub const @"cpu.revision" = "r2p1";
+            pub const @"cpu.vendor_systick_config" = "0";
+            pub const license =
+                \\
+                \\    Copyright 2019 Sipeed Co.,Ltd.
+                \\  
+                \\    Licensed under the Apache License, Version 2.0 (the "License");
+                \\    you may not use this file except in compliance with the License.
+                \\    You may obtain a copy of the License at
+                \\
+                \\        http://www.apache.org/licenses/LICENSE-2.0
+                \\
+                \\    Unless required by applicable law or agreed to in writing, software
+                \\    distributed under the License is distributed on an "AS IS" BASIS,
+                \\    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+                \\    See the License for the specific language governing permissions and
+                \\    limitations under the License.
+                \\
+            ;
+            pub const @"cpu.name" = "CM3";
+            pub const @"cpu.endian" = "little";
+        };
+
+        pub const VectorTable = extern struct {
+            const Handler = micro.interrupt.Handler;
+            const unhandled = micro.interrupt.unhandled;
+
+            initial_stack_pointer: u32,
+            Reset: Handler = unhandled,
+            NMI: Handler = unhandled,
+            HardFault: Handler = unhandled,
+            MemManageFault: Handler = unhandled,
+            BusFault: Handler = unhandled,
+            UsageFault: Handler = unhandled,
+            reserved5: [4]u32 = undefined,
+            SVCall: Handler = unhandled,
+            DebugMonitor: Handler = unhandled,
+            reserved11: [1]u32 = undefined,
+            PendSV: Handler = unhandled,
+            SysTick: Handler = unhandled,
+            WWDGT: Handler = unhandled,
+            reserved15: [20]u32 = undefined,
+            Tamper: Handler = unhandled,
+            RTC: Handler = unhandled,
+            FMC: Handler = unhandled,
+            RCU: Handler = unhandled,
+            EXTI_Line0: Handler = unhandled,
+            EXTI_Line1: Handler = unhandled,
+            EXTI_Line2: Handler = unhandled,
+            EXTI_Line3: Handler = unhandled,
+            EXTI_Line4: Handler = unhandled,
+            DMA0_Channel0: Handler = unhandled,
+            DMA0_Channel1: Handler = unhandled,
+            DMA0_Channel2: Handler = unhandled,
+            DMA0_Channel3: Handler = unhandled,
+            DMA0_Channel4: Handler = unhandled,
+            DMA0_Channel5: Handler = unhandled,
+            DMA0_Channel6: Handler = unhandled,
+            ADC0_1: Handler = unhandled,
+            CAN0_TX: Handler = unhandled,
+            CAN0_RX0: Handler = unhandled,
+            CAN0_RX1: Handler = unhandled,
+            CAN0_EWMC: Handler = unhandled,
+            EXTI_line9_5: Handler = unhandled,
+            TIMER0_BRK: Handler = unhandled,
+            TIMER0_UP: Handler = unhandled,
+            TIMER0_TRG_CMT: Handler = unhandled,
+            TIMER0_Channel: Handler = unhandled,
+            TIMER1: Handler = unhandled,
+            TIMER2: Handler = unhandled,
+            TIMER3: Handler = unhandled,
+            I2C0_EV: Handler = unhandled,
+            I2C0_ER: Handler = unhandled,
+            I2C1_EV: Handler = unhandled,
+            I2C1_ER: Handler = unhandled,
+            SPI0: Handler = unhandled,
+            SPI1: Handler = unhandled,
+            USART0: Handler = unhandled,
+            USART1: Handler = unhandled,
+            USART2: Handler = unhandled,
+            EXTI_line15_10: Handler = unhandled,
+            RTC_Alarm: Handler = unhandled,
+            USBFS_WKUP: Handler = unhandled,
+            reserved76: [7]u32 = undefined,
+            TIMER4: Handler = unhandled,
+            SPI2: Handler = unhandled,
+            UART3: Handler = unhandled,
+            UART4: Handler = unhandled,
+            TIMER5: Handler = unhandled,
+            TIMER6: Handler = unhandled,
+            DMA1_Channel0: Handler = unhandled,
+            DMA1_Channel1: Handler = unhandled,
+            DMA1_Channel2: Handler = unhandled,
+            DMA1_Channel3: Handler = unhandled,
+            DMA1_Channel4: Handler = unhandled,
+            reserved94: [2]u32 = undefined,
+            CAN1_TX: Handler = unhandled,
+            CAN1_RX0: Handler = unhandled,
+            CAN1_RX1: Handler = unhandled,
+            CAN1_EWMC: Handler = unhandled,
+            USBFS: Handler = unhandled,
+        };
+
+        pub const peripherals = struct {
+            ///  General-purpose-timers
+            pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000000);
+            ///  General-purpose-timers
+            pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000400);
+            ///  General-purpose-timers
+            pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000800);
+            ///  General-purpose-timers
+            pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000c00);
+            ///  Basic-timers
+            pub const TIMER5 = @intToPtr(*volatile types.peripherals.TIMER5, 0x40001000);
+            ///  Basic-timers
+            pub const TIMER6 = @intToPtr(*volatile types.peripherals.TIMER5, 0x40001400);
+            ///  Real-time clock
+            pub const RTC = @intToPtr(*volatile types.peripherals.RTC, 0x40002800);
+            ///  Window watchdog timer
+            pub const WWDGT = @intToPtr(*volatile types.peripherals.WWDGT, 0x40002c00);
+            ///  free watchdog timer
+            pub const FWDGT = @intToPtr(*volatile types.peripherals.FWDGT, 0x40003000);
+            ///  Serial peripheral interface
+            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003800);
+            ///  Serial peripheral interface
+            pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003c00);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART1 = @intToPtr(*volatile types.peripherals.USART0, 0x40004400);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART2 = @intToPtr(*volatile types.peripherals.USART0, 0x40004800);
+            ///  Universal asynchronous receiver transmitter
+            pub const UART3 = @intToPtr(*volatile types.peripherals.UART3, 0x40004c00);
+            ///  Universal asynchronous receiver transmitter
+            pub const UART4 = @intToPtr(*volatile types.peripherals.UART3, 0x40005000);
+            ///  Inter integrated circuit
+            pub const I2C0 = @intToPtr(*volatile types.peripherals.I2C0, 0x40005400);
+            ///  Inter integrated circuit
+            pub const I2C1 = @intToPtr(*volatile types.peripherals.I2C0, 0x40005800);
+            ///  Controller area network
+            pub const CAN0 = @intToPtr(*volatile types.peripherals.CAN0, 0x40006400);
+            ///  Controller area network
+            pub const CAN1 = @intToPtr(*volatile types.peripherals.CAN0, 0x40006800);
+            ///  Backup registers
+            pub const BKP = @intToPtr(*volatile types.peripherals.BKP, 0x40006c00);
+            ///  Power management unit
+            pub const PMU = @intToPtr(*volatile types.peripherals.PMU, 0x40007000);
+            ///  Digital-to-analog converter
+            pub const DAC = @intToPtr(*volatile types.peripherals.DAC, 0x40007400);
+            ///  Alternate-function I/Os
+            pub const AFIO = @intToPtr(*volatile types.peripherals.AFIO, 0x40010000);
+            ///  External interrupt/event controller
+            pub const EXTI = @intToPtr(*volatile types.peripherals.EXTI, 0x40010400);
+            ///  General-purpose I/Os
+            pub const GPIOA = @intToPtr(*volatile types.peripherals.GPIOA, 0x40010800);
+            ///  General-purpose I/Os
+            pub const GPIOB = @intToPtr(*volatile types.peripherals.GPIOA, 0x40010c00);
+            ///  General-purpose I/Os
+            pub const GPIOC = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011000);
+            ///  General-purpose I/Os
+            pub const GPIOD = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011400);
+            ///  General-purpose I/Os
+            pub const GPIOE = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011800);
+            ///  Analog to digital converter
+            pub const ADC0 = @intToPtr(*volatile types.peripherals.ADC0, 0x40012400);
+            ///  Analog to digital converter
+            pub const ADC1 = @intToPtr(*volatile types.peripherals.ADC1, 0x40012800);
+            ///  Advanced-timers
+            pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40012c00);
+            ///  Serial peripheral interface
+            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40013000);
+            ///  Universal synchronous asynchronous receiver transmitter
+            pub const USART0 = @intToPtr(*volatile types.peripherals.USART0, 0x40013800);
+            ///  DMA controller
+            pub const DMA0 = @intToPtr(*volatile types.peripherals.DMA0, 0x40020000);
+            ///  Direct memory access controller
+            pub const DMA1 = @intToPtr(*volatile types.peripherals.DMA1, 0x40020000);
+            ///  Reset and clock unit
+            pub const RCU = @intToPtr(*volatile types.peripherals.RCU, 0x40021000);
+            ///  FMC
+            pub const FMC = @intToPtr(*volatile types.peripherals.FMC, 0x40022000);
+            ///  cyclic redundancy check calculation unit
+            pub const CRC = @intToPtr(*volatile types.peripherals.CRC, 0x40023000);
+            ///  USB full speed global registers
+            pub const USBFS_GLOBAL = @intToPtr(*volatile types.peripherals.USBFS_GLOBAL, 0x50000000);
+            ///  USB on the go full speed host
+            pub const USBFS_HOST = @intToPtr(*volatile types.peripherals.USBFS_HOST, 0x50000400);
+            ///  USB on the go full speed device
+            pub const USBFS_DEVICE = @intToPtr(*volatile types.peripherals.USBFS_DEVICE, 0x50000800);
+            ///  USB on the go full speed
+            pub const USBFS_PWRCLK = @intToPtr(*volatile types.peripherals.USBFS_PWRCLK, 0x50000e00);
+            ///  External memory controller
+            pub const EXMC = @intToPtr(*volatile types.peripherals.EXMC, 0xa0000000);
+            ///  Enhanced Core Local Interrupt Controller
+            pub const ECLIC = @intToPtr(*volatile types.peripherals.ECLIC, 0xd2000000);
+            ///  System Tick Timer
+            pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010);
+            ///  Debug support
+            pub const DBG = @intToPtr(*volatile types.peripherals.DBG, 0xe0042000);
+        };
+    };
+};
+
+pub const types = struct {
+    pub const peripherals = struct {
+        ///  System Control Space
+        pub const SCS = struct {
+            ///  System Tick Timer
+            pub const SysTick = extern struct {
+                ///  SysTick Control and Status Register
+                CTRL: mmio.Mmio(packed struct(u32) {
+                    ENABLE: u1,
+                    TICKINT: u1,
+                    CLKSOURCE: u1,
+                    reserved16: u13,
+                    COUNTFLAG: u1,
+                    padding: u15,
+                }),
+                ///  SysTick Reload Value Register
+                LOAD: mmio.Mmio(packed struct(u32) {
+                    RELOAD: u24,
+                    padding: u8,
+                }),
+                ///  SysTick Current Value Register
+                VAL: mmio.Mmio(packed struct(u32) {
+                    CURRENT: u24,
+                    padding: u8,
+                }),
+                ///  SysTick Calibration Register
+                CALIB: mmio.Mmio(packed struct(u32) {
+                    TENMS: u24,
+                    reserved30: u6,
+                    SKEW: u1,
+                    NOREF: u1,
+                }),
+            };
+        };
+
+        ///  Analog to digital converter
+        pub const ADC0 = extern struct {
+            ///  status register
+            STAT: mmio.Mmio(packed struct(u32) {
+                ///  Analog watchdog event flag
+                WDE: u1,
+                ///  End of group conversion flag
+                EOC: u1,
+                ///  End of inserted group conversion flag
+                EOIC: u1,
+                ///  Start flag of inserted channel group
+                STIC: u1,
+                ///  Start flag of regular channel group
+                STRC: u1,
+                padding: u27,
+            }),
+            ///  control register 0
+            CTL0: mmio.Mmio(packed struct(u32) {
+                ///  Analog watchdog channel select
+                WDCHSEL: u5,
+                ///  Interrupt enable for EOC
+                EOCIE: u1,
+                ///  Interrupt enable for WDE
+                WDEIE: u1,
+                ///  Interrupt enable for EOIC
+                EOICIE: u1,
+                ///  Scan mode
+                SM: u1,
+                ///  When in scan mode, analog watchdog is effective on a single channel
+                WDSC: u1,
+                ///  Inserted channel group convert automatically
+                ICA: u1,
+                ///  Discontinuous mode on regular channels
+                DISRC: u1,
+                ///  Discontinuous mode on inserted channels
+                DISIC: u1,
+                ///  Number of conversions in discontinuous mode
+                DISNUM: u3,
+                ///  sync mode selection
+                SYNCM: u4,
+                reserved22: u2,
+                ///  Inserted channel analog watchdog enable
+                IWDEN: u1,
+                ///  Regular channel analog watchdog enable
+                RWDEN: u1,
+                padding: u8,
+            }),
+            ///  control register 1
+            CTL1: mmio.Mmio(packed struct(u32) {
+                ///  ADC on
+                ADCON: u1,
+                ///  Continuous mode
+                CTN: u1,
+                ///  ADC calibration
+                CLB: u1,
+                ///  Reset calibration
+                RSTCLB: u1,
+                reserved8: u4,
+                ///  DMA request enable
+                DMA: u1,
+                reserved11: u2,
+                ///  Data alignment
+                DAL: u1,
+                ///  External trigger select for inserted channel
+                ETSIC: u3,
+                ///  External trigger select for inserted channel
+                ETEIC: u1,
+                reserved17: u1,
+                ///  External trigger select for regular channel
+                ETSRC: u3,
+                ///  External trigger enable for regular channel
+                ETERC: u1,
+                ///  Start on inserted channel
+                SWICST: u1,
+                ///  Start on regular channel
+                SWRCST: u1,
+                ///  Channel 16 and 17 enable of ADC0
+                TSVREN: u1,
+                padding: u8,
+            }),
+            ///  Sample time register 0
+            SAMPT0: mmio.Mmio(packed struct(u32) {
+                ///  Channel 10 sample time selection
+                SPT10: u3,
+                ///  Channel 11 sample time selection
+                SPT11: u3,
+                ///  Channel 12 sample time selection
+                SPT12: u3,
+                ///  Channel 13 sample time selection
+                SPT13: u3,
+                ///  Channel 14 sample time selection
+                SPT14: u3,
+                ///  Channel 15 sample time selection
+                SPT15: u3,
+                ///  Channel 16 sample time selection
+                SPT16: u3,
+                ///  Channel 17 sample time selection
+                SPT17: u3,
+                padding: u8,
+            }),
+            ///  Sample time register 1
+            SAMPT1: mmio.Mmio(packed struct(u32) {
+                ///  Channel 0 sample time selection
+                SPT0: u3,
+                ///  Channel 1 sample time selection
+                SPT1: u3,
+                ///  Channel 2 sample time selection
+                SPT2: u3,
+                ///  Channel 3 sample time selection
+                SPT3: u3,
+                ///  Channel 4 sample time selection
+                SPT4: u3,
+                ///  Channel 5 sample time selection
+                SPT5: u3,
+                ///  Channel 6 sample time selection
+                SPT6: u3,
+                ///  Channel 7 sample time selection
+                SPT7: u3,
+                ///  Channel 8 sample time selection
+                SPT8: u3,
+                ///  Channel 9 sample time selection
+                SPT9: u3,
+                padding: u2,
+            }),
+            ///  Inserted channel data offset register 0
+            IOFF0: mmio.Mmio(packed struct(u32) {
+                ///  Data offset for inserted channel 0
+                IOFF: u12,
+                padding: u20,
+            }),
+            ///  Inserted channel data offset register 1
+            IOFF1: mmio.Mmio(packed struct(u32) {
+                ///  Data offset for inserted channel 1
+                IOFF: u12,
+                padding: u20,
+            }),
+            ///  Inserted channel data offset register 2
+            IOFF2: mmio.Mmio(packed struct(u32) {
+                ///  Data offset for inserted channel 2
+                IOFF: u12,
+                padding: u20,
+            }),
+            ///  Inserted channel data offset register 3
+            IOFF3: mmio.Mmio(packed struct(u32) {
+                ///  Data offset for inserted channel 3
+                IOFF: u12,
+                padding: u20,
+            }),
+            ///  watchdog higher threshold register
+            WDHT: mmio.Mmio(packed struct(u32) {
+                ///  Analog watchdog higher threshold
+                WDHT: u12,
+                padding: u20,
+            }),
+            ///  watchdog lower threshold register
+            WDLT: mmio.Mmio(packed struct(u32) {
+                ///  Analog watchdog lower threshold
+                WDLT: u12,
+                padding: u20,
+            }),
+            ///  regular sequence register 0
+            RSQ0: mmio.Mmio(packed struct(u32) {
+                ///  13th conversion in regular sequence
+                RSQ12: u5,
+                ///  14th conversion in regular sequence
+                RSQ13: u5,
+                ///  15th conversion in regular sequence
+                RSQ14: u5,
+                ///  16th conversion in regular sequence
+                RSQ15: u5,
+                ///  Regular channel group length
+                RL: u4,
+                padding: u8,
+            }),
+            ///  regular sequence register 1
+            RSQ1: mmio.Mmio(packed struct(u32) {
+                ///  7th conversion in regular sequence
+                RSQ6: u5,
+                ///  8th conversion in regular sequence
+                RSQ7: u5,
+                ///  9th conversion in regular sequence
+                RSQ8: u5,
+                ///  10th conversion in regular sequence
+                RSQ9: u5,
+                ///  11th conversion in regular sequence
+                RSQ10: u5,
+                ///  12th conversion in regular sequence
+                RSQ11: u5,
+                padding: u2,
+            }),
+            ///  regular sequence register 2
+            RSQ2: mmio.Mmio(packed struct(u32) {
+                ///  1st conversion in regular sequence
+                RSQ0: u5,
+                ///  2nd conversion in regular sequence
+                RSQ1: u5,
+                ///  3rd conversion in regular sequence
+                RSQ2: u5,
+                ///  4th conversion in regular sequence
+                RSQ3: u5,
+                ///  5th conversion in regular sequence
+                RSQ4: u5,
+                ///  6th conversion in regular sequence
+                RSQ5: u5,
+                padding: u2,
+            }),
+            ///  Inserted sequence register
+            ISQ: mmio.Mmio(packed struct(u32) {
+                ///  1st conversion in inserted sequence
+                ISQ0: u5,
+                ///  2nd conversion in inserted sequence
+                ISQ1: u5,
+                ///  3rd conversion in inserted sequence
+                ISQ2: u5,
+                ///  4th conversion in inserted sequence
+                ISQ3: u5,
+                ///  Inserted channel group length
+                IL: u2,
+                padding: u10,
+            }),
+            ///  Inserted data register 0
+            IDATA0: mmio.Mmio(packed struct(u32) {
+                ///  Inserted number n conversion data
+                IDATAn: u16,
+                padding: u16,
+            }),
+            ///  Inserted data register 1
+            IDATA1: mmio.Mmio(packed struct(u32) {
+                ///  Inserted number n conversion data
+                IDATAn: u16,
+                padding: u16,
+            }),
+            ///  Inserted data register 2
+            IDATA2: mmio.Mmio(packed struct(u32) {
+                ///  Inserted number n conversion data
+                IDATAn: u16,
+                padding: u16,
+            }),
+            ///  Inserted data register 3
+            IDATA3: mmio.Mmio(packed struct(u32) {
+                ///  Inserted number n conversion data
+                IDATAn: u16,
+                padding: u16,
+            }),
+            ///  regular data register
+            RDATA: mmio.Mmio(packed struct(u32) {
+                ///  Regular channel data
+                RDATA: u16,
+                ///  ADC regular channel data
+                ADC1RDTR: u16,
+            }),
+            reserved128: [48]u8,
+            ///  Oversample control register
+            OVSAMPCTL: mmio.Mmio(packed struct(u32) {
+                ///  Oversampler Enable
+                OVSEN: u1,
+                reserved2: u1,
+                ///  Oversampling ratio
+                OVSR: u3,
+                ///  Oversampling shift
+                OVSS: u4,
+                ///  Triggered Oversampling
+                TOVS: u1,
+                reserved12: u2,
+                ///  ADC resolution
+                DRES: u2,
+                padding: u18,
+            }),
+        };
+
+        ///  Analog to digital converter
+        pub const ADC1 = extern struct {
+            ///  status register
+            STAT: mmio.Mmio(packed struct(u32) {
+                ///  Analog watchdog event flag
+                WDE: u1,
+                ///  End of group conversion flag
+                EOC: u1,
+                ///  End of inserted group conversion flag
+                EOIC: u1,
+                ///  Start flag of inserted channel group
+                STIC: u1,
+                ///  Start flag of regular channel group
+                STRC: u1,
+                padding: u27,
+            }),
+            ///  control register 0
+            CTL0: mmio.Mmio(packed struct(u32) {
+                ///  Analog watchdog channel select
+                WDCHSEL: u5,
+                ///  Interrupt enable for EOC
+                EOCIE: u1,
+                ///  Interrupt enable for WDE
+                WDEIE: u1,
+                ///  Interrupt enable for EOIC
+                EOICIE: u1,
+                ///  Scan mode
+                SM: u1,
+                ///  When in scan mode, analog watchdog is effective on a single channel
+                WDSC: u1,
+                ///  Inserted channel group convert automatically
+                ICA: u1,
+                ///  Discontinuous mode on regular channels
+                DISRC: u1,
+                ///  Discontinuous mode on inserted channels
+                DISIC: u1,
+                ///  Number of conversions in discontinuous mode
+                DISNUM: u3,
+                reserved22: u6,
+                ///  Inserted channel analog watchdog enable
+                IWDEN: u1,
+                ///  Regular channel analog watchdog enable
+                RWDEN: u1,
+                padding: u8,
+            }),
+            ///  control register 1
+            CTL1: mmio.Mmio(packed struct(u32) {
+                ///  ADC on
+                ADCON: u1,
+                ///  Continuous mode
+                CTN: u1,
+                ///  ADC calibration
+                CLB: u1,
+                ///  Reset calibration
+                RSTCLB: u1,
+                reserved8: u4,
+                ///  DMA request enable
+                DMA: u1,
+                reserved11: u2,
+                ///  Data alignment
+                DAL: u1,
+                ///  External trigger select for inserted channel
+                ETSIC: u3,
+                ///  External trigger enable for inserted channel
+                ETEIC: u1,
+                reserved17: u1,
+                ///  External trigger select for regular channel
+                ETSRC: u3,
+                ///  External trigger enable for regular channel
+                ETERC: u1,
+                ///  Start on inserted channel
+                SWICST: u1,
+                ///  Start on regular channel
+                SWRCST: u1,
+                padding: u9,
+            }),
+            ///  Sample time register 0
+            SAMPT0: mmio.Mmio(packed struct(u32) {
+                ///  Channel 10 sample time selection
+                SPT10: u3,
+                ///  Channel 11 sample time selection
+                SPT11: u3,
+                ///  Channel 12 sample time selection
+                SPT12: u3,
+                ///  Channel 13 sample time selection
+                SPT13: u3,
+                ///  Channel 14 sample time selection
+                SPT14: u3,
+                ///  Channel 15 sample time selection
+                SPT15: u3,
+                ///  Channel 16 sample time selection
+                SPT16: u3,
+                ///  Channel 17 sample time selection
+                SPT17: u3,
+                padding: u8,
+            }),
+            ///  Sample time register 1
+            SAMPT1: mmio.Mmio(packed struct(u32) {
+                ///  Channel 0 sample time selection
+                SPT0: u3,
+                ///  Channel 1 sample time selection
+                SPT1: u3,
+                ///  Channel 2 sample time selection
+                SPT2: u3,
+                ///  Channel 3 sample time selection
+                SPT3: u3,
+                ///  Channel 4 sample time selection
+                SPT4: u3,
+                ///  Channel 5 sample time selection
+                SPT5: u3,
+                ///  Channel 6 sample time selection
+                SPT6: u3,
+                ///  Channel 7 sample time selection
+                SPT7: u3,
+                ///  Channel 8 sample time selection
+                SPT8: u3,
+                ///  Channel 9 sample time selection
+                SPT9: u3,
+                padding: u2,
+            }),
+            ///  Inserted channel data offset register 0
+            IOFF0: mmio.Mmio(packed struct(u32) {
+                ///  Data offset for inserted channel 0
+                IOFF: u12,
+                padding: u20,
+            }),
+            ///  Inserted channel data offset register 1
+            IOFF1: mmio.Mmio(packed struct(u32) {
+                ///  Data offset for inserted channel 1
+                IOFF: u12,
+                padding: u20,
+            }),
+            ///  Inserted channel data offset register 2
+            IOFF2: mmio.Mmio(packed struct(u32) {
+                ///  Data offset for inserted channel 2
+                IOFF: u12,
+                padding: u20,
+            }),
+            ///  Inserted channel data offset register 3
+            IOFF3: mmio.Mmio(packed struct(u32) {
+                ///  Data offset for inserted channel 3
+                IOFF: u12,
+                padding: u20,
+            }),
+            ///  watchdog higher threshold register
+            WDHT: mmio.Mmio(packed struct(u32) {
+                ///  Analog watchdog higher threshold
+                WDHT: u12,
+                padding: u20,
+            }),
+            ///  watchdog lower threshold register
+            WDLT: mmio.Mmio(packed struct(u32) {
+                ///  Analog watchdog lower threshold
+                WDLT: u12,
+                padding: u20,
+            }),
+            ///  regular sequence register 0
+            RSQ0: mmio.Mmio(packed struct(u32) {
+                ///  13th conversion in regular sequence
+                RSQ12: u5,
+                ///  14th conversion in regular sequence
+                RSQ13: u5,
+                ///  15th conversion in regular sequence
+                RSQ14: u5,
+                ///  16th conversion in regular sequence
+                RSQ15: u5,
+                ///  Regular channel group length
+                RL: u4,
+                padding: u8,
+            }),
+            ///  regular sequence register 1
+            RSQ1: mmio.Mmio(packed struct(u32) {
+                ///  7th conversion in regular sequence
+                RSQ6: u5,
+                ///  8th conversion in regular sequence
+                RSQ7: u5,
+                ///  9th conversion in regular sequence
+                RSQ8: u5,
+                ///  10th conversion in regular sequence
+                RSQ9: u5,
+                ///  11th conversion in regular sequence
+                RSQ10: u5,
+                ///  12th conversion in regular sequence
+                RSQ11: u5,
+                padding: u2,
+            }),
+            ///  regular sequence register 2
+            RSQ2: mmio.Mmio(packed struct(u32) {
+                ///  1st conversion in regular sequence
+                RSQ0: u5,
+                ///  2nd conversion in regular sequence
+                RSQ1: u5,
+                ///  3rd conversion in regular sequence
+                RSQ2: u5,
+                ///  4th conversion in regular sequence
+                RSQ3: u5,
+                ///  5th conversion in regular sequence
+                RSQ4: u5,
+                ///  6th conversion in regular sequence
+                RSQ5: u5,
+                padding: u2,
+            }),
+            ///  Inserted sequence register
+            ISQ: mmio.Mmio(packed struct(u32) {
+                ///  1st conversion in inserted sequence
+                ISQ0: u5,
+                ///  2nd conversion in inserted sequence
+                ISQ1: u5,
+                ///  3rd conversion in inserted sequence
+                ISQ2: u5,
+                ///  4th conversion in inserted sequence
+                ISQ3: u5,
+                ///  Inserted channel group length
+                IL: u2,
+                padding: u10,
+            }),
+            ///  Inserted data register 0
+            IDATA0: mmio.Mmio(packed struct(u32) {
+                ///  Inserted number n conversion data
+                IDATAn: u16,
+                padding: u16,
+            }),
+            ///  Inserted data register 1
+            IDATA1: mmio.Mmio(packed struct(u32) {
+                ///  Inserted number n conversion data
+                IDATAn: u16,
+                padding: u16,
+            }),
+            ///  Inserted data register 2
+            IDATA2: mmio.Mmio(packed struct(u32) {
+                ///  Inserted number n conversion data
+                IDATAn: u16,
+                padding: u16,
+            }),
+            ///  Inserted data register 3
+            IDATA3: mmio.Mmio(packed struct(u32) {
+                ///  Inserted number n conversion data
+                IDATAn: u16,
+                padding: u16,
+            }),
+            ///  regular data register
+            RDATA: mmio.Mmio(packed struct(u32) {
+                ///  Regular channel data
+                RDATA: u16,
+                padding: u16,
+            }),
+        };
+
+        ///  Alternate-function I/Os
+        pub const AFIO = extern struct {
+            ///  Event control register
+            EC: mmio.Mmio(packed struct(u32) {
+                ///  Event output pin selection
+                PIN: u4,
+                ///  Event output port selection
+                PORT: u3,
+                ///  Event output enable
+                EOE: u1,
+                padding: u24,
+            }),
+            ///  AFIO port configuration register 0
+            PCF0: mmio.Mmio(packed struct(u32) {
+                ///  SPI0 remapping
+                SPI0_REMAP: u1,
+                ///  I2C0 remapping
+                I2C0_REMAP: u1,
+                ///  USART0 remapping
+                USART0_REMAP: u1,
+                ///  USART1 remapping
+                USART1_REMAP: u1,
+                ///  USART2 remapping
+                USART2_REMAP: u2,
+                ///  TIMER0 remapping
+                TIMER0_REMAP: u2,
+                ///  TIMER1 remapping
+                TIMER1_REMAP: u2,
+                ///  TIMER2 remapping
+                TIMER2_REMAP: u2,
+                ///  TIMER3 remapping
+                TIMER3_REMAP: u1,
+                ///  CAN0 alternate interface remapping
+                CAN0_REMAP: u2,
+                ///  Port D0/Port D1 mapping on OSC_IN/OSC_OUT
+                PD01_REMAP: u1,
+                ///  TIMER4 channel3 internal remapping
+                TIMER4CH3_IREMAP: u1,
+                reserved22: u5,
+                ///  CAN1 I/O remapping
+                CAN1_REMAP: u1,
+                reserved24: u1,
+                ///  Serial wire JTAG configuration
+                SWJ_CFG: u3,
+                reserved28: u1,
+                ///  SPI2/I2S2 remapping
+                SPI2_REMAP: u1,
+                ///  TIMER1 internal trigger 1 remapping
+                TIMER1ITI1_REMAP: u1,
+                padding: u2,
+            }),
+            ///  EXTI sources selection register 0
+            EXTISS0: mmio.Mmio(packed struct(u32) {
+                ///  EXTI 0 sources selection
+                EXTI0_SS: u4,
+                ///  EXTI 1 sources selection
+                EXTI1_SS: u4,
+                ///  EXTI 2 sources selection
+                EXTI2_SS: u4,
+                ///  EXTI 3 sources selection
+                EXTI3_SS: u4,
+                padding: u16,
+            }),
+            ///  EXTI sources selection register 1
+            EXTISS1: mmio.Mmio(packed struct(u32) {
+                ///  EXTI 4 sources selection
+                EXTI4_SS: u4,
+                ///  EXTI 5 sources selection
+                EXTI5_SS: u4,
+                ///  EXTI 6 sources selection
+                EXTI6_SS: u4,
+                ///  EXTI 7 sources selection
+                EXTI7_SS: u4,
+                padding: u16,
+            }),
+            ///  EXTI sources selection register 2
+            EXTISS2: mmio.Mmio(packed struct(u32) {
+                ///  EXTI 8 sources selection
+                EXTI8_SS: u4,
+                ///  EXTI 9 sources selection
+                EXTI9_SS: u4,
+                ///  EXTI 10 sources selection
+                EXTI10_SS: u4,
+                ///  EXTI 11 sources selection
+                EXTI11_SS: u4,
+                padding: u16,
+            }),
+            ///  EXTI sources selection register 3
+            EXTISS3: mmio.Mmio(packed struct(u32) {
+                ///  EXTI 12 sources selection
+                EXTI12_SS: u4,
+                ///  EXTI 13 sources selection
+                EXTI13_SS: u4,
+                ///  EXTI 14 sources selection
+                EXTI14_SS: u4,
+                ///  EXTI 15 sources selection
+                EXTI15_SS: u4,
+                padding: u16,
+            }),
+            reserved28: [4]u8,
+            ///  AFIO port configuration register 1
+            PCF1: mmio.Mmio(packed struct(u32) {
+                reserved10: u10,
+                ///  EXMC_NADV connect/disconnect
+                EXMC_NADV: u1,
+                padding: u21,
+            }),
+        };
+
+        ///  Backup registers
+        pub const BKP = extern struct {
+            reserved4: [4]u8,
+            ///  Backup data register 0
+            DATA0: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved8: [2]u8,
+            ///  Backup data register 1
+            DATA1: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved12: [2]u8,
+            ///  Backup data register 2
+            DATA2: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved16: [2]u8,
+            ///  Backup data register 3
+            DATA3: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved20: [2]u8,
+            ///  Backup data register 4
+            DATA4: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved24: [2]u8,
+            ///  Backup data register 5
+            DATA5: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved28: [2]u8,
+            ///  Backup data register 6
+            DATA6: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved32: [2]u8,
+            ///  Backup data register 7
+            DATA7: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved36: [2]u8,
+            ///  Backup data register 8
+            DATA8: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved40: [2]u8,
+            ///  Backup data register 9
+            DATA9: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved44: [2]u8,
+            ///  RTC signal output control register
+            OCTL: mmio.Mmio(packed struct(u16) {
+                ///  RTC clock calibration value
+                RCCV: u7,
+                ///  RTC clock calibration output enable
+                COEN: u1,
+                ///  RTC alarm or second signal output enable
+                ASOEN: u1,
+                ///  RTC output selection
+                ROSEL: u1,
+                padding: u6,
+            }),
+            reserved48: [2]u8,
+            ///  Tamper pin control register
+            TPCTL: mmio.Mmio(packed struct(u16) {
+                ///  TAMPER detection enable
+                TPEN: u1,
+                ///  TAMPER pin active level
+                TPAL: u1,
+                padding: u14,
+            }),
+            reserved52: [2]u8,
+            ///  Tamper control and status register
+            TPCS: mmio.Mmio(packed struct(u16) {
+                ///  Tamper event reset
+                TER: u1,
+                ///  Tamper interrupt reset
+                TIR: u1,
+                ///  Tamper interrupt enable
+                TPIE: u1,
+                reserved8: u5,
+                ///  Tamper event flag
+                TEF: u1,
+                ///  Tamper interrupt flag
+                TIF: u1,
+                padding: u6,
+            }),
+            reserved64: [10]u8,
+            ///  Backup data register 10
+            DATA10: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved68: [2]u8,
+            ///  Backup data register 11
+            DATA11: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved72: [2]u8,
+            ///  Backup data register 12
+            DATA12: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved76: [2]u8,
+            ///  Backup data register 13
+            DATA13: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved80: [2]u8,
+            ///  Backup data register 14
+            DATA14: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved84: [2]u8,
+            ///  Backup data register 15
+            DATA15: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved88: [2]u8,
+            ///  Backup data register 16
+            DATA16: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved92: [2]u8,
+            ///  Backup data register 17
+            DATA17: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved96: [2]u8,
+            ///  Backup data register 18
+            DATA18: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved100: [2]u8,
+            ///  Backup data register 19
+            DATA19: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved104: [2]u8,
+            ///  Backup data register 20
+            DATA20: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved108: [2]u8,
+            ///  Backup data register 21
+            DATA21: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved112: [2]u8,
+            ///  Backup data register 22
+            DATA22: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved116: [2]u8,
+            ///  Backup data register 23
+            DATA23: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved120: [2]u8,
+            ///  Backup data register 24
+            DATA24: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved124: [2]u8,
+            ///  Backup data register 25
+            DATA25: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved128: [2]u8,
+            ///  Backup data register 26
+            DATA26: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved132: [2]u8,
+            ///  Backup data register 27
+            DATA27: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved136: [2]u8,
+            ///  Backup data register 28
+            DATA28: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved140: [2]u8,
+            ///  Backup data register 29
+            DATA29: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved144: [2]u8,
+            ///  Backup data register 30
+            DATA30: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved148: [2]u8,
+            ///  Backup data register 31
+            DATA31: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved152: [2]u8,
+            ///  Backup data register 32
+            DATA32: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved156: [2]u8,
+            ///  Backup data register 33
+            DATA33: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved160: [2]u8,
+            ///  Backup data register 34
+            DATA34: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved164: [2]u8,
+            ///  Backup data register 35
+            DATA35: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved168: [2]u8,
+            ///  Backup data register 36
+            DATA36: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved172: [2]u8,
+            ///  Backup data register 37
+            DATA37: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved176: [2]u8,
+            ///  Backup data register 38
+            DATA38: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved180: [2]u8,
+            ///  Backup data register 39
+            DATA39: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved184: [2]u8,
+            ///  Backup data register 40
+            DATA40: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+            reserved188: [2]u8,
+            ///  Backup data register 41
+            DATA41: mmio.Mmio(packed struct(u16) {
+                ///  Backup data
+                DATA: u16,
+            }),
+        };
+
+        ///  Controller area network
+        pub const CAN0 = extern struct {
+            ///  Control register
+            CTL: mmio.Mmio(packed struct(u32) {
+                ///  Initial working mode
+                IWMOD: u1,
+                ///  Sleep working mode
+                SLPWMOD: u1,
+                ///  Transmit FIFO order
+                TFO: u1,
+                ///  Receive FIFO overwrite disable
+                RFOD: u1,
+                ///  Automatic retransmission disable
+                ARD: u1,
+                ///  Automatic wakeup
+                AWU: u1,
+                ///  Automatic bus-off recovery
+                ABOR: u1,
+                ///  Time-triggered communication
+                TTC: u1,
+                reserved15: u7,
+                ///  Software reset
+                SWRST: u1,
+                ///  Debug freeze
+                DFZ: u1,
+                padding: u15,
+            }),
+            ///  Status register
+            STAT: mmio.Mmio(packed struct(u32) {
+                ///  Initial working state
+                IWS: u1,
+                ///  Sleep working state
+                SLPWS: u1,
+                ///  Error interrupt flag
+                ERRIF: u1,
+                ///  Status change interrupt flag of wakeup from sleep working mode
+                WUIF: u1,
+                ///  Status change interrupt flag of sleep working mode entering
+                SLPIF: u1,
+                reserved8: u3,
+                ///  Transmitting state
+                TS: u1,
+                ///  Receiving state
+                RS: u1,
+                ///  Last sample value of RX pin
+                LASTRX: u1,
+                ///  RX level
+                RXL: u1,
+                padding: u20,
+            }),
+            ///  Transmit status register
+            TSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Mailbox 0 transmit finished
+                MTF0: u1,
+                ///  Mailbox 0 transmit finished and no error
+                MTFNERR0: u1,
+                ///  Mailbox 0 arbitration lost
+                MAL0: u1,
+                ///  Mailbox 0 transmit error
+                MTE0: u1,
+                reserved7: u3,
+                ///  Mailbox 0 stop transmitting
+                MST0: u1,
+                ///  Mailbox 1 transmit finished
+                MTF1: u1,
+                ///  Mailbox 1 transmit finished and no error
+                MTFNERR1: u1,
+                ///  Mailbox 1 arbitration lost
+                MAL1: u1,
+                ///  Mailbox 1 transmit error
+                MTE1: u1,
+                reserved15: u3,
+                ///  Mailbox 1 stop transmitting
+                MST1: u1,
+                ///  Mailbox 2 transmit finished
+                MTF2: u1,
+                ///  Mailbox 2 transmit finished and no error
+                MTFNERR2: u1,
+                ///  Mailbox 2 arbitration lost
+                MAL2: u1,
+                ///  Mailbox 2 transmit error
+                MTE2: u1,
+                reserved23: u3,
+                ///  Mailbox 2 stop transmitting
+                MST2: u1,
+                ///  number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty
+                NUM: u2,
+                ///  Transmit mailbox 0 empty
+                TME0: u1,
+                ///  Transmit mailbox 1 empty
+                TME1: u1,
+                ///  Transmit mailbox 2 empty
+                TME2: u1,
+                ///  Transmit mailbox 0 last sending in transmit FIFO
+                TMLS0: u1,
+                ///  Transmit mailbox 1 last sending in transmit FIFO
+                TMLS1: u1,
+                ///  Transmit mailbox 2 last sending in transmit FIFO
+                TMLS2: u1,
+            }),
+            ///  Receive message FIFO0 register
+            RFIFO0: mmio.Mmio(packed struct(u32) {
+                ///  Receive FIFO0 length
+                RFL0: u2,
+                reserved3: u1,
+                ///  Receive FIFO0 full
+                RFF0: u1,
+                ///  Receive FIFO0 overfull
+                RFO0: u1,
+                ///  Receive FIFO0 dequeue
+                RFD0: u1,
+                padding: u26,
+            }),
+            ///  Receive message FIFO1 register
+            RFIFO1: mmio.Mmio(packed struct(u32) {
+                ///  Receive FIFO1 length
+                RFL1: u2,
+                reserved3: u1,
+                ///  Receive FIFO1 full
+                RFF1: u1,
+                ///  Receive FIFO1 overfull
+                RFO1: u1,
+                ///  Receive FIFO1 dequeue
+                RFD1: u1,
+                padding: u26,
+            }),
+            ///  Interrupt enable register
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Transmit mailbox empty interrupt enable
+                TMEIE: u1,
+                ///  Receive FIFO0 not empty interrupt enable
+                RFNEIE0: u1,
+                ///  Receive FIFO0 full interrupt enable
+                RFFIE0: u1,
+                ///  Receive FIFO0 overfull interrupt enable
+                RFOIE0: u1,
+                ///  Receive FIFO1 not empty interrupt enable
+                RFNEIE1: u1,
+                ///  Receive FIFO1 full interrupt enable
+                RFFIE1: u1,
+                ///  Receive FIFO1 overfull interrupt enable
+                RFOIE1: u1,
+                reserved8: u1,
+                ///  Warning error interrupt enable
+                WERRIE: u1,
+                ///  Passive error interrupt enable
+                PERRIE: u1,
+                ///  Bus-off interrupt enable
+                BOIE: u1,
+                ///  Error number interrupt enable
+                ERRNIE: u1,
+                reserved15: u3,
+                ///  Error interrupt enable
+                ERRIE: u1,
+                ///  Wakeup interrupt enable
+                WIE: u1,
+                ///  Sleep working interrupt enable
+                SLPWIE: u1,
+                padding: u14,
+            }),
+            ///  Error register
+            ERR: mmio.Mmio(packed struct(u32) {
+                ///  Warning error
+                WERR: u1,
+                ///  Passive error
+                PERR: u1,
+                ///  Bus-off error
+                BOERR: u1,
+                reserved4: u1,
+                ///  Error number
+                ERRN: u3,
+                reserved16: u9,
+                ///  Transmit Error Count defined by the CAN standard
+                TECNT: u8,
+                ///  Receive Error Count defined by the CAN standard
+                RECNT: u8,
+            }),
+            ///  Bit timing register
+            BT: mmio.Mmio(packed struct(u32) {
+                ///  Baud rate prescaler
+                BAUDPSC: u10,
+                reserved16: u6,
+                ///  Bit segment 1
+                BS1: u4,
+                ///  Bit segment 2
+                BS2: u3,
+                reserved24: u1,
+                ///  Resynchronization jump width
+                SJW: u2,
+                reserved30: u4,
+                ///  Loopback communication mode
+                LCMOD: u1,
+                ///  Silent communication mode
+                SCMOD: u1,
+            }),
+            reserved384: [352]u8,
+            ///  Transmit mailbox identifier register 0
+            TMI0: mmio.Mmio(packed struct(u32) {
+                ///  Transmit enable
+                TEN: u1,
+                ///  Frame type
+                FT: u1,
+                ///  Frame format
+                FF: u1,
+                ///  The frame identifier
+                EFID: u18,
+                ///  The frame identifier
+                SFID_EFID: u11,
+            }),
+            ///  Transmit mailbox property register 0
+            TMP0: mmio.Mmio(packed struct(u32) {
+                ///  Data length code
+                DLENC: u4,
+                reserved8: u4,
+                ///  Time stamp enable
+                TSEN: u1,
+                reserved16: u7,
+                ///  Time stamp
+                TS: u16,
+            }),
+            ///  Transmit mailbox data0 register
+            TMDATA00: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 0
+                DB0: u8,
+                ///  Data byte 1
+                DB1: u8,
+                ///  Data byte 2
+                DB2: u8,
+                ///  Data byte 3
+                DB3: u8,
+            }),
+            ///  Transmit mailbox data1 register
+            TMDATA10: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 4
+                DB4: u8,
+                ///  Data byte 5
+                DB5: u8,
+                ///  Data byte 6
+                DB6: u8,
+                ///  Data byte 7
+                DB7: u8,
+            }),
+            ///  Transmit mailbox identifier register 1
+            TMI1: mmio.Mmio(packed struct(u32) {
+                ///  Transmit enable
+                TEN: u1,
+                ///  Frame type
+                FT: u1,
+                ///  Frame format
+                FF: u1,
+                ///  The frame identifier
+                EFID: u18,
+                ///  The frame identifier
+                SFID_EFID: u11,
+            }),
+            ///  Transmit mailbox property register 1
+            TMP1: mmio.Mmio(packed struct(u32) {
+                ///  Data length code
+                DLENC: u4,
+                reserved8: u4,
+                ///  Time stamp enable
+                TSEN: u1,
+                reserved16: u7,
+                ///  Time stamp
+                TS: u16,
+            }),
+            ///  Transmit mailbox data0 register
+            TMDATA01: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 0
+                DB0: u8,
+                ///  Data byte 1
+                DB1: u8,
+                ///  Data byte 2
+                DB2: u8,
+                ///  Data byte 3
+                DB3: u8,
+            }),
+            ///  Transmit mailbox data1 register
+            TMDATA11: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 4
+                DB4: u8,
+                ///  Data byte 5
+                DB5: u8,
+                ///  Data byte 6
+                DB6: u8,
+                ///  Data byte 7
+                DB7: u8,
+            }),
+            ///  Transmit mailbox identifier register 2
+            TMI2: mmio.Mmio(packed struct(u32) {
+                ///  Transmit enable
+                TEN: u1,
+                ///  Frame type
+                FT: u1,
+                ///  Frame format
+                FF: u1,
+                ///  The frame identifier
+                EFID: u18,
+                ///  The frame identifier
+                SFID_EFID: u11,
+            }),
+            ///  Transmit mailbox property register 2
+            TMP2: mmio.Mmio(packed struct(u32) {
+                ///  Data length code
+                DLENC: u4,
+                reserved8: u4,
+                ///  Time stamp enable
+                TSEN: u1,
+                reserved16: u7,
+                ///  Time stamp
+                TS: u16,
+            }),
+            ///  Transmit mailbox data0 register
+            TMDATA02: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 0
+                DB0: u8,
+                ///  Data byte 1
+                DB1: u8,
+                ///  Data byte 2
+                DB2: u8,
+                ///  Data byte 3
+                DB3: u8,
+            }),
+            ///  Transmit mailbox data1 register
+            TMDATA12: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 4
+                DB4: u8,
+                ///  Data byte 5
+                DB5: u8,
+                ///  Data byte 6
+                DB6: u8,
+                ///  Data byte 7
+                DB7: u8,
+            }),
+            ///  Receive FIFO mailbox identifier register
+            RFIFOMI0: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Frame type
+                FT: u1,
+                ///  Frame format
+                FF: u1,
+                ///  The frame identifier
+                EFID: u18,
+                ///  The frame identifier
+                SFID_EFID: u11,
+            }),
+            ///  Receive FIFO0 mailbox property register
+            RFIFOMP0: mmio.Mmio(packed struct(u32) {
+                ///  Data length code
+                DLENC: u4,
+                reserved8: u4,
+                ///  Filtering index
+                FI: u8,
+                ///  Time stamp
+                TS: u16,
+            }),
+            ///  Receive FIFO0 mailbox data0 register
+            RFIFOMDATA00: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 0
+                DB0: u8,
+                ///  Data byte 1
+                DB1: u8,
+                ///  Data byte 2
+                DB2: u8,
+                ///  Data byte 3
+                DB3: u8,
+            }),
+            ///  Receive FIFO0 mailbox data1 register
+            RFIFOMDATA10: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 4
+                DB4: u8,
+                ///  Data byte 5
+                DB5: u8,
+                ///  Data byte 6
+                DB6: u8,
+                ///  Data byte 7
+                DB7: u8,
+            }),
+            ///  Receive FIFO1 mailbox identifier register
+            RFIFOMI1: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Frame type
+                FT: u1,
+                ///  Frame format
+                FF: u1,
+                ///  The frame identifier
+                EFID: u18,
+                ///  The frame identifier
+                SFID_EFID: u11,
+            }),
+            ///  Receive FIFO1 mailbox property register
+            RFIFOMP1: mmio.Mmio(packed struct(u32) {
+                ///  Data length code
+                DLENC: u4,
+                reserved8: u4,
+                ///  Filtering index
+                FI: u8,
+                ///  Time stamp
+                TS: u16,
+            }),
+            ///  Receive FIFO1 mailbox data0 register
+            RFIFOMDATA01: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 0
+                DB0: u8,
+                ///  Data byte 1
+                DB1: u8,
+                ///  Data byte 2
+                DB2: u8,
+                ///  Data byte 3
+                DB3: u8,
+            }),
+            ///  Receive FIFO1 mailbox data1 register
+            RFIFOMDATA11: mmio.Mmio(packed struct(u32) {
+                ///  Data byte 4
+                DB4: u8,
+                ///  Data byte 5
+                DB5: u8,
+                ///  Data byte 6
+                DB6: u8,
+                ///  Data byte 7
+                DB7: u8,
+            }),
+            reserved512: [48]u8,
+            ///  Filter control register
+            FCTL: mmio.Mmio(packed struct(u32) {
+                ///  Filter lock disable
+                FLD: u1,
+                reserved8: u7,
+                ///  Header bank of CAN1 filter
+                HBC1F: u6,
+                padding: u18,
+            }),
+            ///  Filter mode configuration register
+            FMCFG: mmio.Mmio(packed struct(u32) {
+                ///  Filter mode
+                FMOD0: u1,
+                ///  Filter mode
+                FMOD1: u1,
+                ///  Filter mode
+                FMOD2: u1,
+                ///  Filter mode
+                FMOD3: u1,
+                ///  Filter mode
+                FMOD4: u1,
+                ///  Filter mode
+                FMOD5: u1,
+                ///  Filter mode
+                FMOD6: u1,
+                ///  Filter mode
+                FMOD7: u1,
+                ///  Filter mode
+                FMOD8: u1,
+                ///  Filter mode
+                FMOD9: u1,
+                ///  Filter mode
+                FMOD10: u1,
+                ///  Filter mode
+                FMOD11: u1,
+                ///  Filter mode
+                FMOD12: u1,
+                ///  Filter mode
+                FMOD13: u1,
+                ///  Filter mode
+                FMOD14: u1,
+                ///  Filter mode
+                FMOD15: u1,
+                ///  Filter mode
+                FMOD16: u1,
+                ///  Filter mode
+                FMOD17: u1,
+                ///  Filter mode
+                FMOD18: u1,
+                ///  Filter mode
+                FMOD19: u1,
+                ///  Filter mode
+                FMOD20: u1,
+                ///  Filter mode
+                FMOD21: u1,
+                ///  Filter mode
+                FMOD22: u1,
+                ///  Filter mode
+                FMOD23: u1,
+                ///  Filter mode
+                FMOD24: u1,
+                ///  Filter mode
+                FMOD25: u1,
+                ///  Filter mode
+                FMOD26: u1,
+                ///  Filter mode
+                FMOD27: u1,
+                padding: u4,
+            }),
+            reserved524: [4]u8,
+            ///  Filter scale configuration register
+            FSCFG: mmio.Mmio(packed struct(u32) {
+                ///  Filter scale configuration
+                FS0: u1,
+                ///  Filter scale configuration
+                FS1: u1,
+                ///  Filter scale configuration
+                FS2: u1,
+                ///  Filter scale configuration
+                FS3: u1,
+                ///  Filter scale configuration
+                FS4: u1,
+                ///  Filter scale configuration
+                FS5: u1,
+                ///  Filter scale configuration
+                FS6: u1,
+                ///  Filter scale configuration
+                FS7: u1,
+                ///  Filter scale configuration
+                FS8: u1,
+                ///  Filter scale configuration
+                FS9: u1,
+                ///  Filter scale configuration
+                FS10: u1,
+                ///  Filter scale configuration
+                FS11: u1,
+                ///  Filter scale configuration
+                FS12: u1,
+                ///  Filter scale configuration
+                FS13: u1,
+                ///  Filter scale configuration
+                FS14: u1,
+                ///  Filter scale configuration
+                FS15: u1,
+                ///  Filter scale configuration
+                FS16: u1,
+                ///  Filter scale configuration
+                FS17: u1,
+                ///  Filter scale configuration
+                FS18: u1,
+                ///  Filter scale configuration
+                FS19: u1,
+                ///  Filter scale configuration
+                FS20: u1,
+                ///  Filter scale configuration
+                FS21: u1,
+                ///  Filter scale configuration
+                FS22: u1,
+                ///  Filter scale configuration
+                FS23: u1,
+                ///  Filter scale configuration
+                FS24: u1,
+                ///  Filter scale configuration
+                FS25: u1,
+                ///  Filter scale configuration
+                FS26: u1,
+                ///  Filter scale configuration
+                FS27: u1,
+                padding: u4,
+            }),
+            reserved532: [4]u8,
+            ///  Filter associated FIFO register
+            FAFIFO: mmio.Mmio(packed struct(u32) {
+                ///  Filter 0 associated with FIFO
+                FAF0: u1,
+                ///  Filter 1 associated with FIFO
+                FAF1: u1,
+                ///  Filter 2 associated with FIFO
+                FAF2: u1,
+                ///  Filter 3 associated with FIFO
+                FAF3: u1,
+                ///  Filter 4 associated with FIFO
+                FAF4: u1,
+                ///  Filter 5 associated with FIFO
+                FAF5: u1,
+                ///  Filter 6 associated with FIFO
+                FAF6: u1,
+                ///  Filter 7 associated with FIFO
+                FAF7: u1,
+                ///  Filter 8 associated with FIFO
+                FAF8: u1,
+                ///  Filter 9 associated with FIFO
+                FAF9: u1,
+                ///  Filter 10 associated with FIFO
+                FAF10: u1,
+                ///  Filter 11 associated with FIFO
+                FAF11: u1,
+                ///  Filter 12 associated with FIFO
+                FAF12: u1,
+                ///  Filter 13 associated with FIFO
+                FAF13: u1,
+                ///  Filter 14 associated with FIFO
+                FAF14: u1,
+                ///  Filter 15 associated with FIFO
+                FAF15: u1,
+                ///  Filter 16 associated with FIFO
+                FAF16: u1,
+                ///  Filter 17 associated with FIFO
+                FAF17: u1,
+                ///  Filter 18 associated with FIFO
+                FAF18: u1,
+                ///  Filter 19 associated with FIFO
+                FAF19: u1,
+                ///  Filter 20 associated with FIFO
+                FAF20: u1,
+                ///  Filter 21 associated with FIFO
+                FAF21: u1,
+                ///  Filter 22 associated with FIFO
+                FAF22: u1,
+                ///  Filter 23 associated with FIFO
+                FAF23: u1,
+                ///  Filter 24 associated with FIFO
+                FAF24: u1,
+                ///  Filter 25 associated with FIFO
+                FAF25: u1,
+                ///  Filter 26 associated with FIFO
+                FAF26: u1,
+                ///  Filter 27 associated with FIFO
+                FAF27: u1,
+                padding: u4,
+            }),
+            reserved540: [4]u8,
+            ///  Filter working register
+            FW: mmio.Mmio(packed struct(u32) {
+                ///  Filter working
+                FW0: u1,
+                ///  Filter working
+                FW1: u1,
+                ///  Filter working
+                FW2: u1,
+                ///  Filter working
+                FW3: u1,
+                ///  Filter working
+                FW4: u1,
+                ///  Filter working
+                FW5: u1,
+                ///  Filter working
+                FW6: u1,
+                ///  Filter working
+                FW7: u1,
+                ///  Filter working
+                FW8: u1,
+                ///  Filter working
+                FW9: u1,
+                ///  Filter working
+                FW10: u1,
+                ///  Filter working
+                FW11: u1,
+                ///  Filter working
+                FW12: u1,
+                ///  Filter working
+                FW13: u1,
+                ///  Filter working
+                FW14: u1,
+                ///  Filter working
+                FW15: u1,
+                ///  Filter working
+                FW16: u1,
+                ///  Filter working
+                FW17: u1,
+                ///  Filter working
+                FW18: u1,
+                ///  Filter working
+                FW19: u1,
+                ///  Filter working
+                FW20: u1,
+                ///  Filter working
+                FW21: u1,
+                ///  Filter working
+                FW22: u1,
+                ///  Filter working
+                FW23: u1,
+                ///  Filter working
+                FW24: u1,
+                ///  Filter working
+                FW25: u1,
+                ///  Filter working
+                FW26: u1,
+                ///  Filter working
+                FW27: u1,
+                padding: u4,
+            }),
+            reserved576: [32]u8,
+            ///  Filter 0 data 0 register
+            F0DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 0 data 1 register
+            F0DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 1 data 0 register
+            F1DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 1 data 1 register
+            F1DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 2 data 0 register
+            F2DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 2 data 1 register
+            F2DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 3 data 0 register
+            F3DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 3 data 1 register
+            F3DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 4 data 0 register
+            F4DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 4 data 1 register
+            F4DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 5 data 0 register
+            F5DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 5 data 1 register
+            F5DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 6 data 0 register
+            F6DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 6 data 1 register
+            F6DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 7 data 0 register
+            F7DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 7 data 1 register
+            F7DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 8 data 0 register
+            F8DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 8 data 1 register
+            F8DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 9 data 0 register
+            F9DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 9 data 1 register
+            F9DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 10 data 0 register
+            F10DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 10 data 1 register
+            F10DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 11 data 0 register
+            F11DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 11 data 1 register
+            F11DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 12 data 0 register
+            F12DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 12 data 1 register
+            F12DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 13 data 0 register
+            F13DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 13 data 1 register
+            F13DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 14 data 0 register
+            F14DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 14 data 1 register
+            F14DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 15 data 0 register
+            F15DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 15 data 1 register
+            F15DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 16 data 0 register
+            F16DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 16 data 1 register
+            F16DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 17 data 0 register
+            F17DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 17 data 1 register
+            F17DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 18 data 0 register
+            F18DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 18 data 1 register
+            F18DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 19 data 0 register
+            F19DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 19 data 1 register
+            F19DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 20 data 0 register
+            F20DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 20 data 1 register
+            F20DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 21 data 0 register
+            F21DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 21 data 1 register
+            F21DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 22 data 0 register
+            F22DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 22 data 1 register
+            F22DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 23 data 0 register
+            F23DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 23 data 1 register
+            F23DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 24 data 0 register
+            F24DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 24 data 1 register
+            F24DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 25 data 0 register
+            F25DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 25 data 1 register
+            F25DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 26 data 0 register
+            F26DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 26 data 1 register
+            F26DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 27 data 0 register
+            F27DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+            ///  Filter 27 data 1 register
+            F27DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Filter bits
+                FD0: u1,
+                ///  Filter bits
+                FD1: u1,
+                ///  Filter bits
+                FD2: u1,
+                ///  Filter bits
+                FD3: u1,
+                ///  Filter bits
+                FD4: u1,
+                ///  Filter bits
+                FD5: u1,
+                ///  Filter bits
+                FD6: u1,
+                ///  Filter bits
+                FD7: u1,
+                ///  Filter bits
+                FD8: u1,
+                ///  Filter bits
+                FD9: u1,
+                ///  Filter bits
+                FD10: u1,
+                ///  Filter bits
+                FD11: u1,
+                ///  Filter bits
+                FD12: u1,
+                ///  Filter bits
+                FD13: u1,
+                ///  Filter bits
+                FD14: u1,
+                ///  Filter bits
+                FD15: u1,
+                ///  Filter bits
+                FD16: u1,
+                ///  Filter bits
+                FD17: u1,
+                ///  Filter bits
+                FD18: u1,
+                ///  Filter bits
+                FD19: u1,
+                ///  Filter bits
+                FD20: u1,
+                ///  Filter bits
+                FD21: u1,
+                ///  Filter bits
+                FD22: u1,
+                ///  Filter bits
+                FD23: u1,
+                ///  Filter bits
+                FD24: u1,
+                ///  Filter bits
+                FD25: u1,
+                ///  Filter bits
+                FD26: u1,
+                ///  Filter bits
+                FD27: u1,
+                ///  Filter bits
+                FD28: u1,
+                ///  Filter bits
+                FD29: u1,
+                ///  Filter bits
+                FD30: u1,
+                ///  Filter bits
+                FD31: u1,
+            }),
+        };
+
+        ///  Window watchdog timer
+        pub const WWDGT = extern struct {
+            ///  Control register
+            CTL: mmio.Mmio(packed struct(u32) {
+                ///  7-bit counter
+                CNT: u7,
+                ///  Activation bit
+                WDGTEN: u1,
+                padding: u24,
+            }),
+            ///  Configuration register
+            CFG: mmio.Mmio(packed struct(u32) {
+                ///  7-bit window value
+                WIN: u7,
+                ///  Prescaler
+                PSC: u2,
+                ///  Early wakeup interrupt
+                EWIE: u1,
+                padding: u22,
+            }),
+            ///  Status register
+            STAT: mmio.Mmio(packed struct(u32) {
+                ///  Early wakeup interrupt flag
+                EWIF: u1,
+                padding: u31,
+            }),
+        };
+
+        ///  cyclic redundancy check calculation unit
+        pub const CRC = extern struct {
+            ///  Data register
+            DATA: mmio.Mmio(packed struct(u32) {
+                ///  CRC calculation result bits
+                DATA: u32,
+            }),
+            ///  Free data register
+            FDATA: mmio.Mmio(packed struct(u32) {
+                ///  Free Data Register bits
+                FDATA: u8,
+                padding: u24,
+            }),
+            ///  Control register
+            CTL: mmio.Mmio(packed struct(u32) {
+                ///  reset bit
+                RST: u1,
+                padding: u31,
+            }),
+        };
+
+        ///  Digital-to-analog converter
+        pub const DAC = extern struct {
+            ///  control register
+            CTL: mmio.Mmio(packed struct(u32) {
+                ///  DAC0 enable
+                DEN0: u1,
+                ///  DAC0 output buffer turn off
+                DBOFF0: u1,
+                ///  DAC0 trigger enable
+                DTEN0: u1,
+                ///  DAC0 trigger selection
+                DTSEL0: u3,
+                ///  DAC0 noise wave mode
+                DWM0: u2,
+                ///  DAC0 noise wave bit width
+                DWBW0: u4,
+                ///  DAC0 DMA enable
+                DDMAEN0: u1,
+                reserved16: u3,
+                ///  DAC1 enable
+                DEN1: u1,
+                ///  DAC1 output buffer turn off
+                DBOFF1: u1,
+                ///  DAC1 trigger enable
+                DTEN1: u1,
+                ///  DAC1 trigger selection
+                DTSEL1: u3,
+                ///  DAC1 noise wave mode
+                DWM1: u2,
+                ///  DAC1 noise wave bit width
+                DWBW1: u4,
+                ///  DAC1 DMA enable
+                DDMAEN1: u1,
+                padding: u3,
+            }),
+            ///  software trigger register
+            SWT: mmio.Mmio(packed struct(u32) {
+                ///  DAC0 software trigger
+                SWTR0: u1,
+                ///  DAC1 software trigger
+                SWTR1: u1,
+                padding: u30,
+            }),
+            ///  DAC0 12-bit right-aligned data holding register
+            DAC0_R12DH: mmio.Mmio(packed struct(u32) {
+                ///  DAC0 12-bit right-aligned data
+                DAC0_DH: u12,
+                padding: u20,
+            }),
+            ///  DAC0 12-bit left-aligned data holding register
+            DAC0_L12DH: mmio.Mmio(packed struct(u32) {
+                reserved4: u4,
+                ///  DAC0 12-bit left-aligned data
+                DAC0_DH: u12,
+                padding: u16,
+            }),
+            ///  DAC0 8-bit right aligned data holding register
+            DAC0_R8DH: mmio.Mmio(packed struct(u32) {
+                ///  DAC0 8-bit right-aligned data
+                DAC0_DH: u8,
+                padding: u24,
+            }),
+            ///  DAC1 12-bit right-aligned data holding register
+            DAC1_R12DH: mmio.Mmio(packed struct(u32) {
+                ///  DAC1 12-bit right-aligned data
+                DAC1_DH: u12,
+                padding: u20,
+            }),
+            ///  DAC1 12-bit left aligned data holding register
+            DAC1_L12DH: mmio.Mmio(packed struct(u32) {
+                reserved4: u4,
+                ///  DAC1 12-bit left-aligned data
+                DAC1_DH: u12,
+                padding: u16,
+            }),
+            ///  DAC1 8-bit right aligned data holding register
+            DAC1_R8DH: mmio.Mmio(packed struct(u32) {
+                ///  DAC1 8-bit right-aligned data
+                DAC1_DH: u8,
+                padding: u24,
+            }),
+            ///  DAC concurrent mode 12-bit right-aligned data holding register
+            DACC_R12DH: mmio.Mmio(packed struct(u32) {
+                ///  DAC0 12-bit right-aligned data
+                DAC0_DH: u12,
+                reserved16: u4,
+                ///  DAC1 12-bit right-aligned data
+                DAC1_DH: u12,
+                padding: u4,
+            }),
+            ///  DAC concurrent mode 12-bit left aligned data holding register
+            DACC_L12DH: mmio.Mmio(packed struct(u32) {
+                reserved4: u4,
+                ///  DAC0 12-bit left-aligned data
+                DAC0_DH: u12,
+                reserved20: u4,
+                ///  DAC1 12-bit left-aligned data
+                DAC1_DH: u12,
+            }),
+            ///  DAC concurrent mode 8-bit right aligned data holding register
+            DACC_R8DH: mmio.Mmio(packed struct(u32) {
+                ///  DAC0 8-bit right-aligned data
+                DAC0_DH: u8,
+                ///  DAC1 8-bit right-aligned data
+                DAC1_DH: u8,
+                padding: u16,
+            }),
+            ///  DAC0 data output register
+            DAC0_DO: mmio.Mmio(packed struct(u32) {
+                ///  DAC0 data output
+                DAC0_DO: u12,
+                padding: u20,
+            }),
+            ///  DAC1 data output register
+            DAC1_DO: mmio.Mmio(packed struct(u32) {
+                ///  DAC1 data output
+                DAC1_DO: u12,
+                padding: u20,
+            }),
+        };
+
+        ///  Debug support
+        pub const DBG = extern struct {
+            ///  ID code register
+            ID: mmio.Mmio(packed struct(u32) {
+                ///  DBG ID code register
+                ID_CODE: u32,
+            }),
+            ///  Control register 0
+            CTL: mmio.Mmio(packed struct(u32) {
+                ///  Sleep mode hold register
+                SLP_HOLD: u1,
+                ///  Deep-sleep mode hold register
+                DSLP_HOLD: u1,
+                ///  Standby mode hold register
+                STB_HOLD: u1,
+                reserved8: u5,
+                ///  FWDGT hold bit
+                FWDGT_HOLD: u1,
+                ///  WWDGT hold bit
+                WWDGT_HOLD: u1,
+                ///  TIMER 0 hold bit
+                TIMER0_HOLD: u1,
+                ///  TIMER 1 hold bit
+                TIMER1_HOLD: u1,
+                ///  TIMER 2 hold bit
+                TIMER2_HOLD: u1,
+                ///  TIMER 23 hold bit
+                TIMER3_HOLD: u1,
+                ///  CAN0 hold bit
+                CAN0_HOLD: u1,
+                ///  I2C0 hold bit
+                I2C0_HOLD: u1,
+                ///  I2C1 hold bit
+                I2C1_HOLD: u1,
+                reserved18: u1,
+                ///  TIMER4_HOLD
+                TIMER4_HOLD: u1,
+                ///  TIMER 5 hold bit
+                TIMER5_HOLD: u1,
+                ///  TIMER 6 hold bit
+                TIMER6_HOLD: u1,
+                ///  CAN1 hold bit
+                CAN1_HOLD: u1,
+                padding: u10,
+            }),
+        };
+
+        ///  DMA controller
+        pub const DMA0 = extern struct {
+            ///  Interrupt flag register
+            INTF: mmio.Mmio(packed struct(u32) {
+                ///  Global interrupt flag of channel 0
+                GIF0: u1,
+                ///  Full Transfer finish flag of channe 0
+                FTFIF0: u1,
+                ///  Half transfer finish flag of channel 0
+                HTFIF0: u1,
+                ///  Error flag of channel 0
+                ERRIF0: u1,
+                ///  Global interrupt flag of channel 1
+                GIF1: u1,
+                ///  Full Transfer finish flag of channe 1
+                FTFIF1: u1,
+                ///  Half transfer finish flag of channel 1
+                HTFIF1: u1,
+                ///  Error flag of channel 1
+                ERRIF1: u1,
+                ///  Global interrupt flag of channel 2
+                GIF2: u1,
+                ///  Full Transfer finish flag of channe 2
+                FTFIF2: u1,
+                ///  Half transfer finish flag of channel 2
+                HTFIF2: u1,
+                ///  Error flag of channel 2
+                ERRIF2: u1,
+                ///  Global interrupt flag of channel 3
+                GIF3: u1,
+                ///  Full Transfer finish flag of channe 3
+                FTFIF3: u1,
+                ///  Half transfer finish flag of channel 3
+                HTFIF3: u1,
+                ///  Error flag of channel 3
+                ERRIF3: u1,
+                ///  Global interrupt flag of channel 4
+                GIF4: u1,
+                ///  Full Transfer finish flag of channe 4
+                FTFIF4: u1,
+                ///  Half transfer finish flag of channel 4
+                HTFIF4: u1,
+                ///  Error flag of channel 4
+                ERRIF4: u1,
+                ///  Global interrupt flag of channel 5
+                GIF5: u1,
+                ///  Full Transfer finish flag of channe 5
+                FTFIF5: u1,
+                ///  Half transfer finish flag of channel 5
+                HTFIF5: u1,
+                ///  Error flag of channel 5
+                ERRIF5: u1,
+                ///  Global interrupt flag of channel 6
+                GIF6: u1,
+                ///  Full Transfer finish flag of channe 6
+                FTFIF6: u1,
+                ///  Half transfer finish flag of channel 6
+                HTFIF6: u1,
+                ///  Error flag of channel 6
+                ERRIF6: u1,
+                padding: u4,
+            }),
+            ///  Interrupt flag clear register
+            INTC: mmio.Mmio(packed struct(u32) {
+                ///  Clear global interrupt flag of channel 0
+                GIFC0: u1,
+                ///  Clear bit for full transfer finish flag of channel 0
+                FTFIFC0: u1,
+                ///  Clear bit for half transfer finish flag of channel 0
+                HTFIFC0: u1,
+                ///  Clear bit for error flag of channel 0
+                ERRIFC0: u1,
+                ///  Clear global interrupt flag of channel 1
+                GIFC1: u1,
+                ///  Clear bit for full transfer finish flag of channel 1
+                FTFIFC1: u1,
+                ///  Clear bit for half transfer finish flag of channel 1
+                HTFIFC1: u1,
+                ///  Clear bit for error flag of channel 1
+                ERRIFC1: u1,
+                ///  Clear global interrupt flag of channel 2
+                GIFC2: u1,
+                ///  Clear bit for full transfer finish flag of channel 2
+                FTFIFC2: u1,
+                ///  Clear bit for half transfer finish flag of channel 2
+                HTFIFC2: u1,
+                ///  Clear bit for error flag of channel 2
+                ERRIFC2: u1,
+                ///  Clear global interrupt flag of channel 3
+                GIFC3: u1,
+                ///  Clear bit for full transfer finish flag of channel 3
+                FTFIFC3: u1,
+                ///  Clear bit for half transfer finish flag of channel 3
+                HTFIFC3: u1,
+                ///  Clear bit for error flag of channel 3
+                ERRIFC3: u1,
+                ///  Clear global interrupt flag of channel 4
+                GIFC4: u1,
+                ///  Clear bit for full transfer finish flag of channel 4
+                FTFIFC4: u1,
+                ///  Clear bit for half transfer finish flag of channel 4
+                HTFIFC4: u1,
+                ///  Clear bit for error flag of channel 4
+                ERRIFC4: u1,
+                ///  Clear global interrupt flag of channel 5
+                GIFC5: u1,
+                ///  Clear bit for full transfer finish flag of channel 5
+                FTFIFC5: u1,
+                ///  Clear bit for half transfer finish flag of channel 5
+                HTFIFC5: u1,
+                ///  Clear bit for error flag of channel 5
+                ERRIFC5: u1,
+                ///  Clear global interrupt flag of channel 6
+                GIFC6: u1,
+                ///  Clear bit for full transfer finish flag of channel 6
+                FTFIFC6: u1,
+                ///  Clear bit for half transfer finish flag of channel 6
+                HTFIFC6: u1,
+                ///  Clear bit for error flag of channel 6
+                ERRIFC6: u1,
+                padding: u4,
+            }),
+            ///  Channel 0 control register
+            CH0CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 0 counter register
+            CH0CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 0 peripheral base address register
+            CH0PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 0 memory base address register
+            CH0MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+            reserved28: [4]u8,
+            ///  Channel 1 control register
+            CH1CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 1 counter register
+            CH1CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 1 peripheral base address register
+            CH1PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 1 memory base address register
+            CH1MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+            reserved48: [4]u8,
+            ///  Channel 2 control register
+            CH2CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 2 counter register
+            CH2CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 2 peripheral base address register
+            CH2PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 2 memory base address register
+            CH2MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+            reserved68: [4]u8,
+            ///  Channel 3 control register
+            CH3CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 3 counter register
+            CH3CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 3 peripheral base address register
+            CH3PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 3 memory base address register
+            CH3MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+            reserved88: [4]u8,
+            ///  Channel 4 control register
+            CH4CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 4 counter register
+            CH4CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 4 peripheral base address register
+            CH4PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 4 memory base address register
+            CH4MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+            reserved108: [4]u8,
+            ///  Channel 5 control register
+            CH5CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 5 counter register
+            CH5CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 5 peripheral base address register
+            CH5PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 5 memory base address register
+            CH5MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+            reserved128: [4]u8,
+            ///  Channel 6 control register
+            CH6CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 6 counter register
+            CH6CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 6 peripheral base address register
+            CH6PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 6 memory base address register
+            CH6MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+        };
+
+        ///  Direct memory access controller
+        pub const DMA1 = extern struct {
+            ///  Interrupt flag register
+            INTF: mmio.Mmio(packed struct(u32) {
+                ///  Global interrupt flag of channel 0
+                GIF0: u1,
+                ///  Full Transfer finish flag of channe 0
+                FTFIF0: u1,
+                ///  Half transfer finish flag of channel 0
+                HTFIF0: u1,
+                ///  Error flag of channel 0
+                ERRIF0: u1,
+                ///  Global interrupt flag of channel 1
+                GIF1: u1,
+                ///  Full Transfer finish flag of channe 1
+                FTFIF1: u1,
+                ///  Half transfer finish flag of channel 1
+                HTFIF1: u1,
+                ///  Error flag of channel 1
+                ERRIF1: u1,
+                ///  Global interrupt flag of channel 2
+                GIF2: u1,
+                ///  Full Transfer finish flag of channe 2
+                FTFIF2: u1,
+                ///  Half transfer finish flag of channel 2
+                HTFIF2: u1,
+                ///  Error flag of channel 2
+                ERRIF2: u1,
+                ///  Global interrupt flag of channel 3
+                GIF3: u1,
+                ///  Full Transfer finish flag of channe 3
+                FTFIF3: u1,
+                ///  Half transfer finish flag of channel 3
+                HTFIF3: u1,
+                ///  Error flag of channel 3
+                ERRIF3: u1,
+                ///  Global interrupt flag of channel 4
+                GIF4: u1,
+                ///  Full Transfer finish flag of channe 4
+                FTFIF4: u1,
+                ///  Half transfer finish flag of channel 4
+                HTFIF4: u1,
+                ///  Error flag of channel 4
+                ERRIF4: u1,
+                padding: u12,
+            }),
+            ///  Interrupt flag clear register
+            INTC: mmio.Mmio(packed struct(u32) {
+                ///  Clear global interrupt flag of channel 0
+                GIFC0: u1,
+                ///  Clear bit for full transfer finish flag of channel 0
+                FTFIFC0: u1,
+                ///  Clear bit for half transfer finish flag of channel 0
+                HTFIFC0: u1,
+                ///  Clear bit for error flag of channel 0
+                ERRIFC0: u1,
+                ///  Clear global interrupt flag of channel 1
+                GIFC1: u1,
+                ///  Clear bit for full transfer finish flag of channel 1
+                FTFIFC1: u1,
+                ///  Clear bit for half transfer finish flag of channel 1
+                HTFIFC1: u1,
+                ///  Clear bit for error flag of channel 1
+                ERRIFC1: u1,
+                ///  Clear global interrupt flag of channel 2
+                GIFC2: u1,
+                ///  Clear bit for full transfer finish flag of channel 2
+                FTFIFC2: u1,
+                ///  Clear bit for half transfer finish flag of channel 2
+                HTFIFC2: u1,
+                ///  Clear bit for error flag of channel 2
+                ERRIFC2: u1,
+                ///  Clear global interrupt flag of channel 3
+                GIFC3: u1,
+                ///  Clear bit for full transfer finish flag of channel 3
+                FTFIFC3: u1,
+                ///  Clear bit for half transfer finish flag of channel 3
+                HTFIFC3: u1,
+                ///  Clear bit for error flag of channel 3
+                ERRIFC3: u1,
+                ///  Clear global interrupt flag of channel 4
+                GIFC4: u1,
+                ///  Clear bit for full transfer finish flag of channel 4
+                FTFIFC4: u1,
+                ///  Clear bit for half transfer finish flag of channel 4
+                HTFIFC4: u1,
+                ///  Clear bit for error flag of channel 4
+                ERRIFC4: u1,
+                padding: u12,
+            }),
+            ///  Channel 0 control register
+            CH0CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 0 counter register
+            CH0CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 0 peripheral base address register
+            CH0PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 0 memory base address register
+            CH0MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+            reserved28: [4]u8,
+            ///  Channel 1 control register
+            CH1CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 1 counter register
+            CH1CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 1 peripheral base address register
+            CH1PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 1 memory base address register
+            CH1MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+            reserved48: [4]u8,
+            ///  Channel 2 control register
+            CH2CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 2 counter register
+            CH2CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 2 peripheral base address register
+            CH2PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 2 memory base address register
+            CH2MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+            reserved68: [4]u8,
+            ///  Channel 3 control register
+            CH3CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 3 counter register
+            CH3CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 3 peripheral base address register
+            CH3PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 3 memory base address register
+            CH3MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+            reserved88: [4]u8,
+            ///  Channel 4 control register
+            CH4CTL: mmio.Mmio(packed struct(u32) {
+                ///  Channel enable
+                CHEN: u1,
+                ///  Enable bit for channel full transfer finish interrupt
+                FTFIE: u1,
+                ///  Enable bit for channel half transfer finish interrupt
+                HTFIE: u1,
+                ///  Enable bit for channel error interrupt
+                ERRIE: u1,
+                ///  Transfer direction
+                DIR: u1,
+                ///  Circular mode enable
+                CMEN: u1,
+                ///  Next address generation algorithm of peripheral
+                PNAGA: u1,
+                ///  Next address generation algorithm of memory
+                MNAGA: u1,
+                ///  Transfer data size of peripheral
+                PWIDTH: u2,
+                ///  Transfer data size of memory
+                MWIDTH: u2,
+                ///  Priority level
+                PRIO: u2,
+                ///  Memory to Memory Mode
+                M2M: u1,
+                padding: u17,
+            }),
+            ///  Channel 4 counter register
+            CH4CNT: mmio.Mmio(packed struct(u32) {
+                ///  Transfer counter
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  Channel 4 peripheral base address register
+            CH4PADDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral base address
+                PADDR: u32,
+            }),
+            ///  Channel 4 memory base address register
+            CH4MADDR: mmio.Mmio(packed struct(u32) {
+                ///  Memory base address
+                MADDR: u32,
+            }),
+        };
+
+        ///  External memory controller
+        pub const EXMC = extern struct {
+            ///  SRAM/NOR flash control register 0
+            SNCTL0: mmio.Mmio(packed struct(u32) {
+                ///  NOR bank enable
+                NRBKEN: u1,
+                ///  NOR bank memory address/data multiplexing
+                NRMUX: u1,
+                ///  NOR bank memory type
+                NRTP: u2,
+                ///  NOR bank memory data bus width
+                NRW: u2,
+                ///  NOR Flash access enable
+                NREN: u1,
+                reserved9: u2,
+                ///  NWAIT signal polarity
+                NRWTPOL: u1,
+                reserved12: u2,
+                ///  Write enable
+                WREN: u1,
+                ///  NWAIT signal enable
+                NRWTEN: u1,
+                reserved15: u1,
+                ///  Asynchronous wait
+                ASYNCWAIT: u1,
+                padding: u16,
+            }),
+            ///  SRAM/NOR flash timing configuration register 0
+            SNTCFG0: mmio.Mmio(packed struct(u32) {
+                ///  Address setup time
+                ASET: u4,
+                ///  Address hold time
+                AHLD: u4,
+                ///  Data setup time
+                DSET: u8,
+                ///  Bus latency
+                BUSLAT: u4,
+                padding: u12,
+            }),
+            ///  SRAM/NOR flash control register 1
+            SNCTL1: mmio.Mmio(packed struct(u32) {
+                ///  NOR bank enable
+                NRBKEN: u1,
+                ///  NOR bank memory address/data multiplexing
+                NRMUX: u1,
+                ///  NOR bank memory type
+                NRTP: u2,
+                ///  NOR bank memory data bus width
+                NRW: u2,
+                ///  NOR Flash access enable
+                NREN: u1,
+                reserved9: u2,
+                ///  NWAIT signal polarity
+                NRWTPOL: u1,
+                reserved12: u2,
+                ///  Write enable
+                WREN: u1,
+                ///  NWAIT signal enable
+                NRWTEN: u1,
+                reserved15: u1,
+                ///  Asynchronous wait
+                ASYNCWAIT: u1,
+                padding: u16,
+            }),
+        };
+
+        ///  External interrupt/event controller
+        pub const EXTI = extern struct {
+            ///  Interrupt enable register (EXTI_INTEN)
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable Interrupt on line 0
+                INTEN0: u1,
+                ///  Enable Interrupt on line 1
+                INTEN1: u1,
+                ///  Enable Interrupt on line 2
+                INTEN2: u1,
+                ///  Enable Interrupt on line 3
+                INTEN3: u1,
+                ///  Enable Interrupt on line 4
+                INTEN4: u1,
+                ///  Enable Interrupt on line 5
+                INTEN5: u1,
+                ///  Enable Interrupt on line 6
+                INTEN6: u1,
+                ///  Enable Interrupt on line 7
+                INTEN7: u1,
+                ///  Enable Interrupt on line 8
+                INTEN8: u1,
+                ///  Enable Interrupt on line 9
+                INTEN9: u1,
+                ///  Enable Interrupt on line 10
+                INTEN10: u1,
+                ///  Enable Interrupt on line 11
+                INTEN11: u1,
+                ///  Enable Interrupt on line 12
+                INTEN12: u1,
+                ///  Enable Interrupt on line 13
+                INTEN13: u1,
+                ///  Enable Interrupt on line 14
+                INTEN14: u1,
+                ///  Enable Interrupt on line 15
+                INTEN15: u1,
+                ///  Enable Interrupt on line 16
+                INTEN16: u1,
+                ///  Enable Interrupt on line 17
+                INTEN17: u1,
+                ///  Enable Interrupt on line 18
+                INTEN18: u1,
+                padding: u13,
+            }),
+            ///  Event enable register (EXTI_EVEN)
+            EVEN: mmio.Mmio(packed struct(u32) {
+                ///  Enable Event on line 0
+                EVEN0: u1,
+                ///  Enable Event on line 1
+                EVEN1: u1,
+                ///  Enable Event on line 2
+                EVEN2: u1,
+                ///  Enable Event on line 3
+                EVEN3: u1,
+                ///  Enable Event on line 4
+                EVEN4: u1,
+                ///  Enable Event on line 5
+                EVEN5: u1,
+                ///  Enable Event on line 6
+                EVEN6: u1,
+                ///  Enable Event on line 7
+                EVEN7: u1,
+                ///  Enable Event on line 8
+                EVEN8: u1,
+                ///  Enable Event on line 9
+                EVEN9: u1,
+                ///  Enable Event on line 10
+                EVEN10: u1,
+                ///  Enable Event on line 11
+                EVEN11: u1,
+                ///  Enable Event on line 12
+                EVEN12: u1,
+                ///  Enable Event on line 13
+                EVEN13: u1,
+                ///  Enable Event on line 14
+                EVEN14: u1,
+                ///  Enable Event on line 15
+                EVEN15: u1,
+                ///  Enable Event on line 16
+                EVEN16: u1,
+                ///  Enable Event on line 17
+                EVEN17: u1,
+                ///  Enable Event on line 18
+                EVEN18: u1,
+                padding: u13,
+            }),
+            ///  Rising Edge Trigger Enable register (EXTI_RTEN)
+            RTEN: mmio.Mmio(packed struct(u32) {
+                ///  Rising edge trigger enable of line 0
+                RTEN0: u1,
+                ///  Rising edge trigger enable of line 1
+                RTEN1: u1,
+                ///  Rising edge trigger enable of line 2
+                RTEN2: u1,
+                ///  Rising edge trigger enable of line 3
+                RTEN3: u1,
+                ///  Rising edge trigger enable of line 4
+                RTEN4: u1,
+                ///  Rising edge trigger enable of line 5
+                RTEN5: u1,
+                ///  Rising edge trigger enable of line 6
+                RTEN6: u1,
+                ///  Rising edge trigger enable of line 7
+                RTEN7: u1,
+                ///  Rising edge trigger enable of line 8
+                RTEN8: u1,
+                ///  Rising edge trigger enable of line 9
+                RTEN9: u1,
+                ///  Rising edge trigger enable of line 10
+                RTEN10: u1,
+                ///  Rising edge trigger enable of line 11
+                RTEN11: u1,
+                ///  Rising edge trigger enable of line 12
+                RTEN12: u1,
+                ///  Rising edge trigger enable of line 13
+                RTEN13: u1,
+                ///  Rising edge trigger enable of line 14
+                RTEN14: u1,
+                ///  Rising edge trigger enable of line 15
+                RTEN15: u1,
+                ///  Rising edge trigger enable of line 16
+                RTEN16: u1,
+                ///  Rising edge trigger enable of line 17
+                RTEN17: u1,
+                ///  Rising edge trigger enable of line 18
+                RTEN18: u1,
+                padding: u13,
+            }),
+            ///  Falling Egde Trigger Enable register (EXTI_FTEN)
+            FTEN: mmio.Mmio(packed struct(u32) {
+                ///  Falling edge trigger enable of line 0
+                FTEN0: u1,
+                ///  Falling edge trigger enable of line 1
+                FTEN1: u1,
+                ///  Falling edge trigger enable of line 2
+                FTEN2: u1,
+                ///  Falling edge trigger enable of line 3
+                FTEN3: u1,
+                ///  Falling edge trigger enable of line 4
+                FTEN4: u1,
+                ///  Falling edge trigger enable of line 5
+                FTEN5: u1,
+                ///  Falling edge trigger enable of line 6
+                FTEN6: u1,
+                ///  Falling edge trigger enable of line 7
+                FTEN7: u1,
+                ///  Falling edge trigger enable of line 8
+                FTEN8: u1,
+                ///  Falling edge trigger enable of line 9
+                FTEN9: u1,
+                ///  Falling edge trigger enable of line 10
+                FTEN10: u1,
+                ///  Falling edge trigger enable of line 11
+                FTEN11: u1,
+                ///  Falling edge trigger enable of line 12
+                FTEN12: u1,
+                ///  Falling edge trigger enable of line 13
+                FTEN13: u1,
+                ///  Falling edge trigger enable of line 14
+                FTEN14: u1,
+                ///  Falling edge trigger enable of line 15
+                FTEN15: u1,
+                ///  Falling edge trigger enable of line 16
+                FTEN16: u1,
+                ///  Falling edge trigger enable of line 17
+                FTEN17: u1,
+                ///  Falling edge trigger enable of line 18
+                FTEN18: u1,
+                padding: u13,
+            }),
+            ///  Software interrupt event register (EXTI_SWIEV)
+            SWIEV: mmio.Mmio(packed struct(u32) {
+                ///  Interrupt/Event software trigger on line 0
+                SWIEV0: u1,
+                ///  Interrupt/Event software trigger on line 1
+                SWIEV1: u1,
+                ///  Interrupt/Event software trigger on line 2
+                SWIEV2: u1,
+                ///  Interrupt/Event software trigger on line 3
+                SWIEV3: u1,
+                ///  Interrupt/Event software trigger on line 4
+                SWIEV4: u1,
+                ///  Interrupt/Event software trigger on line 5
+                SWIEV5: u1,
+                ///  Interrupt/Event software trigger on line 6
+                SWIEV6: u1,
+                ///  Interrupt/Event software trigger on line 7
+                SWIEV7: u1,
+                ///  Interrupt/Event software trigger on line 8
+                SWIEV8: u1,
+                ///  Interrupt/Event software trigger on line 9
+                SWIEV9: u1,
+                ///  Interrupt/Event software trigger on line 10
+                SWIEV10: u1,
+                ///  Interrupt/Event software trigger on line 11
+                SWIEV11: u1,
+                ///  Interrupt/Event software trigger on line 12
+                SWIEV12: u1,
+                ///  Interrupt/Event software trigger on line 13
+                SWIEV13: u1,
+                ///  Interrupt/Event software trigger on line 14
+                SWIEV14: u1,
+                ///  Interrupt/Event software trigger on line 15
+                SWIEV15: u1,
+                ///  Interrupt/Event software trigger on line 16
+                SWIEV16: u1,
+                ///  Interrupt/Event software trigger on line 17
+                SWIEV17: u1,
+                ///  Interrupt/Event software trigger on line 18
+                SWIEV18: u1,
+                padding: u13,
+            }),
+            ///  Pending register (EXTI_PD)
+            PD: mmio.Mmio(packed struct(u32) {
+                ///  Interrupt pending status of line 0
+                PD0: u1,
+                ///  Interrupt pending status of line 1
+                PD1: u1,
+                ///  Interrupt pending status of line 2
+                PD2: u1,
+                ///  Interrupt pending status of line 3
+                PD3: u1,
+                ///  Interrupt pending status of line 4
+                PD4: u1,
+                ///  Interrupt pending status of line 5
+                PD5: u1,
+                ///  Interrupt pending status of line 6
+                PD6: u1,
+                ///  Interrupt pending status of line 7
+                PD7: u1,
+                ///  Interrupt pending status of line 8
+                PD8: u1,
+                ///  Interrupt pending status of line 9
+                PD9: u1,
+                ///  Interrupt pending status of line 10
+                PD10: u1,
+                ///  Interrupt pending status of line 11
+                PD11: u1,
+                ///  Interrupt pending status of line 12
+                PD12: u1,
+                ///  Interrupt pending status of line 13
+                PD13: u1,
+                ///  Interrupt pending status of line 14
+                PD14: u1,
+                ///  Interrupt pending status of line 15
+                PD15: u1,
+                ///  Interrupt pending status of line 16
+                PD16: u1,
+                ///  Interrupt pending status of line 17
+                PD17: u1,
+                ///  Interrupt pending status of line 18
+                PD18: u1,
+                padding: u13,
+            }),
+        };
+
+        ///  FMC
+        pub const FMC = extern struct {
+            ///  wait state counter register
+            WS: mmio.Mmio(packed struct(u32) {
+                ///  wait state counter register
+                WSCNT: u3,
+                padding: u29,
+            }),
+            ///  Unlock key register 0
+            KEY0: mmio.Mmio(packed struct(u32) {
+                ///  FMC_CTL0 unlock key
+                KEY: u32,
+            }),
+            ///  Option byte unlock key register
+            OBKEY: mmio.Mmio(packed struct(u32) {
+                ///  FMC_ CTL0 option byte operation unlock register
+                OBKEY: u32,
+            }),
+            ///  Status register 0
+            STAT0: mmio.Mmio(packed struct(u32) {
+                ///  The flash is busy bit
+                BUSY: u1,
+                reserved2: u1,
+                ///  Program error flag bit
+                PGERR: u1,
+                reserved4: u1,
+                ///  Erase/Program protection error flag bit
+                WPERR: u1,
+                ///  End of operation flag bit
+                ENDF: u1,
+                padding: u26,
+            }),
+            ///  Control register 0
+            CTL0: mmio.Mmio(packed struct(u32) {
+                ///  Main flash program for bank0 command bit
+                PG: u1,
+                ///  Main flash page erase for bank0 command bit
+                PER: u1,
+                ///  Main flash mass erase for bank0 command bit
+                MER: u1,
+                reserved4: u1,
+                ///  Option bytes program command bit
+                OBPG: u1,
+                ///  Option bytes erase command bit
+                OBER: u1,
+                ///  Send erase command to FMC bit
+                START: u1,
+                ///  FMC_CTL0 lock bit
+                LK: u1,
+                reserved9: u1,
+                ///  Option byte erase/program enable bit
+                OBWEN: u1,
+                ///  Error interrupt enable bit
+                ERRIE: u1,
+                reserved12: u1,
+                ///  End of operation interrupt enable bit
+                ENDIE: u1,
+                padding: u19,
+            }),
+            ///  Address register 0
+            ADDR0: mmio.Mmio(packed struct(u32) {
+                ///  Flash erase/program command address bits
+                ADDR: u32,
+            }),
+            reserved28: [4]u8,
+            ///  Option byte status register
+            OBSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Option bytes read error bit
+                OBERR: u1,
+                ///  Option bytes security protection code
+                SPC: u1,
+                ///  Store USER of option bytes block after system reset
+                USER: u8,
+                ///  Store DATA[15:0] of option bytes block after system reset
+                DATA: u16,
+                padding: u6,
+            }),
+            ///  Erase/Program Protection register
+            WP: mmio.Mmio(packed struct(u32) {
+                ///  Store WP[31:0] of option bytes block after system reset
+                WP: u32,
+            }),
+            reserved256: [220]u8,
+            ///  Product ID register
+            PID: mmio.Mmio(packed struct(u32) {
+                ///  Product reserved ID code register
+                PID: u32,
+            }),
+        };
+
+        ///  free watchdog timer
+        pub const FWDGT = extern struct {
+            ///  Control register
+            CTL: mmio.Mmio(packed struct(u32) {
+                ///  Key value
+                CMD: u16,
+                padding: u16,
+            }),
+            ///  Prescaler register
+            PSC: mmio.Mmio(packed struct(u32) {
+                ///  Free watchdog timer prescaler selection
+                PSC: u3,
+                padding: u29,
+            }),
+            ///  Reload register
+            RLD: mmio.Mmio(packed struct(u32) {
+                ///  Free watchdog timer counter reload value
+                RLD: u12,
+                padding: u20,
+            }),
+            ///  Status register
+            STAT: mmio.Mmio(packed struct(u32) {
+                ///  Free watchdog timer prescaler value update
+                PUD: u1,
+                ///  Free watchdog timer counter reload value update
+                RUD: u1,
+                padding: u30,
+            }),
+        };
+
+        ///  General-purpose I/Os
+        pub const GPIOA = extern struct {
+            ///  port control register 0
+            CTL0: mmio.Mmio(packed struct(u32) {
+                ///  Port x mode bits (x = 0)
+                MD0: u2,
+                ///  Port x configuration bits (x = 0)
+                CTL0: u2,
+                ///  Port x mode bits (x = 1)
+                MD1: u2,
+                ///  Port x configuration bits (x = 1)
+                CTL1: u2,
+                ///  Port x mode bits (x = 2 )
+                MD2: u2,
+                ///  Port x configuration bits (x = 2)
+                CTL2: u2,
+                ///  Port x mode bits (x = 3 )
+                MD3: u2,
+                ///  Port x configuration bits (x = 3)
+                CTL3: u2,
+                ///  Port x mode bits (x = 4)
+                MD4: u2,
+                ///  Port x configuration bits (x = 4)
+                CTL4: u2,
+                ///  Port x mode bits (x = 5)
+                MD5: u2,
+                ///  Port x configuration bits (x = 5)
+                CTL5: u2,
+                ///  Port x mode bits (x = 6)
+                MD6: u2,
+                ///  Port x configuration bits (x = 6)
+                CTL6: u2,
+                ///  Port x mode bits (x = 7)
+                MD7: u2,
+                ///  Port x configuration bits (x = 7)
+                CTL7: u2,
+            }),
+            ///  port control register 1
+            CTL1: mmio.Mmio(packed struct(u32) {
+                ///  Port x mode bits (x = 8)
+                MD8: u2,
+                ///  Port x configuration bits (x = 8)
+                CTL8: u2,
+                ///  Port x mode bits (x = 9)
+                MD9: u2,
+                ///  Port x configuration bits (x = 9)
+                CTL9: u2,
+                ///  Port x mode bits (x = 10 )
+                MD10: u2,
+                ///  Port x configuration bits (x = 10)
+                CTL10: u2,
+                ///  Port x mode bits (x = 11 )
+                MD11: u2,
+                ///  Port x configuration bits (x = 11)
+                CTL11: u2,
+                ///  Port x mode bits (x = 12)
+                MD12: u2,
+                ///  Port x configuration bits (x = 12)
+                CTL12: u2,
+                ///  Port x mode bits (x = 13)
+                MD13: u2,
+                ///  Port x configuration bits (x = 13)
+                CTL13: u2,
+                ///  Port x mode bits (x = 14)
+                MD14: u2,
+                ///  Port x configuration bits (x = 14)
+                CTL14: u2,
+                ///  Port x mode bits (x = 15)
+                MD15: u2,
+                ///  Port x configuration bits (x = 15)
+                CTL15: u2,
+            }),
+            ///  Port input status register
+            ISTAT: mmio.Mmio(packed struct(u32) {
+                ///  Port input status
+                ISTAT0: u1,
+                ///  Port input status
+                ISTAT1: u1,
+                ///  Port input status
+                ISTAT2: u1,
+                ///  Port input status
+                ISTAT3: u1,
+                ///  Port input status
+                ISTAT4: u1,
+                ///  Port input status
+                ISTAT5: u1,
+                ///  Port input status
+                ISTAT6: u1,
+                ///  Port input status
+                ISTAT7: u1,
+                ///  Port input status
+                ISTAT8: u1,
+                ///  Port input status
+                ISTAT9: u1,
+                ///  Port input status
+                ISTAT10: u1,
+                ///  Port input status
+                ISTAT11: u1,
+                ///  Port input status
+                ISTAT12: u1,
+                ///  Port input status
+                ISTAT13: u1,
+                ///  Port input status
+                ISTAT14: u1,
+                ///  Port input status
+                ISTAT15: u1,
+                padding: u16,
+            }),
+            ///  Port output control register
+            OCTL: mmio.Mmio(packed struct(u32) {
+                ///  Port output control
+                OCTL0: u1,
+                ///  Port output control
+                OCTL1: u1,
+                ///  Port output control
+                OCTL2: u1,
+                ///  Port output control
+                OCTL3: u1,
+                ///  Port output control
+                OCTL4: u1,
+                ///  Port output control
+                OCTL5: u1,
+                ///  Port output control
+                OCTL6: u1,
+                ///  Port output control
+                OCTL7: u1,
+                ///  Port output control
+                OCTL8: u1,
+                ///  Port output control
+                OCTL9: u1,
+                ///  Port output control
+                OCTL10: u1,
+                ///  Port output control
+                OCTL11: u1,
+                ///  Port output control
+                OCTL12: u1,
+                ///  Port output control
+                OCTL13: u1,
+                ///  Port output control
+                OCTL14: u1,
+                ///  Port output control
+                OCTL15: u1,
+                padding: u16,
+            }),
+            ///  Port bit operate register
+            BOP: mmio.Mmio(packed struct(u32) {
+                ///  Port 0 Set bit
+                BOP0: u1,
+                ///  Port 1 Set bit
+                BOP1: u1,
+                ///  Port 2 Set bit
+                BOP2: u1,
+                ///  Port 3 Set bit
+                BOP3: u1,
+                ///  Port 4 Set bit
+                BOP4: u1,
+                ///  Port 5 Set bit
+                BOP5: u1,
+                ///  Port 6 Set bit
+                BOP6: u1,
+                ///  Port 7 Set bit
+                BOP7: u1,
+                ///  Port 8 Set bit
+                BOP8: u1,
+                ///  Port 9 Set bit
+                BOP9: u1,
+                ///  Port 10 Set bit
+                BOP10: u1,
+                ///  Port 11 Set bit
+                BOP11: u1,
+                ///  Port 12 Set bit
+                BOP12: u1,
+                ///  Port 13 Set bit
+                BOP13: u1,
+                ///  Port 14 Set bit
+                BOP14: u1,
+                ///  Port 15 Set bit
+                BOP15: u1,
+                ///  Port 0 Clear bit
+                CR0: u1,
+                ///  Port 1 Clear bit
+                CR1: u1,
+                ///  Port 2 Clear bit
+                CR2: u1,
+                ///  Port 3 Clear bit
+                CR3: u1,
+                ///  Port 4 Clear bit
+                CR4: u1,
+                ///  Port 5 Clear bit
+                CR5: u1,
+                ///  Port 6 Clear bit
+                CR6: u1,
+                ///  Port 7 Clear bit
+                CR7: u1,
+                ///  Port 8 Clear bit
+                CR8: u1,
+                ///  Port 9 Clear bit
+                CR9: u1,
+                ///  Port 10 Clear bit
+                CR10: u1,
+                ///  Port 11 Clear bit
+                CR11: u1,
+                ///  Port 12 Clear bit
+                CR12: u1,
+                ///  Port 13 Clear bit
+                CR13: u1,
+                ///  Port 14 Clear bit
+                CR14: u1,
+                ///  Port 15 Clear bit
+                CR15: u1,
+            }),
+            ///  Port bit clear register
+            BC: mmio.Mmio(packed struct(u32) {
+                ///  Port 0 Clear bit
+                CR0: u1,
+                ///  Port 1 Clear bit
+                CR1: u1,
+                ///  Port 2 Clear bit
+                CR2: u1,
+                ///  Port 3 Clear bit
+                CR3: u1,
+                ///  Port 4 Clear bit
+                CR4: u1,
+                ///  Port 5 Clear bit
+                CR5: u1,
+                ///  Port 6 Clear bit
+                CR6: u1,
+                ///  Port 7 Clear bit
+                CR7: u1,
+                ///  Port 8 Clear bit
+                CR8: u1,
+                ///  Port 9 Clear bit
+                CR9: u1,
+                ///  Port 10 Clear bit
+                CR10: u1,
+                ///  Port 11 Clear bit
+                CR11: u1,
+                ///  Port 12 Clear bit
+                CR12: u1,
+                ///  Port 13 Clear bit
+                CR13: u1,
+                ///  Port 14 Clear bit
+                CR14: u1,
+                ///  Port 15 Clear bit
+                CR15: u1,
+                padding: u16,
+            }),
+            ///  GPIO port configuration lock register
+            LOCK: mmio.Mmio(packed struct(u32) {
+                ///  Port Lock bit 0
+                LK0: u1,
+                ///  Port Lock bit 1
+                LK1: u1,
+                ///  Port Lock bit 2
+                LK2: u1,
+                ///  Port Lock bit 3
+                LK3: u1,
+                ///  Port Lock bit 4
+                LK4: u1,
+                ///  Port Lock bit 5
+                LK5: u1,
+                ///  Port Lock bit 6
+                LK6: u1,
+                ///  Port Lock bit 7
+                LK7: u1,
+                ///  Port Lock bit 8
+                LK8: u1,
+                ///  Port Lock bit 9
+                LK9: u1,
+                ///  Port Lock bit 10
+                LK10: u1,
+                ///  Port Lock bit 11
+                LK11: u1,
+                ///  Port Lock bit 12
+                LK12: u1,
+                ///  Port Lock bit 13
+                LK13: u1,
+                ///  Port Lock bit 14
+                LK14: u1,
+                ///  Port Lock bit 15
+                LK15: u1,
+                ///  Lock sequence key
+                LKK: u1,
+                padding: u15,
+            }),
+        };
+
+        ///  USB on the go full speed
+        pub const USBFS_PWRCLK = extern struct {
+            ///  power and clock gating control register (PWRCLKCTL)
+            PWRCLKCTL: mmio.Mmio(packed struct(u32) {
+                ///  Stop the USB clock
+                SUCLK: u1,
+                ///  Stop HCLK
+                SHCLK: u1,
+                padding: u30,
+            }),
+        };
+
+        ///  USB on the go full speed device
+        pub const USBFS_DEVICE = extern struct {
+            ///  device configuration register (DCFG)
+            DCFG: mmio.Mmio(packed struct(u32) {
+                ///  Device speed
+                DS: u2,
+                ///  Non-zero-length status OUT handshake
+                NZLSOH: u1,
+                reserved4: u1,
+                ///  Device address
+                DAR: u7,
+                ///  end of periodic frame time
+                EOPFT: u2,
+                padding: u19,
+            }),
+            ///  device control register (DCTL)
+            DCTL: mmio.Mmio(packed struct(u32) {
+                ///  Remote wakeup
+                RWKUP: u1,
+                ///  Soft disconnect
+                SD: u1,
+                ///  Global IN NAK status
+                GINS: u1,
+                ///  Global OUT NAK status
+                GONS: u1,
+                reserved7: u3,
+                ///  Set global IN NAK
+                SGINAK: u1,
+                ///  Clear global IN NAK
+                CGINAK: u1,
+                ///  Set global OUT NAK
+                SGONAK: u1,
+                ///  Clear global OUT NAK
+                CGONAK: u1,
+                ///  Power-on initialization flag
+                POIF: u1,
+                padding: u20,
+            }),
+            ///  device status register (DSTAT)
+            DSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Suspend status
+                SPST: u1,
+                ///  Enumerated speed
+                ES: u2,
+                reserved8: u5,
+                ///  Frame number of the received SOF
+                FNRSOF: u14,
+                padding: u10,
+            }),
+            reserved16: [4]u8,
+            ///  device IN endpoint common interrupt mask register (DIEPINTEN)
+            DIEPINTEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished interrupt enable
+                TFEN: u1,
+                ///  Endpoint disabled interrupt enable
+                EPDISEN: u1,
+                reserved3: u1,
+                ///  Control IN timeout condition interrupt enable (Non-isochronous endpoints)
+                CITOEN: u1,
+                ///  Endpoint Tx FIFO underrun interrupt enable bit
+                EPTXFUDEN: u1,
+                reserved6: u1,
+                ///  IN endpoint NAK effective interrupt enable
+                IEPNEEN: u1,
+                padding: u25,
+            }),
+            ///  device OUT endpoint common interrupt enable register (DOEPINTEN)
+            DOEPINTEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished interrupt enable
+                TFEN: u1,
+                ///  Endpoint disabled interrupt enable
+                EPDISEN: u1,
+                reserved3: u1,
+                ///  SETUP phase finished interrupt enable
+                STPFEN: u1,
+                ///  Endpoint Rx FIFO overrun interrupt enable
+                EPRXFOVREN: u1,
+                reserved6: u1,
+                ///  Back-to-back SETUP packets interrupt enable
+                BTBSTPEN: u1,
+                padding: u25,
+            }),
+            ///  device all endpoints interrupt register (DAEPINT)
+            DAEPINT: mmio.Mmio(packed struct(u32) {
+                ///  Device all IN endpoint interrupt bits
+                IEPITB: u4,
+                reserved16: u12,
+                ///  Device all OUT endpoint interrupt bits
+                OEPITB: u4,
+                padding: u12,
+            }),
+            ///  Device all endpoints interrupt enable register (DAEPINTEN)
+            DAEPINTEN: mmio.Mmio(packed struct(u32) {
+                ///  IN EP interrupt interrupt enable bits
+                IEPIE: u4,
+                reserved16: u12,
+                ///  OUT endpoint interrupt enable bits
+                OEPIE: u4,
+                padding: u12,
+            }),
+            reserved40: [8]u8,
+            ///  device VBUS discharge time register
+            DVBUSDT: mmio.Mmio(packed struct(u32) {
+                ///  Device VBUS discharge time
+                DVBUSDT: u16,
+                padding: u16,
+            }),
+            ///  device VBUS pulsing time register
+            DVBUSPT: mmio.Mmio(packed struct(u32) {
+                ///  Device VBUS pulsing time
+                DVBUSPT: u12,
+                padding: u20,
+            }),
+            reserved52: [4]u8,
+            ///  device IN endpoint FIFO empty interrupt enable register
+            DIEPFEINTEN: mmio.Mmio(packed struct(u32) {
+                ///  IN EP Tx FIFO empty interrupt enable bits
+                IEPTXFEIE: u4,
+                padding: u28,
+            }),
+            reserved256: [200]u8,
+            ///  device IN endpoint 0 control register (DIEP0CTL)
+            DIEP0CTL: mmio.Mmio(packed struct(u32) {
+                ///  Maximum packet length
+                MPL: u2,
+                reserved15: u13,
+                ///  endpoint active
+                EPACT: u1,
+                reserved17: u1,
+                ///  NAK status
+                NAKS: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved21: u1,
+                ///  STALL handshake
+                STALL: u1,
+                ///  TxFIFO number
+                TXFNUM: u4,
+                ///  Clear NAK
+                CNAK: u1,
+                ///  Set NAK
+                SNAK: u1,
+                reserved30: u2,
+                ///  Endpoint disable
+                EPD: u1,
+                ///  Endpoint enable
+                EPEN: u1,
+            }),
+            reserved264: [4]u8,
+            ///  device endpoint-0 interrupt register
+            DIEP0INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Endpoint finished
+                EPDIS: u1,
+                reserved3: u1,
+                ///  Control in timeout interrupt
+                CITO: u1,
+                ///  Endpoint Tx FIFO underrun
+                EPTXFUD: u1,
+                reserved6: u1,
+                ///  IN endpoint NAK effective
+                IEPNE: u1,
+                ///  Transmit FIFO empty
+                TXFE: u1,
+                padding: u24,
+            }),
+            reserved272: [4]u8,
+            ///  device IN endpoint-0 transfer length register
+            DIEP0LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u7,
+                reserved19: u12,
+                ///  Packet count
+                PCNT: u2,
+                padding: u11,
+            }),
+            reserved280: [4]u8,
+            ///  device IN endpoint 0 transmit FIFO status register
+            DIEP0TFSTAT: mmio.Mmio(packed struct(u32) {
+                ///  IN endpoint TxFIFO space remaining
+                IEPTFS: u16,
+                padding: u16,
+            }),
+            reserved288: [4]u8,
+            ///  device in endpoint-1 control register
+            DIEP1CTL: mmio.Mmio(packed struct(u32) {
+                ///  maximum packet length
+                MPL: u11,
+                reserved15: u4,
+                ///  Endpoint active
+                EPACT: u1,
+                ///  EOFRM/DPID
+                EOFRM_DPID: u1,
+                ///  NAK status
+                NAKS: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved21: u1,
+                ///  STALL handshake
+                STALL: u1,
+                ///  Tx FIFO number
+                TXFNUM: u4,
+                ///  Clear NAK
+                CNAK: u1,
+                ///  Set NAK
+                SNAK: u1,
+                ///  SD0PID/SEVNFRM
+                SD0PID_SEVENFRM: u1,
+                ///  Set DATA1 PID/Set odd frame
+                SD1PID_SODDFRM: u1,
+                ///  Endpoint disable
+                EPD: u1,
+                ///  Endpoint enable
+                EPEN: u1,
+            }),
+            reserved296: [4]u8,
+            ///  device endpoint-1 interrupt register
+            DIEP1INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Endpoint finished
+                EPDIS: u1,
+                reserved3: u1,
+                ///  Control in timeout interrupt
+                CITO: u1,
+                ///  Endpoint Tx FIFO underrun
+                EPTXFUD: u1,
+                reserved6: u1,
+                ///  IN endpoint NAK effective
+                IEPNE: u1,
+                ///  Transmit FIFO empty
+                TXFE: u1,
+                padding: u24,
+            }),
+            reserved304: [4]u8,
+            ///  device IN endpoint-1 transfer length register
+            DIEP1LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  Multi packet count per frame
+                MCPF: u2,
+                padding: u1,
+            }),
+            reserved312: [4]u8,
+            ///  device IN endpoint 1 transmit FIFO status register
+            DIEP1TFSTAT: mmio.Mmio(packed struct(u32) {
+                ///  IN endpoint TxFIFO space remaining
+                IEPTFS: u16,
+                padding: u16,
+            }),
+            reserved320: [4]u8,
+            ///  device endpoint-2 control register
+            DIEP2CTL: mmio.Mmio(packed struct(u32) {
+                ///  maximum packet length
+                MPL: u11,
+                reserved15: u4,
+                ///  Endpoint active
+                EPACT: u1,
+                ///  EOFRM/DPID
+                EOFRM_DPID: u1,
+                ///  NAK status
+                NAKS: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved21: u1,
+                ///  STALL handshake
+                STALL: u1,
+                ///  Tx FIFO number
+                TXFNUM: u4,
+                ///  Clear NAK
+                CNAK: u1,
+                ///  Set NAK
+                SNAK: u1,
+                ///  SD0PID/SEVNFRM
+                SD0PID_SEVENFRM: u1,
+                ///  Set DATA1 PID/Set odd frame
+                SD1PID_SODDFRM: u1,
+                ///  Endpoint disable
+                EPD: u1,
+                ///  Endpoint enable
+                EPEN: u1,
+            }),
+            reserved328: [4]u8,
+            ///  device endpoint-2 interrupt register
+            DIEP2INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Endpoint finished
+                EPDIS: u1,
+                reserved3: u1,
+                ///  Control in timeout interrupt
+                CITO: u1,
+                ///  Endpoint Tx FIFO underrun
+                EPTXFUD: u1,
+                reserved6: u1,
+                ///  IN endpoint NAK effective
+                IEPNE: u1,
+                ///  Transmit FIFO empty
+                TXFE: u1,
+                padding: u24,
+            }),
+            reserved336: [4]u8,
+            ///  device IN endpoint-2 transfer length register
+            DIEP2LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  Multi packet count per frame
+                MCPF: u2,
+                padding: u1,
+            }),
+            reserved344: [4]u8,
+            ///  device IN endpoint 2 transmit FIFO status register
+            DIEP2TFSTAT: mmio.Mmio(packed struct(u32) {
+                ///  IN endpoint TxFIFO space remaining
+                IEPTFS: u16,
+                padding: u16,
+            }),
+            reserved352: [4]u8,
+            ///  device endpoint-3 control register
+            DIEP3CTL: mmio.Mmio(packed struct(u32) {
+                ///  maximum packet length
+                MPL: u11,
+                reserved15: u4,
+                ///  Endpoint active
+                EPACT: u1,
+                ///  EOFRM/DPID
+                EOFRM_DPID: u1,
+                ///  NAK status
+                NAKS: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved21: u1,
+                ///  STALL handshake
+                STALL: u1,
+                ///  Tx FIFO number
+                TXFNUM: u4,
+                ///  Clear NAK
+                CNAK: u1,
+                ///  Set NAK
+                SNAK: u1,
+                ///  SD0PID/SEVNFRM
+                SD0PID_SEVENFRM: u1,
+                ///  Set DATA1 PID/Set odd frame
+                SD1PID_SODDFRM: u1,
+                ///  Endpoint disable
+                EPD: u1,
+                ///  Endpoint enable
+                EPEN: u1,
+            }),
+            reserved360: [4]u8,
+            ///  device endpoint-3 interrupt register
+            DIEP3INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Endpoint finished
+                EPDIS: u1,
+                reserved3: u1,
+                ///  Control in timeout interrupt
+                CITO: u1,
+                ///  Endpoint Tx FIFO underrun
+                EPTXFUD: u1,
+                reserved6: u1,
+                ///  IN endpoint NAK effective
+                IEPNE: u1,
+                ///  Transmit FIFO empty
+                TXFE: u1,
+                padding: u24,
+            }),
+            reserved368: [4]u8,
+            ///  device IN endpoint-3 transfer length register
+            DIEP3LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  Multi packet count per frame
+                MCPF: u2,
+                padding: u1,
+            }),
+            reserved376: [4]u8,
+            ///  device IN endpoint 3 transmit FIFO status register
+            DIEP3TFSTAT: mmio.Mmio(packed struct(u32) {
+                ///  IN endpoint TxFIFO space remaining
+                IEPTFS: u16,
+                padding: u16,
+            }),
+            reserved768: [388]u8,
+            ///  device endpoint-0 control register
+            DOEP0CTL: mmio.Mmio(packed struct(u32) {
+                ///  Maximum packet length
+                MPL: u2,
+                reserved15: u13,
+                ///  Endpoint active
+                EPACT: u1,
+                reserved17: u1,
+                ///  NAK status
+                NAKS: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                ///  Snoop mode
+                SNOOP: u1,
+                ///  STALL handshake
+                STALL: u1,
+                reserved26: u4,
+                ///  Clear NAK
+                CNAK: u1,
+                ///  Set NAK
+                SNAK: u1,
+                reserved30: u2,
+                ///  Endpoint disable
+                EPD: u1,
+                ///  Endpoint enable
+                EPEN: u1,
+            }),
+            reserved776: [4]u8,
+            ///  device out endpoint-0 interrupt flag register
+            DOEP0INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Endpoint disabled
+                EPDIS: u1,
+                reserved3: u1,
+                ///  Setup phase finished
+                STPF: u1,
+                ///  Endpoint Rx FIFO overrun
+                EPRXFOVR: u1,
+                reserved6: u1,
+                ///  Back-to-back SETUP packets
+                BTBSTP: u1,
+                padding: u25,
+            }),
+            reserved784: [4]u8,
+            ///  device OUT endpoint-0 transfer length register
+            DOEP0LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u7,
+                reserved19: u12,
+                ///  Packet count
+                PCNT: u1,
+                reserved29: u9,
+                ///  SETUP packet count
+                STPCNT: u2,
+                padding: u1,
+            }),
+            reserved800: [12]u8,
+            ///  device endpoint-1 control register
+            DOEP1CTL: mmio.Mmio(packed struct(u32) {
+                ///  maximum packet length
+                MPL: u11,
+                reserved15: u4,
+                ///  Endpoint active
+                EPACT: u1,
+                ///  EOFRM/DPID
+                EOFRM_DPID: u1,
+                ///  NAK status
+                NAKS: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                ///  Snoop mode
+                SNOOP: u1,
+                ///  STALL handshake
+                STALL: u1,
+                reserved26: u4,
+                ///  Clear NAK
+                CNAK: u1,
+                ///  Set NAK
+                SNAK: u1,
+                ///  SD0PID/SEVENFRM
+                SD0PID_SEVENFRM: u1,
+                ///  SD1PID/SODDFRM
+                SD1PID_SODDFRM: u1,
+                ///  Endpoint disable
+                EPD: u1,
+                ///  Endpoint enable
+                EPEN: u1,
+            }),
+            reserved808: [4]u8,
+            ///  device out endpoint-1 interrupt flag register
+            DOEP1INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Endpoint disabled
+                EPDIS: u1,
+                reserved3: u1,
+                ///  Setup phase finished
+                STPF: u1,
+                ///  Endpoint Rx FIFO overrun
+                EPRXFOVR: u1,
+                reserved6: u1,
+                ///  Back-to-back SETUP packets
+                BTBSTP: u1,
+                padding: u25,
+            }),
+            reserved816: [4]u8,
+            ///  device OUT endpoint-1 transfer length register
+            DOEP1LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  SETUP packet count/Received data PID
+                STPCNT_RXDPID: u2,
+                padding: u1,
+            }),
+            reserved832: [12]u8,
+            ///  device endpoint-2 control register
+            DOEP2CTL: mmio.Mmio(packed struct(u32) {
+                ///  maximum packet length
+                MPL: u11,
+                reserved15: u4,
+                ///  Endpoint active
+                EPACT: u1,
+                ///  EOFRM/DPID
+                EOFRM_DPID: u1,
+                ///  NAK status
+                NAKS: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                ///  Snoop mode
+                SNOOP: u1,
+                ///  STALL handshake
+                STALL: u1,
+                reserved26: u4,
+                ///  Clear NAK
+                CNAK: u1,
+                ///  Set NAK
+                SNAK: u1,
+                ///  SD0PID/SEVENFRM
+                SD0PID_SEVENFRM: u1,
+                ///  SD1PID/SODDFRM
+                SD1PID_SODDFRM: u1,
+                ///  Endpoint disable
+                EPD: u1,
+                ///  Endpoint enable
+                EPEN: u1,
+            }),
+            reserved840: [4]u8,
+            ///  device out endpoint-2 interrupt flag register
+            DOEP2INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Endpoint disabled
+                EPDIS: u1,
+                reserved3: u1,
+                ///  Setup phase finished
+                STPF: u1,
+                ///  Endpoint Rx FIFO overrun
+                EPRXFOVR: u1,
+                reserved6: u1,
+                ///  Back-to-back SETUP packets
+                BTBSTP: u1,
+                padding: u25,
+            }),
+            reserved848: [4]u8,
+            ///  device OUT endpoint-2 transfer length register
+            DOEP2LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  SETUP packet count/Received data PID
+                STPCNT_RXDPID: u2,
+                padding: u1,
+            }),
+            reserved864: [12]u8,
+            ///  device endpoint-3 control register
+            DOEP3CTL: mmio.Mmio(packed struct(u32) {
+                ///  maximum packet length
+                MPL: u11,
+                reserved15: u4,
+                ///  Endpoint active
+                EPACT: u1,
+                ///  EOFRM/DPID
+                EOFRM_DPID: u1,
+                ///  NAK status
+                NAKS: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                ///  Snoop mode
+                SNOOP: u1,
+                ///  STALL handshake
+                STALL: u1,
+                reserved26: u4,
+                ///  Clear NAK
+                CNAK: u1,
+                ///  Set NAK
+                SNAK: u1,
+                ///  SD0PID/SEVENFRM
+                SD0PID_SEVENFRM: u1,
+                ///  SD1PID/SODDFRM
+                SD1PID_SODDFRM: u1,
+                ///  Endpoint disable
+                EPD: u1,
+                ///  Endpoint enable
+                EPEN: u1,
+            }),
+            reserved872: [4]u8,
+            ///  device out endpoint-3 interrupt flag register
+            DOEP3INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Endpoint disabled
+                EPDIS: u1,
+                reserved3: u1,
+                ///  Setup phase finished
+                STPF: u1,
+                ///  Endpoint Rx FIFO overrun
+                EPRXFOVR: u1,
+                reserved6: u1,
+                ///  Back-to-back SETUP packets
+                BTBSTP: u1,
+                padding: u25,
+            }),
+            reserved880: [4]u8,
+            ///  device OUT endpoint-3 transfer length register
+            DOEP3LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  SETUP packet count/Received data PID
+                STPCNT_RXDPID: u2,
+                padding: u1,
+            }),
+        };
+
+        ///  USB on the go full speed host
+        pub const USBFS_HOST = extern struct {
+            ///  host configuration register (HCTL)
+            HCTL: mmio.Mmio(packed struct(u32) {
+                ///  clock select for USB clock
+                CLKSEL: u2,
+                padding: u30,
+            }),
+            ///  Host frame interval register
+            HFT: mmio.Mmio(packed struct(u32) {
+                ///  Frame interval
+                FRI: u16,
+                padding: u16,
+            }),
+            ///  FS host frame number/frame time remaining register (HFINFR)
+            HFINFR: mmio.Mmio(packed struct(u32) {
+                ///  Frame number
+                FRNUM: u16,
+                ///  Frame remaining time
+                FRT: u16,
+            }),
+            reserved16: [4]u8,
+            ///  Host periodic transmit FIFO/queue status register (HPTFQSTAT)
+            HPTFQSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Periodic transmit data FIFO space available
+                PTXFS: u16,
+                ///  Periodic transmit request queue space available
+                PTXREQS: u8,
+                ///  Top of the periodic transmit request queue
+                PTXREQT: u8,
+            }),
+            ///  Host all channels interrupt register
+            HACHINT: mmio.Mmio(packed struct(u32) {
+                ///  Host all channel interrupts
+                HACHINT: u8,
+                padding: u24,
+            }),
+            ///  host all channels interrupt mask register
+            HACHINTEN: mmio.Mmio(packed struct(u32) {
+                ///  Channel interrupt enable
+                CINTEN: u8,
+                padding: u24,
+            }),
+            reserved64: [36]u8,
+            ///  Host port control and status register (USBFS_HPCS)
+            HPCS: mmio.Mmio(packed struct(u32) {
+                ///  Port connect status
+                PCST: u1,
+                ///  Port connect detected
+                PCD: u1,
+                ///  Port enable
+                PE: u1,
+                ///  Port enable/disable change
+                PEDC: u1,
+                reserved6: u2,
+                ///  Port resume
+                PREM: u1,
+                ///  Port suspend
+                PSP: u1,
+                ///  Port reset
+                PRST: u1,
+                reserved10: u1,
+                ///  Port line status
+                PLST: u2,
+                ///  Port power
+                PP: u1,
+                reserved17: u4,
+                ///  Port speed
+                PS: u2,
+                padding: u13,
+            }),
+            reserved256: [188]u8,
+            ///  host channel-0 characteristics register (HCH0CTL)
+            HCH0CTL: mmio.Mmio(packed struct(u32) {
+                ///  Maximum packet size
+                MPL: u11,
+                ///  Endpoint number
+                EPNUM: u4,
+                ///  Endpoint direction
+                EPDIR: u1,
+                reserved17: u1,
+                ///  Low-speed device
+                LSD: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved22: u2,
+                ///  Device address
+                DAR: u7,
+                ///  Odd frame
+                ODDFRM: u1,
+                ///  Channel disable
+                CDIS: u1,
+                ///  Channel enable
+                CEN: u1,
+            }),
+            reserved264: [4]u8,
+            ///  host channel-0 interrupt register (USBFS_HCHxINTF)
+            HCH0INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Channel halted
+                CH: u1,
+                reserved3: u1,
+                ///  STALL response received interrupt
+                STALL: u1,
+                ///  NAK response received interrupt
+                NAK: u1,
+                ///  ACK response received/transmitted interrupt
+                ACK: u1,
+                reserved7: u1,
+                ///  USB bus error
+                USBER: u1,
+                ///  Babble error
+                BBER: u1,
+                ///  Request queue overrun
+                REQOVR: u1,
+                ///  Data toggle error
+                DTER: u1,
+                padding: u21,
+            }),
+            ///  host channel-0 interrupt enable register (HCH0INTEN)
+            HCH0INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer completed interrupt enable
+                TFIE: u1,
+                ///  Channel halted interrupt enable
+                CHIE: u1,
+                reserved3: u1,
+                ///  STALL interrupt enable
+                STALLIE: u1,
+                ///  NAK interrupt enable
+                NAKIE: u1,
+                ///  ACK interrupt enable
+                ACKIE: u1,
+                reserved7: u1,
+                ///  USB bus error interrupt enable
+                USBERIE: u1,
+                ///  Babble error interrupt enable
+                BBERIE: u1,
+                ///  request queue overrun interrupt enable
+                REQOVRIE: u1,
+                ///  Data toggle error interrupt enable
+                DTERIE: u1,
+                padding: u21,
+            }),
+            ///  host channel-0 transfer length register
+            HCH0LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  Data PID
+                DPID: u2,
+                padding: u1,
+            }),
+            reserved288: [12]u8,
+            ///  host channel-1 characteristics register (HCH1CTL)
+            HCH1CTL: mmio.Mmio(packed struct(u32) {
+                ///  Maximum packet size
+                MPL: u11,
+                ///  Endpoint number
+                EPNUM: u4,
+                ///  Endpoint direction
+                EPDIR: u1,
+                reserved17: u1,
+                ///  Low-speed device
+                LSD: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved22: u2,
+                ///  Device address
+                DAR: u7,
+                ///  Odd frame
+                ODDFRM: u1,
+                ///  Channel disable
+                CDIS: u1,
+                ///  Channel enable
+                CEN: u1,
+            }),
+            reserved296: [4]u8,
+            ///  host channel-1 interrupt register (HCH1INTF)
+            HCH1INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Channel halted
+                CH: u1,
+                reserved3: u1,
+                ///  STALL response received interrupt
+                STALL: u1,
+                ///  NAK response received interrupt
+                NAK: u1,
+                ///  ACK response received/transmitted interrupt
+                ACK: u1,
+                reserved7: u1,
+                ///  USB bus error
+                USBER: u1,
+                ///  Babble error
+                BBER: u1,
+                ///  Request queue overrun
+                REQOVR: u1,
+                ///  Data toggle error
+                DTER: u1,
+                padding: u21,
+            }),
+            ///  host channel-1 interrupt enable register (HCH1INTEN)
+            HCH1INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer completed interrupt enable
+                TFIE: u1,
+                ///  Channel halted interrupt enable
+                CHIE: u1,
+                reserved3: u1,
+                ///  STALL interrupt enable
+                STALLIE: u1,
+                ///  NAK interrupt enable
+                NAKIE: u1,
+                ///  ACK interrupt enable
+                ACKIE: u1,
+                reserved7: u1,
+                ///  USB bus error interrupt enable
+                USBERIE: u1,
+                ///  Babble error interrupt enable
+                BBERIE: u1,
+                ///  request queue overrun interrupt enable
+                REQOVRIE: u1,
+                ///  Data toggle error interrupt enable
+                DTERIE: u1,
+                padding: u21,
+            }),
+            ///  host channel-1 transfer length register
+            HCH1LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  Data PID
+                DPID: u2,
+                padding: u1,
+            }),
+            reserved320: [12]u8,
+            ///  host channel-2 characteristics register (HCH2CTL)
+            HCH2CTL: mmio.Mmio(packed struct(u32) {
+                ///  Maximum packet size
+                MPL: u11,
+                ///  Endpoint number
+                EPNUM: u4,
+                ///  Endpoint direction
+                EPDIR: u1,
+                reserved17: u1,
+                ///  Low-speed device
+                LSD: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved22: u2,
+                ///  Device address
+                DAR: u7,
+                ///  Odd frame
+                ODDFRM: u1,
+                ///  Channel disable
+                CDIS: u1,
+                ///  Channel enable
+                CEN: u1,
+            }),
+            reserved328: [4]u8,
+            ///  host channel-2 interrupt register (HCH2INTF)
+            HCH2INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Channel halted
+                CH: u1,
+                reserved3: u1,
+                ///  STALL response received interrupt
+                STALL: u1,
+                ///  NAK response received interrupt
+                NAK: u1,
+                ///  ACK response received/transmitted interrupt
+                ACK: u1,
+                reserved7: u1,
+                ///  USB bus error
+                USBER: u1,
+                ///  Babble error
+                BBER: u1,
+                ///  Request queue overrun
+                REQOVR: u1,
+                ///  Data toggle error
+                DTER: u1,
+                padding: u21,
+            }),
+            ///  host channel-2 interrupt enable register (HCH2INTEN)
+            HCH2INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer completed interrupt enable
+                TFIE: u1,
+                ///  Channel halted interrupt enable
+                CHIE: u1,
+                reserved3: u1,
+                ///  STALL interrupt enable
+                STALLIE: u1,
+                ///  NAK interrupt enable
+                NAKIE: u1,
+                ///  ACK interrupt enable
+                ACKIE: u1,
+                reserved7: u1,
+                ///  USB bus error interrupt enable
+                USBERIE: u1,
+                ///  Babble error interrupt enable
+                BBERIE: u1,
+                ///  request queue overrun interrupt enable
+                REQOVRIE: u1,
+                ///  Data toggle error interrupt enable
+                DTERIE: u1,
+                padding: u21,
+            }),
+            ///  host channel-2 transfer length register
+            HCH2LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  Data PID
+                DPID: u2,
+                padding: u1,
+            }),
+            reserved352: [12]u8,
+            ///  host channel-3 characteristics register (HCH3CTL)
+            HCH3CTL: mmio.Mmio(packed struct(u32) {
+                ///  Maximum packet size
+                MPL: u11,
+                ///  Endpoint number
+                EPNUM: u4,
+                ///  Endpoint direction
+                EPDIR: u1,
+                reserved17: u1,
+                ///  Low-speed device
+                LSD: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved22: u2,
+                ///  Device address
+                DAR: u7,
+                ///  Odd frame
+                ODDFRM: u1,
+                ///  Channel disable
+                CDIS: u1,
+                ///  Channel enable
+                CEN: u1,
+            }),
+            reserved360: [4]u8,
+            ///  host channel-3 interrupt register (HCH3INTF)
+            HCH3INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Channel halted
+                CH: u1,
+                reserved3: u1,
+                ///  STALL response received interrupt
+                STALL: u1,
+                ///  NAK response received interrupt
+                NAK: u1,
+                ///  ACK response received/transmitted interrupt
+                ACK: u1,
+                reserved7: u1,
+                ///  USB bus error
+                USBER: u1,
+                ///  Babble error
+                BBER: u1,
+                ///  Request queue overrun
+                REQOVR: u1,
+                ///  Data toggle error
+                DTER: u1,
+                padding: u21,
+            }),
+            ///  host channel-3 interrupt enable register (HCH3INTEN)
+            HCH3INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer completed interrupt enable
+                TFIE: u1,
+                ///  Channel halted interrupt enable
+                CHIE: u1,
+                reserved3: u1,
+                ///  STALL interrupt enable
+                STALLIE: u1,
+                ///  NAK interrupt enable
+                NAKIE: u1,
+                ///  ACK interrupt enable
+                ACKIE: u1,
+                reserved7: u1,
+                ///  USB bus error interrupt enable
+                USBERIE: u1,
+                ///  Babble error interrupt enable
+                BBERIE: u1,
+                ///  request queue overrun interrupt enable
+                REQOVRIE: u1,
+                ///  Data toggle error interrupt enable
+                DTERIE: u1,
+                padding: u21,
+            }),
+            ///  host channel-3 transfer length register
+            HCH3LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  Data PID
+                DPID: u2,
+                padding: u1,
+            }),
+            reserved384: [12]u8,
+            ///  host channel-4 characteristics register (HCH4CTL)
+            HCH4CTL: mmio.Mmio(packed struct(u32) {
+                ///  Maximum packet size
+                MPL: u11,
+                ///  Endpoint number
+                EPNUM: u4,
+                ///  Endpoint direction
+                EPDIR: u1,
+                reserved17: u1,
+                ///  Low-speed device
+                LSD: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved22: u2,
+                ///  Device address
+                DAR: u7,
+                ///  Odd frame
+                ODDFRM: u1,
+                ///  Channel disable
+                CDIS: u1,
+                ///  Channel enable
+                CEN: u1,
+            }),
+            reserved392: [4]u8,
+            ///  host channel-4 interrupt register (HCH4INTF)
+            HCH4INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Channel halted
+                CH: u1,
+                reserved3: u1,
+                ///  STALL response received interrupt
+                STALL: u1,
+                ///  NAK response received interrupt
+                NAK: u1,
+                ///  ACK response received/transmitted interrupt
+                ACK: u1,
+                reserved7: u1,
+                ///  USB bus error
+                USBER: u1,
+                ///  Babble error
+                BBER: u1,
+                ///  Request queue overrun
+                REQOVR: u1,
+                ///  Data toggle error
+                DTER: u1,
+                padding: u21,
+            }),
+            ///  host channel-4 interrupt enable register (HCH4INTEN)
+            HCH4INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer completed interrupt enable
+                TFIE: u1,
+                ///  Channel halted interrupt enable
+                CHIE: u1,
+                reserved3: u1,
+                ///  STALL interrupt enable
+                STALLIE: u1,
+                ///  NAK interrupt enable
+                NAKIE: u1,
+                ///  ACK interrupt enable
+                ACKIE: u1,
+                reserved7: u1,
+                ///  USB bus error interrupt enable
+                USBERIE: u1,
+                ///  Babble error interrupt enable
+                BBERIE: u1,
+                ///  request queue overrun interrupt enable
+                REQOVRIE: u1,
+                ///  Data toggle error interrupt enable
+                DTERIE: u1,
+                padding: u21,
+            }),
+            ///  host channel-4 transfer length register
+            HCH4LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  Data PID
+                DPID: u2,
+                padding: u1,
+            }),
+            reserved416: [12]u8,
+            ///  host channel-5 characteristics register (HCH5CTL)
+            HCH5CTL: mmio.Mmio(packed struct(u32) {
+                ///  Maximum packet size
+                MPL: u11,
+                ///  Endpoint number
+                EPNUM: u4,
+                ///  Endpoint direction
+                EPDIR: u1,
+                reserved17: u1,
+                ///  Low-speed device
+                LSD: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved22: u2,
+                ///  Device address
+                DAR: u7,
+                ///  Odd frame
+                ODDFRM: u1,
+                ///  Channel disable
+                CDIS: u1,
+                ///  Channel enable
+                CEN: u1,
+            }),
+            reserved424: [4]u8,
+            ///  host channel-5 interrupt register (HCH5INTF)
+            HCH5INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Channel halted
+                CH: u1,
+                reserved3: u1,
+                ///  STALL response received interrupt
+                STALL: u1,
+                ///  NAK response received interrupt
+                NAK: u1,
+                ///  ACK response received/transmitted interrupt
+                ACK: u1,
+                reserved7: u1,
+                ///  USB bus error
+                USBER: u1,
+                ///  Babble error
+                BBER: u1,
+                ///  Request queue overrun
+                REQOVR: u1,
+                ///  Data toggle error
+                DTER: u1,
+                padding: u21,
+            }),
+            ///  host channel-5 interrupt enable register (HCH5INTEN)
+            HCH5INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer completed interrupt enable
+                TFIE: u1,
+                ///  Channel halted interrupt enable
+                CHIE: u1,
+                reserved3: u1,
+                ///  STALL interrupt enable
+                STALLIE: u1,
+                ///  NAK interrupt enable
+                NAKIE: u1,
+                ///  ACK interrupt enable
+                ACKIE: u1,
+                reserved7: u1,
+                ///  USB bus error interrupt enable
+                USBERIE: u1,
+                ///  Babble error interrupt enable
+                BBERIE: u1,
+                ///  request queue overrun interrupt enable
+                REQOVRIE: u1,
+                ///  Data toggle error interrupt enable
+                DTERIE: u1,
+                padding: u21,
+            }),
+            ///  host channel-5 transfer length register
+            HCH5LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  Data PID
+                DPID: u2,
+                padding: u1,
+            }),
+            reserved448: [12]u8,
+            ///  host channel-6 characteristics register (HCH6CTL)
+            HCH6CTL: mmio.Mmio(packed struct(u32) {
+                ///  Maximum packet size
+                MPL: u11,
+                ///  Endpoint number
+                EPNUM: u4,
+                ///  Endpoint direction
+                EPDIR: u1,
+                reserved17: u1,
+                ///  Low-speed device
+                LSD: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved22: u2,
+                ///  Device address
+                DAR: u7,
+                ///  Odd frame
+                ODDFRM: u1,
+                ///  Channel disable
+                CDIS: u1,
+                ///  Channel enable
+                CEN: u1,
+            }),
+            reserved456: [4]u8,
+            ///  host channel-6 interrupt register (HCH6INTF)
+            HCH6INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Channel halted
+                CH: u1,
+                reserved3: u1,
+                ///  STALL response received interrupt
+                STALL: u1,
+                ///  NAK response received interrupt
+                NAK: u1,
+                ///  ACK response received/transmitted interrupt
+                ACK: u1,
+                reserved7: u1,
+                ///  USB bus error
+                USBER: u1,
+                ///  Babble error
+                BBER: u1,
+                ///  Request queue overrun
+                REQOVR: u1,
+                ///  Data toggle error
+                DTER: u1,
+                padding: u21,
+            }),
+            ///  host channel-6 interrupt enable register (HCH6INTEN)
+            HCH6INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer completed interrupt enable
+                TFIE: u1,
+                ///  Channel halted interrupt enable
+                CHIE: u1,
+                reserved3: u1,
+                ///  STALL interrupt enable
+                STALLIE: u1,
+                ///  NAK interrupt enable
+                NAKIE: u1,
+                ///  ACK interrupt enable
+                ACKIE: u1,
+                reserved7: u1,
+                ///  USB bus error interrupt enable
+                USBERIE: u1,
+                ///  Babble error interrupt enable
+                BBERIE: u1,
+                ///  request queue overrun interrupt enable
+                REQOVRIE: u1,
+                ///  Data toggle error interrupt enable
+                DTERIE: u1,
+                padding: u21,
+            }),
+            ///  host channel-6 transfer length register
+            HCH6LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  Data PID
+                DPID: u2,
+                padding: u1,
+            }),
+            reserved480: [12]u8,
+            ///  host channel-7 characteristics register (HCH7CTL)
+            HCH7CTL: mmio.Mmio(packed struct(u32) {
+                ///  Maximum packet size
+                MPL: u11,
+                ///  Endpoint number
+                EPNUM: u4,
+                ///  Endpoint direction
+                EPDIR: u1,
+                reserved17: u1,
+                ///  Low-speed device
+                LSD: u1,
+                ///  Endpoint type
+                EPTYPE: u2,
+                reserved22: u2,
+                ///  Device address
+                DAR: u7,
+                ///  Odd frame
+                ODDFRM: u1,
+                ///  Channel disable
+                CDIS: u1,
+                ///  Channel enable
+                CEN: u1,
+            }),
+            reserved488: [4]u8,
+            ///  host channel-7 interrupt register (HCH7INTF)
+            HCH7INTF: mmio.Mmio(packed struct(u32) {
+                ///  Transfer finished
+                TF: u1,
+                ///  Channel halted
+                CH: u1,
+                reserved3: u1,
+                ///  STALL response received interrupt
+                STALL: u1,
+                ///  NAK response received interrupt
+                NAK: u1,
+                ///  ACK response received/transmitted interrupt
+                ACK: u1,
+                reserved7: u1,
+                ///  USB bus error
+                USBER: u1,
+                ///  Babble error
+                BBER: u1,
+                ///  Request queue overrun
+                REQOVR: u1,
+                ///  Data toggle error
+                DTER: u1,
+                padding: u21,
+            }),
+            ///  host channel-7 interrupt enable register (HCH7INTEN)
+            HCH7INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer completed interrupt enable
+                TFIE: u1,
+                ///  Channel halted interrupt enable
+                CHIE: u1,
+                reserved3: u1,
+                ///  STALL interrupt enable
+                STALLIE: u1,
+                ///  NAK interrupt enable
+                NAKIE: u1,
+                ///  ACK interrupt enable
+                ACKIE: u1,
+                reserved7: u1,
+                ///  USB bus error interrupt enable
+                USBERIE: u1,
+                ///  Babble error interrupt enable
+                BBERIE: u1,
+                ///  request queue overrun interrupt enable
+                REQOVRIE: u1,
+                ///  Data toggle error interrupt enable
+                DTERIE: u1,
+                padding: u21,
+            }),
+            ///  host channel-7 transfer length register
+            HCH7LEN: mmio.Mmio(packed struct(u32) {
+                ///  Transfer length
+                TLEN: u19,
+                ///  Packet count
+                PCNT: u10,
+                ///  Data PID
+                DPID: u2,
+                padding: u1,
+            }),
+        };
+
+        ///  USB full speed global registers
+        pub const USBFS_GLOBAL = extern struct {
+            ///  Global OTG control and status register (USBFS_GOTGCS)
+            GOTGCS: mmio.Mmio(packed struct(u32) {
+                ///  SRP success
+                SRPS: u1,
+                ///  SRP request
+                SRPREQ: u1,
+                reserved8: u6,
+                ///  Host success
+                HNPS: u1,
+                ///  HNP request
+                HNPREQ: u1,
+                ///  Host HNP enable
+                HHNPEN: u1,
+                ///  Device HNP enabled
+                DHNPEN: u1,
+                reserved16: u4,
+                ///  ID pin status
+                IDPS: u1,
+                ///  Debounce interval
+                DI: u1,
+                ///  A-session valid
+                ASV: u1,
+                ///  B-session valid
+                BSV: u1,
+                padding: u12,
+            }),
+            ///  Global OTG interrupt flag register (USBFS_GOTGINTF)
+            GOTGINTF: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  Session end
+                SESEND: u1,
+                reserved8: u5,
+                ///  Session request success status change
+                SRPEND: u1,
+                ///  HNP end
+                HNPEND: u1,
+                reserved17: u7,
+                ///  Host negotiation request detected
+                HNPDET: u1,
+                ///  A-device timeout
+                ADTO: u1,
+                ///  Debounce finish
+                DF: u1,
+                padding: u12,
+            }),
+            ///  Global AHB control and status register (USBFS_GAHBCS)
+            GAHBCS: mmio.Mmio(packed struct(u32) {
+                ///  Global interrupt enable
+                GINTEN: u1,
+                reserved7: u6,
+                ///  Tx FIFO threshold
+                TXFTH: u1,
+                ///  Periodic Tx FIFO threshold
+                PTXFTH: u1,
+                padding: u23,
+            }),
+            ///  Global USB control and status register (USBFS_GUSBCSR)
+            GUSBCS: mmio.Mmio(packed struct(u32) {
+                ///  Timeout calibration
+                TOC: u3,
+                reserved8: u5,
+                ///  SRP capability enable
+                SRPCEN: u1,
+                ///  HNP capability enable
+                HNPCEN: u1,
+                ///  USB turnaround time
+                UTT: u4,
+                reserved29: u15,
+                ///  Force host mode
+                FHM: u1,
+                ///  Force device mode
+                FDM: u1,
+                padding: u1,
+            }),
+            ///  Global reset control register (USBFS_GRSTCTL)
+            GRSTCTL: mmio.Mmio(packed struct(u32) {
+                ///  Core soft reset
+                CSRST: u1,
+                ///  HCLK soft reset
+                HCSRST: u1,
+                ///  Host frame counter reset
+                HFCRST: u1,
+                reserved4: u1,
+                ///  RxFIFO flush
+                RXFF: u1,
+                ///  TxFIFO flush
+                TXFF: u1,
+                ///  TxFIFO number
+                TXFNUM: u5,
+                padding: u21,
+            }),
+            ///  Global interrupt flag register (USBFS_GINTF)
+            GINTF: mmio.Mmio(packed struct(u32) {
+                ///  Current operation mode
+                COPM: u1,
+                ///  Mode fault interrupt flag
+                MFIF: u1,
+                ///  OTG interrupt flag
+                OTGIF: u1,
+                ///  Start of frame
+                SOF: u1,
+                ///  RxFIFO non-empty interrupt flag
+                RXFNEIF: u1,
+                ///  Non-periodic TxFIFO empty interrupt flag
+                NPTXFEIF: u1,
+                ///  Global Non-Periodic IN NAK effective
+                GNPINAK: u1,
+                ///  Global OUT NAK effective
+                GONAK: u1,
+                reserved10: u2,
+                ///  Early suspend
+                ESP: u1,
+                ///  USB suspend
+                SP: u1,
+                ///  USB reset
+                RST: u1,
+                ///  Enumeration finished
+                ENUMF: u1,
+                ///  Isochronous OUT packet dropped interrupt
+                ISOOPDIF: u1,
+                ///  End of periodic frame interrupt flag
+                EOPFIF: u1,
+                reserved18: u2,
+                ///  IN endpoint interrupt flag
+                IEPIF: u1,
+                ///  OUT endpoint interrupt flag
+                OEPIF: u1,
+                ///  Isochronous IN transfer Not Complete Interrupt Flag
+                ISOINCIF: u1,
+                ///  periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode)
+                PXNCIF_ISOONCIF: u1,
+                reserved24: u2,
+                ///  Host port interrupt flag
+                HPIF: u1,
+                ///  Host channels interrupt flag
+                HCIF: u1,
+                ///  Periodic TxFIFO empty interrupt flag
+                PTXFEIF: u1,
+                reserved28: u1,
+                ///  ID pin status change
+                IDPSC: u1,
+                ///  Disconnect interrupt flag
+                DISCIF: u1,
+                ///  Session interrupt flag
+                SESIF: u1,
+                ///  Wakeup interrupt flag
+                WKUPIF: u1,
+            }),
+            ///  Global interrupt enable register (USBFS_GINTEN)
+            GINTEN: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Mode fault interrupt enable
+                MFIE: u1,
+                ///  OTG interrupt enable
+                OTGIE: u1,
+                ///  Start of frame interrupt enable
+                SOFIE: u1,
+                ///  Receive FIFO non-empty interrupt enable
+                RXFNEIE: u1,
+                ///  Non-periodic TxFIFO empty interrupt enable
+                NPTXFEIE: u1,
+                ///  Global non-periodic IN NAK effective interrupt enable
+                GNPINAKIE: u1,
+                ///  Global OUT NAK effective interrupt enable
+                GONAKIE: u1,
+                reserved10: u2,
+                ///  Early suspend interrupt enable
+                ESPIE: u1,
+                ///  USB suspend interrupt enable
+                SPIE: u1,
+                ///  USB reset interrupt enable
+                RSTIE: u1,
+                ///  Enumeration finish interrupt enable
+                ENUMFIE: u1,
+                ///  Isochronous OUT packet dropped interrupt enable
+                ISOOPDIE: u1,
+                ///  End of periodic frame interrupt enable
+                EOPFIE: u1,
+                reserved18: u2,
+                ///  IN endpoints interrupt enable
+                IEPIE: u1,
+                ///  OUT endpoints interrupt enable
+                OEPIE: u1,
+                ///  isochronous IN transfer not complete interrupt enable
+                ISOINCIE: u1,
+                ///  periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode)
+                PXNCIE_ISOONCIE: u1,
+                reserved24: u2,
+                ///  Host port interrupt enable
+                HPIE: u1,
+                ///  Host channels interrupt enable
+                HCIE: u1,
+                ///  Periodic TxFIFO empty interrupt enable
+                PTXFEIE: u1,
+                reserved28: u1,
+                ///  ID pin status change interrupt enable
+                IDPSCIE: u1,
+                ///  Disconnect interrupt enable
+                DISCIE: u1,
+                ///  Session interrupt enable
+                SESIE: u1,
+                ///  Wakeup interrupt enable
+                WKUPIE: u1,
+            }),
+            ///  Global Receive status read(Device mode)
+            GRSTATR_Device: mmio.Mmio(packed struct(u32) {
+                ///  Endpoint number
+                EPNUM: u4,
+                ///  Byte count
+                BCOUNT: u11,
+                ///  Data PID
+                DPID: u2,
+                ///  Recieve packet status
+                RPCKST: u4,
+                padding: u11,
+            }),
+            ///  Global Receive status pop(Device mode)
+            GRSTATP_Device: mmio.Mmio(packed struct(u32) {
+                ///  Endpoint number
+                EPNUM: u4,
+                ///  Byte count
+                BCOUNT: u11,
+                ///  Data PID
+                DPID: u2,
+                ///  Recieve packet status
+                RPCKST: u4,
+                padding: u11,
+            }),
+            ///  Global Receive FIFO size register (USBFS_GRFLEN)
+            GRFLEN: mmio.Mmio(packed struct(u32) {
+                ///  Rx FIFO depth
+                RXFD: u16,
+                padding: u16,
+            }),
+            ///  Host non-periodic transmit FIFO length register (Host mode)
+            HNPTFLEN: mmio.Mmio(packed struct(u32) {
+                ///  host non-periodic transmit Tx RAM start address
+                HNPTXRSAR: u16,
+                ///  host non-periodic TxFIFO depth
+                HNPTXFD: u16,
+            }),
+            ///  Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT)
+            HNPTFQSTAT: mmio.Mmio(packed struct(u32) {
+                ///  Non-periodic TxFIFO space
+                NPTXFS: u16,
+                ///  Non-periodic transmit request queue space
+                NPTXRQS: u8,
+                ///  Top of the non-periodic transmit request queue
+                NPTXRQTOP: u7,
+                padding: u1,
+            }),
+            reserved56: [8]u8,
+            ///  Global core configuration register (USBFS_GCCFG)
+            GCCFG: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  Power on
+                PWRON: u1,
+                reserved18: u1,
+                ///  The VBUS A-device Comparer enable
+                VBUSACEN: u1,
+                ///  The VBUS B-device Comparer enable
+                VBUSBCEN: u1,
+                ///  SOF output enable
+                SOFOEN: u1,
+                ///  VBUS ignored
+                VBUSIG: u1,
+                padding: u10,
+            }),
+            ///  core ID register
+            CID: mmio.Mmio(packed struct(u32) {
+                ///  Core ID
+                CID: u32,
+            }),
+            reserved256: [192]u8,
+            ///  Host periodic transmit FIFO length register (HPTFLEN)
+            HPTFLEN: mmio.Mmio(packed struct(u32) {
+                ///  Host periodic TxFIFO start address
+                HPTXFSAR: u16,
+                ///  Host periodic TxFIFO depth
+                HPTXFD: u16,
+            }),
+            ///  device IN endpoint transmit FIFO size register (DIEP1TFLEN)
+            DIEP1TFLEN: mmio.Mmio(packed struct(u32) {
+                ///  IN endpoint FIFO transmit RAM start address
+                IEPTXRSAR: u16,
+                ///  IN endpoint TxFIFO depth
+                IEPTXFD: u16,
+            }),
+            ///  device IN endpoint transmit FIFO size register (DIEP2TFLEN)
+            DIEP2TFLEN: mmio.Mmio(packed struct(u32) {
+                ///  IN endpoint FIFO transmit RAM start address
+                IEPTXRSAR: u16,
+                ///  IN endpoint TxFIFO depth
+                IEPTXFD: u16,
+            }),
+            ///  device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN)
+            DIEP3TFLEN: mmio.Mmio(packed struct(u32) {
+                ///  IN endpoint FIFO4 transmit RAM start address
+                IEPTXRSAR: u16,
+                ///  IN endpoint TxFIFO depth
+                IEPTXFD: u16,
+            }),
+        };
+
+        ///  Inter integrated circuit
+        pub const I2C0 = extern struct {
+            ///  Control register 0
+            CTL0: mmio.Mmio(packed struct(u16) {
+                ///  I2C peripheral enable
+                I2CEN: u1,
+                ///  SMBus/I2C mode switch
+                SMBEN: u1,
+                reserved3: u1,
+                ///  SMBusType Selection
+                SMBSEL: u1,
+                ///  ARP protocol in SMBus switch
+                ARPEN: u1,
+                ///  PEC Calculation Switch
+                PECEN: u1,
+                ///  Whether or not to response to a General Call (0x00)
+                GCEN: u1,
+                ///  Whether to stretch SCL low when data is not ready in slave mode
+                SS: u1,
+                ///  Generate a START condition on I2C bus
+                START: u1,
+                ///  Generate a STOP condition on I2C bus
+                STOP: u1,
+                ///  Whether or not to send an ACK
+                ACKEN: u1,
+                ///  Position of ACK and PEC when receiving
+                POAP: u1,
+                ///  PEC Transfer
+                PECTRANS: u1,
+                ///  SMBus alert
+                SALT: u1,
+                reserved15: u1,
+                ///  Software reset
+                SRESET: u1,
+            }),
+            reserved4: [2]u8,
+            ///  Control register 1
+            CTL1: mmio.Mmio(packed struct(u16) {
+                ///  I2C Peripheral clock frequency
+                I2CCLK: u6,
+                reserved8: u2,
+                ///  Error interrupt enable
+                ERRIE: u1,
+                ///  Event interrupt enable
+                EVIE: u1,
+                ///  Buffer interrupt enable
+                BUFIE: u1,
+                ///  DMA mode switch
+                DMAON: u1,
+                ///  Flag indicating DMA last transfer
+                DMALST: u1,
+                padding: u3,
+            }),
+            reserved8: [2]u8,
+            ///  Slave address register 0
+            SADDR0: mmio.Mmio(packed struct(u16) {
+                ///  Bit 0 of a 10-bit address
+                ADDRESS0: u1,
+                ///  7-bit address or bits 7:1 of a 10-bit address
+                ADDRESS7_1: u7,
+                ///  Highest two bits of a 10-bit address
+                ADDRESS9_8: u2,
+                reserved15: u5,
+                ///  Address mode for the I2C slave
+                ADDFORMAT: u1,
+            }),
+            reserved12: [2]u8,
+            ///  Slave address register 1
+            SADDR1: mmio.Mmio(packed struct(u16) {
+                ///  Dual-Address mode switch
+                DUADEN: u1,
+                ///  Second I2C address for the slave in Dual-Address mode
+                ADDRESS2: u7,
+                padding: u8,
+            }),
+            reserved16: [2]u8,
+            ///  Transfer buffer register
+            DATA: mmio.Mmio(packed struct(u16) {
+                ///  Transmission or reception data buffer register
+                TRB: u8,
+                padding: u8,
+            }),
+            reserved20: [2]u8,
+            ///  Transfer status register 0
+            STAT0: mmio.Mmio(packed struct(u16) {
+                ///  START condition sent out in master mode
+                SBSEND: u1,
+                ///  Address is sent in master mode or received and matches in slave mode
+                ADDSEND: u1,
+                ///  Byte transmission completed
+                BTC: u1,
+                ///  Header of 10-bit address is sent in master mode
+                ADD10SEND: u1,
+                ///  STOP condition detected in slave mode
+                STPDET: u1,
+                reserved6: u1,
+                ///  I2C_DATA is not Empty during receiving
+                RBNE: u1,
+                ///  I2C_DATA is Empty during transmitting
+                TBE: u1,
+                ///  A bus error occurs indication a unexpected START or STOP condition on I2C bus
+                BERR: u1,
+                ///  Arbitration Lost in master mode
+                LOSTARB: u1,
+                ///  Acknowledge error
+                AERR: u1,
+                ///  Over-run or under-run situation occurs in slave mode
+                OUERR: u1,
+                ///  PEC error when receiving data
+                PECERR: u1,
+                reserved14: u1,
+                ///  Timeout signal in SMBus mode
+                SMBTO: u1,
+                ///  SMBus Alert status
+                SMBALT: u1,
+            }),
+            reserved24: [2]u8,
+            ///  Transfer status register 1
+            STAT1: mmio.Mmio(packed struct(u16) {
+                ///  A flag indicating whether I2C block is in master or slave mode
+                MASTER: u1,
+                ///  Busy flag
+                I2CBSY: u1,
+                ///  Whether the I2C is a transmitter or a receiver
+                TR: u1,
+                reserved4: u1,
+                ///  General call address (00h) received
+                RXGC: u1,
+                ///  Default address of SMBusDevice
+                DEFSMB: u1,
+                ///  SMBus Host Header detected in slave mode
+                HSTSMB: u1,
+                ///  Dual Flag in slave mode
+                DUMODF: u1,
+                ///  Packet Error Checking Value that calculated by hardware when PEC is enabled
+                PECV: u8,
+            }),
+            reserved28: [2]u8,
+            ///  Clock configure register
+            CKCFG: mmio.Mmio(packed struct(u16) {
+                ///  I2C Clock control in master mode
+                CLKC: u12,
+                reserved14: u2,
+                ///  Duty cycle in fast mode
+                DTCY: u1,
+                ///  I2C speed selection in master mode
+                FAST: u1,
+            }),
+            reserved32: [2]u8,
+            ///  Rise time register
+            RT: mmio.Mmio(packed struct(u16) {
+                ///  Maximum rise time in master mode
+                RISETIME: u6,
+                padding: u10,
+            }),
+        };
+
+        ///  Basic-timers
+        pub const TIMER5 = extern struct {
+            ///  control register 0
+            CTL0: mmio.Mmio(packed struct(u16) {
+                ///  Counter enable
+                CEN: u1,
+                ///  Update disable
+                UPDIS: u1,
+                ///  Update source
+                UPS: u1,
+                ///  Single pulse mode
+                SPM: u1,
+                reserved7: u3,
+                ///  Auto-reload shadow enable
+                ARSE: u1,
+                padding: u8,
+            }),
+            reserved4: [2]u8,
+            ///  control register 1
+            CTL1: mmio.Mmio(packed struct(u16) {
+                reserved4: u4,
+                ///  Master mode control
+                MMC: u3,
+                padding: u9,
+            }),
+            reserved12: [6]u8,
+            ///  DMA/Interrupt enable register
+            DMAINTEN: mmio.Mmio(packed struct(u16) {
+                ///  Update interrupt enable
+                UPIE: u1,
+                reserved8: u7,
+                ///  Update DMA request enable
+                UPDEN: u1,
+                padding: u7,
+            }),
+            reserved16: [2]u8,
+            ///  Interrupt flag register
+            INTF: mmio.Mmio(packed struct(u16) {
+                ///  Update interrupt flag
+                UPIF: u1,
+                padding: u15,
+            }),
+            reserved20: [2]u8,
+            ///  event generation register
+            SWEVG: mmio.Mmio(packed struct(u16) {
+                ///  Update generation
+                UPG: u1,
+                padding: u15,
+            }),
+            reserved36: [14]u8,
+            ///  Counter register
+            CNT: mmio.Mmio(packed struct(u16) {
+                ///  Low counter value
+                CNT: u16,
+            }),
+            reserved40: [2]u8,
+            ///  Prescaler register
+            PSC: mmio.Mmio(packed struct(u16) {
+                ///  Prescaler value of the counter clock
+                PSC: u16,
+            }),
+            reserved44: [2]u8,
+            ///  Counter auto reload register
+            CAR: mmio.Mmio(packed struct(u16) {
+                ///  Counter auto reload value
+                CARL: u16,
+            }),
+        };
+
+        ///  Enhanced Core Local Interrupt Controller
+        pub const ECLIC = extern struct {
+            ///  cliccfg Register
+            CLICCFG: mmio.Mmio(packed struct(u8) {
+                reserved1: u1,
+                ///  NLBITS
+                NLBITS: u4,
+                padding: u3,
+            }),
+            reserved4: [3]u8,
+            ///  clicinfo Register
+            CLICINFO: mmio.Mmio(packed struct(u32) {
+                ///  NUM_INTERRUPT
+                NUM_INTERRUPT: u13,
+                ///  VERSION
+                VERSION: u8,
+                ///  CLICINTCTLBITS
+                CLICINTCTLBITS: u4,
+                padding: u7,
+            }),
+            reserved11: [3]u8,
+            ///  MTH Register
+            MTH: mmio.Mmio(packed struct(u8) {
+                ///  MTH
+                MTH: u8,
+            }),
+            reserved4096: [4084]u8,
+            ///  clicintip Register
+            CLICINTIP_0: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_0: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_0: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_0: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_1: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_1: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_1: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_1: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_2: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_2: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_2: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_2: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_3: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_3: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_3: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_3: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_4: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_4: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_4: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_4: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_5: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_5: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_5: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_5: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_6: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_6: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_6: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_6: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_7: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_7: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_7: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_7: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_8: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_8: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_8: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_8: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_9: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_9: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_9: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_9: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_10: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_10: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_10: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_10: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_11: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_11: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_11: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_11: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_12: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_12: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_12: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_12: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_13: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_13: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_13: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_13: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_14: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_14: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_14: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_14: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_15: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_15: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_15: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_15: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_16: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_16: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_16: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_16: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_17: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_17: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_17: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_17: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_18: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_18: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_18: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_18: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_19: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_19: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_19: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_19: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_20: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_20: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_20: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_20: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_21: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_21: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_21: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_21: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_22: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_22: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_22: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_22: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_23: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_23: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_23: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_23: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_24: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_24: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_24: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_24: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_25: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_25: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_25: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_25: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_26: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_26: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_26: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_26: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_27: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_27: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_27: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_27: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_28: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_28: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_28: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_28: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_29: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_29: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_29: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_29: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_30: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_30: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_30: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_30: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_31: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_31: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_31: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_31: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_32: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_32: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_32: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_32: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_33: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_33: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_33: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_33: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_34: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_34: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_34: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_34: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_35: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_35: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_35: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_35: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_36: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_36: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_36: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_36: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_37: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_37: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_37: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_37: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_38: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_38: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_38: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_38: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_39: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_39: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_39: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_39: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_40: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_40: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_40: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_40: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_41: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_41: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_41: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_41: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_42: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_42: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_42: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_42: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_43: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_43: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_43: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_43: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_44: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_44: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_44: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_44: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_45: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_45: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_45: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_45: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_46: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_46: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_46: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_46: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_47: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_47: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_47: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_47: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_48: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_48: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_48: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_48: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_49: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_49: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_49: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_49: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_50: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_50: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_50: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_50: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_51: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_51: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_51: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_51: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_52: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_52: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_52: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_52: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_53: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_53: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_53: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_53: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_54: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_54: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_54: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_54: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_55: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_55: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_55: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_55: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_56: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_56: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_56: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_56: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_57: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_57: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_57: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_57: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_58: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_58: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_58: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_58: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_59: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_59: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_59: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_59: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_60: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_60: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_60: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_60: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_61: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_61: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_61: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_61: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_62: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_62: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_62: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_62: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_63: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_63: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_63: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_63: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_64: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_64: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_64: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_64: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_65: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_65: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_65: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_65: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_66: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_66: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_66: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_66: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_67: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_67: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_67: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_67: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_68: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_68: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_68: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_68: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_69: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_69: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_69: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_69: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_70: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_70: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_70: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_70: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_71: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_71: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_71: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_71: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_72: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_72: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_72: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_72: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_73: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_73: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_73: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_73: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_74: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_74: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_74: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_74: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_75: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_75: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_75: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_75: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_76: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_76: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_76: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_76: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_77: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_77: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_77: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_77: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_78: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_78: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_78: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_78: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_79: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_79: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_79: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_79: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_80: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_80: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_80: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_80: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_81: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_81: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_81: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_81: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_82: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_82: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_82: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_82: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_83: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_83: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_83: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_83: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_84: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_84: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_84: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_84: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            reserved4437: [1]u8,
+            ///  clicintie Register
+            CLICINTIE_85: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_85: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_85: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_85: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+            ///  clicintie Register
+            CLICINTIE_86: mmio.Mmio(packed struct(u8) {
+                ///  IE
+                IE: u1,
+                padding: u7,
+            }),
+            ///  clicintattr Register
+            CLICINTATTR_86: mmio.Mmio(packed struct(u8) {
+                ///  SHV
+                SHV: u1,
+                ///  TRIG
+                TRIG: u2,
+                padding: u5,
+            }),
+            ///  clicintctl Register
+            CLICINTCTL_86: mmio.Mmio(packed struct(u8) {
+                ///  LEVEL_PRIORITY
+                LEVEL_PRIORITY: u8,
+            }),
+            ///  clicintip Register
+            CLICINTIP_86: mmio.Mmio(packed struct(u8) {
+                ///  IP
+                IP: u1,
+                padding: u7,
+            }),
+        };
+
+        ///  Power management unit
+        pub const PMU = extern struct {
+            ///  power control register
+            CTL: mmio.Mmio(packed struct(u32) {
+                ///  LDO Low Power Mode
+                LDOLP: u1,
+                ///  Standby Mode
+                STBMOD: u1,
+                ///  Wakeup Flag Reset
+                WURST: u1,
+                ///  Standby Flag Reset
+                STBRST: u1,
+                ///  Low Voltage Detector Enable
+                LVDEN: u1,
+                ///  Low Voltage Detector Threshold
+                LVDT: u3,
+                ///  Backup Domain Write Enable
+                BKPWEN: u1,
+                padding: u23,
+            }),
+            ///  power control/status register
+            CS: mmio.Mmio(packed struct(u32) {
+                ///  Wakeup flag
+                WUF: u1,
+                ///  Standby flag
+                STBF: u1,
+                ///  Low Voltage Detector Status Flag
+                LVDF: u1,
+                reserved8: u5,
+                ///  Enable WKUP pin
+                WUPEN: u1,
+                padding: u23,
+            }),
+        };
+
+        ///  Reset and clock unit
+        pub const RCU = extern struct {
+            ///  Control register
+            CTL: mmio.Mmio(packed struct(u32) {
+                ///  Internal 8MHz RC oscillator Enable
+                IRC8MEN: u1,
+                ///  IRC8M Internal 8MHz RC Oscillator stabilization Flag
+                IRC8MSTB: u1,
+                reserved3: u1,
+                ///  Internal 8MHz RC Oscillator clock trim adjust value
+                IRC8MADJ: u5,
+                ///  Internal 8MHz RC Oscillator calibration value register
+                IRC8MCALIB: u8,
+                ///  External High Speed oscillator Enable
+                HXTALEN: u1,
+                ///  External crystal oscillator (HXTAL) clock stabilization flag
+                HXTALSTB: u1,
+                ///  External crystal oscillator (HXTAL) clock bypass mode enable
+                HXTALBPS: u1,
+                ///  HXTAL Clock Monitor Enable
+                CKMEN: u1,
+                reserved24: u4,
+                ///  PLL enable
+                PLLEN: u1,
+                ///  PLL Clock Stabilization Flag
+                PLLSTB: u1,
+                ///  PLL1 enable
+                PLL1EN: u1,
+                ///  PLL1 Clock Stabilization Flag
+                PLL1STB: u1,
+                ///  PLL2 enable
+                PLL2EN: u1,
+                ///  PLL2 Clock Stabilization Flag
+                PLL2STB: u1,
+                padding: u2,
+            }),
+            ///  Clock configuration register 0 (RCU_CFG0)
+            CFG0: mmio.Mmio(packed struct(u32) {
+                ///  System clock switch
+                SCS: u2,
+                ///  System clock switch status
+                SCSS: u2,
+                ///  AHB prescaler selection
+                AHBPSC: u4,
+                ///  APB1 prescaler selection
+                APB1PSC: u3,
+                ///  APB2 prescaler selection
+                APB2PSC: u3,
+                ///  ADC clock prescaler selection
+                ADCPSC_1_0: u2,
+                ///  PLL Clock Source Selection
+                PLLSEL: u1,
+                ///  The LSB of PREDV0 division factor
+                PREDV0_LSB: u1,
+                ///  The PLL clock multiplication factor
+                PLLMF_3_0: u4,
+                ///  USBFS clock prescaler selection
+                USBFSPSC: u2,
+                ///  CKOUT0 Clock Source Selection
+                CKOUT0SEL: u4,
+                ///  Bit 2 of ADCPSC
+                ADCPSC_2: u1,
+                ///  Bit 4 of PLLMF
+                PLLMF_4: u1,
+                padding: u2,
+            }),
+            ///  Clock interrupt register (RCU_INT)
+            INT: mmio.Mmio(packed struct(u32) {
+                ///  IRC40K stabilization interrupt flag
+                IRC40KSTBIF: u1,
+                ///  LXTAL stabilization interrupt flag
+                LXTALSTBIF: u1,
+                ///  IRC8M stabilization interrupt flag
+                IRC8MSTBIF: u1,
+                ///  HXTAL stabilization interrupt flag
+                HXTALSTBIF: u1,
+                ///  PLL stabilization interrupt flag
+                PLLSTBIF: u1,
+                ///  PLL1 stabilization interrupt flag
+                PLL1STBIF: u1,
+                ///  PLL2 stabilization interrupt flag
+                PLL2STBIF: u1,
+                ///  HXTAL Clock Stuck Interrupt Flag
+                CKMIF: u1,
+                ///  IRC40K Stabilization interrupt enable
+                IRC40KSTBIE: u1,
+                ///  LXTAL Stabilization Interrupt Enable
+                LXTALSTBIE: u1,
+                ///  IRC8M Stabilization Interrupt Enable
+                IRC8MSTBIE: u1,
+                ///  HXTAL Stabilization Interrupt Enable
+                HXTALSTBIE: u1,
+                ///  PLL Stabilization Interrupt Enable
+                PLLSTBIE: u1,
+                ///  PLL1 Stabilization Interrupt Enable
+                PLL1STBIE: u1,
+                ///  PLL2 Stabilization Interrupt Enable
+                PLL2STBIE: u1,
+                reserved16: u1,
+                ///  IRC40K Stabilization Interrupt Clear
+                IRC40KSTBIC: u1,
+                ///  LXTAL Stabilization Interrupt Clear
+                LXTALSTBIC: u1,
+                ///  IRC8M Stabilization Interrupt Clear
+                IRC8MSTBIC: u1,
+                ///  HXTAL Stabilization Interrupt Clear
+                HXTALSTBIC: u1,
+                ///  PLL stabilization Interrupt Clear
+                PLLSTBIC: u1,
+                ///  PLL1 stabilization Interrupt Clear
+                PLL1STBIC: u1,
+                ///  PLL2 stabilization Interrupt Clear
+                PLL2STBIC: u1,
+                ///  HXTAL Clock Stuck Interrupt Clear
+                CKMIC: u1,
+                padding: u8,
+            }),
+            ///  APB2 reset register (RCU_APB2RST)
+            APB2RST: mmio.Mmio(packed struct(u32) {
+                ///  Alternate function I/O reset
+                AFRST: u1,
+                reserved2: u1,
+                ///  GPIO port A reset
+                PARST: u1,
+                ///  GPIO port B reset
+                PBRST: u1,
+                ///  GPIO port C reset
+                PCRST: u1,
+                ///  GPIO port D reset
+                PDRST: u1,
+                ///  GPIO port E reset
+                PERST: u1,
+                reserved9: u2,
+                ///  ADC0 reset
+                ADC0RST: u1,
+                ///  ADC1 reset
+                ADC1RST: u1,
+                ///  Timer 0 reset
+                TIMER0RST: u1,
+                ///  SPI0 reset
+                SPI0RST: u1,
+                reserved14: u1,
+                ///  USART0 Reset
+                USART0RST: u1,
+                padding: u17,
+            }),
+            ///  APB1 reset register (RCU_APB1RST)
+            APB1RST: mmio.Mmio(packed struct(u32) {
+                ///  TIMER1 timer reset
+                TIMER1RST: u1,
+                ///  TIMER2 timer reset
+                TIMER2RST: u1,
+                ///  TIMER3 timer reset
+                TIMER3RST: u1,
+                ///  TIMER4 timer reset
+                TIMER4RST: u1,
+                ///  TIMER5 timer reset
+                TIMER5RST: u1,
+                ///  TIMER6 timer reset
+                TIMER6RST: u1,
+                reserved11: u5,
+                ///  Window watchdog timer reset
+                WWDGTRST: u1,
+                reserved14: u2,
+                ///  SPI1 reset
+                SPI1RST: u1,
+                ///  SPI2 reset
+                SPI2RST: u1,
+                reserved17: u1,
+                ///  USART1 reset
+                USART1RST: u1,
+                ///  USART2 reset
+                USART2RST: u1,
+                ///  UART3 reset
+                UART3RST: u1,
+                ///  UART4 reset
+                UART4RST: u1,
+                ///  I2C0 reset
+                I2C0RST: u1,
+                ///  I2C1 reset
+                I2C1RST: u1,
+                reserved25: u2,
+                ///  CAN0 reset
+                CAN0RST: u1,
+                ///  CAN1 reset
+                CAN1RST: u1,
+                ///  Backup interface reset
+                BKPIRST: u1,
+                ///  Power control reset
+                PMURST: u1,
+                ///  DAC reset
+                DACRST: u1,
+                padding: u2,
+            }),
+            ///  AHB enable register
+            AHBEN: mmio.Mmio(packed struct(u32) {
+                ///  DMA0 clock enable
+                DMA0EN: u1,
+                ///  DMA1 clock enable
+                DMA1EN: u1,
+                ///  SRAM interface clock enable when sleep mode
+                SRAMSPEN: u1,
+                reserved4: u1,
+                ///  FMC clock enable when sleep mode
+                FMCSPEN: u1,
+                reserved6: u1,
+                ///  CRC clock enable
+                CRCEN: u1,
+                reserved8: u1,
+                ///  EXMC clock enable
+                EXMCEN: u1,
+                reserved12: u3,
+                ///  USBFS clock enable
+                USBFSEN: u1,
+                padding: u19,
+            }),
+            ///  APB2 clock enable register (RCU_APB2EN)
+            APB2EN: mmio.Mmio(packed struct(u32) {
+                ///  Alternate function IO clock enable
+                AFEN: u1,
+                reserved2: u1,
+                ///  GPIO port A clock enable
+                PAEN: u1,
+                ///  GPIO port B clock enable
+                PBEN: u1,
+                ///  GPIO port C clock enable
+                PCEN: u1,
+                ///  GPIO port D clock enable
+                PDEN: u1,
+                ///  GPIO port E clock enable
+                PEEN: u1,
+                reserved9: u2,
+                ///  ADC0 clock enable
+                ADC0EN: u1,
+                ///  ADC1 clock enable
+                ADC1EN: u1,
+                ///  TIMER0 clock enable
+                TIMER0EN: u1,
+                ///  SPI0 clock enable
+                SPI0EN: u1,
+                reserved14: u1,
+                ///  USART0 clock enable
+                USART0EN: u1,
+                padding: u17,
+            }),
+            ///  APB1 clock enable register (RCU_APB1EN)
+            APB1EN: mmio.Mmio(packed struct(u32) {
+                ///  TIMER1 timer clock enable
+                TIMER1EN: u1,
+                ///  TIMER2 timer clock enable
+                TIMER2EN: u1,
+                ///  TIMER3 timer clock enable
+                TIMER3EN: u1,
+                ///  TIMER4 timer clock enable
+                TIMER4EN: u1,
+                ///  TIMER5 timer clock enable
+                TIMER5EN: u1,
+                ///  TIMER6 timer clock enable
+                TIMER6EN: u1,
+                reserved11: u5,
+                ///  Window watchdog timer clock enable
+                WWDGTEN: u1,
+                reserved14: u2,
+                ///  SPI1 clock enable
+                SPI1EN: u1,
+                ///  SPI2 clock enable
+                SPI2EN: u1,
+                reserved17: u1,
+                ///  USART1 clock enable
+                USART1EN: u1,
+                ///  USART2 clock enable
+                USART2EN: u1,
+                ///  UART3 clock enable
+                UART3EN: u1,
+                ///  UART4 clock enable
+                UART4EN: u1,
+                ///  I2C0 clock enable
+                I2C0EN: u1,
+                ///  I2C1 clock enable
+                I2C1EN: u1,
+                reserved25: u2,
+                ///  CAN0 clock enable
+                CAN0EN: u1,
+                ///  CAN1 clock enable
+                CAN1EN: u1,
+                ///  Backup interface clock enable
+                BKPIEN: u1,
+                ///  Power control clock enable
+                PMUEN: u1,
+                ///  DAC clock enable
+                DACEN: u1,
+                padding: u2,
+            }),
+            ///  Backup domain control register (RCU_BDCTL)
+            BDCTL: mmio.Mmio(packed struct(u32) {
+                ///  LXTAL enable
+                LXTALEN: u1,
+                ///  External low-speed oscillator stabilization
+                LXTALSTB: u1,
+                ///  LXTAL bypass mode enable
+                LXTALBPS: u1,
+                reserved8: u5,
+                ///  RTC clock entry selection
+                RTCSRC: u2,
+                reserved15: u5,
+                ///  RTC clock enable
+                RTCEN: u1,
+                ///  Backup domain reset
+                BKPRST: u1,
+                padding: u15,
+            }),
+            ///  Reset source /clock register (RCU_RSTSCK)
+            RSTSCK: mmio.Mmio(packed struct(u32) {
+                ///  IRC40K enable
+                IRC40KEN: u1,
+                ///  IRC40K stabilization
+                IRC40KSTB: u1,
+                reserved24: u22,
+                ///  Reset flag clear
+                RSTFC: u1,
+                reserved26: u1,
+                ///  External PIN reset flag
+                EPRSTF: u1,
+                ///  Power reset flag
+                PORRSTF: u1,
+                ///  Software reset flag
+                SWRSTF: u1,
+                ///  Free Watchdog timer reset flag
+                FWDGTRSTF: u1,
+                ///  Window watchdog timer reset flag
+                WWDGTRSTF: u1,
+                ///  Low-power reset flag
+                LPRSTF: u1,
+            }),
+            ///  AHB reset register
+            AHBRST: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  USBFS reset
+                USBFSRST: u1,
+                padding: u19,
+            }),
+            ///  Clock Configuration register 1
+            CFG1: mmio.Mmio(packed struct(u32) {
+                ///  PREDV0 division factor
+                PREDV0: u4,
+                ///  PREDV1 division factor
+                PREDV1: u4,
+                ///  The PLL1 clock multiplication factor
+                PLL1MF: u4,
+                ///  The PLL2 clock multiplication factor
+                PLL2MF: u4,
+                ///  PREDV0 input Clock Source Selection
+                PREDV0SEL: u1,
+                ///  I2S1 Clock Source Selection
+                I2S1SEL: u1,
+                ///  I2S2 Clock Source Selection
+                I2S2SEL: u1,
+                padding: u13,
+            }),
+            reserved52: [4]u8,
+            ///  Deep sleep mode Voltage register
+            DSV: mmio.Mmio(packed struct(u32) {
+                ///  Deep-sleep mode voltage select
+                DSLPVS: u2,
+                padding: u30,
+            }),
+        };
+
+        ///  Real-time clock
+        pub const RTC = extern struct {
+            ///  RTC interrupt enable register
+            INTEN: mmio.Mmio(packed struct(u32) {
+                ///  Second interrupt
+                SCIE: u1,
+                ///  Alarm interrupt enable
+                ALRMIE: u1,
+                ///  Overflow interrupt enable
+                OVIE: u1,
+                padding: u29,
+            }),
+            ///  control register
+            CTL: mmio.Mmio(packed struct(u32) {
+                ///  Sencond interrupt flag
+                SCIF: u1,
+                ///  Alarm interrupt flag
+                ALRMIF: u1,
+                ///  Overflow interrupt flag
+                OVIF: u1,
+                ///  Registers synchronized flag
+                RSYNF: u1,
+                ///  Configuration mode flag
+                CMF: u1,
+                ///  Last write operation finished flag
+                LWOFF: u1,
+                padding: u26,
+            }),
+            ///  RTC prescaler high register
+            PSCH: mmio.Mmio(packed struct(u32) {
+                padding: u32,
+            }),
+            ///  RTC prescaler low register
+            PSCL: mmio.Mmio(packed struct(u32) {
+                padding: u32,
+            }),
+            ///  RTC divider high register
+            DIVH: mmio.Mmio(packed struct(u32) {
+                ///  RTC divider value high
+                DIV: u4,
+                padding: u28,
+            }),
+            ///  RTC divider low register
+            DIVL: mmio.Mmio(packed struct(u32) {
+                ///  RTC divider value low
+                DIV: u16,
+                padding: u16,
+            }),
+            ///  RTC counter high register
+            CNTH: mmio.Mmio(packed struct(u32) {
+                ///  RTC counter value high
+                CNT: u16,
+                padding: u16,
+            }),
+            ///  RTC counter low register
+            CNTL: mmio.Mmio(packed struct(u32) {
+                ///  RTC counter value low
+                CNT: u16,
+                padding: u16,
+            }),
+        };
+
+        ///  Serial peripheral interface
+        pub const SPI0 = extern struct {
+            ///  control register 0
+            CTL0: mmio.Mmio(packed struct(u16) {
+                ///  Clock Phase Selection
+                CKPH: u1,
+                ///  Clock polarity Selection
+                CKPL: u1,
+                ///  Master Mode Enable
+                MSTMOD: u1,
+                ///  Master Clock Prescaler Selection
+                PSC: u3,
+                ///  SPI enable
+                SPIEN: u1,
+                ///  LSB First Mode
+                LF: u1,
+                ///  NSS Pin Selection In NSS Software Mode
+                SWNSS: u1,
+                ///  NSS Software Mode Selection
+                SWNSSEN: u1,
+                ///  Receive only
+                RO: u1,
+                ///  Data frame format
+                FF16: u1,
+                ///  CRC Next Transfer
+                CRCNT: u1,
+                ///  CRC Calculation Enable
+                CRCEN: u1,
+                ///  Bidirectional Transmit output enable
+                BDOEN: u1,
+                ///  Bidirectional enable
+                BDEN: u1,
+            }),
+            reserved4: [2]u8,
+            ///  control register 1
+            CTL1: mmio.Mmio(packed struct(u16) {
+                ///  Rx buffer DMA enable
+                DMAREN: u1,
+                ///  Transmit Buffer DMA Enable
+                DMATEN: u1,
+                ///  Drive NSS Output
+                NSSDRV: u1,
+                ///  SPI NSS pulse mode enable
+                NSSP: u1,
+                ///  SPI TI mode enable
+                TMOD: u1,
+                ///  Error interrupt enable
+                ERRIE: u1,
+                ///  RX buffer not empty interrupt enable
+                RBNEIE: u1,
+                ///  Tx buffer empty interrupt enable
+                TBEIE: u1,
+                padding: u8,
+            }),
+            reserved8: [2]u8,
+            ///  status register
+            STAT: mmio.Mmio(packed struct(u16) {
+                ///  Receive Buffer Not Empty
+                RBNE: u1,
+                ///  Transmit Buffer Empty
+                TBE: u1,
+                ///  I2S channel side
+                I2SCH: u1,
+                ///  Transmission underrun error bit
+                TXURERR: u1,
+                ///  SPI CRC Error Bit
+                CRCERR: u1,
+                ///  SPI Configuration error
+                CONFERR: u1,
+                ///  Reception Overrun Error Bit
+                RXORERR: u1,
+                ///  Transmitting On-going Bit
+                TRANS: u1,
+                ///  Format error
+                FERR: u1,
+                padding: u7,
+            }),
+            reserved12: [2]u8,
+            ///  data register
+            DATA: mmio.Mmio(packed struct(u16) {
+                ///  Data transfer register
+                SPI_DATA: u16,
+            }),
+            reserved16: [2]u8,
+            ///  CRC polynomial register
+            CRCPOLY: mmio.Mmio(packed struct(u16) {
+                ///  CRC polynomial value
+                CRCPOLY: u16,
+            }),
+            reserved20: [2]u8,
+            ///  RX CRC register
+            RCRC: mmio.Mmio(packed struct(u16) {
+                ///  RX CRC value
+                RCRC: u16,
+            }),
+            reserved24: [2]u8,
+            ///  TX CRC register
+            TCRC: mmio.Mmio(packed struct(u16) {
+                ///  Tx CRC value
+                TCRC: u16,
+            }),
+            reserved28: [2]u8,
+            ///  I2S control register
+            I2SCTL: mmio.Mmio(packed struct(u16) {
+                ///  Channel length (number of bits per audio channel)
+                CHLEN: u1,
+                ///  Data length
+                DTLEN: u2,
+                ///  Idle state clock polarity
+                CKPL: u1,
+                ///  I2S standard selection
+                I2SSTD: u2,
+                reserved7: u1,
+                ///  PCM frame synchronization mode
+                PCMSMOD: u1,
+                ///  I2S operation mode
+                I2SOPMOD: u2,
+                ///  I2S Enable
+                I2SEN: u1,
+                ///  I2S mode selection
+                I2SSEL: u1,
+                padding: u4,
+            }),
+            reserved32: [2]u8,
+            ///  I2S prescaler register
+            I2SPSC: mmio.Mmio(packed struct(u16) {
+                ///  Dividing factor for the prescaler
+                DIV: u8,
+                ///  Odd factor for the prescaler
+                OF: u1,
+                ///  I2S_MCK output enable
+                MCKOEN: u1,
+                padding: u6,
+            }),
+        };
+
+        ///  Universal asynchronous receiver transmitter
+        pub const UART3 = extern struct {
+            ///  Status register
+            STAT: mmio.Mmio(packed struct(u32) {
+                ///  Parity error flag
+                PERR: u1,
+                ///  Frame error flag
+                FERR: u1,
+                ///  Noise error flag
+                NERR: u1,
+                ///  Overrun error
+                ORERR: u1,
+                ///  IDLE frame detected flag
+                IDLEF: u1,
+                ///  Read data buffer not empty
+                RBNE: u1,
+                ///  Transmission complete
+                TC: u1,
+                ///  Transmit data buffer empty
+                TBE: u1,
+                ///  LIN break detection flag
+                LBDF: u1,
+                padding: u23,
+            }),
+            ///  Data register
+            DATA: mmio.Mmio(packed struct(u32) {
+                ///  Transmit or read data value
+                DATA: u9,
+                padding: u23,
+            }),
+            ///  Baud rate register
+            BAUD: mmio.Mmio(packed struct(u32) {
+                ///  Fraction part of baud-rate divider
+                FRADIV: u4,
+                ///  Integer part of baud-rate divider
+                INTDIV: u12,
+                padding: u16,
+            }),
+            ///  Control register 0
+            CTL0: mmio.Mmio(packed struct(u32) {
+                ///  Send break command
+                SBKCMD: u1,
+                ///  Receiver wakeup from mute mode
+                RWU: u1,
+                ///  Receiver enable
+                REN: u1,
+                ///  Transmitter enable
+                TEN: u1,
+                ///  IDLE line detected interrupt enable
+                IDLEIE: u1,
+                ///  Read data buffer not empty interrupt and overrun error interrupt enable
+                RBNEIE: u1,
+                ///  Transmission complete interrupt enable
+                TCIE: u1,
+                ///  Transmitter buffer empty interrupt enable
+                TBEIE: u1,
+                ///  Parity error interrupt enable
+                PERRIE: u1,
+                ///  Parity mode
+                PM: u1,
+                ///  Parity check function enable
+                PCEN: u1,
+                ///  Wakeup method in mute mode
+                WM: u1,
+                ///  Word length
+                WL: u1,
+                ///  USART enable
+                UEN: u1,
+                padding: u18,
+            }),
+            ///  Control register 1
+            CTL1: mmio.Mmio(packed struct(u32) {
+                ///  Address of the USART
+                ADDR: u4,
+                reserved5: u1,
+                ///  LIN break frame length
+                LBLEN: u1,
+                ///  LIN break detection interrupt enable
+                LBDIE: u1,
+                reserved12: u5,
+                ///  STOP bits length
+                STB: u2,
+                ///  LIN mode enable
+                LMEN: u1,
+                padding: u17,
+            }),
+            ///  Control register 2
+            CTL2: mmio.Mmio(packed struct(u32) {
+                ///  Error interrupt enable
+                ERRIE: u1,
+                ///  IrDA mode enable
+                IREN: u1,
+                ///  IrDA low-power
+                IRLP: u1,
+                ///  Half-duplex selection
+                HDEN: u1,
+                reserved6: u2,
+                ///  DMA request enable for reception
+                DENR: u1,
+                ///  DMA request enable for transmission
+                DENT: u1,
+                padding: u24,
+            }),
+            ///  Guard time and prescaler register
+            GP: mmio.Mmio(packed struct(u32) {
+                ///  Prescaler value
+                PSC: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  Universal synchronous asynchronous receiver transmitter
+        pub const USART0 = extern struct {
+            ///  Status register
+            STAT: mmio.Mmio(packed struct(u32) {
+                ///  Parity error flag
+                PERR: u1,
+                ///  Frame error flag
+                FERR: u1,
+                ///  Noise error flag
+                NERR: u1,
+                ///  Overrun error
+                ORERR: u1,
+                ///  IDLE frame detected flag
+                IDLEF: u1,
+                ///  Read data buffer not empty
+                RBNE: u1,
+                ///  Transmission complete
+                TC: u1,
+                ///  Transmit data buffer empty
+                TBE: u1,
+                ///  LIN break detection flag
+                LBDF: u1,
+                ///  CTS change flag
+                CTSF: u1,
+                padding: u22,
+            }),
+            ///  Data register
+            DATA: mmio.Mmio(packed struct(u32) {
+                ///  Transmit or read data value
+                DATA: u9,
+                padding: u23,
+            }),
+            ///  Baud rate register
+            BAUD: mmio.Mmio(packed struct(u32) {
+                ///  Fraction part of baud-rate divider
+                FRADIV: u4,
+                ///  Integer part of baud-rate divider
+                INTDIV: u12,
+                padding: u16,
+            }),
+            ///  Control register 0
+            CTL0: mmio.Mmio(packed struct(u32) {
+                ///  Send break command
+                SBKCMD: u1,
+                ///  Receiver wakeup from mute mode
+                RWU: u1,
+                ///  Receiver enable
+                REN: u1,
+                ///  Transmitter enable
+                TEN: u1,
+                ///  IDLE line detected interrupt enable
+                IDLEIE: u1,
+                ///  Read data buffer not empty interrupt and overrun error interrupt enable
+                RBNEIE: u1,
+                ///  Transmission complete interrupt enable
+                TCIE: u1,
+                ///  Transmitter buffer empty interrupt enable
+                TBEIE: u1,
+                ///  Parity error interrupt enable
+                PERRIE: u1,
+                ///  Parity mode
+                PM: u1,
+                ///  Parity check function enable
+                PCEN: u1,
+                ///  Wakeup method in mute mode
+                WM: u1,
+                ///  Word length
+                WL: u1,
+                ///  USART enable
+                UEN: u1,
+                padding: u18,
+            }),
+            ///  Control register 1
+            CTL1: mmio.Mmio(packed struct(u32) {
+                ///  Address of the USART
+                ADDR: u4,
+                reserved5: u1,
+                ///  LIN break frame length
+                LBLEN: u1,
+                ///  LIN break detection interrupt enable
+                LBDIE: u1,
+                reserved8: u1,
+                ///  CK Length
+                CLEN: u1,
+                ///  Clock phase
+                CPH: u1,
+                ///  Clock polarity
+                CPL: u1,
+                ///  CK pin enable
+                CKEN: u1,
+                ///  STOP bits length
+                STB: u2,
+                ///  LIN mode enable
+                LMEN: u1,
+                padding: u17,
+            }),
+            ///  Control register 2
+            CTL2: mmio.Mmio(packed struct(u32) {
+                ///  Error interrupt enable
+                ERRIE: u1,
+                ///  IrDA mode enable
+                IREN: u1,
+                ///  IrDA low-power
+                IRLP: u1,
+                ///  Half-duplex selection
+                HDEN: u1,
+                ///  Smartcard NACK enable
+                NKEN: u1,
+                ///  Smartcard mode enable
+                SCEN: u1,
+                ///  DMA request enable for reception
+                DENR: u1,
+                ///  DMA request enable for transmission
+                DENT: u1,
+                ///  RTS enable
+                RTSEN: u1,
+                ///  CTS enable
+                CTSEN: u1,
+                ///  CTS interrupt enable
+                CTSIE: u1,
+                padding: u21,
+            }),
+            ///  Guard time and prescaler register
+            GP: mmio.Mmio(packed struct(u32) {
+                ///  Prescaler value
+                PSC: u8,
+                ///  Guard time value in Smartcard mode
+                GUAT: u8,
+                padding: u16,
+            }),
+        };
+
+        ///  Advanced-timers
+        pub const TIMER0 = extern struct {
+            ///  control register 0
+            CTL0: mmio.Mmio(packed struct(u16) {
+                ///  Counter enable
+                CEN: u1,
+                ///  Update disable
+                UPDIS: u1,
+                ///  Update source
+                UPS: u1,
+                ///  Single pulse mode
+                SPM: u1,
+                ///  Direction
+                DIR: u1,
+                ///  Counter aligns mode selection
+                CAM: u2,
+                ///  Auto-reload shadow enable
+                ARSE: u1,
+                ///  Clock division
+                CKDIV: u2,
+                padding: u6,
+            }),
+            reserved4: [2]u8,
+            ///  control register 1
+            CTL1: mmio.Mmio(packed struct(u16) {
+                ///  Commutation control shadow enable
+                CCSE: u1,
+                reserved2: u1,
+                ///  Commutation control shadow register update control
+                CCUC: u1,
+                ///  DMA request source selection
+                DMAS: u1,
+                ///  Master mode control
+                MMC: u3,
+                ///  Channel 0 trigger input selection
+                TI0S: u1,
+                ///  Idle state of channel 0 output
+                ISO0: u1,
+                ///  Idle state of channel 0 complementary output
+                ISO0N: u1,
+                ///  Idle state of channel 1 output
+                ISO1: u1,
+                ///  Idle state of channel 1 complementary output
+                ISO1N: u1,
+                ///  Idle state of channel 2 output
+                ISO2: u1,
+                ///  Idle state of channel 2 complementary output
+                ISO2N: u1,
+                ///  Idle state of channel 3 output
+                ISO3: u1,
+                padding: u1,
+            }),
+            reserved8: [2]u8,
+            ///  slave mode configuration register
+            SMCFG: mmio.Mmio(packed struct(u16) {
+                ///  Slave mode selection
+                SMC: u3,
+                reserved4: u1,
+                ///  Trigger selection
+                TRGS: u3,
+                ///  Master/Slave mode
+                MSM: u1,
+                ///  External trigger filter control
+                ETFC: u4,
+                ///  External trigger prescaler
+                ETPSC: u2,
+                ///  Part of SMC for enable External clock mode1
+                SMC1: u1,
+                ///  External trigger polarity
+                ETP: u1,
+            }),
+            reserved12: [2]u8,
+            ///  DMA/Interrupt enable register
+            DMAINTEN: mmio.Mmio(packed struct(u16) {
+                ///  Update interrupt enable
+                UPIE: u1,
+                ///  Channel 0 capture/compare interrupt enable
+                CH0IE: u1,
+                ///  Channel 1 capture/compare interrupt enable
+                CH1IE: u1,
+                ///  Channel 2 capture/compare interrupt enable
+                CH2IE: u1,
+                ///  Channel 3 capture/compare interrupt enable
+                CH3IE: u1,
+                ///  commutation interrupt enable
+                CMTIE: u1,
+                ///  Trigger interrupt enable
+                TRGIE: u1,
+                ///  Break interrupt enable
+                BRKIE: u1,
+                ///  Update DMA request enable
+                UPDEN: u1,
+                ///  Channel 0 capture/compare DMA request enable
+                CH0DEN: u1,
+                ///  Channel 1 capture/compare DMA request enable
+                CH1DEN: u1,
+                ///  Channel 2 capture/compare DMA request enable
+                CH2DEN: u1,
+                ///  Channel 3 capture/compare DMA request enable
+                CH3DEN: u1,
+                ///  Commutation DMA request enable
+                CMTDEN: u1,
+                ///  Trigger DMA request enable
+                TRGDEN: u1,
+                padding: u1,
+            }),
+            reserved16: [2]u8,
+            ///  Interrupt flag register
+            INTF: mmio.Mmio(packed struct(u16) {
+                ///  Update interrupt flag
+                UPIF: u1,
+                ///  Channel 0 capture/compare interrupt flag
+                CH0IF: u1,
+                ///  Channel 1 capture/compare interrupt flag
+                CH1IF: u1,
+                ///  Channel 2 capture/compare interrupt flag
+                CH2IF: u1,
+                ///  Channel 3 capture/compare interrupt flag
+                CH3IF: u1,
+                ///  Channel commutation interrupt flag
+                CMTIF: u1,
+                ///  Trigger interrupt flag
+                TRGIF: u1,
+                ///  Break interrupt flag
+                BRKIF: u1,
+                reserved9: u1,
+                ///  Channel 0 over capture flag
+                CH0OF: u1,
+                ///  Channel 1 over capture flag
+                CH1OF: u1,
+                ///  Channel 2 over capture flag
+                CH2OF: u1,
+                ///  Channel 3 over capture flag
+                CH3OF: u1,
+                padding: u3,
+            }),
+            reserved20: [2]u8,
+            ///  Software event generation register
+            SWEVG: mmio.Mmio(packed struct(u16) {
+                ///  Update event generation
+                UPG: u1,
+                ///  Channel 0 capture or compare event generation
+                CH0G: u1,
+                ///  Channel 1 capture or compare event generation
+                CH1G: u1,
+                ///  Channel 2 capture or compare event generation
+                CH2G: u1,
+                ///  Channel 3 capture or compare event generation
+                CH3G: u1,
+                ///  Channel commutation event generation
+                CMTG: u1,
+                ///  Trigger event generation
+                TRGG: u1,
+                ///  Break event generation
+                BRKG: u1,
+                padding: u8,
+            }),
+            reserved24: [2]u8,
+            ///  Channel control register 0 (output mode)
+            CHCTL0_Output: mmio.Mmio(packed struct(u16) {
+                ///  Channel 0 I/O mode selection
+                CH0MS: u2,
+                ///  Channel 0 output compare fast enable
+                CH0COMFEN: u1,
+                ///  Channel 0 compare output shadow enable
+                CH0COMSEN: u1,
+                ///  Channel 0 compare output control
+                CH0COMCTL: u3,
+                ///  Channel 0 output compare clear enable
+                CH0COMCEN: u1,
+                ///  Channel 1 mode selection
+                CH1MS: u2,
+                ///  Channel 1 output compare fast enable
+                CH1COMFEN: u1,
+                ///  Channel 1 output compare shadow enable
+                CH1COMSEN: u1,
+                ///  Channel 1 compare output control
+                CH1COMCTL: u3,
+                ///  Channel 1 output compare clear enable
+                CH1COMCEN: u1,
+            }),
+            reserved28: [2]u8,
+            ///  Channel control register 1 (output mode)
+            CHCTL1_Output: mmio.Mmio(packed struct(u16) {
+                ///  Channel 2 I/O mode selection
+                CH2MS: u2,
+                ///  Channel 2 output compare fast enable
+                CH2COMFEN: u1,
+                ///  Channel 2 compare output shadow enable
+                CH2COMSEN: u1,
+                ///  Channel 2 compare output control
+                CH2COMCTL: u3,
+                ///  Channel 2 output compare clear enable
+                CH2COMCEN: u1,
+                ///  Channel 3 mode selection
+                CH3MS: u2,
+                ///  Channel 3 output compare fast enable
+                CH3COMFEN: u1,
+                ///  Channel 3 output compare shadow enable
+                CH3COMSEN: u1,
+                ///  Channel 3 compare output control
+                CH3COMCTL: u3,
+                ///  Channel 3 output compare clear enable
+                CH3COMCEN: u1,
+            }),
+            reserved32: [2]u8,
+            ///  Channel control register 2
+            CHCTL2: mmio.Mmio(packed struct(u16) {
+                ///  Channel 0 capture/compare function enable
+                CH0EN: u1,
+                ///  Channel 0 capture/compare function polarity
+                CH0P: u1,
+                ///  Channel 0 complementary output enable
+                CH0NEN: u1,
+                ///  Channel 0 complementary output polarity
+                CH0NP: u1,
+                ///  Channel 1 capture/compare function enable
+                CH1EN: u1,
+                ///  Channel 1 capture/compare function polarity
+                CH1P: u1,
+                ///  Channel 1 complementary output enable
+                CH1NEN: u1,
+                ///  Channel 1 complementary output polarity
+                CH1NP: u1,
+                ///  Channel 2 capture/compare function enable
+                CH2EN: u1,
+                ///  Channel 2 capture/compare function polarity
+                CH2P: u1,
+                ///  Channel 2 complementary output enable
+                CH2NEN: u1,
+                ///  Channel 2 complementary output polarity
+                CH2NP: u1,
+                ///  Channel 3 capture/compare function enable
+                CH3EN: u1,
+                ///  Channel 3 capture/compare function polarity
+                CH3P: u1,
+                padding: u2,
+            }),
+            reserved36: [2]u8,
+            ///  counter
+            CNT: mmio.Mmio(packed struct(u16) {
+                ///  current counter value
+                CNT: u16,
+            }),
+            reserved40: [2]u8,
+            ///  prescaler
+            PSC: mmio.Mmio(packed struct(u16) {
+                ///  Prescaler value of the counter clock
+                PSC: u16,
+            }),
+            reserved44: [2]u8,
+            ///  Counter auto reload register
+            CAR: mmio.Mmio(packed struct(u16) {
+                ///  Counter auto reload value
+                CARL: u16,
+            }),
+            reserved48: [2]u8,
+            ///  Counter repetition register
+            CREP: mmio.Mmio(packed struct(u16) {
+                ///  Counter repetition value
+                CREP: u8,
+                padding: u8,
+            }),
+            reserved52: [2]u8,
+            ///  Channel 0 capture/compare value register
+            CH0CV: mmio.Mmio(packed struct(u16) {
+                ///  Capture or compare value of channel0
+                CH0VAL: u16,
+            }),
+            reserved56: [2]u8,
+            ///  Channel 1 capture/compare value register
+            CH1CV: mmio.Mmio(packed struct(u16) {
+                ///  Capture or compare value of channel1
+                CH1VAL: u16,
+            }),
+            reserved60: [2]u8,
+            ///  Channel 2 capture/compare value register
+            CH2CV: mmio.Mmio(packed struct(u16) {
+                ///  Capture or compare value of channel 2
+                CH2VAL: u16,
+            }),
+            reserved64: [2]u8,
+            ///  Channel 3 capture/compare value register
+            CH3CV: mmio.Mmio(packed struct(u16) {
+                ///  Capture or compare value of channel 3
+                CH3VAL: u16,
+            }),
+            reserved68: [2]u8,
+            ///  channel complementary protection register
+            CCHP: mmio.Mmio(packed struct(u16) {
+                ///  Dead time configure
+                DTCFG: u8,
+                ///  Complementary register protect control
+                PROT: u2,
+                ///  Idle mode off-state configure
+                IOS: u1,
+                ///  Run mode off-state configure
+                ROS: u1,
+                ///  Break enable
+                BRKEN: u1,
+                ///  Break polarity
+                BRKP: u1,
+                ///  Output automatic enable
+                OAEN: u1,
+                ///  Primary output enable
+                POEN: u1,
+            }),
+            reserved72: [2]u8,
+            ///  DMA configuration register
+            DMACFG: mmio.Mmio(packed struct(u16) {
+                ///  DMA transfer access start address
+                DMATA: u5,
+                reserved8: u3,
+                ///  DMA transfer count
+                DMATC: u5,
+                padding: u3,
+            }),
+            reserved76: [2]u8,
+            ///  DMA transfer buffer register
+            DMATB: mmio.Mmio(packed struct(u16) {
+                ///  DMA transfer buffer
+                DMATB: u16,
+            }),
+        };
+
+        ///  General-purpose-timers
+        pub const TIMER1 = extern struct {
+            ///  control register 0
+            CTL0: mmio.Mmio(packed struct(u16) {
+                ///  Counter enable
+                CEN: u1,
+                ///  Update disable
+                UPDIS: u1,
+                ///  Update source
+                UPS: u1,
+                ///  Single pulse mode
+                SPM: u1,
+                ///  Direction
+                DIR: u1,
+                ///  Counter aligns mode selection
+                CAM: u2,
+                ///  Auto-reload shadow enable
+                ARSE: u1,
+                ///  Clock division
+                CKDIV: u2,
+                padding: u6,
+            }),
+            reserved4: [2]u8,
+            ///  control register 1
+            CTL1: mmio.Mmio(packed struct(u16) {
+                reserved3: u3,
+                ///  DMA request source selection
+                DMAS: u1,
+                ///  Master mode control
+                MMC: u3,
+                ///  Channel 0 trigger input selection
+                TI0S: u1,
+                padding: u8,
+            }),
+            reserved8: [2]u8,
+            ///  slave mode control register
+            SMCFG: mmio.Mmio(packed struct(u16) {
+                ///  Slave mode control
+                SMC: u3,
+                reserved4: u1,
+                ///  Trigger selection
+                TRGS: u3,
+                ///  Master-slave mode
+                MSM: u1,
+                ///  External trigger filter control
+                ETFC: u4,
+                ///  External trigger prescaler
+                ETPSC: u2,
+                ///  Part of SMC for enable External clock mode1
+                SMC1: u1,
+                ///  External trigger polarity
+                ETP: u1,
+            }),
+            reserved12: [2]u8,
+            ///  DMA/Interrupt enable register
+            DMAINTEN: mmio.Mmio(packed struct(u16) {
+                ///  Update interrupt enable
+                UPIE: u1,
+                ///  Channel 0 capture/compare interrupt enable
+                CH0IE: u1,
+                ///  Channel 1 capture/compare interrupt enable
+                CH1IE: u1,
+                ///  Channel 2 capture/compare interrupt enable
+                CH2IE: u1,
+                ///  Channel 3 capture/compare interrupt enable
+                CH3IE: u1,
+                reserved6: u1,
+                ///  Trigger interrupt enable
+                TRGIE: u1,
+                reserved8: u1,
+                ///  Update DMA request enable
+                UPDEN: u1,
+                ///  Channel 0 capture/compare DMA request enable
+                CH0DEN: u1,
+                ///  Channel 1 capture/compare DMA request enable
+                CH1DEN: u1,
+                ///  Channel 2 capture/compare DMA request enable
+                CH2DEN: u1,
+                ///  Channel 3 capture/compare DMA request enable
+                CH3DEN: u1,
+                reserved14: u1,
+                ///  Trigger DMA request enable
+                TRGDEN: u1,
+                padding: u1,
+            }),
+            reserved16: [2]u8,
+            ///  interrupt flag register
+            INTF: mmio.Mmio(packed struct(u16) {
+                ///  Update interrupt flag
+                UPIF: u1,
+                ///  Channel 0 capture/compare interrupt flag
+                CH0IF: u1,
+                ///  Channel 1 capture/compare interrupt flag
+                CH1IF: u1,
+                ///  Channel 2 capture/compare interrupt enable
+                CH2IF: u1,
+                ///  Channel 3 capture/compare interrupt enable
+                CH3IF: u1,
+                reserved6: u1,
+                ///  Trigger interrupt flag
+                TRGIF: u1,
+                reserved9: u2,
+                ///  Channel 0 over capture flag
+                CH0OF: u1,
+                ///  Channel 1 over capture flag
+                CH1OF: u1,
+                ///  Channel 2 over capture flag
+                CH2OF: u1,
+                ///  Channel 3 over capture flag
+                CH3OF: u1,
+                padding: u3,
+            }),
+            reserved20: [2]u8,
+            ///  event generation register
+            SWEVG: mmio.Mmio(packed struct(u16) {
+                ///  Update generation
+                UPG: u1,
+                ///  Channel 0 capture or compare event generation
+                CH0G: u1,
+                ///  Channel 1 capture or compare event generation
+                CH1G: u1,
+                ///  Channel 2 capture or compare event generation
+                CH2G: u1,
+                ///  Channel 3 capture or compare event generation
+                CH3G: u1,
+                reserved6: u1,
+                ///  Trigger event generation
+                TRGG: u1,
+                padding: u9,
+            }),
+            reserved24: [2]u8,
+            ///  Channel control register 0 (output mode)
+            CHCTL0_Output: mmio.Mmio(packed struct(u16) {
+                ///  Channel 0 I/O mode selection
+                CH0MS: u2,
+                ///  Channel 0 output compare fast enable
+                CH0COMFEN: u1,
+                ///  Channel 0 compare output shadow enable
+                CH0COMSEN: u1,
+                ///  Channel 0 compare output control
+                CH0COMCTL: u3,
+                ///  Channel 0 output compare clear enable
+                CH0COMCEN: u1,
+                ///  Channel 1 mode selection
+                CH1MS: u2,
+                ///  Channel 1 output compare fast enable
+                CH1COMFEN: u1,
+                ///  Channel 1 output compare shadow enable
+                CH1COMSEN: u1,
+                ///  Channel 1 compare output control
+                CH1COMCTL: u3,
+                ///  Channel 1 output compare clear enable
+                CH1COMCEN: u1,
+            }),
+            reserved28: [2]u8,
+            ///  Channel control register 1 (output mode)
+            CHCTL1_Output: mmio.Mmio(packed struct(u16) {
+                ///  Channel 2 I/O mode selection
+                CH2MS: u2,
+                ///  Channel 2 output compare fast enable
+                CH2COMFEN: u1,
+                ///  Channel 2 compare output shadow enable
+                CH2COMSEN: u1,
+                ///  Channel 2 compare output control
+                CH2COMCTL: u3,
+                ///  Channel 2 output compare clear enable
+                CH2COMCEN: u1,
+                ///  Channel 3 mode selection
+                CH3MS: u2,
+                ///  Channel 3 output compare fast enable
+                CH3COMFEN: u1,
+                ///  Channel 3 output compare shadow enable
+                CH3COMSEN: u1,
+                ///  Channel 3 compare output control
+                CH3COMCTL: u3,
+                ///  Channel 3 output compare clear enable
+                CH3COMCEN: u1,
+            }),
+            reserved32: [2]u8,
+            ///  Channel control register 2
+            CHCTL2: mmio.Mmio(packed struct(u16) {
+                ///  Channel 0 capture/compare function enable
+                CH0EN: u1,
+                ///  Channel 0 capture/compare function polarity
+                CH0P: u1,
+                reserved4: u2,
+                ///  Channel 1 capture/compare function enable
+                CH1EN: u1,
+                ///  Channel 1 capture/compare function polarity
+                CH1P: u1,
+                reserved8: u2,
+                ///  Channel 2 capture/compare function enable
+                CH2EN: u1,
+                ///  Channel 2 capture/compare function polarity
+                CH2P: u1,
+                reserved12: u2,
+                ///  Channel 3 capture/compare function enable
+                CH3EN: u1,
+                ///  Channel 3 capture/compare function polarity
+                CH3P: u1,
+                padding: u2,
+            }),
+            reserved36: [2]u8,
+            ///  Counter register
+            CNT: mmio.Mmio(packed struct(u16) {
+                ///  counter value
+                CNT: u16,
+            }),
+            reserved40: [2]u8,
+            ///  Prescaler register
+            PSC: mmio.Mmio(packed struct(u16) {
+                ///  Prescaler value of the counter clock
+                PSC: u16,
+            }),
+            reserved44: [2]u8,
+            ///  Counter auto reload register
+            CAR: mmio.Mmio(packed struct(u16) {
+                ///  Counter auto reload value
+                CARL: u16,
+            }),
+            reserved52: [6]u8,
+            ///  Channel 0 capture/compare value register
+            CH0CV: mmio.Mmio(packed struct(u32) {
+                ///  Capture or compare value of channel 0
+                CH0VAL: u16,
+                padding: u16,
+            }),
+            ///  Channel 1 capture/compare value register
+            CH1CV: mmio.Mmio(packed struct(u32) {
+                ///  Capture or compare value of channel1
+                CH1VAL: u16,
+                padding: u16,
+            }),
+            ///  Channel 2 capture/compare value register
+            CH2CV: mmio.Mmio(packed struct(u32) {
+                ///  Capture or compare value of channel 2
+                CH2VAL: u16,
+                padding: u16,
+            }),
+            ///  Channel 3 capture/compare value register
+            CH3CV: mmio.Mmio(packed struct(u32) {
+                ///  Capture or compare value of channel 3
+                CH3VAL: u16,
+                padding: u16,
+            }),
+            reserved72: [4]u8,
+            ///  DMA configuration register
+            DMACFG: mmio.Mmio(packed struct(u16) {
+                ///  DMA transfer access start address
+                DMATA: u5,
+                reserved8: u3,
+                ///  DMA transfer count
+                DMATC: u5,
+                padding: u3,
+            }),
+            reserved76: [2]u8,
+            ///  DMA transfer buffer register
+            DMATB: mmio.Mmio(packed struct(u32) {
+                ///  DMA transfer buffer
+                DMATB: u16,
+                padding: u16,
+            }),
+        };
+    };
+};
diff --git a/src/hals/GD32VF103.zig b/src/hals/GD32VF103.zig
new file mode 100644
index 000000000..8b5c72840
--- /dev/null
+++ b/src/hals/GD32VF103.zig
@@ -0,0 +1,112 @@
+const micro = @import("microzig");
+const peripherals = micro.chip.peripherals;
+const UART3 = peripherals.UART3;
+const UART4 = peripherals.UART4;
+
+pub const clock_frequencies = .{
+    .cpu = 8_000_000, // 8 MHz
+};
+
+pub fn parse_pin(comptime spec: []const u8) type {
+    const invalid_format_msg = "The given pin '" ++ spec ++ "' has an invalid format. Pins must follow the format \"P{Port}{Pin}\" scheme.";
+
+    if (spec[0] != 'P')
+        @compileError(invalid_format_msg);
+    if (spec[1] < 'A' or spec[1] > 'E')
+        @compileError(invalid_format_msg);
+
+    return struct {
+        const pin_number: comptime_int = @import("std").fmt.parseInt(u2, spec[2..], 10) catch @compileError(invalid_format_msg);
+        // 'A'...'E'
+        const gpio_port_name = spec[1..2];
+        const gpio_port = @field(peripherals, "GPIO" ++ gpio_port_name);
+        const suffix = @import("std").fmt.comptimePrint("{d}", .{pin_number});
+    };
+}
+
+fn set_reg_field(reg: anytype, comptime field_name: anytype, value: anytype) void {
+    var temp = reg.read();
+    @field(temp, field_name) = value;
+    reg.write(temp);
+}
+
+pub const gpio = struct {
+    pub fn set_output(comptime pin: type) void {
+        _ = pin;
+        // TODO: check if pin is already configured as output
+    }
+    pub fn set_input(comptime pin: type) void {
+        _ = pin;
+        // TODO: check if pin is already configured as input
+    }
+
+    pub fn read(comptime pin: type) micro.gpio.State {
+        _ = pin;
+        // TODO: check if pin is configured as input
+        return .low;
+    }
+
+    pub fn write(comptime pin: type, state: micro.gpio.State) void {
+        _ = pin;
+        _ = state;
+        // TODO: check if pin is configured as output
+    }
+};
+
+pub const uart = struct {
+    pub const DataBits = enum(u2) {
+        five = 0,
+        six = 1,
+        seven = 2,
+        eight = 3,
+    };
+
+    pub const StopBits = enum(u1) {
+        one = 0,
+        two = 1,
+    };
+
+    pub const Parity = enum(u2) {
+        odd = 0,
+        even = 1,
+        mark = 2,
+        space = 3,
+    };
+};
+
+pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
+    if (pins.tx != null or pins.rx != null)
+        @compileError("TODO: custom pins are not currently supported");
+
+    return struct {
+        const UARTn = switch (index) {
+            0 => UART3,
+            1 => UART4,
+            else => @compileError("GD32VF103 has 2 UARTs available."),
+        };
+        const Self = @This();
+
+        pub fn init(config: micro.uart.Config) !Self {
+            _ = config;
+            return Self{};
+        }
+
+        pub fn can_write(self: Self) bool {
+            _ = self;
+            return false;
+        }
+        pub fn tx(self: Self, ch: u8) void {
+            _ = ch;
+            while (!self.can_write()) {} // Wait for Previous transmission
+        }
+
+        pub fn can_read(self: Self) bool {
+            _ = self;
+            return false;
+        }
+        pub fn rx(self: Self) u8 {
+            while (!self.can_read()) {} // Wait till the data is received
+            return 1; // Read received data
+        }
+    };
+}

From 7d81ecf65473cfa19ae7f8cbe9a7961dd79371d0 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 19 Feb 2023 09:39:12 -0500
Subject: [PATCH 047/286] Regz rewrite (#20)

* update to new regz output

* snake case

* update with changes to microzig

* remove symlink

* add microzig submodule
---
 build.zig                              |    48 +-
 deps/microzig                          |     2 +-
 examples/adc.zig                       |     4 +-
 examples/blinky.zig                    |     2 +-
 examples/blinky_core1.zig              |     8 +-
 examples/gpio_clk.zig                  |     2 +-
 examples/pwm.zig                       |     6 +-
 examples/uart.zig                      |     8 +-
 src/boards.zig                         |    15 +
 src/{ => boards}/raspberry_pi_pico.zig |     0
 src/chips.zig                          |    25 +
 src/chips/RP2040.json                  | 43672 +++++++++++++++++++++++
 src/chips/RP2040.zig                   | 18145 ++++++++++
 src/hal.zig                            |     2 +-
 src/hal/adc.zig                        |    43 +-
 src/hal/clocks.zig                     |   150 +-
 src/hal/gpio.zig                       |    59 +-
 src/hal/irq.zig                        |     6 +-
 src/hal/multicore.zig                  |    46 +-
 src/hal/pins.zig                       |    66 +-
 src/hal/pll.zig                        |    78 +-
 src/hal/pwm.zig                        |    69 +-
 src/hal/resets.zig                     |    14 +-
 src/hal/time.zig                       |    24 +-
 src/hal/uart.zig                       |   121 +-
 src/hal/util.zig                       |     8 +-
 src/rp2040.zig                         | 28794 ---------------
 27 files changed, 62224 insertions(+), 29193 deletions(-)
 create mode 100644 src/boards.zig
 rename src/{ => boards}/raspberry_pi_pico.zig (100%)
 create mode 100644 src/chips.zig
 create mode 100644 src/chips/RP2040.json
 create mode 100644 src/chips/RP2040.zig
 delete mode 100644 src/rp2040.zig

diff --git a/build.zig b/build.zig
index 35bad24c9..51bb874e5 100644
--- a/build.zig
+++ b/build.zig
@@ -5,10 +5,10 @@ const comptimePrint = std.fmt.comptimePrint;
 
 pub const microzig = @import("deps/microzig/src/main.zig");
 
-const chip_path = comptimePrint("{s}/src/rp2040.zig", .{root()});
-const board_path = comptimePrint("{s}/src/raspberry_pi_pico.zig", .{root()});
-const hal_path = comptimePrint("{s}/src/hal.zig", .{root()});
-const linkerscript_path = comptimePrint("{s}/rp2040.ld", .{root()});
+const chips = @import("src/chips.zig");
+const boards = @import("src/boards.zig");
+
+const linkerscript_path = root() ++ "rp2040.ld";
 
 pub const BuildOptions = struct {
     optimize: std.builtin.OptimizeMode,
@@ -19,32 +19,14 @@ pub fn addPiPicoExecutable(
     name: []const u8,
     source: []const u8,
     options: BuildOptions,
-) microzig.EmbeddedExecutable {
-    const rp2040 = microzig.Chip{
-        .name = "RP2040",
-        .path = chip_path,
-        .cpu = microzig.cpus.cortex_m0plus,
-        .memory_regions = &.{
-            .{ .kind = .flash, .offset = 0x10000100, .length = (2048 * 1024) - 256 },
-            .{ .kind = .flash, .offset = 0x10000000, .length = 256 },
-            .{ .kind = .ram, .offset = 0x20000000, .length = 256 * 1024 },
-        },
-    };
-
-    const raspberry_pi_pico = microzig.Board{
-        .name = "Raspberry Pi Pico",
-        .path = board_path,
-        .chip = rp2040,
-    };
-
+) *microzig.EmbeddedExecutable {
     const ret = microzig.addEmbeddedExecutable(
         builder,
         name,
         source,
-        .{ .board = raspberry_pi_pico },
+        .{ .board = boards.raspberry_pi_pico },
         .{
             .optimize = options.optimize,
-            .hal_module_path = .{ .path = hal_path },
         },
     );
     ret.inner.setLinkerScriptPath(.{ .path = linkerscript_path });
@@ -62,25 +44,27 @@ pub fn build(b: *Builder) !void {
 }
 
 fn root() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse ".";
+    return comptime (std.fs.path.dirname(@src().file) orelse ".") ++ "/";
 }
 
 pub const Examples = struct {
-    adc: microzig.EmbeddedExecutable,
-    blinky: microzig.EmbeddedExecutable,
-    blinky_core1: microzig.EmbeddedExecutable,
-    gpio_clk: microzig.EmbeddedExecutable,
-    pwm: microzig.EmbeddedExecutable,
-    uart: microzig.EmbeddedExecutable,
+    adc: *microzig.EmbeddedExecutable,
+    blinky: *microzig.EmbeddedExecutable,
+    blinky_core1: *microzig.EmbeddedExecutable,
+    gpio_clk: *microzig.EmbeddedExecutable,
+    pwm: *microzig.EmbeddedExecutable,
+    uart: *microzig.EmbeddedExecutable,
     //uart_pins: microzig.EmbeddedExecutable,
 
     pub fn init(b: *Builder, optimize: std.builtin.OptimizeMode) Examples {
         var ret: Examples = undefined;
         inline for (@typeInfo(Examples).Struct.fields) |field| {
+            const path = comptime root() ++ "examples/" ++ field.name ++ ".zig";
+
             @field(ret, field.name) = addPiPicoExecutable(
                 b,
                 field.name,
-                comptime root() ++ "/examples/" ++ field.name ++ ".zig",
+                path,
                 .{ .optimize = optimize },
             );
         }
diff --git a/deps/microzig b/deps/microzig
index 9ccde9ff3..2d0ee5c47 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 9ccde9ff371b355394f65eacb6b51c5880768505
+Subproject commit 2d0ee5c4731de1d81afb9c8e08ba4e8c2c2cfbf3
diff --git a/examples/adc.zig b/examples/adc.zig
index f8e8c6618..9800e9157 100644
--- a/examples/adc.zig
+++ b/examples/adc.zig
@@ -27,11 +27,11 @@ pub fn init() void {
         .clock_config = rp2040.clock_config,
     });
 
-    rp2040.uart.initLogger(uart);
+    rp2040.uart.init_logger(uart);
 }
 
 pub fn main() void {
-    while (true) : (time.sleepMs(1000)) {
+    while (true) : (time.sleep_ms(1000)) {
         const sample = temp_sensor.read();
         std.log.info("temp value: {}", .{sample});
     }
diff --git a/examples/blinky.zig b/examples/blinky.zig
index ea3f2d8fd..5632fe349 100644
--- a/examples/blinky.zig
+++ b/examples/blinky.zig
@@ -15,6 +15,6 @@ pub fn main() !void {
 
     while (true) {
         pins.led.toggle();
-        time.sleepMs(250);
+        time.sleep_ms(250);
     }
 }
diff --git a/examples/blinky_core1.zig b/examples/blinky_core1.zig
index a549f3094..b3fdd04da 100644
--- a/examples/blinky_core1.zig
+++ b/examples/blinky_core1.zig
@@ -11,17 +11,17 @@ const led = 25;
 fn core1() void {
     while (true) {
         gpio.put(led, 1);
-        time.sleepMs(250);
+        time.sleep_ms(250);
         gpio.put(led, 0);
-        time.sleepMs(250);
+        time.sleep_ms(250);
     }
 }
 
 pub fn main() !void {
     gpio.init(led);
-    gpio.setDir(led, .out);
+    gpio.set_direction(led, .out);
 
-    multicore.launchCore1(core1);
+    multicore.launch_core1(core1);
 
     while (true) {
         microzig.cpu.wfi();
diff --git a/examples/gpio_clk.zig b/examples/gpio_clk.zig
index 52280e4a6..e66761c3b 100644
--- a/examples/gpio_clk.zig
+++ b/examples/gpio_clk.zig
@@ -16,6 +16,6 @@ pub fn init() void {
 }
 
 pub fn main() !void {
-    gpio.setFunction(gpout0_pin, .gpck);
+    gpio.set_function(gpout0_pin, .gpck);
     while (true) {}
 }
diff --git a/examples/pwm.zig b/examples/pwm.zig
index 9eff04393..d372ef4c2 100644
--- a/examples/pwm.zig
+++ b/examples/pwm.zig
@@ -13,11 +13,11 @@ const pin_config = rp2040.pins.GlobalConfiguration{
 
 pub fn main() !void {
     const pins = pin_config.apply();
-    pins.led.slice().setWrap(100);
-    pins.led.setLevel(10);
+    pins.led.slice().set_wrap(100);
+    pins.led.set_level(10);
     pins.led.slice().enable();
 
     while (true) {
-        time.sleepMs(250);
+        time.sleep_ms(250);
     }
 }
diff --git a/examples/uart.zig b/examples/uart.zig
index 7ccbe694a..6eb086415 100644
--- a/examples/uart.zig
+++ b/examples/uart.zig
@@ -24,7 +24,7 @@ pub const log = rp2040.uart.log;
 pub fn main() !void {
     gpio.reset();
     gpio.init(led);
-    gpio.setDir(led, .out);
+    gpio.set_direction(led, .out);
     gpio.put(led, 1);
 
     const uart = rp2040.uart.UART.init(uart_id, .{
@@ -34,15 +34,15 @@ pub fn main() !void {
         .clock_config = rp2040.clock_config,
     });
 
-    rp2040.uart.initLogger(uart);
+    rp2040.uart.init_logger(uart);
 
     var i: u32 = 0;
     while (true) : (i += 1) {
         gpio.put(led, 1);
         std.log.info("what {}", .{i});
-        time.sleepMs(500);
+        time.sleep_ms(500);
 
         gpio.put(led, 0);
-        time.sleepMs(500);
+        time.sleep_ms(500);
     }
 }
diff --git a/src/boards.zig b/src/boards.zig
new file mode 100644
index 000000000..432918247
--- /dev/null
+++ b/src/boards.zig
@@ -0,0 +1,15 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/src/main.zig");
+const chips = @import("chips.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse ".";
+}
+
+const board_path = std.fmt.comptimePrint("{s}/boards/raspberry_pi_pico.zig", .{root_dir()});
+
+pub const raspberry_pi_pico = microzig.Board{
+    .name = "Raspberry Pi Pico",
+    .source = .{ .path = board_path },
+    .chip = chips.rp2040,
+};
diff --git a/src/raspberry_pi_pico.zig b/src/boards/raspberry_pi_pico.zig
similarity index 100%
rename from src/raspberry_pi_pico.zig
rename to src/boards/raspberry_pi_pico.zig
diff --git a/src/chips.zig b/src/chips.zig
new file mode 100644
index 000000000..5e0d39a20
--- /dev/null
+++ b/src/chips.zig
@@ -0,0 +1,25 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/src/main.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse ".";
+}
+
+const chip_path = std.fmt.comptimePrint("{s}/chips/RP2040.zig", .{root_dir()});
+const hal_path = std.fmt.comptimePrint("{s}/hal.zig", .{root_dir()});
+const json_register_schema_path = std.fmt.comptimePrint("{s}/chips/RP2040.json", .{root_dir()});
+
+pub const rp2040 = microzig.Chip{
+    .name = "RP2040",
+    .source = .{ .path = chip_path },
+    .hal = .{ .path = hal_path },
+    .cpu = microzig.cpus.cortex_m0plus,
+    .memory_regions = &.{
+        .{ .kind = .flash, .offset = 0x10000100, .length = (2048 * 1024) - 256 },
+        .{ .kind = .flash, .offset = 0x10000000, .length = 256 },
+        .{ .kind = .ram, .offset = 0x20000000, .length = 256 * 1024 },
+    },
+    .json_register_schema = .{
+        .path = json_register_schema_path,
+    },
+};
diff --git a/src/chips/RP2040.json b/src/chips/RP2040.json
new file mode 100644
index 000000000..6d26913ee
--- /dev/null
+++ b/src/chips/RP2040.json
@@ -0,0 +1,43672 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "SCS": {
+        "description": "System Control Space",
+        "children": {
+          "register_groups": {
+            "SysTick": {
+              "description": "System Tick Timer",
+              "children": {
+                "registers": {
+                  "CTRL": {
+                    "description": "SysTick Control and Status Register",
+                    "offset": 0,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "ENABLE": {
+                          "offset": 0,
+                          "size": 1
+                        },
+                        "TICKINT": {
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "CLKSOURCE": {
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "COUNTFLAG": {
+                          "offset": 16,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "LOAD": {
+                    "description": "SysTick Reload Value Register",
+                    "offset": 4,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "RELOAD": {
+                          "offset": 0,
+                          "size": 24
+                        }
+                      }
+                    }
+                  },
+                  "VAL": {
+                    "description": "SysTick Current Value Register",
+                    "offset": 8,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "CURRENT": {
+                          "offset": 0,
+                          "size": 24
+                        }
+                      }
+                    }
+                  },
+                  "CALIB": {
+                    "description": "SysTick Calibration Register",
+                    "offset": 12,
+                    "size": 32,
+                    "access": "read-only",
+                    "children": {
+                      "fields": {
+                        "TENMS": {
+                          "offset": 0,
+                          "size": 24
+                        },
+                        "SKEW": {
+                          "offset": 30,
+                          "size": 1
+                        },
+                        "NOREF": {
+                          "offset": 31,
+                          "size": 1
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "SCB": {
+              "description": "System Control Block",
+              "children": {
+                "registers": {
+                  "CPUID": {
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only",
+                    "children": {
+                      "fields": {
+                        "REVISION": {
+                          "offset": 0,
+                          "size": 4
+                        },
+                        "PARTNO": {
+                          "offset": 4,
+                          "size": 12
+                        },
+                        "ARCHITECTURE": {
+                          "offset": 16,
+                          "size": 4
+                        },
+                        "VARIANT": {
+                          "offset": 20,
+                          "size": 4
+                        },
+                        "IMPLEMENTER": {
+                          "offset": 24,
+                          "size": 8
+                        }
+                      }
+                    }
+                  },
+                  "ICSR": {
+                    "description": "Interrupt Control and State Register",
+                    "offset": 4,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "VECTACTIVE": {
+                          "offset": 0,
+                          "size": 9
+                        },
+                        "VECTPENDING": {
+                          "offset": 12,
+                          "size": 9
+                        },
+                        "ISRPENDING": {
+                          "offset": 22,
+                          "size": 1
+                        },
+                        "ISRPREEMPT": {
+                          "offset": 23,
+                          "size": 1
+                        },
+                        "PENDSTCLR": {
+                          "offset": 25,
+                          "size": 1
+                        },
+                        "PENDSTSET": {
+                          "offset": 26,
+                          "size": 1
+                        },
+                        "PENDSVCLR": {
+                          "offset": 27,
+                          "size": 1
+                        },
+                        "PENDSVSET": {
+                          "offset": 28,
+                          "size": 1
+                        },
+                        "NMIPENDSET": {
+                          "offset": 31,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "AIRCR": {
+                    "description": "Application Interrupt and Reset Control Register",
+                    "offset": 12,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "VECTCLRACTIVE": {
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "SYSRESETREQ": {
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "ENDIANESS": {
+                          "offset": 15,
+                          "size": 1
+                        },
+                        "VECTKEY": {
+                          "offset": 16,
+                          "size": 16
+                        }
+                      }
+                    }
+                  },
+                  "SCR": {
+                    "description": "System Control Register",
+                    "offset": 16,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "SLEEPONEXIT": {
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "SLEEPDEEP": {
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "SEVONPEND": {
+                          "offset": 4,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "CCR": {
+                    "description": "Configuration Control Register",
+                    "offset": 20,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "UNALIGN_TRP": {
+                          "offset": 3,
+                          "size": 1
+                        },
+                        "STKALIGN": {
+                          "offset": 9,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "SHP": {
+                    "description": "System Handlers Priority Registers. [0] is RESERVED",
+                    "offset": 28,
+                    "size": 32
+                  },
+                  "SHCSR": {
+                    "description": "System Handler Control and State Register",
+                    "offset": 36,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "SVCALLPENDED": {
+                          "offset": 15,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "VTOR": {
+                    "description": "Vector Table Offset Register",
+                    "offset": 8,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "TBLOFF": {
+                          "offset": 8,
+                          "size": 24
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "NVIC": {
+              "description": "Nested Vectored Interrupt Controller",
+              "children": {
+                "registers": {
+                  "ISER": {
+                    "description": "Interrupt Set Enable Register",
+                    "offset": 0,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "XIP_IRQ": {
+                          "offset": 6,
+                          "size": 1
+                        },
+                        "CLOCKS_IRQ": {
+                          "offset": 17,
+                          "size": 1
+                        },
+                        "IO_IRQ_BANK0": {
+                          "offset": 13,
+                          "size": 1
+                        },
+                        "IO_IRQ_QSPI": {
+                          "offset": 14,
+                          "size": 1
+                        },
+                        "UART0_IRQ": {
+                          "offset": 20,
+                          "size": 1
+                        },
+                        "UART1_IRQ": {
+                          "offset": 21,
+                          "size": 1
+                        },
+                        "SPI0_IRQ": {
+                          "offset": 18,
+                          "size": 1
+                        },
+                        "SPI1_IRQ": {
+                          "offset": 19,
+                          "size": 1
+                        },
+                        "I2C0_IRQ": {
+                          "offset": 23,
+                          "size": 1
+                        },
+                        "I2C1_IRQ": {
+                          "offset": 24,
+                          "size": 1
+                        },
+                        "ADC_IRQ_FIFO": {
+                          "offset": 22,
+                          "size": 1
+                        },
+                        "PWM_IRQ_WRAP": {
+                          "offset": 4,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_0": {
+                          "offset": 0,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_1": {
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_2": {
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_3": {
+                          "offset": 3,
+                          "size": 1
+                        },
+                        "RTC_IRQ": {
+                          "offset": 25,
+                          "size": 1
+                        },
+                        "DMA_IRQ_0": {
+                          "offset": 11,
+                          "size": 1
+                        },
+                        "DMA_IRQ_1": {
+                          "offset": 12,
+                          "size": 1
+                        },
+                        "USBCTRL_IRQ": {
+                          "offset": 5,
+                          "size": 1
+                        },
+                        "PIO0_IRQ_0": {
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "PIO0_IRQ_1": {
+                          "offset": 8,
+                          "size": 1
+                        },
+                        "PIO1_IRQ_0": {
+                          "offset": 9,
+                          "size": 1
+                        },
+                        "PIO1_IRQ_1": {
+                          "offset": 10,
+                          "size": 1
+                        },
+                        "SIO_IRQ_PROC0": {
+                          "offset": 15,
+                          "size": 1
+                        },
+                        "SIO_IRQ_PROC1": {
+                          "offset": 16,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "ICER": {
+                    "description": "Interrupt Clear Enable Register",
+                    "offset": 128,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "XIP_IRQ": {
+                          "offset": 6,
+                          "size": 1
+                        },
+                        "CLOCKS_IRQ": {
+                          "offset": 17,
+                          "size": 1
+                        },
+                        "IO_IRQ_BANK0": {
+                          "offset": 13,
+                          "size": 1
+                        },
+                        "IO_IRQ_QSPI": {
+                          "offset": 14,
+                          "size": 1
+                        },
+                        "UART0_IRQ": {
+                          "offset": 20,
+                          "size": 1
+                        },
+                        "UART1_IRQ": {
+                          "offset": 21,
+                          "size": 1
+                        },
+                        "SPI0_IRQ": {
+                          "offset": 18,
+                          "size": 1
+                        },
+                        "SPI1_IRQ": {
+                          "offset": 19,
+                          "size": 1
+                        },
+                        "I2C0_IRQ": {
+                          "offset": 23,
+                          "size": 1
+                        },
+                        "I2C1_IRQ": {
+                          "offset": 24,
+                          "size": 1
+                        },
+                        "ADC_IRQ_FIFO": {
+                          "offset": 22,
+                          "size": 1
+                        },
+                        "PWM_IRQ_WRAP": {
+                          "offset": 4,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_0": {
+                          "offset": 0,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_1": {
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_2": {
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_3": {
+                          "offset": 3,
+                          "size": 1
+                        },
+                        "RTC_IRQ": {
+                          "offset": 25,
+                          "size": 1
+                        },
+                        "DMA_IRQ_0": {
+                          "offset": 11,
+                          "size": 1
+                        },
+                        "DMA_IRQ_1": {
+                          "offset": 12,
+                          "size": 1
+                        },
+                        "USBCTRL_IRQ": {
+                          "offset": 5,
+                          "size": 1
+                        },
+                        "PIO0_IRQ_0": {
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "PIO0_IRQ_1": {
+                          "offset": 8,
+                          "size": 1
+                        },
+                        "PIO1_IRQ_0": {
+                          "offset": 9,
+                          "size": 1
+                        },
+                        "PIO1_IRQ_1": {
+                          "offset": 10,
+                          "size": 1
+                        },
+                        "SIO_IRQ_PROC0": {
+                          "offset": 15,
+                          "size": 1
+                        },
+                        "SIO_IRQ_PROC1": {
+                          "offset": 16,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "ISPR": {
+                    "description": "Interrupt Set Pending Register",
+                    "offset": 256,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "XIP_IRQ": {
+                          "offset": 6,
+                          "size": 1
+                        },
+                        "CLOCKS_IRQ": {
+                          "offset": 17,
+                          "size": 1
+                        },
+                        "IO_IRQ_BANK0": {
+                          "offset": 13,
+                          "size": 1
+                        },
+                        "IO_IRQ_QSPI": {
+                          "offset": 14,
+                          "size": 1
+                        },
+                        "UART0_IRQ": {
+                          "offset": 20,
+                          "size": 1
+                        },
+                        "UART1_IRQ": {
+                          "offset": 21,
+                          "size": 1
+                        },
+                        "SPI0_IRQ": {
+                          "offset": 18,
+                          "size": 1
+                        },
+                        "SPI1_IRQ": {
+                          "offset": 19,
+                          "size": 1
+                        },
+                        "I2C0_IRQ": {
+                          "offset": 23,
+                          "size": 1
+                        },
+                        "I2C1_IRQ": {
+                          "offset": 24,
+                          "size": 1
+                        },
+                        "ADC_IRQ_FIFO": {
+                          "offset": 22,
+                          "size": 1
+                        },
+                        "PWM_IRQ_WRAP": {
+                          "offset": 4,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_0": {
+                          "offset": 0,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_1": {
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_2": {
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_3": {
+                          "offset": 3,
+                          "size": 1
+                        },
+                        "RTC_IRQ": {
+                          "offset": 25,
+                          "size": 1
+                        },
+                        "DMA_IRQ_0": {
+                          "offset": 11,
+                          "size": 1
+                        },
+                        "DMA_IRQ_1": {
+                          "offset": 12,
+                          "size": 1
+                        },
+                        "USBCTRL_IRQ": {
+                          "offset": 5,
+                          "size": 1
+                        },
+                        "PIO0_IRQ_0": {
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "PIO0_IRQ_1": {
+                          "offset": 8,
+                          "size": 1
+                        },
+                        "PIO1_IRQ_0": {
+                          "offset": 9,
+                          "size": 1
+                        },
+                        "PIO1_IRQ_1": {
+                          "offset": 10,
+                          "size": 1
+                        },
+                        "SIO_IRQ_PROC0": {
+                          "offset": 15,
+                          "size": 1
+                        },
+                        "SIO_IRQ_PROC1": {
+                          "offset": 16,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "ICPR": {
+                    "description": "Interrupt Clear Pending Register",
+                    "offset": 384,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "XIP_IRQ": {
+                          "offset": 6,
+                          "size": 1
+                        },
+                        "CLOCKS_IRQ": {
+                          "offset": 17,
+                          "size": 1
+                        },
+                        "IO_IRQ_BANK0": {
+                          "offset": 13,
+                          "size": 1
+                        },
+                        "IO_IRQ_QSPI": {
+                          "offset": 14,
+                          "size": 1
+                        },
+                        "UART0_IRQ": {
+                          "offset": 20,
+                          "size": 1
+                        },
+                        "UART1_IRQ": {
+                          "offset": 21,
+                          "size": 1
+                        },
+                        "SPI0_IRQ": {
+                          "offset": 18,
+                          "size": 1
+                        },
+                        "SPI1_IRQ": {
+                          "offset": 19,
+                          "size": 1
+                        },
+                        "I2C0_IRQ": {
+                          "offset": 23,
+                          "size": 1
+                        },
+                        "I2C1_IRQ": {
+                          "offset": 24,
+                          "size": 1
+                        },
+                        "ADC_IRQ_FIFO": {
+                          "offset": 22,
+                          "size": 1
+                        },
+                        "PWM_IRQ_WRAP": {
+                          "offset": 4,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_0": {
+                          "offset": 0,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_1": {
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_2": {
+                          "offset": 2,
+                          "size": 1
+                        },
+                        "TIMER_IRQ_3": {
+                          "offset": 3,
+                          "size": 1
+                        },
+                        "RTC_IRQ": {
+                          "offset": 25,
+                          "size": 1
+                        },
+                        "DMA_IRQ_0": {
+                          "offset": 11,
+                          "size": 1
+                        },
+                        "DMA_IRQ_1": {
+                          "offset": 12,
+                          "size": 1
+                        },
+                        "USBCTRL_IRQ": {
+                          "offset": 5,
+                          "size": 1
+                        },
+                        "PIO0_IRQ_0": {
+                          "offset": 7,
+                          "size": 1
+                        },
+                        "PIO0_IRQ_1": {
+                          "offset": 8,
+                          "size": 1
+                        },
+                        "PIO1_IRQ_0": {
+                          "offset": 9,
+                          "size": 1
+                        },
+                        "PIO1_IRQ_1": {
+                          "offset": 10,
+                          "size": 1
+                        },
+                        "SIO_IRQ_PROC0": {
+                          "offset": 15,
+                          "size": 1
+                        },
+                        "SIO_IRQ_PROC1": {
+                          "offset": 16,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "IPR0": {
+                    "description": "Interrupt Priority Register",
+                    "offset": 768,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "TIMER_IRQ_0": {
+                          "offset": 6,
+                          "size": 2
+                        },
+                        "TIMER_IRQ_1": {
+                          "offset": 14,
+                          "size": 2
+                        },
+                        "TIMER_IRQ_2": {
+                          "offset": 22,
+                          "size": 2
+                        },
+                        "TIMER_IRQ_3": {
+                          "offset": 30,
+                          "size": 2
+                        }
+                      }
+                    }
+                  },
+                  "IPR1": {
+                    "description": "Interrupt Priority Register",
+                    "offset": 772,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "XIP_IRQ": {
+                          "offset": 22,
+                          "size": 2
+                        },
+                        "PWM_IRQ_WRAP": {
+                          "offset": 6,
+                          "size": 2
+                        },
+                        "USBCTRL_IRQ": {
+                          "offset": 14,
+                          "size": 2
+                        },
+                        "PIO0_IRQ_0": {
+                          "offset": 30,
+                          "size": 2
+                        }
+                      }
+                    }
+                  },
+                  "IPR2": {
+                    "description": "Interrupt Priority Register",
+                    "offset": 776,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "DMA_IRQ_0": {
+                          "offset": 30,
+                          "size": 2
+                        },
+                        "PIO0_IRQ_1": {
+                          "offset": 6,
+                          "size": 2
+                        },
+                        "PIO1_IRQ_0": {
+                          "offset": 14,
+                          "size": 2
+                        },
+                        "PIO1_IRQ_1": {
+                          "offset": 22,
+                          "size": 2
+                        }
+                      }
+                    }
+                  },
+                  "IPR3": {
+                    "description": "Interrupt Priority Register",
+                    "offset": 780,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "IO_IRQ_BANK0": {
+                          "offset": 14,
+                          "size": 2
+                        },
+                        "IO_IRQ_QSPI": {
+                          "offset": 22,
+                          "size": 2
+                        },
+                        "DMA_IRQ_1": {
+                          "offset": 6,
+                          "size": 2
+                        },
+                        "SIO_IRQ_PROC0": {
+                          "offset": 30,
+                          "size": 2
+                        }
+                      }
+                    }
+                  },
+                  "IPR4": {
+                    "description": "Interrupt Priority Register",
+                    "offset": 784,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "CLOCKS_IRQ": {
+                          "offset": 14,
+                          "size": 2
+                        },
+                        "SPI0_IRQ": {
+                          "offset": 22,
+                          "size": 2
+                        },
+                        "SPI1_IRQ": {
+                          "offset": 30,
+                          "size": 2
+                        },
+                        "SIO_IRQ_PROC1": {
+                          "offset": 6,
+                          "size": 2
+                        }
+                      }
+                    }
+                  },
+                  "IPR5": {
+                    "description": "Interrupt Priority Register",
+                    "offset": 788,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "UART0_IRQ": {
+                          "offset": 6,
+                          "size": 2
+                        },
+                        "UART1_IRQ": {
+                          "offset": 14,
+                          "size": 2
+                        },
+                        "I2C0_IRQ": {
+                          "offset": 30,
+                          "size": 2
+                        },
+                        "ADC_IRQ_FIFO": {
+                          "offset": 22,
+                          "size": 2
+                        }
+                      }
+                    }
+                  },
+                  "IPR6": {
+                    "description": "Interrupt Priority Register",
+                    "offset": 792,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "I2C1_IRQ": {
+                          "offset": 6,
+                          "size": 2
+                        },
+                        "RTC_IRQ": {
+                          "offset": 14,
+                          "size": 2
+                        }
+                      }
+                    }
+                  },
+                  "IPR7": {
+                    "description": "Interrupt Priority Register",
+                    "offset": 796,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MPU": {
+              "description": "Memory Protection Unit",
+              "children": {
+                "registers": {
+                  "TYPE": {
+                    "description": "MPU Type Register",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only",
+                    "children": {
+                      "fields": {
+                        "SEPARATE": {
+                          "offset": 0,
+                          "size": 1
+                        },
+                        "DREGION": {
+                          "offset": 8,
+                          "size": 8
+                        },
+                        "IREGION": {
+                          "offset": 16,
+                          "size": 8
+                        }
+                      }
+                    }
+                  },
+                  "CTRL": {
+                    "description": "MPU Control Register",
+                    "offset": 4,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "ENABLE": {
+                          "offset": 0,
+                          "size": 1
+                        },
+                        "HFNMIENA": {
+                          "offset": 1,
+                          "size": 1
+                        },
+                        "PRIVDEFENA": {
+                          "offset": 2,
+                          "size": 1
+                        }
+                      }
+                    }
+                  },
+                  "RNR": {
+                    "description": "MPU Region RNRber Register",
+                    "offset": 8,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "REGION": {
+                          "offset": 0,
+                          "size": 8
+                        }
+                      }
+                    }
+                  },
+                  "RBAR": {
+                    "description": "MPU Region Base Address Register",
+                    "offset": 12,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "REGION": {
+                          "offset": 0,
+                          "size": 4
+                        },
+                        "VALID": {
+                          "offset": 4,
+                          "size": 1
+                        },
+                        "ADDR": {
+                          "offset": 8,
+                          "size": 24
+                        }
+                      }
+                    }
+                  },
+                  "RASR": {
+                    "description": "MPU Region Attribute and Size Register",
+                    "offset": 16,
+                    "size": 32,
+                    "children": {
+                      "fields": {
+                        "ENABLE": {
+                          "offset": 0,
+                          "size": 1
+                        },
+                        "SIZE": {
+                          "offset": 1,
+                          "size": 5
+                        },
+                        "SRD": {
+                          "offset": 8,
+                          "size": 8
+                        },
+                        "B": {
+                          "offset": 16,
+                          "size": 1
+                        },
+                        "C": {
+                          "offset": 17,
+                          "size": 1
+                        },
+                        "S": {
+                          "offset": 18,
+                          "size": 1
+                        },
+                        "TEX": {
+                          "offset": 19,
+                          "size": 3
+                        },
+                        "AP": {
+                          "offset": 24,
+                          "size": 3
+                        },
+                        "XN": {
+                          "offset": 28,
+                          "size": 1
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "XIP_CTRL": {
+        "description": "QSPI flash execute-in-place block",
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "Cache control",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 3,
+              "children": {
+                "fields": {
+                  "POWER_DOWN": {
+                    "description": "When 1, the cache memories are powered down. They retain state,\\n\n                but can not be accessed. This reduces static power dissipation.\\n\n                Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\\n\n                be enabled when powered down.\\n\n                Cache-as-SRAM accesses will produce a bus error response when\\n\n                the cache is powered down.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_BADWRITE": {
+                    "description": "When 1, writes to any alias other than 0x0 (caching, allocating)\\n\n                will produce a bus fault. When 0, these writes are silently ignored.\\n\n                In either case, writes to the 0x0 alias will deallocate on tag match,\\n\n                as usual.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "When 1, enable the cache. When the cache is disabled, all XIP accesses\\n\n                will go straight to the flash, without querying the cache. When enabled,\\n\n                cacheable XIP accesses will query the cache, and the flash will\\n\n                not be accessed if the tag matches and the valid bit is set.\\n\\n\n                If the cache is enabled, cache-as-SRAM accesses have no effect on the\\n\n                cache data RAM, and will produce a bus error response.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FLUSH": {
+              "description": "Cache Flush control",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FLUSH": {
+                    "description": "Write 1 to flush the cache. This clears the tag memory, but\\n\n                the data memory retains its contents. (This means cache-as-SRAM\\n\n                contents is not affected by flush or reset.)\\n\n                Reading will hold the bus (stall the processor) until the flush\\n\n                completes. Alternatively STAT can be polled until completion.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "STAT": {
+              "description": "Cache Status",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 2,
+              "children": {
+                "fields": {
+                  "FIFO_FULL": {
+                    "description": "When 1, indicates the XIP streaming FIFO is completely full.\\n\n                The streaming FIFO is 2 entries deep, so the full and empty\\n\n                flag allow its level to be ascertained.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FIFO_EMPTY": {
+                    "description": "When 1, indicates the XIP streaming FIFO is completely empty.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLUSH_READY": {
+                    "description": "Reads as 0 while a cache flush is in progress, and 1 otherwise.\\n\n                The cache is flushed whenever the XIP block is reset, and also\\n\n                when requested via the FLUSH register.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CTR_HIT": {
+              "description": "Cache Hit counter\\n\n            A 32 bit saturating counter that increments upon each cache hit,\\n\n            i.e. when an XIP access is serviced directly from cached data.\\n\n            Write any value to clear.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CTR_ACC": {
+              "description": "Cache Access counter\\n\n            A 32 bit saturating counter that increments upon each XIP access,\\n\n            whether the cache is hit or not. This includes noncacheable accesses.\\n\n            Write any value to clear.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0
+            },
+            "STREAM_ADDR": {
+              "description": "FIFO stream address",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "STREAM_ADDR": {
+                    "description": "The address of the next word to be streamed from flash to the streaming FIFO.\\n\n                Increments automatically after each flash access.\\n\n                Write the initial access address here before starting a streaming read.",
+                    "offset": 2,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "STREAM_CTR": {
+              "description": "FIFO stream control",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "STREAM_CTR": {
+                    "description": "Write a nonzero value to start a streaming read. This will then\\n\n                progress in the background, using flash idle cycles to transfer\\n\n                a linear data block from flash to the streaming FIFO.\\n\n                Decrements automatically (1 at a time) as the stream\\n\n                progresses, and halts on reaching 0.\\n\n                Write 0 to halt an in-progress stream, and discard any in-flight\\n\n                read, so that a new stream can immediately be started (after\\n\n                draining the FIFO and reinitialising STREAM_ADDR)",
+                    "offset": 0,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "STREAM_FIFO": {
+              "description": "FIFO stream data\\n\n            Streamed data is buffered here, for retrieval by the system DMA.\\n\n            This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\\n\n            the DMA to bus stalls caused by other XIP traffic.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            }
+          }
+        }
+      },
+      "XIP_SSI": {
+        "description": "DW_apb_ssi has the following features:\\n\n        * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\\n\n        * APB3 and APB4 protocol support.\\n\n        * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\\n\n        * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\\n\n        * Programmable Dual/Quad/Octal SPI support in Master Mode.\\n\n        * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\\n\n        * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\\n\n        * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\\n\n        * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\\n\n        * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\\n\n        * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\\n\n        * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\\n\n        * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\\n\n        * Programmable features:\\n\n        - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\\n\n        - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\\n\n        - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\\n\n        * Configured features:\\n\n        - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\\n\n        - 1 slave select output.\\n\n        - Hardware slave-select – Dedicated hardware slave-select line.\\n\n        - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\\n\n        - Interrupt polarity – active high interrupt lines.\\n\n        - Serial clock polarity – low serial-clock polarity directly after reset.\\n\n        - Serial clock phase – capture on first edge of serial-clock directly after reset.",
+        "children": {
+          "registers": {
+            "CTRLR0": {
+              "description": "Control register 0",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SSTE": {
+                    "description": "Slave select toggle enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "SPI_FRF": {
+                    "description": "SPI frame format",
+                    "offset": 21,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "STD": {
+                            "description": "Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex",
+                            "value": 0
+                          },
+                          "DUAL": {
+                            "description": "Dual-SPI frame format; two bits per SCK, half-duplex",
+                            "value": 1
+                          },
+                          "QUAD": {
+                            "description": "Quad-SPI frame format; four bits per SCK, half-duplex",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DFS_32": {
+                    "description": "Data frame size in 32b transfer mode\\n\n                Value of n -> n+1 clocks per frame.",
+                    "offset": 16,
+                    "size": 5
+                  },
+                  "CFS": {
+                    "description": "Control frame size\\n\n                Value of n -> n+1 clocks per frame.",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "SRL": {
+                    "description": "Shift register loop (test mode)",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SLV_OE": {
+                    "description": "Slave output enable",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TMOD": {
+                    "description": "Transfer mode",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "TX_AND_RX": {
+                            "description": "Both transmit and receive",
+                            "value": 0
+                          },
+                          "TX_ONLY": {
+                            "description": "Transmit only (not for FRF == 0, standard SPI mode)",
+                            "value": 1
+                          },
+                          "RX_ONLY": {
+                            "description": "Receive only (not for FRF == 0, standard SPI mode)",
+                            "value": 2
+                          },
+                          "EEPROM_READ": {
+                            "description": "EEPROM read mode (TX then RX; RX starts after control data TX'd)",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SCPOL": {
+                    "description": "Serial clock polarity",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SCPH": {
+                    "description": "Serial clock phase",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FRF": {
+                    "description": "Frame format",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DFS": {
+                    "description": "Data frame size",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CTRLR1": {
+              "description": "Master Control register 1",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "NDF": {
+                    "description": "Number of data frames",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SSIENR": {
+              "description": "SSI Enable",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SSI_EN": {
+                    "description": "SSI enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MWCR": {
+              "description": "Microwire Control",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "MHS": {
+                    "description": "Microwire handshaking",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MDD": {
+                    "description": "Microwire control",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MWMOD": {
+                    "description": "Microwire transfer mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SER": {
+              "description": "Slave enable",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SER": {
+                    "description": "For each bit:\\n\n                0 -> slave not selected\\n\n                1 -> slave selected",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BAUDR": {
+              "description": "Baud rate",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SCKDV": {
+                    "description": "SSI clock divider",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TXFTLR": {
+              "description": "TX FIFO threshold level",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TFT": {
+                    "description": "Transmit FIFO threshold",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RXFTLR": {
+              "description": "RX FIFO threshold level",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RFT": {
+                    "description": "Receive FIFO threshold",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXFLR": {
+              "description": "TX FIFO level",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TFTFL": {
+                    "description": "Transmit FIFO level",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RXFLR": {
+              "description": "RX FIFO level",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RXTFL": {
+                    "description": "Receive FIFO level",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "Status register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DCOL": {
+                    "description": "Data collision error",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXE": {
+                    "description": "Transmission error",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RFF": {
+                    "description": "Receive FIFO full",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RFNE": {
+                    "description": "Receive FIFO not empty",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TFE": {
+                    "description": "Transmit FIFO empty",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TFNF": {
+                    "description": "Transmit FIFO not full",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUSY": {
+                    "description": "SSI busy flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IMR": {
+              "description": "Interrupt mask",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "MSTIM": {
+                    "description": "Multi-master contention interrupt mask",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RXFIM": {
+                    "description": "Receive FIFO full interrupt mask",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RXOIM": {
+                    "description": "Receive FIFO overflow interrupt mask",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXUIM": {
+                    "description": "Receive FIFO underflow interrupt mask",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXOIM": {
+                    "description": "Transmit FIFO overflow interrupt mask",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TXEIM": {
+                    "description": "Transmit FIFO empty interrupt mask",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ISR": {
+              "description": "Interrupt status",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "MSTIS": {
+                    "description": "Multi-master contention interrupt status",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIS": {
+                    "description": "Receive FIFO full interrupt status",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXOIS": {
+                    "description": "Receive FIFO overflow interrupt status",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXUIS": {
+                    "description": "Receive FIFO underflow interrupt status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXOIS": {
+                    "description": "Transmit FIFO overflow interrupt status",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXEIS": {
+                    "description": "Transmit FIFO empty interrupt status",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RISR": {
+              "description": "Raw interrupt status",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "MSTIR": {
+                    "description": "Multi-master contention raw interrupt status",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIR": {
+                    "description": "Receive FIFO full raw interrupt status",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXOIR": {
+                    "description": "Receive FIFO overflow raw interrupt status",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXUIR": {
+                    "description": "Receive FIFO underflow raw interrupt status",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXOIR": {
+                    "description": "Transmit FIFO overflow raw interrupt status",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXEIR": {
+                    "description": "Transmit FIFO empty raw interrupt status",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TXOICR": {
+              "description": "TX FIFO overflow interrupt clear",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TXOICR": {
+                    "description": "Clear-on-read transmit FIFO overflow interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RXOICR": {
+              "description": "RX FIFO overflow interrupt clear",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RXOICR": {
+                    "description": "Clear-on-read receive FIFO overflow interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RXUICR": {
+              "description": "RX FIFO underflow interrupt clear",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RXUICR": {
+                    "description": "Clear-on-read receive FIFO underflow interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MSTICR": {
+              "description": "Multi-master interrupt clear",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "MSTICR": {
+                    "description": "Clear-on-read multi-master contention interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ICR": {
+              "description": "Interrupt clear",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ICR": {
+                    "description": "Clear-on-read all active interrupts",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DMACR": {
+              "description": "DMA control",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TDMAE": {
+                    "description": "Transmit DMA enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RDMAE": {
+                    "description": "Receive DMA enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMATDLR": {
+              "description": "DMA TX data level",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DMATDL": {
+                    "description": "Transmit data watermark level",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DMARDLR": {
+              "description": "DMA RX data level",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DMARDL": {
+                    "description": "Receive data watermark level (DMARDLR+1)",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IDR": {
+              "description": "Identification register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 1364414537,
+              "children": {
+                "fields": {
+                  "IDCODE": {
+                    "description": "Peripheral dentification code",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SSI_VERSION_ID": {
+              "description": "Version ID",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 875573546,
+              "children": {
+                "fields": {
+                  "SSI_COMP_VERSION": {
+                    "description": "SNPS component version (format X.YY)",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DR0": {
+              "description": "Data Register 0 (of 36)",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DR": {
+                    "description": "First data register of 36",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RX_SAMPLE_DLY": {
+              "description": "RX sample delay",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RSD": {
+                    "description": "RXD sample delay (in SCLK cycles)",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SPI_CTRLR0": {
+              "description": "SPI control",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 50331648,
+              "children": {
+                "fields": {
+                  "XIP_CMD": {
+                    "description": "SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)",
+                    "offset": 24,
+                    "size": 8
+                  },
+                  "SPI_RXDS_EN": {
+                    "description": "Read data strobe enable",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "INST_DDR_EN": {
+                    "description": "Instruction DDR transfer enable",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SPI_DDR_EN": {
+                    "description": "SPI DDR transfer enable",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "WAIT_CYCLES": {
+                    "description": "Wait cycles between control frame transmit and data reception (in SCLK cycles)",
+                    "offset": 11,
+                    "size": 5
+                  },
+                  "INST_L": {
+                    "description": "Instruction length (0/4/8/16b)",
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NONE": {
+                            "description": "No instruction",
+                            "value": 0
+                          },
+                          "4B": {
+                            "description": "4-bit instruction",
+                            "value": 1
+                          },
+                          "8B": {
+                            "description": "8-bit instruction",
+                            "value": 2
+                          },
+                          "16B": {
+                            "description": "16-bit instruction",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ADDR_L": {
+                    "description": "Address length (0b-60b in 4b increments)",
+                    "offset": 2,
+                    "size": 4
+                  },
+                  "TRANS_TYPE": {
+                    "description": "Address and instruction transfer format",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "1C1A": {
+                            "description": "Command and address both in standard SPI frame format",
+                            "value": 0
+                          },
+                          "1C2A": {
+                            "description": "Command in standard SPI format, address in format specified by FRF",
+                            "value": 1
+                          },
+                          "2C2A": {
+                            "description": "Command and address both in format specified by FRF (e.g. Dual-SPI)",
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "TXD_DRIVE_EDGE": {
+              "description": "TX drive edge",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TDE": {
+                    "description": "TXD drive edge",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SYSINFO": {
+        "children": {
+          "registers": {
+            "CHIP_ID": {
+              "description": "JEDEC JEP-106 compliant chip identifier.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "REVISION": {
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "PART": {
+                    "offset": 12,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "MANUFACTURER": {
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PLATFORM": {
+              "description": "Platform register. Allows software to know what environment it is running in.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ASIC": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FPGA": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GITREF_RP2040": {
+              "description": "Git hash of the chip source. Used to identify chip version.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            }
+          }
+        }
+      },
+      "SYSCFG": {
+        "description": "Register block for various chip control signals",
+        "children": {
+          "registers": {
+            "PROC0_NMI_MASK": {
+              "description": "Processor core 0 NMI source mask\\n\n            Set a bit high to enable NMI from that IRQ",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0
+            },
+            "PROC1_NMI_MASK": {
+              "description": "Processor core 1 NMI source mask\\n\n            Set a bit high to enable NMI from that IRQ",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0
+            },
+            "PROC_CONFIG": {
+              "description": "Configuration for processors",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 268435456,
+              "children": {
+                "fields": {
+                  "PROC1_DAP_INSTID": {
+                    "description": "Configure proc1 DAP instance ID.\\n\n                Recommend that this is NOT changed until you require debug access in multi-chip environment\\n\n                WARNING: do not set to 15 as this is reserved for RescueDP",
+                    "offset": 28,
+                    "size": 4
+                  },
+                  "PROC0_DAP_INSTID": {
+                    "description": "Configure proc0 DAP instance ID.\\n\n                Recommend that this is NOT changed until you require debug access in multi-chip environment\\n\n                WARNING: do not set to 15 as this is reserved for RescueDP",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "PROC1_HALTED": {
+                    "description": "Indication that proc1 has halted",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PROC0_HALTED": {
+                    "description": "Indication that proc0 has halted",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PROC_IN_SYNC_BYPASS": {
+              "description": "For each bit, if 1, bypass the input synchronizer between that GPIO\\n\n            and the GPIO input register in the SIO. The input synchronizers should\\n\n            generally be unbypassed, to avoid injecting metastabilities into processors.\\n\n            If you're feeling brave, you can bypass to save two cycles of input\\n\n            latency. This register applies to GPIO 0...29.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PROC_IN_SYNC_BYPASS": {
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "PROC_IN_SYNC_BYPASS_HI": {
+              "description": "For each bit, if 1, bypass the input synchronizer between that GPIO\\n\n            and the GPIO input register in the SIO. The input synchronizers should\\n\n            generally be unbypassed, to avoid injecting metastabilities into processors.\\n\n            If you're feeling brave, you can bypass to save two cycles of input\\n\n            latency. This register applies to GPIO 30...35 (the QSPI IOs).",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PROC_IN_SYNC_BYPASS_HI": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "DBGFORCE": {
+              "description": "Directly control the SWD debug port of either processor",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 102,
+              "children": {
+                "fields": {
+                  "PROC1_ATTACH": {
+                    "description": "Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PROC1_SWCLK": {
+                    "description": "Directly drive processor 1 SWCLK, if PROC1_ATTACH is set",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "PROC1_SWDI": {
+                    "description": "Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PROC1_SWDO": {
+                    "description": "Observe the value of processor 1 SWDIO output.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PROC0_ATTACH": {
+                    "description": "Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PROC0_SWCLK": {
+                    "description": "Directly drive processor 0 SWCLK, if PROC0_ATTACH is set",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PROC0_SWDI": {
+                    "description": "Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PROC0_SWDO": {
+                    "description": "Observe the value of processor 0 SWDIO output.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MEMPOWERDOWN": {
+              "description": "Control power downs to memories. Set high to power down memories.\\n\n            Use with extreme caution",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ROM": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "USB": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SRAM5": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SRAM4": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SRAM3": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SRAM2": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SRAM1": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SRAM0": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "CLOCKS": {
+        "children": {
+          "registers": {
+            "CLK_GPOUT0_CTRL": {
+              "description": "Clock control, can be changed on-the-fly (except for auxsrc)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "NUDGE": {
+                    "description": "An edge on this signal shifts the phase of the output by 1 cycle of the input clock\\n\n                This can be done at any time",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PHASE": {
+                    "description": "This delays the enable signal by up to 3 cycles of the input clock\\n\n                This must be set before the clock is enabled to have any effect",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DC50": {
+                    "description": "Enables duty cycle correction for odd divisors",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENABLE": {
+                    "description": "Starts and stops the clock generator cleanly",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "KILL": {
+                    "description": "Asynchronously kills the clock generator",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AUXSRC": {
+                    "description": "Selects the auxiliary clock source, will glitch when switching",
+                    "offset": 5,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "clksrc_pll_sys": {
+                            "value": 0
+                          },
+                          "clksrc_gpin0": {
+                            "value": 1
+                          },
+                          "clksrc_gpin1": {
+                            "value": 2
+                          },
+                          "clksrc_pll_usb": {
+                            "value": 3
+                          },
+                          "rosc_clksrc": {
+                            "value": 4
+                          },
+                          "xosc_clksrc": {
+                            "value": 5
+                          },
+                          "clk_sys": {
+                            "value": 6
+                          },
+                          "clk_usb": {
+                            "value": 7
+                          },
+                          "clk_adc": {
+                            "value": 8
+                          },
+                          "clk_rtc": {
+                            "value": 9
+                          },
+                          "clk_ref": {
+                            "value": 10
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CLK_GPOUT0_DIV": {
+              "description": "Clock divisor, can be changed on-the-fly",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 256,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Integer component of the divisor, 0 -> divide by 2^16",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "FRAC": {
+                    "description": "Fractional component of the divisor",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLK_GPOUT0_SELECTED": {
+              "description": "Indicates which SRC is currently selected by the glitchless mux (one-hot).\\n\n            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 1,
+              "access": "read-only"
+            },
+            "CLK_GPOUT1_CTRL": {
+              "description": "Clock control, can be changed on-the-fly (except for auxsrc)",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "NUDGE": {
+                    "description": "An edge on this signal shifts the phase of the output by 1 cycle of the input clock\\n\n                This can be done at any time",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PHASE": {
+                    "description": "This delays the enable signal by up to 3 cycles of the input clock\\n\n                This must be set before the clock is enabled to have any effect",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DC50": {
+                    "description": "Enables duty cycle correction for odd divisors",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENABLE": {
+                    "description": "Starts and stops the clock generator cleanly",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "KILL": {
+                    "description": "Asynchronously kills the clock generator",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AUXSRC": {
+                    "description": "Selects the auxiliary clock source, will glitch when switching",
+                    "offset": 5,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "clksrc_pll_sys": {
+                            "value": 0
+                          },
+                          "clksrc_gpin0": {
+                            "value": 1
+                          },
+                          "clksrc_gpin1": {
+                            "value": 2
+                          },
+                          "clksrc_pll_usb": {
+                            "value": 3
+                          },
+                          "rosc_clksrc": {
+                            "value": 4
+                          },
+                          "xosc_clksrc": {
+                            "value": 5
+                          },
+                          "clk_sys": {
+                            "value": 6
+                          },
+                          "clk_usb": {
+                            "value": 7
+                          },
+                          "clk_adc": {
+                            "value": 8
+                          },
+                          "clk_rtc": {
+                            "value": 9
+                          },
+                          "clk_ref": {
+                            "value": 10
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CLK_GPOUT1_DIV": {
+              "description": "Clock divisor, can be changed on-the-fly",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 256,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Integer component of the divisor, 0 -> divide by 2^16",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "FRAC": {
+                    "description": "Fractional component of the divisor",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLK_GPOUT1_SELECTED": {
+              "description": "Indicates which SRC is currently selected by the glitchless mux (one-hot).\\n\n            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 1,
+              "access": "read-only"
+            },
+            "CLK_GPOUT2_CTRL": {
+              "description": "Clock control, can be changed on-the-fly (except for auxsrc)",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "NUDGE": {
+                    "description": "An edge on this signal shifts the phase of the output by 1 cycle of the input clock\\n\n                This can be done at any time",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PHASE": {
+                    "description": "This delays the enable signal by up to 3 cycles of the input clock\\n\n                This must be set before the clock is enabled to have any effect",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DC50": {
+                    "description": "Enables duty cycle correction for odd divisors",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENABLE": {
+                    "description": "Starts and stops the clock generator cleanly",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "KILL": {
+                    "description": "Asynchronously kills the clock generator",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AUXSRC": {
+                    "description": "Selects the auxiliary clock source, will glitch when switching",
+                    "offset": 5,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "clksrc_pll_sys": {
+                            "value": 0
+                          },
+                          "clksrc_gpin0": {
+                            "value": 1
+                          },
+                          "clksrc_gpin1": {
+                            "value": 2
+                          },
+                          "clksrc_pll_usb": {
+                            "value": 3
+                          },
+                          "rosc_clksrc_ph": {
+                            "value": 4
+                          },
+                          "xosc_clksrc": {
+                            "value": 5
+                          },
+                          "clk_sys": {
+                            "value": 6
+                          },
+                          "clk_usb": {
+                            "value": 7
+                          },
+                          "clk_adc": {
+                            "value": 8
+                          },
+                          "clk_rtc": {
+                            "value": 9
+                          },
+                          "clk_ref": {
+                            "value": 10
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CLK_GPOUT2_DIV": {
+              "description": "Clock divisor, can be changed on-the-fly",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 256,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Integer component of the divisor, 0 -> divide by 2^16",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "FRAC": {
+                    "description": "Fractional component of the divisor",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLK_GPOUT2_SELECTED": {
+              "description": "Indicates which SRC is currently selected by the glitchless mux (one-hot).\\n\n            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 1,
+              "access": "read-only"
+            },
+            "CLK_GPOUT3_CTRL": {
+              "description": "Clock control, can be changed on-the-fly (except for auxsrc)",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "NUDGE": {
+                    "description": "An edge on this signal shifts the phase of the output by 1 cycle of the input clock\\n\n                This can be done at any time",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PHASE": {
+                    "description": "This delays the enable signal by up to 3 cycles of the input clock\\n\n                This must be set before the clock is enabled to have any effect",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DC50": {
+                    "description": "Enables duty cycle correction for odd divisors",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENABLE": {
+                    "description": "Starts and stops the clock generator cleanly",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "KILL": {
+                    "description": "Asynchronously kills the clock generator",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AUXSRC": {
+                    "description": "Selects the auxiliary clock source, will glitch when switching",
+                    "offset": 5,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "clksrc_pll_sys": {
+                            "value": 0
+                          },
+                          "clksrc_gpin0": {
+                            "value": 1
+                          },
+                          "clksrc_gpin1": {
+                            "value": 2
+                          },
+                          "clksrc_pll_usb": {
+                            "value": 3
+                          },
+                          "rosc_clksrc_ph": {
+                            "value": 4
+                          },
+                          "xosc_clksrc": {
+                            "value": 5
+                          },
+                          "clk_sys": {
+                            "value": 6
+                          },
+                          "clk_usb": {
+                            "value": 7
+                          },
+                          "clk_adc": {
+                            "value": 8
+                          },
+                          "clk_rtc": {
+                            "value": 9
+                          },
+                          "clk_ref": {
+                            "value": 10
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CLK_GPOUT3_DIV": {
+              "description": "Clock divisor, can be changed on-the-fly",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 256,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Integer component of the divisor, 0 -> divide by 2^16",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "FRAC": {
+                    "description": "Fractional component of the divisor",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLK_GPOUT3_SELECTED": {
+              "description": "Indicates which SRC is currently selected by the glitchless mux (one-hot).\\n\n            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 1,
+              "access": "read-only"
+            },
+            "CLK_REF_CTRL": {
+              "description": "Clock control, can be changed on-the-fly (except for auxsrc)",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AUXSRC": {
+                    "description": "Selects the auxiliary clock source, will glitch when switching",
+                    "offset": 5,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "clksrc_pll_usb": {
+                            "value": 0
+                          },
+                          "clksrc_gpin0": {
+                            "value": 1
+                          },
+                          "clksrc_gpin1": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SRC": {
+                    "description": "Selects the clock source glitchlessly, can be changed on-the-fly",
+                    "offset": 0,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "rosc_clksrc_ph": {
+                            "value": 0
+                          },
+                          "clksrc_clk_ref_aux": {
+                            "value": 1
+                          },
+                          "xosc_clksrc": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CLK_REF_DIV": {
+              "description": "Clock divisor, can be changed on-the-fly",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 256,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Integer component of the divisor, 0 -> divide by 2^16",
+                    "offset": 8,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLK_REF_SELECTED": {
+              "description": "Indicates which SRC is currently selected by the glitchless mux (one-hot).\\n\n            The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 1,
+              "access": "read-only"
+            },
+            "CLK_SYS_CTRL": {
+              "description": "Clock control, can be changed on-the-fly (except for auxsrc)",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AUXSRC": {
+                    "description": "Selects the auxiliary clock source, will glitch when switching",
+                    "offset": 5,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "clksrc_pll_sys": {
+                            "value": 0
+                          },
+                          "clksrc_pll_usb": {
+                            "value": 1
+                          },
+                          "rosc_clksrc": {
+                            "value": 2
+                          },
+                          "xosc_clksrc": {
+                            "value": 3
+                          },
+                          "clksrc_gpin0": {
+                            "value": 4
+                          },
+                          "clksrc_gpin1": {
+                            "value": 5
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SRC": {
+                    "description": "Selects the clock source glitchlessly, can be changed on-the-fly",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "clk_ref": {
+                            "value": 0
+                          },
+                          "clksrc_clk_sys_aux": {
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CLK_SYS_DIV": {
+              "description": "Clock divisor, can be changed on-the-fly",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 256,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Integer component of the divisor, 0 -> divide by 2^16",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "FRAC": {
+                    "description": "Fractional component of the divisor",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLK_SYS_SELECTED": {
+              "description": "Indicates which SRC is currently selected by the glitchless mux (one-hot).\\n\n            The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 1,
+              "access": "read-only"
+            },
+            "CLK_PERI_CTRL": {
+              "description": "Clock control, can be changed on-the-fly (except for auxsrc)",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Starts and stops the clock generator cleanly",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "KILL": {
+                    "description": "Asynchronously kills the clock generator",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AUXSRC": {
+                    "description": "Selects the auxiliary clock source, will glitch when switching",
+                    "offset": 5,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "clk_sys": {
+                            "value": 0
+                          },
+                          "clksrc_pll_sys": {
+                            "value": 1
+                          },
+                          "clksrc_pll_usb": {
+                            "value": 2
+                          },
+                          "rosc_clksrc_ph": {
+                            "value": 3
+                          },
+                          "xosc_clksrc": {
+                            "value": 4
+                          },
+                          "clksrc_gpin0": {
+                            "value": 5
+                          },
+                          "clksrc_gpin1": {
+                            "value": 6
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CLK_PERI_SELECTED": {
+              "description": "Indicates which SRC is currently selected by the glitchless mux (one-hot).\\n\n            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 1,
+              "access": "read-only"
+            },
+            "CLK_USB_CTRL": {
+              "description": "Clock control, can be changed on-the-fly (except for auxsrc)",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "NUDGE": {
+                    "description": "An edge on this signal shifts the phase of the output by 1 cycle of the input clock\\n\n                This can be done at any time",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PHASE": {
+                    "description": "This delays the enable signal by up to 3 cycles of the input clock\\n\n                This must be set before the clock is enabled to have any effect",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "ENABLE": {
+                    "description": "Starts and stops the clock generator cleanly",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "KILL": {
+                    "description": "Asynchronously kills the clock generator",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AUXSRC": {
+                    "description": "Selects the auxiliary clock source, will glitch when switching",
+                    "offset": 5,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "clksrc_pll_usb": {
+                            "value": 0
+                          },
+                          "clksrc_pll_sys": {
+                            "value": 1
+                          },
+                          "rosc_clksrc_ph": {
+                            "value": 2
+                          },
+                          "xosc_clksrc": {
+                            "value": 3
+                          },
+                          "clksrc_gpin0": {
+                            "value": 4
+                          },
+                          "clksrc_gpin1": {
+                            "value": 5
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CLK_USB_DIV": {
+              "description": "Clock divisor, can be changed on-the-fly",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 256,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Integer component of the divisor, 0 -> divide by 2^16",
+                    "offset": 8,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLK_USB_SELECTED": {
+              "description": "Indicates which SRC is currently selected by the glitchless mux (one-hot).\\n\n            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 1,
+              "access": "read-only"
+            },
+            "CLK_ADC_CTRL": {
+              "description": "Clock control, can be changed on-the-fly (except for auxsrc)",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "NUDGE": {
+                    "description": "An edge on this signal shifts the phase of the output by 1 cycle of the input clock\\n\n                This can be done at any time",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PHASE": {
+                    "description": "This delays the enable signal by up to 3 cycles of the input clock\\n\n                This must be set before the clock is enabled to have any effect",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "ENABLE": {
+                    "description": "Starts and stops the clock generator cleanly",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "KILL": {
+                    "description": "Asynchronously kills the clock generator",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AUXSRC": {
+                    "description": "Selects the auxiliary clock source, will glitch when switching",
+                    "offset": 5,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "clksrc_pll_usb": {
+                            "value": 0
+                          },
+                          "clksrc_pll_sys": {
+                            "value": 1
+                          },
+                          "rosc_clksrc_ph": {
+                            "value": 2
+                          },
+                          "xosc_clksrc": {
+                            "value": 3
+                          },
+                          "clksrc_gpin0": {
+                            "value": 4
+                          },
+                          "clksrc_gpin1": {
+                            "value": 5
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CLK_ADC_DIV": {
+              "description": "Clock divisor, can be changed on-the-fly",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 256,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Integer component of the divisor, 0 -> divide by 2^16",
+                    "offset": 8,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLK_ADC_SELECTED": {
+              "description": "Indicates which SRC is currently selected by the glitchless mux (one-hot).\\n\n            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 1,
+              "access": "read-only"
+            },
+            "CLK_RTC_CTRL": {
+              "description": "Clock control, can be changed on-the-fly (except for auxsrc)",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "NUDGE": {
+                    "description": "An edge on this signal shifts the phase of the output by 1 cycle of the input clock\\n\n                This can be done at any time",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "PHASE": {
+                    "description": "This delays the enable signal by up to 3 cycles of the input clock\\n\n                This must be set before the clock is enabled to have any effect",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "ENABLE": {
+                    "description": "Starts and stops the clock generator cleanly",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "KILL": {
+                    "description": "Asynchronously kills the clock generator",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "AUXSRC": {
+                    "description": "Selects the auxiliary clock source, will glitch when switching",
+                    "offset": 5,
+                    "size": 3,
+                    "enum": {
+                      "size": 3,
+                      "children": {
+                        "enum_fields": {
+                          "clksrc_pll_usb": {
+                            "value": 0
+                          },
+                          "clksrc_pll_sys": {
+                            "value": 1
+                          },
+                          "rosc_clksrc_ph": {
+                            "value": 2
+                          },
+                          "xosc_clksrc": {
+                            "value": 3
+                          },
+                          "clksrc_gpin0": {
+                            "value": 4
+                          },
+                          "clksrc_gpin1": {
+                            "value": 5
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "CLK_RTC_DIV": {
+              "description": "Clock divisor, can be changed on-the-fly",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 256,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Integer component of the divisor, 0 -> divide by 2^16",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "FRAC": {
+                    "description": "Fractional component of the divisor",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLK_RTC_SELECTED": {
+              "description": "Indicates which SRC is currently selected by the glitchless mux (one-hot).\\n\n            This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 1,
+              "access": "read-only"
+            },
+            "CLK_SYS_RESUS_CTRL": {
+              "offset": 120,
+              "size": 32,
+              "reset_value": 255,
+              "children": {
+                "fields": {
+                  "CLEAR": {
+                    "description": "For clearing the resus after the fault that triggered it has been corrected",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "FRCE": {
+                    "description": "Force a resus, for test purposes only",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ENABLE": {
+                    "description": "Enable resus",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TIMEOUT": {
+                    "description": "This is expressed as a number of clk_ref cycles\\n\n                and must be >= 2x clk_ref_freq/min_clk_tst_freq",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CLK_SYS_RESUS_STATUS": {
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RESUSSED": {
+                    "description": "Clock has been resuscitated, correct the error then send ctrl_clear=1",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FC0_REF_KHZ": {
+              "description": "Reference clock frequency in kHz",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FC0_REF_KHZ": {
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "FC0_MIN_KHZ": {
+              "description": "Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FC0_MIN_KHZ": {
+                    "offset": 0,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "FC0_MAX_KHZ": {
+              "description": "Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 33554431,
+              "children": {
+                "fields": {
+                  "FC0_MAX_KHZ": {
+                    "offset": 0,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "FC0_DELAY": {
+              "description": "Delays the start of frequency counting to allow the mux to settle\\n\n            Delay is measured in multiples of the reference clock period",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 1,
+              "children": {
+                "fields": {
+                  "FC0_DELAY": {
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "FC0_INTERVAL": {
+              "description": "The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\\n\n            The default gives a test interval of 250us",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 8,
+              "children": {
+                "fields": {
+                  "FC0_INTERVAL": {
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "FC0_SRC": {
+              "description": "Clock sent to frequency counter, set to 0 when not required\\n\n            Writing to this register initiates the frequency count",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FC0_SRC": {
+                    "offset": 0,
+                    "size": 8,
+                    "enum": {
+                      "size": 8,
+                      "children": {
+                        "enum_fields": {
+                          "NULL": {
+                            "value": 0
+                          },
+                          "pll_sys_clksrc_primary": {
+                            "value": 1
+                          },
+                          "pll_usb_clksrc_primary": {
+                            "value": 2
+                          },
+                          "rosc_clksrc": {
+                            "value": 3
+                          },
+                          "rosc_clksrc_ph": {
+                            "value": 4
+                          },
+                          "xosc_clksrc": {
+                            "value": 5
+                          },
+                          "clksrc_gpin0": {
+                            "value": 6
+                          },
+                          "clksrc_gpin1": {
+                            "value": 7
+                          },
+                          "clk_ref": {
+                            "value": 8
+                          },
+                          "clk_sys": {
+                            "value": 9
+                          },
+                          "clk_peri": {
+                            "value": 10
+                          },
+                          "clk_usb": {
+                            "value": 11
+                          },
+                          "clk_adc": {
+                            "value": 12
+                          },
+                          "clk_rtc": {
+                            "value": 13
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FC0_STATUS": {
+              "description": "Frequency counter status",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DIED": {
+                    "description": "Test clock stopped during test",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FAST": {
+                    "description": "Test clock faster than expected, only valid when status_done=1",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLOW": {
+                    "description": "Test clock slower than expected, only valid when status_done=1",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FAIL": {
+                    "description": "Test failed",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WAITING": {
+                    "description": "Waiting for test clock to start",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RUNNING": {
+                    "description": "Test running",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DONE": {
+                    "description": "Test complete",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PASS": {
+                    "description": "Test passed",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FC0_RESULT": {
+              "description": "Result of frequency measurement, only valid when status_done=1",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "KHZ": {
+                    "offset": 5,
+                    "size": 25,
+                    "access": "read-only"
+                  },
+                  "FRAC": {
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "WAKE_EN0": {
+              "description": "enable clock in wake mode",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 4294967295,
+              "children": {
+                "fields": {
+                  "clk_sys_sram3": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "clk_sys_sram2": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "clk_sys_sram1": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "clk_sys_sram0": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "clk_sys_spi1": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "clk_peri_spi1": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "clk_sys_spi0": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "clk_peri_spi0": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "clk_sys_sio": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "clk_sys_rtc": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "clk_rtc_rtc": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "clk_sys_rosc": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "clk_sys_rom": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "clk_sys_resets": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "clk_sys_pwm": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "clk_sys_psm": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "clk_sys_pll_usb": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "clk_sys_pll_sys": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "clk_sys_pio1": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "clk_sys_pio0": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "clk_sys_pads": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "clk_sys_vreg_and_chip_reset": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "clk_sys_jtag": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "clk_sys_io": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "clk_sys_i2c1": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "clk_sys_i2c0": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "clk_sys_dma": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "clk_sys_busfabric": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "clk_sys_busctrl": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "clk_sys_adc": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "clk_adc_adc": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "clk_sys_clocks": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WAKE_EN1": {
+              "description": "enable clock in wake mode",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 32767,
+              "children": {
+                "fields": {
+                  "clk_sys_xosc": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "clk_sys_xip": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "clk_sys_watchdog": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "clk_usb_usbctrl": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "clk_sys_usbctrl": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "clk_sys_uart1": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "clk_peri_uart1": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "clk_sys_uart0": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "clk_peri_uart0": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "clk_sys_timer": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "clk_sys_tbman": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "clk_sys_sysinfo": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "clk_sys_syscfg": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "clk_sys_sram5": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "clk_sys_sram4": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLEEP_EN0": {
+              "description": "enable clock in sleep mode",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 4294967295,
+              "children": {
+                "fields": {
+                  "clk_sys_sram3": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "clk_sys_sram2": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "clk_sys_sram1": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "clk_sys_sram0": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "clk_sys_spi1": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "clk_peri_spi1": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "clk_sys_spi0": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "clk_peri_spi0": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "clk_sys_sio": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "clk_sys_rtc": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "clk_rtc_rtc": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "clk_sys_rosc": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "clk_sys_rom": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "clk_sys_resets": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "clk_sys_pwm": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "clk_sys_psm": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "clk_sys_pll_usb": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "clk_sys_pll_sys": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "clk_sys_pio1": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "clk_sys_pio0": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "clk_sys_pads": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "clk_sys_vreg_and_chip_reset": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "clk_sys_jtag": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "clk_sys_io": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "clk_sys_i2c1": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "clk_sys_i2c0": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "clk_sys_dma": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "clk_sys_busfabric": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "clk_sys_busctrl": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "clk_sys_adc": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "clk_adc_adc": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "clk_sys_clocks": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLEEP_EN1": {
+              "description": "enable clock in sleep mode",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 32767,
+              "children": {
+                "fields": {
+                  "clk_sys_xosc": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "clk_sys_xip": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "clk_sys_watchdog": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "clk_usb_usbctrl": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "clk_sys_usbctrl": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "clk_sys_uart1": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "clk_peri_uart1": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "clk_sys_uart0": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "clk_peri_uart0": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "clk_sys_timer": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "clk_sys_tbman": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "clk_sys_sysinfo": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "clk_sys_syscfg": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "clk_sys_sram5": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "clk_sys_sram4": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ENABLED0": {
+              "description": "indicates the state of the clock enable",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "clk_sys_sram3": {
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_sram2": {
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_sram1": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_sram0": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_spi1": {
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_peri_spi1": {
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_spi0": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_peri_spi0": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_sio": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_rtc": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_rtc_rtc": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_rosc": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_rom": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_resets": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_pwm": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_psm": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_pll_usb": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_pll_sys": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_pio1": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_pio0": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_pads": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_vreg_and_chip_reset": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_jtag": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_io": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_i2c1": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_i2c0": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_dma": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_busfabric": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_busctrl": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_adc": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_adc_adc": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_clocks": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ENABLED1": {
+              "description": "indicates the state of the clock enable",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "clk_sys_xosc": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_xip": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_watchdog": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_usb_usbctrl": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_usbctrl": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_uart1": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_peri_uart1": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_uart0": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_peri_uart0": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_timer": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_tbman": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_sysinfo": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_syscfg": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_sram5": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clk_sys_sram4": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTR": {
+              "description": "Raw Interrupts",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLK_SYS_RESUS": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTE": {
+              "description": "Interrupt Enable",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLK_SYS_RESUS": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTF": {
+              "description": "Interrupt Force",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLK_SYS_RESUS": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTS": {
+              "description": "Interrupt status after masking & forcing",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLK_SYS_RESUS": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RESETS": {
+        "children": {
+          "registers": {
+            "RESET": {
+              "description": "Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 33554431,
+              "children": {
+                "fields": {
+                  "usbctrl": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "uart1": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "uart0": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "timer": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "tbman": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "sysinfo": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "syscfg": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "spi1": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "spi0": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "rtc": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "pwm": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "pll_usb": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "pll_sys": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "pio1": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "pio0": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "pads_qspi": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "pads_bank0": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "jtag": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "io_qspi": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "io_bank0": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "i2c1": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "i2c0": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "dma": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "busctrl": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "adc": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WDSEL": {
+              "description": "Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "usbctrl": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "uart1": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "uart0": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "timer": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "tbman": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "sysinfo": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "syscfg": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "spi1": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "spi0": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "rtc": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "pwm": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "pll_usb": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "pll_sys": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "pio1": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "pio0": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "pads_qspi": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "pads_bank0": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "jtag": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "io_qspi": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "io_bank0": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "i2c1": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "i2c0": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "dma": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "busctrl": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "adc": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RESET_DONE": {
+              "description": "Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "usbctrl": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "uart1": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "uart0": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "timer": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "tbman": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "sysinfo": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "syscfg": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "spi1": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "spi0": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "rtc": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "pwm": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "pll_usb": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "pll_sys": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "pio1": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "pio0": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "pads_qspi": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "pads_bank0": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "jtag": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "io_qspi": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "io_bank0": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "i2c1": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "i2c0": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "dma": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "busctrl": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "adc": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PSM": {
+        "children": {
+          "registers": {
+            "FRCE_ON": {
+              "description": "Force block out of reset (i.e. power it on)",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "proc1": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "proc0": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "sio": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "vreg_and_chip_reset": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "xip": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "sram5": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "sram4": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "sram3": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "sram2": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "sram1": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "sram0": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "rom": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "busfabric": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "resets": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "clocks": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "xosc": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "rosc": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FRCE_OFF": {
+              "description": "Force into reset (i.e. power it off)",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "proc1": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "proc0": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "sio": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "vreg_and_chip_reset": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "xip": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "sram5": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "sram4": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "sram3": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "sram2": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "sram1": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "sram0": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "rom": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "busfabric": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "resets": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "clocks": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "xosc": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "rosc": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WDSEL": {
+              "description": "Set to 1 if this peripheral should be reset when the watchdog fires.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "proc1": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "proc0": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "sio": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "vreg_and_chip_reset": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "xip": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "sram5": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "sram4": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "sram3": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "sram2": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "sram1": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "sram0": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "rom": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "busfabric": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "resets": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "clocks": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "xosc": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "rosc": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DONE": {
+              "description": "Indicates the peripheral's registers are ready to access.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "proc1": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "proc0": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "sio": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "vreg_and_chip_reset": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "xip": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "sram5": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "sram4": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "sram3": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "sram2": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "sram1": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "sram0": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "rom": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "busfabric": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "resets": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "clocks": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "xosc": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "rosc": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "IO_BANK0": {
+        "children": {
+          "registers": {
+            "GPIO0_STATUS": {
+              "description": "GPIO status",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO0_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "jtag_tck": {
+                            "value": 0
+                          },
+                          "spi0_rx": {
+                            "value": 1
+                          },
+                          "uart0_tx": {
+                            "value": 2
+                          },
+                          "i2c0_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_0": {
+                            "value": 4
+                          },
+                          "sio_0": {
+                            "value": 5
+                          },
+                          "pio0_0": {
+                            "value": 6
+                          },
+                          "pio1_0": {
+                            "value": 7
+                          },
+                          "usb_muxing_overcurr_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO1_STATUS": {
+              "description": "GPIO status",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO1_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "jtag_tms": {
+                            "value": 0
+                          },
+                          "spi0_ss_n": {
+                            "value": 1
+                          },
+                          "uart0_rx": {
+                            "value": 2
+                          },
+                          "i2c0_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_0": {
+                            "value": 4
+                          },
+                          "sio_1": {
+                            "value": 5
+                          },
+                          "pio0_1": {
+                            "value": 6
+                          },
+                          "pio1_1": {
+                            "value": 7
+                          },
+                          "usb_muxing_vbus_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO2_STATUS": {
+              "description": "GPIO status",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO2_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "jtag_tdi": {
+                            "value": 0
+                          },
+                          "spi0_sclk": {
+                            "value": 1
+                          },
+                          "uart0_cts": {
+                            "value": 2
+                          },
+                          "i2c1_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_1": {
+                            "value": 4
+                          },
+                          "sio_2": {
+                            "value": 5
+                          },
+                          "pio0_2": {
+                            "value": 6
+                          },
+                          "pio1_2": {
+                            "value": 7
+                          },
+                          "usb_muxing_vbus_en": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO3_STATUS": {
+              "description": "GPIO status",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO3_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "jtag_tdo": {
+                            "value": 0
+                          },
+                          "spi0_tx": {
+                            "value": 1
+                          },
+                          "uart0_rts": {
+                            "value": 2
+                          },
+                          "i2c1_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_1": {
+                            "value": 4
+                          },
+                          "sio_3": {
+                            "value": 5
+                          },
+                          "pio0_3": {
+                            "value": 6
+                          },
+                          "pio1_3": {
+                            "value": 7
+                          },
+                          "usb_muxing_overcurr_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO4_STATUS": {
+              "description": "GPIO status",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO4_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_rx": {
+                            "value": 1
+                          },
+                          "uart1_tx": {
+                            "value": 2
+                          },
+                          "i2c0_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_2": {
+                            "value": 4
+                          },
+                          "sio_4": {
+                            "value": 5
+                          },
+                          "pio0_4": {
+                            "value": 6
+                          },
+                          "pio1_4": {
+                            "value": 7
+                          },
+                          "usb_muxing_vbus_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO5_STATUS": {
+              "description": "GPIO status",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO5_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_ss_n": {
+                            "value": 1
+                          },
+                          "uart1_rx": {
+                            "value": 2
+                          },
+                          "i2c0_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_2": {
+                            "value": 4
+                          },
+                          "sio_5": {
+                            "value": 5
+                          },
+                          "pio0_5": {
+                            "value": 6
+                          },
+                          "pio1_5": {
+                            "value": 7
+                          },
+                          "usb_muxing_vbus_en": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO6_STATUS": {
+              "description": "GPIO status",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO6_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_sclk": {
+                            "value": 1
+                          },
+                          "uart1_cts": {
+                            "value": 2
+                          },
+                          "i2c1_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_3": {
+                            "value": 4
+                          },
+                          "sio_6": {
+                            "value": 5
+                          },
+                          "pio0_6": {
+                            "value": 6
+                          },
+                          "pio1_6": {
+                            "value": 7
+                          },
+                          "usb_muxing_extphy_softcon": {
+                            "value": 8
+                          },
+                          "usb_muxing_overcurr_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO7_STATUS": {
+              "description": "GPIO status",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO7_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_tx": {
+                            "value": 1
+                          },
+                          "uart1_rts": {
+                            "value": 2
+                          },
+                          "i2c1_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_3": {
+                            "value": 4
+                          },
+                          "sio_7": {
+                            "value": 5
+                          },
+                          "pio0_7": {
+                            "value": 6
+                          },
+                          "pio1_7": {
+                            "value": 7
+                          },
+                          "usb_muxing_extphy_oe_n": {
+                            "value": 8
+                          },
+                          "usb_muxing_vbus_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO8_STATUS": {
+              "description": "GPIO status",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO8_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_rx": {
+                            "value": 1
+                          },
+                          "uart1_tx": {
+                            "value": 2
+                          },
+                          "i2c0_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_4": {
+                            "value": 4
+                          },
+                          "sio_8": {
+                            "value": 5
+                          },
+                          "pio0_8": {
+                            "value": 6
+                          },
+                          "pio1_8": {
+                            "value": 7
+                          },
+                          "usb_muxing_extphy_rcv": {
+                            "value": 8
+                          },
+                          "usb_muxing_vbus_en": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO9_STATUS": {
+              "description": "GPIO status",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO9_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_ss_n": {
+                            "value": 1
+                          },
+                          "uart1_rx": {
+                            "value": 2
+                          },
+                          "i2c0_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_4": {
+                            "value": 4
+                          },
+                          "sio_9": {
+                            "value": 5
+                          },
+                          "pio0_9": {
+                            "value": 6
+                          },
+                          "pio1_9": {
+                            "value": 7
+                          },
+                          "usb_muxing_extphy_vp": {
+                            "value": 8
+                          },
+                          "usb_muxing_overcurr_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO10_STATUS": {
+              "description": "GPIO status",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO10_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_sclk": {
+                            "value": 1
+                          },
+                          "uart1_cts": {
+                            "value": 2
+                          },
+                          "i2c1_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_5": {
+                            "value": 4
+                          },
+                          "sio_10": {
+                            "value": 5
+                          },
+                          "pio0_10": {
+                            "value": 6
+                          },
+                          "pio1_10": {
+                            "value": 7
+                          },
+                          "usb_muxing_extphy_vm": {
+                            "value": 8
+                          },
+                          "usb_muxing_vbus_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO11_STATUS": {
+              "description": "GPIO status",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO11_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_tx": {
+                            "value": 1
+                          },
+                          "uart1_rts": {
+                            "value": 2
+                          },
+                          "i2c1_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_5": {
+                            "value": 4
+                          },
+                          "sio_11": {
+                            "value": 5
+                          },
+                          "pio0_11": {
+                            "value": 6
+                          },
+                          "pio1_11": {
+                            "value": 7
+                          },
+                          "usb_muxing_extphy_suspnd": {
+                            "value": 8
+                          },
+                          "usb_muxing_vbus_en": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO12_STATUS": {
+              "description": "GPIO status",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO12_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_rx": {
+                            "value": 1
+                          },
+                          "uart0_tx": {
+                            "value": 2
+                          },
+                          "i2c0_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_6": {
+                            "value": 4
+                          },
+                          "sio_12": {
+                            "value": 5
+                          },
+                          "pio0_12": {
+                            "value": 6
+                          },
+                          "pio1_12": {
+                            "value": 7
+                          },
+                          "usb_muxing_extphy_speed": {
+                            "value": 8
+                          },
+                          "usb_muxing_overcurr_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO13_STATUS": {
+              "description": "GPIO status",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO13_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_ss_n": {
+                            "value": 1
+                          },
+                          "uart0_rx": {
+                            "value": 2
+                          },
+                          "i2c0_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_6": {
+                            "value": 4
+                          },
+                          "sio_13": {
+                            "value": 5
+                          },
+                          "pio0_13": {
+                            "value": 6
+                          },
+                          "pio1_13": {
+                            "value": 7
+                          },
+                          "usb_muxing_extphy_vpo": {
+                            "value": 8
+                          },
+                          "usb_muxing_vbus_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO14_STATUS": {
+              "description": "GPIO status",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO14_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_sclk": {
+                            "value": 1
+                          },
+                          "uart0_cts": {
+                            "value": 2
+                          },
+                          "i2c1_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_7": {
+                            "value": 4
+                          },
+                          "sio_14": {
+                            "value": 5
+                          },
+                          "pio0_14": {
+                            "value": 6
+                          },
+                          "pio1_14": {
+                            "value": 7
+                          },
+                          "usb_muxing_extphy_vmo": {
+                            "value": 8
+                          },
+                          "usb_muxing_vbus_en": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO15_STATUS": {
+              "description": "GPIO status",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO15_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_tx": {
+                            "value": 1
+                          },
+                          "uart0_rts": {
+                            "value": 2
+                          },
+                          "i2c1_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_7": {
+                            "value": 4
+                          },
+                          "sio_15": {
+                            "value": 5
+                          },
+                          "pio0_15": {
+                            "value": 6
+                          },
+                          "pio1_15": {
+                            "value": 7
+                          },
+                          "usb_muxing_digital_dp": {
+                            "value": 8
+                          },
+                          "usb_muxing_overcurr_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO16_STATUS": {
+              "description": "GPIO status",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO16_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_rx": {
+                            "value": 1
+                          },
+                          "uart0_tx": {
+                            "value": 2
+                          },
+                          "i2c0_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_0": {
+                            "value": 4
+                          },
+                          "sio_16": {
+                            "value": 5
+                          },
+                          "pio0_16": {
+                            "value": 6
+                          },
+                          "pio1_16": {
+                            "value": 7
+                          },
+                          "usb_muxing_digital_dm": {
+                            "value": 8
+                          },
+                          "usb_muxing_vbus_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO17_STATUS": {
+              "description": "GPIO status",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO17_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_ss_n": {
+                            "value": 1
+                          },
+                          "uart0_rx": {
+                            "value": 2
+                          },
+                          "i2c0_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_0": {
+                            "value": 4
+                          },
+                          "sio_17": {
+                            "value": 5
+                          },
+                          "pio0_17": {
+                            "value": 6
+                          },
+                          "pio1_17": {
+                            "value": 7
+                          },
+                          "usb_muxing_vbus_en": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO18_STATUS": {
+              "description": "GPIO status",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO18_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_sclk": {
+                            "value": 1
+                          },
+                          "uart0_cts": {
+                            "value": 2
+                          },
+                          "i2c1_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_1": {
+                            "value": 4
+                          },
+                          "sio_18": {
+                            "value": 5
+                          },
+                          "pio0_18": {
+                            "value": 6
+                          },
+                          "pio1_18": {
+                            "value": 7
+                          },
+                          "usb_muxing_overcurr_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO19_STATUS": {
+              "description": "GPIO status",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO19_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_tx": {
+                            "value": 1
+                          },
+                          "uart0_rts": {
+                            "value": 2
+                          },
+                          "i2c1_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_1": {
+                            "value": 4
+                          },
+                          "sio_19": {
+                            "value": 5
+                          },
+                          "pio0_19": {
+                            "value": 6
+                          },
+                          "pio1_19": {
+                            "value": 7
+                          },
+                          "usb_muxing_vbus_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO20_STATUS": {
+              "description": "GPIO status",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO20_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_rx": {
+                            "value": 1
+                          },
+                          "uart1_tx": {
+                            "value": 2
+                          },
+                          "i2c0_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_2": {
+                            "value": 4
+                          },
+                          "sio_20": {
+                            "value": 5
+                          },
+                          "pio0_20": {
+                            "value": 6
+                          },
+                          "pio1_20": {
+                            "value": 7
+                          },
+                          "clocks_gpin_0": {
+                            "value": 8
+                          },
+                          "usb_muxing_vbus_en": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO21_STATUS": {
+              "description": "GPIO status",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO21_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_ss_n": {
+                            "value": 1
+                          },
+                          "uart1_rx": {
+                            "value": 2
+                          },
+                          "i2c0_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_2": {
+                            "value": 4
+                          },
+                          "sio_21": {
+                            "value": 5
+                          },
+                          "pio0_21": {
+                            "value": 6
+                          },
+                          "pio1_21": {
+                            "value": 7
+                          },
+                          "clocks_gpout_0": {
+                            "value": 8
+                          },
+                          "usb_muxing_overcurr_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO22_STATUS": {
+              "description": "GPIO status",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO22_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_sclk": {
+                            "value": 1
+                          },
+                          "uart1_cts": {
+                            "value": 2
+                          },
+                          "i2c1_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_3": {
+                            "value": 4
+                          },
+                          "sio_22": {
+                            "value": 5
+                          },
+                          "pio0_22": {
+                            "value": 6
+                          },
+                          "pio1_22": {
+                            "value": 7
+                          },
+                          "clocks_gpin_1": {
+                            "value": 8
+                          },
+                          "usb_muxing_vbus_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO23_STATUS": {
+              "description": "GPIO status",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO23_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi0_tx": {
+                            "value": 1
+                          },
+                          "uart1_rts": {
+                            "value": 2
+                          },
+                          "i2c1_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_3": {
+                            "value": 4
+                          },
+                          "sio_23": {
+                            "value": 5
+                          },
+                          "pio0_23": {
+                            "value": 6
+                          },
+                          "pio1_23": {
+                            "value": 7
+                          },
+                          "clocks_gpout_1": {
+                            "value": 8
+                          },
+                          "usb_muxing_vbus_en": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO24_STATUS": {
+              "description": "GPIO status",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO24_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_rx": {
+                            "value": 1
+                          },
+                          "uart1_tx": {
+                            "value": 2
+                          },
+                          "i2c0_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_4": {
+                            "value": 4
+                          },
+                          "sio_24": {
+                            "value": 5
+                          },
+                          "pio0_24": {
+                            "value": 6
+                          },
+                          "pio1_24": {
+                            "value": 7
+                          },
+                          "clocks_gpout_2": {
+                            "value": 8
+                          },
+                          "usb_muxing_overcurr_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO25_STATUS": {
+              "description": "GPIO status",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO25_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_ss_n": {
+                            "value": 1
+                          },
+                          "uart1_rx": {
+                            "value": 2
+                          },
+                          "i2c0_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_4": {
+                            "value": 4
+                          },
+                          "sio_25": {
+                            "value": 5
+                          },
+                          "pio0_25": {
+                            "value": 6
+                          },
+                          "pio1_25": {
+                            "value": 7
+                          },
+                          "clocks_gpout_3": {
+                            "value": 8
+                          },
+                          "usb_muxing_vbus_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO26_STATUS": {
+              "description": "GPIO status",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO26_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_sclk": {
+                            "value": 1
+                          },
+                          "uart1_cts": {
+                            "value": 2
+                          },
+                          "i2c1_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_5": {
+                            "value": 4
+                          },
+                          "sio_26": {
+                            "value": 5
+                          },
+                          "pio0_26": {
+                            "value": 6
+                          },
+                          "pio1_26": {
+                            "value": 7
+                          },
+                          "usb_muxing_vbus_en": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO27_STATUS": {
+              "description": "GPIO status",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO27_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_tx": {
+                            "value": 1
+                          },
+                          "uart1_rts": {
+                            "value": 2
+                          },
+                          "i2c1_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_5": {
+                            "value": 4
+                          },
+                          "sio_27": {
+                            "value": 5
+                          },
+                          "pio0_27": {
+                            "value": 6
+                          },
+                          "pio1_27": {
+                            "value": 7
+                          },
+                          "usb_muxing_overcurr_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO28_STATUS": {
+              "description": "GPIO status",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO28_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_rx": {
+                            "value": 1
+                          },
+                          "uart0_tx": {
+                            "value": 2
+                          },
+                          "i2c0_sda": {
+                            "value": 3
+                          },
+                          "pwm_a_6": {
+                            "value": 4
+                          },
+                          "sio_28": {
+                            "value": 5
+                          },
+                          "pio0_28": {
+                            "value": 6
+                          },
+                          "pio1_28": {
+                            "value": 7
+                          },
+                          "usb_muxing_vbus_detect": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO29_STATUS": {
+              "description": "GPIO status",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO29_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "spi1_ss_n": {
+                            "value": 1
+                          },
+                          "uart0_rx": {
+                            "value": 2
+                          },
+                          "i2c0_scl": {
+                            "value": 3
+                          },
+                          "pwm_b_6": {
+                            "value": 4
+                          },
+                          "sio_29": {
+                            "value": 5
+                          },
+                          "pio0_29": {
+                            "value": 6
+                          },
+                          "pio1_29": {
+                            "value": 7
+                          },
+                          "usb_muxing_vbus_en": {
+                            "value": 9
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTR0": {
+              "description": "Raw Interrupts",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO7_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO7_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO7_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTR1": {
+              "description": "Raw Interrupts",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO15_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO15_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO15_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTR2": {
+              "description": "Raw Interrupts",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO23_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO23_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO23_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTR3": {
+              "description": "Raw Interrupts",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO29_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO29_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO29_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PROC0_INTE0": {
+              "description": "Interrupt Enable for proc0",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO7_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO7_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC0_INTE1": {
+              "description": "Interrupt Enable for proc0",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO15_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO15_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC0_INTE2": {
+              "description": "Interrupt Enable for proc0",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO23_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO23_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC0_INTE3": {
+              "description": "Interrupt Enable for proc0",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO29_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO29_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC0_INTF0": {
+              "description": "Interrupt Force for proc0",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO7_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO7_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC0_INTF1": {
+              "description": "Interrupt Force for proc0",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO15_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO15_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC0_INTF2": {
+              "description": "Interrupt Force for proc0",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO23_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO23_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC0_INTF3": {
+              "description": "Interrupt Force for proc0",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO29_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO29_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC0_INTS0": {
+              "description": "Interrupt status after masking & forcing for proc0",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO7_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO7_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO7_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO7_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PROC0_INTS1": {
+              "description": "Interrupt status after masking & forcing for proc0",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO15_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO15_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO15_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO15_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PROC0_INTS2": {
+              "description": "Interrupt status after masking & forcing for proc0",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO23_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO23_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO23_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO23_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PROC0_INTS3": {
+              "description": "Interrupt status after masking & forcing for proc0",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO29_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO29_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO29_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO29_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PROC1_INTE0": {
+              "description": "Interrupt Enable for proc1",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO7_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO7_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC1_INTE1": {
+              "description": "Interrupt Enable for proc1",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO15_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO15_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC1_INTE2": {
+              "description": "Interrupt Enable for proc1",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO23_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO23_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC1_INTE3": {
+              "description": "Interrupt Enable for proc1",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO29_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO29_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC1_INTF0": {
+              "description": "Interrupt Force for proc1",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO7_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO7_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC1_INTF1": {
+              "description": "Interrupt Force for proc1",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO15_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO15_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC1_INTF2": {
+              "description": "Interrupt Force for proc1",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO23_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO23_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC1_INTF3": {
+              "description": "Interrupt Force for proc1",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO29_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO29_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC1_INTS0": {
+              "description": "Interrupt status after masking & forcing for proc1",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO7_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO7_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO7_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO7_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PROC1_INTS1": {
+              "description": "Interrupt status after masking & forcing for proc1",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO15_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO15_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO15_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO15_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PROC1_INTS2": {
+              "description": "Interrupt status after masking & forcing for proc1",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO23_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO23_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO23_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO23_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PROC1_INTS3": {
+              "description": "Interrupt status after masking & forcing for proc1",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO29_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO29_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO29_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO29_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTE0": {
+              "description": "Interrupt Enable for dormant_wake",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO7_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO7_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTE1": {
+              "description": "Interrupt Enable for dormant_wake",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO15_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO15_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTE2": {
+              "description": "Interrupt Enable for dormant_wake",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO23_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO23_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTE3": {
+              "description": "Interrupt Enable for dormant_wake",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO29_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO29_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTF0": {
+              "description": "Interrupt Force for dormant_wake",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO7_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO7_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO7_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO6_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO6_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO5_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO5_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO4_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO4_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO3_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO3_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO2_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO2_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO1_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO1_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO0_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO0_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTF1": {
+              "description": "Interrupt Force for dormant_wake",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO15_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO15_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO15_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO14_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO14_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO13_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO13_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO12_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO12_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO11_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO11_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO10_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO10_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO9_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO9_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO8_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO8_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTF2": {
+              "description": "Interrupt Force for dormant_wake",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO23_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "GPIO23_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "GPIO23_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "GPIO22_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "GPIO22_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO21_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO21_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO20_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO20_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO19_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO19_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO18_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO18_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO17_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO17_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO16_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO16_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTF3": {
+              "description": "Interrupt Force for dormant_wake",
+              "offset": 380,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO29_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO29_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO29_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO28_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO28_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO27_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO27_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO26_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO26_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO25_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO25_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO24_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO24_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTS0": {
+              "description": "Interrupt status after masking & forcing for dormant_wake",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO7_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO7_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO7_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO7_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO6_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO5_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO4_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO3_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO2_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO1_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO0_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTS1": {
+              "description": "Interrupt status after masking & forcing for dormant_wake",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO15_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO15_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO15_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO15_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO14_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO13_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO12_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO11_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO10_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO9_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO8_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTS2": {
+              "description": "Interrupt status after masking & forcing for dormant_wake",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO23_EDGE_HIGH": {
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO23_EDGE_LOW": {
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO23_LEVEL_HIGH": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO23_LEVEL_LOW": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_EDGE_HIGH": {
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_EDGE_LOW": {
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_LEVEL_HIGH": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO22_LEVEL_LOW": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO21_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO20_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO19_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO18_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO17_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO16_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTS3": {
+              "description": "Interrupt status after masking & forcing for dormant_wake",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO29_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO29_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO29_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO29_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO28_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO27_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO26_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO25_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO24_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "IO_QSPI": {
+        "children": {
+          "registers": {
+            "GPIO_QSPI_SCLK_STATUS": {
+              "description": "GPIO status",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SCLK_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "xip_sclk": {
+                            "value": 0
+                          },
+                          "sio_30": {
+                            "value": 5
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SS_STATUS": {
+              "description": "GPIO status",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SS_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "xip_ss_n": {
+                            "value": 0
+                          },
+                          "sio_31": {
+                            "value": 5
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD0_STATUS": {
+              "description": "GPIO status",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD0_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "xip_sd0": {
+                            "value": 0
+                          },
+                          "sio_32": {
+                            "value": 5
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD1_STATUS": {
+              "description": "GPIO status",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD1_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "xip_sd1": {
+                            "value": 0
+                          },
+                          "sio_33": {
+                            "value": 5
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD2_STATUS": {
+              "description": "GPIO status",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD2_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "xip_sd2": {
+                            "value": 0
+                          },
+                          "sio_34": {
+                            "value": 5
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD3_STATUS": {
+              "description": "GPIO status",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQTOPROC": {
+                    "description": "interrupt to processors, after override is applied",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IRQFROMPAD": {
+                    "description": "interrupt from pad before override is applied",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTOPERI": {
+                    "description": "input signal to peripheral, after override is applied",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFROMPAD": {
+                    "description": "input signal from pad, before override is applied",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OETOPAD": {
+                    "description": "output enable to pad after register override is applied",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OEFROMPERI": {
+                    "description": "output enable from selected peripheral, before register override is applied",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTTOPAD": {
+                    "description": "output signal to pad after register override is applied",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFROMPERI": {
+                    "description": "output signal from selected peripheral, before register override is applied",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD3_CTRL": {
+              "description": "GPIO control including function select and overrides.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "IRQOVER": {
+                    "offset": 28,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the interrupt",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the interrupt",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive interrupt low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive interrupt high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INOVER": {
+                    "offset": 16,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "don't invert the peri input",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "invert the peri input",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive peri input low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive peri input high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OEOVER": {
+                    "offset": 12,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output enable from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output enable from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "DISABLE": {
+                            "description": "disable output",
+                            "value": 2
+                          },
+                          "ENABLE": {
+                            "description": "enable output",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "OUTOVER": {
+                    "offset": 8,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "NORMAL": {
+                            "description": "drive output from peripheral signal selected by funcsel",
+                            "value": 0
+                          },
+                          "INVERT": {
+                            "description": "drive output from inverse of peripheral signal selected by funcsel",
+                            "value": 1
+                          },
+                          "LOW": {
+                            "description": "drive output low",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "drive output high",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FUNCSEL": {
+                    "description": "0-31 -> selects pin function according to the gpio table\\n\n                31 == NULL",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "xip_sd3": {
+                            "value": 0
+                          },
+                          "sio_35": {
+                            "value": 5
+                          },
+                          "null": {
+                            "value": 31
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "INTR": {
+              "description": "Raw Interrupts",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_QSPI_SD3_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PROC0_INTE": {
+              "description": "Interrupt Enable for proc0",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_QSPI_SD3_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC0_INTF": {
+              "description": "Interrupt Force for proc0",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_QSPI_SD3_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC0_INTS": {
+              "description": "Interrupt status after masking & forcing for proc0",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_QSPI_SD3_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD3_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PROC1_INTE": {
+              "description": "Interrupt Enable for proc1",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_QSPI_SD3_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC1_INTF": {
+              "description": "Interrupt Force for proc1",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_QSPI_SD3_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PROC1_INTS": {
+              "description": "Interrupt status after masking & forcing for proc1",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_QSPI_SD3_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD3_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTE": {
+              "description": "Interrupt Enable for dormant_wake",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_QSPI_SD3_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTF": {
+              "description": "Interrupt Force for dormant_wake",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_QSPI_SD3_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SS_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DORMANT_WAKE_INTS": {
+              "description": "Interrupt status after masking & forcing for dormant_wake",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_QSPI_SD3_EDGE_HIGH": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD3_EDGE_LOW": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_HIGH": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD3_LEVEL_LOW": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_EDGE_HIGH": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_EDGE_LOW": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_HIGH": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD2_LEVEL_LOW": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_EDGE_HIGH": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_EDGE_LOW": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_HIGH": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD1_LEVEL_LOW": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_EDGE_HIGH": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_EDGE_LOW": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_HIGH": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SD0_LEVEL_LOW": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_EDGE_HIGH": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_EDGE_LOW": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_LEVEL_HIGH": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SS_LEVEL_LOW": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_HIGH": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_EDGE_LOW": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_HIGH": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GPIO_QSPI_SCLK_LEVEL_LOW": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PADS_BANK0": {
+        "children": {
+          "registers": {
+            "VOLTAGE_SELECT": {
+              "description": "Voltage select. Per bank control",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "VOLTAGE_SELECT": {
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "3v3": {
+                            "description": "Set voltage to 3.3V (DVDD >= 2V5)",
+                            "value": 0
+                          },
+                          "1v8": {
+                            "description": "Set voltage to 1.8V (DVDD <= 1V8)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO0": {
+              "description": "Pad control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO1": {
+              "description": "Pad control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO2": {
+              "description": "Pad control register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO3": {
+              "description": "Pad control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO4": {
+              "description": "Pad control register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO5": {
+              "description": "Pad control register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO6": {
+              "description": "Pad control register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO7": {
+              "description": "Pad control register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO8": {
+              "description": "Pad control register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO9": {
+              "description": "Pad control register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO10": {
+              "description": "Pad control register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO11": {
+              "description": "Pad control register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO12": {
+              "description": "Pad control register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO13": {
+              "description": "Pad control register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO14": {
+              "description": "Pad control register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO15": {
+              "description": "Pad control register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO16": {
+              "description": "Pad control register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO17": {
+              "description": "Pad control register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO18": {
+              "description": "Pad control register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO19": {
+              "description": "Pad control register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO20": {
+              "description": "Pad control register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO21": {
+              "description": "Pad control register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO22": {
+              "description": "Pad control register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO23": {
+              "description": "Pad control register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO24": {
+              "description": "Pad control register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO25": {
+              "description": "Pad control register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO26": {
+              "description": "Pad control register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO27": {
+              "description": "Pad control register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO28": {
+              "description": "Pad control register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO29": {
+              "description": "Pad control register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWCLK": {
+              "description": "Pad control register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 218,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWD": {
+              "description": "Pad control register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 90,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PADS_QSPI": {
+        "children": {
+          "registers": {
+            "VOLTAGE_SELECT": {
+              "description": "Voltage select. Per bank control",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "VOLTAGE_SELECT": {
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "3v3": {
+                            "description": "Set voltage to 3.3V (DVDD >= 2V5)",
+                            "value": 0
+                          },
+                          "1v8": {
+                            "description": "Set voltage to 1.8V (DVDD <= 1V8)",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SCLK": {
+              "description": "Pad control register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 86,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD0": {
+              "description": "Pad control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 82,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD1": {
+              "description": "Pad control register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 82,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD2": {
+              "description": "Pad control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 82,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SD3": {
+              "description": "Pad control register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 82,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "GPIO_QSPI_SS": {
+              "description": "Pad control register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 90,
+              "children": {
+                "fields": {
+                  "OD": {
+                    "description": "Output disable. Has priority over output enable from peripherals",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IE": {
+                    "description": "Input enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DRIVE": {
+                    "description": "Drive strength.",
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "2mA": {
+                            "value": 0
+                          },
+                          "4mA": {
+                            "value": 1
+                          },
+                          "8mA": {
+                            "value": 2
+                          },
+                          "12mA": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "PUE": {
+                    "description": "Pull up enable",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PDE": {
+                    "description": "Pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SCHMITT": {
+                    "description": "Enable schmitt trigger",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLEWFAST": {
+                    "description": "Slew rate control. 1 = Fast, 0 = Slow",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "XOSC": {
+        "description": "Controls the crystal oscillator",
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "Crystal Oscillator Control",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "On power-up this field is initialised to DISABLE and the chip runs from the ROSC.\\n\n                If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.\\n\n                The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.",
+                    "offset": 12,
+                    "size": 12,
+                    "enum": {
+                      "size": 12,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "value": 3358
+                          },
+                          "ENABLE": {
+                            "value": 4011
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FREQ_RANGE": {
+                    "description": "Frequency range. This resets to 0xAA0 and cannot be changed.",
+                    "offset": 0,
+                    "size": 12,
+                    "enum": {
+                      "size": 12,
+                      "children": {
+                        "enum_fields": {
+                          "1_15MHZ": {
+                            "value": 2720
+                          },
+                          "RESERVED_1": {
+                            "value": 2721
+                          },
+                          "RESERVED_2": {
+                            "value": 2722
+                          },
+                          "RESERVED_3": {
+                            "value": 2723
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Crystal Oscillator Status",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "STABLE": {
+                    "description": "Oscillator is running and stable",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BADWRITE": {
+                    "description": "An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "ENABLED": {
+                    "description": "Oscillator is enabled but not necessarily running and stable, resets to 0",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FREQ_RANGE": {
+                    "description": "The current frequency range setting, always reads 0",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "1_15MHZ": {
+                            "value": 0
+                          },
+                          "RESERVED_1": {
+                            "value": 1
+                          },
+                          "RESERVED_2": {
+                            "value": 2
+                          },
+                          "RESERVED_3": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "DORMANT": {
+              "description": "Crystal Oscillator pause control\\n\n            This is used to save power by pausing the XOSC\\n\n            On power-up this field is initialised to WAKE\\n\n            An invalid write will also select WAKE\\n\n            WARNING: stop the PLLs before selecting dormant mode\\n\n            WARNING: setup the irq before selecting dormant mode",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0
+            },
+            "STARTUP": {
+              "description": "Controls the startup delay",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 196,
+              "children": {
+                "fields": {
+                  "X4": {
+                    "description": "Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "DELAY": {
+                    "description": "in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "COUNT": {
+              "description": "A down counter running at the xosc frequency which counts to zero and stops.\\n\n            To start the counter write a non-zero value.\\n\n            Can be used for short software pauses when setting up time sensitive hardware.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "COUNT": {
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PLL_SYS": {
+        "children": {
+          "registers": {
+            "CS": {
+              "description": "Control and Status\\n\n            GENERAL CONSTRAINTS:\\n\n            Reference clock frequency min=5MHz, max=800MHz\\n\n            Feedback divider min=16, max=320\\n\n            VCO frequency min=400MHz, max=1600MHz",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1,
+              "children": {
+                "fields": {
+                  "LOCK": {
+                    "description": "PLL is locked",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BYPASS": {
+                    "description": "Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "REFDIV": {
+                    "description": "Divides the PLL input reference clock.\\n\n                Behaviour is undefined for div=0.\\n\n                PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "PWR": {
+              "description": "Controls the PLL power modes.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 45,
+              "children": {
+                "fields": {
+                  "VCOPD": {
+                    "description": "PLL VCO powerdown\\n\n                To save power set high when PLL output not required or bypass=1.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "POSTDIVPD": {
+                    "description": "PLL post divider powerdown\\n\n                To save power set high when PLL output not required or bypass=1.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DSMPD": {
+                    "description": "PLL DSM powerdown\\n\n                Nothing is achieved by setting this low.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PD": {
+                    "description": "PLL powerdown\\n\n                To save power set high when PLL output not required.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FBDIV_INT": {
+              "description": "Feedback divisor\\n\n            (note: this PLL does not support fractional division)",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FBDIV_INT": {
+                    "description": "see ctrl reg description for constraints",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "PRIM": {
+              "description": "Controls the PLL post dividers for the primary output\\n\n            (note: this PLL does not have a secondary output)\\n\n            the primary output is driven from VCO divided by postdiv1*postdiv2",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 487424,
+              "children": {
+                "fields": {
+                  "POSTDIV1": {
+                    "description": "divide by 1-7",
+                    "offset": 16,
+                    "size": 3
+                  },
+                  "POSTDIV2": {
+                    "description": "divide by 1-7",
+                    "offset": 12,
+                    "size": 3
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PPB": {
+        "children": {
+          "registers": {
+            "SYST_CSR": {
+              "description": "Use the SysTick Control and Status Register to enable the SysTick features.",
+              "offset": 57360,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "COUNTFLAG": {
+                    "description": "Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CLKSOURCE": {
+                    "description": "SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.\\n\n                Selects the SysTick timer clock source:\\n\n                0 = External reference clock.\\n\n                1 = Processor clock.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TICKINT": {
+                    "description": "Enables SysTick exception request:\\n\n                0 = Counting down to zero does not assert the SysTick exception request.\\n\n                1 = Counting down to zero to asserts the SysTick exception request.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ENABLE": {
+                    "description": "Enable SysTick counter:\\n\n                0 = Counter disabled.\\n\n                1 = Counter enabled.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SYST_RVR": {
+              "description": "Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.\\n\n            To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.",
+              "offset": 57364,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RELOAD": {
+                    "description": "Value to load into the SysTick Current Value Register when the counter reaches 0.",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "SYST_CVR": {
+              "description": "Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.",
+              "offset": 57368,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CURRENT": {
+                    "description": "Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "SYST_CALIB": {
+              "description": "Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.",
+              "offset": 57372,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "NOREF": {
+                    "description": "If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SKEW": {
+                    "description": "If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TENMS": {
+                    "description": "An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "NVIC_ISER": {
+              "description": "Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.\\n\n            If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.",
+              "offset": 57600,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SETENA": {
+                    "description": "Interrupt set-enable bits.\\n\n                Write:\\n\n                0 = No effect.\\n\n                1 = Enable interrupt.\\n\n                Read:\\n\n                0 = Interrupt disabled.\\n\n                1 = Interrupt enabled.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "NVIC_ICER": {
+              "description": "Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.",
+              "offset": 57728,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLRENA": {
+                    "description": "Interrupt clear-enable bits.\\n\n                Write:\\n\n                0 = No effect.\\n\n                1 = Disable interrupt.\\n\n                Read:\\n\n                0 = Interrupt disabled.\\n\n                1 = Interrupt enabled.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "NVIC_ISPR": {
+              "description": "The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.",
+              "offset": 57856,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SETPEND": {
+                    "description": "Interrupt set-pending bits.\\n\n                Write:\\n\n                0 = No effect.\\n\n                1 = Changes interrupt state to pending.\\n\n                Read:\\n\n                0 = Interrupt is not pending.\\n\n                1 = Interrupt is pending.\\n\n                Note: Writing 1 to the NVIC_ISPR bit corresponding to:\\n\n                An interrupt that is pending has no effect.\\n\n                A disabled interrupt sets the state of that interrupt to pending.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "NVIC_ICPR": {
+              "description": "Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.",
+              "offset": 57984,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLRPEND": {
+                    "description": "Interrupt clear-pending bits.\\n\n                Write:\\n\n                0 = No effect.\\n\n                1 = Removes pending state and interrupt.\\n\n                Read:\\n\n                0 = Interrupt is not pending.\\n\n                1 = Interrupt is pending.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "NVIC_IPR0": {
+              "description": "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.\\n\n            Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.\\n\n            These registers are only word-accessible",
+              "offset": 58368,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IP_3": {
+                    "description": "Priority of interrupt 3",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "IP_2": {
+                    "description": "Priority of interrupt 2",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "IP_1": {
+                    "description": "Priority of interrupt 1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "IP_0": {
+                    "description": "Priority of interrupt 0",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "NVIC_IPR1": {
+              "description": "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.",
+              "offset": 58372,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IP_7": {
+                    "description": "Priority of interrupt 7",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "IP_6": {
+                    "description": "Priority of interrupt 6",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "IP_5": {
+                    "description": "Priority of interrupt 5",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "IP_4": {
+                    "description": "Priority of interrupt 4",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "NVIC_IPR2": {
+              "description": "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.",
+              "offset": 58376,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IP_11": {
+                    "description": "Priority of interrupt 11",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "IP_10": {
+                    "description": "Priority of interrupt 10",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "IP_9": {
+                    "description": "Priority of interrupt 9",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "IP_8": {
+                    "description": "Priority of interrupt 8",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "NVIC_IPR3": {
+              "description": "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.",
+              "offset": 58380,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IP_15": {
+                    "description": "Priority of interrupt 15",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "IP_14": {
+                    "description": "Priority of interrupt 14",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "IP_13": {
+                    "description": "Priority of interrupt 13",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "IP_12": {
+                    "description": "Priority of interrupt 12",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "NVIC_IPR4": {
+              "description": "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.",
+              "offset": 58384,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IP_19": {
+                    "description": "Priority of interrupt 19",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "IP_18": {
+                    "description": "Priority of interrupt 18",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "IP_17": {
+                    "description": "Priority of interrupt 17",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "IP_16": {
+                    "description": "Priority of interrupt 16",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "NVIC_IPR5": {
+              "description": "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.",
+              "offset": 58388,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IP_23": {
+                    "description": "Priority of interrupt 23",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "IP_22": {
+                    "description": "Priority of interrupt 22",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "IP_21": {
+                    "description": "Priority of interrupt 21",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "IP_20": {
+                    "description": "Priority of interrupt 20",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "NVIC_IPR6": {
+              "description": "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.",
+              "offset": 58392,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IP_27": {
+                    "description": "Priority of interrupt 27",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "IP_26": {
+                    "description": "Priority of interrupt 26",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "IP_25": {
+                    "description": "Priority of interrupt 25",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "IP_24": {
+                    "description": "Priority of interrupt 24",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "NVIC_IPR7": {
+              "description": "Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.",
+              "offset": 58396,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IP_31": {
+                    "description": "Priority of interrupt 31",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "IP_30": {
+                    "description": "Priority of interrupt 30",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "IP_29": {
+                    "description": "Priority of interrupt 29",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "IP_28": {
+                    "description": "Priority of interrupt 28",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CPUID": {
+              "description": "Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.",
+              "offset": 60672,
+              "size": 32,
+              "reset_value": 1091356161,
+              "children": {
+                "fields": {
+                  "IMPLEMENTER": {
+                    "description": "Implementor code: 0x41 = ARM",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "VARIANT": {
+                    "description": "Major revision number n in the rnpm revision status:\\n\n                0x0 = Revision 0.",
+                    "offset": 20,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "ARCHITECTURE": {
+                    "description": "Constant that defines the architecture of the processor:\\n\n                0xC = ARMv6-M architecture.",
+                    "offset": 16,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "PARTNO": {
+                    "description": "Number of processor within family: 0xC60 = Cortex-M0+",
+                    "offset": 4,
+                    "size": 12,
+                    "access": "read-only"
+                  },
+                  "REVISION": {
+                    "description": "Minor revision number m in the rnpm revision status:\\n\n                0x1 = Patch 1.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ICSR": {
+              "description": "Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.",
+              "offset": 60676,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "NMIPENDSET": {
+                    "description": "Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.\\n\n                NMI set-pending bit.\\n\n                Write:\\n\n                0 = No effect.\\n\n                1 = Changes NMI exception state to pending.\\n\n                Read:\\n\n                0 = NMI exception is not pending.\\n\n                1 = NMI exception is pending.\\n\n                Because NMI is the highest-priority exception, normally the processor enters the NMI\\n\n                exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears\\n\n                this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the\\n\n                NMI signal is reasserted while the processor is executing that handler.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "PENDSVSET": {
+                    "description": "PendSV set-pending bit.\\n\n                Write:\\n\n                0 = No effect.\\n\n                1 = Changes PendSV exception state to pending.\\n\n                Read:\\n\n                0 = PendSV exception is not pending.\\n\n                1 = PendSV exception is pending.\\n\n                Writing 1 to this bit is the only way to set the PendSV exception state to pending.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "PENDSVCLR": {
+                    "description": "PendSV clear-pending bit.\\n\n                Write:\\n\n                0 = No effect.\\n\n                1 = Removes the pending state from the PendSV exception.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "PENDSTSET": {
+                    "description": "SysTick exception set-pending bit.\\n\n                Write:\\n\n                0 = No effect.\\n\n                1 = Changes SysTick exception state to pending.\\n\n                Read:\\n\n                0 = SysTick exception is not pending.\\n\n                1 = SysTick exception is pending.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PENDSTCLR": {
+                    "description": "SysTick exception clear-pending bit.\\n\n                Write:\\n\n                0 = No effect.\\n\n                1 = Removes the pending state from the SysTick exception.\\n\n                This bit is WO. On a register read its value is Unknown.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ISRPREEMPT": {
+                    "description": "The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ISRPENDING": {
+                    "description": "External interrupt pending flag",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "VECTPENDING": {
+                    "description": "Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.",
+                    "offset": 12,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "VECTACTIVE": {
+                    "description": "Active exception number field. Reset clears the VECTACTIVE field.",
+                    "offset": 0,
+                    "size": 9,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "VTOR": {
+              "description": "The VTOR holds the vector table offset address.",
+              "offset": 60680,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TBLOFF": {
+                    "description": "Bits [31:8] of the indicate the vector table offset address.",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "AIRCR": {
+              "description": "Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.",
+              "offset": 60684,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "VECTKEY": {
+                    "description": "Register key:\\n\n                Reads as Unknown\\n\n                On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "ENDIANESS": {
+                    "description": "Data endianness implemented:\\n\n                0 = Little-endian.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SYSRESETREQ": {
+                    "description": "Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "VECTCLRACTIVE": {
+                    "description": "Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted.  When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SCR": {
+              "description": "System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.",
+              "offset": 60688,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SEVONPEND": {
+                    "description": "Send Event on Pending bit:\\n\n                0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.\\n\n                1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.\\n\n                When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the\\n\n                processor is not waiting for an event, the event is registered and affects the next WFE.\\n\n                The processor also wakes up on execution of an SEV instruction or an external event.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SLEEPDEEP": {
+                    "description": "Controls whether the processor uses sleep or deep sleep as its low power mode:\\n\n                0 = Sleep.\\n\n                1 = Deep sleep.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLEEPONEXIT": {
+                    "description": "Indicates sleep-on-exit when returning from Handler mode to Thread mode:\\n\n                0 = Do not sleep when returning to Thread mode.\\n\n                1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.\\n\n                Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CCR": {
+              "description": "The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.",
+              "offset": 60692,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "STKALIGN": {
+                    "description": "Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "UNALIGN_TRP": {
+                    "description": "Always reads as one, indicates that all unaligned accesses generate a HardFault.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SHPR2": {
+              "description": "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.",
+              "offset": 60700,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PRI_11": {
+                    "description": "Priority of system handler 11, SVCall",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "SHPR3": {
+              "description": "System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.",
+              "offset": 60704,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PRI_15": {
+                    "description": "Priority of system handler 15, SysTick",
+                    "offset": 30,
+                    "size": 2
+                  },
+                  "PRI_14": {
+                    "description": "Priority of system handler 14, PendSV",
+                    "offset": 22,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "SHCSR": {
+              "description": "Use the System Handler Control and State Register to determine or clear the pending status of SVCall.",
+              "offset": 60708,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SVCALLPENDED": {
+                    "description": "Reads as 1 if SVCall is Pending.  Write 1 to set pending SVCall, write 0 to clear pending SVCall.",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MPU_TYPE": {
+              "description": "Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.",
+              "offset": 60816,
+              "size": 32,
+              "reset_value": 2048,
+              "children": {
+                "fields": {
+                  "IREGION": {
+                    "description": "Instruction region. Reads as zero as ARMv6-M only supports a unified MPU.",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "DREGION": {
+                    "description": "Number of regions supported by the MPU.",
+                    "offset": 8,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "SEPARATE": {
+                    "description": "Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MPU_CTRL": {
+              "description": "Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.",
+              "offset": 60820,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PRIVDEFENA": {
+                    "description": "Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.\\n\n                0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not\\n\n                covered by any enabled region causes a fault.\\n\n                1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.\\n\n                When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "HFNMIENA": {
+                    "description": "Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.\\n\n                When the MPU is enabled:\\n\n                0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.\\n\n                1 = the MPU is enabled during HardFault and NMI handlers.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ENABLE": {
+                    "description": "Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.\\n\n                0 = MPU disabled.\\n\n                1 = MPU enabled.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MPU_RNR": {
+              "description": "Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.",
+              "offset": 60824,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "REGION": {
+                    "description": "Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.\\n\n                The MPU supports 8 memory regions, so the permitted values of this field are 0-7.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MPU_RBAR": {
+              "description": "Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.",
+              "offset": 60828,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ADDR": {
+                    "description": "Base address of the region.",
+                    "offset": 8,
+                    "size": 24
+                  },
+                  "VALID": {
+                    "description": "On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.\\n\n                Write:\\n\n                0 = MPU_RNR not changed, and the processor:\\n\n                Updates the base address for the region specified in the MPU_RNR.\\n\n                Ignores the value of the REGION field.\\n\n                1 = The processor:\\n\n                Updates the value of the MPU_RNR to the value of the REGION field.\\n\n                Updates the base address for the region specified in the REGION field.\\n\n                Always reads as zero.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "REGION": {
+                    "description": "On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MPU_RASR": {
+              "description": "Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.",
+              "offset": 60832,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ATTRS": {
+                    "description": "The MPU Region Attribute field. Use to define the region attribute control.\\n\n                28 = XN: Instruction access disable bit:\\n\n                0 = Instruction fetches enabled.\\n\n                1 = Instruction fetches disabled.\\n\n                26:24 = AP: Access permission field\\n\n                18 = S: Shareable bit\\n\n                17 = C: Cacheable bit\\n\n                16 = B: Bufferable bit",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "SRD": {
+                    "description": "Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "SIZE": {
+                    "description": "Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes",
+                    "offset": 1,
+                    "size": 5
+                  },
+                  "ENABLE": {
+                    "description": "Enables the region.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "BUSCTRL": {
+        "description": "Register block for busfabric control signals and performance counters",
+        "children": {
+          "registers": {
+            "BUS_PRIORITY": {
+              "description": "Set the priority of each master for bus arbitration.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DMA_W": {
+                    "description": "0 - low priority, 1 - high priority",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DMA_R": {
+                    "description": "0 - low priority, 1 - high priority",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PROC1": {
+                    "description": "0 - low priority, 1 - high priority",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "PROC0": {
+                    "description": "0 - low priority, 1 - high priority",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BUS_PRIORITY_ACK": {
+              "description": "Bus priority acknowledge",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "BUS_PRIORITY_ACK": {
+                    "description": "Goes to 1 once all arbiters have registered the new global priority levels.\\n\n                Arbiters update their local priority when servicing a new nonsequential access.\\n\n                In normal circumstances this will happen almost immediately.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PERFCTR0": {
+              "description": "Bus fabric performance counter 0",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PERFCTR0": {
+                    "description": "Busfabric saturating performance counter 0\\n\n                Count some event signal from the busfabric arbiters.\\n\n                Write any value to clear. Select an event to count using PERFSEL0",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "PERFSEL0": {
+              "description": "Bus fabric performance event select for PERFCTR0",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "PERFSEL0": {
+                    "description": "Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "apb_contested": {
+                            "value": 0
+                          },
+                          "apb": {
+                            "value": 1
+                          },
+                          "fastperi_contested": {
+                            "value": 2
+                          },
+                          "fastperi": {
+                            "value": 3
+                          },
+                          "sram5_contested": {
+                            "value": 4
+                          },
+                          "sram5": {
+                            "value": 5
+                          },
+                          "sram4_contested": {
+                            "value": 6
+                          },
+                          "sram4": {
+                            "value": 7
+                          },
+                          "sram3_contested": {
+                            "value": 8
+                          },
+                          "sram3": {
+                            "value": 9
+                          },
+                          "sram2_contested": {
+                            "value": 10
+                          },
+                          "sram2": {
+                            "value": 11
+                          },
+                          "sram1_contested": {
+                            "value": 12
+                          },
+                          "sram1": {
+                            "value": 13
+                          },
+                          "sram0_contested": {
+                            "value": 14
+                          },
+                          "sram0": {
+                            "value": 15
+                          },
+                          "xip_main_contested": {
+                            "value": 16
+                          },
+                          "xip_main": {
+                            "value": 17
+                          },
+                          "rom_contested": {
+                            "value": 18
+                          },
+                          "rom": {
+                            "value": 19
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PERFCTR1": {
+              "description": "Bus fabric performance counter 1",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PERFCTR1": {
+                    "description": "Busfabric saturating performance counter 1\\n\n                Count some event signal from the busfabric arbiters.\\n\n                Write any value to clear. Select an event to count using PERFSEL1",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "PERFSEL1": {
+              "description": "Bus fabric performance event select for PERFCTR1",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "PERFSEL1": {
+                    "description": "Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "apb_contested": {
+                            "value": 0
+                          },
+                          "apb": {
+                            "value": 1
+                          },
+                          "fastperi_contested": {
+                            "value": 2
+                          },
+                          "fastperi": {
+                            "value": 3
+                          },
+                          "sram5_contested": {
+                            "value": 4
+                          },
+                          "sram5": {
+                            "value": 5
+                          },
+                          "sram4_contested": {
+                            "value": 6
+                          },
+                          "sram4": {
+                            "value": 7
+                          },
+                          "sram3_contested": {
+                            "value": 8
+                          },
+                          "sram3": {
+                            "value": 9
+                          },
+                          "sram2_contested": {
+                            "value": 10
+                          },
+                          "sram2": {
+                            "value": 11
+                          },
+                          "sram1_contested": {
+                            "value": 12
+                          },
+                          "sram1": {
+                            "value": 13
+                          },
+                          "sram0_contested": {
+                            "value": 14
+                          },
+                          "sram0": {
+                            "value": 15
+                          },
+                          "xip_main_contested": {
+                            "value": 16
+                          },
+                          "xip_main": {
+                            "value": 17
+                          },
+                          "rom_contested": {
+                            "value": 18
+                          },
+                          "rom": {
+                            "value": 19
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PERFCTR2": {
+              "description": "Bus fabric performance counter 2",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PERFCTR2": {
+                    "description": "Busfabric saturating performance counter 2\\n\n                Count some event signal from the busfabric arbiters.\\n\n                Write any value to clear. Select an event to count using PERFSEL2",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "PERFSEL2": {
+              "description": "Bus fabric performance event select for PERFCTR2",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "PERFSEL2": {
+                    "description": "Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "apb_contested": {
+                            "value": 0
+                          },
+                          "apb": {
+                            "value": 1
+                          },
+                          "fastperi_contested": {
+                            "value": 2
+                          },
+                          "fastperi": {
+                            "value": 3
+                          },
+                          "sram5_contested": {
+                            "value": 4
+                          },
+                          "sram5": {
+                            "value": 5
+                          },
+                          "sram4_contested": {
+                            "value": 6
+                          },
+                          "sram4": {
+                            "value": 7
+                          },
+                          "sram3_contested": {
+                            "value": 8
+                          },
+                          "sram3": {
+                            "value": 9
+                          },
+                          "sram2_contested": {
+                            "value": 10
+                          },
+                          "sram2": {
+                            "value": 11
+                          },
+                          "sram1_contested": {
+                            "value": 12
+                          },
+                          "sram1": {
+                            "value": 13
+                          },
+                          "sram0_contested": {
+                            "value": 14
+                          },
+                          "sram0": {
+                            "value": 15
+                          },
+                          "xip_main_contested": {
+                            "value": 16
+                          },
+                          "xip_main": {
+                            "value": 17
+                          },
+                          "rom_contested": {
+                            "value": 18
+                          },
+                          "rom": {
+                            "value": 19
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PERFCTR3": {
+              "description": "Bus fabric performance counter 3",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PERFCTR3": {
+                    "description": "Busfabric saturating performance counter 3\\n\n                Count some event signal from the busfabric arbiters.\\n\n                Write any value to clear. Select an event to count using PERFSEL3",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "PERFSEL3": {
+              "description": "Bus fabric performance event select for PERFCTR3",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 31,
+              "children": {
+                "fields": {
+                  "PERFSEL3": {
+                    "description": "Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.",
+                    "offset": 0,
+                    "size": 5,
+                    "enum": {
+                      "size": 5,
+                      "children": {
+                        "enum_fields": {
+                          "apb_contested": {
+                            "value": 0
+                          },
+                          "apb": {
+                            "value": 1
+                          },
+                          "fastperi_contested": {
+                            "value": 2
+                          },
+                          "fastperi": {
+                            "value": 3
+                          },
+                          "sram5_contested": {
+                            "value": 4
+                          },
+                          "sram5": {
+                            "value": 5
+                          },
+                          "sram4_contested": {
+                            "value": 6
+                          },
+                          "sram4": {
+                            "value": 7
+                          },
+                          "sram3_contested": {
+                            "value": 8
+                          },
+                          "sram3": {
+                            "value": 9
+                          },
+                          "sram2_contested": {
+                            "value": 10
+                          },
+                          "sram2": {
+                            "value": 11
+                          },
+                          "sram1_contested": {
+                            "value": 12
+                          },
+                          "sram1": {
+                            "value": 13
+                          },
+                          "sram0_contested": {
+                            "value": 14
+                          },
+                          "sram0": {
+                            "value": 15
+                          },
+                          "xip_main_contested": {
+                            "value": 16
+                          },
+                          "xip_main": {
+                            "value": 17
+                          },
+                          "rom_contested": {
+                            "value": 18
+                          },
+                          "rom": {
+                            "value": 19
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UART0": {
+        "children": {
+          "registers": {
+            "UARTDR": {
+              "description": "Data Register, UARTDR",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "OE": {
+                    "description": "Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BE": {
+                    "description": "Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PE": {
+                    "description": "Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FE": {
+                    "description": "Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DATA": {
+                    "description": "Receive (read) data character. Transmit (write) data character.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "UARTRSR": {
+              "description": "Receive Status Register/Error Clear Register, UARTRSR/UARTECR",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "OE": {
+                    "description": "Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BE": {
+                    "description": "Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PE": {
+                    "description": "Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FE": {
+                    "description": "Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "UARTFR": {
+              "description": "Flag Register, UARTFR",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 144,
+              "children": {
+                "fields": {
+                  "RI": {
+                    "description": "Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFE": {
+                    "description": "Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFF": {
+                    "description": "Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFF": {
+                    "description": "Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFE": {
+                    "description": "Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUSY": {
+                    "description": "UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DCD": {
+                    "description": "Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DSR": {
+                    "description": "Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CTS": {
+                    "description": "Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UARTILPR": {
+              "description": "IrDA Low-Power Counter Register, UARTILPR",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ILPDVSR": {
+                    "description": "8-bit low-power divisor value. These bits are cleared to 0 at reset.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "UARTIBRD": {
+              "description": "Integer Baud Rate Register, UARTIBRD",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "BAUD_DIVINT": {
+                    "description": "The integer baud rate divisor. These bits are cleared to 0 on reset.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "UARTFBRD": {
+              "description": "Fractional Baud Rate Register, UARTFBRD",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "BAUD_DIVFRAC": {
+                    "description": "The fractional baud rate divisor. These bits are cleared to 0 on reset.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "UARTLCR_H": {
+              "description": "Line Control Register, UARTLCR_H",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SPS": {
+                    "description": "Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "WLEN": {
+                    "description": "Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "FEN": {
+                    "description": "Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "STP2": {
+                    "description": "Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EPS": {
+                    "description": "Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PEN": {
+                    "description": "Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BRK": {
+                    "description": "Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "UARTCR": {
+              "description": "Control Register, UARTCR",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 768,
+              "children": {
+                "fields": {
+                  "CTSEN": {
+                    "description": "CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RTSEN": {
+                    "description": "RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OUT2": {
+                    "description": "This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OUT1": {
+                    "description": "This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RTS": {
+                    "description": "Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DTR": {
+                    "description": "Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RXE": {
+                    "description": "Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TXE": {
+                    "description": "Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LBE": {
+                    "description": "Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SIRLP": {
+                    "description": "SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SIREN": {
+                    "description": "SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UARTEN": {
+                    "description": "UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "UARTIFLS": {
+              "description": "Interrupt FIFO Level Select Register, UARTIFLS",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 18,
+              "children": {
+                "fields": {
+                  "RXIFLSEL": {
+                    "description": "Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "TXIFLSEL": {
+                    "description": "Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved.",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "UARTIMSC": {
+              "description": "Interrupt Mask Set/Clear Register, UARTIMSC",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "OEIM": {
+                    "description": "Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BEIM": {
+                    "description": "Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PEIM": {
+                    "description": "Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FEIM": {
+                    "description": "Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RTIM": {
+                    "description": "Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXIM": {
+                    "description": "Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RXIM": {
+                    "description": "Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DSRMIM": {
+                    "description": "nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DCDMIM": {
+                    "description": "nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CTSMIM": {
+                    "description": "nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RIMIM": {
+                    "description": "nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "UARTRIS": {
+              "description": "Raw Interrupt Status Register, UARTRIS",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "OERIS": {
+                    "description": "Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BERIS": {
+                    "description": "Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PERIS": {
+                    "description": "Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FERIS": {
+                    "description": "Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTRIS": {
+                    "description": "Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXRIS": {
+                    "description": "Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXRIS": {
+                    "description": "Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DSRRMIS": {
+                    "description": "nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DCDRMIS": {
+                    "description": "nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CTSRMIS": {
+                    "description": "nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RIRMIS": {
+                    "description": "nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UARTMIS": {
+              "description": "Masked Interrupt Status Register, UARTMIS",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "OEMIS": {
+                    "description": "Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BEMIS": {
+                    "description": "Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PEMIS": {
+                    "description": "Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FEMIS": {
+                    "description": "Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTMIS": {
+                    "description": "Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXMIS": {
+                    "description": "Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXMIS": {
+                    "description": "Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DSRMMIS": {
+                    "description": "nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DCDMMIS": {
+                    "description": "nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CTSMMIS": {
+                    "description": "nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RIMMIS": {
+                    "description": "nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UARTICR": {
+              "description": "Interrupt Clear Register, UARTICR",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "OEIC": {
+                    "description": "Overrun error interrupt clear. Clears the UARTOEINTR interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BEIC": {
+                    "description": "Break error interrupt clear. Clears the UARTBEINTR interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PEIC": {
+                    "description": "Parity error interrupt clear. Clears the UARTPEINTR interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FEIC": {
+                    "description": "Framing error interrupt clear. Clears the UARTFEINTR interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RTIC": {
+                    "description": "Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TXIC": {
+                    "description": "Transmit interrupt clear. Clears the UARTTXINTR interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RXIC": {
+                    "description": "Receive interrupt clear. Clears the UARTRXINTR interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DSRMIC": {
+                    "description": "nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DCDMIC": {
+                    "description": "nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CTSMIC": {
+                    "description": "nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RIMIC": {
+                    "description": "nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "UARTDMACR": {
+              "description": "DMA Control Register, UARTDMACR",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DMAONERR": {
+                    "description": "DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TXDMAE": {
+                    "description": "Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXDMAE": {
+                    "description": "Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "UARTPERIPHID0": {
+              "description": "UARTPeriphID0 Register",
+              "offset": 4064,
+              "size": 32,
+              "reset_value": 17,
+              "children": {
+                "fields": {
+                  "PARTNUMBER0": {
+                    "description": "These bits read back as 0x11",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UARTPERIPHID1": {
+              "description": "UARTPeriphID1 Register",
+              "offset": 4068,
+              "size": 32,
+              "reset_value": 16,
+              "children": {
+                "fields": {
+                  "DESIGNER0": {
+                    "description": "These bits read back as 0x1",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "PARTNUMBER1": {
+                    "description": "These bits read back as 0x0",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UARTPERIPHID2": {
+              "description": "UARTPeriphID2 Register",
+              "offset": 4072,
+              "size": 32,
+              "reset_value": 52,
+              "children": {
+                "fields": {
+                  "REVISION": {
+                    "description": "This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "DESIGNER1": {
+                    "description": "These bits read back as 0x4",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UARTPERIPHID3": {
+              "description": "UARTPeriphID3 Register",
+              "offset": 4076,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CONFIGURATION": {
+                    "description": "These bits read back as 0x00",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UARTPCELLID0": {
+              "description": "UARTPCellID0 Register",
+              "offset": 4080,
+              "size": 32,
+              "reset_value": 13,
+              "children": {
+                "fields": {
+                  "UARTPCELLID0": {
+                    "description": "These bits read back as 0x0D",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UARTPCELLID1": {
+              "description": "UARTPCellID1 Register",
+              "offset": 4084,
+              "size": 32,
+              "reset_value": 240,
+              "children": {
+                "fields": {
+                  "UARTPCELLID1": {
+                    "description": "These bits read back as 0xF0",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UARTPCELLID2": {
+              "description": "UARTPCellID2 Register",
+              "offset": 4088,
+              "size": 32,
+              "reset_value": 5,
+              "children": {
+                "fields": {
+                  "UARTPCELLID2": {
+                    "description": "These bits read back as 0x05",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UARTPCELLID3": {
+              "description": "UARTPCellID3 Register",
+              "offset": 4092,
+              "size": 32,
+              "reset_value": 177,
+              "children": {
+                "fields": {
+                  "UARTPCELLID3": {
+                    "description": "These bits read back as 0xB1",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SIO": {
+        "description": "Single-cycle IO block\\n\n        Provides core-local and inter-core hardware for the two processors, with single-cycle access.",
+        "children": {
+          "registers": {
+            "CPUID": {
+              "description": "Processor core identifier\\n\n            Value is 0 when read from processor core 0, and 1 when read from processor core 1.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "GPIO_IN": {
+              "description": "Input value for GPIO pins",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_IN": {
+                    "description": "Input value for GPIO0...29",
+                    "offset": 0,
+                    "size": 30,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO_HI_IN": {
+              "description": "Input value for QSPI pins",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_HI_IN": {
+                    "description": "Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "GPIO_OUT": {
+              "description": "GPIO output value",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_OUT": {
+                    "description": "Set output level (1/0 -> high/low) for GPIO0...29.\\n\n                Reading back gives the last value written, NOT the input value from the pins.\\n\n                If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),\\n\n                the result is as though the write from core 0 took place first,\\n\n                and the write from core 1 was then applied to that intermediate result.",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "GPIO_OUT_SET": {
+              "description": "GPIO output value set",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_OUT_SET": {
+                    "description": "Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`",
+                    "offset": 0,
+                    "size": 30,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "GPIO_OUT_CLR": {
+              "description": "GPIO output value clear",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_OUT_CLR": {
+                    "description": "Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`",
+                    "offset": 0,
+                    "size": 30,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "GPIO_OUT_XOR": {
+              "description": "GPIO output value XOR",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_OUT_XOR": {
+                    "description": "Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`",
+                    "offset": 0,
+                    "size": 30,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "GPIO_OE": {
+              "description": "GPIO output enable",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_OE": {
+                    "description": "Set output enable (1/0 -> output/input) for GPIO0...29.\\n\n                Reading back gives the last value written.\\n\n                If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),\\n\n                the result is as though the write from core 0 took place first,\\n\n                and the write from core 1 was then applied to that intermediate result.",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "GPIO_OE_SET": {
+              "description": "GPIO output enable set",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_OE_SET": {
+                    "description": "Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`",
+                    "offset": 0,
+                    "size": 30,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "GPIO_OE_CLR": {
+              "description": "GPIO output enable clear",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_OE_CLR": {
+                    "description": "Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`",
+                    "offset": 0,
+                    "size": 30,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "GPIO_OE_XOR": {
+              "description": "GPIO output enable XOR",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_OE_XOR": {
+                    "description": "Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`",
+                    "offset": 0,
+                    "size": 30,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "GPIO_HI_OUT": {
+              "description": "QSPI output value",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_HI_OUT": {
+                    "description": "Set output level (1/0 -> high/low) for QSPI IO0...5.\\n\n                Reading back gives the last value written, NOT the input value from the pins.\\n\n                If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),\\n\n                the result is as though the write from core 0 took place first,\\n\n                and the write from core 1 was then applied to that intermediate result.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "GPIO_HI_OUT_SET": {
+              "description": "QSPI output value set",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_HI_OUT_SET": {
+                    "description": "Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "GPIO_HI_OUT_CLR": {
+              "description": "QSPI output value clear",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_HI_OUT_CLR": {
+                    "description": "Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "GPIO_HI_OUT_XOR": {
+              "description": "QSPI output value XOR",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_HI_OUT_XOR": {
+                    "description": "Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "GPIO_HI_OE": {
+              "description": "QSPI output enable",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_HI_OE": {
+                    "description": "Set output enable (1/0 -> output/input) for QSPI IO0...5.\\n\n                Reading back gives the last value written.\\n\n                If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),\\n\n                the result is as though the write from core 0 took place first,\\n\n                and the write from core 1 was then applied to that intermediate result.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "GPIO_HI_OE_SET": {
+              "description": "QSPI output enable set",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_HI_OE_SET": {
+                    "description": "Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "GPIO_HI_OE_CLR": {
+              "description": "QSPI output enable clear",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_HI_OE_CLR": {
+                    "description": "Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "GPIO_HI_OE_XOR": {
+              "description": "QSPI output enable XOR",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "GPIO_HI_OE_XOR": {
+                    "description": "Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "FIFO_ST": {
+              "description": "Status register for inter-core FIFOs (mailboxes).\\n\n            There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.\\n\n            Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).\\n\n            Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).\\n\n            The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 2,
+              "children": {
+                "fields": {
+                  "ROE": {
+                    "description": "Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "WOF": {
+                    "description": "Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RDY": {
+                    "description": "Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "VLD": {
+                    "description": "Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FIFO_WR": {
+              "description": "Write access to this core's TX FIFO",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "access": "write-only"
+            },
+            "FIFO_RD": {
+              "description": "Read access to this core's RX FIFO",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "SPINLOCK_ST": {
+              "description": "Spinlock state\\n\n            A bitmap containing the state of all 32 spinlocks (1=locked).\\n\n            Mainly intended for debugging.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "DIV_UDIVIDEND": {
+              "description": "Divider unsigned dividend\\n\n            Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\\n\n            Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\\n\n            UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an\\n\n            unsigned calculation, and the S alias starts a signed calculation.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0
+            },
+            "DIV_UDIVISOR": {
+              "description": "Divider unsigned divisor\\n\n            Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\\n\n            Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.\\n\n            UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an\\n\n            unsigned calculation, and the S alias starts a signed calculation.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0
+            },
+            "DIV_SDIVIDEND": {
+              "description": "Divider signed dividend\\n\n            The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0
+            },
+            "DIV_SDIVISOR": {
+              "description": "Divider signed divisor\\n\n            The same as UDIVISOR, but starts a signed calculation, rather than unsigned.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0
+            },
+            "DIV_QUOTIENT": {
+              "description": "Divider result quotient\\n\n            The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.\\n\n            For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.\\n\n            This register can be written to directly, for context save/restore purposes. This halts any\\n\n            in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\\n\n            Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order\\n\n            REMAINDER, QUOTIENT if CSR_DIRTY is used.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0
+            },
+            "DIV_REMAINDER": {
+              "description": "Divider result remainder\\n\n            The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.\\n\n            For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\\n\n            This register can be written to directly, for context save/restore purposes. This halts any\\n\n            in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0
+            },
+            "DIV_CSR": {
+              "description": "Control and status register for divider.",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 1,
+              "children": {
+                "fields": {
+                  "DIRTY": {
+                    "description": "Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.\\n\n                Software can use this flag to make save/restore more efficient (skip if not DIRTY).\\n\n                If the flag is used in this way, it's recommended to either read QUOTIENT only,\\n\n                or REMAINDER and then QUOTIENT, to prevent data loss on context switch.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READY": {
+                    "description": "Reads as 0 when a calculation is in progress, 1 otherwise.\\n\n                Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no\\n\n                matter if one is already in progress.\\n\n                Writing to a result register will immediately terminate any in-progress calculation\\n\n                and set the READY and DIRTY flags.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTERP0_ACCUM0": {
+              "description": "Read/write access to accumulator 0",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0
+            },
+            "INTERP0_ACCUM1": {
+              "description": "Read/write access to accumulator 1",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0
+            },
+            "INTERP0_BASE0": {
+              "description": "Read/write access to BASE0 register.",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0
+            },
+            "INTERP0_BASE1": {
+              "description": "Read/write access to BASE1 register.",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0
+            },
+            "INTERP0_BASE2": {
+              "description": "Read/write access to BASE2 register.",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0
+            },
+            "INTERP0_POP_LANE0": {
+              "description": "Read LANE0 result, and simultaneously write lane results to both accumulators (POP).",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP0_POP_LANE1": {
+              "description": "Read LANE1 result, and simultaneously write lane results to both accumulators (POP).",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP0_POP_FULL": {
+              "description": "Read FULL result, and simultaneously write lane results to both accumulators (POP).",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP0_PEEK_LANE0": {
+              "description": "Read LANE0 result, without altering any internal state (PEEK).",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP0_PEEK_LANE1": {
+              "description": "Read LANE1 result, without altering any internal state (PEEK).",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP0_PEEK_FULL": {
+              "description": "Read FULL result, without altering any internal state (PEEK).",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP0_CTRL_LANE0": {
+              "description": "Control register for lane 0",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "OVERF": {
+                    "description": "Set if either OVERF0 or OVERF1 is set.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVERF1": {
+                    "description": "Indicates if any masked-off MSBs in ACCUM1 are set.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVERF0": {
+                    "description": "Indicates if any masked-off MSBs in ACCUM0 are set.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BLEND": {
+                    "description": "Only present on INTERP0 on each core. If BLEND mode is enabled:\\n\n                - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\\n\n                by the 8 LSBs of lane 1 shift and mask value (a fractional number between\\n\n                0 and 255/256ths)\\n\n                - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)\\n\n                - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)\\n\n                LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FORCE_MSB": {
+                    "description": "ORed into bits 29:28 of the lane result presented to the processor on the bus.\\n\n                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\\n\n                of pointers into flash or SRAM.",
+                    "offset": 19,
+                    "size": 2
+                  },
+                  "ADD_RAW": {
+                    "description": "If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CROSS_RESULT": {
+                    "description": "If 1, feed the opposite lane's result into this lane's accumulator on POP.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "CROSS_INPUT": {
+                    "description": "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\\n\n                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SIGNED": {
+                    "description": "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\\n\n                before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MASK_MSB": {
+                    "description": "The most-significant bit allowed to pass by the mask (inclusive)\\n\n                Setting MSB < LSB may cause chip to turn inside-out",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "MASK_LSB": {
+                    "description": "The least-significant bit allowed to pass by the mask (inclusive)",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SHIFT": {
+                    "description": "Logical right-shift applied to accumulator before masking",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "INTERP0_CTRL_LANE1": {
+              "description": "Control register for lane 1",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FORCE_MSB": {
+                    "description": "ORed into bits 29:28 of the lane result presented to the processor on the bus.\\n\n                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\\n\n                of pointers into flash or SRAM.",
+                    "offset": 19,
+                    "size": 2
+                  },
+                  "ADD_RAW": {
+                    "description": "If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CROSS_RESULT": {
+                    "description": "If 1, feed the opposite lane's result into this lane's accumulator on POP.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "CROSS_INPUT": {
+                    "description": "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\\n\n                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SIGNED": {
+                    "description": "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\\n\n                before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MASK_MSB": {
+                    "description": "The most-significant bit allowed to pass by the mask (inclusive)\\n\n                Setting MSB < LSB may cause chip to turn inside-out",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "MASK_LSB": {
+                    "description": "The least-significant bit allowed to pass by the mask (inclusive)",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SHIFT": {
+                    "description": "Logical right-shift applied to accumulator before masking",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "INTERP0_ACCUM0_ADD": {
+              "description": "Values written here are atomically added to ACCUM0\\n\n            Reading yields lane 0's raw shift and mask value (BASE0 not added).",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTERP0_ACCUM0_ADD": {
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "INTERP0_ACCUM1_ADD": {
+              "description": "Values written here are atomically added to ACCUM1\\n\n            Reading yields lane 1's raw shift and mask value (BASE1 not added).",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTERP0_ACCUM1_ADD": {
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "INTERP0_BASE_1AND0": {
+              "description": "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\\n\n            Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "access": "write-only"
+            },
+            "INTERP1_ACCUM0": {
+              "description": "Read/write access to accumulator 0",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0
+            },
+            "INTERP1_ACCUM1": {
+              "description": "Read/write access to accumulator 1",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0
+            },
+            "INTERP1_BASE0": {
+              "description": "Read/write access to BASE0 register.",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0
+            },
+            "INTERP1_BASE1": {
+              "description": "Read/write access to BASE1 register.",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0
+            },
+            "INTERP1_BASE2": {
+              "description": "Read/write access to BASE2 register.",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0
+            },
+            "INTERP1_POP_LANE0": {
+              "description": "Read LANE0 result, and simultaneously write lane results to both accumulators (POP).",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP1_POP_LANE1": {
+              "description": "Read LANE1 result, and simultaneously write lane results to both accumulators (POP).",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP1_POP_FULL": {
+              "description": "Read FULL result, and simultaneously write lane results to both accumulators (POP).",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP1_PEEK_LANE0": {
+              "description": "Read LANE0 result, without altering any internal state (PEEK).",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP1_PEEK_LANE1": {
+              "description": "Read LANE1 result, without altering any internal state (PEEK).",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP1_PEEK_FULL": {
+              "description": "Read FULL result, without altering any internal state (PEEK).",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "INTERP1_CTRL_LANE0": {
+              "description": "Control register for lane 0",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "OVERF": {
+                    "description": "Set if either OVERF0 or OVERF1 is set.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVERF1": {
+                    "description": "Indicates if any masked-off MSBs in ACCUM1 are set.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVERF0": {
+                    "description": "Indicates if any masked-off MSBs in ACCUM0 are set.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CLAMP": {
+                    "description": "Only present on INTERP1 on each core. If CLAMP mode is enabled:\\n\n                - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\\n\n                BASE0 and an upper bound of BASE1.\\n\n                - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FORCE_MSB": {
+                    "description": "ORed into bits 29:28 of the lane result presented to the processor on the bus.\\n\n                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\\n\n                of pointers into flash or SRAM.",
+                    "offset": 19,
+                    "size": 2
+                  },
+                  "ADD_RAW": {
+                    "description": "If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CROSS_RESULT": {
+                    "description": "If 1, feed the opposite lane's result into this lane's accumulator on POP.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "CROSS_INPUT": {
+                    "description": "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\\n\n                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SIGNED": {
+                    "description": "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\\n\n                before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MASK_MSB": {
+                    "description": "The most-significant bit allowed to pass by the mask (inclusive)\\n\n                Setting MSB < LSB may cause chip to turn inside-out",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "MASK_LSB": {
+                    "description": "The least-significant bit allowed to pass by the mask (inclusive)",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SHIFT": {
+                    "description": "Logical right-shift applied to accumulator before masking",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "INTERP1_CTRL_LANE1": {
+              "description": "Control register for lane 1",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FORCE_MSB": {
+                    "description": "ORed into bits 29:28 of the lane result presented to the processor on the bus.\\n\n                No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence\\n\n                of pointers into flash or SRAM.",
+                    "offset": 19,
+                    "size": 2
+                  },
+                  "ADD_RAW": {
+                    "description": "If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CROSS_RESULT": {
+                    "description": "If 1, feed the opposite lane's result into this lane's accumulator on POP.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "CROSS_INPUT": {
+                    "description": "If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.\\n\n                Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "SIGNED": {
+                    "description": "If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits\\n\n                before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "MASK_MSB": {
+                    "description": "The most-significant bit allowed to pass by the mask (inclusive)\\n\n                Setting MSB < LSB may cause chip to turn inside-out",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "MASK_LSB": {
+                    "description": "The least-significant bit allowed to pass by the mask (inclusive)",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "SHIFT": {
+                    "description": "Logical right-shift applied to accumulator before masking",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "INTERP1_ACCUM0_ADD": {
+              "description": "Values written here are atomically added to ACCUM0\\n\n            Reading yields lane 0's raw shift and mask value (BASE0 not added).",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTERP1_ACCUM0_ADD": {
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "INTERP1_ACCUM1_ADD": {
+              "description": "Values written here are atomically added to ACCUM1\\n\n            Reading yields lane 1's raw shift and mask value (BASE1 not added).",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTERP1_ACCUM1_ADD": {
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "INTERP1_BASE_1AND0": {
+              "description": "On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\\n\n            Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "access": "write-only"
+            },
+            "SPINLOCK0": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK1": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK2": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK3": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK4": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK5": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK6": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK7": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK8": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK9": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK10": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK11": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK12": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK13": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK14": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK15": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK16": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK17": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK18": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK19": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK20": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK21": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK22": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK23": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK24": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK25": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK26": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK27": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK28": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK29": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK30": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SPINLOCK31": {
+              "description": "Reading from a spinlock address will:\\n\n            - Return 0 if lock is already locked\\n\n            - Otherwise return nonzero, and simultaneously claim the lock\\n\\n\n            Writing (any value) releases the lock.\\n\n            If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.\\n\n            The value returned on success is 0x1 << lock number.",
+              "offset": 380,
+              "size": 32,
+              "reset_value": 0
+            }
+          }
+        }
+      },
+      "SPI0": {
+        "children": {
+          "registers": {
+            "SSPCR0": {
+              "description": "Control register 0, SSPCR0 on page 3-4",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SCR": {
+                    "description": "Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "SPH": {
+                    "description": "SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SPO": {
+                    "description": "SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FRF": {
+                    "description": "Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DSS": {
+                    "description": "Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SSPCR1": {
+              "description": "Control register 1, SSPCR1 on page 3-5",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SOD": {
+                    "description": "Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MS": {
+                    "description": "Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SSE": {
+                    "description": "Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LBM": {
+                    "description": "Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SSPDR": {
+              "description": "Data register, SSPDR on page 3-6",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SSPSR": {
+              "description": "Status register, SSPSR on page 3-7",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 3,
+              "children": {
+                "fields": {
+                  "BSY": {
+                    "description": "PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RFF": {
+                    "description": "Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RNE": {
+                    "description": "Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TNF": {
+                    "description": "Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TFE": {
+                    "description": "Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SSPCPSR": {
+              "description": "Clock prescale register, SSPCPSR on page 3-8",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CPSDVSR": {
+                    "description": "Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SSPIMSC": {
+              "description": "Interrupt mask set or clear register, SSPIMSC on page 3-9",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TXIM": {
+                    "description": "Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXIM": {
+                    "description": "Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTIM": {
+                    "description": "Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RORIM": {
+                    "description": "Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SSPRIS": {
+              "description": "Raw interrupt status register, SSPRIS on page 3-10",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 8,
+              "children": {
+                "fields": {
+                  "TXRIS": {
+                    "description": "Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXRIS": {
+                    "description": "Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTRIS": {
+                    "description": "Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RORRIS": {
+                    "description": "Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SSPMIS": {
+              "description": "Masked interrupt status register, SSPMIS on page 3-11",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TXMIS": {
+                    "description": "Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXMIS": {
+                    "description": "Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTMIS": {
+                    "description": "Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RORMIS": {
+                    "description": "Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SSPICR": {
+              "description": "Interrupt clear register, SSPICR on page 3-11",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RTIC": {
+                    "description": "Clears the SSPRTINTR interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RORIC": {
+                    "description": "Clears the SSPRORINTR interrupt",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SSPDMACR": {
+              "description": "DMA control register, SSPDMACR on page 3-12",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TXDMAE": {
+                    "description": "Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXDMAE": {
+                    "description": "Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SSPPERIPHID0": {
+              "description": "Peripheral identification registers, SSPPeriphID0-3 on page 3-13",
+              "offset": 4064,
+              "size": 32,
+              "reset_value": 34,
+              "children": {
+                "fields": {
+                  "PARTNUMBER0": {
+                    "description": "These bits read back as 0x22",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SSPPERIPHID1": {
+              "description": "Peripheral identification registers, SSPPeriphID0-3 on page 3-13",
+              "offset": 4068,
+              "size": 32,
+              "reset_value": 16,
+              "children": {
+                "fields": {
+                  "DESIGNER0": {
+                    "description": "These bits read back as 0x1",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "PARTNUMBER1": {
+                    "description": "These bits read back as 0x0",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SSPPERIPHID2": {
+              "description": "Peripheral identification registers, SSPPeriphID0-3 on page 3-13",
+              "offset": 4072,
+              "size": 32,
+              "reset_value": 52,
+              "children": {
+                "fields": {
+                  "REVISION": {
+                    "description": "These bits return the peripheral revision",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "DESIGNER1": {
+                    "description": "These bits read back as 0x4",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SSPPERIPHID3": {
+              "description": "Peripheral identification registers, SSPPeriphID0-3 on page 3-13",
+              "offset": 4076,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CONFIGURATION": {
+                    "description": "These bits read back as 0x00",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SSPPCELLID0": {
+              "description": "PrimeCell identification registers, SSPPCellID0-3 on page 3-16",
+              "offset": 4080,
+              "size": 32,
+              "reset_value": 13,
+              "children": {
+                "fields": {
+                  "SSPPCELLID0": {
+                    "description": "These bits read back as 0x0D",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SSPPCELLID1": {
+              "description": "PrimeCell identification registers, SSPPCellID0-3 on page 3-16",
+              "offset": 4084,
+              "size": 32,
+              "reset_value": 240,
+              "children": {
+                "fields": {
+                  "SSPPCELLID1": {
+                    "description": "These bits read back as 0xF0",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SSPPCELLID2": {
+              "description": "PrimeCell identification registers, SSPPCellID0-3 on page 3-16",
+              "offset": 4088,
+              "size": 32,
+              "reset_value": 5,
+              "children": {
+                "fields": {
+                  "SSPPCELLID2": {
+                    "description": "These bits read back as 0x05",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SSPPCELLID3": {
+              "description": "PrimeCell identification registers, SSPPCellID0-3 on page 3-16",
+              "offset": 4092,
+              "size": 32,
+              "reset_value": 177,
+              "children": {
+                "fields": {
+                  "SSPPCELLID3": {
+                    "description": "These bits read back as 0xB1",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USBCTRL_REGS": {
+        "description": "USB FS/LS controller device registers",
+        "children": {
+          "registers": {
+            "ADDR_ENDP": {
+              "description": "Device address and endpoint control",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENDPOINT": {
+                    "description": "Device endpoint to send data to. Only valid for HOST mode.",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP1": {
+              "description": "Interrupt endpoint 1. Only valid for HOST mode.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP2": {
+              "description": "Interrupt endpoint 2. Only valid for HOST mode.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP3": {
+              "description": "Interrupt endpoint 3. Only valid for HOST mode.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP4": {
+              "description": "Interrupt endpoint 4. Only valid for HOST mode.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP5": {
+              "description": "Interrupt endpoint 5. Only valid for HOST mode.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP6": {
+              "description": "Interrupt endpoint 6. Only valid for HOST mode.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP7": {
+              "description": "Interrupt endpoint 7. Only valid for HOST mode.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP8": {
+              "description": "Interrupt endpoint 8. Only valid for HOST mode.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP9": {
+              "description": "Interrupt endpoint 9. Only valid for HOST mode.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP10": {
+              "description": "Interrupt endpoint 10. Only valid for HOST mode.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP11": {
+              "description": "Interrupt endpoint 11. Only valid for HOST mode.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP12": {
+              "description": "Interrupt endpoint 12. Only valid for HOST mode.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP13": {
+              "description": "Interrupt endpoint 13. Only valid for HOST mode.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP14": {
+              "description": "Interrupt endpoint 14. Only valid for HOST mode.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ADDR_ENDP15": {
+              "description": "Interrupt endpoint 15. Only valid for HOST mode.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTEP_PREAMBLE": {
+                    "description": "Interrupt EP requires preamble (is a low speed device on a full speed hub)",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "INTEP_DIR": {
+                    "description": "Direction of the interrupt endpoint. In=0, Out=1",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ENDPOINT": {
+                    "description": "Endpoint number of the interrupt endpoint",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "ADDRESS": {
+                    "description": "Device address",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "MAIN_CTRL": {
+              "description": "Main control register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SIM_TIMING": {
+                    "description": "Reduced timings for simulation",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "HOST_NDEVICE": {
+                    "description": "Device mode = 0, Host mode = 1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CONTROLLER_EN": {
+                    "description": "Enable controller",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SOF_WR": {
+              "description": "Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "COUNT": {
+                    "offset": 0,
+                    "size": 11,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SOF_RD": {
+              "description": "Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "COUNT": {
+                    "offset": 0,
+                    "size": 11,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SIE_CTRL": {
+              "description": "SIE control register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "EP0_INT_STALL": {
+                    "description": "Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EP0_DOUBLE_BUF": {
+                    "description": "Device: EP0 single buffered = 0, double buffered = 1",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EP0_INT_1BUF": {
+                    "description": "Device: Set bit in BUFF_STATUS for every buffer completed on EP0",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EP0_INT_2BUF": {
+                    "description": "Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EP0_INT_NAK": {
+                    "description": "Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "DIRECT_EN": {
+                    "description": "Direct bus drive enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "DIRECT_DP": {
+                    "description": "Direct control of DP",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DIRECT_DM": {
+                    "description": "Direct control of DM",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "TRANSCEIVER_PD": {
+                    "description": "Power down bus transceiver",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RPU_OPT": {
+                    "description": "Device: Pull-up strength (0=1K2, 1=2k3)",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "PULLUP_EN": {
+                    "description": "Device: Enable pull up resistor",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PULLDOWN_EN": {
+                    "description": "Host: Enable pull down resistors",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RESET_BUS": {
+                    "description": "Host: Reset bus",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESUME": {
+                    "description": "Device: Remote wakeup. Device can initiate its own resume after suspend.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "VBUS_EN": {
+                    "description": "Host: Enable VBUS",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "KEEP_ALIVE_EN": {
+                    "description": "Host: Enable keep alive packet (for low speed bus)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SOF_EN": {
+                    "description": "Host: Enable SOF generation (for full speed bus)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SOF_SYNC": {
+                    "description": "Host: Delay packet(s) until after SOF",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "PREAMBLE_EN": {
+                    "description": "Host: Preable enable for LS device on FS hub",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "STOP_TRANS": {
+                    "description": "Host: Stop transaction",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RECEIVE_DATA": {
+                    "description": "Host: Receive transaction (IN to host)",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SEND_DATA": {
+                    "description": "Host: Send transaction (OUT from host)",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SEND_SETUP": {
+                    "description": "Host: Send Setup packet",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "START_TRANS": {
+                    "description": "Host: Start transaction",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SIE_STATUS": {
+              "description": "SIE status register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DATA_SEQ_ERROR": {
+                    "description": "Data Sequence Error.\\n\\n\n                The device can raise a sequence error in the following conditions:\\n\\n\n                * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM\\n\\n\n                The host can raise a data sequence error in the following conditions:\\n\\n\n                * An IN packet from the device has the wrong data PID",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "ACK_REC": {
+                    "description": "ACK received. Raised by both host and device.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "STALL_REC": {
+                    "description": "Host: STALL received",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "NAK_REC": {
+                    "description": "Host: NAK received",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "RX_TIMEOUT": {
+                    "description": "RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "RX_OVERFLOW": {
+                    "description": "RX overflow is raised by the Serial RX engine if the incoming data is too fast.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "BIT_STUFF_ERROR": {
+                    "description": "Bit Stuff Error. Raised by the Serial RX engine.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CRC_ERROR": {
+                    "description": "CRC Error. Raised by the Serial RX engine.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BUS_RESET": {
+                    "description": "Device: bus reset received",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TRANS_COMPLETE": {
+                    "description": "Transaction complete.\\n\\n\n                Raised by device if:\\n\\n\n                * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register\\n\\n\n                Raised by host if:\\n\\n\n                * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "SETUP_REC": {
+                    "description": "Device: Setup packet received",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "CONNECTED": {
+                    "description": "Device: connected",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RESUME": {
+                    "description": "Host: Device has initiated a remote resume. Device: host has initiated a resume.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "VBUS_OVER_CURR": {
+                    "description": "VBUS over current detected",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SPEED": {
+                    "description": "Host: device speed. Disconnected = 00, LS = 01, FS = 10",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "SUSPENDED": {
+                    "description": "Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "LINE_STATE": {
+                    "description": "USB bus line state",
+                    "offset": 2,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "VBUS_DETECTED": {
+                    "description": "Device: VBUS Detected",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_EP_CTRL": {
+              "description": "interrupt endpoint control register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INT_EP_ACTIVE": {
+                    "description": "Host: Enable interrupt endpoint 1 -> 15",
+                    "offset": 1,
+                    "size": 15
+                  }
+                }
+              }
+            },
+            "BUFF_STATUS": {
+              "description": "Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "EP15_OUT": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EP15_IN": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EP14_OUT": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EP14_IN": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EP13_OUT": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EP13_IN": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EP12_OUT": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EP12_IN": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EP11_OUT": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EP11_IN": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EP10_OUT": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EP10_IN": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EP9_OUT": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EP9_IN": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EP8_OUT": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EP8_IN": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EP7_OUT": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EP7_IN": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EP6_OUT": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EP6_IN": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EP5_OUT": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EP5_IN": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EP4_OUT": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EP4_IN": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP3_OUT": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP3_IN": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EP2_OUT": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EP2_IN": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EP1_OUT": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EP1_IN": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EP0_OUT": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP0_IN": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BUFF_CPU_SHOULD_HANDLE": {
+              "description": "Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "EP15_OUT": {
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP15_IN": {
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP14_OUT": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP14_IN": {
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP13_OUT": {
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP13_IN": {
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP12_OUT": {
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP12_IN": {
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP11_OUT": {
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP11_IN": {
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP10_OUT": {
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP10_IN": {
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP9_OUT": {
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP9_IN": {
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP8_OUT": {
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP8_IN": {
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP7_OUT": {
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP7_IN": {
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP6_OUT": {
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP6_IN": {
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP5_OUT": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP5_IN": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP4_OUT": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP4_IN": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP3_OUT": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP3_IN": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP2_OUT": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP2_IN": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP1_OUT": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP1_IN": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP0_OUT": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EP0_IN": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "EP_ABORT": {
+              "description": "Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "EP15_OUT": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EP15_IN": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EP14_OUT": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EP14_IN": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EP13_OUT": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EP13_IN": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EP12_OUT": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EP12_IN": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EP11_OUT": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EP11_IN": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EP10_OUT": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EP10_IN": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EP9_OUT": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EP9_IN": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EP8_OUT": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EP8_IN": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EP7_OUT": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EP7_IN": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EP6_OUT": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EP6_IN": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EP5_OUT": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EP5_IN": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EP4_OUT": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EP4_IN": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP3_OUT": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP3_IN": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EP2_OUT": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EP2_IN": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EP1_OUT": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EP1_IN": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EP0_OUT": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP0_IN": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EP_ABORT_DONE": {
+              "description": "Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "EP15_OUT": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EP15_IN": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EP14_OUT": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EP14_IN": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EP13_OUT": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EP13_IN": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EP12_OUT": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EP12_IN": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EP11_OUT": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EP11_IN": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EP10_OUT": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EP10_IN": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EP9_OUT": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EP9_IN": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EP8_OUT": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EP8_IN": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EP7_OUT": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EP7_IN": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EP6_OUT": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EP6_IN": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EP5_OUT": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EP5_IN": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EP4_OUT": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EP4_IN": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP3_OUT": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP3_IN": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EP2_OUT": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EP2_IN": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EP1_OUT": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EP1_IN": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EP0_OUT": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP0_IN": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EP_STALL_ARM": {
+              "description": "Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "EP0_OUT": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP0_IN": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "NAK_POLL": {
+              "description": "Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 1048592,
+              "children": {
+                "fields": {
+                  "DELAY_FS": {
+                    "description": "NAK polling interval for a full speed device",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "DELAY_LS": {
+                    "description": "NAK polling interval for a low speed device",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP_STATUS_STALL_NAK": {
+              "description": "Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "EP15_OUT": {
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "EP15_IN": {
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "EP14_OUT": {
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "EP14_IN": {
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "EP13_OUT": {
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "EP13_IN": {
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "EP12_OUT": {
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "EP12_IN": {
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "EP11_OUT": {
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "EP11_IN": {
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "EP10_OUT": {
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "EP10_IN": {
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "EP9_OUT": {
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "EP9_IN": {
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "EP8_OUT": {
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EP8_IN": {
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "EP7_OUT": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "EP7_IN": {
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "EP6_OUT": {
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EP6_IN": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "EP5_OUT": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "EP5_IN": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "EP4_OUT": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "EP4_IN": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "EP3_OUT": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "EP3_IN": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "EP2_OUT": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "EP2_IN": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "EP1_OUT": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "EP1_IN": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EP0_OUT": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EP0_IN": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USB_MUXING": {
+              "description": "Where to connect the USB controller. Should be to_phy by default.",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SOFTCON": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TO_DIGITAL_PAD": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TO_EXTPHY": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TO_PHY": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USB_PWR": {
+              "description": "Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "OVERCURR_DETECT_EN": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OVERCURR_DETECT": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "VBUS_DETECT_OVERRIDE_EN": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "VBUS_DETECT": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "VBUS_EN_OVERRIDE_EN": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "VBUS_EN": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USBPHY_DIRECT": {
+              "description": "This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DM_OVV": {
+                    "description": "DM over voltage",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DP_OVV": {
+                    "description": "DP over voltage",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DM_OVCN": {
+                    "description": "DM overcurrent",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DP_OVCN": {
+                    "description": "DP overcurrent",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_DM": {
+                    "description": "DPM pin state",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_DP": {
+                    "description": "DPP pin state",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_DD": {
+                    "description": "Differential RX",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_DIFFMODE": {
+                    "description": "TX_DIFFMODE=0: Single ended mode\\n\n                TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TX_FSSLEW": {
+                    "description": "TX_FSSLEW=0: Low speed slew rate\\n\n                TX_FSSLEW=1: Full speed slew rate",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TX_PD": {
+                    "description": "TX power down override (if override enable is set). 1 = powered down.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RX_PD": {
+                    "description": "RX power down override (if override enable is set). 1 = powered down.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TX_DM": {
+                    "description": "Output data. TX_DIFFMODE=1, Ignored\\n\n                TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TX_DP": {
+                    "description": "Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP\\n\n                If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TX_DM_OE": {
+                    "description": "Output enable. If TX_DIFFMODE=1, Ignored.\\n\n                If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TX_DP_OE": {
+                    "description": "Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving\\n\n                If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DM_PULLDN_EN": {
+                    "description": "DM pull down enable",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DM_PULLUP_EN": {
+                    "description": "DM pull up enable",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DM_PULLUP_HISEL": {
+                    "description": "Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DP_PULLDN_EN": {
+                    "description": "DP pull down enable",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DP_PULLUP_EN": {
+                    "description": "DP pull up enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DP_PULLUP_HISEL": {
+                    "description": "Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USBPHY_DIRECT_OVERRIDE": {
+              "description": "Override enable for each control in usbphy_direct",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TX_DIFFMODE_OVERRIDE_EN": {
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "DM_PULLUP_OVERRIDE_EN": {
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TX_FSSLEW_OVERRIDE_EN": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TX_PD_OVERRIDE_EN": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RX_PD_OVERRIDE_EN": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TX_DM_OVERRIDE_EN": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TX_DP_OVERRIDE_EN": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TX_DM_OE_OVERRIDE_EN": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TX_DP_OE_OVERRIDE_EN": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DM_PULLDN_EN_OVERRIDE_EN": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DP_PULLDN_EN_OVERRIDE_EN": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DP_PULLUP_EN_OVERRIDE_EN": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DM_PULLUP_HISEL_OVERRIDE_EN": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DP_PULLUP_HISEL_OVERRIDE_EN": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USBPHY_TRIM": {
+              "description": "Used to adjust trim values of USB phy pull down resistors.",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 7967,
+              "children": {
+                "fields": {
+                  "DM_PULLDN_TRIM": {
+                    "description": "Value to drive to USB PHY\\n\n                DM pulldown resistor trim control\\n\n                Experimental data suggests that the reset value will work, but this register allows adjustment if required",
+                    "offset": 8,
+                    "size": 5
+                  },
+                  "DP_PULLDN_TRIM": {
+                    "description": "Value to drive to USB PHY\\n\n                DP pulldown resistor trim control\\n\n                Experimental data suggests that the reset value will work, but this register allows adjustment if required",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "INTR": {
+              "description": "Raw Interrupts",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "EP_STALL_NAK": {
+                    "description": "Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ABORT_DONE": {
+                    "description": "Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DEV_SOF": {
+                    "description": "Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SETUP_REQ": {
+                    "description": "Device. Source: SIE_STATUS.SETUP_REC",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DEV_RESUME_FROM_HOST": {
+                    "description": "Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DEV_SUSPEND": {
+                    "description": "Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DEV_CONN_DIS": {
+                    "description": "Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUS_RESET": {
+                    "description": "Source: SIE_STATUS.BUS_RESET",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "VBUS_DETECT": {
+                    "description": "Source: SIE_STATUS.VBUS_DETECTED",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STALL": {
+                    "description": "Source: SIE_STATUS.STALL_REC",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERROR_CRC": {
+                    "description": "Source: SIE_STATUS.CRC_ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERROR_BIT_STUFF": {
+                    "description": "Source: SIE_STATUS.BIT_STUFF_ERROR",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERROR_RX_OVERFLOW": {
+                    "description": "Source: SIE_STATUS.RX_OVERFLOW",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERROR_RX_TIMEOUT": {
+                    "description": "Source: SIE_STATUS.RX_TIMEOUT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERROR_DATA_SEQ": {
+                    "description": "Source: SIE_STATUS.DATA_SEQ_ERROR",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUFF_STATUS": {
+                    "description": "Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_COMPLETE": {
+                    "description": "Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HOST_SOF": {
+                    "description": "Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HOST_RESUME": {
+                    "description": "Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HOST_CONN_DIS": {
+                    "description": "Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTE": {
+              "description": "Interrupt Enable",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "EP_STALL_NAK": {
+                    "description": "Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ABORT_DONE": {
+                    "description": "Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DEV_SOF": {
+                    "description": "Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SETUP_REQ": {
+                    "description": "Device. Source: SIE_STATUS.SETUP_REC",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DEV_RESUME_FROM_HOST": {
+                    "description": "Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "DEV_SUSPEND": {
+                    "description": "Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "DEV_CONN_DIS": {
+                    "description": "Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BUS_RESET": {
+                    "description": "Source: SIE_STATUS.BUS_RESET",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "VBUS_DETECT": {
+                    "description": "Source: SIE_STATUS.VBUS_DETECTED",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Source: SIE_STATUS.STALL_REC",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ERROR_CRC": {
+                    "description": "Source: SIE_STATUS.CRC_ERROR",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ERROR_BIT_STUFF": {
+                    "description": "Source: SIE_STATUS.BIT_STUFF_ERROR",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ERROR_RX_OVERFLOW": {
+                    "description": "Source: SIE_STATUS.RX_OVERFLOW",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ERROR_RX_TIMEOUT": {
+                    "description": "Source: SIE_STATUS.RX_TIMEOUT",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ERROR_DATA_SEQ": {
+                    "description": "Source: SIE_STATUS.DATA_SEQ_ERROR",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BUFF_STATUS": {
+                    "description": "Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TRANS_COMPLETE": {
+                    "description": "Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "HOST_SOF": {
+                    "description": "Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "HOST_RESUME": {
+                    "description": "Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HOST_CONN_DIS": {
+                    "description": "Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTF": {
+              "description": "Interrupt Force",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "EP_STALL_NAK": {
+                    "description": "Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "ABORT_DONE": {
+                    "description": "Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DEV_SOF": {
+                    "description": "Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SETUP_REQ": {
+                    "description": "Device. Source: SIE_STATUS.SETUP_REC",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DEV_RESUME_FROM_HOST": {
+                    "description": "Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "DEV_SUSPEND": {
+                    "description": "Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "DEV_CONN_DIS": {
+                    "description": "Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "BUS_RESET": {
+                    "description": "Source: SIE_STATUS.BUS_RESET",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "VBUS_DETECT": {
+                    "description": "Source: SIE_STATUS.VBUS_DETECTED",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Source: SIE_STATUS.STALL_REC",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ERROR_CRC": {
+                    "description": "Source: SIE_STATUS.CRC_ERROR",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ERROR_BIT_STUFF": {
+                    "description": "Source: SIE_STATUS.BIT_STUFF_ERROR",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ERROR_RX_OVERFLOW": {
+                    "description": "Source: SIE_STATUS.RX_OVERFLOW",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ERROR_RX_TIMEOUT": {
+                    "description": "Source: SIE_STATUS.RX_TIMEOUT",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ERROR_DATA_SEQ": {
+                    "description": "Source: SIE_STATUS.DATA_SEQ_ERROR",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "BUFF_STATUS": {
+                    "description": "Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TRANS_COMPLETE": {
+                    "description": "Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "HOST_SOF": {
+                    "description": "Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "HOST_RESUME": {
+                    "description": "Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "HOST_CONN_DIS": {
+                    "description": "Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTS": {
+              "description": "Interrupt status after masking & forcing",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "EP_STALL_NAK": {
+                    "description": "Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ABORT_DONE": {
+                    "description": "Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DEV_SOF": {
+                    "description": "Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SETUP_REQ": {
+                    "description": "Device. Source: SIE_STATUS.SETUP_REC",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DEV_RESUME_FROM_HOST": {
+                    "description": "Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DEV_SUSPEND": {
+                    "description": "Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DEV_CONN_DIS": {
+                    "description": "Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUS_RESET": {
+                    "description": "Source: SIE_STATUS.BUS_RESET",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "VBUS_DETECT": {
+                    "description": "Source: SIE_STATUS.VBUS_DETECTED",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STALL": {
+                    "description": "Source: SIE_STATUS.STALL_REC",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERROR_CRC": {
+                    "description": "Source: SIE_STATUS.CRC_ERROR",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERROR_BIT_STUFF": {
+                    "description": "Source: SIE_STATUS.BIT_STUFF_ERROR",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERROR_RX_OVERFLOW": {
+                    "description": "Source: SIE_STATUS.RX_OVERFLOW",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERROR_RX_TIMEOUT": {
+                    "description": "Source: SIE_STATUS.RX_TIMEOUT",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERROR_DATA_SEQ": {
+                    "description": "Source: SIE_STATUS.DATA_SEQ_ERROR",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUFF_STATUS": {
+                    "description": "Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_COMPLETE": {
+                    "description": "Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HOST_SOF": {
+                    "description": "Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HOST_RESUME": {
+                    "description": "Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HOST_CONN_DIS": {
+                    "description": "Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2C0": {
+        "description": "DW_apb_i2c address block\\n\\n\n        List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\\n\\n\n        IC_ULTRA_FAST_MODE ................ 0x0\\n\n        IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\\n\n        IC_UFM_SCL_LOW_COUNT .............. 0x0008\\n\n        IC_UFM_SCL_HIGH_COUNT ............. 0x0006\\n\n        IC_TX_TL .......................... 0x0\\n\n        IC_TX_CMD_BLOCK ................... 0x1\\n\n        IC_HAS_DMA ........................ 0x1\\n\n        IC_HAS_ASYNC_FIFO ................. 0x0\\n\n        IC_SMBUS_ARP ...................... 0x0\\n\n        IC_FIRST_DATA_BYTE_STATUS ......... 0x1\\n\n        IC_INTR_IO ........................ 0x1\\n\n        IC_MASTER_MODE .................... 0x1\\n\n        IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\\n\n        IC_INTR_POL ....................... 0x1\\n\n        IC_OPTIONAL_SAR ................... 0x0\\n\n        IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\\n\n        IC_DEFAULT_SLAVE_ADDR ............. 0x055\\n\n        IC_DEFAULT_HS_SPKLEN .............. 0x1\\n\n        IC_FS_SCL_HIGH_COUNT .............. 0x0006\\n\n        IC_HS_SCL_LOW_COUNT ............... 0x0008\\n\n        IC_DEVICE_ID_VALUE ................ 0x0\\n\n        IC_10BITADDR_MASTER ............... 0x0\\n\n        IC_CLK_FREQ_OPTIMIZATION .......... 0x0\\n\n        IC_DEFAULT_FS_SPKLEN .............. 0x7\\n\n        IC_ADD_ENCODED_PARAMS ............. 0x0\\n\n        IC_DEFAULT_SDA_HOLD ............... 0x000001\\n\n        IC_DEFAULT_SDA_SETUP .............. 0x64\\n\n        IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\\n\n        IC_CLOCK_PERIOD ................... 100\\n\n        IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\\n\n        IC_RESTART_EN ..................... 0x1\\n\n        IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\\n\n        IC_BUS_CLEAR_FEATURE .............. 0x0\\n\n        IC_CAP_LOADING .................... 100\\n\n        IC_FS_SCL_LOW_COUNT ............... 0x000d\\n\n        APB_DATA_WIDTH .................... 32\\n\n        IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\\n\n        IC_SLV_DATA_NACK_ONLY ............. 0x1\\n\n        IC_10BITADDR_SLAVE ................ 0x0\\n\n        IC_CLK_TYPE ....................... 0x0\\n\n        IC_SMBUS_UDID_MSB ................. 0x0\\n\n        IC_SMBUS_SUSPEND_ALERT ............ 0x0\\n\n        IC_HS_SCL_HIGH_COUNT .............. 0x0006\\n\n        IC_SLV_RESTART_DET_EN ............. 0x1\\n\n        IC_SMBUS .......................... 0x0\\n\n        IC_OPTIONAL_SAR_DEFAULT ........... 0x0\\n\n        IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\\n\n        IC_USE_COUNTS ..................... 0x0\\n\n        IC_RX_BUFFER_DEPTH ................ 16\\n\n        IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\\n\n        IC_RX_FULL_HLD_BUS_EN ............. 0x1\\n\n        IC_SLAVE_DISABLE .................. 0x1\\n\n        IC_RX_TL .......................... 0x0\\n\n        IC_DEVICE_ID ...................... 0x0\\n\n        IC_HC_COUNT_VALUES ................ 0x0\\n\n        I2C_DYNAMIC_TAR_UPDATE ............ 0\\n\n        IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\\n\n        IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\\n\n        IC_HS_MASTER_CODE ................. 0x1\\n\n        IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\\n\n        IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\\n\n        IC_SS_SCL_HIGH_COUNT .............. 0x0028\\n\n        IC_SS_SCL_LOW_COUNT ............... 0x002f\\n\n        IC_MAX_SPEED_MODE ................. 0x2\\n\n        IC_STAT_FOR_CLK_STRETCH ........... 0x0\\n\n        IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\\n\n        IC_DEFAULT_UFM_SPKLEN ............. 0x1\\n\n        IC_TX_BUFFER_DEPTH ................ 16",
+        "children": {
+          "registers": {
+            "IC_CON": {
+              "description": "I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\\n\\n\n            Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 101,
+              "children": {
+                "fields": {
+                  "STOP_DET_IF_MASTER_ACTIVE": {
+                    "description": "Master issues the STOP_DET interrupt irrespective of whether master is active or not",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_FIFO_FULL_HLD_CTRL": {
+                    "description": "This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.\\n\\n\n                Reset value: 0x0.",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Overflow when RX_FIFO is full",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Hold bus when RX_FIFO is full",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TX_EMPTY_CTRL": {
+                    "description": "This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: 0x0.",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Default behaviour of TX_EMPTY interrupt",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Controlled generation of TX_EMPTY interrupt",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOP_DET_IFADDRESSED": {
+                    "description": "In slave mode: - 1'b1:  issues the STOP_DET interrupt only when it is addressed. - 1'b0:  issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0\\n\\n\n                NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "slave issues STOP_DET intr always",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "slave issues STOP_DET intr only if addressed",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IC_SLAVE_DISABLE": {
+                    "description": "This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.\\n\\n\n                If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.\\n\\n\n                NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "SLAVE_ENABLED": {
+                            "description": "Slave mode is enabled",
+                            "value": 0
+                          },
+                          "SLAVE_DISABLED": {
+                            "description": "Slave mode is disabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IC_RESTART_EN": {
+                    "description": "Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: ENABLED",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Master restart disabled",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Master restart enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IC_10BITADDR_MASTER": {
+                    "description": "Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ADDR_7BITS": {
+                            "description": "Master 7Bit addressing mode",
+                            "value": 0
+                          },
+                          "ADDR_10BITS": {
+                            "description": "Master 10Bit addressing mode",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IC_10BITADDR_SLAVE": {
+                    "description": "When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ADDR_7BITS": {
+                            "description": "Slave 7Bit addressing",
+                            "value": 0
+                          },
+                          "ADDR_10BITS": {
+                            "description": "Slave 10Bit addressing",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SPEED": {
+                    "description": "These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.\\n\\n\n                This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.\\n\\n\n                1: standard mode (100 kbit/s)\\n\\n\n                2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\\n\\n\n                3: high speed mode (3.4 Mbit/s)\\n\\n\n                Note: This field is not applicable when IC_ULTRA_FAST_MODE=1",
+                    "offset": 1,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "STANDARD": {
+                            "description": "Standard Speed mode of operation",
+                            "value": 1
+                          },
+                          "FAST": {
+                            "description": "Fast or Fast Plus mode of operation",
+                            "value": 2
+                          },
+                          "HIGH": {
+                            "description": "High Speed mode of operation",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MASTER_MODE": {
+                    "description": "This bit controls whether the DW_apb_i2c master is enabled.\\n\\n\n                NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Master mode is disabled",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Master mode is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IC_TAR": {
+              "description": "I2C Target Address Register\\n\\n\n            This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.\\n\\n\n            Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 85,
+              "children": {
+                "fields": {
+                  "SPECIAL": {
+                    "description": "This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Disables programming of GENERAL_CALL or START_BYTE transmission",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Enables programming of GENERAL_CALL or START_BYTE transmission",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "GC_OR_START": {
+                    "description": "If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "GENERAL_CALL": {
+                            "description": "GENERAL_CALL byte transmission",
+                            "value": 0
+                          },
+                          "START_BYTE": {
+                            "description": "START byte transmission",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IC_TAR": {
+                    "description": "This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.\\n\\n\n                If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "IC_SAR": {
+              "description": "I2C Slave Address Register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 85,
+              "children": {
+                "fields": {
+                  "IC_SAR": {
+                    "description": "The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.\\n\\n\n                This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\\n\\n\n                Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <> for a complete list of these reserved values.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "IC_DATA_CMD": {
+              "description": "I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.\\n\\n\n            The size of the register changes as follows:\\n\\n\n            Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FIRST_DATA_BYTE": {
+                    "description": "Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.\\n\\n\n                Reset value : 0x0\\n\\n\n                NOTE:  In case of APB_DATA_WIDTH=8,\\n\\n\n                1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.\\n\\n\n                2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).\\n\\n\n                3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "Sequential data byte received",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Non sequential data byte received",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RESTART": {
+                    "description": "This bit controls whether a RESTART is issued before the byte is sent or received.\\n\\n\n                1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\\n\\n\n                0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.\\n\\n\n                Reset value: 0x0",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Don't Issue RESTART before this command",
+                            "value": 0
+                          },
+                          "ENABLE": {
+                            "description": "Issue RESTART before this command",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOP": {
+                    "description": "This bit controls whether a STOP is issued after the byte is sent or received.\\n\\n\n                - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "Don't Issue STOP after this command",
+                            "value": 0
+                          },
+                          "ENABLE": {
+                            "description": "Issue STOP after this command",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CMD": {
+                    "description": "This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.\\n\\n\n                When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.\\n\\n\n                When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\\n\\n\n                Reset value: 0x0",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "WRITE": {
+                            "description": "Master Write Command",
+                            "value": 0
+                          },
+                          "READ": {
+                            "description": "Master Read Command",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DAT": {
+                    "description": "This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IC_SS_SCL_HCNT": {
+              "description": "Standard Speed I2C Clock SCL High Count Register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 40,
+              "children": {
+                "fields": {
+                  "IC_SS_SCL_HCNT": {
+                    "description": "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.\\n\\n\n                This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\\n\\n\n                The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.\\n\\n\n                NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IC_SS_SCL_LCNT": {
+              "description": "Standard Speed I2C Clock SCL Low Count Register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 47,
+              "children": {
+                "fields": {
+                  "IC_SS_SCL_LCNT": {
+                    "description": "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'\\n\\n\n                This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\\n\\n\n                The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IC_FS_SCL_HCNT": {
+              "description": "Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 6,
+              "children": {
+                "fields": {
+                  "IC_FS_SCL_HCNT": {
+                    "description": "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\\n\\n\n                This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\\n\\n\n                The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IC_FS_SCL_LCNT": {
+              "description": "Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 13,
+              "children": {
+                "fields": {
+                  "IC_FS_SCL_LCNT": {
+                    "description": "This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.\\n\\n\n                This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.\\n\\n\n                This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.\\n\\n\n                The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IC_INTR_STAT": {
+              "description": "I2C Interrupt Status Register\\n\\n\n            Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "R_RESTART_DET": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_RESTART_DET interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_RESTART_DET interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_GEN_CALL": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_GEN_CALL interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_GEN_CALL interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_START_DET": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_START_DET interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_START_DET interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_STOP_DET": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_STOP_DET interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_STOP_DET interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_ACTIVITY": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_ACTIVITY interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_ACTIVITY interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_RX_DONE": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_RX_DONE interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_RX_DONE interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_TX_ABRT": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_TX_ABRT interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_TX_ABRT interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_RD_REQ": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_RD_REQ interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_RD_REQ interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_TX_EMPTY": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_TX_EMPTY interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_TX_EMPTY interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_TX_OVER": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_TX_OVER interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_TX_OVER interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_RX_FULL": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_RX_FULL interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_RX_FULL interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_RX_OVER": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "R_RX_OVER interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "R_RX_OVER interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "R_RX_UNDER": {
+                    "description": "See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "RX_UNDER interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "RX_UNDER interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IC_INTR_MASK": {
+              "description": "I2C Interrupt Mask Register.\\n\\n\n            These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 2303,
+              "children": {
+                "fields": {
+                  "M_RESTART_DET": {
+                    "description": "This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 12,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "RESTART_DET interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "RESTART_DET interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_GEN_CALL": {
+                    "description": "This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x1",
+                    "offset": 11,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "GEN_CALL interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "GEN_CALL interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_START_DET": {
+                    "description": "This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 10,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "START_DET interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "START_DET interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_STOP_DET": {
+                    "description": "This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 9,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "STOP_DET interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "STOP_DET interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_ACTIVITY": {
+                    "description": "This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 8,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "ACTIVITY interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "ACTIVITY interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_RX_DONE": {
+                    "description": "This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x1",
+                    "offset": 7,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "RX_DONE interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "RX_DONE interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_TX_ABRT": {
+                    "description": "This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x1",
+                    "offset": 6,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "TX_ABORT interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "TX_ABORT interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_RD_REQ": {
+                    "description": "This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x1",
+                    "offset": 5,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "RD_REQ interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "RD_REQ interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_TX_EMPTY": {
+                    "description": "This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x1",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "TX_EMPTY interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "TX_EMPTY interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_TX_OVER": {
+                    "description": "This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x1",
+                    "offset": 3,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "TX_OVER interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "TX_OVER interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_RX_FULL": {
+                    "description": "This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x1",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "RX_FULL interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "RX_FULL interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_RX_OVER": {
+                    "description": "This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x1",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "RX_OVER interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "RX_OVER interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "M_RX_UNDER": {
+                    "description": "This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\\n\\n\n                Reset value: 0x1",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ENABLED": {
+                            "description": "RX_UNDER interrupt is masked",
+                            "value": 0
+                          },
+                          "DISABLED": {
+                            "description": "RX_UNDER interrupt is unmasked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IC_RAW_INTR_STAT": {
+              "description": "I2C Raw Interrupt Status Register\\n\\n\n            Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RESTART_DET": {
+                    "description": "Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.\\n\\n\n                Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.\\n\\n\n                Reset value: 0x0",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "RESTART_DET interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "RESTART_DET interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "GEN_CALL": {
+                    "description": "Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.\\n\\n\n                Reset value: 0x0",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "GEN_CALL interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "GEN_CALL interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "START_DET": {
+                    "description": "Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\\n\\n\n                Reset value: 0x0",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "START_DET interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "START_DET interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STOP_DET": {
+                    "description": "Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.\\n\\n\n                In Slave Mode: - If IC_CON[7]=1'b1  (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1  (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0  (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "STOP_DET interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "STOP_DET interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ACTIVITY": {
+                    "description": "This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.\\n\\n\n                Reset value: 0x0",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "RAW_INTR_ACTIVITY interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "RAW_INTR_ACTIVITY interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RX_DONE": {
+                    "description": "When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.\\n\\n\n                Reset value: 0x0",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "RX_DONE interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "RX_DONE interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TX_ABRT": {
+                    "description": "This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.\\n\\n\n                Note:  The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.\\n\\n\n                Reset value: 0x0",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "TX_ABRT interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "TX_ABRT interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RD_REQ": {
+                    "description": "This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "RD_REQ interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "RD_REQ interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TX_EMPTY": {
+                    "description": "The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.\\n\\n\n                Reset value: 0x0.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "TX_EMPTY interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "TX_EMPTY interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TX_OVER": {
+                    "description": "Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\\n\\n\n                Reset value: 0x0",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "TX_OVER interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "TX_OVER interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RX_FULL": {
+                    "description": "Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.\\n\\n\n                Reset value: 0x0",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "RX_FULL interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "RX_FULL interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RX_OVER": {
+                    "description": "Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\\n\\n\n                Note:  If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.\\n\\n\n                Reset value: 0x0",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "RX_OVER interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "RX_OVER interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RX_UNDER": {
+                    "description": "Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "RX_UNDER interrupt is inactive",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "RX_UNDER interrupt is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IC_RX_TL": {
+              "description": "I2C Receive FIFO Threshold Register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RX_TL": {
+                    "description": "Receive FIFO Threshold Level.\\n\\n\n                Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IC_TX_TL": {
+              "description": "I2C Transmit FIFO Threshold Register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TX_TL": {
+                    "description": "Transmit FIFO Threshold Level.\\n\\n\n                Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IC_CLR_INTR": {
+              "description": "Clear Combined and Individual Interrupt Register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_INTR": {
+                    "description": "Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_CLR_RX_UNDER": {
+              "description": "Clear RX_UNDER Interrupt Register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_RX_UNDER": {
+                    "description": "Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_CLR_RX_OVER": {
+              "description": "Clear RX_OVER Interrupt Register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_RX_OVER": {
+                    "description": "Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_CLR_TX_OVER": {
+              "description": "Clear TX_OVER Interrupt Register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_TX_OVER": {
+                    "description": "Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_CLR_RD_REQ": {
+              "description": "Clear RD_REQ Interrupt Register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_RD_REQ": {
+                    "description": "Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_CLR_TX_ABRT": {
+              "description": "Clear TX_ABRT Interrupt Register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_TX_ABRT": {
+                    "description": "Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_CLR_RX_DONE": {
+              "description": "Clear RX_DONE Interrupt Register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_RX_DONE": {
+                    "description": "Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_CLR_ACTIVITY": {
+              "description": "Clear ACTIVITY Interrupt Register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_ACTIVITY": {
+                    "description": "Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_CLR_STOP_DET": {
+              "description": "Clear STOP_DET Interrupt Register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_STOP_DET": {
+                    "description": "Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_CLR_START_DET": {
+              "description": "Clear START_DET Interrupt Register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_START_DET": {
+                    "description": "Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_CLR_GEN_CALL": {
+              "description": "Clear GEN_CALL Interrupt Register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_GEN_CALL": {
+                    "description": "Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_ENABLE": {
+              "description": "I2C Enable Register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TX_CMD_BLOCK": {
+                    "description": "In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value:  IC_TX_CMD_BLOCK_DEFAULT",
+                    "offset": 2,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NOT_BLOCKED": {
+                            "description": "Tx Command execution not blocked",
+                            "value": 0
+                          },
+                          "BLOCKED": {
+                            "description": "Tx Command execution blocked",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABORT": {
+                    "description": "When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.\\n\\n\n                For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.\\n\\n\n                Reset value: 0x0",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "description": "ABORT operation not in progress",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "ABORT operation in progress",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ENABLE": {
+                    "description": "Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.\\n\\n\n                When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.\\n\\n\n                In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "I2C is disabled",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "I2C is enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IC_STATUS": {
+              "description": "I2C Status Register\\n\\n\n            This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.\\n\\n\n            When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 6,
+              "children": {
+                "fields": {
+                  "SLV_ACTIVITY": {
+                    "description": "Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "IDLE": {
+                            "description": "Slave is idle",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Slave not idle",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "MST_ACTIVITY": {
+                    "description": "Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\\n\\n\n                Reset value: 0x0",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "IDLE": {
+                            "description": "Master is idle",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Master not idle",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RFF": {
+                    "description": "Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NOT_FULL": {
+                            "description": "Rx FIFO not full",
+                            "value": 0
+                          },
+                          "FULL": {
+                            "description": "Rx FIFO is full",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RFNE": {
+                    "description": "Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "EMPTY": {
+                            "description": "Rx FIFO is empty",
+                            "value": 0
+                          },
+                          "NOT_EMPTY": {
+                            "description": "Rx FIFO not empty",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TFE": {
+                    "description": "Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "NON_EMPTY": {
+                            "description": "Tx FIFO not empty",
+                            "value": 0
+                          },
+                          "EMPTY": {
+                            "description": "Tx FIFO is empty",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "TFNF": {
+                    "description": "Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "FULL": {
+                            "description": "Tx FIFO is full",
+                            "value": 0
+                          },
+                          "NOT_FULL": {
+                            "description": "Tx FIFO not full",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ACTIVITY": {
+                    "description": "I2C Activity Status. Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "I2C is idle",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "I2C is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IC_TXFLR": {
+              "description": "I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TXFLR": {
+                    "description": "Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_RXFLR": {
+              "description": "I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RXFLR": {
+                    "description": "Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_SDA_HOLD": {
+              "description": "I2C SDA Hold Time Length Register\\n\\n\n            The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).\\n\\n\n            The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.\\n\\n\n            Writes to this register succeed only when IC_ENABLE[0]=0.\\n\\n\n            The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.\\n\\n\n            The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 1,
+              "children": {
+                "fields": {
+                  "IC_SDA_RX_HOLD": {
+                    "description": "Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.\\n\\n\n                Reset value: IC_DEFAULT_SDA_HOLD[23:16].",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "IC_SDA_TX_HOLD": {
+                    "description": "Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.\\n\\n\n                Reset value: IC_DEFAULT_SDA_HOLD[15:0].",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "IC_TX_ABRT_SOURCE": {
+              "description": "I2C Transmit Abort Source Register\\n\\n\n            This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).\\n\\n\n            Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TX_FLUSH_CNT": {
+                    "description": "This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter",
+                    "offset": 23,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "ABRT_USER_ABRT": {
+                    "description": "This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Transmitter",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_USER_ABRT_VOID": {
+                            "description": "Transfer abort detected by master- scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_USER_ABRT_GENERATED": {
+                            "description": "Transfer abort detected by master",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_SLVRD_INTX": {
+                    "description": "1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Slave-Transmitter",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_SLVRD_INTX_VOID": {
+                            "description": "Slave trying to transmit to remote master in read mode- scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_SLVRD_INTX_GENERATED": {
+                            "description": "Slave trying to transmit to remote master in read mode",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_SLV_ARBLOST": {
+                    "description": "This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note:  Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Slave-Transmitter",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_SLV_ARBLOST_VOID": {
+                            "description": "Slave lost arbitration to remote master- scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_SLV_ARBLOST_GENERATED": {
+                            "description": "Slave lost arbitration to remote master",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_SLVFLUSH_TXFIFO": {
+                    "description": "This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Slave-Transmitter",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_SLVFLUSH_TXFIFO_VOID": {
+                            "description": "Slave flushes existing data in TX-FIFO upon getting read command- scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_SLVFLUSH_TXFIFO_GENERATED": {
+                            "description": "Slave flushes existing data in TX-FIFO upon getting read command",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ARB_LOST": {
+                    "description": "This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Transmitter or Slave-Transmitter",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_LOST_VOID": {
+                            "description": "Master or Slave-Transmitter lost arbitration- scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_LOST_GENERATED": {
+                            "description": "Master or Slave-Transmitter lost arbitration",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_MASTER_DIS": {
+                    "description": "This field indicates that the User tries to initiate a Master operation with the Master mode disabled.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_MASTER_DIS_VOID": {
+                            "description": "User initiating master operation when MASTER disabled- scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_MASTER_DIS_GENERATED": {
+                            "description": "User initiating master operation when MASTER disabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_10B_RD_NORSTRT": {
+                    "description": "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Receiver",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_10B_RD_VOID": {
+                            "description": "Master not trying to read in 10Bit addressing mode when RESTART disabled",
+                            "value": 0
+                          },
+                          "ABRT_10B_RD_GENERATED": {
+                            "description": "Master trying to read in 10Bit addressing mode when RESTART disabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_SBYTE_NORSTRT": {
+                    "description": "To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_SBYTE_NORSTRT_VOID": {
+                            "description": "User trying to send START byte when RESTART disabled- scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_SBYTE_NORSTRT_GENERATED": {
+                            "description": "User trying to send START byte when RESTART disabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_HS_NORSTRT": {
+                    "description": "This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_HS_NORSTRT_VOID": {
+                            "description": "User trying to switch Master to HS mode when RESTART disabled- scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_HS_NORSTRT_GENERATED": {
+                            "description": "User trying to switch Master to HS mode when RESTART disabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_SBYTE_ACKDET": {
+                    "description": "This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_SBYTE_ACKDET_VOID": {
+                            "description": "ACK detected for START byte- scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_SBYTE_ACKDET_GENERATED": {
+                            "description": "ACK detected for START byte",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_HS_ACKDET": {
+                    "description": "This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_HS_ACK_VOID": {
+                            "description": "HS Master code ACKed in HS Mode- scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_HS_ACK_GENERATED": {
+                            "description": "HS Master code ACKed in HS Mode",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_GCALL_READ": {
+                    "description": "This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Transmitter",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_GCALL_READ_VOID": {
+                            "description": "GCALL is followed by read from bus-scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_GCALL_READ_GENERATED": {
+                            "description": "GCALL is followed by read from bus",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_GCALL_NOACK": {
+                    "description": "This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Transmitter",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_GCALL_NOACK_VOID": {
+                            "description": "GCALL not ACKed by any slave-scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_GCALL_NOACK_GENERATED": {
+                            "description": "GCALL not ACKed by any slave",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_TXDATA_NOACK": {
+                    "description": "This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Transmitter",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "ABRT_TXDATA_NOACK_VOID": {
+                            "description": "Transmitted data non-ACKed by addressed slave-scenario not present",
+                            "value": 0
+                          },
+                          "ABRT_TXDATA_NOACK_GENERATED": {
+                            "description": "Transmitted data not ACKed by addressed slave",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_10ADDR2_NOACK": {
+                    "description": "This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "This abort is not generated",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Byte 2 of 10Bit Address not ACKed by any slave",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_10ADDR1_NOACK": {
+                    "description": "This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "This abort is not generated",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Byte 1 of 10Bit Address not ACKed by any slave",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "ABRT_7B_ADDR_NOACK": {
+                    "description": "This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.\\n\\n\n                Reset value: 0x0\\n\\n\n                Role of DW_apb_i2c:  Master-Transmitter or Master-Receiver",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "This abort is not generated",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "This abort is generated because of NOACK for 7-bit address",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IC_SLV_DATA_NACK_ONLY": {
+              "description": "Generate Slave Data NACK Register\\n\\n\n            The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.\\n\\n\n            A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "NACK": {
+                    "description": "Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.\\n\\n\n                When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Slave receiver generates NACK normally",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Slave receiver generates NACK upon data reception only",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IC_DMA_CR": {
+              "description": "DMA Control Register\\n\\n\n            The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TDMAE": {
+                    "description": "Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0",
+                    "offset": 1,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "transmit FIFO DMA channel disabled",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Transmit FIFO DMA channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "RDMAE": {
+                    "description": "Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Receive FIFO DMA channel disabled",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Receive FIFO DMA channel enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IC_DMA_TDLR": {
+              "description": "DMA Transmit Data Level Register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DMATDL": {
+                    "description": "Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "IC_DMA_RDLR": {
+              "description": "I2C Receive Data Level Register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DMARDL": {
+                    "description": "Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "IC_SDA_SETUP": {
+              "description": "I2C SDA Setup Register\\n\\n\n            This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.\\n\\n\n            Writes to this register succeed only when IC_ENABLE[0] = 0.\\n\\n\n            Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 100,
+              "children": {
+                "fields": {
+                  "SDA_SETUP": {
+                    "description": "SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IC_ACK_GENERAL_CALL": {
+              "description": "I2C ACK General Call Register\\n\\n\n            The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.\\n\\n\n            This register is applicable only when the DW_apb_i2c is in slave mode.",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 1,
+              "children": {
+                "fields": {
+                  "ACK_GEN_CALL": {
+                    "description": "ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).",
+                    "offset": 0,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "Generate NACK for a General Call",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "Generate ACK for a General Call",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IC_ENABLE_STATUS": {
+              "description": "I2C Enable Status Register\\n\\n\n            The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.\\n\\n\n            If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.\\n\\n\n            If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.\\n\\n\n            Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SLV_RX_DATA_LOST": {
+                    "description": "Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.\\n\\n\n                Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.\\n\\n\n                When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.\\n\\n\n                Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\\n\\n\n                Reset value: 0x0",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "Slave RX Data is not lost",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Slave RX Data is lost",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "SLV_DISABLED_WHILE_BUSY": {
+                    "description": "Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:\\n\\n\n                (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;\\n\\n\n                OR,\\n\\n\n                (b) address and data bytes of the Slave-Receiver operation from a remote master.\\n\\n\n                When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.\\n\\n\n                Note:  If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.\\n\\n\n                When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.\\n\\n\n                Note:  The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\\n\\n\n                Reset value: 0x0",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "INACTIVE": {
+                            "description": "Slave is disabled when it is idle",
+                            "value": 0
+                          },
+                          "ACTIVE": {
+                            "description": "Slave is disabled when it is active",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "IC_EN": {
+                    "description": "ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note:  The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only",
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLED": {
+                            "description": "I2C disabled",
+                            "value": 0
+                          },
+                          "ENABLED": {
+                            "description": "I2C enabled",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "IC_FS_SPKLEN": {
+              "description": "I2C SS, FS or FM+ spike suppression limit\\n\\n\n            This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 7,
+              "children": {
+                "fields": {
+                  "IC_FS_SPKLEN": {
+                    "description": "This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IC_CLR_RESTART_DET": {
+              "description": "Clear RESTART_DET Interrupt Register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLR_RESTART_DET": {
+                    "description": "Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.\\n\\n\n                Reset value: 0x0",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_COMP_PARAM_1": {
+              "description": "Component Parameter Register 1\\n\\n\n            Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TX_BUFFER_DEPTH": {
+                    "description": "TX Buffer Depth = 16",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "RX_BUFFER_DEPTH": {
+                    "description": "RX Buffer Depth = 16",
+                    "offset": 8,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "ADD_ENCODED_PARAMS": {
+                    "description": "Encoded parameters not visible",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HAS_DMA": {
+                    "description": "DMA handshaking signals are enabled",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INTR_IO": {
+                    "description": "COMBINED Interrupt outputs",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HC_COUNT_VALUES": {
+                    "description": "Programmable count values for each mode.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MAX_SPEED_MODE": {
+                    "description": "MAX SPEED MODE = FAST MODE",
+                    "offset": 2,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "APB_DATA_WIDTH": {
+                    "description": "APB data bus width is 32 bits",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_COMP_VERSION": {
+              "description": "I2C Component Version Register",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 842019114,
+              "children": {
+                "fields": {
+                  "IC_COMP_VERSION": {
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IC_COMP_TYPE": {
+              "description": "I2C Component Type Register",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 1146552640,
+              "children": {
+                "fields": {
+                  "IC_COMP_TYPE": {
+                    "description": "Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PIO0": {
+        "description": "Programmable IO block",
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "PIO control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLKDIV_RESTART": {
+                    "description": "Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.\\n\\n\n                Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.\\n\\n\n                Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "SM_RESTART": {
+                    "description": "Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.\\n\\n\n                Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "SM_ENABLE": {
+                    "description": "Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "FSTAT": {
+              "description": "FIFO status register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 251662080,
+              "children": {
+                "fields": {
+                  "TXEMPTY": {
+                    "description": "State machine TX FIFO is empty",
+                    "offset": 24,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "TXFULL": {
+                    "description": "State machine TX FIFO is full",
+                    "offset": 16,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "RXEMPTY": {
+                    "description": "State machine RX FIFO is empty",
+                    "offset": 8,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "RXFULL": {
+                    "description": "State machine RX FIFO is full",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FDEBUG": {
+              "description": "FIFO debug register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "TXSTALL": {
+                    "description": "State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "TXOVER": {
+                    "description": "TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "RXUNDER": {
+                    "description": "RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "RXSTALL": {
+                    "description": "State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "FLEVEL": {
+              "description": "FIFO levels",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RX3": {
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "TX3": {
+                    "offset": 24,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "RX2": {
+                    "offset": 20,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "TX2": {
+                    "offset": 16,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "RX1": {
+                    "offset": 12,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "TX1": {
+                    "offset": 8,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "RX0": {
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "TX0": {
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TXF0": {
+              "description": "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "access": "write-only"
+            },
+            "TXF1": {
+              "description": "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "access": "write-only"
+            },
+            "TXF2": {
+              "description": "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "access": "write-only"
+            },
+            "TXF3": {
+              "description": "Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "access": "write-only"
+            },
+            "RXF0": {
+              "description": "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "RXF1": {
+              "description": "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "RXF2": {
+              "description": "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "RXF3": {
+              "description": "Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "IRQ": {
+              "description": "State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.\\n\\n\n            Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQ": {
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IRQ_FORCE": {
+              "description": "Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IRQ_FORCE": {
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INPUT_SYNC_BYPASS": {
+              "description": "There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.\\n\n            0 -> input is synchronized (default)\\n\n            1 -> synchronizer is bypassed\\n\n            If in doubt, leave this register as all zeroes.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0
+            },
+            "DBG_PADOUT": {
+              "description": "Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "DBG_PADOE": {
+              "description": "Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "DBG_CFGINFO": {
+              "description": "The PIO hardware has some free parameters that may vary between chip products.\\n\n            These should be provided in the chip datasheet, but are also exposed here.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "IMEM_SIZE": {
+                    "description": "The size of the instruction memory, measured in units of one instruction",
+                    "offset": 16,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "SM_COUNT": {
+                    "description": "The number of state machines this PIO instance is equipped with.",
+                    "offset": 8,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "FIFO_DEPTH": {
+                    "description": "The depth of the state machine TX/RX FIFOs, measured in words.\\n\n                Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\\n\n                this depth.",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM0": {
+              "description": "Write-only access to instruction memory location 0",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM0": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM1": {
+              "description": "Write-only access to instruction memory location 1",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM1": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM2": {
+              "description": "Write-only access to instruction memory location 2",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM2": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM3": {
+              "description": "Write-only access to instruction memory location 3",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM3": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM4": {
+              "description": "Write-only access to instruction memory location 4",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM4": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM5": {
+              "description": "Write-only access to instruction memory location 5",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM5": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM6": {
+              "description": "Write-only access to instruction memory location 6",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM6": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM7": {
+              "description": "Write-only access to instruction memory location 7",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM7": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM8": {
+              "description": "Write-only access to instruction memory location 8",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM8": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM9": {
+              "description": "Write-only access to instruction memory location 9",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM9": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM10": {
+              "description": "Write-only access to instruction memory location 10",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM10": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM11": {
+              "description": "Write-only access to instruction memory location 11",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM11": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM12": {
+              "description": "Write-only access to instruction memory location 12",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM12": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM13": {
+              "description": "Write-only access to instruction memory location 13",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM13": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM14": {
+              "description": "Write-only access to instruction memory location 14",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM14": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM15": {
+              "description": "Write-only access to instruction memory location 15",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM15": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM16": {
+              "description": "Write-only access to instruction memory location 16",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM16": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM17": {
+              "description": "Write-only access to instruction memory location 17",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM17": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM18": {
+              "description": "Write-only access to instruction memory location 18",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM18": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM19": {
+              "description": "Write-only access to instruction memory location 19",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM19": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM20": {
+              "description": "Write-only access to instruction memory location 20",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM20": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM21": {
+              "description": "Write-only access to instruction memory location 21",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM21": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM22": {
+              "description": "Write-only access to instruction memory location 22",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM22": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM23": {
+              "description": "Write-only access to instruction memory location 23",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM23": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM24": {
+              "description": "Write-only access to instruction memory location 24",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM24": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM25": {
+              "description": "Write-only access to instruction memory location 25",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM25": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM26": {
+              "description": "Write-only access to instruction memory location 26",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM26": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM27": {
+              "description": "Write-only access to instruction memory location 27",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM27": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM28": {
+              "description": "Write-only access to instruction memory location 28",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM28": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM29": {
+              "description": "Write-only access to instruction memory location 29",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM29": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM30": {
+              "description": "Write-only access to instruction memory location 30",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM30": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INSTR_MEM31": {
+              "description": "Write-only access to instruction memory location 31",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INSTR_MEM31": {
+                    "offset": 0,
+                    "size": 16,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SM0_CLKDIV": {
+              "description": "Clock divisor register for state machine 0\\n\n            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 65536,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Effective frequency is sysclk/(int + frac/256).\\n\n                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FRAC": {
+                    "description": "Fractional part of clock divisor",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SM0_EXECCTRL": {
+              "description": "Execution/behavioural settings for state machine 0",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 126976,
+              "children": {
+                "fields": {
+                  "EXEC_STALLED": {
+                    "description": "If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SIDE_EN": {
+                    "description": "If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SIDE_PINDIR": {
+                    "description": "If 1, side-set data is asserted to pin directions, instead of pin values",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "JMP_PIN": {
+                    "description": "The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "OUT_EN_SEL": {
+                    "description": "Which data bit to use for inline OUT enable",
+                    "offset": 19,
+                    "size": 5
+                  },
+                  "INLINE_OUT_EN": {
+                    "description": "If 1, use a bit of OUT data as an auxiliary write enable\\n\n                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\\n\n                deassert the latest pin write. This can create useful masking/override behaviour\\n\n                due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OUT_STICKY": {
+                    "description": "Continuously assert the most recent OUT/SET to the pins",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WRAP_TOP": {
+                    "description": "After reaching this address, execution is wrapped to wrap_bottom.\\n\n                If the instruction is a jump, and the jump condition is true, the jump takes priority.",
+                    "offset": 12,
+                    "size": 5
+                  },
+                  "WRAP_BOTTOM": {
+                    "description": "After reaching wrap_top, execution is wrapped to this address.",
+                    "offset": 7,
+                    "size": 5
+                  },
+                  "STATUS_SEL": {
+                    "description": "Comparison used for the MOV x, STATUS instruction.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TXLEVEL": {
+                            "description": "All-ones if TX FIFO level < N, otherwise all-zeroes",
+                            "value": 0
+                          },
+                          "RXLEVEL": {
+                            "description": "All-ones if RX FIFO level < N, otherwise all-zeroes",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STATUS_N": {
+                    "description": "Comparison level for the MOV x, STATUS instruction",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SM0_SHIFTCTRL": {
+              "description": "Control behaviour of the input/output shift registers for state machine 0",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 786432,
+              "children": {
+                "fields": {
+                  "FJOIN_RX": {
+                    "description": "When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\\n\n                TX FIFO is disabled as a result (always reads as both full and empty).\\n\n                FIFOs are flushed when this bit is changed.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "FJOIN_TX": {
+                    "description": "When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\\n\n                RX FIFO is disabled as a result (always reads as both full and empty).\\n\n                FIFOs are flushed when this bit is changed.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PULL_THRESH": {
+                    "description": "Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\\n\n                Write 0 for value of 32.",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "PUSH_THRESH": {
+                    "description": "Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\\n\n                Write 0 for value of 32.",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "OUT_SHIFTDIR": {
+                    "description": "1 = shift out of output shift register to right. 0 = to left.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IN_SHIFTDIR": {
+                    "description": "1 = shift input shift register to right (data enters from left). 0 = to left.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "AUTOPULL": {
+                    "description": "Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "AUTOPUSH": {
+                    "description": "Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SM0_ADDR": {
+              "description": "Current instruction address of state machine 0",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM0_ADDR": {
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SM0_INSTR": {
+              "description": "Read to see the instruction currently addressed by state machine 0's program counter\\n\n            Write to execute an instruction immediately (including jumps) and then resume execution.",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM0_INSTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SM0_PINCTRL": {
+              "description": "State machine pin control",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 335544320,
+              "children": {
+                "fields": {
+                  "SIDESET_COUNT": {
+                    "description": "The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).",
+                    "offset": 29,
+                    "size": 3
+                  },
+                  "SET_COUNT": {
+                    "description": "The number of pins asserted by a SET. In the range 0 to 5 inclusive.",
+                    "offset": 26,
+                    "size": 3
+                  },
+                  "OUT_COUNT": {
+                    "description": "The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.",
+                    "offset": 20,
+                    "size": 6
+                  },
+                  "IN_BASE": {
+                    "description": "The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SIDESET_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SET_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "OUT_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SM1_CLKDIV": {
+              "description": "Clock divisor register for state machine 1\\n\n            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 65536,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Effective frequency is sysclk/(int + frac/256).\\n\n                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FRAC": {
+                    "description": "Fractional part of clock divisor",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SM1_EXECCTRL": {
+              "description": "Execution/behavioural settings for state machine 1",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 126976,
+              "children": {
+                "fields": {
+                  "EXEC_STALLED": {
+                    "description": "If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SIDE_EN": {
+                    "description": "If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SIDE_PINDIR": {
+                    "description": "If 1, side-set data is asserted to pin directions, instead of pin values",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "JMP_PIN": {
+                    "description": "The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "OUT_EN_SEL": {
+                    "description": "Which data bit to use for inline OUT enable",
+                    "offset": 19,
+                    "size": 5
+                  },
+                  "INLINE_OUT_EN": {
+                    "description": "If 1, use a bit of OUT data as an auxiliary write enable\\n\n                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\\n\n                deassert the latest pin write. This can create useful masking/override behaviour\\n\n                due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OUT_STICKY": {
+                    "description": "Continuously assert the most recent OUT/SET to the pins",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WRAP_TOP": {
+                    "description": "After reaching this address, execution is wrapped to wrap_bottom.\\n\n                If the instruction is a jump, and the jump condition is true, the jump takes priority.",
+                    "offset": 12,
+                    "size": 5
+                  },
+                  "WRAP_BOTTOM": {
+                    "description": "After reaching wrap_top, execution is wrapped to this address.",
+                    "offset": 7,
+                    "size": 5
+                  },
+                  "STATUS_SEL": {
+                    "description": "Comparison used for the MOV x, STATUS instruction.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TXLEVEL": {
+                            "description": "All-ones if TX FIFO level < N, otherwise all-zeroes",
+                            "value": 0
+                          },
+                          "RXLEVEL": {
+                            "description": "All-ones if RX FIFO level < N, otherwise all-zeroes",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STATUS_N": {
+                    "description": "Comparison level for the MOV x, STATUS instruction",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SM1_SHIFTCTRL": {
+              "description": "Control behaviour of the input/output shift registers for state machine 1",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 786432,
+              "children": {
+                "fields": {
+                  "FJOIN_RX": {
+                    "description": "When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\\n\n                TX FIFO is disabled as a result (always reads as both full and empty).\\n\n                FIFOs are flushed when this bit is changed.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "FJOIN_TX": {
+                    "description": "When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\\n\n                RX FIFO is disabled as a result (always reads as both full and empty).\\n\n                FIFOs are flushed when this bit is changed.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PULL_THRESH": {
+                    "description": "Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\\n\n                Write 0 for value of 32.",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "PUSH_THRESH": {
+                    "description": "Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\\n\n                Write 0 for value of 32.",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "OUT_SHIFTDIR": {
+                    "description": "1 = shift out of output shift register to right. 0 = to left.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IN_SHIFTDIR": {
+                    "description": "1 = shift input shift register to right (data enters from left). 0 = to left.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "AUTOPULL": {
+                    "description": "Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "AUTOPUSH": {
+                    "description": "Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SM1_ADDR": {
+              "description": "Current instruction address of state machine 1",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM1_ADDR": {
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SM1_INSTR": {
+              "description": "Read to see the instruction currently addressed by state machine 1's program counter\\n\n            Write to execute an instruction immediately (including jumps) and then resume execution.",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM1_INSTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SM1_PINCTRL": {
+              "description": "State machine pin control",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 335544320,
+              "children": {
+                "fields": {
+                  "SIDESET_COUNT": {
+                    "description": "The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).",
+                    "offset": 29,
+                    "size": 3
+                  },
+                  "SET_COUNT": {
+                    "description": "The number of pins asserted by a SET. In the range 0 to 5 inclusive.",
+                    "offset": 26,
+                    "size": 3
+                  },
+                  "OUT_COUNT": {
+                    "description": "The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.",
+                    "offset": 20,
+                    "size": 6
+                  },
+                  "IN_BASE": {
+                    "description": "The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SIDESET_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SET_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "OUT_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SM2_CLKDIV": {
+              "description": "Clock divisor register for state machine 2\\n\n            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 65536,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Effective frequency is sysclk/(int + frac/256).\\n\n                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FRAC": {
+                    "description": "Fractional part of clock divisor",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SM2_EXECCTRL": {
+              "description": "Execution/behavioural settings for state machine 2",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 126976,
+              "children": {
+                "fields": {
+                  "EXEC_STALLED": {
+                    "description": "If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SIDE_EN": {
+                    "description": "If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SIDE_PINDIR": {
+                    "description": "If 1, side-set data is asserted to pin directions, instead of pin values",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "JMP_PIN": {
+                    "description": "The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "OUT_EN_SEL": {
+                    "description": "Which data bit to use for inline OUT enable",
+                    "offset": 19,
+                    "size": 5
+                  },
+                  "INLINE_OUT_EN": {
+                    "description": "If 1, use a bit of OUT data as an auxiliary write enable\\n\n                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\\n\n                deassert the latest pin write. This can create useful masking/override behaviour\\n\n                due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OUT_STICKY": {
+                    "description": "Continuously assert the most recent OUT/SET to the pins",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WRAP_TOP": {
+                    "description": "After reaching this address, execution is wrapped to wrap_bottom.\\n\n                If the instruction is a jump, and the jump condition is true, the jump takes priority.",
+                    "offset": 12,
+                    "size": 5
+                  },
+                  "WRAP_BOTTOM": {
+                    "description": "After reaching wrap_top, execution is wrapped to this address.",
+                    "offset": 7,
+                    "size": 5
+                  },
+                  "STATUS_SEL": {
+                    "description": "Comparison used for the MOV x, STATUS instruction.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TXLEVEL": {
+                            "description": "All-ones if TX FIFO level < N, otherwise all-zeroes",
+                            "value": 0
+                          },
+                          "RXLEVEL": {
+                            "description": "All-ones if RX FIFO level < N, otherwise all-zeroes",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STATUS_N": {
+                    "description": "Comparison level for the MOV x, STATUS instruction",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SM2_SHIFTCTRL": {
+              "description": "Control behaviour of the input/output shift registers for state machine 2",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 786432,
+              "children": {
+                "fields": {
+                  "FJOIN_RX": {
+                    "description": "When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\\n\n                TX FIFO is disabled as a result (always reads as both full and empty).\\n\n                FIFOs are flushed when this bit is changed.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "FJOIN_TX": {
+                    "description": "When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\\n\n                RX FIFO is disabled as a result (always reads as both full and empty).\\n\n                FIFOs are flushed when this bit is changed.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PULL_THRESH": {
+                    "description": "Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\\n\n                Write 0 for value of 32.",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "PUSH_THRESH": {
+                    "description": "Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\\n\n                Write 0 for value of 32.",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "OUT_SHIFTDIR": {
+                    "description": "1 = shift out of output shift register to right. 0 = to left.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IN_SHIFTDIR": {
+                    "description": "1 = shift input shift register to right (data enters from left). 0 = to left.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "AUTOPULL": {
+                    "description": "Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "AUTOPUSH": {
+                    "description": "Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SM2_ADDR": {
+              "description": "Current instruction address of state machine 2",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM2_ADDR": {
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SM2_INSTR": {
+              "description": "Read to see the instruction currently addressed by state machine 2's program counter\\n\n            Write to execute an instruction immediately (including jumps) and then resume execution.",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM2_INSTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SM2_PINCTRL": {
+              "description": "State machine pin control",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 335544320,
+              "children": {
+                "fields": {
+                  "SIDESET_COUNT": {
+                    "description": "The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).",
+                    "offset": 29,
+                    "size": 3
+                  },
+                  "SET_COUNT": {
+                    "description": "The number of pins asserted by a SET. In the range 0 to 5 inclusive.",
+                    "offset": 26,
+                    "size": 3
+                  },
+                  "OUT_COUNT": {
+                    "description": "The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.",
+                    "offset": 20,
+                    "size": 6
+                  },
+                  "IN_BASE": {
+                    "description": "The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SIDESET_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SET_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "OUT_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SM3_CLKDIV": {
+              "description": "Clock divisor register for state machine 3\\n\n            Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 65536,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Effective frequency is sysclk/(int + frac/256).\\n\n                Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "FRAC": {
+                    "description": "Fractional part of clock divisor",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SM3_EXECCTRL": {
+              "description": "Execution/behavioural settings for state machine 3",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 126976,
+              "children": {
+                "fields": {
+                  "EXEC_STALLED": {
+                    "description": "If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SIDE_EN": {
+                    "description": "If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SIDE_PINDIR": {
+                    "description": "If 1, side-set data is asserted to pin directions, instead of pin values",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "JMP_PIN": {
+                    "description": "The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "OUT_EN_SEL": {
+                    "description": "Which data bit to use for inline OUT enable",
+                    "offset": 19,
+                    "size": 5
+                  },
+                  "INLINE_OUT_EN": {
+                    "description": "If 1, use a bit of OUT data as an auxiliary write enable\\n\n                When used in conjunction with OUT_STICKY, writes with an enable of 0 will\\n\n                deassert the latest pin write. This can create useful masking/override behaviour\\n\n                due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OUT_STICKY": {
+                    "description": "Continuously assert the most recent OUT/SET to the pins",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WRAP_TOP": {
+                    "description": "After reaching this address, execution is wrapped to wrap_bottom.\\n\n                If the instruction is a jump, and the jump condition is true, the jump takes priority.",
+                    "offset": 12,
+                    "size": 5
+                  },
+                  "WRAP_BOTTOM": {
+                    "description": "After reaching wrap_top, execution is wrapped to this address.",
+                    "offset": 7,
+                    "size": 5
+                  },
+                  "STATUS_SEL": {
+                    "description": "Comparison used for the MOV x, STATUS instruction.",
+                    "offset": 4,
+                    "size": 1,
+                    "enum": {
+                      "size": 1,
+                      "children": {
+                        "enum_fields": {
+                          "TXLEVEL": {
+                            "description": "All-ones if TX FIFO level < N, otherwise all-zeroes",
+                            "value": 0
+                          },
+                          "RXLEVEL": {
+                            "description": "All-ones if RX FIFO level < N, otherwise all-zeroes",
+                            "value": 1
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "STATUS_N": {
+                    "description": "Comparison level for the MOV x, STATUS instruction",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SM3_SHIFTCTRL": {
+              "description": "Control behaviour of the input/output shift registers for state machine 3",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 786432,
+              "children": {
+                "fields": {
+                  "FJOIN_RX": {
+                    "description": "When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\\n\n                TX FIFO is disabled as a result (always reads as both full and empty).\\n\n                FIFOs are flushed when this bit is changed.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "FJOIN_TX": {
+                    "description": "When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\\n\n                RX FIFO is disabled as a result (always reads as both full and empty).\\n\n                FIFOs are flushed when this bit is changed.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PULL_THRESH": {
+                    "description": "Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.\\n\n                Write 0 for value of 32.",
+                    "offset": 25,
+                    "size": 5
+                  },
+                  "PUSH_THRESH": {
+                    "description": "Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.\\n\n                Write 0 for value of 32.",
+                    "offset": 20,
+                    "size": 5
+                  },
+                  "OUT_SHIFTDIR": {
+                    "description": "1 = shift out of output shift register to right. 0 = to left.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "IN_SHIFTDIR": {
+                    "description": "1 = shift input shift register to right (data enters from left). 0 = to left.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "AUTOPULL": {
+                    "description": "Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "AUTOPUSH": {
+                    "description": "Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SM3_ADDR": {
+              "description": "Current instruction address of state machine 3",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM3_ADDR": {
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SM3_INSTR": {
+              "description": "Read to see the instruction currently addressed by state machine 3's program counter\\n\n            Write to execute an instruction immediately (including jumps) and then resume execution.",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM3_INSTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SM3_PINCTRL": {
+              "description": "State machine pin control",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 335544320,
+              "children": {
+                "fields": {
+                  "SIDESET_COUNT": {
+                    "description": "The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).",
+                    "offset": 29,
+                    "size": 3
+                  },
+                  "SET_COUNT": {
+                    "description": "The number of pins asserted by a SET. In the range 0 to 5 inclusive.",
+                    "offset": 26,
+                    "size": 3
+                  },
+                  "OUT_COUNT": {
+                    "description": "The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.",
+                    "offset": 20,
+                    "size": 6
+                  },
+                  "IN_BASE": {
+                    "description": "The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.",
+                    "offset": 15,
+                    "size": 5
+                  },
+                  "SIDESET_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.",
+                    "offset": 10,
+                    "size": 5
+                  },
+                  "SET_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "OUT_BASE": {
+                    "description": "The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "INTR": {
+              "description": "Raw Interrupts",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM3": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM2": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM1": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM0": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM3_TXNFULL": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM2_TXNFULL": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM1_TXNFULL": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM0_TXNFULL": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM3_RXNEMPTY": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM2_RXNEMPTY": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM1_RXNEMPTY": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM0_RXNEMPTY": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IRQ0_INTE": {
+              "description": "Interrupt Enable for irq0",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM3": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SM2": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SM1": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SM0": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SM3_TXNFULL": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SM2_TXNFULL": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SM1_TXNFULL": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SM0_TXNFULL": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SM3_RXNEMPTY": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SM2_RXNEMPTY": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SM1_RXNEMPTY": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SM0_RXNEMPTY": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IRQ0_INTF": {
+              "description": "Interrupt Force for irq0",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM3": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SM2": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SM1": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SM0": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SM3_TXNFULL": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SM2_TXNFULL": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SM1_TXNFULL": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SM0_TXNFULL": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SM3_RXNEMPTY": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SM2_RXNEMPTY": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SM1_RXNEMPTY": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SM0_RXNEMPTY": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IRQ0_INTS": {
+              "description": "Interrupt status after masking & forcing for irq0",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM3": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM2": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM1": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM0": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM3_TXNFULL": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM2_TXNFULL": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM1_TXNFULL": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM0_TXNFULL": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM3_RXNEMPTY": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM2_RXNEMPTY": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM1_RXNEMPTY": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM0_RXNEMPTY": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IRQ1_INTE": {
+              "description": "Interrupt Enable for irq1",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM3": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SM2": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SM1": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SM0": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SM3_TXNFULL": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SM2_TXNFULL": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SM1_TXNFULL": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SM0_TXNFULL": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SM3_RXNEMPTY": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SM2_RXNEMPTY": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SM1_RXNEMPTY": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SM0_RXNEMPTY": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IRQ1_INTF": {
+              "description": "Interrupt Force for irq1",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM3": {
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "SM2": {
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SM1": {
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SM0": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SM3_TXNFULL": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SM2_TXNFULL": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SM1_TXNFULL": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SM0_TXNFULL": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SM3_RXNEMPTY": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SM2_RXNEMPTY": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SM1_RXNEMPTY": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SM0_RXNEMPTY": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IRQ1_INTS": {
+              "description": "Interrupt status after masking & forcing for irq1",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "SM3": {
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM2": {
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM1": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM0": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM3_TXNFULL": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM2_TXNFULL": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM1_TXNFULL": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM0_TXNFULL": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM3_RXNEMPTY": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM2_RXNEMPTY": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM1_RXNEMPTY": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SM0_RXNEMPTY": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ADC": {
+        "description": "Control and data interface to SAR ADC",
+        "children": {
+          "registers": {
+            "CS": {
+              "description": "ADC Control and Status",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RROBIN": {
+                    "description": "Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\\n\n                Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.\\n\n                The first channel to be sampled will be the one currently indicated by AINSEL.\\n\n                AINSEL will be updated after each conversion with the newly-selected channel.",
+                    "offset": 16,
+                    "size": 5
+                  },
+                  "AINSEL": {
+                    "description": "Select analog mux input. Updated automatically in round-robin mode.",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "ERR_STICKY": {
+                    "description": "Some past ADC conversion encountered an error. Write 1 to clear.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "ERR": {
+                    "description": "The most recent ADC conversion encountered an error; result is undefined or noisy.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READY": {
+                    "description": "1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.\\n\n                0 whilst conversion in progress.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "START_MANY": {
+                    "description": "Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "START_ONCE": {
+                    "description": "Start a single conversion. Self-clearing. Ignored if start_many is asserted.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TS_EN": {
+                    "description": "Power on temperature sensor. 1 - enabled. 0 - disabled.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Power on ADC and enable its clock.\\n\n                1 - enabled. 0 - disabled.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RESULT": {
+              "description": "Result of most recent ADC conversion",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RESULT": {
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FCS": {
+              "description": "FIFO control and status",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "THRESH": {
+                    "description": "DREQ/IRQ asserted when level >= threshold",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "LEVEL": {
+                    "description": "The number of conversion results currently waiting in the FIFO",
+                    "offset": 16,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "OVER": {
+                    "description": "1 if the FIFO has been overflowed. Write 1 to clear.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "UNDER": {
+                    "description": "1 if the FIFO has been underflowed. Write 1 to clear.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FULL": {
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "EMPTY": {
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DREQ_EN": {
+                    "description": "If 1: assert DMA requests when FIFO contains data",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR": {
+                    "description": "If 1: conversion error bit appears in the FIFO alongside the result",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SHIFT": {
+                    "description": "If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "If 1: write result to the FIFO after each conversion.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FIFO": {
+              "description": "Conversion result FIFO",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ERR": {
+                    "description": "1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "VAL": {
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DIV": {
+              "description": "Clock divider. If non-zero, CS_START_MANY will start conversions\\n\n            at regular intervals rather than back-to-back.\\n\n            The divider is reset when either of these fields are written.\\n\n            Total period is 1 + INT + FRAC / 256",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "description": "Integer part of clock divisor.",
+                    "offset": 8,
+                    "size": 16
+                  },
+                  "FRAC": {
+                    "description": "Fractional part of clock divisor. First-order delta-sigma.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "INTR": {
+              "description": "Raw Interrupts",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FIFO": {
+                    "description": "Triggered when the sample FIFO reaches a certain level.\\n\n                This level can be programmed via the FCS_THRESH field.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTE": {
+              "description": "Interrupt Enable",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FIFO": {
+                    "description": "Triggered when the sample FIFO reaches a certain level.\\n\n                This level can be programmed via the FCS_THRESH field.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTF": {
+              "description": "Interrupt Force",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FIFO": {
+                    "description": "Triggered when the sample FIFO reaches a certain level.\\n\n                This level can be programmed via the FCS_THRESH field.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTS": {
+              "description": "Interrupt status after masking & forcing",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FIFO": {
+                    "description": "Triggered when the sample FIFO reaches a certain level.\\n\n                This level can be programmed via the FCS_THRESH field.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "PWM": {
+        "description": "Simple PWM",
+        "children": {
+          "registers": {
+            "CH0_CSR": {
+              "description": "Control and status register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PH_ADV": {
+                    "description": "Advance the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running\\n\n                at less than full speed (div_int + div_frac / 16 > 1)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PH_RET": {
+                    "description": "Retard the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DIVMODE": {
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "div": {
+                            "description": "Free-running counting at rate dictated by fractional divider",
+                            "value": 0
+                          },
+                          "level": {
+                            "description": "Fractional divider operation is gated by the PWM B pin.",
+                            "value": 1
+                          },
+                          "rise": {
+                            "description": "Counter advances with each rising edge of the PWM B pin.",
+                            "value": 2
+                          },
+                          "fall": {
+                            "description": "Counter advances with each falling edge of the PWM B pin.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "B_INV": {
+                    "description": "Invert output B",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "A_INV": {
+                    "description": "Invert output A",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PH_CORRECT": {
+                    "description": "1: Enable phase-correct modulation. 0: Trailing-edge",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Enable the PWM channel.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH0_DIV": {
+              "description": "INT and FRAC form a fixed-point fractional number.\\n\n            Counting rate is system clock frequency divided by this number.\\n\n            Fractional division uses simple 1st-order sigma-delta.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 16,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "offset": 4,
+                    "size": 8
+                  },
+                  "FRAC": {
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CH0_CTR": {
+              "description": "Direct access to the PWM counter",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH0_CTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH0_CC": {
+              "description": "Counter compare values",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "B": {
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "A": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH0_TOP": {
+              "description": "Counter wrap value",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 65535,
+              "children": {
+                "fields": {
+                  "CH0_TOP": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH1_CSR": {
+              "description": "Control and status register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PH_ADV": {
+                    "description": "Advance the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running\\n\n                at less than full speed (div_int + div_frac / 16 > 1)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PH_RET": {
+                    "description": "Retard the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DIVMODE": {
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "div": {
+                            "description": "Free-running counting at rate dictated by fractional divider",
+                            "value": 0
+                          },
+                          "level": {
+                            "description": "Fractional divider operation is gated by the PWM B pin.",
+                            "value": 1
+                          },
+                          "rise": {
+                            "description": "Counter advances with each rising edge of the PWM B pin.",
+                            "value": 2
+                          },
+                          "fall": {
+                            "description": "Counter advances with each falling edge of the PWM B pin.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "B_INV": {
+                    "description": "Invert output B",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "A_INV": {
+                    "description": "Invert output A",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PH_CORRECT": {
+                    "description": "1: Enable phase-correct modulation. 0: Trailing-edge",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Enable the PWM channel.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH1_DIV": {
+              "description": "INT and FRAC form a fixed-point fractional number.\\n\n            Counting rate is system clock frequency divided by this number.\\n\n            Fractional division uses simple 1st-order sigma-delta.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 16,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "offset": 4,
+                    "size": 8
+                  },
+                  "FRAC": {
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CH1_CTR": {
+              "description": "Direct access to the PWM counter",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH1_CTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH1_CC": {
+              "description": "Counter compare values",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "B": {
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "A": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH1_TOP": {
+              "description": "Counter wrap value",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 65535,
+              "children": {
+                "fields": {
+                  "CH1_TOP": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH2_CSR": {
+              "description": "Control and status register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PH_ADV": {
+                    "description": "Advance the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running\\n\n                at less than full speed (div_int + div_frac / 16 > 1)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PH_RET": {
+                    "description": "Retard the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DIVMODE": {
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "div": {
+                            "description": "Free-running counting at rate dictated by fractional divider",
+                            "value": 0
+                          },
+                          "level": {
+                            "description": "Fractional divider operation is gated by the PWM B pin.",
+                            "value": 1
+                          },
+                          "rise": {
+                            "description": "Counter advances with each rising edge of the PWM B pin.",
+                            "value": 2
+                          },
+                          "fall": {
+                            "description": "Counter advances with each falling edge of the PWM B pin.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "B_INV": {
+                    "description": "Invert output B",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "A_INV": {
+                    "description": "Invert output A",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PH_CORRECT": {
+                    "description": "1: Enable phase-correct modulation. 0: Trailing-edge",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Enable the PWM channel.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH2_DIV": {
+              "description": "INT and FRAC form a fixed-point fractional number.\\n\n            Counting rate is system clock frequency divided by this number.\\n\n            Fractional division uses simple 1st-order sigma-delta.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 16,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "offset": 4,
+                    "size": 8
+                  },
+                  "FRAC": {
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CH2_CTR": {
+              "description": "Direct access to the PWM counter",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH2_CTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH2_CC": {
+              "description": "Counter compare values",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "B": {
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "A": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH2_TOP": {
+              "description": "Counter wrap value",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 65535,
+              "children": {
+                "fields": {
+                  "CH2_TOP": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH3_CSR": {
+              "description": "Control and status register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PH_ADV": {
+                    "description": "Advance the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running\\n\n                at less than full speed (div_int + div_frac / 16 > 1)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PH_RET": {
+                    "description": "Retard the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DIVMODE": {
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "div": {
+                            "description": "Free-running counting at rate dictated by fractional divider",
+                            "value": 0
+                          },
+                          "level": {
+                            "description": "Fractional divider operation is gated by the PWM B pin.",
+                            "value": 1
+                          },
+                          "rise": {
+                            "description": "Counter advances with each rising edge of the PWM B pin.",
+                            "value": 2
+                          },
+                          "fall": {
+                            "description": "Counter advances with each falling edge of the PWM B pin.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "B_INV": {
+                    "description": "Invert output B",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "A_INV": {
+                    "description": "Invert output A",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PH_CORRECT": {
+                    "description": "1: Enable phase-correct modulation. 0: Trailing-edge",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Enable the PWM channel.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH3_DIV": {
+              "description": "INT and FRAC form a fixed-point fractional number.\\n\n            Counting rate is system clock frequency divided by this number.\\n\n            Fractional division uses simple 1st-order sigma-delta.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 16,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "offset": 4,
+                    "size": 8
+                  },
+                  "FRAC": {
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CH3_CTR": {
+              "description": "Direct access to the PWM counter",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH3_CTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH3_CC": {
+              "description": "Counter compare values",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "B": {
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "A": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH3_TOP": {
+              "description": "Counter wrap value",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 65535,
+              "children": {
+                "fields": {
+                  "CH3_TOP": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH4_CSR": {
+              "description": "Control and status register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PH_ADV": {
+                    "description": "Advance the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running\\n\n                at less than full speed (div_int + div_frac / 16 > 1)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PH_RET": {
+                    "description": "Retard the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DIVMODE": {
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "div": {
+                            "description": "Free-running counting at rate dictated by fractional divider",
+                            "value": 0
+                          },
+                          "level": {
+                            "description": "Fractional divider operation is gated by the PWM B pin.",
+                            "value": 1
+                          },
+                          "rise": {
+                            "description": "Counter advances with each rising edge of the PWM B pin.",
+                            "value": 2
+                          },
+                          "fall": {
+                            "description": "Counter advances with each falling edge of the PWM B pin.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "B_INV": {
+                    "description": "Invert output B",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "A_INV": {
+                    "description": "Invert output A",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PH_CORRECT": {
+                    "description": "1: Enable phase-correct modulation. 0: Trailing-edge",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Enable the PWM channel.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH4_DIV": {
+              "description": "INT and FRAC form a fixed-point fractional number.\\n\n            Counting rate is system clock frequency divided by this number.\\n\n            Fractional division uses simple 1st-order sigma-delta.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 16,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "offset": 4,
+                    "size": 8
+                  },
+                  "FRAC": {
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CH4_CTR": {
+              "description": "Direct access to the PWM counter",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH4_CTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH4_CC": {
+              "description": "Counter compare values",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "B": {
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "A": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH4_TOP": {
+              "description": "Counter wrap value",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 65535,
+              "children": {
+                "fields": {
+                  "CH4_TOP": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH5_CSR": {
+              "description": "Control and status register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PH_ADV": {
+                    "description": "Advance the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running\\n\n                at less than full speed (div_int + div_frac / 16 > 1)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PH_RET": {
+                    "description": "Retard the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DIVMODE": {
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "div": {
+                            "description": "Free-running counting at rate dictated by fractional divider",
+                            "value": 0
+                          },
+                          "level": {
+                            "description": "Fractional divider operation is gated by the PWM B pin.",
+                            "value": 1
+                          },
+                          "rise": {
+                            "description": "Counter advances with each rising edge of the PWM B pin.",
+                            "value": 2
+                          },
+                          "fall": {
+                            "description": "Counter advances with each falling edge of the PWM B pin.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "B_INV": {
+                    "description": "Invert output B",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "A_INV": {
+                    "description": "Invert output A",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PH_CORRECT": {
+                    "description": "1: Enable phase-correct modulation. 0: Trailing-edge",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Enable the PWM channel.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH5_DIV": {
+              "description": "INT and FRAC form a fixed-point fractional number.\\n\n            Counting rate is system clock frequency divided by this number.\\n\n            Fractional division uses simple 1st-order sigma-delta.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 16,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "offset": 4,
+                    "size": 8
+                  },
+                  "FRAC": {
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CH5_CTR": {
+              "description": "Direct access to the PWM counter",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH5_CTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH5_CC": {
+              "description": "Counter compare values",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "B": {
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "A": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH5_TOP": {
+              "description": "Counter wrap value",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 65535,
+              "children": {
+                "fields": {
+                  "CH5_TOP": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH6_CSR": {
+              "description": "Control and status register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PH_ADV": {
+                    "description": "Advance the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running\\n\n                at less than full speed (div_int + div_frac / 16 > 1)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PH_RET": {
+                    "description": "Retard the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DIVMODE": {
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "div": {
+                            "description": "Free-running counting at rate dictated by fractional divider",
+                            "value": 0
+                          },
+                          "level": {
+                            "description": "Fractional divider operation is gated by the PWM B pin.",
+                            "value": 1
+                          },
+                          "rise": {
+                            "description": "Counter advances with each rising edge of the PWM B pin.",
+                            "value": 2
+                          },
+                          "fall": {
+                            "description": "Counter advances with each falling edge of the PWM B pin.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "B_INV": {
+                    "description": "Invert output B",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "A_INV": {
+                    "description": "Invert output A",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PH_CORRECT": {
+                    "description": "1: Enable phase-correct modulation. 0: Trailing-edge",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Enable the PWM channel.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH6_DIV": {
+              "description": "INT and FRAC form a fixed-point fractional number.\\n\n            Counting rate is system clock frequency divided by this number.\\n\n            Fractional division uses simple 1st-order sigma-delta.",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 16,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "offset": 4,
+                    "size": 8
+                  },
+                  "FRAC": {
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CH6_CTR": {
+              "description": "Direct access to the PWM counter",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH6_CTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH6_CC": {
+              "description": "Counter compare values",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "B": {
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "A": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH6_TOP": {
+              "description": "Counter wrap value",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 65535,
+              "children": {
+                "fields": {
+                  "CH6_TOP": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH7_CSR": {
+              "description": "Control and status register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PH_ADV": {
+                    "description": "Advance the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running\\n\n                at less than full speed (div_int + div_frac / 16 > 1)",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PH_RET": {
+                    "description": "Retard the phase of the counter by 1 count, while it is running.\\n\n                Self-clearing. Write a 1, and poll until low. Counter must be running.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DIVMODE": {
+                    "offset": 4,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "div": {
+                            "description": "Free-running counting at rate dictated by fractional divider",
+                            "value": 0
+                          },
+                          "level": {
+                            "description": "Fractional divider operation is gated by the PWM B pin.",
+                            "value": 1
+                          },
+                          "rise": {
+                            "description": "Counter advances with each rising edge of the PWM B pin.",
+                            "value": 2
+                          },
+                          "fall": {
+                            "description": "Counter advances with each falling edge of the PWM B pin.",
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "B_INV": {
+                    "description": "Invert output B",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "A_INV": {
+                    "description": "Invert output A",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PH_CORRECT": {
+                    "description": "1: Enable phase-correct modulation. 0: Trailing-edge",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Enable the PWM channel.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH7_DIV": {
+              "description": "INT and FRAC form a fixed-point fractional number.\\n\n            Counting rate is system clock frequency divided by this number.\\n\n            Fractional division uses simple 1st-order sigma-delta.",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 16,
+              "children": {
+                "fields": {
+                  "INT": {
+                    "offset": 4,
+                    "size": 8
+                  },
+                  "FRAC": {
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CH7_CTR": {
+              "description": "Direct access to the PWM counter",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH7_CTR": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH7_CC": {
+              "description": "Counter compare values",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "B": {
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "A": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH7_TOP": {
+              "description": "Counter wrap value",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 65535,
+              "children": {
+                "fields": {
+                  "CH7_TOP": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EN": {
+              "description": "This register aliases the CSR_EN bits for all channels.\\n\n            Writing to this register allows multiple channels to be enabled\\n\n            or disabled simultaneously, so they can run in perfect sync.\\n\n            For each channel, there is only one physical EN register bit,\\n\n            which can be accessed through here or CHx_CSR.",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH7": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CH6": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CH5": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CH4": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH3": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH2": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH1": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CH0": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTR": {
+              "description": "Raw Interrupts",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH7": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CH6": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CH5": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CH4": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH3": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH2": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH1": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CH0": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTE": {
+              "description": "Interrupt Enable",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH7": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CH6": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CH5": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CH4": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH3": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH2": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH1": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CH0": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTF": {
+              "description": "Interrupt Force",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH7": {
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CH6": {
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CH5": {
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CH4": {
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CH3": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CH2": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CH1": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CH0": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTS": {
+              "description": "Interrupt status after masking & forcing",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH7": {
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CH6": {
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CH5": {
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CH4": {
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CH3": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CH2": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CH1": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CH0": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIMER": {
+        "description": "Controls time and alarms\\n\n        time is a 64 bit value indicating the time in usec since power-on\\n\n        timeh is the top 32 bits of time & timel is the bottom 32 bits\\n\n        to change time write to timelw before timehw\\n\n        to read time read from timelr before timehr\\n\n        An alarm is set by setting alarm_enable and writing to the corresponding alarm register\\n\n        When an alarm is pending, the corresponding alarm_running signal will be high\\n\n        An alarm can be cancelled before it has finished by clearing the alarm_enable\\n\n        When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\\n\n        To clear the interrupt write a 1 to the corresponding alarm_irq",
+        "children": {
+          "registers": {
+            "TIMEHW": {
+              "description": "Write to bits 63:32 of time\\n\n            always write timelw before timehw",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "access": "write-only"
+            },
+            "TIMELW": {
+              "description": "Write to bits 31:0 of time\\n\n            writes do not get copied to time until timehw is written",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "access": "write-only"
+            },
+            "TIMEHR": {
+              "description": "Read from bits 63:32 of time\\n\n            always read timelr before timehr",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "TIMELR": {
+              "description": "Read from bits 31:0 of time",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "ALARM0": {
+              "description": "Arm alarm 0, and configure the time it will fire.\\n\n            Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\\n\n            The alarm will disarm itself once it fires, and can\\n\n            be disarmed early using the ARMED status register.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0
+            },
+            "ALARM1": {
+              "description": "Arm alarm 1, and configure the time it will fire.\\n\n            Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\\n\n            The alarm will disarm itself once it fires, and can\\n\n            be disarmed early using the ARMED status register.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0
+            },
+            "ALARM2": {
+              "description": "Arm alarm 2, and configure the time it will fire.\\n\n            Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\\n\n            The alarm will disarm itself once it fires, and can\\n\n            be disarmed early using the ARMED status register.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0
+            },
+            "ALARM3": {
+              "description": "Arm alarm 3, and configure the time it will fire.\\n\n            Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\\n\n            The alarm will disarm itself once it fires, and can\\n\n            be disarmed early using the ARMED status register.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0
+            },
+            "ARMED": {
+              "description": "Indicates the armed/disarmed status of each alarm.\\n\n            A write to the corresponding ALARMx register arms the alarm.\\n\n            Alarms automatically disarm upon firing, but writing ones here\\n\n            will disarm immediately without waiting to fire.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ARMED": {
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TIMERAWH": {
+              "description": "Raw read from bits 63:32 of time (no side effects)",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "TIMERAWL": {
+              "description": "Raw read from bits 31:0 of time (no side effects)",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "DBGPAUSE": {
+              "description": "Set bits high to enable pause when the corresponding debug ports are active",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 7,
+              "children": {
+                "fields": {
+                  "DBG1": {
+                    "description": "Pause when processor 1 is in debug mode",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DBG0": {
+                    "description": "Pause when processor 0 is in debug mode",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PAUSE": {
+              "description": "Set high to pause the timer",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PAUSE": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTR": {
+              "description": "Raw Interrupts",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ALARM_3": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ALARM_2": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ALARM_1": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ALARM_0": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTE": {
+              "description": "Interrupt Enable",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ALARM_3": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ALARM_2": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ALARM_1": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ALARM_0": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTF": {
+              "description": "Interrupt Force",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ALARM_3": {
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ALARM_2": {
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ALARM_1": {
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ALARM_0": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTS": {
+              "description": "Interrupt status after masking & forcing",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ALARM_3": {
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ALARM_2": {
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ALARM_1": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ALARM_0": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "WATCHDOG": {
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "Watchdog control\\n\n            The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.\\n\n            The watchdog can be triggered in software.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 117440512,
+              "children": {
+                "fields": {
+                  "TRIGGER": {
+                    "description": "Trigger a watchdog reset",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "ENABLE": {
+                    "description": "When not enabled the watchdog timer is paused",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PAUSE_DBG1": {
+                    "description": "Pause the watchdog timer when processor 1 is in debug mode",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PAUSE_DBG0": {
+                    "description": "Pause the watchdog timer when processor 0 is in debug mode",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PAUSE_JTAG": {
+                    "description": "Pause the watchdog timer when JTAG is accessing the bus fabric",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "TIME": {
+                    "description": "Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LOAD": {
+              "description": "Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "LOAD": {
+                    "offset": 0,
+                    "size": 24,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "REASON": {
+              "description": "Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FORCE": {
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIMER": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SCRATCH0": {
+              "description": "Scratch register. Information persists through soft reset of the chip.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SCRATCH1": {
+              "description": "Scratch register. Information persists through soft reset of the chip.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SCRATCH2": {
+              "description": "Scratch register. Information persists through soft reset of the chip.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SCRATCH3": {
+              "description": "Scratch register. Information persists through soft reset of the chip.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SCRATCH4": {
+              "description": "Scratch register. Information persists through soft reset of the chip.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SCRATCH5": {
+              "description": "Scratch register. Information persists through soft reset of the chip.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SCRATCH6": {
+              "description": "Scratch register. Information persists through soft reset of the chip.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0
+            },
+            "SCRATCH7": {
+              "description": "Scratch register. Information persists through soft reset of the chip.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0
+            },
+            "TICK": {
+              "description": "Controls the tick generator",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 512,
+              "children": {
+                "fields": {
+                  "COUNT": {
+                    "description": "Count down timer: the remaining number clk_tick cycles before the next tick is generated.",
+                    "offset": 11,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "RUNNING": {
+                    "description": "Is the tick generator running?",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ENABLE": {
+                    "description": "start / stop tick generation",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CYCLES": {
+                    "description": "Total number of clk_tick cycles before the next tick.",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RTC": {
+        "description": "Register block to control RTC",
+        "children": {
+          "registers": {
+            "CLKDIV_M1": {
+              "description": "Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CLKDIV_M1": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SETUP_0": {
+              "description": "RTC setup register 0",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "YEAR": {
+                    "description": "Year",
+                    "offset": 12,
+                    "size": 12
+                  },
+                  "MONTH": {
+                    "description": "Month (1..12)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "DAY": {
+                    "description": "Day of the month (1..31)",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SETUP_1": {
+              "description": "RTC setup register 1",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DOTW": {
+                    "description": "Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "HOUR": {
+                    "description": "Hours",
+                    "offset": 16,
+                    "size": 5
+                  },
+                  "MIN": {
+                    "description": "Minutes",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "SEC": {
+                    "description": "Seconds",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CTRL": {
+              "description": "RTC Control and status",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FORCE_NOTLEAPYEAR": {
+                    "description": "If set, leapyear is forced off.\\n\n                Useful for years divisible by 100 but not by 400",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LOAD": {
+                    "description": "Load RTC",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RTC_ACTIVE": {
+                    "description": "RTC enabled (running)",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_ENABLE": {
+                    "description": "Enable RTC",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IRQ_SETUP_0": {
+              "description": "Interrupt setup register 0",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "MATCH_ACTIVE": {
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MATCH_ENA": {
+                    "description": "Global match enable. Don't change any other value while this one is enabled",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "YEAR_ENA": {
+                    "description": "Enable year matching",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "MONTH_ENA": {
+                    "description": "Enable month matching",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "DAY_ENA": {
+                    "description": "Enable day matching",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "YEAR": {
+                    "description": "Year",
+                    "offset": 12,
+                    "size": 12
+                  },
+                  "MONTH": {
+                    "description": "Month (1..12)",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "DAY": {
+                    "description": "Day of the month (1..31)",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "IRQ_SETUP_1": {
+              "description": "Interrupt setup register 1",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DOTW_ENA": {
+                    "description": "Enable day of the week matching",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "HOUR_ENA": {
+                    "description": "Enable hour matching",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "MIN_ENA": {
+                    "description": "Enable minute matching",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SEC_ENA": {
+                    "description": "Enable second matching",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DOTW": {
+                    "description": "Day of the week",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "HOUR": {
+                    "description": "Hours",
+                    "offset": 16,
+                    "size": 5
+                  },
+                  "MIN": {
+                    "description": "Minutes",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "SEC": {
+                    "description": "Seconds",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "RTC_1": {
+              "description": "RTC register 1.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "YEAR": {
+                    "description": "Year",
+                    "offset": 12,
+                    "size": 12,
+                    "access": "read-only"
+                  },
+                  "MONTH": {
+                    "description": "Month (1..12)",
+                    "offset": 8,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "DAY": {
+                    "description": "Day of the month (1..31)",
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RTC_0": {
+              "description": "RTC register 0\\n\n            Read this before RTC 1!",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DOTW": {
+                    "description": "Day of the week",
+                    "offset": 24,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "HOUR": {
+                    "description": "Hours",
+                    "offset": 16,
+                    "size": 5,
+                    "access": "read-only"
+                  },
+                  "MIN": {
+                    "description": "Minutes",
+                    "offset": 8,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "SEC": {
+                    "description": "Seconds",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTR": {
+              "description": "Raw Interrupts",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RTC": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTE": {
+              "description": "Interrupt Enable",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RTC": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTF": {
+              "description": "Interrupt Force",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RTC": {
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTS": {
+              "description": "Interrupt status after masking & forcing",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RTC": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ROSC": {
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "Ring Oscillator control",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2720,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "On power-up this field is initialised to ENABLE\\n\n                The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up\\n\n                The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.",
+                    "offset": 12,
+                    "size": 12,
+                    "enum": {
+                      "size": 12,
+                      "children": {
+                        "enum_fields": {
+                          "DISABLE": {
+                            "value": 3358
+                          },
+                          "ENABLE": {
+                            "value": 4011
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "FREQ_RANGE": {
+                    "description": "Controls the number of delay stages in the ROSC ring\\n\n                LOW uses stages 0 to 7\\n\n                MEDIUM uses stages 0 to 5\\n\n                HIGH uses stages 0 to 3\\n\n                TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications\\n\n                The clock output will not glitch when changing the range up one step at a time\\n\n                The clock output will glitch when changing the range down\\n\n                Note: the values here are gray coded which is why HIGH comes before TOOHIGH",
+                    "offset": 0,
+                    "size": 12,
+                    "enum": {
+                      "size": 12,
+                      "children": {
+                        "enum_fields": {
+                          "LOW": {
+                            "value": 4004
+                          },
+                          "MEDIUM": {
+                            "value": 4005
+                          },
+                          "HIGH": {
+                            "value": 4007
+                          },
+                          "TOOHIGH": {
+                            "value": 4006
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "FREQA": {
+              "description": "The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage\\n\n            The drive strength has 4 levels determined by the number of bits set\\n\n            Increasing the number of bits set increases the drive strength and increases the oscillation frequency\\n\n            0 bits set is the default drive strength\\n\n            1 bit set doubles the drive strength\\n\n            2 bits set triples drive strength\\n\n            3 bits set quadruples drive strength",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PASSWD": {
+                    "description": "Set to 0x9696 to apply the settings\\n\n                Any other value in this field will set all drive strengths to 0",
+                    "offset": 16,
+                    "size": 16,
+                    "enum": {
+                      "size": 16,
+                      "children": {
+                        "enum_fields": {
+                          "PASS": {
+                            "value": 38550
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DS3": {
+                    "description": "Stage 3 drive strength",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "DS2": {
+                    "description": "Stage 2 drive strength",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "DS1": {
+                    "description": "Stage 1 drive strength",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "DS0": {
+                    "description": "Stage 0 drive strength",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "FREQB": {
+              "description": "For a detailed description see freqa register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PASSWD": {
+                    "description": "Set to 0x9696 to apply the settings\\n\n                Any other value in this field will set all drive strengths to 0",
+                    "offset": 16,
+                    "size": 16,
+                    "enum": {
+                      "size": 16,
+                      "children": {
+                        "enum_fields": {
+                          "PASS": {
+                            "value": 38550
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DS7": {
+                    "description": "Stage 7 drive strength",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "DS6": {
+                    "description": "Stage 6 drive strength",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "DS5": {
+                    "description": "Stage 5 drive strength",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "DS4": {
+                    "description": "Stage 4 drive strength",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DORMANT": {
+              "description": "Ring Oscillator pause control\\n\n            This is used to save power by pausing the ROSC\\n\n            On power-up this field is initialised to WAKE\\n\n            An invalid write will also select WAKE\\n\n            Warning: setup the irq before selecting dormant mode",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0
+            },
+            "DIV": {
+              "description": "Controls the output divider",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "DIV": {
+                    "description": "set to 0xaa0 + div where\\n\n                div = 0 divides by 32\\n\n                div = 1-31 divides by div\\n\n                any other value sets div=31\\n\n                this register resets to div=16",
+                    "offset": 0,
+                    "size": 12,
+                    "enum": {
+                      "size": 12,
+                      "children": {
+                        "enum_fields": {
+                          "PASS": {
+                            "value": 2720
+                          }
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "PHASE": {
+              "description": "Controls the phase shifted output",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 8,
+              "children": {
+                "fields": {
+                  "PASSWD": {
+                    "description": "set to 0xaa\\n\n                any other value enables the output with shift=0",
+                    "offset": 4,
+                    "size": 8
+                  },
+                  "ENABLE": {
+                    "description": "enable the phase-shifted output\\n\n                this can be changed on-the-fly",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FLIP": {
+                    "description": "invert the phase-shifted output\\n\n                this is ignored when div=1",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SHIFT": {
+                    "description": "phase shift the phase-shifted output by SHIFT input clocks\\n\n                this can be changed on-the-fly\\n\n                must be set to 0 before setting div=1",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Ring Oscillator Status",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "STABLE": {
+                    "description": "Oscillator is running and stable",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BADWRITE": {
+                    "description": "An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "DIV_RUNNING": {
+                    "description": "post-divider is running\\n\n                this resets to 0 but transitions to 1 during chip startup",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ENABLED": {
+                    "description": "Oscillator is enabled but not necessarily running and stable\\n\n                this resets to 0 but transitions to 1 during chip startup",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RANDOMBIT": {
+              "description": "This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 1,
+              "children": {
+                "fields": {
+                  "RANDOMBIT": {
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COUNT": {
+              "description": "A down counter running at the ROSC frequency which counts to zero and stops.\\n\n            To start the counter write a non-zero value.\\n\n            Can be used for short software pauses when setting up time sensitive hardware.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "COUNT": {
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "VREG_AND_CHIP_RESET": {
+        "description": "control and status for on-chip voltage regulator and chip level reset subsystem",
+        "children": {
+          "registers": {
+            "VREG": {
+              "description": "Voltage regulator control and status",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 177,
+              "children": {
+                "fields": {
+                  "ROK": {
+                    "description": "regulation status\\n\n                0=not in regulation, 1=in regulation",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "VSEL": {
+                    "description": "output voltage select\\n\n                0000 to 0101 - 0.80V\\n\n                0110         - 0.85V\\n\n                0111         - 0.90V\\n\n                1000         - 0.95V\\n\n                1001         - 1.00V\\n\n                1010         - 1.05V\\n\n                1011         - 1.10V (default)\\n\n                1100         - 1.15V\\n\n                1101         - 1.20V\\n\n                1110         - 1.25V\\n\n                1111         - 1.30V",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "HIZ": {
+                    "description": "high impedance mode select\\n\n                0=not in high impedance mode, 1=in high impedance mode",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "enable\\n\n                0=not enabled, 1=enabled",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BOD": {
+              "description": "brown-out detection control",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 145,
+              "children": {
+                "fields": {
+                  "VSEL": {
+                    "description": "threshold select\\n\n                0000 - 0.473V\\n\n                0001 - 0.516V\\n\n                0010 - 0.559V\\n\n                0011 - 0.602V\\n\n                0100 - 0.645V\\n\n                0101 - 0.688V\\n\n                0110 - 0.731V\\n\n                0111 - 0.774V\\n\n                1000 - 0.817V\\n\n                1001 - 0.860V (default)\\n\n                1010 - 0.903V\\n\n                1011 - 0.946V\\n\n                1100 - 0.989V\\n\n                1101 - 1.032V\\n\n                1110 - 1.075V\\n\n                1111 - 1.118V",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "EN": {
+                    "description": "enable\\n\n                0=not enabled, 1=enabled",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CHIP_RESET": {
+              "description": "Chip reset control and status",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "PSM_RESTART_FLAG": {
+                    "description": "This is set by psm_restart from the debugger.\\n\n                Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.\\n\n                In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "HAD_PSM_RESTART": {
+                    "description": "Last reset was from the debug port",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HAD_RUN": {
+                    "description": "Last reset was from the RUN pin",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "HAD_POR": {
+                    "description": "Last reset was from the power-on reset or brown-out detection blocks",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TBMAN": {
+        "description": "Testbench manager. Allows the programmer to know what platform their software is running on.",
+        "children": {
+          "registers": {
+            "PLATFORM": {
+              "description": "Indicates the type of platform in use",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 5,
+              "children": {
+                "fields": {
+                  "FPGA": {
+                    "description": "Indicates the platform is an FPGA",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ASIC": {
+                    "description": "Indicates the platform is an ASIC",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DMA": {
+        "description": "DMA with separate read and write masters",
+        "children": {
+          "registers": {
+            "CH0_READ_ADDR": {
+              "description": "DMA Channel 0 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_WRITE_ADDR": {
+              "description": "DMA Channel 0 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_TRANS_COUNT": {
+              "description": "DMA Channel 0 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_CTRL_TRIG": {
+              "description": "DMA Channel 0 Control and Status",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH0_AL1_CTRL": {
+              "description": "Alias for channel 0 CTRL register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_AL1_READ_ADDR": {
+              "description": "Alias for channel 0 READ_ADDR register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 0 WRITE_ADDR register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 0 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_AL2_CTRL": {
+              "description": "Alias for channel 0 CTRL register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 0 TRANS_COUNT register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_AL2_READ_ADDR": {
+              "description": "Alias for channel 0 READ_ADDR register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 0 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_AL3_CTRL": {
+              "description": "Alias for channel 0 CTRL register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 0 WRITE_ADDR register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 0 TRANS_COUNT register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH0_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 0 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_READ_ADDR": {
+              "description": "DMA Channel 1 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_WRITE_ADDR": {
+              "description": "DMA Channel 1 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_TRANS_COUNT": {
+              "description": "DMA Channel 1 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_CTRL_TRIG": {
+              "description": "DMA Channel 1 Control and Status",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH1_AL1_CTRL": {
+              "description": "Alias for channel 1 CTRL register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_AL1_READ_ADDR": {
+              "description": "Alias for channel 1 READ_ADDR register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 1 WRITE_ADDR register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 1 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_AL2_CTRL": {
+              "description": "Alias for channel 1 CTRL register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 1 TRANS_COUNT register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_AL2_READ_ADDR": {
+              "description": "Alias for channel 1 READ_ADDR register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 1 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_AL3_CTRL": {
+              "description": "Alias for channel 1 CTRL register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 1 WRITE_ADDR register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 1 TRANS_COUNT register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH1_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 1 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_READ_ADDR": {
+              "description": "DMA Channel 2 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_WRITE_ADDR": {
+              "description": "DMA Channel 2 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_TRANS_COUNT": {
+              "description": "DMA Channel 2 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_CTRL_TRIG": {
+              "description": "DMA Channel 2 Control and Status",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH2_AL1_CTRL": {
+              "description": "Alias for channel 2 CTRL register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_AL1_READ_ADDR": {
+              "description": "Alias for channel 2 READ_ADDR register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 2 WRITE_ADDR register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 2 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_AL2_CTRL": {
+              "description": "Alias for channel 2 CTRL register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 2 TRANS_COUNT register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_AL2_READ_ADDR": {
+              "description": "Alias for channel 2 READ_ADDR register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 2 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_AL3_CTRL": {
+              "description": "Alias for channel 2 CTRL register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 2 WRITE_ADDR register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 2 TRANS_COUNT register",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH2_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 2 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_READ_ADDR": {
+              "description": "DMA Channel 3 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_WRITE_ADDR": {
+              "description": "DMA Channel 3 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_TRANS_COUNT": {
+              "description": "DMA Channel 3 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_CTRL_TRIG": {
+              "description": "DMA Channel 3 Control and Status",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH3_AL1_CTRL": {
+              "description": "Alias for channel 3 CTRL register",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_AL1_READ_ADDR": {
+              "description": "Alias for channel 3 READ_ADDR register",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 3 WRITE_ADDR register",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 3 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_AL2_CTRL": {
+              "description": "Alias for channel 3 CTRL register",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 3 TRANS_COUNT register",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_AL2_READ_ADDR": {
+              "description": "Alias for channel 3 READ_ADDR register",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 3 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_AL3_CTRL": {
+              "description": "Alias for channel 3 CTRL register",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 3 WRITE_ADDR register",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 3 TRANS_COUNT register",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH3_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 3 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_READ_ADDR": {
+              "description": "DMA Channel 4 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_WRITE_ADDR": {
+              "description": "DMA Channel 4 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_TRANS_COUNT": {
+              "description": "DMA Channel 4 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_CTRL_TRIG": {
+              "description": "DMA Channel 4 Control and Status",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH4_AL1_CTRL": {
+              "description": "Alias for channel 4 CTRL register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_AL1_READ_ADDR": {
+              "description": "Alias for channel 4 READ_ADDR register",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 4 WRITE_ADDR register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 4 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_AL2_CTRL": {
+              "description": "Alias for channel 4 CTRL register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 4 TRANS_COUNT register",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_AL2_READ_ADDR": {
+              "description": "Alias for channel 4 READ_ADDR register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 4 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_AL3_CTRL": {
+              "description": "Alias for channel 4 CTRL register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 4 WRITE_ADDR register",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 4 TRANS_COUNT register",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH4_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 4 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_READ_ADDR": {
+              "description": "DMA Channel 5 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_WRITE_ADDR": {
+              "description": "DMA Channel 5 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_TRANS_COUNT": {
+              "description": "DMA Channel 5 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_CTRL_TRIG": {
+              "description": "DMA Channel 5 Control and Status",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH5_AL1_CTRL": {
+              "description": "Alias for channel 5 CTRL register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_AL1_READ_ADDR": {
+              "description": "Alias for channel 5 READ_ADDR register",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 5 WRITE_ADDR register",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 5 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_AL2_CTRL": {
+              "description": "Alias for channel 5 CTRL register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 5 TRANS_COUNT register",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_AL2_READ_ADDR": {
+              "description": "Alias for channel 5 READ_ADDR register",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 5 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_AL3_CTRL": {
+              "description": "Alias for channel 5 CTRL register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 5 WRITE_ADDR register",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 5 TRANS_COUNT register",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH5_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 5 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 380,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_READ_ADDR": {
+              "description": "DMA Channel 6 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_WRITE_ADDR": {
+              "description": "DMA Channel 6 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_TRANS_COUNT": {
+              "description": "DMA Channel 6 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_CTRL_TRIG": {
+              "description": "DMA Channel 6 Control and Status",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH6_AL1_CTRL": {
+              "description": "Alias for channel 6 CTRL register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_AL1_READ_ADDR": {
+              "description": "Alias for channel 6 READ_ADDR register",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 6 WRITE_ADDR register",
+              "offset": 408,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 6 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 412,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_AL2_CTRL": {
+              "description": "Alias for channel 6 CTRL register",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 6 TRANS_COUNT register",
+              "offset": 420,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_AL2_READ_ADDR": {
+              "description": "Alias for channel 6 READ_ADDR register",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 6 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_AL3_CTRL": {
+              "description": "Alias for channel 6 CTRL register",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 6 WRITE_ADDR register",
+              "offset": 436,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 6 TRANS_COUNT register",
+              "offset": 440,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH6_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 6 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 444,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_READ_ADDR": {
+              "description": "DMA Channel 7 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_WRITE_ADDR": {
+              "description": "DMA Channel 7 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_TRANS_COUNT": {
+              "description": "DMA Channel 7 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_CTRL_TRIG": {
+              "description": "DMA Channel 7 Control and Status",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH7_AL1_CTRL": {
+              "description": "Alias for channel 7 CTRL register",
+              "offset": 464,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_AL1_READ_ADDR": {
+              "description": "Alias for channel 7 READ_ADDR register",
+              "offset": 468,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 7 WRITE_ADDR register",
+              "offset": 472,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 7 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 476,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_AL2_CTRL": {
+              "description": "Alias for channel 7 CTRL register",
+              "offset": 480,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 7 TRANS_COUNT register",
+              "offset": 484,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_AL2_READ_ADDR": {
+              "description": "Alias for channel 7 READ_ADDR register",
+              "offset": 488,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 7 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 492,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_AL3_CTRL": {
+              "description": "Alias for channel 7 CTRL register",
+              "offset": 496,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 7 WRITE_ADDR register",
+              "offset": 500,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 7 TRANS_COUNT register",
+              "offset": 504,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH7_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 7 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 508,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_READ_ADDR": {
+              "description": "DMA Channel 8 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_WRITE_ADDR": {
+              "description": "DMA Channel 8 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_TRANS_COUNT": {
+              "description": "DMA Channel 8 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_CTRL_TRIG": {
+              "description": "DMA Channel 8 Control and Status",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH8_AL1_CTRL": {
+              "description": "Alias for channel 8 CTRL register",
+              "offset": 528,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_AL1_READ_ADDR": {
+              "description": "Alias for channel 8 READ_ADDR register",
+              "offset": 532,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 8 WRITE_ADDR register",
+              "offset": 536,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 8 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 540,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_AL2_CTRL": {
+              "description": "Alias for channel 8 CTRL register",
+              "offset": 544,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 8 TRANS_COUNT register",
+              "offset": 548,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_AL2_READ_ADDR": {
+              "description": "Alias for channel 8 READ_ADDR register",
+              "offset": 552,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 8 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 556,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_AL3_CTRL": {
+              "description": "Alias for channel 8 CTRL register",
+              "offset": 560,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 8 WRITE_ADDR register",
+              "offset": 564,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 8 TRANS_COUNT register",
+              "offset": 568,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH8_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 8 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 572,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_READ_ADDR": {
+              "description": "DMA Channel 9 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 576,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_WRITE_ADDR": {
+              "description": "DMA Channel 9 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 580,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_TRANS_COUNT": {
+              "description": "DMA Channel 9 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 584,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_CTRL_TRIG": {
+              "description": "DMA Channel 9 Control and Status",
+              "offset": 588,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH9_AL1_CTRL": {
+              "description": "Alias for channel 9 CTRL register",
+              "offset": 592,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_AL1_READ_ADDR": {
+              "description": "Alias for channel 9 READ_ADDR register",
+              "offset": 596,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 9 WRITE_ADDR register",
+              "offset": 600,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 9 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 604,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_AL2_CTRL": {
+              "description": "Alias for channel 9 CTRL register",
+              "offset": 608,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 9 TRANS_COUNT register",
+              "offset": 612,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_AL2_READ_ADDR": {
+              "description": "Alias for channel 9 READ_ADDR register",
+              "offset": 616,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 9 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 620,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_AL3_CTRL": {
+              "description": "Alias for channel 9 CTRL register",
+              "offset": 624,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 9 WRITE_ADDR register",
+              "offset": 628,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 9 TRANS_COUNT register",
+              "offset": 632,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH9_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 9 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 636,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_READ_ADDR": {
+              "description": "DMA Channel 10 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 640,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_WRITE_ADDR": {
+              "description": "DMA Channel 10 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 644,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_TRANS_COUNT": {
+              "description": "DMA Channel 10 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 648,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_CTRL_TRIG": {
+              "description": "DMA Channel 10 Control and Status",
+              "offset": 652,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH10_AL1_CTRL": {
+              "description": "Alias for channel 10 CTRL register",
+              "offset": 656,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_AL1_READ_ADDR": {
+              "description": "Alias for channel 10 READ_ADDR register",
+              "offset": 660,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 10 WRITE_ADDR register",
+              "offset": 664,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 10 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 668,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_AL2_CTRL": {
+              "description": "Alias for channel 10 CTRL register",
+              "offset": 672,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 10 TRANS_COUNT register",
+              "offset": 676,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_AL2_READ_ADDR": {
+              "description": "Alias for channel 10 READ_ADDR register",
+              "offset": 680,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 10 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 684,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_AL3_CTRL": {
+              "description": "Alias for channel 10 CTRL register",
+              "offset": 688,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 10 WRITE_ADDR register",
+              "offset": 692,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 10 TRANS_COUNT register",
+              "offset": 696,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH10_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 10 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 700,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_READ_ADDR": {
+              "description": "DMA Channel 11 Read Address pointer\\n\n            This register updates automatically each time a read completes. The current value is the next address to be read by this channel.",
+              "offset": 704,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_WRITE_ADDR": {
+              "description": "DMA Channel 11 Write Address pointer\\n\n            This register updates automatically each time a write completes. The current value is the next address to be written by this channel.",
+              "offset": 708,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_TRANS_COUNT": {
+              "description": "DMA Channel 11 Transfer Count\\n\n            Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).\\n\\n\n            When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.\\n\\n\n            Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.\\n\\n\n            The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.",
+              "offset": 712,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_CTRL_TRIG": {
+              "description": "DMA Channel 11 Control and Status",
+              "offset": 716,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "AHB_ERROR": {
+                    "description": "Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "READ_ERROR": {
+                    "description": "If 1, the channel received a read bus error. Write one to clear.\\n\n                READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "WRITE_ERROR": {
+                    "description": "If 1, the channel received a write bus error. Write one to clear.\\n\n                WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "BUSY": {
+                    "description": "This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.\\n\\n\n                To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SNIFF_EN": {
+                    "description": "If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.\\n\\n\n                This allows checksum to be enabled or disabled on a per-control- block basis.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Apply byte-swap transformation to DMA data.\\n\n                For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "IRQ_QUIET": {
+                    "description": "In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.\\n\\n\n                This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TREQ_SEL": {
+                    "description": "Select a Transfer Request signal.\\n\n                The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).\\n\n                0x0 to 0x3a -> select DREQ n as TREQ",
+                    "offset": 15,
+                    "size": 6,
+                    "enum": {
+                      "size": 6,
+                      "children": {
+                        "enum_fields": {
+                          "TIMER0": {
+                            "description": "Select Timer 0 as TREQ",
+                            "value": 59
+                          },
+                          "TIMER1": {
+                            "description": "Select Timer 1 as TREQ",
+                            "value": 60
+                          },
+                          "TIMER2": {
+                            "description": "Select Timer 2 as TREQ (Optional)",
+                            "value": 61
+                          },
+                          "TIMER3": {
+                            "description": "Select Timer 3 as TREQ (Optional)",
+                            "value": 62
+                          },
+                          "PERMANENT": {
+                            "description": "Permanent request, for unpaced transfers.",
+                            "value": 63
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "CHAIN_TO": {
+                    "description": "When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.",
+                    "offset": 11,
+                    "size": 4
+                  },
+                  "RING_SEL": {
+                    "description": "Select whether RING_SIZE applies to read or write addresses.\\n\n                If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RING_SIZE": {
+                    "description": "Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.\\n\\n\n                Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.",
+                    "offset": 6,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "RING_NONE": {
+                            "value": 0
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INCR_WRITE": {
+                    "description": "If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for memory-to-peripheral transfers.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "INCR_READ": {
+                    "description": "If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.\\n\\n\n                Generally this should be disabled for peripheral-to-memory transfers.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DATA_SIZE": {
+                    "description": "Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.",
+                    "offset": 2,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "SIZE_BYTE": {
+                            "value": 0
+                          },
+                          "SIZE_HALFWORD": {
+                            "value": 1
+                          },
+                          "SIZE_WORD": {
+                            "value": 2
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "HIGH_PRIORITY": {
+                    "description": "HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.\\n\\n\n                This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "DMA Channel Enable.\\n\n                When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CH11_AL1_CTRL": {
+              "description": "Alias for channel 11 CTRL register",
+              "offset": 720,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_AL1_READ_ADDR": {
+              "description": "Alias for channel 11 READ_ADDR register",
+              "offset": 724,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_AL1_WRITE_ADDR": {
+              "description": "Alias for channel 11 WRITE_ADDR register",
+              "offset": 728,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_AL1_TRANS_COUNT_TRIG": {
+              "description": "Alias for channel 11 TRANS_COUNT register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 732,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_AL2_CTRL": {
+              "description": "Alias for channel 11 CTRL register",
+              "offset": 736,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_AL2_TRANS_COUNT": {
+              "description": "Alias for channel 11 TRANS_COUNT register",
+              "offset": 740,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_AL2_READ_ADDR": {
+              "description": "Alias for channel 11 READ_ADDR register",
+              "offset": 744,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_AL2_WRITE_ADDR_TRIG": {
+              "description": "Alias for channel 11 WRITE_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 748,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_AL3_CTRL": {
+              "description": "Alias for channel 11 CTRL register",
+              "offset": 752,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_AL3_WRITE_ADDR": {
+              "description": "Alias for channel 11 WRITE_ADDR register",
+              "offset": 756,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_AL3_TRANS_COUNT": {
+              "description": "Alias for channel 11 TRANS_COUNT register",
+              "offset": 760,
+              "size": 32,
+              "reset_value": 0
+            },
+            "CH11_AL3_READ_ADDR_TRIG": {
+              "description": "Alias for channel 11 READ_ADDR register\\n\n            This is a trigger register (0xc). Writing a nonzero value will\\n\n            reload the channel counter and start the channel.",
+              "offset": 764,
+              "size": 32,
+              "reset_value": 0
+            },
+            "INTR": {
+              "description": "Interrupt Status (raw)",
+              "offset": 1024,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTR": {
+                    "description": "Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.\\n\\n\n                Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.\\n\\n\n                This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.\\n\\n\n                It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTE0": {
+              "description": "Interrupt Enables for IRQ 0",
+              "offset": 1028,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTE0": {
+                    "description": "Set bit n to pass interrupts from channel n to DMA IRQ 0.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "INTF0": {
+              "description": "Force Interrupts",
+              "offset": 1032,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTF0": {
+                    "description": "Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "INTS0": {
+              "description": "Interrupt Status for IRQ 0",
+              "offset": 1036,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTS0": {
+                    "description": "Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.\\n\n                Channel interrupts can be cleared by writing a bit mask here.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "INTE1": {
+              "description": "Interrupt Enables for IRQ 1",
+              "offset": 1044,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTE1": {
+                    "description": "Set bit n to pass interrupts from channel n to DMA IRQ 1.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "INTF1": {
+              "description": "Force Interrupts for IRQ 1",
+              "offset": 1048,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTF1": {
+                    "description": "Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "INTS1": {
+              "description": "Interrupt Status (masked) for IRQ 1",
+              "offset": 1052,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "INTS1": {
+                    "description": "Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.\\n\n                Channel interrupts can be cleared by writing a bit mask here.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TIMER0": {
+              "description": "Pacing (X/Y) Fractional Timer\\n\n            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.",
+              "offset": 1056,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "X": {
+                    "description": "Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "Y": {
+                    "description": "Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TIMER1": {
+              "description": "Pacing (X/Y) Fractional Timer\\n\n            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.",
+              "offset": 1060,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "X": {
+                    "description": "Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "Y": {
+                    "description": "Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TIMER2": {
+              "description": "Pacing (X/Y) Fractional Timer\\n\n            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.",
+              "offset": 1064,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "X": {
+                    "description": "Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "Y": {
+                    "description": "Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "TIMER3": {
+              "description": "Pacing (X/Y) Fractional Timer\\n\n            The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.",
+              "offset": 1068,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "X": {
+                    "description": "Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.",
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "Y": {
+                    "description": "Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "MULTI_CHAN_TRIGGER": {
+              "description": "Trigger one or more channels simultaneously",
+              "offset": 1072,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "MULTI_CHAN_TRIGGER": {
+                    "description": "Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SNIFF_CTRL": {
+              "description": "Sniffer Control",
+              "offset": 1076,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "OUT_INV": {
+                    "description": "If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OUT_REV": {
+                    "description": "If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BSWAP": {
+                    "description": "Locally perform a byte reverse on the sniffed data, before feeding into checksum.\\n\\n\n                Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CALC": {
+                    "offset": 5,
+                    "size": 4,
+                    "enum": {
+                      "size": 4,
+                      "children": {
+                        "enum_fields": {
+                          "CRC32": {
+                            "description": "Calculate a CRC-32 (IEEE802.3 polynomial)",
+                            "value": 0
+                          },
+                          "CRC32R": {
+                            "description": "Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data",
+                            "value": 1
+                          },
+                          "CRC16": {
+                            "description": "Calculate a CRC-16-CCITT",
+                            "value": 2
+                          },
+                          "CRC16R": {
+                            "description": "Calculate a CRC-16-CCITT with bit reversed data",
+                            "value": 3
+                          },
+                          "EVEN": {
+                            "description": "XOR reduction over all data. == 1 if the total 1 population count is odd.",
+                            "value": 14
+                          },
+                          "SUM": {
+                            "description": "Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)",
+                            "value": 15
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "DMACH": {
+                    "description": "DMA channel for Sniffer to observe",
+                    "offset": 1,
+                    "size": 4
+                  },
+                  "EN": {
+                    "description": "Enable sniffer",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SNIFF_DATA": {
+              "description": "Data accumulator for sniff hardware\\n\n            Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.",
+              "offset": 1080,
+              "size": 32,
+              "reset_value": 0
+            },
+            "FIFO_LEVELS": {
+              "description": "Debug RAF, WAF, TDF levels",
+              "offset": 1088,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "RAF_LVL": {
+                    "description": "Current Read-Address-FIFO fill level",
+                    "offset": 16,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "WAF_LVL": {
+                    "description": "Current Write-Address-FIFO fill level",
+                    "offset": 8,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "TDF_LVL": {
+                    "description": "Current Transfer-Data-FIFO fill level",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CHAN_ABORT": {
+              "description": "Abort an in-progress transfer sequence on one or more channels",
+              "offset": 1092,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CHAN_ABORT": {
+                    "description": "Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.\\n\\n\n                After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "N_CHANNELS": {
+              "description": "The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.",
+              "offset": 1096,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "N_CHANNELS": {
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CH0_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2048,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH0_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH0_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2052,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "CH1_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2112,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH1_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH1_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2116,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "CH2_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2176,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH2_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH2_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2180,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "CH3_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2240,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH3_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH3_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2244,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "CH4_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2304,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH4_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH4_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2308,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "CH5_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2368,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH5_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH5_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2372,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "CH6_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2432,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH6_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH6_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2436,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "CH7_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2496,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH7_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH7_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2500,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "CH8_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2560,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH8_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH8_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2564,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "CH9_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2624,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH9_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH9_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2628,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "CH10_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2688,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH10_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH10_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2692,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            },
+            "CH11_DBG_CTDREQ": {
+              "description": "Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.",
+              "offset": 2752,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "CH11_DBG_CTDREQ": {
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CH11_DBG_TCR": {
+              "description": "Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer",
+              "offset": 2756,
+              "size": 32,
+              "reset_value": 0,
+              "access": "read-only"
+            }
+          }
+        }
+      },
+      "USBCTRL_DPRAM": {
+        "description": "DPRAM layout for USB device.",
+        "children": {
+          "registers": {
+            "SETUP_PACKET_LOW": {
+              "description": "Bytes 0-3 of the SETUP packet from the host.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "WVALUE": {
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "BREQUEST": {
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "BMREQUESTTYPE": {
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SETUP_PACKET_HIGH": {
+              "description": "Bytes 4-7 of the setup packet from the host.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "WLENGTH": {
+                    "offset": 16,
+                    "size": 16
+                  },
+                  "WINDEX": {
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP1_IN_CONTROL": {
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP1_OUT_CONTROL": {
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP2_IN_CONTROL": {
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP2_OUT_CONTROL": {
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP3_IN_CONTROL": {
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP3_OUT_CONTROL": {
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP4_IN_CONTROL": {
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP4_OUT_CONTROL": {
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP5_IN_CONTROL": {
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP5_OUT_CONTROL": {
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP6_IN_CONTROL": {
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP6_OUT_CONTROL": {
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP7_IN_CONTROL": {
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP7_OUT_CONTROL": {
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP8_IN_CONTROL": {
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP8_OUT_CONTROL": {
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP9_IN_CONTROL": {
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP9_OUT_CONTROL": {
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP10_IN_CONTROL": {
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP10_OUT_CONTROL": {
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP11_IN_CONTROL": {
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP11_OUT_CONTROL": {
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP12_IN_CONTROL": {
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP12_OUT_CONTROL": {
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP13_IN_CONTROL": {
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP13_OUT_CONTROL": {
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP14_IN_CONTROL": {
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP14_OUT_CONTROL": {
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP15_IN_CONTROL": {
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP15_OUT_CONTROL": {
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFERED": {
+                    "description": "This endpoint is double buffered.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_BUFF": {
+                    "description": "Trigger an interrupt each time a buffer is done.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "INTERRUPT_PER_DOUBLE_BUFF": {
+                    "description": "Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "ENDPOINT_TYPE": {
+                    "offset": 26,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "Control": {
+                            "value": 0
+                          },
+                          "Isochronous": {
+                            "value": 1
+                          },
+                          "Bulk": {
+                            "value": 2
+                          },
+                          "Interrupt": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "INTERRUPT_ON_STALL": {
+                    "description": "Trigger an interrupt if a STALL is sent. Intended for debug only.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "INTERRUPT_ON_NAK": {
+                    "description": "Trigger an interrupt if a NAK is sent. Intended for debug only.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BUFFER_ADDRESS": {
+                    "description": "64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "EP0_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP0_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP1_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP1_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP2_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP2_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP3_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP3_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP4_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP4_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP5_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP5_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP6_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP6_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP7_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP7_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP8_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP8_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP9_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP9_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP10_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP10_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP11_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP11_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP12_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP12_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP13_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP13_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP14_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP14_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP15_IN_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "EP15_OUT_BUFFER_CONTROL": {
+              "description": "Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.\\n\n            Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "children": {
+                "fields": {
+                  "FULL_1": {
+                    "description": "Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 31,
+                    "size": 1
+                  },
+                  "LAST_1": {
+                    "description": "Buffer 1 is the last buffer of the transfer.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PID_1": {
+                    "description": "The data pid of buffer 1.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DOUBLE_BUFFER_ISO_OFFSET": {
+                    "description": "The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.\\n\n                For a non Isochronous endpoint the offset is always 64 bytes.",
+                    "offset": 27,
+                    "size": 2,
+                    "enum": {
+                      "size": 2,
+                      "children": {
+                        "enum_fields": {
+                          "128": {
+                            "value": 0
+                          },
+                          "256": {
+                            "value": 1
+                          },
+                          "512": {
+                            "value": 2
+                          },
+                          "1024": {
+                            "value": 3
+                          }
+                        }
+                      }
+                    }
+                  },
+                  "AVAILABLE_1": {
+                    "description": "Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LENGTH_1": {
+                    "description": "The length of the data in buffer 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "FULL_0": {
+                    "description": "Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "LAST_0": {
+                    "description": "Buffer 0 is the last buffer of the transfer.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PID_0": {
+                    "description": "The data pid of buffer 0.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RESET": {
+                    "description": "Reset the buffer selector to buffer 0.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STALL": {
+                    "description": "Reply with a stall (valid for both buffers).",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "AVAILABLE_0": {
+                    "description": "Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LENGTH_0": {
+                    "description": "The length of the data in buffer 0.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            }
+          }
+        }
+      }
+    }
+  },
+  "devices": {
+    "RP2040": {
+      "arch": "cortex_m0plus",
+      "properties": {
+        "cpu.nvic_prio_bits": "2",
+        "cpu.mpu": "true",
+        "cpu.fpu": "false",
+        "cpu.num_interrupts": "26",
+        "cpu.vtor": "1",
+        "cpu.revision": "r0p1",
+        "cpu.vendor_systick_config": "false",
+        "license": "\n    Copyright (c) 2020 Raspberry Pi (Trading) Ltd. \\n\n    \\n\n    SPDX-License-Identifier: BSD-3-Clause\n  ",
+        "cpu.name": "CM0PLUS",
+        "cpu.endian": "little"
+      },
+      "children": {
+        "interrupts": {
+          "NMI": {
+            "index": -14
+          },
+          "HardFault": {
+            "index": -13
+          },
+          "SVCall": {
+            "index": -5
+          },
+          "PendSV": {
+            "index": -2
+          },
+          "SysTick": {
+            "index": -1
+          },
+          "XIP_IRQ": {
+            "index": 6
+          },
+          "CLOCKS_IRQ": {
+            "index": 17
+          },
+          "IO_IRQ_BANK0": {
+            "index": 13
+          },
+          "IO_IRQ_QSPI": {
+            "index": 14
+          },
+          "UART0_IRQ": {
+            "index": 20
+          },
+          "UART1_IRQ": {
+            "index": 21
+          },
+          "SPI0_IRQ": {
+            "index": 18
+          },
+          "SPI1_IRQ": {
+            "index": 19
+          },
+          "I2C0_IRQ": {
+            "index": 23
+          },
+          "I2C1_IRQ": {
+            "index": 24
+          },
+          "ADC_IRQ_FIFO": {
+            "index": 22
+          },
+          "PWM_IRQ_WRAP": {
+            "index": 4
+          },
+          "TIMER_IRQ_0": {
+            "index": 0
+          },
+          "TIMER_IRQ_1": {
+            "index": 1
+          },
+          "TIMER_IRQ_2": {
+            "index": 2
+          },
+          "TIMER_IRQ_3": {
+            "index": 3
+          },
+          "RTC_IRQ": {
+            "index": 25
+          },
+          "DMA_IRQ_0": {
+            "index": 11
+          },
+          "DMA_IRQ_1": {
+            "index": 12
+          },
+          "USBCTRL_IRQ": {
+            "index": 5
+          },
+          "PIO0_IRQ_0": {
+            "index": 7
+          },
+          "PIO0_IRQ_1": {
+            "index": 8
+          },
+          "PIO1_IRQ_0": {
+            "index": 9
+          },
+          "PIO1_IRQ_1": {
+            "index": 10
+          },
+          "SIO_IRQ_PROC0": {
+            "index": 15
+          },
+          "SIO_IRQ_PROC1": {
+            "index": 16
+          }
+        },
+        "peripheral_instances": {
+          "SysTick": {
+            "offset": 3758153744,
+            "type": "types.peripherals.SCS.children.register_groups.SysTick"
+          },
+          "SCB": {
+            "offset": 3758157056,
+            "type": "types.peripherals.SCS"
+          },
+          "NVIC": {
+            "offset": 3758153984,
+            "type": "types.peripherals.SCS"
+          },
+          "MPU": {
+            "offset": 3472,
+            "type": "types.peripherals.SCS"
+          },
+          "XIP_CTRL": {
+            "description": "QSPI flash execute-in-place block",
+            "offset": 335544320,
+            "version": "1",
+            "type": "types.peripherals.XIP_CTRL"
+          },
+          "XIP_SSI": {
+            "description": "DW_apb_ssi has the following features:\\n\n        * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.\\n\n        * APB3 and APB4 protocol support.\\n\n        * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.\\n\n        * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.\\n\n        * Programmable Dual/Quad/Octal SPI support in Master Mode.\\n\n        * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.\\n\n        * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.\\n\n        * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.\\n\n        * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.\\n\n        * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.\\n\n        * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.\\n\n        * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.\\n\n        * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.\\n\n        * Programmable features:\\n\n        - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.\\n\n        - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.\\n\n        - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.\\n\n        * Configured features:\\n\n        - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\\n\n        - 1 slave select output.\\n\n        - Hardware slave-select – Dedicated hardware slave-select line.\\n\n        - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.\\n\n        - Interrupt polarity – active high interrupt lines.\\n\n        - Serial clock polarity – low serial-clock polarity directly after reset.\\n\n        - Serial clock phase – capture on first edge of serial-clock directly after reset.",
+            "offset": 402653184,
+            "version": "1",
+            "type": "types.peripherals.XIP_SSI"
+          },
+          "SYSINFO": {
+            "offset": 1073741824,
+            "version": "1",
+            "type": "types.peripherals.SYSINFO"
+          },
+          "SYSCFG": {
+            "description": "Register block for various chip control signals",
+            "offset": 1073758208,
+            "version": "1",
+            "type": "types.peripherals.SYSCFG"
+          },
+          "CLOCKS": {
+            "offset": 1073774592,
+            "version": "1",
+            "type": "types.peripherals.CLOCKS"
+          },
+          "RESETS": {
+            "offset": 1073790976,
+            "version": "1",
+            "type": "types.peripherals.RESETS"
+          },
+          "PSM": {
+            "offset": 1073807360,
+            "version": "1",
+            "type": "types.peripherals.PSM"
+          },
+          "IO_BANK0": {
+            "offset": 1073823744,
+            "version": "1",
+            "type": "types.peripherals.IO_BANK0"
+          },
+          "IO_QSPI": {
+            "offset": 1073840128,
+            "version": "1",
+            "type": "types.peripherals.IO_QSPI"
+          },
+          "PADS_BANK0": {
+            "offset": 1073856512,
+            "version": "1",
+            "type": "types.peripherals.PADS_BANK0"
+          },
+          "PADS_QSPI": {
+            "offset": 1073872896,
+            "version": "1",
+            "type": "types.peripherals.PADS_QSPI"
+          },
+          "XOSC": {
+            "description": "Controls the crystal oscillator",
+            "offset": 1073889280,
+            "version": "1",
+            "type": "types.peripherals.XOSC"
+          },
+          "PLL_SYS": {
+            "offset": 1073905664,
+            "version": "1",
+            "type": "types.peripherals.PLL_SYS"
+          },
+          "PLL_USB": {
+            "offset": 1073922048,
+            "type": "types.peripherals.PLL_SYS"
+          },
+          "BUSCTRL": {
+            "description": "Register block for busfabric control signals and performance counters",
+            "offset": 1073938432,
+            "version": "1",
+            "type": "types.peripherals.BUSCTRL"
+          },
+          "UART0": {
+            "offset": 1073954816,
+            "version": "1",
+            "type": "types.peripherals.UART0"
+          },
+          "UART1": {
+            "offset": 1073971200,
+            "type": "types.peripherals.UART0"
+          },
+          "SPI0": {
+            "offset": 1073987584,
+            "version": "1",
+            "type": "types.peripherals.SPI0"
+          },
+          "SPI1": {
+            "offset": 1074003968,
+            "type": "types.peripherals.SPI0"
+          },
+          "I2C0": {
+            "description": "DW_apb_i2c address block\\n\\n\n        List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):\\n\\n\n        IC_ULTRA_FAST_MODE ................ 0x0\\n\n        IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\\n\n        IC_UFM_SCL_LOW_COUNT .............. 0x0008\\n\n        IC_UFM_SCL_HIGH_COUNT ............. 0x0006\\n\n        IC_TX_TL .......................... 0x0\\n\n        IC_TX_CMD_BLOCK ................... 0x1\\n\n        IC_HAS_DMA ........................ 0x1\\n\n        IC_HAS_ASYNC_FIFO ................. 0x0\\n\n        IC_SMBUS_ARP ...................... 0x0\\n\n        IC_FIRST_DATA_BYTE_STATUS ......... 0x1\\n\n        IC_INTR_IO ........................ 0x1\\n\n        IC_MASTER_MODE .................... 0x1\\n\n        IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\\n\n        IC_INTR_POL ....................... 0x1\\n\n        IC_OPTIONAL_SAR ................... 0x0\\n\n        IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\\n\n        IC_DEFAULT_SLAVE_ADDR ............. 0x055\\n\n        IC_DEFAULT_HS_SPKLEN .............. 0x1\\n\n        IC_FS_SCL_HIGH_COUNT .............. 0x0006\\n\n        IC_HS_SCL_LOW_COUNT ............... 0x0008\\n\n        IC_DEVICE_ID_VALUE ................ 0x0\\n\n        IC_10BITADDR_MASTER ............... 0x0\\n\n        IC_CLK_FREQ_OPTIMIZATION .......... 0x0\\n\n        IC_DEFAULT_FS_SPKLEN .............. 0x7\\n\n        IC_ADD_ENCODED_PARAMS ............. 0x0\\n\n        IC_DEFAULT_SDA_HOLD ............... 0x000001\\n\n        IC_DEFAULT_SDA_SETUP .............. 0x64\\n\n        IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\\n\n        IC_CLOCK_PERIOD ................... 100\\n\n        IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\\n\n        IC_RESTART_EN ..................... 0x1\\n\n        IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\\n\n        IC_BUS_CLEAR_FEATURE .............. 0x0\\n\n        IC_CAP_LOADING .................... 100\\n\n        IC_FS_SCL_LOW_COUNT ............... 0x000d\\n\n        APB_DATA_WIDTH .................... 32\\n\n        IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\\n\n        IC_SLV_DATA_NACK_ONLY ............. 0x1\\n\n        IC_10BITADDR_SLAVE ................ 0x0\\n\n        IC_CLK_TYPE ....................... 0x0\\n\n        IC_SMBUS_UDID_MSB ................. 0x0\\n\n        IC_SMBUS_SUSPEND_ALERT ............ 0x0\\n\n        IC_HS_SCL_HIGH_COUNT .............. 0x0006\\n\n        IC_SLV_RESTART_DET_EN ............. 0x1\\n\n        IC_SMBUS .......................... 0x0\\n\n        IC_OPTIONAL_SAR_DEFAULT ........... 0x0\\n\n        IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\\n\n        IC_USE_COUNTS ..................... 0x0\\n\n        IC_RX_BUFFER_DEPTH ................ 16\\n\n        IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\\n\n        IC_RX_FULL_HLD_BUS_EN ............. 0x1\\n\n        IC_SLAVE_DISABLE .................. 0x1\\n\n        IC_RX_TL .......................... 0x0\\n\n        IC_DEVICE_ID ...................... 0x0\\n\n        IC_HC_COUNT_VALUES ................ 0x0\\n\n        I2C_DYNAMIC_TAR_UPDATE ............ 0\\n\n        IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\\n\n        IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\\n\n        IC_HS_MASTER_CODE ................. 0x1\\n\n        IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\\n\n        IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\\n\n        IC_SS_SCL_HIGH_COUNT .............. 0x0028\\n\n        IC_SS_SCL_LOW_COUNT ............... 0x002f\\n\n        IC_MAX_SPEED_MODE ................. 0x2\\n\n        IC_STAT_FOR_CLK_STRETCH ........... 0x0\\n\n        IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\\n\n        IC_DEFAULT_UFM_SPKLEN ............. 0x1\\n\n        IC_TX_BUFFER_DEPTH ................ 16",
+            "offset": 1074020352,
+            "version": "1",
+            "type": "types.peripherals.I2C0"
+          },
+          "I2C1": {
+            "offset": 1074036736,
+            "type": "types.peripherals.I2C0"
+          },
+          "ADC": {
+            "description": "Control and data interface to SAR ADC",
+            "offset": 1074053120,
+            "version": "2",
+            "type": "types.peripherals.ADC"
+          },
+          "PWM": {
+            "description": "Simple PWM",
+            "offset": 1074069504,
+            "version": "1",
+            "type": "types.peripherals.PWM"
+          },
+          "TIMER": {
+            "description": "Controls time and alarms\\n\n        time is a 64 bit value indicating the time in usec since power-on\\n\n        timeh is the top 32 bits of time & timel is the bottom 32 bits\\n\n        to change time write to timelw before timehw\\n\n        to read time read from timelr before timehr\\n\n        An alarm is set by setting alarm_enable and writing to the corresponding alarm register\\n\n        When an alarm is pending, the corresponding alarm_running signal will be high\\n\n        An alarm can be cancelled before it has finished by clearing the alarm_enable\\n\n        When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared\\n\n        To clear the interrupt write a 1 to the corresponding alarm_irq",
+            "offset": 1074085888,
+            "version": "1",
+            "type": "types.peripherals.TIMER"
+          },
+          "WATCHDOG": {
+            "offset": 1074102272,
+            "version": "1",
+            "type": "types.peripherals.WATCHDOG"
+          },
+          "RTC": {
+            "description": "Register block to control RTC",
+            "offset": 1074118656,
+            "version": "1",
+            "type": "types.peripherals.RTC"
+          },
+          "ROSC": {
+            "offset": 1074135040,
+            "version": "1",
+            "type": "types.peripherals.ROSC"
+          },
+          "VREG_AND_CHIP_RESET": {
+            "description": "control and status for on-chip voltage regulator and chip level reset subsystem",
+            "offset": 1074151424,
+            "version": "1",
+            "type": "types.peripherals.VREG_AND_CHIP_RESET"
+          },
+          "TBMAN": {
+            "description": "Testbench manager. Allows the programmer to know what platform their software is running on.",
+            "offset": 1074184192,
+            "version": "1",
+            "type": "types.peripherals.TBMAN"
+          },
+          "DMA": {
+            "description": "DMA with separate read and write masters",
+            "offset": 1342177280,
+            "version": "1",
+            "type": "types.peripherals.DMA"
+          },
+          "USBCTRL_DPRAM": {
+            "description": "DPRAM layout for USB device.",
+            "offset": 1343225856,
+            "version": "1",
+            "type": "types.peripherals.USBCTRL_DPRAM"
+          },
+          "USBCTRL_REGS": {
+            "description": "USB FS/LS controller device registers",
+            "offset": 1343291392,
+            "version": "1",
+            "type": "types.peripherals.USBCTRL_REGS"
+          },
+          "PIO0": {
+            "description": "Programmable IO block",
+            "offset": 1344274432,
+            "version": "1",
+            "type": "types.peripherals.PIO0"
+          },
+          "PIO1": {
+            "offset": 1345323008,
+            "type": "types.peripherals.PIO0"
+          },
+          "SIO": {
+            "description": "Single-cycle IO block\\n\n        Provides core-local and inter-core hardware for the two processors, with single-cycle access.",
+            "offset": 3489660928,
+            "version": "1",
+            "type": "types.peripherals.SIO"
+          },
+          "PPB": {
+            "offset": 3758096384,
+            "version": "1",
+            "type": "types.peripherals.PPB"
+          }
+        }
+      }
+    }
+  }
+}
diff --git a/src/chips/RP2040.zig b/src/chips/RP2040.zig
new file mode 100644
index 000000000..62af336a8
--- /dev/null
+++ b/src/chips/RP2040.zig
@@ -0,0 +1,18145 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    pub const RP2040 = struct {
+        pub const properties = struct {
+            pub const @"cpu.nvic_prio_bits" = "2";
+            pub const @"cpu.mpu" = "true";
+            pub const @"cpu.fpu" = "false";
+            pub const @"cpu.num_interrupts" = "26";
+            pub const @"cpu.vtor" = "1";
+            pub const @"cpu.revision" = "r0p1";
+            pub const @"cpu.vendor_systick_config" = "false";
+            pub const license =
+                \\
+                \\    Copyright (c) 2020 Raspberry Pi (Trading) Ltd. \n
+                \\    \n
+                \\    SPDX-License-Identifier: BSD-3-Clause
+                \\  
+            ;
+            pub const @"cpu.name" = "CM0PLUS";
+            pub const @"cpu.endian" = "little";
+        };
+
+        pub const VectorTable = extern struct {
+            const Handler = micro.interrupt.Handler;
+            const unhandled = micro.interrupt.unhandled;
+
+            initial_stack_pointer: u32,
+            Reset: Handler = unhandled,
+            NMI: Handler = unhandled,
+            HardFault: Handler = unhandled,
+            reserved2: [7]u32 = undefined,
+            SVCall: Handler = unhandled,
+            reserved10: [2]u32 = undefined,
+            PendSV: Handler = unhandled,
+            SysTick: Handler = unhandled,
+            TIMER_IRQ_0: Handler = unhandled,
+            TIMER_IRQ_1: Handler = unhandled,
+            TIMER_IRQ_2: Handler = unhandled,
+            TIMER_IRQ_3: Handler = unhandled,
+            PWM_IRQ_WRAP: Handler = unhandled,
+            USBCTRL_IRQ: Handler = unhandled,
+            XIP_IRQ: Handler = unhandled,
+            PIO0_IRQ_0: Handler = unhandled,
+            PIO0_IRQ_1: Handler = unhandled,
+            PIO1_IRQ_0: Handler = unhandled,
+            PIO1_IRQ_1: Handler = unhandled,
+            DMA_IRQ_0: Handler = unhandled,
+            DMA_IRQ_1: Handler = unhandled,
+            IO_IRQ_BANK0: Handler = unhandled,
+            IO_IRQ_QSPI: Handler = unhandled,
+            SIO_IRQ_PROC0: Handler = unhandled,
+            SIO_IRQ_PROC1: Handler = unhandled,
+            CLOCKS_IRQ: Handler = unhandled,
+            SPI0_IRQ: Handler = unhandled,
+            SPI1_IRQ: Handler = unhandled,
+            UART0_IRQ: Handler = unhandled,
+            UART1_IRQ: Handler = unhandled,
+            ADC_IRQ_FIFO: Handler = unhandled,
+            I2C0_IRQ: Handler = unhandled,
+            I2C1_IRQ: Handler = unhandled,
+            RTC_IRQ: Handler = unhandled,
+        };
+
+        pub const peripherals = struct {
+            ///  System Control Space
+            pub const MPU = @intToPtr(*volatile types.peripherals.SCS, 0xd90);
+            ///  QSPI flash execute-in-place block
+            pub const XIP_CTRL = @intToPtr(*volatile types.peripherals.XIP_CTRL, 0x14000000);
+            ///  DW_apb_ssi has the following features:
+            ///  * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.
+            ///  * APB3 and APB4 protocol support.
+            ///  * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.
+            ///  * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.
+            ///  * Programmable Dual/Quad/Octal SPI support in Master Mode.
+            ///  * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.
+            ///  * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.
+            ///  * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.
+            ///  * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.
+            ///  * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.
+            ///  * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.
+            ///  * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.
+            ///  * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.
+            ///  * Programmable features:
+            ///  - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.
+            ///  - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.
+            ///  - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.
+            ///  * Configured features:
+            ///  - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.
+            ///  - 1 slave select output.
+            ///  - Hardware slave-select – Dedicated hardware slave-select line.
+            ///  - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.
+            ///  - Interrupt polarity – active high interrupt lines.
+            ///  - Serial clock polarity – low serial-clock polarity directly after reset.
+            ///  - Serial clock phase – capture on first edge of serial-clock directly after reset.
+            pub const XIP_SSI = @intToPtr(*volatile types.peripherals.XIP_SSI, 0x18000000);
+            pub const SYSINFO = @intToPtr(*volatile types.peripherals.SYSINFO, 0x40000000);
+            ///  Register block for various chip control signals
+            pub const SYSCFG = @intToPtr(*volatile types.peripherals.SYSCFG, 0x40004000);
+            pub const CLOCKS = @intToPtr(*volatile types.peripherals.CLOCKS, 0x40008000);
+            pub const RESETS = @intToPtr(*volatile types.peripherals.RESETS, 0x4000c000);
+            pub const PSM = @intToPtr(*volatile types.peripherals.PSM, 0x40010000);
+            pub const IO_BANK0 = @intToPtr(*volatile types.peripherals.IO_BANK0, 0x40014000);
+            pub const IO_QSPI = @intToPtr(*volatile types.peripherals.IO_QSPI, 0x40018000);
+            pub const PADS_BANK0 = @intToPtr(*volatile types.peripherals.PADS_BANK0, 0x4001c000);
+            pub const PADS_QSPI = @intToPtr(*volatile types.peripherals.PADS_QSPI, 0x40020000);
+            ///  Controls the crystal oscillator
+            pub const XOSC = @intToPtr(*volatile types.peripherals.XOSC, 0x40024000);
+            pub const PLL_SYS = @intToPtr(*volatile types.peripherals.PLL_SYS, 0x40028000);
+            pub const PLL_USB = @intToPtr(*volatile types.peripherals.PLL_SYS, 0x4002c000);
+            ///  Register block for busfabric control signals and performance counters
+            pub const BUSCTRL = @intToPtr(*volatile types.peripherals.BUSCTRL, 0x40030000);
+            pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x40034000);
+            pub const UART1 = @intToPtr(*volatile types.peripherals.UART0, 0x40038000);
+            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x4003c000);
+            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40040000);
+            ///  DW_apb_i2c address block
+            ///  List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
+            ///  IC_ULTRA_FAST_MODE ................ 0x0
+            ///  IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
+            ///  IC_UFM_SCL_LOW_COUNT .............. 0x0008
+            ///  IC_UFM_SCL_HIGH_COUNT ............. 0x0006
+            ///  IC_TX_TL .......................... 0x0
+            ///  IC_TX_CMD_BLOCK ................... 0x1
+            ///  IC_HAS_DMA ........................ 0x1
+            ///  IC_HAS_ASYNC_FIFO ................. 0x0
+            ///  IC_SMBUS_ARP ...................... 0x0
+            ///  IC_FIRST_DATA_BYTE_STATUS ......... 0x1
+            ///  IC_INTR_IO ........................ 0x1
+            ///  IC_MASTER_MODE .................... 0x1
+            ///  IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
+            ///  IC_INTR_POL ....................... 0x1
+            ///  IC_OPTIONAL_SAR ................... 0x0
+            ///  IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
+            ///  IC_DEFAULT_SLAVE_ADDR ............. 0x055
+            ///  IC_DEFAULT_HS_SPKLEN .............. 0x1
+            ///  IC_FS_SCL_HIGH_COUNT .............. 0x0006
+            ///  IC_HS_SCL_LOW_COUNT ............... 0x0008
+            ///  IC_DEVICE_ID_VALUE ................ 0x0
+            ///  IC_10BITADDR_MASTER ............... 0x0
+            ///  IC_CLK_FREQ_OPTIMIZATION .......... 0x0
+            ///  IC_DEFAULT_FS_SPKLEN .............. 0x7
+            ///  IC_ADD_ENCODED_PARAMS ............. 0x0
+            ///  IC_DEFAULT_SDA_HOLD ............... 0x000001
+            ///  IC_DEFAULT_SDA_SETUP .............. 0x64
+            ///  IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
+            ///  IC_CLOCK_PERIOD ................... 100
+            ///  IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
+            ///  IC_RESTART_EN ..................... 0x1
+            ///  IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
+            ///  IC_BUS_CLEAR_FEATURE .............. 0x0
+            ///  IC_CAP_LOADING .................... 100
+            ///  IC_FS_SCL_LOW_COUNT ............... 0x000d
+            ///  APB_DATA_WIDTH .................... 32
+            ///  IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+            ///  IC_SLV_DATA_NACK_ONLY ............. 0x1
+            ///  IC_10BITADDR_SLAVE ................ 0x0
+            ///  IC_CLK_TYPE ....................... 0x0
+            ///  IC_SMBUS_UDID_MSB ................. 0x0
+            ///  IC_SMBUS_SUSPEND_ALERT ............ 0x0
+            ///  IC_HS_SCL_HIGH_COUNT .............. 0x0006
+            ///  IC_SLV_RESTART_DET_EN ............. 0x1
+            ///  IC_SMBUS .......................... 0x0
+            ///  IC_OPTIONAL_SAR_DEFAULT ........... 0x0
+            ///  IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
+            ///  IC_USE_COUNTS ..................... 0x0
+            ///  IC_RX_BUFFER_DEPTH ................ 16
+            ///  IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+            ///  IC_RX_FULL_HLD_BUS_EN ............. 0x1
+            ///  IC_SLAVE_DISABLE .................. 0x1
+            ///  IC_RX_TL .......................... 0x0
+            ///  IC_DEVICE_ID ...................... 0x0
+            ///  IC_HC_COUNT_VALUES ................ 0x0
+            ///  I2C_DYNAMIC_TAR_UPDATE ............ 0
+            ///  IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
+            ///  IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
+            ///  IC_HS_MASTER_CODE ................. 0x1
+            ///  IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
+            ///  IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
+            ///  IC_SS_SCL_HIGH_COUNT .............. 0x0028
+            ///  IC_SS_SCL_LOW_COUNT ............... 0x002f
+            ///  IC_MAX_SPEED_MODE ................. 0x2
+            ///  IC_STAT_FOR_CLK_STRETCH ........... 0x0
+            ///  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
+            ///  IC_DEFAULT_UFM_SPKLEN ............. 0x1
+            ///  IC_TX_BUFFER_DEPTH ................ 16
+            pub const I2C0 = @intToPtr(*volatile types.peripherals.I2C0, 0x40044000);
+            ///  DW_apb_i2c address block
+            ///  List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
+            ///  IC_ULTRA_FAST_MODE ................ 0x0
+            ///  IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
+            ///  IC_UFM_SCL_LOW_COUNT .............. 0x0008
+            ///  IC_UFM_SCL_HIGH_COUNT ............. 0x0006
+            ///  IC_TX_TL .......................... 0x0
+            ///  IC_TX_CMD_BLOCK ................... 0x1
+            ///  IC_HAS_DMA ........................ 0x1
+            ///  IC_HAS_ASYNC_FIFO ................. 0x0
+            ///  IC_SMBUS_ARP ...................... 0x0
+            ///  IC_FIRST_DATA_BYTE_STATUS ......... 0x1
+            ///  IC_INTR_IO ........................ 0x1
+            ///  IC_MASTER_MODE .................... 0x1
+            ///  IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
+            ///  IC_INTR_POL ....................... 0x1
+            ///  IC_OPTIONAL_SAR ................... 0x0
+            ///  IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
+            ///  IC_DEFAULT_SLAVE_ADDR ............. 0x055
+            ///  IC_DEFAULT_HS_SPKLEN .............. 0x1
+            ///  IC_FS_SCL_HIGH_COUNT .............. 0x0006
+            ///  IC_HS_SCL_LOW_COUNT ............... 0x0008
+            ///  IC_DEVICE_ID_VALUE ................ 0x0
+            ///  IC_10BITADDR_MASTER ............... 0x0
+            ///  IC_CLK_FREQ_OPTIMIZATION .......... 0x0
+            ///  IC_DEFAULT_FS_SPKLEN .............. 0x7
+            ///  IC_ADD_ENCODED_PARAMS ............. 0x0
+            ///  IC_DEFAULT_SDA_HOLD ............... 0x000001
+            ///  IC_DEFAULT_SDA_SETUP .............. 0x64
+            ///  IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
+            ///  IC_CLOCK_PERIOD ................... 100
+            ///  IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
+            ///  IC_RESTART_EN ..................... 0x1
+            ///  IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
+            ///  IC_BUS_CLEAR_FEATURE .............. 0x0
+            ///  IC_CAP_LOADING .................... 100
+            ///  IC_FS_SCL_LOW_COUNT ............... 0x000d
+            ///  APB_DATA_WIDTH .................... 32
+            ///  IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+            ///  IC_SLV_DATA_NACK_ONLY ............. 0x1
+            ///  IC_10BITADDR_SLAVE ................ 0x0
+            ///  IC_CLK_TYPE ....................... 0x0
+            ///  IC_SMBUS_UDID_MSB ................. 0x0
+            ///  IC_SMBUS_SUSPEND_ALERT ............ 0x0
+            ///  IC_HS_SCL_HIGH_COUNT .............. 0x0006
+            ///  IC_SLV_RESTART_DET_EN ............. 0x1
+            ///  IC_SMBUS .......................... 0x0
+            ///  IC_OPTIONAL_SAR_DEFAULT ........... 0x0
+            ///  IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
+            ///  IC_USE_COUNTS ..................... 0x0
+            ///  IC_RX_BUFFER_DEPTH ................ 16
+            ///  IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+            ///  IC_RX_FULL_HLD_BUS_EN ............. 0x1
+            ///  IC_SLAVE_DISABLE .................. 0x1
+            ///  IC_RX_TL .......................... 0x0
+            ///  IC_DEVICE_ID ...................... 0x0
+            ///  IC_HC_COUNT_VALUES ................ 0x0
+            ///  I2C_DYNAMIC_TAR_UPDATE ............ 0
+            ///  IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
+            ///  IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
+            ///  IC_HS_MASTER_CODE ................. 0x1
+            ///  IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
+            ///  IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
+            ///  IC_SS_SCL_HIGH_COUNT .............. 0x0028
+            ///  IC_SS_SCL_LOW_COUNT ............... 0x002f
+            ///  IC_MAX_SPEED_MODE ................. 0x2
+            ///  IC_STAT_FOR_CLK_STRETCH ........... 0x0
+            ///  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
+            ///  IC_DEFAULT_UFM_SPKLEN ............. 0x1
+            ///  IC_TX_BUFFER_DEPTH ................ 16
+            pub const I2C1 = @intToPtr(*volatile types.peripherals.I2C0, 0x40048000);
+            ///  Control and data interface to SAR ADC
+            pub const ADC = @intToPtr(*volatile types.peripherals.ADC, 0x4004c000);
+            ///  Simple PWM
+            pub const PWM = @intToPtr(*volatile types.peripherals.PWM, 0x40050000);
+            ///  Controls time and alarms
+            ///  time is a 64 bit value indicating the time in usec since power-on
+            ///  timeh is the top 32 bits of time & timel is the bottom 32 bits
+            ///  to change time write to timelw before timehw
+            ///  to read time read from timelr before timehr
+            ///  An alarm is set by setting alarm_enable and writing to the corresponding alarm register
+            ///  When an alarm is pending, the corresponding alarm_running signal will be high
+            ///  An alarm can be cancelled before it has finished by clearing the alarm_enable
+            ///  When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared
+            ///  To clear the interrupt write a 1 to the corresponding alarm_irq
+            pub const TIMER = @intToPtr(*volatile types.peripherals.TIMER, 0x40054000);
+            pub const WATCHDOG = @intToPtr(*volatile types.peripherals.WATCHDOG, 0x40058000);
+            ///  Register block to control RTC
+            pub const RTC = @intToPtr(*volatile types.peripherals.RTC, 0x4005c000);
+            pub const ROSC = @intToPtr(*volatile types.peripherals.ROSC, 0x40060000);
+            ///  control and status for on-chip voltage regulator and chip level reset subsystem
+            pub const VREG_AND_CHIP_RESET = @intToPtr(*volatile types.peripherals.VREG_AND_CHIP_RESET, 0x40064000);
+            ///  Testbench manager. Allows the programmer to know what platform their software is running on.
+            pub const TBMAN = @intToPtr(*volatile types.peripherals.TBMAN, 0x4006c000);
+            ///  DMA with separate read and write masters
+            pub const DMA = @intToPtr(*volatile types.peripherals.DMA, 0x50000000);
+            ///  DPRAM layout for USB device.
+            pub const USBCTRL_DPRAM = @intToPtr(*volatile types.peripherals.USBCTRL_DPRAM, 0x50100000);
+            ///  USB FS/LS controller device registers
+            pub const USBCTRL_REGS = @intToPtr(*volatile types.peripherals.USBCTRL_REGS, 0x50110000);
+            ///  Programmable IO block
+            pub const PIO0 = @intToPtr(*volatile types.peripherals.PIO0, 0x50200000);
+            ///  Programmable IO block
+            pub const PIO1 = @intToPtr(*volatile types.peripherals.PIO0, 0x50300000);
+            ///  Single-cycle IO block
+            ///  Provides core-local and inter-core hardware for the two processors, with single-cycle access.
+            pub const SIO = @intToPtr(*volatile types.peripherals.SIO, 0xd0000000);
+            pub const PPB = @intToPtr(*volatile types.peripherals.PPB, 0xe0000000);
+            ///  System Tick Timer
+            pub const SysTick = @intToPtr(*volatile types.peripherals.SysTick, 0xe000e010);
+            ///  System Control Space
+            pub const NVIC = @intToPtr(*volatile types.peripherals.NVIC, 0xe000e100);
+            ///  System Control Space
+            pub const SCB = @intToPtr(*volatile types.peripherals.SCB, 0xe000ed00);
+        };
+    };
+};
+
+pub const types = struct {
+    pub const peripherals = struct {
+        ///  System Tick Timer
+        pub const SysTick = extern struct {
+            ///  SysTick Control and Status Register
+            CTRL: mmio.Mmio(packed struct(u32) {
+                ENABLE: u1,
+                TICKINT: u1,
+                CLKSOURCE: u1,
+                reserved16: u13,
+                COUNTFLAG: u1,
+                padding: u15,
+            }),
+            ///  SysTick Reload Value Register
+            LOAD: mmio.Mmio(packed struct(u32) {
+                RELOAD: u24,
+                padding: u8,
+            }),
+            ///  SysTick Current Value Register
+            VAL: mmio.Mmio(packed struct(u32) {
+                CURRENT: u24,
+                padding: u8,
+            }),
+            ///  SysTick Calibration Register
+            CALIB: mmio.Mmio(packed struct(u32) {
+                TENMS: u24,
+                reserved30: u6,
+                SKEW: u1,
+                NOREF: u1,
+            }),
+        };
+
+        ///  System Control Block
+        pub const SCB = extern struct {
+            CPUID: mmio.Mmio(packed struct(u32) {
+                REVISION: u4,
+                PARTNO: u12,
+                ARCHITECTURE: u4,
+                VARIANT: u4,
+                IMPLEMENTER: u8,
+            }),
+            ///  Interrupt Control and State Register
+            ICSR: mmio.Mmio(packed struct(u32) {
+                VECTACTIVE: u9,
+                reserved12: u3,
+                VECTPENDING: u9,
+                reserved22: u1,
+                ISRPENDING: u1,
+                ISRPREEMPT: u1,
+                reserved25: u1,
+                PENDSTCLR: u1,
+                PENDSTSET: u1,
+                PENDSVCLR: u1,
+                PENDSVSET: u1,
+                reserved31: u2,
+                NMIPENDSET: u1,
+            }),
+            ///  Vector Table Offset Register
+            VTOR: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                TBLOFF: u24,
+            }),
+            ///  Application Interrupt and Reset Control Register
+            AIRCR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                VECTCLRACTIVE: u1,
+                SYSRESETREQ: u1,
+                reserved15: u12,
+                ENDIANESS: u1,
+                VECTKEY: u16,
+            }),
+            ///  System Control Register
+            SCR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                SLEEPONEXIT: u1,
+                SLEEPDEEP: u1,
+                reserved4: u1,
+                SEVONPEND: u1,
+                padding: u27,
+            }),
+            ///  Configuration Control Register
+            CCR: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                UNALIGN_TRP: u1,
+                reserved9: u5,
+                STKALIGN: u1,
+                padding: u22,
+            }),
+            reserved28: [4]u8,
+            ///  System Handlers Priority Registers. [0] is RESERVED
+            SHP: u32,
+            reserved36: [4]u8,
+            ///  System Handler Control and State Register
+            SHCSR: mmio.Mmio(packed struct(u32) {
+                reserved15: u15,
+                SVCALLPENDED: u1,
+                padding: u16,
+            }),
+        };
+
+        ///  Nested Vectored Interrupt Controller
+        pub const NVIC = extern struct {
+            ///  Interrupt Set Enable Register
+            ISER: mmio.Mmio(packed struct(u32) {
+                TIMER_IRQ_0: u1,
+                TIMER_IRQ_1: u1,
+                TIMER_IRQ_2: u1,
+                TIMER_IRQ_3: u1,
+                PWM_IRQ_WRAP: u1,
+                USBCTRL_IRQ: u1,
+                XIP_IRQ: u1,
+                PIO0_IRQ_0: u1,
+                PIO0_IRQ_1: u1,
+                PIO1_IRQ_0: u1,
+                PIO1_IRQ_1: u1,
+                DMA_IRQ_0: u1,
+                DMA_IRQ_1: u1,
+                IO_IRQ_BANK0: u1,
+                IO_IRQ_QSPI: u1,
+                SIO_IRQ_PROC0: u1,
+                SIO_IRQ_PROC1: u1,
+                CLOCKS_IRQ: u1,
+                SPI0_IRQ: u1,
+                SPI1_IRQ: u1,
+                UART0_IRQ: u1,
+                UART1_IRQ: u1,
+                ADC_IRQ_FIFO: u1,
+                I2C0_IRQ: u1,
+                I2C1_IRQ: u1,
+                RTC_IRQ: u1,
+                padding: u6,
+            }),
+            reserved128: [124]u8,
+            ///  Interrupt Clear Enable Register
+            ICER: mmio.Mmio(packed struct(u32) {
+                TIMER_IRQ_0: u1,
+                TIMER_IRQ_1: u1,
+                TIMER_IRQ_2: u1,
+                TIMER_IRQ_3: u1,
+                PWM_IRQ_WRAP: u1,
+                USBCTRL_IRQ: u1,
+                XIP_IRQ: u1,
+                PIO0_IRQ_0: u1,
+                PIO0_IRQ_1: u1,
+                PIO1_IRQ_0: u1,
+                PIO1_IRQ_1: u1,
+                DMA_IRQ_0: u1,
+                DMA_IRQ_1: u1,
+                IO_IRQ_BANK0: u1,
+                IO_IRQ_QSPI: u1,
+                SIO_IRQ_PROC0: u1,
+                SIO_IRQ_PROC1: u1,
+                CLOCKS_IRQ: u1,
+                SPI0_IRQ: u1,
+                SPI1_IRQ: u1,
+                UART0_IRQ: u1,
+                UART1_IRQ: u1,
+                ADC_IRQ_FIFO: u1,
+                I2C0_IRQ: u1,
+                I2C1_IRQ: u1,
+                RTC_IRQ: u1,
+                padding: u6,
+            }),
+            reserved256: [124]u8,
+            ///  Interrupt Set Pending Register
+            ISPR: mmio.Mmio(packed struct(u32) {
+                TIMER_IRQ_0: u1,
+                TIMER_IRQ_1: u1,
+                TIMER_IRQ_2: u1,
+                TIMER_IRQ_3: u1,
+                PWM_IRQ_WRAP: u1,
+                USBCTRL_IRQ: u1,
+                XIP_IRQ: u1,
+                PIO0_IRQ_0: u1,
+                PIO0_IRQ_1: u1,
+                PIO1_IRQ_0: u1,
+                PIO1_IRQ_1: u1,
+                DMA_IRQ_0: u1,
+                DMA_IRQ_1: u1,
+                IO_IRQ_BANK0: u1,
+                IO_IRQ_QSPI: u1,
+                SIO_IRQ_PROC0: u1,
+                SIO_IRQ_PROC1: u1,
+                CLOCKS_IRQ: u1,
+                SPI0_IRQ: u1,
+                SPI1_IRQ: u1,
+                UART0_IRQ: u1,
+                UART1_IRQ: u1,
+                ADC_IRQ_FIFO: u1,
+                I2C0_IRQ: u1,
+                I2C1_IRQ: u1,
+                RTC_IRQ: u1,
+                padding: u6,
+            }),
+            reserved384: [124]u8,
+            ///  Interrupt Clear Pending Register
+            ICPR: mmio.Mmio(packed struct(u32) {
+                TIMER_IRQ_0: u1,
+                TIMER_IRQ_1: u1,
+                TIMER_IRQ_2: u1,
+                TIMER_IRQ_3: u1,
+                PWM_IRQ_WRAP: u1,
+                USBCTRL_IRQ: u1,
+                XIP_IRQ: u1,
+                PIO0_IRQ_0: u1,
+                PIO0_IRQ_1: u1,
+                PIO1_IRQ_0: u1,
+                PIO1_IRQ_1: u1,
+                DMA_IRQ_0: u1,
+                DMA_IRQ_1: u1,
+                IO_IRQ_BANK0: u1,
+                IO_IRQ_QSPI: u1,
+                SIO_IRQ_PROC0: u1,
+                SIO_IRQ_PROC1: u1,
+                CLOCKS_IRQ: u1,
+                SPI0_IRQ: u1,
+                SPI1_IRQ: u1,
+                UART0_IRQ: u1,
+                UART1_IRQ: u1,
+                ADC_IRQ_FIFO: u1,
+                I2C0_IRQ: u1,
+                I2C1_IRQ: u1,
+                RTC_IRQ: u1,
+                padding: u6,
+            }),
+            reserved768: [380]u8,
+            ///  Interrupt Priority Register
+            IPR0: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                TIMER_IRQ_0: u2,
+                reserved14: u6,
+                TIMER_IRQ_1: u2,
+                reserved22: u6,
+                TIMER_IRQ_2: u2,
+                reserved30: u6,
+                TIMER_IRQ_3: u2,
+            }),
+            ///  Interrupt Priority Register
+            IPR1: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                PWM_IRQ_WRAP: u2,
+                reserved14: u6,
+                USBCTRL_IRQ: u2,
+                reserved22: u6,
+                XIP_IRQ: u2,
+                reserved30: u6,
+                PIO0_IRQ_0: u2,
+            }),
+            ///  Interrupt Priority Register
+            IPR2: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                PIO0_IRQ_1: u2,
+                reserved14: u6,
+                PIO1_IRQ_0: u2,
+                reserved22: u6,
+                PIO1_IRQ_1: u2,
+                reserved30: u6,
+                DMA_IRQ_0: u2,
+            }),
+            ///  Interrupt Priority Register
+            IPR3: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                DMA_IRQ_1: u2,
+                reserved14: u6,
+                IO_IRQ_BANK0: u2,
+                reserved22: u6,
+                IO_IRQ_QSPI: u2,
+                reserved30: u6,
+                SIO_IRQ_PROC0: u2,
+            }),
+            ///  Interrupt Priority Register
+            IPR4: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                SIO_IRQ_PROC1: u2,
+                reserved14: u6,
+                CLOCKS_IRQ: u2,
+                reserved22: u6,
+                SPI0_IRQ: u2,
+                reserved30: u6,
+                SPI1_IRQ: u2,
+            }),
+            ///  Interrupt Priority Register
+            IPR5: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                UART0_IRQ: u2,
+                reserved14: u6,
+                UART1_IRQ: u2,
+                reserved22: u6,
+                ADC_IRQ_FIFO: u2,
+                reserved30: u6,
+                I2C0_IRQ: u2,
+            }),
+            ///  Interrupt Priority Register
+            IPR6: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                I2C1_IRQ: u2,
+                reserved14: u6,
+                RTC_IRQ: u2,
+                padding: u16,
+            }),
+            ///  Interrupt Priority Register
+            IPR7: u32,
+        };
+
+        ///  Memory Protection Unit
+        pub const MPU = extern struct {
+            ///  MPU Type Register
+            TYPE: mmio.Mmio(packed struct(u32) {
+                SEPARATE: u1,
+                reserved8: u7,
+                DREGION: u8,
+                IREGION: u8,
+                padding: u8,
+            }),
+            ///  MPU Control Register
+            CTRL: mmio.Mmio(packed struct(u32) {
+                ENABLE: u1,
+                HFNMIENA: u1,
+                PRIVDEFENA: u1,
+                padding: u29,
+            }),
+            ///  MPU Region RNRber Register
+            RNR: mmio.Mmio(packed struct(u32) {
+                REGION: u8,
+                padding: u24,
+            }),
+            ///  MPU Region Base Address Register
+            RBAR: mmio.Mmio(packed struct(u32) {
+                REGION: u4,
+                VALID: u1,
+                reserved8: u3,
+                ADDR: u24,
+            }),
+            ///  MPU Region Attribute and Size Register
+            RASR: mmio.Mmio(packed struct(u32) {
+                ENABLE: u1,
+                SIZE: u5,
+                reserved8: u2,
+                SRD: u8,
+                B: u1,
+                C: u1,
+                S: u1,
+                TEX: u3,
+                reserved24: u2,
+                AP: u3,
+                reserved28: u1,
+                XN: u1,
+                padding: u3,
+            }),
+        };
+
+        ///  QSPI flash execute-in-place block
+        pub const XIP_CTRL = extern struct {
+            ///  Cache control
+            CTRL: mmio.Mmio(packed struct(u32) {
+                ///  When 1, enable the cache. When the cache is disabled, all XIP accesses
+                ///  will go straight to the flash, without querying the cache. When enabled,
+                ///  cacheable XIP accesses will query the cache, and the flash will
+                ///  not be accessed if the tag matches and the valid bit is set.
+                ///  If the cache is enabled, cache-as-SRAM accesses have no effect on the
+                ///  cache data RAM, and will produce a bus error response.
+                EN: u1,
+                ///  When 1, writes to any alias other than 0x0 (caching, allocating)
+                ///  will produce a bus fault. When 0, these writes are silently ignored.
+                ///  In either case, writes to the 0x0 alias will deallocate on tag match,
+                ///  as usual.
+                ERR_BADWRITE: u1,
+                reserved3: u1,
+                ///  When 1, the cache memories are powered down. They retain state,
+                ///  but can not be accessed. This reduces static power dissipation.
+                ///  Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot
+                ///  be enabled when powered down.
+                ///  Cache-as-SRAM accesses will produce a bus error response when
+                ///  the cache is powered down.
+                POWER_DOWN: u1,
+                padding: u28,
+            }),
+            ///  Cache Flush control
+            FLUSH: mmio.Mmio(packed struct(u32) {
+                ///  Write 1 to flush the cache. This clears the tag memory, but
+                ///  the data memory retains its contents. (This means cache-as-SRAM
+                ///  contents is not affected by flush or reset.)
+                ///  Reading will hold the bus (stall the processor) until the flush
+                ///  completes. Alternatively STAT can be polled until completion.
+                FLUSH: u1,
+                padding: u31,
+            }),
+            ///  Cache Status
+            STAT: mmio.Mmio(packed struct(u32) {
+                ///  Reads as 0 while a cache flush is in progress, and 1 otherwise.
+                ///  The cache is flushed whenever the XIP block is reset, and also
+                ///  when requested via the FLUSH register.
+                FLUSH_READY: u1,
+                ///  When 1, indicates the XIP streaming FIFO is completely empty.
+                FIFO_EMPTY: u1,
+                ///  When 1, indicates the XIP streaming FIFO is completely full.
+                ///  The streaming FIFO is 2 entries deep, so the full and empty
+                ///  flag allow its level to be ascertained.
+                FIFO_FULL: u1,
+                padding: u29,
+            }),
+            ///  Cache Hit counter
+            ///  A 32 bit saturating counter that increments upon each cache hit,
+            ///  i.e. when an XIP access is serviced directly from cached data.
+            ///  Write any value to clear.
+            CTR_HIT: u32,
+            ///  Cache Access counter
+            ///  A 32 bit saturating counter that increments upon each XIP access,
+            ///  whether the cache is hit or not. This includes noncacheable accesses.
+            ///  Write any value to clear.
+            CTR_ACC: u32,
+            ///  FIFO stream address
+            STREAM_ADDR: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  The address of the next word to be streamed from flash to the streaming FIFO.
+                ///  Increments automatically after each flash access.
+                ///  Write the initial access address here before starting a streaming read.
+                STREAM_ADDR: u30,
+            }),
+            ///  FIFO stream control
+            STREAM_CTR: mmio.Mmio(packed struct(u32) {
+                ///  Write a nonzero value to start a streaming read. This will then
+                ///  progress in the background, using flash idle cycles to transfer
+                ///  a linear data block from flash to the streaming FIFO.
+                ///  Decrements automatically (1 at a time) as the stream
+                ///  progresses, and halts on reaching 0.
+                ///  Write 0 to halt an in-progress stream, and discard any in-flight
+                ///  read, so that a new stream can immediately be started (after
+                ///  draining the FIFO and reinitialising STREAM_ADDR)
+                STREAM_CTR: u22,
+                padding: u10,
+            }),
+            ///  FIFO stream data
+            ///  Streamed data is buffered here, for retrieval by the system DMA.
+            ///  This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing
+            ///  the DMA to bus stalls caused by other XIP traffic.
+            STREAM_FIFO: u32,
+        };
+
+        ///  DW_apb_ssi has the following features:
+        ///  * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.
+        ///  * APB3 and APB4 protocol support.
+        ///  * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.
+        ///  * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.
+        ///  * Programmable Dual/Quad/Octal SPI support in Master Mode.
+        ///  * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.
+        ///  * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.
+        ///  * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.
+        ///  * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.
+        ///  * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.
+        ///  * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.
+        ///  * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.
+        ///  * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.
+        ///  * Programmable features:
+        ///  - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.
+        ///  - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.
+        ///  - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.
+        ///  * Configured features:
+        ///  - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.
+        ///  - 1 slave select output.
+        ///  - Hardware slave-select – Dedicated hardware slave-select line.
+        ///  - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.
+        ///  - Interrupt polarity – active high interrupt lines.
+        ///  - Serial clock polarity – low serial-clock polarity directly after reset.
+        ///  - Serial clock phase – capture on first edge of serial-clock directly after reset.
+        pub const XIP_SSI = extern struct {
+            ///  Control register 0
+            CTRLR0: mmio.Mmio(packed struct(u32) {
+                ///  Data frame size
+                DFS: u4,
+                ///  Frame format
+                FRF: u2,
+                ///  Serial clock phase
+                SCPH: u1,
+                ///  Serial clock polarity
+                SCPOL: u1,
+                ///  Transfer mode
+                TMOD: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Both transmit and receive
+                        TX_AND_RX = 0x0,
+                        ///  Transmit only (not for FRF == 0, standard SPI mode)
+                        TX_ONLY = 0x1,
+                        ///  Receive only (not for FRF == 0, standard SPI mode)
+                        RX_ONLY = 0x2,
+                        ///  EEPROM read mode (TX then RX; RX starts after control data TX'd)
+                        EEPROM_READ = 0x3,
+                    },
+                },
+                ///  Slave output enable
+                SLV_OE: u1,
+                ///  Shift register loop (test mode)
+                SRL: u1,
+                ///  Control frame size
+                ///  Value of n -> n+1 clocks per frame.
+                CFS: u4,
+                ///  Data frame size in 32b transfer mode
+                ///  Value of n -> n+1 clocks per frame.
+                DFS_32: u5,
+                ///  SPI frame format
+                SPI_FRF: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex
+                        STD = 0x0,
+                        ///  Dual-SPI frame format; two bits per SCK, half-duplex
+                        DUAL = 0x1,
+                        ///  Quad-SPI frame format; four bits per SCK, half-duplex
+                        QUAD = 0x2,
+                        _,
+                    },
+                },
+                reserved24: u1,
+                ///  Slave select toggle enable
+                SSTE: u1,
+                padding: u7,
+            }),
+            ///  Master Control register 1
+            CTRLR1: mmio.Mmio(packed struct(u32) {
+                ///  Number of data frames
+                NDF: u16,
+                padding: u16,
+            }),
+            ///  SSI Enable
+            SSIENR: mmio.Mmio(packed struct(u32) {
+                ///  SSI enable
+                SSI_EN: u1,
+                padding: u31,
+            }),
+            ///  Microwire Control
+            MWCR: mmio.Mmio(packed struct(u32) {
+                ///  Microwire transfer mode
+                MWMOD: u1,
+                ///  Microwire control
+                MDD: u1,
+                ///  Microwire handshaking
+                MHS: u1,
+                padding: u29,
+            }),
+            ///  Slave enable
+            SER: mmio.Mmio(packed struct(u32) {
+                ///  For each bit:
+                ///  0 -> slave not selected
+                ///  1 -> slave selected
+                SER: u1,
+                padding: u31,
+            }),
+            ///  Baud rate
+            BAUDR: mmio.Mmio(packed struct(u32) {
+                ///  SSI clock divider
+                SCKDV: u16,
+                padding: u16,
+            }),
+            ///  TX FIFO threshold level
+            TXFTLR: mmio.Mmio(packed struct(u32) {
+                ///  Transmit FIFO threshold
+                TFT: u8,
+                padding: u24,
+            }),
+            ///  RX FIFO threshold level
+            RXFTLR: mmio.Mmio(packed struct(u32) {
+                ///  Receive FIFO threshold
+                RFT: u8,
+                padding: u24,
+            }),
+            ///  TX FIFO level
+            TXFLR: mmio.Mmio(packed struct(u32) {
+                ///  Transmit FIFO level
+                TFTFL: u8,
+                padding: u24,
+            }),
+            ///  RX FIFO level
+            RXFLR: mmio.Mmio(packed struct(u32) {
+                ///  Receive FIFO level
+                RXTFL: u8,
+                padding: u24,
+            }),
+            ///  Status register
+            SR: mmio.Mmio(packed struct(u32) {
+                ///  SSI busy flag
+                BUSY: u1,
+                ///  Transmit FIFO not full
+                TFNF: u1,
+                ///  Transmit FIFO empty
+                TFE: u1,
+                ///  Receive FIFO not empty
+                RFNE: u1,
+                ///  Receive FIFO full
+                RFF: u1,
+                ///  Transmission error
+                TXE: u1,
+                ///  Data collision error
+                DCOL: u1,
+                padding: u25,
+            }),
+            ///  Interrupt mask
+            IMR: mmio.Mmio(packed struct(u32) {
+                ///  Transmit FIFO empty interrupt mask
+                TXEIM: u1,
+                ///  Transmit FIFO overflow interrupt mask
+                TXOIM: u1,
+                ///  Receive FIFO underflow interrupt mask
+                RXUIM: u1,
+                ///  Receive FIFO overflow interrupt mask
+                RXOIM: u1,
+                ///  Receive FIFO full interrupt mask
+                RXFIM: u1,
+                ///  Multi-master contention interrupt mask
+                MSTIM: u1,
+                padding: u26,
+            }),
+            ///  Interrupt status
+            ISR: mmio.Mmio(packed struct(u32) {
+                ///  Transmit FIFO empty interrupt status
+                TXEIS: u1,
+                ///  Transmit FIFO overflow interrupt status
+                TXOIS: u1,
+                ///  Receive FIFO underflow interrupt status
+                RXUIS: u1,
+                ///  Receive FIFO overflow interrupt status
+                RXOIS: u1,
+                ///  Receive FIFO full interrupt status
+                RXFIS: u1,
+                ///  Multi-master contention interrupt status
+                MSTIS: u1,
+                padding: u26,
+            }),
+            ///  Raw interrupt status
+            RISR: mmio.Mmio(packed struct(u32) {
+                ///  Transmit FIFO empty raw interrupt status
+                TXEIR: u1,
+                ///  Transmit FIFO overflow raw interrupt status
+                TXOIR: u1,
+                ///  Receive FIFO underflow raw interrupt status
+                RXUIR: u1,
+                ///  Receive FIFO overflow raw interrupt status
+                RXOIR: u1,
+                ///  Receive FIFO full raw interrupt status
+                RXFIR: u1,
+                ///  Multi-master contention raw interrupt status
+                MSTIR: u1,
+                padding: u26,
+            }),
+            ///  TX FIFO overflow interrupt clear
+            TXOICR: mmio.Mmio(packed struct(u32) {
+                ///  Clear-on-read transmit FIFO overflow interrupt
+                TXOICR: u1,
+                padding: u31,
+            }),
+            ///  RX FIFO overflow interrupt clear
+            RXOICR: mmio.Mmio(packed struct(u32) {
+                ///  Clear-on-read receive FIFO overflow interrupt
+                RXOICR: u1,
+                padding: u31,
+            }),
+            ///  RX FIFO underflow interrupt clear
+            RXUICR: mmio.Mmio(packed struct(u32) {
+                ///  Clear-on-read receive FIFO underflow interrupt
+                RXUICR: u1,
+                padding: u31,
+            }),
+            ///  Multi-master interrupt clear
+            MSTICR: mmio.Mmio(packed struct(u32) {
+                ///  Clear-on-read multi-master contention interrupt
+                MSTICR: u1,
+                padding: u31,
+            }),
+            ///  Interrupt clear
+            ICR: mmio.Mmio(packed struct(u32) {
+                ///  Clear-on-read all active interrupts
+                ICR: u1,
+                padding: u31,
+            }),
+            ///  DMA control
+            DMACR: mmio.Mmio(packed struct(u32) {
+                ///  Receive DMA enable
+                RDMAE: u1,
+                ///  Transmit DMA enable
+                TDMAE: u1,
+                padding: u30,
+            }),
+            ///  DMA TX data level
+            DMATDLR: mmio.Mmio(packed struct(u32) {
+                ///  Transmit data watermark level
+                DMATDL: u8,
+                padding: u24,
+            }),
+            ///  DMA RX data level
+            DMARDLR: mmio.Mmio(packed struct(u32) {
+                ///  Receive data watermark level (DMARDLR+1)
+                DMARDL: u8,
+                padding: u24,
+            }),
+            ///  Identification register
+            IDR: mmio.Mmio(packed struct(u32) {
+                ///  Peripheral dentification code
+                IDCODE: u32,
+            }),
+            ///  Version ID
+            SSI_VERSION_ID: mmio.Mmio(packed struct(u32) {
+                ///  SNPS component version (format X.YY)
+                SSI_COMP_VERSION: u32,
+            }),
+            ///  Data Register 0 (of 36)
+            DR0: mmio.Mmio(packed struct(u32) {
+                ///  First data register of 36
+                DR: u32,
+            }),
+            reserved240: [140]u8,
+            ///  RX sample delay
+            RX_SAMPLE_DLY: mmio.Mmio(packed struct(u32) {
+                ///  RXD sample delay (in SCLK cycles)
+                RSD: u8,
+                padding: u24,
+            }),
+            ///  SPI control
+            SPI_CTRLR0: mmio.Mmio(packed struct(u32) {
+                ///  Address and instruction transfer format
+                TRANS_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Command and address both in standard SPI frame format
+                        @"1C1A" = 0x0,
+                        ///  Command in standard SPI format, address in format specified by FRF
+                        @"1C2A" = 0x1,
+                        ///  Command and address both in format specified by FRF (e.g. Dual-SPI)
+                        @"2C2A" = 0x2,
+                        _,
+                    },
+                },
+                ///  Address length (0b-60b in 4b increments)
+                ADDR_L: u4,
+                reserved8: u2,
+                ///  Instruction length (0/4/8/16b)
+                INST_L: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  No instruction
+                        NONE = 0x0,
+                        ///  4-bit instruction
+                        @"4B" = 0x1,
+                        ///  8-bit instruction
+                        @"8B" = 0x2,
+                        ///  16-bit instruction
+                        @"16B" = 0x3,
+                    },
+                },
+                reserved11: u1,
+                ///  Wait cycles between control frame transmit and data reception (in SCLK cycles)
+                WAIT_CYCLES: u5,
+                ///  SPI DDR transfer enable
+                SPI_DDR_EN: u1,
+                ///  Instruction DDR transfer enable
+                INST_DDR_EN: u1,
+                ///  Read data strobe enable
+                SPI_RXDS_EN: u1,
+                reserved24: u5,
+                ///  SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)
+                XIP_CMD: u8,
+            }),
+            ///  TX drive edge
+            TXD_DRIVE_EDGE: mmio.Mmio(packed struct(u32) {
+                ///  TXD drive edge
+                TDE: u8,
+                padding: u24,
+            }),
+        };
+
+        pub const SYSINFO = extern struct {
+            ///  JEDEC JEP-106 compliant chip identifier.
+            CHIP_ID: mmio.Mmio(packed struct(u32) {
+                MANUFACTURER: u12,
+                PART: u16,
+                REVISION: u4,
+            }),
+            ///  Platform register. Allows software to know what environment it is running in.
+            PLATFORM: mmio.Mmio(packed struct(u32) {
+                FPGA: u1,
+                ASIC: u1,
+                padding: u30,
+            }),
+            reserved64: [56]u8,
+            ///  Git hash of the chip source. Used to identify chip version.
+            GITREF_RP2040: u32,
+        };
+
+        ///  Register block for various chip control signals
+        pub const SYSCFG = extern struct {
+            ///  Processor core 0 NMI source mask
+            ///  Set a bit high to enable NMI from that IRQ
+            PROC0_NMI_MASK: u32,
+            ///  Processor core 1 NMI source mask
+            ///  Set a bit high to enable NMI from that IRQ
+            PROC1_NMI_MASK: u32,
+            ///  Configuration for processors
+            PROC_CONFIG: mmio.Mmio(packed struct(u32) {
+                ///  Indication that proc0 has halted
+                PROC0_HALTED: u1,
+                ///  Indication that proc1 has halted
+                PROC1_HALTED: u1,
+                reserved24: u22,
+                ///  Configure proc0 DAP instance ID.
+                ///  Recommend that this is NOT changed until you require debug access in multi-chip environment
+                ///  WARNING: do not set to 15 as this is reserved for RescueDP
+                PROC0_DAP_INSTID: u4,
+                ///  Configure proc1 DAP instance ID.
+                ///  Recommend that this is NOT changed until you require debug access in multi-chip environment
+                ///  WARNING: do not set to 15 as this is reserved for RescueDP
+                PROC1_DAP_INSTID: u4,
+            }),
+            ///  For each bit, if 1, bypass the input synchronizer between that GPIO
+            ///  and the GPIO input register in the SIO. The input synchronizers should
+            ///  generally be unbypassed, to avoid injecting metastabilities into processors.
+            ///  If you're feeling brave, you can bypass to save two cycles of input
+            ///  latency. This register applies to GPIO 0...29.
+            PROC_IN_SYNC_BYPASS: mmio.Mmio(packed struct(u32) {
+                PROC_IN_SYNC_BYPASS: u30,
+                padding: u2,
+            }),
+            ///  For each bit, if 1, bypass the input synchronizer between that GPIO
+            ///  and the GPIO input register in the SIO. The input synchronizers should
+            ///  generally be unbypassed, to avoid injecting metastabilities into processors.
+            ///  If you're feeling brave, you can bypass to save two cycles of input
+            ///  latency. This register applies to GPIO 30...35 (the QSPI IOs).
+            PROC_IN_SYNC_BYPASS_HI: mmio.Mmio(packed struct(u32) {
+                PROC_IN_SYNC_BYPASS_HI: u6,
+                padding: u26,
+            }),
+            ///  Directly control the SWD debug port of either processor
+            DBGFORCE: mmio.Mmio(packed struct(u32) {
+                ///  Observe the value of processor 0 SWDIO output.
+                PROC0_SWDO: u1,
+                ///  Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
+                PROC0_SWDI: u1,
+                ///  Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
+                PROC0_SWCLK: u1,
+                ///  Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.
+                PROC0_ATTACH: u1,
+                ///  Observe the value of processor 1 SWDIO output.
+                PROC1_SWDO: u1,
+                ///  Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
+                PROC1_SWDI: u1,
+                ///  Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
+                PROC1_SWCLK: u1,
+                ///  Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.
+                PROC1_ATTACH: u1,
+                padding: u24,
+            }),
+            ///  Control power downs to memories. Set high to power down memories.
+            ///  Use with extreme caution
+            MEMPOWERDOWN: mmio.Mmio(packed struct(u32) {
+                SRAM0: u1,
+                SRAM1: u1,
+                SRAM2: u1,
+                SRAM3: u1,
+                SRAM4: u1,
+                SRAM5: u1,
+                USB: u1,
+                ROM: u1,
+                padding: u24,
+            }),
+        };
+
+        pub const CLOCKS = extern struct {
+            ///  Clock control, can be changed on-the-fly (except for auxsrc)
+            CLK_GPOUT0_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved5: u5,
+                ///  Selects the auxiliary clock source, will glitch when switching
+                AUXSRC: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        clksrc_pll_sys = 0x0,
+                        clksrc_gpin0 = 0x1,
+                        clksrc_gpin1 = 0x2,
+                        clksrc_pll_usb = 0x3,
+                        rosc_clksrc = 0x4,
+                        xosc_clksrc = 0x5,
+                        clk_sys = 0x6,
+                        clk_usb = 0x7,
+                        clk_adc = 0x8,
+                        clk_rtc = 0x9,
+                        clk_ref = 0xa,
+                        _,
+                    },
+                },
+                reserved10: u1,
+                ///  Asynchronously kills the clock generator
+                KILL: u1,
+                ///  Starts and stops the clock generator cleanly
+                ENABLE: u1,
+                ///  Enables duty cycle correction for odd divisors
+                DC50: u1,
+                reserved16: u3,
+                ///  This delays the enable signal by up to 3 cycles of the input clock
+                ///  This must be set before the clock is enabled to have any effect
+                PHASE: u2,
+                reserved20: u2,
+                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
+                ///  This can be done at any time
+                NUDGE: u1,
+                padding: u11,
+            }),
+            ///  Clock divisor, can be changed on-the-fly
+            CLK_GPOUT0_DIV: mmio.Mmio(packed struct(u32) {
+                ///  Fractional component of the divisor
+                FRAC: u8,
+                ///  Integer component of the divisor, 0 -> divide by 2^16
+                INT: u24,
+            }),
+            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
+            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
+            CLK_GPOUT0_SELECTED: u32,
+            ///  Clock control, can be changed on-the-fly (except for auxsrc)
+            CLK_GPOUT1_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved5: u5,
+                ///  Selects the auxiliary clock source, will glitch when switching
+                AUXSRC: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        clksrc_pll_sys = 0x0,
+                        clksrc_gpin0 = 0x1,
+                        clksrc_gpin1 = 0x2,
+                        clksrc_pll_usb = 0x3,
+                        rosc_clksrc = 0x4,
+                        xosc_clksrc = 0x5,
+                        clk_sys = 0x6,
+                        clk_usb = 0x7,
+                        clk_adc = 0x8,
+                        clk_rtc = 0x9,
+                        clk_ref = 0xa,
+                        _,
+                    },
+                },
+                reserved10: u1,
+                ///  Asynchronously kills the clock generator
+                KILL: u1,
+                ///  Starts and stops the clock generator cleanly
+                ENABLE: u1,
+                ///  Enables duty cycle correction for odd divisors
+                DC50: u1,
+                reserved16: u3,
+                ///  This delays the enable signal by up to 3 cycles of the input clock
+                ///  This must be set before the clock is enabled to have any effect
+                PHASE: u2,
+                reserved20: u2,
+                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
+                ///  This can be done at any time
+                NUDGE: u1,
+                padding: u11,
+            }),
+            ///  Clock divisor, can be changed on-the-fly
+            CLK_GPOUT1_DIV: mmio.Mmio(packed struct(u32) {
+                ///  Fractional component of the divisor
+                FRAC: u8,
+                ///  Integer component of the divisor, 0 -> divide by 2^16
+                INT: u24,
+            }),
+            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
+            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
+            CLK_GPOUT1_SELECTED: u32,
+            ///  Clock control, can be changed on-the-fly (except for auxsrc)
+            CLK_GPOUT2_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved5: u5,
+                ///  Selects the auxiliary clock source, will glitch when switching
+                AUXSRC: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        clksrc_pll_sys = 0x0,
+                        clksrc_gpin0 = 0x1,
+                        clksrc_gpin1 = 0x2,
+                        clksrc_pll_usb = 0x3,
+                        rosc_clksrc_ph = 0x4,
+                        xosc_clksrc = 0x5,
+                        clk_sys = 0x6,
+                        clk_usb = 0x7,
+                        clk_adc = 0x8,
+                        clk_rtc = 0x9,
+                        clk_ref = 0xa,
+                        _,
+                    },
+                },
+                reserved10: u1,
+                ///  Asynchronously kills the clock generator
+                KILL: u1,
+                ///  Starts and stops the clock generator cleanly
+                ENABLE: u1,
+                ///  Enables duty cycle correction for odd divisors
+                DC50: u1,
+                reserved16: u3,
+                ///  This delays the enable signal by up to 3 cycles of the input clock
+                ///  This must be set before the clock is enabled to have any effect
+                PHASE: u2,
+                reserved20: u2,
+                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
+                ///  This can be done at any time
+                NUDGE: u1,
+                padding: u11,
+            }),
+            ///  Clock divisor, can be changed on-the-fly
+            CLK_GPOUT2_DIV: mmio.Mmio(packed struct(u32) {
+                ///  Fractional component of the divisor
+                FRAC: u8,
+                ///  Integer component of the divisor, 0 -> divide by 2^16
+                INT: u24,
+            }),
+            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
+            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
+            CLK_GPOUT2_SELECTED: u32,
+            ///  Clock control, can be changed on-the-fly (except for auxsrc)
+            CLK_GPOUT3_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved5: u5,
+                ///  Selects the auxiliary clock source, will glitch when switching
+                AUXSRC: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        clksrc_pll_sys = 0x0,
+                        clksrc_gpin0 = 0x1,
+                        clksrc_gpin1 = 0x2,
+                        clksrc_pll_usb = 0x3,
+                        rosc_clksrc_ph = 0x4,
+                        xosc_clksrc = 0x5,
+                        clk_sys = 0x6,
+                        clk_usb = 0x7,
+                        clk_adc = 0x8,
+                        clk_rtc = 0x9,
+                        clk_ref = 0xa,
+                        _,
+                    },
+                },
+                reserved10: u1,
+                ///  Asynchronously kills the clock generator
+                KILL: u1,
+                ///  Starts and stops the clock generator cleanly
+                ENABLE: u1,
+                ///  Enables duty cycle correction for odd divisors
+                DC50: u1,
+                reserved16: u3,
+                ///  This delays the enable signal by up to 3 cycles of the input clock
+                ///  This must be set before the clock is enabled to have any effect
+                PHASE: u2,
+                reserved20: u2,
+                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
+                ///  This can be done at any time
+                NUDGE: u1,
+                padding: u11,
+            }),
+            ///  Clock divisor, can be changed on-the-fly
+            CLK_GPOUT3_DIV: mmio.Mmio(packed struct(u32) {
+                ///  Fractional component of the divisor
+                FRAC: u8,
+                ///  Integer component of the divisor, 0 -> divide by 2^16
+                INT: u24,
+            }),
+            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
+            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
+            CLK_GPOUT3_SELECTED: u32,
+            ///  Clock control, can be changed on-the-fly (except for auxsrc)
+            CLK_REF_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Selects the clock source glitchlessly, can be changed on-the-fly
+                SRC: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        rosc_clksrc_ph = 0x0,
+                        clksrc_clk_ref_aux = 0x1,
+                        xosc_clksrc = 0x2,
+                        _,
+                    },
+                },
+                reserved5: u3,
+                ///  Selects the auxiliary clock source, will glitch when switching
+                AUXSRC: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        clksrc_pll_usb = 0x0,
+                        clksrc_gpin0 = 0x1,
+                        clksrc_gpin1 = 0x2,
+                        _,
+                    },
+                },
+                padding: u25,
+            }),
+            ///  Clock divisor, can be changed on-the-fly
+            CLK_REF_DIV: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Integer component of the divisor, 0 -> divide by 2^16
+                INT: u2,
+                padding: u22,
+            }),
+            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
+            ///  The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.
+            CLK_REF_SELECTED: u32,
+            ///  Clock control, can be changed on-the-fly (except for auxsrc)
+            CLK_SYS_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Selects the clock source glitchlessly, can be changed on-the-fly
+                SRC: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        clk_ref = 0x0,
+                        clksrc_clk_sys_aux = 0x1,
+                    },
+                },
+                reserved5: u4,
+                ///  Selects the auxiliary clock source, will glitch when switching
+                AUXSRC: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        clksrc_pll_sys = 0x0,
+                        clksrc_pll_usb = 0x1,
+                        rosc_clksrc = 0x2,
+                        xosc_clksrc = 0x3,
+                        clksrc_gpin0 = 0x4,
+                        clksrc_gpin1 = 0x5,
+                        _,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Clock divisor, can be changed on-the-fly
+            CLK_SYS_DIV: mmio.Mmio(packed struct(u32) {
+                ///  Fractional component of the divisor
+                FRAC: u8,
+                ///  Integer component of the divisor, 0 -> divide by 2^16
+                INT: u24,
+            }),
+            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
+            ///  The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.
+            CLK_SYS_SELECTED: u32,
+            ///  Clock control, can be changed on-the-fly (except for auxsrc)
+            CLK_PERI_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved5: u5,
+                ///  Selects the auxiliary clock source, will glitch when switching
+                AUXSRC: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        clk_sys = 0x0,
+                        clksrc_pll_sys = 0x1,
+                        clksrc_pll_usb = 0x2,
+                        rosc_clksrc_ph = 0x3,
+                        xosc_clksrc = 0x4,
+                        clksrc_gpin0 = 0x5,
+                        clksrc_gpin1 = 0x6,
+                        _,
+                    },
+                },
+                reserved10: u2,
+                ///  Asynchronously kills the clock generator
+                KILL: u1,
+                ///  Starts and stops the clock generator cleanly
+                ENABLE: u1,
+                padding: u20,
+            }),
+            reserved80: [4]u8,
+            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
+            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
+            CLK_PERI_SELECTED: u32,
+            ///  Clock control, can be changed on-the-fly (except for auxsrc)
+            CLK_USB_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved5: u5,
+                ///  Selects the auxiliary clock source, will glitch when switching
+                AUXSRC: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        clksrc_pll_usb = 0x0,
+                        clksrc_pll_sys = 0x1,
+                        rosc_clksrc_ph = 0x2,
+                        xosc_clksrc = 0x3,
+                        clksrc_gpin0 = 0x4,
+                        clksrc_gpin1 = 0x5,
+                        _,
+                    },
+                },
+                reserved10: u2,
+                ///  Asynchronously kills the clock generator
+                KILL: u1,
+                ///  Starts and stops the clock generator cleanly
+                ENABLE: u1,
+                reserved16: u4,
+                ///  This delays the enable signal by up to 3 cycles of the input clock
+                ///  This must be set before the clock is enabled to have any effect
+                PHASE: u2,
+                reserved20: u2,
+                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
+                ///  This can be done at any time
+                NUDGE: u1,
+                padding: u11,
+            }),
+            ///  Clock divisor, can be changed on-the-fly
+            CLK_USB_DIV: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Integer component of the divisor, 0 -> divide by 2^16
+                INT: u2,
+                padding: u22,
+            }),
+            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
+            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
+            CLK_USB_SELECTED: u32,
+            ///  Clock control, can be changed on-the-fly (except for auxsrc)
+            CLK_ADC_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved5: u5,
+                ///  Selects the auxiliary clock source, will glitch when switching
+                AUXSRC: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        clksrc_pll_usb = 0x0,
+                        clksrc_pll_sys = 0x1,
+                        rosc_clksrc_ph = 0x2,
+                        xosc_clksrc = 0x3,
+                        clksrc_gpin0 = 0x4,
+                        clksrc_gpin1 = 0x5,
+                        _,
+                    },
+                },
+                reserved10: u2,
+                ///  Asynchronously kills the clock generator
+                KILL: u1,
+                ///  Starts and stops the clock generator cleanly
+                ENABLE: u1,
+                reserved16: u4,
+                ///  This delays the enable signal by up to 3 cycles of the input clock
+                ///  This must be set before the clock is enabled to have any effect
+                PHASE: u2,
+                reserved20: u2,
+                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
+                ///  This can be done at any time
+                NUDGE: u1,
+                padding: u11,
+            }),
+            ///  Clock divisor, can be changed on-the-fly
+            CLK_ADC_DIV: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Integer component of the divisor, 0 -> divide by 2^16
+                INT: u2,
+                padding: u22,
+            }),
+            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
+            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
+            CLK_ADC_SELECTED: u32,
+            ///  Clock control, can be changed on-the-fly (except for auxsrc)
+            CLK_RTC_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved5: u5,
+                ///  Selects the auxiliary clock source, will glitch when switching
+                AUXSRC: packed union {
+                    raw: u3,
+                    value: enum(u3) {
+                        clksrc_pll_usb = 0x0,
+                        clksrc_pll_sys = 0x1,
+                        rosc_clksrc_ph = 0x2,
+                        xosc_clksrc = 0x3,
+                        clksrc_gpin0 = 0x4,
+                        clksrc_gpin1 = 0x5,
+                        _,
+                    },
+                },
+                reserved10: u2,
+                ///  Asynchronously kills the clock generator
+                KILL: u1,
+                ///  Starts and stops the clock generator cleanly
+                ENABLE: u1,
+                reserved16: u4,
+                ///  This delays the enable signal by up to 3 cycles of the input clock
+                ///  This must be set before the clock is enabled to have any effect
+                PHASE: u2,
+                reserved20: u2,
+                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
+                ///  This can be done at any time
+                NUDGE: u1,
+                padding: u11,
+            }),
+            ///  Clock divisor, can be changed on-the-fly
+            CLK_RTC_DIV: mmio.Mmio(packed struct(u32) {
+                ///  Fractional component of the divisor
+                FRAC: u8,
+                ///  Integer component of the divisor, 0 -> divide by 2^16
+                INT: u24,
+            }),
+            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
+            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
+            CLK_RTC_SELECTED: u32,
+            CLK_SYS_RESUS_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  This is expressed as a number of clk_ref cycles
+                ///  and must be >= 2x clk_ref_freq/min_clk_tst_freq
+                TIMEOUT: u8,
+                ///  Enable resus
+                ENABLE: u1,
+                reserved12: u3,
+                ///  Force a resus, for test purposes only
+                FRCE: u1,
+                reserved16: u3,
+                ///  For clearing the resus after the fault that triggered it has been corrected
+                CLEAR: u1,
+                padding: u15,
+            }),
+            CLK_SYS_RESUS_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  Clock has been resuscitated, correct the error then send ctrl_clear=1
+                RESUSSED: u1,
+                padding: u31,
+            }),
+            ///  Reference clock frequency in kHz
+            FC0_REF_KHZ: mmio.Mmio(packed struct(u32) {
+                FC0_REF_KHZ: u20,
+                padding: u12,
+            }),
+            ///  Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags
+            FC0_MIN_KHZ: mmio.Mmio(packed struct(u32) {
+                FC0_MIN_KHZ: u25,
+                padding: u7,
+            }),
+            ///  Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags
+            FC0_MAX_KHZ: mmio.Mmio(packed struct(u32) {
+                FC0_MAX_KHZ: u25,
+                padding: u7,
+            }),
+            ///  Delays the start of frequency counting to allow the mux to settle
+            ///  Delay is measured in multiples of the reference clock period
+            FC0_DELAY: mmio.Mmio(packed struct(u32) {
+                FC0_DELAY: u3,
+                padding: u29,
+            }),
+            ///  The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval
+            ///  The default gives a test interval of 250us
+            FC0_INTERVAL: mmio.Mmio(packed struct(u32) {
+                FC0_INTERVAL: u4,
+                padding: u28,
+            }),
+            ///  Clock sent to frequency counter, set to 0 when not required
+            ///  Writing to this register initiates the frequency count
+            FC0_SRC: mmio.Mmio(packed struct(u32) {
+                FC0_SRC: packed union {
+                    raw: u8,
+                    value: enum(u8) {
+                        NULL = 0x0,
+                        pll_sys_clksrc_primary = 0x1,
+                        pll_usb_clksrc_primary = 0x2,
+                        rosc_clksrc = 0x3,
+                        rosc_clksrc_ph = 0x4,
+                        xosc_clksrc = 0x5,
+                        clksrc_gpin0 = 0x6,
+                        clksrc_gpin1 = 0x7,
+                        clk_ref = 0x8,
+                        clk_sys = 0x9,
+                        clk_peri = 0xa,
+                        clk_usb = 0xb,
+                        clk_adc = 0xc,
+                        clk_rtc = 0xd,
+                        _,
+                    },
+                },
+                padding: u24,
+            }),
+            ///  Frequency counter status
+            FC0_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  Test passed
+                PASS: u1,
+                reserved4: u3,
+                ///  Test complete
+                DONE: u1,
+                reserved8: u3,
+                ///  Test running
+                RUNNING: u1,
+                reserved12: u3,
+                ///  Waiting for test clock to start
+                WAITING: u1,
+                reserved16: u3,
+                ///  Test failed
+                FAIL: u1,
+                reserved20: u3,
+                ///  Test clock slower than expected, only valid when status_done=1
+                SLOW: u1,
+                reserved24: u3,
+                ///  Test clock faster than expected, only valid when status_done=1
+                FAST: u1,
+                reserved28: u3,
+                ///  Test clock stopped during test
+                DIED: u1,
+                padding: u3,
+            }),
+            ///  Result of frequency measurement, only valid when status_done=1
+            FC0_RESULT: mmio.Mmio(packed struct(u32) {
+                FRAC: u5,
+                KHZ: u25,
+                padding: u2,
+            }),
+            ///  enable clock in wake mode
+            WAKE_EN0: mmio.Mmio(packed struct(u32) {
+                clk_sys_clocks: u1,
+                clk_adc_adc: u1,
+                clk_sys_adc: u1,
+                clk_sys_busctrl: u1,
+                clk_sys_busfabric: u1,
+                clk_sys_dma: u1,
+                clk_sys_i2c0: u1,
+                clk_sys_i2c1: u1,
+                clk_sys_io: u1,
+                clk_sys_jtag: u1,
+                clk_sys_vreg_and_chip_reset: u1,
+                clk_sys_pads: u1,
+                clk_sys_pio0: u1,
+                clk_sys_pio1: u1,
+                clk_sys_pll_sys: u1,
+                clk_sys_pll_usb: u1,
+                clk_sys_psm: u1,
+                clk_sys_pwm: u1,
+                clk_sys_resets: u1,
+                clk_sys_rom: u1,
+                clk_sys_rosc: u1,
+                clk_rtc_rtc: u1,
+                clk_sys_rtc: u1,
+                clk_sys_sio: u1,
+                clk_peri_spi0: u1,
+                clk_sys_spi0: u1,
+                clk_peri_spi1: u1,
+                clk_sys_spi1: u1,
+                clk_sys_sram0: u1,
+                clk_sys_sram1: u1,
+                clk_sys_sram2: u1,
+                clk_sys_sram3: u1,
+            }),
+            ///  enable clock in wake mode
+            WAKE_EN1: mmio.Mmio(packed struct(u32) {
+                clk_sys_sram4: u1,
+                clk_sys_sram5: u1,
+                clk_sys_syscfg: u1,
+                clk_sys_sysinfo: u1,
+                clk_sys_tbman: u1,
+                clk_sys_timer: u1,
+                clk_peri_uart0: u1,
+                clk_sys_uart0: u1,
+                clk_peri_uart1: u1,
+                clk_sys_uart1: u1,
+                clk_sys_usbctrl: u1,
+                clk_usb_usbctrl: u1,
+                clk_sys_watchdog: u1,
+                clk_sys_xip: u1,
+                clk_sys_xosc: u1,
+                padding: u17,
+            }),
+            ///  enable clock in sleep mode
+            SLEEP_EN0: mmio.Mmio(packed struct(u32) {
+                clk_sys_clocks: u1,
+                clk_adc_adc: u1,
+                clk_sys_adc: u1,
+                clk_sys_busctrl: u1,
+                clk_sys_busfabric: u1,
+                clk_sys_dma: u1,
+                clk_sys_i2c0: u1,
+                clk_sys_i2c1: u1,
+                clk_sys_io: u1,
+                clk_sys_jtag: u1,
+                clk_sys_vreg_and_chip_reset: u1,
+                clk_sys_pads: u1,
+                clk_sys_pio0: u1,
+                clk_sys_pio1: u1,
+                clk_sys_pll_sys: u1,
+                clk_sys_pll_usb: u1,
+                clk_sys_psm: u1,
+                clk_sys_pwm: u1,
+                clk_sys_resets: u1,
+                clk_sys_rom: u1,
+                clk_sys_rosc: u1,
+                clk_rtc_rtc: u1,
+                clk_sys_rtc: u1,
+                clk_sys_sio: u1,
+                clk_peri_spi0: u1,
+                clk_sys_spi0: u1,
+                clk_peri_spi1: u1,
+                clk_sys_spi1: u1,
+                clk_sys_sram0: u1,
+                clk_sys_sram1: u1,
+                clk_sys_sram2: u1,
+                clk_sys_sram3: u1,
+            }),
+            ///  enable clock in sleep mode
+            SLEEP_EN1: mmio.Mmio(packed struct(u32) {
+                clk_sys_sram4: u1,
+                clk_sys_sram5: u1,
+                clk_sys_syscfg: u1,
+                clk_sys_sysinfo: u1,
+                clk_sys_tbman: u1,
+                clk_sys_timer: u1,
+                clk_peri_uart0: u1,
+                clk_sys_uart0: u1,
+                clk_peri_uart1: u1,
+                clk_sys_uart1: u1,
+                clk_sys_usbctrl: u1,
+                clk_usb_usbctrl: u1,
+                clk_sys_watchdog: u1,
+                clk_sys_xip: u1,
+                clk_sys_xosc: u1,
+                padding: u17,
+            }),
+            ///  indicates the state of the clock enable
+            ENABLED0: mmio.Mmio(packed struct(u32) {
+                clk_sys_clocks: u1,
+                clk_adc_adc: u1,
+                clk_sys_adc: u1,
+                clk_sys_busctrl: u1,
+                clk_sys_busfabric: u1,
+                clk_sys_dma: u1,
+                clk_sys_i2c0: u1,
+                clk_sys_i2c1: u1,
+                clk_sys_io: u1,
+                clk_sys_jtag: u1,
+                clk_sys_vreg_and_chip_reset: u1,
+                clk_sys_pads: u1,
+                clk_sys_pio0: u1,
+                clk_sys_pio1: u1,
+                clk_sys_pll_sys: u1,
+                clk_sys_pll_usb: u1,
+                clk_sys_psm: u1,
+                clk_sys_pwm: u1,
+                clk_sys_resets: u1,
+                clk_sys_rom: u1,
+                clk_sys_rosc: u1,
+                clk_rtc_rtc: u1,
+                clk_sys_rtc: u1,
+                clk_sys_sio: u1,
+                clk_peri_spi0: u1,
+                clk_sys_spi0: u1,
+                clk_peri_spi1: u1,
+                clk_sys_spi1: u1,
+                clk_sys_sram0: u1,
+                clk_sys_sram1: u1,
+                clk_sys_sram2: u1,
+                clk_sys_sram3: u1,
+            }),
+            ///  indicates the state of the clock enable
+            ENABLED1: mmio.Mmio(packed struct(u32) {
+                clk_sys_sram4: u1,
+                clk_sys_sram5: u1,
+                clk_sys_syscfg: u1,
+                clk_sys_sysinfo: u1,
+                clk_sys_tbman: u1,
+                clk_sys_timer: u1,
+                clk_peri_uart0: u1,
+                clk_sys_uart0: u1,
+                clk_peri_uart1: u1,
+                clk_sys_uart1: u1,
+                clk_sys_usbctrl: u1,
+                clk_usb_usbctrl: u1,
+                clk_sys_watchdog: u1,
+                clk_sys_xip: u1,
+                clk_sys_xosc: u1,
+                padding: u17,
+            }),
+            ///  Raw Interrupts
+            INTR: mmio.Mmio(packed struct(u32) {
+                CLK_SYS_RESUS: u1,
+                padding: u31,
+            }),
+            ///  Interrupt Enable
+            INTE: mmio.Mmio(packed struct(u32) {
+                CLK_SYS_RESUS: u1,
+                padding: u31,
+            }),
+            ///  Interrupt Force
+            INTF: mmio.Mmio(packed struct(u32) {
+                CLK_SYS_RESUS: u1,
+                padding: u31,
+            }),
+            ///  Interrupt status after masking & forcing
+            INTS: mmio.Mmio(packed struct(u32) {
+                CLK_SYS_RESUS: u1,
+                padding: u31,
+            }),
+        };
+
+        pub const RESETS = extern struct {
+            ///  Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted.
+            RESET: mmio.Mmio(packed struct(u32) {
+                adc: u1,
+                busctrl: u1,
+                dma: u1,
+                i2c0: u1,
+                i2c1: u1,
+                io_bank0: u1,
+                io_qspi: u1,
+                jtag: u1,
+                pads_bank0: u1,
+                pads_qspi: u1,
+                pio0: u1,
+                pio1: u1,
+                pll_sys: u1,
+                pll_usb: u1,
+                pwm: u1,
+                rtc: u1,
+                spi0: u1,
+                spi1: u1,
+                syscfg: u1,
+                sysinfo: u1,
+                tbman: u1,
+                timer: u1,
+                uart0: u1,
+                uart1: u1,
+                usbctrl: u1,
+                padding: u7,
+            }),
+            ///  Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires.
+            WDSEL: mmio.Mmio(packed struct(u32) {
+                adc: u1,
+                busctrl: u1,
+                dma: u1,
+                i2c0: u1,
+                i2c1: u1,
+                io_bank0: u1,
+                io_qspi: u1,
+                jtag: u1,
+                pads_bank0: u1,
+                pads_qspi: u1,
+                pio0: u1,
+                pio1: u1,
+                pll_sys: u1,
+                pll_usb: u1,
+                pwm: u1,
+                rtc: u1,
+                spi0: u1,
+                spi1: u1,
+                syscfg: u1,
+                sysinfo: u1,
+                tbman: u1,
+                timer: u1,
+                uart0: u1,
+                uart1: u1,
+                usbctrl: u1,
+                padding: u7,
+            }),
+            ///  Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed.
+            RESET_DONE: mmio.Mmio(packed struct(u32) {
+                adc: u1,
+                busctrl: u1,
+                dma: u1,
+                i2c0: u1,
+                i2c1: u1,
+                io_bank0: u1,
+                io_qspi: u1,
+                jtag: u1,
+                pads_bank0: u1,
+                pads_qspi: u1,
+                pio0: u1,
+                pio1: u1,
+                pll_sys: u1,
+                pll_usb: u1,
+                pwm: u1,
+                rtc: u1,
+                spi0: u1,
+                spi1: u1,
+                syscfg: u1,
+                sysinfo: u1,
+                tbman: u1,
+                timer: u1,
+                uart0: u1,
+                uart1: u1,
+                usbctrl: u1,
+                padding: u7,
+            }),
+        };
+
+        pub const PSM = extern struct {
+            ///  Force block out of reset (i.e. power it on)
+            FRCE_ON: mmio.Mmio(packed struct(u32) {
+                rosc: u1,
+                xosc: u1,
+                clocks: u1,
+                resets: u1,
+                busfabric: u1,
+                rom: u1,
+                sram0: u1,
+                sram1: u1,
+                sram2: u1,
+                sram3: u1,
+                sram4: u1,
+                sram5: u1,
+                xip: u1,
+                vreg_and_chip_reset: u1,
+                sio: u1,
+                proc0: u1,
+                proc1: u1,
+                padding: u15,
+            }),
+            ///  Force into reset (i.e. power it off)
+            FRCE_OFF: mmio.Mmio(packed struct(u32) {
+                rosc: u1,
+                xosc: u1,
+                clocks: u1,
+                resets: u1,
+                busfabric: u1,
+                rom: u1,
+                sram0: u1,
+                sram1: u1,
+                sram2: u1,
+                sram3: u1,
+                sram4: u1,
+                sram5: u1,
+                xip: u1,
+                vreg_and_chip_reset: u1,
+                sio: u1,
+                proc0: u1,
+                proc1: u1,
+                padding: u15,
+            }),
+            ///  Set to 1 if this peripheral should be reset when the watchdog fires.
+            WDSEL: mmio.Mmio(packed struct(u32) {
+                rosc: u1,
+                xosc: u1,
+                clocks: u1,
+                resets: u1,
+                busfabric: u1,
+                rom: u1,
+                sram0: u1,
+                sram1: u1,
+                sram2: u1,
+                sram3: u1,
+                sram4: u1,
+                sram5: u1,
+                xip: u1,
+                vreg_and_chip_reset: u1,
+                sio: u1,
+                proc0: u1,
+                proc1: u1,
+                padding: u15,
+            }),
+            ///  Indicates the peripheral's registers are ready to access.
+            DONE: mmio.Mmio(packed struct(u32) {
+                rosc: u1,
+                xosc: u1,
+                clocks: u1,
+                resets: u1,
+                busfabric: u1,
+                rom: u1,
+                sram0: u1,
+                sram1: u1,
+                sram2: u1,
+                sram3: u1,
+                sram4: u1,
+                sram5: u1,
+                xip: u1,
+                vreg_and_chip_reset: u1,
+                sio: u1,
+                proc0: u1,
+                proc1: u1,
+                padding: u15,
+            }),
+        };
+
+        pub const IO_BANK0 = extern struct {
+            ///  GPIO status
+            GPIO0_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO0_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        jtag_tck = 0x0,
+                        spi0_rx = 0x1,
+                        uart0_tx = 0x2,
+                        i2c0_sda = 0x3,
+                        pwm_a_0 = 0x4,
+                        sio_0 = 0x5,
+                        pio0_0 = 0x6,
+                        pio1_0 = 0x7,
+                        usb_muxing_overcurr_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO1_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO1_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        jtag_tms = 0x0,
+                        spi0_ss_n = 0x1,
+                        uart0_rx = 0x2,
+                        i2c0_scl = 0x3,
+                        pwm_b_0 = 0x4,
+                        sio_1 = 0x5,
+                        pio0_1 = 0x6,
+                        pio1_1 = 0x7,
+                        usb_muxing_vbus_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO2_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO2_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        jtag_tdi = 0x0,
+                        spi0_sclk = 0x1,
+                        uart0_cts = 0x2,
+                        i2c1_sda = 0x3,
+                        pwm_a_1 = 0x4,
+                        sio_2 = 0x5,
+                        pio0_2 = 0x6,
+                        pio1_2 = 0x7,
+                        usb_muxing_vbus_en = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO3_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO3_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        jtag_tdo = 0x0,
+                        spi0_tx = 0x1,
+                        uart0_rts = 0x2,
+                        i2c1_scl = 0x3,
+                        pwm_b_1 = 0x4,
+                        sio_3 = 0x5,
+                        pio0_3 = 0x6,
+                        pio1_3 = 0x7,
+                        usb_muxing_overcurr_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO4_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO4_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_rx = 0x1,
+                        uart1_tx = 0x2,
+                        i2c0_sda = 0x3,
+                        pwm_a_2 = 0x4,
+                        sio_4 = 0x5,
+                        pio0_4 = 0x6,
+                        pio1_4 = 0x7,
+                        usb_muxing_vbus_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO5_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO5_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_ss_n = 0x1,
+                        uart1_rx = 0x2,
+                        i2c0_scl = 0x3,
+                        pwm_b_2 = 0x4,
+                        sio_5 = 0x5,
+                        pio0_5 = 0x6,
+                        pio1_5 = 0x7,
+                        usb_muxing_vbus_en = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO6_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO6_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_sclk = 0x1,
+                        uart1_cts = 0x2,
+                        i2c1_sda = 0x3,
+                        pwm_a_3 = 0x4,
+                        sio_6 = 0x5,
+                        pio0_6 = 0x6,
+                        pio1_6 = 0x7,
+                        usb_muxing_extphy_softcon = 0x8,
+                        usb_muxing_overcurr_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO7_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO7_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_tx = 0x1,
+                        uart1_rts = 0x2,
+                        i2c1_scl = 0x3,
+                        pwm_b_3 = 0x4,
+                        sio_7 = 0x5,
+                        pio0_7 = 0x6,
+                        pio1_7 = 0x7,
+                        usb_muxing_extphy_oe_n = 0x8,
+                        usb_muxing_vbus_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO8_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO8_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_rx = 0x1,
+                        uart1_tx = 0x2,
+                        i2c0_sda = 0x3,
+                        pwm_a_4 = 0x4,
+                        sio_8 = 0x5,
+                        pio0_8 = 0x6,
+                        pio1_8 = 0x7,
+                        usb_muxing_extphy_rcv = 0x8,
+                        usb_muxing_vbus_en = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO9_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO9_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_ss_n = 0x1,
+                        uart1_rx = 0x2,
+                        i2c0_scl = 0x3,
+                        pwm_b_4 = 0x4,
+                        sio_9 = 0x5,
+                        pio0_9 = 0x6,
+                        pio1_9 = 0x7,
+                        usb_muxing_extphy_vp = 0x8,
+                        usb_muxing_overcurr_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO10_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO10_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_sclk = 0x1,
+                        uart1_cts = 0x2,
+                        i2c1_sda = 0x3,
+                        pwm_a_5 = 0x4,
+                        sio_10 = 0x5,
+                        pio0_10 = 0x6,
+                        pio1_10 = 0x7,
+                        usb_muxing_extphy_vm = 0x8,
+                        usb_muxing_vbus_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO11_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO11_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_tx = 0x1,
+                        uart1_rts = 0x2,
+                        i2c1_scl = 0x3,
+                        pwm_b_5 = 0x4,
+                        sio_11 = 0x5,
+                        pio0_11 = 0x6,
+                        pio1_11 = 0x7,
+                        usb_muxing_extphy_suspnd = 0x8,
+                        usb_muxing_vbus_en = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO12_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO12_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_rx = 0x1,
+                        uart0_tx = 0x2,
+                        i2c0_sda = 0x3,
+                        pwm_a_6 = 0x4,
+                        sio_12 = 0x5,
+                        pio0_12 = 0x6,
+                        pio1_12 = 0x7,
+                        usb_muxing_extphy_speed = 0x8,
+                        usb_muxing_overcurr_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO13_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO13_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_ss_n = 0x1,
+                        uart0_rx = 0x2,
+                        i2c0_scl = 0x3,
+                        pwm_b_6 = 0x4,
+                        sio_13 = 0x5,
+                        pio0_13 = 0x6,
+                        pio1_13 = 0x7,
+                        usb_muxing_extphy_vpo = 0x8,
+                        usb_muxing_vbus_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO14_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO14_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_sclk = 0x1,
+                        uart0_cts = 0x2,
+                        i2c1_sda = 0x3,
+                        pwm_a_7 = 0x4,
+                        sio_14 = 0x5,
+                        pio0_14 = 0x6,
+                        pio1_14 = 0x7,
+                        usb_muxing_extphy_vmo = 0x8,
+                        usb_muxing_vbus_en = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO15_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO15_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_tx = 0x1,
+                        uart0_rts = 0x2,
+                        i2c1_scl = 0x3,
+                        pwm_b_7 = 0x4,
+                        sio_15 = 0x5,
+                        pio0_15 = 0x6,
+                        pio1_15 = 0x7,
+                        usb_muxing_digital_dp = 0x8,
+                        usb_muxing_overcurr_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO16_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO16_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_rx = 0x1,
+                        uart0_tx = 0x2,
+                        i2c0_sda = 0x3,
+                        pwm_a_0 = 0x4,
+                        sio_16 = 0x5,
+                        pio0_16 = 0x6,
+                        pio1_16 = 0x7,
+                        usb_muxing_digital_dm = 0x8,
+                        usb_muxing_vbus_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO17_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO17_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_ss_n = 0x1,
+                        uart0_rx = 0x2,
+                        i2c0_scl = 0x3,
+                        pwm_b_0 = 0x4,
+                        sio_17 = 0x5,
+                        pio0_17 = 0x6,
+                        pio1_17 = 0x7,
+                        usb_muxing_vbus_en = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO18_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO18_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_sclk = 0x1,
+                        uart0_cts = 0x2,
+                        i2c1_sda = 0x3,
+                        pwm_a_1 = 0x4,
+                        sio_18 = 0x5,
+                        pio0_18 = 0x6,
+                        pio1_18 = 0x7,
+                        usb_muxing_overcurr_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO19_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO19_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_tx = 0x1,
+                        uart0_rts = 0x2,
+                        i2c1_scl = 0x3,
+                        pwm_b_1 = 0x4,
+                        sio_19 = 0x5,
+                        pio0_19 = 0x6,
+                        pio1_19 = 0x7,
+                        usb_muxing_vbus_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO20_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO20_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_rx = 0x1,
+                        uart1_tx = 0x2,
+                        i2c0_sda = 0x3,
+                        pwm_a_2 = 0x4,
+                        sio_20 = 0x5,
+                        pio0_20 = 0x6,
+                        pio1_20 = 0x7,
+                        clocks_gpin_0 = 0x8,
+                        usb_muxing_vbus_en = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO21_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO21_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_ss_n = 0x1,
+                        uart1_rx = 0x2,
+                        i2c0_scl = 0x3,
+                        pwm_b_2 = 0x4,
+                        sio_21 = 0x5,
+                        pio0_21 = 0x6,
+                        pio1_21 = 0x7,
+                        clocks_gpout_0 = 0x8,
+                        usb_muxing_overcurr_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO22_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO22_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_sclk = 0x1,
+                        uart1_cts = 0x2,
+                        i2c1_sda = 0x3,
+                        pwm_a_3 = 0x4,
+                        sio_22 = 0x5,
+                        pio0_22 = 0x6,
+                        pio1_22 = 0x7,
+                        clocks_gpin_1 = 0x8,
+                        usb_muxing_vbus_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO23_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO23_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi0_tx = 0x1,
+                        uart1_rts = 0x2,
+                        i2c1_scl = 0x3,
+                        pwm_b_3 = 0x4,
+                        sio_23 = 0x5,
+                        pio0_23 = 0x6,
+                        pio1_23 = 0x7,
+                        clocks_gpout_1 = 0x8,
+                        usb_muxing_vbus_en = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO24_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO24_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_rx = 0x1,
+                        uart1_tx = 0x2,
+                        i2c0_sda = 0x3,
+                        pwm_a_4 = 0x4,
+                        sio_24 = 0x5,
+                        pio0_24 = 0x6,
+                        pio1_24 = 0x7,
+                        clocks_gpout_2 = 0x8,
+                        usb_muxing_overcurr_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO25_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO25_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_ss_n = 0x1,
+                        uart1_rx = 0x2,
+                        i2c0_scl = 0x3,
+                        pwm_b_4 = 0x4,
+                        sio_25 = 0x5,
+                        pio0_25 = 0x6,
+                        pio1_25 = 0x7,
+                        clocks_gpout_3 = 0x8,
+                        usb_muxing_vbus_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO26_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO26_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_sclk = 0x1,
+                        uart1_cts = 0x2,
+                        i2c1_sda = 0x3,
+                        pwm_a_5 = 0x4,
+                        sio_26 = 0x5,
+                        pio0_26 = 0x6,
+                        pio1_26 = 0x7,
+                        usb_muxing_vbus_en = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO27_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO27_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_tx = 0x1,
+                        uart1_rts = 0x2,
+                        i2c1_scl = 0x3,
+                        pwm_b_5 = 0x4,
+                        sio_27 = 0x5,
+                        pio0_27 = 0x6,
+                        pio1_27 = 0x7,
+                        usb_muxing_overcurr_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO28_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO28_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_rx = 0x1,
+                        uart0_tx = 0x2,
+                        i2c0_sda = 0x3,
+                        pwm_a_6 = 0x4,
+                        sio_28 = 0x5,
+                        pio0_28 = 0x6,
+                        pio1_28 = 0x7,
+                        usb_muxing_vbus_detect = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO29_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO29_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        spi1_ss_n = 0x1,
+                        uart0_rx = 0x2,
+                        i2c0_scl = 0x3,
+                        pwm_b_6 = 0x4,
+                        sio_29 = 0x5,
+                        pio0_29 = 0x6,
+                        pio1_29 = 0x7,
+                        usb_muxing_vbus_en = 0x9,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  Raw Interrupts
+            INTR0: mmio.Mmio(packed struct(u32) {
+                GPIO0_LEVEL_LOW: u1,
+                GPIO0_LEVEL_HIGH: u1,
+                GPIO0_EDGE_LOW: u1,
+                GPIO0_EDGE_HIGH: u1,
+                GPIO1_LEVEL_LOW: u1,
+                GPIO1_LEVEL_HIGH: u1,
+                GPIO1_EDGE_LOW: u1,
+                GPIO1_EDGE_HIGH: u1,
+                GPIO2_LEVEL_LOW: u1,
+                GPIO2_LEVEL_HIGH: u1,
+                GPIO2_EDGE_LOW: u1,
+                GPIO2_EDGE_HIGH: u1,
+                GPIO3_LEVEL_LOW: u1,
+                GPIO3_LEVEL_HIGH: u1,
+                GPIO3_EDGE_LOW: u1,
+                GPIO3_EDGE_HIGH: u1,
+                GPIO4_LEVEL_LOW: u1,
+                GPIO4_LEVEL_HIGH: u1,
+                GPIO4_EDGE_LOW: u1,
+                GPIO4_EDGE_HIGH: u1,
+                GPIO5_LEVEL_LOW: u1,
+                GPIO5_LEVEL_HIGH: u1,
+                GPIO5_EDGE_LOW: u1,
+                GPIO5_EDGE_HIGH: u1,
+                GPIO6_LEVEL_LOW: u1,
+                GPIO6_LEVEL_HIGH: u1,
+                GPIO6_EDGE_LOW: u1,
+                GPIO6_EDGE_HIGH: u1,
+                GPIO7_LEVEL_LOW: u1,
+                GPIO7_LEVEL_HIGH: u1,
+                GPIO7_EDGE_LOW: u1,
+                GPIO7_EDGE_HIGH: u1,
+            }),
+            ///  Raw Interrupts
+            INTR1: mmio.Mmio(packed struct(u32) {
+                GPIO8_LEVEL_LOW: u1,
+                GPIO8_LEVEL_HIGH: u1,
+                GPIO8_EDGE_LOW: u1,
+                GPIO8_EDGE_HIGH: u1,
+                GPIO9_LEVEL_LOW: u1,
+                GPIO9_LEVEL_HIGH: u1,
+                GPIO9_EDGE_LOW: u1,
+                GPIO9_EDGE_HIGH: u1,
+                GPIO10_LEVEL_LOW: u1,
+                GPIO10_LEVEL_HIGH: u1,
+                GPIO10_EDGE_LOW: u1,
+                GPIO10_EDGE_HIGH: u1,
+                GPIO11_LEVEL_LOW: u1,
+                GPIO11_LEVEL_HIGH: u1,
+                GPIO11_EDGE_LOW: u1,
+                GPIO11_EDGE_HIGH: u1,
+                GPIO12_LEVEL_LOW: u1,
+                GPIO12_LEVEL_HIGH: u1,
+                GPIO12_EDGE_LOW: u1,
+                GPIO12_EDGE_HIGH: u1,
+                GPIO13_LEVEL_LOW: u1,
+                GPIO13_LEVEL_HIGH: u1,
+                GPIO13_EDGE_LOW: u1,
+                GPIO13_EDGE_HIGH: u1,
+                GPIO14_LEVEL_LOW: u1,
+                GPIO14_LEVEL_HIGH: u1,
+                GPIO14_EDGE_LOW: u1,
+                GPIO14_EDGE_HIGH: u1,
+                GPIO15_LEVEL_LOW: u1,
+                GPIO15_LEVEL_HIGH: u1,
+                GPIO15_EDGE_LOW: u1,
+                GPIO15_EDGE_HIGH: u1,
+            }),
+            ///  Raw Interrupts
+            INTR2: mmio.Mmio(packed struct(u32) {
+                GPIO16_LEVEL_LOW: u1,
+                GPIO16_LEVEL_HIGH: u1,
+                GPIO16_EDGE_LOW: u1,
+                GPIO16_EDGE_HIGH: u1,
+                GPIO17_LEVEL_LOW: u1,
+                GPIO17_LEVEL_HIGH: u1,
+                GPIO17_EDGE_LOW: u1,
+                GPIO17_EDGE_HIGH: u1,
+                GPIO18_LEVEL_LOW: u1,
+                GPIO18_LEVEL_HIGH: u1,
+                GPIO18_EDGE_LOW: u1,
+                GPIO18_EDGE_HIGH: u1,
+                GPIO19_LEVEL_LOW: u1,
+                GPIO19_LEVEL_HIGH: u1,
+                GPIO19_EDGE_LOW: u1,
+                GPIO19_EDGE_HIGH: u1,
+                GPIO20_LEVEL_LOW: u1,
+                GPIO20_LEVEL_HIGH: u1,
+                GPIO20_EDGE_LOW: u1,
+                GPIO20_EDGE_HIGH: u1,
+                GPIO21_LEVEL_LOW: u1,
+                GPIO21_LEVEL_HIGH: u1,
+                GPIO21_EDGE_LOW: u1,
+                GPIO21_EDGE_HIGH: u1,
+                GPIO22_LEVEL_LOW: u1,
+                GPIO22_LEVEL_HIGH: u1,
+                GPIO22_EDGE_LOW: u1,
+                GPIO22_EDGE_HIGH: u1,
+                GPIO23_LEVEL_LOW: u1,
+                GPIO23_LEVEL_HIGH: u1,
+                GPIO23_EDGE_LOW: u1,
+                GPIO23_EDGE_HIGH: u1,
+            }),
+            ///  Raw Interrupts
+            INTR3: mmio.Mmio(packed struct(u32) {
+                GPIO24_LEVEL_LOW: u1,
+                GPIO24_LEVEL_HIGH: u1,
+                GPIO24_EDGE_LOW: u1,
+                GPIO24_EDGE_HIGH: u1,
+                GPIO25_LEVEL_LOW: u1,
+                GPIO25_LEVEL_HIGH: u1,
+                GPIO25_EDGE_LOW: u1,
+                GPIO25_EDGE_HIGH: u1,
+                GPIO26_LEVEL_LOW: u1,
+                GPIO26_LEVEL_HIGH: u1,
+                GPIO26_EDGE_LOW: u1,
+                GPIO26_EDGE_HIGH: u1,
+                GPIO27_LEVEL_LOW: u1,
+                GPIO27_LEVEL_HIGH: u1,
+                GPIO27_EDGE_LOW: u1,
+                GPIO27_EDGE_HIGH: u1,
+                GPIO28_LEVEL_LOW: u1,
+                GPIO28_LEVEL_HIGH: u1,
+                GPIO28_EDGE_LOW: u1,
+                GPIO28_EDGE_HIGH: u1,
+                GPIO29_LEVEL_LOW: u1,
+                GPIO29_LEVEL_HIGH: u1,
+                GPIO29_EDGE_LOW: u1,
+                GPIO29_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Enable for proc0
+            PROC0_INTE0: mmio.Mmio(packed struct(u32) {
+                GPIO0_LEVEL_LOW: u1,
+                GPIO0_LEVEL_HIGH: u1,
+                GPIO0_EDGE_LOW: u1,
+                GPIO0_EDGE_HIGH: u1,
+                GPIO1_LEVEL_LOW: u1,
+                GPIO1_LEVEL_HIGH: u1,
+                GPIO1_EDGE_LOW: u1,
+                GPIO1_EDGE_HIGH: u1,
+                GPIO2_LEVEL_LOW: u1,
+                GPIO2_LEVEL_HIGH: u1,
+                GPIO2_EDGE_LOW: u1,
+                GPIO2_EDGE_HIGH: u1,
+                GPIO3_LEVEL_LOW: u1,
+                GPIO3_LEVEL_HIGH: u1,
+                GPIO3_EDGE_LOW: u1,
+                GPIO3_EDGE_HIGH: u1,
+                GPIO4_LEVEL_LOW: u1,
+                GPIO4_LEVEL_HIGH: u1,
+                GPIO4_EDGE_LOW: u1,
+                GPIO4_EDGE_HIGH: u1,
+                GPIO5_LEVEL_LOW: u1,
+                GPIO5_LEVEL_HIGH: u1,
+                GPIO5_EDGE_LOW: u1,
+                GPIO5_EDGE_HIGH: u1,
+                GPIO6_LEVEL_LOW: u1,
+                GPIO6_LEVEL_HIGH: u1,
+                GPIO6_EDGE_LOW: u1,
+                GPIO6_EDGE_HIGH: u1,
+                GPIO7_LEVEL_LOW: u1,
+                GPIO7_LEVEL_HIGH: u1,
+                GPIO7_EDGE_LOW: u1,
+                GPIO7_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Enable for proc0
+            PROC0_INTE1: mmio.Mmio(packed struct(u32) {
+                GPIO8_LEVEL_LOW: u1,
+                GPIO8_LEVEL_HIGH: u1,
+                GPIO8_EDGE_LOW: u1,
+                GPIO8_EDGE_HIGH: u1,
+                GPIO9_LEVEL_LOW: u1,
+                GPIO9_LEVEL_HIGH: u1,
+                GPIO9_EDGE_LOW: u1,
+                GPIO9_EDGE_HIGH: u1,
+                GPIO10_LEVEL_LOW: u1,
+                GPIO10_LEVEL_HIGH: u1,
+                GPIO10_EDGE_LOW: u1,
+                GPIO10_EDGE_HIGH: u1,
+                GPIO11_LEVEL_LOW: u1,
+                GPIO11_LEVEL_HIGH: u1,
+                GPIO11_EDGE_LOW: u1,
+                GPIO11_EDGE_HIGH: u1,
+                GPIO12_LEVEL_LOW: u1,
+                GPIO12_LEVEL_HIGH: u1,
+                GPIO12_EDGE_LOW: u1,
+                GPIO12_EDGE_HIGH: u1,
+                GPIO13_LEVEL_LOW: u1,
+                GPIO13_LEVEL_HIGH: u1,
+                GPIO13_EDGE_LOW: u1,
+                GPIO13_EDGE_HIGH: u1,
+                GPIO14_LEVEL_LOW: u1,
+                GPIO14_LEVEL_HIGH: u1,
+                GPIO14_EDGE_LOW: u1,
+                GPIO14_EDGE_HIGH: u1,
+                GPIO15_LEVEL_LOW: u1,
+                GPIO15_LEVEL_HIGH: u1,
+                GPIO15_EDGE_LOW: u1,
+                GPIO15_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Enable for proc0
+            PROC0_INTE2: mmio.Mmio(packed struct(u32) {
+                GPIO16_LEVEL_LOW: u1,
+                GPIO16_LEVEL_HIGH: u1,
+                GPIO16_EDGE_LOW: u1,
+                GPIO16_EDGE_HIGH: u1,
+                GPIO17_LEVEL_LOW: u1,
+                GPIO17_LEVEL_HIGH: u1,
+                GPIO17_EDGE_LOW: u1,
+                GPIO17_EDGE_HIGH: u1,
+                GPIO18_LEVEL_LOW: u1,
+                GPIO18_LEVEL_HIGH: u1,
+                GPIO18_EDGE_LOW: u1,
+                GPIO18_EDGE_HIGH: u1,
+                GPIO19_LEVEL_LOW: u1,
+                GPIO19_LEVEL_HIGH: u1,
+                GPIO19_EDGE_LOW: u1,
+                GPIO19_EDGE_HIGH: u1,
+                GPIO20_LEVEL_LOW: u1,
+                GPIO20_LEVEL_HIGH: u1,
+                GPIO20_EDGE_LOW: u1,
+                GPIO20_EDGE_HIGH: u1,
+                GPIO21_LEVEL_LOW: u1,
+                GPIO21_LEVEL_HIGH: u1,
+                GPIO21_EDGE_LOW: u1,
+                GPIO21_EDGE_HIGH: u1,
+                GPIO22_LEVEL_LOW: u1,
+                GPIO22_LEVEL_HIGH: u1,
+                GPIO22_EDGE_LOW: u1,
+                GPIO22_EDGE_HIGH: u1,
+                GPIO23_LEVEL_LOW: u1,
+                GPIO23_LEVEL_HIGH: u1,
+                GPIO23_EDGE_LOW: u1,
+                GPIO23_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Enable for proc0
+            PROC0_INTE3: mmio.Mmio(packed struct(u32) {
+                GPIO24_LEVEL_LOW: u1,
+                GPIO24_LEVEL_HIGH: u1,
+                GPIO24_EDGE_LOW: u1,
+                GPIO24_EDGE_HIGH: u1,
+                GPIO25_LEVEL_LOW: u1,
+                GPIO25_LEVEL_HIGH: u1,
+                GPIO25_EDGE_LOW: u1,
+                GPIO25_EDGE_HIGH: u1,
+                GPIO26_LEVEL_LOW: u1,
+                GPIO26_LEVEL_HIGH: u1,
+                GPIO26_EDGE_LOW: u1,
+                GPIO26_EDGE_HIGH: u1,
+                GPIO27_LEVEL_LOW: u1,
+                GPIO27_LEVEL_HIGH: u1,
+                GPIO27_EDGE_LOW: u1,
+                GPIO27_EDGE_HIGH: u1,
+                GPIO28_LEVEL_LOW: u1,
+                GPIO28_LEVEL_HIGH: u1,
+                GPIO28_EDGE_LOW: u1,
+                GPIO28_EDGE_HIGH: u1,
+                GPIO29_LEVEL_LOW: u1,
+                GPIO29_LEVEL_HIGH: u1,
+                GPIO29_EDGE_LOW: u1,
+                GPIO29_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Force for proc0
+            PROC0_INTF0: mmio.Mmio(packed struct(u32) {
+                GPIO0_LEVEL_LOW: u1,
+                GPIO0_LEVEL_HIGH: u1,
+                GPIO0_EDGE_LOW: u1,
+                GPIO0_EDGE_HIGH: u1,
+                GPIO1_LEVEL_LOW: u1,
+                GPIO1_LEVEL_HIGH: u1,
+                GPIO1_EDGE_LOW: u1,
+                GPIO1_EDGE_HIGH: u1,
+                GPIO2_LEVEL_LOW: u1,
+                GPIO2_LEVEL_HIGH: u1,
+                GPIO2_EDGE_LOW: u1,
+                GPIO2_EDGE_HIGH: u1,
+                GPIO3_LEVEL_LOW: u1,
+                GPIO3_LEVEL_HIGH: u1,
+                GPIO3_EDGE_LOW: u1,
+                GPIO3_EDGE_HIGH: u1,
+                GPIO4_LEVEL_LOW: u1,
+                GPIO4_LEVEL_HIGH: u1,
+                GPIO4_EDGE_LOW: u1,
+                GPIO4_EDGE_HIGH: u1,
+                GPIO5_LEVEL_LOW: u1,
+                GPIO5_LEVEL_HIGH: u1,
+                GPIO5_EDGE_LOW: u1,
+                GPIO5_EDGE_HIGH: u1,
+                GPIO6_LEVEL_LOW: u1,
+                GPIO6_LEVEL_HIGH: u1,
+                GPIO6_EDGE_LOW: u1,
+                GPIO6_EDGE_HIGH: u1,
+                GPIO7_LEVEL_LOW: u1,
+                GPIO7_LEVEL_HIGH: u1,
+                GPIO7_EDGE_LOW: u1,
+                GPIO7_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Force for proc0
+            PROC0_INTF1: mmio.Mmio(packed struct(u32) {
+                GPIO8_LEVEL_LOW: u1,
+                GPIO8_LEVEL_HIGH: u1,
+                GPIO8_EDGE_LOW: u1,
+                GPIO8_EDGE_HIGH: u1,
+                GPIO9_LEVEL_LOW: u1,
+                GPIO9_LEVEL_HIGH: u1,
+                GPIO9_EDGE_LOW: u1,
+                GPIO9_EDGE_HIGH: u1,
+                GPIO10_LEVEL_LOW: u1,
+                GPIO10_LEVEL_HIGH: u1,
+                GPIO10_EDGE_LOW: u1,
+                GPIO10_EDGE_HIGH: u1,
+                GPIO11_LEVEL_LOW: u1,
+                GPIO11_LEVEL_HIGH: u1,
+                GPIO11_EDGE_LOW: u1,
+                GPIO11_EDGE_HIGH: u1,
+                GPIO12_LEVEL_LOW: u1,
+                GPIO12_LEVEL_HIGH: u1,
+                GPIO12_EDGE_LOW: u1,
+                GPIO12_EDGE_HIGH: u1,
+                GPIO13_LEVEL_LOW: u1,
+                GPIO13_LEVEL_HIGH: u1,
+                GPIO13_EDGE_LOW: u1,
+                GPIO13_EDGE_HIGH: u1,
+                GPIO14_LEVEL_LOW: u1,
+                GPIO14_LEVEL_HIGH: u1,
+                GPIO14_EDGE_LOW: u1,
+                GPIO14_EDGE_HIGH: u1,
+                GPIO15_LEVEL_LOW: u1,
+                GPIO15_LEVEL_HIGH: u1,
+                GPIO15_EDGE_LOW: u1,
+                GPIO15_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Force for proc0
+            PROC0_INTF2: mmio.Mmio(packed struct(u32) {
+                GPIO16_LEVEL_LOW: u1,
+                GPIO16_LEVEL_HIGH: u1,
+                GPIO16_EDGE_LOW: u1,
+                GPIO16_EDGE_HIGH: u1,
+                GPIO17_LEVEL_LOW: u1,
+                GPIO17_LEVEL_HIGH: u1,
+                GPIO17_EDGE_LOW: u1,
+                GPIO17_EDGE_HIGH: u1,
+                GPIO18_LEVEL_LOW: u1,
+                GPIO18_LEVEL_HIGH: u1,
+                GPIO18_EDGE_LOW: u1,
+                GPIO18_EDGE_HIGH: u1,
+                GPIO19_LEVEL_LOW: u1,
+                GPIO19_LEVEL_HIGH: u1,
+                GPIO19_EDGE_LOW: u1,
+                GPIO19_EDGE_HIGH: u1,
+                GPIO20_LEVEL_LOW: u1,
+                GPIO20_LEVEL_HIGH: u1,
+                GPIO20_EDGE_LOW: u1,
+                GPIO20_EDGE_HIGH: u1,
+                GPIO21_LEVEL_LOW: u1,
+                GPIO21_LEVEL_HIGH: u1,
+                GPIO21_EDGE_LOW: u1,
+                GPIO21_EDGE_HIGH: u1,
+                GPIO22_LEVEL_LOW: u1,
+                GPIO22_LEVEL_HIGH: u1,
+                GPIO22_EDGE_LOW: u1,
+                GPIO22_EDGE_HIGH: u1,
+                GPIO23_LEVEL_LOW: u1,
+                GPIO23_LEVEL_HIGH: u1,
+                GPIO23_EDGE_LOW: u1,
+                GPIO23_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Force for proc0
+            PROC0_INTF3: mmio.Mmio(packed struct(u32) {
+                GPIO24_LEVEL_LOW: u1,
+                GPIO24_LEVEL_HIGH: u1,
+                GPIO24_EDGE_LOW: u1,
+                GPIO24_EDGE_HIGH: u1,
+                GPIO25_LEVEL_LOW: u1,
+                GPIO25_LEVEL_HIGH: u1,
+                GPIO25_EDGE_LOW: u1,
+                GPIO25_EDGE_HIGH: u1,
+                GPIO26_LEVEL_LOW: u1,
+                GPIO26_LEVEL_HIGH: u1,
+                GPIO26_EDGE_LOW: u1,
+                GPIO26_EDGE_HIGH: u1,
+                GPIO27_LEVEL_LOW: u1,
+                GPIO27_LEVEL_HIGH: u1,
+                GPIO27_EDGE_LOW: u1,
+                GPIO27_EDGE_HIGH: u1,
+                GPIO28_LEVEL_LOW: u1,
+                GPIO28_LEVEL_HIGH: u1,
+                GPIO28_EDGE_LOW: u1,
+                GPIO28_EDGE_HIGH: u1,
+                GPIO29_LEVEL_LOW: u1,
+                GPIO29_LEVEL_HIGH: u1,
+                GPIO29_EDGE_LOW: u1,
+                GPIO29_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt status after masking & forcing for proc0
+            PROC0_INTS0: mmio.Mmio(packed struct(u32) {
+                GPIO0_LEVEL_LOW: u1,
+                GPIO0_LEVEL_HIGH: u1,
+                GPIO0_EDGE_LOW: u1,
+                GPIO0_EDGE_HIGH: u1,
+                GPIO1_LEVEL_LOW: u1,
+                GPIO1_LEVEL_HIGH: u1,
+                GPIO1_EDGE_LOW: u1,
+                GPIO1_EDGE_HIGH: u1,
+                GPIO2_LEVEL_LOW: u1,
+                GPIO2_LEVEL_HIGH: u1,
+                GPIO2_EDGE_LOW: u1,
+                GPIO2_EDGE_HIGH: u1,
+                GPIO3_LEVEL_LOW: u1,
+                GPIO3_LEVEL_HIGH: u1,
+                GPIO3_EDGE_LOW: u1,
+                GPIO3_EDGE_HIGH: u1,
+                GPIO4_LEVEL_LOW: u1,
+                GPIO4_LEVEL_HIGH: u1,
+                GPIO4_EDGE_LOW: u1,
+                GPIO4_EDGE_HIGH: u1,
+                GPIO5_LEVEL_LOW: u1,
+                GPIO5_LEVEL_HIGH: u1,
+                GPIO5_EDGE_LOW: u1,
+                GPIO5_EDGE_HIGH: u1,
+                GPIO6_LEVEL_LOW: u1,
+                GPIO6_LEVEL_HIGH: u1,
+                GPIO6_EDGE_LOW: u1,
+                GPIO6_EDGE_HIGH: u1,
+                GPIO7_LEVEL_LOW: u1,
+                GPIO7_LEVEL_HIGH: u1,
+                GPIO7_EDGE_LOW: u1,
+                GPIO7_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt status after masking & forcing for proc0
+            PROC0_INTS1: mmio.Mmio(packed struct(u32) {
+                GPIO8_LEVEL_LOW: u1,
+                GPIO8_LEVEL_HIGH: u1,
+                GPIO8_EDGE_LOW: u1,
+                GPIO8_EDGE_HIGH: u1,
+                GPIO9_LEVEL_LOW: u1,
+                GPIO9_LEVEL_HIGH: u1,
+                GPIO9_EDGE_LOW: u1,
+                GPIO9_EDGE_HIGH: u1,
+                GPIO10_LEVEL_LOW: u1,
+                GPIO10_LEVEL_HIGH: u1,
+                GPIO10_EDGE_LOW: u1,
+                GPIO10_EDGE_HIGH: u1,
+                GPIO11_LEVEL_LOW: u1,
+                GPIO11_LEVEL_HIGH: u1,
+                GPIO11_EDGE_LOW: u1,
+                GPIO11_EDGE_HIGH: u1,
+                GPIO12_LEVEL_LOW: u1,
+                GPIO12_LEVEL_HIGH: u1,
+                GPIO12_EDGE_LOW: u1,
+                GPIO12_EDGE_HIGH: u1,
+                GPIO13_LEVEL_LOW: u1,
+                GPIO13_LEVEL_HIGH: u1,
+                GPIO13_EDGE_LOW: u1,
+                GPIO13_EDGE_HIGH: u1,
+                GPIO14_LEVEL_LOW: u1,
+                GPIO14_LEVEL_HIGH: u1,
+                GPIO14_EDGE_LOW: u1,
+                GPIO14_EDGE_HIGH: u1,
+                GPIO15_LEVEL_LOW: u1,
+                GPIO15_LEVEL_HIGH: u1,
+                GPIO15_EDGE_LOW: u1,
+                GPIO15_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt status after masking & forcing for proc0
+            PROC0_INTS2: mmio.Mmio(packed struct(u32) {
+                GPIO16_LEVEL_LOW: u1,
+                GPIO16_LEVEL_HIGH: u1,
+                GPIO16_EDGE_LOW: u1,
+                GPIO16_EDGE_HIGH: u1,
+                GPIO17_LEVEL_LOW: u1,
+                GPIO17_LEVEL_HIGH: u1,
+                GPIO17_EDGE_LOW: u1,
+                GPIO17_EDGE_HIGH: u1,
+                GPIO18_LEVEL_LOW: u1,
+                GPIO18_LEVEL_HIGH: u1,
+                GPIO18_EDGE_LOW: u1,
+                GPIO18_EDGE_HIGH: u1,
+                GPIO19_LEVEL_LOW: u1,
+                GPIO19_LEVEL_HIGH: u1,
+                GPIO19_EDGE_LOW: u1,
+                GPIO19_EDGE_HIGH: u1,
+                GPIO20_LEVEL_LOW: u1,
+                GPIO20_LEVEL_HIGH: u1,
+                GPIO20_EDGE_LOW: u1,
+                GPIO20_EDGE_HIGH: u1,
+                GPIO21_LEVEL_LOW: u1,
+                GPIO21_LEVEL_HIGH: u1,
+                GPIO21_EDGE_LOW: u1,
+                GPIO21_EDGE_HIGH: u1,
+                GPIO22_LEVEL_LOW: u1,
+                GPIO22_LEVEL_HIGH: u1,
+                GPIO22_EDGE_LOW: u1,
+                GPIO22_EDGE_HIGH: u1,
+                GPIO23_LEVEL_LOW: u1,
+                GPIO23_LEVEL_HIGH: u1,
+                GPIO23_EDGE_LOW: u1,
+                GPIO23_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt status after masking & forcing for proc0
+            PROC0_INTS3: mmio.Mmio(packed struct(u32) {
+                GPIO24_LEVEL_LOW: u1,
+                GPIO24_LEVEL_HIGH: u1,
+                GPIO24_EDGE_LOW: u1,
+                GPIO24_EDGE_HIGH: u1,
+                GPIO25_LEVEL_LOW: u1,
+                GPIO25_LEVEL_HIGH: u1,
+                GPIO25_EDGE_LOW: u1,
+                GPIO25_EDGE_HIGH: u1,
+                GPIO26_LEVEL_LOW: u1,
+                GPIO26_LEVEL_HIGH: u1,
+                GPIO26_EDGE_LOW: u1,
+                GPIO26_EDGE_HIGH: u1,
+                GPIO27_LEVEL_LOW: u1,
+                GPIO27_LEVEL_HIGH: u1,
+                GPIO27_EDGE_LOW: u1,
+                GPIO27_EDGE_HIGH: u1,
+                GPIO28_LEVEL_LOW: u1,
+                GPIO28_LEVEL_HIGH: u1,
+                GPIO28_EDGE_LOW: u1,
+                GPIO28_EDGE_HIGH: u1,
+                GPIO29_LEVEL_LOW: u1,
+                GPIO29_LEVEL_HIGH: u1,
+                GPIO29_EDGE_LOW: u1,
+                GPIO29_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Enable for proc1
+            PROC1_INTE0: mmio.Mmio(packed struct(u32) {
+                GPIO0_LEVEL_LOW: u1,
+                GPIO0_LEVEL_HIGH: u1,
+                GPIO0_EDGE_LOW: u1,
+                GPIO0_EDGE_HIGH: u1,
+                GPIO1_LEVEL_LOW: u1,
+                GPIO1_LEVEL_HIGH: u1,
+                GPIO1_EDGE_LOW: u1,
+                GPIO1_EDGE_HIGH: u1,
+                GPIO2_LEVEL_LOW: u1,
+                GPIO2_LEVEL_HIGH: u1,
+                GPIO2_EDGE_LOW: u1,
+                GPIO2_EDGE_HIGH: u1,
+                GPIO3_LEVEL_LOW: u1,
+                GPIO3_LEVEL_HIGH: u1,
+                GPIO3_EDGE_LOW: u1,
+                GPIO3_EDGE_HIGH: u1,
+                GPIO4_LEVEL_LOW: u1,
+                GPIO4_LEVEL_HIGH: u1,
+                GPIO4_EDGE_LOW: u1,
+                GPIO4_EDGE_HIGH: u1,
+                GPIO5_LEVEL_LOW: u1,
+                GPIO5_LEVEL_HIGH: u1,
+                GPIO5_EDGE_LOW: u1,
+                GPIO5_EDGE_HIGH: u1,
+                GPIO6_LEVEL_LOW: u1,
+                GPIO6_LEVEL_HIGH: u1,
+                GPIO6_EDGE_LOW: u1,
+                GPIO6_EDGE_HIGH: u1,
+                GPIO7_LEVEL_LOW: u1,
+                GPIO7_LEVEL_HIGH: u1,
+                GPIO7_EDGE_LOW: u1,
+                GPIO7_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Enable for proc1
+            PROC1_INTE1: mmio.Mmio(packed struct(u32) {
+                GPIO8_LEVEL_LOW: u1,
+                GPIO8_LEVEL_HIGH: u1,
+                GPIO8_EDGE_LOW: u1,
+                GPIO8_EDGE_HIGH: u1,
+                GPIO9_LEVEL_LOW: u1,
+                GPIO9_LEVEL_HIGH: u1,
+                GPIO9_EDGE_LOW: u1,
+                GPIO9_EDGE_HIGH: u1,
+                GPIO10_LEVEL_LOW: u1,
+                GPIO10_LEVEL_HIGH: u1,
+                GPIO10_EDGE_LOW: u1,
+                GPIO10_EDGE_HIGH: u1,
+                GPIO11_LEVEL_LOW: u1,
+                GPIO11_LEVEL_HIGH: u1,
+                GPIO11_EDGE_LOW: u1,
+                GPIO11_EDGE_HIGH: u1,
+                GPIO12_LEVEL_LOW: u1,
+                GPIO12_LEVEL_HIGH: u1,
+                GPIO12_EDGE_LOW: u1,
+                GPIO12_EDGE_HIGH: u1,
+                GPIO13_LEVEL_LOW: u1,
+                GPIO13_LEVEL_HIGH: u1,
+                GPIO13_EDGE_LOW: u1,
+                GPIO13_EDGE_HIGH: u1,
+                GPIO14_LEVEL_LOW: u1,
+                GPIO14_LEVEL_HIGH: u1,
+                GPIO14_EDGE_LOW: u1,
+                GPIO14_EDGE_HIGH: u1,
+                GPIO15_LEVEL_LOW: u1,
+                GPIO15_LEVEL_HIGH: u1,
+                GPIO15_EDGE_LOW: u1,
+                GPIO15_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Enable for proc1
+            PROC1_INTE2: mmio.Mmio(packed struct(u32) {
+                GPIO16_LEVEL_LOW: u1,
+                GPIO16_LEVEL_HIGH: u1,
+                GPIO16_EDGE_LOW: u1,
+                GPIO16_EDGE_HIGH: u1,
+                GPIO17_LEVEL_LOW: u1,
+                GPIO17_LEVEL_HIGH: u1,
+                GPIO17_EDGE_LOW: u1,
+                GPIO17_EDGE_HIGH: u1,
+                GPIO18_LEVEL_LOW: u1,
+                GPIO18_LEVEL_HIGH: u1,
+                GPIO18_EDGE_LOW: u1,
+                GPIO18_EDGE_HIGH: u1,
+                GPIO19_LEVEL_LOW: u1,
+                GPIO19_LEVEL_HIGH: u1,
+                GPIO19_EDGE_LOW: u1,
+                GPIO19_EDGE_HIGH: u1,
+                GPIO20_LEVEL_LOW: u1,
+                GPIO20_LEVEL_HIGH: u1,
+                GPIO20_EDGE_LOW: u1,
+                GPIO20_EDGE_HIGH: u1,
+                GPIO21_LEVEL_LOW: u1,
+                GPIO21_LEVEL_HIGH: u1,
+                GPIO21_EDGE_LOW: u1,
+                GPIO21_EDGE_HIGH: u1,
+                GPIO22_LEVEL_LOW: u1,
+                GPIO22_LEVEL_HIGH: u1,
+                GPIO22_EDGE_LOW: u1,
+                GPIO22_EDGE_HIGH: u1,
+                GPIO23_LEVEL_LOW: u1,
+                GPIO23_LEVEL_HIGH: u1,
+                GPIO23_EDGE_LOW: u1,
+                GPIO23_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Enable for proc1
+            PROC1_INTE3: mmio.Mmio(packed struct(u32) {
+                GPIO24_LEVEL_LOW: u1,
+                GPIO24_LEVEL_HIGH: u1,
+                GPIO24_EDGE_LOW: u1,
+                GPIO24_EDGE_HIGH: u1,
+                GPIO25_LEVEL_LOW: u1,
+                GPIO25_LEVEL_HIGH: u1,
+                GPIO25_EDGE_LOW: u1,
+                GPIO25_EDGE_HIGH: u1,
+                GPIO26_LEVEL_LOW: u1,
+                GPIO26_LEVEL_HIGH: u1,
+                GPIO26_EDGE_LOW: u1,
+                GPIO26_EDGE_HIGH: u1,
+                GPIO27_LEVEL_LOW: u1,
+                GPIO27_LEVEL_HIGH: u1,
+                GPIO27_EDGE_LOW: u1,
+                GPIO27_EDGE_HIGH: u1,
+                GPIO28_LEVEL_LOW: u1,
+                GPIO28_LEVEL_HIGH: u1,
+                GPIO28_EDGE_LOW: u1,
+                GPIO28_EDGE_HIGH: u1,
+                GPIO29_LEVEL_LOW: u1,
+                GPIO29_LEVEL_HIGH: u1,
+                GPIO29_EDGE_LOW: u1,
+                GPIO29_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Force for proc1
+            PROC1_INTF0: mmio.Mmio(packed struct(u32) {
+                GPIO0_LEVEL_LOW: u1,
+                GPIO0_LEVEL_HIGH: u1,
+                GPIO0_EDGE_LOW: u1,
+                GPIO0_EDGE_HIGH: u1,
+                GPIO1_LEVEL_LOW: u1,
+                GPIO1_LEVEL_HIGH: u1,
+                GPIO1_EDGE_LOW: u1,
+                GPIO1_EDGE_HIGH: u1,
+                GPIO2_LEVEL_LOW: u1,
+                GPIO2_LEVEL_HIGH: u1,
+                GPIO2_EDGE_LOW: u1,
+                GPIO2_EDGE_HIGH: u1,
+                GPIO3_LEVEL_LOW: u1,
+                GPIO3_LEVEL_HIGH: u1,
+                GPIO3_EDGE_LOW: u1,
+                GPIO3_EDGE_HIGH: u1,
+                GPIO4_LEVEL_LOW: u1,
+                GPIO4_LEVEL_HIGH: u1,
+                GPIO4_EDGE_LOW: u1,
+                GPIO4_EDGE_HIGH: u1,
+                GPIO5_LEVEL_LOW: u1,
+                GPIO5_LEVEL_HIGH: u1,
+                GPIO5_EDGE_LOW: u1,
+                GPIO5_EDGE_HIGH: u1,
+                GPIO6_LEVEL_LOW: u1,
+                GPIO6_LEVEL_HIGH: u1,
+                GPIO6_EDGE_LOW: u1,
+                GPIO6_EDGE_HIGH: u1,
+                GPIO7_LEVEL_LOW: u1,
+                GPIO7_LEVEL_HIGH: u1,
+                GPIO7_EDGE_LOW: u1,
+                GPIO7_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Force for proc1
+            PROC1_INTF1: mmio.Mmio(packed struct(u32) {
+                GPIO8_LEVEL_LOW: u1,
+                GPIO8_LEVEL_HIGH: u1,
+                GPIO8_EDGE_LOW: u1,
+                GPIO8_EDGE_HIGH: u1,
+                GPIO9_LEVEL_LOW: u1,
+                GPIO9_LEVEL_HIGH: u1,
+                GPIO9_EDGE_LOW: u1,
+                GPIO9_EDGE_HIGH: u1,
+                GPIO10_LEVEL_LOW: u1,
+                GPIO10_LEVEL_HIGH: u1,
+                GPIO10_EDGE_LOW: u1,
+                GPIO10_EDGE_HIGH: u1,
+                GPIO11_LEVEL_LOW: u1,
+                GPIO11_LEVEL_HIGH: u1,
+                GPIO11_EDGE_LOW: u1,
+                GPIO11_EDGE_HIGH: u1,
+                GPIO12_LEVEL_LOW: u1,
+                GPIO12_LEVEL_HIGH: u1,
+                GPIO12_EDGE_LOW: u1,
+                GPIO12_EDGE_HIGH: u1,
+                GPIO13_LEVEL_LOW: u1,
+                GPIO13_LEVEL_HIGH: u1,
+                GPIO13_EDGE_LOW: u1,
+                GPIO13_EDGE_HIGH: u1,
+                GPIO14_LEVEL_LOW: u1,
+                GPIO14_LEVEL_HIGH: u1,
+                GPIO14_EDGE_LOW: u1,
+                GPIO14_EDGE_HIGH: u1,
+                GPIO15_LEVEL_LOW: u1,
+                GPIO15_LEVEL_HIGH: u1,
+                GPIO15_EDGE_LOW: u1,
+                GPIO15_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Force for proc1
+            PROC1_INTF2: mmio.Mmio(packed struct(u32) {
+                GPIO16_LEVEL_LOW: u1,
+                GPIO16_LEVEL_HIGH: u1,
+                GPIO16_EDGE_LOW: u1,
+                GPIO16_EDGE_HIGH: u1,
+                GPIO17_LEVEL_LOW: u1,
+                GPIO17_LEVEL_HIGH: u1,
+                GPIO17_EDGE_LOW: u1,
+                GPIO17_EDGE_HIGH: u1,
+                GPIO18_LEVEL_LOW: u1,
+                GPIO18_LEVEL_HIGH: u1,
+                GPIO18_EDGE_LOW: u1,
+                GPIO18_EDGE_HIGH: u1,
+                GPIO19_LEVEL_LOW: u1,
+                GPIO19_LEVEL_HIGH: u1,
+                GPIO19_EDGE_LOW: u1,
+                GPIO19_EDGE_HIGH: u1,
+                GPIO20_LEVEL_LOW: u1,
+                GPIO20_LEVEL_HIGH: u1,
+                GPIO20_EDGE_LOW: u1,
+                GPIO20_EDGE_HIGH: u1,
+                GPIO21_LEVEL_LOW: u1,
+                GPIO21_LEVEL_HIGH: u1,
+                GPIO21_EDGE_LOW: u1,
+                GPIO21_EDGE_HIGH: u1,
+                GPIO22_LEVEL_LOW: u1,
+                GPIO22_LEVEL_HIGH: u1,
+                GPIO22_EDGE_LOW: u1,
+                GPIO22_EDGE_HIGH: u1,
+                GPIO23_LEVEL_LOW: u1,
+                GPIO23_LEVEL_HIGH: u1,
+                GPIO23_EDGE_LOW: u1,
+                GPIO23_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Force for proc1
+            PROC1_INTF3: mmio.Mmio(packed struct(u32) {
+                GPIO24_LEVEL_LOW: u1,
+                GPIO24_LEVEL_HIGH: u1,
+                GPIO24_EDGE_LOW: u1,
+                GPIO24_EDGE_HIGH: u1,
+                GPIO25_LEVEL_LOW: u1,
+                GPIO25_LEVEL_HIGH: u1,
+                GPIO25_EDGE_LOW: u1,
+                GPIO25_EDGE_HIGH: u1,
+                GPIO26_LEVEL_LOW: u1,
+                GPIO26_LEVEL_HIGH: u1,
+                GPIO26_EDGE_LOW: u1,
+                GPIO26_EDGE_HIGH: u1,
+                GPIO27_LEVEL_LOW: u1,
+                GPIO27_LEVEL_HIGH: u1,
+                GPIO27_EDGE_LOW: u1,
+                GPIO27_EDGE_HIGH: u1,
+                GPIO28_LEVEL_LOW: u1,
+                GPIO28_LEVEL_HIGH: u1,
+                GPIO28_EDGE_LOW: u1,
+                GPIO28_EDGE_HIGH: u1,
+                GPIO29_LEVEL_LOW: u1,
+                GPIO29_LEVEL_HIGH: u1,
+                GPIO29_EDGE_LOW: u1,
+                GPIO29_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt status after masking & forcing for proc1
+            PROC1_INTS0: mmio.Mmio(packed struct(u32) {
+                GPIO0_LEVEL_LOW: u1,
+                GPIO0_LEVEL_HIGH: u1,
+                GPIO0_EDGE_LOW: u1,
+                GPIO0_EDGE_HIGH: u1,
+                GPIO1_LEVEL_LOW: u1,
+                GPIO1_LEVEL_HIGH: u1,
+                GPIO1_EDGE_LOW: u1,
+                GPIO1_EDGE_HIGH: u1,
+                GPIO2_LEVEL_LOW: u1,
+                GPIO2_LEVEL_HIGH: u1,
+                GPIO2_EDGE_LOW: u1,
+                GPIO2_EDGE_HIGH: u1,
+                GPIO3_LEVEL_LOW: u1,
+                GPIO3_LEVEL_HIGH: u1,
+                GPIO3_EDGE_LOW: u1,
+                GPIO3_EDGE_HIGH: u1,
+                GPIO4_LEVEL_LOW: u1,
+                GPIO4_LEVEL_HIGH: u1,
+                GPIO4_EDGE_LOW: u1,
+                GPIO4_EDGE_HIGH: u1,
+                GPIO5_LEVEL_LOW: u1,
+                GPIO5_LEVEL_HIGH: u1,
+                GPIO5_EDGE_LOW: u1,
+                GPIO5_EDGE_HIGH: u1,
+                GPIO6_LEVEL_LOW: u1,
+                GPIO6_LEVEL_HIGH: u1,
+                GPIO6_EDGE_LOW: u1,
+                GPIO6_EDGE_HIGH: u1,
+                GPIO7_LEVEL_LOW: u1,
+                GPIO7_LEVEL_HIGH: u1,
+                GPIO7_EDGE_LOW: u1,
+                GPIO7_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt status after masking & forcing for proc1
+            PROC1_INTS1: mmio.Mmio(packed struct(u32) {
+                GPIO8_LEVEL_LOW: u1,
+                GPIO8_LEVEL_HIGH: u1,
+                GPIO8_EDGE_LOW: u1,
+                GPIO8_EDGE_HIGH: u1,
+                GPIO9_LEVEL_LOW: u1,
+                GPIO9_LEVEL_HIGH: u1,
+                GPIO9_EDGE_LOW: u1,
+                GPIO9_EDGE_HIGH: u1,
+                GPIO10_LEVEL_LOW: u1,
+                GPIO10_LEVEL_HIGH: u1,
+                GPIO10_EDGE_LOW: u1,
+                GPIO10_EDGE_HIGH: u1,
+                GPIO11_LEVEL_LOW: u1,
+                GPIO11_LEVEL_HIGH: u1,
+                GPIO11_EDGE_LOW: u1,
+                GPIO11_EDGE_HIGH: u1,
+                GPIO12_LEVEL_LOW: u1,
+                GPIO12_LEVEL_HIGH: u1,
+                GPIO12_EDGE_LOW: u1,
+                GPIO12_EDGE_HIGH: u1,
+                GPIO13_LEVEL_LOW: u1,
+                GPIO13_LEVEL_HIGH: u1,
+                GPIO13_EDGE_LOW: u1,
+                GPIO13_EDGE_HIGH: u1,
+                GPIO14_LEVEL_LOW: u1,
+                GPIO14_LEVEL_HIGH: u1,
+                GPIO14_EDGE_LOW: u1,
+                GPIO14_EDGE_HIGH: u1,
+                GPIO15_LEVEL_LOW: u1,
+                GPIO15_LEVEL_HIGH: u1,
+                GPIO15_EDGE_LOW: u1,
+                GPIO15_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt status after masking & forcing for proc1
+            PROC1_INTS2: mmio.Mmio(packed struct(u32) {
+                GPIO16_LEVEL_LOW: u1,
+                GPIO16_LEVEL_HIGH: u1,
+                GPIO16_EDGE_LOW: u1,
+                GPIO16_EDGE_HIGH: u1,
+                GPIO17_LEVEL_LOW: u1,
+                GPIO17_LEVEL_HIGH: u1,
+                GPIO17_EDGE_LOW: u1,
+                GPIO17_EDGE_HIGH: u1,
+                GPIO18_LEVEL_LOW: u1,
+                GPIO18_LEVEL_HIGH: u1,
+                GPIO18_EDGE_LOW: u1,
+                GPIO18_EDGE_HIGH: u1,
+                GPIO19_LEVEL_LOW: u1,
+                GPIO19_LEVEL_HIGH: u1,
+                GPIO19_EDGE_LOW: u1,
+                GPIO19_EDGE_HIGH: u1,
+                GPIO20_LEVEL_LOW: u1,
+                GPIO20_LEVEL_HIGH: u1,
+                GPIO20_EDGE_LOW: u1,
+                GPIO20_EDGE_HIGH: u1,
+                GPIO21_LEVEL_LOW: u1,
+                GPIO21_LEVEL_HIGH: u1,
+                GPIO21_EDGE_LOW: u1,
+                GPIO21_EDGE_HIGH: u1,
+                GPIO22_LEVEL_LOW: u1,
+                GPIO22_LEVEL_HIGH: u1,
+                GPIO22_EDGE_LOW: u1,
+                GPIO22_EDGE_HIGH: u1,
+                GPIO23_LEVEL_LOW: u1,
+                GPIO23_LEVEL_HIGH: u1,
+                GPIO23_EDGE_LOW: u1,
+                GPIO23_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt status after masking & forcing for proc1
+            PROC1_INTS3: mmio.Mmio(packed struct(u32) {
+                GPIO24_LEVEL_LOW: u1,
+                GPIO24_LEVEL_HIGH: u1,
+                GPIO24_EDGE_LOW: u1,
+                GPIO24_EDGE_HIGH: u1,
+                GPIO25_LEVEL_LOW: u1,
+                GPIO25_LEVEL_HIGH: u1,
+                GPIO25_EDGE_LOW: u1,
+                GPIO25_EDGE_HIGH: u1,
+                GPIO26_LEVEL_LOW: u1,
+                GPIO26_LEVEL_HIGH: u1,
+                GPIO26_EDGE_LOW: u1,
+                GPIO26_EDGE_HIGH: u1,
+                GPIO27_LEVEL_LOW: u1,
+                GPIO27_LEVEL_HIGH: u1,
+                GPIO27_EDGE_LOW: u1,
+                GPIO27_EDGE_HIGH: u1,
+                GPIO28_LEVEL_LOW: u1,
+                GPIO28_LEVEL_HIGH: u1,
+                GPIO28_EDGE_LOW: u1,
+                GPIO28_EDGE_HIGH: u1,
+                GPIO29_LEVEL_LOW: u1,
+                GPIO29_LEVEL_HIGH: u1,
+                GPIO29_EDGE_LOW: u1,
+                GPIO29_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Enable for dormant_wake
+            DORMANT_WAKE_INTE0: mmio.Mmio(packed struct(u32) {
+                GPIO0_LEVEL_LOW: u1,
+                GPIO0_LEVEL_HIGH: u1,
+                GPIO0_EDGE_LOW: u1,
+                GPIO0_EDGE_HIGH: u1,
+                GPIO1_LEVEL_LOW: u1,
+                GPIO1_LEVEL_HIGH: u1,
+                GPIO1_EDGE_LOW: u1,
+                GPIO1_EDGE_HIGH: u1,
+                GPIO2_LEVEL_LOW: u1,
+                GPIO2_LEVEL_HIGH: u1,
+                GPIO2_EDGE_LOW: u1,
+                GPIO2_EDGE_HIGH: u1,
+                GPIO3_LEVEL_LOW: u1,
+                GPIO3_LEVEL_HIGH: u1,
+                GPIO3_EDGE_LOW: u1,
+                GPIO3_EDGE_HIGH: u1,
+                GPIO4_LEVEL_LOW: u1,
+                GPIO4_LEVEL_HIGH: u1,
+                GPIO4_EDGE_LOW: u1,
+                GPIO4_EDGE_HIGH: u1,
+                GPIO5_LEVEL_LOW: u1,
+                GPIO5_LEVEL_HIGH: u1,
+                GPIO5_EDGE_LOW: u1,
+                GPIO5_EDGE_HIGH: u1,
+                GPIO6_LEVEL_LOW: u1,
+                GPIO6_LEVEL_HIGH: u1,
+                GPIO6_EDGE_LOW: u1,
+                GPIO6_EDGE_HIGH: u1,
+                GPIO7_LEVEL_LOW: u1,
+                GPIO7_LEVEL_HIGH: u1,
+                GPIO7_EDGE_LOW: u1,
+                GPIO7_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Enable for dormant_wake
+            DORMANT_WAKE_INTE1: mmio.Mmio(packed struct(u32) {
+                GPIO8_LEVEL_LOW: u1,
+                GPIO8_LEVEL_HIGH: u1,
+                GPIO8_EDGE_LOW: u1,
+                GPIO8_EDGE_HIGH: u1,
+                GPIO9_LEVEL_LOW: u1,
+                GPIO9_LEVEL_HIGH: u1,
+                GPIO9_EDGE_LOW: u1,
+                GPIO9_EDGE_HIGH: u1,
+                GPIO10_LEVEL_LOW: u1,
+                GPIO10_LEVEL_HIGH: u1,
+                GPIO10_EDGE_LOW: u1,
+                GPIO10_EDGE_HIGH: u1,
+                GPIO11_LEVEL_LOW: u1,
+                GPIO11_LEVEL_HIGH: u1,
+                GPIO11_EDGE_LOW: u1,
+                GPIO11_EDGE_HIGH: u1,
+                GPIO12_LEVEL_LOW: u1,
+                GPIO12_LEVEL_HIGH: u1,
+                GPIO12_EDGE_LOW: u1,
+                GPIO12_EDGE_HIGH: u1,
+                GPIO13_LEVEL_LOW: u1,
+                GPIO13_LEVEL_HIGH: u1,
+                GPIO13_EDGE_LOW: u1,
+                GPIO13_EDGE_HIGH: u1,
+                GPIO14_LEVEL_LOW: u1,
+                GPIO14_LEVEL_HIGH: u1,
+                GPIO14_EDGE_LOW: u1,
+                GPIO14_EDGE_HIGH: u1,
+                GPIO15_LEVEL_LOW: u1,
+                GPIO15_LEVEL_HIGH: u1,
+                GPIO15_EDGE_LOW: u1,
+                GPIO15_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Enable for dormant_wake
+            DORMANT_WAKE_INTE2: mmio.Mmio(packed struct(u32) {
+                GPIO16_LEVEL_LOW: u1,
+                GPIO16_LEVEL_HIGH: u1,
+                GPIO16_EDGE_LOW: u1,
+                GPIO16_EDGE_HIGH: u1,
+                GPIO17_LEVEL_LOW: u1,
+                GPIO17_LEVEL_HIGH: u1,
+                GPIO17_EDGE_LOW: u1,
+                GPIO17_EDGE_HIGH: u1,
+                GPIO18_LEVEL_LOW: u1,
+                GPIO18_LEVEL_HIGH: u1,
+                GPIO18_EDGE_LOW: u1,
+                GPIO18_EDGE_HIGH: u1,
+                GPIO19_LEVEL_LOW: u1,
+                GPIO19_LEVEL_HIGH: u1,
+                GPIO19_EDGE_LOW: u1,
+                GPIO19_EDGE_HIGH: u1,
+                GPIO20_LEVEL_LOW: u1,
+                GPIO20_LEVEL_HIGH: u1,
+                GPIO20_EDGE_LOW: u1,
+                GPIO20_EDGE_HIGH: u1,
+                GPIO21_LEVEL_LOW: u1,
+                GPIO21_LEVEL_HIGH: u1,
+                GPIO21_EDGE_LOW: u1,
+                GPIO21_EDGE_HIGH: u1,
+                GPIO22_LEVEL_LOW: u1,
+                GPIO22_LEVEL_HIGH: u1,
+                GPIO22_EDGE_LOW: u1,
+                GPIO22_EDGE_HIGH: u1,
+                GPIO23_LEVEL_LOW: u1,
+                GPIO23_LEVEL_HIGH: u1,
+                GPIO23_EDGE_LOW: u1,
+                GPIO23_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Enable for dormant_wake
+            DORMANT_WAKE_INTE3: mmio.Mmio(packed struct(u32) {
+                GPIO24_LEVEL_LOW: u1,
+                GPIO24_LEVEL_HIGH: u1,
+                GPIO24_EDGE_LOW: u1,
+                GPIO24_EDGE_HIGH: u1,
+                GPIO25_LEVEL_LOW: u1,
+                GPIO25_LEVEL_HIGH: u1,
+                GPIO25_EDGE_LOW: u1,
+                GPIO25_EDGE_HIGH: u1,
+                GPIO26_LEVEL_LOW: u1,
+                GPIO26_LEVEL_HIGH: u1,
+                GPIO26_EDGE_LOW: u1,
+                GPIO26_EDGE_HIGH: u1,
+                GPIO27_LEVEL_LOW: u1,
+                GPIO27_LEVEL_HIGH: u1,
+                GPIO27_EDGE_LOW: u1,
+                GPIO27_EDGE_HIGH: u1,
+                GPIO28_LEVEL_LOW: u1,
+                GPIO28_LEVEL_HIGH: u1,
+                GPIO28_EDGE_LOW: u1,
+                GPIO28_EDGE_HIGH: u1,
+                GPIO29_LEVEL_LOW: u1,
+                GPIO29_LEVEL_HIGH: u1,
+                GPIO29_EDGE_LOW: u1,
+                GPIO29_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Force for dormant_wake
+            DORMANT_WAKE_INTF0: mmio.Mmio(packed struct(u32) {
+                GPIO0_LEVEL_LOW: u1,
+                GPIO0_LEVEL_HIGH: u1,
+                GPIO0_EDGE_LOW: u1,
+                GPIO0_EDGE_HIGH: u1,
+                GPIO1_LEVEL_LOW: u1,
+                GPIO1_LEVEL_HIGH: u1,
+                GPIO1_EDGE_LOW: u1,
+                GPIO1_EDGE_HIGH: u1,
+                GPIO2_LEVEL_LOW: u1,
+                GPIO2_LEVEL_HIGH: u1,
+                GPIO2_EDGE_LOW: u1,
+                GPIO2_EDGE_HIGH: u1,
+                GPIO3_LEVEL_LOW: u1,
+                GPIO3_LEVEL_HIGH: u1,
+                GPIO3_EDGE_LOW: u1,
+                GPIO3_EDGE_HIGH: u1,
+                GPIO4_LEVEL_LOW: u1,
+                GPIO4_LEVEL_HIGH: u1,
+                GPIO4_EDGE_LOW: u1,
+                GPIO4_EDGE_HIGH: u1,
+                GPIO5_LEVEL_LOW: u1,
+                GPIO5_LEVEL_HIGH: u1,
+                GPIO5_EDGE_LOW: u1,
+                GPIO5_EDGE_HIGH: u1,
+                GPIO6_LEVEL_LOW: u1,
+                GPIO6_LEVEL_HIGH: u1,
+                GPIO6_EDGE_LOW: u1,
+                GPIO6_EDGE_HIGH: u1,
+                GPIO7_LEVEL_LOW: u1,
+                GPIO7_LEVEL_HIGH: u1,
+                GPIO7_EDGE_LOW: u1,
+                GPIO7_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Force for dormant_wake
+            DORMANT_WAKE_INTF1: mmio.Mmio(packed struct(u32) {
+                GPIO8_LEVEL_LOW: u1,
+                GPIO8_LEVEL_HIGH: u1,
+                GPIO8_EDGE_LOW: u1,
+                GPIO8_EDGE_HIGH: u1,
+                GPIO9_LEVEL_LOW: u1,
+                GPIO9_LEVEL_HIGH: u1,
+                GPIO9_EDGE_LOW: u1,
+                GPIO9_EDGE_HIGH: u1,
+                GPIO10_LEVEL_LOW: u1,
+                GPIO10_LEVEL_HIGH: u1,
+                GPIO10_EDGE_LOW: u1,
+                GPIO10_EDGE_HIGH: u1,
+                GPIO11_LEVEL_LOW: u1,
+                GPIO11_LEVEL_HIGH: u1,
+                GPIO11_EDGE_LOW: u1,
+                GPIO11_EDGE_HIGH: u1,
+                GPIO12_LEVEL_LOW: u1,
+                GPIO12_LEVEL_HIGH: u1,
+                GPIO12_EDGE_LOW: u1,
+                GPIO12_EDGE_HIGH: u1,
+                GPIO13_LEVEL_LOW: u1,
+                GPIO13_LEVEL_HIGH: u1,
+                GPIO13_EDGE_LOW: u1,
+                GPIO13_EDGE_HIGH: u1,
+                GPIO14_LEVEL_LOW: u1,
+                GPIO14_LEVEL_HIGH: u1,
+                GPIO14_EDGE_LOW: u1,
+                GPIO14_EDGE_HIGH: u1,
+                GPIO15_LEVEL_LOW: u1,
+                GPIO15_LEVEL_HIGH: u1,
+                GPIO15_EDGE_LOW: u1,
+                GPIO15_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Force for dormant_wake
+            DORMANT_WAKE_INTF2: mmio.Mmio(packed struct(u32) {
+                GPIO16_LEVEL_LOW: u1,
+                GPIO16_LEVEL_HIGH: u1,
+                GPIO16_EDGE_LOW: u1,
+                GPIO16_EDGE_HIGH: u1,
+                GPIO17_LEVEL_LOW: u1,
+                GPIO17_LEVEL_HIGH: u1,
+                GPIO17_EDGE_LOW: u1,
+                GPIO17_EDGE_HIGH: u1,
+                GPIO18_LEVEL_LOW: u1,
+                GPIO18_LEVEL_HIGH: u1,
+                GPIO18_EDGE_LOW: u1,
+                GPIO18_EDGE_HIGH: u1,
+                GPIO19_LEVEL_LOW: u1,
+                GPIO19_LEVEL_HIGH: u1,
+                GPIO19_EDGE_LOW: u1,
+                GPIO19_EDGE_HIGH: u1,
+                GPIO20_LEVEL_LOW: u1,
+                GPIO20_LEVEL_HIGH: u1,
+                GPIO20_EDGE_LOW: u1,
+                GPIO20_EDGE_HIGH: u1,
+                GPIO21_LEVEL_LOW: u1,
+                GPIO21_LEVEL_HIGH: u1,
+                GPIO21_EDGE_LOW: u1,
+                GPIO21_EDGE_HIGH: u1,
+                GPIO22_LEVEL_LOW: u1,
+                GPIO22_LEVEL_HIGH: u1,
+                GPIO22_EDGE_LOW: u1,
+                GPIO22_EDGE_HIGH: u1,
+                GPIO23_LEVEL_LOW: u1,
+                GPIO23_LEVEL_HIGH: u1,
+                GPIO23_EDGE_LOW: u1,
+                GPIO23_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt Force for dormant_wake
+            DORMANT_WAKE_INTF3: mmio.Mmio(packed struct(u32) {
+                GPIO24_LEVEL_LOW: u1,
+                GPIO24_LEVEL_HIGH: u1,
+                GPIO24_EDGE_LOW: u1,
+                GPIO24_EDGE_HIGH: u1,
+                GPIO25_LEVEL_LOW: u1,
+                GPIO25_LEVEL_HIGH: u1,
+                GPIO25_EDGE_LOW: u1,
+                GPIO25_EDGE_HIGH: u1,
+                GPIO26_LEVEL_LOW: u1,
+                GPIO26_LEVEL_HIGH: u1,
+                GPIO26_EDGE_LOW: u1,
+                GPIO26_EDGE_HIGH: u1,
+                GPIO27_LEVEL_LOW: u1,
+                GPIO27_LEVEL_HIGH: u1,
+                GPIO27_EDGE_LOW: u1,
+                GPIO27_EDGE_HIGH: u1,
+                GPIO28_LEVEL_LOW: u1,
+                GPIO28_LEVEL_HIGH: u1,
+                GPIO28_EDGE_LOW: u1,
+                GPIO28_EDGE_HIGH: u1,
+                GPIO29_LEVEL_LOW: u1,
+                GPIO29_LEVEL_HIGH: u1,
+                GPIO29_EDGE_LOW: u1,
+                GPIO29_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt status after masking & forcing for dormant_wake
+            DORMANT_WAKE_INTS0: mmio.Mmio(packed struct(u32) {
+                GPIO0_LEVEL_LOW: u1,
+                GPIO0_LEVEL_HIGH: u1,
+                GPIO0_EDGE_LOW: u1,
+                GPIO0_EDGE_HIGH: u1,
+                GPIO1_LEVEL_LOW: u1,
+                GPIO1_LEVEL_HIGH: u1,
+                GPIO1_EDGE_LOW: u1,
+                GPIO1_EDGE_HIGH: u1,
+                GPIO2_LEVEL_LOW: u1,
+                GPIO2_LEVEL_HIGH: u1,
+                GPIO2_EDGE_LOW: u1,
+                GPIO2_EDGE_HIGH: u1,
+                GPIO3_LEVEL_LOW: u1,
+                GPIO3_LEVEL_HIGH: u1,
+                GPIO3_EDGE_LOW: u1,
+                GPIO3_EDGE_HIGH: u1,
+                GPIO4_LEVEL_LOW: u1,
+                GPIO4_LEVEL_HIGH: u1,
+                GPIO4_EDGE_LOW: u1,
+                GPIO4_EDGE_HIGH: u1,
+                GPIO5_LEVEL_LOW: u1,
+                GPIO5_LEVEL_HIGH: u1,
+                GPIO5_EDGE_LOW: u1,
+                GPIO5_EDGE_HIGH: u1,
+                GPIO6_LEVEL_LOW: u1,
+                GPIO6_LEVEL_HIGH: u1,
+                GPIO6_EDGE_LOW: u1,
+                GPIO6_EDGE_HIGH: u1,
+                GPIO7_LEVEL_LOW: u1,
+                GPIO7_LEVEL_HIGH: u1,
+                GPIO7_EDGE_LOW: u1,
+                GPIO7_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt status after masking & forcing for dormant_wake
+            DORMANT_WAKE_INTS1: mmio.Mmio(packed struct(u32) {
+                GPIO8_LEVEL_LOW: u1,
+                GPIO8_LEVEL_HIGH: u1,
+                GPIO8_EDGE_LOW: u1,
+                GPIO8_EDGE_HIGH: u1,
+                GPIO9_LEVEL_LOW: u1,
+                GPIO9_LEVEL_HIGH: u1,
+                GPIO9_EDGE_LOW: u1,
+                GPIO9_EDGE_HIGH: u1,
+                GPIO10_LEVEL_LOW: u1,
+                GPIO10_LEVEL_HIGH: u1,
+                GPIO10_EDGE_LOW: u1,
+                GPIO10_EDGE_HIGH: u1,
+                GPIO11_LEVEL_LOW: u1,
+                GPIO11_LEVEL_HIGH: u1,
+                GPIO11_EDGE_LOW: u1,
+                GPIO11_EDGE_HIGH: u1,
+                GPIO12_LEVEL_LOW: u1,
+                GPIO12_LEVEL_HIGH: u1,
+                GPIO12_EDGE_LOW: u1,
+                GPIO12_EDGE_HIGH: u1,
+                GPIO13_LEVEL_LOW: u1,
+                GPIO13_LEVEL_HIGH: u1,
+                GPIO13_EDGE_LOW: u1,
+                GPIO13_EDGE_HIGH: u1,
+                GPIO14_LEVEL_LOW: u1,
+                GPIO14_LEVEL_HIGH: u1,
+                GPIO14_EDGE_LOW: u1,
+                GPIO14_EDGE_HIGH: u1,
+                GPIO15_LEVEL_LOW: u1,
+                GPIO15_LEVEL_HIGH: u1,
+                GPIO15_EDGE_LOW: u1,
+                GPIO15_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt status after masking & forcing for dormant_wake
+            DORMANT_WAKE_INTS2: mmio.Mmio(packed struct(u32) {
+                GPIO16_LEVEL_LOW: u1,
+                GPIO16_LEVEL_HIGH: u1,
+                GPIO16_EDGE_LOW: u1,
+                GPIO16_EDGE_HIGH: u1,
+                GPIO17_LEVEL_LOW: u1,
+                GPIO17_LEVEL_HIGH: u1,
+                GPIO17_EDGE_LOW: u1,
+                GPIO17_EDGE_HIGH: u1,
+                GPIO18_LEVEL_LOW: u1,
+                GPIO18_LEVEL_HIGH: u1,
+                GPIO18_EDGE_LOW: u1,
+                GPIO18_EDGE_HIGH: u1,
+                GPIO19_LEVEL_LOW: u1,
+                GPIO19_LEVEL_HIGH: u1,
+                GPIO19_EDGE_LOW: u1,
+                GPIO19_EDGE_HIGH: u1,
+                GPIO20_LEVEL_LOW: u1,
+                GPIO20_LEVEL_HIGH: u1,
+                GPIO20_EDGE_LOW: u1,
+                GPIO20_EDGE_HIGH: u1,
+                GPIO21_LEVEL_LOW: u1,
+                GPIO21_LEVEL_HIGH: u1,
+                GPIO21_EDGE_LOW: u1,
+                GPIO21_EDGE_HIGH: u1,
+                GPIO22_LEVEL_LOW: u1,
+                GPIO22_LEVEL_HIGH: u1,
+                GPIO22_EDGE_LOW: u1,
+                GPIO22_EDGE_HIGH: u1,
+                GPIO23_LEVEL_LOW: u1,
+                GPIO23_LEVEL_HIGH: u1,
+                GPIO23_EDGE_LOW: u1,
+                GPIO23_EDGE_HIGH: u1,
+            }),
+            ///  Interrupt status after masking & forcing for dormant_wake
+            DORMANT_WAKE_INTS3: mmio.Mmio(packed struct(u32) {
+                GPIO24_LEVEL_LOW: u1,
+                GPIO24_LEVEL_HIGH: u1,
+                GPIO24_EDGE_LOW: u1,
+                GPIO24_EDGE_HIGH: u1,
+                GPIO25_LEVEL_LOW: u1,
+                GPIO25_LEVEL_HIGH: u1,
+                GPIO25_EDGE_LOW: u1,
+                GPIO25_EDGE_HIGH: u1,
+                GPIO26_LEVEL_LOW: u1,
+                GPIO26_LEVEL_HIGH: u1,
+                GPIO26_EDGE_LOW: u1,
+                GPIO26_EDGE_HIGH: u1,
+                GPIO27_LEVEL_LOW: u1,
+                GPIO27_LEVEL_HIGH: u1,
+                GPIO27_EDGE_LOW: u1,
+                GPIO27_EDGE_HIGH: u1,
+                GPIO28_LEVEL_LOW: u1,
+                GPIO28_LEVEL_HIGH: u1,
+                GPIO28_EDGE_LOW: u1,
+                GPIO28_EDGE_HIGH: u1,
+                GPIO29_LEVEL_LOW: u1,
+                GPIO29_LEVEL_HIGH: u1,
+                GPIO29_EDGE_LOW: u1,
+                GPIO29_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+        };
+
+        pub const IO_QSPI = extern struct {
+            ///  GPIO status
+            GPIO_QSPI_SCLK_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO_QSPI_SCLK_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        xip_sclk = 0x0,
+                        sio_30 = 0x5,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO_QSPI_SS_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO_QSPI_SS_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        xip_ss_n = 0x0,
+                        sio_31 = 0x5,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO_QSPI_SD0_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO_QSPI_SD0_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        xip_sd0 = 0x0,
+                        sio_32 = 0x5,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO_QSPI_SD1_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO_QSPI_SD1_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        xip_sd1 = 0x0,
+                        sio_33 = 0x5,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO_QSPI_SD2_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO_QSPI_SD2_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        xip_sd2 = 0x0,
+                        sio_34 = 0x5,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  GPIO status
+            GPIO_QSPI_SD3_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  output signal from selected peripheral, before register override is applied
+                OUTFROMPERI: u1,
+                ///  output signal to pad after register override is applied
+                OUTTOPAD: u1,
+                reserved12: u2,
+                ///  output enable from selected peripheral, before register override is applied
+                OEFROMPERI: u1,
+                ///  output enable to pad after register override is applied
+                OETOPAD: u1,
+                reserved17: u3,
+                ///  input signal from pad, before override is applied
+                INFROMPAD: u1,
+                reserved19: u1,
+                ///  input signal to peripheral, after override is applied
+                INTOPERI: u1,
+                reserved24: u4,
+                ///  interrupt from pad before override is applied
+                IRQFROMPAD: u1,
+                reserved26: u1,
+                ///  interrupt to processors, after override is applied
+                IRQTOPROC: u1,
+                padding: u5,
+            }),
+            ///  GPIO control including function select and overrides.
+            GPIO_QSPI_SD3_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  0-31 -> selects pin function according to the gpio table
+                ///  31 == NULL
+                FUNCSEL: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        xip_sd3 = 0x0,
+                        sio_35 = 0x5,
+                        null = 0x1f,
+                        _,
+                    },
+                },
+                reserved8: u3,
+                OUTOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  drive output low
+                        LOW = 0x2,
+                        ///  drive output high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved12: u2,
+                OEOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  drive output enable from peripheral signal selected by funcsel
+                        NORMAL = 0x0,
+                        ///  drive output enable from inverse of peripheral signal selected by funcsel
+                        INVERT = 0x1,
+                        ///  disable output
+                        DISABLE = 0x2,
+                        ///  enable output
+                        ENABLE = 0x3,
+                    },
+                },
+                reserved16: u2,
+                INOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the peri input
+                        NORMAL = 0x0,
+                        ///  invert the peri input
+                        INVERT = 0x1,
+                        ///  drive peri input low
+                        LOW = 0x2,
+                        ///  drive peri input high
+                        HIGH = 0x3,
+                    },
+                },
+                reserved28: u10,
+                IRQOVER: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  don't invert the interrupt
+                        NORMAL = 0x0,
+                        ///  invert the interrupt
+                        INVERT = 0x1,
+                        ///  drive interrupt low
+                        LOW = 0x2,
+                        ///  drive interrupt high
+                        HIGH = 0x3,
+                    },
+                },
+                padding: u2,
+            }),
+            ///  Raw Interrupts
+            INTR: mmio.Mmio(packed struct(u32) {
+                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
+                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
+                GPIO_QSPI_SCLK_EDGE_LOW: u1,
+                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
+                GPIO_QSPI_SS_LEVEL_LOW: u1,
+                GPIO_QSPI_SS_LEVEL_HIGH: u1,
+                GPIO_QSPI_SS_EDGE_LOW: u1,
+                GPIO_QSPI_SS_EDGE_HIGH: u1,
+                GPIO_QSPI_SD0_LEVEL_LOW: u1,
+                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD0_EDGE_LOW: u1,
+                GPIO_QSPI_SD0_EDGE_HIGH: u1,
+                GPIO_QSPI_SD1_LEVEL_LOW: u1,
+                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD1_EDGE_LOW: u1,
+                GPIO_QSPI_SD1_EDGE_HIGH: u1,
+                GPIO_QSPI_SD2_LEVEL_LOW: u1,
+                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD2_EDGE_LOW: u1,
+                GPIO_QSPI_SD2_EDGE_HIGH: u1,
+                GPIO_QSPI_SD3_LEVEL_LOW: u1,
+                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD3_EDGE_LOW: u1,
+                GPIO_QSPI_SD3_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Enable for proc0
+            PROC0_INTE: mmio.Mmio(packed struct(u32) {
+                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
+                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
+                GPIO_QSPI_SCLK_EDGE_LOW: u1,
+                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
+                GPIO_QSPI_SS_LEVEL_LOW: u1,
+                GPIO_QSPI_SS_LEVEL_HIGH: u1,
+                GPIO_QSPI_SS_EDGE_LOW: u1,
+                GPIO_QSPI_SS_EDGE_HIGH: u1,
+                GPIO_QSPI_SD0_LEVEL_LOW: u1,
+                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD0_EDGE_LOW: u1,
+                GPIO_QSPI_SD0_EDGE_HIGH: u1,
+                GPIO_QSPI_SD1_LEVEL_LOW: u1,
+                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD1_EDGE_LOW: u1,
+                GPIO_QSPI_SD1_EDGE_HIGH: u1,
+                GPIO_QSPI_SD2_LEVEL_LOW: u1,
+                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD2_EDGE_LOW: u1,
+                GPIO_QSPI_SD2_EDGE_HIGH: u1,
+                GPIO_QSPI_SD3_LEVEL_LOW: u1,
+                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD3_EDGE_LOW: u1,
+                GPIO_QSPI_SD3_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Force for proc0
+            PROC0_INTF: mmio.Mmio(packed struct(u32) {
+                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
+                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
+                GPIO_QSPI_SCLK_EDGE_LOW: u1,
+                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
+                GPIO_QSPI_SS_LEVEL_LOW: u1,
+                GPIO_QSPI_SS_LEVEL_HIGH: u1,
+                GPIO_QSPI_SS_EDGE_LOW: u1,
+                GPIO_QSPI_SS_EDGE_HIGH: u1,
+                GPIO_QSPI_SD0_LEVEL_LOW: u1,
+                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD0_EDGE_LOW: u1,
+                GPIO_QSPI_SD0_EDGE_HIGH: u1,
+                GPIO_QSPI_SD1_LEVEL_LOW: u1,
+                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD1_EDGE_LOW: u1,
+                GPIO_QSPI_SD1_EDGE_HIGH: u1,
+                GPIO_QSPI_SD2_LEVEL_LOW: u1,
+                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD2_EDGE_LOW: u1,
+                GPIO_QSPI_SD2_EDGE_HIGH: u1,
+                GPIO_QSPI_SD3_LEVEL_LOW: u1,
+                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD3_EDGE_LOW: u1,
+                GPIO_QSPI_SD3_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt status after masking & forcing for proc0
+            PROC0_INTS: mmio.Mmio(packed struct(u32) {
+                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
+                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
+                GPIO_QSPI_SCLK_EDGE_LOW: u1,
+                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
+                GPIO_QSPI_SS_LEVEL_LOW: u1,
+                GPIO_QSPI_SS_LEVEL_HIGH: u1,
+                GPIO_QSPI_SS_EDGE_LOW: u1,
+                GPIO_QSPI_SS_EDGE_HIGH: u1,
+                GPIO_QSPI_SD0_LEVEL_LOW: u1,
+                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD0_EDGE_LOW: u1,
+                GPIO_QSPI_SD0_EDGE_HIGH: u1,
+                GPIO_QSPI_SD1_LEVEL_LOW: u1,
+                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD1_EDGE_LOW: u1,
+                GPIO_QSPI_SD1_EDGE_HIGH: u1,
+                GPIO_QSPI_SD2_LEVEL_LOW: u1,
+                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD2_EDGE_LOW: u1,
+                GPIO_QSPI_SD2_EDGE_HIGH: u1,
+                GPIO_QSPI_SD3_LEVEL_LOW: u1,
+                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD3_EDGE_LOW: u1,
+                GPIO_QSPI_SD3_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Enable for proc1
+            PROC1_INTE: mmio.Mmio(packed struct(u32) {
+                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
+                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
+                GPIO_QSPI_SCLK_EDGE_LOW: u1,
+                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
+                GPIO_QSPI_SS_LEVEL_LOW: u1,
+                GPIO_QSPI_SS_LEVEL_HIGH: u1,
+                GPIO_QSPI_SS_EDGE_LOW: u1,
+                GPIO_QSPI_SS_EDGE_HIGH: u1,
+                GPIO_QSPI_SD0_LEVEL_LOW: u1,
+                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD0_EDGE_LOW: u1,
+                GPIO_QSPI_SD0_EDGE_HIGH: u1,
+                GPIO_QSPI_SD1_LEVEL_LOW: u1,
+                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD1_EDGE_LOW: u1,
+                GPIO_QSPI_SD1_EDGE_HIGH: u1,
+                GPIO_QSPI_SD2_LEVEL_LOW: u1,
+                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD2_EDGE_LOW: u1,
+                GPIO_QSPI_SD2_EDGE_HIGH: u1,
+                GPIO_QSPI_SD3_LEVEL_LOW: u1,
+                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD3_EDGE_LOW: u1,
+                GPIO_QSPI_SD3_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Force for proc1
+            PROC1_INTF: mmio.Mmio(packed struct(u32) {
+                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
+                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
+                GPIO_QSPI_SCLK_EDGE_LOW: u1,
+                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
+                GPIO_QSPI_SS_LEVEL_LOW: u1,
+                GPIO_QSPI_SS_LEVEL_HIGH: u1,
+                GPIO_QSPI_SS_EDGE_LOW: u1,
+                GPIO_QSPI_SS_EDGE_HIGH: u1,
+                GPIO_QSPI_SD0_LEVEL_LOW: u1,
+                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD0_EDGE_LOW: u1,
+                GPIO_QSPI_SD0_EDGE_HIGH: u1,
+                GPIO_QSPI_SD1_LEVEL_LOW: u1,
+                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD1_EDGE_LOW: u1,
+                GPIO_QSPI_SD1_EDGE_HIGH: u1,
+                GPIO_QSPI_SD2_LEVEL_LOW: u1,
+                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD2_EDGE_LOW: u1,
+                GPIO_QSPI_SD2_EDGE_HIGH: u1,
+                GPIO_QSPI_SD3_LEVEL_LOW: u1,
+                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD3_EDGE_LOW: u1,
+                GPIO_QSPI_SD3_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt status after masking & forcing for proc1
+            PROC1_INTS: mmio.Mmio(packed struct(u32) {
+                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
+                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
+                GPIO_QSPI_SCLK_EDGE_LOW: u1,
+                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
+                GPIO_QSPI_SS_LEVEL_LOW: u1,
+                GPIO_QSPI_SS_LEVEL_HIGH: u1,
+                GPIO_QSPI_SS_EDGE_LOW: u1,
+                GPIO_QSPI_SS_EDGE_HIGH: u1,
+                GPIO_QSPI_SD0_LEVEL_LOW: u1,
+                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD0_EDGE_LOW: u1,
+                GPIO_QSPI_SD0_EDGE_HIGH: u1,
+                GPIO_QSPI_SD1_LEVEL_LOW: u1,
+                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD1_EDGE_LOW: u1,
+                GPIO_QSPI_SD1_EDGE_HIGH: u1,
+                GPIO_QSPI_SD2_LEVEL_LOW: u1,
+                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD2_EDGE_LOW: u1,
+                GPIO_QSPI_SD2_EDGE_HIGH: u1,
+                GPIO_QSPI_SD3_LEVEL_LOW: u1,
+                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD3_EDGE_LOW: u1,
+                GPIO_QSPI_SD3_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Enable for dormant_wake
+            DORMANT_WAKE_INTE: mmio.Mmio(packed struct(u32) {
+                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
+                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
+                GPIO_QSPI_SCLK_EDGE_LOW: u1,
+                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
+                GPIO_QSPI_SS_LEVEL_LOW: u1,
+                GPIO_QSPI_SS_LEVEL_HIGH: u1,
+                GPIO_QSPI_SS_EDGE_LOW: u1,
+                GPIO_QSPI_SS_EDGE_HIGH: u1,
+                GPIO_QSPI_SD0_LEVEL_LOW: u1,
+                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD0_EDGE_LOW: u1,
+                GPIO_QSPI_SD0_EDGE_HIGH: u1,
+                GPIO_QSPI_SD1_LEVEL_LOW: u1,
+                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD1_EDGE_LOW: u1,
+                GPIO_QSPI_SD1_EDGE_HIGH: u1,
+                GPIO_QSPI_SD2_LEVEL_LOW: u1,
+                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD2_EDGE_LOW: u1,
+                GPIO_QSPI_SD2_EDGE_HIGH: u1,
+                GPIO_QSPI_SD3_LEVEL_LOW: u1,
+                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD3_EDGE_LOW: u1,
+                GPIO_QSPI_SD3_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt Force for dormant_wake
+            DORMANT_WAKE_INTF: mmio.Mmio(packed struct(u32) {
+                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
+                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
+                GPIO_QSPI_SCLK_EDGE_LOW: u1,
+                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
+                GPIO_QSPI_SS_LEVEL_LOW: u1,
+                GPIO_QSPI_SS_LEVEL_HIGH: u1,
+                GPIO_QSPI_SS_EDGE_LOW: u1,
+                GPIO_QSPI_SS_EDGE_HIGH: u1,
+                GPIO_QSPI_SD0_LEVEL_LOW: u1,
+                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD0_EDGE_LOW: u1,
+                GPIO_QSPI_SD0_EDGE_HIGH: u1,
+                GPIO_QSPI_SD1_LEVEL_LOW: u1,
+                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD1_EDGE_LOW: u1,
+                GPIO_QSPI_SD1_EDGE_HIGH: u1,
+                GPIO_QSPI_SD2_LEVEL_LOW: u1,
+                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD2_EDGE_LOW: u1,
+                GPIO_QSPI_SD2_EDGE_HIGH: u1,
+                GPIO_QSPI_SD3_LEVEL_LOW: u1,
+                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD3_EDGE_LOW: u1,
+                GPIO_QSPI_SD3_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+            ///  Interrupt status after masking & forcing for dormant_wake
+            DORMANT_WAKE_INTS: mmio.Mmio(packed struct(u32) {
+                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
+                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
+                GPIO_QSPI_SCLK_EDGE_LOW: u1,
+                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
+                GPIO_QSPI_SS_LEVEL_LOW: u1,
+                GPIO_QSPI_SS_LEVEL_HIGH: u1,
+                GPIO_QSPI_SS_EDGE_LOW: u1,
+                GPIO_QSPI_SS_EDGE_HIGH: u1,
+                GPIO_QSPI_SD0_LEVEL_LOW: u1,
+                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD0_EDGE_LOW: u1,
+                GPIO_QSPI_SD0_EDGE_HIGH: u1,
+                GPIO_QSPI_SD1_LEVEL_LOW: u1,
+                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD1_EDGE_LOW: u1,
+                GPIO_QSPI_SD1_EDGE_HIGH: u1,
+                GPIO_QSPI_SD2_LEVEL_LOW: u1,
+                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD2_EDGE_LOW: u1,
+                GPIO_QSPI_SD2_EDGE_HIGH: u1,
+                GPIO_QSPI_SD3_LEVEL_LOW: u1,
+                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
+                GPIO_QSPI_SD3_EDGE_LOW: u1,
+                GPIO_QSPI_SD3_EDGE_HIGH: u1,
+                padding: u8,
+            }),
+        };
+
+        pub const PADS_BANK0 = extern struct {
+            ///  Voltage select. Per bank control
+            VOLTAGE_SELECT: mmio.Mmio(packed struct(u32) {
+                VOLTAGE_SELECT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Set voltage to 3.3V (DVDD >= 2V5)
+                        @"3v3" = 0x0,
+                        ///  Set voltage to 1.8V (DVDD <= 1V8)
+                        @"1v8" = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Pad control register
+            GPIO0: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO1: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO2: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO3: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO4: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO5: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO6: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO7: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO8: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO9: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO10: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO11: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO12: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO13: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO14: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO15: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO16: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO17: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO18: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO19: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO20: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO21: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO22: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO23: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO24: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO25: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO26: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO27: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO28: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO29: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            SWCLK: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            SWD: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+        };
+
+        pub const PADS_QSPI = extern struct {
+            ///  Voltage select. Per bank control
+            VOLTAGE_SELECT: mmio.Mmio(packed struct(u32) {
+                VOLTAGE_SELECT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Set voltage to 3.3V (DVDD >= 2V5)
+                        @"3v3" = 0x0,
+                        ///  Set voltage to 1.8V (DVDD <= 1V8)
+                        @"1v8" = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  Pad control register
+            GPIO_QSPI_SCLK: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO_QSPI_SD0: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO_QSPI_SD1: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO_QSPI_SD2: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO_QSPI_SD3: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+            ///  Pad control register
+            GPIO_QSPI_SS: mmio.Mmio(packed struct(u32) {
+                ///  Slew rate control. 1 = Fast, 0 = Slow
+                SLEWFAST: u1,
+                ///  Enable schmitt trigger
+                SCHMITT: u1,
+                ///  Pull down enable
+                PDE: u1,
+                ///  Pull up enable
+                PUE: u1,
+                ///  Drive strength.
+                DRIVE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"2mA" = 0x0,
+                        @"4mA" = 0x1,
+                        @"8mA" = 0x2,
+                        @"12mA" = 0x3,
+                    },
+                },
+                ///  Input enable
+                IE: u1,
+                ///  Output disable. Has priority over output enable from peripherals
+                OD: u1,
+                padding: u24,
+            }),
+        };
+
+        ///  Controls the crystal oscillator
+        pub const XOSC = extern struct {
+            ///  Crystal Oscillator Control
+            CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Frequency range. This resets to 0xAA0 and cannot be changed.
+                FREQ_RANGE: packed union {
+                    raw: u12,
+                    value: enum(u12) {
+                        @"1_15MHZ" = 0xaa0,
+                        RESERVED_1 = 0xaa1,
+                        RESERVED_2 = 0xaa2,
+                        RESERVED_3 = 0xaa3,
+                        _,
+                    },
+                },
+                ///  On power-up this field is initialised to DISABLE and the chip runs from the ROSC.
+                ///  If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.
+                ///  The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.
+                ENABLE: packed union {
+                    raw: u12,
+                    value: enum(u12) {
+                        DISABLE = 0xd1e,
+                        ENABLE = 0xfab,
+                        _,
+                    },
+                },
+                padding: u8,
+            }),
+            ///  Crystal Oscillator Status
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  The current frequency range setting, always reads 0
+                FREQ_RANGE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"1_15MHZ" = 0x0,
+                        RESERVED_1 = 0x1,
+                        RESERVED_2 = 0x2,
+                        RESERVED_3 = 0x3,
+                    },
+                },
+                reserved12: u10,
+                ///  Oscillator is enabled but not necessarily running and stable, resets to 0
+                ENABLED: u1,
+                reserved24: u11,
+                ///  An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT
+                BADWRITE: u1,
+                reserved31: u6,
+                ///  Oscillator is running and stable
+                STABLE: u1,
+            }),
+            ///  Crystal Oscillator pause control
+            ///  This is used to save power by pausing the XOSC
+            ///  On power-up this field is initialised to WAKE
+            ///  An invalid write will also select WAKE
+            ///  WARNING: stop the PLLs before selecting dormant mode
+            ///  WARNING: setup the irq before selecting dormant mode
+            DORMANT: u32,
+            ///  Controls the startup delay
+            STARTUP: mmio.Mmio(packed struct(u32) {
+                ///  in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.
+                DELAY: u14,
+                reserved20: u6,
+                ///  Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly.
+                X4: u1,
+                padding: u11,
+            }),
+            reserved28: [12]u8,
+            ///  A down counter running at the xosc frequency which counts to zero and stops.
+            ///  To start the counter write a non-zero value.
+            ///  Can be used for short software pauses when setting up time sensitive hardware.
+            COUNT: mmio.Mmio(packed struct(u32) {
+                COUNT: u8,
+                padding: u24,
+            }),
+        };
+
+        pub const PLL_SYS = extern struct {
+            ///  Control and Status
+            ///  GENERAL CONSTRAINTS:
+            ///  Reference clock frequency min=5MHz, max=800MHz
+            ///  Feedback divider min=16, max=320
+            ///  VCO frequency min=400MHz, max=1600MHz
+            CS: mmio.Mmio(packed struct(u32) {
+                ///  Divides the PLL input reference clock.
+                ///  Behaviour is undefined for div=0.
+                ///  PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.
+                REFDIV: u6,
+                reserved8: u2,
+                ///  Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.
+                BYPASS: u1,
+                reserved31: u22,
+                ///  PLL is locked
+                LOCK: u1,
+            }),
+            ///  Controls the PLL power modes.
+            PWR: mmio.Mmio(packed struct(u32) {
+                ///  PLL powerdown
+                ///  To save power set high when PLL output not required.
+                PD: u1,
+                reserved2: u1,
+                ///  PLL DSM powerdown
+                ///  Nothing is achieved by setting this low.
+                DSMPD: u1,
+                ///  PLL post divider powerdown
+                ///  To save power set high when PLL output not required or bypass=1.
+                POSTDIVPD: u1,
+                reserved5: u1,
+                ///  PLL VCO powerdown
+                ///  To save power set high when PLL output not required or bypass=1.
+                VCOPD: u1,
+                padding: u26,
+            }),
+            ///  Feedback divisor
+            ///  (note: this PLL does not support fractional division)
+            FBDIV_INT: mmio.Mmio(packed struct(u32) {
+                ///  see ctrl reg description for constraints
+                FBDIV_INT: u12,
+                padding: u20,
+            }),
+            ///  Controls the PLL post dividers for the primary output
+            ///  (note: this PLL does not have a secondary output)
+            ///  the primary output is driven from VCO divided by postdiv1*postdiv2
+            PRIM: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  divide by 1-7
+                POSTDIV2: u3,
+                reserved16: u1,
+                ///  divide by 1-7
+                POSTDIV1: u3,
+                padding: u13,
+            }),
+        };
+
+        pub const PPB = extern struct {
+            reserved57360: [57360]u8,
+            ///  Use the SysTick Control and Status Register to enable the SysTick features.
+            SYST_CSR: mmio.Mmio(packed struct(u32) {
+                ///  Enable SysTick counter:
+                ///  0 = Counter disabled.
+                ///  1 = Counter enabled.
+                ENABLE: u1,
+                ///  Enables SysTick exception request:
+                ///  0 = Counting down to zero does not assert the SysTick exception request.
+                ///  1 = Counting down to zero to asserts the SysTick exception request.
+                TICKINT: u1,
+                ///  SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.
+                ///  Selects the SysTick timer clock source:
+                ///  0 = External reference clock.
+                ///  1 = Processor clock.
+                CLKSOURCE: u1,
+                reserved16: u13,
+                ///  Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.
+                COUNTFLAG: u1,
+                padding: u15,
+            }),
+            ///  Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.
+            ///  To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.
+            SYST_RVR: mmio.Mmio(packed struct(u32) {
+                ///  Value to load into the SysTick Current Value Register when the counter reaches 0.
+                RELOAD: u24,
+                padding: u8,
+            }),
+            ///  Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.
+            SYST_CVR: mmio.Mmio(packed struct(u32) {
+                ///  Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
+                CURRENT: u24,
+                padding: u8,
+            }),
+            ///  Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.
+            SYST_CALIB: mmio.Mmio(packed struct(u32) {
+                ///  An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.
+                TENMS: u24,
+                reserved30: u6,
+                ///  If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).
+                SKEW: u1,
+                ///  If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.
+                NOREF: u1,
+            }),
+            reserved57600: [224]u8,
+            ///  Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.
+            ///  If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.
+            NVIC_ISER: mmio.Mmio(packed struct(u32) {
+                ///  Interrupt set-enable bits.
+                ///  Write:
+                ///  0 = No effect.
+                ///  1 = Enable interrupt.
+                ///  Read:
+                ///  0 = Interrupt disabled.
+                ///  1 = Interrupt enabled.
+                SETENA: u32,
+            }),
+            reserved57728: [124]u8,
+            ///  Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.
+            NVIC_ICER: mmio.Mmio(packed struct(u32) {
+                ///  Interrupt clear-enable bits.
+                ///  Write:
+                ///  0 = No effect.
+                ///  1 = Disable interrupt.
+                ///  Read:
+                ///  0 = Interrupt disabled.
+                ///  1 = Interrupt enabled.
+                CLRENA: u32,
+            }),
+            reserved57856: [124]u8,
+            ///  The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.
+            NVIC_ISPR: mmio.Mmio(packed struct(u32) {
+                ///  Interrupt set-pending bits.
+                ///  Write:
+                ///  0 = No effect.
+                ///  1 = Changes interrupt state to pending.
+                ///  Read:
+                ///  0 = Interrupt is not pending.
+                ///  1 = Interrupt is pending.
+                ///  Note: Writing 1 to the NVIC_ISPR bit corresponding to:
+                ///  An interrupt that is pending has no effect.
+                ///  A disabled interrupt sets the state of that interrupt to pending.
+                SETPEND: u32,
+            }),
+            reserved57984: [124]u8,
+            ///  Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.
+            NVIC_ICPR: mmio.Mmio(packed struct(u32) {
+                ///  Interrupt clear-pending bits.
+                ///  Write:
+                ///  0 = No effect.
+                ///  1 = Removes pending state and interrupt.
+                ///  Read:
+                ///  0 = Interrupt is not pending.
+                ///  1 = Interrupt is pending.
+                CLRPEND: u32,
+            }),
+            reserved58368: [380]u8,
+            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
+            ///  Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.
+            ///  These registers are only word-accessible
+            NVIC_IPR0: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  Priority of interrupt 0
+                IP_0: u2,
+                reserved14: u6,
+                ///  Priority of interrupt 1
+                IP_1: u2,
+                reserved22: u6,
+                ///  Priority of interrupt 2
+                IP_2: u2,
+                reserved30: u6,
+                ///  Priority of interrupt 3
+                IP_3: u2,
+            }),
+            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
+            NVIC_IPR1: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  Priority of interrupt 4
+                IP_4: u2,
+                reserved14: u6,
+                ///  Priority of interrupt 5
+                IP_5: u2,
+                reserved22: u6,
+                ///  Priority of interrupt 6
+                IP_6: u2,
+                reserved30: u6,
+                ///  Priority of interrupt 7
+                IP_7: u2,
+            }),
+            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
+            NVIC_IPR2: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  Priority of interrupt 8
+                IP_8: u2,
+                reserved14: u6,
+                ///  Priority of interrupt 9
+                IP_9: u2,
+                reserved22: u6,
+                ///  Priority of interrupt 10
+                IP_10: u2,
+                reserved30: u6,
+                ///  Priority of interrupt 11
+                IP_11: u2,
+            }),
+            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
+            NVIC_IPR3: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  Priority of interrupt 12
+                IP_12: u2,
+                reserved14: u6,
+                ///  Priority of interrupt 13
+                IP_13: u2,
+                reserved22: u6,
+                ///  Priority of interrupt 14
+                IP_14: u2,
+                reserved30: u6,
+                ///  Priority of interrupt 15
+                IP_15: u2,
+            }),
+            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
+            NVIC_IPR4: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  Priority of interrupt 16
+                IP_16: u2,
+                reserved14: u6,
+                ///  Priority of interrupt 17
+                IP_17: u2,
+                reserved22: u6,
+                ///  Priority of interrupt 18
+                IP_18: u2,
+                reserved30: u6,
+                ///  Priority of interrupt 19
+                IP_19: u2,
+            }),
+            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
+            NVIC_IPR5: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  Priority of interrupt 20
+                IP_20: u2,
+                reserved14: u6,
+                ///  Priority of interrupt 21
+                IP_21: u2,
+                reserved22: u6,
+                ///  Priority of interrupt 22
+                IP_22: u2,
+                reserved30: u6,
+                ///  Priority of interrupt 23
+                IP_23: u2,
+            }),
+            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
+            NVIC_IPR6: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  Priority of interrupt 24
+                IP_24: u2,
+                reserved14: u6,
+                ///  Priority of interrupt 25
+                IP_25: u2,
+                reserved22: u6,
+                ///  Priority of interrupt 26
+                IP_26: u2,
+                reserved30: u6,
+                ///  Priority of interrupt 27
+                IP_27: u2,
+            }),
+            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
+            NVIC_IPR7: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  Priority of interrupt 28
+                IP_28: u2,
+                reserved14: u6,
+                ///  Priority of interrupt 29
+                IP_29: u2,
+                reserved22: u6,
+                ///  Priority of interrupt 30
+                IP_30: u2,
+                reserved30: u6,
+                ///  Priority of interrupt 31
+                IP_31: u2,
+            }),
+            reserved60672: [2272]u8,
+            ///  Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.
+            CPUID: mmio.Mmio(packed struct(u32) {
+                ///  Minor revision number m in the rnpm revision status:
+                ///  0x1 = Patch 1.
+                REVISION: u4,
+                ///  Number of processor within family: 0xC60 = Cortex-M0+
+                PARTNO: u12,
+                ///  Constant that defines the architecture of the processor:
+                ///  0xC = ARMv6-M architecture.
+                ARCHITECTURE: u4,
+                ///  Major revision number n in the rnpm revision status:
+                ///  0x0 = Revision 0.
+                VARIANT: u4,
+                ///  Implementor code: 0x41 = ARM
+                IMPLEMENTER: u8,
+            }),
+            ///  Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.
+            ICSR: mmio.Mmio(packed struct(u32) {
+                ///  Active exception number field. Reset clears the VECTACTIVE field.
+                VECTACTIVE: u9,
+                reserved12: u3,
+                ///  Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.
+                VECTPENDING: u9,
+                reserved22: u1,
+                ///  External interrupt pending flag
+                ISRPENDING: u1,
+                ///  The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.
+                ISRPREEMPT: u1,
+                reserved25: u1,
+                ///  SysTick exception clear-pending bit.
+                ///  Write:
+                ///  0 = No effect.
+                ///  1 = Removes the pending state from the SysTick exception.
+                ///  This bit is WO. On a register read its value is Unknown.
+                PENDSTCLR: u1,
+                ///  SysTick exception set-pending bit.
+                ///  Write:
+                ///  0 = No effect.
+                ///  1 = Changes SysTick exception state to pending.
+                ///  Read:
+                ///  0 = SysTick exception is not pending.
+                ///  1 = SysTick exception is pending.
+                PENDSTSET: u1,
+                ///  PendSV clear-pending bit.
+                ///  Write:
+                ///  0 = No effect.
+                ///  1 = Removes the pending state from the PendSV exception.
+                PENDSVCLR: u1,
+                ///  PendSV set-pending bit.
+                ///  Write:
+                ///  0 = No effect.
+                ///  1 = Changes PendSV exception state to pending.
+                ///  Read:
+                ///  0 = PendSV exception is not pending.
+                ///  1 = PendSV exception is pending.
+                ///  Writing 1 to this bit is the only way to set the PendSV exception state to pending.
+                PENDSVSET: u1,
+                reserved31: u2,
+                ///  Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.
+                ///  NMI set-pending bit.
+                ///  Write:
+                ///  0 = No effect.
+                ///  1 = Changes NMI exception state to pending.
+                ///  Read:
+                ///  0 = NMI exception is not pending.
+                ///  1 = NMI exception is pending.
+                ///  Because NMI is the highest-priority exception, normally the processor enters the NMI
+                ///  exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears
+                ///  this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the
+                ///  NMI signal is reasserted while the processor is executing that handler.
+                NMIPENDSET: u1,
+            }),
+            ///  The VTOR holds the vector table offset address.
+            VTOR: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Bits [31:8] of the indicate the vector table offset address.
+                TBLOFF: u24,
+            }),
+            ///  Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.
+            AIRCR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.
+                VECTCLRACTIVE: u1,
+                ///  Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.
+                SYSRESETREQ: u1,
+                reserved15: u12,
+                ///  Data endianness implemented:
+                ///  0 = Little-endian.
+                ENDIANESS: u1,
+                ///  Register key:
+                ///  Reads as Unknown
+                ///  On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.
+                VECTKEY: u16,
+            }),
+            ///  System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.
+            SCR: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Indicates sleep-on-exit when returning from Handler mode to Thread mode:
+                ///  0 = Do not sleep when returning to Thread mode.
+                ///  1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.
+                ///  Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
+                SLEEPONEXIT: u1,
+                ///  Controls whether the processor uses sleep or deep sleep as its low power mode:
+                ///  0 = Sleep.
+                ///  1 = Deep sleep.
+                SLEEPDEEP: u1,
+                reserved4: u1,
+                ///  Send Event on Pending bit:
+                ///  0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
+                ///  1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
+                ///  When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the
+                ///  processor is not waiting for an event, the event is registered and affects the next WFE.
+                ///  The processor also wakes up on execution of an SEV instruction or an external event.
+                SEVONPEND: u1,
+                padding: u27,
+            }),
+            ///  The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.
+            CCR: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                ///  Always reads as one, indicates that all unaligned accesses generate a HardFault.
+                UNALIGN_TRP: u1,
+                reserved9: u5,
+                ///  Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.
+                STKALIGN: u1,
+                padding: u22,
+            }),
+            reserved60700: [4]u8,
+            ///  System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.
+            SHPR2: mmio.Mmio(packed struct(u32) {
+                reserved30: u30,
+                ///  Priority of system handler 11, SVCall
+                PRI_11: u2,
+            }),
+            ///  System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.
+            SHPR3: mmio.Mmio(packed struct(u32) {
+                reserved22: u22,
+                ///  Priority of system handler 14, PendSV
+                PRI_14: u2,
+                reserved30: u6,
+                ///  Priority of system handler 15, SysTick
+                PRI_15: u2,
+            }),
+            ///  Use the System Handler Control and State Register to determine or clear the pending status of SVCall.
+            SHCSR: mmio.Mmio(packed struct(u32) {
+                reserved15: u15,
+                ///  Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall.
+                SVCALLPENDED: u1,
+                padding: u16,
+            }),
+            reserved60816: [104]u8,
+            ///  Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.
+            MPU_TYPE: mmio.Mmio(packed struct(u32) {
+                ///  Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU.
+                SEPARATE: u1,
+                reserved8: u7,
+                ///  Number of regions supported by the MPU.
+                DREGION: u8,
+                ///  Instruction region. Reads as zero as ARMv6-M only supports a unified MPU.
+                IREGION: u8,
+                padding: u8,
+            }),
+            ///  Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.
+            MPU_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.
+                ///  0 = MPU disabled.
+                ///  1 = MPU enabled.
+                ENABLE: u1,
+                ///  Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.
+                ///  When the MPU is enabled:
+                ///  0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.
+                ///  1 = the MPU is enabled during HardFault and NMI handlers.
+                HFNMIENA: u1,
+                ///  Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.
+                ///  0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not
+                ///  covered by any enabled region causes a fault.
+                ///  1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.
+                ///  When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.
+                PRIVDEFENA: u1,
+                padding: u29,
+            }),
+            ///  Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.
+            MPU_RNR: mmio.Mmio(packed struct(u32) {
+                ///  Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.
+                ///  The MPU supports 8 memory regions, so the permitted values of this field are 0-7.
+                REGION: u4,
+                padding: u28,
+            }),
+            ///  Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.
+            MPU_RBAR: mmio.Mmio(packed struct(u32) {
+                ///  On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.
+                REGION: u4,
+                ///  On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.
+                ///  Write:
+                ///  0 = MPU_RNR not changed, and the processor:
+                ///  Updates the base address for the region specified in the MPU_RNR.
+                ///  Ignores the value of the REGION field.
+                ///  1 = The processor:
+                ///  Updates the value of the MPU_RNR to the value of the REGION field.
+                ///  Updates the base address for the region specified in the REGION field.
+                ///  Always reads as zero.
+                VALID: u1,
+                reserved8: u3,
+                ///  Base address of the region.
+                ADDR: u24,
+            }),
+            ///  Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.
+            MPU_RASR: mmio.Mmio(packed struct(u32) {
+                ///  Enables the region.
+                ENABLE: u1,
+                ///  Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes
+                SIZE: u5,
+                reserved8: u2,
+                ///  Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.
+                SRD: u8,
+                ///  The MPU Region Attribute field. Use to define the region attribute control.
+                ///  28 = XN: Instruction access disable bit:
+                ///  0 = Instruction fetches enabled.
+                ///  1 = Instruction fetches disabled.
+                ///  26:24 = AP: Access permission field
+                ///  18 = S: Shareable bit
+                ///  17 = C: Cacheable bit
+                ///  16 = B: Bufferable bit
+                ATTRS: u16,
+            }),
+        };
+
+        ///  Register block for busfabric control signals and performance counters
+        pub const BUSCTRL = extern struct {
+            ///  Set the priority of each master for bus arbitration.
+            BUS_PRIORITY: mmio.Mmio(packed struct(u32) {
+                ///  0 - low priority, 1 - high priority
+                PROC0: u1,
+                reserved4: u3,
+                ///  0 - low priority, 1 - high priority
+                PROC1: u1,
+                reserved8: u3,
+                ///  0 - low priority, 1 - high priority
+                DMA_R: u1,
+                reserved12: u3,
+                ///  0 - low priority, 1 - high priority
+                DMA_W: u1,
+                padding: u19,
+            }),
+            ///  Bus priority acknowledge
+            BUS_PRIORITY_ACK: mmio.Mmio(packed struct(u32) {
+                ///  Goes to 1 once all arbiters have registered the new global priority levels.
+                ///  Arbiters update their local priority when servicing a new nonsequential access.
+                ///  In normal circumstances this will happen almost immediately.
+                BUS_PRIORITY_ACK: u1,
+                padding: u31,
+            }),
+            ///  Bus fabric performance counter 0
+            PERFCTR0: mmio.Mmio(packed struct(u32) {
+                ///  Busfabric saturating performance counter 0
+                ///  Count some event signal from the busfabric arbiters.
+                ///  Write any value to clear. Select an event to count using PERFSEL0
+                PERFCTR0: u24,
+                padding: u8,
+            }),
+            ///  Bus fabric performance event select for PERFCTR0
+            PERFSEL0: mmio.Mmio(packed struct(u32) {
+                ///  Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
+                PERFSEL0: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        apb_contested = 0x0,
+                        apb = 0x1,
+                        fastperi_contested = 0x2,
+                        fastperi = 0x3,
+                        sram5_contested = 0x4,
+                        sram5 = 0x5,
+                        sram4_contested = 0x6,
+                        sram4 = 0x7,
+                        sram3_contested = 0x8,
+                        sram3 = 0x9,
+                        sram2_contested = 0xa,
+                        sram2 = 0xb,
+                        sram1_contested = 0xc,
+                        sram1 = 0xd,
+                        sram0_contested = 0xe,
+                        sram0 = 0xf,
+                        xip_main_contested = 0x10,
+                        xip_main = 0x11,
+                        rom_contested = 0x12,
+                        rom = 0x13,
+                        _,
+                    },
+                },
+                padding: u27,
+            }),
+            ///  Bus fabric performance counter 1
+            PERFCTR1: mmio.Mmio(packed struct(u32) {
+                ///  Busfabric saturating performance counter 1
+                ///  Count some event signal from the busfabric arbiters.
+                ///  Write any value to clear. Select an event to count using PERFSEL1
+                PERFCTR1: u24,
+                padding: u8,
+            }),
+            ///  Bus fabric performance event select for PERFCTR1
+            PERFSEL1: mmio.Mmio(packed struct(u32) {
+                ///  Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
+                PERFSEL1: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        apb_contested = 0x0,
+                        apb = 0x1,
+                        fastperi_contested = 0x2,
+                        fastperi = 0x3,
+                        sram5_contested = 0x4,
+                        sram5 = 0x5,
+                        sram4_contested = 0x6,
+                        sram4 = 0x7,
+                        sram3_contested = 0x8,
+                        sram3 = 0x9,
+                        sram2_contested = 0xa,
+                        sram2 = 0xb,
+                        sram1_contested = 0xc,
+                        sram1 = 0xd,
+                        sram0_contested = 0xe,
+                        sram0 = 0xf,
+                        xip_main_contested = 0x10,
+                        xip_main = 0x11,
+                        rom_contested = 0x12,
+                        rom = 0x13,
+                        _,
+                    },
+                },
+                padding: u27,
+            }),
+            ///  Bus fabric performance counter 2
+            PERFCTR2: mmio.Mmio(packed struct(u32) {
+                ///  Busfabric saturating performance counter 2
+                ///  Count some event signal from the busfabric arbiters.
+                ///  Write any value to clear. Select an event to count using PERFSEL2
+                PERFCTR2: u24,
+                padding: u8,
+            }),
+            ///  Bus fabric performance event select for PERFCTR2
+            PERFSEL2: mmio.Mmio(packed struct(u32) {
+                ///  Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
+                PERFSEL2: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        apb_contested = 0x0,
+                        apb = 0x1,
+                        fastperi_contested = 0x2,
+                        fastperi = 0x3,
+                        sram5_contested = 0x4,
+                        sram5 = 0x5,
+                        sram4_contested = 0x6,
+                        sram4 = 0x7,
+                        sram3_contested = 0x8,
+                        sram3 = 0x9,
+                        sram2_contested = 0xa,
+                        sram2 = 0xb,
+                        sram1_contested = 0xc,
+                        sram1 = 0xd,
+                        sram0_contested = 0xe,
+                        sram0 = 0xf,
+                        xip_main_contested = 0x10,
+                        xip_main = 0x11,
+                        rom_contested = 0x12,
+                        rom = 0x13,
+                        _,
+                    },
+                },
+                padding: u27,
+            }),
+            ///  Bus fabric performance counter 3
+            PERFCTR3: mmio.Mmio(packed struct(u32) {
+                ///  Busfabric saturating performance counter 3
+                ///  Count some event signal from the busfabric arbiters.
+                ///  Write any value to clear. Select an event to count using PERFSEL3
+                PERFCTR3: u24,
+                padding: u8,
+            }),
+            ///  Bus fabric performance event select for PERFCTR3
+            PERFSEL3: mmio.Mmio(packed struct(u32) {
+                ///  Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
+                PERFSEL3: packed union {
+                    raw: u5,
+                    value: enum(u5) {
+                        apb_contested = 0x0,
+                        apb = 0x1,
+                        fastperi_contested = 0x2,
+                        fastperi = 0x3,
+                        sram5_contested = 0x4,
+                        sram5 = 0x5,
+                        sram4_contested = 0x6,
+                        sram4 = 0x7,
+                        sram3_contested = 0x8,
+                        sram3 = 0x9,
+                        sram2_contested = 0xa,
+                        sram2 = 0xb,
+                        sram1_contested = 0xc,
+                        sram1 = 0xd,
+                        sram0_contested = 0xe,
+                        sram0 = 0xf,
+                        xip_main_contested = 0x10,
+                        xip_main = 0x11,
+                        rom_contested = 0x12,
+                        rom = 0x13,
+                        _,
+                    },
+                },
+                padding: u27,
+            }),
+        };
+
+        pub const UART0 = extern struct {
+            ///  Data Register, UARTDR
+            UARTDR: mmio.Mmio(packed struct(u32) {
+                ///  Receive (read) data character. Transmit (write) data character.
+                DATA: u8,
+                ///  Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.
+                FE: u1,
+                ///  Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.
+                PE: u1,
+                ///  Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.
+                BE: u1,
+                ///  Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.
+                OE: u1,
+                padding: u20,
+            }),
+            ///  Receive Status Register/Error Clear Register, UARTRSR/UARTECR
+            UARTRSR: mmio.Mmio(packed struct(u32) {
+                ///  Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
+                FE: u1,
+                ///  Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
+                PE: u1,
+                ///  Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.
+                BE: u1,
+                ///  Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.
+                OE: u1,
+                padding: u28,
+            }),
+            reserved24: [16]u8,
+            ///  Flag Register, UARTFR
+            UARTFR: mmio.Mmio(packed struct(u32) {
+                ///  Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.
+                CTS: u1,
+                ///  Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.
+                DSR: u1,
+                ///  Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.
+                DCD: u1,
+                ///  UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.
+                BUSY: u1,
+                ///  Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
+                RXFE: u1,
+                ///  Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
+                TXFF: u1,
+                ///  Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
+                RXFF: u1,
+                ///  Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.
+                TXFE: u1,
+                ///  Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.
+                RI: u1,
+                padding: u23,
+            }),
+            reserved32: [4]u8,
+            ///  IrDA Low-Power Counter Register, UARTILPR
+            UARTILPR: mmio.Mmio(packed struct(u32) {
+                ///  8-bit low-power divisor value. These bits are cleared to 0 at reset.
+                ILPDVSR: u8,
+                padding: u24,
+            }),
+            ///  Integer Baud Rate Register, UARTIBRD
+            UARTIBRD: mmio.Mmio(packed struct(u32) {
+                ///  The integer baud rate divisor. These bits are cleared to 0 on reset.
+                BAUD_DIVINT: u16,
+                padding: u16,
+            }),
+            ///  Fractional Baud Rate Register, UARTFBRD
+            UARTFBRD: mmio.Mmio(packed struct(u32) {
+                ///  The fractional baud rate divisor. These bits are cleared to 0 on reset.
+                BAUD_DIVFRAC: u6,
+                padding: u26,
+            }),
+            ///  Line Control Register, UARTLCR_H
+            UARTLCR_H: mmio.Mmio(packed struct(u32) {
+                ///  Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.
+                BRK: u1,
+                ///  Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.
+                PEN: u1,
+                ///  Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.
+                EPS: u1,
+                ///  Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.
+                STP2: u1,
+                ///  Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
+                FEN: u1,
+                ///  Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.
+                WLEN: u2,
+                ///  Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.
+                SPS: u1,
+                padding: u24,
+            }),
+            ///  Control Register, UARTCR
+            UARTCR: mmio.Mmio(packed struct(u32) {
+                ///  UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.
+                UARTEN: u1,
+                ///  SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.
+                SIREN: u1,
+                ///  SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.
+                SIRLP: u1,
+                reserved7: u4,
+                ///  Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.
+                LBE: u1,
+                ///  Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.
+                TXE: u1,
+                ///  Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.
+                RXE: u1,
+                ///  Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.
+                DTR: u1,
+                ///  Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.
+                RTS: u1,
+                ///  This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).
+                OUT1: u1,
+                ///  This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).
+                OUT2: u1,
+                ///  RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.
+                RTSEN: u1,
+                ///  CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.
+                CTSEN: u1,
+                padding: u16,
+            }),
+            ///  Interrupt FIFO Level Select Register, UARTIFLS
+            UARTIFLS: mmio.Mmio(packed struct(u32) {
+                ///  Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved.
+                TXIFLSEL: u3,
+                ///  Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.
+                RXIFLSEL: u3,
+                padding: u26,
+            }),
+            ///  Interrupt Mask Set/Clear Register, UARTIMSC
+            UARTIMSC: mmio.Mmio(packed struct(u32) {
+                ///  nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.
+                RIMIM: u1,
+                ///  nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.
+                CTSMIM: u1,
+                ///  nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.
+                DCDMIM: u1,
+                ///  nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.
+                DSRMIM: u1,
+                ///  Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.
+                RXIM: u1,
+                ///  Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.
+                TXIM: u1,
+                ///  Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.
+                RTIM: u1,
+                ///  Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.
+                FEIM: u1,
+                ///  Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.
+                PEIM: u1,
+                ///  Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.
+                BEIM: u1,
+                ///  Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.
+                OEIM: u1,
+                padding: u21,
+            }),
+            ///  Raw Interrupt Status Register, UARTRIS
+            UARTRIS: mmio.Mmio(packed struct(u32) {
+                ///  nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.
+                RIRMIS: u1,
+                ///  nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.
+                CTSRMIS: u1,
+                ///  nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.
+                DCDRMIS: u1,
+                ///  nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.
+                DSRRMIS: u1,
+                ///  Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.
+                RXRIS: u1,
+                ///  Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.
+                TXRIS: u1,
+                ///  Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a
+                RTRIS: u1,
+                ///  Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.
+                FERIS: u1,
+                ///  Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.
+                PERIS: u1,
+                ///  Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.
+                BERIS: u1,
+                ///  Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.
+                OERIS: u1,
+                padding: u21,
+            }),
+            ///  Masked Interrupt Status Register, UARTMIS
+            UARTMIS: mmio.Mmio(packed struct(u32) {
+                ///  nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.
+                RIMMIS: u1,
+                ///  nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.
+                CTSMMIS: u1,
+                ///  nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.
+                DCDMMIS: u1,
+                ///  nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.
+                DSRMMIS: u1,
+                ///  Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.
+                RXMIS: u1,
+                ///  Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.
+                TXMIS: u1,
+                ///  Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.
+                RTMIS: u1,
+                ///  Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.
+                FEMIS: u1,
+                ///  Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.
+                PEMIS: u1,
+                ///  Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.
+                BEMIS: u1,
+                ///  Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.
+                OEMIS: u1,
+                padding: u21,
+            }),
+            ///  Interrupt Clear Register, UARTICR
+            UARTICR: mmio.Mmio(packed struct(u32) {
+                ///  nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.
+                RIMIC: u1,
+                ///  nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.
+                CTSMIC: u1,
+                ///  nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.
+                DCDMIC: u1,
+                ///  nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.
+                DSRMIC: u1,
+                ///  Receive interrupt clear. Clears the UARTRXINTR interrupt.
+                RXIC: u1,
+                ///  Transmit interrupt clear. Clears the UARTTXINTR interrupt.
+                TXIC: u1,
+                ///  Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.
+                RTIC: u1,
+                ///  Framing error interrupt clear. Clears the UARTFEINTR interrupt.
+                FEIC: u1,
+                ///  Parity error interrupt clear. Clears the UARTPEINTR interrupt.
+                PEIC: u1,
+                ///  Break error interrupt clear. Clears the UARTBEINTR interrupt.
+                BEIC: u1,
+                ///  Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
+                OEIC: u1,
+                padding: u21,
+            }),
+            ///  DMA Control Register, UARTDMACR
+            UARTDMACR: mmio.Mmio(packed struct(u32) {
+                ///  Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
+                RXDMAE: u1,
+                ///  Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
+                TXDMAE: u1,
+                ///  DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.
+                DMAONERR: u1,
+                padding: u29,
+            }),
+            reserved4064: [3988]u8,
+            ///  UARTPeriphID0 Register
+            UARTPERIPHID0: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x11
+                PARTNUMBER0: u8,
+                padding: u24,
+            }),
+            ///  UARTPeriphID1 Register
+            UARTPERIPHID1: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x0
+                PARTNUMBER1: u4,
+                ///  These bits read back as 0x1
+                DESIGNER0: u4,
+                padding: u24,
+            }),
+            ///  UARTPeriphID2 Register
+            UARTPERIPHID2: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x4
+                DESIGNER1: u4,
+                ///  This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3
+                REVISION: u4,
+                padding: u24,
+            }),
+            ///  UARTPeriphID3 Register
+            UARTPERIPHID3: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x00
+                CONFIGURATION: u8,
+                padding: u24,
+            }),
+            ///  UARTPCellID0 Register
+            UARTPCELLID0: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x0D
+                UARTPCELLID0: u8,
+                padding: u24,
+            }),
+            ///  UARTPCellID1 Register
+            UARTPCELLID1: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0xF0
+                UARTPCELLID1: u8,
+                padding: u24,
+            }),
+            ///  UARTPCellID2 Register
+            UARTPCELLID2: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x05
+                UARTPCELLID2: u8,
+                padding: u24,
+            }),
+            ///  UARTPCellID3 Register
+            UARTPCELLID3: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0xB1
+                UARTPCELLID3: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  Single-cycle IO block
+        ///  Provides core-local and inter-core hardware for the two processors, with single-cycle access.
+        pub const SIO = extern struct {
+            ///  Processor core identifier
+            ///  Value is 0 when read from processor core 0, and 1 when read from processor core 1.
+            CPUID: u32,
+            ///  Input value for GPIO pins
+            GPIO_IN: mmio.Mmio(packed struct(u32) {
+                ///  Input value for GPIO0...29
+                GPIO_IN: u30,
+                padding: u2,
+            }),
+            ///  Input value for QSPI pins
+            GPIO_HI_IN: mmio.Mmio(packed struct(u32) {
+                ///  Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3
+                GPIO_HI_IN: u6,
+                padding: u26,
+            }),
+            reserved16: [4]u8,
+            ///  GPIO output value
+            GPIO_OUT: mmio.Mmio(packed struct(u32) {
+                ///  Set output level (1/0 -> high/low) for GPIO0...29.
+                ///  Reading back gives the last value written, NOT the input value from the pins.
+                ///  If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),
+                ///  the result is as though the write from core 0 took place first,
+                ///  and the write from core 1 was then applied to that intermediate result.
+                GPIO_OUT: u30,
+                padding: u2,
+            }),
+            ///  GPIO output value set
+            GPIO_OUT_SET: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`
+                GPIO_OUT_SET: u30,
+                padding: u2,
+            }),
+            ///  GPIO output value clear
+            GPIO_OUT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`
+                GPIO_OUT_CLR: u30,
+                padding: u2,
+            }),
+            ///  GPIO output value XOR
+            GPIO_OUT_XOR: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`
+                GPIO_OUT_XOR: u30,
+                padding: u2,
+            }),
+            ///  GPIO output enable
+            GPIO_OE: mmio.Mmio(packed struct(u32) {
+                ///  Set output enable (1/0 -> output/input) for GPIO0...29.
+                ///  Reading back gives the last value written.
+                ///  If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),
+                ///  the result is as though the write from core 0 took place first,
+                ///  and the write from core 1 was then applied to that intermediate result.
+                GPIO_OE: u30,
+                padding: u2,
+            }),
+            ///  GPIO output enable set
+            GPIO_OE_SET: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`
+                GPIO_OE_SET: u30,
+                padding: u2,
+            }),
+            ///  GPIO output enable clear
+            GPIO_OE_CLR: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`
+                GPIO_OE_CLR: u30,
+                padding: u2,
+            }),
+            ///  GPIO output enable XOR
+            GPIO_OE_XOR: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`
+                GPIO_OE_XOR: u30,
+                padding: u2,
+            }),
+            ///  QSPI output value
+            GPIO_HI_OUT: mmio.Mmio(packed struct(u32) {
+                ///  Set output level (1/0 -> high/low) for QSPI IO0...5.
+                ///  Reading back gives the last value written, NOT the input value from the pins.
+                ///  If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),
+                ///  the result is as though the write from core 0 took place first,
+                ///  and the write from core 1 was then applied to that intermediate result.
+                GPIO_HI_OUT: u6,
+                padding: u26,
+            }),
+            ///  QSPI output value set
+            GPIO_HI_OUT_SET: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`
+                GPIO_HI_OUT_SET: u6,
+                padding: u26,
+            }),
+            ///  QSPI output value clear
+            GPIO_HI_OUT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`
+                GPIO_HI_OUT_CLR: u6,
+                padding: u26,
+            }),
+            ///  QSPI output value XOR
+            GPIO_HI_OUT_XOR: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`
+                GPIO_HI_OUT_XOR: u6,
+                padding: u26,
+            }),
+            ///  QSPI output enable
+            GPIO_HI_OE: mmio.Mmio(packed struct(u32) {
+                ///  Set output enable (1/0 -> output/input) for QSPI IO0...5.
+                ///  Reading back gives the last value written.
+                ///  If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),
+                ///  the result is as though the write from core 0 took place first,
+                ///  and the write from core 1 was then applied to that intermediate result.
+                GPIO_HI_OE: u6,
+                padding: u26,
+            }),
+            ///  QSPI output enable set
+            GPIO_HI_OE_SET: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`
+                GPIO_HI_OE_SET: u6,
+                padding: u26,
+            }),
+            ///  QSPI output enable clear
+            GPIO_HI_OE_CLR: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`
+                GPIO_HI_OE_CLR: u6,
+                padding: u26,
+            }),
+            ///  QSPI output enable XOR
+            GPIO_HI_OE_XOR: mmio.Mmio(packed struct(u32) {
+                ///  Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`
+                GPIO_HI_OE_XOR: u6,
+                padding: u26,
+            }),
+            ///  Status register for inter-core FIFOs (mailboxes).
+            ///  There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
+            ///  Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
+            ///  Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
+            ///  The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
+            FIFO_ST: mmio.Mmio(packed struct(u32) {
+                ///  Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)
+                VLD: u1,
+                ///  Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)
+                RDY: u1,
+                ///  Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.
+                WOF: u1,
+                ///  Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.
+                ROE: u1,
+                padding: u28,
+            }),
+            ///  Write access to this core's TX FIFO
+            FIFO_WR: u32,
+            ///  Read access to this core's RX FIFO
+            FIFO_RD: u32,
+            ///  Spinlock state
+            ///  A bitmap containing the state of all 32 spinlocks (1=locked).
+            ///  Mainly intended for debugging.
+            SPINLOCK_ST: u32,
+            ///  Divider unsigned dividend
+            ///  Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.
+            ///  Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
+            ///  UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an
+            ///  unsigned calculation, and the S alias starts a signed calculation.
+            DIV_UDIVIDEND: u32,
+            ///  Divider unsigned divisor
+            ///  Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.
+            ///  Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
+            ///  UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an
+            ///  unsigned calculation, and the S alias starts a signed calculation.
+            DIV_UDIVISOR: u32,
+            ///  Divider signed dividend
+            ///  The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.
+            DIV_SDIVIDEND: u32,
+            ///  Divider signed divisor
+            ///  The same as UDIVISOR, but starts a signed calculation, rather than unsigned.
+            DIV_SDIVISOR: u32,
+            ///  Divider result quotient
+            ///  The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.
+            ///  For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.
+            ///  This register can be written to directly, for context save/restore purposes. This halts any
+            ///  in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
+            ///  Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order
+            ///  REMAINDER, QUOTIENT if CSR_DIRTY is used.
+            DIV_QUOTIENT: u32,
+            ///  Divider result remainder
+            ///  The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.
+            ///  For signed calculations, REMAINDER is negative only when DIVIDEND is negative.
+            ///  This register can be written to directly, for context save/restore purposes. This halts any
+            ///  in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
+            DIV_REMAINDER: u32,
+            ///  Control and status register for divider.
+            DIV_CSR: mmio.Mmio(packed struct(u32) {
+                ///  Reads as 0 when a calculation is in progress, 1 otherwise.
+                ///  Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no
+                ///  matter if one is already in progress.
+                ///  Writing to a result register will immediately terminate any in-progress calculation
+                ///  and set the READY and DIRTY flags.
+                READY: u1,
+                ///  Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.
+                ///  Software can use this flag to make save/restore more efficient (skip if not DIRTY).
+                ///  If the flag is used in this way, it's recommended to either read QUOTIENT only,
+                ///  or REMAINDER and then QUOTIENT, to prevent data loss on context switch.
+                DIRTY: u1,
+                padding: u30,
+            }),
+            reserved128: [4]u8,
+            ///  Read/write access to accumulator 0
+            INTERP0_ACCUM0: u32,
+            ///  Read/write access to accumulator 1
+            INTERP0_ACCUM1: u32,
+            ///  Read/write access to BASE0 register.
+            INTERP0_BASE0: u32,
+            ///  Read/write access to BASE1 register.
+            INTERP0_BASE1: u32,
+            ///  Read/write access to BASE2 register.
+            INTERP0_BASE2: u32,
+            ///  Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
+            INTERP0_POP_LANE0: u32,
+            ///  Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
+            INTERP0_POP_LANE1: u32,
+            ///  Read FULL result, and simultaneously write lane results to both accumulators (POP).
+            INTERP0_POP_FULL: u32,
+            ///  Read LANE0 result, without altering any internal state (PEEK).
+            INTERP0_PEEK_LANE0: u32,
+            ///  Read LANE1 result, without altering any internal state (PEEK).
+            INTERP0_PEEK_LANE1: u32,
+            ///  Read FULL result, without altering any internal state (PEEK).
+            INTERP0_PEEK_FULL: u32,
+            ///  Control register for lane 0
+            INTERP0_CTRL_LANE0: mmio.Mmio(packed struct(u32) {
+                ///  Logical right-shift applied to accumulator before masking
+                SHIFT: u5,
+                ///  The least-significant bit allowed to pass by the mask (inclusive)
+                MASK_LSB: u5,
+                ///  The most-significant bit allowed to pass by the mask (inclusive)
+                ///  Setting MSB < LSB may cause chip to turn inside-out
+                MASK_MSB: u5,
+                ///  If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
+                ///  before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
+                SIGNED: u1,
+                ///  If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.
+                ///  Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
+                CROSS_INPUT: u1,
+                ///  If 1, feed the opposite lane's result into this lane's accumulator on POP.
+                CROSS_RESULT: u1,
+                ///  If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
+                ADD_RAW: u1,
+                ///  ORed into bits 29:28 of the lane result presented to the processor on the bus.
+                ///  No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
+                ///  of pointers into flash or SRAM.
+                FORCE_MSB: u2,
+                ///  Only present on INTERP0 on each core. If BLEND mode is enabled:
+                ///  - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled
+                ///  by the 8 LSBs of lane 1 shift and mask value (a fractional number between
+                ///  0 and 255/256ths)
+                ///  - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)
+                ///  - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)
+                ///  LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.
+                BLEND: u1,
+                reserved23: u1,
+                ///  Indicates if any masked-off MSBs in ACCUM0 are set.
+                OVERF0: u1,
+                ///  Indicates if any masked-off MSBs in ACCUM1 are set.
+                OVERF1: u1,
+                ///  Set if either OVERF0 or OVERF1 is set.
+                OVERF: u1,
+                padding: u6,
+            }),
+            ///  Control register for lane 1
+            INTERP0_CTRL_LANE1: mmio.Mmio(packed struct(u32) {
+                ///  Logical right-shift applied to accumulator before masking
+                SHIFT: u5,
+                ///  The least-significant bit allowed to pass by the mask (inclusive)
+                MASK_LSB: u5,
+                ///  The most-significant bit allowed to pass by the mask (inclusive)
+                ///  Setting MSB < LSB may cause chip to turn inside-out
+                MASK_MSB: u5,
+                ///  If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
+                ///  before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.
+                SIGNED: u1,
+                ///  If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.
+                ///  Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
+                CROSS_INPUT: u1,
+                ///  If 1, feed the opposite lane's result into this lane's accumulator on POP.
+                CROSS_RESULT: u1,
+                ///  If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
+                ADD_RAW: u1,
+                ///  ORed into bits 29:28 of the lane result presented to the processor on the bus.
+                ///  No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
+                ///  of pointers into flash or SRAM.
+                FORCE_MSB: u2,
+                padding: u11,
+            }),
+            ///  Values written here are atomically added to ACCUM0
+            ///  Reading yields lane 0's raw shift and mask value (BASE0 not added).
+            INTERP0_ACCUM0_ADD: mmio.Mmio(packed struct(u32) {
+                INTERP0_ACCUM0_ADD: u24,
+                padding: u8,
+            }),
+            ///  Values written here are atomically added to ACCUM1
+            ///  Reading yields lane 1's raw shift and mask value (BASE1 not added).
+            INTERP0_ACCUM1_ADD: mmio.Mmio(packed struct(u32) {
+                INTERP0_ACCUM1_ADD: u24,
+                padding: u8,
+            }),
+            ///  On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
+            ///  Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.
+            INTERP0_BASE_1AND0: u32,
+            ///  Read/write access to accumulator 0
+            INTERP1_ACCUM0: u32,
+            ///  Read/write access to accumulator 1
+            INTERP1_ACCUM1: u32,
+            ///  Read/write access to BASE0 register.
+            INTERP1_BASE0: u32,
+            ///  Read/write access to BASE1 register.
+            INTERP1_BASE1: u32,
+            ///  Read/write access to BASE2 register.
+            INTERP1_BASE2: u32,
+            ///  Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
+            INTERP1_POP_LANE0: u32,
+            ///  Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
+            INTERP1_POP_LANE1: u32,
+            ///  Read FULL result, and simultaneously write lane results to both accumulators (POP).
+            INTERP1_POP_FULL: u32,
+            ///  Read LANE0 result, without altering any internal state (PEEK).
+            INTERP1_PEEK_LANE0: u32,
+            ///  Read LANE1 result, without altering any internal state (PEEK).
+            INTERP1_PEEK_LANE1: u32,
+            ///  Read FULL result, without altering any internal state (PEEK).
+            INTERP1_PEEK_FULL: u32,
+            ///  Control register for lane 0
+            INTERP1_CTRL_LANE0: mmio.Mmio(packed struct(u32) {
+                ///  Logical right-shift applied to accumulator before masking
+                SHIFT: u5,
+                ///  The least-significant bit allowed to pass by the mask (inclusive)
+                MASK_LSB: u5,
+                ///  The most-significant bit allowed to pass by the mask (inclusive)
+                ///  Setting MSB < LSB may cause chip to turn inside-out
+                MASK_MSB: u5,
+                ///  If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
+                ///  before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
+                SIGNED: u1,
+                ///  If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.
+                ///  Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
+                CROSS_INPUT: u1,
+                ///  If 1, feed the opposite lane's result into this lane's accumulator on POP.
+                CROSS_RESULT: u1,
+                ///  If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
+                ADD_RAW: u1,
+                ///  ORed into bits 29:28 of the lane result presented to the processor on the bus.
+                ///  No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
+                ///  of pointers into flash or SRAM.
+                FORCE_MSB: u2,
+                reserved22: u1,
+                ///  Only present on INTERP1 on each core. If CLAMP mode is enabled:
+                ///  - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of
+                ///  BASE0 and an upper bound of BASE1.
+                ///  - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED
+                CLAMP: u1,
+                ///  Indicates if any masked-off MSBs in ACCUM0 are set.
+                OVERF0: u1,
+                ///  Indicates if any masked-off MSBs in ACCUM1 are set.
+                OVERF1: u1,
+                ///  Set if either OVERF0 or OVERF1 is set.
+                OVERF: u1,
+                padding: u6,
+            }),
+            ///  Control register for lane 1
+            INTERP1_CTRL_LANE1: mmio.Mmio(packed struct(u32) {
+                ///  Logical right-shift applied to accumulator before masking
+                SHIFT: u5,
+                ///  The least-significant bit allowed to pass by the mask (inclusive)
+                MASK_LSB: u5,
+                ///  The most-significant bit allowed to pass by the mask (inclusive)
+                ///  Setting MSB < LSB may cause chip to turn inside-out
+                MASK_MSB: u5,
+                ///  If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
+                ///  before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.
+                SIGNED: u1,
+                ///  If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.
+                ///  Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
+                CROSS_INPUT: u1,
+                ///  If 1, feed the opposite lane's result into this lane's accumulator on POP.
+                CROSS_RESULT: u1,
+                ///  If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
+                ADD_RAW: u1,
+                ///  ORed into bits 29:28 of the lane result presented to the processor on the bus.
+                ///  No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
+                ///  of pointers into flash or SRAM.
+                FORCE_MSB: u2,
+                padding: u11,
+            }),
+            ///  Values written here are atomically added to ACCUM0
+            ///  Reading yields lane 0's raw shift and mask value (BASE0 not added).
+            INTERP1_ACCUM0_ADD: mmio.Mmio(packed struct(u32) {
+                INTERP1_ACCUM0_ADD: u24,
+                padding: u8,
+            }),
+            ///  Values written here are atomically added to ACCUM1
+            ///  Reading yields lane 1's raw shift and mask value (BASE1 not added).
+            INTERP1_ACCUM1_ADD: mmio.Mmio(packed struct(u32) {
+                INTERP1_ACCUM1_ADD: u24,
+                padding: u8,
+            }),
+            ///  On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
+            ///  Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.
+            INTERP1_BASE_1AND0: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK0: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK1: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK2: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK3: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK4: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK5: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK6: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK7: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK8: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK9: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK10: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK11: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK12: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK13: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK14: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK15: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK16: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK17: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK18: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK19: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK20: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK21: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK22: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK23: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK24: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK25: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK26: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK27: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK28: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK29: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK30: u32,
+            ///  Reading from a spinlock address will:
+            ///  - Return 0 if lock is already locked
+            ///  - Otherwise return nonzero, and simultaneously claim the lock
+            ///  Writing (any value) releases the lock.
+            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
+            ///  The value returned on success is 0x1 << lock number.
+            SPINLOCK31: u32,
+        };
+
+        pub const SPI0 = extern struct {
+            ///  Control register 0, SSPCR0 on page 3-4
+            SSPCR0: mmio.Mmio(packed struct(u32) {
+                ///  Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
+                DSS: u4,
+                ///  Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.
+                FRF: u2,
+                ///  SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.
+                SPO: u1,
+                ///  SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.
+                SPH: u1,
+                ///  Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.
+                SCR: u8,
+                padding: u16,
+            }),
+            ///  Control register 1, SSPCR1 on page 3-5
+            SSPCR1: mmio.Mmio(packed struct(u32) {
+                ///  Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.
+                LBM: u1,
+                ///  Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.
+                SSE: u1,
+                ///  Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.
+                MS: u1,
+                ///  Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.
+                SOD: u1,
+                padding: u28,
+            }),
+            ///  Data register, SSPDR on page 3-6
+            SSPDR: mmio.Mmio(packed struct(u32) {
+                ///  Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.
+                DATA: u16,
+                padding: u16,
+            }),
+            ///  Status register, SSPSR on page 3-7
+            SSPSR: mmio.Mmio(packed struct(u32) {
+                ///  Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.
+                TFE: u1,
+                ///  Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.
+                TNF: u1,
+                ///  Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.
+                RNE: u1,
+                ///  Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.
+                RFF: u1,
+                ///  PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.
+                BSY: u1,
+                padding: u27,
+            }),
+            ///  Clock prescale register, SSPCPSR on page 3-8
+            SSPCPSR: mmio.Mmio(packed struct(u32) {
+                ///  Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.
+                CPSDVSR: u8,
+                padding: u24,
+            }),
+            ///  Interrupt mask set or clear register, SSPIMSC on page 3-9
+            SSPIMSC: mmio.Mmio(packed struct(u32) {
+                ///  Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.
+                RORIM: u1,
+                ///  Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.
+                RTIM: u1,
+                ///  Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.
+                RXIM: u1,
+                ///  Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.
+                TXIM: u1,
+                padding: u28,
+            }),
+            ///  Raw interrupt status register, SSPRIS on page 3-10
+            SSPRIS: mmio.Mmio(packed struct(u32) {
+                ///  Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
+                RORRIS: u1,
+                ///  Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
+                RTRIS: u1,
+                ///  Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
+                RXRIS: u1,
+                ///  Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
+                TXRIS: u1,
+                padding: u28,
+            }),
+            ///  Masked interrupt status register, SSPMIS on page 3-11
+            SSPMIS: mmio.Mmio(packed struct(u32) {
+                ///  Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
+                RORMIS: u1,
+                ///  Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
+                RTMIS: u1,
+                ///  Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
+                RXMIS: u1,
+                ///  Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
+                TXMIS: u1,
+                padding: u28,
+            }),
+            ///  Interrupt clear register, SSPICR on page 3-11
+            SSPICR: mmio.Mmio(packed struct(u32) {
+                ///  Clears the SSPRORINTR interrupt
+                RORIC: u1,
+                ///  Clears the SSPRTINTR interrupt
+                RTIC: u1,
+                padding: u30,
+            }),
+            ///  DMA control register, SSPDMACR on page 3-12
+            SSPDMACR: mmio.Mmio(packed struct(u32) {
+                ///  Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
+                RXDMAE: u1,
+                ///  Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
+                TXDMAE: u1,
+                padding: u30,
+            }),
+            reserved4064: [4024]u8,
+            ///  Peripheral identification registers, SSPPeriphID0-3 on page 3-13
+            SSPPERIPHID0: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x22
+                PARTNUMBER0: u8,
+                padding: u24,
+            }),
+            ///  Peripheral identification registers, SSPPeriphID0-3 on page 3-13
+            SSPPERIPHID1: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x0
+                PARTNUMBER1: u4,
+                ///  These bits read back as 0x1
+                DESIGNER0: u4,
+                padding: u24,
+            }),
+            ///  Peripheral identification registers, SSPPeriphID0-3 on page 3-13
+            SSPPERIPHID2: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x4
+                DESIGNER1: u4,
+                ///  These bits return the peripheral revision
+                REVISION: u4,
+                padding: u24,
+            }),
+            ///  Peripheral identification registers, SSPPeriphID0-3 on page 3-13
+            SSPPERIPHID3: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x00
+                CONFIGURATION: u8,
+                padding: u24,
+            }),
+            ///  PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+            SSPPCELLID0: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x0D
+                SSPPCELLID0: u8,
+                padding: u24,
+            }),
+            ///  PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+            SSPPCELLID1: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0xF0
+                SSPPCELLID1: u8,
+                padding: u24,
+            }),
+            ///  PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+            SSPPCELLID2: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0x05
+                SSPPCELLID2: u8,
+                padding: u24,
+            }),
+            ///  PrimeCell identification registers, SSPPCellID0-3 on page 3-16
+            SSPPCELLID3: mmio.Mmio(packed struct(u32) {
+                ///  These bits read back as 0xB1
+                SSPPCELLID3: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  USB FS/LS controller device registers
+        pub const USBCTRL_REGS = extern struct {
+            ///  Device address and endpoint control
+            ADDR_ENDP: mmio.Mmio(packed struct(u32) {
+                ///  In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Device endpoint to send data to. Only valid for HOST mode.
+                ENDPOINT: u4,
+                padding: u12,
+            }),
+            ///  Interrupt endpoint 1. Only valid for HOST mode.
+            ADDR_ENDP1: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 2. Only valid for HOST mode.
+            ADDR_ENDP2: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 3. Only valid for HOST mode.
+            ADDR_ENDP3: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 4. Only valid for HOST mode.
+            ADDR_ENDP4: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 5. Only valid for HOST mode.
+            ADDR_ENDP5: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 6. Only valid for HOST mode.
+            ADDR_ENDP6: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 7. Only valid for HOST mode.
+            ADDR_ENDP7: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 8. Only valid for HOST mode.
+            ADDR_ENDP8: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 9. Only valid for HOST mode.
+            ADDR_ENDP9: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 10. Only valid for HOST mode.
+            ADDR_ENDP10: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 11. Only valid for HOST mode.
+            ADDR_ENDP11: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 12. Only valid for HOST mode.
+            ADDR_ENDP12: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 13. Only valid for HOST mode.
+            ADDR_ENDP13: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 14. Only valid for HOST mode.
+            ADDR_ENDP14: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Interrupt endpoint 15. Only valid for HOST mode.
+            ADDR_ENDP15: mmio.Mmio(packed struct(u32) {
+                ///  Device address
+                ADDRESS: u7,
+                reserved16: u9,
+                ///  Endpoint number of the interrupt endpoint
+                ENDPOINT: u4,
+                reserved25: u5,
+                ///  Direction of the interrupt endpoint. In=0, Out=1
+                INTEP_DIR: u1,
+                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
+                INTEP_PREAMBLE: u1,
+                padding: u5,
+            }),
+            ///  Main control register
+            MAIN_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Enable controller
+                CONTROLLER_EN: u1,
+                ///  Device mode = 0, Host mode = 1
+                HOST_NDEVICE: u1,
+                reserved31: u29,
+                ///  Reduced timings for simulation
+                SIM_TIMING: u1,
+            }),
+            ///  Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.
+            SOF_WR: mmio.Mmio(packed struct(u32) {
+                COUNT: u11,
+                padding: u21,
+            }),
+            ///  Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.
+            SOF_RD: mmio.Mmio(packed struct(u32) {
+                COUNT: u11,
+                padding: u21,
+            }),
+            ///  SIE control register
+            SIE_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Host: Start transaction
+                START_TRANS: u1,
+                ///  Host: Send Setup packet
+                SEND_SETUP: u1,
+                ///  Host: Send transaction (OUT from host)
+                SEND_DATA: u1,
+                ///  Host: Receive transaction (IN to host)
+                RECEIVE_DATA: u1,
+                ///  Host: Stop transaction
+                STOP_TRANS: u1,
+                reserved6: u1,
+                ///  Host: Preable enable for LS device on FS hub
+                PREAMBLE_EN: u1,
+                reserved8: u1,
+                ///  Host: Delay packet(s) until after SOF
+                SOF_SYNC: u1,
+                ///  Host: Enable SOF generation (for full speed bus)
+                SOF_EN: u1,
+                ///  Host: Enable keep alive packet (for low speed bus)
+                KEEP_ALIVE_EN: u1,
+                ///  Host: Enable VBUS
+                VBUS_EN: u1,
+                ///  Device: Remote wakeup. Device can initiate its own resume after suspend.
+                RESUME: u1,
+                ///  Host: Reset bus
+                RESET_BUS: u1,
+                reserved15: u1,
+                ///  Host: Enable pull down resistors
+                PULLDOWN_EN: u1,
+                ///  Device: Enable pull up resistor
+                PULLUP_EN: u1,
+                ///  Device: Pull-up strength (0=1K2, 1=2k3)
+                RPU_OPT: u1,
+                ///  Power down bus transceiver
+                TRANSCEIVER_PD: u1,
+                reserved24: u5,
+                ///  Direct control of DM
+                DIRECT_DM: u1,
+                ///  Direct control of DP
+                DIRECT_DP: u1,
+                ///  Direct bus drive enable
+                DIRECT_EN: u1,
+                ///  Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
+                EP0_INT_NAK: u1,
+                ///  Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0
+                EP0_INT_2BUF: u1,
+                ///  Device: Set bit in BUFF_STATUS for every buffer completed on EP0
+                EP0_INT_1BUF: u1,
+                ///  Device: EP0 single buffered = 0, double buffered = 1
+                EP0_DOUBLE_BUF: u1,
+                ///  Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
+                EP0_INT_STALL: u1,
+            }),
+            ///  SIE status register
+            SIE_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  Device: VBUS Detected
+                VBUS_DETECTED: u1,
+                reserved2: u1,
+                ///  USB bus line state
+                LINE_STATE: u2,
+                ///  Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.
+                SUSPENDED: u1,
+                reserved8: u3,
+                ///  Host: device speed. Disconnected = 00, LS = 01, FS = 10
+                SPEED: u2,
+                ///  VBUS over current detected
+                VBUS_OVER_CURR: u1,
+                ///  Host: Device has initiated a remote resume. Device: host has initiated a resume.
+                RESUME: u1,
+                reserved16: u4,
+                ///  Device: connected
+                CONNECTED: u1,
+                ///  Device: Setup packet received
+                SETUP_REC: u1,
+                ///  Transaction complete.
+                ///  Raised by device if:
+                ///  * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register
+                ///  Raised by host if:
+                ///  * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set
+                TRANS_COMPLETE: u1,
+                ///  Device: bus reset received
+                BUS_RESET: u1,
+                reserved24: u4,
+                ///  CRC Error. Raised by the Serial RX engine.
+                CRC_ERROR: u1,
+                ///  Bit Stuff Error. Raised by the Serial RX engine.
+                BIT_STUFF_ERROR: u1,
+                ///  RX overflow is raised by the Serial RX engine if the incoming data is too fast.
+                RX_OVERFLOW: u1,
+                ///  RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.
+                RX_TIMEOUT: u1,
+                ///  Host: NAK received
+                NAK_REC: u1,
+                ///  Host: STALL received
+                STALL_REC: u1,
+                ///  ACK received. Raised by both host and device.
+                ACK_REC: u1,
+                ///  Data Sequence Error.
+                ///  The device can raise a sequence error in the following conditions:
+                ///  * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM
+                ///  The host can raise a data sequence error in the following conditions:
+                ///  * An IN packet from the device has the wrong data PID
+                DATA_SEQ_ERROR: u1,
+            }),
+            ///  interrupt endpoint control register
+            INT_EP_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Host: Enable interrupt endpoint 1 -> 15
+                INT_EP_ACTIVE: u15,
+                padding: u16,
+            }),
+            ///  Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.
+            BUFF_STATUS: mmio.Mmio(packed struct(u32) {
+                EP0_IN: u1,
+                EP0_OUT: u1,
+                EP1_IN: u1,
+                EP1_OUT: u1,
+                EP2_IN: u1,
+                EP2_OUT: u1,
+                EP3_IN: u1,
+                EP3_OUT: u1,
+                EP4_IN: u1,
+                EP4_OUT: u1,
+                EP5_IN: u1,
+                EP5_OUT: u1,
+                EP6_IN: u1,
+                EP6_OUT: u1,
+                EP7_IN: u1,
+                EP7_OUT: u1,
+                EP8_IN: u1,
+                EP8_OUT: u1,
+                EP9_IN: u1,
+                EP9_OUT: u1,
+                EP10_IN: u1,
+                EP10_OUT: u1,
+                EP11_IN: u1,
+                EP11_OUT: u1,
+                EP12_IN: u1,
+                EP12_OUT: u1,
+                EP13_IN: u1,
+                EP13_OUT: u1,
+                EP14_IN: u1,
+                EP14_OUT: u1,
+                EP15_IN: u1,
+                EP15_OUT: u1,
+            }),
+            ///  Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.
+            BUFF_CPU_SHOULD_HANDLE: mmio.Mmio(packed struct(u32) {
+                EP0_IN: u1,
+                EP0_OUT: u1,
+                EP1_IN: u1,
+                EP1_OUT: u1,
+                EP2_IN: u1,
+                EP2_OUT: u1,
+                EP3_IN: u1,
+                EP3_OUT: u1,
+                EP4_IN: u1,
+                EP4_OUT: u1,
+                EP5_IN: u1,
+                EP5_OUT: u1,
+                EP6_IN: u1,
+                EP6_OUT: u1,
+                EP7_IN: u1,
+                EP7_OUT: u1,
+                EP8_IN: u1,
+                EP8_OUT: u1,
+                EP9_IN: u1,
+                EP9_OUT: u1,
+                EP10_IN: u1,
+                EP10_OUT: u1,
+                EP11_IN: u1,
+                EP11_OUT: u1,
+                EP12_IN: u1,
+                EP12_OUT: u1,
+                EP13_IN: u1,
+                EP13_OUT: u1,
+                EP14_IN: u1,
+                EP14_OUT: u1,
+                EP15_IN: u1,
+                EP15_OUT: u1,
+            }),
+            ///  Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.
+            EP_ABORT: mmio.Mmio(packed struct(u32) {
+                EP0_IN: u1,
+                EP0_OUT: u1,
+                EP1_IN: u1,
+                EP1_OUT: u1,
+                EP2_IN: u1,
+                EP2_OUT: u1,
+                EP3_IN: u1,
+                EP3_OUT: u1,
+                EP4_IN: u1,
+                EP4_OUT: u1,
+                EP5_IN: u1,
+                EP5_OUT: u1,
+                EP6_IN: u1,
+                EP6_OUT: u1,
+                EP7_IN: u1,
+                EP7_OUT: u1,
+                EP8_IN: u1,
+                EP8_OUT: u1,
+                EP9_IN: u1,
+                EP9_OUT: u1,
+                EP10_IN: u1,
+                EP10_OUT: u1,
+                EP11_IN: u1,
+                EP11_OUT: u1,
+                EP12_IN: u1,
+                EP12_OUT: u1,
+                EP13_IN: u1,
+                EP13_OUT: u1,
+                EP14_IN: u1,
+                EP14_OUT: u1,
+                EP15_IN: u1,
+                EP15_OUT: u1,
+            }),
+            ///  Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.
+            EP_ABORT_DONE: mmio.Mmio(packed struct(u32) {
+                EP0_IN: u1,
+                EP0_OUT: u1,
+                EP1_IN: u1,
+                EP1_OUT: u1,
+                EP2_IN: u1,
+                EP2_OUT: u1,
+                EP3_IN: u1,
+                EP3_OUT: u1,
+                EP4_IN: u1,
+                EP4_OUT: u1,
+                EP5_IN: u1,
+                EP5_OUT: u1,
+                EP6_IN: u1,
+                EP6_OUT: u1,
+                EP7_IN: u1,
+                EP7_OUT: u1,
+                EP8_IN: u1,
+                EP8_OUT: u1,
+                EP9_IN: u1,
+                EP9_OUT: u1,
+                EP10_IN: u1,
+                EP10_OUT: u1,
+                EP11_IN: u1,
+                EP11_OUT: u1,
+                EP12_IN: u1,
+                EP12_OUT: u1,
+                EP13_IN: u1,
+                EP13_OUT: u1,
+                EP14_IN: u1,
+                EP14_OUT: u1,
+                EP15_IN: u1,
+                EP15_OUT: u1,
+            }),
+            ///  Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.
+            EP_STALL_ARM: mmio.Mmio(packed struct(u32) {
+                EP0_IN: u1,
+                EP0_OUT: u1,
+                padding: u30,
+            }),
+            ///  Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.
+            NAK_POLL: mmio.Mmio(packed struct(u32) {
+                ///  NAK polling interval for a low speed device
+                DELAY_LS: u10,
+                reserved16: u6,
+                ///  NAK polling interval for a full speed device
+                DELAY_FS: u10,
+                padding: u6,
+            }),
+            ///  Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.
+            EP_STATUS_STALL_NAK: mmio.Mmio(packed struct(u32) {
+                EP0_IN: u1,
+                EP0_OUT: u1,
+                EP1_IN: u1,
+                EP1_OUT: u1,
+                EP2_IN: u1,
+                EP2_OUT: u1,
+                EP3_IN: u1,
+                EP3_OUT: u1,
+                EP4_IN: u1,
+                EP4_OUT: u1,
+                EP5_IN: u1,
+                EP5_OUT: u1,
+                EP6_IN: u1,
+                EP6_OUT: u1,
+                EP7_IN: u1,
+                EP7_OUT: u1,
+                EP8_IN: u1,
+                EP8_OUT: u1,
+                EP9_IN: u1,
+                EP9_OUT: u1,
+                EP10_IN: u1,
+                EP10_OUT: u1,
+                EP11_IN: u1,
+                EP11_OUT: u1,
+                EP12_IN: u1,
+                EP12_OUT: u1,
+                EP13_IN: u1,
+                EP13_OUT: u1,
+                EP14_IN: u1,
+                EP14_OUT: u1,
+                EP15_IN: u1,
+                EP15_OUT: u1,
+            }),
+            ///  Where to connect the USB controller. Should be to_phy by default.
+            USB_MUXING: mmio.Mmio(packed struct(u32) {
+                TO_PHY: u1,
+                TO_EXTPHY: u1,
+                TO_DIGITAL_PAD: u1,
+                SOFTCON: u1,
+                padding: u28,
+            }),
+            ///  Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.
+            USB_PWR: mmio.Mmio(packed struct(u32) {
+                VBUS_EN: u1,
+                VBUS_EN_OVERRIDE_EN: u1,
+                VBUS_DETECT: u1,
+                VBUS_DETECT_OVERRIDE_EN: u1,
+                OVERCURR_DETECT: u1,
+                OVERCURR_DETECT_EN: u1,
+                padding: u26,
+            }),
+            ///  This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.
+            USBPHY_DIRECT: mmio.Mmio(packed struct(u32) {
+                ///  Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2
+                DP_PULLUP_HISEL: u1,
+                ///  DP pull up enable
+                DP_PULLUP_EN: u1,
+                ///  DP pull down enable
+                DP_PULLDN_EN: u1,
+                reserved4: u1,
+                ///  Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2
+                DM_PULLUP_HISEL: u1,
+                ///  DM pull up enable
+                DM_PULLUP_EN: u1,
+                ///  DM pull down enable
+                DM_PULLDN_EN: u1,
+                reserved8: u1,
+                ///  Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving
+                ///  If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving
+                TX_DP_OE: u1,
+                ///  Output enable. If TX_DIFFMODE=1, Ignored.
+                ///  If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving
+                TX_DM_OE: u1,
+                ///  Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP
+                ///  If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP
+                TX_DP: u1,
+                ///  Output data. TX_DIFFMODE=1, Ignored
+                ///  TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM
+                TX_DM: u1,
+                ///  RX power down override (if override enable is set). 1 = powered down.
+                RX_PD: u1,
+                ///  TX power down override (if override enable is set). 1 = powered down.
+                TX_PD: u1,
+                ///  TX_FSSLEW=0: Low speed slew rate
+                ///  TX_FSSLEW=1: Full speed slew rate
+                TX_FSSLEW: u1,
+                ///  TX_DIFFMODE=0: Single ended mode
+                ///  TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)
+                TX_DIFFMODE: u1,
+                ///  Differential RX
+                RX_DD: u1,
+                ///  DPP pin state
+                RX_DP: u1,
+                ///  DPM pin state
+                RX_DM: u1,
+                ///  DP overcurrent
+                DP_OVCN: u1,
+                ///  DM overcurrent
+                DM_OVCN: u1,
+                ///  DP over voltage
+                DP_OVV: u1,
+                ///  DM over voltage
+                DM_OVV: u1,
+                padding: u9,
+            }),
+            ///  Override enable for each control in usbphy_direct
+            USBPHY_DIRECT_OVERRIDE: mmio.Mmio(packed struct(u32) {
+                DP_PULLUP_HISEL_OVERRIDE_EN: u1,
+                DM_PULLUP_HISEL_OVERRIDE_EN: u1,
+                DP_PULLUP_EN_OVERRIDE_EN: u1,
+                DP_PULLDN_EN_OVERRIDE_EN: u1,
+                DM_PULLDN_EN_OVERRIDE_EN: u1,
+                TX_DP_OE_OVERRIDE_EN: u1,
+                TX_DM_OE_OVERRIDE_EN: u1,
+                TX_DP_OVERRIDE_EN: u1,
+                TX_DM_OVERRIDE_EN: u1,
+                RX_PD_OVERRIDE_EN: u1,
+                TX_PD_OVERRIDE_EN: u1,
+                TX_FSSLEW_OVERRIDE_EN: u1,
+                DM_PULLUP_OVERRIDE_EN: u1,
+                reserved15: u2,
+                TX_DIFFMODE_OVERRIDE_EN: u1,
+                padding: u16,
+            }),
+            ///  Used to adjust trim values of USB phy pull down resistors.
+            USBPHY_TRIM: mmio.Mmio(packed struct(u32) {
+                ///  Value to drive to USB PHY
+                ///  DP pulldown resistor trim control
+                ///  Experimental data suggests that the reset value will work, but this register allows adjustment if required
+                DP_PULLDN_TRIM: u5,
+                reserved8: u3,
+                ///  Value to drive to USB PHY
+                ///  DM pulldown resistor trim control
+                ///  Experimental data suggests that the reset value will work, but this register allows adjustment if required
+                DM_PULLDN_TRIM: u5,
+                padding: u19,
+            }),
+            reserved140: [4]u8,
+            ///  Raw Interrupts
+            INTR: mmio.Mmio(packed struct(u32) {
+                ///  Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
+                HOST_CONN_DIS: u1,
+                ///  Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
+                HOST_RESUME: u1,
+                ///  Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
+                HOST_SOF: u1,
+                ///  Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
+                TRANS_COMPLETE: u1,
+                ///  Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
+                BUFF_STATUS: u1,
+                ///  Source: SIE_STATUS.DATA_SEQ_ERROR
+                ERROR_DATA_SEQ: u1,
+                ///  Source: SIE_STATUS.RX_TIMEOUT
+                ERROR_RX_TIMEOUT: u1,
+                ///  Source: SIE_STATUS.RX_OVERFLOW
+                ERROR_RX_OVERFLOW: u1,
+                ///  Source: SIE_STATUS.BIT_STUFF_ERROR
+                ERROR_BIT_STUFF: u1,
+                ///  Source: SIE_STATUS.CRC_ERROR
+                ERROR_CRC: u1,
+                ///  Source: SIE_STATUS.STALL_REC
+                STALL: u1,
+                ///  Source: SIE_STATUS.VBUS_DETECTED
+                VBUS_DETECT: u1,
+                ///  Source: SIE_STATUS.BUS_RESET
+                BUS_RESET: u1,
+                ///  Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
+                DEV_CONN_DIS: u1,
+                ///  Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
+                DEV_SUSPEND: u1,
+                ///  Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
+                DEV_RESUME_FROM_HOST: u1,
+                ///  Device. Source: SIE_STATUS.SETUP_REC
+                SETUP_REQ: u1,
+                ///  Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
+                DEV_SOF: u1,
+                ///  Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
+                ABORT_DONE: u1,
+                ///  Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
+                EP_STALL_NAK: u1,
+                padding: u12,
+            }),
+            ///  Interrupt Enable
+            INTE: mmio.Mmio(packed struct(u32) {
+                ///  Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
+                HOST_CONN_DIS: u1,
+                ///  Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
+                HOST_RESUME: u1,
+                ///  Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
+                HOST_SOF: u1,
+                ///  Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
+                TRANS_COMPLETE: u1,
+                ///  Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
+                BUFF_STATUS: u1,
+                ///  Source: SIE_STATUS.DATA_SEQ_ERROR
+                ERROR_DATA_SEQ: u1,
+                ///  Source: SIE_STATUS.RX_TIMEOUT
+                ERROR_RX_TIMEOUT: u1,
+                ///  Source: SIE_STATUS.RX_OVERFLOW
+                ERROR_RX_OVERFLOW: u1,
+                ///  Source: SIE_STATUS.BIT_STUFF_ERROR
+                ERROR_BIT_STUFF: u1,
+                ///  Source: SIE_STATUS.CRC_ERROR
+                ERROR_CRC: u1,
+                ///  Source: SIE_STATUS.STALL_REC
+                STALL: u1,
+                ///  Source: SIE_STATUS.VBUS_DETECTED
+                VBUS_DETECT: u1,
+                ///  Source: SIE_STATUS.BUS_RESET
+                BUS_RESET: u1,
+                ///  Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
+                DEV_CONN_DIS: u1,
+                ///  Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
+                DEV_SUSPEND: u1,
+                ///  Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
+                DEV_RESUME_FROM_HOST: u1,
+                ///  Device. Source: SIE_STATUS.SETUP_REC
+                SETUP_REQ: u1,
+                ///  Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
+                DEV_SOF: u1,
+                ///  Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
+                ABORT_DONE: u1,
+                ///  Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
+                EP_STALL_NAK: u1,
+                padding: u12,
+            }),
+            ///  Interrupt Force
+            INTF: mmio.Mmio(packed struct(u32) {
+                ///  Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
+                HOST_CONN_DIS: u1,
+                ///  Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
+                HOST_RESUME: u1,
+                ///  Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
+                HOST_SOF: u1,
+                ///  Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
+                TRANS_COMPLETE: u1,
+                ///  Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
+                BUFF_STATUS: u1,
+                ///  Source: SIE_STATUS.DATA_SEQ_ERROR
+                ERROR_DATA_SEQ: u1,
+                ///  Source: SIE_STATUS.RX_TIMEOUT
+                ERROR_RX_TIMEOUT: u1,
+                ///  Source: SIE_STATUS.RX_OVERFLOW
+                ERROR_RX_OVERFLOW: u1,
+                ///  Source: SIE_STATUS.BIT_STUFF_ERROR
+                ERROR_BIT_STUFF: u1,
+                ///  Source: SIE_STATUS.CRC_ERROR
+                ERROR_CRC: u1,
+                ///  Source: SIE_STATUS.STALL_REC
+                STALL: u1,
+                ///  Source: SIE_STATUS.VBUS_DETECTED
+                VBUS_DETECT: u1,
+                ///  Source: SIE_STATUS.BUS_RESET
+                BUS_RESET: u1,
+                ///  Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
+                DEV_CONN_DIS: u1,
+                ///  Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
+                DEV_SUSPEND: u1,
+                ///  Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
+                DEV_RESUME_FROM_HOST: u1,
+                ///  Device. Source: SIE_STATUS.SETUP_REC
+                SETUP_REQ: u1,
+                ///  Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
+                DEV_SOF: u1,
+                ///  Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
+                ABORT_DONE: u1,
+                ///  Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
+                EP_STALL_NAK: u1,
+                padding: u12,
+            }),
+            ///  Interrupt status after masking & forcing
+            INTS: mmio.Mmio(packed struct(u32) {
+                ///  Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
+                HOST_CONN_DIS: u1,
+                ///  Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
+                HOST_RESUME: u1,
+                ///  Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
+                HOST_SOF: u1,
+                ///  Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
+                TRANS_COMPLETE: u1,
+                ///  Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
+                BUFF_STATUS: u1,
+                ///  Source: SIE_STATUS.DATA_SEQ_ERROR
+                ERROR_DATA_SEQ: u1,
+                ///  Source: SIE_STATUS.RX_TIMEOUT
+                ERROR_RX_TIMEOUT: u1,
+                ///  Source: SIE_STATUS.RX_OVERFLOW
+                ERROR_RX_OVERFLOW: u1,
+                ///  Source: SIE_STATUS.BIT_STUFF_ERROR
+                ERROR_BIT_STUFF: u1,
+                ///  Source: SIE_STATUS.CRC_ERROR
+                ERROR_CRC: u1,
+                ///  Source: SIE_STATUS.STALL_REC
+                STALL: u1,
+                ///  Source: SIE_STATUS.VBUS_DETECTED
+                VBUS_DETECT: u1,
+                ///  Source: SIE_STATUS.BUS_RESET
+                BUS_RESET: u1,
+                ///  Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
+                DEV_CONN_DIS: u1,
+                ///  Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
+                DEV_SUSPEND: u1,
+                ///  Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
+                DEV_RESUME_FROM_HOST: u1,
+                ///  Device. Source: SIE_STATUS.SETUP_REC
+                SETUP_REQ: u1,
+                ///  Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
+                DEV_SOF: u1,
+                ///  Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
+                ABORT_DONE: u1,
+                ///  Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
+                EP_STALL_NAK: u1,
+                padding: u12,
+            }),
+        };
+
+        ///  DW_apb_i2c address block
+        ///  List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
+        ///  IC_ULTRA_FAST_MODE ................ 0x0
+        ///  IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
+        ///  IC_UFM_SCL_LOW_COUNT .............. 0x0008
+        ///  IC_UFM_SCL_HIGH_COUNT ............. 0x0006
+        ///  IC_TX_TL .......................... 0x0
+        ///  IC_TX_CMD_BLOCK ................... 0x1
+        ///  IC_HAS_DMA ........................ 0x1
+        ///  IC_HAS_ASYNC_FIFO ................. 0x0
+        ///  IC_SMBUS_ARP ...................... 0x0
+        ///  IC_FIRST_DATA_BYTE_STATUS ......... 0x1
+        ///  IC_INTR_IO ........................ 0x1
+        ///  IC_MASTER_MODE .................... 0x1
+        ///  IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
+        ///  IC_INTR_POL ....................... 0x1
+        ///  IC_OPTIONAL_SAR ................... 0x0
+        ///  IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
+        ///  IC_DEFAULT_SLAVE_ADDR ............. 0x055
+        ///  IC_DEFAULT_HS_SPKLEN .............. 0x1
+        ///  IC_FS_SCL_HIGH_COUNT .............. 0x0006
+        ///  IC_HS_SCL_LOW_COUNT ............... 0x0008
+        ///  IC_DEVICE_ID_VALUE ................ 0x0
+        ///  IC_10BITADDR_MASTER ............... 0x0
+        ///  IC_CLK_FREQ_OPTIMIZATION .......... 0x0
+        ///  IC_DEFAULT_FS_SPKLEN .............. 0x7
+        ///  IC_ADD_ENCODED_PARAMS ............. 0x0
+        ///  IC_DEFAULT_SDA_HOLD ............... 0x000001
+        ///  IC_DEFAULT_SDA_SETUP .............. 0x64
+        ///  IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
+        ///  IC_CLOCK_PERIOD ................... 100
+        ///  IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
+        ///  IC_RESTART_EN ..................... 0x1
+        ///  IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
+        ///  IC_BUS_CLEAR_FEATURE .............. 0x0
+        ///  IC_CAP_LOADING .................... 100
+        ///  IC_FS_SCL_LOW_COUNT ............... 0x000d
+        ///  APB_DATA_WIDTH .................... 32
+        ///  IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+        ///  IC_SLV_DATA_NACK_ONLY ............. 0x1
+        ///  IC_10BITADDR_SLAVE ................ 0x0
+        ///  IC_CLK_TYPE ....................... 0x0
+        ///  IC_SMBUS_UDID_MSB ................. 0x0
+        ///  IC_SMBUS_SUSPEND_ALERT ............ 0x0
+        ///  IC_HS_SCL_HIGH_COUNT .............. 0x0006
+        ///  IC_SLV_RESTART_DET_EN ............. 0x1
+        ///  IC_SMBUS .......................... 0x0
+        ///  IC_OPTIONAL_SAR_DEFAULT ........... 0x0
+        ///  IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
+        ///  IC_USE_COUNTS ..................... 0x0
+        ///  IC_RX_BUFFER_DEPTH ................ 16
+        ///  IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
+        ///  IC_RX_FULL_HLD_BUS_EN ............. 0x1
+        ///  IC_SLAVE_DISABLE .................. 0x1
+        ///  IC_RX_TL .......................... 0x0
+        ///  IC_DEVICE_ID ...................... 0x0
+        ///  IC_HC_COUNT_VALUES ................ 0x0
+        ///  I2C_DYNAMIC_TAR_UPDATE ............ 0
+        ///  IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
+        ///  IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
+        ///  IC_HS_MASTER_CODE ................. 0x1
+        ///  IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
+        ///  IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
+        ///  IC_SS_SCL_HIGH_COUNT .............. 0x0028
+        ///  IC_SS_SCL_LOW_COUNT ............... 0x002f
+        ///  IC_MAX_SPEED_MODE ................. 0x2
+        ///  IC_STAT_FOR_CLK_STRETCH ........... 0x0
+        ///  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
+        ///  IC_DEFAULT_UFM_SPKLEN ............. 0x1
+        ///  IC_TX_BUFFER_DEPTH ................ 16
+        pub const I2C0 = extern struct {
+            ///  I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+            ///  Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.
+            IC_CON: mmio.Mmio(packed struct(u32) {
+                ///  This bit controls whether the DW_apb_i2c master is enabled.
+                ///  NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.
+                MASTER_MODE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Master mode is disabled
+                        DISABLED = 0x0,
+                        ///  Master mode is enabled
+                        ENABLED = 0x1,
+                    },
+                },
+                ///  These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.
+                ///  This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.
+                ///  1: standard mode (100 kbit/s)
+                ///  2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)
+                ///  3: high speed mode (3.4 Mbit/s)
+                ///  Note: This field is not applicable when IC_ULTRA_FAST_MODE=1
+                SPEED: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Standard Speed mode of operation
+                        STANDARD = 0x1,
+                        ///  Fast or Fast Plus mode of operation
+                        FAST = 0x2,
+                        ///  High Speed mode of operation
+                        HIGH = 0x3,
+                        _,
+                    },
+                },
+                ///  When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.
+                IC_10BITADDR_SLAVE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Slave 7Bit addressing
+                        ADDR_7BITS = 0x0,
+                        ///  Slave 10Bit addressing
+                        ADDR_10BITS = 0x1,
+                    },
+                },
+                ///  Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing
+                IC_10BITADDR_MASTER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Master 7Bit addressing mode
+                        ADDR_7BITS = 0x0,
+                        ///  Master 10Bit addressing mode
+                        ADDR_10BITS = 0x1,
+                    },
+                },
+                ///  Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.
+                ///  Reset value: ENABLED
+                IC_RESTART_EN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Master restart disabled
+                        DISABLED = 0x0,
+                        ///  Master restart enabled
+                        ENABLED = 0x1,
+                    },
+                },
+                ///  This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.
+                ///  If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.
+                ///  NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.
+                IC_SLAVE_DISABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Slave mode is enabled
+                        SLAVE_ENABLED = 0x0,
+                        ///  Slave mode is disabled
+                        SLAVE_DISABLED = 0x1,
+                    },
+                },
+                ///  In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0
+                ///  NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).
+                STOP_DET_IFADDRESSED: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  slave issues STOP_DET intr always
+                        DISABLED = 0x0,
+                        ///  slave issues STOP_DET intr only if addressed
+                        ENABLED = 0x1,
+                    },
+                },
+                ///  This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.
+                ///  Reset value: 0x0.
+                TX_EMPTY_CTRL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Default behaviour of TX_EMPTY interrupt
+                        DISABLED = 0x0,
+                        ///  Controlled generation of TX_EMPTY interrupt
+                        ENABLED = 0x1,
+                    },
+                },
+                ///  This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.
+                ///  Reset value: 0x0.
+                RX_FIFO_FULL_HLD_CTRL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Overflow when RX_FIFO is full
+                        DISABLED = 0x0,
+                        ///  Hold bus when RX_FIFO is full
+                        ENABLED = 0x1,
+                    },
+                },
+                ///  Master issues the STOP_DET interrupt irrespective of whether master is active or not
+                STOP_DET_IF_MASTER_ACTIVE: u1,
+                padding: u21,
+            }),
+            ///  I2C Target Address Register
+            ///  This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.
+            ///  Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.
+            IC_TAR: mmio.Mmio(packed struct(u32) {
+                ///  This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.
+                ///  If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.
+                IC_TAR: u10,
+                ///  If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0
+                GC_OR_START: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  GENERAL_CALL byte transmission
+                        GENERAL_CALL = 0x0,
+                        ///  START byte transmission
+                        START_BYTE = 0x1,
+                    },
+                },
+                ///  This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0
+                SPECIAL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Disables programming of GENERAL_CALL or START_BYTE transmission
+                        DISABLED = 0x0,
+                        ///  Enables programming of GENERAL_CALL or START_BYTE transmission
+                        ENABLED = 0x1,
+                    },
+                },
+                padding: u20,
+            }),
+            ///  I2C Slave Address Register
+            IC_SAR: mmio.Mmio(packed struct(u32) {
+                ///  The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.
+                ///  This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+                ///  Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <> for a complete list of these reserved values.
+                IC_SAR: u10,
+                padding: u22,
+            }),
+            reserved16: [4]u8,
+            ///  I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
+            ///  The size of the register changes as follows:
+            ///  Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.
+            IC_DATA_CMD: mmio.Mmio(packed struct(u32) {
+                ///  This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.
+                ///  Reset value: 0x0
+                DAT: u8,
+                ///  This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
+                ///  When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.
+                ///  When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.
+                ///  Reset value: 0x0
+                CMD: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Master Write Command
+                        WRITE = 0x0,
+                        ///  Master Read Command
+                        READ = 0x1,
+                    },
+                },
+                ///  This bit controls whether a STOP is issued after the byte is sent or received.
+                ///  - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0
+                STOP: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Don't Issue STOP after this command
+                        DISABLE = 0x0,
+                        ///  Issue STOP after this command
+                        ENABLE = 0x1,
+                    },
+                },
+                ///  This bit controls whether a RESTART is issued before the byte is sent or received.
+                ///  1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
+                ///  0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
+                ///  Reset value: 0x0
+                RESTART: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Don't Issue RESTART before this command
+                        DISABLE = 0x0,
+                        ///  Issue RESTART before this command
+                        ENABLE = 0x1,
+                    },
+                },
+                ///  Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.
+                ///  Reset value : 0x0
+                ///  NOTE: In case of APB_DATA_WIDTH=8,
+                ///  1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.
+                ///  2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).
+                ///  3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status.
+                FIRST_DATA_BYTE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Sequential data byte received
+                        INACTIVE = 0x0,
+                        ///  Non sequential data byte received
+                        ACTIVE = 0x1,
+                    },
+                },
+                padding: u20,
+            }),
+            ///  Standard Speed I2C Clock SCL High Count Register
+            IC_SS_SCL_HCNT: mmio.Mmio(packed struct(u32) {
+                ///  This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.
+                ///  This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+                ///  The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.
+                ///  NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.
+                IC_SS_SCL_HCNT: u16,
+                padding: u16,
+            }),
+            ///  Standard Speed I2C Clock SCL Low Count Register
+            IC_SS_SCL_LCNT: mmio.Mmio(packed struct(u32) {
+                ///  This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'
+                ///  This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+                ///  The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed.
+                IC_SS_SCL_LCNT: u16,
+                padding: u16,
+            }),
+            ///  Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
+            IC_FS_SCL_HCNT: mmio.Mmio(packed struct(u32) {
+                ///  This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.
+                ///  This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+                ///  The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.
+                IC_FS_SCL_HCNT: u16,
+                padding: u16,
+            }),
+            ///  Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
+            IC_FS_SCL_LCNT: mmio.Mmio(packed struct(u32) {
+                ///  This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.
+                ///  This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.
+                ///  This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
+                ///  The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.
+                IC_FS_SCL_LCNT: u16,
+                padding: u16,
+            }),
+            reserved44: [8]u8,
+            ///  I2C Interrupt Status Register
+            ///  Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.
+            IC_INTR_STAT: mmio.Mmio(packed struct(u32) {
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.
+                ///  Reset value: 0x0
+                R_RX_UNDER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RX_UNDER interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  RX_UNDER interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.
+                ///  Reset value: 0x0
+                R_RX_OVER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_RX_OVER interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_RX_OVER interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.
+                ///  Reset value: 0x0
+                R_RX_FULL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_RX_FULL interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_RX_FULL interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.
+                ///  Reset value: 0x0
+                R_TX_OVER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_TX_OVER interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_TX_OVER interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.
+                ///  Reset value: 0x0
+                R_TX_EMPTY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_TX_EMPTY interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_TX_EMPTY interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.
+                ///  Reset value: 0x0
+                R_RD_REQ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_RD_REQ interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_RD_REQ interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.
+                ///  Reset value: 0x0
+                R_TX_ABRT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_TX_ABRT interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_TX_ABRT interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.
+                ///  Reset value: 0x0
+                R_RX_DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_RX_DONE interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_RX_DONE interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.
+                ///  Reset value: 0x0
+                R_ACTIVITY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_ACTIVITY interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_ACTIVITY interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.
+                ///  Reset value: 0x0
+                R_STOP_DET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_STOP_DET interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_STOP_DET interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.
+                ///  Reset value: 0x0
+                R_START_DET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_START_DET interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_START_DET interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.
+                ///  Reset value: 0x0
+                R_GEN_CALL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_GEN_CALL interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_GEN_CALL interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.
+                ///  Reset value: 0x0
+                R_RESTART_DET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  R_RESTART_DET interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  R_RESTART_DET interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                padding: u19,
+            }),
+            ///  I2C Interrupt Mask Register.
+            ///  These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.
+            IC_INTR_MASK: mmio.Mmio(packed struct(u32) {
+                ///  This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x1
+                M_RX_UNDER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RX_UNDER interrupt is masked
+                        ENABLED = 0x0,
+                        ///  RX_UNDER interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x1
+                M_RX_OVER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RX_OVER interrupt is masked
+                        ENABLED = 0x0,
+                        ///  RX_OVER interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x1
+                M_RX_FULL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RX_FULL interrupt is masked
+                        ENABLED = 0x0,
+                        ///  RX_FULL interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x1
+                M_TX_OVER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  TX_OVER interrupt is masked
+                        ENABLED = 0x0,
+                        ///  TX_OVER interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x1
+                M_TX_EMPTY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  TX_EMPTY interrupt is masked
+                        ENABLED = 0x0,
+                        ///  TX_EMPTY interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x1
+                M_RD_REQ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RD_REQ interrupt is masked
+                        ENABLED = 0x0,
+                        ///  RD_REQ interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x1
+                M_TX_ABRT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  TX_ABORT interrupt is masked
+                        ENABLED = 0x0,
+                        ///  TX_ABORT interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x1
+                M_RX_DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RX_DONE interrupt is masked
+                        ENABLED = 0x0,
+                        ///  RX_DONE interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x0
+                M_ACTIVITY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  ACTIVITY interrupt is masked
+                        ENABLED = 0x0,
+                        ///  ACTIVITY interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x0
+                M_STOP_DET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  STOP_DET interrupt is masked
+                        ENABLED = 0x0,
+                        ///  STOP_DET interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_START_DET interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x0
+                M_START_DET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  START_DET interrupt is masked
+                        ENABLED = 0x0,
+                        ///  START_DET interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x1
+                M_GEN_CALL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  GEN_CALL interrupt is masked
+                        ENABLED = 0x0,
+                        ///  GEN_CALL interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                ///  This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.
+                ///  Reset value: 0x0
+                M_RESTART_DET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RESTART_DET interrupt is masked
+                        ENABLED = 0x0,
+                        ///  RESTART_DET interrupt is unmasked
+                        DISABLED = 0x1,
+                    },
+                },
+                padding: u19,
+            }),
+            ///  I2C Raw Interrupt Status Register
+            ///  Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.
+            IC_RAW_INTR_STAT: mmio.Mmio(packed struct(u32) {
+                ///  Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
+                ///  Reset value: 0x0
+                RX_UNDER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RX_UNDER interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  RX_UNDER interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
+                ///  Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.
+                ///  Reset value: 0x0
+                RX_OVER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RX_OVER interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  RX_OVER interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
+                ///  Reset value: 0x0
+                RX_FULL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RX_FULL interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  RX_FULL interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
+                ///  Reset value: 0x0
+                TX_OVER: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  TX_OVER interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  TX_OVER interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.
+                ///  Reset value: 0x0.
+                TX_EMPTY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  TX_EMPTY interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  TX_EMPTY interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.
+                ///  Reset value: 0x0
+                RD_REQ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RD_REQ interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  RD_REQ interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.
+                ///  Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.
+                ///  Reset value: 0x0
+                TX_ABRT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  TX_ABRT interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  TX_ABRT interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
+                ///  Reset value: 0x0
+                RX_DONE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RX_DONE interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  RX_DONE interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.
+                ///  Reset value: 0x0
+                ACTIVITY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RAW_INTR_ACTIVITY interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  RAW_INTR_ACTIVITY interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
+                ///  In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0
+                STOP_DET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  STOP_DET interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  STOP_DET interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
+                ///  Reset value: 0x0
+                START_DET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  START_DET interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  START_DET interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.
+                ///  Reset value: 0x0
+                GEN_CALL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  GEN_CALL interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  GEN_CALL interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.
+                ///  Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.
+                ///  Reset value: 0x0
+                RESTART_DET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  RESTART_DET interrupt is inactive
+                        INACTIVE = 0x0,
+                        ///  RESTART_DET interrupt is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                padding: u19,
+            }),
+            ///  I2C Receive FIFO Threshold Register
+            IC_RX_TL: mmio.Mmio(packed struct(u32) {
+                ///  Receive FIFO Threshold Level.
+                ///  Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
+                RX_TL: u8,
+                padding: u24,
+            }),
+            ///  I2C Transmit FIFO Threshold Register
+            IC_TX_TL: mmio.Mmio(packed struct(u32) {
+                ///  Transmit FIFO Threshold Level.
+                ///  Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.
+                TX_TL: u8,
+                padding: u24,
+            }),
+            ///  Clear Combined and Individual Interrupt Register
+            IC_CLR_INTR: mmio.Mmio(packed struct(u32) {
+                ///  Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
+                ///  Reset value: 0x0
+                CLR_INTR: u1,
+                padding: u31,
+            }),
+            ///  Clear RX_UNDER Interrupt Register
+            IC_CLR_RX_UNDER: mmio.Mmio(packed struct(u32) {
+                ///  Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.
+                ///  Reset value: 0x0
+                CLR_RX_UNDER: u1,
+                padding: u31,
+            }),
+            ///  Clear RX_OVER Interrupt Register
+            IC_CLR_RX_OVER: mmio.Mmio(packed struct(u32) {
+                ///  Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.
+                ///  Reset value: 0x0
+                CLR_RX_OVER: u1,
+                padding: u31,
+            }),
+            ///  Clear TX_OVER Interrupt Register
+            IC_CLR_TX_OVER: mmio.Mmio(packed struct(u32) {
+                ///  Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.
+                ///  Reset value: 0x0
+                CLR_TX_OVER: u1,
+                padding: u31,
+            }),
+            ///  Clear RD_REQ Interrupt Register
+            IC_CLR_RD_REQ: mmio.Mmio(packed struct(u32) {
+                ///  Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.
+                ///  Reset value: 0x0
+                CLR_RD_REQ: u1,
+                padding: u31,
+            }),
+            ///  Clear TX_ABRT Interrupt Register
+            IC_CLR_TX_ABRT: mmio.Mmio(packed struct(u32) {
+                ///  Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
+                ///  Reset value: 0x0
+                CLR_TX_ABRT: u1,
+                padding: u31,
+            }),
+            ///  Clear RX_DONE Interrupt Register
+            IC_CLR_RX_DONE: mmio.Mmio(packed struct(u32) {
+                ///  Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.
+                ///  Reset value: 0x0
+                CLR_RX_DONE: u1,
+                padding: u31,
+            }),
+            ///  Clear ACTIVITY Interrupt Register
+            IC_CLR_ACTIVITY: mmio.Mmio(packed struct(u32) {
+                ///  Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.
+                ///  Reset value: 0x0
+                CLR_ACTIVITY: u1,
+                padding: u31,
+            }),
+            ///  Clear STOP_DET Interrupt Register
+            IC_CLR_STOP_DET: mmio.Mmio(packed struct(u32) {
+                ///  Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.
+                ///  Reset value: 0x0
+                CLR_STOP_DET: u1,
+                padding: u31,
+            }),
+            ///  Clear START_DET Interrupt Register
+            IC_CLR_START_DET: mmio.Mmio(packed struct(u32) {
+                ///  Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.
+                ///  Reset value: 0x0
+                CLR_START_DET: u1,
+                padding: u31,
+            }),
+            ///  Clear GEN_CALL Interrupt Register
+            IC_CLR_GEN_CALL: mmio.Mmio(packed struct(u32) {
+                ///  Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.
+                ///  Reset value: 0x0
+                CLR_GEN_CALL: u1,
+                padding: u31,
+            }),
+            ///  I2C Enable Register
+            IC_ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.
+                ///  When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.
+                ///  In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'
+                ///  Reset value: 0x0
+                ENABLE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  I2C is disabled
+                        DISABLED = 0x0,
+                        ///  I2C is enabled
+                        ENABLED = 0x1,
+                    },
+                },
+                ///  When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.
+                ///  For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.
+                ///  Reset value: 0x0
+                ABORT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  ABORT operation not in progress
+                        DISABLE = 0x0,
+                        ///  ABORT operation in progress
+                        ENABLED = 0x1,
+                    },
+                },
+                ///  In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT
+                TX_CMD_BLOCK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Tx Command execution not blocked
+                        NOT_BLOCKED = 0x0,
+                        ///  Tx Command execution blocked
+                        BLOCKED = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  I2C Status Register
+            ///  This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.
+            ///  When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0
+            IC_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  I2C Activity Status. Reset value: 0x0
+                ACTIVITY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  I2C is idle
+                        INACTIVE = 0x0,
+                        ///  I2C is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1
+                TFNF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Tx FIFO is full
+                        FULL = 0x0,
+                        ///  Tx FIFO not full
+                        NOT_FULL = 0x1,
+                    },
+                },
+                ///  Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1
+                TFE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Tx FIFO not empty
+                        NON_EMPTY = 0x0,
+                        ///  Tx FIFO is empty
+                        EMPTY = 0x1,
+                    },
+                },
+                ///  Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0
+                RFNE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Rx FIFO is empty
+                        EMPTY = 0x0,
+                        ///  Rx FIFO not empty
+                        NOT_EMPTY = 0x1,
+                    },
+                },
+                ///  Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0
+                RFF: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Rx FIFO not full
+                        NOT_FULL = 0x0,
+                        ///  Rx FIFO is full
+                        FULL = 0x1,
+                    },
+                },
+                ///  Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.
+                ///  Reset value: 0x0
+                MST_ACTIVITY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Master is idle
+                        IDLE = 0x0,
+                        ///  Master not idle
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0
+                SLV_ACTIVITY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Slave is idle
+                        IDLE = 0x0,
+                        ///  Slave not idle
+                        ACTIVE = 0x1,
+                    },
+                },
+                padding: u25,
+            }),
+            ///  I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
+            IC_TXFLR: mmio.Mmio(packed struct(u32) {
+                ///  Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.
+                ///  Reset value: 0x0
+                TXFLR: u5,
+                padding: u27,
+            }),
+            ///  I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.
+            IC_RXFLR: mmio.Mmio(packed struct(u32) {
+                ///  Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.
+                ///  Reset value: 0x0
+                RXFLR: u5,
+                padding: u27,
+            }),
+            ///  I2C SDA Hold Time Length Register
+            ///  The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).
+            ///  The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.
+            ///  Writes to this register succeed only when IC_ENABLE[0]=0.
+            ///  The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.
+            ///  The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.
+            IC_SDA_HOLD: mmio.Mmio(packed struct(u32) {
+                ///  Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.
+                ///  Reset value: IC_DEFAULT_SDA_HOLD[15:0].
+                IC_SDA_TX_HOLD: u16,
+                ///  Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.
+                ///  Reset value: IC_DEFAULT_SDA_HOLD[23:16].
+                IC_SDA_RX_HOLD: u8,
+                padding: u8,
+            }),
+            ///  I2C Transmit Abort Source Register
+            ///  This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).
+            ///  Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.
+            IC_TX_ABRT_SOURCE: mmio.Mmio(packed struct(u32) {
+                ///  This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
+                ABRT_7B_ADDR_NOACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  This abort is not generated
+                        INACTIVE = 0x0,
+                        ///  This abort is generated because of NOACK for 7-bit address
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
+                ABRT_10ADDR1_NOACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  This abort is not generated
+                        INACTIVE = 0x0,
+                        ///  Byte 1 of 10Bit Address not ACKed by any slave
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
+                ABRT_10ADDR2_NOACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  This abort is not generated
+                        INACTIVE = 0x0,
+                        ///  Byte 2 of 10Bit Address not ACKed by any slave
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Transmitter
+                ABRT_TXDATA_NOACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Transmitted data non-ACKed by addressed slave-scenario not present
+                        ABRT_TXDATA_NOACK_VOID = 0x0,
+                        ///  Transmitted data not ACKed by addressed slave
+                        ABRT_TXDATA_NOACK_GENERATED = 0x1,
+                    },
+                },
+                ///  This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Transmitter
+                ABRT_GCALL_NOACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  GCALL not ACKed by any slave-scenario not present
+                        ABRT_GCALL_NOACK_VOID = 0x0,
+                        ///  GCALL not ACKed by any slave
+                        ABRT_GCALL_NOACK_GENERATED = 0x1,
+                    },
+                },
+                ///  This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Transmitter
+                ABRT_GCALL_READ: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  GCALL is followed by read from bus-scenario not present
+                        ABRT_GCALL_READ_VOID = 0x0,
+                        ///  GCALL is followed by read from bus
+                        ABRT_GCALL_READ_GENERATED = 0x1,
+                    },
+                },
+                ///  This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master
+                ABRT_HS_ACKDET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  HS Master code ACKed in HS Mode- scenario not present
+                        ABRT_HS_ACK_VOID = 0x0,
+                        ///  HS Master code ACKed in HS Mode
+                        ABRT_HS_ACK_GENERATED = 0x1,
+                    },
+                },
+                ///  This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master
+                ABRT_SBYTE_ACKDET: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  ACK detected for START byte- scenario not present
+                        ABRT_SBYTE_ACKDET_VOID = 0x0,
+                        ///  ACK detected for START byte
+                        ABRT_SBYTE_ACKDET_GENERATED = 0x1,
+                    },
+                },
+                ///  This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
+                ABRT_HS_NORSTRT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  User trying to switch Master to HS mode when RESTART disabled- scenario not present
+                        ABRT_HS_NORSTRT_VOID = 0x0,
+                        ///  User trying to switch Master to HS mode when RESTART disabled
+                        ABRT_HS_NORSTRT_GENERATED = 0x1,
+                    },
+                },
+                ///  To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master
+                ABRT_SBYTE_NORSTRT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  User trying to send START byte when RESTART disabled- scenario not present
+                        ABRT_SBYTE_NORSTRT_VOID = 0x0,
+                        ///  User trying to send START byte when RESTART disabled
+                        ABRT_SBYTE_NORSTRT_GENERATED = 0x1,
+                    },
+                },
+                ///  This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Receiver
+                ABRT_10B_RD_NORSTRT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Master not trying to read in 10Bit addressing mode when RESTART disabled
+                        ABRT_10B_RD_VOID = 0x0,
+                        ///  Master trying to read in 10Bit addressing mode when RESTART disabled
+                        ABRT_10B_RD_GENERATED = 0x1,
+                    },
+                },
+                ///  This field indicates that the User tries to initiate a Master operation with the Master mode disabled.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
+                ABRT_MASTER_DIS: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  User initiating master operation when MASTER disabled- scenario not present
+                        ABRT_MASTER_DIS_VOID = 0x0,
+                        ///  User initiating master operation when MASTER disabled
+                        ABRT_MASTER_DIS_GENERATED = 0x1,
+                    },
+                },
+                ///  This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
+                ARB_LOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Master or Slave-Transmitter lost arbitration- scenario not present
+                        ABRT_LOST_VOID = 0x0,
+                        ///  Master or Slave-Transmitter lost arbitration
+                        ABRT_LOST_GENERATED = 0x1,
+                    },
+                },
+                ///  This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Slave-Transmitter
+                ABRT_SLVFLUSH_TXFIFO: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Slave flushes existing data in TX-FIFO upon getting read command- scenario not present
+                        ABRT_SLVFLUSH_TXFIFO_VOID = 0x0,
+                        ///  Slave flushes existing data in TX-FIFO upon getting read command
+                        ABRT_SLVFLUSH_TXFIFO_GENERATED = 0x1,
+                    },
+                },
+                ///  This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Slave-Transmitter
+                ABRT_SLV_ARBLOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Slave lost arbitration to remote master- scenario not present
+                        ABRT_SLV_ARBLOST_VOID = 0x0,
+                        ///  Slave lost arbitration to remote master
+                        ABRT_SLV_ARBLOST_GENERATED = 0x1,
+                    },
+                },
+                ///  1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Slave-Transmitter
+                ABRT_SLVRD_INTX: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Slave trying to transmit to remote master in read mode- scenario not present
+                        ABRT_SLVRD_INTX_VOID = 0x0,
+                        ///  Slave trying to transmit to remote master in read mode
+                        ABRT_SLVRD_INTX_GENERATED = 0x1,
+                    },
+                },
+                ///  This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Transmitter
+                ABRT_USER_ABRT: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Transfer abort detected by master- scenario not present
+                        ABRT_USER_ABRT_VOID = 0x0,
+                        ///  Transfer abort detected by master
+                        ABRT_USER_ABRT_GENERATED = 0x1,
+                    },
+                },
+                reserved23: u6,
+                ///  This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.
+                ///  Reset value: 0x0
+                ///  Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
+                TX_FLUSH_CNT: u9,
+            }),
+            ///  Generate Slave Data NACK Register
+            ///  The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.
+            ///  A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.
+            IC_SLV_DATA_NACK_ONLY: mmio.Mmio(packed struct(u32) {
+                ///  Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.
+                ///  When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0
+                NACK: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Slave receiver generates NACK normally
+                        DISABLED = 0x0,
+                        ///  Slave receiver generates NACK upon data reception only
+                        ENABLED = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  DMA Control Register
+            ///  The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.
+            IC_DMA_CR: mmio.Mmio(packed struct(u32) {
+                ///  Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0
+                RDMAE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Receive FIFO DMA channel disabled
+                        DISABLED = 0x0,
+                        ///  Receive FIFO DMA channel enabled
+                        ENABLED = 0x1,
+                    },
+                },
+                ///  Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0
+                TDMAE: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  transmit FIFO DMA channel disabled
+                        DISABLED = 0x0,
+                        ///  Transmit FIFO DMA channel enabled
+                        ENABLED = 0x1,
+                    },
+                },
+                padding: u30,
+            }),
+            ///  DMA Transmit Data Level Register
+            IC_DMA_TDLR: mmio.Mmio(packed struct(u32) {
+                ///  Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.
+                ///  Reset value: 0x0
+                DMATDL: u4,
+                padding: u28,
+            }),
+            ///  I2C Receive Data Level Register
+            IC_DMA_RDLR: mmio.Mmio(packed struct(u32) {
+                ///  Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.
+                ///  Reset value: 0x0
+                DMARDL: u4,
+                padding: u28,
+            }),
+            ///  I2C SDA Setup Register
+            ///  This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.
+            ///  Writes to this register succeed only when IC_ENABLE[0] = 0.
+            ///  Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.
+            IC_SDA_SETUP: mmio.Mmio(packed struct(u32) {
+                ///  SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.
+                SDA_SETUP: u8,
+                padding: u24,
+            }),
+            ///  I2C ACK General Call Register
+            ///  The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.
+            ///  This register is applicable only when the DW_apb_i2c is in slave mode.
+            IC_ACK_GENERAL_CALL: mmio.Mmio(packed struct(u32) {
+                ///  ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).
+                ACK_GEN_CALL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Generate NACK for a General Call
+                        DISABLED = 0x0,
+                        ///  Generate ACK for a General Call
+                        ENABLED = 0x1,
+                    },
+                },
+                padding: u31,
+            }),
+            ///  I2C Enable Status Register
+            ///  The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.
+            ///  If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.
+            ///  If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.
+            ///  Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.
+            IC_ENABLE_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).
+                ///  Reset value: 0x0
+                IC_EN: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  I2C disabled
+                        DISABLED = 0x0,
+                        ///  I2C enabled
+                        ENABLED = 0x1,
+                    },
+                },
+                ///  Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:
+                ///  (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;
+                ///  OR,
+                ///  (b) address and data bytes of the Slave-Receiver operation from a remote master.
+                ///  When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.
+                ///  Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.
+                ///  When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.
+                ///  Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
+                ///  Reset value: 0x0
+                SLV_DISABLED_WHILE_BUSY: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Slave is disabled when it is idle
+                        INACTIVE = 0x0,
+                        ///  Slave is disabled when it is active
+                        ACTIVE = 0x1,
+                    },
+                },
+                ///  Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.
+                ///  Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.
+                ///  When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.
+                ///  Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
+                ///  Reset value: 0x0
+                SLV_RX_DATA_LOST: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  Slave RX Data is not lost
+                        INACTIVE = 0x0,
+                        ///  Slave RX Data is lost
+                        ACTIVE = 0x1,
+                    },
+                },
+                padding: u29,
+            }),
+            ///  I2C SS, FS or FM+ spike suppression limit
+            ///  This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.
+            IC_FS_SPKLEN: mmio.Mmio(packed struct(u32) {
+                ///  This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'.
+                IC_FS_SPKLEN: u8,
+                padding: u24,
+            }),
+            reserved168: [4]u8,
+            ///  Clear RESTART_DET Interrupt Register
+            IC_CLR_RESTART_DET: mmio.Mmio(packed struct(u32) {
+                ///  Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.
+                ///  Reset value: 0x0
+                CLR_RESTART_DET: u1,
+                padding: u31,
+            }),
+            reserved244: [72]u8,
+            ///  Component Parameter Register 1
+            ///  Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters
+            IC_COMP_PARAM_1: mmio.Mmio(packed struct(u32) {
+                ///  APB data bus width is 32 bits
+                APB_DATA_WIDTH: u2,
+                ///  MAX SPEED MODE = FAST MODE
+                MAX_SPEED_MODE: u2,
+                ///  Programmable count values for each mode.
+                HC_COUNT_VALUES: u1,
+                ///  COMBINED Interrupt outputs
+                INTR_IO: u1,
+                ///  DMA handshaking signals are enabled
+                HAS_DMA: u1,
+                ///  Encoded parameters not visible
+                ADD_ENCODED_PARAMS: u1,
+                ///  RX Buffer Depth = 16
+                RX_BUFFER_DEPTH: u8,
+                ///  TX Buffer Depth = 16
+                TX_BUFFER_DEPTH: u8,
+                padding: u8,
+            }),
+            ///  I2C Component Version Register
+            IC_COMP_VERSION: mmio.Mmio(packed struct(u32) {
+                IC_COMP_VERSION: u32,
+            }),
+            ///  I2C Component Type Register
+            IC_COMP_TYPE: mmio.Mmio(packed struct(u32) {
+                ///  Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number.
+                IC_COMP_TYPE: u32,
+            }),
+        };
+
+        ///  Programmable IO block
+        pub const PIO0 = extern struct {
+            ///  PIO control register
+            CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.
+                SM_ENABLE: u4,
+                ///  Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.
+                ///  Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.
+                SM_RESTART: u4,
+                ///  Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.
+                ///  Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.
+                ///  Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.
+                CLKDIV_RESTART: u4,
+                padding: u20,
+            }),
+            ///  FIFO status register
+            FSTAT: mmio.Mmio(packed struct(u32) {
+                ///  State machine RX FIFO is full
+                RXFULL: u4,
+                reserved8: u4,
+                ///  State machine RX FIFO is empty
+                RXEMPTY: u4,
+                reserved16: u4,
+                ///  State machine TX FIFO is full
+                TXFULL: u4,
+                reserved24: u4,
+                ///  State machine TX FIFO is empty
+                TXEMPTY: u4,
+                padding: u4,
+            }),
+            ///  FIFO debug register
+            FDEBUG: mmio.Mmio(packed struct(u32) {
+                ///  State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.
+                RXSTALL: u4,
+                reserved8: u4,
+                ///  RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.
+                RXUNDER: u4,
+                reserved16: u4,
+                ///  TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.
+                TXOVER: u4,
+                reserved24: u4,
+                ///  State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.
+                TXSTALL: u4,
+                padding: u4,
+            }),
+            ///  FIFO levels
+            FLEVEL: mmio.Mmio(packed struct(u32) {
+                TX0: u4,
+                RX0: u4,
+                TX1: u4,
+                RX1: u4,
+                TX2: u4,
+                RX2: u4,
+                TX3: u4,
+                RX3: u4,
+            }),
+            ///  Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
+            TXF0: u32,
+            ///  Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
+            TXF1: u32,
+            ///  Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
+            TXF2: u32,
+            ///  Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
+            TXF3: u32,
+            ///  Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
+            RXF0: u32,
+            ///  Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
+            RXF1: u32,
+            ///  Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
+            RXF2: u32,
+            ///  Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
+            RXF3: u32,
+            ///  State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.
+            ///  Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE.
+            IRQ: mmio.Mmio(packed struct(u32) {
+                IRQ: u8,
+                padding: u24,
+            }),
+            ///  Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.
+            IRQ_FORCE: mmio.Mmio(packed struct(u32) {
+                IRQ_FORCE: u8,
+                padding: u24,
+            }),
+            ///  There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.
+            ///  0 -> input is synchronized (default)
+            ///  1 -> synchronizer is bypassed
+            ///  If in doubt, leave this register as all zeroes.
+            INPUT_SYNC_BYPASS: u32,
+            ///  Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.
+            DBG_PADOUT: u32,
+            ///  Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.
+            DBG_PADOE: u32,
+            ///  The PIO hardware has some free parameters that may vary between chip products.
+            ///  These should be provided in the chip datasheet, but are also exposed here.
+            DBG_CFGINFO: mmio.Mmio(packed struct(u32) {
+                ///  The depth of the state machine TX/RX FIFOs, measured in words.
+                ///  Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double
+                ///  this depth.
+                FIFO_DEPTH: u6,
+                reserved8: u2,
+                ///  The number of state machines this PIO instance is equipped with.
+                SM_COUNT: u4,
+                reserved16: u4,
+                ///  The size of the instruction memory, measured in units of one instruction
+                IMEM_SIZE: u6,
+                padding: u10,
+            }),
+            ///  Write-only access to instruction memory location 0
+            INSTR_MEM0: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM0: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 1
+            INSTR_MEM1: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM1: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 2
+            INSTR_MEM2: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM2: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 3
+            INSTR_MEM3: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM3: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 4
+            INSTR_MEM4: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM4: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 5
+            INSTR_MEM5: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM5: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 6
+            INSTR_MEM6: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM6: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 7
+            INSTR_MEM7: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM7: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 8
+            INSTR_MEM8: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM8: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 9
+            INSTR_MEM9: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM9: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 10
+            INSTR_MEM10: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM10: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 11
+            INSTR_MEM11: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM11: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 12
+            INSTR_MEM12: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM12: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 13
+            INSTR_MEM13: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM13: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 14
+            INSTR_MEM14: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM14: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 15
+            INSTR_MEM15: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM15: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 16
+            INSTR_MEM16: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM16: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 17
+            INSTR_MEM17: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM17: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 18
+            INSTR_MEM18: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM18: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 19
+            INSTR_MEM19: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM19: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 20
+            INSTR_MEM20: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM20: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 21
+            INSTR_MEM21: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM21: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 22
+            INSTR_MEM22: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM22: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 23
+            INSTR_MEM23: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM23: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 24
+            INSTR_MEM24: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM24: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 25
+            INSTR_MEM25: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM25: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 26
+            INSTR_MEM26: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM26: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 27
+            INSTR_MEM27: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM27: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 28
+            INSTR_MEM28: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM28: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 29
+            INSTR_MEM29: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM29: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 30
+            INSTR_MEM30: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM30: u16,
+                padding: u16,
+            }),
+            ///  Write-only access to instruction memory location 31
+            INSTR_MEM31: mmio.Mmio(packed struct(u32) {
+                INSTR_MEM31: u16,
+                padding: u16,
+            }),
+            ///  Clock divisor register for state machine 0
+            ///  Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+            SM0_CLKDIV: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Fractional part of clock divisor
+                FRAC: u8,
+                ///  Effective frequency is sysclk/(int + frac/256).
+                ///  Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
+                INT: u16,
+            }),
+            ///  Execution/behavioural settings for state machine 0
+            SM0_EXECCTRL: mmio.Mmio(packed struct(u32) {
+                ///  Comparison level for the MOV x, STATUS instruction
+                STATUS_N: u4,
+                ///  Comparison used for the MOV x, STATUS instruction.
+                STATUS_SEL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  All-ones if TX FIFO level < N, otherwise all-zeroes
+                        TXLEVEL = 0x0,
+                        ///  All-ones if RX FIFO level < N, otherwise all-zeroes
+                        RXLEVEL = 0x1,
+                    },
+                },
+                reserved7: u2,
+                ///  After reaching wrap_top, execution is wrapped to this address.
+                WRAP_BOTTOM: u5,
+                ///  After reaching this address, execution is wrapped to wrap_bottom.
+                ///  If the instruction is a jump, and the jump condition is true, the jump takes priority.
+                WRAP_TOP: u5,
+                ///  Continuously assert the most recent OUT/SET to the pins
+                OUT_STICKY: u1,
+                ///  If 1, use a bit of OUT data as an auxiliary write enable
+                ///  When used in conjunction with OUT_STICKY, writes with an enable of 0 will
+                ///  deassert the latest pin write. This can create useful masking/override behaviour
+                ///  due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
+                INLINE_OUT_EN: u1,
+                ///  Which data bit to use for inline OUT enable
+                OUT_EN_SEL: u5,
+                ///  The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
+                JMP_PIN: u5,
+                ///  If 1, side-set data is asserted to pin directions, instead of pin values
+                SIDE_PINDIR: u1,
+                ///  If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+                SIDE_EN: u1,
+                ///  If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
+                EXEC_STALLED: u1,
+            }),
+            ///  Control behaviour of the input/output shift registers for state machine 0
+            SM0_SHIFTCTRL: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
+                AUTOPUSH: u1,
+                ///  Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
+                AUTOPULL: u1,
+                ///  1 = shift input shift register to right (data enters from left). 0 = to left.
+                IN_SHIFTDIR: u1,
+                ///  1 = shift out of output shift register to right. 0 = to left.
+                OUT_SHIFTDIR: u1,
+                ///  Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.
+                ///  Write 0 for value of 32.
+                PUSH_THRESH: u5,
+                ///  Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.
+                ///  Write 0 for value of 32.
+                PULL_THRESH: u5,
+                ///  When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.
+                ///  RX FIFO is disabled as a result (always reads as both full and empty).
+                ///  FIFOs are flushed when this bit is changed.
+                FJOIN_TX: u1,
+                ///  When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.
+                ///  TX FIFO is disabled as a result (always reads as both full and empty).
+                ///  FIFOs are flushed when this bit is changed.
+                FJOIN_RX: u1,
+            }),
+            ///  Current instruction address of state machine 0
+            SM0_ADDR: mmio.Mmio(packed struct(u32) {
+                SM0_ADDR: u5,
+                padding: u27,
+            }),
+            ///  Read to see the instruction currently addressed by state machine 0's program counter
+            ///  Write to execute an instruction immediately (including jumps) and then resume execution.
+            SM0_INSTR: mmio.Mmio(packed struct(u32) {
+                SM0_INSTR: u16,
+                padding: u16,
+            }),
+            ///  State machine pin control
+            SM0_PINCTRL: mmio.Mmio(packed struct(u32) {
+                ///  The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
+                OUT_BASE: u5,
+                ///  The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
+                SET_BASE: u5,
+                ///  The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
+                SIDESET_BASE: u5,
+                ///  The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
+                IN_BASE: u5,
+                ///  The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
+                OUT_COUNT: u6,
+                ///  The number of pins asserted by a SET. In the range 0 to 5 inclusive.
+                SET_COUNT: u3,
+                ///  The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
+                SIDESET_COUNT: u3,
+            }),
+            ///  Clock divisor register for state machine 1
+            ///  Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+            SM1_CLKDIV: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Fractional part of clock divisor
+                FRAC: u8,
+                ///  Effective frequency is sysclk/(int + frac/256).
+                ///  Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
+                INT: u16,
+            }),
+            ///  Execution/behavioural settings for state machine 1
+            SM1_EXECCTRL: mmio.Mmio(packed struct(u32) {
+                ///  Comparison level for the MOV x, STATUS instruction
+                STATUS_N: u4,
+                ///  Comparison used for the MOV x, STATUS instruction.
+                STATUS_SEL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  All-ones if TX FIFO level < N, otherwise all-zeroes
+                        TXLEVEL = 0x0,
+                        ///  All-ones if RX FIFO level < N, otherwise all-zeroes
+                        RXLEVEL = 0x1,
+                    },
+                },
+                reserved7: u2,
+                ///  After reaching wrap_top, execution is wrapped to this address.
+                WRAP_BOTTOM: u5,
+                ///  After reaching this address, execution is wrapped to wrap_bottom.
+                ///  If the instruction is a jump, and the jump condition is true, the jump takes priority.
+                WRAP_TOP: u5,
+                ///  Continuously assert the most recent OUT/SET to the pins
+                OUT_STICKY: u1,
+                ///  If 1, use a bit of OUT data as an auxiliary write enable
+                ///  When used in conjunction with OUT_STICKY, writes with an enable of 0 will
+                ///  deassert the latest pin write. This can create useful masking/override behaviour
+                ///  due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
+                INLINE_OUT_EN: u1,
+                ///  Which data bit to use for inline OUT enable
+                OUT_EN_SEL: u5,
+                ///  The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
+                JMP_PIN: u5,
+                ///  If 1, side-set data is asserted to pin directions, instead of pin values
+                SIDE_PINDIR: u1,
+                ///  If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+                SIDE_EN: u1,
+                ///  If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
+                EXEC_STALLED: u1,
+            }),
+            ///  Control behaviour of the input/output shift registers for state machine 1
+            SM1_SHIFTCTRL: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
+                AUTOPUSH: u1,
+                ///  Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
+                AUTOPULL: u1,
+                ///  1 = shift input shift register to right (data enters from left). 0 = to left.
+                IN_SHIFTDIR: u1,
+                ///  1 = shift out of output shift register to right. 0 = to left.
+                OUT_SHIFTDIR: u1,
+                ///  Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.
+                ///  Write 0 for value of 32.
+                PUSH_THRESH: u5,
+                ///  Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.
+                ///  Write 0 for value of 32.
+                PULL_THRESH: u5,
+                ///  When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.
+                ///  RX FIFO is disabled as a result (always reads as both full and empty).
+                ///  FIFOs are flushed when this bit is changed.
+                FJOIN_TX: u1,
+                ///  When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.
+                ///  TX FIFO is disabled as a result (always reads as both full and empty).
+                ///  FIFOs are flushed when this bit is changed.
+                FJOIN_RX: u1,
+            }),
+            ///  Current instruction address of state machine 1
+            SM1_ADDR: mmio.Mmio(packed struct(u32) {
+                SM1_ADDR: u5,
+                padding: u27,
+            }),
+            ///  Read to see the instruction currently addressed by state machine 1's program counter
+            ///  Write to execute an instruction immediately (including jumps) and then resume execution.
+            SM1_INSTR: mmio.Mmio(packed struct(u32) {
+                SM1_INSTR: u16,
+                padding: u16,
+            }),
+            ///  State machine pin control
+            SM1_PINCTRL: mmio.Mmio(packed struct(u32) {
+                ///  The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
+                OUT_BASE: u5,
+                ///  The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
+                SET_BASE: u5,
+                ///  The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
+                SIDESET_BASE: u5,
+                ///  The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
+                IN_BASE: u5,
+                ///  The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
+                OUT_COUNT: u6,
+                ///  The number of pins asserted by a SET. In the range 0 to 5 inclusive.
+                SET_COUNT: u3,
+                ///  The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
+                SIDESET_COUNT: u3,
+            }),
+            ///  Clock divisor register for state machine 2
+            ///  Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+            SM2_CLKDIV: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Fractional part of clock divisor
+                FRAC: u8,
+                ///  Effective frequency is sysclk/(int + frac/256).
+                ///  Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
+                INT: u16,
+            }),
+            ///  Execution/behavioural settings for state machine 2
+            SM2_EXECCTRL: mmio.Mmio(packed struct(u32) {
+                ///  Comparison level for the MOV x, STATUS instruction
+                STATUS_N: u4,
+                ///  Comparison used for the MOV x, STATUS instruction.
+                STATUS_SEL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  All-ones if TX FIFO level < N, otherwise all-zeroes
+                        TXLEVEL = 0x0,
+                        ///  All-ones if RX FIFO level < N, otherwise all-zeroes
+                        RXLEVEL = 0x1,
+                    },
+                },
+                reserved7: u2,
+                ///  After reaching wrap_top, execution is wrapped to this address.
+                WRAP_BOTTOM: u5,
+                ///  After reaching this address, execution is wrapped to wrap_bottom.
+                ///  If the instruction is a jump, and the jump condition is true, the jump takes priority.
+                WRAP_TOP: u5,
+                ///  Continuously assert the most recent OUT/SET to the pins
+                OUT_STICKY: u1,
+                ///  If 1, use a bit of OUT data as an auxiliary write enable
+                ///  When used in conjunction with OUT_STICKY, writes with an enable of 0 will
+                ///  deassert the latest pin write. This can create useful masking/override behaviour
+                ///  due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
+                INLINE_OUT_EN: u1,
+                ///  Which data bit to use for inline OUT enable
+                OUT_EN_SEL: u5,
+                ///  The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
+                JMP_PIN: u5,
+                ///  If 1, side-set data is asserted to pin directions, instead of pin values
+                SIDE_PINDIR: u1,
+                ///  If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+                SIDE_EN: u1,
+                ///  If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
+                EXEC_STALLED: u1,
+            }),
+            ///  Control behaviour of the input/output shift registers for state machine 2
+            SM2_SHIFTCTRL: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
+                AUTOPUSH: u1,
+                ///  Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
+                AUTOPULL: u1,
+                ///  1 = shift input shift register to right (data enters from left). 0 = to left.
+                IN_SHIFTDIR: u1,
+                ///  1 = shift out of output shift register to right. 0 = to left.
+                OUT_SHIFTDIR: u1,
+                ///  Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.
+                ///  Write 0 for value of 32.
+                PUSH_THRESH: u5,
+                ///  Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.
+                ///  Write 0 for value of 32.
+                PULL_THRESH: u5,
+                ///  When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.
+                ///  RX FIFO is disabled as a result (always reads as both full and empty).
+                ///  FIFOs are flushed when this bit is changed.
+                FJOIN_TX: u1,
+                ///  When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.
+                ///  TX FIFO is disabled as a result (always reads as both full and empty).
+                ///  FIFOs are flushed when this bit is changed.
+                FJOIN_RX: u1,
+            }),
+            ///  Current instruction address of state machine 2
+            SM2_ADDR: mmio.Mmio(packed struct(u32) {
+                SM2_ADDR: u5,
+                padding: u27,
+            }),
+            ///  Read to see the instruction currently addressed by state machine 2's program counter
+            ///  Write to execute an instruction immediately (including jumps) and then resume execution.
+            SM2_INSTR: mmio.Mmio(packed struct(u32) {
+                SM2_INSTR: u16,
+                padding: u16,
+            }),
+            ///  State machine pin control
+            SM2_PINCTRL: mmio.Mmio(packed struct(u32) {
+                ///  The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
+                OUT_BASE: u5,
+                ///  The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
+                SET_BASE: u5,
+                ///  The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
+                SIDESET_BASE: u5,
+                ///  The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
+                IN_BASE: u5,
+                ///  The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
+                OUT_COUNT: u6,
+                ///  The number of pins asserted by a SET. In the range 0 to 5 inclusive.
+                SET_COUNT: u3,
+                ///  The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
+                SIDESET_COUNT: u3,
+            }),
+            ///  Clock divisor register for state machine 3
+            ///  Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
+            SM3_CLKDIV: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Fractional part of clock divisor
+                FRAC: u8,
+                ///  Effective frequency is sysclk/(int + frac/256).
+                ///  Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
+                INT: u16,
+            }),
+            ///  Execution/behavioural settings for state machine 3
+            SM3_EXECCTRL: mmio.Mmio(packed struct(u32) {
+                ///  Comparison level for the MOV x, STATUS instruction
+                STATUS_N: u4,
+                ///  Comparison used for the MOV x, STATUS instruction.
+                STATUS_SEL: packed union {
+                    raw: u1,
+                    value: enum(u1) {
+                        ///  All-ones if TX FIFO level < N, otherwise all-zeroes
+                        TXLEVEL = 0x0,
+                        ///  All-ones if RX FIFO level < N, otherwise all-zeroes
+                        RXLEVEL = 0x1,
+                    },
+                },
+                reserved7: u2,
+                ///  After reaching wrap_top, execution is wrapped to this address.
+                WRAP_BOTTOM: u5,
+                ///  After reaching this address, execution is wrapped to wrap_bottom.
+                ///  If the instruction is a jump, and the jump condition is true, the jump takes priority.
+                WRAP_TOP: u5,
+                ///  Continuously assert the most recent OUT/SET to the pins
+                OUT_STICKY: u1,
+                ///  If 1, use a bit of OUT data as an auxiliary write enable
+                ///  When used in conjunction with OUT_STICKY, writes with an enable of 0 will
+                ///  deassert the latest pin write. This can create useful masking/override behaviour
+                ///  due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
+                INLINE_OUT_EN: u1,
+                ///  Which data bit to use for inline OUT enable
+                OUT_EN_SEL: u5,
+                ///  The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
+                JMP_PIN: u5,
+                ///  If 1, side-set data is asserted to pin directions, instead of pin values
+                SIDE_PINDIR: u1,
+                ///  If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
+                SIDE_EN: u1,
+                ///  If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
+                EXEC_STALLED: u1,
+            }),
+            ///  Control behaviour of the input/output shift registers for state machine 3
+            SM3_SHIFTCTRL: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
+                AUTOPUSH: u1,
+                ///  Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
+                AUTOPULL: u1,
+                ///  1 = shift input shift register to right (data enters from left). 0 = to left.
+                IN_SHIFTDIR: u1,
+                ///  1 = shift out of output shift register to right. 0 = to left.
+                OUT_SHIFTDIR: u1,
+                ///  Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.
+                ///  Write 0 for value of 32.
+                PUSH_THRESH: u5,
+                ///  Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.
+                ///  Write 0 for value of 32.
+                PULL_THRESH: u5,
+                ///  When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.
+                ///  RX FIFO is disabled as a result (always reads as both full and empty).
+                ///  FIFOs are flushed when this bit is changed.
+                FJOIN_TX: u1,
+                ///  When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.
+                ///  TX FIFO is disabled as a result (always reads as both full and empty).
+                ///  FIFOs are flushed when this bit is changed.
+                FJOIN_RX: u1,
+            }),
+            ///  Current instruction address of state machine 3
+            SM3_ADDR: mmio.Mmio(packed struct(u32) {
+                SM3_ADDR: u5,
+                padding: u27,
+            }),
+            ///  Read to see the instruction currently addressed by state machine 3's program counter
+            ///  Write to execute an instruction immediately (including jumps) and then resume execution.
+            SM3_INSTR: mmio.Mmio(packed struct(u32) {
+                SM3_INSTR: u16,
+                padding: u16,
+            }),
+            ///  State machine pin control
+            SM3_PINCTRL: mmio.Mmio(packed struct(u32) {
+                ///  The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
+                OUT_BASE: u5,
+                ///  The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
+                SET_BASE: u5,
+                ///  The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
+                SIDESET_BASE: u5,
+                ///  The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
+                IN_BASE: u5,
+                ///  The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
+                OUT_COUNT: u6,
+                ///  The number of pins asserted by a SET. In the range 0 to 5 inclusive.
+                SET_COUNT: u3,
+                ///  The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
+                SIDESET_COUNT: u3,
+            }),
+            ///  Raw Interrupts
+            INTR: mmio.Mmio(packed struct(u32) {
+                SM0_RXNEMPTY: u1,
+                SM1_RXNEMPTY: u1,
+                SM2_RXNEMPTY: u1,
+                SM3_RXNEMPTY: u1,
+                SM0_TXNFULL: u1,
+                SM1_TXNFULL: u1,
+                SM2_TXNFULL: u1,
+                SM3_TXNFULL: u1,
+                SM0: u1,
+                SM1: u1,
+                SM2: u1,
+                SM3: u1,
+                padding: u20,
+            }),
+            ///  Interrupt Enable for irq0
+            IRQ0_INTE: mmio.Mmio(packed struct(u32) {
+                SM0_RXNEMPTY: u1,
+                SM1_RXNEMPTY: u1,
+                SM2_RXNEMPTY: u1,
+                SM3_RXNEMPTY: u1,
+                SM0_TXNFULL: u1,
+                SM1_TXNFULL: u1,
+                SM2_TXNFULL: u1,
+                SM3_TXNFULL: u1,
+                SM0: u1,
+                SM1: u1,
+                SM2: u1,
+                SM3: u1,
+                padding: u20,
+            }),
+            ///  Interrupt Force for irq0
+            IRQ0_INTF: mmio.Mmio(packed struct(u32) {
+                SM0_RXNEMPTY: u1,
+                SM1_RXNEMPTY: u1,
+                SM2_RXNEMPTY: u1,
+                SM3_RXNEMPTY: u1,
+                SM0_TXNFULL: u1,
+                SM1_TXNFULL: u1,
+                SM2_TXNFULL: u1,
+                SM3_TXNFULL: u1,
+                SM0: u1,
+                SM1: u1,
+                SM2: u1,
+                SM3: u1,
+                padding: u20,
+            }),
+            ///  Interrupt status after masking & forcing for irq0
+            IRQ0_INTS: mmio.Mmio(packed struct(u32) {
+                SM0_RXNEMPTY: u1,
+                SM1_RXNEMPTY: u1,
+                SM2_RXNEMPTY: u1,
+                SM3_RXNEMPTY: u1,
+                SM0_TXNFULL: u1,
+                SM1_TXNFULL: u1,
+                SM2_TXNFULL: u1,
+                SM3_TXNFULL: u1,
+                SM0: u1,
+                SM1: u1,
+                SM2: u1,
+                SM3: u1,
+                padding: u20,
+            }),
+            ///  Interrupt Enable for irq1
+            IRQ1_INTE: mmio.Mmio(packed struct(u32) {
+                SM0_RXNEMPTY: u1,
+                SM1_RXNEMPTY: u1,
+                SM2_RXNEMPTY: u1,
+                SM3_RXNEMPTY: u1,
+                SM0_TXNFULL: u1,
+                SM1_TXNFULL: u1,
+                SM2_TXNFULL: u1,
+                SM3_TXNFULL: u1,
+                SM0: u1,
+                SM1: u1,
+                SM2: u1,
+                SM3: u1,
+                padding: u20,
+            }),
+            ///  Interrupt Force for irq1
+            IRQ1_INTF: mmio.Mmio(packed struct(u32) {
+                SM0_RXNEMPTY: u1,
+                SM1_RXNEMPTY: u1,
+                SM2_RXNEMPTY: u1,
+                SM3_RXNEMPTY: u1,
+                SM0_TXNFULL: u1,
+                SM1_TXNFULL: u1,
+                SM2_TXNFULL: u1,
+                SM3_TXNFULL: u1,
+                SM0: u1,
+                SM1: u1,
+                SM2: u1,
+                SM3: u1,
+                padding: u20,
+            }),
+            ///  Interrupt status after masking & forcing for irq1
+            IRQ1_INTS: mmio.Mmio(packed struct(u32) {
+                SM0_RXNEMPTY: u1,
+                SM1_RXNEMPTY: u1,
+                SM2_RXNEMPTY: u1,
+                SM3_RXNEMPTY: u1,
+                SM0_TXNFULL: u1,
+                SM1_TXNFULL: u1,
+                SM2_TXNFULL: u1,
+                SM3_TXNFULL: u1,
+                SM0: u1,
+                SM1: u1,
+                SM2: u1,
+                SM3: u1,
+                padding: u20,
+            }),
+        };
+
+        ///  Control and data interface to SAR ADC
+        pub const ADC = extern struct {
+            ///  ADC Control and Status
+            CS: mmio.Mmio(packed struct(u32) {
+                ///  Power on ADC and enable its clock.
+                ///  1 - enabled. 0 - disabled.
+                EN: u1,
+                ///  Power on temperature sensor. 1 - enabled. 0 - disabled.
+                TS_EN: u1,
+                ///  Start a single conversion. Self-clearing. Ignored if start_many is asserted.
+                START_ONCE: u1,
+                ///  Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.
+                START_MANY: u1,
+                reserved8: u4,
+                ///  1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.
+                ///  0 whilst conversion in progress.
+                READY: u1,
+                ///  The most recent ADC conversion encountered an error; result is undefined or noisy.
+                ERR: u1,
+                ///  Some past ADC conversion encountered an error. Write 1 to clear.
+                ERR_STICKY: u1,
+                reserved12: u1,
+                ///  Select analog mux input. Updated automatically in round-robin mode.
+                AINSEL: u3,
+                reserved16: u1,
+                ///  Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.
+                ///  Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.
+                ///  The first channel to be sampled will be the one currently indicated by AINSEL.
+                ///  AINSEL will be updated after each conversion with the newly-selected channel.
+                RROBIN: u5,
+                padding: u11,
+            }),
+            ///  Result of most recent ADC conversion
+            RESULT: mmio.Mmio(packed struct(u32) {
+                RESULT: u12,
+                padding: u20,
+            }),
+            ///  FIFO control and status
+            FCS: mmio.Mmio(packed struct(u32) {
+                ///  If 1: write result to the FIFO after each conversion.
+                EN: u1,
+                ///  If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.
+                SHIFT: u1,
+                ///  If 1: conversion error bit appears in the FIFO alongside the result
+                ERR: u1,
+                ///  If 1: assert DMA requests when FIFO contains data
+                DREQ_EN: u1,
+                reserved8: u4,
+                EMPTY: u1,
+                FULL: u1,
+                ///  1 if the FIFO has been underflowed. Write 1 to clear.
+                UNDER: u1,
+                ///  1 if the FIFO has been overflowed. Write 1 to clear.
+                OVER: u1,
+                reserved16: u4,
+                ///  The number of conversion results currently waiting in the FIFO
+                LEVEL: u4,
+                reserved24: u4,
+                ///  DREQ/IRQ asserted when level >= threshold
+                THRESH: u4,
+                padding: u4,
+            }),
+            ///  Conversion result FIFO
+            FIFO: mmio.Mmio(packed struct(u32) {
+                VAL: u12,
+                reserved15: u3,
+                ///  1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.
+                ERR: u1,
+                padding: u16,
+            }),
+            ///  Clock divider. If non-zero, CS_START_MANY will start conversions
+            ///  at regular intervals rather than back-to-back.
+            ///  The divider is reset when either of these fields are written.
+            ///  Total period is 1 + INT + FRAC / 256
+            DIV: mmio.Mmio(packed struct(u32) {
+                ///  Fractional part of clock divisor. First-order delta-sigma.
+                FRAC: u8,
+                ///  Integer part of clock divisor.
+                INT: u16,
+                padding: u8,
+            }),
+            ///  Raw Interrupts
+            INTR: mmio.Mmio(packed struct(u32) {
+                ///  Triggered when the sample FIFO reaches a certain level.
+                ///  This level can be programmed via the FCS_THRESH field.
+                FIFO: u1,
+                padding: u31,
+            }),
+            ///  Interrupt Enable
+            INTE: mmio.Mmio(packed struct(u32) {
+                ///  Triggered when the sample FIFO reaches a certain level.
+                ///  This level can be programmed via the FCS_THRESH field.
+                FIFO: u1,
+                padding: u31,
+            }),
+            ///  Interrupt Force
+            INTF: mmio.Mmio(packed struct(u32) {
+                ///  Triggered when the sample FIFO reaches a certain level.
+                ///  This level can be programmed via the FCS_THRESH field.
+                FIFO: u1,
+                padding: u31,
+            }),
+            ///  Interrupt status after masking & forcing
+            INTS: mmio.Mmio(packed struct(u32) {
+                ///  Triggered when the sample FIFO reaches a certain level.
+                ///  This level can be programmed via the FCS_THRESH field.
+                FIFO: u1,
+                padding: u31,
+            }),
+        };
+
+        ///  Simple PWM
+        pub const PWM = extern struct {
+            ///  Control and status register
+            CH0_CSR: mmio.Mmio(packed struct(u32) {
+                ///  Enable the PWM channel.
+                EN: u1,
+                ///  1: Enable phase-correct modulation. 0: Trailing-edge
+                PH_CORRECT: u1,
+                ///  Invert output A
+                A_INV: u1,
+                ///  Invert output B
+                B_INV: u1,
+                DIVMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Free-running counting at rate dictated by fractional divider
+                        div = 0x0,
+                        ///  Fractional divider operation is gated by the PWM B pin.
+                        level = 0x1,
+                        ///  Counter advances with each rising edge of the PWM B pin.
+                        rise = 0x2,
+                        ///  Counter advances with each falling edge of the PWM B pin.
+                        fall = 0x3,
+                    },
+                },
+                ///  Retard the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
+                PH_RET: u1,
+                ///  Advance the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
+                ///  at less than full speed (div_int + div_frac / 16 > 1)
+                PH_ADV: u1,
+                padding: u24,
+            }),
+            ///  INT and FRAC form a fixed-point fractional number.
+            ///  Counting rate is system clock frequency divided by this number.
+            ///  Fractional division uses simple 1st-order sigma-delta.
+            CH0_DIV: mmio.Mmio(packed struct(u32) {
+                FRAC: u4,
+                INT: u8,
+                padding: u20,
+            }),
+            ///  Direct access to the PWM counter
+            CH0_CTR: mmio.Mmio(packed struct(u32) {
+                CH0_CTR: u16,
+                padding: u16,
+            }),
+            ///  Counter compare values
+            CH0_CC: mmio.Mmio(packed struct(u32) {
+                A: u16,
+                B: u16,
+            }),
+            ///  Counter wrap value
+            CH0_TOP: mmio.Mmio(packed struct(u32) {
+                CH0_TOP: u16,
+                padding: u16,
+            }),
+            ///  Control and status register
+            CH1_CSR: mmio.Mmio(packed struct(u32) {
+                ///  Enable the PWM channel.
+                EN: u1,
+                ///  1: Enable phase-correct modulation. 0: Trailing-edge
+                PH_CORRECT: u1,
+                ///  Invert output A
+                A_INV: u1,
+                ///  Invert output B
+                B_INV: u1,
+                DIVMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Free-running counting at rate dictated by fractional divider
+                        div = 0x0,
+                        ///  Fractional divider operation is gated by the PWM B pin.
+                        level = 0x1,
+                        ///  Counter advances with each rising edge of the PWM B pin.
+                        rise = 0x2,
+                        ///  Counter advances with each falling edge of the PWM B pin.
+                        fall = 0x3,
+                    },
+                },
+                ///  Retard the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
+                PH_RET: u1,
+                ///  Advance the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
+                ///  at less than full speed (div_int + div_frac / 16 > 1)
+                PH_ADV: u1,
+                padding: u24,
+            }),
+            ///  INT and FRAC form a fixed-point fractional number.
+            ///  Counting rate is system clock frequency divided by this number.
+            ///  Fractional division uses simple 1st-order sigma-delta.
+            CH1_DIV: mmio.Mmio(packed struct(u32) {
+                FRAC: u4,
+                INT: u8,
+                padding: u20,
+            }),
+            ///  Direct access to the PWM counter
+            CH1_CTR: mmio.Mmio(packed struct(u32) {
+                CH1_CTR: u16,
+                padding: u16,
+            }),
+            ///  Counter compare values
+            CH1_CC: mmio.Mmio(packed struct(u32) {
+                A: u16,
+                B: u16,
+            }),
+            ///  Counter wrap value
+            CH1_TOP: mmio.Mmio(packed struct(u32) {
+                CH1_TOP: u16,
+                padding: u16,
+            }),
+            ///  Control and status register
+            CH2_CSR: mmio.Mmio(packed struct(u32) {
+                ///  Enable the PWM channel.
+                EN: u1,
+                ///  1: Enable phase-correct modulation. 0: Trailing-edge
+                PH_CORRECT: u1,
+                ///  Invert output A
+                A_INV: u1,
+                ///  Invert output B
+                B_INV: u1,
+                DIVMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Free-running counting at rate dictated by fractional divider
+                        div = 0x0,
+                        ///  Fractional divider operation is gated by the PWM B pin.
+                        level = 0x1,
+                        ///  Counter advances with each rising edge of the PWM B pin.
+                        rise = 0x2,
+                        ///  Counter advances with each falling edge of the PWM B pin.
+                        fall = 0x3,
+                    },
+                },
+                ///  Retard the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
+                PH_RET: u1,
+                ///  Advance the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
+                ///  at less than full speed (div_int + div_frac / 16 > 1)
+                PH_ADV: u1,
+                padding: u24,
+            }),
+            ///  INT and FRAC form a fixed-point fractional number.
+            ///  Counting rate is system clock frequency divided by this number.
+            ///  Fractional division uses simple 1st-order sigma-delta.
+            CH2_DIV: mmio.Mmio(packed struct(u32) {
+                FRAC: u4,
+                INT: u8,
+                padding: u20,
+            }),
+            ///  Direct access to the PWM counter
+            CH2_CTR: mmio.Mmio(packed struct(u32) {
+                CH2_CTR: u16,
+                padding: u16,
+            }),
+            ///  Counter compare values
+            CH2_CC: mmio.Mmio(packed struct(u32) {
+                A: u16,
+                B: u16,
+            }),
+            ///  Counter wrap value
+            CH2_TOP: mmio.Mmio(packed struct(u32) {
+                CH2_TOP: u16,
+                padding: u16,
+            }),
+            ///  Control and status register
+            CH3_CSR: mmio.Mmio(packed struct(u32) {
+                ///  Enable the PWM channel.
+                EN: u1,
+                ///  1: Enable phase-correct modulation. 0: Trailing-edge
+                PH_CORRECT: u1,
+                ///  Invert output A
+                A_INV: u1,
+                ///  Invert output B
+                B_INV: u1,
+                DIVMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Free-running counting at rate dictated by fractional divider
+                        div = 0x0,
+                        ///  Fractional divider operation is gated by the PWM B pin.
+                        level = 0x1,
+                        ///  Counter advances with each rising edge of the PWM B pin.
+                        rise = 0x2,
+                        ///  Counter advances with each falling edge of the PWM B pin.
+                        fall = 0x3,
+                    },
+                },
+                ///  Retard the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
+                PH_RET: u1,
+                ///  Advance the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
+                ///  at less than full speed (div_int + div_frac / 16 > 1)
+                PH_ADV: u1,
+                padding: u24,
+            }),
+            ///  INT and FRAC form a fixed-point fractional number.
+            ///  Counting rate is system clock frequency divided by this number.
+            ///  Fractional division uses simple 1st-order sigma-delta.
+            CH3_DIV: mmio.Mmio(packed struct(u32) {
+                FRAC: u4,
+                INT: u8,
+                padding: u20,
+            }),
+            ///  Direct access to the PWM counter
+            CH3_CTR: mmio.Mmio(packed struct(u32) {
+                CH3_CTR: u16,
+                padding: u16,
+            }),
+            ///  Counter compare values
+            CH3_CC: mmio.Mmio(packed struct(u32) {
+                A: u16,
+                B: u16,
+            }),
+            ///  Counter wrap value
+            CH3_TOP: mmio.Mmio(packed struct(u32) {
+                CH3_TOP: u16,
+                padding: u16,
+            }),
+            ///  Control and status register
+            CH4_CSR: mmio.Mmio(packed struct(u32) {
+                ///  Enable the PWM channel.
+                EN: u1,
+                ///  1: Enable phase-correct modulation. 0: Trailing-edge
+                PH_CORRECT: u1,
+                ///  Invert output A
+                A_INV: u1,
+                ///  Invert output B
+                B_INV: u1,
+                DIVMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Free-running counting at rate dictated by fractional divider
+                        div = 0x0,
+                        ///  Fractional divider operation is gated by the PWM B pin.
+                        level = 0x1,
+                        ///  Counter advances with each rising edge of the PWM B pin.
+                        rise = 0x2,
+                        ///  Counter advances with each falling edge of the PWM B pin.
+                        fall = 0x3,
+                    },
+                },
+                ///  Retard the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
+                PH_RET: u1,
+                ///  Advance the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
+                ///  at less than full speed (div_int + div_frac / 16 > 1)
+                PH_ADV: u1,
+                padding: u24,
+            }),
+            ///  INT and FRAC form a fixed-point fractional number.
+            ///  Counting rate is system clock frequency divided by this number.
+            ///  Fractional division uses simple 1st-order sigma-delta.
+            CH4_DIV: mmio.Mmio(packed struct(u32) {
+                FRAC: u4,
+                INT: u8,
+                padding: u20,
+            }),
+            ///  Direct access to the PWM counter
+            CH4_CTR: mmio.Mmio(packed struct(u32) {
+                CH4_CTR: u16,
+                padding: u16,
+            }),
+            ///  Counter compare values
+            CH4_CC: mmio.Mmio(packed struct(u32) {
+                A: u16,
+                B: u16,
+            }),
+            ///  Counter wrap value
+            CH4_TOP: mmio.Mmio(packed struct(u32) {
+                CH4_TOP: u16,
+                padding: u16,
+            }),
+            ///  Control and status register
+            CH5_CSR: mmio.Mmio(packed struct(u32) {
+                ///  Enable the PWM channel.
+                EN: u1,
+                ///  1: Enable phase-correct modulation. 0: Trailing-edge
+                PH_CORRECT: u1,
+                ///  Invert output A
+                A_INV: u1,
+                ///  Invert output B
+                B_INV: u1,
+                DIVMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Free-running counting at rate dictated by fractional divider
+                        div = 0x0,
+                        ///  Fractional divider operation is gated by the PWM B pin.
+                        level = 0x1,
+                        ///  Counter advances with each rising edge of the PWM B pin.
+                        rise = 0x2,
+                        ///  Counter advances with each falling edge of the PWM B pin.
+                        fall = 0x3,
+                    },
+                },
+                ///  Retard the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
+                PH_RET: u1,
+                ///  Advance the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
+                ///  at less than full speed (div_int + div_frac / 16 > 1)
+                PH_ADV: u1,
+                padding: u24,
+            }),
+            ///  INT and FRAC form a fixed-point fractional number.
+            ///  Counting rate is system clock frequency divided by this number.
+            ///  Fractional division uses simple 1st-order sigma-delta.
+            CH5_DIV: mmio.Mmio(packed struct(u32) {
+                FRAC: u4,
+                INT: u8,
+                padding: u20,
+            }),
+            ///  Direct access to the PWM counter
+            CH5_CTR: mmio.Mmio(packed struct(u32) {
+                CH5_CTR: u16,
+                padding: u16,
+            }),
+            ///  Counter compare values
+            CH5_CC: mmio.Mmio(packed struct(u32) {
+                A: u16,
+                B: u16,
+            }),
+            ///  Counter wrap value
+            CH5_TOP: mmio.Mmio(packed struct(u32) {
+                CH5_TOP: u16,
+                padding: u16,
+            }),
+            ///  Control and status register
+            CH6_CSR: mmio.Mmio(packed struct(u32) {
+                ///  Enable the PWM channel.
+                EN: u1,
+                ///  1: Enable phase-correct modulation. 0: Trailing-edge
+                PH_CORRECT: u1,
+                ///  Invert output A
+                A_INV: u1,
+                ///  Invert output B
+                B_INV: u1,
+                DIVMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Free-running counting at rate dictated by fractional divider
+                        div = 0x0,
+                        ///  Fractional divider operation is gated by the PWM B pin.
+                        level = 0x1,
+                        ///  Counter advances with each rising edge of the PWM B pin.
+                        rise = 0x2,
+                        ///  Counter advances with each falling edge of the PWM B pin.
+                        fall = 0x3,
+                    },
+                },
+                ///  Retard the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
+                PH_RET: u1,
+                ///  Advance the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
+                ///  at less than full speed (div_int + div_frac / 16 > 1)
+                PH_ADV: u1,
+                padding: u24,
+            }),
+            ///  INT and FRAC form a fixed-point fractional number.
+            ///  Counting rate is system clock frequency divided by this number.
+            ///  Fractional division uses simple 1st-order sigma-delta.
+            CH6_DIV: mmio.Mmio(packed struct(u32) {
+                FRAC: u4,
+                INT: u8,
+                padding: u20,
+            }),
+            ///  Direct access to the PWM counter
+            CH6_CTR: mmio.Mmio(packed struct(u32) {
+                CH6_CTR: u16,
+                padding: u16,
+            }),
+            ///  Counter compare values
+            CH6_CC: mmio.Mmio(packed struct(u32) {
+                A: u16,
+                B: u16,
+            }),
+            ///  Counter wrap value
+            CH6_TOP: mmio.Mmio(packed struct(u32) {
+                CH6_TOP: u16,
+                padding: u16,
+            }),
+            ///  Control and status register
+            CH7_CSR: mmio.Mmio(packed struct(u32) {
+                ///  Enable the PWM channel.
+                EN: u1,
+                ///  1: Enable phase-correct modulation. 0: Trailing-edge
+                PH_CORRECT: u1,
+                ///  Invert output A
+                A_INV: u1,
+                ///  Invert output B
+                B_INV: u1,
+                DIVMODE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        ///  Free-running counting at rate dictated by fractional divider
+                        div = 0x0,
+                        ///  Fractional divider operation is gated by the PWM B pin.
+                        level = 0x1,
+                        ///  Counter advances with each rising edge of the PWM B pin.
+                        rise = 0x2,
+                        ///  Counter advances with each falling edge of the PWM B pin.
+                        fall = 0x3,
+                    },
+                },
+                ///  Retard the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
+                PH_RET: u1,
+                ///  Advance the phase of the counter by 1 count, while it is running.
+                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
+                ///  at less than full speed (div_int + div_frac / 16 > 1)
+                PH_ADV: u1,
+                padding: u24,
+            }),
+            ///  INT and FRAC form a fixed-point fractional number.
+            ///  Counting rate is system clock frequency divided by this number.
+            ///  Fractional division uses simple 1st-order sigma-delta.
+            CH7_DIV: mmio.Mmio(packed struct(u32) {
+                FRAC: u4,
+                INT: u8,
+                padding: u20,
+            }),
+            ///  Direct access to the PWM counter
+            CH7_CTR: mmio.Mmio(packed struct(u32) {
+                CH7_CTR: u16,
+                padding: u16,
+            }),
+            ///  Counter compare values
+            CH7_CC: mmio.Mmio(packed struct(u32) {
+                A: u16,
+                B: u16,
+            }),
+            ///  Counter wrap value
+            CH7_TOP: mmio.Mmio(packed struct(u32) {
+                CH7_TOP: u16,
+                padding: u16,
+            }),
+            ///  This register aliases the CSR_EN bits for all channels.
+            ///  Writing to this register allows multiple channels to be enabled
+            ///  or disabled simultaneously, so they can run in perfect sync.
+            ///  For each channel, there is only one physical EN register bit,
+            ///  which can be accessed through here or CHx_CSR.
+            EN: mmio.Mmio(packed struct(u32) {
+                CH0: u1,
+                CH1: u1,
+                CH2: u1,
+                CH3: u1,
+                CH4: u1,
+                CH5: u1,
+                CH6: u1,
+                CH7: u1,
+                padding: u24,
+            }),
+            ///  Raw Interrupts
+            INTR: mmio.Mmio(packed struct(u32) {
+                CH0: u1,
+                CH1: u1,
+                CH2: u1,
+                CH3: u1,
+                CH4: u1,
+                CH5: u1,
+                CH6: u1,
+                CH7: u1,
+                padding: u24,
+            }),
+            ///  Interrupt Enable
+            INTE: mmio.Mmio(packed struct(u32) {
+                CH0: u1,
+                CH1: u1,
+                CH2: u1,
+                CH3: u1,
+                CH4: u1,
+                CH5: u1,
+                CH6: u1,
+                CH7: u1,
+                padding: u24,
+            }),
+            ///  Interrupt Force
+            INTF: mmio.Mmio(packed struct(u32) {
+                CH0: u1,
+                CH1: u1,
+                CH2: u1,
+                CH3: u1,
+                CH4: u1,
+                CH5: u1,
+                CH6: u1,
+                CH7: u1,
+                padding: u24,
+            }),
+            ///  Interrupt status after masking & forcing
+            INTS: mmio.Mmio(packed struct(u32) {
+                CH0: u1,
+                CH1: u1,
+                CH2: u1,
+                CH3: u1,
+                CH4: u1,
+                CH5: u1,
+                CH6: u1,
+                CH7: u1,
+                padding: u24,
+            }),
+        };
+
+        ///  Controls time and alarms
+        ///  time is a 64 bit value indicating the time in usec since power-on
+        ///  timeh is the top 32 bits of time & timel is the bottom 32 bits
+        ///  to change time write to timelw before timehw
+        ///  to read time read from timelr before timehr
+        ///  An alarm is set by setting alarm_enable and writing to the corresponding alarm register
+        ///  When an alarm is pending, the corresponding alarm_running signal will be high
+        ///  An alarm can be cancelled before it has finished by clearing the alarm_enable
+        ///  When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared
+        ///  To clear the interrupt write a 1 to the corresponding alarm_irq
+        pub const TIMER = extern struct {
+            ///  Write to bits 63:32 of time
+            ///  always write timelw before timehw
+            TIMEHW: u32,
+            ///  Write to bits 31:0 of time
+            ///  writes do not get copied to time until timehw is written
+            TIMELW: u32,
+            ///  Read from bits 63:32 of time
+            ///  always read timelr before timehr
+            TIMEHR: u32,
+            ///  Read from bits 31:0 of time
+            TIMELR: u32,
+            ///  Arm alarm 0, and configure the time it will fire.
+            ///  Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
+            ///  The alarm will disarm itself once it fires, and can
+            ///  be disarmed early using the ARMED status register.
+            ALARM0: u32,
+            ///  Arm alarm 1, and configure the time it will fire.
+            ///  Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
+            ///  The alarm will disarm itself once it fires, and can
+            ///  be disarmed early using the ARMED status register.
+            ALARM1: u32,
+            ///  Arm alarm 2, and configure the time it will fire.
+            ///  Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
+            ///  The alarm will disarm itself once it fires, and can
+            ///  be disarmed early using the ARMED status register.
+            ALARM2: u32,
+            ///  Arm alarm 3, and configure the time it will fire.
+            ///  Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
+            ///  The alarm will disarm itself once it fires, and can
+            ///  be disarmed early using the ARMED status register.
+            ALARM3: u32,
+            ///  Indicates the armed/disarmed status of each alarm.
+            ///  A write to the corresponding ALARMx register arms the alarm.
+            ///  Alarms automatically disarm upon firing, but writing ones here
+            ///  will disarm immediately without waiting to fire.
+            ARMED: mmio.Mmio(packed struct(u32) {
+                ARMED: u4,
+                padding: u28,
+            }),
+            ///  Raw read from bits 63:32 of time (no side effects)
+            TIMERAWH: u32,
+            ///  Raw read from bits 31:0 of time (no side effects)
+            TIMERAWL: u32,
+            ///  Set bits high to enable pause when the corresponding debug ports are active
+            DBGPAUSE: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Pause when processor 0 is in debug mode
+                DBG0: u1,
+                ///  Pause when processor 1 is in debug mode
+                DBG1: u1,
+                padding: u29,
+            }),
+            ///  Set high to pause the timer
+            PAUSE: mmio.Mmio(packed struct(u32) {
+                PAUSE: u1,
+                padding: u31,
+            }),
+            ///  Raw Interrupts
+            INTR: mmio.Mmio(packed struct(u32) {
+                ALARM_0: u1,
+                ALARM_1: u1,
+                ALARM_2: u1,
+                ALARM_3: u1,
+                padding: u28,
+            }),
+            ///  Interrupt Enable
+            INTE: mmio.Mmio(packed struct(u32) {
+                ALARM_0: u1,
+                ALARM_1: u1,
+                ALARM_2: u1,
+                ALARM_3: u1,
+                padding: u28,
+            }),
+            ///  Interrupt Force
+            INTF: mmio.Mmio(packed struct(u32) {
+                ALARM_0: u1,
+                ALARM_1: u1,
+                ALARM_2: u1,
+                ALARM_3: u1,
+                padding: u28,
+            }),
+            ///  Interrupt status after masking & forcing
+            INTS: mmio.Mmio(packed struct(u32) {
+                ALARM_0: u1,
+                ALARM_1: u1,
+                ALARM_2: u1,
+                ALARM_3: u1,
+                padding: u28,
+            }),
+        };
+
+        pub const WATCHDOG = extern struct {
+            ///  Watchdog control
+            ///  The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.
+            ///  The watchdog can be triggered in software.
+            CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered
+                TIME: u24,
+                ///  Pause the watchdog timer when JTAG is accessing the bus fabric
+                PAUSE_JTAG: u1,
+                ///  Pause the watchdog timer when processor 0 is in debug mode
+                PAUSE_DBG0: u1,
+                ///  Pause the watchdog timer when processor 1 is in debug mode
+                PAUSE_DBG1: u1,
+                reserved30: u3,
+                ///  When not enabled the watchdog timer is paused
+                ENABLE: u1,
+                ///  Trigger a watchdog reset
+                TRIGGER: u1,
+            }),
+            ///  Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).
+            LOAD: mmio.Mmio(packed struct(u32) {
+                LOAD: u24,
+                padding: u8,
+            }),
+            ///  Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.
+            REASON: mmio.Mmio(packed struct(u32) {
+                TIMER: u1,
+                FORCE: u1,
+                padding: u30,
+            }),
+            ///  Scratch register. Information persists through soft reset of the chip.
+            SCRATCH0: u32,
+            ///  Scratch register. Information persists through soft reset of the chip.
+            SCRATCH1: u32,
+            ///  Scratch register. Information persists through soft reset of the chip.
+            SCRATCH2: u32,
+            ///  Scratch register. Information persists through soft reset of the chip.
+            SCRATCH3: u32,
+            ///  Scratch register. Information persists through soft reset of the chip.
+            SCRATCH4: u32,
+            ///  Scratch register. Information persists through soft reset of the chip.
+            SCRATCH5: u32,
+            ///  Scratch register. Information persists through soft reset of the chip.
+            SCRATCH6: u32,
+            ///  Scratch register. Information persists through soft reset of the chip.
+            SCRATCH7: u32,
+            ///  Controls the tick generator
+            TICK: mmio.Mmio(packed struct(u32) {
+                ///  Total number of clk_tick cycles before the next tick.
+                CYCLES: u9,
+                ///  start / stop tick generation
+                ENABLE: u1,
+                ///  Is the tick generator running?
+                RUNNING: u1,
+                ///  Count down timer: the remaining number clk_tick cycles before the next tick is generated.
+                COUNT: u9,
+                padding: u12,
+            }),
+        };
+
+        ///  Register block to control RTC
+        pub const RTC = extern struct {
+            ///  Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled.
+            CLKDIV_M1: mmio.Mmio(packed struct(u32) {
+                CLKDIV_M1: u16,
+                padding: u16,
+            }),
+            ///  RTC setup register 0
+            SETUP_0: mmio.Mmio(packed struct(u32) {
+                ///  Day of the month (1..31)
+                DAY: u5,
+                reserved8: u3,
+                ///  Month (1..12)
+                MONTH: u4,
+                ///  Year
+                YEAR: u12,
+                padding: u8,
+            }),
+            ///  RTC setup register 1
+            SETUP_1: mmio.Mmio(packed struct(u32) {
+                ///  Seconds
+                SEC: u6,
+                reserved8: u2,
+                ///  Minutes
+                MIN: u6,
+                reserved16: u2,
+                ///  Hours
+                HOUR: u5,
+                reserved24: u3,
+                ///  Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
+                DOTW: u3,
+                padding: u5,
+            }),
+            ///  RTC Control and status
+            CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Enable RTC
+                RTC_ENABLE: u1,
+                ///  RTC enabled (running)
+                RTC_ACTIVE: u1,
+                reserved4: u2,
+                ///  Load RTC
+                LOAD: u1,
+                reserved8: u3,
+                ///  If set, leapyear is forced off.
+                ///  Useful for years divisible by 100 but not by 400
+                FORCE_NOTLEAPYEAR: u1,
+                padding: u23,
+            }),
+            ///  Interrupt setup register 0
+            IRQ_SETUP_0: mmio.Mmio(packed struct(u32) {
+                ///  Day of the month (1..31)
+                DAY: u5,
+                reserved8: u3,
+                ///  Month (1..12)
+                MONTH: u4,
+                ///  Year
+                YEAR: u12,
+                ///  Enable day matching
+                DAY_ENA: u1,
+                ///  Enable month matching
+                MONTH_ENA: u1,
+                ///  Enable year matching
+                YEAR_ENA: u1,
+                reserved28: u1,
+                ///  Global match enable. Don't change any other value while this one is enabled
+                MATCH_ENA: u1,
+                MATCH_ACTIVE: u1,
+                padding: u2,
+            }),
+            ///  Interrupt setup register 1
+            IRQ_SETUP_1: mmio.Mmio(packed struct(u32) {
+                ///  Seconds
+                SEC: u6,
+                reserved8: u2,
+                ///  Minutes
+                MIN: u6,
+                reserved16: u2,
+                ///  Hours
+                HOUR: u5,
+                reserved24: u3,
+                ///  Day of the week
+                DOTW: u3,
+                reserved28: u1,
+                ///  Enable second matching
+                SEC_ENA: u1,
+                ///  Enable minute matching
+                MIN_ENA: u1,
+                ///  Enable hour matching
+                HOUR_ENA: u1,
+                ///  Enable day of the week matching
+                DOTW_ENA: u1,
+            }),
+            ///  RTC register 1.
+            RTC_1: mmio.Mmio(packed struct(u32) {
+                ///  Day of the month (1..31)
+                DAY: u5,
+                reserved8: u3,
+                ///  Month (1..12)
+                MONTH: u4,
+                ///  Year
+                YEAR: u12,
+                padding: u8,
+            }),
+            ///  RTC register 0
+            ///  Read this before RTC 1!
+            RTC_0: mmio.Mmio(packed struct(u32) {
+                ///  Seconds
+                SEC: u6,
+                reserved8: u2,
+                ///  Minutes
+                MIN: u6,
+                reserved16: u2,
+                ///  Hours
+                HOUR: u5,
+                reserved24: u3,
+                ///  Day of the week
+                DOTW: u3,
+                padding: u5,
+            }),
+            ///  Raw Interrupts
+            INTR: mmio.Mmio(packed struct(u32) {
+                RTC: u1,
+                padding: u31,
+            }),
+            ///  Interrupt Enable
+            INTE: mmio.Mmio(packed struct(u32) {
+                RTC: u1,
+                padding: u31,
+            }),
+            ///  Interrupt Force
+            INTF: mmio.Mmio(packed struct(u32) {
+                RTC: u1,
+                padding: u31,
+            }),
+            ///  Interrupt status after masking & forcing
+            INTS: mmio.Mmio(packed struct(u32) {
+                RTC: u1,
+                padding: u31,
+            }),
+        };
+
+        pub const ROSC = extern struct {
+            ///  Ring Oscillator control
+            CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Controls the number of delay stages in the ROSC ring
+                ///  LOW uses stages 0 to 7
+                ///  MEDIUM uses stages 0 to 5
+                ///  HIGH uses stages 0 to 3
+                ///  TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications
+                ///  The clock output will not glitch when changing the range up one step at a time
+                ///  The clock output will glitch when changing the range down
+                ///  Note: the values here are gray coded which is why HIGH comes before TOOHIGH
+                FREQ_RANGE: packed union {
+                    raw: u12,
+                    value: enum(u12) {
+                        LOW = 0xfa4,
+                        MEDIUM = 0xfa5,
+                        HIGH = 0xfa7,
+                        TOOHIGH = 0xfa6,
+                        _,
+                    },
+                },
+                ///  On power-up this field is initialised to ENABLE
+                ///  The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up
+                ///  The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.
+                ENABLE: packed union {
+                    raw: u12,
+                    value: enum(u12) {
+                        DISABLE = 0xd1e,
+                        ENABLE = 0xfab,
+                        _,
+                    },
+                },
+                padding: u8,
+            }),
+            ///  The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage
+            ///  The drive strength has 4 levels determined by the number of bits set
+            ///  Increasing the number of bits set increases the drive strength and increases the oscillation frequency
+            ///  0 bits set is the default drive strength
+            ///  1 bit set doubles the drive strength
+            ///  2 bits set triples drive strength
+            ///  3 bits set quadruples drive strength
+            FREQA: mmio.Mmio(packed struct(u32) {
+                ///  Stage 0 drive strength
+                DS0: u3,
+                reserved4: u1,
+                ///  Stage 1 drive strength
+                DS1: u3,
+                reserved8: u1,
+                ///  Stage 2 drive strength
+                DS2: u3,
+                reserved12: u1,
+                ///  Stage 3 drive strength
+                DS3: u3,
+                reserved16: u1,
+                ///  Set to 0x9696 to apply the settings
+                ///  Any other value in this field will set all drive strengths to 0
+                PASSWD: packed union {
+                    raw: u16,
+                    value: enum(u16) {
+                        PASS = 0x9696,
+                        _,
+                    },
+                },
+            }),
+            ///  For a detailed description see freqa register
+            FREQB: mmio.Mmio(packed struct(u32) {
+                ///  Stage 4 drive strength
+                DS4: u3,
+                reserved4: u1,
+                ///  Stage 5 drive strength
+                DS5: u3,
+                reserved8: u1,
+                ///  Stage 6 drive strength
+                DS6: u3,
+                reserved12: u1,
+                ///  Stage 7 drive strength
+                DS7: u3,
+                reserved16: u1,
+                ///  Set to 0x9696 to apply the settings
+                ///  Any other value in this field will set all drive strengths to 0
+                PASSWD: packed union {
+                    raw: u16,
+                    value: enum(u16) {
+                        PASS = 0x9696,
+                        _,
+                    },
+                },
+            }),
+            ///  Ring Oscillator pause control
+            ///  This is used to save power by pausing the ROSC
+            ///  On power-up this field is initialised to WAKE
+            ///  An invalid write will also select WAKE
+            ///  Warning: setup the irq before selecting dormant mode
+            DORMANT: u32,
+            ///  Controls the output divider
+            DIV: mmio.Mmio(packed struct(u32) {
+                ///  set to 0xaa0 + div where
+                ///  div = 0 divides by 32
+                ///  div = 1-31 divides by div
+                ///  any other value sets div=31
+                ///  this register resets to div=16
+                DIV: packed union {
+                    raw: u12,
+                    value: enum(u12) {
+                        PASS = 0xaa0,
+                        _,
+                    },
+                },
+                padding: u20,
+            }),
+            ///  Controls the phase shifted output
+            PHASE: mmio.Mmio(packed struct(u32) {
+                ///  phase shift the phase-shifted output by SHIFT input clocks
+                ///  this can be changed on-the-fly
+                ///  must be set to 0 before setting div=1
+                SHIFT: u2,
+                ///  invert the phase-shifted output
+                ///  this is ignored when div=1
+                FLIP: u1,
+                ///  enable the phase-shifted output
+                ///  this can be changed on-the-fly
+                ENABLE: u1,
+                ///  set to 0xaa
+                ///  any other value enables the output with shift=0
+                PASSWD: u8,
+                padding: u20,
+            }),
+            ///  Ring Oscillator Status
+            STATUS: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Oscillator is enabled but not necessarily running and stable
+                ///  this resets to 0 but transitions to 1 during chip startup
+                ENABLED: u1,
+                reserved16: u3,
+                ///  post-divider is running
+                ///  this resets to 0 but transitions to 1 during chip startup
+                DIV_RUNNING: u1,
+                reserved24: u7,
+                ///  An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
+                BADWRITE: u1,
+                reserved31: u6,
+                ///  Oscillator is running and stable
+                STABLE: u1,
+            }),
+            ///  This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency
+            RANDOMBIT: mmio.Mmio(packed struct(u32) {
+                RANDOMBIT: u1,
+                padding: u31,
+            }),
+            ///  A down counter running at the ROSC frequency which counts to zero and stops.
+            ///  To start the counter write a non-zero value.
+            ///  Can be used for short software pauses when setting up time sensitive hardware.
+            COUNT: mmio.Mmio(packed struct(u32) {
+                COUNT: u8,
+                padding: u24,
+            }),
+        };
+
+        ///  control and status for on-chip voltage regulator and chip level reset subsystem
+        pub const VREG_AND_CHIP_RESET = extern struct {
+            ///  Voltage regulator control and status
+            VREG: mmio.Mmio(packed struct(u32) {
+                ///  enable
+                ///  0=not enabled, 1=enabled
+                EN: u1,
+                ///  high impedance mode select
+                ///  0=not in high impedance mode, 1=in high impedance mode
+                HIZ: u1,
+                reserved4: u2,
+                ///  output voltage select
+                ///  0000 to 0101 - 0.80V
+                ///  0110 - 0.85V
+                ///  0111 - 0.90V
+                ///  1000 - 0.95V
+                ///  1001 - 1.00V
+                ///  1010 - 1.05V
+                ///  1011 - 1.10V (default)
+                ///  1100 - 1.15V
+                ///  1101 - 1.20V
+                ///  1110 - 1.25V
+                ///  1111 - 1.30V
+                VSEL: u4,
+                reserved12: u4,
+                ///  regulation status
+                ///  0=not in regulation, 1=in regulation
+                ROK: u1,
+                padding: u19,
+            }),
+            ///  brown-out detection control
+            BOD: mmio.Mmio(packed struct(u32) {
+                ///  enable
+                ///  0=not enabled, 1=enabled
+                EN: u1,
+                reserved4: u3,
+                ///  threshold select
+                ///  0000 - 0.473V
+                ///  0001 - 0.516V
+                ///  0010 - 0.559V
+                ///  0011 - 0.602V
+                ///  0100 - 0.645V
+                ///  0101 - 0.688V
+                ///  0110 - 0.731V
+                ///  0111 - 0.774V
+                ///  1000 - 0.817V
+                ///  1001 - 0.860V (default)
+                ///  1010 - 0.903V
+                ///  1011 - 0.946V
+                ///  1100 - 0.989V
+                ///  1101 - 1.032V
+                ///  1110 - 1.075V
+                ///  1111 - 1.118V
+                VSEL: u4,
+                padding: u24,
+            }),
+            ///  Chip reset control and status
+            CHIP_RESET: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Last reset was from the power-on reset or brown-out detection blocks
+                HAD_POR: u1,
+                reserved16: u7,
+                ///  Last reset was from the RUN pin
+                HAD_RUN: u1,
+                reserved20: u3,
+                ///  Last reset was from the debug port
+                HAD_PSM_RESTART: u1,
+                reserved24: u3,
+                ///  This is set by psm_restart from the debugger.
+                ///  Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.
+                ///  In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor.
+                PSM_RESTART_FLAG: u1,
+                padding: u7,
+            }),
+        };
+
+        ///  Testbench manager. Allows the programmer to know what platform their software is running on.
+        pub const TBMAN = extern struct {
+            ///  Indicates the type of platform in use
+            PLATFORM: mmio.Mmio(packed struct(u32) {
+                ///  Indicates the platform is an ASIC
+                ASIC: u1,
+                ///  Indicates the platform is an FPGA
+                FPGA: u1,
+                padding: u30,
+            }),
+        };
+
+        ///  DMA with separate read and write masters
+        pub const DMA = extern struct {
+            ///  DMA Channel 0 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH0_READ_ADDR: u32,
+            ///  DMA Channel 0 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH0_WRITE_ADDR: u32,
+            ///  DMA Channel 0 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH0_TRANS_COUNT: u32,
+            ///  DMA Channel 0 Control and Status
+            CH0_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 0 CTRL register
+            CH0_AL1_CTRL: u32,
+            ///  Alias for channel 0 READ_ADDR register
+            CH0_AL1_READ_ADDR: u32,
+            ///  Alias for channel 0 WRITE_ADDR register
+            CH0_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 0 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH0_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 0 CTRL register
+            CH0_AL2_CTRL: u32,
+            ///  Alias for channel 0 TRANS_COUNT register
+            CH0_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 0 READ_ADDR register
+            CH0_AL2_READ_ADDR: u32,
+            ///  Alias for channel 0 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH0_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 0 CTRL register
+            CH0_AL3_CTRL: u32,
+            ///  Alias for channel 0 WRITE_ADDR register
+            CH0_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 0 TRANS_COUNT register
+            CH0_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 0 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH0_AL3_READ_ADDR_TRIG: u32,
+            ///  DMA Channel 1 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH1_READ_ADDR: u32,
+            ///  DMA Channel 1 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH1_WRITE_ADDR: u32,
+            ///  DMA Channel 1 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH1_TRANS_COUNT: u32,
+            ///  DMA Channel 1 Control and Status
+            CH1_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 1 CTRL register
+            CH1_AL1_CTRL: u32,
+            ///  Alias for channel 1 READ_ADDR register
+            CH1_AL1_READ_ADDR: u32,
+            ///  Alias for channel 1 WRITE_ADDR register
+            CH1_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 1 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH1_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 1 CTRL register
+            CH1_AL2_CTRL: u32,
+            ///  Alias for channel 1 TRANS_COUNT register
+            CH1_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 1 READ_ADDR register
+            CH1_AL2_READ_ADDR: u32,
+            ///  Alias for channel 1 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH1_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 1 CTRL register
+            CH1_AL3_CTRL: u32,
+            ///  Alias for channel 1 WRITE_ADDR register
+            CH1_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 1 TRANS_COUNT register
+            CH1_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 1 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH1_AL3_READ_ADDR_TRIG: u32,
+            ///  DMA Channel 2 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH2_READ_ADDR: u32,
+            ///  DMA Channel 2 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH2_WRITE_ADDR: u32,
+            ///  DMA Channel 2 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH2_TRANS_COUNT: u32,
+            ///  DMA Channel 2 Control and Status
+            CH2_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 2 CTRL register
+            CH2_AL1_CTRL: u32,
+            ///  Alias for channel 2 READ_ADDR register
+            CH2_AL1_READ_ADDR: u32,
+            ///  Alias for channel 2 WRITE_ADDR register
+            CH2_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 2 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH2_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 2 CTRL register
+            CH2_AL2_CTRL: u32,
+            ///  Alias for channel 2 TRANS_COUNT register
+            CH2_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 2 READ_ADDR register
+            CH2_AL2_READ_ADDR: u32,
+            ///  Alias for channel 2 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH2_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 2 CTRL register
+            CH2_AL3_CTRL: u32,
+            ///  Alias for channel 2 WRITE_ADDR register
+            CH2_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 2 TRANS_COUNT register
+            CH2_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 2 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH2_AL3_READ_ADDR_TRIG: u32,
+            ///  DMA Channel 3 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH3_READ_ADDR: u32,
+            ///  DMA Channel 3 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH3_WRITE_ADDR: u32,
+            ///  DMA Channel 3 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH3_TRANS_COUNT: u32,
+            ///  DMA Channel 3 Control and Status
+            CH3_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 3 CTRL register
+            CH3_AL1_CTRL: u32,
+            ///  Alias for channel 3 READ_ADDR register
+            CH3_AL1_READ_ADDR: u32,
+            ///  Alias for channel 3 WRITE_ADDR register
+            CH3_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 3 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH3_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 3 CTRL register
+            CH3_AL2_CTRL: u32,
+            ///  Alias for channel 3 TRANS_COUNT register
+            CH3_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 3 READ_ADDR register
+            CH3_AL2_READ_ADDR: u32,
+            ///  Alias for channel 3 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH3_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 3 CTRL register
+            CH3_AL3_CTRL: u32,
+            ///  Alias for channel 3 WRITE_ADDR register
+            CH3_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 3 TRANS_COUNT register
+            CH3_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 3 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH3_AL3_READ_ADDR_TRIG: u32,
+            ///  DMA Channel 4 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH4_READ_ADDR: u32,
+            ///  DMA Channel 4 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH4_WRITE_ADDR: u32,
+            ///  DMA Channel 4 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH4_TRANS_COUNT: u32,
+            ///  DMA Channel 4 Control and Status
+            CH4_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 4 CTRL register
+            CH4_AL1_CTRL: u32,
+            ///  Alias for channel 4 READ_ADDR register
+            CH4_AL1_READ_ADDR: u32,
+            ///  Alias for channel 4 WRITE_ADDR register
+            CH4_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 4 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH4_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 4 CTRL register
+            CH4_AL2_CTRL: u32,
+            ///  Alias for channel 4 TRANS_COUNT register
+            CH4_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 4 READ_ADDR register
+            CH4_AL2_READ_ADDR: u32,
+            ///  Alias for channel 4 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH4_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 4 CTRL register
+            CH4_AL3_CTRL: u32,
+            ///  Alias for channel 4 WRITE_ADDR register
+            CH4_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 4 TRANS_COUNT register
+            CH4_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 4 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH4_AL3_READ_ADDR_TRIG: u32,
+            ///  DMA Channel 5 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH5_READ_ADDR: u32,
+            ///  DMA Channel 5 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH5_WRITE_ADDR: u32,
+            ///  DMA Channel 5 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH5_TRANS_COUNT: u32,
+            ///  DMA Channel 5 Control and Status
+            CH5_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 5 CTRL register
+            CH5_AL1_CTRL: u32,
+            ///  Alias for channel 5 READ_ADDR register
+            CH5_AL1_READ_ADDR: u32,
+            ///  Alias for channel 5 WRITE_ADDR register
+            CH5_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 5 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH5_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 5 CTRL register
+            CH5_AL2_CTRL: u32,
+            ///  Alias for channel 5 TRANS_COUNT register
+            CH5_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 5 READ_ADDR register
+            CH5_AL2_READ_ADDR: u32,
+            ///  Alias for channel 5 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH5_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 5 CTRL register
+            CH5_AL3_CTRL: u32,
+            ///  Alias for channel 5 WRITE_ADDR register
+            CH5_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 5 TRANS_COUNT register
+            CH5_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 5 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH5_AL3_READ_ADDR_TRIG: u32,
+            ///  DMA Channel 6 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH6_READ_ADDR: u32,
+            ///  DMA Channel 6 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH6_WRITE_ADDR: u32,
+            ///  DMA Channel 6 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH6_TRANS_COUNT: u32,
+            ///  DMA Channel 6 Control and Status
+            CH6_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 6 CTRL register
+            CH6_AL1_CTRL: u32,
+            ///  Alias for channel 6 READ_ADDR register
+            CH6_AL1_READ_ADDR: u32,
+            ///  Alias for channel 6 WRITE_ADDR register
+            CH6_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 6 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH6_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 6 CTRL register
+            CH6_AL2_CTRL: u32,
+            ///  Alias for channel 6 TRANS_COUNT register
+            CH6_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 6 READ_ADDR register
+            CH6_AL2_READ_ADDR: u32,
+            ///  Alias for channel 6 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH6_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 6 CTRL register
+            CH6_AL3_CTRL: u32,
+            ///  Alias for channel 6 WRITE_ADDR register
+            CH6_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 6 TRANS_COUNT register
+            CH6_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 6 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH6_AL3_READ_ADDR_TRIG: u32,
+            ///  DMA Channel 7 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH7_READ_ADDR: u32,
+            ///  DMA Channel 7 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH7_WRITE_ADDR: u32,
+            ///  DMA Channel 7 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH7_TRANS_COUNT: u32,
+            ///  DMA Channel 7 Control and Status
+            CH7_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 7 CTRL register
+            CH7_AL1_CTRL: u32,
+            ///  Alias for channel 7 READ_ADDR register
+            CH7_AL1_READ_ADDR: u32,
+            ///  Alias for channel 7 WRITE_ADDR register
+            CH7_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 7 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH7_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 7 CTRL register
+            CH7_AL2_CTRL: u32,
+            ///  Alias for channel 7 TRANS_COUNT register
+            CH7_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 7 READ_ADDR register
+            CH7_AL2_READ_ADDR: u32,
+            ///  Alias for channel 7 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH7_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 7 CTRL register
+            CH7_AL3_CTRL: u32,
+            ///  Alias for channel 7 WRITE_ADDR register
+            CH7_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 7 TRANS_COUNT register
+            CH7_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 7 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH7_AL3_READ_ADDR_TRIG: u32,
+            ///  DMA Channel 8 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH8_READ_ADDR: u32,
+            ///  DMA Channel 8 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH8_WRITE_ADDR: u32,
+            ///  DMA Channel 8 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH8_TRANS_COUNT: u32,
+            ///  DMA Channel 8 Control and Status
+            CH8_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 8 CTRL register
+            CH8_AL1_CTRL: u32,
+            ///  Alias for channel 8 READ_ADDR register
+            CH8_AL1_READ_ADDR: u32,
+            ///  Alias for channel 8 WRITE_ADDR register
+            CH8_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 8 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH8_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 8 CTRL register
+            CH8_AL2_CTRL: u32,
+            ///  Alias for channel 8 TRANS_COUNT register
+            CH8_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 8 READ_ADDR register
+            CH8_AL2_READ_ADDR: u32,
+            ///  Alias for channel 8 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH8_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 8 CTRL register
+            CH8_AL3_CTRL: u32,
+            ///  Alias for channel 8 WRITE_ADDR register
+            CH8_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 8 TRANS_COUNT register
+            CH8_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 8 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH8_AL3_READ_ADDR_TRIG: u32,
+            ///  DMA Channel 9 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH9_READ_ADDR: u32,
+            ///  DMA Channel 9 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH9_WRITE_ADDR: u32,
+            ///  DMA Channel 9 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH9_TRANS_COUNT: u32,
+            ///  DMA Channel 9 Control and Status
+            CH9_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 9 CTRL register
+            CH9_AL1_CTRL: u32,
+            ///  Alias for channel 9 READ_ADDR register
+            CH9_AL1_READ_ADDR: u32,
+            ///  Alias for channel 9 WRITE_ADDR register
+            CH9_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 9 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH9_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 9 CTRL register
+            CH9_AL2_CTRL: u32,
+            ///  Alias for channel 9 TRANS_COUNT register
+            CH9_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 9 READ_ADDR register
+            CH9_AL2_READ_ADDR: u32,
+            ///  Alias for channel 9 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH9_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 9 CTRL register
+            CH9_AL3_CTRL: u32,
+            ///  Alias for channel 9 WRITE_ADDR register
+            CH9_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 9 TRANS_COUNT register
+            CH9_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 9 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH9_AL3_READ_ADDR_TRIG: u32,
+            ///  DMA Channel 10 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH10_READ_ADDR: u32,
+            ///  DMA Channel 10 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH10_WRITE_ADDR: u32,
+            ///  DMA Channel 10 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH10_TRANS_COUNT: u32,
+            ///  DMA Channel 10 Control and Status
+            CH10_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 10 CTRL register
+            CH10_AL1_CTRL: u32,
+            ///  Alias for channel 10 READ_ADDR register
+            CH10_AL1_READ_ADDR: u32,
+            ///  Alias for channel 10 WRITE_ADDR register
+            CH10_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 10 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH10_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 10 CTRL register
+            CH10_AL2_CTRL: u32,
+            ///  Alias for channel 10 TRANS_COUNT register
+            CH10_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 10 READ_ADDR register
+            CH10_AL2_READ_ADDR: u32,
+            ///  Alias for channel 10 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH10_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 10 CTRL register
+            CH10_AL3_CTRL: u32,
+            ///  Alias for channel 10 WRITE_ADDR register
+            CH10_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 10 TRANS_COUNT register
+            CH10_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 10 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH10_AL3_READ_ADDR_TRIG: u32,
+            ///  DMA Channel 11 Read Address pointer
+            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
+            CH11_READ_ADDR: u32,
+            ///  DMA Channel 11 Write Address pointer
+            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
+            CH11_WRITE_ADDR: u32,
+            ///  DMA Channel 11 Transfer Count
+            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
+            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
+            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
+            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
+            CH11_TRANS_COUNT: u32,
+            ///  DMA Channel 11 Control and Status
+            CH11_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
+                ///  DMA Channel Enable.
+                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
+                EN: u1,
+                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
+                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
+                HIGH_PRIORITY: u1,
+                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
+                DATA_SIZE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        SIZE_BYTE = 0x0,
+                        SIZE_HALFWORD = 0x1,
+                        SIZE_WORD = 0x2,
+                        _,
+                    },
+                },
+                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
+                ///  Generally this should be disabled for peripheral-to-memory transfers.
+                INCR_READ: u1,
+                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
+                ///  Generally this should be disabled for memory-to-peripheral transfers.
+                INCR_WRITE: u1,
+                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
+                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
+                RING_SIZE: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        RING_NONE = 0x0,
+                        _,
+                    },
+                },
+                ///  Select whether RING_SIZE applies to read or write addresses.
+                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
+                RING_SEL: u1,
+                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
+                CHAIN_TO: u4,
+                ///  Select a Transfer Request signal.
+                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
+                ///  0x0 to 0x3a -> select DREQ n as TREQ
+                TREQ_SEL: packed union {
+                    raw: u6,
+                    value: enum(u6) {
+                        ///  Select Timer 0 as TREQ
+                        TIMER0 = 0x3b,
+                        ///  Select Timer 1 as TREQ
+                        TIMER1 = 0x3c,
+                        ///  Select Timer 2 as TREQ (Optional)
+                        TIMER2 = 0x3d,
+                        ///  Select Timer 3 as TREQ (Optional)
+                        TIMER3 = 0x3e,
+                        ///  Permanent request, for unpaced transfers.
+                        PERMANENT = 0x3f,
+                        _,
+                    },
+                },
+                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
+                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
+                IRQ_QUIET: u1,
+                ///  Apply byte-swap transformation to DMA data.
+                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
+                BSWAP: u1,
+                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
+                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
+                SNIFF_EN: u1,
+                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
+                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
+                BUSY: u1,
+                reserved29: u4,
+                ///  If 1, the channel received a write bus error. Write one to clear.
+                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
+                WRITE_ERROR: u1,
+                ///  If 1, the channel received a read bus error. Write one to clear.
+                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
+                READ_ERROR: u1,
+                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
+                AHB_ERROR: u1,
+            }),
+            ///  Alias for channel 11 CTRL register
+            CH11_AL1_CTRL: u32,
+            ///  Alias for channel 11 READ_ADDR register
+            CH11_AL1_READ_ADDR: u32,
+            ///  Alias for channel 11 WRITE_ADDR register
+            CH11_AL1_WRITE_ADDR: u32,
+            ///  Alias for channel 11 TRANS_COUNT register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH11_AL1_TRANS_COUNT_TRIG: u32,
+            ///  Alias for channel 11 CTRL register
+            CH11_AL2_CTRL: u32,
+            ///  Alias for channel 11 TRANS_COUNT register
+            CH11_AL2_TRANS_COUNT: u32,
+            ///  Alias for channel 11 READ_ADDR register
+            CH11_AL2_READ_ADDR: u32,
+            ///  Alias for channel 11 WRITE_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH11_AL2_WRITE_ADDR_TRIG: u32,
+            ///  Alias for channel 11 CTRL register
+            CH11_AL3_CTRL: u32,
+            ///  Alias for channel 11 WRITE_ADDR register
+            CH11_AL3_WRITE_ADDR: u32,
+            ///  Alias for channel 11 TRANS_COUNT register
+            CH11_AL3_TRANS_COUNT: u32,
+            ///  Alias for channel 11 READ_ADDR register
+            ///  This is a trigger register (0xc). Writing a nonzero value will
+            ///  reload the channel counter and start the channel.
+            CH11_AL3_READ_ADDR_TRIG: u32,
+            reserved1024: [256]u8,
+            ///  Interrupt Status (raw)
+            INTR: mmio.Mmio(packed struct(u32) {
+                ///  Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.
+                ///  Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.
+                ///  This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.
+                ///  It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.
+                INTR: u16,
+                padding: u16,
+            }),
+            ///  Interrupt Enables for IRQ 0
+            INTE0: mmio.Mmio(packed struct(u32) {
+                ///  Set bit n to pass interrupts from channel n to DMA IRQ 0.
+                INTE0: u16,
+                padding: u16,
+            }),
+            ///  Force Interrupts
+            INTF0: mmio.Mmio(packed struct(u32) {
+                ///  Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.
+                INTF0: u16,
+                padding: u16,
+            }),
+            ///  Interrupt Status for IRQ 0
+            INTS0: mmio.Mmio(packed struct(u32) {
+                ///  Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.
+                ///  Channel interrupts can be cleared by writing a bit mask here.
+                INTS0: u16,
+                padding: u16,
+            }),
+            reserved1044: [4]u8,
+            ///  Interrupt Enables for IRQ 1
+            INTE1: mmio.Mmio(packed struct(u32) {
+                ///  Set bit n to pass interrupts from channel n to DMA IRQ 1.
+                INTE1: u16,
+                padding: u16,
+            }),
+            ///  Force Interrupts for IRQ 1
+            INTF1: mmio.Mmio(packed struct(u32) {
+                ///  Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.
+                INTF1: u16,
+                padding: u16,
+            }),
+            ///  Interrupt Status (masked) for IRQ 1
+            INTS1: mmio.Mmio(packed struct(u32) {
+                ///  Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.
+                ///  Channel interrupts can be cleared by writing a bit mask here.
+                INTS1: u16,
+                padding: u16,
+            }),
+            ///  Pacing (X/Y) Fractional Timer
+            ///  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
+            TIMER0: mmio.Mmio(packed struct(u32) {
+                ///  Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
+                Y: u16,
+                ///  Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
+                X: u16,
+            }),
+            ///  Pacing (X/Y) Fractional Timer
+            ///  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
+            TIMER1: mmio.Mmio(packed struct(u32) {
+                ///  Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
+                Y: u16,
+                ///  Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
+                X: u16,
+            }),
+            ///  Pacing (X/Y) Fractional Timer
+            ///  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
+            TIMER2: mmio.Mmio(packed struct(u32) {
+                ///  Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
+                Y: u16,
+                ///  Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
+                X: u16,
+            }),
+            ///  Pacing (X/Y) Fractional Timer
+            ///  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
+            TIMER3: mmio.Mmio(packed struct(u32) {
+                ///  Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
+                Y: u16,
+                ///  Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
+                X: u16,
+            }),
+            ///  Trigger one or more channels simultaneously
+            MULTI_CHAN_TRIGGER: mmio.Mmio(packed struct(u32) {
+                ///  Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy.
+                MULTI_CHAN_TRIGGER: u16,
+                padding: u16,
+            }),
+            ///  Sniffer Control
+            SNIFF_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Enable sniffer
+                EN: u1,
+                ///  DMA channel for Sniffer to observe
+                DMACH: u4,
+                CALC: packed union {
+                    raw: u4,
+                    value: enum(u4) {
+                        ///  Calculate a CRC-32 (IEEE802.3 polynomial)
+                        CRC32 = 0x0,
+                        ///  Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data
+                        CRC32R = 0x1,
+                        ///  Calculate a CRC-16-CCITT
+                        CRC16 = 0x2,
+                        ///  Calculate a CRC-16-CCITT with bit reversed data
+                        CRC16R = 0x3,
+                        ///  XOR reduction over all data. == 1 if the total 1 population count is odd.
+                        EVEN = 0xe,
+                        ///  Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)
+                        SUM = 0xf,
+                        _,
+                    },
+                },
+                ///  Locally perform a byte reverse on the sniffed data, before feeding into checksum.
+                ///  Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view.
+                BSWAP: u1,
+                ///  If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.
+                OUT_REV: u1,
+                ///  If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.
+                OUT_INV: u1,
+                padding: u20,
+            }),
+            ///  Data accumulator for sniff hardware
+            ///  Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.
+            SNIFF_DATA: u32,
+            reserved1088: [4]u8,
+            ///  Debug RAF, WAF, TDF levels
+            FIFO_LEVELS: mmio.Mmio(packed struct(u32) {
+                ///  Current Transfer-Data-FIFO fill level
+                TDF_LVL: u8,
+                ///  Current Write-Address-FIFO fill level
+                WAF_LVL: u8,
+                ///  Current Read-Address-FIFO fill level
+                RAF_LVL: u8,
+                padding: u8,
+            }),
+            ///  Abort an in-progress transfer sequence on one or more channels
+            CHAN_ABORT: mmio.Mmio(packed struct(u32) {
+                ///  Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.
+                ///  After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.
+                CHAN_ABORT: u16,
+                padding: u16,
+            }),
+            ///  The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.
+            N_CHANNELS: mmio.Mmio(packed struct(u32) {
+                N_CHANNELS: u5,
+                padding: u27,
+            }),
+            reserved2048: [948]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH0_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH0_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH0_DBG_TCR: u32,
+            reserved2112: [56]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH1_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH1_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH1_DBG_TCR: u32,
+            reserved2176: [56]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH2_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH2_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH2_DBG_TCR: u32,
+            reserved2240: [56]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH3_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH3_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH3_DBG_TCR: u32,
+            reserved2304: [56]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH4_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH4_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH4_DBG_TCR: u32,
+            reserved2368: [56]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH5_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH5_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH5_DBG_TCR: u32,
+            reserved2432: [56]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH6_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH6_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH6_DBG_TCR: u32,
+            reserved2496: [56]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH7_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH7_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH7_DBG_TCR: u32,
+            reserved2560: [56]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH8_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH8_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH8_DBG_TCR: u32,
+            reserved2624: [56]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH9_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH9_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH9_DBG_TCR: u32,
+            reserved2688: [56]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH10_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH10_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH10_DBG_TCR: u32,
+            reserved2752: [56]u8,
+            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
+            CH11_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
+                CH11_DBG_CTDREQ: u6,
+                padding: u26,
+            }),
+            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
+            CH11_DBG_TCR: u32,
+        };
+
+        ///  DPRAM layout for USB device.
+        pub const USBCTRL_DPRAM = extern struct {
+            ///  Bytes 0-3 of the SETUP packet from the host.
+            SETUP_PACKET_LOW: mmio.Mmio(packed struct(u32) {
+                BMREQUESTTYPE: u8,
+                BREQUEST: u8,
+                WVALUE: u16,
+            }),
+            ///  Bytes 4-7 of the setup packet from the host.
+            SETUP_PACKET_HIGH: mmio.Mmio(packed struct(u32) {
+                WINDEX: u16,
+                WLENGTH: u16,
+            }),
+            EP1_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP1_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP2_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP2_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP3_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP3_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP4_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP4_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP5_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP5_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP6_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP6_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP7_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP7_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP8_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP8_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP9_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP9_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP10_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP10_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP11_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP11_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP12_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP12_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP13_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP13_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP14_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP14_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP15_IN_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            EP15_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
+                BUFFER_ADDRESS: u16,
+                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
+                INTERRUPT_ON_NAK: u1,
+                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
+                INTERRUPT_ON_STALL: u1,
+                reserved26: u8,
+                ENDPOINT_TYPE: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        Control = 0x0,
+                        Isochronous = 0x1,
+                        Bulk = 0x2,
+                        Interrupt = 0x3,
+                    },
+                },
+                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
+                INTERRUPT_PER_DOUBLE_BUFF: u1,
+                ///  Trigger an interrupt each time a buffer is done.
+                INTERRUPT_PER_BUFF: u1,
+                ///  This endpoint is double buffered.
+                DOUBLE_BUFFERED: u1,
+                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
+                ENABLE: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP0_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP0_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP1_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP1_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP2_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP2_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP3_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP3_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP4_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP4_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP5_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP5_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP6_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP6_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP7_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP7_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP8_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP8_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP9_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP9_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP10_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP10_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP11_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP11_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP12_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP12_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP13_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP13_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP14_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP14_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP15_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
+            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
+            EP15_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  The length of the data in buffer 0.
+                LENGTH_0: u10,
+                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_0: u1,
+                ///  Reply with a stall (valid for both buffers).
+                STALL: u1,
+                ///  Reset the buffer selector to buffer 0.
+                RESET: u1,
+                ///  The data pid of buffer 0.
+                PID_0: u1,
+                ///  Buffer 0 is the last buffer of the transfer.
+                LAST_0: u1,
+                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_0: u1,
+                ///  The length of the data in buffer 1.
+                LENGTH_1: u10,
+                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
+                AVAILABLE_1: u1,
+                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
+                ///  For a non Isochronous endpoint the offset is always 64 bytes.
+                DOUBLE_BUFFER_ISO_OFFSET: packed union {
+                    raw: u2,
+                    value: enum(u2) {
+                        @"128" = 0x0,
+                        @"256" = 0x1,
+                        @"512" = 0x2,
+                        @"1024" = 0x3,
+                    },
+                },
+                ///  The data pid of buffer 1.
+                PID_1: u1,
+                ///  Buffer 1 is the last buffer of the transfer.
+                LAST_1: u1,
+                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
+                FULL_1: u1,
+            }),
+        };
+    };
+};
diff --git a/src/hal.zig b/src/hal.zig
index 06c0cdd9d..21323dedd 100644
--- a/src/hal.zig
+++ b/src/hal.zig
@@ -28,6 +28,6 @@ pub fn init() void {
     clock_config.apply();
 }
 
-pub fn getCpuId() u32 {
+pub fn get_cpu_id() u32 {
     return regs.SIO.CPUID.*;
 }
diff --git a/src/hal/adc.zig b/src/hal/adc.zig
index 3cf29fab0..1746ccc87 100644
--- a/src/hal/adc.zig
+++ b/src/hal/adc.zig
@@ -4,28 +4,28 @@ const std = @import("std");
 const assert = std.debug.assert;
 
 const microzig = @import("microzig");
-const ADC = microzig.chip.registers.ADC;
+const ADC = microzig.chip.peripherals.ADC;
 const rp2040 = microzig.hal;
 const gpio = rp2040.gpio;
 const resets = rp2040.resets;
 
 pub const temperature_sensor = struct {
     pub inline fn init() void {
-        setTempSensorEnabled(true);
+        set_temp_sensor_enabled(true);
     }
 
     pub inline fn deinit() void {
-        setTempSensorEnabled(false);
+        set_temp_sensor_enabled(false);
     }
 
-    pub inline fn readRaw() u16 {
+    pub inline fn read_raw() u16 {
         return Input.read(.temperature_sensor);
     }
 
     // One-shot conversion returning the temperature in Celcius
     pub inline fn read(comptime T: type, comptime Vref: T) T {
         // TODO: consider fixed-point
-        const raw = @intToFloat(T, readRaw());
+        const raw = @intToFloat(T, read_raw());
         const voltage: T = Vref * raw / 0x0fff;
         return (27.0 - ((voltage - 0.706) / 0.001721));
     }
@@ -41,11 +41,11 @@ pub const Input = enum(u3) {
     /// Setup the GPIO pin as an ADC input
     pub fn init(comptime input: Input) void {
         switch (input) {
-            .temperature_sensor => setTempSensorEnabled(true),
+            .temperature_sensor => set_temp_sensor_enabled(true),
             else => {
                 const gpio_num = @as(u32, @enumToInt(input)) + 26;
 
-                gpio.setFunction(gpio_num, .@"null");
+                gpio.set_function(gpio_num, .null);
                 // TODO: implement these, otherwise adc isn't going to work.
                 //gpio.disablePulls(gpio_num);
                 //gpio.setInputEnabled(gpio_num, false);
@@ -57,7 +57,7 @@ pub const Input = enum(u3) {
     /// one of the others.
     pub inline fn deinit(input: Input) void {
         switch (input) {
-            .temperature_sensor => setTempSensorEnabled(true),
+            .temperature_sensor => set_temp_sensor_enabled(true),
             else => {},
         }
     }
@@ -74,7 +74,7 @@ pub const Input = enum(u3) {
         // wait for the
         while (ADC.CS.read().READY == 0) {}
 
-        return ADC.RESULT.read();
+        return ADC.RESULT.read().RESULT;
     }
 };
 
@@ -116,42 +116,47 @@ pub fn init() void {
         .ERR_STICKY = 0,
         .AINSEL = 0,
         .RROBIN = 0,
+
+        .reserved8 = 0,
+        .reserved12 = 0,
+        .reserved16 = 0,
+        .padding = 0,
     });
     while (ADC.CS.read().READY == 0) {}
 }
 
 /// Enable/disable ADC interrupt
-pub inline fn irqSetEnabled(enable: bool) void {
+pub inline fn irq_set_enabled(enable: bool) void {
     // TODO: check if this works
     ADC.INTE.write(.{ .FIFO = if (enable) @as(u1, 1) else @as(u1, 0) });
 }
 
 /// Select analog input for next conversion.
-pub inline fn selectInput(input: Input) void {
+pub inline fn select_input(input: Input) void {
     ADC.CS.modify(.{ .AINSEL = @enumToInt(input) });
 }
 
 /// Get the currently selected analog input. 0..3 are GPIO 26..29 respectively,
 /// 4 is the temperature sensor.
-pub inline fn getSelectedInput() Input {
+pub inline fn get_selected_input() Input {
     // TODO: ensure that the field shouldn't have other values
     return @intToEnum(Input, ADC.CS.read().AINSEL);
 }
 
 /// Set to true to power on the temperature sensor.
-pub inline fn setTempSensorEnabled(enable: bool) void {
+pub inline fn set_temp_sensor_enabled(enable: bool) void {
     ADC.CS.modify(.{ .TS_EN = if (enable) @as(u1, 1) else @as(u1, 0) });
 }
 
 /// Sets which of the inputs are to be run in round-robin mode. Setting all to
 /// 0 will disable round-robin mode but `disableRoundRobin()` is provided so
 /// the user may be explicit.
-pub inline fn setRoundRobin(comptime enabled_inputs: InputMask) void {
+pub inline fn set_round_robin(comptime enabled_inputs: InputMask) void {
     ADC.CS.modify(.{ .RROBIN = @bitCast(u5, enabled_inputs) });
 }
 
 /// Disable round-robin sample mode.
-pub inline fn disableRoundRobin() void {
+pub inline fn disable_round_robin() void {
     ADC.CS.modify(.{ .RROBIN = 0 });
 }
 
@@ -160,7 +165,7 @@ pub inline fn run(enable: bool) void {
     ADC.CS.modify(.{ .START_MANY = if (enable) @as(u1, 1) else @as(u1, 0) });
 }
 
-pub inline fn setClkDiv() void {
+pub inline fn set_clk_div() void {
     @compileError("todo");
 }
 
@@ -173,12 +178,12 @@ pub const fifo = struct {
     }
 
     /// Return true if FIFO is empty.
-    pub inline fn isEmpty() bool {
+    pub inline fn is_empty() bool {
         @compileError("todo");
     }
 
     /// Read how many samples are in the FIFO.
-    pub inline fn getLevel() u8 {
+    pub inline fn get_level() u8 {
         @compileError("todo");
     }
 
@@ -188,7 +193,7 @@ pub const fifo = struct {
     }
 
     /// Block until result is available in FIFO, then pop it.
-    pub inline fn getBlocking() u16 {
+    pub inline fn get_blocking() u16 {
         @compileError("todo");
     }
 
diff --git a/src/hal/clocks.zig b/src/hal/clocks.zig
index e703db46a..4a4980964 100644
--- a/src/hal/clocks.zig
+++ b/src/hal/clocks.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("microzig");
+
 const pll = @import("pll.zig");
 const util = @import("util.zig");
 const assert = std.debug.assert;
@@ -7,8 +7,11 @@ const assert = std.debug.assert;
 // TODO: remove
 const gpio = @import("gpio.zig");
 
-const regs = microzig.chip.registers;
-const CLOCKS = regs.CLOCKS;
+const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+const CLOCKS = peripherals.CLOCKS;
+const WATCHDOG = peripherals.WATCHDOG;
+const XOSC = peripherals.XOSC;
 const xosc_freq = microzig.board.xosc_freq;
 /// this is only nominal, very imprecise and prone to drift over time
 const rosc_freq = 6_500_000;
@@ -22,25 +25,25 @@ pub const xosc = struct {
     const startup_delay_value = xosc_freq * startup_delay_ms / 1000 / 256;
 
     pub fn init() void {
-        regs.XOSC.STARTUP.modify(.{ .DELAY = startup_delay_value });
-        regs.XOSC.CTRL.modify(.{ .ENABLE = 4011 });
+        XOSC.STARTUP.modify(.{ .DELAY = startup_delay_value });
+        XOSC.CTRL.modify(.{ .ENABLE = .{ .value = .ENABLE } });
 
         // wait for xosc startup to complete:
-        while (regs.XOSC.STATUS.read().STABLE == 0) {}
+        while (XOSC.STATUS.read().STABLE == 0) {}
     }
 
-    pub fn waitCycles(value: u8) void {
+    pub fn wait_cycles(value: u8) void {
         assert(is_enabled: {
-            const status = regs.XOSC.STATUS.read();
+            const status = XOSC.STATUS.read();
             break :is_enabled status.STABLE != 0 and status.ENABLED != 0;
         });
 
-        regs.XOSC.COUNT.modify(value);
-        while (regs.XOSC.COUNT.read() != 0) {}
+        XOSC.COUNT.modify(value);
+        while (XOSC.COUNT.read() != 0) {}
     }
 };
 
-fn formatUppercase(
+fn format_uppercase(
     bytes: []const u8,
     comptime fmt: []const u8,
     options: std.fmt.FormatOptions,
@@ -52,7 +55,7 @@ fn formatUppercase(
         try writer.writeByte(std.ascii.toUpper(c));
 }
 
-fn uppercase(bytes: []const u8) std.fmt.Formatter(formatUppercase) {
+fn uppercase(bytes: []const u8) std.fmt.Formatter(format_uppercase) {
     return .{ .data = bytes };
 }
 
@@ -81,16 +84,13 @@ pub const Generator = enum(u32) {
         assert(24 == @sizeOf([2]GeneratorRegs));
     }
 
-    const generators = @intToPtr(
-        *volatile [@typeInfo(Generator).Enum.fields.len]GeneratorRegs,
-        regs.CLOCKS.base_address,
-    );
+    const generators = @ptrCast(*volatile [@typeInfo(Generator).Enum.fields.len]GeneratorRegs, CLOCKS);
 
-    fn getRegs(generator: Generator) *volatile GeneratorRegs {
+    fn get_regs(generator: Generator) *volatile GeneratorRegs {
         return &generators[@enumToInt(generator)];
     }
 
-    pub fn hasGlitchlessMux(generator: Generator) bool {
+    pub fn has_glitchless_mux(generator: Generator) bool {
         return switch (generator) {
             .sys, .ref => true,
             else => false,
@@ -100,22 +100,22 @@ pub const Generator = enum(u32) {
     pub fn enable(generator: Generator) void {
         switch (generator) {
             .ref, .sys => {},
-            else => generator.getRegs().ctrl |= (1 << 11),
+            else => generator.get_regs().ctrl |= (1 << 11),
         }
     }
 
-    pub fn setDiv(generator: Generator, div: u32) void {
+    pub fn set_div(generator: Generator, div: u32) void {
         if (generator == .peri)
             return;
 
-        generator.getRegs().div = div;
+        generator.get_regs().div = div;
     }
 
-    pub fn getDiv(generator: Generator) u32 {
+    pub fn get_div(generator: Generator) u32 {
         if (generator == .peri)
             return 1;
 
-        return generator.getRegs().div;
+        return generator.get_regs().div;
     }
 
     // The bitfields for the *_SELECTED registers are actually a mask of which
@@ -125,21 +125,21 @@ pub const Generator = enum(u32) {
     //
     // Some mention that this is only for the glitchless mux, so if it is non-glitchless then return true
     pub fn selected(generator: Generator) bool {
-        return (0 != generator.getRegs().selected);
+        return (0 != generator.get_regs().selected);
     }
 
-    pub fn clearSource(generator: Generator) void {
-        generator.getRegs().ctrl &= ~@as(u32, 0x3);
+    pub fn clear_source(generator: Generator) void {
+        generator.get_regs().ctrl &= ~@as(u32, 0x3);
     }
 
     pub fn disable(generator: Generator) void {
         switch (generator) {
             .sys, .ref => {},
-            else => generator.getRegs().ctrl &= ~@as(u32, 1 << 11),
+            else => generator.get_regs().ctrl &= ~@as(u32, 1 << 11),
         }
     }
 
-    pub fn isAuxSource(generator: Generator, source: Source) bool {
+    pub fn is_aux_source(generator: Generator, source: Source) bool {
         return switch (generator) {
             .sys => switch (source) {
                 .clk_ref => false,
@@ -153,16 +153,16 @@ pub const Generator = enum(u32) {
         };
     }
 
-    pub fn setSource(generator: Generator, src: u32) void {
-        std.debug.assert(generator.hasGlitchlessMux());
-        const gen_regs = generator.getRegs();
+    pub fn set_source(generator: Generator, src: u32) void {
+        std.debug.assert(generator.has_glitchless_mux());
+        const gen_regs = generator.get_regs();
         const mask = ~@as(u32, 0x3);
         const ctrl_value = gen_regs.ctrl;
         gen_regs.ctrl = (ctrl_value & mask) | src;
     }
 
-    pub fn setAuxSource(generator: Generator, auxsrc: u32) void {
-        const gen_regs = generator.getRegs();
+    pub fn set_aux_source(generator: Generator, auxsrc: u32) void {
+        const gen_regs = generator.get_regs();
         const mask = ~@as(u32, 0x1e0);
         const ctrl_value = gen_regs.ctrl;
         gen_regs.ctrl = (ctrl_value & mask) | (auxsrc << 5);
@@ -183,7 +183,7 @@ pub const Source = enum {
     clk_rtc,
 };
 
-fn srcValue(generator: Generator, source: Source) u32 {
+fn src_value(generator: Generator, source: Source) u32 {
     return switch (generator) {
         .sys => src: {
             const ret: u32 = switch (source) {
@@ -204,7 +204,7 @@ fn srcValue(generator: Generator, source: Source) u32 {
     };
 }
 
-fn auxSrcValue(generator: Generator, source: Source) u32 {
+fn aux_src_value(generator: Generator, source: Source) u32 {
     return switch (generator) {
         .sys => auxsrc: {
             const ret: u32 = switch (source) {
@@ -308,7 +308,7 @@ pub const GlobalConfiguration = struct {
         // TODO: allow user to configure PLLs to optimize for low-jitter, low-power, or manually specify
     };
 
-    pub fn getFrequency(config: GlobalConfiguration, source: Source) ?u32 {
+    pub fn get_frequency(config: GlobalConfiguration, source: Source) ?u32 {
         return switch (source) {
             .src_xosc => xosc_freq,
             .src_rosc => rosc_freq,
@@ -337,11 +337,11 @@ pub const GlobalConfiguration = struct {
                 .generator = .ref,
                 .input = .{
                     .source = ref_opts.source,
-                    .freq = config.getFrequency(ref_opts.source).?,
-                    .src_value = srcValue(.ref, ref_opts.source),
-                    .auxsrc_value = auxSrcValue(.ref, ref_opts.source),
+                    .freq = config.get_frequency(ref_opts.source).?,
+                    .src_value = src_value(.ref, ref_opts.source),
+                    .auxsrc_value = aux_src_value(.ref, ref_opts.source),
                 },
-                .output_freq = config.getFrequency(ref_opts.source).?,
+                .output_freq = config.get_frequency(ref_opts.source).?,
             };
         } else if (config.pll_sys != null or config.pll_usb != null) ref_config: {
             config.xosc_configured = true;
@@ -350,8 +350,8 @@ pub const GlobalConfiguration = struct {
                 .input = .{
                     .source = .src_xosc,
                     .freq = xosc_freq,
-                    .src_value = srcValue(.ref, .src_xosc),
-                    .auxsrc_value = auxSrcValue(.ref, .src_xosc),
+                    .src_value = src_value(.ref, .src_xosc),
+                    .auxsrc_value = aux_src_value(.ref, .src_xosc),
                 },
                 .output_freq = xosc_freq,
             };
@@ -369,8 +369,8 @@ pub const GlobalConfiguration = struct {
                         break :input .{
                             .source = .src_rosc,
                             .freq = rosc_freq,
-                            .src_value = srcValue(.sys, .src_rosc),
-                            .auxsrc_value = auxSrcValue(.sys, .src_rosc),
+                            .src_value = src_value(.sys, .src_rosc),
+                            .auxsrc_value = aux_src_value(.sys, .src_rosc),
                         };
                     },
                     .src_xosc => input: {
@@ -380,8 +380,8 @@ pub const GlobalConfiguration = struct {
                         break :input .{
                             .source = .src_xosc,
                             .freq = xosc_freq,
-                            .src_value = srcValue(.sys, .src_xosc),
-                            .auxsrc_value = auxSrcValue(.sys, .src_xosc),
+                            .src_value = src_value(.sys, .src_xosc),
+                            .auxsrc_value = aux_src_value(.sys, .src_xosc),
                         };
                     },
                     .pll_sys => input: {
@@ -402,8 +402,8 @@ pub const GlobalConfiguration = struct {
                             // TODO: not really sure what frequency to
                             // drive pll at yet, but this is an okay start
                             .freq = 125_000_000,
-                            .src_value = srcValue(.sys, .pll_sys),
-                            .auxsrc_value = auxSrcValue(.sys, .pll_sys),
+                            .src_value = src_value(.sys, .pll_sys),
+                            .auxsrc_value = aux_src_value(.sys, .pll_sys),
                         };
                     },
 
@@ -433,8 +433,8 @@ pub const GlobalConfiguration = struct {
                 .input = .{
                     .source = .pll_usb,
                     .freq = 48_000_000,
-                    .src_value = srcValue(.usb, .pll_usb),
-                    .auxsrc_value = auxSrcValue(.usb, .pll_usb),
+                    .src_value = src_value(.usb, .pll_usb),
+                    .auxsrc_value = aux_src_value(.usb, .pll_usb),
                 },
                 .output_freq = 48_000_000,
             };
@@ -470,8 +470,8 @@ pub const GlobalConfiguration = struct {
                 .input = .{
                     .source = .pll_usb,
                     .freq = 48_000_000,
-                    .src_value = srcValue(.adc, .pll_usb),
-                    .auxsrc_value = auxSrcValue(.adc, .pll_usb),
+                    .src_value = src_value(.adc, .pll_usb),
+                    .auxsrc_value = aux_src_value(.adc, .pll_usb),
                 },
                 .output_freq = 48_000_000,
             };
@@ -501,8 +501,8 @@ pub const GlobalConfiguration = struct {
                 .input = .{
                     .source = .pll_usb,
                     .freq = 48_000_000,
-                    .src_value = srcValue(.rtc, .pll_usb),
-                    .auxsrc_value = auxSrcValue(.rtc, .pll_usb),
+                    .src_value = src_value(.rtc, .pll_usb),
+                    .auxsrc_value = aux_src_value(.rtc, .pll_usb),
                 },
                 .output_freq = 48_000_000,
             };
@@ -516,15 +516,15 @@ pub const GlobalConfiguration = struct {
                 .generator = .peri,
                 .input = .{
                     .source = peri_opts.source,
-                    .freq = config.getFrequency(peri_opts.source) orelse
+                    .freq = config.get_frequency(peri_opts.source) orelse
                         @compileError("you need to configure the source: " ++ @tagName(peri_opts.source)),
-                    .src_value = srcValue(.peri, peri_opts.source),
-                    .auxsrc_value = auxSrcValue(.peri, peri_opts.source),
+                    .src_value = src_value(.peri, peri_opts.source),
+                    .auxsrc_value = aux_src_value(.peri, peri_opts.source),
                 },
                 .output_freq = if (peri_opts.freq) |output_freq|
                     output_freq
                 else
-                    config.getFrequency(peri_opts.source).?,
+                    config.get_frequency(peri_opts.source).?,
             };
         } else null;
 
@@ -532,15 +532,15 @@ pub const GlobalConfiguration = struct {
             .generator = .gpout0,
             .input = .{
                 .source = gpout0_opts.source,
-                .freq = config.getFrequency(gpout0_opts.source) orelse
+                .freq = config.get_frequency(gpout0_opts.source) orelse
                     @compileError("you need to configure the source: " ++ @tagName(gpout0_opts.source)),
-                .src_value = srcValue(.gpout0, gpout0_opts.source),
-                .auxsrc_value = auxSrcValue(.gpout0, gpout0_opts.source),
+                .src_value = src_value(.gpout0, gpout0_opts.source),
+                .auxsrc_value = aux_src_value(.gpout0, gpout0_opts.source),
             },
             .output_freq = if (gpout0_opts.freq) |output_freq|
                 output_freq
             else
-                config.getFrequency(gpout0_opts.source).?,
+                config.get_frequency(gpout0_opts.source).?,
         } else null;
 
         return config;
@@ -551,10 +551,10 @@ pub const GlobalConfiguration = struct {
     pub fn apply(comptime config: GlobalConfiguration) void {
 
         // disable resus if it has been turned on elsewhere
-        regs.CLOCKS.CLK_SYS_RESUS_CTRL.raw = 0;
+        CLOCKS.CLK_SYS_RESUS_CTRL.raw = 0;
 
         if (config.xosc_configured) {
-            regs.WATCHDOG.TICK.modify(.{
+            WATCHDOG.TICK.modify(.{
                 .CYCLES = xosc_freq / 1_000_000,
                 .ENABLE = 1,
             });
@@ -565,7 +565,7 @@ pub const GlobalConfiguration = struct {
         // configured to use/be used from PLLs
         if (config.sys) |sys| switch (sys.input.source) {
             .pll_usb, .pll_sys => {
-                regs.CLOCKS.CLK_SYS_CTRL.modify(.{ .SRC = 0 });
+                CLOCKS.CLK_SYS_CTRL.modify(.{ .SRC = .{ .raw = 0 } });
                 while (!Generator.sys.selected()) {}
             },
             else => {},
@@ -573,7 +573,7 @@ pub const GlobalConfiguration = struct {
 
         if (config.ref) |ref| switch (ref.input.source) {
             .pll_usb, .pll_sys => {
-                regs.CLOCKS.CLK_REF_CTRL.modify(.{ .SRC = 0 });
+                CLOCKS.CLK_REF_CTRL.modify(.{ .SRC = .{ .raw = 0 } });
                 while (!Generator.ref.selected()) {}
             },
             else => {},
@@ -621,11 +621,11 @@ pub const Configuration = struct {
         const div = @intCast(u32, (@intCast(u64, input.freq) << 8) / output_freq);
 
         // check divisor
-        if (div > generator.getDiv())
-            generator.setDiv(div);
+        if (div > generator.get_div())
+            generator.set_div(div);
 
-        if (generator.hasGlitchlessMux() and input.src_value == 1) {
-            generator.clearSource();
+        if (generator.has_glitchless_mux() and input.src_value == 1) {
+            generator.clear_source();
 
             while (!generator.selected()) {}
         } else {
@@ -643,21 +643,21 @@ pub const Configuration = struct {
             );
         }
 
-        generator.setAuxSource(input.auxsrc_value);
+        generator.set_aux_source(input.auxsrc_value);
 
         // set aux mux first and then glitchless mex if this clock has one
-        if (generator.hasGlitchlessMux()) {
-            generator.setSource(input.src_value);
+        if (generator.has_glitchless_mux()) {
+            generator.set_source(input.src_value);
             while (!generator.selected()) {}
         }
 
         generator.enable();
-        generator.setDiv(div);
+        generator.set_div(div);
     }
 };
 
 // NOTE: untested
-pub fn countFrequencyKhz(source: Source, comptime clock_config: GlobalConfiguration) u32 {
+pub fn count_frequency_khz(source: Source, comptime clock_config: GlobalConfiguration) u32 {
     const ref_freq = clock_config.ref.?.output_freq;
 
     // wait for counter to be done
diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig
index e725d79fa..1e333b148 100644
--- a/src/hal/gpio.zig
+++ b/src/hal/gpio.zig
@@ -1,8 +1,13 @@
 const std = @import("std");
+const assert = std.debug.assert;
+
 const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+const SIO = peripherals.SIO;
+const PADS_BANK0 = peripherals.PADS_BANK0;
+const IO_BANK0 = peripherals.IO_BANK0;
+
 const resets = @import("resets.zig");
-const regs = microzig.chip.registers;
-const assert = std.debug.assert;
 
 const log = std.log.scoped(.gpio);
 
@@ -17,7 +22,7 @@ pub const Function = enum(u5) {
     pio1,
     gpck,
     usb,
-    @"null" = 0x1f,
+    null = 0x1f,
 };
 
 pub const Direction = enum(u1) {
@@ -65,14 +70,14 @@ pub inline fn reset() void {
 /// Initialize a GPIO, set func to SIO
 pub inline fn init(comptime gpio: u32) void {
     const mask = 1 << gpio;
-    regs.SIO.GPIO_OE_CLR.raw = mask;
-    regs.SIO.GPIO_OUT_CLR.raw = mask;
-    setFunction(gpio, .sio);
+    SIO.GPIO_OE_CLR.raw = mask;
+    SIO.GPIO_OUT_CLR.raw = mask;
+    set_function(gpio, .sio);
 }
 
 /// Reset GPIO back to null function (disables it)
 pub inline fn deinit(comptime gpio: u32) void {
-    setFunction(gpio, .@"null");
+    set_function(gpio, .null);
 }
 
 pub const PullUpDown = enum {
@@ -80,9 +85,9 @@ pub const PullUpDown = enum {
     down,
 };
 
-pub inline fn setPullUpDown(comptime gpio: u32, mode: ?PullUpDown) void {
+pub inline fn set_pull(comptime gpio: u32, mode: ?PullUpDown) void {
     const gpio_name = comptime std.fmt.comptimePrint("GPIO{d}", .{gpio});
-    const gpio_regs = @field(regs.PADS_BANK0, gpio_name);
+    const gpio_regs = @field(PADS_BANK0, gpio_name);
 
     if (mode == null) {
         gpio_regs.modify(.{ .PUE = 0, .PDE = 0 });
@@ -92,11 +97,11 @@ pub inline fn setPullUpDown(comptime gpio: u32, mode: ?PullUpDown) void {
     }
 }
 
-pub inline fn setDir(comptime gpio: u32, direction: Direction) void {
+pub inline fn set_direction(comptime gpio: u32, direction: Direction) void {
     const mask = 1 << gpio;
     switch (direction) {
-        .in => regs.SIO.GPIO_OE_CLR.raw = mask,
-        .out => regs.SIO.GPIO_OE_SET.raw = mask,
+        .in => SIO.GPIO_OE_CLR.raw = mask,
+        .out => SIO.GPIO_OE_SET.raw = mask,
     }
 }
 
@@ -105,37 +110,43 @@ pub inline fn put(comptime gpio: u32, value: u1) void {
     std.log.debug("GPIO{} put: {}", .{ gpio, value });
     const mask = 1 << gpio;
     switch (value) {
-        0 => regs.SIO.GPIO_OUT_CLR.raw = mask,
-        1 => regs.SIO.GPIO_OUT_SET.raw = mask,
+        0 => SIO.GPIO_OUT_CLR.raw = mask,
+        1 => SIO.GPIO_OUT_SET.raw = mask,
     }
 }
 
 pub inline fn toggle(comptime gpio: u32) void {
-    regs.SIO.GPIO_OUT_XOR.raw = (1 << gpio);
+    SIO.GPIO_OUT_XOR.raw = (1 << gpio);
 }
 
 pub inline fn read(comptime gpio: u32) u1 {
     const mask = 1 << gpio;
-    return if ((regs.SIO.GPIO_IN.raw & mask) != 0)
+    return if ((SIO.GPIO_IN.raw & mask) != 0)
         1
     else
         0;
 }
 
-pub inline fn setFunction(comptime gpio: u32, function: Function) void {
+pub inline fn set_function(comptime gpio: u32, function: Function) void {
     const pad_bank_reg = comptime std.fmt.comptimePrint("GPIO{}", .{gpio});
-    @field(regs.PADS_BANK0, pad_bank_reg).modify(.{
+    @field(PADS_BANK0, pad_bank_reg).modify(.{
         .IE = 1,
         .OD = 0,
     });
 
     const io_bank_reg = comptime std.fmt.comptimePrint("GPIO{}_CTRL", .{gpio});
-    @field(regs.IO_BANK0, io_bank_reg).write(.{
-        .FUNCSEL = @enumToInt(function),
-        .OUTOVER = 0,
-        .INOVER = 0,
-        .IRQOVER = 0,
-        .OEOVER = 0,
+    @field(IO_BANK0, io_bank_reg).write(.{
+        .FUNCSEL = .{ .raw = @enumToInt(function) },
+        .OUTOVER = .{ .value = .NORMAL },
+        .INOVER = .{ .value = .NORMAL },
+        .IRQOVER = .{ .value = .NORMAL },
+        .OEOVER = .{ .value = .NORMAL },
+
+        .reserved8 = 0,
+        .reserved12 = 0,
+        .reserved16 = 0,
+        .reserved28 = 0,
+        .padding = 0,
     });
 }
 
diff --git a/src/hal/irq.zig b/src/hal/irq.zig
index 7d57c7854..f3502be5b 100644
--- a/src/hal/irq.zig
+++ b/src/hal/irq.zig
@@ -3,18 +3,18 @@ const regs = microzig.chip.registers;
 
 // TODO: the register definitions are improved now, use them instead of raw
 // writes/reads
-fn getInterruptMask(comptime interrupt_name: []const u8) u32 {
+fn get_interrupt_mask(comptime interrupt_name: []const u8) u32 {
     const offset = @offsetOf(microzig.chip.VectorTable, interrupt_name);
 
     return (1 << ((offset / 4) - 16));
 }
 pub fn enable(comptime interrupt_name: []const u8) void {
-    const mask = comptime getInterruptMask(interrupt_name);
+    const mask = comptime get_interrupt_mask(interrupt_name);
     regs.SCS.NVIC.ICPR.raw = mask;
     regs.SCS.NVIC.ISER.raw = mask;
 }
 
 pub fn disable(comptime interrupt_name: []const u8) void {
-    const mask = comptime getInterruptMask(interrupt_name);
+    const mask = comptime get_interrupt_mask(interrupt_name);
     regs.SCS.NVIC.ICER.raw = mask;
 }
diff --git a/src/hal/multicore.zig b/src/hal/multicore.zig
index f1bcfe08c..e3199d9af 100644
--- a/src/hal/multicore.zig
+++ b/src/hal/multicore.zig
@@ -1,25 +1,29 @@
 const std = @import("std");
-const microzig = @import("microzig");
-const regs = microzig.chip.registers;
 const assert = std.debug.assert;
 
+const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+const SIO = peripherals.SIO;
+const PSM = peripherals.PSM;
+const SCB = peripherals.SCB;
+
 pub const fifo = struct {
     /// Check if the FIFO has valid data for reading.
-    pub fn isReadReady() bool {
-        return regs.SIO.FIFO_ST.read().VLD == 1;
+    pub fn is_read_ready() bool {
+        return SIO.FIFO_ST.read().VLD == 1;
     }
 
     /// Read from the FIFO
     /// Will return null if it is empty.
     pub fn read() ?u32 {
-        if (!isReadReady())
+        if (!is_read_ready())
             return null;
 
-        return regs.SIO.FIFO_RD.*;
+        return SIO.FIFO_RD;
     }
 
     /// Read from the FIFO, waiting for data if there is none.
-    pub fn readBloacking() u32 {
+    pub fn read_blocking() u32 {
         while (true) {
             if (read()) |value| return value;
             microzig.cpu.wfe();
@@ -32,20 +36,20 @@ pub const fifo = struct {
     }
 
     /// Check if the FIFO is ready to receive data.
-    pub fn isWriteReady() bool {
-        return regs.SIO.FIFO_ST.read().RDY == 1;
+    pub fn is_write_ready() bool {
+        return SIO.FIFO_ST.read().RDY == 1;
     }
 
     /// Write to the FIFO
     /// You must check if there is space by calling is_write_ready
     pub fn write(value: u32) void {
-        regs.SIO.FIFO_WR.* = value;
+        SIO.FIFO_WR = value;
         microzig.cpu.sev();
     }
 
     /// Write to the FIFO, waiting for room if it is full.
-    pub fn writeBlocking(value: u32) void {
-        while (!isWriteReady())
+    pub fn write_blocking(value: u32) void {
+        while (!is_write_ready())
             std.mem.doNotOptimizeAway(value);
 
         write(value);
@@ -55,11 +59,11 @@ pub const fifo = struct {
 var core1_stack: [128]u32 = undefined;
 
 /// Runs `entrypoint` on the second core.
-pub fn launchCore1(entrypoint: *const fn () void) void {
-    launchCore1WithStack(entrypoint, &core1_stack);
+pub fn launch_core1(entrypoint: *const fn () void) void {
+    launch_core1_with_stack(entrypoint, &core1_stack);
 }
 
-pub fn launchCore1WithStack(entrypoint: *const fn () void, stack: []u32) void {
+pub fn launch_core1_with_stack(entrypoint: *const fn () void, stack: []u32) void {
     // TODO: disable SIO interrupts
 
     const wrapper = &struct {
@@ -71,9 +75,9 @@ pub fn launchCore1WithStack(entrypoint: *const fn () void, stack: []u32) void {
     }.wrapper;
 
     // reset the second core
-    regs.PSM.FRCE_OFF.modify(.{ .proc1 = 1 });
-    while (regs.PSM.FRCE_OFF.read().proc1 != 1) microzig.cpu.nop();
-    regs.PSM.FRCE_OFF.modify(.{ .proc1 = 0 });
+    PSM.FRCE_OFF.modify(.{ .proc1 = 1 });
+    while (PSM.FRCE_OFF.read().proc1 != 1) microzig.cpu.nop();
+    PSM.FRCE_OFF.modify(.{ .proc1 = 0 });
 
     stack[stack.len - 2] = @ptrToInt(entrypoint);
     stack[stack.len - 1] = @ptrToInt(stack.ptr);
@@ -88,7 +92,7 @@ pub fn launchCore1WithStack(entrypoint: *const fn () void, stack: []u32) void {
         0,
         0,
         1,
-        regs.SCS.SCB.VTOR.raw,
+        SCB.VTOR.raw,
         stack_ptr,
         @ptrToInt(wrapper),
     };
@@ -102,8 +106,8 @@ pub fn launchCore1WithStack(entrypoint: *const fn () void, stack: []u32) void {
             microzig.cpu.sev();
         }
 
-        fifo.writeBlocking(cmd);
+        fifo.write_blocking(cmd);
         // the second core should respond with the same value, if it doesnt't lets start over
-        seq = if (cmd == fifo.readBloacking()) seq + 1 else 0;
+        seq = if (cmd == fifo.read_blocking()) seq + 1 else 0;
     }
 }
diff --git a/src/hal/pins.zig b/src/hal/pins.zig
index dce1c2418..24b9d7af6 100644
--- a/src/hal/pins.zig
+++ b/src/hal/pins.zig
@@ -1,13 +1,15 @@
 const std = @import("std");
+const assert = std.debug.assert;
+const comptimePrint = std.fmt.comptimePrint;
+const StructField = std.builtin.Type.StructField;
+
+const microzig = @import("microzig");
+const SIO = microzig.chip.peripherals.SIO;
+
 const gpio = @import("gpio.zig");
 const pwm = @import("pwm.zig");
 const adc = @import("adc.zig");
 const resets = @import("resets.zig");
-const regs = @import("microzig").chip.registers;
-
-const assert = std.debug.assert;
-const comptimePrint = std.fmt.comptimePrint;
-const StructField = std.builtin.Type.StructField;
 
 pub const Pin = enum {
     GPIO0,
@@ -52,16 +54,16 @@ pub const Pin = enum {
         // schmitt trigger
         // hysteresis
 
-        pub fn getDirection(comptime config: Configuration) gpio.Direction {
+        pub fn get_direction(comptime config: Configuration) gpio.Direction {
             return if (config.direction) |direction|
                 direction
-            else if (comptime config.function.isPwm())
+            else if (comptime config.function.is_pwm())
                 .out
-            else if (comptime config.function.isUartTx())
+            else if (comptime config.function.is_uart_tx())
                 .out
-            else if (comptime config.function.isUartRx())
+            else if (comptime config.function.is_uart_rx())
                 .in
-            else if (comptime config.function.isAdc())
+            else if (comptime config.function.is_adc())
                 .in
             else
                 @panic("TODO");
@@ -142,7 +144,7 @@ pub const Function = enum {
     ADC2,
     ADC3,
 
-    pub fn isPwm(function: Function) bool {
+    pub fn is_pwm(function: Function) bool {
         return switch (function) {
             .PWM0_A,
             .PWM0_B,
@@ -165,7 +167,7 @@ pub const Function = enum {
         };
     }
 
-    pub fn isUartTx(function: Function) bool {
+    pub fn is_uart_tx(function: Function) bool {
         return switch (function) {
             .UART0_TX,
             .UART1_TX,
@@ -174,7 +176,7 @@ pub const Function = enum {
         };
     }
 
-    pub fn isUartRx(function: Function) bool {
+    pub fn is_uart_rx(function: Function) bool {
         return switch (function) {
             .UART0_RX,
             .UART1_RX,
@@ -183,7 +185,7 @@ pub const Function = enum {
         };
     }
 
-    pub fn pwmSlice(comptime function: Function) u32 {
+    pub fn pwm_slice(comptime function: Function) u32 {
         return switch (function) {
             .PWM0_A, .PWM0_B => 0,
             .PWM1_A, .PWM1_B => 1,
@@ -197,7 +199,7 @@ pub const Function = enum {
         };
     }
 
-    pub fn isAdc(function: Function) bool {
+    pub fn is_adc(function: Function) bool {
         return switch (function) {
             .ADC0,
             .ADC1,
@@ -208,7 +210,7 @@ pub const Function = enum {
         };
     }
 
-    pub fn pwmChannel(comptime function: Function) pwm.Channel {
+    pub fn pwm_channel(comptime function: Function) pwm.Channel {
         return switch (function) {
             .PWM0_A,
             .PWM1_A,
@@ -354,10 +356,10 @@ pub fn Pins(comptime config: GlobalConfiguration) type {
                 if (pin_config.function == .SIO) {
                     pin_field.name = pin_config.name orelse field.name;
                     pin_field.type = GPIO(@enumToInt(@field(Pin, field.name)), pin_config.direction orelse .in);
-                } else if (pin_config.function.isPwm()) {
+                } else if (pin_config.function.is_pwm()) {
                     pin_field.name = pin_config.name orelse @tagName(pin_config.function);
-                    pin_field.type = pwm.PWM(pin_config.function.pwmSlice(), pin_config.function.pwmChannel());
-                } else if (pin_config.function.isAdc()) {
+                    pin_field.type = pwm.Pwm(pin_config.function.pwm_slice(), pin_config.function.pwm_channel());
+                } else if (pin_config.function.is_adc()) {
                     pin_field.name = pin_config.name orelse @tagName(pin_config.function);
                     pin_field.type = adc.Input;
                     pin_field.default_value = @ptrCast(?*const anyopaque, switch (pin_config.function) {
@@ -453,16 +455,16 @@ pub const GlobalConfiguration = struct {
                         @compileError(comptimePrint("{s} cannot be configured for {}", .{ field.name, pin_config.function }));
 
                     if (pin_config.function == .SIO) {
-                        switch (pin_config.getDirection()) {
+                        switch (pin_config.get_direction()) {
                             .in => input_gpios |= 1 << gpio_num,
                             .out => output_gpios |= 1 << gpio_num,
                         }
                     }
 
-                    if (pin_config.function.isAdc()) {
+                    if (pin_config.function.is_adc()) {
                         has_adc = true;
                     }
-                    if (pin_config.function.isPwm()) {
+                    if (pin_config.function.is_pwm()) {
                         has_pwm = true;
                     }
                 };
@@ -474,8 +476,8 @@ pub const GlobalConfiguration = struct {
         gpio.reset();
 
         if (used_gpios != 0) {
-            regs.SIO.GPIO_OE_CLR.raw = used_gpios;
-            regs.SIO.GPIO_OUT_CLR.raw = used_gpios;
+            SIO.GPIO_OE_CLR.raw = used_gpios;
+            SIO.GPIO_OUT_CLR.raw = used_gpios;
         }
 
         inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| {
@@ -494,13 +496,13 @@ pub const GlobalConfiguration = struct {
                 // @"null" = 0x1f,
 
                 if (func == .SIO) {
-                    gpio.setFunction(gpio_num, .sio);
-                } else if (comptime func.isPwm()) {
-                    gpio.setFunction(gpio_num, .pwm);
-                } else if (comptime func.isAdc()) {
-                    gpio.setFunction(gpio_num, .null);
+                    gpio.set_function(gpio_num, .sio);
+                } else if (comptime func.is_pwm()) {
+                    gpio.set_function(gpio_num, .pwm);
+                } else if (comptime func.is_adc()) {
+                    gpio.set_function(gpio_num, .null);
                 } else if (comptime func.isUartTx() or func.isUartRx()) {
-                    gpio.setFunction(gpio_num, .uart);
+                    gpio.set_function(gpio_num, .uart);
                 } else {
                     @compileError(std.fmt.comptimePrint("Unimplemented pin function. Please implement setting pin function {s} for GPIO {}", .{
                         @tagName(func),
@@ -511,7 +513,7 @@ pub const GlobalConfiguration = struct {
         }
 
         if (output_gpios != 0)
-            regs.SIO.GPIO_OE_SET.raw = output_gpios;
+            SIO.GPIO_OE_SET.raw = output_gpios;
 
         if (input_gpios != 0) {
             inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field|
@@ -521,7 +523,7 @@ pub const GlobalConfiguration = struct {
                     if (comptime pin_config.getDirection() != .in)
                         @compileError("Only input pins can have pull up/down enabled");
 
-                    gpio.setPullUpDown(gpio_num, pull);
+                    gpio.set_pull(gpio_num, pull);
                 };
         }
 
diff --git a/src/hal/pll.zig b/src/hal/pll.zig
index 117a42c14..62fd9ecd7 100644
--- a/src/hal/pll.zig
+++ b/src/hal/pll.zig
@@ -1,12 +1,12 @@
 const std = @import("std");
-const microzig = @import("microzig");
 const assert = std.debug.assert;
 
-// TODO: remove
-const gpio = @import("gpio.zig");
-
-const regs = microzig.chip.registers;
+const microzig = @import("microzig");
 const xosc_freq = microzig.board.xosc_freq;
+const peripherals = microzig.chip.peripherals;
+const RESETS = peripherals.RESETS;
+
+const PllRegs = microzig.chip.types.peripherals.PLL_SYS;
 
 pub const Configuration = struct {
     refdiv: u6,
@@ -23,28 +23,31 @@ pub const PLL = enum {
     sys,
     usb,
 
-    fn getRegs(pll: PLL) *volatile PllRegs {
-        return &plls[@enumToInt(pll)];
+    fn get_regs(pll: PLL) *volatile PllRegs {
+        return switch (pll) {
+            .sys => peripherals.PLL_SYS,
+            .usb => peripherals.PLL_USB,
+        };
     }
 
     pub fn reset(pll: PLL) void {
         switch (pll) {
             .sys => {
-                regs.RESETS.RESET.modify(.{ .pll_sys = 1 });
-                regs.RESETS.RESET.modify(.{ .pll_sys = 0 });
-                while (regs.RESETS.RESET_DONE.read().pll_sys != 1) {}
+                RESETS.RESET.modify(.{ .pll_sys = 1 });
+                RESETS.RESET.modify(.{ .pll_sys = 0 });
+                while (RESETS.RESET_DONE.read().pll_sys != 1) {}
             },
             .usb => {
-                regs.RESETS.RESET.modify(.{ .pll_usb = 1 });
-                regs.RESETS.RESET.modify(.{ .pll_usb = 0 });
-                while (regs.RESETS.RESET_DONE.read().pll_usb != 1) {}
+                RESETS.RESET.modify(.{ .pll_usb = 1 });
+                RESETS.RESET.modify(.{ .pll_usb = 0 });
+                while (RESETS.RESET_DONE.read().pll_usb != 1) {}
             },
         }
     }
 
-    pub fn isLocked(pll: PLL) bool {
-        const pll_regs = pll.getRegs();
-        return pll_regs.cs.read().LOCK == 1;
+    pub fn is_locked(pll: PLL) bool {
+        const pll_regs = pll.get_regs();
+        return pll_regs.CS.read().LOCK == 1;
     }
 
     pub fn apply(pll: PLL, comptime config: Configuration) void {
@@ -53,7 +56,7 @@ pub const PLL = enum {
         assert(config.postdiv2 >= 1 and config.postdiv2 <= 7);
         assert(config.postdiv2 <= config.postdiv1);
 
-        const pll_regs = pll.getRegs();
+        const pll_regs = pll.get_regs();
         const ref_freq = xosc_freq / @as(u32, config.refdiv);
         const vco_freq = ref_freq * config.fbdiv;
         assert(ref_freq <= vco_freq / 16);
@@ -65,11 +68,11 @@ pub const PLL = enum {
         // 5. set up post dividers and turn them on
 
         // do not bother a PLL which is already configured
-        if (pll.isLocked() and
-            config.refdiv == pll_regs.cs.read().REFDIV and
-            config.fbdiv == pll_regs.fbdiv_int.read() and
-            config.postdiv1 == pll_regs.prim.read().POSTDIV1 and
-            config.postdiv2 == pll_regs.prim.read().POSTDIV2)
+        if (pll.is_locked() and
+            config.refdiv == pll_regs.CS.read().REFDIV and
+            config.fbdiv == pll_regs.FBDIV_INT.read().FBDIV_INT and
+            config.postdiv1 == pll_regs.PRIM.read().POSTDIV1 and
+            config.postdiv2 == pll_regs.PRIM.read().POSTDIV2)
         {
             return;
         }
@@ -77,39 +80,20 @@ pub const PLL = enum {
         pll.reset();
 
         // load vco related dividers
-        pll_regs.cs.modify(.{ .REFDIV = config.refdiv });
-        pll_regs.fbdiv_int.modify(config.fbdiv);
+        pll_regs.CS.modify(.{ .REFDIV = config.refdiv });
+        pll_regs.FBDIV_INT.modify(.{ .FBDIV_INT = config.fbdiv });
 
         // turn on PLL
-        pll_regs.pwr.modify(.{ .PD = 0, .VCOPD = 0 });
+        pll_regs.PWR.modify(.{ .PD = 0, .VCOPD = 0 });
 
         // wait for PLL to lock
-        while (!pll.isLocked()) {}
+        while (!pll.is_locked()) {}
 
-        pll_regs.prim.modify(.{
+        pll_regs.PRIM.modify(.{
             .POSTDIV1 = config.postdiv1,
             .POSTDIV2 = config.postdiv2,
         });
 
-        pll_regs.pwr.modify(.{ .POSTDIVPD = 0 });
+        pll_regs.PWR.modify(.{ .POSTDIVPD = 0 });
     }
 };
-
-const plls = @intToPtr(*volatile [2]PllRegs, regs.PLL_SYS.base_address);
-comptime {
-    assert(@sizeOf(PllRegs) == (regs.PLL_USB.base_address - regs.PLL_SYS.base_address));
-}
-
-const CsReg = @typeInfo(@TypeOf(regs.PLL_SYS.CS)).Pointer.child;
-const PwrReg = @typeInfo(@TypeOf(regs.PLL_SYS.PWR)).Pointer.child;
-const FbdivIntReg = @typeInfo(@TypeOf(regs.PLL_SYS.FBDIV_INT)).Pointer.child;
-const PrimReg = @typeInfo(@TypeOf(regs.PLL_SYS.PRIM)).Pointer.child;
-
-pub const PllRegs = extern struct {
-    cs: CsReg,
-    pwr: PwrReg,
-    fbdiv_int: FbdivIntReg,
-    prim: PrimReg,
-
-    padding: [4092]u32,
-};
diff --git a/src/hal/pwm.zig b/src/hal/pwm.zig
index 8d2857300..7277b11e0 100644
--- a/src/hal/pwm.zig
+++ b/src/hal/pwm.zig
@@ -1,24 +1,25 @@
 const std = @import("std");
 const microzig = @import("microzig");
-const regs = microzig.chip.registers;
+const PWM = microzig.chip.peripherals.PWM;
 
 const log = std.log.scoped(.pwm);
 
 pub const Config = struct {};
 
-fn getRegs(comptime slice: u32) *volatile Regs {
+fn get_regs(comptime slice: u32) *volatile Regs {
     @import("std").debug.assert(slice < 8);
-    const reg_diff = comptime (@ptrToInt(regs.PWM.CH1_CSR) - @ptrToInt(regs.PWM.CH0_CSR));
-    return @intToPtr(*volatile Regs, regs.PWM.base_address + reg_diff * slice);
+    const PwmType = microzig.chip.types.peripherals.PWM;
+    const reg_diff = comptime @offsetOf(PwmType, "CH1_CSR") - @offsetOf(PwmType, "CH0_CSR");
+    return @intToPtr(*volatile Regs, @ptrToInt(PWM) + reg_diff * slice);
 }
 
-pub fn PWM(comptime slice_num: u32, comptime chan: Channel) type {
+pub fn Pwm(comptime slice_num: u32, comptime chan: Channel) type {
     return struct {
         pub const slice_number = slice_num;
         pub const channel = chan;
 
-        pub inline fn setLevel(_: @This(), level: u16) void {
-            setChannelLevel(slice_number, channel, level);
+        pub inline fn set_level(_: @This(), level: u16) void {
+            set_channel_level(slice_number, channel, level);
         }
 
         pub fn slice(_: @This()) Slice(slice_number) {
@@ -31,24 +32,24 @@ pub fn Slice(comptime slice_num: u32) type {
     return struct {
         const slice_number = slice_num;
 
-        pub inline fn setWrap(_: @This(), wrap: u16) void {
-            setSliceWrap(slice_number, wrap);
+        pub inline fn set_wrap(_: @This(), wrap: u16) void {
+            set_slice_wrap(slice_number, wrap);
         }
 
         pub inline fn enable(_: @This()) void {
-            getRegs(slice_number).csr.modify(.{ .EN = 1 });
+            get_regs(slice_number).csr.modify(.{ .EN = 1 });
         }
 
         pub inline fn disable(_: @This()) void {
-            getRegs(slice_number).csr.modify(.{ .EN = 0 });
+            get_regs(slice_number).csr.modify(.{ .EN = 0 });
         }
 
-        pub inline fn setPhaseCorrect(_: @This(), phase_correct: bool) void {
-            setSlicePhaseCorrect(slice_number, phase_correct);
+        pub inline fn set_phase_correct(_: @This(), phase_correct: bool) void {
+            set_slice_phase_correct(slice_number, phase_correct);
         }
 
-        pub inline fn setClkDiv(_: @This(), integer: u8, fraction: u4) void {
-            setSliceClkDiv(slice_number, integer, fraction);
+        pub inline fn set_clk_div(_: @This(), integer: u8, fraction: u4) void {
+            set_slice_clk_div(slice_number, integer, fraction);
         }
     };
 }
@@ -63,63 +64,63 @@ pub const ClkDivMode = enum(u2) {
 pub const Channel = enum(u1) { a, b };
 
 const Regs = extern struct {
-    csr: @typeInfo(@TypeOf(regs.PWM.CH0_CSR)).Pointer.child,
-    div: @typeInfo(@TypeOf(regs.PWM.CH0_DIV)).Pointer.child,
-    ctr: @typeInfo(@TypeOf(regs.PWM.CH0_CTR)).Pointer.child,
-    cc: @typeInfo(@TypeOf(regs.PWM.CH0_CC)).Pointer.child,
-    top: @typeInfo(@TypeOf(regs.PWM.CH0_TOP)).Pointer.child,
+    csr: @TypeOf(PWM.CH0_CSR),
+    div: @TypeOf(PWM.CH0_DIV),
+    ctr: @TypeOf(PWM.CH0_CTR),
+    cc: @TypeOf(PWM.CH0_CC),
+    top: @TypeOf(PWM.CH0_TOP),
 };
 
-pub inline fn setSlicePhaseCorrect(comptime slice: u32, phase_correct: bool) void {
+pub inline fn set_slice_phase_correct(comptime slice: u32, phase_correct: bool) void {
     log.debug("PWM{} set phase correct: {}", .{ slice, phase_correct });
-    getRegs(slice).csr.modify(.{
+    get_regs(slice).csr.modify(.{
         .PH_CORRECT = @boolToInt(phase_correct),
     });
 }
 
-pub inline fn setSliceClkDiv(comptime slice: u32, integer: u8, fraction: u4) void {
+pub inline fn set_slice_clk_div(comptime slice: u32, integer: u8, fraction: u4) void {
     log.debug("PWM{} set clk div: {}.{}", .{ slice, integer, fraction });
-    getRegs(slice).div.modify(.{
+    get_regs(slice).div.modify(.{
         .INT = integer,
         .FRAC = fraction,
     });
 }
 
-pub inline fn setSliceClkDivMode(comptime slice: u32, mode: ClkDivMode) void {
+pub inline fn set_slice_clk_div_mode(comptime slice: u32, mode: ClkDivMode) void {
     log.debug("PWM{} set clk div mode: {}", .{ slice, mode });
-    getRegs(slice).csr.modify(.{
+    get_regs(slice).csr.modify(.{
         .DIVMODE = @enumToInt(mode),
     });
 }
 
-pub inline fn setChannelInversion(
+pub inline fn set_channel_inversion(
     comptime slice: u32,
     comptime channel: Channel,
     invert: bool,
 ) void {
     switch (channel) {
-        .a => getRegs(slice).csr.modify(.{
+        .a => get_regs(slice).csr.modify(.{
             .A_INV = @boolToInt(invert),
         }),
-        .b => getRegs(slice).csr.modifi(.{
+        .b => get_regs(slice).csr.modifi(.{
             .B_INV = @boolToInt(invert),
         }),
     }
 }
 
-pub inline fn setSliceWrap(comptime slice: u32, wrap: u16) void {
+pub inline fn set_slice_wrap(comptime slice: u32, wrap: u16) void {
     log.debug("PWM{} set wrap: {}", .{ slice, wrap });
-    getRegs(slice).top.raw = wrap;
+    get_regs(slice).top.raw = wrap;
 }
 
-pub inline fn setChannelLevel(
+pub inline fn set_channel_level(
     comptime slice: u32,
     comptime channel: Channel,
     level: u16,
 ) void {
     log.debug("PWM{} {} set level: {}", .{ slice, channel, level });
     switch (channel) {
-        .a => getRegs(slice).cc.modify(.{ .A = level }),
-        .b => getRegs(slice).cc.modify(.{ .B = level }),
+        .a => get_regs(slice).cc.modify(.{ .A = level }),
+        .b => get_regs(slice).cc.modify(.{ .B = level }),
     }
 }
diff --git a/src/hal/resets.zig b/src/hal/resets.zig
index 45b22305a..218e6b427 100644
--- a/src/hal/resets.zig
+++ b/src/hal/resets.zig
@@ -1,9 +1,9 @@
 const std = @import("std");
-const microzig = @import("microzig");
-
-const regs = microzig.chip.registers;
 const EnumField = std.builtin.Type.EnumField;
-const Mask = @typeInfo(@TypeOf(regs.RESETS.RESET)).Pointer.child.underlying_type;
+
+const microzig = @import("microzig");
+const RESETS = microzig.chip.peripherals.RESETS;
+const Mask = @TypeOf(RESETS.RESET).underlying_type;
 
 pub const Module = enum {
     adc,
@@ -41,8 +41,8 @@ pub inline fn reset(comptime modules: []const Module) void {
 
     const raw_mask = @bitCast(u32, mask);
 
-    regs.RESETS.RESET.raw = raw_mask;
-    regs.RESETS.RESET.raw = 0;
+    RESETS.RESET.raw = raw_mask;
+    RESETS.RESET.raw = 0;
 
-    while ((regs.RESETS.RESET_DONE.raw & raw_mask) != raw_mask) {}
+    while ((RESETS.RESET_DONE.raw & raw_mask) != raw_mask) {}
 }
diff --git a/src/hal/time.zig b/src/hal/time.zig
index 2ed49aeb8..3b568bf5a 100644
--- a/src/hal/time.zig
+++ b/src/hal/time.zig
@@ -1,16 +1,16 @@
 const microzig = @import("microzig");
-const TIMER = microzig.chip.registers.TIMER;
+const TIMER = microzig.chip.peripherals.TIMER;
 
 pub const Absolute = struct {
     us_since_boot: u64,
 };
 
-pub fn getTimeSinceBoot() Absolute {
-    var high_word = TIMER.TIMERAWH.*;
+pub fn get_time_since_boot() Absolute {
+    var high_word = TIMER.TIMERAWH;
 
     return while (true) {
-        var low_word = TIMER.TIMERAWL.*;
-        const next_high_word = TIMER.TIMERAWH.*;
+        var low_word = TIMER.TIMERAWL;
+        const next_high_word = TIMER.TIMERAWH;
         if (next_high_word == high_word)
             break Absolute{
                 .us_since_boot = @intCast(u64, high_word) << 32 | low_word,
@@ -20,24 +20,24 @@ pub fn getTimeSinceBoot() Absolute {
     } else unreachable;
 }
 
-pub fn makeTimeoutUs(timeout_us: u64) Absolute {
+pub fn make_timeout_us(timeout_us: u64) Absolute {
     return Absolute{
-        .us_since_boot = getTimeSinceBoot().us_since_boot + timeout_us,
+        .us_since_boot = get_time_since_boot().us_since_boot + timeout_us,
     };
 }
 
 pub fn reached(time: Absolute) bool {
-    const now = getTimeSinceBoot();
+    const now = get_time_since_boot();
     return now.us_since_boot >= time.us_since_boot;
 }
 
-pub fn sleepMs(time_ms: u32) void {
-    sleepUs(time_ms * 1000);
+pub fn sleep_ms(time_ms: u32) void {
+    sleep_us(time_ms * 1000);
 }
 
-pub fn sleepUs(time_us: u64) void {
+pub fn sleep_us(time_us: u64) void {
     const end_time = Absolute{
-        .us_since_boot = time_us + getTimeSinceBoot().us_since_boot,
+        .us_since_boot = time_us + get_time_since_boot().us_since_boot,
     };
 
     while (!reached(end_time)) {}
diff --git a/src/hal/uart.zig b/src/hal/uart.zig
index d1ca4193d..f4c72c5a6 100644
--- a/src/hal/uart.zig
+++ b/src/hal/uart.zig
@@ -1,12 +1,17 @@
 const std = @import("std");
 const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+const UART0 = peripherals.UART0;
+const UART1 = peripherals.UART1;
+
 const gpio = @import("gpio.zig");
 const clocks = @import("clocks.zig");
 const resets = @import("resets.zig");
 const time = @import("time.zig");
 
 const assert = std.debug.assert;
-const regs = microzig.chip.registers;
+
+const UartRegs = microzig.chip.types.peripherals.UART0;
 
 pub const WordBits = enum {
     five,
@@ -36,40 +41,6 @@ pub const Config = struct {
     parity: Parity = .none,
 };
 
-pub const UartRegs = extern struct {
-    dr: u32,
-    rsr: u32,
-    reserved0: [4]u32,
-    fr: @typeInfo(@TypeOf(regs.UART0.UARTFR)).Pointer.child,
-    reserved1: [1]u32,
-    ilpr: u32,
-    ibrd: u32,
-    fbrd: u32,
-    lcr_h: @typeInfo(@TypeOf(regs.UART0.UARTLCR_H)).Pointer.child,
-    cr: @typeInfo(@TypeOf(regs.UART0.UARTCR)).Pointer.child,
-    ifls: u32,
-    imsc: u32,
-    ris: u32,
-    mis: u32,
-    icr: u32,
-    dmacr: @typeInfo(@TypeOf(regs.UART0.UARTDMACR)).Pointer.child,
-    periphid0: u32,
-    periphid1: u32,
-    periphid2: u32,
-    periphid3: u32,
-    cellid0: u32,
-    cellid1: u32,
-    cellid2: u32,
-    cellid3: u32,
-
-    padding: [4069]u32,
-};
-
-const uarts = @intToPtr(*volatile [2]UartRegs, regs.UART0.base_address);
-comptime {
-    assert(@sizeOf(UartRegs) == (regs.UART1.base_address - regs.UART0.base_address));
-}
-
 pub const UART = enum {
     uart0,
     uart1,
@@ -87,8 +58,11 @@ pub const UART = enum {
         return .{ .context = uart };
     }
 
-    fn getRegs(uart: UART) *volatile UartRegs {
-        return &uarts[@enumToInt(uart)];
+    fn get_regs(uart: UART) *volatile UartRegs {
+        return switch (uart) {
+            .uart0 => UART0,
+            .uart1 => UART1,
+        };
     }
 
     pub fn init(comptime id: u32, comptime config: Config) UART {
@@ -102,66 +76,69 @@ pub const UART = enum {
 
         uart.reset();
 
-        const uart_regs = uart.getRegs();
+        const uart_regs = uart.get_regs();
         const peri_freq = config.clock_config.peri.?.output_freq;
-        uart.setBaudRate(config.baud_rate, peri_freq);
-        uart.setFormat(config.word_bits, config.stop_bits, config.parity);
+        uart.set_baudrate(config.baud_rate, peri_freq);
+        uart.set_format(config.word_bits, config.stop_bits, config.parity);
 
-        uart_regs.cr.modify(.{
+        uart_regs.UARTCR.modify(.{
             .UARTEN = 1,
             .TXE = 1,
             .RXE = 1,
         });
 
-        uart_regs.lcr_h.modify(.{ .FEN = 1 });
+        uart_regs.UARTLCR_H.modify(.{ .FEN = 1 });
 
         // - always enable DREQ signals -- no harm if dma isn't listening
-        uart_regs.dmacr.modify(.{
+        uart_regs.UARTDMACR.modify(.{
             .TXDMAE = 1,
             .RXDMAE = 1,
         });
 
         // TODO comptime assertions
-        if (config.tx_pin) |tx_pin| gpio.setFunction(tx_pin, .uart);
-        if (config.rx_pin) |rx_pin| gpio.setFunction(rx_pin, .uart);
+        if (config.tx_pin) |tx_pin| gpio.set_function(tx_pin, .uart);
+        if (config.rx_pin) |rx_pin| gpio.set_function(rx_pin, .uart);
 
         return uart;
     }
 
-    pub fn isReadable(uart: UART) bool {
-        return (0 == uart.getRegs().fr.read().RXFE);
+    pub fn is_readable(uart: UART) bool {
+        return (0 == uart.get_regs().UARTFR.read().RXFE);
     }
 
-    pub fn isWritable(uart: UART) bool {
-        return (0 == uart.getRegs().fr.read().TXFF);
+    pub fn is_writeable(uart: UART) bool {
+        return (0 == uart.get_regs().UARTFR.read().TXFF);
     }
 
     // TODO: implement tx fifo
     pub fn write(uart: UART, payload: []const u8) WriteError!usize {
-        const uart_regs = uart.getRegs();
+        const uart_regs = uart.get_regs();
         for (payload) |byte| {
-            while (!uart.isWritable()) {}
+            while (!uart.is_writeable()) {}
 
-            uart_regs.dr = byte;
+            uart_regs.UARTDR.raw = byte;
         }
 
         return payload.len;
     }
 
     pub fn read(uart: UART, buffer: []u8) ReadError!usize {
-        const uart_regs = uart.getRegs();
+        const uart_regs = uart.get_regs();
         for (buffer) |*byte| {
-            while (!uart.isReadable()) {}
-            byte.* = @truncate(u8, uart_regs.dr);
+            while (!uart.is_readable()) {}
+
+            // TODO: error checking
+            byte.* = uart_regs.UARTDR.read().DATA;
         }
         return buffer.len;
     }
 
-    pub fn readWord(uart: UART) u8 {
-        const uart_regs = uart.getRegs();
-        while (!uart.isReadable()) {}
+    pub fn read_word(uart: UART) u8 {
+        const uart_regs = uart.get_regs();
+        while (!uart.is_readable()) {}
 
-        return @truncate(u8, uart_regs.dr);
+        // TODO: error checking
+        return uart_regs.UARTDR.read().DATA;
     }
 
     pub fn reset(uart: UART) void {
@@ -171,14 +148,14 @@ pub const UART = enum {
         }
     }
 
-    pub fn setFormat(
+    pub fn set_format(
         uart: UART,
         word_bits: WordBits,
         stop_bits: StopBits,
         parity: Parity,
     ) void {
-        const uart_regs = uart.getRegs();
-        uart_regs.lcr_h.modify(.{
+        const uart_regs = uart.get_regs();
+        uart_regs.UARTLCR_H.modify(.{
             .WLEN = switch (word_bits) {
                 .eight => @as(u2, 0b11),
                 .seven => @as(u2, 0b10),
@@ -200,31 +177,31 @@ pub const UART = enum {
         });
     }
 
-    fn setBaudRate(uart: UART, baud_rate: u32, peri_freq: u32) void {
+    fn set_baudrate(uart: UART, baud_rate: u32, peri_freq: u32) void {
         assert(baud_rate > 0);
-        const uart_regs = uart.getRegs();
+        const uart_regs = uart.get_regs();
         const baud_rate_div = (8 * peri_freq / baud_rate);
-        var baud_ibrd = baud_rate_div >> 7;
+        var baud_ibrd = @intCast(u16, baud_rate_div >> 7);
 
-        const baud_fbrd = if (baud_ibrd == 0) baud_fbrd: {
+        const baud_fbrd: u6 = if (baud_ibrd == 0) baud_fbrd: {
             baud_ibrd = 1;
             break :baud_fbrd 0;
         } else if (baud_ibrd >= 65535) baud_fbrd: {
             baud_ibrd = 65535;
             break :baud_fbrd 0;
-        } else ((baud_rate_div & 0x7f) + 1) / 2;
+        } else @intCast(u6, ((@truncate(u7, baud_rate_div)) + 1) / 2);
 
-        uart_regs.ibrd = baud_ibrd;
-        uart_regs.fbrd = baud_fbrd;
+        uart_regs.UARTIBRD.write(.{ .BAUD_DIVINT = baud_ibrd, .padding = 0 });
+        uart_regs.UARTFBRD.write(.{ .BAUD_DIVFRAC = baud_fbrd, .padding = 0 });
 
         // just want a write, don't want to change these values
-        uart_regs.lcr_h.modify(.{});
+        uart_regs.UARTLCR_H.modify(.{});
     }
 };
 
 var uart_logger: ?UART.Writer = null;
 
-pub fn initLogger(uart: UART) void {
+pub fn init_logger(uart: UART) void {
     uart_logger = uart.writer();
     uart_logger.?.writeAll("\r\n================ STARTING NEW LOGGER ================\r\n") catch {};
 }
@@ -242,7 +219,7 @@ pub fn log(
     };
 
     if (uart_logger) |uart| {
-        const current_time = time.getTimeSinceBoot();
+        const current_time = time.get_time_since_boot();
         const seconds = current_time.us_since_boot / std.time.us_per_s;
         const microseconds = current_time.us_since_boot % std.time.us_per_s;
 
diff --git a/src/hal/util.zig b/src/hal/util.zig
index 9d7863c17..4f0d71c6c 100644
--- a/src/hal/util.zig
+++ b/src/hal/util.zig
@@ -1,18 +1,18 @@
-pub fn xorAlias(ptr: anytype) @TypeOf(ptr) {
+pub fn xor_alias(ptr: anytype) @TypeOf(ptr) {
     const xor_addr = @ptrToInt(ptr) | (1 << 12);
     return @ptrCast(@TypeOf(ptr), xor_addr);
 }
 
-pub fn setAlias(ptr: anytype) @TypeOf(ptr) {
+pub fn set_alias(ptr: anytype) @TypeOf(ptr) {
     const set_addr = @ptrToInt(ptr) | (2 << 12);
     return @ptrCast(@TypeOf(ptr), set_addr);
 }
 
-pub fn clearAlias(ptr: anytype) @TypeOf(ptr) {
+pub fn clear_alias(ptr: anytype) @TypeOf(ptr) {
     const clear_addr = @ptrToInt(ptr) | (3 << 12);
     return @ptrCast(@TypeOf(ptr), clear_addr);
 }
 
-pub inline fn tightLoopContents() void {
+pub inline fn tight_loop_contents() void {
     asm volatile ("" ::: "memory");
 }
diff --git a/src/rp2040.zig b/src/rp2040.zig
deleted file mode 100644
index d3c2e1868..000000000
--- a/src/rp2040.zig
+++ /dev/null
@@ -1,28794 +0,0 @@
-// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz
-// commit: 644b9d6f61ba1e49d90e4f606f82727f3d6581f2
-//
-// vendor: Raspberry Pi
-// device: RP2040
-// cpu: CM0PLUS
-
-pub const VectorTable = extern struct {
-    initial_stack_pointer: u32,
-    Reset: InterruptVector = unhandled,
-    NMI: InterruptVector = unhandled,
-    HardFault: InterruptVector = unhandled,
-    reserved0: [7]u32 = undefined,
-    SVCall: InterruptVector = unhandled,
-    reserved1: [2]u32 = undefined,
-    PendSV: InterruptVector = unhandled,
-    SysTick: InterruptVector = unhandled,
-    TIMER_IRQ_0: InterruptVector = unhandled,
-    TIMER_IRQ_1: InterruptVector = unhandled,
-    TIMER_IRQ_2: InterruptVector = unhandled,
-    TIMER_IRQ_3: InterruptVector = unhandled,
-    PWM_IRQ_WRAP: InterruptVector = unhandled,
-    USBCTRL_IRQ: InterruptVector = unhandled,
-    XIP_IRQ: InterruptVector = unhandled,
-    PIO0_IRQ_0: InterruptVector = unhandled,
-    PIO0_IRQ_1: InterruptVector = unhandled,
-    PIO1_IRQ_0: InterruptVector = unhandled,
-    PIO1_IRQ_1: InterruptVector = unhandled,
-    DMA_IRQ_0: InterruptVector = unhandled,
-    DMA_IRQ_1: InterruptVector = unhandled,
-    IO_IRQ_BANK0: InterruptVector = unhandled,
-    IO_IRQ_QSPI: InterruptVector = unhandled,
-    SIO_IRQ_PROC0: InterruptVector = unhandled,
-    SIO_IRQ_PROC1: InterruptVector = unhandled,
-    CLOCKS_IRQ: InterruptVector = unhandled,
-    SPI0_IRQ: InterruptVector = unhandled,
-    SPI1_IRQ: InterruptVector = unhandled,
-    UART0_IRQ: InterruptVector = unhandled,
-    UART1_IRQ: InterruptVector = unhandled,
-    ADC_IRQ_FIFO: InterruptVector = unhandled,
-    I2C0_IRQ: InterruptVector = unhandled,
-    I2C1_IRQ: InterruptVector = unhandled,
-    RTC_IRQ: InterruptVector = unhandled,
-};
-
-pub const registers = struct {
-    /// System Control Space
-    pub const SCS = struct {
-        pub const base_address = 0xe000e000;
-
-        /// System Tick Timer
-        pub const SysTick = struct {
-            /// address: 0xe000e010
-            /// SysTick Control and Status Register
-            pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-                ENABLE: u1,
-                TICKINT: u1,
-                CLKSOURCE: u1,
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                reserved8: u1 = 0,
-                reserved9: u1 = 0,
-                reserved10: u1 = 0,
-                reserved11: u1 = 0,
-                reserved12: u1 = 0,
-                COUNTFLAG: u1,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-                padding6: u1 = 0,
-                padding7: u1 = 0,
-                padding8: u1 = 0,
-                padding9: u1 = 0,
-                padding10: u1 = 0,
-                padding11: u1 = 0,
-                padding12: u1 = 0,
-                padding13: u1 = 0,
-                padding14: u1 = 0,
-            }), base_address + 0x10);
-
-            /// address: 0xe000e014
-            /// SysTick Reload Value Register
-            pub const LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-                RELOAD: u24,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-                padding6: u1 = 0,
-                padding7: u1 = 0,
-            }), base_address + 0x14);
-
-            /// address: 0xe000e018
-            /// SysTick Current Value Register
-            pub const VAL = @intToPtr(*volatile Mmio(32, packed struct {
-                CURRENT: u24,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-                padding6: u1 = 0,
-                padding7: u1 = 0,
-            }), base_address + 0x18);
-
-            /// address: 0xe000e01c
-            /// SysTick Calibration Register
-            pub const CALIB = @intToPtr(*volatile Mmio(32, packed struct {
-                TENMS: u24,
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                SKEW: u1,
-                NOREF: u1,
-            }), base_address + 0x1c);
-        };
-
-        /// Nested Vectored Interrupt Controller
-        pub const NVIC = struct {
-            /// address: 0xe000e100
-            /// Interrupt Set Enable Register
-            pub const ISER = @intToPtr(*volatile Mmio(32, packed struct {
-                TIMER_IRQ_0: u1,
-                TIMER_IRQ_1: u1,
-                TIMER_IRQ_2: u1,
-                TIMER_IRQ_3: u1,
-                PWM_IRQ_WRAP: u1,
-                USBCTRL_IRQ: u1,
-                XIP_IRQ: u1,
-                PIO0_IRQ_0: u1,
-                PIO0_IRQ_1: u1,
-                PIO1_IRQ_0: u1,
-                PIO1_IRQ_1: u1,
-                DMA_IRQ_0: u1,
-                DMA_IRQ_1: u1,
-                IO_IRQ_BANK0: u1,
-                IO_IRQ_QSPI: u1,
-                SIO_IRQ_PROC0: u1,
-                SIO_IRQ_PROC1: u1,
-                CLOCKS_IRQ: u1,
-                SPI0_IRQ: u1,
-                SPI1_IRQ: u1,
-                UART0_IRQ: u1,
-                UART1_IRQ: u1,
-                ADC_IRQ_FIFO: u1,
-                I2C0_IRQ: u1,
-                I2C1_IRQ: u1,
-                RTC_IRQ: u1,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-            }), base_address + 0x100);
-
-            /// address: 0xe000e180
-            /// Interrupt Clear Enable Register
-            pub const ICER = @intToPtr(*volatile Mmio(32, packed struct {
-                TIMER_IRQ_0: u1,
-                TIMER_IRQ_1: u1,
-                TIMER_IRQ_2: u1,
-                TIMER_IRQ_3: u1,
-                PWM_IRQ_WRAP: u1,
-                USBCTRL_IRQ: u1,
-                XIP_IRQ: u1,
-                PIO0_IRQ_0: u1,
-                PIO0_IRQ_1: u1,
-                PIO1_IRQ_0: u1,
-                PIO1_IRQ_1: u1,
-                DMA_IRQ_0: u1,
-                DMA_IRQ_1: u1,
-                IO_IRQ_BANK0: u1,
-                IO_IRQ_QSPI: u1,
-                SIO_IRQ_PROC0: u1,
-                SIO_IRQ_PROC1: u1,
-                CLOCKS_IRQ: u1,
-                SPI0_IRQ: u1,
-                SPI1_IRQ: u1,
-                UART0_IRQ: u1,
-                UART1_IRQ: u1,
-                ADC_IRQ_FIFO: u1,
-                I2C0_IRQ: u1,
-                I2C1_IRQ: u1,
-                RTC_IRQ: u1,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-            }), base_address + 0x180);
-
-            /// address: 0xe000e200
-            /// Interrupt Set Pending Register
-            pub const ISPR = @intToPtr(*volatile Mmio(32, packed struct {
-                TIMER_IRQ_0: u1,
-                TIMER_IRQ_1: u1,
-                TIMER_IRQ_2: u1,
-                TIMER_IRQ_3: u1,
-                PWM_IRQ_WRAP: u1,
-                USBCTRL_IRQ: u1,
-                XIP_IRQ: u1,
-                PIO0_IRQ_0: u1,
-                PIO0_IRQ_1: u1,
-                PIO1_IRQ_0: u1,
-                PIO1_IRQ_1: u1,
-                DMA_IRQ_0: u1,
-                DMA_IRQ_1: u1,
-                IO_IRQ_BANK0: u1,
-                IO_IRQ_QSPI: u1,
-                SIO_IRQ_PROC0: u1,
-                SIO_IRQ_PROC1: u1,
-                CLOCKS_IRQ: u1,
-                SPI0_IRQ: u1,
-                SPI1_IRQ: u1,
-                UART0_IRQ: u1,
-                UART1_IRQ: u1,
-                ADC_IRQ_FIFO: u1,
-                I2C0_IRQ: u1,
-                I2C1_IRQ: u1,
-                RTC_IRQ: u1,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-            }), base_address + 0x200);
-
-            /// address: 0xe000e280
-            /// Interrupt Clear Pending Register
-            pub const ICPR = @intToPtr(*volatile Mmio(32, packed struct {
-                TIMER_IRQ_0: u1,
-                TIMER_IRQ_1: u1,
-                TIMER_IRQ_2: u1,
-                TIMER_IRQ_3: u1,
-                PWM_IRQ_WRAP: u1,
-                USBCTRL_IRQ: u1,
-                XIP_IRQ: u1,
-                PIO0_IRQ_0: u1,
-                PIO0_IRQ_1: u1,
-                PIO1_IRQ_0: u1,
-                PIO1_IRQ_1: u1,
-                DMA_IRQ_0: u1,
-                DMA_IRQ_1: u1,
-                IO_IRQ_BANK0: u1,
-                IO_IRQ_QSPI: u1,
-                SIO_IRQ_PROC0: u1,
-                SIO_IRQ_PROC1: u1,
-                CLOCKS_IRQ: u1,
-                SPI0_IRQ: u1,
-                SPI1_IRQ: u1,
-                UART0_IRQ: u1,
-                UART1_IRQ: u1,
-                ADC_IRQ_FIFO: u1,
-                I2C0_IRQ: u1,
-                I2C1_IRQ: u1,
-                RTC_IRQ: u1,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-            }), base_address + 0x280);
-
-            /// address: 0xe000e400
-            /// Interrupt Priority Register
-            pub const IP0 = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                TIMER_IRQ_0: u2,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                reserved8: u1 = 0,
-                reserved9: u1 = 0,
-                reserved10: u1 = 0,
-                reserved11: u1 = 0,
-                TIMER_IRQ_1: u2,
-                reserved12: u1 = 0,
-                reserved13: u1 = 0,
-                reserved14: u1 = 0,
-                reserved15: u1 = 0,
-                reserved16: u1 = 0,
-                reserved17: u1 = 0,
-                TIMER_IRQ_2: u2,
-                reserved18: u1 = 0,
-                reserved19: u1 = 0,
-                reserved20: u1 = 0,
-                reserved21: u1 = 0,
-                reserved22: u1 = 0,
-                reserved23: u1 = 0,
-                TIMER_IRQ_3: u2,
-            }), base_address + 0x400);
-
-            /// address: 0xe000e404
-            /// Interrupt Priority Register
-            pub const IP1 = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                PWM_IRQ_WRAP: u2,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                reserved8: u1 = 0,
-                reserved9: u1 = 0,
-                reserved10: u1 = 0,
-                reserved11: u1 = 0,
-                USBCTRL_IRQ: u2,
-                reserved12: u1 = 0,
-                reserved13: u1 = 0,
-                reserved14: u1 = 0,
-                reserved15: u1 = 0,
-                reserved16: u1 = 0,
-                reserved17: u1 = 0,
-                XIP_IRQ: u2,
-                reserved18: u1 = 0,
-                reserved19: u1 = 0,
-                reserved20: u1 = 0,
-                reserved21: u1 = 0,
-                reserved22: u1 = 0,
-                reserved23: u1 = 0,
-                PIO0_IRQ_0: u2,
-            }), base_address + 0x404);
-
-            /// address: 0xe000e408
-            /// Interrupt Priority Register
-            pub const IP2 = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                PIO0_IRQ_1: u2,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                reserved8: u1 = 0,
-                reserved9: u1 = 0,
-                reserved10: u1 = 0,
-                reserved11: u1 = 0,
-                PIO1_IRQ_0: u2,
-                reserved12: u1 = 0,
-                reserved13: u1 = 0,
-                reserved14: u1 = 0,
-                reserved15: u1 = 0,
-                reserved16: u1 = 0,
-                reserved17: u1 = 0,
-                PIO1_IRQ_1: u2,
-                reserved18: u1 = 0,
-                reserved19: u1 = 0,
-                reserved20: u1 = 0,
-                reserved21: u1 = 0,
-                reserved22: u1 = 0,
-                reserved23: u1 = 0,
-                DMA_IRQ_0: u2,
-            }), base_address + 0x408);
-
-            /// address: 0xe000e40c
-            /// Interrupt Priority Register
-            pub const IP3 = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                DMA_IRQ_1: u2,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                reserved8: u1 = 0,
-                reserved9: u1 = 0,
-                reserved10: u1 = 0,
-                reserved11: u1 = 0,
-                IO_IRQ_BANK0: u2,
-                reserved12: u1 = 0,
-                reserved13: u1 = 0,
-                reserved14: u1 = 0,
-                reserved15: u1 = 0,
-                reserved16: u1 = 0,
-                reserved17: u1 = 0,
-                IO_IRQ_QSPI: u2,
-                reserved18: u1 = 0,
-                reserved19: u1 = 0,
-                reserved20: u1 = 0,
-                reserved21: u1 = 0,
-                reserved22: u1 = 0,
-                reserved23: u1 = 0,
-                SIO_IRQ_PROC0: u2,
-            }), base_address + 0x40c);
-
-            /// address: 0xe000e410
-            /// Interrupt Priority Register
-            pub const IP4 = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                SIO_IRQ_PROC1: u2,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                reserved8: u1 = 0,
-                reserved9: u1 = 0,
-                reserved10: u1 = 0,
-                reserved11: u1 = 0,
-                CLOCKS_IRQ: u2,
-                reserved12: u1 = 0,
-                reserved13: u1 = 0,
-                reserved14: u1 = 0,
-                reserved15: u1 = 0,
-                reserved16: u1 = 0,
-                reserved17: u1 = 0,
-                SPI0_IRQ: u2,
-                reserved18: u1 = 0,
-                reserved19: u1 = 0,
-                reserved20: u1 = 0,
-                reserved21: u1 = 0,
-                reserved22: u1 = 0,
-                reserved23: u1 = 0,
-                SPI1_IRQ: u2,
-            }), base_address + 0x410);
-
-            /// address: 0xe000e414
-            /// Interrupt Priority Register
-            pub const IP5 = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                UART0_IRQ: u2,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                reserved8: u1 = 0,
-                reserved9: u1 = 0,
-                reserved10: u1 = 0,
-                reserved11: u1 = 0,
-                UART1_IRQ: u2,
-                reserved12: u1 = 0,
-                reserved13: u1 = 0,
-                reserved14: u1 = 0,
-                reserved15: u1 = 0,
-                reserved16: u1 = 0,
-                reserved17: u1 = 0,
-                ADC_IRQ_FIFO: u2,
-                reserved18: u1 = 0,
-                reserved19: u1 = 0,
-                reserved20: u1 = 0,
-                reserved21: u1 = 0,
-                reserved22: u1 = 0,
-                reserved23: u1 = 0,
-                I2C0_IRQ: u2,
-            }), base_address + 0x414);
-
-            /// address: 0xe000e418
-            /// Interrupt Priority Register
-            pub const IP6 = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                I2C1_IRQ: u2,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                reserved8: u1 = 0,
-                reserved9: u1 = 0,
-                reserved10: u1 = 0,
-                reserved11: u1 = 0,
-                RTC_IRQ: u2,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-                padding6: u1 = 0,
-                padding7: u1 = 0,
-                padding8: u1 = 0,
-                padding9: u1 = 0,
-                padding10: u1 = 0,
-                padding11: u1 = 0,
-                padding12: u1 = 0,
-                padding13: u1 = 0,
-                padding14: u1 = 0,
-                padding15: u1 = 0,
-            }), base_address + 0x418);
-
-            /// address: 0xe000e41c
-            /// Interrupt Priority Register
-            pub const IP7 = @intToPtr(*volatile u32, base_address + 0x41c);
-        };
-
-        /// System Control Block
-        pub const SCB = struct {
-            /// address: 0xe000ed00
-            pub const CPUID = @intToPtr(*volatile Mmio(32, packed struct {
-                REVISION: u4,
-                PARTNO: u12,
-                ARCHITECTURE: u4,
-                VARIANT: u4,
-                IMPLEMENTER: u8,
-            }), base_address + 0xd00);
-
-            /// address: 0xe000ed04
-            /// Interrupt Control and State Register
-            pub const ICSR = @intToPtr(*volatile Mmio(32, packed struct {
-                VECTACTIVE: u9,
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                VECTPENDING: u9,
-                reserved3: u1 = 0,
-                ISRPENDING: u1,
-                ISRPREEMPT: u1,
-                reserved4: u1 = 0,
-                PENDSTCLR: u1,
-                PENDSTSET: u1,
-                PENDSVCLR: u1,
-                PENDSVSET: u1,
-                reserved5: u1 = 0,
-                reserved6: u1 = 0,
-                NMIPENDSET: u1,
-            }), base_address + 0xd04);
-
-            /// address: 0xe000ed0c
-            /// Application Interrupt and Reset Control Register
-            pub const AIRCR = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                VECTCLRACTIVE: u1,
-                SYSRESETREQ: u1,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                reserved8: u1 = 0,
-                reserved9: u1 = 0,
-                reserved10: u1 = 0,
-                reserved11: u1 = 0,
-                reserved12: u1 = 0,
-                ENDIANESS: u1,
-                VECTKEY: u16,
-            }), base_address + 0xd0c);
-
-            /// address: 0xe000ed10
-            /// System Control Register
-            pub const SCR = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                SLEEPONEXIT: u1,
-                SLEEPDEEP: u1,
-                reserved1: u1 = 0,
-                SEVONPEND: u1,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-                padding6: u1 = 0,
-                padding7: u1 = 0,
-                padding8: u1 = 0,
-                padding9: u1 = 0,
-                padding10: u1 = 0,
-                padding11: u1 = 0,
-                padding12: u1 = 0,
-                padding13: u1 = 0,
-                padding14: u1 = 0,
-                padding15: u1 = 0,
-                padding16: u1 = 0,
-                padding17: u1 = 0,
-                padding18: u1 = 0,
-                padding19: u1 = 0,
-                padding20: u1 = 0,
-                padding21: u1 = 0,
-                padding22: u1 = 0,
-                padding23: u1 = 0,
-                padding24: u1 = 0,
-                padding25: u1 = 0,
-                padding26: u1 = 0,
-            }), base_address + 0xd10);
-
-            /// address: 0xe000ed14
-            /// Configuration Control Register
-            pub const CCR = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                UNALIGN_TRP: u1,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                STKALIGN: u1,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-                padding6: u1 = 0,
-                padding7: u1 = 0,
-                padding8: u1 = 0,
-                padding9: u1 = 0,
-                padding10: u1 = 0,
-                padding11: u1 = 0,
-                padding12: u1 = 0,
-                padding13: u1 = 0,
-                padding14: u1 = 0,
-                padding15: u1 = 0,
-                padding16: u1 = 0,
-                padding17: u1 = 0,
-                padding18: u1 = 0,
-                padding19: u1 = 0,
-                padding20: u1 = 0,
-                padding21: u1 = 0,
-            }), base_address + 0xd14);
-
-            /// address: 0xe000ed1c
-            /// System Handlers Priority Registers. [0] is RESERVED
-            pub const SHP = @intToPtr(*volatile u32, base_address + 0xd1c);
-
-            /// address: 0xe000ed24
-            /// System Handler Control and State Register
-            pub const SHCSR = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                reserved8: u1 = 0,
-                reserved9: u1 = 0,
-                reserved10: u1 = 0,
-                reserved11: u1 = 0,
-                reserved12: u1 = 0,
-                reserved13: u1 = 0,
-                reserved14: u1 = 0,
-                SVCALLPENDED: u1,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-                padding6: u1 = 0,
-                padding7: u1 = 0,
-                padding8: u1 = 0,
-                padding9: u1 = 0,
-                padding10: u1 = 0,
-                padding11: u1 = 0,
-                padding12: u1 = 0,
-                padding13: u1 = 0,
-                padding14: u1 = 0,
-                padding15: u1 = 0,
-            }), base_address + 0xd24);
-
-            /// address: 0xe000ed08
-            /// Vector Table Offset Register
-            pub const VTOR = @intToPtr(*volatile Mmio(32, packed struct {
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                reserved6: u1 = 0,
-                reserved7: u1 = 0,
-                TBLOFF: u24,
-            }), base_address + 0xd08);
-        };
-
-        /// Memory Protection Unit
-        pub const MPU = struct {
-            /// address: 0xe000ed90
-            /// MPU Type Register
-            pub const TYPE = @intToPtr(*volatile Mmio(32, packed struct {
-                SEPARATE: u1,
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                reserved4: u1 = 0,
-                reserved5: u1 = 0,
-                reserved6: u1 = 0,
-                DREGION: u8,
-                IREGION: u8,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-                padding6: u1 = 0,
-                padding7: u1 = 0,
-            }), base_address + 0xd90);
-
-            /// address: 0xe000ed94
-            /// MPU Control Register
-            pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-                ENABLE: u1,
-                HFNMIENA: u1,
-                PRIVDEFENA: u1,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-                padding6: u1 = 0,
-                padding7: u1 = 0,
-                padding8: u1 = 0,
-                padding9: u1 = 0,
-                padding10: u1 = 0,
-                padding11: u1 = 0,
-                padding12: u1 = 0,
-                padding13: u1 = 0,
-                padding14: u1 = 0,
-                padding15: u1 = 0,
-                padding16: u1 = 0,
-                padding17: u1 = 0,
-                padding18: u1 = 0,
-                padding19: u1 = 0,
-                padding20: u1 = 0,
-                padding21: u1 = 0,
-                padding22: u1 = 0,
-                padding23: u1 = 0,
-                padding24: u1 = 0,
-                padding25: u1 = 0,
-                padding26: u1 = 0,
-                padding27: u1 = 0,
-                padding28: u1 = 0,
-            }), base_address + 0xd94);
-
-            /// address: 0xe000ed98
-            /// MPU Region RNRber Register
-            pub const RNR = @intToPtr(*volatile Mmio(32, packed struct {
-                REGION: u8,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-                padding3: u1 = 0,
-                padding4: u1 = 0,
-                padding5: u1 = 0,
-                padding6: u1 = 0,
-                padding7: u1 = 0,
-                padding8: u1 = 0,
-                padding9: u1 = 0,
-                padding10: u1 = 0,
-                padding11: u1 = 0,
-                padding12: u1 = 0,
-                padding13: u1 = 0,
-                padding14: u1 = 0,
-                padding15: u1 = 0,
-                padding16: u1 = 0,
-                padding17: u1 = 0,
-                padding18: u1 = 0,
-                padding19: u1 = 0,
-                padding20: u1 = 0,
-                padding21: u1 = 0,
-                padding22: u1 = 0,
-                padding23: u1 = 0,
-            }), base_address + 0xd98);
-
-            /// address: 0xe000ed9c
-            /// MPU Region Base Address Register
-            pub const RBAR = @intToPtr(*volatile Mmio(32, packed struct {
-                REGION: u4,
-                VALID: u1,
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                reserved2: u1 = 0,
-                ADDR: u24,
-            }), base_address + 0xd9c);
-
-            /// address: 0xe000eda0
-            /// MPU Region Attribute and Size Register
-            pub const RASR = @intToPtr(*volatile Mmio(32, packed struct {
-                ENABLE: u1,
-                SIZE: u5,
-                reserved0: u1 = 0,
-                reserved1: u1 = 0,
-                SRD: u8,
-                B: u1,
-                C: u1,
-                S: u1,
-                TEX: u3,
-                reserved2: u1 = 0,
-                reserved3: u1 = 0,
-                AP: u3,
-                reserved4: u1 = 0,
-                XN: u1,
-                padding0: u1 = 0,
-                padding1: u1 = 0,
-                padding2: u1 = 0,
-            }), base_address + 0xda0);
-        };
-    };
-
-    /// QSPI flash execute-in-place block
-    pub const XIP_CTRL = struct {
-        pub const base_address = 0x14000000;
-        pub const version = "1";
-
-        /// address: 0x14000000
-        /// Cache control
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// When 1, enable the cache. When the cache is disabled, all XIP accesses\n
-            /// will go straight to the flash, without querying the cache. When enabled,\n
-            /// cacheable XIP accesses will query the cache, and the flash will\n
-            /// not be accessed if the tag matches and the valid bit is set.\n\n
-            /// If the cache is enabled, cache-as-SRAM accesses have no effect on the\n
-            /// cache data RAM, and will produce a bus error response.
-            EN: u1,
-            /// When 1, writes to any alias other than 0x0 (caching, allocating)\n
-            /// will produce a bus fault. When 0, these writes are silently ignored.\n
-            /// In either case, writes to the 0x0 alias will deallocate on tag match,\n
-            /// as usual.
-            ERR_BADWRITE: u1,
-            reserved0: u1 = 0,
-            /// When 1, the cache memories are powered down. They retain state,\n
-            /// but can not be accessed. This reduces static power dissipation.\n
-            /// Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot\n
-            /// be enabled when powered down.\n
-            /// Cache-as-SRAM accesses will produce a bus error response when\n
-            /// the cache is powered down.
-            POWER_DOWN: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x14000004
-        /// Cache Flush control
-        pub const FLUSH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4);
-
-        /// address: 0x14000008
-        /// Cache Status
-        pub const STAT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reads as 0 while a cache flush is in progress, and 1 otherwise.\n
-            /// The cache is flushed whenever the XIP block is reset, and also\n
-            /// when requested via the FLUSH register.
-            FLUSH_READY: u1,
-            /// When 1, indicates the XIP streaming FIFO is completely empty.
-            FIFO_EMPTY: u1,
-            /// When 1, indicates the XIP streaming FIFO is completely full.\n
-            /// The streaming FIFO is 2 entries deep, so the full and empty\n
-            /// flag allow its level to be ascertained.
-            FIFO_FULL: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x1400000c
-        /// Cache Hit counter\n
-        /// A 32 bit saturating counter that increments upon each cache hit,\n
-        /// i.e. when an XIP access is serviced directly from cached data.\n
-        /// Write any value to clear.
-        pub const CTR_HIT = @intToPtr(*volatile u32, base_address + 0xc);
-
-        /// address: 0x14000010
-        /// Cache Access counter\n
-        /// A 32 bit saturating counter that increments upon each XIP access,\n
-        /// whether the cache is hit or not. This includes noncacheable accesses.\n
-        /// Write any value to clear.
-        pub const CTR_ACC = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x14000014
-        /// FIFO stream address
-        pub const STREAM_ADDR = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x14);
-
-        /// address: 0x14000018
-        /// FIFO stream control
-        pub const STREAM_CTR = @intToPtr(*volatile MmioInt(32, u22), base_address + 0x18);
-
-        /// address: 0x1400001c
-        /// FIFO stream data\n
-        /// Streamed data is buffered here, for retrieval by the system DMA.\n
-        /// This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing\n
-        /// the DMA to bus stalls caused by other XIP traffic.
-        pub const STREAM_FIFO = @intToPtr(*volatile u32, base_address + 0x1c);
-    };
-
-    /// DW_apb_ssi has the following features:\n
-    /// * APB interface – Allows for easy integration into a DesignWare Synthesizable
-    /// Components for AMBA 2 implementation.\n
-    /// * APB3 and APB4 protocol support.\n
-    /// * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32
-    /// bits.\n
-    /// * Serial-master or serial-slave operation – Enables serial communication with
-    /// serial-master or serial-slave peripheral devices.\n
-    /// * Programmable Dual/Quad/Octal SPI support in Master Mode.\n
-    /// * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the
-    /// DW_apb_ssi master to perform operations with the device in DDR and RDS modes
-    /// when working in Dual/Quad/Octal mode of operation.\n
-    /// * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in
-    /// the device. This feature is applicable only in enhanced SPI modes.\n
-    /// * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a
-    /// memory mapped I/O and fetches the data from the device based on the APB read
-    /// request. This feature is applicable only in enhanced SPI modes.\n
-    /// * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA
-    /// controller over the bus using a handshaking interface for transfer requests.\n
-    /// * Independent masking of interrupts – Master collision, transmit FIFO
-    /// overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and
-    /// receive FIFO overflow interrupts can all be masked independently.\n
-    /// * Multi-master contention detection – Informs the processor of multiple
-    /// serial-master accesses on the serial bus.\n
-    /// * Bypass of meta-stability flip-flops for synchronous clocks – When the APB
-    /// clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous,
-    /// meta-stable flip-flops are not used when transferring control signals across
-    /// these clock domains.\n
-    /// * Programmable delay on the sample time of the received serial data bit (rxd);
-    /// enables programmable control of routing delays resulting in higher serial
-    /// data-bit rates.\n
-    /// * Programmable features:\n
-    /// - Serial interface operation – Choice of Motorola SPI, Texas Instruments
-    /// Synchronous Serial Protocol or National Semiconductor Microwire.\n
-    /// - Clock bit-rate – Dynamic control of the serial bit rate of the data
-    /// transfer; used in only serial-master mode of operation.\n
-    /// - Data Item size (4 to 32 bits) – Item size of each data transfer under the
-    /// control of the programmer.\n
-    /// * Configured features:\n
-    /// - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.\n
-    /// - 1 slave select output.\n
-    /// - Hardware slave-select – Dedicated hardware slave-select line.\n
-    /// - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to
-    /// the interrupt controller.\n
-    /// - Interrupt polarity – active high interrupt lines.\n
-    /// - Serial clock polarity – low serial-clock polarity directly after reset.\n
-    /// - Serial clock phase – capture on first edge of serial-clock directly after
-    /// reset.
-    pub const XIP_SSI = struct {
-        pub const base_address = 0x18000000;
-        pub const version = "1";
-
-        /// address: 0x18000000
-        /// Control register 0
-        pub const CTRLR0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Data frame size
-            DFS: u4,
-            /// Frame format
-            FRF: u2,
-            /// Serial clock phase
-            SCPH: u1,
-            /// Serial clock polarity
-            SCPOL: u1,
-            /// Transfer mode
-            TMOD: u2,
-            /// Slave output enable
-            SLV_OE: u1,
-            /// Shift register loop (test mode)
-            SRL: u1,
-            /// Control frame size\n
-            /// Value of n -> n+1 clocks per frame.
-            CFS: u4,
-            /// Data frame size in 32b transfer mode\n
-            /// Value of n -> n+1 clocks per frame.
-            DFS_32: u5,
-            /// SPI frame format
-            SPI_FRF: u2,
-            reserved0: u1 = 0,
-            /// Slave select toggle enable
-            SSTE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x18000004
-        /// Master Control register 1
-        pub const CTRLR1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Number of data frames
-            NDF: u16,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x18000008
-        /// SSI Enable
-        pub const SSIENR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SSI enable
-            SSI_EN: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x1800000c
-        /// Microwire Control
-        pub const MWCR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Microwire transfer mode
-            MWMOD: u1,
-            /// Microwire control
-            MDD: u1,
-            /// Microwire handshaking
-            MHS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x18000010
-        /// Slave enable
-        pub const SER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x10);
-
-        /// address: 0x18000014
-        /// Baud rate
-        pub const BAUDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SSI clock divider
-            SCKDV: u16,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x18000018
-        /// TX FIFO threshold level
-        pub const TXFTLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit FIFO threshold
-            TFT: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x1800001c
-        /// RX FIFO threshold level
-        pub const RXFTLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive FIFO threshold
-            RFT: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x1c);
-
-        /// address: 0x18000020
-        /// TX FIFO level
-        pub const TXFLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit FIFO level
-            TFTFL: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x20);
-
-        /// address: 0x18000024
-        /// RX FIFO level
-        pub const RXFLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive FIFO level
-            RXTFL: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x24);
-
-        /// address: 0x18000028
-        /// Status register
-        pub const SR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SSI busy flag
-            BUSY: u1,
-            /// Transmit FIFO not full
-            TFNF: u1,
-            /// Transmit FIFO empty
-            TFE: u1,
-            /// Receive FIFO not empty
-            RFNE: u1,
-            /// Receive FIFO full
-            RFF: u1,
-            /// Transmission error
-            TXE: u1,
-            /// Data collision error
-            DCOL: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-        }), base_address + 0x28);
-
-        /// address: 0x1800002c
-        /// Interrupt mask
-        pub const IMR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit FIFO empty interrupt mask
-            TXEIM: u1,
-            /// Transmit FIFO overflow interrupt mask
-            TXOIM: u1,
-            /// Receive FIFO underflow interrupt mask
-            RXUIM: u1,
-            /// Receive FIFO overflow interrupt mask
-            RXOIM: u1,
-            /// Receive FIFO full interrupt mask
-            RXFIM: u1,
-            /// Multi-master contention interrupt mask
-            MSTIM: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-        }), base_address + 0x2c);
-
-        /// address: 0x18000030
-        /// Interrupt status
-        pub const ISR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit FIFO empty interrupt status
-            TXEIS: u1,
-            /// Transmit FIFO overflow interrupt status
-            TXOIS: u1,
-            /// Receive FIFO underflow interrupt status
-            RXUIS: u1,
-            /// Receive FIFO overflow interrupt status
-            RXOIS: u1,
-            /// Receive FIFO full interrupt status
-            RXFIS: u1,
-            /// Multi-master contention interrupt status
-            MSTIS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-        }), base_address + 0x30);
-
-        /// address: 0x18000034
-        /// Raw interrupt status
-        pub const RISR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit FIFO empty raw interrupt status
-            TXEIR: u1,
-            /// Transmit FIFO overflow raw interrupt status
-            TXOIR: u1,
-            /// Receive FIFO underflow raw interrupt status
-            RXUIR: u1,
-            /// Receive FIFO overflow raw interrupt status
-            RXOIR: u1,
-            /// Receive FIFO full raw interrupt status
-            RXFIR: u1,
-            /// Multi-master contention raw interrupt status
-            MSTIR: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-        }), base_address + 0x34);
-
-        /// address: 0x18000038
-        /// TX FIFO overflow interrupt clear
-        pub const TXOICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x38);
-
-        /// address: 0x1800003c
-        /// RX FIFO overflow interrupt clear
-        pub const RXOICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x3c);
-
-        /// address: 0x18000040
-        /// RX FIFO underflow interrupt clear
-        pub const RXUICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x40);
-
-        /// address: 0x18000044
-        /// Multi-master interrupt clear
-        pub const MSTICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x44);
-
-        /// address: 0x18000048
-        /// Interrupt clear
-        pub const ICR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x48);
-
-        /// address: 0x1800004c
-        /// DMA control
-        pub const DMACR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive DMA enable
-            RDMAE: u1,
-            /// Transmit DMA enable
-            TDMAE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x4c);
-
-        /// address: 0x18000050
-        /// DMA TX data level
-        pub const DMATDLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit data watermark level
-            DMATDL: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x50);
-
-        /// address: 0x18000054
-        /// DMA RX data level
-        pub const DMARDLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive data watermark level (DMARDLR+1)
-            DMARDL: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x54);
-
-        /// address: 0x18000058
-        /// Identification register
-        pub const IDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Peripheral dentification code
-            IDCODE: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x1800005c
-        /// Version ID
-        pub const SSI_VERSION_ID = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SNPS component version (format X.YY)
-            SSI_COMP_VERSION: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x18000060
-        /// Data Register 0 (of 36)
-        pub const DR0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// First data register of 36
-            DR: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x180000f0
-        /// RX sample delay
-        pub const RX_SAMPLE_DLY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// RXD sample delay (in SCLK cycles)
-            RSD: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xf0);
-
-        /// address: 0x180000f4
-        /// SPI control
-        pub const SPI_CTRLR0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Address and instruction transfer format
-            TRANS_TYPE: u2,
-            /// Address length (0b-60b in 4b increments)
-            ADDR_L: u4,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// Instruction length (0/4/8/16b)
-            INST_L: u2,
-            reserved2: u1 = 0,
-            /// Wait cycles between control frame transmit and data reception (in SCLK cycles)
-            WAIT_CYCLES: u5,
-            /// SPI DDR transfer enable
-            SPI_DDR_EN: u1,
-            /// Instruction DDR transfer enable
-            INST_DDR_EN: u1,
-            /// Read data strobe enable
-            SPI_RXDS_EN: u1,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L
-            /// = 0-bit)
-            XIP_CMD: u8,
-        }), base_address + 0xf4);
-
-        /// address: 0x180000f8
-        /// TX drive edge
-        pub const TXD_DRIVE_EDGE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// TXD drive edge
-            TDE: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xf8);
-    };
-    pub const SYSINFO = struct {
-        pub const base_address = 0x40000000;
-        pub const version = "1";
-
-        /// address: 0x40000000
-        /// JEDEC JEP-106 compliant chip identifier.
-        pub const CHIP_ID = @intToPtr(*volatile Mmio(32, packed struct {
-            MANUFACTURER: u12,
-            PART: u16,
-            REVISION: u4,
-        }), base_address + 0x0);
-
-        /// address: 0x40000004
-        /// Platform register. Allows software to know what environment it is running in.
-        pub const PLATFORM = @intToPtr(*volatile Mmio(32, packed struct {
-            FPGA: u1,
-            ASIC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40000040
-        /// Git hash of the chip source. Used to identify chip version.
-        pub const GITREF_RP2040 = @intToPtr(*volatile u32, base_address + 0x40);
-    };
-
-    /// Register block for various chip control signals
-    pub const SYSCFG = struct {
-        pub const base_address = 0x40004000;
-        pub const version = "1";
-
-        /// address: 0x40004000
-        /// Processor core 0 NMI source mask\n
-        /// Set a bit high to enable NMI from that IRQ
-        pub const PROC0_NMI_MASK = @intToPtr(*volatile u32, base_address + 0x0);
-
-        /// address: 0x40004004
-        /// Processor core 1 NMI source mask\n
-        /// Set a bit high to enable NMI from that IRQ
-        pub const PROC1_NMI_MASK = @intToPtr(*volatile u32, base_address + 0x4);
-
-        /// address: 0x40004008
-        /// Configuration for processors
-        pub const PROC_CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Indication that proc0 has halted
-            PROC0_HALTED: u1,
-            /// Indication that proc1 has halted
-            PROC1_HALTED: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            reserved18: u1 = 0,
-            reserved19: u1 = 0,
-            reserved20: u1 = 0,
-            reserved21: u1 = 0,
-            /// Configure proc0 DAP instance ID.\n
-            /// Recommend that this is NOT changed until you require debug access in multi-chip
-            /// environment\n
-            /// WARNING: do not set to 15 as this is reserved for RescueDP
-            PROC0_DAP_INSTID: u4,
-            /// Configure proc1 DAP instance ID.\n
-            /// Recommend that this is NOT changed until you require debug access in multi-chip
-            /// environment\n
-            /// WARNING: do not set to 15 as this is reserved for RescueDP
-            PROC1_DAP_INSTID: u4,
-        }), base_address + 0x8);
-
-        /// address: 0x4000400c
-        /// For each bit, if 1, bypass the input synchronizer between that GPIO\n
-        /// and the GPIO input register in the SIO. The input synchronizers should\n
-        /// generally be unbypassed, to avoid injecting metastabilities into processors.\n
-        /// If you're feeling brave, you can bypass to save two cycles of input\n
-        /// latency. This register applies to GPIO 0...29.
-        pub const PROC_IN_SYNC_BYPASS = @intToPtr(*volatile MmioInt(32, u30), base_address + 0xc);
-
-        /// address: 0x40004010
-        /// For each bit, if 1, bypass the input synchronizer between that GPIO\n
-        /// and the GPIO input register in the SIO. The input synchronizers should\n
-        /// generally be unbypassed, to avoid injecting metastabilities into processors.\n
-        /// If you're feeling brave, you can bypass to save two cycles of input\n
-        /// latency. This register applies to GPIO 30...35 (the QSPI IOs).
-        pub const PROC_IN_SYNC_BYPASS_HI = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x10);
-
-        /// address: 0x40004014
-        /// Directly control the SWD debug port of either processor
-        pub const DBGFORCE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Observe the value of processor 0 SWDIO output.
-            PROC0_SWDO: u1,
-            /// Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
-            PROC0_SWDI: u1,
-            /// Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
-            PROC0_SWCLK: u1,
-            /// Attach processor 0 debug port to syscfg controls, and disconnect it from
-            /// external SWD pads.
-            PROC0_ATTACH: u1,
-            /// Observe the value of processor 1 SWDIO output.
-            PROC1_SWDO: u1,
-            /// Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
-            PROC1_SWDI: u1,
-            /// Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
-            PROC1_SWCLK: u1,
-            /// Attach processor 1 debug port to syscfg controls, and disconnect it from
-            /// external SWD pads.
-            PROC1_ATTACH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x40004018
-        /// Control power downs to memories. Set high to power down memories.\n
-        /// Use with extreme caution
-        pub const MEMPOWERDOWN = @intToPtr(*volatile Mmio(32, packed struct {
-            SRAM0: u1,
-            SRAM1: u1,
-            SRAM2: u1,
-            SRAM3: u1,
-            SRAM4: u1,
-            SRAM5: u1,
-            USB: u1,
-            ROM: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x18);
-    };
-    pub const CLOCKS = struct {
-        pub const base_address = 0x40008000;
-        pub const version = "1";
-
-        /// address: 0x40008000
-        /// Clock control, can be changed on-the-fly (except for auxsrc)
-        pub const CLK_GPOUT0_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            /// Selects the auxiliary clock source, will glitch when switching
-            AUXSRC: u4,
-            reserved5: u1 = 0,
-            /// Asynchronously kills the clock generator
-            KILL: u1,
-            /// Starts and stops the clock generator cleanly
-            ENABLE: u1,
-            /// Enables duty cycle correction for odd divisors
-            DC50: u1,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// This delays the enable signal by up to 3 cycles of the input clock\n
-            /// This must be set before the clock is enabled to have any effect
-            PHASE: u2,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            /// An edge on this signal shifts the phase of the output by 1 cycle of the input
-            /// clock\n
-            /// This can be done at any time
-            NUDGE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40008004
-        /// Clock divisor, can be changed on-the-fly
-        pub const CLK_GPOUT0_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Fractional component of the divisor
-            FRAC: u8,
-            /// Integer component of the divisor, 0 -> divide by 2^16
-            INT: u24,
-        }), base_address + 0x4);
-
-        /// address: 0x40008008
-        /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-        /// This slice does not have a glitchless mux (only the AUX_SRC field is present,
-        /// not SRC) so this register is hardwired to 0x1.
-        pub const CLK_GPOUT0_SELECTED = @intToPtr(*volatile u32, base_address + 0x8);
-
-        /// address: 0x4000800c
-        /// Clock control, can be changed on-the-fly (except for auxsrc)
-        pub const CLK_GPOUT1_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            /// Selects the auxiliary clock source, will glitch when switching
-            AUXSRC: u4,
-            reserved5: u1 = 0,
-            /// Asynchronously kills the clock generator
-            KILL: u1,
-            /// Starts and stops the clock generator cleanly
-            ENABLE: u1,
-            /// Enables duty cycle correction for odd divisors
-            DC50: u1,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// This delays the enable signal by up to 3 cycles of the input clock\n
-            /// This must be set before the clock is enabled to have any effect
-            PHASE: u2,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            /// An edge on this signal shifts the phase of the output by 1 cycle of the input
-            /// clock\n
-            /// This can be done at any time
-            NUDGE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x40008010
-        /// Clock divisor, can be changed on-the-fly
-        pub const CLK_GPOUT1_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Fractional component of the divisor
-            FRAC: u8,
-            /// Integer component of the divisor, 0 -> divide by 2^16
-            INT: u24,
-        }), base_address + 0x10);
-
-        /// address: 0x40008014
-        /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-        /// This slice does not have a glitchless mux (only the AUX_SRC field is present,
-        /// not SRC) so this register is hardwired to 0x1.
-        pub const CLK_GPOUT1_SELECTED = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x40008018
-        /// Clock control, can be changed on-the-fly (except for auxsrc)
-        pub const CLK_GPOUT2_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            /// Selects the auxiliary clock source, will glitch when switching
-            AUXSRC: u4,
-            reserved5: u1 = 0,
-            /// Asynchronously kills the clock generator
-            KILL: u1,
-            /// Starts and stops the clock generator cleanly
-            ENABLE: u1,
-            /// Enables duty cycle correction for odd divisors
-            DC50: u1,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// This delays the enable signal by up to 3 cycles of the input clock\n
-            /// This must be set before the clock is enabled to have any effect
-            PHASE: u2,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            /// An edge on this signal shifts the phase of the output by 1 cycle of the input
-            /// clock\n
-            /// This can be done at any time
-            NUDGE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x4000801c
-        /// Clock divisor, can be changed on-the-fly
-        pub const CLK_GPOUT2_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Fractional component of the divisor
-            FRAC: u8,
-            /// Integer component of the divisor, 0 -> divide by 2^16
-            INT: u24,
-        }), base_address + 0x1c);
-
-        /// address: 0x40008020
-        /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-        /// This slice does not have a glitchless mux (only the AUX_SRC field is present,
-        /// not SRC) so this register is hardwired to 0x1.
-        pub const CLK_GPOUT2_SELECTED = @intToPtr(*volatile u32, base_address + 0x20);
-
-        /// address: 0x40008024
-        /// Clock control, can be changed on-the-fly (except for auxsrc)
-        pub const CLK_GPOUT3_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            /// Selects the auxiliary clock source, will glitch when switching
-            AUXSRC: u4,
-            reserved5: u1 = 0,
-            /// Asynchronously kills the clock generator
-            KILL: u1,
-            /// Starts and stops the clock generator cleanly
-            ENABLE: u1,
-            /// Enables duty cycle correction for odd divisors
-            DC50: u1,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// This delays the enable signal by up to 3 cycles of the input clock\n
-            /// This must be set before the clock is enabled to have any effect
-            PHASE: u2,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            /// An edge on this signal shifts the phase of the output by 1 cycle of the input
-            /// clock\n
-            /// This can be done at any time
-            NUDGE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-        }), base_address + 0x24);
-
-        /// address: 0x40008028
-        /// Clock divisor, can be changed on-the-fly
-        pub const CLK_GPOUT3_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Fractional component of the divisor
-            FRAC: u8,
-            /// Integer component of the divisor, 0 -> divide by 2^16
-            INT: u24,
-        }), base_address + 0x28);
-
-        /// address: 0x4000802c
-        /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-        /// This slice does not have a glitchless mux (only the AUX_SRC field is present,
-        /// not SRC) so this register is hardwired to 0x1.
-        pub const CLK_GPOUT3_SELECTED = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x40008030
-        /// Clock control, can be changed on-the-fly (except for auxsrc)
-        pub const CLK_REF_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Selects the clock source glitchlessly, can be changed on-the-fly
-            SRC: u2,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            /// Selects the auxiliary clock source, will glitch when switching
-            AUXSRC: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-        }), base_address + 0x30);
-
-        /// address: 0x40008034
-        /// Clock divisor, can be changed on-the-fly
-        pub const CLK_REF_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Integer component of the divisor, 0 -> divide by 2^16
-            INT: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-        }), base_address + 0x34);
-
-        /// address: 0x40008038
-        /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-        /// The glitchless multiplexer does not switch instantaneously (to avoid glitches),
-        /// so software should poll this register to wait for the switch to complete. This
-        /// register contains one decoded bit for each of the clock sources enumerated in
-        /// the CTRL SRC field. At most one of these bits will be set at any time,
-        /// indicating that clock is currently present at the output of the glitchless mux.
-        /// Whilst switching is in progress, this register may briefly show all-0s.
-        pub const CLK_REF_SELECTED = @intToPtr(*volatile u32, base_address + 0x38);
-
-        /// address: 0x4000803c
-        /// Clock control, can be changed on-the-fly (except for auxsrc)
-        pub const CLK_SYS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Selects the clock source glitchlessly, can be changed on-the-fly
-            SRC: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// Selects the auxiliary clock source, will glitch when switching
-            AUXSRC: u3,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x3c);
-
-        /// address: 0x40008040
-        /// Clock divisor, can be changed on-the-fly
-        pub const CLK_SYS_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Fractional component of the divisor
-            FRAC: u8,
-            /// Integer component of the divisor, 0 -> divide by 2^16
-            INT: u24,
-        }), base_address + 0x40);
-
-        /// address: 0x40008044
-        /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-        /// The glitchless multiplexer does not switch instantaneously (to avoid glitches),
-        /// so software should poll this register to wait for the switch to complete. This
-        /// register contains one decoded bit for each of the clock sources enumerated in
-        /// the CTRL SRC field. At most one of these bits will be set at any time,
-        /// indicating that clock is currently present at the output of the glitchless mux.
-        /// Whilst switching is in progress, this register may briefly show all-0s.
-        pub const CLK_SYS_SELECTED = @intToPtr(*volatile u32, base_address + 0x44);
-
-        /// address: 0x40008048
-        /// Clock control, can be changed on-the-fly (except for auxsrc)
-        pub const CLK_PERI_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            /// Selects the auxiliary clock source, will glitch when switching
-            AUXSRC: u3,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            /// Asynchronously kills the clock generator
-            KILL: u1,
-            /// Starts and stops the clock generator cleanly
-            ENABLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x48);
-
-        /// address: 0x40008050
-        /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-        /// This slice does not have a glitchless mux (only the AUX_SRC field is present,
-        /// not SRC) so this register is hardwired to 0x1.
-        pub const CLK_PERI_SELECTED = @intToPtr(*volatile u32, base_address + 0x50);
-
-        /// address: 0x40008054
-        /// Clock control, can be changed on-the-fly (except for auxsrc)
-        pub const CLK_USB_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            /// Selects the auxiliary clock source, will glitch when switching
-            AUXSRC: u3,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            /// Asynchronously kills the clock generator
-            KILL: u1,
-            /// Starts and stops the clock generator cleanly
-            ENABLE: u1,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            /// This delays the enable signal by up to 3 cycles of the input clock\n
-            /// This must be set before the clock is enabled to have any effect
-            PHASE: u2,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// An edge on this signal shifts the phase of the output by 1 cycle of the input
-            /// clock\n
-            /// This can be done at any time
-            NUDGE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-        }), base_address + 0x54);
-
-        /// address: 0x40008058
-        /// Clock divisor, can be changed on-the-fly
-        pub const CLK_USB_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Integer component of the divisor, 0 -> divide by 2^16
-            INT: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-        }), base_address + 0x58);
-
-        /// address: 0x4000805c
-        /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-        /// This slice does not have a glitchless mux (only the AUX_SRC field is present,
-        /// not SRC) so this register is hardwired to 0x1.
-        pub const CLK_USB_SELECTED = @intToPtr(*volatile u32, base_address + 0x5c);
-
-        /// address: 0x40008060
-        /// Clock control, can be changed on-the-fly (except for auxsrc)
-        pub const CLK_ADC_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            /// Selects the auxiliary clock source, will glitch when switching
-            AUXSRC: u3,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            /// Asynchronously kills the clock generator
-            KILL: u1,
-            /// Starts and stops the clock generator cleanly
-            ENABLE: u1,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            /// This delays the enable signal by up to 3 cycles of the input clock\n
-            /// This must be set before the clock is enabled to have any effect
-            PHASE: u2,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// An edge on this signal shifts the phase of the output by 1 cycle of the input
-            /// clock\n
-            /// This can be done at any time
-            NUDGE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-        }), base_address + 0x60);
-
-        /// address: 0x40008064
-        /// Clock divisor, can be changed on-the-fly
-        pub const CLK_ADC_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Integer component of the divisor, 0 -> divide by 2^16
-            INT: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-        }), base_address + 0x64);
-
-        /// address: 0x40008068
-        /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-        /// This slice does not have a glitchless mux (only the AUX_SRC field is present,
-        /// not SRC) so this register is hardwired to 0x1.
-        pub const CLK_ADC_SELECTED = @intToPtr(*volatile u32, base_address + 0x68);
-
-        /// address: 0x4000806c
-        /// Clock control, can be changed on-the-fly (except for auxsrc)
-        pub const CLK_RTC_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            /// Selects the auxiliary clock source, will glitch when switching
-            AUXSRC: u3,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            /// Asynchronously kills the clock generator
-            KILL: u1,
-            /// Starts and stops the clock generator cleanly
-            ENABLE: u1,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            /// This delays the enable signal by up to 3 cycles of the input clock\n
-            /// This must be set before the clock is enabled to have any effect
-            PHASE: u2,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// An edge on this signal shifts the phase of the output by 1 cycle of the input
-            /// clock\n
-            /// This can be done at any time
-            NUDGE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-        }), base_address + 0x6c);
-
-        /// address: 0x40008070
-        /// Clock divisor, can be changed on-the-fly
-        pub const CLK_RTC_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Fractional component of the divisor
-            FRAC: u8,
-            /// Integer component of the divisor, 0 -> divide by 2^16
-            INT: u24,
-        }), base_address + 0x70);
-
-        /// address: 0x40008074
-        /// Indicates which SRC is currently selected by the glitchless mux (one-hot).\n
-        /// This slice does not have a glitchless mux (only the AUX_SRC field is present,
-        /// not SRC) so this register is hardwired to 0x1.
-        pub const CLK_RTC_SELECTED = @intToPtr(*volatile u32, base_address + 0x74);
-
-        /// address: 0x40008078
-        pub const CLK_SYS_RESUS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is expressed as a number of clk_ref cycles\n
-            /// and must be >= 2x clk_ref_freq/min_clk_tst_freq
-            TIMEOUT: u8,
-            /// Enable resus
-            ENABLE: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            /// Force a resus, for test purposes only
-            FRCE: u1,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            /// For clearing the resus after the fault that triggered it has been corrected
-            CLEAR: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-        }), base_address + 0x78);
-
-        /// address: 0x4000807c
-        pub const CLK_SYS_RESUS_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Clock has been resuscitated, correct the error then send ctrl_clear=1
-            RESUSSED: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x7c);
-
-        /// address: 0x40008080
-        /// Reference clock frequency in kHz
-        pub const FC0_REF_KHZ = @intToPtr(*volatile MmioInt(32, u20), base_address + 0x80);
-
-        /// address: 0x40008084
-        /// Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using
-        /// the pass/fail flags
-        pub const FC0_MIN_KHZ = @intToPtr(*volatile MmioInt(32, u25), base_address + 0x84);
-
-        /// address: 0x40008088
-        /// Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not
-        /// using the pass/fail flags
-        pub const FC0_MAX_KHZ = @intToPtr(*volatile MmioInt(32, u25), base_address + 0x88);
-
-        /// address: 0x4000808c
-        /// Delays the start of frequency counting to allow the mux to settle\n
-        /// Delay is measured in multiples of the reference clock period
-        pub const FC0_DELAY = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x8c);
-
-        /// address: 0x40008090
-        /// The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval\n
-        /// The default gives a test interval of 250us
-        pub const FC0_INTERVAL = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x90);
-
-        /// address: 0x40008094
-        /// Clock sent to frequency counter, set to 0 when not required\n
-        /// Writing to this register initiates the frequency count
-        pub const FC0_SRC = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x94);
-
-        /// address: 0x40008098
-        /// Frequency counter status
-        pub const FC0_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Test passed
-            PASS: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            /// Test complete
-            DONE: u1,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            /// Test running
-            RUNNING: u1,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Waiting for test clock to start
-            WAITING: u1,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            /// Test failed
-            FAIL: u1,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            /// Test clock slower than expected, only valid when status_done=1
-            SLOW: u1,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// Test clock faster than expected, only valid when status_done=1
-            FAST: u1,
-            reserved18: u1 = 0,
-            reserved19: u1 = 0,
-            reserved20: u1 = 0,
-            /// Test clock stopped during test
-            DIED: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-        }), base_address + 0x98);
-
-        /// address: 0x4000809c
-        /// Result of frequency measurement, only valid when status_done=1
-        pub const FC0_RESULT = @intToPtr(*volatile Mmio(32, packed struct {
-            FRAC: u5,
-            KHZ: u25,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x9c);
-
-        /// address: 0x400080a0
-        /// enable clock in wake mode
-        pub const WAKE_EN0 = @intToPtr(*volatile Mmio(32, packed struct {
-            clk_sys_clocks: u1,
-            clk_adc_adc: u1,
-            clk_sys_adc: u1,
-            clk_sys_busctrl: u1,
-            clk_sys_busfabric: u1,
-            clk_sys_dma: u1,
-            clk_sys_i2c0: u1,
-            clk_sys_i2c1: u1,
-            clk_sys_io: u1,
-            clk_sys_jtag: u1,
-            clk_sys_vreg_and_chip_reset: u1,
-            clk_sys_pads: u1,
-            clk_sys_pio0: u1,
-            clk_sys_pio1: u1,
-            clk_sys_pll_sys: u1,
-            clk_sys_pll_usb: u1,
-            clk_sys_psm: u1,
-            clk_sys_pwm: u1,
-            clk_sys_resets: u1,
-            clk_sys_rom: u1,
-            clk_sys_rosc: u1,
-            clk_rtc_rtc: u1,
-            clk_sys_rtc: u1,
-            clk_sys_sio: u1,
-            clk_peri_spi0: u1,
-            clk_sys_spi0: u1,
-            clk_peri_spi1: u1,
-            clk_sys_spi1: u1,
-            clk_sys_sram0: u1,
-            clk_sys_sram1: u1,
-            clk_sys_sram2: u1,
-            clk_sys_sram3: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x400080a4
-        /// enable clock in wake mode
-        pub const WAKE_EN1 = @intToPtr(*volatile Mmio(32, packed struct {
-            clk_sys_sram4: u1,
-            clk_sys_sram5: u1,
-            clk_sys_syscfg: u1,
-            clk_sys_sysinfo: u1,
-            clk_sys_tbman: u1,
-            clk_sys_timer: u1,
-            clk_peri_uart0: u1,
-            clk_sys_uart0: u1,
-            clk_peri_uart1: u1,
-            clk_sys_uart1: u1,
-            clk_sys_usbctrl: u1,
-            clk_usb_usbctrl: u1,
-            clk_sys_watchdog: u1,
-            clk_sys_xip: u1,
-            clk_sys_xosc: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-        }), base_address + 0xa4);
-
-        /// address: 0x400080a8
-        /// enable clock in sleep mode
-        pub const SLEEP_EN0 = @intToPtr(*volatile Mmio(32, packed struct {
-            clk_sys_clocks: u1,
-            clk_adc_adc: u1,
-            clk_sys_adc: u1,
-            clk_sys_busctrl: u1,
-            clk_sys_busfabric: u1,
-            clk_sys_dma: u1,
-            clk_sys_i2c0: u1,
-            clk_sys_i2c1: u1,
-            clk_sys_io: u1,
-            clk_sys_jtag: u1,
-            clk_sys_vreg_and_chip_reset: u1,
-            clk_sys_pads: u1,
-            clk_sys_pio0: u1,
-            clk_sys_pio1: u1,
-            clk_sys_pll_sys: u1,
-            clk_sys_pll_usb: u1,
-            clk_sys_psm: u1,
-            clk_sys_pwm: u1,
-            clk_sys_resets: u1,
-            clk_sys_rom: u1,
-            clk_sys_rosc: u1,
-            clk_rtc_rtc: u1,
-            clk_sys_rtc: u1,
-            clk_sys_sio: u1,
-            clk_peri_spi0: u1,
-            clk_sys_spi0: u1,
-            clk_peri_spi1: u1,
-            clk_sys_spi1: u1,
-            clk_sys_sram0: u1,
-            clk_sys_sram1: u1,
-            clk_sys_sram2: u1,
-            clk_sys_sram3: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x400080ac
-        /// enable clock in sleep mode
-        pub const SLEEP_EN1 = @intToPtr(*volatile Mmio(32, packed struct {
-            clk_sys_sram4: u1,
-            clk_sys_sram5: u1,
-            clk_sys_syscfg: u1,
-            clk_sys_sysinfo: u1,
-            clk_sys_tbman: u1,
-            clk_sys_timer: u1,
-            clk_peri_uart0: u1,
-            clk_sys_uart0: u1,
-            clk_peri_uart1: u1,
-            clk_sys_uart1: u1,
-            clk_sys_usbctrl: u1,
-            clk_usb_usbctrl: u1,
-            clk_sys_watchdog: u1,
-            clk_sys_xip: u1,
-            clk_sys_xosc: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-        }), base_address + 0xac);
-
-        /// address: 0x400080b0
-        /// indicates the state of the clock enable
-        pub const ENABLED0 = @intToPtr(*volatile Mmio(32, packed struct {
-            clk_sys_clocks: u1,
-            clk_adc_adc: u1,
-            clk_sys_adc: u1,
-            clk_sys_busctrl: u1,
-            clk_sys_busfabric: u1,
-            clk_sys_dma: u1,
-            clk_sys_i2c0: u1,
-            clk_sys_i2c1: u1,
-            clk_sys_io: u1,
-            clk_sys_jtag: u1,
-            clk_sys_vreg_and_chip_reset: u1,
-            clk_sys_pads: u1,
-            clk_sys_pio0: u1,
-            clk_sys_pio1: u1,
-            clk_sys_pll_sys: u1,
-            clk_sys_pll_usb: u1,
-            clk_sys_psm: u1,
-            clk_sys_pwm: u1,
-            clk_sys_resets: u1,
-            clk_sys_rom: u1,
-            clk_sys_rosc: u1,
-            clk_rtc_rtc: u1,
-            clk_sys_rtc: u1,
-            clk_sys_sio: u1,
-            clk_peri_spi0: u1,
-            clk_sys_spi0: u1,
-            clk_peri_spi1: u1,
-            clk_sys_spi1: u1,
-            clk_sys_sram0: u1,
-            clk_sys_sram1: u1,
-            clk_sys_sram2: u1,
-            clk_sys_sram3: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x400080b4
-        /// indicates the state of the clock enable
-        pub const ENABLED1 = @intToPtr(*volatile Mmio(32, packed struct {
-            clk_sys_sram4: u1,
-            clk_sys_sram5: u1,
-            clk_sys_syscfg: u1,
-            clk_sys_sysinfo: u1,
-            clk_sys_tbman: u1,
-            clk_sys_timer: u1,
-            clk_peri_uart0: u1,
-            clk_sys_uart0: u1,
-            clk_peri_uart1: u1,
-            clk_sys_uart1: u1,
-            clk_sys_usbctrl: u1,
-            clk_usb_usbctrl: u1,
-            clk_sys_watchdog: u1,
-            clk_sys_xip: u1,
-            clk_sys_xosc: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-        }), base_address + 0xb4);
-
-        /// address: 0x400080b8
-        /// Raw Interrupts
-        pub const INTR = @intToPtr(*volatile Mmio(32, packed struct {
-            CLK_SYS_RESUS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0xb8);
-
-        /// address: 0x400080bc
-        /// Interrupt Enable
-        pub const INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            CLK_SYS_RESUS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0xbc);
-
-        /// address: 0x400080c0
-        /// Interrupt Force
-        pub const INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            CLK_SYS_RESUS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0xc0);
-
-        /// address: 0x400080c4
-        /// Interrupt status after masking & forcing
-        pub const INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            CLK_SYS_RESUS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0xc4);
-    };
-    pub const RESETS = struct {
-        pub const base_address = 0x4000c000;
-        pub const version = "1";
-
-        /// address: 0x4000c000
-        /// Reset control. If a bit is set it means the peripheral is in reset. 0 means the
-        /// peripheral's reset is deasserted.
-        pub const RESET = @intToPtr(*volatile Mmio(32, packed struct {
-            adc: u1,
-            busctrl: u1,
-            dma: u1,
-            i2c0: u1,
-            i2c1: u1,
-            io_bank0: u1,
-            io_qspi: u1,
-            jtag: u1,
-            pads_bank0: u1,
-            pads_qspi: u1,
-            pio0: u1,
-            pio1: u1,
-            pll_sys: u1,
-            pll_usb: u1,
-            pwm: u1,
-            rtc: u1,
-            spi0: u1,
-            spi1: u1,
-            syscfg: u1,
-            sysinfo: u1,
-            tbman: u1,
-            timer: u1,
-            uart0: u1,
-            uart1: u1,
-            usbctrl: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x4000c004
-        /// Watchdog select. If a bit is set then the watchdog will reset this peripheral
-        /// when the watchdog fires.
-        pub const WDSEL = @intToPtr(*volatile Mmio(32, packed struct {
-            adc: u1,
-            busctrl: u1,
-            dma: u1,
-            i2c0: u1,
-            i2c1: u1,
-            io_bank0: u1,
-            io_qspi: u1,
-            jtag: u1,
-            pads_bank0: u1,
-            pads_qspi: u1,
-            pio0: u1,
-            pio1: u1,
-            pll_sys: u1,
-            pll_usb: u1,
-            pwm: u1,
-            rtc: u1,
-            spi0: u1,
-            spi1: u1,
-            syscfg: u1,
-            sysinfo: u1,
-            tbman: u1,
-            timer: u1,
-            uart0: u1,
-            uart1: u1,
-            usbctrl: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x4000c008
-        /// Reset done. If a bit is set then a reset done signal has been returned by the
-        /// peripheral. This indicates that the peripheral's registers are ready to be
-        /// accessed.
-        pub const RESET_DONE = @intToPtr(*volatile Mmio(32, packed struct {
-            adc: u1,
-            busctrl: u1,
-            dma: u1,
-            i2c0: u1,
-            i2c1: u1,
-            io_bank0: u1,
-            io_qspi: u1,
-            jtag: u1,
-            pads_bank0: u1,
-            pads_qspi: u1,
-            pio0: u1,
-            pio1: u1,
-            pll_sys: u1,
-            pll_usb: u1,
-            pwm: u1,
-            rtc: u1,
-            spi0: u1,
-            spi1: u1,
-            syscfg: u1,
-            sysinfo: u1,
-            tbman: u1,
-            timer: u1,
-            uart0: u1,
-            uart1: u1,
-            usbctrl: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-        }), base_address + 0x8);
-    };
-    pub const PSM = struct {
-        pub const base_address = 0x40010000;
-        pub const version = "1";
-
-        /// address: 0x40010000
-        /// Force block out of reset (i.e. power it on)
-        pub const FRCE_ON = @intToPtr(*volatile Mmio(32, packed struct {
-            rosc: u1,
-            xosc: u1,
-            clocks: u1,
-            resets: u1,
-            busfabric: u1,
-            rom: u1,
-            sram0: u1,
-            sram1: u1,
-            sram2: u1,
-            sram3: u1,
-            sram4: u1,
-            sram5: u1,
-            xip: u1,
-            vreg_and_chip_reset: u1,
-            sio: u1,
-            proc0: u1,
-            proc1: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40010004
-        /// Force into reset (i.e. power it off)
-        pub const FRCE_OFF = @intToPtr(*volatile Mmio(32, packed struct {
-            rosc: u1,
-            xosc: u1,
-            clocks: u1,
-            resets: u1,
-            busfabric: u1,
-            rom: u1,
-            sram0: u1,
-            sram1: u1,
-            sram2: u1,
-            sram3: u1,
-            sram4: u1,
-            sram5: u1,
-            xip: u1,
-            vreg_and_chip_reset: u1,
-            sio: u1,
-            proc0: u1,
-            proc1: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40010008
-        /// Set to 1 if this peripheral should be reset when the watchdog fires.
-        pub const WDSEL = @intToPtr(*volatile Mmio(32, packed struct {
-            rosc: u1,
-            xosc: u1,
-            clocks: u1,
-            resets: u1,
-            busfabric: u1,
-            rom: u1,
-            sram0: u1,
-            sram1: u1,
-            sram2: u1,
-            sram3: u1,
-            sram4: u1,
-            sram5: u1,
-            xip: u1,
-            vreg_and_chip_reset: u1,
-            sio: u1,
-            proc0: u1,
-            proc1: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x4001000c
-        /// Indicates the peripheral's registers are ready to access.
-        pub const DONE = @intToPtr(*volatile Mmio(32, packed struct {
-            rosc: u1,
-            xosc: u1,
-            clocks: u1,
-            resets: u1,
-            busfabric: u1,
-            rom: u1,
-            sram0: u1,
-            sram1: u1,
-            sram2: u1,
-            sram3: u1,
-            sram4: u1,
-            sram5: u1,
-            xip: u1,
-            vreg_and_chip_reset: u1,
-            sio: u1,
-            proc0: u1,
-            proc1: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-        }), base_address + 0xc);
-    };
-    pub const IO_BANK0 = struct {
-        pub const base_address = 0x40014000;
-        pub const version = "1";
-
-        /// address: 0x40014000
-        /// GPIO status
-        pub const GPIO0_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40014004
-        /// GPIO control including function select and overrides.
-        pub const GPIO0_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40014008
-        /// GPIO status
-        pub const GPIO1_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x4001400c
-        /// GPIO control including function select and overrides.
-        pub const GPIO1_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x40014010
-        /// GPIO status
-        pub const GPIO2_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x10);
-
-        /// address: 0x40014014
-        /// GPIO control including function select and overrides.
-        pub const GPIO2_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x40014018
-        /// GPIO status
-        pub const GPIO3_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x4001401c
-        /// GPIO control including function select and overrides.
-        pub const GPIO3_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x1c);
-
-        /// address: 0x40014020
-        /// GPIO status
-        pub const GPIO4_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x20);
-
-        /// address: 0x40014024
-        /// GPIO control including function select and overrides.
-        pub const GPIO4_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x24);
-
-        /// address: 0x40014028
-        /// GPIO status
-        pub const GPIO5_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x28);
-
-        /// address: 0x4001402c
-        /// GPIO control including function select and overrides.
-        pub const GPIO5_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x2c);
-
-        /// address: 0x40014030
-        /// GPIO status
-        pub const GPIO6_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x30);
-
-        /// address: 0x40014034
-        /// GPIO control including function select and overrides.
-        pub const GPIO6_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x34);
-
-        /// address: 0x40014038
-        /// GPIO status
-        pub const GPIO7_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x38);
-
-        /// address: 0x4001403c
-        /// GPIO control including function select and overrides.
-        pub const GPIO7_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x3c);
-
-        /// address: 0x40014040
-        /// GPIO status
-        pub const GPIO8_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x40);
-
-        /// address: 0x40014044
-        /// GPIO control including function select and overrides.
-        pub const GPIO8_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x44);
-
-        /// address: 0x40014048
-        /// GPIO status
-        pub const GPIO9_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x48);
-
-        /// address: 0x4001404c
-        /// GPIO control including function select and overrides.
-        pub const GPIO9_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x4c);
-
-        /// address: 0x40014050
-        /// GPIO status
-        pub const GPIO10_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x50);
-
-        /// address: 0x40014054
-        /// GPIO control including function select and overrides.
-        pub const GPIO10_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x54);
-
-        /// address: 0x40014058
-        /// GPIO status
-        pub const GPIO11_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x58);
-
-        /// address: 0x4001405c
-        /// GPIO control including function select and overrides.
-        pub const GPIO11_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x5c);
-
-        /// address: 0x40014060
-        /// GPIO status
-        pub const GPIO12_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x60);
-
-        /// address: 0x40014064
-        /// GPIO control including function select and overrides.
-        pub const GPIO12_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x64);
-
-        /// address: 0x40014068
-        /// GPIO status
-        pub const GPIO13_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x68);
-
-        /// address: 0x4001406c
-        /// GPIO control including function select and overrides.
-        pub const GPIO13_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x6c);
-
-        /// address: 0x40014070
-        /// GPIO status
-        pub const GPIO14_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x70);
-
-        /// address: 0x40014074
-        /// GPIO control including function select and overrides.
-        pub const GPIO14_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x74);
-
-        /// address: 0x40014078
-        /// GPIO status
-        pub const GPIO15_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x78);
-
-        /// address: 0x4001407c
-        /// GPIO control including function select and overrides.
-        pub const GPIO15_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x7c);
-
-        /// address: 0x40014080
-        /// GPIO status
-        pub const GPIO16_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x80);
-
-        /// address: 0x40014084
-        /// GPIO control including function select and overrides.
-        pub const GPIO16_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x84);
-
-        /// address: 0x40014088
-        /// GPIO status
-        pub const GPIO17_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x88);
-
-        /// address: 0x4001408c
-        /// GPIO control including function select and overrides.
-        pub const GPIO17_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x8c);
-
-        /// address: 0x40014090
-        /// GPIO status
-        pub const GPIO18_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x90);
-
-        /// address: 0x40014094
-        /// GPIO control including function select and overrides.
-        pub const GPIO18_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x94);
-
-        /// address: 0x40014098
-        /// GPIO status
-        pub const GPIO19_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x98);
-
-        /// address: 0x4001409c
-        /// GPIO control including function select and overrides.
-        pub const GPIO19_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x9c);
-
-        /// address: 0x400140a0
-        /// GPIO status
-        pub const GPIO20_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0xa0);
-
-        /// address: 0x400140a4
-        /// GPIO control including function select and overrides.
-        pub const GPIO20_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xa4);
-
-        /// address: 0x400140a8
-        /// GPIO status
-        pub const GPIO21_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0xa8);
-
-        /// address: 0x400140ac
-        /// GPIO control including function select and overrides.
-        pub const GPIO21_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xac);
-
-        /// address: 0x400140b0
-        /// GPIO status
-        pub const GPIO22_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0xb0);
-
-        /// address: 0x400140b4
-        /// GPIO control including function select and overrides.
-        pub const GPIO22_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xb4);
-
-        /// address: 0x400140b8
-        /// GPIO status
-        pub const GPIO23_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0xb8);
-
-        /// address: 0x400140bc
-        /// GPIO control including function select and overrides.
-        pub const GPIO23_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xbc);
-
-        /// address: 0x400140c0
-        /// GPIO status
-        pub const GPIO24_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0xc0);
-
-        /// address: 0x400140c4
-        /// GPIO control including function select and overrides.
-        pub const GPIO24_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xc4);
-
-        /// address: 0x400140c8
-        /// GPIO status
-        pub const GPIO25_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0xc8);
-
-        /// address: 0x400140cc
-        /// GPIO control including function select and overrides.
-        pub const GPIO25_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xcc);
-
-        /// address: 0x400140d0
-        /// GPIO status
-        pub const GPIO26_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0xd0);
-
-        /// address: 0x400140d4
-        /// GPIO control including function select and overrides.
-        pub const GPIO26_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xd4);
-
-        /// address: 0x400140d8
-        /// GPIO status
-        pub const GPIO27_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0xd8);
-
-        /// address: 0x400140dc
-        /// GPIO control including function select and overrides.
-        pub const GPIO27_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xdc);
-
-        /// address: 0x400140e0
-        /// GPIO status
-        pub const GPIO28_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0xe0);
-
-        /// address: 0x400140e4
-        /// GPIO control including function select and overrides.
-        pub const GPIO28_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xe4);
-
-        /// address: 0x400140e8
-        /// GPIO status
-        pub const GPIO29_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0xe8);
-
-        /// address: 0x400140ec
-        /// GPIO control including function select and overrides.
-        pub const GPIO29_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xec);
-
-        /// address: 0x400140f0
-        /// Raw Interrupts
-        pub const INTR0 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO0_LEVEL_LOW: u1,
-            GPIO0_LEVEL_HIGH: u1,
-            GPIO0_EDGE_LOW: u1,
-            GPIO0_EDGE_HIGH: u1,
-            GPIO1_LEVEL_LOW: u1,
-            GPIO1_LEVEL_HIGH: u1,
-            GPIO1_EDGE_LOW: u1,
-            GPIO1_EDGE_HIGH: u1,
-            GPIO2_LEVEL_LOW: u1,
-            GPIO2_LEVEL_HIGH: u1,
-            GPIO2_EDGE_LOW: u1,
-            GPIO2_EDGE_HIGH: u1,
-            GPIO3_LEVEL_LOW: u1,
-            GPIO3_LEVEL_HIGH: u1,
-            GPIO3_EDGE_LOW: u1,
-            GPIO3_EDGE_HIGH: u1,
-            GPIO4_LEVEL_LOW: u1,
-            GPIO4_LEVEL_HIGH: u1,
-            GPIO4_EDGE_LOW: u1,
-            GPIO4_EDGE_HIGH: u1,
-            GPIO5_LEVEL_LOW: u1,
-            GPIO5_LEVEL_HIGH: u1,
-            GPIO5_EDGE_LOW: u1,
-            GPIO5_EDGE_HIGH: u1,
-            GPIO6_LEVEL_LOW: u1,
-            GPIO6_LEVEL_HIGH: u1,
-            GPIO6_EDGE_LOW: u1,
-            GPIO6_EDGE_HIGH: u1,
-            GPIO7_LEVEL_LOW: u1,
-            GPIO7_LEVEL_HIGH: u1,
-            GPIO7_EDGE_LOW: u1,
-            GPIO7_EDGE_HIGH: u1,
-        }), base_address + 0xf0);
-
-        /// address: 0x400140f4
-        /// Raw Interrupts
-        pub const INTR1 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO8_LEVEL_LOW: u1,
-            GPIO8_LEVEL_HIGH: u1,
-            GPIO8_EDGE_LOW: u1,
-            GPIO8_EDGE_HIGH: u1,
-            GPIO9_LEVEL_LOW: u1,
-            GPIO9_LEVEL_HIGH: u1,
-            GPIO9_EDGE_LOW: u1,
-            GPIO9_EDGE_HIGH: u1,
-            GPIO10_LEVEL_LOW: u1,
-            GPIO10_LEVEL_HIGH: u1,
-            GPIO10_EDGE_LOW: u1,
-            GPIO10_EDGE_HIGH: u1,
-            GPIO11_LEVEL_LOW: u1,
-            GPIO11_LEVEL_HIGH: u1,
-            GPIO11_EDGE_LOW: u1,
-            GPIO11_EDGE_HIGH: u1,
-            GPIO12_LEVEL_LOW: u1,
-            GPIO12_LEVEL_HIGH: u1,
-            GPIO12_EDGE_LOW: u1,
-            GPIO12_EDGE_HIGH: u1,
-            GPIO13_LEVEL_LOW: u1,
-            GPIO13_LEVEL_HIGH: u1,
-            GPIO13_EDGE_LOW: u1,
-            GPIO13_EDGE_HIGH: u1,
-            GPIO14_LEVEL_LOW: u1,
-            GPIO14_LEVEL_HIGH: u1,
-            GPIO14_EDGE_LOW: u1,
-            GPIO14_EDGE_HIGH: u1,
-            GPIO15_LEVEL_LOW: u1,
-            GPIO15_LEVEL_HIGH: u1,
-            GPIO15_EDGE_LOW: u1,
-            GPIO15_EDGE_HIGH: u1,
-        }), base_address + 0xf4);
-
-        /// address: 0x400140f8
-        /// Raw Interrupts
-        pub const INTR2 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO16_LEVEL_LOW: u1,
-            GPIO16_LEVEL_HIGH: u1,
-            GPIO16_EDGE_LOW: u1,
-            GPIO16_EDGE_HIGH: u1,
-            GPIO17_LEVEL_LOW: u1,
-            GPIO17_LEVEL_HIGH: u1,
-            GPIO17_EDGE_LOW: u1,
-            GPIO17_EDGE_HIGH: u1,
-            GPIO18_LEVEL_LOW: u1,
-            GPIO18_LEVEL_HIGH: u1,
-            GPIO18_EDGE_LOW: u1,
-            GPIO18_EDGE_HIGH: u1,
-            GPIO19_LEVEL_LOW: u1,
-            GPIO19_LEVEL_HIGH: u1,
-            GPIO19_EDGE_LOW: u1,
-            GPIO19_EDGE_HIGH: u1,
-            GPIO20_LEVEL_LOW: u1,
-            GPIO20_LEVEL_HIGH: u1,
-            GPIO20_EDGE_LOW: u1,
-            GPIO20_EDGE_HIGH: u1,
-            GPIO21_LEVEL_LOW: u1,
-            GPIO21_LEVEL_HIGH: u1,
-            GPIO21_EDGE_LOW: u1,
-            GPIO21_EDGE_HIGH: u1,
-            GPIO22_LEVEL_LOW: u1,
-            GPIO22_LEVEL_HIGH: u1,
-            GPIO22_EDGE_LOW: u1,
-            GPIO22_EDGE_HIGH: u1,
-            GPIO23_LEVEL_LOW: u1,
-            GPIO23_LEVEL_HIGH: u1,
-            GPIO23_EDGE_LOW: u1,
-            GPIO23_EDGE_HIGH: u1,
-        }), base_address + 0xf8);
-
-        /// address: 0x400140fc
-        /// Raw Interrupts
-        pub const INTR3 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO24_LEVEL_LOW: u1,
-            GPIO24_LEVEL_HIGH: u1,
-            GPIO24_EDGE_LOW: u1,
-            GPIO24_EDGE_HIGH: u1,
-            GPIO25_LEVEL_LOW: u1,
-            GPIO25_LEVEL_HIGH: u1,
-            GPIO25_EDGE_LOW: u1,
-            GPIO25_EDGE_HIGH: u1,
-            GPIO26_LEVEL_LOW: u1,
-            GPIO26_LEVEL_HIGH: u1,
-            GPIO26_EDGE_LOW: u1,
-            GPIO26_EDGE_HIGH: u1,
-            GPIO27_LEVEL_LOW: u1,
-            GPIO27_LEVEL_HIGH: u1,
-            GPIO27_EDGE_LOW: u1,
-            GPIO27_EDGE_HIGH: u1,
-            GPIO28_LEVEL_LOW: u1,
-            GPIO28_LEVEL_HIGH: u1,
-            GPIO28_EDGE_LOW: u1,
-            GPIO28_EDGE_HIGH: u1,
-            GPIO29_LEVEL_LOW: u1,
-            GPIO29_LEVEL_HIGH: u1,
-            GPIO29_EDGE_LOW: u1,
-            GPIO29_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0xfc);
-
-        /// address: 0x40014100
-        /// Interrupt Enable for proc0
-        pub const PROC0_INTE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO0_LEVEL_LOW: u1,
-            GPIO0_LEVEL_HIGH: u1,
-            GPIO0_EDGE_LOW: u1,
-            GPIO0_EDGE_HIGH: u1,
-            GPIO1_LEVEL_LOW: u1,
-            GPIO1_LEVEL_HIGH: u1,
-            GPIO1_EDGE_LOW: u1,
-            GPIO1_EDGE_HIGH: u1,
-            GPIO2_LEVEL_LOW: u1,
-            GPIO2_LEVEL_HIGH: u1,
-            GPIO2_EDGE_LOW: u1,
-            GPIO2_EDGE_HIGH: u1,
-            GPIO3_LEVEL_LOW: u1,
-            GPIO3_LEVEL_HIGH: u1,
-            GPIO3_EDGE_LOW: u1,
-            GPIO3_EDGE_HIGH: u1,
-            GPIO4_LEVEL_LOW: u1,
-            GPIO4_LEVEL_HIGH: u1,
-            GPIO4_EDGE_LOW: u1,
-            GPIO4_EDGE_HIGH: u1,
-            GPIO5_LEVEL_LOW: u1,
-            GPIO5_LEVEL_HIGH: u1,
-            GPIO5_EDGE_LOW: u1,
-            GPIO5_EDGE_HIGH: u1,
-            GPIO6_LEVEL_LOW: u1,
-            GPIO6_LEVEL_HIGH: u1,
-            GPIO6_EDGE_LOW: u1,
-            GPIO6_EDGE_HIGH: u1,
-            GPIO7_LEVEL_LOW: u1,
-            GPIO7_LEVEL_HIGH: u1,
-            GPIO7_EDGE_LOW: u1,
-            GPIO7_EDGE_HIGH: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x40014104
-        /// Interrupt Enable for proc0
-        pub const PROC0_INTE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO8_LEVEL_LOW: u1,
-            GPIO8_LEVEL_HIGH: u1,
-            GPIO8_EDGE_LOW: u1,
-            GPIO8_EDGE_HIGH: u1,
-            GPIO9_LEVEL_LOW: u1,
-            GPIO9_LEVEL_HIGH: u1,
-            GPIO9_EDGE_LOW: u1,
-            GPIO9_EDGE_HIGH: u1,
-            GPIO10_LEVEL_LOW: u1,
-            GPIO10_LEVEL_HIGH: u1,
-            GPIO10_EDGE_LOW: u1,
-            GPIO10_EDGE_HIGH: u1,
-            GPIO11_LEVEL_LOW: u1,
-            GPIO11_LEVEL_HIGH: u1,
-            GPIO11_EDGE_LOW: u1,
-            GPIO11_EDGE_HIGH: u1,
-            GPIO12_LEVEL_LOW: u1,
-            GPIO12_LEVEL_HIGH: u1,
-            GPIO12_EDGE_LOW: u1,
-            GPIO12_EDGE_HIGH: u1,
-            GPIO13_LEVEL_LOW: u1,
-            GPIO13_LEVEL_HIGH: u1,
-            GPIO13_EDGE_LOW: u1,
-            GPIO13_EDGE_HIGH: u1,
-            GPIO14_LEVEL_LOW: u1,
-            GPIO14_LEVEL_HIGH: u1,
-            GPIO14_EDGE_LOW: u1,
-            GPIO14_EDGE_HIGH: u1,
-            GPIO15_LEVEL_LOW: u1,
-            GPIO15_LEVEL_HIGH: u1,
-            GPIO15_EDGE_LOW: u1,
-            GPIO15_EDGE_HIGH: u1,
-        }), base_address + 0x104);
-
-        /// address: 0x40014108
-        /// Interrupt Enable for proc0
-        pub const PROC0_INTE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO16_LEVEL_LOW: u1,
-            GPIO16_LEVEL_HIGH: u1,
-            GPIO16_EDGE_LOW: u1,
-            GPIO16_EDGE_HIGH: u1,
-            GPIO17_LEVEL_LOW: u1,
-            GPIO17_LEVEL_HIGH: u1,
-            GPIO17_EDGE_LOW: u1,
-            GPIO17_EDGE_HIGH: u1,
-            GPIO18_LEVEL_LOW: u1,
-            GPIO18_LEVEL_HIGH: u1,
-            GPIO18_EDGE_LOW: u1,
-            GPIO18_EDGE_HIGH: u1,
-            GPIO19_LEVEL_LOW: u1,
-            GPIO19_LEVEL_HIGH: u1,
-            GPIO19_EDGE_LOW: u1,
-            GPIO19_EDGE_HIGH: u1,
-            GPIO20_LEVEL_LOW: u1,
-            GPIO20_LEVEL_HIGH: u1,
-            GPIO20_EDGE_LOW: u1,
-            GPIO20_EDGE_HIGH: u1,
-            GPIO21_LEVEL_LOW: u1,
-            GPIO21_LEVEL_HIGH: u1,
-            GPIO21_EDGE_LOW: u1,
-            GPIO21_EDGE_HIGH: u1,
-            GPIO22_LEVEL_LOW: u1,
-            GPIO22_LEVEL_HIGH: u1,
-            GPIO22_EDGE_LOW: u1,
-            GPIO22_EDGE_HIGH: u1,
-            GPIO23_LEVEL_LOW: u1,
-            GPIO23_LEVEL_HIGH: u1,
-            GPIO23_EDGE_LOW: u1,
-            GPIO23_EDGE_HIGH: u1,
-        }), base_address + 0x108);
-
-        /// address: 0x4001410c
-        /// Interrupt Enable for proc0
-        pub const PROC0_INTE3 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO24_LEVEL_LOW: u1,
-            GPIO24_LEVEL_HIGH: u1,
-            GPIO24_EDGE_LOW: u1,
-            GPIO24_EDGE_HIGH: u1,
-            GPIO25_LEVEL_LOW: u1,
-            GPIO25_LEVEL_HIGH: u1,
-            GPIO25_EDGE_LOW: u1,
-            GPIO25_EDGE_HIGH: u1,
-            GPIO26_LEVEL_LOW: u1,
-            GPIO26_LEVEL_HIGH: u1,
-            GPIO26_EDGE_LOW: u1,
-            GPIO26_EDGE_HIGH: u1,
-            GPIO27_LEVEL_LOW: u1,
-            GPIO27_LEVEL_HIGH: u1,
-            GPIO27_EDGE_LOW: u1,
-            GPIO27_EDGE_HIGH: u1,
-            GPIO28_LEVEL_LOW: u1,
-            GPIO28_LEVEL_HIGH: u1,
-            GPIO28_EDGE_LOW: u1,
-            GPIO28_EDGE_HIGH: u1,
-            GPIO29_LEVEL_LOW: u1,
-            GPIO29_LEVEL_HIGH: u1,
-            GPIO29_EDGE_LOW: u1,
-            GPIO29_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x10c);
-
-        /// address: 0x40014110
-        /// Interrupt Force for proc0
-        pub const PROC0_INTF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO0_LEVEL_LOW: u1,
-            GPIO0_LEVEL_HIGH: u1,
-            GPIO0_EDGE_LOW: u1,
-            GPIO0_EDGE_HIGH: u1,
-            GPIO1_LEVEL_LOW: u1,
-            GPIO1_LEVEL_HIGH: u1,
-            GPIO1_EDGE_LOW: u1,
-            GPIO1_EDGE_HIGH: u1,
-            GPIO2_LEVEL_LOW: u1,
-            GPIO2_LEVEL_HIGH: u1,
-            GPIO2_EDGE_LOW: u1,
-            GPIO2_EDGE_HIGH: u1,
-            GPIO3_LEVEL_LOW: u1,
-            GPIO3_LEVEL_HIGH: u1,
-            GPIO3_EDGE_LOW: u1,
-            GPIO3_EDGE_HIGH: u1,
-            GPIO4_LEVEL_LOW: u1,
-            GPIO4_LEVEL_HIGH: u1,
-            GPIO4_EDGE_LOW: u1,
-            GPIO4_EDGE_HIGH: u1,
-            GPIO5_LEVEL_LOW: u1,
-            GPIO5_LEVEL_HIGH: u1,
-            GPIO5_EDGE_LOW: u1,
-            GPIO5_EDGE_HIGH: u1,
-            GPIO6_LEVEL_LOW: u1,
-            GPIO6_LEVEL_HIGH: u1,
-            GPIO6_EDGE_LOW: u1,
-            GPIO6_EDGE_HIGH: u1,
-            GPIO7_LEVEL_LOW: u1,
-            GPIO7_LEVEL_HIGH: u1,
-            GPIO7_EDGE_LOW: u1,
-            GPIO7_EDGE_HIGH: u1,
-        }), base_address + 0x110);
-
-        /// address: 0x40014114
-        /// Interrupt Force for proc0
-        pub const PROC0_INTF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO8_LEVEL_LOW: u1,
-            GPIO8_LEVEL_HIGH: u1,
-            GPIO8_EDGE_LOW: u1,
-            GPIO8_EDGE_HIGH: u1,
-            GPIO9_LEVEL_LOW: u1,
-            GPIO9_LEVEL_HIGH: u1,
-            GPIO9_EDGE_LOW: u1,
-            GPIO9_EDGE_HIGH: u1,
-            GPIO10_LEVEL_LOW: u1,
-            GPIO10_LEVEL_HIGH: u1,
-            GPIO10_EDGE_LOW: u1,
-            GPIO10_EDGE_HIGH: u1,
-            GPIO11_LEVEL_LOW: u1,
-            GPIO11_LEVEL_HIGH: u1,
-            GPIO11_EDGE_LOW: u1,
-            GPIO11_EDGE_HIGH: u1,
-            GPIO12_LEVEL_LOW: u1,
-            GPIO12_LEVEL_HIGH: u1,
-            GPIO12_EDGE_LOW: u1,
-            GPIO12_EDGE_HIGH: u1,
-            GPIO13_LEVEL_LOW: u1,
-            GPIO13_LEVEL_HIGH: u1,
-            GPIO13_EDGE_LOW: u1,
-            GPIO13_EDGE_HIGH: u1,
-            GPIO14_LEVEL_LOW: u1,
-            GPIO14_LEVEL_HIGH: u1,
-            GPIO14_EDGE_LOW: u1,
-            GPIO14_EDGE_HIGH: u1,
-            GPIO15_LEVEL_LOW: u1,
-            GPIO15_LEVEL_HIGH: u1,
-            GPIO15_EDGE_LOW: u1,
-            GPIO15_EDGE_HIGH: u1,
-        }), base_address + 0x114);
-
-        /// address: 0x40014118
-        /// Interrupt Force for proc0
-        pub const PROC0_INTF2 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO16_LEVEL_LOW: u1,
-            GPIO16_LEVEL_HIGH: u1,
-            GPIO16_EDGE_LOW: u1,
-            GPIO16_EDGE_HIGH: u1,
-            GPIO17_LEVEL_LOW: u1,
-            GPIO17_LEVEL_HIGH: u1,
-            GPIO17_EDGE_LOW: u1,
-            GPIO17_EDGE_HIGH: u1,
-            GPIO18_LEVEL_LOW: u1,
-            GPIO18_LEVEL_HIGH: u1,
-            GPIO18_EDGE_LOW: u1,
-            GPIO18_EDGE_HIGH: u1,
-            GPIO19_LEVEL_LOW: u1,
-            GPIO19_LEVEL_HIGH: u1,
-            GPIO19_EDGE_LOW: u1,
-            GPIO19_EDGE_HIGH: u1,
-            GPIO20_LEVEL_LOW: u1,
-            GPIO20_LEVEL_HIGH: u1,
-            GPIO20_EDGE_LOW: u1,
-            GPIO20_EDGE_HIGH: u1,
-            GPIO21_LEVEL_LOW: u1,
-            GPIO21_LEVEL_HIGH: u1,
-            GPIO21_EDGE_LOW: u1,
-            GPIO21_EDGE_HIGH: u1,
-            GPIO22_LEVEL_LOW: u1,
-            GPIO22_LEVEL_HIGH: u1,
-            GPIO22_EDGE_LOW: u1,
-            GPIO22_EDGE_HIGH: u1,
-            GPIO23_LEVEL_LOW: u1,
-            GPIO23_LEVEL_HIGH: u1,
-            GPIO23_EDGE_LOW: u1,
-            GPIO23_EDGE_HIGH: u1,
-        }), base_address + 0x118);
-
-        /// address: 0x4001411c
-        /// Interrupt Force for proc0
-        pub const PROC0_INTF3 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO24_LEVEL_LOW: u1,
-            GPIO24_LEVEL_HIGH: u1,
-            GPIO24_EDGE_LOW: u1,
-            GPIO24_EDGE_HIGH: u1,
-            GPIO25_LEVEL_LOW: u1,
-            GPIO25_LEVEL_HIGH: u1,
-            GPIO25_EDGE_LOW: u1,
-            GPIO25_EDGE_HIGH: u1,
-            GPIO26_LEVEL_LOW: u1,
-            GPIO26_LEVEL_HIGH: u1,
-            GPIO26_EDGE_LOW: u1,
-            GPIO26_EDGE_HIGH: u1,
-            GPIO27_LEVEL_LOW: u1,
-            GPIO27_LEVEL_HIGH: u1,
-            GPIO27_EDGE_LOW: u1,
-            GPIO27_EDGE_HIGH: u1,
-            GPIO28_LEVEL_LOW: u1,
-            GPIO28_LEVEL_HIGH: u1,
-            GPIO28_EDGE_LOW: u1,
-            GPIO28_EDGE_HIGH: u1,
-            GPIO29_LEVEL_LOW: u1,
-            GPIO29_LEVEL_HIGH: u1,
-            GPIO29_EDGE_LOW: u1,
-            GPIO29_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x11c);
-
-        /// address: 0x40014120
-        /// Interrupt status after masking & forcing for proc0
-        pub const PROC0_INTS0 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO0_LEVEL_LOW: u1,
-            GPIO0_LEVEL_HIGH: u1,
-            GPIO0_EDGE_LOW: u1,
-            GPIO0_EDGE_HIGH: u1,
-            GPIO1_LEVEL_LOW: u1,
-            GPIO1_LEVEL_HIGH: u1,
-            GPIO1_EDGE_LOW: u1,
-            GPIO1_EDGE_HIGH: u1,
-            GPIO2_LEVEL_LOW: u1,
-            GPIO2_LEVEL_HIGH: u1,
-            GPIO2_EDGE_LOW: u1,
-            GPIO2_EDGE_HIGH: u1,
-            GPIO3_LEVEL_LOW: u1,
-            GPIO3_LEVEL_HIGH: u1,
-            GPIO3_EDGE_LOW: u1,
-            GPIO3_EDGE_HIGH: u1,
-            GPIO4_LEVEL_LOW: u1,
-            GPIO4_LEVEL_HIGH: u1,
-            GPIO4_EDGE_LOW: u1,
-            GPIO4_EDGE_HIGH: u1,
-            GPIO5_LEVEL_LOW: u1,
-            GPIO5_LEVEL_HIGH: u1,
-            GPIO5_EDGE_LOW: u1,
-            GPIO5_EDGE_HIGH: u1,
-            GPIO6_LEVEL_LOW: u1,
-            GPIO6_LEVEL_HIGH: u1,
-            GPIO6_EDGE_LOW: u1,
-            GPIO6_EDGE_HIGH: u1,
-            GPIO7_LEVEL_LOW: u1,
-            GPIO7_LEVEL_HIGH: u1,
-            GPIO7_EDGE_LOW: u1,
-            GPIO7_EDGE_HIGH: u1,
-        }), base_address + 0x120);
-
-        /// address: 0x40014124
-        /// Interrupt status after masking & forcing for proc0
-        pub const PROC0_INTS1 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO8_LEVEL_LOW: u1,
-            GPIO8_LEVEL_HIGH: u1,
-            GPIO8_EDGE_LOW: u1,
-            GPIO8_EDGE_HIGH: u1,
-            GPIO9_LEVEL_LOW: u1,
-            GPIO9_LEVEL_HIGH: u1,
-            GPIO9_EDGE_LOW: u1,
-            GPIO9_EDGE_HIGH: u1,
-            GPIO10_LEVEL_LOW: u1,
-            GPIO10_LEVEL_HIGH: u1,
-            GPIO10_EDGE_LOW: u1,
-            GPIO10_EDGE_HIGH: u1,
-            GPIO11_LEVEL_LOW: u1,
-            GPIO11_LEVEL_HIGH: u1,
-            GPIO11_EDGE_LOW: u1,
-            GPIO11_EDGE_HIGH: u1,
-            GPIO12_LEVEL_LOW: u1,
-            GPIO12_LEVEL_HIGH: u1,
-            GPIO12_EDGE_LOW: u1,
-            GPIO12_EDGE_HIGH: u1,
-            GPIO13_LEVEL_LOW: u1,
-            GPIO13_LEVEL_HIGH: u1,
-            GPIO13_EDGE_LOW: u1,
-            GPIO13_EDGE_HIGH: u1,
-            GPIO14_LEVEL_LOW: u1,
-            GPIO14_LEVEL_HIGH: u1,
-            GPIO14_EDGE_LOW: u1,
-            GPIO14_EDGE_HIGH: u1,
-            GPIO15_LEVEL_LOW: u1,
-            GPIO15_LEVEL_HIGH: u1,
-            GPIO15_EDGE_LOW: u1,
-            GPIO15_EDGE_HIGH: u1,
-        }), base_address + 0x124);
-
-        /// address: 0x40014128
-        /// Interrupt status after masking & forcing for proc0
-        pub const PROC0_INTS2 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO16_LEVEL_LOW: u1,
-            GPIO16_LEVEL_HIGH: u1,
-            GPIO16_EDGE_LOW: u1,
-            GPIO16_EDGE_HIGH: u1,
-            GPIO17_LEVEL_LOW: u1,
-            GPIO17_LEVEL_HIGH: u1,
-            GPIO17_EDGE_LOW: u1,
-            GPIO17_EDGE_HIGH: u1,
-            GPIO18_LEVEL_LOW: u1,
-            GPIO18_LEVEL_HIGH: u1,
-            GPIO18_EDGE_LOW: u1,
-            GPIO18_EDGE_HIGH: u1,
-            GPIO19_LEVEL_LOW: u1,
-            GPIO19_LEVEL_HIGH: u1,
-            GPIO19_EDGE_LOW: u1,
-            GPIO19_EDGE_HIGH: u1,
-            GPIO20_LEVEL_LOW: u1,
-            GPIO20_LEVEL_HIGH: u1,
-            GPIO20_EDGE_LOW: u1,
-            GPIO20_EDGE_HIGH: u1,
-            GPIO21_LEVEL_LOW: u1,
-            GPIO21_LEVEL_HIGH: u1,
-            GPIO21_EDGE_LOW: u1,
-            GPIO21_EDGE_HIGH: u1,
-            GPIO22_LEVEL_LOW: u1,
-            GPIO22_LEVEL_HIGH: u1,
-            GPIO22_EDGE_LOW: u1,
-            GPIO22_EDGE_HIGH: u1,
-            GPIO23_LEVEL_LOW: u1,
-            GPIO23_LEVEL_HIGH: u1,
-            GPIO23_EDGE_LOW: u1,
-            GPIO23_EDGE_HIGH: u1,
-        }), base_address + 0x128);
-
-        /// address: 0x4001412c
-        /// Interrupt status after masking & forcing for proc0
-        pub const PROC0_INTS3 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO24_LEVEL_LOW: u1,
-            GPIO24_LEVEL_HIGH: u1,
-            GPIO24_EDGE_LOW: u1,
-            GPIO24_EDGE_HIGH: u1,
-            GPIO25_LEVEL_LOW: u1,
-            GPIO25_LEVEL_HIGH: u1,
-            GPIO25_EDGE_LOW: u1,
-            GPIO25_EDGE_HIGH: u1,
-            GPIO26_LEVEL_LOW: u1,
-            GPIO26_LEVEL_HIGH: u1,
-            GPIO26_EDGE_LOW: u1,
-            GPIO26_EDGE_HIGH: u1,
-            GPIO27_LEVEL_LOW: u1,
-            GPIO27_LEVEL_HIGH: u1,
-            GPIO27_EDGE_LOW: u1,
-            GPIO27_EDGE_HIGH: u1,
-            GPIO28_LEVEL_LOW: u1,
-            GPIO28_LEVEL_HIGH: u1,
-            GPIO28_EDGE_LOW: u1,
-            GPIO28_EDGE_HIGH: u1,
-            GPIO29_LEVEL_LOW: u1,
-            GPIO29_LEVEL_HIGH: u1,
-            GPIO29_EDGE_LOW: u1,
-            GPIO29_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x12c);
-
-        /// address: 0x40014130
-        /// Interrupt Enable for proc1
-        pub const PROC1_INTE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO0_LEVEL_LOW: u1,
-            GPIO0_LEVEL_HIGH: u1,
-            GPIO0_EDGE_LOW: u1,
-            GPIO0_EDGE_HIGH: u1,
-            GPIO1_LEVEL_LOW: u1,
-            GPIO1_LEVEL_HIGH: u1,
-            GPIO1_EDGE_LOW: u1,
-            GPIO1_EDGE_HIGH: u1,
-            GPIO2_LEVEL_LOW: u1,
-            GPIO2_LEVEL_HIGH: u1,
-            GPIO2_EDGE_LOW: u1,
-            GPIO2_EDGE_HIGH: u1,
-            GPIO3_LEVEL_LOW: u1,
-            GPIO3_LEVEL_HIGH: u1,
-            GPIO3_EDGE_LOW: u1,
-            GPIO3_EDGE_HIGH: u1,
-            GPIO4_LEVEL_LOW: u1,
-            GPIO4_LEVEL_HIGH: u1,
-            GPIO4_EDGE_LOW: u1,
-            GPIO4_EDGE_HIGH: u1,
-            GPIO5_LEVEL_LOW: u1,
-            GPIO5_LEVEL_HIGH: u1,
-            GPIO5_EDGE_LOW: u1,
-            GPIO5_EDGE_HIGH: u1,
-            GPIO6_LEVEL_LOW: u1,
-            GPIO6_LEVEL_HIGH: u1,
-            GPIO6_EDGE_LOW: u1,
-            GPIO6_EDGE_HIGH: u1,
-            GPIO7_LEVEL_LOW: u1,
-            GPIO7_LEVEL_HIGH: u1,
-            GPIO7_EDGE_LOW: u1,
-            GPIO7_EDGE_HIGH: u1,
-        }), base_address + 0x130);
-
-        /// address: 0x40014134
-        /// Interrupt Enable for proc1
-        pub const PROC1_INTE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO8_LEVEL_LOW: u1,
-            GPIO8_LEVEL_HIGH: u1,
-            GPIO8_EDGE_LOW: u1,
-            GPIO8_EDGE_HIGH: u1,
-            GPIO9_LEVEL_LOW: u1,
-            GPIO9_LEVEL_HIGH: u1,
-            GPIO9_EDGE_LOW: u1,
-            GPIO9_EDGE_HIGH: u1,
-            GPIO10_LEVEL_LOW: u1,
-            GPIO10_LEVEL_HIGH: u1,
-            GPIO10_EDGE_LOW: u1,
-            GPIO10_EDGE_HIGH: u1,
-            GPIO11_LEVEL_LOW: u1,
-            GPIO11_LEVEL_HIGH: u1,
-            GPIO11_EDGE_LOW: u1,
-            GPIO11_EDGE_HIGH: u1,
-            GPIO12_LEVEL_LOW: u1,
-            GPIO12_LEVEL_HIGH: u1,
-            GPIO12_EDGE_LOW: u1,
-            GPIO12_EDGE_HIGH: u1,
-            GPIO13_LEVEL_LOW: u1,
-            GPIO13_LEVEL_HIGH: u1,
-            GPIO13_EDGE_LOW: u1,
-            GPIO13_EDGE_HIGH: u1,
-            GPIO14_LEVEL_LOW: u1,
-            GPIO14_LEVEL_HIGH: u1,
-            GPIO14_EDGE_LOW: u1,
-            GPIO14_EDGE_HIGH: u1,
-            GPIO15_LEVEL_LOW: u1,
-            GPIO15_LEVEL_HIGH: u1,
-            GPIO15_EDGE_LOW: u1,
-            GPIO15_EDGE_HIGH: u1,
-        }), base_address + 0x134);
-
-        /// address: 0x40014138
-        /// Interrupt Enable for proc1
-        pub const PROC1_INTE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO16_LEVEL_LOW: u1,
-            GPIO16_LEVEL_HIGH: u1,
-            GPIO16_EDGE_LOW: u1,
-            GPIO16_EDGE_HIGH: u1,
-            GPIO17_LEVEL_LOW: u1,
-            GPIO17_LEVEL_HIGH: u1,
-            GPIO17_EDGE_LOW: u1,
-            GPIO17_EDGE_HIGH: u1,
-            GPIO18_LEVEL_LOW: u1,
-            GPIO18_LEVEL_HIGH: u1,
-            GPIO18_EDGE_LOW: u1,
-            GPIO18_EDGE_HIGH: u1,
-            GPIO19_LEVEL_LOW: u1,
-            GPIO19_LEVEL_HIGH: u1,
-            GPIO19_EDGE_LOW: u1,
-            GPIO19_EDGE_HIGH: u1,
-            GPIO20_LEVEL_LOW: u1,
-            GPIO20_LEVEL_HIGH: u1,
-            GPIO20_EDGE_LOW: u1,
-            GPIO20_EDGE_HIGH: u1,
-            GPIO21_LEVEL_LOW: u1,
-            GPIO21_LEVEL_HIGH: u1,
-            GPIO21_EDGE_LOW: u1,
-            GPIO21_EDGE_HIGH: u1,
-            GPIO22_LEVEL_LOW: u1,
-            GPIO22_LEVEL_HIGH: u1,
-            GPIO22_EDGE_LOW: u1,
-            GPIO22_EDGE_HIGH: u1,
-            GPIO23_LEVEL_LOW: u1,
-            GPIO23_LEVEL_HIGH: u1,
-            GPIO23_EDGE_LOW: u1,
-            GPIO23_EDGE_HIGH: u1,
-        }), base_address + 0x138);
-
-        /// address: 0x4001413c
-        /// Interrupt Enable for proc1
-        pub const PROC1_INTE3 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO24_LEVEL_LOW: u1,
-            GPIO24_LEVEL_HIGH: u1,
-            GPIO24_EDGE_LOW: u1,
-            GPIO24_EDGE_HIGH: u1,
-            GPIO25_LEVEL_LOW: u1,
-            GPIO25_LEVEL_HIGH: u1,
-            GPIO25_EDGE_LOW: u1,
-            GPIO25_EDGE_HIGH: u1,
-            GPIO26_LEVEL_LOW: u1,
-            GPIO26_LEVEL_HIGH: u1,
-            GPIO26_EDGE_LOW: u1,
-            GPIO26_EDGE_HIGH: u1,
-            GPIO27_LEVEL_LOW: u1,
-            GPIO27_LEVEL_HIGH: u1,
-            GPIO27_EDGE_LOW: u1,
-            GPIO27_EDGE_HIGH: u1,
-            GPIO28_LEVEL_LOW: u1,
-            GPIO28_LEVEL_HIGH: u1,
-            GPIO28_EDGE_LOW: u1,
-            GPIO28_EDGE_HIGH: u1,
-            GPIO29_LEVEL_LOW: u1,
-            GPIO29_LEVEL_HIGH: u1,
-            GPIO29_EDGE_LOW: u1,
-            GPIO29_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x13c);
-
-        /// address: 0x40014140
-        /// Interrupt Force for proc1
-        pub const PROC1_INTF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO0_LEVEL_LOW: u1,
-            GPIO0_LEVEL_HIGH: u1,
-            GPIO0_EDGE_LOW: u1,
-            GPIO0_EDGE_HIGH: u1,
-            GPIO1_LEVEL_LOW: u1,
-            GPIO1_LEVEL_HIGH: u1,
-            GPIO1_EDGE_LOW: u1,
-            GPIO1_EDGE_HIGH: u1,
-            GPIO2_LEVEL_LOW: u1,
-            GPIO2_LEVEL_HIGH: u1,
-            GPIO2_EDGE_LOW: u1,
-            GPIO2_EDGE_HIGH: u1,
-            GPIO3_LEVEL_LOW: u1,
-            GPIO3_LEVEL_HIGH: u1,
-            GPIO3_EDGE_LOW: u1,
-            GPIO3_EDGE_HIGH: u1,
-            GPIO4_LEVEL_LOW: u1,
-            GPIO4_LEVEL_HIGH: u1,
-            GPIO4_EDGE_LOW: u1,
-            GPIO4_EDGE_HIGH: u1,
-            GPIO5_LEVEL_LOW: u1,
-            GPIO5_LEVEL_HIGH: u1,
-            GPIO5_EDGE_LOW: u1,
-            GPIO5_EDGE_HIGH: u1,
-            GPIO6_LEVEL_LOW: u1,
-            GPIO6_LEVEL_HIGH: u1,
-            GPIO6_EDGE_LOW: u1,
-            GPIO6_EDGE_HIGH: u1,
-            GPIO7_LEVEL_LOW: u1,
-            GPIO7_LEVEL_HIGH: u1,
-            GPIO7_EDGE_LOW: u1,
-            GPIO7_EDGE_HIGH: u1,
-        }), base_address + 0x140);
-
-        /// address: 0x40014144
-        /// Interrupt Force for proc1
-        pub const PROC1_INTF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO8_LEVEL_LOW: u1,
-            GPIO8_LEVEL_HIGH: u1,
-            GPIO8_EDGE_LOW: u1,
-            GPIO8_EDGE_HIGH: u1,
-            GPIO9_LEVEL_LOW: u1,
-            GPIO9_LEVEL_HIGH: u1,
-            GPIO9_EDGE_LOW: u1,
-            GPIO9_EDGE_HIGH: u1,
-            GPIO10_LEVEL_LOW: u1,
-            GPIO10_LEVEL_HIGH: u1,
-            GPIO10_EDGE_LOW: u1,
-            GPIO10_EDGE_HIGH: u1,
-            GPIO11_LEVEL_LOW: u1,
-            GPIO11_LEVEL_HIGH: u1,
-            GPIO11_EDGE_LOW: u1,
-            GPIO11_EDGE_HIGH: u1,
-            GPIO12_LEVEL_LOW: u1,
-            GPIO12_LEVEL_HIGH: u1,
-            GPIO12_EDGE_LOW: u1,
-            GPIO12_EDGE_HIGH: u1,
-            GPIO13_LEVEL_LOW: u1,
-            GPIO13_LEVEL_HIGH: u1,
-            GPIO13_EDGE_LOW: u1,
-            GPIO13_EDGE_HIGH: u1,
-            GPIO14_LEVEL_LOW: u1,
-            GPIO14_LEVEL_HIGH: u1,
-            GPIO14_EDGE_LOW: u1,
-            GPIO14_EDGE_HIGH: u1,
-            GPIO15_LEVEL_LOW: u1,
-            GPIO15_LEVEL_HIGH: u1,
-            GPIO15_EDGE_LOW: u1,
-            GPIO15_EDGE_HIGH: u1,
-        }), base_address + 0x144);
-
-        /// address: 0x40014148
-        /// Interrupt Force for proc1
-        pub const PROC1_INTF2 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO16_LEVEL_LOW: u1,
-            GPIO16_LEVEL_HIGH: u1,
-            GPIO16_EDGE_LOW: u1,
-            GPIO16_EDGE_HIGH: u1,
-            GPIO17_LEVEL_LOW: u1,
-            GPIO17_LEVEL_HIGH: u1,
-            GPIO17_EDGE_LOW: u1,
-            GPIO17_EDGE_HIGH: u1,
-            GPIO18_LEVEL_LOW: u1,
-            GPIO18_LEVEL_HIGH: u1,
-            GPIO18_EDGE_LOW: u1,
-            GPIO18_EDGE_HIGH: u1,
-            GPIO19_LEVEL_LOW: u1,
-            GPIO19_LEVEL_HIGH: u1,
-            GPIO19_EDGE_LOW: u1,
-            GPIO19_EDGE_HIGH: u1,
-            GPIO20_LEVEL_LOW: u1,
-            GPIO20_LEVEL_HIGH: u1,
-            GPIO20_EDGE_LOW: u1,
-            GPIO20_EDGE_HIGH: u1,
-            GPIO21_LEVEL_LOW: u1,
-            GPIO21_LEVEL_HIGH: u1,
-            GPIO21_EDGE_LOW: u1,
-            GPIO21_EDGE_HIGH: u1,
-            GPIO22_LEVEL_LOW: u1,
-            GPIO22_LEVEL_HIGH: u1,
-            GPIO22_EDGE_LOW: u1,
-            GPIO22_EDGE_HIGH: u1,
-            GPIO23_LEVEL_LOW: u1,
-            GPIO23_LEVEL_HIGH: u1,
-            GPIO23_EDGE_LOW: u1,
-            GPIO23_EDGE_HIGH: u1,
-        }), base_address + 0x148);
-
-        /// address: 0x4001414c
-        /// Interrupt Force for proc1
-        pub const PROC1_INTF3 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO24_LEVEL_LOW: u1,
-            GPIO24_LEVEL_HIGH: u1,
-            GPIO24_EDGE_LOW: u1,
-            GPIO24_EDGE_HIGH: u1,
-            GPIO25_LEVEL_LOW: u1,
-            GPIO25_LEVEL_HIGH: u1,
-            GPIO25_EDGE_LOW: u1,
-            GPIO25_EDGE_HIGH: u1,
-            GPIO26_LEVEL_LOW: u1,
-            GPIO26_LEVEL_HIGH: u1,
-            GPIO26_EDGE_LOW: u1,
-            GPIO26_EDGE_HIGH: u1,
-            GPIO27_LEVEL_LOW: u1,
-            GPIO27_LEVEL_HIGH: u1,
-            GPIO27_EDGE_LOW: u1,
-            GPIO27_EDGE_HIGH: u1,
-            GPIO28_LEVEL_LOW: u1,
-            GPIO28_LEVEL_HIGH: u1,
-            GPIO28_EDGE_LOW: u1,
-            GPIO28_EDGE_HIGH: u1,
-            GPIO29_LEVEL_LOW: u1,
-            GPIO29_LEVEL_HIGH: u1,
-            GPIO29_EDGE_LOW: u1,
-            GPIO29_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x14c);
-
-        /// address: 0x40014150
-        /// Interrupt status after masking & forcing for proc1
-        pub const PROC1_INTS0 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO0_LEVEL_LOW: u1,
-            GPIO0_LEVEL_HIGH: u1,
-            GPIO0_EDGE_LOW: u1,
-            GPIO0_EDGE_HIGH: u1,
-            GPIO1_LEVEL_LOW: u1,
-            GPIO1_LEVEL_HIGH: u1,
-            GPIO1_EDGE_LOW: u1,
-            GPIO1_EDGE_HIGH: u1,
-            GPIO2_LEVEL_LOW: u1,
-            GPIO2_LEVEL_HIGH: u1,
-            GPIO2_EDGE_LOW: u1,
-            GPIO2_EDGE_HIGH: u1,
-            GPIO3_LEVEL_LOW: u1,
-            GPIO3_LEVEL_HIGH: u1,
-            GPIO3_EDGE_LOW: u1,
-            GPIO3_EDGE_HIGH: u1,
-            GPIO4_LEVEL_LOW: u1,
-            GPIO4_LEVEL_HIGH: u1,
-            GPIO4_EDGE_LOW: u1,
-            GPIO4_EDGE_HIGH: u1,
-            GPIO5_LEVEL_LOW: u1,
-            GPIO5_LEVEL_HIGH: u1,
-            GPIO5_EDGE_LOW: u1,
-            GPIO5_EDGE_HIGH: u1,
-            GPIO6_LEVEL_LOW: u1,
-            GPIO6_LEVEL_HIGH: u1,
-            GPIO6_EDGE_LOW: u1,
-            GPIO6_EDGE_HIGH: u1,
-            GPIO7_LEVEL_LOW: u1,
-            GPIO7_LEVEL_HIGH: u1,
-            GPIO7_EDGE_LOW: u1,
-            GPIO7_EDGE_HIGH: u1,
-        }), base_address + 0x150);
-
-        /// address: 0x40014154
-        /// Interrupt status after masking & forcing for proc1
-        pub const PROC1_INTS1 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO8_LEVEL_LOW: u1,
-            GPIO8_LEVEL_HIGH: u1,
-            GPIO8_EDGE_LOW: u1,
-            GPIO8_EDGE_HIGH: u1,
-            GPIO9_LEVEL_LOW: u1,
-            GPIO9_LEVEL_HIGH: u1,
-            GPIO9_EDGE_LOW: u1,
-            GPIO9_EDGE_HIGH: u1,
-            GPIO10_LEVEL_LOW: u1,
-            GPIO10_LEVEL_HIGH: u1,
-            GPIO10_EDGE_LOW: u1,
-            GPIO10_EDGE_HIGH: u1,
-            GPIO11_LEVEL_LOW: u1,
-            GPIO11_LEVEL_HIGH: u1,
-            GPIO11_EDGE_LOW: u1,
-            GPIO11_EDGE_HIGH: u1,
-            GPIO12_LEVEL_LOW: u1,
-            GPIO12_LEVEL_HIGH: u1,
-            GPIO12_EDGE_LOW: u1,
-            GPIO12_EDGE_HIGH: u1,
-            GPIO13_LEVEL_LOW: u1,
-            GPIO13_LEVEL_HIGH: u1,
-            GPIO13_EDGE_LOW: u1,
-            GPIO13_EDGE_HIGH: u1,
-            GPIO14_LEVEL_LOW: u1,
-            GPIO14_LEVEL_HIGH: u1,
-            GPIO14_EDGE_LOW: u1,
-            GPIO14_EDGE_HIGH: u1,
-            GPIO15_LEVEL_LOW: u1,
-            GPIO15_LEVEL_HIGH: u1,
-            GPIO15_EDGE_LOW: u1,
-            GPIO15_EDGE_HIGH: u1,
-        }), base_address + 0x154);
-
-        /// address: 0x40014158
-        /// Interrupt status after masking & forcing for proc1
-        pub const PROC1_INTS2 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO16_LEVEL_LOW: u1,
-            GPIO16_LEVEL_HIGH: u1,
-            GPIO16_EDGE_LOW: u1,
-            GPIO16_EDGE_HIGH: u1,
-            GPIO17_LEVEL_LOW: u1,
-            GPIO17_LEVEL_HIGH: u1,
-            GPIO17_EDGE_LOW: u1,
-            GPIO17_EDGE_HIGH: u1,
-            GPIO18_LEVEL_LOW: u1,
-            GPIO18_LEVEL_HIGH: u1,
-            GPIO18_EDGE_LOW: u1,
-            GPIO18_EDGE_HIGH: u1,
-            GPIO19_LEVEL_LOW: u1,
-            GPIO19_LEVEL_HIGH: u1,
-            GPIO19_EDGE_LOW: u1,
-            GPIO19_EDGE_HIGH: u1,
-            GPIO20_LEVEL_LOW: u1,
-            GPIO20_LEVEL_HIGH: u1,
-            GPIO20_EDGE_LOW: u1,
-            GPIO20_EDGE_HIGH: u1,
-            GPIO21_LEVEL_LOW: u1,
-            GPIO21_LEVEL_HIGH: u1,
-            GPIO21_EDGE_LOW: u1,
-            GPIO21_EDGE_HIGH: u1,
-            GPIO22_LEVEL_LOW: u1,
-            GPIO22_LEVEL_HIGH: u1,
-            GPIO22_EDGE_LOW: u1,
-            GPIO22_EDGE_HIGH: u1,
-            GPIO23_LEVEL_LOW: u1,
-            GPIO23_LEVEL_HIGH: u1,
-            GPIO23_EDGE_LOW: u1,
-            GPIO23_EDGE_HIGH: u1,
-        }), base_address + 0x158);
-
-        /// address: 0x4001415c
-        /// Interrupt status after masking & forcing for proc1
-        pub const PROC1_INTS3 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO24_LEVEL_LOW: u1,
-            GPIO24_LEVEL_HIGH: u1,
-            GPIO24_EDGE_LOW: u1,
-            GPIO24_EDGE_HIGH: u1,
-            GPIO25_LEVEL_LOW: u1,
-            GPIO25_LEVEL_HIGH: u1,
-            GPIO25_EDGE_LOW: u1,
-            GPIO25_EDGE_HIGH: u1,
-            GPIO26_LEVEL_LOW: u1,
-            GPIO26_LEVEL_HIGH: u1,
-            GPIO26_EDGE_LOW: u1,
-            GPIO26_EDGE_HIGH: u1,
-            GPIO27_LEVEL_LOW: u1,
-            GPIO27_LEVEL_HIGH: u1,
-            GPIO27_EDGE_LOW: u1,
-            GPIO27_EDGE_HIGH: u1,
-            GPIO28_LEVEL_LOW: u1,
-            GPIO28_LEVEL_HIGH: u1,
-            GPIO28_EDGE_LOW: u1,
-            GPIO28_EDGE_HIGH: u1,
-            GPIO29_LEVEL_LOW: u1,
-            GPIO29_LEVEL_HIGH: u1,
-            GPIO29_EDGE_LOW: u1,
-            GPIO29_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x15c);
-
-        /// address: 0x40014160
-        /// Interrupt Enable for dormant_wake
-        pub const DORMANT_WAKE_INTE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO0_LEVEL_LOW: u1,
-            GPIO0_LEVEL_HIGH: u1,
-            GPIO0_EDGE_LOW: u1,
-            GPIO0_EDGE_HIGH: u1,
-            GPIO1_LEVEL_LOW: u1,
-            GPIO1_LEVEL_HIGH: u1,
-            GPIO1_EDGE_LOW: u1,
-            GPIO1_EDGE_HIGH: u1,
-            GPIO2_LEVEL_LOW: u1,
-            GPIO2_LEVEL_HIGH: u1,
-            GPIO2_EDGE_LOW: u1,
-            GPIO2_EDGE_HIGH: u1,
-            GPIO3_LEVEL_LOW: u1,
-            GPIO3_LEVEL_HIGH: u1,
-            GPIO3_EDGE_LOW: u1,
-            GPIO3_EDGE_HIGH: u1,
-            GPIO4_LEVEL_LOW: u1,
-            GPIO4_LEVEL_HIGH: u1,
-            GPIO4_EDGE_LOW: u1,
-            GPIO4_EDGE_HIGH: u1,
-            GPIO5_LEVEL_LOW: u1,
-            GPIO5_LEVEL_HIGH: u1,
-            GPIO5_EDGE_LOW: u1,
-            GPIO5_EDGE_HIGH: u1,
-            GPIO6_LEVEL_LOW: u1,
-            GPIO6_LEVEL_HIGH: u1,
-            GPIO6_EDGE_LOW: u1,
-            GPIO6_EDGE_HIGH: u1,
-            GPIO7_LEVEL_LOW: u1,
-            GPIO7_LEVEL_HIGH: u1,
-            GPIO7_EDGE_LOW: u1,
-            GPIO7_EDGE_HIGH: u1,
-        }), base_address + 0x160);
-
-        /// address: 0x40014164
-        /// Interrupt Enable for dormant_wake
-        pub const DORMANT_WAKE_INTE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO8_LEVEL_LOW: u1,
-            GPIO8_LEVEL_HIGH: u1,
-            GPIO8_EDGE_LOW: u1,
-            GPIO8_EDGE_HIGH: u1,
-            GPIO9_LEVEL_LOW: u1,
-            GPIO9_LEVEL_HIGH: u1,
-            GPIO9_EDGE_LOW: u1,
-            GPIO9_EDGE_HIGH: u1,
-            GPIO10_LEVEL_LOW: u1,
-            GPIO10_LEVEL_HIGH: u1,
-            GPIO10_EDGE_LOW: u1,
-            GPIO10_EDGE_HIGH: u1,
-            GPIO11_LEVEL_LOW: u1,
-            GPIO11_LEVEL_HIGH: u1,
-            GPIO11_EDGE_LOW: u1,
-            GPIO11_EDGE_HIGH: u1,
-            GPIO12_LEVEL_LOW: u1,
-            GPIO12_LEVEL_HIGH: u1,
-            GPIO12_EDGE_LOW: u1,
-            GPIO12_EDGE_HIGH: u1,
-            GPIO13_LEVEL_LOW: u1,
-            GPIO13_LEVEL_HIGH: u1,
-            GPIO13_EDGE_LOW: u1,
-            GPIO13_EDGE_HIGH: u1,
-            GPIO14_LEVEL_LOW: u1,
-            GPIO14_LEVEL_HIGH: u1,
-            GPIO14_EDGE_LOW: u1,
-            GPIO14_EDGE_HIGH: u1,
-            GPIO15_LEVEL_LOW: u1,
-            GPIO15_LEVEL_HIGH: u1,
-            GPIO15_EDGE_LOW: u1,
-            GPIO15_EDGE_HIGH: u1,
-        }), base_address + 0x164);
-
-        /// address: 0x40014168
-        /// Interrupt Enable for dormant_wake
-        pub const DORMANT_WAKE_INTE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO16_LEVEL_LOW: u1,
-            GPIO16_LEVEL_HIGH: u1,
-            GPIO16_EDGE_LOW: u1,
-            GPIO16_EDGE_HIGH: u1,
-            GPIO17_LEVEL_LOW: u1,
-            GPIO17_LEVEL_HIGH: u1,
-            GPIO17_EDGE_LOW: u1,
-            GPIO17_EDGE_HIGH: u1,
-            GPIO18_LEVEL_LOW: u1,
-            GPIO18_LEVEL_HIGH: u1,
-            GPIO18_EDGE_LOW: u1,
-            GPIO18_EDGE_HIGH: u1,
-            GPIO19_LEVEL_LOW: u1,
-            GPIO19_LEVEL_HIGH: u1,
-            GPIO19_EDGE_LOW: u1,
-            GPIO19_EDGE_HIGH: u1,
-            GPIO20_LEVEL_LOW: u1,
-            GPIO20_LEVEL_HIGH: u1,
-            GPIO20_EDGE_LOW: u1,
-            GPIO20_EDGE_HIGH: u1,
-            GPIO21_LEVEL_LOW: u1,
-            GPIO21_LEVEL_HIGH: u1,
-            GPIO21_EDGE_LOW: u1,
-            GPIO21_EDGE_HIGH: u1,
-            GPIO22_LEVEL_LOW: u1,
-            GPIO22_LEVEL_HIGH: u1,
-            GPIO22_EDGE_LOW: u1,
-            GPIO22_EDGE_HIGH: u1,
-            GPIO23_LEVEL_LOW: u1,
-            GPIO23_LEVEL_HIGH: u1,
-            GPIO23_EDGE_LOW: u1,
-            GPIO23_EDGE_HIGH: u1,
-        }), base_address + 0x168);
-
-        /// address: 0x4001416c
-        /// Interrupt Enable for dormant_wake
-        pub const DORMANT_WAKE_INTE3 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO24_LEVEL_LOW: u1,
-            GPIO24_LEVEL_HIGH: u1,
-            GPIO24_EDGE_LOW: u1,
-            GPIO24_EDGE_HIGH: u1,
-            GPIO25_LEVEL_LOW: u1,
-            GPIO25_LEVEL_HIGH: u1,
-            GPIO25_EDGE_LOW: u1,
-            GPIO25_EDGE_HIGH: u1,
-            GPIO26_LEVEL_LOW: u1,
-            GPIO26_LEVEL_HIGH: u1,
-            GPIO26_EDGE_LOW: u1,
-            GPIO26_EDGE_HIGH: u1,
-            GPIO27_LEVEL_LOW: u1,
-            GPIO27_LEVEL_HIGH: u1,
-            GPIO27_EDGE_LOW: u1,
-            GPIO27_EDGE_HIGH: u1,
-            GPIO28_LEVEL_LOW: u1,
-            GPIO28_LEVEL_HIGH: u1,
-            GPIO28_EDGE_LOW: u1,
-            GPIO28_EDGE_HIGH: u1,
-            GPIO29_LEVEL_LOW: u1,
-            GPIO29_LEVEL_HIGH: u1,
-            GPIO29_EDGE_LOW: u1,
-            GPIO29_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x16c);
-
-        /// address: 0x40014170
-        /// Interrupt Force for dormant_wake
-        pub const DORMANT_WAKE_INTF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO0_LEVEL_LOW: u1,
-            GPIO0_LEVEL_HIGH: u1,
-            GPIO0_EDGE_LOW: u1,
-            GPIO0_EDGE_HIGH: u1,
-            GPIO1_LEVEL_LOW: u1,
-            GPIO1_LEVEL_HIGH: u1,
-            GPIO1_EDGE_LOW: u1,
-            GPIO1_EDGE_HIGH: u1,
-            GPIO2_LEVEL_LOW: u1,
-            GPIO2_LEVEL_HIGH: u1,
-            GPIO2_EDGE_LOW: u1,
-            GPIO2_EDGE_HIGH: u1,
-            GPIO3_LEVEL_LOW: u1,
-            GPIO3_LEVEL_HIGH: u1,
-            GPIO3_EDGE_LOW: u1,
-            GPIO3_EDGE_HIGH: u1,
-            GPIO4_LEVEL_LOW: u1,
-            GPIO4_LEVEL_HIGH: u1,
-            GPIO4_EDGE_LOW: u1,
-            GPIO4_EDGE_HIGH: u1,
-            GPIO5_LEVEL_LOW: u1,
-            GPIO5_LEVEL_HIGH: u1,
-            GPIO5_EDGE_LOW: u1,
-            GPIO5_EDGE_HIGH: u1,
-            GPIO6_LEVEL_LOW: u1,
-            GPIO6_LEVEL_HIGH: u1,
-            GPIO6_EDGE_LOW: u1,
-            GPIO6_EDGE_HIGH: u1,
-            GPIO7_LEVEL_LOW: u1,
-            GPIO7_LEVEL_HIGH: u1,
-            GPIO7_EDGE_LOW: u1,
-            GPIO7_EDGE_HIGH: u1,
-        }), base_address + 0x170);
-
-        /// address: 0x40014174
-        /// Interrupt Force for dormant_wake
-        pub const DORMANT_WAKE_INTF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO8_LEVEL_LOW: u1,
-            GPIO8_LEVEL_HIGH: u1,
-            GPIO8_EDGE_LOW: u1,
-            GPIO8_EDGE_HIGH: u1,
-            GPIO9_LEVEL_LOW: u1,
-            GPIO9_LEVEL_HIGH: u1,
-            GPIO9_EDGE_LOW: u1,
-            GPIO9_EDGE_HIGH: u1,
-            GPIO10_LEVEL_LOW: u1,
-            GPIO10_LEVEL_HIGH: u1,
-            GPIO10_EDGE_LOW: u1,
-            GPIO10_EDGE_HIGH: u1,
-            GPIO11_LEVEL_LOW: u1,
-            GPIO11_LEVEL_HIGH: u1,
-            GPIO11_EDGE_LOW: u1,
-            GPIO11_EDGE_HIGH: u1,
-            GPIO12_LEVEL_LOW: u1,
-            GPIO12_LEVEL_HIGH: u1,
-            GPIO12_EDGE_LOW: u1,
-            GPIO12_EDGE_HIGH: u1,
-            GPIO13_LEVEL_LOW: u1,
-            GPIO13_LEVEL_HIGH: u1,
-            GPIO13_EDGE_LOW: u1,
-            GPIO13_EDGE_HIGH: u1,
-            GPIO14_LEVEL_LOW: u1,
-            GPIO14_LEVEL_HIGH: u1,
-            GPIO14_EDGE_LOW: u1,
-            GPIO14_EDGE_HIGH: u1,
-            GPIO15_LEVEL_LOW: u1,
-            GPIO15_LEVEL_HIGH: u1,
-            GPIO15_EDGE_LOW: u1,
-            GPIO15_EDGE_HIGH: u1,
-        }), base_address + 0x174);
-
-        /// address: 0x40014178
-        /// Interrupt Force for dormant_wake
-        pub const DORMANT_WAKE_INTF2 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO16_LEVEL_LOW: u1,
-            GPIO16_LEVEL_HIGH: u1,
-            GPIO16_EDGE_LOW: u1,
-            GPIO16_EDGE_HIGH: u1,
-            GPIO17_LEVEL_LOW: u1,
-            GPIO17_LEVEL_HIGH: u1,
-            GPIO17_EDGE_LOW: u1,
-            GPIO17_EDGE_HIGH: u1,
-            GPIO18_LEVEL_LOW: u1,
-            GPIO18_LEVEL_HIGH: u1,
-            GPIO18_EDGE_LOW: u1,
-            GPIO18_EDGE_HIGH: u1,
-            GPIO19_LEVEL_LOW: u1,
-            GPIO19_LEVEL_HIGH: u1,
-            GPIO19_EDGE_LOW: u1,
-            GPIO19_EDGE_HIGH: u1,
-            GPIO20_LEVEL_LOW: u1,
-            GPIO20_LEVEL_HIGH: u1,
-            GPIO20_EDGE_LOW: u1,
-            GPIO20_EDGE_HIGH: u1,
-            GPIO21_LEVEL_LOW: u1,
-            GPIO21_LEVEL_HIGH: u1,
-            GPIO21_EDGE_LOW: u1,
-            GPIO21_EDGE_HIGH: u1,
-            GPIO22_LEVEL_LOW: u1,
-            GPIO22_LEVEL_HIGH: u1,
-            GPIO22_EDGE_LOW: u1,
-            GPIO22_EDGE_HIGH: u1,
-            GPIO23_LEVEL_LOW: u1,
-            GPIO23_LEVEL_HIGH: u1,
-            GPIO23_EDGE_LOW: u1,
-            GPIO23_EDGE_HIGH: u1,
-        }), base_address + 0x178);
-
-        /// address: 0x4001417c
-        /// Interrupt Force for dormant_wake
-        pub const DORMANT_WAKE_INTF3 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO24_LEVEL_LOW: u1,
-            GPIO24_LEVEL_HIGH: u1,
-            GPIO24_EDGE_LOW: u1,
-            GPIO24_EDGE_HIGH: u1,
-            GPIO25_LEVEL_LOW: u1,
-            GPIO25_LEVEL_HIGH: u1,
-            GPIO25_EDGE_LOW: u1,
-            GPIO25_EDGE_HIGH: u1,
-            GPIO26_LEVEL_LOW: u1,
-            GPIO26_LEVEL_HIGH: u1,
-            GPIO26_EDGE_LOW: u1,
-            GPIO26_EDGE_HIGH: u1,
-            GPIO27_LEVEL_LOW: u1,
-            GPIO27_LEVEL_HIGH: u1,
-            GPIO27_EDGE_LOW: u1,
-            GPIO27_EDGE_HIGH: u1,
-            GPIO28_LEVEL_LOW: u1,
-            GPIO28_LEVEL_HIGH: u1,
-            GPIO28_EDGE_LOW: u1,
-            GPIO28_EDGE_HIGH: u1,
-            GPIO29_LEVEL_LOW: u1,
-            GPIO29_LEVEL_HIGH: u1,
-            GPIO29_EDGE_LOW: u1,
-            GPIO29_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x17c);
-
-        /// address: 0x40014180
-        /// Interrupt status after masking & forcing for dormant_wake
-        pub const DORMANT_WAKE_INTS0 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO0_LEVEL_LOW: u1,
-            GPIO0_LEVEL_HIGH: u1,
-            GPIO0_EDGE_LOW: u1,
-            GPIO0_EDGE_HIGH: u1,
-            GPIO1_LEVEL_LOW: u1,
-            GPIO1_LEVEL_HIGH: u1,
-            GPIO1_EDGE_LOW: u1,
-            GPIO1_EDGE_HIGH: u1,
-            GPIO2_LEVEL_LOW: u1,
-            GPIO2_LEVEL_HIGH: u1,
-            GPIO2_EDGE_LOW: u1,
-            GPIO2_EDGE_HIGH: u1,
-            GPIO3_LEVEL_LOW: u1,
-            GPIO3_LEVEL_HIGH: u1,
-            GPIO3_EDGE_LOW: u1,
-            GPIO3_EDGE_HIGH: u1,
-            GPIO4_LEVEL_LOW: u1,
-            GPIO4_LEVEL_HIGH: u1,
-            GPIO4_EDGE_LOW: u1,
-            GPIO4_EDGE_HIGH: u1,
-            GPIO5_LEVEL_LOW: u1,
-            GPIO5_LEVEL_HIGH: u1,
-            GPIO5_EDGE_LOW: u1,
-            GPIO5_EDGE_HIGH: u1,
-            GPIO6_LEVEL_LOW: u1,
-            GPIO6_LEVEL_HIGH: u1,
-            GPIO6_EDGE_LOW: u1,
-            GPIO6_EDGE_HIGH: u1,
-            GPIO7_LEVEL_LOW: u1,
-            GPIO7_LEVEL_HIGH: u1,
-            GPIO7_EDGE_LOW: u1,
-            GPIO7_EDGE_HIGH: u1,
-        }), base_address + 0x180);
-
-        /// address: 0x40014184
-        /// Interrupt status after masking & forcing for dormant_wake
-        pub const DORMANT_WAKE_INTS1 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO8_LEVEL_LOW: u1,
-            GPIO8_LEVEL_HIGH: u1,
-            GPIO8_EDGE_LOW: u1,
-            GPIO8_EDGE_HIGH: u1,
-            GPIO9_LEVEL_LOW: u1,
-            GPIO9_LEVEL_HIGH: u1,
-            GPIO9_EDGE_LOW: u1,
-            GPIO9_EDGE_HIGH: u1,
-            GPIO10_LEVEL_LOW: u1,
-            GPIO10_LEVEL_HIGH: u1,
-            GPIO10_EDGE_LOW: u1,
-            GPIO10_EDGE_HIGH: u1,
-            GPIO11_LEVEL_LOW: u1,
-            GPIO11_LEVEL_HIGH: u1,
-            GPIO11_EDGE_LOW: u1,
-            GPIO11_EDGE_HIGH: u1,
-            GPIO12_LEVEL_LOW: u1,
-            GPIO12_LEVEL_HIGH: u1,
-            GPIO12_EDGE_LOW: u1,
-            GPIO12_EDGE_HIGH: u1,
-            GPIO13_LEVEL_LOW: u1,
-            GPIO13_LEVEL_HIGH: u1,
-            GPIO13_EDGE_LOW: u1,
-            GPIO13_EDGE_HIGH: u1,
-            GPIO14_LEVEL_LOW: u1,
-            GPIO14_LEVEL_HIGH: u1,
-            GPIO14_EDGE_LOW: u1,
-            GPIO14_EDGE_HIGH: u1,
-            GPIO15_LEVEL_LOW: u1,
-            GPIO15_LEVEL_HIGH: u1,
-            GPIO15_EDGE_LOW: u1,
-            GPIO15_EDGE_HIGH: u1,
-        }), base_address + 0x184);
-
-        /// address: 0x40014188
-        /// Interrupt status after masking & forcing for dormant_wake
-        pub const DORMANT_WAKE_INTS2 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO16_LEVEL_LOW: u1,
-            GPIO16_LEVEL_HIGH: u1,
-            GPIO16_EDGE_LOW: u1,
-            GPIO16_EDGE_HIGH: u1,
-            GPIO17_LEVEL_LOW: u1,
-            GPIO17_LEVEL_HIGH: u1,
-            GPIO17_EDGE_LOW: u1,
-            GPIO17_EDGE_HIGH: u1,
-            GPIO18_LEVEL_LOW: u1,
-            GPIO18_LEVEL_HIGH: u1,
-            GPIO18_EDGE_LOW: u1,
-            GPIO18_EDGE_HIGH: u1,
-            GPIO19_LEVEL_LOW: u1,
-            GPIO19_LEVEL_HIGH: u1,
-            GPIO19_EDGE_LOW: u1,
-            GPIO19_EDGE_HIGH: u1,
-            GPIO20_LEVEL_LOW: u1,
-            GPIO20_LEVEL_HIGH: u1,
-            GPIO20_EDGE_LOW: u1,
-            GPIO20_EDGE_HIGH: u1,
-            GPIO21_LEVEL_LOW: u1,
-            GPIO21_LEVEL_HIGH: u1,
-            GPIO21_EDGE_LOW: u1,
-            GPIO21_EDGE_HIGH: u1,
-            GPIO22_LEVEL_LOW: u1,
-            GPIO22_LEVEL_HIGH: u1,
-            GPIO22_EDGE_LOW: u1,
-            GPIO22_EDGE_HIGH: u1,
-            GPIO23_LEVEL_LOW: u1,
-            GPIO23_LEVEL_HIGH: u1,
-            GPIO23_EDGE_LOW: u1,
-            GPIO23_EDGE_HIGH: u1,
-        }), base_address + 0x188);
-
-        /// address: 0x4001418c
-        /// Interrupt status after masking & forcing for dormant_wake
-        pub const DORMANT_WAKE_INTS3 = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO24_LEVEL_LOW: u1,
-            GPIO24_LEVEL_HIGH: u1,
-            GPIO24_EDGE_LOW: u1,
-            GPIO24_EDGE_HIGH: u1,
-            GPIO25_LEVEL_LOW: u1,
-            GPIO25_LEVEL_HIGH: u1,
-            GPIO25_EDGE_LOW: u1,
-            GPIO25_EDGE_HIGH: u1,
-            GPIO26_LEVEL_LOW: u1,
-            GPIO26_LEVEL_HIGH: u1,
-            GPIO26_EDGE_LOW: u1,
-            GPIO26_EDGE_HIGH: u1,
-            GPIO27_LEVEL_LOW: u1,
-            GPIO27_LEVEL_HIGH: u1,
-            GPIO27_EDGE_LOW: u1,
-            GPIO27_EDGE_HIGH: u1,
-            GPIO28_LEVEL_LOW: u1,
-            GPIO28_LEVEL_HIGH: u1,
-            GPIO28_EDGE_LOW: u1,
-            GPIO28_EDGE_HIGH: u1,
-            GPIO29_LEVEL_LOW: u1,
-            GPIO29_LEVEL_HIGH: u1,
-            GPIO29_EDGE_LOW: u1,
-            GPIO29_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x18c);
-    };
-    pub const IO_QSPI = struct {
-        pub const base_address = 0x40018000;
-        pub const version = "1";
-
-        /// address: 0x40018000
-        /// GPIO status
-        pub const GPIO_QSPI_SCLK_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40018004
-        /// GPIO control including function select and overrides.
-        pub const GPIO_QSPI_SCLK_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40018008
-        /// GPIO status
-        pub const GPIO_QSPI_SS_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x4001800c
-        /// GPIO control including function select and overrides.
-        pub const GPIO_QSPI_SS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x40018010
-        /// GPIO status
-        pub const GPIO_QSPI_SD0_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x10);
-
-        /// address: 0x40018014
-        /// GPIO control including function select and overrides.
-        pub const GPIO_QSPI_SD0_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x40018018
-        /// GPIO status
-        pub const GPIO_QSPI_SD1_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x4001801c
-        /// GPIO control including function select and overrides.
-        pub const GPIO_QSPI_SD1_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x1c);
-
-        /// address: 0x40018020
-        /// GPIO status
-        pub const GPIO_QSPI_SD2_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x20);
-
-        /// address: 0x40018024
-        /// GPIO control including function select and overrides.
-        pub const GPIO_QSPI_SD2_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x24);
-
-        /// address: 0x40018028
-        /// GPIO status
-        pub const GPIO_QSPI_SD3_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// output signal from selected peripheral, before register override is applied
-            OUTFROMPERI: u1,
-            /// output signal to pad after register override is applied
-            OUTTOPAD: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// output enable from selected peripheral, before register override is applied
-            OEFROMPERI: u1,
-            /// output enable to pad after register override is applied
-            OETOPAD: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            /// input signal from pad, before override is applied
-            INFROMPAD: u1,
-            reserved13: u1 = 0,
-            /// input signal to peripheral, after override is applied
-            INTOPERI: u1,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// interrupt from pad before override is applied
-            IRQFROMPAD: u1,
-            reserved18: u1 = 0,
-            /// interrupt to processors, after override is applied
-            IRQTOPROC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x28);
-
-        /// address: 0x4001802c
-        /// GPIO control including function select and overrides.
-        pub const GPIO_QSPI_SD3_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0-31 -> selects pin function according to the gpio table\n
-            /// 31 == NULL
-            FUNCSEL: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            OUTOVER: u2,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            OEOVER: u2,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            INOVER: u2,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            IRQOVER: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x2c);
-
-        /// address: 0x40018030
-        /// Raw Interrupts
-        pub const INTR = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-            GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-            GPIO_QSPI_SCLK_EDGE_LOW: u1,
-            GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-            GPIO_QSPI_SS_LEVEL_LOW: u1,
-            GPIO_QSPI_SS_LEVEL_HIGH: u1,
-            GPIO_QSPI_SS_EDGE_LOW: u1,
-            GPIO_QSPI_SS_EDGE_HIGH: u1,
-            GPIO_QSPI_SD0_LEVEL_LOW: u1,
-            GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD0_EDGE_LOW: u1,
-            GPIO_QSPI_SD0_EDGE_HIGH: u1,
-            GPIO_QSPI_SD1_LEVEL_LOW: u1,
-            GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD1_EDGE_LOW: u1,
-            GPIO_QSPI_SD1_EDGE_HIGH: u1,
-            GPIO_QSPI_SD2_LEVEL_LOW: u1,
-            GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD2_EDGE_LOW: u1,
-            GPIO_QSPI_SD2_EDGE_HIGH: u1,
-            GPIO_QSPI_SD3_LEVEL_LOW: u1,
-            GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD3_EDGE_LOW: u1,
-            GPIO_QSPI_SD3_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x30);
-
-        /// address: 0x40018034
-        /// Interrupt Enable for proc0
-        pub const PROC0_INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-            GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-            GPIO_QSPI_SCLK_EDGE_LOW: u1,
-            GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-            GPIO_QSPI_SS_LEVEL_LOW: u1,
-            GPIO_QSPI_SS_LEVEL_HIGH: u1,
-            GPIO_QSPI_SS_EDGE_LOW: u1,
-            GPIO_QSPI_SS_EDGE_HIGH: u1,
-            GPIO_QSPI_SD0_LEVEL_LOW: u1,
-            GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD0_EDGE_LOW: u1,
-            GPIO_QSPI_SD0_EDGE_HIGH: u1,
-            GPIO_QSPI_SD1_LEVEL_LOW: u1,
-            GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD1_EDGE_LOW: u1,
-            GPIO_QSPI_SD1_EDGE_HIGH: u1,
-            GPIO_QSPI_SD2_LEVEL_LOW: u1,
-            GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD2_EDGE_LOW: u1,
-            GPIO_QSPI_SD2_EDGE_HIGH: u1,
-            GPIO_QSPI_SD3_LEVEL_LOW: u1,
-            GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD3_EDGE_LOW: u1,
-            GPIO_QSPI_SD3_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x34);
-
-        /// address: 0x40018038
-        /// Interrupt Force for proc0
-        pub const PROC0_INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-            GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-            GPIO_QSPI_SCLK_EDGE_LOW: u1,
-            GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-            GPIO_QSPI_SS_LEVEL_LOW: u1,
-            GPIO_QSPI_SS_LEVEL_HIGH: u1,
-            GPIO_QSPI_SS_EDGE_LOW: u1,
-            GPIO_QSPI_SS_EDGE_HIGH: u1,
-            GPIO_QSPI_SD0_LEVEL_LOW: u1,
-            GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD0_EDGE_LOW: u1,
-            GPIO_QSPI_SD0_EDGE_HIGH: u1,
-            GPIO_QSPI_SD1_LEVEL_LOW: u1,
-            GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD1_EDGE_LOW: u1,
-            GPIO_QSPI_SD1_EDGE_HIGH: u1,
-            GPIO_QSPI_SD2_LEVEL_LOW: u1,
-            GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD2_EDGE_LOW: u1,
-            GPIO_QSPI_SD2_EDGE_HIGH: u1,
-            GPIO_QSPI_SD3_LEVEL_LOW: u1,
-            GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD3_EDGE_LOW: u1,
-            GPIO_QSPI_SD3_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x38);
-
-        /// address: 0x4001803c
-        /// Interrupt status after masking & forcing for proc0
-        pub const PROC0_INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-            GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-            GPIO_QSPI_SCLK_EDGE_LOW: u1,
-            GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-            GPIO_QSPI_SS_LEVEL_LOW: u1,
-            GPIO_QSPI_SS_LEVEL_HIGH: u1,
-            GPIO_QSPI_SS_EDGE_LOW: u1,
-            GPIO_QSPI_SS_EDGE_HIGH: u1,
-            GPIO_QSPI_SD0_LEVEL_LOW: u1,
-            GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD0_EDGE_LOW: u1,
-            GPIO_QSPI_SD0_EDGE_HIGH: u1,
-            GPIO_QSPI_SD1_LEVEL_LOW: u1,
-            GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD1_EDGE_LOW: u1,
-            GPIO_QSPI_SD1_EDGE_HIGH: u1,
-            GPIO_QSPI_SD2_LEVEL_LOW: u1,
-            GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD2_EDGE_LOW: u1,
-            GPIO_QSPI_SD2_EDGE_HIGH: u1,
-            GPIO_QSPI_SD3_LEVEL_LOW: u1,
-            GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD3_EDGE_LOW: u1,
-            GPIO_QSPI_SD3_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x3c);
-
-        /// address: 0x40018040
-        /// Interrupt Enable for proc1
-        pub const PROC1_INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-            GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-            GPIO_QSPI_SCLK_EDGE_LOW: u1,
-            GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-            GPIO_QSPI_SS_LEVEL_LOW: u1,
-            GPIO_QSPI_SS_LEVEL_HIGH: u1,
-            GPIO_QSPI_SS_EDGE_LOW: u1,
-            GPIO_QSPI_SS_EDGE_HIGH: u1,
-            GPIO_QSPI_SD0_LEVEL_LOW: u1,
-            GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD0_EDGE_LOW: u1,
-            GPIO_QSPI_SD0_EDGE_HIGH: u1,
-            GPIO_QSPI_SD1_LEVEL_LOW: u1,
-            GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD1_EDGE_LOW: u1,
-            GPIO_QSPI_SD1_EDGE_HIGH: u1,
-            GPIO_QSPI_SD2_LEVEL_LOW: u1,
-            GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD2_EDGE_LOW: u1,
-            GPIO_QSPI_SD2_EDGE_HIGH: u1,
-            GPIO_QSPI_SD3_LEVEL_LOW: u1,
-            GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD3_EDGE_LOW: u1,
-            GPIO_QSPI_SD3_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x40);
-
-        /// address: 0x40018044
-        /// Interrupt Force for proc1
-        pub const PROC1_INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-            GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-            GPIO_QSPI_SCLK_EDGE_LOW: u1,
-            GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-            GPIO_QSPI_SS_LEVEL_LOW: u1,
-            GPIO_QSPI_SS_LEVEL_HIGH: u1,
-            GPIO_QSPI_SS_EDGE_LOW: u1,
-            GPIO_QSPI_SS_EDGE_HIGH: u1,
-            GPIO_QSPI_SD0_LEVEL_LOW: u1,
-            GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD0_EDGE_LOW: u1,
-            GPIO_QSPI_SD0_EDGE_HIGH: u1,
-            GPIO_QSPI_SD1_LEVEL_LOW: u1,
-            GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD1_EDGE_LOW: u1,
-            GPIO_QSPI_SD1_EDGE_HIGH: u1,
-            GPIO_QSPI_SD2_LEVEL_LOW: u1,
-            GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD2_EDGE_LOW: u1,
-            GPIO_QSPI_SD2_EDGE_HIGH: u1,
-            GPIO_QSPI_SD3_LEVEL_LOW: u1,
-            GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD3_EDGE_LOW: u1,
-            GPIO_QSPI_SD3_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x44);
-
-        /// address: 0x40018048
-        /// Interrupt status after masking & forcing for proc1
-        pub const PROC1_INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-            GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-            GPIO_QSPI_SCLK_EDGE_LOW: u1,
-            GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-            GPIO_QSPI_SS_LEVEL_LOW: u1,
-            GPIO_QSPI_SS_LEVEL_HIGH: u1,
-            GPIO_QSPI_SS_EDGE_LOW: u1,
-            GPIO_QSPI_SS_EDGE_HIGH: u1,
-            GPIO_QSPI_SD0_LEVEL_LOW: u1,
-            GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD0_EDGE_LOW: u1,
-            GPIO_QSPI_SD0_EDGE_HIGH: u1,
-            GPIO_QSPI_SD1_LEVEL_LOW: u1,
-            GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD1_EDGE_LOW: u1,
-            GPIO_QSPI_SD1_EDGE_HIGH: u1,
-            GPIO_QSPI_SD2_LEVEL_LOW: u1,
-            GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD2_EDGE_LOW: u1,
-            GPIO_QSPI_SD2_EDGE_HIGH: u1,
-            GPIO_QSPI_SD3_LEVEL_LOW: u1,
-            GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD3_EDGE_LOW: u1,
-            GPIO_QSPI_SD3_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x48);
-
-        /// address: 0x4001804c
-        /// Interrupt Enable for dormant_wake
-        pub const DORMANT_WAKE_INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-            GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-            GPIO_QSPI_SCLK_EDGE_LOW: u1,
-            GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-            GPIO_QSPI_SS_LEVEL_LOW: u1,
-            GPIO_QSPI_SS_LEVEL_HIGH: u1,
-            GPIO_QSPI_SS_EDGE_LOW: u1,
-            GPIO_QSPI_SS_EDGE_HIGH: u1,
-            GPIO_QSPI_SD0_LEVEL_LOW: u1,
-            GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD0_EDGE_LOW: u1,
-            GPIO_QSPI_SD0_EDGE_HIGH: u1,
-            GPIO_QSPI_SD1_LEVEL_LOW: u1,
-            GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD1_EDGE_LOW: u1,
-            GPIO_QSPI_SD1_EDGE_HIGH: u1,
-            GPIO_QSPI_SD2_LEVEL_LOW: u1,
-            GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD2_EDGE_LOW: u1,
-            GPIO_QSPI_SD2_EDGE_HIGH: u1,
-            GPIO_QSPI_SD3_LEVEL_LOW: u1,
-            GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD3_EDGE_LOW: u1,
-            GPIO_QSPI_SD3_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x4c);
-
-        /// address: 0x40018050
-        /// Interrupt Force for dormant_wake
-        pub const DORMANT_WAKE_INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-            GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-            GPIO_QSPI_SCLK_EDGE_LOW: u1,
-            GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-            GPIO_QSPI_SS_LEVEL_LOW: u1,
-            GPIO_QSPI_SS_LEVEL_HIGH: u1,
-            GPIO_QSPI_SS_EDGE_LOW: u1,
-            GPIO_QSPI_SS_EDGE_HIGH: u1,
-            GPIO_QSPI_SD0_LEVEL_LOW: u1,
-            GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD0_EDGE_LOW: u1,
-            GPIO_QSPI_SD0_EDGE_HIGH: u1,
-            GPIO_QSPI_SD1_LEVEL_LOW: u1,
-            GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD1_EDGE_LOW: u1,
-            GPIO_QSPI_SD1_EDGE_HIGH: u1,
-            GPIO_QSPI_SD2_LEVEL_LOW: u1,
-            GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD2_EDGE_LOW: u1,
-            GPIO_QSPI_SD2_EDGE_HIGH: u1,
-            GPIO_QSPI_SD3_LEVEL_LOW: u1,
-            GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD3_EDGE_LOW: u1,
-            GPIO_QSPI_SD3_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x50);
-
-        /// address: 0x40018054
-        /// Interrupt status after masking & forcing for dormant_wake
-        pub const DORMANT_WAKE_INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-            GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-            GPIO_QSPI_SCLK_EDGE_LOW: u1,
-            GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-            GPIO_QSPI_SS_LEVEL_LOW: u1,
-            GPIO_QSPI_SS_LEVEL_HIGH: u1,
-            GPIO_QSPI_SS_EDGE_LOW: u1,
-            GPIO_QSPI_SS_EDGE_HIGH: u1,
-            GPIO_QSPI_SD0_LEVEL_LOW: u1,
-            GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD0_EDGE_LOW: u1,
-            GPIO_QSPI_SD0_EDGE_HIGH: u1,
-            GPIO_QSPI_SD1_LEVEL_LOW: u1,
-            GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD1_EDGE_LOW: u1,
-            GPIO_QSPI_SD1_EDGE_HIGH: u1,
-            GPIO_QSPI_SD2_LEVEL_LOW: u1,
-            GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD2_EDGE_LOW: u1,
-            GPIO_QSPI_SD2_EDGE_HIGH: u1,
-            GPIO_QSPI_SD3_LEVEL_LOW: u1,
-            GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-            GPIO_QSPI_SD3_EDGE_LOW: u1,
-            GPIO_QSPI_SD3_EDGE_HIGH: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x54);
-    };
-    pub const PADS_BANK0 = struct {
-        pub const base_address = 0x4001c000;
-        pub const version = "1";
-
-        /// address: 0x4001c000
-        /// Voltage select. Per bank control
-        pub const VOLTAGE_SELECT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0);
-
-        /// address: 0x4001c004
-        /// Pad control register
-        pub const GPIO0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x4001c008
-        /// Pad control register
-        pub const GPIO1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x4001c00c
-        /// Pad control register
-        pub const GPIO2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x4001c010
-        /// Pad control register
-        pub const GPIO3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x10);
-
-        /// address: 0x4001c014
-        /// Pad control register
-        pub const GPIO4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x4001c018
-        /// Pad control register
-        pub const GPIO5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x4001c01c
-        /// Pad control register
-        pub const GPIO6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x1c);
-
-        /// address: 0x4001c020
-        /// Pad control register
-        pub const GPIO7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x20);
-
-        /// address: 0x4001c024
-        /// Pad control register
-        pub const GPIO8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x24);
-
-        /// address: 0x4001c028
-        /// Pad control register
-        pub const GPIO9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x28);
-
-        /// address: 0x4001c02c
-        /// Pad control register
-        pub const GPIO10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x2c);
-
-        /// address: 0x4001c030
-        /// Pad control register
-        pub const GPIO11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x30);
-
-        /// address: 0x4001c034
-        /// Pad control register
-        pub const GPIO12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x34);
-
-        /// address: 0x4001c038
-        /// Pad control register
-        pub const GPIO13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x38);
-
-        /// address: 0x4001c03c
-        /// Pad control register
-        pub const GPIO14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x3c);
-
-        /// address: 0x4001c040
-        /// Pad control register
-        pub const GPIO15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x40);
-
-        /// address: 0x4001c044
-        /// Pad control register
-        pub const GPIO16 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x44);
-
-        /// address: 0x4001c048
-        /// Pad control register
-        pub const GPIO17 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x48);
-
-        /// address: 0x4001c04c
-        /// Pad control register
-        pub const GPIO18 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x4c);
-
-        /// address: 0x4001c050
-        /// Pad control register
-        pub const GPIO19 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x50);
-
-        /// address: 0x4001c054
-        /// Pad control register
-        pub const GPIO20 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x54);
-
-        /// address: 0x4001c058
-        /// Pad control register
-        pub const GPIO21 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x58);
-
-        /// address: 0x4001c05c
-        /// Pad control register
-        pub const GPIO22 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x5c);
-
-        /// address: 0x4001c060
-        /// Pad control register
-        pub const GPIO23 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x60);
-
-        /// address: 0x4001c064
-        /// Pad control register
-        pub const GPIO24 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x64);
-
-        /// address: 0x4001c068
-        /// Pad control register
-        pub const GPIO25 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x68);
-
-        /// address: 0x4001c06c
-        /// Pad control register
-        pub const GPIO26 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x6c);
-
-        /// address: 0x4001c070
-        /// Pad control register
-        pub const GPIO27 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x70);
-
-        /// address: 0x4001c074
-        /// Pad control register
-        pub const GPIO28 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x74);
-
-        /// address: 0x4001c078
-        /// Pad control register
-        pub const GPIO29 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x78);
-
-        /// address: 0x4001c07c
-        /// Pad control register
-        pub const SWCLK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x7c);
-
-        /// address: 0x4001c080
-        /// Pad control register
-        pub const SWD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x80);
-    };
-    pub const PADS_QSPI = struct {
-        pub const base_address = 0x40020000;
-        pub const version = "1";
-
-        /// address: 0x40020000
-        /// Voltage select. Per bank control
-        pub const VOLTAGE_SELECT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0);
-
-        /// address: 0x40020004
-        /// Pad control register
-        pub const GPIO_QSPI_SCLK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40020008
-        /// Pad control register
-        pub const GPIO_QSPI_SD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x4002000c
-        /// Pad control register
-        pub const GPIO_QSPI_SD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x40020010
-        /// Pad control register
-        pub const GPIO_QSPI_SD2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x10);
-
-        /// address: 0x40020014
-        /// Pad control register
-        pub const GPIO_QSPI_SD3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x40020018
-        /// Pad control register
-        pub const GPIO_QSPI_SS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Slew rate control. 1 = Fast, 0 = Slow
-            SLEWFAST: u1,
-            /// Enable schmitt trigger
-            SCHMITT: u1,
-            /// Pull down enable
-            PDE: u1,
-            /// Pull up enable
-            PUE: u1,
-            /// Drive strength.
-            DRIVE: u2,
-            /// Input enable
-            IE: u1,
-            /// Output disable. Has priority over output enable from peripherals
-            OD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x18);
-    };
-
-    /// Controls the crystal oscillator
-    pub const XOSC = struct {
-        pub const base_address = 0x40024000;
-        pub const version = "1";
-
-        /// address: 0x40024000
-        /// Crystal Oscillator Control
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Frequency range. This resets to 0xAA0 and cannot be changed.
-            FREQ_RANGE: u12,
-            /// On power-up this field is initialised to DISABLE and the chip runs from the
-            /// ROSC.\n
-            /// If the chip has subsequently been programmed to run from the XOSC then setting
-            /// this field to DISABLE may lock-up the chip. If this is a concern then run the
-            /// clk_ref from the ROSC and enable the clk_sys RESUS feature.\n
-            /// The 12-bit code is intended to give some protection against accidental writes.
-            /// An invalid setting will enable the oscillator.
-            ENABLE: u12,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40024004
-        /// Crystal Oscillator Status
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The current frequency range setting, always reads 0
-            FREQ_RANGE: u2,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            /// Oscillator is enabled but not necessarily running and stable, resets to 0
-            ENABLED: u1,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            reserved18: u1 = 0,
-            reserved19: u1 = 0,
-            reserved20: u1 = 0,
-            /// An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT
-            BADWRITE: u1,
-            reserved21: u1 = 0,
-            reserved22: u1 = 0,
-            reserved23: u1 = 0,
-            reserved24: u1 = 0,
-            reserved25: u1 = 0,
-            reserved26: u1 = 0,
-            /// Oscillator is running and stable
-            STABLE: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x40024008
-        /// Crystal Oscillator pause control\n
-        /// This is used to save power by pausing the XOSC\n
-        /// On power-up this field is initialised to WAKE\n
-        /// An invalid write will also select WAKE\n
-        /// WARNING: stop the PLLs before selecting dormant mode\n
-        /// WARNING: setup the irq before selecting dormant mode
-        pub const DORMANT = @intToPtr(*volatile u32, base_address + 0x8);
-
-        /// address: 0x4002400c
-        /// Controls the startup delay
-        pub const STARTUP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx
-            /// 50 000 cycles.
-            DELAY: u14,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            /// Multiplies the startup_delay by 4. This is of little value to the user given
-            /// that the delay can be programmed directly.
-            X4: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x4002401c
-        /// A down counter running at the xosc frequency which counts to zero and stops.\n
-        /// To start the counter write a non-zero value.\n
-        /// Can be used for short software pauses when setting up time sensitive hardware.
-        pub const COUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x1c);
-    };
-    pub const PLL_SYS = struct {
-        pub const base_address = 0x40028000;
-        pub const version = "1";
-
-        /// address: 0x40028000
-        /// Control and Status\n
-        /// GENERAL CONSTRAINTS:\n
-        /// Reference clock frequency min=5MHz, max=800MHz\n
-        /// Feedback divider min=16, max=320\n
-        /// VCO frequency min=400MHz, max=1600MHz
-        pub const CS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Divides the PLL input reference clock.\n
-            /// Behaviour is undefined for div=0.\n
-            /// PLL output will be unpredictable during refdiv changes, wait for lock=1 before
-            /// using it.
-            REFDIV: u6,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// Passes the reference clock to the output instead of the divided VCO. The VCO
-            /// continues to run so the user can switch between the reference clock and the
-            /// divided VCO but the output will glitch when doing so.
-            BYPASS: u1,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            reserved18: u1 = 0,
-            reserved19: u1 = 0,
-            reserved20: u1 = 0,
-            reserved21: u1 = 0,
-            reserved22: u1 = 0,
-            reserved23: u1 = 0,
-            /// PLL is locked
-            LOCK: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x40028004
-        /// Controls the PLL power modes.
-        pub const PWR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// PLL powerdown\n
-            /// To save power set high when PLL output not required.
-            PD: u1,
-            reserved0: u1 = 0,
-            /// PLL DSM powerdown\n
-            /// Nothing is achieved by setting this low.
-            DSMPD: u1,
-            /// PLL post divider powerdown\n
-            /// To save power set high when PLL output not required or bypass=1.
-            POSTDIVPD: u1,
-            reserved1: u1 = 0,
-            /// PLL VCO powerdown\n
-            /// To save power set high when PLL output not required or bypass=1.
-            VCOPD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40028008
-        /// Feedback divisor\n
-        /// (note: this PLL does not support fractional division)
-        pub const FBDIV_INT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x8);
-
-        /// address: 0x4002800c
-        /// Controls the PLL post dividers for the primary output\n
-        /// (note: this PLL does not have a secondary output)\n
-        /// the primary output is driven from VCO divided by postdiv1*postdiv2
-        pub const PRIM = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            /// divide by 1-7
-            POSTDIV2: u3,
-            reserved12: u1 = 0,
-            /// divide by 1-7
-            POSTDIV1: u3,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-        }), base_address + 0xc);
-    };
-    pub const PLL_USB = struct {
-        pub const base_address = 0x4002c000;
-
-        /// address: 0x4002c000
-        /// Control and Status\n
-        /// GENERAL CONSTRAINTS:\n
-        /// Reference clock frequency min=5MHz, max=800MHz\n
-        /// Feedback divider min=16, max=320\n
-        /// VCO frequency min=400MHz, max=1600MHz
-        pub const CS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Divides the PLL input reference clock.\n
-            /// Behaviour is undefined for div=0.\n
-            /// PLL output will be unpredictable during refdiv changes, wait for lock=1 before
-            /// using it.
-            REFDIV: u6,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// Passes the reference clock to the output instead of the divided VCO. The VCO
-            /// continues to run so the user can switch between the reference clock and the
-            /// divided VCO but the output will glitch when doing so.
-            BYPASS: u1,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            reserved18: u1 = 0,
-            reserved19: u1 = 0,
-            reserved20: u1 = 0,
-            reserved21: u1 = 0,
-            reserved22: u1 = 0,
-            reserved23: u1 = 0,
-            /// PLL is locked
-            LOCK: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x4002c004
-        /// Controls the PLL power modes.
-        pub const PWR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// PLL powerdown\n
-            /// To save power set high when PLL output not required.
-            PD: u1,
-            reserved0: u1 = 0,
-            /// PLL DSM powerdown\n
-            /// Nothing is achieved by setting this low.
-            DSMPD: u1,
-            /// PLL post divider powerdown\n
-            /// To save power set high when PLL output not required or bypass=1.
-            POSTDIVPD: u1,
-            reserved1: u1 = 0,
-            /// PLL VCO powerdown\n
-            /// To save power set high when PLL output not required or bypass=1.
-            VCOPD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x4002c008
-        /// Feedback divisor\n
-        /// (note: this PLL does not support fractional division)
-        pub const FBDIV_INT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x8);
-
-        /// address: 0x4002c00c
-        /// Controls the PLL post dividers for the primary output\n
-        /// (note: this PLL does not have a secondary output)\n
-        /// the primary output is driven from VCO divided by postdiv1*postdiv2
-        pub const PRIM = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            /// divide by 1-7
-            POSTDIV2: u3,
-            reserved12: u1 = 0,
-            /// divide by 1-7
-            POSTDIV1: u3,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-        }), base_address + 0xc);
-    };
-
-    /// Register block for busfabric control signals and performance counters
-    pub const BUSCTRL = struct {
-        pub const base_address = 0x40030000;
-        pub const version = "1";
-
-        /// address: 0x40030000
-        /// Set the priority of each master for bus arbitration.
-        pub const BUS_PRIORITY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0 - low priority, 1 - high priority
-            PROC0: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            /// 0 - low priority, 1 - high priority
-            PROC1: u1,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            /// 0 - low priority, 1 - high priority
-            DMA_R: u1,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// 0 - low priority, 1 - high priority
-            DMA_W: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40030004
-        /// Bus priority acknowledge
-        pub const BUS_PRIORITY_ACK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4);
-
-        /// address: 0x40030008
-        /// Bus fabric performance counter 0
-        pub const PERFCTR0 = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x8);
-
-        /// address: 0x4003000c
-        /// Bus fabric performance event select for PERFCTR0
-        pub const PERFSEL0 = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc);
-
-        /// address: 0x40030010
-        /// Bus fabric performance counter 1
-        pub const PERFCTR1 = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x10);
-
-        /// address: 0x40030014
-        /// Bus fabric performance event select for PERFCTR1
-        pub const PERFSEL1 = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x14);
-
-        /// address: 0x40030018
-        /// Bus fabric performance counter 2
-        pub const PERFCTR2 = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x18);
-
-        /// address: 0x4003001c
-        /// Bus fabric performance event select for PERFCTR2
-        pub const PERFSEL2 = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x1c);
-
-        /// address: 0x40030020
-        /// Bus fabric performance counter 3
-        pub const PERFCTR3 = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x20);
-
-        /// address: 0x40030024
-        /// Bus fabric performance event select for PERFCTR3
-        pub const PERFSEL3 = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x24);
-    };
-    pub const UART0 = struct {
-        pub const base_address = 0x40034000;
-        pub const version = "1";
-
-        /// address: 0x40034000
-        /// Data Register, UARTDR
-        pub const UARTDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive (read) data character. Transmit (write) data character.
-            DATA: u8,
-            /// Framing error. When set to 1, it indicates that the received character did not
-            /// have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is
-            /// associated with the character at the top of the FIFO.
-            FE: u1,
-            /// Parity error. When set to 1, it indicates that the parity of the received data
-            /// character does not match the parity that the EPS and SPS bits in the Line
-            /// Control Register, UARTLCR_H. In FIFO mode, this error is associated with the
-            /// character at the top of the FIFO.
-            PE: u1,
-            /// Break error. This bit is set to 1 if a break condition was detected, indicating
-            /// that the received data input was held LOW for longer than a full-word
-            /// transmission time (defined as start, data, parity and stop bits). In FIFO mode,
-            /// this error is associated with the character at the top of the FIFO. When a break
-            /// occurs, only one 0 character is loaded into the FIFO. The next character is only
-            /// enabled after the receive data input goes to a 1 (marking state), and the next
-            /// valid start bit is received.
-            BE: u1,
-            /// Overrun error. This bit is set to 1 if data is received and the receive FIFO is
-            /// already full. This is cleared to 0 once there is an empty space in the FIFO and
-            /// a new character can be written to it.
-            OE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40034004
-        /// Receive Status Register/Error Clear Register, UARTRSR/UARTECR
-        pub const UARTRSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Framing error. When set to 1, it indicates that the received character did not
-            /// have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a
-            /// write to UARTECR. In FIFO mode, this error is associated with the character at
-            /// the top of the FIFO.
-            FE: u1,
-            /// Parity error. When set to 1, it indicates that the parity of the received data
-            /// character does not match the parity that the EPS and SPS bits in the Line
-            /// Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In
-            /// FIFO mode, this error is associated with the character at the top of the FIFO.
-            PE: u1,
-            /// Break error. This bit is set to 1 if a break condition was detected, indicating
-            /// that the received data input was held LOW for longer than a full-word
-            /// transmission time (defined as start, data, parity, and stop bits). This bit is
-            /// cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated
-            /// with the character at the top of the FIFO. When a break occurs, only one 0
-            /// character is loaded into the FIFO. The next character is only enabled after the
-            /// receive data input goes to a 1 (marking state) and the next valid start bit is
-            /// received.
-            BE: u1,
-            /// Overrun error. This bit is set to 1 if data is received and the FIFO is already
-            /// full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain
-            /// valid because no more data is written when the FIFO is full, only the contents
-            /// of the shift register are overwritten. The CPU must now read the data, to empty
-            /// the FIFO.
-            OE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40034018
-        /// Flag Register, UARTFR
-        pub const UARTFR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Clear to send. This bit is the complement of the UART clear to send, nUARTCTS,
-            /// modem status input. That is, the bit is 1 when nUARTCTS is LOW.
-            CTS: u1,
-            /// Data set ready. This bit is the complement of the UART data set ready, nUARTDSR,
-            /// modem status input. That is, the bit is 1 when nUARTDSR is LOW.
-            DSR: u1,
-            /// Data carrier detect. This bit is the complement of the UART data carrier detect,
-            /// nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.
-            DCD: u1,
-            /// UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit
-            /// remains set until the complete byte, including all the stop bits, has been sent
-            /// from the shift register. This bit is set as soon as the transmit FIFO becomes
-            /// non-empty, regardless of whether the UART is enabled or not.
-            BUSY: u1,
-            /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit
-            /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the
-            /// receive holding register is empty. If the FIFO is enabled, the RXFE bit is set
-            /// when the receive FIFO is empty.
-            RXFE: u1,
-            /// Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit
-            /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the
-            /// transmit holding register is full. If the FIFO is enabled, the TXFF bit is set
-            /// when the transmit FIFO is full.
-            TXFF: u1,
-            /// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit
-            /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the
-            /// receive holding register is full. If the FIFO is enabled, the RXFF bit is set
-            /// when the receive FIFO is full.
-            RXFF: u1,
-            /// Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit
-            /// in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is
-            /// set when the transmit holding register is empty. If the FIFO is enabled, the
-            /// TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if
-            /// there is data in the transmit shift register.
-            TXFE: u1,
-            /// Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI,
-            /// modem status input. That is, the bit is 1 when nUARTRI is LOW.
-            RI: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x40034020
-        /// IrDA Low-Power Counter Register, UARTILPR
-        pub const UARTILPR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 8-bit low-power divisor value. These bits are cleared to 0 at reset.
-            ILPDVSR: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x20);
-
-        /// address: 0x40034024
-        /// Integer Baud Rate Register, UARTIBRD
-        pub const UARTIBRD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The integer baud rate divisor. These bits are cleared to 0 on reset.
-            BAUD_DIVINT: u16,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x24);
-
-        /// address: 0x40034028
-        /// Fractional Baud Rate Register, UARTFBRD
-        pub const UARTFBRD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The fractional baud rate divisor. These bits are cleared to 0 on reset.
-            BAUD_DIVFRAC: u6,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-        }), base_address + 0x28);
-
-        /// address: 0x4003402c
-        /// Line Control Register, UARTLCR_H
-        pub const UARTLCR_H = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Send break. If this bit is set to 1, a low-level is continually output on the
-            /// UARTTXD output, after completing transmission of the current character. For the
-            /// proper execution of the break command, the software must set this bit for at
-            /// least two complete frames. For normal use, this bit must be cleared to 0.
-            BRK: u1,
-            /// Parity enable: 0 = parity is disabled and no parity bit added to the data frame
-            /// 1 = parity checking and generation is enabled.
-            PEN: u1,
-            /// Even parity select. Controls the type of parity the UART uses during
-            /// transmission and reception: 0 = odd parity. The UART generates or checks for an
-            /// odd number of 1s in the data and parity bits. 1 = even parity. The UART
-            /// generates or checks for an even number of 1s in the data and parity bits. This
-            /// bit has no effect when the PEN bit disables parity checking and generation.
-            EPS: u1,
-            /// Two stop bits select. If this bit is set to 1, two stop bits are transmitted at
-            /// the end of the frame. The receive logic does not check for two stop bits being
-            /// received.
-            STP2: u1,
-            /// Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become
-            /// 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled
-            /// (FIFO mode).
-            FEN: u1,
-            /// Word length. These bits indicate the number of data bits transmitted or received
-            /// in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.
-            WLEN: u2,
-            /// Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit
-            /// is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1
-            /// then the parity bit is transmitted and checked as a 0. This bit has no effect
-            /// when the PEN bit disables parity checking and generation.
-            SPS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x2c);
-
-        /// address: 0x40034030
-        /// Control Register, UARTCR
-        pub const UARTCR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// UART enable: 0 = UART is disabled. If the UART is disabled in the middle of
-            /// transmission or reception, it completes the current character before stopping. 1
-            /// = the UART is enabled. Data transmission and reception occurs for either UART
-            /// signals or SIR signals depending on the setting of the SIREN bit.
-            UARTEN: u1,
-            /// SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse
-            /// generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC
-            /// is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD
-            /// remains HIGH, in the marking state. Signal transitions on UARTRXD or modem
-            /// status inputs have no effect. This bit has no effect if the UARTEN bit disables
-            /// the UART.
-            SIREN: u1,
-            /// SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is
-            /// cleared to 0, low-level bits are transmitted as an active high pulse with a
-            /// width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are
-            /// transmitted with a pulse width that is 3 times the period of the IrLPBaud16
-            /// input signal, regardless of the selected bit rate. Setting this bit uses less
-            /// power, but might reduce transmission distances.
-            SIRLP: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the
-            /// SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT
-            /// path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test
-            /// register must be set to 1 to override the normal half-duplex SIR operation. This
-            /// must be the requirement for accessing the test registers during normal
-            /// operation, and SIRTEST must be cleared to 0 when loopback testing is finished.
-            /// This feature reduces the amount of external coupling required during system
-            /// test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path
-            /// is fed through to the UARTRXD path. In either SIR mode or UART mode, when this
-            /// bit is set, the modem outputs are also fed through to the modem inputs. This bit
-            /// is cleared to 0 on reset, to disable loopback.
-            LBE: u1,
-            /// Transmit enable. If this bit is set to 1, the transmit section of the UART is
-            /// enabled. Data transmission occurs for either UART signals, or SIR signals
-            /// depending on the setting of the SIREN bit. When the UART is disabled in the
-            /// middle of transmission, it completes the current character before stopping.
-            TXE: u1,
-            /// Receive enable. If this bit is set to 1, the receive section of the UART is
-            /// enabled. Data reception occurs for either UART signals or SIR signals depending
-            /// on the setting of the SIREN bit. When the UART is disabled in the middle of
-            /// reception, it completes the current character before stopping.
-            RXE: u1,
-            /// Data transmit ready. This bit is the complement of the UART data transmit ready,
-            /// nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then
-            /// nUARTDTR is LOW.
-            DTR: u1,
-            /// Request to send. This bit is the complement of the UART request to send,
-            /// nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then
-            /// nUARTRTS is LOW.
-            RTS: u1,
-            /// This bit is the complement of the UART Out1 (nUARTOut1) modem status output.
-            /// That is, when the bit is programmed to a 1 the output is 0. For DTE this can be
-            /// used as Data Carrier Detect (DCD).
-            OUT1: u1,
-            /// This bit is the complement of the UART Out2 (nUARTOut2) modem status output.
-            /// That is, when the bit is programmed to a 1, the output is 0. For DTE this can be
-            /// used as Ring Indicator (RI).
-            OUT2: u1,
-            /// RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow
-            /// control is enabled. Data is only requested when there is space in the receive
-            /// FIFO for it to be received.
-            RTSEN: u1,
-            /// CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow
-            /// control is enabled. Data is only transmitted when the nUARTCTS signal is
-            /// asserted.
-            CTSEN: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x30);
-
-        /// address: 0x40034034
-        /// Interrupt FIFO Level Select Register, UARTIFLS
-        pub const UARTIFLS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit interrupt FIFO level select. The trigger points for the transmit
-            /// interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 =
-            /// Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full
-            /// b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8
-            /// full b101-b111 = reserved.
-            TXIFLSEL: u3,
-            /// Receive interrupt FIFO level select. The trigger points for the receive
-            /// interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 =
-            /// Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full
-            /// b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8
-            /// full b101-b111 = reserved.
-            RXIFLSEL: u3,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-        }), base_address + 0x34);
-
-        /// address: 0x40034038
-        /// Interrupt Mask Set/Clear Register, UARTIMSC
-        pub const UARTIMSC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR
-            /// interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            RIMIM: u1,
-            /// nUARTCTS modem interrupt mask. A read returns the current mask for the
-            /// UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is
-            /// set. A write of 0 clears the mask.
-            CTSMIM: u1,
-            /// nUARTDCD modem interrupt mask. A read returns the current mask for the
-            /// UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is
-            /// set. A write of 0 clears the mask.
-            DCDMIM: u1,
-            /// nUARTDSR modem interrupt mask. A read returns the current mask for the
-            /// UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is
-            /// set. A write of 0 clears the mask.
-            DSRMIM: u1,
-            /// Receive interrupt mask. A read returns the current mask for the UARTRXINTR
-            /// interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            RXIM: u1,
-            /// Transmit interrupt mask. A read returns the current mask for the UARTTXINTR
-            /// interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            TXIM: u1,
-            /// Receive timeout interrupt mask. A read returns the current mask for the
-            /// UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is
-            /// set. A write of 0 clears the mask.
-            RTIM: u1,
-            /// Framing error interrupt mask. A read returns the current mask for the UARTFEINTR
-            /// interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            FEIM: u1,
-            /// Parity error interrupt mask. A read returns the current mask for the UARTPEINTR
-            /// interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            PEIM: u1,
-            /// Break error interrupt mask. A read returns the current mask for the UARTBEINTR
-            /// interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            BEIM: u1,
-            /// Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR
-            /// interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            OEIM: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x38);
-
-        /// address: 0x4003403c
-        /// Raw Interrupt Status Register, UARTRIS
-        pub const UARTRIS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// nUARTRI modem interrupt status. Returns the raw interrupt state of the
-            /// UARTRIINTR interrupt.
-            RIRMIS: u1,
-            /// nUARTCTS modem interrupt status. Returns the raw interrupt state of the
-            /// UARTCTSINTR interrupt.
-            CTSRMIS: u1,
-            /// nUARTDCD modem interrupt status. Returns the raw interrupt state of the
-            /// UARTDCDINTR interrupt.
-            DCDRMIS: u1,
-            /// nUARTDSR modem interrupt status. Returns the raw interrupt state of the
-            /// UARTDSRINTR interrupt.
-            DSRRMIS: u1,
-            /// Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR
-            /// interrupt.
-            RXRIS: u1,
-            /// Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR
-            /// interrupt.
-            TXRIS: u1,
-            /// Receive timeout interrupt status. Returns the raw interrupt state of the
-            /// UARTRTINTR interrupt. a
-            RTRIS: u1,
-            /// Framing error interrupt status. Returns the raw interrupt state of the
-            /// UARTFEINTR interrupt.
-            FERIS: u1,
-            /// Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR
-            /// interrupt.
-            PERIS: u1,
-            /// Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR
-            /// interrupt.
-            BERIS: u1,
-            /// Overrun error interrupt status. Returns the raw interrupt state of the
-            /// UARTOEINTR interrupt.
-            OERIS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x3c);
-
-        /// address: 0x40034040
-        /// Masked Interrupt Status Register, UARTMIS
-        pub const UARTMIS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// nUARTRI modem masked interrupt status. Returns the masked interrupt state of the
-            /// UARTRIINTR interrupt.
-            RIMMIS: u1,
-            /// nUARTCTS modem masked interrupt status. Returns the masked interrupt state of
-            /// the UARTCTSINTR interrupt.
-            CTSMMIS: u1,
-            /// nUARTDCD modem masked interrupt status. Returns the masked interrupt state of
-            /// the UARTDCDINTR interrupt.
-            DCDMMIS: u1,
-            /// nUARTDSR modem masked interrupt status. Returns the masked interrupt state of
-            /// the UARTDSRINTR interrupt.
-            DSRMMIS: u1,
-            /// Receive masked interrupt status. Returns the masked interrupt state of the
-            /// UARTRXINTR interrupt.
-            RXMIS: u1,
-            /// Transmit masked interrupt status. Returns the masked interrupt state of the
-            /// UARTTXINTR interrupt.
-            TXMIS: u1,
-            /// Receive timeout masked interrupt status. Returns the masked interrupt state of
-            /// the UARTRTINTR interrupt.
-            RTMIS: u1,
-            /// Framing error masked interrupt status. Returns the masked interrupt state of the
-            /// UARTFEINTR interrupt.
-            FEMIS: u1,
-            /// Parity error masked interrupt status. Returns the masked interrupt state of the
-            /// UARTPEINTR interrupt.
-            PEMIS: u1,
-            /// Break error masked interrupt status. Returns the masked interrupt state of the
-            /// UARTBEINTR interrupt.
-            BEMIS: u1,
-            /// Overrun error masked interrupt status. Returns the masked interrupt state of the
-            /// UARTOEINTR interrupt.
-            OEMIS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x40);
-
-        /// address: 0x40034044
-        /// Interrupt Clear Register, UARTICR
-        pub const UARTICR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.
-            RIMIC: u1,
-            /// nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.
-            CTSMIC: u1,
-            /// nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.
-            DCDMIC: u1,
-            /// nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.
-            DSRMIC: u1,
-            /// Receive interrupt clear. Clears the UARTRXINTR interrupt.
-            RXIC: u1,
-            /// Transmit interrupt clear. Clears the UARTTXINTR interrupt.
-            TXIC: u1,
-            /// Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.
-            RTIC: u1,
-            /// Framing error interrupt clear. Clears the UARTFEINTR interrupt.
-            FEIC: u1,
-            /// Parity error interrupt clear. Clears the UARTPEINTR interrupt.
-            PEIC: u1,
-            /// Break error interrupt clear. Clears the UARTBEINTR interrupt.
-            BEIC: u1,
-            /// Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
-            OEIC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x44);
-
-        /// address: 0x40034048
-        /// DMA Control Register, UARTDMACR
-        pub const UARTDMACR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is
-            /// enabled.
-            RXDMAE: u1,
-            /// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is
-            /// enabled.
-            TXDMAE: u1,
-            /// DMA on error. If this bit is set to 1, the DMA receive request outputs,
-            /// UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is
-            /// asserted.
-            DMAONERR: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-        }), base_address + 0x48);
-
-        /// address: 0x40034fe0
-        /// UARTPeriphID0 Register
-        pub const UARTPERIPHID0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x11
-            PARTNUMBER0: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe0);
-
-        /// address: 0x40034fe4
-        /// UARTPeriphID1 Register
-        pub const UARTPERIPHID1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x0
-            PARTNUMBER1: u4,
-            /// These bits read back as 0x1
-            DESIGNER0: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe4);
-
-        /// address: 0x40034fe8
-        /// UARTPeriphID2 Register
-        pub const UARTPERIPHID2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x4
-            DESIGNER1: u4,
-            /// This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4
-            /// 0x2 r1p5 0x3
-            REVISION: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe8);
-
-        /// address: 0x40034fec
-        /// UARTPeriphID3 Register
-        pub const UARTPERIPHID3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x00
-            CONFIGURATION: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfec);
-
-        /// address: 0x40034ff0
-        /// UARTPCellID0 Register
-        pub const UARTPCELLID0 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff0);
-
-        /// address: 0x40034ff4
-        /// UARTPCellID1 Register
-        pub const UARTPCELLID1 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff4);
-
-        /// address: 0x40034ff8
-        /// UARTPCellID2 Register
-        pub const UARTPCELLID2 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff8);
-
-        /// address: 0x40034ffc
-        /// UARTPCellID3 Register
-        pub const UARTPCELLID3 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xffc);
-    };
-    pub const UART1 = struct {
-        pub const base_address = 0x40038000;
-
-        /// address: 0x40038000
-        /// Data Register, UARTDR
-        pub const UARTDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive (read) data character. Transmit (write) data character.
-            DATA: u8,
-            /// Framing error. When set to 1, it indicates that the received character did not
-            /// have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is
-            /// associated with the character at the top of the FIFO.
-            FE: u1,
-            /// Parity error. When set to 1, it indicates that the parity of the received data
-            /// character does not match the parity that the EPS and SPS bits in the Line
-            /// Control Register, UARTLCR_H. In FIFO mode, this error is associated with the
-            /// character at the top of the FIFO.
-            PE: u1,
-            /// Break error. This bit is set to 1 if a break condition was detected, indicating
-            /// that the received data input was held LOW for longer than a full-word
-            /// transmission time (defined as start, data, parity and stop bits). In FIFO mode,
-            /// this error is associated with the character at the top of the FIFO. When a break
-            /// occurs, only one 0 character is loaded into the FIFO. The next character is only
-            /// enabled after the receive data input goes to a 1 (marking state), and the next
-            /// valid start bit is received.
-            BE: u1,
-            /// Overrun error. This bit is set to 1 if data is received and the receive FIFO is
-            /// already full. This is cleared to 0 once there is an empty space in the FIFO and
-            /// a new character can be written to it.
-            OE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40038004
-        /// Receive Status Register/Error Clear Register, UARTRSR/UARTECR
-        pub const UARTRSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Framing error. When set to 1, it indicates that the received character did not
-            /// have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a
-            /// write to UARTECR. In FIFO mode, this error is associated with the character at
-            /// the top of the FIFO.
-            FE: u1,
-            /// Parity error. When set to 1, it indicates that the parity of the received data
-            /// character does not match the parity that the EPS and SPS bits in the Line
-            /// Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In
-            /// FIFO mode, this error is associated with the character at the top of the FIFO.
-            PE: u1,
-            /// Break error. This bit is set to 1 if a break condition was detected, indicating
-            /// that the received data input was held LOW for longer than a full-word
-            /// transmission time (defined as start, data, parity, and stop bits). This bit is
-            /// cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated
-            /// with the character at the top of the FIFO. When a break occurs, only one 0
-            /// character is loaded into the FIFO. The next character is only enabled after the
-            /// receive data input goes to a 1 (marking state) and the next valid start bit is
-            /// received.
-            BE: u1,
-            /// Overrun error. This bit is set to 1 if data is received and the FIFO is already
-            /// full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain
-            /// valid because no more data is written when the FIFO is full, only the contents
-            /// of the shift register are overwritten. The CPU must now read the data, to empty
-            /// the FIFO.
-            OE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40038018
-        /// Flag Register, UARTFR
-        pub const UARTFR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Clear to send. This bit is the complement of the UART clear to send, nUARTCTS,
-            /// modem status input. That is, the bit is 1 when nUARTCTS is LOW.
-            CTS: u1,
-            /// Data set ready. This bit is the complement of the UART data set ready, nUARTDSR,
-            /// modem status input. That is, the bit is 1 when nUARTDSR is LOW.
-            DSR: u1,
-            /// Data carrier detect. This bit is the complement of the UART data carrier detect,
-            /// nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.
-            DCD: u1,
-            /// UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit
-            /// remains set until the complete byte, including all the stop bits, has been sent
-            /// from the shift register. This bit is set as soon as the transmit FIFO becomes
-            /// non-empty, regardless of whether the UART is enabled or not.
-            BUSY: u1,
-            /// Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit
-            /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the
-            /// receive holding register is empty. If the FIFO is enabled, the RXFE bit is set
-            /// when the receive FIFO is empty.
-            RXFE: u1,
-            /// Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit
-            /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the
-            /// transmit holding register is full. If the FIFO is enabled, the TXFF bit is set
-            /// when the transmit FIFO is full.
-            TXFF: u1,
-            /// Receive FIFO full. The meaning of this bit depends on the state of the FEN bit
-            /// in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the
-            /// receive holding register is full. If the FIFO is enabled, the RXFF bit is set
-            /// when the receive FIFO is full.
-            RXFF: u1,
-            /// Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit
-            /// in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is
-            /// set when the transmit holding register is empty. If the FIFO is enabled, the
-            /// TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if
-            /// there is data in the transmit shift register.
-            TXFE: u1,
-            /// Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI,
-            /// modem status input. That is, the bit is 1 when nUARTRI is LOW.
-            RI: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x40038020
-        /// IrDA Low-Power Counter Register, UARTILPR
-        pub const UARTILPR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 8-bit low-power divisor value. These bits are cleared to 0 at reset.
-            ILPDVSR: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x20);
-
-        /// address: 0x40038024
-        /// Integer Baud Rate Register, UARTIBRD
-        pub const UARTIBRD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The integer baud rate divisor. These bits are cleared to 0 on reset.
-            BAUD_DIVINT: u16,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x24);
-
-        /// address: 0x40038028
-        /// Fractional Baud Rate Register, UARTFBRD
-        pub const UARTFBRD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The fractional baud rate divisor. These bits are cleared to 0 on reset.
-            BAUD_DIVFRAC: u6,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-        }), base_address + 0x28);
-
-        /// address: 0x4003802c
-        /// Line Control Register, UARTLCR_H
-        pub const UARTLCR_H = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Send break. If this bit is set to 1, a low-level is continually output on the
-            /// UARTTXD output, after completing transmission of the current character. For the
-            /// proper execution of the break command, the software must set this bit for at
-            /// least two complete frames. For normal use, this bit must be cleared to 0.
-            BRK: u1,
-            /// Parity enable: 0 = parity is disabled and no parity bit added to the data frame
-            /// 1 = parity checking and generation is enabled.
-            PEN: u1,
-            /// Even parity select. Controls the type of parity the UART uses during
-            /// transmission and reception: 0 = odd parity. The UART generates or checks for an
-            /// odd number of 1s in the data and parity bits. 1 = even parity. The UART
-            /// generates or checks for an even number of 1s in the data and parity bits. This
-            /// bit has no effect when the PEN bit disables parity checking and generation.
-            EPS: u1,
-            /// Two stop bits select. If this bit is set to 1, two stop bits are transmitted at
-            /// the end of the frame. The receive logic does not check for two stop bits being
-            /// received.
-            STP2: u1,
-            /// Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become
-            /// 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled
-            /// (FIFO mode).
-            FEN: u1,
-            /// Word length. These bits indicate the number of data bits transmitted or received
-            /// in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.
-            WLEN: u2,
-            /// Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit
-            /// is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1
-            /// then the parity bit is transmitted and checked as a 0. This bit has no effect
-            /// when the PEN bit disables parity checking and generation.
-            SPS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x2c);
-
-        /// address: 0x40038030
-        /// Control Register, UARTCR
-        pub const UARTCR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// UART enable: 0 = UART is disabled. If the UART is disabled in the middle of
-            /// transmission or reception, it completes the current character before stopping. 1
-            /// = the UART is enabled. Data transmission and reception occurs for either UART
-            /// signals or SIR signals depending on the setting of the SIREN bit.
-            UARTEN: u1,
-            /// SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse
-            /// generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC
-            /// is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD
-            /// remains HIGH, in the marking state. Signal transitions on UARTRXD or modem
-            /// status inputs have no effect. This bit has no effect if the UARTEN bit disables
-            /// the UART.
-            SIREN: u1,
-            /// SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is
-            /// cleared to 0, low-level bits are transmitted as an active high pulse with a
-            /// width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are
-            /// transmitted with a pulse width that is 3 times the period of the IrLPBaud16
-            /// input signal, regardless of the selected bit rate. Setting this bit uses less
-            /// power, but might reduce transmission distances.
-            SIRLP: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the
-            /// SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT
-            /// path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test
-            /// register must be set to 1 to override the normal half-duplex SIR operation. This
-            /// must be the requirement for accessing the test registers during normal
-            /// operation, and SIRTEST must be cleared to 0 when loopback testing is finished.
-            /// This feature reduces the amount of external coupling required during system
-            /// test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path
-            /// is fed through to the UARTRXD path. In either SIR mode or UART mode, when this
-            /// bit is set, the modem outputs are also fed through to the modem inputs. This bit
-            /// is cleared to 0 on reset, to disable loopback.
-            LBE: u1,
-            /// Transmit enable. If this bit is set to 1, the transmit section of the UART is
-            /// enabled. Data transmission occurs for either UART signals, or SIR signals
-            /// depending on the setting of the SIREN bit. When the UART is disabled in the
-            /// middle of transmission, it completes the current character before stopping.
-            TXE: u1,
-            /// Receive enable. If this bit is set to 1, the receive section of the UART is
-            /// enabled. Data reception occurs for either UART signals or SIR signals depending
-            /// on the setting of the SIREN bit. When the UART is disabled in the middle of
-            /// reception, it completes the current character before stopping.
-            RXE: u1,
-            /// Data transmit ready. This bit is the complement of the UART data transmit ready,
-            /// nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then
-            /// nUARTDTR is LOW.
-            DTR: u1,
-            /// Request to send. This bit is the complement of the UART request to send,
-            /// nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then
-            /// nUARTRTS is LOW.
-            RTS: u1,
-            /// This bit is the complement of the UART Out1 (nUARTOut1) modem status output.
-            /// That is, when the bit is programmed to a 1 the output is 0. For DTE this can be
-            /// used as Data Carrier Detect (DCD).
-            OUT1: u1,
-            /// This bit is the complement of the UART Out2 (nUARTOut2) modem status output.
-            /// That is, when the bit is programmed to a 1, the output is 0. For DTE this can be
-            /// used as Ring Indicator (RI).
-            OUT2: u1,
-            /// RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow
-            /// control is enabled. Data is only requested when there is space in the receive
-            /// FIFO for it to be received.
-            RTSEN: u1,
-            /// CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow
-            /// control is enabled. Data is only transmitted when the nUARTCTS signal is
-            /// asserted.
-            CTSEN: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x30);
-
-        /// address: 0x40038034
-        /// Interrupt FIFO Level Select Register, UARTIFLS
-        pub const UARTIFLS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit interrupt FIFO level select. The trigger points for the transmit
-            /// interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 =
-            /// Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full
-            /// b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8
-            /// full b101-b111 = reserved.
-            TXIFLSEL: u3,
-            /// Receive interrupt FIFO level select. The trigger points for the receive
-            /// interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 =
-            /// Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full
-            /// b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8
-            /// full b101-b111 = reserved.
-            RXIFLSEL: u3,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-        }), base_address + 0x34);
-
-        /// address: 0x40038038
-        /// Interrupt Mask Set/Clear Register, UARTIMSC
-        pub const UARTIMSC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR
-            /// interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            RIMIM: u1,
-            /// nUARTCTS modem interrupt mask. A read returns the current mask for the
-            /// UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is
-            /// set. A write of 0 clears the mask.
-            CTSMIM: u1,
-            /// nUARTDCD modem interrupt mask. A read returns the current mask for the
-            /// UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is
-            /// set. A write of 0 clears the mask.
-            DCDMIM: u1,
-            /// nUARTDSR modem interrupt mask. A read returns the current mask for the
-            /// UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is
-            /// set. A write of 0 clears the mask.
-            DSRMIM: u1,
-            /// Receive interrupt mask. A read returns the current mask for the UARTRXINTR
-            /// interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            RXIM: u1,
-            /// Transmit interrupt mask. A read returns the current mask for the UARTTXINTR
-            /// interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            TXIM: u1,
-            /// Receive timeout interrupt mask. A read returns the current mask for the
-            /// UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is
-            /// set. A write of 0 clears the mask.
-            RTIM: u1,
-            /// Framing error interrupt mask. A read returns the current mask for the UARTFEINTR
-            /// interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            FEIM: u1,
-            /// Parity error interrupt mask. A read returns the current mask for the UARTPEINTR
-            /// interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            PEIM: u1,
-            /// Break error interrupt mask. A read returns the current mask for the UARTBEINTR
-            /// interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            BEIM: u1,
-            /// Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR
-            /// interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write
-            /// of 0 clears the mask.
-            OEIM: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x38);
-
-        /// address: 0x4003803c
-        /// Raw Interrupt Status Register, UARTRIS
-        pub const UARTRIS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// nUARTRI modem interrupt status. Returns the raw interrupt state of the
-            /// UARTRIINTR interrupt.
-            RIRMIS: u1,
-            /// nUARTCTS modem interrupt status. Returns the raw interrupt state of the
-            /// UARTCTSINTR interrupt.
-            CTSRMIS: u1,
-            /// nUARTDCD modem interrupt status. Returns the raw interrupt state of the
-            /// UARTDCDINTR interrupt.
-            DCDRMIS: u1,
-            /// nUARTDSR modem interrupt status. Returns the raw interrupt state of the
-            /// UARTDSRINTR interrupt.
-            DSRRMIS: u1,
-            /// Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR
-            /// interrupt.
-            RXRIS: u1,
-            /// Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR
-            /// interrupt.
-            TXRIS: u1,
-            /// Receive timeout interrupt status. Returns the raw interrupt state of the
-            /// UARTRTINTR interrupt. a
-            RTRIS: u1,
-            /// Framing error interrupt status. Returns the raw interrupt state of the
-            /// UARTFEINTR interrupt.
-            FERIS: u1,
-            /// Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR
-            /// interrupt.
-            PERIS: u1,
-            /// Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR
-            /// interrupt.
-            BERIS: u1,
-            /// Overrun error interrupt status. Returns the raw interrupt state of the
-            /// UARTOEINTR interrupt.
-            OERIS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x3c);
-
-        /// address: 0x40038040
-        /// Masked Interrupt Status Register, UARTMIS
-        pub const UARTMIS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// nUARTRI modem masked interrupt status. Returns the masked interrupt state of the
-            /// UARTRIINTR interrupt.
-            RIMMIS: u1,
-            /// nUARTCTS modem masked interrupt status. Returns the masked interrupt state of
-            /// the UARTCTSINTR interrupt.
-            CTSMMIS: u1,
-            /// nUARTDCD modem masked interrupt status. Returns the masked interrupt state of
-            /// the UARTDCDINTR interrupt.
-            DCDMMIS: u1,
-            /// nUARTDSR modem masked interrupt status. Returns the masked interrupt state of
-            /// the UARTDSRINTR interrupt.
-            DSRMMIS: u1,
-            /// Receive masked interrupt status. Returns the masked interrupt state of the
-            /// UARTRXINTR interrupt.
-            RXMIS: u1,
-            /// Transmit masked interrupt status. Returns the masked interrupt state of the
-            /// UARTTXINTR interrupt.
-            TXMIS: u1,
-            /// Receive timeout masked interrupt status. Returns the masked interrupt state of
-            /// the UARTRTINTR interrupt.
-            RTMIS: u1,
-            /// Framing error masked interrupt status. Returns the masked interrupt state of the
-            /// UARTFEINTR interrupt.
-            FEMIS: u1,
-            /// Parity error masked interrupt status. Returns the masked interrupt state of the
-            /// UARTPEINTR interrupt.
-            PEMIS: u1,
-            /// Break error masked interrupt status. Returns the masked interrupt state of the
-            /// UARTBEINTR interrupt.
-            BEMIS: u1,
-            /// Overrun error masked interrupt status. Returns the masked interrupt state of the
-            /// UARTOEINTR interrupt.
-            OEMIS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x40);
-
-        /// address: 0x40038044
-        /// Interrupt Clear Register, UARTICR
-        pub const UARTICR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.
-            RIMIC: u1,
-            /// nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.
-            CTSMIC: u1,
-            /// nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.
-            DCDMIC: u1,
-            /// nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.
-            DSRMIC: u1,
-            /// Receive interrupt clear. Clears the UARTRXINTR interrupt.
-            RXIC: u1,
-            /// Transmit interrupt clear. Clears the UARTTXINTR interrupt.
-            TXIC: u1,
-            /// Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.
-            RTIC: u1,
-            /// Framing error interrupt clear. Clears the UARTFEINTR interrupt.
-            FEIC: u1,
-            /// Parity error interrupt clear. Clears the UARTPEINTR interrupt.
-            PEIC: u1,
-            /// Break error interrupt clear. Clears the UARTBEINTR interrupt.
-            BEIC: u1,
-            /// Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
-            OEIC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x44);
-
-        /// address: 0x40038048
-        /// DMA Control Register, UARTDMACR
-        pub const UARTDMACR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is
-            /// enabled.
-            RXDMAE: u1,
-            /// Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is
-            /// enabled.
-            TXDMAE: u1,
-            /// DMA on error. If this bit is set to 1, the DMA receive request outputs,
-            /// UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is
-            /// asserted.
-            DMAONERR: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-        }), base_address + 0x48);
-
-        /// address: 0x40038fe0
-        /// UARTPeriphID0 Register
-        pub const UARTPERIPHID0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x11
-            PARTNUMBER0: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe0);
-
-        /// address: 0x40038fe4
-        /// UARTPeriphID1 Register
-        pub const UARTPERIPHID1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x0
-            PARTNUMBER1: u4,
-            /// These bits read back as 0x1
-            DESIGNER0: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe4);
-
-        /// address: 0x40038fe8
-        /// UARTPeriphID2 Register
-        pub const UARTPERIPHID2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x4
-            DESIGNER1: u4,
-            /// This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4
-            /// 0x2 r1p5 0x3
-            REVISION: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe8);
-
-        /// address: 0x40038fec
-        /// UARTPeriphID3 Register
-        pub const UARTPERIPHID3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x00
-            CONFIGURATION: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfec);
-
-        /// address: 0x40038ff0
-        /// UARTPCellID0 Register
-        pub const UARTPCELLID0 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff0);
-
-        /// address: 0x40038ff4
-        /// UARTPCellID1 Register
-        pub const UARTPCELLID1 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff4);
-
-        /// address: 0x40038ff8
-        /// UARTPCellID2 Register
-        pub const UARTPCELLID2 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff8);
-
-        /// address: 0x40038ffc
-        /// UARTPCellID3 Register
-        pub const UARTPCELLID3 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xffc);
-    };
-    pub const SPI0 = struct {
-        pub const base_address = 0x4003c000;
-        pub const version = "1";
-
-        /// address: 0x4003c000
-        /// Control register 0, SSPCR0 on page 3-4
-        pub const SSPCR0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined
-            /// operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data.
-            /// 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
-            /// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data.
-            /// 1110 15-bit data. 1111 16-bit data.
-            DSS: u4,
-            /// Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame
-            /// format. 10 National Microwire frame format. 11 Reserved, undefined operation.
-            FRF: u2,
-            /// SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola
-            /// SPI frame format on page 2-10.
-            SPO: u1,
-            /// SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI
-            /// frame format on page 2-10.
-            SPH: u1,
-            /// Serial clock rate. The value SCR is used to generate the transmit and receive
-            /// bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where
-            /// CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and
-            /// SCR is a value from 0-255.
-            SCR: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x4003c004
-        /// Control register 1, SSPCR1 on page 3-5
-        pub const SSPCR1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit
-            /// serial shifter is connected to input of receive serial shifter internally.
-            LBM: u1,
-            /// Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation
-            /// enabled.
-            SSE: u1,
-            /// Master or slave mode select. This bit can be modified only when the PrimeCell
-            /// SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device
-            /// configured as slave.
-            MS: u1,
-            /// Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In
-            /// multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast
-            /// a message to all slaves in the system while ensuring that only one slave drives
-            /// data onto its serial output line. In such systems the RXD lines from multiple
-            /// slaves could be tied together. To operate in such systems, the SOD bit can be
-            /// set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP
-            /// can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
-            /// output in slave mode.
-            SOD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x4003c008
-        /// Data register, SSPDR on page 3-6
-        pub const SSPDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must
-            /// right-justify data when the PrimeCell SSP is programmed for a data size that is
-            /// less than 16 bits. Unused bits at the top are ignored by transmit logic. The
-            /// receive logic automatically right-justifies.
-            DATA: u16,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x4003c00c
-        /// Status register, SSPSR on page 3-7
-        pub const SSPSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.
-            TFE: u1,
-            /// Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not
-            /// full.
-            TNF: u1,
-            /// Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not
-            /// empty.
-            RNE: u1,
-            /// Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.
-            RFF: u1,
-            /// PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting
-            /// and/or receiving a frame or the transmit FIFO is not empty.
-            BSY: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x4003c010
-        /// Clock prescale register, SSPCPSR on page 3-8
-        pub const SSPCPSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Clock prescale divisor. Must be an even number from 2-254, depending on the
-            /// frequency of SSPCLK. The least significant bit always returns zero on reads.
-            CPSDVSR: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x10);
-
-        /// address: 0x4003c014
-        /// Interrupt mask set or clear register, SSPIMSC on page 3-9
-        pub const SSPIMSC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive overrun interrupt mask: 0 Receive FIFO written to while full condition
-            /// interrupt is masked. 1 Receive FIFO written to while full condition interrupt is
-            /// not masked.
-            RORIM: u1,
-            /// Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to
-            /// timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior
-            /// to timeout period interrupt is not masked.
-            RTIM: u1,
-            /// Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition
-            /// interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not
-            /// masked.
-            RXIM: u1,
-            /// Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition
-            /// interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is
-            /// not masked.
-            TXIM: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x4003c018
-        /// Raw interrupt status register, SSPRIS on page 3-10
-        pub const SSPRIS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
-            RORRIS: u1,
-            /// Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
-            RTRIS: u1,
-            /// Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
-            RXRIS: u1,
-            /// Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
-            TXRIS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x4003c01c
-        /// Masked interrupt status register, SSPMIS on page 3-11
-        pub const SSPMIS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Gives the receive over run masked interrupt status, after masking, of the
-            /// SSPRORINTR interrupt
-            RORMIS: u1,
-            /// Gives the receive timeout masked interrupt state, after masking, of the
-            /// SSPRTINTR interrupt
-            RTMIS: u1,
-            /// Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR
-            /// interrupt
-            RXMIS: u1,
-            /// Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR
-            /// interrupt
-            TXMIS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x1c);
-
-        /// address: 0x4003c020
-        /// Interrupt clear register, SSPICR on page 3-11
-        pub const SSPICR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Clears the SSPRORINTR interrupt
-            RORIC: u1,
-            /// Clears the SSPRTINTR interrupt
-            RTIC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x20);
-
-        /// address: 0x4003c024
-        /// DMA control register, SSPDMACR on page 3-12
-        pub const SSPDMACR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is
-            /// enabled.
-            RXDMAE: u1,
-            /// Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is
-            /// enabled.
-            TXDMAE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x24);
-
-        /// address: 0x4003cfe0
-        /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-        pub const SSPPERIPHID0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x22
-            PARTNUMBER0: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe0);
-
-        /// address: 0x4003cfe4
-        /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-        pub const SSPPERIPHID1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x0
-            PARTNUMBER1: u4,
-            /// These bits read back as 0x1
-            DESIGNER0: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe4);
-
-        /// address: 0x4003cfe8
-        /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-        pub const SSPPERIPHID2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x4
-            DESIGNER1: u4,
-            /// These bits return the peripheral revision
-            REVISION: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe8);
-
-        /// address: 0x4003cfec
-        /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-        pub const SSPPERIPHID3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x00
-            CONFIGURATION: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfec);
-
-        /// address: 0x4003cff0
-        /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-        pub const SSPPCELLID0 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff0);
-
-        /// address: 0x4003cff4
-        /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-        pub const SSPPCELLID1 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff4);
-
-        /// address: 0x4003cff8
-        /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-        pub const SSPPCELLID2 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff8);
-
-        /// address: 0x4003cffc
-        /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-        pub const SSPPCELLID3 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xffc);
-    };
-    pub const SPI1 = struct {
-        pub const base_address = 0x40040000;
-
-        /// address: 0x40040000
-        /// Control register 0, SSPCR0 on page 3-4
-        pub const SSPCR0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined
-            /// operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data.
-            /// 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit
-            /// data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data.
-            /// 1110 15-bit data. 1111 16-bit data.
-            DSS: u4,
-            /// Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame
-            /// format. 10 National Microwire frame format. 11 Reserved, undefined operation.
-            FRF: u2,
-            /// SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola
-            /// SPI frame format on page 2-10.
-            SPO: u1,
-            /// SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI
-            /// frame format on page 2-10.
-            SPH: u1,
-            /// Serial clock rate. The value SCR is used to generate the transmit and receive
-            /// bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where
-            /// CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and
-            /// SCR is a value from 0-255.
-            SCR: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40040004
-        /// Control register 1, SSPCR1 on page 3-5
-        pub const SSPCR1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit
-            /// serial shifter is connected to input of receive serial shifter internally.
-            LBM: u1,
-            /// Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation
-            /// enabled.
-            SSE: u1,
-            /// Master or slave mode select. This bit can be modified only when the PrimeCell
-            /// SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device
-            /// configured as slave.
-            MS: u1,
-            /// Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In
-            /// multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast
-            /// a message to all slaves in the system while ensuring that only one slave drives
-            /// data onto its serial output line. In such systems the RXD lines from multiple
-            /// slaves could be tied together. To operate in such systems, the SOD bit can be
-            /// set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP
-            /// can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD
-            /// output in slave mode.
-            SOD: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40040008
-        /// Data register, SSPDR on page 3-6
-        pub const SSPDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must
-            /// right-justify data when the PrimeCell SSP is programmed for a data size that is
-            /// less than 16 bits. Unused bits at the top are ignored by transmit logic. The
-            /// receive logic automatically right-justifies.
-            DATA: u16,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x4004000c
-        /// Status register, SSPSR on page 3-7
-        pub const SSPSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.
-            TFE: u1,
-            /// Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not
-            /// full.
-            TNF: u1,
-            /// Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not
-            /// empty.
-            RNE: u1,
-            /// Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.
-            RFF: u1,
-            /// PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting
-            /// and/or receiving a frame or the transmit FIFO is not empty.
-            BSY: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x40040010
-        /// Clock prescale register, SSPCPSR on page 3-8
-        pub const SSPCPSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Clock prescale divisor. Must be an even number from 2-254, depending on the
-            /// frequency of SSPCLK. The least significant bit always returns zero on reads.
-            CPSDVSR: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x10);
-
-        /// address: 0x40040014
-        /// Interrupt mask set or clear register, SSPIMSC on page 3-9
-        pub const SSPIMSC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive overrun interrupt mask: 0 Receive FIFO written to while full condition
-            /// interrupt is masked. 1 Receive FIFO written to while full condition interrupt is
-            /// not masked.
-            RORIM: u1,
-            /// Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to
-            /// timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior
-            /// to timeout period interrupt is not masked.
-            RTIM: u1,
-            /// Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition
-            /// interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not
-            /// masked.
-            RXIM: u1,
-            /// Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition
-            /// interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is
-            /// not masked.
-            TXIM: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x40040018
-        /// Raw interrupt status register, SSPRIS on page 3-10
-        pub const SSPRIS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
-            RORRIS: u1,
-            /// Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
-            RTRIS: u1,
-            /// Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
-            RXRIS: u1,
-            /// Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
-            TXRIS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x4004001c
-        /// Masked interrupt status register, SSPMIS on page 3-11
-        pub const SSPMIS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Gives the receive over run masked interrupt status, after masking, of the
-            /// SSPRORINTR interrupt
-            RORMIS: u1,
-            /// Gives the receive timeout masked interrupt state, after masking, of the
-            /// SSPRTINTR interrupt
-            RTMIS: u1,
-            /// Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR
-            /// interrupt
-            RXMIS: u1,
-            /// Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR
-            /// interrupt
-            TXMIS: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x1c);
-
-        /// address: 0x40040020
-        /// Interrupt clear register, SSPICR on page 3-11
-        pub const SSPICR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Clears the SSPRORINTR interrupt
-            RORIC: u1,
-            /// Clears the SSPRTINTR interrupt
-            RTIC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x20);
-
-        /// address: 0x40040024
-        /// DMA control register, SSPDMACR on page 3-12
-        pub const SSPDMACR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is
-            /// enabled.
-            RXDMAE: u1,
-            /// Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is
-            /// enabled.
-            TXDMAE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x24);
-
-        /// address: 0x40040fe0
-        /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-        pub const SSPPERIPHID0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x22
-            PARTNUMBER0: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe0);
-
-        /// address: 0x40040fe4
-        /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-        pub const SSPPERIPHID1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x0
-            PARTNUMBER1: u4,
-            /// These bits read back as 0x1
-            DESIGNER0: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe4);
-
-        /// address: 0x40040fe8
-        /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-        pub const SSPPERIPHID2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x4
-            DESIGNER1: u4,
-            /// These bits return the peripheral revision
-            REVISION: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfe8);
-
-        /// address: 0x40040fec
-        /// Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-        pub const SSPPERIPHID3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits read back as 0x00
-            CONFIGURATION: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xfec);
-
-        /// address: 0x40040ff0
-        /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-        pub const SSPPCELLID0 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff0);
-
-        /// address: 0x40040ff4
-        /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-        pub const SSPPCELLID1 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff4);
-
-        /// address: 0x40040ff8
-        /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-        pub const SSPPCELLID2 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xff8);
-
-        /// address: 0x40040ffc
-        /// PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-        pub const SSPPCELLID3 = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xffc);
-    };
-
-    /// DW_apb_i2c address block\n\n
-    /// List of configuration constants for the Synopsys I2C hardware (you may see
-    /// references to these in I2C register header; these are *fixed* values, set at
-    /// hardware design time):\n\n
-    /// IC_ULTRA_FAST_MODE ................ 0x0\n
-    /// IC_UFM_TBUF_CNT_DEFAULT ........... 0x8\n
-    /// IC_UFM_SCL_LOW_COUNT .............. 0x0008\n
-    /// IC_UFM_SCL_HIGH_COUNT ............. 0x0006\n
-    /// IC_TX_TL .......................... 0x0\n
-    /// IC_TX_CMD_BLOCK ................... 0x1\n
-    /// IC_HAS_DMA ........................ 0x1\n
-    /// IC_HAS_ASYNC_FIFO ................. 0x0\n
-    /// IC_SMBUS_ARP ...................... 0x0\n
-    /// IC_FIRST_DATA_BYTE_STATUS ......... 0x1\n
-    /// IC_INTR_IO ........................ 0x1\n
-    /// IC_MASTER_MODE .................... 0x1\n
-    /// IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1\n
-    /// IC_INTR_POL ....................... 0x1\n
-    /// IC_OPTIONAL_SAR ................... 0x0\n
-    /// IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055\n
-    /// IC_DEFAULT_SLAVE_ADDR ............. 0x055\n
-    /// IC_DEFAULT_HS_SPKLEN .............. 0x1\n
-    /// IC_FS_SCL_HIGH_COUNT .............. 0x0006\n
-    /// IC_HS_SCL_LOW_COUNT ............... 0x0008\n
-    /// IC_DEVICE_ID_VALUE ................ 0x0\n
-    /// IC_10BITADDR_MASTER ............... 0x0\n
-    /// IC_CLK_FREQ_OPTIMIZATION .......... 0x0\n
-    /// IC_DEFAULT_FS_SPKLEN .............. 0x7\n
-    /// IC_ADD_ENCODED_PARAMS ............. 0x0\n
-    /// IC_DEFAULT_SDA_HOLD ............... 0x000001\n
-    /// IC_DEFAULT_SDA_SETUP .............. 0x64\n
-    /// IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0\n
-    /// IC_CLOCK_PERIOD ................... 100\n
-    /// IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1\n
-    /// IC_RESTART_EN ..................... 0x1\n
-    /// IC_TX_CMD_BLOCK_DEFAULT ........... 0x0\n
-    /// IC_BUS_CLEAR_FEATURE .............. 0x0\n
-    /// IC_CAP_LOADING .................... 100\n
-    /// IC_FS_SCL_LOW_COUNT ............... 0x000d\n
-    /// APB_DATA_WIDTH .................... 32\n
-    /// IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
-    /// IC_SLV_DATA_NACK_ONLY ............. 0x1\n
-    /// IC_10BITADDR_SLAVE ................ 0x0\n
-    /// IC_CLK_TYPE ....................... 0x0\n
-    /// IC_SMBUS_UDID_MSB ................. 0x0\n
-    /// IC_SMBUS_SUSPEND_ALERT ............ 0x0\n
-    /// IC_HS_SCL_HIGH_COUNT .............. 0x0006\n
-    /// IC_SLV_RESTART_DET_EN ............. 0x1\n
-    /// IC_SMBUS .......................... 0x0\n
-    /// IC_OPTIONAL_SAR_DEFAULT ........... 0x0\n
-    /// IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0\n
-    /// IC_USE_COUNTS ..................... 0x0\n
-    /// IC_RX_BUFFER_DEPTH ................ 16\n
-    /// IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff\n
-    /// IC_RX_FULL_HLD_BUS_EN ............. 0x1\n
-    /// IC_SLAVE_DISABLE .................. 0x1\n
-    /// IC_RX_TL .......................... 0x0\n
-    /// IC_DEVICE_ID ...................... 0x0\n
-    /// IC_HC_COUNT_VALUES ................ 0x0\n
-    /// I2C_DYNAMIC_TAR_UPDATE ............ 0\n
-    /// IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff\n
-    /// IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff\n
-    /// IC_HS_MASTER_CODE ................. 0x1\n
-    /// IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff\n
-    /// IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff\n
-    /// IC_SS_SCL_HIGH_COUNT .............. 0x0028\n
-    /// IC_SS_SCL_LOW_COUNT ............... 0x002f\n
-    /// IC_MAX_SPEED_MODE ................. 0x2\n
-    /// IC_STAT_FOR_CLK_STRETCH ........... 0x0\n
-    /// IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0\n
-    /// IC_DEFAULT_UFM_SPKLEN ............. 0x1\n
-    /// IC_TX_BUFFER_DEPTH ................ 16
-    pub const I2C0 = struct {
-        pub const base_address = 0x40044000;
-        pub const version = "1";
-
-        /// address: 0x40044000
-        /// I2C Control Register. This register can be written only when the DW_apb_i2c is
-        /// disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes
-        /// at other times have no effect.\n\n
-        /// Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read
-        /// only - bit 17 is read only - bits 18 and 19 are read only.
-        pub const IC_CON = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit controls whether the DW_apb_i2c master is enabled.\n\n
-            /// NOTE: Software should ensure that if this bit is written with '1' then bit 6
-            /// should also be written with a '1'.
-            MASTER_MODE: u1,
-            /// These bits control at which speed the DW_apb_i2c operates; its setting is
-            /// relevant only if one is operating the DW_apb_i2c in master mode. Hardware
-            /// protects against illegal values being programmed by software. These bits must be
-            /// programmed appropriately for slave mode also, as it is used to capture correct
-            /// value of spike filter as per the speed mode.\n\n
-            /// This register should be programmed only with a value in the range of 1 to
-            /// IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of
-            /// IC_MAX_SPEED_MODE.\n\n
-            /// 1: standard mode (100 kbit/s)\n\n
-            /// 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n
-            /// 3: high speed mode (3.4 Mbit/s)\n\n
-            /// Note: This field is not applicable when IC_ULTRA_FAST_MODE=1
-            SPEED: u2,
-            /// When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7-
-            /// or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions
-            /// that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of
-            /// the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c
-            /// responds to only 10-bit addressing transfers that match the full 10 bits of the
-            /// IC_SAR register.
-            IC_10BITADDR_SLAVE: u1,
-            /// Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing
-            /// mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing
-            IC_10BITADDR_MASTER: u1,
-            /// Determines whether RESTART conditions may be sent when acting as a master. Some
-            /// older slaves do not support handling RESTART conditions; however, RESTART
-            /// conditions are used in several DW_apb_i2c operations. When RESTART is disabled,
-            /// the master is prohibited from performing the following functions: - Sending a
-            /// START BYTE - Performing any high-speed mode operation - High-speed mode
-            /// operation - Performing direction changes in combined format mode - Performing a
-            /// read operation with a 10-bit address By replacing RESTART condition followed by
-            /// a STOP and a subsequent START condition, split operations are broken down into
-            /// multiple DW_apb_i2c transfers. If the above operations are performed, it will
-            /// result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: ENABLED
-            IC_RESTART_EN: u1,
-            /// This bit controls whether I2C has its slave disabled, which means once the
-            /// presetn signal is applied, then this bit is set and the slave is disabled.\n\n
-            /// If this bit is set (slave is disabled), DW_apb_i2c functions only as a master
-            /// and does not perform any action that requires a slave.\n\n
-            /// NOTE: Software should ensure that if this bit is written with 0, then bit 0
-            /// should also be written with a 0.
-            IC_SLAVE_DISABLE: u1,
-            /// In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed.
-            /// - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset
-            /// value: 0x0\n\n
-            /// NOTE: During a general call address, this slave does not issue the STOP_DET
-            /// interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the
-            /// general call address by generating ACK. The STOP_DET interrupt is generated only
-            /// when the transmitted address matches the slave address (SAR).
-            STOP_DET_IFADDRESSED: u1,
-            /// This bit controls the generation of the TX_EMPTY interrupt, as described in the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0.
-            TX_EMPTY_CTRL: u1,
-            /// This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is
-            /// physically full to its RX_BUFFER_DEPTH, as described in the
-            /// IC_RX_FULL_HLD_BUS_EN parameter.\n\n
-            /// Reset value: 0x0.
-            RX_FIFO_FULL_HLD_CTRL: u1,
-            /// Master issues the STOP_DET interrupt irrespective of whether master is active or
-            /// not
-            STOP_DET_IF_MASTER_ACTIVE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40044004
-        /// I2C Target Address Register\n\n
-        /// This register is 12 bits wide, and bits 31:12 are reserved. This register can be
-        /// written to only when IC_ENABLE[0] is set to 0.\n\n
-        /// Note: If the software or application is aware that the DW_apb_i2c is not using
-        /// the TAR address for the pending commands in the Tx FIFO, then it is possible to
-        /// update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). -
-        /// It is not necessary to perform any write to this register if DW_apb_i2c is
-        /// enabled as an I2C slave only.
-        pub const IC_TAR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the target address for any master transaction. When transmitting a
-            /// General Call, these bits are ignored. To generate a START BYTE, the CPU needs to
-            /// write only once into these bits.\n\n
-            /// If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared
-            /// between master and slave, so full loopback is not feasible. Only one direction
-            /// loopback mode is supported (simplex), not duplex. A master cannot transmit to
-            /// itself; it can transmit to only a slave.
-            IC_TAR: u10,
-            /// If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit
-            /// indicates whether a General Call or START byte command is to be performed by the
-            /// DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only
-            /// writes may be performed. Attempting to issue a read command results in setting
-            /// bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in
-            /// General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START
-            /// BYTE Reset value: 0x0
-            GC_OR_START: u1,
-            /// This bit indicates whether software performs a Device-ID or General Call or
-            /// START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1:
-            /// perform special I2C command as specified in Device_ID or GC_OR_START bit Reset
-            /// value: 0x0
-            SPECIAL: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40044008
-        /// I2C Slave Address Register
-        pub const IC_SAR = @intToPtr(*volatile MmioInt(32, u10), base_address + 0x8);
-
-        /// address: 0x40044010
-        /// I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes
-        /// to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX
-        /// FIFO.\n\n
-        /// The size of the register changes as follows:\n\n
-        /// Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when
-        /// IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1
-        /// - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to
-        /// continue acknowledging reads, a read command should be written for every byte
-        /// that is to be received; otherwise the DW_apb_i2c will stop acknowledging.
-        pub const IC_DATA_CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register contains the data to be transmitted or received on the I2C bus. If
-            /// you are writing to this register and want to perform a read, bits 7:0 (DAT) are
-            /// ignored by the DW_apb_i2c. However, when you read this register, these bits
-            /// return the value of data received on the DW_apb_i2c interface.\n\n
-            /// Reset value: 0x0
-            DAT: u8,
-            /// This bit controls whether a read or a write is performed. This bit does not
-            /// control the direction when the DW_apb_i2con acts as a slave. It controls only
-            /// the direction when it acts as a master.\n\n
-            /// When a command is entered in the TX FIFO, this bit distinguishes the write and
-            /// read commands. In slave-receiver mode, this bit is a 'don't care' because writes
-            /// to this register are not required. In slave-transmitter mode, a '0' indicates
-            /// that the data in IC_DATA_CMD is to be transmitted.\n\n
-            /// When programming this bit, you should remember the following: attempting to
-            /// perform a read operation after a General Call command has been sent results in a
-            /// TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11
-            /// (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this
-            /// bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n
-            /// Reset value: 0x0
-            CMD: u1,
-            /// This bit controls whether a STOP is issued after the byte is sent or
-            /// received.\n\n
-            /// - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO
-            /// is empty. If the Tx FIFO is not empty, the master immediately tries to start a
-            /// new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not
-            /// issued after this byte, regardless of whether or not the Tx FIFO is empty. If
-            /// the Tx FIFO is not empty, the master continues the current transfer by
-            /// sending/receiving data bytes according to the value of the CMD bit. If the Tx
-            /// FIFO is empty, the master holds the SCL line low and stalls the bus until a new
-            /// command is available in the Tx FIFO. Reset value: 0x0
-            STOP: u1,
-            /// This bit controls whether a RESTART is issued before the byte is sent or
-            /// received.\n\n
-            /// 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received
-            /// (according to the value of CMD), regardless of whether or not the transfer
-            /// direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP
-            /// followed by a START is issued instead.\n\n
-            /// 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is
-            /// changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a
-            /// START is issued instead.\n\n
-            /// Reset value: 0x0
-            RESTART: u1,
-            /// Indicates the first data byte received after the address phase for receive
-            /// transfer in Master receiver or Slave receiver mode.\n\n
-            /// Reset value : 0x0\n\n
-            /// NOTE: In case of APB_DATA_WIDTH=8,\n\n
-            /// 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status
-            /// on 11 bit.\n\n
-            /// 2. In order to read the 11 bit, the user has to perform the first data byte read
-            /// [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in
-            /// order to know the status of 11 bit (whether the data received in previous read
-            /// is a first data byte or not).\n\n
-            /// 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8]
-            /// (offset 0x11) if not interested in FIRST_DATA_BYTE status.
-            FIRST_DATA_BYTE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x10);
-
-        /// address: 0x40044014
-        /// Standard Speed I2C Clock SCL High Count Register
-        pub const IC_SS_SCL_HCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14);
-
-        /// address: 0x40044018
-        /// Standard Speed I2C Clock SCL Low Count Register
-        pub const IC_SS_SCL_LCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x18);
-
-        /// address: 0x4004401c
-        /// Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
-        pub const IC_FS_SCL_HCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c);
-
-        /// address: 0x40044020
-        /// Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
-        pub const IC_FS_SCL_LCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x20);
-
-        /// address: 0x4004402c
-        /// I2C Interrupt Status Register\n\n
-        /// Each bit in this register has a corresponding mask bit in the IC_INTR_MASK
-        /// register. These bits are cleared by reading the matching interrupt clear
-        /// register. The unmasked raw versions of these bits are available in the
-        /// IC_RAW_INTR_STAT register.
-        pub const IC_INTR_STAT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n
-            /// Reset value: 0x0
-            R_RX_UNDER: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n
-            /// Reset value: 0x0
-            R_RX_OVER: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n
-            /// Reset value: 0x0
-            R_RX_FULL: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n
-            /// Reset value: 0x0
-            R_TX_OVER: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n
-            /// Reset value: 0x0
-            R_TX_EMPTY: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n
-            /// Reset value: 0x0
-            R_RD_REQ: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n
-            /// Reset value: 0x0
-            R_TX_ABRT: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n
-            /// Reset value: 0x0
-            R_RX_DONE: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n
-            /// Reset value: 0x0
-            R_ACTIVITY: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n
-            /// Reset value: 0x0
-            R_STOP_DET: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n
-            /// Reset value: 0x0
-            R_START_DET: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n
-            /// Reset value: 0x0
-            R_GEN_CALL: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n
-            /// Reset value: 0x0
-            R_RESTART_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-        }), base_address + 0x2c);
-
-        /// address: 0x40044030
-        /// I2C Interrupt Mask Register.\n\n
-        /// These bits mask their corresponding interrupt status bits. This register is
-        /// active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the
-        /// interrupt.
-        pub const IC_INTR_MASK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_RX_UNDER: u1,
-            /// This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_RX_OVER: u1,
-            /// This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_RX_FULL: u1,
-            /// This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_TX_OVER: u1,
-            /// This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_TX_EMPTY: u1,
-            /// This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_RD_REQ: u1,
-            /// This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_TX_ABRT: u1,
-            /// This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_RX_DONE: u1,
-            /// This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            M_ACTIVITY: u1,
-            /// This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            M_STOP_DET: u1,
-            /// This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            M_START_DET: u1,
-            /// This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_GEN_CALL: u1,
-            /// This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            M_RESTART_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-        }), base_address + 0x30);
-
-        /// address: 0x40044034
-        /// I2C Raw Interrupt Status Register\n\n
-        /// Unlike the IC_INTR_STAT register, these bits are not masked so they always show
-        /// the true status of the DW_apb_i2c.
-        pub const IC_RAW_INTR_STAT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set if the processor attempts to read the receive buffer when it is empty by
-            /// reading from the IC_DATA_CMD register. If the module is disabled
-            /// (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state
-            /// machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
-            /// Reset value: 0x0
-            RX_UNDER: u1,
-            /// Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
-            /// additional byte is received from an external I2C device. The DW_apb_i2c
-            /// acknowledges this, but any data bytes received after the FIFO is full are lost.
-            /// If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the
-            /// master or slave state machines go into idle, and when ic_en goes to 0, this
-            /// interrupt is cleared.\n\n
-            /// Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to
-            /// HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never
-            /// overflows.\n\n
-            /// Reset value: 0x0
-            RX_OVER: u1,
-            /// Set when the receive buffer reaches or goes above the RX_TL threshold in the
-            /// IC_RX_TL register. It is automatically cleared by hardware when buffer level
-            /// goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX
-            /// FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this
-            /// bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of
-            /// the activity that continues.\n\n
-            /// Reset value: 0x0
-            RX_FULL: u1,
-            /// Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
-            /// the processor attempts to issue another I2C command by writing to the
-            /// IC_DATA_CMD register. When the module is disabled, this bit keeps its level
-            /// until the master or slave state machines go into idle, and when ic_en goes to 0,
-            /// this interrupt is cleared.\n\n
-            /// Reset value: 0x0
-            TX_OVER: u1,
-            /// The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL
-            /// selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1
-            /// when the transmit buffer is at or below the threshold value set in the IC_TX_TL
-            /// register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit
-            /// buffer is at or below the threshold value set in the IC_TX_TL register and the
-            /// transmission of the address/data from the internal shift register for the most
-            /// recently popped command is completed. It is automatically cleared by hardware
-            /// when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0,
-            /// the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no
-            /// data within it, so this bit is set to 1, provided there is activity in the
-            /// master or slave state machines. When there is no longer any activity, then with
-            /// ic_en=0, this bit is set to 0.\n\n
-            /// Reset value: 0x0.
-            TX_EMPTY: u1,
-            /// This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master
-            /// is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in
-            /// a wait state (SCL=0) until this interrupt is serviced, which means that the
-            /// slave has been addressed by a remote master that is asking for data to be
-            /// transferred. The processor must respond to this interrupt and then write the
-            /// requested data to the IC_DATA_CMD register. This bit is set to 0 just after the
-            /// processor reads the IC_CLR_RD_REQ register.\n\n
-            /// Reset value: 0x0
-            RD_REQ: u1,
-            /// This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete
-            /// the intended actions on the contents of the transmit FIFO. This situation can
-            /// occur both as an I2C master or an I2C slave, and is referred to as a 'transmit
-            /// abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the
-            /// reason why the transmit abort takes places.\n\n
-            /// Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever
-            /// there is a transmit abort caused by any of the events tracked by the
-            /// IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the
-            /// register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is
-            /// then ready to accept more data bytes from the APB interface.\n\n
-            /// Reset value: 0x0
-            TX_ABRT: u1,
-            /// When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if
-            /// the master does not acknowledge a transmitted byte. This occurs on the last byte
-            /// of the transmission, indicating that the transmission is done.\n\n
-            /// Reset value: 0x0
-            RX_DONE: u1,
-            /// This bit captures DW_apb_i2c activity and stays set until it is cleared. There
-            /// are four ways to clear it: - Disabling the DW_apb_i2c - Reading the
-            /// IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once
-            /// this bit is set, it stays set unless one of the four methods is used to clear
-            /// it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared,
-            /// indicating that there was activity on the bus.\n\n
-            /// Reset value: 0x0
-            ACTIVITY: u1,
-            /// Indicates whether a STOP condition has occurred on the I2C interface regardless
-            /// of whether DW_apb_i2c is operating in slave or master mode.\n\n
-            /// In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET
-            /// interrupt will be issued only if slave is addressed. Note: During a general call
-            /// address, this slave does not issue a STOP_DET interrupt if
-            /// STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call
-            /// address by generating ACK. The STOP_DET interrupt is generated only when the
-            /// transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0
-            /// (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether
-            /// it is being addressed. In Master Mode: - If IC_CON[10]=1'b1
-            /// (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master
-            /// is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt
-            /// will be issued irrespective of whether master is active or not. Reset value: 0x0
-            STOP_DET: u1,
-            /// Indicates whether a START or RESTART condition has occurred on the I2C interface
-            /// regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
-            /// Reset value: 0x0
-            START_DET: u1,
-            /// Set only when a General Call address is received and it is acknowledged. It
-            /// stays set until it is cleared either by disabling DW_apb_i2c or when the CPU
-            /// reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data
-            /// in the Rx buffer.\n\n
-            /// Reset value: 0x0
-            GEN_CALL: u1,
-            /// Indicates whether a RESTART condition has occurred on the I2C interface when
-            /// DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled
-            /// only when IC_SLV_RESTART_DET_EN=1.\n\n
-            /// Note: However, in high-speed mode or during a START BYTE transfer, the RESTART
-            /// comes before the address field as per the I2C protocol. In this case, the slave
-            /// is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does
-            /// not generate the RESTART_DET interrupt.\n\n
-            /// Reset value: 0x0
-            RESTART_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-        }), base_address + 0x34);
-
-        /// address: 0x40044038
-        /// I2C Receive FIFO Threshold Register
-        pub const IC_RX_TL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive FIFO Threshold Level.\n\n
-            /// Controls the level of entries (or above) that triggers the RX_FULL interrupt
-            /// (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the
-            /// additional restriction that hardware does not allow this value to be set to a
-            /// value larger than the depth of the buffer. If an attempt is made to do that, the
-            /// actual value set will be the maximum depth of the buffer. A value of 0 sets the
-            /// threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
-            RX_TL: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x38);
-
-        /// address: 0x4004403c
-        /// I2C Transmit FIFO Threshold Register
-        pub const IC_TX_TL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit FIFO Threshold Level.\n\n
-            /// Controls the level of entries (or below) that trigger the TX_EMPTY interrupt
-            /// (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the
-            /// additional restriction that it may not be set to value larger than the depth of
-            /// the buffer. If an attempt is made to do that, the actual value set will be the
-            /// maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and
-            /// a value of 255 sets the threshold for 255 entries.
-            TX_TL: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x3c);
-
-        /// address: 0x40044040
-        /// Clear Combined and Individual Interrupt Register
-        pub const IC_CLR_INTR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the combined interrupt, all individual interrupts,
-            /// and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable
-            /// interrupts but software clearable interrupts. Refer to Bit 9 of the
-            /// IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
-            /// Reset value: 0x0
-            CLR_INTR: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x40);
-
-        /// address: 0x40044044
-        /// Clear RX_UNDER Interrupt Register
-        pub const IC_CLR_RX_UNDER = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the RX_UNDER interrupt (bit 0) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_RX_UNDER: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x44);
-
-        /// address: 0x40044048
-        /// Clear RX_OVER Interrupt Register
-        pub const IC_CLR_RX_OVER = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the RX_OVER interrupt (bit 1) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_RX_OVER: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x48);
-
-        /// address: 0x4004404c
-        /// Clear TX_OVER Interrupt Register
-        pub const IC_CLR_TX_OVER = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the TX_OVER interrupt (bit 3) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_TX_OVER: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x4c);
-
-        /// address: 0x40044050
-        /// Clear RD_REQ Interrupt Register
-        pub const IC_CLR_RD_REQ = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT
-            /// register.\n\n
-            /// Reset value: 0x0
-            CLR_RD_REQ: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x50);
-
-        /// address: 0x40044054
-        /// Clear TX_ABRT Interrupt Register
-        pub const IC_CLR_TX_ABRT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the TX_ABRT interrupt (bit 6) of the
-            /// IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also
-            /// releases the TX FIFO from the flushed/reset state, allowing more writes to the
-            /// TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to
-            /// clearing IC_TX_ABRT_SOURCE.\n\n
-            /// Reset value: 0x0
-            CLR_TX_ABRT: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x54);
-
-        /// address: 0x40044058
-        /// Clear RX_DONE Interrupt Register
-        pub const IC_CLR_RX_DONE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the RX_DONE interrupt (bit 7) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_RX_DONE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x58);
-
-        /// address: 0x4004405c
-        /// Clear ACTIVITY Interrupt Register
-        pub const IC_CLR_ACTIVITY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reading this register clears the ACTIVITY interrupt if the I2C is not active
-            /// anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt
-            /// bit continues to be set. It is automatically cleared by hardware if the module
-            /// is disabled and if there is no further activity on the bus. The value read from
-            /// this register to get status of the ACTIVITY interrupt (bit 8) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_ACTIVITY: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x5c);
-
-        /// address: 0x40044060
-        /// Clear STOP_DET Interrupt Register
-        pub const IC_CLR_STOP_DET = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the STOP_DET interrupt (bit 9) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_STOP_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x60);
-
-        /// address: 0x40044064
-        /// Clear START_DET Interrupt Register
-        pub const IC_CLR_START_DET = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the START_DET interrupt (bit 10) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_START_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x64);
-
-        /// address: 0x40044068
-        /// Clear GEN_CALL Interrupt Register
-        pub const IC_CLR_GEN_CALL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT
-            /// register.\n\n
-            /// Reset value: 0x0
-            CLR_GEN_CALL: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x68);
-
-        /// address: 0x4004406c
-        /// I2C Enable Register
-        pub const IC_ENABLE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX
-            /// FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable
-            /// DW_apb_i2c while it is active. However, it is important that care be taken to
-            /// ensure that DW_apb_i2c is disabled properly. A recommended procedure is
-            /// described in 'Disabling DW_apb_i2c'.\n\n
-            /// When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get
-            /// flushed. - Status bits in the IC_INTR_STAT register are still active until
-            /// DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well
-            /// as deletes the contents of the transmit buffer after the current transfer is
-            /// complete. If the module is receiving, the DW_apb_i2c stops the current transfer
-            /// at the end of the current byte and does not acknowledge the transfer.\n\n
-            /// In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to
-            /// asynchronous (1), there is a two ic_clk delay when enabling or disabling the
-            /// DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to
-            /// 'Disabling DW_apb_i2c'\n\n
-            /// Reset value: 0x0
-            ENABLE: u1,
-            /// When set, the controller initiates the transfer abort. - 0: ABORT not initiated
-            /// or ABORT done - 1: ABORT operation in progress The software can abort the I2C
-            /// transfer in master mode by setting this bit. The software can set this bit only
-            /// when ENABLE is already set; otherwise, the controller ignores any write to ABORT
-            /// bit. The software cannot clear the ABORT bit once set. In response to an ABORT,
-            /// the controller issues a STOP and flushes the Tx FIFO after completing the
-            /// current transfer, then sets the TX_ABORT interrupt after the abort operation.
-            /// The ABORT bit is cleared automatically after the abort operation.\n\n
-            /// For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C
-            /// Transfers'.\n\n
-            /// Reset value: 0x0
-            ABORT: u1,
-            /// In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx
-            /// FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus
-            /// automatically, as soon as the first data is available in the Tx FIFO. Note: To
-            /// block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx
-            /// FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0).
-            /// Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit
-            /// is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT
-            TX_CMD_BLOCK: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-        }), base_address + 0x6c);
-
-        /// address: 0x40044070
-        /// I2C Status Register\n\n
-        /// This is a read-only register used to indicate the current transfer status and
-        /// FIFO status. The status register may be read at any time. None of the bits in
-        /// this register request an interrupt.\n\n
-        /// When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits
-        /// 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state
-        /// machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0
-        pub const IC_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// I2C Activity Status. Reset value: 0x0
-            ACTIVITY: u1,
-            /// Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty
-            /// locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1:
-            /// Transmit FIFO is not full Reset value: 0x1
-            TFNF: u1,
-            /// Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this
-            /// bit is set. When it contains one or more valid entries, this bit is cleared.
-            /// This bit field does not request an interrupt. - 0: Transmit FIFO is not empty -
-            /// 1: Transmit FIFO is empty Reset value: 0x1
-            TFE: u1,
-            /// Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or
-            /// more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is
-            /// empty - 1: Receive FIFO is not empty Reset value: 0x0
-            RFNE: u1,
-            /// Receive FIFO Completely Full. When the receive FIFO is completely full, this bit
-            /// is set. When the receive FIFO contains one or more empty location, this bit is
-            /// cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value:
-            /// 0x0
-            RFF: u1,
-            /// Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in
-            /// the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master
-            /// part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the
-            /// Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is
-            /// the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n
-            /// Reset value: 0x0
-            MST_ACTIVITY: u1,
-            /// Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in
-            /// the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave
-            /// part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the
-            /// Slave part of DW_apb_i2c is Active Reset value: 0x0
-            SLV_ACTIVITY: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-        }), base_address + 0x70);
-
-        /// address: 0x40044074
-        /// I2C Transmit FIFO Level Register This register contains the number of valid data
-        /// entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is
-        /// disabled - There is a transmit abort - that is, TX_ABRT bit is set in the
-        /// IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register
-        /// increments whenever data is placed into the transmit FIFO and decrements when
-        /// data is taken from the transmit FIFO.
-        pub const IC_TXFLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit FIFO Level. Contains the number of valid data entries in the transmit
-            /// FIFO.\n\n
-            /// Reset value: 0x0
-            TXFLR: u5,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-        }), base_address + 0x74);
-
-        /// address: 0x40044078
-        /// I2C Receive FIFO Level Register This register contains the number of valid data
-        /// entries in the receive FIFO buffer. It is cleared whenever: - The I2C is
-        /// disabled - Whenever there is a transmit abort caused by any of the events
-        /// tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed
-        /// into the receive FIFO and decrements when data is taken from the receive FIFO.
-        pub const IC_RXFLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive FIFO Level. Contains the number of valid data entries in the receive
-            /// FIFO.\n\n
-            /// Reset value: 0x0
-            RXFLR: u5,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-        }), base_address + 0x78);
-
-        /// address: 0x4004407c
-        /// I2C SDA Hold Time Length Register\n\n
-        /// The bits [15:0] of this register are used to control the hold time of SDA during
-        /// transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n
-        /// The bits [23:16] of this register are used to extend the SDA transition (if any)
-        /// whenever SCL is HIGH in the receiver in either master or slave mode.\n\n
-        /// Writes to this register succeed only when IC_ENABLE[0]=0.\n\n
-        /// The values in this register are in units of ic_clk period. The value programmed
-        /// in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one
-        /// cycle in master mode, seven cycles in slave mode) for the value to be
-        /// implemented.\n\n
-        /// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at
-        /// any time the duration of the low part of scl. Therefore the programmed value
-        /// cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low
-        /// part of the scl period measured in ic_clk cycles.
-        pub const IC_SDA_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts
-            /// as a transmitter.\n\n
-            /// Reset value: IC_DEFAULT_SDA_HOLD[15:0].
-            IC_SDA_TX_HOLD: u16,
-            /// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts
-            /// as a receiver.\n\n
-            /// Reset value: IC_DEFAULT_SDA_HOLD[23:16].
-            IC_SDA_RX_HOLD: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x7c);
-
-        /// address: 0x40044080
-        /// I2C Transmit Abort Source Register\n\n
-        /// This register has 32 bits that indicate the source of the TX_ABRT bit. Except
-        /// for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the
-        /// IC_CLR_INTR register is read. To clear Bit 9, the source of the
-        /// ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1),
-        /// the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be
-        /// cleared (IC_TAR[10]).\n\n
-        /// Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared
-        /// in the same manner as other bits in this register. If the source of the
-        /// ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9
-        /// clears for one cycle and is then re-asserted.
-        pub const IC_TX_ABRT_SOURCE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This field indicates that the Master is in 7-bit addressing mode and the address
-            /// sent was not acknowledged by any slave.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-            ABRT_7B_ADDR_NOACK: u1,
-            /// This field indicates that the Master is in 10-bit address mode and the first
-            /// 10-bit address byte was not acknowledged by any slave.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-            ABRT_10ADDR1_NOACK: u1,
-            /// This field indicates that the Master is in 10-bit address mode and that the
-            /// second address byte of the 10-bit address was not acknowledged by any slave.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-            ABRT_10ADDR2_NOACK: u1,
-            /// This field indicates the master-mode only bit. When the master receives an
-            /// acknowledgement for the address, but when it sends data byte(s) following the
-            /// address, it did not receive an acknowledge from the remote slave(s).\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter
-            ABRT_TXDATA_NOACK: u1,
-            /// This field indicates that DW_apb_i2c in master mode has sent a General Call and
-            /// no slave on the bus acknowledged the General Call.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter
-            ABRT_GCALL_NOACK: u1,
-            /// This field indicates that DW_apb_i2c in the master mode has sent a General Call
-            /// but the user programmed the byte following the General Call to be a read from
-            /// the bus (IC_DATA_CMD[9] is set to 1).\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter
-            ABRT_GCALL_READ: u1,
-            /// This field indicates that the Master is in High Speed mode and the High Speed
-            /// Master code was acknowledged (wrong behavior).\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master
-            ABRT_HS_ACKDET: u1,
-            /// This field indicates that the Master has sent a START Byte and the START Byte
-            /// was acknowledged (wrong behavior).\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master
-            ABRT_SBYTE_ACKDET: u1,
-            /// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5])
-            /// =0) and the user is trying to use the master to transfer data in High Speed
-            /// mode.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-            ABRT_HS_NORSTRT: u1,
-            /// To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first;
-            /// restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared
-            /// (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the
-            /// source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the
-            /// same manner as other bits in this register. If the source of the
-            /// ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9
-            /// clears for one cycle and then gets reasserted. When this field is set to 1, the
-            /// restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to
-            /// send a START Byte.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master
-            ABRT_SBYTE_NORSTRT: u1,
-            /// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5])
-            /// =0) and the master sends a read command in 10-bit addressing mode.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Receiver
-            ABRT_10B_RD_NORSTRT: u1,
-            /// This field indicates that the User tries to initiate a Master operation with the
-            /// Master mode disabled.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-            ABRT_MASTER_DIS: u1,
-            /// This field specifies that the Master has lost arbitration, or if
-            /// IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost
-            /// arbitration.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
-            ARB_LOST: u1,
-            /// This field specifies that the Slave has received a read command and some data
-            /// exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data
-            /// in TX FIFO.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Slave-Transmitter
-            ABRT_SLVFLUSH_TXFIFO: u1,
-            /// This field indicates that a Slave has lost the bus while transmitting data to a
-            /// remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though
-            /// the slave never 'owns' the bus, something could go wrong on the bus. This is a
-            /// fail safe check. For instance, during a data transmission at the low-to-high
-            /// transition of SCL, if what is on the data bus is not what is supposed to be
-            /// transmitted, then DW_apb_i2c no longer own the bus.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Slave-Transmitter
-            ABRT_SLV_ARBLOST: u1,
-            /// 1: When the processor side responds to a slave mode request for data to be
-            /// transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD
-            /// register.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Slave-Transmitter
-            ABRT_SLVRD_INTX: u1,
-            /// This is a master-mode-only bit. Master has detected the transfer abort
-            /// (IC_ENABLE[1])\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter
-            ABRT_USER_ABRT: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            /// This field indicates the number of Tx FIFO Data Commands which are flushed due
-            /// to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
-            TX_FLUSH_CNT: u9,
-        }), base_address + 0x80);
-
-        /// address: 0x40044084
-        /// Generate Slave Data NACK Register\n\n
-        /// The register is used to generate a NACK for the data part of a transfer when
-        /// DW_apb_i2c is acting as a slave-receiver. This register only exists when the
-        /// IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this
-        /// register does not exist and writing to the register's address has no effect.\n\n
-        /// A write can occur on this register if both of the following conditions are met:
-        /// - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive
-        /// (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for
-        /// the internal slv_activity signal; the user should poll this before writing the
-        /// ic_slv_data_nack_only bit.
-        pub const IC_SLV_DATA_NACK_ONLY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Generate NACK. This NACK generation only occurs when DW_apb_i2c is a
-            /// slave-receiver. If this register is set to a value of 1, it can only generate a
-            /// NACK after a data byte is received; hence, the data transfer is aborted and the
-            /// data received is not pushed to the receive buffer.\n\n
-            /// When the register is set to a value of 0, it generates NACK/ACK, depending on
-            /// normal criteria. - 1: generate NACK after data byte received - 0: generate
-            /// NACK/ACK normally Reset value: 0x0
-            NACK: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x84);
-
-        /// address: 0x40044088
-        /// DMA Control Register\n\n
-        /// The register is used to enable the DMA Controller interface operation. There is
-        /// a separate bit for transmit and receive. This can be programmed regardless of
-        /// the state of IC_ENABLE.
-        pub const IC_DMA_CR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel.
-            /// Reset value: 0x0
-            RDMAE: u1,
-            /// Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel.
-            /// Reset value: 0x0
-            TDMAE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x88);
-
-        /// address: 0x4004408c
-        /// DMA Transmit Data Level Register
-        pub const IC_DMA_TDLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit Data Level. This bit field controls the level at which a DMA request is
-            /// made by the transmit logic. It is equal to the watermark level; that is, the
-            /// dma_tx_req signal is generated when the number of valid data entries in the
-            /// transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n
-            /// Reset value: 0x0
-            DMATDL: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x8c);
-
-        /// address: 0x40044090
-        /// I2C Receive Data Level Register
-        pub const IC_DMA_RDLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive Data Level. This bit field controls the level at which a DMA request is
-            /// made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req
-            /// is generated when the number of valid data entries in the receive FIFO is equal
-            /// to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is
-            /// 0, then dma_rx_req is asserted when 1 or more data entries are present in the
-            /// receive FIFO.\n\n
-            /// Reset value: 0x0
-            DMARDL: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x90);
-
-        /// address: 0x40044094
-        /// I2C SDA Setup Register\n\n
-        /// This register controls the amount of time delay (in terms of number of ic_clk
-        /// clock periods) introduced in the rising edge of SCL - relative to SDA changing -
-        /// when DW_apb_i2c services a read request in a slave-transmitter operation. The
-        /// relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus
-        /// Specification. This register must be programmed with a value equal to or greater
-        /// than 2.\n\n
-        /// Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n
-        /// Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) *
-        /// (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they
-        /// should program a value of 11. The IC_SDA_SETUP register is only used by the
-        /// DW_apb_i2c when operating as a slave transmitter.
-        pub const IC_SDA_SETUP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SDA Setup. It is recommended that if the required delay is 1000ns, then for an
-            /// ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11.
-            /// IC_SDA_SETUP must be programmed with a minimum value of 2.
-            SDA_SETUP: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x94);
-
-        /// address: 0x40044098
-        /// I2C ACK General Call Register\n\n
-        /// The register controls whether DW_apb_i2c responds with a ACK or NACK when it
-        /// receives an I2C General Call address.\n\n
-        /// This register is applicable only when the DW_apb_i2c is in slave mode.
-        pub const IC_ACK_GENERAL_CALL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting
-            /// ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with
-            /// a NACK (by negating ic_data_oe).
-            ACK_GEN_CALL: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x98);
-
-        /// address: 0x4004409c
-        /// I2C Enable Status Register\n\n
-        /// The register is used to report the DW_apb_i2c hardware status when the
-        /// IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is
-        /// disabled.\n\n
-        /// If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced
-        /// to 1.\n\n
-        /// If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is
-        /// read as '0'.\n\n
-        /// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read
-        /// as 0 because disabling the DW_apb_i2c depends on I2C bus activities.
-        pub const IC_ENABLE_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// ic_en Status. This bit always reflects the value driven on the output port
-            /// ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When
-            /// read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely
-            /// read this bit anytime. When this bit is read as 0, the CPU can safely read
-            /// SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n
-            /// Reset value: 0x0
-            IC_EN: u1,
-            /// Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential
-            /// or active Slave operation has been aborted due to the setting bit 0 of the
-            /// IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the
-            /// IC_ENABLE register while:\n\n
-            /// (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation
-            /// from a remote master;\n\n
-            /// OR,\n\n
-            /// (b) address and data bytes of the Slave-Receiver operation from a remote
-            /// master.\n\n
-            /// When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an
-            /// I2C transfer, irrespective of whether the I2C address matches the slave address
-            /// set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before
-            /// IC_ENABLE is set to 0 but has not taken effect.\n\n
-            /// Note: If the remote I2C master terminates the transfer with a STOP condition
-            /// before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been
-            /// set to 0, then this bit will also be set to 1.\n\n
-            /// When read as 0, DW_apb_i2c is deemed to have been disabled when there is master
-            /// activity, or when the I2C bus is idle.\n\n
-            /// Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n
-            /// Reset value: 0x0
-            SLV_DISABLED_WHILE_BUSY: u1,
-            /// Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has
-            /// been aborted with at least one data byte received from an I2C transfer due to
-            /// the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed
-            /// to have been actively engaged in an aborted I2C transfer (with matching address)
-            /// and the data phase of the I2C transfer has been entered, even though a data byte
-            /// has been responded with a NACK.\n\n
-            /// Note: If the remote I2C master terminates the transfer with a STOP condition
-            /// before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been
-            /// set to 0, then this bit is also set to 1.\n\n
-            /// When read as 0, DW_apb_i2c is deemed to have been disabled without being
-            /// actively involved in the data phase of a Slave-Receiver transfer.\n\n
-            /// Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n
-            /// Reset value: 0x0
-            SLV_RX_DATA_LOST: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-        }), base_address + 0x9c);
-
-        /// address: 0x400440a0
-        /// I2C SS, FS or FM+ spike suppression limit\n\n
-        /// This register is used to store the duration, measured in ic_clk cycles, of the
-        /// longest spike that is filtered out by the spike suppression logic when the
-        /// component is operating in SS, FS or FM+ modes. The relevant I2C requirement is
-        /// tSP (table 4) as detailed in the I2C Bus Specification. This register must be
-        /// programmed with a minimum value of 1.
-        pub const IC_FS_SPKLEN = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xa0);
-
-        /// address: 0x400440a8
-        /// Clear RESTART_DET Interrupt Register
-        pub const IC_CLR_RESTART_DET = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the RESTART_DET interrupt (bit 12) of
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_RESTART_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0xa8);
-
-        /// address: 0x400440f4
-        /// Component Parameter Register 1\n\n
-        /// Note This register is not implemented and therefore reads as 0. If it was
-        /// implemented it would be a constant read-only register that contains encoded
-        /// information about the component's parameter settings. Fields shown below are the
-        /// settings for those parameters
-        pub const IC_COMP_PARAM_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// APB data bus width is 32 bits
-            APB_DATA_WIDTH: u2,
-            /// MAX SPEED MODE = FAST MODE
-            MAX_SPEED_MODE: u2,
-            /// Programmable count values for each mode.
-            HC_COUNT_VALUES: u1,
-            /// COMBINED Interrupt outputs
-            INTR_IO: u1,
-            /// DMA handshaking signals are enabled
-            HAS_DMA: u1,
-            /// Encoded parameters not visible
-            ADD_ENCODED_PARAMS: u1,
-            /// RX Buffer Depth = 16
-            RX_BUFFER_DEPTH: u8,
-            /// TX Buffer Depth = 16
-            TX_BUFFER_DEPTH: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0xf4);
-
-        /// address: 0x400440f8
-        /// I2C Component Version Register
-        pub const IC_COMP_VERSION = @intToPtr(*volatile u32, base_address + 0xf8);
-
-        /// address: 0x400440fc
-        /// I2C Component Type Register
-        pub const IC_COMP_TYPE = @intToPtr(*volatile u32, base_address + 0xfc);
-    };
-    pub const I2C1 = struct {
-        pub const base_address = 0x40048000;
-
-        /// address: 0x40048000
-        /// I2C Control Register. This register can be written only when the DW_apb_i2c is
-        /// disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes
-        /// at other times have no effect.\n\n
-        /// Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read
-        /// only - bit 17 is read only - bits 18 and 19 are read only.
-        pub const IC_CON = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit controls whether the DW_apb_i2c master is enabled.\n\n
-            /// NOTE: Software should ensure that if this bit is written with '1' then bit 6
-            /// should also be written with a '1'.
-            MASTER_MODE: u1,
-            /// These bits control at which speed the DW_apb_i2c operates; its setting is
-            /// relevant only if one is operating the DW_apb_i2c in master mode. Hardware
-            /// protects against illegal values being programmed by software. These bits must be
-            /// programmed appropriately for slave mode also, as it is used to capture correct
-            /// value of spike filter as per the speed mode.\n\n
-            /// This register should be programmed only with a value in the range of 1 to
-            /// IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of
-            /// IC_MAX_SPEED_MODE.\n\n
-            /// 1: standard mode (100 kbit/s)\n\n
-            /// 2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)\n\n
-            /// 3: high speed mode (3.4 Mbit/s)\n\n
-            /// Note: This field is not applicable when IC_ULTRA_FAST_MODE=1
-            SPEED: u2,
-            /// When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7-
-            /// or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions
-            /// that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of
-            /// the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c
-            /// responds to only 10-bit addressing transfers that match the full 10 bits of the
-            /// IC_SAR register.
-            IC_10BITADDR_SLAVE: u1,
-            /// Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing
-            /// mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing
-            IC_10BITADDR_MASTER: u1,
-            /// Determines whether RESTART conditions may be sent when acting as a master. Some
-            /// older slaves do not support handling RESTART conditions; however, RESTART
-            /// conditions are used in several DW_apb_i2c operations. When RESTART is disabled,
-            /// the master is prohibited from performing the following functions: - Sending a
-            /// START BYTE - Performing any high-speed mode operation - High-speed mode
-            /// operation - Performing direction changes in combined format mode - Performing a
-            /// read operation with a 10-bit address By replacing RESTART condition followed by
-            /// a STOP and a subsequent START condition, split operations are broken down into
-            /// multiple DW_apb_i2c transfers. If the above operations are performed, it will
-            /// result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: ENABLED
-            IC_RESTART_EN: u1,
-            /// This bit controls whether I2C has its slave disabled, which means once the
-            /// presetn signal is applied, then this bit is set and the slave is disabled.\n\n
-            /// If this bit is set (slave is disabled), DW_apb_i2c functions only as a master
-            /// and does not perform any action that requires a slave.\n\n
-            /// NOTE: Software should ensure that if this bit is written with 0, then bit 0
-            /// should also be written with a 0.
-            IC_SLAVE_DISABLE: u1,
-            /// In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed.
-            /// - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset
-            /// value: 0x0\n\n
-            /// NOTE: During a general call address, this slave does not issue the STOP_DET
-            /// interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the
-            /// general call address by generating ACK. The STOP_DET interrupt is generated only
-            /// when the transmitted address matches the slave address (SAR).
-            STOP_DET_IFADDRESSED: u1,
-            /// This bit controls the generation of the TX_EMPTY interrupt, as described in the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0.
-            TX_EMPTY_CTRL: u1,
-            /// This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is
-            /// physically full to its RX_BUFFER_DEPTH, as described in the
-            /// IC_RX_FULL_HLD_BUS_EN parameter.\n\n
-            /// Reset value: 0x0.
-            RX_FIFO_FULL_HLD_CTRL: u1,
-            /// Master issues the STOP_DET interrupt irrespective of whether master is active or
-            /// not
-            STOP_DET_IF_MASTER_ACTIVE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40048004
-        /// I2C Target Address Register\n\n
-        /// This register is 12 bits wide, and bits 31:12 are reserved. This register can be
-        /// written to only when IC_ENABLE[0] is set to 0.\n\n
-        /// Note: If the software or application is aware that the DW_apb_i2c is not using
-        /// the TAR address for the pending commands in the Tx FIFO, then it is possible to
-        /// update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). -
-        /// It is not necessary to perform any write to this register if DW_apb_i2c is
-        /// enabled as an I2C slave only.
-        pub const IC_TAR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the target address for any master transaction. When transmitting a
-            /// General Call, these bits are ignored. To generate a START BYTE, the CPU needs to
-            /// write only once into these bits.\n\n
-            /// If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared
-            /// between master and slave, so full loopback is not feasible. Only one direction
-            /// loopback mode is supported (simplex), not duplex. A master cannot transmit to
-            /// itself; it can transmit to only a slave.
-            IC_TAR: u10,
-            /// If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit
-            /// indicates whether a General Call or START byte command is to be performed by the
-            /// DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only
-            /// writes may be performed. Attempting to issue a read command results in setting
-            /// bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in
-            /// General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START
-            /// BYTE Reset value: 0x0
-            GC_OR_START: u1,
-            /// This bit indicates whether software performs a Device-ID or General Call or
-            /// START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1:
-            /// perform special I2C command as specified in Device_ID or GC_OR_START bit Reset
-            /// value: 0x0
-            SPECIAL: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40048008
-        /// I2C Slave Address Register
-        pub const IC_SAR = @intToPtr(*volatile MmioInt(32, u10), base_address + 0x8);
-
-        /// address: 0x40048010
-        /// I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes
-        /// to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX
-        /// FIFO.\n\n
-        /// The size of the register changes as follows:\n\n
-        /// Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when
-        /// IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1
-        /// - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to
-        /// continue acknowledging reads, a read command should be written for every byte
-        /// that is to be received; otherwise the DW_apb_i2c will stop acknowledging.
-        pub const IC_DATA_CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register contains the data to be transmitted or received on the I2C bus. If
-            /// you are writing to this register and want to perform a read, bits 7:0 (DAT) are
-            /// ignored by the DW_apb_i2c. However, when you read this register, these bits
-            /// return the value of data received on the DW_apb_i2c interface.\n\n
-            /// Reset value: 0x0
-            DAT: u8,
-            /// This bit controls whether a read or a write is performed. This bit does not
-            /// control the direction when the DW_apb_i2con acts as a slave. It controls only
-            /// the direction when it acts as a master.\n\n
-            /// When a command is entered in the TX FIFO, this bit distinguishes the write and
-            /// read commands. In slave-receiver mode, this bit is a 'don't care' because writes
-            /// to this register are not required. In slave-transmitter mode, a '0' indicates
-            /// that the data in IC_DATA_CMD is to be transmitted.\n\n
-            /// When programming this bit, you should remember the following: attempting to
-            /// perform a read operation after a General Call command has been sent results in a
-            /// TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11
-            /// (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this
-            /// bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.\n\n
-            /// Reset value: 0x0
-            CMD: u1,
-            /// This bit controls whether a STOP is issued after the byte is sent or
-            /// received.\n\n
-            /// - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO
-            /// is empty. If the Tx FIFO is not empty, the master immediately tries to start a
-            /// new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not
-            /// issued after this byte, regardless of whether or not the Tx FIFO is empty. If
-            /// the Tx FIFO is not empty, the master continues the current transfer by
-            /// sending/receiving data bytes according to the value of the CMD bit. If the Tx
-            /// FIFO is empty, the master holds the SCL line low and stalls the bus until a new
-            /// command is available in the Tx FIFO. Reset value: 0x0
-            STOP: u1,
-            /// This bit controls whether a RESTART is issued before the byte is sent or
-            /// received.\n\n
-            /// 1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received
-            /// (according to the value of CMD), regardless of whether or not the transfer
-            /// direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP
-            /// followed by a START is issued instead.\n\n
-            /// 0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is
-            /// changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a
-            /// START is issued instead.\n\n
-            /// Reset value: 0x0
-            RESTART: u1,
-            /// Indicates the first data byte received after the address phase for receive
-            /// transfer in Master receiver or Slave receiver mode.\n\n
-            /// Reset value : 0x0\n\n
-            /// NOTE: In case of APB_DATA_WIDTH=8,\n\n
-            /// 1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status
-            /// on 11 bit.\n\n
-            /// 2. In order to read the 11 bit, the user has to perform the first data byte read
-            /// [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in
-            /// order to know the status of 11 bit (whether the data received in previous read
-            /// is a first data byte or not).\n\n
-            /// 3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8]
-            /// (offset 0x11) if not interested in FIRST_DATA_BYTE status.
-            FIRST_DATA_BYTE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x10);
-
-        /// address: 0x40048014
-        /// Standard Speed I2C Clock SCL High Count Register
-        pub const IC_SS_SCL_HCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x14);
-
-        /// address: 0x40048018
-        /// Standard Speed I2C Clock SCL Low Count Register
-        pub const IC_SS_SCL_LCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x18);
-
-        /// address: 0x4004801c
-        /// Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
-        pub const IC_FS_SCL_HCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c);
-
-        /// address: 0x40048020
-        /// Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
-        pub const IC_FS_SCL_LCNT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x20);
-
-        /// address: 0x4004802c
-        /// I2C Interrupt Status Register\n\n
-        /// Each bit in this register has a corresponding mask bit in the IC_INTR_MASK
-        /// register. These bits are cleared by reading the matching interrupt clear
-        /// register. The unmasked raw versions of these bits are available in the
-        /// IC_RAW_INTR_STAT register.
-        pub const IC_INTR_STAT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.\n\n
-            /// Reset value: 0x0
-            R_RX_UNDER: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.\n\n
-            /// Reset value: 0x0
-            R_RX_OVER: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.\n\n
-            /// Reset value: 0x0
-            R_RX_FULL: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.\n\n
-            /// Reset value: 0x0
-            R_TX_OVER: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.\n\n
-            /// Reset value: 0x0
-            R_TX_EMPTY: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.\n\n
-            /// Reset value: 0x0
-            R_RD_REQ: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.\n\n
-            /// Reset value: 0x0
-            R_TX_ABRT: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.\n\n
-            /// Reset value: 0x0
-            R_RX_DONE: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.\n\n
-            /// Reset value: 0x0
-            R_ACTIVITY: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.\n\n
-            /// Reset value: 0x0
-            R_STOP_DET: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.\n\n
-            /// Reset value: 0x0
-            R_START_DET: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.\n\n
-            /// Reset value: 0x0
-            R_GEN_CALL: u1,
-            /// See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.\n\n
-            /// Reset value: 0x0
-            R_RESTART_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-        }), base_address + 0x2c);
-
-        /// address: 0x40048030
-        /// I2C Interrupt Mask Register.\n\n
-        /// These bits mask their corresponding interrupt status bits. This register is
-        /// active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the
-        /// interrupt.
-        pub const IC_INTR_MASK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_RX_UNDER: u1,
-            /// This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_RX_OVER: u1,
-            /// This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_RX_FULL: u1,
-            /// This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_TX_OVER: u1,
-            /// This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_TX_EMPTY: u1,
-            /// This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_RD_REQ: u1,
-            /// This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_TX_ABRT: u1,
-            /// This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_RX_DONE: u1,
-            /// This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            M_ACTIVITY: u1,
-            /// This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            M_STOP_DET: u1,
-            /// This bit masks the R_START_DET interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            M_START_DET: u1,
-            /// This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x1
-            M_GEN_CALL: u1,
-            /// This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            M_RESTART_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-        }), base_address + 0x30);
-
-        /// address: 0x40048034
-        /// I2C Raw Interrupt Status Register\n\n
-        /// Unlike the IC_INTR_STAT register, these bits are not masked so they always show
-        /// the true status of the DW_apb_i2c.
-        pub const IC_RAW_INTR_STAT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set if the processor attempts to read the receive buffer when it is empty by
-            /// reading from the IC_DATA_CMD register. If the module is disabled
-            /// (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state
-            /// machines go into idle, and when ic_en goes to 0, this interrupt is cleared.\n\n
-            /// Reset value: 0x0
-            RX_UNDER: u1,
-            /// Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an
-            /// additional byte is received from an external I2C device. The DW_apb_i2c
-            /// acknowledges this, but any data bytes received after the FIFO is full are lost.
-            /// If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the
-            /// master or slave state machines go into idle, and when ic_en goes to 0, this
-            /// interrupt is cleared.\n\n
-            /// Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to
-            /// HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never
-            /// overflows.\n\n
-            /// Reset value: 0x0
-            RX_OVER: u1,
-            /// Set when the receive buffer reaches or goes above the RX_TL threshold in the
-            /// IC_RX_TL register. It is automatically cleared by hardware when buffer level
-            /// goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX
-            /// FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this
-            /// bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of
-            /// the activity that continues.\n\n
-            /// Reset value: 0x0
-            RX_FULL: u1,
-            /// Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and
-            /// the processor attempts to issue another I2C command by writing to the
-            /// IC_DATA_CMD register. When the module is disabled, this bit keeps its level
-            /// until the master or slave state machines go into idle, and when ic_en goes to 0,
-            /// this interrupt is cleared.\n\n
-            /// Reset value: 0x0
-            TX_OVER: u1,
-            /// The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL
-            /// selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1
-            /// when the transmit buffer is at or below the threshold value set in the IC_TX_TL
-            /// register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit
-            /// buffer is at or below the threshold value set in the IC_TX_TL register and the
-            /// transmission of the address/data from the internal shift register for the most
-            /// recently popped command is completed. It is automatically cleared by hardware
-            /// when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0,
-            /// the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no
-            /// data within it, so this bit is set to 1, provided there is activity in the
-            /// master or slave state machines. When there is no longer any activity, then with
-            /// ic_en=0, this bit is set to 0.\n\n
-            /// Reset value: 0x0.
-            TX_EMPTY: u1,
-            /// This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master
-            /// is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in
-            /// a wait state (SCL=0) until this interrupt is serviced, which means that the
-            /// slave has been addressed by a remote master that is asking for data to be
-            /// transferred. The processor must respond to this interrupt and then write the
-            /// requested data to the IC_DATA_CMD register. This bit is set to 0 just after the
-            /// processor reads the IC_CLR_RD_REQ register.\n\n
-            /// Reset value: 0x0
-            RD_REQ: u1,
-            /// This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete
-            /// the intended actions on the contents of the transmit FIFO. This situation can
-            /// occur both as an I2C master or an I2C slave, and is referred to as a 'transmit
-            /// abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the
-            /// reason why the transmit abort takes places.\n\n
-            /// Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever
-            /// there is a transmit abort caused by any of the events tracked by the
-            /// IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the
-            /// register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is
-            /// then ready to accept more data bytes from the APB interface.\n\n
-            /// Reset value: 0x0
-            TX_ABRT: u1,
-            /// When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if
-            /// the master does not acknowledge a transmitted byte. This occurs on the last byte
-            /// of the transmission, indicating that the transmission is done.\n\n
-            /// Reset value: 0x0
-            RX_DONE: u1,
-            /// This bit captures DW_apb_i2c activity and stays set until it is cleared. There
-            /// are four ways to clear it: - Disabling the DW_apb_i2c - Reading the
-            /// IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once
-            /// this bit is set, it stays set unless one of the four methods is used to clear
-            /// it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared,
-            /// indicating that there was activity on the bus.\n\n
-            /// Reset value: 0x0
-            ACTIVITY: u1,
-            /// Indicates whether a STOP condition has occurred on the I2C interface regardless
-            /// of whether DW_apb_i2c is operating in slave or master mode.\n\n
-            /// In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET
-            /// interrupt will be issued only if slave is addressed. Note: During a general call
-            /// address, this slave does not issue a STOP_DET interrupt if
-            /// STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call
-            /// address by generating ACK. The STOP_DET interrupt is generated only when the
-            /// transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0
-            /// (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether
-            /// it is being addressed. In Master Mode: - If IC_CON[10]=1'b1
-            /// (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master
-            /// is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt
-            /// will be issued irrespective of whether master is active or not. Reset value: 0x0
-            STOP_DET: u1,
-            /// Indicates whether a START or RESTART condition has occurred on the I2C interface
-            /// regardless of whether DW_apb_i2c is operating in slave or master mode.\n\n
-            /// Reset value: 0x0
-            START_DET: u1,
-            /// Set only when a General Call address is received and it is acknowledged. It
-            /// stays set until it is cleared either by disabling DW_apb_i2c or when the CPU
-            /// reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data
-            /// in the Rx buffer.\n\n
-            /// Reset value: 0x0
-            GEN_CALL: u1,
-            /// Indicates whether a RESTART condition has occurred on the I2C interface when
-            /// DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled
-            /// only when IC_SLV_RESTART_DET_EN=1.\n\n
-            /// Note: However, in high-speed mode or during a START BYTE transfer, the RESTART
-            /// comes before the address field as per the I2C protocol. In this case, the slave
-            /// is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does
-            /// not generate the RESTART_DET interrupt.\n\n
-            /// Reset value: 0x0
-            RESTART_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-        }), base_address + 0x34);
-
-        /// address: 0x40048038
-        /// I2C Receive FIFO Threshold Register
-        pub const IC_RX_TL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive FIFO Threshold Level.\n\n
-            /// Controls the level of entries (or above) that triggers the RX_FULL interrupt
-            /// (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the
-            /// additional restriction that hardware does not allow this value to be set to a
-            /// value larger than the depth of the buffer. If an attempt is made to do that, the
-            /// actual value set will be the maximum depth of the buffer. A value of 0 sets the
-            /// threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
-            RX_TL: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x38);
-
-        /// address: 0x4004803c
-        /// I2C Transmit FIFO Threshold Register
-        pub const IC_TX_TL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit FIFO Threshold Level.\n\n
-            /// Controls the level of entries (or below) that trigger the TX_EMPTY interrupt
-            /// (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the
-            /// additional restriction that it may not be set to value larger than the depth of
-            /// the buffer. If an attempt is made to do that, the actual value set will be the
-            /// maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and
-            /// a value of 255 sets the threshold for 255 entries.
-            TX_TL: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x3c);
-
-        /// address: 0x40048040
-        /// Clear Combined and Individual Interrupt Register
-        pub const IC_CLR_INTR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the combined interrupt, all individual interrupts,
-            /// and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable
-            /// interrupts but software clearable interrupts. Refer to Bit 9 of the
-            /// IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.\n\n
-            /// Reset value: 0x0
-            CLR_INTR: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x40);
-
-        /// address: 0x40048044
-        /// Clear RX_UNDER Interrupt Register
-        pub const IC_CLR_RX_UNDER = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the RX_UNDER interrupt (bit 0) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_RX_UNDER: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x44);
-
-        /// address: 0x40048048
-        /// Clear RX_OVER Interrupt Register
-        pub const IC_CLR_RX_OVER = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the RX_OVER interrupt (bit 1) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_RX_OVER: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x48);
-
-        /// address: 0x4004804c
-        /// Clear TX_OVER Interrupt Register
-        pub const IC_CLR_TX_OVER = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the TX_OVER interrupt (bit 3) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_TX_OVER: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x4c);
-
-        /// address: 0x40048050
-        /// Clear RD_REQ Interrupt Register
-        pub const IC_CLR_RD_REQ = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT
-            /// register.\n\n
-            /// Reset value: 0x0
-            CLR_RD_REQ: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x50);
-
-        /// address: 0x40048054
-        /// Clear TX_ABRT Interrupt Register
-        pub const IC_CLR_TX_ABRT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the TX_ABRT interrupt (bit 6) of the
-            /// IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also
-            /// releases the TX FIFO from the flushed/reset state, allowing more writes to the
-            /// TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to
-            /// clearing IC_TX_ABRT_SOURCE.\n\n
-            /// Reset value: 0x0
-            CLR_TX_ABRT: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x54);
-
-        /// address: 0x40048058
-        /// Clear RX_DONE Interrupt Register
-        pub const IC_CLR_RX_DONE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the RX_DONE interrupt (bit 7) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_RX_DONE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x58);
-
-        /// address: 0x4004805c
-        /// Clear ACTIVITY Interrupt Register
-        pub const IC_CLR_ACTIVITY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reading this register clears the ACTIVITY interrupt if the I2C is not active
-            /// anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt
-            /// bit continues to be set. It is automatically cleared by hardware if the module
-            /// is disabled and if there is no further activity on the bus. The value read from
-            /// this register to get status of the ACTIVITY interrupt (bit 8) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_ACTIVITY: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x5c);
-
-        /// address: 0x40048060
-        /// Clear STOP_DET Interrupt Register
-        pub const IC_CLR_STOP_DET = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the STOP_DET interrupt (bit 9) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_STOP_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x60);
-
-        /// address: 0x40048064
-        /// Clear START_DET Interrupt Register
-        pub const IC_CLR_START_DET = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the START_DET interrupt (bit 10) of the
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_START_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x64);
-
-        /// address: 0x40048068
-        /// Clear GEN_CALL Interrupt Register
-        pub const IC_CLR_GEN_CALL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT
-            /// register.\n\n
-            /// Reset value: 0x0
-            CLR_GEN_CALL: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x68);
-
-        /// address: 0x4004806c
-        /// I2C Enable Register
-        pub const IC_ENABLE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX
-            /// FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable
-            /// DW_apb_i2c while it is active. However, it is important that care be taken to
-            /// ensure that DW_apb_i2c is disabled properly. A recommended procedure is
-            /// described in 'Disabling DW_apb_i2c'.\n\n
-            /// When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get
-            /// flushed. - Status bits in the IC_INTR_STAT register are still active until
-            /// DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well
-            /// as deletes the contents of the transmit buffer after the current transfer is
-            /// complete. If the module is receiving, the DW_apb_i2c stops the current transfer
-            /// at the end of the current byte and does not acknowledge the transfer.\n\n
-            /// In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to
-            /// asynchronous (1), there is a two ic_clk delay when enabling or disabling the
-            /// DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to
-            /// 'Disabling DW_apb_i2c'\n\n
-            /// Reset value: 0x0
-            ENABLE: u1,
-            /// When set, the controller initiates the transfer abort. - 0: ABORT not initiated
-            /// or ABORT done - 1: ABORT operation in progress The software can abort the I2C
-            /// transfer in master mode by setting this bit. The software can set this bit only
-            /// when ENABLE is already set; otherwise, the controller ignores any write to ABORT
-            /// bit. The software cannot clear the ABORT bit once set. In response to an ABORT,
-            /// the controller issues a STOP and flushes the Tx FIFO after completing the
-            /// current transfer, then sets the TX_ABORT interrupt after the abort operation.
-            /// The ABORT bit is cleared automatically after the abort operation.\n\n
-            /// For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C
-            /// Transfers'.\n\n
-            /// Reset value: 0x0
-            ABORT: u1,
-            /// In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx
-            /// FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus
-            /// automatically, as soon as the first data is available in the Tx FIFO. Note: To
-            /// block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx
-            /// FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0).
-            /// Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit
-            /// is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT
-            TX_CMD_BLOCK: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-        }), base_address + 0x6c);
-
-        /// address: 0x40048070
-        /// I2C Status Register\n\n
-        /// This is a read-only register used to indicate the current transfer status and
-        /// FIFO status. The status register may be read at any time. None of the bits in
-        /// this register request an interrupt.\n\n
-        /// When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits
-        /// 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state
-        /// machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0
-        pub const IC_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// I2C Activity Status. Reset value: 0x0
-            ACTIVITY: u1,
-            /// Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty
-            /// locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1:
-            /// Transmit FIFO is not full Reset value: 0x1
-            TFNF: u1,
-            /// Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this
-            /// bit is set. When it contains one or more valid entries, this bit is cleared.
-            /// This bit field does not request an interrupt. - 0: Transmit FIFO is not empty -
-            /// 1: Transmit FIFO is empty Reset value: 0x1
-            TFE: u1,
-            /// Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or
-            /// more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is
-            /// empty - 1: Receive FIFO is not empty Reset value: 0x0
-            RFNE: u1,
-            /// Receive FIFO Completely Full. When the receive FIFO is completely full, this bit
-            /// is set. When the receive FIFO contains one or more empty location, this bit is
-            /// cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value:
-            /// 0x0
-            RFF: u1,
-            /// Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in
-            /// the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master
-            /// part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the
-            /// Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is
-            /// the OR of SLV_ACTIVITY and MST_ACTIVITY bits.\n\n
-            /// Reset value: 0x0
-            MST_ACTIVITY: u1,
-            /// Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in
-            /// the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave
-            /// part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the
-            /// Slave part of DW_apb_i2c is Active Reset value: 0x0
-            SLV_ACTIVITY: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-        }), base_address + 0x70);
-
-        /// address: 0x40048074
-        /// I2C Transmit FIFO Level Register This register contains the number of valid data
-        /// entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is
-        /// disabled - There is a transmit abort - that is, TX_ABRT bit is set in the
-        /// IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register
-        /// increments whenever data is placed into the transmit FIFO and decrements when
-        /// data is taken from the transmit FIFO.
-        pub const IC_TXFLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit FIFO Level. Contains the number of valid data entries in the transmit
-            /// FIFO.\n\n
-            /// Reset value: 0x0
-            TXFLR: u5,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-        }), base_address + 0x74);
-
-        /// address: 0x40048078
-        /// I2C Receive FIFO Level Register This register contains the number of valid data
-        /// entries in the receive FIFO buffer. It is cleared whenever: - The I2C is
-        /// disabled - Whenever there is a transmit abort caused by any of the events
-        /// tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed
-        /// into the receive FIFO and decrements when data is taken from the receive FIFO.
-        pub const IC_RXFLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive FIFO Level. Contains the number of valid data entries in the receive
-            /// FIFO.\n\n
-            /// Reset value: 0x0
-            RXFLR: u5,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-        }), base_address + 0x78);
-
-        /// address: 0x4004807c
-        /// I2C SDA Hold Time Length Register\n\n
-        /// The bits [15:0] of this register are used to control the hold time of SDA during
-        /// transmit in both slave and master mode (after SCL goes from HIGH to LOW).\n\n
-        /// The bits [23:16] of this register are used to extend the SDA transition (if any)
-        /// whenever SCL is HIGH in the receiver in either master or slave mode.\n\n
-        /// Writes to this register succeed only when IC_ENABLE[0]=0.\n\n
-        /// The values in this register are in units of ic_clk period. The value programmed
-        /// in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one
-        /// cycle in master mode, seven cycles in slave mode) for the value to be
-        /// implemented.\n\n
-        /// The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at
-        /// any time the duration of the low part of scl. Therefore the programmed value
-        /// cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low
-        /// part of the scl period measured in ic_clk cycles.
-        pub const IC_SDA_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts
-            /// as a transmitter.\n\n
-            /// Reset value: IC_DEFAULT_SDA_HOLD[15:0].
-            IC_SDA_TX_HOLD: u16,
-            /// Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts
-            /// as a receiver.\n\n
-            /// Reset value: IC_DEFAULT_SDA_HOLD[23:16].
-            IC_SDA_RX_HOLD: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x7c);
-
-        /// address: 0x40048080
-        /// I2C Transmit Abort Source Register\n\n
-        /// This register has 32 bits that indicate the source of the TX_ABRT bit. Except
-        /// for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the
-        /// IC_CLR_INTR register is read. To clear Bit 9, the source of the
-        /// ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1),
-        /// the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be
-        /// cleared (IC_TAR[10]).\n\n
-        /// Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared
-        /// in the same manner as other bits in this register. If the source of the
-        /// ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9
-        /// clears for one cycle and is then re-asserted.
-        pub const IC_TX_ABRT_SOURCE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This field indicates that the Master is in 7-bit addressing mode and the address
-            /// sent was not acknowledged by any slave.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-            ABRT_7B_ADDR_NOACK: u1,
-            /// This field indicates that the Master is in 10-bit address mode and the first
-            /// 10-bit address byte was not acknowledged by any slave.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-            ABRT_10ADDR1_NOACK: u1,
-            /// This field indicates that the Master is in 10-bit address mode and that the
-            /// second address byte of the 10-bit address was not acknowledged by any slave.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-            ABRT_10ADDR2_NOACK: u1,
-            /// This field indicates the master-mode only bit. When the master receives an
-            /// acknowledgement for the address, but when it sends data byte(s) following the
-            /// address, it did not receive an acknowledge from the remote slave(s).\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter
-            ABRT_TXDATA_NOACK: u1,
-            /// This field indicates that DW_apb_i2c in master mode has sent a General Call and
-            /// no slave on the bus acknowledged the General Call.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter
-            ABRT_GCALL_NOACK: u1,
-            /// This field indicates that DW_apb_i2c in the master mode has sent a General Call
-            /// but the user programmed the byte following the General Call to be a read from
-            /// the bus (IC_DATA_CMD[9] is set to 1).\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter
-            ABRT_GCALL_READ: u1,
-            /// This field indicates that the Master is in High Speed mode and the High Speed
-            /// Master code was acknowledged (wrong behavior).\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master
-            ABRT_HS_ACKDET: u1,
-            /// This field indicates that the Master has sent a START Byte and the START Byte
-            /// was acknowledged (wrong behavior).\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master
-            ABRT_SBYTE_ACKDET: u1,
-            /// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5])
-            /// =0) and the user is trying to use the master to transfer data in High Speed
-            /// mode.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-            ABRT_HS_NORSTRT: u1,
-            /// To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first;
-            /// restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared
-            /// (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the
-            /// source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the
-            /// same manner as other bits in this register. If the source of the
-            /// ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9
-            /// clears for one cycle and then gets reasserted. When this field is set to 1, the
-            /// restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to
-            /// send a START Byte.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master
-            ABRT_SBYTE_NORSTRT: u1,
-            /// This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5])
-            /// =0) and the master sends a read command in 10-bit addressing mode.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Receiver
-            ABRT_10B_RD_NORSTRT: u1,
-            /// This field indicates that the User tries to initiate a Master operation with the
-            /// Master mode disabled.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-            ABRT_MASTER_DIS: u1,
-            /// This field specifies that the Master has lost arbitration, or if
-            /// IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost
-            /// arbitration.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
-            ARB_LOST: u1,
-            /// This field specifies that the Slave has received a read command and some data
-            /// exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data
-            /// in TX FIFO.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Slave-Transmitter
-            ABRT_SLVFLUSH_TXFIFO: u1,
-            /// This field indicates that a Slave has lost the bus while transmitting data to a
-            /// remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though
-            /// the slave never 'owns' the bus, something could go wrong on the bus. This is a
-            /// fail safe check. For instance, during a data transmission at the low-to-high
-            /// transition of SCL, if what is on the data bus is not what is supposed to be
-            /// transmitted, then DW_apb_i2c no longer own the bus.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Slave-Transmitter
-            ABRT_SLV_ARBLOST: u1,
-            /// 1: When the processor side responds to a slave mode request for data to be
-            /// transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD
-            /// register.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Slave-Transmitter
-            ABRT_SLVRD_INTX: u1,
-            /// This is a master-mode-only bit. Master has detected the transfer abort
-            /// (IC_ENABLE[1])\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter
-            ABRT_USER_ABRT: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            /// This field indicates the number of Tx FIFO Data Commands which are flushed due
-            /// to TX_ABRT interrupt. It is cleared whenever I2C is disabled.\n\n
-            /// Reset value: 0x0\n\n
-            /// Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
-            TX_FLUSH_CNT: u9,
-        }), base_address + 0x80);
-
-        /// address: 0x40048084
-        /// Generate Slave Data NACK Register\n\n
-        /// The register is used to generate a NACK for the data part of a transfer when
-        /// DW_apb_i2c is acting as a slave-receiver. This register only exists when the
-        /// IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this
-        /// register does not exist and writing to the register's address has no effect.\n\n
-        /// A write can occur on this register if both of the following conditions are met:
-        /// - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive
-        /// (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for
-        /// the internal slv_activity signal; the user should poll this before writing the
-        /// ic_slv_data_nack_only bit.
-        pub const IC_SLV_DATA_NACK_ONLY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Generate NACK. This NACK generation only occurs when DW_apb_i2c is a
-            /// slave-receiver. If this register is set to a value of 1, it can only generate a
-            /// NACK after a data byte is received; hence, the data transfer is aborted and the
-            /// data received is not pushed to the receive buffer.\n\n
-            /// When the register is set to a value of 0, it generates NACK/ACK, depending on
-            /// normal criteria. - 1: generate NACK after data byte received - 0: generate
-            /// NACK/ACK normally Reset value: 0x0
-            NACK: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x84);
-
-        /// address: 0x40048088
-        /// DMA Control Register\n\n
-        /// The register is used to enable the DMA Controller interface operation. There is
-        /// a separate bit for transmit and receive. This can be programmed regardless of
-        /// the state of IC_ENABLE.
-        pub const IC_DMA_CR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel.
-            /// Reset value: 0x0
-            RDMAE: u1,
-            /// Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel.
-            /// Reset value: 0x0
-            TDMAE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x88);
-
-        /// address: 0x4004808c
-        /// DMA Transmit Data Level Register
-        pub const IC_DMA_TDLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Transmit Data Level. This bit field controls the level at which a DMA request is
-            /// made by the transmit logic. It is equal to the watermark level; that is, the
-            /// dma_tx_req signal is generated when the number of valid data entries in the
-            /// transmit FIFO is equal to or below this field value, and TDMAE = 1.\n\n
-            /// Reset value: 0x0
-            DMATDL: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x8c);
-
-        /// address: 0x40048090
-        /// I2C Receive Data Level Register
-        pub const IC_DMA_RDLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive Data Level. This bit field controls the level at which a DMA request is
-            /// made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req
-            /// is generated when the number of valid data entries in the receive FIFO is equal
-            /// to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is
-            /// 0, then dma_rx_req is asserted when 1 or more data entries are present in the
-            /// receive FIFO.\n\n
-            /// Reset value: 0x0
-            DMARDL: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x90);
-
-        /// address: 0x40048094
-        /// I2C SDA Setup Register\n\n
-        /// This register controls the amount of time delay (in terms of number of ic_clk
-        /// clock periods) introduced in the rising edge of SCL - relative to SDA changing -
-        /// when DW_apb_i2c services a read request in a slave-transmitter operation. The
-        /// relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus
-        /// Specification. This register must be programmed with a value equal to or greater
-        /// than 2.\n\n
-        /// Writes to this register succeed only when IC_ENABLE[0] = 0.\n\n
-        /// Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) *
-        /// (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they
-        /// should program a value of 11. The IC_SDA_SETUP register is only used by the
-        /// DW_apb_i2c when operating as a slave transmitter.
-        pub const IC_SDA_SETUP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SDA Setup. It is recommended that if the required delay is 1000ns, then for an
-            /// ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11.
-            /// IC_SDA_SETUP must be programmed with a minimum value of 2.
-            SDA_SETUP: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x94);
-
-        /// address: 0x40048098
-        /// I2C ACK General Call Register\n\n
-        /// The register controls whether DW_apb_i2c responds with a ACK or NACK when it
-        /// receives an I2C General Call address.\n\n
-        /// This register is applicable only when the DW_apb_i2c is in slave mode.
-        pub const IC_ACK_GENERAL_CALL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting
-            /// ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with
-            /// a NACK (by negating ic_data_oe).
-            ACK_GEN_CALL: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x98);
-
-        /// address: 0x4004809c
-        /// I2C Enable Status Register\n\n
-        /// The register is used to report the DW_apb_i2c hardware status when the
-        /// IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is
-        /// disabled.\n\n
-        /// If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced
-        /// to 1.\n\n
-        /// If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is
-        /// read as '0'.\n\n
-        /// Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read
-        /// as 0 because disabling the DW_apb_i2c depends on I2C bus activities.
-        pub const IC_ENABLE_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// ic_en Status. This bit always reflects the value driven on the output port
-            /// ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When
-            /// read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely
-            /// read this bit anytime. When this bit is read as 0, the CPU can safely read
-            /// SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).\n\n
-            /// Reset value: 0x0
-            IC_EN: u1,
-            /// Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential
-            /// or active Slave operation has been aborted due to the setting bit 0 of the
-            /// IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the
-            /// IC_ENABLE register while:\n\n
-            /// (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation
-            /// from a remote master;\n\n
-            /// OR,\n\n
-            /// (b) address and data bytes of the Slave-Receiver operation from a remote
-            /// master.\n\n
-            /// When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an
-            /// I2C transfer, irrespective of whether the I2C address matches the slave address
-            /// set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before
-            /// IC_ENABLE is set to 0 but has not taken effect.\n\n
-            /// Note: If the remote I2C master terminates the transfer with a STOP condition
-            /// before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been
-            /// set to 0, then this bit will also be set to 1.\n\n
-            /// When read as 0, DW_apb_i2c is deemed to have been disabled when there is master
-            /// activity, or when the I2C bus is idle.\n\n
-            /// Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n
-            /// Reset value: 0x0
-            SLV_DISABLED_WHILE_BUSY: u1,
-            /// Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has
-            /// been aborted with at least one data byte received from an I2C transfer due to
-            /// the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed
-            /// to have been actively engaged in an aborted I2C transfer (with matching address)
-            /// and the data phase of the I2C transfer has been entered, even though a data byte
-            /// has been responded with a NACK.\n\n
-            /// Note: If the remote I2C master terminates the transfer with a STOP condition
-            /// before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been
-            /// set to 0, then this bit is also set to 1.\n\n
-            /// When read as 0, DW_apb_i2c is deemed to have been disabled without being
-            /// actively involved in the data phase of a Slave-Receiver transfer.\n\n
-            /// Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.\n\n
-            /// Reset value: 0x0
-            SLV_RX_DATA_LOST: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-        }), base_address + 0x9c);
-
-        /// address: 0x400480a0
-        /// I2C SS, FS or FM+ spike suppression limit\n\n
-        /// This register is used to store the duration, measured in ic_clk cycles, of the
-        /// longest spike that is filtered out by the spike suppression logic when the
-        /// component is operating in SS, FS or FM+ modes. The relevant I2C requirement is
-        /// tSP (table 4) as detailed in the I2C Bus Specification. This register must be
-        /// programmed with a minimum value of 1.
-        pub const IC_FS_SPKLEN = @intToPtr(*volatile MmioInt(32, u8), base_address + 0xa0);
-
-        /// address: 0x400480a8
-        /// Clear RESTART_DET Interrupt Register
-        pub const IC_CLR_RESTART_DET = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Read this register to clear the RESTART_DET interrupt (bit 12) of
-            /// IC_RAW_INTR_STAT register.\n\n
-            /// Reset value: 0x0
-            CLR_RESTART_DET: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0xa8);
-
-        /// address: 0x400480f4
-        /// Component Parameter Register 1\n\n
-        /// Note This register is not implemented and therefore reads as 0. If it was
-        /// implemented it would be a constant read-only register that contains encoded
-        /// information about the component's parameter settings. Fields shown below are the
-        /// settings for those parameters
-        pub const IC_COMP_PARAM_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// APB data bus width is 32 bits
-            APB_DATA_WIDTH: u2,
-            /// MAX SPEED MODE = FAST MODE
-            MAX_SPEED_MODE: u2,
-            /// Programmable count values for each mode.
-            HC_COUNT_VALUES: u1,
-            /// COMBINED Interrupt outputs
-            INTR_IO: u1,
-            /// DMA handshaking signals are enabled
-            HAS_DMA: u1,
-            /// Encoded parameters not visible
-            ADD_ENCODED_PARAMS: u1,
-            /// RX Buffer Depth = 16
-            RX_BUFFER_DEPTH: u8,
-            /// TX Buffer Depth = 16
-            TX_BUFFER_DEPTH: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0xf4);
-
-        /// address: 0x400480f8
-        /// I2C Component Version Register
-        pub const IC_COMP_VERSION = @intToPtr(*volatile u32, base_address + 0xf8);
-
-        /// address: 0x400480fc
-        /// I2C Component Type Register
-        pub const IC_COMP_TYPE = @intToPtr(*volatile u32, base_address + 0xfc);
-    };
-
-    /// Control and data interface to SAR ADC
-    pub const ADC = struct {
-        pub const base_address = 0x4004c000;
-        pub const version = "2";
-
-        /// address: 0x4004c000
-        /// ADC Control and Status
-        pub const CS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Power on ADC and enable its clock.\n
-            /// 1 - enabled. 0 - disabled.
-            EN: u1,
-            /// Power on temperature sensor. 1 - enabled. 0 - disabled.
-            TS_EN: u1,
-            /// Start a single conversion. Self-clearing. Ignored if start_many is asserted.
-            START_ONCE: u1,
-            /// Continuously perform conversions whilst this bit is 1. A new conversion will
-            /// start immediately after the previous finishes.
-            START_MANY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// 1 if the ADC is ready to start a new conversion. Implies any previous conversion
-            /// has completed.\n
-            /// 0 whilst conversion in progress.
-            READY: u1,
-            /// The most recent ADC conversion encountered an error; result is undefined or
-            /// noisy.
-            ERR: u1,
-            /// Some past ADC conversion encountered an error. Write 1 to clear.
-            ERR_STICKY: u1,
-            reserved4: u1 = 0,
-            /// Select analog mux input. Updated automatically in round-robin mode.
-            AINSEL: u3,
-            reserved5: u1 = 0,
-            /// Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.\n
-            /// Otherwise, the ADC will cycle through each enabled channel in a round-robin
-            /// fashion.\n
-            /// The first channel to be sampled will be the one currently indicated by AINSEL.\n
-            /// AINSEL will be updated after each conversion with the newly-selected channel.
-            RROBIN: u5,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x4004c004
-        /// Result of most recent ADC conversion
-        pub const RESULT = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x4);
-
-        /// address: 0x4004c008
-        /// FIFO control and status
-        pub const FCS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// If 1: write result to the FIFO after each conversion.
-            EN: u1,
-            /// If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte
-            /// buffers.
-            SHIFT: u1,
-            /// If 1: conversion error bit appears in the FIFO alongside the result
-            ERR: u1,
-            /// If 1: assert DMA requests when FIFO contains data
-            DREQ_EN: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            EMPTY: u1,
-            FULL: u1,
-            /// 1 if the FIFO has been underflowed. Write 1 to clear.
-            UNDER: u1,
-            /// 1 if the FIFO has been overflowed. Write 1 to clear.
-            OVER: u1,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// The number of conversion results currently waiting in the FIFO
-            LEVEL: u4,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            /// DREQ/IRQ asserted when level >= threshold
-            THRESH: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x4004c00c
-        /// Conversion result FIFO
-        pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct {
-            VAL: u12,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            /// 1 if this particular sample experienced a conversion error. Remains in the same
-            /// location if the sample is shifted.
-            ERR: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x4004c010
-        /// Clock divider. If non-zero, CS_START_MANY will start conversions\n
-        /// at regular intervals rather than back-to-back.\n
-        /// The divider is reset when either of these fields are written.\n
-        /// Total period is 1 + INT + FRAC / 256
-        pub const DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Fractional part of clock divisor. First-order delta-sigma.
-            FRAC: u8,
-            /// Integer part of clock divisor.
-            INT: u16,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x10);
-
-        /// address: 0x4004c014
-        /// Raw Interrupts
-        pub const INTR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Triggered when the sample FIFO reaches a certain level.\n
-            /// This level can be programmed via the FCS_THRESH field.
-            FIFO: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x4004c018
-        /// Interrupt Enable
-        pub const INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Triggered when the sample FIFO reaches a certain level.\n
-            /// This level can be programmed via the FCS_THRESH field.
-            FIFO: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x4004c01c
-        /// Interrupt Force
-        pub const INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Triggered when the sample FIFO reaches a certain level.\n
-            /// This level can be programmed via the FCS_THRESH field.
-            FIFO: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x1c);
-
-        /// address: 0x4004c020
-        /// Interrupt status after masking & forcing
-        pub const INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Triggered when the sample FIFO reaches a certain level.\n
-            /// This level can be programmed via the FCS_THRESH field.
-            FIFO: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x20);
-    };
-
-    /// Simple PWM
-    pub const PWM = struct {
-        pub const base_address = 0x40050000;
-        pub const version = "1";
-
-        /// address: 0x40050000
-        /// Control and status register
-        pub const CH0_CSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable the PWM channel.
-            EN: u1,
-            /// 1: Enable phase-correct modulation. 0: Trailing-edge
-            PH_CORRECT: u1,
-            /// Invert output A
-            A_INV: u1,
-            /// Invert output B
-            B_INV: u1,
-            DIVMODE: u2,
-            /// Retard the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running.
-            PH_RET: u1,
-            /// Advance the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running\n
-            /// at less than full speed (div_int + div_frac / 16 > 1)
-            PH_ADV: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40050004
-        /// INT and FRAC form a fixed-point fractional number.\n
-        /// Counting rate is system clock frequency divided by this number.\n
-        /// Fractional division uses simple 1st-order sigma-delta.
-        pub const CH0_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            FRAC: u4,
-            INT: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40050008
-        /// Direct access to the PWM counter
-        pub const CH0_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x8);
-
-        /// address: 0x4005000c
-        /// Counter compare values
-        pub const CH0_CC = @intToPtr(*volatile Mmio(32, packed struct {
-            A: u16,
-            B: u16,
-        }), base_address + 0xc);
-
-        /// address: 0x40050010
-        /// Counter wrap value
-        pub const CH0_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x10);
-
-        /// address: 0x40050014
-        /// Control and status register
-        pub const CH1_CSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable the PWM channel.
-            EN: u1,
-            /// 1: Enable phase-correct modulation. 0: Trailing-edge
-            PH_CORRECT: u1,
-            /// Invert output A
-            A_INV: u1,
-            /// Invert output B
-            B_INV: u1,
-            DIVMODE: u2,
-            /// Retard the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running.
-            PH_RET: u1,
-            /// Advance the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running\n
-            /// at less than full speed (div_int + div_frac / 16 > 1)
-            PH_ADV: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x40050018
-        /// INT and FRAC form a fixed-point fractional number.\n
-        /// Counting rate is system clock frequency divided by this number.\n
-        /// Fractional division uses simple 1st-order sigma-delta.
-        pub const CH1_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            FRAC: u4,
-            INT: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x4005001c
-        /// Direct access to the PWM counter
-        pub const CH1_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x1c);
-
-        /// address: 0x40050020
-        /// Counter compare values
-        pub const CH1_CC = @intToPtr(*volatile Mmio(32, packed struct {
-            A: u16,
-            B: u16,
-        }), base_address + 0x20);
-
-        /// address: 0x40050024
-        /// Counter wrap value
-        pub const CH1_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24);
-
-        /// address: 0x40050028
-        /// Control and status register
-        pub const CH2_CSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable the PWM channel.
-            EN: u1,
-            /// 1: Enable phase-correct modulation. 0: Trailing-edge
-            PH_CORRECT: u1,
-            /// Invert output A
-            A_INV: u1,
-            /// Invert output B
-            B_INV: u1,
-            DIVMODE: u2,
-            /// Retard the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running.
-            PH_RET: u1,
-            /// Advance the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running\n
-            /// at less than full speed (div_int + div_frac / 16 > 1)
-            PH_ADV: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x28);
-
-        /// address: 0x4005002c
-        /// INT and FRAC form a fixed-point fractional number.\n
-        /// Counting rate is system clock frequency divided by this number.\n
-        /// Fractional division uses simple 1st-order sigma-delta.
-        pub const CH2_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            FRAC: u4,
-            INT: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x2c);
-
-        /// address: 0x40050030
-        /// Direct access to the PWM counter
-        pub const CH2_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x30);
-
-        /// address: 0x40050034
-        /// Counter compare values
-        pub const CH2_CC = @intToPtr(*volatile Mmio(32, packed struct {
-            A: u16,
-            B: u16,
-        }), base_address + 0x34);
-
-        /// address: 0x40050038
-        /// Counter wrap value
-        pub const CH2_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x38);
-
-        /// address: 0x4005003c
-        /// Control and status register
-        pub const CH3_CSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable the PWM channel.
-            EN: u1,
-            /// 1: Enable phase-correct modulation. 0: Trailing-edge
-            PH_CORRECT: u1,
-            /// Invert output A
-            A_INV: u1,
-            /// Invert output B
-            B_INV: u1,
-            DIVMODE: u2,
-            /// Retard the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running.
-            PH_RET: u1,
-            /// Advance the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running\n
-            /// at less than full speed (div_int + div_frac / 16 > 1)
-            PH_ADV: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x3c);
-
-        /// address: 0x40050040
-        /// INT and FRAC form a fixed-point fractional number.\n
-        /// Counting rate is system clock frequency divided by this number.\n
-        /// Fractional division uses simple 1st-order sigma-delta.
-        pub const CH3_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            FRAC: u4,
-            INT: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x40);
-
-        /// address: 0x40050044
-        /// Direct access to the PWM counter
-        pub const CH3_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x44);
-
-        /// address: 0x40050048
-        /// Counter compare values
-        pub const CH3_CC = @intToPtr(*volatile Mmio(32, packed struct {
-            A: u16,
-            B: u16,
-        }), base_address + 0x48);
-
-        /// address: 0x4005004c
-        /// Counter wrap value
-        pub const CH3_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x4c);
-
-        /// address: 0x40050050
-        /// Control and status register
-        pub const CH4_CSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable the PWM channel.
-            EN: u1,
-            /// 1: Enable phase-correct modulation. 0: Trailing-edge
-            PH_CORRECT: u1,
-            /// Invert output A
-            A_INV: u1,
-            /// Invert output B
-            B_INV: u1,
-            DIVMODE: u2,
-            /// Retard the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running.
-            PH_RET: u1,
-            /// Advance the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running\n
-            /// at less than full speed (div_int + div_frac / 16 > 1)
-            PH_ADV: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x50);
-
-        /// address: 0x40050054
-        /// INT and FRAC form a fixed-point fractional number.\n
-        /// Counting rate is system clock frequency divided by this number.\n
-        /// Fractional division uses simple 1st-order sigma-delta.
-        pub const CH4_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            FRAC: u4,
-            INT: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x54);
-
-        /// address: 0x40050058
-        /// Direct access to the PWM counter
-        pub const CH4_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x58);
-
-        /// address: 0x4005005c
-        /// Counter compare values
-        pub const CH4_CC = @intToPtr(*volatile Mmio(32, packed struct {
-            A: u16,
-            B: u16,
-        }), base_address + 0x5c);
-
-        /// address: 0x40050060
-        /// Counter wrap value
-        pub const CH4_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x60);
-
-        /// address: 0x40050064
-        /// Control and status register
-        pub const CH5_CSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable the PWM channel.
-            EN: u1,
-            /// 1: Enable phase-correct modulation. 0: Trailing-edge
-            PH_CORRECT: u1,
-            /// Invert output A
-            A_INV: u1,
-            /// Invert output B
-            B_INV: u1,
-            DIVMODE: u2,
-            /// Retard the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running.
-            PH_RET: u1,
-            /// Advance the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running\n
-            /// at less than full speed (div_int + div_frac / 16 > 1)
-            PH_ADV: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x64);
-
-        /// address: 0x40050068
-        /// INT and FRAC form a fixed-point fractional number.\n
-        /// Counting rate is system clock frequency divided by this number.\n
-        /// Fractional division uses simple 1st-order sigma-delta.
-        pub const CH5_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            FRAC: u4,
-            INT: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x68);
-
-        /// address: 0x4005006c
-        /// Direct access to the PWM counter
-        pub const CH5_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x6c);
-
-        /// address: 0x40050070
-        /// Counter compare values
-        pub const CH5_CC = @intToPtr(*volatile Mmio(32, packed struct {
-            A: u16,
-            B: u16,
-        }), base_address + 0x70);
-
-        /// address: 0x40050074
-        /// Counter wrap value
-        pub const CH5_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x74);
-
-        /// address: 0x40050078
-        /// Control and status register
-        pub const CH6_CSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable the PWM channel.
-            EN: u1,
-            /// 1: Enable phase-correct modulation. 0: Trailing-edge
-            PH_CORRECT: u1,
-            /// Invert output A
-            A_INV: u1,
-            /// Invert output B
-            B_INV: u1,
-            DIVMODE: u2,
-            /// Retard the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running.
-            PH_RET: u1,
-            /// Advance the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running\n
-            /// at less than full speed (div_int + div_frac / 16 > 1)
-            PH_ADV: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x78);
-
-        /// address: 0x4005007c
-        /// INT and FRAC form a fixed-point fractional number.\n
-        /// Counting rate is system clock frequency divided by this number.\n
-        /// Fractional division uses simple 1st-order sigma-delta.
-        pub const CH6_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            FRAC: u4,
-            INT: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x7c);
-
-        /// address: 0x40050080
-        /// Direct access to the PWM counter
-        pub const CH6_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x80);
-
-        /// address: 0x40050084
-        /// Counter compare values
-        pub const CH6_CC = @intToPtr(*volatile Mmio(32, packed struct {
-            A: u16,
-            B: u16,
-        }), base_address + 0x84);
-
-        /// address: 0x40050088
-        /// Counter wrap value
-        pub const CH6_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x88);
-
-        /// address: 0x4005008c
-        /// Control and status register
-        pub const CH7_CSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable the PWM channel.
-            EN: u1,
-            /// 1: Enable phase-correct modulation. 0: Trailing-edge
-            PH_CORRECT: u1,
-            /// Invert output A
-            A_INV: u1,
-            /// Invert output B
-            B_INV: u1,
-            DIVMODE: u2,
-            /// Retard the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running.
-            PH_RET: u1,
-            /// Advance the phase of the counter by 1 count, while it is running.\n
-            /// Self-clearing. Write a 1, and poll until low. Counter must be running\n
-            /// at less than full speed (div_int + div_frac / 16 > 1)
-            PH_ADV: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x8c);
-
-        /// address: 0x40050090
-        /// INT and FRAC form a fixed-point fractional number.\n
-        /// Counting rate is system clock frequency divided by this number.\n
-        /// Fractional division uses simple 1st-order sigma-delta.
-        pub const CH7_DIV = @intToPtr(*volatile Mmio(32, packed struct {
-            FRAC: u4,
-            INT: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x90);
-
-        /// address: 0x40050094
-        /// Direct access to the PWM counter
-        pub const CH7_CTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x94);
-
-        /// address: 0x40050098
-        /// Counter compare values
-        pub const CH7_CC = @intToPtr(*volatile Mmio(32, packed struct {
-            A: u16,
-            B: u16,
-        }), base_address + 0x98);
-
-        /// address: 0x4005009c
-        /// Counter wrap value
-        pub const CH7_TOP = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x9c);
-
-        /// address: 0x400500a0
-        /// This register aliases the CSR_EN bits for all channels.\n
-        /// Writing to this register allows multiple channels to be enabled\n
-        /// or disabled simultaneously, so they can run in perfect sync.\n
-        /// For each channel, there is only one physical EN register bit,\n
-        /// which can be accessed through here or CHx_CSR.
-        pub const EN = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0: u1,
-            CH1: u1,
-            CH2: u1,
-            CH3: u1,
-            CH4: u1,
-            CH5: u1,
-            CH6: u1,
-            CH7: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xa0);
-
-        /// address: 0x400500a4
-        /// Raw Interrupts
-        pub const INTR = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0: u1,
-            CH1: u1,
-            CH2: u1,
-            CH3: u1,
-            CH4: u1,
-            CH5: u1,
-            CH6: u1,
-            CH7: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xa4);
-
-        /// address: 0x400500a8
-        /// Interrupt Enable
-        pub const INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0: u1,
-            CH1: u1,
-            CH2: u1,
-            CH3: u1,
-            CH4: u1,
-            CH5: u1,
-            CH6: u1,
-            CH7: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xa8);
-
-        /// address: 0x400500ac
-        /// Interrupt Force
-        pub const INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0: u1,
-            CH1: u1,
-            CH2: u1,
-            CH3: u1,
-            CH4: u1,
-            CH5: u1,
-            CH6: u1,
-            CH7: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xac);
-
-        /// address: 0x400500b0
-        /// Interrupt status after masking & forcing
-        pub const INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0: u1,
-            CH1: u1,
-            CH2: u1,
-            CH3: u1,
-            CH4: u1,
-            CH5: u1,
-            CH6: u1,
-            CH7: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0xb0);
-    };
-
-    /// Controls time and alarms\n
-    /// time is a 64 bit value indicating the time in usec since power-on\n
-    /// timeh is the top 32 bits of time & timel is the bottom 32 bits\n
-    /// to change time write to timelw before timehw\n
-    /// to read time read from timelr before timehr\n
-    /// An alarm is set by setting alarm_enable and writing to the corresponding alarm
-    /// register\n
-    /// When an alarm is pending, the corresponding alarm_running signal will be high\n
-    /// An alarm can be cancelled before it has finished by clearing the alarm_enable\n
-    /// When an alarm fires, the corresponding alarm_irq is set and alarm_running is
-    /// cleared\n
-    /// To clear the interrupt write a 1 to the corresponding alarm_irq
-    pub const TIMER = struct {
-        pub const base_address = 0x40054000;
-        pub const version = "1";
-
-        /// address: 0x40054000
-        /// Write to bits 63:32 of time\n
-        /// always write timelw before timehw
-        pub const TIMEHW = @intToPtr(*volatile u32, base_address + 0x0);
-
-        /// address: 0x40054004
-        /// Write to bits 31:0 of time\n
-        /// writes do not get copied to time until timehw is written
-        pub const TIMELW = @intToPtr(*volatile u32, base_address + 0x4);
-
-        /// address: 0x40054008
-        /// Read from bits 63:32 of time\n
-        /// always read timelr before timehr
-        pub const TIMEHR = @intToPtr(*volatile u32, base_address + 0x8);
-
-        /// address: 0x4005400c
-        /// Read from bits 31:0 of time
-        pub const TIMELR = @intToPtr(*volatile u32, base_address + 0xc);
-
-        /// address: 0x40054010
-        /// Arm alarm 0, and configure the time it will fire.\n
-        /// Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.\n
-        /// The alarm will disarm itself once it fires, and can\n
-        /// be disarmed early using the ARMED status register.
-        pub const ALARM0 = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x40054014
-        /// Arm alarm 1, and configure the time it will fire.\n
-        /// Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.\n
-        /// The alarm will disarm itself once it fires, and can\n
-        /// be disarmed early using the ARMED status register.
-        pub const ALARM1 = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x40054018
-        /// Arm alarm 2, and configure the time it will fire.\n
-        /// Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.\n
-        /// The alarm will disarm itself once it fires, and can\n
-        /// be disarmed early using the ARMED status register.
-        pub const ALARM2 = @intToPtr(*volatile u32, base_address + 0x18);
-
-        /// address: 0x4005401c
-        /// Arm alarm 3, and configure the time it will fire.\n
-        /// Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.\n
-        /// The alarm will disarm itself once it fires, and can\n
-        /// be disarmed early using the ARMED status register.
-        pub const ALARM3 = @intToPtr(*volatile u32, base_address + 0x1c);
-
-        /// address: 0x40054020
-        /// Indicates the armed/disarmed status of each alarm.\n
-        /// A write to the corresponding ALARMx register arms the alarm.\n
-        /// Alarms automatically disarm upon firing, but writing ones here\n
-        /// will disarm immediately without waiting to fire.
-        pub const ARMED = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x20);
-
-        /// address: 0x40054024
-        /// Raw read from bits 63:32 of time (no side effects)
-        pub const TIMERAWH = @intToPtr(*volatile u32, base_address + 0x24);
-
-        /// address: 0x40054028
-        /// Raw read from bits 31:0 of time (no side effects)
-        pub const TIMERAWL = @intToPtr(*volatile u32, base_address + 0x28);
-
-        /// address: 0x4005402c
-        /// Set bits high to enable pause when the corresponding debug ports are active
-        pub const DBGPAUSE = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            /// Pause when processor 0 is in debug mode
-            DBG0: u1,
-            /// Pause when processor 1 is in debug mode
-            DBG1: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-        }), base_address + 0x2c);
-
-        /// address: 0x40054030
-        /// Set high to pause the timer
-        pub const PAUSE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x30);
-
-        /// address: 0x40054034
-        /// Raw Interrupts
-        pub const INTR = @intToPtr(*volatile Mmio(32, packed struct {
-            ALARM_0: u1,
-            ALARM_1: u1,
-            ALARM_2: u1,
-            ALARM_3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x34);
-
-        /// address: 0x40054038
-        /// Interrupt Enable
-        pub const INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            ALARM_0: u1,
-            ALARM_1: u1,
-            ALARM_2: u1,
-            ALARM_3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x38);
-
-        /// address: 0x4005403c
-        /// Interrupt Force
-        pub const INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            ALARM_0: u1,
-            ALARM_1: u1,
-            ALARM_2: u1,
-            ALARM_3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x3c);
-
-        /// address: 0x40054040
-        /// Interrupt status after masking & forcing
-        pub const INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            ALARM_0: u1,
-            ALARM_1: u1,
-            ALARM_2: u1,
-            ALARM_3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x40);
-    };
-    pub const WATCHDOG = struct {
-        pub const base_address = 0x40058000;
-        pub const version = "1";
-
-        /// address: 0x40058000
-        /// Watchdog control\n
-        /// The rst_wdsel register determines which subsystems are reset when the watchdog
-        /// is triggered.\n
-        /// The watchdog can be triggered in software.
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset
-            /// will be triggered
-            TIME: u24,
-            /// Pause the watchdog timer when JTAG is accessing the bus fabric
-            PAUSE_JTAG: u1,
-            /// Pause the watchdog timer when processor 0 is in debug mode
-            PAUSE_DBG0: u1,
-            /// Pause the watchdog timer when processor 1 is in debug mode
-            PAUSE_DBG1: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            /// When not enabled the watchdog timer is paused
-            ENABLE: u1,
-            /// Trigger a watchdog reset
-            TRIGGER: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x40058004
-        /// Load the watchdog timer. The maximum setting is 0xffffff which corresponds to
-        /// 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).
-        pub const LOAD = @intToPtr(*volatile MmioInt(32, u24), base_address + 0x4);
-
-        /// address: 0x40058008
-        /// Logs the reason for the last reset. Both bits are zero for the case of a
-        /// hardware reset.
-        pub const REASON = @intToPtr(*volatile Mmio(32, packed struct {
-            TIMER: u1,
-            FORCE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x4005800c
-        /// Scratch register. Information persists through soft reset of the chip.
-        pub const SCRATCH0 = @intToPtr(*volatile u32, base_address + 0xc);
-
-        /// address: 0x40058010
-        /// Scratch register. Information persists through soft reset of the chip.
-        pub const SCRATCH1 = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x40058014
-        /// Scratch register. Information persists through soft reset of the chip.
-        pub const SCRATCH2 = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x40058018
-        /// Scratch register. Information persists through soft reset of the chip.
-        pub const SCRATCH3 = @intToPtr(*volatile u32, base_address + 0x18);
-
-        /// address: 0x4005801c
-        /// Scratch register. Information persists through soft reset of the chip.
-        pub const SCRATCH4 = @intToPtr(*volatile u32, base_address + 0x1c);
-
-        /// address: 0x40058020
-        /// Scratch register. Information persists through soft reset of the chip.
-        pub const SCRATCH5 = @intToPtr(*volatile u32, base_address + 0x20);
-
-        /// address: 0x40058024
-        /// Scratch register. Information persists through soft reset of the chip.
-        pub const SCRATCH6 = @intToPtr(*volatile u32, base_address + 0x24);
-
-        /// address: 0x40058028
-        /// Scratch register. Information persists through soft reset of the chip.
-        pub const SCRATCH7 = @intToPtr(*volatile u32, base_address + 0x28);
-
-        /// address: 0x4005802c
-        /// Controls the tick generator
-        pub const TICK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Total number of clk_tick cycles before the next tick.
-            CYCLES: u9,
-            /// start / stop tick generation
-            ENABLE: u1,
-            /// Is the tick generator running?
-            RUNNING: u1,
-            /// Count down timer: the remaining number clk_tick cycles before the next tick is
-            /// generated.
-            COUNT: u9,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-        }), base_address + 0x2c);
-    };
-
-    /// Register block to control RTC
-    pub const RTC = struct {
-        pub const base_address = 0x4005c000;
-        pub const version = "1";
-
-        /// address: 0x4005c000
-        /// Divider minus 1 for the 1 second counter. Safe to change the value when RTC is
-        /// not enabled.
-        pub const CLKDIV_M1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x0);
-
-        /// address: 0x4005c004
-        /// RTC setup register 0
-        pub const SETUP_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Day of the month (1..31)
-            DAY: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            /// Month (1..12)
-            MONTH: u4,
-            /// Year
-            YEAR: u12,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x4005c008
-        /// RTC setup register 1
-        pub const SETUP_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Seconds
-            SEC: u6,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// Minutes
-            MIN: u6,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// Hours
-            HOUR: u5,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            /// Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
-            DOTW: u3,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x4005c00c
-        /// RTC Control and status
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable RTC
-            RTC_ENABLE: u1,
-            /// RTC enabled (running)
-            RTC_ACTIVE: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// Load RTC
-            LOAD: u1,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            /// If set, leapyear is forced off.\n
-            /// Useful for years divisible by 100 but not by 400
-            FORCE_NOTLEAPYEAR: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x4005c010
-        /// Interrupt setup register 0
-        pub const IRQ_SETUP_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Day of the month (1..31)
-            DAY: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            /// Month (1..12)
-            MONTH: u4,
-            /// Year
-            YEAR: u12,
-            /// Enable day matching
-            DAY_ENA: u1,
-            /// Enable month matching
-            MONTH_ENA: u1,
-            /// Enable year matching
-            YEAR_ENA: u1,
-            reserved3: u1 = 0,
-            /// Global match enable. Don't change any other value while this one is enabled
-            MATCH_ENA: u1,
-            MATCH_ACTIVE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-        }), base_address + 0x10);
-
-        /// address: 0x4005c014
-        /// Interrupt setup register 1
-        pub const IRQ_SETUP_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Seconds
-            SEC: u6,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// Minutes
-            MIN: u6,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// Hours
-            HOUR: u5,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            /// Day of the week
-            DOTW: u3,
-            reserved7: u1 = 0,
-            /// Enable second matching
-            SEC_ENA: u1,
-            /// Enable minute matching
-            MIN_ENA: u1,
-            /// Enable hour matching
-            HOUR_ENA: u1,
-            /// Enable day of the week matching
-            DOTW_ENA: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x4005c018
-        /// RTC register 1.
-        pub const RTC_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Day of the month (1..31)
-            DAY: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            /// Month (1..12)
-            MONTH: u4,
-            /// Year
-            YEAR: u12,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x4005c01c
-        /// RTC register 0\n
-        /// Read this before RTC 1!
-        pub const RTC_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Seconds
-            SEC: u6,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// Minutes
-            MIN: u6,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// Hours
-            HOUR: u5,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            /// Day of the week
-            DOTW: u3,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x1c);
-
-        /// address: 0x4005c020
-        /// Raw Interrupts
-        pub const INTR = @intToPtr(*volatile Mmio(32, packed struct {
-            RTC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x20);
-
-        /// address: 0x4005c024
-        /// Interrupt Enable
-        pub const INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            RTC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x24);
-
-        /// address: 0x4005c028
-        /// Interrupt Force
-        pub const INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            RTC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x28);
-
-        /// address: 0x4005c02c
-        /// Interrupt status after masking & forcing
-        pub const INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            RTC: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-            padding30: u1 = 0,
-        }), base_address + 0x2c);
-    };
-    pub const ROSC = struct {
-        pub const base_address = 0x40060000;
-        pub const version = "1";
-
-        /// address: 0x40060000
-        /// Ring Oscillator control
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Controls the number of delay stages in the ROSC ring\n
-            /// LOW uses stages 0 to 7\n
-            /// MEDIUM uses stages 0 to 5\n
-            /// HIGH uses stages 0 to 3\n
-            /// TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds
-            /// design specifications\n
-            /// The clock output will not glitch when changing the range up one step at a time\n
-            /// The clock output will glitch when changing the range down\n
-            /// Note: the values here are gray coded which is why HIGH comes before TOOHIGH
-            FREQ_RANGE: u12,
-            /// On power-up this field is initialised to ENABLE\n
-            /// The system clock must be switched to another source before setting this field to
-            /// DISABLE otherwise the chip will lock up\n
-            /// The 12-bit code is intended to give some protection against accidental writes.
-            /// An invalid setting will enable the oscillator.
-            ENABLE: u12,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40060004
-        /// The FREQA & FREQB registers control the frequency by controlling the drive
-        /// strength of each stage\n
-        /// The drive strength has 4 levels determined by the number of bits set\n
-        /// Increasing the number of bits set increases the drive strength and increases the
-        /// oscillation frequency\n
-        /// 0 bits set is the default drive strength\n
-        /// 1 bit set doubles the drive strength\n
-        /// 2 bits set triples drive strength\n
-        /// 3 bits set quadruples drive strength
-        pub const FREQA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stage 0 drive strength
-            DS0: u3,
-            reserved0: u1 = 0,
-            /// Stage 1 drive strength
-            DS1: u3,
-            reserved1: u1 = 0,
-            /// Stage 2 drive strength
-            DS2: u3,
-            reserved2: u1 = 0,
-            /// Stage 3 drive strength
-            DS3: u3,
-            reserved3: u1 = 0,
-            /// Set to 0x9696 to apply the settings\n
-            /// Any other value in this field will set all drive strengths to 0
-            PASSWD: u16,
-        }), base_address + 0x4);
-
-        /// address: 0x40060008
-        /// For a detailed description see freqa register
-        pub const FREQB = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stage 4 drive strength
-            DS4: u3,
-            reserved0: u1 = 0,
-            /// Stage 5 drive strength
-            DS5: u3,
-            reserved1: u1 = 0,
-            /// Stage 6 drive strength
-            DS6: u3,
-            reserved2: u1 = 0,
-            /// Stage 7 drive strength
-            DS7: u3,
-            reserved3: u1 = 0,
-            /// Set to 0x9696 to apply the settings\n
-            /// Any other value in this field will set all drive strengths to 0
-            PASSWD: u16,
-        }), base_address + 0x8);
-
-        /// address: 0x4006000c
-        /// Ring Oscillator pause control\n
-        /// This is used to save power by pausing the ROSC\n
-        /// On power-up this field is initialised to WAKE\n
-        /// An invalid write will also select WAKE\n
-        /// Warning: setup the irq before selecting dormant mode
-        pub const DORMANT = @intToPtr(*volatile u32, base_address + 0xc);
-
-        /// address: 0x40060010
-        /// Controls the output divider
-        pub const DIV = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x10);
-
-        /// address: 0x40060014
-        /// Controls the phase shifted output
-        pub const PHASE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// phase shift the phase-shifted output by SHIFT input clocks\n
-            /// this can be changed on-the-fly\n
-            /// must be set to 0 before setting div=1
-            SHIFT: u2,
-            /// invert the phase-shifted output\n
-            /// this is ignored when div=1
-            FLIP: u1,
-            /// enable the phase-shifted output\n
-            /// this can be changed on-the-fly
-            ENABLE: u1,
-            /// set to 0xaa\n
-            /// any other value enables the output with shift=0
-            PASSWD: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x40060018
-        /// Ring Oscillator Status
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            /// Oscillator is enabled but not necessarily running and stable\n
-            /// this resets to 0 but transitions to 1 during chip startup
-            ENABLED: u1,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            /// post-divider is running\n
-            /// this resets to 0 but transitions to 1 during chip startup
-            DIV_RUNNING: u1,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            reserved18: u1 = 0,
-            reserved19: u1 = 0,
-            reserved20: u1 = 0,
-            reserved21: u1 = 0,
-            /// An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or
-            /// FREQB or DIV or PHASE or DORMANT
-            BADWRITE: u1,
-            reserved22: u1 = 0,
-            reserved23: u1 = 0,
-            reserved24: u1 = 0,
-            reserved25: u1 = 0,
-            reserved26: u1 = 0,
-            reserved27: u1 = 0,
-            /// Oscillator is running and stable
-            STABLE: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x4006001c
-        /// This just reads the state of the oscillator output so randomness is compromised
-        /// if the ring oscillator is stopped or run at a harmonic of the bus frequency
-        pub const RANDOMBIT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x1c);
-
-        /// address: 0x40060020
-        /// A down counter running at the ROSC frequency which counts to zero and stops.\n
-        /// To start the counter write a non-zero value.\n
-        /// Can be used for short software pauses when setting up time sensitive hardware.
-        pub const COUNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x20);
-    };
-
-    /// control and status for on-chip voltage regulator and chip level reset subsystem
-    pub const VREG_AND_CHIP_RESET = struct {
-        pub const base_address = 0x40064000;
-        pub const version = "1";
-
-        /// address: 0x40064000
-        /// Voltage regulator control and status
-        pub const VREG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// enable\n
-            /// 0=not enabled, 1=enabled
-            EN: u1,
-            /// high impedance mode select\n
-            /// 0=not in high impedance mode, 1=in high impedance mode
-            HIZ: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// output voltage select\n
-            /// 0000 to 0101 - 0.80V\n
-            /// 0110 - 0.85V\n
-            /// 0111 - 0.90V\n
-            /// 1000 - 0.95V\n
-            /// 1001 - 1.00V\n
-            /// 1010 - 1.05V\n
-            /// 1011 - 1.10V (default)\n
-            /// 1100 - 1.15V\n
-            /// 1101 - 1.20V\n
-            /// 1110 - 1.25V\n
-            /// 1111 - 1.30V
-            VSEL: u4,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            /// regulation status\n
-            /// 0=not in regulation, 1=in regulation
-            ROK: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x40064004
-        /// brown-out detection control
-        pub const BOD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// enable\n
-            /// 0=not enabled, 1=enabled
-            EN: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            /// threshold select\n
-            /// 0000 - 0.473V\n
-            /// 0001 - 0.516V\n
-            /// 0010 - 0.559V\n
-            /// 0011 - 0.602V\n
-            /// 0100 - 0.645V\n
-            /// 0101 - 0.688V\n
-            /// 0110 - 0.731V\n
-            /// 0111 - 0.774V\n
-            /// 1000 - 0.817V\n
-            /// 1001 - 0.860V (default)\n
-            /// 1010 - 0.903V\n
-            /// 1011 - 0.946V\n
-            /// 1100 - 0.989V\n
-            /// 1101 - 1.032V\n
-            /// 1110 - 1.075V\n
-            /// 1111 - 1.118V
-            VSEL: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x40064008
-        /// Chip reset control and status
-        pub const CHIP_RESET = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Last reset was from the power-on reset or brown-out detection blocks
-            HAD_POR: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            /// Last reset was from the RUN pin
-            HAD_RUN: u1,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            /// Last reset was from the debug port
-            HAD_PSM_RESTART: u1,
-            reserved18: u1 = 0,
-            reserved19: u1 = 0,
-            reserved20: u1 = 0,
-            /// This is set by psm_restart from the debugger.\n
-            /// Its purpose is to branch bootcode to a safe mode when the debugger has issued a
-            /// psm_restart in order to recover from a boot lock-up.\n
-            /// In the safe mode the debugger can repair the boot code, clear this flag then
-            /// reboot the processor.
-            PSM_RESTART_FLAG: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-        }), base_address + 0x8);
-    };
-
-    /// Testbench manager. Allows the programmer to know what platform their software is
-    /// running on.
-    pub const TBMAN = struct {
-        pub const base_address = 0x4006c000;
-        pub const version = "1";
-
-        /// address: 0x4006c000
-        /// Indicates the type of platform in use
-        pub const PLATFORM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Indicates the platform is an ASIC
-            ASIC: u1,
-            /// Indicates the platform is an FPGA
-            FPGA: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x0);
-    };
-
-    /// DMA with separate read and write masters
-    pub const DMA = struct {
-        pub const base_address = 0x50000000;
-        pub const version = "1";
-
-        /// address: 0x50000000
-        /// DMA Channel 0 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH0_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x0);
-
-        /// address: 0x50000004
-        /// DMA Channel 0 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH0_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x4);
-
-        /// address: 0x50000008
-        /// DMA Channel 0 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH0_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x8);
-
-        /// address: 0x5000000c
-        /// DMA Channel 0 Control and Status
-        pub const CH0_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (0).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x50000010
-        /// Alias for channel 0 CTRL register
-        pub const CH0_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x50000014
-        /// Alias for channel 0 READ_ADDR register
-        pub const CH0_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x50000018
-        /// Alias for channel 0 WRITE_ADDR register
-        pub const CH0_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x18);
-
-        /// address: 0x5000001c
-        /// Alias for channel 0 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH0_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x1c);
-
-        /// address: 0x50000020
-        /// Alias for channel 0 CTRL register
-        pub const CH0_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x20);
-
-        /// address: 0x50000024
-        /// Alias for channel 0 TRANS_COUNT register
-        pub const CH0_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x24);
-
-        /// address: 0x50000028
-        /// Alias for channel 0 READ_ADDR register
-        pub const CH0_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x28);
-
-        /// address: 0x5000002c
-        /// Alias for channel 0 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH0_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x50000030
-        /// Alias for channel 0 CTRL register
-        pub const CH0_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x30);
-
-        /// address: 0x50000034
-        /// Alias for channel 0 WRITE_ADDR register
-        pub const CH0_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x34);
-
-        /// address: 0x50000038
-        /// Alias for channel 0 TRANS_COUNT register
-        pub const CH0_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x38);
-
-        /// address: 0x5000003c
-        /// Alias for channel 0 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH0_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x3c);
-
-        /// address: 0x50000040
-        /// DMA Channel 1 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x40);
-
-        /// address: 0x50000044
-        /// DMA Channel 1 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x44);
-
-        /// address: 0x50000048
-        /// DMA Channel 1 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH1_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x48);
-
-        /// address: 0x5000004c
-        /// DMA Channel 1 Control and Status
-        pub const CH1_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (1).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x50000050
-        /// Alias for channel 1 CTRL register
-        pub const CH1_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x50);
-
-        /// address: 0x50000054
-        /// Alias for channel 1 READ_ADDR register
-        pub const CH1_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x54);
-
-        /// address: 0x50000058
-        /// Alias for channel 1 WRITE_ADDR register
-        pub const CH1_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x58);
-
-        /// address: 0x5000005c
-        /// Alias for channel 1 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH1_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x5c);
-
-        /// address: 0x50000060
-        /// Alias for channel 1 CTRL register
-        pub const CH1_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x60);
-
-        /// address: 0x50000064
-        /// Alias for channel 1 TRANS_COUNT register
-        pub const CH1_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x64);
-
-        /// address: 0x50000068
-        /// Alias for channel 1 READ_ADDR register
-        pub const CH1_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x68);
-
-        /// address: 0x5000006c
-        /// Alias for channel 1 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH1_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x6c);
-
-        /// address: 0x50000070
-        /// Alias for channel 1 CTRL register
-        pub const CH1_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x70);
-
-        /// address: 0x50000074
-        /// Alias for channel 1 WRITE_ADDR register
-        pub const CH1_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x74);
-
-        /// address: 0x50000078
-        /// Alias for channel 1 TRANS_COUNT register
-        pub const CH1_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x78);
-
-        /// address: 0x5000007c
-        /// Alias for channel 1 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH1_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x7c);
-
-        /// address: 0x50000080
-        /// DMA Channel 2 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x80);
-
-        /// address: 0x50000084
-        /// DMA Channel 2 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH2_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x84);
-
-        /// address: 0x50000088
-        /// DMA Channel 2 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x88);
-
-        /// address: 0x5000008c
-        /// DMA Channel 2 Control and Status
-        pub const CH2_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (2).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x50000090
-        /// Alias for channel 2 CTRL register
-        pub const CH2_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x90);
-
-        /// address: 0x50000094
-        /// Alias for channel 2 READ_ADDR register
-        pub const CH2_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x94);
-
-        /// address: 0x50000098
-        /// Alias for channel 2 WRITE_ADDR register
-        pub const CH2_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x98);
-
-        /// address: 0x5000009c
-        /// Alias for channel 2 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH2_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x9c);
-
-        /// address: 0x500000a0
-        /// Alias for channel 2 CTRL register
-        pub const CH2_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0xa0);
-
-        /// address: 0x500000a4
-        /// Alias for channel 2 TRANS_COUNT register
-        pub const CH2_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0xa4);
-
-        /// address: 0x500000a8
-        /// Alias for channel 2 READ_ADDR register
-        pub const CH2_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0xa8);
-
-        /// address: 0x500000ac
-        /// Alias for channel 2 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH2_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0xac);
-
-        /// address: 0x500000b0
-        /// Alias for channel 2 CTRL register
-        pub const CH2_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0xb0);
-
-        /// address: 0x500000b4
-        /// Alias for channel 2 WRITE_ADDR register
-        pub const CH2_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0xb4);
-
-        /// address: 0x500000b8
-        /// Alias for channel 2 TRANS_COUNT register
-        pub const CH2_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0xb8);
-
-        /// address: 0x500000bc
-        /// Alias for channel 2 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH2_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0xbc);
-
-        /// address: 0x500000c0
-        /// DMA Channel 3 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH3_READ_ADDR = @intToPtr(*volatile u32, base_address + 0xc0);
-
-        /// address: 0x500000c4
-        /// DMA Channel 3 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0xc4);
-
-        /// address: 0x500000c8
-        /// DMA Channel 3 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0xc8);
-
-        /// address: 0x500000cc
-        /// DMA Channel 3 Control and Status
-        pub const CH3_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (3).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x500000d0
-        /// Alias for channel 3 CTRL register
-        pub const CH3_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0xd0);
-
-        /// address: 0x500000d4
-        /// Alias for channel 3 READ_ADDR register
-        pub const CH3_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0xd4);
-
-        /// address: 0x500000d8
-        /// Alias for channel 3 WRITE_ADDR register
-        pub const CH3_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0xd8);
-
-        /// address: 0x500000dc
-        /// Alias for channel 3 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH3_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0xdc);
-
-        /// address: 0x500000e0
-        /// Alias for channel 3 CTRL register
-        pub const CH3_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0xe0);
-
-        /// address: 0x500000e4
-        /// Alias for channel 3 TRANS_COUNT register
-        pub const CH3_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0xe4);
-
-        /// address: 0x500000e8
-        /// Alias for channel 3 READ_ADDR register
-        pub const CH3_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0xe8);
-
-        /// address: 0x500000ec
-        /// Alias for channel 3 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH3_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0xec);
-
-        /// address: 0x500000f0
-        /// Alias for channel 3 CTRL register
-        pub const CH3_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0xf0);
-
-        /// address: 0x500000f4
-        /// Alias for channel 3 WRITE_ADDR register
-        pub const CH3_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0xf4);
-
-        /// address: 0x500000f8
-        /// Alias for channel 3 TRANS_COUNT register
-        pub const CH3_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0xf8);
-
-        /// address: 0x500000fc
-        /// Alias for channel 3 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH3_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0xfc);
-
-        /// address: 0x50000100
-        /// DMA Channel 4 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH4_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x100);
-
-        /// address: 0x50000104
-        /// DMA Channel 4 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH4_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x104);
-
-        /// address: 0x50000108
-        /// DMA Channel 4 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH4_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x108);
-
-        /// address: 0x5000010c
-        /// DMA Channel 4 Control and Status
-        pub const CH4_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (4).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0x10c);
-
-        /// address: 0x50000110
-        /// Alias for channel 4 CTRL register
-        pub const CH4_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x110);
-
-        /// address: 0x50000114
-        /// Alias for channel 4 READ_ADDR register
-        pub const CH4_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x114);
-
-        /// address: 0x50000118
-        /// Alias for channel 4 WRITE_ADDR register
-        pub const CH4_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x118);
-
-        /// address: 0x5000011c
-        /// Alias for channel 4 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH4_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x11c);
-
-        /// address: 0x50000120
-        /// Alias for channel 4 CTRL register
-        pub const CH4_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x120);
-
-        /// address: 0x50000124
-        /// Alias for channel 4 TRANS_COUNT register
-        pub const CH4_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x124);
-
-        /// address: 0x50000128
-        /// Alias for channel 4 READ_ADDR register
-        pub const CH4_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x128);
-
-        /// address: 0x5000012c
-        /// Alias for channel 4 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH4_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x12c);
-
-        /// address: 0x50000130
-        /// Alias for channel 4 CTRL register
-        pub const CH4_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x130);
-
-        /// address: 0x50000134
-        /// Alias for channel 4 WRITE_ADDR register
-        pub const CH4_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x134);
-
-        /// address: 0x50000138
-        /// Alias for channel 4 TRANS_COUNT register
-        pub const CH4_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x138);
-
-        /// address: 0x5000013c
-        /// Alias for channel 4 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH4_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x13c);
-
-        /// address: 0x50000140
-        /// DMA Channel 5 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH5_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x140);
-
-        /// address: 0x50000144
-        /// DMA Channel 5 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH5_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x144);
-
-        /// address: 0x50000148
-        /// DMA Channel 5 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH5_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x148);
-
-        /// address: 0x5000014c
-        /// DMA Channel 5 Control and Status
-        pub const CH5_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (5).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0x14c);
-
-        /// address: 0x50000150
-        /// Alias for channel 5 CTRL register
-        pub const CH5_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x150);
-
-        /// address: 0x50000154
-        /// Alias for channel 5 READ_ADDR register
-        pub const CH5_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x154);
-
-        /// address: 0x50000158
-        /// Alias for channel 5 WRITE_ADDR register
-        pub const CH5_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x158);
-
-        /// address: 0x5000015c
-        /// Alias for channel 5 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH5_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x15c);
-
-        /// address: 0x50000160
-        /// Alias for channel 5 CTRL register
-        pub const CH5_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x160);
-
-        /// address: 0x50000164
-        /// Alias for channel 5 TRANS_COUNT register
-        pub const CH5_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x164);
-
-        /// address: 0x50000168
-        /// Alias for channel 5 READ_ADDR register
-        pub const CH5_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x168);
-
-        /// address: 0x5000016c
-        /// Alias for channel 5 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH5_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x16c);
-
-        /// address: 0x50000170
-        /// Alias for channel 5 CTRL register
-        pub const CH5_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x170);
-
-        /// address: 0x50000174
-        /// Alias for channel 5 WRITE_ADDR register
-        pub const CH5_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x174);
-
-        /// address: 0x50000178
-        /// Alias for channel 5 TRANS_COUNT register
-        pub const CH5_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x178);
-
-        /// address: 0x5000017c
-        /// Alias for channel 5 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH5_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x17c);
-
-        /// address: 0x50000180
-        /// DMA Channel 6 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH6_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x180);
-
-        /// address: 0x50000184
-        /// DMA Channel 6 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH6_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x184);
-
-        /// address: 0x50000188
-        /// DMA Channel 6 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH6_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x188);
-
-        /// address: 0x5000018c
-        /// DMA Channel 6 Control and Status
-        pub const CH6_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (6).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0x18c);
-
-        /// address: 0x50000190
-        /// Alias for channel 6 CTRL register
-        pub const CH6_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x190);
-
-        /// address: 0x50000194
-        /// Alias for channel 6 READ_ADDR register
-        pub const CH6_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x194);
-
-        /// address: 0x50000198
-        /// Alias for channel 6 WRITE_ADDR register
-        pub const CH6_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x198);
-
-        /// address: 0x5000019c
-        /// Alias for channel 6 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH6_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x19c);
-
-        /// address: 0x500001a0
-        /// Alias for channel 6 CTRL register
-        pub const CH6_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x1a0);
-
-        /// address: 0x500001a4
-        /// Alias for channel 6 TRANS_COUNT register
-        pub const CH6_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x1a4);
-
-        /// address: 0x500001a8
-        /// Alias for channel 6 READ_ADDR register
-        pub const CH6_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x1a8);
-
-        /// address: 0x500001ac
-        /// Alias for channel 6 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH6_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x1ac);
-
-        /// address: 0x500001b0
-        /// Alias for channel 6 CTRL register
-        pub const CH6_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x1b0);
-
-        /// address: 0x500001b4
-        /// Alias for channel 6 WRITE_ADDR register
-        pub const CH6_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x1b4);
-
-        /// address: 0x500001b8
-        /// Alias for channel 6 TRANS_COUNT register
-        pub const CH6_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x1b8);
-
-        /// address: 0x500001bc
-        /// Alias for channel 6 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH6_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x1bc);
-
-        /// address: 0x500001c0
-        /// DMA Channel 7 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH7_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x1c0);
-
-        /// address: 0x500001c4
-        /// DMA Channel 7 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH7_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x1c4);
-
-        /// address: 0x500001c8
-        /// DMA Channel 7 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH7_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x1c8);
-
-        /// address: 0x500001cc
-        /// DMA Channel 7 Control and Status
-        pub const CH7_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (7).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0x1cc);
-
-        /// address: 0x500001d0
-        /// Alias for channel 7 CTRL register
-        pub const CH7_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x1d0);
-
-        /// address: 0x500001d4
-        /// Alias for channel 7 READ_ADDR register
-        pub const CH7_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x1d4);
-
-        /// address: 0x500001d8
-        /// Alias for channel 7 WRITE_ADDR register
-        pub const CH7_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x1d8);
-
-        /// address: 0x500001dc
-        /// Alias for channel 7 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH7_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x1dc);
-
-        /// address: 0x500001e0
-        /// Alias for channel 7 CTRL register
-        pub const CH7_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x1e0);
-
-        /// address: 0x500001e4
-        /// Alias for channel 7 TRANS_COUNT register
-        pub const CH7_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x1e4);
-
-        /// address: 0x500001e8
-        /// Alias for channel 7 READ_ADDR register
-        pub const CH7_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x1e8);
-
-        /// address: 0x500001ec
-        /// Alias for channel 7 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH7_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x1ec);
-
-        /// address: 0x500001f0
-        /// Alias for channel 7 CTRL register
-        pub const CH7_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x1f0);
-
-        /// address: 0x500001f4
-        /// Alias for channel 7 WRITE_ADDR register
-        pub const CH7_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x1f4);
-
-        /// address: 0x500001f8
-        /// Alias for channel 7 TRANS_COUNT register
-        pub const CH7_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x1f8);
-
-        /// address: 0x500001fc
-        /// Alias for channel 7 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH7_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x1fc);
-
-        /// address: 0x50000200
-        /// DMA Channel 8 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH8_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x200);
-
-        /// address: 0x50000204
-        /// DMA Channel 8 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH8_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x204);
-
-        /// address: 0x50000208
-        /// DMA Channel 8 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH8_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x208);
-
-        /// address: 0x5000020c
-        /// DMA Channel 8 Control and Status
-        pub const CH8_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (8).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0x20c);
-
-        /// address: 0x50000210
-        /// Alias for channel 8 CTRL register
-        pub const CH8_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x210);
-
-        /// address: 0x50000214
-        /// Alias for channel 8 READ_ADDR register
-        pub const CH8_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x214);
-
-        /// address: 0x50000218
-        /// Alias for channel 8 WRITE_ADDR register
-        pub const CH8_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x218);
-
-        /// address: 0x5000021c
-        /// Alias for channel 8 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH8_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x21c);
-
-        /// address: 0x50000220
-        /// Alias for channel 8 CTRL register
-        pub const CH8_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x220);
-
-        /// address: 0x50000224
-        /// Alias for channel 8 TRANS_COUNT register
-        pub const CH8_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x224);
-
-        /// address: 0x50000228
-        /// Alias for channel 8 READ_ADDR register
-        pub const CH8_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x228);
-
-        /// address: 0x5000022c
-        /// Alias for channel 8 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH8_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x22c);
-
-        /// address: 0x50000230
-        /// Alias for channel 8 CTRL register
-        pub const CH8_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x230);
-
-        /// address: 0x50000234
-        /// Alias for channel 8 WRITE_ADDR register
-        pub const CH8_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x234);
-
-        /// address: 0x50000238
-        /// Alias for channel 8 TRANS_COUNT register
-        pub const CH8_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x238);
-
-        /// address: 0x5000023c
-        /// Alias for channel 8 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH8_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x23c);
-
-        /// address: 0x50000240
-        /// DMA Channel 9 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH9_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x240);
-
-        /// address: 0x50000244
-        /// DMA Channel 9 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH9_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x244);
-
-        /// address: 0x50000248
-        /// DMA Channel 9 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH9_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x248);
-
-        /// address: 0x5000024c
-        /// DMA Channel 9 Control and Status
-        pub const CH9_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (9).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0x24c);
-
-        /// address: 0x50000250
-        /// Alias for channel 9 CTRL register
-        pub const CH9_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x250);
-
-        /// address: 0x50000254
-        /// Alias for channel 9 READ_ADDR register
-        pub const CH9_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x254);
-
-        /// address: 0x50000258
-        /// Alias for channel 9 WRITE_ADDR register
-        pub const CH9_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x258);
-
-        /// address: 0x5000025c
-        /// Alias for channel 9 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH9_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x25c);
-
-        /// address: 0x50000260
-        /// Alias for channel 9 CTRL register
-        pub const CH9_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x260);
-
-        /// address: 0x50000264
-        /// Alias for channel 9 TRANS_COUNT register
-        pub const CH9_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x264);
-
-        /// address: 0x50000268
-        /// Alias for channel 9 READ_ADDR register
-        pub const CH9_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x268);
-
-        /// address: 0x5000026c
-        /// Alias for channel 9 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH9_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x26c);
-
-        /// address: 0x50000270
-        /// Alias for channel 9 CTRL register
-        pub const CH9_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x270);
-
-        /// address: 0x50000274
-        /// Alias for channel 9 WRITE_ADDR register
-        pub const CH9_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x274);
-
-        /// address: 0x50000278
-        /// Alias for channel 9 TRANS_COUNT register
-        pub const CH9_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x278);
-
-        /// address: 0x5000027c
-        /// Alias for channel 9 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH9_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x27c);
-
-        /// address: 0x50000280
-        /// DMA Channel 10 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH10_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x280);
-
-        /// address: 0x50000284
-        /// DMA Channel 10 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH10_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x284);
-
-        /// address: 0x50000288
-        /// DMA Channel 10 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH10_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x288);
-
-        /// address: 0x5000028c
-        /// DMA Channel 10 Control and Status
-        pub const CH10_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (10).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0x28c);
-
-        /// address: 0x50000290
-        /// Alias for channel 10 CTRL register
-        pub const CH10_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x290);
-
-        /// address: 0x50000294
-        /// Alias for channel 10 READ_ADDR register
-        pub const CH10_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x294);
-
-        /// address: 0x50000298
-        /// Alias for channel 10 WRITE_ADDR register
-        pub const CH10_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x298);
-
-        /// address: 0x5000029c
-        /// Alias for channel 10 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH10_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x29c);
-
-        /// address: 0x500002a0
-        /// Alias for channel 10 CTRL register
-        pub const CH10_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x2a0);
-
-        /// address: 0x500002a4
-        /// Alias for channel 10 TRANS_COUNT register
-        pub const CH10_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x2a4);
-
-        /// address: 0x500002a8
-        /// Alias for channel 10 READ_ADDR register
-        pub const CH10_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x2a8);
-
-        /// address: 0x500002ac
-        /// Alias for channel 10 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH10_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x2ac);
-
-        /// address: 0x500002b0
-        /// Alias for channel 10 CTRL register
-        pub const CH10_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x2b0);
-
-        /// address: 0x500002b4
-        /// Alias for channel 10 WRITE_ADDR register
-        pub const CH10_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x2b4);
-
-        /// address: 0x500002b8
-        /// Alias for channel 10 TRANS_COUNT register
-        pub const CH10_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x2b8);
-
-        /// address: 0x500002bc
-        /// Alias for channel 10 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH10_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x2bc);
-
-        /// address: 0x500002c0
-        /// DMA Channel 11 Read Address pointer\n
-        /// This register updates automatically each time a read completes. The current
-        /// value is the next address to be read by this channel.
-        pub const CH11_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x2c0);
-
-        /// address: 0x500002c4
-        /// DMA Channel 11 Write Address pointer\n
-        /// This register updates automatically each time a write completes. The current
-        /// value is the next address to be written by this channel.
-        pub const CH11_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x2c4);
-
-        /// address: 0x500002c8
-        /// DMA Channel 11 Transfer Count\n
-        /// Program the number of bus transfers a channel will perform before halting. Note
-        /// that, if transfers are larger than one byte in size, this is not equal to the
-        /// number of bytes transferred (see CTRL_DATA_SIZE).\n\n
-        /// When the channel is active, reading this register shows the number of transfers
-        /// remaining, updating automatically each time a write transfer completes.\n\n
-        /// Writing this register sets the RELOAD value for the transfer counter. Each time
-        /// this channel is triggered, the RELOAD value is copied into the live transfer
-        /// counter. The channel can be started multiple times, and will perform the same
-        /// number of transfers each time, as programmed by most recent write.\n\n
-        /// The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a
-        /// trigger, the written value is used immediately as the length of the new transfer
-        /// sequence, as well as being written to RELOAD.
-        pub const CH11_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x2c8);
-
-        /// address: 0x500002cc
-        /// DMA Channel 11 Control and Status
-        pub const CH11_CTRL_TRIG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// DMA Channel Enable.\n
-            /// When 1, the channel will respond to triggering events, which will cause it to
-            /// become BUSY and start transferring data. When 0, the channel will ignore
-            /// triggers, stop issuing transfers, and pause the current transfer sequence (i.e.
-            /// BUSY will remain high if already high)
-            EN: u1,
-            /// HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in
-            /// each scheduling round, all high priority channels are considered first, and then
-            /// only a single low priority channel, before returning to the high priority
-            /// channels.\n\n
-            /// This only affects the order in which the DMA schedules channels. The DMA's bus
-            /// priority is not changed. If the DMA is not saturated then a low priority channel
-            /// will see no loss of throughput.
-            HIGH_PRIORITY: u1,
-            /// Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR
-            /// advance by this amount (1/2/4 bytes) with each transfer.
-            DATA_SIZE: u2,
-            /// If 1, the read address increments with each transfer. If 0, each read is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for peripheral-to-memory transfers.
-            INCR_READ: u1,
-            /// If 1, the write address increments with each transfer. If 0, each write is
-            /// directed to the same, initial address.\n\n
-            /// Generally this should be disabled for memory-to-peripheral transfers.
-            INCR_WRITE: u1,
-            /// Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower
-            /// n bits of the address will change. This wraps the address on a (1 << n) byte
-            /// boundary, facilitating access to naturally-aligned ring buffers.\n\n
-            /// Ring sizes between 2 and 32768 bytes are possible. This can apply to either read
-            /// or write addresses, based on value of RING_SEL.
-            RING_SIZE: u4,
-            /// Select whether RING_SIZE applies to read or write addresses.\n
-            /// If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write
-            /// addresses are wrapped.
-            RING_SEL: u1,
-            /// When this channel completes, it will trigger the channel indicated by CHAIN_TO.
-            /// Disable by setting CHAIN_TO = _(this channel)_.\n
-            /// Reset value is equal to channel number (11).
-            CHAIN_TO: u4,
-            /// Select a Transfer Request signal.\n
-            /// The channel uses the transfer request signal to pace its data transfer rate.
-            /// Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request
-            /// from the system).\n
-            /// 0x0 to 0x3a -> select DREQ n as TREQ
-            TREQ_SEL: u6,
-            /// In QUIET mode, the channel does not generate IRQs at the end of every transfer
-            /// block. Instead, an IRQ is raised when NULL is written to a trigger register,
-            /// indicating the end of a control block chain.\n\n
-            /// This reduces the number of interrupts to be serviced by the CPU when
-            /// transferring a DMA chain of many small control blocks.
-            IRQ_QUIET: u1,
-            /// Apply byte-swap transformation to DMA data.\n
-            /// For byte data, this has no effect. For halfword data, the two bytes of each
-            /// halfword are swapped. For word data, the four bytes of each word are swapped to
-            /// reverse order.
-            BSWAP: u1,
-            /// If 1, this channel's data transfers are visible to the sniff hardware, and each
-            /// transfer will advance the state of the checksum. This only applies if the sniff
-            /// hardware is enabled, and has this channel selected.\n\n
-            /// This allows checksum to be enabled or disabled on a per-control- block basis.
-            SNIFF_EN: u1,
-            /// This flag goes high when the channel starts a new transfer sequence, and low
-            /// when the last transfer of that sequence completes. Clearing EN while BUSY is
-            /// high pauses the channel, and BUSY will stay high while paused.\n\n
-            /// To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-            BUSY: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// If 1, the channel received a write bus error. Write one to clear.\n
-            /// WRITE_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 5 transfers later)
-            WRITE_ERROR: u1,
-            /// If 1, the channel received a read bus error. Write one to clear.\n
-            /// READ_ADDR shows the approximate address where the bus error was encountered
-            /// (will not to be earlier, or more than 3 transfers later)
-            READ_ERROR: u1,
-            /// Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it
-            /// encounters any bus error, and always raises its channel IRQ flag.
-            AHB_ERROR: u1,
-        }), base_address + 0x2cc);
-
-        /// address: 0x500002d0
-        /// Alias for channel 11 CTRL register
-        pub const CH11_AL1_CTRL = @intToPtr(*volatile u32, base_address + 0x2d0);
-
-        /// address: 0x500002d4
-        /// Alias for channel 11 READ_ADDR register
-        pub const CH11_AL1_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x2d4);
-
-        /// address: 0x500002d8
-        /// Alias for channel 11 WRITE_ADDR register
-        pub const CH11_AL1_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x2d8);
-
-        /// address: 0x500002dc
-        /// Alias for channel 11 TRANS_COUNT register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH11_AL1_TRANS_COUNT_TRIG = @intToPtr(*volatile u32, base_address + 0x2dc);
-
-        /// address: 0x500002e0
-        /// Alias for channel 11 CTRL register
-        pub const CH11_AL2_CTRL = @intToPtr(*volatile u32, base_address + 0x2e0);
-
-        /// address: 0x500002e4
-        /// Alias for channel 11 TRANS_COUNT register
-        pub const CH11_AL2_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x2e4);
-
-        /// address: 0x500002e8
-        /// Alias for channel 11 READ_ADDR register
-        pub const CH11_AL2_READ_ADDR = @intToPtr(*volatile u32, base_address + 0x2e8);
-
-        /// address: 0x500002ec
-        /// Alias for channel 11 WRITE_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH11_AL2_WRITE_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x2ec);
-
-        /// address: 0x500002f0
-        /// Alias for channel 11 CTRL register
-        pub const CH11_AL3_CTRL = @intToPtr(*volatile u32, base_address + 0x2f0);
-
-        /// address: 0x500002f4
-        /// Alias for channel 11 WRITE_ADDR register
-        pub const CH11_AL3_WRITE_ADDR = @intToPtr(*volatile u32, base_address + 0x2f4);
-
-        /// address: 0x500002f8
-        /// Alias for channel 11 TRANS_COUNT register
-        pub const CH11_AL3_TRANS_COUNT = @intToPtr(*volatile u32, base_address + 0x2f8);
-
-        /// address: 0x500002fc
-        /// Alias for channel 11 READ_ADDR register\n
-        /// This is a trigger register (0xc). Writing a nonzero value will\n
-        /// reload the channel counter and start the channel.
-        pub const CH11_AL3_READ_ADDR_TRIG = @intToPtr(*volatile u32, base_address + 0x2fc);
-
-        /// address: 0x50000400
-        /// Interrupt Status (raw)
-        pub const INTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x400);
-
-        /// address: 0x50000404
-        /// Interrupt Enables for IRQ 0
-        pub const INTE0 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x404);
-
-        /// address: 0x50000408
-        /// Force Interrupts
-        pub const INTF0 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x408);
-
-        /// address: 0x5000040c
-        /// Interrupt Status for IRQ 0
-        pub const INTS0 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x40c);
-
-        /// address: 0x50000414
-        /// Interrupt Enables for IRQ 1
-        pub const INTE1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x414);
-
-        /// address: 0x50000418
-        /// Force Interrupts for IRQ 1
-        pub const INTF1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x418);
-
-        /// address: 0x5000041c
-        /// Interrupt Status (masked) for IRQ 1
-        pub const INTS1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x41c);
-
-        /// address: 0x50000420
-        /// Pacing (X/Y) Fractional Timer\n
-        /// The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk).
-        /// This equation is evaluated every sys_clk cycles and therefore can only generate
-        /// TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
-        pub const TIMER0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
-            Y: u16,
-            /// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
-            X: u16,
-        }), base_address + 0x420);
-
-        /// address: 0x50000424
-        /// Pacing (X/Y) Fractional Timer\n
-        /// The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk).
-        /// This equation is evaluated every sys_clk cycles and therefore can only generate
-        /// TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
-        pub const TIMER1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
-            Y: u16,
-            /// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
-            X: u16,
-        }), base_address + 0x424);
-
-        /// address: 0x50000428
-        /// Pacing (X/Y) Fractional Timer\n
-        /// The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk).
-        /// This equation is evaluated every sys_clk cycles and therefore can only generate
-        /// TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
-        pub const TIMER2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
-            Y: u16,
-            /// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
-            X: u16,
-        }), base_address + 0x428);
-
-        /// address: 0x5000042c
-        /// Pacing (X/Y) Fractional Timer\n
-        /// The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk).
-        /// This equation is evaluated every sys_clk cycles and therefore can only generate
-        /// TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
-        pub const TIMER3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
-            Y: u16,
-            /// Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
-            X: u16,
-        }), base_address + 0x42c);
-
-        /// address: 0x50000430
-        /// Trigger one or more channels simultaneously
-        pub const MULTI_CHAN_TRIGGER = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x430);
-
-        /// address: 0x50000434
-        /// Sniffer Control
-        pub const SNIFF_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable sniffer
-            EN: u1,
-            /// DMA channel for Sniffer to observe
-            DMACH: u4,
-            CALC: u4,
-            /// Locally perform a byte reverse on the sniffed data, before feeding into
-            /// checksum.\n\n
-            /// Note that the sniff hardware is downstream of the DMA channel byteswap performed
-            /// in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled,
-            /// their effects cancel from the sniffer's point of view.
-            BSWAP: u1,
-            /// If set, the result appears bit-reversed when read. This does not affect the way
-            /// the checksum is calculated; the result is transformed on-the-fly between the
-            /// result register and the bus.
-            OUT_REV: u1,
-            /// If set, the result appears inverted (bitwise complement) when read. This does
-            /// not affect the way the checksum is calculated; the result is transformed
-            /// on-the-fly between the result register and the bus.
-            OUT_INV: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x434);
-
-        /// address: 0x50000438
-        /// Data accumulator for sniff hardware\n
-        /// Write an initial seed value here before starting a DMA transfer on the channel
-        /// indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time
-        /// it observes a read from the indicated channel. Once the channel completes, the
-        /// final result can be read from this register.
-        pub const SNIFF_DATA = @intToPtr(*volatile u32, base_address + 0x438);
-
-        /// address: 0x50000440
-        /// Debug RAF, WAF, TDF levels
-        pub const FIFO_LEVELS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Current Transfer-Data-FIFO fill level
-            TDF_LVL: u8,
-            /// Current Write-Address-FIFO fill level
-            WAF_LVL: u8,
-            /// Current Read-Address-FIFO fill level
-            RAF_LVL: u8,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-        }), base_address + 0x440);
-
-        /// address: 0x50000444
-        /// Abort an in-progress transfer sequence on one or more channels
-        pub const CHAN_ABORT = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x444);
-
-        /// address: 0x50000448
-        /// The number of channels this DMA instance is equipped with. This DMA supports up
-        /// to 16 hardware channels, but can be configured with as few as one, to minimise
-        /// silicon area.
-        pub const N_CHANNELS = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x448);
-
-        /// address: 0x50000800
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH0_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x800);
-
-        /// address: 0x50000804
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH0_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x804);
-
-        /// address: 0x50000840
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH1_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x840);
-
-        /// address: 0x50000844
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH1_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x844);
-
-        /// address: 0x50000880
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH2_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x880);
-
-        /// address: 0x50000884
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH2_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x884);
-
-        /// address: 0x500008c0
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH3_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x8c0);
-
-        /// address: 0x500008c4
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH3_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x8c4);
-
-        /// address: 0x50000900
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH4_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x900);
-
-        /// address: 0x50000904
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH4_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x904);
-
-        /// address: 0x50000940
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH5_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x940);
-
-        /// address: 0x50000944
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH5_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x944);
-
-        /// address: 0x50000980
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH6_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x980);
-
-        /// address: 0x50000984
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH6_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x984);
-
-        /// address: 0x500009c0
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH7_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x9c0);
-
-        /// address: 0x500009c4
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH7_DBG_TCR = @intToPtr(*volatile u32, base_address + 0x9c4);
-
-        /// address: 0x50000a00
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH8_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xa00);
-
-        /// address: 0x50000a04
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH8_DBG_TCR = @intToPtr(*volatile u32, base_address + 0xa04);
-
-        /// address: 0x50000a40
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH9_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xa40);
-
-        /// address: 0x50000a44
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH9_DBG_TCR = @intToPtr(*volatile u32, base_address + 0xa44);
-
-        /// address: 0x50000a80
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH10_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xa80);
-
-        /// address: 0x50000a84
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH10_DBG_TCR = @intToPtr(*volatile u32, base_address + 0xa84);
-
-        /// address: 0x50000ac0
-        /// Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can
-        /// perform on the peripheral without overflow/underflow. Write any value: clears
-        /// the counter, and cause channel to re-initiate DREQ handshake.
-        pub const CH11_DBG_CTDREQ = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xac0);
-
-        /// address: 0x50000ac4
-        /// Read to get channel TRANS_COUNT reload value, i.e. the length of the next
-        /// transfer
-        pub const CH11_DBG_TCR = @intToPtr(*volatile u32, base_address + 0xac4);
-    };
-
-    /// DPRAM layout for USB device.
-    pub const USBCTRL_DPRAM = struct {
-        pub const base_address = 0x50100000;
-        pub const version = "1";
-
-        /// address: 0x50100000
-        /// Bytes 0-3 of the SETUP packet from the host.
-        pub const SETUP_PACKET_LOW = @intToPtr(*volatile Mmio(32, packed struct {
-            BMREQUESTTYPE: u8,
-            BREQUEST: u8,
-            WVALUE: u16,
-        }), base_address + 0x0);
-
-        /// address: 0x50100004
-        /// Bytes 4-7 of the setup packet from the host.
-        pub const SETUP_PACKET_HIGH = @intToPtr(*volatile Mmio(32, packed struct {
-            WINDEX: u16,
-            WLENGTH: u16,
-        }), base_address + 0x4);
-
-        /// address: 0x50100008
-        pub const EP1_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x5010000c
-        pub const EP1_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x50100010
-        pub const EP2_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x50100014
-        pub const EP2_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x50100018
-        pub const EP3_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x5010001c
-        pub const EP3_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x50100020
-        pub const EP4_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x50100024
-        pub const EP4_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x50100028
-        pub const EP5_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x5010002c
-        pub const EP5_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x50100030
-        pub const EP6_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x50100034
-        pub const EP6_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x50100038
-        pub const EP7_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x5010003c
-        pub const EP7_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x50100040
-        pub const EP8_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x50100044
-        pub const EP8_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x50100048
-        pub const EP9_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x5010004c
-        pub const EP9_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x50100050
-        pub const EP10_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x50100054
-        pub const EP10_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x50100058
-        pub const EP11_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x5010005c
-        pub const EP11_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x50100060
-        pub const EP12_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x50100064
-        pub const EP12_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x50100068
-        pub const EP13_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x5010006c
-        pub const EP13_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x50100070
-        pub const EP14_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x50100074
-        pub const EP14_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x50100078
-        pub const EP15_IN_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x5010007c
-        pub const EP15_OUT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to
-            /// the start of the DPRAM.
-            BUFFER_ADDRESS: u16,
-            /// Trigger an interrupt if a NAK is sent. Intended for debug only.
-            INTERRUPT_ON_NAK: u1,
-            /// Trigger an interrupt if a STALL is sent. Intended for debug only.
-            INTERRUPT_ON_STALL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            ENDPOINT_TYPE: u2,
-            /// Trigger an interrupt each time both buffers are done. Only valid in double
-            /// buffered mode.
-            INTERRUPT_PER_DOUBLE_BUFF: u1,
-            /// Trigger an interrupt each time a buffer is done.
-            INTERRUPT_PER_BUFF: u1,
-            /// This endpoint is double buffered.
-            DOUBLE_BUFFERED: u1,
-            /// Enable this endpoint. The device will not reply to any packets for this endpoint
-            /// if this bit is not set.
-            ENABLE: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x50100080
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP0_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x50100084
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP0_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x50100088
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP1_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x5010008c
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP1_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x50100090
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP2_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x50100094
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP2_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0x94);
-
-        /// address: 0x50100098
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP3_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x5010009c
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP3_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0x9c);
-
-        /// address: 0x501000a0
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP4_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x501000a4
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP4_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x501000a8
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP5_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x501000ac
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP5_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x501000b0
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP6_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x501000b4
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP6_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x501000b8
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP7_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xb8);
-
-        /// address: 0x501000bc
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP7_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xbc);
-
-        /// address: 0x501000c0
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP8_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x501000c4
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP8_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xc4);
-
-        /// address: 0x501000c8
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP9_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x501000cc
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP9_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x501000d0
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP10_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x501000d4
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP10_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xd4);
-
-        /// address: 0x501000d8
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP11_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xd8);
-
-        /// address: 0x501000dc
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP11_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xdc);
-
-        /// address: 0x501000e0
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP12_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xe0);
-
-        /// address: 0x501000e4
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP12_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xe4);
-
-        /// address: 0x501000e8
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP13_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xe8);
-
-        /// address: 0x501000ec
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP13_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xec);
-
-        /// address: 0x501000f0
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP14_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xf0);
-
-        /// address: 0x501000f4
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP14_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xf4);
-
-        /// address: 0x501000f8
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP15_IN_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xf8);
-
-        /// address: 0x501000fc
-        /// Buffer control for both buffers of an endpoint. Fields ending in a _1 are for
-        /// buffer 1.\n
-        /// Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the
-        /// endpoint is in double buffered mode.
-        pub const EP15_OUT_BUFFER_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length of the data in buffer 0.
-            LENGTH_0: u10,
-            /// Buffer 0 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_0: u1,
-            /// Reply with a stall (valid for both buffers).
-            STALL: u1,
-            /// Reset the buffer selector to buffer 0.
-            RESET: u1,
-            /// The data pid of buffer 0.
-            PID_0: u1,
-            /// Buffer 0 is the last buffer of the transfer.
-            LAST_0: u1,
-            /// Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_0: u1,
-            /// The length of the data in buffer 1.
-            LENGTH_1: u10,
-            /// Buffer 1 is available. This bit is set to indicate the buffer can be used by the
-            /// controller. The controller clears the available bit when writing the status
-            /// back.
-            AVAILABLE_1: u1,
-            /// The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only
-            /// valid in double buffered mode for an Isochronous endpoint.\n
-            /// For a non Isochronous endpoint the offset is always 64 bytes.
-            DOUBLE_BUFFER_ISO_OFFSET: u2,
-            /// The data pid of buffer 1.
-            PID_1: u1,
-            /// Buffer 1 is the last buffer of the transfer.
-            LAST_1: u1,
-            /// Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate
-            /// the data is valid. For an OUT transfer (RX from the host) this bit should be
-            /// left as a 0. The host will set it when it has filled the buffer with data.
-            FULL_1: u1,
-        }), base_address + 0xfc);
-    };
-
-    /// USB FS/LS controller device registers
-    pub const USBCTRL_REGS = struct {
-        pub const base_address = 0x50110000;
-        pub const version = "1";
-
-        /// address: 0x50110000
-        /// Device address and endpoint control
-        pub const ADDR_ENDP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In device mode, the address that the device should respond to. Set in response
-            /// to a SET_ADDR setup packet from the host. In host mode set to the address of the
-            /// device to communicate with.
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Device endpoint to send data to. Only valid for HOST mode.
-            ENDPOINT: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x50110004
-        /// Interrupt endpoint 1. Only valid for HOST mode.
-        pub const ADDR_ENDP1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x50110008
-        /// Interrupt endpoint 2. Only valid for HOST mode.
-        pub const ADDR_ENDP2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x5011000c
-        /// Interrupt endpoint 3. Only valid for HOST mode.
-        pub const ADDR_ENDP3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0xc);
-
-        /// address: 0x50110010
-        /// Interrupt endpoint 4. Only valid for HOST mode.
-        pub const ADDR_ENDP4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x10);
-
-        /// address: 0x50110014
-        /// Interrupt endpoint 5. Only valid for HOST mode.
-        pub const ADDR_ENDP5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x14);
-
-        /// address: 0x50110018
-        /// Interrupt endpoint 6. Only valid for HOST mode.
-        pub const ADDR_ENDP6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x18);
-
-        /// address: 0x5011001c
-        /// Interrupt endpoint 7. Only valid for HOST mode.
-        pub const ADDR_ENDP7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x1c);
-
-        /// address: 0x50110020
-        /// Interrupt endpoint 8. Only valid for HOST mode.
-        pub const ADDR_ENDP8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x20);
-
-        /// address: 0x50110024
-        /// Interrupt endpoint 9. Only valid for HOST mode.
-        pub const ADDR_ENDP9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x24);
-
-        /// address: 0x50110028
-        /// Interrupt endpoint 10. Only valid for HOST mode.
-        pub const ADDR_ENDP10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x28);
-
-        /// address: 0x5011002c
-        /// Interrupt endpoint 11. Only valid for HOST mode.
-        pub const ADDR_ENDP11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x2c);
-
-        /// address: 0x50110030
-        /// Interrupt endpoint 12. Only valid for HOST mode.
-        pub const ADDR_ENDP12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x30);
-
-        /// address: 0x50110034
-        /// Interrupt endpoint 13. Only valid for HOST mode.
-        pub const ADDR_ENDP13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x34);
-
-        /// address: 0x50110038
-        /// Interrupt endpoint 14. Only valid for HOST mode.
-        pub const ADDR_ENDP14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x38);
-
-        /// address: 0x5011003c
-        /// Interrupt endpoint 15. Only valid for HOST mode.
-        pub const ADDR_ENDP15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device address
-            ADDRESS: u7,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            /// Endpoint number of the interrupt endpoint
-            ENDPOINT: u4,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            /// Direction of the interrupt endpoint. In=0, Out=1
-            INTEP_DIR: u1,
-            /// Interrupt EP requires preamble (is a low speed device on a full speed hub)
-            INTEP_PREAMBLE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-        }), base_address + 0x3c);
-
-        /// address: 0x50110040
-        /// Main control register
-        pub const MAIN_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable controller
-            CONTROLLER_EN: u1,
-            /// Device mode = 0, Host mode = 1
-            HOST_NDEVICE: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            reserved18: u1 = 0,
-            reserved19: u1 = 0,
-            reserved20: u1 = 0,
-            reserved21: u1 = 0,
-            reserved22: u1 = 0,
-            reserved23: u1 = 0,
-            reserved24: u1 = 0,
-            reserved25: u1 = 0,
-            reserved26: u1 = 0,
-            reserved27: u1 = 0,
-            reserved28: u1 = 0,
-            /// Reduced timings for simulation
-            SIM_TIMING: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x50110044
-        /// Set the SOF (Start of Frame) frame number in the host controller. The SOF packet
-        /// is sent every 1ms and the host will increment the frame number by 1 each time.
-        pub const SOF_WR = @intToPtr(*volatile Mmio(32, packed struct {
-            COUNT: u11,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x44);
-
-        /// address: 0x50110048
-        /// Read the last SOF (Start of Frame) frame number seen. In device mode the last
-        /// SOF received from the host. In host mode the last SOF sent by the host.
-        pub const SOF_RD = @intToPtr(*volatile Mmio(32, packed struct {
-            COUNT: u11,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-        }), base_address + 0x48);
-
-        /// address: 0x5011004c
-        /// SIE control register
-        pub const SIE_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Host: Start transaction
-            START_TRANS: u1,
-            /// Host: Send Setup packet
-            SEND_SETUP: u1,
-            /// Host: Send transaction (OUT from host)
-            SEND_DATA: u1,
-            /// Host: Receive transaction (IN to host)
-            RECEIVE_DATA: u1,
-            /// Host: Stop transaction
-            STOP_TRANS: u1,
-            reserved0: u1 = 0,
-            /// Host: Preable enable for LS device on FS hub
-            PREAMBLE_EN: u1,
-            reserved1: u1 = 0,
-            /// Host: Delay packet(s) until after SOF
-            SOF_SYNC: u1,
-            /// Host: Enable SOF generation (for full speed bus)
-            SOF_EN: u1,
-            /// Host: Enable keep alive packet (for low speed bus)
-            KEEP_ALIVE_EN: u1,
-            /// Host: Enable VBUS
-            VBUS_EN: u1,
-            /// Device: Remote wakeup. Device can initiate its own resume after suspend.
-            RESUME: u1,
-            /// Host: Reset bus
-            RESET_BUS: u1,
-            reserved2: u1 = 0,
-            /// Host: Enable pull down resistors
-            PULLDOWN_EN: u1,
-            /// Device: Enable pull up resistor
-            PULLUP_EN: u1,
-            /// Device: Pull-up strength (0=1K2, 1=2k3)
-            RPU_OPT: u1,
-            /// Power down bus transceiver
-            TRANSCEIVER_PD: u1,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Direct control of DM
-            DIRECT_DM: u1,
-            /// Direct control of DP
-            DIRECT_DP: u1,
-            /// Direct bus drive enable
-            DIRECT_EN: u1,
-            /// Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
-            EP0_INT_NAK: u1,
-            /// Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0
-            EP0_INT_2BUF: u1,
-            /// Device: Set bit in BUFF_STATUS for every buffer completed on EP0
-            EP0_INT_1BUF: u1,
-            /// Device: EP0 single buffered = 0, double buffered = 1
-            EP0_DOUBLE_BUF: u1,
-            /// Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
-            EP0_INT_STALL: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x50110050
-        /// SIE status register
-        pub const SIE_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Device: VBUS Detected
-            VBUS_DETECTED: u1,
-            reserved0: u1 = 0,
-            /// USB bus line state
-            LINE_STATE: u2,
-            /// Bus in suspended state. Valid for device and host. Host and device will go into
-            /// suspend if neither Keep Alive / SOF frames are enabled.
-            SUSPENDED: u1,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// Host: device speed. Disconnected = 00, LS = 01, FS = 10
-            SPEED: u2,
-            /// VBUS over current detected
-            VBUS_OVER_CURR: u1,
-            /// Host: Device has initiated a remote resume. Device: host has initiated a resume.
-            RESUME: u1,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Device: connected
-            CONNECTED: u1,
-            /// Device: Setup packet received
-            SETUP_REC: u1,
-            /// Transaction complete.\n\n
-            /// Raised by device if:\n\n
-            /// * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control
-            /// register\n\n
-            /// Raised by host if:\n\n
-            /// * A setup packet is sent when no data in or data out transaction follows * An IN
-            /// packet is received and the `LAST_BUFF` bit is set in the buffer control register
-            /// * An IN packet is received with zero length * An OUT packet is sent and the
-            /// `LAST_BUFF` bit is set
-            TRANS_COMPLETE: u1,
-            /// Device: bus reset received
-            BUS_RESET: u1,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            /// CRC Error. Raised by the Serial RX engine.
-            CRC_ERROR: u1,
-            /// Bit Stuff Error. Raised by the Serial RX engine.
-            BIT_STUFF_ERROR: u1,
-            /// RX overflow is raised by the Serial RX engine if the incoming data is too fast.
-            RX_OVERFLOW: u1,
-            /// RX timeout is raised by both the host and device if an ACK is not received in
-            /// the maximum time specified by the USB spec.
-            RX_TIMEOUT: u1,
-            /// Host: NAK received
-            NAK_REC: u1,
-            /// Host: STALL received
-            STALL_REC: u1,
-            /// ACK received. Raised by both host and device.
-            ACK_REC: u1,
-            /// Data Sequence Error.\n\n
-            /// The device can raise a sequence error in the following conditions:\n\n
-            /// * A SETUP packet is received followed by a DATA1 packet (data phase should
-            /// always be DATA0) * An OUT packet is received from the host but doesn't match the
-            /// data pid in the buffer control register read from DPSRAM\n\n
-            /// The host can raise a data sequence error in the following conditions:\n\n
-            /// * An IN packet from the device has the wrong data PID
-            DATA_SEQ_ERROR: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x50110054
-        /// interrupt endpoint control register
-        pub const INT_EP_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            /// Host: Enable interrupt endpoint 1 -> 15
-            INT_EP_ACTIVE: u15,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x54);
-
-        /// address: 0x50110058
-        /// Buffer status register. A bit set here indicates that a buffer has completed on
-        /// the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers
-        /// to be completed, so clearing the buffer status bit may instantly re set it on
-        /// the next clock cycle.
-        pub const BUFF_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            EP0_IN: u1,
-            EP0_OUT: u1,
-            EP1_IN: u1,
-            EP1_OUT: u1,
-            EP2_IN: u1,
-            EP2_OUT: u1,
-            EP3_IN: u1,
-            EP3_OUT: u1,
-            EP4_IN: u1,
-            EP4_OUT: u1,
-            EP5_IN: u1,
-            EP5_OUT: u1,
-            EP6_IN: u1,
-            EP6_OUT: u1,
-            EP7_IN: u1,
-            EP7_OUT: u1,
-            EP8_IN: u1,
-            EP8_OUT: u1,
-            EP9_IN: u1,
-            EP9_OUT: u1,
-            EP10_IN: u1,
-            EP10_OUT: u1,
-            EP11_IN: u1,
-            EP11_OUT: u1,
-            EP12_IN: u1,
-            EP12_OUT: u1,
-            EP13_IN: u1,
-            EP13_OUT: u1,
-            EP14_IN: u1,
-            EP14_OUT: u1,
-            EP15_IN: u1,
-            EP15_OUT: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x5011005c
-        /// Which of the double buffers should be handled. Only valid if using an interrupt
-        /// per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint
-        /// polling because they are only single buffered.
-        pub const BUFF_CPU_SHOULD_HANDLE = @intToPtr(*volatile Mmio(32, packed struct {
-            EP0_IN: u1,
-            EP0_OUT: u1,
-            EP1_IN: u1,
-            EP1_OUT: u1,
-            EP2_IN: u1,
-            EP2_OUT: u1,
-            EP3_IN: u1,
-            EP3_OUT: u1,
-            EP4_IN: u1,
-            EP4_OUT: u1,
-            EP5_IN: u1,
-            EP5_OUT: u1,
-            EP6_IN: u1,
-            EP6_OUT: u1,
-            EP7_IN: u1,
-            EP7_OUT: u1,
-            EP8_IN: u1,
-            EP8_OUT: u1,
-            EP9_IN: u1,
-            EP9_OUT: u1,
-            EP10_IN: u1,
-            EP10_OUT: u1,
-            EP11_IN: u1,
-            EP11_OUT: u1,
-            EP12_IN: u1,
-            EP12_OUT: u1,
-            EP13_IN: u1,
-            EP13_OUT: u1,
-            EP14_IN: u1,
-            EP14_OUT: u1,
-            EP15_IN: u1,
-            EP15_OUT: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x50110060
-        /// Device only: Can be set to ignore the buffer control register for this endpoint
-        /// in case you would like to revoke a buffer. A NAK will be sent for every access
-        /// to the endpoint until this bit is cleared. A corresponding bit in
-        /// `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.
-        pub const EP_ABORT = @intToPtr(*volatile Mmio(32, packed struct {
-            EP0_IN: u1,
-            EP0_OUT: u1,
-            EP1_IN: u1,
-            EP1_OUT: u1,
-            EP2_IN: u1,
-            EP2_OUT: u1,
-            EP3_IN: u1,
-            EP3_OUT: u1,
-            EP4_IN: u1,
-            EP4_OUT: u1,
-            EP5_IN: u1,
-            EP5_OUT: u1,
-            EP6_IN: u1,
-            EP6_OUT: u1,
-            EP7_IN: u1,
-            EP7_OUT: u1,
-            EP8_IN: u1,
-            EP8_OUT: u1,
-            EP9_IN: u1,
-            EP9_OUT: u1,
-            EP10_IN: u1,
-            EP10_OUT: u1,
-            EP11_IN: u1,
-            EP11_OUT: u1,
-            EP12_IN: u1,
-            EP12_OUT: u1,
-            EP13_IN: u1,
-            EP13_OUT: u1,
-            EP14_IN: u1,
-            EP14_OUT: u1,
-            EP15_IN: u1,
-            EP15_OUT: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x50110064
-        /// Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle
-        /// so the programmer knows it is safe to modify the buffer control register.
-        pub const EP_ABORT_DONE = @intToPtr(*volatile Mmio(32, packed struct {
-            EP0_IN: u1,
-            EP0_OUT: u1,
-            EP1_IN: u1,
-            EP1_OUT: u1,
-            EP2_IN: u1,
-            EP2_OUT: u1,
-            EP3_IN: u1,
-            EP3_OUT: u1,
-            EP4_IN: u1,
-            EP4_OUT: u1,
-            EP5_IN: u1,
-            EP5_OUT: u1,
-            EP6_IN: u1,
-            EP6_OUT: u1,
-            EP7_IN: u1,
-            EP7_OUT: u1,
-            EP8_IN: u1,
-            EP8_OUT: u1,
-            EP9_IN: u1,
-            EP9_OUT: u1,
-            EP10_IN: u1,
-            EP10_OUT: u1,
-            EP11_IN: u1,
-            EP11_OUT: u1,
-            EP12_IN: u1,
-            EP12_OUT: u1,
-            EP13_IN: u1,
-            EP13_OUT: u1,
-            EP14_IN: u1,
-            EP14_OUT: u1,
-            EP15_IN: u1,
-            EP15_OUT: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x50110068
-        /// Device: this bit must be set in conjunction with the `STALL` bit in the buffer
-        /// control register to send a STALL on EP0. The device controller clears these bits
-        /// when a SETUP packet is received because the USB spec requires that a STALL
-        /// condition is cleared when a SETUP packet is received.
-        pub const EP_STALL_ARM = @intToPtr(*volatile Mmio(32, packed struct {
-            EP0_IN: u1,
-            EP0_OUT: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x68);
-
-        /// address: 0x5011006c
-        /// Used by the host controller. Sets the wait time in microseconds before trying
-        /// again if the device replies with a NAK.
-        pub const NAK_POLL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// NAK polling interval for a low speed device
-            DELAY_LS: u10,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            /// NAK polling interval for a full speed device
-            DELAY_FS: u10,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-        }), base_address + 0x6c);
-
-        /// address: 0x50110070
-        /// Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For
-        /// EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the
-        /// endpoint control register.
-        pub const EP_STATUS_STALL_NAK = @intToPtr(*volatile Mmio(32, packed struct {
-            EP0_IN: u1,
-            EP0_OUT: u1,
-            EP1_IN: u1,
-            EP1_OUT: u1,
-            EP2_IN: u1,
-            EP2_OUT: u1,
-            EP3_IN: u1,
-            EP3_OUT: u1,
-            EP4_IN: u1,
-            EP4_OUT: u1,
-            EP5_IN: u1,
-            EP5_OUT: u1,
-            EP6_IN: u1,
-            EP6_OUT: u1,
-            EP7_IN: u1,
-            EP7_OUT: u1,
-            EP8_IN: u1,
-            EP8_OUT: u1,
-            EP9_IN: u1,
-            EP9_OUT: u1,
-            EP10_IN: u1,
-            EP10_OUT: u1,
-            EP11_IN: u1,
-            EP11_OUT: u1,
-            EP12_IN: u1,
-            EP12_OUT: u1,
-            EP13_IN: u1,
-            EP13_OUT: u1,
-            EP14_IN: u1,
-            EP14_OUT: u1,
-            EP15_IN: u1,
-            EP15_OUT: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x50110074
-        /// Where to connect the USB controller. Should be to_phy by default.
-        pub const USB_MUXING = @intToPtr(*volatile Mmio(32, packed struct {
-            TO_PHY: u1,
-            TO_EXTPHY: u1,
-            TO_DIGITAL_PAD: u1,
-            SOFTCON: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x74);
-
-        /// address: 0x50110078
-        /// Overrides for the power signals in the event that the VBUS signals are not
-        /// hooked up to GPIO. Set the value of the override and then the override enable to
-        /// switch over to the override value.
-        pub const USB_PWR = @intToPtr(*volatile Mmio(32, packed struct {
-            VBUS_EN: u1,
-            VBUS_EN_OVERRIDE_EN: u1,
-            VBUS_DETECT: u1,
-            VBUS_DETECT_OVERRIDE_EN: u1,
-            OVERCURR_DETECT: u1,
-            OVERCURR_DETECT_EN: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-        }), base_address + 0x78);
-
-        /// address: 0x5011007c
-        /// This register allows for direct control of the USB phy. Use in conjunction with
-        /// usbphy_direct_override register to enable each override bit.
-        pub const USBPHY_DIRECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2
-            DP_PULLUP_HISEL: u1,
-            /// DP pull up enable
-            DP_PULLUP_EN: u1,
-            /// DP pull down enable
-            DP_PULLDN_EN: u1,
-            reserved0: u1 = 0,
-            /// Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2
-            DM_PULLUP_HISEL: u1,
-            /// DM pull up enable
-            DM_PULLUP_EN: u1,
-            /// DM pull down enable
-            DM_PULLDN_EN: u1,
-            reserved1: u1 = 0,
-            /// Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z
-            /// state; 1 - DPP/DPM driving\n
-            /// If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving
-            TX_DP_OE: u1,
-            /// Output enable. If TX_DIFFMODE=1, Ignored.\n
-            /// If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving
-            TX_DM_OE: u1,
-            /// Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable
-            /// drive. DPP=TX_DP, DPM=~TX_DP\n
-            /// If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP
-            TX_DP: u1,
-            /// Output data. TX_DIFFMODE=1, Ignored\n
-            /// TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM
-            TX_DM: u1,
-            /// RX power down override (if override enable is set). 1 = powered down.
-            RX_PD: u1,
-            /// TX power down override (if override enable is set). 1 = powered down.
-            TX_PD: u1,
-            /// TX_FSSLEW=0: Low speed slew rate\n
-            /// TX_FSSLEW=1: Full speed slew rate
-            TX_FSSLEW: u1,
-            /// TX_DIFFMODE=0: Single ended mode\n
-            /// TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)
-            TX_DIFFMODE: u1,
-            /// Differential RX
-            RX_DD: u1,
-            /// DPP pin state
-            RX_DP: u1,
-            /// DPM pin state
-            RX_DM: u1,
-            /// DP overcurrent
-            DP_OVCN: u1,
-            /// DM overcurrent
-            DM_OVCN: u1,
-            /// DP over voltage
-            DP_OVV: u1,
-            /// DM over voltage
-            DM_OVV: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-        }), base_address + 0x7c);
-
-        /// address: 0x50110080
-        /// Override enable for each control in usbphy_direct
-        pub const USBPHY_DIRECT_OVERRIDE = @intToPtr(*volatile Mmio(32, packed struct {
-            DP_PULLUP_HISEL_OVERRIDE_EN: u1,
-            DM_PULLUP_HISEL_OVERRIDE_EN: u1,
-            DP_PULLUP_EN_OVERRIDE_EN: u1,
-            DP_PULLDN_EN_OVERRIDE_EN: u1,
-            DM_PULLDN_EN_OVERRIDE_EN: u1,
-            TX_DP_OE_OVERRIDE_EN: u1,
-            TX_DM_OE_OVERRIDE_EN: u1,
-            TX_DP_OVERRIDE_EN: u1,
-            TX_DM_OVERRIDE_EN: u1,
-            RX_PD_OVERRIDE_EN: u1,
-            TX_PD_OVERRIDE_EN: u1,
-            TX_FSSLEW_OVERRIDE_EN: u1,
-            DM_PULLUP_OVERRIDE_EN: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            TX_DIFFMODE_OVERRIDE_EN: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-        }), base_address + 0x80);
-
-        /// address: 0x50110084
-        /// Used to adjust trim values of USB phy pull down resistors.
-        pub const USBPHY_TRIM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Value to drive to USB PHY\n
-            /// DP pulldown resistor trim control\n
-            /// Experimental data suggests that the reset value will work, but this register
-            /// allows adjustment if required
-            DP_PULLDN_TRIM: u5,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            /// Value to drive to USB PHY\n
-            /// DM pulldown resistor trim control\n
-            /// Experimental data suggests that the reset value will work, but this register
-            /// allows adjustment if required
-            DM_PULLDN_TRIM: u5,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-        }), base_address + 0x84);
-
-        /// address: 0x5011008c
-        /// Raw Interrupts
-        pub const INTR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Host: raised when a device is connected or disconnected (i.e. when
-            /// SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
-            HOST_CONN_DIS: u1,
-            /// Host: raised when a device wakes up the host. Cleared by writing to
-            /// SIE_STATUS.RESUME
-            HOST_RESUME: u1,
-            /// Host: raised every time the host sends a SOF (Start of Frame). Cleared by
-            /// reading SOF_RD
-            HOST_SOF: u1,
-            /// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this
-            /// bit.
-            TRANS_COMPLETE: u1,
-            /// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in
-            /// BUFF_STATUS.
-            BUFF_STATUS: u1,
-            /// Source: SIE_STATUS.DATA_SEQ_ERROR
-            ERROR_DATA_SEQ: u1,
-            /// Source: SIE_STATUS.RX_TIMEOUT
-            ERROR_RX_TIMEOUT: u1,
-            /// Source: SIE_STATUS.RX_OVERFLOW
-            ERROR_RX_OVERFLOW: u1,
-            /// Source: SIE_STATUS.BIT_STUFF_ERROR
-            ERROR_BIT_STUFF: u1,
-            /// Source: SIE_STATUS.CRC_ERROR
-            ERROR_CRC: u1,
-            /// Source: SIE_STATUS.STALL_REC
-            STALL: u1,
-            /// Source: SIE_STATUS.VBUS_DETECTED
-            VBUS_DETECT: u1,
-            /// Source: SIE_STATUS.BUS_RESET
-            BUS_RESET: u1,
-            /// Set when the device connection state changes. Cleared by writing to
-            /// SIE_STATUS.CONNECTED
-            DEV_CONN_DIS: u1,
-            /// Set when the device suspend state changes. Cleared by writing to
-            /// SIE_STATUS.SUSPENDED
-            DEV_SUSPEND: u1,
-            /// Set when the device receives a resume from the host. Cleared by writing to
-            /// SIE_STATUS.RESUME
-            DEV_RESUME_FROM_HOST: u1,
-            /// Device. Source: SIE_STATUS.SETUP_REC
-            SETUP_REQ: u1,
-            /// Set every time the device receives a SOF (Start of Frame) packet. Cleared by
-            /// reading SOF_RD
-            DEV_SOF: u1,
-            /// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in
-            /// ABORT_DONE.
-            ABORT_DONE: u1,
-            /// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in
-            /// EP_STATUS_STALL_NAK.
-            EP_STALL_NAK: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-        }), base_address + 0x8c);
-
-        /// address: 0x50110090
-        /// Interrupt Enable
-        pub const INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Host: raised when a device is connected or disconnected (i.e. when
-            /// SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
-            HOST_CONN_DIS: u1,
-            /// Host: raised when a device wakes up the host. Cleared by writing to
-            /// SIE_STATUS.RESUME
-            HOST_RESUME: u1,
-            /// Host: raised every time the host sends a SOF (Start of Frame). Cleared by
-            /// reading SOF_RD
-            HOST_SOF: u1,
-            /// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this
-            /// bit.
-            TRANS_COMPLETE: u1,
-            /// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in
-            /// BUFF_STATUS.
-            BUFF_STATUS: u1,
-            /// Source: SIE_STATUS.DATA_SEQ_ERROR
-            ERROR_DATA_SEQ: u1,
-            /// Source: SIE_STATUS.RX_TIMEOUT
-            ERROR_RX_TIMEOUT: u1,
-            /// Source: SIE_STATUS.RX_OVERFLOW
-            ERROR_RX_OVERFLOW: u1,
-            /// Source: SIE_STATUS.BIT_STUFF_ERROR
-            ERROR_BIT_STUFF: u1,
-            /// Source: SIE_STATUS.CRC_ERROR
-            ERROR_CRC: u1,
-            /// Source: SIE_STATUS.STALL_REC
-            STALL: u1,
-            /// Source: SIE_STATUS.VBUS_DETECTED
-            VBUS_DETECT: u1,
-            /// Source: SIE_STATUS.BUS_RESET
-            BUS_RESET: u1,
-            /// Set when the device connection state changes. Cleared by writing to
-            /// SIE_STATUS.CONNECTED
-            DEV_CONN_DIS: u1,
-            /// Set when the device suspend state changes. Cleared by writing to
-            /// SIE_STATUS.SUSPENDED
-            DEV_SUSPEND: u1,
-            /// Set when the device receives a resume from the host. Cleared by writing to
-            /// SIE_STATUS.RESUME
-            DEV_RESUME_FROM_HOST: u1,
-            /// Device. Source: SIE_STATUS.SETUP_REC
-            SETUP_REQ: u1,
-            /// Set every time the device receives a SOF (Start of Frame) packet. Cleared by
-            /// reading SOF_RD
-            DEV_SOF: u1,
-            /// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in
-            /// ABORT_DONE.
-            ABORT_DONE: u1,
-            /// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in
-            /// EP_STATUS_STALL_NAK.
-            EP_STALL_NAK: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-        }), base_address + 0x90);
-
-        /// address: 0x50110094
-        /// Interrupt Force
-        pub const INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Host: raised when a device is connected or disconnected (i.e. when
-            /// SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
-            HOST_CONN_DIS: u1,
-            /// Host: raised when a device wakes up the host. Cleared by writing to
-            /// SIE_STATUS.RESUME
-            HOST_RESUME: u1,
-            /// Host: raised every time the host sends a SOF (Start of Frame). Cleared by
-            /// reading SOF_RD
-            HOST_SOF: u1,
-            /// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this
-            /// bit.
-            TRANS_COMPLETE: u1,
-            /// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in
-            /// BUFF_STATUS.
-            BUFF_STATUS: u1,
-            /// Source: SIE_STATUS.DATA_SEQ_ERROR
-            ERROR_DATA_SEQ: u1,
-            /// Source: SIE_STATUS.RX_TIMEOUT
-            ERROR_RX_TIMEOUT: u1,
-            /// Source: SIE_STATUS.RX_OVERFLOW
-            ERROR_RX_OVERFLOW: u1,
-            /// Source: SIE_STATUS.BIT_STUFF_ERROR
-            ERROR_BIT_STUFF: u1,
-            /// Source: SIE_STATUS.CRC_ERROR
-            ERROR_CRC: u1,
-            /// Source: SIE_STATUS.STALL_REC
-            STALL: u1,
-            /// Source: SIE_STATUS.VBUS_DETECTED
-            VBUS_DETECT: u1,
-            /// Source: SIE_STATUS.BUS_RESET
-            BUS_RESET: u1,
-            /// Set when the device connection state changes. Cleared by writing to
-            /// SIE_STATUS.CONNECTED
-            DEV_CONN_DIS: u1,
-            /// Set when the device suspend state changes. Cleared by writing to
-            /// SIE_STATUS.SUSPENDED
-            DEV_SUSPEND: u1,
-            /// Set when the device receives a resume from the host. Cleared by writing to
-            /// SIE_STATUS.RESUME
-            DEV_RESUME_FROM_HOST: u1,
-            /// Device. Source: SIE_STATUS.SETUP_REC
-            SETUP_REQ: u1,
-            /// Set every time the device receives a SOF (Start of Frame) packet. Cleared by
-            /// reading SOF_RD
-            DEV_SOF: u1,
-            /// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in
-            /// ABORT_DONE.
-            ABORT_DONE: u1,
-            /// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in
-            /// EP_STATUS_STALL_NAK.
-            EP_STALL_NAK: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-        }), base_address + 0x94);
-
-        /// address: 0x50110098
-        /// Interrupt status after masking & forcing
-        pub const INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Host: raised when a device is connected or disconnected (i.e. when
-            /// SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
-            HOST_CONN_DIS: u1,
-            /// Host: raised when a device wakes up the host. Cleared by writing to
-            /// SIE_STATUS.RESUME
-            HOST_RESUME: u1,
-            /// Host: raised every time the host sends a SOF (Start of Frame). Cleared by
-            /// reading SOF_RD
-            HOST_SOF: u1,
-            /// Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this
-            /// bit.
-            TRANS_COMPLETE: u1,
-            /// Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in
-            /// BUFF_STATUS.
-            BUFF_STATUS: u1,
-            /// Source: SIE_STATUS.DATA_SEQ_ERROR
-            ERROR_DATA_SEQ: u1,
-            /// Source: SIE_STATUS.RX_TIMEOUT
-            ERROR_RX_TIMEOUT: u1,
-            /// Source: SIE_STATUS.RX_OVERFLOW
-            ERROR_RX_OVERFLOW: u1,
-            /// Source: SIE_STATUS.BIT_STUFF_ERROR
-            ERROR_BIT_STUFF: u1,
-            /// Source: SIE_STATUS.CRC_ERROR
-            ERROR_CRC: u1,
-            /// Source: SIE_STATUS.STALL_REC
-            STALL: u1,
-            /// Source: SIE_STATUS.VBUS_DETECTED
-            VBUS_DETECT: u1,
-            /// Source: SIE_STATUS.BUS_RESET
-            BUS_RESET: u1,
-            /// Set when the device connection state changes. Cleared by writing to
-            /// SIE_STATUS.CONNECTED
-            DEV_CONN_DIS: u1,
-            /// Set when the device suspend state changes. Cleared by writing to
-            /// SIE_STATUS.SUSPENDED
-            DEV_SUSPEND: u1,
-            /// Set when the device receives a resume from the host. Cleared by writing to
-            /// SIE_STATUS.RESUME
-            DEV_RESUME_FROM_HOST: u1,
-            /// Device. Source: SIE_STATUS.SETUP_REC
-            SETUP_REQ: u1,
-            /// Set every time the device receives a SOF (Start of Frame) packet. Cleared by
-            /// reading SOF_RD
-            DEV_SOF: u1,
-            /// Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in
-            /// ABORT_DONE.
-            ABORT_DONE: u1,
-            /// Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in
-            /// EP_STATUS_STALL_NAK.
-            EP_STALL_NAK: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-        }), base_address + 0x98);
-    };
-
-    /// Programmable IO block
-    pub const PIO0 = struct {
-        pub const base_address = 0x50200000;
-        pub const version = "1";
-
-        /// address: 0x50200000
-        /// PIO control register
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable/disable each of the four state machines by writing 1/0 to each of these
-            /// four bits. When disabled, a state machine will cease executing instructions,
-            /// except those written directly to SMx_INSTR by the system. Multiple bits can be
-            /// set/cleared at once to run/halt multiple state machines simultaneously.
-            SM_ENABLE: u4,
-            /// Write 1 to instantly clear internal SM state which may be otherwise difficult to
-            /// access and will affect future execution.\n\n
-            /// Specifically, the following are cleared: input and output shift counters; the
-            /// contents of the input shift register; the delay counter; the waiting-on-IRQ
-            /// state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any
-            /// pin write left asserted due to OUT_STICKY.
-            SM_RESTART: u4,
-            /// Restart a state machine's clock divider from an initial phase of 0. Clock
-            /// dividers are free-running, so once started, their output (including fractional
-            /// jitter) is completely determined by the integer/fractional divisor configured in
-            /// SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor
-            /// are restarted simultaneously, by writing multiple 1 bits to this field, the
-            /// execution clocks of those state machines will run in precise lockstep.\n\n
-            /// Note that setting/clearing SM_ENABLE does not stop the clock divider from
-            /// running, so once multiple state machines' clocks are synchronised, it is safe to
-            /// disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n
-            /// Note also that CLKDIV_RESTART can be written to whilst the state machine is
-            /// running, and this is useful to resynchronise clock dividers after the divisors
-            /// (SMx_CLKDIV) have been changed on-the-fly.
-            CLKDIV_RESTART: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x50200004
-        /// FIFO status register
-        pub const FSTAT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State machine RX FIFO is full
-            RXFULL: u4,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// State machine RX FIFO is empty
-            RXEMPTY: u4,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// State machine TX FIFO is full
-            TXFULL: u4,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            /// State machine TX FIFO is empty
-            TXEMPTY: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x50200008
-        /// FIFO debug register
-        pub const FDEBUG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with
-            /// autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO
-            /// took place, in which case the state machine has dropped data. Write 1 to clear.
-            RXSTALL: u4,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to
-            /// clear. Note that read-on-empty does not perturb the state of the FIFO in any
-            /// way, but the data returned by reading from an empty FIFO is undefined, so this
-            /// flag generally only becomes set due to some kind of software error.
-            RXUNDER: u4,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to
-            /// clear. Note that write-on-full does not alter the state or contents of the FIFO
-            /// in any way, but the data that the system attempted to write is dropped, so if
-            /// this flag is set, your software has quite likely dropped some data on the floor.
-            TXOVER: u4,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            /// State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT
-            /// with autopull enabled. Write 1 to clear.
-            TXSTALL: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x5020000c
-        /// FIFO levels
-        pub const FLEVEL = @intToPtr(*volatile Mmio(32, packed struct {
-            TX0: u4,
-            RX0: u4,
-            TX1: u4,
-            RX1: u4,
-            TX2: u4,
-            RX2: u4,
-            TX3: u4,
-            RX3: u4,
-        }), base_address + 0xc);
-
-        /// address: 0x50200010
-        /// Direct write access to the TX FIFO for this state machine. Each write pushes one
-        /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO
-        /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-        pub const TXF0 = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x50200014
-        /// Direct write access to the TX FIFO for this state machine. Each write pushes one
-        /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO
-        /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-        pub const TXF1 = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x50200018
-        /// Direct write access to the TX FIFO for this state machine. Each write pushes one
-        /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO
-        /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-        pub const TXF2 = @intToPtr(*volatile u32, base_address + 0x18);
-
-        /// address: 0x5020001c
-        /// Direct write access to the TX FIFO for this state machine. Each write pushes one
-        /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO
-        /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-        pub const TXF3 = @intToPtr(*volatile u32, base_address + 0x1c);
-
-        /// address: 0x50200020
-        /// Direct read access to the RX FIFO for this state machine. Each read pops one
-        /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the
-        /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The
-        /// data returned to the system on a read from an empty FIFO is undefined.
-        pub const RXF0 = @intToPtr(*volatile u32, base_address + 0x20);
-
-        /// address: 0x50200024
-        /// Direct read access to the RX FIFO for this state machine. Each read pops one
-        /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the
-        /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The
-        /// data returned to the system on a read from an empty FIFO is undefined.
-        pub const RXF1 = @intToPtr(*volatile u32, base_address + 0x24);
-
-        /// address: 0x50200028
-        /// Direct read access to the RX FIFO for this state machine. Each read pops one
-        /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the
-        /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The
-        /// data returned to the system on a read from an empty FIFO is undefined.
-        pub const RXF2 = @intToPtr(*volatile u32, base_address + 0x28);
-
-        /// address: 0x5020002c
-        /// Direct read access to the RX FIFO for this state machine. Each read pops one
-        /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the
-        /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The
-        /// data returned to the system on a read from an empty FIFO is undefined.
-        pub const RXF3 = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x50200030
-        /// State machine IRQ flags register. Write 1 to clear. There are 8 state machine
-        /// IRQ flags, which can be set, cleared, and waited on by the state machines.
-        /// There's no fixed association between flags and state machines -- any state
-        /// machine can use any flag.\n\n
-        /// Any of the 8 flags can be used for timing synchronisation between state
-        /// machines, using IRQ and WAIT instructions. The lower four of these flags are
-        /// also routed out to system-level interrupt requests, alongside FIFO status
-        /// interrupts -- see e.g. IRQ0_INTE.
-        pub const IRQ = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x30);
-
-        /// address: 0x50200034
-        /// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ.
-        /// Note this is different to the INTF register: writing here affects PIO internal
-        /// state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and
-        /// is not visible to the state machines.
-        pub const IRQ_FORCE = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x34);
-
-        /// address: 0x50200038
-        /// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic
-        /// from metastabilities. This increases input delay, and for fast synchronous IO
-        /// (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this
-        /// register corresponds to one GPIO.\n
-        /// 0 -> input is synchronized (default)\n
-        /// 1 -> synchronizer is bypassed\n
-        /// If in doubt, leave this register as all zeroes.
-        pub const INPUT_SYNC_BYPASS = @intToPtr(*volatile u32, base_address + 0x38);
-
-        /// address: 0x5020003c
-        /// Read to sample the pad output values PIO is currently driving to the GPIOs. On
-        /// RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.
-        pub const DBG_PADOUT = @intToPtr(*volatile u32, base_address + 0x3c);
-
-        /// address: 0x50200040
-        /// Read to sample the pad output enables (direction) PIO is currently driving to
-        /// the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are
-        /// hardwired to 0.
-        pub const DBG_PADOE = @intToPtr(*volatile u32, base_address + 0x40);
-
-        /// address: 0x50200044
-        /// The PIO hardware has some free parameters that may vary between chip products.\n
-        /// These should be provided in the chip datasheet, but are also exposed here.
-        pub const DBG_CFGINFO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The depth of the state machine TX/RX FIFOs, measured in words.\n
-            /// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n
-            /// this depth.
-            FIFO_DEPTH: u6,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// The number of state machines this PIO instance is equipped with.
-            SM_COUNT: u4,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            /// The size of the instruction memory, measured in units of one instruction
-            IMEM_SIZE: u6,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-        }), base_address + 0x44);
-
-        /// address: 0x50200048
-        /// Write-only access to instruction memory location 0
-        pub const INSTR_MEM0 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x48);
-
-        /// address: 0x5020004c
-        /// Write-only access to instruction memory location 1
-        pub const INSTR_MEM1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x4c);
-
-        /// address: 0x50200050
-        /// Write-only access to instruction memory location 2
-        pub const INSTR_MEM2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x50);
-
-        /// address: 0x50200054
-        /// Write-only access to instruction memory location 3
-        pub const INSTR_MEM3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x54);
-
-        /// address: 0x50200058
-        /// Write-only access to instruction memory location 4
-        pub const INSTR_MEM4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x58);
-
-        /// address: 0x5020005c
-        /// Write-only access to instruction memory location 5
-        pub const INSTR_MEM5 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c);
-
-        /// address: 0x50200060
-        /// Write-only access to instruction memory location 6
-        pub const INSTR_MEM6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x60);
-
-        /// address: 0x50200064
-        /// Write-only access to instruction memory location 7
-        pub const INSTR_MEM7 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x64);
-
-        /// address: 0x50200068
-        /// Write-only access to instruction memory location 8
-        pub const INSTR_MEM8 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x68);
-
-        /// address: 0x5020006c
-        /// Write-only access to instruction memory location 9
-        pub const INSTR_MEM9 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x6c);
-
-        /// address: 0x50200070
-        /// Write-only access to instruction memory location 10
-        pub const INSTR_MEM10 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x70);
-
-        /// address: 0x50200074
-        /// Write-only access to instruction memory location 11
-        pub const INSTR_MEM11 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x74);
-
-        /// address: 0x50200078
-        /// Write-only access to instruction memory location 12
-        pub const INSTR_MEM12 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x78);
-
-        /// address: 0x5020007c
-        /// Write-only access to instruction memory location 13
-        pub const INSTR_MEM13 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x7c);
-
-        /// address: 0x50200080
-        /// Write-only access to instruction memory location 14
-        pub const INSTR_MEM14 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x80);
-
-        /// address: 0x50200084
-        /// Write-only access to instruction memory location 15
-        pub const INSTR_MEM15 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x84);
-
-        /// address: 0x50200088
-        /// Write-only access to instruction memory location 16
-        pub const INSTR_MEM16 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x88);
-
-        /// address: 0x5020008c
-        /// Write-only access to instruction memory location 17
-        pub const INSTR_MEM17 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x8c);
-
-        /// address: 0x50200090
-        /// Write-only access to instruction memory location 18
-        pub const INSTR_MEM18 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x90);
-
-        /// address: 0x50200094
-        /// Write-only access to instruction memory location 19
-        pub const INSTR_MEM19 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x94);
-
-        /// address: 0x50200098
-        /// Write-only access to instruction memory location 20
-        pub const INSTR_MEM20 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x98);
-
-        /// address: 0x5020009c
-        /// Write-only access to instruction memory location 21
-        pub const INSTR_MEM21 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x9c);
-
-        /// address: 0x502000a0
-        /// Write-only access to instruction memory location 22
-        pub const INSTR_MEM22 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa0);
-
-        /// address: 0x502000a4
-        /// Write-only access to instruction memory location 23
-        pub const INSTR_MEM23 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa4);
-
-        /// address: 0x502000a8
-        /// Write-only access to instruction memory location 24
-        pub const INSTR_MEM24 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa8);
-
-        /// address: 0x502000ac
-        /// Write-only access to instruction memory location 25
-        pub const INSTR_MEM25 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xac);
-
-        /// address: 0x502000b0
-        /// Write-only access to instruction memory location 26
-        pub const INSTR_MEM26 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb0);
-
-        /// address: 0x502000b4
-        /// Write-only access to instruction memory location 27
-        pub const INSTR_MEM27 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb4);
-
-        /// address: 0x502000b8
-        /// Write-only access to instruction memory location 28
-        pub const INSTR_MEM28 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb8);
-
-        /// address: 0x502000bc
-        /// Write-only access to instruction memory location 29
-        pub const INSTR_MEM29 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xbc);
-
-        /// address: 0x502000c0
-        /// Write-only access to instruction memory location 30
-        pub const INSTR_MEM30 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc0);
-
-        /// address: 0x502000c4
-        /// Write-only access to instruction memory location 31
-        pub const INSTR_MEM31 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc4);
-
-        /// address: 0x502000c8
-        /// Clock divisor register for state machine 0\n
-        /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-        pub const SM0_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Fractional part of clock divisor
-            FRAC: u8,
-            /// Effective frequency is sysclk/(int + frac/256).\n
-            /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-            INT: u16,
-        }), base_address + 0xc8);
-
-        /// address: 0x502000cc
-        /// Execution/behavioural settings for state machine 0
-        pub const SM0_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Comparison level for the MOV x, STATUS instruction
-            STATUS_N: u4,
-            /// Comparison used for the MOV x, STATUS instruction.
-            STATUS_SEL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// After reaching wrap_top, execution is wrapped to this address.
-            WRAP_BOTTOM: u5,
-            /// After reaching this address, execution is wrapped to wrap_bottom.\n
-            /// If the instruction is a jump, and the jump condition is true, the jump takes
-            /// priority.
-            WRAP_TOP: u5,
-            /// Continuously assert the most recent OUT/SET to the pins
-            OUT_STICKY: u1,
-            /// If 1, use a bit of OUT data as an auxiliary write enable\n
-            /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-            /// deassert the latest pin write. This can create useful masking/override
-            /// behaviour\n
-            /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-            INLINE_OUT_EN: u1,
-            /// Which data bit to use for inline OUT enable
-            OUT_EN_SEL: u5,
-            /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-            JMP_PIN: u5,
-            /// If 1, side-set data is asserted to pin directions, instead of pin values
-            SIDE_PINDIR: u1,
-            /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set
-            /// enable, rather than a side-set data bit. This allows instructions to perform
-            /// side-set optionally, rather than on every instruction, but the maximum possible
-            /// side-set width is reduced from 5 to 4. Note that the value of
-            /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-            SIDE_EN: u1,
-            /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state
-            /// machine. Will clear to 0 once this instruction completes.
-            EXEC_STALLED: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x502000d0
-        /// Control behaviour of the input/output shift registers for state machine 0
-        pub const SM0_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            /// Push automatically when the input shift register is filled, i.e. on an IN
-            /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-            AUTOPUSH: u1,
-            /// Pull automatically when the output shift register is emptied, i.e. on or
-            /// following an OUT instruction which causes the output shift counter to reach or
-            /// exceed PULL_THRESH.
-            AUTOPULL: u1,
-            /// 1 = shift input shift register to right (data enters from left). 0 = to left.
-            IN_SHIFTDIR: u1,
-            /// 1 = shift out of output shift register to right. 0 = to left.
-            OUT_SHIFTDIR: u1,
-            /// Number of bits shifted into ISR before autopush, or conditional push (PUSH
-            /// IFFULL), will take place.\n
-            /// Write 0 for value of 32.
-            PUSH_THRESH: u5,
-            /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL
-            /// IFEMPTY), will take place.\n
-            /// Write 0 for value of 32.
-            PULL_THRESH: u5,
-            /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-            /// RX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_TX: u1,
-            /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-            /// TX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_RX: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x502000d4
-        /// Current instruction address of state machine 0
-        pub const SM0_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd4);
-
-        /// address: 0x502000d8
-        /// Read to see the instruction currently addressed by state machine 0's program
-        /// counter\n
-        /// Write to execute an instruction immediately (including jumps) and then resume
-        /// execution.
-        pub const SM0_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xd8);
-
-        /// address: 0x502000dc
-        /// State machine pin control
-        pub const SM0_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV
-            /// PINS instruction. The data written to this pin will always be the
-            /// least-significant bit of the OUT or MOV data.
-            OUT_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS
-            /// instruction. The data written to this pin is the least-significant bit of the
-            /// SET data.
-            SET_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs
-            /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT)
-            /// are used for side-set data, with the remaining LSBs used for delay. The
-            /// least-significant bit of the side-set portion is the bit written to this pin,
-            /// with more-significant bits written to higher-numbered pins.
-            SIDESET_BASE: u5,
-            /// The pin which is mapped to the least-significant bit of a state machine's IN
-            /// data bus. Higher-numbered pins are mapped to consecutively more-significant data
-            /// bits, with a modulo of 32 applied to pin number.
-            IN_BASE: u5,
-            /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction.
-            /// In the range 0 to 32 inclusive.
-            OUT_COUNT: u6,
-            /// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-            SET_COUNT: u3,
-            /// The number of MSBs of the Delay/Side-set instruction field which are used for
-            /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits,
-            /// no side-set) and maximum of 5 (all side-set, no delay).
-            SIDESET_COUNT: u3,
-        }), base_address + 0xdc);
-
-        /// address: 0x502000e0
-        /// Clock divisor register for state machine 1\n
-        /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-        pub const SM1_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Fractional part of clock divisor
-            FRAC: u8,
-            /// Effective frequency is sysclk/(int + frac/256).\n
-            /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-            INT: u16,
-        }), base_address + 0xe0);
-
-        /// address: 0x502000e4
-        /// Execution/behavioural settings for state machine 1
-        pub const SM1_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Comparison level for the MOV x, STATUS instruction
-            STATUS_N: u4,
-            /// Comparison used for the MOV x, STATUS instruction.
-            STATUS_SEL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// After reaching wrap_top, execution is wrapped to this address.
-            WRAP_BOTTOM: u5,
-            /// After reaching this address, execution is wrapped to wrap_bottom.\n
-            /// If the instruction is a jump, and the jump condition is true, the jump takes
-            /// priority.
-            WRAP_TOP: u5,
-            /// Continuously assert the most recent OUT/SET to the pins
-            OUT_STICKY: u1,
-            /// If 1, use a bit of OUT data as an auxiliary write enable\n
-            /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-            /// deassert the latest pin write. This can create useful masking/override
-            /// behaviour\n
-            /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-            INLINE_OUT_EN: u1,
-            /// Which data bit to use for inline OUT enable
-            OUT_EN_SEL: u5,
-            /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-            JMP_PIN: u5,
-            /// If 1, side-set data is asserted to pin directions, instead of pin values
-            SIDE_PINDIR: u1,
-            /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set
-            /// enable, rather than a side-set data bit. This allows instructions to perform
-            /// side-set optionally, rather than on every instruction, but the maximum possible
-            /// side-set width is reduced from 5 to 4. Note that the value of
-            /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-            SIDE_EN: u1,
-            /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state
-            /// machine. Will clear to 0 once this instruction completes.
-            EXEC_STALLED: u1,
-        }), base_address + 0xe4);
-
-        /// address: 0x502000e8
-        /// Control behaviour of the input/output shift registers for state machine 1
-        pub const SM1_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            /// Push automatically when the input shift register is filled, i.e. on an IN
-            /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-            AUTOPUSH: u1,
-            /// Pull automatically when the output shift register is emptied, i.e. on or
-            /// following an OUT instruction which causes the output shift counter to reach or
-            /// exceed PULL_THRESH.
-            AUTOPULL: u1,
-            /// 1 = shift input shift register to right (data enters from left). 0 = to left.
-            IN_SHIFTDIR: u1,
-            /// 1 = shift out of output shift register to right. 0 = to left.
-            OUT_SHIFTDIR: u1,
-            /// Number of bits shifted into ISR before autopush, or conditional push (PUSH
-            /// IFFULL), will take place.\n
-            /// Write 0 for value of 32.
-            PUSH_THRESH: u5,
-            /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL
-            /// IFEMPTY), will take place.\n
-            /// Write 0 for value of 32.
-            PULL_THRESH: u5,
-            /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-            /// RX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_TX: u1,
-            /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-            /// TX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_RX: u1,
-        }), base_address + 0xe8);
-
-        /// address: 0x502000ec
-        /// Current instruction address of state machine 1
-        pub const SM1_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xec);
-
-        /// address: 0x502000f0
-        /// Read to see the instruction currently addressed by state machine 1's program
-        /// counter\n
-        /// Write to execute an instruction immediately (including jumps) and then resume
-        /// execution.
-        pub const SM1_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xf0);
-
-        /// address: 0x502000f4
-        /// State machine pin control
-        pub const SM1_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV
-            /// PINS instruction. The data written to this pin will always be the
-            /// least-significant bit of the OUT or MOV data.
-            OUT_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS
-            /// instruction. The data written to this pin is the least-significant bit of the
-            /// SET data.
-            SET_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs
-            /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT)
-            /// are used for side-set data, with the remaining LSBs used for delay. The
-            /// least-significant bit of the side-set portion is the bit written to this pin,
-            /// with more-significant bits written to higher-numbered pins.
-            SIDESET_BASE: u5,
-            /// The pin which is mapped to the least-significant bit of a state machine's IN
-            /// data bus. Higher-numbered pins are mapped to consecutively more-significant data
-            /// bits, with a modulo of 32 applied to pin number.
-            IN_BASE: u5,
-            /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction.
-            /// In the range 0 to 32 inclusive.
-            OUT_COUNT: u6,
-            /// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-            SET_COUNT: u3,
-            /// The number of MSBs of the Delay/Side-set instruction field which are used for
-            /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits,
-            /// no side-set) and maximum of 5 (all side-set, no delay).
-            SIDESET_COUNT: u3,
-        }), base_address + 0xf4);
-
-        /// address: 0x502000f8
-        /// Clock divisor register for state machine 2\n
-        /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-        pub const SM2_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Fractional part of clock divisor
-            FRAC: u8,
-            /// Effective frequency is sysclk/(int + frac/256).\n
-            /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-            INT: u16,
-        }), base_address + 0xf8);
-
-        /// address: 0x502000fc
-        /// Execution/behavioural settings for state machine 2
-        pub const SM2_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Comparison level for the MOV x, STATUS instruction
-            STATUS_N: u4,
-            /// Comparison used for the MOV x, STATUS instruction.
-            STATUS_SEL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// After reaching wrap_top, execution is wrapped to this address.
-            WRAP_BOTTOM: u5,
-            /// After reaching this address, execution is wrapped to wrap_bottom.\n
-            /// If the instruction is a jump, and the jump condition is true, the jump takes
-            /// priority.
-            WRAP_TOP: u5,
-            /// Continuously assert the most recent OUT/SET to the pins
-            OUT_STICKY: u1,
-            /// If 1, use a bit of OUT data as an auxiliary write enable\n
-            /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-            /// deassert the latest pin write. This can create useful masking/override
-            /// behaviour\n
-            /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-            INLINE_OUT_EN: u1,
-            /// Which data bit to use for inline OUT enable
-            OUT_EN_SEL: u5,
-            /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-            JMP_PIN: u5,
-            /// If 1, side-set data is asserted to pin directions, instead of pin values
-            SIDE_PINDIR: u1,
-            /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set
-            /// enable, rather than a side-set data bit. This allows instructions to perform
-            /// side-set optionally, rather than on every instruction, but the maximum possible
-            /// side-set width is reduced from 5 to 4. Note that the value of
-            /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-            SIDE_EN: u1,
-            /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state
-            /// machine. Will clear to 0 once this instruction completes.
-            EXEC_STALLED: u1,
-        }), base_address + 0xfc);
-
-        /// address: 0x50200100
-        /// Control behaviour of the input/output shift registers for state machine 2
-        pub const SM2_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            /// Push automatically when the input shift register is filled, i.e. on an IN
-            /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-            AUTOPUSH: u1,
-            /// Pull automatically when the output shift register is emptied, i.e. on or
-            /// following an OUT instruction which causes the output shift counter to reach or
-            /// exceed PULL_THRESH.
-            AUTOPULL: u1,
-            /// 1 = shift input shift register to right (data enters from left). 0 = to left.
-            IN_SHIFTDIR: u1,
-            /// 1 = shift out of output shift register to right. 0 = to left.
-            OUT_SHIFTDIR: u1,
-            /// Number of bits shifted into ISR before autopush, or conditional push (PUSH
-            /// IFFULL), will take place.\n
-            /// Write 0 for value of 32.
-            PUSH_THRESH: u5,
-            /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL
-            /// IFEMPTY), will take place.\n
-            /// Write 0 for value of 32.
-            PULL_THRESH: u5,
-            /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-            /// RX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_TX: u1,
-            /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-            /// TX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_RX: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x50200104
-        /// Current instruction address of state machine 2
-        pub const SM2_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x104);
-
-        /// address: 0x50200108
-        /// Read to see the instruction currently addressed by state machine 2's program
-        /// counter\n
-        /// Write to execute an instruction immediately (including jumps) and then resume
-        /// execution.
-        pub const SM2_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x108);
-
-        /// address: 0x5020010c
-        /// State machine pin control
-        pub const SM2_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV
-            /// PINS instruction. The data written to this pin will always be the
-            /// least-significant bit of the OUT or MOV data.
-            OUT_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS
-            /// instruction. The data written to this pin is the least-significant bit of the
-            /// SET data.
-            SET_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs
-            /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT)
-            /// are used for side-set data, with the remaining LSBs used for delay. The
-            /// least-significant bit of the side-set portion is the bit written to this pin,
-            /// with more-significant bits written to higher-numbered pins.
-            SIDESET_BASE: u5,
-            /// The pin which is mapped to the least-significant bit of a state machine's IN
-            /// data bus. Higher-numbered pins are mapped to consecutively more-significant data
-            /// bits, with a modulo of 32 applied to pin number.
-            IN_BASE: u5,
-            /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction.
-            /// In the range 0 to 32 inclusive.
-            OUT_COUNT: u6,
-            /// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-            SET_COUNT: u3,
-            /// The number of MSBs of the Delay/Side-set instruction field which are used for
-            /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits,
-            /// no side-set) and maximum of 5 (all side-set, no delay).
-            SIDESET_COUNT: u3,
-        }), base_address + 0x10c);
-
-        /// address: 0x50200110
-        /// Clock divisor register for state machine 3\n
-        /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-        pub const SM3_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Fractional part of clock divisor
-            FRAC: u8,
-            /// Effective frequency is sysclk/(int + frac/256).\n
-            /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-            INT: u16,
-        }), base_address + 0x110);
-
-        /// address: 0x50200114
-        /// Execution/behavioural settings for state machine 3
-        pub const SM3_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Comparison level for the MOV x, STATUS instruction
-            STATUS_N: u4,
-            /// Comparison used for the MOV x, STATUS instruction.
-            STATUS_SEL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// After reaching wrap_top, execution is wrapped to this address.
-            WRAP_BOTTOM: u5,
-            /// After reaching this address, execution is wrapped to wrap_bottom.\n
-            /// If the instruction is a jump, and the jump condition is true, the jump takes
-            /// priority.
-            WRAP_TOP: u5,
-            /// Continuously assert the most recent OUT/SET to the pins
-            OUT_STICKY: u1,
-            /// If 1, use a bit of OUT data as an auxiliary write enable\n
-            /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-            /// deassert the latest pin write. This can create useful masking/override
-            /// behaviour\n
-            /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-            INLINE_OUT_EN: u1,
-            /// Which data bit to use for inline OUT enable
-            OUT_EN_SEL: u5,
-            /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-            JMP_PIN: u5,
-            /// If 1, side-set data is asserted to pin directions, instead of pin values
-            SIDE_PINDIR: u1,
-            /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set
-            /// enable, rather than a side-set data bit. This allows instructions to perform
-            /// side-set optionally, rather than on every instruction, but the maximum possible
-            /// side-set width is reduced from 5 to 4. Note that the value of
-            /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-            SIDE_EN: u1,
-            /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state
-            /// machine. Will clear to 0 once this instruction completes.
-            EXEC_STALLED: u1,
-        }), base_address + 0x114);
-
-        /// address: 0x50200118
-        /// Control behaviour of the input/output shift registers for state machine 3
-        pub const SM3_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            /// Push automatically when the input shift register is filled, i.e. on an IN
-            /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-            AUTOPUSH: u1,
-            /// Pull automatically when the output shift register is emptied, i.e. on or
-            /// following an OUT instruction which causes the output shift counter to reach or
-            /// exceed PULL_THRESH.
-            AUTOPULL: u1,
-            /// 1 = shift input shift register to right (data enters from left). 0 = to left.
-            IN_SHIFTDIR: u1,
-            /// 1 = shift out of output shift register to right. 0 = to left.
-            OUT_SHIFTDIR: u1,
-            /// Number of bits shifted into ISR before autopush, or conditional push (PUSH
-            /// IFFULL), will take place.\n
-            /// Write 0 for value of 32.
-            PUSH_THRESH: u5,
-            /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL
-            /// IFEMPTY), will take place.\n
-            /// Write 0 for value of 32.
-            PULL_THRESH: u5,
-            /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-            /// RX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_TX: u1,
-            /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-            /// TX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_RX: u1,
-        }), base_address + 0x118);
-
-        /// address: 0x5020011c
-        /// Current instruction address of state machine 3
-        pub const SM3_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x11c);
-
-        /// address: 0x50200120
-        /// Read to see the instruction currently addressed by state machine 3's program
-        /// counter\n
-        /// Write to execute an instruction immediately (including jumps) and then resume
-        /// execution.
-        pub const SM3_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x120);
-
-        /// address: 0x50200124
-        /// State machine pin control
-        pub const SM3_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV
-            /// PINS instruction. The data written to this pin will always be the
-            /// least-significant bit of the OUT or MOV data.
-            OUT_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS
-            /// instruction. The data written to this pin is the least-significant bit of the
-            /// SET data.
-            SET_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs
-            /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT)
-            /// are used for side-set data, with the remaining LSBs used for delay. The
-            /// least-significant bit of the side-set portion is the bit written to this pin,
-            /// with more-significant bits written to higher-numbered pins.
-            SIDESET_BASE: u5,
-            /// The pin which is mapped to the least-significant bit of a state machine's IN
-            /// data bus. Higher-numbered pins are mapped to consecutively more-significant data
-            /// bits, with a modulo of 32 applied to pin number.
-            IN_BASE: u5,
-            /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction.
-            /// In the range 0 to 32 inclusive.
-            OUT_COUNT: u6,
-            /// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-            SET_COUNT: u3,
-            /// The number of MSBs of the Delay/Side-set instruction field which are used for
-            /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits,
-            /// no side-set) and maximum of 5 (all side-set, no delay).
-            SIDESET_COUNT: u3,
-        }), base_address + 0x124);
-
-        /// address: 0x50200128
-        /// Raw Interrupts
-        pub const INTR = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x128);
-
-        /// address: 0x5020012c
-        /// Interrupt Enable for irq0
-        pub const IRQ0_INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x12c);
-
-        /// address: 0x50200130
-        /// Interrupt Force for irq0
-        pub const IRQ0_INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x130);
-
-        /// address: 0x50200134
-        /// Interrupt status after masking & forcing for irq0
-        pub const IRQ0_INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x134);
-
-        /// address: 0x50200138
-        /// Interrupt Enable for irq1
-        pub const IRQ1_INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x138);
-
-        /// address: 0x5020013c
-        /// Interrupt Force for irq1
-        pub const IRQ1_INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x13c);
-
-        /// address: 0x50200140
-        /// Interrupt status after masking & forcing for irq1
-        pub const IRQ1_INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x140);
-    };
-    pub const PIO1 = struct {
-        pub const base_address = 0x50300000;
-
-        /// address: 0x50300000
-        /// PIO control register
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable/disable each of the four state machines by writing 1/0 to each of these
-            /// four bits. When disabled, a state machine will cease executing instructions,
-            /// except those written directly to SMx_INSTR by the system. Multiple bits can be
-            /// set/cleared at once to run/halt multiple state machines simultaneously.
-            SM_ENABLE: u4,
-            /// Write 1 to instantly clear internal SM state which may be otherwise difficult to
-            /// access and will affect future execution.\n\n
-            /// Specifically, the following are cleared: input and output shift counters; the
-            /// contents of the input shift register; the delay counter; the waiting-on-IRQ
-            /// state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any
-            /// pin write left asserted due to OUT_STICKY.
-            SM_RESTART: u4,
-            /// Restart a state machine's clock divider from an initial phase of 0. Clock
-            /// dividers are free-running, so once started, their output (including fractional
-            /// jitter) is completely determined by the integer/fractional divisor configured in
-            /// SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor
-            /// are restarted simultaneously, by writing multiple 1 bits to this field, the
-            /// execution clocks of those state machines will run in precise lockstep.\n\n
-            /// Note that setting/clearing SM_ENABLE does not stop the clock divider from
-            /// running, so once multiple state machines' clocks are synchronised, it is safe to
-            /// disable/reenable a state machine, whilst keeping the clock dividers in sync.\n\n
-            /// Note also that CLKDIV_RESTART can be written to whilst the state machine is
-            /// running, and this is useful to resynchronise clock dividers after the divisors
-            /// (SMx_CLKDIV) have been changed on-the-fly.
-            CLKDIV_RESTART: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x0);
-
-        /// address: 0x50300004
-        /// FIFO status register
-        pub const FSTAT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State machine RX FIFO is full
-            RXFULL: u4,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// State machine RX FIFO is empty
-            RXEMPTY: u4,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// State machine TX FIFO is full
-            TXFULL: u4,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            /// State machine TX FIFO is empty
-            TXEMPTY: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-        }), base_address + 0x4);
-
-        /// address: 0x50300008
-        /// FIFO debug register
-        pub const FDEBUG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with
-            /// autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO
-            /// took place, in which case the state machine has dropped data. Write 1 to clear.
-            RXSTALL: u4,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            /// RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to
-            /// clear. Note that read-on-empty does not perturb the state of the FIFO in any
-            /// way, but the data returned by reading from an empty FIFO is undefined, so this
-            /// flag generally only becomes set due to some kind of software error.
-            RXUNDER: u4,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to
-            /// clear. Note that write-on-full does not alter the state or contents of the FIFO
-            /// in any way, but the data that the system attempted to write is dropped, so if
-            /// this flag is set, your software has quite likely dropped some data on the floor.
-            TXOVER: u4,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            /// State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT
-            /// with autopull enabled. Write 1 to clear.
-            TXSTALL: u4,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-        }), base_address + 0x8);
-
-        /// address: 0x5030000c
-        /// FIFO levels
-        pub const FLEVEL = @intToPtr(*volatile Mmio(32, packed struct {
-            TX0: u4,
-            RX0: u4,
-            TX1: u4,
-            RX1: u4,
-            TX2: u4,
-            RX2: u4,
-            TX3: u4,
-            RX3: u4,
-        }), base_address + 0xc);
-
-        /// address: 0x50300010
-        /// Direct write access to the TX FIFO for this state machine. Each write pushes one
-        /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO
-        /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-        pub const TXF0 = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x50300014
-        /// Direct write access to the TX FIFO for this state machine. Each write pushes one
-        /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO
-        /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-        pub const TXF1 = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x50300018
-        /// Direct write access to the TX FIFO for this state machine. Each write pushes one
-        /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO
-        /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-        pub const TXF2 = @intToPtr(*volatile u32, base_address + 0x18);
-
-        /// address: 0x5030001c
-        /// Direct write access to the TX FIFO for this state machine. Each write pushes one
-        /// word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO
-        /// state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-        pub const TXF3 = @intToPtr(*volatile u32, base_address + 0x1c);
-
-        /// address: 0x50300020
-        /// Direct read access to the RX FIFO for this state machine. Each read pops one
-        /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the
-        /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The
-        /// data returned to the system on a read from an empty FIFO is undefined.
-        pub const RXF0 = @intToPtr(*volatile u32, base_address + 0x20);
-
-        /// address: 0x50300024
-        /// Direct read access to the RX FIFO for this state machine. Each read pops one
-        /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the
-        /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The
-        /// data returned to the system on a read from an empty FIFO is undefined.
-        pub const RXF1 = @intToPtr(*volatile u32, base_address + 0x24);
-
-        /// address: 0x50300028
-        /// Direct read access to the RX FIFO for this state machine. Each read pops one
-        /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the
-        /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The
-        /// data returned to the system on a read from an empty FIFO is undefined.
-        pub const RXF2 = @intToPtr(*volatile u32, base_address + 0x28);
-
-        /// address: 0x5030002c
-        /// Direct read access to the RX FIFO for this state machine. Each read pops one
-        /// word from the FIFO. Attempting to read from an empty FIFO has no effect on the
-        /// FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The
-        /// data returned to the system on a read from an empty FIFO is undefined.
-        pub const RXF3 = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x50300030
-        /// State machine IRQ flags register. Write 1 to clear. There are 8 state machine
-        /// IRQ flags, which can be set, cleared, and waited on by the state machines.
-        /// There's no fixed association between flags and state machines -- any state
-        /// machine can use any flag.\n\n
-        /// Any of the 8 flags can be used for timing synchronisation between state
-        /// machines, using IRQ and WAIT instructions. The lower four of these flags are
-        /// also routed out to system-level interrupt requests, alongside FIFO status
-        /// interrupts -- see e.g. IRQ0_INTE.
-        pub const IRQ = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x30);
-
-        /// address: 0x50300034
-        /// Writing a 1 to each of these bits will forcibly assert the corresponding IRQ.
-        /// Note this is different to the INTF register: writing here affects PIO internal
-        /// state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and
-        /// is not visible to the state machines.
-        pub const IRQ_FORCE = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x34);
-
-        /// address: 0x50300038
-        /// There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic
-        /// from metastabilities. This increases input delay, and for fast synchronous IO
-        /// (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this
-        /// register corresponds to one GPIO.\n
-        /// 0 -> input is synchronized (default)\n
-        /// 1 -> synchronizer is bypassed\n
-        /// If in doubt, leave this register as all zeroes.
-        pub const INPUT_SYNC_BYPASS = @intToPtr(*volatile u32, base_address + 0x38);
-
-        /// address: 0x5030003c
-        /// Read to sample the pad output values PIO is currently driving to the GPIOs. On
-        /// RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.
-        pub const DBG_PADOUT = @intToPtr(*volatile u32, base_address + 0x3c);
-
-        /// address: 0x50300040
-        /// Read to sample the pad output enables (direction) PIO is currently driving to
-        /// the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are
-        /// hardwired to 0.
-        pub const DBG_PADOE = @intToPtr(*volatile u32, base_address + 0x40);
-
-        /// address: 0x50300044
-        /// The PIO hardware has some free parameters that may vary between chip products.\n
-        /// These should be provided in the chip datasheet, but are also exposed here.
-        pub const DBG_CFGINFO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The depth of the state machine TX/RX FIFOs, measured in words.\n
-            /// Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double\n
-            /// this depth.
-            FIFO_DEPTH: u6,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// The number of state machines this PIO instance is equipped with.
-            SM_COUNT: u4,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            /// The size of the instruction memory, measured in units of one instruction
-            IMEM_SIZE: u6,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-        }), base_address + 0x44);
-
-        /// address: 0x50300048
-        /// Write-only access to instruction memory location 0
-        pub const INSTR_MEM0 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x48);
-
-        /// address: 0x5030004c
-        /// Write-only access to instruction memory location 1
-        pub const INSTR_MEM1 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x4c);
-
-        /// address: 0x50300050
-        /// Write-only access to instruction memory location 2
-        pub const INSTR_MEM2 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x50);
-
-        /// address: 0x50300054
-        /// Write-only access to instruction memory location 3
-        pub const INSTR_MEM3 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x54);
-
-        /// address: 0x50300058
-        /// Write-only access to instruction memory location 4
-        pub const INSTR_MEM4 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x58);
-
-        /// address: 0x5030005c
-        /// Write-only access to instruction memory location 5
-        pub const INSTR_MEM5 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x5c);
-
-        /// address: 0x50300060
-        /// Write-only access to instruction memory location 6
-        pub const INSTR_MEM6 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x60);
-
-        /// address: 0x50300064
-        /// Write-only access to instruction memory location 7
-        pub const INSTR_MEM7 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x64);
-
-        /// address: 0x50300068
-        /// Write-only access to instruction memory location 8
-        pub const INSTR_MEM8 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x68);
-
-        /// address: 0x5030006c
-        /// Write-only access to instruction memory location 9
-        pub const INSTR_MEM9 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x6c);
-
-        /// address: 0x50300070
-        /// Write-only access to instruction memory location 10
-        pub const INSTR_MEM10 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x70);
-
-        /// address: 0x50300074
-        /// Write-only access to instruction memory location 11
-        pub const INSTR_MEM11 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x74);
-
-        /// address: 0x50300078
-        /// Write-only access to instruction memory location 12
-        pub const INSTR_MEM12 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x78);
-
-        /// address: 0x5030007c
-        /// Write-only access to instruction memory location 13
-        pub const INSTR_MEM13 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x7c);
-
-        /// address: 0x50300080
-        /// Write-only access to instruction memory location 14
-        pub const INSTR_MEM14 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x80);
-
-        /// address: 0x50300084
-        /// Write-only access to instruction memory location 15
-        pub const INSTR_MEM15 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x84);
-
-        /// address: 0x50300088
-        /// Write-only access to instruction memory location 16
-        pub const INSTR_MEM16 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x88);
-
-        /// address: 0x5030008c
-        /// Write-only access to instruction memory location 17
-        pub const INSTR_MEM17 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x8c);
-
-        /// address: 0x50300090
-        /// Write-only access to instruction memory location 18
-        pub const INSTR_MEM18 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x90);
-
-        /// address: 0x50300094
-        /// Write-only access to instruction memory location 19
-        pub const INSTR_MEM19 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x94);
-
-        /// address: 0x50300098
-        /// Write-only access to instruction memory location 20
-        pub const INSTR_MEM20 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x98);
-
-        /// address: 0x5030009c
-        /// Write-only access to instruction memory location 21
-        pub const INSTR_MEM21 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x9c);
-
-        /// address: 0x503000a0
-        /// Write-only access to instruction memory location 22
-        pub const INSTR_MEM22 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa0);
-
-        /// address: 0x503000a4
-        /// Write-only access to instruction memory location 23
-        pub const INSTR_MEM23 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa4);
-
-        /// address: 0x503000a8
-        /// Write-only access to instruction memory location 24
-        pub const INSTR_MEM24 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xa8);
-
-        /// address: 0x503000ac
-        /// Write-only access to instruction memory location 25
-        pub const INSTR_MEM25 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xac);
-
-        /// address: 0x503000b0
-        /// Write-only access to instruction memory location 26
-        pub const INSTR_MEM26 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb0);
-
-        /// address: 0x503000b4
-        /// Write-only access to instruction memory location 27
-        pub const INSTR_MEM27 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb4);
-
-        /// address: 0x503000b8
-        /// Write-only access to instruction memory location 28
-        pub const INSTR_MEM28 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xb8);
-
-        /// address: 0x503000bc
-        /// Write-only access to instruction memory location 29
-        pub const INSTR_MEM29 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xbc);
-
-        /// address: 0x503000c0
-        /// Write-only access to instruction memory location 30
-        pub const INSTR_MEM30 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc0);
-
-        /// address: 0x503000c4
-        /// Write-only access to instruction memory location 31
-        pub const INSTR_MEM31 = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xc4);
-
-        /// address: 0x503000c8
-        /// Clock divisor register for state machine 0\n
-        /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-        pub const SM0_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Fractional part of clock divisor
-            FRAC: u8,
-            /// Effective frequency is sysclk/(int + frac/256).\n
-            /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-            INT: u16,
-        }), base_address + 0xc8);
-
-        /// address: 0x503000cc
-        /// Execution/behavioural settings for state machine 0
-        pub const SM0_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Comparison level for the MOV x, STATUS instruction
-            STATUS_N: u4,
-            /// Comparison used for the MOV x, STATUS instruction.
-            STATUS_SEL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// After reaching wrap_top, execution is wrapped to this address.
-            WRAP_BOTTOM: u5,
-            /// After reaching this address, execution is wrapped to wrap_bottom.\n
-            /// If the instruction is a jump, and the jump condition is true, the jump takes
-            /// priority.
-            WRAP_TOP: u5,
-            /// Continuously assert the most recent OUT/SET to the pins
-            OUT_STICKY: u1,
-            /// If 1, use a bit of OUT data as an auxiliary write enable\n
-            /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-            /// deassert the latest pin write. This can create useful masking/override
-            /// behaviour\n
-            /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-            INLINE_OUT_EN: u1,
-            /// Which data bit to use for inline OUT enable
-            OUT_EN_SEL: u5,
-            /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-            JMP_PIN: u5,
-            /// If 1, side-set data is asserted to pin directions, instead of pin values
-            SIDE_PINDIR: u1,
-            /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set
-            /// enable, rather than a side-set data bit. This allows instructions to perform
-            /// side-set optionally, rather than on every instruction, but the maximum possible
-            /// side-set width is reduced from 5 to 4. Note that the value of
-            /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-            SIDE_EN: u1,
-            /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state
-            /// machine. Will clear to 0 once this instruction completes.
-            EXEC_STALLED: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x503000d0
-        /// Control behaviour of the input/output shift registers for state machine 0
-        pub const SM0_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            /// Push automatically when the input shift register is filled, i.e. on an IN
-            /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-            AUTOPUSH: u1,
-            /// Pull automatically when the output shift register is emptied, i.e. on or
-            /// following an OUT instruction which causes the output shift counter to reach or
-            /// exceed PULL_THRESH.
-            AUTOPULL: u1,
-            /// 1 = shift input shift register to right (data enters from left). 0 = to left.
-            IN_SHIFTDIR: u1,
-            /// 1 = shift out of output shift register to right. 0 = to left.
-            OUT_SHIFTDIR: u1,
-            /// Number of bits shifted into ISR before autopush, or conditional push (PUSH
-            /// IFFULL), will take place.\n
-            /// Write 0 for value of 32.
-            PUSH_THRESH: u5,
-            /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL
-            /// IFEMPTY), will take place.\n
-            /// Write 0 for value of 32.
-            PULL_THRESH: u5,
-            /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-            /// RX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_TX: u1,
-            /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-            /// TX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_RX: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x503000d4
-        /// Current instruction address of state machine 0
-        pub const SM0_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd4);
-
-        /// address: 0x503000d8
-        /// Read to see the instruction currently addressed by state machine 0's program
-        /// counter\n
-        /// Write to execute an instruction immediately (including jumps) and then resume
-        /// execution.
-        pub const SM0_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xd8);
-
-        /// address: 0x503000dc
-        /// State machine pin control
-        pub const SM0_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV
-            /// PINS instruction. The data written to this pin will always be the
-            /// least-significant bit of the OUT or MOV data.
-            OUT_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS
-            /// instruction. The data written to this pin is the least-significant bit of the
-            /// SET data.
-            SET_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs
-            /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT)
-            /// are used for side-set data, with the remaining LSBs used for delay. The
-            /// least-significant bit of the side-set portion is the bit written to this pin,
-            /// with more-significant bits written to higher-numbered pins.
-            SIDESET_BASE: u5,
-            /// The pin which is mapped to the least-significant bit of a state machine's IN
-            /// data bus. Higher-numbered pins are mapped to consecutively more-significant data
-            /// bits, with a modulo of 32 applied to pin number.
-            IN_BASE: u5,
-            /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction.
-            /// In the range 0 to 32 inclusive.
-            OUT_COUNT: u6,
-            /// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-            SET_COUNT: u3,
-            /// The number of MSBs of the Delay/Side-set instruction field which are used for
-            /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits,
-            /// no side-set) and maximum of 5 (all side-set, no delay).
-            SIDESET_COUNT: u3,
-        }), base_address + 0xdc);
-
-        /// address: 0x503000e0
-        /// Clock divisor register for state machine 1\n
-        /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-        pub const SM1_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Fractional part of clock divisor
-            FRAC: u8,
-            /// Effective frequency is sysclk/(int + frac/256).\n
-            /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-            INT: u16,
-        }), base_address + 0xe0);
-
-        /// address: 0x503000e4
-        /// Execution/behavioural settings for state machine 1
-        pub const SM1_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Comparison level for the MOV x, STATUS instruction
-            STATUS_N: u4,
-            /// Comparison used for the MOV x, STATUS instruction.
-            STATUS_SEL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// After reaching wrap_top, execution is wrapped to this address.
-            WRAP_BOTTOM: u5,
-            /// After reaching this address, execution is wrapped to wrap_bottom.\n
-            /// If the instruction is a jump, and the jump condition is true, the jump takes
-            /// priority.
-            WRAP_TOP: u5,
-            /// Continuously assert the most recent OUT/SET to the pins
-            OUT_STICKY: u1,
-            /// If 1, use a bit of OUT data as an auxiliary write enable\n
-            /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-            /// deassert the latest pin write. This can create useful masking/override
-            /// behaviour\n
-            /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-            INLINE_OUT_EN: u1,
-            /// Which data bit to use for inline OUT enable
-            OUT_EN_SEL: u5,
-            /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-            JMP_PIN: u5,
-            /// If 1, side-set data is asserted to pin directions, instead of pin values
-            SIDE_PINDIR: u1,
-            /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set
-            /// enable, rather than a side-set data bit. This allows instructions to perform
-            /// side-set optionally, rather than on every instruction, but the maximum possible
-            /// side-set width is reduced from 5 to 4. Note that the value of
-            /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-            SIDE_EN: u1,
-            /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state
-            /// machine. Will clear to 0 once this instruction completes.
-            EXEC_STALLED: u1,
-        }), base_address + 0xe4);
-
-        /// address: 0x503000e8
-        /// Control behaviour of the input/output shift registers for state machine 1
-        pub const SM1_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            /// Push automatically when the input shift register is filled, i.e. on an IN
-            /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-            AUTOPUSH: u1,
-            /// Pull automatically when the output shift register is emptied, i.e. on or
-            /// following an OUT instruction which causes the output shift counter to reach or
-            /// exceed PULL_THRESH.
-            AUTOPULL: u1,
-            /// 1 = shift input shift register to right (data enters from left). 0 = to left.
-            IN_SHIFTDIR: u1,
-            /// 1 = shift out of output shift register to right. 0 = to left.
-            OUT_SHIFTDIR: u1,
-            /// Number of bits shifted into ISR before autopush, or conditional push (PUSH
-            /// IFFULL), will take place.\n
-            /// Write 0 for value of 32.
-            PUSH_THRESH: u5,
-            /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL
-            /// IFEMPTY), will take place.\n
-            /// Write 0 for value of 32.
-            PULL_THRESH: u5,
-            /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-            /// RX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_TX: u1,
-            /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-            /// TX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_RX: u1,
-        }), base_address + 0xe8);
-
-        /// address: 0x503000ec
-        /// Current instruction address of state machine 1
-        pub const SM1_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xec);
-
-        /// address: 0x503000f0
-        /// Read to see the instruction currently addressed by state machine 1's program
-        /// counter\n
-        /// Write to execute an instruction immediately (including jumps) and then resume
-        /// execution.
-        pub const SM1_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0xf0);
-
-        /// address: 0x503000f4
-        /// State machine pin control
-        pub const SM1_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV
-            /// PINS instruction. The data written to this pin will always be the
-            /// least-significant bit of the OUT or MOV data.
-            OUT_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS
-            /// instruction. The data written to this pin is the least-significant bit of the
-            /// SET data.
-            SET_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs
-            /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT)
-            /// are used for side-set data, with the remaining LSBs used for delay. The
-            /// least-significant bit of the side-set portion is the bit written to this pin,
-            /// with more-significant bits written to higher-numbered pins.
-            SIDESET_BASE: u5,
-            /// The pin which is mapped to the least-significant bit of a state machine's IN
-            /// data bus. Higher-numbered pins are mapped to consecutively more-significant data
-            /// bits, with a modulo of 32 applied to pin number.
-            IN_BASE: u5,
-            /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction.
-            /// In the range 0 to 32 inclusive.
-            OUT_COUNT: u6,
-            /// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-            SET_COUNT: u3,
-            /// The number of MSBs of the Delay/Side-set instruction field which are used for
-            /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits,
-            /// no side-set) and maximum of 5 (all side-set, no delay).
-            SIDESET_COUNT: u3,
-        }), base_address + 0xf4);
-
-        /// address: 0x503000f8
-        /// Clock divisor register for state machine 2\n
-        /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-        pub const SM2_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Fractional part of clock divisor
-            FRAC: u8,
-            /// Effective frequency is sysclk/(int + frac/256).\n
-            /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-            INT: u16,
-        }), base_address + 0xf8);
-
-        /// address: 0x503000fc
-        /// Execution/behavioural settings for state machine 2
-        pub const SM2_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Comparison level for the MOV x, STATUS instruction
-            STATUS_N: u4,
-            /// Comparison used for the MOV x, STATUS instruction.
-            STATUS_SEL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// After reaching wrap_top, execution is wrapped to this address.
-            WRAP_BOTTOM: u5,
-            /// After reaching this address, execution is wrapped to wrap_bottom.\n
-            /// If the instruction is a jump, and the jump condition is true, the jump takes
-            /// priority.
-            WRAP_TOP: u5,
-            /// Continuously assert the most recent OUT/SET to the pins
-            OUT_STICKY: u1,
-            /// If 1, use a bit of OUT data as an auxiliary write enable\n
-            /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-            /// deassert the latest pin write. This can create useful masking/override
-            /// behaviour\n
-            /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-            INLINE_OUT_EN: u1,
-            /// Which data bit to use for inline OUT enable
-            OUT_EN_SEL: u5,
-            /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-            JMP_PIN: u5,
-            /// If 1, side-set data is asserted to pin directions, instead of pin values
-            SIDE_PINDIR: u1,
-            /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set
-            /// enable, rather than a side-set data bit. This allows instructions to perform
-            /// side-set optionally, rather than on every instruction, but the maximum possible
-            /// side-set width is reduced from 5 to 4. Note that the value of
-            /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-            SIDE_EN: u1,
-            /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state
-            /// machine. Will clear to 0 once this instruction completes.
-            EXEC_STALLED: u1,
-        }), base_address + 0xfc);
-
-        /// address: 0x50300100
-        /// Control behaviour of the input/output shift registers for state machine 2
-        pub const SM2_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            /// Push automatically when the input shift register is filled, i.e. on an IN
-            /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-            AUTOPUSH: u1,
-            /// Pull automatically when the output shift register is emptied, i.e. on or
-            /// following an OUT instruction which causes the output shift counter to reach or
-            /// exceed PULL_THRESH.
-            AUTOPULL: u1,
-            /// 1 = shift input shift register to right (data enters from left). 0 = to left.
-            IN_SHIFTDIR: u1,
-            /// 1 = shift out of output shift register to right. 0 = to left.
-            OUT_SHIFTDIR: u1,
-            /// Number of bits shifted into ISR before autopush, or conditional push (PUSH
-            /// IFFULL), will take place.\n
-            /// Write 0 for value of 32.
-            PUSH_THRESH: u5,
-            /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL
-            /// IFEMPTY), will take place.\n
-            /// Write 0 for value of 32.
-            PULL_THRESH: u5,
-            /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-            /// RX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_TX: u1,
-            /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-            /// TX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_RX: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x50300104
-        /// Current instruction address of state machine 2
-        pub const SM2_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x104);
-
-        /// address: 0x50300108
-        /// Read to see the instruction currently addressed by state machine 2's program
-        /// counter\n
-        /// Write to execute an instruction immediately (including jumps) and then resume
-        /// execution.
-        pub const SM2_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x108);
-
-        /// address: 0x5030010c
-        /// State machine pin control
-        pub const SM2_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV
-            /// PINS instruction. The data written to this pin will always be the
-            /// least-significant bit of the OUT or MOV data.
-            OUT_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS
-            /// instruction. The data written to this pin is the least-significant bit of the
-            /// SET data.
-            SET_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs
-            /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT)
-            /// are used for side-set data, with the remaining LSBs used for delay. The
-            /// least-significant bit of the side-set portion is the bit written to this pin,
-            /// with more-significant bits written to higher-numbered pins.
-            SIDESET_BASE: u5,
-            /// The pin which is mapped to the least-significant bit of a state machine's IN
-            /// data bus. Higher-numbered pins are mapped to consecutively more-significant data
-            /// bits, with a modulo of 32 applied to pin number.
-            IN_BASE: u5,
-            /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction.
-            /// In the range 0 to 32 inclusive.
-            OUT_COUNT: u6,
-            /// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-            SET_COUNT: u3,
-            /// The number of MSBs of the Delay/Side-set instruction field which are used for
-            /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits,
-            /// no side-set) and maximum of 5 (all side-set, no delay).
-            SIDESET_COUNT: u3,
-        }), base_address + 0x10c);
-
-        /// address: 0x50300110
-        /// Clock divisor register for state machine 3\n
-        /// Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-        pub const SM3_CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            /// Fractional part of clock divisor
-            FRAC: u8,
-            /// Effective frequency is sysclk/(int + frac/256).\n
-            /// Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-            INT: u16,
-        }), base_address + 0x110);
-
-        /// address: 0x50300114
-        /// Execution/behavioural settings for state machine 3
-        pub const SM3_EXECCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Comparison level for the MOV x, STATUS instruction
-            STATUS_N: u4,
-            /// Comparison used for the MOV x, STATUS instruction.
-            STATUS_SEL: u1,
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            /// After reaching wrap_top, execution is wrapped to this address.
-            WRAP_BOTTOM: u5,
-            /// After reaching this address, execution is wrapped to wrap_bottom.\n
-            /// If the instruction is a jump, and the jump condition is true, the jump takes
-            /// priority.
-            WRAP_TOP: u5,
-            /// Continuously assert the most recent OUT/SET to the pins
-            OUT_STICKY: u1,
-            /// If 1, use a bit of OUT data as an auxiliary write enable\n
-            /// When used in conjunction with OUT_STICKY, writes with an enable of 0 will\n
-            /// deassert the latest pin write. This can create useful masking/override
-            /// behaviour\n
-            /// due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-            INLINE_OUT_EN: u1,
-            /// Which data bit to use for inline OUT enable
-            OUT_EN_SEL: u5,
-            /// The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-            JMP_PIN: u5,
-            /// If 1, side-set data is asserted to pin directions, instead of pin values
-            SIDE_PINDIR: u1,
-            /// If 1, the MSB of the Delay/Side-set instruction field is used as side-set
-            /// enable, rather than a side-set data bit. This allows instructions to perform
-            /// side-set optionally, rather than on every instruction, but the maximum possible
-            /// side-set width is reduced from 5 to 4. Note that the value of
-            /// PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-            SIDE_EN: u1,
-            /// If 1, an instruction written to SMx_INSTR is stalled, and latched by the state
-            /// machine. Will clear to 0 once this instruction completes.
-            EXEC_STALLED: u1,
-        }), base_address + 0x114);
-
-        /// address: 0x50300118
-        /// Control behaviour of the input/output shift registers for state machine 3
-        pub const SM3_SHIFTCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            /// Push automatically when the input shift register is filled, i.e. on an IN
-            /// instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-            AUTOPUSH: u1,
-            /// Pull automatically when the output shift register is emptied, i.e. on or
-            /// following an OUT instruction which causes the output shift counter to reach or
-            /// exceed PULL_THRESH.
-            AUTOPULL: u1,
-            /// 1 = shift input shift register to right (data enters from left). 0 = to left.
-            IN_SHIFTDIR: u1,
-            /// 1 = shift out of output shift register to right. 0 = to left.
-            OUT_SHIFTDIR: u1,
-            /// Number of bits shifted into ISR before autopush, or conditional push (PUSH
-            /// IFFULL), will take place.\n
-            /// Write 0 for value of 32.
-            PUSH_THRESH: u5,
-            /// Number of bits shifted out of OSR before autopull, or conditional pull (PULL
-            /// IFEMPTY), will take place.\n
-            /// Write 0 for value of 32.
-            PULL_THRESH: u5,
-            /// When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.\n
-            /// RX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_TX: u1,
-            /// When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.\n
-            /// TX FIFO is disabled as a result (always reads as both full and empty).\n
-            /// FIFOs are flushed when this bit is changed.
-            FJOIN_RX: u1,
-        }), base_address + 0x118);
-
-        /// address: 0x5030011c
-        /// Current instruction address of state machine 3
-        pub const SM3_ADDR = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x11c);
-
-        /// address: 0x50300120
-        /// Read to see the instruction currently addressed by state machine 3's program
-        /// counter\n
-        /// Write to execute an instruction immediately (including jumps) and then resume
-        /// execution.
-        pub const SM3_INSTR = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x120);
-
-        /// address: 0x50300124
-        /// State machine pin control
-        pub const SM3_PINCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV
-            /// PINS instruction. The data written to this pin will always be the
-            /// least-significant bit of the OUT or MOV data.
-            OUT_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS
-            /// instruction. The data written to this pin is the least-significant bit of the
-            /// SET data.
-            SET_BASE: u5,
-            /// The lowest-numbered pin that will be affected by a side-set operation. The MSBs
-            /// of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT)
-            /// are used for side-set data, with the remaining LSBs used for delay. The
-            /// least-significant bit of the side-set portion is the bit written to this pin,
-            /// with more-significant bits written to higher-numbered pins.
-            SIDESET_BASE: u5,
-            /// The pin which is mapped to the least-significant bit of a state machine's IN
-            /// data bus. Higher-numbered pins are mapped to consecutively more-significant data
-            /// bits, with a modulo of 32 applied to pin number.
-            IN_BASE: u5,
-            /// The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction.
-            /// In the range 0 to 32 inclusive.
-            OUT_COUNT: u6,
-            /// The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-            SET_COUNT: u3,
-            /// The number of MSBs of the Delay/Side-set instruction field which are used for
-            /// side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits,
-            /// no side-set) and maximum of 5 (all side-set, no delay).
-            SIDESET_COUNT: u3,
-        }), base_address + 0x124);
-
-        /// address: 0x50300128
-        /// Raw Interrupts
-        pub const INTR = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x128);
-
-        /// address: 0x5030012c
-        /// Interrupt Enable for irq0
-        pub const IRQ0_INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x12c);
-
-        /// address: 0x50300130
-        /// Interrupt Force for irq0
-        pub const IRQ0_INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x130);
-
-        /// address: 0x50300134
-        /// Interrupt status after masking & forcing for irq0
-        pub const IRQ0_INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x134);
-
-        /// address: 0x50300138
-        /// Interrupt Enable for irq1
-        pub const IRQ1_INTE = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x138);
-
-        /// address: 0x5030013c
-        /// Interrupt Force for irq1
-        pub const IRQ1_INTF = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x13c);
-
-        /// address: 0x50300140
-        /// Interrupt status after masking & forcing for irq1
-        pub const IRQ1_INTS = @intToPtr(*volatile Mmio(32, packed struct {
-            SM0_RXNEMPTY: u1,
-            SM1_RXNEMPTY: u1,
-            SM2_RXNEMPTY: u1,
-            SM3_RXNEMPTY: u1,
-            SM0_TXNFULL: u1,
-            SM1_TXNFULL: u1,
-            SM2_TXNFULL: u1,
-            SM3_TXNFULL: u1,
-            SM0: u1,
-            SM1: u1,
-            SM2: u1,
-            SM3: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-        }), base_address + 0x140);
-    };
-
-    /// Single-cycle IO block\n
-    /// Provides core-local and inter-core hardware for the two processors, with
-    /// single-cycle access.
-    pub const SIO = struct {
-        pub const base_address = 0xd0000000;
-        pub const version = "1";
-
-        /// address: 0xd0000000
-        /// Processor core identifier\n
-        /// Value is 0 when read from processor core 0, and 1 when read from processor core
-        /// 1.
-        pub const CPUID = @intToPtr(*volatile u32, base_address + 0x0);
-
-        /// address: 0xd0000004
-        /// Input value for GPIO pins
-        pub const GPIO_IN = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x4);
-
-        /// address: 0xd0000008
-        /// Input value for QSPI pins
-        pub const GPIO_HI_IN = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x8);
-
-        /// address: 0xd0000010
-        /// GPIO output value
-        pub const GPIO_OUT = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x10);
-
-        /// address: 0xd0000014
-        /// GPIO output value set
-        pub const GPIO_OUT_SET = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x14);
-
-        /// address: 0xd0000018
-        /// GPIO output value clear
-        pub const GPIO_OUT_CLR = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x18);
-
-        /// address: 0xd000001c
-        /// GPIO output value XOR
-        pub const GPIO_OUT_XOR = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x1c);
-
-        /// address: 0xd0000020
-        /// GPIO output enable
-        pub const GPIO_OE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x20);
-
-        /// address: 0xd0000024
-        /// GPIO output enable set
-        pub const GPIO_OE_SET = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x24);
-
-        /// address: 0xd0000028
-        /// GPIO output enable clear
-        pub const GPIO_OE_CLR = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x28);
-
-        /// address: 0xd000002c
-        /// GPIO output enable XOR
-        pub const GPIO_OE_XOR = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x2c);
-
-        /// address: 0xd0000030
-        /// QSPI output value
-        pub const GPIO_HI_OUT = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x30);
-
-        /// address: 0xd0000034
-        /// QSPI output value set
-        pub const GPIO_HI_OUT_SET = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x34);
-
-        /// address: 0xd0000038
-        /// QSPI output value clear
-        pub const GPIO_HI_OUT_CLR = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x38);
-
-        /// address: 0xd000003c
-        /// QSPI output value XOR
-        pub const GPIO_HI_OUT_XOR = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x3c);
-
-        /// address: 0xd0000040
-        /// QSPI output enable
-        pub const GPIO_HI_OE = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x40);
-
-        /// address: 0xd0000044
-        /// QSPI output enable set
-        pub const GPIO_HI_OE_SET = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x44);
-
-        /// address: 0xd0000048
-        /// QSPI output enable clear
-        pub const GPIO_HI_OE_CLR = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x48);
-
-        /// address: 0xd000004c
-        /// QSPI output enable XOR
-        pub const GPIO_HI_OE_XOR = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x4c);
-
-        /// address: 0xd0000050
-        /// Status register for inter-core FIFOs (mailboxes).\n
-        /// There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0.
-        /// Both are 32 bits wide and 8 words deep.\n
-        /// Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1
-        /// FIFO (TX).\n
-        /// Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0
-        /// FIFO (TX).\n
-        /// The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of
-        /// its FIFO_ST register.
-        pub const FIFO_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)
-            VLD: u1,
-            /// Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more
-            /// data)
-            RDY: u1,
-            /// Sticky flag indicating the TX FIFO was written when full. This write was ignored
-            /// by the FIFO.
-            WOF: u1,
-            /// Sticky flag indicating the RX FIFO was read when empty. This read was ignored by
-            /// the FIFO.
-            ROE: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-        }), base_address + 0x50);
-
-        /// address: 0xd0000054
-        /// Write access to this core's TX FIFO
-        pub const FIFO_WR = @intToPtr(*volatile u32, base_address + 0x54);
-
-        /// address: 0xd0000058
-        /// Read access to this core's RX FIFO
-        pub const FIFO_RD = @intToPtr(*volatile u32, base_address + 0x58);
-
-        /// address: 0xd000005c
-        /// Spinlock state\n
-        /// A bitmap containing the state of all 32 spinlocks (1=locked).\n
-        /// Mainly intended for debugging.
-        pub const SPINLOCK_ST = @intToPtr(*volatile u32, base_address + 0x5c);
-
-        /// address: 0xd0000060
-        /// Divider unsigned dividend\n
-        /// Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.\n
-        /// Any operand write starts a new calculation. The results appear in QUOTIENT,
-        /// REMAINDER.\n
-        /// UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias
-        /// starts an\n
-        /// unsigned calculation, and the S alias starts a signed calculation.
-        pub const DIV_UDIVIDEND = @intToPtr(*volatile u32, base_address + 0x60);
-
-        /// address: 0xd0000064
-        /// Divider unsigned divisor\n
-        /// Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.\n
-        /// Any operand write starts a new calculation. The results appear in QUOTIENT,
-        /// REMAINDER.\n
-        /// UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias
-        /// starts an\n
-        /// unsigned calculation, and the S alias starts a signed calculation.
-        pub const DIV_UDIVISOR = @intToPtr(*volatile u32, base_address + 0x64);
-
-        /// address: 0xd0000068
-        /// Divider signed dividend\n
-        /// The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.
-        pub const DIV_SDIVIDEND = @intToPtr(*volatile u32, base_address + 0x68);
-
-        /// address: 0xd000006c
-        /// Divider signed divisor\n
-        /// The same as UDIVISOR, but starts a signed calculation, rather than unsigned.
-        pub const DIV_SDIVISOR = @intToPtr(*volatile u32, base_address + 0x6c);
-
-        /// address: 0xd0000070
-        /// Divider result quotient\n
-        /// The result of `DIVIDEND / DIVISOR` (division). Contents undefined while
-        /// CSR_READY is low.\n
-        /// For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and
-        /// DIVISOR differ.\n
-        /// This register can be written to directly, for context save/restore purposes.
-        /// This halts any\n
-        /// in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.\n
-        /// Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the
-        /// order\n
-        /// REMAINDER, QUOTIENT if CSR_DIRTY is used.
-        pub const DIV_QUOTIENT = @intToPtr(*volatile u32, base_address + 0x70);
-
-        /// address: 0xd0000074
-        /// Divider result remainder\n
-        /// The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY
-        /// is low.\n
-        /// For signed calculations, REMAINDER is negative only when DIVIDEND is negative.\n
-        /// This register can be written to directly, for context save/restore purposes.
-        /// This halts any\n
-        /// in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
-        pub const DIV_REMAINDER = @intToPtr(*volatile u32, base_address + 0x74);
-
-        /// address: 0xd0000078
-        /// Control and status register for divider.
-        pub const DIV_CSR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reads as 0 when a calculation is in progress, 1 otherwise.\n
-            /// Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new
-            /// calculation, no\n
-            /// matter if one is already in progress.\n
-            /// Writing to a result register will immediately terminate any in-progress
-            /// calculation\n
-            /// and set the READY and DIRTY flags.
-            READY: u1,
-            /// Changes to 1 when any register is written, and back to 0 when QUOTIENT is
-            /// read.\n
-            /// Software can use this flag to make save/restore more efficient (skip if not
-            /// DIRTY).\n
-            /// If the flag is used in this way, it's recommended to either read QUOTIENT
-            /// only,\n
-            /// or REMAINDER and then QUOTIENT, to prevent data loss on context switch.
-            DIRTY: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-            padding11: u1 = 0,
-            padding12: u1 = 0,
-            padding13: u1 = 0,
-            padding14: u1 = 0,
-            padding15: u1 = 0,
-            padding16: u1 = 0,
-            padding17: u1 = 0,
-            padding18: u1 = 0,
-            padding19: u1 = 0,
-            padding20: u1 = 0,
-            padding21: u1 = 0,
-            padding22: u1 = 0,
-            padding23: u1 = 0,
-            padding24: u1 = 0,
-            padding25: u1 = 0,
-            padding26: u1 = 0,
-            padding27: u1 = 0,
-            padding28: u1 = 0,
-            padding29: u1 = 0,
-        }), base_address + 0x78);
-
-        /// address: 0xd0000080
-        /// Read/write access to accumulator 0
-        pub const INTERP0_ACCUM0 = @intToPtr(*volatile u32, base_address + 0x80);
-
-        /// address: 0xd0000084
-        /// Read/write access to accumulator 1
-        pub const INTERP0_ACCUM1 = @intToPtr(*volatile u32, base_address + 0x84);
-
-        /// address: 0xd0000088
-        /// Read/write access to BASE0 register.
-        pub const INTERP0_BASE0 = @intToPtr(*volatile u32, base_address + 0x88);
-
-        /// address: 0xd000008c
-        /// Read/write access to BASE1 register.
-        pub const INTERP0_BASE1 = @intToPtr(*volatile u32, base_address + 0x8c);
-
-        /// address: 0xd0000090
-        /// Read/write access to BASE2 register.
-        pub const INTERP0_BASE2 = @intToPtr(*volatile u32, base_address + 0x90);
-
-        /// address: 0xd0000094
-        /// Read LANE0 result, and simultaneously write lane results to both accumulators
-        /// (POP).
-        pub const INTERP0_POP_LANE0 = @intToPtr(*volatile u32, base_address + 0x94);
-
-        /// address: 0xd0000098
-        /// Read LANE1 result, and simultaneously write lane results to both accumulators
-        /// (POP).
-        pub const INTERP0_POP_LANE1 = @intToPtr(*volatile u32, base_address + 0x98);
-
-        /// address: 0xd000009c
-        /// Read FULL result, and simultaneously write lane results to both accumulators
-        /// (POP).
-        pub const INTERP0_POP_FULL = @intToPtr(*volatile u32, base_address + 0x9c);
-
-        /// address: 0xd00000a0
-        /// Read LANE0 result, without altering any internal state (PEEK).
-        pub const INTERP0_PEEK_LANE0 = @intToPtr(*volatile u32, base_address + 0xa0);
-
-        /// address: 0xd00000a4
-        /// Read LANE1 result, without altering any internal state (PEEK).
-        pub const INTERP0_PEEK_LANE1 = @intToPtr(*volatile u32, base_address + 0xa4);
-
-        /// address: 0xd00000a8
-        /// Read FULL result, without altering any internal state (PEEK).
-        pub const INTERP0_PEEK_FULL = @intToPtr(*volatile u32, base_address + 0xa8);
-
-        /// address: 0xd00000ac
-        /// Control register for lane 0
-        pub const INTERP0_CTRL_LANE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Logical right-shift applied to accumulator before masking
-            SHIFT: u5,
-            /// The least-significant bit allowed to pass by the mask (inclusive)
-            MASK_LSB: u5,
-            /// The most-significant bit allowed to pass by the mask (inclusive)\n
-            /// Setting MSB < LSB may cause chip to turn inside-out
-            MASK_MSB: u5,
-            /// If SIGNED is set, the shifted and masked accumulator value is sign-extended to
-            /// 32 bits\n
-            /// before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read
-            /// by processor.
-            SIGNED: u1,
-            /// If 1, feed the opposite lane's accumulator into this lane's shift + mask
-            /// hardware.\n
-            /// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the
-            /// shift+mask bypass)
-            CROSS_INPUT: u1,
-            /// If 1, feed the opposite lane's result into this lane's accumulator on POP.
-            CROSS_RESULT: u1,
-            /// If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL
-            /// result.
-            ADD_RAW: u1,
-            /// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
-            /// No effect on the internal 32-bit datapath. Handy for using a lane to generate
-            /// sequence\n
-            /// of pointers into flash or SRAM.
-            FORCE_MSB: u2,
-            /// Only present on INTERP0 on each core. If BLEND mode is enabled:\n
-            /// - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled\n
-            /// by the 8 LSBs of lane 1 shift and mask value (a fractional number between\n
-            /// 0 and 255/256ths)\n
-            /// - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1
-            /// shift+mask value)\n
-            /// - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0
-            /// shift+mask)\n
-            /// LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.
-            BLEND: u1,
-            reserved0: u1 = 0,
-            /// Indicates if any masked-off MSBs in ACCUM0 are set.
-            OVERF0: u1,
-            /// Indicates if any masked-off MSBs in ACCUM1 are set.
-            OVERF1: u1,
-            /// Set if either OVERF0 or OVERF1 is set.
-            OVERF: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-        }), base_address + 0xac);
-
-        /// address: 0xd00000b0
-        /// Control register for lane 1
-        pub const INTERP0_CTRL_LANE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Logical right-shift applied to accumulator before masking
-            SHIFT: u5,
-            /// The least-significant bit allowed to pass by the mask (inclusive)
-            MASK_LSB: u5,
-            /// The most-significant bit allowed to pass by the mask (inclusive)\n
-            /// Setting MSB < LSB may cause chip to turn inside-out
-            MASK_MSB: u5,
-            /// If SIGNED is set, the shifted and masked accumulator value is sign-extended to
-            /// 32 bits\n
-            /// before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read
-            /// by processor.
-            SIGNED: u1,
-            /// If 1, feed the opposite lane's accumulator into this lane's shift + mask
-            /// hardware.\n
-            /// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the
-            /// shift+mask bypass)
-            CROSS_INPUT: u1,
-            /// If 1, feed the opposite lane's result into this lane's accumulator on POP.
-            CROSS_RESULT: u1,
-            /// If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL
-            /// result.
-            ADD_RAW: u1,
-            /// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
-            /// No effect on the internal 32-bit datapath. Handy for using a lane to generate
-            /// sequence\n
-            /// of pointers into flash or SRAM.
-            FORCE_MSB: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-        }), base_address + 0xb0);
-
-        /// address: 0xd00000b4
-        /// Values written here are atomically added to ACCUM0\n
-        /// Reading yields lane 0's raw shift and mask value (BASE0 not added).
-        pub const INTERP0_ACCUM0_ADD = @intToPtr(*volatile MmioInt(32, u24), base_address + 0xb4);
-
-        /// address: 0xd00000b8
-        /// Values written here are atomically added to ACCUM1\n
-        /// Reading yields lane 1's raw shift and mask value (BASE1 not added).
-        pub const INTERP0_ACCUM1_ADD = @intToPtr(*volatile MmioInt(32, u24), base_address + 0xb8);
-
-        /// address: 0xd00000bc
-        /// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
-        /// Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.
-        pub const INTERP0_BASE_1AND0 = @intToPtr(*volatile u32, base_address + 0xbc);
-
-        /// address: 0xd00000c0
-        /// Read/write access to accumulator 0
-        pub const INTERP1_ACCUM0 = @intToPtr(*volatile u32, base_address + 0xc0);
-
-        /// address: 0xd00000c4
-        /// Read/write access to accumulator 1
-        pub const INTERP1_ACCUM1 = @intToPtr(*volatile u32, base_address + 0xc4);
-
-        /// address: 0xd00000c8
-        /// Read/write access to BASE0 register.
-        pub const INTERP1_BASE0 = @intToPtr(*volatile u32, base_address + 0xc8);
-
-        /// address: 0xd00000cc
-        /// Read/write access to BASE1 register.
-        pub const INTERP1_BASE1 = @intToPtr(*volatile u32, base_address + 0xcc);
-
-        /// address: 0xd00000d0
-        /// Read/write access to BASE2 register.
-        pub const INTERP1_BASE2 = @intToPtr(*volatile u32, base_address + 0xd0);
-
-        /// address: 0xd00000d4
-        /// Read LANE0 result, and simultaneously write lane results to both accumulators
-        /// (POP).
-        pub const INTERP1_POP_LANE0 = @intToPtr(*volatile u32, base_address + 0xd4);
-
-        /// address: 0xd00000d8
-        /// Read LANE1 result, and simultaneously write lane results to both accumulators
-        /// (POP).
-        pub const INTERP1_POP_LANE1 = @intToPtr(*volatile u32, base_address + 0xd8);
-
-        /// address: 0xd00000dc
-        /// Read FULL result, and simultaneously write lane results to both accumulators
-        /// (POP).
-        pub const INTERP1_POP_FULL = @intToPtr(*volatile u32, base_address + 0xdc);
-
-        /// address: 0xd00000e0
-        /// Read LANE0 result, without altering any internal state (PEEK).
-        pub const INTERP1_PEEK_LANE0 = @intToPtr(*volatile u32, base_address + 0xe0);
-
-        /// address: 0xd00000e4
-        /// Read LANE1 result, without altering any internal state (PEEK).
-        pub const INTERP1_PEEK_LANE1 = @intToPtr(*volatile u32, base_address + 0xe4);
-
-        /// address: 0xd00000e8
-        /// Read FULL result, without altering any internal state (PEEK).
-        pub const INTERP1_PEEK_FULL = @intToPtr(*volatile u32, base_address + 0xe8);
-
-        /// address: 0xd00000ec
-        /// Control register for lane 0
-        pub const INTERP1_CTRL_LANE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Logical right-shift applied to accumulator before masking
-            SHIFT: u5,
-            /// The least-significant bit allowed to pass by the mask (inclusive)
-            MASK_LSB: u5,
-            /// The most-significant bit allowed to pass by the mask (inclusive)\n
-            /// Setting MSB < LSB may cause chip to turn inside-out
-            MASK_MSB: u5,
-            /// If SIGNED is set, the shifted and masked accumulator value is sign-extended to
-            /// 32 bits\n
-            /// before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read
-            /// by processor.
-            SIGNED: u1,
-            /// If 1, feed the opposite lane's accumulator into this lane's shift + mask
-            /// hardware.\n
-            /// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the
-            /// shift+mask bypass)
-            CROSS_INPUT: u1,
-            /// If 1, feed the opposite lane's result into this lane's accumulator on POP.
-            CROSS_RESULT: u1,
-            /// If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL
-            /// result.
-            ADD_RAW: u1,
-            /// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
-            /// No effect on the internal 32-bit datapath. Handy for using a lane to generate
-            /// sequence\n
-            /// of pointers into flash or SRAM.
-            FORCE_MSB: u2,
-            reserved0: u1 = 0,
-            /// Only present on INTERP1 on each core. If CLAMP mode is enabled:\n
-            /// - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of\n
-            /// BASE0 and an upper bound of BASE1.\n
-            /// - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED
-            CLAMP: u1,
-            /// Indicates if any masked-off MSBs in ACCUM0 are set.
-            OVERF0: u1,
-            /// Indicates if any masked-off MSBs in ACCUM1 are set.
-            OVERF1: u1,
-            /// Set if either OVERF0 or OVERF1 is set.
-            OVERF: u1,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-        }), base_address + 0xec);
-
-        /// address: 0xd00000f0
-        /// Control register for lane 1
-        pub const INTERP1_CTRL_LANE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Logical right-shift applied to accumulator before masking
-            SHIFT: u5,
-            /// The least-significant bit allowed to pass by the mask (inclusive)
-            MASK_LSB: u5,
-            /// The most-significant bit allowed to pass by the mask (inclusive)\n
-            /// Setting MSB < LSB may cause chip to turn inside-out
-            MASK_MSB: u5,
-            /// If SIGNED is set, the shifted and masked accumulator value is sign-extended to
-            /// 32 bits\n
-            /// before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read
-            /// by processor.
-            SIGNED: u1,
-            /// If 1, feed the opposite lane's accumulator into this lane's shift + mask
-            /// hardware.\n
-            /// Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the
-            /// shift+mask bypass)
-            CROSS_INPUT: u1,
-            /// If 1, feed the opposite lane's result into this lane's accumulator on POP.
-            CROSS_RESULT: u1,
-            /// If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL
-            /// result.
-            ADD_RAW: u1,
-            /// ORed into bits 29:28 of the lane result presented to the processor on the bus.\n
-            /// No effect on the internal 32-bit datapath. Handy for using a lane to generate
-            /// sequence\n
-            /// of pointers into flash or SRAM.
-            FORCE_MSB: u2,
-            padding0: u1 = 0,
-            padding1: u1 = 0,
-            padding2: u1 = 0,
-            padding3: u1 = 0,
-            padding4: u1 = 0,
-            padding5: u1 = 0,
-            padding6: u1 = 0,
-            padding7: u1 = 0,
-            padding8: u1 = 0,
-            padding9: u1 = 0,
-            padding10: u1 = 0,
-        }), base_address + 0xf0);
-
-        /// address: 0xd00000f4
-        /// Values written here are atomically added to ACCUM0\n
-        /// Reading yields lane 0's raw shift and mask value (BASE0 not added).
-        pub const INTERP1_ACCUM0_ADD = @intToPtr(*volatile MmioInt(32, u24), base_address + 0xf4);
-
-        /// address: 0xd00000f8
-        /// Values written here are atomically added to ACCUM1\n
-        /// Reading yields lane 1's raw shift and mask value (BASE1 not added).
-        pub const INTERP1_ACCUM1_ADD = @intToPtr(*volatile MmioInt(32, u24), base_address + 0xf8);
-
-        /// address: 0xd00000fc
-        /// On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.\n
-        /// Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.
-        pub const INTERP1_BASE_1AND0 = @intToPtr(*volatile u32, base_address + 0xfc);
-
-        /// address: 0xd0000100
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK0 = @intToPtr(*volatile u32, base_address + 0x100);
-
-        /// address: 0xd0000104
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK1 = @intToPtr(*volatile u32, base_address + 0x104);
-
-        /// address: 0xd0000108
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK2 = @intToPtr(*volatile u32, base_address + 0x108);
-
-        /// address: 0xd000010c
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK3 = @intToPtr(*volatile u32, base_address + 0x10c);
-
-        /// address: 0xd0000110
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK4 = @intToPtr(*volatile u32, base_address + 0x110);
-
-        /// address: 0xd0000114
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK5 = @intToPtr(*volatile u32, base_address + 0x114);
-
-        /// address: 0xd0000118
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK6 = @intToPtr(*volatile u32, base_address + 0x118);
-
-        /// address: 0xd000011c
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK7 = @intToPtr(*volatile u32, base_address + 0x11c);
-
-        /// address: 0xd0000120
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK8 = @intToPtr(*volatile u32, base_address + 0x120);
-
-        /// address: 0xd0000124
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK9 = @intToPtr(*volatile u32, base_address + 0x124);
-
-        /// address: 0xd0000128
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK10 = @intToPtr(*volatile u32, base_address + 0x128);
-
-        /// address: 0xd000012c
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK11 = @intToPtr(*volatile u32, base_address + 0x12c);
-
-        /// address: 0xd0000130
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK12 = @intToPtr(*volatile u32, base_address + 0x130);
-
-        /// address: 0xd0000134
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK13 = @intToPtr(*volatile u32, base_address + 0x134);
-
-        /// address: 0xd0000138
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK14 = @intToPtr(*volatile u32, base_address + 0x138);
-
-        /// address: 0xd000013c
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK15 = @intToPtr(*volatile u32, base_address + 0x13c);
-
-        /// address: 0xd0000140
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK16 = @intToPtr(*volatile u32, base_address + 0x140);
-
-        /// address: 0xd0000144
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK17 = @intToPtr(*volatile u32, base_address + 0x144);
-
-        /// address: 0xd0000148
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK18 = @intToPtr(*volatile u32, base_address + 0x148);
-
-        /// address: 0xd000014c
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK19 = @intToPtr(*volatile u32, base_address + 0x14c);
-
-        /// address: 0xd0000150
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK20 = @intToPtr(*volatile u32, base_address + 0x150);
-
-        /// address: 0xd0000154
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK21 = @intToPtr(*volatile u32, base_address + 0x154);
-
-        /// address: 0xd0000158
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK22 = @intToPtr(*volatile u32, base_address + 0x158);
-
-        /// address: 0xd000015c
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK23 = @intToPtr(*volatile u32, base_address + 0x15c);
-
-        /// address: 0xd0000160
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK24 = @intToPtr(*volatile u32, base_address + 0x160);
-
-        /// address: 0xd0000164
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK25 = @intToPtr(*volatile u32, base_address + 0x164);
-
-        /// address: 0xd0000168
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK26 = @intToPtr(*volatile u32, base_address + 0x168);
-
-        /// address: 0xd000016c
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK27 = @intToPtr(*volatile u32, base_address + 0x16c);
-
-        /// address: 0xd0000170
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK28 = @intToPtr(*volatile u32, base_address + 0x170);
-
-        /// address: 0xd0000174
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK29 = @intToPtr(*volatile u32, base_address + 0x174);
-
-        /// address: 0xd0000178
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK30 = @intToPtr(*volatile u32, base_address + 0x178);
-
-        /// address: 0xd000017c
-        /// Reading from a spinlock address will:\n
-        /// - Return 0 if lock is already locked\n
-        /// - Otherwise return nonzero, and simultaneously claim the lock\n\n
-        /// Writing (any value) releases the lock.\n
-        /// If core 0 and core 1 attempt to claim the same lock simultaneously, core 0
-        /// wins.\n
-        /// The value returned on success is 0x1 << lock number.
-        pub const SPINLOCK31 = @intToPtr(*volatile u32, base_address + 0x17c);
-    };
-    pub const PPB = struct {
-        pub const base_address = 0xe0000000;
-        pub const version = "1";
-
-        /// address: 0xe000ed20
-        /// System handlers are a special class of exception handler that can have their
-        /// priority set to any of the priority levels. Use the System Handler Priority
-        /// Register 3 to set the priority of PendSV and SysTick.
-        pub const SHPR3 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1 = 0,
-            reserved1: u1 = 0,
-            reserved2: u1 = 0,
-            reserved3: u1 = 0,
-            reserved4: u1 = 0,
-            reserved5: u1 = 0,
-            reserved6: u1 = 0,
-            reserved7: u1 = 0,
-            reserved8: u1 = 0,
-            reserved9: u1 = 0,
-            reserved10: u1 = 0,
-            reserved11: u1 = 0,
-            reserved12: u1 = 0,
-            reserved13: u1 = 0,
-            reserved14: u1 = 0,
-            reserved15: u1 = 0,
-            reserved16: u1 = 0,
-            reserved17: u1 = 0,
-            reserved18: u1 = 0,
-            reserved19: u1 = 0,
-            reserved20: u1 = 0,
-            reserved21: u1 = 0,
-            /// Priority of system handler 14, PendSV
-            PRI_14: u2,
-            reserved22: u1 = 0,
-            reserved23: u1 = 0,
-            reserved24: u1 = 0,
-            reserved25: u1 = 0,
-            reserved26: u1 = 0,
-            reserved27: u1 = 0,
-            /// Priority of system handler 15, SysTick
-            PRI_15: u2,
-        }), base_address + 0xed20);
-    };
-};
-
-const std = @import("std");
-
-pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) {
-    return @intToPtr(*volatile Mmio(size, PackedT), addr);
-}
-
-pub fn Mmio(comptime size: u8, comptime PackedT: type) type {
-    if ((size % 8) != 0)
-        @compileError("size must be divisible by 8!");
-
-    if (!std.math.isPowerOfTwo(size / 8))
-        @compileError("size must encode a power of two number of bytes!");
-
-    const IntT = std.meta.Int(.unsigned, size);
-
-    if (@sizeOf(PackedT) != (size / 8))
-        @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) }));
-
-    return extern struct {
-        const Self = @This();
-
-        raw: IntT,
-
-        pub const underlying_type = PackedT;
-
-        pub inline fn read(addr: *volatile Self) PackedT {
-            return @bitCast(PackedT, addr.raw);
-        }
-
-        pub inline fn write(addr: *volatile Self, val: PackedT) void {
-            // This is a workaround for a compiler bug related to miscompilation
-            // If the tmp var is not used, result location will fuck things up
-            var tmp = @bitCast(IntT, val);
-            addr.raw = tmp;
-        }
-
-        pub inline fn modify(addr: *volatile Self, fields: anytype) void {
-            var val = read(addr);
-            inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
-                @field(val, field.name) = @field(fields, field.name);
-            }
-            write(addr, val);
-        }
-
-        pub inline fn toggle(addr: *volatile Self, fields: anytype) void {
-            var val = read(addr);
-            inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
-                @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?));
-            }
-            write(addr, val);
-        }
-    };
-}
-
-pub fn MmioInt(comptime size: u8, comptime T: type) type {
-    return extern struct {
-        const Self = @This();
-
-        raw: std.meta.Int(.unsigned, size),
-
-        pub inline fn read(addr: *volatile Self) T {
-            return @truncate(T, addr.raw);
-        }
-
-        pub inline fn modify(addr: *volatile Self, val: T) void {
-            const Int = std.meta.Int(.unsigned, size);
-            const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1);
-
-            var tmp = addr.raw;
-            addr.raw = (tmp & mask) | val;
-        }
-    };
-}
-
-pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) {
-    return @intToPtr(*volatile MmioInt(size, T), addr);
-}
-
-pub const InterruptVector = extern union {
-    C: *const fn () callconv(.C) void,
-    Naked: *const fn () callconv(.Naked) void,
-    // Interrupt is not supported on arm
-};
-
-const unhandled = InterruptVector{
-    .C = struct {
-        fn tmp() callconv(.C) noreturn {
-            @panic("unhandled interrupt");
-        }
-    }.tmp,
-};

From 24bb6dced705bef2d5db29a4cdb398327ff1dffb Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 20 Feb 2023 11:03:20 -0800
Subject: [PATCH 048/286] add microzig submodule (#1)

---
 .gitmodules   | 3 +++
 deps/microzig | 1 +
 2 files changed, 4 insertions(+)
 create mode 160000 deps/microzig

diff --git a/.gitmodules b/.gitmodules
index 54620ef7a..911b8cfac 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +1,6 @@
 [submodule "vendor/microzig"]
 	path = vendor/microzig
 	url = https://github.com/ZigEmbeddedGroup/microzig
+[submodule "deps/microzig"]
+	path = deps/microzig
+	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/deps/microzig b/deps/microzig
new file mode 160000
index 000000000..4bb65617a
--- /dev/null
+++ b/deps/microzig
@@ -0,0 +1 @@
+Subproject commit 4bb65617a47dc30282ffe340cc45d202b973650b

From 8cb150e968c16e7633fb4ddcae1d38dd8c405afc Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 20 Feb 2023 11:09:18 -0800
Subject: [PATCH 049/286] update microzig (#2)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 2d0ee5c47..831cfff35 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 2d0ee5c4731de1d81afb9c8e08ba4e8c2c2cfbf3
+Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec

From 026af75f81fa6ad0b5033e9c3ed1565ec9369b92 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 20 Feb 2023 11:09:54 -0800
Subject: [PATCH 050/286] update microzig (#22)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 2d0ee5c47..4bb65617a 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 2d0ee5c4731de1d81afb9c8e08ba4e8c2c2cfbf3
+Subproject commit 4bb65617a47dc30282ffe340cc45d202b973650b

From f26efd50424daa962d7aa11cac1edecacc63d1a4 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 20 Feb 2023 11:10:08 -0800
Subject: [PATCH 051/286] update microzig (#2)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 97ca5497d..831cfff35 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 97ca5497da0f22d025e18bced9311efed088d893
+Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec

From b8b5df0dc66f4b2ff11051ddbaf820fdf4b46b4d Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 20 Feb 2023 11:10:38 -0800
Subject: [PATCH 052/286] update microzig (#2)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 97ca5497d..831cfff35 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 97ca5497da0f22d025e18bced9311efed088d893
+Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec

From 49c61c7e1417c013612c26b52c175df16722cc2b Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 20 Feb 2023 11:11:42 -0800
Subject: [PATCH 053/286] update microzig (#2)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 97ca5497d..831cfff35 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 97ca5497da0f22d025e18bced9311efed088d893
+Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec

From f625be1dff15eb1dac1fd5c29e2c7dec4604d3bd Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 20 Feb 2023 11:11:54 -0800
Subject: [PATCH 054/286] update microzig (#2)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 4bb65617a..831cfff35 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4bb65617a47dc30282ffe340cc45d202b973650b
+Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec

From c15e52ba1da72c04ccb664dff57619ca51be8aa2 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 20 Feb 2023 11:12:04 -0800
Subject: [PATCH 055/286] update microzig (#2)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 97ca5497d..831cfff35 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 97ca5497da0f22d025e18bced9311efed088d893
+Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec

From 0e22da698beee3bca49af1ebd400b5bb02f8c151 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Fri, 24 Feb 2023 09:12:06 -0800
Subject: [PATCH 056/286] Update microzig (#3)

* update microzig

* update paths and for loops

---------

Co-authored-by: mattnite 
---
 build.zig      | 2 +-
 deps/microzig  | 2 +-
 src/boards.zig | 2 +-
 src/chips.zig  | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/build.zig b/build.zig
index 3b787fe3f..30cd9c99e 100644
--- a/build.zig
+++ b/build.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/src/main.zig");
+const microzig = @import("deps/microzig/build.zig");
 const boards = @import("src/boards.zig");
 const chips = @import("src/chips.zig");
 
diff --git a/deps/microzig b/deps/microzig
index 831cfff35..11214ed8b 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec
+Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
diff --git a/src/boards.zig b/src/boards.zig
index d9a73b5f4..264bfeef9 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const micro = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/build.zig");
 const chips = @import("chips.zig");
 
 fn root_dir() []const u8 {
diff --git a/src/chips.zig b/src/chips.zig
index ac1beefb0..2822bd7cd 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const micro = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/build.zig");
 const Chip = micro.Chip;
 const MemoryRegion = micro.MemoryRegion;
 

From 58d73abc08952aac55301bd1ac66af49a3022711 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Fri, 24 Feb 2023 09:12:22 -0800
Subject: [PATCH 057/286] Update microzig (#24)

* update microzig

* update paths and for loops

---------

Co-authored-by: mattnite 
---
 build.zig        | 2 +-
 deps/microzig    | 2 +-
 src/boards.zig   | 2 +-
 src/chips.zig    | 2 +-
 src/hal/adc.zig  | 4 ++--
 src/hal/pins.zig | 2 +-
 6 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/build.zig b/build.zig
index 51bb874e5..a0ed86cf1 100644
--- a/build.zig
+++ b/build.zig
@@ -3,7 +3,7 @@ const Builder = std.build.Builder;
 const Pkg = std.build.Pkg;
 const comptimePrint = std.fmt.comptimePrint;
 
-pub const microzig = @import("deps/microzig/src/main.zig");
+pub const microzig = @import("deps/microzig/build.zig");
 
 const chips = @import("src/chips.zig");
 const boards = @import("src/boards.zig");
diff --git a/deps/microzig b/deps/microzig
index 4bb65617a..11214ed8b 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4bb65617a47dc30282ffe340cc45d202b973650b
+Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
diff --git a/src/boards.zig b/src/boards.zig
index 432918247..ebbf0d8cc 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/src/main.zig");
+const microzig = @import("../deps/microzig/build.zig");
 const chips = @import("chips.zig");
 
 fn root_dir() []const u8 {
diff --git a/src/chips.zig b/src/chips.zig
index 5e0d39a20..8363cea7a 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/src/main.zig");
+const microzig = @import("../deps/microzig/build.zig");
 
 fn root_dir() []const u8 {
     return std.fs.path.dirname(@src().file) orelse ".";
diff --git a/src/hal/adc.zig b/src/hal/adc.zig
index 1746ccc87..ba293b096 100644
--- a/src/hal/adc.zig
+++ b/src/hal/adc.zig
@@ -83,8 +83,8 @@ pub const InputMask = InputMask: {
     var fields: [enum_fields.len]std.builtin.Type.StructField = undefined;
 
     const default_value: u1 = 0;
-    for (enum_fields) |enum_field, i|
-        fields[i] = std.builtin.Type.StructField{
+    for (enum_fields, &fields) |enum_field, *field|
+        field = std.builtin.Type.StructField{
             .name = enum_field.name,
             .field_type = u1,
             .default_value = &default_value,
diff --git a/src/hal/pins.zig b/src/hal/pins.zig
index 24b9d7af6..7a204b8d2 100644
--- a/src/hal/pins.zig
+++ b/src/hal/pins.zig
@@ -237,7 +237,7 @@ pub const Function = enum {
 
 fn all() [30]u1 {
     var ret: [30]u1 = undefined;
-    for (ret) |*elem|
+    for (&ret) |*elem|
         elem.* = 1;
 
     return ret;

From 39245b48ac1dea7f070fdbd50ddecaa73fb5bc45 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Fri, 24 Feb 2023 09:12:42 -0800
Subject: [PATCH 058/286] Update microzig (#3)

* update microzig

* update paths and for loops

---------

Co-authored-by: mattnite 
---
 build.zig     | 2 +-
 deps/microzig | 2 +-
 src/chips.zig | 2 +-
 3 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/build.zig b/build.zig
index 40398384d..d6590025b 100644
--- a/build.zig
+++ b/build.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/src/main.zig");
+const microzig = @import("deps/microzig/build.zig");
 const chips = @import("src/chips.zig");
 
 pub fn build(b: *std.build.Builder) void {
diff --git a/deps/microzig b/deps/microzig
index 831cfff35..11214ed8b 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec
+Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
diff --git a/src/chips.zig b/src/chips.zig
index 50b2aad62..2487aa066 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const micro = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/build.zig");
 const Chip = micro.Chip;
 const MemoryRegion = micro.MemoryRegion;
 

From e8ad894d942b133bc45847d8fcbcb6b4b7aca47f Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Fri, 24 Feb 2023 09:23:02 -0800
Subject: [PATCH 059/286] Update microzig (#3)

* update microzig

* update paths and for loops

* update paths

---------

Co-authored-by: mattnite 
---
 build.zig                                 | 2 +-
 deps/microzig                             | 2 +-
 src/boards.zig                            | 2 +-
 src/chips.zig                             | 2 +-
 src/hals/{stm32f103.zig => STM32F103.zig} | 0
 src/hals/{stm32f303.zig => STM32F303.zig} | 4 ++--
 src/hals/{stm32f407.zig => STM32F407.zig} | 2 +-
 src/hals/{stm32f429.zig => STM32F429.zig} | 0
 8 files changed, 7 insertions(+), 7 deletions(-)
 rename src/hals/{stm32f103.zig => STM32F103.zig} (100%)
 rename src/hals/{stm32f303.zig => STM32F303.zig} (99%)
 rename src/hals/{stm32f407.zig => STM32F407.zig} (99%)
 rename src/hals/{stm32f429.zig => STM32F429.zig} (100%)

diff --git a/build.zig b/build.zig
index 3b787fe3f..30cd9c99e 100644
--- a/build.zig
+++ b/build.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/src/main.zig");
+const microzig = @import("deps/microzig/build.zig");
 const boards = @import("src/boards.zig");
 const chips = @import("src/chips.zig");
 
diff --git a/deps/microzig b/deps/microzig
index 831cfff35..11214ed8b 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec
+Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
diff --git a/src/boards.zig b/src/boards.zig
index 13f4c6156..9f9c3fa5d 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/src/main.zig");
+const microzig = @import("../deps/microzig/build.zig");
 const Board = microzig.Board;
 
 const chips = @import("chips.zig");
diff --git a/src/chips.zig b/src/chips.zig
index c492323bf..c7a2eda64 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/src/main.zig");
+const microzig = @import("../deps/microzig/build.zig");
 const Chip = microzig.Chip;
 const MemoryRegion = microzig.MemoryRegion;
 
diff --git a/src/hals/stm32f103.zig b/src/hals/STM32F103.zig
similarity index 100%
rename from src/hals/stm32f103.zig
rename to src/hals/STM32F103.zig
diff --git a/src/hals/stm32f303.zig b/src/hals/STM32F303.zig
similarity index 99%
rename from src/hals/stm32f303.zig
rename to src/hals/STM32F303.zig
index 272e8b1d7..5c470c83b 100644
--- a/src/hals/stm32f303.zig
+++ b/src/hals/STM32F303.zig
@@ -441,7 +441,7 @@ pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type
 
                 if (runtime_safety) self.read_allowed = false;
 
-                for (buffer) |_, i| {
+                for (buffer, 0..) |_, i| {
                     // Wait for data to be received
                     while (I2C1.ISR.read().RXNE == 0) {
                         debug_print("I2C1 waiting for data (RXNE=0)\r\n", .{});
@@ -582,7 +582,7 @@ pub fn SpiBus(comptime index: usize) type {
 
         /// Read bytes to fill the given buffer exactly, writing arbitrary bytes (`undefined`).
         pub fn read_into(self: Self, buffer: []u8) !void {
-            for (buffer) |_, i| {
+            for (buffer, 0..) |_, i| {
                 try self.transceive_byte(null, &buffer[i]);
             }
         }
diff --git a/src/hals/stm32f407.zig b/src/hals/STM32F407.zig
similarity index 99%
rename from src/hals/stm32f407.zig
rename to src/hals/STM32F407.zig
index 6461bd899..f48e05c8d 100644
--- a/src/hals/stm32f407.zig
+++ b/src/hals/STM32F407.zig
@@ -592,7 +592,7 @@ pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type
                 // Read SR2 to clear address condition
                 _ = i2c_base.SR2.read();
 
-                for (buffer) |_, i| {
+                for (buffer, 0..) |_, i| {
                     if (i == buffer.len - 1) {
                         // Disable ACK
                         i2c_base.CR1.modify(.{ .ACK = 0 });
diff --git a/src/hals/stm32f429.zig b/src/hals/STM32F429.zig
similarity index 100%
rename from src/hals/stm32f429.zig
rename to src/hals/STM32F429.zig

From 1d6d7d98a59863427b28c26ea553f464ee3c54ce Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Fri, 24 Feb 2023 09:23:29 -0800
Subject: [PATCH 060/286] Update microzig (#3)

* update microzig

* update paths

---------

Co-authored-by: mattnite 
---
 build.zig               |  2 +-
 deps/microzig           |  2 +-
 src/boards.zig          |  2 +-
 src/chips.zig           |  2 +-
 src/hals/ATmega328P.zig | 21 ++++++++++-----------
 5 files changed, 14 insertions(+), 15 deletions(-)

diff --git a/build.zig b/build.zig
index 3b787fe3f..30cd9c99e 100644
--- a/build.zig
+++ b/build.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/src/main.zig");
+const microzig = @import("deps/microzig/build.zig");
 const boards = @import("src/boards.zig");
 const chips = @import("src/chips.zig");
 
diff --git a/deps/microzig b/deps/microzig
index 831cfff35..11214ed8b 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec
+Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
diff --git a/src/boards.zig b/src/boards.zig
index 928877039..55fc2208e 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const micro = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/build.zig");
 const chips = @import("chips.zig");
 
 fn root_dir() []const u8 {
diff --git a/src/chips.zig b/src/chips.zig
index b47fe15ec..cc7816b83 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const micro = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/build.zig");
 const Chip = micro.Chip;
 const MemoryRegion = micro.MemoryRegion;
 
diff --git a/src/hals/ATmega328P.zig b/src/hals/ATmega328P.zig
index b836c651c..6e4ef9400 100644
--- a/src/hals/ATmega328P.zig
+++ b/src/hals/ATmega328P.zig
@@ -1,8 +1,7 @@
 const std = @import("std");
 const micro = @import("microzig");
-
-pub usingnamespace @import("registers.zig");
-const regz = @import("registers.zig").registers;
+const peripherals = micro.chip.peripherals;
+const USART0 = peripherals.USART0;
 
 pub const cpu = micro.cpu;
 const Port = enum(u8) {
@@ -141,11 +140,11 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
 
             const ubrr_val = try computeDivider(config.baud_rate);
 
-            regz.USART0.UCSR0A.modify(.{
+            USART0.UCSR0A.modify(.{
                 .MPCM0 = 0,
                 .U2X0 = 0,
             });
-            regz.USART0.UCSR0B.write(.{
+            USART0.UCSR0B.write(.{
                 .TXB80 = 0, // we don't care about these btw
                 .RXB80 = 0, // we don't care about these btw
                 .UCSZ02 = @truncate(u1, (ucsz & 0x04) >> 2),
@@ -155,7 +154,7 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
                 .TXCIE0 = 0, // no interrupts
                 .RXCIE0 = 0, // no interrupts
             });
-            regz.USART0.UCSR0C.write(.{
+            USART0.UCSR0C.write(.{
                 .UCPOL0 = 0, // async mode
                 .UCSZ0 = @truncate(u2, (ucsz & 0x03) >> 0),
                 .USBS0 = usbs,
@@ -163,29 +162,29 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
                 .UMSEL0 = umsel,
             });
 
-            regz.USART0.UBRR0.modify(ubrr_val);
+            USART0.UBRR0.modify(ubrr_val);
 
             return Self{};
         }
 
         pub fn canWrite(self: Self) bool {
             _ = self;
-            return (regz.USART0.UCSR0A.read().UDRE0 == 1);
+            return (USART0.UCSR0A.read().UDRE0 == 1);
         }
 
         pub fn tx(self: Self, ch: u8) void {
             while (!self.canWrite()) {} // Wait for Previous transmission
-            regz.USART0.UDR0.* = ch; // Load the data to be transmitted
+            USART0.UDR0.* = ch; // Load the data to be transmitted
         }
 
         pub fn canRead(self: Self) bool {
             _ = self;
-            return (regz.USART0.UCSR0A.read().RXC0 == 1);
+            return (USART0.UCSR0A.read().RXC0 == 1);
         }
 
         pub fn rx(self: Self) u8 {
             while (!self.canRead()) {} // Wait till the data is received
-            return regz.USART0.UDR0.*; // Read received data
+            return USART0.UDR0.*; // Read received data
         }
     };
 }

From 38d8d86941922bebb72d27edfc4daa9629c38629 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Fri, 24 Feb 2023 09:23:51 -0800
Subject: [PATCH 061/286] Update microzig (#3)

* update microzig

* update paths

---------

Co-authored-by: mattnite 
---
 build.zig              |  2 +-
 deps/microzig          |  2 +-
 src/boards.zig         |  2 +-
 src/chips.zig          |  2 +-
 src/hals/LPC176x5x.zig | 48 +++++++++++++++++++++++-------------------
 5 files changed, 30 insertions(+), 26 deletions(-)

diff --git a/build.zig b/build.zig
index 3b787fe3f..30cd9c99e 100644
--- a/build.zig
+++ b/build.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/src/main.zig");
+const microzig = @import("deps/microzig/build.zig");
 const boards = @import("src/boards.zig");
 const chips = @import("src/chips.zig");
 
diff --git a/deps/microzig b/deps/microzig
index 831cfff35..11214ed8b 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec
+Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
diff --git a/src/boards.zig b/src/boards.zig
index 1690f0d93..9890a0c00 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const micro = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/build.zig");
 const chips = @import("chips.zig");
 
 fn root_dir() []const u8 {
diff --git a/src/chips.zig b/src/chips.zig
index 0e8592591..741fabadb 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const micro = @import("../deps/microzig/src/main.zig");
+const micro = @import("../deps/microzig/build.zig");
 const Chip = micro.Chip;
 const MemoryRegion = micro.MemoryRegion;
 
diff --git a/src/hals/LPC176x5x.zig b/src/hals/LPC176x5x.zig
index 3db032e0e..8202d52ba 100644
--- a/src/hals/LPC176x5x.zig
+++ b/src/hals/LPC176x5x.zig
@@ -1,9 +1,13 @@
 const std = @import("std");
 const micro = @import("microzig");
-const chip = @import("registers.zig");
-const regs = chip.registers;
-
-pub usingnamespace chip;
+const peripherals = micro.chip.peripherals;
+const GPIO = peripherals.GPIO;
+const PINCONNECT = peripherals.PINCONNECT;
+const UART0 = peripherals.UART0;
+const UART1 = peripherals.UART1;
+const UART2 = peripherals.UART2;
+const UART3 = peripherals.UART3;
+const SYSCON = peripherals.SYSCON;
 
 pub const clock = struct {
     pub const Domain = enum {
@@ -37,14 +41,14 @@ pub fn parse_pin(comptime spec: []const u8) type {
     const _regs = struct {
         const name_suffix = std.fmt.comptimePrint("{d}", .{_port});
 
-        const pinsel_reg = @field(regs.PINCONNECT, sel_reg_name);
+        const pinsel_reg = @field(PINCONNECT, sel_reg_name);
         const pinsel_field = std.fmt.comptimePrint("P{d}_{d}", .{ _port, _pin });
 
-        const dir = @field(regs.GPIO, "DIR" ++ name_suffix);
-        const pin = @field(regs.GPIO, "PIN" ++ name_suffix);
-        const set = @field(regs.GPIO, "SET" ++ name_suffix);
-        const clr = @field(regs.GPIO, "CLR" ++ name_suffix);
-        const mask = @field(regs.GPIO, "MASK" ++ name_suffix);
+        const dir = @field(GPIO, "DIR" ++ name_suffix);
+        const pin = @field(GPIO, "PIN" ++ name_suffix);
+        const set = @field(GPIO, "SET" ++ name_suffix);
+        const clr = @field(GPIO, "CLR" ++ name_suffix);
+        const mask = @field(GPIO, "MASK" ++ name_suffix);
     };
 
     return struct {
@@ -121,10 +125,10 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
 
     return struct {
         const UARTn = switch (index) {
-            0 => regs.UART0,
-            1 => regs.UART1,
-            2 => regs.UART2,
-            3 => regs.UART3,
+            0 => UART0,
+            1 => UART1,
+            2 => UART2,
+            3 => UART3,
             else => @compileError("LPC1768 has 4 UARTs available."),
         };
         const Self = @This();
@@ -133,20 +137,20 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
             micro.debug.write("0");
             switch (index) {
                 0 => {
-                    regs.SYSCON.PCONP.modify(.{ .PCUART0 = 1 });
-                    regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = @enumToInt(uart.CClkDiv.four) });
+                    SYSCON.PCONP.modify(.{ .PCUART0 = 1 });
+                    SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = @enumToInt(uart.CClkDiv.four) });
                 },
                 1 => {
-                    regs.SYSCON.PCONP.modify(.{ .PCUART1 = 1 });
-                    regs.SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = @enumToInt(uart.CClkDiv.four) });
+                    SYSCON.PCONP.modify(.{ .PCUART1 = 1 });
+                    SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = @enumToInt(uart.CClkDiv.four) });
                 },
                 2 => {
-                    regs.SYSCON.PCONP.modify(.{ .PCUART2 = 1 });
-                    regs.SYSCON.PCLKSEL1.modify(.{ .PCLK_UART2 = @enumToInt(uart.CClkDiv.four) });
+                    SYSCON.PCONP.modify(.{ .PCUART2 = 1 });
+                    SYSCON.PCLKSEL1.modify(.{ .PCLK_UART2 = @enumToInt(uart.CClkDiv.four) });
                 },
                 3 => {
-                    regs.SYSCON.PCONP.modify(.{ .PCUART3 = 1 });
-                    regs.SYSCON.PCLKSEL1.modify(.{ .PCLK_UART3 = @enumToInt(uart.CClkDiv.four) });
+                    SYSCON.PCONP.modify(.{ .PCUART3 = 1 });
+                    SYSCON.PCLKSEL1.modify(.{ .PCLK_UART3 = @enumToInt(uart.CClkDiv.four) });
                 },
                 else => unreachable,
             }

From 31613f43a145b46be4ed140e0a538b5da447320c Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:26:10 -0800
Subject: [PATCH 062/286] Update microzig (#4)

* update microzig

* update to new api

---------

Co-authored-by: mattnite 
---
 build.zig     | 35 +++++++++++++++++++----------------
 deps/microzig |  2 +-
 2 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/build.zig b/build.zig
index 30cd9c99e..86ad2161d 100644
--- a/build.zig
+++ b/build.zig
@@ -1,7 +1,8 @@
 const std = @import("std");
 const microzig = @import("deps/microzig/build.zig");
-const boards = @import("src/boards.zig");
-const chips = @import("src/chips.zig");
+
+pub const boards = @import("src/boards.zig");
+pub const chips = @import("src/chips.zig");
 
 pub fn build(b: *std.build.Builder) void {
     const optimize = b.standardOptimizeOption(.{});
@@ -9,13 +10,14 @@ pub fn build(b: *std.build.Builder) void {
         if (!decl.is_pub)
             continue;
 
-        const exe = microzig.addEmbeddedExecutable(
-            b,
-            @field(boards, decl.name).name ++ ".minimal",
-            "test/programs/minimal.zig",
-            .{ .board = @field(boards, decl.name) },
-            .{ .optimize = optimize },
-        );
+        const exe = microzig.addEmbeddedExecutable(b, .{
+            .name = @field(boards, decl.name).name ++ ".minimal",
+            .source_file = .{
+                .path = "test/programs/minimal.zig",
+            },
+            .backing = .{ .board = @field(boards, decl.name) },
+            .optimize = optimize,
+        });
         exe.install();
     }
 
@@ -23,13 +25,14 @@ pub fn build(b: *std.build.Builder) void {
         if (!decl.is_pub)
             continue;
 
-        const exe = microzig.addEmbeddedExecutable(
-            b,
-            @field(chips, decl.name).name ++ ".minimal",
-            "test/programs/minimal.zig",
-            .{ .chip = @field(chips, decl.name) },
-            .{ .optimize = optimize },
-        );
+        const exe = microzig.addEmbeddedExecutable(b, .{
+            .name = @field(chips, decl.name).name ++ ".minimal",
+            .source_file = .{
+                .path = "test/programs/minimal.zig",
+            },
+            .backing = .{ .chip = @field(chips, decl.name) },
+            .optimize = optimize,
+        });
         exe.install();
     }
 }
diff --git a/deps/microzig b/deps/microzig
index 11214ed8b..b6fc3abbf 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
+Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84

From 1a9e4cdbc3c2cfdd3ecfef1df447d67283f1f7b5 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:26:24 -0800
Subject: [PATCH 063/286] Update microzig (#4)

* update microzig

* update to new api

---------

Co-authored-by: mattnite 
---
 build.zig     | 35 +++++++++++++++++++----------------
 deps/microzig |  2 +-
 2 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/build.zig b/build.zig
index 30cd9c99e..86ad2161d 100644
--- a/build.zig
+++ b/build.zig
@@ -1,7 +1,8 @@
 const std = @import("std");
 const microzig = @import("deps/microzig/build.zig");
-const boards = @import("src/boards.zig");
-const chips = @import("src/chips.zig");
+
+pub const boards = @import("src/boards.zig");
+pub const chips = @import("src/chips.zig");
 
 pub fn build(b: *std.build.Builder) void {
     const optimize = b.standardOptimizeOption(.{});
@@ -9,13 +10,14 @@ pub fn build(b: *std.build.Builder) void {
         if (!decl.is_pub)
             continue;
 
-        const exe = microzig.addEmbeddedExecutable(
-            b,
-            @field(boards, decl.name).name ++ ".minimal",
-            "test/programs/minimal.zig",
-            .{ .board = @field(boards, decl.name) },
-            .{ .optimize = optimize },
-        );
+        const exe = microzig.addEmbeddedExecutable(b, .{
+            .name = @field(boards, decl.name).name ++ ".minimal",
+            .source_file = .{
+                .path = "test/programs/minimal.zig",
+            },
+            .backing = .{ .board = @field(boards, decl.name) },
+            .optimize = optimize,
+        });
         exe.install();
     }
 
@@ -23,13 +25,14 @@ pub fn build(b: *std.build.Builder) void {
         if (!decl.is_pub)
             continue;
 
-        const exe = microzig.addEmbeddedExecutable(
-            b,
-            @field(chips, decl.name).name ++ ".minimal",
-            "test/programs/minimal.zig",
-            .{ .chip = @field(chips, decl.name) },
-            .{ .optimize = optimize },
-        );
+        const exe = microzig.addEmbeddedExecutable(b, .{
+            .name = @field(chips, decl.name).name ++ ".minimal",
+            .source_file = .{
+                .path = "test/programs/minimal.zig",
+            },
+            .backing = .{ .chip = @field(chips, decl.name) },
+            .optimize = optimize,
+        });
         exe.install();
     }
 }
diff --git a/deps/microzig b/deps/microzig
index 11214ed8b..b6fc3abbf 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
+Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84

From 44ac467baa882c755a7d102efc437cc42eba578f Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:32:24 -0800
Subject: [PATCH 064/286] Update microzig (#4)

* update microzig

* update to new api

---------

Co-authored-by: mattnite 
---
 build.zig     | 35 +++++++++++++++++++----------------
 deps/microzig |  2 +-
 2 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/build.zig b/build.zig
index 30cd9c99e..86ad2161d 100644
--- a/build.zig
+++ b/build.zig
@@ -1,7 +1,8 @@
 const std = @import("std");
 const microzig = @import("deps/microzig/build.zig");
-const boards = @import("src/boards.zig");
-const chips = @import("src/chips.zig");
+
+pub const boards = @import("src/boards.zig");
+pub const chips = @import("src/chips.zig");
 
 pub fn build(b: *std.build.Builder) void {
     const optimize = b.standardOptimizeOption(.{});
@@ -9,13 +10,14 @@ pub fn build(b: *std.build.Builder) void {
         if (!decl.is_pub)
             continue;
 
-        const exe = microzig.addEmbeddedExecutable(
-            b,
-            @field(boards, decl.name).name ++ ".minimal",
-            "test/programs/minimal.zig",
-            .{ .board = @field(boards, decl.name) },
-            .{ .optimize = optimize },
-        );
+        const exe = microzig.addEmbeddedExecutable(b, .{
+            .name = @field(boards, decl.name).name ++ ".minimal",
+            .source_file = .{
+                .path = "test/programs/minimal.zig",
+            },
+            .backing = .{ .board = @field(boards, decl.name) },
+            .optimize = optimize,
+        });
         exe.install();
     }
 
@@ -23,13 +25,14 @@ pub fn build(b: *std.build.Builder) void {
         if (!decl.is_pub)
             continue;
 
-        const exe = microzig.addEmbeddedExecutable(
-            b,
-            @field(chips, decl.name).name ++ ".minimal",
-            "test/programs/minimal.zig",
-            .{ .chip = @field(chips, decl.name) },
-            .{ .optimize = optimize },
-        );
+        const exe = microzig.addEmbeddedExecutable(b, .{
+            .name = @field(chips, decl.name).name ++ ".minimal",
+            .source_file = .{
+                .path = "test/programs/minimal.zig",
+            },
+            .backing = .{ .chip = @field(chips, decl.name) },
+            .optimize = optimize,
+        });
         exe.install();
     }
 }
diff --git a/deps/microzig b/deps/microzig
index 11214ed8b..b6fc3abbf 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
+Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84

From 3b129e1ca5ce7317e29f50cb1beaf67ce6281122 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:32:34 -0800
Subject: [PATCH 065/286] Update microzig (#26)

* update microzig

* update to new api

---------

Co-authored-by: mattnite 
---
 build.zig         | 45 ++++++++++++++++++++++-----------------------
 deps/microzig     |  2 +-
 examples/adc.zig  |  4 +++-
 examples/uart.zig |  6 ++++--
 4 files changed, 30 insertions(+), 27 deletions(-)

diff --git a/build.zig b/build.zig
index a0ed86cf1..5da87f7b7 100644
--- a/build.zig
+++ b/build.zig
@@ -2,11 +2,12 @@ const std = @import("std");
 const Builder = std.build.Builder;
 const Pkg = std.build.Pkg;
 const comptimePrint = std.fmt.comptimePrint;
+const FileSource = std.build.FileSource;
 
 pub const microzig = @import("deps/microzig/build.zig");
 
-const chips = @import("src/chips.zig");
-const boards = @import("src/boards.zig");
+pub const chips = @import("src/chips.zig");
+pub const boards = @import("src/boards.zig");
 
 const linkerscript_path = root() ++ "rp2040.ld";
 
@@ -14,24 +15,23 @@ pub const BuildOptions = struct {
     optimize: std.builtin.OptimizeMode,
 };
 
+pub const PicoExecutableOptions = struct {
+    name: []const u8,
+    source_file: FileSource,
+    optimize: std.builtin.OptimizeMode = .Debug,
+};
+
 pub fn addPiPicoExecutable(
     builder: *Builder,
-    name: []const u8,
-    source: []const u8,
-    options: BuildOptions,
+    opts: PicoExecutableOptions,
 ) *microzig.EmbeddedExecutable {
-    const ret = microzig.addEmbeddedExecutable(
-        builder,
-        name,
-        source,
-        .{ .board = boards.raspberry_pi_pico },
-        .{
-            .optimize = options.optimize,
-        },
-    );
-    ret.inner.setLinkerScriptPath(.{ .path = linkerscript_path });
-
-    return ret;
+    return microzig.addEmbeddedExecutable(builder, .{
+        .name = opts.name,
+        .source_file = opts.source_file,
+        .backing = .{ .board = boards.raspberry_pi_pico },
+        .optimize = opts.optimize,
+        .linkerscript_source_file = .{ .path = linkerscript_path },
+    });
 }
 
 // this build script is mostly for testing and verification of this
@@ -61,12 +61,11 @@ pub const Examples = struct {
         inline for (@typeInfo(Examples).Struct.fields) |field| {
             const path = comptime root() ++ "examples/" ++ field.name ++ ".zig";
 
-            @field(ret, field.name) = addPiPicoExecutable(
-                b,
-                field.name,
-                path,
-                .{ .optimize = optimize },
-            );
+            @field(ret, field.name) = addPiPicoExecutable(b, .{
+                .name = field.name,
+                .source_file = .{ .path = path },
+                .optimize = optimize,
+            });
         }
 
         return ret;
diff --git a/deps/microzig b/deps/microzig
index 11214ed8b..b6fc3abbf 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
+Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84
diff --git a/examples/adc.zig b/examples/adc.zig
index 9800e9157..5d8f0c3eb 100644
--- a/examples/adc.zig
+++ b/examples/adc.zig
@@ -12,7 +12,9 @@ const baud_rate = 115200;
 const uart_tx_pin = 0;
 const uart_rx_pin = 1;
 
-pub const log = rp2040.uart.log;
+pub const std_options = struct {
+    pub const logFn = rp2040.uart.log;
+};
 
 pub fn init() void {
     rp2040.clock_config.apply();
diff --git a/examples/uart.zig b/examples/uart.zig
index 6eb086415..57cf1c49f 100644
--- a/examples/uart.zig
+++ b/examples/uart.zig
@@ -18,8 +18,10 @@ pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noretu
     while (true) {}
 }
 
-pub const log_level = .debug;
-pub const log = rp2040.uart.log;
+pub const std_options = struct {
+    pub const log_level = .debug;
+    pub const logFn = rp2040.uart.log;
+};
 
 pub fn main() !void {
     gpio.reset();

From 50429bcc852c2574c280dc2c4b50107c57f98976 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:37:10 -0800
Subject: [PATCH 066/286] Update microzig (#4)

* update microzig

* update to new api

---------

Co-authored-by: mattnite 
---
 build.zig     | 35 +++++++++++++++++++----------------
 deps/microzig |  2 +-
 2 files changed, 20 insertions(+), 17 deletions(-)

diff --git a/build.zig b/build.zig
index 30cd9c99e..86ad2161d 100644
--- a/build.zig
+++ b/build.zig
@@ -1,7 +1,8 @@
 const std = @import("std");
 const microzig = @import("deps/microzig/build.zig");
-const boards = @import("src/boards.zig");
-const chips = @import("src/chips.zig");
+
+pub const boards = @import("src/boards.zig");
+pub const chips = @import("src/chips.zig");
 
 pub fn build(b: *std.build.Builder) void {
     const optimize = b.standardOptimizeOption(.{});
@@ -9,13 +10,14 @@ pub fn build(b: *std.build.Builder) void {
         if (!decl.is_pub)
             continue;
 
-        const exe = microzig.addEmbeddedExecutable(
-            b,
-            @field(boards, decl.name).name ++ ".minimal",
-            "test/programs/minimal.zig",
-            .{ .board = @field(boards, decl.name) },
-            .{ .optimize = optimize },
-        );
+        const exe = microzig.addEmbeddedExecutable(b, .{
+            .name = @field(boards, decl.name).name ++ ".minimal",
+            .source_file = .{
+                .path = "test/programs/minimal.zig",
+            },
+            .backing = .{ .board = @field(boards, decl.name) },
+            .optimize = optimize,
+        });
         exe.install();
     }
 
@@ -23,13 +25,14 @@ pub fn build(b: *std.build.Builder) void {
         if (!decl.is_pub)
             continue;
 
-        const exe = microzig.addEmbeddedExecutable(
-            b,
-            @field(chips, decl.name).name ++ ".minimal",
-            "test/programs/minimal.zig",
-            .{ .chip = @field(chips, decl.name) },
-            .{ .optimize = optimize },
-        );
+        const exe = microzig.addEmbeddedExecutable(b, .{
+            .name = @field(chips, decl.name).name ++ ".minimal",
+            .source_file = .{
+                .path = "test/programs/minimal.zig",
+            },
+            .backing = .{ .chip = @field(chips, decl.name) },
+            .optimize = optimize,
+        });
         exe.install();
     }
 }
diff --git a/deps/microzig b/deps/microzig
index 11214ed8b..b6fc3abbf 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
+Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84

From 92d7d14d124c799f20c3074633565993fbc2585b Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:37:40 -0800
Subject: [PATCH 067/286] Update microzig (#3)

* update microzig

* update to new api

---------

Co-authored-by: mattnite 
---
 build.zig     | 25 ++++++++++++++++---------
 deps/microzig |  2 +-
 2 files changed, 17 insertions(+), 10 deletions(-)

diff --git a/build.zig b/build.zig
index c0d71db84..dd5a65c3d 100644
--- a/build.zig
+++ b/build.zig
@@ -2,7 +2,7 @@ const std = @import("std");
 const microzig = @import("zpm.zig").sdks.microzig;
 
 pub fn build(b: *std.build.Builder) void {
-    const mode = b.standardReleaseOptions();
+    const optimize = b.standardOptimizeOption(.{});
 
     const esp32_c3_cpu = microzig.Cpu{
         .name = "Espressif RISC-V",
@@ -21,7 +21,13 @@ pub fn build(b: *std.build.Builder) void {
 
     const esp32_c3 = microzig.Chip{
         .name = "ESP32 C3",
-        .path = "src/package/esp32-c3.zig",
+        .source = .{
+            .path = "src/package/esp32-c3.zig",
+        },
+        .hal = .{
+            .source = "src/hal/root.zig",
+        },
+
         .cpu = esp32_c3_cpu,
         .memory_regions = &.{
             .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
@@ -29,13 +35,14 @@ pub fn build(b: *std.build.Builder) void {
         },
     };
 
-    var exe = microzig.addEmbeddedExecutable(
-        b,
-        "esp-bringup",
-        "src/example/blinky.zig",
-        .{ .chip = esp32_c3 },
-        .{ .hal_package_path = .{ .path = "src/hal/root.zig" } },
-    );
+    var exe = microzig.addEmbeddedExecutable(b, .{
+        .name = "esp-bringup",
+        .source_file = .{
+            .path = "src/example/blinky.zig",
+        },
+        .backing = .{ .chip = esp32_c3 },
+        .optimize = optimize,
+    });
     exe.setBuildMode(mode);
     exe.install();
 
diff --git a/deps/microzig b/deps/microzig
index 831cfff35..b6fc3abbf 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 831cfff35c259d68ee023ba7bb94dae8b7b94bec
+Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84

From 359e25db56a2c932692cab1ad3f45091aabce014 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:45:54 -0800
Subject: [PATCH 068/286] update microzig (#5)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b6fc3abbf..08e7d5b01 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84
+Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725

From d31c4ce02ce4e8f1be9e7fc6b730e1d7a4aa7639 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:46:06 -0800
Subject: [PATCH 069/286] update microzig (#5)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b6fc3abbf..08e7d5b01 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84
+Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725

From b60328ea97e2a1951cdc201056bac3e6740cda00 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:46:17 -0800
Subject: [PATCH 070/286] update microzig (#5)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b6fc3abbf..08e7d5b01 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84
+Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725

From 52092330a2a251962bf8681f0148b5dafb682c4a Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:46:44 -0800
Subject: [PATCH 071/286] update microzig (#4)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b6fc3abbf..08e7d5b01 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84
+Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725

From 9a47a0183e58d68ff3889147c99e0789292bdf7f Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:47:34 -0800
Subject: [PATCH 072/286] update microzig (#27)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b6fc3abbf..08e7d5b01 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84
+Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725

From 5570bfa13f464b47f53755428c9bfc1d4f4f428d Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:47:45 -0800
Subject: [PATCH 073/286] update microzig (#5)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b6fc3abbf..08e7d5b01 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b6fc3abbf7a91cb0cdafc7843ac7e6c26042ff84
+Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725

From 2872b218e0c21d9f023b81360407cb173e8becd0 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 28 Feb 2023 01:47:56 -0800
Subject: [PATCH 074/286] Update microzig (#5)

* update microzig

* update to new api

---------

Co-authored-by: mattnite 
---
 build.zig     | 18 ++++++++++--------
 deps/microzig |  2 +-
 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/build.zig b/build.zig
index d6590025b..edb8df879 100644
--- a/build.zig
+++ b/build.zig
@@ -1,6 +1,7 @@
 const std = @import("std");
 const microzig = @import("deps/microzig/build.zig");
-const chips = @import("src/chips.zig");
+
+pub const chips = @import("src/chips.zig");
 
 pub fn build(b: *std.build.Builder) void {
     const optimize = b.standardOptimizeOption(.{});
@@ -8,13 +9,14 @@ pub fn build(b: *std.build.Builder) void {
         if (!decl.is_pub)
             continue;
 
-        const exe = microzig.addEmbeddedExecutable(
-            b,
-            decl.name ++ ".minimal",
-            "test/programs/minimal.zig",
-            .{ .chip = @field(chips, decl.name) },
-            .{ .optimize = optimize },
-        );
+        const exe = microzig.addEmbeddedExecutable(b, .{
+            .name = decl.name ++ ".minimal",
+            .source_file = .{
+                .path = "test/programs/minimal.zig",
+            },
+            .backing = .{ .chip = @field(chips, decl.name) },
+            .optimize = optimize,
+        });
         exe.install();
     }
 }
diff --git a/deps/microzig b/deps/microzig
index 11214ed8b..08e7d5b01 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 11214ed8ba05e380a516beef3f3f594571a1c732
+Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725

From 2381f96b9afee214b3e7f84beab937038e0b947b Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 2 Mar 2023 01:13:42 -0800
Subject: [PATCH 075/286] organzie (#5)

* organzie

* add buildkite pipeline
---
 .buildkite/pipeline.yml                       |     4 +
 build.zig                                     |    43 +-
 src/chips.zig                                 |    23 +
 src/chips/ESP32_C3.json                       | 33570 ++++++++++++++
 src/chips/ESP32_C3.zig                        | 12378 +++++
 src/cpus.zig                                  |    23 +
 .../esp32-c3.zig => cpus/espressif-riscv.zig} |    38 +-
 src/example/blinky.zig                        |    37 +-
 src/{hal/root.zig => hals/ESP32_C3.zig}       |    23 +-
 src/package/espressif-riscv.zig               |    39 -
 src/package/registers.zig                     | 37956 ----------------
 11 files changed, 46068 insertions(+), 38066 deletions(-)
 create mode 100644 .buildkite/pipeline.yml
 create mode 100644 src/chips.zig
 create mode 100644 src/chips/ESP32_C3.json
 create mode 100644 src/chips/ESP32_C3.zig
 create mode 100644 src/cpus.zig
 rename src/{package/esp32-c3.zig => cpus/espressif-riscv.zig} (72%)
 rename src/{hal/root.zig => hals/ESP32_C3.zig} (57%)
 delete mode 100644 src/package/espressif-riscv.zig
 delete mode 100644 src/package/registers.zig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
new file mode 100644
index 000000000..7767bbb66
--- /dev/null
+++ b/.buildkite/pipeline.yml
@@ -0,0 +1,4 @@
+steps:
+  - group: Build
+    steps:
+    - command: zig build
diff --git a/build.zig b/build.zig
index dd5a65c3d..f96f446c5 100644
--- a/build.zig
+++ b/build.zig
@@ -1,52 +1,19 @@
 const std = @import("std");
-const microzig = @import("zpm.zig").sdks.microzig;
+const microzig = @import("deps/microzig/build.zig");
+
+pub const chips = @import("src/chips.zig");
+pub const cpus = @import("src/cpus.zig");
 
 pub fn build(b: *std.build.Builder) void {
     const optimize = b.standardOptimizeOption(.{});
 
-    const esp32_c3_cpu = microzig.Cpu{
-        .name = "Espressif RISC-V",
-        .path = "src/package/espressif-riscv.zig",
-        .target = std.zig.CrossTarget{
-            .cpu_arch = .riscv32,
-            .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
-            .cpu_features_add = std.Target.riscv.featureSet(&.{
-                std.Target.riscv.Feature.c,
-                std.Target.riscv.Feature.m,
-            }),
-            .os_tag = .freestanding,
-            .abi = .eabi,
-        },
-    };
-
-    const esp32_c3 = microzig.Chip{
-        .name = "ESP32 C3",
-        .source = .{
-            .path = "src/package/esp32-c3.zig",
-        },
-        .hal = .{
-            .source = "src/hal/root.zig",
-        },
-
-        .cpu = esp32_c3_cpu,
-        .memory_regions = &.{
-            .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
-            .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
-        },
-    };
-
     var exe = microzig.addEmbeddedExecutable(b, .{
         .name = "esp-bringup",
         .source_file = .{
             .path = "src/example/blinky.zig",
         },
-        .backing = .{ .chip = esp32_c3 },
+        .backing = .{ .chip = chips.esp32_c3 },
         .optimize = optimize,
     });
-    exe.setBuildMode(mode);
     exe.install();
-
-    const raw_step = exe.installRaw("firmware.bin", .{});
-
-    b.getInstallStep().dependOn(&raw_step.step);
 }
diff --git a/src/chips.zig b/src/chips.zig
new file mode 100644
index 000000000..14769f383
--- /dev/null
+++ b/src/chips.zig
@@ -0,0 +1,23 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/build.zig");
+const cpus = @import("cpus.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse unreachable;
+}
+
+pub const esp32_c3 = microzig.Chip{
+    .name = "ESP32-C3",
+    .source = .{
+        .path = root_dir() ++ "/chips/ESP32_C3.zig",
+    },
+    .hal = .{
+        .path = root_dir() ++ "/hals/ESP32_C3.zig",
+    },
+
+    .cpu = cpus.esp32_c3,
+    .memory_regions = &.{
+        .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
+        .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
+    },
+};
diff --git a/src/chips/ESP32_C3.json b/src/chips/ESP32_C3.json
new file mode 100644
index 000000000..4691dc788
--- /dev/null
+++ b/src/chips/ESP32_C3.json
@@ -0,0 +1,33570 @@
+{
+  "version": "0.1.0",
+  "types": {
+    "peripherals": {
+      "AES": {
+        "description": "AES (Advanced Encryption Standard) Accelerator",
+        "children": {
+          "registers": {
+            "KEY_0": {
+              "description": "Key material key_0 configure register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_0": {
+                    "description": "This bits stores key_0 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_1": {
+              "description": "Key material key_1 configure register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_1": {
+                    "description": "This bits stores key_1 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_2": {
+              "description": "Key material key_2 configure register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_2": {
+                    "description": "This bits stores key_2 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_3": {
+              "description": "Key material key_3 configure register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_3": {
+                    "description": "This bits stores key_3 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_4": {
+              "description": "Key material key_4 configure register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_4": {
+                    "description": "This bits stores key_4 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_5": {
+              "description": "Key material key_5 configure register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_5": {
+                    "description": "This bits stores key_5 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_6": {
+              "description": "Key material key_6 configure register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_6": {
+                    "description": "This bits stores key_6 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "KEY_7": {
+              "description": "Key material key_7 configure register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_7": {
+                    "description": "This bits stores key_7 that is a part of key material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_IN_0": {
+              "description": "source text material text_in_0 configure register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_IN_0": {
+                    "description": "This bits stores text_in_0 that is a part of source text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_IN_1": {
+              "description": "source text material text_in_1 configure register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_IN_1": {
+                    "description": "This bits stores text_in_1 that is a part of source text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_IN_2": {
+              "description": "source text material text_in_2 configure register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_IN_2": {
+                    "description": "This bits stores text_in_2 that is a part of source text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_IN_3": {
+              "description": "source text material text_in_3 configure register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_IN_3": {
+                    "description": "This bits stores text_in_3 that is a part of source text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_OUT_0": {
+              "description": "result text material text_out_0 configure register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_OUT_0": {
+                    "description": "This bits stores text_out_0 that is a part of result text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_OUT_1": {
+              "description": "result text material text_out_1 configure register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_OUT_1": {
+                    "description": "This bits stores text_out_1 that is a part of result text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_OUT_2": {
+              "description": "result text material text_out_2 configure register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_OUT_2": {
+                    "description": "This bits stores text_out_2 that is a part of result text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TEXT_OUT_3": {
+              "description": "result text material text_out_3 configure register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TEXT_OUT_3": {
+                    "description": "This bits stores text_out_3 that is a part of result text material.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "AES Mode register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "ENDIAN": {
+              "description": "AES Endian configure register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENDIAN": {
+                    "description": "endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out endian or out_stream endian",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "TRIGGER": {
+              "description": "AES trigger register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRIGGER": {
+                    "description": "Set this bit to start AES calculation.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STATE": {
+              "description": "AES state register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATE": {
+                    "description": "Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IV_MEM": {
+              "description": "The memory that stores initialization vector",
+              "offset": 80,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "H_MEM": {
+              "description": "The memory that stores GCM hash subkey",
+              "offset": 96,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "J0_MEM": {
+              "description": "The memory that stores J0",
+              "offset": 112,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "T0_MEM": {
+              "description": "The memory that stores T0",
+              "offset": 128,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "DMA_ENABLE": {
+              "description": "DMA-AES working mode register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_ENABLE": {
+                    "description": "1'b0: typical AES working mode, 1'b1: DMA-AES working mode.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BLOCK_MODE": {
+              "description": "AES cipher block mode register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BLOCK_MODE": {
+                    "description": "Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "BLOCK_NUM": {
+              "description": "AES block number register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BLOCK_NUM": {
+                    "description": "Those bits stores the number of Plaintext/ciphertext block.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "INC_SEL": {
+              "description": "Standard incrementing function configure register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INC_SEL": {
+                    "description": "This bit decides the standard incrementing function. 0: INC32. 1: INC128.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "AAD_BLOCK_NUM": {
+              "description": "Additional Authential Data block number register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AAD_BLOCK_NUM": {
+                    "description": "Those bits stores the number of AAD block.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "REMAINDER_BIT_NUM": {
+              "description": "AES remainder bit number register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REMAINDER_BIT_NUM": {
+                    "description": "Those bits stores the number of remainder bit.",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "CONTINUE": {
+              "description": "AES continue register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONTINUE": {
+                    "description": "Set this bit to continue GCM operation.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_CLEAR": {
+              "description": "AES Interrupt clear register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INT_CLEAR": {
+                    "description": "Set this bit to clear the AES interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "AES Interrupt enable register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INT_ENA": {
+                    "description": "Set this bit to enable interrupt that occurs when DMA-AES calculation is done.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "AES version control register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 538513936,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "This bits stores the version information of AES.",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "DMA_EXIT": {
+              "description": "AES-DMA exit config",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_EXIT": {
+                    "description": "Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "APB_CTRL": {
+        "description": "Advanced Peripheral Bus Controller",
+        "children": {
+          "registers": {
+            "SYSCLK_CONF": {
+              "description": "APB_CTRL_SYSCLK_CONF_REG",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRE_DIV_CNT": {
+                    "description": "reg_pre_div_cnt",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "CLK_320M_EN": {
+                    "description": "reg_clk_320m_en",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RST_TICK_CNT": {
+                    "description": "reg_rst_tick_cnt",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TICK_CONF": {
+              "description": "APB_CTRL_TICK_CONF_REG",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 67367,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XTAL_TICK_NUM": {
+                    "description": "reg_xtal_tick_num",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CK8M_TICK_NUM": {
+                    "description": "reg_ck8m_tick_num",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "TICK_ENABLE": {
+                    "description": "reg_tick_enable",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLK_OUT_EN": {
+              "description": "APB_CTRL_CLK_OUT_EN_REG",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 2047,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK20_OEN": {
+                    "description": "reg_clk20_oen",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CLK22_OEN": {
+                    "description": "reg_clk22_oen",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CLK44_OEN": {
+                    "description": "reg_clk44_oen",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CLK_BB_OEN": {
+                    "description": "reg_clk_bb_oen",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CLK80_OEN": {
+                    "description": "reg_clk80_oen",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CLK160_OEN": {
+                    "description": "reg_clk160_oen",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CLK_320M_OEN": {
+                    "description": "reg_clk_320m_oen",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CLK_ADC_INF_OEN": {
+                    "description": "reg_clk_adc_inf_oen",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CLK_DAC_CPU_OEN": {
+                    "description": "reg_clk_dac_cpu_oen",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CLK40X_BB_OEN": {
+                    "description": "reg_clk40x_bb_oen",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CLK_XTAL_OEN": {
+                    "description": "reg_clk_xtal_oen",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WIFI_BB_CFG": {
+              "description": "APB_CTRL_WIFI_BB_CFG_REG",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WIFI_BB_CFG": {
+                    "description": "reg_wifi_bb_cfg",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WIFI_BB_CFG_2": {
+              "description": "APB_CTRL_WIFI_BB_CFG_2_REG",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WIFI_BB_CFG_2": {
+                    "description": "reg_wifi_bb_cfg_2",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WIFI_CLK_EN": {
+              "description": "APB_CTRL_WIFI_CLK_EN_REG",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 4294762544,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WIFI_CLK_EN": {
+                    "description": "reg_wifi_clk_en",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WIFI_RST_EN": {
+              "description": "APB_CTRL_WIFI_RST_EN_REG",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WIFI_RST": {
+                    "description": "reg_wifi_rst",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "HOST_INF_SEL": {
+              "description": "APB_CTRL_HOST_INF_SEL_REG",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_IO_SWAP": {
+                    "description": "reg_peri_io_swap",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "EXT_MEM_PMS_LOCK": {
+              "description": "APB_CTRL_EXT_MEM_PMS_LOCK_REG",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EXT_MEM_PMS_LOCK": {
+                    "description": "reg_ext_mem_pms_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FLASH_ACE0_ATTR": {
+              "description": "APB_CTRL_FLASH_ACE0_ATTR_REG",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE0_ATTR": {
+                    "description": "reg_flash_ace0_attr",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FLASH_ACE1_ATTR": {
+              "description": "APB_CTRL_FLASH_ACE1_ATTR_REG",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE1_ATTR": {
+                    "description": "reg_flash_ace1_attr",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FLASH_ACE2_ATTR": {
+              "description": "APB_CTRL_FLASH_ACE2_ATTR_REG",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE2_ATTR": {
+                    "description": "reg_flash_ace2_attr",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FLASH_ACE3_ATTR": {
+              "description": "APB_CTRL_FLASH_ACE3_ATTR_REG",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE3_ATTR": {
+                    "description": "reg_flash_ace3_attr",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "FLASH_ACE0_ADDR": {
+              "description": "APB_CTRL_FLASH_ACE0_ADDR_REG",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "S": {
+                    "description": "reg_flash_ace0_addr_s",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FLASH_ACE1_ADDR": {
+              "description": "APB_CTRL_FLASH_ACE1_ADDR_REG",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 4194304,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "S": {
+                    "description": "reg_flash_ace1_addr_s",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FLASH_ACE2_ADDR": {
+              "description": "APB_CTRL_FLASH_ACE2_ADDR_REG",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "S": {
+                    "description": "reg_flash_ace2_addr_s",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FLASH_ACE3_ADDR": {
+              "description": "APB_CTRL_FLASH_ACE3_ADDR_REG",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 12582912,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "S": {
+                    "description": "reg_flash_ace3_addr_s",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FLASH_ACE0_SIZE": {
+              "description": "APB_CTRL_FLASH_ACE0_SIZE_REG",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 1024,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE0_SIZE": {
+                    "description": "reg_flash_ace0_size",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "FLASH_ACE1_SIZE": {
+              "description": "APB_CTRL_FLASH_ACE1_SIZE_REG",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 1024,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE1_SIZE": {
+                    "description": "reg_flash_ace1_size",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "FLASH_ACE2_SIZE": {
+              "description": "APB_CTRL_FLASH_ACE2_SIZE_REG",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 1024,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE2_SIZE": {
+                    "description": "reg_flash_ace2_size",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "FLASH_ACE3_SIZE": {
+              "description": "APB_CTRL_FLASH_ACE3_SIZE_REG",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 1024,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_ACE3_SIZE": {
+                    "description": "reg_flash_ace3_size",
+                    "offset": 0,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "SPI_MEM_PMS_CTRL": {
+              "description": "APB_CTRL_SPI_MEM_PMS_CTRL_REG",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_MEM_REJECT_INT": {
+                    "description": "reg_spi_mem_reject_int",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SPI_MEM_REJECT_CLR": {
+                    "description": "reg_spi_mem_reject_clr",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SPI_MEM_REJECT_CDE": {
+                    "description": "reg_spi_mem_reject_cde",
+                    "offset": 2,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SPI_MEM_REJECT_ADDR": {
+              "description": "APB_CTRL_SPI_MEM_REJECT_ADDR_REG",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_MEM_REJECT_ADDR": {
+                    "description": "reg_spi_mem_reject_addr",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SDIO_CTRL": {
+              "description": "APB_CTRL_SDIO_CTRL_REG",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDIO_WIN_ACCESS_EN": {
+                    "description": "reg_sdio_win_access_en",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REDCY_SIG0": {
+              "description": "APB_CTRL_REDCY_SIG0_REG",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REDCY_SIG0": {
+                    "description": "reg_redcy_sig0",
+                    "offset": 0,
+                    "size": 31
+                  },
+                  "REDCY_ANDOR": {
+                    "description": "reg_redcy_andor",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "REDCY_SIG1": {
+              "description": "APB_CTRL_REDCY_SIG1_REG",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REDCY_SIG1": {
+                    "description": "reg_redcy_sig1",
+                    "offset": 0,
+                    "size": 31
+                  },
+                  "REDCY_NANDOR": {
+                    "description": "reg_redcy_nandor",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FRONT_END_MEM_PD": {
+              "description": "APB_CTRL_FRONT_END_MEM_PD_REG",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 21,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AGC_MEM_FORCE_PU": {
+                    "description": "reg_agc_mem_force_pu",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "AGC_MEM_FORCE_PD": {
+                    "description": "reg_agc_mem_force_pd",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PBUS_MEM_FORCE_PU": {
+                    "description": "reg_pbus_mem_force_pu",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PBUS_MEM_FORCE_PD": {
+                    "description": "reg_pbus_mem_force_pd",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DC_MEM_FORCE_PU": {
+                    "description": "reg_dc_mem_force_pu",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DC_MEM_FORCE_PD": {
+                    "description": "reg_dc_mem_force_pd",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RETENTION_CTRL": {
+              "description": "APB_CTRL_RETENTION_CTRL_REG",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RETENTION_LINK_ADDR": {
+                    "description": "reg_retention_link_addr",
+                    "offset": 0,
+                    "size": 27
+                  },
+                  "NOBYPASS_CPU_ISO_RST": {
+                    "description": "reg_nobypass_cpu_iso_rst",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLKGATE_FORCE_ON": {
+              "description": "APB_CTRL_CLKGATE_FORCE_ON_REG",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ROM_CLKGATE_FORCE_ON": {
+                    "description": "reg_rom_clkgate_force_on",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SRAM_CLKGATE_FORCE_ON": {
+                    "description": "reg_sram_clkgate_force_on",
+                    "offset": 2,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MEM_POWER_DOWN": {
+              "description": "APB_CTRL_MEM_POWER_DOWN_REG",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ROM_POWER_DOWN": {
+                    "description": "reg_rom_power_down",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SRAM_POWER_DOWN": {
+                    "description": "reg_sram_power_down",
+                    "offset": 2,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MEM_POWER_UP": {
+              "description": "APB_CTRL_MEM_POWER_UP_REG",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ROM_POWER_UP": {
+                    "description": "reg_rom_power_up",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SRAM_POWER_UP": {
+                    "description": "reg_sram_power_up",
+                    "offset": 2,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RND_DATA": {
+              "description": "APB_CTRL_RND_DATA_REG",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RND_DATA": {
+                    "description": "reg_rnd_data",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_CONFIG": {
+              "description": "APB_CTRL_PERI_BACKUP_CONFIG_REG",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 25728,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_BACKUP_FLOW_ERR": {
+                    "description": "reg_peri_backup_flow_err",
+                    "offset": 1,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PERI_BACKUP_BURST_LIMIT": {
+                    "description": "reg_peri_backup_burst_limit",
+                    "offset": 4,
+                    "size": 5
+                  },
+                  "PERI_BACKUP_TOUT_THRES": {
+                    "description": "reg_peri_backup_tout_thres",
+                    "offset": 9,
+                    "size": 10
+                  },
+                  "PERI_BACKUP_SIZE": {
+                    "description": "reg_peri_backup_size",
+                    "offset": 19,
+                    "size": 10
+                  },
+                  "PERI_BACKUP_START": {
+                    "description": "reg_peri_backup_start",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PERI_BACKUP_TO_MEM": {
+                    "description": "reg_peri_backup_to_mem",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PERI_BACKUP_ENA": {
+                    "description": "reg_peri_backup_ena",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_APB_ADDR": {
+              "description": "APB_CTRL_PERI_BACKUP_APB_ADDR_REG",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_APB_START_ADDR": {
+                    "description": "reg_backup_apb_start_addr",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_MEM_ADDR": {
+              "description": "APB_CTRL_PERI_BACKUP_MEM_ADDR_REG",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_MEM_START_ADDR": {
+                    "description": "reg_backup_mem_start_addr",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_INT_RAW": {
+              "description": "APB_CTRL_PERI_BACKUP_INT_RAW_REG",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_BACKUP_DONE_INT_RAW": {
+                    "description": "reg_peri_backup_done_int_raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PERI_BACKUP_ERR_INT_RAW": {
+                    "description": "reg_peri_backup_err_int_raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_INT_ST": {
+              "description": "APB_CTRL_PERI_BACKUP_INT_ST_REG",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_BACKUP_DONE_INT_ST": {
+                    "description": "reg_peri_backup_done_int_st",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PERI_BACKUP_ERR_INT_ST": {
+                    "description": "reg_peri_backup_err_int_st",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_INT_ENA": {
+              "description": "APB_CTRL_PERI_BACKUP_INT_ENA_REG",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_BACKUP_DONE_INT_ENA": {
+                    "description": "reg_peri_backup_done_int_ena",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PERI_BACKUP_ERR_INT_ENA": {
+                    "description": "reg_peri_backup_err_int_ena",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERI_BACKUP_INT_CLR": {
+              "description": "APB_CTRL_PERI_BACKUP_INT_CLR_REG",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_BACKUP_DONE_INT_CLR": {
+                    "description": "reg_peri_backup_done_int_clr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PERI_BACKUP_ERR_INT_CLR": {
+                    "description": "reg_peri_backup_err_int_clr",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "APB_CTRL_DATE_REG",
+              "offset": 1020,
+              "size": 32,
+              "reset_value": 33583632,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "reg_dateVersion control",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "APB_SARADC": {
+        "description": "Successive Approximation Register Analog to Digital Converter",
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "digital saradc configure register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1073971776,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_START_FORCE": {
+                    "description": "select software enable saradc sample",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SARADC_START": {
+                    "description": "software enable saradc sample",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SARADC_SAR_CLK_GATED": {
+                    "description": "SAR clock gated",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SARADC_SAR_CLK_DIV": {
+                    "description": "SAR clock divider",
+                    "offset": 7,
+                    "size": 8
+                  },
+                  "SARADC_SAR_PATT_LEN": {
+                    "description": "0 ~ 15 means length 1 ~ 16",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "SARADC_SAR_PATT_P_CLEAR": {
+                    "description": "clear the pointer of pattern table for DIG ADC1 CTRL",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "SARADC_XPD_SAR_FORCE": {
+                    "description": "force option to xpd sar blocks",
+                    "offset": 27,
+                    "size": 2
+                  },
+                  "SARADC_WAIT_ARB_CYCLE": {
+                    "description": "wait arbit signal stable after sar_done",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CTRL2": {
+              "description": "digital saradc configure register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 41470,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_MEAS_NUM_LIMIT": {
+                    "description": "enable max meas num",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SARADC_MAX_MEAS_NUM": {
+                    "description": "max conversion number",
+                    "offset": 1,
+                    "size": 8
+                  },
+                  "SARADC_SAR1_INV": {
+                    "description": "1: data to DIG ADC1 CTRL is inverted, otherwise not",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SARADC_SAR2_INV": {
+                    "description": "1: data to DIG ADC2 CTRL is inverted, otherwise not",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SARADC_TIMER_TARGET": {
+                    "description": "to set saradc timer target",
+                    "offset": 12,
+                    "size": 12
+                  },
+                  "SARADC_TIMER_EN": {
+                    "description": "to enable saradc timer trigger",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FILTER_CTRL1": {
+              "description": "digital saradc configure register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_FILTER_FACTOR1": {
+                    "description": "Factor of saradc filter1",
+                    "offset": 26,
+                    "size": 3
+                  },
+                  "APB_SARADC_FILTER_FACTOR0": {
+                    "description": "Factor of saradc filter0",
+                    "offset": 29,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "FSM_WAIT": {
+              "description": "digital saradc configure register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 16713736,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_XPD_WAIT": {
+                    "description": "saradc_xpd_wait",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SARADC_RSTB_WAIT": {
+                    "description": "saradc_rstb_wait",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "SARADC_STANDBY_WAIT": {
+                    "description": "saradc_standby_wait",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SAR1_STATUS": {
+              "description": "digital saradc configure register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_SAR1_STATUS": {
+                    "description": "saradc1 status about data and channel",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SAR2_STATUS": {
+              "description": "digital saradc configure register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_SAR2_STATUS": {
+                    "description": "saradc2 status about data and channel",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SAR_PATT_TAB1": {
+              "description": "digital saradc configure register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_SAR_PATT_TAB1": {
+                    "description": "item 0 ~ 3 for pattern table 1 (each item one byte)",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "SAR_PATT_TAB2": {
+              "description": "digital saradc configure register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_SAR_PATT_TAB2": {
+                    "description": "Item 4 ~ 7 for pattern table 1 (each item one byte)",
+                    "offset": 0,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "ONETIME_SAMPLE": {
+              "description": "digital saradc configure register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 436207616,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SARADC_ONETIME_ATTEN": {
+                    "description": "configure onetime atten",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "SARADC_ONETIME_CHANNEL": {
+                    "description": "configure onetime channel",
+                    "offset": 25,
+                    "size": 4
+                  },
+                  "SARADC_ONETIME_START": {
+                    "description": "trigger adc onetime sample",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SARADC2_ONETIME_SAMPLE": {
+                    "description": "enable adc2 onetime sample",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SARADC1_ONETIME_SAMPLE": {
+                    "description": "enable adc1 onetime sample",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ARB_CTRL": {
+              "description": "digital saradc configure register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 2304,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ADC_ARB_APB_FORCE": {
+                    "description": "adc2 arbiter force to enableapb controller",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ADC_ARB_RTC_FORCE": {
+                    "description": "adc2 arbiter force to enable rtc controller",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ADC_ARB_WIFI_FORCE": {
+                    "description": "adc2 arbiter force to enable wifi controller",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ADC_ARB_GRANT_FORCE": {
+                    "description": "adc2 arbiter force grant",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ADC_ARB_APB_PRIORITY": {
+                    "description": "Set adc2 arbiterapb priority",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "ADC_ARB_RTC_PRIORITY": {
+                    "description": "Set adc2 arbiter rtc priority",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "ADC_ARB_WIFI_PRIORITY": {
+                    "description": "Set adc2 arbiter wifi priority",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "ADC_ARB_FIX_PRIORITY": {
+                    "description": "adc2 arbiter uses fixed priority",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FILTER_CTRL0": {
+              "description": "digital saradc configure register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 57933824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_FILTER_CHANNEL1": {
+                    "description": "configure filter1 to adc channel",
+                    "offset": 18,
+                    "size": 4
+                  },
+                  "APB_SARADC_FILTER_CHANNEL0": {
+                    "description": "configure filter0 to adc channel",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "APB_SARADC_FILTER_RESET": {
+                    "description": "enable apb_adc1_filter",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SAR1DATA_STATUS": {
+              "description": "digital saradc configure register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC1_DATA": {
+                    "description": "saradc1 data",
+                    "offset": 0,
+                    "size": 17,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SAR2DATA_STATUS": {
+              "description": "digital saradc configure register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC2_DATA": {
+                    "description": "saradc2 data",
+                    "offset": 0,
+                    "size": 17,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "THRES0_CTRL": {
+              "description": "digital saradc configure register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 262125,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES0_CHANNEL": {
+                    "description": "configure thres0 to adc channel",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "APB_SARADC_THRES0_HIGH": {
+                    "description": "saradc thres0 monitor thres",
+                    "offset": 5,
+                    "size": 13
+                  },
+                  "APB_SARADC_THRES0_LOW": {
+                    "description": "saradc thres0 monitor thres",
+                    "offset": 18,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "THRES1_CTRL": {
+              "description": "digital saradc configure register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 262125,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES1_CHANNEL": {
+                    "description": "configure thres1 to adc channel",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "APB_SARADC_THRES1_HIGH": {
+                    "description": "saradc thres1 monitor thres",
+                    "offset": 5,
+                    "size": 13
+                  },
+                  "APB_SARADC_THRES1_LOW": {
+                    "description": "saradc thres1 monitor thres",
+                    "offset": 18,
+                    "size": 13
+                  }
+                }
+              }
+            },
+            "THRES_CTRL": {
+              "description": "digital saradc configure register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES_ALL_EN": {
+                    "description": "enable thres to all channel",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "APB_SARADC_THRES1_EN": {
+                    "description": "enable thres1",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "APB_SARADC_THRES0_EN": {
+                    "description": "enable thres0",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "digital saradc int register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES1_LOW_INT_ENA": {
+                    "description": "saradc thres1 low  interrupt enable",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "APB_SARADC_THRES0_LOW_INT_ENA": {
+                    "description": "saradc thres0 low interrupt enable",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "APB_SARADC_THRES1_HIGH_INT_ENA": {
+                    "description": "saradc thres1 high interrupt enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "APB_SARADC_THRES0_HIGH_INT_ENA": {
+                    "description": "saradc thres0 high interrupt enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "APB_SARADC2_DONE_INT_ENA": {
+                    "description": "saradc2 done interrupt enable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "APB_SARADC1_DONE_INT_ENA": {
+                    "description": "saradc1 done interrupt enable",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "digital saradc int register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES1_LOW_INT_RAW": {
+                    "description": "saradc thres1 low  interrupt raw",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES0_LOW_INT_RAW": {
+                    "description": "saradc thres0 low interrupt raw",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES1_HIGH_INT_RAW": {
+                    "description": "saradc thres1 high interrupt raw",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES0_HIGH_INT_RAW": {
+                    "description": "saradc thres0 high interrupt raw",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC2_DONE_INT_RAW": {
+                    "description": "saradc2 done interrupt raw",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC1_DONE_INT_RAW": {
+                    "description": "saradc1 done interrupt raw",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "digital saradc int register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES1_LOW_INT_ST": {
+                    "description": "saradc thres1 low  interrupt state",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES0_LOW_INT_ST": {
+                    "description": "saradc thres0 low interrupt state",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES1_HIGH_INT_ST": {
+                    "description": "saradc thres1 high interrupt state",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC_THRES0_HIGH_INT_ST": {
+                    "description": "saradc thres0 high interrupt state",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC2_DONE_INT_ST": {
+                    "description": "saradc2 done interrupt state",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_SARADC1_DONE_INT_ST": {
+                    "description": "saradc1 done interrupt state",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "digital saradc int register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_THRES1_LOW_INT_CLR": {
+                    "description": "saradc thres1 low  interrupt clear",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_SARADC_THRES0_LOW_INT_CLR": {
+                    "description": "saradc thres0 low interrupt clear",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_SARADC_THRES1_HIGH_INT_CLR": {
+                    "description": "saradc thres1 high interrupt clear",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_SARADC_THRES0_HIGH_INT_CLR": {
+                    "description": "saradc thres0 high interrupt clear",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_SARADC2_DONE_INT_CLR": {
+                    "description": "saradc2 done interrupt clear",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_SARADC1_DONE_INT_CLR": {
+                    "description": "saradc1 done interrupt clear",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DMA_CONF": {
+              "description": "digital saradc configure register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 255,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_ADC_EOF_NUM": {
+                    "description": "the dma_in_suc_eof gen when sample cnt = spi_eof_num",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "APB_ADC_RESET_FSM": {
+                    "description": "reset_apb_adc_state",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "APB_ADC_TRANS": {
+                    "description": "enable apb_adc use spi_dma",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLKM_CONF": {
+              "description": "digital saradc configure register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKM_DIV_NUM": {
+                    "description": "Integral I2S clock divider value",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CLKM_DIV_B": {
+                    "description": "Fractional clock divider numerator value",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "CLKM_DIV_A": {
+                    "description": "Fractional clock divider denominator value",
+                    "offset": 14,
+                    "size": 6
+                  },
+                  "CLK_EN": {
+                    "description": "reg clk en",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CLK_SEL": {
+                    "description": "Set this bit to enable clk_apll",
+                    "offset": 21,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "APB_TSENS_CTRL": {
+              "description": "digital tsens configure register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 98304,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSENS_OUT": {
+                    "description": "temperature sensor data out",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "read-only"
+                  },
+                  "TSENS_IN_INV": {
+                    "description": "invert temperature sensor data",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TSENS_CLK_DIV": {
+                    "description": "temperature sensor clock divider",
+                    "offset": 14,
+                    "size": 8
+                  },
+                  "TSENS_PU": {
+                    "description": "temperature sensor power up",
+                    "offset": 22,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TSENS_CTRL2": {
+              "description": "digital tsens configure register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 16386,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TSENS_XPD_WAIT": {
+                    "description": "the time that power up tsens need wait",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "TSENS_XPD_FORCE": {
+                    "description": "force power up tsens",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "TSENS_CLK_INV": {
+                    "description": "inv tsens clk",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TSENS_CLK_SEL": {
+                    "description": "tsens clk select",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CALI": {
+              "description": "digital saradc configure register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_SARADC_CALI_CFG": {
+                    "description": "saradc cali factor",
+                    "offset": 0,
+                    "size": 17
+                  }
+                }
+              }
+            },
+            "CTRL_DATE": {
+              "description": "version",
+              "offset": 1020,
+              "size": 32,
+              "reset_value": 33583473,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "version",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "ASSIST_DEBUG": {
+        "description": "Debug Assist",
+        "children": {
+          "registers": {
+            "C0RE_0_MONTR_ENA": {
+              "description": "ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_RD_ENA": {
+                    "description": "reg_core_0_area_dram0_0_rd_ena",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_0_WR_ENA": {
+                    "description": "reg_core_0_area_dram0_0_wr_ena",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_RD_ENA": {
+                    "description": "reg_core_0_area_dram0_1_rd_ena",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_WR_ENA": {
+                    "description": "reg_core_0_area_dram0_1_wr_ena",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_RD_ENA": {
+                    "description": "reg_core_0_area_pif_0_rd_ena",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_WR_ENA": {
+                    "description": "reg_core_0_area_pif_0_wr_ena",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_RD_ENA": {
+                    "description": "reg_core_0_area_pif_1_rd_ena",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_WR_ENA": {
+                    "description": "reg_core_0_area_pif_1_wr_ena",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MIN_ENA": {
+                    "description": "reg_core_0_sp_spill_min_ena",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MAX_ENA": {
+                    "description": "reg_core_0_sp_spill_max_ena",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CORE_0_IRAM0_EXCEPTION_MONITOR_ENA": {
+                    "description": "reg_core_0_iram0_exception_monitor_ena",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CORE_0_DRAM0_EXCEPTION_MONITOR_ENA": {
+                    "description": "reg_core_0_dram0_exception_monitor_ena",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_INTR_RAW": {
+              "description": "ASSIST_DEBUG_CORE_0_INTR_RAW_REG",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_RD_RAW": {
+                    "description": "reg_core_0_area_dram0_0_rd_raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_DRAM0_0_WR_RAW": {
+                    "description": "reg_core_0_area_dram0_0_wr_raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_DRAM0_1_RD_RAW": {
+                    "description": "reg_core_0_area_dram0_1_rd_raw",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_DRAM0_1_WR_RAW": {
+                    "description": "reg_core_0_area_dram0_1_wr_raw",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_PIF_0_RD_RAW": {
+                    "description": "reg_core_0_area_pif_0_rd_raw",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_PIF_0_WR_RAW": {
+                    "description": "reg_core_0_area_pif_0_wr_raw",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_PIF_1_RD_RAW": {
+                    "description": "reg_core_0_area_pif_1_rd_raw",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_AREA_PIF_1_WR_RAW": {
+                    "description": "reg_core_0_area_pif_1_wr_raw",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_SP_SPILL_MIN_RAW": {
+                    "description": "reg_core_0_sp_spill_min_raw",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_SP_SPILL_MAX_RAW": {
+                    "description": "reg_core_0_sp_spill_max_raw",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_EXCEPTION_MONITOR_RAW": {
+                    "description": "reg_core_0_iram0_exception_monitor_raw",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_EXCEPTION_MONITOR_RAW": {
+                    "description": "reg_core_0_dram0_exception_monitor_raw",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_INTR_ENA": {
+              "description": "ASSIST_DEBUG_CORE_0_INTR_ENA_REG",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_RD_INTR_ENA": {
+                    "description": "reg_core_0_area_dram0_0_rd_intr_ena",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_0_WR_INTR_ENA": {
+                    "description": "reg_core_0_area_dram0_0_wr_intr_ena",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_RD_INTR_ENA": {
+                    "description": "reg_core_0_area_dram0_1_rd_intr_ena",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_WR_INTR_ENA": {
+                    "description": "reg_core_0_area_dram0_1_wr_intr_ena",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_RD_INTR_ENA": {
+                    "description": "reg_core_0_area_pif_0_rd_intr_ena",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_WR_INTR_ENA": {
+                    "description": "reg_core_0_area_pif_0_wr_intr_ena",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_RD_INTR_ENA": {
+                    "description": "reg_core_0_area_pif_1_rd_intr_ena",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_WR_INTR_ENA": {
+                    "description": "reg_core_0_area_pif_1_wr_intr_ena",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MIN_INTR_ENA": {
+                    "description": "reg_core_0_sp_spill_min_intr_ena",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MAX_INTR_ENA": {
+                    "description": "reg_core_0_sp_spill_max_intr_ena",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CORE_0_IRAM0_EXCEPTION_MONITOR_RLS": {
+                    "description": "reg_core_0_iram0_exception_monitor_ena",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CORE_0_DRAM0_EXCEPTION_MONITOR_RLS": {
+                    "description": "reg_core_0_dram0_exception_monitor_ena",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_INTR_CLR": {
+              "description": "ASSIST_DEBUG_CORE_0_INTR_CLR_REG",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_RD_CLR": {
+                    "description": "reg_core_0_area_dram0_0_rd_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_0_WR_CLR": {
+                    "description": "reg_core_0_area_dram0_0_wr_clr",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_RD_CLR": {
+                    "description": "reg_core_0_area_dram0_1_rd_clr",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_DRAM0_1_WR_CLR": {
+                    "description": "reg_core_0_area_dram0_1_wr_clr",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_RD_CLR": {
+                    "description": "reg_core_0_area_pif_0_rd_clr",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_0_WR_CLR": {
+                    "description": "reg_core_0_area_pif_0_wr_clr",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_RD_CLR": {
+                    "description": "reg_core_0_area_pif_1_rd_clr",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CORE_0_AREA_PIF_1_WR_CLR": {
+                    "description": "reg_core_0_area_pif_1_wr_clr",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MIN_CLR": {
+                    "description": "reg_core_0_sp_spill_min_clr",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CORE_0_SP_SPILL_MAX_CLR": {
+                    "description": "reg_core_0_sp_spill_max_clr",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CORE_0_IRAM0_EXCEPTION_MONITOR_CLR": {
+                    "description": "reg_core_0_iram0_exception_monitor_clr",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CORE_0_DRAM0_EXCEPTION_MONITOR_CLR": {
+                    "description": "reg_core_0_dram0_exception_monitor_clr",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_DRAM0_0_MIN": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_MIN": {
+                    "description": "reg_core_0_area_dram0_0_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_DRAM0_0_MAX": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_0_MAX": {
+                    "description": "reg_core_0_area_dram0_0_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_DRAM0_1_MIN": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_1_MIN": {
+                    "description": "reg_core_0_area_dram0_1_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_DRAM0_1_MAX": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_DRAM0_1_MAX": {
+                    "description": "reg_core_0_area_dram0_1_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_PIF_0_MIN": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_PIF_0_MIN": {
+                    "description": "reg_core_0_area_pif_0_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_PIF_0_MAX": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_PIF_0_MAX": {
+                    "description": "reg_core_0_area_pif_0_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_PIF_1_MIN": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_PIF_1_MIN": {
+                    "description": "reg_core_0_area_pif_1_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_PIF_1_MAX": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_PIF_1_MAX": {
+                    "description": "reg_core_0_area_pif_1_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_PC": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_PC_REG",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_PC": {
+                    "description": "reg_core_0_area_pc",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_AREA_SP": {
+              "description": "ASSIST_DEBUG_CORE_0_AREA_SP_REG",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_AREA_SP": {
+                    "description": "reg_core_0_area_sp",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_SP_MIN": {
+              "description": "ASSIST_DEBUG_CORE_0_SP_MIN_REG",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_SP_MIN": {
+                    "description": "reg_core_0_sp_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_SP_MAX": {
+              "description": "ASSIST_DEBUG_CORE_0_SP_MAX_REG",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_SP_MAX": {
+                    "description": "reg_core_0_sp_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CORE_0_SP_PC": {
+              "description": "ASSIST_DEBUG_CORE_0_SP_PC_REG",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_SP_PC": {
+                    "description": "reg_core_0_sp_pc",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_RCD_EN": {
+              "description": "ASSIST_DEBUG_CORE_0_RCD_EN_REG",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_RCD_RECORDEN": {
+                    "description": "reg_core_0_rcd_recorden",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_RCD_PDEBUGEN": {
+                    "description": "reg_core_0_rcd_pdebugen",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_RCD_PDEBUGPC": {
+              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_RCD_PDEBUGPC": {
+                    "description": "reg_core_0_rcd_pdebugpc",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_RCD_PDEBUGSP": {
+              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_RCD_PDEBUGSP": {
+                    "description": "reg_core_0_rcd_pdebugsp",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_EXCEPTION_MONITOR_0": {
+              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_RECORDING_ADDR_0": {
+                    "description": "reg_core_0_iram0_recording_addr_0",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_RECORDING_WR_0": {
+                    "description": "reg_core_0_iram0_recording_wr_0",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_RECORDING_LOADSTORE_0": {
+                    "description": "reg_core_0_iram0_recording_loadstore_0",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_EXCEPTION_MONITOR_1": {
+              "description": "ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_RECORDING_ADDR_1": {
+                    "description": "reg_core_0_iram0_recording_addr_1",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_RECORDING_WR_1": {
+                    "description": "reg_core_0_iram0_recording_wr_1",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_RECORDING_LOADSTORE_1": {
+                    "description": "reg_core_0_iram0_recording_loadstore_1",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_EXCEPTION_MONITOR_0": {
+              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_RECORDING_ADDR_0": {
+                    "description": "reg_core_0_dram0_recording_addr_0",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_RECORDING_WR_0": {
+                    "description": "reg_core_0_dram0_recording_wr_0",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_RECORDING_BYTEEN_0": {
+                    "description": "reg_core_0_dram0_recording_byteen_0",
+                    "offset": 25,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_EXCEPTION_MONITOR_1": {
+              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_RECORDING_PC_0": {
+                    "description": "reg_core_0_dram0_recording_pc_0",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_EXCEPTION_MONITOR_2": {
+              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_RECORDING_ADDR_1": {
+                    "description": "reg_core_0_dram0_recording_addr_1",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_RECORDING_WR_1": {
+                    "description": "reg_core_0_dram0_recording_wr_1",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_RECORDING_BYTEEN_1": {
+                    "description": "reg_core_0_dram0_recording_byteen_1",
+                    "offset": 25,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_EXCEPTION_MONITOR_3": {
+              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_RECORDING_PC_1": {
+                    "description": "reg_core_0_dram0_recording_pc_1",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0": {
+              "description": "ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0": {
+                    "description": "reg_core_x_iram0_dram0_limit_cycle_0",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1": {
+              "description": "ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1": {
+                    "description": "reg_core_x_iram0_dram0_limit_cycle_1",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "LOG_SETTING": {
+              "description": "ASSIST_DEBUG_LOG_SETTING",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_ENA": {
+                    "description": "reg_log_ena",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "LOG_MODE": {
+                    "description": "reg_log_mode",
+                    "offset": 3,
+                    "size": 4
+                  },
+                  "LOG_MEM_LOOP_ENABLE": {
+                    "description": "reg_log_mem_loop_enable",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LOG_DATA_0": {
+              "description": "ASSIST_DEBUG_LOG_DATA_0_REG",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_DATA_0": {
+                    "description": "reg_log_data_0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOG_DATA_MASK": {
+              "description": "ASSIST_DEBUG_LOG_DATA_MASK_REG",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_DATA_SIZE": {
+                    "description": "reg_log_data_size",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "LOG_MIN": {
+              "description": "ASSIST_DEBUG_LOG_MIN_REG",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MIN": {
+                    "description": "reg_log_min",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOG_MAX": {
+              "description": "ASSIST_DEBUG_LOG_MAX_REG",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MAX": {
+                    "description": "reg_log_max",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOG_MEM_START": {
+              "description": "ASSIST_DEBUG_LOG_MEM_START_REG",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MEM_START": {
+                    "description": "reg_log_mem_start",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOG_MEM_END": {
+              "description": "ASSIST_DEBUG_LOG_MEM_END_REG",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MEM_END": {
+                    "description": "reg_log_mem_end",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOG_MEM_WRITING_ADDR": {
+              "description": "ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MEM_WRITING_ADDR": {
+                    "description": "reg_log_mem_writing_addr",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LOG_MEM_FULL_FLAG": {
+              "description": "ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LOG_MEM_FULL_FLAG": {
+                    "description": "reg_log_mem_full_flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CLR_LOG_MEM_FULL_FLAG": {
+                    "description": "reg_clr_log_mem_full_flag",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "C0RE_0_LASTPC_BEFORE_EXCEPTION": {
+              "description": "ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_LASTPC_BEFORE_EXC": {
+                    "description": "reg_core_0_lastpc_before_exc",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "C0RE_0_DEBUG_MODE": {
+              "description": "ASSIST_DEBUG_C0RE_0_DEBUG_MODE",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DEBUG_MODE": {
+                    "description": "reg_core_0_debug_mode",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DEBUG_MODULE_ACTIVE": {
+                    "description": "reg_core_0_debug_module_active",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "ASSIST_DEBUG_DATE_REG",
+              "offset": 508,
+              "size": 32,
+              "reset_value": 33587216,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ASSIST_DEBUG_DATE": {
+                    "description": "reg_assist_debug_date",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DMA": {
+        "description": "DMA (Direct Memory Access) Controller",
+        "children": {
+          "registers": {
+            "INT_RAW_CH0": {
+              "description": "DMA_INT_RAW_CH0_REG.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH0_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH0_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH0_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH0_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH0_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST_CH0": {
+              "description": "DMA_INT_ST_CH0_REG.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH0_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA_CH0": {
+              "description": "DMA_INT_ENA_CH0_REG.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_SUC_EOF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IN_ERR_EOF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_DONE_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUT_EOF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IN_DSCR_ERR_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OUT_DSCR_ERR_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IN_DSCR_EMPTY_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OUT_TOTAL_EOF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "INFIFO_OVF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "INFIFO_UDF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OUTFIFO_OVF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OUTFIFO_UDF_CH0_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR_CH0": {
+              "description": "DMA_INT_CLR_CH0_REG.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_SUC_EOF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_ERR_EOF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DONE_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_EOF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_ERR_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DSCR_ERR_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_EMPTY_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_TOTAL_EOF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_OVF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_UDF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_OVF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_UDF_CH0_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW_CH1": {
+              "description": "DMA_INT_RAW_CH1_REG.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH1_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH1_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH1_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH1_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST_CH1": {
+              "description": "DMA_INT_ST_CH1_REG.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH1_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA_CH1": {
+              "description": "DMA_INT_ENA_CH1_REG.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_SUC_EOF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IN_ERR_EOF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_DONE_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUT_EOF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IN_DSCR_ERR_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OUT_DSCR_ERR_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IN_DSCR_EMPTY_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OUT_TOTAL_EOF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "INFIFO_OVF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "INFIFO_UDF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OUTFIFO_OVF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OUTFIFO_UDF_CH1_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR_CH1": {
+              "description": "DMA_INT_CLR_CH1_REG.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_SUC_EOF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_ERR_EOF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DONE_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_EOF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_ERR_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DSCR_ERR_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_EMPTY_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_TOTAL_EOF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_OVF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_UDF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_OVF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_UDF_CH1_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW_CH2": {
+              "description": "DMA_INT_RAW_CH2_REG.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH2_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH2_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH2_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH2_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH2_INT_RAW": {
+                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST_CH2": {
+              "description": "DMA_INT_ST_CH2_REG.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_SUC_EOF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_ERR_EOF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DONE_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_ERR_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_ERR_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_EMPTY_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_TOTAL_EOF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_OVF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_UDF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_OVF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_UDF_CH2_INT_ST": {
+                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA_CH2": {
+              "description": "DMA_INT_ENA_CH2_REG.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_SUC_EOF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "IN_ERR_EOF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_DONE_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUT_EOF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "IN_DSCR_ERR_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "OUT_DSCR_ERR_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "IN_DSCR_EMPTY_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "OUT_TOTAL_EOF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "INFIFO_OVF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "INFIFO_UDF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OUTFIFO_OVF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OUTFIFO_UDF_CH2_INT_ENA": {
+                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR_CH2": {
+              "description": "DMA_INT_CLR_CH2_REG.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_DONE_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_SUC_EOF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_ERR_EOF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DONE_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_EOF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_ERR_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_DSCR_ERR_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_DSCR_EMPTY_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_TOTAL_EOF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_OVF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "INFIFO_UDF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_OVF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUTFIFO_UDF_CH2_INT_CLR": {
+                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "AHB_TEST": {
+              "description": "DMA_AHB_TEST_REG.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AHB_TESTMODE": {
+                    "description": "reserved",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "AHB_TESTADDR": {
+                    "description": "reserved",
+                    "offset": 4,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "MISC_CONF": {
+              "description": "DMA_MISC_CONF_REG.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AHBM_RST_INTER": {
+                    "description": "Set this bit, then clear this bit to reset the internal ahb FSM.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ARB_PRI_DIS": {
+                    "description": "Set this bit to disable priority arbitration function.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "DMA_DATE_REG.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 33587792,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "register version.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IN_CONF0_CH0": {
+              "description": "DMA_IN_CONF0_CH0_REG.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_RST_CH0": {
+                    "description": "This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_LOOP_TEST_CH0": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INDSCR_BURST_EN_CH0": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IN_DATA_BURST_EN_CH0": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MEM_TRANS_EN_CH0": {
+                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_CONF1_CH0": {
+              "description": "DMA_IN_CONF1_CH0_REG.",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_CHECK_OWNER_CH0": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INFIFO_STATUS_CH0": {
+              "description": "DMA_INFIFO_STATUS_CH0_REG.",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 125829123,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_FULL_CH0": {
+                    "description": "L1 Rx FIFO full signal for Rx channel 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_EMPTY_CH0": {
+                    "description": "L1 Rx FIFO empty signal for Rx channel 0.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_CNT_CH0": {
+                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_1B_CH0": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_2B_CH0": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_3B_CH0": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_4B_CH0": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_BUF_HUNGRY_CH0": {
+                    "description": "reserved",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_POP_CH0": {
+              "description": "DMA_IN_POP_CH0_REG.",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_RDATA_CH0": {
+                    "description": "This register stores the data popping from DMA FIFO.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  },
+                  "INFIFO_POP_CH0": {
+                    "description": "Set this bit to pop data from DMA FIFO.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_LINK_CH0": {
+              "description": "DMA_IN_LINK_CH0_REG.",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 17825792,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_ADDR_CH0": {
+                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "INLINK_AUTO_RET_CH0": {
+                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "INLINK_STOP_CH0": {
+                    "description": "Set this bit to stop dealing with the inlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "INLINK_START_CH0": {
+                    "description": "Set this bit to start dealing with the inlink descriptors.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "INLINK_RESTART_CH0": {
+                    "description": "Set this bit to mount a new inlink descriptor.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "INLINK_PARK_CH0": {
+                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_STATE_CH0": {
+              "description": "DMA_IN_STATE_CH0_REG.",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_ADDR_CH0": {
+                    "description": "This register stores the current inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_STATE_CH0": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_STATE_CH0": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_SUC_EOF_DES_ADDR_CH0": {
+              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_SUC_EOF_DES_ADDR_CH0": {
+                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_ERR_EOF_DES_ADDR_CH0": {
+              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_ERR_EOF_DES_ADDR_CH0": {
+                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_CH0": {
+              "description": "DMA_IN_DSCR_CH0_REG.",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_CH0": {
+                    "description": "The address of the current inlink descriptor x.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF0_CH0": {
+              "description": "DMA_IN_DSCR_BF0_CH0_REG.",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF0_CH0": {
+                    "description": "The address of the last inlink descriptor x-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF1_CH0": {
+              "description": "DMA_IN_DSCR_BF1_CH0_REG.",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF1_CH0": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_PRI_CH0": {
+              "description": "DMA_IN_PRI_CH0_REG.",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_PRI_CH0": {
+                    "description": "The priority of Rx channel 0. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "IN_PERI_SEL_CH0": {
+              "description": "DMA_IN_PERI_SEL_CH0_REG.",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_IN_SEL_CH0": {
+                    "description": "This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "OUT_CONF0_CH0": {
+              "description": "DMA_OUT_CONF0_CH0_REG.",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_RST_CH0": {
+                    "description": "This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "OUT_LOOP_TEST_CH0": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OUT_AUTO_WRBACK_CH0": {
+                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_EOF_MODE_CH0": {
+                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUTDSCR_BURST_EN_CH0": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OUT_DATA_BURST_EN_CH0": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_CONF1_CH0": {
+              "description": "DMA_OUT_CONF1_CH0_REG.",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_CHECK_OWNER_CH0": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUTFIFO_STATUS_CH0": {
+              "description": "DMA_OUTFIFO_STATUS_CH0_REG.",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 125829122,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_FULL_CH0": {
+                    "description": "L1 Tx FIFO full signal for Tx channel 0.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_EMPTY_CH0": {
+                    "description": "L1 Tx FIFO empty signal for Tx channel 0.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_CNT_CH0": {
+                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_1B_CH0": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_2B_CH0": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_3B_CH0": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_4B_CH0": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PUSH_CH0": {
+              "description": "DMA_OUT_PUSH_CH0_REG.",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_WDATA_CH0": {
+                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "OUTFIFO_PUSH_CH0": {
+                    "description": "Set this bit to push data into DMA FIFO.",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_LINK_CH0": {
+              "description": "DMA_OUT_LINK_CH0_REG.",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_ADDR_CH0": {
+                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "OUTLINK_STOP_CH0": {
+                    "description": "Set this bit to stop dealing with the outlink descriptors.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "OUTLINK_START_CH0": {
+                    "description": "Set this bit to start dealing with the outlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "OUTLINK_RESTART_CH0": {
+                    "description": "Set this bit to restart a new outlink from the last address.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "OUTLINK_PARK_CH0": {
+                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_STATE_CH0": {
+              "description": "DMA_OUT_STATE_CH0_REG.",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_ADDR_CH0": {
+                    "description": "This register stores the current outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_STATE_CH0": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_STATE_CH0": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_DES_ADDR_CH0": {
+              "description": "DMA_OUT_EOF_DES_ADDR_CH0_REG.",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_DES_ADDR_CH0": {
+                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_BFR_DES_ADDR_CH0": {
+              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_BFR_DES_ADDR_CH0": {
+                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_CH0": {
+              "description": "DMA_OUT_DSCR_CH0_REG.",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_CH0": {
+                    "description": "The address of the current outlink descriptor y.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF0_CH0": {
+              "description": "DMA_OUT_DSCR_BF0_CH0_REG.",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF0_CH0": {
+                    "description": "The address of the last outlink descriptor y-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF1_CH0": {
+              "description": "DMA_OUT_DSCR_BF1_CH0_REG.",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF1_CH0": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PRI_CH0": {
+              "description": "DMA_OUT_PRI_CH0_REG.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_PRI_CH0": {
+                    "description": "The priority of Tx channel 0. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OUT_PERI_SEL_CH0": {
+              "description": "DMA_OUT_PERI_SEL_CH0_REG.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_OUT_SEL_CH0": {
+                    "description": "This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "IN_CONF0_CH1": {
+              "description": "DMA_IN_CONF0_CH1_REG.",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_RST_CH1": {
+                    "description": "This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_LOOP_TEST_CH1": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INDSCR_BURST_EN_CH1": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IN_DATA_BURST_EN_CH1": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MEM_TRANS_EN_CH1": {
+                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_CONF1_CH1": {
+              "description": "DMA_IN_CONF1_CH1_REG.",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_CHECK_OWNER_CH1": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INFIFO_STATUS_CH1": {
+              "description": "DMA_INFIFO_STATUS_CH1_REG.",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 125829123,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_FULL_CH1": {
+                    "description": "L1 Rx FIFO full signal for Rx channel 1.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_EMPTY_CH1": {
+                    "description": "L1 Rx FIFO empty signal for Rx channel 1.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_CNT_CH1": {
+                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_1B_CH1": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_2B_CH1": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_3B_CH1": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_4B_CH1": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_BUF_HUNGRY_CH1": {
+                    "description": "reserved",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_POP_CH1": {
+              "description": "DMA_IN_POP_CH1_REG.",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_RDATA_CH1": {
+                    "description": "This register stores the data popping from DMA FIFO.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  },
+                  "INFIFO_POP_CH1": {
+                    "description": "Set this bit to pop data from DMA FIFO.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_LINK_CH1": {
+              "description": "DMA_IN_LINK_CH1_REG.",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 17825792,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_ADDR_CH1": {
+                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "INLINK_AUTO_RET_CH1": {
+                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "INLINK_STOP_CH1": {
+                    "description": "Set this bit to stop dealing with the inlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "INLINK_START_CH1": {
+                    "description": "Set this bit to start dealing with the inlink descriptors.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "INLINK_RESTART_CH1": {
+                    "description": "Set this bit to mount a new inlink descriptor.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "INLINK_PARK_CH1": {
+                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_STATE_CH1": {
+              "description": "DMA_IN_STATE_CH1_REG.",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_ADDR_CH1": {
+                    "description": "This register stores the current inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_STATE_CH1": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_STATE_CH1": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_SUC_EOF_DES_ADDR_CH1": {
+              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_SUC_EOF_DES_ADDR_CH1": {
+                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_ERR_EOF_DES_ADDR_CH1": {
+              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_ERR_EOF_DES_ADDR_CH1": {
+                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_CH1": {
+              "description": "DMA_IN_DSCR_CH1_REG.",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_CH1": {
+                    "description": "The address of the current inlink descriptor x.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF0_CH1": {
+              "description": "DMA_IN_DSCR_BF0_CH1_REG.",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF0_CH1": {
+                    "description": "The address of the last inlink descriptor x-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF1_CH1": {
+              "description": "DMA_IN_DSCR_BF1_CH1_REG.",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF1_CH1": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_PRI_CH1": {
+              "description": "DMA_IN_PRI_CH1_REG.",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_PRI_CH1": {
+                    "description": "The priority of Rx channel 1. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "IN_PERI_SEL_CH1": {
+              "description": "DMA_IN_PERI_SEL_CH1_REG.",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_IN_SEL_CH1": {
+                    "description": "This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "OUT_CONF0_CH1": {
+              "description": "DMA_OUT_CONF0_CH1_REG.",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_RST_CH1": {
+                    "description": "This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "OUT_LOOP_TEST_CH1": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OUT_AUTO_WRBACK_CH1": {
+                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_EOF_MODE_CH1": {
+                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUTDSCR_BURST_EN_CH1": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OUT_DATA_BURST_EN_CH1": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_CONF1_CH1": {
+              "description": "DMA_OUT_CONF1_CH1_REG.",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_CHECK_OWNER_CH1": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUTFIFO_STATUS_CH1": {
+              "description": "DMA_OUTFIFO_STATUS_CH1_REG.",
+              "offset": 408,
+              "size": 32,
+              "reset_value": 125829122,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_FULL_CH1": {
+                    "description": "L1 Tx FIFO full signal for Tx channel 1.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_EMPTY_CH1": {
+                    "description": "L1 Tx FIFO empty signal for Tx channel 1.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_CNT_CH1": {
+                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_1B_CH1": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_2B_CH1": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_3B_CH1": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_4B_CH1": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PUSH_CH1": {
+              "description": "DMA_OUT_PUSH_CH1_REG.",
+              "offset": 412,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_WDATA_CH1": {
+                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "OUTFIFO_PUSH_CH1": {
+                    "description": "Set this bit to push data into DMA FIFO.",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_LINK_CH1": {
+              "description": "DMA_OUT_LINK_CH1_REG.",
+              "offset": 416,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_ADDR_CH1": {
+                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "OUTLINK_STOP_CH1": {
+                    "description": "Set this bit to stop dealing with the outlink descriptors.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "OUTLINK_START_CH1": {
+                    "description": "Set this bit to start dealing with the outlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "OUTLINK_RESTART_CH1": {
+                    "description": "Set this bit to restart a new outlink from the last address.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "OUTLINK_PARK_CH1": {
+                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_STATE_CH1": {
+              "description": "DMA_OUT_STATE_CH1_REG.",
+              "offset": 420,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_ADDR_CH1": {
+                    "description": "This register stores the current outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_STATE_CH1": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_STATE_CH1": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_DES_ADDR_CH1": {
+              "description": "DMA_OUT_EOF_DES_ADDR_CH1_REG.",
+              "offset": 424,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_DES_ADDR_CH1": {
+                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_BFR_DES_ADDR_CH1": {
+              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.",
+              "offset": 428,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_BFR_DES_ADDR_CH1": {
+                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_CH1": {
+              "description": "DMA_OUT_DSCR_CH1_REG.",
+              "offset": 432,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_CH1": {
+                    "description": "The address of the current outlink descriptor y.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF0_CH1": {
+              "description": "DMA_OUT_DSCR_BF0_CH1_REG.",
+              "offset": 436,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF0_CH1": {
+                    "description": "The address of the last outlink descriptor y-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF1_CH1": {
+              "description": "DMA_OUT_DSCR_BF1_CH1_REG.",
+              "offset": 440,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF1_CH1": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PRI_CH1": {
+              "description": "DMA_OUT_PRI_CH1_REG.",
+              "offset": 444,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_PRI_CH1": {
+                    "description": "The priority of Tx channel 1. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OUT_PERI_SEL_CH1": {
+              "description": "DMA_OUT_PERI_SEL_CH1_REG.",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_OUT_SEL_CH1": {
+                    "description": "This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "IN_CONF0_CH2": {
+              "description": "DMA_IN_CONF0_CH2_REG.",
+              "offset": 496,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_RST_CH2": {
+                    "description": "This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "IN_LOOP_TEST_CH2": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "INDSCR_BURST_EN_CH2": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IN_DATA_BURST_EN_CH2": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MEM_TRANS_EN_CH2": {
+                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_CONF1_CH2": {
+              "description": "DMA_IN_CONF1_CH2_REG.",
+              "offset": 500,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_CHECK_OWNER_CH2": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INFIFO_STATUS_CH2": {
+              "description": "DMA_INFIFO_STATUS_CH2_REG.",
+              "offset": 504,
+              "size": 32,
+              "reset_value": 125829123,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_FULL_CH2": {
+                    "description": "L1 Rx FIFO full signal for Rx channel 2.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_EMPTY_CH2": {
+                    "description": "L1 Rx FIFO empty signal for Rx channel 2.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "INFIFO_CNT_CH2": {
+                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_1B_CH2": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_2B_CH2": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_3B_CH2": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_REMAIN_UNDER_4B_CH2": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_BUF_HUNGRY_CH2": {
+                    "description": "reserved",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_POP_CH2": {
+              "description": "DMA_IN_POP_CH2_REG.",
+              "offset": 508,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INFIFO_RDATA_CH2": {
+                    "description": "This register stores the data popping from DMA FIFO.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  },
+                  "INFIFO_POP_CH2": {
+                    "description": "Set this bit to pop data from DMA FIFO.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IN_LINK_CH2": {
+              "description": "DMA_IN_LINK_CH2_REG.",
+              "offset": 512,
+              "size": 32,
+              "reset_value": 17825792,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_ADDR_CH2": {
+                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "INLINK_AUTO_RET_CH2": {
+                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "INLINK_STOP_CH2": {
+                    "description": "Set this bit to stop dealing with the inlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "INLINK_START_CH2": {
+                    "description": "Set this bit to start dealing with the inlink descriptors.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "INLINK_RESTART_CH2": {
+                    "description": "Set this bit to mount a new inlink descriptor.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "INLINK_PARK_CH2": {
+                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_STATE_CH2": {
+              "description": "DMA_IN_STATE_CH2_REG.",
+              "offset": 516,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_ADDR_CH2": {
+                    "description": "This register stores the current inlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "IN_DSCR_STATE_CH2": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_STATE_CH2": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_SUC_EOF_DES_ADDR_CH2": {
+              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.",
+              "offset": 520,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_SUC_EOF_DES_ADDR_CH2": {
+                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_ERR_EOF_DES_ADDR_CH2": {
+              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.",
+              "offset": 524,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_ERR_EOF_DES_ADDR_CH2": {
+                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_CH2": {
+              "description": "DMA_IN_DSCR_CH2_REG.",
+              "offset": 528,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_CH2": {
+                    "description": "The address of the current inlink descriptor x.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF0_CH2": {
+              "description": "DMA_IN_DSCR_BF0_CH2_REG.",
+              "offset": 532,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF0_CH2": {
+                    "description": "The address of the last inlink descriptor x-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_DSCR_BF1_CH2": {
+              "description": "DMA_IN_DSCR_BF1_CH2_REG.",
+              "offset": 536,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INLINK_DSCR_BF1_CH2": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_PRI_CH2": {
+              "description": "DMA_IN_PRI_CH2_REG.",
+              "offset": 540,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_PRI_CH2": {
+                    "description": "The priority of Rx channel 2. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "IN_PERI_SEL_CH2": {
+              "description": "DMA_IN_PERI_SEL_CH2_REG.",
+              "offset": 544,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_IN_SEL_CH2": {
+                    "description": "This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "OUT_CONF0_CH2": {
+              "description": "DMA_OUT_CONF0_CH2_REG.",
+              "offset": 592,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_RST_CH2": {
+                    "description": "This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "OUT_LOOP_TEST_CH2": {
+                    "description": "reserved",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "OUT_AUTO_WRBACK_CH2": {
+                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OUT_EOF_MODE_CH2": {
+                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "OUTDSCR_BURST_EN_CH2": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "OUT_DATA_BURST_EN_CH2": {
+                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_CONF1_CH2": {
+              "description": "DMA_OUT_CONF1_CH2_REG.",
+              "offset": 596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_CHECK_OWNER_CH2": {
+                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUTFIFO_STATUS_CH2": {
+              "description": "DMA_OUTFIFO_STATUS_CH2_REG.",
+              "offset": 600,
+              "size": 32,
+              "reset_value": 125829122,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_FULL_CH2": {
+                    "description": "L1 Tx FIFO full signal for Tx channel 2.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_EMPTY_CH2": {
+                    "description": "L1 Tx FIFO empty signal for Tx channel 2.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUTFIFO_CNT_CH2": {
+                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.",
+                    "offset": 2,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_1B_CH2": {
+                    "description": "reserved",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_2B_CH2": {
+                    "description": "reserved",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_3B_CH2": {
+                    "description": "reserved",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_REMAIN_UNDER_4B_CH2": {
+                    "description": "reserved",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PUSH_CH2": {
+              "description": "DMA_OUT_PUSH_CH2_REG.",
+              "offset": 604,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTFIFO_WDATA_CH2": {
+                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "OUTFIFO_PUSH_CH2": {
+                    "description": "Set this bit to push data into DMA FIFO.",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "OUT_LINK_CH2": {
+              "description": "DMA_OUT_LINK_CH2_REG.",
+              "offset": 608,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_ADDR_CH2": {
+                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 20
+                  },
+                  "OUTLINK_STOP_CH2": {
+                    "description": "Set this bit to stop dealing with the outlink descriptors.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "OUTLINK_START_CH2": {
+                    "description": "Set this bit to start dealing with the outlink descriptors.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "OUTLINK_RESTART_CH2": {
+                    "description": "Set this bit to restart a new outlink from the last address.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "OUTLINK_PARK_CH2": {
+                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_STATE_CH2": {
+              "description": "DMA_OUT_STATE_CH2_REG.",
+              "offset": 612,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_ADDR_CH2": {
+                    "description": "This register stores the current outlink descriptor's address.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "OUT_DSCR_STATE_CH2": {
+                    "description": "reserved",
+                    "offset": 18,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_STATE_CH2": {
+                    "description": "reserved",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_DES_ADDR_CH2": {
+              "description": "DMA_OUT_EOF_DES_ADDR_CH2_REG.",
+              "offset": 616,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_DES_ADDR_CH2": {
+                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EOF_BFR_DES_ADDR_CH2": {
+              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.",
+              "offset": 620,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EOF_BFR_DES_ADDR_CH2": {
+                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_CH2": {
+              "description": "DMA_OUT_DSCR_CH2_REG.",
+              "offset": 624,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_CH2": {
+                    "description": "The address of the current outlink descriptor y.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF0_CH2": {
+              "description": "DMA_OUT_DSCR_BF0_CH2_REG.",
+              "offset": 628,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF0_CH2": {
+                    "description": "The address of the last outlink descriptor y-1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_DSCR_BF1_CH2": {
+              "description": "DMA_OUT_DSCR_BF1_CH2_REG.",
+              "offset": 632,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUTLINK_DSCR_BF1_CH2": {
+                    "description": "The address of the second-to-last inlink descriptor x-2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_PRI_CH2": {
+              "description": "DMA_OUT_PRI_CH2_REG.",
+              "offset": 636,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_PRI_CH2": {
+                    "description": "The priority of Tx channel 2. The larger of the value, the higher of the priority.",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "OUT_PERI_SEL_CH2": {
+              "description": "DMA_OUT_PERI_SEL_CH2_REG.",
+              "offset": 640,
+              "size": 32,
+              "reset_value": 63,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PERI_OUT_SEL_CH2": {
+                    "description": "This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "DS": {
+        "description": "Digital Signature",
+        "children": {
+          "registers": {
+            "Y_MEM": {
+              "description": "memory that stores Y",
+              "offset": 0,
+              "size": 8,
+              "count": 512,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "M_MEM": {
+              "description": "memory that stores M",
+              "offset": 512,
+              "size": 8,
+              "count": 512,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "RB_MEM": {
+              "description": "memory that stores Rb",
+              "offset": 1024,
+              "size": 8,
+              "count": 512,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "BOX_MEM": {
+              "description": "memory that stores BOX",
+              "offset": 1536,
+              "size": 8,
+              "count": 48,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "X_MEM": {
+              "description": "memory that stores X",
+              "offset": 2048,
+              "size": 8,
+              "count": 512,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "Z_MEM": {
+              "description": "memory that stores Z",
+              "offset": 2560,
+              "size": 8,
+              "count": 512,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SET_START": {
+              "description": "DS start control register",
+              "offset": 3584,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_START": {
+                    "description": "set this bit to start DS operation.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_CONTINUE": {
+              "description": "DS continue control register",
+              "offset": 3588,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_CONTINUE": {
+                    "description": "set this bit to continue DS operation.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_FINISH": {
+              "description": "DS finish control register",
+              "offset": 3592,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_FINISH": {
+                    "description": "Set this bit to finish DS process.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "QUERY_BUSY": {
+              "description": "DS query busy register",
+              "offset": 3596,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "QUERY_BUSY": {
+                    "description": "digital signature state. 1'b0: idle, 1'b1: busy",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "QUERY_KEY_WRONG": {
+              "description": "DS query key-wrong counter register",
+              "offset": 3600,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "QUERY_KEY_WRONG": {
+                    "description": "digital signature key wrong counter",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "QUERY_CHECK": {
+              "description": "DS query check result register",
+              "offset": 3604,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MD_ERROR": {
+                    "description": "MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PADDING_BAD": {
+                    "description": "padding checkout result. 1'b0: a good padding, 1'b1: a bad padding",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "DS version control register",
+              "offset": 3616,
+              "size": 32,
+              "reset_value": 538969624,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "ds version information",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EFUSE": {
+        "description": "eFuse Controller",
+        "children": {
+          "registers": {
+            "PGM_DATA0": {
+              "description": "Register 0 that stores data to be programmed.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_0": {
+                    "description": "The content of the 0th 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA1": {
+              "description": "Register 1 that stores data to be programmed.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_1": {
+                    "description": "The content of the 1st 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA2": {
+              "description": "Register 2 that stores data to be programmed.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_2": {
+                    "description": "The content of the 2nd 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA3": {
+              "description": "Register 3 that stores data to be programmed.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_3": {
+                    "description": "The content of the 3rd 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA4": {
+              "description": "Register 4 that stores data to be programmed.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_4": {
+                    "description": "The content of the 4th 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA5": {
+              "description": "Register 5 that stores data to be programmed.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_5": {
+                    "description": "The content of the 5th 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA6": {
+              "description": "Register 6 that stores data to be programmed.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_6": {
+                    "description": "The content of the 6th 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_DATA7": {
+              "description": "Register 7 that stores data to be programmed.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_DATA_7": {
+                    "description": "The content of the 7th 32-bit data to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_CHECK_VALUE0": {
+              "description": "Register 0 that stores the RS code to be programmed.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_RS_DATA_0": {
+                    "description": "The content of the 0th 32-bit RS code to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_CHECK_VALUE1": {
+              "description": "Register 1 that stores the RS code to be programmed.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_RS_DATA_1": {
+                    "description": "The content of the 1st 32-bit RS code to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PGM_CHECK_VALUE2": {
+              "description": "Register 2 that stores the RS code to be programmed.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PGM_RS_DATA_2": {
+                    "description": "The content of the 2nd 32-bit RS code to be programmed.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RD_WR_DIS": {
+              "description": "BLOCK0 data register 0.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WR_DIS": {
+                    "description": "Disable programming of individual eFuses.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_DATA0": {
+              "description": "BLOCK0 data register 1.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RD_DIS": {
+                    "description": "Set this bit to disable reading from BlOCK4-10.",
+                    "offset": 0,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "DIS_RTC_RAM_BOOT": {
+                    "description": "Set this bit to disable boot from RTC RAM.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_ICACHE": {
+                    "description": "Set this bit to disable Icache.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_JTAG": {
+                    "description": "Set this bit to disable function of usb switch to jtag in module of usb device.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_DOWNLOAD_ICACHE": {
+                    "description": "Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_DEVICE": {
+                    "description": "Set this bit to disable usb device.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_FORCE_DOWNLOAD": {
+                    "description": "Set this bit to disable the function that forces chip into download mode.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED6": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_CAN": {
+                    "description": "Set this bit to disable CAN function.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "JTAG_SEL_ENABLE": {
+                    "description": "Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOFT_DIS_JTAG": {
+                    "description": "Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.",
+                    "offset": 16,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DIS_PAD_JTAG": {
+                    "description": "Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_DOWNLOAD_MANUAL_ENCRYPT": {
+                    "description": "Set this bit to disable flash encryption when in download boot modes.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USB_DREFH": {
+                    "description": "Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.",
+                    "offset": 21,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "USB_DREFL": {
+                    "description": "Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.",
+                    "offset": 23,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "USB_EXCHG_PINS": {
+                    "description": "Set this bit to exchange USB D+ and D- pins.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "VDD_SPI_AS_GPIO": {
+                    "description": "Set this bit to vdd spi pin function as gpio.",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BTLC_GPIO_ENABLE": {
+                    "description": "Enable btlc gpio.",
+                    "offset": 27,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "POWERGLITCH_EN": {
+                    "description": "Set this bit to enable power glitch function.",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "POWER_GLITCH_DSENSE": {
+                    "description": "Sample delay configuration of power glitch.",
+                    "offset": 30,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_DATA1": {
+              "description": "BLOCK0 data register 2.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RPT4_RESERVED2": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "WDT_DELAY_SEL": {
+                    "description": "Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.",
+                    "offset": 16,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "SPI_BOOT_CRYPT_CNT": {
+                    "description": "Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.",
+                    "offset": 18,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE0": {
+                    "description": "Set this bit to enable revoking first secure boot key.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE1": {
+                    "description": "Set this bit to enable revoking second secure boot key.",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE2": {
+                    "description": "Set this bit to enable revoking third secure boot key.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_0": {
+                    "description": "Purpose of Key0.",
+                    "offset": 24,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_1": {
+                    "description": "Purpose of Key1.",
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_DATA2": {
+              "description": "BLOCK0 data register 3.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_PURPOSE_2": {
+                    "description": "Purpose of Key2.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_3": {
+                    "description": "Purpose of Key3.",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_4": {
+                    "description": "Purpose of Key4.",
+                    "offset": 8,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_5": {
+                    "description": "Purpose of Key5.",
+                    "offset": 12,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED3": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 16,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_EN": {
+                    "description": "Set this bit to enable secure boot.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_AGGRESSIVE_REVOKE": {
+                    "description": "Set this bit to enable revoking aggressive secure boot.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED0": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 22,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "FLASH_TPUW": {
+                    "description": "Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.",
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_DATA3": {
+              "description": "BLOCK0 data register 4.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIS_DOWNLOAD_MODE": {
+                    "description": "Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_LEGACY_SPI_BOOT": {
+                    "description": "Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "UART_PRINT_CHANNEL": {
+                    "description": "Selectes the default UART print channel. 0: UART0. 1: UART1.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_ECC_MODE": {
+                    "description": "Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_DOWNLOAD_MODE": {
+                    "description": "Set this bit to disable UART download mode through USB.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ENABLE_SECURITY_DOWNLOAD": {
+                    "description": "Set this bit to enable secure UART download mode.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "UART_PRINT_CONTROL": {
+                    "description": "Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.",
+                    "offset": 6,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PIN_POWER_SELECTION": {
+                    "description": "GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_TYPE": {
+                    "description": "Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_PAGE_SIZE": {
+                    "description": "Set Flash page size.",
+                    "offset": 10,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "FLASH_ECC_EN": {
+                    "description": "Set 1 to enable ECC for flash boot.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FORCE_SEND_RESUME": {
+                    "description": "Set this bit to force ROM code to send a resume command during SPI boot.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_VERSION": {
+                    "description": "Secure version (used by ESP-IDF anti-rollback feature).",
+                    "offset": 14,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED1": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 30,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_DATA4": {
+              "description": "BLOCK0 data register 5.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RPT4_RESERVED4": {
+                    "description": "Reserved (used for four backups method).",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_0": {
+              "description": "BLOCK1 data register 0.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC_0": {
+                    "description": "Stores the low 32 bits of MAC address.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_1": {
+              "description": "BLOCK1 data register 1.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC_1": {
+                    "description": "Stores the high 16 bits of MAC address.",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "SPI_PAD_CONF_0": {
+                    "description": "Stores the zeroth part of SPI_PAD_CONF.",
+                    "offset": 16,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_2": {
+              "description": "BLOCK1 data register 2.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_PAD_CONF_1": {
+                    "description": "Stores the first part of SPI_PAD_CONF.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_3": {
+              "description": "BLOCK1 data register 3.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_PAD_CONF_2": {
+                    "description": "Stores the second part of SPI_PAD_CONF.",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  },
+                  "SYS_DATA_PART0_0": {
+                    "description": "Stores the fist 14 bits of the zeroth part of system data.",
+                    "offset": 18,
+                    "size": 14,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_4": {
+              "description": "BLOCK1 data register 4.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART0_1": {
+                    "description": "Stores the fist 32 bits of the zeroth part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_MAC_SPI_SYS_5": {
+              "description": "BLOCK1 data register 5.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART0_2": {
+                    "description": "Stores the second 32 bits of the zeroth part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA0": {
+              "description": "Register 0 of BLOCK2 (system).",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_0": {
+                    "description": "Stores the zeroth 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA1": {
+              "description": "Register 1 of BLOCK2 (system).",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_1": {
+                    "description": "Stores the first 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA2": {
+              "description": "Register 2 of BLOCK2 (system).",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_2": {
+                    "description": "Stores the second 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA3": {
+              "description": "Register 3 of BLOCK2 (system).",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_3": {
+                    "description": "Stores the third 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA4": {
+              "description": "Register 4 of BLOCK2 (system).",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_4": {
+                    "description": "Stores the fourth 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA5": {
+              "description": "Register 5 of BLOCK2 (system).",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_5": {
+                    "description": "Stores the fifth 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA6": {
+              "description": "Register 6 of BLOCK2 (system).",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_6": {
+                    "description": "Stores the sixth 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART1_DATA7": {
+              "description": "Register 7 of BLOCK2 (system).",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART1_7": {
+                    "description": "Stores the seventh 32 bits of the first part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA0": {
+              "description": "Register 0 of BLOCK3 (user).",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA0": {
+                    "description": "Stores the zeroth 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA1": {
+              "description": "Register 1 of BLOCK3 (user).",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA1": {
+                    "description": "Stores the first 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA2": {
+              "description": "Register 2 of BLOCK3 (user).",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA2": {
+                    "description": "Stores the second 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA3": {
+              "description": "Register 3 of BLOCK3 (user).",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA3": {
+                    "description": "Stores the third 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA4": {
+              "description": "Register 4 of BLOCK3 (user).",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA4": {
+                    "description": "Stores the fourth 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA5": {
+              "description": "Register 5 of BLOCK3 (user).",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA5": {
+                    "description": "Stores the fifth 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA6": {
+              "description": "Register 6 of BLOCK3 (user).",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA6": {
+                    "description": "Stores the sixth 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_USR_DATA7": {
+              "description": "Register 7 of BLOCK3 (user).",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DATA7": {
+                    "description": "Stores the seventh 32 bits of BLOCK3 (user).",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA0": {
+              "description": "Register 0 of BLOCK4 (KEY0).",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA1": {
+              "description": "Register 1 of BLOCK4 (KEY0).",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA1": {
+                    "description": "Stores the first 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA2": {
+              "description": "Register 2 of BLOCK4 (KEY0).",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA2": {
+                    "description": "Stores the second 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA3": {
+              "description": "Register 3 of BLOCK4 (KEY0).",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA3": {
+                    "description": "Stores the third 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA4": {
+              "description": "Register 4 of BLOCK4 (KEY0).",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA5": {
+              "description": "Register 5 of BLOCK4 (KEY0).",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA6": {
+              "description": "Register 6 of BLOCK4 (KEY0).",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY0_DATA7": {
+              "description": "Register 7 of BLOCK4 (KEY0).",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY0_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY0.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA0": {
+              "description": "Register 0 of BLOCK5 (KEY1).",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA1": {
+              "description": "Register 1 of BLOCK5 (KEY1).",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA1": {
+                    "description": "Stores the first 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA2": {
+              "description": "Register 2 of BLOCK5 (KEY1).",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA2": {
+                    "description": "Stores the second 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA3": {
+              "description": "Register 3 of BLOCK5 (KEY1).",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA3": {
+                    "description": "Stores the third 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA4": {
+              "description": "Register 4 of BLOCK5 (KEY1).",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA5": {
+              "description": "Register 5 of BLOCK5 (KEY1).",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA6": {
+              "description": "Register 6 of BLOCK5 (KEY1).",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY1_DATA7": {
+              "description": "Register 7 of BLOCK5 (KEY1).",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY1_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY1.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA0": {
+              "description": "Register 0 of BLOCK6 (KEY2).",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA1": {
+              "description": "Register 1 of BLOCK6 (KEY2).",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA1": {
+                    "description": "Stores the first 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA2": {
+              "description": "Register 2 of BLOCK6 (KEY2).",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA2": {
+                    "description": "Stores the second 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA3": {
+              "description": "Register 3 of BLOCK6 (KEY2).",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA3": {
+                    "description": "Stores the third 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA4": {
+              "description": "Register 4 of BLOCK6 (KEY2).",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA5": {
+              "description": "Register 5 of BLOCK6 (KEY2).",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA6": {
+              "description": "Register 6 of BLOCK6 (KEY2).",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY2_DATA7": {
+              "description": "Register 7 of BLOCK6 (KEY2).",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY2_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY2.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA0": {
+              "description": "Register 0 of BLOCK7 (KEY3).",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA1": {
+              "description": "Register 1 of BLOCK7 (KEY3).",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA1": {
+                    "description": "Stores the first 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA2": {
+              "description": "Register 2 of BLOCK7 (KEY3).",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA2": {
+                    "description": "Stores the second 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA3": {
+              "description": "Register 3 of BLOCK7 (KEY3).",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA3": {
+                    "description": "Stores the third 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA4": {
+              "description": "Register 4 of BLOCK7 (KEY3).",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA5": {
+              "description": "Register 5 of BLOCK7 (KEY3).",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA6": {
+              "description": "Register 6 of BLOCK7 (KEY3).",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY3_DATA7": {
+              "description": "Register 7 of BLOCK7 (KEY3).",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY3_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY3.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA0": {
+              "description": "Register 0 of BLOCK8 (KEY4).",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA1": {
+              "description": "Register 1 of BLOCK8 (KEY4).",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA1": {
+                    "description": "Stores the first 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA2": {
+              "description": "Register 2 of BLOCK8 (KEY4).",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA2": {
+                    "description": "Stores the second 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA3": {
+              "description": "Register 3 of BLOCK8 (KEY4).",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA3": {
+                    "description": "Stores the third 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA4": {
+              "description": "Register 4 of BLOCK8 (KEY4).",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA5": {
+              "description": "Register 5 of BLOCK8 (KEY4).",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA6": {
+              "description": "Register 6 of BLOCK8 (KEY4).",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY4_DATA7": {
+              "description": "Register 7 of BLOCK8 (KEY4).",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY4_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY4.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA0": {
+              "description": "Register 0 of BLOCK9 (KEY5).",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA0": {
+                    "description": "Stores the zeroth 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA1": {
+              "description": "Register 1 of BLOCK9 (KEY5).",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA1": {
+                    "description": "Stores the first 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA2": {
+              "description": "Register 2 of BLOCK9 (KEY5).",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA2": {
+                    "description": "Stores the second 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA3": {
+              "description": "Register 3 of BLOCK9 (KEY5).",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA3": {
+                    "description": "Stores the third 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA4": {
+              "description": "Register 4 of BLOCK9 (KEY5).",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA4": {
+                    "description": "Stores the fourth 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA5": {
+              "description": "Register 5 of BLOCK9 (KEY5).",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA5": {
+                    "description": "Stores the fifth 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA6": {
+              "description": "Register 6 of BLOCK9 (KEY5).",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA6": {
+                    "description": "Stores the sixth 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_KEY5_DATA7": {
+              "description": "Register 7 of BLOCK9 (KEY5).",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_DATA7": {
+                    "description": "Stores the seventh 32 bits of KEY5.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA0": {
+              "description": "Register 0 of BLOCK10 (system).",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_0": {
+                    "description": "Stores the 0th 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA1": {
+              "description": "Register 1 of BLOCK9 (KEY5).",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_1": {
+                    "description": "Stores the 1st 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA2": {
+              "description": "Register 2 of BLOCK10 (system).",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_2": {
+                    "description": "Stores the 2nd 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA3": {
+              "description": "Register 3 of BLOCK10 (system).",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_3": {
+                    "description": "Stores the 3rd 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA4": {
+              "description": "Register 4 of BLOCK10 (system).",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_4": {
+                    "description": "Stores the 4th 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA5": {
+              "description": "Register 5 of BLOCK10 (system).",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_5": {
+                    "description": "Stores the 5th 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA6": {
+              "description": "Register 6 of BLOCK10 (system).",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_6": {
+                    "description": "Stores the 6th 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_SYS_PART2_DATA7": {
+              "description": "Register 7 of BLOCK10 (system).",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYS_DATA_PART2_7": {
+                    "description": "Stores the 7th 32 bits of the 2nd part of system data.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_ERR0": {
+              "description": "Programming error record register 0 of BLOCK0.",
+              "offset": 380,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RD_DIS_ERR": {
+                    "description": "If any bit in RD_DIS is 1, then it indicates a programming error.",
+                    "offset": 0,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "DIS_RTC_RAM_BOOT_ERR": {
+                    "description": "If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_ICACHE_ERR": {
+                    "description": "If DIS_ICACHE is 1, then it indicates a programming error.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_JTAG_ERR": {
+                    "description": "If DIS_USB_JTAG is 1, then it indicates a programming error.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_DOWNLOAD_ICACHE_ERR": {
+                    "description": "If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_DEVICE_ERR": {
+                    "description": "If DIS_USB_DEVICE is 1, then it indicates a programming error.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_FORCE_DOWNLOAD_ERR": {
+                    "description": "If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED6_ERR": {
+                    "description": "Reserved.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_CAN_ERR": {
+                    "description": "If DIS_CAN is 1, then it indicates a programming error.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "JTAG_SEL_ENABLE_ERR": {
+                    "description": "If JTAG_SEL_ENABLE is 1, then it indicates a programming error.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOFT_DIS_JTAG_ERR": {
+                    "description": "If SOFT_DIS_JTAG is 1, then it indicates a programming error.",
+                    "offset": 16,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "DIS_PAD_JTAG_ERR": {
+                    "description": "If DIS_PAD_JTAG is 1, then it indicates a programming error.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR": {
+                    "description": "If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USB_DREFH_ERR": {
+                    "description": "If any bit in USB_DREFH is 1, then it indicates a programming error.",
+                    "offset": 21,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "USB_DREFL_ERR": {
+                    "description": "If any bit in USB_DREFL is 1, then it indicates a programming error.",
+                    "offset": 23,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "USB_EXCHG_PINS_ERR": {
+                    "description": "If USB_EXCHG_PINS is 1, then it indicates a programming error.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "VDD_SPI_AS_GPIO_ERR": {
+                    "description": "If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BTLC_GPIO_ENABLE_ERR": {
+                    "description": "If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.",
+                    "offset": 27,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "POWERGLITCH_EN_ERR": {
+                    "description": "If POWERGLITCH_EN is 1, then it indicates a programming error.",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "POWER_GLITCH_DSENSE_ERR": {
+                    "description": "If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.",
+                    "offset": 30,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_ERR1": {
+              "description": "Programming error record register 1 of BLOCK0.",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RPT4_RESERVED2_ERR": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "WDT_DELAY_SEL_ERR": {
+                    "description": "If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.",
+                    "offset": 16,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "SPI_BOOT_CRYPT_CNT_ERR": {
+                    "description": "If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.",
+                    "offset": 18,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE0_ERR": {
+                    "description": "If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE1_ERR": {
+                    "description": "If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_KEY_REVOKE2_ERR": {
+                    "description": "If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_0_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.",
+                    "offset": 24,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_1_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.",
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_ERR2": {
+              "description": "Programming error record register 2 of BLOCK0.",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_PURPOSE_2_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_3_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_4_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.",
+                    "offset": 8,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "KEY_PURPOSE_5_ERR": {
+                    "description": "If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.",
+                    "offset": 12,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED3_ERR": {
+                    "description": "Reserved.",
+                    "offset": 16,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_EN_ERR": {
+                    "description": "If SECURE_BOOT_EN is 1, then it indicates a programming error.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_BOOT_AGGRESSIVE_REVOKE_ERR": {
+                    "description": "If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED0_ERR": {
+                    "description": "Reserved.",
+                    "offset": 22,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "FLASH_TPUW_ERR": {
+                    "description": "If any bit in FLASH_TPUM is 1, then it indicates a programming error.",
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_ERR3": {
+              "description": "Programming error record register 3 of BLOCK0.",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIS_DOWNLOAD_MODE_ERR": {
+                    "description": "If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_LEGACY_SPI_BOOT_ERR": {
+                    "description": "If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "UART_PRINT_CHANNEL_ERR": {
+                    "description": "If UART_PRINT_CHANNEL is 1, then it indicates a programming error.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_ECC_MODE_ERR": {
+                    "description": "If FLASH_ECC_MODE is 1, then it indicates a programming error.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIS_USB_DOWNLOAD_MODE_ERR": {
+                    "description": "If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ENABLE_SECURITY_DOWNLOAD_ERR": {
+                    "description": "If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "UART_PRINT_CONTROL_ERR": {
+                    "description": "If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.",
+                    "offset": 6,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "PIN_POWER_SELECTION_ERR": {
+                    "description": "If PIN_POWER_SELECTION is 1, then it indicates a programming error.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_TYPE_ERR": {
+                    "description": "If FLASH_TYPE is 1, then it indicates a programming error.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FLASH_PAGE_SIZE_ERR": {
+                    "description": "If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.",
+                    "offset": 10,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "FLASH_ECC_EN_ERR": {
+                    "description": "If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FORCE_SEND_RESUME_ERR": {
+                    "description": "If FORCE_SEND_RESUME is 1, then it indicates a programming error.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SECURE_VERSION_ERR": {
+                    "description": "If any bit in SECURE_VERSION is 1, then it indicates a programming error.",
+                    "offset": 14,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "RPT4_RESERVED1_ERR": {
+                    "description": "Reserved.",
+                    "offset": 30,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_REPEAT_ERR4": {
+              "description": "Programming error record register 4 of BLOCK0.",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RPT4_RESERVED4_ERR": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_RS_ERR0": {
+              "description": "Programming error record register 0 of BLOCK1-10.",
+              "offset": 448,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC_SPI_8M_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "MAC_SPI_8M_FAIL": {
+                    "description": "0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SYS_PART1_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 4,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "SYS_PART1_FAIL": {
+                    "description": "0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USR_DATA_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 8,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "USR_DATA_FAIL": {
+                    "description": "0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY0_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 12,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY0_FAIL": {
+                    "description": "0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY1_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 16,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY1_FAIL": {
+                    "description": "0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY2_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY2_FAIL": {
+                    "description": "0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY3_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 24,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY3_FAIL": {
+                    "description": "0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "KEY4_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 28,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY4_FAIL": {
+                    "description": "0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RD_RS_ERR1": {
+              "description": "Programming error record register 1 of BLOCK1-10.",
+              "offset": 452,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY5_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "KEY5_FAIL": {
+                    "description": "0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SYS_PART2_ERR_NUM": {
+                    "description": "The value of this signal means the number of error bytes.",
+                    "offset": 4,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "SYS_PART2_FAIL": {
+                    "description": "0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLK": {
+              "description": "eFuse clcok configuration register.",
+              "offset": 456,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EFUSE_MEM_FORCE_PD": {
+                    "description": "Set this bit to force eFuse SRAM into power-saving mode.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MEM_CLK_FORCE_ON": {
+                    "description": "Set this bit and force to activate clock signal of eFuse SRAM.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EFUSE_MEM_FORCE_PU": {
+                    "description": "Set this bit to force eFuse SRAM into working mode.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "EN": {
+                    "description": "Set this bit and force to enable clock signal of eFuse memory.",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CONF": {
+              "description": "eFuse operation mode configuraiton register;",
+              "offset": 460,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OP_CODE": {
+                    "description": "0x5A5A: Operate programming command 0x5AA5: Operate read command.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "eFuse status register.",
+              "offset": 464,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATE": {
+                    "description": "Indicates the state of the eFuse state machine.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "OTP_LOAD_SW": {
+                    "description": "The value of OTP_LOAD_SW.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OTP_VDDQ_C_SYNC2": {
+                    "description": "The value of OTP_VDDQ_C_SYNC2.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OTP_STROBE_SW": {
+                    "description": "The value of OTP_STROBE_SW.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OTP_CSB_SW": {
+                    "description": "The value of OTP_CSB_SW.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OTP_PGENB_SW": {
+                    "description": "The value of OTP_PGENB_SW.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OTP_VDDQ_IS_SW": {
+                    "description": "The value of OTP_VDDQ_IS_SW.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "REPEAT_ERR_CNT": {
+                    "description": "Indicates the number of error bits during programming BLOCK0.",
+                    "offset": 10,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CMD": {
+              "description": "eFuse command register.",
+              "offset": 468,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_CMD": {
+                    "description": "Set this bit to send read command.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PGM_CMD": {
+                    "description": "Set this bit to send programming command.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BLK_NUM": {
+                    "description": "The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.",
+                    "offset": 2,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "eFuse raw interrupt register.",
+              "offset": 472,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_DONE_INT_RAW": {
+                    "description": "The raw bit signal for read_done interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PGM_DONE_INT_RAW": {
+                    "description": "The raw bit signal for pgm_done interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "eFuse interrupt status register.",
+              "offset": 476,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_DONE_INT_ST": {
+                    "description": "The status signal for read_done interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PGM_DONE_INT_ST": {
+                    "description": "The status signal for pgm_done interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "eFuse interrupt enable register.",
+              "offset": 480,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_DONE_INT_ENA": {
+                    "description": "The enable signal for read_done interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PGM_DONE_INT_ENA": {
+                    "description": "The enable signal for pgm_done interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "eFuse interrupt clear register.",
+              "offset": 484,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_DONE_INT_CLR": {
+                    "description": "The clear signal for read_done interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PGM_DONE_INT_CLR": {
+                    "description": "The clear signal for pgm_done interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DAC_CONF": {
+              "description": "Controls the eFuse programming voltage.",
+              "offset": 488,
+              "size": 32,
+              "reset_value": 130588,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DAC_CLK_DIV": {
+                    "description": "Controls the division factor of the rising clock of the programming voltage.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "DAC_CLK_PAD_SEL": {
+                    "description": "Don't care.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DAC_NUM": {
+                    "description": "Controls the rising period of the programming voltage.",
+                    "offset": 9,
+                    "size": 8
+                  },
+                  "OE_CLR": {
+                    "description": "Reduces the power supply of the programming voltage.",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RD_TIM_CONF": {
+              "description": "Configures read timing parameters.",
+              "offset": 492,
+              "size": 32,
+              "reset_value": 301989888,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "READ_INIT_NUM": {
+                    "description": "Configures the initial read time of eFuse.",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "WR_TIM_CONF1": {
+              "description": "Configurarion register 1 of eFuse programming timing parameters.",
+              "offset": 496,
+              "size": 32,
+              "reset_value": 2654208,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWR_ON_NUM": {
+                    "description": "Configures the power up time for VDDQ.",
+                    "offset": 8,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "WR_TIM_CONF2": {
+              "description": "Configurarion register 2 of eFuse programming timing parameters.",
+              "offset": 500,
+              "size": 32,
+              "reset_value": 400,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWR_OFF_NUM": {
+                    "description": "Configures the power outage time for VDDQ.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "eFuse version register.",
+              "offset": 508,
+              "size": 32,
+              "reset_value": 33583616,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "Stores eFuse version.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "EXTMEM": {
+        "description": "External Memory",
+        "children": {
+          "registers": {
+            "ICACHE_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_ENABLE": {
+                    "description": "The bit is used to activate the data cache. 0: disable, 1: enable",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_CTRL1": {
+              "description": "This description will be updated in the near future.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SHUT_IBUS": {
+                    "description": "The bit is used to disable core0 ibus, 0: enable, 1: disable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_SHUT_DBUS": {
+                    "description": "The bit is used to disable core1 ibus, 0: enable, 1: disable",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_TAG_POWER_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 5,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_TAG_MEM_FORCE_ON": {
+                    "description": "The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_TAG_MEM_FORCE_PD": {
+                    "description": "The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICACHE_TAG_MEM_FORCE_PU": {
+                    "description": "The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOCK_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOCK_SCT0_EN": {
+                    "description": "The bit is used to enable the first section of prelock function.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_PRELOCK_SCT1_EN": {
+                    "description": "The bit is used to enable the second section of prelock function.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOCK_SCT0_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOCK_SCT0_ADDR": {
+                    "description": "The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOCK_SCT1_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOCK_SCT1_ADDR": {
+                    "description": "The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOCK_SCT_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOCK_SCT1_SIZE": {
+                    "description": "The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "ICACHE_PRELOCK_SCT0_SIZE": {
+                    "description": "The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ICACHE_LOCK_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 4,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_LOCK_ENA": {
+                    "description": "The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_UNLOCK_ENA": {
+                    "description": "The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICACHE_LOCK_DONE": {
+                    "description": "The bit is used to indicate unlock/lock operation is finished.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ICACHE_LOCK_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_LOCK_ADDR": {
+                    "description": "The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_LOCK_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_LOCK_SIZE": {
+                    "description": "The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ICACHE_SYNC_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_INVALIDATE_ENA": {
+                    "description": "The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_SYNC_DONE": {
+                    "description": "The bit is used to indicate invalidate operation is finished.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ICACHE_SYNC_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_ADDR": {
+                    "description": "The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_SYNC_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_SIZE": {
+                    "description": "The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.",
+                    "offset": 0,
+                    "size": 23
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOAD_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOAD_ENA": {
+                    "description": "The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_PRELOAD_DONE": {
+                    "description": "The bit is used to indicate preload operation is finished.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ICACHE_PRELOAD_ORDER": {
+                    "description": "The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOAD_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOAD_ADDR": {
+                    "description": "The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOAD_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOAD_SIZE": {
+                    "description": "The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "ICACHE_AUTOLOAD_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_AUTOLOAD_SCT0_ENA": {
+                    "description": "The bits are used to enable the first section for autoload operation.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_AUTOLOAD_SCT1_ENA": {
+                    "description": "The bits are used to enable the second section for autoload operation.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICACHE_AUTOLOAD_ENA": {
+                    "description": "The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ICACHE_AUTOLOAD_DONE": {
+                    "description": "The bit is used to indicate autoload operation is finished.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ICACHE_AUTOLOAD_ORDER": {
+                    "description": "The bits are used to configure the direction of autoload. 1: descending, 0: ascending.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ICACHE_AUTOLOAD_RQST": {
+                    "description": "The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.",
+                    "offset": 5,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "ICACHE_AUTOLOAD_SCT0_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_AUTOLOAD_SCT0_ADDR": {
+                    "description": "The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_AUTOLOAD_SCT0_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_AUTOLOAD_SCT0_SIZE": {
+                    "description": "The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.",
+                    "offset": 0,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "ICACHE_AUTOLOAD_SCT1_ADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_AUTOLOAD_SCT1_ADDR": {
+                    "description": "The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ICACHE_AUTOLOAD_SCT1_SIZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_AUTOLOAD_SCT1_SIZE": {
+                    "description": "The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.",
+                    "offset": 0,
+                    "size": 27
+                  }
+                }
+              }
+            },
+            "IBUS_TO_FLASH_START_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 1107296256,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_TO_FLASH_START_VADDR": {
+                    "description": "The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "IBUS_TO_FLASH_END_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 1115684863,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_TO_FLASH_END_VADDR": {
+                    "description": "The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DBUS_TO_FLASH_START_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 1006632960,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_TO_FLASH_START_VADDR": {
+                    "description": "The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "DBUS_TO_FLASH_END_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 1015021567,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_TO_FLASH_END_VADDR": {
+                    "description": "The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CACHE_ACS_CNT_CLR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_ACS_CNT_CLR": {
+                    "description": "The bit is used to clear ibus counter.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DBUS_ACS_CNT_CLR": {
+                    "description": "The bit is used to clear dbus counter.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "IBUS_ACS_MISS_CNT": {
+              "description": "This description will be updated in the near future.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_ACS_MISS_CNT": {
+                    "description": "The bits are used to count the number of the cache miss caused by ibus access flash.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IBUS_ACS_CNT": {
+              "description": "This description will be updated in the near future.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_ACS_CNT": {
+                    "description": "The bits are used to count the number of ibus access flash through icache.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DBUS_ACS_FLASH_MISS_CNT": {
+              "description": "This description will be updated in the near future.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_ACS_FLASH_MISS_CNT": {
+                    "description": "The bits are used to count the number of the cache miss caused by dbus access flash.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DBUS_ACS_CNT": {
+              "description": "This description will be updated in the near future.",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_ACS_CNT": {
+                    "description": "The bits are used to count the number of dbus access flash through icache.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_ILG_INT_ENA": {
+              "description": "This description will be updated in the near future.",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_OP_FAULT_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by sync configurations fault.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_PRELOAD_OP_FAULT_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by preload configurations fault.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MMU_ENTRY_FAULT_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by mmu entry fault.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "IBUS_CNT_OVF_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by ibus counter overflow.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DBUS_CNT_OVF_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by dbus counter overflow.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_ILG_INT_CLR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_OP_FAULT_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by sync configurations fault.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "ICACHE_PRELOAD_OP_FAULT_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by preload configurations fault.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MMU_ENTRY_FAULT_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by mmu entry fault.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IBUS_CNT_OVF_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by ibus counter overflow.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DBUS_CNT_OVF_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by dbus counter overflow.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CACHE_ILG_INT_ST": {
+              "description": "This description will be updated in the near future.",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_OP_FAULT_ST": {
+                    "description": "The bit is used to indicate interrupt by sync configurations fault.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ICACHE_PRELOAD_OP_FAULT_ST": {
+                    "description": "The bit is used to indicate interrupt by preload configurations fault.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MMU_ENTRY_FAULT_ST": {
+                    "description": "The bit is used to indicate interrupt by mmu entry fault.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IBUS_ACS_CNT_OVF_ST": {
+                    "description": "The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IBUS_ACS_MISS_CNT_OVF_ST": {
+                    "description": "The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DBUS_ACS_CNT_OVF_ST": {
+                    "description": "The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DBUS_ACS_FLASH_MISS_CNT_OVF_ST": {
+                    "description": "The bit is used to indicate interrupt by dbus access flash miss counter overflow.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE0_ACS_CACHE_INT_ENA": {
+              "description": "This description will be updated in the near future.",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_IBUS_ACS_MSK_IC_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE0_IBUS_WR_IC_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by ibus trying to write icache",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CORE0_IBUS_REJECT_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by authentication fail.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CORE0_DBUS_ACS_MSK_IC_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CORE0_DBUS_REJECT_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by authentication fail.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CORE0_DBUS_WR_IC_INT_ENA": {
+                    "description": "The bit is used to enable interrupt by dbus trying to write icache",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE0_ACS_CACHE_INT_CLR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_IBUS_ACS_MSK_IC_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CORE0_IBUS_WR_IC_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by ibus trying to write icache",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CORE0_IBUS_REJECT_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by authentication fail.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CORE0_DBUS_ACS_MSK_IC_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CORE0_DBUS_REJECT_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by authentication fail.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CORE0_DBUS_WR_IC_INT_CLR": {
+                    "description": "The bit is used to clear interrupt by dbus trying to write icache",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CORE0_ACS_CACHE_INT_ST": {
+              "description": "This description will be updated in the near future.",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_IBUS_ACS_MSK_ICACHE_ST": {
+                    "description": "The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE0_IBUS_WR_ICACHE_ST": {
+                    "description": "The bit is used to indicate interrupt by ibus trying to write icache",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE0_IBUS_REJECT_ST": {
+                    "description": "The bit is used to indicate interrupt by authentication fail.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE0_DBUS_ACS_MSK_ICACHE_ST": {
+                    "description": "The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE0_DBUS_REJECT_ST": {
+                    "description": "The bit is used to indicate interrupt by authentication fail.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE0_DBUS_WR_ICACHE_ST": {
+                    "description": "The bit is used to indicate interrupt by dbus trying to write icache",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE0_DBUS_REJECT_ST": {
+              "description": "This description will be updated in the near future.",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_DBUS_ATTR": {
+                    "description": "The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "CORE0_DBUS_WORLD": {
+                    "description": "The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE0_DBUS_REJECT_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_DBUS_VADDR": {
+                    "description": "The bits are used to indicate the virtual address of CPU access dbus when authentication fail.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE0_IBUS_REJECT_ST": {
+              "description": "This description will be updated in the near future.",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_IBUS_ATTR": {
+                    "description": "The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "CORE0_IBUS_WORLD": {
+                    "description": "The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE0_IBUS_REJECT_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE0_IBUS_VADDR": {
+                    "description": "The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_FAULT_CONTENT": {
+              "description": "This description will be updated in the near future.",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_MMU_FAULT_CONTENT": {
+                    "description": "The bits are used to indicate the content of mmu entry which cause mmu fault..",
+                    "offset": 0,
+                    "size": 10,
+                    "access": "read-only"
+                  },
+                  "CACHE_MMU_FAULT_CODE": {
+                    "description": "The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.",
+                    "offset": 10,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_FAULT_VADDR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_MMU_FAULT_VADDR": {
+                    "description": "The bits are used to indicate the virtual address which cause mmu fault..",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_WRAP_AROUND_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_FLASH_WRAP_AROUND": {
+                    "description": "The bit is used to enable wrap around mode when read data from flash.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_POWER_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 5,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_MMU_MEM_FORCE_ON": {
+                    "description": "The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CACHE_MMU_MEM_FORCE_PD": {
+                    "description": "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CACHE_MMU_MEM_FORCE_PU": {
+                    "description": "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_STATE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_STATE": {
+                    "description": "The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RECORD_DISABLE_DB_ENCRYPT": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RECORD_DISABLE_G0CB_DECRYPT": {
+                    "description": "Reserved.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON": {
+              "description": "This description will be updated in the near future.",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_FORCE_ON_MANUAL_CRYPT": {
+                    "description": "The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CLK_FORCE_ON_AUTO_CRYPT": {
+                    "description": "The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CLK_FORCE_ON_CRYPT": {
+                    "description": "The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_PRELOAD_INT_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOAD_INT_ST": {
+                    "description": "The bit is used to indicate the interrupt by  icache pre-load done.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ICACHE_PRELOAD_INT_ENA": {
+                    "description": "The bit is used to enable the interrupt by  icache pre-load done.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICACHE_PRELOAD_INT_CLR": {
+                    "description": "The bit is used to clear the interrupt by  icache pre-load done.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CACHE_SYNC_INT_CTRL": {
+              "description": "This description will be updated in the near future.",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_INT_ST": {
+                    "description": "The bit is used to indicate the interrupt by  icache sync done.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ICACHE_SYNC_INT_ENA": {
+                    "description": "The bit is used to enable the interrupt by  icache sync done.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ICACHE_SYNC_INT_CLR": {
+                    "description": "The bit is used to clear the interrupt by  icache sync done.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_OWNER": {
+              "description": "This description will be updated in the near future.",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_MMU_OWNER": {
+                    "description": "The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CACHE_CONF_MISC": {
+              "description": "This description will be updated in the near future.",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT": {
+                    "description": "The bit is used to disable checking mmu entry fault by preload operation.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT": {
+                    "description": "The bit is used to disable checking mmu entry fault by sync operation.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CACHE_TRACE_ENA": {
+                    "description": "The bit is used to enable cache trace function.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ICACHE_FREEZE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENA": {
+                    "description": "The bit is used to enable icache freeze mode",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MODE": {
+                    "description": "The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DONE": {
+                    "description": "The bit is used to indicate icache freeze success",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ICACHE_ATOMIC_OPERATE_ENA": {
+              "description": "This description will be updated in the near future.",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_ATOMIC_OPERATE_ENA": {
+                    "description": "The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_REQUEST": {
+              "description": "This description will be updated in the near future.",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BYPASS": {
+                    "description": "The bit is used to disable request recording which could cause performance issue",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IBUS_PMS_TBL_LOCK": {
+              "description": "This description will be updated in the near future.",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_PMS_LOCK": {
+                    "description": "The bit is used to configure the ibus permission control section boundary0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "IBUS_PMS_TBL_BOUNDARY0": {
+              "description": "This description will be updated in the near future.",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_PMS_BOUNDARY0": {
+                    "description": "The bit is used to configure the ibus permission control section boundary0",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IBUS_PMS_TBL_BOUNDARY1": {
+              "description": "This description will be updated in the near future.",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_PMS_BOUNDARY1": {
+                    "description": "The bit is used to configure the ibus permission control section boundary1",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IBUS_PMS_TBL_BOUNDARY2": {
+              "description": "This description will be updated in the near future.",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_PMS_BOUNDARY2": {
+                    "description": "The bit is used to configure the ibus permission control section boundary2",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "IBUS_PMS_TBL_ATTR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 255,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IBUS_PMS_SCT1_ATTR": {
+                    "description": "The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "IBUS_PMS_SCT2_ATTR": {
+                    "description": "The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1",
+                    "offset": 4,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "DBUS_PMS_TBL_LOCK": {
+              "description": "This description will be updated in the near future.",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_PMS_LOCK": {
+                    "description": "The bit is used to configure the ibus permission control section boundary0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DBUS_PMS_TBL_BOUNDARY0": {
+              "description": "This description will be updated in the near future.",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_PMS_BOUNDARY0": {
+                    "description": "The bit is used to configure the dbus permission control section boundary0",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DBUS_PMS_TBL_BOUNDARY1": {
+              "description": "This description will be updated in the near future.",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_PMS_BOUNDARY1": {
+                    "description": "The bit is used to configure the dbus permission control section boundary1",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DBUS_PMS_TBL_BOUNDARY2": {
+              "description": "This description will be updated in the near future.",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 2048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_PMS_BOUNDARY2": {
+                    "description": "The bit is used to configure the dbus permission control section boundary2",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "DBUS_PMS_TBL_ATTR": {
+              "description": "This description will be updated in the near future.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 15,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DBUS_PMS_SCT1_ATTR": {
+                    "description": "The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DBUS_PMS_SCT2_ATTR": {
+                    "description": "The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1",
+                    "offset": 2,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "clock gate enable.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REG_DATE": {
+              "description": "This description will be updated in the near future.",
+              "offset": 1020,
+              "size": 32,
+              "reset_value": 33583456,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "version information",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIO": {
+        "description": "General Purpose Input/Output",
+        "children": {
+          "registers": {
+            "BT_SELECT": {
+              "description": "GPIO bit select register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_SEL": {
+                    "description": "GPIO bit select register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "OUT": {
+              "description": "GPIO output register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA_ORIG": {
+                    "description": "GPIO output register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "OUT_W1TS": {
+              "description": "GPIO output set register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_W1TS": {
+                    "description": "GPIO output set register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "OUT_W1TC": {
+              "description": "GPIO output clear register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_W1TC": {
+                    "description": "GPIO output clear register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SDIO_SELECT": {
+              "description": "GPIO sdio select register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDIO_SEL": {
+                    "description": "GPIO sdio select register",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "ENABLE": {
+              "description": "GPIO output enable register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "GPIO output enable register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "ENABLE_W1TS": {
+              "description": "GPIO output enable set register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE_W1TS": {
+                    "description": "GPIO output enable set register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "ENABLE_W1TC": {
+              "description": "GPIO output enable clear register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE_W1TC": {
+                    "description": "GPIO output enable clear register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STRAP": {
+              "description": "pad strapping register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STRAPPING": {
+                    "description": "pad strapping register",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN": {
+              "description": "GPIO input register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA_NEXT": {
+                    "description": "GPIO input register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "GPIO interrupt status register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERRUPT": {
+                    "description": "GPIO interrupt status register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26
+                  }
+                }
+              }
+            },
+            "STATUS_W1TS": {
+              "description": "GPIO interrupt status set register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATUS_W1TS": {
+                    "description": "GPIO interrupt status set register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STATUS_W1TC": {
+              "description": "GPIO interrupt status clear register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATUS_W1TC": {
+                    "description": "GPIO interrupt status clear register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "PCPU_INT": {
+              "description": "GPIO PRO_CPU interrupt status register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PROCPU_INT": {
+                    "description": "GPIO PRO_CPU interrupt status register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PCPU_NMI_INT": {
+              "description": "GPIO PRO_CPU(not shielded) interrupt status register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PROCPU_NMI_INT": {
+                    "description": "GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CPUSDIO_INT": {
+              "description": "GPIO CPUSDIO interrupt status register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDIO_INT": {
+                    "description": "GPIO CPUSDIO interrupt status register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PIN": {
+              "description": "GPIO pin configuration register",
+              "offset": 116,
+              "size": 32,
+              "count": 26,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PIN_SYNC2_BYPASS": {
+                    "description": "set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "PIN_PAD_DRIVER": {
+                    "description": "set this bit to select pad driver. 1:open-drain. :normal.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PIN_SYNC1_BYPASS": {
+                    "description": "set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "PIN_INT_TYPE": {
+                    "description": "set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level",
+                    "offset": 7,
+                    "size": 3
+                  },
+                  "PIN_WAKEUP_ENABLE": {
+                    "description": "set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "PIN_CONFIG": {
+                    "description": "reserved",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "PIN_INT_ENA": {
+                    "description": "set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.",
+                    "offset": 13,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "STATUS_NEXT": {
+              "description": "GPIO interrupt source register",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATUS_INTERRUPT_NEXT": {
+                    "description": "GPIO interrupt source register for GPIO0-25",
+                    "offset": 0,
+                    "size": 26,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FUNC_IN_SEL_CFG": {
+              "description": "GPIO input function configuration register",
+              "offset": 340,
+              "size": 32,
+              "count": 128,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_SEL": {
+                    "description": "set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level.",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "IN_INV_SEL": {
+                    "description": "set this bit to invert input signal. 1:invert. :not invert.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SEL": {
+                    "description": "set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FUNC_OUT_SEL_CFG": {
+              "description": "GPIO output function select register",
+              "offset": 1364,
+              "size": 32,
+              "count": 26,
+              "reset_value": 128,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_SEL": {
+                    "description": "The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "INV_SEL": {
+                    "description": "set this bit to invert output signal.1:invert.:not invert.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OEN_SEL": {
+                    "description": "set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OEN_INV_SEL": {
+                    "description": "set this bit to invert output enable signal.1:invert.:not invert.",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "GPIO clock gate register",
+              "offset": 1580,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "set this bit to enable GPIO clock gate",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REG_DATE": {
+              "description": "GPIO version register",
+              "offset": 1788,
+              "size": 32,
+              "reset_value": 33579312,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REG_DATE": {
+                    "description": "version register",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "GPIOSD": {
+        "description": "Sigma-Delta Modulation",
+        "children": {
+          "registers": {
+            "SIGMADELTA": {
+              "description": "Duty Cycle Configure Register of SDM%s",
+              "offset": 0,
+              "size": 32,
+              "count": 4,
+              "reset_value": 65280,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SD0_IN": {
+                    "description": "This field is used to configure the duty cycle of sigma delta modulation output.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SD0_PRESCALE": {
+                    "description": "This field is used to set a divider value to divide APB clock.",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SIGMADELTA_CG": {
+              "description": "Clock Gating Configure Register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "Clock enable bit of configuration registers for sigma delta modulation.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SIGMADELTA_MISC": {
+              "description": "MISC Register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FUNCTION_CLK_EN": {
+                    "description": "Clock enable bit of sigma delta modulation.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SPI_SWAP": {
+                    "description": "Reserved.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SIGMADELTA_VERSION": {
+              "description": "Version Control Register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 33579568,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPIO_SD_DATE": {
+                    "description": "Version control register.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "HMAC": {
+        "description": "HMAC (Hash-based Message Authentication Code) Accelerator",
+        "children": {
+          "registers": {
+            "SET_START": {
+              "description": "Process control register 0.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_START": {
+                    "description": "Start hmac operation.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_PARA_PURPOSE": {
+              "description": "Configure purpose.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PURPOSE_SET": {
+                    "description": "Set hmac parameter purpose.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_PARA_KEY": {
+              "description": "Configure key.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "KEY_SET": {
+                    "description": "Set hmac parameter key.",
+                    "offset": 0,
+                    "size": 3,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_PARA_FINISH": {
+              "description": "Finish initial configuration.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_PARA_END": {
+                    "description": "Finish hmac configuration.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_MESSAGE_ONE": {
+              "description": "Process control register 1.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_TEXT_ONE": {
+                    "description": "Call SHA to calculate one message block.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_MESSAGE_ING": {
+              "description": "Process control register 2.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_TEXT_ING": {
+                    "description": "Continue typical hmac.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_MESSAGE_END": {
+              "description": "Process control register 3.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_TEXT_END": {
+                    "description": "Start hardware padding.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_RESULT_FINISH": {
+              "description": "Process control register 4.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_RESULT_END": {
+                    "description": "After read result from upstream, then let hmac back to idle.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_INVALIDATE_JTAG": {
+              "description": "Invalidate register 0.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_INVALIDATE_JTAG": {
+                    "description": "Clear result from hmac downstream JTAG.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_INVALIDATE_DS": {
+              "description": "Invalidate register 1.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_INVALIDATE_DS": {
+                    "description": "Clear result from hmac downstream DS.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "QUERY_ERROR": {
+              "description": "Error register.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "QUREY_CHECK": {
+                    "description": "Hmac configuration state. 0: key are agree with purpose. 1: error",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "QUERY_BUSY": {
+              "description": "Busy register.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUSY_STATE": {
+                    "description": "Hmac state. 1'b0: idle. 1'b1: busy",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "WR_MESSAGE_MEM": {
+              "description": "Message block memory.",
+              "offset": 128,
+              "size": 8,
+              "count": 64,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "RD_RESULT_MEM": {
+              "description": "Result from upstream.",
+              "offset": 192,
+              "size": 8,
+              "count": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "SET_MESSAGE_PAD": {
+              "description": "Process control register 5.",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_TEXT_PAD": {
+                    "description": "Start software padding.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "ONE_BLOCK": {
+              "description": "Process control register 6.",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_ONE_BLOCK": {
+                    "description": "Don't have to do padding.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SOFT_JTAG_CTRL": {
+              "description": "Jtag register 0.",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SOFT_JTAG_CTRL": {
+                    "description": "Turn on JTAG verification.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "WR_JTAG": {
+              "description": "Jtag register 1.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WR_JTAG": {
+                    "description": "32-bit of key to be compared.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "write-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2C0": {
+        "description": "I2C (Inter-Integrated Circuit) Controller",
+        "children": {
+          "registers": {
+            "SCL_LOW_PERIOD": {
+              "description": "I2C_SCL_LOW_PERIOD_REG",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_LOW_PERIOD": {
+                    "description": "reg_scl_low_period",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "CTR": {
+              "description": "I2C_CTR_REG",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 523,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDA_FORCE_OUT": {
+                    "description": "reg_sda_force_out",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SCL_FORCE_OUT": {
+                    "description": "reg_scl_force_out",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SAMPLE_SCL_LEVEL": {
+                    "description": "reg_sample_scl_level",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RX_FULL_ACK_LEVEL": {
+                    "description": "reg_rx_full_ack_level",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MS_MODE": {
+                    "description": "reg_ms_mode",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TRANS_START": {
+                    "description": "reg_trans_start",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_LSB_FIRST": {
+                    "description": "reg_tx_lsb_first",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RX_LSB_FIRST": {
+                    "description": "reg_rx_lsb_first",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "ARBITRATION_EN": {
+                    "description": "reg_arbitration_en",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FSM_RST": {
+                    "description": "reg_fsm_rst",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CONF_UPGATE": {
+                    "description": "reg_conf_upgate",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_TX_AUTO_START_EN": {
+                    "description": "reg_slv_tx_auto_start_en",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "ADDR_10BIT_RW_CHECK_EN": {
+                    "description": "reg_addr_10bit_rw_check_en",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ADDR_BROADCASTING_EN": {
+                    "description": "reg_addr_broadcasting_en",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SR": {
+              "description": "I2C_SR_REG",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 49152,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESP_REC": {
+                    "description": "reg_resp_rec",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAVE_RW": {
+                    "description": "reg_slave_rw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ARB_LOST": {
+                    "description": "reg_arb_lost",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUS_BUSY": {
+                    "description": "reg_bus_busy",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAVE_ADDRESSED": {
+                    "description": "reg_slave_addressed",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_CNT": {
+                    "description": "reg_rxfifo_cnt",
+                    "offset": 8,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "STRETCH_CAUSE": {
+                    "description": "reg_stretch_cause",
+                    "offset": 14,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_CNT": {
+                    "description": "reg_txfifo_cnt",
+                    "offset": 18,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "SCL_MAIN_STATE_LAST": {
+                    "description": "reg_scl_main_state_last",
+                    "offset": 24,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "SCL_STATE_LAST": {
+                    "description": "reg_scl_state_last",
+                    "offset": 28,
+                    "size": 3,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TO": {
+              "description": "I2C_TO_REG",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME_OUT_VALUE": {
+                    "description": "reg_time_out_value",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "TIME_OUT_EN": {
+                    "description": "reg_time_out_en",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLAVE_ADDR": {
+              "description": "I2C_SLAVE_ADDR_REG",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLAVE_ADDR": {
+                    "description": "reg_slave_addr",
+                    "offset": 0,
+                    "size": 15
+                  },
+                  "ADDR_10BIT_EN": {
+                    "description": "reg_addr_10bit_en",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FIFO_ST": {
+              "description": "I2C_FIFO_ST_REG",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_RADDR": {
+                    "description": "reg_rxfifo_raddr",
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_WADDR": {
+                    "description": "reg_rxfifo_waddr",
+                    "offset": 5,
+                    "size": 5,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_RADDR": {
+                    "description": "reg_txfifo_raddr",
+                    "offset": 10,
+                    "size": 5,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_WADDR": {
+                    "description": "reg_txfifo_waddr",
+                    "offset": 15,
+                    "size": 5,
+                    "access": "read-only"
+                  },
+                  "SLAVE_RW_POINT": {
+                    "description": "reg_slave_rw_point",
+                    "offset": 22,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FIFO_CONF": {
+              "description": "I2C_FIFO_CONF_REG",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 16523,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_WM_THRHD": {
+                    "description": "reg_rxfifo_wm_thrhd",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "TXFIFO_WM_THRHD": {
+                    "description": "reg_txfifo_wm_thrhd",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "NONFIFO_EN": {
+                    "description": "reg_nonfifo_en",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "FIFO_ADDR_CFG_EN": {
+                    "description": "reg_fifo_addr_cfg_en",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RX_FIFO_RST": {
+                    "description": "reg_rx_fifo_rst",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TX_FIFO_RST": {
+                    "description": "reg_tx_fifo_rst",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FIFO_PRT_EN": {
+                    "description": "reg_fifo_prt_en",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATA": {
+              "description": "I2C_FIFO_DATA_REG",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FIFO_RDATA": {
+                    "description": "reg_fifo_rdata",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "I2C_INT_RAW_REG",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_WM_INT_RAW": {
+                    "description": "reg_rxfifo_wm_int_raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_WM_INT_RAW": {
+                    "description": "reg_txfifo_wm_int_raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_OVF_INT_RAW": {
+                    "description": "reg_rxfifo_ovf_int_raw",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "END_DETECT_INT_RAW": {
+                    "description": "reg_end_detect_int_raw",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BYTE_TRANS_DONE_INT_RAW": {
+                    "description": "reg_byte_trans_done_int_raw",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ARBITRATION_LOST_INT_RAW": {
+                    "description": "reg_arbitration_lost_int_raw",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_TXFIFO_UDF_INT_RAW": {
+                    "description": "reg_mst_txfifo_udf_int_raw",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_COMPLETE_INT_RAW": {
+                    "description": "reg_trans_complete_int_raw",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIME_OUT_INT_RAW": {
+                    "description": "reg_time_out_int_raw",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_START_INT_RAW": {
+                    "description": "reg_trans_start_int_raw",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NACK_INT_RAW": {
+                    "description": "reg_nack_int_raw",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_OVF_INT_RAW": {
+                    "description": "reg_txfifo_ovf_int_raw",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_UDF_INT_RAW": {
+                    "description": "reg_rxfifo_udf_int_raw",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SCL_ST_TO_INT_RAW": {
+                    "description": "reg_scl_st_to_int_raw",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SCL_MAIN_ST_TO_INT_RAW": {
+                    "description": "reg_scl_main_st_to_int_raw",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DET_START_INT_RAW": {
+                    "description": "reg_det_start_int_raw",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAVE_STRETCH_INT_RAW": {
+                    "description": "reg_slave_stretch_int_raw",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GENERAL_CALL_INT_RAW": {
+                    "description": "reg_general_call_int_raw",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "I2C_INT_CLR_REG",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_WM_INT_CLR": {
+                    "description": "reg_rxfifo_wm_int_clr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFIFO_WM_INT_CLR": {
+                    "description": "reg_txfifo_wm_int_clr",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RXFIFO_OVF_INT_CLR": {
+                    "description": "reg_rxfifo_ovf_int_clr",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "END_DETECT_INT_CLR": {
+                    "description": "reg_end_detect_int_clr",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "BYTE_TRANS_DONE_INT_CLR": {
+                    "description": "reg_byte_trans_done_int_clr",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "ARBITRATION_LOST_INT_CLR": {
+                    "description": "reg_arbitration_lost_int_clr",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MST_TXFIFO_UDF_INT_CLR": {
+                    "description": "reg_mst_txfifo_udf_int_clr",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TRANS_COMPLETE_INT_CLR": {
+                    "description": "reg_trans_complete_int_clr",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TIME_OUT_INT_CLR": {
+                    "description": "reg_time_out_int_clr",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TRANS_START_INT_CLR": {
+                    "description": "reg_trans_start_int_clr",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "NACK_INT_CLR": {
+                    "description": "reg_nack_int_clr",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFIFO_OVF_INT_CLR": {
+                    "description": "reg_txfifo_ovf_int_clr",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RXFIFO_UDF_INT_CLR": {
+                    "description": "reg_rxfifo_udf_int_clr",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SCL_ST_TO_INT_CLR": {
+                    "description": "reg_scl_st_to_int_clr",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SCL_MAIN_ST_TO_INT_CLR": {
+                    "description": "reg_scl_main_st_to_int_clr",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DET_START_INT_CLR": {
+                    "description": "reg_det_start_int_clr",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLAVE_STRETCH_INT_CLR": {
+                    "description": "reg_slave_stretch_int_clr",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "GENERAL_CALL_INT_CLR": {
+                    "description": "reg_general_call_int_clr",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "I2C_INT_ENA_REG",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_WM_INT_ENA": {
+                    "description": "reg_rxfifo_wm_int_ena",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXFIFO_WM_INT_ENA": {
+                    "description": "reg_txfifo_wm_int_ena",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RXFIFO_OVF_INT_ENA": {
+                    "description": "reg_rxfifo_ovf_int_ena",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "END_DETECT_INT_ENA": {
+                    "description": "reg_end_detect_int_ena",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "BYTE_TRANS_DONE_INT_ENA": {
+                    "description": "reg_byte_trans_done_int_ena",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "ARBITRATION_LOST_INT_ENA": {
+                    "description": "reg_arbitration_lost_int_ena",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MST_TXFIFO_UDF_INT_ENA": {
+                    "description": "reg_mst_txfifo_udf_int_ena",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TRANS_COMPLETE_INT_ENA": {
+                    "description": "reg_trans_complete_int_ena",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TIME_OUT_INT_ENA": {
+                    "description": "reg_time_out_int_ena",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TRANS_START_INT_ENA": {
+                    "description": "reg_trans_start_int_ena",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "NACK_INT_ENA": {
+                    "description": "reg_nack_int_ena",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TXFIFO_OVF_INT_ENA": {
+                    "description": "reg_txfifo_ovf_int_ena",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RXFIFO_UDF_INT_ENA": {
+                    "description": "reg_rxfifo_udf_int_ena",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SCL_ST_TO_INT_ENA": {
+                    "description": "reg_scl_st_to_int_ena",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SCL_MAIN_ST_TO_INT_ENA": {
+                    "description": "reg_scl_main_st_to_int_ena",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "DET_START_INT_ENA": {
+                    "description": "reg_det_start_int_ena",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SLAVE_STRETCH_INT_ENA": {
+                    "description": "reg_slave_stretch_int_ena",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "GENERAL_CALL_INT_ENA": {
+                    "description": "reg_general_call_int_ena",
+                    "offset": 17,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_STATUS": {
+              "description": "I2C_INT_STATUS_REG",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_WM_INT_ST": {
+                    "description": "reg_rxfifo_wm_int_st",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_WM_INT_ST": {
+                    "description": "reg_txfifo_wm_int_st",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_OVF_INT_ST": {
+                    "description": "reg_rxfifo_ovf_int_st",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "END_DETECT_INT_ST": {
+                    "description": "reg_end_detect_int_st",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BYTE_TRANS_DONE_INT_ST": {
+                    "description": "reg_byte_trans_done_int_st",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ARBITRATION_LOST_INT_ST": {
+                    "description": "reg_arbitration_lost_int_st",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_TXFIFO_UDF_INT_ST": {
+                    "description": "reg_mst_txfifo_udf_int_st",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_COMPLETE_INT_ST": {
+                    "description": "reg_trans_complete_int_st",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIME_OUT_INT_ST": {
+                    "description": "reg_time_out_int_st",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_START_INT_ST": {
+                    "description": "reg_trans_start_int_st",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "NACK_INT_ST": {
+                    "description": "reg_nack_int_st",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_OVF_INT_ST": {
+                    "description": "reg_txfifo_ovf_int_st",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_UDF_INT_ST": {
+                    "description": "reg_rxfifo_udf_int_st",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SCL_ST_TO_INT_ST": {
+                    "description": "reg_scl_st_to_int_st",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SCL_MAIN_ST_TO_INT_ST": {
+                    "description": "reg_scl_main_st_to_int_st",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DET_START_INT_ST": {
+                    "description": "reg_det_start_int_st",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLAVE_STRETCH_INT_ST": {
+                    "description": "reg_slave_stretch_int_st",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GENERAL_CALL_INT_ST": {
+                    "description": "reg_general_call_int_st",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SDA_HOLD": {
+              "description": "I2C_SDA_HOLD_REG",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_sda_hold_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "SDA_SAMPLE": {
+              "description": "I2C_SDA_SAMPLE_REG",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_sda_sample_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "SCL_HIGH_PERIOD": {
+              "description": "I2C_SCL_HIGH_PERIOD_REG",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_HIGH_PERIOD": {
+                    "description": "reg_scl_high_period",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "SCL_WAIT_HIGH_PERIOD": {
+                    "description": "reg_scl_wait_high_period",
+                    "offset": 9,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "SCL_START_HOLD": {
+              "description": "I2C_SCL_START_HOLD_REG",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_scl_start_hold_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "SCL_RSTART_SETUP": {
+              "description": "I2C_SCL_RSTART_SETUP_REG",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_scl_rstart_setup_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "SCL_STOP_HOLD": {
+              "description": "I2C_SCL_STOP_HOLD_REG",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_scl_stop_hold_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "SCL_STOP_SETUP": {
+              "description": "I2C_SCL_STOP_SETUP_REG",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME": {
+                    "description": "reg_scl_stop_setup_time",
+                    "offset": 0,
+                    "size": 9
+                  }
+                }
+              }
+            },
+            "FILTER_CFG": {
+              "description": "I2C_FILTER_CFG_REG",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_FILTER_THRES": {
+                    "description": "reg_scl_filter_thres",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "SDA_FILTER_THRES": {
+                    "description": "reg_sda_filter_thres",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "SCL_FILTER_EN": {
+                    "description": "reg_scl_filter_en",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SDA_FILTER_EN": {
+                    "description": "reg_sda_filter_en",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLK_CONF": {
+              "description": "I2C_CLK_CONF_REG",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 2097152,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCLK_DIV_NUM": {
+                    "description": "reg_sclk_div_num",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SCLK_DIV_A": {
+                    "description": "reg_sclk_div_a",
+                    "offset": 8,
+                    "size": 6
+                  },
+                  "SCLK_DIV_B": {
+                    "description": "reg_sclk_div_b",
+                    "offset": 14,
+                    "size": 6
+                  },
+                  "SCLK_SEL": {
+                    "description": "reg_sclk_sel",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "SCLK_ACTIVE": {
+                    "description": "reg_sclk_active",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMD": {
+              "description": "I2C_COMD%s_REG",
+              "offset": 88,
+              "size": 32,
+              "count": 8,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMMAND": {
+                    "description": "reg_command",
+                    "offset": 0,
+                    "size": 14
+                  },
+                  "COMMAND_DONE": {
+                    "description": "reg_command_done",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SCL_ST_TIME_OUT": {
+              "description": "I2C_SCL_ST_TIME_OUT_REG",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_ST_TO_I2C": {
+                    "description": "reg_scl_st_to_regno more than 23",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SCL_MAIN_ST_TIME_OUT": {
+              "description": "I2C_SCL_MAIN_ST_TIME_OUT_REG",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 16,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_MAIN_ST_TO_I2C": {
+                    "description": "reg_scl_main_st_to_regno more than 23",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SCL_SP_CONF": {
+              "description": "I2C_SCL_SP_CONF_REG",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCL_RST_SLV_EN": {
+                    "description": "reg_scl_rst_slv_en",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SCL_RST_SLV_NUM": {
+                    "description": "reg_scl_rst_slv_num",
+                    "offset": 1,
+                    "size": 5
+                  },
+                  "SCL_PD_EN": {
+                    "description": "reg_scl_pd_en",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SDA_PD_EN": {
+                    "description": "reg_sda_pd_en",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SCL_STRETCH_CONF": {
+              "description": "I2C_SCL_STRETCH_CONF_REG",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STRETCH_PROTECT_NUM": {
+                    "description": "reg_stretch_protect_num",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "SLAVE_SCL_STRETCH_EN": {
+                    "description": "reg_slave_scl_stretch_en",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SLAVE_SCL_STRETCH_CLR": {
+                    "description": "reg_slave_scl_stretch_clr",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLAVE_BYTE_ACK_CTL_EN": {
+                    "description": "reg_slave_byte_ack_ctl_en",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "SLAVE_BYTE_ACK_LVL": {
+                    "description": "reg_slave_byte_ack_lvl",
+                    "offset": 13,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "I2C_DATE_REG",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 537330177,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "reg_date",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TXFIFO_START_ADDR": {
+              "description": "I2C_TXFIFO_START_ADDR_REG",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TXFIFO_START_ADDR": {
+                    "description": "reg_txfifo_start_addr.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RXFIFO_START_ADDR": {
+              "description": "I2C_RXFIFO_START_ADDR_REG",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_START_ADDR": {
+                    "description": "reg_rxfifo_start_addr.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "I2S": {
+        "description": "I2S (Inter-IC Sound) Controller",
+        "children": {
+          "registers": {
+            "INT_RAW": {
+              "description": "I2S interrupt raw register, valid in level.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_DONE_INT_RAW": {
+                    "description": "The raw interrupt status bit  for the i2s_rx_done_int interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_DONE_INT_RAW": {
+                    "description": "The raw interrupt status bit  for the i2s_tx_done_int interrupt",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_HUNG_INT_RAW": {
+                    "description": "The raw interrupt status bit  for the i2s_rx_hung_int interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_HUNG_INT_RAW": {
+                    "description": "The raw interrupt status bit  for the i2s_tx_hung_int interrupt",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "I2S interrupt status register.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_DONE_INT_ST": {
+                    "description": "The masked interrupt status bit  for the i2s_rx_done_int interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_DONE_INT_ST": {
+                    "description": "The masked interrupt status bit  for the i2s_tx_done_int interrupt",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_HUNG_INT_ST": {
+                    "description": "The masked interrupt status bit  for the i2s_rx_hung_int interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_HUNG_INT_ST": {
+                    "description": "The masked interrupt status bit  for the i2s_tx_hung_int interrupt",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "I2S interrupt enable register.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_DONE_INT_ENA": {
+                    "description": "The interrupt enable bit  for the i2s_rx_done_int interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_DONE_INT_ENA": {
+                    "description": "The interrupt enable bit  for the i2s_tx_done_int interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RX_HUNG_INT_ENA": {
+                    "description": "The interrupt enable bit  for the i2s_rx_hung_int interrupt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TX_HUNG_INT_ENA": {
+                    "description": "The interrupt enable bit  for the i2s_tx_hung_int interrupt",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "I2S interrupt clear register.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_DONE_INT_CLR": {
+                    "description": "Set this bit to clear the i2s_rx_done_int interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_DONE_INT_CLR": {
+                    "description": "Set this bit to clear the i2s_tx_done_int interrupt",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RX_HUNG_INT_CLR": {
+                    "description": "Set this bit to clear the i2s_rx_hung_int interrupt",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_HUNG_INT_CLR": {
+                    "description": "Set this bit to clear the i2s_tx_hung_int interrupt",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "RX_CONF": {
+              "description": "I2S RX configure register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 38400,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_RESET": {
+                    "description": "Set this bit to reset receiver",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RX_FIFO_RESET": {
+                    "description": "Set this bit to reset Rx AFIFO",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RX_START": {
+                    "description": "Set this bit to start receiving data",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RX_SLAVE_MOD": {
+                    "description": "Set this bit to enable slave receiver mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RX_MONO": {
+                    "description": "Set this bit to enable receiver  in mono mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RX_BIG_ENDIAN": {
+                    "description": "I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RX_UPDATE": {
+                    "description": "Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RX_MONO_FST_VLD": {
+                    "description": "1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RX_PCM_CONF": {
+                    "description": "I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "RX_PCM_BYPASS": {
+                    "description": "Set this bit to bypass Compress/Decompress module for received data.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RX_STOP_MODE": {
+                    "description": "0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "RX_LEFT_ALIGN": {
+                    "description": "1: I2S RX left alignment mode. 0: I2S RX right alignment mode.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RX_24_FILL_EN": {
+                    "description": "1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RX_WS_IDLE_POL": {
+                    "description": "0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "RX_BIT_ORDER": {
+                    "description": "I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RX_TDM_EN": {
+                    "description": "1: Enable I2S TDM Rx mode . 0: Disable.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "RX_PDM_EN": {
+                    "description": "1: Enable I2S PDM Rx mode . 0: Disable.",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_CONF": {
+              "description": "I2S TX configure register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 45568,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_RESET": {
+                    "description": "Set this bit to reset transmitter",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_FIFO_RESET": {
+                    "description": "Set this bit to reset Tx AFIFO",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_START": {
+                    "description": "Set this bit to start transmitting data",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TX_SLAVE_MOD": {
+                    "description": "Set this bit to enable slave transmitter mode",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TX_MONO": {
+                    "description": "Set this bit to enable transmitter in mono mode",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TX_CHAN_EQUAL": {
+                    "description": "1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TX_BIG_ENDIAN": {
+                    "description": "I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TX_UPDATE": {
+                    "description": "Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TX_MONO_FST_VLD": {
+                    "description": "1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TX_PCM_CONF": {
+                    "description": "I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "TX_PCM_BYPASS": {
+                    "description": "Set this bit to bypass  Compress/Decompress module for transmitted data.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TX_STOP_EN": {
+                    "description": "Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TX_LEFT_ALIGN": {
+                    "description": "1: I2S TX left alignment mode. 0: I2S TX right alignment mode.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TX_24_FILL_EN": {
+                    "description": "1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "TX_WS_IDLE_POL": {
+                    "description": "0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TX_BIT_ORDER": {
+                    "description": "I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "TX_TDM_EN": {
+                    "description": "1: Enable I2S TDM Tx mode . 0: Disable.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "TX_PDM_EN": {
+                    "description": "1: Enable I2S PDM Tx mode . 0: Disable.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "TX_CHAN_MOD": {
+                    "description": "I2S transmitter channel mode configuration bits.",
+                    "offset": 24,
+                    "size": 3
+                  },
+                  "SIG_LOOPBACK": {
+                    "description": "Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RX_CONF1": {
+              "description": "I2S RX configure register 1",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 792584960,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_TDM_WS_WIDTH": {
+                    "description": "The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "RX_BCK_DIV_NUM": {
+                    "description": "Bit clock configuration bits in receiver mode.",
+                    "offset": 7,
+                    "size": 6
+                  },
+                  "RX_BITS_MOD": {
+                    "description": "Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.",
+                    "offset": 13,
+                    "size": 5
+                  },
+                  "RX_HALF_SAMPLE_BITS": {
+                    "description": "I2S Rx half sample bits -1.",
+                    "offset": 18,
+                    "size": 6
+                  },
+                  "RX_TDM_CHAN_BITS": {
+                    "description": "The Rx bit number for each channel minus 1in TDM mode.",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "RX_MSB_SHIFT": {
+                    "description": "Set this bit to enable receiver in Phillips standard mode",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_CONF1": {
+              "description": "I2S TX configure register 1",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 1866326784,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_TDM_WS_WIDTH": {
+                    "description": "The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck",
+                    "offset": 0,
+                    "size": 7
+                  },
+                  "TX_BCK_DIV_NUM": {
+                    "description": "Bit clock configuration bits in transmitter mode.",
+                    "offset": 7,
+                    "size": 6
+                  },
+                  "TX_BITS_MOD": {
+                    "description": "Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.",
+                    "offset": 13,
+                    "size": 5
+                  },
+                  "TX_HALF_SAMPLE_BITS": {
+                    "description": "I2S Tx half sample bits -1.",
+                    "offset": 18,
+                    "size": 6
+                  },
+                  "TX_TDM_CHAN_BITS": {
+                    "description": "The Tx bit number for each channel minus 1in TDM mode.",
+                    "offset": 24,
+                    "size": 5
+                  },
+                  "TX_MSB_SHIFT": {
+                    "description": "Set this bit to enable transmitter in Phillips standard mode",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "TX_BCK_NO_DLY": {
+                    "description": "1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.",
+                    "offset": 30,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RX_CLKM_CONF": {
+              "description": "I2S RX clock configure register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_CLKM_DIV_NUM": {
+                    "description": "Integral I2S clock divider value",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "RX_CLK_ACTIVE": {
+                    "description": "I2S Rx module clock enable signal.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RX_CLK_SEL": {
+                    "description": "Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.",
+                    "offset": 27,
+                    "size": 2
+                  },
+                  "MCLK_SEL": {
+                    "description": "0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_CLKM_CONF": {
+              "description": "I2S TX clock configure register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_CLKM_DIV_NUM": {
+                    "description": "Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "TX_CLK_ACTIVE": {
+                    "description": "I2S Tx module clock enable signal.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TX_CLK_SEL": {
+                    "description": "Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.",
+                    "offset": 27,
+                    "size": 2
+                  },
+                  "CLK_EN": {
+                    "description": "Set this bit to enable clk gate",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RX_CLKM_DIV_CONF": {
+              "description": "I2S RX module clock divider configure register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_CLKM_DIV_Z": {
+                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "RX_CLKM_DIV_Y": {
+                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).",
+                    "offset": 9,
+                    "size": 9
+                  },
+                  "RX_CLKM_DIV_X": {
+                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.",
+                    "offset": 18,
+                    "size": 9
+                  },
+                  "RX_CLKM_DIV_YN1": {
+                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_CLKM_DIV_CONF": {
+              "description": "I2S TX module clock divider configure register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_CLKM_DIV_Z": {
+                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "TX_CLKM_DIV_Y": {
+                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).",
+                    "offset": 9,
+                    "size": 9
+                  },
+                  "TX_CLKM_DIV_X": {
+                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.",
+                    "offset": 18,
+                    "size": 9
+                  },
+                  "TX_CLKM_DIV_YN1": {
+                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_PCM2PDM_CONF": {
+              "description": "I2S TX PCM2PDM configuration register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 4890628,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_PDM_HP_BYPASS": {
+                    "description": "I2S TX PDM bypass hp filter or not. The option has been removed.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_PDM_SINC_OSR2": {
+                    "description": "I2S TX PDM OSR2 value",
+                    "offset": 1,
+                    "size": 4
+                  },
+                  "TX_PDM_PRESCALE": {
+                    "description": "I2S TX PDM prescale for sigmadelta",
+                    "offset": 5,
+                    "size": 8
+                  },
+                  "TX_PDM_HP_IN_SHIFT": {
+                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "TX_PDM_LP_IN_SHIFT": {
+                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
+                    "offset": 15,
+                    "size": 2
+                  },
+                  "TX_PDM_SINC_IN_SHIFT": {
+                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
+                    "offset": 17,
+                    "size": 2
+                  },
+                  "TX_PDM_SIGMADELTA_IN_SHIFT": {
+                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
+                    "offset": 19,
+                    "size": 2
+                  },
+                  "TX_PDM_SIGMADELTA_DITHER2": {
+                    "description": "I2S TX PDM sigmadelta dither2 value",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TX_PDM_SIGMADELTA_DITHER": {
+                    "description": "I2S TX PDM sigmadelta dither value",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TX_PDM_DAC_2OUT_EN": {
+                    "description": "I2S TX PDM dac mode enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TX_PDM_DAC_MODE_EN": {
+                    "description": "I2S TX PDM dac 2channel enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PCM2PDM_CONV_EN": {
+                    "description": "I2S TX PDM Converter enable",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_PCM2PDM_CONF1": {
+              "description": "I2S TX PCM2PDM configuration register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 66552768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_PDM_FP": {
+                    "description": "I2S TX PDM Fp",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "TX_PDM_FS": {
+                    "description": "I2S TX PDM Fs",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "TX_IIR_HP_MULT12_5": {
+                    "description": "The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "TX_IIR_HP_MULT12_0": {
+                    "description": "The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])",
+                    "offset": 23,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "RX_TDM_CTRL": {
+              "description": "I2S TX TDM mode control register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_TDM_PDM_CHAN0_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0:  Disable, just input 0 in this channel.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN1_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0:  Disable, just input 0 in this channel.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN2_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0:  Disable, just input 0 in this channel.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN3_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0:  Disable, just input 0 in this channel.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN4_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0:  Disable, just input 0 in this channel.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN5_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0:  Disable, just input 0 in this channel.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN6_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0:  Disable, just input 0 in this channel.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RX_TDM_PDM_CHAN7_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0:  Disable, just input 0 in this channel.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN8_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 8. 0:  Disable, just input 0 in this channel.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN9_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 9. 0:  Disable, just input 0 in this channel.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN10_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 10. 0:  Disable, just input 0 in this channel.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN11_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 11. 0:  Disable, just input 0 in this channel.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN12_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 12. 0:  Disable, just input 0 in this channel.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN13_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 13. 0:  Disable, just input 0 in this channel.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN14_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 14. 0:  Disable, just input 0 in this channel.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RX_TDM_CHAN15_EN": {
+                    "description": "1: Enable the valid data input of I2S RX TDM channel 15. 0:  Disable, just input 0 in this channel.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RX_TDM_TOT_CHAN_NUM": {
+                    "description": "The total channel number of I2S TX TDM mode.",
+                    "offset": 16,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "TX_TDM_CTRL": {
+              "description": "I2S TX TDM mode control register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 65535,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_TDM_CHAN0_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 0. 0:  Disable, just output 0 in this channel.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN1_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 1. 0:  Disable, just output 0 in this channel.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN2_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 2. 0:  Disable, just output 0 in this channel.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN3_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 3. 0:  Disable, just output 0 in this channel.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN4_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 4. 0:  Disable, just output 0 in this channel.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN5_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 5. 0:  Disable, just output 0 in this channel.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN6_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 6. 0:  Disable, just output 0 in this channel.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN7_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 7. 0:  Disable, just output 0 in this channel.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN8_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 8. 0:  Disable, just output 0 in this channel.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN9_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 9. 0:  Disable, just output 0 in this channel.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN10_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 10. 0:  Disable, just output 0 in this channel.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN11_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 11. 0:  Disable, just output 0 in this channel.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN12_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 12. 0:  Disable, just output 0 in this channel.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN13_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 13. 0:  Disable, just output 0 in this channel.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN14_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 14. 0:  Disable, just output 0 in this channel.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TX_TDM_CHAN15_EN": {
+                    "description": "1: Enable the valid data output of I2S TX TDM channel 15. 0:  Disable, just output 0 in this channel.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "TX_TDM_TOT_CHAN_NUM": {
+                    "description": "The total channel number of I2S TX TDM mode.",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "TX_TDM_SKIP_MSK_EN": {
+                    "description": "When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RX_TIMING": {
+              "description": "I2S RX timing control register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_SD_IN_DM": {
+                    "description": "The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "RX_WS_OUT_DM": {
+                    "description": "The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "RX_BCK_OUT_DM": {
+                    "description": "The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "RX_WS_IN_DM": {
+                    "description": "The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "RX_BCK_IN_DM": {
+                    "description": "The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 28,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "TX_TIMING": {
+              "description": "I2S TX timing control register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_SD_OUT_DM": {
+                    "description": "The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "TX_SD1_OUT_DM": {
+                    "description": "The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "TX_WS_OUT_DM": {
+                    "description": "The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "TX_BCK_OUT_DM": {
+                    "description": "The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "TX_WS_IN_DM": {
+                    "description": "The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "TX_BCK_IN_DM": {
+                    "description": "The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
+                    "offset": 28,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "LC_HUNG_CONF": {
+              "description": "I2S HUNG configure register.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 2064,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LC_FIFO_TIMEOUT": {
+                    "description": "the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "LC_FIFO_TIMEOUT_SHIFT": {
+                    "description": "The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "LC_FIFO_TIMEOUT_ENA": {
+                    "description": "The enable bit for FIFO timeout",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RXEOF_NUM": {
+              "description": "I2S RX data number control register.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 64,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_EOF_NUM": {
+                    "description": "The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "CONF_SIGLE_DATA": {
+              "description": "I2S signal data register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SINGLE_DATA": {
+                    "description": "The configured constant channel data to be sent out.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STATE": {
+              "description": "I2S TX status register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_IDLE": {
+                    "description": "1: i2s_tx is idle state. 0: i2s_tx is working.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "Version control register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 33583648,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "I2S version control register",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "INTERRUPT_CORE0": {
+        "description": "Interrupt Core",
+        "children": {
+          "registers": {
+            "MAC_INTR_MAP": {
+              "description": "mac intr map register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC_INTR_MAP": {
+                    "description": "core0_mac_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "MAC_NMI_MAP": {
+              "description": "mac nmi_intr map register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MAC_NMI_MAP": {
+                    "description": "reg_core0_mac_nmi_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "PWR_INTR_MAP": {
+              "description": "pwr intr map register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PWR_INTR_MAP": {
+                    "description": "reg_core0_pwr_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "BB_INT_MAP": {
+              "description": "bb intr map register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BB_INT_MAP": {
+                    "description": "reg_core0_bb_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "BT_MAC_INT_MAP": {
+              "description": "bt intr map register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_MAC_INT_MAP": {
+                    "description": "reg_core0_bt_mac_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "BT_BB_INT_MAP": {
+              "description": "bb_bt intr map register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_BB_INT_MAP": {
+                    "description": "reg_core0_bt_bb_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "BT_BB_NMI_MAP": {
+              "description": "bb_bt_nmi intr map register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_BB_NMI_MAP": {
+                    "description": "reg_core0_bt_bb_nmi_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RWBT_IRQ_MAP": {
+              "description": "rwbt intr map register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWBT_IRQ_MAP": {
+                    "description": "reg_core0_rwbt_irq_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RWBLE_IRQ_MAP": {
+              "description": "rwble intr map register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWBLE_IRQ_MAP": {
+                    "description": "reg_core0_rwble_irq_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RWBT_NMI_MAP": {
+              "description": "rwbt_nmi intr map register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWBT_NMI_MAP": {
+                    "description": "reg_core0_rwbt_nmi_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RWBLE_NMI_MAP": {
+              "description": "rwble_nmi intr map register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RWBLE_NMI_MAP": {
+                    "description": "reg_core0_rwble_nmi_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "I2C_MST_INT_MAP": {
+              "description": "i2c intr map register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "I2C_MST_INT_MAP": {
+                    "description": "reg_core0_i2c_mst_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SLC0_INTR_MAP": {
+              "description": "slc0 intr map register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLC0_INTR_MAP": {
+                    "description": "reg_core0_slc0_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SLC1_INTR_MAP": {
+              "description": "slc1 intr map register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLC1_INTR_MAP": {
+                    "description": "reg_core0_slc1_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "APB_CTRL_INTR_MAP": {
+              "description": "apb_ctrl intr map register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_CTRL_INTR_MAP": {
+                    "description": "reg_core0_apb_ctrl_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "UHCI0_INTR_MAP": {
+              "description": "uchi0 intr map register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UHCI0_INTR_MAP": {
+                    "description": "reg_core0_uhci0_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "GPIO_INTERRUPT_PRO_MAP": {
+              "description": "gpio intr map register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPIO_INTERRUPT_PRO_MAP": {
+                    "description": "reg_core0_gpio_interrupt_pro_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "GPIO_INTERRUPT_PRO_NMI_MAP": {
+              "description": "gpio_pro intr map register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPIO_INTERRUPT_PRO_NMI_MAP": {
+                    "description": "reg_core0_gpio_interrupt_pro_nmi_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SPI_INTR_1_MAP": {
+              "description": "gpio_pro_nmi intr map register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_INTR_1_MAP": {
+                    "description": "reg_core0_spi_intr_1_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SPI_INTR_2_MAP": {
+              "description": "spi1 intr map register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_INTR_2_MAP": {
+                    "description": "reg_core0_spi_intr_2_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "I2S1_INT_MAP": {
+              "description": "spi2 intr map register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "I2S1_INT_MAP": {
+                    "description": "reg_core0_i2s1_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "UART_INTR_MAP": {
+              "description": "i2s1 intr map register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UART_INTR_MAP": {
+                    "description": "reg_core0_uart_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "UART1_INTR_MAP": {
+              "description": "uart1 intr map register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "UART1_INTR_MAP": {
+                    "description": "reg_core0_uart1_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "LEDC_INT_MAP": {
+              "description": "ledc intr map register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEDC_INT_MAP": {
+                    "description": "reg_core0_ledc_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "EFUSE_INT_MAP": {
+              "description": "efuse intr map register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EFUSE_INT_MAP": {
+                    "description": "reg_core0_efuse_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CAN_INT_MAP": {
+              "description": "can intr map register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CAN_INT_MAP": {
+                    "description": "reg_core0_can_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "USB_INTR_MAP": {
+              "description": "usb intr map register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USB_INTR_MAP": {
+                    "description": "reg_core0_usb_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RTC_CORE_INTR_MAP": {
+              "description": "rtc intr map register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CORE_INTR_MAP": {
+                    "description": "reg_core0_rtc_core_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RMT_INTR_MAP": {
+              "description": "rmt intr map register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RMT_INTR_MAP": {
+                    "description": "reg_core0_rmt_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "I2C_EXT0_INTR_MAP": {
+              "description": "i2c intr map register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "I2C_EXT0_INTR_MAP": {
+                    "description": "reg_core0_i2c_ext0_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TIMER_INT1_MAP": {
+              "description": "timer1 intr map register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_INT1_MAP": {
+                    "description": "reg_core0_timer_int1_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TIMER_INT2_MAP": {
+              "description": "timer2 intr map register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_INT2_MAP": {
+                    "description": "reg_core0_timer_int2_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TG_T0_INT_MAP": {
+              "description": "tg to intr map register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TG_T0_INT_MAP": {
+                    "description": "reg_core0_tg_t0_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TG_WDT_INT_MAP": {
+              "description": "tg wdt intr map register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TG_WDT_INT_MAP": {
+                    "description": "reg_core0_tg_wdt_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TG1_T0_INT_MAP": {
+              "description": "tg1 to intr map register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TG1_T0_INT_MAP": {
+                    "description": "reg_core0_tg1_t0_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TG1_WDT_INT_MAP": {
+              "description": "tg1 wdt intr map register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TG1_WDT_INT_MAP": {
+                    "description": "reg_core0_tg1_wdt_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CACHE_IA_INT_MAP": {
+              "description": "cache ia intr map register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_IA_INT_MAP": {
+                    "description": "reg_core0_cache_ia_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SYSTIMER_TARGET0_INT_MAP": {
+              "description": "systimer intr map register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSTIMER_TARGET0_INT_MAP": {
+                    "description": "reg_core0_systimer_target0_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SYSTIMER_TARGET1_INT_MAP": {
+              "description": "systimer target1 intr map register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSTIMER_TARGET1_INT_MAP": {
+                    "description": "reg_core0_systimer_target1_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SYSTIMER_TARGET2_INT_MAP": {
+              "description": "systimer target2 intr map register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSTIMER_TARGET2_INT_MAP": {
+                    "description": "reg_core0_systimer_target2_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SPI_MEM_REJECT_INTR_MAP": {
+              "description": "spi mem reject intr map register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI_MEM_REJECT_INTR_MAP": {
+                    "description": "reg_core0_spi_mem_reject_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "ICACHE_PRELOAD_INT_MAP": {
+              "description": "icache perload intr map register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_PRELOAD_INT_MAP": {
+                    "description": "reg_core0_icache_preload_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "ICACHE_SYNC_INT_MAP": {
+              "description": "icache sync intr map register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_SYNC_INT_MAP": {
+                    "description": "reg_core0_icache_sync_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "APB_ADC_INT_MAP": {
+              "description": "adc intr map register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_ADC_INT_MAP": {
+                    "description": "reg_core0_apb_adc_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMA_CH0_INT_MAP": {
+              "description": "dma ch0 intr map register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_CH0_INT_MAP": {
+                    "description": "reg_core0_dma_ch0_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMA_CH1_INT_MAP": {
+              "description": "dma ch1 intr map register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_CH1_INT_MAP": {
+                    "description": "reg_core0_dma_ch1_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMA_CH2_INT_MAP": {
+              "description": "dma ch2 intr map register",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_CH2_INT_MAP": {
+                    "description": "reg_core0_dma_ch2_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "RSA_INT_MAP": {
+              "description": "rsa intr map register",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RSA_INT_MAP": {
+                    "description": "reg_core0_rsa_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "AES_INT_MAP": {
+              "description": "aes intr map register",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AES_INT_MAP": {
+                    "description": "reg_core0_aes_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "SHA_INT_MAP": {
+              "description": "sha intr map register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SHA_INT_MAP": {
+                    "description": "reg_core0_sha_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_0_MAP": {
+              "description": "cpu from cpu 0 intr map register",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_0_MAP": {
+                    "description": "reg_core0_cpu_intr_from_cpu_0_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_1_MAP": {
+              "description": "cpu from cpu 0 intr map register",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_1_MAP": {
+                    "description": "reg_core0_cpu_intr_from_cpu_1_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_2_MAP": {
+              "description": "cpu from cpu 1 intr map register",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_2_MAP": {
+                    "description": "reg_core0_cpu_intr_from_cpu_2_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_3_MAP": {
+              "description": "cpu from cpu 3 intr map register",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_3_MAP": {
+                    "description": "reg_core0_cpu_intr_from_cpu_3_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "ASSIST_DEBUG_INTR_MAP": {
+              "description": "assist debug intr map register",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ASSIST_DEBUG_INTR_MAP": {
+                    "description": "reg_core0_assist_debug_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP": {
+              "description": "dma pms violatile intr map register",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP": {
+                    "description": "reg_core0_dma_apbperi_pms_monitor_violate_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
+              "description": "iram0 pms violatile intr map register",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
+                    "description": "reg_core0_core_0_iram0_pms_monitor_violate_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
+              "description": "mac intr map register",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
+                    "description": "reg_core0_core_0_dram0_pms_monitor_violate_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP": {
+              "description": "mac intr map register",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP": {
+                    "description": "reg_core0_core_0_pif_pms_monitor_violate_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP": {
+              "description": "mac intr map register",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP": {
+                    "description": "reg_core0_core_0_pif_pms_monitor_violate_size_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "BACKUP_PMS_VIOLATE_INTR_MAP": {
+              "description": "mac intr map register",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_PMS_VIOLATE_INTR_MAP": {
+                    "description": "reg_core0_backup_pms_violate_intr_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "CACHE_CORE0_ACS_INT_MAP": {
+              "description": "mac intr map register",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_CORE0_ACS_INT_MAP": {
+                    "description": "reg_core0_cache_core0_acs_int_map",
+                    "offset": 0,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "INTR_STATUS_REG_0": {
+              "description": "mac intr map register",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTR_STATUS_0": {
+                    "description": "reg_core0_intr_status_0",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INTR_STATUS_REG_1": {
+              "description": "mac intr map register",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTR_STATUS_1": {
+                    "description": "reg_core0_intr_status_1",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "mac intr map register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REG_CLK_EN": {
+                    "description": "reg_core0_reg_clk_en",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_INT_ENABLE": {
+              "description": "mac intr map register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INT_ENABLE": {
+                    "description": "reg_core0_cpu_int_enable",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CPU_INT_TYPE": {
+              "description": "mac intr map register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INT_TYPE": {
+                    "description": "reg_core0_cpu_int_type",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CPU_INT_CLEAR": {
+              "description": "mac intr map register",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INT_CLEAR": {
+                    "description": "reg_core0_cpu_int_clear",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CPU_INT_EIP_STATUS": {
+              "description": "mac intr map register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INT_EIP_STATUS": {
+                    "description": "reg_core0_cpu_int_eip_status",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_0": {
+              "description": "mac intr map register",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_0_MAP": {
+                    "description": "reg_core0_cpu_pri_0_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_1": {
+              "description": "mac intr map register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_1_MAP": {
+                    "description": "reg_core0_cpu_pri_1_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_2": {
+              "description": "mac intr map register",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_2_MAP": {
+                    "description": "reg_core0_cpu_pri_2_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_3": {
+              "description": "mac intr map register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_3_MAP": {
+                    "description": "reg_core0_cpu_pri_3_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_4": {
+              "description": "mac intr map register",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_4_MAP": {
+                    "description": "reg_core0_cpu_pri_4_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_5": {
+              "description": "mac intr map register",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_5_MAP": {
+                    "description": "reg_core0_cpu_pri_5_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_6": {
+              "description": "mac intr map register",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_6_MAP": {
+                    "description": "reg_core0_cpu_pri_6_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_7": {
+              "description": "mac intr map register",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_7_MAP": {
+                    "description": "reg_core0_cpu_pri_7_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_8": {
+              "description": "mac intr map register",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_8_MAP": {
+                    "description": "reg_core0_cpu_pri_8_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_9": {
+              "description": "mac intr map register",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_9_MAP": {
+                    "description": "reg_core0_cpu_pri_9_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_10": {
+              "description": "mac intr map register",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_10_MAP": {
+                    "description": "reg_core0_cpu_pri_10_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_11": {
+              "description": "mac intr map register",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_11_MAP": {
+                    "description": "reg_core0_cpu_pri_11_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_12": {
+              "description": "mac intr map register",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_12_MAP": {
+                    "description": "reg_core0_cpu_pri_12_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_13": {
+              "description": "mac intr map register",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_13_MAP": {
+                    "description": "reg_core0_cpu_pri_13_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_14": {
+              "description": "mac intr map register",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_14_MAP": {
+                    "description": "reg_core0_cpu_pri_14_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_15": {
+              "description": "mac intr map register",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_15_MAP": {
+                    "description": "reg_core0_cpu_pri_15_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_16": {
+              "description": "mac intr map register",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_16_MAP": {
+                    "description": "reg_core0_cpu_pri_16_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_17": {
+              "description": "mac intr map register",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_17_MAP": {
+                    "description": "reg_core0_cpu_pri_17_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_18": {
+              "description": "mac intr map register",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_18_MAP": {
+                    "description": "reg_core0_cpu_pri_18_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_19": {
+              "description": "mac intr map register",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_19_MAP": {
+                    "description": "reg_core0_cpu_pri_19_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_20": {
+              "description": "mac intr map register",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_20_MAP": {
+                    "description": "reg_core0_cpu_pri_20_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_21": {
+              "description": "mac intr map register",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_21_MAP": {
+                    "description": "reg_core0_cpu_pri_21_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_22": {
+              "description": "mac intr map register",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_22_MAP": {
+                    "description": "reg_core0_cpu_pri_22_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_23": {
+              "description": "mac intr map register",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_23_MAP": {
+                    "description": "reg_core0_cpu_pri_23_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_24": {
+              "description": "mac intr map register",
+              "offset": 372,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_24_MAP": {
+                    "description": "reg_core0_cpu_pri_24_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_25": {
+              "description": "mac intr map register",
+              "offset": 376,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_25_MAP": {
+                    "description": "reg_core0_cpu_pri_25_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_26": {
+              "description": "mac intr map register",
+              "offset": 380,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_26_MAP": {
+                    "description": "reg_core0_cpu_pri_26_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_27": {
+              "description": "mac intr map register",
+              "offset": 384,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_27_MAP": {
+                    "description": "reg_core0_cpu_pri_27_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_28": {
+              "description": "mac intr map register",
+              "offset": 388,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_28_MAP": {
+                    "description": "reg_core0_cpu_pri_28_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_29": {
+              "description": "mac intr map register",
+              "offset": 392,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_29_MAP": {
+                    "description": "reg_core0_cpu_pri_29_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_30": {
+              "description": "mac intr map register",
+              "offset": 396,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_30_MAP": {
+                    "description": "reg_core0_cpu_pri_30_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_PRI_31": {
+              "description": "mac intr map register",
+              "offset": 400,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_PRI_31_MAP": {
+                    "description": "reg_core0_cpu_pri_31_map",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "CPU_INT_THRESH": {
+              "description": "mac intr map register",
+              "offset": 404,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INT_THRESH": {
+                    "description": "reg_core0_cpu_int_thresh",
+                    "offset": 0,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "INTERRUPT_REG_DATE": {
+              "description": "mac intr map register",
+              "offset": 2044,
+              "size": 32,
+              "reset_value": 33583632,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERRUPT_REG_DATE": {
+                    "description": "reg_core0_interrupt_reg_date",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "IO_MUX": {
+        "description": "Input/Output Multiplexer",
+        "children": {
+          "registers": {
+            "PIN_CTRL": {
+              "description": "Clock Output Configuration Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 2047,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_OUT1": {
+                    "description": "If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "CLK_OUT2": {
+                    "description": "If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.",
+                    "offset": 4,
+                    "size": 4
+                  },
+                  "CLK_OUT3": {
+                    "description": "If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.",
+                    "offset": 8,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "GPIO": {
+              "description": "IO MUX Configure Register for pad XTAL_32K_P",
+              "offset": 4,
+              "size": 32,
+              "count": 22,
+              "reset_value": 2816,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MCU_OE": {
+                    "description": "Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SLP_SEL": {
+                    "description": "Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MCU_WPD": {
+                    "description": "Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MCU_WPU": {
+                    "description": "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MCU_IE": {
+                    "description": "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FUN_WPD": {
+                    "description": "Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FUN_WPU": {
+                    "description": "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FUN_IE": {
+                    "description": "Input enable of the pad. 1: input enabled; 0: input disabled.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FUN_DRV": {
+                    "description": "Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "MCU_SEL": {
+                    "description": "Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "FILTER_EN": {
+                    "description": "Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "IO MUX Version Control Register",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 33579088,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REG_DATE": {
+                    "description": "Version control register",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "LEDC": {
+        "description": "LED Control PWM (Pulse Width Modulation)",
+        "children": {
+          "registers": {
+            "LSCH0_CONF0": {
+              "description": "LEDC_LSCH0_CONF0.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH0": {
+                    "description": "reg_timer_sel_lsch0.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH0": {
+                    "description": "reg_sig_out_en_lsch0.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH0": {
+                    "description": "reg_idle_lv_lsch0.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH0": {
+                    "description": "reg_para_up_lsch0.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH0": {
+                    "description": "reg_ovf_num_lsch0.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH0": {
+                    "description": "reg_ovf_cnt_en_lsch0.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH0": {
+                    "description": "reg_ovf_cnt_reset_lsch0.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH0_HPOINT": {
+              "description": "LEDC_LSCH0_HPOINT.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH0": {
+                    "description": "reg_hpoint_lsch0.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH0_DUTY": {
+              "description": "LEDC_LSCH0_DUTY.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH0": {
+                    "description": "reg_duty_lsch0.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH0_CONF1": {
+              "description": "LEDC_LSCH0_CONF1.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH0": {
+                    "description": "reg_duty_scale_lsch0.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH0": {
+                    "description": "reg_duty_cycle_lsch0.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH0": {
+                    "description": "reg_duty_num_lsch0.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH0": {
+                    "description": "reg_duty_inc_lsch0.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH0": {
+                    "description": "reg_duty_start_lsch0.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH0_DUTY_R": {
+              "description": "LEDC_LSCH0_DUTY_R.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH0_R": {
+                    "description": "reg_duty_lsch0_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSCH1_CONF0": {
+              "description": "LEDC_LSCH1_CONF0.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH1": {
+                    "description": "reg_timer_sel_lsch1.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH1": {
+                    "description": "reg_sig_out_en_lsch1.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH1": {
+                    "description": "reg_idle_lv_lsch1.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH1": {
+                    "description": "reg_para_up_lsch1.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH1": {
+                    "description": "reg_ovf_num_lsch1.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH1": {
+                    "description": "reg_ovf_cnt_en_lsch1.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH1": {
+                    "description": "reg_ovf_cnt_reset_lsch1.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH1_HPOINT": {
+              "description": "LEDC_LSCH1_HPOINT.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH1": {
+                    "description": "reg_hpoint_lsch1.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH1_DUTY": {
+              "description": "LEDC_LSCH1_DUTY.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH1": {
+                    "description": "reg_duty_lsch1.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH1_CONF1": {
+              "description": "LEDC_LSCH1_CONF1.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH1": {
+                    "description": "reg_duty_scale_lsch1.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH1": {
+                    "description": "reg_duty_cycle_lsch1.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH1": {
+                    "description": "reg_duty_num_lsch1.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH1": {
+                    "description": "reg_duty_inc_lsch1.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH1": {
+                    "description": "reg_duty_start_lsch1.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH1_DUTY_R": {
+              "description": "LEDC_LSCH1_DUTY_R.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH1_R": {
+                    "description": "reg_duty_lsch1_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSCH2_CONF0": {
+              "description": "LEDC_LSCH2_CONF0.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH2": {
+                    "description": "reg_timer_sel_lsch2.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH2": {
+                    "description": "reg_sig_out_en_lsch2.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH2": {
+                    "description": "reg_idle_lv_lsch2.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH2": {
+                    "description": "reg_para_up_lsch2.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH2": {
+                    "description": "reg_ovf_num_lsch2.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH2": {
+                    "description": "reg_ovf_cnt_en_lsch2.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH2": {
+                    "description": "reg_ovf_cnt_reset_lsch2.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH2_HPOINT": {
+              "description": "LEDC_LSCH2_HPOINT.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH2": {
+                    "description": "reg_hpoint_lsch2.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH2_DUTY": {
+              "description": "LEDC_LSCH2_DUTY.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH2": {
+                    "description": "reg_duty_lsch2.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH2_CONF1": {
+              "description": "LEDC_LSCH2_CONF1.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH2": {
+                    "description": "reg_duty_scale_lsch2.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH2": {
+                    "description": "reg_duty_cycle_lsch2.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH2": {
+                    "description": "reg_duty_num_lsch2.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH2": {
+                    "description": "reg_duty_inc_lsch2.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH2": {
+                    "description": "reg_duty_start_lsch2.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH2_DUTY_R": {
+              "description": "LEDC_LSCH2_DUTY_R.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH2_R": {
+                    "description": "reg_duty_lsch2_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSCH3_CONF0": {
+              "description": "LEDC_LSCH3_CONF0.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH3": {
+                    "description": "reg_timer_sel_lsch3.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH3": {
+                    "description": "reg_sig_out_en_lsch3.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH3": {
+                    "description": "reg_idle_lv_lsch3.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH3": {
+                    "description": "reg_para_up_lsch3.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH3": {
+                    "description": "reg_ovf_num_lsch3.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH3": {
+                    "description": "reg_ovf_cnt_en_lsch3.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH3": {
+                    "description": "reg_ovf_cnt_reset_lsch3.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH3_HPOINT": {
+              "description": "LEDC_LSCH3_HPOINT.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH3": {
+                    "description": "reg_hpoint_lsch3.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH3_DUTY": {
+              "description": "LEDC_LSCH3_DUTY.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH3": {
+                    "description": "reg_duty_lsch3.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH3_CONF1": {
+              "description": "LEDC_LSCH3_CONF1.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH3": {
+                    "description": "reg_duty_scale_lsch3.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH3": {
+                    "description": "reg_duty_cycle_lsch3.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH3": {
+                    "description": "reg_duty_num_lsch3.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH3": {
+                    "description": "reg_duty_inc_lsch3.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH3": {
+                    "description": "reg_duty_start_lsch3.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH3_DUTY_R": {
+              "description": "LEDC_LSCH3_DUTY_R.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH3_R": {
+                    "description": "reg_duty_lsch3_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSCH4_CONF0": {
+              "description": "LEDC_LSCH4_CONF0.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH4": {
+                    "description": "reg_timer_sel_lsch4.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH4": {
+                    "description": "reg_sig_out_en_lsch4.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH4": {
+                    "description": "reg_idle_lv_lsch4.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH4": {
+                    "description": "reg_para_up_lsch4.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH4": {
+                    "description": "reg_ovf_num_lsch4.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH4": {
+                    "description": "reg_ovf_cnt_en_lsch4.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH4": {
+                    "description": "reg_ovf_cnt_reset_lsch4.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH4_HPOINT": {
+              "description": "LEDC_LSCH4_HPOINT.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH4": {
+                    "description": "reg_hpoint_lsch4.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH4_DUTY": {
+              "description": "LEDC_LSCH4_DUTY.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH4": {
+                    "description": "reg_duty_lsch4.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH4_CONF1": {
+              "description": "LEDC_LSCH4_CONF1.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH4": {
+                    "description": "reg_duty_scale_lsch4.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH4": {
+                    "description": "reg_duty_cycle_lsch4.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH4": {
+                    "description": "reg_duty_num_lsch4.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH4": {
+                    "description": "reg_duty_inc_lsch4.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH4": {
+                    "description": "reg_duty_start_lsch4.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH4_DUTY_R": {
+              "description": "LEDC_LSCH4_DUTY_R.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH4_R": {
+                    "description": "reg_duty_lsch4_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSCH5_CONF0": {
+              "description": "LEDC_LSCH5_CONF0.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SEL_LSCH5": {
+                    "description": "reg_timer_sel_lsch5.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SIG_OUT_EN_LSCH5": {
+                    "description": "reg_sig_out_en_lsch5.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "IDLE_LV_LSCH5": {
+                    "description": "reg_idle_lv_lsch5.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PARA_UP_LSCH5": {
+                    "description": "reg_para_up_lsch5.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_NUM_LSCH5": {
+                    "description": "reg_ovf_num_lsch5.",
+                    "offset": 5,
+                    "size": 10
+                  },
+                  "OVF_CNT_EN_LSCH5": {
+                    "description": "reg_ovf_cnt_en_lsch5.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "OVF_CNT_RESET_LSCH5": {
+                    "description": "reg_ovf_cnt_reset_lsch5.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSCH5_HPOINT": {
+              "description": "LEDC_LSCH5_HPOINT.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "HPOINT_LSCH5": {
+                    "description": "reg_hpoint_lsch5.",
+                    "offset": 0,
+                    "size": 14
+                  }
+                }
+              }
+            },
+            "LSCH5_DUTY": {
+              "description": "LEDC_LSCH5_DUTY.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH5": {
+                    "description": "reg_duty_lsch5.",
+                    "offset": 0,
+                    "size": 19
+                  }
+                }
+              }
+            },
+            "LSCH5_CONF1": {
+              "description": "LEDC_LSCH5_CONF1.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 1073741824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_SCALE_LSCH5": {
+                    "description": "reg_duty_scale_lsch5.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "DUTY_CYCLE_LSCH5": {
+                    "description": "reg_duty_cycle_lsch5.",
+                    "offset": 10,
+                    "size": 10
+                  },
+                  "DUTY_NUM_LSCH5": {
+                    "description": "reg_duty_num_lsch5.",
+                    "offset": 20,
+                    "size": 10
+                  },
+                  "DUTY_INC_LSCH5": {
+                    "description": "reg_duty_inc_lsch5.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DUTY_START_LSCH5": {
+                    "description": "reg_duty_start_lsch5.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LSCH5_DUTY_R": {
+              "description": "LEDC_LSCH5_DUTY_R.",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUTY_LSCH5_R": {
+                    "description": "reg_duty_lsch5_r.",
+                    "offset": 0,
+                    "size": 19,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER0_CONF": {
+              "description": "LEDC_LSTIMER0_CONF.",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_DUTY_RES": {
+                    "description": "reg_lstimer0_duty_res.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "CLK_DIV_LSTIMER0": {
+                    "description": "reg_clk_div_lstimer0.",
+                    "offset": 4,
+                    "size": 18
+                  },
+                  "LSTIMER0_PAUSE": {
+                    "description": "reg_lstimer0_pause.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "LSTIMER0_RST": {
+                    "description": "reg_lstimer0_rst.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TICK_SEL_LSTIMER0": {
+                    "description": "reg_tick_sel_lstimer0.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LSTIMER0_PARA_UP": {
+                    "description": "reg_lstimer0_para_up.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER0_VALUE": {
+              "description": "LEDC_LSTIMER0_VALUE.",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_CNT": {
+                    "description": "reg_lstimer0_cnt.",
+                    "offset": 0,
+                    "size": 14,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER1_CONF": {
+              "description": "LEDC_LSTIMER1_CONF.",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER1_DUTY_RES": {
+                    "description": "reg_lstimer1_duty_res.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "CLK_DIV_LSTIMER1": {
+                    "description": "reg_clk_div_lstimer1.",
+                    "offset": 4,
+                    "size": 18
+                  },
+                  "LSTIMER1_PAUSE": {
+                    "description": "reg_lstimer1_pause.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "LSTIMER1_RST": {
+                    "description": "reg_lstimer1_rst.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TICK_SEL_LSTIMER1": {
+                    "description": "reg_tick_sel_lstimer1.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LSTIMER1_PARA_UP": {
+                    "description": "reg_lstimer1_para_up.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER1_VALUE": {
+              "description": "LEDC_LSTIMER1_VALUE.",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER1_CNT": {
+                    "description": "reg_lstimer1_cnt.",
+                    "offset": 0,
+                    "size": 14,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER2_CONF": {
+              "description": "LEDC_LSTIMER2_CONF.",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER2_DUTY_RES": {
+                    "description": "reg_lstimer2_duty_res.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "CLK_DIV_LSTIMER2": {
+                    "description": "reg_clk_div_lstimer2.",
+                    "offset": 4,
+                    "size": 18
+                  },
+                  "LSTIMER2_PAUSE": {
+                    "description": "reg_lstimer2_pause.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "LSTIMER2_RST": {
+                    "description": "reg_lstimer2_rst.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TICK_SEL_LSTIMER2": {
+                    "description": "reg_tick_sel_lstimer2.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LSTIMER2_PARA_UP": {
+                    "description": "reg_lstimer2_para_up.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER2_VALUE": {
+              "description": "LEDC_LSTIMER2_VALUE.",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER2_CNT": {
+                    "description": "reg_lstimer2_cnt.",
+                    "offset": 0,
+                    "size": 14,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER3_CONF": {
+              "description": "LEDC_LSTIMER3_CONF.",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 8388608,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER3_DUTY_RES": {
+                    "description": "reg_lstimer3_duty_res.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "CLK_DIV_LSTIMER3": {
+                    "description": "reg_clk_div_lstimer3.",
+                    "offset": 4,
+                    "size": 18
+                  },
+                  "LSTIMER3_PAUSE": {
+                    "description": "reg_lstimer3_pause.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "LSTIMER3_RST": {
+                    "description": "reg_lstimer3_rst.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TICK_SEL_LSTIMER3": {
+                    "description": "reg_tick_sel_lstimer3.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LSTIMER3_PARA_UP": {
+                    "description": "reg_lstimer3_para_up.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "LSTIMER3_VALUE": {
+              "description": "LEDC_LSTIMER3_VALUE.",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER3_CNT": {
+                    "description": "reg_lstimer3_cnt.",
+                    "offset": 0,
+                    "size": 14,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "LEDC_INT_RAW.",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_OVF_INT_RAW": {
+                    "description": "reg_lstimer0_ovf_int_raw.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER1_OVF_INT_RAW": {
+                    "description": "reg_lstimer1_ovf_int_raw.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER2_OVF_INT_RAW": {
+                    "description": "reg_lstimer2_ovf_int_raw.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER3_OVF_INT_RAW": {
+                    "description": "reg_lstimer3_ovf_int_raw.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH0_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch0_int_raw.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH1_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch1_int_raw.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH2_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch2_int_raw.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH3_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch3_int_raw.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH4_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch4_int_raw.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH5_INT_RAW": {
+                    "description": "reg_duty_chng_end_lsch5_int_raw.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH0_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch0_int_raw.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH1_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch1_int_raw.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH2_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch2_int_raw.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH3_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch3_int_raw.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH4_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch4_int_raw.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH5_INT_RAW": {
+                    "description": "reg_ovf_cnt_lsch5_int_raw.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "LEDC_INT_ST.",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_OVF_INT_ST": {
+                    "description": "reg_lstimer0_ovf_int_st.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER1_OVF_INT_ST": {
+                    "description": "reg_lstimer1_ovf_int_st.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER2_OVF_INT_ST": {
+                    "description": "reg_lstimer2_ovf_int_st.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "LSTIMER3_OVF_INT_ST": {
+                    "description": "reg_lstimer3_ovf_int_st.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH0_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch0_int_st.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH1_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch1_int_st.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH2_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch2_int_st.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH3_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch3_int_st.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH4_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch4_int_st.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DUTY_CHNG_END_LSCH5_INT_ST": {
+                    "description": "reg_duty_chng_end_lsch5_int_st.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH0_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch0_int_st.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH1_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch1_int_st.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH2_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch2_int_st.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH3_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch3_int_st.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH4_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch4_int_st.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVF_CNT_LSCH5_INT_ST": {
+                    "description": "reg_ovf_cnt_lsch5_int_st.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "LEDC_INT_ENA.",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_OVF_INT_ENA": {
+                    "description": "reg_lstimer0_ovf_int_ena.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LSTIMER1_OVF_INT_ENA": {
+                    "description": "reg_lstimer1_ovf_int_ena.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "LSTIMER2_OVF_INT_ENA": {
+                    "description": "reg_lstimer2_ovf_int_ena.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LSTIMER3_OVF_INT_ENA": {
+                    "description": "reg_lstimer3_ovf_int_ena.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH0_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch0_int_ena.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH1_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch1_int_ena.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH2_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch2_int_ena.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH3_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch3_int_ena.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH4_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch4_int_ena.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DUTY_CHNG_END_LSCH5_INT_ENA": {
+                    "description": "reg_duty_chng_end_lsch5_int_ena.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH0_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch0_int_ena.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH1_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch1_int_ena.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH2_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch2_int_ena.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH3_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch3_int_ena.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH4_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch4_int_ena.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "OVF_CNT_LSCH5_INT_ENA": {
+                    "description": "reg_ovf_cnt_lsch5_int_ena.",
+                    "offset": 15,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "LEDC_INT_CLR.",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSTIMER0_OVF_INT_CLR": {
+                    "description": "reg_lstimer0_ovf_int_clr.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSTIMER1_OVF_INT_CLR": {
+                    "description": "reg_lstimer1_ovf_int_clr.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSTIMER2_OVF_INT_CLR": {
+                    "description": "reg_lstimer2_ovf_int_clr.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "LSTIMER3_OVF_INT_CLR": {
+                    "description": "reg_lstimer3_ovf_int_clr.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH0_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch0_int_clr.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH1_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch1_int_clr.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH2_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch2_int_clr.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH3_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch3_int_clr.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH4_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch4_int_clr.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DUTY_CHNG_END_LSCH5_INT_CLR": {
+                    "description": "reg_duty_chng_end_lsch5_int_clr.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH0_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch0_int_clr.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH1_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch1_int_clr.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH2_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch2_int_clr.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH3_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch3_int_clr.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH4_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch4_int_clr.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OVF_CNT_LSCH5_INT_CLR": {
+                    "description": "reg_ovf_cnt_lsch5_int_clr.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CONF": {
+              "description": "LEDC_CONF.",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_CLK_SEL": {
+                    "description": "reg_apb_clk_sel.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "LEDC_DATE.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 419829504,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LEDC_DATE": {
+                    "description": "reg_ledc_date.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RMT": {
+        "description": "Remote Control Peripheral",
+        "children": {
+          "registers": {
+            "CH0DATA": {
+              "description": "RMT_CH0DATA_REG.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH1DATA": {
+              "description": "RMT_CH1DATA_REG.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH2DATA": {
+              "description": "RMT_CH2DATA_REG.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH3DATA": {
+              "description": "RMT_CH3DATA_REG.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "Reserved.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CH2CONF1": {
+              "description": "RMT_CH2CONF1_REG.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 488,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_EN": {
+                    "description": "reg_rx_en_ch2.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MEM_WR_RST": {
+                    "description": "reg_mem_wr_rst_ch2.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_MEM_RST": {
+                    "description": "reg_apb_mem_rst_ch2.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MEM_OWNER": {
+                    "description": "reg_mem_owner_ch2.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RX_FILTER_EN": {
+                    "description": "reg_rx_filter_en_ch2.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RX_FILTER_THRES": {
+                    "description": "reg_rx_filter_thres_ch2.",
+                    "offset": 5,
+                    "size": 8
+                  },
+                  "MEM_RX_WRAP_EN": {
+                    "description": "reg_mem_rx_wrap_en_ch2.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "AFIFO_RST": {
+                    "description": "reg_afifo_rst_ch2.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CONF_UPDATE": {
+                    "description": "reg_conf_update_ch2.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CH3CONF1": {
+              "description": "RMT_CH3CONF1_REG.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 488,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_EN": {
+                    "description": "reg_rx_en_ch3.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MEM_WR_RST": {
+                    "description": "reg_mem_wr_rst_ch3.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB_MEM_RST": {
+                    "description": "reg_apb_mem_rst_ch3.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MEM_OWNER": {
+                    "description": "reg_mem_owner_ch3.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RX_FILTER_EN": {
+                    "description": "reg_rx_filter_en_ch3.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RX_FILTER_THRES": {
+                    "description": "reg_rx_filter_thres_ch3.",
+                    "offset": 5,
+                    "size": 8
+                  },
+                  "MEM_RX_WRAP_EN": {
+                    "description": "reg_mem_rx_wrap_en_ch3.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "AFIFO_RST": {
+                    "description": "reg_afifo_rst_ch3.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CONF_UPDATE": {
+                    "description": "reg_conf_update_ch3.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CH0STATUS": {
+              "description": "RMT_CH0STATUS_REG.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_RADDR_EX": {
+                    "description": "reg_mem_raddr_ex_ch0.",
+                    "offset": 0,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "STATE": {
+                    "description": "reg_state_ch0.",
+                    "offset": 9,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_WADDR": {
+                    "description": "reg_apb_mem_waddr_ch0.",
+                    "offset": 12,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RD_ERR": {
+                    "description": "reg_apb_mem_rd_err_ch0.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MEM_EMPTY": {
+                    "description": "reg_mem_empty_ch0.",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_WR_ERR": {
+                    "description": "reg_apb_mem_wr_err_ch0.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RADDR": {
+                    "description": "reg_apb_mem_raddr_ch0.",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CH1STATUS": {
+              "description": "RMT_CH1STATUS_REG.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_RADDR_EX": {
+                    "description": "reg_mem_raddr_ex_ch1.",
+                    "offset": 0,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "STATE": {
+                    "description": "reg_state_ch1.",
+                    "offset": 9,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_WADDR": {
+                    "description": "reg_apb_mem_waddr_ch1.",
+                    "offset": 12,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RD_ERR": {
+                    "description": "reg_apb_mem_rd_err_ch1.",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MEM_EMPTY": {
+                    "description": "reg_mem_empty_ch1.",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_WR_ERR": {
+                    "description": "reg_apb_mem_wr_err_ch1.",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RADDR": {
+                    "description": "reg_apb_mem_raddr_ch1.",
+                    "offset": 24,
+                    "size": 8,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CH2STATUS": {
+              "description": "RMT_CH2STATUS_REG.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_WADDR_EX": {
+                    "description": "reg_mem_waddr_ex_ch2.",
+                    "offset": 0,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RADDR": {
+                    "description": "reg_apb_mem_raddr_ch2.",
+                    "offset": 12,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "STATE": {
+                    "description": "reg_state_ch2.",
+                    "offset": 22,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "MEM_OWNER_ERR": {
+                    "description": "reg_mem_owner_err_ch2.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MEM_FULL": {
+                    "description": "reg_mem_full_ch2.",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RD_ERR": {
+                    "description": "reg_apb_mem_rd_err_ch2.",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CH3STATUS": {
+              "description": "RMT_CH3STATUS_REG.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_WADDR_EX": {
+                    "description": "reg_mem_waddr_ex_ch3.",
+                    "offset": 0,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RADDR": {
+                    "description": "reg_apb_mem_raddr_ch3.",
+                    "offset": 12,
+                    "size": 9,
+                    "access": "read-only"
+                  },
+                  "STATE": {
+                    "description": "reg_state_ch3.",
+                    "offset": 22,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "MEM_OWNER_ERR": {
+                    "description": "reg_mem_owner_err_ch3.",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MEM_FULL": {
+                    "description": "reg_mem_full_ch3.",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APB_MEM_RD_ERR": {
+                    "description": "reg_apb_mem_rd_err_ch3.",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "RMT_INT_RAW_REG.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH2_RX_THR_EVENT_INT_RAW": {
+                    "description": "reg_ch2_rx_thr_event_int_raw.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CH3_RX_THR_EVENT_INT_RAW": {
+                    "description": "reg_ch3_rx_thr_event_int_raw.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "RMT_INT_ST_REG.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH2_RX_THR_EVENT_INT_ST": {
+                    "description": "reg_ch2_rx_thr_event_int_st.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CH3_RX_THR_EVENT_INT_ST": {
+                    "description": "reg_ch3_rx_thr_event_int_st.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "RMT_INT_ENA_REG.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH2_RX_THR_EVENT_INT_ENA": {
+                    "description": "reg_ch2_rx_thr_event_int_ena.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CH3_RX_THR_EVENT_INT_ENA": {
+                    "description": "reg_ch3_rx_thr_event_int_ena.",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "RMT_INT_CLR_REG.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH2_RX_THR_EVENT_INT_CLR": {
+                    "description": "reg_ch2_rx_thr_event_int_clr.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CH3_RX_THR_EVENT_INT_CLR": {
+                    "description": "reg_ch3_rx_thr_event_int_clr.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CH0CARRIER_DUTY": {
+              "description": "RMT_CH0CARRIER_DUTY_REG.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 4194368,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CARRIER_LOW": {
+                    "description": "reg_carrier_low_ch0.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CARRIER_HIGH": {
+                    "description": "reg_carrier_high_ch0.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH1CARRIER_DUTY": {
+              "description": "RMT_CH1CARRIER_DUTY_REG.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 4194368,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CARRIER_LOW": {
+                    "description": "reg_carrier_low_ch1.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CARRIER_HIGH": {
+                    "description": "reg_carrier_high_ch1.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH2_RX_CARRIER_RM": {
+              "description": "RMT_CH2_RX_CARRIER_RM_REG.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CARRIER_LOW_THRES": {
+                    "description": "reg_carrier_low_thres_ch2.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CARRIER_HIGH_THRES": {
+                    "description": "reg_carrier_high_thres_ch2.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "CH3_RX_CARRIER_RM": {
+              "description": "RMT_CH3_RX_CARRIER_RM_REG.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CARRIER_LOW_THRES": {
+                    "description": "reg_carrier_low_thres_ch3.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "CARRIER_HIGH_THRES": {
+                    "description": "reg_carrier_high_thres_ch3.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SYS_CONF": {
+              "description": "RMT_SYS_CONF_REG.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 83886096,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_FIFO_MASK": {
+                    "description": "reg_apb_fifo_mask.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MEM_CLK_FORCE_ON": {
+                    "description": "reg_mem_clk_force_on.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MEM_FORCE_PD": {
+                    "description": "reg_rmt_mem_force_pd.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "MEM_FORCE_PU": {
+                    "description": "reg_rmt_mem_force_pu.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SCLK_DIV_NUM": {
+                    "description": "reg_rmt_sclk_div_num.",
+                    "offset": 4,
+                    "size": 8
+                  },
+                  "SCLK_DIV_A": {
+                    "description": "reg_rmt_sclk_div_a.",
+                    "offset": 12,
+                    "size": 6
+                  },
+                  "SCLK_DIV_B": {
+                    "description": "reg_rmt_sclk_div_b.",
+                    "offset": 18,
+                    "size": 6
+                  },
+                  "SCLK_SEL": {
+                    "description": "reg_rmt_sclk_sel.",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "SCLK_ACTIVE": {
+                    "description": "reg_rmt_sclk_active.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_SIM": {
+              "description": "RMT_TX_SIM_REG.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_SIM_CH0": {
+                    "description": "reg_rmt_tx_sim_ch0.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_SIM_CH1": {
+                    "description": "reg_rmt_tx_sim_ch1.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TX_SIM_EN": {
+                    "description": "reg_rmt_tx_sim_en.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REF_CNT_RST": {
+              "description": "RMT_REF_CNT_RST_REG.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CH0": {
+                    "description": "reg_ref_cnt_rst_ch0.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CH1": {
+                    "description": "reg_ref_cnt_rst_ch1.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CH2": {
+                    "description": "reg_ref_cnt_rst_ch2.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CH3": {
+                    "description": "reg_ref_cnt_rst_ch3.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "RMT_DATE_REG.",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 33579569,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "reg_rmt_date.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RNG": {
+        "description": "Hardware random number generator",
+        "children": {
+          "registers": {
+            "DATA": {
+              "description": "Random number data",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            }
+          }
+        }
+      },
+      "RSA": {
+        "description": "RSA (Rivest Shamir Adleman) Accelerator",
+        "children": {
+          "registers": {
+            "M_MEM": {
+              "description": "The memory that stores M",
+              "offset": 0,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "Z_MEM": {
+              "description": "The memory that stores Z",
+              "offset": 512,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "Y_MEM": {
+              "description": "The memory that stores Y",
+              "offset": 1024,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "X_MEM": {
+              "description": "The memory that stores X",
+              "offset": 1536,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "M_PRIME": {
+              "description": "RSA M_prime register",
+              "offset": 2048,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "M_PRIME": {
+                    "description": "Those bits stores m'",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "MODE": {
+              "description": "RSA mode register",
+              "offset": 2052,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "rsa mode (rsa length).",
+                    "offset": 0,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "QUERY_CLEAN": {
+              "description": "RSA query clean register",
+              "offset": 2056,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "QUERY_CLEAN": {
+                    "description": "query clean",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SET_START_MODEXP": {
+              "description": "RSA modular exponentiation trigger register.",
+              "offset": 2060,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_START_MODEXP": {
+                    "description": "start modular exponentiation",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_START_MODMULT": {
+              "description": "RSA modular multiplication trigger register.",
+              "offset": 2064,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_START_MODMULT": {
+                    "description": "start modular multiplication",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SET_START_MULT": {
+              "description": "RSA normal multiplication trigger register.",
+              "offset": 2068,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SET_START_MULT": {
+                    "description": "start multiplicaiton",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "QUERY_IDLE": {
+              "description": "RSA query idle register",
+              "offset": 2072,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "QUERY_IDLE": {
+                    "description": "query rsa idle. 1'b0: busy, 1'b1: idle",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "RSA interrupt clear register",
+              "offset": 2076,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLEAR_INTERRUPT": {
+                    "description": "set this bit to clear RSA interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CONSTANT_TIME": {
+              "description": "RSA constant time option register",
+              "offset": 2080,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONSTANT_TIME": {
+                    "description": "Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SEARCH_ENABLE": {
+              "description": "RSA search option",
+              "offset": 2084,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEARCH_ENABLE": {
+                    "description": "Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SEARCH_POS": {
+              "description": "RSA search position configure register",
+              "offset": 2088,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SEARCH_POS": {
+                    "description": "Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "RSA interrupt enable register",
+              "offset": 2092,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INT_ENA": {
+                    "description": "Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "RSA version control register",
+              "offset": 2096,
+              "size": 32,
+              "reset_value": 538969624,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "rsa version information",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "RTC_CNTL": {
+        "description": "Real-Time Clock Control",
+        "children": {
+          "registers": {
+            "OPTIONS0": {
+              "description": "rtc configure register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 469803008,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SW_STALL_APPCPU_C0": {
+                    "description": "{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "SW_STALL_PROCPU_C0": {
+                    "description": "{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "SW_APPCPU_RST": {
+                    "description": "APP CPU SW reset",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SW_PROCPU_RST": {
+                    "description": "PRO CPU SW reset",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "BB_I2C_FORCE_PD": {
+                    "description": "BB_I2C force power down",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BB_I2C_FORCE_PU": {
+                    "description": "BB_I2C force power up",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "BBPLL_I2C_FORCE_PD": {
+                    "description": "BB_PLL _I2C force power down",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BBPLL_I2C_FORCE_PU": {
+                    "description": "BB_PLL_I2C force power up",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "BBPLL_FORCE_PD": {
+                    "description": "BB_PLL force power down",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BBPLL_FORCE_PU": {
+                    "description": "BB_PLL force power up",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "XTL_FORCE_PD": {
+                    "description": "crystall force power down",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "XTL_FORCE_PU": {
+                    "description": "crystall force power up",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "XTL_EN_WAIT": {
+                    "description": "wait bias_sleep and current source wakeup",
+                    "offset": 14,
+                    "size": 4
+                  },
+                  "XTL_EXT_CTR_SEL": {
+                    "description": "analog configure",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "XTL_FORCE_ISO": {
+                    "description": "analog configure",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PLL_FORCE_ISO": {
+                    "description": "analog configure",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "ANALOG_FORCE_ISO": {
+                    "description": "analog configure",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "XTL_FORCE_NOISO": {
+                    "description": "analog configure",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "PLL_FORCE_NOISO": {
+                    "description": "analog configure",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "ANALOG_FORCE_NOISO": {
+                    "description": "analog configure",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_RST": {
+                    "description": "digital wrap force reset in deep sleep",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_NORST": {
+                    "description": "digital core force no reset in deep sleep",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SW_SYS_RST": {
+                    "description": "SW system reset",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "SLP_TIMER0": {
+              "description": "rtc configure register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_VAL_LO": {
+                    "description": "configure the  sleep time",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SLP_TIMER1": {
+              "description": "rtc configure register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_VAL_HI": {
+                    "description": "RTC sleep timer high 16 bits",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "RTC_MAIN_TIMER_ALARM_EN": {
+                    "description": "timer alarm enable bit",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "TIME_UPDATE": {
+              "description": "rtc configure register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_SYS_STALL": {
+                    "description": "Enable to record system stall time",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "TIMER_XTL_OFF": {
+                    "description": "Enable to record 40M XTAL OFF time",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "TIMER_SYS_RST": {
+                    "description": "enable to record system reset time",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "RTC_TIME_UPDATE": {
+                    "description": "Set 1: to update register with RTC timer",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "TIME_LOW0": {
+              "description": "rtc configure register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_TIMER_VALUE0_LOW": {
+                    "description": "RTC timer low 32 bits",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TIME_HIGH0": {
+              "description": "rtc configure register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_TIMER_VALUE0_HIGH": {
+                    "description": "RTC timer high 16 bits",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "STATE0": {
+              "description": "rtc configure register",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SW_CPU_INT": {
+                    "description": "rtc software interrupt to main cpu",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_SLP_REJECT_CAUSE_CLR": {
+                    "description": "clear rtc sleep reject cause",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APB2RTC_BRIDGE_SEL": {
+                    "description": "1: APB to RTC using bridge",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "SDIO_ACTIVE_IND": {
+                    "description": "SDIO active indication",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLP_WAKEUP": {
+                    "description": "leep wakeup bit",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "SLP_REJECT": {
+                    "description": "leep reject bit",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SLEEP_EN": {
+                    "description": "sleep enable bit",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TIMER1": {
+              "description": "rtc configure register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 672400387,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_STALL_EN": {
+                    "description": "CPU stall enable bit",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CPU_STALL_WAIT": {
+                    "description": "CPU stall wait cycles in fast_clk_rtc",
+                    "offset": 1,
+                    "size": 5
+                  },
+                  "CK8M_WAIT": {
+                    "description": "CK8M wait cycles in slow_clk_rtc",
+                    "offset": 6,
+                    "size": 8
+                  },
+                  "XTL_BUF_WAIT": {
+                    "description": "XTAL wait cycles in slow_clk_rtc",
+                    "offset": 14,
+                    "size": 10
+                  },
+                  "PLL_BUF_WAIT": {
+                    "description": "PLL wait cycles in slow_clk_rtc",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TIMER2": {
+              "description": "rtc configure register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 16777216,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MIN_TIME_CK8M_OFF": {
+                    "description": "minimal cycles in slow_clk_rtc for CK8M in power down state",
+                    "offset": 24,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TIMER3": {
+              "description": "rtc configure register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 168299016,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WIFI_WAIT_TIMER": {
+                    "description": "wifi power domain wakeup time",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "WIFI_POWERUP_TIMER": {
+                    "description": "wifi power domain power on time",
+                    "offset": 9,
+                    "size": 7
+                  },
+                  "BT_WAIT_TIMER": {
+                    "description": "bt power domain wakeup time",
+                    "offset": 16,
+                    "size": 9
+                  },
+                  "BT_POWERUP_TIMER": {
+                    "description": "bt power domain power on time",
+                    "offset": 25,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "TIMER4": {
+              "description": "rtc configure register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 270535176,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_TOP_WAIT_TIMER": {
+                    "description": "cpu top power domain wakeup time",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "CPU_TOP_POWERUP_TIMER": {
+                    "description": "cpu top power domain power on time",
+                    "offset": 9,
+                    "size": 7
+                  },
+                  "DG_WRAP_WAIT_TIMER": {
+                    "description": "digital wrap power domain wakeup time",
+                    "offset": 16,
+                    "size": 9
+                  },
+                  "DG_WRAP_POWERUP_TIMER": {
+                    "description": "digital wrap power domain power on time",
+                    "offset": 25,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "TIMER5": {
+              "description": "rtc configure register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 32768,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MIN_SLP_VAL": {
+                    "description": "minimal sleep cycles in slow_clk_rtc",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TIMER6": {
+              "description": "rtc configure register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 168296448,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DG_PERI_WAIT_TIMER": {
+                    "description": "digital peri power domain wakeup time",
+                    "offset": 16,
+                    "size": 9
+                  },
+                  "DG_PERI_POWERUP_TIMER": {
+                    "description": "digital peri power domain power on time",
+                    "offset": 25,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "ANA_CONF": {
+              "description": "rtc configure register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 12845056,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESET_POR_FORCE_PD": {
+                    "description": "force no bypass i2c power on reset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RESET_POR_FORCE_PU": {
+                    "description": "force bypass i2c power on reset",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "GLITCH_RST_EN": {
+                    "description": "enable glitch reset",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "SAR_I2C_PU": {
+                    "description": "PLLA force power up",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PLLA_FORCE_PD": {
+                    "description": "PLLA force power down",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PLLA_FORCE_PU": {
+                    "description": "PLLA force power up",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "BBPLL_CAL_SLP_START": {
+                    "description": "start BBPLL calibration during sleep",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PVTMON_PU": {
+                    "description": "1: PVTMON power up",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TXRF_I2C_PU": {
+                    "description": "1: TXRF_I2C power up",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "RFRX_PBUS_PU": {
+                    "description": "1: RFRX_PBUS power up",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "CKGEN_I2C_PU": {
+                    "description": "1: CKGEN_I2C power up",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "PLL_I2C_PU": {
+                    "description": "power up pll i2c",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RESET_STATE": {
+              "description": "rtc configure register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 12288,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESET_CAUSE_PROCPU": {
+                    "description": "reset cause of PRO CPU",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "RESET_CAUSE_APPCPU": {
+                    "description": "reset cause of APP CPU",
+                    "offset": 6,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "STAT_VECTOR_SEL_APPCPU": {
+                    "description": "APP CPU state vector sel",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "STAT_VECTOR_SEL_PROCPU": {
+                    "description": "PRO CPU state vector sel",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "ALL_RESET_FLAG_PROCPU": {
+                    "description": "PRO CPU reset_flag",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ALL_RESET_FLAG_APPCPU": {
+                    "description": "APP CPU reset flag",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ALL_RESET_FLAG_CLR_PROCPU": {
+                    "description": "clear PRO CPU reset_flag",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "ALL_RESET_FLAG_CLR_APPCPU": {
+                    "description": "clear APP CPU reset flag",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OCD_HALT_ON_RESET_APPCPU": {
+                    "description": "APPCPU OcdHaltOnReset",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "OCD_HALT_ON_RESET_PROCPU": {
+                    "description": "PROCPU OcdHaltOnReset",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "JTAG_RESET_FLAG_PROCPU": {
+                    "description": "configure jtag reset configure",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "JTAG_RESET_FLAG_APPCPU": {
+                    "description": "configure jtag reset configure",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "JTAG_RESET_FLAG_CLR_PROCPU": {
+                    "description": "configure jtag reset configure",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "JTAG_RESET_FLAG_CLR_APPCPU": {
+                    "description": "configure jtag reset configure",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_DRESET_MASK_APPCPU": {
+                    "description": "configure dreset configure",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "RTC_DRESET_MASK_PROCPU": {
+                    "description": "configure dreset configure",
+                    "offset": 25,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WAKEUP_STATE": {
+              "description": "rtc configure register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 393216,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_WAKEUP_ENA": {
+                    "description": "wakeup enable bitmap",
+                    "offset": 15,
+                    "size": 17
+                  }
+                }
+              }
+            },
+            "INT_ENA_RTC": {
+              "description": "rtc configure register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_ENA": {
+                    "description": "enable sleep wakeup interrupt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SLP_REJECT_INT_ENA": {
+                    "description": "enable sleep reject interrupt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RTC_WDT_INT_ENA": {
+                    "description": "enable RTC WDT interrupt",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RTC_BROWN_OUT_INT_ENA": {
+                    "description": "enable brown out interrupt",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "RTC_MAIN_TIMER_INT_ENA": {
+                    "description": "enable RTC main timer interrupt",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "RTC_SWD_INT_ENA": {
+                    "description": "enable super watch dog interrupt",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RTC_XTAL32K_DEAD_INT_ENA": {
+                    "description": "enable xtal32k_dead  interrupt",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RTC_GLITCH_DET_INT_ENA": {
+                    "description": "enbale gitch det interrupt",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "RTC_BBPLL_CAL_INT_ENA": {
+                    "description": "enbale bbpll cal end interrupt",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_RAW_RTC": {
+              "description": "rtc configure register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_RAW": {
+                    "description": "sleep wakeup interrupt raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLP_REJECT_INT_RAW": {
+                    "description": "sleep reject interrupt raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_WDT_INT_RAW": {
+                    "description": "RTC WDT interrupt raw",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_BROWN_OUT_INT_RAW": {
+                    "description": "brown out interrupt raw",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_TIMER_INT_RAW": {
+                    "description": "RTC main timer interrupt raw",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_SWD_INT_RAW": {
+                    "description": "super watch dog interrupt raw",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_XTAL32K_DEAD_INT_RAW": {
+                    "description": "xtal32k dead detection interrupt raw",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_GLITCH_DET_INT_RAW": {
+                    "description": "glitch_det_interrupt_raw",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_BBPLL_CAL_INT_RAW": {
+                    "description": "bbpll cal end interrupt state",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST_RTC": {
+              "description": "rtc configure register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_ST": {
+                    "description": "sleep wakeup interrupt state",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLP_REJECT_INT_ST": {
+                    "description": "sleep reject interrupt state",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_WDT_INT_ST": {
+                    "description": "RTC WDT interrupt state",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_BROWN_OUT_INT_ST": {
+                    "description": "brown out interrupt state",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_TIMER_INT_ST": {
+                    "description": "RTC main timer interrupt state",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_SWD_INT_ST": {
+                    "description": "super watch dog interrupt state",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_XTAL32K_DEAD_INT_ST": {
+                    "description": "xtal32k dead detection interrupt state",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_GLITCH_DET_INT_ST": {
+                    "description": "glitch_det_interrupt state",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_BBPLL_CAL_INT_ST": {
+                    "description": "bbpll cal end interrupt state",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR_RTC": {
+              "description": "rtc configure register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_CLR": {
+                    "description": "Clear sleep wakeup interrupt state",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLP_REJECT_INT_CLR": {
+                    "description": "Clear sleep reject interrupt state",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_WDT_INT_CLR": {
+                    "description": "Clear RTC WDT interrupt state",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BROWN_OUT_INT_CLR": {
+                    "description": "Clear brown out interrupt state",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_MAIN_TIMER_INT_CLR": {
+                    "description": "Clear RTC main timer interrupt state",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_SWD_INT_CLR": {
+                    "description": "Clear super watch dog interrupt state",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_XTAL32K_DEAD_INT_CLR": {
+                    "description": "Clear RTC WDT interrupt state",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_GLITCH_DET_INT_CLR": {
+                    "description": "Clear glitch det interrupt state",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BBPLL_CAL_INT_CLR": {
+                    "description": "clear bbpll cal end interrupt state",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STORE0": {
+              "description": "rtc configure register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH0": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE1": {
+              "description": "rtc configure register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH1": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE2": {
+              "description": "rtc configure register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH2": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE3": {
+              "description": "rtc configure register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH3": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "EXT_XTL_CONF": {
+              "description": "rtc configure register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 420992,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XTAL32K_WDT_EN": {
+                    "description": "xtal 32k watch dog enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "XTAL32K_WDT_CLK_FO": {
+                    "description": "xtal 32k watch dog clock force on",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "XTAL32K_WDT_RESET": {
+                    "description": "xtal 32k watch dog sw reset",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "XTAL32K_EXT_CLK_FO": {
+                    "description": "xtal 32k external xtal clock force on",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "XTAL32K_AUTO_BACKUP": {
+                    "description": "xtal 32k switch to back up clock when xtal is dead",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "XTAL32K_AUTO_RESTART": {
+                    "description": "xtal 32k restart xtal when xtal is dead",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "XTAL32K_AUTO_RETURN": {
+                    "description": "xtal 32k switch back xtal when xtal is restarted",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "XTAL32K_XPD_FORCE": {
+                    "description": "Xtal 32k xpd control by sw or fsm",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "ENCKINIT_XTAL_32K": {
+                    "description": "apply an internal clock to help xtal 32k to start",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DBUF_XTAL_32K": {
+                    "description": "0: single-end buffer 1: differential buffer",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DGM_XTAL_32K": {
+                    "description": "xtal_32k gm control",
+                    "offset": 10,
+                    "size": 3
+                  },
+                  "DRES_XTAL_32K": {
+                    "description": "DRES_XTAL_32K",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "XPD_XTAL_32K": {
+                    "description": "XPD_XTAL_32K",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "DAC_XTAL_32K": {
+                    "description": "DAC_XTAL_32K",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "RTC_WDT_STATE": {
+                    "description": "state of 32k_wdt",
+                    "offset": 20,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "RTC_XTAL32K_GPIO_SEL": {
+                    "description": "XTAL_32K sel. 0: external XTAL_32K",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "XTL_EXT_CTR_LV": {
+                    "description": "0: power down XTAL at high level",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "XTL_EXT_CTR_EN": {
+                    "description": "enable gpio configure xtal power on",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EXT_WAKEUP_CONF": {
+              "description": "rtc configure register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GPIO_WAKEUP_FILTER": {
+                    "description": "enable filter for gpio wakeup event",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLP_REJECT_CONF": {
+              "description": "rtc configure register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SLEEP_REJECT_ENA": {
+                    "description": "sleep reject enable",
+                    "offset": 12,
+                    "size": 18
+                  },
+                  "LIGHT_SLP_REJECT_EN": {
+                    "description": "enable reject for light sleep",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DEEP_SLP_REJECT_EN": {
+                    "description": "enable reject for deep sleep",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_PERIOD_CONF": {
+              "description": "rtc configure register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CPUSEL_CONF": {
+                    "description": "CPU sel option",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "RTC_CPUPERIOD_SEL": {
+                    "description": "CPU clk sel option",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CLK_CONF": {
+              "description": "rtc configure register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 290992664,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EFUSE_CLK_FORCE_GATING": {
+                    "description": "efuse_clk_force_gating",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EFUSE_CLK_FORCE_NOGATING": {
+                    "description": "efuse_clk_force_nogating",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CK8M_DIV_SEL_VLD": {
+                    "description": "used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CK8M_DIV": {
+                    "description": "CK8M_D256_OUT divider. 00: div128",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "ENB_CK8M": {
+                    "description": "disable CK8M and CK8M_D256_OUT",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "ENB_CK8M_DIV": {
+                    "description": "1: CK8M_D256_OUT is actually CK8M",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "DIG_XTAL32K_EN": {
+                    "description": "enable CK_XTAL_32K for digital core (no relationship with RTC core)",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DIG_CLK8M_D256_EN": {
+                    "description": "enable CK8M_D256_OUT for digital core (no relationship with RTC core)",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DIG_CLK8M_EN": {
+                    "description": "enable CK8M for digital core (no relationship with RTC core)",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CK8M_DIV_SEL": {
+                    "description": "divider = reg_ck8m_div_sel + 1",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "XTAL_FORCE_NOGATING": {
+                    "description": "XTAL force no gating during sleep",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "CK8M_FORCE_NOGATING": {
+                    "description": "CK8M force no gating during sleep",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CK8M_DFREQ": {
+                    "description": "CK8M_DFREQ",
+                    "offset": 17,
+                    "size": 8
+                  },
+                  "CK8M_FORCE_PD": {
+                    "description": "CK8M force power down",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CK8M_FORCE_PU": {
+                    "description": "CK8M force power up",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "XTAL_GLOBAL_FORCE_GATING": {
+                    "description": "force enable xtal clk gating",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "XTAL_GLOBAL_FORCE_NOGATING": {
+                    "description": "force bypass xtal clk gating",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FAST_CLK_RTC_SEL": {
+                    "description": "fast_clk_rtc sel. 0: XTAL div 4",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ANA_CLK_RTC_SEL": {
+                    "description": "slelect rtc slow clk",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "SLOW_CLK_CONF": {
+              "description": "rtc configure register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 4194304,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_ANA_CLK_DIV_VLD": {
+                    "description": "used to sync div bus. clear vld before set reg_rtc_ana_clk_div",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "RTC_ANA_CLK_DIV": {
+                    "description": "the clk divider num of RTC_CLK",
+                    "offset": 23,
+                    "size": 8
+                  },
+                  "RTC_SLOW_CLK_NEXT_EDGE": {
+                    "description": "flag rtc_slow_clk_next_edge",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SDIO_CONF": {
+              "description": "rtc configure register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 179355146,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SDIO_TIMER_TARGET": {
+                    "description": "timer count to apply reg_sdio_dcap after sdio power on",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "SDIO_DTHDRV": {
+                    "description": "Tieh = 1 mode drive ability. Initially set to 0 to limit charge current",
+                    "offset": 9,
+                    "size": 2
+                  },
+                  "SDIO_DCAP": {
+                    "description": "ability to prevent LDO from overshoot",
+                    "offset": 11,
+                    "size": 2
+                  },
+                  "SDIO_INITI": {
+                    "description": "add resistor from ldo output to ground. 0: no res",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "SDIO_EN_INITI": {
+                    "description": "0 to set init[1:0]=0",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SDIO_DCURLIM": {
+                    "description": "tune current limit threshold when tieh = 0. About 800mA/(8+d)",
+                    "offset": 16,
+                    "size": 3
+                  },
+                  "SDIO_MODECURLIM": {
+                    "description": "select current limit mode",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SDIO_ENCURLIM": {
+                    "description": "enable current limit",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "SDIO_REG_PD_EN": {
+                    "description": "power down SDIO_REG in sleep. Only active when reg_sdio_force = 0",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SDIO_FORCE": {
+                    "description": "1: use SW option to control SDIO_REG",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "SDIO_TIEH": {
+                    "description": "SW option for SDIO_TIEH. Only active when reg_sdio_force = 1",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "_1P8_READY": {
+                    "description": "read only register for REG1P8_READY",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DREFL_SDIO": {
+                    "description": "SW option for DREFL_SDIO. Only active when reg_sdio_force = 1",
+                    "offset": 25,
+                    "size": 2
+                  },
+                  "DREFM_SDIO": {
+                    "description": "SW option for DREFM_SDIO. Only active when reg_sdio_force = 1",
+                    "offset": 27,
+                    "size": 2
+                  },
+                  "DREFH_SDIO": {
+                    "description": "SW option for DREFH_SDIO. Only active when reg_sdio_force = 1",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "XPD_SDIO": {
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BIAS_CONF": {
+              "description": "rtc configure register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 67584,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DG_VDD_DRV_B_SLP": {
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "DG_VDD_DRV_B_SLP_EN": {
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "BIAS_BUF_IDLE": {
+                    "description": "bias buf when rtc in normal work state",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "BIAS_BUF_WAKE": {
+                    "description": "bias buf when rtc in wakeup state",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BIAS_BUF_DEEP_SLP": {
+                    "description": "bias buf when rtc in sleep state",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "BIAS_BUF_MONITOR": {
+                    "description": "bias buf when rtc in monitor state",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "PD_CUR_DEEP_SLP": {
+                    "description": "xpd cur when rtc in sleep_state",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PD_CUR_MONITOR": {
+                    "description": "xpd cur when rtc in monitor state",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BIAS_SLEEP_DEEP_SLP": {
+                    "description": "bias_sleep when rtc in sleep_state",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "BIAS_SLEEP_MONITOR": {
+                    "description": "bias_sleep when rtc in monitor state",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "DBG_ATTEN_DEEP_SLP": {
+                    "description": "DBG_ATTEN when rtc in sleep state",
+                    "offset": 18,
+                    "size": 4
+                  },
+                  "DBG_ATTEN_MONITOR": {
+                    "description": "DBG_ATTEN when rtc in monitor state",
+                    "offset": 22,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RTC_CNTL": {
+              "description": "rtc configure register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 2684354560,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIG_REG_CAL_EN": {
+                    "description": "software enable digital regulator cali",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SCK_DCAP": {
+                    "description": "SCK_DCAP",
+                    "offset": 14,
+                    "size": 8
+                  },
+                  "DBOOST_FORCE_PD": {
+                    "description": "RTC_DBOOST force power down",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "DBOOST_FORCE_PU": {
+                    "description": "RTC_DBOOST force power up",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "REGULATOR_FORCE_PD": {
+                    "description": "RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "REGULATOR_FORCE_PU": {
+                    "description": "RTC_REG force power up",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PWC": {
+              "description": "rtc configure register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_PAD_FORCE_HOLD": {
+                    "description": "rtc pad force hold",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIG_PWC": {
+              "description": "rtc configure register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 5591056,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "VDD_SPI_PWR_DRV": {
+                    "description": "vdd_spi drv's software value",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "VDD_SPI_PWR_FORCE": {
+                    "description": "vdd_spi drv use software value",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "LSLP_MEM_FORCE_PD": {
+                    "description": "memories in digital core force PD in sleep",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "LSLP_MEM_FORCE_PU": {
+                    "description": "memories in digital core force PU in sleep",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "BT_FORCE_PD": {
+                    "description": "bt force power down",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "BT_FORCE_PU": {
+                    "description": "bt force power up",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DG_PERI_FORCE_PD": {
+                    "description": "digital peri force power down",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "DG_PERI_FORCE_PU": {
+                    "description": "digital peri force power up",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RTC_FASTMEM_FORCE_LPD": {
+                    "description": "fastmemory  retention mode in sleep",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RTC_FASTMEM_FORCE_LPU": {
+                    "description": "fastmemory donlt entry retention mode in sleep",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "WIFI_FORCE_PD": {
+                    "description": "wifi force power down",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "WIFI_FORCE_PU": {
+                    "description": "wifi force power up",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_PD": {
+                    "description": "digital core force power down",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_PU": {
+                    "description": "digital core force power up",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "CPU_TOP_FORCE_PD": {
+                    "description": "cpu core force power down",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "CPU_TOP_FORCE_PU": {
+                    "description": "cpu force power up",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BT_PD_EN": {
+                    "description": "enable power down bt in sleep",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "DG_PERI_PD_EN": {
+                    "description": "enable power down digital peri in sleep",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "CPU_TOP_PD_EN": {
+                    "description": "enable power down cpu in sleep",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "WIFI_PD_EN": {
+                    "description": "enable power down wifi in sleep",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DG_WRAP_PD_EN": {
+                    "description": "enable power down digital wrap in sleep",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIG_ISO": {
+              "description": "rtc configure register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 2860535936,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FORCE_OFF": {
+                    "description": "DIG_ISO force off",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FORCE_ON": {
+                    "description": "DIG_ISO force on",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DG_PAD_AUTOHOLD": {
+                    "description": "read only register to indicate digital pad auto-hold status",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CLR_DG_PAD_AUTOHOLD": {
+                    "description": "wtite only register to clear digital pad auto-hold",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DG_PAD_AUTOHOLD_EN": {
+                    "description": "digital pad enable auto-hold",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DG_PAD_FORCE_NOISO": {
+                    "description": "digital pad force no ISO",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DG_PAD_FORCE_ISO": {
+                    "description": "digital pad force ISO",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "DG_PAD_FORCE_UNHOLD": {
+                    "description": "digital pad force un-hold",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "DG_PAD_FORCE_HOLD": {
+                    "description": "digital pad force hold",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "BT_FORCE_ISO": {
+                    "description": "bt force ISO",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "BT_FORCE_NOISO": {
+                    "description": "bt force no ISO",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "DG_PERI_FORCE_ISO": {
+                    "description": "Digital peri force ISO",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "DG_PERI_FORCE_NOISO": {
+                    "description": "digital peri force no ISO",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "CPU_TOP_FORCE_ISO": {
+                    "description": "cpu force ISO",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "CPU_TOP_FORCE_NOISO": {
+                    "description": "cpu force no ISO",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "WIFI_FORCE_ISO": {
+                    "description": "wifi force ISO",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "WIFI_FORCE_NOISO": {
+                    "description": "wifi force no ISO",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_ISO": {
+                    "description": "digital core force ISO",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DG_WRAP_FORCE_NOISO": {
+                    "description": "digital core force no ISO",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WDTCONFIG0": {
+              "description": "rtc configure register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 78356,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_CHIP_RESET_WIDTH": {
+                    "description": "chip reset siginal pulse width",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "WDT_CHIP_RESET_EN": {
+                    "description": "wdt reset whole chip enable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "WDT_PAUSE_IN_SLP": {
+                    "description": "pause WDT in sleep",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "WDT_APPCPU_RESET_EN": {
+                    "description": "enable WDT reset APP CPU",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "WDT_PROCPU_RESET_EN": {
+                    "description": "enable WDT reset PRO CPU",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "WDT_FLASHBOOT_MOD_EN": {
+                    "description": "enable WDT in flash boot",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WDT_SYS_RESET_LENGTH": {
+                    "description": "system reset counter length",
+                    "offset": 13,
+                    "size": 3
+                  },
+                  "WDT_CPU_RESET_LENGTH": {
+                    "description": "CPU reset counter length",
+                    "offset": 16,
+                    "size": 3
+                  },
+                  "WDT_STG3": {
+                    "description": "1: interrupt stage en",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "WDT_STG2": {
+                    "description": "1: interrupt stage en",
+                    "offset": 22,
+                    "size": 3
+                  },
+                  "WDT_STG1": {
+                    "description": "1: interrupt stage en",
+                    "offset": 25,
+                    "size": 3
+                  },
+                  "WDT_STG0": {
+                    "description": "1: interrupt stage en",
+                    "offset": 28,
+                    "size": 3
+                  },
+                  "WDT_EN": {
+                    "description": "enable rtc wdt",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WDTCONFIG1": {
+              "description": "rtc configure register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 200000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG0_HOLD": {
+                    "description": "the hold time of stage0",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG2": {
+              "description": "rtc configure register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 80000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG1_HOLD": {
+                    "description": "the hold time of stage1",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG3": {
+              "description": "rtc configure register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG2_HOLD": {
+                    "description": "the hold time of stage2",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG4": {
+              "description": "rtc configure register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG3_HOLD": {
+                    "description": "the hold time of stage3",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTFEED": {
+              "description": "rtc configure register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_WDT_FEED": {
+                    "description": "sw feed rtc wdt",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "WDTWPROTECT": {
+              "description": "rtc configure register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_WKEY": {
+                    "description": "the key of rtc wdt",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SWD_CONF": {
+              "description": "rtc configure register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 78643200,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWD_RESET_FLAG": {
+                    "description": "swd reset flag",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SWD_FEED_INT": {
+                    "description": "swd interrupt for feeding",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SWD_BYPASS_RST": {
+                    "description": "Bypass swd rst",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "SWD_SIGNAL_WIDTH": {
+                    "description": "adjust signal width send to swd",
+                    "offset": 18,
+                    "size": 10
+                  },
+                  "SWD_RST_FLAG_CLR": {
+                    "description": "reset swd reset flag",
+                    "offset": 28,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SWD_FEED": {
+                    "description": "Sw feed swd",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SWD_DISABLE": {
+                    "description": "disabel SWD",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SWD_AUTO_FEED_EN": {
+                    "description": "automatically feed swd when int comes",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SWD_WPROTECT": {
+              "description": "rtc configure register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SWD_WKEY": {
+                    "description": "the key of super wdt",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SW_CPU_STALL": {
+              "description": "rtc configure register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SW_STALL_APPCPU_C1": {
+                    "description": "{reg_sw_stall_appcpu_c1[5:0]",
+                    "offset": 20,
+                    "size": 6
+                  },
+                  "SW_STALL_PROCPU_C1": {
+                    "description": "stall cpu by software",
+                    "offset": 26,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "STORE4": {
+              "description": "rtc configure register",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH4": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE5": {
+              "description": "rtc configure register",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH5": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE6": {
+              "description": "rtc configure register",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH6": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "STORE7": {
+              "description": "rtc configure register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_SCRATCH7": {
+                    "description": "reserved register",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "LOW_POWER_ST": {
+              "description": "rtc configure register",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XPD_ROM0": {
+                    "description": "rom0 power down",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "XPD_DIG_DCDC": {
+                    "description": "External DCDC power down",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_PERI_ISO": {
+                    "description": "rtc peripheral iso",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "XPD_RTC_PERI": {
+                    "description": "rtc peripheral power down",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WIFI_ISO": {
+                    "description": "wifi iso",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "XPD_WIFI": {
+                    "description": "wifi wrap power down",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DIG_ISO": {
+                    "description": "digital wrap iso",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "XPD_DIG": {
+                    "description": "digital wrap power down",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_TOUCH_STATE_START": {
+                    "description": "touch should start to work",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_TOUCH_STATE_SWITCH": {
+                    "description": "touch is about to working. Switch rtc main state",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_TOUCH_STATE_SLP": {
+                    "description": "touch is in sleep state",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_TOUCH_STATE_DONE": {
+                    "description": "touch is done",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_COCPU_STATE_START": {
+                    "description": "ulp/cocpu should start to work",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_COCPU_STATE_SWITCH": {
+                    "description": "ulp/cocpu is about to working. Switch rtc main state",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_COCPU_STATE_SLP": {
+                    "description": "ulp/cocpu is in sleep state",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_COCPU_STATE_DONE": {
+                    "description": "ulp/cocpu is done",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_XTAL_ISO": {
+                    "description": "no use any more",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_PLL_ON": {
+                    "description": "rtc main state machine is in states that pll should be running",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_RDY_FOR_WAKEUP": {
+                    "description": "rtc is ready to receive wake up trigger from wake up source",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_WAIT_END": {
+                    "description": "rtc main state machine has been waited for some cycles",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_IN_WAKEUP_STATE": {
+                    "description": "rtc main state machine is in the states of wakeup process",
+                    "offset": 21,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_IN_LOW_POWER_STATE": {
+                    "description": "rtc main state machine is in the states of low power",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_IN_WAIT_8M": {
+                    "description": "rtc main state machine is in wait 8m state",
+                    "offset": 23,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_IN_WAIT_PLL": {
+                    "description": "rtc main state machine is in wait pll state",
+                    "offset": 24,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_IN_WAIT_XTL": {
+                    "description": "rtc main state machine is in wait xtal state",
+                    "offset": 25,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_IN_SLP": {
+                    "description": "rtc main state machine is in sleep state",
+                    "offset": 26,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE_IN_IDLE": {
+                    "description": "rtc main state machine is in idle state",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_MAIN_STATE": {
+                    "description": "rtc main state machine status",
+                    "offset": 28,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DIAG0": {
+              "description": "rtc configure register",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_LOW_POWER_DIAG1": {
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "PAD_HOLD": {
+              "description": "rtc configure register",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_GPIO_PIN0_HOLD": {
+                    "description": "the hold configure of rtc gpio0",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN1_HOLD": {
+                    "description": "the hold configure of rtc gpio1",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN2_HOLD": {
+                    "description": "the hold configure of rtc gpio2",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN3_HOLD": {
+                    "description": "the hold configure of rtc gpio3",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN4_HOLD": {
+                    "description": "the hold configure of rtc gpio4",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN5_HOLD": {
+                    "description": "the hold configure of rtc gpio5",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIG_PAD_HOLD": {
+              "description": "rtc configure register",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIG_PAD_HOLD": {
+                    "description": "the configure of digital pad",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "BROWN_OUT": {
+              "description": "rtc configure register",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 1140785168,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INT_WAIT": {
+                    "description": "brown out interrupt wait cycles",
+                    "offset": 4,
+                    "size": 10
+                  },
+                  "CLOSE_FLASH_ENA": {
+                    "description": "enable close flash when brown out happens",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "PD_RF_ENA": {
+                    "description": "enable power down RF when brown out happens",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RST_WAIT": {
+                    "description": "brown out reset wait cycles",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "RST_ENA": {
+                    "description": "enable brown out reset",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RST_SEL": {
+                    "description": "1:  4-pos reset",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "ANA_RST_EN": {
+                    "description": "brown_out origin reset enable",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "CNT_CLR": {
+                    "description": "clear brown out counter",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "ENA": {
+                    "description": "enable brown out",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "DET": {
+                    "description": "the flag of brown det from analog",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TIME_LOW1": {
+              "description": "rtc configure register",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_TIMER_VALUE1_LOW": {
+                    "description": "RTC timer low 32 bits",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "TIME_HIGH1": {
+              "description": "rtc configure register",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_TIMER_VALUE1_HIGH": {
+                    "description": "RTC timer high 16 bits",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "XTAL32K_CLK_FACTOR": {
+              "description": "rtc configure register",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XTAL32K_CLK_FACTOR": {
+                    "description": "xtal 32k watch dog backup clock factor",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "XTAL32K_CONF": {
+              "description": "rtc configure register",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 267386880,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XTAL32K_RETURN_WAIT": {
+                    "description": "cycles to wait to return noral xtal 32k",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "XTAL32K_RESTART_WAIT": {
+                    "description": "cycles to wait to repower on xtal 32k",
+                    "offset": 4,
+                    "size": 16
+                  },
+                  "XTAL32K_WDT_TIMEOUT": {
+                    "description": "If no clock detected for this amount of time",
+                    "offset": 20,
+                    "size": 8
+                  },
+                  "XTAL32K_STABLE_THRES": {
+                    "description": "if restarted xtal32k period is smaller than this",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "USB_CONF": {
+              "description": "rtc configure register",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IO_MUX_RESET_DISABLE": {
+                    "description": "disable io_mux reset",
+                    "offset": 18,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLP_REJECT_CAUSE": {
+              "description": "RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REJECT_CAUSE": {
+                    "description": "sleep reject cause",
+                    "offset": 0,
+                    "size": 18,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OPTION1": {
+              "description": "rtc configure register",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FORCE_DOWNLOAD_BOOT": {
+                    "description": "force chip entry download mode",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLP_WAKEUP_CAUSE": {
+              "description": "RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WAKEUP_CAUSE": {
+                    "description": "sleep wakeup cause",
+                    "offset": 0,
+                    "size": 17,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ULP_CP_TIMER_1": {
+              "description": "rtc configure register",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 51200,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ULP_CP_TIMER_SLP_CYCLE": {
+                    "description": "sleep cycles for ULP-coprocessor timer",
+                    "offset": 8,
+                    "size": 24
+                  }
+                }
+              }
+            },
+            "INT_ENA_RTC_W1TS": {
+              "description": "rtc configure register",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_ENA_W1TS": {
+                    "description": "enable sleep wakeup interrupt",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLP_REJECT_INT_ENA_W1TS": {
+                    "description": "enable sleep reject interrupt",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_WDT_INT_ENA_W1TS": {
+                    "description": "enable RTC WDT interrupt",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BROWN_OUT_INT_ENA_W1TS": {
+                    "description": "enable brown out interrupt",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_MAIN_TIMER_INT_ENA_W1TS": {
+                    "description": "enable RTC main timer interrupt",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_SWD_INT_ENA_W1TS": {
+                    "description": "enable super watch dog interrupt",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_XTAL32K_DEAD_INT_ENA_W1TS": {
+                    "description": "enable xtal32k_dead  interrupt",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_GLITCH_DET_INT_ENA_W1TS": {
+                    "description": "enbale gitch det interrupt",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BBPLL_CAL_INT_ENA_W1TS": {
+                    "description": "enbale bbpll cal interrupt",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA_RTC_W1TC": {
+              "description": "rtc configure register",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLP_WAKEUP_INT_ENA_W1TC": {
+                    "description": "clear sleep wakeup interrupt enable",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLP_REJECT_INT_ENA_W1TC": {
+                    "description": "clear sleep reject interrupt enable",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_WDT_INT_ENA_W1TC": {
+                    "description": "clear RTC WDT interrupt enable",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BROWN_OUT_INT_ENA_W1TC": {
+                    "description": "clear brown out interrupt enable",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_MAIN_TIMER_INT_ENA_W1TC": {
+                    "description": "Clear RTC main timer interrupt enable",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_SWD_INT_ENA_W1TC": {
+                    "description": "clear super watch dog interrupt enable",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_XTAL32K_DEAD_INT_ENA_W1TC": {
+                    "description": "clear xtal32k_dead  interrupt enable",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_GLITCH_DET_INT_ENA_W1TC": {
+                    "description": "clear gitch det interrupt enable",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RTC_BBPLL_CAL_INT_ENA_W1TC": {
+                    "description": "clear bbpll cal interrupt enable",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "RETENTION_CTRL": {
+              "description": "rtc configure register",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 2697986048,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RETENTION_CLK_SEL": {
+                    "description": "Retention clk sel",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RETENTION_DONE_WAIT": {
+                    "description": "Retention done wait time",
+                    "offset": 19,
+                    "size": 3
+                  },
+                  "RETENTION_CLKOFF_WAIT": {
+                    "description": "Retention clkoff wait time",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "RETENTION_EN": {
+                    "description": "enable cpu retention when light sleep",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RETENTION_WAIT": {
+                    "description": "wait cycles for rention operation",
+                    "offset": 27,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "FIB_SEL": {
+              "description": "rtc configure register",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 7,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_FIB_SEL": {
+                    "description": "select use analog fib signal",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "GPIO_WAKEUP": {
+              "description": "rtc configure register",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_GPIO_WAKEUP_STATUS": {
+                    "description": "rtc gpio wakeup flag",
+                    "offset": 0,
+                    "size": 6,
+                    "access": "read-only"
+                  },
+                  "RTC_GPIO_WAKEUP_STATUS_CLR": {
+                    "description": "clear rtc gpio wakeup flag",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN_CLK_GATE": {
+                    "description": "enable rtc io clk gate",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN5_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 8,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN4_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 11,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN3_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 14,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN2_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 17,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN1_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 20,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN0_INT_TYPE": {
+                    "description": "configure gpio wakeup type",
+                    "offset": 23,
+                    "size": 3
+                  },
+                  "RTC_GPIO_PIN5_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio5",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN4_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio4",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN3_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio3",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN2_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio2",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN1_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio1",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN0_WAKEUP_ENABLE": {
+                    "description": "enable wakeup from rtc gpio0",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DBG_SEL": {
+              "description": "rtc configure register",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_DEBUG_12M_NO_GATING": {
+                    "description": "use for debug",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RTC_DEBUG_BIT_SEL": {
+                    "description": "use for debug",
+                    "offset": 2,
+                    "size": 5
+                  },
+                  "RTC_DEBUG_SEL0": {
+                    "description": "use for debug",
+                    "offset": 7,
+                    "size": 5
+                  },
+                  "RTC_DEBUG_SEL1": {
+                    "description": "use for debug",
+                    "offset": 12,
+                    "size": 5
+                  },
+                  "RTC_DEBUG_SEL2": {
+                    "description": "use for debug",
+                    "offset": 17,
+                    "size": 5
+                  },
+                  "RTC_DEBUG_SEL3": {
+                    "description": "use for debug",
+                    "offset": 22,
+                    "size": 5
+                  },
+                  "RTC_DEBUG_SEL4": {
+                    "description": "use for debug",
+                    "offset": 27,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "DBG_MAP": {
+              "description": "rtc configure register",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_GPIO_PIN5_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN4_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN3_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN2_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN1_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN0_MUX_SEL": {
+                    "description": "use for debug",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RTC_GPIO_PIN5_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 8,
+                    "size": 4
+                  },
+                  "RTC_GPIO_PIN4_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 12,
+                    "size": 4
+                  },
+                  "RTC_GPIO_PIN3_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 16,
+                    "size": 4
+                  },
+                  "RTC_GPIO_PIN2_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 20,
+                    "size": 4
+                  },
+                  "RTC_GPIO_PIN1_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 24,
+                    "size": 4
+                  },
+                  "RTC_GPIO_PIN0_FUN_SEL": {
+                    "description": "use for debug",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "SENSOR_CTRL": {
+              "description": "rtc configure register",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SAR2_PWDET_CCT": {
+                    "description": "reg_sar2_pwdet_cct",
+                    "offset": 27,
+                    "size": 3
+                  },
+                  "FORCE_XPD_SAR": {
+                    "description": "force power up SAR",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DBG_SAR_SEL": {
+              "description": "rtc configure register",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SAR_DEBUG_SEL": {
+                    "description": "use for debug",
+                    "offset": 27,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "PG_CTRL": {
+              "description": "rtc configure register",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POWER_GLITCH_DSENSE": {
+                    "description": "power glitch desense",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "POWER_GLITCH_FORCE_PD": {
+                    "description": "force disable power glitch",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "POWER_GLITCH_FORCE_PU": {
+                    "description": "force enable power glitch",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "POWER_GLITCH_EFUSE_SEL": {
+                    "description": "use efuse value control power glitch enable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "POWER_GLITCH_EN": {
+                    "description": "enable power glitch",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "rtc configure register",
+              "offset": 508,
+              "size": 32,
+              "reset_value": 33583728,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CNTL_DATE": {
+                    "description": "verision",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SENSITIVE": {
+        "description": "Sensitive",
+        "children": {
+          "registers": {
+            "ROM_TABLE_LOCK": {
+              "description": "SENSITIVE_ROM_TABLE_LOCK_REG",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ROM_TABLE_LOCK": {
+                    "description": "rom_table_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ROM_TABLE": {
+              "description": "SENSITIVE_ROM_TABLE_REG",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ROM_TABLE": {
+                    "description": "rom_table",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "PRIVILEGE_MODE_SEL_LOCK": {
+              "description": "SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRIVILEGE_MODE_SEL_LOCK": {
+                    "description": "privilege_mode_sel_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PRIVILEGE_MODE_SEL": {
+              "description": "SENSITIVE_PRIVILEGE_MODE_SEL_REG",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRIVILEGE_MODE_SEL": {
+                    "description": "privilege_mode_sel",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB_PERIPHERAL_ACCESS_0": {
+              "description": "SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_PERIPHERAL_ACCESS_LOCK": {
+                    "description": "apb_peripheral_access_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "APB_PERIPHERAL_ACCESS_1": {
+              "description": "SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_PERIPHERAL_ACCESS_SPLIT_BURST": {
+                    "description": "apb_peripheral_access_split_burst",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTERNAL_SRAM_USAGE_0": {
+              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_0_REG",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERNAL_SRAM_USAGE_LOCK": {
+                    "description": "internal_sram_usage_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTERNAL_SRAM_USAGE_1": {
+              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_1_REG",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 15,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERNAL_SRAM_USAGE_CPU_CACHE": {
+                    "description": "internal_sram_usage_cpu_cache",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "INTERNAL_SRAM_USAGE_CPU_SRAM": {
+                    "description": "internal_sram_usage_cpu_sram",
+                    "offset": 1,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "INTERNAL_SRAM_USAGE_3": {
+              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_3_REG",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM": {
+                    "description": "internal_sram_usage_mac_dump_sram",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "INTERNAL_SRAM_ALLOC_MAC_DUMP": {
+                    "description": "internal_sram_alloc_mac_dump",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INTERNAL_SRAM_USAGE_4": {
+              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_4_REG",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERNAL_SRAM_USAGE_LOG_SRAM": {
+                    "description": "internal_sram_usage_log_sram",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_TAG_ACCESS_0": {
+              "description": "SENSITIVE_CACHE_TAG_ACCESS_0_REG",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_TAG_ACCESS_LOCK": {
+                    "description": "cache_tag_access_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_TAG_ACCESS_1": {
+              "description": "SENSITIVE_CACHE_TAG_ACCESS_1_REG",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 15,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRO_I_TAG_RD_ACS": {
+                    "description": "pro_i_tag_rd_acs",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PRO_I_TAG_WR_ACS": {
+                    "description": "pro_i_tag_wr_acs",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PRO_D_TAG_RD_ACS": {
+                    "description": "pro_d_tag_rd_acs",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "PRO_D_TAG_WR_ACS": {
+                    "description": "pro_d_tag_wr_acs",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_ACCESS_0": {
+              "description": "SENSITIVE_CACHE_MMU_ACCESS_0_REG",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_MMU_ACCESS_LOCK": {
+                    "description": "cache_mmu_access_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_MMU_ACCESS_1": {
+              "description": "SENSITIVE_CACHE_MMU_ACCESS_1_REG",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRO_MMU_RD_ACS": {
+                    "description": "pro_mmu_rd_acs",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PRO_MMU_WR_ACS": {
+                    "description": "pro_mmu_wr_acs",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_SPI2_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_spi2_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_SPI2_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_I2S0_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_I2S0_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_MAC_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_mac_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_MAC_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_backup_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_LC_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_lc_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_LC_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_AES_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_aes_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_AES_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_SHA_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_sha_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_SHA_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 1044735,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_PMS_MONITOR_0": {
+              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_PMS_MONITOR_LOCK": {
+                    "description": "dma_apbperi_pms_monitor_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_PMS_MONITOR_1": {
+              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR": {
+                    "description": "dma_apbperi_pms_monitor_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_EN": {
+                    "description": "dma_apbperi_pms_monitor_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_PMS_MONITOR_2": {
+              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR": {
+                    "description": "dma_apbperi_pms_monitor_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
+                    "description": "dma_apbperi_pms_monitor_violate_status_world",
+                    "offset": 1,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
+                    "description": "dma_apbperi_pms_monitor_violate_status_addr",
+                    "offset": 3,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DMA_APBPERI_PMS_MONITOR_3": {
+              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR": {
+                    "description": "dma_apbperi_pms_monitor_violate_status_wr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN": {
+                    "description": "dma_apbperi_pms_monitor_violate_status_byteen",
+                    "offset": 1,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK": {
+                    "description": "core_x_iram0_dram0_dma_split_line_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0": {
+                    "description": "core_x_iram0_dram0_dma_sram_category_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1": {
+                    "description": "core_x_iram0_dram0_dma_sram_category_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2": {
+                    "description": "core_x_iram0_dram0_dma_sram_category_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR": {
+                    "description": "core_x_iram0_dram0_dma_sram_splitaddr",
+                    "offset": 14,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0": {
+                    "description": "core_x_iram0_sram_line_0_category_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1": {
+                    "description": "core_x_iram0_sram_line_0_category_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2": {
+                    "description": "core_x_iram0_sram_line_0_category_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR": {
+                    "description": "core_x_iram0_sram_line_0_splitaddr",
+                    "offset": 14,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0": {
+                    "description": "core_x_iram0_sram_line_1_category_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1": {
+                    "description": "core_x_iram0_sram_line_1_category_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2": {
+                    "description": "core_x_iram0_sram_line_1_category_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR": {
+                    "description": "core_x_iram0_sram_line_1_splitaddr",
+                    "offset": 14,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0": {
+                    "description": "core_x_dram0_dma_sram_line_0_category_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1": {
+                    "description": "core_x_dram0_dma_sram_line_0_category_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2": {
+                    "description": "core_x_dram0_dma_sram_line_0_category_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR": {
+                    "description": "core_x_dram0_dma_sram_line_0_splitaddr",
+                    "offset": 14,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5": {
+              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0": {
+                    "description": "core_x_dram0_dma_sram_line_1_category_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1": {
+                    "description": "core_x_dram0_dma_sram_line_1_category_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2": {
+                    "description": "core_x_dram0_dma_sram_line_1_category_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR": {
+                    "description": "core_x_dram0_dma_sram_line_1_splitaddr",
+                    "offset": 14,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_LOCK": {
+                    "description": "core_x_iram0_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 1867775,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_0",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_1",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_2",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_3",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS": {
+                    "description": "core_x_iram0_pms_constrain_rom_world_1_pms",
+                    "offset": 18,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "CORE_X_IRAM0_PMS_CONSTRAIN_2": {
+              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 1867775,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_1",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_2",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_3",
+                    "offset": 9,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0": {
+                    "description": "core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0",
+                    "offset": 12,
+                    "size": 3
+                  },
+                  "CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS": {
+                    "description": "core_x_iram0_pms_constrain_rom_world_0_pms",
+                    "offset": 18,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_PMS_MONITOR_0": {
+              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_PMS_MONITOR_LOCK": {
+                    "description": "core_0_iram0_pms_monitor_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_PMS_MONITOR_1": {
+              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR": {
+                    "description": "core_0_iram0_pms_monitor_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN": {
+                    "description": "core_0_iram0_pms_monitor_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_IRAM0_PMS_MONITOR_2": {
+              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR": {
+                    "description": "core_0_iram0_pms_monitor_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR": {
+                    "description": "core_0_iram0_pms_monitor_violate_status_wr",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE": {
+                    "description": "core_0_iram0_pms_monitor_violate_status_loadstore",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
+                    "description": "core_0_iram0_pms_monitor_violate_status_world",
+                    "offset": 3,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
+                    "description": "core_0_iram0_pms_monitor_violate_status_addr",
+                    "offset": 5,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_X_DRAM0_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_LOCK": {
+                    "description": "core_x_dram0_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_X_DRAM0_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 252702975,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_0",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_2",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
+                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_3",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS": {
+                    "description": "core_x_dram0_pms_constrain_rom_world_0_pms",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS": {
+                    "description": "core_x_dram0_pms_constrain_rom_world_1_pms",
+                    "offset": 26,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_PMS_MONITOR_0": {
+              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_PMS_MONITOR_LOCK": {
+                    "description": "core_0_dram0_pms_monitor_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_PMS_MONITOR_1": {
+              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR": {
+                    "description": "core_0_dram0_pms_monitor_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN": {
+                    "description": "core_0_dram0_pms_monitor_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_PMS_MONITOR_2": {
+              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR": {
+                    "description": "core_0_dram0_pms_monitor_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK": {
+                    "description": "core_0_dram0_pms_monitor_violate_status_lock",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
+                    "description": "core_0_dram0_pms_monitor_violate_status_world",
+                    "offset": 2,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
+                    "description": "core_0_dram0_pms_monitor_violate_status_addr",
+                    "offset": 4,
+                    "size": 24,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_DRAM0_PMS_MONITOR_3": {
+              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR": {
+                    "description": "core_0_dram0_pms_monitor_violate_status_wr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN": {
+                    "description": "core_0_dram0_pms_monitor_violate_status_byteen",
+                    "offset": 1,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG",
+              "offset": 216,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_LOCK": {
+                    "description": "core_0_pif_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 3473932287,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART": {
+                    "description": "core_0_pif_pms_constrain_world_0_uart",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1": {
+                    "description": "core_0_pif_pms_constrain_world_0_g0spi_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0": {
+                    "description": "core_0_pif_pms_constrain_world_0_g0spi_0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO": {
+                    "description": "core_0_pif_pms_constrain_world_0_gpio",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2": {
+                    "description": "core_0_pif_pms_constrain_world_0_fe2",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE": {
+                    "description": "core_0_pif_pms_constrain_world_0_fe",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER": {
+                    "description": "core_0_pif_pms_constrain_world_0_timer",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC": {
+                    "description": "core_0_pif_pms_constrain_world_0_rtc",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX": {
+                    "description": "core_0_pif_pms_constrain_world_0_io_mux",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG": {
+                    "description": "core_0_pif_pms_constrain_world_0_wdg",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC": {
+                    "description": "core_0_pif_pms_constrain_world_0_misc",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C": {
+                    "description": "core_0_pif_pms_constrain_world_0_i2c",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1": {
+                    "description": "core_0_pif_pms_constrain_world_0_uart1",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_2": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 4240641267,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT": {
+                    "description": "core_0_pif_pms_constrain_world_0_bt",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0": {
+                    "description": "core_0_pif_pms_constrain_world_0_i2c_ext0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0": {
+                    "description": "core_0_pif_pms_constrain_world_0_uhci0",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT": {
+                    "description": "core_0_pif_pms_constrain_world_0_rmt",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC": {
+                    "description": "core_0_pif_pms_constrain_world_0_ledc",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB": {
+                    "description": "core_0_pif_pms_constrain_world_0_bb",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP": {
+                    "description": "core_0_pif_pms_constrain_world_0_timergroup",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1": {
+                    "description": "core_0_pif_pms_constrain_world_0_timergroup1",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER": {
+                    "description": "core_0_pif_pms_constrain_world_0_systimer",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_3": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 1019268147,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2": {
+                    "description": "core_0_pif_pms_constrain_world_0_spi_2",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL": {
+                    "description": "core_0_pif_pms_constrain_world_0_apb_ctrl",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN": {
+                    "description": "core_0_pif_pms_constrain_world_0_can",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1": {
+                    "description": "core_0_pif_pms_constrain_world_0_i2s1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT": {
+                    "description": "core_0_pif_pms_constrain_world_0_rwbt",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC": {
+                    "description": "core_0_pif_pms_constrain_world_0_wifimac",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR": {
+                    "description": "core_0_pif_pms_constrain_world_0_pwr",
+                    "offset": 28,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_4": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 4294964220,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP": {
+                    "description": "core_0_pif_pms_constrain_world_0_usb_wrap",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI": {
+                    "description": "core_0_pif_pms_constrain_world_0_crypto_peri",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA": {
+                    "description": "core_0_pif_pms_constrain_world_0_crypto_dma",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC": {
+                    "description": "core_0_pif_pms_constrain_world_0_apb_adc",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR": {
+                    "description": "core_0_pif_pms_constrain_world_0_bt_pwr",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE": {
+                    "description": "core_0_pif_pms_constrain_world_0_usb_device",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM": {
+                    "description": "core_0_pif_pms_constrain_world_0_system",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE": {
+                    "description": "core_0_pif_pms_constrain_world_0_sensitive",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT": {
+                    "description": "core_0_pif_pms_constrain_world_0_interrupt",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY": {
+                    "description": "core_0_pif_pms_constrain_world_0_dma_copy",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG": {
+                    "description": "core_0_pif_pms_constrain_world_0_cache_config",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD": {
+                    "description": "core_0_pif_pms_constrain_world_0_ad",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO": {
+                    "description": "core_0_pif_pms_constrain_world_0_dio",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER": {
+                    "description": "core_0_pif_pms_constrain_world_0_world_controller",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_5": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG",
+              "offset": 236,
+              "size": 32,
+              "reset_value": 3473932287,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART": {
+                    "description": "core_0_pif_pms_constrain_world_1_uart",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1": {
+                    "description": "core_0_pif_pms_constrain_world_1_g0spi_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0": {
+                    "description": "core_0_pif_pms_constrain_world_1_g0spi_0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO": {
+                    "description": "core_0_pif_pms_constrain_world_1_gpio",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2": {
+                    "description": "core_0_pif_pms_constrain_world_1_fe2",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE": {
+                    "description": "core_0_pif_pms_constrain_world_1_fe",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER": {
+                    "description": "core_0_pif_pms_constrain_world_1_timer",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC": {
+                    "description": "core_0_pif_pms_constrain_world_1_rtc",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX": {
+                    "description": "core_0_pif_pms_constrain_world_1_io_mux",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG": {
+                    "description": "core_0_pif_pms_constrain_world_1_wdg",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC": {
+                    "description": "core_0_pif_pms_constrain_world_1_misc",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C": {
+                    "description": "core_0_pif_pms_constrain_world_1_i2c",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1": {
+                    "description": "core_0_pif_pms_constrain_world_1_uart1",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_6": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 4240641267,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT": {
+                    "description": "core_0_pif_pms_constrain_world_1_bt",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0": {
+                    "description": "core_0_pif_pms_constrain_world_1_i2c_ext0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0": {
+                    "description": "core_0_pif_pms_constrain_world_1_uhci0",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT": {
+                    "description": "core_0_pif_pms_constrain_world_1_rmt",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC": {
+                    "description": "core_0_pif_pms_constrain_world_1_ledc",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB": {
+                    "description": "core_0_pif_pms_constrain_world_1_bb",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP": {
+                    "description": "core_0_pif_pms_constrain_world_1_timergroup",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1": {
+                    "description": "core_0_pif_pms_constrain_world_1_timergroup1",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER": {
+                    "description": "core_0_pif_pms_constrain_world_1_systimer",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_7": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG",
+              "offset": 244,
+              "size": 32,
+              "reset_value": 1019268147,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2": {
+                    "description": "core_0_pif_pms_constrain_world_1_spi_2",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL": {
+                    "description": "core_0_pif_pms_constrain_world_1_apb_ctrl",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN": {
+                    "description": "core_0_pif_pms_constrain_world_1_can",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1": {
+                    "description": "core_0_pif_pms_constrain_world_1_i2s1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT": {
+                    "description": "core_0_pif_pms_constrain_world_1_rwbt",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC": {
+                    "description": "core_0_pif_pms_constrain_world_1_wifimac",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR": {
+                    "description": "core_0_pif_pms_constrain_world_1_pwr",
+                    "offset": 28,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_8": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 4294964220,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP": {
+                    "description": "core_0_pif_pms_constrain_world_1_usb_wrap",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI": {
+                    "description": "core_0_pif_pms_constrain_world_1_crypto_peri",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA": {
+                    "description": "core_0_pif_pms_constrain_world_1_crypto_dma",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC": {
+                    "description": "core_0_pif_pms_constrain_world_1_apb_adc",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR": {
+                    "description": "core_0_pif_pms_constrain_world_1_bt_pwr",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE": {
+                    "description": "core_0_pif_pms_constrain_world_1_usb_device",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM": {
+                    "description": "core_0_pif_pms_constrain_world_1_system",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE": {
+                    "description": "core_0_pif_pms_constrain_world_1_sensitive",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT": {
+                    "description": "core_0_pif_pms_constrain_world_1_interrupt",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY": {
+                    "description": "core_0_pif_pms_constrain_world_1_dma_copy",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG": {
+                    "description": "core_0_pif_pms_constrain_world_1_cache_config",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD": {
+                    "description": "core_0_pif_pms_constrain_world_1_ad",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO": {
+                    "description": "core_0_pif_pms_constrain_world_1_dio",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER": {
+                    "description": "core_0_pif_pms_constrain_world_1_world_controller",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_9": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 4194303,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_spltaddr_world_0",
+                    "offset": 0,
+                    "size": 11
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_spltaddr_world_1",
+                    "offset": 11,
+                    "size": 11
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_CONSTRAIN_10": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG",
+              "offset": 256,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_world_0_l",
+                    "offset": 0,
+                    "size": 3
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_world_0_h",
+                    "offset": 3,
+                    "size": 3
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_world_1_l",
+                    "offset": 6,
+                    "size": 3
+                  },
+                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H": {
+                    "description": "core_0_pif_pms_constrain_rtcfast_world_1_h",
+                    "offset": 9,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_0_REG",
+              "offset": 260,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_LOCK": {
+                    "description": "region_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_1_REG",
+              "offset": 264,
+              "size": 32,
+              "reset_value": 16383,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_0": {
+                    "description": "region_pms_constrain_world_0_area_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_1": {
+                    "description": "region_pms_constrain_world_0_area_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_2": {
+                    "description": "region_pms_constrain_world_0_area_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_3": {
+                    "description": "region_pms_constrain_world_0_area_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_4": {
+                    "description": "region_pms_constrain_world_0_area_4",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_5": {
+                    "description": "region_pms_constrain_world_0_area_5",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_6": {
+                    "description": "region_pms_constrain_world_0_area_6",
+                    "offset": 12,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_2": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_2_REG",
+              "offset": 268,
+              "size": 32,
+              "reset_value": 16383,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_0": {
+                    "description": "region_pms_constrain_world_1_area_0",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_1": {
+                    "description": "region_pms_constrain_world_1_area_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_2": {
+                    "description": "region_pms_constrain_world_1_area_2",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_3": {
+                    "description": "region_pms_constrain_world_1_area_3",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_4": {
+                    "description": "region_pms_constrain_world_1_area_4",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_5": {
+                    "description": "region_pms_constrain_world_1_area_5",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_6": {
+                    "description": "region_pms_constrain_world_1_area_6",
+                    "offset": 12,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_3": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_3_REG",
+              "offset": 272,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_0": {
+                    "description": "region_pms_constrain_addr_0",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_4": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_4_REG",
+              "offset": 276,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_1": {
+                    "description": "region_pms_constrain_addr_1",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_5": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_5_REG",
+              "offset": 280,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_2": {
+                    "description": "region_pms_constrain_addr_2",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_6": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_6_REG",
+              "offset": 284,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_3": {
+                    "description": "region_pms_constrain_addr_3",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_7": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_7_REG",
+              "offset": 288,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_4": {
+                    "description": "region_pms_constrain_addr_4",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_8": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_8_REG",
+              "offset": 292,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_5": {
+                    "description": "region_pms_constrain_addr_5",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_9": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_9_REG",
+              "offset": 296,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_6": {
+                    "description": "region_pms_constrain_addr_6",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "REGION_PMS_CONSTRAIN_10": {
+              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_10_REG",
+              "offset": 300,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REGION_PMS_CONSTRAIN_ADDR_7": {
+                    "description": "region_pms_constrain_addr_7",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_0": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG",
+              "offset": 304,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_LOCK": {
+                    "description": "core_0_pif_pms_monitor_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_1": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG",
+              "offset": 308,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR": {
+                    "description": "core_0_pif_pms_monitor_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_EN": {
+                    "description": "core_0_pif_pms_monitor_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_2": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG",
+              "offset": 312,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR": {
+                    "description": "core_0_pif_pms_monitor_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0": {
+                    "description": "core_0_pif_pms_monitor_violate_status_hport_0",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE": {
+                    "description": "core_0_pif_pms_monitor_violate_status_hsize",
+                    "offset": 2,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE": {
+                    "description": "core_0_pif_pms_monitor_violate_status_hwrite",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD": {
+                    "description": "core_0_pif_pms_monitor_violate_status_hworld",
+                    "offset": 6,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_3": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG",
+              "offset": 316,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR": {
+                    "description": "core_0_pif_pms_monitor_violate_status_haddr",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_4": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG",
+              "offset": 320,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_5": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG",
+              "offset": 324,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_status_hsize",
+                    "offset": 1,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_status_hworld",
+                    "offset": 3,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CORE_0_PIF_PMS_MONITOR_6": {
+              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG",
+              "offset": 328,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR": {
+                    "description": "core_0_pif_pms_monitor_nonword_violate_status_haddr",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_CONSTRAIN_0": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG",
+              "offset": 332,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_CONSTRAIN_LOCK": {
+                    "description": "backup_bus_pms_constrain_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_CONSTRAIN_1": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG",
+              "offset": 336,
+              "size": 32,
+              "reset_value": 3473932287,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_CONSTRAIN_UART": {
+                    "description": "backup_bus_pms_constrain_uart",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1": {
+                    "description": "backup_bus_pms_constrain_g0spi_1",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0": {
+                    "description": "backup_bus_pms_constrain_g0spi_0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_GPIO": {
+                    "description": "backup_bus_pms_constrain_gpio",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_FE2": {
+                    "description": "backup_bus_pms_constrain_fe2",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_FE": {
+                    "description": "backup_bus_pms_constrain_fe",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_TIMER": {
+                    "description": "backup_bus_pms_constrain_timer",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_RTC": {
+                    "description": "backup_bus_pms_constrain_rtc",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_IO_MUX": {
+                    "description": "backup_bus_pms_constrain_io_mux",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_WDG": {
+                    "description": "backup_bus_pms_constrain_wdg",
+                    "offset": 18,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_MISC": {
+                    "description": "backup_bus_pms_constrain_misc",
+                    "offset": 24,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_I2C": {
+                    "description": "backup_bus_pms_constrain_i2c",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_UART1": {
+                    "description": "backup_bus_pms_constrain_uart1",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_CONSTRAIN_2": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG",
+              "offset": 340,
+              "size": 32,
+              "reset_value": 4240641267,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_CONSTRAIN_BT": {
+                    "description": "backup_bus_pms_constrain_bt",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0": {
+                    "description": "backup_bus_pms_constrain_i2c_ext0",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_UHCI0": {
+                    "description": "backup_bus_pms_constrain_uhci0",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_RMT": {
+                    "description": "backup_bus_pms_constrain_rmt",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_LEDC": {
+                    "description": "backup_bus_pms_constrain_ledc",
+                    "offset": 16,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_BB": {
+                    "description": "backup_bus_pms_constrain_bb",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP": {
+                    "description": "backup_bus_pms_constrain_timergroup",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1": {
+                    "description": "backup_bus_pms_constrain_timergroup1",
+                    "offset": 28,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER": {
+                    "description": "backup_bus_pms_constrain_systimer",
+                    "offset": 30,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_CONSTRAIN_3": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG",
+              "offset": 344,
+              "size": 32,
+              "reset_value": 1019268147,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_CONSTRAIN_SPI_2": {
+                    "description": "backup_bus_pms_constrain_spi_2",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL": {
+                    "description": "backup_bus_pms_constrain_apb_ctrl",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_CAN": {
+                    "description": "backup_bus_pms_constrain_can",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_I2S1": {
+                    "description": "backup_bus_pms_constrain_i2s1",
+                    "offset": 14,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_RWBT": {
+                    "description": "backup_bus_pms_constrain_rwbt",
+                    "offset": 22,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC": {
+                    "description": "backup_bus_pms_constrain_wifimac",
+                    "offset": 26,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_PWR": {
+                    "description": "backup_bus_pms_constrain_pwr",
+                    "offset": 28,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_CONSTRAIN_4": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG",
+              "offset": 348,
+              "size": 32,
+              "reset_value": 62460,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP": {
+                    "description": "backup_bus_pms_constrain_usb_wrap",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI": {
+                    "description": "backup_bus_pms_constrain_crypto_peri",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA": {
+                    "description": "backup_bus_pms_constrain_crypto_dma",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_APB_ADC": {
+                    "description": "backup_bus_pms_constrain_apb_adc",
+                    "offset": 8,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_BT_PWR": {
+                    "description": "backup_bus_pms_constrain_bt_pwr",
+                    "offset": 12,
+                    "size": 2
+                  },
+                  "BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE": {
+                    "description": "backup_bus_pms_constrain_usb_device",
+                    "offset": 14,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_MONITOR_0": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG",
+              "offset": 352,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_MONITOR_LOCK": {
+                    "description": "backup_bus_pms_monitor_lock",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_MONITOR_1": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG",
+              "offset": 356,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR": {
+                    "description": "backup_bus_pms_monitor_violate_clr",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_EN": {
+                    "description": "backup_bus_pms_monitor_violate_en",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_MONITOR_2": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG",
+              "offset": 360,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR": {
+                    "description": "backup_bus_pms_monitor_violate_intr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS": {
+                    "description": "backup_bus_pms_monitor_violate_status_htrans",
+                    "offset": 1,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE": {
+                    "description": "backup_bus_pms_monitor_violate_status_hsize",
+                    "offset": 3,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE": {
+                    "description": "backup_bus_pms_monitor_violate_status_hwrite",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "BACKUP_BUS_PMS_MONITOR_3": {
+              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG",
+              "offset": 364,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR": {
+                    "description": "backup_bus_pms_monitor_violate_haddr",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "SENSITIVE_CLOCK_GATE_REG",
+              "offset": 368,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "clk_en",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "SENSITIVE_DATE_REG",
+              "offset": 4092,
+              "size": 32,
+              "reset_value": 33620480,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "reg_date",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SHA": {
+        "description": "SHA (Secure Hash Algorithm) Accelerator",
+        "children": {
+          "registers": {
+            "MODE": {
+              "description": "Initial configuration register.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MODE": {
+                    "description": "Sha mode.",
+                    "offset": 0,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "T_STRING": {
+              "description": "SHA 512/t configuration register 0.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T_STRING": {
+                    "description": "Sha t_string (used if and only if mode == SHA_512/t).",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "T_LENGTH": {
+              "description": "SHA 512/t configuration register 1.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T_LENGTH": {
+                    "description": "Sha t_length (used if and only if mode == SHA_512/t).",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "DMA_BLOCK_NUM": {
+              "description": "DMA configuration register 0.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_BLOCK_NUM": {
+                    "description": "Dma-sha block number.",
+                    "offset": 0,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "START": {
+              "description": "Typical SHA configuration register 0.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "START": {
+                    "description": "Reserved.",
+                    "offset": 1,
+                    "size": 31,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CONTINUE": {
+              "description": "Typical SHA configuration register 1.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONTINUE": {
+                    "description": "Reserved.",
+                    "offset": 1,
+                    "size": 31,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "BUSY": {
+              "description": "Busy register.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATE": {
+                    "description": "Sha busy state. 1'b0: idle. 1'b1: busy.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DMA_START": {
+              "description": "DMA configuration register 1.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_START": {
+                    "description": "Start dma-sha.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DMA_CONTINUE": {
+              "description": "DMA configuration register 2.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_CONTINUE": {
+                    "description": "Continue dma-sha.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CLEAR_IRQ": {
+              "description": "Interrupt clear register.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLEAR_INTERRUPT": {
+                    "description": "Clear sha interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "IRQ_ENA": {
+              "description": "Interrupt enable register.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "INTERRUPT_ENA": {
+                    "description": "Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "Date register.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 538969622,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "Sha date information/ sha version information.",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "H_MEM": {
+              "description": "Sha H memory which contains intermediate hash or finial hash.",
+              "offset": 64,
+              "size": 8,
+              "count": 64,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "M_MEM": {
+              "description": "Sha M memory which contains message.",
+              "offset": 128,
+              "size": 8,
+              "count": 64,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            }
+          }
+        }
+      },
+      "SPI0": {
+        "description": "SPI (Serial Peripheral Interface) Controller",
+        "children": {
+          "registers": {
+            "CTRL": {
+              "description": "SPI0 control register.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 2891776,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FDUMMY_OUT": {
+                    "description": "In the dummy phase the signal level of spi is output by the spi controller.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FCMD_DUAL": {
+                    "description": "Apply 2 signals during command phase 1:enable 0: disable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FCMD_QUAD": {
+                    "description": "Apply 4 signals during command phase 1:enable 0: disable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FASTRD_MODE": {
+                    "description": "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FREAD_DUAL": {
+                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "Q_POL": {
+                    "description": "The bit is used to set MISO line polarity, 1: high 0, low",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "D_POL": {
+                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FREAD_QUAD": {
+                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "WP": {
+                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FREAD_DIO": {
+                    "description": "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FREAD_QIO": {
+                    "description": "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTRL1": {
+              "description": "SPI0 control1 register.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_MODE": {
+                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "RXFIFO_RST": {
+                    "description": "SPI0 RX FIFO reset signal.",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CTRL2": {
+              "description": "SPI0 control2 register.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 33,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CS_SETUP_TIME": {
+                    "description": "(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "CS_HOLD_TIME": {
+                    "description": "Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.",
+                    "offset": 5,
+                    "size": 5
+                  },
+                  "CS_HOLD_DELAY": {
+                    "description": "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.",
+                    "offset": 25,
+                    "size": 6
+                  },
+                  "SYNC_RESET": {
+                    "description": "The FSM will be reset.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CLOCK": {
+              "description": "SPI clock division control register.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 196867,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKCNT_L": {
+                    "description": "In the master mode it must be equal to spi_mem_clkcnt_N.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CLKCNT_H": {
+                    "description": "In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "CLKCNT_N": {
+                    "description": "In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "CLK_EQU_SYSCLK": {
+                    "description": "Set this bit in 1-division mode.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER": {
+              "description": "SPI0 user register.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CS_HOLD": {
+                    "description": "spi cs keep low when spi is in  done  phase. 1: enable 0: disable.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CS_SETUP": {
+                    "description": "spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "CK_OUT_EDGE": {
+                    "description": "the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "USR_DUMMY_IDLE": {
+                    "description": "spi clock is disable in dummy phase when the bit is enable.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "USR_DUMMY": {
+                    "description": "This bit enable the dummy phase of an operation.",
+                    "offset": 29,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER1": {
+              "description": "SPI0 user1 register.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 1543503879,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DUMMY_CYCLELEN": {
+                    "description": "The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "USR_ADDR_BITLEN": {
+                    "description": "The length in bits of address phase. The register value shall be (bit_num-1).",
+                    "offset": 26,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "USER2": {
+              "description": "SPI0 user2 register.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 1879048192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_COMMAND_VALUE": {
+                    "description": "The value of  command.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "USR_COMMAND_BITLEN": {
+                    "description": "The length in bits of command phase. The register value shall be (bit_num-1)",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RD_STATUS": {
+              "description": "SPI0 read control register.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WB_MODE": {
+                    "description": "Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MISC": {
+              "description": "SPI0 misc register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRANS_END": {
+                    "description": "The bit is used to indicate the  spi0_mst_st controlled transmitting is done.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TRANS_END_INT_ENA": {
+                    "description": "The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CSPI_ST_TRANS_END": {
+                    "description": "The bit is used to indicate the  spi0_slv_st controlled transmitting is done.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CSPI_ST_TRANS_END_INT_ENA": {
+                    "description": "The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CK_IDLE_EDGE": {
+                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CS_KEEP_ACTIVE": {
+                    "description": "spi cs line keep low when the bit is set.",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_FCTRL": {
+              "description": "SPI0 bit mode control register.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_REQ_EN": {
+                    "description": "For SPI0, Cache access enable, 1: enable, 0:disable.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CACHE_USR_ADDR_4BYTE": {
+                    "description": "For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CACHE_FLASH_USR_CMD": {
+                    "description": "For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FDIN_DUAL": {
+                    "description": "For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FDOUT_DUAL": {
+                    "description": "For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FADDR_DUAL": {
+                    "description": "For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FDIN_QUAD": {
+                    "description": "For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FDOUT_QUAD": {
+                    "description": "For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FADDR_QUAD": {
+                    "description": "For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FSM": {
+              "description": "SPI0 FSM status register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CSPI_ST": {
+                    "description": "The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "EM_ST": {
+                    "description": "The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.",
+                    "offset": 4,
+                    "size": 3,
+                    "access": "read-only"
+                  },
+                  "CSPI_LOCK_DELAY_TIME": {
+                    "description": "The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.",
+                    "offset": 7,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "TIMING_CALI": {
+              "description": "SPI0 timing calibration register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMING_CLK_ENA": {
+                    "description": "The bit is used to enable timing adjust clock for all reading operations.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TIMING_CALI": {
+                    "description": "The bit is used to enable timing auto-calibration for all reading operations.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EXTRA_DUMMY_CYCLELEN": {
+                    "description": "add extra dummy spi clock cycle length for spi clock calibration.",
+                    "offset": 2,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "DIN_MODE": {
+              "description": "SPI0 input delay mode control register",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIN0_MODE": {
+                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DIN1_MODE": {
+                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DIN2_MODE": {
+                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DIN3_MODE": {
+                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DIN_NUM": {
+              "description": "SPI0 input delay number control register",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIN0_NUM": {
+                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DIN1_NUM": {
+                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DIN2_NUM": {
+                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DIN3_NUM": {
+                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DOUT_MODE": {
+              "description": "SPI0 output delay mode control register",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DOUT0_MODE": {
+                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DOUT1_MODE": {
+                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DOUT2_MODE": {
+                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DOUT3_MODE": {
+                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "SPI0 clk_gate register",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "Register clock gate enable signal. 1: Enable. 0: Disable.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CORE_CLK_SEL": {
+              "description": "SPI0 module clock select register",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI01_CLK_SEL": {
+                    "description": "When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.",
+                    "offset": 0,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "Version control register",
+              "offset": 1020,
+              "size": 32,
+              "reset_value": 33583408,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "SPI register version.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI1": {
+        "description": "SPI (Serial Peripheral Interface) Controller",
+        "children": {
+          "registers": {
+            "CMD": {
+              "description": "SPI1 memory command register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SPI1_MST_ST": {
+                    "description": "The current status of SPI1 master FSM.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "MSPI_ST": {
+                    "description": "The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "FLASH_PE": {
+                    "description": "In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USR": {
+                    "description": "User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "FLASH_HPM": {
+                    "description": "Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FLASH_RES": {
+                    "description": "This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "FLASH_DP": {
+                    "description": "Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "FLASH_CE": {
+                    "description": "Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FLASH_BE": {
+                    "description": "Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FLASH_SE": {
+                    "description": "Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "FLASH_PP": {
+                    "description": "Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "FLASH_WRSR": {
+                    "description": "Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "FLASH_RDSR": {
+                    "description": "Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "FLASH_RDID": {
+                    "description": "Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "FLASH_WRDI": {
+                    "description": "Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "FLASH_WREN": {
+                    "description": "Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "FLASH_READ": {
+                    "description": "Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ADDR": {
+              "description": "SPI1 address register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_ADDR_VALUE": {
+                    "description": "In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CTRL": {
+              "description": "SPI1 control register.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 2924544,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FDUMMY_OUT": {
+                    "description": "In the dummy phase the signal level of spi is output by the spi controller.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FCMD_DUAL": {
+                    "description": "Apply 2 signals during command phase 1:enable 0: disable",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FCMD_QUAD": {
+                    "description": "Apply 4 signals during command phase 1:enable 0: disable",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FCS_CRC_EN": {
+                    "description": "For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "TX_CRC_EN": {
+                    "description": "For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "FASTRD_MODE": {
+                    "description": "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FREAD_DUAL": {
+                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RESANDRES": {
+                    "description": "The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "Q_POL": {
+                    "description": "The bit is used to set MISO line polarity, 1: high 0, low",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "D_POL": {
+                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "FREAD_QUAD": {
+                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "WP": {
+                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "WRSR_2B": {
+                    "description": "two bytes data will be written to status register when it is set. 1: enable 0: disable.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "FREAD_DIO": {
+                    "description": "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "FREAD_QIO": {
+                    "description": "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CTRL1": {
+              "description": "SPI1 control1 register.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 4092,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_MODE": {
+                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CS_HOLD_DLY_RES": {
+                    "description": "After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.",
+                    "offset": 2,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "CTRL2": {
+              "description": "SPI1 control2 register.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYNC_RESET": {
+                    "description": "The FSM will be reset.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CLOCK": {
+              "description": "SPI1 clock division control register.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 196867,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKCNT_L": {
+                    "description": "In the master mode it must be equal to spi_mem_clkcnt_N.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CLKCNT_H": {
+                    "description": "In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "CLKCNT_N": {
+                    "description": "In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)",
+                    "offset": 16,
+                    "size": 8
+                  },
+                  "CLK_EQU_SYSCLK": {
+                    "description": "reserved",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER": {
+              "description": "SPI1 user register.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 2147483648,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CK_OUT_EDGE": {
+                    "description": "the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FWRITE_DUAL": {
+                    "description": "In the write operations read-data phase apply 2 signals",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FWRITE_QUAD": {
+                    "description": "In the write operations read-data phase apply 4 signals",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "FWRITE_DIO": {
+                    "description": "In the write operations address phase and read-data phase apply 2 signals.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FWRITE_QIO": {
+                    "description": "In the write operations address phase and read-data phase apply 4 signals.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "USR_MISO_HIGHPART": {
+                    "description": "read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "USR_MOSI_HIGHPART": {
+                    "description": "write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "USR_DUMMY_IDLE": {
+                    "description": "SPI clock is disable in dummy phase when the bit is enable.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "USR_MOSI": {
+                    "description": "This bit enable the write-data phase of an operation.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "USR_MISO": {
+                    "description": "This bit enable the read-data phase of an operation.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "USR_DUMMY": {
+                    "description": "This bit enable the dummy phase of an operation.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "USR_ADDR": {
+                    "description": "This bit enable the address phase of an operation.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "USR_COMMAND": {
+                    "description": "This bit enable the command phase of an operation.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER1": {
+              "description": "SPI1 user1 register.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 1543503879,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DUMMY_CYCLELEN": {
+                    "description": "The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "USR_ADDR_BITLEN": {
+                    "description": "The length in bits of address phase. The register value shall be (bit_num-1).",
+                    "offset": 26,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "USER2": {
+              "description": "SPI1 user2 register.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 1879048192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_COMMAND_VALUE": {
+                    "description": "The value of  command.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "USR_COMMAND_BITLEN": {
+                    "description": "The length in bits of command phase. The register value shall be (bit_num-1)",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MOSI_DLEN": {
+              "description": "SPI1 send data bit length control register.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_MOSI_DBITLEN": {
+                    "description": "The length in bits of write-data. The register value shall be (bit_num-1).",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "MISO_DLEN": {
+              "description": "SPI1 receive data bit length control register.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_MISO_DBITLEN": {
+                    "description": "The length in bits of  read-data. The register value shall be (bit_num-1).",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "RD_STATUS": {
+              "description": "SPI1 status register.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATUS": {
+                    "description": "The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "WB_MODE": {
+                    "description": "Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.",
+                    "offset": 16,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MISC": {
+              "description": "SPI1 misc register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CS0_DIS": {
+                    "description": "SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CS1_DIS": {
+                    "description": "SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CK_IDLE_EDGE": {
+                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "CS_KEEP_ACTIVE": {
+                    "description": "spi cs line keep low when the bit is set.",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TX_CRC": {
+              "description": "SPI1 TX CRC data register.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 4294967295,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATA": {
+                    "description": "For SPI1, the value of crc32.",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CACHE_FCTRL": {
+              "description": "SPI1 bit mode control register.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CACHE_USR_ADDR_4BYTE": {
+                    "description": "For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FDIN_DUAL": {
+                    "description": "For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FDOUT_DUAL": {
+                    "description": "For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FADDR_DUAL": {
+                    "description": "For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FDIN_QUAD": {
+                    "description": "For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FDOUT_QUAD": {
+                    "description": "For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "FADDR_QUAD": {
+                    "description": "For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "W0": {
+              "description": "SPI1 memory data buffer0",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF0": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W1": {
+              "description": "SPI1 memory data buffer1",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF1": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W2": {
+              "description": "SPI1 memory data buffer2",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF2": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W3": {
+              "description": "SPI1 memory data buffer3",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF3": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W4": {
+              "description": "SPI1 memory data buffer4",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF4": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W5": {
+              "description": "SPI1 memory data buffer5",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF5": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W6": {
+              "description": "SPI1 memory data buffer6",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF6": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W7": {
+              "description": "SPI1 memory data buffer7",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF7": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W8": {
+              "description": "SPI1 memory data buffer8",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF8": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W9": {
+              "description": "SPI1 memory data buffer9",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF9": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W10": {
+              "description": "SPI1 memory data buffer10",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF10": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W11": {
+              "description": "SPI1 memory data buffer11",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF11": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W12": {
+              "description": "SPI1 memory data buffer12",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF12": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W13": {
+              "description": "SPI1 memory data buffer13",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF13": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W14": {
+              "description": "SPI1 memory data buffer14",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF14": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W15": {
+              "description": "SPI1 memory data buffer15",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF15": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "FLASH_WAITI_CTRL": {
+              "description": "SPI1 wait idle control register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 20,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WAITI_DUMMY": {
+                    "description": "The dummy phase enable when wait flash idle (RDSR)",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WAITI_CMD": {
+                    "description": "The command to wait flash idle(RDSR).",
+                    "offset": 2,
+                    "size": 8
+                  },
+                  "WAITI_DUMMY_CYCLELEN": {
+                    "description": "The dummy cycle length when wait flash idle(RDSR).",
+                    "offset": 10,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "FLASH_SUS_CTRL": {
+              "description": "SPI1 flash suspend control register",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 134225920,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_PER": {
+                    "description": "program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "FLASH_PES": {
+                    "description": "program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FLASH_PER_WAIT_EN": {
+                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FLASH_PES_WAIT_EN": {
+                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PES_PER_EN": {
+                    "description": "Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FLASH_PES_EN": {
+                    "description": "Set this bit to enable Auto-suspending function.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "PESR_END_MSK": {
+                    "description": "The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].",
+                    "offset": 6,
+                    "size": 16
+                  },
+                  "RD_SUS_2B": {
+                    "description": "1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "PER_END_EN": {
+                    "description": "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "PES_END_EN": {
+                    "description": "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "SUS_TIMEOUT_CNT": {
+                    "description": "When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.",
+                    "offset": 25,
+                    "size": 7
+                  }
+                }
+              }
+            },
+            "FLASH_SUS_CMD": {
+              "description": "SPI1 flash suspend command register",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 357754,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_PER_COMMAND": {
+                    "description": "Program/Erase resume command.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "FLASH_PES_COMMAND": {
+                    "description": "Program/Erase suspend command.",
+                    "offset": 8,
+                    "size": 8
+                  },
+                  "WAIT_PESR_COMMAND": {
+                    "description": "Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "SUS_STATUS": {
+              "description": "SPI1 flash suspend status register",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "FLASH_SUS": {
+                    "description": "The status of flash suspend, only used in SPI1.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "WAIT_PESR_CMD_2B": {
+                    "description": "1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FLASH_HPM_DLY_128": {
+                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FLASH_RES_DLY_128": {
+                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FLASH_DP_DLY_128": {
+                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "FLASH_PER_DLY_128": {
+                    "description": "Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FLASH_PES_DLY_128": {
+                    "description": "Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SPI0_LOCK_EN": {
+                    "description": "1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TIMING_CALI": {
+              "description": "SPI1 timing control register",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMING_CALI": {
+                    "description": "The bit is used to enable timing auto-calibration for all reading operations.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EXTRA_DUMMY_CYCLELEN": {
+                    "description": "add extra dummy spi clock cycle length for spi clock calibration.",
+                    "offset": 2,
+                    "size": 3
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "SPI1 interrupt enable register",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PER_END_INT_ENA": {
+                    "description": "The enable bit for SPI_MEM_PER_END_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PES_END_INT_ENA": {
+                    "description": "The enable bit for SPI_MEM_PES_END_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "WPE_END_INT_ENA": {
+                    "description": "The enable bit for SPI_MEM_WPE_END_INT interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLV_ST_END_INT_ENA": {
+                    "description": "The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "MST_ST_END_INT_ENA": {
+                    "description": "The enable bit for SPI_MEM_MST_ST_END_INT interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "SPI1 interrupt clear register",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PER_END_INT_CLR": {
+                    "description": "The clear bit for SPI_MEM_PER_END_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PES_END_INT_CLR": {
+                    "description": "The clear bit for SPI_MEM_PES_END_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "WPE_END_INT_CLR": {
+                    "description": "The clear bit for SPI_MEM_WPE_END_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_ST_END_INT_CLR": {
+                    "description": "The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MST_ST_END_INT_CLR": {
+                    "description": "The clear bit for SPI_MEM_MST_ST_END_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "SPI1 interrupt raw register",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PER_END_INT_RAW": {
+                    "description": "The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PES_END_INT_RAW": {
+                    "description": "The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WPE_END_INT_RAW": {
+                    "description": "The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_ST_END_INT_RAW": {
+                    "description": "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_ST_END_INT_RAW": {
+                    "description": "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "SPI1 interrupt status register",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PER_END_INT_ST": {
+                    "description": "The status bit for SPI_MEM_PER_END_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PES_END_INT_ST": {
+                    "description": "The status bit for SPI_MEM_PES_END_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WPE_END_INT_ST": {
+                    "description": "The status bit for SPI_MEM_WPE_END_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_ST_END_INT_ST": {
+                    "description": "The status bit for SPI_MEM_SLV_ST_END_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_ST_END_INT_ST": {
+                    "description": "The status bit for SPI_MEM_MST_ST_END_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "SPI1 clk_gate register",
+              "offset": 220,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "Register clock gate enable signal. 1: Enable. 0: Disable.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "Version control register",
+              "offset": 1020,
+              "size": 32,
+              "reset_value": 33583472,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "Version control register",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SPI2": {
+        "description": "SPI (Serial Peripheral Interface) Controller",
+        "children": {
+          "registers": {
+            "CMD": {
+              "description": "Command control register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CONF_BITLEN": {
+                    "description": "Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 18
+                  },
+                  "UPDATE": {
+                    "description": "Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "USR": {
+                    "description": "User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.",
+                    "offset": 24,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ADDR": {
+              "description": "Address value register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_ADDR_VALUE": {
+                    "description": "Address to slave. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "CTRL": {
+              "description": "SPI control register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 3932160,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DUMMY_OUT": {
+                    "description": "In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "FADDR_DUAL": {
+                    "description": "Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "FADDR_QUAD": {
+                    "description": "Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "FCMD_DUAL": {
+                    "description": "Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "FCMD_QUAD": {
+                    "description": "Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FREAD_DUAL": {
+                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "FREAD_QUAD": {
+                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "Q_POL": {
+                    "description": "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "D_POL": {
+                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "HOLD_POL": {
+                    "description": "SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "WP_POL": {
+                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "RD_BIT_ORDER": {
+                    "description": "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "WR_BIT_ORDER": {
+                    "description": "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.",
+                    "offset": 26,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CLOCK": {
+              "description": "SPI clock control register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 2147496003,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKCNT_L": {
+                    "description": "In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "CLKCNT_H": {
+                    "description": "In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 6
+                  },
+                  "CLKCNT_N": {
+                    "description": "In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.",
+                    "offset": 12,
+                    "size": 6
+                  },
+                  "CLKDIV_PRE": {
+                    "description": "In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.",
+                    "offset": 18,
+                    "size": 4
+                  },
+                  "CLK_EQU_SYSCLK": {
+                    "description": "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER": {
+              "description": "SPI USER control register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 2147483840,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DOUTDIN": {
+                    "description": "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "QPI_MODE": {
+                    "description": "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "TSCK_I_EDGE": {
+                    "description": "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CS_HOLD": {
+                    "description": "spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CS_SETUP": {
+                    "description": "spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RSCK_I_EDGE": {
+                    "description": "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "CK_OUT_EDGE": {
+                    "description": "the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "FWRITE_DUAL": {
+                    "description": "In the write operations read-data phase apply 2 signals. Can be configured in CONF state.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "FWRITE_QUAD": {
+                    "description": "In the write operations read-data phase apply 4 signals. Can be configured in CONF state.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "USR_CONF_NXT": {
+                    "description": "1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SIO": {
+                    "description": "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "USR_MISO_HIGHPART": {
+                    "description": "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "USR_MOSI_HIGHPART": {
+                    "description": "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "USR_DUMMY_IDLE": {
+                    "description": "spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "USR_MOSI": {
+                    "description": "This bit enable the write-data phase of an operation. Can be configured in CONF state.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "USR_MISO": {
+                    "description": "This bit enable the read-data phase of an operation. Can be configured in CONF state.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "USR_DUMMY": {
+                    "description": "This bit enable the dummy phase of an operation. Can be configured in CONF state.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "USR_ADDR": {
+                    "description": "This bit enable the address phase of an operation. Can be configured in CONF state.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "USR_COMMAND": {
+                    "description": "This bit enable the command phase of an operation. Can be configured in CONF state.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "USER1": {
+              "description": "SPI USER control register 1",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 3091267591,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_DUMMY_CYCLELEN": {
+                    "description": "The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "MST_WFULL_ERR_END_EN": {
+                    "description": "1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "CS_SETUP_TIME": {
+                    "description": "(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.",
+                    "offset": 17,
+                    "size": 5
+                  },
+                  "CS_HOLD_TIME": {
+                    "description": "delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.",
+                    "offset": 22,
+                    "size": 5
+                  },
+                  "USR_ADDR_BITLEN": {
+                    "description": "The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.",
+                    "offset": 27,
+                    "size": 5
+                  }
+                }
+              }
+            },
+            "USER2": {
+              "description": "SPI USER control register 2",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 2013265920,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USR_COMMAND_VALUE": {
+                    "description": "The value of  command. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 16
+                  },
+                  "MST_REMPTY_ERR_END_EN": {
+                    "description": "1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "USR_COMMAND_BITLEN": {
+                    "description": "The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.",
+                    "offset": 28,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MS_DLEN": {
+              "description": "SPI data bit length control register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MS_DATA_BITLEN": {
+                    "description": "The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 18
+                  }
+                }
+              }
+            },
+            "MISC": {
+              "description": "SPI misc register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 62,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CS0_DIS": {
+                    "description": "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "CS1_DIS": {
+                    "description": "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CS2_DIS": {
+                    "description": "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CS3_DIS": {
+                    "description": "SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CS4_DIS": {
+                    "description": "SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CS5_DIS": {
+                    "description": "SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CK_DIS": {
+                    "description": "1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "MASTER_CS_POL": {
+                    "description": "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.",
+                    "offset": 7,
+                    "size": 6
+                  },
+                  "SLAVE_CS_POL": {
+                    "description": "spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "CK_IDLE_EDGE": {
+                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "CS_KEEP_ACTIVE": {
+                    "description": "spi cs line keep low when the bit is set. Can be configured in CONF state.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "QUAD_DIN_PIN_SWAP": {
+                    "description": "1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIN_MODE": {
+              "description": "SPI input delay mode configuration",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIN0_MODE": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DIN1_MODE": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DIN2_MODE": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DIN3_MODE": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 2
+                  },
+                  "TIMING_HCLK_ACTIVE": {
+                    "description": "1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.",
+                    "offset": 16,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DIN_NUM": {
+              "description": "SPI input delay number configuration",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DIN0_NUM": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "DIN1_NUM": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "DIN2_NUM": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "DIN3_NUM": {
+                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
+                    "offset": 6,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "DOUT_MODE": {
+              "description": "SPI output delay mode configuration",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DOUT0_MODE": {
+                    "description": "The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DOUT1_MODE": {
+                    "description": "The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DOUT2_MODE": {
+                    "description": "The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DOUT3_MODE": {
+                    "description": "The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_CONF": {
+              "description": "SPI DMA control register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_SLV_SEG_TRANS_EN": {
+                    "description": "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "SLV_RX_SEG_TRANS_CLR_EN": {
+                    "description": "1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "SLV_TX_SEG_TRANS_CLR_EN": {
+                    "description": "1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RX_EOF_EN": {
+                    "description": "1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "DMA_RX_ENA": {
+                    "description": "Set this bit to enable SPI DMA controlled receive data mode.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "DMA_TX_ENA": {
+                    "description": "Set this bit to enable SPI DMA controlled send data mode.",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "RX_AFIFO_RST": {
+                    "description": "Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "BUF_AFIFO_RST": {
+                    "description": "Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DMA_AFIFO_RST": {
+                    "description": "Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DMA_INT_ENA": {
+              "description": "SPI DMA interrupt enable register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_INFIFO_FULL_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMA_OUTFIFO_EMPTY_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLV_EX_QPI_INT_ENA": {
+                    "description": "The enable bit for SPI slave Ex_QPI interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLV_EN_QPI_INT_ENA": {
+                    "description": "The enable bit for SPI slave En_QPI interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SLV_CMD7_INT_ENA": {
+                    "description": "The enable bit for SPI slave CMD7 interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SLV_CMD8_INT_ENA": {
+                    "description": "The enable bit for SPI slave CMD8 interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SLV_CMD9_INT_ENA": {
+                    "description": "The enable bit for SPI slave CMD9 interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SLV_CMDA_INT_ENA": {
+                    "description": "The enable bit for SPI slave CMDA interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SLV_RD_DMA_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SLV_WR_DMA_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SLV_RD_BUF_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SLV_WR_BUF_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TRANS_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_TRANS_DONE_INT interrupt.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DMA_SEG_TRANS_DONE_INT_ENA": {
+                    "description": "The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SEG_MAGIC_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SLV_BUF_ADDR_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SLV_CMD_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_SLV_CMD_ERR_INT interrupt.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MST_RX_AFIFO_WFULL_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MST_TX_AFIFO_REMPTY_ERR_INT_ENA": {
+                    "description": "The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "APP2_INT_ENA": {
+                    "description": "The enable bit for SPI_APP2_INT interrupt.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "APP1_INT_ENA": {
+                    "description": "The enable bit for SPI_APP1_INT interrupt.",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_INT_CLR": {
+              "description": "SPI DMA interrupt clear register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_INFIFO_FULL_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DMA_OUTFIFO_EMPTY_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_EX_QPI_INT_CLR": {
+                    "description": "The clear bit for SPI slave Ex_QPI interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_EN_QPI_INT_CLR": {
+                    "description": "The clear bit for SPI slave En_QPI interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_CMD7_INT_CLR": {
+                    "description": "The clear bit for SPI slave CMD7 interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_CMD8_INT_CLR": {
+                    "description": "The clear bit for SPI slave CMD8 interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_CMD9_INT_CLR": {
+                    "description": "The clear bit for SPI slave CMD9 interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_CMDA_INT_CLR": {
+                    "description": "The clear bit for SPI slave CMDA interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_RD_DMA_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_WR_DMA_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_RD_BUF_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_WR_BUF_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TRANS_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_TRANS_DONE_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DMA_SEG_TRANS_DONE_INT_CLR": {
+                    "description": "The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SEG_MAGIC_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_BUF_ADDR_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SLV_CMD_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_SLV_CMD_ERR_INT interrupt.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MST_RX_AFIFO_WFULL_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MST_TX_AFIFO_REMPTY_ERR_INT_CLR": {
+                    "description": "The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APP2_INT_CLR": {
+                    "description": "The clear bit for SPI_APP2_INT interrupt.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "APP1_INT_CLR": {
+                    "description": "The clear bit for SPI_APP1_INT interrupt.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DMA_INT_RAW": {
+              "description": "SPI DMA interrupt raw register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_INFIFO_FULL_ERR_INT_RAW": {
+                    "description": "1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DMA_OUTFIFO_EMPTY_ERR_INT_RAW": {
+                    "description": "1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SLV_EX_QPI_INT_RAW": {
+                    "description": "The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SLV_EN_QPI_INT_RAW": {
+                    "description": "The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SLV_CMD7_INT_RAW": {
+                    "description": "The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SLV_CMD8_INT_RAW": {
+                    "description": "The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SLV_CMD9_INT_RAW": {
+                    "description": "The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SLV_CMDA_INT_RAW": {
+                    "description": "The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "SLV_RD_DMA_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SLV_WR_DMA_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SLV_RD_BUF_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SLV_WR_BUF_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TRANS_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "DMA_SEG_TRANS_DONE_INT_RAW": {
+                    "description": "The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "SEG_MAGIC_ERR_INT_RAW": {
+                    "description": "The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "SLV_BUF_ADDR_ERR_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SLV_CMD_ERR_INT_RAW": {
+                    "description": "The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "MST_RX_AFIFO_WFULL_ERR_INT_RAW": {
+                    "description": "The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "MST_TX_AFIFO_REMPTY_ERR_INT_RAW": {
+                    "description": "The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "APP2_INT_RAW": {
+                    "description": "The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "APP1_INT_RAW": {
+                    "description": "The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.",
+                    "offset": 20,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DMA_INT_ST": {
+              "description": "SPI DMA interrupt status register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DMA_INFIFO_FULL_ERR_INT_ST": {
+                    "description": "The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DMA_OUTFIFO_EMPTY_ERR_INT_ST": {
+                    "description": "The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_EX_QPI_INT_ST": {
+                    "description": "The status bit for SPI slave Ex_QPI interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_EN_QPI_INT_ST": {
+                    "description": "The status bit for SPI slave En_QPI interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_CMD7_INT_ST": {
+                    "description": "The status bit for SPI slave CMD7 interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_CMD8_INT_ST": {
+                    "description": "The status bit for SPI slave CMD8 interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_CMD9_INT_ST": {
+                    "description": "The status bit for SPI slave CMD9 interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_CMDA_INT_ST": {
+                    "description": "The status bit for SPI slave CMDA interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_RD_DMA_DONE_INT_ST": {
+                    "description": "The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_WR_DMA_DONE_INT_ST": {
+                    "description": "The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_RD_BUF_DONE_INT_ST": {
+                    "description": "The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_WR_BUF_DONE_INT_ST": {
+                    "description": "The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TRANS_DONE_INT_ST": {
+                    "description": "The status bit for SPI_TRANS_DONE_INT interrupt.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DMA_SEG_TRANS_DONE_INT_ST": {
+                    "description": "The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SEG_MAGIC_ERR_INT_ST": {
+                    "description": "The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_BUF_ADDR_ERR_INT_ST": {
+                    "description": "The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SLV_CMD_ERR_INT_ST": {
+                    "description": "The status bit for SPI_SLV_CMD_ERR_INT interrupt.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_RX_AFIFO_WFULL_ERR_INT_ST": {
+                    "description": "The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MST_TX_AFIFO_REMPTY_ERR_INT_ST": {
+                    "description": "The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APP2_INT_ST": {
+                    "description": "The status bit for SPI_APP2_INT interrupt.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APP1_INT_ST": {
+                    "description": "The status bit for SPI_APP1_INT interrupt.",
+                    "offset": 20,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "W0": {
+              "description": "SPI CPU-controlled buffer0",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF0": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W1": {
+              "description": "SPI CPU-controlled buffer1",
+              "offset": 156,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF1": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W2": {
+              "description": "SPI CPU-controlled buffer2",
+              "offset": 160,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF2": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W3": {
+              "description": "SPI CPU-controlled buffer3",
+              "offset": 164,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF3": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W4": {
+              "description": "SPI CPU-controlled buffer4",
+              "offset": 168,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF4": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W5": {
+              "description": "SPI CPU-controlled buffer5",
+              "offset": 172,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF5": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W6": {
+              "description": "SPI CPU-controlled buffer6",
+              "offset": 176,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF6": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W7": {
+              "description": "SPI CPU-controlled buffer7",
+              "offset": 180,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF7": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W8": {
+              "description": "SPI CPU-controlled buffer8",
+              "offset": 184,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF8": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W9": {
+              "description": "SPI CPU-controlled buffer9",
+              "offset": 188,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF9": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W10": {
+              "description": "SPI CPU-controlled buffer10",
+              "offset": 192,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF10": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W11": {
+              "description": "SPI CPU-controlled buffer11",
+              "offset": 196,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF11": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W12": {
+              "description": "SPI CPU-controlled buffer12",
+              "offset": 200,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF12": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W13": {
+              "description": "SPI CPU-controlled buffer13",
+              "offset": 204,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF13": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W14": {
+              "description": "SPI CPU-controlled buffer14",
+              "offset": 208,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF14": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "W15": {
+              "description": "SPI CPU-controlled buffer15",
+              "offset": 212,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BUF15": {
+                    "description": "data buffer",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "SLAVE": {
+              "description": "SPI slave control register",
+              "offset": 224,
+              "size": 32,
+              "reset_value": 41943040,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_MODE": {
+                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "CLK_MODE_13": {
+                    "description": "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RSCK_DATA_OUT": {
+                    "description": "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SLV_RDDMA_BITLEN_EN": {
+                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SLV_WRDMA_BITLEN_EN": {
+                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SLV_RDBUF_BITLEN_EN": {
+                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "SLV_WRBUF_BITLEN_EN": {
+                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DMA_SEG_MAGIC_VALUE": {
+                    "description": "The magic value of BM table in master DMA seg-trans.",
+                    "offset": 22,
+                    "size": 4
+                  },
+                  "MODE": {
+                    "description": "Set SPI work mode. 1: slave mode 0: master mode.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "SOFT_RESET": {
+                    "description": "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.",
+                    "offset": 27,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "USR_CONF": {
+                    "description": "1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLAVE1": {
+              "description": "SPI slave control register 1",
+              "offset": 228,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SLV_DATA_BITLEN": {
+                    "description": "The transferred data bit length in SPI slave FD and HD mode.",
+                    "offset": 0,
+                    "size": 18
+                  },
+                  "SLV_LAST_COMMAND": {
+                    "description": "In the slave mode it is the value of command.",
+                    "offset": 18,
+                    "size": 8
+                  },
+                  "SLV_LAST_ADDR": {
+                    "description": "In the slave mode it is the value of address.",
+                    "offset": 26,
+                    "size": 6
+                  }
+                }
+              }
+            },
+            "CLK_GATE": {
+              "description": "SPI module clock and register clock control",
+              "offset": 232,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "Set this bit to enable clk gate",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "MST_CLK_ACTIVE": {
+                    "description": "Set this bit to power on the SPI module clock.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "MST_CLK_SEL": {
+                    "description": "This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "Version control",
+              "offset": 240,
+              "size": 32,
+              "reset_value": 33583648,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "SPI register version.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SYSTEM": {
+        "description": "System",
+        "children": {
+          "registers": {
+            "CPU_PERI_CLK_EN": {
+              "description": "cpu_peripheral clock gating register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN_ASSIST_DEBUG": {
+                    "description": "reg_clk_en_assist_debug",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CLK_EN_DEDICATED_GPIO": {
+                    "description": "reg_clk_en_dedicated_gpio",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_PERI_RST_EN": {
+              "description": "cpu_peripheral reset register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RST_EN_ASSIST_DEBUG": {
+                    "description": "reg_rst_en_assist_debug",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "RST_EN_DEDICATED_GPIO": {
+                    "description": "reg_rst_en_dedicated_gpio",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_PER_CONF": {
+              "description": "cpu clock config register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 12,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPUPERIOD_SEL": {
+                    "description": "reg_cpuperiod_sel",
+                    "offset": 0,
+                    "size": 2
+                  },
+                  "PLL_FREQ_SEL": {
+                    "description": "reg_pll_freq_sel",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CPU_WAIT_MODE_FORCE_ON": {
+                    "description": "reg_cpu_wait_mode_force_on",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CPU_WAITI_DELAY_NUM": {
+                    "description": "reg_cpu_waiti_delay_num",
+                    "offset": 4,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "MEM_PD_MASK": {
+              "description": "memory power down mask register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LSLP_MEM_PD_MASK": {
+                    "description": "reg_lslp_mem_pd_mask",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERIP_CLK_EN0": {
+              "description": "peripheral clock gating register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 4190232687,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMERS_CLK_EN": {
+                    "description": "reg_timers_clk_en",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SPI01_CLK_EN": {
+                    "description": "reg_spi01_clk_en",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UART_CLK_EN": {
+                    "description": "reg_uart_clk_en",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "WDG_CLK_EN": {
+                    "description": "reg_wdg_clk_en",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "I2S0_CLK_EN": {
+                    "description": "reg_i2s0_clk_en",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "UART1_CLK_EN": {
+                    "description": "reg_uart1_clk_en",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SPI2_CLK_EN": {
+                    "description": "reg_spi2_clk_en",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "I2C_EXT0_CLK_EN": {
+                    "description": "reg_ext0_clk_en",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "UHCI0_CLK_EN": {
+                    "description": "reg_uhci0_clk_en",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RMT_CLK_EN": {
+                    "description": "reg_rmt_clk_en",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PCNT_CLK_EN": {
+                    "description": "reg_pcnt_clk_en",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LEDC_CLK_EN": {
+                    "description": "reg_ledc_clk_en",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "UHCI1_CLK_EN": {
+                    "description": "reg_uhci1_clk_en",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIMERGROUP_CLK_EN": {
+                    "description": "reg_timergroup_clk_en",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EFUSE_CLK_EN": {
+                    "description": "reg_efuse_clk_en",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TIMERGROUP1_CLK_EN": {
+                    "description": "reg_timergroup1_clk_en",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SPI3_CLK_EN": {
+                    "description": "reg_spi3_clk_en",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PWM0_CLK_EN": {
+                    "description": "reg_pwm0_clk_en",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EXT1_CLK_EN": {
+                    "description": "reg_ext1_clk_en",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CAN_CLK_EN": {
+                    "description": "reg_can_clk_en",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PWM1_CLK_EN": {
+                    "description": "reg_pwm1_clk_en",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2S1_CLK_EN": {
+                    "description": "reg_i2s1_clk_en",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SPI2_DMA_CLK_EN": {
+                    "description": "reg_spi2_dma_clk_en",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "USB_DEVICE_CLK_EN": {
+                    "description": "reg_usb_device_clk_en",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "UART_MEM_CLK_EN": {
+                    "description": "reg_uart_mem_clk_en",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PWM2_CLK_EN": {
+                    "description": "reg_pwm2_clk_en",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PWM3_CLK_EN": {
+                    "description": "reg_pwm3_clk_en",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "SPI3_DMA_CLK_EN": {
+                    "description": "reg_spi3_dma_clk_en",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "APB_SARADC_CLK_EN": {
+                    "description": "reg_apb_saradc_clk_en",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "SYSTIMER_CLK_EN": {
+                    "description": "reg_systimer_clk_en",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ADC2_ARB_CLK_EN": {
+                    "description": "reg_adc2_arb_clk_en",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SPI4_CLK_EN": {
+                    "description": "reg_spi4_clk_en",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERIP_CLK_EN1": {
+              "description": "peripheral clock gating register",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 512,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRYPTO_AES_CLK_EN": {
+                    "description": "reg_crypto_aes_clk_en",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CRYPTO_SHA_CLK_EN": {
+                    "description": "reg_crypto_sha_clk_en",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CRYPTO_RSA_CLK_EN": {
+                    "description": "reg_crypto_rsa_clk_en",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CRYPTO_DS_CLK_EN": {
+                    "description": "reg_crypto_ds_clk_en",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CRYPTO_HMAC_CLK_EN": {
+                    "description": "reg_crypto_hmac_clk_en",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DMA_CLK_EN": {
+                    "description": "reg_dma_clk_en",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SDIO_HOST_CLK_EN": {
+                    "description": "reg_sdio_host_clk_en",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCD_CAM_CLK_EN": {
+                    "description": "reg_lcd_cam_clk_en",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "UART2_CLK_EN": {
+                    "description": "reg_uart2_clk_en",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TSENS_CLK_EN": {
+                    "description": "reg_tsens_clk_en",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERIP_RST_EN0": {
+              "description": "reserved",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMERS_RST": {
+                    "description": "reg_timers_rst",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SPI01_RST": {
+                    "description": "reg_spi01_rst",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UART_RST": {
+                    "description": "reg_uart_rst",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "WDG_RST": {
+                    "description": "reg_wdg_rst",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "I2S0_RST": {
+                    "description": "reg_i2s0_rst",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "UART1_RST": {
+                    "description": "reg_uart1_rst",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "SPI2_RST": {
+                    "description": "reg_spi2_rst",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "I2C_EXT0_RST": {
+                    "description": "reg_ext0_rst",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "UHCI0_RST": {
+                    "description": "reg_uhci0_rst",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RMT_RST": {
+                    "description": "reg_rmt_rst",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "PCNT_RST": {
+                    "description": "reg_pcnt_rst",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "LEDC_RST": {
+                    "description": "reg_ledc_rst",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "UHCI1_RST": {
+                    "description": "reg_uhci1_rst",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TIMERGROUP_RST": {
+                    "description": "reg_timergroup_rst",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "EFUSE_RST": {
+                    "description": "reg_efuse_rst",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TIMERGROUP1_RST": {
+                    "description": "reg_timergroup1_rst",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "SPI3_RST": {
+                    "description": "reg_spi3_rst",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "PWM0_RST": {
+                    "description": "reg_pwm0_rst",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "EXT1_RST": {
+                    "description": "reg_ext1_rst",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "CAN_RST": {
+                    "description": "reg_can_rst",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "PWM1_RST": {
+                    "description": "reg_pwm1_rst",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "I2S1_RST": {
+                    "description": "reg_i2s1_rst",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "SPI2_DMA_RST": {
+                    "description": "reg_spi2_dma_rst",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "USB_DEVICE_RST": {
+                    "description": "reg_usb_device_rst",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "UART_MEM_RST": {
+                    "description": "reg_uart_mem_rst",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "PWM2_RST": {
+                    "description": "reg_pwm2_rst",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "PWM3_RST": {
+                    "description": "reg_pwm3_rst",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "SPI3_DMA_RST": {
+                    "description": "reg_spi3_dma_rst",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "APB_SARADC_RST": {
+                    "description": "reg_apb_saradc_rst",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "SYSTIMER_RST": {
+                    "description": "reg_systimer_rst",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "ADC2_ARB_RST": {
+                    "description": "reg_adc2_arb_rst",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "SPI4_RST": {
+                    "description": "reg_spi4_rst",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PERIP_RST_EN1": {
+              "description": "peripheral reset register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 510,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CRYPTO_AES_RST": {
+                    "description": "reg_crypto_aes_rst",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "CRYPTO_SHA_RST": {
+                    "description": "reg_crypto_sha_rst",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "CRYPTO_RSA_RST": {
+                    "description": "reg_crypto_rsa_rst",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "CRYPTO_DS_RST": {
+                    "description": "reg_crypto_ds_rst",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CRYPTO_HMAC_RST": {
+                    "description": "reg_crypto_hmac_rst",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "DMA_RST": {
+                    "description": "reg_dma_rst",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SDIO_HOST_RST": {
+                    "description": "reg_sdio_host_rst",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "LCD_CAM_RST": {
+                    "description": "reg_lcd_cam_rst",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "UART2_RST": {
+                    "description": "reg_uart2_rst",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "TSENS_RST": {
+                    "description": "reg_tsens_rst",
+                    "offset": 10,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BT_LPCK_DIV_INT": {
+              "description": "clock config register",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 255,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_LPCK_DIV_NUM": {
+                    "description": "reg_bt_lpck_div_num",
+                    "offset": 0,
+                    "size": 12
+                  }
+                }
+              }
+            },
+            "BT_LPCK_DIV_FRAC": {
+              "description": "clock config register",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 33558529,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BT_LPCK_DIV_B": {
+                    "description": "reg_bt_lpck_div_b",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "BT_LPCK_DIV_A": {
+                    "description": "reg_bt_lpck_div_a",
+                    "offset": 12,
+                    "size": 12
+                  },
+                  "LPCLK_SEL_RTC_SLOW": {
+                    "description": "reg_lpclk_sel_rtc_slow",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "LPCLK_SEL_8M": {
+                    "description": "reg_lpclk_sel_8m",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "LPCLK_SEL_XTAL": {
+                    "description": "reg_lpclk_sel_xtal",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "LPCLK_SEL_XTAL32K": {
+                    "description": "reg_lpclk_sel_xtal32k",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "LPCLK_RTC_EN": {
+                    "description": "reg_lpclk_rtc_en",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_0": {
+              "description": "interrupt generate register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_0": {
+                    "description": "reg_cpu_intr_from_cpu_0",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_1": {
+              "description": "interrupt generate register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_1": {
+                    "description": "reg_cpu_intr_from_cpu_1",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_2": {
+              "description": "interrupt generate register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_2": {
+                    "description": "reg_cpu_intr_from_cpu_2",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CPU_INTR_FROM_CPU_3": {
+              "description": "interrupt generate register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CPU_INTR_FROM_CPU_3": {
+                    "description": "reg_cpu_intr_from_cpu_3",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RSA_PD_CTRL": {
+              "description": "rsa memory power control register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RSA_MEM_PD": {
+                    "description": "reg_rsa_mem_pd",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RSA_MEM_FORCE_PU": {
+                    "description": "reg_rsa_mem_force_pu",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "RSA_MEM_FORCE_PD": {
+                    "description": "reg_rsa_mem_force_pd",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EDMA_CTRL": {
+              "description": "edma clcok and reset register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "EDMA_CLK_ON": {
+                    "description": "reg_edma_clk_on",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EDMA_RESET": {
+                    "description": "reg_edma_reset",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CACHE_CONTROL": {
+              "description": "cache control register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 5,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ICACHE_CLK_ON": {
+                    "description": "reg_icache_clk_on",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ICACHE_RESET": {
+                    "description": "reg_icache_reset",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DCACHE_CLK_ON": {
+                    "description": "reg_dcache_clk_on",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "DCACHE_RESET": {
+                    "description": "reg_dcache_reset",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL": {
+              "description": "SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE_SPI_MANUAL_ENCRYPT": {
+                    "description": "reg_enable_spi_manual_encrypt",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "ENABLE_DOWNLOAD_DB_ENCRYPT": {
+                    "description": "reg_enable_download_db_encrypt",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ENABLE_DOWNLOAD_G0CB_DECRYPT": {
+                    "description": "reg_enable_download_g0cb_decrypt",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "ENABLE_DOWNLOAD_MANUAL_ENCRYPT": {
+                    "description": "reg_enable_download_manual_encrypt",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RTC_FASTMEM_CONFIG": {
+              "description": "fast memory config register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 2146435072,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_MEM_CRC_START": {
+                    "description": "reg_rtc_mem_crc_start",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "RTC_MEM_CRC_ADDR": {
+                    "description": "reg_rtc_mem_crc_addr",
+                    "offset": 9,
+                    "size": 11
+                  },
+                  "RTC_MEM_CRC_LEN": {
+                    "description": "reg_rtc_mem_crc_len",
+                    "offset": 20,
+                    "size": 11
+                  },
+                  "RTC_MEM_CRC_FINISH": {
+                    "description": "reg_rtc_mem_crc_finish",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RTC_FASTMEM_CRC": {
+              "description": "reserved",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_MEM_CRC_RES": {
+                    "description": "reg_rtc_mem_crc_res",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "REDUNDANT_ECO_CTRL": {
+              "description": "eco register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "REDUNDANT_ECO_DRIVE": {
+                    "description": "reg_redundant_eco_drive",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "REDUNDANT_ECO_RESULT": {
+                    "description": "reg_redundant_eco_result",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLOCK_GATE": {
+              "description": "clock gating register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "reg_clk_en",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SYSCLK_CONF": {
+              "description": "system clock config register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRE_DIV_CNT": {
+                    "description": "reg_pre_div_cnt",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "SOC_CLK_SEL": {
+                    "description": "reg_soc_clk_sel",
+                    "offset": 10,
+                    "size": 2
+                  },
+                  "CLK_XTAL_FREQ": {
+                    "description": "reg_clk_xtal_freq",
+                    "offset": 12,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "CLK_DIV_EN": {
+                    "description": "reg_clk_div_en",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MEM_PVT": {
+              "description": "mem pvt register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MEM_PATH_LEN": {
+                    "description": "reg_mem_path_len",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "MEM_ERR_CNT_CLR": {
+                    "description": "reg_mem_err_cnt_clr",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "MONITOR_EN": {
+                    "description": "reg_mem_pvt_monitor_en",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "MEM_TIMING_ERR_CNT": {
+                    "description": "reg_mem_timing_err_cnt",
+                    "offset": 6,
+                    "size": 16,
+                    "access": "read-only"
+                  },
+                  "MEM_VT_SEL": {
+                    "description": "reg_mem_vt_sel",
+                    "offset": 22,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "COMB_PVT_LVT_CONF": {
+              "description": "mem pvt register",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_PATH_LEN_LVT": {
+                    "description": "reg_comb_path_len_lvt",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "COMB_ERR_CNT_CLR_LVT": {
+                    "description": "reg_comb_err_cnt_clr_lvt",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "COMB_PVT_MONITOR_EN_LVT": {
+                    "description": "reg_comb_pvt_monitor_en_lvt",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMB_PVT_NVT_CONF": {
+              "description": "mem pvt register",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_PATH_LEN_NVT": {
+                    "description": "reg_comb_path_len_nvt",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "COMB_ERR_CNT_CLR_NVT": {
+                    "description": "reg_comb_err_cnt_clr_nvt",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "COMB_PVT_MONITOR_EN_NVT": {
+                    "description": "reg_comb_pvt_monitor_en_nvt",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMB_PVT_HVT_CONF": {
+              "description": "mem pvt register",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 3,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_PATH_LEN_HVT": {
+                    "description": "reg_comb_path_len_hvt",
+                    "offset": 0,
+                    "size": 5
+                  },
+                  "COMB_ERR_CNT_CLR_HVT": {
+                    "description": "reg_comb_err_cnt_clr_hvt",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "COMB_PVT_MONITOR_EN_HVT": {
+                    "description": "reg_comb_pvt_monitor_en_hvt",
+                    "offset": 6,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_LVT_SITE0": {
+              "description": "mem pvt register",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_LVT_SITE0": {
+                    "description": "reg_comb_timing_err_cnt_lvt_site0",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_NVT_SITE0": {
+              "description": "mem pvt register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_NVT_SITE0": {
+                    "description": "reg_comb_timing_err_cnt_nvt_site0",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_HVT_SITE0": {
+              "description": "mem pvt register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_HVT_SITE0": {
+                    "description": "reg_comb_timing_err_cnt_hvt_site0",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_LVT_SITE1": {
+              "description": "mem pvt register",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_LVT_SITE1": {
+                    "description": "reg_comb_timing_err_cnt_lvt_site1",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_NVT_SITE1": {
+              "description": "mem pvt register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_NVT_SITE1": {
+                    "description": "reg_comb_timing_err_cnt_nvt_site1",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_HVT_SITE1": {
+              "description": "mem pvt register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_HVT_SITE1": {
+                    "description": "reg_comb_timing_err_cnt_hvt_site1",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_LVT_SITE2": {
+              "description": "mem pvt register",
+              "offset": 132,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_LVT_SITE2": {
+                    "description": "reg_comb_timing_err_cnt_lvt_site2",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_NVT_SITE2": {
+              "description": "mem pvt register",
+              "offset": 136,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_NVT_SITE2": {
+                    "description": "reg_comb_timing_err_cnt_nvt_site2",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_HVT_SITE2": {
+              "description": "mem pvt register",
+              "offset": 140,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_HVT_SITE2": {
+                    "description": "reg_comb_timing_err_cnt_hvt_site2",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_LVT_SITE3": {
+              "description": "mem pvt register",
+              "offset": 144,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_LVT_SITE3": {
+                    "description": "reg_comb_timing_err_cnt_lvt_site3",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_NVT_SITE3": {
+              "description": "mem pvt register",
+              "offset": 148,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_NVT_SITE3": {
+                    "description": "reg_comb_timing_err_cnt_nvt_site3",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMB_PVT_ERR_HVT_SITE3": {
+              "description": "mem pvt register",
+              "offset": 152,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "COMB_TIMING_ERR_CNT_HVT_SITE3": {
+                    "description": "reg_comb_timing_err_cnt_hvt_site3",
+                    "offset": 0,
+                    "size": 16,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "SYSTEM_REG_DATE": {
+              "description": "Version register",
+              "offset": 4092,
+              "size": 32,
+              "reset_value": 33583440,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSTEM_REG_DATE": {
+                    "description": "reg_system_reg_date",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "SYSTIMER": {
+        "description": "System Timer",
+        "children": {
+          "registers": {
+            "CONF": {
+              "description": "SYSTIMER_CONF.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1174405120,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SYSTIMER_CLK_FO": {
+                    "description": "systimer clock force on",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TARGET2_WORK_EN": {
+                    "description": "target2 work enable",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "TARGET1_WORK_EN": {
+                    "description": "target1 work enable",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TARGET0_WORK_EN": {
+                    "description": "target0 work enable",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "TIMER_UNIT1_CORE1_STALL_EN": {
+                    "description": "If timer unit1 is stalled when core1 stalled",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "TIMER_UNIT1_CORE0_STALL_EN": {
+                    "description": "If timer unit1 is stalled when core0 stalled",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "TIMER_UNIT0_CORE1_STALL_EN": {
+                    "description": "If timer unit0 is stalled when core1 stalled",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "TIMER_UNIT0_CORE0_STALL_EN": {
+                    "description": "If timer unit0 is stalled when core0 stalled",
+                    "offset": 28,
+                    "size": 1
+                  },
+                  "TIMER_UNIT1_WORK_EN": {
+                    "description": "timer unit1 work enable",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "TIMER_UNIT0_WORK_EN": {
+                    "description": "timer unit0 work enable",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "register file clk gating",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "UNIT0_OP": {
+              "description": "SYSTIMER_UNIT0_OP.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_VALUE_VALID": {
+                    "description": "reg_timer_unit0_value_valid",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIMER_UNIT0_UPDATE": {
+                    "description": "update timer_unit0",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "UNIT1_OP": {
+              "description": "SYSTIMER_UNIT1_OP.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_VALUE_VALID": {
+                    "description": "timer value is sync and valid",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TIMER_UNIT1_UPDATE": {
+                    "description": "update timer unit1",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "UNIT0_LOAD_HI": {
+              "description": "SYSTIMER_UNIT0_LOAD_HI.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_LOAD_HI": {
+                    "description": "timer unit0 load high 32 bit",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "UNIT0_LOAD_LO": {
+              "description": "SYSTIMER_UNIT0_LOAD_LO.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_LOAD_LO": {
+                    "description": "timer unit0 load low 32 bit",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "UNIT1_LOAD_HI": {
+              "description": "SYSTIMER_UNIT1_LOAD_HI.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_LOAD_HI": {
+                    "description": "timer unit1 load high 32 bit",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "UNIT1_LOAD_LO": {
+              "description": "SYSTIMER_UNIT1_LOAD_LO.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_LOAD_LO": {
+                    "description": "timer unit1 load low 32 bit",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TARGET0_HI": {
+              "description": "SYSTIMER_TARGET0_HI.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET0_HI": {
+                    "description": "timer taget0 high 32 bit",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "TARGET0_LO": {
+              "description": "SYSTIMER_TARGET0_LO.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET0_LO": {
+                    "description": "timer taget0 low 32 bit",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TARGET1_HI": {
+              "description": "SYSTIMER_TARGET1_HI.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET1_HI": {
+                    "description": "timer taget1 high 32 bit",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "TARGET1_LO": {
+              "description": "SYSTIMER_TARGET1_LO.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET1_LO": {
+                    "description": "timer taget1 low 32 bit",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TARGET2_HI": {
+              "description": "SYSTIMER_TARGET2_HI.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET2_HI": {
+                    "description": "timer taget2 high 32 bit",
+                    "offset": 0,
+                    "size": 20
+                  }
+                }
+              }
+            },
+            "TARGET2_LO": {
+              "description": "SYSTIMER_TARGET2_LO.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_TARGET2_LO": {
+                    "description": "timer taget2 low 32 bit",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "TARGET0_CONF": {
+              "description": "SYSTIMER_TARGET0_CONF.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET0_PERIOD": {
+                    "description": "target0 period",
+                    "offset": 0,
+                    "size": 26
+                  },
+                  "TARGET0_PERIOD_MODE": {
+                    "description": "Set target0 to period mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "TARGET0_TIMER_UNIT_SEL": {
+                    "description": "select which unit to compare",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TARGET1_CONF": {
+              "description": "SYSTIMER_TARGET1_CONF.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET1_PERIOD": {
+                    "description": "target1 period",
+                    "offset": 0,
+                    "size": 26
+                  },
+                  "TARGET1_PERIOD_MODE": {
+                    "description": "Set target1 to period mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "TARGET1_TIMER_UNIT_SEL": {
+                    "description": "select which unit to compare",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TARGET2_CONF": {
+              "description": "SYSTIMER_TARGET2_CONF.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET2_PERIOD": {
+                    "description": "target2 period",
+                    "offset": 0,
+                    "size": 26
+                  },
+                  "TARGET2_PERIOD_MODE": {
+                    "description": "Set target2 to period mode",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "TARGET2_TIMER_UNIT_SEL": {
+                    "description": "select which unit to compare",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "UNIT0_VALUE_HI": {
+              "description": "SYSTIMER_UNIT0_VALUE_HI.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_VALUE_HI": {
+                    "description": "timer read value high 32bit",
+                    "offset": 0,
+                    "size": 20,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UNIT0_VALUE_LO": {
+              "description": "SYSTIMER_UNIT0_VALUE_LO.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_VALUE_LO": {
+                    "description": "timer read value low 32bit",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UNIT1_VALUE_HI": {
+              "description": "SYSTIMER_UNIT1_VALUE_HI.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_VALUE_HI": {
+                    "description": "timer read value high 32bit",
+                    "offset": 0,
+                    "size": 20,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "UNIT1_VALUE_LO": {
+              "description": "SYSTIMER_UNIT1_VALUE_LO.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_VALUE_LO": {
+                    "description": "timer read value low 32bit",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "COMP0_LOAD": {
+              "description": "SYSTIMER_COMP0_LOAD.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_COMP0_LOAD": {
+                    "description": "timer comp0 load value",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "COMP1_LOAD": {
+              "description": "SYSTIMER_COMP1_LOAD.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_COMP1_LOAD": {
+                    "description": "timer comp1 load value",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "COMP2_LOAD": {
+              "description": "SYSTIMER_COMP2_LOAD.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_COMP2_LOAD": {
+                    "description": "timer comp2 load value",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "UNIT0_LOAD": {
+              "description": "SYSTIMER_UNIT0_LOAD.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT0_LOAD": {
+                    "description": "timer unit0 load value",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "UNIT1_LOAD": {
+              "description": "SYSTIMER_UNIT1_LOAD.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIMER_UNIT1_LOAD": {
+                    "description": "timer unit1 load value",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "SYSTIMER_INT_ENA.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET0_INT_ENA": {
+                    "description": "interupt0 enable",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TARGET1_INT_ENA": {
+                    "description": "interupt1 enable",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TARGET2_INT_ENA": {
+                    "description": "interupt2 enable",
+                    "offset": 2,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "SYSTIMER_INT_RAW.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET0_INT_RAW": {
+                    "description": "interupt0 raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TARGET1_INT_RAW": {
+                    "description": "interupt1 raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TARGET2_INT_RAW": {
+                    "description": "interupt2 raw",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "SYSTIMER_INT_CLR.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET0_INT_CLR": {
+                    "description": "interupt0 clear",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TARGET1_INT_CLR": {
+                    "description": "interupt1 clear",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TARGET2_INT_CLR": {
+                    "description": "interupt2 clear",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "SYSTIMER_INT_ST.",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TARGET0_INT_ST": {
+                    "description": "reg_target0_int_st",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TARGET1_INT_ST": {
+                    "description": "reg_target1_int_st",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TARGET2_INT_ST": {
+                    "description": "reg_target2_int_st",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "SYSTIMER_DATE.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 33579377,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "reg_date",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TIMG0": {
+        "description": "Timer Group",
+        "children": {
+          "registers": {
+            "T0CONFIG": {
+              "description": "TIMG_T0CONFIG_REG.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1610620928,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_USE_XTAL": {
+                    "description": "reg_t0_use_xtal.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "T0_ALARM_EN": {
+                    "description": "reg_t0_alarm_en.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "T0_DIVCNT_RST": {
+                    "description": "reg_t0_divcnt_rst.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "T0_DIVIDER": {
+                    "description": "reg_t0_divider.",
+                    "offset": 13,
+                    "size": 16
+                  },
+                  "T0_AUTORELOAD": {
+                    "description": "reg_t0_autoreload.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "T0_INCREASE": {
+                    "description": "reg_t0_increase.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "T0_EN": {
+                    "description": "reg_t0_en.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "T0LO": {
+              "description": "TIMG_T0LO_REG.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_LO": {
+                    "description": "t0_lo",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "T0HI": {
+              "description": "TIMG_T0HI_REG.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_HI": {
+                    "description": "t0_hi",
+                    "offset": 0,
+                    "size": 22,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "T0UPDATE": {
+              "description": "TIMG_T0UPDATE_REG.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_UPDATE": {
+                    "description": "t0_update",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "T0ALARMLO": {
+              "description": "TIMG_T0ALARMLO_REG.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_ALARM_LO": {
+                    "description": "reg_t0_alarm_lo.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "T0ALARMHI": {
+              "description": "TIMG_T0ALARMHI_REG.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_ALARM_HI": {
+                    "description": "reg_t0_alarm_hi.",
+                    "offset": 0,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "T0LOADLO": {
+              "description": "TIMG_T0LOADLO_REG.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_LOAD_LO": {
+                    "description": "reg_t0_load_lo.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "T0LOADHI": {
+              "description": "TIMG_T0LOADHI_REG.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_LOAD_HI": {
+                    "description": "reg_t0_load_hi.",
+                    "offset": 0,
+                    "size": 22
+                  }
+                }
+              }
+            },
+            "T0LOAD": {
+              "description": "TIMG_T0LOAD_REG.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_LOAD": {
+                    "description": "t0_load",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "WDTCONFIG0": {
+              "description": "TIMG_WDTCONFIG0_REG.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 311296,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_APPCPU_RESET_EN": {
+                    "description": "reg_wdt_appcpu_reset_en.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "WDT_PROCPU_RESET_EN": {
+                    "description": "reg_wdt_procpu_reset_en.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "WDT_FLASHBOOT_MOD_EN": {
+                    "description": "reg_wdt_flashboot_mod_en.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "WDT_SYS_RESET_LENGTH": {
+                    "description": "reg_wdt_sys_reset_length.",
+                    "offset": 15,
+                    "size": 3
+                  },
+                  "WDT_CPU_RESET_LENGTH": {
+                    "description": "reg_wdt_cpu_reset_length.",
+                    "offset": 18,
+                    "size": 3
+                  },
+                  "WDT_USE_XTAL": {
+                    "description": "reg_wdt_use_xtal.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "WDT_CONF_UPDATE_EN": {
+                    "description": "reg_wdt_conf_update_en.",
+                    "offset": 22,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "WDT_STG3": {
+                    "description": "reg_wdt_stg3.",
+                    "offset": 23,
+                    "size": 2
+                  },
+                  "WDT_STG2": {
+                    "description": "reg_wdt_stg2.",
+                    "offset": 25,
+                    "size": 2
+                  },
+                  "WDT_STG1": {
+                    "description": "reg_wdt_stg1.",
+                    "offset": 27,
+                    "size": 2
+                  },
+                  "WDT_STG0": {
+                    "description": "reg_wdt_stg0.",
+                    "offset": 29,
+                    "size": 2
+                  },
+                  "WDT_EN": {
+                    "description": "reg_wdt_en.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "WDTCONFIG1": {
+              "description": "TIMG_WDTCONFIG1_REG.",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 65536,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_DIVCNT_RST": {
+                    "description": "reg_wdt_divcnt_rst.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "WDT_CLK_PRESCALE": {
+                    "description": "reg_wdt_clk_prescale.",
+                    "offset": 16,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "WDTCONFIG2": {
+              "description": "TIMG_WDTCONFIG2_REG.",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 26000000,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG0_HOLD": {
+                    "description": "reg_wdt_stg0_hold.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG3": {
+              "description": "TIMG_WDTCONFIG3_REG.",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 134217727,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG1_HOLD": {
+                    "description": "reg_wdt_stg1_hold.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG4": {
+              "description": "TIMG_WDTCONFIG4_REG.",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 1048575,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG2_HOLD": {
+                    "description": "reg_wdt_stg2_hold.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTCONFIG5": {
+              "description": "TIMG_WDTCONFIG5_REG.",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 1048575,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_STG3_HOLD": {
+                    "description": "reg_wdt_stg3_hold.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "WDTFEED": {
+              "description": "TIMG_WDTFEED_REG.",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_FEED": {
+                    "description": "wdt_feed",
+                    "offset": 0,
+                    "size": 32,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "WDTWPROTECT": {
+              "description": "TIMG_WDTWPROTECT_REG.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 1356348065,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_WKEY": {
+                    "description": "reg_wdt_wkey.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "RTCCALICFG": {
+              "description": "TIMG_RTCCALICFG_REG.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 77824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CALI_START_CYCLING": {
+                    "description": "reg_rtc_cali_start_cycling.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "RTC_CALI_CLK_SEL": {
+                    "description": "reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k",
+                    "offset": 13,
+                    "size": 2
+                  },
+                  "RTC_CALI_RDY": {
+                    "description": "rtc_cali_rdy",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_CALI_MAX": {
+                    "description": "reg_rtc_cali_max.",
+                    "offset": 16,
+                    "size": 15
+                  },
+                  "RTC_CALI_START": {
+                    "description": "reg_rtc_cali_start.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "RTCCALICFG1": {
+              "description": "TIMG_RTCCALICFG1_REG.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CALI_CYCLING_DATA_VLD": {
+                    "description": "rtc_cali_cycling_data_vld",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_CALI_VALUE": {
+                    "description": "rtc_cali_value",
+                    "offset": 7,
+                    "size": 25,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA_TIMERS": {
+              "description": "INT_ENA_TIMG_REG",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_INT_ENA": {
+                    "description": "t0_int_ena",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "WDT_INT_ENA": {
+                    "description": "wdt_int_ena",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_RAW_TIMERS": {
+              "description": "INT_RAW_TIMG_REG",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_INT_RAW": {
+                    "description": "t0_int_raw",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WDT_INT_RAW": {
+                    "description": "wdt_int_raw",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST_TIMERS": {
+              "description": "INT_ST_TIMG_REG",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_INT_ST": {
+                    "description": "t0_int_st",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WDT_INT_ST": {
+                    "description": "wdt_int_st",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_CLR_TIMERS": {
+              "description": "INT_CLR_TIMG_REG",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "T0_INT_CLR": {
+                    "description": "t0_int_clr",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "WDT_INT_CLR": {
+                    "description": "wdt_int_clr",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "RTCCALICFG2": {
+              "description": "TIMG_RTCCALICFG2_REG.",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 4294967192,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RTC_CALI_TIMEOUT": {
+                    "description": "timeoutindicator",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTC_CALI_TIMEOUT_RST_CNT": {
+                    "description": "reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset",
+                    "offset": 3,
+                    "size": 4
+                  },
+                  "RTC_CALI_TIMEOUT_THRES": {
+                    "description": "reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold",
+                    "offset": 7,
+                    "size": 25
+                  }
+                }
+              }
+            },
+            "NTIMG_DATE": {
+              "description": "TIMG_NTIMG_DATE_REG.",
+              "offset": 248,
+              "size": 32,
+              "reset_value": 33579409,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NTIMGS_DATE": {
+                    "description": "reg_ntimers_date.",
+                    "offset": 0,
+                    "size": 28
+                  }
+                }
+              }
+            },
+            "REGCLK": {
+              "description": "TIMG_REGCLK_REG.",
+              "offset": 252,
+              "size": 32,
+              "reset_value": 1610612736,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WDT_CLK_IS_ACTIVE": {
+                    "description": "reg_wdt_clk_is_active.",
+                    "offset": 29,
+                    "size": 1
+                  },
+                  "TIMER_CLK_IS_ACTIVE": {
+                    "description": "reg_timer_clk_is_active.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "reg_clk_en.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "XTS_AES": {
+        "description": "XTS-AES-128 Flash Encryption",
+        "children": {
+          "registers": {
+            "PLAIN_MEM": {
+              "description": "The memory that stores plaintext",
+              "offset": 0,
+              "size": 8,
+              "count": 16,
+              "reset_value": 0,
+              "reset_mask": 4294967295
+            },
+            "LINESIZE": {
+              "description": "XTS-AES line-size register",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "LINESIZE": {
+                    "description": "This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DESTINATION": {
+              "description": "XTS-AES destination register",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DESTINATION": {
+                    "description": "This bit stores the destination. 0: flash(default). 1: reserved.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "PHYSICAL_ADDRESS": {
+              "description": "XTS-AES physical address register",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PHYSICAL_ADDRESS": {
+                    "description": "Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            },
+            "TRIGGER": {
+              "description": "XTS-AES trigger register",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TRIGGER": {
+                    "description": "Set this bit to start manual encryption calculation",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "RELEASE": {
+              "description": "XTS-AES release register",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RELEASE": {
+                    "description": "Set this bit to release the manual encrypted result, after that the result will be visible to spi",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DESTROY": {
+              "description": "XTS-AES destroy register",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DESTROY": {
+                    "description": "Set this bit to destroy XTS-AES result.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STATE": {
+              "description": "XTS-AES status register",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "STATE": {
+                    "description": "Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "XTS-AES version control register",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 538969635,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "Those bits stores the version information of XTS-AES.",
+                    "offset": 0,
+                    "size": 30
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "TWAI": {
+        "description": "Two-Wire Automotive Interface",
+        "children": {
+          "registers": {
+            "MODE": {
+              "description": "Mode Register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RESET_MODE": {
+                    "description": "This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "LISTEN_ONLY_MODE": {
+                    "description": "1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SELF_TEST_MODE": {
+                    "description": "1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RX_FILTER_MODE": {
+                    "description": "This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CMD": {
+              "description": "Command Register",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_REQ": {
+                    "description": "Set the bit to 1 to allow the driving nodes start transmission.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "ABORT_TX": {
+                    "description": "Set the bit to 1 to cancel a pending transmission request.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RELEASE_BUF": {
+                    "description": "Set the bit to 1 to release the RX buffer.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CLR_OVERRUN": {
+                    "description": "Set the bit to 1 to clear the data overrun status bit.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SELF_RX_REQ": {
+                    "description": "Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "Status register",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_BUF_ST": {
+                    "description": "1: The data in the RX buffer is not empty, with at least one received data packet.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVERRUN_ST": {
+                    "description": "1: The RX FIFO is full and data overrun has occurred.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_BUF_ST": {
+                    "description": "1: The TX buffer is empty, the CPU may write a message into it.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_COMPLETE": {
+                    "description": "1: The TWAI controller has successfully received a packet from the bus.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_ST": {
+                    "description": "1: The TWAI Controller is receiving a message from the bus.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_ST": {
+                    "description": "1: The TWAI Controller is transmitting a message to the bus.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERR_ST": {
+                    "description": "1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUS_OFF_ST": {
+                    "description": "1: In bus-off status, the TWAI Controller is no longer involved in bus activities.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "MISS_ST": {
+                    "description": "This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "Interrupt Register",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_INT_ST": {
+                    "description": "Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_INT_ST": {
+                    "description": "Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERR_WARN_INT_ST": {
+                    "description": "Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OVERRUN_INT_ST": {
+                    "description": "Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ERR_PASSIVE_INT_ST": {
+                    "description": "Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ARB_LOST_INT_ST": {
+                    "description": "Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BUS_ERR_INT_ST": {
+                    "description": "Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "Interrupt Enable Register",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_INT_ENA": {
+                    "description": "Set this bit to 1 to enable receive interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TX_INT_ENA": {
+                    "description": "Set this bit to 1 to enable transmit interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "ERR_WARN_INT_ENA": {
+                    "description": "Set this bit to 1 to enable error warning interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "OVERRUN_INT_ENA": {
+                    "description": "Set this bit to 1 to enable data overrun interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "ERR_PASSIVE_INT_ENA": {
+                    "description": "Set this bit to 1 to enable error passive interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "ARB_LOST_INT_ENA": {
+                    "description": "Set this bit to 1 to enable arbitration lost interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BUS_ERR_INT_ENA": {
+                    "description": "Set this bit to 1 to enable error interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "BUS_TIMING_0": {
+              "description": "Bus Timing Register 0",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "BAUD_PRESC": {
+                    "description": "Baud Rate Prescaler, determines the frequency dividing ratio.",
+                    "offset": 0,
+                    "size": 13
+                  },
+                  "SYNC_JUMP_WIDTH": {
+                    "description": "Synchronization Jump Width (SJW), 1 \\verb+~+ 14 Tq wide.",
+                    "offset": 14,
+                    "size": 2
+                  }
+                }
+              }
+            },
+            "BUS_TIMING_1": {
+              "description": "Bus Timing Register 1",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TIME_SEG1": {
+                    "description": "The width of PBS1.",
+                    "offset": 0,
+                    "size": 4
+                  },
+                  "TIME_SEG2": {
+                    "description": "The width of PBS2.",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "TIME_SAMP": {
+                    "description": "The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times",
+                    "offset": 7,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "ARB_LOST_CAP": {
+              "description": "Arbitration Lost Capture Register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ARB_LOST_CAP": {
+                    "description": "This register contains information about the bit position of lost arbitration.",
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ERR_CODE_CAP": {
+              "description": "Error Code Capture Register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ECC_SEGMENT": {
+                    "description": "This register contains information about the location of errors, see Table 181 for details.",
+                    "offset": 0,
+                    "size": 5,
+                    "access": "read-only"
+                  },
+                  "ECC_DIRECTION": {
+                    "description": "This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "ECC_TYPE": {
+                    "description": "This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error",
+                    "offset": 6,
+                    "size": 2,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "ERR_WARNING_LIMIT": {
+              "description": "Error Warning Limit Register",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 96,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ERR_WARNING_LIMIT": {
+                    "description": "Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "RX_ERR_CNT": {
+              "description": "Receive Error Counter Register",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_ERR_CNT": {
+                    "description": "The RX error counter register, reflects value changes under reception status.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TX_ERR_CNT": {
+              "description": "Transmit Error Counter Register",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_ERR_CNT": {
+                    "description": "The TX error counter register, reflects value changes under transmission status.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "DATA_0": {
+              "description": "Data register 0",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_0": {
+                    "description": "In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_1": {
+              "description": "Data register 1",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_1": {
+                    "description": "In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_2": {
+              "description": "Data register 2",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_2": {
+                    "description": "In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_3": {
+              "description": "Data register 3",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_3": {
+                    "description": "In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_4": {
+              "description": "Data register 4",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_4": {
+                    "description": "In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_5": {
+              "description": "Data register 5",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_5": {
+                    "description": "In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_6": {
+              "description": "Data register 6",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_6": {
+                    "description": "In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_7": {
+              "description": "Data register 7",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_7": {
+                    "description": "In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_8": {
+              "description": "Data register 8",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_8": {
+                    "description": "Stored the 8th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_9": {
+              "description": "Data register 9",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_9": {
+                    "description": "Stored the 9th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_10": {
+              "description": "Data register 10",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_10": {
+                    "description": "Stored the 10th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_11": {
+              "description": "Data register 11",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_11": {
+                    "description": "Stored the 11th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "DATA_12": {
+              "description": "Data register 12",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BYTE_12": {
+                    "description": "Stored the 12th byte information of the data to be transmitted under operating mode.",
+                    "offset": 0,
+                    "size": 8,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "RX_MESSAGE_CNT": {
+              "description": "Receive Message Counter Register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_MESSAGE_COUNTER": {
+                    "description": "This register reflects the number of messages available within the RX FIFO.",
+                    "offset": 0,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLOCK_DIVIDER": {
+              "description": "Clock Divider register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CD": {
+                    "description": "These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CLOCK_OFF": {
+                    "description": "This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UART0": {
+        "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
+        "children": {
+          "registers": {
+            "FIFO": {
+              "description": "FIFO data register",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_RD_BYTE": {
+                    "description": "UART 0 accesses FIFO via this register.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "Raw interrupt status",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_FULL_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_EMPTY_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PARITY_ERR_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a parity error in the data.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FRM_ERR_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a data frame error .",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_OVF_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DSR_CHG_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CTS_CHG_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BRK_DET_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_TOUT_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SW_XON_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SW_XOFF_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GLITCH_DET_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_BRK_DONE_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_BRK_IDLE_DONE_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_DONE_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_PARITY_ERR_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_FRM_ERR_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_CLASH_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "AT_CMD_CHAR_DET_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WAKEUP_INT_RAW": {
+                    "description": "This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "Masked interrupt status",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_FULL_INT_ST": {
+                    "description": "This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_EMPTY_INT_ST": {
+                    "description": "This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PARITY_ERR_INT_ST": {
+                    "description": "This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "FRM_ERR_INT_ST": {
+                    "description": "This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_OVF_INT_ST": {
+                    "description": "This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "DSR_CHG_INT_ST": {
+                    "description": "This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CTS_CHG_INT_ST": {
+                    "description": "This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "BRK_DET_INT_ST": {
+                    "description": "This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXFIFO_TOUT_INT_ST": {
+                    "description": "This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SW_XON_INT_ST": {
+                    "description": "This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SW_XOFF_INT_ST": {
+                    "description": "This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "GLITCH_DET_INT_ST": {
+                    "description": "This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_BRK_DONE_INT_ST": {
+                    "description": "This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_BRK_IDLE_DONE_INT_ST": {
+                    "description": "This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_DONE_INT_ST": {
+                    "description": "This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_PARITY_ERR_INT_ST": {
+                    "description": "This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_FRM_ERR_INT_ST": {
+                    "description": "This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RS485_CLASH_INT_ST": {
+                    "description": "This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "AT_CMD_CHAR_DET_INT_ST": {
+                    "description": "This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "WAKEUP_INT_ST": {
+                    "description": "This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "Interrupt enable bits",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_FULL_INT_ENA": {
+                    "description": "This is the enable bit for rxfifo_full_int_st register.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "TXFIFO_EMPTY_INT_ENA": {
+                    "description": "This is the enable bit for txfifo_empty_int_st register.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "PARITY_ERR_INT_ENA": {
+                    "description": "This is the enable bit for parity_err_int_st register.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FRM_ERR_INT_ENA": {
+                    "description": "This is the enable bit for frm_err_int_st register.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RXFIFO_OVF_INT_ENA": {
+                    "description": "This is the enable bit for rxfifo_ovf_int_st register.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "DSR_CHG_INT_ENA": {
+                    "description": "This is the enable bit for dsr_chg_int_st register.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CTS_CHG_INT_ENA": {
+                    "description": "This is the enable bit for cts_chg_int_st register.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "BRK_DET_INT_ENA": {
+                    "description": "This is the enable bit for brk_det_int_st register.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "RXFIFO_TOUT_INT_ENA": {
+                    "description": "This is the enable bit for rxfifo_tout_int_st register.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "SW_XON_INT_ENA": {
+                    "description": "This is the enable bit for sw_xon_int_st register.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "SW_XOFF_INT_ENA": {
+                    "description": "This is the enable bit for sw_xoff_int_st register.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "GLITCH_DET_INT_ENA": {
+                    "description": "This is the enable bit for glitch_det_int_st register.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "TX_BRK_DONE_INT_ENA": {
+                    "description": "This is the enable bit for tx_brk_done_int_st register.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "TX_BRK_IDLE_DONE_INT_ENA": {
+                    "description": "This is the enable bit for tx_brk_idle_done_int_st register.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "TX_DONE_INT_ENA": {
+                    "description": "This is the enable bit for tx_done_int_st register.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "RS485_PARITY_ERR_INT_ENA": {
+                    "description": "This is the enable bit for rs485_parity_err_int_st register.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "RS485_FRM_ERR_INT_ENA": {
+                    "description": "This is the enable bit for rs485_parity_err_int_st register.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RS485_CLASH_INT_ENA": {
+                    "description": "This is the enable bit for rs485_clash_int_st register.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "AT_CMD_CHAR_DET_INT_ENA": {
+                    "description": "This is the enable bit for at_cmd_char_det_int_st register.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "WAKEUP_INT_ENA": {
+                    "description": "This is the enable bit for uart_wakeup_int_st register.",
+                    "offset": 19,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "Interrupt clear bits",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_FULL_INT_CLR": {
+                    "description": "Set this bit to clear the rxfifo_full_int_raw interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TXFIFO_EMPTY_INT_CLR": {
+                    "description": "Set this bit to clear txfifo_empty_int_raw interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PARITY_ERR_INT_CLR": {
+                    "description": "Set this bit to clear parity_err_int_raw interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "FRM_ERR_INT_CLR": {
+                    "description": "Set this bit to clear frm_err_int_raw interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RXFIFO_OVF_INT_CLR": {
+                    "description": "Set this bit to clear rxfifo_ovf_int_raw interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "DSR_CHG_INT_CLR": {
+                    "description": "Set this bit to clear the dsr_chg_int_raw interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CTS_CHG_INT_CLR": {
+                    "description": "Set this bit to clear the cts_chg_int_raw interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "BRK_DET_INT_CLR": {
+                    "description": "Set this bit to clear the brk_det_int_raw interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RXFIFO_TOUT_INT_CLR": {
+                    "description": "Set this bit to clear the rxfifo_tout_int_raw interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SW_XON_INT_CLR": {
+                    "description": "Set this bit to clear the sw_xon_int_raw interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SW_XOFF_INT_CLR": {
+                    "description": "Set this bit to clear the sw_xoff_int_raw interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "GLITCH_DET_INT_CLR": {
+                    "description": "Set this bit to clear the glitch_det_int_raw interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_BRK_DONE_INT_CLR": {
+                    "description": "Set this bit to clear the tx_brk_done_int_raw interrupt..",
+                    "offset": 12,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_BRK_IDLE_DONE_INT_CLR": {
+                    "description": "Set this bit to clear the tx_brk_idle_done_int_raw interrupt.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "TX_DONE_INT_CLR": {
+                    "description": "Set this bit to clear the tx_done_int_raw interrupt.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RS485_PARITY_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the rs485_parity_err_int_raw interrupt.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RS485_FRM_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the rs485_frm_err_int_raw interrupt.",
+                    "offset": 16,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "RS485_CLASH_INT_CLR": {
+                    "description": "Set this bit to clear the rs485_clash_int_raw interrupt.",
+                    "offset": 17,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "AT_CMD_CHAR_DET_INT_CLR": {
+                    "description": "Set this bit to clear the at_cmd_char_det_int_raw interrupt.",
+                    "offset": 18,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "WAKEUP_INT_CLR": {
+                    "description": "Set this bit to clear the uart_wakeup_int_raw interrupt.",
+                    "offset": 19,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CLKDIV": {
+              "description": "Clock divider configuration",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 694,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLKDIV": {
+                    "description": "The integral part of the frequency divider factor.",
+                    "offset": 0,
+                    "size": 12
+                  },
+                  "FRAG": {
+                    "description": "The decimal part of the frequency divider factor.",
+                    "offset": 20,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "RX_FILT": {
+              "description": "Rx Filter configuration",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "GLITCH_FILT": {
+                    "description": "when input pulse width is lower than this value, the pulse is ignored.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "GLITCH_FILT_EN": {
+                    "description": "Set this bit to enable Rx signal filter.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "STATUS": {
+              "description": "UART status register",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 3758145536,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_CNT": {
+                    "description": "Stores the byte number of valid data in Rx-FIFO.",
+                    "offset": 0,
+                    "size": 10,
+                    "access": "read-only"
+                  },
+                  "DSRN": {
+                    "description": "The register represent the level value of the internal uart dsr signal.",
+                    "offset": 13,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CTSN": {
+                    "description": "This register represent the level value of the internal uart cts signal.",
+                    "offset": 14,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RXD": {
+                    "description": "This register represent the  level value of the internal uart rxd signal.",
+                    "offset": 15,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXFIFO_CNT": {
+                    "description": "Stores the byte number of data in Tx-FIFO.",
+                    "offset": 16,
+                    "size": 10,
+                    "access": "read-only"
+                  },
+                  "DTRN": {
+                    "description": "This bit represents the level of the internal uart dtr signal.",
+                    "offset": 29,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RTSN": {
+                    "description": "This bit represents the level of the internal uart rts signal.",
+                    "offset": 30,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TXD": {
+                    "description": "This bit represents the  level of the internal uart txd signal.",
+                    "offset": 31,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CONF0": {
+              "description": "a",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 268435484,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PARITY": {
+                    "description": "This register is used to configure the parity check mode.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "PARITY_EN": {
+                    "description": "Set this bit to enable uart parity check.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "BIT_NUM": {
+                    "description": "This register is used to set the length of data.",
+                    "offset": 2,
+                    "size": 2
+                  },
+                  "STOP_BIT_NUM": {
+                    "description": "This register is used to set the length of  stop bit.",
+                    "offset": 4,
+                    "size": 2
+                  },
+                  "SW_RTS": {
+                    "description": "This register is used to configure the software rts signal which is used in software flow control.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "SW_DTR": {
+                    "description": "This register is used to configure the software dtr signal which is used in software flow control.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "TXD_BRK": {
+                    "description": "Set this bit to enbale transmitter to  send NULL when the process of sending data is done.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "IRDA_DPLX": {
+                    "description": "Set this bit to enable IrDA loopback mode.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "IRDA_TX_EN": {
+                    "description": "This is the start enable bit for IrDA transmitter.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "IRDA_WCTL": {
+                    "description": "1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "IRDA_TX_INV": {
+                    "description": "Set this bit to invert the level of  IrDA transmitter.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "IRDA_RX_INV": {
+                    "description": "Set this bit to invert the level of IrDA receiver.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "LOOPBACK": {
+                    "description": "Set this bit to enable uart loopback test mode.",
+                    "offset": 14,
+                    "size": 1
+                  },
+                  "TX_FLOW_EN": {
+                    "description": "Set this bit to enable flow control function for transmitter.",
+                    "offset": 15,
+                    "size": 1
+                  },
+                  "IRDA_EN": {
+                    "description": "Set this bit to enable IrDA protocol.",
+                    "offset": 16,
+                    "size": 1
+                  },
+                  "RXFIFO_RST": {
+                    "description": "Set this bit to reset the uart receive-FIFO.",
+                    "offset": 17,
+                    "size": 1
+                  },
+                  "TXFIFO_RST": {
+                    "description": "Set this bit to reset the uart transmit-FIFO.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RXD_INV": {
+                    "description": "Set this bit to inverse the level value of uart rxd signal.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "CTS_INV": {
+                    "description": "Set this bit to inverse the level value of uart cts signal.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "DSR_INV": {
+                    "description": "Set this bit to inverse the level value of uart dsr signal.",
+                    "offset": 21,
+                    "size": 1
+                  },
+                  "TXD_INV": {
+                    "description": "Set this bit to inverse the level value of uart txd signal.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "RTS_INV": {
+                    "description": "Set this bit to inverse the level value of uart rts signal.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "DTR_INV": {
+                    "description": "Set this bit to inverse the level value of uart dtr signal.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "ERR_WR_MASK": {
+                    "description": "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "AUTOBAUD_EN": {
+                    "description": "This is the enable bit for detecting baudrate.",
+                    "offset": 27,
+                    "size": 1
+                  },
+                  "MEM_CLK_EN": {
+                    "description": "UART memory clock gate enable signal.",
+                    "offset": 28,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "CONF1": {
+              "description": "Configuration register 1",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 49248,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXFIFO_FULL_THRHD": {
+                    "description": "It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "TXFIFO_EMPTY_THRHD": {
+                    "description": "It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.",
+                    "offset": 9,
+                    "size": 9
+                  },
+                  "DIS_RX_DAT_OVF": {
+                    "description": "Disable UART Rx data overflow detect.",
+                    "offset": 18,
+                    "size": 1
+                  },
+                  "RX_TOUT_FLOW_DIS": {
+                    "description": "Set this bit to stop accumulating idle_cnt when hardware flow control works.",
+                    "offset": 19,
+                    "size": 1
+                  },
+                  "RX_FLOW_EN": {
+                    "description": "This is the flow enable bit for UART receiver.",
+                    "offset": 20,
+                    "size": 1
+                  },
+                  "RX_TOUT_EN": {
+                    "description": "This is the enble bit for uart receiver's timeout function.",
+                    "offset": 21,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "LOWPULSE": {
+              "description": "Autobaud minimum low pulse duration register",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MIN_CNT": {
+                    "description": "This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "HIGHPULSE": {
+              "description": "Autobaud minimum high pulse duration register",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "MIN_CNT": {
+                    "description": "This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "RXD_CNT": {
+              "description": "Autobaud edge change count register",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RXD_EDGE_CNT": {
+                    "description": "This register stores the count of rxd edge change. It is used in baud rate-detect process.",
+                    "offset": 0,
+                    "size": 10,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FLOW_CONF": {
+              "description": "Software flow-control configuration",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SW_FLOW_CON_EN": {
+                    "description": "Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "XONOFF_DEL": {
+                    "description": "Set this bit to remove flow control char from the received data.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "FORCE_XON": {
+                    "description": "Set this bit to enable the transmitter to go on sending data.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "FORCE_XOFF": {
+                    "description": "Set this bit to stop the  transmitter from sending data.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SEND_XON": {
+                    "description": "Set this bit to send Xon char. It is cleared by hardware automatically.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "SEND_XOFF": {
+                    "description": "Set this bit to send Xoff char. It is cleared by hardware automatically.",
+                    "offset": 5,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "SLEEP_CONF": {
+              "description": "Sleep-mode configuration",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 240,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ACTIVE_THRESHOLD": {
+                    "description": "The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.",
+                    "offset": 0,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "SWFC_CONF0": {
+              "description": "Software flow-control character configuration",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 9952,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XOFF_THRESHOLD": {
+                    "description": "When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "XOFF_CHAR": {
+                    "description": "This register stores the Xoff flow control char.",
+                    "offset": 9,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "SWFC_CONF1": {
+              "description": "Software flow-control character configuration",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 8704,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "XON_THRESHOLD": {
+                    "description": "When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.",
+                    "offset": 0,
+                    "size": 9
+                  },
+                  "XON_CHAR": {
+                    "description": "This register stores the Xon flow control char.",
+                    "offset": 9,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "TXBRK_CONF": {
+              "description": "Tx Break character configuration",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 10,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_BRK_NUM": {
+                    "description": "This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "IDLE_CONF": {
+              "description": "Frame-end idle configuration",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 262400,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_IDLE_THRHD": {
+                    "description": "It will produce frame end signal when receiver takes more time to receive one byte data than this register value.",
+                    "offset": 0,
+                    "size": 10
+                  },
+                  "TX_IDLE_NUM": {
+                    "description": "This register is used to configure the duration time between transfers.",
+                    "offset": 10,
+                    "size": 10
+                  }
+                }
+              }
+            },
+            "RS485_CONF": {
+              "description": "RS485 mode configuration",
+              "offset": 76,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RS485_EN": {
+                    "description": "Set this bit to choose the rs485 mode.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "DL0_EN": {
+                    "description": "Set this bit to delay the stop bit by 1 bit.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "DL1_EN": {
+                    "description": "Set this bit to delay the stop bit by 1 bit.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "RS485TX_RX_EN": {
+                    "description": "Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "RS485RXBY_TX_EN": {
+                    "description": "1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "RS485_RX_DLY_NUM": {
+                    "description": "This register is used to delay the receiver's internal data signal.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "RS485_TX_DLY_NUM": {
+                    "description": "This register is used to delay the transmitter's internal data signal.",
+                    "offset": 6,
+                    "size": 4
+                  }
+                }
+              }
+            },
+            "AT_CMD_PRECNT": {
+              "description": "Pre-sequence timing configuration",
+              "offset": 80,
+              "size": 32,
+              "reset_value": 2305,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PRE_IDLE_NUM": {
+                    "description": "This register is used to configure the idle duration time before the first at_cmd is received by receiver.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "AT_CMD_POSTCNT": {
+              "description": "Post-sequence timing configuration",
+              "offset": 84,
+              "size": 32,
+              "reset_value": 2305,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POST_IDLE_NUM": {
+                    "description": "This register is used to configure the duration time between the last at_cmd and the next data.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "AT_CMD_GAPTOUT": {
+              "description": "Timeout configuration",
+              "offset": 88,
+              "size": 32,
+              "reset_value": 11,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_GAP_TOUT": {
+                    "description": "This register is used to configure the duration time between the at_cmd chars.",
+                    "offset": 0,
+                    "size": 16
+                  }
+                }
+              }
+            },
+            "AT_CMD_CHAR": {
+              "description": "AT escape sequence detection configuration",
+              "offset": 92,
+              "size": 32,
+              "reset_value": 811,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "AT_CMD_CHAR": {
+                    "description": "This register is used to configure the content of at_cmd char.",
+                    "offset": 0,
+                    "size": 8
+                  },
+                  "CHAR_NUM": {
+                    "description": "This register is used to configure the num of continuous at_cmd chars received by receiver.",
+                    "offset": 8,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "MEM_CONF": {
+              "description": "UART threshold and allocation configuration",
+              "offset": 96,
+              "size": 32,
+              "reset_value": 655378,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_SIZE": {
+                    "description": "This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.",
+                    "offset": 1,
+                    "size": 3
+                  },
+                  "TX_SIZE": {
+                    "description": "This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.",
+                    "offset": 4,
+                    "size": 3
+                  },
+                  "RX_FLOW_THRHD": {
+                    "description": "This register is used to configure the maximum amount of data that can be received  when hardware flow control works.",
+                    "offset": 7,
+                    "size": 9
+                  },
+                  "RX_TOUT_THRHD": {
+                    "description": "This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.",
+                    "offset": 16,
+                    "size": 10
+                  },
+                  "MEM_FORCE_PD": {
+                    "description": "Set this bit to force power down UART memory.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "MEM_FORCE_PU": {
+                    "description": "Set this bit to force power up UART memory.",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MEM_TX_STATUS": {
+              "description": "Tx-FIFO write and read offset address.",
+              "offset": 100,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_TX_WADDR": {
+                    "description": "This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.",
+                    "offset": 0,
+                    "size": 10,
+                    "access": "read-only"
+                  },
+                  "TX_RADDR": {
+                    "description": "This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.",
+                    "offset": 11,
+                    "size": 10,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MEM_RX_STATUS": {
+              "description": "Rx-FIFO write and read offset address.",
+              "offset": 104,
+              "size": 32,
+              "reset_value": 524544,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "APB_RX_RADDR": {
+                    "description": "This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.",
+                    "offset": 0,
+                    "size": 10,
+                    "access": "read-only"
+                  },
+                  "RX_WADDR": {
+                    "description": "This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.",
+                    "offset": 11,
+                    "size": 10,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "FSM_STATUS": {
+              "description": "UART transmit and receive status.",
+              "offset": 108,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ST_URX_OUT": {
+                    "description": "This is the status register of receiver.",
+                    "offset": 0,
+                    "size": 4,
+                    "access": "read-only"
+                  },
+                  "ST_UTX_OUT": {
+                    "description": "This is the status register of transmitter.",
+                    "offset": 4,
+                    "size": 4,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "POSPULSE": {
+              "description": "Autobaud high pulse register",
+              "offset": 112,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "POSEDGE_MIN_CNT": {
+                    "description": "This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "NEGPULSE": {
+              "description": "Autobaud low pulse register",
+              "offset": 116,
+              "size": 32,
+              "reset_value": 4095,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "NEGEDGE_MIN_CNT": {
+                    "description": "This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.",
+                    "offset": 0,
+                    "size": 12,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "CLK_CONF": {
+              "description": "UART core clock configuration",
+              "offset": 120,
+              "size": 32,
+              "reset_value": 57675776,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SCLK_DIV_B": {
+                    "description": "The  denominator of the frequency divider factor.",
+                    "offset": 0,
+                    "size": 6
+                  },
+                  "SCLK_DIV_A": {
+                    "description": "The numerator of the frequency divider factor.",
+                    "offset": 6,
+                    "size": 6
+                  },
+                  "SCLK_DIV_NUM": {
+                    "description": "The integral part of the frequency divider factor.",
+                    "offset": 12,
+                    "size": 8
+                  },
+                  "SCLK_SEL": {
+                    "description": "UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.",
+                    "offset": 20,
+                    "size": 2
+                  },
+                  "SCLK_EN": {
+                    "description": "Set this bit to enable UART Tx/Rx clock.",
+                    "offset": 22,
+                    "size": 1
+                  },
+                  "RST_CORE": {
+                    "description": "Write 1 then write 0 to this bit, reset UART Tx/Rx.",
+                    "offset": 23,
+                    "size": 1
+                  },
+                  "TX_SCLK_EN": {
+                    "description": "Set this bit to enable UART Tx clock.",
+                    "offset": 24,
+                    "size": 1
+                  },
+                  "RX_SCLK_EN": {
+                    "description": "Set this bit to enable UART Rx clock.",
+                    "offset": 25,
+                    "size": 1
+                  },
+                  "TX_RST_CORE": {
+                    "description": "Write 1 then write 0 to this bit, reset UART Tx.",
+                    "offset": 26,
+                    "size": 1
+                  },
+                  "RX_RST_CORE": {
+                    "description": "Write 1 then write 0 to this bit, reset UART Rx.",
+                    "offset": 27,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "UART Version register",
+              "offset": 124,
+              "size": 32,
+              "reset_value": 33587824,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "This is the version register.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            },
+            "ID": {
+              "description": "UART ID register",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 1073743104,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ID": {
+                    "description": "This register is used to configure the uart_id.",
+                    "offset": 0,
+                    "size": 30
+                  },
+                  "HIGH_SPEED": {
+                    "description": "This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.",
+                    "offset": 30,
+                    "size": 1
+                  },
+                  "REG_UPDATE": {
+                    "description": "Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.",
+                    "offset": 31,
+                    "size": 1
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "USB_DEVICE": {
+        "description": "Full-speed USB Serial/JTAG Controller",
+        "children": {
+          "registers": {
+            "EP1": {
+              "description": "USB_DEVICE_EP1_REG.",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RDWR_BYTE": {
+                    "description": "Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.",
+                    "offset": 0,
+                    "size": 8
+                  }
+                }
+              }
+            },
+            "EP1_CONF": {
+              "description": "USB_DEVICE_EP1_CONF_REG.",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "WR_DONE": {
+                    "description": "Set this bit to indicate writing byte data to UART Tx FIFO is done.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SERIAL_IN_EP_DATA_FREE": {
+                    "description": "1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SERIAL_OUT_EP_DATA_AVAIL": {
+                    "description": "1'b1: Indicate there is data in UART Rx FIFO.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "USB_DEVICE_INT_RAW_REG.",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 8,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JTAG_IN_FLUSH_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOF_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when SOF frame is received.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SERIAL_OUT_RECV_PKT_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SERIAL_IN_EMPTY_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PID_ERR_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when pid error is detected.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRC5_ERR_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when CRC5 error is detected.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRC16_ERR_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when CRC16 error is detected.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STUFF_ERR_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when stuff error is detected.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_TOKEN_REC_IN_EP1_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USB_BUS_RESET_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when usb bus reset is detected.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EP1_ZERO_PAYLOAD_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EP2_ZERO_PAYLOAD_INT_RAW": {
+                    "description": "The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "USB_DEVICE_INT_ST_REG.",
+              "offset": 12,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JTAG_IN_FLUSH_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SOF_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SERIAL_OUT_RECV_PKT_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SERIAL_IN_EMPTY_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "PID_ERR_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRC5_ERR_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "CRC16_ERR_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "STUFF_ERR_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_TOKEN_REC_IN_EP1_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "USB_BUS_RESET_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EP1_ZERO_PAYLOAD_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EP2_ZERO_PAYLOAD_INT_ST": {
+                    "description": "The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "INT_ENA": {
+              "description": "USB_DEVICE_INT_ENA_REG.",
+              "offset": 16,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JTAG_IN_FLUSH_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "SOF_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "SERIAL_OUT_RECV_PKT_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "SERIAL_IN_EMPTY_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "PID_ERR_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.",
+                    "offset": 4,
+                    "size": 1
+                  },
+                  "CRC5_ERR_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "CRC16_ERR_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "STUFF_ERR_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "IN_TOKEN_REC_IN_EP1_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "USB_BUS_RESET_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "OUT_EP1_ZERO_PAYLOAD_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "OUT_EP2_ZERO_PAYLOAD_INT_ENA": {
+                    "description": "The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 11,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_CLR": {
+              "description": "USB_DEVICE_INT_CLR_REG.",
+              "offset": 20,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "JTAG_IN_FLUSH_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SOF_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SERIAL_OUT_RECV_PKT_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "SERIAL_IN_EMPTY_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "PID_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CRC5_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "CRC16_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "STUFF_ERR_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "IN_TOKEN_REC_IN_EP1_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.",
+                    "offset": 8,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "USB_BUS_RESET_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
+                    "offset": 9,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_EP1_ZERO_PAYLOAD_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 10,
+                    "size": 1,
+                    "access": "write-only"
+                  },
+                  "OUT_EP2_ZERO_PAYLOAD_INT_CLR": {
+                    "description": "Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
+                    "offset": 11,
+                    "size": 1,
+                    "access": "write-only"
+                  }
+                }
+              }
+            },
+            "CONF0": {
+              "description": "USB_DEVICE_CONF0_REG.",
+              "offset": 24,
+              "size": 32,
+              "reset_value": 16896,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "PHY_SEL": {
+                    "description": "Select internal/external PHY",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "EXCHG_PINS_OVERRIDE": {
+                    "description": "Enable software control USB D+ D- exchange",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "EXCHG_PINS": {
+                    "description": "USB D+ D- exchange",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "VREFH": {
+                    "description": "Control single-end input high threshold,1.76V to 2V, step 80mV",
+                    "offset": 3,
+                    "size": 2
+                  },
+                  "VREFL": {
+                    "description": "Control single-end input low threshold,0.8V to 1.04V, step 80mV",
+                    "offset": 5,
+                    "size": 2
+                  },
+                  "VREF_OVERRIDE": {
+                    "description": "Enable software control input  threshold",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "PAD_PULL_OVERRIDE": {
+                    "description": "Enable software control USB D+ D- pullup pulldown",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "DP_PULLUP": {
+                    "description": "Control USB D+ pull up.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "DP_PULLDOWN": {
+                    "description": "Control USB D+ pull down.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "DM_PULLUP": {
+                    "description": "Control USB D- pull up.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "DM_PULLDOWN": {
+                    "description": "Control USB D- pull down.",
+                    "offset": 12,
+                    "size": 1
+                  },
+                  "PULLUP_VALUE": {
+                    "description": "Control pull up value.",
+                    "offset": 13,
+                    "size": 1
+                  },
+                  "USB_PAD_ENABLE": {
+                    "description": "Enable USB pad function.",
+                    "offset": 14,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "TEST": {
+              "description": "USB_DEVICE_TEST_REG.",
+              "offset": 28,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "ENABLE": {
+                    "description": "Enable test of the USB pad",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USB_OE": {
+                    "description": "USB pad oen in test",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "TX_DP": {
+                    "description": "USB D+ tx value in test",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "TX_DM": {
+                    "description": "USB D- tx value in test",
+                    "offset": 3,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "JFIFO_ST": {
+              "description": "USB_DEVICE_JFIFO_ST_REG.",
+              "offset": 32,
+              "size": 32,
+              "reset_value": 68,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_FIFO_CNT": {
+                    "description": "JTAT in fifo counter.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_FIFO_EMPTY": {
+                    "description": "1: JTAG in fifo is empty.",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_FIFO_FULL": {
+                    "description": "1: JTAG in fifo is full.",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_FIFO_CNT": {
+                    "description": "JTAT out fifo counter.",
+                    "offset": 4,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_FIFO_EMPTY": {
+                    "description": "1: JTAG out fifo is empty.",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_FIFO_FULL": {
+                    "description": "1: JTAG out fifo is full.",
+                    "offset": 7,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "IN_FIFO_RESET": {
+                    "description": "Write 1 to reset JTAG in fifo.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "OUT_FIFO_RESET": {
+                    "description": "Write 1 to reset JTAG out fifo.",
+                    "offset": 9,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "FRAM_NUM": {
+              "description": "USB_DEVICE_FRAM_NUM_REG.",
+              "offset": 36,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "SOF_FRAME_INDEX": {
+                    "description": "Frame index of received SOF frame.",
+                    "offset": 0,
+                    "size": 11,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_EP0_ST": {
+              "description": "USB_DEVICE_IN_EP0_ST_REG.",
+              "offset": 40,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_EP0_STATE": {
+                    "description": "State of IN Endpoint 0.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_EP0_WR_ADDR": {
+                    "description": "Write data address of IN endpoint 0.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "IN_EP0_RD_ADDR": {
+                    "description": "Read data address of IN endpoint 0.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_EP1_ST": {
+              "description": "USB_DEVICE_IN_EP1_ST_REG.",
+              "offset": 44,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_EP1_STATE": {
+                    "description": "State of IN Endpoint 1.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_EP1_WR_ADDR": {
+                    "description": "Write data address of IN endpoint 1.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "IN_EP1_RD_ADDR": {
+                    "description": "Read data address of IN endpoint 1.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_EP2_ST": {
+              "description": "USB_DEVICE_IN_EP2_ST_REG.",
+              "offset": 48,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_EP2_STATE": {
+                    "description": "State of IN Endpoint 2.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_EP2_WR_ADDR": {
+                    "description": "Write data address of IN endpoint 2.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "IN_EP2_RD_ADDR": {
+                    "description": "Read data address of IN endpoint 2.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "IN_EP3_ST": {
+              "description": "USB_DEVICE_IN_EP3_ST_REG.",
+              "offset": 52,
+              "size": 32,
+              "reset_value": 1,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "IN_EP3_STATE": {
+                    "description": "State of IN Endpoint 3.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "IN_EP3_WR_ADDR": {
+                    "description": "Write data address of IN endpoint 3.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "IN_EP3_RD_ADDR": {
+                    "description": "Read data address of IN endpoint 3.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EP0_ST": {
+              "description": "USB_DEVICE_OUT_EP0_ST_REG.",
+              "offset": 56,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EP0_STATE": {
+                    "description": "State of OUT Endpoint 0.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_EP0_WR_ADDR": {
+                    "description": "Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "OUT_EP0_RD_ADDR": {
+                    "description": "Read data address of OUT endpoint 0.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EP1_ST": {
+              "description": "USB_DEVICE_OUT_EP1_ST_REG.",
+              "offset": 60,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EP1_STATE": {
+                    "description": "State of OUT Endpoint 1.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_EP1_WR_ADDR": {
+                    "description": "Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "OUT_EP1_RD_ADDR": {
+                    "description": "Read data address of OUT endpoint 1.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "OUT_EP1_REC_DATA_CNT": {
+                    "description": "Data count in OUT endpoint 1 when one packet is received.",
+                    "offset": 16,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "OUT_EP2_ST": {
+              "description": "USB_DEVICE_OUT_EP2_ST_REG.",
+              "offset": 64,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "OUT_EP2_STATE": {
+                    "description": "State of OUT Endpoint 2.",
+                    "offset": 0,
+                    "size": 2,
+                    "access": "read-only"
+                  },
+                  "OUT_EP2_WR_ADDR": {
+                    "description": "Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.",
+                    "offset": 2,
+                    "size": 7,
+                    "access": "read-only"
+                  },
+                  "OUT_EP2_RD_ADDR": {
+                    "description": "Read data address of OUT endpoint 2.",
+                    "offset": 9,
+                    "size": 7,
+                    "access": "read-only"
+                  }
+                }
+              }
+            },
+            "MISC_CONF": {
+              "description": "USB_DEVICE_MISC_CONF_REG.",
+              "offset": 68,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "CLK_EN": {
+                    "description": "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.",
+                    "offset": 0,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "MEM_CONF": {
+              "description": "USB_DEVICE_MEM_CONF_REG.",
+              "offset": 72,
+              "size": 32,
+              "reset_value": 2,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "USB_MEM_PD": {
+                    "description": "1: power down usb memory.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "USB_MEM_CLK_EN": {
+                    "description": "1: Force clock on for usb memory.",
+                    "offset": 1,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "DATE": {
+              "description": "USB_DEVICE_DATE_REG.",
+              "offset": 128,
+              "size": 32,
+              "reset_value": 33583872,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "DATE": {
+                    "description": "register version.",
+                    "offset": 0,
+                    "size": 32
+                  }
+                }
+              }
+            }
+          }
+        }
+      },
+      "UHCI0": {
+        "description": "Universal Host Controller Interface",
+        "children": {
+          "registers": {
+            "CONF0": {
+              "description": "a",
+              "offset": 0,
+              "size": 32,
+              "reset_value": 1760,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "TX_RST": {
+                    "description": "Write 1, then write 0 to this bit to reset decode state machine.",
+                    "offset": 0,
+                    "size": 1
+                  },
+                  "RX_RST": {
+                    "description": "Write 1, then write 0 to this bit to reset encode state machine.",
+                    "offset": 1,
+                    "size": 1
+                  },
+                  "UART0_CE": {
+                    "description": "Set this bit to link up HCI and UART0.",
+                    "offset": 2,
+                    "size": 1
+                  },
+                  "UART1_CE": {
+                    "description": "Set this bit to link up HCI and UART1.",
+                    "offset": 3,
+                    "size": 1
+                  },
+                  "SEPER_EN": {
+                    "description": "Set this bit to separate the data frame using a special char.",
+                    "offset": 5,
+                    "size": 1
+                  },
+                  "HEAD_EN": {
+                    "description": "Set this bit to encode the data packet with a formatting header.",
+                    "offset": 6,
+                    "size": 1
+                  },
+                  "CRC_REC_EN": {
+                    "description": "Set this bit to enable UHCI to receive the 16 bit CRC.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "UART_IDLE_EOF_EN": {
+                    "description": "If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.",
+                    "offset": 8,
+                    "size": 1
+                  },
+                  "LEN_EOF_EN": {
+                    "description": "If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.",
+                    "offset": 9,
+                    "size": 1
+                  },
+                  "ENCODE_CRC_EN": {
+                    "description": "Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.",
+                    "offset": 10,
+                    "size": 1
+                  },
+                  "CLK_EN": {
+                    "description": "1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.",
+                    "offset": 11,
+                    "size": 1
+                  },
+                  "UART_RX_BRK_EOF_EN": {
+                    "description": "If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.",
+                    "offset": 12,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_RAW": {
+              "description": "a",
+              "offset": 4,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_START_INT_RAW": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_START_INT_RAW": {
+                    "description": "a",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_HUNG_INT_RAW": {
+                    "description": "a",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_HUNG_INT_RAW": {
+                    "description": "a",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SEND_S_REG_Q_INT_RAW": {
+                    "description": "a",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SEND_A_REG_Q_INT_RAW": {
+                    "description": "a",
+                    "offset": 5,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "OUT_EOF_INT_RAW": {
+                    "description": "This is the interrupt raw bit. Triggered when there are some errors in EOF in the",
+                    "offset": 6,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "APP_CTRL0_INT_RAW": {
+                    "description": "Soft control int raw bit.",
+                    "offset": 7,
+                    "size": 1
+                  },
+                  "APP_CTRL1_INT_RAW": {
+                    "description": "Soft control int raw bit.",
+                    "offset": 8,
+                    "size": 1
+                  }
+                }
+              }
+            },
+            "INT_ST": {
+              "description": "a",
+              "offset": 8,
+              "size": 32,
+              "reset_value": 0,
+              "reset_mask": 4294967295,
+              "children": {
+                "fields": {
+                  "RX_START_INT_ST": {
+                    "description": "a",
+                    "offset": 0,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_START_INT_ST": {
+                    "description": "a",
+                    "offset": 1,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "RX_HUNG_INT_ST": {
+                    "description": "a",
+                    "offset": 2,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "TX_HUNG_INT_ST": {
+                    "description": "a",
+                    "offset": 3,
+                    "size": 1,
+                    "access": "read-only"
+                  },
+                  "SEND_S_REG_Q_INT_ST": {
+                    "description": "a",
+                    "offset": 4,
+                    "size": 1,
+                    "access": "read-only"
+                  },
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+      "description": "32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)",
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+        "cpu.vendorSystickConfig": "false",
+        "cpu.revision": "r0p0",
+        "cpu.endian": "little",
+        "license": "\n    Copyright 2022 Espressif Systems (Shanghai) PTE LTD\n\n    Licensed under the Apache License, Version 2.0 (the \"License\");\n    you may not use this file except in compliance with the License.\n    You may obtain a copy of the License at\n\n        http://www.apache.org/licenses/LICENSE-2.0\n\n    Unless required by applicable law or agreed to in writing, software\n    distributed under the License is distributed on an \"AS IS\" BASIS,\n    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n    See the License for the specific language governing permissions and\n    limitations under the License.\n",
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+            "description": "Advanced Peripheral Bus Controller",
+            "offset": 1610768384,
+            "type": "types.peripherals.APB_CTRL"
+          },
+          "APB_SARADC": {
+            "description": "Successive Approximation Register Analog to Digital Converter",
+            "offset": 1610874880,
+            "type": "types.peripherals.APB_SARADC"
+          },
+          "ASSIST_DEBUG": {
+            "description": "Debug Assist",
+            "offset": 1611456512,
+            "type": "types.peripherals.ASSIST_DEBUG"
+          },
+          "DMA": {
+            "description": "DMA (Direct Memory Access) Controller",
+            "offset": 1610870784,
+            "type": "types.peripherals.DMA"
+          },
+          "DS": {
+            "description": "Digital Signature",
+            "offset": 1610862592,
+            "type": "types.peripherals.DS"
+          },
+          "EFUSE": {
+            "description": "eFuse Controller",
+            "offset": 1610647552,
+            "type": "types.peripherals.EFUSE"
+          },
+          "EXTMEM": {
+            "description": "External Memory",
+            "offset": 1611415552,
+            "type": "types.peripherals.EXTMEM"
+          },
+          "GPIO": {
+            "description": "General Purpose Input/Output",
+            "offset": 1610629120,
+            "type": "types.peripherals.GPIO"
+          },
+          "GPIOSD": {
+            "description": "Sigma-Delta Modulation",
+            "offset": 1610632960,
+            "type": "types.peripherals.GPIOSD"
+          },
+          "HMAC": {
+            "description": "HMAC (Hash-based Message Authentication Code) Accelerator",
+            "offset": 1610866688,
+            "type": "types.peripherals.HMAC"
+          },
+          "I2C0": {
+            "description": "I2C (Inter-Integrated Circuit) Controller",
+            "offset": 1610690560,
+            "type": "types.peripherals.I2C0"
+          },
+          "I2S": {
+            "description": "I2S (Inter-IC Sound) Controller",
+            "offset": 1610797056,
+            "type": "types.peripherals.I2S"
+          },
+          "INTERRUPT_CORE0": {
+            "description": "Interrupt Core",
+            "offset": 1611407360,
+            "type": "types.peripherals.INTERRUPT_CORE0"
+          },
+          "IO_MUX": {
+            "description": "Input/Output Multiplexer",
+            "offset": 1610649600,
+            "type": "types.peripherals.IO_MUX"
+          },
+          "LEDC": {
+            "description": "LED Control PWM (Pulse Width Modulation)",
+            "offset": 1610715136,
+            "type": "types.peripherals.LEDC"
+          },
+          "RMT": {
+            "description": "Remote Control Peripheral",
+            "offset": 1610702848,
+            "type": "types.peripherals.RMT"
+          },
+          "RNG": {
+            "description": "Hardware random number generator",
+            "offset": 1610768384,
+            "type": "types.peripherals.RNG"
+          },
+          "RSA": {
+            "description": "RSA (Rivest Shamir Adleman) Accelerator",
+            "offset": 1610858496,
+            "type": "types.peripherals.RSA"
+          },
+          "RTC_CNTL": {
+            "description": "Real-Time Clock Control",
+            "offset": 1610645504,
+            "type": "types.peripherals.RTC_CNTL"
+          },
+          "SENSITIVE": {
+            "description": "Sensitive",
+            "offset": 1611403264,
+            "type": "types.peripherals.SENSITIVE"
+          },
+          "SHA": {
+            "description": "SHA (Secure Hash Algorithm) Accelerator",
+            "offset": 1610854400,
+            "type": "types.peripherals.SHA"
+          },
+          "SPI0": {
+            "description": "SPI (Serial Peripheral Interface) Controller",
+            "offset": 1610625024,
+            "type": "types.peripherals.SPI0"
+          },
+          "SPI1": {
+            "description": "SPI (Serial Peripheral Interface) Controller",
+            "offset": 1610620928,
+            "type": "types.peripherals.SPI1"
+          },
+          "SPI2": {
+            "description": "SPI (Serial Peripheral Interface) Controller",
+            "offset": 1610760192,
+            "type": "types.peripherals.SPI2"
+          },
+          "SYSTEM": {
+            "description": "System",
+            "offset": 1611399168,
+            "type": "types.peripherals.SYSTEM"
+          },
+          "SYSTIMER": {
+            "description": "System Timer",
+            "offset": 1610756096,
+            "type": "types.peripherals.SYSTIMER"
+          },
+          "TIMG0": {
+            "description": "Timer Group",
+            "offset": 1610739712,
+            "type": "types.peripherals.TIMG0"
+          },
+          "TIMG1": {
+            "description": "Timer Group",
+            "offset": 1610743808,
+            "type": "types.peripherals.TIMG0"
+          },
+          "TWAI": {
+            "description": "Two-Wire Automotive Interface",
+            "offset": 1610788864,
+            "type": "types.peripherals.TWAI"
+          },
+          "UART0": {
+            "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
+            "offset": 1610612736,
+            "type": "types.peripherals.UART0"
+          },
+          "UART1": {
+            "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
+            "offset": 1610678272,
+            "type": "types.peripherals.UART0"
+          },
+          "UHCI0": {
+            "description": "Universal Host Controller Interface",
+            "offset": 1610694656,
+            "type": "types.peripherals.UHCI0"
+          },
+          "UHCI1": {
+            "description": "Universal Host Controller Interface",
+            "offset": 1610661888,
+            "type": "types.peripherals.UHCI0"
+          },
+          "USB_DEVICE": {
+            "description": "Full-speed USB Serial/JTAG Controller",
+            "offset": 1610887168,
+            "type": "types.peripherals.USB_DEVICE"
+          },
+          "XTS_AES": {
+            "description": "XTS-AES-128 Flash Encryption",
+            "offset": 1611448320,
+            "type": "types.peripherals.XTS_AES"
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
diff --git a/src/chips/ESP32_C3.zig b/src/chips/ESP32_C3.zig
new file mode 100644
index 000000000..50a326366
--- /dev/null
+++ b/src/chips/ESP32_C3.zig
@@ -0,0 +1,12378 @@
+const micro = @import("microzig");
+const mmio = micro.mmio;
+
+pub const devices = struct {
+    ///  32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
+    pub const @"ESP32-C3" = struct {
+        pub const properties = struct {
+            pub const @"cpu.mpuPresent" = "false";
+            pub const @"cpu.nvicPrioBits" = "4";
+            pub const @"cpu.vendorSystickConfig" = "false";
+            pub const @"cpu.revision" = "r0p0";
+            pub const @"cpu.endian" = "little";
+            pub const license =
+                \\
+                \\    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
+                \\
+                \\    Licensed under the Apache License, Version 2.0 (the "License");
+                \\    you may not use this file except in compliance with the License.
+                \\    You may obtain a copy of the License at
+                \\
+                \\        http://www.apache.org/licenses/LICENSE-2.0
+                \\
+                \\    Unless required by applicable law or agreed to in writing, software
+                \\    distributed under the License is distributed on an "AS IS" BASIS,
+                \\    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+                \\    See the License for the specific language governing permissions and
+                \\    limitations under the License.
+                \\
+            ;
+            pub const @"cpu.name" = "RV32IMC";
+            pub const @"cpu.fpuPresent" = "false";
+        };
+
+        pub const peripherals = struct {
+            ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
+            pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x60000000);
+            ///  SPI (Serial Peripheral Interface) Controller
+            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI1, 0x60002000);
+            ///  SPI (Serial Peripheral Interface) Controller
+            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x60003000);
+            ///  General Purpose Input/Output
+            pub const GPIO = @intToPtr(*volatile types.peripherals.GPIO, 0x60004000);
+            ///  Sigma-Delta Modulation
+            pub const GPIOSD = @intToPtr(*volatile types.peripherals.GPIOSD, 0x60004f00);
+            ///  Real-Time Clock Control
+            pub const RTC_CNTL = @intToPtr(*volatile types.peripherals.RTC_CNTL, 0x60008000);
+            ///  eFuse Controller
+            pub const EFUSE = @intToPtr(*volatile types.peripherals.EFUSE, 0x60008800);
+            ///  Input/Output Multiplexer
+            pub const IO_MUX = @intToPtr(*volatile types.peripherals.IO_MUX, 0x60009000);
+            ///  Universal Host Controller Interface
+            pub const UHCI1 = @intToPtr(*volatile types.peripherals.UHCI0, 0x6000c000);
+            ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
+            pub const UART1 = @intToPtr(*volatile types.peripherals.UART0, 0x60010000);
+            ///  I2C (Inter-Integrated Circuit) Controller
+            pub const I2C0 = @intToPtr(*volatile types.peripherals.I2C0, 0x60013000);
+            ///  Universal Host Controller Interface
+            pub const UHCI0 = @intToPtr(*volatile types.peripherals.UHCI0, 0x60014000);
+            ///  Remote Control Peripheral
+            pub const RMT = @intToPtr(*volatile types.peripherals.RMT, 0x60016000);
+            ///  LED Control PWM (Pulse Width Modulation)
+            pub const LEDC = @intToPtr(*volatile types.peripherals.LEDC, 0x60019000);
+            ///  Timer Group
+            pub const TIMG0 = @intToPtr(*volatile types.peripherals.TIMG0, 0x6001f000);
+            ///  Timer Group
+            pub const TIMG1 = @intToPtr(*volatile types.peripherals.TIMG0, 0x60020000);
+            ///  System Timer
+            pub const SYSTIMER = @intToPtr(*volatile types.peripherals.SYSTIMER, 0x60023000);
+            ///  SPI (Serial Peripheral Interface) Controller
+            pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI2, 0x60024000);
+            ///  Advanced Peripheral Bus Controller
+            pub const APB_CTRL = @intToPtr(*volatile types.peripherals.APB_CTRL, 0x60026000);
+            ///  Hardware random number generator
+            pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x60026000);
+            ///  Two-Wire Automotive Interface
+            pub const TWAI = @intToPtr(*volatile types.peripherals.TWAI, 0x6002b000);
+            ///  I2S (Inter-IC Sound) Controller
+            pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x6002d000);
+            ///  AES (Advanced Encryption Standard) Accelerator
+            pub const AES = @intToPtr(*volatile types.peripherals.AES, 0x6003a000);
+            ///  SHA (Secure Hash Algorithm) Accelerator
+            pub const SHA = @intToPtr(*volatile types.peripherals.SHA, 0x6003b000);
+            ///  RSA (Rivest Shamir Adleman) Accelerator
+            pub const RSA = @intToPtr(*volatile types.peripherals.RSA, 0x6003c000);
+            ///  Digital Signature
+            pub const DS = @intToPtr(*volatile types.peripherals.DS, 0x6003d000);
+            ///  HMAC (Hash-based Message Authentication Code) Accelerator
+            pub const HMAC = @intToPtr(*volatile types.peripherals.HMAC, 0x6003e000);
+            ///  DMA (Direct Memory Access) Controller
+            pub const DMA = @intToPtr(*volatile types.peripherals.DMA, 0x6003f000);
+            ///  Successive Approximation Register Analog to Digital Converter
+            pub const APB_SARADC = @intToPtr(*volatile types.peripherals.APB_SARADC, 0x60040000);
+            ///  Full-speed USB Serial/JTAG Controller
+            pub const USB_DEVICE = @intToPtr(*volatile types.peripherals.USB_DEVICE, 0x60043000);
+            ///  System
+            pub const SYSTEM = @intToPtr(*volatile types.peripherals.SYSTEM, 0x600c0000);
+            ///  Sensitive
+            pub const SENSITIVE = @intToPtr(*volatile types.peripherals.SENSITIVE, 0x600c1000);
+            ///  Interrupt Core
+            pub const INTERRUPT_CORE0 = @intToPtr(*volatile types.peripherals.INTERRUPT_CORE0, 0x600c2000);
+            ///  External Memory
+            pub const EXTMEM = @intToPtr(*volatile types.peripherals.EXTMEM, 0x600c4000);
+            ///  XTS-AES-128 Flash Encryption
+            pub const XTS_AES = @intToPtr(*volatile types.peripherals.XTS_AES, 0x600cc000);
+            ///  Debug Assist
+            pub const ASSIST_DEBUG = @intToPtr(*volatile types.peripherals.ASSIST_DEBUG, 0x600ce000);
+        };
+    };
+};
+
+pub const types = struct {
+    pub const peripherals = struct {
+        ///  AES (Advanced Encryption Standard) Accelerator
+        pub const AES = extern struct {
+            ///  Key material key_0 configure register
+            KEY_0: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_0 that is a part of key material.
+                KEY_0: u32,
+            }),
+            ///  Key material key_1 configure register
+            KEY_1: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_1 that is a part of key material.
+                KEY_1: u32,
+            }),
+            ///  Key material key_2 configure register
+            KEY_2: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_2 that is a part of key material.
+                KEY_2: u32,
+            }),
+            ///  Key material key_3 configure register
+            KEY_3: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_3 that is a part of key material.
+                KEY_3: u32,
+            }),
+            ///  Key material key_4 configure register
+            KEY_4: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_4 that is a part of key material.
+                KEY_4: u32,
+            }),
+            ///  Key material key_5 configure register
+            KEY_5: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_5 that is a part of key material.
+                KEY_5: u32,
+            }),
+            ///  Key material key_6 configure register
+            KEY_6: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_6 that is a part of key material.
+                KEY_6: u32,
+            }),
+            ///  Key material key_7 configure register
+            KEY_7: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores key_7 that is a part of key material.
+                KEY_7: u32,
+            }),
+            ///  source text material text_in_0 configure register
+            TEXT_IN_0: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_in_0 that is a part of source text material.
+                TEXT_IN_0: u32,
+            }),
+            ///  source text material text_in_1 configure register
+            TEXT_IN_1: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_in_1 that is a part of source text material.
+                TEXT_IN_1: u32,
+            }),
+            ///  source text material text_in_2 configure register
+            TEXT_IN_2: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_in_2 that is a part of source text material.
+                TEXT_IN_2: u32,
+            }),
+            ///  source text material text_in_3 configure register
+            TEXT_IN_3: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_in_3 that is a part of source text material.
+                TEXT_IN_3: u32,
+            }),
+            ///  result text material text_out_0 configure register
+            TEXT_OUT_0: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_out_0 that is a part of result text material.
+                TEXT_OUT_0: u32,
+            }),
+            ///  result text material text_out_1 configure register
+            TEXT_OUT_1: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_out_1 that is a part of result text material.
+                TEXT_OUT_1: u32,
+            }),
+            ///  result text material text_out_2 configure register
+            TEXT_OUT_2: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_out_2 that is a part of result text material.
+                TEXT_OUT_2: u32,
+            }),
+            ///  result text material text_out_3 configure register
+            TEXT_OUT_3: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores text_out_3 that is a part of result text material.
+                TEXT_OUT_3: u32,
+            }),
+            ///  AES Mode register
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
+                MODE: u3,
+                padding: u29,
+            }),
+            ///  AES Endian configure register
+            ENDIAN: mmio.Mmio(packed struct(u32) {
+                ///  endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian
+                ENDIAN: u6,
+                padding: u26,
+            }),
+            ///  AES trigger register
+            TRIGGER: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to start AES calculation.
+                TRIGGER: u1,
+                padding: u31,
+            }),
+            ///  AES state register
+            STATE: mmio.Mmio(packed struct(u32) {
+                ///  Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.
+                STATE: u2,
+                padding: u30,
+            }),
+            ///  The memory that stores initialization vector
+            IV_MEM: [16]u8,
+            ///  The memory that stores GCM hash subkey
+            H_MEM: [16]u8,
+            ///  The memory that stores J0
+            J0_MEM: [16]u8,
+            ///  The memory that stores T0
+            T0_MEM: [16]u8,
+            ///  DMA-AES working mode register
+            DMA_ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
+                DMA_ENABLE: u1,
+                padding: u31,
+            }),
+            ///  AES cipher block mode register
+            BLOCK_MODE: mmio.Mmio(packed struct(u32) {
+                ///  Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
+                BLOCK_MODE: u3,
+                padding: u29,
+            }),
+            ///  AES block number register
+            BLOCK_NUM: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores the number of Plaintext/ciphertext block.
+                BLOCK_NUM: u32,
+            }),
+            ///  Standard incrementing function configure register
+            INC_SEL: mmio.Mmio(packed struct(u32) {
+                ///  This bit decides the standard incrementing function. 0: INC32. 1: INC128.
+                INC_SEL: u1,
+                padding: u31,
+            }),
+            ///  Additional Authential Data block number register
+            AAD_BLOCK_NUM: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores the number of AAD block.
+                AAD_BLOCK_NUM: u32,
+            }),
+            ///  AES remainder bit number register
+            REMAINDER_BIT_NUM: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores the number of remainder bit.
+                REMAINDER_BIT_NUM: u7,
+                padding: u25,
+            }),
+            ///  AES continue register
+            CONTINUE: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to continue GCM operation.
+                CONTINUE: u1,
+                padding: u31,
+            }),
+            ///  AES Interrupt clear register
+            INT_CLEAR: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the AES interrupt.
+                INT_CLEAR: u1,
+                padding: u31,
+            }),
+            ///  AES Interrupt enable register
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
+                INT_ENA: u1,
+                padding: u31,
+            }),
+            ///  AES version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  This bits stores the version information of AES.
+                DATE: u30,
+                padding: u2,
+            }),
+            ///  AES-DMA exit config
+            DMA_EXIT: mmio.Mmio(packed struct(u32) {
+                ///  Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.
+                DMA_EXIT: u1,
+                padding: u31,
+            }),
+        };
+
+        ///  Advanced Peripheral Bus Controller
+        pub const APB_CTRL = extern struct {
+            ///  APB_CTRL_SYSCLK_CONF_REG
+            SYSCLK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_pre_div_cnt
+                PRE_DIV_CNT: u10,
+                ///  reg_clk_320m_en
+                CLK_320M_EN: u1,
+                ///  reg_clk_en
+                CLK_EN: u1,
+                ///  reg_rst_tick_cnt
+                RST_TICK_CNT: u1,
+                padding: u19,
+            }),
+            ///  APB_CTRL_TICK_CONF_REG
+            TICK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_xtal_tick_num
+                XTAL_TICK_NUM: u8,
+                ///  reg_ck8m_tick_num
+                CK8M_TICK_NUM: u8,
+                ///  reg_tick_enable
+                TICK_ENABLE: u1,
+                padding: u15,
+            }),
+            ///  APB_CTRL_CLK_OUT_EN_REG
+            CLK_OUT_EN: mmio.Mmio(packed struct(u32) {
+                ///  reg_clk20_oen
+                CLK20_OEN: u1,
+                ///  reg_clk22_oen
+                CLK22_OEN: u1,
+                ///  reg_clk44_oen
+                CLK44_OEN: u1,
+                ///  reg_clk_bb_oen
+                CLK_BB_OEN: u1,
+                ///  reg_clk80_oen
+                CLK80_OEN: u1,
+                ///  reg_clk160_oen
+                CLK160_OEN: u1,
+                ///  reg_clk_320m_oen
+                CLK_320M_OEN: u1,
+                ///  reg_clk_adc_inf_oen
+                CLK_ADC_INF_OEN: u1,
+                ///  reg_clk_dac_cpu_oen
+                CLK_DAC_CPU_OEN: u1,
+                ///  reg_clk40x_bb_oen
+                CLK40X_BB_OEN: u1,
+                ///  reg_clk_xtal_oen
+                CLK_XTAL_OEN: u1,
+                padding: u21,
+            }),
+            ///  APB_CTRL_WIFI_BB_CFG_REG
+            WIFI_BB_CFG: mmio.Mmio(packed struct(u32) {
+                ///  reg_wifi_bb_cfg
+                WIFI_BB_CFG: u32,
+            }),
+            ///  APB_CTRL_WIFI_BB_CFG_2_REG
+            WIFI_BB_CFG_2: mmio.Mmio(packed struct(u32) {
+                ///  reg_wifi_bb_cfg_2
+                WIFI_BB_CFG_2: u32,
+            }),
+            ///  APB_CTRL_WIFI_CLK_EN_REG
+            WIFI_CLK_EN: mmio.Mmio(packed struct(u32) {
+                ///  reg_wifi_clk_en
+                WIFI_CLK_EN: u32,
+            }),
+            ///  APB_CTRL_WIFI_RST_EN_REG
+            WIFI_RST_EN: mmio.Mmio(packed struct(u32) {
+                ///  reg_wifi_rst
+                WIFI_RST: u32,
+            }),
+            ///  APB_CTRL_HOST_INF_SEL_REG
+            HOST_INF_SEL: mmio.Mmio(packed struct(u32) {
+                ///  reg_peri_io_swap
+                PERI_IO_SWAP: u8,
+                padding: u24,
+            }),
+            ///  APB_CTRL_EXT_MEM_PMS_LOCK_REG
+            EXT_MEM_PMS_LOCK: mmio.Mmio(packed struct(u32) {
+                ///  reg_ext_mem_pms_lock
+                EXT_MEM_PMS_LOCK: u1,
+                padding: u31,
+            }),
+            reserved40: [4]u8,
+            ///  APB_CTRL_FLASH_ACE0_ATTR_REG
+            FLASH_ACE0_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace0_attr
+                FLASH_ACE0_ATTR: u2,
+                padding: u30,
+            }),
+            ///  APB_CTRL_FLASH_ACE1_ATTR_REG
+            FLASH_ACE1_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace1_attr
+                FLASH_ACE1_ATTR: u2,
+                padding: u30,
+            }),
+            ///  APB_CTRL_FLASH_ACE2_ATTR_REG
+            FLASH_ACE2_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace2_attr
+                FLASH_ACE2_ATTR: u2,
+                padding: u30,
+            }),
+            ///  APB_CTRL_FLASH_ACE3_ATTR_REG
+            FLASH_ACE3_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace3_attr
+                FLASH_ACE3_ATTR: u2,
+                padding: u30,
+            }),
+            ///  APB_CTRL_FLASH_ACE0_ADDR_REG
+            FLASH_ACE0_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace0_addr_s
+                S: u32,
+            }),
+            ///  APB_CTRL_FLASH_ACE1_ADDR_REG
+            FLASH_ACE1_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace1_addr_s
+                S: u32,
+            }),
+            ///  APB_CTRL_FLASH_ACE2_ADDR_REG
+            FLASH_ACE2_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace2_addr_s
+                S: u32,
+            }),
+            ///  APB_CTRL_FLASH_ACE3_ADDR_REG
+            FLASH_ACE3_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace3_addr_s
+                S: u32,
+            }),
+            ///  APB_CTRL_FLASH_ACE0_SIZE_REG
+            FLASH_ACE0_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace0_size
+                FLASH_ACE0_SIZE: u13,
+                padding: u19,
+            }),
+            ///  APB_CTRL_FLASH_ACE1_SIZE_REG
+            FLASH_ACE1_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace1_size
+                FLASH_ACE1_SIZE: u13,
+                padding: u19,
+            }),
+            ///  APB_CTRL_FLASH_ACE2_SIZE_REG
+            FLASH_ACE2_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace2_size
+                FLASH_ACE2_SIZE: u13,
+                padding: u19,
+            }),
+            ///  APB_CTRL_FLASH_ACE3_SIZE_REG
+            FLASH_ACE3_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  reg_flash_ace3_size
+                FLASH_ACE3_SIZE: u13,
+                padding: u19,
+            }),
+            reserved136: [48]u8,
+            ///  APB_CTRL_SPI_MEM_PMS_CTRL_REG
+            SPI_MEM_PMS_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_spi_mem_reject_int
+                SPI_MEM_REJECT_INT: u1,
+                ///  reg_spi_mem_reject_clr
+                SPI_MEM_REJECT_CLR: u1,
+                ///  reg_spi_mem_reject_cde
+                SPI_MEM_REJECT_CDE: u5,
+                padding: u25,
+            }),
+            ///  APB_CTRL_SPI_MEM_REJECT_ADDR_REG
+            SPI_MEM_REJECT_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_spi_mem_reject_addr
+                SPI_MEM_REJECT_ADDR: u32,
+            }),
+            ///  APB_CTRL_SDIO_CTRL_REG
+            SDIO_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_sdio_win_access_en
+                SDIO_WIN_ACCESS_EN: u1,
+                padding: u31,
+            }),
+            ///  APB_CTRL_REDCY_SIG0_REG
+            REDCY_SIG0: mmio.Mmio(packed struct(u32) {
+                ///  reg_redcy_sig0
+                REDCY_SIG0: u31,
+                ///  reg_redcy_andor
+                REDCY_ANDOR: u1,
+            }),
+            ///  APB_CTRL_REDCY_SIG1_REG
+            REDCY_SIG1: mmio.Mmio(packed struct(u32) {
+                ///  reg_redcy_sig1
+                REDCY_SIG1: u31,
+                ///  reg_redcy_nandor
+                REDCY_NANDOR: u1,
+            }),
+            ///  APB_CTRL_FRONT_END_MEM_PD_REG
+            FRONT_END_MEM_PD: mmio.Mmio(packed struct(u32) {
+                ///  reg_agc_mem_force_pu
+                AGC_MEM_FORCE_PU: u1,
+                ///  reg_agc_mem_force_pd
+                AGC_MEM_FORCE_PD: u1,
+                ///  reg_pbus_mem_force_pu
+                PBUS_MEM_FORCE_PU: u1,
+                ///  reg_pbus_mem_force_pd
+                PBUS_MEM_FORCE_PD: u1,
+                ///  reg_dc_mem_force_pu
+                DC_MEM_FORCE_PU: u1,
+                ///  reg_dc_mem_force_pd
+                DC_MEM_FORCE_PD: u1,
+                padding: u26,
+            }),
+            ///  APB_CTRL_RETENTION_CTRL_REG
+            RETENTION_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_retention_link_addr
+                RETENTION_LINK_ADDR: u27,
+                ///  reg_nobypass_cpu_iso_rst
+                NOBYPASS_CPU_ISO_RST: u1,
+                padding: u4,
+            }),
+            ///  APB_CTRL_CLKGATE_FORCE_ON_REG
+            CLKGATE_FORCE_ON: mmio.Mmio(packed struct(u32) {
+                ///  reg_rom_clkgate_force_on
+                ROM_CLKGATE_FORCE_ON: u2,
+                ///  reg_sram_clkgate_force_on
+                SRAM_CLKGATE_FORCE_ON: u4,
+                padding: u26,
+            }),
+            ///  APB_CTRL_MEM_POWER_DOWN_REG
+            MEM_POWER_DOWN: mmio.Mmio(packed struct(u32) {
+                ///  reg_rom_power_down
+                ROM_POWER_DOWN: u2,
+                ///  reg_sram_power_down
+                SRAM_POWER_DOWN: u4,
+                padding: u26,
+            }),
+            ///  APB_CTRL_MEM_POWER_UP_REG
+            MEM_POWER_UP: mmio.Mmio(packed struct(u32) {
+                ///  reg_rom_power_up
+                ROM_POWER_UP: u2,
+                ///  reg_sram_power_up
+                SRAM_POWER_UP: u4,
+                padding: u26,
+            }),
+            ///  APB_CTRL_RND_DATA_REG
+            RND_DATA: mmio.Mmio(packed struct(u32) {
+                ///  reg_rnd_data
+                RND_DATA: u32,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_CONFIG_REG
+            PERI_BACKUP_CONFIG: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  reg_peri_backup_flow_err
+                PERI_BACKUP_FLOW_ERR: u2,
+                reserved4: u1,
+                ///  reg_peri_backup_burst_limit
+                PERI_BACKUP_BURST_LIMIT: u5,
+                ///  reg_peri_backup_tout_thres
+                PERI_BACKUP_TOUT_THRES: u10,
+                ///  reg_peri_backup_size
+                PERI_BACKUP_SIZE: u10,
+                ///  reg_peri_backup_start
+                PERI_BACKUP_START: u1,
+                ///  reg_peri_backup_to_mem
+                PERI_BACKUP_TO_MEM: u1,
+                ///  reg_peri_backup_ena
+                PERI_BACKUP_ENA: u1,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_APB_ADDR_REG
+            PERI_BACKUP_APB_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_backup_apb_start_addr
+                BACKUP_APB_START_ADDR: u32,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_MEM_ADDR_REG
+            PERI_BACKUP_MEM_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_backup_mem_start_addr
+                BACKUP_MEM_START_ADDR: u32,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_INT_RAW_REG
+            PERI_BACKUP_INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  reg_peri_backup_done_int_raw
+                PERI_BACKUP_DONE_INT_RAW: u1,
+                ///  reg_peri_backup_err_int_raw
+                PERI_BACKUP_ERR_INT_RAW: u1,
+                padding: u30,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_INT_ST_REG
+            PERI_BACKUP_INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  reg_peri_backup_done_int_st
+                PERI_BACKUP_DONE_INT_ST: u1,
+                ///  reg_peri_backup_err_int_st
+                PERI_BACKUP_ERR_INT_ST: u1,
+                padding: u30,
+            }),
+            ///  APB_CTRL_PERI_BACKUP_INT_ENA_REG
+            PERI_BACKUP_INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  reg_peri_backup_done_int_ena
+                PERI_BACKUP_DONE_INT_ENA: u1,
+                ///  reg_peri_backup_err_int_ena
+                PERI_BACKUP_ERR_INT_ENA: u1,
+                padding: u30,
+            }),
+            reserved208: [4]u8,
+            ///  APB_CTRL_PERI_BACKUP_INT_CLR_REG
+            PERI_BACKUP_INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  reg_peri_backup_done_int_clr
+                PERI_BACKUP_DONE_INT_CLR: u1,
+                ///  reg_peri_backup_err_int_clr
+                PERI_BACKUP_ERR_INT_CLR: u1,
+                padding: u30,
+            }),
+            reserved1020: [808]u8,
+            ///  APB_CTRL_DATE_REG
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_dateVersion control
+                DATE: u32,
+            }),
+        };
+
+        ///  Successive Approximation Register Analog to Digital Converter
+        pub const APB_SARADC = extern struct {
+            ///  digital saradc configure register
+            CTRL: mmio.Mmio(packed struct(u32) {
+                ///  select software enable saradc sample
+                SARADC_START_FORCE: u1,
+                ///  software enable saradc sample
+                SARADC_START: u1,
+                reserved6: u4,
+                ///  SAR clock gated
+                SARADC_SAR_CLK_GATED: u1,
+                ///  SAR clock divider
+                SARADC_SAR_CLK_DIV: u8,
+                ///  0 ~ 15 means length 1 ~ 16
+                SARADC_SAR_PATT_LEN: u3,
+                reserved23: u5,
+                ///  clear the pointer of pattern table for DIG ADC1 CTRL
+                SARADC_SAR_PATT_P_CLEAR: u1,
+                reserved27: u3,
+                ///  force option to xpd sar blocks
+                SARADC_XPD_SAR_FORCE: u2,
+                reserved30: u1,
+                ///  wait arbit signal stable after sar_done
+                SARADC_WAIT_ARB_CYCLE: u2,
+            }),
+            ///  digital saradc configure register
+            CTRL2: mmio.Mmio(packed struct(u32) {
+                ///  enable max meas num
+                SARADC_MEAS_NUM_LIMIT: u1,
+                ///  max conversion number
+                SARADC_MAX_MEAS_NUM: u8,
+                ///  1: data to DIG ADC1 CTRL is inverted, otherwise not
+                SARADC_SAR1_INV: u1,
+                ///  1: data to DIG ADC2 CTRL is inverted, otherwise not
+                SARADC_SAR2_INV: u1,
+                reserved12: u1,
+                ///  to set saradc timer target
+                SARADC_TIMER_TARGET: u12,
+                ///  to enable saradc timer trigger
+                SARADC_TIMER_EN: u1,
+                padding: u7,
+            }),
+            ///  digital saradc configure register
+            FILTER_CTRL1: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  Factor of saradc filter1
+                APB_SARADC_FILTER_FACTOR1: u3,
+                ///  Factor of saradc filter0
+                APB_SARADC_FILTER_FACTOR0: u3,
+            }),
+            ///  digital saradc configure register
+            FSM_WAIT: mmio.Mmio(packed struct(u32) {
+                ///  saradc_xpd_wait
+                SARADC_XPD_WAIT: u8,
+                ///  saradc_rstb_wait
+                SARADC_RSTB_WAIT: u8,
+                ///  saradc_standby_wait
+                SARADC_STANDBY_WAIT: u8,
+                padding: u8,
+            }),
+            ///  digital saradc configure register
+            SAR1_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  saradc1 status about data and channel
+                SARADC_SAR1_STATUS: u32,
+            }),
+            ///  digital saradc configure register
+            SAR2_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  saradc2 status about data and channel
+                SARADC_SAR2_STATUS: u32,
+            }),
+            ///  digital saradc configure register
+            SAR_PATT_TAB1: mmio.Mmio(packed struct(u32) {
+                ///  item 0 ~ 3 for pattern table 1 (each item one byte)
+                SARADC_SAR_PATT_TAB1: u24,
+                padding: u8,
+            }),
+            ///  digital saradc configure register
+            SAR_PATT_TAB2: mmio.Mmio(packed struct(u32) {
+                ///  Item 4 ~ 7 for pattern table 1 (each item one byte)
+                SARADC_SAR_PATT_TAB2: u24,
+                padding: u8,
+            }),
+            ///  digital saradc configure register
+            ONETIME_SAMPLE: mmio.Mmio(packed struct(u32) {
+                reserved23: u23,
+                ///  configure onetime atten
+                SARADC_ONETIME_ATTEN: u2,
+                ///  configure onetime channel
+                SARADC_ONETIME_CHANNEL: u4,
+                ///  trigger adc onetime sample
+                SARADC_ONETIME_START: u1,
+                ///  enable adc2 onetime sample
+                SARADC2_ONETIME_SAMPLE: u1,
+                ///  enable adc1 onetime sample
+                SARADC1_ONETIME_SAMPLE: u1,
+            }),
+            ///  digital saradc configure register
+            ARB_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  adc2 arbiter force to enableapb controller
+                ADC_ARB_APB_FORCE: u1,
+                ///  adc2 arbiter force to enable rtc controller
+                ADC_ARB_RTC_FORCE: u1,
+                ///  adc2 arbiter force to enable wifi controller
+                ADC_ARB_WIFI_FORCE: u1,
+                ///  adc2 arbiter force grant
+                ADC_ARB_GRANT_FORCE: u1,
+                ///  Set adc2 arbiterapb priority
+                ADC_ARB_APB_PRIORITY: u2,
+                ///  Set adc2 arbiter rtc priority
+                ADC_ARB_RTC_PRIORITY: u2,
+                ///  Set adc2 arbiter wifi priority
+                ADC_ARB_WIFI_PRIORITY: u2,
+                ///  adc2 arbiter uses fixed priority
+                ADC_ARB_FIX_PRIORITY: u1,
+                padding: u19,
+            }),
+            ///  digital saradc configure register
+            FILTER_CTRL0: mmio.Mmio(packed struct(u32) {
+                reserved18: u18,
+                ///  configure filter1 to adc channel
+                APB_SARADC_FILTER_CHANNEL1: u4,
+                ///  configure filter0 to adc channel
+                APB_SARADC_FILTER_CHANNEL0: u4,
+                reserved31: u5,
+                ///  enable apb_adc1_filter
+                APB_SARADC_FILTER_RESET: u1,
+            }),
+            ///  digital saradc configure register
+            SAR1DATA_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  saradc1 data
+                APB_SARADC1_DATA: u17,
+                padding: u15,
+            }),
+            ///  digital saradc configure register
+            SAR2DATA_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  saradc2 data
+                APB_SARADC2_DATA: u17,
+                padding: u15,
+            }),
+            ///  digital saradc configure register
+            THRES0_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  configure thres0 to adc channel
+                APB_SARADC_THRES0_CHANNEL: u4,
+                reserved5: u1,
+                ///  saradc thres0 monitor thres
+                APB_SARADC_THRES0_HIGH: u13,
+                ///  saradc thres0 monitor thres
+                APB_SARADC_THRES0_LOW: u13,
+                padding: u1,
+            }),
+            ///  digital saradc configure register
+            THRES1_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  configure thres1 to adc channel
+                APB_SARADC_THRES1_CHANNEL: u4,
+                reserved5: u1,
+                ///  saradc thres1 monitor thres
+                APB_SARADC_THRES1_HIGH: u13,
+                ///  saradc thres1 monitor thres
+                APB_SARADC_THRES1_LOW: u13,
+                padding: u1,
+            }),
+            ///  digital saradc configure register
+            THRES_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved27: u27,
+                ///  enable thres to all channel
+                APB_SARADC_THRES_ALL_EN: u1,
+                reserved30: u2,
+                ///  enable thres1
+                APB_SARADC_THRES1_EN: u1,
+                ///  enable thres0
+                APB_SARADC_THRES0_EN: u1,
+            }),
+            ///  digital saradc int register
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  saradc thres1 low interrupt enable
+                APB_SARADC_THRES1_LOW_INT_ENA: u1,
+                ///  saradc thres0 low interrupt enable
+                APB_SARADC_THRES0_LOW_INT_ENA: u1,
+                ///  saradc thres1 high interrupt enable
+                APB_SARADC_THRES1_HIGH_INT_ENA: u1,
+                ///  saradc thres0 high interrupt enable
+                APB_SARADC_THRES0_HIGH_INT_ENA: u1,
+                ///  saradc2 done interrupt enable
+                APB_SARADC2_DONE_INT_ENA: u1,
+                ///  saradc1 done interrupt enable
+                APB_SARADC1_DONE_INT_ENA: u1,
+            }),
+            ///  digital saradc int register
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  saradc thres1 low interrupt raw
+                APB_SARADC_THRES1_LOW_INT_RAW: u1,
+                ///  saradc thres0 low interrupt raw
+                APB_SARADC_THRES0_LOW_INT_RAW: u1,
+                ///  saradc thres1 high interrupt raw
+                APB_SARADC_THRES1_HIGH_INT_RAW: u1,
+                ///  saradc thres0 high interrupt raw
+                APB_SARADC_THRES0_HIGH_INT_RAW: u1,
+                ///  saradc2 done interrupt raw
+                APB_SARADC2_DONE_INT_RAW: u1,
+                ///  saradc1 done interrupt raw
+                APB_SARADC1_DONE_INT_RAW: u1,
+            }),
+            ///  digital saradc int register
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  saradc thres1 low interrupt state
+                APB_SARADC_THRES1_LOW_INT_ST: u1,
+                ///  saradc thres0 low interrupt state
+                APB_SARADC_THRES0_LOW_INT_ST: u1,
+                ///  saradc thres1 high interrupt state
+                APB_SARADC_THRES1_HIGH_INT_ST: u1,
+                ///  saradc thres0 high interrupt state
+                APB_SARADC_THRES0_HIGH_INT_ST: u1,
+                ///  saradc2 done interrupt state
+                APB_SARADC2_DONE_INT_ST: u1,
+                ///  saradc1 done interrupt state
+                APB_SARADC1_DONE_INT_ST: u1,
+            }),
+            ///  digital saradc int register
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  saradc thres1 low interrupt clear
+                APB_SARADC_THRES1_LOW_INT_CLR: u1,
+                ///  saradc thres0 low interrupt clear
+                APB_SARADC_THRES0_LOW_INT_CLR: u1,
+                ///  saradc thres1 high interrupt clear
+                APB_SARADC_THRES1_HIGH_INT_CLR: u1,
+                ///  saradc thres0 high interrupt clear
+                APB_SARADC_THRES0_HIGH_INT_CLR: u1,
+                ///  saradc2 done interrupt clear
+                APB_SARADC2_DONE_INT_CLR: u1,
+                ///  saradc1 done interrupt clear
+                APB_SARADC1_DONE_INT_CLR: u1,
+            }),
+            ///  digital saradc configure register
+            DMA_CONF: mmio.Mmio(packed struct(u32) {
+                ///  the dma_in_suc_eof gen when sample cnt = spi_eof_num
+                APB_ADC_EOF_NUM: u16,
+                reserved30: u14,
+                ///  reset_apb_adc_state
+                APB_ADC_RESET_FSM: u1,
+                ///  enable apb_adc use spi_dma
+                APB_ADC_TRANS: u1,
+            }),
+            ///  digital saradc configure register
+            CLKM_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Integral I2S clock divider value
+                CLKM_DIV_NUM: u8,
+                ///  Fractional clock divider numerator value
+                CLKM_DIV_B: u6,
+                ///  Fractional clock divider denominator value
+                CLKM_DIV_A: u6,
+                ///  reg clk en
+                CLK_EN: u1,
+                ///  Set this bit to enable clk_apll
+                CLK_SEL: u2,
+                padding: u9,
+            }),
+            ///  digital tsens configure register
+            APB_TSENS_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  temperature sensor data out
+                TSENS_OUT: u8,
+                reserved13: u5,
+                ///  invert temperature sensor data
+                TSENS_IN_INV: u1,
+                ///  temperature sensor clock divider
+                TSENS_CLK_DIV: u8,
+                ///  temperature sensor power up
+                TSENS_PU: u1,
+                padding: u9,
+            }),
+            ///  digital tsens configure register
+            TSENS_CTRL2: mmio.Mmio(packed struct(u32) {
+                ///  the time that power up tsens need wait
+                TSENS_XPD_WAIT: u12,
+                ///  force power up tsens
+                TSENS_XPD_FORCE: u2,
+                ///  inv tsens clk
+                TSENS_CLK_INV: u1,
+                ///  tsens clk select
+                TSENS_CLK_SEL: u1,
+                padding: u16,
+            }),
+            ///  digital saradc configure register
+            CALI: mmio.Mmio(packed struct(u32) {
+                ///  saradc cali factor
+                APB_SARADC_CALI_CFG: u17,
+                padding: u15,
+            }),
+            reserved1020: [920]u8,
+            ///  version
+            CTRL_DATE: mmio.Mmio(packed struct(u32) {
+                ///  version
+                DATE: u32,
+            }),
+        };
+
+        ///  Debug Assist
+        pub const ASSIST_DEBUG = extern struct {
+            ///  ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG
+            C0RE_0_MONTR_ENA: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_rd_ena
+                CORE_0_AREA_DRAM0_0_RD_ENA: u1,
+                ///  reg_core_0_area_dram0_0_wr_ena
+                CORE_0_AREA_DRAM0_0_WR_ENA: u1,
+                ///  reg_core_0_area_dram0_1_rd_ena
+                CORE_0_AREA_DRAM0_1_RD_ENA: u1,
+                ///  reg_core_0_area_dram0_1_wr_ena
+                CORE_0_AREA_DRAM0_1_WR_ENA: u1,
+                ///  reg_core_0_area_pif_0_rd_ena
+                CORE_0_AREA_PIF_0_RD_ENA: u1,
+                ///  reg_core_0_area_pif_0_wr_ena
+                CORE_0_AREA_PIF_0_WR_ENA: u1,
+                ///  reg_core_0_area_pif_1_rd_ena
+                CORE_0_AREA_PIF_1_RD_ENA: u1,
+                ///  reg_core_0_area_pif_1_wr_ena
+                CORE_0_AREA_PIF_1_WR_ENA: u1,
+                ///  reg_core_0_sp_spill_min_ena
+                CORE_0_SP_SPILL_MIN_ENA: u1,
+                ///  reg_core_0_sp_spill_max_ena
+                CORE_0_SP_SPILL_MAX_ENA: u1,
+                ///  reg_core_0_iram0_exception_monitor_ena
+                CORE_0_IRAM0_EXCEPTION_MONITOR_ENA: u1,
+                ///  reg_core_0_dram0_exception_monitor_ena
+                CORE_0_DRAM0_EXCEPTION_MONITOR_ENA: u1,
+                padding: u20,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_INTR_RAW_REG
+            CORE_0_INTR_RAW: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_rd_raw
+                CORE_0_AREA_DRAM0_0_RD_RAW: u1,
+                ///  reg_core_0_area_dram0_0_wr_raw
+                CORE_0_AREA_DRAM0_0_WR_RAW: u1,
+                ///  reg_core_0_area_dram0_1_rd_raw
+                CORE_0_AREA_DRAM0_1_RD_RAW: u1,
+                ///  reg_core_0_area_dram0_1_wr_raw
+                CORE_0_AREA_DRAM0_1_WR_RAW: u1,
+                ///  reg_core_0_area_pif_0_rd_raw
+                CORE_0_AREA_PIF_0_RD_RAW: u1,
+                ///  reg_core_0_area_pif_0_wr_raw
+                CORE_0_AREA_PIF_0_WR_RAW: u1,
+                ///  reg_core_0_area_pif_1_rd_raw
+                CORE_0_AREA_PIF_1_RD_RAW: u1,
+                ///  reg_core_0_area_pif_1_wr_raw
+                CORE_0_AREA_PIF_1_WR_RAW: u1,
+                ///  reg_core_0_sp_spill_min_raw
+                CORE_0_SP_SPILL_MIN_RAW: u1,
+                ///  reg_core_0_sp_spill_max_raw
+                CORE_0_SP_SPILL_MAX_RAW: u1,
+                ///  reg_core_0_iram0_exception_monitor_raw
+                CORE_0_IRAM0_EXCEPTION_MONITOR_RAW: u1,
+                ///  reg_core_0_dram0_exception_monitor_raw
+                CORE_0_DRAM0_EXCEPTION_MONITOR_RAW: u1,
+                padding: u20,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_INTR_ENA_REG
+            CORE_0_INTR_ENA: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_rd_intr_ena
+                CORE_0_AREA_DRAM0_0_RD_INTR_ENA: u1,
+                ///  reg_core_0_area_dram0_0_wr_intr_ena
+                CORE_0_AREA_DRAM0_0_WR_INTR_ENA: u1,
+                ///  reg_core_0_area_dram0_1_rd_intr_ena
+                CORE_0_AREA_DRAM0_1_RD_INTR_ENA: u1,
+                ///  reg_core_0_area_dram0_1_wr_intr_ena
+                CORE_0_AREA_DRAM0_1_WR_INTR_ENA: u1,
+                ///  reg_core_0_area_pif_0_rd_intr_ena
+                CORE_0_AREA_PIF_0_RD_INTR_ENA: u1,
+                ///  reg_core_0_area_pif_0_wr_intr_ena
+                CORE_0_AREA_PIF_0_WR_INTR_ENA: u1,
+                ///  reg_core_0_area_pif_1_rd_intr_ena
+                CORE_0_AREA_PIF_1_RD_INTR_ENA: u1,
+                ///  reg_core_0_area_pif_1_wr_intr_ena
+                CORE_0_AREA_PIF_1_WR_INTR_ENA: u1,
+                ///  reg_core_0_sp_spill_min_intr_ena
+                CORE_0_SP_SPILL_MIN_INTR_ENA: u1,
+                ///  reg_core_0_sp_spill_max_intr_ena
+                CORE_0_SP_SPILL_MAX_INTR_ENA: u1,
+                ///  reg_core_0_iram0_exception_monitor_ena
+                CORE_0_IRAM0_EXCEPTION_MONITOR_RLS: u1,
+                ///  reg_core_0_dram0_exception_monitor_ena
+                CORE_0_DRAM0_EXCEPTION_MONITOR_RLS: u1,
+                padding: u20,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_INTR_CLR_REG
+            CORE_0_INTR_CLR: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_rd_clr
+                CORE_0_AREA_DRAM0_0_RD_CLR: u1,
+                ///  reg_core_0_area_dram0_0_wr_clr
+                CORE_0_AREA_DRAM0_0_WR_CLR: u1,
+                ///  reg_core_0_area_dram0_1_rd_clr
+                CORE_0_AREA_DRAM0_1_RD_CLR: u1,
+                ///  reg_core_0_area_dram0_1_wr_clr
+                CORE_0_AREA_DRAM0_1_WR_CLR: u1,
+                ///  reg_core_0_area_pif_0_rd_clr
+                CORE_0_AREA_PIF_0_RD_CLR: u1,
+                ///  reg_core_0_area_pif_0_wr_clr
+                CORE_0_AREA_PIF_0_WR_CLR: u1,
+                ///  reg_core_0_area_pif_1_rd_clr
+                CORE_0_AREA_PIF_1_RD_CLR: u1,
+                ///  reg_core_0_area_pif_1_wr_clr
+                CORE_0_AREA_PIF_1_WR_CLR: u1,
+                ///  reg_core_0_sp_spill_min_clr
+                CORE_0_SP_SPILL_MIN_CLR: u1,
+                ///  reg_core_0_sp_spill_max_clr
+                CORE_0_SP_SPILL_MAX_CLR: u1,
+                ///  reg_core_0_iram0_exception_monitor_clr
+                CORE_0_IRAM0_EXCEPTION_MONITOR_CLR: u1,
+                ///  reg_core_0_dram0_exception_monitor_clr
+                CORE_0_DRAM0_EXCEPTION_MONITOR_CLR: u1,
+                padding: u20,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG
+            CORE_0_AREA_DRAM0_0_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_min
+                CORE_0_AREA_DRAM0_0_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG
+            CORE_0_AREA_DRAM0_0_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_0_max
+                CORE_0_AREA_DRAM0_0_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG
+            CORE_0_AREA_DRAM0_1_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_1_min
+                CORE_0_AREA_DRAM0_1_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG
+            CORE_0_AREA_DRAM0_1_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_dram0_1_max
+                CORE_0_AREA_DRAM0_1_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG
+            CORE_0_AREA_PIF_0_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_pif_0_min
+                CORE_0_AREA_PIF_0_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG
+            CORE_0_AREA_PIF_0_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_pif_0_max
+                CORE_0_AREA_PIF_0_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG
+            CORE_0_AREA_PIF_1_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_pif_1_min
+                CORE_0_AREA_PIF_1_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG
+            CORE_0_AREA_PIF_1_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_pif_1_max
+                CORE_0_AREA_PIF_1_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_PC_REG
+            CORE_0_AREA_PC: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_pc
+                CORE_0_AREA_PC: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_AREA_SP_REG
+            CORE_0_AREA_SP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_area_sp
+                CORE_0_AREA_SP: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_SP_MIN_REG
+            CORE_0_SP_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_sp_min
+                CORE_0_SP_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_SP_MAX_REG
+            CORE_0_SP_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_sp_max
+                CORE_0_SP_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_SP_PC_REG
+            CORE_0_SP_PC: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_sp_pc
+                CORE_0_SP_PC: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_RCD_EN_REG
+            CORE_0_RCD_EN: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_rcd_recorden
+                CORE_0_RCD_RECORDEN: u1,
+                ///  reg_core_0_rcd_pdebugen
+                CORE_0_RCD_PDEBUGEN: u1,
+                padding: u30,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG
+            CORE_0_RCD_PDEBUGPC: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_rcd_pdebugpc
+                CORE_0_RCD_PDEBUGPC: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+            CORE_0_RCD_PDEBUGSP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_rcd_pdebugsp
+                CORE_0_RCD_PDEBUGSP: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
+            CORE_0_IRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_iram0_recording_addr_0
+                CORE_0_IRAM0_RECORDING_ADDR_0: u24,
+                ///  reg_core_0_iram0_recording_wr_0
+                CORE_0_IRAM0_RECORDING_WR_0: u1,
+                ///  reg_core_0_iram0_recording_loadstore_0
+                CORE_0_IRAM0_RECORDING_LOADSTORE_0: u1,
+                padding: u6,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG
+            CORE_0_IRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_iram0_recording_addr_1
+                CORE_0_IRAM0_RECORDING_ADDR_1: u24,
+                ///  reg_core_0_iram0_recording_wr_1
+                CORE_0_IRAM0_RECORDING_WR_1: u1,
+                ///  reg_core_0_iram0_recording_loadstore_1
+                CORE_0_IRAM0_RECORDING_LOADSTORE_1: u1,
+                padding: u6,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG
+            CORE_0_DRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_dram0_recording_addr_0
+                CORE_0_DRAM0_RECORDING_ADDR_0: u24,
+                ///  reg_core_0_dram0_recording_wr_0
+                CORE_0_DRAM0_RECORDING_WR_0: u1,
+                ///  reg_core_0_dram0_recording_byteen_0
+                CORE_0_DRAM0_RECORDING_BYTEEN_0: u4,
+                padding: u3,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+            CORE_0_DRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_dram0_recording_pc_0
+                CORE_0_DRAM0_RECORDING_PC_0: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
+            CORE_0_DRAM0_EXCEPTION_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_dram0_recording_addr_1
+                CORE_0_DRAM0_RECORDING_ADDR_1: u24,
+                ///  reg_core_0_dram0_recording_wr_1
+                CORE_0_DRAM0_RECORDING_WR_1: u1,
+                ///  reg_core_0_dram0_recording_byteen_1
+                CORE_0_DRAM0_RECORDING_BYTEEN_1: u4,
+                padding: u3,
+            }),
+            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG
+            CORE_0_DRAM0_EXCEPTION_MONITOR_3: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_dram0_recording_pc_1
+                CORE_0_DRAM0_RECORDING_PC_1: u32,
+            }),
+            ///  ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG
+            CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_x_iram0_dram0_limit_cycle_0
+                CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0: u20,
+                padding: u12,
+            }),
+            ///  ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG
+            CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_x_iram0_dram0_limit_cycle_1
+                CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1: u20,
+                padding: u12,
+            }),
+            ///  ASSIST_DEBUG_LOG_SETTING
+            LOG_SETTING: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_ena
+                LOG_ENA: u3,
+                ///  reg_log_mode
+                LOG_MODE: u4,
+                ///  reg_log_mem_loop_enable
+                LOG_MEM_LOOP_ENABLE: u1,
+                padding: u24,
+            }),
+            ///  ASSIST_DEBUG_LOG_DATA_0_REG
+            LOG_DATA_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_data_0
+                LOG_DATA_0: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_DATA_MASK_REG
+            LOG_DATA_MASK: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_data_size
+                LOG_DATA_SIZE: u16,
+                padding: u16,
+            }),
+            ///  ASSIST_DEBUG_LOG_MIN_REG
+            LOG_MIN: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_min
+                LOG_MIN: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_MAX_REG
+            LOG_MAX: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_max
+                LOG_MAX: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_MEM_START_REG
+            LOG_MEM_START: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_mem_start
+                LOG_MEM_START: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_MEM_END_REG
+            LOG_MEM_END: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_mem_end
+                LOG_MEM_END: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG
+            LOG_MEM_WRITING_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_mem_writing_addr
+                LOG_MEM_WRITING_ADDR: u32,
+            }),
+            ///  ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG
+            LOG_MEM_FULL_FLAG: mmio.Mmio(packed struct(u32) {
+                ///  reg_log_mem_full_flag
+                LOG_MEM_FULL_FLAG: u1,
+                ///  reg_clr_log_mem_full_flag
+                CLR_LOG_MEM_FULL_FLAG: u1,
+                padding: u30,
+            }),
+            ///  ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION
+            C0RE_0_LASTPC_BEFORE_EXCEPTION: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_lastpc_before_exc
+                CORE_0_LASTPC_BEFORE_EXC: u32,
+            }),
+            ///  ASSIST_DEBUG_C0RE_0_DEBUG_MODE
+            C0RE_0_DEBUG_MODE: mmio.Mmio(packed struct(u32) {
+                ///  reg_core_0_debug_mode
+                CORE_0_DEBUG_MODE: u1,
+                ///  reg_core_0_debug_module_active
+                CORE_0_DEBUG_MODULE_ACTIVE: u1,
+                padding: u30,
+            }),
+            reserved508: [352]u8,
+            ///  ASSIST_DEBUG_DATE_REG
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_assist_debug_date
+                ASSIST_DEBUG_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  DMA (Direct Memory Access) Controller
+        pub const DMA = extern struct {
+            ///  DMA_INT_RAW_CH0_REG.
+            INT_RAW_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.
+                IN_DONE_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.
+                IN_SUC_EOF_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.
+                IN_ERR_EOF_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.
+                OUT_DONE_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.
+                OUT_EOF_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.
+                IN_DSCR_ERR_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.
+                OUT_DSCR_ERR_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.
+                IN_DSCR_EMPTY_CH0_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.
+                OUT_TOTAL_EOF_CH0_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.
+                INFIFO_OVF_CH0_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.
+                INFIFO_UDF_CH0_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.
+                OUTFIFO_OVF_CH0_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.
+                OUTFIFO_UDF_CH0_INT_RAW: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ST_CH0_REG.
+            INT_ST_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH0_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH0_INT_ST: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ENA_CH0_REG.
+            INT_ENA_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH0_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH0_INT_ENA: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_CLR_CH0_REG.
+            INT_CLR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH0_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH0_INT_CLR: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_RAW_CH1_REG.
+            INT_RAW_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.
+                IN_DONE_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.
+                IN_SUC_EOF_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.
+                IN_ERR_EOF_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.
+                OUT_DONE_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.
+                OUT_EOF_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.
+                IN_DSCR_ERR_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.
+                OUT_DSCR_ERR_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.
+                IN_DSCR_EMPTY_CH1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.
+                OUT_TOTAL_EOF_CH1_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.
+                INFIFO_OVF_CH1_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.
+                INFIFO_UDF_CH1_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.
+                OUTFIFO_OVF_CH1_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.
+                OUTFIFO_UDF_CH1_INT_RAW: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ST_CH1_REG.
+            INT_ST_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH1_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH1_INT_ST: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ENA_CH1_REG.
+            INT_ENA_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH1_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH1_INT_ENA: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_CLR_CH1_REG.
+            INT_CLR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH1_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH1_INT_CLR: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_RAW_CH2_REG.
+            INT_RAW_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.
+                IN_DONE_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.
+                IN_SUC_EOF_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved.
+                IN_ERR_EOF_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.
+                OUT_DONE_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.
+                OUT_EOF_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2.
+                IN_DSCR_ERR_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2.
+                OUT_DSCR_ERR_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2.
+                IN_DSCR_EMPTY_CH2_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.
+                OUT_TOTAL_EOF_CH2_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.
+                INFIFO_OVF_CH2_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.
+                INFIFO_UDF_CH2_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.
+                OUTFIFO_OVF_CH2_INT_RAW: u1,
+                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.
+                OUTFIFO_UDF_CH2_INT_RAW: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ST_CH2_REG.
+            INT_ST_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH2_INT_ST: u1,
+                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH2_INT_ST: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_ENA_CH2_REG.
+            INT_ENA_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH2_INT_ENA: u1,
+                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH2_INT_ENA: u1,
+                padding: u19,
+            }),
+            ///  DMA_INT_CLR_CH2_REG.
+            INT_CLR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
+                IN_DONE_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
+                IN_SUC_EOF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
+                IN_ERR_EOF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
+                OUT_DONE_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
+                OUT_EOF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
+                IN_DSCR_ERR_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
+                OUT_DSCR_ERR_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
+                IN_DSCR_EMPTY_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
+                OUT_TOTAL_EOF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
+                INFIFO_OVF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
+                INFIFO_UDF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
+                OUTFIFO_OVF_CH2_INT_CLR: u1,
+                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
+                OUTFIFO_UDF_CH2_INT_CLR: u1,
+                padding: u19,
+            }),
+            reserved64: [16]u8,
+            ///  DMA_AHB_TEST_REG.
+            AHB_TEST: mmio.Mmio(packed struct(u32) {
+                ///  reserved
+                AHB_TESTMODE: u3,
+                reserved4: u1,
+                ///  reserved
+                AHB_TESTADDR: u2,
+                padding: u26,
+            }),
+            ///  DMA_MISC_CONF_REG.
+            MISC_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit, then clear this bit to reset the internal ahb FSM.
+                AHBM_RST_INTER: u1,
+                reserved2: u1,
+                ///  Set this bit to disable priority arbitration function.
+                ARB_PRI_DIS: u1,
+                ///  reg_clk_en
+                CLK_EN: u1,
+                padding: u28,
+            }),
+            ///  DMA_DATE_REG.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  register version.
+                DATE: u32,
+            }),
+            reserved112: [36]u8,
+            ///  DMA_IN_CONF0_CH0_REG.
+            IN_CONF0_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
+                IN_RST_CH0: u1,
+                ///  reserved
+                IN_LOOP_TEST_CH0: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.
+                INDSCR_BURST_EN_CH0: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.
+                IN_DATA_BURST_EN_CH0: u1,
+                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+                MEM_TRANS_EN_CH0: u1,
+                padding: u27,
+            }),
+            ///  DMA_IN_CONF1_CH0_REG.
+            IN_CONF1_CH0: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                IN_CHECK_OWNER_CH0: u1,
+                padding: u19,
+            }),
+            ///  DMA_INFIFO_STATUS_CH0_REG.
+            INFIFO_STATUS_CH0: mmio.Mmio(packed struct(u32) {
+                ///  L1 Rx FIFO full signal for Rx channel 0.
+                INFIFO_FULL_CH0: u1,
+                ///  L1 Rx FIFO empty signal for Rx channel 0.
+                INFIFO_EMPTY_CH0: u1,
+                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
+                INFIFO_CNT_CH0: u6,
+                reserved23: u15,
+                ///  reserved
+                IN_REMAIN_UNDER_1B_CH0: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_2B_CH0: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_3B_CH0: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_4B_CH0: u1,
+                ///  reserved
+                IN_BUF_HUNGRY_CH0: u1,
+                padding: u4,
+            }),
+            ///  DMA_IN_POP_CH0_REG.
+            IN_POP_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data popping from DMA FIFO.
+                INFIFO_RDATA_CH0: u12,
+                ///  Set this bit to pop data from DMA FIFO.
+                INFIFO_POP_CH0: u1,
+                padding: u19,
+            }),
+            ///  DMA_IN_LINK_CH0_REG.
+            IN_LINK_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
+                INLINK_ADDR_CH0: u20,
+                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+                INLINK_AUTO_RET_CH0: u1,
+                ///  Set this bit to stop dealing with the inlink descriptors.
+                INLINK_STOP_CH0: u1,
+                ///  Set this bit to start dealing with the inlink descriptors.
+                INLINK_START_CH0: u1,
+                ///  Set this bit to mount a new inlink descriptor.
+                INLINK_RESTART_CH0: u1,
+                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
+                INLINK_PARK_CH0: u1,
+                padding: u7,
+            }),
+            ///  DMA_IN_STATE_CH0_REG.
+            IN_STATE_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current inlink descriptor's address.
+                INLINK_DSCR_ADDR_CH0: u18,
+                ///  reserved
+                IN_DSCR_STATE_CH0: u2,
+                ///  reserved
+                IN_STATE_CH0: u3,
+                padding: u9,
+            }),
+            ///  DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
+            IN_SUC_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+                IN_SUC_EOF_DES_ADDR_CH0: u32,
+            }),
+            ///  DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
+            IN_ERR_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+                IN_ERR_EOF_DES_ADDR_CH0: u32,
+            }),
+            ///  DMA_IN_DSCR_CH0_REG.
+            IN_DSCR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current inlink descriptor x.
+                INLINK_DSCR_CH0: u32,
+            }),
+            ///  DMA_IN_DSCR_BF0_CH0_REG.
+            IN_DSCR_BF0_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last inlink descriptor x-1.
+                INLINK_DSCR_BF0_CH0: u32,
+            }),
+            ///  DMA_IN_DSCR_BF1_CH0_REG.
+            IN_DSCR_BF1_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                INLINK_DSCR_BF1_CH0: u32,
+            }),
+            ///  DMA_IN_PRI_CH0_REG.
+            IN_PRI_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Rx channel 0. The larger of the value, the higher of the priority.
+                RX_PRI_CH0: u4,
+                padding: u28,
+            }),
+            ///  DMA_IN_PERI_SEL_CH0_REG.
+            IN_PERI_SEL_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_IN_SEL_CH0: u6,
+                padding: u26,
+            }),
+            reserved208: [44]u8,
+            ///  DMA_OUT_CONF0_CH0_REG.
+            OUT_CONF0_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
+                OUT_RST_CH0: u1,
+                ///  reserved
+                OUT_LOOP_TEST_CH0: u1,
+                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+                OUT_AUTO_WRBACK_CH0: u1,
+                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA
+                OUT_EOF_MODE_CH0: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.
+                OUTDSCR_BURST_EN_CH0: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.
+                OUT_DATA_BURST_EN_CH0: u1,
+                padding: u26,
+            }),
+            ///  DMA_OUT_CONF1_CH0_REG.
+            OUT_CONF1_CH0: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                OUT_CHECK_OWNER_CH0: u1,
+                padding: u19,
+            }),
+            ///  DMA_OUTFIFO_STATUS_CH0_REG.
+            OUTFIFO_STATUS_CH0: mmio.Mmio(packed struct(u32) {
+                ///  L1 Tx FIFO full signal for Tx channel 0.
+                OUTFIFO_FULL_CH0: u1,
+                ///  L1 Tx FIFO empty signal for Tx channel 0.
+                OUTFIFO_EMPTY_CH0: u1,
+                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
+                OUTFIFO_CNT_CH0: u6,
+                reserved23: u15,
+                ///  reserved
+                OUT_REMAIN_UNDER_1B_CH0: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_2B_CH0: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_3B_CH0: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_4B_CH0: u1,
+                padding: u5,
+            }),
+            ///  DMA_OUT_PUSH_CH0_REG.
+            OUT_PUSH_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data that need to be pushed into DMA FIFO.
+                OUTFIFO_WDATA_CH0: u9,
+                ///  Set this bit to push data into DMA FIFO.
+                OUTFIFO_PUSH_CH0: u1,
+                padding: u22,
+            }),
+            ///  DMA_OUT_LINK_CH0_REG.
+            OUT_LINK_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
+                OUTLINK_ADDR_CH0: u20,
+                ///  Set this bit to stop dealing with the outlink descriptors.
+                OUTLINK_STOP_CH0: u1,
+                ///  Set this bit to start dealing with the outlink descriptors.
+                OUTLINK_START_CH0: u1,
+                ///  Set this bit to restart a new outlink from the last address.
+                OUTLINK_RESTART_CH0: u1,
+                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
+                OUTLINK_PARK_CH0: u1,
+                padding: u8,
+            }),
+            ///  DMA_OUT_STATE_CH0_REG.
+            OUT_STATE_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current outlink descriptor's address.
+                OUTLINK_DSCR_ADDR_CH0: u18,
+                ///  reserved
+                OUT_DSCR_STATE_CH0: u2,
+                ///  reserved
+                OUT_STATE_CH0: u3,
+                padding: u9,
+            }),
+            ///  DMA_OUT_EOF_DES_ADDR_CH0_REG.
+            OUT_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+                OUT_EOF_DES_ADDR_CH0: u32,
+            }),
+            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
+            OUT_EOF_BFR_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
+                OUT_EOF_BFR_DES_ADDR_CH0: u32,
+            }),
+            ///  DMA_OUT_DSCR_CH0_REG.
+            OUT_DSCR_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current outlink descriptor y.
+                OUTLINK_DSCR_CH0: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF0_CH0_REG.
+            OUT_DSCR_BF0_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last outlink descriptor y-1.
+                OUTLINK_DSCR_BF0_CH0: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF1_CH0_REG.
+            OUT_DSCR_BF1_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                OUTLINK_DSCR_BF1_CH0: u32,
+            }),
+            ///  DMA_OUT_PRI_CH0_REG.
+            OUT_PRI_CH0: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Tx channel 0. The larger of the value, the higher of the priority.
+                TX_PRI_CH0: u4,
+                padding: u28,
+            }),
+            ///  DMA_OUT_PERI_SEL_CH0_REG.
+            OUT_PERI_SEL_CH0: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_OUT_SEL_CH0: u6,
+                padding: u26,
+            }),
+            reserved304: [44]u8,
+            ///  DMA_IN_CONF0_CH1_REG.
+            IN_CONF0_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
+                IN_RST_CH1: u1,
+                ///  reserved
+                IN_LOOP_TEST_CH1: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.
+                INDSCR_BURST_EN_CH1: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.
+                IN_DATA_BURST_EN_CH1: u1,
+                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+                MEM_TRANS_EN_CH1: u1,
+                padding: u27,
+            }),
+            ///  DMA_IN_CONF1_CH1_REG.
+            IN_CONF1_CH1: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                IN_CHECK_OWNER_CH1: u1,
+                padding: u19,
+            }),
+            ///  DMA_INFIFO_STATUS_CH1_REG.
+            INFIFO_STATUS_CH1: mmio.Mmio(packed struct(u32) {
+                ///  L1 Rx FIFO full signal for Rx channel 1.
+                INFIFO_FULL_CH1: u1,
+                ///  L1 Rx FIFO empty signal for Rx channel 1.
+                INFIFO_EMPTY_CH1: u1,
+                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.
+                INFIFO_CNT_CH1: u6,
+                reserved23: u15,
+                ///  reserved
+                IN_REMAIN_UNDER_1B_CH1: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_2B_CH1: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_3B_CH1: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_4B_CH1: u1,
+                ///  reserved
+                IN_BUF_HUNGRY_CH1: u1,
+                padding: u4,
+            }),
+            ///  DMA_IN_POP_CH1_REG.
+            IN_POP_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data popping from DMA FIFO.
+                INFIFO_RDATA_CH1: u12,
+                ///  Set this bit to pop data from DMA FIFO.
+                INFIFO_POP_CH1: u1,
+                padding: u19,
+            }),
+            ///  DMA_IN_LINK_CH1_REG.
+            IN_LINK_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
+                INLINK_ADDR_CH1: u20,
+                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+                INLINK_AUTO_RET_CH1: u1,
+                ///  Set this bit to stop dealing with the inlink descriptors.
+                INLINK_STOP_CH1: u1,
+                ///  Set this bit to start dealing with the inlink descriptors.
+                INLINK_START_CH1: u1,
+                ///  Set this bit to mount a new inlink descriptor.
+                INLINK_RESTART_CH1: u1,
+                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
+                INLINK_PARK_CH1: u1,
+                padding: u7,
+            }),
+            ///  DMA_IN_STATE_CH1_REG.
+            IN_STATE_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current inlink descriptor's address.
+                INLINK_DSCR_ADDR_CH1: u18,
+                ///  reserved
+                IN_DSCR_STATE_CH1: u2,
+                ///  reserved
+                IN_STATE_CH1: u3,
+                padding: u9,
+            }),
+            ///  DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.
+            IN_SUC_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+                IN_SUC_EOF_DES_ADDR_CH1: u32,
+            }),
+            ///  DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.
+            IN_ERR_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+                IN_ERR_EOF_DES_ADDR_CH1: u32,
+            }),
+            ///  DMA_IN_DSCR_CH1_REG.
+            IN_DSCR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current inlink descriptor x.
+                INLINK_DSCR_CH1: u32,
+            }),
+            ///  DMA_IN_DSCR_BF0_CH1_REG.
+            IN_DSCR_BF0_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last inlink descriptor x-1.
+                INLINK_DSCR_BF0_CH1: u32,
+            }),
+            ///  DMA_IN_DSCR_BF1_CH1_REG.
+            IN_DSCR_BF1_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                INLINK_DSCR_BF1_CH1: u32,
+            }),
+            ///  DMA_IN_PRI_CH1_REG.
+            IN_PRI_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Rx channel 1. The larger of the value, the higher of the priority.
+                RX_PRI_CH1: u4,
+                padding: u28,
+            }),
+            ///  DMA_IN_PERI_SEL_CH1_REG.
+            IN_PERI_SEL_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_IN_SEL_CH1: u6,
+                padding: u26,
+            }),
+            reserved400: [44]u8,
+            ///  DMA_OUT_CONF0_CH1_REG.
+            OUT_CONF0_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
+                OUT_RST_CH1: u1,
+                ///  reserved
+                OUT_LOOP_TEST_CH1: u1,
+                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+                OUT_AUTO_WRBACK_CH1: u1,
+                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA
+                OUT_EOF_MODE_CH1: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.
+                OUTDSCR_BURST_EN_CH1: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.
+                OUT_DATA_BURST_EN_CH1: u1,
+                padding: u26,
+            }),
+            ///  DMA_OUT_CONF1_CH1_REG.
+            OUT_CONF1_CH1: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                OUT_CHECK_OWNER_CH1: u1,
+                padding: u19,
+            }),
+            ///  DMA_OUTFIFO_STATUS_CH1_REG.
+            OUTFIFO_STATUS_CH1: mmio.Mmio(packed struct(u32) {
+                ///  L1 Tx FIFO full signal for Tx channel 1.
+                OUTFIFO_FULL_CH1: u1,
+                ///  L1 Tx FIFO empty signal for Tx channel 1.
+                OUTFIFO_EMPTY_CH1: u1,
+                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.
+                OUTFIFO_CNT_CH1: u6,
+                reserved23: u15,
+                ///  reserved
+                OUT_REMAIN_UNDER_1B_CH1: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_2B_CH1: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_3B_CH1: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_4B_CH1: u1,
+                padding: u5,
+            }),
+            ///  DMA_OUT_PUSH_CH1_REG.
+            OUT_PUSH_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data that need to be pushed into DMA FIFO.
+                OUTFIFO_WDATA_CH1: u9,
+                ///  Set this bit to push data into DMA FIFO.
+                OUTFIFO_PUSH_CH1: u1,
+                padding: u22,
+            }),
+            ///  DMA_OUT_LINK_CH1_REG.
+            OUT_LINK_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
+                OUTLINK_ADDR_CH1: u20,
+                ///  Set this bit to stop dealing with the outlink descriptors.
+                OUTLINK_STOP_CH1: u1,
+                ///  Set this bit to start dealing with the outlink descriptors.
+                OUTLINK_START_CH1: u1,
+                ///  Set this bit to restart a new outlink from the last address.
+                OUTLINK_RESTART_CH1: u1,
+                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
+                OUTLINK_PARK_CH1: u1,
+                padding: u8,
+            }),
+            ///  DMA_OUT_STATE_CH1_REG.
+            OUT_STATE_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current outlink descriptor's address.
+                OUTLINK_DSCR_ADDR_CH1: u18,
+                ///  reserved
+                OUT_DSCR_STATE_CH1: u2,
+                ///  reserved
+                OUT_STATE_CH1: u3,
+                padding: u9,
+            }),
+            ///  DMA_OUT_EOF_DES_ADDR_CH1_REG.
+            OUT_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+                OUT_EOF_DES_ADDR_CH1: u32,
+            }),
+            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.
+            OUT_EOF_BFR_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
+                OUT_EOF_BFR_DES_ADDR_CH1: u32,
+            }),
+            ///  DMA_OUT_DSCR_CH1_REG.
+            OUT_DSCR_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current outlink descriptor y.
+                OUTLINK_DSCR_CH1: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF0_CH1_REG.
+            OUT_DSCR_BF0_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last outlink descriptor y-1.
+                OUTLINK_DSCR_BF0_CH1: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF1_CH1_REG.
+            OUT_DSCR_BF1_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                OUTLINK_DSCR_BF1_CH1: u32,
+            }),
+            ///  DMA_OUT_PRI_CH1_REG.
+            OUT_PRI_CH1: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Tx channel 1. The larger of the value, the higher of the priority.
+                TX_PRI_CH1: u4,
+                padding: u28,
+            }),
+            ///  DMA_OUT_PERI_SEL_CH1_REG.
+            OUT_PERI_SEL_CH1: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_OUT_SEL_CH1: u6,
+                padding: u26,
+            }),
+            reserved496: [44]u8,
+            ///  DMA_IN_CONF0_CH2_REG.
+            IN_CONF0_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
+                IN_RST_CH2: u1,
+                ///  reserved
+                IN_LOOP_TEST_CH2: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.
+                INDSCR_BURST_EN_CH2: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.
+                IN_DATA_BURST_EN_CH2: u1,
+                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
+                MEM_TRANS_EN_CH2: u1,
+                padding: u27,
+            }),
+            ///  DMA_IN_CONF1_CH2_REG.
+            IN_CONF1_CH2: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                IN_CHECK_OWNER_CH2: u1,
+                padding: u19,
+            }),
+            ///  DMA_INFIFO_STATUS_CH2_REG.
+            INFIFO_STATUS_CH2: mmio.Mmio(packed struct(u32) {
+                ///  L1 Rx FIFO full signal for Rx channel 2.
+                INFIFO_FULL_CH2: u1,
+                ///  L1 Rx FIFO empty signal for Rx channel 2.
+                INFIFO_EMPTY_CH2: u1,
+                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.
+                INFIFO_CNT_CH2: u6,
+                reserved23: u15,
+                ///  reserved
+                IN_REMAIN_UNDER_1B_CH2: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_2B_CH2: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_3B_CH2: u1,
+                ///  reserved
+                IN_REMAIN_UNDER_4B_CH2: u1,
+                ///  reserved
+                IN_BUF_HUNGRY_CH2: u1,
+                padding: u4,
+            }),
+            ///  DMA_IN_POP_CH2_REG.
+            IN_POP_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data popping from DMA FIFO.
+                INFIFO_RDATA_CH2: u12,
+                ///  Set this bit to pop data from DMA FIFO.
+                INFIFO_POP_CH2: u1,
+                padding: u19,
+            }),
+            ///  DMA_IN_LINK_CH2_REG.
+            IN_LINK_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
+                INLINK_ADDR_CH2: u20,
+                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
+                INLINK_AUTO_RET_CH2: u1,
+                ///  Set this bit to stop dealing with the inlink descriptors.
+                INLINK_STOP_CH2: u1,
+                ///  Set this bit to start dealing with the inlink descriptors.
+                INLINK_START_CH2: u1,
+                ///  Set this bit to mount a new inlink descriptor.
+                INLINK_RESTART_CH2: u1,
+                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
+                INLINK_PARK_CH2: u1,
+                padding: u7,
+            }),
+            ///  DMA_IN_STATE_CH2_REG.
+            IN_STATE_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current inlink descriptor's address.
+                INLINK_DSCR_ADDR_CH2: u18,
+                ///  reserved
+                IN_DSCR_STATE_CH2: u2,
+                ///  reserved
+                IN_STATE_CH2: u3,
+                padding: u9,
+            }),
+            ///  DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.
+            IN_SUC_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
+                IN_SUC_EOF_DES_ADDR_CH2: u32,
+            }),
+            ///  DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.
+            IN_ERR_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
+                IN_ERR_EOF_DES_ADDR_CH2: u32,
+            }),
+            ///  DMA_IN_DSCR_CH2_REG.
+            IN_DSCR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current inlink descriptor x.
+                INLINK_DSCR_CH2: u32,
+            }),
+            ///  DMA_IN_DSCR_BF0_CH2_REG.
+            IN_DSCR_BF0_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last inlink descriptor x-1.
+                INLINK_DSCR_BF0_CH2: u32,
+            }),
+            ///  DMA_IN_DSCR_BF1_CH2_REG.
+            IN_DSCR_BF1_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                INLINK_DSCR_BF1_CH2: u32,
+            }),
+            ///  DMA_IN_PRI_CH2_REG.
+            IN_PRI_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Rx channel 2. The larger of the value, the higher of the priority.
+                RX_PRI_CH2: u4,
+                padding: u28,
+            }),
+            ///  DMA_IN_PERI_SEL_CH2_REG.
+            IN_PERI_SEL_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_IN_SEL_CH2: u6,
+                padding: u26,
+            }),
+            reserved592: [44]u8,
+            ///  DMA_OUT_CONF0_CH2_REG.
+            OUT_CONF0_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
+                OUT_RST_CH2: u1,
+                ///  reserved
+                OUT_LOOP_TEST_CH2: u1,
+                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
+                OUT_AUTO_WRBACK_CH2: u1,
+                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA
+                OUT_EOF_MODE_CH2: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.
+                OUTDSCR_BURST_EN_CH2: u1,
+                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.
+                OUT_DATA_BURST_EN_CH2: u1,
+                padding: u26,
+            }),
+            ///  DMA_OUT_CONF1_CH2_REG.
+            OUT_CONF1_CH2: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  Set this bit to enable checking the owner attribute of the link descriptor.
+                OUT_CHECK_OWNER_CH2: u1,
+                padding: u19,
+            }),
+            ///  DMA_OUTFIFO_STATUS_CH2_REG.
+            OUTFIFO_STATUS_CH2: mmio.Mmio(packed struct(u32) {
+                ///  L1 Tx FIFO full signal for Tx channel 2.
+                OUTFIFO_FULL_CH2: u1,
+                ///  L1 Tx FIFO empty signal for Tx channel 2.
+                OUTFIFO_EMPTY_CH2: u1,
+                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.
+                OUTFIFO_CNT_CH2: u6,
+                reserved23: u15,
+                ///  reserved
+                OUT_REMAIN_UNDER_1B_CH2: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_2B_CH2: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_3B_CH2: u1,
+                ///  reserved
+                OUT_REMAIN_UNDER_4B_CH2: u1,
+                padding: u5,
+            }),
+            ///  DMA_OUT_PUSH_CH2_REG.
+            OUT_PUSH_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the data that need to be pushed into DMA FIFO.
+                OUTFIFO_WDATA_CH2: u9,
+                ///  Set this bit to push data into DMA FIFO.
+                OUTFIFO_PUSH_CH2: u1,
+                padding: u22,
+            }),
+            ///  DMA_OUT_LINK_CH2_REG.
+            OUT_LINK_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
+                OUTLINK_ADDR_CH2: u20,
+                ///  Set this bit to stop dealing with the outlink descriptors.
+                OUTLINK_STOP_CH2: u1,
+                ///  Set this bit to start dealing with the outlink descriptors.
+                OUTLINK_START_CH2: u1,
+                ///  Set this bit to restart a new outlink from the last address.
+                OUTLINK_RESTART_CH2: u1,
+                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
+                OUTLINK_PARK_CH2: u1,
+                padding: u8,
+            }),
+            ///  DMA_OUT_STATE_CH2_REG.
+            OUT_STATE_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the current outlink descriptor's address.
+                OUTLINK_DSCR_ADDR_CH2: u18,
+                ///  reserved
+                OUT_DSCR_STATE_CH2: u2,
+                ///  reserved
+                OUT_STATE_CH2: u3,
+                padding: u9,
+            }),
+            ///  DMA_OUT_EOF_DES_ADDR_CH2_REG.
+            OUT_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
+                OUT_EOF_DES_ADDR_CH2: u32,
+            }),
+            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.
+            OUT_EOF_BFR_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
+                OUT_EOF_BFR_DES_ADDR_CH2: u32,
+            }),
+            ///  DMA_OUT_DSCR_CH2_REG.
+            OUT_DSCR_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the current outlink descriptor y.
+                OUTLINK_DSCR_CH2: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF0_CH2_REG.
+            OUT_DSCR_BF0_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the last outlink descriptor y-1.
+                OUTLINK_DSCR_BF0_CH2: u32,
+            }),
+            ///  DMA_OUT_DSCR_BF1_CH2_REG.
+            OUT_DSCR_BF1_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The address of the second-to-last inlink descriptor x-2.
+                OUTLINK_DSCR_BF1_CH2: u32,
+            }),
+            ///  DMA_OUT_PRI_CH2_REG.
+            OUT_PRI_CH2: mmio.Mmio(packed struct(u32) {
+                ///  The priority of Tx channel 2. The larger of the value, the higher of the priority.
+                TX_PRI_CH2: u4,
+                padding: u28,
+            }),
+            ///  DMA_OUT_PERI_SEL_CH2_REG.
+            OUT_PERI_SEL_CH2: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
+                PERI_OUT_SEL_CH2: u6,
+                padding: u26,
+            }),
+        };
+
+        ///  Digital Signature
+        pub const DS = extern struct {
+            ///  memory that stores Y
+            Y_MEM: [512]u8,
+            ///  memory that stores M
+            M_MEM: [512]u8,
+            ///  memory that stores Rb
+            RB_MEM: [512]u8,
+            ///  memory that stores BOX
+            BOX_MEM: [48]u8,
+            reserved2048: [464]u8,
+            ///  memory that stores X
+            X_MEM: [512]u8,
+            ///  memory that stores Z
+            Z_MEM: [512]u8,
+            reserved3584: [512]u8,
+            ///  DS start control register
+            SET_START: mmio.Mmio(packed struct(u32) {
+                ///  set this bit to start DS operation.
+                SET_START: u1,
+                padding: u31,
+            }),
+            ///  DS continue control register
+            SET_CONTINUE: mmio.Mmio(packed struct(u32) {
+                ///  set this bit to continue DS operation.
+                SET_CONTINUE: u1,
+                padding: u31,
+            }),
+            ///  DS finish control register
+            SET_FINISH: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to finish DS process.
+                SET_FINISH: u1,
+                padding: u31,
+            }),
+            ///  DS query busy register
+            QUERY_BUSY: mmio.Mmio(packed struct(u32) {
+                ///  digital signature state. 1'b0: idle, 1'b1: busy
+                QUERY_BUSY: u1,
+                padding: u31,
+            }),
+            ///  DS query key-wrong counter register
+            QUERY_KEY_WRONG: mmio.Mmio(packed struct(u32) {
+                ///  digital signature key wrong counter
+                QUERY_KEY_WRONG: u4,
+                padding: u28,
+            }),
+            ///  DS query check result register
+            QUERY_CHECK: mmio.Mmio(packed struct(u32) {
+                ///  MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
+                MD_ERROR: u1,
+                ///  padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
+                PADDING_BAD: u1,
+                padding: u30,
+            }),
+            reserved3616: [8]u8,
+            ///  DS version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  ds version information
+                DATE: u30,
+                padding: u2,
+            }),
+        };
+
+        ///  eFuse Controller
+        pub const EFUSE = extern struct {
+            ///  Register 0 that stores data to be programmed.
+            PGM_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 0th 32-bit data to be programmed.
+                PGM_DATA_0: u32,
+            }),
+            ///  Register 1 that stores data to be programmed.
+            PGM_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 1st 32-bit data to be programmed.
+                PGM_DATA_1: u32,
+            }),
+            ///  Register 2 that stores data to be programmed.
+            PGM_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 2nd 32-bit data to be programmed.
+                PGM_DATA_2: u32,
+            }),
+            ///  Register 3 that stores data to be programmed.
+            PGM_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 3rd 32-bit data to be programmed.
+                PGM_DATA_3: u32,
+            }),
+            ///  Register 4 that stores data to be programmed.
+            PGM_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 4th 32-bit data to be programmed.
+                PGM_DATA_4: u32,
+            }),
+            ///  Register 5 that stores data to be programmed.
+            PGM_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 5th 32-bit data to be programmed.
+                PGM_DATA_5: u32,
+            }),
+            ///  Register 6 that stores data to be programmed.
+            PGM_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 6th 32-bit data to be programmed.
+                PGM_DATA_6: u32,
+            }),
+            ///  Register 7 that stores data to be programmed.
+            PGM_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 7th 32-bit data to be programmed.
+                PGM_DATA_7: u32,
+            }),
+            ///  Register 0 that stores the RS code to be programmed.
+            PGM_CHECK_VALUE0: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 0th 32-bit RS code to be programmed.
+                PGM_RS_DATA_0: u32,
+            }),
+            ///  Register 1 that stores the RS code to be programmed.
+            PGM_CHECK_VALUE1: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 1st 32-bit RS code to be programmed.
+                PGM_RS_DATA_1: u32,
+            }),
+            ///  Register 2 that stores the RS code to be programmed.
+            PGM_CHECK_VALUE2: mmio.Mmio(packed struct(u32) {
+                ///  The content of the 2nd 32-bit RS code to be programmed.
+                PGM_RS_DATA_2: u32,
+            }),
+            ///  BLOCK0 data register 0.
+            RD_WR_DIS: mmio.Mmio(packed struct(u32) {
+                ///  Disable programming of individual eFuses.
+                WR_DIS: u32,
+            }),
+            ///  BLOCK0 data register 1.
+            RD_REPEAT_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to disable reading from BlOCK4-10.
+                RD_DIS: u7,
+                ///  Set this bit to disable boot from RTC RAM.
+                DIS_RTC_RAM_BOOT: u1,
+                ///  Set this bit to disable Icache.
+                DIS_ICACHE: u1,
+                ///  Set this bit to disable function of usb switch to jtag in module of usb device.
+                DIS_USB_JTAG: u1,
+                ///  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).
+                DIS_DOWNLOAD_ICACHE: u1,
+                ///  Set this bit to disable usb device.
+                DIS_USB_DEVICE: u1,
+                ///  Set this bit to disable the function that forces chip into download mode.
+                DIS_FORCE_DOWNLOAD: u1,
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED6: u1,
+                ///  Set this bit to disable CAN function.
+                DIS_CAN: u1,
+                ///  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
+                JTAG_SEL_ENABLE: u1,
+                ///  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.
+                SOFT_DIS_JTAG: u3,
+                ///  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
+                DIS_PAD_JTAG: u1,
+                ///  Set this bit to disable flash encryption when in download boot modes.
+                DIS_DOWNLOAD_MANUAL_ENCRYPT: u1,
+                ///  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.
+                USB_DREFH: u2,
+                ///  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.
+                USB_DREFL: u2,
+                ///  Set this bit to exchange USB D+ and D- pins.
+                USB_EXCHG_PINS: u1,
+                ///  Set this bit to vdd spi pin function as gpio.
+                VDD_SPI_AS_GPIO: u1,
+                ///  Enable btlc gpio.
+                BTLC_GPIO_ENABLE: u2,
+                ///  Set this bit to enable power glitch function.
+                POWERGLITCH_EN: u1,
+                ///  Sample delay configuration of power glitch.
+                POWER_GLITCH_DSENSE: u2,
+            }),
+            ///  BLOCK0 data register 2.
+            RD_REPEAT_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED2: u16,
+                ///  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.
+                WDT_DELAY_SEL: u2,
+                ///  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.
+                SPI_BOOT_CRYPT_CNT: u3,
+                ///  Set this bit to enable revoking first secure boot key.
+                SECURE_BOOT_KEY_REVOKE0: u1,
+                ///  Set this bit to enable revoking second secure boot key.
+                SECURE_BOOT_KEY_REVOKE1: u1,
+                ///  Set this bit to enable revoking third secure boot key.
+                SECURE_BOOT_KEY_REVOKE2: u1,
+                ///  Purpose of Key0.
+                KEY_PURPOSE_0: u4,
+                ///  Purpose of Key1.
+                KEY_PURPOSE_1: u4,
+            }),
+            ///  BLOCK0 data register 3.
+            RD_REPEAT_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Purpose of Key2.
+                KEY_PURPOSE_2: u4,
+                ///  Purpose of Key3.
+                KEY_PURPOSE_3: u4,
+                ///  Purpose of Key4.
+                KEY_PURPOSE_4: u4,
+                ///  Purpose of Key5.
+                KEY_PURPOSE_5: u4,
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED3: u4,
+                ///  Set this bit to enable secure boot.
+                SECURE_BOOT_EN: u1,
+                ///  Set this bit to enable revoking aggressive secure boot.
+                SECURE_BOOT_AGGRESSIVE_REVOKE: u1,
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED0: u6,
+                ///  Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.
+                FLASH_TPUW: u4,
+            }),
+            ///  BLOCK0 data register 4.
+            RD_REPEAT_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
+                DIS_DOWNLOAD_MODE: u1,
+                ///  Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).
+                DIS_LEGACY_SPI_BOOT: u1,
+                ///  Selectes the default UART print channel. 0: UART0. 1: UART1.
+                UART_PRINT_CHANNEL: u1,
+                ///  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.
+                FLASH_ECC_MODE: u1,
+                ///  Set this bit to disable UART download mode through USB.
+                DIS_USB_DOWNLOAD_MODE: u1,
+                ///  Set this bit to enable secure UART download mode.
+                ENABLE_SECURITY_DOWNLOAD: u1,
+                ///  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
+                UART_PRINT_CONTROL: u2,
+                ///  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
+                PIN_POWER_SELECTION: u1,
+                ///  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
+                FLASH_TYPE: u1,
+                ///  Set Flash page size.
+                FLASH_PAGE_SIZE: u2,
+                ///  Set 1 to enable ECC for flash boot.
+                FLASH_ECC_EN: u1,
+                ///  Set this bit to force ROM code to send a resume command during SPI boot.
+                FORCE_SEND_RESUME: u1,
+                ///  Secure version (used by ESP-IDF anti-rollback feature).
+                SECURE_VERSION: u16,
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED1: u2,
+            }),
+            ///  BLOCK0 data register 5.
+            RD_REPEAT_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Reserved (used for four backups method).
+                RPT4_RESERVED4: u24,
+                padding: u8,
+            }),
+            ///  BLOCK1 data register 0.
+            RD_MAC_SPI_SYS_0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the low 32 bits of MAC address.
+                MAC_0: u32,
+            }),
+            ///  BLOCK1 data register 1.
+            RD_MAC_SPI_SYS_1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the high 16 bits of MAC address.
+                MAC_1: u16,
+                ///  Stores the zeroth part of SPI_PAD_CONF.
+                SPI_PAD_CONF_0: u16,
+            }),
+            ///  BLOCK1 data register 2.
+            RD_MAC_SPI_SYS_2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first part of SPI_PAD_CONF.
+                SPI_PAD_CONF_1: u32,
+            }),
+            ///  BLOCK1 data register 3.
+            RD_MAC_SPI_SYS_3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second part of SPI_PAD_CONF.
+                SPI_PAD_CONF_2: u18,
+                ///  Stores the fist 14 bits of the zeroth part of system data.
+                SYS_DATA_PART0_0: u14,
+            }),
+            ///  BLOCK1 data register 4.
+            RD_MAC_SPI_SYS_4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fist 32 bits of the zeroth part of system data.
+                SYS_DATA_PART0_1: u32,
+            }),
+            ///  BLOCK1 data register 5.
+            RD_MAC_SPI_SYS_5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of the zeroth part of system data.
+                SYS_DATA_PART0_2: u32,
+            }),
+            ///  Register 0 of BLOCK2 (system).
+            RD_SYS_PART1_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of the first part of system data.
+                SYS_DATA_PART1_0: u32,
+            }),
+            ///  Register 1 of BLOCK2 (system).
+            RD_SYS_PART1_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of the first part of system data.
+                SYS_DATA_PART1_1: u32,
+            }),
+            ///  Register 2 of BLOCK2 (system).
+            RD_SYS_PART1_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of the first part of system data.
+                SYS_DATA_PART1_2: u32,
+            }),
+            ///  Register 3 of BLOCK2 (system).
+            RD_SYS_PART1_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of the first part of system data.
+                SYS_DATA_PART1_3: u32,
+            }),
+            ///  Register 4 of BLOCK2 (system).
+            RD_SYS_PART1_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of the first part of system data.
+                SYS_DATA_PART1_4: u32,
+            }),
+            ///  Register 5 of BLOCK2 (system).
+            RD_SYS_PART1_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of the first part of system data.
+                SYS_DATA_PART1_5: u32,
+            }),
+            ///  Register 6 of BLOCK2 (system).
+            RD_SYS_PART1_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of the first part of system data.
+                SYS_DATA_PART1_6: u32,
+            }),
+            ///  Register 7 of BLOCK2 (system).
+            RD_SYS_PART1_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of the first part of system data.
+                SYS_DATA_PART1_7: u32,
+            }),
+            ///  Register 0 of BLOCK3 (user).
+            RD_USR_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of BLOCK3 (user).
+                USR_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK3 (user).
+            RD_USR_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of BLOCK3 (user).
+                USR_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK3 (user).
+            RD_USR_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of BLOCK3 (user).
+                USR_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK3 (user).
+            RD_USR_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of BLOCK3 (user).
+                USR_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK3 (user).
+            RD_USR_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of BLOCK3 (user).
+                USR_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK3 (user).
+            RD_USR_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of BLOCK3 (user).
+                USR_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK3 (user).
+            RD_USR_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of BLOCK3 (user).
+                USR_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK3 (user).
+            RD_USR_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of BLOCK3 (user).
+                USR_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK4 (KEY0).
+            RD_KEY0_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY0.
+                KEY0_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK4 (KEY0).
+            RD_KEY0_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY0.
+                KEY0_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK4 (KEY0).
+            RD_KEY0_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY0.
+                KEY0_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK4 (KEY0).
+            RD_KEY0_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY0.
+                KEY0_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK4 (KEY0).
+            RD_KEY0_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY0.
+                KEY0_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK4 (KEY0).
+            RD_KEY0_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY0.
+                KEY0_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK4 (KEY0).
+            RD_KEY0_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY0.
+                KEY0_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK4 (KEY0).
+            RD_KEY0_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY0.
+                KEY0_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK5 (KEY1).
+            RD_KEY1_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY1.
+                KEY1_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK5 (KEY1).
+            RD_KEY1_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY1.
+                KEY1_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK5 (KEY1).
+            RD_KEY1_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY1.
+                KEY1_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK5 (KEY1).
+            RD_KEY1_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY1.
+                KEY1_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK5 (KEY1).
+            RD_KEY1_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY1.
+                KEY1_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK5 (KEY1).
+            RD_KEY1_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY1.
+                KEY1_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK5 (KEY1).
+            RD_KEY1_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY1.
+                KEY1_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK5 (KEY1).
+            RD_KEY1_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY1.
+                KEY1_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK6 (KEY2).
+            RD_KEY2_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY2.
+                KEY2_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK6 (KEY2).
+            RD_KEY2_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY2.
+                KEY2_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK6 (KEY2).
+            RD_KEY2_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY2.
+                KEY2_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK6 (KEY2).
+            RD_KEY2_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY2.
+                KEY2_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK6 (KEY2).
+            RD_KEY2_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY2.
+                KEY2_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK6 (KEY2).
+            RD_KEY2_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY2.
+                KEY2_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK6 (KEY2).
+            RD_KEY2_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY2.
+                KEY2_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK6 (KEY2).
+            RD_KEY2_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY2.
+                KEY2_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK7 (KEY3).
+            RD_KEY3_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY3.
+                KEY3_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK7 (KEY3).
+            RD_KEY3_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY3.
+                KEY3_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK7 (KEY3).
+            RD_KEY3_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY3.
+                KEY3_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK7 (KEY3).
+            RD_KEY3_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY3.
+                KEY3_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK7 (KEY3).
+            RD_KEY3_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY3.
+                KEY3_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK7 (KEY3).
+            RD_KEY3_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY3.
+                KEY3_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK7 (KEY3).
+            RD_KEY3_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY3.
+                KEY3_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK7 (KEY3).
+            RD_KEY3_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY3.
+                KEY3_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK8 (KEY4).
+            RD_KEY4_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY4.
+                KEY4_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK8 (KEY4).
+            RD_KEY4_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY4.
+                KEY4_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK8 (KEY4).
+            RD_KEY4_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY4.
+                KEY4_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK8 (KEY4).
+            RD_KEY4_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY4.
+                KEY4_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK8 (KEY4).
+            RD_KEY4_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY4.
+                KEY4_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK8 (KEY4).
+            RD_KEY4_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY4.
+                KEY4_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK8 (KEY4).
+            RD_KEY4_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY4.
+                KEY4_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK8 (KEY4).
+            RD_KEY4_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY4.
+                KEY4_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK9 (KEY5).
+            RD_KEY5_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the zeroth 32 bits of KEY5.
+                KEY5_DATA0: u32,
+            }),
+            ///  Register 1 of BLOCK9 (KEY5).
+            RD_KEY5_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the first 32 bits of KEY5.
+                KEY5_DATA1: u32,
+            }),
+            ///  Register 2 of BLOCK9 (KEY5).
+            RD_KEY5_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the second 32 bits of KEY5.
+                KEY5_DATA2: u32,
+            }),
+            ///  Register 3 of BLOCK9 (KEY5).
+            RD_KEY5_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the third 32 bits of KEY5.
+                KEY5_DATA3: u32,
+            }),
+            ///  Register 4 of BLOCK9 (KEY5).
+            RD_KEY5_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fourth 32 bits of KEY5.
+                KEY5_DATA4: u32,
+            }),
+            ///  Register 5 of BLOCK9 (KEY5).
+            RD_KEY5_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the fifth 32 bits of KEY5.
+                KEY5_DATA5: u32,
+            }),
+            ///  Register 6 of BLOCK9 (KEY5).
+            RD_KEY5_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the sixth 32 bits of KEY5.
+                KEY5_DATA6: u32,
+            }),
+            ///  Register 7 of BLOCK9 (KEY5).
+            RD_KEY5_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the seventh 32 bits of KEY5.
+                KEY5_DATA7: u32,
+            }),
+            ///  Register 0 of BLOCK10 (system).
+            RD_SYS_PART2_DATA0: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 0th 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_0: u32,
+            }),
+            ///  Register 1 of BLOCK9 (KEY5).
+            RD_SYS_PART2_DATA1: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 1st 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_1: u32,
+            }),
+            ///  Register 2 of BLOCK10 (system).
+            RD_SYS_PART2_DATA2: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 2nd 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_2: u32,
+            }),
+            ///  Register 3 of BLOCK10 (system).
+            RD_SYS_PART2_DATA3: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 3rd 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_3: u32,
+            }),
+            ///  Register 4 of BLOCK10 (system).
+            RD_SYS_PART2_DATA4: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 4th 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_4: u32,
+            }),
+            ///  Register 5 of BLOCK10 (system).
+            RD_SYS_PART2_DATA5: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 5th 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_5: u32,
+            }),
+            ///  Register 6 of BLOCK10 (system).
+            RD_SYS_PART2_DATA6: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 6th 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_6: u32,
+            }),
+            ///  Register 7 of BLOCK10 (system).
+            RD_SYS_PART2_DATA7: mmio.Mmio(packed struct(u32) {
+                ///  Stores the 7th 32 bits of the 2nd part of system data.
+                SYS_DATA_PART2_7: u32,
+            }),
+            ///  Programming error record register 0 of BLOCK0.
+            RD_REPEAT_ERR0: mmio.Mmio(packed struct(u32) {
+                ///  If any bit in RD_DIS is 1, then it indicates a programming error.
+                RD_DIS_ERR: u7,
+                ///  If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
+                DIS_RTC_RAM_BOOT_ERR: u1,
+                ///  If DIS_ICACHE is 1, then it indicates a programming error.
+                DIS_ICACHE_ERR: u1,
+                ///  If DIS_USB_JTAG is 1, then it indicates a programming error.
+                DIS_USB_JTAG_ERR: u1,
+                ///  If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
+                DIS_DOWNLOAD_ICACHE_ERR: u1,
+                ///  If DIS_USB_DEVICE is 1, then it indicates a programming error.
+                DIS_USB_DEVICE_ERR: u1,
+                ///  If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
+                DIS_FORCE_DOWNLOAD_ERR: u1,
+                ///  Reserved.
+                RPT4_RESERVED6_ERR: u1,
+                ///  If DIS_CAN is 1, then it indicates a programming error.
+                DIS_CAN_ERR: u1,
+                ///  If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
+                JTAG_SEL_ENABLE_ERR: u1,
+                ///  If SOFT_DIS_JTAG is 1, then it indicates a programming error.
+                SOFT_DIS_JTAG_ERR: u3,
+                ///  If DIS_PAD_JTAG is 1, then it indicates a programming error.
+                DIS_PAD_JTAG_ERR: u1,
+                ///  If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
+                DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR: u1,
+                ///  If any bit in USB_DREFH is 1, then it indicates a programming error.
+                USB_DREFH_ERR: u2,
+                ///  If any bit in USB_DREFL is 1, then it indicates a programming error.
+                USB_DREFL_ERR: u2,
+                ///  If USB_EXCHG_PINS is 1, then it indicates a programming error.
+                USB_EXCHG_PINS_ERR: u1,
+                ///  If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
+                VDD_SPI_AS_GPIO_ERR: u1,
+                ///  If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
+                BTLC_GPIO_ENABLE_ERR: u2,
+                ///  If POWERGLITCH_EN is 1, then it indicates a programming error.
+                POWERGLITCH_EN_ERR: u1,
+                ///  If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
+                POWER_GLITCH_DSENSE_ERR: u2,
+            }),
+            ///  Programming error record register 1 of BLOCK0.
+            RD_REPEAT_ERR1: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                RPT4_RESERVED2_ERR: u16,
+                ///  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
+                WDT_DELAY_SEL_ERR: u2,
+                ///  If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
+                SPI_BOOT_CRYPT_CNT_ERR: u3,
+                ///  If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
+                SECURE_BOOT_KEY_REVOKE0_ERR: u1,
+                ///  If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
+                SECURE_BOOT_KEY_REVOKE1_ERR: u1,
+                ///  If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
+                SECURE_BOOT_KEY_REVOKE2_ERR: u1,
+                ///  If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
+                KEY_PURPOSE_0_ERR: u4,
+                ///  If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
+                KEY_PURPOSE_1_ERR: u4,
+            }),
+            ///  Programming error record register 2 of BLOCK0.
+            RD_REPEAT_ERR2: mmio.Mmio(packed struct(u32) {
+                ///  If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
+                KEY_PURPOSE_2_ERR: u4,
+                ///  If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
+                KEY_PURPOSE_3_ERR: u4,
+                ///  If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
+                KEY_PURPOSE_4_ERR: u4,
+                ///  If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
+                KEY_PURPOSE_5_ERR: u4,
+                ///  Reserved.
+                RPT4_RESERVED3_ERR: u4,
+                ///  If SECURE_BOOT_EN is 1, then it indicates a programming error.
+                SECURE_BOOT_EN_ERR: u1,
+                ///  If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
+                SECURE_BOOT_AGGRESSIVE_REVOKE_ERR: u1,
+                ///  Reserved.
+                RPT4_RESERVED0_ERR: u6,
+                ///  If any bit in FLASH_TPUM is 1, then it indicates a programming error.
+                FLASH_TPUW_ERR: u4,
+            }),
+            ///  Programming error record register 3 of BLOCK0.
+            RD_REPEAT_ERR3: mmio.Mmio(packed struct(u32) {
+                ///  If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
+                DIS_DOWNLOAD_MODE_ERR: u1,
+                ///  If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
+                DIS_LEGACY_SPI_BOOT_ERR: u1,
+                ///  If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
+                UART_PRINT_CHANNEL_ERR: u1,
+                ///  If FLASH_ECC_MODE is 1, then it indicates a programming error.
+                FLASH_ECC_MODE_ERR: u1,
+                ///  If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
+                DIS_USB_DOWNLOAD_MODE_ERR: u1,
+                ///  If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
+                ENABLE_SECURITY_DOWNLOAD_ERR: u1,
+                ///  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
+                UART_PRINT_CONTROL_ERR: u2,
+                ///  If PIN_POWER_SELECTION is 1, then it indicates a programming error.
+                PIN_POWER_SELECTION_ERR: u1,
+                ///  If FLASH_TYPE is 1, then it indicates a programming error.
+                FLASH_TYPE_ERR: u1,
+                ///  If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
+                FLASH_PAGE_SIZE_ERR: u2,
+                ///  If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
+                FLASH_ECC_EN_ERR: u1,
+                ///  If FORCE_SEND_RESUME is 1, then it indicates a programming error.
+                FORCE_SEND_RESUME_ERR: u1,
+                ///  If any bit in SECURE_VERSION is 1, then it indicates a programming error.
+                SECURE_VERSION_ERR: u16,
+                ///  Reserved.
+                RPT4_RESERVED1_ERR: u2,
+            }),
+            reserved400: [4]u8,
+            ///  Programming error record register 4 of BLOCK0.
+            RD_REPEAT_ERR4: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                RPT4_RESERVED4_ERR: u24,
+                padding: u8,
+            }),
+            reserved448: [44]u8,
+            ///  Programming error record register 0 of BLOCK1-10.
+            RD_RS_ERR0: mmio.Mmio(packed struct(u32) {
+                ///  The value of this signal means the number of error bytes.
+                MAC_SPI_8M_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+                MAC_SPI_8M_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                SYS_PART1_NUM: u3,
+                ///  0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+                SYS_PART1_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                USR_DATA_ERR_NUM: u3,
+                ///  0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+                USR_DATA_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                KEY0_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.
+                KEY0_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                KEY1_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.
+                KEY1_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                KEY2_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.
+                KEY2_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                KEY3_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.
+                KEY3_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                KEY4_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.
+                KEY4_FAIL: u1,
+            }),
+            ///  Programming error record register 1 of BLOCK1-10.
+            RD_RS_ERR1: mmio.Mmio(packed struct(u32) {
+                ///  The value of this signal means the number of error bytes.
+                KEY5_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+                KEY5_FAIL: u1,
+                ///  The value of this signal means the number of error bytes.
+                SYS_PART2_ERR_NUM: u3,
+                ///  0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
+                SYS_PART2_FAIL: u1,
+                padding: u24,
+            }),
+            ///  eFuse clcok configuration register.
+            CLK: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to force eFuse SRAM into power-saving mode.
+                EFUSE_MEM_FORCE_PD: u1,
+                ///  Set this bit and force to activate clock signal of eFuse SRAM.
+                MEM_CLK_FORCE_ON: u1,
+                ///  Set this bit to force eFuse SRAM into working mode.
+                EFUSE_MEM_FORCE_PU: u1,
+                reserved16: u13,
+                ///  Set this bit and force to enable clock signal of eFuse memory.
+                EN: u1,
+                padding: u15,
+            }),
+            ///  eFuse operation mode configuraiton register;
+            CONF: mmio.Mmio(packed struct(u32) {
+                ///  0x5A5A: Operate programming command 0x5AA5: Operate read command.
+                OP_CODE: u16,
+                padding: u16,
+            }),
+            ///  eFuse status register.
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  Indicates the state of the eFuse state machine.
+                STATE: u4,
+                ///  The value of OTP_LOAD_SW.
+                OTP_LOAD_SW: u1,
+                ///  The value of OTP_VDDQ_C_SYNC2.
+                OTP_VDDQ_C_SYNC2: u1,
+                ///  The value of OTP_STROBE_SW.
+                OTP_STROBE_SW: u1,
+                ///  The value of OTP_CSB_SW.
+                OTP_CSB_SW: u1,
+                ///  The value of OTP_PGENB_SW.
+                OTP_PGENB_SW: u1,
+                ///  The value of OTP_VDDQ_IS_SW.
+                OTP_VDDQ_IS_SW: u1,
+                ///  Indicates the number of error bits during programming BLOCK0.
+                REPEAT_ERR_CNT: u8,
+                padding: u14,
+            }),
+            ///  eFuse command register.
+            CMD: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to send read command.
+                READ_CMD: u1,
+                ///  Set this bit to send programming command.
+                PGM_CMD: u1,
+                ///  The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.
+                BLK_NUM: u4,
+                padding: u26,
+            }),
+            ///  eFuse raw interrupt register.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  The raw bit signal for read_done interrupt.
+                READ_DONE_INT_RAW: u1,
+                ///  The raw bit signal for pgm_done interrupt.
+                PGM_DONE_INT_RAW: u1,
+                padding: u30,
+            }),
+            ///  eFuse interrupt status register.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The status signal for read_done interrupt.
+                READ_DONE_INT_ST: u1,
+                ///  The status signal for pgm_done interrupt.
+                PGM_DONE_INT_ST: u1,
+                padding: u30,
+            }),
+            ///  eFuse interrupt enable register.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The enable signal for read_done interrupt.
+                READ_DONE_INT_ENA: u1,
+                ///  The enable signal for pgm_done interrupt.
+                PGM_DONE_INT_ENA: u1,
+                padding: u30,
+            }),
+            ///  eFuse interrupt clear register.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The clear signal for read_done interrupt.
+                READ_DONE_INT_CLR: u1,
+                ///  The clear signal for pgm_done interrupt.
+                PGM_DONE_INT_CLR: u1,
+                padding: u30,
+            }),
+            ///  Controls the eFuse programming voltage.
+            DAC_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Controls the division factor of the rising clock of the programming voltage.
+                DAC_CLK_DIV: u8,
+                ///  Don't care.
+                DAC_CLK_PAD_SEL: u1,
+                ///  Controls the rising period of the programming voltage.
+                DAC_NUM: u8,
+                ///  Reduces the power supply of the programming voltage.
+                OE_CLR: u1,
+                padding: u14,
+            }),
+            ///  Configures read timing parameters.
+            RD_TIM_CONF: mmio.Mmio(packed struct(u32) {
+                reserved24: u24,
+                ///  Configures the initial read time of eFuse.
+                READ_INIT_NUM: u8,
+            }),
+            ///  Configurarion register 1 of eFuse programming timing parameters.
+            WR_TIM_CONF1: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  Configures the power up time for VDDQ.
+                PWR_ON_NUM: u16,
+                padding: u8,
+            }),
+            ///  Configurarion register 2 of eFuse programming timing parameters.
+            WR_TIM_CONF2: mmio.Mmio(packed struct(u32) {
+                ///  Configures the power outage time for VDDQ.
+                PWR_OFF_NUM: u16,
+                padding: u16,
+            }),
+            reserved508: [4]u8,
+            ///  eFuse version register.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  Stores eFuse version.
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  External Memory
+        pub const EXTMEM = extern struct {
+            ///  This description will be updated in the near future.
+            ICACHE_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to activate the data cache. 0: disable, 1: enable
+                ICACHE_ENABLE: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_CTRL1: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to disable core0 ibus, 0: enable, 1: disable
+                ICACHE_SHUT_IBUS: u1,
+                ///  The bit is used to disable core1 ibus, 0: enable, 1: disable
+                ICACHE_SHUT_DBUS: u1,
+                padding: u30,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_TAG_POWER_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating.
+                ICACHE_TAG_MEM_FORCE_ON: u1,
+                ///  The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down
+                ICACHE_TAG_MEM_FORCE_PD: u1,
+                ///  The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up
+                ICACHE_TAG_MEM_FORCE_PU: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOCK_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable the first section of prelock function.
+                ICACHE_PRELOCK_SCT0_EN: u1,
+                ///  The bit is used to enable the second section of prelock function.
+                ICACHE_PRELOCK_SCT1_EN: u1,
+                padding: u30,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOCK_SCT0_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG
+                ICACHE_PRELOCK_SCT0_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOCK_SCT1_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG
+                ICACHE_PRELOCK_SCT1_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOCK_SCT_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG
+                ICACHE_PRELOCK_SCT1_SIZE: u16,
+                ///  The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG
+                ICACHE_PRELOCK_SCT0_SIZE: u16,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_LOCK_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.
+                ICACHE_LOCK_ENA: u1,
+                ///  The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.
+                ICACHE_UNLOCK_ENA: u1,
+                ///  The bit is used to indicate unlock/lock operation is finished.
+                ICACHE_LOCK_DONE: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_LOCK_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.
+                ICACHE_LOCK_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_LOCK_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.
+                ICACHE_LOCK_SIZE: u16,
+                padding: u16,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_SYNC_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.
+                ICACHE_INVALIDATE_ENA: u1,
+                ///  The bit is used to indicate invalidate operation is finished.
+                ICACHE_SYNC_DONE: u1,
+                padding: u30,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_SYNC_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.
+                ICACHE_SYNC_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_SYNC_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.
+                ICACHE_SYNC_SIZE: u23,
+                padding: u9,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOAD_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.
+                ICACHE_PRELOAD_ENA: u1,
+                ///  The bit is used to indicate preload operation is finished.
+                ICACHE_PRELOAD_DONE: u1,
+                ///  The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.
+                ICACHE_PRELOAD_ORDER: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOAD_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.
+                ICACHE_PRELOAD_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_PRELOAD_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..
+                ICACHE_PRELOAD_SIZE: u16,
+                padding: u16,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_AUTOLOAD_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to enable the first section for autoload operation.
+                ICACHE_AUTOLOAD_SCT0_ENA: u1,
+                ///  The bits are used to enable the second section for autoload operation.
+                ICACHE_AUTOLOAD_SCT1_ENA: u1,
+                ///  The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.
+                ICACHE_AUTOLOAD_ENA: u1,
+                ///  The bit is used to indicate autoload operation is finished.
+                ICACHE_AUTOLOAD_DONE: u1,
+                ///  The bits are used to configure the direction of autoload. 1: descending, 0: ascending.
+                ICACHE_AUTOLOAD_ORDER: u1,
+                ///  The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
+                ICACHE_AUTOLOAD_RQST: u2,
+                padding: u25,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_AUTOLOAD_SCT0_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
+                ICACHE_AUTOLOAD_SCT0_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_AUTOLOAD_SCT0_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
+                ICACHE_AUTOLOAD_SCT0_SIZE: u27,
+                padding: u5,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_AUTOLOAD_SCT1_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
+                ICACHE_AUTOLOAD_SCT1_ADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_AUTOLOAD_SCT1_SIZE: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
+                ICACHE_AUTOLOAD_SCT1_SIZE: u27,
+                padding: u5,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_TO_FLASH_START_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
+                IBUS_TO_FLASH_START_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_TO_FLASH_END_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
+                IBUS_TO_FLASH_END_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_TO_FLASH_START_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
+                DBUS_TO_FLASH_START_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_TO_FLASH_END_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
+                DBUS_TO_FLASH_END_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ACS_CNT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to clear ibus counter.
+                IBUS_ACS_CNT_CLR: u1,
+                ///  The bit is used to clear dbus counter.
+                DBUS_ACS_CNT_CLR: u1,
+                padding: u30,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_ACS_MISS_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to count the number of the cache miss caused by ibus access flash.
+                IBUS_ACS_MISS_CNT: u32,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_ACS_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to count the number of ibus access flash through icache.
+                IBUS_ACS_CNT: u32,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_ACS_FLASH_MISS_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to count the number of the cache miss caused by dbus access flash.
+                DBUS_ACS_FLASH_MISS_CNT: u32,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_ACS_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to count the number of dbus access flash through icache.
+                DBUS_ACS_CNT: u32,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ILG_INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable interrupt by sync configurations fault.
+                ICACHE_SYNC_OP_FAULT_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by preload configurations fault.
+                ICACHE_PRELOAD_OP_FAULT_INT_ENA: u1,
+                reserved5: u3,
+                ///  The bit is used to enable interrupt by mmu entry fault.
+                MMU_ENTRY_FAULT_INT_ENA: u1,
+                reserved7: u1,
+                ///  The bit is used to enable interrupt by ibus counter overflow.
+                IBUS_CNT_OVF_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by dbus counter overflow.
+                DBUS_CNT_OVF_INT_ENA: u1,
+                padding: u23,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ILG_INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to clear interrupt by sync configurations fault.
+                ICACHE_SYNC_OP_FAULT_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by preload configurations fault.
+                ICACHE_PRELOAD_OP_FAULT_INT_CLR: u1,
+                reserved5: u3,
+                ///  The bit is used to clear interrupt by mmu entry fault.
+                MMU_ENTRY_FAULT_INT_CLR: u1,
+                reserved7: u1,
+                ///  The bit is used to clear interrupt by ibus counter overflow.
+                IBUS_CNT_OVF_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by dbus counter overflow.
+                DBUS_CNT_OVF_INT_CLR: u1,
+                padding: u23,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ILG_INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to indicate interrupt by sync configurations fault.
+                ICACHE_SYNC_OP_FAULT_ST: u1,
+                ///  The bit is used to indicate interrupt by preload configurations fault.
+                ICACHE_PRELOAD_OP_FAULT_ST: u1,
+                reserved5: u3,
+                ///  The bit is used to indicate interrupt by mmu entry fault.
+                MMU_ENTRY_FAULT_ST: u1,
+                reserved7: u1,
+                ///  The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.
+                IBUS_ACS_CNT_OVF_ST: u1,
+                ///  The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.
+                IBUS_ACS_MISS_CNT_OVF_ST: u1,
+                ///  The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.
+                DBUS_ACS_CNT_OVF_ST: u1,
+                ///  The bit is used to indicate interrupt by dbus access flash miss counter overflow.
+                DBUS_ACS_FLASH_MISS_CNT_OVF_ST: u1,
+                padding: u21,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_ACS_CACHE_INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.
+                CORE0_IBUS_ACS_MSK_IC_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by ibus trying to write icache
+                CORE0_IBUS_WR_IC_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by authentication fail.
+                CORE0_IBUS_REJECT_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.
+                CORE0_DBUS_ACS_MSK_IC_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by authentication fail.
+                CORE0_DBUS_REJECT_INT_ENA: u1,
+                ///  The bit is used to enable interrupt by dbus trying to write icache
+                CORE0_DBUS_WR_IC_INT_ENA: u1,
+                padding: u26,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_ACS_CACHE_INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.
+                CORE0_IBUS_ACS_MSK_IC_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by ibus trying to write icache
+                CORE0_IBUS_WR_IC_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by authentication fail.
+                CORE0_IBUS_REJECT_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.
+                CORE0_DBUS_ACS_MSK_IC_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by authentication fail.
+                CORE0_DBUS_REJECT_INT_CLR: u1,
+                ///  The bit is used to clear interrupt by dbus trying to write icache
+                CORE0_DBUS_WR_IC_INT_CLR: u1,
+                padding: u26,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_ACS_CACHE_INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access.
+                CORE0_IBUS_ACS_MSK_ICACHE_ST: u1,
+                ///  The bit is used to indicate interrupt by ibus trying to write icache
+                CORE0_IBUS_WR_ICACHE_ST: u1,
+                ///  The bit is used to indicate interrupt by authentication fail.
+                CORE0_IBUS_REJECT_ST: u1,
+                ///  The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.
+                CORE0_DBUS_ACS_MSK_ICACHE_ST: u1,
+                ///  The bit is used to indicate interrupt by authentication fail.
+                CORE0_DBUS_REJECT_ST: u1,
+                ///  The bit is used to indicate interrupt by dbus trying to write icache
+                CORE0_DBUS_WR_ICACHE_ST: u1,
+                padding: u26,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_DBUS_REJECT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.
+                CORE0_DBUS_ATTR: u3,
+                ///  The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1
+                CORE0_DBUS_WORLD: u1,
+                padding: u28,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_DBUS_REJECT_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the virtual address of CPU access dbus when authentication fail.
+                CORE0_DBUS_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_IBUS_REJECT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able
+                CORE0_IBUS_ATTR: u3,
+                ///  The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1
+                CORE0_IBUS_WORLD: u1,
+                padding: u28,
+            }),
+            ///  This description will be updated in the near future.
+            CORE0_IBUS_REJECT_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the virtual address of CPU access ibus when authentication fail.
+                CORE0_IBUS_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_MMU_FAULT_CONTENT: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the content of mmu entry which cause mmu fault..
+                CACHE_MMU_FAULT_CONTENT: u10,
+                ///  The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.
+                CACHE_MMU_FAULT_CODE: u4,
+                padding: u18,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_MMU_FAULT_VADDR: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to indicate the virtual address which cause mmu fault..
+                CACHE_MMU_FAULT_VADDR: u32,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_WRAP_AROUND_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable wrap around mode when read data from flash.
+                CACHE_FLASH_WRAP_AROUND: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_MMU_POWER_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable
+                CACHE_MMU_MEM_FORCE_ON: u1,
+                ///  The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down
+                CACHE_MMU_MEM_FORCE_PD: u1,
+                ///  The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up
+                CACHE_MMU_MEM_FORCE_PU: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_STATE: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state
+                ICACHE_STATE: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                RECORD_DISABLE_DB_ENCRYPT: u1,
+                ///  Reserved.
+                RECORD_DISABLE_G0CB_DECRYPT: u1,
+                padding: u30,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.
+                CLK_FORCE_ON_MANUAL_CRYPT: u1,
+                ///  The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.
+                CLK_FORCE_ON_AUTO_CRYPT: u1,
+                ///  The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.
+                CLK_FORCE_ON_CRYPT: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_PRELOAD_INT_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to indicate the interrupt by icache pre-load done.
+                ICACHE_PRELOAD_INT_ST: u1,
+                ///  The bit is used to enable the interrupt by icache pre-load done.
+                ICACHE_PRELOAD_INT_ENA: u1,
+                ///  The bit is used to clear the interrupt by icache pre-load done.
+                ICACHE_PRELOAD_INT_CLR: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_SYNC_INT_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to indicate the interrupt by icache sync done.
+                ICACHE_SYNC_INT_ST: u1,
+                ///  The bit is used to enable the interrupt by icache sync done.
+                ICACHE_SYNC_INT_ENA: u1,
+                ///  The bit is used to clear the interrupt by icache sync done.
+                ICACHE_SYNC_INT_CLR: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_MMU_OWNER: mmio.Mmio(packed struct(u32) {
+                ///  The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus
+                CACHE_MMU_OWNER: u4,
+                padding: u28,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_CONF_MISC: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to disable checking mmu entry fault by preload operation.
+                CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT: u1,
+                ///  The bit is used to disable checking mmu entry fault by sync operation.
+                CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT: u1,
+                ///  The bit is used to enable cache trace function.
+                CACHE_TRACE_ENA: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_FREEZE: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable icache freeze mode
+                ENA: u1,
+                ///  The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss
+                MODE: u1,
+                ///  The bit is used to indicate icache freeze success
+                DONE: u1,
+                padding: u29,
+            }),
+            ///  This description will be updated in the near future.
+            ICACHE_ATOMIC_OPERATE_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.
+                ICACHE_ATOMIC_OPERATE_ENA: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            CACHE_REQUEST: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to disable request recording which could cause performance issue
+                BYPASS: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_PMS_TBL_LOCK: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the ibus permission control section boundary0
+                IBUS_PMS_LOCK: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_PMS_TBL_BOUNDARY0: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the ibus permission control section boundary0
+                IBUS_PMS_BOUNDARY0: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_PMS_TBL_BOUNDARY1: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the ibus permission control section boundary1
+                IBUS_PMS_BOUNDARY1: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_PMS_TBL_BOUNDARY2: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the ibus permission control section boundary2
+                IBUS_PMS_BOUNDARY2: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            IBUS_PMS_TBL_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
+                IBUS_PMS_SCT1_ATTR: u4,
+                ///  The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
+                IBUS_PMS_SCT2_ATTR: u4,
+                padding: u24,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_PMS_TBL_LOCK: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the ibus permission control section boundary0
+                DBUS_PMS_LOCK: u1,
+                padding: u31,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_PMS_TBL_BOUNDARY0: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the dbus permission control section boundary0
+                DBUS_PMS_BOUNDARY0: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_PMS_TBL_BOUNDARY1: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the dbus permission control section boundary1
+                DBUS_PMS_BOUNDARY1: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_PMS_TBL_BOUNDARY2: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure the dbus permission control section boundary2
+                DBUS_PMS_BOUNDARY2: u12,
+                padding: u20,
+            }),
+            ///  This description will be updated in the near future.
+            DBUS_PMS_TBL_ATTR: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1
+                DBUS_PMS_SCT1_ATTR: u2,
+                ///  The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1
+                DBUS_PMS_SCT2_ATTR: u2,
+                padding: u28,
+            }),
+            ///  This description will be updated in the near future.
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  clock gate enable.
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            reserved1020: [760]u8,
+            ///  This description will be updated in the near future.
+            REG_DATE: mmio.Mmio(packed struct(u32) {
+                ///  version information
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  General Purpose Input/Output
+        pub const GPIO = extern struct {
+            ///  GPIO bit select register
+            BT_SELECT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO bit select register
+                BT_SEL: u32,
+            }),
+            ///  GPIO output register
+            OUT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output register for GPIO0-25
+                DATA_ORIG: u26,
+                padding: u6,
+            }),
+            ///  GPIO output set register
+            OUT_W1TS: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output set register for GPIO0-25
+                OUT_W1TS: u26,
+                padding: u6,
+            }),
+            ///  GPIO output clear register
+            OUT_W1TC: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output clear register for GPIO0-25
+                OUT_W1TC: u26,
+                padding: u6,
+            }),
+            reserved28: [12]u8,
+            ///  GPIO sdio select register
+            SDIO_SELECT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO sdio select register
+                SDIO_SEL: u8,
+                padding: u24,
+            }),
+            ///  GPIO output enable register
+            ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output enable register for GPIO0-25
+                DATA: u26,
+                padding: u6,
+            }),
+            ///  GPIO output enable set register
+            ENABLE_W1TS: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output enable set register for GPIO0-25
+                ENABLE_W1TS: u26,
+                padding: u6,
+            }),
+            ///  GPIO output enable clear register
+            ENABLE_W1TC: mmio.Mmio(packed struct(u32) {
+                ///  GPIO output enable clear register for GPIO0-25
+                ENABLE_W1TC: u26,
+                padding: u6,
+            }),
+            reserved56: [12]u8,
+            ///  pad strapping register
+            STRAP: mmio.Mmio(packed struct(u32) {
+                ///  pad strapping register
+                STRAPPING: u16,
+                padding: u16,
+            }),
+            ///  GPIO input register
+            IN: mmio.Mmio(packed struct(u32) {
+                ///  GPIO input register for GPIO0-25
+                DATA_NEXT: u26,
+                padding: u6,
+            }),
+            reserved68: [4]u8,
+            ///  GPIO interrupt status register
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  GPIO interrupt status register for GPIO0-25
+                INTERRUPT: u26,
+                padding: u6,
+            }),
+            ///  GPIO interrupt status set register
+            STATUS_W1TS: mmio.Mmio(packed struct(u32) {
+                ///  GPIO interrupt status set register for GPIO0-25
+                STATUS_W1TS: u26,
+                padding: u6,
+            }),
+            ///  GPIO interrupt status clear register
+            STATUS_W1TC: mmio.Mmio(packed struct(u32) {
+                ///  GPIO interrupt status clear register for GPIO0-25
+                STATUS_W1TC: u26,
+                padding: u6,
+            }),
+            reserved92: [12]u8,
+            ///  GPIO PRO_CPU interrupt status register
+            PCPU_INT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO PRO_CPU interrupt status register for GPIO0-25
+                PROCPU_INT: u26,
+                padding: u6,
+            }),
+            ///  GPIO PRO_CPU(not shielded) interrupt status register
+            PCPU_NMI_INT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25
+                PROCPU_NMI_INT: u26,
+                padding: u6,
+            }),
+            ///  GPIO CPUSDIO interrupt status register
+            CPUSDIO_INT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO CPUSDIO interrupt status register for GPIO0-25
+                SDIO_INT: u26,
+                padding: u6,
+            }),
+            reserved116: [12]u8,
+            ///  GPIO pin configuration register
+            PIN: [26]mmio.Mmio(packed struct(u32) {
+                ///  set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
+                PIN_SYNC2_BYPASS: u2,
+                ///  set this bit to select pad driver. 1:open-drain. :normal.
+                PIN_PAD_DRIVER: u1,
+                ///  set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
+                PIN_SYNC1_BYPASS: u2,
+                reserved7: u2,
+                ///  set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level
+                PIN_INT_TYPE: u3,
+                ///  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
+                PIN_WAKEUP_ENABLE: u1,
+                ///  reserved
+                PIN_CONFIG: u2,
+                ///  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.
+                PIN_INT_ENA: u5,
+                padding: u14,
+            }),
+            reserved332: [112]u8,
+            ///  GPIO interrupt source register
+            STATUS_NEXT: mmio.Mmio(packed struct(u32) {
+                ///  GPIO interrupt source register for GPIO0-25
+                STATUS_INTERRUPT_NEXT: u26,
+                padding: u6,
+            }),
+            reserved340: [4]u8,
+            ///  GPIO input function configuration register
+            FUNC_IN_SEL_CFG: [128]mmio.Mmio(packed struct(u32) {
+                ///  set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level.
+                IN_SEL: u5,
+                ///  set this bit to invert input signal. 1:invert. :not invert.
+                IN_INV_SEL: u1,
+                ///  set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
+                SEL: u1,
+                padding: u25,
+            }),
+            reserved1364: [512]u8,
+            ///  GPIO output function select register
+            FUNC_OUT_SEL_CFG: [26]mmio.Mmio(packed struct(u32) {
+                ///  The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].
+                OUT_SEL: u8,
+                ///  set this bit to invert output signal.1:invert.:not invert.
+                INV_SEL: u1,
+                ///  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal.
+                OEN_SEL: u1,
+                ///  set this bit to invert output enable signal.1:invert.:not invert.
+                OEN_INV_SEL: u1,
+                padding: u21,
+            }),
+            reserved1580: [112]u8,
+            ///  GPIO clock gate register
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  set this bit to enable GPIO clock gate
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            reserved1788: [204]u8,
+            ///  GPIO version register
+            REG_DATE: mmio.Mmio(packed struct(u32) {
+                ///  version register
+                REG_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  Sigma-Delta Modulation
+        pub const GPIOSD = extern struct {
+            ///  Duty Cycle Configure Register of SDM%s
+            SIGMADELTA: [4]mmio.Mmio(packed struct(u32) {
+                ///  This field is used to configure the duty cycle of sigma delta modulation output.
+                SD0_IN: u8,
+                ///  This field is used to set a divider value to divide APB clock.
+                SD0_PRESCALE: u8,
+                padding: u16,
+            }),
+            reserved32: [16]u8,
+            ///  Clock Gating Configure Register
+            SIGMADELTA_CG: mmio.Mmio(packed struct(u32) {
+                reserved31: u31,
+                ///  Clock enable bit of configuration registers for sigma delta modulation.
+                CLK_EN: u1,
+            }),
+            ///  MISC Register
+            SIGMADELTA_MISC: mmio.Mmio(packed struct(u32) {
+                reserved30: u30,
+                ///  Clock enable bit of sigma delta modulation.
+                FUNCTION_CLK_EN: u1,
+                ///  Reserved.
+                SPI_SWAP: u1,
+            }),
+            ///  Version Control Register
+            SIGMADELTA_VERSION: mmio.Mmio(packed struct(u32) {
+                ///  Version control register.
+                GPIO_SD_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  HMAC (Hash-based Message Authentication Code) Accelerator
+        pub const HMAC = extern struct {
+            reserved64: [64]u8,
+            ///  Process control register 0.
+            SET_START: mmio.Mmio(packed struct(u32) {
+                ///  Start hmac operation.
+                SET_START: u1,
+                padding: u31,
+            }),
+            ///  Configure purpose.
+            SET_PARA_PURPOSE: mmio.Mmio(packed struct(u32) {
+                ///  Set hmac parameter purpose.
+                PURPOSE_SET: u4,
+                padding: u28,
+            }),
+            ///  Configure key.
+            SET_PARA_KEY: mmio.Mmio(packed struct(u32) {
+                ///  Set hmac parameter key.
+                KEY_SET: u3,
+                padding: u29,
+            }),
+            ///  Finish initial configuration.
+            SET_PARA_FINISH: mmio.Mmio(packed struct(u32) {
+                ///  Finish hmac configuration.
+                SET_PARA_END: u1,
+                padding: u31,
+            }),
+            ///  Process control register 1.
+            SET_MESSAGE_ONE: mmio.Mmio(packed struct(u32) {
+                ///  Call SHA to calculate one message block.
+                SET_TEXT_ONE: u1,
+                padding: u31,
+            }),
+            ///  Process control register 2.
+            SET_MESSAGE_ING: mmio.Mmio(packed struct(u32) {
+                ///  Continue typical hmac.
+                SET_TEXT_ING: u1,
+                padding: u31,
+            }),
+            ///  Process control register 3.
+            SET_MESSAGE_END: mmio.Mmio(packed struct(u32) {
+                ///  Start hardware padding.
+                SET_TEXT_END: u1,
+                padding: u31,
+            }),
+            ///  Process control register 4.
+            SET_RESULT_FINISH: mmio.Mmio(packed struct(u32) {
+                ///  After read result from upstream, then let hmac back to idle.
+                SET_RESULT_END: u1,
+                padding: u31,
+            }),
+            ///  Invalidate register 0.
+            SET_INVALIDATE_JTAG: mmio.Mmio(packed struct(u32) {
+                ///  Clear result from hmac downstream JTAG.
+                SET_INVALIDATE_JTAG: u1,
+                padding: u31,
+            }),
+            ///  Invalidate register 1.
+            SET_INVALIDATE_DS: mmio.Mmio(packed struct(u32) {
+                ///  Clear result from hmac downstream DS.
+                SET_INVALIDATE_DS: u1,
+                padding: u31,
+            }),
+            ///  Error register.
+            QUERY_ERROR: mmio.Mmio(packed struct(u32) {
+                ///  Hmac configuration state. 0: key are agree with purpose. 1: error
+                QUREY_CHECK: u1,
+                padding: u31,
+            }),
+            ///  Busy register.
+            QUERY_BUSY: mmio.Mmio(packed struct(u32) {
+                ///  Hmac state. 1'b0: idle. 1'b1: busy
+                BUSY_STATE: u1,
+                padding: u31,
+            }),
+            reserved128: [16]u8,
+            ///  Message block memory.
+            WR_MESSAGE_MEM: [64]u8,
+            ///  Result from upstream.
+            RD_RESULT_MEM: [32]u8,
+            reserved240: [16]u8,
+            ///  Process control register 5.
+            SET_MESSAGE_PAD: mmio.Mmio(packed struct(u32) {
+                ///  Start software padding.
+                SET_TEXT_PAD: u1,
+                padding: u31,
+            }),
+            ///  Process control register 6.
+            ONE_BLOCK: mmio.Mmio(packed struct(u32) {
+                ///  Don't have to do padding.
+                SET_ONE_BLOCK: u1,
+                padding: u31,
+            }),
+            ///  Jtag register 0.
+            SOFT_JTAG_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  Turn on JTAG verification.
+                SOFT_JTAG_CTRL: u1,
+                padding: u31,
+            }),
+            ///  Jtag register 1.
+            WR_JTAG: mmio.Mmio(packed struct(u32) {
+                ///  32-bit of key to be compared.
+                WR_JTAG: u32,
+            }),
+        };
+
+        ///  I2C (Inter-Integrated Circuit) Controller
+        pub const I2C0 = extern struct {
+            ///  I2C_SCL_LOW_PERIOD_REG
+            SCL_LOW_PERIOD: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_low_period
+                SCL_LOW_PERIOD: u9,
+                padding: u23,
+            }),
+            ///  I2C_CTR_REG
+            CTR: mmio.Mmio(packed struct(u32) {
+                ///  reg_sda_force_out
+                SDA_FORCE_OUT: u1,
+                ///  reg_scl_force_out
+                SCL_FORCE_OUT: u1,
+                ///  reg_sample_scl_level
+                SAMPLE_SCL_LEVEL: u1,
+                ///  reg_rx_full_ack_level
+                RX_FULL_ACK_LEVEL: u1,
+                ///  reg_ms_mode
+                MS_MODE: u1,
+                ///  reg_trans_start
+                TRANS_START: u1,
+                ///  reg_tx_lsb_first
+                TX_LSB_FIRST: u1,
+                ///  reg_rx_lsb_first
+                RX_LSB_FIRST: u1,
+                ///  reg_clk_en
+                CLK_EN: u1,
+                ///  reg_arbitration_en
+                ARBITRATION_EN: u1,
+                ///  reg_fsm_rst
+                FSM_RST: u1,
+                ///  reg_conf_upgate
+                CONF_UPGATE: u1,
+                ///  reg_slv_tx_auto_start_en
+                SLV_TX_AUTO_START_EN: u1,
+                ///  reg_addr_10bit_rw_check_en
+                ADDR_10BIT_RW_CHECK_EN: u1,
+                ///  reg_addr_broadcasting_en
+                ADDR_BROADCASTING_EN: u1,
+                padding: u17,
+            }),
+            ///  I2C_SR_REG
+            SR: mmio.Mmio(packed struct(u32) {
+                ///  reg_resp_rec
+                RESP_REC: u1,
+                ///  reg_slave_rw
+                SLAVE_RW: u1,
+                reserved3: u1,
+                ///  reg_arb_lost
+                ARB_LOST: u1,
+                ///  reg_bus_busy
+                BUS_BUSY: u1,
+                ///  reg_slave_addressed
+                SLAVE_ADDRESSED: u1,
+                reserved8: u2,
+                ///  reg_rxfifo_cnt
+                RXFIFO_CNT: u6,
+                ///  reg_stretch_cause
+                STRETCH_CAUSE: u2,
+                reserved18: u2,
+                ///  reg_txfifo_cnt
+                TXFIFO_CNT: u6,
+                ///  reg_scl_main_state_last
+                SCL_MAIN_STATE_LAST: u3,
+                reserved28: u1,
+                ///  reg_scl_state_last
+                SCL_STATE_LAST: u3,
+                padding: u1,
+            }),
+            ///  I2C_TO_REG
+            TO: mmio.Mmio(packed struct(u32) {
+                ///  reg_time_out_value
+                TIME_OUT_VALUE: u5,
+                ///  reg_time_out_en
+                TIME_OUT_EN: u1,
+                padding: u26,
+            }),
+            ///  I2C_SLAVE_ADDR_REG
+            SLAVE_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_slave_addr
+                SLAVE_ADDR: u15,
+                reserved31: u16,
+                ///  reg_addr_10bit_en
+                ADDR_10BIT_EN: u1,
+            }),
+            ///  I2C_FIFO_ST_REG
+            FIFO_ST: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_raddr
+                RXFIFO_RADDR: u5,
+                ///  reg_rxfifo_waddr
+                RXFIFO_WADDR: u5,
+                ///  reg_txfifo_raddr
+                TXFIFO_RADDR: u5,
+                ///  reg_txfifo_waddr
+                TXFIFO_WADDR: u5,
+                reserved22: u2,
+                ///  reg_slave_rw_point
+                SLAVE_RW_POINT: u8,
+                padding: u2,
+            }),
+            ///  I2C_FIFO_CONF_REG
+            FIFO_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_wm_thrhd
+                RXFIFO_WM_THRHD: u5,
+                ///  reg_txfifo_wm_thrhd
+                TXFIFO_WM_THRHD: u5,
+                ///  reg_nonfifo_en
+                NONFIFO_EN: u1,
+                ///  reg_fifo_addr_cfg_en
+                FIFO_ADDR_CFG_EN: u1,
+                ///  reg_rx_fifo_rst
+                RX_FIFO_RST: u1,
+                ///  reg_tx_fifo_rst
+                TX_FIFO_RST: u1,
+                ///  reg_fifo_prt_en
+                FIFO_PRT_EN: u1,
+                padding: u17,
+            }),
+            ///  I2C_FIFO_DATA_REG
+            DATA: mmio.Mmio(packed struct(u32) {
+                ///  reg_fifo_rdata
+                FIFO_RDATA: u8,
+                padding: u24,
+            }),
+            ///  I2C_INT_RAW_REG
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_wm_int_raw
+                RXFIFO_WM_INT_RAW: u1,
+                ///  reg_txfifo_wm_int_raw
+                TXFIFO_WM_INT_RAW: u1,
+                ///  reg_rxfifo_ovf_int_raw
+                RXFIFO_OVF_INT_RAW: u1,
+                ///  reg_end_detect_int_raw
+                END_DETECT_INT_RAW: u1,
+                ///  reg_byte_trans_done_int_raw
+                BYTE_TRANS_DONE_INT_RAW: u1,
+                ///  reg_arbitration_lost_int_raw
+                ARBITRATION_LOST_INT_RAW: u1,
+                ///  reg_mst_txfifo_udf_int_raw
+                MST_TXFIFO_UDF_INT_RAW: u1,
+                ///  reg_trans_complete_int_raw
+                TRANS_COMPLETE_INT_RAW: u1,
+                ///  reg_time_out_int_raw
+                TIME_OUT_INT_RAW: u1,
+                ///  reg_trans_start_int_raw
+                TRANS_START_INT_RAW: u1,
+                ///  reg_nack_int_raw
+                NACK_INT_RAW: u1,
+                ///  reg_txfifo_ovf_int_raw
+                TXFIFO_OVF_INT_RAW: u1,
+                ///  reg_rxfifo_udf_int_raw
+                RXFIFO_UDF_INT_RAW: u1,
+                ///  reg_scl_st_to_int_raw
+                SCL_ST_TO_INT_RAW: u1,
+                ///  reg_scl_main_st_to_int_raw
+                SCL_MAIN_ST_TO_INT_RAW: u1,
+                ///  reg_det_start_int_raw
+                DET_START_INT_RAW: u1,
+                ///  reg_slave_stretch_int_raw
+                SLAVE_STRETCH_INT_RAW: u1,
+                ///  reg_general_call_int_raw
+                GENERAL_CALL_INT_RAW: u1,
+                padding: u14,
+            }),
+            ///  I2C_INT_CLR_REG
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_wm_int_clr
+                RXFIFO_WM_INT_CLR: u1,
+                ///  reg_txfifo_wm_int_clr
+                TXFIFO_WM_INT_CLR: u1,
+                ///  reg_rxfifo_ovf_int_clr
+                RXFIFO_OVF_INT_CLR: u1,
+                ///  reg_end_detect_int_clr
+                END_DETECT_INT_CLR: u1,
+                ///  reg_byte_trans_done_int_clr
+                BYTE_TRANS_DONE_INT_CLR: u1,
+                ///  reg_arbitration_lost_int_clr
+                ARBITRATION_LOST_INT_CLR: u1,
+                ///  reg_mst_txfifo_udf_int_clr
+                MST_TXFIFO_UDF_INT_CLR: u1,
+                ///  reg_trans_complete_int_clr
+                TRANS_COMPLETE_INT_CLR: u1,
+                ///  reg_time_out_int_clr
+                TIME_OUT_INT_CLR: u1,
+                ///  reg_trans_start_int_clr
+                TRANS_START_INT_CLR: u1,
+                ///  reg_nack_int_clr
+                NACK_INT_CLR: u1,
+                ///  reg_txfifo_ovf_int_clr
+                TXFIFO_OVF_INT_CLR: u1,
+                ///  reg_rxfifo_udf_int_clr
+                RXFIFO_UDF_INT_CLR: u1,
+                ///  reg_scl_st_to_int_clr
+                SCL_ST_TO_INT_CLR: u1,
+                ///  reg_scl_main_st_to_int_clr
+                SCL_MAIN_ST_TO_INT_CLR: u1,
+                ///  reg_det_start_int_clr
+                DET_START_INT_CLR: u1,
+                ///  reg_slave_stretch_int_clr
+                SLAVE_STRETCH_INT_CLR: u1,
+                ///  reg_general_call_int_clr
+                GENERAL_CALL_INT_CLR: u1,
+                padding: u14,
+            }),
+            ///  I2C_INT_ENA_REG
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_wm_int_ena
+                RXFIFO_WM_INT_ENA: u1,
+                ///  reg_txfifo_wm_int_ena
+                TXFIFO_WM_INT_ENA: u1,
+                ///  reg_rxfifo_ovf_int_ena
+                RXFIFO_OVF_INT_ENA: u1,
+                ///  reg_end_detect_int_ena
+                END_DETECT_INT_ENA: u1,
+                ///  reg_byte_trans_done_int_ena
+                BYTE_TRANS_DONE_INT_ENA: u1,
+                ///  reg_arbitration_lost_int_ena
+                ARBITRATION_LOST_INT_ENA: u1,
+                ///  reg_mst_txfifo_udf_int_ena
+                MST_TXFIFO_UDF_INT_ENA: u1,
+                ///  reg_trans_complete_int_ena
+                TRANS_COMPLETE_INT_ENA: u1,
+                ///  reg_time_out_int_ena
+                TIME_OUT_INT_ENA: u1,
+                ///  reg_trans_start_int_ena
+                TRANS_START_INT_ENA: u1,
+                ///  reg_nack_int_ena
+                NACK_INT_ENA: u1,
+                ///  reg_txfifo_ovf_int_ena
+                TXFIFO_OVF_INT_ENA: u1,
+                ///  reg_rxfifo_udf_int_ena
+                RXFIFO_UDF_INT_ENA: u1,
+                ///  reg_scl_st_to_int_ena
+                SCL_ST_TO_INT_ENA: u1,
+                ///  reg_scl_main_st_to_int_ena
+                SCL_MAIN_ST_TO_INT_ENA: u1,
+                ///  reg_det_start_int_ena
+                DET_START_INT_ENA: u1,
+                ///  reg_slave_stretch_int_ena
+                SLAVE_STRETCH_INT_ENA: u1,
+                ///  reg_general_call_int_ena
+                GENERAL_CALL_INT_ENA: u1,
+                padding: u14,
+            }),
+            ///  I2C_INT_STATUS_REG
+            INT_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_wm_int_st
+                RXFIFO_WM_INT_ST: u1,
+                ///  reg_txfifo_wm_int_st
+                TXFIFO_WM_INT_ST: u1,
+                ///  reg_rxfifo_ovf_int_st
+                RXFIFO_OVF_INT_ST: u1,
+                ///  reg_end_detect_int_st
+                END_DETECT_INT_ST: u1,
+                ///  reg_byte_trans_done_int_st
+                BYTE_TRANS_DONE_INT_ST: u1,
+                ///  reg_arbitration_lost_int_st
+                ARBITRATION_LOST_INT_ST: u1,
+                ///  reg_mst_txfifo_udf_int_st
+                MST_TXFIFO_UDF_INT_ST: u1,
+                ///  reg_trans_complete_int_st
+                TRANS_COMPLETE_INT_ST: u1,
+                ///  reg_time_out_int_st
+                TIME_OUT_INT_ST: u1,
+                ///  reg_trans_start_int_st
+                TRANS_START_INT_ST: u1,
+                ///  reg_nack_int_st
+                NACK_INT_ST: u1,
+                ///  reg_txfifo_ovf_int_st
+                TXFIFO_OVF_INT_ST: u1,
+                ///  reg_rxfifo_udf_int_st
+                RXFIFO_UDF_INT_ST: u1,
+                ///  reg_scl_st_to_int_st
+                SCL_ST_TO_INT_ST: u1,
+                ///  reg_scl_main_st_to_int_st
+                SCL_MAIN_ST_TO_INT_ST: u1,
+                ///  reg_det_start_int_st
+                DET_START_INT_ST: u1,
+                ///  reg_slave_stretch_int_st
+                SLAVE_STRETCH_INT_ST: u1,
+                ///  reg_general_call_int_st
+                GENERAL_CALL_INT_ST: u1,
+                padding: u14,
+            }),
+            ///  I2C_SDA_HOLD_REG
+            SDA_HOLD: mmio.Mmio(packed struct(u32) {
+                ///  reg_sda_hold_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_SDA_SAMPLE_REG
+            SDA_SAMPLE: mmio.Mmio(packed struct(u32) {
+                ///  reg_sda_sample_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_SCL_HIGH_PERIOD_REG
+            SCL_HIGH_PERIOD: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_high_period
+                SCL_HIGH_PERIOD: u9,
+                ///  reg_scl_wait_high_period
+                SCL_WAIT_HIGH_PERIOD: u7,
+                padding: u16,
+            }),
+            reserved64: [4]u8,
+            ///  I2C_SCL_START_HOLD_REG
+            SCL_START_HOLD: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_start_hold_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_SCL_RSTART_SETUP_REG
+            SCL_RSTART_SETUP: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_rstart_setup_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_SCL_STOP_HOLD_REG
+            SCL_STOP_HOLD: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_stop_hold_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_SCL_STOP_SETUP_REG
+            SCL_STOP_SETUP: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_stop_setup_time
+                TIME: u9,
+                padding: u23,
+            }),
+            ///  I2C_FILTER_CFG_REG
+            FILTER_CFG: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_filter_thres
+                SCL_FILTER_THRES: u4,
+                ///  reg_sda_filter_thres
+                SDA_FILTER_THRES: u4,
+                ///  reg_scl_filter_en
+                SCL_FILTER_EN: u1,
+                ///  reg_sda_filter_en
+                SDA_FILTER_EN: u1,
+                padding: u22,
+            }),
+            ///  I2C_CLK_CONF_REG
+            CLK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_sclk_div_num
+                SCLK_DIV_NUM: u8,
+                ///  reg_sclk_div_a
+                SCLK_DIV_A: u6,
+                ///  reg_sclk_div_b
+                SCLK_DIV_B: u6,
+                ///  reg_sclk_sel
+                SCLK_SEL: u1,
+                ///  reg_sclk_active
+                SCLK_ACTIVE: u1,
+                padding: u10,
+            }),
+            ///  I2C_COMD%s_REG
+            COMD: [8]mmio.Mmio(packed struct(u32) {
+                ///  reg_command
+                COMMAND: u14,
+                reserved31: u17,
+                ///  reg_command_done
+                COMMAND_DONE: u1,
+            }),
+            ///  I2C_SCL_ST_TIME_OUT_REG
+            SCL_ST_TIME_OUT: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_st_to_regno more than 23
+                SCL_ST_TO_I2C: u5,
+                padding: u27,
+            }),
+            ///  I2C_SCL_MAIN_ST_TIME_OUT_REG
+            SCL_MAIN_ST_TIME_OUT: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_main_st_to_regno more than 23
+                SCL_MAIN_ST_TO_I2C: u5,
+                padding: u27,
+            }),
+            ///  I2C_SCL_SP_CONF_REG
+            SCL_SP_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_scl_rst_slv_en
+                SCL_RST_SLV_EN: u1,
+                ///  reg_scl_rst_slv_num
+                SCL_RST_SLV_NUM: u5,
+                ///  reg_scl_pd_en
+                SCL_PD_EN: u1,
+                ///  reg_sda_pd_en
+                SDA_PD_EN: u1,
+                padding: u24,
+            }),
+            ///  I2C_SCL_STRETCH_CONF_REG
+            SCL_STRETCH_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_stretch_protect_num
+                STRETCH_PROTECT_NUM: u10,
+                ///  reg_slave_scl_stretch_en
+                SLAVE_SCL_STRETCH_EN: u1,
+                ///  reg_slave_scl_stretch_clr
+                SLAVE_SCL_STRETCH_CLR: u1,
+                ///  reg_slave_byte_ack_ctl_en
+                SLAVE_BYTE_ACK_CTL_EN: u1,
+                ///  reg_slave_byte_ack_lvl
+                SLAVE_BYTE_ACK_LVL: u1,
+                padding: u18,
+            }),
+            reserved248: [112]u8,
+            ///  I2C_DATE_REG
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_date
+                DATE: u32,
+            }),
+            reserved256: [4]u8,
+            ///  I2C_TXFIFO_START_ADDR_REG
+            TXFIFO_START_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_txfifo_start_addr.
+                TXFIFO_START_ADDR: u32,
+            }),
+            reserved384: [124]u8,
+            ///  I2C_RXFIFO_START_ADDR_REG
+            RXFIFO_START_ADDR: mmio.Mmio(packed struct(u32) {
+                ///  reg_rxfifo_start_addr.
+                RXFIFO_START_ADDR: u32,
+            }),
+        };
+
+        ///  I2S (Inter-IC Sound) Controller
+        pub const I2S = extern struct {
+            reserved12: [12]u8,
+            ///  I2S interrupt raw register, valid in level.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt status bit for the i2s_rx_done_int interrupt
+                RX_DONE_INT_RAW: u1,
+                ///  The raw interrupt status bit for the i2s_tx_done_int interrupt
+                TX_DONE_INT_RAW: u1,
+                ///  The raw interrupt status bit for the i2s_rx_hung_int interrupt
+                RX_HUNG_INT_RAW: u1,
+                ///  The raw interrupt status bit for the i2s_tx_hung_int interrupt
+                TX_HUNG_INT_RAW: u1,
+                padding: u28,
+            }),
+            ///  I2S interrupt status register.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The masked interrupt status bit for the i2s_rx_done_int interrupt
+                RX_DONE_INT_ST: u1,
+                ///  The masked interrupt status bit for the i2s_tx_done_int interrupt
+                TX_DONE_INT_ST: u1,
+                ///  The masked interrupt status bit for the i2s_rx_hung_int interrupt
+                RX_HUNG_INT_ST: u1,
+                ///  The masked interrupt status bit for the i2s_tx_hung_int interrupt
+                TX_HUNG_INT_ST: u1,
+                padding: u28,
+            }),
+            ///  I2S interrupt enable register.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The interrupt enable bit for the i2s_rx_done_int interrupt
+                RX_DONE_INT_ENA: u1,
+                ///  The interrupt enable bit for the i2s_tx_done_int interrupt
+                TX_DONE_INT_ENA: u1,
+                ///  The interrupt enable bit for the i2s_rx_hung_int interrupt
+                RX_HUNG_INT_ENA: u1,
+                ///  The interrupt enable bit for the i2s_tx_hung_int interrupt
+                TX_HUNG_INT_ENA: u1,
+                padding: u28,
+            }),
+            ///  I2S interrupt clear register.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the i2s_rx_done_int interrupt
+                RX_DONE_INT_CLR: u1,
+                ///  Set this bit to clear the i2s_tx_done_int interrupt
+                TX_DONE_INT_CLR: u1,
+                ///  Set this bit to clear the i2s_rx_hung_int interrupt
+                RX_HUNG_INT_CLR: u1,
+                ///  Set this bit to clear the i2s_tx_hung_int interrupt
+                TX_HUNG_INT_CLR: u1,
+                padding: u28,
+            }),
+            reserved32: [4]u8,
+            ///  I2S RX configure register
+            RX_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to reset receiver
+                RX_RESET: u1,
+                ///  Set this bit to reset Rx AFIFO
+                RX_FIFO_RESET: u1,
+                ///  Set this bit to start receiving data
+                RX_START: u1,
+                ///  Set this bit to enable slave receiver mode
+                RX_SLAVE_MOD: u1,
+                reserved5: u1,
+                ///  Set this bit to enable receiver in mono mode
+                RX_MONO: u1,
+                reserved7: u1,
+                ///  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+                RX_BIG_ENDIAN: u1,
+                ///  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.
+                RX_UPDATE: u1,
+                ///  1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.
+                RX_MONO_FST_VLD: u1,
+                ///  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+                RX_PCM_CONF: u2,
+                ///  Set this bit to bypass Compress/Decompress module for received data.
+                RX_PCM_BYPASS: u1,
+                ///  0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
+                RX_STOP_MODE: u2,
+                ///  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
+                RX_LEFT_ALIGN: u1,
+                ///  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
+                RX_24_FILL_EN: u1,
+                ///  0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
+                RX_WS_IDLE_POL: u1,
+                ///  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.
+                RX_BIT_ORDER: u1,
+                ///  1: Enable I2S TDM Rx mode . 0: Disable.
+                RX_TDM_EN: u1,
+                ///  1: Enable I2S PDM Rx mode . 0: Disable.
+                RX_PDM_EN: u1,
+                padding: u11,
+            }),
+            ///  I2S TX configure register
+            TX_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to reset transmitter
+                TX_RESET: u1,
+                ///  Set this bit to reset Tx AFIFO
+                TX_FIFO_RESET: u1,
+                ///  Set this bit to start transmitting data
+                TX_START: u1,
+                ///  Set this bit to enable slave transmitter mode
+                TX_SLAVE_MOD: u1,
+                reserved5: u1,
+                ///  Set this bit to enable transmitter in mono mode
+                TX_MONO: u1,
+                ///  1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
+                TX_CHAN_EQUAL: u1,
+                ///  I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
+                TX_BIG_ENDIAN: u1,
+                ///  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.
+                TX_UPDATE: u1,
+                ///  1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.
+                TX_MONO_FST_VLD: u1,
+                ///  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
+                TX_PCM_CONF: u2,
+                ///  Set this bit to bypass Compress/Decompress module for transmitted data.
+                TX_PCM_BYPASS: u1,
+                ///  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
+                TX_STOP_EN: u1,
+                reserved15: u1,
+                ///  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
+                TX_LEFT_ALIGN: u1,
+                ///  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
+                TX_24_FILL_EN: u1,
+                ///  0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel.
+                TX_WS_IDLE_POL: u1,
+                ///  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.
+                TX_BIT_ORDER: u1,
+                ///  1: Enable I2S TDM Tx mode . 0: Disable.
+                TX_TDM_EN: u1,
+                ///  1: Enable I2S PDM Tx mode . 0: Disable.
+                TX_PDM_EN: u1,
+                reserved24: u3,
+                ///  I2S transmitter channel mode configuration bits.
+                TX_CHAN_MOD: u3,
+                ///  Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.
+                SIG_LOOPBACK: u1,
+                padding: u4,
+            }),
+            ///  I2S RX configure register 1
+            RX_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
+                RX_TDM_WS_WIDTH: u7,
+                ///  Bit clock configuration bits in receiver mode.
+                RX_BCK_DIV_NUM: u6,
+                ///  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
+                RX_BITS_MOD: u5,
+                ///  I2S Rx half sample bits -1.
+                RX_HALF_SAMPLE_BITS: u6,
+                ///  The Rx bit number for each channel minus 1in TDM mode.
+                RX_TDM_CHAN_BITS: u5,
+                ///  Set this bit to enable receiver in Phillips standard mode
+                RX_MSB_SHIFT: u1,
+                padding: u2,
+            }),
+            ///  I2S TX configure register 1
+            TX_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
+                TX_TDM_WS_WIDTH: u7,
+                ///  Bit clock configuration bits in transmitter mode.
+                TX_BCK_DIV_NUM: u6,
+                ///  Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
+                TX_BITS_MOD: u5,
+                ///  I2S Tx half sample bits -1.
+                TX_HALF_SAMPLE_BITS: u6,
+                ///  The Tx bit number for each channel minus 1in TDM mode.
+                TX_TDM_CHAN_BITS: u5,
+                ///  Set this bit to enable transmitter in Phillips standard mode
+                TX_MSB_SHIFT: u1,
+                ///  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.
+                TX_BCK_NO_DLY: u1,
+                padding: u1,
+            }),
+            ///  I2S RX clock configure register
+            RX_CLKM_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Integral I2S clock divider value
+                RX_CLKM_DIV_NUM: u8,
+                reserved26: u18,
+                ///  I2S Rx module clock enable signal.
+                RX_CLK_ACTIVE: u1,
+                ///  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+                RX_CLK_SEL: u2,
+                ///  0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.
+                MCLK_SEL: u1,
+                padding: u2,
+            }),
+            ///  I2S TX clock configure register
+            TX_CLKM_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.
+                TX_CLKM_DIV_NUM: u8,
+                reserved26: u18,
+                ///  I2S Tx module clock enable signal.
+                TX_CLK_ACTIVE: u1,
+                ///  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
+                TX_CLK_SEL: u2,
+                ///  Set this bit to enable clk gate
+                CLK_EN: u1,
+                padding: u2,
+            }),
+            ///  I2S RX module clock divider configure register
+            RX_CLKM_DIV_CONF: mmio.Mmio(packed struct(u32) {
+                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).
+                RX_CLKM_DIV_Z: u9,
+                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).
+                RX_CLKM_DIV_Y: u9,
+                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
+                RX_CLKM_DIV_X: u9,
+                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.
+                RX_CLKM_DIV_YN1: u1,
+                padding: u4,
+            }),
+            ///  I2S TX module clock divider configure register
+            TX_CLKM_DIV_CONF: mmio.Mmio(packed struct(u32) {
+                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).
+                TX_CLKM_DIV_Z: u9,
+                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).
+                TX_CLKM_DIV_Y: u9,
+                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
+                TX_CLKM_DIV_X: u9,
+                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.
+                TX_CLKM_DIV_YN1: u1,
+                padding: u4,
+            }),
+            ///  I2S TX PCM2PDM configuration register
+            TX_PCM2PDM_CONF: mmio.Mmio(packed struct(u32) {
+                ///  I2S TX PDM bypass hp filter or not. The option has been removed.
+                TX_PDM_HP_BYPASS: u1,
+                ///  I2S TX PDM OSR2 value
+                TX_PDM_SINC_OSR2: u4,
+                ///  I2S TX PDM prescale for sigmadelta
+                TX_PDM_PRESCALE: u8,
+                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+                TX_PDM_HP_IN_SHIFT: u2,
+                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+                TX_PDM_LP_IN_SHIFT: u2,
+                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+                TX_PDM_SINC_IN_SHIFT: u2,
+                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
+                TX_PDM_SIGMADELTA_IN_SHIFT: u2,
+                ///  I2S TX PDM sigmadelta dither2 value
+                TX_PDM_SIGMADELTA_DITHER2: u1,
+                ///  I2S TX PDM sigmadelta dither value
+                TX_PDM_SIGMADELTA_DITHER: u1,
+                ///  I2S TX PDM dac mode enable
+                TX_PDM_DAC_2OUT_EN: u1,
+                ///  I2S TX PDM dac 2channel enable
+                TX_PDM_DAC_MODE_EN: u1,
+                ///  I2S TX PDM Converter enable
+                PCM2PDM_CONV_EN: u1,
+                padding: u6,
+            }),
+            ///  I2S TX PCM2PDM configuration register
+            TX_PCM2PDM_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  I2S TX PDM Fp
+                TX_PDM_FP: u10,
+                ///  I2S TX PDM Fs
+                TX_PDM_FS: u10,
+                ///  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])
+                TX_IIR_HP_MULT12_5: u3,
+                ///  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])
+                TX_IIR_HP_MULT12_0: u3,
+                padding: u6,
+            }),
+            reserved80: [8]u8,
+            ///  I2S TX TDM mode control register
+            RX_TDM_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN0_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN1_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN2_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN3_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN4_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN5_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN6_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel.
+                RX_TDM_PDM_CHAN7_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN8_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN9_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN10_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN11_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN12_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN13_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN14_EN: u1,
+                ///  1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel.
+                RX_TDM_CHAN15_EN: u1,
+                ///  The total channel number of I2S TX TDM mode.
+                RX_TDM_TOT_CHAN_NUM: u4,
+                padding: u12,
+            }),
+            ///  I2S TX TDM mode control register
+            TX_TDM_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN0_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN1_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN2_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN3_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN4_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN5_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN6_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN7_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN8_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN9_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN10_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN11_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN12_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN13_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN14_EN: u1,
+                ///  1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel.
+                TX_TDM_CHAN15_EN: u1,
+                ///  The total channel number of I2S TX TDM mode.
+                TX_TDM_TOT_CHAN_NUM: u4,
+                ///  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.
+                TX_TDM_SKIP_MSK_EN: u1,
+                padding: u11,
+            }),
+            ///  I2S RX timing control register
+            RX_TIMING: mmio.Mmio(packed struct(u32) {
+                ///  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                RX_SD_IN_DM: u2,
+                reserved16: u14,
+                ///  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                RX_WS_OUT_DM: u2,
+                reserved20: u2,
+                ///  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                RX_BCK_OUT_DM: u2,
+                reserved24: u2,
+                ///  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                RX_WS_IN_DM: u2,
+                reserved28: u2,
+                ///  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                RX_BCK_IN_DM: u2,
+                padding: u2,
+            }),
+            ///  I2S TX timing control register
+            TX_TIMING: mmio.Mmio(packed struct(u32) {
+                ///  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_SD_OUT_DM: u2,
+                reserved4: u2,
+                ///  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_SD1_OUT_DM: u2,
+                reserved16: u10,
+                ///  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_WS_OUT_DM: u2,
+                reserved20: u2,
+                ///  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_BCK_OUT_DM: u2,
+                reserved24: u2,
+                ///  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_WS_IN_DM: u2,
+                reserved28: u2,
+                ///  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
+                TX_BCK_IN_DM: u2,
+                padding: u2,
+            }),
+            ///  I2S HUNG configure register.
+            LC_HUNG_CONF: mmio.Mmio(packed struct(u32) {
+                ///  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value
+                LC_FIFO_TIMEOUT: u8,
+                ///  The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift
+                LC_FIFO_TIMEOUT_SHIFT: u3,
+                ///  The enable bit for FIFO timeout
+                LC_FIFO_TIMEOUT_ENA: u1,
+                padding: u20,
+            }),
+            ///  I2S RX data number control register.
+            RXEOF_NUM: mmio.Mmio(packed struct(u32) {
+                ///  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
+                RX_EOF_NUM: u12,
+                padding: u20,
+            }),
+            ///  I2S signal data register
+            CONF_SIGLE_DATA: mmio.Mmio(packed struct(u32) {
+                ///  The configured constant channel data to be sent out.
+                SINGLE_DATA: u32,
+            }),
+            ///  I2S TX status register
+            STATE: mmio.Mmio(packed struct(u32) {
+                ///  1: i2s_tx is idle state. 0: i2s_tx is working.
+                TX_IDLE: u1,
+                padding: u31,
+            }),
+            reserved128: [16]u8,
+            ///  Version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  I2S version control register
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  Interrupt Core
+        pub const INTERRUPT_CORE0 = extern struct {
+            ///  mac intr map register
+            MAC_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  core0_mac_intr_map
+                MAC_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac nmi_intr map register
+            MAC_NMI_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_mac_nmi_map
+                MAC_NMI_MAP: u5,
+                padding: u27,
+            }),
+            ///  pwr intr map register
+            PWR_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_pwr_intr_map
+                PWR_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  bb intr map register
+            BB_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_bb_int_map
+                BB_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  bt intr map register
+            BT_MAC_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_bt_mac_int_map
+                BT_MAC_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  bb_bt intr map register
+            BT_BB_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_bt_bb_int_map
+                BT_BB_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  bb_bt_nmi intr map register
+            BT_BB_NMI_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_bt_bb_nmi_map
+                BT_BB_NMI_MAP: u5,
+                padding: u27,
+            }),
+            ///  rwbt intr map register
+            RWBT_IRQ_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rwbt_irq_map
+                RWBT_IRQ_MAP: u5,
+                padding: u27,
+            }),
+            ///  rwble intr map register
+            RWBLE_IRQ_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rwble_irq_map
+                RWBLE_IRQ_MAP: u5,
+                padding: u27,
+            }),
+            ///  rwbt_nmi intr map register
+            RWBT_NMI_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rwbt_nmi_map
+                RWBT_NMI_MAP: u5,
+                padding: u27,
+            }),
+            ///  rwble_nmi intr map register
+            RWBLE_NMI_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rwble_nmi_map
+                RWBLE_NMI_MAP: u5,
+                padding: u27,
+            }),
+            ///  i2c intr map register
+            I2C_MST_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_i2c_mst_int_map
+                I2C_MST_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  slc0 intr map register
+            SLC0_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_slc0_intr_map
+                SLC0_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  slc1 intr map register
+            SLC1_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_slc1_intr_map
+                SLC1_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  apb_ctrl intr map register
+            APB_CTRL_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_apb_ctrl_intr_map
+                APB_CTRL_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  uchi0 intr map register
+            UHCI0_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_uhci0_intr_map
+                UHCI0_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  gpio intr map register
+            GPIO_INTERRUPT_PRO_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_gpio_interrupt_pro_map
+                GPIO_INTERRUPT_PRO_MAP: u5,
+                padding: u27,
+            }),
+            ///  gpio_pro intr map register
+            GPIO_INTERRUPT_PRO_NMI_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_gpio_interrupt_pro_nmi_map
+                GPIO_INTERRUPT_PRO_NMI_MAP: u5,
+                padding: u27,
+            }),
+            ///  gpio_pro_nmi intr map register
+            SPI_INTR_1_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_spi_intr_1_map
+                SPI_INTR_1_MAP: u5,
+                padding: u27,
+            }),
+            ///  spi1 intr map register
+            SPI_INTR_2_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_spi_intr_2_map
+                SPI_INTR_2_MAP: u5,
+                padding: u27,
+            }),
+            ///  spi2 intr map register
+            I2S1_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_i2s1_int_map
+                I2S1_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  i2s1 intr map register
+            UART_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_uart_intr_map
+                UART_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  uart1 intr map register
+            UART1_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_uart1_intr_map
+                UART1_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  ledc intr map register
+            LEDC_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_ledc_int_map
+                LEDC_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  efuse intr map register
+            EFUSE_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_efuse_int_map
+                EFUSE_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  can intr map register
+            CAN_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_can_int_map
+                CAN_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  usb intr map register
+            USB_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_usb_intr_map
+                USB_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  rtc intr map register
+            RTC_CORE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rtc_core_intr_map
+                RTC_CORE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  rmt intr map register
+            RMT_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rmt_intr_map
+                RMT_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  i2c intr map register
+            I2C_EXT0_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_i2c_ext0_intr_map
+                I2C_EXT0_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  timer1 intr map register
+            TIMER_INT1_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_timer_int1_map
+                TIMER_INT1_MAP: u5,
+                padding: u27,
+            }),
+            ///  timer2 intr map register
+            TIMER_INT2_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_timer_int2_map
+                TIMER_INT2_MAP: u5,
+                padding: u27,
+            }),
+            ///  tg to intr map register
+            TG_T0_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_tg_t0_int_map
+                TG_T0_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  tg wdt intr map register
+            TG_WDT_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_tg_wdt_int_map
+                TG_WDT_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  tg1 to intr map register
+            TG1_T0_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_tg1_t0_int_map
+                TG1_T0_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  tg1 wdt intr map register
+            TG1_WDT_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_tg1_wdt_int_map
+                TG1_WDT_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  cache ia intr map register
+            CACHE_IA_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cache_ia_int_map
+                CACHE_IA_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  systimer intr map register
+            SYSTIMER_TARGET0_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_systimer_target0_int_map
+                SYSTIMER_TARGET0_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  systimer target1 intr map register
+            SYSTIMER_TARGET1_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_systimer_target1_int_map
+                SYSTIMER_TARGET1_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  systimer target2 intr map register
+            SYSTIMER_TARGET2_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_systimer_target2_int_map
+                SYSTIMER_TARGET2_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  spi mem reject intr map register
+            SPI_MEM_REJECT_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_spi_mem_reject_intr_map
+                SPI_MEM_REJECT_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  icache perload intr map register
+            ICACHE_PRELOAD_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_icache_preload_int_map
+                ICACHE_PRELOAD_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  icache sync intr map register
+            ICACHE_SYNC_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_icache_sync_int_map
+                ICACHE_SYNC_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  adc intr map register
+            APB_ADC_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_apb_adc_int_map
+                APB_ADC_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  dma ch0 intr map register
+            DMA_CH0_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_dma_ch0_int_map
+                DMA_CH0_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  dma ch1 intr map register
+            DMA_CH1_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_dma_ch1_int_map
+                DMA_CH1_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  dma ch2 intr map register
+            DMA_CH2_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_dma_ch2_int_map
+                DMA_CH2_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  rsa intr map register
+            RSA_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_rsa_int_map
+                RSA_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  aes intr map register
+            AES_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_aes_int_map
+                AES_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  sha intr map register
+            SHA_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_sha_int_map
+                SHA_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  cpu from cpu 0 intr map register
+            CPU_INTR_FROM_CPU_0_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_intr_from_cpu_0_map
+                CPU_INTR_FROM_CPU_0_MAP: u5,
+                padding: u27,
+            }),
+            ///  cpu from cpu 0 intr map register
+            CPU_INTR_FROM_CPU_1_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_intr_from_cpu_1_map
+                CPU_INTR_FROM_CPU_1_MAP: u5,
+                padding: u27,
+            }),
+            ///  cpu from cpu 1 intr map register
+            CPU_INTR_FROM_CPU_2_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_intr_from_cpu_2_map
+                CPU_INTR_FROM_CPU_2_MAP: u5,
+                padding: u27,
+            }),
+            ///  cpu from cpu 3 intr map register
+            CPU_INTR_FROM_CPU_3_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_intr_from_cpu_3_map
+                CPU_INTR_FROM_CPU_3_MAP: u5,
+                padding: u27,
+            }),
+            ///  assist debug intr map register
+            ASSIST_DEBUG_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_assist_debug_intr_map
+                ASSIST_DEBUG_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  dma pms violatile intr map register
+            DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_dma_apbperi_pms_monitor_violate_intr_map
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  iram0 pms violatile intr map register
+            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_core_0_iram0_pms_monitor_violate_intr_map
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_core_0_dram0_pms_monitor_violate_intr_map
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_core_0_pif_pms_monitor_violate_intr_map
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_core_0_pif_pms_monitor_violate_size_intr_map
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            BACKUP_PMS_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_backup_pms_violate_intr_map
+                BACKUP_PMS_VIOLATE_INTR_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            CACHE_CORE0_ACS_INT_MAP: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cache_core0_acs_int_map
+                CACHE_CORE0_ACS_INT_MAP: u5,
+                padding: u27,
+            }),
+            ///  mac intr map register
+            INTR_STATUS_REG_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_intr_status_0
+                INTR_STATUS_0: u32,
+            }),
+            ///  mac intr map register
+            INTR_STATUS_REG_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_intr_status_1
+                INTR_STATUS_1: u32,
+            }),
+            ///  mac intr map register
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_reg_clk_en
+                REG_CLK_EN: u1,
+                padding: u31,
+            }),
+            ///  mac intr map register
+            CPU_INT_ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_int_enable
+                CPU_INT_ENABLE: u32,
+            }),
+            ///  mac intr map register
+            CPU_INT_TYPE: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_int_type
+                CPU_INT_TYPE: u32,
+            }),
+            ///  mac intr map register
+            CPU_INT_CLEAR: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_int_clear
+                CPU_INT_CLEAR: u32,
+            }),
+            ///  mac intr map register
+            CPU_INT_EIP_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_int_eip_status
+                CPU_INT_EIP_STATUS: u32,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_0_map
+                CPU_PRI_0_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_1_map
+                CPU_PRI_1_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_2: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_2_map
+                CPU_PRI_2_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_3: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_3_map
+                CPU_PRI_3_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_4: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_4_map
+                CPU_PRI_4_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_5: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_5_map
+                CPU_PRI_5_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_6: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_6_map
+                CPU_PRI_6_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_7: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_7_map
+                CPU_PRI_7_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_8: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_8_map
+                CPU_PRI_8_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_9: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_9_map
+                CPU_PRI_9_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_10: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_10_map
+                CPU_PRI_10_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_11: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_11_map
+                CPU_PRI_11_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_12: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_12_map
+                CPU_PRI_12_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_13: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_13_map
+                CPU_PRI_13_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_14: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_14_map
+                CPU_PRI_14_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_15: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_15_map
+                CPU_PRI_15_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_16: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_16_map
+                CPU_PRI_16_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_17: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_17_map
+                CPU_PRI_17_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_18: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_18_map
+                CPU_PRI_18_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_19: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_19_map
+                CPU_PRI_19_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_20: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_20_map
+                CPU_PRI_20_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_21: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_21_map
+                CPU_PRI_21_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_22: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_22_map
+                CPU_PRI_22_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_23: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_23_map
+                CPU_PRI_23_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_24: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_24_map
+                CPU_PRI_24_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_25: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_25_map
+                CPU_PRI_25_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_26: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_26_map
+                CPU_PRI_26_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_27: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_27_map
+                CPU_PRI_27_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_28: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_28_map
+                CPU_PRI_28_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_29: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_29_map
+                CPU_PRI_29_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_30: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_30_map
+                CPU_PRI_30_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_PRI_31: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_pri_31_map
+                CPU_PRI_31_MAP: u4,
+                padding: u28,
+            }),
+            ///  mac intr map register
+            CPU_INT_THRESH: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_cpu_int_thresh
+                CPU_INT_THRESH: u4,
+                padding: u28,
+            }),
+            reserved2044: [1636]u8,
+            ///  mac intr map register
+            INTERRUPT_REG_DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_core0_interrupt_reg_date
+                INTERRUPT_REG_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  Input/Output Multiplexer
+        pub const IO_MUX = extern struct {
+            ///  Clock Output Configuration Register
+            PIN_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.
+                CLK_OUT1: u4,
+                ///  If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.
+                CLK_OUT2: u4,
+                ///  If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.
+                CLK_OUT3: u4,
+                padding: u20,
+            }),
+            ///  IO MUX Configure Register for pad XTAL_32K_P
+            GPIO: [22]mmio.Mmio(packed struct(u32) {
+                ///  Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
+                MCU_OE: u1,
+                ///  Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
+                SLP_SEL: u1,
+                ///  Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.
+                MCU_WPD: u1,
+                ///  Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.
+                MCU_WPU: u1,
+                ///  Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
+                MCU_IE: u1,
+                reserved7: u2,
+                ///  Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.
+                FUN_WPD: u1,
+                ///  Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.
+                FUN_WPU: u1,
+                ///  Input enable of the pad. 1: input enabled; 0: input disabled.
+                FUN_IE: u1,
+                ///  Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
+                FUN_DRV: u2,
+                ///  Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.
+                MCU_SEL: u3,
+                ///  Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
+                FILTER_EN: u1,
+                padding: u16,
+            }),
+            reserved252: [160]u8,
+            ///  IO MUX Version Control Register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  Version control register
+                REG_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  LED Control PWM (Pulse Width Modulation)
+        pub const LEDC = extern struct {
+            ///  LEDC_LSCH0_CONF0.
+            LSCH0_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch0.
+                TIMER_SEL_LSCH0: u2,
+                ///  reg_sig_out_en_lsch0.
+                SIG_OUT_EN_LSCH0: u1,
+                ///  reg_idle_lv_lsch0.
+                IDLE_LV_LSCH0: u1,
+                ///  reg_para_up_lsch0.
+                PARA_UP_LSCH0: u1,
+                ///  reg_ovf_num_lsch0.
+                OVF_NUM_LSCH0: u10,
+                ///  reg_ovf_cnt_en_lsch0.
+                OVF_CNT_EN_LSCH0: u1,
+                ///  reg_ovf_cnt_reset_lsch0.
+                OVF_CNT_RESET_LSCH0: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH0_HPOINT.
+            LSCH0_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch0.
+                HPOINT_LSCH0: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH0_DUTY.
+            LSCH0_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch0.
+                DUTY_LSCH0: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH0_CONF1.
+            LSCH0_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch0.
+                DUTY_SCALE_LSCH0: u10,
+                ///  reg_duty_cycle_lsch0.
+                DUTY_CYCLE_LSCH0: u10,
+                ///  reg_duty_num_lsch0.
+                DUTY_NUM_LSCH0: u10,
+                ///  reg_duty_inc_lsch0.
+                DUTY_INC_LSCH0: u1,
+                ///  reg_duty_start_lsch0.
+                DUTY_START_LSCH0: u1,
+            }),
+            ///  LEDC_LSCH0_DUTY_R.
+            LSCH0_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch0_r.
+                DUTY_LSCH0_R: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH1_CONF0.
+            LSCH1_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch1.
+                TIMER_SEL_LSCH1: u2,
+                ///  reg_sig_out_en_lsch1.
+                SIG_OUT_EN_LSCH1: u1,
+                ///  reg_idle_lv_lsch1.
+                IDLE_LV_LSCH1: u1,
+                ///  reg_para_up_lsch1.
+                PARA_UP_LSCH1: u1,
+                ///  reg_ovf_num_lsch1.
+                OVF_NUM_LSCH1: u10,
+                ///  reg_ovf_cnt_en_lsch1.
+                OVF_CNT_EN_LSCH1: u1,
+                ///  reg_ovf_cnt_reset_lsch1.
+                OVF_CNT_RESET_LSCH1: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH1_HPOINT.
+            LSCH1_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch1.
+                HPOINT_LSCH1: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH1_DUTY.
+            LSCH1_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch1.
+                DUTY_LSCH1: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH1_CONF1.
+            LSCH1_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch1.
+                DUTY_SCALE_LSCH1: u10,
+                ///  reg_duty_cycle_lsch1.
+                DUTY_CYCLE_LSCH1: u10,
+                ///  reg_duty_num_lsch1.
+                DUTY_NUM_LSCH1: u10,
+                ///  reg_duty_inc_lsch1.
+                DUTY_INC_LSCH1: u1,
+                ///  reg_duty_start_lsch1.
+                DUTY_START_LSCH1: u1,
+            }),
+            ///  LEDC_LSCH1_DUTY_R.
+            LSCH1_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch1_r.
+                DUTY_LSCH1_R: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH2_CONF0.
+            LSCH2_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch2.
+                TIMER_SEL_LSCH2: u2,
+                ///  reg_sig_out_en_lsch2.
+                SIG_OUT_EN_LSCH2: u1,
+                ///  reg_idle_lv_lsch2.
+                IDLE_LV_LSCH2: u1,
+                ///  reg_para_up_lsch2.
+                PARA_UP_LSCH2: u1,
+                ///  reg_ovf_num_lsch2.
+                OVF_NUM_LSCH2: u10,
+                ///  reg_ovf_cnt_en_lsch2.
+                OVF_CNT_EN_LSCH2: u1,
+                ///  reg_ovf_cnt_reset_lsch2.
+                OVF_CNT_RESET_LSCH2: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH2_HPOINT.
+            LSCH2_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch2.
+                HPOINT_LSCH2: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH2_DUTY.
+            LSCH2_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch2.
+                DUTY_LSCH2: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH2_CONF1.
+            LSCH2_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch2.
+                DUTY_SCALE_LSCH2: u10,
+                ///  reg_duty_cycle_lsch2.
+                DUTY_CYCLE_LSCH2: u10,
+                ///  reg_duty_num_lsch2.
+                DUTY_NUM_LSCH2: u10,
+                ///  reg_duty_inc_lsch2.
+                DUTY_INC_LSCH2: u1,
+                ///  reg_duty_start_lsch2.
+                DUTY_START_LSCH2: u1,
+            }),
+            ///  LEDC_LSCH2_DUTY_R.
+            LSCH2_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch2_r.
+                DUTY_LSCH2_R: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH3_CONF0.
+            LSCH3_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch3.
+                TIMER_SEL_LSCH3: u2,
+                ///  reg_sig_out_en_lsch3.
+                SIG_OUT_EN_LSCH3: u1,
+                ///  reg_idle_lv_lsch3.
+                IDLE_LV_LSCH3: u1,
+                ///  reg_para_up_lsch3.
+                PARA_UP_LSCH3: u1,
+                ///  reg_ovf_num_lsch3.
+                OVF_NUM_LSCH3: u10,
+                ///  reg_ovf_cnt_en_lsch3.
+                OVF_CNT_EN_LSCH3: u1,
+                ///  reg_ovf_cnt_reset_lsch3.
+                OVF_CNT_RESET_LSCH3: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH3_HPOINT.
+            LSCH3_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch3.
+                HPOINT_LSCH3: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH3_DUTY.
+            LSCH3_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch3.
+                DUTY_LSCH3: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH3_CONF1.
+            LSCH3_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch3.
+                DUTY_SCALE_LSCH3: u10,
+                ///  reg_duty_cycle_lsch3.
+                DUTY_CYCLE_LSCH3: u10,
+                ///  reg_duty_num_lsch3.
+                DUTY_NUM_LSCH3: u10,
+                ///  reg_duty_inc_lsch3.
+                DUTY_INC_LSCH3: u1,
+                ///  reg_duty_start_lsch3.
+                DUTY_START_LSCH3: u1,
+            }),
+            ///  LEDC_LSCH3_DUTY_R.
+            LSCH3_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch3_r.
+                DUTY_LSCH3_R: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH4_CONF0.
+            LSCH4_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch4.
+                TIMER_SEL_LSCH4: u2,
+                ///  reg_sig_out_en_lsch4.
+                SIG_OUT_EN_LSCH4: u1,
+                ///  reg_idle_lv_lsch4.
+                IDLE_LV_LSCH4: u1,
+                ///  reg_para_up_lsch4.
+                PARA_UP_LSCH4: u1,
+                ///  reg_ovf_num_lsch4.
+                OVF_NUM_LSCH4: u10,
+                ///  reg_ovf_cnt_en_lsch4.
+                OVF_CNT_EN_LSCH4: u1,
+                ///  reg_ovf_cnt_reset_lsch4.
+                OVF_CNT_RESET_LSCH4: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH4_HPOINT.
+            LSCH4_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch4.
+                HPOINT_LSCH4: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH4_DUTY.
+            LSCH4_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch4.
+                DUTY_LSCH4: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH4_CONF1.
+            LSCH4_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch4.
+                DUTY_SCALE_LSCH4: u10,
+                ///  reg_duty_cycle_lsch4.
+                DUTY_CYCLE_LSCH4: u10,
+                ///  reg_duty_num_lsch4.
+                DUTY_NUM_LSCH4: u10,
+                ///  reg_duty_inc_lsch4.
+                DUTY_INC_LSCH4: u1,
+                ///  reg_duty_start_lsch4.
+                DUTY_START_LSCH4: u1,
+            }),
+            ///  LEDC_LSCH4_DUTY_R.
+            LSCH4_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch4_r.
+                DUTY_LSCH4_R: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH5_CONF0.
+            LSCH5_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timer_sel_lsch5.
+                TIMER_SEL_LSCH5: u2,
+                ///  reg_sig_out_en_lsch5.
+                SIG_OUT_EN_LSCH5: u1,
+                ///  reg_idle_lv_lsch5.
+                IDLE_LV_LSCH5: u1,
+                ///  reg_para_up_lsch5.
+                PARA_UP_LSCH5: u1,
+                ///  reg_ovf_num_lsch5.
+                OVF_NUM_LSCH5: u10,
+                ///  reg_ovf_cnt_en_lsch5.
+                OVF_CNT_EN_LSCH5: u1,
+                ///  reg_ovf_cnt_reset_lsch5.
+                OVF_CNT_RESET_LSCH5: u1,
+                padding: u15,
+            }),
+            ///  LEDC_LSCH5_HPOINT.
+            LSCH5_HPOINT: mmio.Mmio(packed struct(u32) {
+                ///  reg_hpoint_lsch5.
+                HPOINT_LSCH5: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSCH5_DUTY.
+            LSCH5_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch5.
+                DUTY_LSCH5: u19,
+                padding: u13,
+            }),
+            ///  LEDC_LSCH5_CONF1.
+            LSCH5_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_scale_lsch5.
+                DUTY_SCALE_LSCH5: u10,
+                ///  reg_duty_cycle_lsch5.
+                DUTY_CYCLE_LSCH5: u10,
+                ///  reg_duty_num_lsch5.
+                DUTY_NUM_LSCH5: u10,
+                ///  reg_duty_inc_lsch5.
+                DUTY_INC_LSCH5: u1,
+                ///  reg_duty_start_lsch5.
+                DUTY_START_LSCH5: u1,
+            }),
+            ///  LEDC_LSCH5_DUTY_R.
+            LSCH5_DUTY_R: mmio.Mmio(packed struct(u32) {
+                ///  reg_duty_lsch5_r.
+                DUTY_LSCH5_R: u19,
+                padding: u13,
+            }),
+            reserved160: [40]u8,
+            ///  LEDC_LSTIMER0_CONF.
+            LSTIMER0_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_duty_res.
+                LSTIMER0_DUTY_RES: u4,
+                ///  reg_clk_div_lstimer0.
+                CLK_DIV_LSTIMER0: u18,
+                ///  reg_lstimer0_pause.
+                LSTIMER0_PAUSE: u1,
+                ///  reg_lstimer0_rst.
+                LSTIMER0_RST: u1,
+                ///  reg_tick_sel_lstimer0.
+                TICK_SEL_LSTIMER0: u1,
+                ///  reg_lstimer0_para_up.
+                LSTIMER0_PARA_UP: u1,
+                padding: u6,
+            }),
+            ///  LEDC_LSTIMER0_VALUE.
+            LSTIMER0_VALUE: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_cnt.
+                LSTIMER0_CNT: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSTIMER1_CONF.
+            LSTIMER1_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer1_duty_res.
+                LSTIMER1_DUTY_RES: u4,
+                ///  reg_clk_div_lstimer1.
+                CLK_DIV_LSTIMER1: u18,
+                ///  reg_lstimer1_pause.
+                LSTIMER1_PAUSE: u1,
+                ///  reg_lstimer1_rst.
+                LSTIMER1_RST: u1,
+                ///  reg_tick_sel_lstimer1.
+                TICK_SEL_LSTIMER1: u1,
+                ///  reg_lstimer1_para_up.
+                LSTIMER1_PARA_UP: u1,
+                padding: u6,
+            }),
+            ///  LEDC_LSTIMER1_VALUE.
+            LSTIMER1_VALUE: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer1_cnt.
+                LSTIMER1_CNT: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSTIMER2_CONF.
+            LSTIMER2_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer2_duty_res.
+                LSTIMER2_DUTY_RES: u4,
+                ///  reg_clk_div_lstimer2.
+                CLK_DIV_LSTIMER2: u18,
+                ///  reg_lstimer2_pause.
+                LSTIMER2_PAUSE: u1,
+                ///  reg_lstimer2_rst.
+                LSTIMER2_RST: u1,
+                ///  reg_tick_sel_lstimer2.
+                TICK_SEL_LSTIMER2: u1,
+                ///  reg_lstimer2_para_up.
+                LSTIMER2_PARA_UP: u1,
+                padding: u6,
+            }),
+            ///  LEDC_LSTIMER2_VALUE.
+            LSTIMER2_VALUE: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer2_cnt.
+                LSTIMER2_CNT: u14,
+                padding: u18,
+            }),
+            ///  LEDC_LSTIMER3_CONF.
+            LSTIMER3_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer3_duty_res.
+                LSTIMER3_DUTY_RES: u4,
+                ///  reg_clk_div_lstimer3.
+                CLK_DIV_LSTIMER3: u18,
+                ///  reg_lstimer3_pause.
+                LSTIMER3_PAUSE: u1,
+                ///  reg_lstimer3_rst.
+                LSTIMER3_RST: u1,
+                ///  reg_tick_sel_lstimer3.
+                TICK_SEL_LSTIMER3: u1,
+                ///  reg_lstimer3_para_up.
+                LSTIMER3_PARA_UP: u1,
+                padding: u6,
+            }),
+            ///  LEDC_LSTIMER3_VALUE.
+            LSTIMER3_VALUE: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer3_cnt.
+                LSTIMER3_CNT: u14,
+                padding: u18,
+            }),
+            ///  LEDC_INT_RAW.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_ovf_int_raw.
+                LSTIMER0_OVF_INT_RAW: u1,
+                ///  reg_lstimer1_ovf_int_raw.
+                LSTIMER1_OVF_INT_RAW: u1,
+                ///  reg_lstimer2_ovf_int_raw.
+                LSTIMER2_OVF_INT_RAW: u1,
+                ///  reg_lstimer3_ovf_int_raw.
+                LSTIMER3_OVF_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch0_int_raw.
+                DUTY_CHNG_END_LSCH0_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch1_int_raw.
+                DUTY_CHNG_END_LSCH1_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch2_int_raw.
+                DUTY_CHNG_END_LSCH2_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch3_int_raw.
+                DUTY_CHNG_END_LSCH3_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch4_int_raw.
+                DUTY_CHNG_END_LSCH4_INT_RAW: u1,
+                ///  reg_duty_chng_end_lsch5_int_raw.
+                DUTY_CHNG_END_LSCH5_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch0_int_raw.
+                OVF_CNT_LSCH0_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch1_int_raw.
+                OVF_CNT_LSCH1_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch2_int_raw.
+                OVF_CNT_LSCH2_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch3_int_raw.
+                OVF_CNT_LSCH3_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch4_int_raw.
+                OVF_CNT_LSCH4_INT_RAW: u1,
+                ///  reg_ovf_cnt_lsch5_int_raw.
+                OVF_CNT_LSCH5_INT_RAW: u1,
+                padding: u16,
+            }),
+            ///  LEDC_INT_ST.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_ovf_int_st.
+                LSTIMER0_OVF_INT_ST: u1,
+                ///  reg_lstimer1_ovf_int_st.
+                LSTIMER1_OVF_INT_ST: u1,
+                ///  reg_lstimer2_ovf_int_st.
+                LSTIMER2_OVF_INT_ST: u1,
+                ///  reg_lstimer3_ovf_int_st.
+                LSTIMER3_OVF_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch0_int_st.
+                DUTY_CHNG_END_LSCH0_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch1_int_st.
+                DUTY_CHNG_END_LSCH1_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch2_int_st.
+                DUTY_CHNG_END_LSCH2_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch3_int_st.
+                DUTY_CHNG_END_LSCH3_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch4_int_st.
+                DUTY_CHNG_END_LSCH4_INT_ST: u1,
+                ///  reg_duty_chng_end_lsch5_int_st.
+                DUTY_CHNG_END_LSCH5_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch0_int_st.
+                OVF_CNT_LSCH0_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch1_int_st.
+                OVF_CNT_LSCH1_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch2_int_st.
+                OVF_CNT_LSCH2_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch3_int_st.
+                OVF_CNT_LSCH3_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch4_int_st.
+                OVF_CNT_LSCH4_INT_ST: u1,
+                ///  reg_ovf_cnt_lsch5_int_st.
+                OVF_CNT_LSCH5_INT_ST: u1,
+                padding: u16,
+            }),
+            ///  LEDC_INT_ENA.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_ovf_int_ena.
+                LSTIMER0_OVF_INT_ENA: u1,
+                ///  reg_lstimer1_ovf_int_ena.
+                LSTIMER1_OVF_INT_ENA: u1,
+                ///  reg_lstimer2_ovf_int_ena.
+                LSTIMER2_OVF_INT_ENA: u1,
+                ///  reg_lstimer3_ovf_int_ena.
+                LSTIMER3_OVF_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch0_int_ena.
+                DUTY_CHNG_END_LSCH0_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch1_int_ena.
+                DUTY_CHNG_END_LSCH1_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch2_int_ena.
+                DUTY_CHNG_END_LSCH2_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch3_int_ena.
+                DUTY_CHNG_END_LSCH3_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch4_int_ena.
+                DUTY_CHNG_END_LSCH4_INT_ENA: u1,
+                ///  reg_duty_chng_end_lsch5_int_ena.
+                DUTY_CHNG_END_LSCH5_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch0_int_ena.
+                OVF_CNT_LSCH0_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch1_int_ena.
+                OVF_CNT_LSCH1_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch2_int_ena.
+                OVF_CNT_LSCH2_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch3_int_ena.
+                OVF_CNT_LSCH3_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch4_int_ena.
+                OVF_CNT_LSCH4_INT_ENA: u1,
+                ///  reg_ovf_cnt_lsch5_int_ena.
+                OVF_CNT_LSCH5_INT_ENA: u1,
+                padding: u16,
+            }),
+            ///  LEDC_INT_CLR.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  reg_lstimer0_ovf_int_clr.
+                LSTIMER0_OVF_INT_CLR: u1,
+                ///  reg_lstimer1_ovf_int_clr.
+                LSTIMER1_OVF_INT_CLR: u1,
+                ///  reg_lstimer2_ovf_int_clr.
+                LSTIMER2_OVF_INT_CLR: u1,
+                ///  reg_lstimer3_ovf_int_clr.
+                LSTIMER3_OVF_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch0_int_clr.
+                DUTY_CHNG_END_LSCH0_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch1_int_clr.
+                DUTY_CHNG_END_LSCH1_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch2_int_clr.
+                DUTY_CHNG_END_LSCH2_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch3_int_clr.
+                DUTY_CHNG_END_LSCH3_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch4_int_clr.
+                DUTY_CHNG_END_LSCH4_INT_CLR: u1,
+                ///  reg_duty_chng_end_lsch5_int_clr.
+                DUTY_CHNG_END_LSCH5_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch0_int_clr.
+                OVF_CNT_LSCH0_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch1_int_clr.
+                OVF_CNT_LSCH1_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch2_int_clr.
+                OVF_CNT_LSCH2_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch3_int_clr.
+                OVF_CNT_LSCH3_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch4_int_clr.
+                OVF_CNT_LSCH4_INT_CLR: u1,
+                ///  reg_ovf_cnt_lsch5_int_clr.
+                OVF_CNT_LSCH5_INT_CLR: u1,
+                padding: u16,
+            }),
+            ///  LEDC_CONF.
+            CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_apb_clk_sel.
+                APB_CLK_SEL: u2,
+                reserved31: u29,
+                ///  reg_clk_en.
+                CLK_EN: u1,
+            }),
+            reserved252: [40]u8,
+            ///  LEDC_DATE.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_ledc_date.
+                LEDC_DATE: u32,
+            }),
+        };
+
+        ///  Remote Control Peripheral
+        pub const RMT = extern struct {
+            ///  RMT_CH0DATA_REG.
+            CH0DATA: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                DATA: u32,
+            }),
+            ///  RMT_CH1DATA_REG.
+            CH1DATA: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                DATA: u32,
+            }),
+            ///  RMT_CH2DATA_REG.
+            CH2DATA: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                DATA: u32,
+            }),
+            ///  RMT_CH3DATA_REG.
+            CH3DATA: mmio.Mmio(packed struct(u32) {
+                ///  Reserved.
+                DATA: u32,
+            }),
+            reserved28: [12]u8,
+            ///  RMT_CH2CONF1_REG.
+            CH2CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_rx_en_ch2.
+                RX_EN: u1,
+                ///  reg_mem_wr_rst_ch2.
+                MEM_WR_RST: u1,
+                ///  reg_apb_mem_rst_ch2.
+                APB_MEM_RST: u1,
+                ///  reg_mem_owner_ch2.
+                MEM_OWNER: u1,
+                ///  reg_rx_filter_en_ch2.
+                RX_FILTER_EN: u1,
+                ///  reg_rx_filter_thres_ch2.
+                RX_FILTER_THRES: u8,
+                ///  reg_mem_rx_wrap_en_ch2.
+                MEM_RX_WRAP_EN: u1,
+                ///  reg_afifo_rst_ch2.
+                AFIFO_RST: u1,
+                ///  reg_conf_update_ch2.
+                CONF_UPDATE: u1,
+                padding: u16,
+            }),
+            reserved36: [4]u8,
+            ///  RMT_CH3CONF1_REG.
+            CH3CONF1: mmio.Mmio(packed struct(u32) {
+                ///  reg_rx_en_ch3.
+                RX_EN: u1,
+                ///  reg_mem_wr_rst_ch3.
+                MEM_WR_RST: u1,
+                ///  reg_apb_mem_rst_ch3.
+                APB_MEM_RST: u1,
+                ///  reg_mem_owner_ch3.
+                MEM_OWNER: u1,
+                ///  reg_rx_filter_en_ch3.
+                RX_FILTER_EN: u1,
+                ///  reg_rx_filter_thres_ch3.
+                RX_FILTER_THRES: u8,
+                ///  reg_mem_rx_wrap_en_ch3.
+                MEM_RX_WRAP_EN: u1,
+                ///  reg_afifo_rst_ch3.
+                AFIFO_RST: u1,
+                ///  reg_conf_update_ch3.
+                CONF_UPDATE: u1,
+                padding: u16,
+            }),
+            ///  RMT_CH0STATUS_REG.
+            CH0STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_mem_raddr_ex_ch0.
+                MEM_RADDR_EX: u9,
+                ///  reg_state_ch0.
+                STATE: u3,
+                ///  reg_apb_mem_waddr_ch0.
+                APB_MEM_WADDR: u9,
+                ///  reg_apb_mem_rd_err_ch0.
+                APB_MEM_RD_ERR: u1,
+                ///  reg_mem_empty_ch0.
+                MEM_EMPTY: u1,
+                ///  reg_apb_mem_wr_err_ch0.
+                APB_MEM_WR_ERR: u1,
+                ///  reg_apb_mem_raddr_ch0.
+                APB_MEM_RADDR: u8,
+            }),
+            ///  RMT_CH1STATUS_REG.
+            CH1STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_mem_raddr_ex_ch1.
+                MEM_RADDR_EX: u9,
+                ///  reg_state_ch1.
+                STATE: u3,
+                ///  reg_apb_mem_waddr_ch1.
+                APB_MEM_WADDR: u9,
+                ///  reg_apb_mem_rd_err_ch1.
+                APB_MEM_RD_ERR: u1,
+                ///  reg_mem_empty_ch1.
+                MEM_EMPTY: u1,
+                ///  reg_apb_mem_wr_err_ch1.
+                APB_MEM_WR_ERR: u1,
+                ///  reg_apb_mem_raddr_ch1.
+                APB_MEM_RADDR: u8,
+            }),
+            ///  RMT_CH2STATUS_REG.
+            CH2STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_mem_waddr_ex_ch2.
+                MEM_WADDR_EX: u9,
+                reserved12: u3,
+                ///  reg_apb_mem_raddr_ch2.
+                APB_MEM_RADDR: u9,
+                reserved22: u1,
+                ///  reg_state_ch2.
+                STATE: u3,
+                ///  reg_mem_owner_err_ch2.
+                MEM_OWNER_ERR: u1,
+                ///  reg_mem_full_ch2.
+                MEM_FULL: u1,
+                ///  reg_apb_mem_rd_err_ch2.
+                APB_MEM_RD_ERR: u1,
+                padding: u4,
+            }),
+            ///  RMT_CH3STATUS_REG.
+            CH3STATUS: mmio.Mmio(packed struct(u32) {
+                ///  reg_mem_waddr_ex_ch3.
+                MEM_WADDR_EX: u9,
+                reserved12: u3,
+                ///  reg_apb_mem_raddr_ch3.
+                APB_MEM_RADDR: u9,
+                reserved22: u1,
+                ///  reg_state_ch3.
+                STATE: u3,
+                ///  reg_mem_owner_err_ch3.
+                MEM_OWNER_ERR: u1,
+                ///  reg_mem_full_ch3.
+                MEM_FULL: u1,
+                ///  reg_apb_mem_rd_err_ch3.
+                APB_MEM_RD_ERR: u1,
+                padding: u4,
+            }),
+            ///  RMT_INT_RAW_REG.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                reserved10: u10,
+                ///  reg_ch2_rx_thr_event_int_raw.
+                CH2_RX_THR_EVENT_INT_RAW: u1,
+                ///  reg_ch3_rx_thr_event_int_raw.
+                CH3_RX_THR_EVENT_INT_RAW: u1,
+                padding: u20,
+            }),
+            ///  RMT_INT_ST_REG.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                reserved10: u10,
+                ///  reg_ch2_rx_thr_event_int_st.
+                CH2_RX_THR_EVENT_INT_ST: u1,
+                ///  reg_ch3_rx_thr_event_int_st.
+                CH3_RX_THR_EVENT_INT_ST: u1,
+                padding: u20,
+            }),
+            ///  RMT_INT_ENA_REG.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                reserved10: u10,
+                ///  reg_ch2_rx_thr_event_int_ena.
+                CH2_RX_THR_EVENT_INT_ENA: u1,
+                ///  reg_ch3_rx_thr_event_int_ena.
+                CH3_RX_THR_EVENT_INT_ENA: u1,
+                padding: u20,
+            }),
+            ///  RMT_INT_CLR_REG.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                reserved10: u10,
+                ///  reg_ch2_rx_thr_event_int_clr.
+                CH2_RX_THR_EVENT_INT_CLR: u1,
+                ///  reg_ch3_rx_thr_event_int_clr.
+                CH3_RX_THR_EVENT_INT_CLR: u1,
+                padding: u20,
+            }),
+            ///  RMT_CH0CARRIER_DUTY_REG.
+            CH0CARRIER_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_carrier_low_ch0.
+                CARRIER_LOW: u16,
+                ///  reg_carrier_high_ch0.
+                CARRIER_HIGH: u16,
+            }),
+            ///  RMT_CH1CARRIER_DUTY_REG.
+            CH1CARRIER_DUTY: mmio.Mmio(packed struct(u32) {
+                ///  reg_carrier_low_ch1.
+                CARRIER_LOW: u16,
+                ///  reg_carrier_high_ch1.
+                CARRIER_HIGH: u16,
+            }),
+            ///  RMT_CH2_RX_CARRIER_RM_REG.
+            CH2_RX_CARRIER_RM: mmio.Mmio(packed struct(u32) {
+                ///  reg_carrier_low_thres_ch2.
+                CARRIER_LOW_THRES: u16,
+                ///  reg_carrier_high_thres_ch2.
+                CARRIER_HIGH_THRES: u16,
+            }),
+            ///  RMT_CH3_RX_CARRIER_RM_REG.
+            CH3_RX_CARRIER_RM: mmio.Mmio(packed struct(u32) {
+                ///  reg_carrier_low_thres_ch3.
+                CARRIER_LOW_THRES: u16,
+                ///  reg_carrier_high_thres_ch3.
+                CARRIER_HIGH_THRES: u16,
+            }),
+            reserved104: [16]u8,
+            ///  RMT_SYS_CONF_REG.
+            SYS_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_apb_fifo_mask.
+                APB_FIFO_MASK: u1,
+                ///  reg_mem_clk_force_on.
+                MEM_CLK_FORCE_ON: u1,
+                ///  reg_rmt_mem_force_pd.
+                MEM_FORCE_PD: u1,
+                ///  reg_rmt_mem_force_pu.
+                MEM_FORCE_PU: u1,
+                ///  reg_rmt_sclk_div_num.
+                SCLK_DIV_NUM: u8,
+                ///  reg_rmt_sclk_div_a.
+                SCLK_DIV_A: u6,
+                ///  reg_rmt_sclk_div_b.
+                SCLK_DIV_B: u6,
+                ///  reg_rmt_sclk_sel.
+                SCLK_SEL: u2,
+                ///  reg_rmt_sclk_active.
+                SCLK_ACTIVE: u1,
+                reserved31: u4,
+                ///  reg_clk_en.
+                CLK_EN: u1,
+            }),
+            ///  RMT_TX_SIM_REG.
+            TX_SIM: mmio.Mmio(packed struct(u32) {
+                ///  reg_rmt_tx_sim_ch0.
+                TX_SIM_CH0: u1,
+                ///  reg_rmt_tx_sim_ch1.
+                TX_SIM_CH1: u1,
+                ///  reg_rmt_tx_sim_en.
+                TX_SIM_EN: u1,
+                padding: u29,
+            }),
+            ///  RMT_REF_CNT_RST_REG.
+            REF_CNT_RST: mmio.Mmio(packed struct(u32) {
+                ///  reg_ref_cnt_rst_ch0.
+                CH0: u1,
+                ///  reg_ref_cnt_rst_ch1.
+                CH1: u1,
+                ///  reg_ref_cnt_rst_ch2.
+                CH2: u1,
+                ///  reg_ref_cnt_rst_ch3.
+                CH3: u1,
+                padding: u28,
+            }),
+            reserved204: [88]u8,
+            ///  RMT_DATE_REG.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_rmt_date.
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  Hardware random number generator
+        pub const RNG = extern struct {
+            reserved176: [176]u8,
+            ///  Random number data
+            DATA: u32,
+        };
+
+        ///  RSA (Rivest Shamir Adleman) Accelerator
+        pub const RSA = extern struct {
+            ///  The memory that stores M
+            M_MEM: [16]u8,
+            reserved512: [496]u8,
+            ///  The memory that stores Z
+            Z_MEM: [16]u8,
+            reserved1024: [496]u8,
+            ///  The memory that stores Y
+            Y_MEM: [16]u8,
+            reserved1536: [496]u8,
+            ///  The memory that stores X
+            X_MEM: [16]u8,
+            reserved2048: [496]u8,
+            ///  RSA M_prime register
+            M_PRIME: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores m'
+                M_PRIME: u32,
+            }),
+            ///  RSA mode register
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  rsa mode (rsa length).
+                MODE: u7,
+                padding: u25,
+            }),
+            ///  RSA query clean register
+            QUERY_CLEAN: mmio.Mmio(packed struct(u32) {
+                ///  query clean
+                QUERY_CLEAN: u1,
+                padding: u31,
+            }),
+            ///  RSA modular exponentiation trigger register.
+            SET_START_MODEXP: mmio.Mmio(packed struct(u32) {
+                ///  start modular exponentiation
+                SET_START_MODEXP: u1,
+                padding: u31,
+            }),
+            ///  RSA modular multiplication trigger register.
+            SET_START_MODMULT: mmio.Mmio(packed struct(u32) {
+                ///  start modular multiplication
+                SET_START_MODMULT: u1,
+                padding: u31,
+            }),
+            ///  RSA normal multiplication trigger register.
+            SET_START_MULT: mmio.Mmio(packed struct(u32) {
+                ///  start multiplicaiton
+                SET_START_MULT: u1,
+                padding: u31,
+            }),
+            ///  RSA query idle register
+            QUERY_IDLE: mmio.Mmio(packed struct(u32) {
+                ///  query rsa idle. 1'b0: busy, 1'b1: idle
+                QUERY_IDLE: u1,
+                padding: u31,
+            }),
+            ///  RSA interrupt clear register
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  set this bit to clear RSA interrupt.
+                CLEAR_INTERRUPT: u1,
+                padding: u31,
+            }),
+            ///  RSA constant time option register
+            CONSTANT_TIME: mmio.Mmio(packed struct(u32) {
+                ///  Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).
+                CONSTANT_TIME: u1,
+                padding: u31,
+            }),
+            ///  RSA search option
+            SEARCH_ENABLE: mmio.Mmio(packed struct(u32) {
+                ///  Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.
+                SEARCH_ENABLE: u1,
+                padding: u31,
+            }),
+            ///  RSA search position configure register
+            SEARCH_POS: mmio.Mmio(packed struct(u32) {
+                ///  Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.
+                SEARCH_POS: u12,
+                padding: u20,
+            }),
+            ///  RSA interrupt enable register
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).
+                INT_ENA: u1,
+                padding: u31,
+            }),
+            ///  RSA version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  rsa version information
+                DATE: u30,
+                padding: u2,
+            }),
+        };
+
+        ///  Real-Time Clock Control
+        pub const RTC_CNTL = extern struct {
+            ///  rtc configure register
+            OPTIONS0: mmio.Mmio(packed struct(u32) {
+                ///  {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU
+                SW_STALL_APPCPU_C0: u2,
+                ///  {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU
+                SW_STALL_PROCPU_C0: u2,
+                ///  APP CPU SW reset
+                SW_APPCPU_RST: u1,
+                ///  PRO CPU SW reset
+                SW_PROCPU_RST: u1,
+                ///  BB_I2C force power down
+                BB_I2C_FORCE_PD: u1,
+                ///  BB_I2C force power up
+                BB_I2C_FORCE_PU: u1,
+                ///  BB_PLL _I2C force power down
+                BBPLL_I2C_FORCE_PD: u1,
+                ///  BB_PLL_I2C force power up
+                BBPLL_I2C_FORCE_PU: u1,
+                ///  BB_PLL force power down
+                BBPLL_FORCE_PD: u1,
+                ///  BB_PLL force power up
+                BBPLL_FORCE_PU: u1,
+                ///  crystall force power down
+                XTL_FORCE_PD: u1,
+                ///  crystall force power up
+                XTL_FORCE_PU: u1,
+                ///  wait bias_sleep and current source wakeup
+                XTL_EN_WAIT: u4,
+                reserved20: u2,
+                ///  analog configure
+                XTL_EXT_CTR_SEL: u3,
+                ///  analog configure
+                XTL_FORCE_ISO: u1,
+                ///  analog configure
+                PLL_FORCE_ISO: u1,
+                ///  analog configure
+                ANALOG_FORCE_ISO: u1,
+                ///  analog configure
+                XTL_FORCE_NOISO: u1,
+                ///  analog configure
+                PLL_FORCE_NOISO: u1,
+                ///  analog configure
+                ANALOG_FORCE_NOISO: u1,
+                ///  digital wrap force reset in deep sleep
+                DG_WRAP_FORCE_RST: u1,
+                ///  digital core force no reset in deep sleep
+                DG_WRAP_FORCE_NORST: u1,
+                ///  SW system reset
+                SW_SYS_RST: u1,
+            }),
+            ///  rtc configure register
+            SLP_TIMER0: mmio.Mmio(packed struct(u32) {
+                ///  configure the sleep time
+                SLP_VAL_LO: u32,
+            }),
+            ///  rtc configure register
+            SLP_TIMER1: mmio.Mmio(packed struct(u32) {
+                ///  RTC sleep timer high 16 bits
+                SLP_VAL_HI: u16,
+                ///  timer alarm enable bit
+                RTC_MAIN_TIMER_ALARM_EN: u1,
+                padding: u15,
+            }),
+            ///  rtc configure register
+            TIME_UPDATE: mmio.Mmio(packed struct(u32) {
+                reserved27: u27,
+                ///  Enable to record system stall time
+                TIMER_SYS_STALL: u1,
+                ///  Enable to record 40M XTAL OFF time
+                TIMER_XTL_OFF: u1,
+                ///  enable to record system reset time
+                TIMER_SYS_RST: u1,
+                reserved31: u1,
+                ///  Set 1: to update register with RTC timer
+                RTC_TIME_UPDATE: u1,
+            }),
+            ///  rtc configure register
+            TIME_LOW0: mmio.Mmio(packed struct(u32) {
+                ///  RTC timer low 32 bits
+                RTC_TIMER_VALUE0_LOW: u32,
+            }),
+            ///  rtc configure register
+            TIME_HIGH0: mmio.Mmio(packed struct(u32) {
+                ///  RTC timer high 16 bits
+                RTC_TIMER_VALUE0_HIGH: u16,
+                padding: u16,
+            }),
+            ///  rtc configure register
+            STATE0: mmio.Mmio(packed struct(u32) {
+                ///  rtc software interrupt to main cpu
+                RTC_SW_CPU_INT: u1,
+                ///  clear rtc sleep reject cause
+                RTC_SLP_REJECT_CAUSE_CLR: u1,
+                reserved22: u20,
+                ///  1: APB to RTC using bridge
+                APB2RTC_BRIDGE_SEL: u1,
+                reserved28: u5,
+                ///  SDIO active indication
+                SDIO_ACTIVE_IND: u1,
+                ///  leep wakeup bit
+                SLP_WAKEUP: u1,
+                ///  leep reject bit
+                SLP_REJECT: u1,
+                ///  sleep enable bit
+                SLEEP_EN: u1,
+            }),
+            ///  rtc configure register
+            TIMER1: mmio.Mmio(packed struct(u32) {
+                ///  CPU stall enable bit
+                CPU_STALL_EN: u1,
+                ///  CPU stall wait cycles in fast_clk_rtc
+                CPU_STALL_WAIT: u5,
+                ///  CK8M wait cycles in slow_clk_rtc
+                CK8M_WAIT: u8,
+                ///  XTAL wait cycles in slow_clk_rtc
+                XTL_BUF_WAIT: u10,
+                ///  PLL wait cycles in slow_clk_rtc
+                PLL_BUF_WAIT: u8,
+            }),
+            ///  rtc configure register
+            TIMER2: mmio.Mmio(packed struct(u32) {
+                reserved24: u24,
+                ///  minimal cycles in slow_clk_rtc for CK8M in power down state
+                MIN_TIME_CK8M_OFF: u8,
+            }),
+            ///  rtc configure register
+            TIMER3: mmio.Mmio(packed struct(u32) {
+                ///  wifi power domain wakeup time
+                WIFI_WAIT_TIMER: u9,
+                ///  wifi power domain power on time
+                WIFI_POWERUP_TIMER: u7,
+                ///  bt power domain wakeup time
+                BT_WAIT_TIMER: u9,
+                ///  bt power domain power on time
+                BT_POWERUP_TIMER: u7,
+            }),
+            ///  rtc configure register
+            TIMER4: mmio.Mmio(packed struct(u32) {
+                ///  cpu top power domain wakeup time
+                CPU_TOP_WAIT_TIMER: u9,
+                ///  cpu top power domain power on time
+                CPU_TOP_POWERUP_TIMER: u7,
+                ///  digital wrap power domain wakeup time
+                DG_WRAP_WAIT_TIMER: u9,
+                ///  digital wrap power domain power on time
+                DG_WRAP_POWERUP_TIMER: u7,
+            }),
+            ///  rtc configure register
+            TIMER5: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  minimal sleep cycles in slow_clk_rtc
+                MIN_SLP_VAL: u8,
+                padding: u16,
+            }),
+            ///  rtc configure register
+            TIMER6: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  digital peri power domain wakeup time
+                DG_PERI_WAIT_TIMER: u9,
+                ///  digital peri power domain power on time
+                DG_PERI_POWERUP_TIMER: u7,
+            }),
+            ///  rtc configure register
+            ANA_CONF: mmio.Mmio(packed struct(u32) {
+                reserved18: u18,
+                ///  force no bypass i2c power on reset
+                RESET_POR_FORCE_PD: u1,
+                ///  force bypass i2c power on reset
+                RESET_POR_FORCE_PU: u1,
+                ///  enable glitch reset
+                GLITCH_RST_EN: u1,
+                reserved22: u1,
+                ///  PLLA force power up
+                SAR_I2C_PU: u1,
+                ///  PLLA force power down
+                PLLA_FORCE_PD: u1,
+                ///  PLLA force power up
+                PLLA_FORCE_PU: u1,
+                ///  start BBPLL calibration during sleep
+                BBPLL_CAL_SLP_START: u1,
+                ///  1: PVTMON power up
+                PVTMON_PU: u1,
+                ///  1: TXRF_I2C power up
+                TXRF_I2C_PU: u1,
+                ///  1: RFRX_PBUS power up
+                RFRX_PBUS_PU: u1,
+                reserved30: u1,
+                ///  1: CKGEN_I2C power up
+                CKGEN_I2C_PU: u1,
+                ///  power up pll i2c
+                PLL_I2C_PU: u1,
+            }),
+            ///  rtc configure register
+            RESET_STATE: mmio.Mmio(packed struct(u32) {
+                ///  reset cause of PRO CPU
+                RESET_CAUSE_PROCPU: u6,
+                ///  reset cause of APP CPU
+                RESET_CAUSE_APPCPU: u6,
+                ///  APP CPU state vector sel
+                STAT_VECTOR_SEL_APPCPU: u1,
+                ///  PRO CPU state vector sel
+                STAT_VECTOR_SEL_PROCPU: u1,
+                ///  PRO CPU reset_flag
+                ALL_RESET_FLAG_PROCPU: u1,
+                ///  APP CPU reset flag
+                ALL_RESET_FLAG_APPCPU: u1,
+                ///  clear PRO CPU reset_flag
+                ALL_RESET_FLAG_CLR_PROCPU: u1,
+                ///  clear APP CPU reset flag
+                ALL_RESET_FLAG_CLR_APPCPU: u1,
+                ///  APPCPU OcdHaltOnReset
+                OCD_HALT_ON_RESET_APPCPU: u1,
+                ///  PROCPU OcdHaltOnReset
+                OCD_HALT_ON_RESET_PROCPU: u1,
+                ///  configure jtag reset configure
+                JTAG_RESET_FLAG_PROCPU: u1,
+                ///  configure jtag reset configure
+                JTAG_RESET_FLAG_APPCPU: u1,
+                ///  configure jtag reset configure
+                JTAG_RESET_FLAG_CLR_PROCPU: u1,
+                ///  configure jtag reset configure
+                JTAG_RESET_FLAG_CLR_APPCPU: u1,
+                ///  configure dreset configure
+                RTC_DRESET_MASK_APPCPU: u1,
+                ///  configure dreset configure
+                RTC_DRESET_MASK_PROCPU: u1,
+                padding: u6,
+            }),
+            ///  rtc configure register
+            WAKEUP_STATE: mmio.Mmio(packed struct(u32) {
+                reserved15: u15,
+                ///  wakeup enable bitmap
+                RTC_WAKEUP_ENA: u17,
+            }),
+            ///  rtc configure register
+            INT_ENA_RTC: mmio.Mmio(packed struct(u32) {
+                ///  enable sleep wakeup interrupt
+                SLP_WAKEUP_INT_ENA: u1,
+                ///  enable sleep reject interrupt
+                SLP_REJECT_INT_ENA: u1,
+                reserved3: u1,
+                ///  enable RTC WDT interrupt
+                RTC_WDT_INT_ENA: u1,
+                reserved9: u5,
+                ///  enable brown out interrupt
+                RTC_BROWN_OUT_INT_ENA: u1,
+                ///  enable RTC main timer interrupt
+                RTC_MAIN_TIMER_INT_ENA: u1,
+                reserved15: u4,
+                ///  enable super watch dog interrupt
+                RTC_SWD_INT_ENA: u1,
+                ///  enable xtal32k_dead interrupt
+                RTC_XTAL32K_DEAD_INT_ENA: u1,
+                reserved19: u2,
+                ///  enbale gitch det interrupt
+                RTC_GLITCH_DET_INT_ENA: u1,
+                ///  enbale bbpll cal end interrupt
+                RTC_BBPLL_CAL_INT_ENA: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            INT_RAW_RTC: mmio.Mmio(packed struct(u32) {
+                ///  sleep wakeup interrupt raw
+                SLP_WAKEUP_INT_RAW: u1,
+                ///  sleep reject interrupt raw
+                SLP_REJECT_INT_RAW: u1,
+                reserved3: u1,
+                ///  RTC WDT interrupt raw
+                RTC_WDT_INT_RAW: u1,
+                reserved9: u5,
+                ///  brown out interrupt raw
+                RTC_BROWN_OUT_INT_RAW: u1,
+                ///  RTC main timer interrupt raw
+                RTC_MAIN_TIMER_INT_RAW: u1,
+                reserved15: u4,
+                ///  super watch dog interrupt raw
+                RTC_SWD_INT_RAW: u1,
+                ///  xtal32k dead detection interrupt raw
+                RTC_XTAL32K_DEAD_INT_RAW: u1,
+                reserved19: u2,
+                ///  glitch_det_interrupt_raw
+                RTC_GLITCH_DET_INT_RAW: u1,
+                ///  bbpll cal end interrupt state
+                RTC_BBPLL_CAL_INT_RAW: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            INT_ST_RTC: mmio.Mmio(packed struct(u32) {
+                ///  sleep wakeup interrupt state
+                SLP_WAKEUP_INT_ST: u1,
+                ///  sleep reject interrupt state
+                SLP_REJECT_INT_ST: u1,
+                reserved3: u1,
+                ///  RTC WDT interrupt state
+                RTC_WDT_INT_ST: u1,
+                reserved9: u5,
+                ///  brown out interrupt state
+                RTC_BROWN_OUT_INT_ST: u1,
+                ///  RTC main timer interrupt state
+                RTC_MAIN_TIMER_INT_ST: u1,
+                reserved15: u4,
+                ///  super watch dog interrupt state
+                RTC_SWD_INT_ST: u1,
+                ///  xtal32k dead detection interrupt state
+                RTC_XTAL32K_DEAD_INT_ST: u1,
+                reserved19: u2,
+                ///  glitch_det_interrupt state
+                RTC_GLITCH_DET_INT_ST: u1,
+                ///  bbpll cal end interrupt state
+                RTC_BBPLL_CAL_INT_ST: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            INT_CLR_RTC: mmio.Mmio(packed struct(u32) {
+                ///  Clear sleep wakeup interrupt state
+                SLP_WAKEUP_INT_CLR: u1,
+                ///  Clear sleep reject interrupt state
+                SLP_REJECT_INT_CLR: u1,
+                reserved3: u1,
+                ///  Clear RTC WDT interrupt state
+                RTC_WDT_INT_CLR: u1,
+                reserved9: u5,
+                ///  Clear brown out interrupt state
+                RTC_BROWN_OUT_INT_CLR: u1,
+                ///  Clear RTC main timer interrupt state
+                RTC_MAIN_TIMER_INT_CLR: u1,
+                reserved15: u4,
+                ///  Clear super watch dog interrupt state
+                RTC_SWD_INT_CLR: u1,
+                ///  Clear RTC WDT interrupt state
+                RTC_XTAL32K_DEAD_INT_CLR: u1,
+                reserved19: u2,
+                ///  Clear glitch det interrupt state
+                RTC_GLITCH_DET_INT_CLR: u1,
+                ///  clear bbpll cal end interrupt state
+                RTC_BBPLL_CAL_INT_CLR: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            STORE0: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH0: u32,
+            }),
+            ///  rtc configure register
+            STORE1: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH1: u32,
+            }),
+            ///  rtc configure register
+            STORE2: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH2: u32,
+            }),
+            ///  rtc configure register
+            STORE3: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH3: u32,
+            }),
+            ///  rtc configure register
+            EXT_XTL_CONF: mmio.Mmio(packed struct(u32) {
+                ///  xtal 32k watch dog enable
+                XTAL32K_WDT_EN: u1,
+                ///  xtal 32k watch dog clock force on
+                XTAL32K_WDT_CLK_FO: u1,
+                ///  xtal 32k watch dog sw reset
+                XTAL32K_WDT_RESET: u1,
+                ///  xtal 32k external xtal clock force on
+                XTAL32K_EXT_CLK_FO: u1,
+                ///  xtal 32k switch to back up clock when xtal is dead
+                XTAL32K_AUTO_BACKUP: u1,
+                ///  xtal 32k restart xtal when xtal is dead
+                XTAL32K_AUTO_RESTART: u1,
+                ///  xtal 32k switch back xtal when xtal is restarted
+                XTAL32K_AUTO_RETURN: u1,
+                ///  Xtal 32k xpd control by sw or fsm
+                XTAL32K_XPD_FORCE: u1,
+                ///  apply an internal clock to help xtal 32k to start
+                ENCKINIT_XTAL_32K: u1,
+                ///  0: single-end buffer 1: differential buffer
+                DBUF_XTAL_32K: u1,
+                ///  xtal_32k gm control
+                DGM_XTAL_32K: u3,
+                ///  DRES_XTAL_32K
+                DRES_XTAL_32K: u3,
+                ///  XPD_XTAL_32K
+                XPD_XTAL_32K: u1,
+                ///  DAC_XTAL_32K
+                DAC_XTAL_32K: u3,
+                ///  state of 32k_wdt
+                RTC_WDT_STATE: u3,
+                ///  XTAL_32K sel. 0: external XTAL_32K
+                RTC_XTAL32K_GPIO_SEL: u1,
+                reserved30: u6,
+                ///  0: power down XTAL at high level
+                XTL_EXT_CTR_LV: u1,
+                ///  enable gpio configure xtal power on
+                XTL_EXT_CTR_EN: u1,
+            }),
+            ///  rtc configure register
+            EXT_WAKEUP_CONF: mmio.Mmio(packed struct(u32) {
+                reserved31: u31,
+                ///  enable filter for gpio wakeup event
+                GPIO_WAKEUP_FILTER: u1,
+            }),
+            ///  rtc configure register
+            SLP_REJECT_CONF: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  sleep reject enable
+                RTC_SLEEP_REJECT_ENA: u18,
+                ///  enable reject for light sleep
+                LIGHT_SLP_REJECT_EN: u1,
+                ///  enable reject for deep sleep
+                DEEP_SLP_REJECT_EN: u1,
+            }),
+            ///  rtc configure register
+            CPU_PERIOD_CONF: mmio.Mmio(packed struct(u32) {
+                reserved29: u29,
+                ///  CPU sel option
+                RTC_CPUSEL_CONF: u1,
+                ///  CPU clk sel option
+                RTC_CPUPERIOD_SEL: u2,
+            }),
+            ///  rtc configure register
+            CLK_CONF: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  efuse_clk_force_gating
+                EFUSE_CLK_FORCE_GATING: u1,
+                ///  efuse_clk_force_nogating
+                EFUSE_CLK_FORCE_NOGATING: u1,
+                ///  used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel
+                CK8M_DIV_SEL_VLD: u1,
+                ///  CK8M_D256_OUT divider. 00: div128
+                CK8M_DIV: u2,
+                ///  disable CK8M and CK8M_D256_OUT
+                ENB_CK8M: u1,
+                ///  1: CK8M_D256_OUT is actually CK8M
+                ENB_CK8M_DIV: u1,
+                ///  enable CK_XTAL_32K for digital core (no relationship with RTC core)
+                DIG_XTAL32K_EN: u1,
+                ///  enable CK8M_D256_OUT for digital core (no relationship with RTC core)
+                DIG_CLK8M_D256_EN: u1,
+                ///  enable CK8M for digital core (no relationship with RTC core)
+                DIG_CLK8M_EN: u1,
+                reserved12: u1,
+                ///  divider = reg_ck8m_div_sel + 1
+                CK8M_DIV_SEL: u3,
+                ///  XTAL force no gating during sleep
+                XTAL_FORCE_NOGATING: u1,
+                ///  CK8M force no gating during sleep
+                CK8M_FORCE_NOGATING: u1,
+                ///  CK8M_DFREQ
+                CK8M_DFREQ: u8,
+                ///  CK8M force power down
+                CK8M_FORCE_PD: u1,
+                ///  CK8M force power up
+                CK8M_FORCE_PU: u1,
+                ///  force enable xtal clk gating
+                XTAL_GLOBAL_FORCE_GATING: u1,
+                ///  force bypass xtal clk gating
+                XTAL_GLOBAL_FORCE_NOGATING: u1,
+                ///  fast_clk_rtc sel. 0: XTAL div 4
+                FAST_CLK_RTC_SEL: u1,
+                ///  slelect rtc slow clk
+                ANA_CLK_RTC_SEL: u2,
+            }),
+            ///  rtc configure register
+            SLOW_CLK_CONF: mmio.Mmio(packed struct(u32) {
+                reserved22: u22,
+                ///  used to sync div bus. clear vld before set reg_rtc_ana_clk_div
+                RTC_ANA_CLK_DIV_VLD: u1,
+                ///  the clk divider num of RTC_CLK
+                RTC_ANA_CLK_DIV: u8,
+                ///  flag rtc_slow_clk_next_edge
+                RTC_SLOW_CLK_NEXT_EDGE: u1,
+            }),
+            ///  rtc configure register
+            SDIO_CONF: mmio.Mmio(packed struct(u32) {
+                ///  timer count to apply reg_sdio_dcap after sdio power on
+                SDIO_TIMER_TARGET: u8,
+                reserved9: u1,
+                ///  Tieh = 1 mode drive ability. Initially set to 0 to limit charge current
+                SDIO_DTHDRV: u2,
+                ///  ability to prevent LDO from overshoot
+                SDIO_DCAP: u2,
+                ///  add resistor from ldo output to ground. 0: no res
+                SDIO_INITI: u2,
+                ///  0 to set init[1:0]=0
+                SDIO_EN_INITI: u1,
+                ///  tune current limit threshold when tieh = 0. About 800mA/(8+d)
+                SDIO_DCURLIM: u3,
+                ///  select current limit mode
+                SDIO_MODECURLIM: u1,
+                ///  enable current limit
+                SDIO_ENCURLIM: u1,
+                ///  power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
+                SDIO_REG_PD_EN: u1,
+                ///  1: use SW option to control SDIO_REG
+                SDIO_FORCE: u1,
+                ///  SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
+                SDIO_TIEH: u1,
+                ///  read only register for REG1P8_READY
+                _1P8_READY: u1,
+                ///  SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
+                DREFL_SDIO: u2,
+                ///  SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
+                DREFM_SDIO: u2,
+                ///  SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
+                DREFH_SDIO: u2,
+                XPD_SDIO: u1,
+            }),
+            ///  rtc configure register
+            BIAS_CONF: mmio.Mmio(packed struct(u32) {
+                DG_VDD_DRV_B_SLP: u8,
+                DG_VDD_DRV_B_SLP_EN: u1,
+                reserved10: u1,
+                ///  bias buf when rtc in normal work state
+                BIAS_BUF_IDLE: u1,
+                ///  bias buf when rtc in wakeup state
+                BIAS_BUF_WAKE: u1,
+                ///  bias buf when rtc in sleep state
+                BIAS_BUF_DEEP_SLP: u1,
+                ///  bias buf when rtc in monitor state
+                BIAS_BUF_MONITOR: u1,
+                ///  xpd cur when rtc in sleep_state
+                PD_CUR_DEEP_SLP: u1,
+                ///  xpd cur when rtc in monitor state
+                PD_CUR_MONITOR: u1,
+                ///  bias_sleep when rtc in sleep_state
+                BIAS_SLEEP_DEEP_SLP: u1,
+                ///  bias_sleep when rtc in monitor state
+                BIAS_SLEEP_MONITOR: u1,
+                ///  DBG_ATTEN when rtc in sleep state
+                DBG_ATTEN_DEEP_SLP: u4,
+                ///  DBG_ATTEN when rtc in monitor state
+                DBG_ATTEN_MONITOR: u4,
+                padding: u6,
+            }),
+            ///  rtc configure register
+            RTC_CNTL: mmio.Mmio(packed struct(u32) {
+                reserved7: u7,
+                ///  software enable digital regulator cali
+                DIG_REG_CAL_EN: u1,
+                reserved14: u6,
+                ///  SCK_DCAP
+                SCK_DCAP: u8,
+                reserved28: u6,
+                ///  RTC_DBOOST force power down
+                DBOOST_FORCE_PD: u1,
+                ///  RTC_DBOOST force power up
+                DBOOST_FORCE_PU: u1,
+                ///  RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )
+                REGULATOR_FORCE_PD: u1,
+                ///  RTC_REG force power up
+                REGULATOR_FORCE_PU: u1,
+            }),
+            ///  rtc configure register
+            PWC: mmio.Mmio(packed struct(u32) {
+                reserved21: u21,
+                ///  rtc pad force hold
+                RTC_PAD_FORCE_HOLD: u1,
+                padding: u10,
+            }),
+            ///  rtc configure register
+            DIG_PWC: mmio.Mmio(packed struct(u32) {
+                ///  vdd_spi drv's software value
+                VDD_SPI_PWR_DRV: u2,
+                ///  vdd_spi drv use software value
+                VDD_SPI_PWR_FORCE: u1,
+                ///  memories in digital core force PD in sleep
+                LSLP_MEM_FORCE_PD: u1,
+                ///  memories in digital core force PU in sleep
+                LSLP_MEM_FORCE_PU: u1,
+                reserved11: u6,
+                ///  bt force power down
+                BT_FORCE_PD: u1,
+                ///  bt force power up
+                BT_FORCE_PU: u1,
+                ///  digital peri force power down
+                DG_PERI_FORCE_PD: u1,
+                ///  digital peri force power up
+                DG_PERI_FORCE_PU: u1,
+                ///  fastmemory retention mode in sleep
+                RTC_FASTMEM_FORCE_LPD: u1,
+                ///  fastmemory donlt entry retention mode in sleep
+                RTC_FASTMEM_FORCE_LPU: u1,
+                ///  wifi force power down
+                WIFI_FORCE_PD: u1,
+                ///  wifi force power up
+                WIFI_FORCE_PU: u1,
+                ///  digital core force power down
+                DG_WRAP_FORCE_PD: u1,
+                ///  digital core force power up
+                DG_WRAP_FORCE_PU: u1,
+                ///  cpu core force power down
+                CPU_TOP_FORCE_PD: u1,
+                ///  cpu force power up
+                CPU_TOP_FORCE_PU: u1,
+                reserved27: u4,
+                ///  enable power down bt in sleep
+                BT_PD_EN: u1,
+                ///  enable power down digital peri in sleep
+                DG_PERI_PD_EN: u1,
+                ///  enable power down cpu in sleep
+                CPU_TOP_PD_EN: u1,
+                ///  enable power down wifi in sleep
+                WIFI_PD_EN: u1,
+                ///  enable power down digital wrap in sleep
+                DG_WRAP_PD_EN: u1,
+            }),
+            ///  rtc configure register
+            DIG_ISO: mmio.Mmio(packed struct(u32) {
+                reserved7: u7,
+                ///  DIG_ISO force off
+                FORCE_OFF: u1,
+                ///  DIG_ISO force on
+                FORCE_ON: u1,
+                ///  read only register to indicate digital pad auto-hold status
+                DG_PAD_AUTOHOLD: u1,
+                ///  wtite only register to clear digital pad auto-hold
+                CLR_DG_PAD_AUTOHOLD: u1,
+                ///  digital pad enable auto-hold
+                DG_PAD_AUTOHOLD_EN: u1,
+                ///  digital pad force no ISO
+                DG_PAD_FORCE_NOISO: u1,
+                ///  digital pad force ISO
+                DG_PAD_FORCE_ISO: u1,
+                ///  digital pad force un-hold
+                DG_PAD_FORCE_UNHOLD: u1,
+                ///  digital pad force hold
+                DG_PAD_FORCE_HOLD: u1,
+                reserved22: u6,
+                ///  bt force ISO
+                BT_FORCE_ISO: u1,
+                ///  bt force no ISO
+                BT_FORCE_NOISO: u1,
+                ///  Digital peri force ISO
+                DG_PERI_FORCE_ISO: u1,
+                ///  digital peri force no ISO
+                DG_PERI_FORCE_NOISO: u1,
+                ///  cpu force ISO
+                CPU_TOP_FORCE_ISO: u1,
+                ///  cpu force no ISO
+                CPU_TOP_FORCE_NOISO: u1,
+                ///  wifi force ISO
+                WIFI_FORCE_ISO: u1,
+                ///  wifi force no ISO
+                WIFI_FORCE_NOISO: u1,
+                ///  digital core force ISO
+                DG_WRAP_FORCE_ISO: u1,
+                ///  digital core force no ISO
+                DG_WRAP_FORCE_NOISO: u1,
+            }),
+            ///  rtc configure register
+            WDTCONFIG0: mmio.Mmio(packed struct(u32) {
+                ///  chip reset siginal pulse width
+                WDT_CHIP_RESET_WIDTH: u8,
+                ///  wdt reset whole chip enable
+                WDT_CHIP_RESET_EN: u1,
+                ///  pause WDT in sleep
+                WDT_PAUSE_IN_SLP: u1,
+                ///  enable WDT reset APP CPU
+                WDT_APPCPU_RESET_EN: u1,
+                ///  enable WDT reset PRO CPU
+                WDT_PROCPU_RESET_EN: u1,
+                ///  enable WDT in flash boot
+                WDT_FLASHBOOT_MOD_EN: u1,
+                ///  system reset counter length
+                WDT_SYS_RESET_LENGTH: u3,
+                ///  CPU reset counter length
+                WDT_CPU_RESET_LENGTH: u3,
+                ///  1: interrupt stage en
+                WDT_STG3: u3,
+                ///  1: interrupt stage en
+                WDT_STG2: u3,
+                ///  1: interrupt stage en
+                WDT_STG1: u3,
+                ///  1: interrupt stage en
+                WDT_STG0: u3,
+                ///  enable rtc wdt
+                WDT_EN: u1,
+            }),
+            ///  rtc configure register
+            WDTCONFIG1: mmio.Mmio(packed struct(u32) {
+                ///  the hold time of stage0
+                WDT_STG0_HOLD: u32,
+            }),
+            ///  rtc configure register
+            WDTCONFIG2: mmio.Mmio(packed struct(u32) {
+                ///  the hold time of stage1
+                WDT_STG1_HOLD: u32,
+            }),
+            ///  rtc configure register
+            WDTCONFIG3: mmio.Mmio(packed struct(u32) {
+                ///  the hold time of stage2
+                WDT_STG2_HOLD: u32,
+            }),
+            ///  rtc configure register
+            WDTCONFIG4: mmio.Mmio(packed struct(u32) {
+                ///  the hold time of stage3
+                WDT_STG3_HOLD: u32,
+            }),
+            ///  rtc configure register
+            WDTFEED: mmio.Mmio(packed struct(u32) {
+                reserved31: u31,
+                ///  sw feed rtc wdt
+                RTC_WDT_FEED: u1,
+            }),
+            ///  rtc configure register
+            WDTWPROTECT: mmio.Mmio(packed struct(u32) {
+                ///  the key of rtc wdt
+                WDT_WKEY: u32,
+            }),
+            ///  rtc configure register
+            SWD_CONF: mmio.Mmio(packed struct(u32) {
+                ///  swd reset flag
+                SWD_RESET_FLAG: u1,
+                ///  swd interrupt for feeding
+                SWD_FEED_INT: u1,
+                reserved17: u15,
+                ///  Bypass swd rst
+                SWD_BYPASS_RST: u1,
+                ///  adjust signal width send to swd
+                SWD_SIGNAL_WIDTH: u10,
+                ///  reset swd reset flag
+                SWD_RST_FLAG_CLR: u1,
+                ///  Sw feed swd
+                SWD_FEED: u1,
+                ///  disabel SWD
+                SWD_DISABLE: u1,
+                ///  automatically feed swd when int comes
+                SWD_AUTO_FEED_EN: u1,
+            }),
+            ///  rtc configure register
+            SWD_WPROTECT: mmio.Mmio(packed struct(u32) {
+                ///  the key of super wdt
+                SWD_WKEY: u32,
+            }),
+            ///  rtc configure register
+            SW_CPU_STALL: mmio.Mmio(packed struct(u32) {
+                reserved20: u20,
+                ///  {reg_sw_stall_appcpu_c1[5:0]
+                SW_STALL_APPCPU_C1: u6,
+                ///  stall cpu by software
+                SW_STALL_PROCPU_C1: u6,
+            }),
+            ///  rtc configure register
+            STORE4: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH4: u32,
+            }),
+            ///  rtc configure register
+            STORE5: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH5: u32,
+            }),
+            ///  rtc configure register
+            STORE6: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH6: u32,
+            }),
+            ///  rtc configure register
+            STORE7: mmio.Mmio(packed struct(u32) {
+                ///  reserved register
+                RTC_SCRATCH7: u32,
+            }),
+            ///  rtc configure register
+            LOW_POWER_ST: mmio.Mmio(packed struct(u32) {
+                ///  rom0 power down
+                XPD_ROM0: u1,
+                reserved2: u1,
+                ///  External DCDC power down
+                XPD_DIG_DCDC: u1,
+                ///  rtc peripheral iso
+                RTC_PERI_ISO: u1,
+                ///  rtc peripheral power down
+                XPD_RTC_PERI: u1,
+                ///  wifi iso
+                WIFI_ISO: u1,
+                ///  wifi wrap power down
+                XPD_WIFI: u1,
+                ///  digital wrap iso
+                DIG_ISO: u1,
+                ///  digital wrap power down
+                XPD_DIG: u1,
+                ///  touch should start to work
+                RTC_TOUCH_STATE_START: u1,
+                ///  touch is about to working. Switch rtc main state
+                RTC_TOUCH_STATE_SWITCH: u1,
+                ///  touch is in sleep state
+                RTC_TOUCH_STATE_SLP: u1,
+                ///  touch is done
+                RTC_TOUCH_STATE_DONE: u1,
+                ///  ulp/cocpu should start to work
+                RTC_COCPU_STATE_START: u1,
+                ///  ulp/cocpu is about to working. Switch rtc main state
+                RTC_COCPU_STATE_SWITCH: u1,
+                ///  ulp/cocpu is in sleep state
+                RTC_COCPU_STATE_SLP: u1,
+                ///  ulp/cocpu is done
+                RTC_COCPU_STATE_DONE: u1,
+                ///  no use any more
+                RTC_MAIN_STATE_XTAL_ISO: u1,
+                ///  rtc main state machine is in states that pll should be running
+                RTC_MAIN_STATE_PLL_ON: u1,
+                ///  rtc is ready to receive wake up trigger from wake up source
+                RTC_RDY_FOR_WAKEUP: u1,
+                ///  rtc main state machine has been waited for some cycles
+                RTC_MAIN_STATE_WAIT_END: u1,
+                ///  rtc main state machine is in the states of wakeup process
+                RTC_IN_WAKEUP_STATE: u1,
+                ///  rtc main state machine is in the states of low power
+                RTC_IN_LOW_POWER_STATE: u1,
+                ///  rtc main state machine is in wait 8m state
+                RTC_MAIN_STATE_IN_WAIT_8M: u1,
+                ///  rtc main state machine is in wait pll state
+                RTC_MAIN_STATE_IN_WAIT_PLL: u1,
+                ///  rtc main state machine is in wait xtal state
+                RTC_MAIN_STATE_IN_WAIT_XTL: u1,
+                ///  rtc main state machine is in sleep state
+                RTC_MAIN_STATE_IN_SLP: u1,
+                ///  rtc main state machine is in idle state
+                RTC_MAIN_STATE_IN_IDLE: u1,
+                ///  rtc main state machine status
+                RTC_MAIN_STATE: u4,
+            }),
+            ///  rtc configure register
+            DIAG0: mmio.Mmio(packed struct(u32) {
+                RTC_LOW_POWER_DIAG1: u32,
+            }),
+            ///  rtc configure register
+            PAD_HOLD: mmio.Mmio(packed struct(u32) {
+                ///  the hold configure of rtc gpio0
+                RTC_GPIO_PIN0_HOLD: u1,
+                ///  the hold configure of rtc gpio1
+                RTC_GPIO_PIN1_HOLD: u1,
+                ///  the hold configure of rtc gpio2
+                RTC_GPIO_PIN2_HOLD: u1,
+                ///  the hold configure of rtc gpio3
+                RTC_GPIO_PIN3_HOLD: u1,
+                ///  the hold configure of rtc gpio4
+                RTC_GPIO_PIN4_HOLD: u1,
+                ///  the hold configure of rtc gpio5
+                RTC_GPIO_PIN5_HOLD: u1,
+                padding: u26,
+            }),
+            ///  rtc configure register
+            DIG_PAD_HOLD: mmio.Mmio(packed struct(u32) {
+                ///  the configure of digital pad
+                DIG_PAD_HOLD: u32,
+            }),
+            ///  rtc configure register
+            BROWN_OUT: mmio.Mmio(packed struct(u32) {
+                reserved4: u4,
+                ///  brown out interrupt wait cycles
+                INT_WAIT: u10,
+                ///  enable close flash when brown out happens
+                CLOSE_FLASH_ENA: u1,
+                ///  enable power down RF when brown out happens
+                PD_RF_ENA: u1,
+                ///  brown out reset wait cycles
+                RST_WAIT: u10,
+                ///  enable brown out reset
+                RST_ENA: u1,
+                ///  1: 4-pos reset
+                RST_SEL: u1,
+                ///  brown_out origin reset enable
+                ANA_RST_EN: u1,
+                ///  clear brown out counter
+                CNT_CLR: u1,
+                ///  enable brown out
+                ENA: u1,
+                ///  the flag of brown det from analog
+                DET: u1,
+            }),
+            ///  rtc configure register
+            TIME_LOW1: mmio.Mmio(packed struct(u32) {
+                ///  RTC timer low 32 bits
+                RTC_TIMER_VALUE1_LOW: u32,
+            }),
+            ///  rtc configure register
+            TIME_HIGH1: mmio.Mmio(packed struct(u32) {
+                ///  RTC timer high 16 bits
+                RTC_TIMER_VALUE1_HIGH: u16,
+                padding: u16,
+            }),
+            ///  rtc configure register
+            XTAL32K_CLK_FACTOR: mmio.Mmio(packed struct(u32) {
+                ///  xtal 32k watch dog backup clock factor
+                XTAL32K_CLK_FACTOR: u32,
+            }),
+            ///  rtc configure register
+            XTAL32K_CONF: mmio.Mmio(packed struct(u32) {
+                ///  cycles to wait to return noral xtal 32k
+                XTAL32K_RETURN_WAIT: u4,
+                ///  cycles to wait to repower on xtal 32k
+                XTAL32K_RESTART_WAIT: u16,
+                ///  If no clock detected for this amount of time
+                XTAL32K_WDT_TIMEOUT: u8,
+                ///  if restarted xtal32k period is smaller than this
+                XTAL32K_STABLE_THRES: u4,
+            }),
+            ///  rtc configure register
+            USB_CONF: mmio.Mmio(packed struct(u32) {
+                reserved18: u18,
+                ///  disable io_mux reset
+                IO_MUX_RESET_DISABLE: u1,
+                padding: u13,
+            }),
+            ///  RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG
+            SLP_REJECT_CAUSE: mmio.Mmio(packed struct(u32) {
+                ///  sleep reject cause
+                REJECT_CAUSE: u18,
+                padding: u14,
+            }),
+            ///  rtc configure register
+            OPTION1: mmio.Mmio(packed struct(u32) {
+                ///  force chip entry download mode
+                FORCE_DOWNLOAD_BOOT: u1,
+                padding: u31,
+            }),
+            ///  RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG
+            SLP_WAKEUP_CAUSE: mmio.Mmio(packed struct(u32) {
+                ///  sleep wakeup cause
+                WAKEUP_CAUSE: u17,
+                padding: u15,
+            }),
+            ///  rtc configure register
+            ULP_CP_TIMER_1: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  sleep cycles for ULP-coprocessor timer
+                ULP_CP_TIMER_SLP_CYCLE: u24,
+            }),
+            ///  rtc configure register
+            INT_ENA_RTC_W1TS: mmio.Mmio(packed struct(u32) {
+                ///  enable sleep wakeup interrupt
+                SLP_WAKEUP_INT_ENA_W1TS: u1,
+                ///  enable sleep reject interrupt
+                SLP_REJECT_INT_ENA_W1TS: u1,
+                reserved3: u1,
+                ///  enable RTC WDT interrupt
+                RTC_WDT_INT_ENA_W1TS: u1,
+                reserved9: u5,
+                ///  enable brown out interrupt
+                RTC_BROWN_OUT_INT_ENA_W1TS: u1,
+                ///  enable RTC main timer interrupt
+                RTC_MAIN_TIMER_INT_ENA_W1TS: u1,
+                reserved15: u4,
+                ///  enable super watch dog interrupt
+                RTC_SWD_INT_ENA_W1TS: u1,
+                ///  enable xtal32k_dead interrupt
+                RTC_XTAL32K_DEAD_INT_ENA_W1TS: u1,
+                reserved19: u2,
+                ///  enbale gitch det interrupt
+                RTC_GLITCH_DET_INT_ENA_W1TS: u1,
+                ///  enbale bbpll cal interrupt
+                RTC_BBPLL_CAL_INT_ENA_W1TS: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            INT_ENA_RTC_W1TC: mmio.Mmio(packed struct(u32) {
+                ///  clear sleep wakeup interrupt enable
+                SLP_WAKEUP_INT_ENA_W1TC: u1,
+                ///  clear sleep reject interrupt enable
+                SLP_REJECT_INT_ENA_W1TC: u1,
+                reserved3: u1,
+                ///  clear RTC WDT interrupt enable
+                RTC_WDT_INT_ENA_W1TC: u1,
+                reserved9: u5,
+                ///  clear brown out interrupt enable
+                RTC_BROWN_OUT_INT_ENA_W1TC: u1,
+                ///  Clear RTC main timer interrupt enable
+                RTC_MAIN_TIMER_INT_ENA_W1TC: u1,
+                reserved15: u4,
+                ///  clear super watch dog interrupt enable
+                RTC_SWD_INT_ENA_W1TC: u1,
+                ///  clear xtal32k_dead interrupt enable
+                RTC_XTAL32K_DEAD_INT_ENA_W1TC: u1,
+                reserved19: u2,
+                ///  clear gitch det interrupt enable
+                RTC_GLITCH_DET_INT_ENA_W1TC: u1,
+                ///  clear bbpll cal interrupt enable
+                RTC_BBPLL_CAL_INT_ENA_W1TC: u1,
+                padding: u11,
+            }),
+            ///  rtc configure register
+            RETENTION_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved18: u18,
+                ///  Retention clk sel
+                RETENTION_CLK_SEL: u1,
+                ///  Retention done wait time
+                RETENTION_DONE_WAIT: u3,
+                ///  Retention clkoff wait time
+                RETENTION_CLKOFF_WAIT: u4,
+                ///  enable cpu retention when light sleep
+                RETENTION_EN: u1,
+                ///  wait cycles for rention operation
+                RETENTION_WAIT: u5,
+            }),
+            ///  rtc configure register
+            FIB_SEL: mmio.Mmio(packed struct(u32) {
+                ///  select use analog fib signal
+                RTC_FIB_SEL: u3,
+                padding: u29,
+            }),
+            ///  rtc configure register
+            GPIO_WAKEUP: mmio.Mmio(packed struct(u32) {
+                ///  rtc gpio wakeup flag
+                RTC_GPIO_WAKEUP_STATUS: u6,
+                ///  clear rtc gpio wakeup flag
+                RTC_GPIO_WAKEUP_STATUS_CLR: u1,
+                ///  enable rtc io clk gate
+                RTC_GPIO_PIN_CLK_GATE: u1,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN5_INT_TYPE: u3,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN4_INT_TYPE: u3,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN3_INT_TYPE: u3,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN2_INT_TYPE: u3,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN1_INT_TYPE: u3,
+                ///  configure gpio wakeup type
+                RTC_GPIO_PIN0_INT_TYPE: u3,
+                ///  enable wakeup from rtc gpio5
+                RTC_GPIO_PIN5_WAKEUP_ENABLE: u1,
+                ///  enable wakeup from rtc gpio4
+                RTC_GPIO_PIN4_WAKEUP_ENABLE: u1,
+                ///  enable wakeup from rtc gpio3
+                RTC_GPIO_PIN3_WAKEUP_ENABLE: u1,
+                ///  enable wakeup from rtc gpio2
+                RTC_GPIO_PIN2_WAKEUP_ENABLE: u1,
+                ///  enable wakeup from rtc gpio1
+                RTC_GPIO_PIN1_WAKEUP_ENABLE: u1,
+                ///  enable wakeup from rtc gpio0
+                RTC_GPIO_PIN0_WAKEUP_ENABLE: u1,
+            }),
+            ///  rtc configure register
+            DBG_SEL: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  use for debug
+                RTC_DEBUG_12M_NO_GATING: u1,
+                ///  use for debug
+                RTC_DEBUG_BIT_SEL: u5,
+                ///  use for debug
+                RTC_DEBUG_SEL0: u5,
+                ///  use for debug
+                RTC_DEBUG_SEL1: u5,
+                ///  use for debug
+                RTC_DEBUG_SEL2: u5,
+                ///  use for debug
+                RTC_DEBUG_SEL3: u5,
+                ///  use for debug
+                RTC_DEBUG_SEL4: u5,
+            }),
+            ///  rtc configure register
+            DBG_MAP: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  use for debug
+                RTC_GPIO_PIN5_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN4_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN3_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN2_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN1_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN0_MUX_SEL: u1,
+                ///  use for debug
+                RTC_GPIO_PIN5_FUN_SEL: u4,
+                ///  use for debug
+                RTC_GPIO_PIN4_FUN_SEL: u4,
+                ///  use for debug
+                RTC_GPIO_PIN3_FUN_SEL: u4,
+                ///  use for debug
+                RTC_GPIO_PIN2_FUN_SEL: u4,
+                ///  use for debug
+                RTC_GPIO_PIN1_FUN_SEL: u4,
+                ///  use for debug
+                RTC_GPIO_PIN0_FUN_SEL: u4,
+            }),
+            ///  rtc configure register
+            SENSOR_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved27: u27,
+                ///  reg_sar2_pwdet_cct
+                SAR2_PWDET_CCT: u3,
+                ///  force power up SAR
+                FORCE_XPD_SAR: u2,
+            }),
+            ///  rtc configure register
+            DBG_SAR_SEL: mmio.Mmio(packed struct(u32) {
+                reserved27: u27,
+                ///  use for debug
+                SAR_DEBUG_SEL: u5,
+            }),
+            ///  rtc configure register
+            PG_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved26: u26,
+                ///  power glitch desense
+                POWER_GLITCH_DSENSE: u2,
+                ///  force disable power glitch
+                POWER_GLITCH_FORCE_PD: u1,
+                ///  force enable power glitch
+                POWER_GLITCH_FORCE_PU: u1,
+                ///  use efuse value control power glitch enable
+                POWER_GLITCH_EFUSE_SEL: u1,
+                ///  enable power glitch
+                POWER_GLITCH_EN: u1,
+            }),
+            reserved508: [212]u8,
+            ///  rtc configure register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  verision
+                RTC_CNTL_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  Sensitive
+        pub const SENSITIVE = extern struct {
+            ///  SENSITIVE_ROM_TABLE_LOCK_REG
+            ROM_TABLE_LOCK: mmio.Mmio(packed struct(u32) {
+                ///  rom_table_lock
+                ROM_TABLE_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_ROM_TABLE_REG
+            ROM_TABLE: mmio.Mmio(packed struct(u32) {
+                ///  rom_table
+                ROM_TABLE: u32,
+            }),
+            ///  SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
+            PRIVILEGE_MODE_SEL_LOCK: mmio.Mmio(packed struct(u32) {
+                ///  privilege_mode_sel_lock
+                PRIVILEGE_MODE_SEL_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_PRIVILEGE_MODE_SEL_REG
+            PRIVILEGE_MODE_SEL: mmio.Mmio(packed struct(u32) {
+                ///  privilege_mode_sel
+                PRIVILEGE_MODE_SEL: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
+            APB_PERIPHERAL_ACCESS_0: mmio.Mmio(packed struct(u32) {
+                ///  apb_peripheral_access_lock
+                APB_PERIPHERAL_ACCESS_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
+            APB_PERIPHERAL_ACCESS_1: mmio.Mmio(packed struct(u32) {
+                ///  apb_peripheral_access_split_burst
+                APB_PERIPHERAL_ACCESS_SPLIT_BURST: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
+            INTERNAL_SRAM_USAGE_0: mmio.Mmio(packed struct(u32) {
+                ///  internal_sram_usage_lock
+                INTERNAL_SRAM_USAGE_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
+            INTERNAL_SRAM_USAGE_1: mmio.Mmio(packed struct(u32) {
+                ///  internal_sram_usage_cpu_cache
+                INTERNAL_SRAM_USAGE_CPU_CACHE: u1,
+                ///  internal_sram_usage_cpu_sram
+                INTERNAL_SRAM_USAGE_CPU_SRAM: u3,
+                padding: u28,
+            }),
+            ///  SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
+            INTERNAL_SRAM_USAGE_3: mmio.Mmio(packed struct(u32) {
+                ///  internal_sram_usage_mac_dump_sram
+                INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM: u3,
+                ///  internal_sram_alloc_mac_dump
+                INTERNAL_SRAM_ALLOC_MAC_DUMP: u1,
+                padding: u28,
+            }),
+            ///  SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
+            INTERNAL_SRAM_USAGE_4: mmio.Mmio(packed struct(u32) {
+                ///  internal_sram_usage_log_sram
+                INTERNAL_SRAM_USAGE_LOG_SRAM: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CACHE_TAG_ACCESS_0_REG
+            CACHE_TAG_ACCESS_0: mmio.Mmio(packed struct(u32) {
+                ///  cache_tag_access_lock
+                CACHE_TAG_ACCESS_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CACHE_TAG_ACCESS_1_REG
+            CACHE_TAG_ACCESS_1: mmio.Mmio(packed struct(u32) {
+                ///  pro_i_tag_rd_acs
+                PRO_I_TAG_RD_ACS: u1,
+                ///  pro_i_tag_wr_acs
+                PRO_I_TAG_WR_ACS: u1,
+                ///  pro_d_tag_rd_acs
+                PRO_D_TAG_RD_ACS: u1,
+                ///  pro_d_tag_wr_acs
+                PRO_D_TAG_WR_ACS: u1,
+                padding: u28,
+            }),
+            ///  SENSITIVE_CACHE_MMU_ACCESS_0_REG
+            CACHE_MMU_ACCESS_0: mmio.Mmio(packed struct(u32) {
+                ///  cache_mmu_access_lock
+                CACHE_MMU_ACCESS_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CACHE_MMU_ACCESS_1_REG
+            CACHE_MMU_ACCESS_1: mmio.Mmio(packed struct(u32) {
+                ///  pro_mmu_rd_acs
+                PRO_MMU_RD_ACS: u1,
+                ///  pro_mmu_wr_acs
+                PRO_MMU_WR_ACS: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_spi2_pms_constrain_lock
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_SPI2_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_uchi0_pms_constrain_lock
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_i2s0_pms_constrain_lock
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_I2S0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_mac_pms_constrain_lock
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_MAC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_backup_pms_constrain_lock
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_LC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_lc_pms_constrain_lock
+                DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_LC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_AES_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_aes_pms_constrain_lock
+                DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_AES_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_sha_pms_constrain_lock
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_SHA_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_adc_dac_pms_constrain_lock
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
+            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3
+                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                padding: u12,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
+            DMA_APBPERI_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_pms_monitor_lock
+                DMA_APBPERI_PMS_MONITOR_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
+            DMA_APBPERI_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_pms_monitor_violate_clr
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR: u1,
+                ///  dma_apbperi_pms_monitor_violate_en
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
+            DMA_APBPERI_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_pms_monitor_violate_intr
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR: u1,
+                ///  dma_apbperi_pms_monitor_violate_status_world
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+                ///  dma_apbperi_pms_monitor_violate_status_addr
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+                padding: u5,
+            }),
+            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
+            DMA_APBPERI_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
+                ///  dma_apbperi_pms_monitor_violate_status_wr
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+                ///  dma_apbperi_pms_monitor_violate_status_byteen
+                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
+                padding: u27,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_dram0_dma_split_line_constrain_lock
+                CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_dram0_dma_sram_category_0
+                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0: u2,
+                ///  core_x_iram0_dram0_dma_sram_category_1
+                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1: u2,
+                ///  core_x_iram0_dram0_dma_sram_category_2
+                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2: u2,
+                reserved14: u8,
+                ///  core_x_iram0_dram0_dma_sram_splitaddr
+                CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR: u8,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_sram_line_0_category_0
+                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0: u2,
+                ///  core_x_iram0_sram_line_0_category_1
+                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1: u2,
+                ///  core_x_iram0_sram_line_0_category_2
+                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2: u2,
+                reserved14: u8,
+                ///  core_x_iram0_sram_line_0_splitaddr
+                CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR: u8,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_sram_line_1_category_0
+                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0: u2,
+                ///  core_x_iram0_sram_line_1_category_1
+                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1: u2,
+                ///  core_x_iram0_sram_line_1_category_2
+                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2: u2,
+                reserved14: u8,
+                ///  core_x_iram0_sram_line_1_splitaddr
+                CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR: u8,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
+                ///  core_x_dram0_dma_sram_line_0_category_0
+                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0: u2,
+                ///  core_x_dram0_dma_sram_line_0_category_1
+                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1: u2,
+                ///  core_x_dram0_dma_sram_line_0_category_2
+                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2: u2,
+                reserved14: u8,
+                ///  core_x_dram0_dma_sram_line_0_splitaddr
+                CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR: u8,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
+            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
+                ///  core_x_dram0_dma_sram_line_1_category_0
+                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0: u2,
+                ///  core_x_dram0_dma_sram_line_1_category_1
+                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1: u2,
+                ///  core_x_dram0_dma_sram_line_1_category_2
+                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2: u2,
+                reserved14: u8,
+                ///  core_x_dram0_dma_sram_line_1_splitaddr
+                CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR: u8,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
+            CORE_X_IRAM0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_pms_constrain_lock
+                CORE_X_IRAM0_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
+            CORE_X_IRAM0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_pms_constrain_sram_world_1_pms_0
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_1_pms_1
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_1_pms_2
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_1_pms_3
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0: u3,
+                reserved18: u3,
+                ///  core_x_iram0_pms_constrain_rom_world_1_pms
+                CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u3,
+                padding: u11,
+            }),
+            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
+            CORE_X_IRAM0_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
+                ///  core_x_iram0_pms_constrain_sram_world_0_pms_0
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_0_pms_1
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_0_pms_2
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_0_pms_3
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u3,
+                ///  core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0
+                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0: u3,
+                reserved18: u3,
+                ///  core_x_iram0_pms_constrain_rom_world_0_pms
+                CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u3,
+                padding: u11,
+            }),
+            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
+            CORE_0_IRAM0_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  core_0_iram0_pms_monitor_lock
+                CORE_0_IRAM0_PMS_MONITOR_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
+            CORE_0_IRAM0_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  core_0_iram0_pms_monitor_violate_clr
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
+                ///  core_0_iram0_pms_monitor_violate_en
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
+            CORE_0_IRAM0_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  core_0_iram0_pms_monitor_violate_intr
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
+                ///  core_0_iram0_pms_monitor_violate_status_wr
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+                ///  core_0_iram0_pms_monitor_violate_status_loadstore
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE: u1,
+                ///  core_0_iram0_pms_monitor_violate_status_world
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+                ///  core_0_iram0_pms_monitor_violate_status_addr
+                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+                padding: u3,
+            }),
+            ///  SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
+            CORE_X_DRAM0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  core_x_dram0_pms_constrain_lock
+                CORE_X_DRAM0_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
+            CORE_X_DRAM0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  core_x_dram0_pms_constrain_sram_world_0_pms_0
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_0_pms_1
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_0_pms_2
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_0_pms_3
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
+                reserved12: u4,
+                ///  core_x_dram0_pms_constrain_sram_world_1_pms_0
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_1_pms_1
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_1_pms_2
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
+                ///  core_x_dram0_pms_constrain_sram_world_1_pms_3
+                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
+                reserved24: u4,
+                ///  core_x_dram0_pms_constrain_rom_world_0_pms
+                CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u2,
+                ///  core_x_dram0_pms_constrain_rom_world_1_pms
+                CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u2,
+                padding: u4,
+            }),
+            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
+            CORE_0_DRAM0_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  core_0_dram0_pms_monitor_lock
+                CORE_0_DRAM0_PMS_MONITOR_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
+            CORE_0_DRAM0_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  core_0_dram0_pms_monitor_violate_clr
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
+                ///  core_0_dram0_pms_monitor_violate_en
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
+            CORE_0_DRAM0_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  core_0_dram0_pms_monitor_violate_intr
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
+                ///  core_0_dram0_pms_monitor_violate_status_lock
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK: u1,
+                ///  core_0_dram0_pms_monitor_violate_status_world
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
+                ///  core_0_dram0_pms_monitor_violate_status_addr
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
+                padding: u4,
+            }),
+            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
+            CORE_0_DRAM0_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
+                ///  core_0_dram0_pms_monitor_violate_status_wr
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
+                ///  core_0_dram0_pms_monitor_violate_status_byteen
+                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
+                padding: u27,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
+            CORE_0_PIF_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_lock
+                CORE_0_PIF_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
+            CORE_0_PIF_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_0_uart
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART: u2,
+                ///  core_0_pif_pms_constrain_world_0_g0spi_1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1: u2,
+                ///  core_0_pif_pms_constrain_world_0_g0spi_0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0: u2,
+                ///  core_0_pif_pms_constrain_world_0_gpio
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO: u2,
+                ///  core_0_pif_pms_constrain_world_0_fe2
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2: u2,
+                ///  core_0_pif_pms_constrain_world_0_fe
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE: u2,
+                ///  core_0_pif_pms_constrain_world_0_timer
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER: u2,
+                ///  core_0_pif_pms_constrain_world_0_rtc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC: u2,
+                ///  core_0_pif_pms_constrain_world_0_io_mux
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX: u2,
+                ///  core_0_pif_pms_constrain_world_0_wdg
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG: u2,
+                reserved24: u4,
+                ///  core_0_pif_pms_constrain_world_0_misc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC: u2,
+                ///  core_0_pif_pms_constrain_world_0_i2c
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C: u2,
+                reserved30: u2,
+                ///  core_0_pif_pms_constrain_world_0_uart1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
+            CORE_0_PIF_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_0_bt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT: u2,
+                reserved4: u2,
+                ///  core_0_pif_pms_constrain_world_0_i2c_ext0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0: u2,
+                ///  core_0_pif_pms_constrain_world_0_uhci0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0: u2,
+                reserved10: u2,
+                ///  core_0_pif_pms_constrain_world_0_rmt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT: u2,
+                reserved16: u4,
+                ///  core_0_pif_pms_constrain_world_0_ledc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC: u2,
+                reserved22: u4,
+                ///  core_0_pif_pms_constrain_world_0_bb
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB: u2,
+                reserved26: u2,
+                ///  core_0_pif_pms_constrain_world_0_timergroup
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP: u2,
+                ///  core_0_pif_pms_constrain_world_0_timergroup1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1: u2,
+                ///  core_0_pif_pms_constrain_world_0_systimer
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
+            CORE_0_PIF_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_0_spi_2
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2: u2,
+                reserved4: u2,
+                ///  core_0_pif_pms_constrain_world_0_apb_ctrl
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL: u2,
+                reserved10: u4,
+                ///  core_0_pif_pms_constrain_world_0_can
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN: u2,
+                reserved14: u2,
+                ///  core_0_pif_pms_constrain_world_0_i2s1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1: u2,
+                reserved22: u6,
+                ///  core_0_pif_pms_constrain_world_0_rwbt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT: u2,
+                reserved26: u2,
+                ///  core_0_pif_pms_constrain_world_0_wifimac
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC: u2,
+                ///  core_0_pif_pms_constrain_world_0_pwr
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR: u2,
+                padding: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
+            CORE_0_PIF_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  core_0_pif_pms_constrain_world_0_usb_wrap
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP: u2,
+                ///  core_0_pif_pms_constrain_world_0_crypto_peri
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI: u2,
+                ///  core_0_pif_pms_constrain_world_0_crypto_dma
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA: u2,
+                ///  core_0_pif_pms_constrain_world_0_apb_adc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC: u2,
+                reserved12: u2,
+                ///  core_0_pif_pms_constrain_world_0_bt_pwr
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR: u2,
+                ///  core_0_pif_pms_constrain_world_0_usb_device
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE: u2,
+                ///  core_0_pif_pms_constrain_world_0_system
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM: u2,
+                ///  core_0_pif_pms_constrain_world_0_sensitive
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE: u2,
+                ///  core_0_pif_pms_constrain_world_0_interrupt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT: u2,
+                ///  core_0_pif_pms_constrain_world_0_dma_copy
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY: u2,
+                ///  core_0_pif_pms_constrain_world_0_cache_config
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG: u2,
+                ///  core_0_pif_pms_constrain_world_0_ad
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD: u2,
+                ///  core_0_pif_pms_constrain_world_0_dio
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO: u2,
+                ///  core_0_pif_pms_constrain_world_0_world_controller
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
+            CORE_0_PIF_PMS_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_1_uart
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART: u2,
+                ///  core_0_pif_pms_constrain_world_1_g0spi_1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1: u2,
+                ///  core_0_pif_pms_constrain_world_1_g0spi_0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0: u2,
+                ///  core_0_pif_pms_constrain_world_1_gpio
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO: u2,
+                ///  core_0_pif_pms_constrain_world_1_fe2
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2: u2,
+                ///  core_0_pif_pms_constrain_world_1_fe
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE: u2,
+                ///  core_0_pif_pms_constrain_world_1_timer
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER: u2,
+                ///  core_0_pif_pms_constrain_world_1_rtc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC: u2,
+                ///  core_0_pif_pms_constrain_world_1_io_mux
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX: u2,
+                ///  core_0_pif_pms_constrain_world_1_wdg
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG: u2,
+                reserved24: u4,
+                ///  core_0_pif_pms_constrain_world_1_misc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC: u2,
+                ///  core_0_pif_pms_constrain_world_1_i2c
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C: u2,
+                reserved30: u2,
+                ///  core_0_pif_pms_constrain_world_1_uart1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
+            CORE_0_PIF_PMS_CONSTRAIN_6: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_1_bt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT: u2,
+                reserved4: u2,
+                ///  core_0_pif_pms_constrain_world_1_i2c_ext0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0: u2,
+                ///  core_0_pif_pms_constrain_world_1_uhci0
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0: u2,
+                reserved10: u2,
+                ///  core_0_pif_pms_constrain_world_1_rmt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT: u2,
+                reserved16: u4,
+                ///  core_0_pif_pms_constrain_world_1_ledc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC: u2,
+                reserved22: u4,
+                ///  core_0_pif_pms_constrain_world_1_bb
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB: u2,
+                reserved26: u2,
+                ///  core_0_pif_pms_constrain_world_1_timergroup
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP: u2,
+                ///  core_0_pif_pms_constrain_world_1_timergroup1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1: u2,
+                ///  core_0_pif_pms_constrain_world_1_systimer
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
+            CORE_0_PIF_PMS_CONSTRAIN_7: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_world_1_spi_2
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2: u2,
+                reserved4: u2,
+                ///  core_0_pif_pms_constrain_world_1_apb_ctrl
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL: u2,
+                reserved10: u4,
+                ///  core_0_pif_pms_constrain_world_1_can
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN: u2,
+                reserved14: u2,
+                ///  core_0_pif_pms_constrain_world_1_i2s1
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1: u2,
+                reserved22: u6,
+                ///  core_0_pif_pms_constrain_world_1_rwbt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT: u2,
+                reserved26: u2,
+                ///  core_0_pif_pms_constrain_world_1_wifimac
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC: u2,
+                ///  core_0_pif_pms_constrain_world_1_pwr
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR: u2,
+                padding: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
+            CORE_0_PIF_PMS_CONSTRAIN_8: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  core_0_pif_pms_constrain_world_1_usb_wrap
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP: u2,
+                ///  core_0_pif_pms_constrain_world_1_crypto_peri
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI: u2,
+                ///  core_0_pif_pms_constrain_world_1_crypto_dma
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA: u2,
+                ///  core_0_pif_pms_constrain_world_1_apb_adc
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC: u2,
+                reserved12: u2,
+                ///  core_0_pif_pms_constrain_world_1_bt_pwr
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR: u2,
+                ///  core_0_pif_pms_constrain_world_1_usb_device
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE: u2,
+                ///  core_0_pif_pms_constrain_world_1_system
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM: u2,
+                ///  core_0_pif_pms_constrain_world_1_sensitive
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE: u2,
+                ///  core_0_pif_pms_constrain_world_1_interrupt
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT: u2,
+                ///  core_0_pif_pms_constrain_world_1_dma_copy
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY: u2,
+                ///  core_0_pif_pms_constrain_world_1_cache_config
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG: u2,
+                ///  core_0_pif_pms_constrain_world_1_ad
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD: u2,
+                ///  core_0_pif_pms_constrain_world_1_dio
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO: u2,
+                ///  core_0_pif_pms_constrain_world_1_world_controller
+                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
+            CORE_0_PIF_PMS_CONSTRAIN_9: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_rtcfast_spltaddr_world_0
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0: u11,
+                ///  core_0_pif_pms_constrain_rtcfast_spltaddr_world_1
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1: u11,
+                padding: u10,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
+            CORE_0_PIF_PMS_CONSTRAIN_10: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_constrain_rtcfast_world_0_l
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L: u3,
+                ///  core_0_pif_pms_constrain_rtcfast_world_0_h
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H: u3,
+                ///  core_0_pif_pms_constrain_rtcfast_world_1_l
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L: u3,
+                ///  core_0_pif_pms_constrain_rtcfast_world_1_h
+                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H: u3,
+                padding: u20,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
+            REGION_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_lock
+                REGION_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
+            REGION_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_world_0_area_0
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_0: u2,
+                ///  region_pms_constrain_world_0_area_1
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_1: u2,
+                ///  region_pms_constrain_world_0_area_2
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_2: u2,
+                ///  region_pms_constrain_world_0_area_3
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_3: u2,
+                ///  region_pms_constrain_world_0_area_4
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_4: u2,
+                ///  region_pms_constrain_world_0_area_5
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_5: u2,
+                ///  region_pms_constrain_world_0_area_6
+                REGION_PMS_CONSTRAIN_WORLD_0_AREA_6: u2,
+                padding: u18,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
+            REGION_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_world_1_area_0
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_0: u2,
+                ///  region_pms_constrain_world_1_area_1
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_1: u2,
+                ///  region_pms_constrain_world_1_area_2
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_2: u2,
+                ///  region_pms_constrain_world_1_area_3
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_3: u2,
+                ///  region_pms_constrain_world_1_area_4
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_4: u2,
+                ///  region_pms_constrain_world_1_area_5
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_5: u2,
+                ///  region_pms_constrain_world_1_area_6
+                REGION_PMS_CONSTRAIN_WORLD_1_AREA_6: u2,
+                padding: u18,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
+            REGION_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_0
+                REGION_PMS_CONSTRAIN_ADDR_0: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
+            REGION_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_1
+                REGION_PMS_CONSTRAIN_ADDR_1: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
+            REGION_PMS_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_2
+                REGION_PMS_CONSTRAIN_ADDR_2: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
+            REGION_PMS_CONSTRAIN_6: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_3
+                REGION_PMS_CONSTRAIN_ADDR_3: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
+            REGION_PMS_CONSTRAIN_7: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_4
+                REGION_PMS_CONSTRAIN_ADDR_4: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
+            REGION_PMS_CONSTRAIN_8: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_5
+                REGION_PMS_CONSTRAIN_ADDR_5: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
+            REGION_PMS_CONSTRAIN_9: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_6
+                REGION_PMS_CONSTRAIN_ADDR_6: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
+            REGION_PMS_CONSTRAIN_10: mmio.Mmio(packed struct(u32) {
+                ///  region_pms_constrain_addr_7
+                REGION_PMS_CONSTRAIN_ADDR_7: u30,
+                padding: u2,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
+            CORE_0_PIF_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_lock
+                CORE_0_PIF_PMS_MONITOR_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
+            CORE_0_PIF_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_violate_clr
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR: u1,
+                ///  core_0_pif_pms_monitor_violate_en
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
+            CORE_0_PIF_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_violate_intr
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR: u1,
+                ///  core_0_pif_pms_monitor_violate_status_hport_0
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0: u1,
+                ///  core_0_pif_pms_monitor_violate_status_hsize
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
+                ///  core_0_pif_pms_monitor_violate_status_hwrite
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
+                ///  core_0_pif_pms_monitor_violate_status_hworld
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD: u2,
+                padding: u24,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
+            CORE_0_PIF_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_violate_status_haddr
+                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR: u32,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
+            CORE_0_PIF_PMS_MONITOR_4: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_nonword_violate_clr
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR: u1,
+                ///  core_0_pif_pms_monitor_nonword_violate_en
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
+            CORE_0_PIF_PMS_MONITOR_5: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_nonword_violate_intr
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR: u1,
+                ///  core_0_pif_pms_monitor_nonword_violate_status_hsize
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE: u2,
+                ///  core_0_pif_pms_monitor_nonword_violate_status_hworld
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD: u2,
+                padding: u27,
+            }),
+            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
+            CORE_0_PIF_PMS_MONITOR_6: mmio.Mmio(packed struct(u32) {
+                ///  core_0_pif_pms_monitor_nonword_violate_status_haddr
+                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR: u32,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
+            BACKUP_BUS_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_constrain_lock
+                BACKUP_BUS_PMS_CONSTRAIN_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
+            BACKUP_BUS_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_constrain_uart
+                BACKUP_BUS_PMS_CONSTRAIN_UART: u2,
+                ///  backup_bus_pms_constrain_g0spi_1
+                BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1: u2,
+                ///  backup_bus_pms_constrain_g0spi_0
+                BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0: u2,
+                ///  backup_bus_pms_constrain_gpio
+                BACKUP_BUS_PMS_CONSTRAIN_GPIO: u2,
+                ///  backup_bus_pms_constrain_fe2
+                BACKUP_BUS_PMS_CONSTRAIN_FE2: u2,
+                ///  backup_bus_pms_constrain_fe
+                BACKUP_BUS_PMS_CONSTRAIN_FE: u2,
+                ///  backup_bus_pms_constrain_timer
+                BACKUP_BUS_PMS_CONSTRAIN_TIMER: u2,
+                ///  backup_bus_pms_constrain_rtc
+                BACKUP_BUS_PMS_CONSTRAIN_RTC: u2,
+                ///  backup_bus_pms_constrain_io_mux
+                BACKUP_BUS_PMS_CONSTRAIN_IO_MUX: u2,
+                ///  backup_bus_pms_constrain_wdg
+                BACKUP_BUS_PMS_CONSTRAIN_WDG: u2,
+                reserved24: u4,
+                ///  backup_bus_pms_constrain_misc
+                BACKUP_BUS_PMS_CONSTRAIN_MISC: u2,
+                ///  backup_bus_pms_constrain_i2c
+                BACKUP_BUS_PMS_CONSTRAIN_I2C: u2,
+                reserved30: u2,
+                ///  backup_bus_pms_constrain_uart1
+                BACKUP_BUS_PMS_CONSTRAIN_UART1: u2,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
+            BACKUP_BUS_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_constrain_bt
+                BACKUP_BUS_PMS_CONSTRAIN_BT: u2,
+                reserved4: u2,
+                ///  backup_bus_pms_constrain_i2c_ext0
+                BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0: u2,
+                ///  backup_bus_pms_constrain_uhci0
+                BACKUP_BUS_PMS_CONSTRAIN_UHCI0: u2,
+                reserved10: u2,
+                ///  backup_bus_pms_constrain_rmt
+                BACKUP_BUS_PMS_CONSTRAIN_RMT: u2,
+                reserved16: u4,
+                ///  backup_bus_pms_constrain_ledc
+                BACKUP_BUS_PMS_CONSTRAIN_LEDC: u2,
+                reserved22: u4,
+                ///  backup_bus_pms_constrain_bb
+                BACKUP_BUS_PMS_CONSTRAIN_BB: u2,
+                reserved26: u2,
+                ///  backup_bus_pms_constrain_timergroup
+                BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP: u2,
+                ///  backup_bus_pms_constrain_timergroup1
+                BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1: u2,
+                ///  backup_bus_pms_constrain_systimer
+                BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER: u2,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
+            BACKUP_BUS_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_constrain_spi_2
+                BACKUP_BUS_PMS_CONSTRAIN_SPI_2: u2,
+                reserved4: u2,
+                ///  backup_bus_pms_constrain_apb_ctrl
+                BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL: u2,
+                reserved10: u4,
+                ///  backup_bus_pms_constrain_can
+                BACKUP_BUS_PMS_CONSTRAIN_CAN: u2,
+                reserved14: u2,
+                ///  backup_bus_pms_constrain_i2s1
+                BACKUP_BUS_PMS_CONSTRAIN_I2S1: u2,
+                reserved22: u6,
+                ///  backup_bus_pms_constrain_rwbt
+                BACKUP_BUS_PMS_CONSTRAIN_RWBT: u2,
+                reserved26: u2,
+                ///  backup_bus_pms_constrain_wifimac
+                BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC: u2,
+                ///  backup_bus_pms_constrain_pwr
+                BACKUP_BUS_PMS_CONSTRAIN_PWR: u2,
+                padding: u2,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
+            BACKUP_BUS_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
+                reserved2: u2,
+                ///  backup_bus_pms_constrain_usb_wrap
+                BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP: u2,
+                ///  backup_bus_pms_constrain_crypto_peri
+                BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI: u2,
+                ///  backup_bus_pms_constrain_crypto_dma
+                BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA: u2,
+                ///  backup_bus_pms_constrain_apb_adc
+                BACKUP_BUS_PMS_CONSTRAIN_APB_ADC: u2,
+                reserved12: u2,
+                ///  backup_bus_pms_constrain_bt_pwr
+                BACKUP_BUS_PMS_CONSTRAIN_BT_PWR: u2,
+                ///  backup_bus_pms_constrain_usb_device
+                BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE: u2,
+                padding: u16,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
+            BACKUP_BUS_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_monitor_lock
+                BACKUP_BUS_PMS_MONITOR_LOCK: u1,
+                padding: u31,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
+            BACKUP_BUS_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_monitor_violate_clr
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR: u1,
+                ///  backup_bus_pms_monitor_violate_en
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_EN: u1,
+                padding: u30,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
+            BACKUP_BUS_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_monitor_violate_intr
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR: u1,
+                ///  backup_bus_pms_monitor_violate_status_htrans
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS: u2,
+                ///  backup_bus_pms_monitor_violate_status_hsize
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
+                ///  backup_bus_pms_monitor_violate_status_hwrite
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
+                padding: u25,
+            }),
+            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
+            BACKUP_BUS_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
+                ///  backup_bus_pms_monitor_violate_haddr
+                BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR: u32,
+            }),
+            ///  SENSITIVE_CLOCK_GATE_REG
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  clk_en
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            reserved4092: [3720]u8,
+            ///  SENSITIVE_DATE_REG
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_date
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  SHA (Secure Hash Algorithm) Accelerator
+        pub const SHA = extern struct {
+            ///  Initial configuration register.
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  Sha mode.
+                MODE: u3,
+                padding: u29,
+            }),
+            ///  SHA 512/t configuration register 0.
+            T_STRING: mmio.Mmio(packed struct(u32) {
+                ///  Sha t_string (used if and only if mode == SHA_512/t).
+                T_STRING: u32,
+            }),
+            ///  SHA 512/t configuration register 1.
+            T_LENGTH: mmio.Mmio(packed struct(u32) {
+                ///  Sha t_length (used if and only if mode == SHA_512/t).
+                T_LENGTH: u6,
+                padding: u26,
+            }),
+            ///  DMA configuration register 0.
+            DMA_BLOCK_NUM: mmio.Mmio(packed struct(u32) {
+                ///  Dma-sha block number.
+                DMA_BLOCK_NUM: u6,
+                padding: u26,
+            }),
+            ///  Typical SHA configuration register 0.
+            START: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Reserved.
+                START: u31,
+            }),
+            ///  Typical SHA configuration register 1.
+            CONTINUE: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  Reserved.
+                CONTINUE: u31,
+            }),
+            ///  Busy register.
+            BUSY: mmio.Mmio(packed struct(u32) {
+                ///  Sha busy state. 1'b0: idle. 1'b1: busy.
+                STATE: u1,
+                padding: u31,
+            }),
+            ///  DMA configuration register 1.
+            DMA_START: mmio.Mmio(packed struct(u32) {
+                ///  Start dma-sha.
+                DMA_START: u1,
+                padding: u31,
+            }),
+            ///  DMA configuration register 2.
+            DMA_CONTINUE: mmio.Mmio(packed struct(u32) {
+                ///  Continue dma-sha.
+                DMA_CONTINUE: u1,
+                padding: u31,
+            }),
+            ///  Interrupt clear register.
+            CLEAR_IRQ: mmio.Mmio(packed struct(u32) {
+                ///  Clear sha interrupt.
+                CLEAR_INTERRUPT: u1,
+                padding: u31,
+            }),
+            ///  Interrupt enable register.
+            IRQ_ENA: mmio.Mmio(packed struct(u32) {
+                ///  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
+                INTERRUPT_ENA: u1,
+                padding: u31,
+            }),
+            ///  Date register.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  Sha date information/ sha version information.
+                DATE: u30,
+                padding: u2,
+            }),
+            reserved64: [16]u8,
+            ///  Sha H memory which contains intermediate hash or finial hash.
+            H_MEM: [64]u8,
+            ///  Sha M memory which contains message.
+            M_MEM: [64]u8,
+        };
+
+        ///  SPI (Serial Peripheral Interface) Controller
+        pub const SPI0 = extern struct {
+            reserved8: [8]u8,
+            ///  SPI0 control register.
+            CTRL: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                ///  In the dummy phase the signal level of spi is output by the spi controller.
+                FDUMMY_OUT: u1,
+                reserved7: u3,
+                ///  Apply 2 signals during command phase 1:enable 0: disable
+                FCMD_DUAL: u1,
+                ///  Apply 4 signals during command phase 1:enable 0: disable
+                FCMD_QUAD: u1,
+                reserved13: u4,
+                ///  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+                FASTRD_MODE: u1,
+                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+                FREAD_DUAL: u1,
+                reserved18: u3,
+                ///  The bit is used to set MISO line polarity, 1: high 0, low
+                Q_POL: u1,
+                ///  The bit is used to set MOSI line polarity, 1: high 0, low
+                D_POL: u1,
+                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+                FREAD_QUAD: u1,
+                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low.
+                WP: u1,
+                reserved23: u1,
+                ///  In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
+                FREAD_DIO: u1,
+                ///  In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
+                FREAD_QIO: u1,
+                padding: u7,
+            }),
+            ///  SPI0 control1 register.
+            CTRL1: mmio.Mmio(packed struct(u32) {
+                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
+                CLK_MODE: u2,
+                reserved30: u28,
+                ///  SPI0 RX FIFO reset signal.
+                RXFIFO_RST: u1,
+                padding: u1,
+            }),
+            ///  SPI0 control2 register.
+            CTRL2: mmio.Mmio(packed struct(u32) {
+                ///  (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.
+                CS_SETUP_TIME: u5,
+                ///  Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.
+                CS_HOLD_TIME: u5,
+                reserved25: u15,
+                ///  These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.
+                CS_HOLD_DELAY: u6,
+                ///  The FSM will be reset.
+                SYNC_RESET: u1,
+            }),
+            ///  SPI clock division control register.
+            CLOCK: mmio.Mmio(packed struct(u32) {
+                ///  In the master mode it must be equal to spi_mem_clkcnt_N.
+                CLKCNT_L: u8,
+                ///  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+                CLKCNT_H: u8,
+                ///  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
+                CLKCNT_N: u8,
+                reserved31: u7,
+                ///  Set this bit in 1-division mode.
+                CLK_EQU_SYSCLK: u1,
+            }),
+            ///  SPI0 user register.
+            USER: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  spi cs keep low when spi is in done phase. 1: enable 0: disable.
+                CS_HOLD: u1,
+                ///  spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
+                CS_SETUP: u1,
+                reserved9: u1,
+                ///  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+                CK_OUT_EDGE: u1,
+                reserved26: u16,
+                ///  spi clock is disable in dummy phase when the bit is enable.
+                USR_DUMMY_IDLE: u1,
+                reserved29: u2,
+                ///  This bit enable the dummy phase of an operation.
+                USR_DUMMY: u1,
+                padding: u2,
+            }),
+            ///  SPI0 user1 register.
+            USER1: mmio.Mmio(packed struct(u32) {
+                ///  The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
+                USR_DUMMY_CYCLELEN: u6,
+                reserved26: u20,
+                ///  The length in bits of address phase. The register value shall be (bit_num-1).
+                USR_ADDR_BITLEN: u6,
+            }),
+            ///  SPI0 user2 register.
+            USER2: mmio.Mmio(packed struct(u32) {
+                ///  The value of command.
+                USR_COMMAND_VALUE: u16,
+                reserved28: u12,
+                ///  The length in bits of command phase. The register value shall be (bit_num-1)
+                USR_COMMAND_BITLEN: u4,
+            }),
+            reserved44: [8]u8,
+            ///  SPI0 read control register.
+            RD_STATUS: mmio.Mmio(packed struct(u32) {
+                reserved16: u16,
+                ///  Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
+                WB_MODE: u8,
+                padding: u8,
+            }),
+            reserved52: [4]u8,
+            ///  SPI0 misc register
+            MISC: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                ///  The bit is used to indicate the spi0_mst_st controlled transmitting is done.
+                TRANS_END: u1,
+                ///  The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done.
+                TRANS_END_INT_ENA: u1,
+                ///  The bit is used to indicate the spi0_slv_st controlled transmitting is done.
+                CSPI_ST_TRANS_END: u1,
+                ///  The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.
+                CSPI_ST_TRANS_END_INT_ENA: u1,
+                reserved9: u2,
+                ///  1: spi clk line is high when idle 0: spi clk line is low when idle
+                CK_IDLE_EDGE: u1,
+                ///  spi cs line keep low when the bit is set.
+                CS_KEEP_ACTIVE: u1,
+                padding: u21,
+            }),
+            reserved60: [4]u8,
+            ///  SPI0 bit mode control register.
+            CACHE_FCTRL: mmio.Mmio(packed struct(u32) {
+                ///  For SPI0, Cache access enable, 1: enable, 0:disable.
+                CACHE_REQ_EN: u1,
+                ///  For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
+                CACHE_USR_ADDR_4BYTE: u1,
+                ///  For SPI0, cache read flash for user define command, 1: enable, 0:disable.
+                CACHE_FLASH_USR_CMD: u1,
+                ///  For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FDIN_DUAL: u1,
+                ///  For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FDOUT_DUAL: u1,
+                ///  For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FADDR_DUAL: u1,
+                ///  For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FDIN_QUAD: u1,
+                ///  For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FDOUT_QUAD: u1,
+                ///  For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FADDR_QUAD: u1,
+                padding: u23,
+            }),
+            reserved84: [20]u8,
+            ///  SPI0 FSM status register
+            FSM: mmio.Mmio(packed struct(u32) {
+                ///  The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
+                CSPI_ST: u4,
+                ///  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
+                EM_ST: u3,
+                ///  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
+                CSPI_LOCK_DELAY_TIME: u5,
+                padding: u20,
+            }),
+            reserved168: [80]u8,
+            ///  SPI0 timing calibration register
+            TIMING_CALI: mmio.Mmio(packed struct(u32) {
+                ///  The bit is used to enable timing adjust clock for all reading operations.
+                TIMING_CLK_ENA: u1,
+                ///  The bit is used to enable timing auto-calibration for all reading operations.
+                TIMING_CALI: u1,
+                ///  add extra dummy spi clock cycle length for spi clock calibration.
+                EXTRA_DUMMY_CYCLELEN: u3,
+                padding: u27,
+            }),
+            ///  SPI0 input delay mode control register
+            DIN_MODE: mmio.Mmio(packed struct(u32) {
+                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
+                DIN0_MODE: u2,
+                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
+                DIN1_MODE: u2,
+                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
+                DIN2_MODE: u2,
+                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
+                DIN3_MODE: u2,
+                padding: u24,
+            }),
+            ///  SPI0 input delay number control register
+            DIN_NUM: mmio.Mmio(packed struct(u32) {
+                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+                DIN0_NUM: u2,
+                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+                DIN1_NUM: u2,
+                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+                DIN2_NUM: u2,
+                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
+                DIN3_NUM: u2,
+                padding: u24,
+            }),
+            ///  SPI0 output delay mode control register
+            DOUT_MODE: mmio.Mmio(packed struct(u32) {
+                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+                DOUT0_MODE: u1,
+                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+                DOUT1_MODE: u1,
+                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+                DOUT2_MODE: u1,
+                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
+                DOUT3_MODE: u1,
+                padding: u28,
+            }),
+            reserved220: [36]u8,
+            ///  SPI0 clk_gate register
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  Register clock gate enable signal. 1: Enable. 0: Disable.
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            ///  SPI0 module clock select register
+            CORE_CLK_SEL: mmio.Mmio(packed struct(u32) {
+                ///  When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.
+                SPI01_CLK_SEL: u2,
+                padding: u30,
+            }),
+            reserved1020: [792]u8,
+            ///  Version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  SPI register version.
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  SPI (Serial Peripheral Interface) Controller
+        pub const SPI1 = extern struct {
+            ///  SPI1 memory command register
+            CMD: mmio.Mmio(packed struct(u32) {
+                ///  The current status of SPI1 master FSM.
+                SPI1_MST_ST: u4,
+                ///  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
+                MSPI_ST: u4,
+                reserved17: u9,
+                ///  In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_PE: u1,
+                ///  User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                USR: u1,
+                ///  Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_HPM: u1,
+                ///  This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_RES: u1,
+                ///  Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_DP: u1,
+                ///  Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_CE: u1,
+                ///  Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_BE: u1,
+                ///  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_SE: u1,
+                ///  Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.
+                FLASH_PP: u1,
+                ///  Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_WRSR: u1,
+                ///  Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_RDSR: u1,
+                ///  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+                FLASH_RDID: u1,
+                ///  Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+                FLASH_WRDI: u1,
+                ///  Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+                FLASH_WREN: u1,
+                ///  Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
+                FLASH_READ: u1,
+            }),
+            ///  SPI1 address register
+            ADDR: mmio.Mmio(packed struct(u32) {
+                ///  In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.
+                USR_ADDR_VALUE: u32,
+            }),
+            ///  SPI1 control register.
+            CTRL: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                ///  In the dummy phase the signal level of spi is output by the spi controller.
+                FDUMMY_OUT: u1,
+                reserved7: u3,
+                ///  Apply 2 signals during command phase 1:enable 0: disable
+                FCMD_DUAL: u1,
+                ///  Apply 4 signals during command phase 1:enable 0: disable
+                FCMD_QUAD: u1,
+                reserved10: u1,
+                ///  For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.
+                FCS_CRC_EN: u1,
+                ///  For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
+                TX_CRC_EN: u1,
+                reserved13: u1,
+                ///  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
+                FASTRD_MODE: u1,
+                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
+                FREAD_DUAL: u1,
+                ///  The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
+                RESANDRES: u1,
+                reserved18: u2,
+                ///  The bit is used to set MISO line polarity, 1: high 0, low
+                Q_POL: u1,
+                ///  The bit is used to set MOSI line polarity, 1: high 0, low
+                D_POL: u1,
+                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
+                FREAD_QUAD: u1,
+                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low.
+                WP: u1,
+                ///  two bytes data will be written to status register when it is set. 1: enable 0: disable.
+                WRSR_2B: u1,
+                ///  In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
+                FREAD_DIO: u1,
+                ///  In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
+                FREAD_QIO: u1,
+                padding: u7,
+            }),
+            ///  SPI1 control1 register.
+            CTRL1: mmio.Mmio(packed struct(u32) {
+                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
+                CLK_MODE: u2,
+                ///  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.
+                CS_HOLD_DLY_RES: u10,
+                padding: u20,
+            }),
+            ///  SPI1 control2 register.
+            CTRL2: mmio.Mmio(packed struct(u32) {
+                reserved31: u31,
+                ///  The FSM will be reset.
+                SYNC_RESET: u1,
+            }),
+            ///  SPI1 clock division control register.
+            CLOCK: mmio.Mmio(packed struct(u32) {
+                ///  In the master mode it must be equal to spi_mem_clkcnt_N.
+                CLKCNT_L: u8,
+                ///  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
+                CLKCNT_H: u8,
+                ///  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
+                CLKCNT_N: u8,
+                reserved31: u7,
+                ///  reserved
+                CLK_EQU_SYSCLK: u1,
+            }),
+            ///  SPI1 user register.
+            USER: mmio.Mmio(packed struct(u32) {
+                reserved9: u9,
+                ///  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
+                CK_OUT_EDGE: u1,
+                reserved12: u2,
+                ///  In the write operations read-data phase apply 2 signals
+                FWRITE_DUAL: u1,
+                ///  In the write operations read-data phase apply 4 signals
+                FWRITE_QUAD: u1,
+                ///  In the write operations address phase and read-data phase apply 2 signals.
+                FWRITE_DIO: u1,
+                ///  In the write operations address phase and read-data phase apply 4 signals.
+                FWRITE_QIO: u1,
+                reserved24: u8,
+                ///  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
+                USR_MISO_HIGHPART: u1,
+                ///  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
+                USR_MOSI_HIGHPART: u1,
+                ///  SPI clock is disable in dummy phase when the bit is enable.
+                USR_DUMMY_IDLE: u1,
+                ///  This bit enable the write-data phase of an operation.
+                USR_MOSI: u1,
+                ///  This bit enable the read-data phase of an operation.
+                USR_MISO: u1,
+                ///  This bit enable the dummy phase of an operation.
+                USR_DUMMY: u1,
+                ///  This bit enable the address phase of an operation.
+                USR_ADDR: u1,
+                ///  This bit enable the command phase of an operation.
+                USR_COMMAND: u1,
+            }),
+            ///  SPI1 user1 register.
+            USER1: mmio.Mmio(packed struct(u32) {
+                ///  The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
+                USR_DUMMY_CYCLELEN: u6,
+                reserved26: u20,
+                ///  The length in bits of address phase. The register value shall be (bit_num-1).
+                USR_ADDR_BITLEN: u6,
+            }),
+            ///  SPI1 user2 register.
+            USER2: mmio.Mmio(packed struct(u32) {
+                ///  The value of command.
+                USR_COMMAND_VALUE: u16,
+                reserved28: u12,
+                ///  The length in bits of command phase. The register value shall be (bit_num-1)
+                USR_COMMAND_BITLEN: u4,
+            }),
+            ///  SPI1 send data bit length control register.
+            MOSI_DLEN: mmio.Mmio(packed struct(u32) {
+                ///  The length in bits of write-data. The register value shall be (bit_num-1).
+                USR_MOSI_DBITLEN: u10,
+                padding: u22,
+            }),
+            ///  SPI1 receive data bit length control register.
+            MISO_DLEN: mmio.Mmio(packed struct(u32) {
+                ///  The length in bits of read-data. The register value shall be (bit_num-1).
+                USR_MISO_DBITLEN: u10,
+                padding: u22,
+            }),
+            ///  SPI1 status register.
+            RD_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
+                STATUS: u16,
+                ///  Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
+                WB_MODE: u8,
+                padding: u8,
+            }),
+            reserved52: [4]u8,
+            ///  SPI1 misc register
+            MISC: mmio.Mmio(packed struct(u32) {
+                ///  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.
+                CS0_DIS: u1,
+                ///  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.
+                CS1_DIS: u1,
+                reserved9: u7,
+                ///  1: spi clk line is high when idle 0: spi clk line is low when idle
+                CK_IDLE_EDGE: u1,
+                ///  spi cs line keep low when the bit is set.
+                CS_KEEP_ACTIVE: u1,
+                padding: u21,
+            }),
+            ///  SPI1 TX CRC data register.
+            TX_CRC: mmio.Mmio(packed struct(u32) {
+                ///  For SPI1, the value of crc32.
+                DATA: u32,
+            }),
+            ///  SPI1 bit mode control register.
+            CACHE_FCTRL: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
+                CACHE_USR_ADDR_4BYTE: u1,
+                reserved3: u1,
+                ///  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FDIN_DUAL: u1,
+                ///  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FDOUT_DUAL: u1,
+                ///  For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
+                FADDR_DUAL: u1,
+                ///  For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FDIN_QUAD: u1,
+                ///  For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FDOUT_QUAD: u1,
+                ///  For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
+                FADDR_QUAD: u1,
+                padding: u23,
+            }),
+            reserved88: [24]u8,
+            ///  SPI1 memory data buffer0
+            W0: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF0: u32,
+            }),
+            ///  SPI1 memory data buffer1
+            W1: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF1: u32,
+            }),
+            ///  SPI1 memory data buffer2
+            W2: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF2: u32,
+            }),
+            ///  SPI1 memory data buffer3
+            W3: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF3: u32,
+            }),
+            ///  SPI1 memory data buffer4
+            W4: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF4: u32,
+            }),
+            ///  SPI1 memory data buffer5
+            W5: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF5: u32,
+            }),
+            ///  SPI1 memory data buffer6
+            W6: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF6: u32,
+            }),
+            ///  SPI1 memory data buffer7
+            W7: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF7: u32,
+            }),
+            ///  SPI1 memory data buffer8
+            W8: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF8: u32,
+            }),
+            ///  SPI1 memory data buffer9
+            W9: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF9: u32,
+            }),
+            ///  SPI1 memory data buffer10
+            W10: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF10: u32,
+            }),
+            ///  SPI1 memory data buffer11
+            W11: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF11: u32,
+            }),
+            ///  SPI1 memory data buffer12
+            W12: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF12: u32,
+            }),
+            ///  SPI1 memory data buffer13
+            W13: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF13: u32,
+            }),
+            ///  SPI1 memory data buffer14
+            W14: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF14: u32,
+            }),
+            ///  SPI1 memory data buffer15
+            W15: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF15: u32,
+            }),
+            ///  SPI1 wait idle control register
+            FLASH_WAITI_CTRL: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  The dummy phase enable when wait flash idle (RDSR)
+                WAITI_DUMMY: u1,
+                ///  The command to wait flash idle(RDSR).
+                WAITI_CMD: u8,
+                ///  The dummy cycle length when wait flash idle(RDSR).
+                WAITI_DUMMY_CYCLELEN: u6,
+                padding: u16,
+            }),
+            ///  SPI1 flash suspend control register
+            FLASH_SUS_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_PER: u1,
+                ///  program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
+                FLASH_PES: u1,
+                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.
+                FLASH_PER_WAIT_EN: u1,
+                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.
+                FLASH_PES_WAIT_EN: u1,
+                ///  Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.
+                PES_PER_EN: u1,
+                ///  Set this bit to enable Auto-suspending function.
+                FLASH_PES_EN: u1,
+                ///  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
+                PESR_END_MSK: u16,
+                ///  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit
+                RD_SUS_2B: u1,
+                ///  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.
+                PER_END_EN: u1,
+                ///  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.
+                PES_END_EN: u1,
+                ///  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.
+                SUS_TIMEOUT_CNT: u7,
+            }),
+            ///  SPI1 flash suspend command register
+            FLASH_SUS_CMD: mmio.Mmio(packed struct(u32) {
+                ///  Program/Erase resume command.
+                FLASH_PER_COMMAND: u8,
+                ///  Program/Erase suspend command.
+                FLASH_PES_COMMAND: u8,
+                ///  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
+                WAIT_PESR_COMMAND: u16,
+            }),
+            ///  SPI1 flash suspend status register
+            SUS_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  The status of flash suspend, only used in SPI1.
+                FLASH_SUS: u1,
+                ///  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
+                WAIT_PESR_CMD_2B: u1,
+                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.
+                FLASH_HPM_DLY_128: u1,
+                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.
+                FLASH_RES_DLY_128: u1,
+                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.
+                FLASH_DP_DLY_128: u1,
+                ///  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.
+                FLASH_PER_DLY_128: u1,
+                ///  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.
+                FLASH_PES_DLY_128: u1,
+                ///  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
+                SPI0_LOCK_EN: u1,
+                padding: u24,
+            }),
+            ///  SPI1 timing control register
+            TIMING_CALI: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  The bit is used to enable timing auto-calibration for all reading operations.
+                TIMING_CALI: u1,
+                ///  add extra dummy spi clock cycle length for spi clock calibration.
+                EXTRA_DUMMY_CYCLELEN: u3,
+                padding: u27,
+            }),
+            reserved192: [20]u8,
+            ///  SPI1 interrupt enable register
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The enable bit for SPI_MEM_PER_END_INT interrupt.
+                PER_END_INT_ENA: u1,
+                ///  The enable bit for SPI_MEM_PES_END_INT interrupt.
+                PES_END_INT_ENA: u1,
+                ///  The enable bit for SPI_MEM_WPE_END_INT interrupt.
+                WPE_END_INT_ENA: u1,
+                ///  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
+                SLV_ST_END_INT_ENA: u1,
+                ///  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
+                MST_ST_END_INT_ENA: u1,
+                padding: u27,
+            }),
+            ///  SPI1 interrupt clear register
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The clear bit for SPI_MEM_PER_END_INT interrupt.
+                PER_END_INT_CLR: u1,
+                ///  The clear bit for SPI_MEM_PES_END_INT interrupt.
+                PES_END_INT_CLR: u1,
+                ///  The clear bit for SPI_MEM_WPE_END_INT interrupt.
+                WPE_END_INT_CLR: u1,
+                ///  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
+                SLV_ST_END_INT_CLR: u1,
+                ///  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
+                MST_ST_END_INT_CLR: u1,
+                padding: u27,
+            }),
+            ///  SPI1 interrupt raw register
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.
+                PER_END_INT_RAW: u1,
+                ///  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.
+                PES_END_INT_RAW: u1,
+                ///  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
+                WPE_END_INT_RAW: u1,
+                ///  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others
+                SLV_ST_END_INT_RAW: u1,
+                ///  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.
+                MST_ST_END_INT_RAW: u1,
+                padding: u27,
+            }),
+            ///  SPI1 interrupt status register
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The status bit for SPI_MEM_PER_END_INT interrupt.
+                PER_END_INT_ST: u1,
+                ///  The status bit for SPI_MEM_PES_END_INT interrupt.
+                PES_END_INT_ST: u1,
+                ///  The status bit for SPI_MEM_WPE_END_INT interrupt.
+                WPE_END_INT_ST: u1,
+                ///  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
+                SLV_ST_END_INT_ST: u1,
+                ///  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
+                MST_ST_END_INT_ST: u1,
+                padding: u27,
+            }),
+            reserved220: [12]u8,
+            ///  SPI1 clk_gate register
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  Register clock gate enable signal. 1: Enable. 0: Disable.
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            reserved1020: [796]u8,
+            ///  Version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  Version control register
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  SPI (Serial Peripheral Interface) Controller
+        pub const SPI2 = extern struct {
+            ///  Command control register
+            CMD: mmio.Mmio(packed struct(u32) {
+                ///  Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
+                CONF_BITLEN: u18,
+                reserved23: u5,
+                ///  Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.
+                UPDATE: u1,
+                ///  User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.
+                USR: u1,
+                padding: u7,
+            }),
+            ///  Address value register
+            ADDR: mmio.Mmio(packed struct(u32) {
+                ///  Address to slave. Can be configured in CONF state.
+                USR_ADDR_VALUE: u32,
+            }),
+            ///  SPI control register
+            CTRL: mmio.Mmio(packed struct(u32) {
+                reserved3: u3,
+                ///  In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.
+                DUMMY_OUT: u1,
+                reserved5: u1,
+                ///  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
+                FADDR_DUAL: u1,
+                ///  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
+                FADDR_QUAD: u1,
+                reserved8: u1,
+                ///  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
+                FCMD_DUAL: u1,
+                ///  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
+                FCMD_QUAD: u1,
+                reserved14: u4,
+                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.
+                FREAD_DUAL: u1,
+                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.
+                FREAD_QUAD: u1,
+                reserved18: u2,
+                ///  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.
+                Q_POL: u1,
+                ///  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.
+                D_POL: u1,
+                ///  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
+                HOLD_POL: u1,
+                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
+                WP_POL: u1,
+                reserved25: u3,
+                ///  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.
+                RD_BIT_ORDER: u1,
+                ///  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.
+                WR_BIT_ORDER: u1,
+                padding: u5,
+            }),
+            ///  SPI clock control register
+            CLOCK: mmio.Mmio(packed struct(u32) {
+                ///  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.
+                CLKCNT_L: u6,
+                ///  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.
+                CLKCNT_H: u6,
+                ///  In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
+                CLKCNT_N: u6,
+                ///  In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.
+                CLKDIV_PRE: u4,
+                reserved31: u9,
+                ///  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.
+                CLK_EQU_SYSCLK: u1,
+            }),
+            ///  SPI USER control register
+            USER: mmio.Mmio(packed struct(u32) {
+                ///  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.
+                DOUTDIN: u1,
+                reserved3: u2,
+                ///  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.
+                QPI_MODE: u1,
+                reserved5: u1,
+                ///  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.
+                TSCK_I_EDGE: u1,
+                ///  spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.
+                CS_HOLD: u1,
+                ///  spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.
+                CS_SETUP: u1,
+                ///  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.
+                RSCK_I_EDGE: u1,
+                ///  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.
+                CK_OUT_EDGE: u1,
+                reserved12: u2,
+                ///  In the write operations read-data phase apply 2 signals. Can be configured in CONF state.
+                FWRITE_DUAL: u1,
+                ///  In the write operations read-data phase apply 4 signals. Can be configured in CONF state.
+                FWRITE_QUAD: u1,
+                reserved15: u1,
+                ///  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.
+                USR_CONF_NXT: u1,
+                reserved17: u1,
+                ///  Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.
+                SIO: u1,
+                reserved24: u6,
+                ///  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
+                USR_MISO_HIGHPART: u1,
+                ///  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
+                USR_MOSI_HIGHPART: u1,
+                ///  spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.
+                USR_DUMMY_IDLE: u1,
+                ///  This bit enable the write-data phase of an operation. Can be configured in CONF state.
+                USR_MOSI: u1,
+                ///  This bit enable the read-data phase of an operation. Can be configured in CONF state.
+                USR_MISO: u1,
+                ///  This bit enable the dummy phase of an operation. Can be configured in CONF state.
+                USR_DUMMY: u1,
+                ///  This bit enable the address phase of an operation. Can be configured in CONF state.
+                USR_ADDR: u1,
+                ///  This bit enable the command phase of an operation. Can be configured in CONF state.
+                USR_COMMAND: u1,
+            }),
+            ///  SPI USER control register 1
+            USER1: mmio.Mmio(packed struct(u32) {
+                ///  The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.
+                USR_DUMMY_CYCLELEN: u8,
+                reserved16: u8,
+                ///  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.
+                MST_WFULL_ERR_END_EN: u1,
+                ///  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.
+                CS_SETUP_TIME: u5,
+                ///  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.
+                CS_HOLD_TIME: u5,
+                ///  The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.
+                USR_ADDR_BITLEN: u5,
+            }),
+            ///  SPI USER control register 2
+            USER2: mmio.Mmio(packed struct(u32) {
+                ///  The value of command. Can be configured in CONF state.
+                USR_COMMAND_VALUE: u16,
+                reserved27: u11,
+                ///  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.
+                MST_REMPTY_ERR_END_EN: u1,
+                ///  The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.
+                USR_COMMAND_BITLEN: u4,
+            }),
+            ///  SPI data bit length control register
+            MS_DLEN: mmio.Mmio(packed struct(u32) {
+                ///  The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.
+                MS_DATA_BITLEN: u18,
+                padding: u14,
+            }),
+            ///  SPI misc register
+            MISC: mmio.Mmio(packed struct(u32) {
+                ///  SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.
+                CS0_DIS: u1,
+                ///  SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.
+                CS1_DIS: u1,
+                ///  SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.
+                CS2_DIS: u1,
+                ///  SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.
+                CS3_DIS: u1,
+                ///  SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.
+                CS4_DIS: u1,
+                ///  SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.
+                CS5_DIS: u1,
+                ///  1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.
+                CK_DIS: u1,
+                ///  In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
+                MASTER_CS_POL: u6,
+                reserved23: u10,
+                ///  spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.
+                SLAVE_CS_POL: u1,
+                reserved29: u5,
+                ///  1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.
+                CK_IDLE_EDGE: u1,
+                ///  spi cs line keep low when the bit is set. Can be configured in CONF state.
+                CS_KEEP_ACTIVE: u1,
+                ///  1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.
+                QUAD_DIN_PIN_SWAP: u1,
+            }),
+            ///  SPI input delay mode configuration
+            DIN_MODE: mmio.Mmio(packed struct(u32) {
+                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+                DIN0_MODE: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+                DIN1_MODE: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+                DIN2_MODE: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
+                DIN3_MODE: u2,
+                reserved16: u8,
+                ///  1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.
+                TIMING_HCLK_ACTIVE: u1,
+                padding: u15,
+            }),
+            ///  SPI input delay number configuration
+            DIN_NUM: mmio.Mmio(packed struct(u32) {
+                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
+                DIN0_NUM: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
+                DIN1_NUM: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
+                DIN2_NUM: u2,
+                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
+                DIN3_NUM: u2,
+                padding: u24,
+            }),
+            ///  SPI output delay mode configuration
+            DOUT_MODE: mmio.Mmio(packed struct(u32) {
+                ///  The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+                DOUT0_MODE: u1,
+                ///  The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+                DOUT1_MODE: u1,
+                ///  The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+                DOUT2_MODE: u1,
+                ///  The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
+                DOUT3_MODE: u1,
+                padding: u28,
+            }),
+            ///  SPI DMA control register
+            DMA_CONF: mmio.Mmio(packed struct(u32) {
+                reserved18: u18,
+                ///  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
+                DMA_SLV_SEG_TRANS_EN: u1,
+                ///  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.
+                SLV_RX_SEG_TRANS_CLR_EN: u1,
+                ///  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
+                SLV_TX_SEG_TRANS_CLR_EN: u1,
+                ///  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.
+                RX_EOF_EN: u1,
+                reserved27: u5,
+                ///  Set this bit to enable SPI DMA controlled receive data mode.
+                DMA_RX_ENA: u1,
+                ///  Set this bit to enable SPI DMA controlled send data mode.
+                DMA_TX_ENA: u1,
+                ///  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.
+                RX_AFIFO_RST: u1,
+                ///  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.
+                BUF_AFIFO_RST: u1,
+                ///  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.
+                DMA_AFIFO_RST: u1,
+            }),
+            ///  SPI DMA interrupt enable register
+            DMA_INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+                DMA_INFIFO_FULL_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+                DMA_OUTFIFO_EMPTY_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI slave Ex_QPI interrupt.
+                SLV_EX_QPI_INT_ENA: u1,
+                ///  The enable bit for SPI slave En_QPI interrupt.
+                SLV_EN_QPI_INT_ENA: u1,
+                ///  The enable bit for SPI slave CMD7 interrupt.
+                SLV_CMD7_INT_ENA: u1,
+                ///  The enable bit for SPI slave CMD8 interrupt.
+                SLV_CMD8_INT_ENA: u1,
+                ///  The enable bit for SPI slave CMD9 interrupt.
+                SLV_CMD9_INT_ENA: u1,
+                ///  The enable bit for SPI slave CMDA interrupt.
+                SLV_CMDA_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+                SLV_RD_DMA_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+                SLV_WR_DMA_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+                SLV_RD_BUF_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+                SLV_WR_BUF_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_TRANS_DONE_INT interrupt.
+                TRANS_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+                DMA_SEG_TRANS_DONE_INT_ENA: u1,
+                ///  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+                SEG_MAGIC_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+                SLV_BUF_ADDR_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
+                SLV_CMD_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+                MST_RX_AFIFO_WFULL_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+                MST_TX_AFIFO_REMPTY_ERR_INT_ENA: u1,
+                ///  The enable bit for SPI_APP2_INT interrupt.
+                APP2_INT_ENA: u1,
+                ///  The enable bit for SPI_APP1_INT interrupt.
+                APP1_INT_ENA: u1,
+                padding: u11,
+            }),
+            ///  SPI DMA interrupt clear register
+            DMA_INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+                DMA_INFIFO_FULL_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+                DMA_OUTFIFO_EMPTY_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI slave Ex_QPI interrupt.
+                SLV_EX_QPI_INT_CLR: u1,
+                ///  The clear bit for SPI slave En_QPI interrupt.
+                SLV_EN_QPI_INT_CLR: u1,
+                ///  The clear bit for SPI slave CMD7 interrupt.
+                SLV_CMD7_INT_CLR: u1,
+                ///  The clear bit for SPI slave CMD8 interrupt.
+                SLV_CMD8_INT_CLR: u1,
+                ///  The clear bit for SPI slave CMD9 interrupt.
+                SLV_CMD9_INT_CLR: u1,
+                ///  The clear bit for SPI slave CMDA interrupt.
+                SLV_CMDA_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+                SLV_RD_DMA_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+                SLV_WR_DMA_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+                SLV_RD_BUF_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+                SLV_WR_BUF_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_TRANS_DONE_INT interrupt.
+                TRANS_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+                DMA_SEG_TRANS_DONE_INT_CLR: u1,
+                ///  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+                SEG_MAGIC_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+                SLV_BUF_ADDR_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
+                SLV_CMD_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+                MST_RX_AFIFO_WFULL_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+                MST_TX_AFIFO_REMPTY_ERR_INT_CLR: u1,
+                ///  The clear bit for SPI_APP2_INT interrupt.
+                APP2_INT_CLR: u1,
+                ///  The clear bit for SPI_APP1_INT interrupt.
+                APP1_INT_CLR: u1,
+                padding: u11,
+            }),
+            ///  SPI DMA interrupt raw register
+            DMA_INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others.
+                DMA_INFIFO_FULL_ERR_INT_RAW: u1,
+                ///  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others.
+                DMA_OUTFIFO_EMPTY_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.
+                SLV_EX_QPI_INT_RAW: u1,
+                ///  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.
+                SLV_EN_QPI_INT_RAW: u1,
+                ///  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.
+                SLV_CMD7_INT_RAW: u1,
+                ///  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.
+                SLV_CMD8_INT_RAW: u1,
+                ///  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.
+                SLV_CMD9_INT_RAW: u1,
+                ///  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.
+                SLV_CMDA_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.
+                SLV_RD_DMA_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.
+                SLV_WR_DMA_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.
+                SLV_RD_BUF_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.
+                SLV_WR_BUF_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.
+                TRANS_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred.
+                DMA_SEG_TRANS_DONE_INT_RAW: u1,
+                ///  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.
+                SEG_MAGIC_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.
+                SLV_BUF_ADDR_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.
+                SLV_CMD_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.
+                MST_RX_AFIFO_WFULL_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
+                MST_TX_AFIFO_REMPTY_ERR_INT_RAW: u1,
+                ///  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.
+                APP2_INT_RAW: u1,
+                ///  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.
+                APP1_INT_RAW: u1,
+                padding: u11,
+            }),
+            ///  SPI DMA interrupt status register
+            DMA_INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
+                DMA_INFIFO_FULL_ERR_INT_ST: u1,
+                ///  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
+                DMA_OUTFIFO_EMPTY_ERR_INT_ST: u1,
+                ///  The status bit for SPI slave Ex_QPI interrupt.
+                SLV_EX_QPI_INT_ST: u1,
+                ///  The status bit for SPI slave En_QPI interrupt.
+                SLV_EN_QPI_INT_ST: u1,
+                ///  The status bit for SPI slave CMD7 interrupt.
+                SLV_CMD7_INT_ST: u1,
+                ///  The status bit for SPI slave CMD8 interrupt.
+                SLV_CMD8_INT_ST: u1,
+                ///  The status bit for SPI slave CMD9 interrupt.
+                SLV_CMD9_INT_ST: u1,
+                ///  The status bit for SPI slave CMDA interrupt.
+                SLV_CMDA_INT_ST: u1,
+                ///  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
+                SLV_RD_DMA_DONE_INT_ST: u1,
+                ///  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
+                SLV_WR_DMA_DONE_INT_ST: u1,
+                ///  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
+                SLV_RD_BUF_DONE_INT_ST: u1,
+                ///  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
+                SLV_WR_BUF_DONE_INT_ST: u1,
+                ///  The status bit for SPI_TRANS_DONE_INT interrupt.
+                TRANS_DONE_INT_ST: u1,
+                ///  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
+                DMA_SEG_TRANS_DONE_INT_ST: u1,
+                ///  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
+                SEG_MAGIC_ERR_INT_ST: u1,
+                ///  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
+                SLV_BUF_ADDR_ERR_INT_ST: u1,
+                ///  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
+                SLV_CMD_ERR_INT_ST: u1,
+                ///  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
+                MST_RX_AFIFO_WFULL_ERR_INT_ST: u1,
+                ///  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
+                MST_TX_AFIFO_REMPTY_ERR_INT_ST: u1,
+                ///  The status bit for SPI_APP2_INT interrupt.
+                APP2_INT_ST: u1,
+                ///  The status bit for SPI_APP1_INT interrupt.
+                APP1_INT_ST: u1,
+                padding: u11,
+            }),
+            reserved152: [84]u8,
+            ///  SPI CPU-controlled buffer0
+            W0: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF0: u32,
+            }),
+            ///  SPI CPU-controlled buffer1
+            W1: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF1: u32,
+            }),
+            ///  SPI CPU-controlled buffer2
+            W2: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF2: u32,
+            }),
+            ///  SPI CPU-controlled buffer3
+            W3: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF3: u32,
+            }),
+            ///  SPI CPU-controlled buffer4
+            W4: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF4: u32,
+            }),
+            ///  SPI CPU-controlled buffer5
+            W5: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF5: u32,
+            }),
+            ///  SPI CPU-controlled buffer6
+            W6: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF6: u32,
+            }),
+            ///  SPI CPU-controlled buffer7
+            W7: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF7: u32,
+            }),
+            ///  SPI CPU-controlled buffer8
+            W8: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF8: u32,
+            }),
+            ///  SPI CPU-controlled buffer9
+            W9: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF9: u32,
+            }),
+            ///  SPI CPU-controlled buffer10
+            W10: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF10: u32,
+            }),
+            ///  SPI CPU-controlled buffer11
+            W11: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF11: u32,
+            }),
+            ///  SPI CPU-controlled buffer12
+            W12: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF12: u32,
+            }),
+            ///  SPI CPU-controlled buffer13
+            W13: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF13: u32,
+            }),
+            ///  SPI CPU-controlled buffer14
+            W14: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF14: u32,
+            }),
+            ///  SPI CPU-controlled buffer15
+            W15: mmio.Mmio(packed struct(u32) {
+                ///  data buffer
+                BUF15: u32,
+            }),
+            reserved224: [8]u8,
+            ///  SPI slave control register
+            SLAVE: mmio.Mmio(packed struct(u32) {
+                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.
+                CLK_MODE: u2,
+                ///  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].
+                CLK_MODE_13: u1,
+                ///  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge
+                RSCK_DATA_OUT: u1,
+                reserved8: u4,
+                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others
+                SLV_RDDMA_BITLEN_EN: u1,
+                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others
+                SLV_WRDMA_BITLEN_EN: u1,
+                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others
+                SLV_RDBUF_BITLEN_EN: u1,
+                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others
+                SLV_WRBUF_BITLEN_EN: u1,
+                reserved22: u10,
+                ///  The magic value of BM table in master DMA seg-trans.
+                DMA_SEG_MAGIC_VALUE: u4,
+                ///  Set SPI work mode. 1: slave mode 0: master mode.
+                MODE: u1,
+                ///  Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.
+                SOFT_RESET: u1,
+                ///  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.
+                USR_CONF: u1,
+                padding: u3,
+            }),
+            ///  SPI slave control register 1
+            SLAVE1: mmio.Mmio(packed struct(u32) {
+                ///  The transferred data bit length in SPI slave FD and HD mode.
+                SLV_DATA_BITLEN: u18,
+                ///  In the slave mode it is the value of command.
+                SLV_LAST_COMMAND: u8,
+                ///  In the slave mode it is the value of address.
+                SLV_LAST_ADDR: u6,
+            }),
+            ///  SPI module clock and register clock control
+            CLK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to enable clk gate
+                CLK_EN: u1,
+                ///  Set this bit to power on the SPI module clock.
+                MST_CLK_ACTIVE: u1,
+                ///  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.
+                MST_CLK_SEL: u1,
+                padding: u29,
+            }),
+            reserved240: [4]u8,
+            ///  Version control
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  SPI register version.
+                DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  System
+        pub const SYSTEM = extern struct {
+            ///  cpu_peripheral clock gating register
+            CPU_PERI_CLK_EN: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  reg_clk_en_assist_debug
+                CLK_EN_ASSIST_DEBUG: u1,
+                ///  reg_clk_en_dedicated_gpio
+                CLK_EN_DEDICATED_GPIO: u1,
+                padding: u24,
+            }),
+            ///  cpu_peripheral reset register
+            CPU_PERI_RST_EN: mmio.Mmio(packed struct(u32) {
+                reserved6: u6,
+                ///  reg_rst_en_assist_debug
+                RST_EN_ASSIST_DEBUG: u1,
+                ///  reg_rst_en_dedicated_gpio
+                RST_EN_DEDICATED_GPIO: u1,
+                padding: u24,
+            }),
+            ///  cpu clock config register
+            CPU_PER_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_cpuperiod_sel
+                CPUPERIOD_SEL: u2,
+                ///  reg_pll_freq_sel
+                PLL_FREQ_SEL: u1,
+                ///  reg_cpu_wait_mode_force_on
+                CPU_WAIT_MODE_FORCE_ON: u1,
+                ///  reg_cpu_waiti_delay_num
+                CPU_WAITI_DELAY_NUM: u4,
+                padding: u24,
+            }),
+            ///  memory power down mask register
+            MEM_PD_MASK: mmio.Mmio(packed struct(u32) {
+                ///  reg_lslp_mem_pd_mask
+                LSLP_MEM_PD_MASK: u1,
+                padding: u31,
+            }),
+            ///  peripheral clock gating register
+            PERIP_CLK_EN0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timers_clk_en
+                TIMERS_CLK_EN: u1,
+                ///  reg_spi01_clk_en
+                SPI01_CLK_EN: u1,
+                ///  reg_uart_clk_en
+                UART_CLK_EN: u1,
+                ///  reg_wdg_clk_en
+                WDG_CLK_EN: u1,
+                ///  reg_i2s0_clk_en
+                I2S0_CLK_EN: u1,
+                ///  reg_uart1_clk_en
+                UART1_CLK_EN: u1,
+                ///  reg_spi2_clk_en
+                SPI2_CLK_EN: u1,
+                ///  reg_ext0_clk_en
+                I2C_EXT0_CLK_EN: u1,
+                ///  reg_uhci0_clk_en
+                UHCI0_CLK_EN: u1,
+                ///  reg_rmt_clk_en
+                RMT_CLK_EN: u1,
+                ///  reg_pcnt_clk_en
+                PCNT_CLK_EN: u1,
+                ///  reg_ledc_clk_en
+                LEDC_CLK_EN: u1,
+                ///  reg_uhci1_clk_en
+                UHCI1_CLK_EN: u1,
+                ///  reg_timergroup_clk_en
+                TIMERGROUP_CLK_EN: u1,
+                ///  reg_efuse_clk_en
+                EFUSE_CLK_EN: u1,
+                ///  reg_timergroup1_clk_en
+                TIMERGROUP1_CLK_EN: u1,
+                ///  reg_spi3_clk_en
+                SPI3_CLK_EN: u1,
+                ///  reg_pwm0_clk_en
+                PWM0_CLK_EN: u1,
+                ///  reg_ext1_clk_en
+                EXT1_CLK_EN: u1,
+                ///  reg_can_clk_en
+                CAN_CLK_EN: u1,
+                ///  reg_pwm1_clk_en
+                PWM1_CLK_EN: u1,
+                ///  reg_i2s1_clk_en
+                I2S1_CLK_EN: u1,
+                ///  reg_spi2_dma_clk_en
+                SPI2_DMA_CLK_EN: u1,
+                ///  reg_usb_device_clk_en
+                USB_DEVICE_CLK_EN: u1,
+                ///  reg_uart_mem_clk_en
+                UART_MEM_CLK_EN: u1,
+                ///  reg_pwm2_clk_en
+                PWM2_CLK_EN: u1,
+                ///  reg_pwm3_clk_en
+                PWM3_CLK_EN: u1,
+                ///  reg_spi3_dma_clk_en
+                SPI3_DMA_CLK_EN: u1,
+                ///  reg_apb_saradc_clk_en
+                APB_SARADC_CLK_EN: u1,
+                ///  reg_systimer_clk_en
+                SYSTIMER_CLK_EN: u1,
+                ///  reg_adc2_arb_clk_en
+                ADC2_ARB_CLK_EN: u1,
+                ///  reg_spi4_clk_en
+                SPI4_CLK_EN: u1,
+            }),
+            ///  peripheral clock gating register
+            PERIP_CLK_EN1: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  reg_crypto_aes_clk_en
+                CRYPTO_AES_CLK_EN: u1,
+                ///  reg_crypto_sha_clk_en
+                CRYPTO_SHA_CLK_EN: u1,
+                ///  reg_crypto_rsa_clk_en
+                CRYPTO_RSA_CLK_EN: u1,
+                ///  reg_crypto_ds_clk_en
+                CRYPTO_DS_CLK_EN: u1,
+                ///  reg_crypto_hmac_clk_en
+                CRYPTO_HMAC_CLK_EN: u1,
+                ///  reg_dma_clk_en
+                DMA_CLK_EN: u1,
+                ///  reg_sdio_host_clk_en
+                SDIO_HOST_CLK_EN: u1,
+                ///  reg_lcd_cam_clk_en
+                LCD_CAM_CLK_EN: u1,
+                ///  reg_uart2_clk_en
+                UART2_CLK_EN: u1,
+                ///  reg_tsens_clk_en
+                TSENS_CLK_EN: u1,
+                padding: u21,
+            }),
+            ///  reserved
+            PERIP_RST_EN0: mmio.Mmio(packed struct(u32) {
+                ///  reg_timers_rst
+                TIMERS_RST: u1,
+                ///  reg_spi01_rst
+                SPI01_RST: u1,
+                ///  reg_uart_rst
+                UART_RST: u1,
+                ///  reg_wdg_rst
+                WDG_RST: u1,
+                ///  reg_i2s0_rst
+                I2S0_RST: u1,
+                ///  reg_uart1_rst
+                UART1_RST: u1,
+                ///  reg_spi2_rst
+                SPI2_RST: u1,
+                ///  reg_ext0_rst
+                I2C_EXT0_RST: u1,
+                ///  reg_uhci0_rst
+                UHCI0_RST: u1,
+                ///  reg_rmt_rst
+                RMT_RST: u1,
+                ///  reg_pcnt_rst
+                PCNT_RST: u1,
+                ///  reg_ledc_rst
+                LEDC_RST: u1,
+                ///  reg_uhci1_rst
+                UHCI1_RST: u1,
+                ///  reg_timergroup_rst
+                TIMERGROUP_RST: u1,
+                ///  reg_efuse_rst
+                EFUSE_RST: u1,
+                ///  reg_timergroup1_rst
+                TIMERGROUP1_RST: u1,
+                ///  reg_spi3_rst
+                SPI3_RST: u1,
+                ///  reg_pwm0_rst
+                PWM0_RST: u1,
+                ///  reg_ext1_rst
+                EXT1_RST: u1,
+                ///  reg_can_rst
+                CAN_RST: u1,
+                ///  reg_pwm1_rst
+                PWM1_RST: u1,
+                ///  reg_i2s1_rst
+                I2S1_RST: u1,
+                ///  reg_spi2_dma_rst
+                SPI2_DMA_RST: u1,
+                ///  reg_usb_device_rst
+                USB_DEVICE_RST: u1,
+                ///  reg_uart_mem_rst
+                UART_MEM_RST: u1,
+                ///  reg_pwm2_rst
+                PWM2_RST: u1,
+                ///  reg_pwm3_rst
+                PWM3_RST: u1,
+                ///  reg_spi3_dma_rst
+                SPI3_DMA_RST: u1,
+                ///  reg_apb_saradc_rst
+                APB_SARADC_RST: u1,
+                ///  reg_systimer_rst
+                SYSTIMER_RST: u1,
+                ///  reg_adc2_arb_rst
+                ADC2_ARB_RST: u1,
+                ///  reg_spi4_rst
+                SPI4_RST: u1,
+            }),
+            ///  peripheral reset register
+            PERIP_RST_EN1: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  reg_crypto_aes_rst
+                CRYPTO_AES_RST: u1,
+                ///  reg_crypto_sha_rst
+                CRYPTO_SHA_RST: u1,
+                ///  reg_crypto_rsa_rst
+                CRYPTO_RSA_RST: u1,
+                ///  reg_crypto_ds_rst
+                CRYPTO_DS_RST: u1,
+                ///  reg_crypto_hmac_rst
+                CRYPTO_HMAC_RST: u1,
+                ///  reg_dma_rst
+                DMA_RST: u1,
+                ///  reg_sdio_host_rst
+                SDIO_HOST_RST: u1,
+                ///  reg_lcd_cam_rst
+                LCD_CAM_RST: u1,
+                ///  reg_uart2_rst
+                UART2_RST: u1,
+                ///  reg_tsens_rst
+                TSENS_RST: u1,
+                padding: u21,
+            }),
+            ///  clock config register
+            BT_LPCK_DIV_INT: mmio.Mmio(packed struct(u32) {
+                ///  reg_bt_lpck_div_num
+                BT_LPCK_DIV_NUM: u12,
+                padding: u20,
+            }),
+            ///  clock config register
+            BT_LPCK_DIV_FRAC: mmio.Mmio(packed struct(u32) {
+                ///  reg_bt_lpck_div_b
+                BT_LPCK_DIV_B: u12,
+                ///  reg_bt_lpck_div_a
+                BT_LPCK_DIV_A: u12,
+                ///  reg_lpclk_sel_rtc_slow
+                LPCLK_SEL_RTC_SLOW: u1,
+                ///  reg_lpclk_sel_8m
+                LPCLK_SEL_8M: u1,
+                ///  reg_lpclk_sel_xtal
+                LPCLK_SEL_XTAL: u1,
+                ///  reg_lpclk_sel_xtal32k
+                LPCLK_SEL_XTAL32K: u1,
+                ///  reg_lpclk_rtc_en
+                LPCLK_RTC_EN: u1,
+                padding: u3,
+            }),
+            ///  interrupt generate register
+            CPU_INTR_FROM_CPU_0: mmio.Mmio(packed struct(u32) {
+                ///  reg_cpu_intr_from_cpu_0
+                CPU_INTR_FROM_CPU_0: u1,
+                padding: u31,
+            }),
+            ///  interrupt generate register
+            CPU_INTR_FROM_CPU_1: mmio.Mmio(packed struct(u32) {
+                ///  reg_cpu_intr_from_cpu_1
+                CPU_INTR_FROM_CPU_1: u1,
+                padding: u31,
+            }),
+            ///  interrupt generate register
+            CPU_INTR_FROM_CPU_2: mmio.Mmio(packed struct(u32) {
+                ///  reg_cpu_intr_from_cpu_2
+                CPU_INTR_FROM_CPU_2: u1,
+                padding: u31,
+            }),
+            ///  interrupt generate register
+            CPU_INTR_FROM_CPU_3: mmio.Mmio(packed struct(u32) {
+                ///  reg_cpu_intr_from_cpu_3
+                CPU_INTR_FROM_CPU_3: u1,
+                padding: u31,
+            }),
+            ///  rsa memory power control register
+            RSA_PD_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_rsa_mem_pd
+                RSA_MEM_PD: u1,
+                ///  reg_rsa_mem_force_pu
+                RSA_MEM_FORCE_PU: u1,
+                ///  reg_rsa_mem_force_pd
+                RSA_MEM_FORCE_PD: u1,
+                padding: u29,
+            }),
+            ///  edma clcok and reset register
+            EDMA_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_edma_clk_on
+                EDMA_CLK_ON: u1,
+                ///  reg_edma_reset
+                EDMA_RESET: u1,
+                padding: u30,
+            }),
+            ///  cache control register
+            CACHE_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  reg_icache_clk_on
+                ICACHE_CLK_ON: u1,
+                ///  reg_icache_reset
+                ICACHE_RESET: u1,
+                ///  reg_dcache_clk_on
+                DCACHE_CLK_ON: u1,
+                ///  reg_dcache_reset
+                DCACHE_RESET: u1,
+                padding: u28,
+            }),
+            ///  SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
+            EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: mmio.Mmio(packed struct(u32) {
+                ///  reg_enable_spi_manual_encrypt
+                ENABLE_SPI_MANUAL_ENCRYPT: u1,
+                ///  reg_enable_download_db_encrypt
+                ENABLE_DOWNLOAD_DB_ENCRYPT: u1,
+                ///  reg_enable_download_g0cb_decrypt
+                ENABLE_DOWNLOAD_G0CB_DECRYPT: u1,
+                ///  reg_enable_download_manual_encrypt
+                ENABLE_DOWNLOAD_MANUAL_ENCRYPT: u1,
+                padding: u28,
+            }),
+            ///  fast memory config register
+            RTC_FASTMEM_CONFIG: mmio.Mmio(packed struct(u32) {
+                reserved8: u8,
+                ///  reg_rtc_mem_crc_start
+                RTC_MEM_CRC_START: u1,
+                ///  reg_rtc_mem_crc_addr
+                RTC_MEM_CRC_ADDR: u11,
+                ///  reg_rtc_mem_crc_len
+                RTC_MEM_CRC_LEN: u11,
+                ///  reg_rtc_mem_crc_finish
+                RTC_MEM_CRC_FINISH: u1,
+            }),
+            ///  reserved
+            RTC_FASTMEM_CRC: mmio.Mmio(packed struct(u32) {
+                ///  reg_rtc_mem_crc_res
+                RTC_MEM_CRC_RES: u32,
+            }),
+            ///  eco register
+            REDUNDANT_ECO_CTRL: mmio.Mmio(packed struct(u32) {
+                ///  reg_redundant_eco_drive
+                REDUNDANT_ECO_DRIVE: u1,
+                ///  reg_redundant_eco_result
+                REDUNDANT_ECO_RESULT: u1,
+                padding: u30,
+            }),
+            ///  clock gating register
+            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_clk_en
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            ///  system clock config register
+            SYSCLK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_pre_div_cnt
+                PRE_DIV_CNT: u10,
+                ///  reg_soc_clk_sel
+                SOC_CLK_SEL: u2,
+                ///  reg_clk_xtal_freq
+                CLK_XTAL_FREQ: u7,
+                ///  reg_clk_div_en
+                CLK_DIV_EN: u1,
+                padding: u12,
+            }),
+            ///  mem pvt register
+            MEM_PVT: mmio.Mmio(packed struct(u32) {
+                ///  reg_mem_path_len
+                MEM_PATH_LEN: u4,
+                ///  reg_mem_err_cnt_clr
+                MEM_ERR_CNT_CLR: u1,
+                ///  reg_mem_pvt_monitor_en
+                MONITOR_EN: u1,
+                ///  reg_mem_timing_err_cnt
+                MEM_TIMING_ERR_CNT: u16,
+                ///  reg_mem_vt_sel
+                MEM_VT_SEL: u2,
+                padding: u8,
+            }),
+            ///  mem pvt register
+            COMB_PVT_LVT_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_path_len_lvt
+                COMB_PATH_LEN_LVT: u5,
+                ///  reg_comb_err_cnt_clr_lvt
+                COMB_ERR_CNT_CLR_LVT: u1,
+                ///  reg_comb_pvt_monitor_en_lvt
+                COMB_PVT_MONITOR_EN_LVT: u1,
+                padding: u25,
+            }),
+            ///  mem pvt register
+            COMB_PVT_NVT_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_path_len_nvt
+                COMB_PATH_LEN_NVT: u5,
+                ///  reg_comb_err_cnt_clr_nvt
+                COMB_ERR_CNT_CLR_NVT: u1,
+                ///  reg_comb_pvt_monitor_en_nvt
+                COMB_PVT_MONITOR_EN_NVT: u1,
+                padding: u25,
+            }),
+            ///  mem pvt register
+            COMB_PVT_HVT_CONF: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_path_len_hvt
+                COMB_PATH_LEN_HVT: u5,
+                ///  reg_comb_err_cnt_clr_hvt
+                COMB_ERR_CNT_CLR_HVT: u1,
+                ///  reg_comb_pvt_monitor_en_hvt
+                COMB_PVT_MONITOR_EN_HVT: u1,
+                padding: u25,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_LVT_SITE0: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_lvt_site0
+                COMB_TIMING_ERR_CNT_LVT_SITE0: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_NVT_SITE0: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_nvt_site0
+                COMB_TIMING_ERR_CNT_NVT_SITE0: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_HVT_SITE0: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_hvt_site0
+                COMB_TIMING_ERR_CNT_HVT_SITE0: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_LVT_SITE1: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_lvt_site1
+                COMB_TIMING_ERR_CNT_LVT_SITE1: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_NVT_SITE1: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_nvt_site1
+                COMB_TIMING_ERR_CNT_NVT_SITE1: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_HVT_SITE1: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_hvt_site1
+                COMB_TIMING_ERR_CNT_HVT_SITE1: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_LVT_SITE2: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_lvt_site2
+                COMB_TIMING_ERR_CNT_LVT_SITE2: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_NVT_SITE2: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_nvt_site2
+                COMB_TIMING_ERR_CNT_NVT_SITE2: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_HVT_SITE2: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_hvt_site2
+                COMB_TIMING_ERR_CNT_HVT_SITE2: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_LVT_SITE3: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_lvt_site3
+                COMB_TIMING_ERR_CNT_LVT_SITE3: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_NVT_SITE3: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_nvt_site3
+                COMB_TIMING_ERR_CNT_NVT_SITE3: u16,
+                padding: u16,
+            }),
+            ///  mem pvt register
+            COMB_PVT_ERR_HVT_SITE3: mmio.Mmio(packed struct(u32) {
+                ///  reg_comb_timing_err_cnt_hvt_site3
+                COMB_TIMING_ERR_CNT_HVT_SITE3: u16,
+                padding: u16,
+            }),
+            reserved4092: [3936]u8,
+            ///  Version register
+            SYSTEM_REG_DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_system_reg_date
+                SYSTEM_REG_DATE: u28,
+                padding: u4,
+            }),
+        };
+
+        ///  System Timer
+        pub const SYSTIMER = extern struct {
+            ///  SYSTIMER_CONF.
+            CONF: mmio.Mmio(packed struct(u32) {
+                ///  systimer clock force on
+                SYSTIMER_CLK_FO: u1,
+                reserved22: u21,
+                ///  target2 work enable
+                TARGET2_WORK_EN: u1,
+                ///  target1 work enable
+                TARGET1_WORK_EN: u1,
+                ///  target0 work enable
+                TARGET0_WORK_EN: u1,
+                ///  If timer unit1 is stalled when core1 stalled
+                TIMER_UNIT1_CORE1_STALL_EN: u1,
+                ///  If timer unit1 is stalled when core0 stalled
+                TIMER_UNIT1_CORE0_STALL_EN: u1,
+                ///  If timer unit0 is stalled when core1 stalled
+                TIMER_UNIT0_CORE1_STALL_EN: u1,
+                ///  If timer unit0 is stalled when core0 stalled
+                TIMER_UNIT0_CORE0_STALL_EN: u1,
+                ///  timer unit1 work enable
+                TIMER_UNIT1_WORK_EN: u1,
+                ///  timer unit0 work enable
+                TIMER_UNIT0_WORK_EN: u1,
+                ///  register file clk gating
+                CLK_EN: u1,
+            }),
+            ///  SYSTIMER_UNIT0_OP.
+            UNIT0_OP: mmio.Mmio(packed struct(u32) {
+                reserved29: u29,
+                ///  reg_timer_unit0_value_valid
+                TIMER_UNIT0_VALUE_VALID: u1,
+                ///  update timer_unit0
+                TIMER_UNIT0_UPDATE: u1,
+                padding: u1,
+            }),
+            ///  SYSTIMER_UNIT1_OP.
+            UNIT1_OP: mmio.Mmio(packed struct(u32) {
+                reserved29: u29,
+                ///  timer value is sync and valid
+                TIMER_UNIT1_VALUE_VALID: u1,
+                ///  update timer unit1
+                TIMER_UNIT1_UPDATE: u1,
+                padding: u1,
+            }),
+            ///  SYSTIMER_UNIT0_LOAD_HI.
+            UNIT0_LOAD_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer unit0 load high 32 bit
+                TIMER_UNIT0_LOAD_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_UNIT0_LOAD_LO.
+            UNIT0_LOAD_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer unit0 load low 32 bit
+                TIMER_UNIT0_LOAD_LO: u32,
+            }),
+            ///  SYSTIMER_UNIT1_LOAD_HI.
+            UNIT1_LOAD_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer unit1 load high 32 bit
+                TIMER_UNIT1_LOAD_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_UNIT1_LOAD_LO.
+            UNIT1_LOAD_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer unit1 load low 32 bit
+                TIMER_UNIT1_LOAD_LO: u32,
+            }),
+            ///  SYSTIMER_TARGET0_HI.
+            TARGET0_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer taget0 high 32 bit
+                TIMER_TARGET0_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_TARGET0_LO.
+            TARGET0_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer taget0 low 32 bit
+                TIMER_TARGET0_LO: u32,
+            }),
+            ///  SYSTIMER_TARGET1_HI.
+            TARGET1_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer taget1 high 32 bit
+                TIMER_TARGET1_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_TARGET1_LO.
+            TARGET1_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer taget1 low 32 bit
+                TIMER_TARGET1_LO: u32,
+            }),
+            ///  SYSTIMER_TARGET2_HI.
+            TARGET2_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer taget2 high 32 bit
+                TIMER_TARGET2_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_TARGET2_LO.
+            TARGET2_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer taget2 low 32 bit
+                TIMER_TARGET2_LO: u32,
+            }),
+            ///  SYSTIMER_TARGET0_CONF.
+            TARGET0_CONF: mmio.Mmio(packed struct(u32) {
+                ///  target0 period
+                TARGET0_PERIOD: u26,
+                reserved30: u4,
+                ///  Set target0 to period mode
+                TARGET0_PERIOD_MODE: u1,
+                ///  select which unit to compare
+                TARGET0_TIMER_UNIT_SEL: u1,
+            }),
+            ///  SYSTIMER_TARGET1_CONF.
+            TARGET1_CONF: mmio.Mmio(packed struct(u32) {
+                ///  target1 period
+                TARGET1_PERIOD: u26,
+                reserved30: u4,
+                ///  Set target1 to period mode
+                TARGET1_PERIOD_MODE: u1,
+                ///  select which unit to compare
+                TARGET1_TIMER_UNIT_SEL: u1,
+            }),
+            ///  SYSTIMER_TARGET2_CONF.
+            TARGET2_CONF: mmio.Mmio(packed struct(u32) {
+                ///  target2 period
+                TARGET2_PERIOD: u26,
+                reserved30: u4,
+                ///  Set target2 to period mode
+                TARGET2_PERIOD_MODE: u1,
+                ///  select which unit to compare
+                TARGET2_TIMER_UNIT_SEL: u1,
+            }),
+            ///  SYSTIMER_UNIT0_VALUE_HI.
+            UNIT0_VALUE_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer read value high 32bit
+                TIMER_UNIT0_VALUE_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_UNIT0_VALUE_LO.
+            UNIT0_VALUE_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer read value low 32bit
+                TIMER_UNIT0_VALUE_LO: u32,
+            }),
+            ///  SYSTIMER_UNIT1_VALUE_HI.
+            UNIT1_VALUE_HI: mmio.Mmio(packed struct(u32) {
+                ///  timer read value high 32bit
+                TIMER_UNIT1_VALUE_HI: u20,
+                padding: u12,
+            }),
+            ///  SYSTIMER_UNIT1_VALUE_LO.
+            UNIT1_VALUE_LO: mmio.Mmio(packed struct(u32) {
+                ///  timer read value low 32bit
+                TIMER_UNIT1_VALUE_LO: u32,
+            }),
+            ///  SYSTIMER_COMP0_LOAD.
+            COMP0_LOAD: mmio.Mmio(packed struct(u32) {
+                ///  timer comp0 load value
+                TIMER_COMP0_LOAD: u1,
+                padding: u31,
+            }),
+            ///  SYSTIMER_COMP1_LOAD.
+            COMP1_LOAD: mmio.Mmio(packed struct(u32) {
+                ///  timer comp1 load value
+                TIMER_COMP1_LOAD: u1,
+                padding: u31,
+            }),
+            ///  SYSTIMER_COMP2_LOAD.
+            COMP2_LOAD: mmio.Mmio(packed struct(u32) {
+                ///  timer comp2 load value
+                TIMER_COMP2_LOAD: u1,
+                padding: u31,
+            }),
+            ///  SYSTIMER_UNIT0_LOAD.
+            UNIT0_LOAD: mmio.Mmio(packed struct(u32) {
+                ///  timer unit0 load value
+                TIMER_UNIT0_LOAD: u1,
+                padding: u31,
+            }),
+            ///  SYSTIMER_UNIT1_LOAD.
+            UNIT1_LOAD: mmio.Mmio(packed struct(u32) {
+                ///  timer unit1 load value
+                TIMER_UNIT1_LOAD: u1,
+                padding: u31,
+            }),
+            ///  SYSTIMER_INT_ENA.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  interupt0 enable
+                TARGET0_INT_ENA: u1,
+                ///  interupt1 enable
+                TARGET1_INT_ENA: u1,
+                ///  interupt2 enable
+                TARGET2_INT_ENA: u1,
+                padding: u29,
+            }),
+            ///  SYSTIMER_INT_RAW.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  interupt0 raw
+                TARGET0_INT_RAW: u1,
+                ///  interupt1 raw
+                TARGET1_INT_RAW: u1,
+                ///  interupt2 raw
+                TARGET2_INT_RAW: u1,
+                padding: u29,
+            }),
+            ///  SYSTIMER_INT_CLR.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  interupt0 clear
+                TARGET0_INT_CLR: u1,
+                ///  interupt1 clear
+                TARGET1_INT_CLR: u1,
+                ///  interupt2 clear
+                TARGET2_INT_CLR: u1,
+                padding: u29,
+            }),
+            ///  SYSTIMER_INT_ST.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  reg_target0_int_st
+                TARGET0_INT_ST: u1,
+                ///  reg_target1_int_st
+                TARGET1_INT_ST: u1,
+                ///  reg_target2_int_st
+                TARGET2_INT_ST: u1,
+                padding: u29,
+            }),
+            reserved252: [136]u8,
+            ///  SYSTIMER_DATE.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_date
+                DATE: u32,
+            }),
+        };
+
+        ///  Timer Group
+        pub const TIMG0 = extern struct {
+            ///  TIMG_T0CONFIG_REG.
+            T0CONFIG: mmio.Mmio(packed struct(u32) {
+                reserved9: u9,
+                ///  reg_t0_use_xtal.
+                T0_USE_XTAL: u1,
+                ///  reg_t0_alarm_en.
+                T0_ALARM_EN: u1,
+                reserved12: u1,
+                ///  reg_t0_divcnt_rst.
+                T0_DIVCNT_RST: u1,
+                ///  reg_t0_divider.
+                T0_DIVIDER: u16,
+                ///  reg_t0_autoreload.
+                T0_AUTORELOAD: u1,
+                ///  reg_t0_increase.
+                T0_INCREASE: u1,
+                ///  reg_t0_en.
+                T0_EN: u1,
+            }),
+            ///  TIMG_T0LO_REG.
+            T0LO: mmio.Mmio(packed struct(u32) {
+                ///  t0_lo
+                T0_LO: u32,
+            }),
+            ///  TIMG_T0HI_REG.
+            T0HI: mmio.Mmio(packed struct(u32) {
+                ///  t0_hi
+                T0_HI: u22,
+                padding: u10,
+            }),
+            ///  TIMG_T0UPDATE_REG.
+            T0UPDATE: mmio.Mmio(packed struct(u32) {
+                reserved31: u31,
+                ///  t0_update
+                T0_UPDATE: u1,
+            }),
+            ///  TIMG_T0ALARMLO_REG.
+            T0ALARMLO: mmio.Mmio(packed struct(u32) {
+                ///  reg_t0_alarm_lo.
+                T0_ALARM_LO: u32,
+            }),
+            ///  TIMG_T0ALARMHI_REG.
+            T0ALARMHI: mmio.Mmio(packed struct(u32) {
+                ///  reg_t0_alarm_hi.
+                T0_ALARM_HI: u22,
+                padding: u10,
+            }),
+            ///  TIMG_T0LOADLO_REG.
+            T0LOADLO: mmio.Mmio(packed struct(u32) {
+                ///  reg_t0_load_lo.
+                T0_LOAD_LO: u32,
+            }),
+            ///  TIMG_T0LOADHI_REG.
+            T0LOADHI: mmio.Mmio(packed struct(u32) {
+                ///  reg_t0_load_hi.
+                T0_LOAD_HI: u22,
+                padding: u10,
+            }),
+            ///  TIMG_T0LOAD_REG.
+            T0LOAD: mmio.Mmio(packed struct(u32) {
+                ///  t0_load
+                T0_LOAD: u32,
+            }),
+            reserved72: [36]u8,
+            ///  TIMG_WDTCONFIG0_REG.
+            WDTCONFIG0: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  reg_wdt_appcpu_reset_en.
+                WDT_APPCPU_RESET_EN: u1,
+                ///  reg_wdt_procpu_reset_en.
+                WDT_PROCPU_RESET_EN: u1,
+                ///  reg_wdt_flashboot_mod_en.
+                WDT_FLASHBOOT_MOD_EN: u1,
+                ///  reg_wdt_sys_reset_length.
+                WDT_SYS_RESET_LENGTH: u3,
+                ///  reg_wdt_cpu_reset_length.
+                WDT_CPU_RESET_LENGTH: u3,
+                ///  reg_wdt_use_xtal.
+                WDT_USE_XTAL: u1,
+                ///  reg_wdt_conf_update_en.
+                WDT_CONF_UPDATE_EN: u1,
+                ///  reg_wdt_stg3.
+                WDT_STG3: u2,
+                ///  reg_wdt_stg2.
+                WDT_STG2: u2,
+                ///  reg_wdt_stg1.
+                WDT_STG1: u2,
+                ///  reg_wdt_stg0.
+                WDT_STG0: u2,
+                ///  reg_wdt_en.
+                WDT_EN: u1,
+            }),
+            ///  TIMG_WDTCONFIG1_REG.
+            WDTCONFIG1: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_divcnt_rst.
+                WDT_DIVCNT_RST: u1,
+                reserved16: u15,
+                ///  reg_wdt_clk_prescale.
+                WDT_CLK_PRESCALE: u16,
+            }),
+            ///  TIMG_WDTCONFIG2_REG.
+            WDTCONFIG2: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_stg0_hold.
+                WDT_STG0_HOLD: u32,
+            }),
+            ///  TIMG_WDTCONFIG3_REG.
+            WDTCONFIG3: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_stg1_hold.
+                WDT_STG1_HOLD: u32,
+            }),
+            ///  TIMG_WDTCONFIG4_REG.
+            WDTCONFIG4: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_stg2_hold.
+                WDT_STG2_HOLD: u32,
+            }),
+            ///  TIMG_WDTCONFIG5_REG.
+            WDTCONFIG5: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_stg3_hold.
+                WDT_STG3_HOLD: u32,
+            }),
+            ///  TIMG_WDTFEED_REG.
+            WDTFEED: mmio.Mmio(packed struct(u32) {
+                ///  wdt_feed
+                WDT_FEED: u32,
+            }),
+            ///  TIMG_WDTWPROTECT_REG.
+            WDTWPROTECT: mmio.Mmio(packed struct(u32) {
+                ///  reg_wdt_wkey.
+                WDT_WKEY: u32,
+            }),
+            ///  TIMG_RTCCALICFG_REG.
+            RTCCALICFG: mmio.Mmio(packed struct(u32) {
+                reserved12: u12,
+                ///  reg_rtc_cali_start_cycling.
+                RTC_CALI_START_CYCLING: u1,
+                ///  reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
+                RTC_CALI_CLK_SEL: u2,
+                ///  rtc_cali_rdy
+                RTC_CALI_RDY: u1,
+                ///  reg_rtc_cali_max.
+                RTC_CALI_MAX: u15,
+                ///  reg_rtc_cali_start.
+                RTC_CALI_START: u1,
+            }),
+            ///  TIMG_RTCCALICFG1_REG.
+            RTCCALICFG1: mmio.Mmio(packed struct(u32) {
+                ///  rtc_cali_cycling_data_vld
+                RTC_CALI_CYCLING_DATA_VLD: u1,
+                reserved7: u6,
+                ///  rtc_cali_value
+                RTC_CALI_VALUE: u25,
+            }),
+            ///  INT_ENA_TIMG_REG
+            INT_ENA_TIMERS: mmio.Mmio(packed struct(u32) {
+                ///  t0_int_ena
+                T0_INT_ENA: u1,
+                ///  wdt_int_ena
+                WDT_INT_ENA: u1,
+                padding: u30,
+            }),
+            ///  INT_RAW_TIMG_REG
+            INT_RAW_TIMERS: mmio.Mmio(packed struct(u32) {
+                ///  t0_int_raw
+                T0_INT_RAW: u1,
+                ///  wdt_int_raw
+                WDT_INT_RAW: u1,
+                padding: u30,
+            }),
+            ///  INT_ST_TIMG_REG
+            INT_ST_TIMERS: mmio.Mmio(packed struct(u32) {
+                ///  t0_int_st
+                T0_INT_ST: u1,
+                ///  wdt_int_st
+                WDT_INT_ST: u1,
+                padding: u30,
+            }),
+            ///  INT_CLR_TIMG_REG
+            INT_CLR_TIMERS: mmio.Mmio(packed struct(u32) {
+                ///  t0_int_clr
+                T0_INT_CLR: u1,
+                ///  wdt_int_clr
+                WDT_INT_CLR: u1,
+                padding: u30,
+            }),
+            ///  TIMG_RTCCALICFG2_REG.
+            RTCCALICFG2: mmio.Mmio(packed struct(u32) {
+                ///  timeoutindicator
+                RTC_CALI_TIMEOUT: u1,
+                reserved3: u2,
+                ///  reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
+                RTC_CALI_TIMEOUT_RST_CNT: u4,
+                ///  reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
+                RTC_CALI_TIMEOUT_THRES: u25,
+            }),
+            reserved248: [116]u8,
+            ///  TIMG_NTIMG_DATE_REG.
+            NTIMG_DATE: mmio.Mmio(packed struct(u32) {
+                ///  reg_ntimers_date.
+                NTIMGS_DATE: u28,
+                padding: u4,
+            }),
+            ///  TIMG_REGCLK_REG.
+            REGCLK: mmio.Mmio(packed struct(u32) {
+                reserved29: u29,
+                ///  reg_wdt_clk_is_active.
+                WDT_CLK_IS_ACTIVE: u1,
+                ///  reg_timer_clk_is_active.
+                TIMER_CLK_IS_ACTIVE: u1,
+                ///  reg_clk_en.
+                CLK_EN: u1,
+            }),
+        };
+
+        ///  XTS-AES-128 Flash Encryption
+        pub const XTS_AES = extern struct {
+            ///  The memory that stores plaintext
+            PLAIN_MEM: [16]u8,
+            reserved64: [48]u8,
+            ///  XTS-AES line-size register
+            LINESIZE: mmio.Mmio(packed struct(u32) {
+                ///  This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
+                LINESIZE: u1,
+                padding: u31,
+            }),
+            ///  XTS-AES destination register
+            DESTINATION: mmio.Mmio(packed struct(u32) {
+                ///  This bit stores the destination. 0: flash(default). 1: reserved.
+                DESTINATION: u1,
+                padding: u31,
+            }),
+            ///  XTS-AES physical address register
+            PHYSICAL_ADDRESS: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.
+                PHYSICAL_ADDRESS: u30,
+                padding: u2,
+            }),
+            ///  XTS-AES trigger register
+            TRIGGER: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to start manual encryption calculation
+                TRIGGER: u1,
+                padding: u31,
+            }),
+            ///  XTS-AES release register
+            RELEASE: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to release the manual encrypted result, after that the result will be visible to spi
+                RELEASE: u1,
+                padding: u31,
+            }),
+            ///  XTS-AES destroy register
+            DESTROY: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to destroy XTS-AES result.
+                DESTROY: u1,
+                padding: u31,
+            }),
+            ///  XTS-AES status register
+            STATE: mmio.Mmio(packed struct(u32) {
+                ///  Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.
+                STATE: u2,
+                padding: u30,
+            }),
+            ///  XTS-AES version control register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  Those bits stores the version information of XTS-AES.
+                DATE: u30,
+                padding: u2,
+            }),
+        };
+
+        ///  Two-Wire Automotive Interface
+        pub const TWAI = extern struct {
+            ///  Mode Register
+            MODE: mmio.Mmio(packed struct(u32) {
+                ///  This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.
+                RESET_MODE: u1,
+                ///  1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.
+                LISTEN_ONLY_MODE: u1,
+                ///  1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.
+                SELF_TEST_MODE: u1,
+                ///  This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.
+                RX_FILTER_MODE: u1,
+                padding: u28,
+            }),
+            ///  Command Register
+            CMD: mmio.Mmio(packed struct(u32) {
+                ///  Set the bit to 1 to allow the driving nodes start transmission.
+                TX_REQ: u1,
+                ///  Set the bit to 1 to cancel a pending transmission request.
+                ABORT_TX: u1,
+                ///  Set the bit to 1 to release the RX buffer.
+                RELEASE_BUF: u1,
+                ///  Set the bit to 1 to clear the data overrun status bit.
+                CLR_OVERRUN: u1,
+                ///  Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.
+                SELF_RX_REQ: u1,
+                padding: u27,
+            }),
+            ///  Status register
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  1: The data in the RX buffer is not empty, with at least one received data packet.
+                RX_BUF_ST: u1,
+                ///  1: The RX FIFO is full and data overrun has occurred.
+                OVERRUN_ST: u1,
+                ///  1: The TX buffer is empty, the CPU may write a message into it.
+                TX_BUF_ST: u1,
+                ///  1: The TWAI controller has successfully received a packet from the bus.
+                TX_COMPLETE: u1,
+                ///  1: The TWAI Controller is receiving a message from the bus.
+                RX_ST: u1,
+                ///  1: The TWAI Controller is transmitting a message to the bus.
+                TX_ST: u1,
+                ///  1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.
+                ERR_ST: u1,
+                ///  1: In bus-off status, the TWAI Controller is no longer involved in bus activities.
+                BUS_OFF_ST: u1,
+                ///  This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete
+                MISS_ST: u1,
+                padding: u23,
+            }),
+            ///  Interrupt Register
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.
+                RX_INT_ST: u1,
+                ///  Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.
+                TX_INT_ST: u1,
+                ///  Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).
+                ERR_WARN_INT_ST: u1,
+                ///  Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.
+                OVERRUN_INT_ST: u1,
+                reserved5: u1,
+                ///  Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.
+                ERR_PASSIVE_INT_ST: u1,
+                ///  Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.
+                ARB_LOST_INT_ST: u1,
+                ///  Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.
+                BUS_ERR_INT_ST: u1,
+                padding: u24,
+            }),
+            ///  Interrupt Enable Register
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to 1 to enable receive interrupt.
+                RX_INT_ENA: u1,
+                ///  Set this bit to 1 to enable transmit interrupt.
+                TX_INT_ENA: u1,
+                ///  Set this bit to 1 to enable error warning interrupt.
+                ERR_WARN_INT_ENA: u1,
+                ///  Set this bit to 1 to enable data overrun interrupt.
+                OVERRUN_INT_ENA: u1,
+                reserved5: u1,
+                ///  Set this bit to 1 to enable error passive interrupt.
+                ERR_PASSIVE_INT_ENA: u1,
+                ///  Set this bit to 1 to enable arbitration lost interrupt.
+                ARB_LOST_INT_ENA: u1,
+                ///  Set this bit to 1 to enable error interrupt.
+                BUS_ERR_INT_ENA: u1,
+                padding: u24,
+            }),
+            reserved24: [4]u8,
+            ///  Bus Timing Register 0
+            BUS_TIMING_0: mmio.Mmio(packed struct(u32) {
+                ///  Baud Rate Prescaler, determines the frequency dividing ratio.
+                BAUD_PRESC: u13,
+                reserved14: u1,
+                ///  Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.
+                SYNC_JUMP_WIDTH: u2,
+                padding: u16,
+            }),
+            ///  Bus Timing Register 1
+            BUS_TIMING_1: mmio.Mmio(packed struct(u32) {
+                ///  The width of PBS1.
+                TIME_SEG1: u4,
+                ///  The width of PBS2.
+                TIME_SEG2: u3,
+                ///  The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times
+                TIME_SAMP: u1,
+                padding: u24,
+            }),
+            reserved44: [12]u8,
+            ///  Arbitration Lost Capture Register
+            ARB_LOST_CAP: mmio.Mmio(packed struct(u32) {
+                ///  This register contains information about the bit position of lost arbitration.
+                ARB_LOST_CAP: u5,
+                padding: u27,
+            }),
+            ///  Error Code Capture Register
+            ERR_CODE_CAP: mmio.Mmio(packed struct(u32) {
+                ///  This register contains information about the location of errors, see Table 181 for details.
+                ECC_SEGMENT: u5,
+                ///  This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message
+                ECC_DIRECTION: u1,
+                ///  This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error
+                ECC_TYPE: u2,
+                padding: u24,
+            }),
+            ///  Error Warning Limit Register
+            ERR_WARNING_LIMIT: mmio.Mmio(packed struct(u32) {
+                ///  Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).
+                ERR_WARNING_LIMIT: u8,
+                padding: u24,
+            }),
+            ///  Receive Error Counter Register
+            RX_ERR_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The RX error counter register, reflects value changes under reception status.
+                RX_ERR_CNT: u8,
+                padding: u24,
+            }),
+            ///  Transmit Error Counter Register
+            TX_ERR_CNT: mmio.Mmio(packed struct(u32) {
+                ///  The TX error counter register, reflects value changes under transmission status.
+                TX_ERR_CNT: u8,
+                padding: u24,
+            }),
+            ///  Data register 0
+            DATA_0: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_0: u8,
+                padding: u24,
+            }),
+            ///  Data register 1
+            DATA_1: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.
+                TX_BYTE_1: u8,
+                padding: u24,
+            }),
+            ///  Data register 2
+            DATA_2: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.
+                TX_BYTE_2: u8,
+                padding: u24,
+            }),
+            ///  Data register 3
+            DATA_3: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.
+                TX_BYTE_3: u8,
+                padding: u24,
+            }),
+            ///  Data register 4
+            DATA_4: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_4: u8,
+                padding: u24,
+            }),
+            ///  Data register 5
+            DATA_5: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_5: u8,
+                padding: u24,
+            }),
+            ///  Data register 6
+            DATA_6: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_6: u8,
+                padding: u24,
+            }),
+            ///  Data register 7
+            DATA_7: mmio.Mmio(packed struct(u32) {
+                ///  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_7: u8,
+                padding: u24,
+            }),
+            ///  Data register 8
+            DATA_8: mmio.Mmio(packed struct(u32) {
+                ///  Stored the 8th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_8: u8,
+                padding: u24,
+            }),
+            ///  Data register 9
+            DATA_9: mmio.Mmio(packed struct(u32) {
+                ///  Stored the 9th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_9: u8,
+                padding: u24,
+            }),
+            ///  Data register 10
+            DATA_10: mmio.Mmio(packed struct(u32) {
+                ///  Stored the 10th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_10: u8,
+                padding: u24,
+            }),
+            ///  Data register 11
+            DATA_11: mmio.Mmio(packed struct(u32) {
+                ///  Stored the 11th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_11: u8,
+                padding: u24,
+            }),
+            ///  Data register 12
+            DATA_12: mmio.Mmio(packed struct(u32) {
+                ///  Stored the 12th byte information of the data to be transmitted under operating mode.
+                TX_BYTE_12: u8,
+                padding: u24,
+            }),
+            ///  Receive Message Counter Register
+            RX_MESSAGE_CNT: mmio.Mmio(packed struct(u32) {
+                ///  This register reflects the number of messages available within the RX FIFO.
+                RX_MESSAGE_COUNTER: u7,
+                padding: u25,
+            }),
+            reserved124: [4]u8,
+            ///  Clock Divider register
+            CLOCK_DIVIDER: mmio.Mmio(packed struct(u32) {
+                ///  These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.
+                CD: u8,
+                ///  This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin
+                CLOCK_OFF: u1,
+                padding: u23,
+            }),
+        };
+
+        ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
+        pub const UART0 = extern struct {
+            ///  FIFO data register
+            FIFO: mmio.Mmio(packed struct(u32) {
+                ///  UART 0 accesses FIFO via this register.
+                RXFIFO_RD_BYTE: u8,
+                padding: u24,
+            }),
+            ///  Raw interrupt status
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.
+                RXFIFO_FULL_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .
+                TXFIFO_EMPTY_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a parity error in the data.
+                PARITY_ERR_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a data frame error .
+                FRM_ERR_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.
+                RXFIFO_OVF_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.
+                DSR_CHG_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.
+                CTS_CHG_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.
+                BRK_DET_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.
+                RXFIFO_TOUT_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.
+                SW_XON_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.
+                SW_XOFF_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.
+                GLITCH_DET_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent.
+                TX_BRK_DONE_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.
+                TX_BRK_IDLE_DONE_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.
+                TX_DONE_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.
+                RS485_PARITY_ERR_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.
+                RS485_FRM_ERR_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.
+                RS485_CLASH_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.
+                AT_CMD_CHAR_DET_INT_RAW: u1,
+                ///  This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.
+                WAKEUP_INT_RAW: u1,
+                padding: u12,
+            }),
+            ///  Masked interrupt status
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
+                RXFIFO_FULL_INT_ST: u1,
+                ///  This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.
+                TXFIFO_EMPTY_INT_ST: u1,
+                ///  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
+                PARITY_ERR_INT_ST: u1,
+                ///  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
+                FRM_ERR_INT_ST: u1,
+                ///  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
+                RXFIFO_OVF_INT_ST: u1,
+                ///  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
+                DSR_CHG_INT_ST: u1,
+                ///  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
+                CTS_CHG_INT_ST: u1,
+                ///  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
+                BRK_DET_INT_ST: u1,
+                ///  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
+                RXFIFO_TOUT_INT_ST: u1,
+                ///  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
+                SW_XON_INT_ST: u1,
+                ///  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
+                SW_XOFF_INT_ST: u1,
+                ///  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
+                GLITCH_DET_INT_ST: u1,
+                ///  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
+                TX_BRK_DONE_INT_ST: u1,
+                ///  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.
+                TX_BRK_IDLE_DONE_INT_ST: u1,
+                ///  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
+                TX_DONE_INT_ST: u1,
+                ///  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.
+                RS485_PARITY_ERR_INT_ST: u1,
+                ///  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.
+                RS485_FRM_ERR_INT_ST: u1,
+                ///  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
+                RS485_CLASH_INT_ST: u1,
+                ///  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.
+                AT_CMD_CHAR_DET_INT_ST: u1,
+                ///  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
+                WAKEUP_INT_ST: u1,
+                padding: u12,
+            }),
+            ///  Interrupt enable bits
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  This is the enable bit for rxfifo_full_int_st register.
+                RXFIFO_FULL_INT_ENA: u1,
+                ///  This is the enable bit for txfifo_empty_int_st register.
+                TXFIFO_EMPTY_INT_ENA: u1,
+                ///  This is the enable bit for parity_err_int_st register.
+                PARITY_ERR_INT_ENA: u1,
+                ///  This is the enable bit for frm_err_int_st register.
+                FRM_ERR_INT_ENA: u1,
+                ///  This is the enable bit for rxfifo_ovf_int_st register.
+                RXFIFO_OVF_INT_ENA: u1,
+                ///  This is the enable bit for dsr_chg_int_st register.
+                DSR_CHG_INT_ENA: u1,
+                ///  This is the enable bit for cts_chg_int_st register.
+                CTS_CHG_INT_ENA: u1,
+                ///  This is the enable bit for brk_det_int_st register.
+                BRK_DET_INT_ENA: u1,
+                ///  This is the enable bit for rxfifo_tout_int_st register.
+                RXFIFO_TOUT_INT_ENA: u1,
+                ///  This is the enable bit for sw_xon_int_st register.
+                SW_XON_INT_ENA: u1,
+                ///  This is the enable bit for sw_xoff_int_st register.
+                SW_XOFF_INT_ENA: u1,
+                ///  This is the enable bit for glitch_det_int_st register.
+                GLITCH_DET_INT_ENA: u1,
+                ///  This is the enable bit for tx_brk_done_int_st register.
+                TX_BRK_DONE_INT_ENA: u1,
+                ///  This is the enable bit for tx_brk_idle_done_int_st register.
+                TX_BRK_IDLE_DONE_INT_ENA: u1,
+                ///  This is the enable bit for tx_done_int_st register.
+                TX_DONE_INT_ENA: u1,
+                ///  This is the enable bit for rs485_parity_err_int_st register.
+                RS485_PARITY_ERR_INT_ENA: u1,
+                ///  This is the enable bit for rs485_parity_err_int_st register.
+                RS485_FRM_ERR_INT_ENA: u1,
+                ///  This is the enable bit for rs485_clash_int_st register.
+                RS485_CLASH_INT_ENA: u1,
+                ///  This is the enable bit for at_cmd_char_det_int_st register.
+                AT_CMD_CHAR_DET_INT_ENA: u1,
+                ///  This is the enable bit for uart_wakeup_int_st register.
+                WAKEUP_INT_ENA: u1,
+                padding: u12,
+            }),
+            ///  Interrupt clear bits
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the rxfifo_full_int_raw interrupt.
+                RXFIFO_FULL_INT_CLR: u1,
+                ///  Set this bit to clear txfifo_empty_int_raw interrupt.
+                TXFIFO_EMPTY_INT_CLR: u1,
+                ///  Set this bit to clear parity_err_int_raw interrupt.
+                PARITY_ERR_INT_CLR: u1,
+                ///  Set this bit to clear frm_err_int_raw interrupt.
+                FRM_ERR_INT_CLR: u1,
+                ///  Set this bit to clear rxfifo_ovf_int_raw interrupt.
+                RXFIFO_OVF_INT_CLR: u1,
+                ///  Set this bit to clear the dsr_chg_int_raw interrupt.
+                DSR_CHG_INT_CLR: u1,
+                ///  Set this bit to clear the cts_chg_int_raw interrupt.
+                CTS_CHG_INT_CLR: u1,
+                ///  Set this bit to clear the brk_det_int_raw interrupt.
+                BRK_DET_INT_CLR: u1,
+                ///  Set this bit to clear the rxfifo_tout_int_raw interrupt.
+                RXFIFO_TOUT_INT_CLR: u1,
+                ///  Set this bit to clear the sw_xon_int_raw interrupt.
+                SW_XON_INT_CLR: u1,
+                ///  Set this bit to clear the sw_xoff_int_raw interrupt.
+                SW_XOFF_INT_CLR: u1,
+                ///  Set this bit to clear the glitch_det_int_raw interrupt.
+                GLITCH_DET_INT_CLR: u1,
+                ///  Set this bit to clear the tx_brk_done_int_raw interrupt..
+                TX_BRK_DONE_INT_CLR: u1,
+                ///  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
+                TX_BRK_IDLE_DONE_INT_CLR: u1,
+                ///  Set this bit to clear the tx_done_int_raw interrupt.
+                TX_DONE_INT_CLR: u1,
+                ///  Set this bit to clear the rs485_parity_err_int_raw interrupt.
+                RS485_PARITY_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the rs485_frm_err_int_raw interrupt.
+                RS485_FRM_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the rs485_clash_int_raw interrupt.
+                RS485_CLASH_INT_CLR: u1,
+                ///  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
+                AT_CMD_CHAR_DET_INT_CLR: u1,
+                ///  Set this bit to clear the uart_wakeup_int_raw interrupt.
+                WAKEUP_INT_CLR: u1,
+                padding: u12,
+            }),
+            ///  Clock divider configuration
+            CLKDIV: mmio.Mmio(packed struct(u32) {
+                ///  The integral part of the frequency divider factor.
+                CLKDIV: u12,
+                reserved20: u8,
+                ///  The decimal part of the frequency divider factor.
+                FRAG: u4,
+                padding: u8,
+            }),
+            ///  Rx Filter configuration
+            RX_FILT: mmio.Mmio(packed struct(u32) {
+                ///  when input pulse width is lower than this value, the pulse is ignored.
+                GLITCH_FILT: u8,
+                ///  Set this bit to enable Rx signal filter.
+                GLITCH_FILT_EN: u1,
+                padding: u23,
+            }),
+            ///  UART status register
+            STATUS: mmio.Mmio(packed struct(u32) {
+                ///  Stores the byte number of valid data in Rx-FIFO.
+                RXFIFO_CNT: u10,
+                reserved13: u3,
+                ///  The register represent the level value of the internal uart dsr signal.
+                DSRN: u1,
+                ///  This register represent the level value of the internal uart cts signal.
+                CTSN: u1,
+                ///  This register represent the level value of the internal uart rxd signal.
+                RXD: u1,
+                ///  Stores the byte number of data in Tx-FIFO.
+                TXFIFO_CNT: u10,
+                reserved29: u3,
+                ///  This bit represents the level of the internal uart dtr signal.
+                DTRN: u1,
+                ///  This bit represents the level of the internal uart rts signal.
+                RTSN: u1,
+                ///  This bit represents the level of the internal uart txd signal.
+                TXD: u1,
+            }),
+            ///  a
+            CONF0: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the parity check mode.
+                PARITY: u1,
+                ///  Set this bit to enable uart parity check.
+                PARITY_EN: u1,
+                ///  This register is used to set the length of data.
+                BIT_NUM: u2,
+                ///  This register is used to set the length of stop bit.
+                STOP_BIT_NUM: u2,
+                ///  This register is used to configure the software rts signal which is used in software flow control.
+                SW_RTS: u1,
+                ///  This register is used to configure the software dtr signal which is used in software flow control.
+                SW_DTR: u1,
+                ///  Set this bit to enbale transmitter to send NULL when the process of sending data is done.
+                TXD_BRK: u1,
+                ///  Set this bit to enable IrDA loopback mode.
+                IRDA_DPLX: u1,
+                ///  This is the start enable bit for IrDA transmitter.
+                IRDA_TX_EN: u1,
+                ///  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.
+                IRDA_WCTL: u1,
+                ///  Set this bit to invert the level of IrDA transmitter.
+                IRDA_TX_INV: u1,
+                ///  Set this bit to invert the level of IrDA receiver.
+                IRDA_RX_INV: u1,
+                ///  Set this bit to enable uart loopback test mode.
+                LOOPBACK: u1,
+                ///  Set this bit to enable flow control function for transmitter.
+                TX_FLOW_EN: u1,
+                ///  Set this bit to enable IrDA protocol.
+                IRDA_EN: u1,
+                ///  Set this bit to reset the uart receive-FIFO.
+                RXFIFO_RST: u1,
+                ///  Set this bit to reset the uart transmit-FIFO.
+                TXFIFO_RST: u1,
+                ///  Set this bit to inverse the level value of uart rxd signal.
+                RXD_INV: u1,
+                ///  Set this bit to inverse the level value of uart cts signal.
+                CTS_INV: u1,
+                ///  Set this bit to inverse the level value of uart dsr signal.
+                DSR_INV: u1,
+                ///  Set this bit to inverse the level value of uart txd signal.
+                TXD_INV: u1,
+                ///  Set this bit to inverse the level value of uart rts signal.
+                RTS_INV: u1,
+                ///  Set this bit to inverse the level value of uart dtr signal.
+                DTR_INV: u1,
+                ///  1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
+                CLK_EN: u1,
+                ///  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.
+                ERR_WR_MASK: u1,
+                ///  This is the enable bit for detecting baudrate.
+                AUTOBAUD_EN: u1,
+                ///  UART memory clock gate enable signal.
+                MEM_CLK_EN: u1,
+                padding: u3,
+            }),
+            ///  Configuration register 1
+            CONF1: mmio.Mmio(packed struct(u32) {
+                ///  It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.
+                RXFIFO_FULL_THRHD: u9,
+                ///  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.
+                TXFIFO_EMPTY_THRHD: u9,
+                ///  Disable UART Rx data overflow detect.
+                DIS_RX_DAT_OVF: u1,
+                ///  Set this bit to stop accumulating idle_cnt when hardware flow control works.
+                RX_TOUT_FLOW_DIS: u1,
+                ///  This is the flow enable bit for UART receiver.
+                RX_FLOW_EN: u1,
+                ///  This is the enble bit for uart receiver's timeout function.
+                RX_TOUT_EN: u1,
+                padding: u10,
+            }),
+            ///  Autobaud minimum low pulse duration register
+            LOWPULSE: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.
+                MIN_CNT: u12,
+                padding: u20,
+            }),
+            ///  Autobaud minimum high pulse duration register
+            HIGHPULSE: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.
+                MIN_CNT: u12,
+                padding: u20,
+            }),
+            ///  Autobaud edge change count register
+            RXD_CNT: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the count of rxd edge change. It is used in baud rate-detect process.
+                RXD_EDGE_CNT: u10,
+                padding: u22,
+            }),
+            ///  Software flow-control configuration
+            FLOW_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.
+                SW_FLOW_CON_EN: u1,
+                ///  Set this bit to remove flow control char from the received data.
+                XONOFF_DEL: u1,
+                ///  Set this bit to enable the transmitter to go on sending data.
+                FORCE_XON: u1,
+                ///  Set this bit to stop the transmitter from sending data.
+                FORCE_XOFF: u1,
+                ///  Set this bit to send Xon char. It is cleared by hardware automatically.
+                SEND_XON: u1,
+                ///  Set this bit to send Xoff char. It is cleared by hardware automatically.
+                SEND_XOFF: u1,
+                padding: u26,
+            }),
+            ///  Sleep-mode configuration
+            SLEEP_CONF: mmio.Mmio(packed struct(u32) {
+                ///  The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.
+                ACTIVE_THRESHOLD: u10,
+                padding: u22,
+            }),
+            ///  Software flow-control character configuration
+            SWFC_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.
+                XOFF_THRESHOLD: u9,
+                ///  This register stores the Xoff flow control char.
+                XOFF_CHAR: u8,
+                padding: u15,
+            }),
+            ///  Software flow-control character configuration
+            SWFC_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.
+                XON_THRESHOLD: u9,
+                ///  This register stores the Xon flow control char.
+                XON_CHAR: u8,
+                padding: u15,
+            }),
+            ///  Tx Break character configuration
+            TXBRK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.
+                TX_BRK_NUM: u8,
+                padding: u24,
+            }),
+            ///  Frame-end idle configuration
+            IDLE_CONF: mmio.Mmio(packed struct(u32) {
+                ///  It will produce frame end signal when receiver takes more time to receive one byte data than this register value.
+                RX_IDLE_THRHD: u10,
+                ///  This register is used to configure the duration time between transfers.
+                TX_IDLE_NUM: u10,
+                padding: u12,
+            }),
+            ///  RS485 mode configuration
+            RS485_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to choose the rs485 mode.
+                RS485_EN: u1,
+                ///  Set this bit to delay the stop bit by 1 bit.
+                DL0_EN: u1,
+                ///  Set this bit to delay the stop bit by 1 bit.
+                DL1_EN: u1,
+                ///  Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.
+                RS485TX_RX_EN: u1,
+                ///  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
+                RS485RXBY_TX_EN: u1,
+                ///  This register is used to delay the receiver's internal data signal.
+                RS485_RX_DLY_NUM: u1,
+                ///  This register is used to delay the transmitter's internal data signal.
+                RS485_TX_DLY_NUM: u4,
+                padding: u22,
+            }),
+            ///  Pre-sequence timing configuration
+            AT_CMD_PRECNT: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the idle duration time before the first at_cmd is received by receiver.
+                PRE_IDLE_NUM: u16,
+                padding: u16,
+            }),
+            ///  Post-sequence timing configuration
+            AT_CMD_POSTCNT: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the duration time between the last at_cmd and the next data.
+                POST_IDLE_NUM: u16,
+                padding: u16,
+            }),
+            ///  Timeout configuration
+            AT_CMD_GAPTOUT: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the duration time between the at_cmd chars.
+                RX_GAP_TOUT: u16,
+                padding: u16,
+            }),
+            ///  AT escape sequence detection configuration
+            AT_CMD_CHAR: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the content of at_cmd char.
+                AT_CMD_CHAR: u8,
+                ///  This register is used to configure the num of continuous at_cmd chars received by receiver.
+                CHAR_NUM: u8,
+                padding: u16,
+            }),
+            ///  UART threshold and allocation configuration
+            MEM_CONF: mmio.Mmio(packed struct(u32) {
+                reserved1: u1,
+                ///  This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.
+                RX_SIZE: u3,
+                ///  This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.
+                TX_SIZE: u3,
+                ///  This register is used to configure the maximum amount of data that can be received when hardware flow control works.
+                RX_FLOW_THRHD: u9,
+                ///  This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.
+                RX_TOUT_THRHD: u10,
+                ///  Set this bit to force power down UART memory.
+                MEM_FORCE_PD: u1,
+                ///  Set this bit to force power up UART memory.
+                MEM_FORCE_PU: u1,
+                padding: u4,
+            }),
+            ///  Tx-FIFO write and read offset address.
+            MEM_TX_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.
+                APB_TX_WADDR: u10,
+                reserved11: u1,
+                ///  This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.
+                TX_RADDR: u10,
+                padding: u11,
+            }),
+            ///  Rx-FIFO write and read offset address.
+            MEM_RX_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
+                APB_RX_RADDR: u10,
+                reserved11: u1,
+                ///  This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
+                RX_WADDR: u10,
+                padding: u11,
+            }),
+            ///  UART transmit and receive status.
+            FSM_STATUS: mmio.Mmio(packed struct(u32) {
+                ///  This is the status register of receiver.
+                ST_URX_OUT: u4,
+                ///  This is the status register of transmitter.
+                ST_UTX_OUT: u4,
+                padding: u24,
+            }),
+            ///  Autobaud high pulse register
+            POSPULSE: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.
+                POSEDGE_MIN_CNT: u12,
+                padding: u20,
+            }),
+            ///  Autobaud low pulse register
+            NEGPULSE: mmio.Mmio(packed struct(u32) {
+                ///  This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.
+                NEGEDGE_MIN_CNT: u12,
+                padding: u20,
+            }),
+            ///  UART core clock configuration
+            CLK_CONF: mmio.Mmio(packed struct(u32) {
+                ///  The denominator of the frequency divider factor.
+                SCLK_DIV_B: u6,
+                ///  The numerator of the frequency divider factor.
+                SCLK_DIV_A: u6,
+                ///  The integral part of the frequency divider factor.
+                SCLK_DIV_NUM: u8,
+                ///  UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
+                SCLK_SEL: u2,
+                ///  Set this bit to enable UART Tx/Rx clock.
+                SCLK_EN: u1,
+                ///  Write 1 then write 0 to this bit, reset UART Tx/Rx.
+                RST_CORE: u1,
+                ///  Set this bit to enable UART Tx clock.
+                TX_SCLK_EN: u1,
+                ///  Set this bit to enable UART Rx clock.
+                RX_SCLK_EN: u1,
+                ///  Write 1 then write 0 to this bit, reset UART Tx.
+                TX_RST_CORE: u1,
+                ///  Write 1 then write 0 to this bit, reset UART Rx.
+                RX_RST_CORE: u1,
+                padding: u4,
+            }),
+            ///  UART Version register
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  This is the version register.
+                DATE: u32,
+            }),
+            ///  UART ID register
+            ID: mmio.Mmio(packed struct(u32) {
+                ///  This register is used to configure the uart_id.
+                ID: u30,
+                ///  This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.
+                HIGH_SPEED: u1,
+                ///  Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.
+                REG_UPDATE: u1,
+            }),
+        };
+
+        ///  Full-speed USB Serial/JTAG Controller
+        pub const USB_DEVICE = extern struct {
+            ///  USB_DEVICE_EP1_REG.
+            EP1: mmio.Mmio(packed struct(u32) {
+                ///  Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.
+                RDWR_BYTE: u8,
+                padding: u24,
+            }),
+            ///  USB_DEVICE_EP1_CONF_REG.
+            EP1_CONF: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to indicate writing byte data to UART Tx FIFO is done.
+                WR_DONE: u1,
+                ///  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.
+                SERIAL_IN_EP_DATA_FREE: u1,
+                ///  1'b1: Indicate there is data in UART Rx FIFO.
+                SERIAL_OUT_EP_DATA_AVAIL: u1,
+                padding: u29,
+            }),
+            ///  USB_DEVICE_INT_RAW_REG.
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.
+                JTAG_IN_FLUSH_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when SOF frame is received.
+                SOF_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.
+                SERIAL_OUT_RECV_PKT_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
+                SERIAL_IN_EMPTY_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when pid error is detected.
+                PID_ERR_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when CRC5 error is detected.
+                CRC5_ERR_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when CRC16 error is detected.
+                CRC16_ERR_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when stuff error is detected.
+                STUFF_ERR_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.
+                IN_TOKEN_REC_IN_EP1_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when usb bus reset is detected.
+                USB_BUS_RESET_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.
+                OUT_EP1_ZERO_PAYLOAD_INT_RAW: u1,
+                ///  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.
+                OUT_EP2_ZERO_PAYLOAD_INT_RAW: u1,
+                padding: u20,
+            }),
+            ///  USB_DEVICE_INT_ST_REG.
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+                JTAG_IN_FLUSH_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
+                SOF_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+                SERIAL_OUT_RECV_PKT_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+                SERIAL_IN_EMPTY_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
+                PID_ERR_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+                CRC5_ERR_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+                CRC16_ERR_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+                STUFF_ERR_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+                IN_TOKEN_REC_IN_EP1_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+                USB_BUS_RESET_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP1_ZERO_PAYLOAD_INT_ST: u1,
+                ///  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP2_ZERO_PAYLOAD_INT_ST: u1,
+                padding: u20,
+            }),
+            ///  USB_DEVICE_INT_ENA_REG.
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+                JTAG_IN_FLUSH_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
+                SOF_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+                SERIAL_OUT_RECV_PKT_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+                SERIAL_IN_EMPTY_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
+                PID_ERR_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
+                CRC5_ERR_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
+                CRC16_ERR_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
+                STUFF_ERR_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
+                IN_TOKEN_REC_IN_EP1_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+                USB_BUS_RESET_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP1_ZERO_PAYLOAD_INT_ENA: u1,
+                ///  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP2_ZERO_PAYLOAD_INT_ENA: u1,
+                padding: u20,
+            }),
+            ///  USB_DEVICE_INT_CLR_REG.
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
+                JTAG_IN_FLUSH_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
+                SOF_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
+                SERIAL_OUT_RECV_PKT_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
+                SERIAL_IN_EMPTY_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
+                PID_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
+                CRC5_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
+                CRC16_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
+                STUFF_ERR_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
+                IN_TOKEN_REC_IN_EP1_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
+                USB_BUS_RESET_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP1_ZERO_PAYLOAD_INT_CLR: u1,
+                ///  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
+                OUT_EP2_ZERO_PAYLOAD_INT_CLR: u1,
+                padding: u20,
+            }),
+            ///  USB_DEVICE_CONF0_REG.
+            CONF0: mmio.Mmio(packed struct(u32) {
+                ///  Select internal/external PHY
+                PHY_SEL: u1,
+                ///  Enable software control USB D+ D- exchange
+                EXCHG_PINS_OVERRIDE: u1,
+                ///  USB D+ D- exchange
+                EXCHG_PINS: u1,
+                ///  Control single-end input high threshold,1.76V to 2V, step 80mV
+                VREFH: u2,
+                ///  Control single-end input low threshold,0.8V to 1.04V, step 80mV
+                VREFL: u2,
+                ///  Enable software control input threshold
+                VREF_OVERRIDE: u1,
+                ///  Enable software control USB D+ D- pullup pulldown
+                PAD_PULL_OVERRIDE: u1,
+                ///  Control USB D+ pull up.
+                DP_PULLUP: u1,
+                ///  Control USB D+ pull down.
+                DP_PULLDOWN: u1,
+                ///  Control USB D- pull up.
+                DM_PULLUP: u1,
+                ///  Control USB D- pull down.
+                DM_PULLDOWN: u1,
+                ///  Control pull up value.
+                PULLUP_VALUE: u1,
+                ///  Enable USB pad function.
+                USB_PAD_ENABLE: u1,
+                padding: u17,
+            }),
+            ///  USB_DEVICE_TEST_REG.
+            TEST: mmio.Mmio(packed struct(u32) {
+                ///  Enable test of the USB pad
+                ENABLE: u1,
+                ///  USB pad oen in test
+                USB_OE: u1,
+                ///  USB D+ tx value in test
+                TX_DP: u1,
+                ///  USB D- tx value in test
+                TX_DM: u1,
+                padding: u28,
+            }),
+            ///  USB_DEVICE_JFIFO_ST_REG.
+            JFIFO_ST: mmio.Mmio(packed struct(u32) {
+                ///  JTAT in fifo counter.
+                IN_FIFO_CNT: u2,
+                ///  1: JTAG in fifo is empty.
+                IN_FIFO_EMPTY: u1,
+                ///  1: JTAG in fifo is full.
+                IN_FIFO_FULL: u1,
+                ///  JTAT out fifo counter.
+                OUT_FIFO_CNT: u2,
+                ///  1: JTAG out fifo is empty.
+                OUT_FIFO_EMPTY: u1,
+                ///  1: JTAG out fifo is full.
+                OUT_FIFO_FULL: u1,
+                ///  Write 1 to reset JTAG in fifo.
+                IN_FIFO_RESET: u1,
+                ///  Write 1 to reset JTAG out fifo.
+                OUT_FIFO_RESET: u1,
+                padding: u22,
+            }),
+            ///  USB_DEVICE_FRAM_NUM_REG.
+            FRAM_NUM: mmio.Mmio(packed struct(u32) {
+                ///  Frame index of received SOF frame.
+                SOF_FRAME_INDEX: u11,
+                padding: u21,
+            }),
+            ///  USB_DEVICE_IN_EP0_ST_REG.
+            IN_EP0_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of IN Endpoint 0.
+                IN_EP0_STATE: u2,
+                ///  Write data address of IN endpoint 0.
+                IN_EP0_WR_ADDR: u7,
+                ///  Read data address of IN endpoint 0.
+                IN_EP0_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_IN_EP1_ST_REG.
+            IN_EP1_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of IN Endpoint 1.
+                IN_EP1_STATE: u2,
+                ///  Write data address of IN endpoint 1.
+                IN_EP1_WR_ADDR: u7,
+                ///  Read data address of IN endpoint 1.
+                IN_EP1_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_IN_EP2_ST_REG.
+            IN_EP2_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of IN Endpoint 2.
+                IN_EP2_STATE: u2,
+                ///  Write data address of IN endpoint 2.
+                IN_EP2_WR_ADDR: u7,
+                ///  Read data address of IN endpoint 2.
+                IN_EP2_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_IN_EP3_ST_REG.
+            IN_EP3_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of IN Endpoint 3.
+                IN_EP3_STATE: u2,
+                ///  Write data address of IN endpoint 3.
+                IN_EP3_WR_ADDR: u7,
+                ///  Read data address of IN endpoint 3.
+                IN_EP3_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_OUT_EP0_ST_REG.
+            OUT_EP0_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of OUT Endpoint 0.
+                OUT_EP0_STATE: u2,
+                ///  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
+                OUT_EP0_WR_ADDR: u7,
+                ///  Read data address of OUT endpoint 0.
+                OUT_EP0_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_OUT_EP1_ST_REG.
+            OUT_EP1_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of OUT Endpoint 1.
+                OUT_EP1_STATE: u2,
+                ///  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
+                OUT_EP1_WR_ADDR: u7,
+                ///  Read data address of OUT endpoint 1.
+                OUT_EP1_RD_ADDR: u7,
+                ///  Data count in OUT endpoint 1 when one packet is received.
+                OUT_EP1_REC_DATA_CNT: u7,
+                padding: u9,
+            }),
+            ///  USB_DEVICE_OUT_EP2_ST_REG.
+            OUT_EP2_ST: mmio.Mmio(packed struct(u32) {
+                ///  State of OUT Endpoint 2.
+                OUT_EP2_STATE: u2,
+                ///  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
+                OUT_EP2_WR_ADDR: u7,
+                ///  Read data address of OUT endpoint 2.
+                OUT_EP2_RD_ADDR: u7,
+                padding: u16,
+            }),
+            ///  USB_DEVICE_MISC_CONF_REG.
+            MISC_CONF: mmio.Mmio(packed struct(u32) {
+                ///  1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
+                CLK_EN: u1,
+                padding: u31,
+            }),
+            ///  USB_DEVICE_MEM_CONF_REG.
+            MEM_CONF: mmio.Mmio(packed struct(u32) {
+                ///  1: power down usb memory.
+                USB_MEM_PD: u1,
+                ///  1: Force clock on for usb memory.
+                USB_MEM_CLK_EN: u1,
+                padding: u30,
+            }),
+            reserved128: [52]u8,
+            ///  USB_DEVICE_DATE_REG.
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  register version.
+                DATE: u32,
+            }),
+        };
+
+        ///  Universal Host Controller Interface
+        pub const UHCI0 = extern struct {
+            ///  a
+            CONF0: mmio.Mmio(packed struct(u32) {
+                ///  Write 1, then write 0 to this bit to reset decode state machine.
+                TX_RST: u1,
+                ///  Write 1, then write 0 to this bit to reset encode state machine.
+                RX_RST: u1,
+                ///  Set this bit to link up HCI and UART0.
+                UART0_CE: u1,
+                ///  Set this bit to link up HCI and UART1.
+                UART1_CE: u1,
+                reserved5: u1,
+                ///  Set this bit to separate the data frame using a special char.
+                SEPER_EN: u1,
+                ///  Set this bit to encode the data packet with a formatting header.
+                HEAD_EN: u1,
+                ///  Set this bit to enable UHCI to receive the 16 bit CRC.
+                CRC_REC_EN: u1,
+                ///  If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.
+                UART_IDLE_EOF_EN: u1,
+                ///  If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.
+                LEN_EOF_EN: u1,
+                ///  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.
+                ENCODE_CRC_EN: u1,
+                ///  1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.
+                CLK_EN: u1,
+                ///  If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.
+                UART_RX_BRK_EOF_EN: u1,
+                padding: u19,
+            }),
+            ///  a
+            INT_RAW: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_START_INT_RAW: u1,
+                ///  a
+                TX_START_INT_RAW: u1,
+                ///  a
+                RX_HUNG_INT_RAW: u1,
+                ///  a
+                TX_HUNG_INT_RAW: u1,
+                ///  a
+                SEND_S_REG_Q_INT_RAW: u1,
+                ///  a
+                SEND_A_REG_Q_INT_RAW: u1,
+                ///  This is the interrupt raw bit. Triggered when there are some errors in EOF in the
+                OUT_EOF_INT_RAW: u1,
+                ///  Soft control int raw bit.
+                APP_CTRL0_INT_RAW: u1,
+                ///  Soft control int raw bit.
+                APP_CTRL1_INT_RAW: u1,
+                padding: u23,
+            }),
+            ///  a
+            INT_ST: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_START_INT_ST: u1,
+                ///  a
+                TX_START_INT_ST: u1,
+                ///  a
+                RX_HUNG_INT_ST: u1,
+                ///  a
+                TX_HUNG_INT_ST: u1,
+                ///  a
+                SEND_S_REG_Q_INT_ST: u1,
+                ///  a
+                SEND_A_REG_Q_INT_ST: u1,
+                ///  a
+                OUTLINK_EOF_ERR_INT_ST: u1,
+                ///  a
+                APP_CTRL0_INT_ST: u1,
+                ///  a
+                APP_CTRL1_INT_ST: u1,
+                padding: u23,
+            }),
+            ///  a
+            INT_ENA: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_START_INT_ENA: u1,
+                ///  a
+                TX_START_INT_ENA: u1,
+                ///  a
+                RX_HUNG_INT_ENA: u1,
+                ///  a
+                TX_HUNG_INT_ENA: u1,
+                ///  a
+                SEND_S_REG_Q_INT_ENA: u1,
+                ///  a
+                SEND_A_REG_Q_INT_ENA: u1,
+                ///  a
+                OUTLINK_EOF_ERR_INT_ENA: u1,
+                ///  a
+                APP_CTRL0_INT_ENA: u1,
+                ///  a
+                APP_CTRL1_INT_ENA: u1,
+                padding: u23,
+            }),
+            ///  a
+            INT_CLR: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_START_INT_CLR: u1,
+                ///  a
+                TX_START_INT_CLR: u1,
+                ///  a
+                RX_HUNG_INT_CLR: u1,
+                ///  a
+                TX_HUNG_INT_CLR: u1,
+                ///  a
+                SEND_S_REG_Q_INT_CLR: u1,
+                ///  a
+                SEND_A_REG_Q_INT_CLR: u1,
+                ///  a
+                OUTLINK_EOF_ERR_INT_CLR: u1,
+                ///  a
+                APP_CTRL0_INT_CLR: u1,
+                ///  a
+                APP_CTRL1_INT_CLR: u1,
+                padding: u23,
+            }),
+            ///  a
+            CONF1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                CHECK_SUM_EN: u1,
+                ///  a
+                CHECK_SEQ_EN: u1,
+                ///  a
+                CRC_DISABLE: u1,
+                ///  a
+                SAVE_HEAD: u1,
+                ///  a
+                TX_CHECK_SUM_RE: u1,
+                ///  a
+                TX_ACK_NUM_RE: u1,
+                reserved7: u1,
+                ///  a
+                WAIT_SW_START: u1,
+                ///  a
+                SW_START: u1,
+                padding: u23,
+            }),
+            ///  a
+            STATE0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_ERR_CAUSE: u3,
+                ///  a
+                DECODE_STATE: u3,
+                padding: u26,
+            }),
+            ///  a
+            STATE1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                ENCODE_STATE: u3,
+                padding: u29,
+            }),
+            ///  a
+            ESCAPE_CONF: mmio.Mmio(packed struct(u32) {
+                ///  a
+                TX_C0_ESC_EN: u1,
+                ///  a
+                TX_DB_ESC_EN: u1,
+                ///  a
+                TX_11_ESC_EN: u1,
+                ///  a
+                TX_13_ESC_EN: u1,
+                ///  a
+                RX_C0_ESC_EN: u1,
+                ///  a
+                RX_DB_ESC_EN: u1,
+                ///  a
+                RX_11_ESC_EN: u1,
+                ///  a
+                RX_13_ESC_EN: u1,
+                padding: u24,
+            }),
+            ///  a
+            HUNG_CONF: mmio.Mmio(packed struct(u32) {
+                ///  a
+                TXFIFO_TIMEOUT: u8,
+                ///  a
+                TXFIFO_TIMEOUT_SHIFT: u3,
+                ///  a
+                TXFIFO_TIMEOUT_ENA: u1,
+                ///  a
+                RXFIFO_TIMEOUT: u8,
+                ///  a
+                RXFIFO_TIMEOUT_SHIFT: u3,
+                ///  a
+                RXFIFO_TIMEOUT_ENA: u1,
+                padding: u8,
+            }),
+            ///  a
+            ACK_NUM: mmio.Mmio(packed struct(u32) {
+                ///  a
+                ACK_NUM: u3,
+                ///  a
+                LOAD: u1,
+                padding: u28,
+            }),
+            ///  a
+            RX_HEAD: mmio.Mmio(packed struct(u32) {
+                ///  a
+                RX_HEAD: u32,
+            }),
+            ///  a
+            QUICK_SENT: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SINGLE_SEND_NUM: u3,
+                ///  a
+                SINGLE_SEND_EN: u1,
+                ///  a
+                ALWAYS_SEND_NUM: u3,
+                ///  a
+                ALWAYS_SEND_EN: u1,
+                padding: u24,
+            }),
+            ///  a
+            REG_Q0_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q0_WORD0: u32,
+            }),
+            ///  a
+            REG_Q0_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q0_WORD1: u32,
+            }),
+            ///  a
+            REG_Q1_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q1_WORD0: u32,
+            }),
+            ///  a
+            REG_Q1_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q1_WORD1: u32,
+            }),
+            ///  a
+            REG_Q2_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q2_WORD0: u32,
+            }),
+            ///  a
+            REG_Q2_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q2_WORD1: u32,
+            }),
+            ///  a
+            REG_Q3_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q3_WORD0: u32,
+            }),
+            ///  a
+            REG_Q3_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q3_WORD1: u32,
+            }),
+            ///  a
+            REG_Q4_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q4_WORD0: u32,
+            }),
+            ///  a
+            REG_Q4_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q4_WORD1: u32,
+            }),
+            ///  a
+            REG_Q5_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q5_WORD0: u32,
+            }),
+            ///  a
+            REG_Q5_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q5_WORD1: u32,
+            }),
+            ///  a
+            REG_Q6_WORD0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q6_WORD0: u32,
+            }),
+            ///  a
+            REG_Q6_WORD1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEND_Q6_WORD1: u32,
+            }),
+            ///  a
+            ESC_CONF0: mmio.Mmio(packed struct(u32) {
+                ///  a
+                SEPER_CHAR: u8,
+                ///  a
+                SEPER_ESC_CHAR0: u8,
+                ///  a
+                SEPER_ESC_CHAR1: u8,
+                padding: u8,
+            }),
+            ///  a
+            ESC_CONF1: mmio.Mmio(packed struct(u32) {
+                ///  a
+                ESC_SEQ0: u8,
+                ///  a
+                ESC_SEQ0_CHAR0: u8,
+                ///  a
+                ESC_SEQ0_CHAR1: u8,
+                padding: u8,
+            }),
+            ///  a
+            ESC_CONF2: mmio.Mmio(packed struct(u32) {
+                ///  a
+                ESC_SEQ1: u8,
+                ///  a
+                ESC_SEQ1_CHAR0: u8,
+                ///  a
+                ESC_SEQ1_CHAR1: u8,
+                padding: u8,
+            }),
+            ///  a
+            ESC_CONF3: mmio.Mmio(packed struct(u32) {
+                ///  a
+                ESC_SEQ2: u8,
+                ///  a
+                ESC_SEQ2_CHAR0: u8,
+                ///  a
+                ESC_SEQ2_CHAR1: u8,
+                padding: u8,
+            }),
+            ///  a
+            PKT_THRES: mmio.Mmio(packed struct(u32) {
+                ///  a
+                PKT_THRS: u13,
+                padding: u19,
+            }),
+            ///  a
+            DATE: mmio.Mmio(packed struct(u32) {
+                ///  a
+                DATE: u32,
+            }),
+        };
+    };
+};
diff --git a/src/cpus.zig b/src/cpus.zig
new file mode 100644
index 000000000..b087d90a9
--- /dev/null
+++ b/src/cpus.zig
@@ -0,0 +1,23 @@
+const std = @import("std");
+const microzig = @import("../deps/microzig/build.zig");
+
+fn root_dir() []const u8 {
+    return std.fs.path.dirname(@src().file) orelse unreachable;
+}
+
+pub const esp32_c3 = microzig.Cpu{
+    .name = "Espressif RISC-V",
+    .source = .{
+        .path = root_dir() ++ "/cpus/espressif-riscv.zig",
+    },
+    .target = std.zig.CrossTarget{
+        .cpu_arch = .riscv32,
+        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
+        .cpu_features_add = std.Target.riscv.featureSet(&.{
+            std.Target.riscv.Feature.c,
+            std.Target.riscv.Feature.m,
+        }),
+        .os_tag = .freestanding,
+        .abi = .eabi,
+    },
+};
diff --git a/src/package/esp32-c3.zig b/src/cpus/espressif-riscv.zig
similarity index 72%
rename from src/package/esp32-c3.zig
rename to src/cpus/espressif-riscv.zig
index 0ab49440d..e20072daa 100644
--- a/src/package/esp32-c3.zig
+++ b/src/cpus/espressif-riscv.zig
@@ -1,7 +1,41 @@
 const std = @import("std");
 const microzig = @import("microzig");
+const root = @import("root");
 
-pub const registers = @import("registers.zig").registers;
+pub const StatusRegister = enum(u8) {
+    // machine information
+    mvendorid,
+    marchid,
+    mimpid,
+    mhartid,
+
+    // machine trap setup
+    mstatus,
+    misa,
+    mtvec,
+};
+
+pub inline fn setStatusBit(comptime reg: StatusRegister, bits: u32) void {
+    asm volatile ("csrrs zero, " ++ @tagName(reg) ++ ", %[value]"
+        :
+        : [value] "r" (bits),
+    );
+}
+
+pub inline fn clearStatusBit(comptime reg: StatusRegister, bits: u32) void {
+    asm volatile ("csrrc zero, " ++ @tagName(reg) ++ ", %[value]"
+        :
+        : [value] "r" (bits),
+    );
+}
+
+pub inline fn cli() void {
+    clearStatusBit(.mstatus, 0x08);
+}
+
+pub inline fn sei() void {
+    setStatusBit(.mstatus, 0x08);
+}
 
 pub const startup_logic = struct {
     comptime {
@@ -35,7 +69,7 @@ pub const startup_logic = struct {
         );
         asm volatile ("la gp, __global_pointer$");
         microzig.cpu.setStatusBit(.mtvec, microzig.config.end_of_stack);
-        microzig.initializeSystemMemories();
+        root.initialize_system_memories();
         microzig_main();
     }
 
diff --git a/src/example/blinky.zig b/src/example/blinky.zig
index 0518c5334..5ee1eefc5 100644
--- a/src/example/blinky.zig
+++ b/src/example/blinky.zig
@@ -1,23 +1,28 @@
 const std = @import("std");
 const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+const TIMG0 = peripherals.TIMG0;
+const RTC_CNTL = peripherals.RTC_CNTL;
+const INTERRUPT_CORE0 = peripherals.INTERRUPT_CORE0;
+const GPIO = peripherals.GPIO;
 
 const dogfood: u32 = 0x50D83AA1;
 const super_dogfood: u32 = 0x8F1D312A;
 
 pub fn main() !void {
-    microzig.chip.registers.TIMG0.WDTWPROTECT.raw = dogfood;
-    microzig.chip.registers.TIMG0.WDTCONFIG0.raw = 0;
-    microzig.chip.registers.TIMG0.WDTWPROTECT.raw = 0;
+    TIMG0.WDTWPROTECT.raw = dogfood;
+    TIMG0.WDTCONFIG0.raw = 0;
+    TIMG0.WDTWPROTECT.raw = 0;
 
-    microzig.chip.registers.RTC_CNTL.WDTWPROTECT.raw = dogfood;
-    microzig.chip.registers.RTC_CNTL.WDTCONFIG0.raw = 0;
-    microzig.chip.registers.RTC_CNTL.WDTWPROTECT.raw = 0;
+    RTC_CNTL.WDTWPROTECT.raw = dogfood;
+    RTC_CNTL.WDTCONFIG0.raw = 0;
+    RTC_CNTL.WDTWPROTECT.raw = 0;
 
-    microzig.chip.registers.RTC_CNTL.SWD_WPROTECT.raw = super_dogfood;
-    microzig.chip.registers.RTC_CNTL.SWD_CONF.modify(.{ .SWD_DISABLE = 1 });
-    microzig.chip.registers.RTC_CNTL.SWD_WPROTECT.raw = 0;
+    RTC_CNTL.SWD_WPROTECT.raw = super_dogfood;
+    RTC_CNTL.SWD_CONF.modify(.{ .SWD_DISABLE = 1 });
+    RTC_CNTL.SWD_WPROTECT.raw = 0;
 
-    microzig.chip.registers.INTERRUPT_CORE0.CPU_INT_ENABLE.* = 0;
+    INTERRUPT_CORE0.CPU_INT_ENABLE.raw = 0;
 
     microzig.hal.gpio.init(LED_R_PIN, .{
         .direction = .output,
@@ -35,15 +40,15 @@ pub fn main() !void {
     microzig.hal.uart.write(0, "Hello from Zig!\r\n");
 
     while (true) {
-        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
         microzig.hal.uart.write(0, "R");
-        microzig.debug.busySleep(1_000_000);
-        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
+        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
         microzig.hal.uart.write(0, "G");
-        microzig.debug.busySleep(1_000_000);
-        microzig.chip.registers.GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
+        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
         microzig.hal.uart.write(0, "B");
-        microzig.debug.busySleep(1_000_000);
+        microzig.core.experimental.debug.busy_sleep(1_000_000);
     }
 }
 
diff --git a/src/hal/root.zig b/src/hals/ESP32_C3.zig
similarity index 57%
rename from src/hal/root.zig
rename to src/hals/ESP32_C3.zig
index d87dab85e..516ed1524 100644
--- a/src/hal/root.zig
+++ b/src/hals/ESP32_C3.zig
@@ -1,16 +1,9 @@
 const std = @import("std");
 const microzig = @import("microzig");
-const regz = microzig.chip.registers;
+const peripherals = microzig.chip.peripherals;
+const GPIO = peripherals.GPIO;
 
 pub const gpio = struct {
-    fn getRegNamed(comptime fld: []const u8) @TypeOf(@field(regz.GPIO, fld)) {
-        return @field(regz.GPIO, fld);
-    }
-
-    fn getReg(comptime template: []const u8, comptime pin: comptime_int) @TypeOf(@field(regz.GPIO, std.fmt.comptimePrint(template, .{pin}))) {
-        return getRegNamed(comptime std.fmt.comptimePrint(template, .{pin}));
-    }
-
     fn assertRange(comptime p: comptime_int) void {
         if (p < 0 or p >= 21)
             @compileError(std.fmt.comptimePrint("GPIO {} does not exist. GPIO pins can be between 0 and 21", .{p}));
@@ -19,29 +12,29 @@ pub const gpio = struct {
     pub const Config = struct {
         function: u8 = 0x80,
         invert_function: bool = false,
-        direction: microzig.gpio.Direction,
+        direction: microzig.core.experimental.gpio.Direction,
         direct_io: bool = false,
         invert_direct_io: bool = false,
     };
 
     pub fn init(comptime pin: comptime_int, comptime config: Config) void {
         assertRange(pin);
-        getReg("FUNC{}_OUT_SEL_CFG", pin).modify(.{
+        GPIO.FUNC_OUT_SEL_CFG[pin].modify(.{
             .OUT_SEL = config.function,
             .INV_SEL = @boolToInt(config.invert_function),
             .OEN_SEL = @boolToInt(config.direct_io),
             .OEN_INV_SEL = @boolToInt(config.invert_direct_io),
         });
         switch (config.direction) {
-            .input => microzig.chip.registers.GPIO.ENABLE.raw &= ~(@as(u32, 1) << pin),
-            .output => microzig.chip.registers.GPIO.ENABLE.raw |= (@as(u32, 1) << pin),
+            .input => GPIO.ENABLE.raw &= ~(@as(u32, 1) << pin),
+            .output => GPIO.ENABLE.raw |= (@as(u32, 1) << pin),
         }
     }
 };
 
 pub const uart = struct {
-    fn reg(comptime index: comptime_int) @TypeOf(@field(regz, std.fmt.comptimePrint("UART{}", .{index}))) {
-        return @field(regz, std.fmt.comptimePrint("UART{}", .{index}));
+    fn reg(comptime index: comptime_int) @TypeOf(@field(peripherals, std.fmt.comptimePrint("UART{}", .{index}))) {
+        return @field(peripherals, std.fmt.comptimePrint("UART{}", .{index}));
     }
 
     pub fn write(comptime index: comptime_int, slice: []const u8) void {
diff --git a/src/package/espressif-riscv.zig b/src/package/espressif-riscv.zig
deleted file mode 100644
index 06d7bc444..000000000
--- a/src/package/espressif-riscv.zig
+++ /dev/null
@@ -1,39 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-pub const StatusRegister = enum(u8) {
-    // machine information
-    mvendorid,
-    marchid,
-    mimpid,
-    mhartid,
-
-    // machine trap setup
-    mstatus,
-    misa,
-    mtvec,
-};
-
-pub inline fn setStatusBit(comptime reg: StatusRegister, bits: u32) void {
-    asm volatile ("csrrs zero, " ++ @tagName(reg) ++ ", %[value]"
-        :
-        : [value] "r" (bits),
-    );
-}
-
-pub inline fn clearStatusBit(comptime reg: StatusRegister, bits: u32) void {
-    asm volatile ("csrrc zero, " ++ @tagName(reg) ++ ", %[value]"
-        :
-        : [value] "r" (bits),
-    );
-}
-
-pub inline fn cli() void {
-    clearStatusBit(.mstatus, 0x08);
-}
-
-pub inline fn sei() void {
-    setStatusBit(.mstatus, 0x08);
-}
-
-pub const startup_logic = microzig.chip.startup_logic;
diff --git a/src/package/registers.zig b/src/package/registers.zig
deleted file mode 100644
index 77bed3f3d..000000000
--- a/src/package/registers.zig
+++ /dev/null
@@ -1,37956 +0,0 @@
-// this file was generated by regz: https://github.com/ZigEmbeddedGroup/regz
-// commit: 62e33d0e2175e4c1621e1dbf9f6ac3ec18f6ba38
-//
-// vendor: ESPRESSIF SYSTEMS (SHANGHAI) CO., LTD.
-// device: ESP32-C3
-// cpu: RV32IMC
-
-pub const registers = struct {
-    /// AES (Advanced Encryption Standard) Accelerator
-    pub const AES = struct {
-        pub const base_address = 0x6003a000;
-
-        /// address: 0x6003a000
-        /// Key material key_0 configure register
-        pub const KEY_0 = @intToPtr(*volatile u32, base_address + 0x0);
-
-        /// address: 0x6003a004
-        /// Key material key_1 configure register
-        pub const KEY_1 = @intToPtr(*volatile u32, base_address + 0x4);
-
-        /// address: 0x6003a008
-        /// Key material key_2 configure register
-        pub const KEY_2 = @intToPtr(*volatile u32, base_address + 0x8);
-
-        /// address: 0x6003a00c
-        /// Key material key_3 configure register
-        pub const KEY_3 = @intToPtr(*volatile u32, base_address + 0xc);
-
-        /// address: 0x6003a010
-        /// Key material key_4 configure register
-        pub const KEY_4 = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x6003a014
-        /// Key material key_5 configure register
-        pub const KEY_5 = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x6003a018
-        /// Key material key_6 configure register
-        pub const KEY_6 = @intToPtr(*volatile u32, base_address + 0x18);
-
-        /// address: 0x6003a01c
-        /// Key material key_7 configure register
-        pub const KEY_7 = @intToPtr(*volatile u32, base_address + 0x1c);
-
-        /// address: 0x6003a020
-        /// source text material text_in_0 configure register
-        pub const TEXT_IN_0 = @intToPtr(*volatile u32, base_address + 0x20);
-
-        /// address: 0x6003a024
-        /// source text material text_in_1 configure register
-        pub const TEXT_IN_1 = @intToPtr(*volatile u32, base_address + 0x24);
-
-        /// address: 0x6003a028
-        /// source text material text_in_2 configure register
-        pub const TEXT_IN_2 = @intToPtr(*volatile u32, base_address + 0x28);
-
-        /// address: 0x6003a02c
-        /// source text material text_in_3 configure register
-        pub const TEXT_IN_3 = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x6003a030
-        /// result text material text_out_0 configure register
-        pub const TEXT_OUT_0 = @intToPtr(*volatile u32, base_address + 0x30);
-
-        /// address: 0x6003a034
-        /// result text material text_out_1 configure register
-        pub const TEXT_OUT_1 = @intToPtr(*volatile u32, base_address + 0x34);
-
-        /// address: 0x6003a038
-        /// result text material text_out_2 configure register
-        pub const TEXT_OUT_2 = @intToPtr(*volatile u32, base_address + 0x38);
-
-        /// address: 0x6003a03c
-        /// result text material text_out_3 configure register
-        pub const TEXT_OUT_3 = @intToPtr(*volatile u32, base_address + 0x3c);
-
-        /// address: 0x6003a040
-        /// AES Mode register
-        pub const MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x40);
-
-        /// address: 0x6003a044
-        /// AES Endian configure register
-        pub const ENDIAN = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x44);
-
-        /// address: 0x6003a048
-        /// AES trigger register
-        pub const TRIGGER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x48);
-
-        /// address: 0x6003a04c
-        /// AES state register
-        pub const STATE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x4c);
-
-        /// address: 0x6003a050
-        /// The memory that stores initialization vector
-        pub const IV_MEM = @intToPtr(*volatile [16]u8, base_address + 0x50);
-
-        /// address: 0x6003a060
-        /// The memory that stores GCM hash subkey
-        pub const H_MEM = @intToPtr(*volatile [16]u8, base_address + 0x60);
-
-        /// address: 0x6003a070
-        /// The memory that stores J0
-        pub const J0_MEM = @intToPtr(*volatile [16]u8, base_address + 0x70);
-
-        /// address: 0x6003a080
-        /// The memory that stores T0
-        pub const T0_MEM = @intToPtr(*volatile [16]u8, base_address + 0x80);
-
-        /// address: 0x6003a090
-        /// DMA-AES working mode register
-        pub const DMA_ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x90);
-
-        /// address: 0x6003a094
-        /// AES cipher block mode register
-        pub const BLOCK_MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x94);
-
-        /// address: 0x6003a098
-        /// AES block number register
-        pub const BLOCK_NUM = @intToPtr(*volatile u32, base_address + 0x98);
-
-        /// address: 0x6003a09c
-        /// Standard incrementing function configure register
-        pub const INC_SEL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x9c);
-
-        /// address: 0x6003a0a0
-        /// Additional Authential Data block number register
-        pub const AAD_BLOCK_NUM = @intToPtr(*volatile u32, base_address + 0xa0);
-
-        /// address: 0x6003a0a4
-        /// AES remainder bit number register
-        pub const REMAINDER_BIT_NUM = @intToPtr(*volatile MmioInt(32, u7), base_address + 0xa4);
-
-        /// address: 0x6003a0a8
-        /// AES continue register
-        pub const CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xa8);
-
-        /// address: 0x6003a0ac
-        /// AES Interrupt clear register
-        pub const INT_CLEAR = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xac);
-
-        /// address: 0x6003a0b0
-        /// AES Interrupt enable register
-        pub const INT_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xb0);
-
-        /// address: 0x6003a0b4
-        /// AES version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0xb4);
-
-        /// address: 0x6003a0b8
-        /// AES-DMA exit config
-        pub const DMA_EXIT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xb8);
-    };
-
-    /// Advanced Peripheral Bus Controller
-    pub const APB_CTRL = struct {
-        pub const base_address = 0x60026000;
-
-        /// address: 0x60026000
-        /// APB_CTRL_SYSCLK_CONF_REG
-        pub const SYSCLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_pre_div_cnt
-            PRE_DIV_CNT: u10,
-            /// reg_clk_320m_en
-            CLK_320M_EN: u1,
-            /// reg_clk_en
-            CLK_EN: u1,
-            /// reg_rst_tick_cnt
-            RST_TICK_CNT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60026004
-        /// APB_CTRL_TICK_CONF_REG
-        pub const TICK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_xtal_tick_num
-            XTAL_TICK_NUM: u8,
-            /// reg_ck8m_tick_num
-            CK8M_TICK_NUM: u8,
-            /// reg_tick_enable
-            TICK_ENABLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60026008
-        /// APB_CTRL_CLK_OUT_EN_REG
-        pub const CLK_OUT_EN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_clk20_oen
-            CLK20_OEN: u1,
-            /// reg_clk22_oen
-            CLK22_OEN: u1,
-            /// reg_clk44_oen
-            CLK44_OEN: u1,
-            /// reg_clk_bb_oen
-            CLK_BB_OEN: u1,
-            /// reg_clk80_oen
-            CLK80_OEN: u1,
-            /// reg_clk160_oen
-            CLK160_OEN: u1,
-            /// reg_clk_320m_oen
-            CLK_320M_OEN: u1,
-            /// reg_clk_adc_inf_oen
-            CLK_ADC_INF_OEN: u1,
-            /// reg_clk_dac_cpu_oen
-            CLK_DAC_CPU_OEN: u1,
-            /// reg_clk40x_bb_oen
-            CLK40X_BB_OEN: u1,
-            /// reg_clk_xtal_oen
-            CLK_XTAL_OEN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6002600c
-        /// APB_CTRL_WIFI_BB_CFG_REG
-        pub const WIFI_BB_CFG = @intToPtr(*volatile u32, base_address + 0xc);
-
-        /// address: 0x60026010
-        /// APB_CTRL_WIFI_BB_CFG_2_REG
-        pub const WIFI_BB_CFG_2 = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x60026014
-        /// APB_CTRL_WIFI_CLK_EN_REG
-        pub const WIFI_CLK_EN = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x60026018
-        /// APB_CTRL_WIFI_RST_EN_REG
-        pub const WIFI_RST_EN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wifi_rst
-            WIFI_RST: u32,
-        }), base_address + 0x18);
-
-        /// address: 0x6002601c
-        /// APB_CTRL_HOST_INF_SEL_REG
-        pub const HOST_INF_SEL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_peri_io_swap
-            PERI_IO_SWAP: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60026020
-        /// APB_CTRL_EXT_MEM_PMS_LOCK_REG
-        pub const EXT_MEM_PMS_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x20);
-
-        /// address: 0x60026028
-        /// APB_CTRL_FLASH_ACE0_ATTR_REG
-        pub const FLASH_ACE0_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x28);
-
-        /// address: 0x6002602c
-        /// APB_CTRL_FLASH_ACE1_ATTR_REG
-        pub const FLASH_ACE1_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x2c);
-
-        /// address: 0x60026030
-        /// APB_CTRL_FLASH_ACE2_ATTR_REG
-        pub const FLASH_ACE2_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x30);
-
-        /// address: 0x60026034
-        /// APB_CTRL_FLASH_ACE3_ATTR_REG
-        pub const FLASH_ACE3_ATTR = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x34);
-
-        /// address: 0x60026038
-        /// APB_CTRL_FLASH_ACE0_ADDR_REG
-        pub const FLASH_ACE0_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_flash_ace0_addr_s
-            S: u32,
-        }), base_address + 0x38);
-
-        /// address: 0x6002603c
-        /// APB_CTRL_FLASH_ACE1_ADDR_REG
-        pub const FLASH_ACE1_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_flash_ace1_addr_s
-            S: u32,
-        }), base_address + 0x3c);
-
-        /// address: 0x60026040
-        /// APB_CTRL_FLASH_ACE2_ADDR_REG
-        pub const FLASH_ACE2_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_flash_ace2_addr_s
-            S: u32,
-        }), base_address + 0x40);
-
-        /// address: 0x60026044
-        /// APB_CTRL_FLASH_ACE3_ADDR_REG
-        pub const FLASH_ACE3_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_flash_ace3_addr_s
-            S: u32,
-        }), base_address + 0x44);
-
-        /// address: 0x60026048
-        /// APB_CTRL_FLASH_ACE0_SIZE_REG
-        pub const FLASH_ACE0_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x48);
-
-        /// address: 0x6002604c
-        /// APB_CTRL_FLASH_ACE1_SIZE_REG
-        pub const FLASH_ACE1_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x4c);
-
-        /// address: 0x60026050
-        /// APB_CTRL_FLASH_ACE2_SIZE_REG
-        pub const FLASH_ACE2_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x50);
-
-        /// address: 0x60026054
-        /// APB_CTRL_FLASH_ACE3_SIZE_REG
-        pub const FLASH_ACE3_SIZE = @intToPtr(*volatile MmioInt(32, u13), base_address + 0x54);
-
-        /// address: 0x60026088
-        /// APB_CTRL_SPI_MEM_PMS_CTRL_REG
-        pub const SPI_MEM_PMS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_spi_mem_reject_int
-            SPI_MEM_REJECT_INT: u1,
-            /// reg_spi_mem_reject_clr
-            SPI_MEM_REJECT_CLR: u1,
-            /// reg_spi_mem_reject_cde
-            SPI_MEM_REJECT_CDE: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x6002608c
-        /// APB_CTRL_SPI_MEM_REJECT_ADDR_REG
-        pub const SPI_MEM_REJECT_ADDR = @intToPtr(*volatile u32, base_address + 0x8c);
-
-        /// address: 0x60026090
-        /// APB_CTRL_SDIO_CTRL_REG
-        pub const SDIO_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_sdio_win_access_en
-            SDIO_WIN_ACCESS_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x60026094
-        /// APB_CTRL_REDCY_SIG0_REG
-        pub const REDCY_SIG0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_redcy_sig0
-            REDCY_SIG0: u31,
-            /// reg_redcy_andor
-            REDCY_ANDOR: u1,
-        }), base_address + 0x94);
-
-        /// address: 0x60026098
-        /// APB_CTRL_REDCY_SIG1_REG
-        pub const REDCY_SIG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_redcy_sig1
-            REDCY_SIG1: u31,
-            /// reg_redcy_nandor
-            REDCY_NANDOR: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x6002609c
-        /// APB_CTRL_FRONT_END_MEM_PD_REG
-        pub const FRONT_END_MEM_PD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_agc_mem_force_pu
-            AGC_MEM_FORCE_PU: u1,
-            /// reg_agc_mem_force_pd
-            AGC_MEM_FORCE_PD: u1,
-            /// reg_pbus_mem_force_pu
-            PBUS_MEM_FORCE_PU: u1,
-            /// reg_pbus_mem_force_pd
-            PBUS_MEM_FORCE_PD: u1,
-            /// reg_dc_mem_force_pu
-            DC_MEM_FORCE_PU: u1,
-            /// reg_dc_mem_force_pd
-            DC_MEM_FORCE_PD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x9c);
-
-        /// address: 0x600260a0
-        /// APB_CTRL_RETENTION_CTRL_REG
-        pub const RETENTION_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_retention_link_addr
-            RETENTION_LINK_ADDR: u27,
-            /// reg_nobypass_cpu_iso_rst
-            NOBYPASS_CPU_ISO_RST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x600260a4
-        /// APB_CTRL_CLKGATE_FORCE_ON_REG
-        pub const CLKGATE_FORCE_ON = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rom_clkgate_force_on
-            ROM_CLKGATE_FORCE_ON: u2,
-            /// reg_sram_clkgate_force_on
-            SRAM_CLKGATE_FORCE_ON: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600260a8
-        /// APB_CTRL_MEM_POWER_DOWN_REG
-        pub const MEM_POWER_DOWN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rom_power_down
-            ROM_POWER_DOWN: u2,
-            /// reg_sram_power_down
-            SRAM_POWER_DOWN: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600260ac
-        /// APB_CTRL_MEM_POWER_UP_REG
-        pub const MEM_POWER_UP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rom_power_up
-            ROM_POWER_UP: u2,
-            /// reg_sram_power_up
-            SRAM_POWER_UP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600260b0
-        /// APB_CTRL_RND_DATA_REG
-        pub const RND_DATA = @intToPtr(*volatile u32, base_address + 0xb0);
-
-        /// address: 0x600260b4
-        /// APB_CTRL_PERI_BACKUP_CONFIG_REG
-        pub const PERI_BACKUP_CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// reg_peri_backup_flow_err
-            PERI_BACKUP_FLOW_ERR: u2,
-            reserved1: u1,
-            /// reg_peri_backup_burst_limit
-            PERI_BACKUP_BURST_LIMIT: u5,
-            /// reg_peri_backup_tout_thres
-            PERI_BACKUP_TOUT_THRES: u10,
-            /// reg_peri_backup_size
-            PERI_BACKUP_SIZE: u10,
-            /// reg_peri_backup_start
-            PERI_BACKUP_START: u1,
-            /// reg_peri_backup_to_mem
-            PERI_BACKUP_TO_MEM: u1,
-            /// reg_peri_backup_ena
-            PERI_BACKUP_ENA: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600260b8
-        /// APB_CTRL_PERI_BACKUP_APB_ADDR_REG
-        pub const PERI_BACKUP_APB_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_backup_apb_start_addr
-            BACKUP_APB_START_ADDR: u32,
-        }), base_address + 0xb8);
-
-        /// address: 0x600260bc
-        /// APB_CTRL_PERI_BACKUP_MEM_ADDR_REG
-        pub const PERI_BACKUP_MEM_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_backup_mem_start_addr
-            BACKUP_MEM_START_ADDR: u32,
-        }), base_address + 0xbc);
-
-        /// address: 0x600260c0
-        /// APB_CTRL_PERI_BACKUP_INT_RAW_REG
-        pub const PERI_BACKUP_INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_peri_backup_done_int_raw
-            PERI_BACKUP_DONE_INT_RAW: u1,
-            /// reg_peri_backup_err_int_raw
-            PERI_BACKUP_ERR_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600260c4
-        /// APB_CTRL_PERI_BACKUP_INT_ST_REG
-        pub const PERI_BACKUP_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_peri_backup_done_int_st
-            PERI_BACKUP_DONE_INT_ST: u1,
-            /// reg_peri_backup_err_int_st
-            PERI_BACKUP_ERR_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xc4);
-
-        /// address: 0x600260c8
-        /// APB_CTRL_PERI_BACKUP_INT_ENA_REG
-        pub const PERI_BACKUP_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_peri_backup_done_int_ena
-            PERI_BACKUP_DONE_INT_ENA: u1,
-            /// reg_peri_backup_err_int_ena
-            PERI_BACKUP_ERR_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600260d0
-        /// APB_CTRL_PERI_BACKUP_INT_CLR_REG
-        pub const PERI_BACKUP_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_peri_backup_done_int_clr
-            PERI_BACKUP_DONE_INT_CLR: u1,
-            /// reg_peri_backup_err_int_clr
-            PERI_BACKUP_ERR_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x600263fc
-        /// APB_CTRL_DATE_REG
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x3fc);
-    };
-
-    /// Successive Approximation Register Analog to Digital Converter
-    pub const APB_SARADC = struct {
-        pub const base_address = 0x60040000;
-
-        /// address: 0x60040000
-        /// digital saradc configure register
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// select software enable saradc sample
-            SARADC_START_FORCE: u1,
-            /// software enable saradc sample
-            SARADC_START: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// SAR clock gated
-            SARADC_SAR_CLK_GATED: u1,
-            /// SAR clock divider
-            SARADC_SAR_CLK_DIV: u8,
-            /// 0 ~ 15 means length 1 ~ 16
-            SARADC_SAR_PATT_LEN: u3,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// clear the pointer of pattern table for DIG ADC1 CTRL
-            SARADC_SAR_PATT_P_CLEAR: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// force option to xpd sar blocks
-            SARADC_XPD_SAR_FORCE: u2,
-            reserved12: u1,
-            /// wait arbit signal stable after sar_done
-            SARADC_WAIT_ARB_CYCLE: u2,
-        }), base_address + 0x0);
-
-        /// address: 0x60040004
-        /// digital saradc configure register
-        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// enable max meas num
-            SARADC_MEAS_NUM_LIMIT: u1,
-            /// max conversion number
-            SARADC_MAX_MEAS_NUM: u8,
-            /// 1: data to DIG ADC1 CTRL is inverted, otherwise not
-            SARADC_SAR1_INV: u1,
-            /// 1: data to DIG ADC2 CTRL is inverted, otherwise not
-            SARADC_SAR2_INV: u1,
-            reserved0: u1,
-            /// to set saradc timer target
-            SARADC_TIMER_TARGET: u12,
-            /// to enable saradc timer trigger
-            SARADC_TIMER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60040008
-        /// digital saradc configure register
-        pub const FILTER_CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// Factor of saradc filter1
-            APB_SARADC_FILTER_FACTOR1: u3,
-            /// Factor of saradc filter0
-            APB_SARADC_FILTER_FACTOR0: u3,
-        }), base_address + 0x8);
-
-        /// address: 0x6004000c
-        /// digital saradc configure register
-        pub const FSM_WAIT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc_xpd_wait
-            SARADC_XPD_WAIT: u8,
-            /// saradc_rstb_wait
-            SARADC_RSTB_WAIT: u8,
-            /// saradc_standby_wait
-            SARADC_STANDBY_WAIT: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60040010
-        /// digital saradc configure register
-        pub const SAR1_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc1 status about data and channel
-            SARADC_SAR1_STATUS: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x60040014
-        /// digital saradc configure register
-        pub const SAR2_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc2 status about data and channel
-            SARADC_SAR2_STATUS: u32,
-        }), base_address + 0x14);
-
-        /// address: 0x60040018
-        /// digital saradc configure register
-        pub const SAR_PATT_TAB1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// item 0 ~ 3 for pattern table 1 (each item one byte)
-            SARADC_SAR_PATT_TAB1: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6004001c
-        /// digital saradc configure register
-        pub const SAR_PATT_TAB2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Item 4 ~ 7 for pattern table 1 (each item one byte)
-            SARADC_SAR_PATT_TAB2: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60040020
-        /// digital saradc configure register
-        pub const ONETIME_SAMPLE = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            /// configure onetime atten
-            SARADC_ONETIME_ATTEN: u2,
-            /// configure onetime channel
-            SARADC_ONETIME_CHANNEL: u4,
-            /// trigger adc onetime sample
-            SARADC_ONETIME_START: u1,
-            /// enable adc2 onetime sample
-            SARADC2_ONETIME_SAMPLE: u1,
-            /// enable adc1 onetime sample
-            SARADC1_ONETIME_SAMPLE: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60040024
-        /// digital saradc configure register
-        pub const ARB_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            /// adc2 arbiter force to enableapb controller
-            ADC_ARB_APB_FORCE: u1,
-            /// adc2 arbiter force to enable rtc controller
-            ADC_ARB_RTC_FORCE: u1,
-            /// adc2 arbiter force to enable wifi controller
-            ADC_ARB_WIFI_FORCE: u1,
-            /// adc2 arbiter force grant
-            ADC_ARB_GRANT_FORCE: u1,
-            /// Set adc2 arbiterapb priority
-            ADC_ARB_APB_PRIORITY: u2,
-            /// Set adc2 arbiter rtc priority
-            ADC_ARB_RTC_PRIORITY: u2,
-            /// Set adc2 arbiter wifi priority
-            ADC_ARB_WIFI_PRIORITY: u2,
-            /// adc2 arbiter uses fixed priority
-            ADC_ARB_FIX_PRIORITY: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60040028
-        /// digital saradc configure register
-        pub const FILTER_CTRL0 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// configure filter1 to adc channel
-            APB_SARADC_FILTER_CHANNEL1: u4,
-            /// configure filter0 to adc channel
-            APB_SARADC_FILTER_CHANNEL0: u4,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            /// enable apb_adc1_filter
-            APB_SARADC_FILTER_RESET: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6004002c
-        /// digital saradc configure register
-        pub const SAR1DATA_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc1 data
-            APB_SARADC1_DATA: u17,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60040030
-        /// digital saradc configure register
-        pub const SAR2DATA_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc2 data
-            APB_SARADC2_DATA: u17,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60040034
-        /// digital saradc configure register
-        pub const THRES0_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// configure thres0 to adc channel
-            APB_SARADC_THRES0_CHANNEL: u4,
-            reserved0: u1,
-            /// saradc thres0 monitor thres
-            APB_SARADC_THRES0_HIGH: u13,
-            /// saradc thres0 monitor thres
-            APB_SARADC_THRES0_LOW: u13,
-            padding0: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60040038
-        /// digital saradc configure register
-        pub const THRES1_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// configure thres1 to adc channel
-            APB_SARADC_THRES1_CHANNEL: u4,
-            reserved0: u1,
-            /// saradc thres1 monitor thres
-            APB_SARADC_THRES1_HIGH: u13,
-            /// saradc thres1 monitor thres
-            APB_SARADC_THRES1_LOW: u13,
-            padding0: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6004003c
-        /// digital saradc configure register
-        pub const THRES_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            /// enable thres to all channel
-            APB_SARADC_THRES_ALL_EN: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// enable thres1
-            APB_SARADC_THRES1_EN: u1,
-            /// enable thres0
-            APB_SARADC_THRES0_EN: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60040040
-        /// digital saradc int register
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// saradc thres1 low interrupt enable
-            APB_SARADC_THRES1_LOW_INT_ENA: u1,
-            /// saradc thres0 low interrupt enable
-            APB_SARADC_THRES0_LOW_INT_ENA: u1,
-            /// saradc thres1 high interrupt enable
-            APB_SARADC_THRES1_HIGH_INT_ENA: u1,
-            /// saradc thres0 high interrupt enable
-            APB_SARADC_THRES0_HIGH_INT_ENA: u1,
-            /// saradc2 done interrupt enable
-            APB_SARADC2_DONE_INT_ENA: u1,
-            /// saradc1 done interrupt enable
-            APB_SARADC1_DONE_INT_ENA: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60040044
-        /// digital saradc int register
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// saradc thres1 low interrupt raw
-            APB_SARADC_THRES1_LOW_INT_RAW: u1,
-            /// saradc thres0 low interrupt raw
-            APB_SARADC_THRES0_LOW_INT_RAW: u1,
-            /// saradc thres1 high interrupt raw
-            APB_SARADC_THRES1_HIGH_INT_RAW: u1,
-            /// saradc thres0 high interrupt raw
-            APB_SARADC_THRES0_HIGH_INT_RAW: u1,
-            /// saradc2 done interrupt raw
-            APB_SARADC2_DONE_INT_RAW: u1,
-            /// saradc1 done interrupt raw
-            APB_SARADC1_DONE_INT_RAW: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60040048
-        /// digital saradc int register
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// saradc thres1 low interrupt state
-            APB_SARADC_THRES1_LOW_INT_ST: u1,
-            /// saradc thres0 low interrupt state
-            APB_SARADC_THRES0_LOW_INT_ST: u1,
-            /// saradc thres1 high interrupt state
-            APB_SARADC_THRES1_HIGH_INT_ST: u1,
-            /// saradc thres0 high interrupt state
-            APB_SARADC_THRES0_HIGH_INT_ST: u1,
-            /// saradc2 done interrupt state
-            APB_SARADC2_DONE_INT_ST: u1,
-            /// saradc1 done interrupt state
-            APB_SARADC1_DONE_INT_ST: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6004004c
-        /// digital saradc int register
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// saradc thres1 low interrupt clear
-            APB_SARADC_THRES1_LOW_INT_CLR: u1,
-            /// saradc thres0 low interrupt clear
-            APB_SARADC_THRES0_LOW_INT_CLR: u1,
-            /// saradc thres1 high interrupt clear
-            APB_SARADC_THRES1_HIGH_INT_CLR: u1,
-            /// saradc thres0 high interrupt clear
-            APB_SARADC_THRES0_HIGH_INT_CLR: u1,
-            /// saradc2 done interrupt clear
-            APB_SARADC2_DONE_INT_CLR: u1,
-            /// saradc1 done interrupt clear
-            APB_SARADC1_DONE_INT_CLR: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60040050
-        /// digital saradc configure register
-        pub const DMA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the dma_in_suc_eof gen when sample cnt = spi_eof_num
-            APB_ADC_EOF_NUM: u16,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// reset_apb_adc_state
-            APB_ADC_RESET_FSM: u1,
-            /// enable apb_adc use spi_dma
-            APB_ADC_TRANS: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60040054
-        /// digital saradc configure register
-        pub const CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Integral I2S clock divider value
-            CLKM_DIV_NUM: u8,
-            /// Fractional clock divider numerator value
-            CLKM_DIV_B: u6,
-            /// Fractional clock divider denominator value
-            CLKM_DIV_A: u6,
-            /// reg clk en
-            CLK_EN: u1,
-            /// Set this bit to enable clk_apll
-            CLK_SEL: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60040058
-        /// digital tsens configure register
-        pub const APB_TSENS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// temperature sensor data out
-            TSENS_OUT: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            /// invert temperature sensor data
-            TSENS_IN_INV: u1,
-            /// temperature sensor clock divider
-            TSENS_CLK_DIV: u8,
-            /// temperature sensor power up
-            TSENS_PU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6004005c
-        /// digital tsens configure register
-        pub const TSENS_CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the time that power up tsens need wait
-            TSENS_XPD_WAIT: u12,
-            /// force power up tsens
-            TSENS_XPD_FORCE: u2,
-            /// inv tsens clk
-            TSENS_CLK_INV: u1,
-            /// tsens clk select
-            TSENS_CLK_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60040060
-        /// digital saradc configure register
-        pub const CALI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// saradc cali factor
-            APB_SARADC_CALI_CFG: u17,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x600403fc
-        /// version
-        pub const CTRL_DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// version
-            DATE: u32,
-        }), base_address + 0x3fc);
-    };
-
-    /// Debug Assist
-    pub const ASSIST_DEBUG = struct {
-        pub const base_address = 0x600ce000;
-
-        /// address: 0x600ce000
-        /// ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG
-        pub const C0RE_0_MONTR_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_area_dram0_0_rd_ena
-            CORE_0_AREA_DRAM0_0_RD_ENA: u1,
-            /// reg_core_0_area_dram0_0_wr_ena
-            CORE_0_AREA_DRAM0_0_WR_ENA: u1,
-            /// reg_core_0_area_dram0_1_rd_ena
-            CORE_0_AREA_DRAM0_1_RD_ENA: u1,
-            /// reg_core_0_area_dram0_1_wr_ena
-            CORE_0_AREA_DRAM0_1_WR_ENA: u1,
-            /// reg_core_0_area_pif_0_rd_ena
-            CORE_0_AREA_PIF_0_RD_ENA: u1,
-            /// reg_core_0_area_pif_0_wr_ena
-            CORE_0_AREA_PIF_0_WR_ENA: u1,
-            /// reg_core_0_area_pif_1_rd_ena
-            CORE_0_AREA_PIF_1_RD_ENA: u1,
-            /// reg_core_0_area_pif_1_wr_ena
-            CORE_0_AREA_PIF_1_WR_ENA: u1,
-            /// reg_core_0_sp_spill_min_ena
-            CORE_0_SP_SPILL_MIN_ENA: u1,
-            /// reg_core_0_sp_spill_max_ena
-            CORE_0_SP_SPILL_MAX_ENA: u1,
-            /// reg_core_0_iram0_exception_monitor_ena
-            CORE_0_IRAM0_EXCEPTION_MONITOR_ENA: u1,
-            /// reg_core_0_dram0_exception_monitor_ena
-            CORE_0_DRAM0_EXCEPTION_MONITOR_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x600ce004
-        /// ASSIST_DEBUG_CORE_0_INTR_RAW_REG
-        pub const CORE_0_INTR_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_area_dram0_0_rd_raw
-            CORE_0_AREA_DRAM0_0_RD_RAW: u1,
-            /// reg_core_0_area_dram0_0_wr_raw
-            CORE_0_AREA_DRAM0_0_WR_RAW: u1,
-            /// reg_core_0_area_dram0_1_rd_raw
-            CORE_0_AREA_DRAM0_1_RD_RAW: u1,
-            /// reg_core_0_area_dram0_1_wr_raw
-            CORE_0_AREA_DRAM0_1_WR_RAW: u1,
-            /// reg_core_0_area_pif_0_rd_raw
-            CORE_0_AREA_PIF_0_RD_RAW: u1,
-            /// reg_core_0_area_pif_0_wr_raw
-            CORE_0_AREA_PIF_0_WR_RAW: u1,
-            /// reg_core_0_area_pif_1_rd_raw
-            CORE_0_AREA_PIF_1_RD_RAW: u1,
-            /// reg_core_0_area_pif_1_wr_raw
-            CORE_0_AREA_PIF_1_WR_RAW: u1,
-            /// reg_core_0_sp_spill_min_raw
-            CORE_0_SP_SPILL_MIN_RAW: u1,
-            /// reg_core_0_sp_spill_max_raw
-            CORE_0_SP_SPILL_MAX_RAW: u1,
-            /// reg_core_0_iram0_exception_monitor_raw
-            CORE_0_IRAM0_EXCEPTION_MONITOR_RAW: u1,
-            /// reg_core_0_dram0_exception_monitor_raw
-            CORE_0_DRAM0_EXCEPTION_MONITOR_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x600ce008
-        /// ASSIST_DEBUG_CORE_0_INTR_ENA_REG
-        pub const CORE_0_INTR_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_area_dram0_0_rd_intr_ena
-            CORE_0_AREA_DRAM0_0_RD_INTR_ENA: u1,
-            /// reg_core_0_area_dram0_0_wr_intr_ena
-            CORE_0_AREA_DRAM0_0_WR_INTR_ENA: u1,
-            /// reg_core_0_area_dram0_1_rd_intr_ena
-            CORE_0_AREA_DRAM0_1_RD_INTR_ENA: u1,
-            /// reg_core_0_area_dram0_1_wr_intr_ena
-            CORE_0_AREA_DRAM0_1_WR_INTR_ENA: u1,
-            /// reg_core_0_area_pif_0_rd_intr_ena
-            CORE_0_AREA_PIF_0_RD_INTR_ENA: u1,
-            /// reg_core_0_area_pif_0_wr_intr_ena
-            CORE_0_AREA_PIF_0_WR_INTR_ENA: u1,
-            /// reg_core_0_area_pif_1_rd_intr_ena
-            CORE_0_AREA_PIF_1_RD_INTR_ENA: u1,
-            /// reg_core_0_area_pif_1_wr_intr_ena
-            CORE_0_AREA_PIF_1_WR_INTR_ENA: u1,
-            /// reg_core_0_sp_spill_min_intr_ena
-            CORE_0_SP_SPILL_MIN_INTR_ENA: u1,
-            /// reg_core_0_sp_spill_max_intr_ena
-            CORE_0_SP_SPILL_MAX_INTR_ENA: u1,
-            /// reg_core_0_iram0_exception_monitor_ena
-            CORE_0_IRAM0_EXCEPTION_MONITOR_RLS: u1,
-            /// reg_core_0_dram0_exception_monitor_ena
-            CORE_0_DRAM0_EXCEPTION_MONITOR_RLS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x600ce00c
-        /// ASSIST_DEBUG_CORE_0_INTR_CLR_REG
-        pub const CORE_0_INTR_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_area_dram0_0_rd_clr
-            CORE_0_AREA_DRAM0_0_RD_CLR: u1,
-            /// reg_core_0_area_dram0_0_wr_clr
-            CORE_0_AREA_DRAM0_0_WR_CLR: u1,
-            /// reg_core_0_area_dram0_1_rd_clr
-            CORE_0_AREA_DRAM0_1_RD_CLR: u1,
-            /// reg_core_0_area_dram0_1_wr_clr
-            CORE_0_AREA_DRAM0_1_WR_CLR: u1,
-            /// reg_core_0_area_pif_0_rd_clr
-            CORE_0_AREA_PIF_0_RD_CLR: u1,
-            /// reg_core_0_area_pif_0_wr_clr
-            CORE_0_AREA_PIF_0_WR_CLR: u1,
-            /// reg_core_0_area_pif_1_rd_clr
-            CORE_0_AREA_PIF_1_RD_CLR: u1,
-            /// reg_core_0_area_pif_1_wr_clr
-            CORE_0_AREA_PIF_1_WR_CLR: u1,
-            /// reg_core_0_sp_spill_min_clr
-            CORE_0_SP_SPILL_MIN_CLR: u1,
-            /// reg_core_0_sp_spill_max_clr
-            CORE_0_SP_SPILL_MAX_CLR: u1,
-            /// reg_core_0_iram0_exception_monitor_clr
-            CORE_0_IRAM0_EXCEPTION_MONITOR_CLR: u1,
-            /// reg_core_0_dram0_exception_monitor_clr
-            CORE_0_DRAM0_EXCEPTION_MONITOR_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x600ce010
-        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG
-        pub const CORE_0_AREA_DRAM0_0_MIN = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x600ce014
-        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG
-        pub const CORE_0_AREA_DRAM0_0_MAX = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x600ce018
-        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG
-        pub const CORE_0_AREA_DRAM0_1_MIN = @intToPtr(*volatile u32, base_address + 0x18);
-
-        /// address: 0x600ce01c
-        /// ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG
-        pub const CORE_0_AREA_DRAM0_1_MAX = @intToPtr(*volatile u32, base_address + 0x1c);
-
-        /// address: 0x600ce020
-        /// ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG
-        pub const CORE_0_AREA_PIF_0_MIN = @intToPtr(*volatile u32, base_address + 0x20);
-
-        /// address: 0x600ce024
-        /// ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG
-        pub const CORE_0_AREA_PIF_0_MAX = @intToPtr(*volatile u32, base_address + 0x24);
-
-        /// address: 0x600ce028
-        /// ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG
-        pub const CORE_0_AREA_PIF_1_MIN = @intToPtr(*volatile u32, base_address + 0x28);
-
-        /// address: 0x600ce02c
-        /// ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG
-        pub const CORE_0_AREA_PIF_1_MAX = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x600ce030
-        /// ASSIST_DEBUG_CORE_0_AREA_PC_REG
-        pub const CORE_0_AREA_PC = @intToPtr(*volatile u32, base_address + 0x30);
-
-        /// address: 0x600ce034
-        /// ASSIST_DEBUG_CORE_0_AREA_SP_REG
-        pub const CORE_0_AREA_SP = @intToPtr(*volatile u32, base_address + 0x34);
-
-        /// address: 0x600ce038
-        /// ASSIST_DEBUG_CORE_0_SP_MIN_REG
-        pub const CORE_0_SP_MIN = @intToPtr(*volatile u32, base_address + 0x38);
-
-        /// address: 0x600ce03c
-        /// ASSIST_DEBUG_CORE_0_SP_MAX_REG
-        pub const CORE_0_SP_MAX = @intToPtr(*volatile u32, base_address + 0x3c);
-
-        /// address: 0x600ce040
-        /// ASSIST_DEBUG_CORE_0_SP_PC_REG
-        pub const CORE_0_SP_PC = @intToPtr(*volatile u32, base_address + 0x40);
-
-        /// address: 0x600ce044
-        /// ASSIST_DEBUG_CORE_0_RCD_EN_REG
-        pub const CORE_0_RCD_EN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_rcd_recorden
-            CORE_0_RCD_RECORDEN: u1,
-            /// reg_core_0_rcd_pdebugen
-            CORE_0_RCD_PDEBUGEN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x600ce048
-        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG
-        pub const CORE_0_RCD_PDEBUGPC = @intToPtr(*volatile u32, base_address + 0x48);
-
-        /// address: 0x600ce04c
-        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
-        pub const CORE_0_RCD_PDEBUGSP = @intToPtr(*volatile u32, base_address + 0x4c);
-
-        /// address: 0x600ce050
-        /// ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
-        pub const CORE_0_IRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_iram0_recording_addr_0
-            CORE_0_IRAM0_RECORDING_ADDR_0: u24,
-            /// reg_core_0_iram0_recording_wr_0
-            CORE_0_IRAM0_RECORDING_WR_0: u1,
-            /// reg_core_0_iram0_recording_loadstore_0
-            CORE_0_IRAM0_RECORDING_LOADSTORE_0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x600ce054
-        /// ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG
-        pub const CORE_0_IRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_iram0_recording_addr_1
-            CORE_0_IRAM0_RECORDING_ADDR_1: u24,
-            /// reg_core_0_iram0_recording_wr_1
-            CORE_0_IRAM0_RECORDING_WR_1: u1,
-            /// reg_core_0_iram0_recording_loadstore_1
-            CORE_0_IRAM0_RECORDING_LOADSTORE_1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x600ce058
-        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG
-        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_dram0_recording_addr_0
-            CORE_0_DRAM0_RECORDING_ADDR_0: u24,
-            /// reg_core_0_dram0_recording_wr_0
-            CORE_0_DRAM0_RECORDING_WR_0: u1,
-            /// reg_core_0_dram0_recording_byteen_0
-            CORE_0_DRAM0_RECORDING_BYTEEN_0: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x600ce05c
-        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
-        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_dram0_recording_pc_0
-            CORE_0_DRAM0_RECORDING_PC_0: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x600ce060
-        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
-        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_dram0_recording_addr_1
-            CORE_0_DRAM0_RECORDING_ADDR_1: u24,
-            /// reg_core_0_dram0_recording_wr_1
-            CORE_0_DRAM0_RECORDING_WR_1: u1,
-            /// reg_core_0_dram0_recording_byteen_1
-            CORE_0_DRAM0_RECORDING_BYTEEN_1: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x600ce064
-        /// ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG
-        pub const CORE_0_DRAM0_EXCEPTION_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_dram0_recording_pc_1
-            CORE_0_DRAM0_RECORDING_PC_1: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x600ce068
-        /// ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG
-        pub const CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_x_iram0_dram0_limit_cycle_0
-            CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x600ce06c
-        /// ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG
-        pub const CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_x_iram0_dram0_limit_cycle_1
-            CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x600ce070
-        /// ASSIST_DEBUG_LOG_SETTING
-        pub const LOG_SETTING = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_log_ena
-            LOG_ENA: u3,
-            /// reg_log_mode
-            LOG_MODE: u4,
-            /// reg_log_mem_loop_enable
-            LOG_MEM_LOOP_ENABLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x600ce074
-        /// ASSIST_DEBUG_LOG_DATA_0_REG
-        pub const LOG_DATA_0 = @intToPtr(*volatile u32, base_address + 0x74);
-
-        /// address: 0x600ce078
-        /// ASSIST_DEBUG_LOG_DATA_MASK_REG
-        pub const LOG_DATA_MASK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_log_data_size
-            LOG_DATA_SIZE: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x600ce07c
-        /// ASSIST_DEBUG_LOG_MIN_REG
-        pub const LOG_MIN = @intToPtr(*volatile u32, base_address + 0x7c);
-
-        /// address: 0x600ce080
-        /// ASSIST_DEBUG_LOG_MAX_REG
-        pub const LOG_MAX = @intToPtr(*volatile u32, base_address + 0x80);
-
-        /// address: 0x600ce084
-        /// ASSIST_DEBUG_LOG_MEM_START_REG
-        pub const LOG_MEM_START = @intToPtr(*volatile u32, base_address + 0x84);
-
-        /// address: 0x600ce088
-        /// ASSIST_DEBUG_LOG_MEM_END_REG
-        pub const LOG_MEM_END = @intToPtr(*volatile u32, base_address + 0x88);
-
-        /// address: 0x600ce08c
-        /// ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG
-        pub const LOG_MEM_WRITING_ADDR = @intToPtr(*volatile u32, base_address + 0x8c);
-
-        /// address: 0x600ce090
-        /// ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG
-        pub const LOG_MEM_FULL_FLAG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_log_mem_full_flag
-            LOG_MEM_FULL_FLAG: u1,
-            /// reg_clr_log_mem_full_flag
-            CLR_LOG_MEM_FULL_FLAG: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x600ce094
-        /// ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION
-        pub const C0RE_0_LASTPC_BEFORE_EXCEPTION = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_lastpc_before_exc
-            CORE_0_LASTPC_BEFORE_EXC: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x600ce098
-        /// ASSIST_DEBUG_C0RE_0_DEBUG_MODE
-        pub const C0RE_0_DEBUG_MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core_0_debug_mode
-            CORE_0_DEBUG_MODE: u1,
-            /// reg_core_0_debug_module_active
-            CORE_0_DEBUG_MODULE_ACTIVE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x600ce1fc
-        /// ASSIST_DEBUG_DATE_REG
-        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_assist_debug_date
-            ASSIST_DEBUG_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x1fc);
-    };
-
-    /// DMA (Direct Memory Access) Controller
-    pub const DMA = struct {
-        pub const base_address = 0x6003f000;
-
-        /// address: 0x6003f000
-        /// DMA_INT_RAW_CH0_REG.
-        pub const INT_RAW_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 0.
-            IN_DONE_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 0. For UHCI0, the raw
-            /// interrupt bit turns to high level when the last data pointed by one inlink
-            /// descriptor has been received and no data error is detected for Rx channel 0.
-            IN_SUC_EOF_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data error is detected only in
-            /// the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals,
-            /// this raw interrupt is reserved.
-            IN_ERR_EOF_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been transmitted to peripherals for Tx channel 0.
-            OUT_DONE_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been read from memory for Tx channel 0.
-            OUT_EOF_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting inlink descriptor
-            /// error, including owner error, the second and third word error of inlink
-            /// descriptor for Rx channel 0.
-            IN_DSCR_ERR_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting outlink descriptor
-            /// error, including owner error, the second and third word error of outlink
-            /// descriptor for Tx channel 0.
-            OUT_DSCR_ERR_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
-            /// full and receiving data is not completed, but there is no more inlink for Rx
-            /// channel 0.
-            IN_DSCR_EMPTY_CH0_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data corresponding a outlink
-            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
-            /// channel 0.
-            OUT_TOTAL_EOF_CH0_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
-            /// overflow.
-            INFIFO_OVF_CH0_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is
-            /// underflow.
-            INFIFO_UDF_CH0_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
-            /// overflow.
-            OUTFIFO_OVF_CH0_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is
-            /// underflow.
-            OUTFIFO_UDF_CH0_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x6003f004
-        /// DMA_INT_ST_CH0_REG.
-        pub const INT_ST_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH0_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH0_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x6003f008
-        /// DMA_INT_ENA_CH0_REG.
-        pub const INT_ENA_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH0_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH0_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6003f00c
-        /// DMA_INT_CLR_CH0_REG.
-        pub const INT_CLR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH0_INT_CLR: u1,
-            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH0_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH0_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH0_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x6003f010
-        /// DMA_INT_RAW_CH1_REG.
-        pub const INT_RAW_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 1.
-            IN_DONE_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 1. For UHCI0, the raw
-            /// interrupt bit turns to high level when the last data pointed by one inlink
-            /// descriptor has been received and no data error is detected for Rx channel 1.
-            IN_SUC_EOF_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data error is detected only in
-            /// the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals,
-            /// this raw interrupt is reserved.
-            IN_ERR_EOF_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been transmitted to peripherals for Tx channel 1.
-            OUT_DONE_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been read from memory for Tx channel 1.
-            OUT_EOF_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting inlink descriptor
-            /// error, including owner error, the second and third word error of inlink
-            /// descriptor for Rx channel 1.
-            IN_DSCR_ERR_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting outlink descriptor
-            /// error, including owner error, the second and third word error of outlink
-            /// descriptor for Tx channel 1.
-            OUT_DSCR_ERR_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
-            /// full and receiving data is not completed, but there is no more inlink for Rx
-            /// channel 1.
-            IN_DSCR_EMPTY_CH1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data corresponding a outlink
-            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
-            /// channel 1.
-            OUT_TOTAL_EOF_CH1_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is
-            /// overflow.
-            INFIFO_OVF_CH1_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is
-            /// underflow.
-            INFIFO_UDF_CH1_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is
-            /// overflow.
-            OUTFIFO_OVF_CH1_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is
-            /// underflow.
-            OUTFIFO_UDF_CH1_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x6003f014
-        /// DMA_INT_ST_CH1_REG.
-        pub const INT_ST_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH1_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH1_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x6003f018
-        /// DMA_INT_ENA_CH1_REG.
-        pub const INT_ENA_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH1_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH1_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6003f01c
-        /// DMA_INT_CLR_CH1_REG.
-        pub const INT_CLR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH1_INT_CLR: u1,
-            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH1_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH1_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH1_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x6003f020
-        /// DMA_INT_RAW_CH2_REG.
-        pub const INT_RAW_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 2.
-            IN_DONE_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// inlink descriptor has been received for Rx channel 2. For UHCI0, the raw
-            /// interrupt bit turns to high level when the last data pointed by one inlink
-            /// descriptor has been received and no data error is detected for Rx channel 2.
-            IN_SUC_EOF_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data error is detected only in
-            /// the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals,
-            /// this raw interrupt is reserved.
-            IN_ERR_EOF_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been transmitted to peripherals for Tx channel 2.
-            OUT_DONE_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when the last data pointed by one
-            /// outlink descriptor has been read from memory for Tx channel 2.
-            OUT_EOF_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting inlink descriptor
-            /// error, including owner error, the second and third word error of inlink
-            /// descriptor for Rx channel 2.
-            IN_DSCR_ERR_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when detecting outlink descriptor
-            /// error, including owner error, the second and third word error of outlink
-            /// descriptor for Tx channel 2.
-            OUT_DSCR_ERR_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when Rx buffer pointed by inlink is
-            /// full and receiving data is not completed, but there is no more inlink for Rx
-            /// channel 2.
-            IN_DSCR_EMPTY_CH2_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when data corresponding a outlink
-            /// (includes one link descriptor or few link descriptors) is transmitted out for Tx
-            /// channel 2.
-            OUT_TOTAL_EOF_CH2_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is
-            /// overflow.
-            INFIFO_OVF_CH2_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is
-            /// underflow.
-            INFIFO_UDF_CH2_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is
-            /// overflow.
-            OUTFIFO_OVF_CH2_INT_RAW: u1,
-            /// This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is
-            /// underflow.
-            OUTFIFO_UDF_CH2_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x6003f024
-        /// DMA_INT_ST_CH2_REG.
-        pub const INT_ST_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH2_INT_ST: u1,
-            /// The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH2_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x6003f028
-        /// DMA_INT_ENA_CH2_REG.
-        pub const INT_ENA_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH2_INT_ENA: u1,
-            /// The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH2_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6003f02c
-        /// DMA_INT_CLR_CH2_REG.
-        pub const INT_CLR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the IN_DONE_CH_INT interrupt.
-            IN_DONE_CH2_INT_CLR: u1,
-            /// Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-            IN_SUC_EOF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-            IN_ERR_EOF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DONE_CH_INT interrupt.
-            OUT_DONE_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUT_EOF_CH_INT interrupt.
-            OUT_EOF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-            IN_DSCR_ERR_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-            OUT_DSCR_ERR_CH2_INT_CLR: u1,
-            /// Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-            IN_DSCR_EMPTY_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-            OUT_TOTAL_EOF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-            INFIFO_OVF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-            INFIFO_UDF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-            OUTFIFO_OVF_CH2_INT_CLR: u1,
-            /// Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-            OUTFIFO_UDF_CH2_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x6003f040
-        /// DMA_AHB_TEST_REG.
-        pub const AHB_TEST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved
-            AHB_TESTMODE: u3,
-            reserved0: u1,
-            /// reserved
-            AHB_TESTADDR: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x6003f044
-        /// DMA_MISC_CONF_REG.
-        pub const MISC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit, then clear this bit to reset the internal ahb FSM.
-            AHBM_RST_INTER: u1,
-            reserved0: u1,
-            /// Set this bit to disable priority arbitration function.
-            ARB_PRI_DIS: u1,
-            /// reg_clk_en
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x6003f048
-        /// DMA_DATE_REG.
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x48);
-
-        /// address: 0x6003f070
-        /// DMA_IN_CONF0_CH0_REG.
-        pub const IN_CONF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
-            IN_RST_CH0: u1,
-            /// reserved
-            IN_LOOP_TEST_CH0: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link
-            /// descriptor when accessing internal SRAM.
-            INDSCR_BURST_EN_CH0: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data
-            /// when accessing internal SRAM.
-            IN_DATA_BURST_EN_CH0: u1,
-            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
-            /// DMA.
-            MEM_TRANS_EN_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x6003f074
-        /// DMA_IN_CONF1_CH0_REG.
-        pub const IN_CONF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            IN_CHECK_OWNER_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x6003f078
-        /// DMA_INFIFO_STATUS_CH0_REG.
-        pub const INFIFO_STATUS_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Rx FIFO full signal for Rx channel 0.
-            INFIFO_FULL_CH0: u1,
-            /// L1 Rx FIFO empty signal for Rx channel 0.
-            INFIFO_EMPTY_CH0: u1,
-            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
-            INFIFO_CNT_CH0: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            IN_REMAIN_UNDER_1B_CH0: u1,
-            /// reserved
-            IN_REMAIN_UNDER_2B_CH0: u1,
-            /// reserved
-            IN_REMAIN_UNDER_3B_CH0: u1,
-            /// reserved
-            IN_REMAIN_UNDER_4B_CH0: u1,
-            /// reserved
-            IN_BUF_HUNGRY_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6003f07c
-        /// DMA_IN_POP_CH0_REG.
-        pub const IN_POP_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data popping from DMA FIFO.
-            INFIFO_RDATA_CH0: u12,
-            /// Set this bit to pop data from DMA FIFO.
-            INFIFO_POP_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x6003f080
-        /// DMA_IN_LINK_CH0_REG.
-        pub const IN_LINK_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first inlink
-            /// descriptor's address.
-            INLINK_ADDR_CH0: u20,
-            /// Set this bit to return to current inlink descriptor's address, when there are
-            /// some errors in current receiving data.
-            INLINK_AUTO_RET_CH0: u1,
-            /// Set this bit to stop dealing with the inlink descriptors.
-            INLINK_STOP_CH0: u1,
-            /// Set this bit to start dealing with the inlink descriptors.
-            INLINK_START_CH0: u1,
-            /// Set this bit to mount a new inlink descriptor.
-            INLINK_RESTART_CH0: u1,
-            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
-            /// is working.
-            INLINK_PARK_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x6003f084
-        /// DMA_IN_STATE_CH0_REG.
-        pub const IN_STATE_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current inlink descriptor's address.
-            INLINK_DSCR_ADDR_CH0: u18,
-            /// reserved
-            IN_DSCR_STATE_CH0: u2,
-            /// reserved
-            IN_STATE_CH0: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x6003f088
-        /// DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
-        pub const IN_SUC_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0x88);
-
-        /// address: 0x6003f08c
-        /// DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
-        pub const IN_ERR_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0x8c);
-
-        /// address: 0x6003f090
-        /// DMA_IN_DSCR_CH0_REG.
-        pub const IN_DSCR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current inlink descriptor x.
-            INLINK_DSCR_CH0: u32,
-        }), base_address + 0x90);
-
-        /// address: 0x6003f094
-        /// DMA_IN_DSCR_BF0_CH0_REG.
-        pub const IN_DSCR_BF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last inlink descriptor x-1.
-            INLINK_DSCR_BF0_CH0: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x6003f098
-        /// DMA_IN_DSCR_BF1_CH0_REG.
-        pub const IN_DSCR_BF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            INLINK_DSCR_BF1_CH0: u32,
-        }), base_address + 0x98);
-
-        /// address: 0x6003f09c
-        /// DMA_IN_PRI_CH0_REG.
-        pub const IN_PRI_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Rx channel 0. The larger of the value, the higher of the
-            /// priority.
-            RX_PRI_CH0: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x9c);
-
-        /// address: 0x6003f0a0
-        /// DMA_IN_PERI_SEL_CH0_REG.
-        pub const IN_PERI_SEL_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Rx channel 0. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_IN_SEL_CH0: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x6003f0d0
-        /// DMA_OUT_CONF0_CH0_REG.
-        pub const OUT_CONF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
-            OUT_RST_CH0: u1,
-            /// reserved
-            OUT_LOOP_TEST_CH0: u1,
-            /// Set this bit to enable automatic outlink-writeback when all the data in tx
-            /// buffer has been transmitted.
-            OUT_AUTO_WRBACK_CH0: u1,
-            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is
-            /// generated when data need to transmit has been popped from FIFO in DMA
-            OUT_EOF_MODE_CH0: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link
-            /// descriptor when accessing internal SRAM.
-            OUTDSCR_BURST_EN_CH0: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting
-            /// data when accessing internal SRAM.
-            OUT_DATA_BURST_EN_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x6003f0d4
-        /// DMA_OUT_CONF1_CH0_REG.
-        pub const OUT_CONF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            OUT_CHECK_OWNER_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0xd4);
-
-        /// address: 0x6003f0d8
-        /// DMA_OUTFIFO_STATUS_CH0_REG.
-        pub const OUTFIFO_STATUS_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Tx FIFO full signal for Tx channel 0.
-            OUTFIFO_FULL_CH0: u1,
-            /// L1 Tx FIFO empty signal for Tx channel 0.
-            OUTFIFO_EMPTY_CH0: u1,
-            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
-            OUTFIFO_CNT_CH0: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_1B_CH0: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_2B_CH0: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_3B_CH0: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_4B_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-        }), base_address + 0xd8);
-
-        /// address: 0x6003f0dc
-        /// DMA_OUT_PUSH_CH0_REG.
-        pub const OUT_PUSH_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data that need to be pushed into DMA FIFO.
-            OUTFIFO_WDATA_CH0: u9,
-            /// Set this bit to push data into DMA FIFO.
-            OUTFIFO_PUSH_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0xdc);
-
-        /// address: 0x6003f0e0
-        /// DMA_OUT_LINK_CH0_REG.
-        pub const OUT_LINK_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first outlink
-            /// descriptor's address.
-            OUTLINK_ADDR_CH0: u20,
-            /// Set this bit to stop dealing with the outlink descriptors.
-            OUTLINK_STOP_CH0: u1,
-            /// Set this bit to start dealing with the outlink descriptors.
-            OUTLINK_START_CH0: u1,
-            /// Set this bit to restart a new outlink from the last address.
-            OUTLINK_RESTART_CH0: u1,
-            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
-            /// FSM is working.
-            OUTLINK_PARK_CH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0xe0);
-
-        /// address: 0x6003f0e4
-        /// DMA_OUT_STATE_CH0_REG.
-        pub const OUT_STATE_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current outlink descriptor's address.
-            OUTLINK_DSCR_ADDR_CH0: u18,
-            /// reserved
-            OUT_DSCR_STATE_CH0: u2,
-            /// reserved
-            OUT_STATE_CH0: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0xe4);
-
-        /// address: 0x6003f0e8
-        /// DMA_OUT_EOF_DES_ADDR_CH0_REG.
-        pub const OUT_EOF_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0xe8);
-
-        /// address: 0x6003f0ec
-        /// DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
-        pub const OUT_EOF_BFR_DES_ADDR_CH0 = @intToPtr(*volatile u32, base_address + 0xec);
-
-        /// address: 0x6003f0f0
-        /// DMA_OUT_DSCR_CH0_REG.
-        pub const OUT_DSCR_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current outlink descriptor y.
-            OUTLINK_DSCR_CH0: u32,
-        }), base_address + 0xf0);
-
-        /// address: 0x6003f0f4
-        /// DMA_OUT_DSCR_BF0_CH0_REG.
-        pub const OUT_DSCR_BF0_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last outlink descriptor y-1.
-            OUTLINK_DSCR_BF0_CH0: u32,
-        }), base_address + 0xf4);
-
-        /// address: 0x6003f0f8
-        /// DMA_OUT_DSCR_BF1_CH0_REG.
-        pub const OUT_DSCR_BF1_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            OUTLINK_DSCR_BF1_CH0: u32,
-        }), base_address + 0xf8);
-
-        /// address: 0x6003f0fc
-        /// DMA_OUT_PRI_CH0_REG.
-        pub const OUT_PRI_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Tx channel 0. The larger of the value, the higher of the
-            /// priority.
-            TX_PRI_CH0: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0xfc);
-
-        /// address: 0x6003f100
-        /// DMA_OUT_PERI_SEL_CH0_REG.
-        pub const OUT_PERI_SEL_CH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Tx channel 0. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_OUT_SEL_CH0: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x6003f130
-        /// DMA_IN_CONF0_CH1_REG.
-        pub const IN_CONF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
-            IN_RST_CH1: u1,
-            /// reserved
-            IN_LOOP_TEST_CH1: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link
-            /// descriptor when accessing internal SRAM.
-            INDSCR_BURST_EN_CH1: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data
-            /// when accessing internal SRAM.
-            IN_DATA_BURST_EN_CH1: u1,
-            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
-            /// DMA.
-            MEM_TRANS_EN_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x130);
-
-        /// address: 0x6003f134
-        /// DMA_IN_CONF1_CH1_REG.
-        pub const IN_CONF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            IN_CHECK_OWNER_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x134);
-
-        /// address: 0x6003f138
-        /// DMA_INFIFO_STATUS_CH1_REG.
-        pub const INFIFO_STATUS_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Rx FIFO full signal for Rx channel 1.
-            INFIFO_FULL_CH1: u1,
-            /// L1 Rx FIFO empty signal for Rx channel 1.
-            INFIFO_EMPTY_CH1: u1,
-            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.
-            INFIFO_CNT_CH1: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            IN_REMAIN_UNDER_1B_CH1: u1,
-            /// reserved
-            IN_REMAIN_UNDER_2B_CH1: u1,
-            /// reserved
-            IN_REMAIN_UNDER_3B_CH1: u1,
-            /// reserved
-            IN_REMAIN_UNDER_4B_CH1: u1,
-            /// reserved
-            IN_BUF_HUNGRY_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x138);
-
-        /// address: 0x6003f13c
-        /// DMA_IN_POP_CH1_REG.
-        pub const IN_POP_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data popping from DMA FIFO.
-            INFIFO_RDATA_CH1: u12,
-            /// Set this bit to pop data from DMA FIFO.
-            INFIFO_POP_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x13c);
-
-        /// address: 0x6003f140
-        /// DMA_IN_LINK_CH1_REG.
-        pub const IN_LINK_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first inlink
-            /// descriptor's address.
-            INLINK_ADDR_CH1: u20,
-            /// Set this bit to return to current inlink descriptor's address, when there are
-            /// some errors in current receiving data.
-            INLINK_AUTO_RET_CH1: u1,
-            /// Set this bit to stop dealing with the inlink descriptors.
-            INLINK_STOP_CH1: u1,
-            /// Set this bit to start dealing with the inlink descriptors.
-            INLINK_START_CH1: u1,
-            /// Set this bit to mount a new inlink descriptor.
-            INLINK_RESTART_CH1: u1,
-            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
-            /// is working.
-            INLINK_PARK_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x140);
-
-        /// address: 0x6003f144
-        /// DMA_IN_STATE_CH1_REG.
-        pub const IN_STATE_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current inlink descriptor's address.
-            INLINK_DSCR_ADDR_CH1: u18,
-            /// reserved
-            IN_DSCR_STATE_CH1: u2,
-            /// reserved
-            IN_STATE_CH1: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x144);
-
-        /// address: 0x6003f148
-        /// DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.
-        pub const IN_SUC_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x148);
-
-        /// address: 0x6003f14c
-        /// DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.
-        pub const IN_ERR_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x14c);
-
-        /// address: 0x6003f150
-        /// DMA_IN_DSCR_CH1_REG.
-        pub const IN_DSCR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current inlink descriptor x.
-            INLINK_DSCR_CH1: u32,
-        }), base_address + 0x150);
-
-        /// address: 0x6003f154
-        /// DMA_IN_DSCR_BF0_CH1_REG.
-        pub const IN_DSCR_BF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last inlink descriptor x-1.
-            INLINK_DSCR_BF0_CH1: u32,
-        }), base_address + 0x154);
-
-        /// address: 0x6003f158
-        /// DMA_IN_DSCR_BF1_CH1_REG.
-        pub const IN_DSCR_BF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            INLINK_DSCR_BF1_CH1: u32,
-        }), base_address + 0x158);
-
-        /// address: 0x6003f15c
-        /// DMA_IN_PRI_CH1_REG.
-        pub const IN_PRI_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Rx channel 1. The larger of the value, the higher of the
-            /// priority.
-            RX_PRI_CH1: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x15c);
-
-        /// address: 0x6003f160
-        /// DMA_IN_PERI_SEL_CH1_REG.
-        pub const IN_PERI_SEL_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Rx channel 1. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_IN_SEL_CH1: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x160);
-
-        /// address: 0x6003f190
-        /// DMA_OUT_CONF0_CH1_REG.
-        pub const OUT_CONF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
-            OUT_RST_CH1: u1,
-            /// reserved
-            OUT_LOOP_TEST_CH1: u1,
-            /// Set this bit to enable automatic outlink-writeback when all the data in tx
-            /// buffer has been transmitted.
-            OUT_AUTO_WRBACK_CH1: u1,
-            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is
-            /// generated when data need to transmit has been popped from FIFO in DMA
-            OUT_EOF_MODE_CH1: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link
-            /// descriptor when accessing internal SRAM.
-            OUTDSCR_BURST_EN_CH1: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting
-            /// data when accessing internal SRAM.
-            OUT_DATA_BURST_EN_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x190);
-
-        /// address: 0x6003f194
-        /// DMA_OUT_CONF1_CH1_REG.
-        pub const OUT_CONF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            OUT_CHECK_OWNER_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x194);
-
-        /// address: 0x6003f198
-        /// DMA_OUTFIFO_STATUS_CH1_REG.
-        pub const OUTFIFO_STATUS_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Tx FIFO full signal for Tx channel 1.
-            OUTFIFO_FULL_CH1: u1,
-            /// L1 Tx FIFO empty signal for Tx channel 1.
-            OUTFIFO_EMPTY_CH1: u1,
-            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.
-            OUTFIFO_CNT_CH1: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_1B_CH1: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_2B_CH1: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_3B_CH1: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_4B_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-        }), base_address + 0x198);
-
-        /// address: 0x6003f19c
-        /// DMA_OUT_PUSH_CH1_REG.
-        pub const OUT_PUSH_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data that need to be pushed into DMA FIFO.
-            OUTFIFO_WDATA_CH1: u9,
-            /// Set this bit to push data into DMA FIFO.
-            OUTFIFO_PUSH_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x19c);
-
-        /// address: 0x6003f1a0
-        /// DMA_OUT_LINK_CH1_REG.
-        pub const OUT_LINK_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first outlink
-            /// descriptor's address.
-            OUTLINK_ADDR_CH1: u20,
-            /// Set this bit to stop dealing with the outlink descriptors.
-            OUTLINK_STOP_CH1: u1,
-            /// Set this bit to start dealing with the outlink descriptors.
-            OUTLINK_START_CH1: u1,
-            /// Set this bit to restart a new outlink from the last address.
-            OUTLINK_RESTART_CH1: u1,
-            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
-            /// FSM is working.
-            OUTLINK_PARK_CH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x1a0);
-
-        /// address: 0x6003f1a4
-        /// DMA_OUT_STATE_CH1_REG.
-        pub const OUT_STATE_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current outlink descriptor's address.
-            OUTLINK_DSCR_ADDR_CH1: u18,
-            /// reserved
-            OUT_DSCR_STATE_CH1: u2,
-            /// reserved
-            OUT_STATE_CH1: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x1a4);
-
-        /// address: 0x6003f1a8
-        /// DMA_OUT_EOF_DES_ADDR_CH1_REG.
-        pub const OUT_EOF_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x1a8);
-
-        /// address: 0x6003f1ac
-        /// DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.
-        pub const OUT_EOF_BFR_DES_ADDR_CH1 = @intToPtr(*volatile u32, base_address + 0x1ac);
-
-        /// address: 0x6003f1b0
-        /// DMA_OUT_DSCR_CH1_REG.
-        pub const OUT_DSCR_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current outlink descriptor y.
-            OUTLINK_DSCR_CH1: u32,
-        }), base_address + 0x1b0);
-
-        /// address: 0x6003f1b4
-        /// DMA_OUT_DSCR_BF0_CH1_REG.
-        pub const OUT_DSCR_BF0_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last outlink descriptor y-1.
-            OUTLINK_DSCR_BF0_CH1: u32,
-        }), base_address + 0x1b4);
-
-        /// address: 0x6003f1b8
-        /// DMA_OUT_DSCR_BF1_CH1_REG.
-        pub const OUT_DSCR_BF1_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            OUTLINK_DSCR_BF1_CH1: u32,
-        }), base_address + 0x1b8);
-
-        /// address: 0x6003f1bc
-        /// DMA_OUT_PRI_CH1_REG.
-        pub const OUT_PRI_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Tx channel 1. The larger of the value, the higher of the
-            /// priority.
-            TX_PRI_CH1: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x1bc);
-
-        /// address: 0x6003f1c0
-        /// DMA_OUT_PERI_SEL_CH1_REG.
-        pub const OUT_PERI_SEL_CH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Tx channel 1. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_OUT_SEL_CH1: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x1c0);
-
-        /// address: 0x6003f1f0
-        /// DMA_IN_CONF0_CH2_REG.
-        pub const IN_CONF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
-            IN_RST_CH2: u1,
-            /// reserved
-            IN_LOOP_TEST_CH2: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link
-            /// descriptor when accessing internal SRAM.
-            INDSCR_BURST_EN_CH2: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data
-            /// when accessing internal SRAM.
-            IN_DATA_BURST_EN_CH2: u1,
-            /// Set this bit 1 to enable automatic transmitting data from memory to memory via
-            /// DMA.
-            MEM_TRANS_EN_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x1f0);
-
-        /// address: 0x6003f1f4
-        /// DMA_IN_CONF1_CH2_REG.
-        pub const IN_CONF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            IN_CHECK_OWNER_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x1f4);
-
-        /// address: 0x6003f1f8
-        /// DMA_INFIFO_STATUS_CH2_REG.
-        pub const INFIFO_STATUS_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Rx FIFO full signal for Rx channel 2.
-            INFIFO_FULL_CH2: u1,
-            /// L1 Rx FIFO empty signal for Rx channel 2.
-            INFIFO_EMPTY_CH2: u1,
-            /// The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.
-            INFIFO_CNT_CH2: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            IN_REMAIN_UNDER_1B_CH2: u1,
-            /// reserved
-            IN_REMAIN_UNDER_2B_CH2: u1,
-            /// reserved
-            IN_REMAIN_UNDER_3B_CH2: u1,
-            /// reserved
-            IN_REMAIN_UNDER_4B_CH2: u1,
-            /// reserved
-            IN_BUF_HUNGRY_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x1f8);
-
-        /// address: 0x6003f1fc
-        /// DMA_IN_POP_CH2_REG.
-        pub const IN_POP_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data popping from DMA FIFO.
-            INFIFO_RDATA_CH2: u12,
-            /// Set this bit to pop data from DMA FIFO.
-            INFIFO_POP_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x1fc);
-
-        /// address: 0x6003f200
-        /// DMA_IN_LINK_CH2_REG.
-        pub const IN_LINK_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first inlink
-            /// descriptor's address.
-            INLINK_ADDR_CH2: u20,
-            /// Set this bit to return to current inlink descriptor's address, when there are
-            /// some errors in current receiving data.
-            INLINK_AUTO_RET_CH2: u1,
-            /// Set this bit to stop dealing with the inlink descriptors.
-            INLINK_STOP_CH2: u1,
-            /// Set this bit to start dealing with the inlink descriptors.
-            INLINK_START_CH2: u1,
-            /// Set this bit to mount a new inlink descriptor.
-            INLINK_RESTART_CH2: u1,
-            /// 1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM
-            /// is working.
-            INLINK_PARK_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x200);
-
-        /// address: 0x6003f204
-        /// DMA_IN_STATE_CH2_REG.
-        pub const IN_STATE_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current inlink descriptor's address.
-            INLINK_DSCR_ADDR_CH2: u18,
-            /// reserved
-            IN_DSCR_STATE_CH2: u2,
-            /// reserved
-            IN_STATE_CH2: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x204);
-
-        /// address: 0x6003f208
-        /// DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.
-        pub const IN_SUC_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x208);
-
-        /// address: 0x6003f20c
-        /// DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.
-        pub const IN_ERR_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x20c);
-
-        /// address: 0x6003f210
-        /// DMA_IN_DSCR_CH2_REG.
-        pub const IN_DSCR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current inlink descriptor x.
-            INLINK_DSCR_CH2: u32,
-        }), base_address + 0x210);
-
-        /// address: 0x6003f214
-        /// DMA_IN_DSCR_BF0_CH2_REG.
-        pub const IN_DSCR_BF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last inlink descriptor x-1.
-            INLINK_DSCR_BF0_CH2: u32,
-        }), base_address + 0x214);
-
-        /// address: 0x6003f218
-        /// DMA_IN_DSCR_BF1_CH2_REG.
-        pub const IN_DSCR_BF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            INLINK_DSCR_BF1_CH2: u32,
-        }), base_address + 0x218);
-
-        /// address: 0x6003f21c
-        /// DMA_IN_PRI_CH2_REG.
-        pub const IN_PRI_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Rx channel 2. The larger of the value, the higher of the
-            /// priority.
-            RX_PRI_CH2: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x21c);
-
-        /// address: 0x6003f220
-        /// DMA_IN_PERI_SEL_CH2_REG.
-        pub const IN_PERI_SEL_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Rx channel 2. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_IN_SEL_CH2: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x220);
-
-        /// address: 0x6003f250
-        /// DMA_OUT_CONF0_CH2_REG.
-        pub const OUT_CONF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
-            OUT_RST_CH2: u1,
-            /// reserved
-            OUT_LOOP_TEST_CH2: u1,
-            /// Set this bit to enable automatic outlink-writeback when all the data in tx
-            /// buffer has been transmitted.
-            OUT_AUTO_WRBACK_CH2: u1,
-            /// EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is
-            /// generated when data need to transmit has been popped from FIFO in DMA
-            OUT_EOF_MODE_CH2: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link
-            /// descriptor when accessing internal SRAM.
-            OUTDSCR_BURST_EN_CH2: u1,
-            /// Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting
-            /// data when accessing internal SRAM.
-            OUT_DATA_BURST_EN_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x250);
-
-        /// address: 0x6003f254
-        /// DMA_OUT_CONF1_CH2_REG.
-        pub const OUT_CONF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Set this bit to enable checking the owner attribute of the link descriptor.
-            OUT_CHECK_OWNER_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x254);
-
-        /// address: 0x6003f258
-        /// DMA_OUTFIFO_STATUS_CH2_REG.
-        pub const OUTFIFO_STATUS_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// L1 Tx FIFO full signal for Tx channel 2.
-            OUTFIFO_FULL_CH2: u1,
-            /// L1 Tx FIFO empty signal for Tx channel 2.
-            OUTFIFO_EMPTY_CH2: u1,
-            /// The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.
-            OUTFIFO_CNT_CH2: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_1B_CH2: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_2B_CH2: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_3B_CH2: u1,
-            /// reserved
-            OUT_REMAIN_UNDER_4B_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-        }), base_address + 0x258);
-
-        /// address: 0x6003f25c
-        /// DMA_OUT_PUSH_CH2_REG.
-        pub const OUT_PUSH_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the data that need to be pushed into DMA FIFO.
-            OUTFIFO_WDATA_CH2: u9,
-            /// Set this bit to push data into DMA FIFO.
-            OUTFIFO_PUSH_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x25c);
-
-        /// address: 0x6003f260
-        /// DMA_OUT_LINK_CH2_REG.
-        pub const OUT_LINK_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the 20 least significant bits of the first outlink
-            /// descriptor's address.
-            OUTLINK_ADDR_CH2: u20,
-            /// Set this bit to stop dealing with the outlink descriptors.
-            OUTLINK_STOP_CH2: u1,
-            /// Set this bit to start dealing with the outlink descriptors.
-            OUTLINK_START_CH2: u1,
-            /// Set this bit to restart a new outlink from the last address.
-            OUTLINK_RESTART_CH2: u1,
-            /// 1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's
-            /// FSM is working.
-            OUTLINK_PARK_CH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x260);
-
-        /// address: 0x6003f264
-        /// DMA_OUT_STATE_CH2_REG.
-        pub const OUT_STATE_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the current outlink descriptor's address.
-            OUTLINK_DSCR_ADDR_CH2: u18,
-            /// reserved
-            OUT_DSCR_STATE_CH2: u2,
-            /// reserved
-            OUT_STATE_CH2: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x264);
-
-        /// address: 0x6003f268
-        /// DMA_OUT_EOF_DES_ADDR_CH2_REG.
-        pub const OUT_EOF_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x268);
-
-        /// address: 0x6003f26c
-        /// DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.
-        pub const OUT_EOF_BFR_DES_ADDR_CH2 = @intToPtr(*volatile u32, base_address + 0x26c);
-
-        /// address: 0x6003f270
-        /// DMA_OUT_DSCR_CH2_REG.
-        pub const OUT_DSCR_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the current outlink descriptor y.
-            OUTLINK_DSCR_CH2: u32,
-        }), base_address + 0x270);
-
-        /// address: 0x6003f274
-        /// DMA_OUT_DSCR_BF0_CH2_REG.
-        pub const OUT_DSCR_BF0_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the last outlink descriptor y-1.
-            OUTLINK_DSCR_BF0_CH2: u32,
-        }), base_address + 0x274);
-
-        /// address: 0x6003f278
-        /// DMA_OUT_DSCR_BF1_CH2_REG.
-        pub const OUT_DSCR_BF1_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The address of the second-to-last inlink descriptor x-2.
-            OUTLINK_DSCR_BF1_CH2: u32,
-        }), base_address + 0x278);
-
-        /// address: 0x6003f27c
-        /// DMA_OUT_PRI_CH2_REG.
-        pub const OUT_PRI_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The priority of Tx channel 2. The larger of the value, the higher of the
-            /// priority.
-            TX_PRI_CH2: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x27c);
-
-        /// address: 0x6003f280
-        /// DMA_OUT_PERI_SEL_CH2_REG.
-        pub const OUT_PERI_SEL_CH2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to select peripheral for Tx channel 2. 0:SPI2. 1:
-            /// reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8:
-            /// ADC_DAC.
-            PERI_OUT_SEL_CH2: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x280);
-    };
-
-    /// Digital Signature
-    pub const DS = struct {
-        pub const base_address = 0x6003d000;
-
-        /// address: 0x6003d000
-        /// memory that stores Y
-        pub const Y_MEM = @intToPtr(*volatile [512]u8, base_address + 0x0);
-
-        /// address: 0x6003d200
-        /// memory that stores M
-        pub const M_MEM = @intToPtr(*volatile [512]u8, base_address + 0x200);
-
-        /// address: 0x6003d400
-        /// memory that stores Rb
-        pub const RB_MEM = @intToPtr(*volatile [512]u8, base_address + 0x400);
-
-        /// address: 0x6003d600
-        /// memory that stores BOX
-        pub const BOX_MEM = @intToPtr(*volatile [48]u8, base_address + 0x600);
-
-        /// address: 0x6003d800
-        /// memory that stores X
-        pub const X_MEM = @intToPtr(*volatile [512]u8, base_address + 0x800);
-
-        /// address: 0x6003da00
-        /// memory that stores Z
-        pub const Z_MEM = @intToPtr(*volatile [512]u8, base_address + 0xa00);
-
-        /// address: 0x6003de00
-        /// DS start control register
-        pub const SET_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe00);
-
-        /// address: 0x6003de04
-        /// DS continue control register
-        pub const SET_CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe04);
-
-        /// address: 0x6003de08
-        /// DS finish control register
-        pub const SET_FINISH = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe08);
-
-        /// address: 0x6003de0c
-        /// DS query busy register
-        pub const QUERY_BUSY = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xe0c);
-
-        /// address: 0x6003de10
-        /// DS query key-wrong counter register
-        pub const QUERY_KEY_WRONG = @intToPtr(*volatile MmioInt(32, u4), base_address + 0xe10);
-
-        /// address: 0x6003de14
-        /// DS query check result register
-        pub const QUERY_CHECK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
-            MD_ERROR: u1,
-            /// padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
-            PADDING_BAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xe14);
-
-        /// address: 0x6003de20
-        /// DS version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0xe20);
-    };
-
-    /// eFuse Controller
-    pub const EFUSE = struct {
-        pub const base_address = 0x60008800;
-
-        /// address: 0x60008800
-        /// Register 0 that stores data to be programmed.
-        pub const PGM_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 0th 32-bit data to be programmed.
-            PGM_DATA_0: u32,
-        }), base_address + 0x0);
-
-        /// address: 0x60008804
-        /// Register 1 that stores data to be programmed.
-        pub const PGM_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 1st 32-bit data to be programmed.
-            PGM_DATA_1: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60008808
-        /// Register 2 that stores data to be programmed.
-        pub const PGM_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 2nd 32-bit data to be programmed.
-            PGM_DATA_2: u32,
-        }), base_address + 0x8);
-
-        /// address: 0x6000880c
-        /// Register 3 that stores data to be programmed.
-        pub const PGM_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 3rd 32-bit data to be programmed.
-            PGM_DATA_3: u32,
-        }), base_address + 0xc);
-
-        /// address: 0x60008810
-        /// Register 4 that stores data to be programmed.
-        pub const PGM_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 4th 32-bit data to be programmed.
-            PGM_DATA_4: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x60008814
-        /// Register 5 that stores data to be programmed.
-        pub const PGM_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 5th 32-bit data to be programmed.
-            PGM_DATA_5: u32,
-        }), base_address + 0x14);
-
-        /// address: 0x60008818
-        /// Register 6 that stores data to be programmed.
-        pub const PGM_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 6th 32-bit data to be programmed.
-            PGM_DATA_6: u32,
-        }), base_address + 0x18);
-
-        /// address: 0x6000881c
-        /// Register 7 that stores data to be programmed.
-        pub const PGM_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 7th 32-bit data to be programmed.
-            PGM_DATA_7: u32,
-        }), base_address + 0x1c);
-
-        /// address: 0x60008820
-        /// Register 0 that stores the RS code to be programmed.
-        pub const PGM_CHECK_VALUE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 0th 32-bit RS code to be programmed.
-            PGM_RS_DATA_0: u32,
-        }), base_address + 0x20);
-
-        /// address: 0x60008824
-        /// Register 1 that stores the RS code to be programmed.
-        pub const PGM_CHECK_VALUE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 1st 32-bit RS code to be programmed.
-            PGM_RS_DATA_1: u32,
-        }), base_address + 0x24);
-
-        /// address: 0x60008828
-        /// Register 2 that stores the RS code to be programmed.
-        pub const PGM_CHECK_VALUE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The content of the 2nd 32-bit RS code to be programmed.
-            PGM_RS_DATA_2: u32,
-        }), base_address + 0x28);
-
-        /// address: 0x6000882c
-        /// BLOCK0 data register 0.
-        pub const RD_WR_DIS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Disable programming of individual eFuses.
-            WR_DIS: u32,
-        }), base_address + 0x2c);
-
-        /// address: 0x60008830
-        /// BLOCK0 data register 1.
-        pub const RD_REPEAT_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to disable reading from BlOCK4-10.
-            RD_DIS: u7,
-            /// Set this bit to disable boot from RTC RAM.
-            DIS_RTC_RAM_BOOT: u1,
-            /// Set this bit to disable Icache.
-            DIS_ICACHE: u1,
-            /// Set this bit to disable function of usb switch to jtag in module of usb device.
-            DIS_USB_JTAG: u1,
-            /// Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3,
-            /// 6, 7).
-            DIS_DOWNLOAD_ICACHE: u1,
-            /// Set this bit to disable usb device.
-            DIS_USB_DEVICE: u1,
-            /// Set this bit to disable the function that forces chip into download mode.
-            DIS_FORCE_DOWNLOAD: u1,
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED6: u1,
-            /// Set this bit to disable CAN function.
-            DIS_CAN: u1,
-            /// Set this bit to enable selection between usb_to_jtag and pad_to_jtag through
-            /// strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
-            JTAG_SEL_ENABLE: u1,
-            /// Set these bits to disable JTAG in the soft way (odd number 1 means disable ).
-            /// JTAG can be enabled in HMAC module.
-            SOFT_DIS_JTAG: u3,
-            /// Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
-            DIS_PAD_JTAG: u1,
-            /// Set this bit to disable flash encryption when in download boot modes.
-            DIS_DOWNLOAD_MANUAL_ENCRYPT: u1,
-            /// Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV,
-            /// stored in eFuse.
-            USB_DREFH: u2,
-            /// Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV,
-            /// stored in eFuse.
-            USB_DREFL: u2,
-            /// Set this bit to exchange USB D+ and D- pins.
-            USB_EXCHG_PINS: u1,
-            /// Set this bit to vdd spi pin function as gpio.
-            VDD_SPI_AS_GPIO: u1,
-            /// Enable btlc gpio.
-            BTLC_GPIO_ENABLE: u2,
-            /// Set this bit to enable power glitch function.
-            POWERGLITCH_EN: u1,
-            /// Sample delay configuration of power glitch.
-            POWER_GLITCH_DSENSE: u2,
-        }), base_address + 0x30);
-
-        /// address: 0x60008834
-        /// BLOCK0 data register 2.
-        pub const RD_REPEAT_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED2: u16,
-            /// Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000.
-            /// 1: 80000. 2: 160000. 3:320000.
-            WDT_DELAY_SEL: u2,
-            /// Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even
-            /// number of 1: disable.
-            SPI_BOOT_CRYPT_CNT: u3,
-            /// Set this bit to enable revoking first secure boot key.
-            SECURE_BOOT_KEY_REVOKE0: u1,
-            /// Set this bit to enable revoking second secure boot key.
-            SECURE_BOOT_KEY_REVOKE1: u1,
-            /// Set this bit to enable revoking third secure boot key.
-            SECURE_BOOT_KEY_REVOKE2: u1,
-            /// Purpose of Key0.
-            KEY_PURPOSE_0: u4,
-            /// Purpose of Key1.
-            KEY_PURPOSE_1: u4,
-        }), base_address + 0x34);
-
-        /// address: 0x60008838
-        /// BLOCK0 data register 3.
-        pub const RD_REPEAT_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Purpose of Key2.
-            KEY_PURPOSE_2: u4,
-            /// Purpose of Key3.
-            KEY_PURPOSE_3: u4,
-            /// Purpose of Key4.
-            KEY_PURPOSE_4: u4,
-            /// Purpose of Key5.
-            KEY_PURPOSE_5: u4,
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED3: u4,
-            /// Set this bit to enable secure boot.
-            SECURE_BOOT_EN: u1,
-            /// Set this bit to enable revoking aggressive secure boot.
-            SECURE_BOOT_AGGRESSIVE_REVOKE: u1,
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED0: u6,
-            /// Configures flash waiting time after power-up, in unit of ms. If the value is
-            /// less than 15, the waiting time is the configurable value; Otherwise, the waiting
-            /// time is twice the configurable value.
-            FLASH_TPUW: u4,
-        }), base_address + 0x38);
-
-        /// address: 0x6000883c
-        /// BLOCK0 data register 4.
-        pub const RD_REPEAT_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
-            DIS_DOWNLOAD_MODE: u1,
-            /// Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).
-            DIS_LEGACY_SPI_BOOT: u1,
-            /// Selectes the default UART print channel. 0: UART0. 1: UART1.
-            UART_PRINT_CHANNEL: u1,
-            /// Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would
-            /// use 16to17 byte mode.
-            FLASH_ECC_MODE: u1,
-            /// Set this bit to disable UART download mode through USB.
-            DIS_USB_DOWNLOAD_MODE: u1,
-            /// Set this bit to enable secure UART download mode.
-            ENABLE_SECURITY_DOWNLOAD: u1,
-            /// Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when
-            /// GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
-            UART_PRINT_CONTROL: u2,
-            /// GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
-            PIN_POWER_SELECTION: u1,
-            /// Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
-            FLASH_TYPE: u1,
-            /// Set Flash page size.
-            FLASH_PAGE_SIZE: u2,
-            /// Set 1 to enable ECC for flash boot.
-            FLASH_ECC_EN: u1,
-            /// Set this bit to force ROM code to send a resume command during SPI boot.
-            FORCE_SEND_RESUME: u1,
-            /// Secure version (used by ESP-IDF anti-rollback feature).
-            SECURE_VERSION: u16,
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED1: u2,
-        }), base_address + 0x3c);
-
-        /// address: 0x60008840
-        /// BLOCK0 data register 5.
-        pub const RD_REPEAT_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved (used for four backups method).
-            RPT4_RESERVED4: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60008844
-        /// BLOCK1 data register 0.
-        pub const RD_MAC_SPI_SYS_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the low 32 bits of MAC address.
-            MAC_0: u32,
-        }), base_address + 0x44);
-
-        /// address: 0x60008848
-        /// BLOCK1 data register 1.
-        pub const RD_MAC_SPI_SYS_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the high 16 bits of MAC address.
-            MAC_1: u16,
-            /// Stores the zeroth part of SPI_PAD_CONF.
-            SPI_PAD_CONF_0: u16,
-        }), base_address + 0x48);
-
-        /// address: 0x6000884c
-        /// BLOCK1 data register 2.
-        pub const RD_MAC_SPI_SYS_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first part of SPI_PAD_CONF.
-            SPI_PAD_CONF_1: u32,
-        }), base_address + 0x4c);
-
-        /// address: 0x60008850
-        /// BLOCK1 data register 3.
-        pub const RD_MAC_SPI_SYS_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second part of SPI_PAD_CONF.
-            SPI_PAD_CONF_2: u18,
-            /// Stores the fist 14 bits of the zeroth part of system data.
-            SYS_DATA_PART0_0: u14,
-        }), base_address + 0x50);
-
-        /// address: 0x60008854
-        /// BLOCK1 data register 4.
-        pub const RD_MAC_SPI_SYS_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fist 32 bits of the zeroth part of system data.
-            SYS_DATA_PART0_1: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x60008858
-        /// BLOCK1 data register 5.
-        pub const RD_MAC_SPI_SYS_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of the zeroth part of system data.
-            SYS_DATA_PART0_2: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6000885c
-        /// Register 0 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of the first part of system data.
-            SYS_DATA_PART1_0: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x60008860
-        /// Register 1 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of the first part of system data.
-            SYS_DATA_PART1_1: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x60008864
-        /// Register 2 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of the first part of system data.
-            SYS_DATA_PART1_2: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x60008868
-        /// Register 3 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of the first part of system data.
-            SYS_DATA_PART1_3: u32,
-        }), base_address + 0x68);
-
-        /// address: 0x6000886c
-        /// Register 4 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of the first part of system data.
-            SYS_DATA_PART1_4: u32,
-        }), base_address + 0x6c);
-
-        /// address: 0x60008870
-        /// Register 5 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of the first part of system data.
-            SYS_DATA_PART1_5: u32,
-        }), base_address + 0x70);
-
-        /// address: 0x60008874
-        /// Register 6 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of the first part of system data.
-            SYS_DATA_PART1_6: u32,
-        }), base_address + 0x74);
-
-        /// address: 0x60008878
-        /// Register 7 of BLOCK2 (system).
-        pub const RD_SYS_PART1_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of the first part of system data.
-            SYS_DATA_PART1_7: u32,
-        }), base_address + 0x78);
-
-        /// address: 0x6000887c
-        /// Register 0 of BLOCK3 (user).
-        pub const RD_USR_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of BLOCK3 (user).
-            USR_DATA0: u32,
-        }), base_address + 0x7c);
-
-        /// address: 0x60008880
-        /// Register 1 of BLOCK3 (user).
-        pub const RD_USR_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of BLOCK3 (user).
-            USR_DATA1: u32,
-        }), base_address + 0x80);
-
-        /// address: 0x60008884
-        /// Register 2 of BLOCK3 (user).
-        pub const RD_USR_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of BLOCK3 (user).
-            USR_DATA2: u32,
-        }), base_address + 0x84);
-
-        /// address: 0x60008888
-        /// Register 3 of BLOCK3 (user).
-        pub const RD_USR_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of BLOCK3 (user).
-            USR_DATA3: u32,
-        }), base_address + 0x88);
-
-        /// address: 0x6000888c
-        /// Register 4 of BLOCK3 (user).
-        pub const RD_USR_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of BLOCK3 (user).
-            USR_DATA4: u32,
-        }), base_address + 0x8c);
-
-        /// address: 0x60008890
-        /// Register 5 of BLOCK3 (user).
-        pub const RD_USR_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of BLOCK3 (user).
-            USR_DATA5: u32,
-        }), base_address + 0x90);
-
-        /// address: 0x60008894
-        /// Register 6 of BLOCK3 (user).
-        pub const RD_USR_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of BLOCK3 (user).
-            USR_DATA6: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x60008898
-        /// Register 7 of BLOCK3 (user).
-        pub const RD_USR_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of BLOCK3 (user).
-            USR_DATA7: u32,
-        }), base_address + 0x98);
-
-        /// address: 0x6000889c
-        /// Register 0 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY0.
-            KEY0_DATA0: u32,
-        }), base_address + 0x9c);
-
-        /// address: 0x600088a0
-        /// Register 1 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY0.
-            KEY0_DATA1: u32,
-        }), base_address + 0xa0);
-
-        /// address: 0x600088a4
-        /// Register 2 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY0.
-            KEY0_DATA2: u32,
-        }), base_address + 0xa4);
-
-        /// address: 0x600088a8
-        /// Register 3 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY0.
-            KEY0_DATA3: u32,
-        }), base_address + 0xa8);
-
-        /// address: 0x600088ac
-        /// Register 4 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY0.
-            KEY0_DATA4: u32,
-        }), base_address + 0xac);
-
-        /// address: 0x600088b0
-        /// Register 5 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY0.
-            KEY0_DATA5: u32,
-        }), base_address + 0xb0);
-
-        /// address: 0x600088b4
-        /// Register 6 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY0.
-            KEY0_DATA6: u32,
-        }), base_address + 0xb4);
-
-        /// address: 0x600088b8
-        /// Register 7 of BLOCK4 (KEY0).
-        pub const RD_KEY0_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY0.
-            KEY0_DATA7: u32,
-        }), base_address + 0xb8);
-
-        /// address: 0x600088bc
-        /// Register 0 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY1.
-            KEY1_DATA0: u32,
-        }), base_address + 0xbc);
-
-        /// address: 0x600088c0
-        /// Register 1 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY1.
-            KEY1_DATA1: u32,
-        }), base_address + 0xc0);
-
-        /// address: 0x600088c4
-        /// Register 2 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY1.
-            KEY1_DATA2: u32,
-        }), base_address + 0xc4);
-
-        /// address: 0x600088c8
-        /// Register 3 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY1.
-            KEY1_DATA3: u32,
-        }), base_address + 0xc8);
-
-        /// address: 0x600088cc
-        /// Register 4 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY1.
-            KEY1_DATA4: u32,
-        }), base_address + 0xcc);
-
-        /// address: 0x600088d0
-        /// Register 5 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY1.
-            KEY1_DATA5: u32,
-        }), base_address + 0xd0);
-
-        /// address: 0x600088d4
-        /// Register 6 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY1.
-            KEY1_DATA6: u32,
-        }), base_address + 0xd4);
-
-        /// address: 0x600088d8
-        /// Register 7 of BLOCK5 (KEY1).
-        pub const RD_KEY1_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY1.
-            KEY1_DATA7: u32,
-        }), base_address + 0xd8);
-
-        /// address: 0x600088dc
-        /// Register 0 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY2.
-            KEY2_DATA0: u32,
-        }), base_address + 0xdc);
-
-        /// address: 0x600088e0
-        /// Register 1 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY2.
-            KEY2_DATA1: u32,
-        }), base_address + 0xe0);
-
-        /// address: 0x600088e4
-        /// Register 2 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY2.
-            KEY2_DATA2: u32,
-        }), base_address + 0xe4);
-
-        /// address: 0x600088e8
-        /// Register 3 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY2.
-            KEY2_DATA3: u32,
-        }), base_address + 0xe8);
-
-        /// address: 0x600088ec
-        /// Register 4 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY2.
-            KEY2_DATA4: u32,
-        }), base_address + 0xec);
-
-        /// address: 0x600088f0
-        /// Register 5 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY2.
-            KEY2_DATA5: u32,
-        }), base_address + 0xf0);
-
-        /// address: 0x600088f4
-        /// Register 6 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY2.
-            KEY2_DATA6: u32,
-        }), base_address + 0xf4);
-
-        /// address: 0x600088f8
-        /// Register 7 of BLOCK6 (KEY2).
-        pub const RD_KEY2_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY2.
-            KEY2_DATA7: u32,
-        }), base_address + 0xf8);
-
-        /// address: 0x600088fc
-        /// Register 0 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY3.
-            KEY3_DATA0: u32,
-        }), base_address + 0xfc);
-
-        /// address: 0x60008900
-        /// Register 1 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY3.
-            KEY3_DATA1: u32,
-        }), base_address + 0x100);
-
-        /// address: 0x60008904
-        /// Register 2 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY3.
-            KEY3_DATA2: u32,
-        }), base_address + 0x104);
-
-        /// address: 0x60008908
-        /// Register 3 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY3.
-            KEY3_DATA3: u32,
-        }), base_address + 0x108);
-
-        /// address: 0x6000890c
-        /// Register 4 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY3.
-            KEY3_DATA4: u32,
-        }), base_address + 0x10c);
-
-        /// address: 0x60008910
-        /// Register 5 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY3.
-            KEY3_DATA5: u32,
-        }), base_address + 0x110);
-
-        /// address: 0x60008914
-        /// Register 6 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY3.
-            KEY3_DATA6: u32,
-        }), base_address + 0x114);
-
-        /// address: 0x60008918
-        /// Register 7 of BLOCK7 (KEY3).
-        pub const RD_KEY3_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY3.
-            KEY3_DATA7: u32,
-        }), base_address + 0x118);
-
-        /// address: 0x6000891c
-        /// Register 0 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY4.
-            KEY4_DATA0: u32,
-        }), base_address + 0x11c);
-
-        /// address: 0x60008920
-        /// Register 1 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY4.
-            KEY4_DATA1: u32,
-        }), base_address + 0x120);
-
-        /// address: 0x60008924
-        /// Register 2 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY4.
-            KEY4_DATA2: u32,
-        }), base_address + 0x124);
-
-        /// address: 0x60008928
-        /// Register 3 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY4.
-            KEY4_DATA3: u32,
-        }), base_address + 0x128);
-
-        /// address: 0x6000892c
-        /// Register 4 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY4.
-            KEY4_DATA4: u32,
-        }), base_address + 0x12c);
-
-        /// address: 0x60008930
-        /// Register 5 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY4.
-            KEY4_DATA5: u32,
-        }), base_address + 0x130);
-
-        /// address: 0x60008934
-        /// Register 6 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY4.
-            KEY4_DATA6: u32,
-        }), base_address + 0x134);
-
-        /// address: 0x60008938
-        /// Register 7 of BLOCK8 (KEY4).
-        pub const RD_KEY4_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY4.
-            KEY4_DATA7: u32,
-        }), base_address + 0x138);
-
-        /// address: 0x6000893c
-        /// Register 0 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the zeroth 32 bits of KEY5.
-            KEY5_DATA0: u32,
-        }), base_address + 0x13c);
-
-        /// address: 0x60008940
-        /// Register 1 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the first 32 bits of KEY5.
-            KEY5_DATA1: u32,
-        }), base_address + 0x140);
-
-        /// address: 0x60008944
-        /// Register 2 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the second 32 bits of KEY5.
-            KEY5_DATA2: u32,
-        }), base_address + 0x144);
-
-        /// address: 0x60008948
-        /// Register 3 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the third 32 bits of KEY5.
-            KEY5_DATA3: u32,
-        }), base_address + 0x148);
-
-        /// address: 0x6000894c
-        /// Register 4 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fourth 32 bits of KEY5.
-            KEY5_DATA4: u32,
-        }), base_address + 0x14c);
-
-        /// address: 0x60008950
-        /// Register 5 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the fifth 32 bits of KEY5.
-            KEY5_DATA5: u32,
-        }), base_address + 0x150);
-
-        /// address: 0x60008954
-        /// Register 6 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the sixth 32 bits of KEY5.
-            KEY5_DATA6: u32,
-        }), base_address + 0x154);
-
-        /// address: 0x60008958
-        /// Register 7 of BLOCK9 (KEY5).
-        pub const RD_KEY5_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the seventh 32 bits of KEY5.
-            KEY5_DATA7: u32,
-        }), base_address + 0x158);
-
-        /// address: 0x6000895c
-        /// Register 0 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 0th 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_0: u32,
-        }), base_address + 0x15c);
-
-        /// address: 0x60008960
-        /// Register 1 of BLOCK9 (KEY5).
-        pub const RD_SYS_PART2_DATA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 1st 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_1: u32,
-        }), base_address + 0x160);
-
-        /// address: 0x60008964
-        /// Register 2 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 2nd 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_2: u32,
-        }), base_address + 0x164);
-
-        /// address: 0x60008968
-        /// Register 3 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 3rd 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_3: u32,
-        }), base_address + 0x168);
-
-        /// address: 0x6000896c
-        /// Register 4 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 4th 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_4: u32,
-        }), base_address + 0x16c);
-
-        /// address: 0x60008970
-        /// Register 5 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 5th 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_5: u32,
-        }), base_address + 0x170);
-
-        /// address: 0x60008974
-        /// Register 6 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 6th 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_6: u32,
-        }), base_address + 0x174);
-
-        /// address: 0x60008978
-        /// Register 7 of BLOCK10 (system).
-        pub const RD_SYS_PART2_DATA7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the 7th 32 bits of the 2nd part of system data.
-            SYS_DATA_PART2_7: u32,
-        }), base_address + 0x178);
-
-        /// address: 0x6000897c
-        /// Programming error record register 0 of BLOCK0.
-        pub const RD_REPEAT_ERR0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// If any bit in RD_DIS is 1, then it indicates a programming error.
-            RD_DIS_ERR: u7,
-            /// If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
-            DIS_RTC_RAM_BOOT_ERR: u1,
-            /// If DIS_ICACHE is 1, then it indicates a programming error.
-            DIS_ICACHE_ERR: u1,
-            /// If DIS_USB_JTAG is 1, then it indicates a programming error.
-            DIS_USB_JTAG_ERR: u1,
-            /// If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
-            DIS_DOWNLOAD_ICACHE_ERR: u1,
-            /// If DIS_USB_DEVICE is 1, then it indicates a programming error.
-            DIS_USB_DEVICE_ERR: u1,
-            /// If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
-            DIS_FORCE_DOWNLOAD_ERR: u1,
-            /// Reserved.
-            RPT4_RESERVED6_ERR: u1,
-            /// If DIS_CAN is 1, then it indicates a programming error.
-            DIS_CAN_ERR: u1,
-            /// If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
-            JTAG_SEL_ENABLE_ERR: u1,
-            /// If SOFT_DIS_JTAG is 1, then it indicates a programming error.
-            SOFT_DIS_JTAG_ERR: u3,
-            /// If DIS_PAD_JTAG is 1, then it indicates a programming error.
-            DIS_PAD_JTAG_ERR: u1,
-            /// If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
-            DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR: u1,
-            /// If any bit in USB_DREFH is 1, then it indicates a programming error.
-            USB_DREFH_ERR: u2,
-            /// If any bit in USB_DREFL is 1, then it indicates a programming error.
-            USB_DREFL_ERR: u2,
-            /// If USB_EXCHG_PINS is 1, then it indicates a programming error.
-            USB_EXCHG_PINS_ERR: u1,
-            /// If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
-            VDD_SPI_AS_GPIO_ERR: u1,
-            /// If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
-            BTLC_GPIO_ENABLE_ERR: u2,
-            /// If POWERGLITCH_EN is 1, then it indicates a programming error.
-            POWERGLITCH_EN_ERR: u1,
-            /// If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
-            POWER_GLITCH_DSENSE_ERR: u2,
-        }), base_address + 0x17c);
-
-        /// address: 0x60008980
-        /// Programming error record register 1 of BLOCK0.
-        pub const RD_REPEAT_ERR1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            RPT4_RESERVED2_ERR: u16,
-            /// If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
-            WDT_DELAY_SEL_ERR: u2,
-            /// If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
-            SPI_BOOT_CRYPT_CNT_ERR: u3,
-            /// If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
-            SECURE_BOOT_KEY_REVOKE0_ERR: u1,
-            /// If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
-            SECURE_BOOT_KEY_REVOKE1_ERR: u1,
-            /// If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
-            SECURE_BOOT_KEY_REVOKE2_ERR: u1,
-            /// If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
-            KEY_PURPOSE_0_ERR: u4,
-            /// If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
-            KEY_PURPOSE_1_ERR: u4,
-        }), base_address + 0x180);
-
-        /// address: 0x60008984
-        /// Programming error record register 2 of BLOCK0.
-        pub const RD_REPEAT_ERR2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
-            KEY_PURPOSE_2_ERR: u4,
-            /// If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
-            KEY_PURPOSE_3_ERR: u4,
-            /// If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
-            KEY_PURPOSE_4_ERR: u4,
-            /// If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
-            KEY_PURPOSE_5_ERR: u4,
-            /// Reserved.
-            RPT4_RESERVED3_ERR: u4,
-            /// If SECURE_BOOT_EN is 1, then it indicates a programming error.
-            SECURE_BOOT_EN_ERR: u1,
-            /// If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
-            SECURE_BOOT_AGGRESSIVE_REVOKE_ERR: u1,
-            /// Reserved.
-            RPT4_RESERVED0_ERR: u6,
-            /// If any bit in FLASH_TPUM is 1, then it indicates a programming error.
-            FLASH_TPUW_ERR: u4,
-        }), base_address + 0x184);
-
-        /// address: 0x60008988
-        /// Programming error record register 3 of BLOCK0.
-        pub const RD_REPEAT_ERR3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
-            DIS_DOWNLOAD_MODE_ERR: u1,
-            /// If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
-            DIS_LEGACY_SPI_BOOT_ERR: u1,
-            /// If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
-            UART_PRINT_CHANNEL_ERR: u1,
-            /// If FLASH_ECC_MODE is 1, then it indicates a programming error.
-            FLASH_ECC_MODE_ERR: u1,
-            /// If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
-            DIS_USB_DOWNLOAD_MODE_ERR: u1,
-            /// If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
-            ENABLE_SECURITY_DOWNLOAD_ERR: u1,
-            /// If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
-            UART_PRINT_CONTROL_ERR: u2,
-            /// If PIN_POWER_SELECTION is 1, then it indicates a programming error.
-            PIN_POWER_SELECTION_ERR: u1,
-            /// If FLASH_TYPE is 1, then it indicates a programming error.
-            FLASH_TYPE_ERR: u1,
-            /// If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
-            FLASH_PAGE_SIZE_ERR: u2,
-            /// If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
-            FLASH_ECC_EN_ERR: u1,
-            /// If FORCE_SEND_RESUME is 1, then it indicates a programming error.
-            FORCE_SEND_RESUME_ERR: u1,
-            /// If any bit in SECURE_VERSION is 1, then it indicates a programming error.
-            SECURE_VERSION_ERR: u16,
-            /// Reserved.
-            RPT4_RESERVED1_ERR: u2,
-        }), base_address + 0x188);
-
-        /// address: 0x60008990
-        /// Programming error record register 4 of BLOCK0.
-        pub const RD_REPEAT_ERR4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            RPT4_RESERVED4_ERR: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x190);
-
-        /// address: 0x600089c0
-        /// Programming error record register 0 of BLOCK1-10.
-        pub const RD_RS_ERR0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of this signal means the number of error bytes.
-            MAC_SPI_8M_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that
-            /// programming user data failed and the number of error bytes is over 6.
-            MAC_SPI_8M_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            SYS_PART1_NUM: u3,
-            /// 0: Means no failure and that the data of system part1 is reliable 1: Means that
-            /// programming user data failed and the number of error bytes is over 6.
-            SYS_PART1_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            USR_DATA_ERR_NUM: u3,
-            /// 0: Means no failure and that the user data is reliable 1: Means that programming
-            /// user data failed and the number of error bytes is over 6.
-            USR_DATA_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            KEY0_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of key0 is reliable 1: Means that
-            /// programming key0 failed and the number of error bytes is over 6.
-            KEY0_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            KEY1_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of key1 is reliable 1: Means that
-            /// programming key1 failed and the number of error bytes is over 6.
-            KEY1_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            KEY2_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of key2 is reliable 1: Means that
-            /// programming key2 failed and the number of error bytes is over 6.
-            KEY2_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            KEY3_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of key3 is reliable 1: Means that
-            /// programming key3 failed and the number of error bytes is over 6.
-            KEY3_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            KEY4_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of key4 is reliable 1: Means that
-            /// programming key4 failed and the number of error bytes is over 6.
-            KEY4_FAIL: u1,
-        }), base_address + 0x1c0);
-
-        /// address: 0x600089c4
-        /// Programming error record register 1 of BLOCK1-10.
-        pub const RD_RS_ERR1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of this signal means the number of error bytes.
-            KEY5_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of KEY5 is reliable 1: Means that
-            /// programming user data failed and the number of error bytes is over 6.
-            KEY5_FAIL: u1,
-            /// The value of this signal means the number of error bytes.
-            SYS_PART2_ERR_NUM: u3,
-            /// 0: Means no failure and that the data of system part2 is reliable 1: Means that
-            /// programming user data failed and the number of error bytes is over 6.
-            SYS_PART2_FAIL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x1c4);
-
-        /// address: 0x600089c8
-        /// eFuse clcok configuration register.
-        pub const CLK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to force eFuse SRAM into power-saving mode.
-            EFUSE_MEM_FORCE_PD: u1,
-            /// Set this bit and force to activate clock signal of eFuse SRAM.
-            MEM_CLK_FORCE_ON: u1,
-            /// Set this bit to force eFuse SRAM into working mode.
-            EFUSE_MEM_FORCE_PU: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            /// Set this bit and force to enable clock signal of eFuse memory.
-            EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x1c8);
-
-        /// address: 0x600089cc
-        /// eFuse operation mode configuraiton register;
-        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 0x5A5A: Operate programming command 0x5AA5: Operate read command.
-            OP_CODE: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x1cc);
-
-        /// address: 0x600089d0
-        /// eFuse status register.
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Indicates the state of the eFuse state machine.
-            STATE: u4,
-            /// The value of OTP_LOAD_SW.
-            OTP_LOAD_SW: u1,
-            /// The value of OTP_VDDQ_C_SYNC2.
-            OTP_VDDQ_C_SYNC2: u1,
-            /// The value of OTP_STROBE_SW.
-            OTP_STROBE_SW: u1,
-            /// The value of OTP_CSB_SW.
-            OTP_CSB_SW: u1,
-            /// The value of OTP_PGENB_SW.
-            OTP_PGENB_SW: u1,
-            /// The value of OTP_VDDQ_IS_SW.
-            OTP_VDDQ_IS_SW: u1,
-            /// Indicates the number of error bits during programming BLOCK0.
-            REPEAT_ERR_CNT: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x1d0);
-
-        /// address: 0x600089d4
-        /// eFuse command register.
-        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to send read command.
-            READ_CMD: u1,
-            /// Set this bit to send programming command.
-            PGM_CMD: u1,
-            /// The serial number of the block to be programmed. Value 0-10 corresponds to block
-            /// number 0-10, respectively.
-            BLK_NUM: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x1d4);
-
-        /// address: 0x600089d8
-        /// eFuse raw interrupt register.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw bit signal for read_done interrupt.
-            READ_DONE_INT_RAW: u1,
-            /// The raw bit signal for pgm_done interrupt.
-            PGM_DONE_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x1d8);
-
-        /// address: 0x600089dc
-        /// eFuse interrupt status register.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The status signal for read_done interrupt.
-            READ_DONE_INT_ST: u1,
-            /// The status signal for pgm_done interrupt.
-            PGM_DONE_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x1dc);
-
-        /// address: 0x600089e0
-        /// eFuse interrupt enable register.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The enable signal for read_done interrupt.
-            READ_DONE_INT_ENA: u1,
-            /// The enable signal for pgm_done interrupt.
-            PGM_DONE_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x1e0);
-
-        /// address: 0x600089e4
-        /// eFuse interrupt clear register.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The clear signal for read_done interrupt.
-            READ_DONE_INT_CLR: u1,
-            /// The clear signal for pgm_done interrupt.
-            PGM_DONE_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x1e4);
-
-        /// address: 0x600089e8
-        /// Controls the eFuse programming voltage.
-        pub const DAC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Controls the division factor of the rising clock of the programming voltage.
-            DAC_CLK_DIV: u8,
-            /// Don't care.
-            DAC_CLK_PAD_SEL: u1,
-            /// Controls the rising period of the programming voltage.
-            DAC_NUM: u8,
-            /// Reduces the power supply of the programming voltage.
-            OE_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x1e8);
-
-        /// address: 0x600089ec
-        /// Configures read timing parameters.
-        pub const RD_TIM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            /// Configures the initial read time of eFuse.
-            READ_INIT_NUM: u8,
-        }), base_address + 0x1ec);
-
-        /// address: 0x600089f0
-        /// Configurarion register 1 of eFuse programming timing parameters.
-        pub const WR_TIM_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// Configures the power up time for VDDQ.
-            PWR_ON_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x1f0);
-
-        /// address: 0x600089f4
-        /// Configurarion register 2 of eFuse programming timing parameters.
-        pub const WR_TIM_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Configures the power outage time for VDDQ.
-            PWR_OFF_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x1f4);
-
-        /// address: 0x600089fc
-        /// eFuse version register.
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x1fc);
-    };
-
-    /// External Memory
-    pub const EXTMEM = struct {
-        pub const base_address = 0x600c4000;
-
-        /// address: 0x600c4000
-        /// This description will be updated in the near future.
-        pub const ICACHE_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to activate the data cache. 0: disable, 1: enable
-            ICACHE_ENABLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x600c4004
-        /// This description will be updated in the near future.
-        pub const ICACHE_CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to disable core0 ibus, 0: enable, 1: disable
-            ICACHE_SHUT_IBUS: u1,
-            /// The bit is used to disable core1 ibus, 0: enable, 1: disable
-            ICACHE_SHUT_DBUS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x600c4008
-        /// This description will be updated in the near future.
-        pub const ICACHE_TAG_POWER_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to close clock gating of icache tag memory. 1: close gating, 0:
-            /// open clock gating.
-            ICACHE_TAG_MEM_FORCE_ON: u1,
-            /// The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power
-            /// down
-            ICACHE_TAG_MEM_FORCE_PD: u1,
-            /// The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up
-            ICACHE_TAG_MEM_FORCE_PU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x600c400c
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOCK_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable the first section of prelock function.
-            ICACHE_PRELOCK_SCT0_EN: u1,
-            /// The bit is used to enable the second section of prelock function.
-            ICACHE_PRELOCK_SCT1_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x600c4010
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOCK_SCT0_ADDR = @intToPtr(*volatile u32, base_address + 0x10);
-
-        /// address: 0x600c4014
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOCK_SCT1_ADDR = @intToPtr(*volatile u32, base_address + 0x14);
-
-        /// address: 0x600c4018
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOCK_SCT_SIZE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to configure the second length of data locking, which is
-            /// combined with ICACHE_PRELOCK_SCT1_ADDR_REG
-            ICACHE_PRELOCK_SCT1_SIZE: u16,
-            /// The bits are used to configure the first length of data locking, which is
-            /// combined with ICACHE_PRELOCK_SCT0_ADDR_REG
-            ICACHE_PRELOCK_SCT0_SIZE: u16,
-        }), base_address + 0x18);
-
-        /// address: 0x600c401c
-        /// This description will be updated in the near future.
-        pub const ICACHE_LOCK_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable lock operation. It will be cleared by hardware after
-            /// lock operation done.
-            ICACHE_LOCK_ENA: u1,
-            /// The bit is used to enable unlock operation. It will be cleared by hardware after
-            /// unlock operation done.
-            ICACHE_UNLOCK_ENA: u1,
-            /// The bit is used to indicate unlock/lock operation is finished.
-            ICACHE_LOCK_DONE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x600c4020
-        /// This description will be updated in the near future.
-        pub const ICACHE_LOCK_ADDR = @intToPtr(*volatile u32, base_address + 0x20);
-
-        /// address: 0x600c4024
-        /// This description will be updated in the near future.
-        pub const ICACHE_LOCK_SIZE = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x24);
-
-        /// address: 0x600c4028
-        /// This description will be updated in the near future.
-        pub const ICACHE_SYNC_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable invalidate operation. It will be cleared by hardware
-            /// after invalidate operation done.
-            ICACHE_INVALIDATE_ENA: u1,
-            /// The bit is used to indicate invalidate operation is finished.
-            ICACHE_SYNC_DONE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x600c402c
-        /// This description will be updated in the near future.
-        pub const ICACHE_SYNC_ADDR = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x600c4030
-        /// This description will be updated in the near future.
-        pub const ICACHE_SYNC_SIZE = @intToPtr(*volatile MmioInt(32, u23), base_address + 0x30);
-
-        /// address: 0x600c4034
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOAD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable preload operation. It will be cleared by hardware
-            /// after preload operation done.
-            ICACHE_PRELOAD_ENA: u1,
-            /// The bit is used to indicate preload operation is finished.
-            ICACHE_PRELOAD_DONE: u1,
-            /// The bit is used to configure the direction of preload operation. 1: descending,
-            /// 0: ascending.
-            ICACHE_PRELOAD_ORDER: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x600c4038
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOAD_ADDR = @intToPtr(*volatile u32, base_address + 0x38);
-
-        /// address: 0x600c403c
-        /// This description will be updated in the near future.
-        pub const ICACHE_PRELOAD_SIZE = @intToPtr(*volatile MmioInt(32, u16), base_address + 0x3c);
-
-        /// address: 0x600c4040
-        /// This description will be updated in the near future.
-        pub const ICACHE_AUTOLOAD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to enable the first section for autoload operation.
-            ICACHE_AUTOLOAD_SCT0_ENA: u1,
-            /// The bits are used to enable the second section for autoload operation.
-            ICACHE_AUTOLOAD_SCT1_ENA: u1,
-            /// The bit is used to enable and disable autoload operation. It is combined with
-            /// icache_autoload_done. 1: enable, 0: disable.
-            ICACHE_AUTOLOAD_ENA: u1,
-            /// The bit is used to indicate autoload operation is finished.
-            ICACHE_AUTOLOAD_DONE: u1,
-            /// The bits are used to configure the direction of autoload. 1: descending, 0:
-            /// ascending.
-            ICACHE_AUTOLOAD_ORDER: u1,
-            /// The bits are used to configure trigger conditions for autoload. 0/3: cache miss,
-            /// 1: cache hit, 2: both cache miss and hit.
-            ICACHE_AUTOLOAD_RQST: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x600c4044
-        /// This description will be updated in the near future.
-        pub const ICACHE_AUTOLOAD_SCT0_ADDR = @intToPtr(*volatile u32, base_address + 0x44);
-
-        /// address: 0x600c4048
-        /// This description will be updated in the near future.
-        pub const ICACHE_AUTOLOAD_SCT0_SIZE = @intToPtr(*volatile MmioInt(32, u27), base_address + 0x48);
-
-        /// address: 0x600c404c
-        /// This description will be updated in the near future.
-        pub const ICACHE_AUTOLOAD_SCT1_ADDR = @intToPtr(*volatile u32, base_address + 0x4c);
-
-        /// address: 0x600c4050
-        /// This description will be updated in the near future.
-        pub const ICACHE_AUTOLOAD_SCT1_SIZE = @intToPtr(*volatile MmioInt(32, u27), base_address + 0x50);
-
-        /// address: 0x600c4054
-        /// This description will be updated in the near future.
-        pub const IBUS_TO_FLASH_START_VADDR = @intToPtr(*volatile u32, base_address + 0x54);
-
-        /// address: 0x600c4058
-        /// This description will be updated in the near future.
-        pub const IBUS_TO_FLASH_END_VADDR = @intToPtr(*volatile u32, base_address + 0x58);
-
-        /// address: 0x600c405c
-        /// This description will be updated in the near future.
-        pub const DBUS_TO_FLASH_START_VADDR = @intToPtr(*volatile u32, base_address + 0x5c);
-
-        /// address: 0x600c4060
-        /// This description will be updated in the near future.
-        pub const DBUS_TO_FLASH_END_VADDR = @intToPtr(*volatile u32, base_address + 0x60);
-
-        /// address: 0x600c4064
-        /// This description will be updated in the near future.
-        pub const CACHE_ACS_CNT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to clear ibus counter.
-            IBUS_ACS_CNT_CLR: u1,
-            /// The bit is used to clear dbus counter.
-            DBUS_ACS_CNT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x600c4068
-        /// This description will be updated in the near future.
-        pub const IBUS_ACS_MISS_CNT = @intToPtr(*volatile u32, base_address + 0x68);
-
-        /// address: 0x600c406c
-        /// This description will be updated in the near future.
-        pub const IBUS_ACS_CNT = @intToPtr(*volatile u32, base_address + 0x6c);
-
-        /// address: 0x600c4070
-        /// This description will be updated in the near future.
-        pub const DBUS_ACS_FLASH_MISS_CNT = @intToPtr(*volatile u32, base_address + 0x70);
-
-        /// address: 0x600c4074
-        /// This description will be updated in the near future.
-        pub const DBUS_ACS_CNT = @intToPtr(*volatile u32, base_address + 0x74);
-
-        /// address: 0x600c4078
-        /// This description will be updated in the near future.
-        pub const CACHE_ILG_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable interrupt by sync configurations fault.
-            ICACHE_SYNC_OP_FAULT_INT_ENA: u1,
-            /// The bit is used to enable interrupt by preload configurations fault.
-            ICACHE_PRELOAD_OP_FAULT_INT_ENA: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The bit is used to enable interrupt by mmu entry fault.
-            MMU_ENTRY_FAULT_INT_ENA: u1,
-            reserved3: u1,
-            /// The bit is used to enable interrupt by ibus counter overflow.
-            IBUS_CNT_OVF_INT_ENA: u1,
-            /// The bit is used to enable interrupt by dbus counter overflow.
-            DBUS_CNT_OVF_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x600c407c
-        /// This description will be updated in the near future.
-        pub const CACHE_ILG_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to clear interrupt by sync configurations fault.
-            ICACHE_SYNC_OP_FAULT_INT_CLR: u1,
-            /// The bit is used to clear interrupt by preload configurations fault.
-            ICACHE_PRELOAD_OP_FAULT_INT_CLR: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The bit is used to clear interrupt by mmu entry fault.
-            MMU_ENTRY_FAULT_INT_CLR: u1,
-            reserved3: u1,
-            /// The bit is used to clear interrupt by ibus counter overflow.
-            IBUS_CNT_OVF_INT_CLR: u1,
-            /// The bit is used to clear interrupt by dbus counter overflow.
-            DBUS_CNT_OVF_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x600c4080
-        /// This description will be updated in the near future.
-        pub const CACHE_ILG_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to indicate interrupt by sync configurations fault.
-            ICACHE_SYNC_OP_FAULT_ST: u1,
-            /// The bit is used to indicate interrupt by preload configurations fault.
-            ICACHE_PRELOAD_OP_FAULT_ST: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The bit is used to indicate interrupt by mmu entry fault.
-            MMU_ENTRY_FAULT_ST: u1,
-            reserved3: u1,
-            /// The bit is used to indicate interrupt by ibus access flash/spiram counter
-            /// overflow.
-            IBUS_ACS_CNT_OVF_ST: u1,
-            /// The bit is used to indicate interrupt by ibus access flash/spiram miss counter
-            /// overflow.
-            IBUS_ACS_MISS_CNT_OVF_ST: u1,
-            /// The bit is used to indicate interrupt by dbus access flash/spiram counter
-            /// overflow.
-            DBUS_ACS_CNT_OVF_ST: u1,
-            /// The bit is used to indicate interrupt by dbus access flash miss counter
-            /// overflow.
-            DBUS_ACS_FLASH_MISS_CNT_OVF_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x600c4084
-        /// This description will be updated in the near future.
-        pub const CORE0_ACS_CACHE_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable interrupt by cpu access icache while the corresponding
-            /// ibus is disabled which include speculative access.
-            CORE0_IBUS_ACS_MSK_IC_INT_ENA: u1,
-            /// The bit is used to enable interrupt by ibus trying to write icache
-            CORE0_IBUS_WR_IC_INT_ENA: u1,
-            /// The bit is used to enable interrupt by authentication fail.
-            CORE0_IBUS_REJECT_INT_ENA: u1,
-            /// The bit is used to enable interrupt by cpu access icache while the corresponding
-            /// dbus is disabled which include speculative access.
-            CORE0_DBUS_ACS_MSK_IC_INT_ENA: u1,
-            /// The bit is used to enable interrupt by authentication fail.
-            CORE0_DBUS_REJECT_INT_ENA: u1,
-            /// The bit is used to enable interrupt by dbus trying to write icache
-            CORE0_DBUS_WR_IC_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x600c4088
-        /// This description will be updated in the near future.
-        pub const CORE0_ACS_CACHE_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to clear interrupt by cpu access icache while the corresponding
-            /// ibus is disabled or icache is disabled which include speculative access.
-            CORE0_IBUS_ACS_MSK_IC_INT_CLR: u1,
-            /// The bit is used to clear interrupt by ibus trying to write icache
-            CORE0_IBUS_WR_IC_INT_CLR: u1,
-            /// The bit is used to clear interrupt by authentication fail.
-            CORE0_IBUS_REJECT_INT_CLR: u1,
-            /// The bit is used to clear interrupt by cpu access icache while the corresponding
-            /// dbus is disabled or icache is disabled which include speculative access.
-            CORE0_DBUS_ACS_MSK_IC_INT_CLR: u1,
-            /// The bit is used to clear interrupt by authentication fail.
-            CORE0_DBUS_REJECT_INT_CLR: u1,
-            /// The bit is used to clear interrupt by dbus trying to write icache
-            CORE0_DBUS_WR_IC_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x600c408c
-        /// This description will be updated in the near future.
-        pub const CORE0_ACS_CACHE_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to indicate interrupt by cpu access icache while the core0_ibus
-            /// is disabled or icache is disabled which include speculative access.
-            CORE0_IBUS_ACS_MSK_ICACHE_ST: u1,
-            /// The bit is used to indicate interrupt by ibus trying to write icache
-            CORE0_IBUS_WR_ICACHE_ST: u1,
-            /// The bit is used to indicate interrupt by authentication fail.
-            CORE0_IBUS_REJECT_ST: u1,
-            /// The bit is used to indicate interrupt by cpu access icache while the core0_dbus
-            /// is disabled or icache is disabled which include speculative access.
-            CORE0_DBUS_ACS_MSK_ICACHE_ST: u1,
-            /// The bit is used to indicate interrupt by authentication fail.
-            CORE0_DBUS_REJECT_ST: u1,
-            /// The bit is used to indicate interrupt by dbus trying to write icache
-            CORE0_DBUS_WR_ICACHE_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x600c4090
-        /// This description will be updated in the near future.
-        pub const CORE0_DBUS_REJECT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to indicate the attribute of CPU access dbus when
-            /// authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4:
-            /// write-able.
-            CORE0_DBUS_ATTR: u3,
-            /// The bit is used to indicate the world of CPU access dbus when authentication
-            /// fail. 0: WORLD0, 1: WORLD1
-            CORE0_DBUS_WORLD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x600c4094
-        /// This description will be updated in the near future.
-        pub const CORE0_DBUS_REJECT_VADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to indicate the virtual address of CPU access dbus when
-            /// authentication fail.
-            CORE0_DBUS_VADDR: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x600c4098
-        /// This description will be updated in the near future.
-        pub const CORE0_IBUS_REJECT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to indicate the attribute of CPU access ibus when
-            /// authentication fail. 0: invalidate, 1: execute-able, 2: read-able
-            CORE0_IBUS_ATTR: u3,
-            /// The bit is used to indicate the world of CPU access ibus when authentication
-            /// fail. 0: WORLD0, 1: WORLD1
-            CORE0_IBUS_WORLD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x600c409c
-        /// This description will be updated in the near future.
-        pub const CORE0_IBUS_REJECT_VADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to indicate the virtual address of CPU access ibus when
-            /// authentication fail.
-            CORE0_IBUS_VADDR: u32,
-        }), base_address + 0x9c);
-
-        /// address: 0x600c40a0
-        /// This description will be updated in the near future.
-        pub const CACHE_MMU_FAULT_CONTENT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bits are used to indicate the content of mmu entry which cause mmu fault..
-            CACHE_MMU_FAULT_CONTENT: u10,
-            /// The right-most 3 bits are used to indicate the operations which cause mmu fault
-            /// occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss
-            /// evict recovery address, 5: load miss evict recovery address, 6: external dma tx,
-            /// 7: external dma rx. The most significant bit is used to indicate this operation
-            /// occurs in which one icache.
-            CACHE_MMU_FAULT_CODE: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x600c40a4
-        /// This description will be updated in the near future.
-        pub const CACHE_MMU_FAULT_VADDR = @intToPtr(*volatile u32, base_address + 0xa4);
-
-        /// address: 0x600c40a8
-        /// This description will be updated in the near future.
-        pub const CACHE_WRAP_AROUND_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable wrap around mode when read data from flash.
-            CACHE_FLASH_WRAP_AROUND: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600c40ac
-        /// This description will be updated in the near future.
-        pub const CACHE_MMU_POWER_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable clock gating to save power when access mmu memory, 0:
-            /// enable, 1: disable
-            CACHE_MMU_MEM_FORCE_ON: u1,
-            /// The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down
-            CACHE_MMU_MEM_FORCE_PD: u1,
-            /// The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up
-            CACHE_MMU_MEM_FORCE_PU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600c40b0
-        /// This description will be updated in the near future.
-        pub const CACHE_STATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to indicate whether icache main fsm is in idle state or not. 1:
-            /// in idle state, 0: not in idle state
-            ICACHE_STATE: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x600c40b4
-        /// This description will be updated in the near future.
-        pub const CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            RECORD_DISABLE_DB_ENCRYPT: u1,
-            /// Reserved.
-            RECORD_DISABLE_G0CB_DECRYPT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600c40b8
-        /// This description will be updated in the near future.
-        pub const CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to close clock gating of manual crypt clock. 1: close gating, 0:
-            /// open clock gating.
-            CLK_FORCE_ON_MANUAL_CRYPT: u1,
-            /// The bit is used to close clock gating of automatic crypt clock. 1: close gating,
-            /// 0: open clock gating.
-            CLK_FORCE_ON_AUTO_CRYPT: u1,
-            /// The bit is used to close clock gating of external memory encrypt and decrypt
-            /// clock. 1: close gating, 0: open clock gating.
-            CLK_FORCE_ON_CRYPT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xb8);
-
-        /// address: 0x600c40bc
-        /// This description will be updated in the near future.
-        pub const CACHE_PRELOAD_INT_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to indicate the interrupt by icache pre-load done.
-            ICACHE_PRELOAD_INT_ST: u1,
-            /// The bit is used to enable the interrupt by icache pre-load done.
-            ICACHE_PRELOAD_INT_ENA: u1,
-            /// The bit is used to clear the interrupt by icache pre-load done.
-            ICACHE_PRELOAD_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xbc);
-
-        /// address: 0x600c40c0
-        /// This description will be updated in the near future.
-        pub const CACHE_SYNC_INT_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to indicate the interrupt by icache sync done.
-            ICACHE_SYNC_INT_ST: u1,
-            /// The bit is used to enable the interrupt by icache sync done.
-            ICACHE_SYNC_INT_ENA: u1,
-            /// The bit is used to clear the interrupt by icache sync done.
-            ICACHE_SYNC_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600c40c4
-        /// This description will be updated in the near future.
-        pub const CACHE_MMU_OWNER = @intToPtr(*volatile MmioInt(32, u4), base_address + 0xc4);
-
-        /// address: 0x600c40c8
-        /// This description will be updated in the near future.
-        pub const CACHE_CONF_MISC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to disable checking mmu entry fault by preload operation.
-            CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT: u1,
-            /// The bit is used to disable checking mmu entry fault by sync operation.
-            CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT: u1,
-            /// The bit is used to enable cache trace function.
-            CACHE_TRACE_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600c40cc
-        /// This description will be updated in the near future.
-        pub const ICACHE_FREEZE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable icache freeze mode
-            ENA: u1,
-            /// The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert
-            /// hit if CPU miss
-            MODE: u1,
-            /// The bit is used to indicate icache freeze success
-            DONE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x600c40d0
-        /// This description will be updated in the near future.
-        pub const ICACHE_ATOMIC_OPERATE_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xd0);
-
-        /// address: 0x600c40d4
-        /// This description will be updated in the near future.
-        pub const CACHE_REQUEST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to disable request recording which could cause performance issue
-            BYPASS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xd4);
-
-        /// address: 0x600c40d8
-        /// This description will be updated in the near future.
-        pub const IBUS_PMS_TBL_LOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the ibus permission control section boundary0
-            IBUS_PMS_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xd8);
-
-        /// address: 0x600c40dc
-        /// This description will be updated in the near future.
-        pub const IBUS_PMS_TBL_BOUNDARY0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the ibus permission control section boundary0
-            IBUS_PMS_BOUNDARY0: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xdc);
-
-        /// address: 0x600c40e0
-        /// This description will be updated in the near future.
-        pub const IBUS_PMS_TBL_BOUNDARY1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the ibus permission control section boundary1
-            IBUS_PMS_BOUNDARY1: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xe0);
-
-        /// address: 0x600c40e4
-        /// This description will be updated in the near future.
-        pub const IBUS_PMS_TBL_BOUNDARY2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the ibus permission control section boundary2
-            IBUS_PMS_BOUNDARY2: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xe4);
-
-        /// address: 0x600c40e8
-        /// This description will be updated in the near future.
-        pub const IBUS_PMS_TBL_ATTR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure attribute of the ibus permission control section1,
-            /// bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load
-            /// in world1
-            IBUS_PMS_SCT1_ATTR: u4,
-            /// The bit is used to configure attribute of the ibus permission control section2,
-            /// bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load
-            /// in world1
-            IBUS_PMS_SCT2_ATTR: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0xe8);
-
-        /// address: 0x600c40ec
-        /// This description will be updated in the near future.
-        pub const DBUS_PMS_TBL_LOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the ibus permission control section boundary0
-            DBUS_PMS_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xec);
-
-        /// address: 0x600c40f0
-        /// This description will be updated in the near future.
-        pub const DBUS_PMS_TBL_BOUNDARY0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the dbus permission control section boundary0
-            DBUS_PMS_BOUNDARY0: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xf0);
-
-        /// address: 0x600c40f4
-        /// This description will be updated in the near future.
-        pub const DBUS_PMS_TBL_BOUNDARY1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the dbus permission control section boundary1
-            DBUS_PMS_BOUNDARY1: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xf4);
-
-        /// address: 0x600c40f8
-        /// This description will be updated in the near future.
-        pub const DBUS_PMS_TBL_BOUNDARY2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure the dbus permission control section boundary2
-            DBUS_PMS_BOUNDARY2: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xf8);
-
-        /// address: 0x600c40fc
-        /// This description will be updated in the near future.
-        pub const DBUS_PMS_TBL_ATTR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to configure attribute of the dbus permission control section1,
-            /// bit0: load in world0, bit2: load in world1
-            DBUS_PMS_SCT1_ATTR: u2,
-            /// The bit is used to configure attribute of the dbus permission control section2,
-            /// bit0: load in world0, bit2: load in world1
-            DBUS_PMS_SCT2_ATTR: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0xfc);
-
-        /// address: 0x600c4100
-        /// This description will be updated in the near future.
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// clock gate enable.
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x600c43fc
-        /// This description will be updated in the near future.
-        pub const REG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// version information
-            DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x3fc);
-    };
-
-    /// General Purpose Input/Output
-    pub const GPIO = struct {
-        pub const base_address = 0x60004000;
-
-        /// address: 0x60004000
-        /// GPIO bit select register
-        pub const BT_SELECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO bit select register
-            BT_SEL: u32,
-        }), base_address + 0x0);
-
-        /// address: 0x60004004
-        /// GPIO output register
-        pub const OUT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO output register for GPIO0-25
-            DATA_ORIG: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60004008
-        /// GPIO output set register
-        pub const OUT_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x8);
-
-        /// address: 0x6000400c
-        /// GPIO output clear register
-        pub const OUT_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0xc);
-
-        /// address: 0x6000401c
-        /// GPIO sdio select register
-        pub const SDIO_SELECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO sdio select register
-            SDIO_SEL: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60004020
-        /// GPIO output enable register
-        pub const ENABLE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO output enable register for GPIO0-25
-            DATA: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60004024
-        /// GPIO output enable set register
-        pub const ENABLE_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x24);
-
-        /// address: 0x60004028
-        /// GPIO output enable clear register
-        pub const ENABLE_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x28);
-
-        /// address: 0x60004038
-        /// pad strapping register
-        pub const STRAP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// pad strapping register
-            STRAPPING: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6000403c
-        /// GPIO input register
-        pub const IN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO input register for GPIO0-25
-            DATA_NEXT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60004044
-        /// GPIO interrupt status register
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO interrupt status register for GPIO0-25
-            INTERRUPT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60004048
-        /// GPIO interrupt status set register
-        pub const STATUS_W1TS = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x48);
-
-        /// address: 0x6000404c
-        /// GPIO interrupt status clear register
-        pub const STATUS_W1TC = @intToPtr(*volatile MmioInt(32, u26), base_address + 0x4c);
-
-        /// address: 0x6000405c
-        /// GPIO PRO_CPU interrupt status register
-        pub const PCPU_INT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO PRO_CPU interrupt status register for GPIO0-25
-            PROCPU_INT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60004060
-        /// GPIO PRO_CPU(not shielded) interrupt status register
-        pub const PCPU_NMI_INT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25
-            PROCPU_NMI_INT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60004064
-        /// GPIO CPUSDIO interrupt status register
-        pub const CPUSDIO_INT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO CPUSDIO interrupt status register for GPIO0-25
-            SDIO_INT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60004074
-        /// GPIO pin configuration register
-        pub const PIN0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60004078
-        /// GPIO pin configuration register
-        pub const PIN1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6000407c
-        /// GPIO pin configuration register
-        pub const PIN2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x60004080
-        /// GPIO pin configuration register
-        pub const PIN3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x60004084
-        /// GPIO pin configuration register
-        pub const PIN4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x60004088
-        /// GPIO pin configuration register
-        pub const PIN5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x6000408c
-        /// GPIO pin configuration register
-        pub const PIN6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x60004090
-        /// GPIO pin configuration register
-        pub const PIN7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x60004094
-        /// GPIO pin configuration register
-        pub const PIN8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x94);
-
-        /// address: 0x60004098
-        /// GPIO pin configuration register
-        pub const PIN9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x6000409c
-        /// GPIO pin configuration register
-        pub const PIN10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x9c);
-
-        /// address: 0x600040a0
-        /// GPIO pin configuration register
-        pub const PIN11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x600040a4
-        /// GPIO pin configuration register
-        pub const PIN12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600040a8
-        /// GPIO pin configuration register
-        pub const PIN13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600040ac
-        /// GPIO pin configuration register
-        pub const PIN14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600040b0
-        /// GPIO pin configuration register
-        pub const PIN15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x600040b4
-        /// GPIO pin configuration register
-        pub const PIN16 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600040b8
-        /// GPIO pin configuration register
-        pub const PIN17 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xb8);
-
-        /// address: 0x600040bc
-        /// GPIO pin configuration register
-        pub const PIN18 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xbc);
-
-        /// address: 0x600040c0
-        /// GPIO pin configuration register
-        pub const PIN19 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600040c4
-        /// GPIO pin configuration register
-        pub const PIN20 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xc4);
-
-        /// address: 0x600040c8
-        /// GPIO pin configuration register
-        pub const PIN21 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600040cc
-        /// GPIO pin configuration register
-        pub const PIN22 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x600040d0
-        /// GPIO pin configuration register
-        pub const PIN23 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x600040d4
-        /// GPIO pin configuration register
-        pub const PIN24 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xd4);
-
-        /// address: 0x600040d8
-        /// GPIO pin configuration register
-        pub const PIN25 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC2_BYPASS: u2,
-            /// set this bit to select pad driver. 1:open-drain. :normal.
-            PIN_PAD_DRIVER: u1,
-            /// set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger
-            /// at posedge.
-            PIN_SYNC1_BYPASS: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at
-            /// posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level.
-            /// 5:valid at high level
-            PIN_INT_TYPE: u3,
-            /// set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-            PIN_WAKEUP_ENABLE: u1,
-            /// reserved
-            PIN_CONFIG: u2,
-            /// set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded)
-            /// interrupt.
-            PIN_INT_ENA: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xd8);
-
-        /// address: 0x6000414c
-        /// GPIO interrupt source register
-        pub const STATUS_NEXT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// GPIO interrupt source register for GPIO0-25
-            STATUS_INTERRUPT_NEXT: u26,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x14c);
-
-        /// address: 0x60004154
-        /// GPIO input function configuration register
-        pub const FUNC0_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x154);
-
-        /// address: 0x60004158
-        /// GPIO input function configuration register
-        pub const FUNC1_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x158);
-
-        /// address: 0x6000415c
-        /// GPIO input function configuration register
-        pub const FUNC2_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x15c);
-
-        /// address: 0x60004160
-        /// GPIO input function configuration register
-        pub const FUNC3_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x160);
-
-        /// address: 0x60004164
-        /// GPIO input function configuration register
-        pub const FUNC4_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x164);
-
-        /// address: 0x60004168
-        /// GPIO input function configuration register
-        pub const FUNC5_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x168);
-
-        /// address: 0x6000416c
-        /// GPIO input function configuration register
-        pub const FUNC6_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x16c);
-
-        /// address: 0x60004170
-        /// GPIO input function configuration register
-        pub const FUNC7_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x170);
-
-        /// address: 0x60004174
-        /// GPIO input function configuration register
-        pub const FUNC8_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x174);
-
-        /// address: 0x60004178
-        /// GPIO input function configuration register
-        pub const FUNC9_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x178);
-
-        /// address: 0x6000417c
-        /// GPIO input function configuration register
-        pub const FUNC10_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x17c);
-
-        /// address: 0x60004180
-        /// GPIO input function configuration register
-        pub const FUNC11_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x180);
-
-        /// address: 0x60004184
-        /// GPIO input function configuration register
-        pub const FUNC12_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x184);
-
-        /// address: 0x60004188
-        /// GPIO input function configuration register
-        pub const FUNC13_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x188);
-
-        /// address: 0x6000418c
-        /// GPIO input function configuration register
-        pub const FUNC14_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x18c);
-
-        /// address: 0x60004190
-        /// GPIO input function configuration register
-        pub const FUNC15_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x190);
-
-        /// address: 0x60004194
-        /// GPIO input function configuration register
-        pub const FUNC16_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x194);
-
-        /// address: 0x60004198
-        /// GPIO input function configuration register
-        pub const FUNC17_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x198);
-
-        /// address: 0x6000419c
-        /// GPIO input function configuration register
-        pub const FUNC18_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x19c);
-
-        /// address: 0x600041a0
-        /// GPIO input function configuration register
-        pub const FUNC19_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1a0);
-
-        /// address: 0x600041a4
-        /// GPIO input function configuration register
-        pub const FUNC20_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1a4);
-
-        /// address: 0x600041a8
-        /// GPIO input function configuration register
-        pub const FUNC21_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1a8);
-
-        /// address: 0x600041ac
-        /// GPIO input function configuration register
-        pub const FUNC22_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1ac);
-
-        /// address: 0x600041b0
-        /// GPIO input function configuration register
-        pub const FUNC23_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1b0);
-
-        /// address: 0x600041b4
-        /// GPIO input function configuration register
-        pub const FUNC24_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1b4);
-
-        /// address: 0x600041b8
-        /// GPIO input function configuration register
-        pub const FUNC25_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1b8);
-
-        /// address: 0x600041bc
-        /// GPIO input function configuration register
-        pub const FUNC26_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1bc);
-
-        /// address: 0x600041c0
-        /// GPIO input function configuration register
-        pub const FUNC27_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1c0);
-
-        /// address: 0x600041c4
-        /// GPIO input function configuration register
-        pub const FUNC28_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1c4);
-
-        /// address: 0x600041c8
-        /// GPIO input function configuration register
-        pub const FUNC29_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1c8);
-
-        /// address: 0x600041cc
-        /// GPIO input function configuration register
-        pub const FUNC30_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1cc);
-
-        /// address: 0x600041d0
-        /// GPIO input function configuration register
-        pub const FUNC31_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1d0);
-
-        /// address: 0x600041d4
-        /// GPIO input function configuration register
-        pub const FUNC32_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1d4);
-
-        /// address: 0x600041d8
-        /// GPIO input function configuration register
-        pub const FUNC33_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1d8);
-
-        /// address: 0x600041dc
-        /// GPIO input function configuration register
-        pub const FUNC34_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1dc);
-
-        /// address: 0x600041e0
-        /// GPIO input function configuration register
-        pub const FUNC35_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1e0);
-
-        /// address: 0x600041e4
-        /// GPIO input function configuration register
-        pub const FUNC36_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1e4);
-
-        /// address: 0x600041e8
-        /// GPIO input function configuration register
-        pub const FUNC37_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1e8);
-
-        /// address: 0x600041ec
-        /// GPIO input function configuration register
-        pub const FUNC38_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1ec);
-
-        /// address: 0x600041f0
-        /// GPIO input function configuration register
-        pub const FUNC39_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1f0);
-
-        /// address: 0x600041f4
-        /// GPIO input function configuration register
-        pub const FUNC40_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1f4);
-
-        /// address: 0x600041f8
-        /// GPIO input function configuration register
-        pub const FUNC41_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1f8);
-
-        /// address: 0x600041fc
-        /// GPIO input function configuration register
-        pub const FUNC42_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x1fc);
-
-        /// address: 0x60004200
-        /// GPIO input function configuration register
-        pub const FUNC43_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x200);
-
-        /// address: 0x60004204
-        /// GPIO input function configuration register
-        pub const FUNC44_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x204);
-
-        /// address: 0x60004208
-        /// GPIO input function configuration register
-        pub const FUNC45_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x208);
-
-        /// address: 0x6000420c
-        /// GPIO input function configuration register
-        pub const FUNC46_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x20c);
-
-        /// address: 0x60004210
-        /// GPIO input function configuration register
-        pub const FUNC47_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x210);
-
-        /// address: 0x60004214
-        /// GPIO input function configuration register
-        pub const FUNC48_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x214);
-
-        /// address: 0x60004218
-        /// GPIO input function configuration register
-        pub const FUNC49_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x218);
-
-        /// address: 0x6000421c
-        /// GPIO input function configuration register
-        pub const FUNC50_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x21c);
-
-        /// address: 0x60004220
-        /// GPIO input function configuration register
-        pub const FUNC51_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x220);
-
-        /// address: 0x60004224
-        /// GPIO input function configuration register
-        pub const FUNC52_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x224);
-
-        /// address: 0x60004228
-        /// GPIO input function configuration register
-        pub const FUNC53_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x228);
-
-        /// address: 0x6000422c
-        /// GPIO input function configuration register
-        pub const FUNC54_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x22c);
-
-        /// address: 0x60004230
-        /// GPIO input function configuration register
-        pub const FUNC55_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x230);
-
-        /// address: 0x60004234
-        /// GPIO input function configuration register
-        pub const FUNC56_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x234);
-
-        /// address: 0x60004238
-        /// GPIO input function configuration register
-        pub const FUNC57_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x238);
-
-        /// address: 0x6000423c
-        /// GPIO input function configuration register
-        pub const FUNC58_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x23c);
-
-        /// address: 0x60004240
-        /// GPIO input function configuration register
-        pub const FUNC59_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x240);
-
-        /// address: 0x60004244
-        /// GPIO input function configuration register
-        pub const FUNC60_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x244);
-
-        /// address: 0x60004248
-        /// GPIO input function configuration register
-        pub const FUNC61_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x248);
-
-        /// address: 0x6000424c
-        /// GPIO input function configuration register
-        pub const FUNC62_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x24c);
-
-        /// address: 0x60004250
-        /// GPIO input function configuration register
-        pub const FUNC63_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x250);
-
-        /// address: 0x60004254
-        /// GPIO input function configuration register
-        pub const FUNC64_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x254);
-
-        /// address: 0x60004258
-        /// GPIO input function configuration register
-        pub const FUNC65_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x258);
-
-        /// address: 0x6000425c
-        /// GPIO input function configuration register
-        pub const FUNC66_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x25c);
-
-        /// address: 0x60004260
-        /// GPIO input function configuration register
-        pub const FUNC67_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x260);
-
-        /// address: 0x60004264
-        /// GPIO input function configuration register
-        pub const FUNC68_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x264);
-
-        /// address: 0x60004268
-        /// GPIO input function configuration register
-        pub const FUNC69_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x268);
-
-        /// address: 0x6000426c
-        /// GPIO input function configuration register
-        pub const FUNC70_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x26c);
-
-        /// address: 0x60004270
-        /// GPIO input function configuration register
-        pub const FUNC71_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x270);
-
-        /// address: 0x60004274
-        /// GPIO input function configuration register
-        pub const FUNC72_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x274);
-
-        /// address: 0x60004278
-        /// GPIO input function configuration register
-        pub const FUNC73_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x278);
-
-        /// address: 0x6000427c
-        /// GPIO input function configuration register
-        pub const FUNC74_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x27c);
-
-        /// address: 0x60004280
-        /// GPIO input function configuration register
-        pub const FUNC75_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x280);
-
-        /// address: 0x60004284
-        /// GPIO input function configuration register
-        pub const FUNC76_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x284);
-
-        /// address: 0x60004288
-        /// GPIO input function configuration register
-        pub const FUNC77_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x288);
-
-        /// address: 0x6000428c
-        /// GPIO input function configuration register
-        pub const FUNC78_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x28c);
-
-        /// address: 0x60004290
-        /// GPIO input function configuration register
-        pub const FUNC79_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x290);
-
-        /// address: 0x60004294
-        /// GPIO input function configuration register
-        pub const FUNC80_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x294);
-
-        /// address: 0x60004298
-        /// GPIO input function configuration register
-        pub const FUNC81_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x298);
-
-        /// address: 0x6000429c
-        /// GPIO input function configuration register
-        pub const FUNC82_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x29c);
-
-        /// address: 0x600042a0
-        /// GPIO input function configuration register
-        pub const FUNC83_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2a0);
-
-        /// address: 0x600042a4
-        /// GPIO input function configuration register
-        pub const FUNC84_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2a4);
-
-        /// address: 0x600042a8
-        /// GPIO input function configuration register
-        pub const FUNC85_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2a8);
-
-        /// address: 0x600042ac
-        /// GPIO input function configuration register
-        pub const FUNC86_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2ac);
-
-        /// address: 0x600042b0
-        /// GPIO input function configuration register
-        pub const FUNC87_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2b0);
-
-        /// address: 0x600042b4
-        /// GPIO input function configuration register
-        pub const FUNC88_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2b4);
-
-        /// address: 0x600042b8
-        /// GPIO input function configuration register
-        pub const FUNC89_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2b8);
-
-        /// address: 0x600042bc
-        /// GPIO input function configuration register
-        pub const FUNC90_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2bc);
-
-        /// address: 0x600042c0
-        /// GPIO input function configuration register
-        pub const FUNC91_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2c0);
-
-        /// address: 0x600042c4
-        /// GPIO input function configuration register
-        pub const FUNC92_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2c4);
-
-        /// address: 0x600042c8
-        /// GPIO input function configuration register
-        pub const FUNC93_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2c8);
-
-        /// address: 0x600042cc
-        /// GPIO input function configuration register
-        pub const FUNC94_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2cc);
-
-        /// address: 0x600042d0
-        /// GPIO input function configuration register
-        pub const FUNC95_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2d0);
-
-        /// address: 0x600042d4
-        /// GPIO input function configuration register
-        pub const FUNC96_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2d4);
-
-        /// address: 0x600042d8
-        /// GPIO input function configuration register
-        pub const FUNC97_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2d8);
-
-        /// address: 0x600042dc
-        /// GPIO input function configuration register
-        pub const FUNC98_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2dc);
-
-        /// address: 0x600042e0
-        /// GPIO input function configuration register
-        pub const FUNC99_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2e0);
-
-        /// address: 0x600042e4
-        /// GPIO input function configuration register
-        pub const FUNC100_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2e4);
-
-        /// address: 0x600042e8
-        /// GPIO input function configuration register
-        pub const FUNC101_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2e8);
-
-        /// address: 0x600042ec
-        /// GPIO input function configuration register
-        pub const FUNC102_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2ec);
-
-        /// address: 0x600042f0
-        /// GPIO input function configuration register
-        pub const FUNC103_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2f0);
-
-        /// address: 0x600042f4
-        /// GPIO input function configuration register
-        pub const FUNC104_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2f4);
-
-        /// address: 0x600042f8
-        /// GPIO input function configuration register
-        pub const FUNC105_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2f8);
-
-        /// address: 0x600042fc
-        /// GPIO input function configuration register
-        pub const FUNC106_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x2fc);
-
-        /// address: 0x60004300
-        /// GPIO input function configuration register
-        pub const FUNC107_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x300);
-
-        /// address: 0x60004304
-        /// GPIO input function configuration register
-        pub const FUNC108_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x304);
-
-        /// address: 0x60004308
-        /// GPIO input function configuration register
-        pub const FUNC109_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x308);
-
-        /// address: 0x6000430c
-        /// GPIO input function configuration register
-        pub const FUNC110_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x30c);
-
-        /// address: 0x60004310
-        /// GPIO input function configuration register
-        pub const FUNC111_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x310);
-
-        /// address: 0x60004314
-        /// GPIO input function configuration register
-        pub const FUNC112_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x314);
-
-        /// address: 0x60004318
-        /// GPIO input function configuration register
-        pub const FUNC113_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x318);
-
-        /// address: 0x6000431c
-        /// GPIO input function configuration register
-        pub const FUNC114_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x31c);
-
-        /// address: 0x60004320
-        /// GPIO input function configuration register
-        pub const FUNC115_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x320);
-
-        /// address: 0x60004324
-        /// GPIO input function configuration register
-        pub const FUNC116_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x324);
-
-        /// address: 0x60004328
-        /// GPIO input function configuration register
-        pub const FUNC117_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x328);
-
-        /// address: 0x6000432c
-        /// GPIO input function configuration register
-        pub const FUNC118_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x32c);
-
-        /// address: 0x60004330
-        /// GPIO input function configuration register
-        pub const FUNC119_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x330);
-
-        /// address: 0x60004334
-        /// GPIO input function configuration register
-        pub const FUNC120_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x334);
-
-        /// address: 0x60004338
-        /// GPIO input function configuration register
-        pub const FUNC121_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x338);
-
-        /// address: 0x6000433c
-        /// GPIO input function configuration register
-        pub const FUNC122_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x33c);
-
-        /// address: 0x60004340
-        /// GPIO input function configuration register
-        pub const FUNC123_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x340);
-
-        /// address: 0x60004344
-        /// GPIO input function configuration register
-        pub const FUNC124_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x344);
-
-        /// address: 0x60004348
-        /// GPIO input function configuration register
-        pub const FUNC125_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x348);
-
-        /// address: 0x6000434c
-        /// GPIO input function configuration register
-        pub const FUNC126_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x34c);
-
-        /// address: 0x60004350
-        /// GPIO input function configuration register
-        pub const FUNC127_IN_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always
-            /// high level. s=x3C: set this port always low level.
-            IN_SEL: u5,
-            /// set this bit to invert input signal. 1:invert. :not invert.
-            IN_INV_SEL: u1,
-            /// set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-            SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x350);
-
-        /// address: 0x60004554
-        /// GPIO output function select register
-        pub const FUNC0_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x554);
-
-        /// address: 0x60004558
-        /// GPIO output function select register
-        pub const FUNC1_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x558);
-
-        /// address: 0x6000455c
-        /// GPIO output function select register
-        pub const FUNC2_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x55c);
-
-        /// address: 0x60004560
-        /// GPIO output function select register
-        pub const FUNC3_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x560);
-
-        /// address: 0x60004564
-        /// GPIO output function select register
-        pub const FUNC4_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x564);
-
-        /// address: 0x60004568
-        /// GPIO output function select register
-        pub const FUNC5_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x568);
-
-        /// address: 0x6000456c
-        /// GPIO output function select register
-        pub const FUNC6_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x56c);
-
-        /// address: 0x60004570
-        /// GPIO output function select register
-        pub const FUNC7_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x570);
-
-        /// address: 0x60004574
-        /// GPIO output function select register
-        pub const FUNC8_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x574);
-
-        /// address: 0x60004578
-        /// GPIO output function select register
-        pub const FUNC9_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x578);
-
-        /// address: 0x6000457c
-        /// GPIO output function select register
-        pub const FUNC10_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x57c);
-
-        /// address: 0x60004580
-        /// GPIO output function select register
-        pub const FUNC11_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x580);
-
-        /// address: 0x60004584
-        /// GPIO output function select register
-        pub const FUNC12_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x584);
-
-        /// address: 0x60004588
-        /// GPIO output function select register
-        pub const FUNC13_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x588);
-
-        /// address: 0x6000458c
-        /// GPIO output function select register
-        pub const FUNC14_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x58c);
-
-        /// address: 0x60004590
-        /// GPIO output function select register
-        pub const FUNC15_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x590);
-
-        /// address: 0x60004594
-        /// GPIO output function select register
-        pub const FUNC16_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x594);
-
-        /// address: 0x60004598
-        /// GPIO output function select register
-        pub const FUNC17_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x598);
-
-        /// address: 0x6000459c
-        /// GPIO output function select register
-        pub const FUNC18_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x59c);
-
-        /// address: 0x600045a0
-        /// GPIO output function select register
-        pub const FUNC19_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5a0);
-
-        /// address: 0x600045a4
-        /// GPIO output function select register
-        pub const FUNC20_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5a4);
-
-        /// address: 0x600045a8
-        /// GPIO output function select register
-        pub const FUNC21_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5a8);
-
-        /// address: 0x600045ac
-        /// GPIO output function select register
-        pub const FUNC22_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5ac);
-
-        /// address: 0x600045b0
-        /// GPIO output function select register
-        pub const FUNC23_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5b0);
-
-        /// address: 0x600045b4
-        /// GPIO output function select register
-        pub const FUNC24_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5b4);
-
-        /// address: 0x600045b8
-        /// GPIO output function select register
-        pub const FUNC25_OUT_SEL_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of the bits: <=s<=256. Set the value to select output signal. s=-255:
-            /// output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals
-            /// GPIO_OUT_REG[n].
-            OUT_SEL: u8,
-            /// set this bit to invert output signal.1:invert.:not invert.
-            INV_SEL: u1,
-            /// set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output
-            /// enable signal.:use peripheral output enable signal.
-            OEN_SEL: u1,
-            /// set this bit to invert output enable signal.1:invert.:not invert.
-            OEN_INV_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x5b8);
-
-        /// address: 0x6000462c
-        /// GPIO clock gate register
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this bit to enable GPIO clock gate
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x62c);
-
-        /// address: 0x600046fc
-        /// GPIO version register
-        pub const REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x6fc);
-    };
-
-    /// Sigma-Delta Modulation
-    pub const GPIOSD = struct {
-        pub const base_address = 0x60004f00;
-
-        /// address: 0x60004f00
-        /// Duty Cycle Configure Register of SDM%s
-        pub const SIGMADELTA0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This field is used to configure the duty cycle of sigma delta modulation output.
-            SD0_IN: u8,
-            /// This field is used to set a divider value to divide APB clock.
-            SD0_PRESCALE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60004f04
-        /// Duty Cycle Configure Register of SDM%s
-        pub const SIGMADELTA1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This field is used to configure the duty cycle of sigma delta modulation output.
-            SD0_IN: u8,
-            /// This field is used to set a divider value to divide APB clock.
-            SD0_PRESCALE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60004f08
-        /// Duty Cycle Configure Register of SDM%s
-        pub const SIGMADELTA2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This field is used to configure the duty cycle of sigma delta modulation output.
-            SD0_IN: u8,
-            /// This field is used to set a divider value to divide APB clock.
-            SD0_PRESCALE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x60004f0c
-        /// Duty Cycle Configure Register of SDM%s
-        pub const SIGMADELTA3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This field is used to configure the duty cycle of sigma delta modulation output.
-            SD0_IN: u8,
-            /// This field is used to set a divider value to divide APB clock.
-            SD0_PRESCALE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60004f20
-        /// Clock Gating Configure Register
-        pub const SIGMADELTA_CG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// Clock enable bit of configuration registers for sigma delta modulation.
-            CLK_EN: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60004f24
-        /// MISC Register
-        pub const SIGMADELTA_MISC = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            /// Clock enable bit of sigma delta modulation.
-            FUNCTION_CLK_EN: u1,
-            /// Reserved.
-            SPI_SWAP: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60004f28
-        /// Version Control Register
-        pub const SIGMADELTA_VERSION = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Version control register.
-            GPIO_SD_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x28);
-    };
-
-    /// HMAC (Hash-based Message Authentication Code) Accelerator
-    pub const HMAC = struct {
-        pub const base_address = 0x6003e000;
-
-        /// address: 0x6003e040
-        /// Process control register 0.
-        pub const SET_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x40);
-
-        /// address: 0x6003e044
-        /// Configure purpose.
-        pub const SET_PARA_PURPOSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set hmac parameter purpose.
-            PURPOSE_SET: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x6003e048
-        /// Configure key.
-        pub const SET_PARA_KEY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set hmac parameter key.
-            KEY_SET: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6003e04c
-        /// Finish initial configuration.
-        pub const SET_PARA_FINISH = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Finish hmac configuration.
-            SET_PARA_END: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x6003e050
-        /// Process control register 1.
-        pub const SET_MESSAGE_ONE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Call SHA to calculate one message block.
-            SET_TEXT_ONE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x6003e054
-        /// Process control register 2.
-        pub const SET_MESSAGE_ING = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Continue typical hmac.
-            SET_TEXT_ING: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x6003e058
-        /// Process control register 3.
-        pub const SET_MESSAGE_END = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Start hardware padding.
-            SET_TEXT_END: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6003e05c
-        /// Process control register 4.
-        pub const SET_RESULT_FINISH = @intToPtr(*volatile Mmio(32, packed struct {
-            /// After read result from upstream, then let hmac back to idle.
-            SET_RESULT_END: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x6003e060
-        /// Invalidate register 0.
-        pub const SET_INVALIDATE_JTAG = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x60);
-
-        /// address: 0x6003e064
-        /// Invalidate register 1.
-        pub const SET_INVALIDATE_DS = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x64);
-
-        /// address: 0x6003e068
-        /// Error register.
-        pub const QUERY_ERROR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Hmac configuration state. 0: key are agree with purpose. 1: error
-            QUREY_CHECK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6003e06c
-        /// Busy register.
-        pub const QUERY_BUSY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Hmac state. 1'b0: idle. 1'b1: busy
-            BUSY_STATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x6003e080
-        /// Message block memory.
-        pub const WR_MESSAGE_MEM = @intToPtr(*volatile [64]u8, base_address + 0x80);
-
-        /// address: 0x6003e0c0
-        /// Result from upstream.
-        pub const RD_RESULT_MEM = @intToPtr(*volatile [32]u8, base_address + 0xc0);
-
-        /// address: 0x6003e0f0
-        /// Process control register 5.
-        pub const SET_MESSAGE_PAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Start software padding.
-            SET_TEXT_PAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xf0);
-
-        /// address: 0x6003e0f4
-        /// Process control register 6.
-        pub const ONE_BLOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Don't have to do padding.
-            SET_ONE_BLOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xf4);
-
-        /// address: 0x6003e0f8
-        /// Jtag register 0.
-        pub const SOFT_JTAG_CTRL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xf8);
-
-        /// address: 0x6003e0fc
-        /// Jtag register 1.
-        pub const WR_JTAG = @intToPtr(*volatile u32, base_address + 0xfc);
-    };
-
-    /// I2C (Inter-Integrated Circuit) Controller
-    pub const I2C0 = struct {
-        pub const base_address = 0x60013000;
-
-        /// address: 0x60013000
-        /// I2C_SCL_LOW_PERIOD_REG
-        pub const SCL_LOW_PERIOD = @intToPtr(*volatile MmioInt(32, u9), base_address + 0x0);
-
-        /// address: 0x60013004
-        /// I2C_CTR_REG
-        pub const CTR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_sda_force_out
-            SDA_FORCE_OUT: u1,
-            /// reg_scl_force_out
-            SCL_FORCE_OUT: u1,
-            /// reg_sample_scl_level
-            SAMPLE_SCL_LEVEL: u1,
-            /// reg_rx_full_ack_level
-            RX_FULL_ACK_LEVEL: u1,
-            /// reg_ms_mode
-            MS_MODE: u1,
-            /// reg_trans_start
-            TRANS_START: u1,
-            /// reg_tx_lsb_first
-            TX_LSB_FIRST: u1,
-            /// reg_rx_lsb_first
-            RX_LSB_FIRST: u1,
-            /// reg_clk_en
-            CLK_EN: u1,
-            /// reg_arbitration_en
-            ARBITRATION_EN: u1,
-            /// reg_fsm_rst
-            FSM_RST: u1,
-            /// reg_conf_upgate
-            CONF_UPGATE: u1,
-            /// reg_slv_tx_auto_start_en
-            SLV_TX_AUTO_START_EN: u1,
-            /// reg_addr_10bit_rw_check_en
-            ADDR_10BIT_RW_CHECK_EN: u1,
-            /// reg_addr_broadcasting_en
-            ADDR_BROADCASTING_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60013008
-        /// I2C_SR_REG
-        pub const SR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_resp_rec
-            RESP_REC: u1,
-            /// reg_slave_rw
-            SLAVE_RW: u1,
-            reserved0: u1,
-            /// reg_arb_lost
-            ARB_LOST: u1,
-            /// reg_bus_busy
-            BUS_BUSY: u1,
-            /// reg_slave_addressed
-            SLAVE_ADDRESSED: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// reg_rxfifo_cnt
-            RXFIFO_CNT: u6,
-            /// reg_stretch_cause
-            STRETCH_CAUSE: u2,
-            reserved3: u1,
-            reserved4: u1,
-            /// reg_txfifo_cnt
-            TXFIFO_CNT: u6,
-            /// reg_scl_main_state_last
-            SCL_MAIN_STATE_LAST: u3,
-            reserved5: u1,
-            /// reg_scl_state_last
-            SCL_STATE_LAST: u3,
-            padding0: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6001300c
-        /// I2C_TO_REG
-        pub const TO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_time_out_value
-            TIME_OUT_VALUE: u5,
-            /// reg_time_out_en
-            TIME_OUT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60013010
-        /// I2C_SLAVE_ADDR_REG
-        pub const SLAVE_ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_slave_addr
-            SLAVE_ADDR: u15,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            /// reg_addr_10bit_en
-            ADDR_10BIT_EN: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60013014
-        /// I2C_FIFO_ST_REG
-        pub const FIFO_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_raddr
-            RXFIFO_RADDR: u5,
-            /// reg_rxfifo_waddr
-            RXFIFO_WADDR: u5,
-            /// reg_txfifo_raddr
-            TXFIFO_RADDR: u5,
-            /// reg_txfifo_waddr
-            TXFIFO_WADDR: u5,
-            reserved0: u1,
-            reserved1: u1,
-            /// reg_slave_rw_point
-            SLAVE_RW_POINT: u8,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60013018
-        /// I2C_FIFO_CONF_REG
-        pub const FIFO_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_wm_thrhd
-            RXFIFO_WM_THRHD: u5,
-            /// reg_txfifo_wm_thrhd
-            TXFIFO_WM_THRHD: u5,
-            /// reg_nonfifo_en
-            NONFIFO_EN: u1,
-            /// reg_fifo_addr_cfg_en
-            FIFO_ADDR_CFG_EN: u1,
-            /// reg_rx_fifo_rst
-            RX_FIFO_RST: u1,
-            /// reg_tx_fifo_rst
-            TX_FIFO_RST: u1,
-            /// reg_fifo_prt_en
-            FIFO_PRT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6001301c
-        /// I2C_FIFO_DATA_REG
-        pub const DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_fifo_rdata
-            FIFO_RDATA: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60013020
-        /// I2C_INT_RAW_REG
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_wm_int_raw
-            RXFIFO_WM_INT_RAW: u1,
-            /// reg_txfifo_wm_int_raw
-            TXFIFO_WM_INT_RAW: u1,
-            /// reg_rxfifo_ovf_int_raw
-            RXFIFO_OVF_INT_RAW: u1,
-            /// reg_end_detect_int_raw
-            END_DETECT_INT_RAW: u1,
-            /// reg_byte_trans_done_int_raw
-            BYTE_TRANS_DONE_INT_RAW: u1,
-            /// reg_arbitration_lost_int_raw
-            ARBITRATION_LOST_INT_RAW: u1,
-            /// reg_mst_txfifo_udf_int_raw
-            MST_TXFIFO_UDF_INT_RAW: u1,
-            /// reg_trans_complete_int_raw
-            TRANS_COMPLETE_INT_RAW: u1,
-            /// reg_time_out_int_raw
-            TIME_OUT_INT_RAW: u1,
-            /// reg_trans_start_int_raw
-            TRANS_START_INT_RAW: u1,
-            /// reg_nack_int_raw
-            NACK_INT_RAW: u1,
-            /// reg_txfifo_ovf_int_raw
-            TXFIFO_OVF_INT_RAW: u1,
-            /// reg_rxfifo_udf_int_raw
-            RXFIFO_UDF_INT_RAW: u1,
-            /// reg_scl_st_to_int_raw
-            SCL_ST_TO_INT_RAW: u1,
-            /// reg_scl_main_st_to_int_raw
-            SCL_MAIN_ST_TO_INT_RAW: u1,
-            /// reg_det_start_int_raw
-            DET_START_INT_RAW: u1,
-            /// reg_slave_stretch_int_raw
-            SLAVE_STRETCH_INT_RAW: u1,
-            /// reg_general_call_int_raw
-            GENERAL_CALL_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60013024
-        /// I2C_INT_CLR_REG
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_wm_int_clr
-            RXFIFO_WM_INT_CLR: u1,
-            /// reg_txfifo_wm_int_clr
-            TXFIFO_WM_INT_CLR: u1,
-            /// reg_rxfifo_ovf_int_clr
-            RXFIFO_OVF_INT_CLR: u1,
-            /// reg_end_detect_int_clr
-            END_DETECT_INT_CLR: u1,
-            /// reg_byte_trans_done_int_clr
-            BYTE_TRANS_DONE_INT_CLR: u1,
-            /// reg_arbitration_lost_int_clr
-            ARBITRATION_LOST_INT_CLR: u1,
-            /// reg_mst_txfifo_udf_int_clr
-            MST_TXFIFO_UDF_INT_CLR: u1,
-            /// reg_trans_complete_int_clr
-            TRANS_COMPLETE_INT_CLR: u1,
-            /// reg_time_out_int_clr
-            TIME_OUT_INT_CLR: u1,
-            /// reg_trans_start_int_clr
-            TRANS_START_INT_CLR: u1,
-            /// reg_nack_int_clr
-            NACK_INT_CLR: u1,
-            /// reg_txfifo_ovf_int_clr
-            TXFIFO_OVF_INT_CLR: u1,
-            /// reg_rxfifo_udf_int_clr
-            RXFIFO_UDF_INT_CLR: u1,
-            /// reg_scl_st_to_int_clr
-            SCL_ST_TO_INT_CLR: u1,
-            /// reg_scl_main_st_to_int_clr
-            SCL_MAIN_ST_TO_INT_CLR: u1,
-            /// reg_det_start_int_clr
-            DET_START_INT_CLR: u1,
-            /// reg_slave_stretch_int_clr
-            SLAVE_STRETCH_INT_CLR: u1,
-            /// reg_general_call_int_clr
-            GENERAL_CALL_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60013028
-        /// I2C_INT_ENA_REG
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_wm_int_ena
-            RXFIFO_WM_INT_ENA: u1,
-            /// reg_txfifo_wm_int_ena
-            TXFIFO_WM_INT_ENA: u1,
-            /// reg_rxfifo_ovf_int_ena
-            RXFIFO_OVF_INT_ENA: u1,
-            /// reg_end_detect_int_ena
-            END_DETECT_INT_ENA: u1,
-            /// reg_byte_trans_done_int_ena
-            BYTE_TRANS_DONE_INT_ENA: u1,
-            /// reg_arbitration_lost_int_ena
-            ARBITRATION_LOST_INT_ENA: u1,
-            /// reg_mst_txfifo_udf_int_ena
-            MST_TXFIFO_UDF_INT_ENA: u1,
-            /// reg_trans_complete_int_ena
-            TRANS_COMPLETE_INT_ENA: u1,
-            /// reg_time_out_int_ena
-            TIME_OUT_INT_ENA: u1,
-            /// reg_trans_start_int_ena
-            TRANS_START_INT_ENA: u1,
-            /// reg_nack_int_ena
-            NACK_INT_ENA: u1,
-            /// reg_txfifo_ovf_int_ena
-            TXFIFO_OVF_INT_ENA: u1,
-            /// reg_rxfifo_udf_int_ena
-            RXFIFO_UDF_INT_ENA: u1,
-            /// reg_scl_st_to_int_ena
-            SCL_ST_TO_INT_ENA: u1,
-            /// reg_scl_main_st_to_int_ena
-            SCL_MAIN_ST_TO_INT_ENA: u1,
-            /// reg_det_start_int_ena
-            DET_START_INT_ENA: u1,
-            /// reg_slave_stretch_int_ena
-            SLAVE_STRETCH_INT_ENA: u1,
-            /// reg_general_call_int_ena
-            GENERAL_CALL_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6001302c
-        /// I2C_INT_STATUS_REG
-        pub const INT_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rxfifo_wm_int_st
-            RXFIFO_WM_INT_ST: u1,
-            /// reg_txfifo_wm_int_st
-            TXFIFO_WM_INT_ST: u1,
-            /// reg_rxfifo_ovf_int_st
-            RXFIFO_OVF_INT_ST: u1,
-            /// reg_end_detect_int_st
-            END_DETECT_INT_ST: u1,
-            /// reg_byte_trans_done_int_st
-            BYTE_TRANS_DONE_INT_ST: u1,
-            /// reg_arbitration_lost_int_st
-            ARBITRATION_LOST_INT_ST: u1,
-            /// reg_mst_txfifo_udf_int_st
-            MST_TXFIFO_UDF_INT_ST: u1,
-            /// reg_trans_complete_int_st
-            TRANS_COMPLETE_INT_ST: u1,
-            /// reg_time_out_int_st
-            TIME_OUT_INT_ST: u1,
-            /// reg_trans_start_int_st
-            TRANS_START_INT_ST: u1,
-            /// reg_nack_int_st
-            NACK_INT_ST: u1,
-            /// reg_txfifo_ovf_int_st
-            TXFIFO_OVF_INT_ST: u1,
-            /// reg_rxfifo_udf_int_st
-            RXFIFO_UDF_INT_ST: u1,
-            /// reg_scl_st_to_int_st
-            SCL_ST_TO_INT_ST: u1,
-            /// reg_scl_main_st_to_int_st
-            SCL_MAIN_ST_TO_INT_ST: u1,
-            /// reg_det_start_int_st
-            DET_START_INT_ST: u1,
-            /// reg_slave_stretch_int_st
-            SLAVE_STRETCH_INT_ST: u1,
-            /// reg_general_call_int_st
-            GENERAL_CALL_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60013030
-        /// I2C_SDA_HOLD_REG
-        pub const SDA_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_sda_hold_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60013034
-        /// I2C_SDA_SAMPLE_REG
-        pub const SDA_SAMPLE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_sda_sample_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60013038
-        /// I2C_SCL_HIGH_PERIOD_REG
-        pub const SCL_HIGH_PERIOD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_high_period
-            SCL_HIGH_PERIOD: u9,
-            /// reg_scl_wait_high_period
-            SCL_WAIT_HIGH_PERIOD: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x60013040
-        /// I2C_SCL_START_HOLD_REG
-        pub const SCL_START_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_start_hold_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60013044
-        /// I2C_SCL_RSTART_SETUP_REG
-        pub const SCL_RSTART_SETUP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_rstart_setup_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60013048
-        /// I2C_SCL_STOP_HOLD_REG
-        pub const SCL_STOP_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_stop_hold_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6001304c
-        /// I2C_SCL_STOP_SETUP_REG
-        pub const SCL_STOP_SETUP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_stop_setup_time
-            TIME: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60013050
-        /// I2C_FILTER_CFG_REG
-        pub const FILTER_CFG = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_filter_thres
-            SCL_FILTER_THRES: u4,
-            /// reg_sda_filter_thres
-            SDA_FILTER_THRES: u4,
-            /// reg_scl_filter_en
-            SCL_FILTER_EN: u1,
-            /// reg_sda_filter_en
-            SDA_FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60013054
-        /// I2C_CLK_CONF_REG
-        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_sclk_div_num
-            SCLK_DIV_NUM: u8,
-            /// reg_sclk_div_a
-            SCLK_DIV_A: u6,
-            /// reg_sclk_div_b
-            SCLK_DIV_B: u6,
-            /// reg_sclk_sel
-            SCLK_SEL: u1,
-            /// reg_sclk_active
-            SCLK_ACTIVE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60013058
-        /// I2C_COMD%s_REG
-        pub const COMD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6001305c
-        /// I2C_COMD%s_REG
-        pub const COMD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60013060
-        /// I2C_COMD%s_REG
-        pub const COMD2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60013064
-        /// I2C_COMD%s_REG
-        pub const COMD3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60013068
-        /// I2C_COMD%s_REG
-        pub const COMD4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6001306c
-        /// I2C_COMD%s_REG
-        pub const COMD5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60013070
-        /// I2C_COMD%s_REG
-        pub const COMD6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60013074
-        /// I2C_COMD%s_REG
-        pub const COMD7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_command
-            COMMAND: u14,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            /// reg_command_done
-            COMMAND_DONE: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60013078
-        /// I2C_SCL_ST_TIME_OUT_REG
-        pub const SCL_ST_TIME_OUT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_st_to_regno more than 23
-            SCL_ST_TO_I2C: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6001307c
-        /// I2C_SCL_MAIN_ST_TIME_OUT_REG
-        pub const SCL_MAIN_ST_TIME_OUT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_main_st_to_regno more than 23
-            SCL_MAIN_ST_TO_I2C: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x60013080
-        /// I2C_SCL_SP_CONF_REG
-        pub const SCL_SP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_scl_rst_slv_en
-            SCL_RST_SLV_EN: u1,
-            /// reg_scl_rst_slv_num
-            SCL_RST_SLV_NUM: u5,
-            /// reg_scl_pd_en
-            SCL_PD_EN: u1,
-            /// reg_sda_pd_en
-            SDA_PD_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x60013084
-        /// I2C_SCL_STRETCH_CONF_REG
-        pub const SCL_STRETCH_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_stretch_protect_num
-            STRETCH_PROTECT_NUM: u10,
-            /// reg_slave_scl_stretch_en
-            SLAVE_SCL_STRETCH_EN: u1,
-            /// reg_slave_scl_stretch_clr
-            SLAVE_SCL_STRETCH_CLR: u1,
-            /// reg_slave_byte_ack_ctl_en
-            SLAVE_BYTE_ACK_CTL_EN: u1,
-            /// reg_slave_byte_ack_lvl
-            SLAVE_BYTE_ACK_LVL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x600130f8
-        /// I2C_DATE_REG
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0xf8);
-
-        /// address: 0x60013100
-        /// I2C_TXFIFO_START_ADDR_REG
-        pub const TXFIFO_START_ADDR = @intToPtr(*volatile u32, base_address + 0x100);
-
-        /// address: 0x60013180
-        /// I2C_RXFIFO_START_ADDR_REG
-        pub const RXFIFO_START_ADDR = @intToPtr(*volatile u32, base_address + 0x180);
-    };
-
-    /// I2S (Inter-IC Sound) Controller
-    pub const I2S = struct {
-        pub const base_address = 0x6002d000;
-
-        /// address: 0x6002d00c
-        /// I2S interrupt raw register, valid in level.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt status bit for the i2s_rx_done_int interrupt
-            RX_DONE_INT_RAW: u1,
-            /// The raw interrupt status bit for the i2s_tx_done_int interrupt
-            TX_DONE_INT_RAW: u1,
-            /// The raw interrupt status bit for the i2s_rx_hung_int interrupt
-            RX_HUNG_INT_RAW: u1,
-            /// The raw interrupt status bit for the i2s_tx_hung_int interrupt
-            TX_HUNG_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x6002d010
-        /// I2S interrupt status register.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The masked interrupt status bit for the i2s_rx_done_int interrupt
-            RX_DONE_INT_ST: u1,
-            /// The masked interrupt status bit for the i2s_tx_done_int interrupt
-            TX_DONE_INT_ST: u1,
-            /// The masked interrupt status bit for the i2s_rx_hung_int interrupt
-            RX_HUNG_INT_ST: u1,
-            /// The masked interrupt status bit for the i2s_tx_hung_int interrupt
-            TX_HUNG_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x6002d014
-        /// I2S interrupt enable register.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The interrupt enable bit for the i2s_rx_done_int interrupt
-            RX_DONE_INT_ENA: u1,
-            /// The interrupt enable bit for the i2s_tx_done_int interrupt
-            TX_DONE_INT_ENA: u1,
-            /// The interrupt enable bit for the i2s_rx_hung_int interrupt
-            RX_HUNG_INT_ENA: u1,
-            /// The interrupt enable bit for the i2s_tx_hung_int interrupt
-            TX_HUNG_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x6002d018
-        /// I2S interrupt clear register.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the i2s_rx_done_int interrupt
-            RX_DONE_INT_CLR: u1,
-            /// Set this bit to clear the i2s_tx_done_int interrupt
-            TX_DONE_INT_CLR: u1,
-            /// Set this bit to clear the i2s_rx_hung_int interrupt
-            RX_HUNG_INT_CLR: u1,
-            /// Set this bit to clear the i2s_tx_hung_int interrupt
-            TX_HUNG_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6002d020
-        /// I2S RX configure register
-        pub const RX_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to reset receiver
-            RX_RESET: u1,
-            /// Set this bit to reset Rx AFIFO
-            RX_FIFO_RESET: u1,
-            /// Set this bit to start receiving data
-            RX_START: u1,
-            /// Set this bit to enable slave receiver mode
-            RX_SLAVE_MOD: u1,
-            reserved0: u1,
-            /// Set this bit to enable receiver in mono mode
-            RX_MONO: u1,
-            reserved1: u1,
-            /// I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr
-            /// value.
-            RX_BIG_ENDIAN: u1,
-            /// Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain.
-            /// This bit will be cleared by hardware after update register done.
-            RX_UPDATE: u1,
-            /// 1: The first channel data value is valid in I2S RX mono mode. 0: The second
-            /// channel data value is valid in I2S RX mono mode.
-            RX_MONO_FST_VLD: u1,
-            /// I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-            /// (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress.
-            /// &
-            RX_PCM_CONF: u2,
-            /// Set this bit to bypass Compress/Decompress module for received data.
-            RX_PCM_BYPASS: u1,
-            /// 0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is
-            /// 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
-            RX_STOP_MODE: u2,
-            /// 1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
-            RX_LEFT_ALIGN: u1,
-            /// 1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
-            RX_24_FILL_EN: u1,
-            /// 0: WS should be 0 when receiving left channel data, and WS is 1in right channel.
-            /// 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
-            RX_WS_IDLE_POL: u1,
-            /// I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the
-            /// MSB is received first.
-            RX_BIT_ORDER: u1,
-            /// 1: Enable I2S TDM Rx mode . 0: Disable.
-            RX_TDM_EN: u1,
-            /// 1: Enable I2S PDM Rx mode . 0: Disable.
-            RX_PDM_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x6002d024
-        /// I2S TX configure register
-        pub const TX_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to reset transmitter
-            TX_RESET: u1,
-            /// Set this bit to reset Tx AFIFO
-            TX_FIFO_RESET: u1,
-            /// Set this bit to start transmitting data
-            TX_START: u1,
-            /// Set this bit to enable slave transmitter mode
-            TX_SLAVE_MOD: u1,
-            reserved0: u1,
-            /// Set this bit to enable transmitter in mono mode
-            TX_MONO: u1,
-            /// 1: The value of Left channel data is equal to the value of right channel data in
-            /// I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is
-            /// reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
-            TX_CHAN_EQUAL: u1,
-            /// I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr
-            /// value.
-            TX_BIG_ENDIAN: u1,
-            /// Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain.
-            /// This bit will be cleared by hardware after update register done.
-            TX_UPDATE: u1,
-            /// 1: The first channel data value is valid in I2S TX mono mode. 0: The second
-            /// channel data value is valid in I2S TX mono mode.
-            TX_MONO_FST_VLD: u1,
-            /// I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1
-            /// (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress.
-            /// &
-            TX_PCM_CONF: u2,
-            /// Set this bit to bypass Compress/Decompress module for transmitted data.
-            TX_PCM_BYPASS: u1,
-            /// Set this bit to stop disable output BCK signal and WS signal when tx FIFO is
-            /// emtpy
-            TX_STOP_EN: u1,
-            reserved1: u1,
-            /// 1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
-            TX_LEFT_ALIGN: u1,
-            /// 1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
-            TX_24_FILL_EN: u1,
-            /// 0: WS should be 0 when sending left channel data, and WS is 1in right channel.
-            /// 1: WS should be 1 when sending left channel data, and WS is 0in right channel.
-            TX_WS_IDLE_POL: u1,
-            /// I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB
-            /// is sent first.
-            TX_BIT_ORDER: u1,
-            /// 1: Enable I2S TDM Tx mode . 0: Disable.
-            TX_TDM_EN: u1,
-            /// 1: Enable I2S PDM Tx mode . 0: Disable.
-            TX_PDM_EN: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            /// I2S transmitter channel mode configuration bits.
-            TX_CHAN_MOD: u3,
-            /// Enable signal loop back mode with transmitter module and receiver module sharing
-            /// the same WS and BCK signals.
-            SIG_LOOPBACK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x6002d028
-        /// I2S RX configure register 1
-        pub const RX_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
-            RX_TDM_WS_WIDTH: u7,
-            /// Bit clock configuration bits in receiver mode.
-            RX_BCK_DIV_NUM: u6,
-            /// Set the bits to configure the valid data bit length of I2S receiver channel. 7:
-            /// all the valid channel data is in 8-bit-mode. 15: all the valid channel data is
-            /// in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the
-            /// valid channel data is in 32-bit-mode.
-            RX_BITS_MOD: u5,
-            /// I2S Rx half sample bits -1.
-            RX_HALF_SAMPLE_BITS: u6,
-            /// The Rx bit number for each channel minus 1in TDM mode.
-            RX_TDM_CHAN_BITS: u5,
-            /// Set this bit to enable receiver in Phillips standard mode
-            RX_MSB_SHIFT: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6002d02c
-        /// I2S TX configure register 1
-        pub const TX_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
-            TX_TDM_WS_WIDTH: u7,
-            /// Bit clock configuration bits in transmitter mode.
-            TX_BCK_DIV_NUM: u6,
-            /// Set the bits to configure the valid data bit length of I2S transmitter channel.
-            /// 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data
-            /// is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the
-            /// valid channel data is in 32-bit-mode.
-            TX_BITS_MOD: u5,
-            /// I2S Tx half sample bits -1.
-            TX_HALF_SAMPLE_BITS: u6,
-            /// The Tx bit number for each channel minus 1in TDM mode.
-            TX_TDM_CHAN_BITS: u5,
-            /// Set this bit to enable transmitter in Phillips standard mode
-            TX_MSB_SHIFT: u1,
-            /// 1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed
-            /// to generate pos/neg edge in master mode.
-            TX_BCK_NO_DLY: u1,
-            padding0: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x6002d030
-        /// I2S RX clock configure register
-        pub const RX_CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Integral I2S clock divider value
-            RX_CLKM_DIV_NUM: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// I2S Rx module clock enable signal.
-            RX_CLK_ACTIVE: u1,
-            /// Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3:
-            /// I2S_MCLK_in.
-            RX_CLK_SEL: u2,
-            /// 0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as
-            /// I2S_MCLK_OUT.
-            MCLK_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x6002d034
-        /// I2S TX clock configure register
-        pub const TX_CLKM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will
-            /// be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <=
-            /// a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x *
-            /// (n+1)-div] + y * (n+1)-div.
-            TX_CLKM_DIV_NUM: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// I2S Tx module clock enable signal.
-            TX_CLK_ACTIVE: u1,
-            /// Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3:
-            /// I2S_MCLK_in.
-            TX_CLK_SEL: u2,
-            /// Set this bit to enable clk gate
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x6002d038
-        /// I2S RX module clock divider configure register
-        pub const RX_CLKM_DIV_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of
-            /// I2S_RX_CLKM_DIV_Z is (a-b).
-            RX_CLKM_DIV_Z: u9,
-            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value
-            /// of I2S_RX_CLKM_DIV_Y is (a%(a-b)).
-            RX_CLKM_DIV_Y: u9,
-            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the
-            /// value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
-            RX_CLKM_DIV_X: u9,
-            /// For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-            /// I2S_RX_CLKM_DIV_YN1 is 1.
-            RX_CLKM_DIV_YN1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6002d03c
-        /// I2S TX module clock divider configure register
-        pub const TX_CLKM_DIV_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of
-            /// I2S_TX_CLKM_DIV_Z is (a-b).
-            TX_CLKM_DIV_Z: u9,
-            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value
-            /// of I2S_TX_CLKM_DIV_Y is (a%(a-b)).
-            TX_CLKM_DIV_Y: u9,
-            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the
-            /// value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
-            TX_CLKM_DIV_X: u9,
-            /// For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of
-            /// I2S_TX_CLKM_DIV_YN1 is 1.
-            TX_CLKM_DIV_YN1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x6002d040
-        /// I2S TX PCM2PDM configuration register
-        pub const TX_PCM2PDM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// I2S TX PDM bypass hp filter or not. The option has been removed.
-            TX_PDM_HP_BYPASS: u1,
-            /// I2S TX PDM OSR2 value
-            TX_PDM_SINC_OSR2: u4,
-            /// I2S TX PDM prescale for sigmadelta
-            TX_PDM_PRESCALE: u8,
-            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-            TX_PDM_HP_IN_SHIFT: u2,
-            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-            TX_PDM_LP_IN_SHIFT: u2,
-            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-            TX_PDM_SINC_IN_SHIFT: u2,
-            /// I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-            TX_PDM_SIGMADELTA_IN_SHIFT: u2,
-            /// I2S TX PDM sigmadelta dither2 value
-            TX_PDM_SIGMADELTA_DITHER2: u1,
-            /// I2S TX PDM sigmadelta dither value
-            TX_PDM_SIGMADELTA_DITHER: u1,
-            /// I2S TX PDM dac mode enable
-            TX_PDM_DAC_2OUT_EN: u1,
-            /// I2S TX PDM dac 2channel enable
-            TX_PDM_DAC_MODE_EN: u1,
-            /// I2S TX PDM Converter enable
-            PCM2PDM_CONV_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x6002d044
-        /// I2S TX PCM2PDM configuration register
-        pub const TX_PCM2PDM_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// I2S TX PDM Fp
-            TX_PDM_FP: u10,
-            /// I2S TX PDM Fs
-            TX_PDM_FS: u10,
-            /// The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 +
-            /// I2S_TX_IIR_HP_MULT12_5[2:0])
-            TX_IIR_HP_MULT12_5: u3,
-            /// The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 +
-            /// I2S_TX_IIR_HP_MULT12_0[2:0])
-            TX_IIR_HP_MULT12_0: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x6002d050
-        /// I2S TX TDM mode control register
-        pub const RX_TDM_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN0_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN1_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN2_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN3_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN4_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN5_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN6_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just
-            /// input 0 in this channel.
-            RX_TDM_PDM_CHAN7_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0
-            /// in this channel.
-            RX_TDM_CHAN8_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0
-            /// in this channel.
-            RX_TDM_CHAN9_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN10_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN11_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN12_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN13_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN14_EN: u1,
-            /// 1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input
-            /// 0 in this channel.
-            RX_TDM_CHAN15_EN: u1,
-            /// The total channel number of I2S TX TDM mode.
-            RX_TDM_TOT_CHAN_NUM: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x6002d054
-        /// I2S TX TDM mode control register
-        pub const TX_TDM_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN0_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN1_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN2_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN3_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN4_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN5_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN6_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN7_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN8_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output
-            /// 0 in this channel.
-            TX_TDM_CHAN9_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN10_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN11_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN12_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN13_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN14_EN: u1,
-            /// 1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just
-            /// output 0 in this channel.
-            TX_TDM_CHAN15_EN: u1,
-            /// The total channel number of I2S TX TDM mode.
-            TX_TDM_TOT_CHAN_NUM: u4,
-            /// When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels,
-            /// and only the data of the enabled channels is sent, then this bit should be set.
-            /// Clear it when all the data stored in DMA TX buffer is for enabled channels.
-            TX_TDM_SKIP_MSK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x6002d058
-        /// I2S RX timing control register
-        pub const RX_TIMING = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            RX_SD_IN_DM: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            RX_WS_OUT_DM: u2,
-            reserved14: u1,
-            reserved15: u1,
-            /// The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            RX_BCK_OUT_DM: u2,
-            reserved16: u1,
-            reserved17: u1,
-            /// The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            RX_WS_IN_DM: u2,
-            reserved18: u1,
-            reserved19: u1,
-            /// The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            RX_BCK_IN_DM: u2,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6002d05c
-        /// I2S TX timing control register
-        pub const TX_TIMING = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_SD_OUT_DM: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_SD1_OUT_DM: u2,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_WS_OUT_DM: u2,
-            reserved12: u1,
-            reserved13: u1,
-            /// The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_BCK_OUT_DM: u2,
-            reserved14: u1,
-            reserved15: u1,
-            /// The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_WS_IN_DM: u2,
-            reserved16: u1,
-            reserved17: u1,
-            /// The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2:
-            /// delay by neg edge. 3: not used.
-            TX_BCK_IN_DM: u2,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x6002d060
-        /// I2S HUNG configure register.
-        pub const LC_HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered
-            /// when fifo hung counter is equal to this value
-            LC_FIFO_TIMEOUT: u8,
-            /// The bits are used to scale tick counter threshold. The tick counter is reset
-            /// when counter value >= 88000/2^i2s_lc_fifo_timeout_shift
-            LC_FIFO_TIMEOUT_SHIFT: u3,
-            /// The enable bit for FIFO timeout
-            LC_FIFO_TIMEOUT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x6002d064
-        /// I2S RX data number control register.
-        pub const RXEOF_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) *
-            /// (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the
-            /// configured DMA RX channel.
-            RX_EOF_NUM: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x6002d068
-        /// I2S signal data register
-        pub const CONF_SIGLE_DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The configured constant channel data to be sent out.
-            SINGLE_DATA: u32,
-        }), base_address + 0x68);
-
-        /// address: 0x6002d06c
-        /// I2S TX status register
-        pub const STATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: i2s_tx is idle state. 0: i2s_tx is working.
-            TX_IDLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x6002d080
-        /// Version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x80);
-    };
-
-    /// Interrupt Core
-    pub const INTERRUPT_CORE0 = struct {
-        pub const base_address = 0x600c2000;
-
-        /// address: 0x600c2000
-        /// mac intr map register
-        pub const MAC_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x0);
-
-        /// address: 0x600c2004
-        /// mac nmi_intr map register
-        pub const MAC_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x4);
-
-        /// address: 0x600c2008
-        /// pwr intr map register
-        pub const PWR_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x8);
-
-        /// address: 0x600c200c
-        /// bb intr map register
-        pub const BB_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc);
-
-        /// address: 0x600c2010
-        /// bt intr map register
-        pub const BT_MAC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x10);
-
-        /// address: 0x600c2014
-        /// bb_bt intr map register
-        pub const BT_BB_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x14);
-
-        /// address: 0x600c2018
-        /// bb_bt_nmi intr map register
-        pub const BT_BB_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x18);
-
-        /// address: 0x600c201c
-        /// rwbt intr map register
-        pub const RWBT_IRQ_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x1c);
-
-        /// address: 0x600c2020
-        /// rwble intr map register
-        pub const RWBLE_IRQ_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x20);
-
-        /// address: 0x600c2024
-        /// rwbt_nmi intr map register
-        pub const RWBT_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x24);
-
-        /// address: 0x600c2028
-        /// rwble_nmi intr map register
-        pub const RWBLE_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x28);
-
-        /// address: 0x600c202c
-        /// i2c intr map register
-        pub const I2C_MST_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x2c);
-
-        /// address: 0x600c2030
-        /// slc0 intr map register
-        pub const SLC0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x30);
-
-        /// address: 0x600c2034
-        /// slc1 intr map register
-        pub const SLC1_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x34);
-
-        /// address: 0x600c2038
-        /// apb_ctrl intr map register
-        pub const APB_CTRL_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x38);
-
-        /// address: 0x600c203c
-        /// uchi0 intr map register
-        pub const UHCI0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x3c);
-
-        /// address: 0x600c2040
-        /// gpio intr map register
-        pub const GPIO_INTERRUPT_PRO_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x40);
-
-        /// address: 0x600c2044
-        /// gpio_pro intr map register
-        pub const GPIO_INTERRUPT_PRO_NMI_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x44);
-
-        /// address: 0x600c2048
-        /// gpio_pro_nmi intr map register
-        pub const SPI_INTR_1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x48);
-
-        /// address: 0x600c204c
-        /// spi1 intr map register
-        pub const SPI_INTR_2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x4c);
-
-        /// address: 0x600c2050
-        /// spi2 intr map register
-        pub const I2S1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x50);
-
-        /// address: 0x600c2054
-        /// i2s1 intr map register
-        pub const UART_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x54);
-
-        /// address: 0x600c2058
-        /// uart1 intr map register
-        pub const UART1_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x58);
-
-        /// address: 0x600c205c
-        /// ledc intr map register
-        pub const LEDC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x5c);
-
-        /// address: 0x600c2060
-        /// efuse intr map register
-        pub const EFUSE_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x60);
-
-        /// address: 0x600c2064
-        /// can intr map register
-        pub const CAN_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x64);
-
-        /// address: 0x600c2068
-        /// usb intr map register
-        pub const USB_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x68);
-
-        /// address: 0x600c206c
-        /// rtc intr map register
-        pub const RTC_CORE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x6c);
-
-        /// address: 0x600c2070
-        /// rmt intr map register
-        pub const RMT_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x70);
-
-        /// address: 0x600c2074
-        /// i2c intr map register
-        pub const I2C_EXT0_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x74);
-
-        /// address: 0x600c2078
-        /// timer1 intr map register
-        pub const TIMER_INT1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x78);
-
-        /// address: 0x600c207c
-        /// timer2 intr map register
-        pub const TIMER_INT2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x7c);
-
-        /// address: 0x600c2080
-        /// tg to intr map register
-        pub const TG_T0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x80);
-
-        /// address: 0x600c2084
-        /// tg wdt intr map register
-        pub const TG_WDT_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x84);
-
-        /// address: 0x600c2088
-        /// tg1 to intr map register
-        pub const TG1_T0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x88);
-
-        /// address: 0x600c208c
-        /// tg1 wdt intr map register
-        pub const TG1_WDT_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x8c);
-
-        /// address: 0x600c2090
-        /// cache ia intr map register
-        pub const CACHE_IA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x90);
-
-        /// address: 0x600c2094
-        /// systimer intr map register
-        pub const SYSTIMER_TARGET0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x94);
-
-        /// address: 0x600c2098
-        /// systimer target1 intr map register
-        pub const SYSTIMER_TARGET1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x98);
-
-        /// address: 0x600c209c
-        /// systimer target2 intr map register
-        pub const SYSTIMER_TARGET2_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x9c);
-
-        /// address: 0x600c20a0
-        /// spi mem reject intr map register
-        pub const SPI_MEM_REJECT_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa0);
-
-        /// address: 0x600c20a4
-        /// icache perload intr map register
-        pub const ICACHE_PRELOAD_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa4);
-
-        /// address: 0x600c20a8
-        /// icache sync intr map register
-        pub const ICACHE_SYNC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xa8);
-
-        /// address: 0x600c20ac
-        /// adc intr map register
-        pub const APB_ADC_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xac);
-
-        /// address: 0x600c20b0
-        /// dma ch0 intr map register
-        pub const DMA_CH0_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb0);
-
-        /// address: 0x600c20b4
-        /// dma ch1 intr map register
-        pub const DMA_CH1_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb4);
-
-        /// address: 0x600c20b8
-        /// dma ch2 intr map register
-        pub const DMA_CH2_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xb8);
-
-        /// address: 0x600c20bc
-        /// rsa intr map register
-        pub const RSA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xbc);
-
-        /// address: 0x600c20c0
-        /// aes intr map register
-        pub const AES_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc0);
-
-        /// address: 0x600c20c4
-        /// sha intr map register
-        pub const SHA_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc4);
-
-        /// address: 0x600c20c8
-        /// cpu from cpu 0 intr map register
-        pub const CPU_INTR_FROM_CPU_0_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xc8);
-
-        /// address: 0x600c20cc
-        /// cpu from cpu 0 intr map register
-        pub const CPU_INTR_FROM_CPU_1_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xcc);
-
-        /// address: 0x600c20d0
-        /// cpu from cpu 1 intr map register
-        pub const CPU_INTR_FROM_CPU_2_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd0);
-
-        /// address: 0x600c20d4
-        /// cpu from cpu 3 intr map register
-        pub const CPU_INTR_FROM_CPU_3_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd4);
-
-        /// address: 0x600c20d8
-        /// assist debug intr map register
-        pub const ASSIST_DEBUG_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xd8);
-
-        /// address: 0x600c20dc
-        /// dma pms violatile intr map register
-        pub const DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xdc);
-
-        /// address: 0x600c20e0
-        /// iram0 pms violatile intr map register
-        pub const CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe0);
-
-        /// address: 0x600c20e4
-        /// mac intr map register
-        pub const CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe4);
-
-        /// address: 0x600c20e8
-        /// mac intr map register
-        pub const CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xe8);
-
-        /// address: 0x600c20ec
-        /// mac intr map register
-        pub const CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xec);
-
-        /// address: 0x600c20f0
-        /// mac intr map register
-        pub const BACKUP_PMS_VIOLATE_INTR_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xf0);
-
-        /// address: 0x600c20f4
-        /// mac intr map register
-        pub const CACHE_CORE0_ACS_INT_MAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0xf4);
-
-        /// address: 0x600c20f8
-        /// mac intr map register
-        pub const INTR_STATUS_REG_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_intr_status_0
-            INTR_STATUS_0: u32,
-        }), base_address + 0xf8);
-
-        /// address: 0x600c20fc
-        /// mac intr map register
-        pub const INTR_STATUS_REG_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_intr_status_1
-            INTR_STATUS_1: u32,
-        }), base_address + 0xfc);
-
-        /// address: 0x600c2100
-        /// mac intr map register
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_reg_clk_en
-            REG_CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x600c2104
-        /// mac intr map register
-        pub const CPU_INT_ENABLE = @intToPtr(*volatile u32, base_address + 0x104);
-
-        /// address: 0x600c2108
-        /// mac intr map register
-        pub const CPU_INT_TYPE = @intToPtr(*volatile u32, base_address + 0x108);
-
-        /// address: 0x600c210c
-        /// mac intr map register
-        pub const CPU_INT_CLEAR = @intToPtr(*volatile u32, base_address + 0x10c);
-
-        /// address: 0x600c2110
-        /// mac intr map register
-        pub const CPU_INT_EIP_STATUS = @intToPtr(*volatile u32, base_address + 0x110);
-
-        /// address: 0x600c2114
-        /// mac intr map register
-        pub const CPU_INT_PRI_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_0_map
-            CPU_PRI_0_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x114);
-
-        /// address: 0x600c2118
-        /// mac intr map register
-        pub const CPU_INT_PRI_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_1_map
-            CPU_PRI_1_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x118);
-
-        /// address: 0x600c211c
-        /// mac intr map register
-        pub const CPU_INT_PRI_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_2_map
-            CPU_PRI_2_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x11c);
-
-        /// address: 0x600c2120
-        /// mac intr map register
-        pub const CPU_INT_PRI_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_3_map
-            CPU_PRI_3_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x120);
-
-        /// address: 0x600c2124
-        /// mac intr map register
-        pub const CPU_INT_PRI_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_4_map
-            CPU_PRI_4_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x124);
-
-        /// address: 0x600c2128
-        /// mac intr map register
-        pub const CPU_INT_PRI_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_5_map
-            CPU_PRI_5_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x128);
-
-        /// address: 0x600c212c
-        /// mac intr map register
-        pub const CPU_INT_PRI_6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_6_map
-            CPU_PRI_6_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x12c);
-
-        /// address: 0x600c2130
-        /// mac intr map register
-        pub const CPU_INT_PRI_7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_7_map
-            CPU_PRI_7_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x130);
-
-        /// address: 0x600c2134
-        /// mac intr map register
-        pub const CPU_INT_PRI_8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_8_map
-            CPU_PRI_8_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x134);
-
-        /// address: 0x600c2138
-        /// mac intr map register
-        pub const CPU_INT_PRI_9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_9_map
-            CPU_PRI_9_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x138);
-
-        /// address: 0x600c213c
-        /// mac intr map register
-        pub const CPU_INT_PRI_10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_10_map
-            CPU_PRI_10_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x13c);
-
-        /// address: 0x600c2140
-        /// mac intr map register
-        pub const CPU_INT_PRI_11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_11_map
-            CPU_PRI_11_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x140);
-
-        /// address: 0x600c2144
-        /// mac intr map register
-        pub const CPU_INT_PRI_12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_12_map
-            CPU_PRI_12_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x144);
-
-        /// address: 0x600c2148
-        /// mac intr map register
-        pub const CPU_INT_PRI_13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_13_map
-            CPU_PRI_13_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x148);
-
-        /// address: 0x600c214c
-        /// mac intr map register
-        pub const CPU_INT_PRI_14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_14_map
-            CPU_PRI_14_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x14c);
-
-        /// address: 0x600c2150
-        /// mac intr map register
-        pub const CPU_INT_PRI_15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_15_map
-            CPU_PRI_15_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x150);
-
-        /// address: 0x600c2154
-        /// mac intr map register
-        pub const CPU_INT_PRI_16 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_16_map
-            CPU_PRI_16_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x154);
-
-        /// address: 0x600c2158
-        /// mac intr map register
-        pub const CPU_INT_PRI_17 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_17_map
-            CPU_PRI_17_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x158);
-
-        /// address: 0x600c215c
-        /// mac intr map register
-        pub const CPU_INT_PRI_18 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_18_map
-            CPU_PRI_18_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x15c);
-
-        /// address: 0x600c2160
-        /// mac intr map register
-        pub const CPU_INT_PRI_19 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_19_map
-            CPU_PRI_19_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x160);
-
-        /// address: 0x600c2164
-        /// mac intr map register
-        pub const CPU_INT_PRI_20 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_20_map
-            CPU_PRI_20_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x164);
-
-        /// address: 0x600c2168
-        /// mac intr map register
-        pub const CPU_INT_PRI_21 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_21_map
-            CPU_PRI_21_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x168);
-
-        /// address: 0x600c216c
-        /// mac intr map register
-        pub const CPU_INT_PRI_22 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_22_map
-            CPU_PRI_22_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x16c);
-
-        /// address: 0x600c2170
-        /// mac intr map register
-        pub const CPU_INT_PRI_23 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_23_map
-            CPU_PRI_23_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x170);
-
-        /// address: 0x600c2174
-        /// mac intr map register
-        pub const CPU_INT_PRI_24 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_24_map
-            CPU_PRI_24_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x174);
-
-        /// address: 0x600c2178
-        /// mac intr map register
-        pub const CPU_INT_PRI_25 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_25_map
-            CPU_PRI_25_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x178);
-
-        /// address: 0x600c217c
-        /// mac intr map register
-        pub const CPU_INT_PRI_26 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_26_map
-            CPU_PRI_26_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x17c);
-
-        /// address: 0x600c2180
-        /// mac intr map register
-        pub const CPU_INT_PRI_27 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_27_map
-            CPU_PRI_27_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x180);
-
-        /// address: 0x600c2184
-        /// mac intr map register
-        pub const CPU_INT_PRI_28 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_28_map
-            CPU_PRI_28_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x184);
-
-        /// address: 0x600c2188
-        /// mac intr map register
-        pub const CPU_INT_PRI_29 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_29_map
-            CPU_PRI_29_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x188);
-
-        /// address: 0x600c218c
-        /// mac intr map register
-        pub const CPU_INT_PRI_30 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_30_map
-            CPU_PRI_30_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x18c);
-
-        /// address: 0x600c2190
-        /// mac intr map register
-        pub const CPU_INT_PRI_31 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_core0_cpu_pri_31_map
-            CPU_PRI_31_MAP: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x190);
-
-        /// address: 0x600c2194
-        /// mac intr map register
-        pub const CPU_INT_THRESH = @intToPtr(*volatile MmioInt(32, u4), base_address + 0x194);
-
-        /// address: 0x600c27fc
-        /// mac intr map register
-        pub const INTERRUPT_REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x7fc);
-    };
-
-    /// Input/Output Multiplexer
-    pub const IO_MUX = struct {
-        pub const base_address = 0x60009000;
-
-        /// address: 0x60009000
-        /// Clock Output Configuration Register
-        pub const PIN_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0.
-            /// CLK_OUT_out1 can be found in peripheral output signals.
-            CLK_OUT1: u4,
-            /// If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0.
-            /// CLK_OUT_out2 can be found in peripheral output signals.
-            CLK_OUT2: u4,
-            /// If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0.
-            /// CLK_OUT_out3 can be found in peripheral output signals.
-            CLK_OUT3: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60009004
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60009008
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000900c
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60009010
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60009014
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60009018
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000901c
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60009020
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60009024
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60009028
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6000902c
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60009030
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60009034
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60009038
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6000903c
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60009040
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60009044
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO16 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60009048
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO17 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6000904c
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO18 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60009050
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO19 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60009054
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO20 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60009058
-        /// IO MUX Configure Register for pad XTAL_32K_P
-        pub const GPIO21 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-            MCU_OE: u1,
-            /// Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-            SLP_SEL: u1,
-            /// Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0:
-            /// internal pull-down disabled.
-            MCU_WPD: u1,
-            /// Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0:
-            /// internal pull-up disabled.
-            MCU_WPU: u1,
-            /// Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-            MCU_IE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal
-            /// pull-down disabled.
-            FUN_WPD: u1,
-            /// Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up
-            /// disabled.
-            FUN_WPU: u1,
-            /// Input enable of the pad. 1: input enabled; 0: input disabled.
-            FUN_IE: u1,
-            /// Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-            FUN_DRV: u2,
-            /// Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function
-            /// 2; etc.
-            MCU_SEL: u3,
-            /// Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-            FILTER_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x600090fc
-        /// IO MUX Version Control Register
-        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Version control register
-            REG_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xfc);
-    };
-
-    /// LED Control PWM (Pulse Width Modulation)
-    pub const LEDC = struct {
-        pub const base_address = 0x60019000;
-
-        /// address: 0x60019000
-        /// LEDC_LSCH0_CONF0.
-        pub const LSCH0_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch0.
-            TIMER_SEL_LSCH0: u2,
-            /// reg_sig_out_en_lsch0.
-            SIG_OUT_EN_LSCH0: u1,
-            /// reg_idle_lv_lsch0.
-            IDLE_LV_LSCH0: u1,
-            /// reg_para_up_lsch0.
-            PARA_UP_LSCH0: u1,
-            /// reg_ovf_num_lsch0.
-            OVF_NUM_LSCH0: u10,
-            /// reg_ovf_cnt_en_lsch0.
-            OVF_CNT_EN_LSCH0: u1,
-            /// reg_ovf_cnt_reset_lsch0.
-            OVF_CNT_RESET_LSCH0: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60019004
-        /// LEDC_LSCH0_HPOINT.
-        pub const LSCH0_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch0.
-            HPOINT_LSCH0: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60019008
-        /// LEDC_LSCH0_DUTY.
-        pub const LSCH0_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch0.
-            DUTY_LSCH0: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6001900c
-        /// LEDC_LSCH0_CONF1.
-        pub const LSCH0_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch0.
-            DUTY_SCALE_LSCH0: u10,
-            /// reg_duty_cycle_lsch0.
-            DUTY_CYCLE_LSCH0: u10,
-            /// reg_duty_num_lsch0.
-            DUTY_NUM_LSCH0: u10,
-            /// reg_duty_inc_lsch0.
-            DUTY_INC_LSCH0: u1,
-            /// reg_duty_start_lsch0.
-            DUTY_START_LSCH0: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60019010
-        /// LEDC_LSCH0_DUTY_R.
-        pub const LSCH0_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch0_r.
-            DUTY_LSCH0_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60019014
-        /// LEDC_LSCH1_CONF0.
-        pub const LSCH1_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch1.
-            TIMER_SEL_LSCH1: u2,
-            /// reg_sig_out_en_lsch1.
-            SIG_OUT_EN_LSCH1: u1,
-            /// reg_idle_lv_lsch1.
-            IDLE_LV_LSCH1: u1,
-            /// reg_para_up_lsch1.
-            PARA_UP_LSCH1: u1,
-            /// reg_ovf_num_lsch1.
-            OVF_NUM_LSCH1: u10,
-            /// reg_ovf_cnt_en_lsch1.
-            OVF_CNT_EN_LSCH1: u1,
-            /// reg_ovf_cnt_reset_lsch1.
-            OVF_CNT_RESET_LSCH1: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60019018
-        /// LEDC_LSCH1_HPOINT.
-        pub const LSCH1_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch1.
-            HPOINT_LSCH1: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6001901c
-        /// LEDC_LSCH1_DUTY.
-        pub const LSCH1_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch1.
-            DUTY_LSCH1: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60019020
-        /// LEDC_LSCH1_CONF1.
-        pub const LSCH1_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch1.
-            DUTY_SCALE_LSCH1: u10,
-            /// reg_duty_cycle_lsch1.
-            DUTY_CYCLE_LSCH1: u10,
-            /// reg_duty_num_lsch1.
-            DUTY_NUM_LSCH1: u10,
-            /// reg_duty_inc_lsch1.
-            DUTY_INC_LSCH1: u1,
-            /// reg_duty_start_lsch1.
-            DUTY_START_LSCH1: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60019024
-        /// LEDC_LSCH1_DUTY_R.
-        pub const LSCH1_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch1_r.
-            DUTY_LSCH1_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60019028
-        /// LEDC_LSCH2_CONF0.
-        pub const LSCH2_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch2.
-            TIMER_SEL_LSCH2: u2,
-            /// reg_sig_out_en_lsch2.
-            SIG_OUT_EN_LSCH2: u1,
-            /// reg_idle_lv_lsch2.
-            IDLE_LV_LSCH2: u1,
-            /// reg_para_up_lsch2.
-            PARA_UP_LSCH2: u1,
-            /// reg_ovf_num_lsch2.
-            OVF_NUM_LSCH2: u10,
-            /// reg_ovf_cnt_en_lsch2.
-            OVF_CNT_EN_LSCH2: u1,
-            /// reg_ovf_cnt_reset_lsch2.
-            OVF_CNT_RESET_LSCH2: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6001902c
-        /// LEDC_LSCH2_HPOINT.
-        pub const LSCH2_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch2.
-            HPOINT_LSCH2: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60019030
-        /// LEDC_LSCH2_DUTY.
-        pub const LSCH2_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch2.
-            DUTY_LSCH2: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60019034
-        /// LEDC_LSCH2_CONF1.
-        pub const LSCH2_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch2.
-            DUTY_SCALE_LSCH2: u10,
-            /// reg_duty_cycle_lsch2.
-            DUTY_CYCLE_LSCH2: u10,
-            /// reg_duty_num_lsch2.
-            DUTY_NUM_LSCH2: u10,
-            /// reg_duty_inc_lsch2.
-            DUTY_INC_LSCH2: u1,
-            /// reg_duty_start_lsch2.
-            DUTY_START_LSCH2: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60019038
-        /// LEDC_LSCH2_DUTY_R.
-        pub const LSCH2_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch2_r.
-            DUTY_LSCH2_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6001903c
-        /// LEDC_LSCH3_CONF0.
-        pub const LSCH3_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch3.
-            TIMER_SEL_LSCH3: u2,
-            /// reg_sig_out_en_lsch3.
-            SIG_OUT_EN_LSCH3: u1,
-            /// reg_idle_lv_lsch3.
-            IDLE_LV_LSCH3: u1,
-            /// reg_para_up_lsch3.
-            PARA_UP_LSCH3: u1,
-            /// reg_ovf_num_lsch3.
-            OVF_NUM_LSCH3: u10,
-            /// reg_ovf_cnt_en_lsch3.
-            OVF_CNT_EN_LSCH3: u1,
-            /// reg_ovf_cnt_reset_lsch3.
-            OVF_CNT_RESET_LSCH3: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60019040
-        /// LEDC_LSCH3_HPOINT.
-        pub const LSCH3_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch3.
-            HPOINT_LSCH3: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60019044
-        /// LEDC_LSCH3_DUTY.
-        pub const LSCH3_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch3.
-            DUTY_LSCH3: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60019048
-        /// LEDC_LSCH3_CONF1.
-        pub const LSCH3_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch3.
-            DUTY_SCALE_LSCH3: u10,
-            /// reg_duty_cycle_lsch3.
-            DUTY_CYCLE_LSCH3: u10,
-            /// reg_duty_num_lsch3.
-            DUTY_NUM_LSCH3: u10,
-            /// reg_duty_inc_lsch3.
-            DUTY_INC_LSCH3: u1,
-            /// reg_duty_start_lsch3.
-            DUTY_START_LSCH3: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6001904c
-        /// LEDC_LSCH3_DUTY_R.
-        pub const LSCH3_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch3_r.
-            DUTY_LSCH3_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60019050
-        /// LEDC_LSCH4_CONF0.
-        pub const LSCH4_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch4.
-            TIMER_SEL_LSCH4: u2,
-            /// reg_sig_out_en_lsch4.
-            SIG_OUT_EN_LSCH4: u1,
-            /// reg_idle_lv_lsch4.
-            IDLE_LV_LSCH4: u1,
-            /// reg_para_up_lsch4.
-            PARA_UP_LSCH4: u1,
-            /// reg_ovf_num_lsch4.
-            OVF_NUM_LSCH4: u10,
-            /// reg_ovf_cnt_en_lsch4.
-            OVF_CNT_EN_LSCH4: u1,
-            /// reg_ovf_cnt_reset_lsch4.
-            OVF_CNT_RESET_LSCH4: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60019054
-        /// LEDC_LSCH4_HPOINT.
-        pub const LSCH4_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch4.
-            HPOINT_LSCH4: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60019058
-        /// LEDC_LSCH4_DUTY.
-        pub const LSCH4_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch4.
-            DUTY_LSCH4: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6001905c
-        /// LEDC_LSCH4_CONF1.
-        pub const LSCH4_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch4.
-            DUTY_SCALE_LSCH4: u10,
-            /// reg_duty_cycle_lsch4.
-            DUTY_CYCLE_LSCH4: u10,
-            /// reg_duty_num_lsch4.
-            DUTY_NUM_LSCH4: u10,
-            /// reg_duty_inc_lsch4.
-            DUTY_INC_LSCH4: u1,
-            /// reg_duty_start_lsch4.
-            DUTY_START_LSCH4: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60019060
-        /// LEDC_LSCH4_DUTY_R.
-        pub const LSCH4_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch4_r.
-            DUTY_LSCH4_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60019064
-        /// LEDC_LSCH5_CONF0.
-        pub const LSCH5_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timer_sel_lsch5.
-            TIMER_SEL_LSCH5: u2,
-            /// reg_sig_out_en_lsch5.
-            SIG_OUT_EN_LSCH5: u1,
-            /// reg_idle_lv_lsch5.
-            IDLE_LV_LSCH5: u1,
-            /// reg_para_up_lsch5.
-            PARA_UP_LSCH5: u1,
-            /// reg_ovf_num_lsch5.
-            OVF_NUM_LSCH5: u10,
-            /// reg_ovf_cnt_en_lsch5.
-            OVF_CNT_EN_LSCH5: u1,
-            /// reg_ovf_cnt_reset_lsch5.
-            OVF_CNT_RESET_LSCH5: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60019068
-        /// LEDC_LSCH5_HPOINT.
-        pub const LSCH5_HPOINT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_hpoint_lsch5.
-            HPOINT_LSCH5: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6001906c
-        /// LEDC_LSCH5_DUTY.
-        pub const LSCH5_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch5.
-            DUTY_LSCH5: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60019070
-        /// LEDC_LSCH5_CONF1.
-        pub const LSCH5_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_scale_lsch5.
-            DUTY_SCALE_LSCH5: u10,
-            /// reg_duty_cycle_lsch5.
-            DUTY_CYCLE_LSCH5: u10,
-            /// reg_duty_num_lsch5.
-            DUTY_NUM_LSCH5: u10,
-            /// reg_duty_inc_lsch5.
-            DUTY_INC_LSCH5: u1,
-            /// reg_duty_start_lsch5.
-            DUTY_START_LSCH5: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60019074
-        /// LEDC_LSCH5_DUTY_R.
-        pub const LSCH5_DUTY_R = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_duty_lsch5_r.
-            DUTY_LSCH5_R: u19,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x600190a0
-        /// LEDC_LSTIMER0_CONF.
-        pub const LSTIMER0_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_duty_res.
-            LSTIMER0_DUTY_RES: u4,
-            /// reg_clk_div_lstimer0.
-            CLK_DIV_LSTIMER0: u18,
-            /// reg_lstimer0_pause.
-            LSTIMER0_PAUSE: u1,
-            /// reg_lstimer0_rst.
-            LSTIMER0_RST: u1,
-            /// reg_tick_sel_lstimer0.
-            TICK_SEL_LSTIMER0: u1,
-            /// reg_lstimer0_para_up.
-            LSTIMER0_PARA_UP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x600190a4
-        /// LEDC_LSTIMER0_VALUE.
-        pub const LSTIMER0_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_cnt.
-            LSTIMER0_CNT: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600190a8
-        /// LEDC_LSTIMER1_CONF.
-        pub const LSTIMER1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer1_duty_res.
-            LSTIMER1_DUTY_RES: u4,
-            /// reg_clk_div_lstimer1.
-            CLK_DIV_LSTIMER1: u18,
-            /// reg_lstimer1_pause.
-            LSTIMER1_PAUSE: u1,
-            /// reg_lstimer1_rst.
-            LSTIMER1_RST: u1,
-            /// reg_tick_sel_lstimer1.
-            TICK_SEL_LSTIMER1: u1,
-            /// reg_lstimer1_para_up.
-            LSTIMER1_PARA_UP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600190ac
-        /// LEDC_LSTIMER1_VALUE.
-        pub const LSTIMER1_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer1_cnt.
-            LSTIMER1_CNT: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600190b0
-        /// LEDC_LSTIMER2_CONF.
-        pub const LSTIMER2_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer2_duty_res.
-            LSTIMER2_DUTY_RES: u4,
-            /// reg_clk_div_lstimer2.
-            CLK_DIV_LSTIMER2: u18,
-            /// reg_lstimer2_pause.
-            LSTIMER2_PAUSE: u1,
-            /// reg_lstimer2_rst.
-            LSTIMER2_RST: u1,
-            /// reg_tick_sel_lstimer2.
-            TICK_SEL_LSTIMER2: u1,
-            /// reg_lstimer2_para_up.
-            LSTIMER2_PARA_UP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x600190b4
-        /// LEDC_LSTIMER2_VALUE.
-        pub const LSTIMER2_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer2_cnt.
-            LSTIMER2_CNT: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600190b8
-        /// LEDC_LSTIMER3_CONF.
-        pub const LSTIMER3_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer3_duty_res.
-            LSTIMER3_DUTY_RES: u4,
-            /// reg_clk_div_lstimer3.
-            CLK_DIV_LSTIMER3: u18,
-            /// reg_lstimer3_pause.
-            LSTIMER3_PAUSE: u1,
-            /// reg_lstimer3_rst.
-            LSTIMER3_RST: u1,
-            /// reg_tick_sel_lstimer3.
-            TICK_SEL_LSTIMER3: u1,
-            /// reg_lstimer3_para_up.
-            LSTIMER3_PARA_UP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0xb8);
-
-        /// address: 0x600190bc
-        /// LEDC_LSTIMER3_VALUE.
-        pub const LSTIMER3_VALUE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer3_cnt.
-            LSTIMER3_CNT: u14,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0xbc);
-
-        /// address: 0x600190c0
-        /// LEDC_INT_RAW.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_ovf_int_raw.
-            LSTIMER0_OVF_INT_RAW: u1,
-            /// reg_lstimer1_ovf_int_raw.
-            LSTIMER1_OVF_INT_RAW: u1,
-            /// reg_lstimer2_ovf_int_raw.
-            LSTIMER2_OVF_INT_RAW: u1,
-            /// reg_lstimer3_ovf_int_raw.
-            LSTIMER3_OVF_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch0_int_raw.
-            DUTY_CHNG_END_LSCH0_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch1_int_raw.
-            DUTY_CHNG_END_LSCH1_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch2_int_raw.
-            DUTY_CHNG_END_LSCH2_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch3_int_raw.
-            DUTY_CHNG_END_LSCH3_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch4_int_raw.
-            DUTY_CHNG_END_LSCH4_INT_RAW: u1,
-            /// reg_duty_chng_end_lsch5_int_raw.
-            DUTY_CHNG_END_LSCH5_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch0_int_raw.
-            OVF_CNT_LSCH0_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch1_int_raw.
-            OVF_CNT_LSCH1_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch2_int_raw.
-            OVF_CNT_LSCH2_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch3_int_raw.
-            OVF_CNT_LSCH3_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch4_int_raw.
-            OVF_CNT_LSCH4_INT_RAW: u1,
-            /// reg_ovf_cnt_lsch5_int_raw.
-            OVF_CNT_LSCH5_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600190c4
-        /// LEDC_INT_ST.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_ovf_int_st.
-            LSTIMER0_OVF_INT_ST: u1,
-            /// reg_lstimer1_ovf_int_st.
-            LSTIMER1_OVF_INT_ST: u1,
-            /// reg_lstimer2_ovf_int_st.
-            LSTIMER2_OVF_INT_ST: u1,
-            /// reg_lstimer3_ovf_int_st.
-            LSTIMER3_OVF_INT_ST: u1,
-            /// reg_duty_chng_end_lsch0_int_st.
-            DUTY_CHNG_END_LSCH0_INT_ST: u1,
-            /// reg_duty_chng_end_lsch1_int_st.
-            DUTY_CHNG_END_LSCH1_INT_ST: u1,
-            /// reg_duty_chng_end_lsch2_int_st.
-            DUTY_CHNG_END_LSCH2_INT_ST: u1,
-            /// reg_duty_chng_end_lsch3_int_st.
-            DUTY_CHNG_END_LSCH3_INT_ST: u1,
-            /// reg_duty_chng_end_lsch4_int_st.
-            DUTY_CHNG_END_LSCH4_INT_ST: u1,
-            /// reg_duty_chng_end_lsch5_int_st.
-            DUTY_CHNG_END_LSCH5_INT_ST: u1,
-            /// reg_ovf_cnt_lsch0_int_st.
-            OVF_CNT_LSCH0_INT_ST: u1,
-            /// reg_ovf_cnt_lsch1_int_st.
-            OVF_CNT_LSCH1_INT_ST: u1,
-            /// reg_ovf_cnt_lsch2_int_st.
-            OVF_CNT_LSCH2_INT_ST: u1,
-            /// reg_ovf_cnt_lsch3_int_st.
-            OVF_CNT_LSCH3_INT_ST: u1,
-            /// reg_ovf_cnt_lsch4_int_st.
-            OVF_CNT_LSCH4_INT_ST: u1,
-            /// reg_ovf_cnt_lsch5_int_st.
-            OVF_CNT_LSCH5_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xc4);
-
-        /// address: 0x600190c8
-        /// LEDC_INT_ENA.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_ovf_int_ena.
-            LSTIMER0_OVF_INT_ENA: u1,
-            /// reg_lstimer1_ovf_int_ena.
-            LSTIMER1_OVF_INT_ENA: u1,
-            /// reg_lstimer2_ovf_int_ena.
-            LSTIMER2_OVF_INT_ENA: u1,
-            /// reg_lstimer3_ovf_int_ena.
-            LSTIMER3_OVF_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch0_int_ena.
-            DUTY_CHNG_END_LSCH0_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch1_int_ena.
-            DUTY_CHNG_END_LSCH1_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch2_int_ena.
-            DUTY_CHNG_END_LSCH2_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch3_int_ena.
-            DUTY_CHNG_END_LSCH3_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch4_int_ena.
-            DUTY_CHNG_END_LSCH4_INT_ENA: u1,
-            /// reg_duty_chng_end_lsch5_int_ena.
-            DUTY_CHNG_END_LSCH5_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch0_int_ena.
-            OVF_CNT_LSCH0_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch1_int_ena.
-            OVF_CNT_LSCH1_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch2_int_ena.
-            OVF_CNT_LSCH2_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch3_int_ena.
-            OVF_CNT_LSCH3_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch4_int_ena.
-            OVF_CNT_LSCH4_INT_ENA: u1,
-            /// reg_ovf_cnt_lsch5_int_ena.
-            OVF_CNT_LSCH5_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600190cc
-        /// LEDC_INT_CLR.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lstimer0_ovf_int_clr.
-            LSTIMER0_OVF_INT_CLR: u1,
-            /// reg_lstimer1_ovf_int_clr.
-            LSTIMER1_OVF_INT_CLR: u1,
-            /// reg_lstimer2_ovf_int_clr.
-            LSTIMER2_OVF_INT_CLR: u1,
-            /// reg_lstimer3_ovf_int_clr.
-            LSTIMER3_OVF_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch0_int_clr.
-            DUTY_CHNG_END_LSCH0_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch1_int_clr.
-            DUTY_CHNG_END_LSCH1_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch2_int_clr.
-            DUTY_CHNG_END_LSCH2_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch3_int_clr.
-            DUTY_CHNG_END_LSCH3_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch4_int_clr.
-            DUTY_CHNG_END_LSCH4_INT_CLR: u1,
-            /// reg_duty_chng_end_lsch5_int_clr.
-            DUTY_CHNG_END_LSCH5_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch0_int_clr.
-            OVF_CNT_LSCH0_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch1_int_clr.
-            OVF_CNT_LSCH1_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch2_int_clr.
-            OVF_CNT_LSCH2_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch3_int_clr.
-            OVF_CNT_LSCH3_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch4_int_clr.
-            OVF_CNT_LSCH4_INT_CLR: u1,
-            /// reg_ovf_cnt_lsch5_int_clr.
-            OVF_CNT_LSCH5_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x600190d0
-        /// LEDC_CONF.
-        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_apb_clk_sel.
-            APB_CLK_SEL: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// reg_clk_en.
-            CLK_EN: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x600190fc
-        /// LEDC_DATE.
-        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_ledc_date.
-            LEDC_DATE: u32,
-        }), base_address + 0xfc);
-    };
-
-    /// Remote Control Peripheral
-    pub const RMT = struct {
-        pub const base_address = 0x60016000;
-
-        /// address: 0x60016000
-        /// RMT_CH0DATA_REG.
-        pub const CH0DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            DATA: u32,
-        }), base_address + 0x0);
-
-        /// address: 0x60016004
-        /// RMT_CH1DATA_REG.
-        pub const CH1DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            DATA: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60016008
-        /// RMT_CH2DATA_REG.
-        pub const CH2DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            DATA: u32,
-        }), base_address + 0x8);
-
-        /// address: 0x6001600c
-        /// RMT_CH3DATA_REG.
-        pub const CH3DATA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Reserved.
-            DATA: u32,
-        }), base_address + 0xc);
-
-        /// address: 0x60016010
-        /// RMT_CH%sCONF%s_REG.
-        pub const CH0_TX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_tx_start_ch0.
-            TX_START: u1,
-            /// reg_mem_rd_rst_ch0.
-            MEM_RD_RST: u1,
-            /// reg_apb_mem_rst_ch0.
-            APB_MEM_RST: u1,
-            /// reg_tx_conti_mode_ch0.
-            TX_CONTI_MODE: u1,
-            /// reg_mem_tx_wrap_en_ch0.
-            MEM_TX_WRAP_EN: u1,
-            /// reg_idle_out_lv_ch0.
-            IDLE_OUT_LV: u1,
-            /// reg_idle_out_en_ch0.
-            IDLE_OUT_EN: u1,
-            /// reg_tx_stop_ch0.
-            TX_STOP: u1,
-            /// reg_div_cnt_ch0.
-            DIV_CNT: u8,
-            /// reg_mem_size_ch0.
-            MEM_SIZE: u3,
-            reserved0: u1,
-            /// reg_carrier_eff_en_ch0.
-            CARRIER_EFF_EN: u1,
-            /// reg_carrier_en_ch0.
-            CARRIER_EN: u1,
-            /// reg_carrier_out_lv_ch0.
-            CARRIER_OUT_LV: u1,
-            /// reg_afifo_rst_ch0.
-            AFIFO_RST: u1,
-            /// reg_reg_conf_update_ch0.
-            CONF_UPDATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60016014
-        /// RMT_CH%sCONF%s_REG.
-        pub const CH1_TX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_tx_start_ch0.
-            TX_START: u1,
-            /// reg_mem_rd_rst_ch0.
-            MEM_RD_RST: u1,
-            /// reg_apb_mem_rst_ch0.
-            APB_MEM_RST: u1,
-            /// reg_tx_conti_mode_ch0.
-            TX_CONTI_MODE: u1,
-            /// reg_mem_tx_wrap_en_ch0.
-            MEM_TX_WRAP_EN: u1,
-            /// reg_idle_out_lv_ch0.
-            IDLE_OUT_LV: u1,
-            /// reg_idle_out_en_ch0.
-            IDLE_OUT_EN: u1,
-            /// reg_tx_stop_ch0.
-            TX_STOP: u1,
-            /// reg_div_cnt_ch0.
-            DIV_CNT: u8,
-            /// reg_mem_size_ch0.
-            MEM_SIZE: u3,
-            reserved0: u1,
-            /// reg_carrier_eff_en_ch0.
-            CARRIER_EFF_EN: u1,
-            /// reg_carrier_en_ch0.
-            CARRIER_EN: u1,
-            /// reg_carrier_out_lv_ch0.
-            CARRIER_OUT_LV: u1,
-            /// reg_afifo_rst_ch0.
-            AFIFO_RST: u1,
-            /// reg_reg_conf_update_ch0.
-            CONF_UPDATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60016018
-        /// RMT_CH2CONF0_REG.
-        pub const CH2_RX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_div_cnt_ch2.
-            DIV_CNT: u8,
-            /// reg_idle_thres_ch2.
-            IDLE_THRES: u15,
-            /// reg_mem_size_ch2.
-            MEM_SIZE: u3,
-            reserved0: u1,
-            reserved1: u1,
-            /// reg_carrier_en_ch2.
-            CARRIER_EN: u1,
-            /// reg_carrier_out_lv_ch2.
-            CARRIER_OUT_LV: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x60016020
-        /// RMT_CH2CONF0_REG.
-        pub const CH3_RX_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_div_cnt_ch2.
-            DIV_CNT: u8,
-            /// reg_idle_thres_ch2.
-            IDLE_THRES: u15,
-            /// reg_mem_size_ch2.
-            MEM_SIZE: u3,
-            reserved0: u1,
-            reserved1: u1,
-            /// reg_carrier_en_ch2.
-            CARRIER_EN: u1,
-            /// reg_carrier_out_lv_ch2.
-            CARRIER_OUT_LV: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x6001601c
-        /// RMT_CH2CONF1_REG.
-        pub const CH2CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rx_en_ch2.
-            RX_EN: u1,
-            /// reg_mem_wr_rst_ch2.
-            MEM_WR_RST: u1,
-            /// reg_apb_mem_rst_ch2.
-            APB_MEM_RST: u1,
-            /// reg_mem_owner_ch2.
-            MEM_OWNER: u1,
-            /// reg_rx_filter_en_ch2.
-            RX_FILTER_EN: u1,
-            /// reg_rx_filter_thres_ch2.
-            RX_FILTER_THRES: u8,
-            /// reg_mem_rx_wrap_en_ch2.
-            MEM_RX_WRAP_EN: u1,
-            /// reg_afifo_rst_ch2.
-            AFIFO_RST: u1,
-            /// reg_conf_update_ch2.
-            CONF_UPDATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60016024
-        /// RMT_CH3CONF1_REG.
-        pub const CH3CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rx_en_ch3.
-            RX_EN: u1,
-            /// reg_mem_wr_rst_ch3.
-            MEM_WR_RST: u1,
-            /// reg_apb_mem_rst_ch3.
-            APB_MEM_RST: u1,
-            /// reg_mem_owner_ch3.
-            MEM_OWNER: u1,
-            /// reg_rx_filter_en_ch3.
-            RX_FILTER_EN: u1,
-            /// reg_rx_filter_thres_ch3.
-            RX_FILTER_THRES: u8,
-            /// reg_mem_rx_wrap_en_ch3.
-            MEM_RX_WRAP_EN: u1,
-            /// reg_afifo_rst_ch3.
-            AFIFO_RST: u1,
-            /// reg_conf_update_ch3.
-            CONF_UPDATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60016028
-        /// RMT_CH0STATUS_REG.
-        pub const CH0STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_mem_raddr_ex_ch0.
-            MEM_RADDR_EX: u9,
-            /// reg_state_ch0.
-            STATE: u3,
-            /// reg_apb_mem_waddr_ch0.
-            APB_MEM_WADDR: u9,
-            /// reg_apb_mem_rd_err_ch0.
-            APB_MEM_RD_ERR: u1,
-            /// reg_mem_empty_ch0.
-            MEM_EMPTY: u1,
-            /// reg_apb_mem_wr_err_ch0.
-            APB_MEM_WR_ERR: u1,
-            /// reg_apb_mem_raddr_ch0.
-            APB_MEM_RADDR: u8,
-        }), base_address + 0x28);
-
-        /// address: 0x6001602c
-        /// RMT_CH1STATUS_REG.
-        pub const CH1STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_mem_raddr_ex_ch1.
-            MEM_RADDR_EX: u9,
-            /// reg_state_ch1.
-            STATE: u3,
-            /// reg_apb_mem_waddr_ch1.
-            APB_MEM_WADDR: u9,
-            /// reg_apb_mem_rd_err_ch1.
-            APB_MEM_RD_ERR: u1,
-            /// reg_mem_empty_ch1.
-            MEM_EMPTY: u1,
-            /// reg_apb_mem_wr_err_ch1.
-            APB_MEM_WR_ERR: u1,
-            /// reg_apb_mem_raddr_ch1.
-            APB_MEM_RADDR: u8,
-        }), base_address + 0x2c);
-
-        /// address: 0x60016030
-        /// RMT_CH2STATUS_REG.
-        pub const CH2STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_mem_waddr_ex_ch2.
-            MEM_WADDR_EX: u9,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// reg_apb_mem_raddr_ch2.
-            APB_MEM_RADDR: u9,
-            reserved3: u1,
-            /// reg_state_ch2.
-            STATE: u3,
-            /// reg_mem_owner_err_ch2.
-            MEM_OWNER_ERR: u1,
-            /// reg_mem_full_ch2.
-            MEM_FULL: u1,
-            /// reg_apb_mem_rd_err_ch2.
-            APB_MEM_RD_ERR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60016034
-        /// RMT_CH3STATUS_REG.
-        pub const CH3STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_mem_waddr_ex_ch3.
-            MEM_WADDR_EX: u9,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// reg_apb_mem_raddr_ch3.
-            APB_MEM_RADDR: u9,
-            reserved3: u1,
-            /// reg_state_ch3.
-            STATE: u3,
-            /// reg_mem_owner_err_ch3.
-            MEM_OWNER_ERR: u1,
-            /// reg_mem_full_ch3.
-            MEM_FULL: u1,
-            /// reg_apb_mem_rd_err_ch3.
-            APB_MEM_RD_ERR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60016038
-        /// RMT_INT_RAW_REG.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0_TX_END_INT_RAW: u1,
-            CH1_TX_END_INT_RAW: u1,
-            CH2_RX_END_INT_RAW: u1,
-            CH3_RX_END_INT_RAW: u1,
-            CH0_TX_ERR_INT_RAW: u1,
-            CH1_TX_ERR_INT_RAW: u1,
-            CH2_RX_ERR_INT_RAW: u1,
-            CH3_RX_ERR_INT_RAW: u1,
-            CH0_TX_THR_EVENT_INT_RAW: u1,
-            CH1_TX_THR_EVENT_INT_RAW: u1,
-            /// reg_ch2_rx_thr_event_int_raw.
-            CH2_RX_THR_EVENT_INT_RAW: u1,
-            /// reg_ch3_rx_thr_event_int_raw.
-            CH3_RX_THR_EVENT_INT_RAW: u1,
-            CH0_TX_LOOP_INT_RAW: u1,
-            CH1_TX_LOOP_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6001603c
-        /// RMT_INT_ST_REG.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0_TX_END_INT_ST: u1,
-            CH1_TX_END_INT_ST: u1,
-            CH2_RX_END_INT_ST: u1,
-            CH3_RX_END_INT_ST: u1,
-            CH0_TX_ERR_INT_ST: u1,
-            CH1_TX_ERR_INT_ST: u1,
-            CH2_RX_ERR_INT_ST: u1,
-            CH3_RX_ERR_INT_ST: u1,
-            CH0_TX_THR_EVENT_INT_ST: u1,
-            CH1_TX_THR_EVENT_INT_ST: u1,
-            /// reg_ch2_rx_thr_event_int_st.
-            CH2_RX_THR_EVENT_INT_ST: u1,
-            /// reg_ch3_rx_thr_event_int_st.
-            CH3_RX_THR_EVENT_INT_ST: u1,
-            CH0_TX_LOOP_INT_ST: u1,
-            CH1_TX_LOOP_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60016040
-        /// RMT_INT_ENA_REG.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0_TX_END_INT_ENA: u1,
-            CH1_TX_END_INT_ENA: u1,
-            CH2_RX_END_INT_ENA: u1,
-            CH3_RX_END_INT_ENA: u1,
-            CH0_TX_ERR_INT_ENA: u1,
-            CH1_TX_ERR_INT_ENA: u1,
-            CH2_RX_ERR_INT_ENA: u1,
-            CH3_RX_ERR_INT_ENA: u1,
-            CH0_TX_THR_EVENT_INT_ENA: u1,
-            CH1_TX_THR_EVENT_INT_ENA: u1,
-            /// reg_ch2_rx_thr_event_int_ena.
-            CH2_RX_THR_EVENT_INT_ENA: u1,
-            /// reg_ch3_rx_thr_event_int_ena.
-            CH3_RX_THR_EVENT_INT_ENA: u1,
-            CH0_TX_LOOP_INT_ENA: u1,
-            CH1_TX_LOOP_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60016044
-        /// RMT_INT_CLR_REG.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            CH0_TX_END_INT_CLR: u1,
-            CH1_TX_END_INT_CLR: u1,
-            CH2_RX_END_INT_CLR: u1,
-            CH3_RX_END_INT_CLR: u1,
-            CH0_TX_ERR_INT_CLR: u1,
-            CH1_TX_ERR_INT_CLR: u1,
-            CH2_RX_ERR_INT_CLR: u1,
-            CH3_RX_ERR_INT_CLR: u1,
-            CH0_TX_THR_EVENT_INT_CLR: u1,
-            CH1_TX_THR_EVENT_INT_CLR: u1,
-            /// reg_ch2_rx_thr_event_int_clr.
-            CH2_RX_THR_EVENT_INT_CLR: u1,
-            /// reg_ch3_rx_thr_event_int_clr.
-            CH3_RX_THR_EVENT_INT_CLR: u1,
-            CH0_TX_LOOP_INT_CLR: u1,
-            CH1_TX_LOOP_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60016048
-        /// RMT_CH0CARRIER_DUTY_REG.
-        pub const CH0CARRIER_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_carrier_low_ch0.
-            CARRIER_LOW: u16,
-            /// reg_carrier_high_ch0.
-            CARRIER_HIGH: u16,
-        }), base_address + 0x48);
-
-        /// address: 0x6001604c
-        /// RMT_CH1CARRIER_DUTY_REG.
-        pub const CH1CARRIER_DUTY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_carrier_low_ch1.
-            CARRIER_LOW: u16,
-            /// reg_carrier_high_ch1.
-            CARRIER_HIGH: u16,
-        }), base_address + 0x4c);
-
-        /// address: 0x60016050
-        /// RMT_CH2_RX_CARRIER_RM_REG.
-        pub const CH2_RX_CARRIER_RM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_carrier_low_thres_ch2.
-            CARRIER_LOW_THRES: u16,
-            /// reg_carrier_high_thres_ch2.
-            CARRIER_HIGH_THRES: u16,
-        }), base_address + 0x50);
-
-        /// address: 0x60016054
-        /// RMT_CH3_RX_CARRIER_RM_REG.
-        pub const CH3_RX_CARRIER_RM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_carrier_low_thres_ch3.
-            CARRIER_LOW_THRES: u16,
-            /// reg_carrier_high_thres_ch3.
-            CARRIER_HIGH_THRES: u16,
-        }), base_address + 0x54);
-
-        /// address: 0x60016058
-        /// RMT_CH%s_TX_LIM_REG.
-        pub const CH0_TX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rmt_tx_lim_ch0.
-            TX_LIM: u9,
-            /// reg_rmt_tx_loop_num_ch0.
-            TX_LOOP_NUM: u10,
-            /// reg_rmt_tx_loop_cnt_en_ch0.
-            TX_LOOP_CNT_EN: u1,
-            /// reg_loop_count_reset_ch0.
-            LOOP_COUNT_RESET: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6001605c
-        /// RMT_CH%s_TX_LIM_REG.
-        pub const CH1_TX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rmt_tx_lim_ch0.
-            TX_LIM: u9,
-            /// reg_rmt_tx_loop_num_ch0.
-            TX_LOOP_NUM: u10,
-            /// reg_rmt_tx_loop_cnt_en_ch0.
-            TX_LOOP_CNT_EN: u1,
-            /// reg_loop_count_reset_ch0.
-            LOOP_COUNT_RESET: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60016060
-        /// RMT_CH2_RX_LIM_REG.
-        pub const CH2_RX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rmt_rx_lim_ch2.
-            RX_LIM: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60016064
-        /// RMT_CH2_RX_LIM_REG.
-        pub const CH3_RX_LIM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rmt_rx_lim_ch2.
-            RX_LIM: u9,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60016068
-        /// RMT_SYS_CONF_REG.
-        pub const SYS_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_apb_fifo_mask.
-            APB_FIFO_MASK: u1,
-            /// reg_mem_clk_force_on.
-            MEM_CLK_FORCE_ON: u1,
-            /// reg_rmt_mem_force_pd.
-            MEM_FORCE_PD: u1,
-            /// reg_rmt_mem_force_pu.
-            MEM_FORCE_PU: u1,
-            /// reg_rmt_sclk_div_num.
-            SCLK_DIV_NUM: u8,
-            /// reg_rmt_sclk_div_a.
-            SCLK_DIV_A: u6,
-            /// reg_rmt_sclk_div_b.
-            SCLK_DIV_B: u6,
-            /// reg_rmt_sclk_sel.
-            SCLK_SEL: u2,
-            /// reg_rmt_sclk_active.
-            SCLK_ACTIVE: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// reg_clk_en.
-            CLK_EN: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6001606c
-        /// RMT_TX_SIM_REG.
-        pub const TX_SIM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rmt_tx_sim_ch0.
-            TX_SIM_CH0: u1,
-            /// reg_rmt_tx_sim_ch1.
-            TX_SIM_CH1: u1,
-            /// reg_rmt_tx_sim_en.
-            TX_SIM_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60016070
-        /// RMT_REF_CNT_RST_REG.
-        pub const REF_CNT_RST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_ref_cnt_rst_ch0.
-            CH0: u1,
-            /// reg_ref_cnt_rst_ch1.
-            CH1: u1,
-            /// reg_ref_cnt_rst_ch2.
-            CH2: u1,
-            /// reg_ref_cnt_rst_ch3.
-            CH3: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x600160cc
-        /// RMT_DATE_REG.
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xcc);
-    };
-
-    /// Hardware random number generator
-    pub const RNG = struct {
-        pub const base_address = 0x60026000;
-
-        /// address: 0x600260b0
-        /// Random number data
-        pub const DATA = @intToPtr(*volatile u32, base_address + 0xb0);
-    };
-
-    /// RSA (Rivest Shamir Adleman) Accelerator
-    pub const RSA = struct {
-        pub const base_address = 0x6003c000;
-
-        /// address: 0x6003c000
-        /// The memory that stores M
-        pub const M_MEM = @intToPtr(*volatile [16]u8, base_address + 0x0);
-
-        /// address: 0x6003c200
-        /// The memory that stores Z
-        pub const Z_MEM = @intToPtr(*volatile [16]u8, base_address + 0x200);
-
-        /// address: 0x6003c400
-        /// The memory that stores Y
-        pub const Y_MEM = @intToPtr(*volatile [16]u8, base_address + 0x400);
-
-        /// address: 0x6003c600
-        /// The memory that stores X
-        pub const X_MEM = @intToPtr(*volatile [16]u8, base_address + 0x600);
-
-        /// address: 0x6003c800
-        /// RSA M_prime register
-        pub const M_PRIME = @intToPtr(*volatile u32, base_address + 0x800);
-
-        /// address: 0x6003c804
-        /// RSA mode register
-        pub const MODE = @intToPtr(*volatile MmioInt(32, u7), base_address + 0x804);
-
-        /// address: 0x6003c808
-        /// RSA query clean register
-        pub const QUERY_CLEAN = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x808);
-
-        /// address: 0x6003c80c
-        /// RSA modular exponentiation trigger register.
-        pub const SET_START_MODEXP = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x80c);
-
-        /// address: 0x6003c810
-        /// RSA modular multiplication trigger register.
-        pub const SET_START_MODMULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x810);
-
-        /// address: 0x6003c814
-        /// RSA normal multiplication trigger register.
-        pub const SET_START_MULT = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x814);
-
-        /// address: 0x6003c818
-        /// RSA query idle register
-        pub const QUERY_IDLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x818);
-
-        /// address: 0x6003c81c
-        /// RSA interrupt clear register
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// set this bit to clear RSA interrupt.
-            CLEAR_INTERRUPT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x81c);
-
-        /// address: 0x6003c820
-        /// RSA constant time option register
-        pub const CONSTANT_TIME = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x820);
-
-        /// address: 0x6003c824
-        /// RSA search option
-        pub const SEARCH_ENABLE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x824);
-
-        /// address: 0x6003c828
-        /// RSA search position configure register
-        pub const SEARCH_POS = @intToPtr(*volatile MmioInt(32, u12), base_address + 0x828);
-
-        /// address: 0x6003c82c
-        /// RSA interrupt enable register
-        pub const INT_ENA = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x82c);
-
-        /// address: 0x6003c830
-        /// RSA version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x830);
-    };
-
-    /// Real-Time Clock Control
-    pub const RTC_CNTL = struct {
-        pub const base_address = 0x60008000;
-
-        /// address: 0x60008000
-        /// rtc configure register
-        pub const OPTIONS0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall
-            /// APP CPU
-            SW_STALL_APPCPU_C0: u2,
-            /// {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall
-            /// PRO CPU
-            SW_STALL_PROCPU_C0: u2,
-            /// APP CPU SW reset
-            SW_APPCPU_RST: u1,
-            /// PRO CPU SW reset
-            SW_PROCPU_RST: u1,
-            /// BB_I2C force power down
-            BB_I2C_FORCE_PD: u1,
-            /// BB_I2C force power up
-            BB_I2C_FORCE_PU: u1,
-            /// BB_PLL _I2C force power down
-            BBPLL_I2C_FORCE_PD: u1,
-            /// BB_PLL_I2C force power up
-            BBPLL_I2C_FORCE_PU: u1,
-            /// BB_PLL force power down
-            BBPLL_FORCE_PD: u1,
-            /// BB_PLL force power up
-            BBPLL_FORCE_PU: u1,
-            /// crystall force power down
-            XTL_FORCE_PD: u1,
-            /// crystall force power up
-            XTL_FORCE_PU: u1,
-            /// wait bias_sleep and current source wakeup
-            XTL_EN_WAIT: u4,
-            reserved0: u1,
-            reserved1: u1,
-            /// analog configure
-            XTL_EXT_CTR_SEL: u3,
-            /// analog configure
-            XTL_FORCE_ISO: u1,
-            /// analog configure
-            PLL_FORCE_ISO: u1,
-            /// analog configure
-            ANALOG_FORCE_ISO: u1,
-            /// analog configure
-            XTL_FORCE_NOISO: u1,
-            /// analog configure
-            PLL_FORCE_NOISO: u1,
-            /// analog configure
-            ANALOG_FORCE_NOISO: u1,
-            /// digital wrap force reset in deep sleep
-            DG_WRAP_FORCE_RST: u1,
-            /// digital core force no reset in deep sleep
-            DG_WRAP_FORCE_NORST: u1,
-            /// SW system reset
-            SW_SYS_RST: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60008004
-        /// rtc configure register
-        pub const SLP_TIMER0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// configure the sleep time
-            SLP_VAL_LO: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60008008
-        /// rtc configure register
-        pub const SLP_TIMER1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// RTC sleep timer high 16 bits
-            SLP_VAL_HI: u16,
-            /// timer alarm enable bit
-            RTC_MAIN_TIMER_ALARM_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000800c
-        /// rtc configure register
-        pub const TIME_UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            /// Enable to record system stall time
-            TIMER_SYS_STALL: u1,
-            /// Enable to record 40M XTAL OFF time
-            TIMER_XTL_OFF: u1,
-            /// enable to record system reset time
-            TIMER_SYS_RST: u1,
-            reserved27: u1,
-            /// Set 1: to update register with RTC timer
-            RTC_TIME_UPDATE: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60008010
-        /// rtc configure register
-        pub const TIME_LOW0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// RTC timer low 32 bits
-            RTC_TIMER_VALUE0_LOW: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x60008014
-        /// rtc configure register
-        pub const TIME_HIGH0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// RTC timer high 16 bits
-            RTC_TIMER_VALUE0_HIGH: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60008018
-        /// rtc configure register
-        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// rtc software interrupt to main cpu
-            RTC_SW_CPU_INT: u1,
-            /// clear rtc sleep reject cause
-            RTC_SLP_REJECT_CAUSE_CLR: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            /// 1: APB to RTC using bridge
-            APB2RTC_BRIDGE_SEL: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            /// SDIO active indication
-            SDIO_ACTIVE_IND: u1,
-            /// leep wakeup bit
-            SLP_WAKEUP: u1,
-            /// leep reject bit
-            SLP_REJECT: u1,
-            /// sleep enable bit
-            SLEEP_EN: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000801c
-        /// rtc configure register
-        pub const TIMER1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// CPU stall enable bit
-            CPU_STALL_EN: u1,
-            /// CPU stall wait cycles in fast_clk_rtc
-            CPU_STALL_WAIT: u5,
-            /// CK8M wait cycles in slow_clk_rtc
-            CK8M_WAIT: u8,
-            /// XTAL wait cycles in slow_clk_rtc
-            XTL_BUF_WAIT: u10,
-            /// PLL wait cycles in slow_clk_rtc
-            PLL_BUF_WAIT: u8,
-        }), base_address + 0x1c);
-
-        /// address: 0x60008020
-        /// rtc configure register
-        pub const TIMER2 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            /// minimal cycles in slow_clk_rtc for CK8M in power down state
-            MIN_TIME_CK8M_OFF: u8,
-        }), base_address + 0x20);
-
-        /// address: 0x60008024
-        /// rtc configure register
-        pub const TIMER3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// wifi power domain wakeup time
-            WIFI_WAIT_TIMER: u9,
-            /// wifi power domain power on time
-            WIFI_POWERUP_TIMER: u7,
-            /// bt power domain wakeup time
-            BT_WAIT_TIMER: u9,
-            /// bt power domain power on time
-            BT_POWERUP_TIMER: u7,
-        }), base_address + 0x24);
-
-        /// address: 0x60008028
-        /// rtc configure register
-        pub const TIMER4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// cpu top power domain wakeup time
-            CPU_TOP_WAIT_TIMER: u9,
-            /// cpu top power domain power on time
-            CPU_TOP_POWERUP_TIMER: u7,
-            /// digital wrap power domain wakeup time
-            DG_WRAP_WAIT_TIMER: u9,
-            /// digital wrap power domain power on time
-            DG_WRAP_POWERUP_TIMER: u7,
-        }), base_address + 0x28);
-
-        /// address: 0x6000802c
-        /// rtc configure register
-        pub const TIMER5 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// minimal sleep cycles in slow_clk_rtc
-            MIN_SLP_VAL: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60008030
-        /// rtc configure register
-        pub const TIMER6 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            /// digital peri power domain wakeup time
-            DG_PERI_WAIT_TIMER: u9,
-            /// digital peri power domain power on time
-            DG_PERI_POWERUP_TIMER: u7,
-        }), base_address + 0x30);
-
-        /// address: 0x60008034
-        /// rtc configure register
-        pub const ANA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// force no bypass i2c power on reset
-            RESET_POR_FORCE_PD: u1,
-            /// force bypass i2c power on reset
-            RESET_POR_FORCE_PU: u1,
-            /// enable glitch reset
-            GLITCH_RST_EN: u1,
-            reserved18: u1,
-            /// PLLA force power up
-            SAR_I2C_PU: u1,
-            /// PLLA force power down
-            PLLA_FORCE_PD: u1,
-            /// PLLA force power up
-            PLLA_FORCE_PU: u1,
-            /// start BBPLL calibration during sleep
-            BBPLL_CAL_SLP_START: u1,
-            /// 1: PVTMON power up
-            PVTMON_PU: u1,
-            /// 1: TXRF_I2C power up
-            TXRF_I2C_PU: u1,
-            /// 1: RFRX_PBUS power up
-            RFRX_PBUS_PU: u1,
-            reserved19: u1,
-            /// 1: CKGEN_I2C power up
-            CKGEN_I2C_PU: u1,
-            /// power up pll i2c
-            PLL_I2C_PU: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60008038
-        /// rtc configure register
-        pub const RESET_STATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reset cause of PRO CPU
-            RESET_CAUSE_PROCPU: u6,
-            /// reset cause of APP CPU
-            RESET_CAUSE_APPCPU: u6,
-            /// APP CPU state vector sel
-            STAT_VECTOR_SEL_APPCPU: u1,
-            /// PRO CPU state vector sel
-            STAT_VECTOR_SEL_PROCPU: u1,
-            /// PRO CPU reset_flag
-            ALL_RESET_FLAG_PROCPU: u1,
-            /// APP CPU reset flag
-            ALL_RESET_FLAG_APPCPU: u1,
-            /// clear PRO CPU reset_flag
-            ALL_RESET_FLAG_CLR_PROCPU: u1,
-            /// clear APP CPU reset flag
-            ALL_RESET_FLAG_CLR_APPCPU: u1,
-            /// APPCPU OcdHaltOnReset
-            OCD_HALT_ON_RESET_APPCPU: u1,
-            /// PROCPU OcdHaltOnReset
-            OCD_HALT_ON_RESET_PROCPU: u1,
-            /// configure jtag reset configure
-            JTAG_RESET_FLAG_PROCPU: u1,
-            /// configure jtag reset configure
-            JTAG_RESET_FLAG_APPCPU: u1,
-            /// configure jtag reset configure
-            JTAG_RESET_FLAG_CLR_PROCPU: u1,
-            /// configure jtag reset configure
-            JTAG_RESET_FLAG_CLR_APPCPU: u1,
-            /// configure dreset configure
-            RTC_DRESET_MASK_APPCPU: u1,
-            /// configure dreset configure
-            RTC_DRESET_MASK_PROCPU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6000803c
-        /// rtc configure register
-        pub const WAKEUP_STATE = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// wakeup enable bitmap
-            RTC_WAKEUP_ENA: u17,
-        }), base_address + 0x3c);
-
-        /// address: 0x60008040
-        /// rtc configure register
-        pub const INT_ENA_RTC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// enable sleep wakeup interrupt
-            SLP_WAKEUP_INT_ENA: u1,
-            /// enable sleep reject interrupt
-            SLP_REJECT_INT_ENA: u1,
-            reserved0: u1,
-            /// enable RTC WDT interrupt
-            RTC_WDT_INT_ENA: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// enable brown out interrupt
-            RTC_BROWN_OUT_INT_ENA: u1,
-            /// enable RTC main timer interrupt
-            RTC_MAIN_TIMER_INT_ENA: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// enable super watch dog interrupt
-            RTC_SWD_INT_ENA: u1,
-            /// enable xtal32k_dead interrupt
-            RTC_XTAL32K_DEAD_INT_ENA: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// enbale gitch det interrupt
-            RTC_GLITCH_DET_INT_ENA: u1,
-            /// enbale bbpll cal end interrupt
-            RTC_BBPLL_CAL_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60008044
-        /// rtc configure register
-        pub const INT_RAW_RTC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// sleep wakeup interrupt raw
-            SLP_WAKEUP_INT_RAW: u1,
-            /// sleep reject interrupt raw
-            SLP_REJECT_INT_RAW: u1,
-            reserved0: u1,
-            /// RTC WDT interrupt raw
-            RTC_WDT_INT_RAW: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// brown out interrupt raw
-            RTC_BROWN_OUT_INT_RAW: u1,
-            /// RTC main timer interrupt raw
-            RTC_MAIN_TIMER_INT_RAW: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// super watch dog interrupt raw
-            RTC_SWD_INT_RAW: u1,
-            /// xtal32k dead detection interrupt raw
-            RTC_XTAL32K_DEAD_INT_RAW: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// glitch_det_interrupt_raw
-            RTC_GLITCH_DET_INT_RAW: u1,
-            /// bbpll cal end interrupt state
-            RTC_BBPLL_CAL_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60008048
-        /// rtc configure register
-        pub const INT_ST_RTC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// sleep wakeup interrupt state
-            SLP_WAKEUP_INT_ST: u1,
-            /// sleep reject interrupt state
-            SLP_REJECT_INT_ST: u1,
-            reserved0: u1,
-            /// RTC WDT interrupt state
-            RTC_WDT_INT_ST: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// brown out interrupt state
-            RTC_BROWN_OUT_INT_ST: u1,
-            /// RTC main timer interrupt state
-            RTC_MAIN_TIMER_INT_ST: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// super watch dog interrupt state
-            RTC_SWD_INT_ST: u1,
-            /// xtal32k dead detection interrupt state
-            RTC_XTAL32K_DEAD_INT_ST: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// glitch_det_interrupt state
-            RTC_GLITCH_DET_INT_ST: u1,
-            /// bbpll cal end interrupt state
-            RTC_BBPLL_CAL_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6000804c
-        /// rtc configure register
-        pub const INT_CLR_RTC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Clear sleep wakeup interrupt state
-            SLP_WAKEUP_INT_CLR: u1,
-            /// Clear sleep reject interrupt state
-            SLP_REJECT_INT_CLR: u1,
-            reserved0: u1,
-            /// Clear RTC WDT interrupt state
-            RTC_WDT_INT_CLR: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// Clear brown out interrupt state
-            RTC_BROWN_OUT_INT_CLR: u1,
-            /// Clear RTC main timer interrupt state
-            RTC_MAIN_TIMER_INT_CLR: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// Clear super watch dog interrupt state
-            RTC_SWD_INT_CLR: u1,
-            /// Clear RTC WDT interrupt state
-            RTC_XTAL32K_DEAD_INT_CLR: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// Clear glitch det interrupt state
-            RTC_GLITCH_DET_INT_CLR: u1,
-            /// clear bbpll cal end interrupt state
-            RTC_BBPLL_CAL_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60008050
-        /// rtc configure register
-        pub const STORE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH0: u32,
-        }), base_address + 0x50);
-
-        /// address: 0x60008054
-        /// rtc configure register
-        pub const STORE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH1: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x60008058
-        /// rtc configure register
-        pub const STORE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH2: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6000805c
-        /// rtc configure register
-        pub const STORE3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH3: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x60008060
-        /// rtc configure register
-        pub const EXT_XTL_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// xtal 32k watch dog enable
-            XTAL32K_WDT_EN: u1,
-            /// xtal 32k watch dog clock force on
-            XTAL32K_WDT_CLK_FO: u1,
-            /// xtal 32k watch dog sw reset
-            XTAL32K_WDT_RESET: u1,
-            /// xtal 32k external xtal clock force on
-            XTAL32K_EXT_CLK_FO: u1,
-            /// xtal 32k switch to back up clock when xtal is dead
-            XTAL32K_AUTO_BACKUP: u1,
-            /// xtal 32k restart xtal when xtal is dead
-            XTAL32K_AUTO_RESTART: u1,
-            /// xtal 32k switch back xtal when xtal is restarted
-            XTAL32K_AUTO_RETURN: u1,
-            /// Xtal 32k xpd control by sw or fsm
-            XTAL32K_XPD_FORCE: u1,
-            /// apply an internal clock to help xtal 32k to start
-            ENCKINIT_XTAL_32K: u1,
-            /// 0: single-end buffer 1: differential buffer
-            DBUF_XTAL_32K: u1,
-            /// xtal_32k gm control
-            DGM_XTAL_32K: u3,
-            /// DRES_XTAL_32K
-            DRES_XTAL_32K: u3,
-            /// XPD_XTAL_32K
-            XPD_XTAL_32K: u1,
-            /// DAC_XTAL_32K
-            DAC_XTAL_32K: u3,
-            /// state of 32k_wdt
-            RTC_WDT_STATE: u3,
-            /// XTAL_32K sel. 0: external XTAL_32K
-            RTC_XTAL32K_GPIO_SEL: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// 0: power down XTAL at high level
-            XTL_EXT_CTR_LV: u1,
-            /// enable gpio configure xtal power on
-            XTL_EXT_CTR_EN: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60008064
-        /// rtc configure register
-        pub const EXT_WAKEUP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// enable filter for gpio wakeup event
-            GPIO_WAKEUP_FILTER: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60008068
-        /// rtc configure register
-        pub const SLP_REJECT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// sleep reject enable
-            RTC_SLEEP_REJECT_ENA: u18,
-            /// enable reject for light sleep
-            LIGHT_SLP_REJECT_EN: u1,
-            /// enable reject for deep sleep
-            DEEP_SLP_REJECT_EN: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6000806c
-        /// rtc configure register
-        pub const CPU_PERIOD_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// CPU sel option
-            RTC_CPUSEL_CONF: u1,
-            /// CPU clk sel option
-            RTC_CPUPERIOD_SEL: u2,
-        }), base_address + 0x6c);
-
-        /// address: 0x60008070
-        /// rtc configure register
-        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// efuse_clk_force_gating
-            EFUSE_CLK_FORCE_GATING: u1,
-            /// efuse_clk_force_nogating
-            EFUSE_CLK_FORCE_NOGATING: u1,
-            /// used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel
-            CK8M_DIV_SEL_VLD: u1,
-            /// CK8M_D256_OUT divider. 00: div128
-            CK8M_DIV: u2,
-            /// disable CK8M and CK8M_D256_OUT
-            ENB_CK8M: u1,
-            /// 1: CK8M_D256_OUT is actually CK8M
-            ENB_CK8M_DIV: u1,
-            /// enable CK_XTAL_32K for digital core (no relationship with RTC core)
-            DIG_XTAL32K_EN: u1,
-            /// enable CK8M_D256_OUT for digital core (no relationship with RTC core)
-            DIG_CLK8M_D256_EN: u1,
-            /// enable CK8M for digital core (no relationship with RTC core)
-            DIG_CLK8M_EN: u1,
-            reserved1: u1,
-            /// divider = reg_ck8m_div_sel + 1
-            CK8M_DIV_SEL: u3,
-            /// XTAL force no gating during sleep
-            XTAL_FORCE_NOGATING: u1,
-            /// CK8M force no gating during sleep
-            CK8M_FORCE_NOGATING: u1,
-            /// CK8M_DFREQ
-            CK8M_DFREQ: u8,
-            /// CK8M force power down
-            CK8M_FORCE_PD: u1,
-            /// CK8M force power up
-            CK8M_FORCE_PU: u1,
-            /// force enable xtal clk gating
-            XTAL_GLOBAL_FORCE_GATING: u1,
-            /// force bypass xtal clk gating
-            XTAL_GLOBAL_FORCE_NOGATING: u1,
-            /// fast_clk_rtc sel. 0: XTAL div 4
-            FAST_CLK_RTC_SEL: u1,
-            /// slelect rtc slow clk
-            ANA_CLK_RTC_SEL: u2,
-        }), base_address + 0x70);
-
-        /// address: 0x60008074
-        /// rtc configure register
-        pub const SLOW_CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            /// used to sync div bus. clear vld before set reg_rtc_ana_clk_div
-            RTC_ANA_CLK_DIV_VLD: u1,
-            /// the clk divider num of RTC_CLK
-            RTC_ANA_CLK_DIV: u8,
-            /// flag rtc_slow_clk_next_edge
-            RTC_SLOW_CLK_NEXT_EDGE: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60008078
-        /// rtc configure register
-        pub const SDIO_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer count to apply reg_sdio_dcap after sdio power on
-            SDIO_TIMER_TARGET: u8,
-            reserved0: u1,
-            /// Tieh = 1 mode drive ability. Initially set to 0 to limit charge current
-            SDIO_DTHDRV: u2,
-            /// ability to prevent LDO from overshoot
-            SDIO_DCAP: u2,
-            /// add resistor from ldo output to ground. 0: no res
-            SDIO_INITI: u2,
-            /// 0 to set init[1:0]=0
-            SDIO_EN_INITI: u1,
-            /// tune current limit threshold when tieh = 0. About 800mA/(8+d)
-            SDIO_DCURLIM: u3,
-            /// select current limit mode
-            SDIO_MODECURLIM: u1,
-            /// enable current limit
-            SDIO_ENCURLIM: u1,
-            /// power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
-            SDIO_REG_PD_EN: u1,
-            /// 1: use SW option to control SDIO_REG
-            SDIO_FORCE: u1,
-            /// SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
-            SDIO_TIEH: u1,
-            /// read only register for REG1P8_READY
-            _1P8_READY: u1,
-            /// SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
-            DREFL_SDIO: u2,
-            /// SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
-            DREFM_SDIO: u2,
-            /// SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
-            DREFH_SDIO: u2,
-            XPD_SDIO: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6000807c
-        /// rtc configure register
-        pub const BIAS_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            DG_VDD_DRV_B_SLP: u8,
-            DG_VDD_DRV_B_SLP_EN: u1,
-            reserved0: u1,
-            /// bias buf when rtc in normal work state
-            BIAS_BUF_IDLE: u1,
-            /// bias buf when rtc in wakeup state
-            BIAS_BUF_WAKE: u1,
-            /// bias buf when rtc in sleep state
-            BIAS_BUF_DEEP_SLP: u1,
-            /// bias buf when rtc in monitor state
-            BIAS_BUF_MONITOR: u1,
-            /// xpd cur when rtc in sleep_state
-            PD_CUR_DEEP_SLP: u1,
-            /// xpd cur when rtc in monitor state
-            PD_CUR_MONITOR: u1,
-            /// bias_sleep when rtc in sleep_state
-            BIAS_SLEEP_DEEP_SLP: u1,
-            /// bias_sleep when rtc in monitor state
-            BIAS_SLEEP_MONITOR: u1,
-            /// DBG_ATTEN when rtc in sleep state
-            DBG_ATTEN_DEEP_SLP: u4,
-            /// DBG_ATTEN when rtc in monitor state
-            DBG_ATTEN_MONITOR: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x60008080
-        /// rtc configure register
-        pub const RTC_CNTL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            /// software enable digital regulator cali
-            DIG_REG_CAL_EN: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            /// SCK_DCAP
-            SCK_DCAP: u8,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            /// RTC_DBOOST force power down
-            DBOOST_FORCE_PD: u1,
-            /// RTC_DBOOST force power up
-            DBOOST_FORCE_PU: u1,
-            /// RTC_REG force power down (for RTC_REG power down means decrease the voltage to
-            /// 0.8v or lower )
-            REGULATOR_FORCE_PD: u1,
-            /// RTC_REG force power up
-            REGULATOR_FORCE_PU: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x60008084
-        /// rtc configure register
-        pub const PWC = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            /// rtc pad force hold
-            RTC_PAD_FORCE_HOLD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x60008088
-        /// rtc configure register
-        pub const DIG_PWC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// vdd_spi drv's software value
-            VDD_SPI_PWR_DRV: u2,
-            /// vdd_spi drv use software value
-            VDD_SPI_PWR_FORCE: u1,
-            /// memories in digital core force PD in sleep
-            LSLP_MEM_FORCE_PD: u1,
-            /// memories in digital core force PU in sleep
-            LSLP_MEM_FORCE_PU: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// bt force power down
-            BT_FORCE_PD: u1,
-            /// bt force power up
-            BT_FORCE_PU: u1,
-            /// digital peri force power down
-            DG_PERI_FORCE_PD: u1,
-            /// digital peri force power up
-            DG_PERI_FORCE_PU: u1,
-            /// fastmemory retention mode in sleep
-            RTC_FASTMEM_FORCE_LPD: u1,
-            /// fastmemory donlt entry retention mode in sleep
-            RTC_FASTMEM_FORCE_LPU: u1,
-            /// wifi force power down
-            WIFI_FORCE_PD: u1,
-            /// wifi force power up
-            WIFI_FORCE_PU: u1,
-            /// digital core force power down
-            DG_WRAP_FORCE_PD: u1,
-            /// digital core force power up
-            DG_WRAP_FORCE_PU: u1,
-            /// cpu core force power down
-            CPU_TOP_FORCE_PD: u1,
-            /// cpu force power up
-            CPU_TOP_FORCE_PU: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// enable power down bt in sleep
-            BT_PD_EN: u1,
-            /// enable power down digital peri in sleep
-            DG_PERI_PD_EN: u1,
-            /// enable power down cpu in sleep
-            CPU_TOP_PD_EN: u1,
-            /// enable power down wifi in sleep
-            WIFI_PD_EN: u1,
-            /// enable power down digital wrap in sleep
-            DG_WRAP_PD_EN: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x6000808c
-        /// rtc configure register
-        pub const DIG_ISO = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            /// DIG_ISO force off
-            FORCE_OFF: u1,
-            /// DIG_ISO force on
-            FORCE_ON: u1,
-            /// read only register to indicate digital pad auto-hold status
-            DG_PAD_AUTOHOLD: u1,
-            /// wtite only register to clear digital pad auto-hold
-            CLR_DG_PAD_AUTOHOLD: u1,
-            /// digital pad enable auto-hold
-            DG_PAD_AUTOHOLD_EN: u1,
-            /// digital pad force no ISO
-            DG_PAD_FORCE_NOISO: u1,
-            /// digital pad force ISO
-            DG_PAD_FORCE_ISO: u1,
-            /// digital pad force un-hold
-            DG_PAD_FORCE_UNHOLD: u1,
-            /// digital pad force hold
-            DG_PAD_FORCE_HOLD: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            /// bt force ISO
-            BT_FORCE_ISO: u1,
-            /// bt force no ISO
-            BT_FORCE_NOISO: u1,
-            /// Digital peri force ISO
-            DG_PERI_FORCE_ISO: u1,
-            /// digital peri force no ISO
-            DG_PERI_FORCE_NOISO: u1,
-            /// cpu force ISO
-            CPU_TOP_FORCE_ISO: u1,
-            /// cpu force no ISO
-            CPU_TOP_FORCE_NOISO: u1,
-            /// wifi force ISO
-            WIFI_FORCE_ISO: u1,
-            /// wifi force no ISO
-            WIFI_FORCE_NOISO: u1,
-            /// digital core force ISO
-            DG_WRAP_FORCE_ISO: u1,
-            /// digital core force no ISO
-            DG_WRAP_FORCE_NOISO: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x60008090
-        /// rtc configure register
-        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// chip reset siginal pulse width
-            WDT_CHIP_RESET_WIDTH: u8,
-            /// wdt reset whole chip enable
-            WDT_CHIP_RESET_EN: u1,
-            /// pause WDT in sleep
-            WDT_PAUSE_IN_SLP: u1,
-            /// enable WDT reset APP CPU
-            WDT_APPCPU_RESET_EN: u1,
-            /// enable WDT reset PRO CPU
-            WDT_PROCPU_RESET_EN: u1,
-            /// enable WDT in flash boot
-            WDT_FLASHBOOT_MOD_EN: u1,
-            /// system reset counter length
-            WDT_SYS_RESET_LENGTH: u3,
-            /// CPU reset counter length
-            WDT_CPU_RESET_LENGTH: u3,
-            /// 1: interrupt stage en
-            WDT_STG3: u3,
-            /// 1: interrupt stage en
-            WDT_STG2: u3,
-            /// 1: interrupt stage en
-            WDT_STG1: u3,
-            /// 1: interrupt stage en
-            WDT_STG0: u3,
-            /// enable rtc wdt
-            WDT_EN: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x60008094
-        /// rtc configure register
-        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the hold time of stage0
-            WDT_STG0_HOLD: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x60008098
-        /// rtc configure register
-        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the hold time of stage1
-            WDT_STG1_HOLD: u32,
-        }), base_address + 0x98);
-
-        /// address: 0x6000809c
-        /// rtc configure register
-        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the hold time of stage2
-            WDT_STG2_HOLD: u32,
-        }), base_address + 0x9c);
-
-        /// address: 0x600080a0
-        /// rtc configure register
-        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the hold time of stage3
-            WDT_STG3_HOLD: u32,
-        }), base_address + 0xa0);
-
-        /// address: 0x600080a4
-        /// rtc configure register
-        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// sw feed rtc wdt
-            RTC_WDT_FEED: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600080a8
-        /// rtc configure register
-        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the key of rtc wdt
-            WDT_WKEY: u32,
-        }), base_address + 0xa8);
-
-        /// address: 0x600080ac
-        /// rtc configure register
-        pub const SWD_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// swd reset flag
-            SWD_RESET_FLAG: u1,
-            /// swd interrupt for feeding
-            SWD_FEED_INT: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// Bypass swd rst
-            SWD_BYPASS_RST: u1,
-            /// adjust signal width send to swd
-            SWD_SIGNAL_WIDTH: u10,
-            /// reset swd reset flag
-            SWD_RST_FLAG_CLR: u1,
-            /// Sw feed swd
-            SWD_FEED: u1,
-            /// disabel SWD
-            SWD_DISABLE: u1,
-            /// automatically feed swd when int comes
-            SWD_AUTO_FEED_EN: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600080b0
-        /// rtc configure register
-        pub const SWD_WPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the key of super wdt
-            SWD_WKEY: u32,
-        }), base_address + 0xb0);
-
-        /// address: 0x600080b4
-        /// rtc configure register
-        pub const SW_CPU_STALL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            /// {reg_sw_stall_appcpu_c1[5:0]
-            SW_STALL_APPCPU_C1: u6,
-            /// stall cpu by software
-            SW_STALL_PROCPU_C1: u6,
-        }), base_address + 0xb4);
-
-        /// address: 0x600080b8
-        /// rtc configure register
-        pub const STORE4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH4: u32,
-        }), base_address + 0xb8);
-
-        /// address: 0x600080bc
-        /// rtc configure register
-        pub const STORE5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH5: u32,
-        }), base_address + 0xbc);
-
-        /// address: 0x600080c0
-        /// rtc configure register
-        pub const STORE6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH6: u32,
-        }), base_address + 0xc0);
-
-        /// address: 0x600080c4
-        /// rtc configure register
-        pub const STORE7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reserved register
-            RTC_SCRATCH7: u32,
-        }), base_address + 0xc4);
-
-        /// address: 0x600080c8
-        /// rtc configure register
-        pub const LOW_POWER_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// rom0 power down
-            XPD_ROM0: u1,
-            reserved0: u1,
-            /// External DCDC power down
-            XPD_DIG_DCDC: u1,
-            /// rtc peripheral iso
-            RTC_PERI_ISO: u1,
-            /// rtc peripheral power down
-            XPD_RTC_PERI: u1,
-            /// wifi iso
-            WIFI_ISO: u1,
-            /// wifi wrap power down
-            XPD_WIFI: u1,
-            /// digital wrap iso
-            DIG_ISO: u1,
-            /// digital wrap power down
-            XPD_DIG: u1,
-            /// touch should start to work
-            RTC_TOUCH_STATE_START: u1,
-            /// touch is about to working. Switch rtc main state
-            RTC_TOUCH_STATE_SWITCH: u1,
-            /// touch is in sleep state
-            RTC_TOUCH_STATE_SLP: u1,
-            /// touch is done
-            RTC_TOUCH_STATE_DONE: u1,
-            /// ulp/cocpu should start to work
-            RTC_COCPU_STATE_START: u1,
-            /// ulp/cocpu is about to working. Switch rtc main state
-            RTC_COCPU_STATE_SWITCH: u1,
-            /// ulp/cocpu is in sleep state
-            RTC_COCPU_STATE_SLP: u1,
-            /// ulp/cocpu is done
-            RTC_COCPU_STATE_DONE: u1,
-            /// no use any more
-            RTC_MAIN_STATE_XTAL_ISO: u1,
-            /// rtc main state machine is in states that pll should be running
-            RTC_MAIN_STATE_PLL_ON: u1,
-            /// rtc is ready to receive wake up trigger from wake up source
-            RTC_RDY_FOR_WAKEUP: u1,
-            /// rtc main state machine has been waited for some cycles
-            RTC_MAIN_STATE_WAIT_END: u1,
-            /// rtc main state machine is in the states of wakeup process
-            RTC_IN_WAKEUP_STATE: u1,
-            /// rtc main state machine is in the states of low power
-            RTC_IN_LOW_POWER_STATE: u1,
-            /// rtc main state machine is in wait 8m state
-            RTC_MAIN_STATE_IN_WAIT_8M: u1,
-            /// rtc main state machine is in wait pll state
-            RTC_MAIN_STATE_IN_WAIT_PLL: u1,
-            /// rtc main state machine is in wait xtal state
-            RTC_MAIN_STATE_IN_WAIT_XTL: u1,
-            /// rtc main state machine is in sleep state
-            RTC_MAIN_STATE_IN_SLP: u1,
-            /// rtc main state machine is in idle state
-            RTC_MAIN_STATE_IN_IDLE: u1,
-            /// rtc main state machine status
-            RTC_MAIN_STATE: u4,
-        }), base_address + 0xc8);
-
-        /// address: 0x600080cc
-        /// rtc configure register
-        pub const DIAG0 = @intToPtr(*volatile Mmio(32, packed struct {
-            RTC_LOW_POWER_DIAG1: u32,
-        }), base_address + 0xcc);
-
-        /// address: 0x600080d0
-        /// rtc configure register
-        pub const PAD_HOLD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the hold configure of rtc gpio0
-            RTC_GPIO_PIN0_HOLD: u1,
-            /// the hold configure of rtc gpio1
-            RTC_GPIO_PIN1_HOLD: u1,
-            /// the hold configure of rtc gpio2
-            RTC_GPIO_PIN2_HOLD: u1,
-            /// the hold configure of rtc gpio3
-            RTC_GPIO_PIN3_HOLD: u1,
-            /// the hold configure of rtc gpio4
-            RTC_GPIO_PIN4_HOLD: u1,
-            /// the hold configure of rtc gpio5
-            RTC_GPIO_PIN5_HOLD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x600080d4
-        /// rtc configure register
-        pub const DIG_PAD_HOLD = @intToPtr(*volatile u32, base_address + 0xd4);
-
-        /// address: 0x600080d8
-        /// rtc configure register
-        pub const BROWN_OUT = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// brown out interrupt wait cycles
-            INT_WAIT: u10,
-            /// enable close flash when brown out happens
-            CLOSE_FLASH_ENA: u1,
-            /// enable power down RF when brown out happens
-            PD_RF_ENA: u1,
-            /// brown out reset wait cycles
-            RST_WAIT: u10,
-            /// enable brown out reset
-            RST_ENA: u1,
-            /// 1: 4-pos reset
-            RST_SEL: u1,
-            /// brown_out origin reset enable
-            ANA_RST_EN: u1,
-            /// clear brown out counter
-            CNT_CLR: u1,
-            /// enable brown out
-            ENA: u1,
-            /// the flag of brown det from analog
-            DET: u1,
-        }), base_address + 0xd8);
-
-        /// address: 0x600080dc
-        /// rtc configure register
-        pub const TIME_LOW1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// RTC timer low 32 bits
-            RTC_TIMER_VALUE1_LOW: u32,
-        }), base_address + 0xdc);
-
-        /// address: 0x600080e0
-        /// rtc configure register
-        pub const TIME_HIGH1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// RTC timer high 16 bits
-            RTC_TIMER_VALUE1_HIGH: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0xe0);
-
-        /// address: 0x600080e4
-        /// rtc configure register
-        pub const XTAL32K_CLK_FACTOR = @intToPtr(*volatile u32, base_address + 0xe4);
-
-        /// address: 0x600080e8
-        /// rtc configure register
-        pub const XTAL32K_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// cycles to wait to return noral xtal 32k
-            XTAL32K_RETURN_WAIT: u4,
-            /// cycles to wait to repower on xtal 32k
-            XTAL32K_RESTART_WAIT: u16,
-            /// If no clock detected for this amount of time
-            XTAL32K_WDT_TIMEOUT: u8,
-            /// if restarted xtal32k period is smaller than this
-            XTAL32K_STABLE_THRES: u4,
-        }), base_address + 0xe8);
-
-        /// address: 0x600080ec
-        /// rtc configure register
-        pub const USB_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// disable io_mux reset
-            IO_MUX_RESET_DISABLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-        }), base_address + 0xec);
-
-        /// address: 0x600080f0
-        /// RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG
-        pub const SLP_REJECT_CAUSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// sleep reject cause
-            REJECT_CAUSE: u18,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0xf0);
-
-        /// address: 0x600080f4
-        /// rtc configure register
-        pub const OPTION1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// force chip entry download mode
-            FORCE_DOWNLOAD_BOOT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xf4);
-
-        /// address: 0x600080f8
-        /// RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG
-        pub const SLP_WAKEUP_CAUSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// sleep wakeup cause
-            WAKEUP_CAUSE: u17,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0xf8);
-
-        /// address: 0x600080fc
-        /// rtc configure register
-        pub const ULP_CP_TIMER_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// sleep cycles for ULP-coprocessor timer
-            ULP_CP_TIMER_SLP_CYCLE: u24,
-        }), base_address + 0xfc);
-
-        /// address: 0x60008100
-        /// rtc configure register
-        pub const INT_ENA_RTC_W1TS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// enable sleep wakeup interrupt
-            SLP_WAKEUP_INT_ENA_W1TS: u1,
-            /// enable sleep reject interrupt
-            SLP_REJECT_INT_ENA_W1TS: u1,
-            reserved0: u1,
-            /// enable RTC WDT interrupt
-            RTC_WDT_INT_ENA_W1TS: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// enable brown out interrupt
-            RTC_BROWN_OUT_INT_ENA_W1TS: u1,
-            /// enable RTC main timer interrupt
-            RTC_MAIN_TIMER_INT_ENA_W1TS: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// enable super watch dog interrupt
-            RTC_SWD_INT_ENA_W1TS: u1,
-            /// enable xtal32k_dead interrupt
-            RTC_XTAL32K_DEAD_INT_ENA_W1TS: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// enbale gitch det interrupt
-            RTC_GLITCH_DET_INT_ENA_W1TS: u1,
-            /// enbale bbpll cal interrupt
-            RTC_BBPLL_CAL_INT_ENA_W1TS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x60008104
-        /// rtc configure register
-        pub const INT_ENA_RTC_W1TC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// clear sleep wakeup interrupt enable
-            SLP_WAKEUP_INT_ENA_W1TC: u1,
-            /// clear sleep reject interrupt enable
-            SLP_REJECT_INT_ENA_W1TC: u1,
-            reserved0: u1,
-            /// clear RTC WDT interrupt enable
-            RTC_WDT_INT_ENA_W1TC: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// clear brown out interrupt enable
-            RTC_BROWN_OUT_INT_ENA_W1TC: u1,
-            /// Clear RTC main timer interrupt enable
-            RTC_MAIN_TIMER_INT_ENA_W1TC: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// clear super watch dog interrupt enable
-            RTC_SWD_INT_ENA_W1TC: u1,
-            /// clear xtal32k_dead interrupt enable
-            RTC_XTAL32K_DEAD_INT_ENA_W1TC: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// clear gitch det interrupt enable
-            RTC_GLITCH_DET_INT_ENA_W1TC: u1,
-            /// clear bbpll cal interrupt enable
-            RTC_BBPLL_CAL_INT_ENA_W1TC: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x104);
-
-        /// address: 0x60008108
-        /// rtc configure register
-        pub const RETENTION_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// Retention clk sel
-            RETENTION_CLK_SEL: u1,
-            /// Retention done wait time
-            RETENTION_DONE_WAIT: u3,
-            /// Retention clkoff wait time
-            RETENTION_CLKOFF_WAIT: u4,
-            /// enable cpu retention when light sleep
-            RETENTION_EN: u1,
-            /// wait cycles for rention operation
-            RETENTION_WAIT: u5,
-        }), base_address + 0x108);
-
-        /// address: 0x6000810c
-        /// rtc configure register
-        pub const FIB_SEL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// select use analog fib signal
-            RTC_FIB_SEL: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x10c);
-
-        /// address: 0x60008110
-        /// rtc configure register
-        pub const GPIO_WAKEUP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// rtc gpio wakeup flag
-            RTC_GPIO_WAKEUP_STATUS: u6,
-            /// clear rtc gpio wakeup flag
-            RTC_GPIO_WAKEUP_STATUS_CLR: u1,
-            /// enable rtc io clk gate
-            RTC_GPIO_PIN_CLK_GATE: u1,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN5_INT_TYPE: u3,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN4_INT_TYPE: u3,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN3_INT_TYPE: u3,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN2_INT_TYPE: u3,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN1_INT_TYPE: u3,
-            /// configure gpio wakeup type
-            RTC_GPIO_PIN0_INT_TYPE: u3,
-            /// enable wakeup from rtc gpio5
-            RTC_GPIO_PIN5_WAKEUP_ENABLE: u1,
-            /// enable wakeup from rtc gpio4
-            RTC_GPIO_PIN4_WAKEUP_ENABLE: u1,
-            /// enable wakeup from rtc gpio3
-            RTC_GPIO_PIN3_WAKEUP_ENABLE: u1,
-            /// enable wakeup from rtc gpio2
-            RTC_GPIO_PIN2_WAKEUP_ENABLE: u1,
-            /// enable wakeup from rtc gpio1
-            RTC_GPIO_PIN1_WAKEUP_ENABLE: u1,
-            /// enable wakeup from rtc gpio0
-            RTC_GPIO_PIN0_WAKEUP_ENABLE: u1,
-        }), base_address + 0x110);
-
-        /// address: 0x60008114
-        /// rtc configure register
-        pub const DBG_SEL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// use for debug
-            RTC_DEBUG_12M_NO_GATING: u1,
-            /// use for debug
-            RTC_DEBUG_BIT_SEL: u5,
-            /// use for debug
-            RTC_DEBUG_SEL0: u5,
-            /// use for debug
-            RTC_DEBUG_SEL1: u5,
-            /// use for debug
-            RTC_DEBUG_SEL2: u5,
-            /// use for debug
-            RTC_DEBUG_SEL3: u5,
-            /// use for debug
-            RTC_DEBUG_SEL4: u5,
-        }), base_address + 0x114);
-
-        /// address: 0x60008118
-        /// rtc configure register
-        pub const DBG_MAP = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            /// use for debug
-            RTC_GPIO_PIN5_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN4_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN3_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN2_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN1_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN0_MUX_SEL: u1,
-            /// use for debug
-            RTC_GPIO_PIN5_FUN_SEL: u4,
-            /// use for debug
-            RTC_GPIO_PIN4_FUN_SEL: u4,
-            /// use for debug
-            RTC_GPIO_PIN3_FUN_SEL: u4,
-            /// use for debug
-            RTC_GPIO_PIN2_FUN_SEL: u4,
-            /// use for debug
-            RTC_GPIO_PIN1_FUN_SEL: u4,
-            /// use for debug
-            RTC_GPIO_PIN0_FUN_SEL: u4,
-        }), base_address + 0x118);
-
-        /// address: 0x6000811c
-        /// rtc configure register
-        pub const SENSOR_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            /// reg_sar2_pwdet_cct
-            SAR2_PWDET_CCT: u3,
-            /// force power up SAR
-            FORCE_XPD_SAR: u2,
-        }), base_address + 0x11c);
-
-        /// address: 0x60008120
-        /// rtc configure register
-        pub const DBG_SAR_SEL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            /// use for debug
-            SAR_DEBUG_SEL: u5,
-        }), base_address + 0x120);
-
-        /// address: 0x60008124
-        /// rtc configure register
-        pub const PG_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            /// power glitch desense
-            POWER_GLITCH_DSENSE: u2,
-            /// force disable power glitch
-            POWER_GLITCH_FORCE_PD: u1,
-            /// force enable power glitch
-            POWER_GLITCH_FORCE_PU: u1,
-            /// use efuse value control power glitch enable
-            POWER_GLITCH_EFUSE_SEL: u1,
-            /// enable power glitch
-            POWER_GLITCH_EN: u1,
-        }), base_address + 0x124);
-
-        /// address: 0x600081fc
-        /// rtc configure register
-        pub const DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// verision
-            RTC_CNTL_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x1fc);
-    };
-
-    /// Sensitive
-    pub const SENSITIVE = struct {
-        pub const base_address = 0x600c1000;
-
-        /// address: 0x600c1000
-        /// SENSITIVE_ROM_TABLE_LOCK_REG
-        pub const ROM_TABLE_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x0);
-
-        /// address: 0x600c1004
-        /// SENSITIVE_ROM_TABLE_REG
-        pub const ROM_TABLE = @intToPtr(*volatile u32, base_address + 0x4);
-
-        /// address: 0x600c1008
-        /// SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
-        pub const PRIVILEGE_MODE_SEL_LOCK = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x8);
-
-        /// address: 0x600c100c
-        /// SENSITIVE_PRIVILEGE_MODE_SEL_REG
-        pub const PRIVILEGE_MODE_SEL = @intToPtr(*volatile MmioInt(32, u1), base_address + 0xc);
-
-        /// address: 0x600c1010
-        /// SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
-        pub const APB_PERIPHERAL_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// apb_peripheral_access_lock
-            APB_PERIPHERAL_ACCESS_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x600c1014
-        /// SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
-        pub const APB_PERIPHERAL_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// apb_peripheral_access_split_burst
-            APB_PERIPHERAL_ACCESS_SPLIT_BURST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x600c1018
-        /// SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
-        pub const INTERNAL_SRAM_USAGE_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// internal_sram_usage_lock
-            INTERNAL_SRAM_USAGE_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x600c101c
-        /// SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
-        pub const INTERNAL_SRAM_USAGE_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// internal_sram_usage_cpu_cache
-            INTERNAL_SRAM_USAGE_CPU_CACHE: u1,
-            /// internal_sram_usage_cpu_sram
-            INTERNAL_SRAM_USAGE_CPU_SRAM: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x600c1020
-        /// SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
-        pub const INTERNAL_SRAM_USAGE_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// internal_sram_usage_mac_dump_sram
-            INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM: u3,
-            /// internal_sram_alloc_mac_dump
-            INTERNAL_SRAM_ALLOC_MAC_DUMP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x600c1024
-        /// SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
-        pub const INTERNAL_SRAM_USAGE_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// internal_sram_usage_log_sram
-            INTERNAL_SRAM_USAGE_LOG_SRAM: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x600c1028
-        /// SENSITIVE_CACHE_TAG_ACCESS_0_REG
-        pub const CACHE_TAG_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// cache_tag_access_lock
-            CACHE_TAG_ACCESS_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x600c102c
-        /// SENSITIVE_CACHE_TAG_ACCESS_1_REG
-        pub const CACHE_TAG_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// pro_i_tag_rd_acs
-            PRO_I_TAG_RD_ACS: u1,
-            /// pro_i_tag_wr_acs
-            PRO_I_TAG_WR_ACS: u1,
-            /// pro_d_tag_rd_acs
-            PRO_D_TAG_RD_ACS: u1,
-            /// pro_d_tag_wr_acs
-            PRO_D_TAG_WR_ACS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x600c1030
-        /// SENSITIVE_CACHE_MMU_ACCESS_0_REG
-        pub const CACHE_MMU_ACCESS_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// cache_mmu_access_lock
-            CACHE_MMU_ACCESS_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x600c1034
-        /// SENSITIVE_CACHE_MMU_ACCESS_1_REG
-        pub const CACHE_MMU_ACCESS_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// pro_mmu_rd_acs
-            PRO_MMU_RD_ACS: u1,
-            /// pro_mmu_wr_acs
-            PRO_MMU_WR_ACS: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x600c1038
-        /// SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_SPI2_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_spi2_pms_constrain_lock
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x600c103c
-        /// SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_SPI2_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x600c1040
-        /// SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_uchi0_pms_constrain_lock
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x600c1044
-        /// SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x600c1048
-        /// SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_I2S0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_i2s0_pms_constrain_lock
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x600c104c
-        /// SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_I2S0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x600c1050
-        /// SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_MAC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_mac_pms_constrain_lock
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x600c1054
-        /// SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_MAC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_mac_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x600c1058
-        /// SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_backup_pms_constrain_lock
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x600c105c
-        /// SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_backup_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x600c1060
-        /// SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_LC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_lc_pms_constrain_lock
-            DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x600c1064
-        /// SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_LC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_lc_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x600c1068
-        /// SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_AES_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_aes_pms_constrain_lock
-            DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x600c106c
-        /// SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_AES_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_aes_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x600c1070
-        /// SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_SHA_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_sha_pms_constrain_lock
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x600c1074
-        /// SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_SHA_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_sha_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x600c1078
-        /// SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
-        pub const DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_adc_dac_pms_constrain_lock
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x600c107c
-        /// SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
-        pub const DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x600c1080
-        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
-        pub const DMA_APBPERI_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_pms_monitor_lock
-            DMA_APBPERI_PMS_MONITOR_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x600c1084
-        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
-        pub const DMA_APBPERI_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_pms_monitor_violate_clr
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR: u1,
-            /// dma_apbperi_pms_monitor_violate_en
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x600c1088
-        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
-        pub const DMA_APBPERI_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_pms_monitor_violate_intr
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR: u1,
-            /// dma_apbperi_pms_monitor_violate_status_world
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-            /// dma_apbperi_pms_monitor_violate_status_addr
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x600c108c
-        /// SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
-        pub const DMA_APBPERI_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// dma_apbperi_pms_monitor_violate_status_wr
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-            /// dma_apbperi_pms_monitor_violate_status_byteen
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x600c1090
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_dram0_dma_split_line_constrain_lock
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x600c1094
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_dram0_dma_sram_category_0
-            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0: u2,
-            /// core_x_iram0_dram0_dma_sram_category_1
-            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1: u2,
-            /// core_x_iram0_dram0_dma_sram_category_2
-            CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_iram0_dram0_dma_sram_splitaddr
-            CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x94);
-
-        /// address: 0x600c1098
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_sram_line_0_category_0
-            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0: u2,
-            /// core_x_iram0_sram_line_0_category_1
-            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1: u2,
-            /// core_x_iram0_sram_line_0_category_2
-            CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_iram0_sram_line_0_splitaddr
-            CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x600c109c
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_sram_line_1_category_0
-            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0: u2,
-            /// core_x_iram0_sram_line_1_category_1
-            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1: u2,
-            /// core_x_iram0_sram_line_1_category_2
-            CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_iram0_sram_line_1_splitaddr
-            CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x9c);
-
-        /// address: 0x600c10a0
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_dram0_dma_sram_line_0_category_0
-            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0: u2,
-            /// core_x_dram0_dma_sram_line_0_category_1
-            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1: u2,
-            /// core_x_dram0_dma_sram_line_0_category_2
-            CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_dram0_dma_sram_line_0_splitaddr
-            CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0xa0);
-
-        /// address: 0x600c10a4
-        /// SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
-        pub const CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_dram0_dma_sram_line_1_category_0
-            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0: u2,
-            /// core_x_dram0_dma_sram_line_1_category_1
-            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1: u2,
-            /// core_x_dram0_dma_sram_line_1_category_2
-            CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_dram0_dma_sram_line_1_splitaddr
-            CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600c10a8
-        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
-        pub const CORE_X_IRAM0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_pms_constrain_lock
-            CORE_X_IRAM0_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600c10ac
-        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
-        pub const CORE_X_IRAM0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_pms_constrain_sram_world_1_pms_0
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u3,
-            /// core_x_iram0_pms_constrain_sram_world_1_pms_1
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u3,
-            /// core_x_iram0_pms_constrain_sram_world_1_pms_2
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u3,
-            /// core_x_iram0_pms_constrain_sram_world_1_pms_3
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u3,
-            /// core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0: u3,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// core_x_iram0_pms_constrain_rom_world_1_pms
-            CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600c10b0
-        /// SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
-        pub const CORE_X_IRAM0_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_iram0_pms_constrain_sram_world_0_pms_0
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u3,
-            /// core_x_iram0_pms_constrain_sram_world_0_pms_1
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u3,
-            /// core_x_iram0_pms_constrain_sram_world_0_pms_2
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u3,
-            /// core_x_iram0_pms_constrain_sram_world_0_pms_3
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u3,
-            /// core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0
-            CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0: u3,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// core_x_iram0_pms_constrain_rom_world_0_pms
-            CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x600c10b4
-        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
-        pub const CORE_0_IRAM0_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_iram0_pms_monitor_lock
-            CORE_0_IRAM0_PMS_MONITOR_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600c10b8
-        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
-        pub const CORE_0_IRAM0_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_iram0_pms_monitor_violate_clr
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
-            /// core_0_iram0_pms_monitor_violate_en
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xb8);
-
-        /// address: 0x600c10bc
-        /// SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
-        pub const CORE_0_IRAM0_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_iram0_pms_monitor_violate_intr
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
-            /// core_0_iram0_pms_monitor_violate_status_wr
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-            /// core_0_iram0_pms_monitor_violate_status_loadstore
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE: u1,
-            /// core_0_iram0_pms_monitor_violate_status_world
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-            /// core_0_iram0_pms_monitor_violate_status_addr
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0xbc);
-
-        /// address: 0x600c10c0
-        /// SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
-        pub const CORE_X_DRAM0_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_dram0_pms_constrain_lock
-            CORE_X_DRAM0_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600c10c4
-        /// SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
-        pub const CORE_X_DRAM0_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_x_dram0_pms_constrain_sram_world_0_pms_0
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-            /// core_x_dram0_pms_constrain_sram_world_0_pms_1
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-            /// core_x_dram0_pms_constrain_sram_world_0_pms_2
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-            /// core_x_dram0_pms_constrain_sram_world_0_pms_3
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_x_dram0_pms_constrain_sram_world_1_pms_0
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-            /// core_x_dram0_pms_constrain_sram_world_1_pms_1
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-            /// core_x_dram0_pms_constrain_sram_world_1_pms_2
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-            /// core_x_dram0_pms_constrain_sram_world_1_pms_3
-            CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_x_dram0_pms_constrain_rom_world_0_pms
-            CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u2,
-            /// core_x_dram0_pms_constrain_rom_world_1_pms
-            CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xc4);
-
-        /// address: 0x600c10c8
-        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
-        pub const CORE_0_DRAM0_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_dram0_pms_monitor_lock
-            CORE_0_DRAM0_PMS_MONITOR_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600c10cc
-        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
-        pub const CORE_0_DRAM0_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_dram0_pms_monitor_violate_clr
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
-            /// core_0_dram0_pms_monitor_violate_en
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x600c10d0
-        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
-        pub const CORE_0_DRAM0_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_dram0_pms_monitor_violate_intr
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
-            /// core_0_dram0_pms_monitor_violate_status_lock
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK: u1,
-            /// core_0_dram0_pms_monitor_violate_status_world
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-            /// core_0_dram0_pms_monitor_violate_status_addr
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xd0);
-
-        /// address: 0x600c10d4
-        /// SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
-        pub const CORE_0_DRAM0_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_dram0_pms_monitor_violate_status_wr
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-            /// core_0_dram0_pms_monitor_violate_status_byteen
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xd4);
-
-        /// address: 0x600c10d8
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_lock
-            CORE_0_PIF_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xd8);
-
-        /// address: 0x600c10dc
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_0_uart
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART: u2,
-            /// core_0_pif_pms_constrain_world_0_g0spi_1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1: u2,
-            /// core_0_pif_pms_constrain_world_0_g0spi_0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0: u2,
-            /// core_0_pif_pms_constrain_world_0_gpio
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO: u2,
-            /// core_0_pif_pms_constrain_world_0_fe2
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2: u2,
-            /// core_0_pif_pms_constrain_world_0_fe
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE: u2,
-            /// core_0_pif_pms_constrain_world_0_timer
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER: u2,
-            /// core_0_pif_pms_constrain_world_0_rtc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC: u2,
-            /// core_0_pif_pms_constrain_world_0_io_mux
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX: u2,
-            /// core_0_pif_pms_constrain_world_0_wdg
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_0_misc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC: u2,
-            /// core_0_pif_pms_constrain_world_0_i2c
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C: u2,
-            reserved4: u1,
-            reserved5: u1,
-            /// core_0_pif_pms_constrain_world_0_uart1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1: u2,
-        }), base_address + 0xdc);
-
-        /// address: 0x600c10e0
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_0_bt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_0_i2c_ext0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0: u2,
-            /// core_0_pif_pms_constrain_world_0_uhci0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_0_rmt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT: u2,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_0_pif_pms_constrain_world_0_ledc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// core_0_pif_pms_constrain_world_0_bb
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB: u2,
-            reserved12: u1,
-            reserved13: u1,
-            /// core_0_pif_pms_constrain_world_0_timergroup
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP: u2,
-            /// core_0_pif_pms_constrain_world_0_timergroup1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1: u2,
-            /// core_0_pif_pms_constrain_world_0_systimer
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER: u2,
-        }), base_address + 0xe0);
-
-        /// address: 0x600c10e4
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_0_spi_2
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_0_apb_ctrl
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL: u2,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// core_0_pif_pms_constrain_world_0_can
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN: u2,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_0_pif_pms_constrain_world_0_i2s1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// core_0_pif_pms_constrain_world_0_rwbt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT: u2,
-            reserved14: u1,
-            reserved15: u1,
-            /// core_0_pif_pms_constrain_world_0_wifimac
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC: u2,
-            /// core_0_pif_pms_constrain_world_0_pwr
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR: u2,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0xe4);
-
-        /// address: 0x600c10e8
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_0_usb_wrap
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP: u2,
-            /// core_0_pif_pms_constrain_world_0_crypto_peri
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI: u2,
-            /// core_0_pif_pms_constrain_world_0_crypto_dma
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA: u2,
-            /// core_0_pif_pms_constrain_world_0_apb_adc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_0_bt_pwr
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR: u2,
-            /// core_0_pif_pms_constrain_world_0_usb_device
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE: u2,
-            /// core_0_pif_pms_constrain_world_0_system
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM: u2,
-            /// core_0_pif_pms_constrain_world_0_sensitive
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE: u2,
-            /// core_0_pif_pms_constrain_world_0_interrupt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT: u2,
-            /// core_0_pif_pms_constrain_world_0_dma_copy
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY: u2,
-            /// core_0_pif_pms_constrain_world_0_cache_config
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG: u2,
-            /// core_0_pif_pms_constrain_world_0_ad
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD: u2,
-            /// core_0_pif_pms_constrain_world_0_dio
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO: u2,
-            /// core_0_pif_pms_constrain_world_0_world_controller
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER: u2,
-        }), base_address + 0xe8);
-
-        /// address: 0x600c10ec
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_1_uart
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART: u2,
-            /// core_0_pif_pms_constrain_world_1_g0spi_1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1: u2,
-            /// core_0_pif_pms_constrain_world_1_g0spi_0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0: u2,
-            /// core_0_pif_pms_constrain_world_1_gpio
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO: u2,
-            /// core_0_pif_pms_constrain_world_1_fe2
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2: u2,
-            /// core_0_pif_pms_constrain_world_1_fe
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE: u2,
-            /// core_0_pif_pms_constrain_world_1_timer
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER: u2,
-            /// core_0_pif_pms_constrain_world_1_rtc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC: u2,
-            /// core_0_pif_pms_constrain_world_1_io_mux
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX: u2,
-            /// core_0_pif_pms_constrain_world_1_wdg
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_1_misc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC: u2,
-            /// core_0_pif_pms_constrain_world_1_i2c
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C: u2,
-            reserved4: u1,
-            reserved5: u1,
-            /// core_0_pif_pms_constrain_world_1_uart1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1: u2,
-        }), base_address + 0xec);
-
-        /// address: 0x600c10f0
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_1_bt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_1_i2c_ext0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0: u2,
-            /// core_0_pif_pms_constrain_world_1_uhci0
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_1_rmt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT: u2,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_0_pif_pms_constrain_world_1_ledc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// core_0_pif_pms_constrain_world_1_bb
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB: u2,
-            reserved12: u1,
-            reserved13: u1,
-            /// core_0_pif_pms_constrain_world_1_timergroup
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP: u2,
-            /// core_0_pif_pms_constrain_world_1_timergroup1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1: u2,
-            /// core_0_pif_pms_constrain_world_1_systimer
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER: u2,
-        }), base_address + 0xf0);
-
-        /// address: 0x600c10f4
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_world_1_spi_2
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_1_apb_ctrl
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL: u2,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// core_0_pif_pms_constrain_world_1_can
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN: u2,
-            reserved6: u1,
-            reserved7: u1,
-            /// core_0_pif_pms_constrain_world_1_i2s1
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// core_0_pif_pms_constrain_world_1_rwbt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT: u2,
-            reserved14: u1,
-            reserved15: u1,
-            /// core_0_pif_pms_constrain_world_1_wifimac
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC: u2,
-            /// core_0_pif_pms_constrain_world_1_pwr
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR: u2,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0xf4);
-
-        /// address: 0x600c10f8
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_8 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            /// core_0_pif_pms_constrain_world_1_usb_wrap
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP: u2,
-            /// core_0_pif_pms_constrain_world_1_crypto_peri
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI: u2,
-            /// core_0_pif_pms_constrain_world_1_crypto_dma
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA: u2,
-            /// core_0_pif_pms_constrain_world_1_apb_adc
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// core_0_pif_pms_constrain_world_1_bt_pwr
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR: u2,
-            /// core_0_pif_pms_constrain_world_1_usb_device
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE: u2,
-            /// core_0_pif_pms_constrain_world_1_system
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM: u2,
-            /// core_0_pif_pms_constrain_world_1_sensitive
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE: u2,
-            /// core_0_pif_pms_constrain_world_1_interrupt
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT: u2,
-            /// core_0_pif_pms_constrain_world_1_dma_copy
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY: u2,
-            /// core_0_pif_pms_constrain_world_1_cache_config
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG: u2,
-            /// core_0_pif_pms_constrain_world_1_ad
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD: u2,
-            /// core_0_pif_pms_constrain_world_1_dio
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO: u2,
-            /// core_0_pif_pms_constrain_world_1_world_controller
-            CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER: u2,
-        }), base_address + 0xf8);
-
-        /// address: 0x600c10fc
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_rtcfast_spltaddr_world_0
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0: u11,
-            /// core_0_pif_pms_constrain_rtcfast_spltaddr_world_1
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1: u11,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0xfc);
-
-        /// address: 0x600c1100
-        /// SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
-        pub const CORE_0_PIF_PMS_CONSTRAIN_10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_constrain_rtcfast_world_0_l
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L: u3,
-            /// core_0_pif_pms_constrain_rtcfast_world_0_h
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H: u3,
-            /// core_0_pif_pms_constrain_rtcfast_world_1_l
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L: u3,
-            /// core_0_pif_pms_constrain_rtcfast_world_1_h
-            CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x100);
-
-        /// address: 0x600c1104
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
-        pub const REGION_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_lock
-            REGION_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x104);
-
-        /// address: 0x600c1108
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
-        pub const REGION_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_world_0_area_0
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_0: u2,
-            /// region_pms_constrain_world_0_area_1
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_1: u2,
-            /// region_pms_constrain_world_0_area_2
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_2: u2,
-            /// region_pms_constrain_world_0_area_3
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_3: u2,
-            /// region_pms_constrain_world_0_area_4
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_4: u2,
-            /// region_pms_constrain_world_0_area_5
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_5: u2,
-            /// region_pms_constrain_world_0_area_6
-            REGION_PMS_CONSTRAIN_WORLD_0_AREA_6: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x108);
-
-        /// address: 0x600c110c
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
-        pub const REGION_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_world_1_area_0
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_0: u2,
-            /// region_pms_constrain_world_1_area_1
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_1: u2,
-            /// region_pms_constrain_world_1_area_2
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_2: u2,
-            /// region_pms_constrain_world_1_area_3
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_3: u2,
-            /// region_pms_constrain_world_1_area_4
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_4: u2,
-            /// region_pms_constrain_world_1_area_5
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_5: u2,
-            /// region_pms_constrain_world_1_area_6
-            REGION_PMS_CONSTRAIN_WORLD_1_AREA_6: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-        }), base_address + 0x10c);
-
-        /// address: 0x600c1110
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
-        pub const REGION_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_0
-            REGION_PMS_CONSTRAIN_ADDR_0: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x110);
-
-        /// address: 0x600c1114
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
-        pub const REGION_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_1
-            REGION_PMS_CONSTRAIN_ADDR_1: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x114);
-
-        /// address: 0x600c1118
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
-        pub const REGION_PMS_CONSTRAIN_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_2
-            REGION_PMS_CONSTRAIN_ADDR_2: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x118);
-
-        /// address: 0x600c111c
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
-        pub const REGION_PMS_CONSTRAIN_6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_3
-            REGION_PMS_CONSTRAIN_ADDR_3: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x11c);
-
-        /// address: 0x600c1120
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
-        pub const REGION_PMS_CONSTRAIN_7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_4
-            REGION_PMS_CONSTRAIN_ADDR_4: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x120);
-
-        /// address: 0x600c1124
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
-        pub const REGION_PMS_CONSTRAIN_8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_5
-            REGION_PMS_CONSTRAIN_ADDR_5: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x124);
-
-        /// address: 0x600c1128
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
-        pub const REGION_PMS_CONSTRAIN_9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_6
-            REGION_PMS_CONSTRAIN_ADDR_6: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x128);
-
-        /// address: 0x600c112c
-        /// SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
-        pub const REGION_PMS_CONSTRAIN_10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// region_pms_constrain_addr_7
-            REGION_PMS_CONSTRAIN_ADDR_7: u30,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x12c);
-
-        /// address: 0x600c1130
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
-        pub const CORE_0_PIF_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_lock
-            CORE_0_PIF_PMS_MONITOR_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x130);
-
-        /// address: 0x600c1134
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
-        pub const CORE_0_PIF_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_violate_clr
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR: u1,
-            /// core_0_pif_pms_monitor_violate_en
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x134);
-
-        /// address: 0x600c1138
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
-        pub const CORE_0_PIF_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_violate_intr
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR: u1,
-            /// core_0_pif_pms_monitor_violate_status_hport_0
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0: u1,
-            /// core_0_pif_pms_monitor_violate_status_hsize
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
-            /// core_0_pif_pms_monitor_violate_status_hwrite
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
-            /// core_0_pif_pms_monitor_violate_status_hworld
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x138);
-
-        /// address: 0x600c113c
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
-        pub const CORE_0_PIF_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_violate_status_haddr
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR: u32,
-        }), base_address + 0x13c);
-
-        /// address: 0x600c1140
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
-        pub const CORE_0_PIF_PMS_MONITOR_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_nonword_violate_clr
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR: u1,
-            /// core_0_pif_pms_monitor_nonword_violate_en
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x140);
-
-        /// address: 0x600c1144
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
-        pub const CORE_0_PIF_PMS_MONITOR_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_nonword_violate_intr
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR: u1,
-            /// core_0_pif_pms_monitor_nonword_violate_status_hsize
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE: u2,
-            /// core_0_pif_pms_monitor_nonword_violate_status_hworld
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x144);
-
-        /// address: 0x600c1148
-        /// SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
-        pub const CORE_0_PIF_PMS_MONITOR_6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// core_0_pif_pms_monitor_nonword_violate_status_haddr
-            CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR: u32,
-        }), base_address + 0x148);
-
-        /// address: 0x600c114c
-        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
-        pub const BACKUP_BUS_PMS_CONSTRAIN_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_constrain_lock
-            BACKUP_BUS_PMS_CONSTRAIN_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x14c);
-
-        /// address: 0x600c1150
-        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
-        pub const BACKUP_BUS_PMS_CONSTRAIN_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_constrain_uart
-            BACKUP_BUS_PMS_CONSTRAIN_UART: u2,
-            /// backup_bus_pms_constrain_g0spi_1
-            BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1: u2,
-            /// backup_bus_pms_constrain_g0spi_0
-            BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0: u2,
-            /// backup_bus_pms_constrain_gpio
-            BACKUP_BUS_PMS_CONSTRAIN_GPIO: u2,
-            /// backup_bus_pms_constrain_fe2
-            BACKUP_BUS_PMS_CONSTRAIN_FE2: u2,
-            /// backup_bus_pms_constrain_fe
-            BACKUP_BUS_PMS_CONSTRAIN_FE: u2,
-            /// backup_bus_pms_constrain_timer
-            BACKUP_BUS_PMS_CONSTRAIN_TIMER: u2,
-            /// backup_bus_pms_constrain_rtc
-            BACKUP_BUS_PMS_CONSTRAIN_RTC: u2,
-            /// backup_bus_pms_constrain_io_mux
-            BACKUP_BUS_PMS_CONSTRAIN_IO_MUX: u2,
-            /// backup_bus_pms_constrain_wdg
-            BACKUP_BUS_PMS_CONSTRAIN_WDG: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// backup_bus_pms_constrain_misc
-            BACKUP_BUS_PMS_CONSTRAIN_MISC: u2,
-            /// backup_bus_pms_constrain_i2c
-            BACKUP_BUS_PMS_CONSTRAIN_I2C: u2,
-            reserved4: u1,
-            reserved5: u1,
-            /// backup_bus_pms_constrain_uart1
-            BACKUP_BUS_PMS_CONSTRAIN_UART1: u2,
-        }), base_address + 0x150);
-
-        /// address: 0x600c1154
-        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
-        pub const BACKUP_BUS_PMS_CONSTRAIN_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_constrain_bt
-            BACKUP_BUS_PMS_CONSTRAIN_BT: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// backup_bus_pms_constrain_i2c_ext0
-            BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0: u2,
-            /// backup_bus_pms_constrain_uhci0
-            BACKUP_BUS_PMS_CONSTRAIN_UHCI0: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// backup_bus_pms_constrain_rmt
-            BACKUP_BUS_PMS_CONSTRAIN_RMT: u2,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// backup_bus_pms_constrain_ledc
-            BACKUP_BUS_PMS_CONSTRAIN_LEDC: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// backup_bus_pms_constrain_bb
-            BACKUP_BUS_PMS_CONSTRAIN_BB: u2,
-            reserved12: u1,
-            reserved13: u1,
-            /// backup_bus_pms_constrain_timergroup
-            BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP: u2,
-            /// backup_bus_pms_constrain_timergroup1
-            BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1: u2,
-            /// backup_bus_pms_constrain_systimer
-            BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER: u2,
-        }), base_address + 0x154);
-
-        /// address: 0x600c1158
-        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
-        pub const BACKUP_BUS_PMS_CONSTRAIN_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_constrain_spi_2
-            BACKUP_BUS_PMS_CONSTRAIN_SPI_2: u2,
-            reserved0: u1,
-            reserved1: u1,
-            /// backup_bus_pms_constrain_apb_ctrl
-            BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL: u2,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// backup_bus_pms_constrain_can
-            BACKUP_BUS_PMS_CONSTRAIN_CAN: u2,
-            reserved6: u1,
-            reserved7: u1,
-            /// backup_bus_pms_constrain_i2s1
-            BACKUP_BUS_PMS_CONSTRAIN_I2S1: u2,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// backup_bus_pms_constrain_rwbt
-            BACKUP_BUS_PMS_CONSTRAIN_RWBT: u2,
-            reserved14: u1,
-            reserved15: u1,
-            /// backup_bus_pms_constrain_wifimac
-            BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC: u2,
-            /// backup_bus_pms_constrain_pwr
-            BACKUP_BUS_PMS_CONSTRAIN_PWR: u2,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x158);
-
-        /// address: 0x600c115c
-        /// SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
-        pub const BACKUP_BUS_PMS_CONSTRAIN_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            /// backup_bus_pms_constrain_usb_wrap
-            BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP: u2,
-            /// backup_bus_pms_constrain_crypto_peri
-            BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI: u2,
-            /// backup_bus_pms_constrain_crypto_dma
-            BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA: u2,
-            /// backup_bus_pms_constrain_apb_adc
-            BACKUP_BUS_PMS_CONSTRAIN_APB_ADC: u2,
-            reserved2: u1,
-            reserved3: u1,
-            /// backup_bus_pms_constrain_bt_pwr
-            BACKUP_BUS_PMS_CONSTRAIN_BT_PWR: u2,
-            /// backup_bus_pms_constrain_usb_device
-            BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x15c);
-
-        /// address: 0x600c1160
-        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
-        pub const BACKUP_BUS_PMS_MONITOR_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_monitor_lock
-            BACKUP_BUS_PMS_MONITOR_LOCK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x160);
-
-        /// address: 0x600c1164
-        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
-        pub const BACKUP_BUS_PMS_MONITOR_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_monitor_violate_clr
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR: u1,
-            /// backup_bus_pms_monitor_violate_en
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x164);
-
-        /// address: 0x600c1168
-        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
-        pub const BACKUP_BUS_PMS_MONITOR_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_monitor_violate_intr
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR: u1,
-            /// backup_bus_pms_monitor_violate_status_htrans
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS: u2,
-            /// backup_bus_pms_monitor_violate_status_hsize
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
-            /// backup_bus_pms_monitor_violate_status_hwrite
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x168);
-
-        /// address: 0x600c116c
-        /// SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
-        pub const BACKUP_BUS_PMS_MONITOR_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// backup_bus_pms_monitor_violate_haddr
-            BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR: u32,
-        }), base_address + 0x16c);
-
-        /// address: 0x600c1170
-        /// SENSITIVE_CLOCK_GATE_REG
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// clk_en
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x170);
-
-        /// address: 0x600c1ffc
-        /// SENSITIVE_DATE_REG
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xffc);
-    };
-
-    /// SHA (Secure Hash Algorithm) Accelerator
-    pub const SHA = struct {
-        pub const base_address = 0x6003b000;
-
-        /// address: 0x6003b000
-        /// Initial configuration register.
-        pub const MODE = @intToPtr(*volatile MmioInt(32, u3), base_address + 0x0);
-
-        /// address: 0x6003b004
-        /// SHA 512/t configuration register 0.
-        pub const T_STRING = @intToPtr(*volatile u32, base_address + 0x4);
-
-        /// address: 0x6003b008
-        /// SHA 512/t configuration register 1.
-        pub const T_LENGTH = @intToPtr(*volatile MmioInt(32, u6), base_address + 0x8);
-
-        /// address: 0x6003b00c
-        /// DMA configuration register 0.
-        pub const DMA_BLOCK_NUM = @intToPtr(*volatile MmioInt(32, u6), base_address + 0xc);
-
-        /// address: 0x6003b010
-        /// Typical SHA configuration register 0.
-        pub const START = @intToPtr(*volatile MmioInt(32, u31), base_address + 0x10);
-
-        /// address: 0x6003b014
-        /// Typical SHA configuration register 1.
-        pub const CONTINUE = @intToPtr(*volatile MmioInt(32, u31), base_address + 0x14);
-
-        /// address: 0x6003b018
-        /// Busy register.
-        pub const BUSY = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Sha busy state. 1'b0: idle. 1'b1: busy.
-            STATE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6003b01c
-        /// DMA configuration register 1.
-        pub const DMA_START = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x1c);
-
-        /// address: 0x6003b020
-        /// DMA configuration register 2.
-        pub const DMA_CONTINUE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x20);
-
-        /// address: 0x6003b024
-        /// Interrupt clear register.
-        pub const CLEAR_IRQ = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Clear sha interrupt.
-            CLEAR_INTERRUPT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x6003b028
-        /// Interrupt enable register.
-        pub const IRQ_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
-            INTERRUPT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6003b02c
-        /// Date register.
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x2c);
-
-        /// address: 0x6003b040
-        /// Sha H memory which contains intermediate hash or finial hash.
-        pub const H_MEM = @intToPtr(*volatile [64]u8, base_address + 0x40);
-
-        /// address: 0x6003b080
-        /// Sha M memory which contains message.
-        pub const M_MEM = @intToPtr(*volatile [64]u8, base_address + 0x80);
-    };
-
-    /// SPI (Serial Peripheral Interface) Controller
-    pub const SPI0 = struct {
-        pub const base_address = 0x60003000;
-
-        /// address: 0x60003008
-        /// SPI0 control register.
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// In the dummy phase the signal level of spi is output by the spi controller.
-            FDUMMY_OUT: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// Apply 2 signals during command phase 1:enable 0: disable
-            FCMD_DUAL: u1,
-            /// Apply 4 signals during command phase 1:enable 0: disable
-            FCMD_QUAD: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio,
-            /// spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
-            FASTRD_MODE: u1,
-            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
-            FREAD_DUAL: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            /// The bit is used to set MISO line polarity, 1: high 0, low
-            Q_POL: u1,
-            /// The bit is used to set MOSI line polarity, 1: high 0, low
-            D_POL: u1,
-            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
-            FREAD_QUAD: u1,
-            /// Write protect signal output when SPI is idle. 1: output high, 0: output low.
-            WP: u1,
-            reserved13: u1,
-            /// In the read operations address phase and read-data phase apply 2 signals. 1:
-            /// enable 0: disable.
-            FREAD_DIO: u1,
-            /// In the read operations address phase and read-data phase apply 4 signals. 1:
-            /// enable 0: disable.
-            FREAD_QIO: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000300c
-        /// SPI0 control1 register.
-        pub const CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
-            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
-            /// inactive 3: SPI clock is alwasy on.
-            CLK_MODE: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            /// SPI0 RX FIFO reset signal.
-            RXFIFO_RST: u1,
-            padding0: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60003010
-        /// SPI0 control2 register.
-        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// (cycles-1) of prepare phase by spi clock this bits are combined with
-            /// spi_mem_cs_setup bit.
-            CS_SETUP_TIME: u5,
-            /// Spi cs signal is delayed to inactive by spi clock this bits are combined with
-            /// spi_mem_cs_hold bit.
-            CS_HOLD_TIME: u5,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// These bits are used to set the minimum CS high time tSHSL between SPI burst
-            /// transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI
-            /// core clock cycles.
-            CS_HOLD_DELAY: u6,
-            /// The FSM will be reset.
-            SYNC_RESET: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60003014
-        /// SPI clock division control register.
-        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In the master mode it must be equal to spi_mem_clkcnt_N.
-            CLKCNT_L: u8,
-            /// In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
-            CLKCNT_H: u8,
-            /// In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-            /// system/(spi_mem_clkcnt_N+1)
-            CLKCNT_N: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            /// Set this bit in 1-division mode.
-            CLK_EQU_SYSCLK: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60003018
-        /// SPI0 user register.
-        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// spi cs keep low when spi is in done phase. 1: enable 0: disable.
-            CS_HOLD: u1,
-            /// spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
-            CS_SETUP: u1,
-            reserved6: u1,
-            /// the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay
-            /// mode.
-            CK_OUT_EDGE: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            /// spi clock is disable in dummy phase when the bit is enable.
-            USR_DUMMY_IDLE: u1,
-            reserved23: u1,
-            reserved24: u1,
-            /// This bit enable the dummy phase of an operation.
-            USR_DUMMY: u1,
-            padding0: u1,
-            padding1: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000301c
-        /// SPI0 user1 register.
-        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length in spi_mem_clk cycles of dummy phase. The register value shall be
-            /// (cycle_num-1).
-            USR_DUMMY_CYCLELEN: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            /// The length in bits of address phase. The register value shall be (bit_num-1).
-            USR_ADDR_BITLEN: u6,
-        }), base_address + 0x1c);
-
-        /// address: 0x60003020
-        /// SPI0 user2 register.
-        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of command.
-            USR_COMMAND_VALUE: u16,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// The length in bits of command phase. The register value shall be (bit_num-1)
-            USR_COMMAND_BITLEN: u4,
-        }), base_address + 0x20);
-
-        /// address: 0x6000302c
-        /// SPI0 read control register.
-        pub const RD_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            /// Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode
-            /// bit.
-            WB_MODE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60003034
-        /// SPI0 misc register
-        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The bit is used to indicate the spi0_mst_st controlled transmitting is done.
-            TRANS_END: u1,
-            /// The bit is used to enable the interrupt of spi0_mst_st controlled transmitting
-            /// is done.
-            TRANS_END_INT_ENA: u1,
-            /// The bit is used to indicate the spi0_slv_st controlled transmitting is done.
-            CSPI_ST_TRANS_END: u1,
-            /// The bit is used to enable the interrupt of spi0_slv_st controlled transmitting
-            /// is done.
-            CSPI_ST_TRANS_END_INT_ENA: u1,
-            reserved3: u1,
-            reserved4: u1,
-            /// 1: spi clk line is high when idle 0: spi clk line is low when idle
-            CK_IDLE_EDGE: u1,
-            /// spi cs line keep low when the bit is set.
-            CS_KEEP_ACTIVE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x6000303c
-        /// SPI0 bit mode control register.
-        pub const CACHE_FCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// For SPI0, Cache access enable, 1: enable, 0:disable.
-            CACHE_REQ_EN: u1,
-            /// For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
-            CACHE_USR_ADDR_4BYTE: u1,
-            /// For SPI0, cache read flash for user define command, 1: enable, 0:disable.
-            CACHE_FLASH_USR_CMD: u1,
-            /// For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_dio.
-            FDIN_DUAL: u1,
-            /// For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_dio.
-            FDOUT_DUAL: u1,
-            /// For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is
-            /// the same with spi_mem_fread_dio.
-            FADDR_DUAL: u1,
-            /// For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_qio.
-            FDIN_QUAD: u1,
-            /// For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_qio.
-            FDOUT_QUAD: u1,
-            /// For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is
-            /// the same with spi_mem_fread_qio.
-            FADDR_QUAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60003054
-        /// SPI0 FSM status register
-        pub const FSM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation
-            /// state, 2: send command state, 3: send address state, 4: wait state, 5: read data
-            /// state, 6:write data state, 7: done state, 8: read data end state.
-            CSPI_ST: u4,
-            /// The current status of SPI0 master FSM: spi0_mst_st. 0: idle state,
-            /// 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4:
-            /// wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
-            EM_ST: u3,
-            /// The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
-            CSPI_LOCK_DELAY_TIME: u5,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x600030a8
-        /// SPI0 timing calibration register
-        pub const TIMING_CALI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The bit is used to enable timing adjust clock for all reading operations.
-            TIMING_CLK_ENA: u1,
-            /// The bit is used to enable timing auto-calibration for all reading operations.
-            TIMING_CALI: u1,
-            /// add extra dummy spi clock cycle length for spi clock calibration.
-            EXTRA_DUMMY_CYCLELEN: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600030ac
-        /// SPI0 input delay mode control register
-        pub const DIN_MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the input signals are delayed by system clock cycles, 0: input without delayed,
-            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
-            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
-            /// with the spi_clk high edge, 6: input with the spi_clk low edge
-            DIN0_MODE: u2,
-            /// the input signals are delayed by system clock cycles, 0: input without delayed,
-            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
-            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
-            /// with the spi_clk high edge, 6: input with the spi_clk low edge
-            DIN1_MODE: u2,
-            /// the input signals are delayed by system clock cycles, 0: input without delayed,
-            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
-            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
-            /// with the spi_clk high edge, 6: input with the spi_clk low edge
-            DIN2_MODE: u2,
-            /// the input signals are delayed by system clock cycles, 0: input without delayed,
-            /// 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3:
-            /// input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input
-            /// with the spi_clk high edge, 6: input with the spi_clk low edge
-            DIN3_MODE: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0xac);
-
-        /// address: 0x600030b0
-        /// SPI0 input delay number control register
-        pub const DIN_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-            /// delayed by 2 cycles,...
-            DIN0_NUM: u2,
-            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-            /// delayed by 2 cycles,...
-            DIN1_NUM: u2,
-            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-            /// delayed by 2 cycles,...
-            DIN2_NUM: u2,
-            /// the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1:
-            /// delayed by 2 cycles,...
-            DIN3_NUM: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0xb0);
-
-        /// address: 0x600030b4
-        /// SPI0 output delay mode control register
-        pub const DOUT_MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the output signals are delayed by system clock cycles, 0: output without
-            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
-            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
-            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
-            /// edge
-            DOUT0_MODE: u1,
-            /// the output signals are delayed by system clock cycles, 0: output without
-            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
-            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
-            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
-            /// edge
-            DOUT1_MODE: u1,
-            /// the output signals are delayed by system clock cycles, 0: output without
-            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
-            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
-            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
-            /// edge
-            DOUT2_MODE: u1,
-            /// the output signals are delayed by system clock cycles, 0: output without
-            /// delayed, 1: output with the posedge of clk_apb,2 output with the negedge of
-            /// clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of
-            /// clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low
-            /// edge
-            DOUT3_MODE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0xb4);
-
-        /// address: 0x600030dc
-        /// SPI0 clk_gate register
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Register clock gate enable signal. 1: Enable. 0: Disable.
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xdc);
-
-        /// address: 0x600030e0
-        /// SPI0 module clock select register
-        pub const CORE_CLK_SEL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// When the digital system clock selects PLL clock and the frequency of PLL clock
-            /// is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is
-            /// 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk)
-            /// 160MHz. 3: Not used. When the digital system clock selects PLL clock and the
-            /// frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1
-            /// module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1
-            /// module clock (clk) 160MHz. 3: Not used.
-            SPI01_CLK_SEL: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0xe0);
-
-        /// address: 0x600033fc
-        /// Version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x3fc);
-    };
-
-    /// SPI (Serial Peripheral Interface) Controller
-    pub const SPI1 = struct {
-        pub const base_address = 0x60002000;
-
-        /// address: 0x60002000
-        /// SPI1 memory command register
-        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The current status of SPI1 master FSM.
-            SPI1_MST_ST: u4,
-            /// The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation
-            /// state, 2: send command state, 3: send address state, 4: wait state, 5: read data
-            /// state, 6:write data state, 7: done state, 8: read data end state.
-            MSPI_ST: u4,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// In user mode, it is set to indicate that program/erase operation will be
-            /// triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared
-            /// once the operation done.1: enable 0: disable.
-            FLASH_PE: u1,
-            /// User define command enable. An operation will be triggered when the bit is set.
-            /// The bit will be cleared once the operation done.1: enable 0: disable.
-            USR: u1,
-            /// Drive Flash into high performance mode. The bit will be cleared once the
-            /// operation done.1: enable 0: disable.
-            FLASH_HPM: u1,
-            /// This bit combined with reg_resandres bit releases Flash from the power-down
-            /// state or high performance mode and obtains the devices ID. The bit will be
-            /// cleared once the operation done.1: enable 0: disable.
-            FLASH_RES: u1,
-            /// Drive Flash into power down. An operation will be triggered when the bit is set.
-            /// The bit will be cleared once the operation done.1: enable 0: disable.
-            FLASH_DP: u1,
-            /// Chip erase enable. Chip erase operation will be triggered when the bit is set.
-            /// The bit will be cleared once the operation done.1: enable 0: disable.
-            FLASH_CE: u1,
-            /// Block erase enable(32KB) . Block erase operation will be triggered when the bit
-            /// is set. The bit will be cleared once the operation done.1: enable 0: disable.
-            FLASH_BE: u1,
-            /// Sector erase enable(4KB). Sector erase operation will be triggered when the bit
-            /// is set. The bit will be cleared once the operation done.1: enable 0: disable.
-            FLASH_SE: u1,
-            /// Page program enable(1 byte ~256 bytes data to be programmed). Page program
-            /// operation will be triggered when the bit is set. The bit will be cleared once
-            /// the operation done .1: enable 0: disable.
-            FLASH_PP: u1,
-            /// Write status register enable. Write status operation will be triggered when the
-            /// bit is set. The bit will be cleared once the operation done.1: enable 0:
-            /// disable.
-            FLASH_WRSR: u1,
-            /// Read status register-1. Read status operation will be triggered when the bit is
-            /// set. The bit will be cleared once the operation done.1: enable 0: disable.
-            FLASH_RDSR: u1,
-            /// Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will
-            /// be cleared once the operation done. 1: enable 0: disable.
-            FLASH_RDID: u1,
-            /// Write flash disable. Write disable command will be sent when the bit is set. The
-            /// bit will be cleared once the operation done. 1: enable 0: disable.
-            FLASH_WRDI: u1,
-            /// Write flash enable. Write enable command will be sent when the bit is set. The
-            /// bit will be cleared once the operation done. 1: enable 0: disable.
-            FLASH_WREN: u1,
-            /// Read flash enable. Read flash operation will be triggered when the bit is set.
-            /// The bit will be cleared once the operation done. 1: enable 0: disable.
-            FLASH_READ: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60002004
-        /// SPI1 address register
-        pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In user mode, it is the memory address. other then the bit0-bit23 is the memory
-            /// address, the bit24-bit31 are the byte length of a transfer.
-            USR_ADDR_VALUE: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60002008
-        /// SPI1 control register.
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// In the dummy phase the signal level of spi is output by the spi controller.
-            FDUMMY_OUT: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// Apply 2 signals during command phase 1:enable 0: disable
-            FCMD_DUAL: u1,
-            /// Apply 4 signals during command phase 1:enable 0: disable
-            FCMD_QUAD: u1,
-            reserved6: u1,
-            /// For SPI1, initialize crc32 module before writing encrypted data to flash. Active
-            /// low.
-            FCS_CRC_EN: u1,
-            /// For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
-            TX_CRC_EN: u1,
-            reserved7: u1,
-            /// This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio,
-            /// spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
-            FASTRD_MODE: u1,
-            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
-            FREAD_DUAL: u1,
-            /// The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with
-            /// spi_mem_flash_res bit. 1: enable 0: disable.
-            RESANDRES: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// The bit is used to set MISO line polarity, 1: high 0, low
-            Q_POL: u1,
-            /// The bit is used to set MOSI line polarity, 1: high 0, low
-            D_POL: u1,
-            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
-            FREAD_QUAD: u1,
-            /// Write protect signal output when SPI is idle. 1: output high, 0: output low.
-            WP: u1,
-            /// two bytes data will be written to status register when it is set. 1: enable 0:
-            /// disable.
-            WRSR_2B: u1,
-            /// In the read operations address phase and read-data phase apply 2 signals. 1:
-            /// enable 0: disable.
-            FREAD_DIO: u1,
-            /// In the read operations address phase and read-data phase apply 4 signals. 1:
-            /// enable 0: disable.
-            FREAD_QIO: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000200c
-        /// SPI1 control1 register.
-        pub const CTRL1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
-            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
-            /// inactive 3: SPI clock is alwasy on.
-            CLK_MODE: u2,
-            /// After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] *
-            /// 512) SPI_CLK cycles.
-            CS_HOLD_DLY_RES: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60002010
-        /// SPI1 control2 register.
-        pub const CTRL2 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// The FSM will be reset.
-            SYNC_RESET: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60002014
-        /// SPI1 clock division control register.
-        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In the master mode it must be equal to spi_mem_clkcnt_N.
-            CLKCNT_L: u8,
-            /// In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
-            CLKCNT_H: u8,
-            /// In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is
-            /// system/(spi_mem_clkcnt_N+1)
-            CLKCNT_N: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            /// reserved
-            CLK_EQU_SYSCLK: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60002018
-        /// SPI1 user register.
-        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay
-            /// mode.
-            CK_OUT_EDGE: u1,
-            reserved9: u1,
-            reserved10: u1,
-            /// In the write operations read-data phase apply 2 signals
-            FWRITE_DUAL: u1,
-            /// In the write operations read-data phase apply 4 signals
-            FWRITE_QUAD: u1,
-            /// In the write operations address phase and read-data phase apply 2 signals.
-            FWRITE_DIO: u1,
-            /// In the write operations address phase and read-data phase apply 4 signals.
-            FWRITE_QIO: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            /// read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
-            /// 1: enable 0: disable.
-            USR_MISO_HIGHPART: u1,
-            /// write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15.
-            /// 1: enable 0: disable.
-            USR_MOSI_HIGHPART: u1,
-            /// SPI clock is disable in dummy phase when the bit is enable.
-            USR_DUMMY_IDLE: u1,
-            /// This bit enable the write-data phase of an operation.
-            USR_MOSI: u1,
-            /// This bit enable the read-data phase of an operation.
-            USR_MISO: u1,
-            /// This bit enable the dummy phase of an operation.
-            USR_DUMMY: u1,
-            /// This bit enable the address phase of an operation.
-            USR_ADDR: u1,
-            /// This bit enable the command phase of an operation.
-            USR_COMMAND: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000201c
-        /// SPI1 user1 register.
-        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length in spi_mem_clk cycles of dummy phase. The register value shall be
-            /// (cycle_num-1).
-            USR_DUMMY_CYCLELEN: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            /// The length in bits of address phase. The register value shall be (bit_num-1).
-            USR_ADDR_BITLEN: u6,
-        }), base_address + 0x1c);
-
-        /// address: 0x60002020
-        /// SPI1 user2 register.
-        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of command.
-            USR_COMMAND_VALUE: u16,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// The length in bits of command phase. The register value shall be (bit_num-1)
-            USR_COMMAND_BITLEN: u4,
-        }), base_address + 0x20);
-
-        /// address: 0x60002024
-        /// SPI1 send data bit length control register.
-        pub const MOSI_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length in bits of write-data. The register value shall be (bit_num-1).
-            USR_MOSI_DBITLEN: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60002028
-        /// SPI1 receive data bit length control register.
-        pub const MISO_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length in bits of read-data. The register value shall be (bit_num-1).
-            USR_MISO_DBITLEN: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6000202c
-        /// SPI1 status register.
-        pub const RD_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
-            STATUS: u16,
-            /// Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode
-            /// bit.
-            WB_MODE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60002034
-        /// SPI1 misc register
-        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI
-            /// device, such as flash, external RAM and so on.
-            CS0_DIS: u1,
-            /// SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI
-            /// device, such as flash, external RAM and so on.
-            CS1_DIS: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            /// 1: spi clk line is high when idle 0: spi clk line is low when idle
-            CK_IDLE_EDGE: u1,
-            /// spi cs line keep low when the bit is set.
-            CS_KEEP_ACTIVE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60002038
-        /// SPI1 TX CRC data register.
-        pub const TX_CRC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// For SPI1, the value of crc32.
-            DATA: u32,
-        }), base_address + 0x38);
-
-        /// address: 0x6000203c
-        /// SPI1 bit mode control register.
-        pub const CACHE_FCTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
-            CACHE_USR_ADDR_4BYTE: u1,
-            reserved1: u1,
-            /// For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same
-            /// with spi_mem_fread_dio.
-            FDIN_DUAL: u1,
-            /// For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same
-            /// with spi_mem_fread_dio.
-            FDOUT_DUAL: u1,
-            /// For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_dio.
-            FADDR_DUAL: u1,
-            /// For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same
-            /// with spi_mem_fread_qio.
-            FDIN_QUAD: u1,
-            /// For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same
-            /// with spi_mem_fread_qio.
-            FDOUT_QUAD: u1,
-            /// For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the
-            /// same with spi_mem_fread_qio.
-            FADDR_QUAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60002058
-        /// SPI1 memory data buffer0
-        pub const W0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF0: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6000205c
-        /// SPI1 memory data buffer1
-        pub const W1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF1: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x60002060
-        /// SPI1 memory data buffer2
-        pub const W2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF2: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x60002064
-        /// SPI1 memory data buffer3
-        pub const W3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF3: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x60002068
-        /// SPI1 memory data buffer4
-        pub const W4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF4: u32,
-        }), base_address + 0x68);
-
-        /// address: 0x6000206c
-        /// SPI1 memory data buffer5
-        pub const W5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF5: u32,
-        }), base_address + 0x6c);
-
-        /// address: 0x60002070
-        /// SPI1 memory data buffer6
-        pub const W6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF6: u32,
-        }), base_address + 0x70);
-
-        /// address: 0x60002074
-        /// SPI1 memory data buffer7
-        pub const W7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF7: u32,
-        }), base_address + 0x74);
-
-        /// address: 0x60002078
-        /// SPI1 memory data buffer8
-        pub const W8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF8: u32,
-        }), base_address + 0x78);
-
-        /// address: 0x6000207c
-        /// SPI1 memory data buffer9
-        pub const W9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF9: u32,
-        }), base_address + 0x7c);
-
-        /// address: 0x60002080
-        /// SPI1 memory data buffer10
-        pub const W10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF10: u32,
-        }), base_address + 0x80);
-
-        /// address: 0x60002084
-        /// SPI1 memory data buffer11
-        pub const W11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF11: u32,
-        }), base_address + 0x84);
-
-        /// address: 0x60002088
-        /// SPI1 memory data buffer12
-        pub const W12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF12: u32,
-        }), base_address + 0x88);
-
-        /// address: 0x6000208c
-        /// SPI1 memory data buffer13
-        pub const W13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF13: u32,
-        }), base_address + 0x8c);
-
-        /// address: 0x60002090
-        /// SPI1 memory data buffer14
-        pub const W14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF14: u32,
-        }), base_address + 0x90);
-
-        /// address: 0x60002094
-        /// SPI1 memory data buffer15
-        pub const W15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF15: u32,
-        }), base_address + 0x94);
-
-        /// address: 0x60002098
-        /// SPI1 wait idle control register
-        pub const FLASH_WAITI_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// The dummy phase enable when wait flash idle (RDSR)
-            WAITI_DUMMY: u1,
-            /// The command to wait flash idle(RDSR).
-            WAITI_CMD: u8,
-            /// The dummy cycle length when wait flash idle(RDSR).
-            WAITI_DUMMY_CYCLELEN: u6,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x6000209c
-        /// SPI1 flash suspend control register
-        pub const FLASH_SUS_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// program erase resume bit, program erase suspend operation will be triggered when
-            /// the bit is set. The bit will be cleared once the operation done.1: enable 0:
-            /// disable.
-            FLASH_PER: u1,
-            /// program erase suspend bit, program erase suspend operation will be triggered
-            /// when the bit is set. The bit will be cleared once the operation done.1: enable
-            /// 0: disable.
-            FLASH_PES: u1,
-            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-            /// program erase resume command is sent. 0: SPI1 does not wait after program erase
-            /// resume command is sent.
-            FLASH_PER_WAIT_EN: u1,
-            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after
-            /// program erase suspend command is sent. 0: SPI1 does not wait after program erase
-            /// suspend command is sent.
-            FLASH_PES_WAIT_EN: u1,
-            /// Set this bit to enable PES end triggers PER transfer option. If this bit is 0,
-            /// application should send PER after PES is done.
-            PES_PER_EN: u1,
-            /// Set this bit to enable Auto-suspending function.
-            FLASH_PES_EN: u1,
-            /// The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is
-            /// status_in[15:0](only status_in[7:0] is valid when only one byte of data is read
-            /// out, status_in[15:0] is valid when two bytes of data are read out),
-            /// SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
-            PESR_END_MSK: u16,
-            /// 1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte
-            /// when check flash SUS/SUS1/SUS2 status bit
-            RD_SUS_2B: u1,
-            /// 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status
-            /// of flash. 0: Only need to check WIP is 0.
-            PER_END_EN: u1,
-            /// 1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend
-            /// status of flash. 0: Only need to check WIP is 0.
-            PES_END_EN: u1,
-            /// When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times,
-            /// it will be treated as check pass.
-            SUS_TIMEOUT_CNT: u7,
-        }), base_address + 0x9c);
-
-        /// address: 0x600020a0
-        /// SPI1 flash suspend command register
-        pub const FLASH_SUS_CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Program/Erase resume command.
-            FLASH_PER_COMMAND: u8,
-            /// Program/Erase suspend command.
-            FLASH_PES_COMMAND: u8,
-            /// Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when
-            /// SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of
-            /// flash.
-            WAIT_PESR_COMMAND: u16,
-        }), base_address + 0xa0);
-
-        /// address: 0x600020a4
-        /// SPI1 flash suspend status register
-        pub const SUS_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The status of flash suspend, only used in SPI1.
-            FLASH_SUS: u1,
-            /// 1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0:
-            /// SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
-            WAIT_PESR_CMD_2B: u1,
-            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM
-            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
-            /// cycles after HPM command is sent.
-            FLASH_HPM_DLY_128: u1,
-            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES
-            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
-            /// cycles after RES command is sent.
-            FLASH_RES_DLY_128: u1,
-            /// 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP
-            /// command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK
-            /// cycles after DP command is sent.
-            FLASH_DP_DLY_128: u1,
-            /// Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits
-            /// (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent.
-            /// 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER
-            /// command is sent.
-            FLASH_PER_DLY_128: u1,
-            /// Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits
-            /// (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent.
-            /// 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES
-            /// command is sent.
-            FLASH_PES_DLY_128: u1,
-            /// 1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
-            SPI0_LOCK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0xa4);
-
-        /// address: 0x600020a8
-        /// SPI1 timing control register
-        pub const TIMING_CALI = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// The bit is used to enable timing auto-calibration for all reading operations.
-            TIMING_CALI: u1,
-            /// add extra dummy spi clock cycle length for spi clock calibration.
-            EXTRA_DUMMY_CYCLELEN: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xa8);
-
-        /// address: 0x600020c0
-        /// SPI1 interrupt enable register
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The enable bit for SPI_MEM_PER_END_INT interrupt.
-            PER_END_INT_ENA: u1,
-            /// The enable bit for SPI_MEM_PES_END_INT interrupt.
-            PES_END_INT_ENA: u1,
-            /// The enable bit for SPI_MEM_WPE_END_INT interrupt.
-            WPE_END_INT_ENA: u1,
-            /// The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
-            SLV_ST_END_INT_ENA: u1,
-            /// The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
-            MST_ST_END_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xc0);
-
-        /// address: 0x600020c4
-        /// SPI1 interrupt clear register
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The clear bit for SPI_MEM_PER_END_INT interrupt.
-            PER_END_INT_CLR: u1,
-            /// The clear bit for SPI_MEM_PES_END_INT interrupt.
-            PES_END_INT_CLR: u1,
-            /// The clear bit for SPI_MEM_WPE_END_INT interrupt.
-            WPE_END_INT_CLR: u1,
-            /// The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
-            SLV_ST_END_INT_CLR: u1,
-            /// The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
-            MST_ST_END_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xc4);
-
-        /// address: 0x600020c8
-        /// SPI1 interrupt raw register
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume
-            /// command (0x7A) is sent and flash is resumed. 0: Others.
-            PER_END_INT_RAW: u1,
-            /// The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend
-            /// command (0x75) is sent and flash is suspended. 0: Others.
-            PES_END_INT_RAW: u1,
-            /// The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when
-            /// WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
-            WPE_END_INT_RAW: u1,
-            /// The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st
-            /// is changed from non idle state to idle state. It means that SPI_CS raises high.
-            /// 0: Others
-            SLV_ST_END_INT_RAW: u1,
-            /// The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st
-            /// is changed from non idle state to idle state. 0: Others.
-            MST_ST_END_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xc8);
-
-        /// address: 0x600020cc
-        /// SPI1 interrupt status register
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The status bit for SPI_MEM_PER_END_INT interrupt.
-            PER_END_INT_ST: u1,
-            /// The status bit for SPI_MEM_PES_END_INT interrupt.
-            PES_END_INT_ST: u1,
-            /// The status bit for SPI_MEM_WPE_END_INT interrupt.
-            WPE_END_INT_ST: u1,
-            /// The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
-            SLV_ST_END_INT_ST: u1,
-            /// The status bit for SPI_MEM_MST_ST_END_INT interrupt.
-            MST_ST_END_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0xcc);
-
-        /// address: 0x600020dc
-        /// SPI1 clk_gate register
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Register clock gate enable signal. 1: Enable. 0: Disable.
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xdc);
-
-        /// address: 0x600023fc
-        /// Version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0x3fc);
-    };
-
-    /// SPI (Serial Peripheral Interface) Controller
-    pub const SPI2 = struct {
-        pub const base_address = 0x60024000;
-
-        /// address: 0x60024000
-        /// Command control register
-        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
-            CONF_BITLEN: u18,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            /// Set this bit to synchronize SPI registers from APB clock domain into SPI module
-            /// clock domain, which is only used in SPI master mode.
-            UPDATE: u1,
-            /// User define command enable. An operation will be triggered when the bit is set.
-            /// The bit will be cleared once the operation done.1: enable 0: disable. Can not be
-            /// changed by CONF_buf.
-            USR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60024004
-        /// Address value register
-        pub const ADDR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Address to slave. Can be configured in CONF state.
-            USR_ADDR_VALUE: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60024008
-        /// SPI control register
-        pub const CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// In the dummy phase the signal level of spi is output by the spi controller. Can
-            /// be configured in CONF state.
-            DUMMY_OUT: u1,
-            reserved3: u1,
-            /// Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-            /// state.
-            FADDR_DUAL: u1,
-            /// Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF
-            /// state.
-            FADDR_QUAD: u1,
-            reserved4: u1,
-            /// Apply 2 signals during command phase 1:enable 0: disable. Can be configured in
-            /// CONF state.
-            FCMD_DUAL: u1,
-            /// Apply 4 signals during command phase 1:enable 0: disable. Can be configured in
-            /// CONF state.
-            FCMD_QUAD: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
-            /// Can be configured in CONF state.
-            FREAD_DUAL: u1,
-            /// In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
-            /// Can be configured in CONF state.
-            FREAD_QUAD: u1,
-            reserved9: u1,
-            reserved10: u1,
-            /// The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in
-            /// CONF state.
-            Q_POL: u1,
-            /// The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in
-            /// CONF state.
-            D_POL: u1,
-            /// SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be
-            /// configured in CONF state.
-            HOLD_POL: u1,
-            /// Write protect signal output when SPI is idle. 1: output high, 0: output low. Can
-            /// be configured in CONF state.
-            WP_POL: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF
-            /// state.
-            RD_BIT_ORDER: u1,
-            /// In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be
-            /// configured in CONF state.
-            WR_BIT_ORDER: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6002400c
-        /// SPI clock control register
-        pub const CLOCK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must
-            /// be 0. Can be configured in CONF state.
-            CLKCNT_L: u6,
-            /// In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it
-            /// must be 0. Can be configured in CONF state.
-            CLKCNT_H: u6,
-            /// In the master mode it is the divider of spi_clk. So spi_clk frequency is
-            /// system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
-            CLKCNT_N: u6,
-            /// In the master mode it is pre-divider of spi_clk. Can be configured in CONF
-            /// state.
-            CLKDIV_PRE: u4,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from
-            /// system clock. Can be configured in CONF state.
-            CLK_EQU_SYSCLK: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60024010
-        /// SPI USER control register
-        pub const USER = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set the bit to enable full duplex communication. 1: enable 0: disable. Can be
-            /// configured in CONF state.
-            DOUTDIN: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// Both for master mode and slave mode. 1: spi controller is in QPI mode. 0:
-            /// others. Can be configured in CONF state.
-            QPI_MODE: u1,
-            reserved2: u1,
-            /// In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck
-            /// = spi_ck_i. 1:tsck = !spi_ck_i.
-            TSCK_I_EDGE: u1,
-            /// spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be
-            /// configured in CONF state.
-            CS_HOLD: u1,
-            /// spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be
-            /// configured in CONF state.
-            CS_SETUP: u1,
-            /// In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck
-            /// = !spi_ck_i. 1:rsck = spi_ck_i.
-            RSCK_I_EDGE: u1,
-            /// the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode.
-            /// Can be configured in CONF state.
-            CK_OUT_EDGE: u1,
-            reserved3: u1,
-            reserved4: u1,
-            /// In the write operations read-data phase apply 2 signals. Can be configured in
-            /// CONF state.
-            FWRITE_DUAL: u1,
-            /// In the write operations read-data phase apply 4 signals. Can be configured in
-            /// CONF state.
-            FWRITE_QUAD: u1,
-            reserved5: u1,
-            /// 1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans
-            /// will continue. 0: The seg-trans will end after the current SPI seg-trans or this
-            /// is not seg-trans mode. Can be configured in CONF state.
-            USR_CONF_NXT: u1,
-            reserved6: u1,
-            /// Set the bit to enable 3-line half duplex communication mosi and miso signals
-            /// share the same pin. 1: enable 0: disable. Can be configured in CONF state.
-            SIO: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            /// read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable
-            /// 0: disable. Can be configured in CONF state.
-            USR_MISO_HIGHPART: u1,
-            /// write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1:
-            /// enable 0: disable. Can be configured in CONF state.
-            USR_MOSI_HIGHPART: u1,
-            /// spi clock is disable in dummy phase when the bit is enable. Can be configured in
-            /// CONF state.
-            USR_DUMMY_IDLE: u1,
-            /// This bit enable the write-data phase of an operation. Can be configured in CONF
-            /// state.
-            USR_MOSI: u1,
-            /// This bit enable the read-data phase of an operation. Can be configured in CONF
-            /// state.
-            USR_MISO: u1,
-            /// This bit enable the dummy phase of an operation. Can be configured in CONF
-            /// state.
-            USR_DUMMY: u1,
-            /// This bit enable the address phase of an operation. Can be configured in CONF
-            /// state.
-            USR_ADDR: u1,
-            /// This bit enable the command phase of an operation. Can be configured in CONF
-            /// state.
-            USR_COMMAND: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60024014
-        /// SPI USER control register 1
-        pub const USER1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The length in spi_clk cycles of dummy phase. The register value shall be
-            /// (cycle_num-1). Can be configured in CONF state.
-            USR_DUMMY_CYCLELEN: u8,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// 1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master
-            /// FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid
-            /// in GP-SPI master FD/HD-mode.
-            MST_WFULL_ERR_END_EN: u1,
-            /// (cycles+1) of prepare phase by spi clock this bits are combined with
-            /// spi_cs_setup bit. Can be configured in CONF state.
-            CS_SETUP_TIME: u5,
-            /// delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit.
-            /// Can be configured in CONF state.
-            CS_HOLD_TIME: u5,
-            /// The length in bits of address phase. The register value shall be (bit_num-1).
-            /// Can be configured in CONF state.
-            USR_ADDR_BITLEN: u5,
-        }), base_address + 0x14);
-
-        /// address: 0x60024018
-        /// SPI USER control register 2
-        pub const USER2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of command. Can be configured in CONF state.
-            USR_COMMAND_VALUE: u16,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            /// 1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI
-            /// master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty
-            /// error is valid in GP-SPI master FD/HD-mode.
-            MST_REMPTY_ERR_END_EN: u1,
-            /// The length in bits of command phase. The register value shall be (bit_num-1).
-            /// Can be configured in CONF state.
-            USR_COMMAND_BITLEN: u4,
-        }), base_address + 0x18);
-
-        /// address: 0x6002401c
-        /// SPI data bit length control register
-        pub const MS_DLEN = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The value of these bits is the configured SPI transmission data bit length in
-            /// master mode DMA controlled transfer or CPU controlled transfer. The value is
-            /// also the configured bit length in slave mode DMA RX controlled transfer. The
-            /// register value shall be (bit_num-1). Can be configured in CONF state.
-            MS_DATA_BITLEN: u18,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60024020
-        /// SPI misc register
-        pub const MISC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be
-            /// configured in CONF state.
-            CS0_DIS: u1,
-            /// SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be
-            /// configured in CONF state.
-            CS1_DIS: u1,
-            /// SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be
-            /// configured in CONF state.
-            CS2_DIS: u1,
-            /// SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be
-            /// configured in CONF state.
-            CS3_DIS: u1,
-            /// SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be
-            /// configured in CONF state.
-            CS4_DIS: u1,
-            /// SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be
-            /// configured in CONF state.
-            CS5_DIS: u1,
-            /// 1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.
-            CK_DIS: u1,
-            /// In the master mode the bits are the polarity of spi cs line, the value is
-            /// equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
-            MASTER_CS_POL: u6,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            /// spi slave input cs polarity select. 1: inv 0: not change. Can be configured in
-            /// CONF state.
-            SLAVE_CS_POL: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// 1: spi clk line is high when idle 0: spi clk line is low when idle. Can be
-            /// configured in CONF state.
-            CK_IDLE_EDGE: u1,
-            /// spi cs line keep low when the bit is set. Can be configured in CONF state.
-            CS_KEEP_ACTIVE: u1,
-            /// 1: spi quad input swap enable 0: spi quad input swap disable. Can be configured
-            /// in CONF state.
-            QUAD_DIN_PIN_SWAP: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60024024
-        /// SPI input delay mode configuration
-        pub const DIN_MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the input signals are delayed by SPI module clock cycles, 0: input without
-            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
-            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-            DIN0_MODE: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: input without
-            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
-            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-            DIN1_MODE: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: input without
-            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
-            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-            DIN2_MODE: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: input without
-            /// delayed, 1: input with the posedge of clk_apb,2 input with the negedge of
-            /// clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-            DIN3_MODE: u2,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// 1:enable hclk in SPI input timing module. 0: disable it. Can be configured in
-            /// CONF state.
-            TIMING_HCLK_ACTIVE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60024028
-        /// SPI input delay number configuration
-        pub const DIN_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
-            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
-            DIN0_NUM: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
-            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
-            DIN1_NUM: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
-            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
-            DIN2_NUM: u2,
-            /// the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle,
-            /// 1: delayed by 2 cycles,... Can be configured in CONF state.
-            DIN3_NUM: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6002402c
-        /// SPI output delay mode configuration
-        pub const DOUT_MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The output signal 0 is delayed by the SPI module clock, 0: output without
-            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
-            /// be configured in CONF state.
-            DOUT0_MODE: u1,
-            /// The output signal 1 is delayed by the SPI module clock, 0: output without
-            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
-            /// be configured in CONF state.
-            DOUT1_MODE: u1,
-            /// The output signal 2 is delayed by the SPI module clock, 0: output without
-            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
-            /// be configured in CONF state.
-            DOUT2_MODE: u1,
-            /// The output signal 3 is delayed by the SPI module clock, 0: output without
-            /// delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can
-            /// be configured in CONF state.
-            DOUT3_MODE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60024030
-        /// SPI DMA control register
-        pub const DMA_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            /// Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
-            DMA_SLV_SEG_TRANS_EN: u1,
-            /// 1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0:
-            /// spi_dma_infifo_full_vld is cleared by spi_trans_done.
-            SLV_RX_SEG_TRANS_CLR_EN: u1,
-            /// 1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0:
-            /// spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
-            SLV_TX_SEG_TRANS_CLR_EN: u1,
-            /// 1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal
-            /// to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0:
-            /// spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or
-            /// spi_dma_seg_trans_done in seg-trans.
-            RX_EOF_EN: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            /// Set this bit to enable SPI DMA controlled receive data mode.
-            DMA_RX_ENA: u1,
-            /// Set this bit to enable SPI DMA controlled send data mode.
-            DMA_TX_ENA: u1,
-            /// Set this bit to reset RX AFIFO, which is used to receive data in SPI master and
-            /// slave mode transfer.
-            RX_AFIFO_RST: u1,
-            /// Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU
-            /// controlled mode transfer and master mode transfer.
-            BUF_AFIFO_RST: u1,
-            /// Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave
-            /// DMA controlled mode transfer.
-            DMA_AFIFO_RST: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60024034
-        /// SPI DMA interrupt enable register
-        pub const DMA_INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-            DMA_INFIFO_FULL_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-            DMA_OUTFIFO_EMPTY_ERR_INT_ENA: u1,
-            /// The enable bit for SPI slave Ex_QPI interrupt.
-            SLV_EX_QPI_INT_ENA: u1,
-            /// The enable bit for SPI slave En_QPI interrupt.
-            SLV_EN_QPI_INT_ENA: u1,
-            /// The enable bit for SPI slave CMD7 interrupt.
-            SLV_CMD7_INT_ENA: u1,
-            /// The enable bit for SPI slave CMD8 interrupt.
-            SLV_CMD8_INT_ENA: u1,
-            /// The enable bit for SPI slave CMD9 interrupt.
-            SLV_CMD9_INT_ENA: u1,
-            /// The enable bit for SPI slave CMDA interrupt.
-            SLV_CMDA_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-            SLV_RD_DMA_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-            SLV_WR_DMA_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-            SLV_RD_BUF_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-            SLV_WR_BUF_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_TRANS_DONE_INT interrupt.
-            TRANS_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-            DMA_SEG_TRANS_DONE_INT_ENA: u1,
-            /// The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-            SEG_MAGIC_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-            SLV_BUF_ADDR_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
-            SLV_CMD_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-            MST_RX_AFIFO_WFULL_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-            MST_TX_AFIFO_REMPTY_ERR_INT_ENA: u1,
-            /// The enable bit for SPI_APP2_INT interrupt.
-            APP2_INT_ENA: u1,
-            /// The enable bit for SPI_APP1_INT interrupt.
-            APP1_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60024038
-        /// SPI DMA interrupt clear register
-        pub const DMA_INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-            DMA_INFIFO_FULL_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-            DMA_OUTFIFO_EMPTY_ERR_INT_CLR: u1,
-            /// The clear bit for SPI slave Ex_QPI interrupt.
-            SLV_EX_QPI_INT_CLR: u1,
-            /// The clear bit for SPI slave En_QPI interrupt.
-            SLV_EN_QPI_INT_CLR: u1,
-            /// The clear bit for SPI slave CMD7 interrupt.
-            SLV_CMD7_INT_CLR: u1,
-            /// The clear bit for SPI slave CMD8 interrupt.
-            SLV_CMD8_INT_CLR: u1,
-            /// The clear bit for SPI slave CMD9 interrupt.
-            SLV_CMD9_INT_CLR: u1,
-            /// The clear bit for SPI slave CMDA interrupt.
-            SLV_CMDA_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-            SLV_RD_DMA_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-            SLV_WR_DMA_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-            SLV_RD_BUF_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-            SLV_WR_BUF_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_TRANS_DONE_INT interrupt.
-            TRANS_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-            DMA_SEG_TRANS_DONE_INT_CLR: u1,
-            /// The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-            SEG_MAGIC_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-            SLV_BUF_ADDR_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
-            SLV_CMD_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-            MST_RX_AFIFO_WFULL_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-            MST_TX_AFIFO_REMPTY_ERR_INT_CLR: u1,
-            /// The clear bit for SPI_APP2_INT interrupt.
-            APP2_INT_CLR: u1,
-            /// The clear bit for SPI_APP1_INT interrupt.
-            APP1_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6002403c
-        /// SPI DMA interrupt raw register
-        pub const DMA_INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: The current data rate of DMA Rx is smaller than that of SPI, which will lose
-            /// the receive data. 0: Others.
-            DMA_INFIFO_FULL_ERR_INT_RAW: u1,
-            /// 1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in
-            /// master mode and send out all 0 in slave mode. 0: Others.
-            DMA_OUTFIFO_EMPTY_ERR_INT_RAW: u1,
-            /// The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI
-            /// transmission is ended. 0: Others.
-            SLV_EX_QPI_INT_RAW: u1,
-            /// The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI
-            /// transmission is ended. 0: Others.
-            SLV_EN_QPI_INT_RAW: u1,
-            /// The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is
-            /// ended. 0: Others.
-            SLV_CMD7_INT_RAW: u1,
-            /// The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is
-            /// ended. 0: Others.
-            SLV_CMD8_INT_RAW: u1,
-            /// The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is
-            /// ended. 0: Others.
-            SLV_CMD9_INT_RAW: u1,
-            /// The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is
-            /// ended. 0: Others.
-            SLV_CMDA_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA
-            /// transmission is ended. 0: Others.
-            SLV_RD_DMA_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA
-            /// transmission is ended. 0: Others.
-            SLV_WR_DMA_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF
-            /// transmission is ended. 0: Others.
-            SLV_RD_BUF_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF
-            /// transmission is ended. 0: Others.
-            SLV_WR_BUF_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is
-            /// ended. 0: others.
-            TRANS_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA
-            /// full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends.
-            /// And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans
-            /// is not ended or not occurred.
-            DMA_SEG_TRANS_DONE_INT_RAW: u1,
-            /// The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF
-            /// buffer is error in the DMA seg-conf-trans. 0: others.
-            SEG_MAGIC_ERR_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data
-            /// address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF
-            /// transmission is bigger than 63. 0: Others.
-            SLV_BUF_ADDR_ERR_INT_RAW: u1,
-            /// The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the
-            /// current SPI slave HD mode transmission is not supported. 0: Others.
-            SLV_CMD_ERR_INT_RAW: u1,
-            /// The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO
-            /// write-full error when SPI inputs data in master mode. 0: Others.
-            MST_RX_AFIFO_WFULL_ERR_INT_RAW: u1,
-            /// The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF
-            /// AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
-            MST_TX_AFIFO_REMPTY_ERR_INT_RAW: u1,
-            /// The raw bit for SPI_APP2_INT interrupt. The value is only controlled by
-            /// application.
-            APP2_INT_RAW: u1,
-            /// The raw bit for SPI_APP1_INT interrupt. The value is only controlled by
-            /// application.
-            APP1_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60024040
-        /// SPI DMA interrupt status register
-        pub const DMA_INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-            DMA_INFIFO_FULL_ERR_INT_ST: u1,
-            /// The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-            DMA_OUTFIFO_EMPTY_ERR_INT_ST: u1,
-            /// The status bit for SPI slave Ex_QPI interrupt.
-            SLV_EX_QPI_INT_ST: u1,
-            /// The status bit for SPI slave En_QPI interrupt.
-            SLV_EN_QPI_INT_ST: u1,
-            /// The status bit for SPI slave CMD7 interrupt.
-            SLV_CMD7_INT_ST: u1,
-            /// The status bit for SPI slave CMD8 interrupt.
-            SLV_CMD8_INT_ST: u1,
-            /// The status bit for SPI slave CMD9 interrupt.
-            SLV_CMD9_INT_ST: u1,
-            /// The status bit for SPI slave CMDA interrupt.
-            SLV_CMDA_INT_ST: u1,
-            /// The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-            SLV_RD_DMA_DONE_INT_ST: u1,
-            /// The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-            SLV_WR_DMA_DONE_INT_ST: u1,
-            /// The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-            SLV_RD_BUF_DONE_INT_ST: u1,
-            /// The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-            SLV_WR_BUF_DONE_INT_ST: u1,
-            /// The status bit for SPI_TRANS_DONE_INT interrupt.
-            TRANS_DONE_INT_ST: u1,
-            /// The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-            DMA_SEG_TRANS_DONE_INT_ST: u1,
-            /// The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-            SEG_MAGIC_ERR_INT_ST: u1,
-            /// The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-            SLV_BUF_ADDR_ERR_INT_ST: u1,
-            /// The status bit for SPI_SLV_CMD_ERR_INT interrupt.
-            SLV_CMD_ERR_INT_ST: u1,
-            /// The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-            MST_RX_AFIFO_WFULL_ERR_INT_ST: u1,
-            /// The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-            MST_TX_AFIFO_REMPTY_ERR_INT_ST: u1,
-            /// The status bit for SPI_APP2_INT interrupt.
-            APP2_INT_ST: u1,
-            /// The status bit for SPI_APP1_INT interrupt.
-            APP1_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60024098
-        /// SPI CPU-controlled buffer0
-        pub const W0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF0: u32,
-        }), base_address + 0x98);
-
-        /// address: 0x6002409c
-        /// SPI CPU-controlled buffer1
-        pub const W1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF1: u32,
-        }), base_address + 0x9c);
-
-        /// address: 0x600240a0
-        /// SPI CPU-controlled buffer2
-        pub const W2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF2: u32,
-        }), base_address + 0xa0);
-
-        /// address: 0x600240a4
-        /// SPI CPU-controlled buffer3
-        pub const W3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF3: u32,
-        }), base_address + 0xa4);
-
-        /// address: 0x600240a8
-        /// SPI CPU-controlled buffer4
-        pub const W4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF4: u32,
-        }), base_address + 0xa8);
-
-        /// address: 0x600240ac
-        /// SPI CPU-controlled buffer5
-        pub const W5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF5: u32,
-        }), base_address + 0xac);
-
-        /// address: 0x600240b0
-        /// SPI CPU-controlled buffer6
-        pub const W6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF6: u32,
-        }), base_address + 0xb0);
-
-        /// address: 0x600240b4
-        /// SPI CPU-controlled buffer7
-        pub const W7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF7: u32,
-        }), base_address + 0xb4);
-
-        /// address: 0x600240b8
-        /// SPI CPU-controlled buffer8
-        pub const W8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF8: u32,
-        }), base_address + 0xb8);
-
-        /// address: 0x600240bc
-        /// SPI CPU-controlled buffer9
-        pub const W9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF9: u32,
-        }), base_address + 0xbc);
-
-        /// address: 0x600240c0
-        /// SPI CPU-controlled buffer10
-        pub const W10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF10: u32,
-        }), base_address + 0xc0);
-
-        /// address: 0x600240c4
-        /// SPI CPU-controlled buffer11
-        pub const W11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF11: u32,
-        }), base_address + 0xc4);
-
-        /// address: 0x600240c8
-        /// SPI CPU-controlled buffer12
-        pub const W12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF12: u32,
-        }), base_address + 0xc8);
-
-        /// address: 0x600240cc
-        /// SPI CPU-controlled buffer13
-        pub const W13 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF13: u32,
-        }), base_address + 0xcc);
-
-        /// address: 0x600240d0
-        /// SPI CPU-controlled buffer14
-        pub const W14 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF14: u32,
-        }), base_address + 0xd0);
-
-        /// address: 0x600240d4
-        /// SPI CPU-controlled buffer15
-        pub const W15 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// data buffer
-            BUF15: u32,
-        }), base_address + 0xd4);
-
-        /// address: 0x600240e0
-        /// SPI slave control register
-        pub const SLAVE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is
-            /// delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS
-            /// inactive 3: SPI clock is alwasy on. Can be configured in CONF state.
-            CLK_MODE: u2,
-            /// {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].
-            /// 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].
-            CLK_MODE_13: u1,
-            /// It saves half a cycle when tsck is the same as rsck. 1: output data at rsck
-            /// posedge 0: output data at tsck posedge
-            RSCK_DATA_OUT: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length
-            /// in DMA controlled mode(Rd_DMA). 0: others
-            SLV_RDDMA_BITLEN_EN: u1,
-            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data
-            /// length in DMA controlled mode(Wr_DMA). 0: others
-            SLV_WRDMA_BITLEN_EN: u1,
-            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length
-            /// in CPU controlled mode(Rd_BUF). 0: others
-            SLV_RDBUF_BITLEN_EN: u1,
-            /// 1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data
-            /// length in CPU controlled mode(Wr_BUF). 0: others
-            SLV_WRBUF_BITLEN_EN: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            /// The magic value of BM table in master DMA seg-trans.
-            DMA_SEG_MAGIC_VALUE: u4,
-            /// Set SPI work mode. 1: slave mode 0: master mode.
-            MODE: u1,
-            /// Software reset enable, reset the spi clock line cs line and data lines. Can be
-            /// configured in CONF state.
-            SOFT_RESET: u1,
-            /// 1: Enable the DMA CONF phase of current seg-trans operation, which means
-            /// seg-trans will start. 0: This is not seg-trans mode.
-            USR_CONF: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0xe0);
-
-        /// address: 0x600240e4
-        /// SPI slave control register 1
-        pub const SLAVE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The transferred data bit length in SPI slave FD and HD mode.
-            SLV_DATA_BITLEN: u18,
-            /// In the slave mode it is the value of command.
-            SLV_LAST_COMMAND: u8,
-            /// In the slave mode it is the value of address.
-            SLV_LAST_ADDR: u6,
-        }), base_address + 0xe4);
-
-        /// address: 0x600240e8
-        /// SPI module clock and register clock control
-        pub const CLK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to enable clk gate
-            CLK_EN: u1,
-            /// Set this bit to power on the SPI module clock.
-            MST_CLK_ACTIVE: u1,
-            /// This bit is used to select SPI module clock source in master mode. 1:
-            /// PLL_CLK_80M. 0: XTAL CLK.
-            MST_CLK_SEL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0xe8);
-
-        /// address: 0x600240f0
-        /// Version control
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xf0);
-    };
-
-    /// System
-    pub const SYSTEM = struct {
-        pub const base_address = 0x600c0000;
-
-        /// address: 0x600c0000
-        /// cpu_peripheral clock gating register
-        pub const CPU_PERI_CLK_EN = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// reg_clk_en_assist_debug
-            CLK_EN_ASSIST_DEBUG: u1,
-            /// reg_clk_en_dedicated_gpio
-            CLK_EN_DEDICATED_GPIO: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x600c0004
-        /// cpu_peripheral reset register
-        pub const CPU_PERI_RST_EN = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// reg_rst_en_assist_debug
-            RST_EN_ASSIST_DEBUG: u1,
-            /// reg_rst_en_dedicated_gpio
-            RST_EN_DEDICATED_GPIO: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x600c0008
-        /// cpu clock config register
-        pub const CPU_PER_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_cpuperiod_sel
-            CPUPERIOD_SEL: u2,
-            /// reg_pll_freq_sel
-            PLL_FREQ_SEL: u1,
-            /// reg_cpu_wait_mode_force_on
-            CPU_WAIT_MODE_FORCE_ON: u1,
-            /// reg_cpu_waiti_delay_num
-            CPU_WAITI_DELAY_NUM: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x600c000c
-        /// memory power down mask register
-        pub const MEM_PD_MASK = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_lslp_mem_pd_mask
-            LSLP_MEM_PD_MASK: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x600c0010
-        /// peripheral clock gating register
-        pub const PERIP_CLK_EN0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timers_clk_en
-            TIMERS_CLK_EN: u1,
-            /// reg_spi01_clk_en
-            SPI01_CLK_EN: u1,
-            /// reg_uart_clk_en
-            UART_CLK_EN: u1,
-            /// reg_wdg_clk_en
-            WDG_CLK_EN: u1,
-            /// reg_i2s0_clk_en
-            I2S0_CLK_EN: u1,
-            /// reg_uart1_clk_en
-            UART1_CLK_EN: u1,
-            /// reg_spi2_clk_en
-            SPI2_CLK_EN: u1,
-            /// reg_ext0_clk_en
-            I2C_EXT0_CLK_EN: u1,
-            /// reg_uhci0_clk_en
-            UHCI0_CLK_EN: u1,
-            /// reg_rmt_clk_en
-            RMT_CLK_EN: u1,
-            /// reg_pcnt_clk_en
-            PCNT_CLK_EN: u1,
-            /// reg_ledc_clk_en
-            LEDC_CLK_EN: u1,
-            /// reg_uhci1_clk_en
-            UHCI1_CLK_EN: u1,
-            /// reg_timergroup_clk_en
-            TIMERGROUP_CLK_EN: u1,
-            /// reg_efuse_clk_en
-            EFUSE_CLK_EN: u1,
-            /// reg_timergroup1_clk_en
-            TIMERGROUP1_CLK_EN: u1,
-            /// reg_spi3_clk_en
-            SPI3_CLK_EN: u1,
-            /// reg_pwm0_clk_en
-            PWM0_CLK_EN: u1,
-            /// reg_ext1_clk_en
-            EXT1_CLK_EN: u1,
-            /// reg_can_clk_en
-            CAN_CLK_EN: u1,
-            /// reg_pwm1_clk_en
-            PWM1_CLK_EN: u1,
-            /// reg_i2s1_clk_en
-            I2S1_CLK_EN: u1,
-            /// reg_spi2_dma_clk_en
-            SPI2_DMA_CLK_EN: u1,
-            /// reg_usb_device_clk_en
-            USB_DEVICE_CLK_EN: u1,
-            /// reg_uart_mem_clk_en
-            UART_MEM_CLK_EN: u1,
-            /// reg_pwm2_clk_en
-            PWM2_CLK_EN: u1,
-            /// reg_pwm3_clk_en
-            PWM3_CLK_EN: u1,
-            /// reg_spi3_dma_clk_en
-            SPI3_DMA_CLK_EN: u1,
-            /// reg_apb_saradc_clk_en
-            APB_SARADC_CLK_EN: u1,
-            /// reg_systimer_clk_en
-            SYSTIMER_CLK_EN: u1,
-            /// reg_adc2_arb_clk_en
-            ADC2_ARB_CLK_EN: u1,
-            /// reg_spi4_clk_en
-            SPI4_CLK_EN: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x600c0014
-        /// peripheral clock gating register
-        pub const PERIP_CLK_EN1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// reg_crypto_aes_clk_en
-            CRYPTO_AES_CLK_EN: u1,
-            /// reg_crypto_sha_clk_en
-            CRYPTO_SHA_CLK_EN: u1,
-            /// reg_crypto_rsa_clk_en
-            CRYPTO_RSA_CLK_EN: u1,
-            /// reg_crypto_ds_clk_en
-            CRYPTO_DS_CLK_EN: u1,
-            /// reg_crypto_hmac_clk_en
-            CRYPTO_HMAC_CLK_EN: u1,
-            /// reg_dma_clk_en
-            DMA_CLK_EN: u1,
-            /// reg_sdio_host_clk_en
-            SDIO_HOST_CLK_EN: u1,
-            /// reg_lcd_cam_clk_en
-            LCD_CAM_CLK_EN: u1,
-            /// reg_uart2_clk_en
-            UART2_CLK_EN: u1,
-            /// reg_tsens_clk_en
-            TSENS_CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x600c0018
-        /// reserved
-        pub const PERIP_RST_EN0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_timers_rst
-            TIMERS_RST: u1,
-            /// reg_spi01_rst
-            SPI01_RST: u1,
-            /// reg_uart_rst
-            UART_RST: u1,
-            /// reg_wdg_rst
-            WDG_RST: u1,
-            /// reg_i2s0_rst
-            I2S0_RST: u1,
-            /// reg_uart1_rst
-            UART1_RST: u1,
-            /// reg_spi2_rst
-            SPI2_RST: u1,
-            /// reg_ext0_rst
-            I2C_EXT0_RST: u1,
-            /// reg_uhci0_rst
-            UHCI0_RST: u1,
-            /// reg_rmt_rst
-            RMT_RST: u1,
-            /// reg_pcnt_rst
-            PCNT_RST: u1,
-            /// reg_ledc_rst
-            LEDC_RST: u1,
-            /// reg_uhci1_rst
-            UHCI1_RST: u1,
-            /// reg_timergroup_rst
-            TIMERGROUP_RST: u1,
-            /// reg_efuse_rst
-            EFUSE_RST: u1,
-            /// reg_timergroup1_rst
-            TIMERGROUP1_RST: u1,
-            /// reg_spi3_rst
-            SPI3_RST: u1,
-            /// reg_pwm0_rst
-            PWM0_RST: u1,
-            /// reg_ext1_rst
-            EXT1_RST: u1,
-            /// reg_can_rst
-            CAN_RST: u1,
-            /// reg_pwm1_rst
-            PWM1_RST: u1,
-            /// reg_i2s1_rst
-            I2S1_RST: u1,
-            /// reg_spi2_dma_rst
-            SPI2_DMA_RST: u1,
-            /// reg_usb_device_rst
-            USB_DEVICE_RST: u1,
-            /// reg_uart_mem_rst
-            UART_MEM_RST: u1,
-            /// reg_pwm2_rst
-            PWM2_RST: u1,
-            /// reg_pwm3_rst
-            PWM3_RST: u1,
-            /// reg_spi3_dma_rst
-            SPI3_DMA_RST: u1,
-            /// reg_apb_saradc_rst
-            APB_SARADC_RST: u1,
-            /// reg_systimer_rst
-            SYSTIMER_RST: u1,
-            /// reg_adc2_arb_rst
-            ADC2_ARB_RST: u1,
-            /// reg_spi4_rst
-            SPI4_RST: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x600c001c
-        /// peripheral reset register
-        pub const PERIP_RST_EN1 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// reg_crypto_aes_rst
-            CRYPTO_AES_RST: u1,
-            /// reg_crypto_sha_rst
-            CRYPTO_SHA_RST: u1,
-            /// reg_crypto_rsa_rst
-            CRYPTO_RSA_RST: u1,
-            /// reg_crypto_ds_rst
-            CRYPTO_DS_RST: u1,
-            /// reg_crypto_hmac_rst
-            CRYPTO_HMAC_RST: u1,
-            /// reg_dma_rst
-            DMA_RST: u1,
-            /// reg_sdio_host_rst
-            SDIO_HOST_RST: u1,
-            /// reg_lcd_cam_rst
-            LCD_CAM_RST: u1,
-            /// reg_uart2_rst
-            UART2_RST: u1,
-            /// reg_tsens_rst
-            TSENS_RST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x600c0020
-        /// clock config register
-        pub const BT_LPCK_DIV_INT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_bt_lpck_div_num
-            BT_LPCK_DIV_NUM: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x600c0024
-        /// clock config register
-        pub const BT_LPCK_DIV_FRAC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_bt_lpck_div_b
-            BT_LPCK_DIV_B: u12,
-            /// reg_bt_lpck_div_a
-            BT_LPCK_DIV_A: u12,
-            /// reg_lpclk_sel_rtc_slow
-            LPCLK_SEL_RTC_SLOW: u1,
-            /// reg_lpclk_sel_8m
-            LPCLK_SEL_8M: u1,
-            /// reg_lpclk_sel_xtal
-            LPCLK_SEL_XTAL: u1,
-            /// reg_lpclk_sel_xtal32k
-            LPCLK_SEL_XTAL32K: u1,
-            /// reg_lpclk_rtc_en
-            LPCLK_RTC_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x600c0028
-        /// interrupt generate register
-        pub const CPU_INTR_FROM_CPU_0 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x28);
-
-        /// address: 0x600c002c
-        /// interrupt generate register
-        pub const CPU_INTR_FROM_CPU_1 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x2c);
-
-        /// address: 0x600c0030
-        /// interrupt generate register
-        pub const CPU_INTR_FROM_CPU_2 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x30);
-
-        /// address: 0x600c0034
-        /// interrupt generate register
-        pub const CPU_INTR_FROM_CPU_3 = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x34);
-
-        /// address: 0x600c0038
-        /// rsa memory power control register
-        pub const RSA_PD_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rsa_mem_pd
-            RSA_MEM_PD: u1,
-            /// reg_rsa_mem_force_pu
-            RSA_MEM_FORCE_PU: u1,
-            /// reg_rsa_mem_force_pd
-            RSA_MEM_FORCE_PD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x600c003c
-        /// edma clcok and reset register
-        pub const EDMA_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_edma_clk_on
-            EDMA_CLK_ON: u1,
-            /// reg_edma_reset
-            EDMA_RESET: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x600c0040
-        /// cache control register
-        pub const CACHE_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_icache_clk_on
-            ICACHE_CLK_ON: u1,
-            /// reg_icache_reset
-            ICACHE_RESET: u1,
-            /// reg_dcache_clk_on
-            DCACHE_CLK_ON: u1,
-            /// reg_dcache_reset
-            DCACHE_RESET: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x600c0044
-        /// SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
-        pub const EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_enable_spi_manual_encrypt
-            ENABLE_SPI_MANUAL_ENCRYPT: u1,
-            /// reg_enable_download_db_encrypt
-            ENABLE_DOWNLOAD_DB_ENCRYPT: u1,
-            /// reg_enable_download_g0cb_decrypt
-            ENABLE_DOWNLOAD_G0CB_DECRYPT: u1,
-            /// reg_enable_download_manual_encrypt
-            ENABLE_DOWNLOAD_MANUAL_ENCRYPT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x600c0048
-        /// fast memory config register
-        pub const RTC_FASTMEM_CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// reg_rtc_mem_crc_start
-            RTC_MEM_CRC_START: u1,
-            /// reg_rtc_mem_crc_addr
-            RTC_MEM_CRC_ADDR: u11,
-            /// reg_rtc_mem_crc_len
-            RTC_MEM_CRC_LEN: u11,
-            /// reg_rtc_mem_crc_finish
-            RTC_MEM_CRC_FINISH: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x600c004c
-        /// reserved
-        pub const RTC_FASTMEM_CRC = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_rtc_mem_crc_res
-            RTC_MEM_CRC_RES: u32,
-        }), base_address + 0x4c);
-
-        /// address: 0x600c0050
-        /// eco register
-        pub const REDUNDANT_ECO_CTRL = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_redundant_eco_drive
-            REDUNDANT_ECO_DRIVE: u1,
-            /// reg_redundant_eco_result
-            REDUNDANT_ECO_RESULT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x600c0054
-        /// clock gating register
-        pub const CLOCK_GATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_clk_en
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x600c0058
-        /// system clock config register
-        pub const SYSCLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_pre_div_cnt
-            PRE_DIV_CNT: u10,
-            /// reg_soc_clk_sel
-            SOC_CLK_SEL: u2,
-            /// reg_clk_xtal_freq
-            CLK_XTAL_FREQ: u7,
-            /// reg_clk_div_en
-            CLK_DIV_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x600c005c
-        /// mem pvt register
-        pub const MEM_PVT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_mem_path_len
-            MEM_PATH_LEN: u4,
-            /// reg_mem_err_cnt_clr
-            MEM_ERR_CNT_CLR: u1,
-            /// reg_mem_pvt_monitor_en
-            MONITOR_EN: u1,
-            /// reg_mem_timing_err_cnt
-            MEM_TIMING_ERR_CNT: u16,
-            /// reg_mem_vt_sel
-            MEM_VT_SEL: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x600c0060
-        /// mem pvt register
-        pub const COMB_PVT_LVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_path_len_lvt
-            COMB_PATH_LEN_LVT: u5,
-            /// reg_comb_err_cnt_clr_lvt
-            COMB_ERR_CNT_CLR_LVT: u1,
-            /// reg_comb_pvt_monitor_en_lvt
-            COMB_PVT_MONITOR_EN_LVT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x600c0064
-        /// mem pvt register
-        pub const COMB_PVT_NVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_path_len_nvt
-            COMB_PATH_LEN_NVT: u5,
-            /// reg_comb_err_cnt_clr_nvt
-            COMB_ERR_CNT_CLR_NVT: u1,
-            /// reg_comb_pvt_monitor_en_nvt
-            COMB_PVT_MONITOR_EN_NVT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x600c0068
-        /// mem pvt register
-        pub const COMB_PVT_HVT_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_path_len_hvt
-            COMB_PATH_LEN_HVT: u5,
-            /// reg_comb_err_cnt_clr_hvt
-            COMB_ERR_CNT_CLR_HVT: u1,
-            /// reg_comb_pvt_monitor_en_hvt
-            COMB_PVT_MONITOR_EN_HVT: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x600c006c
-        /// mem pvt register
-        pub const COMB_PVT_ERR_LVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_lvt_site0
-            COMB_TIMING_ERR_CNT_LVT_SITE0: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x600c0070
-        /// mem pvt register
-        pub const COMB_PVT_ERR_NVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_nvt_site0
-            COMB_TIMING_ERR_CNT_NVT_SITE0: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x600c0074
-        /// mem pvt register
-        pub const COMB_PVT_ERR_HVT_SITE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_hvt_site0
-            COMB_TIMING_ERR_CNT_HVT_SITE0: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x600c0078
-        /// mem pvt register
-        pub const COMB_PVT_ERR_LVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_lvt_site1
-            COMB_TIMING_ERR_CNT_LVT_SITE1: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x600c007c
-        /// mem pvt register
-        pub const COMB_PVT_ERR_NVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_nvt_site1
-            COMB_TIMING_ERR_CNT_NVT_SITE1: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x600c0080
-        /// mem pvt register
-        pub const COMB_PVT_ERR_HVT_SITE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_hvt_site1
-            COMB_TIMING_ERR_CNT_HVT_SITE1: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x80);
-
-        /// address: 0x600c0084
-        /// mem pvt register
-        pub const COMB_PVT_ERR_LVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_lvt_site2
-            COMB_TIMING_ERR_CNT_LVT_SITE2: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x84);
-
-        /// address: 0x600c0088
-        /// mem pvt register
-        pub const COMB_PVT_ERR_NVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_nvt_site2
-            COMB_TIMING_ERR_CNT_NVT_SITE2: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x88);
-
-        /// address: 0x600c008c
-        /// mem pvt register
-        pub const COMB_PVT_ERR_HVT_SITE2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_hvt_site2
-            COMB_TIMING_ERR_CNT_HVT_SITE2: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x8c);
-
-        /// address: 0x600c0090
-        /// mem pvt register
-        pub const COMB_PVT_ERR_LVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_lvt_site3
-            COMB_TIMING_ERR_CNT_LVT_SITE3: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x90);
-
-        /// address: 0x600c0094
-        /// mem pvt register
-        pub const COMB_PVT_ERR_NVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_nvt_site3
-            COMB_TIMING_ERR_CNT_NVT_SITE3: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x94);
-
-        /// address: 0x600c0098
-        /// mem pvt register
-        pub const COMB_PVT_ERR_HVT_SITE3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_comb_timing_err_cnt_hvt_site3
-            COMB_TIMING_ERR_CNT_HVT_SITE3: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x98);
-
-        /// address: 0x600c0ffc
-        /// Version register
-        pub const SYSTEM_REG_DATE = @intToPtr(*volatile MmioInt(32, u28), base_address + 0xffc);
-    };
-
-    /// System Timer
-    pub const SYSTIMER = struct {
-        pub const base_address = 0x60023000;
-
-        /// address: 0x60023000
-        /// SYSTIMER_CONF.
-        pub const CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// systimer clock force on
-            SYSTIMER_CLK_FO: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            /// target2 work enable
-            TARGET2_WORK_EN: u1,
-            /// target1 work enable
-            TARGET1_WORK_EN: u1,
-            /// target0 work enable
-            TARGET0_WORK_EN: u1,
-            /// If timer unit1 is stalled when core1 stalled
-            TIMER_UNIT1_CORE1_STALL_EN: u1,
-            /// If timer unit1 is stalled when core0 stalled
-            TIMER_UNIT1_CORE0_STALL_EN: u1,
-            /// If timer unit0 is stalled when core1 stalled
-            TIMER_UNIT0_CORE1_STALL_EN: u1,
-            /// If timer unit0 is stalled when core0 stalled
-            TIMER_UNIT0_CORE0_STALL_EN: u1,
-            /// timer unit1 work enable
-            TIMER_UNIT1_WORK_EN: u1,
-            /// timer unit0 work enable
-            TIMER_UNIT0_WORK_EN: u1,
-            /// register file clk gating
-            CLK_EN: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60023004
-        /// SYSTIMER_UNIT0_OP.
-        pub const UNIT0_OP = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// reg_timer_unit0_value_valid
-            TIMER_UNIT0_VALUE_VALID: u1,
-            /// update timer_unit0
-            TIMER_UNIT0_UPDATE: u1,
-            padding0: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60023008
-        /// SYSTIMER_UNIT1_OP.
-        pub const UNIT1_OP = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// timer value is sync and valid
-            TIMER_UNIT1_VALUE_VALID: u1,
-            /// update timer unit1
-            TIMER_UNIT1_UPDATE: u1,
-            padding0: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6002300c
-        /// SYSTIMER_UNIT0_LOAD_HI.
-        pub const UNIT0_LOAD_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit0 load high 32 bit
-            TIMER_UNIT0_LOAD_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60023010
-        /// SYSTIMER_UNIT0_LOAD_LO.
-        pub const UNIT0_LOAD_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit0 load low 32 bit
-            TIMER_UNIT0_LOAD_LO: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x60023014
-        /// SYSTIMER_UNIT1_LOAD_HI.
-        pub const UNIT1_LOAD_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit1 load high 32 bit
-            TIMER_UNIT1_LOAD_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60023018
-        /// SYSTIMER_UNIT1_LOAD_LO.
-        pub const UNIT1_LOAD_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit1 load low 32 bit
-            TIMER_UNIT1_LOAD_LO: u32,
-        }), base_address + 0x18);
-
-        /// address: 0x6002301c
-        /// SYSTIMER_TARGET0_HI.
-        pub const TARGET0_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget0 high 32 bit
-            TIMER_TARGET0_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60023020
-        /// SYSTIMER_TARGET0_LO.
-        pub const TARGET0_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget0 low 32 bit
-            TIMER_TARGET0_LO: u32,
-        }), base_address + 0x20);
-
-        /// address: 0x60023024
-        /// SYSTIMER_TARGET1_HI.
-        pub const TARGET1_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget1 high 32 bit
-            TIMER_TARGET1_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60023028
-        /// SYSTIMER_TARGET1_LO.
-        pub const TARGET1_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget1 low 32 bit
-            TIMER_TARGET1_LO: u32,
-        }), base_address + 0x28);
-
-        /// address: 0x6002302c
-        /// SYSTIMER_TARGET2_HI.
-        pub const TARGET2_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget2 high 32 bit
-            TIMER_TARGET2_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60023030
-        /// SYSTIMER_TARGET2_LO.
-        pub const TARGET2_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer taget2 low 32 bit
-            TIMER_TARGET2_LO: u32,
-        }), base_address + 0x30);
-
-        /// address: 0x60023034
-        /// SYSTIMER_TARGET0_CONF.
-        pub const TARGET0_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// target0 period
-            TARGET0_PERIOD: u26,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// Set target0 to period mode
-            TARGET0_PERIOD_MODE: u1,
-            /// select which unit to compare
-            TARGET0_TIMER_UNIT_SEL: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60023038
-        /// SYSTIMER_TARGET1_CONF.
-        pub const TARGET1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// target1 period
-            TARGET1_PERIOD: u26,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// Set target1 to period mode
-            TARGET1_PERIOD_MODE: u1,
-            /// select which unit to compare
-            TARGET1_TIMER_UNIT_SEL: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6002303c
-        /// SYSTIMER_TARGET2_CONF.
-        pub const TARGET2_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// target2 period
-            TARGET2_PERIOD: u26,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            /// Set target2 to period mode
-            TARGET2_PERIOD_MODE: u1,
-            /// select which unit to compare
-            TARGET2_TIMER_UNIT_SEL: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60023040
-        /// SYSTIMER_UNIT0_VALUE_HI.
-        pub const UNIT0_VALUE_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer read value high 32bit
-            TIMER_UNIT0_VALUE_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60023044
-        /// SYSTIMER_UNIT0_VALUE_LO.
-        pub const UNIT0_VALUE_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer read value low 32bit
-            TIMER_UNIT0_VALUE_LO: u32,
-        }), base_address + 0x44);
-
-        /// address: 0x60023048
-        /// SYSTIMER_UNIT1_VALUE_HI.
-        pub const UNIT1_VALUE_HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer read value high 32bit
-            TIMER_UNIT1_VALUE_HI: u20,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6002304c
-        /// SYSTIMER_UNIT1_VALUE_LO.
-        pub const UNIT1_VALUE_LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer read value low 32bit
-            TIMER_UNIT1_VALUE_LO: u32,
-        }), base_address + 0x4c);
-
-        /// address: 0x60023050
-        /// SYSTIMER_COMP0_LOAD.
-        pub const COMP0_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer comp0 load value
-            TIMER_COMP0_LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60023054
-        /// SYSTIMER_COMP1_LOAD.
-        pub const COMP1_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer comp1 load value
-            TIMER_COMP1_LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60023058
-        /// SYSTIMER_COMP2_LOAD.
-        pub const COMP2_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer comp2 load value
-            TIMER_COMP2_LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6002305c
-        /// SYSTIMER_UNIT0_LOAD.
-        pub const UNIT0_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit0 load value
-            TIMER_UNIT0_LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60023060
-        /// SYSTIMER_UNIT1_LOAD.
-        pub const UNIT1_LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timer unit1 load value
-            TIMER_UNIT1_LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60023064
-        /// SYSTIMER_INT_ENA.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// interupt0 enable
-            TARGET0_INT_ENA: u1,
-            /// interupt1 enable
-            TARGET1_INT_ENA: u1,
-            /// interupt2 enable
-            TARGET2_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60023068
-        /// SYSTIMER_INT_RAW.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// interupt0 raw
-            TARGET0_INT_RAW: u1,
-            /// interupt1 raw
-            TARGET1_INT_RAW: u1,
-            /// interupt2 raw
-            TARGET2_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6002306c
-        /// SYSTIMER_INT_CLR.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// interupt0 clear
-            TARGET0_INT_CLR: u1,
-            /// interupt1 clear
-            TARGET1_INT_CLR: u1,
-            /// interupt2 clear
-            TARGET2_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60023070
-        /// SYSTIMER_INT_ST.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_target0_int_st
-            TARGET0_INT_ST: u1,
-            /// reg_target1_int_st
-            TARGET1_INT_ST: u1,
-            /// reg_target2_int_st
-            TARGET2_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x600230fc
-        /// SYSTIMER_DATE.
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0xfc);
-    };
-
-    /// Timer Group
-    pub const TIMG0 = struct {
-        pub const base_address = 0x6001f000;
-
-        /// address: 0x6001f000
-        /// TIMG_T0CONFIG_REG.
-        pub const T0CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// reg_t0_use_xtal.
-            T0_USE_XTAL: u1,
-            /// reg_t0_alarm_en.
-            T0_ALARM_EN: u1,
-            reserved9: u1,
-            /// reg_t0_divcnt_rst.
-            T0_DIVCNT_RST: u1,
-            /// reg_t0_divider.
-            T0_DIVIDER: u16,
-            /// reg_t0_autoreload.
-            T0_AUTORELOAD: u1,
-            /// reg_t0_increase.
-            T0_INCREASE: u1,
-            /// reg_t0_en.
-            T0_EN: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x6001f004
-        /// TIMG_T0LO_REG.
-        pub const T0LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_lo
-            T0_LO: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x6001f008
-        /// TIMG_T0HI_REG.
-        pub const T0HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_hi
-            T0_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6001f00c
-        /// TIMG_T0UPDATE_REG.
-        pub const T0UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// t0_update
-            T0_UPDATE: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x6001f010
-        /// TIMG_T0ALARMLO_REG.
-        pub const T0ALARMLO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_alarm_lo.
-            T0_ALARM_LO: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x6001f014
-        /// TIMG_T0ALARMHI_REG.
-        pub const T0ALARMHI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_alarm_hi.
-            T0_ALARM_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x6001f018
-        /// TIMG_T0LOADLO_REG.
-        pub const T0LOADLO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_load_lo.
-            T0_LOAD_LO: u32,
-        }), base_address + 0x18);
-
-        /// address: 0x6001f01c
-        /// TIMG_T0LOADHI_REG.
-        pub const T0LOADHI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_load_hi.
-            T0_LOAD_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x6001f020
-        /// TIMG_T0LOAD_REG.
-        pub const T0LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_load
-            T0_LOAD: u32,
-        }), base_address + 0x20);
-
-        /// address: 0x6001f048
-        /// TIMG_WDTCONFIG0_REG.
-        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// reg_wdt_appcpu_reset_en.
-            WDT_APPCPU_RESET_EN: u1,
-            /// reg_wdt_procpu_reset_en.
-            WDT_PROCPU_RESET_EN: u1,
-            /// reg_wdt_flashboot_mod_en.
-            WDT_FLASHBOOT_MOD_EN: u1,
-            /// reg_wdt_sys_reset_length.
-            WDT_SYS_RESET_LENGTH: u3,
-            /// reg_wdt_cpu_reset_length.
-            WDT_CPU_RESET_LENGTH: u3,
-            /// reg_wdt_use_xtal.
-            WDT_USE_XTAL: u1,
-            /// reg_wdt_conf_update_en.
-            WDT_CONF_UPDATE_EN: u1,
-            /// reg_wdt_stg3.
-            WDT_STG3: u2,
-            /// reg_wdt_stg2.
-            WDT_STG2: u2,
-            /// reg_wdt_stg1.
-            WDT_STG1: u2,
-            /// reg_wdt_stg0.
-            WDT_STG0: u2,
-            /// reg_wdt_en.
-            WDT_EN: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6001f04c
-        /// TIMG_WDTCONFIG1_REG.
-        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_divcnt_rst.
-            WDT_DIVCNT_RST: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reg_wdt_clk_prescale.
-            WDT_CLK_PRESCALE: u16,
-        }), base_address + 0x4c);
-
-        /// address: 0x6001f050
-        /// TIMG_WDTCONFIG2_REG.
-        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg0_hold.
-            WDT_STG0_HOLD: u32,
-        }), base_address + 0x50);
-
-        /// address: 0x6001f054
-        /// TIMG_WDTCONFIG3_REG.
-        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg1_hold.
-            WDT_STG1_HOLD: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x6001f058
-        /// TIMG_WDTCONFIG4_REG.
-        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg2_hold.
-            WDT_STG2_HOLD: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6001f05c
-        /// TIMG_WDTCONFIG5_REG.
-        pub const WDTCONFIG5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg3_hold.
-            WDT_STG3_HOLD: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x6001f060
-        /// TIMG_WDTFEED_REG.
-        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
-            /// wdt_feed
-            WDT_FEED: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x6001f064
-        /// TIMG_WDTWPROTECT_REG.
-        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_wkey.
-            WDT_WKEY: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x6001f068
-        /// TIMG_RTCCALICFG_REG.
-        pub const RTCCALICFG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// reg_rtc_cali_start_cycling.
-            RTC_CALI_START_CYCLING: u1,
-            /// reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
-            RTC_CALI_CLK_SEL: u2,
-            /// rtc_cali_rdy
-            RTC_CALI_RDY: u1,
-            /// reg_rtc_cali_max.
-            RTC_CALI_MAX: u15,
-            /// reg_rtc_cali_start.
-            RTC_CALI_START: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6001f06c
-        /// TIMG_RTCCALICFG1_REG.
-        pub const RTCCALICFG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// rtc_cali_cycling_data_vld
-            RTC_CALI_CYCLING_DATA_VLD: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// rtc_cali_value
-            RTC_CALI_VALUE: u25,
-        }), base_address + 0x6c);
-
-        /// address: 0x6001f070
-        /// INT_ENA_TIMG_REG
-        pub const INT_ENA_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_ena
-            T0_INT_ENA: u1,
-            /// wdt_int_ena
-            WDT_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x6001f074
-        /// INT_RAW_TIMG_REG
-        pub const INT_RAW_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_raw
-            T0_INT_RAW: u1,
-            /// wdt_int_raw
-            WDT_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x6001f078
-        /// INT_ST_TIMG_REG
-        pub const INT_ST_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_st
-            T0_INT_ST: u1,
-            /// wdt_int_st
-            WDT_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6001f07c
-        /// INT_CLR_TIMG_REG
-        pub const INT_CLR_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_clr
-            T0_INT_CLR: u1,
-            /// wdt_int_clr
-            WDT_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x6001f080
-        /// TIMG_RTCCALICFG2_REG.
-        pub const RTCCALICFG2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timeoutindicator
-            RTC_CALI_TIMEOUT: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
-            RTC_CALI_TIMEOUT_RST_CNT: u4,
-            /// reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
-            RTC_CALI_TIMEOUT_THRES: u25,
-        }), base_address + 0x80);
-
-        /// address: 0x6001f0f8
-        /// TIMG_NTIMG_DATE_REG.
-        pub const NTIMG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_ntimers_date.
-            NTIMGS_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xf8);
-
-        /// address: 0x6001f0fc
-        /// TIMG_REGCLK_REG.
-        pub const REGCLK = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// reg_wdt_clk_is_active.
-            WDT_CLK_IS_ACTIVE: u1,
-            /// reg_timer_clk_is_active.
-            TIMER_CLK_IS_ACTIVE: u1,
-            /// reg_clk_en.
-            CLK_EN: u1,
-        }), base_address + 0xfc);
-    };
-
-    /// Timer Group
-    pub const TIMG1 = struct {
-        pub const base_address = 0x60020000;
-
-        /// address: 0x60020000
-        /// TIMG_T0CONFIG_REG.
-        pub const T0CONFIG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            /// reg_t0_use_xtal.
-            T0_USE_XTAL: u1,
-            /// reg_t0_alarm_en.
-            T0_ALARM_EN: u1,
-            reserved9: u1,
-            /// reg_t0_divcnt_rst.
-            T0_DIVCNT_RST: u1,
-            /// reg_t0_divider.
-            T0_DIVIDER: u16,
-            /// reg_t0_autoreload.
-            T0_AUTORELOAD: u1,
-            /// reg_t0_increase.
-            T0_INCREASE: u1,
-            /// reg_t0_en.
-            T0_EN: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60020004
-        /// TIMG_T0LO_REG.
-        pub const T0LO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_lo
-            T0_LO: u32,
-        }), base_address + 0x4);
-
-        /// address: 0x60020008
-        /// TIMG_T0HI_REG.
-        pub const T0HI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_hi
-            T0_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6002000c
-        /// TIMG_T0UPDATE_REG.
-        pub const T0UPDATE = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            reserved29: u1,
-            reserved30: u1,
-            /// t0_update
-            T0_UPDATE: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60020010
-        /// TIMG_T0ALARMLO_REG.
-        pub const T0ALARMLO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_alarm_lo.
-            T0_ALARM_LO: u32,
-        }), base_address + 0x10);
-
-        /// address: 0x60020014
-        /// TIMG_T0ALARMHI_REG.
-        pub const T0ALARMHI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_alarm_hi.
-            T0_ALARM_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60020018
-        /// TIMG_T0LOADLO_REG.
-        pub const T0LOADLO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_load_lo.
-            T0_LOAD_LO: u32,
-        }), base_address + 0x18);
-
-        /// address: 0x6002001c
-        /// TIMG_T0LOADHI_REG.
-        pub const T0LOADHI = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_t0_load_hi.
-            T0_LOAD_HI: u22,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60020020
-        /// TIMG_T0LOAD_REG.
-        pub const T0LOAD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_load
-            T0_LOAD: u32,
-        }), base_address + 0x20);
-
-        /// address: 0x60020048
-        /// TIMG_WDTCONFIG0_REG.
-        pub const WDTCONFIG0 = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// reg_wdt_appcpu_reset_en.
-            WDT_APPCPU_RESET_EN: u1,
-            /// reg_wdt_procpu_reset_en.
-            WDT_PROCPU_RESET_EN: u1,
-            /// reg_wdt_flashboot_mod_en.
-            WDT_FLASHBOOT_MOD_EN: u1,
-            /// reg_wdt_sys_reset_length.
-            WDT_SYS_RESET_LENGTH: u3,
-            /// reg_wdt_cpu_reset_length.
-            WDT_CPU_RESET_LENGTH: u3,
-            /// reg_wdt_use_xtal.
-            WDT_USE_XTAL: u1,
-            /// reg_wdt_conf_update_en.
-            WDT_CONF_UPDATE_EN: u1,
-            /// reg_wdt_stg3.
-            WDT_STG3: u2,
-            /// reg_wdt_stg2.
-            WDT_STG2: u2,
-            /// reg_wdt_stg1.
-            WDT_STG1: u2,
-            /// reg_wdt_stg0.
-            WDT_STG0: u2,
-            /// reg_wdt_en.
-            WDT_EN: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6002004c
-        /// TIMG_WDTCONFIG1_REG.
-        pub const WDTCONFIG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_divcnt_rst.
-            WDT_DIVCNT_RST: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            /// reg_wdt_clk_prescale.
-            WDT_CLK_PRESCALE: u16,
-        }), base_address + 0x4c);
-
-        /// address: 0x60020050
-        /// TIMG_WDTCONFIG2_REG.
-        pub const WDTCONFIG2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg0_hold.
-            WDT_STG0_HOLD: u32,
-        }), base_address + 0x50);
-
-        /// address: 0x60020054
-        /// TIMG_WDTCONFIG3_REG.
-        pub const WDTCONFIG3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg1_hold.
-            WDT_STG1_HOLD: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x60020058
-        /// TIMG_WDTCONFIG4_REG.
-        pub const WDTCONFIG4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg2_hold.
-            WDT_STG2_HOLD: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6002005c
-        /// TIMG_WDTCONFIG5_REG.
-        pub const WDTCONFIG5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_stg3_hold.
-            WDT_STG3_HOLD: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x60020060
-        /// TIMG_WDTFEED_REG.
-        pub const WDTFEED = @intToPtr(*volatile Mmio(32, packed struct {
-            /// wdt_feed
-            WDT_FEED: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x60020064
-        /// TIMG_WDTWPROTECT_REG.
-        pub const WDTWPROTECT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_wdt_wkey.
-            WDT_WKEY: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x60020068
-        /// TIMG_RTCCALICFG_REG.
-        pub const RTCCALICFG = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            /// reg_rtc_cali_start_cycling.
-            RTC_CALI_START_CYCLING: u1,
-            /// reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
-            RTC_CALI_CLK_SEL: u2,
-            /// rtc_cali_rdy
-            RTC_CALI_RDY: u1,
-            /// reg_rtc_cali_max.
-            RTC_CALI_MAX: u15,
-            /// reg_rtc_cali_start.
-            RTC_CALI_START: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6002006c
-        /// TIMG_RTCCALICFG1_REG.
-        pub const RTCCALICFG1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// rtc_cali_cycling_data_vld
-            RTC_CALI_CYCLING_DATA_VLD: u1,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// rtc_cali_value
-            RTC_CALI_VALUE: u25,
-        }), base_address + 0x6c);
-
-        /// address: 0x60020070
-        /// INT_ENA_TIMG_REG
-        pub const INT_ENA_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_ena
-            T0_INT_ENA: u1,
-            /// wdt_int_ena
-            WDT_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60020074
-        /// INT_RAW_TIMG_REG
-        pub const INT_RAW_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_raw
-            T0_INT_RAW: u1,
-            /// wdt_int_raw
-            WDT_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60020078
-        /// INT_ST_TIMG_REG
-        pub const INT_ST_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_st
-            T0_INT_ST: u1,
-            /// wdt_int_st
-            WDT_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6002007c
-        /// INT_CLR_TIMG_REG
-        pub const INT_CLR_TIMERS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// t0_int_clr
-            T0_INT_CLR: u1,
-            /// wdt_int_clr
-            WDT_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x60020080
-        /// TIMG_RTCCALICFG2_REG.
-        pub const RTCCALICFG2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// timeoutindicator
-            RTC_CALI_TIMEOUT: u1,
-            reserved0: u1,
-            reserved1: u1,
-            /// reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
-            RTC_CALI_TIMEOUT_RST_CNT: u4,
-            /// reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
-            RTC_CALI_TIMEOUT_THRES: u25,
-        }), base_address + 0x80);
-
-        /// address: 0x600200f8
-        /// TIMG_NTIMG_DATE_REG.
-        pub const NTIMG_DATE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// reg_ntimers_date.
-            NTIMGS_DATE: u28,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0xf8);
-
-        /// address: 0x600200fc
-        /// TIMG_REGCLK_REG.
-        pub const REGCLK = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            reserved8: u1,
-            reserved9: u1,
-            reserved10: u1,
-            reserved11: u1,
-            reserved12: u1,
-            reserved13: u1,
-            reserved14: u1,
-            reserved15: u1,
-            reserved16: u1,
-            reserved17: u1,
-            reserved18: u1,
-            reserved19: u1,
-            reserved20: u1,
-            reserved21: u1,
-            reserved22: u1,
-            reserved23: u1,
-            reserved24: u1,
-            reserved25: u1,
-            reserved26: u1,
-            reserved27: u1,
-            reserved28: u1,
-            /// reg_wdt_clk_is_active.
-            WDT_CLK_IS_ACTIVE: u1,
-            /// reg_timer_clk_is_active.
-            TIMER_CLK_IS_ACTIVE: u1,
-            /// reg_clk_en.
-            CLK_EN: u1,
-        }), base_address + 0xfc);
-    };
-
-    /// Two-Wire Automotive Interface
-    pub const TWAI = struct {
-        pub const base_address = 0x6002b000;
-
-        /// address: 0x6002b000
-        /// Mode Register
-        pub const MODE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This bit is used to configure the operating mode of the TWAI Controller. 1:
-            /// Reset mode; 0: Operating mode.
-            RESET_MODE: u1,
-            /// 1: Listen only mode. In this mode the nodes will only receive messages from the
-            /// bus, without generating the acknowledge signal nor updating the RX error
-            /// counter.
-            LISTEN_ONLY_MODE: u1,
-            /// 1: Self test mode. In this mode the TX nodes can perform a successful
-            /// transmission without receiving the acknowledge signal. This mode is often used
-            /// to test a single node with the self reception request command.
-            SELF_TEST_MODE: u1,
-            /// This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single
-            /// filter mode.
-            RX_FILTER_MODE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x6002b004
-        /// Command Register
-        pub const CMD = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set the bit to 1 to allow the driving nodes start transmission.
-            TX_REQ: u1,
-            /// Set the bit to 1 to cancel a pending transmission request.
-            ABORT_TX: u1,
-            /// Set the bit to 1 to release the RX buffer.
-            RELEASE_BUF: u1,
-            /// Set the bit to 1 to clear the data overrun status bit.
-            CLR_OVERRUN: u1,
-            /// Self reception request command. Set the bit to 1 to allow a message be
-            /// transmitted and received simultaneously.
-            SELF_RX_REQ: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x6002b008
-        /// Status register
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: The data in the RX buffer is not empty, with at least one received data
-            /// packet.
-            RX_BUF_ST: u1,
-            /// 1: The RX FIFO is full and data overrun has occurred.
-            OVERRUN_ST: u1,
-            /// 1: The TX buffer is empty, the CPU may write a message into it.
-            TX_BUF_ST: u1,
-            /// 1: The TWAI controller has successfully received a packet from the bus.
-            TX_COMPLETE: u1,
-            /// 1: The TWAI Controller is receiving a message from the bus.
-            RX_ST: u1,
-            /// 1: The TWAI Controller is transmitting a message to the bus.
-            TX_ST: u1,
-            /// 1: At least one of the RX/TX error counter has reached or exceeded the value set
-            /// in register TWAI_ERR_WARNING_LIMIT_REG.
-            ERR_ST: u1,
-            /// 1: In bus-off status, the TWAI Controller is no longer involved in bus
-            /// activities.
-            BUS_OFF_ST: u1,
-            /// This bit reflects whether the data packet in the RX FIFO is complete. 1: The
-            /// current packet is missing; 0: The current packet is complete
-            MISS_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6002b00c
-        /// Interrupt Register
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Receive interrupt. If this bit is set to 1, it indicates there are messages to
-            /// be handled in the RX FIFO.
-            RX_INT_ST: u1,
-            /// Transmit interrupt. If this bit is set to 1, it indicates the message
-            /// transmitting mis- sion is finished and a new transmission is able to execute.
-            TX_INT_ST: u1,
-            /// Error warning interrupt. If this bit is set to 1, it indicates the error status
-            /// signal and the bus-off status signal of Status register have changed (e.g.,
-            /// switched from 0 to 1 or from 1 to 0).
-            ERR_WARN_INT_ST: u1,
-            /// Data overrun interrupt. If this bit is set to 1, it indicates a data overrun
-            /// interrupt is generated in the RX FIFO.
-            OVERRUN_INT_ST: u1,
-            reserved0: u1,
-            /// Error passive interrupt. If this bit is set to 1, it indicates the TWAI
-            /// Controller is switched between error active status and error passive status due
-            /// to the change of error counters.
-            ERR_PASSIVE_INT_ST: u1,
-            /// Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration
-            /// lost interrupt is generated.
-            ARB_LOST_INT_ST: u1,
-            /// Error interrupt. If this bit is set to 1, it indicates an error is detected on
-            /// the bus.
-            BUS_ERR_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x6002b010
-        /// Interrupt Enable Register
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to 1 to enable receive interrupt.
-            RX_INT_ENA: u1,
-            /// Set this bit to 1 to enable transmit interrupt.
-            TX_INT_ENA: u1,
-            /// Set this bit to 1 to enable error warning interrupt.
-            ERR_WARN_INT_ENA: u1,
-            /// Set this bit to 1 to enable data overrun interrupt.
-            OVERRUN_INT_ENA: u1,
-            reserved0: u1,
-            /// Set this bit to 1 to enable error passive interrupt.
-            ERR_PASSIVE_INT_ENA: u1,
-            /// Set this bit to 1 to enable arbitration lost interrupt.
-            ARB_LOST_INT_ENA: u1,
-            /// Set this bit to 1 to enable error interrupt.
-            BUS_ERR_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x6002b018
-        /// Bus Timing Register 0
-        pub const BUS_TIMING_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Baud Rate Prescaler, determines the frequency dividing ratio.
-            BAUD_PRESC: u13,
-            reserved0: u1,
-            /// Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.
-            SYNC_JUMP_WIDTH: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6002b01c
-        /// Bus Timing Register 1
-        pub const BUS_TIMING_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The width of PBS1.
-            TIME_SEG1: u4,
-            /// The width of PBS2.
-            TIME_SEG2: u3,
-            /// The number of sample points. 0: the bus is sampled once; 1: the bus is sampled
-            /// three times
-            TIME_SAMP: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x6002b02c
-        /// Arbitration Lost Capture Register
-        pub const ARB_LOST_CAP = @intToPtr(*volatile MmioInt(32, u5), base_address + 0x2c);
-
-        /// address: 0x6002b030
-        /// Error Code Capture Register
-        pub const ERR_CODE_CAP = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register contains information about the location of errors, see Table 181
-            /// for details.
-            ECC_SEGMENT: u5,
-            /// This register contains information about transmission direction of the node when
-            /// error occurs. 1: Error occurs when receiving a message; 0: Error occurs when
-            /// transmitting a message
-            ECC_DIRECTION: u1,
-            /// This register contains information about error types: 00: bit error; 01: form
-            /// error; 10: stuff error; 11: other type of error
-            ECC_TYPE: u2,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x6002b034
-        /// Error Warning Limit Register
-        pub const ERR_WARNING_LIMIT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x34);
-
-        /// address: 0x6002b038
-        /// Receive Error Counter Register
-        pub const RX_ERR_CNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x38);
-
-        /// address: 0x6002b03c
-        /// Transmit Error Counter Register
-        pub const TX_ERR_CNT = @intToPtr(*volatile MmioInt(32, u8), base_address + 0x3c);
-
-        /// address: 0x6002b040
-        /// Data register 0
-        pub const DATA_0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance code register 0 with R/W Permission. In
-            /// operation mode, it stores the 0th byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_0: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x6002b044
-        /// Data register 1
-        pub const DATA_1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance code register 1 with R/W Permission. In
-            /// operation mode, it stores the 1st byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x6002b048
-        /// Data register 2
-        pub const DATA_2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance code register 2 with R/W Permission. In
-            /// operation mode, it stores the 2nd byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_2: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6002b04c
-        /// Data register 3
-        pub const DATA_3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance code register 3 with R/W Permission. In
-            /// operation mode, it stores the 3rd byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_3: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x6002b050
-        /// Data register 4
-        pub const DATA_4 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance mask register 0 with R/W Permission. In
-            /// operation mode, it stores the 4th byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_4: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x6002b054
-        /// Data register 5
-        pub const DATA_5 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance mask register 1 with R/W Permission. In
-            /// operation mode, it stores the 5th byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_5: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x6002b058
-        /// Data register 6
-        pub const DATA_6 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance mask register 2 with R/W Permission. In
-            /// operation mode, it stores the 6th byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_6: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6002b05c
-        /// Data register 7
-        pub const DATA_7 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// In reset mode, it is acceptance mask register 3 with R/W Permission. In
-            /// operation mode, it stores the 7th byte information of the data to be transmitted
-            /// under operating mode.
-            TX_BYTE_7: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x6002b060
-        /// Data register 8
-        pub const DATA_8 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stored the 8th byte information of the data to be transmitted under operating
-            /// mode.
-            TX_BYTE_8: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x6002b064
-        /// Data register 9
-        pub const DATA_9 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stored the 9th byte information of the data to be transmitted under operating
-            /// mode.
-            TX_BYTE_9: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x6002b068
-        /// Data register 10
-        pub const DATA_10 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stored the 10th byte information of the data to be transmitted under operating
-            /// mode.
-            TX_BYTE_10: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6002b06c
-        /// Data register 11
-        pub const DATA_11 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stored the 11th byte information of the data to be transmitted under operating
-            /// mode.
-            TX_BYTE_11: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x6002b070
-        /// Data register 12
-        pub const DATA_12 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stored the 12th byte information of the data to be transmitted under operating
-            /// mode.
-            TX_BYTE_12: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x6002b074
-        /// Receive Message Counter Register
-        pub const RX_MESSAGE_CNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register reflects the number of messages available within the RX FIFO.
-            RX_MESSAGE_COUNTER: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x6002b07c
-        /// Clock Divider register
-        pub const CLOCK_DIVIDER = @intToPtr(*volatile Mmio(32, packed struct {
-            /// These bits are used to configure frequency dividing coefficients of the external
-            /// CLKOUT pin.
-            CD: u8,
-            /// This bit can be configured under reset mode. 1: Disable the external CLKOUT pin;
-            /// 0: Enable the external CLKOUT pin
-            CLOCK_OFF: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x7c);
-    };
-
-    /// UART (Universal Asynchronous Receiver-Transmitter) Controller
-    pub const UART0 = struct {
-        pub const base_address = 0x60000000;
-
-        /// address: 0x60000000
-        /// FIFO data register
-        pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// UART 0 accesses FIFO via this register.
-            RXFIFO_RD_BYTE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60000004
-        /// Raw interrupt status
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This interrupt raw bit turns to high level when receiver receives more data than
-            /// what rxfifo_full_thrhd specifies.
-            RXFIFO_FULL_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-            /// less than what txfifo_empty_thrhd specifies .
-            TXFIFO_EMPTY_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a parity error
-            /// in the data.
-            PARITY_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a data frame
-            /// error .
-            FRM_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver receives more data than
-            /// the FIFO can store.
-            RXFIFO_OVF_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the edge change
-            /// of DSRn signal.
-            DSR_CHG_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the edge change
-            /// of CTSn signal.
-            CTS_CHG_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a 0 after the
-            /// stop bit.
-            BRK_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver takes more time than
-            /// rx_tout_thrhd to receive a byte.
-            RXFIFO_TOUT_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver recevies Xon char when
-            /// uart_sw_flow_con_en is set to 1.
-            SW_XON_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver receives Xoff char when
-            /// uart_sw_flow_con_en is set to 1.
-            SW_XOFF_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a glitch in the
-            /// middle of a start bit.
-            GLITCH_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter completes sending
-            /// NULL characters, after all data in Tx-FIFO are sent.
-            TX_BRK_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter has kept the
-            /// shortest duration after sending the last data.
-            TX_BRK_IDLE_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter has send out all
-            /// data in FIFO.
-            TX_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a parity error
-            /// from the echo of transmitter in rs485 mode.
-            RS485_PARITY_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a data frame
-            /// error from the echo of transmitter in rs485 mode.
-            RS485_FRM_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when detects a clash between
-            /// transmitter and receiver in rs485 mode.
-            RS485_CLASH_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the configured
-            /// at_cmd char.
-            AT_CMD_CHAR_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when input rxd edge changes more
-            /// times than what reg_active_threshold specifies in light sleeping mode.
-            WAKEUP_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60000008
-        /// Masked interrupt status
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set
-            /// to 1.
-            RXFIFO_FULL_INT_ST: u1,
-            /// This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set
-            /// to 1.
-            TXFIFO_EMPTY_INT_ST: u1,
-            /// This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
-            /// 1.
-            PARITY_ERR_INT_ST: u1,
-            /// This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-            FRM_ERR_INT_ST: u1,
-            /// This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
-            /// 1.
-            RXFIFO_OVF_INT_ST: u1,
-            /// This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-            DSR_CHG_INT_ST: u1,
-            /// This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-            CTS_CHG_INT_ST: u1,
-            /// This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-            BRK_DET_INT_ST: u1,
-            /// This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set
-            /// to 1.
-            RXFIFO_TOUT_INT_ST: u1,
-            /// This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-            SW_XON_INT_ST: u1,
-            /// This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-            SW_XOFF_INT_ST: u1,
-            /// This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
-            /// 1.
-            GLITCH_DET_INT_ST: u1,
-            /// This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set
-            /// to 1.
-            TX_BRK_DONE_INT_ST: u1,
-            /// This is the stauts bit for tx_brk_idle_done_int_raw when
-            /// tx_brk_idle_done_int_ena is set to 1.
-            TX_BRK_IDLE_DONE_INT_ST: u1,
-            /// This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-            TX_DONE_INT_ST: u1,
-            /// This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
-            /// set to 1.
-            RS485_PARITY_ERR_INT_ST: u1,
-            /// This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is
-            /// set to 1.
-            RS485_FRM_ERR_INT_ST: u1,
-            /// This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set
-            /// to 1.
-            RS485_CLASH_INT_ST: u1,
-            /// This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is
-            /// set to 1.
-            AT_CMD_CHAR_DET_INT_ST: u1,
-            /// This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set
-            /// to 1.
-            WAKEUP_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000000c
-        /// Interrupt enable bits
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the enable bit for rxfifo_full_int_st register.
-            RXFIFO_FULL_INT_ENA: u1,
-            /// This is the enable bit for txfifo_empty_int_st register.
-            TXFIFO_EMPTY_INT_ENA: u1,
-            /// This is the enable bit for parity_err_int_st register.
-            PARITY_ERR_INT_ENA: u1,
-            /// This is the enable bit for frm_err_int_st register.
-            FRM_ERR_INT_ENA: u1,
-            /// This is the enable bit for rxfifo_ovf_int_st register.
-            RXFIFO_OVF_INT_ENA: u1,
-            /// This is the enable bit for dsr_chg_int_st register.
-            DSR_CHG_INT_ENA: u1,
-            /// This is the enable bit for cts_chg_int_st register.
-            CTS_CHG_INT_ENA: u1,
-            /// This is the enable bit for brk_det_int_st register.
-            BRK_DET_INT_ENA: u1,
-            /// This is the enable bit for rxfifo_tout_int_st register.
-            RXFIFO_TOUT_INT_ENA: u1,
-            /// This is the enable bit for sw_xon_int_st register.
-            SW_XON_INT_ENA: u1,
-            /// This is the enable bit for sw_xoff_int_st register.
-            SW_XOFF_INT_ENA: u1,
-            /// This is the enable bit for glitch_det_int_st register.
-            GLITCH_DET_INT_ENA: u1,
-            /// This is the enable bit for tx_brk_done_int_st register.
-            TX_BRK_DONE_INT_ENA: u1,
-            /// This is the enable bit for tx_brk_idle_done_int_st register.
-            TX_BRK_IDLE_DONE_INT_ENA: u1,
-            /// This is the enable bit for tx_done_int_st register.
-            TX_DONE_INT_ENA: u1,
-            /// This is the enable bit for rs485_parity_err_int_st register.
-            RS485_PARITY_ERR_INT_ENA: u1,
-            /// This is the enable bit for rs485_parity_err_int_st register.
-            RS485_FRM_ERR_INT_ENA: u1,
-            /// This is the enable bit for rs485_clash_int_st register.
-            RS485_CLASH_INT_ENA: u1,
-            /// This is the enable bit for at_cmd_char_det_int_st register.
-            AT_CMD_CHAR_DET_INT_ENA: u1,
-            /// This is the enable bit for uart_wakeup_int_st register.
-            WAKEUP_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60000010
-        /// Interrupt clear bits
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the rxfifo_full_int_raw interrupt.
-            RXFIFO_FULL_INT_CLR: u1,
-            /// Set this bit to clear txfifo_empty_int_raw interrupt.
-            TXFIFO_EMPTY_INT_CLR: u1,
-            /// Set this bit to clear parity_err_int_raw interrupt.
-            PARITY_ERR_INT_CLR: u1,
-            /// Set this bit to clear frm_err_int_raw interrupt.
-            FRM_ERR_INT_CLR: u1,
-            /// Set this bit to clear rxfifo_ovf_int_raw interrupt.
-            RXFIFO_OVF_INT_CLR: u1,
-            /// Set this bit to clear the dsr_chg_int_raw interrupt.
-            DSR_CHG_INT_CLR: u1,
-            /// Set this bit to clear the cts_chg_int_raw interrupt.
-            CTS_CHG_INT_CLR: u1,
-            /// Set this bit to clear the brk_det_int_raw interrupt.
-            BRK_DET_INT_CLR: u1,
-            /// Set this bit to clear the rxfifo_tout_int_raw interrupt.
-            RXFIFO_TOUT_INT_CLR: u1,
-            /// Set this bit to clear the sw_xon_int_raw interrupt.
-            SW_XON_INT_CLR: u1,
-            /// Set this bit to clear the sw_xoff_int_raw interrupt.
-            SW_XOFF_INT_CLR: u1,
-            /// Set this bit to clear the glitch_det_int_raw interrupt.
-            GLITCH_DET_INT_CLR: u1,
-            /// Set this bit to clear the tx_brk_done_int_raw interrupt..
-            TX_BRK_DONE_INT_CLR: u1,
-            /// Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-            TX_BRK_IDLE_DONE_INT_CLR: u1,
-            /// Set this bit to clear the tx_done_int_raw interrupt.
-            TX_DONE_INT_CLR: u1,
-            /// Set this bit to clear the rs485_parity_err_int_raw interrupt.
-            RS485_PARITY_ERR_INT_CLR: u1,
-            /// Set this bit to clear the rs485_frm_err_int_raw interrupt.
-            RS485_FRM_ERR_INT_CLR: u1,
-            /// Set this bit to clear the rs485_clash_int_raw interrupt.
-            RS485_CLASH_INT_CLR: u1,
-            /// Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-            AT_CMD_CHAR_DET_INT_CLR: u1,
-            /// Set this bit to clear the uart_wakeup_int_raw interrupt.
-            WAKEUP_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60000014
-        /// Clock divider configuration
-        pub const CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The integral part of the frequency divider factor.
-            CLKDIV: u12,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// The decimal part of the frequency divider factor.
-            FRAG: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60000018
-        /// Rx Filter configuration
-        pub const RX_FILT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// when input pulse width is lower than this value, the pulse is ignored.
-            GLITCH_FILT: u8,
-            /// Set this bit to enable Rx signal filter.
-            GLITCH_FILT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000001c
-        /// UART status register
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the byte number of valid data in Rx-FIFO.
-            RXFIFO_CNT: u10,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The register represent the level value of the internal uart dsr signal.
-            DSRN: u1,
-            /// This register represent the level value of the internal uart cts signal.
-            CTSN: u1,
-            /// This register represent the level value of the internal uart rxd signal.
-            RXD: u1,
-            /// Stores the byte number of data in Tx-FIFO.
-            TXFIFO_CNT: u10,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// This bit represents the level of the internal uart dtr signal.
-            DTRN: u1,
-            /// This bit represents the level of the internal uart rts signal.
-            RTSN: u1,
-            /// This bit represents the level of the internal uart txd signal.
-            TXD: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60000020
-        /// a
-        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the parity check mode.
-            PARITY: u1,
-            /// Set this bit to enable uart parity check.
-            PARITY_EN: u1,
-            /// This register is used to set the length of data.
-            BIT_NUM: u2,
-            /// This register is used to set the length of stop bit.
-            STOP_BIT_NUM: u2,
-            /// This register is used to configure the software rts signal which is used in
-            /// software flow control.
-            SW_RTS: u1,
-            /// This register is used to configure the software dtr signal which is used in
-            /// software flow control.
-            SW_DTR: u1,
-            /// Set this bit to enbale transmitter to send NULL when the process of sending data
-            /// is done.
-            TXD_BRK: u1,
-            /// Set this bit to enable IrDA loopback mode.
-            IRDA_DPLX: u1,
-            /// This is the start enable bit for IrDA transmitter.
-            IRDA_TX_EN: u1,
-            /// 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
-            /// transmitter's 11th bit to 0.
-            IRDA_WCTL: u1,
-            /// Set this bit to invert the level of IrDA transmitter.
-            IRDA_TX_INV: u1,
-            /// Set this bit to invert the level of IrDA receiver.
-            IRDA_RX_INV: u1,
-            /// Set this bit to enable uart loopback test mode.
-            LOOPBACK: u1,
-            /// Set this bit to enable flow control function for transmitter.
-            TX_FLOW_EN: u1,
-            /// Set this bit to enable IrDA protocol.
-            IRDA_EN: u1,
-            /// Set this bit to reset the uart receive-FIFO.
-            RXFIFO_RST: u1,
-            /// Set this bit to reset the uart transmit-FIFO.
-            TXFIFO_RST: u1,
-            /// Set this bit to inverse the level value of uart rxd signal.
-            RXD_INV: u1,
-            /// Set this bit to inverse the level value of uart cts signal.
-            CTS_INV: u1,
-            /// Set this bit to inverse the level value of uart dsr signal.
-            DSR_INV: u1,
-            /// Set this bit to inverse the level value of uart txd signal.
-            TXD_INV: u1,
-            /// Set this bit to inverse the level value of uart rts signal.
-            RTS_INV: u1,
-            /// Set this bit to inverse the level value of uart dtr signal.
-            DTR_INV: u1,
-            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
-            /// writes registers.
-            CLK_EN: u1,
-            /// 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-            /// stores the data even if the received data is wrong.
-            ERR_WR_MASK: u1,
-            /// This is the enable bit for detecting baudrate.
-            AUTOBAUD_EN: u1,
-            /// UART memory clock gate enable signal.
-            MEM_CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60000024
-        /// Configuration register 1
-        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// It will produce rxfifo_full_int interrupt when receiver receives more data than
-            /// this register value.
-            RXFIFO_FULL_THRHD: u9,
-            /// It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is
-            /// less than this register value.
-            TXFIFO_EMPTY_THRHD: u9,
-            /// Disable UART Rx data overflow detect.
-            DIS_RX_DAT_OVF: u1,
-            /// Set this bit to stop accumulating idle_cnt when hardware flow control works.
-            RX_TOUT_FLOW_DIS: u1,
-            /// This is the flow enable bit for UART receiver.
-            RX_FLOW_EN: u1,
-            /// This is the enble bit for uart receiver's timeout function.
-            RX_TOUT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60000028
-        /// Autobaud minimum low pulse duration register
-        pub const LOWPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the value of the minimum duration time of the low level
-            /// pulse. It is used in baud rate-detect process.
-            MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6000002c
-        /// Autobaud minimum high pulse duration register
-        pub const HIGHPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the value of the maxinum duration time for the high level
-            /// pulse. It is used in baud rate-detect process.
-            MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60000030
-        /// Autobaud edge change count register
-        pub const RXD_CNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the count of rxd edge change. It is used in baud
-            /// rate-detect process.
-            RXD_EDGE_CNT: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60000034
-        /// Software flow-control configuration
-        pub const FLOW_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to enable software flow control. It is used with register sw_xon or
-            /// sw_xoff.
-            SW_FLOW_CON_EN: u1,
-            /// Set this bit to remove flow control char from the received data.
-            XONOFF_DEL: u1,
-            /// Set this bit to enable the transmitter to go on sending data.
-            FORCE_XON: u1,
-            /// Set this bit to stop the transmitter from sending data.
-            FORCE_XOFF: u1,
-            /// Set this bit to send Xon char. It is cleared by hardware automatically.
-            SEND_XON: u1,
-            /// Set this bit to send Xoff char. It is cleared by hardware automatically.
-            SEND_XOFF: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60000038
-        /// Sleep-mode configuration
-        pub const SLEEP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The uart is activated from light sleeping mode when the input rxd edge changes
-            /// more times than this register value.
-            ACTIVE_THRESHOLD: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6000003c
-        /// Software flow-control character configuration
-        pub const SWFC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// When the data amount in Rx-FIFO is more than this register value with
-            /// uart_sw_flow_con_en set to 1, it will send a Xoff char.
-            XOFF_THRESHOLD: u9,
-            /// This register stores the Xoff flow control char.
-            XOFF_CHAR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60000040
-        /// Software flow-control character configuration
-        pub const SWFC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// When the data amount in Rx-FIFO is less than this register value with
-            /// uart_sw_flow_con_en set to 1, it will send a Xon char.
-            XON_THRESHOLD: u9,
-            /// This register stores the Xon flow control char.
-            XON_CHAR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60000044
-        /// Tx Break character configuration
-        pub const TXBRK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the number of 0 to be sent after the process
-            /// of sending data is done. It is active when txd_brk is set to 1.
-            TX_BRK_NUM: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60000048
-        /// Frame-end idle configuration
-        pub const IDLE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// It will produce frame end signal when receiver takes more time to receive one
-            /// byte data than this register value.
-            RX_IDLE_THRHD: u10,
-            /// This register is used to configure the duration time between transfers.
-            TX_IDLE_NUM: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6000004c
-        /// RS485 mode configuration
-        pub const RS485_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to choose the rs485 mode.
-            RS485_EN: u1,
-            /// Set this bit to delay the stop bit by 1 bit.
-            DL0_EN: u1,
-            /// Set this bit to delay the stop bit by 1 bit.
-            DL1_EN: u1,
-            /// Set this bit to enable receiver could receive data when the transmitter is
-            /// transmitting data in rs485 mode.
-            RS485TX_RX_EN: u1,
-            /// 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
-            RS485RXBY_TX_EN: u1,
-            /// This register is used to delay the receiver's internal data signal.
-            RS485_RX_DLY_NUM: u1,
-            /// This register is used to delay the transmitter's internal data signal.
-            RS485_TX_DLY_NUM: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60000050
-        /// Pre-sequence timing configuration
-        pub const AT_CMD_PRECNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the idle duration time before the first
-            /// at_cmd is received by receiver.
-            PRE_IDLE_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60000054
-        /// Post-sequence timing configuration
-        pub const AT_CMD_POSTCNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the duration time between the last at_cmd and
-            /// the next data.
-            POST_IDLE_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60000058
-        /// Timeout configuration
-        pub const AT_CMD_GAPTOUT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the duration time between the at_cmd chars.
-            RX_GAP_TOUT: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6000005c
-        /// AT escape sequence detection configuration
-        pub const AT_CMD_CHAR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the content of at_cmd char.
-            AT_CMD_CHAR: u8,
-            /// This register is used to configure the num of continuous at_cmd chars received
-            /// by receiver.
-            CHAR_NUM: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60000060
-        /// UART threshold and allocation configuration
-        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// This register is used to configure the amount of mem allocated for receive-FIFO.
-            /// The default number is 128 bytes.
-            RX_SIZE: u3,
-            /// This register is used to configure the amount of mem allocated for
-            /// transmit-FIFO. The default number is 128 bytes.
-            TX_SIZE: u3,
-            /// This register is used to configure the maximum amount of data that can be
-            /// received when hardware flow control works.
-            RX_FLOW_THRHD: u9,
-            /// This register is used to configure the threshold time that receiver takes to
-            /// receive one byte. The rxfifo_tout_int interrupt will be trigger when the
-            /// receiver takes more time to receive one byte with rx_tout_en set to 1.
-            RX_TOUT_THRHD: u10,
-            /// Set this bit to force power down UART memory.
-            MEM_FORCE_PD: u1,
-            /// Set this bit to force power up UART memory.
-            MEM_FORCE_PU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60000064
-        /// Tx-FIFO write and read offset address.
-        pub const MEM_TX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
-            /// via APB.
-            APB_TX_WADDR: u10,
-            reserved0: u1,
-            /// This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
-            /// Tx-FIFO_Ctrl.
-            TX_RADDR: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60000068
-        /// Rx-FIFO write and read offset address.
-        pub const MEM_RX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the offset address in RX-FIFO when software reads data from
-            /// Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
-            APB_RX_RADDR: u10,
-            reserved0: u1,
-            /// This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
-            /// Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
-            RX_WADDR: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6000006c
-        /// UART transmit and receive status.
-        pub const FSM_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the status register of receiver.
-            ST_URX_OUT: u4,
-            /// This is the status register of transmitter.
-            ST_UTX_OUT: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60000070
-        /// Autobaud high pulse register
-        pub const POSPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the minimal input clock count between two positive edges.
-            /// It is used in boudrate-detect process.
-            POSEDGE_MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60000074
-        /// Autobaud low pulse register
-        pub const NEGPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the minimal input clock count between two negative edges.
-            /// It is used in boudrate-detect process.
-            NEGEDGE_MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60000078
-        /// UART core clock configuration
-        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The denominator of the frequency divider factor.
-            SCLK_DIV_B: u6,
-            /// The numerator of the frequency divider factor.
-            SCLK_DIV_A: u6,
-            /// The integral part of the frequency divider factor.
-            SCLK_DIV_NUM: u8,
-            /// UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
-            SCLK_SEL: u2,
-            /// Set this bit to enable UART Tx/Rx clock.
-            SCLK_EN: u1,
-            /// Write 1 then write 0 to this bit, reset UART Tx/Rx.
-            RST_CORE: u1,
-            /// Set this bit to enable UART Tx clock.
-            TX_SCLK_EN: u1,
-            /// Set this bit to enable UART Rx clock.
-            RX_SCLK_EN: u1,
-            /// Write 1 then write 0 to this bit, reset UART Tx.
-            TX_RST_CORE: u1,
-            /// Write 1 then write 0 to this bit, reset UART Rx.
-            RX_RST_CORE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6000007c
-        /// UART Version register
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x7c);
-
-        /// address: 0x60000080
-        /// UART ID register
-        pub const ID = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the uart_id.
-            ID: u30,
-            /// This bit used to select synchronize mode. 1: Registers are auto synchronized
-            /// into UART Core clock and UART core should be keep the same with APB clock. 0:
-            /// After configure registers, software needs to write 1 to UART_REG_UPDATE to
-            /// synchronize registers.
-            HIGH_SPEED: u1,
-            /// Software write 1 would synchronize registers into UART Core clock domain and
-            /// would be cleared by hardware after synchronization is done.
-            REG_UPDATE: u1,
-        }), base_address + 0x80);
-    };
-
-    /// UART (Universal Asynchronous Receiver-Transmitter) Controller
-    pub const UART1 = struct {
-        pub const base_address = 0x60010000;
-
-        /// address: 0x60010000
-        /// FIFO data register
-        pub const FIFO = @intToPtr(*volatile Mmio(32, packed struct {
-            /// UART 0 accesses FIFO via this register.
-            RXFIFO_RD_BYTE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60010004
-        /// Raw interrupt status
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This interrupt raw bit turns to high level when receiver receives more data than
-            /// what rxfifo_full_thrhd specifies.
-            RXFIFO_FULL_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is
-            /// less than what txfifo_empty_thrhd specifies .
-            TXFIFO_EMPTY_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a parity error
-            /// in the data.
-            PARITY_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a data frame
-            /// error .
-            FRM_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver receives more data than
-            /// the FIFO can store.
-            RXFIFO_OVF_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the edge change
-            /// of DSRn signal.
-            DSR_CHG_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the edge change
-            /// of CTSn signal.
-            CTS_CHG_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a 0 after the
-            /// stop bit.
-            BRK_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver takes more time than
-            /// rx_tout_thrhd to receive a byte.
-            RXFIFO_TOUT_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver recevies Xon char when
-            /// uart_sw_flow_con_en is set to 1.
-            SW_XON_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver receives Xoff char when
-            /// uart_sw_flow_con_en is set to 1.
-            SW_XOFF_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a glitch in the
-            /// middle of a start bit.
-            GLITCH_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter completes sending
-            /// NULL characters, after all data in Tx-FIFO are sent.
-            TX_BRK_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter has kept the
-            /// shortest duration after sending the last data.
-            TX_BRK_IDLE_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when transmitter has send out all
-            /// data in FIFO.
-            TX_DONE_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a parity error
-            /// from the echo of transmitter in rs485 mode.
-            RS485_PARITY_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects a data frame
-            /// error from the echo of transmitter in rs485 mode.
-            RS485_FRM_ERR_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when detects a clash between
-            /// transmitter and receiver in rs485 mode.
-            RS485_CLASH_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when receiver detects the configured
-            /// at_cmd char.
-            AT_CMD_CHAR_DET_INT_RAW: u1,
-            /// This interrupt raw bit turns to high level when input rxd edge changes more
-            /// times than what reg_active_threshold specifies in light sleeping mode.
-            WAKEUP_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60010008
-        /// Masked interrupt status
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set
-            /// to 1.
-            RXFIFO_FULL_INT_ST: u1,
-            /// This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set
-            /// to 1.
-            TXFIFO_EMPTY_INT_ST: u1,
-            /// This is the status bit for parity_err_int_raw when parity_err_int_ena is set to
-            /// 1.
-            PARITY_ERR_INT_ST: u1,
-            /// This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-            FRM_ERR_INT_ST: u1,
-            /// This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to
-            /// 1.
-            RXFIFO_OVF_INT_ST: u1,
-            /// This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-            DSR_CHG_INT_ST: u1,
-            /// This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-            CTS_CHG_INT_ST: u1,
-            /// This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-            BRK_DET_INT_ST: u1,
-            /// This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set
-            /// to 1.
-            RXFIFO_TOUT_INT_ST: u1,
-            /// This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-            SW_XON_INT_ST: u1,
-            /// This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-            SW_XOFF_INT_ST: u1,
-            /// This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to
-            /// 1.
-            GLITCH_DET_INT_ST: u1,
-            /// This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set
-            /// to 1.
-            TX_BRK_DONE_INT_ST: u1,
-            /// This is the stauts bit for tx_brk_idle_done_int_raw when
-            /// tx_brk_idle_done_int_ena is set to 1.
-            TX_BRK_IDLE_DONE_INT_ST: u1,
-            /// This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-            TX_DONE_INT_ST: u1,
-            /// This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is
-            /// set to 1.
-            RS485_PARITY_ERR_INT_ST: u1,
-            /// This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is
-            /// set to 1.
-            RS485_FRM_ERR_INT_ST: u1,
-            /// This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set
-            /// to 1.
-            RS485_CLASH_INT_ST: u1,
-            /// This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is
-            /// set to 1.
-            AT_CMD_CHAR_DET_INT_ST: u1,
-            /// This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set
-            /// to 1.
-            WAKEUP_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6001000c
-        /// Interrupt enable bits
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the enable bit for rxfifo_full_int_st register.
-            RXFIFO_FULL_INT_ENA: u1,
-            /// This is the enable bit for txfifo_empty_int_st register.
-            TXFIFO_EMPTY_INT_ENA: u1,
-            /// This is the enable bit for parity_err_int_st register.
-            PARITY_ERR_INT_ENA: u1,
-            /// This is the enable bit for frm_err_int_st register.
-            FRM_ERR_INT_ENA: u1,
-            /// This is the enable bit for rxfifo_ovf_int_st register.
-            RXFIFO_OVF_INT_ENA: u1,
-            /// This is the enable bit for dsr_chg_int_st register.
-            DSR_CHG_INT_ENA: u1,
-            /// This is the enable bit for cts_chg_int_st register.
-            CTS_CHG_INT_ENA: u1,
-            /// This is the enable bit for brk_det_int_st register.
-            BRK_DET_INT_ENA: u1,
-            /// This is the enable bit for rxfifo_tout_int_st register.
-            RXFIFO_TOUT_INT_ENA: u1,
-            /// This is the enable bit for sw_xon_int_st register.
-            SW_XON_INT_ENA: u1,
-            /// This is the enable bit for sw_xoff_int_st register.
-            SW_XOFF_INT_ENA: u1,
-            /// This is the enable bit for glitch_det_int_st register.
-            GLITCH_DET_INT_ENA: u1,
-            /// This is the enable bit for tx_brk_done_int_st register.
-            TX_BRK_DONE_INT_ENA: u1,
-            /// This is the enable bit for tx_brk_idle_done_int_st register.
-            TX_BRK_IDLE_DONE_INT_ENA: u1,
-            /// This is the enable bit for tx_done_int_st register.
-            TX_DONE_INT_ENA: u1,
-            /// This is the enable bit for rs485_parity_err_int_st register.
-            RS485_PARITY_ERR_INT_ENA: u1,
-            /// This is the enable bit for rs485_parity_err_int_st register.
-            RS485_FRM_ERR_INT_ENA: u1,
-            /// This is the enable bit for rs485_clash_int_st register.
-            RS485_CLASH_INT_ENA: u1,
-            /// This is the enable bit for at_cmd_char_det_int_st register.
-            AT_CMD_CHAR_DET_INT_ENA: u1,
-            /// This is the enable bit for uart_wakeup_int_st register.
-            WAKEUP_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60010010
-        /// Interrupt clear bits
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the rxfifo_full_int_raw interrupt.
-            RXFIFO_FULL_INT_CLR: u1,
-            /// Set this bit to clear txfifo_empty_int_raw interrupt.
-            TXFIFO_EMPTY_INT_CLR: u1,
-            /// Set this bit to clear parity_err_int_raw interrupt.
-            PARITY_ERR_INT_CLR: u1,
-            /// Set this bit to clear frm_err_int_raw interrupt.
-            FRM_ERR_INT_CLR: u1,
-            /// Set this bit to clear rxfifo_ovf_int_raw interrupt.
-            RXFIFO_OVF_INT_CLR: u1,
-            /// Set this bit to clear the dsr_chg_int_raw interrupt.
-            DSR_CHG_INT_CLR: u1,
-            /// Set this bit to clear the cts_chg_int_raw interrupt.
-            CTS_CHG_INT_CLR: u1,
-            /// Set this bit to clear the brk_det_int_raw interrupt.
-            BRK_DET_INT_CLR: u1,
-            /// Set this bit to clear the rxfifo_tout_int_raw interrupt.
-            RXFIFO_TOUT_INT_CLR: u1,
-            /// Set this bit to clear the sw_xon_int_raw interrupt.
-            SW_XON_INT_CLR: u1,
-            /// Set this bit to clear the sw_xoff_int_raw interrupt.
-            SW_XOFF_INT_CLR: u1,
-            /// Set this bit to clear the glitch_det_int_raw interrupt.
-            GLITCH_DET_INT_CLR: u1,
-            /// Set this bit to clear the tx_brk_done_int_raw interrupt..
-            TX_BRK_DONE_INT_CLR: u1,
-            /// Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-            TX_BRK_IDLE_DONE_INT_CLR: u1,
-            /// Set this bit to clear the tx_done_int_raw interrupt.
-            TX_DONE_INT_CLR: u1,
-            /// Set this bit to clear the rs485_parity_err_int_raw interrupt.
-            RS485_PARITY_ERR_INT_CLR: u1,
-            /// Set this bit to clear the rs485_frm_err_int_raw interrupt.
-            RS485_FRM_ERR_INT_CLR: u1,
-            /// Set this bit to clear the rs485_clash_int_raw interrupt.
-            RS485_CLASH_INT_CLR: u1,
-            /// Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-            AT_CMD_CHAR_DET_INT_CLR: u1,
-            /// Set this bit to clear the uart_wakeup_int_raw interrupt.
-            WAKEUP_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60010014
-        /// Clock divider configuration
-        pub const CLKDIV = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The integral part of the frequency divider factor.
-            CLKDIV: u12,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            reserved6: u1,
-            reserved7: u1,
-            /// The decimal part of the frequency divider factor.
-            FRAG: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60010018
-        /// Rx Filter configuration
-        pub const RX_FILT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// when input pulse width is lower than this value, the pulse is ignored.
-            GLITCH_FILT: u8,
-            /// Set this bit to enable Rx signal filter.
-            GLITCH_FILT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6001001c
-        /// UART status register
-        pub const STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Stores the byte number of valid data in Rx-FIFO.
-            RXFIFO_CNT: u10,
-            reserved0: u1,
-            reserved1: u1,
-            reserved2: u1,
-            /// The register represent the level value of the internal uart dsr signal.
-            DSRN: u1,
-            /// This register represent the level value of the internal uart cts signal.
-            CTSN: u1,
-            /// This register represent the level value of the internal uart rxd signal.
-            RXD: u1,
-            /// Stores the byte number of data in Tx-FIFO.
-            TXFIFO_CNT: u10,
-            reserved3: u1,
-            reserved4: u1,
-            reserved5: u1,
-            /// This bit represents the level of the internal uart dtr signal.
-            DTRN: u1,
-            /// This bit represents the level of the internal uart rts signal.
-            RTSN: u1,
-            /// This bit represents the level of the internal uart txd signal.
-            TXD: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60010020
-        /// a
-        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the parity check mode.
-            PARITY: u1,
-            /// Set this bit to enable uart parity check.
-            PARITY_EN: u1,
-            /// This register is used to set the length of data.
-            BIT_NUM: u2,
-            /// This register is used to set the length of stop bit.
-            STOP_BIT_NUM: u2,
-            /// This register is used to configure the software rts signal which is used in
-            /// software flow control.
-            SW_RTS: u1,
-            /// This register is used to configure the software dtr signal which is used in
-            /// software flow control.
-            SW_DTR: u1,
-            /// Set this bit to enbale transmitter to send NULL when the process of sending data
-            /// is done.
-            TXD_BRK: u1,
-            /// Set this bit to enable IrDA loopback mode.
-            IRDA_DPLX: u1,
-            /// This is the start enable bit for IrDA transmitter.
-            IRDA_TX_EN: u1,
-            /// 1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA
-            /// transmitter's 11th bit to 0.
-            IRDA_WCTL: u1,
-            /// Set this bit to invert the level of IrDA transmitter.
-            IRDA_TX_INV: u1,
-            /// Set this bit to invert the level of IrDA receiver.
-            IRDA_RX_INV: u1,
-            /// Set this bit to enable uart loopback test mode.
-            LOOPBACK: u1,
-            /// Set this bit to enable flow control function for transmitter.
-            TX_FLOW_EN: u1,
-            /// Set this bit to enable IrDA protocol.
-            IRDA_EN: u1,
-            /// Set this bit to reset the uart receive-FIFO.
-            RXFIFO_RST: u1,
-            /// Set this bit to reset the uart transmit-FIFO.
-            TXFIFO_RST: u1,
-            /// Set this bit to inverse the level value of uart rxd signal.
-            RXD_INV: u1,
-            /// Set this bit to inverse the level value of uart cts signal.
-            CTS_INV: u1,
-            /// Set this bit to inverse the level value of uart dsr signal.
-            DSR_INV: u1,
-            /// Set this bit to inverse the level value of uart txd signal.
-            TXD_INV: u1,
-            /// Set this bit to inverse the level value of uart rts signal.
-            RTS_INV: u1,
-            /// Set this bit to inverse the level value of uart dtr signal.
-            DTR_INV: u1,
-            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
-            /// writes registers.
-            CLK_EN: u1,
-            /// 1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver
-            /// stores the data even if the received data is wrong.
-            ERR_WR_MASK: u1,
-            /// This is the enable bit for detecting baudrate.
-            AUTOBAUD_EN: u1,
-            /// UART memory clock gate enable signal.
-            MEM_CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60010024
-        /// Configuration register 1
-        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// It will produce rxfifo_full_int interrupt when receiver receives more data than
-            /// this register value.
-            RXFIFO_FULL_THRHD: u9,
-            /// It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is
-            /// less than this register value.
-            TXFIFO_EMPTY_THRHD: u9,
-            /// Disable UART Rx data overflow detect.
-            DIS_RX_DAT_OVF: u1,
-            /// Set this bit to stop accumulating idle_cnt when hardware flow control works.
-            RX_TOUT_FLOW_DIS: u1,
-            /// This is the flow enable bit for UART receiver.
-            RX_FLOW_EN: u1,
-            /// This is the enble bit for uart receiver's timeout function.
-            RX_TOUT_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60010028
-        /// Autobaud minimum low pulse duration register
-        pub const LOWPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the value of the minimum duration time of the low level
-            /// pulse. It is used in baud rate-detect process.
-            MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6001002c
-        /// Autobaud minimum high pulse duration register
-        pub const HIGHPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the value of the maxinum duration time for the high level
-            /// pulse. It is used in baud rate-detect process.
-            MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60010030
-        /// Autobaud edge change count register
-        pub const RXD_CNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the count of rxd edge change. It is used in baud
-            /// rate-detect process.
-            RXD_EDGE_CNT: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60010034
-        /// Software flow-control configuration
-        pub const FLOW_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to enable software flow control. It is used with register sw_xon or
-            /// sw_xoff.
-            SW_FLOW_CON_EN: u1,
-            /// Set this bit to remove flow control char from the received data.
-            XONOFF_DEL: u1,
-            /// Set this bit to enable the transmitter to go on sending data.
-            FORCE_XON: u1,
-            /// Set this bit to stop the transmitter from sending data.
-            FORCE_XOFF: u1,
-            /// Set this bit to send Xon char. It is cleared by hardware automatically.
-            SEND_XON: u1,
-            /// Set this bit to send Xoff char. It is cleared by hardware automatically.
-            SEND_XOFF: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60010038
-        /// Sleep-mode configuration
-        pub const SLEEP_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The uart is activated from light sleeping mode when the input rxd edge changes
-            /// more times than this register value.
-            ACTIVE_THRESHOLD: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6001003c
-        /// Software flow-control character configuration
-        pub const SWFC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// When the data amount in Rx-FIFO is more than this register value with
-            /// uart_sw_flow_con_en set to 1, it will send a Xoff char.
-            XOFF_THRESHOLD: u9,
-            /// This register stores the Xoff flow control char.
-            XOFF_CHAR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60010040
-        /// Software flow-control character configuration
-        pub const SWFC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// When the data amount in Rx-FIFO is less than this register value with
-            /// uart_sw_flow_con_en set to 1, it will send a Xon char.
-            XON_THRESHOLD: u9,
-            /// This register stores the Xon flow control char.
-            XON_CHAR: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60010044
-        /// Tx Break character configuration
-        pub const TXBRK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the number of 0 to be sent after the process
-            /// of sending data is done. It is active when txd_brk is set to 1.
-            TX_BRK_NUM: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60010048
-        /// Frame-end idle configuration
-        pub const IDLE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// It will produce frame end signal when receiver takes more time to receive one
-            /// byte data than this register value.
-            RX_IDLE_THRHD: u10,
-            /// This register is used to configure the duration time between transfers.
-            TX_IDLE_NUM: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x6001004c
-        /// RS485 mode configuration
-        pub const RS485_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to choose the rs485 mode.
-            RS485_EN: u1,
-            /// Set this bit to delay the stop bit by 1 bit.
-            DL0_EN: u1,
-            /// Set this bit to delay the stop bit by 1 bit.
-            DL1_EN: u1,
-            /// Set this bit to enable receiver could receive data when the transmitter is
-            /// transmitting data in rs485 mode.
-            RS485TX_RX_EN: u1,
-            /// 1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
-            RS485RXBY_TX_EN: u1,
-            /// This register is used to delay the receiver's internal data signal.
-            RS485_RX_DLY_NUM: u1,
-            /// This register is used to delay the transmitter's internal data signal.
-            RS485_TX_DLY_NUM: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x4c);
-
-        /// address: 0x60010050
-        /// Pre-sequence timing configuration
-        pub const AT_CMD_PRECNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the idle duration time before the first
-            /// at_cmd is received by receiver.
-            PRE_IDLE_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x50);
-
-        /// address: 0x60010054
-        /// Post-sequence timing configuration
-        pub const AT_CMD_POSTCNT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the duration time between the last at_cmd and
-            /// the next data.
-            POST_IDLE_NUM: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x54);
-
-        /// address: 0x60010058
-        /// Timeout configuration
-        pub const AT_CMD_GAPTOUT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the duration time between the at_cmd chars.
-            RX_GAP_TOUT: u16,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x58);
-
-        /// address: 0x6001005c
-        /// AT escape sequence detection configuration
-        pub const AT_CMD_CHAR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the content of at_cmd char.
-            AT_CMD_CHAR: u8,
-            /// This register is used to configure the num of continuous at_cmd chars received
-            /// by receiver.
-            CHAR_NUM: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x5c);
-
-        /// address: 0x60010060
-        /// UART threshold and allocation configuration
-        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            reserved0: u1,
-            /// This register is used to configure the amount of mem allocated for receive-FIFO.
-            /// The default number is 128 bytes.
-            RX_SIZE: u3,
-            /// This register is used to configure the amount of mem allocated for
-            /// transmit-FIFO. The default number is 128 bytes.
-            TX_SIZE: u3,
-            /// This register is used to configure the maximum amount of data that can be
-            /// received when hardware flow control works.
-            RX_FLOW_THRHD: u9,
-            /// This register is used to configure the threshold time that receiver takes to
-            /// receive one byte. The rxfifo_tout_int interrupt will be trigger when the
-            /// receiver takes more time to receive one byte with rx_tout_en set to 1.
-            RX_TOUT_THRHD: u10,
-            /// Set this bit to force power down UART memory.
-            MEM_FORCE_PD: u1,
-            /// Set this bit to force power up UART memory.
-            MEM_FORCE_PU: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x60);
-
-        /// address: 0x60010064
-        /// Tx-FIFO write and read offset address.
-        pub const MEM_TX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the offset address in Tx-FIFO when software writes Tx-FIFO
-            /// via APB.
-            APB_TX_WADDR: u10,
-            reserved0: u1,
-            /// This register stores the offset address in Tx-FIFO when Tx-FSM reads data via
-            /// Tx-FIFO_Ctrl.
-            TX_RADDR: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x64);
-
-        /// address: 0x60010068
-        /// Rx-FIFO write and read offset address.
-        pub const MEM_RX_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the offset address in RX-FIFO when software reads data from
-            /// Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
-            APB_RX_RADDR: u10,
-            reserved0: u1,
-            /// This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes
-            /// Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
-            RX_WADDR: u10,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-        }), base_address + 0x68);
-
-        /// address: 0x6001006c
-        /// UART transmit and receive status.
-        pub const FSM_STATUS = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This is the status register of receiver.
-            ST_URX_OUT: u4,
-            /// This is the status register of transmitter.
-            ST_UTX_OUT: u4,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60010070
-        /// Autobaud high pulse register
-        pub const POSPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the minimal input clock count between two positive edges.
-            /// It is used in boudrate-detect process.
-            POSEDGE_MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60010074
-        /// Autobaud low pulse register
-        pub const NEGPULSE = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register stores the minimal input clock count between two negative edges.
-            /// It is used in boudrate-detect process.
-            NEGEDGE_MIN_CNT: u12,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60010078
-        /// UART core clock configuration
-        pub const CLK_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The denominator of the frequency divider factor.
-            SCLK_DIV_B: u6,
-            /// The numerator of the frequency divider factor.
-            SCLK_DIV_A: u6,
-            /// The integral part of the frequency divider factor.
-            SCLK_DIV_NUM: u8,
-            /// UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
-            SCLK_SEL: u2,
-            /// Set this bit to enable UART Tx/Rx clock.
-            SCLK_EN: u1,
-            /// Write 1 then write 0 to this bit, reset UART Tx/Rx.
-            RST_CORE: u1,
-            /// Set this bit to enable UART Tx clock.
-            TX_SCLK_EN: u1,
-            /// Set this bit to enable UART Rx clock.
-            RX_SCLK_EN: u1,
-            /// Write 1 then write 0 to this bit, reset UART Tx.
-            TX_RST_CORE: u1,
-            /// Write 1 then write 0 to this bit, reset UART Rx.
-            RX_RST_CORE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6001007c
-        /// UART Version register
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x7c);
-
-        /// address: 0x60010080
-        /// UART ID register
-        pub const ID = @intToPtr(*volatile Mmio(32, packed struct {
-            /// This register is used to configure the uart_id.
-            ID: u30,
-            /// This bit used to select synchronize mode. 1: Registers are auto synchronized
-            /// into UART Core clock and UART core should be keep the same with APB clock. 0:
-            /// After configure registers, software needs to write 1 to UART_REG_UPDATE to
-            /// synchronize registers.
-            HIGH_SPEED: u1,
-            /// Software write 1 would synchronize registers into UART Core clock domain and
-            /// would be cleared by hardware after synchronization is done.
-            REG_UPDATE: u1,
-        }), base_address + 0x80);
-    };
-
-    /// Universal Host Controller Interface
-    pub const UHCI0 = struct {
-        pub const base_address = 0x60014000;
-
-        /// address: 0x60014000
-        /// a
-        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Write 1, then write 0 to this bit to reset decode state machine.
-            TX_RST: u1,
-            /// Write 1, then write 0 to this bit to reset encode state machine.
-            RX_RST: u1,
-            /// Set this bit to link up HCI and UART0.
-            UART0_CE: u1,
-            /// Set this bit to link up HCI and UART1.
-            UART1_CE: u1,
-            reserved0: u1,
-            /// Set this bit to separate the data frame using a special char.
-            SEPER_EN: u1,
-            /// Set this bit to encode the data packet with a formatting header.
-            HEAD_EN: u1,
-            /// Set this bit to enable UHCI to receive the 16 bit CRC.
-            CRC_REC_EN: u1,
-            /// If this bit is set to 1, UHCI will end the payload receiving process when UART
-            /// has been in idle state.
-            UART_IDLE_EOF_EN: u1,
-            /// If this bit is set to 1, UHCI decoder receiving payload data is end when the
-            /// receiving byte count has reached the specified value. The value is payload
-            /// length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
-            /// configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI
-            /// decoder receiving payload data is end when 0xc0 is received.
-            LEN_EOF_EN: u1,
-            /// Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC
-            /// to end of the payload.
-            ENCODE_CRC_EN: u1,
-            /// 1'b1: Force clock on for register. 1'b0: Support clock only when application
-            /// writes registers.
-            CLK_EN: u1,
-            /// If this bit is set to 1, UHCI will end payload receive process when NULL frame
-            /// is received by UART.
-            UART_RX_BRK_EOF_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60014004
-        /// a
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_RAW: u1,
-            /// a
-            TX_START_INT_RAW: u1,
-            /// a
-            RX_HUNG_INT_RAW: u1,
-            /// a
-            TX_HUNG_INT_RAW: u1,
-            /// a
-            SEND_S_REG_Q_INT_RAW: u1,
-            /// a
-            SEND_A_REG_Q_INT_RAW: u1,
-            /// This is the interrupt raw bit. Triggered when there are some errors in EOF in
-            /// the
-            OUT_EOF_INT_RAW: u1,
-            /// Soft control int raw bit.
-            APP_CTRL0_INT_RAW: u1,
-            /// Soft control int raw bit.
-            APP_CTRL1_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60014008
-        /// a
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_ST: u1,
-            /// a
-            TX_START_INT_ST: u1,
-            /// a
-            RX_HUNG_INT_ST: u1,
-            /// a
-            TX_HUNG_INT_ST: u1,
-            /// a
-            SEND_S_REG_Q_INT_ST: u1,
-            /// a
-            SEND_A_REG_Q_INT_ST: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_ST: u1,
-            /// a
-            APP_CTRL0_INT_ST: u1,
-            /// a
-            APP_CTRL1_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6001400c
-        /// a
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_ENA: u1,
-            /// a
-            TX_START_INT_ENA: u1,
-            /// a
-            RX_HUNG_INT_ENA: u1,
-            /// a
-            TX_HUNG_INT_ENA: u1,
-            /// a
-            SEND_S_REG_Q_INT_ENA: u1,
-            /// a
-            SEND_A_REG_Q_INT_ENA: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_ENA: u1,
-            /// a
-            APP_CTRL0_INT_ENA: u1,
-            /// a
-            APP_CTRL1_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60014010
-        /// a
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_CLR: u1,
-            /// a
-            TX_START_INT_CLR: u1,
-            /// a
-            RX_HUNG_INT_CLR: u1,
-            /// a
-            TX_HUNG_INT_CLR: u1,
-            /// a
-            SEND_S_REG_Q_INT_CLR: u1,
-            /// a
-            SEND_A_REG_Q_INT_CLR: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_CLR: u1,
-            /// a
-            APP_CTRL0_INT_CLR: u1,
-            /// a
-            APP_CTRL1_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60014014
-        /// a
-        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            CHECK_SUM_EN: u1,
-            /// a
-            CHECK_SEQ_EN: u1,
-            /// a
-            CRC_DISABLE: u1,
-            /// a
-            SAVE_HEAD: u1,
-            /// a
-            TX_CHECK_SUM_RE: u1,
-            /// a
-            TX_ACK_NUM_RE: u1,
-            reserved0: u1,
-            /// a
-            WAIT_SW_START: u1,
-            /// a
-            SW_START: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60014018
-        /// a
-        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_ERR_CAUSE: u3,
-            /// a
-            DECODE_STATE: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6001401c
-        /// a
-        pub const STATE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ENCODE_STATE: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60014020
-        /// a
-        pub const ESCAPE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            TX_C0_ESC_EN: u1,
-            /// a
-            TX_DB_ESC_EN: u1,
-            /// a
-            TX_11_ESC_EN: u1,
-            /// a
-            TX_13_ESC_EN: u1,
-            /// a
-            RX_C0_ESC_EN: u1,
-            /// a
-            RX_DB_ESC_EN: u1,
-            /// a
-            RX_11_ESC_EN: u1,
-            /// a
-            RX_13_ESC_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60014024
-        /// a
-        pub const HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            TXFIFO_TIMEOUT: u8,
-            /// a
-            TXFIFO_TIMEOUT_SHIFT: u3,
-            /// a
-            TXFIFO_TIMEOUT_ENA: u1,
-            /// a
-            RXFIFO_TIMEOUT: u8,
-            /// a
-            RXFIFO_TIMEOUT_SHIFT: u3,
-            /// a
-            RXFIFO_TIMEOUT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60014028
-        /// a
-        pub const ACK_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ACK_NUM: u3,
-            /// a
-            LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6001402c
-        /// a
-        pub const RX_HEAD = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x60014030
-        /// a
-        pub const QUICK_SENT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SINGLE_SEND_NUM: u3,
-            /// a
-            SINGLE_SEND_EN: u1,
-            /// a
-            ALWAYS_SEND_NUM: u3,
-            /// a
-            ALWAYS_SEND_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60014034
-        /// a
-        pub const REG_Q0_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q0_WORD0: u32,
-        }), base_address + 0x34);
-
-        /// address: 0x60014038
-        /// a
-        pub const REG_Q0_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q0_WORD1: u32,
-        }), base_address + 0x38);
-
-        /// address: 0x6001403c
-        /// a
-        pub const REG_Q1_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q1_WORD0: u32,
-        }), base_address + 0x3c);
-
-        /// address: 0x60014040
-        /// a
-        pub const REG_Q1_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q1_WORD1: u32,
-        }), base_address + 0x40);
-
-        /// address: 0x60014044
-        /// a
-        pub const REG_Q2_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q2_WORD0: u32,
-        }), base_address + 0x44);
-
-        /// address: 0x60014048
-        /// a
-        pub const REG_Q2_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q2_WORD1: u32,
-        }), base_address + 0x48);
-
-        /// address: 0x6001404c
-        /// a
-        pub const REG_Q3_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q3_WORD0: u32,
-        }), base_address + 0x4c);
-
-        /// address: 0x60014050
-        /// a
-        pub const REG_Q3_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q3_WORD1: u32,
-        }), base_address + 0x50);
-
-        /// address: 0x60014054
-        /// a
-        pub const REG_Q4_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q4_WORD0: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x60014058
-        /// a
-        pub const REG_Q4_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q4_WORD1: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6001405c
-        /// a
-        pub const REG_Q5_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q5_WORD0: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x60014060
-        /// a
-        pub const REG_Q5_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q5_WORD1: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x60014064
-        /// a
-        pub const REG_Q6_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q6_WORD0: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x60014068
-        /// a
-        pub const REG_Q6_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q6_WORD1: u32,
-        }), base_address + 0x68);
-
-        /// address: 0x6001406c
-        /// a
-        pub const ESC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEPER_CHAR: u8,
-            /// a
-            SEPER_ESC_CHAR0: u8,
-            /// a
-            SEPER_ESC_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x60014070
-        /// a
-        pub const ESC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ0: u8,
-            /// a
-            ESC_SEQ0_CHAR0: u8,
-            /// a
-            ESC_SEQ0_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x60014074
-        /// a
-        pub const ESC_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ1: u8,
-            /// a
-            ESC_SEQ1_CHAR0: u8,
-            /// a
-            ESC_SEQ1_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x60014078
-        /// a
-        pub const ESC_CONF3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ2: u8,
-            /// a
-            ESC_SEQ2_CHAR0: u8,
-            /// a
-            ESC_SEQ2_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6001407c
-        /// a
-        pub const PKT_THRES = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            PKT_THRS: u13,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x60014080
-        /// a
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
-    };
-
-    /// Universal Host Controller Interface
-    pub const UHCI1 = struct {
-        pub const base_address = 0x6000c000;
-
-        /// address: 0x6000c000
-        /// a
-        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Write 1, then write 0 to this bit to reset decode state machine.
-            TX_RST: u1,
-            /// Write 1, then write 0 to this bit to reset encode state machine.
-            RX_RST: u1,
-            /// Set this bit to link up HCI and UART0.
-            UART0_CE: u1,
-            /// Set this bit to link up HCI and UART1.
-            UART1_CE: u1,
-            reserved0: u1,
-            /// Set this bit to separate the data frame using a special char.
-            SEPER_EN: u1,
-            /// Set this bit to encode the data packet with a formatting header.
-            HEAD_EN: u1,
-            /// Set this bit to enable UHCI to receive the 16 bit CRC.
-            CRC_REC_EN: u1,
-            /// If this bit is set to 1, UHCI will end the payload receiving process when UART
-            /// has been in idle state.
-            UART_IDLE_EOF_EN: u1,
-            /// If this bit is set to 1, UHCI decoder receiving payload data is end when the
-            /// receiving byte count has reached the specified value. The value is payload
-            /// length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is
-            /// configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI
-            /// decoder receiving payload data is end when 0xc0 is received.
-            LEN_EOF_EN: u1,
-            /// Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC
-            /// to end of the payload.
-            ENCODE_CRC_EN: u1,
-            /// 1'b1: Force clock on for register. 1'b0: Support clock only when application
-            /// writes registers.
-            CLK_EN: u1,
-            /// If this bit is set to 1, UHCI will end payload receive process when NULL frame
-            /// is received by UART.
-            UART_RX_BRK_EOF_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x6000c004
-        /// a
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_RAW: u1,
-            /// a
-            TX_START_INT_RAW: u1,
-            /// a
-            RX_HUNG_INT_RAW: u1,
-            /// a
-            TX_HUNG_INT_RAW: u1,
-            /// a
-            SEND_S_REG_Q_INT_RAW: u1,
-            /// a
-            SEND_A_REG_Q_INT_RAW: u1,
-            /// This is the interrupt raw bit. Triggered when there are some errors in EOF in
-            /// the
-            OUT_EOF_INT_RAW: u1,
-            /// Soft control int raw bit.
-            APP_CTRL0_INT_RAW: u1,
-            /// Soft control int raw bit.
-            APP_CTRL1_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x6000c008
-        /// a
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_ST: u1,
-            /// a
-            TX_START_INT_ST: u1,
-            /// a
-            RX_HUNG_INT_ST: u1,
-            /// a
-            TX_HUNG_INT_ST: u1,
-            /// a
-            SEND_S_REG_Q_INT_ST: u1,
-            /// a
-            SEND_A_REG_Q_INT_ST: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_ST: u1,
-            /// a
-            APP_CTRL0_INT_ST: u1,
-            /// a
-            APP_CTRL1_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6000c00c
-        /// a
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_ENA: u1,
-            /// a
-            TX_START_INT_ENA: u1,
-            /// a
-            RX_HUNG_INT_ENA: u1,
-            /// a
-            TX_HUNG_INT_ENA: u1,
-            /// a
-            SEND_S_REG_Q_INT_ENA: u1,
-            /// a
-            SEND_A_REG_Q_INT_ENA: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_ENA: u1,
-            /// a
-            APP_CTRL0_INT_ENA: u1,
-            /// a
-            APP_CTRL1_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x6000c010
-        /// a
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_START_INT_CLR: u1,
-            /// a
-            TX_START_INT_CLR: u1,
-            /// a
-            RX_HUNG_INT_CLR: u1,
-            /// a
-            TX_HUNG_INT_CLR: u1,
-            /// a
-            SEND_S_REG_Q_INT_CLR: u1,
-            /// a
-            SEND_A_REG_Q_INT_CLR: u1,
-            /// a
-            OUTLINK_EOF_ERR_INT_CLR: u1,
-            /// a
-            APP_CTRL0_INT_CLR: u1,
-            /// a
-            APP_CTRL1_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x6000c014
-        /// a
-        pub const CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            CHECK_SUM_EN: u1,
-            /// a
-            CHECK_SEQ_EN: u1,
-            /// a
-            CRC_DISABLE: u1,
-            /// a
-            SAVE_HEAD: u1,
-            /// a
-            TX_CHECK_SUM_RE: u1,
-            /// a
-            TX_ACK_NUM_RE: u1,
-            reserved0: u1,
-            /// a
-            WAIT_SW_START: u1,
-            /// a
-            SW_START: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x6000c018
-        /// a
-        pub const STATE0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            RX_ERR_CAUSE: u3,
-            /// a
-            DECODE_STATE: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6000c01c
-        /// a
-        pub const STATE1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ENCODE_STATE: u3,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x6000c020
-        /// a
-        pub const ESCAPE_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            TX_C0_ESC_EN: u1,
-            /// a
-            TX_DB_ESC_EN: u1,
-            /// a
-            TX_11_ESC_EN: u1,
-            /// a
-            TX_13_ESC_EN: u1,
-            /// a
-            RX_C0_ESC_EN: u1,
-            /// a
-            RX_DB_ESC_EN: u1,
-            /// a
-            RX_11_ESC_EN: u1,
-            /// a
-            RX_13_ESC_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x6000c024
-        /// a
-        pub const HUNG_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            TXFIFO_TIMEOUT: u8,
-            /// a
-            TXFIFO_TIMEOUT_SHIFT: u3,
-            /// a
-            TXFIFO_TIMEOUT_ENA: u1,
-            /// a
-            RXFIFO_TIMEOUT: u8,
-            /// a
-            RXFIFO_TIMEOUT_SHIFT: u3,
-            /// a
-            RXFIFO_TIMEOUT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x6000c028
-        /// a
-        pub const ACK_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ACK_NUM: u3,
-            /// a
-            LOAD: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6000c02c
-        /// a
-        pub const RX_HEAD = @intToPtr(*volatile u32, base_address + 0x2c);
-
-        /// address: 0x6000c030
-        /// a
-        pub const QUICK_SENT = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SINGLE_SEND_NUM: u3,
-            /// a
-            SINGLE_SEND_EN: u1,
-            /// a
-            ALWAYS_SEND_NUM: u3,
-            /// a
-            ALWAYS_SEND_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x6000c034
-        /// a
-        pub const REG_Q0_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q0_WORD0: u32,
-        }), base_address + 0x34);
-
-        /// address: 0x6000c038
-        /// a
-        pub const REG_Q0_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q0_WORD1: u32,
-        }), base_address + 0x38);
-
-        /// address: 0x6000c03c
-        /// a
-        pub const REG_Q1_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q1_WORD0: u32,
-        }), base_address + 0x3c);
-
-        /// address: 0x6000c040
-        /// a
-        pub const REG_Q1_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q1_WORD1: u32,
-        }), base_address + 0x40);
-
-        /// address: 0x6000c044
-        /// a
-        pub const REG_Q2_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q2_WORD0: u32,
-        }), base_address + 0x44);
-
-        /// address: 0x6000c048
-        /// a
-        pub const REG_Q2_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q2_WORD1: u32,
-        }), base_address + 0x48);
-
-        /// address: 0x6000c04c
-        /// a
-        pub const REG_Q3_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q3_WORD0: u32,
-        }), base_address + 0x4c);
-
-        /// address: 0x6000c050
-        /// a
-        pub const REG_Q3_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q3_WORD1: u32,
-        }), base_address + 0x50);
-
-        /// address: 0x6000c054
-        /// a
-        pub const REG_Q4_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q4_WORD0: u32,
-        }), base_address + 0x54);
-
-        /// address: 0x6000c058
-        /// a
-        pub const REG_Q4_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q4_WORD1: u32,
-        }), base_address + 0x58);
-
-        /// address: 0x6000c05c
-        /// a
-        pub const REG_Q5_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q5_WORD0: u32,
-        }), base_address + 0x5c);
-
-        /// address: 0x6000c060
-        /// a
-        pub const REG_Q5_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q5_WORD1: u32,
-        }), base_address + 0x60);
-
-        /// address: 0x6000c064
-        /// a
-        pub const REG_Q6_WORD0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q6_WORD0: u32,
-        }), base_address + 0x64);
-
-        /// address: 0x6000c068
-        /// a
-        pub const REG_Q6_WORD1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEND_Q6_WORD1: u32,
-        }), base_address + 0x68);
-
-        /// address: 0x6000c06c
-        /// a
-        pub const ESC_CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            SEPER_CHAR: u8,
-            /// a
-            SEPER_ESC_CHAR0: u8,
-            /// a
-            SEPER_ESC_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x6c);
-
-        /// address: 0x6000c070
-        /// a
-        pub const ESC_CONF1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ0: u8,
-            /// a
-            ESC_SEQ0_CHAR0: u8,
-            /// a
-            ESC_SEQ0_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x70);
-
-        /// address: 0x6000c074
-        /// a
-        pub const ESC_CONF2 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ1: u8,
-            /// a
-            ESC_SEQ1_CHAR0: u8,
-            /// a
-            ESC_SEQ1_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x74);
-
-        /// address: 0x6000c078
-        /// a
-        pub const ESC_CONF3 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            ESC_SEQ2: u8,
-            /// a
-            ESC_SEQ2_CHAR0: u8,
-            /// a
-            ESC_SEQ2_CHAR1: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-        }), base_address + 0x78);
-
-        /// address: 0x6000c07c
-        /// a
-        pub const PKT_THRES = @intToPtr(*volatile Mmio(32, packed struct {
-            /// a
-            PKT_THRS: u13,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-        }), base_address + 0x7c);
-
-        /// address: 0x6000c080
-        /// a
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
-    };
-
-    /// Full-speed USB Serial/JTAG Controller
-    pub const USB_DEVICE = struct {
-        pub const base_address = 0x60043000;
-
-        /// address: 0x60043000
-        /// USB_DEVICE_EP1_REG.
-        pub const EP1 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Write and read byte data to/from UART Tx/Rx FIFO through this field. When
-            /// USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes)
-            /// into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can
-            /// check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many
-            /// data is received, then read data from UART Rx FIFO.
-            RDWR_BYTE: u8,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-        }), base_address + 0x0);
-
-        /// address: 0x60043004
-        /// USB_DEVICE_EP1_CONF_REG.
-        pub const EP1_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to indicate writing byte data to UART Tx FIFO is done.
-            WR_DONE: u1,
-            /// 1'b1: Indicate UART Tx FIFO is not full and can write data into in. After
-            /// writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is
-            /// read by USB Host.
-            SERIAL_IN_EP_DATA_FREE: u1,
-            /// 1'b1: Indicate there is data in UART Rx FIFO.
-            SERIAL_OUT_EP_DATA_AVAIL: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-        }), base_address + 0x4);
-
-        /// address: 0x60043008
-        /// USB_DEVICE_INT_RAW_REG.
-        pub const INT_RAW = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt bit turns to high level when flush cmd is received for IN
-            /// endpoint 2 of JTAG.
-            JTAG_IN_FLUSH_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when SOF frame is received.
-            SOF_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when Serial Port OUT Endpoint received
-            /// one packet.
-            SERIAL_OUT_RECV_PKT_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
-            SERIAL_IN_EMPTY_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when pid error is detected.
-            PID_ERR_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when CRC5 error is detected.
-            CRC5_ERR_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when CRC16 error is detected.
-            CRC16_ERR_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when stuff error is detected.
-            STUFF_ERR_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when IN token for IN endpoint 1 is
-            /// received.
-            IN_TOKEN_REC_IN_EP1_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when usb bus reset is detected.
-            USB_BUS_RESET_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when OUT endpoint 1 received packet
-            /// with zero palyload.
-            OUT_EP1_ZERO_PAYLOAD_INT_RAW: u1,
-            /// The raw interrupt bit turns to high level when OUT endpoint 2 received packet
-            /// with zero palyload.
-            OUT_EP2_ZERO_PAYLOAD_INT_RAW: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x8);
-
-        /// address: 0x6004300c
-        /// USB_DEVICE_INT_ST_REG.
-        pub const INT_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-            JTAG_IN_FLUSH_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
-            SOF_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT
-            /// interrupt.
-            SERIAL_OUT_RECV_PKT_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-            SERIAL_IN_EMPTY_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
-            PID_ERR_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
-            CRC5_ERR_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
-            CRC16_ERR_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
-            STUFF_ERR_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT
-            /// interrupt.
-            IN_TOKEN_REC_IN_EP1_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-            USB_BUS_RESET_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT
-            /// interrupt.
-            OUT_EP1_ZERO_PAYLOAD_INT_ST: u1,
-            /// The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT
-            /// interrupt.
-            OUT_EP2_ZERO_PAYLOAD_INT_ST: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0xc);
-
-        /// address: 0x60043010
-        /// USB_DEVICE_INT_ENA_REG.
-        pub const INT_ENA = @intToPtr(*volatile Mmio(32, packed struct {
-            /// The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-            JTAG_IN_FLUSH_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
-            SOF_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-            SERIAL_OUT_RECV_PKT_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-            SERIAL_IN_EMPTY_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
-            PID_ERR_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
-            CRC5_ERR_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
-            CRC16_ERR_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
-            STUFF_ERR_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
-            IN_TOKEN_REC_IN_EP1_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-            USB_BUS_RESET_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-            OUT_EP1_ZERO_PAYLOAD_INT_ENA: u1,
-            /// The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-            OUT_EP2_ZERO_PAYLOAD_INT_ENA: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x10);
-
-        /// address: 0x60043014
-        /// USB_DEVICE_INT_CLR_REG.
-        pub const INT_CLR = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-            JTAG_IN_FLUSH_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
-            SOF_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-            SERIAL_OUT_RECV_PKT_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-            SERIAL_IN_EMPTY_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
-            PID_ERR_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
-            CRC5_ERR_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
-            CRC16_ERR_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
-            STUFF_ERR_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
-            IN_TOKEN_REC_IN_EP1_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-            USB_BUS_RESET_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-            OUT_EP1_ZERO_PAYLOAD_INT_CLR: u1,
-            /// Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-            OUT_EP2_ZERO_PAYLOAD_INT_CLR: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-        }), base_address + 0x14);
-
-        /// address: 0x60043018
-        /// USB_DEVICE_CONF0_REG.
-        pub const CONF0 = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Select internal/external PHY
-            PHY_SEL: u1,
-            /// Enable software control USB D+ D- exchange
-            EXCHG_PINS_OVERRIDE: u1,
-            /// USB D+ D- exchange
-            EXCHG_PINS: u1,
-            /// Control single-end input high threshold,1.76V to 2V, step 80mV
-            VREFH: u2,
-            /// Control single-end input low threshold,0.8V to 1.04V, step 80mV
-            VREFL: u2,
-            /// Enable software control input threshold
-            VREF_OVERRIDE: u1,
-            /// Enable software control USB D+ D- pullup pulldown
-            PAD_PULL_OVERRIDE: u1,
-            /// Control USB D+ pull up.
-            DP_PULLUP: u1,
-            /// Control USB D+ pull down.
-            DP_PULLDOWN: u1,
-            /// Control USB D- pull up.
-            DM_PULLUP: u1,
-            /// Control USB D- pull down.
-            DM_PULLDOWN: u1,
-            /// Control pull up value.
-            PULLUP_VALUE: u1,
-            /// Enable USB pad function.
-            USB_PAD_ENABLE: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-        }), base_address + 0x18);
-
-        /// address: 0x6004301c
-        /// USB_DEVICE_TEST_REG.
-        pub const TEST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Enable test of the USB pad
-            ENABLE: u1,
-            /// USB pad oen in test
-            USB_OE: u1,
-            /// USB D+ tx value in test
-            TX_DP: u1,
-            /// USB D- tx value in test
-            TX_DM: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-        }), base_address + 0x1c);
-
-        /// address: 0x60043020
-        /// USB_DEVICE_JFIFO_ST_REG.
-        pub const JFIFO_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// JTAT in fifo counter.
-            IN_FIFO_CNT: u2,
-            /// 1: JTAG in fifo is empty.
-            IN_FIFO_EMPTY: u1,
-            /// 1: JTAG in fifo is full.
-            IN_FIFO_FULL: u1,
-            /// JTAT out fifo counter.
-            OUT_FIFO_CNT: u2,
-            /// 1: JTAG out fifo is empty.
-            OUT_FIFO_EMPTY: u1,
-            /// 1: JTAG out fifo is full.
-            OUT_FIFO_FULL: u1,
-            /// Write 1 to reset JTAG in fifo.
-            IN_FIFO_RESET: u1,
-            /// Write 1 to reset JTAG out fifo.
-            OUT_FIFO_RESET: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-        }), base_address + 0x20);
-
-        /// address: 0x60043024
-        /// USB_DEVICE_FRAM_NUM_REG.
-        pub const FRAM_NUM = @intToPtr(*volatile Mmio(32, packed struct {
-            /// Frame index of received SOF frame.
-            SOF_FRAME_INDEX: u11,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-        }), base_address + 0x24);
-
-        /// address: 0x60043028
-        /// USB_DEVICE_IN_EP0_ST_REG.
-        pub const IN_EP0_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of IN Endpoint 0.
-            IN_EP0_STATE: u2,
-            /// Write data address of IN endpoint 0.
-            IN_EP0_WR_ADDR: u7,
-            /// Read data address of IN endpoint 0.
-            IN_EP0_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x28);
-
-        /// address: 0x6004302c
-        /// USB_DEVICE_IN_EP1_ST_REG.
-        pub const IN_EP1_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of IN Endpoint 1.
-            IN_EP1_STATE: u2,
-            /// Write data address of IN endpoint 1.
-            IN_EP1_WR_ADDR: u7,
-            /// Read data address of IN endpoint 1.
-            IN_EP1_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x2c);
-
-        /// address: 0x60043030
-        /// USB_DEVICE_IN_EP2_ST_REG.
-        pub const IN_EP2_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of IN Endpoint 2.
-            IN_EP2_STATE: u2,
-            /// Write data address of IN endpoint 2.
-            IN_EP2_WR_ADDR: u7,
-            /// Read data address of IN endpoint 2.
-            IN_EP2_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x30);
-
-        /// address: 0x60043034
-        /// USB_DEVICE_IN_EP3_ST_REG.
-        pub const IN_EP3_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of IN Endpoint 3.
-            IN_EP3_STATE: u2,
-            /// Write data address of IN endpoint 3.
-            IN_EP3_WR_ADDR: u7,
-            /// Read data address of IN endpoint 3.
-            IN_EP3_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x34);
-
-        /// address: 0x60043038
-        /// USB_DEVICE_OUT_EP0_ST_REG.
-        pub const OUT_EP0_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of OUT Endpoint 0.
-            OUT_EP0_STATE: u2,
-            /// Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
-            /// detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
-            OUT_EP0_WR_ADDR: u7,
-            /// Read data address of OUT endpoint 0.
-            OUT_EP0_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x38);
-
-        /// address: 0x6004303c
-        /// USB_DEVICE_OUT_EP1_ST_REG.
-        pub const OUT_EP1_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of OUT Endpoint 1.
-            OUT_EP1_STATE: u2,
-            /// Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
-            /// detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
-            OUT_EP1_WR_ADDR: u7,
-            /// Read data address of OUT endpoint 1.
-            OUT_EP1_RD_ADDR: u7,
-            /// Data count in OUT endpoint 1 when one packet is received.
-            OUT_EP1_REC_DATA_CNT: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-        }), base_address + 0x3c);
-
-        /// address: 0x60043040
-        /// USB_DEVICE_OUT_EP2_ST_REG.
-        pub const OUT_EP2_ST = @intToPtr(*volatile Mmio(32, packed struct {
-            /// State of OUT Endpoint 2.
-            OUT_EP2_STATE: u2,
-            /// Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is
-            /// detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
-            OUT_EP2_WR_ADDR: u7,
-            /// Read data address of OUT endpoint 2.
-            OUT_EP2_RD_ADDR: u7,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-        }), base_address + 0x40);
-
-        /// address: 0x60043044
-        /// USB_DEVICE_MISC_CONF_REG.
-        pub const MISC_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1'h1: Force clock on for register. 1'h0: Support clock only when application
-            /// writes registers.
-            CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-            padding30: u1,
-        }), base_address + 0x44);
-
-        /// address: 0x60043048
-        /// USB_DEVICE_MEM_CONF_REG.
-        pub const MEM_CONF = @intToPtr(*volatile Mmio(32, packed struct {
-            /// 1: power down usb memory.
-            USB_MEM_PD: u1,
-            /// 1: Force clock on for usb memory.
-            USB_MEM_CLK_EN: u1,
-            padding0: u1,
-            padding1: u1,
-            padding2: u1,
-            padding3: u1,
-            padding4: u1,
-            padding5: u1,
-            padding6: u1,
-            padding7: u1,
-            padding8: u1,
-            padding9: u1,
-            padding10: u1,
-            padding11: u1,
-            padding12: u1,
-            padding13: u1,
-            padding14: u1,
-            padding15: u1,
-            padding16: u1,
-            padding17: u1,
-            padding18: u1,
-            padding19: u1,
-            padding20: u1,
-            padding21: u1,
-            padding22: u1,
-            padding23: u1,
-            padding24: u1,
-            padding25: u1,
-            padding26: u1,
-            padding27: u1,
-            padding28: u1,
-            padding29: u1,
-        }), base_address + 0x48);
-
-        /// address: 0x60043080
-        /// USB_DEVICE_DATE_REG.
-        pub const DATE = @intToPtr(*volatile u32, base_address + 0x80);
-    };
-
-    /// XTS-AES-128 Flash Encryption
-    pub const XTS_AES = struct {
-        pub const base_address = 0x600cc000;
-
-        /// address: 0x600cc000
-        /// The memory that stores plaintext
-        pub const PLAIN_MEM = @intToPtr(*volatile [16]u8, base_address + 0x0);
-
-        /// address: 0x600cc040
-        /// XTS-AES line-size register
-        pub const LINESIZE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x40);
-
-        /// address: 0x600cc044
-        /// XTS-AES destination register
-        pub const DESTINATION = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x44);
-
-        /// address: 0x600cc048
-        /// XTS-AES physical address register
-        pub const PHYSICAL_ADDRESS = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x48);
-
-        /// address: 0x600cc04c
-        /// XTS-AES trigger register
-        pub const TRIGGER = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x4c);
-
-        /// address: 0x600cc050
-        /// XTS-AES release register
-        pub const RELEASE = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x50);
-
-        /// address: 0x600cc054
-        /// XTS-AES destroy register
-        pub const DESTROY = @intToPtr(*volatile MmioInt(32, u1), base_address + 0x54);
-
-        /// address: 0x600cc058
-        /// XTS-AES status register
-        pub const STATE = @intToPtr(*volatile MmioInt(32, u2), base_address + 0x58);
-
-        /// address: 0x600cc05c
-        /// XTS-AES version control register
-        pub const DATE = @intToPtr(*volatile MmioInt(32, u30), base_address + 0x5c);
-    };
-};
-
-const std = @import("std");
-
-pub fn mmio(addr: usize, comptime size: u8, comptime PackedT: type) *volatile Mmio(size, PackedT) {
-    return @intToPtr(*volatile Mmio(size, PackedT), addr);
-}
-
-pub fn Mmio(comptime size: u8, comptime PackedT: type) type {
-    if ((size % 8) != 0)
-        @compileError("size must be divisible by 8!");
-
-    if (!std.math.isPowerOfTwo(size / 8))
-        @compileError("size must encode a power of two number of bytes!");
-
-    const IntT = std.meta.Int(.unsigned, size);
-
-    if (@sizeOf(PackedT) != (size / 8))
-        @compileError(std.fmt.comptimePrint("IntT and PackedT must have the same size!, they are {} and {} bytes respectively", .{ size / 8, @sizeOf(PackedT) }));
-
-    return extern struct {
-        const Self = @This();
-
-        raw: IntT,
-
-        pub const underlying_type = PackedT;
-
-        pub inline fn read(addr: *volatile Self) PackedT {
-            return @bitCast(PackedT, addr.raw);
-        }
-
-        pub inline fn write(addr: *volatile Self, val: PackedT) void {
-            // This is a workaround for a compiler bug related to miscompilation
-            // If the tmp var is not used, result location will fuck things up
-            var tmp = @bitCast(IntT, val);
-            addr.raw = tmp;
-        }
-
-        pub inline fn modify(addr: *volatile Self, fields: anytype) void {
-            var val = read(addr);
-            inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
-                @field(val, field.name) = @field(fields, field.name);
-            }
-            write(addr, val);
-        }
-
-        pub inline fn toggle(addr: *volatile Self, fields: anytype) void {
-            var val = read(addr);
-            inline for (@typeInfo(@TypeOf(fields)).Struct.fields) |field| {
-                @field(val, @tagName(field.default_value.?)) = !@field(val, @tagName(field.default_value.?));
-            }
-            write(addr, val);
-        }
-    };
-}
-
-pub fn MmioInt(comptime size: u8, comptime T: type) type {
-    return extern struct {
-        const Self = @This();
-
-        raw: std.meta.Int(.unsigned, size),
-
-        pub inline fn read(addr: *volatile Self) T {
-            return @truncate(T, addr.raw);
-        }
-
-        pub inline fn modify(addr: *volatile Self, val: T) void {
-            const Int = std.meta.Int(.unsigned, size);
-            const mask = ~@as(Int, (1 << @bitSizeOf(T)) - 1);
-
-            var tmp = addr.raw;
-            addr.raw = (tmp & mask) | val;
-        }
-    };
-}
-
-pub fn mmioInt(addr: usize, comptime size: usize, comptime T: type) *volatile MmioInt(size, T) {
-    return @intToPtr(*volatile MmioInt(size, T), addr);
-}
-
-pub const InterruptVector = extern union {
-    C: fn () callconv(.C) void,
-    Naked: fn () callconv(.Naked) void,
-    // Interrupt is not supported on arm
-};
-
-const unhandled = InterruptVector{
-    .C = struct {
-        fn tmp() callconv(.C) noreturn {
-            @panic("unhandled interrupt");
-        }
-    }.tmp,
-};

From e92707cc11afea619a41a133515dacaac3d98230 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 19 Mar 2023 16:31:11 -0700
Subject: [PATCH 076/286] update microzig (#7)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 08e7d5b01..6f5b7268f 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725
+Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde

From 78722261cdee6fe5ae1061f2f19e9c4989cf2f89 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 19 Mar 2023 16:31:32 -0700
Subject: [PATCH 077/286] update microzig (#7)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 08e7d5b01..6f5b7268f 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725
+Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde

From 63ea5efd3719edbf92dae57e7ab9896c115de7a0 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 19 Mar 2023 16:31:43 -0700
Subject: [PATCH 078/286] update microzig (#7)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 08e7d5b01..6f5b7268f 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725
+Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde

From 0856b148a32dbb946e977e2d9faf48575beb8cf3 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 19 Mar 2023 16:32:02 -0700
Subject: [PATCH 079/286] update microzig (#7)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 08e7d5b01..6f5b7268f 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725
+Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde

From 0676e6baf31d40b91015d46f7721b5d27fb0e6a6 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 19 Mar 2023 16:32:20 -0700
Subject: [PATCH 080/286] update microzig (#7)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 08e7d5b01..6f5b7268f 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725
+Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde

From bdc5606a387df2c7ee694b1adba3ef6a58df1355 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 19 Mar 2023 16:32:29 -0700
Subject: [PATCH 081/286] update microzig (#7)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 08e7d5b01..6f5b7268f 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725
+Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde

From 3cef64600605de66e36a37ec58cb2053c7314243 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 19 Mar 2023 16:32:34 -0700
Subject: [PATCH 082/286] update microzig (#29)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 08e7d5b01..6f5b7268f 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 08e7d5b01a8ca6a53e3892f763507f1ff3b07725
+Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde

From 3ffa60b2dc5304223f32ac68c5d6ac8059789081 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 22 Mar 2023 00:54:36 -0700
Subject: [PATCH 083/286] update microzig (#8)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 6f5b7268f..dabc9325c 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde
+Subproject commit dabc9325cdee394ff66e28c91803cb814954b157

From 8031b4cf20fcee88104f45592f4cca5698141fe0 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 22 Mar 2023 00:54:47 -0700
Subject: [PATCH 084/286] update microzig (#8)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 6f5b7268f..dabc9325c 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde
+Subproject commit dabc9325cdee394ff66e28c91803cb814954b157

From 04fad531d9b8d45ca73c835fbbd322fc07028617 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 22 Mar 2023 00:54:56 -0700
Subject: [PATCH 085/286] update microzig (#8)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 6f5b7268f..dabc9325c 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde
+Subproject commit dabc9325cdee394ff66e28c91803cb814954b157

From 0524d7e82a4a020a7a0e340a1cea8edf3d1e236e Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 22 Mar 2023 00:55:07 -0700
Subject: [PATCH 086/286] update microzig (#8)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 6f5b7268f..dabc9325c 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde
+Subproject commit dabc9325cdee394ff66e28c91803cb814954b157

From 6b7b7a6ec47d064bbd5ed35269c854c3ca4f9c0f Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 22 Mar 2023 00:55:14 -0700
Subject: [PATCH 087/286] update microzig (#8)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 6f5b7268f..dabc9325c 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde
+Subproject commit dabc9325cdee394ff66e28c91803cb814954b157

From 9b577faacf1e8de67943b6c82d4d1fb8ac0efeed Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 22 Mar 2023 00:56:23 -0700
Subject: [PATCH 088/286] update microzig (#8)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 6f5b7268f..dabc9325c 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde
+Subproject commit dabc9325cdee394ff66e28c91803cb814954b157

From 160bee73e0774ecf44e2d6a0f8494f48b0c8d0f2 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 22 Mar 2023 00:56:30 -0700
Subject: [PATCH 089/286] update microzig (#30)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 6f5b7268f..dabc9325c 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 6f5b7268f68f001144bd5ebacc0c0203a7a50fde
+Subproject commit dabc9325cdee394ff66e28c91803cb814954b157

From 808209091c4c654ac7787ac05dad85371d7ed3a9 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:27:18 -0700
Subject: [PATCH 090/286] Update microzig (#9)

* update microzig

* add zig version

---------

Co-authored-by: mattnite 
---
 README.adoc   | 4 ++++
 deps/microzig | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/README.adoc b/README.adoc
index fdee92cc1..ae26554f0 100644
--- a/README.adoc
+++ b/README.adoc
@@ -2,6 +2,10 @@
 
 HALs and register definitions for stm32 (STMicro) devices
 
+== What version of Zig to use
+
+Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+
 == stm32 boards that renode supports:
 
 - blue pill (stm32f103)
diff --git a/deps/microzig b/deps/microzig
index dabc9325c..5b0176e97 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dabc9325cdee394ff66e28c91803cb814954b157
+Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5

From 6850cf21de558cdb167c2b2461b495f40c5b2a44 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:27:31 -0700
Subject: [PATCH 091/286] Update microzig (#9)

* update microzig

* add zig version

---------

Co-authored-by: mattnite 
---
 README.adoc   | 4 ++++
 deps/microzig | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/README.adoc b/README.adoc
index 6e0fc7d9c..394015ff4 100644
--- a/README.adoc
+++ b/README.adoc
@@ -1,3 +1,7 @@
 = NXP LPC Hardware Support Package
 
 Please see https://github.com/ZigEmbeddedGroup/lpcboot[lpcboot] as well
+
+== What version of Zig to use
+
+Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
diff --git a/deps/microzig b/deps/microzig
index dabc9325c..5b0176e97 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dabc9325cdee394ff66e28c91803cb814954b157
+Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5

From 66fd9718330b4075d94d83ade1ffa774ada568c1 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:27:44 -0700
Subject: [PATCH 092/286] Update microzig (#9)

* update microzig

* add zig version

---------

Co-authored-by: mattnite 
---
 README.adoc   | 4 ++++
 deps/microzig | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/README.adoc b/README.adoc
index 65801a9ae..9bf6631a3 100644
--- a/README.adoc
+++ b/README.adoc
@@ -3,3 +3,7 @@
 [WIP]
 
 SVD is copied from https://github.com/esp-rs/esp-pacs
+
+== What version of Zig to use
+
+Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
diff --git a/deps/microzig b/deps/microzig
index dabc9325c..5b0176e97 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dabc9325cdee394ff66e28c91803cb814954b157
+Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5

From 7c781dc37730b448d78f5621b965b74bc3112680 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:28:01 -0700
Subject: [PATCH 093/286] Update microzig (#31)

* update microzig

* add zig version

---------

Co-authored-by: mattnite 
---
 README.adoc   | 7 +++++++
 deps/microzig | 2 +-
 2 files changed, 8 insertions(+), 1 deletion(-)
 create mode 100644 README.adoc

diff --git a/README.adoc b/README.adoc
new file mode 100644
index 000000000..171c62d0a
--- /dev/null
+++ b/README.adoc
@@ -0,0 +1,7 @@
+= raspberrypi-rp2040
+
+HAL and register definitions for the RP2040.
+
+== What version of Zig to use
+
+Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
diff --git a/deps/microzig b/deps/microzig
index dabc9325c..5b0176e97 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dabc9325cdee394ff66e28c91803cb814954b157
+Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5

From 14239a66fa3eda789eadb24e8ea7390fe07bd383 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:28:11 -0700
Subject: [PATCH 094/286] Update microzig (#9)

* update microzig

* add zig version

---------

Co-authored-by: mattnite 
---
 README.adoc   | 4 ++++
 deps/microzig | 2 +-
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/README.adoc b/README.adoc
index 0a66afd4e..9bef0932f 100644
--- a/README.adoc
+++ b/README.adoc
@@ -2,6 +2,10 @@
 
 HALs and register definitions for nrf5x devices
 
+== What version of Zig to use
+
+Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+
 == Renode supports:
 
 - nrf52840 development kit
diff --git a/deps/microzig b/deps/microzig
index dabc9325c..5b0176e97 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dabc9325cdee394ff66e28c91803cb814954b157
+Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5

From 215711d807f5a983a660ff3adefbe49e38ae9acd Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:28:29 -0700
Subject: [PATCH 095/286] Update microzig (#9)

* update microzig

* add zig version

---------

Co-authored-by: mattnite 
---
 README.adoc   | 5 +++++
 deps/microzig | 2 +-
 2 files changed, 6 insertions(+), 1 deletion(-)

diff --git a/README.adoc b/README.adoc
index f23b1bfb8..daa2bccc5 100644
--- a/README.adoc
+++ b/README.adoc
@@ -1 +1,6 @@
 = GigaDevice GD32 Hardware Support Package
+
+== What version of Zig to use
+
+Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+
diff --git a/deps/microzig b/deps/microzig
index dabc9325c..5b0176e97 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dabc9325cdee394ff66e28c91803cb814954b157
+Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5

From c0c93c89462565db9ab33f08918253a613759f4a Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:28:49 -0700
Subject: [PATCH 096/286] Update microzig (#9)

* update microzig

* add zig version

---------

Co-authored-by: mattnite 
---
 README.adoc   | 6 ++++++
 deps/microzig | 2 +-
 2 files changed, 7 insertions(+), 1 deletion(-)

diff --git a/README.adoc b/README.adoc
index f4214f4b0..71e604c1f 100644
--- a/README.adoc
+++ b/README.adoc
@@ -2,6 +2,12 @@
 
 Note: for testing, renode supports arduino nano 33 BLE
 
+== What version of Zig to use
+
+Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+
+== FYI: LLVM issues
+
 Currently LLVM is having trouble lowering AVR when this is built in debug mode:
 
 [source]
diff --git a/deps/microzig b/deps/microzig
index dabc9325c..5b0176e97 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dabc9325cdee394ff66e28c91803cb814954b157
+Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5

From fca3d574a6d1ffce1f455249fc49b0eb490b793b Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:39:15 -0700
Subject: [PATCH 097/286] Update microzig (#10)

* update microzig

* fix link

---------

Co-authored-by: mattnite 
---
 README.adoc   | 2 +-
 deps/microzig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.adoc b/README.adoc
index 71e604c1f..3ff88eb09 100644
--- a/README.adoc
+++ b/README.adoc
@@ -4,7 +4,7 @@ Note: for testing, renode supports arduino nano 33 BLE
 
 == What version of Zig to use
 
-Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
 
 == FYI: LLVM issues
 
diff --git a/deps/microzig b/deps/microzig
index 5b0176e97..ceaa9ddcb 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5
+Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e

From 3f5786f9386ab97d837bbf4d5c60dcdb49f0f263 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:42:17 -0700
Subject: [PATCH 098/286] Update microzig (#10)

* update microzig

* fix link

---------

Co-authored-by: mattnite 
---
 README.adoc   | 2 +-
 deps/microzig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.adoc b/README.adoc
index 9bf6631a3..4123f3c9a 100644
--- a/README.adoc
+++ b/README.adoc
@@ -6,4 +6,4 @@ SVD is copied from https://github.com/esp-rs/esp-pacs
 
 == What version of Zig to use
 
-Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
diff --git a/deps/microzig b/deps/microzig
index 5b0176e97..ceaa9ddcb 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5
+Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e

From 422aa77f2ef5ee139d55fb730cf868ad10857fac Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:42:28 -0700
Subject: [PATCH 099/286] Update microzig (#10)

* update microzig

* fix link

---------

Co-authored-by: mattnite 
---
 README.adoc   | 2 +-
 deps/microzig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.adoc b/README.adoc
index ae26554f0..163532031 100644
--- a/README.adoc
+++ b/README.adoc
@@ -4,7 +4,7 @@ HALs and register definitions for stm32 (STMicro) devices
 
 == What version of Zig to use
 
-Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
 
 == stm32 boards that renode supports:
 
diff --git a/deps/microzig b/deps/microzig
index 5b0176e97..ceaa9ddcb 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5
+Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e

From 623a7f24eecad9e5ef0bf3aab50d9671233380eb Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:42:36 -0700
Subject: [PATCH 100/286] update microzig (#32)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 5b0176e97..ceaa9ddcb 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5
+Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e

From bdba656f9baa0bbfafe456a1d150bc35dfad4f05 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:42:47 -0700
Subject: [PATCH 101/286] Update microzig (#10)

* update microzig

* fix link

---------

Co-authored-by: mattnite 
---
 README.adoc   | 2 +-
 deps/microzig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.adoc b/README.adoc
index daa2bccc5..9985edf67 100644
--- a/README.adoc
+++ b/README.adoc
@@ -2,5 +2,5 @@
 
 == What version of Zig to use
 
-Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
 
diff --git a/deps/microzig b/deps/microzig
index 5b0176e97..ceaa9ddcb 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5
+Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e

From 37031c26cb409aa7157aa5a9e43b434b3402f679 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:42:55 -0700
Subject: [PATCH 102/286] Update microzig (#10)

* update microzig

* fix link

---------

Co-authored-by: mattnite 
---
 README.adoc   | 2 +-
 deps/microzig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.adoc b/README.adoc
index 394015ff4..f32fd9780 100644
--- a/README.adoc
+++ b/README.adoc
@@ -4,4 +4,4 @@ Please see https://github.com/ZigEmbeddedGroup/lpcboot[lpcboot] as well
 
 == What version of Zig to use
 
-Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
diff --git a/deps/microzig b/deps/microzig
index 5b0176e97..ceaa9ddcb 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5
+Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e

From ea7bdcb3fbf64b44e3a7bc7dfb7ca0985f43634a Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 23 Mar 2023 08:43:04 -0700
Subject: [PATCH 103/286] Update microzig (#10)

* update microzig

* fix link

---------

Co-authored-by: mattnite 
---
 README.adoc   | 2 +-
 deps/microzig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.adoc b/README.adoc
index 9bef0932f..7c2fa2fb5 100644
--- a/README.adoc
+++ b/README.adoc
@@ -4,7 +4,7 @@ HALs and register definitions for nrf5x devices
 
 == What version of Zig to use
 
-Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
 
 == Renode supports:
 
diff --git a/deps/microzig b/deps/microzig
index 5b0176e97..ceaa9ddcb 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 5b0176e97781a77420be309b6505dc582713a2a5
+Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e

From a4de9d2f3e332d6f49c192b8cbdf96cfb383cd8c Mon Sep 17 00:00:00 2001
From: Vlad Panazan 
Date: Thu, 23 Mar 2023 20:37:48 +0200
Subject: [PATCH 104/286] add SPI hal (#33)

---
 build.zig               |   1 +
 examples/spi_master.zig |  25 +++++++
 src/hal.zig             |   1 +
 src/hal/spi.zig         | 159 ++++++++++++++++++++++++++++++++++++++++
 4 files changed, 186 insertions(+)
 create mode 100644 examples/spi_master.zig
 create mode 100644 src/hal/spi.zig

diff --git a/build.zig b/build.zig
index 5da87f7b7..b1225d22a 100644
--- a/build.zig
+++ b/build.zig
@@ -53,6 +53,7 @@ pub const Examples = struct {
     blinky_core1: *microzig.EmbeddedExecutable,
     gpio_clk: *microzig.EmbeddedExecutable,
     pwm: *microzig.EmbeddedExecutable,
+    spi_master: *microzig.EmbeddedExecutable,
     uart: *microzig.EmbeddedExecutable,
     //uart_pins: microzig.EmbeddedExecutable,
 
diff --git a/examples/spi_master.zig b/examples/spi_master.zig
new file mode 100644
index 000000000..ba1c0c2db
--- /dev/null
+++ b/examples/spi_master.zig
@@ -0,0 +1,25 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const time = rp2040.time;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+const peripherals = microzig.chip.peripherals;
+
+const BUF_LEN = 0x100;
+
+// Communicate with another RP2040 over spi
+// Slave implementation: https://github.com/raspberrypi/pico-examples/blob/master/spi/spi_master_slave/spi_slave/spi_slave.c
+pub fn main() !void {
+    const spi = rp2040.spi.SPI.init(0, .{
+        .clock_config = rp2040.clock_config,
+    });
+    var out_buf: [BUF_LEN]u8 = .{ 0xAA, 0xBB, 0xCC, 0xDD } ** (BUF_LEN / 4);
+    var in_buf: [BUF_LEN]u8 = undefined;
+
+    while (true) {
+        _ = spi.transceive(&out_buf, &in_buf);
+        time.sleep_ms(1 * 1000);
+    }
+}
diff --git a/src/hal.zig b/src/hal.zig
index 21323dedd..568c691e4 100644
--- a/src/hal.zig
+++ b/src/hal.zig
@@ -9,6 +9,7 @@ pub const multicore = @import("hal/multicore.zig");
 pub const time = @import("hal/time.zig");
 pub const uart = @import("hal/uart.zig");
 pub const pwm = @import("hal/pwm.zig");
+pub const spi = @import("hal/spi.zig");
 pub const resets = @import("hal/resets.zig");
 pub const irq = @import("hal/irq.zig");
 
diff --git a/src/hal/spi.zig b/src/hal/spi.zig
new file mode 100644
index 000000000..ea96f4099
--- /dev/null
+++ b/src/hal/spi.zig
@@ -0,0 +1,159 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+const SPI0 = peripherals.SPI0;
+const SPI1 = peripherals.SPI1;
+
+const gpio = @import("gpio.zig");
+const clocks = @import("clocks.zig");
+const resets = @import("resets.zig");
+const time = @import("time.zig");
+
+const SpiRegs = microzig.chip.types.peripherals.SPI0;
+
+pub const Config = struct {
+    clock_config: clocks.GlobalConfiguration,
+    tx_pin: ?u32 = 19,
+    rx_pin: ?u32 = 16,
+    sck_pin: ?u32 = 18,
+    csn_pin: ?u32 = 17,
+    baud_rate: u32 = 1000 * 1000,
+};
+
+pub const SPI = enum {
+    spi0,
+    spi1,
+
+    fn get_regs(spi: SPI) *volatile SpiRegs {
+        return switch (spi) {
+            .spi0 => SPI0,
+            .spi1 => SPI1,
+        };
+    }
+
+    pub fn reset(spi: SPI) void {
+        switch (spi) {
+            .spi0 => resets.reset(&.{.spi0}),
+            .spi1 => resets.reset(&.{.spi1}),
+        }
+    }
+
+    pub fn init(comptime id: u32, comptime config: Config) SPI {
+        const spi: SPI = switch (id) {
+            0 => .spi0,
+            1 => .spi1,
+            else => @compileError("there is only spi0 and spi1"),
+        };
+
+        spi.reset();
+
+        const peri_freq = config.clock_config.peri.?.output_freq;
+        _ = spi.set_baudrate(config.baud_rate, peri_freq);
+
+        const spi_regs = spi.get_regs();
+
+        // set fromat
+        spi_regs.SSPCR0.modify(.{
+            .DSS = 0b0111, // 8 bits
+            .SPO = 0,
+            .SPH = 0,
+        });
+
+        // Always enable DREQ signals -- harmless if DMA is not listening
+        spi_regs.SSPDMACR.modify(.{
+            .TXDMAE = 1,
+            .RXDMAE = 1,
+        });
+
+        // Finally enable the SPI
+        spi_regs.SSPCR1.modify(.{
+            .SSE = 1,
+        });
+
+        if (config.tx_pin) |pin| gpio.set_function(pin, .spi);
+        if (config.rx_pin) |pin| gpio.set_function(pin, .spi);
+        if (config.sck_pin) |pin| gpio.set_function(pin, .spi);
+        if (config.csn_pin) |pin| gpio.set_function(pin, .spi);
+
+        return spi;
+    }
+
+    pub fn is_writable(spi: SPI) bool {
+        return spi.get_regs().SSPSR.read().TNF == 1;
+    }
+
+    pub fn is_readable(spi: SPI) bool {
+        return spi.get_regs().SSPSR.read().RNE == 1;
+    }
+    pub fn transceive(spi: SPI, src: []const u8, dst: []u8) usize {
+        const spi_regs = spi.get_regs();
+        std.debug.assert(src.len == dst.len);
+        const fifo_depth = 8;
+        var rx_remaining = dst.len;
+        var tx_remaining = src.len;
+
+        while (rx_remaining > 0 or tx_remaining > 0) {
+            if (tx_remaining > 0 and spi.is_writable() and rx_remaining < tx_remaining + fifo_depth) {
+                spi_regs.SSPDR.write_raw(src[src.len - tx_remaining]);
+                tx_remaining -= 1;
+            }
+            if (rx_remaining > 0 and spi.is_readable()) {
+                const bytes = std.mem.asBytes(&spi_regs.SSPDR.read().DATA);
+                dst[dst.len - rx_remaining] = bytes[0];
+                rx_remaining -= 1;
+            }
+        }
+
+        return src.len;
+    }
+    // Write len bytes directly from src to the SPI, and discard any data received back
+    pub fn write(spi: SPI, src: []const u8) usize {
+        const spi_regs = spi.get_regs();
+        // Write to TX FIFO whilst ignoring RX, then clean up afterward. When RX
+        // is full, PL022 inhibits RX pushes, and sets a sticky flag on
+        // push-on-full, but continues shifting. Safe if SSPIMSC_RORIM is not set.
+        for (src) |s| {
+            while (!spi.is_writable()) {
+                std.log.debug("SPI not writable!", .{});
+            }
+            spi_regs.SSPDR.write_raw(s);
+        }
+        // Drain RX FIFO, then wait for shifting to finish (which may be *after*
+        // TX FIFO drains), then drain RX FIFO again
+        while (spi.is_readable()) {
+            _ = spi_regs.SSPDR.raw;
+        }
+        while (spi.get_regs().SSPSR.read().BSY == 1) {
+            std.log.debug("SPI busy!", .{});
+        }
+        while (spi.is_readable()) {
+            _ = spi_regs.SSPDR.raw;
+        }
+        // Don't leave overrun flag set
+        peripherals.SPI0.SSPICR.modify(.{ .RORIC = 1 });
+        return src.len;
+    }
+
+    fn set_baudrate(spi: SPI, baudrate: u32, freq_in: u32) u64 {
+        const spi_regs = spi.get_regs();
+        // Find smallest prescale value which puts output frequency in range of
+        // post-divide. Prescale is an even number from 2 to 254 inclusive.
+        var prescale: u64 = 2;
+        while (prescale <= 254) : (prescale += 2) {
+            if (freq_in < (prescale + 2) * 256 * baudrate) break;
+        }
+        std.debug.assert(prescale <= 254); //Freq too low
+        // Find largest post-divide which makes output <= baudrate. Post-divide is
+        // an integer in the range 1 to 256 inclusive.
+
+        var postdiv: u64 = 256;
+        while (postdiv > 1) : (postdiv -= 1) {
+            if (freq_in / (prescale * (postdiv - 1)) > baudrate) break;
+        }
+        spi_regs.SSPCPSR.modify(.{ .CPSDVSR = @intCast(u8, prescale) });
+        spi_regs.SSPCR0.modify(.{ .SCR = @intCast(u8, postdiv - 1) });
+
+        // Return the frequency we were able to achieve
+        return freq_in / (prescale * postdiv);
+    }
+};

From 7f8246ea4ccdf91f54922520d9373d59f05e1502 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 5 Apr 2023 17:18:57 -0700
Subject: [PATCH 105/286] update microzig (#11)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ceaa9ddcb..23482a698 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e
+Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7

From 68ebc9a0adb0ab584a9852d93bb7d4cd45bae1c7 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 5 Apr 2023 17:19:06 -0700
Subject: [PATCH 106/286] update microzig (#11)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ceaa9ddcb..23482a698 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e
+Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7

From a548d0ef1391f154f8907e6be3ed64c0939bcd6c Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 5 Apr 2023 17:19:15 -0700
Subject: [PATCH 107/286] update microzig (#11)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ceaa9ddcb..23482a698 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e
+Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7

From 10e700b6e799589ff4a38866fb4c76fb9ca248d3 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 5 Apr 2023 17:19:22 -0700
Subject: [PATCH 108/286] update microzig (#11)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ceaa9ddcb..23482a698 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e
+Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7

From 7df8396558ade478266f3182e7be6f9a3bd466c4 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 5 Apr 2023 17:19:42 -0700
Subject: [PATCH 109/286] update microzig (#11)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ceaa9ddcb..23482a698 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e
+Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7

From 433572081e13b8242f4980c7e1ddd21f4e61431c Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 5 Apr 2023 17:19:49 -0700
Subject: [PATCH 110/286] update microzig (#11)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ceaa9ddcb..23482a698 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e
+Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7

From f250134e2f0a142c26a0e34a95ed4a5140790312 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 5 Apr 2023 17:20:16 -0700
Subject: [PATCH 111/286] update microzig (#34)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ceaa9ddcb..23482a698 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e
+Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7

From 20e4c9f8f631d6525d40644142abd0ea773a8a0f Mon Sep 17 00:00:00 2001
From: David Sugar 
Date: Thu, 6 Apr 2023 02:29:08 +0200
Subject: [PATCH 112/286] Flash from user code (#35)

* support for a subset of the bootrom functions added: fast bit count/ manipulation functions (tested), fast bulk memory fill/ copy functions (tested), flash access functions (NOT tested), debugging support functions (not implemented), miscellaneous functions (not implemented).

* added support for erasing and programming flash from user code. between the first and last call in a programming sequence, the SSI is not in a state where it can handle XIP accesses, so the code that calls the intervening functions must be located in SRAM. this is why I added the time_critical section to rp2040.ld (maybe one should create a dedicated section in ram that is rwx and keep data rwNx).

* flash_program.zig example added
---
 build.zig                  |   1 +
 examples/flash_program.zig |  82 +++++++++++
 rp2040.ld                  |   3 +-
 src/hal.zig                |   2 +
 src/hal/flash.zig          |  81 +++++++++++
 src/hal/rom.zig            | 269 +++++++++++++++++++++++++++++++++++++
 6 files changed, 437 insertions(+), 1 deletion(-)
 create mode 100644 examples/flash_program.zig
 create mode 100644 src/hal/flash.zig
 create mode 100644 src/hal/rom.zig

diff --git a/build.zig b/build.zig
index b1225d22a..5144b3642 100644
--- a/build.zig
+++ b/build.zig
@@ -56,6 +56,7 @@ pub const Examples = struct {
     spi_master: *microzig.EmbeddedExecutable,
     uart: *microzig.EmbeddedExecutable,
     //uart_pins: microzig.EmbeddedExecutable,
+    flash_program: *microzig.EmbeddedExecutable,
 
     pub fn init(b: *Builder, optimize: std.builtin.OptimizeMode) Examples {
         var ret: Examples = undefined;
diff --git a/examples/flash_program.zig b/examples/flash_program.zig
new file mode 100644
index 000000000..2fc5cc097
--- /dev/null
+++ b/examples/flash_program.zig
@@ -0,0 +1,82 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const flash = rp2040.flash;
+const time = rp2040.time;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+
+const led = 25;
+const uart_id = 0;
+const baud_rate = 115200;
+const uart_tx_pin = 0;
+const uart_rx_pin = 1;
+
+const flash_target_offset: u32 = 256 * 1024;
+const flash_target_contents = @intToPtr([*]const u8, rp2040.flash.XIP_BASE + flash_target_offset);
+
+pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
+    std.log.err("panic: {s}", .{message});
+    @breakpoint();
+    while (true) {}
+}
+
+pub const std_options = struct {
+    pub const log_level = .debug;
+    pub const logFn = rp2040.uart.log;
+};
+
+pub fn main() !void {
+    gpio.reset();
+    gpio.init(led);
+    gpio.set_direction(led, .out);
+    gpio.put(led, 1);
+
+    const uart = rp2040.uart.UART.init(uart_id, .{
+        .baud_rate = baud_rate,
+        .tx_pin = uart_tx_pin,
+        .rx_pin = uart_rx_pin,
+        .clock_config = rp2040.clock_config,
+    });
+
+    rp2040.uart.init_logger(uart);
+
+    var data: [flash.PAGE_SIZE]u8 = undefined;
+    var i: usize = 0;
+    var j: u8 = 0;
+    while (i < flash.PAGE_SIZE) : (i += 1) {
+        data[i] = j;
+
+        if (j == 255) j = 0;
+        j += 1;
+    }
+
+    std.log.info("Generate data", .{});
+    std.log.info("data: {s}", .{&data});
+
+    // Note that a whole number of sectors (4096 bytes) must be erased at a time
+    std.log.info("Erasing target region...", .{});
+    flash.range_erase(flash_target_offset, flash.SECTOR_SIZE);
+    std.log.info("Done. Read back target region:", .{});
+    std.log.info("data: {s}", .{flash_target_contents[0..flash.PAGE_SIZE]});
+
+    // Note that a whole number of pages (256 bytes) must be written at a time
+    std.log.info("Programming target region...", .{});
+    flash.range_program(flash_target_offset, &data);
+    std.log.info("Done. Read back target region:", .{});
+    std.log.info("data: {s}", .{flash_target_contents[0..flash.PAGE_SIZE]});
+
+    var mismatch: bool = false;
+    i = 0;
+    while (i < flash.PAGE_SIZE) : (i += 1) {
+        if (data[i] != flash_target_contents[i])
+            mismatch = true;
+    }
+
+    if (mismatch) {
+        std.log.info("Programming failed!", .{});
+    } else {
+        std.log.info("Programming successful!", .{});
+    }
+}
diff --git a/rp2040.ld b/rp2040.ld
index f293543dc..cac0892e9 100644
--- a/rp2040.ld
+++ b/rp2040.ld
@@ -10,7 +10,7 @@ ENTRY(microzig_main);
 MEMORY
 {
   flash0 (rx!w) : ORIGIN = 0x10000000, LENGTH = 0x00200000
-  ram0   (rw!x) : ORIGIN = 0x20000000, LENGTH = 0x00040000
+  ram0   (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
 }
 
 SECTIONS
@@ -43,6 +43,7 @@ SECTIONS
   .data :
   {
      microzig_data_start = .;
+     *(.time_critical*)
      *(.data*)
      microzig_data_end = .;
   } > ram0 AT> flash0
diff --git a/src/hal.zig b/src/hal.zig
index 568c691e4..f8a74d2f8 100644
--- a/src/hal.zig
+++ b/src/hal.zig
@@ -12,6 +12,8 @@ pub const pwm = @import("hal/pwm.zig");
 pub const spi = @import("hal/spi.zig");
 pub const resets = @import("hal/resets.zig");
 pub const irq = @import("hal/irq.zig");
+pub const rom = @import("hal/rom.zig");
+pub const flash = @import("hal/flash.zig");
 
 pub const clock_config = clocks.GlobalConfiguration.init(.{
     .ref = .{ .source = .src_xosc },
diff --git a/src/hal/flash.zig b/src/hal/flash.zig
new file mode 100644
index 000000000..a7404b120
--- /dev/null
+++ b/src/hal/flash.zig
@@ -0,0 +1,81 @@
+const rom = @import("rom.zig");
+
+pub const Command = enum(u8) {
+    block_erase = 0xd8,
+    ruid_cmd = 0x4b,
+};
+
+pub const PAGE_SIZE = 256;
+pub const SECTOR_SIZE = 4096;
+pub const BLOCK_SIZE = 65536;
+
+/// Bus reads to a 16MB memory window start at this address
+pub const XIP_BASE = 0x10000000;
+
+pub const boot2 = struct {
+    /// Size of the second stage bootloader in bytes
+    const BOOT2_SIZE_BYTES = 64;
+
+    /// Buffer for the second stage bootloader
+    var copyout: [BOOT2_SIZE_BYTES]u32 = undefined;
+    var copyout_valid: bool = false;
+
+    /// Copy the 2nd stage bootloader into memory
+    pub fn flash_init() linksection(".time_critical") void {
+        if (copyout_valid) return;
+        const bootloader = @intToPtr([*]u32, XIP_BASE);
+        var i: usize = 0;
+        while (i < BOOT2_SIZE_BYTES) : (i += 1) {
+            copyout[i] = bootloader[i];
+        }
+        copyout_valid = true;
+    }
+
+    pub fn flash_enable_xip() linksection(".time_critical") void {
+        // TODO: use the second stage bootloader instead of cmd_xip
+        //const bootloader: []u32 = copyout[1..];
+
+        //const f = @ptrCast(*fn () void, bootloader.ptr);
+        //f();
+
+        rom.flash_enter_cmd_xip()();
+    }
+};
+
+/// Erase count bytes starting at offset (offset from start of flash)
+///
+/// The offset must be aligned to a 4096-byte sector, and count must
+/// be a multiple of 4096 bytes!
+pub fn range_erase(offset: u32, count: u32) linksection(".time_critical") void {
+    // TODO: add sanity checks, e.g., offset + count < flash size
+
+    boot2.flash_init();
+
+    // TODO: __compiler_memory_barrier
+
+    rom.connect_internal_flash()();
+    rom.flash_exit_xip()();
+    rom.flash_range_erase()(offset, count, BLOCK_SIZE, @enumToInt(Command.block_erase));
+    rom.flash_flush_cache()();
+
+    boot2.flash_enable_xip();
+}
+
+/// Program data to flash starting at offset (offset from the start of flash)
+///
+/// The offset must be aligned to a 256-byte boundary, and the length of data
+/// must be a multiple of 256!
+pub fn range_program(offset: u32, data: []const u8) linksection(".time_critical") void {
+    // TODO: add sanity checks, e.g., offset + count < flash size
+
+    boot2.flash_init();
+
+    // TODO: __compiler_memory_barrier
+
+    rom.connect_internal_flash()();
+    rom.flash_exit_xip()();
+    rom.flash_range_program()(offset, data.ptr, data.len);
+    rom.flash_flush_cache()();
+
+    boot2.flash_enable_xip();
+}
diff --git a/src/hal/rom.zig b/src/hal/rom.zig
new file mode 100644
index 000000000..128c08549
--- /dev/null
+++ b/src/hal/rom.zig
@@ -0,0 +1,269 @@
+//! Access to functions and data in the RP2040 bootrom
+//!
+//! The Bootrom contains a number of public functions that provide useful RP2040 functionality that might be needed in
+//! the absence of any other code on the device, as well as highly optimized versions of certain key functionality that would
+//! otherwise have to take up space in most user binaries.
+//!
+//! The functions include:
+//! 1. Fast Bit Counting / Manipulation Functions
+//! 2. Fast Bulk Memory Fill / Copy Functions
+//! 3. Flash Access Functions
+//! 4. Debugging Support Functions (TODO)
+//! 5. Miscellaneous Functions (TODO)
+
+/// Function codes to lookup public functions that provide useful RP2040 functionality
+pub const Code = enum(u32) {
+    popcount32 = rom_table_code('P', '3'),
+    reverse32 = rom_table_code('R', '3'),
+    clz32 = rom_table_code('L', '3'),
+    ctz32 = rom_table_code('T', '3'),
+    memset = rom_table_code('M', 'S'),
+    memset4 = rom_table_code('S', '4'),
+    memcpy = rom_table_code('M', 'C'),
+    memcpy44 = rom_table_code('C', '4'),
+    reset_usb_boot = rom_table_code('U', 'B'),
+    connect_internal_flash = rom_table_code('I', 'F'),
+    flash_exit_xip = rom_table_code('E', 'X'),
+    flash_range_erase = rom_table_code('R', 'E'),
+    flash_range_program = rom_table_code('R', 'P'),
+    flash_flush_cache = rom_table_code('F', 'C'),
+    flash_enter_cmd_xip = rom_table_code('C', 'X'),
+};
+
+/// Signatures of all public bootrom functions
+pub const signatures = struct {
+    /// Returns the 32 bit pointer into the ROM if found or NULL otherwise
+    const rom_table_lookup = fn (table: *u16, code: u32) *anyopaque;
+    /// Signature for popcount32: Return a count of the number of 1 bits in value
+    const popcount32 = fn (value: u32) u32;
+    /// Signature for reverse32: Return the bits of value in the reverse order
+    const reverse32 = fn (value: u32) u32;
+    /// Signature for clz32: Return the number of consecutive high order 0 bits of value
+    const clz32 = fn (value: u32) u32;
+    /// Signature for ctz32: Return the number of consecutive low order 0 bits of value
+    const ctz32 = fn (value: u32) u32;
+    /// Signature of memset: Sets n bytes start at ptr to the value c and returns ptr
+    const memset = fn (ptr: [*]u8, c: u8, n: u32) [*]u8;
+    /// Signature of memset4: Sets n bytes start at ptr to the value c and returns ptr; must be word (32-bit) aligned!
+    const memset4 = fn (ptr: [*]u32, c: u8, n: u32) [*]u32;
+    /// Signature of memcpy: Copies n bytes starting at src to dest and returns dest. The results are undefined if the regions overlap.
+    const memcpy = fn (dest: [*]u8, src: [*]u8, n: u32) [*]u8;
+    /// Signature of memcpy44: Copies n bytes starting at src to dest and returns dest; must be word (32-bit) aligned!
+    const memcpy44 = fn (dest: [*]u32, src: [*]u32, n: u32) [*]u8;
+    /// Signature of connect_internal_flash: Restore all QSPI pad controls to their default state, and connect the SSI to the QSPI pads
+    const connect_internal_flash = fn () void;
+    /// Signature of flash_exit_xip: First set up the SSI for serial-mode operations, then issue the fixed XIP exit sequence described in
+    /// Section 2.8.1.2. Note that the bootrom code uses the IO forcing logic to drive the CS pin, which must be
+    /// cleared before returning the SSI to XIP mode (e.g. by a call to _flash_flush_cache). This function
+    /// configures the SSI with a fixed SCK clock divisor of /6.
+    const flash_exit_xip = fn () void;
+    /// Signature of flash_range_erase: Erase a count bytes, starting at addr (offset from start of flash). Optionally, pass a block erase command
+    /// e.g. D8h block erase, and the size of the block erased by this command — this function will use the larger
+    /// block erase where possible, for much higher erase speed. addr must be aligned to a 4096-byte sector, and
+    /// count must be a multiple of 4096 bytes.
+    const flash_range_erase = fn (addr: u32, count: usize, block_size: u32, block_cmd: u8) void;
+    /// Signature of flash_range_program: Program data to a range of flash addresses starting at addr (offset from the start of flash) and count bytes
+    /// in size. addr must be aligned to a 256-byte boundary, and count must be a multiple of 256.
+    const flash_range_program = fn (addr: u32, data: [*]const u8, count: usize) void;
+    /// Signature of flash_flush_cache: Flush and enable the XIP cache. Also clears the IO forcing on QSPI CSn, so that the SSI can drive the
+    /// flash chip select as normal.
+    const flash_flush_cache = fn () void;
+    /// Signature of flash_enter_cmd_xip: Configure the SSI to generate a standard 03h serial read command, with 24 address bits, upon each XIP
+    /// access. This is a very slow XIP configuration, but is very widely supported. The debugger calls this
+    /// function after performing a flash erase/programming operation, so that the freshly-programmed code
+    /// and data is visible to the debug host, without having to know exactly what kind of flash device is
+    /// connected.
+    const flash_enter_cmd_xip = fn () void;
+};
+
+/// Return a bootrom lookup code based on two ASCII characters
+///
+/// These codes are uses to lookup data or function addresses in the bootrom
+///
+/// # Parameters
+/// * `c1` - the first character
+/// * `c2` - the second character
+///
+/// # Returns
+///
+/// A 32 bit address pointing into bootrom
+pub fn rom_table_code(c1: u8, c2: u8) u32 {
+    return @intCast(u32, c1) | (@intCast(u32, c2) << 8);
+}
+
+/// Convert a 16 bit pointer stored at the given rom address into a pointer
+///
+/// # Parameters
+/// * `rom_addr` - address of the 16-bit pointer in rom
+///
+/// # Returns
+///
+/// The converted pointer
+pub inline fn rom_hword_as_ptr(rom_addr: u32) *anyopaque {
+    const ptr_to_ptr = @intToPtr(*u16, rom_addr);
+    return @intToPtr(*anyopaque, @intCast(usize, ptr_to_ptr.*));
+}
+
+/// Lookup a bootrom function by code (inline)
+///
+/// # Parameters
+/// * `code` - code of the function (see codes)
+///
+/// # Returns
+///
+/// A anyopaque pointer to the function; must be cast by the caller
+pub inline fn _rom_func_lookup(code: Code) *anyopaque {
+    const rom_table_lookup = @ptrCast(*signatures.rom_table_lookup, rom_hword_as_ptr(0x18));
+    const func_table = @ptrCast(*u16, @alignCast(2, rom_hword_as_ptr(0x14)));
+    return rom_table_lookup(func_table, @enumToInt(code));
+}
+
+/// Lookup a bootrom function by code
+///
+/// # Parameters
+/// * `code` - code of the function (see codes)
+///
+/// # Returns
+///
+/// A anyopaque pointer to the function; must be cast by the caller
+pub fn rom_func_lookup(code: Code) *anyopaque {
+    return _rom_func_lookup(code);
+}
+
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+// Fast Bit Counting / Manipulation Functions (Datasheet p. 135)
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+/// Return a count of the number of 1 bits in value
+pub fn popcount32(value: u32) u32 {
+    const S = struct {
+        var f: ?*signatures.popcount32 = null;
+    };
+
+    if (S.f == null) S.f = @ptrCast(*signatures.popcount32, _rom_func_lookup(Code.popcount32));
+    return S.f.?(value);
+}
+
+/// Return a count of the number of 1 bits in value
+pub fn reverse32(value: u32) u32 {
+    const S = struct {
+        var f: ?*signatures.reverse32 = null;
+    };
+
+    if (S.f == null) S.f = @ptrCast(*signatures.reverse32, _rom_func_lookup(Code.reverse32));
+    return S.f.?(value);
+}
+
+/// Return the number of consecutive high order 0 bits of value
+pub fn clz32(value: u32) u32 {
+    const S = struct {
+        var f: ?*signatures.clz32 = null;
+    };
+
+    if (S.f == null) S.f = @ptrCast(*signatures.clz32, _rom_func_lookup(Code.clz32));
+    return S.f.?(value);
+}
+
+/// Return the number of consecutive low order 0 bits of value
+pub fn ctz32(value: u32) u32 {
+    const S = struct {
+        var f: ?*signatures.ctz32 = null;
+    };
+
+    if (S.f == null) S.f = @ptrCast(*signatures.ctz32, _rom_func_lookup(Code.ctz32));
+    return S.f.?(value);
+}
+
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+// Fast Bulk Memory Fill / Copy Functions (Datasheet p. 136)
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+/// Sets all bytes of dest to the value c and returns ptr
+pub fn memset(dest: []u8, c: u8) []u8 {
+    const S = struct {
+        var f: ?*signatures.memset = null;
+    };
+
+    if (S.f == null) S.f = @ptrCast(*signatures.memset, _rom_func_lookup(Code.memset));
+    return S.f.?(dest.ptr, c, dest.len)[0..dest.len];
+}
+
+/// Copies n bytes from src to dest; The number of bytes copied is the size of the smaller slice
+pub fn memcpy(dest: []u8, src: []u8) []u8 {
+    const S = struct {
+        var f: ?*signatures.memcpy = null;
+    };
+
+    const n = if (dest.len <= src.len) dest.len else src.len;
+
+    if (S.f == null) S.f = @ptrCast(*signatures.memcpy, _rom_func_lookup(Code.memcpy));
+    return S.f.?(dest.ptr, src.ptr, n)[0..n];
+}
+
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+// Flash Access Functions (Datasheet p. 137)
+// ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
+
+/// Restore all QSPI pad controls to their default state, and connect the SSI to the QSPI pads
+pub inline fn connect_internal_flash() *signatures.connect_internal_flash {
+    return @ptrCast(
+        *signatures.connect_internal_flash,
+        _rom_func_lookup(Code.connect_internal_flash),
+    );
+}
+
+/// First set up the SSI for serial-mode operations, then issue the fixed XIP exit
+/// sequence described in Section 2.8.1.2. Note that the bootrom code uses the IO
+/// forcing logic to drive the CS pin, which must be cleared before returning the
+/// SSI to XIP mode (e.g. by a call to _flash_flush_cache). This function configures
+/// the SSI with a fixed SCK clock divisor of /6.
+pub inline fn flash_exit_xip() *signatures.flash_exit_xip {
+    return @ptrCast(
+        *signatures.flash_exit_xip,
+        _rom_func_lookup(Code.flash_exit_xip),
+    );
+}
+
+/// Erase a count bytes, starting at addr (offset from start of flash). Optionally,
+/// pass a block erase command e.g. D8h block erase, and the size of the block
+/// erased by this command — this function will use the larger block erase where
+/// possible, for much higher erase speed. addr must be aligned to a 4096-byte sector,
+/// and count must be a multiple of 4096 bytes.
+pub inline fn flash_range_erase() *signatures.flash_range_erase {
+    return @ptrCast(
+        *signatures.flash_range_erase,
+        _rom_func_lookup(Code.flash_range_erase),
+    );
+}
+
+/// Program data to a range of flash addresses starting at addr (offset from the
+/// start of flash) and count bytes in size. addr must be aligned to a 256-byte
+/// boundary, and the length of data must be a multiple of 256.
+pub inline fn flash_range_program() *signatures.flash_range_program {
+    return @ptrCast(
+        *signatures.flash_range_program,
+        _rom_func_lookup(Code.flash_range_program),
+    );
+}
+
+/// Flush and enable the XIP cache. Also clears the IO forcing on QSPI CSn, so that
+/// the SSI can drive the flash chip select as normal.
+pub inline fn flash_flush_cache() *signatures.flash_flush_cache {
+    return @ptrCast(
+        *signatures.flash_flush_cache,
+        _rom_func_lookup(Code.flash_flush_cache),
+    );
+}
+
+/// Configure the SSI to generate a standard 03h serial read command, with 24 address
+/// bits, upon each XIP access. This is a very slow XIP configuration, but is very
+/// widely supported. The debugger calls this function after performing a flash
+/// erase/programming operation, so that the freshly-programmed code and data is
+/// visible to the debug host, without having to know exactly what kind of flash
+/// device is connected.
+pub inline fn flash_enter_cmd_xip() *signatures.flash_enter_cmd_xip {
+    return @ptrCast(
+        *signatures.flash_enter_cmd_xip,
+        _rom_func_lookup(Code.flash_enter_cmd_xip),
+    );
+}

From 666f444037ebe2920912234c60b359fc122c8f83 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Fri, 7 Apr 2023 09:11:31 -0700
Subject: [PATCH 113/286] Readme fix (#37)

* fix link
---
 .buildkite/pipeline.yml | 2 ++
 README.adoc             | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)
 create mode 100644 .buildkite/pipeline.yml

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
new file mode 100644
index 000000000..b1f338d11
--- /dev/null
+++ b/.buildkite/pipeline.yml
@@ -0,0 +1,2 @@
+steps:
+  - command: zig build
diff --git a/README.adoc b/README.adoc
index 171c62d0a..fc0ca7fe8 100644
--- a/README.adoc
+++ b/README.adoc
@@ -4,4 +4,4 @@ HAL and register definitions for the RP2040.
 
 == What version of Zig to use
 
-Right now we are following [master](https://ziglang.org/download/), but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.

From b0e346608e4abef37302412c5f62c389cd04e5bd Mon Sep 17 00:00:00 2001
From: Vesim 
Date: Sat, 8 Apr 2023 19:22:19 +0200
Subject: [PATCH 114/286] PIO assembler (#25)

* WIP pio assembler

* add comparison tests against the official assembler

* tokenizer passing tests

* add buildkite pipeline

* comparison tests

* assembler now outputting a few programs similar to official

* largely complete

---------

Co-authored-by: Matt Knight 
---
 .buildkite/pipeline.yml                       |    2 +-
 .gitignore                                    |    3 +
 build.zig                                     |   16 +-
 deps/microzig                                 |    2 +-
 examples/squarewave.zig                       |   53 +
 src/hal.zig                                   |    6 +-
 src/hal/gpio.zig                              |    2 +-
 src/hal/hw.zig                                |   11 +
 src/hal/irq.zig                               |    8 +-
 src/hal/pio.zig                               |  358 +++
 src/hal/pio/assembler.zig                     |  140 ++
 src/hal/pio/assembler/Expression.zig          |  706 ++++++
 src/hal/pio/assembler/comparison_tests.zig    |  168 ++
 .../assembler/comparison_tests/README.adoc    |    4 +
 .../assembler/comparison_tests/addition.pio   |   33 +
 .../assembler/comparison_tests/addition.pio.h |   52 +
 .../pio/assembler/comparison_tests/apa102.pio |   89 +
 .../assembler/comparison_tests/apa102.pio.h   |  105 +
 .../pio/assembler/comparison_tests/blink.pio  |   34 +
 .../assembler/comparison_tests/blink.pio.h    |   54 +
 .../comparison_tests/clocked_input.pio        |   51 +
 .../comparison_tests/clocked_input.pio.h      |   64 +
 .../differential_manchester.pio               |  104 +
 .../differential_manchester.pio.h             |  120 +
 .../pio/assembler/comparison_tests/hello.pio  |   34 +
 .../assembler/comparison_tests/hello.pio.h    |   55 +
 .../pio/assembler/comparison_tests/hub75.pio  |  128 ++
 .../assembler/comparison_tests/hub75.pio.h    |  138 ++
 .../pio/assembler/comparison_tests/i2c.pio    |  145 ++
 .../pio/assembler/comparison_tests/i2c.pio.h  |  136 ++
 .../comparison_tests/manchester_encoding.pio  |   94 +
 .../manchester_encoding.pio.h                 |  112 +
 .../comparison_tests/nec_carrier_burst.pio    |   61 +
 .../comparison_tests/nec_carrier_burst.pio.h  |   70 +
 .../comparison_tests/nec_carrier_control.pio  |   79 +
 .../nec_carrier_control.pio.h                 |   73 +
 .../comparison_tests/nec_receive.pio          |   96 +
 .../comparison_tests/nec_receive.pio.h        |   84 +
 .../comparison_tests/pio_serialiser.pio       |   27 +
 .../comparison_tests/pio_serialiser.pio.h     |   50 +
 .../pio/assembler/comparison_tests/pwm.pio    |   31 +
 .../pio/assembler/comparison_tests/pwm.pio.h  |   53 +
 .../comparison_tests/quadrature_encoder.pio   |  165 ++
 .../comparison_tests/quadrature_encoder.pio.h |  116 +
 .../comparison_tests/resistor_dac.pio         |   38 +
 .../comparison_tests/resistor_dac.pio.h       |   57 +
 .../pio/assembler/comparison_tests/spi.pio    |  168 ++
 .../pio/assembler/comparison_tests/spi.pio.h  |  198 ++
 .../assembler/comparison_tests/squarewave.pio |   13 +
 .../comparison_tests/squarewave.pio.h         |   40 +
 .../comparison_tests/squarewave_fast.pio      |   19 +
 .../comparison_tests/squarewave_fast.pio.h    |   39 +
 .../comparison_tests/squarewave_test.pio      |   12 +
 .../comparison_tests/squarewave_wrap.pio      |   19 +
 .../comparison_tests/squarewave_wrap.pio.h    |   39 +
 .../assembler/comparison_tests/st7789_lcd.pio |   57 +
 .../comparison_tests/st7789_lcd.pio.h         |   72 +
 .../assembler/comparison_tests/uart_rx.pio    |   94 +
 .../assembler/comparison_tests/uart_rx.pio.h  |  120 +
 .../assembler/comparison_tests/uart_tx.pio    |   61 +
 .../assembler/comparison_tests/uart_tx.pio.h  |   73 +
 .../pio/assembler/comparison_tests/ws2812.pio |   85 +
 .../assembler/comparison_tests/ws2812.pio.h   |  114 +
 src/hal/pio/assembler/encoder.zig             | 1005 +++++++++
 src/hal/pio/assembler/tokenizer.zig           | 1947 +++++++++++++++++
 65 files changed, 8191 insertions(+), 11 deletions(-)
 create mode 100644 examples/squarewave.zig
 create mode 100644 src/hal/hw.zig
 create mode 100644 src/hal/pio.zig
 create mode 100644 src/hal/pio/assembler.zig
 create mode 100644 src/hal/pio/assembler/Expression.zig
 create mode 100644 src/hal/pio/assembler/comparison_tests.zig
 create mode 100644 src/hal/pio/assembler/comparison_tests/README.adoc
 create mode 100644 src/hal/pio/assembler/comparison_tests/addition.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/addition.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/apa102.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/apa102.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/blink.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/blink.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/clocked_input.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/clocked_input.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/differential_manchester.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/differential_manchester.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/hello.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/hello.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/hub75.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/hub75.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/i2c.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/i2c.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/manchester_encoding.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/manchester_encoding.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/nec_carrier_burst.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/nec_carrier_burst.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/nec_carrier_control.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/nec_carrier_control.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/nec_receive.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/nec_receive.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/pio_serialiser.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/pio_serialiser.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/pwm.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/pwm.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/quadrature_encoder.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/quadrature_encoder.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/resistor_dac.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/resistor_dac.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/spi.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/spi.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/squarewave.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/squarewave.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/squarewave_fast.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/squarewave_fast.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/squarewave_test.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/st7789_lcd.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/st7789_lcd.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/uart_rx.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/uart_rx.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/uart_tx.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/uart_tx.pio.h
 create mode 100644 src/hal/pio/assembler/comparison_tests/ws2812.pio
 create mode 100644 src/hal/pio/assembler/comparison_tests/ws2812.pio.h
 create mode 100644 src/hal/pio/assembler/encoder.zig
 create mode 100644 src/hal/pio/assembler/tokenizer.zig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
index b1f338d11..50f730f18 100644
--- a/.buildkite/pipeline.yml
+++ b/.buildkite/pipeline.yml
@@ -1,2 +1,2 @@
 steps:
-  - command: zig build
+  - command: zig build test
diff --git a/.gitignore b/.gitignore
index 4c82b07c0..c8366d4d8 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,2 +1,5 @@
 zig-cache
 zig-out
+.DS_Store
+.gdbinit
+.lldbinit
diff --git a/build.zig b/build.zig
index 5144b3642..21a91ff64 100644
--- a/build.zig
+++ b/build.zig
@@ -39,8 +39,19 @@ pub fn addPiPicoExecutable(
 // project requires multiple HALs, it accepts microzig as a param
 pub fn build(b: *Builder) !void {
     const optimize = b.standardOptimizeOption(.{});
-    var examples = Examples.init(b, optimize);
-    examples.install();
+    //var examples = Examples.init(b, optimize);
+    //examples.install();
+
+    const pio_tests = b.addTest(.{
+        .root_source_file = .{
+            .path = "src/hal/pio.zig",
+        },
+        .optimize = optimize,
+    });
+    pio_tests.addIncludePath("src/hal/pio/assembler");
+
+    const test_step = b.step("test", "run unit tests");
+    test_step.dependOn(&pio_tests.run().step);
 }
 
 fn root() []const u8 {
@@ -55,6 +66,7 @@ pub const Examples = struct {
     pwm: *microzig.EmbeddedExecutable,
     spi_master: *microzig.EmbeddedExecutable,
     uart: *microzig.EmbeddedExecutable,
+    squarewave: *microzig.EmbeddedExecutable,
     //uart_pins: microzig.EmbeddedExecutable,
     flash_program: *microzig.EmbeddedExecutable,
 
diff --git a/deps/microzig b/deps/microzig
index 23482a698..dabc9325c 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7
+Subproject commit dabc9325cdee394ff66e28c91803cb814954b157
diff --git a/examples/squarewave.zig b/examples/squarewave.zig
new file mode 100644
index 000000000..b320681ed
--- /dev/null
+++ b/examples/squarewave.zig
@@ -0,0 +1,53 @@
+//! Hello world for the PIO module: generating a square wave
+const std = @import("std");
+const microzig = @import("microzig");
+const rp2040 = microzig.hal;
+const gpio = rp2040.gpio;
+const Pio = rp2040.pio.Pio;
+const StateMachine = rp2040.pio.StateMachine;
+
+const squarewave_program = (rp2040.pio.assemble(
+    \\.program squarewave
+    \\    set pindirs, 1   ; Set pin to output
+    \\again:
+    \\    set pins, 1 [1]  ; Drive pin high and then delay for one cycle
+    \\    set pins, 0      ; Drive pin low
+    \\    jmp again        ; Set PC to label `again`
+) catch
+    @panic("failed to assemble program"))
+    .get_program_by_name("squarewave");
+
+pub fn main() void {
+    // Pick one PIO instance arbitrarily. We're also arbitrarily picking state
+    // machine 0 on this PIO instance (the state machines are numbered 0 to 3
+    // inclusive).
+    const pio: Pio = .pio0;
+    const sm: StateMachine = .sm0;
+
+    // Load the assembled program directly into the PIO's instruction memory.
+    // Each PIO instance has a 32-slot instruction memory, which all 4 state
+    // machines can see. The system has write-only access.
+    for (squarewave_program.instructions, 0..) |insn, i|
+        pio.get_instruction_memory()[i] = insn;
+
+    // Configure state machine 0 to run at sysclk/2.5. The state machines can
+    // run as fast as one instruction per clock cycle, but we can scale their
+    // speed down uniformly to meet some precise frequency target, e.g. for a
+    // UART baud rate. This register has 16 integer divisor bits and 8
+    // fractional divisor bits.
+    pio.set_clkdiv_int_frac(sm, 2, 0x80);
+
+    // There are five pin mapping groups (out, in, set, side-set, jmp pin)
+    // which are used by different instructions or in different circumstances.
+    // Here we're just using SET instructions. Configure state machine 0 SETs
+    // to affect GPIO 0 only; then configure GPIO0 to be controlled by PIO0,
+    // as opposed to e.g. the processors.
+    pio.set_out_pins(sm, 0, 1);
+    gpio.set_function(0, .pio0);
+
+    // Set the state machine running. The PIO CTRL register is global within a
+    // PIO instance, so you can start/stop multiple state machines
+    // simultaneously. We're using the register's hardware atomic set alias to
+    // make one bit high without doing a read-modify-write on the register.
+    pio.set_enabled(sm, true);
+}
diff --git a/src/hal.zig b/src/hal.zig
index f8a74d2f8..5813cf947 100644
--- a/src/hal.zig
+++ b/src/hal.zig
@@ -1,5 +1,6 @@
+const std = @import("std");
 const microzig = @import("microzig");
-const regs = microzig.chip.registers;
+const SIO = microzig.chip.peripherals.SIO;
 
 pub const adc = @import("hal/adc.zig");
 pub const pins = @import("hal/pins.zig");
@@ -14,6 +15,7 @@ pub const resets = @import("hal/resets.zig");
 pub const irq = @import("hal/irq.zig");
 pub const rom = @import("hal/rom.zig");
 pub const flash = @import("hal/flash.zig");
+pub const pio = @import("hal/pio.zig");
 
 pub const clock_config = clocks.GlobalConfiguration.init(.{
     .ref = .{ .source = .src_xosc },
@@ -32,5 +34,5 @@ pub fn init() void {
 }
 
 pub fn get_cpu_id() u32 {
-    return regs.SIO.CPUID.*;
+    return SIO.CPUID.*;
 }
diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig
index 1e333b148..c0b6baeee 100644
--- a/src/hal/gpio.zig
+++ b/src/hal/gpio.zig
@@ -87,7 +87,7 @@ pub const PullUpDown = enum {
 
 pub inline fn set_pull(comptime gpio: u32, mode: ?PullUpDown) void {
     const gpio_name = comptime std.fmt.comptimePrint("GPIO{d}", .{gpio});
-    const gpio_regs = @field(PADS_BANK0, gpio_name);
+    const gpio_regs = &@field(PADS_BANK0, gpio_name);
 
     if (mode == null) {
         gpio_regs.modify(.{ .PUE = 0, .PDE = 0 });
diff --git a/src/hal/hw.zig b/src/hal/hw.zig
new file mode 100644
index 000000000..a44aff121
--- /dev/null
+++ b/src/hal/hw.zig
@@ -0,0 +1,11 @@
+pub const Lock = struct {
+    impl: u32,
+
+    pub fn claim() Lock {
+
+    }
+
+    pub fn unlock(lock: Lock) void {
+
+    }
+};
diff --git a/src/hal/irq.zig b/src/hal/irq.zig
index f3502be5b..2ff9a137b 100644
--- a/src/hal/irq.zig
+++ b/src/hal/irq.zig
@@ -1,5 +1,5 @@
 const microzig = @import("microzig");
-const regs = microzig.chip.registers;
+const NVIC = microzig.chip.peripherals.NVIC;
 
 // TODO: the register definitions are improved now, use them instead of raw
 // writes/reads
@@ -10,11 +10,11 @@ fn get_interrupt_mask(comptime interrupt_name: []const u8) u32 {
 }
 pub fn enable(comptime interrupt_name: []const u8) void {
     const mask = comptime get_interrupt_mask(interrupt_name);
-    regs.SCS.NVIC.ICPR.raw = mask;
-    regs.SCS.NVIC.ISER.raw = mask;
+    NVIC.ICPR.raw = mask;
+    NVIC.ISER.raw = mask;
 }
 
 pub fn disable(comptime interrupt_name: []const u8) void {
     const mask = comptime get_interrupt_mask(interrupt_name);
-    regs.SCS.NVIC.ICER.raw = mask;
+    NVIC.ICER.raw = mask;
 }
diff --git a/src/hal/pio.zig b/src/hal/pio.zig
new file mode 100644
index 000000000..e37d713d9
--- /dev/null
+++ b/src/hal/pio.zig
@@ -0,0 +1,358 @@
+//! A PIO instance can load a single `Bytecode`, it has to be loaded into memory
+const std = @import("std");
+
+const microzig = @import("microzig");
+const PIO = microzig.chip.types.peripherals.PIO0;
+const PIO0 = microzig.chip.peripherals.PIO0;
+const PIO1 = microzig.chip.peripherals.PIO1;
+
+const gpio = @import("gpio.zig");
+const assembler = @import("pio/assembler.zig");
+pub const Bytecode = Bytecode;
+pub const Program = assembler.Program;
+pub const assemble = assembler.assemble;
+
+var used_instruction_space: [2]u32 = [_]u32{ 0, 0 };
+var claimed_state_machines: [2]u4 = [_]u4{ 0, 0 };
+
+pub const Join = enum {
+    none,
+    rx,
+    tx,
+};
+
+pub const Status = enum {
+    rx_lessthan,
+    tx_lessthan,
+};
+
+pub const Configuration = struct {
+    pin: u32,
+};
+
+pub const StateMachine = enum(u2) {
+    sm0,
+    sm1,
+    sm2,
+    sm3,
+};
+
+pub const Pio = enum(u1) {
+    pio0 = 0,
+    pio1 = 1,
+
+    fn get_regs(self: Pio) *volatile PIO {
+        return switch (self) {
+            .pio0 => PIO0,
+            .pio1 => PIO1,
+        };
+    }
+
+    pub fn get_instruction_memory(self: Pio) *volatile [32]u32 {
+        const regs = self.get_regs();
+        return @ptrCast(*volatile [32]u32, ®s.INSTR_MEM0);
+    }
+
+    pub fn gpio_init(self: Pio, comptime pin: u5) void {
+        gpio.set_function(pin, switch (self) {
+            .pio0 => .pio0,
+            .pio1 => .pio1,
+        });
+    }
+
+    pub fn load(self: Pio, bytecode: Bytecode) !void {
+        _ = self;
+        _ = bytecode;
+    }
+
+    fn can_add_program_at_offset(self: Pio, program: Program, offset: u5) bool {
+        if (program.origin) |origin|
+            if (origin != offset)
+                return false;
+
+        const used_mask = used_instruction_space[@enumToInt(self)];
+        const program_mask = program.get_mask();
+
+        // We can add the program if the masks don't overlap, if there is
+        // overlap the result of a bitwise AND will have a non-zero result
+        return (used_mask & program_mask) == 0;
+    }
+
+    fn find_offset_for_program(self: Pio, program: Program) !u5 {
+        return if (program.origin) |origin|
+            if (self.can_add_program_at_offset(program, origin))
+                origin
+            else
+                error.NoSpace
+        else for (0..32 - program.isntruction.len) |i| {
+            if (self.can_add_program_at_offset(program, i))
+                break i;
+        } else error.NoSpace;
+    }
+
+    fn add_program_at_offset_unlocked(self: Pio, program: Program, offset: u5) !void {
+        if (!self.can_add_program_at_offset(program, offset))
+            return error.NoSpace;
+
+        const instruction_memory = self.get_instruction_memory();
+        for (program.instructions, offset..) |insn, i|
+            instruction_memory[i] = insn;
+
+        const program_mask = program.get_mask();
+        used_instruction_space[@enumToInt(self)] |= program_mask << offset;
+    }
+
+    /// Public functions will need to lock independently, so only exposing this function for now
+    pub fn add_program(self: Pio, program: Program) !void {
+        // TODO: const lock = hw.Lock.claim()
+        // defer lock.unlock();
+
+        const offset = try self.find_offset_for_program_unlocked();
+        try self.add_program_at_offset(program, offset);
+    }
+
+    pub fn claim_unused_state_machine(self: Pio) !StateMachine {
+        // TODO: const lock = hw.Lock.claim()
+        // defer lock.unlock();
+
+        const claimed_mask = claimed_state_machines[@enumToInt(self)];
+        return for (0..4) |i| {
+            const sm_mask = (@as(u4, 1) << @intCast(u2, i));
+            if (0 == (claimed_mask & sm_mask)) {
+                claimed_state_machines[@enumToInt(self)] |= sm_mask;
+                break @intToEnum(StateMachine, i);
+            }
+        } else error.NoSpace;
+    }
+
+    pub const StateMachineRegs = extern struct {
+        clkdiv: @TypeOf(PIO0.SM0_CLKDIV),
+        execctrl: @TypeOf(PIO0.SM0_EXECCTRL),
+        shiftctrl: @TypeOf(PIO0.SM0_SHIFTCTRL),
+        addr: @TypeOf(PIO0.SM0_ADDR),
+        instr: @TypeOf(PIO0.SM0_INSTR),
+        pinctrl: @TypeOf(PIO0.SM0_PINCTRL),
+    };
+
+    fn get_sm_regs(self: Pio, sm: StateMachine) *volatile StateMachineRegs {
+        const pio_regs = self.get_regs();
+        return switch (sm) {
+            .sm0 => @ptrCast(*volatile StateMachineRegs, &pio_regs.SM0_CLKDIV),
+            .sm1 => @ptrCast(*volatile StateMachineRegs, &pio_regs.SM1_CLKDIV),
+            .sm2 => @ptrCast(*volatile StateMachineRegs, &pio_regs.SM2_CLKDIV),
+            .sm3 => @ptrCast(*volatile StateMachineRegs, &pio_regs.SM3_CLKDIV),
+        };
+    }
+
+    pub fn join_fifo(self: Pio, sm: StateMachine, join: Join) void {
+        const tx: u1 = switch (join) {
+            .tx => 1,
+            .rx => 0,
+            .none => 0,
+        };
+        const rx: u1 = switch (join) {
+            .tx => 0,
+            .rx => 1,
+            .none => 0,
+        };
+
+        const sm_regs = self.get_sm_regs(sm);
+        sm_regs.shiftctrl.modify(.{
+            .FJOIN_TX = tx,
+            .FJOIN_RX = rx,
+        });
+    }
+
+    pub fn set_clkdiv_int_frac(self: Pio, sm: StateMachine, div_int: u16, div_frac: u8) void {
+        if (div_int == 0 and div_frac != 0)
+            @panic("invalid params");
+
+        const sm_regs = self.get_sm_regs(sm);
+        sm_regs.clkdiv.write(.{
+            .INT = div_int,
+            .FRAC = div_frac,
+
+            .reserved8 = 0,
+        });
+    }
+
+    pub fn set_out_shift(self: Pio, sm: StateMachine, args: struct {
+        shift_right: bool,
+        autopull: bool,
+        pull_threshold: u5,
+    }) void {
+        const sm_regs = self.get_sm_regs(sm);
+        sm_regs.shiftctrl.modify(.{
+            .OUT_SHIFTDIR = @boolToInt(args.shift_right),
+            .AUTOPULL = @boolToInt(args.autopull),
+            .PULL_THRESH = args.pull_threshold,
+        });
+    }
+
+    pub fn set_out_pins(self: Pio, sm: StateMachine, base: u5, count: u5) void {
+        const sm_regs = self.get_sm_regs(sm);
+        sm_regs.pinctrl.modify(.{
+            .OUT_BASE = base,
+            .OUT_COUNT = count,
+        });
+    }
+
+    pub fn set_sideset_pins(self: Pio, sm: StateMachine, base: u5) void {
+        const sm_regs = self.get_sm_regs(sm);
+        sm_regs.pinctrl.modify(.{ .SIDESET_BASE = base });
+    }
+
+    pub fn is_tx_fifo_full(self: Pio, sm: StateMachine) bool {
+        const regs = self.get_regs();
+        const txfull = regs.FSTAT.read().TXFULL;
+        return (txfull & (@as(u4, 1) << @enumToInt(sm))) != 0;
+    }
+
+    pub fn get_tx_fifo(self: Pio, sm: StateMachine) *volatile u32 {
+        const regs = self.get_regs();
+        return switch (sm) {
+            .sm0 => ®s.TXF0,
+            .sm1 => ®s.TXF1,
+            .sm2 => ®s.TXF2,
+            .sm3 => ®s.TXF3,
+        };
+    }
+
+    pub fn blocking_write(self: Pio, sm: StateMachine, value: u32) void {
+        while (self.is_tx_fifo_full(sm)) {}
+
+        const fifo_ptr = self.get_tx_fifo(sm);
+        fifo_ptr.* = value;
+    }
+
+    pub fn encode_jmp() void {}
+
+    //static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) {
+    //    valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7);
+    //#if PARAM_ASSERTIONS_ENABLED(PIO_INSTRUCTIONS)
+    //    uint32_t major = _pio_major_instr_bits(instr_bits);
+    //    if (major == pio_instr_bits_in || major == pio_instr_bits_out) {
+    //        assert(arg2 && arg2 <= 32);
+    //    } else {
+    //        assert(arg2 <= 31);
+    //    }
+    //#endif
+    //    return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu);
+    //}
+    //
+    //static inline uint pio_encode_jmp(uint addr) {
+    //    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr);
+    //}
+
+    pub fn set_enabled(self: Pio, sm: StateMachine, enabled: bool) void {
+        const regs = self.get_regs();
+
+        var value = regs.CTRL.read();
+        if (enabled)
+            value.SM_ENABLE |= @as(u4, 1) << @enumToInt(sm)
+        else
+            value.SM_ENABLE &= ~(@as(u4, 1) << @enumToInt(sm));
+
+        regs.CTRL.write(value);
+    }
+
+    pub fn sm_init(self: Pio, sm: StateMachine, initial_pc: u5, config: StateMachineRegs) void {
+        // Halt the machine, set some sensible defaults
+        self.set_enabled(sm, false);
+
+        self.set_config(sm, config);
+        self.clear_fifos(sm);
+
+        // Clear FIFO debug flags
+        //const uint32_t fdebug_sm_mask =
+        //        (1u << PIO_FDEBUG_TXOVER_LSB) |
+        //        (1u << PIO_FDEBUG_RXUNDER_LSB) |
+        //        (1u << PIO_FDEBUG_TXSTALL_LSB) |
+        //        (1u << PIO_FDEBUG_RXSTALL_LSB);
+        //pio->fdebug = fdebug_sm_mask << sm;
+
+        // Finally, clear some internal SM state
+        self.restart(sm);
+        self.clkdiv_restart(sm);
+        self.exec(sm, encode_jmp(initial_pc));
+    }
+
+    // state machine configuration helpers:
+    //
+    // - set_out_pins
+    // - set_set_pins
+    // - set_in_pins
+    // - set_sideset_pins
+    // - set_sideset
+    // - calculate_clkdiv_from_float
+    // - set_clkdiv
+    // - set_wrap
+    // - set_jmp_pin
+    // - set_in_shift
+    // - set_out_shift
+    // - set_fifo_join
+    // - set_out_special
+    // - set_mov_status
+    //
+    // PIO:
+    //
+    // - can_add_program
+    // - add_program_at_offset
+    // - add_program
+    // - remove_program
+    // - clear_instruction_memory
+    // - sm_init
+    // - sm_set_enabled
+    // - sm_mask_enabled
+    // - sm_restart
+    // - restart_sm_mask
+    // - sm_clkdiv_restart
+    // - clkdiv_restart_sm_mask
+    // - enable_sm_mask_in_sync
+    // - set_irq0_source_enabled
+    // - set_irq1_source_enabled
+    // - set_irq0_source_mask_enabled
+    // - set_irq1_source_mask_enabled
+    // - set_irqn_source_enabled
+    // - set_irqn_source_mask_enabled
+    // - interrupt_get
+    // - interrupt_clear
+    // - sm_get_pc
+    // - sm_exec
+    // - sm_is_exec_stalled
+    // - sm_exec_wait_blocking
+    // - sm_set_wrap
+    // - sm_set_out_pins
+    // - sm_set_set_pins
+    // - sm_set_in_pins
+    // - sm_set_sideset_pins
+    // - sm_put
+    // - sm_get
+    // - sm_is_rx_fifo_full
+    // - sm_is_rx_fifo_empty
+    // - sm_is_rx_fifo_level
+    // - sm_is_tx_fifo_full
+    // - sm_is_tx_fifo_empty
+    // - sm_is_tx_fifo_level
+    // - sm_put_blocking
+    // - sm_get_blocking
+    // - sm_drain_tx_fifo
+    // - sm_set_clkdiv_int_frac
+    // - sm_set_clkdiv
+    // - sm_clear_fifos
+    // - sm_set_pins
+    // - sm_set_pins_with_mask
+    // - sm_set_pindirs_with_mask
+    // - sm_set_consecutive_pindirs
+    // - sm_claim
+    // - claim_sm_mask
+    // - sm_unclaim
+    // - claim_unused_sm
+    // - sm_is_claimed
+    //
+};
+
+test "pio" {
+    std.testing.refAllDecls(assembler);
+    //std.testing.refAllDecls(@import("pio/test.zig"));
+}
diff --git a/src/hal/pio/assembler.zig b/src/hal/pio/assembler.zig
new file mode 100644
index 000000000..d3596fd93
--- /dev/null
+++ b/src/hal/pio/assembler.zig
@@ -0,0 +1,140 @@
+const std = @import("std");
+const assert = std.debug.assert;
+
+const tokenizer = @import("assembler/tokenizer.zig");
+const encoder = @import("assembler/encoder.zig");
+
+pub const TokenizeOptions = tokenizer.Options;
+pub const EncodeOptions = encoder.Options;
+
+pub const Define = struct {
+    name: []const u8,
+    value: i64,
+};
+
+pub const Program = struct {
+    name: []const u8,
+    defines: []const Define,
+    instructions: []const u16,
+    origin: ?u5,
+    side_set: ?encoder.SideSet,
+    wrap_target: ?u5,
+    wrap: ?u5,
+
+    pub fn get_mask(program: Program) u32 {
+        return (1 << program.instructions.len) - 1;
+    }
+};
+
+pub const Output = struct {
+    defines: []const Define,
+    programs: []const Program,
+
+    pub fn get_program_by_name(
+        comptime output: Output,
+        comptime name: []const u8,
+    ) Program {
+        return for (output.programs) |program| {
+            if (std.mem.eql(u8, program.name, program))
+                break program;
+        } else @panic(std.fmt.comptimePrint("program '{s}' not found", .{name}));
+    }
+
+    pub fn get_define_by_name(
+        comptime output: Output,
+        comptime name: []const u8,
+    ) u32 {
+        return for (output.defines) |define| {
+            if (std.mem.eql(u8, define.name, define))
+                break define;
+        } else @panic(std.fmt.comptimePrint("define '{s}' not found", .{name}));
+    }
+};
+
+pub const AssembleOptions = struct {
+    tokenize: TokenizeOptions = .{},
+    encode: EncodeOptions = .{},
+};
+
+pub const Diagnostics = struct {
+    message: std.BoundedArray(u8, 256),
+    index: u32,
+
+    pub fn init(index: u32, comptime fmt: []const u8, args: anytype) Diagnostics {
+        var ret = Diagnostics{
+            .message = std.BoundedArray(u8, 256).init(0) catch unreachable,
+            .index = index,
+        };
+
+        ret.message.writer().print(fmt, args) catch unreachable;
+        return ret;
+    }
+};
+
+pub fn assemble_impl(comptime source: []const u8, diags: *?Diagnostics, options: AssembleOptions) !Output {
+    const tokens = try tokenizer.tokenize(source, diags, options.tokenize);
+    const encoder_output = try encoder.encode(tokens.slice(), diags, options.encode);
+    var programs = std.BoundedArray(Program, options.encode.max_programs).init(0) catch unreachable;
+    for (encoder_output.programs.slice()) |bounded|
+        try programs.append(bounded.to_exported_program());
+
+    return Output{
+        .defines = blk: {
+            var tmp = std.BoundedArray(Define, options.encode.max_defines).init(0) catch unreachable;
+            for (encoder_output.global_defines.slice()) |define|
+                tmp.append(.{
+                    .name = define.name,
+                    .value = define.value,
+                }) catch unreachable;
+            break :blk tmp.slice();
+        },
+        .programs = programs.slice(),
+    };
+}
+
+fn format_compile_error(comptime message: []const u8, comptime source: []const u8, comptime index: u32) []const u8 {
+    var line_str: []const u8 = "";
+    var line_num: u32 = 1;
+    var column: u32 = 0;
+    var line_it = std.mem.tokenize(u8, source, "\n\r");
+    while (line_it.next()) |line| : (line_num += 1) {
+        line_str = line_str ++ "\n" ++ line;
+        if (line_it.index > index) {
+            column = line.len - (line_it.index - index);
+            line_str = line;
+            break;
+        }
+    }
+
+    return std.fmt.comptimePrint(
+        \\failed to assemble PIO code:
+        \\
+        \\{s}
+        \\{s}^
+        \\{s}{s}
+        \\
+    , .{
+        line_str,
+        [_]u8{' '} ** column,
+        [_]u8{' '} ** column,
+        message,
+    });
+}
+
+pub fn assemble(comptime source: []const u8, comptime options: AssembleOptions) !Output {
+    var diags: ?Diagnostics = null;
+    return assemble_impl(source, &diags, options) catch |err| if (diags) |d|
+        @compileError(format_compile_error(d.message.slice(), source, d.index))
+    else
+        err;
+}
+
+test "tokenizer and encoder" {
+    std.testing.refAllDecls(tokenizer);
+    std.testing.refAllDecls(@import("assembler/Expression.zig"));
+    std.testing.refAllDecls(encoder);
+}
+
+test "comparison" {
+    //std.testing.refAllDecls(@import("assembler/comparison_tests.zig"));
+}
diff --git a/src/hal/pio/assembler/Expression.zig b/src/hal/pio/assembler/Expression.zig
new file mode 100644
index 000000000..794b5c3b1
--- /dev/null
+++ b/src/hal/pio/assembler/Expression.zig
@@ -0,0 +1,706 @@
+//! Expressions for PIO are weird. The documentation states that an expression,
+//! when used as a "value", requires parenthesis. However the official PIO
+//! assembler allows for defines with a value of `::1` which is an expression.
+//!
+//! Annoyingly, looking at the parser, it seems that it supports a number of
+//! other operations not covered in the documentation.
+ops: BoundedOperations,
+values: BoundedValues,
+
+const std = @import("std");
+const assert = std.debug.assert;
+
+const assembler = @import("../assembler.zig");
+const Diagnostics = assembler.Diagnostics;
+
+const encoder = @import("encoder.zig");
+const DefineWithIndex = encoder.DefineWithIndex;
+
+const Expression = @This();
+const BoundedOperations = std.BoundedArray(OperationWithIndex, 32);
+const BoundedValues = std.BoundedArray(Value, 32);
+
+const Value = struct {
+    str: []const u8,
+    index: u32,
+};
+
+const OperationWithIndex = struct {
+    op: Operation,
+    index: u32,
+};
+
+const call_depth_max = 64;
+
+pub const Operation = enum {
+    add,
+    sub,
+    mul,
+    div,
+    negative,
+    bit_reverse,
+    value,
+    // operations shown in pioasm's parser:
+    // - OR
+    // - AND
+    // - XOR
+
+    pub fn format(
+        op: Operation,
+        comptime fmt: []const u8,
+        options: std.fmt.FormatOptions,
+        writer: anytype,
+    ) !void {
+        _ = fmt;
+        _ = options;
+        try writer.print("{s}", .{switch (op) {
+            .add => "add",
+            .sub => "sub",
+            .mul => "mul",
+            .div => "div",
+            .negative => "neg",
+            .bit_reverse => "rev",
+            .value => "val",
+        }});
+    }
+};
+
+pub fn tokenize(
+    str: []const u8,
+    /// starting index of the expression
+    index: u32,
+    diags: *?Diagnostics,
+) !Expression {
+    var ops = BoundedOperations.init(0) catch unreachable;
+    var values = BoundedValues.init(0) catch unreachable;
+
+    const call_depth: u32 = 0;
+    try recursive_tokenize(call_depth, &ops, &values, str, index, diags);
+    return Expression{
+        .ops = ops,
+        .values = values,
+    };
+}
+
+const TrimResult = struct {
+    str: []const u8,
+    index: u32,
+
+    fn default(str: []const u8) TrimResult {
+        return TrimResult{
+            .str = str,
+            .index = 0,
+        };
+    }
+};
+
+fn trim_outer_parenthesis(str: []const u8) TrimResult {
+    // if the outer characters (not including whitespace) are parenthesis, then include the inside string
+
+    // scan the prefix
+    const start: usize = for (str, 0..) |c, i| {
+        switch (c) {
+            ' ',
+            '\t',
+            => {},
+            '(' => break i + 1,
+            else => return TrimResult.default(str),
+        }
+    } else return TrimResult.default(str);
+
+    const end: usize = blk: {
+        var i = str.len - 1;
+        break :blk while (i > 0) : (i -= 1) {
+            switch (str[i]) {
+                ' ',
+                '\t',
+                => {},
+                ')' => break i,
+                else => return TrimResult.default(str),
+            }
+        } else return TrimResult.default(str);
+    };
+
+    return TrimResult{
+        .str = str[start..end],
+        .index = @intCast(u32, start),
+    };
+}
+
+fn recursive_tokenize(
+    call_depth: u32,
+    ops: *BoundedOperations,
+    values: *BoundedValues,
+    str: []const u8,
+    index: u32,
+    diags: *?Diagnostics,
+) !void {
+    assert(call_depth < call_depth_max);
+    const trim_result = trim_outer_parenthesis(str);
+    const expr_str = trim_result.str;
+    const expr_index = index + trim_result.index;
+
+    var parenthesis_found = false;
+    var depth: u32 = 0;
+    var i = @intCast(i32, expr_str.len - 1);
+    outer: while (i >= 0) : (i -= 1) {
+        const idx = @intCast(u32, i);
+        // TODO: how about if the expression is fully enveloped in parenthesis?
+        switch (expr_str[idx]) {
+            ')' => {
+                depth += 1;
+                parenthesis_found = true;
+                continue :outer;
+            },
+            '(' => {
+                if (depth == 0) {
+                    diags.* = Diagnostics.init(expr_index + idx, "mismatched parenthesis", .{});
+                    return error.MismatchedParenthesis;
+                }
+
+                depth -= 1;
+                parenthesis_found = true;
+                if (depth != 0)
+                    continue :outer;
+            },
+            else => if (depth > 0)
+                continue :outer,
+        }
+
+        const op: Operation = switch (expr_str[idx]) {
+            '+' => .add,
+            // needs context to determine if it's a negative or subtraction
+            '-' => blk: {
+                // it's negative if we have nothing to the left. If an operator
+                // is found to the left we continue
+                const is_negative = (i == 0) or is_negative: {
+                    var j = i - 1;
+                    while (j >= 0) : (j -= 1) {
+                        const jdx = @intCast(u32, j);
+                        switch (expr_str[jdx]) {
+                            ' ', '\t' => continue,
+                            '+', '-', '*', '/' => continue :outer,
+                            else => break :is_negative false,
+                        }
+                    }
+
+                    break :is_negative true;
+                };
+
+                if (is_negative) {
+                    try ops.append(.{
+                        .op = .negative,
+                        .index = expr_index + idx,
+                    });
+                    try recursive_tokenize(call_depth + 1, ops, values, expr_str[idx + 1 ..], expr_index + idx + 1, diags);
+                    return;
+                }
+
+                break :blk .sub;
+            },
+            '*' => .mul,
+            '/' => .div,
+            ':' => {
+                const is_bit_reverse = (i != 0) and expr_str[idx - 1] == ':';
+                if (is_bit_reverse) {
+                    try ops.append(.{
+                        .op = .bit_reverse,
+                        .index = expr_index + idx - 1,
+                    });
+                    try recursive_tokenize(call_depth + 1, ops, values, expr_str[idx + 1 ..], expr_index + idx + 1, diags);
+                    i -= 1;
+                    return;
+                }
+
+                return error.InvalidBitReverse;
+            },
+            else => continue,
+        };
+
+        try ops.append(.{
+            .op = op,
+            .index = expr_index + idx,
+        });
+        try recursive_tokenize(call_depth + 1, ops, values, expr_str[idx + 1 ..], expr_index + idx + 1, diags);
+        try recursive_tokenize(call_depth + 1, ops, values, expr_str[0..idx], expr_index, diags);
+        return;
+    } else if (parenthesis_found) {
+        try recursive_tokenize(call_depth + 1, ops, values, expr_str, expr_index, diags);
+    } else {
+        // if we hit this path, then the full string has been scanned, and no operators
+        const trimmed = std.mem.trim(u8, expr_str, " \t");
+        const value_index = expr_index + @intCast(u32, std.mem.indexOf(u8, expr_str, trimmed).?);
+        try ops.append(.{
+            .op = .value,
+            .index = value_index,
+        });
+
+        try values.append(.{
+            .str = trimmed,
+            .index = value_index,
+        });
+    }
+
+    if (depth != 0) {
+        diags.* = Diagnostics.init(expr_index + @intCast(u32, i), "mismatched parenthesis", .{});
+        return error.MismatchedParenthesis;
+    }
+}
+
+const EvaluatedValue = struct {
+    num: i128,
+    index: u32,
+
+    pub fn format(
+        eval_value: EvaluatedValue,
+        comptime fmt: []const u8,
+        options: std.fmt.FormatOptions,
+        writer: anytype,
+    ) !void {
+        _ = fmt;
+        _ = options;
+        try writer.print("{}", .{eval_value.num});
+    }
+};
+
+pub fn evaluate(
+    self: Expression,
+    define_lists: []const []const DefineWithIndex,
+    diags: *?Diagnostics,
+) !i128 {
+    var values = std.BoundedArray(EvaluatedValue, 32).init(0) catch unreachable;
+    // parse/extract values into numbers
+    for (self.values.slice()) |entry| {
+        const value: EvaluatedValue = if (std.fmt.parseInt(i128, entry.str, 0)) |num| .{
+            .num = num,
+            .index = entry.index,
+        } else |_| blk: {
+            // if it fails, try looking up the strings in definitions
+            for (define_lists) |define_list|
+                for (define_list) |define|
+                    if (std.mem.eql(u8, define.name, entry.str))
+                        break :blk .{
+                            .num = define.value,
+                            .index = define.index,
+                        };
+
+            diags.* = Diagnostics.init(entry.index, "value doesn't parse as an integer, or define not found", .{});
+            return error.UnresolvedValue;
+        };
+
+        try values.append(value);
+    }
+
+    return if (self.ops.len == 1) blk: {
+        assert(self.values.len == 1);
+        assert(self.ops.get(0).op == .value);
+
+        break :blk values.get(0).num;
+    } else blk: {
+        const result = try recursive_evaluate(0, self.ops.slice(), values.slice(), diags);
+        assert(result.consumed.ops == self.ops.len);
+        assert(result.consumed.values == self.values.len);
+        break :blk result.value;
+    };
+}
+
+const RecursiveEvalResult = struct {
+    value: i128,
+    consumed: struct {
+        ops: u32,
+        values: u32,
+    },
+    index: u32,
+};
+
+fn recursive_evaluate(
+    call_depth: u32,
+    owis: []const OperationWithIndex,
+    values: []const EvaluatedValue,
+    diags: *?Diagnostics,
+) !RecursiveEvalResult {
+    assert(call_depth < call_depth_max);
+    assert(owis.len != 0);
+    assert(values.len != 0);
+
+    return switch (owis[0].op) {
+        .value => .{
+            .value = values[0].num,
+            .index = values[0].index,
+            .consumed = .{
+                .ops = 1,
+                .values = 1,
+            },
+        },
+        .negative => .{
+            .value = -values[0].num,
+            .index = values[0].index,
+            .consumed = .{
+                .ops = 2,
+                .values = 1,
+            },
+        },
+        .bit_reverse => blk: {
+            if (values[0].num >= std.math.maxInt(u32) or
+                values[0].num < std.math.minInt(i32))
+            {
+                diags.* = Diagnostics.init(owis[0].index, "Evaluated value does not fit in 32-bits: 0x{x}", .{values[0].num});
+                return error.EvaluatedValueDoesntFit;
+            }
+
+            break :blk .{
+                .value = @bitCast(i128, @bitReverse(@bitCast(u128, values[0].num)) >> (128 - 32)),
+                .index = values[0].index,
+                .consumed = .{
+                    .ops = 2,
+                    .values = 1,
+                },
+            };
+        },
+        .add, .sub, .mul, .div => blk: {
+            const rhs = try recursive_evaluate(call_depth + 1, owis[1..], values, diags);
+            const lhs = try recursive_evaluate(call_depth + 1, owis[1 + rhs.consumed.ops ..], values[rhs.consumed.values..], diags);
+            break :blk .{
+                .consumed = .{
+                    .ops = 1 + lhs.consumed.ops + rhs.consumed.ops,
+                    .values = lhs.consumed.values + rhs.consumed.values,
+                },
+                .index = lhs.index,
+                .value = switch (owis[0].op) {
+                    .add => lhs.value + rhs.value,
+                    .sub => lhs.value - rhs.value,
+                    .mul => lhs.value * rhs.value,
+                    .div => div: {
+                        if (rhs.value == 0) {
+                            diags.* = Diagnostics.init(owis[0].index, "divide by zero (denominator evaluates to zero)", .{});
+                            return error.DivideByZero;
+                        }
+
+                        // TODO: other requirement for @divExact
+                        break :div @divExact(lhs.value, rhs.value);
+                    },
+                    else => unreachable,
+                },
+            };
+        },
+    };
+}
+
+const expect = std.testing.expect;
+const expectEqual = std.testing.expectEqual;
+const expectEqualStrings = std.testing.expectEqualStrings;
+
+fn expect_equal_slices_of_values(
+    expected: []const Value,
+    actual: []const Value,
+) !void {
+    for (expected, actual) |e, a| {
+        try expectEqualStrings(e.str, a.str);
+        try expectEqual(e.index, a.index);
+    }
+}
+
+fn expect_equal_slices_of_ops(
+    expected: []const OperationWithIndex,
+    actual: []const OperationWithIndex,
+) !void {
+    for (expected, actual) |e, a| {
+        try expectEqual(e.op, a.op);
+        try expectEqual(e.index, a.index);
+    }
+}
+
+test "expr.tokenize.integer" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("1", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 0, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 0, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.integer.parenthesis" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("(1)", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 1, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 1, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.integer.double parenthesis" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("((1))", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 2, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 2, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.symbol" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("BAR", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 0, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 0, .str = "BAR" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.add" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("1 + 2", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 2, .op = .add },
+        .{ .index = 4, .op = .value },
+        .{ .index = 0, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 4, .str = "2" },
+        .{ .index = 0, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.add.chain" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("1 + 2 + 3", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 6, .op = .add },
+        .{ .index = 8, .op = .value },
+        .{ .index = 2, .op = .add },
+        .{ .index = 4, .op = .value },
+        .{ .index = 0, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 8, .str = "3" },
+        .{ .index = 4, .str = "2" },
+        .{ .index = 0, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.sub" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("1 - 2", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 2, .op = .sub },
+        .{ .index = 4, .op = .value },
+        .{ .index = 0, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 4, .str = "2" },
+        .{ .index = 0, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.sub.nospace" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("1-2", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 1, .op = .sub },
+        .{ .index = 2, .op = .value },
+        .{ .index = 0, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 2, .str = "2" },
+        .{ .index = 0, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.sub.negative" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("1 - -2", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 2, .op = .sub },
+        .{ .index = 4, .op = .negative },
+        .{ .index = 5, .op = .value },
+        .{ .index = 0, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 5, .str = "2" },
+        .{ .index = 0, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.mul" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("1 * 2", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 2, .op = .mul },
+        .{ .index = 4, .op = .value },
+        .{ .index = 0, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 4, .str = "2" },
+        .{ .index = 0, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.div" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("1 / 2", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 2, .op = .div },
+        .{ .index = 4, .op = .value },
+        .{ .index = 0, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 4, .str = "2" },
+        .{ .index = 0, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.negative" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("-1", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 0, .op = .negative },
+        .{ .index = 1, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 1, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenize.bit reverse" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("::1", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 0, .op = .bit_reverse },
+        .{ .index = 2, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 2, .str = "1" },
+    }, expr.values.slice());
+}
+
+test "expr.tokenzie.parenthesis" {
+    var diags: ?Diagnostics = null;
+    const expr = try tokenize("1 * (::2 + (12 / 3)) - 5", 0, &diags);
+
+    try expect_equal_slices_of_ops(&.{
+        .{ .index = 21, .op = .sub },
+        .{ .index = 23, .op = .value },
+        .{ .index = 2, .op = .mul },
+        .{ .index = 9, .op = .add },
+        .{ .index = 15, .op = .div },
+        .{ .index = 17, .op = .value },
+        .{ .index = 12, .op = .value },
+        .{ .index = 5, .op = .bit_reverse },
+        .{ .index = 7, .op = .value },
+        .{ .index = 0, .op = .value },
+    }, expr.ops.slice());
+
+    try expect_equal_slices_of_values(&.{
+        .{ .index = 23, .str = "5" },
+        .{ .index = 17, .str = "3" },
+        .{ .index = 12, .str = "12" },
+        .{ .index = 7, .str = "2" },
+        .{ .index = 0, .str = "1" },
+    }, expr.values.slice());
+}
+
+fn evaluate_test(expected: i128, str: []const u8, define_list: []const DefineWithIndex) !void {
+    var diags: ?Diagnostics = null;
+    const expr = tokenize(str, 0, &diags) catch |err| {
+        if (diags) |d|
+            std.log.err("{}: {s}", .{ err, d.message.slice() });
+
+        return err;
+    };
+
+    const actual = expr.evaluate(&.{define_list}, &diags) catch |err| {
+        if (diags) |d|
+            std.log.err("{}: {s}", .{ err, d.message.slice() })
+        else
+            std.log.err("{}", .{err});
+
+        return err;
+    };
+
+    try expectEqual(expected, actual);
+}
+
+test "expr.evaluate.integer" {
+    try evaluate_test(1, "1", &.{});
+}
+
+test "expr.evaluate.symbol" {
+    try evaluate_test(5, "BAR", &.{
+        .{
+            .name = "BAR",
+            .value = 5,
+            .index = 0,
+        },
+    });
+}
+
+test "expr.evaluate.add" {
+    try evaluate_test(3, "1 + 2", &.{});
+    try evaluate_test(6, "1 + 2 + 3", &.{});
+}
+
+test "expr.evaluate.sub" {
+    try evaluate_test(1, "2 - 1", &.{});
+    try evaluate_test(1, "(NUM_CYCLES - 1)", &.{
+        .{
+            .name = "NUM_CYCLES",
+            .value = 2,
+            .index = 1,
+        },
+    });
+}
+
+test "expr.evaluate.mul" {
+    try evaluate_test(9, "3 * 3", &.{});
+}
+
+test "expr.evaluate.div" {
+    try evaluate_test(3, "9 / 3", &.{});
+    try evaluate_test(3, "9 / 3", &.{});
+}
+
+test "expr.evaluate.negative" {
+    try evaluate_test(-3, "-3", &.{});
+}
+
+test "expr.evaluate.bit reverse" {
+    try evaluate_test(0x80000000, "::1", &.{});
+}
+
+test "expr.evaluate.parenthesis" {
+    try evaluate_test(15, "5 * (1 + 2)", &.{});
+    try evaluate_test(1 * (@bitReverse(@as(u32, 2)) + (12 / 3)) - 5, "1 * (::2 + (12 / 3)) - 5", &.{});
+}
diff --git a/src/hal/pio/assembler/comparison_tests.zig b/src/hal/pio/assembler/comparison_tests.zig
new file mode 100644
index 000000000..4a3946575
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests.zig
@@ -0,0 +1,168 @@
+const std = @import("std");
+const assembler = @import("../assembler.zig");
+const tokenizer = @import("tokenizer.zig");
+const c = @cImport({
+    @cDefine("PICO_NO_HARDWARE", "1");
+    @cInclude("stdint.h");
+    @cInclude("comparison_tests/addition.pio.h");
+    @cInclude("comparison_tests/apa102.pio.h");
+    @cInclude("comparison_tests/blink.pio.h");
+    @cInclude("comparison_tests/clocked_input.pio.h");
+    @cInclude("comparison_tests/differential_manchester.pio.h");
+    @cInclude("comparison_tests/hello.pio.h");
+    @cInclude("comparison_tests/hub75.pio.h");
+    @cInclude("comparison_tests/i2c.pio.h");
+    @cInclude("comparison_tests/manchester_encoding.pio.h");
+    @cInclude("comparison_tests/nec_carrier_burst.pio.h");
+    @cInclude("comparison_tests/nec_carrier_control.pio.h");
+    @cInclude("comparison_tests/nec_receive.pio.h");
+    @cInclude("comparison_tests/pio_serialiser.pio.h");
+    @cInclude("comparison_tests/pwm.pio.h");
+    @cInclude("comparison_tests/quadrature_encoder.pio.h");
+    @cInclude("comparison_tests/resistor_dac.pio.h");
+    @cInclude("comparison_tests/spi.pio.h");
+    @cInclude("comparison_tests/squarewave.pio.h");
+    @cInclude("comparison_tests/squarewave_fast.pio.h");
+    @cInclude("comparison_tests/squarewave_wrap.pio.h");
+    @cInclude("comparison_tests/st7789_lcd.pio.h");
+    @cInclude("comparison_tests/uart_rx.pio.h");
+    @cInclude("comparison_tests/uart_tx.pio.h");
+    @cInclude("comparison_tests/ws2812.pio.h");
+});
+
+fn pio_comparison(comptime source: []const u8) !void {
+    const output = comptime assembler.assemble(source, .{}) catch unreachable;
+    try std.testing.expect(output.programs.len > 0);
+
+    inline for (output.programs) |program| {
+        const expected_insns = @field(c, program.name ++ "_program_instructions");
+        for (program.instructions, expected_insns) |actual, expected| {
+            std.log.debug("expected: 0x{x}", .{expected});
+            std.log.debug("  actual: 0x{x}", .{actual});
+            std.log.debug("", .{});
+        }
+
+        for (program.instructions, expected_insns) |actual, expected|
+            try std.testing.expectEqual(expected, actual);
+    }
+}
+
+test "pio.comparison.addition" {
+    @setEvalBranchQuota(4000);
+    try pio_comparison(@embedFile("comparison_tests/addition.pio"));
+}
+
+test "pio.comparison.apa102" {
+    @setEvalBranchQuota(10000);
+    try pio_comparison(@embedFile("comparison_tests/apa102.pio"));
+}
+
+test "pio.comparison.blink" {
+    @setEvalBranchQuota(4000);
+    try pio_comparison(@embedFile("comparison_tests/blink.pio"));
+}
+
+test "pio.comparison.clocked_input" {
+    @setEvalBranchQuota(5000);
+    try pio_comparison(@embedFile("comparison_tests/clocked_input.pio"));
+}
+
+test "pio.comparison.differential_manchester" {
+    @setEvalBranchQuota(14000);
+    try pio_comparison(@embedFile("comparison_tests/differential_manchester.pio"));
+}
+
+test "pio.comparison.hello" {
+    @setEvalBranchQuota(3000);
+    try pio_comparison(@embedFile("comparison_tests/hello.pio"));
+}
+
+test "pio.comparison.hub75" {
+    @setEvalBranchQuota(17000);
+    try pio_comparison(@embedFile("comparison_tests/hub75.pio"));
+}
+
+test "pio.comparison.i2c" {
+    @setEvalBranchQuota(17000);
+    try pio_comparison(@embedFile("comparison_tests/i2c.pio"));
+}
+
+test "pio.comparison.manchester_encoding" {
+    @setEvalBranchQuota(11000);
+    try pio_comparison(@embedFile("comparison_tests/manchester_encoding.pio"));
+}
+
+test "pio.comparison.nec_carrier_burst" {
+    @setEvalBranchQuota(6000);
+    try pio_comparison(@embedFile("comparison_tests/nec_carrier_burst.pio"));
+}
+
+test "pio.comparison.nec_carrier_control" {
+    @setEvalBranchQuota(9000);
+    try pio_comparison(@embedFile("comparison_tests/nec_carrier_control.pio"));
+}
+
+test "pio.comparison.nec_receive" {
+    @setEvalBranchQuota(11000);
+    try pio_comparison(@embedFile("comparison_tests/nec_receive.pio"));
+}
+
+test "pio.comparison.pio_serialiser" {
+    @setEvalBranchQuota(3000);
+    try pio_comparison(@embedFile("comparison_tests/pio_serialiser.pio"));
+}
+
+test "pio.comparison.pwm" {
+    @setEvalBranchQuota(4000);
+    try pio_comparison(@embedFile("comparison_tests/pwm.pio"));
+}
+
+test "pio.comparison.quadrature_encoder" {
+    @setEvalBranchQuota(17000);
+    try pio_comparison(@embedFile("comparison_tests/quadrature_encoder.pio"));
+}
+
+test "pio.comparison.resistor_dac" {
+    @setEvalBranchQuota(3000);
+    try pio_comparison(@embedFile("comparison_tests/resistor_dac.pio"));
+}
+
+test "pio.comparison.spi" {
+    @setEvalBranchQuota(22000);
+    try pio_comparison(@embedFile("comparison_tests/spi.pio"));
+}
+
+test "pio.comparison.squarewave" {
+    @setEvalBranchQuota(2000);
+    try pio_comparison(@embedFile("comparison_tests/squarewave.pio"));
+}
+
+test "pio.comparison.squarewave_fast" {
+    @setEvalBranchQuota(2000);
+    try pio_comparison(@embedFile("comparison_tests/squarewave_fast.pio"));
+}
+
+test "pio.comparison.squarewave_wrap" {
+    @setEvalBranchQuota(3000);
+    try pio_comparison(@embedFile("comparison_tests/squarewave_wrap.pio"));
+}
+
+test "pio.comparison.st7789_lcd" {
+    @setEvalBranchQuota(5000);
+    try pio_comparison(@embedFile("comparison_tests/st7789_lcd.pio"));
+}
+
+test "pio.comparison.uart_rx" {
+    @setEvalBranchQuota(10000);
+    try pio_comparison(@embedFile("comparison_tests/uart_rx.pio"));
+}
+
+test "pio.comparison.uart_tx" {
+    @setEvalBranchQuota(6000);
+    try pio_comparison(@embedFile("comparison_tests/uart_tx.pio"));
+}
+
+test "pio.comparison.ws2812" {
+    @setEvalBranchQuota(10000);
+    try pio_comparison(@embedFile("comparison_tests/ws2812.pio"));
+}
diff --git a/src/hal/pio/assembler/comparison_tests/README.adoc b/src/hal/pio/assembler/comparison_tests/README.adoc
new file mode 100644
index 000000000..872e125c6
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/README.adoc
@@ -0,0 +1,4 @@
+= PIO example programs for testing
+
+These were all taken from https://github.com/raspberrypi/pico-examples[the official pico examples repo].
+The headers are generated using `pioasm`.
diff --git a/src/hal/pio/assembler/comparison_tests/addition.pio b/src/hal/pio/assembler/comparison_tests/addition.pio
new file mode 100644
index 000000000..8eddd0e7b
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/addition.pio
@@ -0,0 +1,33 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program addition
+
+; Pop two 32 bit integers from the TX FIFO, add them together, and push the
+; result to the TX FIFO. Autopush/pull should be disabled as we're using
+; explicit push and pull instructions.
+;
+; This program uses the two's complement identity x + y == ~(~x - y)
+
+	pull
+	mov x, ~osr
+	pull
+	mov y, osr
+	jmp test        ; this loop is equivalent to the following C code:
+incr:               ; while (y--)
+	jmp x-- test    ;     x--;
+test:               ; This has the effect of subtracting y from x, eventually.
+	jmp y-- incr
+	mov isr, ~x
+	push
+
+% c-sdk {
+static inline void addition_program_init(PIO pio, uint sm, uint offset) {
+	pio_sm_config c = addition_program_get_default_config(offset);
+	pio_sm_init(pio, sm, offset, &c);
+	pio_sm_set_enabled(pio, sm, true);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/addition.pio.h b/src/hal/pio/assembler/comparison_tests/addition.pio.h
new file mode 100644
index 000000000..7621c5809
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/addition.pio.h
@@ -0,0 +1,52 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// -------- //
+// addition //
+// -------- //
+
+#define addition_wrap_target 0
+#define addition_wrap 8
+
+static const uint16_t addition_program_instructions[] = {
+            //     .wrap_target
+    0x80a0, //  0: pull   block                      
+    0xa02f, //  1: mov    x, !osr                    
+    0x80a0, //  2: pull   block                      
+    0xa047, //  3: mov    y, osr                     
+    0x0006, //  4: jmp    6                          
+    0x0046, //  5: jmp    x--, 6                     
+    0x0085, //  6: jmp    y--, 5                     
+    0xa0c9, //  7: mov    isr, !x                    
+    0x8020, //  8: push   block                      
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program addition_program = {
+    .instructions = addition_program_instructions,
+    .length = 9,
+    .origin = -1,
+};
+
+static inline pio_sm_config addition_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + addition_wrap_target, offset + addition_wrap);
+    return c;
+}
+
+static inline void addition_program_init(PIO pio, uint sm, uint offset) {
+	pio_sm_config c = addition_program_get_default_config(offset);
+	pio_sm_init(pio, sm, offset, &c);
+	pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/apa102.pio b/src/hal/pio/assembler/comparison_tests/apa102.pio
new file mode 100644
index 000000000..5d76f088a
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/apa102.pio
@@ -0,0 +1,89 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program apa102_mini
+.side_set 1
+
+; This is really just a TX-only SPI. CLK is side-set pin 0, DIN is OUT pin 0.
+; Autopull enabled, threshold 32.
+;
+; Every word (32 bits) written to the FIFO will be shifted out in its entirety, MSB-first.
+
+    out pins, 1   side 0   ; Stall here when no data (still asserts clock low)
+    nop           side 1
+
+% c-sdk {
+#include "hardware/clocks.h"
+static inline void apa102_mini_program_init(PIO pio, uint sm, uint offset,
+        uint baud, uint pin_clk, uint pin_din) {
+    pio_sm_set_pins_with_mask(pio, sm, 0, (1u << pin_clk) | (1u << pin_din));
+    pio_sm_set_pindirs_with_mask(pio, sm, ~0u, (1u << pin_clk) | (1u << pin_din));
+    pio_gpio_init(pio, pin_clk);
+    pio_gpio_init(pio, pin_din);
+
+    pio_sm_config c = apa102_mini_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, pin_din, 1);
+    sm_config_set_sideset_pins(&c, pin_clk);
+    // Shift to right, autopull with threshold 32
+    sm_config_set_out_shift(&c, false, true, 32);
+    // Deeper FIFO as we're not doing any RX
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    // We transmit 1 bit every 2 execution cycles
+    float div = (float)clock_get_hz(clk_sys) / (2 * baud);
+    sm_config_set_clkdiv(&c, div);
+
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
+
+.program apa102_rgb555
+
+; Alternative program to unpack two RGB555 pixels from a FIFO word and transmit.
+; This makes it easier to DMA large buffers without processor involvement.
+
+; OSR: shift to right
+; ISR: shift to right
+
+; To set brightness, set ISR to bit-reverse of 5-bit brightness,
+; followed by 111. (00...00_b0b1b2b3b4_111)
+
+; DMA pixel format is 0RRRRRGGGGGBBBBB x2 (15 bpp, 2px per FIFO word)
+
+; APA102 command structure:
+; increasing time ---->>
+;             | byte 3 | byte 2 | byte 1 | byte 0 |
+;             |7      0|7      0|7      0|7      0|
+;             -------------------------------------
+; Pixel       |111bbbbb|BBBBBBBB|GGGGGGGG|RRRRRRRR|
+; Start Frame |00000000|00000000|00000000|00000000|
+; Stop Frame  |11111111|11111111|11111111|11111111|
+
+.wrap_target
+public pixel_out:
+    ; pixel_out formats an APA102 colour command in the ISR.
+    ; bit_run shifts 32 bits out of the ISR, with clock.
+    pull ifempty
+    set x, 2
+colour_loop:
+    in osr, 5
+    out null, 5
+    in null, 3
+    jmp x-- colour_loop
+    in y, 8
+    mov isr, ::isr ; reverse for msb-first wire order
+    out null, 1
+public bit_run:
+    ; in isr, n rotates ISR by n bits (right rotation only)
+    ; Use this to perform out shifts from ISR, via mov pins
+    set x, 31
+bit_out:
+    set pins, 0
+    mov pins, isr [6]
+    set pins, 1
+    in isr, 1 [6]
+    jmp x-- bit_out
+.wrap
diff --git a/src/hal/pio/assembler/comparison_tests/apa102.pio.h b/src/hal/pio/assembler/comparison_tests/apa102.pio.h
new file mode 100644
index 000000000..fd5a5200f
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/apa102.pio.h
@@ -0,0 +1,105 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ----------- //
+// apa102_mini //
+// ----------- //
+
+#define apa102_mini_wrap_target 0
+#define apa102_mini_wrap 1
+
+static const uint16_t apa102_mini_program_instructions[] = {
+            //     .wrap_target
+    0x6001, //  0: out    pins, 1         side 0     
+    0xb042, //  1: nop                    side 1     
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program apa102_mini_program = {
+    .instructions = apa102_mini_program_instructions,
+    .length = 2,
+    .origin = -1,
+};
+
+static inline pio_sm_config apa102_mini_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + apa102_mini_wrap_target, offset + apa102_mini_wrap);
+    sm_config_set_sideset(&c, 1, false, false);
+    return c;
+}
+
+#include "hardware/clocks.h"
+static inline void apa102_mini_program_init(PIO pio, uint sm, uint offset,
+        uint baud, uint pin_clk, uint pin_din) {
+    pio_sm_set_pins_with_mask(pio, sm, 0, (1u << pin_clk) | (1u << pin_din));
+    pio_sm_set_pindirs_with_mask(pio, sm, ~0u, (1u << pin_clk) | (1u << pin_din));
+    pio_gpio_init(pio, pin_clk);
+    pio_gpio_init(pio, pin_din);
+    pio_sm_config c = apa102_mini_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, pin_din, 1);
+    sm_config_set_sideset_pins(&c, pin_clk);
+    // Shift to right, autopull with threshold 32
+    sm_config_set_out_shift(&c, false, true, 32);
+    // Deeper FIFO as we're not doing any RX
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    // We transmit 1 bit every 2 execution cycles
+    float div = (float)clock_get_hz(clk_sys) / (2 * baud);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
+// ------------- //
+// apa102_rgb555 //
+// ------------- //
+
+#define apa102_rgb555_wrap_target 0
+#define apa102_rgb555_wrap 14
+
+#define apa102_rgb555_offset_pixel_out 0u
+#define apa102_rgb555_offset_bit_run 9u
+
+static const uint16_t apa102_rgb555_program_instructions[] = {
+            //     .wrap_target
+    0x80e0, //  0: pull   ifempty block              
+    0xe022, //  1: set    x, 2                       
+    0x40e5, //  2: in     osr, 5                     
+    0x6065, //  3: out    null, 5                    
+    0x4063, //  4: in     null, 3                    
+    0x0042, //  5: jmp    x--, 2                     
+    0x4048, //  6: in     y, 8                       
+    0xa0d6, //  7: mov    isr, ::isr                 
+    0x6061, //  8: out    null, 1                    
+    0xe03f, //  9: set    x, 31                      
+    0xe000, // 10: set    pins, 0                    
+    0xa606, // 11: mov    pins, isr              [6] 
+    0xe001, // 12: set    pins, 1                    
+    0x46c1, // 13: in     isr, 1                 [6] 
+    0x004a, // 14: jmp    x--, 10                    
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program apa102_rgb555_program = {
+    .instructions = apa102_rgb555_program_instructions,
+    .length = 15,
+    .origin = -1,
+};
+
+static inline pio_sm_config apa102_rgb555_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + apa102_rgb555_wrap_target, offset + apa102_rgb555_wrap);
+    return c;
+}
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/blink.pio b/src/hal/pio/assembler/comparison_tests/blink.pio
new file mode 100644
index 000000000..ef3090022
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/blink.pio
@@ -0,0 +1,34 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+; SET pin 0 should be mapped to your LED GPIO
+
+.program blink
+    pull block
+    out y, 32
+.wrap_target
+    mov x, y
+    set pins, 1   ; Turn LED on
+lp1:
+    jmp x-- lp1   ; Delay for (x + 1) cycles, x is a 32 bit number
+    mov x, y
+    set pins, 0   ; Turn LED off
+lp2:
+    jmp x-- lp2   ; Delay for the same number of cycles again
+.wrap             ; Blink forever!
+
+
+% c-sdk {
+// this is a raw helper function for use by the user which sets up the GPIO output, and configures the SM to output on a particular pin
+
+void blink_program_init(PIO pio, uint sm, uint offset, uint pin) {
+   pio_gpio_init(pio, pin);
+   pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+   pio_sm_config c = blink_program_get_default_config(offset);
+   sm_config_set_set_pins(&c, pin, 1);
+   pio_sm_init(pio, sm, offset, &c);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/blink.pio.h b/src/hal/pio/assembler/comparison_tests/blink.pio.h
new file mode 100644
index 000000000..e466a2843
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/blink.pio.h
@@ -0,0 +1,54 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ----- //
+// blink //
+// ----- //
+
+#define blink_wrap_target 2
+#define blink_wrap 7
+
+static const uint16_t blink_program_instructions[] = {
+    0x80a0, //  0: pull   block                      
+    0x6040, //  1: out    y, 32                      
+            //     .wrap_target
+    0xa022, //  2: mov    x, y                       
+    0xe001, //  3: set    pins, 1                    
+    0x0044, //  4: jmp    x--, 4                     
+    0xa022, //  5: mov    x, y                       
+    0xe000, //  6: set    pins, 0                    
+    0x0047, //  7: jmp    x--, 7                     
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program blink_program = {
+    .instructions = blink_program_instructions,
+    .length = 8,
+    .origin = -1,
+};
+
+static inline pio_sm_config blink_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + blink_wrap_target, offset + blink_wrap);
+    return c;
+}
+
+// this is a raw helper function for use by the user which sets up the GPIO output, and configures the SM to output on a particular pin
+void blink_program_init(PIO pio, uint sm, uint offset, uint pin) {
+   pio_gpio_init(pio, pin);
+   pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+   pio_sm_config c = blink_program_get_default_config(offset);
+   sm_config_set_set_pins(&c, pin, 1);
+   pio_sm_init(pio, sm, offset, &c);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/clocked_input.pio b/src/hal/pio/assembler/comparison_tests/clocked_input.pio
new file mode 100644
index 000000000..51fa54ca3
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/clocked_input.pio
@@ -0,0 +1,51 @@
+;
+; Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program clocked_input
+
+; Sample bits using an external clock, and push groups of bits into the RX FIFO.
+; - IN pin 0 is the data pin
+; - IN pin 1 is the clock pin
+; - Autopush is enabled, threshold 8
+;
+; This program samples data with each rising clock edge (like mode 0 or mode 3
+; SPI). The data is actually sampled one system clock cycle after the rising
+; edge is observed, so a clock ratio of at least input_clk < clk_sys / 6 is
+; recommended for good sampling alignment.
+
+    wait 0 pin 1
+    wait 1 pin 1
+    in pins, 1
+
+% c-sdk {
+static inline void clocked_input_program_init(PIO pio, uint sm, uint offset, uint pin) {
+    pio_sm_config c = clocked_input_program_get_default_config(offset);
+
+    // Set the IN base pin to the provided `pin` parameter. This is the data
+    // pin, and the next-numbered GPIO is used as the clock pin.
+    sm_config_set_in_pins(&c, pin);
+    // Set the pin directions to input at the PIO
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 2, false);
+    // Connect these GPIOs to this PIO block
+    pio_gpio_init(pio, pin);
+    pio_gpio_init(pio, pin + 1);
+
+    // Shifting to left matches the customary MSB-first ordering of SPI.
+    sm_config_set_in_shift(
+        &c,
+        false, // Shift-to-right = false (i.e. shift to left)
+        true,  // Autopush enabled
+        8      // Autopush threshold = 8
+    );
+
+    // We only receive, so disable the TX FIFO to make the RX FIFO deeper.
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+
+    // Load our configuration, and start the program from the beginning
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/clocked_input.pio.h b/src/hal/pio/assembler/comparison_tests/clocked_input.pio.h
new file mode 100644
index 000000000..277b939cb
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/clocked_input.pio.h
@@ -0,0 +1,64 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ------------- //
+// clocked_input //
+// ------------- //
+
+#define clocked_input_wrap_target 0
+#define clocked_input_wrap 2
+
+static const uint16_t clocked_input_program_instructions[] = {
+            //     .wrap_target
+    0x2021, //  0: wait   0 pin, 1                   
+    0x20a1, //  1: wait   1 pin, 1                   
+    0x4001, //  2: in     pins, 1                    
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program clocked_input_program = {
+    .instructions = clocked_input_program_instructions,
+    .length = 3,
+    .origin = -1,
+};
+
+static inline pio_sm_config clocked_input_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + clocked_input_wrap_target, offset + clocked_input_wrap);
+    return c;
+}
+
+static inline void clocked_input_program_init(PIO pio, uint sm, uint offset, uint pin) {
+    pio_sm_config c = clocked_input_program_get_default_config(offset);
+    // Set the IN base pin to the provided `pin` parameter. This is the data
+    // pin, and the next-numbered GPIO is used as the clock pin.
+    sm_config_set_in_pins(&c, pin);
+    // Set the pin directions to input at the PIO
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 2, false);
+    // Connect these GPIOs to this PIO block
+    pio_gpio_init(pio, pin);
+    pio_gpio_init(pio, pin + 1);
+    // Shifting to left matches the customary MSB-first ordering of SPI.
+    sm_config_set_in_shift(
+        &c,
+        false, // Shift-to-right = false (i.e. shift to left)
+        true,  // Autopush enabled
+        8      // Autopush threshold = 8
+    );
+    // We only receive, so disable the TX FIFO to make the RX FIFO deeper.
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    // Load our configuration, and start the program from the beginning
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/differential_manchester.pio b/src/hal/pio/assembler/comparison_tests/differential_manchester.pio
new file mode 100644
index 000000000..a9e825dac
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/differential_manchester.pio
@@ -0,0 +1,104 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program differential_manchester_tx
+.side_set 1 opt
+
+; Transmit one bit every 16 cycles. In each bit period:
+; - A '0' is encoded as a transition at the start of the bit period
+; - A '1' is encoded as a transition at the start *and* in the middle
+;
+; Side-set bit 0 must be mapped to the data output pin.
+; Autopull must be enabled.
+
+public start:
+initial_high:
+    out x, 1                     ; Start of bit period: always assert transition
+    jmp !x high_0     side 1 [6] ; Test the data bit we just shifted out of OSR
+high_1:
+    nop
+    jmp initial_high  side 0 [6] ; For `1` bits, also transition in the middle
+high_0:
+    jmp initial_low          [7] ; Otherwise, the line is stable in the middle
+
+initial_low:
+    out x, 1                     ; Always shift 1 bit from OSR to X so we can
+    jmp !x low_0      side 0 [6] ; branch on it. Autopull refills OSR for us.
+low_1:
+    nop
+    jmp initial_low   side 1 [6] ; If there are two transitions, return to
+low_0:
+    jmp initial_high         [7] ; the initial line state is flipped!
+
+% c-sdk {
+static inline void differential_manchester_tx_program_init(PIO pio, uint sm, uint offset, uint pin, float div) {
+    pio_sm_set_pins_with_mask(pio, sm, 0, 1u << pin);
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+    pio_gpio_init(pio, pin);
+
+    pio_sm_config c = differential_manchester_tx_program_get_default_config(offset);
+    sm_config_set_sideset_pins(&c, pin);
+    sm_config_set_out_shift(&c, true, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset + differential_manchester_tx_offset_start, &c);
+
+    // Execute a blocking pull so that we maintain the initial line state until data is available
+    pio_sm_exec(pio, sm, pio_encode_pull(false, true));
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
+.program differential_manchester_rx
+
+; Assumes line is idle low
+; One bit is 16 cycles. In each bit period:
+; - A '0' is encoded as a transition at time 0
+; - A '1' is encoded as a transition at time 0 and a transition at time T/2
+;
+; The IN mapping and the JMP pin select must both be mapped to the GPIO used for
+; RX data. Autopush must be enabled.
+
+public start:
+initial_high:           ; Find rising edge at start of bit period
+    wait 1 pin, 0  [11] ; Delay to eye of second half-period (i.e 3/4 of way
+    jmp pin high_0      ; through bit) and branch on RX pin high/low.
+high_1:
+    in x, 1             ; Second transition detected (a `1` data symbol)
+    jmp initial_high
+high_0:
+    in y, 1 [1]         ; Line still high, no centre transition (data is `0`)
+    ; Fall-through
+
+.wrap_target
+initial_low:            ; Find falling edge at start of bit period
+    wait 0 pin, 0 [11]  ; Delay to eye of second half-period
+    jmp pin low_1
+low_0:
+    in y, 1             ; Line still low, no centre transition (data is `0`)
+    jmp initial_high
+low_1:                  ; Second transition detected (data is `1`)
+    in x, 1 [1]
+.wrap
+
+% c-sdk {
+static inline void differential_manchester_rx_program_init(PIO pio, uint sm, uint offset, uint pin, float div) {
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    pio_gpio_init(pio, pin);
+
+    pio_sm_config c = differential_manchester_rx_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, pin); // for WAIT
+    sm_config_set_jmp_pin(&c, pin); // for JMP
+    sm_config_set_in_shift(&c, true, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset, &c);
+
+    // X and Y are set to 0 and 1, to conveniently emit these to ISR/FIFO.
+    pio_sm_exec(pio, sm, pio_encode_set(pio_x, 1));
+    pio_sm_exec(pio, sm, pio_encode_set(pio_y, 0));
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/differential_manchester.pio.h b/src/hal/pio/assembler/comparison_tests/differential_manchester.pio.h
new file mode 100644
index 000000000..c8d76ca54
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/differential_manchester.pio.h
@@ -0,0 +1,120 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// -------------------------- //
+// differential_manchester_tx //
+// -------------------------- //
+
+#define differential_manchester_tx_wrap_target 0
+#define differential_manchester_tx_wrap 9
+
+#define differential_manchester_tx_offset_start 0u
+
+static const uint16_t differential_manchester_tx_program_instructions[] = {
+            //     .wrap_target
+    0x6021, //  0: out    x, 1                       
+    0x1e24, //  1: jmp    !x, 4           side 1 [6] 
+    0xa042, //  2: nop                               
+    0x1600, //  3: jmp    0               side 0 [6] 
+    0x0705, //  4: jmp    5                      [7] 
+    0x6021, //  5: out    x, 1                       
+    0x1629, //  6: jmp    !x, 9           side 0 [6] 
+    0xa042, //  7: nop                               
+    0x1e05, //  8: jmp    5               side 1 [6] 
+    0x0700, //  9: jmp    0                      [7] 
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program differential_manchester_tx_program = {
+    .instructions = differential_manchester_tx_program_instructions,
+    .length = 10,
+    .origin = -1,
+};
+
+static inline pio_sm_config differential_manchester_tx_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + differential_manchester_tx_wrap_target, offset + differential_manchester_tx_wrap);
+    sm_config_set_sideset(&c, 2, true, false);
+    return c;
+}
+
+static inline void differential_manchester_tx_program_init(PIO pio, uint sm, uint offset, uint pin, float div) {
+    pio_sm_set_pins_with_mask(pio, sm, 0, 1u << pin);
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+    pio_gpio_init(pio, pin);
+    pio_sm_config c = differential_manchester_tx_program_get_default_config(offset);
+    sm_config_set_sideset_pins(&c, pin);
+    sm_config_set_out_shift(&c, true, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset + differential_manchester_tx_offset_start, &c);
+    // Execute a blocking pull so that we maintain the initial line state until data is available
+    pio_sm_exec(pio, sm, pio_encode_pull(false, true));
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
+// -------------------------- //
+// differential_manchester_rx //
+// -------------------------- //
+
+#define differential_manchester_rx_wrap_target 5
+#define differential_manchester_rx_wrap 9
+
+#define differential_manchester_rx_offset_start 0u
+
+static const uint16_t differential_manchester_rx_program_instructions[] = {
+    0x2ba0, //  0: wait   1 pin, 0               [11]
+    0x00c4, //  1: jmp    pin, 4                     
+    0x4021, //  2: in     x, 1                       
+    0x0000, //  3: jmp    0                          
+    0x4141, //  4: in     y, 1                   [1] 
+            //     .wrap_target
+    0x2b20, //  5: wait   0 pin, 0               [11]
+    0x00c9, //  6: jmp    pin, 9                     
+    0x4041, //  7: in     y, 1                       
+    0x0000, //  8: jmp    0                          
+    0x4121, //  9: in     x, 1                   [1] 
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program differential_manchester_rx_program = {
+    .instructions = differential_manchester_rx_program_instructions,
+    .length = 10,
+    .origin = -1,
+};
+
+static inline pio_sm_config differential_manchester_rx_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + differential_manchester_rx_wrap_target, offset + differential_manchester_rx_wrap);
+    return c;
+}
+
+static inline void differential_manchester_rx_program_init(PIO pio, uint sm, uint offset, uint pin, float div) {
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    pio_gpio_init(pio, pin);
+    pio_sm_config c = differential_manchester_rx_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, pin); // for WAIT
+    sm_config_set_jmp_pin(&c, pin); // for JMP
+    sm_config_set_in_shift(&c, true, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset, &c);
+    // X and Y are set to 0 and 1, to conveniently emit these to ISR/FIFO.
+    pio_sm_exec(pio, sm, pio_encode_set(pio_x, 1));
+    pio_sm_exec(pio, sm, pio_encode_set(pio_y, 0));
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/hello.pio b/src/hal/pio/assembler/comparison_tests/hello.pio
new file mode 100644
index 000000000..9eac4de71
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/hello.pio
@@ -0,0 +1,34 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program hello
+
+; Repeatedly get one word of data from the TX FIFO, stalling when the FIFO is
+; empty. Write the least significant bit to the OUT pin group.
+
+loop:
+    pull
+    out pins, 1
+    jmp loop
+
+% c-sdk {
+static inline void hello_program_init(PIO pio, uint sm, uint offset, uint pin) {
+    pio_sm_config c = hello_program_get_default_config(offset);
+
+    // Map the state machine's OUT pin group to one pin, namely the `pin`
+    // parameter to this function.
+    sm_config_set_out_pins(&c, pin, 1);
+    // Set this pin's GPIO function (connect PIO to the pad)
+    pio_gpio_init(pio, pin);
+    // Set the pin direction to output at the PIO
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+
+    // Load our configuration, and jump to the start of the program
+    pio_sm_init(pio, sm, offset, &c);
+    // Set the state machine running
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/hello.pio.h b/src/hal/pio/assembler/comparison_tests/hello.pio.h
new file mode 100644
index 000000000..415d1ccb0
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/hello.pio.h
@@ -0,0 +1,55 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ----- //
+// hello //
+// ----- //
+
+#define hello_wrap_target 0
+#define hello_wrap 2
+
+static const uint16_t hello_program_instructions[] = {
+            //     .wrap_target
+    0x80a0, //  0: pull   block                      
+    0x6001, //  1: out    pins, 1                    
+    0x0000, //  2: jmp    0                          
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program hello_program = {
+    .instructions = hello_program_instructions,
+    .length = 3,
+    .origin = -1,
+};
+
+static inline pio_sm_config hello_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + hello_wrap_target, offset + hello_wrap);
+    return c;
+}
+
+static inline void hello_program_init(PIO pio, uint sm, uint offset, uint pin) {
+    pio_sm_config c = hello_program_get_default_config(offset);
+    // Map the state machine's OUT pin group to one pin, namely the `pin`
+    // parameter to this function.
+    sm_config_set_out_pins(&c, pin, 1);
+    // Set this pin's GPIO function (connect PIO to the pad)
+    pio_gpio_init(pio, pin);
+    // Set the pin direction to output at the PIO
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+    // Load our configuration, and jump to the start of the program
+    pio_sm_init(pio, sm, offset, &c);
+    // Set the state machine running
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/hub75.pio b/src/hal/pio/assembler/comparison_tests/hub75.pio
new file mode 100644
index 000000000..a6fb619cd
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/hub75.pio
@@ -0,0 +1,128 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program hub75_row
+
+; side-set pin 0 is LATCH
+; side-set pin 1 is OEn
+; OUT pins are row select A-E
+;
+; Each FIFO record consists of:
+; - 5-bit row select (LSBs)
+; - Pulse width - 1 (27 MSBs)
+;
+; Repeatedly select a row, pulse LATCH, and generate a pulse of a certain
+; width on OEn.
+
+.side_set 2
+
+.wrap_target
+    out pins, 5 [7]    side 0x2 ; Deassert OEn, output row select
+    out x, 27   [7]    side 0x3 ; Pulse LATCH, get OEn pulse width
+pulse_loop:
+    jmp x-- pulse_loop side 0x0 ; Assert OEn for x+1 cycles
+.wrap
+
+% c-sdk {
+static inline void hub75_row_program_init(PIO pio, uint sm, uint offset, uint row_base_pin, uint n_row_pins, uint latch_base_pin) {
+    pio_sm_set_consecutive_pindirs(pio, sm, row_base_pin, n_row_pins, true);
+    pio_sm_set_consecutive_pindirs(pio, sm, latch_base_pin, 2, true);
+    for (uint i = row_base_pin; i < row_base_pin + n_row_pins; ++i)
+        pio_gpio_init(pio, i);
+    pio_gpio_init(pio, latch_base_pin);
+    pio_gpio_init(pio, latch_base_pin + 1);
+
+    pio_sm_config c = hub75_row_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, row_base_pin, n_row_pins);
+    sm_config_set_sideset_pins(&c, latch_base_pin);
+    sm_config_set_out_shift(&c, true, true, 32);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+static inline void hub75_wait_tx_stall(PIO pio, uint sm) {
+    uint32_t txstall_mask = 1u << (PIO_FDEBUG_TXSTALL_LSB + sm);
+    pio->fdebug = txstall_mask;
+    while (!(pio->fdebug & txstall_mask))
+        tight_loop_contents();
+}
+%}
+
+.program hub75_data_rgb888
+.side_set 1
+
+; Each FIFO record consists of a RGB888 pixel. (This is ok for e.g. an RGB565
+; source which has been gamma-corrected)
+;
+; Even pixels are sent on R0, G0, B0 and odd pixels on R1, G1, B1 (typically
+; these are for different parts of the screen, NOT for adjacent pixels, so the
+; frame buffer must be interleaved before passing to PIO.)
+;
+; Each pass through, we take bit n, n + 8 and n + 16 from each pixel, for n in
+; {0...7}. Therefore the pixels need to be transmitted 8 times (ouch) to build
+; up the full 8 bit value for each channel, and perform bit-planed PWM by
+; varying pulse widths on the other state machine, in ascending powers of 2.
+; This avoids a lot of bit shuffling on the processors, at the cost of DMA
+; bandwidth (which we have loads of).
+
+; Might want to close your eyes before you read this
+public entry_point:
+.wrap_target
+public shift0:
+    pull             side 0 ; gets patched to `out null, n` if n nonzero (otherwise the PULL is required for fencing)
+    in osr, 1        side 0 ; shuffle shuffle shuffle
+    out null, 8      side 0
+    in osr, 1        side 0
+    out null, 8      side 0
+    in osr, 1        side 0
+    out null, 32     side 0 ; Discard remainder of OSR contents
+public shift1:
+    pull             side 0 ; gets patched to out null, n if n is nonzero (otherwise PULL required)
+    in osr, 1        side 1 ; Note this posedge clocks in the data from the previous iteration
+    out null, 8      side 1
+    in osr, 1        side 1
+    out null, 8      side 1
+    in osr, 1        side 1
+    out null, 32     side 1
+    in null, 26      side 1 ; Note we are just doing this little manoeuvre here to get GPIOs in the order
+    mov pins, ::isr  side 1 ; R0, G0, B0, R1, G1, B1. Can go 1 cycle faster if reversed
+.wrap
+; Note that because the clock edge for pixel n is in the middle of pixel n +
+; 1, a dummy pixel at the end is required to clock the last piece of genuine
+; data. (Also 1 pixel of garbage is clocked out at the start, but this is
+; harmless)
+
+% c-sdk {
+static inline void hub75_data_rgb888_program_init(PIO pio, uint sm, uint offset, uint rgb_base_pin, uint clock_pin) {
+    pio_sm_set_consecutive_pindirs(pio, sm, rgb_base_pin, 6, true);
+    pio_sm_set_consecutive_pindirs(pio, sm, clock_pin, 1, true);
+    for (uint i = rgb_base_pin; i < rgb_base_pin + 6; ++i)
+        pio_gpio_init(pio, i);
+    pio_gpio_init(pio, clock_pin);
+
+    pio_sm_config c = hub75_data_rgb888_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, rgb_base_pin, 6);
+    sm_config_set_sideset_pins(&c, clock_pin);
+    sm_config_set_out_shift(&c, true, true, 24);
+    // ISR shift to left. R0 ends up at bit 5. We push it up to MSB and then flip the register.
+    sm_config_set_in_shift(&c, false, false, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_exec(pio, sm, offset + hub75_data_rgb888_offset_entry_point);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+// Patch a data program at `offset` to preshift pixels by `shamt`
+static inline void hub75_data_rgb888_set_shift(PIO pio, uint sm, uint offset, uint shamt) {
+    uint16_t instr;
+    if (shamt == 0)
+        instr = pio_encode_pull(false, true); // blocking PULL
+    else
+        instr = pio_encode_out(pio_null, shamt);
+    pio->instr_mem[offset + hub75_data_rgb888_offset_shift0] = instr;
+    pio->instr_mem[offset + hub75_data_rgb888_offset_shift1] = instr;
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/hub75.pio.h b/src/hal/pio/assembler/comparison_tests/hub75.pio.h
new file mode 100644
index 000000000..4d6df6945
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/hub75.pio.h
@@ -0,0 +1,138 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// --------- //
+// hub75_row //
+// --------- //
+
+#define hub75_row_wrap_target 0
+#define hub75_row_wrap 2
+
+static const uint16_t hub75_row_program_instructions[] = {
+            //     .wrap_target
+    0x7705, //  0: out    pins, 5         side 2 [7] 
+    0x7f3b, //  1: out    x, 27           side 3 [7] 
+    0x0042, //  2: jmp    x--, 2          side 0     
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program hub75_row_program = {
+    .instructions = hub75_row_program_instructions,
+    .length = 3,
+    .origin = -1,
+};
+
+static inline pio_sm_config hub75_row_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + hub75_row_wrap_target, offset + hub75_row_wrap);
+    sm_config_set_sideset(&c, 2, false, false);
+    return c;
+}
+
+static inline void hub75_row_program_init(PIO pio, uint sm, uint offset, uint row_base_pin, uint n_row_pins, uint latch_base_pin) {
+    pio_sm_set_consecutive_pindirs(pio, sm, row_base_pin, n_row_pins, true);
+    pio_sm_set_consecutive_pindirs(pio, sm, latch_base_pin, 2, true);
+    for (uint i = row_base_pin; i < row_base_pin + n_row_pins; ++i)
+        pio_gpio_init(pio, i);
+    pio_gpio_init(pio, latch_base_pin);
+    pio_gpio_init(pio, latch_base_pin + 1);
+    pio_sm_config c = hub75_row_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, row_base_pin, n_row_pins);
+    sm_config_set_sideset_pins(&c, latch_base_pin);
+    sm_config_set_out_shift(&c, true, true, 32);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+static inline void hub75_wait_tx_stall(PIO pio, uint sm) {
+    uint32_t txstall_mask = 1u << (PIO_FDEBUG_TXSTALL_LSB + sm);
+    pio->fdebug = txstall_mask;
+    while (!(pio->fdebug & txstall_mask))
+        tight_loop_contents();
+}
+
+#endif
+
+// ----------------- //
+// hub75_data_rgb888 //
+// ----------------- //
+
+#define hub75_data_rgb888_wrap_target 0
+#define hub75_data_rgb888_wrap 15
+
+#define hub75_data_rgb888_offset_entry_point 0u
+#define hub75_data_rgb888_offset_shift0 0u
+#define hub75_data_rgb888_offset_shift1 7u
+
+static const uint16_t hub75_data_rgb888_program_instructions[] = {
+            //     .wrap_target
+    0x80a0, //  0: pull   block           side 0     
+    0x40e1, //  1: in     osr, 1          side 0     
+    0x6068, //  2: out    null, 8         side 0     
+    0x40e1, //  3: in     osr, 1          side 0     
+    0x6068, //  4: out    null, 8         side 0     
+    0x40e1, //  5: in     osr, 1          side 0     
+    0x6060, //  6: out    null, 32        side 0     
+    0x80a0, //  7: pull   block           side 0     
+    0x50e1, //  8: in     osr, 1          side 1     
+    0x7068, //  9: out    null, 8         side 1     
+    0x50e1, // 10: in     osr, 1          side 1     
+    0x7068, // 11: out    null, 8         side 1     
+    0x50e1, // 12: in     osr, 1          side 1     
+    0x7060, // 13: out    null, 32        side 1     
+    0x507a, // 14: in     null, 26        side 1     
+    0xb016, // 15: mov    pins, ::isr     side 1     
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program hub75_data_rgb888_program = {
+    .instructions = hub75_data_rgb888_program_instructions,
+    .length = 16,
+    .origin = -1,
+};
+
+static inline pio_sm_config hub75_data_rgb888_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + hub75_data_rgb888_wrap_target, offset + hub75_data_rgb888_wrap);
+    sm_config_set_sideset(&c, 1, false, false);
+    return c;
+}
+
+static inline void hub75_data_rgb888_program_init(PIO pio, uint sm, uint offset, uint rgb_base_pin, uint clock_pin) {
+    pio_sm_set_consecutive_pindirs(pio, sm, rgb_base_pin, 6, true);
+    pio_sm_set_consecutive_pindirs(pio, sm, clock_pin, 1, true);
+    for (uint i = rgb_base_pin; i < rgb_base_pin + 6; ++i)
+        pio_gpio_init(pio, i);
+    pio_gpio_init(pio, clock_pin);
+    pio_sm_config c = hub75_data_rgb888_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, rgb_base_pin, 6);
+    sm_config_set_sideset_pins(&c, clock_pin);
+    sm_config_set_out_shift(&c, true, true, 24);
+    // ISR shift to left. R0 ends up at bit 5. We push it up to MSB and then flip the register.
+    sm_config_set_in_shift(&c, false, false, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_exec(pio, sm, offset + hub75_data_rgb888_offset_entry_point);
+    pio_sm_set_enabled(pio, sm, true);
+}
+// Patch a data program at `offset` to preshift pixels by `shamt`
+static inline void hub75_data_rgb888_set_shift(PIO pio, uint sm, uint offset, uint shamt) {
+    uint16_t instr;
+    if (shamt == 0)
+        instr = pio_encode_pull(false, true); // blocking PULL
+    else
+        instr = pio_encode_out(pio_null, shamt);
+    pio->instr_mem[offset + hub75_data_rgb888_offset_shift0] = instr;
+    pio->instr_mem[offset + hub75_data_rgb888_offset_shift1] = instr;
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/i2c.pio b/src/hal/pio/assembler/comparison_tests/i2c.pio
new file mode 100644
index 000000000..65f3e7834
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/i2c.pio
@@ -0,0 +1,145 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program i2c
+.side_set 1 opt pindirs
+
+; TX Encoding:
+; | 15:10 | 9     | 8:1  | 0   |
+; | Instr | Final | Data | NAK |
+;
+; If Instr has a value n > 0, then this FIFO word has no
+; data payload, and the next n + 1 words will be executed as instructions.
+; Otherwise, shift out the 8 data bits, followed by the ACK bit.
+;
+; The Instr mechanism allows stop/start/repstart sequences to be programmed
+; by the processor, and then carried out by the state machine at defined points
+; in the datastream.
+;
+; The "Final" field should be set for the final byte in a transfer.
+; This tells the state machine to ignore a NAK: if this field is not
+; set, then any NAK will cause the state machine to halt and interrupt.
+;
+; Autopull should be enabled, with a threshold of 16.
+; Autopush should be enabled, with a threshold of 8.
+; The TX FIFO should be accessed with halfword writes, to ensure
+; the data is immediately available in the OSR.
+;
+; Pin mapping:
+; - Input pin 0 is SDA, 1 is SCL (if clock stretching used)
+; - Jump pin is SDA
+; - Side-set pin 0 is SCL
+; - Set pin 0 is SDA
+; - OUT pin 0 is SDA
+; - SCL must be SDA + 1 (for wait mapping)
+;
+; The OE outputs should be inverted in the system IO controls!
+; (It's possible for the inversion to be done in this program,
+; but costs 2 instructions: 1 for inversion, and one to cope
+; with the side effect of the MOV on TX shift counter.)
+
+do_nack:
+    jmp y-- entry_point        ; Continue if NAK was expected
+    irq wait 0 rel             ; Otherwise stop, ask for help
+
+do_byte:
+    set x, 7                   ; Loop 8 times
+bitloop:
+    out pindirs, 1         [7] ; Serialise write data (all-ones if reading)
+    nop             side 1 [2] ; SCL rising edge
+    wait 1 pin, 1          [4] ; Allow clock to be stretched
+    in pins, 1             [7] ; Sample read data in middle of SCL pulse
+    jmp x-- bitloop side 0 [7] ; SCL falling edge
+
+    ; Handle ACK pulse
+    out pindirs, 1         [7] ; On reads, we provide the ACK.
+    nop             side 1 [7] ; SCL rising edge
+    wait 1 pin, 1          [7] ; Allow clock to be stretched
+    jmp pin do_nack side 0 [2] ; Test SDA for ACK/NAK, fall through if ACK
+
+public entry_point:
+.wrap_target
+    out x, 6                   ; Unpack Instr count
+    out y, 1                   ; Unpack the NAK ignore bit
+    jmp !x do_byte             ; Instr == 0, this is a data record.
+    out null, 32               ; Instr > 0, remainder of this OSR is invalid
+do_exec:
+    out exec, 16               ; Execute one instruction per FIFO word
+    jmp x-- do_exec            ; Repeat n + 1 times
+.wrap
+
+% c-sdk {
+
+#include "hardware/clocks.h"
+#include "hardware/gpio.h"
+
+
+static inline void i2c_program_init(PIO pio, uint sm, uint offset, uint pin_sda, uint pin_scl) {
+    assert(pin_scl == pin_sda + 1);
+    pio_sm_config c = i2c_program_get_default_config(offset);
+
+    // IO mapping
+    sm_config_set_out_pins(&c, pin_sda, 1);
+    sm_config_set_set_pins(&c, pin_sda, 1);
+    sm_config_set_in_pins(&c, pin_sda);
+    sm_config_set_sideset_pins(&c, pin_scl);
+    sm_config_set_jmp_pin(&c, pin_sda);
+
+    sm_config_set_out_shift(&c, false, true, 16);
+    sm_config_set_in_shift(&c, false, true, 8);
+
+    float div = (float)clock_get_hz(clk_sys) / (32 * 100000);
+    sm_config_set_clkdiv(&c, div);
+
+    // Try to avoid glitching the bus while connecting the IOs. Get things set
+    // up so that pin is driven down when PIO asserts OE low, and pulled up
+    // otherwise.
+    gpio_pull_up(pin_scl);
+    gpio_pull_up(pin_sda);
+    uint32_t both_pins = (1u << pin_sda) | (1u << pin_scl);
+    pio_sm_set_pins_with_mask(pio, sm, both_pins, both_pins);
+    pio_sm_set_pindirs_with_mask(pio, sm, both_pins, both_pins);
+    pio_gpio_init(pio, pin_sda);
+    gpio_set_oeover(pin_sda, GPIO_OVERRIDE_INVERT);
+    pio_gpio_init(pio, pin_scl);
+    gpio_set_oeover(pin_scl, GPIO_OVERRIDE_INVERT);
+    pio_sm_set_pins_with_mask(pio, sm, 0, both_pins);
+
+    // Clear IRQ flag before starting, and make sure flag doesn't actually
+    // assert a system-level interrupt (we're using it as a status flag)
+    pio_set_irq0_source_enabled(pio, pis_interrupt0 + sm, false);
+    pio_set_irq1_source_enabled(pio, pis_interrupt0 + sm, false);
+    pio_interrupt_clear(pio, sm);
+
+    // Configure and start SM
+    pio_sm_init(pio, sm, offset + i2c_offset_entry_point, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+%}
+
+
+.program set_scl_sda
+.side_set 1 opt
+
+; Assemble a table of instructions which software can select from, and pass
+; into the FIFO, to issue START/STOP/RSTART. This isn't intended to be run as
+; a complete program.
+
+    set pindirs, 0 side 0 [7] ; SCL = 0, SDA = 0
+    set pindirs, 1 side 0 [7] ; SCL = 0, SDA = 1
+    set pindirs, 0 side 1 [7] ; SCL = 1, SDA = 0
+    set pindirs, 1 side 1 [7] ; SCL = 1, SDA = 1
+
+% c-sdk {
+// Define order of our instruction table
+enum {
+    I2C_SC0_SD0 = 0,
+    I2C_SC0_SD1,
+    I2C_SC1_SD0,
+    I2C_SC1_SD1
+};
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/i2c.pio.h b/src/hal/pio/assembler/comparison_tests/i2c.pio.h
new file mode 100644
index 000000000..5c470395a
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/i2c.pio.h
@@ -0,0 +1,136 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// --- //
+// i2c //
+// --- //
+
+#define i2c_wrap_target 12
+#define i2c_wrap 17
+
+#define i2c_offset_entry_point 12u
+
+static const uint16_t i2c_program_instructions[] = {
+    0x008c, //  0: jmp    y--, 12                    
+    0xc030, //  1: irq    wait 0 rel                 
+    0xe027, //  2: set    x, 7                       
+    0x6781, //  3: out    pindirs, 1             [7] 
+    0xba42, //  4: nop                    side 1 [2] 
+    0x24a1, //  5: wait   1 pin, 1               [4] 
+    0x4701, //  6: in     pins, 1                [7] 
+    0x1743, //  7: jmp    x--, 3          side 0 [7] 
+    0x6781, //  8: out    pindirs, 1             [7] 
+    0xbf42, //  9: nop                    side 1 [7] 
+    0x27a1, // 10: wait   1 pin, 1               [7] 
+    0x12c0, // 11: jmp    pin, 0          side 0 [2] 
+            //     .wrap_target
+    0x6026, // 12: out    x, 6                       
+    0x6041, // 13: out    y, 1                       
+    0x0022, // 14: jmp    !x, 2                      
+    0x6060, // 15: out    null, 32                   
+    0x60f0, // 16: out    exec, 16                   
+    0x0050, // 17: jmp    x--, 16                    
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program i2c_program = {
+    .instructions = i2c_program_instructions,
+    .length = 18,
+    .origin = -1,
+};
+
+static inline pio_sm_config i2c_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + i2c_wrap_target, offset + i2c_wrap);
+    sm_config_set_sideset(&c, 2, true, true);
+    return c;
+}
+
+#include "hardware/clocks.h"
+#include "hardware/gpio.h"
+static inline void i2c_program_init(PIO pio, uint sm, uint offset, uint pin_sda, uint pin_scl) {
+    assert(pin_scl == pin_sda + 1);
+    pio_sm_config c = i2c_program_get_default_config(offset);
+    // IO mapping
+    sm_config_set_out_pins(&c, pin_sda, 1);
+    sm_config_set_set_pins(&c, pin_sda, 1);
+    sm_config_set_in_pins(&c, pin_sda);
+    sm_config_set_sideset_pins(&c, pin_scl);
+    sm_config_set_jmp_pin(&c, pin_sda);
+    sm_config_set_out_shift(&c, false, true, 16);
+    sm_config_set_in_shift(&c, false, true, 8);
+    float div = (float)clock_get_hz(clk_sys) / (32 * 100000);
+    sm_config_set_clkdiv(&c, div);
+    // Try to avoid glitching the bus while connecting the IOs. Get things set
+    // up so that pin is driven down when PIO asserts OE low, and pulled up
+    // otherwise.
+    gpio_pull_up(pin_scl);
+    gpio_pull_up(pin_sda);
+    uint32_t both_pins = (1u << pin_sda) | (1u << pin_scl);
+    pio_sm_set_pins_with_mask(pio, sm, both_pins, both_pins);
+    pio_sm_set_pindirs_with_mask(pio, sm, both_pins, both_pins);
+    pio_gpio_init(pio, pin_sda);
+    gpio_set_oeover(pin_sda, GPIO_OVERRIDE_INVERT);
+    pio_gpio_init(pio, pin_scl);
+    gpio_set_oeover(pin_scl, GPIO_OVERRIDE_INVERT);
+    pio_sm_set_pins_with_mask(pio, sm, 0, both_pins);
+    // Clear IRQ flag before starting, and make sure flag doesn't actually
+    // assert a system-level interrupt (we're using it as a status flag)
+    pio_set_irq0_source_enabled(pio, pis_interrupt0 + sm, false);
+    pio_set_irq1_source_enabled(pio, pis_interrupt0 + sm, false);
+    pio_interrupt_clear(pio, sm);
+    // Configure and start SM
+    pio_sm_init(pio, sm, offset + i2c_offset_entry_point, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
+// ----------- //
+// set_scl_sda //
+// ----------- //
+
+#define set_scl_sda_wrap_target 0
+#define set_scl_sda_wrap 3
+
+static const uint16_t set_scl_sda_program_instructions[] = {
+            //     .wrap_target
+    0xf780, //  0: set    pindirs, 0      side 0 [7] 
+    0xf781, //  1: set    pindirs, 1      side 0 [7] 
+    0xff80, //  2: set    pindirs, 0      side 1 [7] 
+    0xff81, //  3: set    pindirs, 1      side 1 [7] 
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program set_scl_sda_program = {
+    .instructions = set_scl_sda_program_instructions,
+    .length = 4,
+    .origin = -1,
+};
+
+static inline pio_sm_config set_scl_sda_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + set_scl_sda_wrap_target, offset + set_scl_sda_wrap);
+    sm_config_set_sideset(&c, 2, true, false);
+    return c;
+}
+
+// Define order of our instruction table
+enum {
+    I2C_SC0_SD0 = 0,
+    I2C_SC0_SD1,
+    I2C_SC1_SD0,
+    I2C_SC1_SD1
+};
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/manchester_encoding.pio b/src/hal/pio/assembler/comparison_tests/manchester_encoding.pio
new file mode 100644
index 000000000..0117d2a35
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/manchester_encoding.pio
@@ -0,0 +1,94 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program manchester_tx
+.side_set 1 opt
+
+; Transmit one bit every 12 cycles. a '0' is encoded as a high-low sequence
+; (each part lasting half a bit period, or 6 cycles) and a '1' is encoded as a
+; low-high sequence.
+;
+; Side-set bit 0 must be mapped to the GPIO used for TX.
+; Autopull must be enabled -- this program does not care about the threshold.
+; The program starts at the public label 'start'.
+
+.wrap_target
+do_1:
+    nop         side 0 [5] ; Low for 6 cycles (5 delay, +1 for nop)
+    jmp get_bit side 1 [3] ; High for 4 cycles. 'get_bit' takes another 2 cycles
+do_0:
+    nop         side 1 [5] ; Output high for 6 cycles
+    nop         side 0 [3] ; Output low for 4 cycles
+public start:
+get_bit:
+    out x, 1               ; Always shift out one bit from OSR to X, so we can
+    jmp !x do_0            ; branch on it. Autopull refills the OSR when empty.
+.wrap
+
+% c-sdk {
+static inline void manchester_tx_program_init(PIO pio, uint sm, uint offset, uint pin, float div) {
+    pio_sm_set_pins_with_mask(pio, sm, 0, 1u << pin);
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+    pio_gpio_init(pio, pin);
+
+    pio_sm_config c = manchester_tx_program_get_default_config(offset);
+    sm_config_set_sideset_pins(&c, pin);
+    sm_config_set_out_shift(&c, true, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset + manchester_tx_offset_start, &c);
+
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
+
+.program manchester_rx
+
+; Assumes line is idle low, first bit is 0
+; One bit is 12 cycles
+; a '0' is encoded as 10
+; a '1' is encoded as 01
+;
+; Both the IN base and the JMP pin mapping must be pointed at the GPIO used for RX.
+; Autopush must be enabled.
+; Before enabling the SM, it should be placed in a 'wait 1, pin` state, so that
+; it will not start sampling until the initial line idle state ends.
+
+start_of_0:            ; We are 0.25 bits into a 0 - signal is high
+    wait 0 pin 0       ; Wait for the 1->0 transition - at this point we are 0.5 into the bit
+    in y, 1 [8]        ; Emit a 0, sleep 3/4 of a bit
+    jmp pin start_of_0 ; If signal is 1 again, it's another 0 bit, otherwise it's a 1
+
+.wrap_target
+start_of_1:            ; We are 0.25 bits into a 1 - signal is 1   
+    wait 1 pin 0       ; Wait for the 0->1 transition - at this point we are 0.5 into the bit
+    in x, 1 [8]        ; Emit a 1, sleep 3/4 of a bit
+    jmp pin start_of_0 ; If signal is 0 again, it's another 1 bit otherwise it's a 0
+.wrap
+
+% c-sdk {
+static inline void manchester_rx_program_init(PIO pio, uint sm, uint offset, uint pin, float div) {
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    pio_gpio_init(pio, pin);
+
+    pio_sm_config c = manchester_rx_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, pin); // for WAIT
+    sm_config_set_jmp_pin(&c, pin); // for JMP
+    sm_config_set_in_shift(&c, true, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset, &c);
+
+    // X and Y are set to 0 and 1, to conveniently emit these to ISR/FIFO.
+    pio_sm_exec(pio, sm, pio_encode_set(pio_x, 1));
+    pio_sm_exec(pio, sm, pio_encode_set(pio_y, 0));
+    // Assume line is idle low, and first transmitted bit is 0. Put SM in a
+    // wait state before enabling. RX will begin once the first 0 symbol is
+    // detected.
+    pio_sm_exec(pio, sm, pio_encode_wait_pin(1, 0) | pio_encode_delay(2));
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/manchester_encoding.pio.h b/src/hal/pio/assembler/comparison_tests/manchester_encoding.pio.h
new file mode 100644
index 000000000..ee0088680
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/manchester_encoding.pio.h
@@ -0,0 +1,112 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ------------- //
+// manchester_tx //
+// ------------- //
+
+#define manchester_tx_wrap_target 0
+#define manchester_tx_wrap 5
+
+#define manchester_tx_offset_start 4u
+
+static const uint16_t manchester_tx_program_instructions[] = {
+            //     .wrap_target
+    0xb542, //  0: nop                    side 0 [5] 
+    0x1b04, //  1: jmp    4               side 1 [3] 
+    0xbd42, //  2: nop                    side 1 [5] 
+    0xb342, //  3: nop                    side 0 [3] 
+    0x6021, //  4: out    x, 1                       
+    0x0022, //  5: jmp    !x, 2                      
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program manchester_tx_program = {
+    .instructions = manchester_tx_program_instructions,
+    .length = 6,
+    .origin = -1,
+};
+
+static inline pio_sm_config manchester_tx_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + manchester_tx_wrap_target, offset + manchester_tx_wrap);
+    sm_config_set_sideset(&c, 2, true, false);
+    return c;
+}
+
+static inline void manchester_tx_program_init(PIO pio, uint sm, uint offset, uint pin, float div) {
+    pio_sm_set_pins_with_mask(pio, sm, 0, 1u << pin);
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+    pio_gpio_init(pio, pin);
+    pio_sm_config c = manchester_tx_program_get_default_config(offset);
+    sm_config_set_sideset_pins(&c, pin);
+    sm_config_set_out_shift(&c, true, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset + manchester_tx_offset_start, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
+// ------------- //
+// manchester_rx //
+// ------------- //
+
+#define manchester_rx_wrap_target 3
+#define manchester_rx_wrap 5
+
+static const uint16_t manchester_rx_program_instructions[] = {
+    0x2020, //  0: wait   0 pin, 0                   
+    0x4841, //  1: in     y, 1                   [8] 
+    0x00c0, //  2: jmp    pin, 0                     
+            //     .wrap_target
+    0x20a0, //  3: wait   1 pin, 0                   
+    0x4821, //  4: in     x, 1                   [8] 
+    0x00c0, //  5: jmp    pin, 0                     
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program manchester_rx_program = {
+    .instructions = manchester_rx_program_instructions,
+    .length = 6,
+    .origin = -1,
+};
+
+static inline pio_sm_config manchester_rx_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + manchester_rx_wrap_target, offset + manchester_rx_wrap);
+    return c;
+}
+
+static inline void manchester_rx_program_init(PIO pio, uint sm, uint offset, uint pin, float div) {
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    pio_gpio_init(pio, pin);
+    pio_sm_config c = manchester_rx_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, pin); // for WAIT
+    sm_config_set_jmp_pin(&c, pin); // for JMP
+    sm_config_set_in_shift(&c, true, true, 32);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset, &c);
+    // X and Y are set to 0 and 1, to conveniently emit these to ISR/FIFO.
+    pio_sm_exec(pio, sm, pio_encode_set(pio_x, 1));
+    pio_sm_exec(pio, sm, pio_encode_set(pio_y, 0));
+    // Assume line is idle low, and first transmitted bit is 0. Put SM in a
+    // wait state before enabling. RX will begin once the first 0 symbol is
+    // detected.
+    pio_sm_exec(pio, sm, pio_encode_wait_pin(1, 0) | pio_encode_delay(2));
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/nec_carrier_burst.pio b/src/hal/pio/assembler/comparison_tests/nec_carrier_burst.pio
new file mode 100644
index 000000000..499e892fc
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/nec_carrier_burst.pio
@@ -0,0 +1,61 @@
+;
+; Copyright (c) 2021 mjcross
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+
+.program nec_carrier_burst
+
+; Generate bursts of carrier.
+;
+; Repeatedly wait for an IRQ to be set then clear it and generate 21 cycles of
+; carrier with 25% duty cycle
+;
+.define NUM_CYCLES 21               ; how many carrier cycles to generate
+.define BURST_IRQ 7                 ; which IRQ should trigger a carrier burst
+.define public TICKS_PER_LOOP 4     ; the number of instructions in the loop (for timing)
+
+.wrap_target
+    set X, (NUM_CYCLES - 1)         ; initialise the loop counter
+    wait 1 irq BURST_IRQ            ; wait for the IRQ then clear it
+cycle_loop:
+    set pins, 1                     ; set the pin high (1 cycle)
+    set pins, 0 [1]                 ; set the pin low (2 cycles)
+    jmp X--, cycle_loop             ; (1 more cycle)
+.wrap
+
+
+% c-sdk {
+static inline void nec_carrier_burst_program_init(PIO pio, uint sm, uint offset, uint pin, float freq) {
+    // Create a new state machine configuration
+    //
+    pio_sm_config c = nec_carrier_burst_program_get_default_config (offset);
+
+    // Map the SET pin group to one pin, namely the `pin`
+    // parameter to this function.
+    //
+    sm_config_set_set_pins (&c, pin, 1);
+
+    // Set the GPIO function of the pin (connect the PIO to the pad)
+    //
+    pio_gpio_init (pio, pin);
+
+    // Set the pin direction to output at the PIO
+    //
+    pio_sm_set_consecutive_pindirs (pio, sm, pin, 1, true);
+
+    // Set the clock divider to generate the required frequency
+    //
+    float div = clock_get_hz (clk_sys) / (freq * nec_carrier_burst_TICKS_PER_LOOP);
+    sm_config_set_clkdiv (&c, div);
+
+    // Apply the configuration to the state machine
+    //
+    pio_sm_init (pio, sm, offset, &c);
+
+    // Set the state machine running
+    //
+    pio_sm_set_enabled (pio, sm, true);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/nec_carrier_burst.pio.h b/src/hal/pio/assembler/comparison_tests/nec_carrier_burst.pio.h
new file mode 100644
index 000000000..5fa001492
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/nec_carrier_burst.pio.h
@@ -0,0 +1,70 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ----------------- //
+// nec_carrier_burst //
+// ----------------- //
+
+#define nec_carrier_burst_wrap_target 0
+#define nec_carrier_burst_wrap 4
+
+#define nec_carrier_burst_TICKS_PER_LOOP 4
+
+static const uint16_t nec_carrier_burst_program_instructions[] = {
+            //     .wrap_target
+    0xe034, //  0: set    x, 20                      
+    0x20c7, //  1: wait   1 irq, 7                   
+    0xe001, //  2: set    pins, 1                    
+    0xe100, //  3: set    pins, 0                [1] 
+    0x0042, //  4: jmp    x--, 2                     
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program nec_carrier_burst_program = {
+    .instructions = nec_carrier_burst_program_instructions,
+    .length = 5,
+    .origin = -1,
+};
+
+static inline pio_sm_config nec_carrier_burst_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + nec_carrier_burst_wrap_target, offset + nec_carrier_burst_wrap);
+    return c;
+}
+
+static inline void nec_carrier_burst_program_init(PIO pio, uint sm, uint offset, uint pin, float freq) {
+    // Create a new state machine configuration
+    //
+    pio_sm_config c = nec_carrier_burst_program_get_default_config (offset);
+    // Map the SET pin group to one pin, namely the `pin`
+    // parameter to this function.
+    //
+    sm_config_set_set_pins (&c, pin, 1);
+    // Set the GPIO function of the pin (connect the PIO to the pad)
+    //
+    pio_gpio_init (pio, pin);
+    // Set the pin direction to output at the PIO
+    //
+    pio_sm_set_consecutive_pindirs (pio, sm, pin, 1, true);
+    // Set the clock divider to generate the required frequency
+    //
+    float div = clock_get_hz (clk_sys) / (freq * nec_carrier_burst_TICKS_PER_LOOP);
+    sm_config_set_clkdiv (&c, div);
+    // Apply the configuration to the state machine
+    //
+    pio_sm_init (pio, sm, offset, &c);
+    // Set the state machine running
+    //
+    pio_sm_set_enabled (pio, sm, true);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/nec_carrier_control.pio b/src/hal/pio/assembler/comparison_tests/nec_carrier_control.pio
new file mode 100644
index 000000000..0733afef0
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/nec_carrier_control.pio
@@ -0,0 +1,79 @@
+;
+; Copyright (c) 2021 mjcross
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+
+.program nec_carrier_control
+
+; Transmit an encoded 32-bit frame in NEC IR format.
+;
+; Accepts 32-bit words from the transmit FIFO and sends them least-significant bit first
+; using pulse position modulation.
+;
+; Carrier bursts are generated using the nec_carrier_burst program, which is expected to be
+; running on a separate state machine.
+;
+; This program expects there to be 2 state machine ticks per 'normal' 562.5us
+; burst period.
+;
+.define BURST_IRQ 7                     ; the IRQ used to trigger a carrier burst
+.define NUM_INITIAL_BURSTS 16           ; how many bursts to transmit for a 'sync burst'
+
+.wrap_target
+    pull                                ; fetch a data word from the transmit FIFO into the
+                                        ; output shift register, blocking if the FIFO is empty
+
+    set X, (NUM_INITIAL_BURSTS - 1)     ; send a sync burst (9ms)
+long_burst:
+    irq BURST_IRQ
+    jmp X-- long_burst
+
+    nop [15]                            ; send a 4.5ms space
+    irq BURST_IRQ [1]                   ; send a 562.5us burst to begin the first data bit
+
+data_bit:
+    out X, 1                            ; shift the least-significant bit from the OSR
+    jmp !X burst                        ; send a short delay for a '0' bit
+    nop [3]                             ; send an additional delay for a '1' bit
+burst:
+    irq BURST_IRQ                       ; send a 562.5us burst to end the data bit
+
+jmp !OSRE data_bit                      ; continue sending bits until the OSR is empty
+
+.wrap                                   ; fetch another data word from the FIFO
+
+
+% c-sdk {
+static inline void nec_carrier_control_program_init (PIO pio, uint sm, uint offset, float tick_rate, int bits_per_frame) {
+
+    // create a new state machine configuration
+    //
+    pio_sm_config c = nec_carrier_control_program_get_default_config(offset);
+
+    // configure the output shift register
+    //
+    sm_config_set_out_shift (&c,
+                             true,       // shift right
+                             false,      // disable autopull
+                             bits_per_frame);
+
+    // join the FIFOs to make a single large transmit FIFO
+    //
+    sm_config_set_fifo_join (&c, PIO_FIFO_JOIN_TX);
+
+    // configure the clock divider
+    //
+    float div = clock_get_hz (clk_sys) / tick_rate;
+    sm_config_set_clkdiv (&c, div);
+
+    // apply the configuration to the state machine
+    //
+    pio_sm_init(pio, sm, offset, &c);
+
+    // set the state machine running
+    //
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/nec_carrier_control.pio.h b/src/hal/pio/assembler/comparison_tests/nec_carrier_control.pio.h
new file mode 100644
index 000000000..8c9a3059b
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/nec_carrier_control.pio.h
@@ -0,0 +1,73 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ------------------- //
+// nec_carrier_control //
+// ------------------- //
+
+#define nec_carrier_control_wrap_target 0
+#define nec_carrier_control_wrap 10
+
+static const uint16_t nec_carrier_control_program_instructions[] = {
+            //     .wrap_target
+    0x80a0, //  0: pull   block                      
+    0xe02f, //  1: set    x, 15                      
+    0xc007, //  2: irq    nowait 7                   
+    0x0042, //  3: jmp    x--, 2                     
+    0xaf42, //  4: nop                           [15]
+    0xc107, //  5: irq    nowait 7               [1] 
+    0x6021, //  6: out    x, 1                       
+    0x0029, //  7: jmp    !x, 9                      
+    0xa342, //  8: nop                           [3] 
+    0xc007, //  9: irq    nowait 7                   
+    0x00e6, // 10: jmp    !osre, 6                   
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program nec_carrier_control_program = {
+    .instructions = nec_carrier_control_program_instructions,
+    .length = 11,
+    .origin = -1,
+};
+
+static inline pio_sm_config nec_carrier_control_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + nec_carrier_control_wrap_target, offset + nec_carrier_control_wrap);
+    return c;
+}
+
+static inline void nec_carrier_control_program_init (PIO pio, uint sm, uint offset, float tick_rate, int bits_per_frame) {
+    // create a new state machine configuration
+    //
+    pio_sm_config c = nec_carrier_control_program_get_default_config(offset);
+    // configure the output shift register
+    //
+    sm_config_set_out_shift (&c,
+                             true,       // shift right
+                             false,      // disable autopull
+                             bits_per_frame);
+    // join the FIFOs to make a single large transmit FIFO
+    //
+    sm_config_set_fifo_join (&c, PIO_FIFO_JOIN_TX);
+    // configure the clock divider
+    //
+    float div = clock_get_hz (clk_sys) / tick_rate;
+    sm_config_set_clkdiv (&c, div);
+    // apply the configuration to the state machine
+    //
+    pio_sm_init(pio, sm, offset, &c);
+    // set the state machine running
+    //
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/nec_receive.pio b/src/hal/pio/assembler/comparison_tests/nec_receive.pio
new file mode 100644
index 000000000..a2c5f5e70
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/nec_receive.pio
@@ -0,0 +1,96 @@
+;
+; Copyright (c) 2021 mjcross
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+
+.program nec_receive
+
+; Decode IR frames in NEC format and push 32-bit words to the input FIFO.
+;
+; The input pin should be connected to an IR detector with an 'active low' output.
+;
+; This program expects there to be 10 state machine clock ticks per 'normal' 562.5us burst period
+; in order to permit timely detection of start of a burst. The initailisation function below sets
+; the correct divisor to achive this relative to the system clock.
+;
+; Within the 'NEC' protocol frames consists of 32 bits sent least-siginificant bit first; so the
+; Input Shift Register should be configured to shift right and autopush after 32 bits, as in the
+; initialisation function below.
+;
+.define BURST_LOOP_COUNTER 30                   ; the detection threshold for a 'frame sync' burst
+.define BIT_SAMPLE_DELAY 15                     ; how long to wait after the end of the burst before sampling
+
+.wrap_target
+
+next_burst:
+    set X, BURST_LOOP_COUNTER
+    wait 0 pin 0                                ; wait for the next burst to start
+
+burst_loop:
+    jmp pin data_bit                            ; the burst ended before the counter expired
+    jmp X-- burst_loop                          ; wait for the burst to end
+
+                                                ; the counter expired - this is a sync burst
+    mov ISR, NULL                               ; reset the Input Shift Register
+    wait 1 pin 0                                ; wait for the sync burst to finish
+    jmp next_burst                              ; wait for the first data bit
+
+data_bit:
+    nop [ BIT_SAMPLE_DELAY - 1 ]                ; wait for 1.5 burst periods before sampling the bit value
+    in PINS, 1                                  ; if the next burst has started then detect a '0' (short gap)
+                                                ; otherwise detect a '1' (long gap)
+                                                ; after 32 bits the ISR will autopush to the receive FIFO
+.wrap
+
+
+% c-sdk {
+static inline void nec_receive_program_init (PIO pio, uint sm, uint offset, uint pin) {
+
+    // Set the GPIO function of the pin (connect the PIO to the pad)
+    //
+    pio_gpio_init(pio, pin);
+
+    // Set the pin direction to `input` at the PIO
+    //
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+
+    // Create a new state machine configuration
+    //
+    pio_sm_config c = nec_receive_program_get_default_config (offset);
+
+    // configure the Input Shift Register
+    //
+    sm_config_set_in_shift (&c,
+                            true,       // shift right
+                            true,       // enable autopush
+                            32);        // autopush after 32 bits
+
+    // join the FIFOs to make a single large receive FIFO
+    //
+    sm_config_set_fifo_join (&c, PIO_FIFO_JOIN_RX);
+
+    // Map the IN pin group to one pin, namely the `pin`
+    // parameter to this function.
+    //
+    sm_config_set_in_pins (&c, pin);
+
+    // Map the JMP pin to the `pin` parameter of this function.
+    //
+    sm_config_set_jmp_pin (&c, pin);
+
+    // Set the clock divider to 10 ticks per 562.5us burst period
+    //
+    float div = clock_get_hz (clk_sys) / (10.0 / 562.5e-6);
+    sm_config_set_clkdiv (&c, div);
+
+    // Apply the configuration to the state machine
+    //
+    pio_sm_init (pio, sm, offset, &c);
+
+    // Set the state machine running
+    //
+    pio_sm_set_enabled (pio, sm, true);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/nec_receive.pio.h b/src/hal/pio/assembler/comparison_tests/nec_receive.pio.h
new file mode 100644
index 000000000..e9611b67a
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/nec_receive.pio.h
@@ -0,0 +1,84 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ----------- //
+// nec_receive //
+// ----------- //
+
+#define nec_receive_wrap_target 0
+#define nec_receive_wrap 8
+
+static const uint16_t nec_receive_program_instructions[] = {
+            //     .wrap_target
+    0xe03e, //  0: set    x, 30                      
+    0x2020, //  1: wait   0 pin, 0                   
+    0x00c7, //  2: jmp    pin, 7                     
+    0x0042, //  3: jmp    x--, 2                     
+    0xa0c3, //  4: mov    isr, null                  
+    0x20a0, //  5: wait   1 pin, 0                   
+    0x0000, //  6: jmp    0                          
+    0xae42, //  7: nop                           [14]
+    0x4001, //  8: in     pins, 1                    
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program nec_receive_program = {
+    .instructions = nec_receive_program_instructions,
+    .length = 9,
+    .origin = -1,
+};
+
+static inline pio_sm_config nec_receive_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + nec_receive_wrap_target, offset + nec_receive_wrap);
+    return c;
+}
+
+static inline void nec_receive_program_init (PIO pio, uint sm, uint offset, uint pin) {
+    // Set the GPIO function of the pin (connect the PIO to the pad)
+    //
+    pio_gpio_init(pio, pin);
+    // Set the pin direction to `input` at the PIO
+    //
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    // Create a new state machine configuration
+    //
+    pio_sm_config c = nec_receive_program_get_default_config (offset);
+    // configure the Input Shift Register
+    //
+    sm_config_set_in_shift (&c,
+                            true,       // shift right
+                            true,       // enable autopush
+                            32);        // autopush after 32 bits
+    // join the FIFOs to make a single large receive FIFO
+    //
+    sm_config_set_fifo_join (&c, PIO_FIFO_JOIN_RX);
+    // Map the IN pin group to one pin, namely the `pin`
+    // parameter to this function.
+    //
+    sm_config_set_in_pins (&c, pin);
+    // Map the JMP pin to the `pin` parameter of this function.
+    //
+    sm_config_set_jmp_pin (&c, pin);
+    // Set the clock divider to 10 ticks per 562.5us burst period
+    //
+    float div = clock_get_hz (clk_sys) / (10.0 / 562.5e-6);
+    sm_config_set_clkdiv (&c, div);
+    // Apply the configuration to the state machine
+    //
+    pio_sm_init (pio, sm, offset, &c);
+    // Set the state machine running
+    //
+    pio_sm_set_enabled (pio, sm, true);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/pio_serialiser.pio b/src/hal/pio/assembler/comparison_tests/pio_serialiser.pio
new file mode 100644
index 000000000..67a6866ab
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/pio_serialiser.pio
@@ -0,0 +1,27 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program pio_serialiser
+
+; Just serialise a stream of bits. Take 32 bits from each FIFO record. LSB-first.
+
+.wrap_target
+    out pins, 1
+.wrap
+
+% c-sdk {
+static inline void pio_serialiser_program_init(PIO pio, uint sm, uint offset, uint data_pin, float clk_div) {
+    pio_gpio_init(pio, data_pin);
+    pio_sm_set_consecutive_pindirs(pio, sm, data_pin, 1, true);
+    pio_sm_config c = pio_serialiser_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, data_pin, 1);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    sm_config_set_clkdiv(&c, clk_div);
+    sm_config_set_out_shift(&c, true, true, 32);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/pio_serialiser.pio.h b/src/hal/pio/assembler/comparison_tests/pio_serialiser.pio.h
new file mode 100644
index 000000000..062758540
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/pio_serialiser.pio.h
@@ -0,0 +1,50 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// -------------- //
+// pio_serialiser //
+// -------------- //
+
+#define pio_serialiser_wrap_target 0
+#define pio_serialiser_wrap 0
+
+static const uint16_t pio_serialiser_program_instructions[] = {
+            //     .wrap_target
+    0x6001, //  0: out    pins, 1                    
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program pio_serialiser_program = {
+    .instructions = pio_serialiser_program_instructions,
+    .length = 1,
+    .origin = -1,
+};
+
+static inline pio_sm_config pio_serialiser_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + pio_serialiser_wrap_target, offset + pio_serialiser_wrap);
+    return c;
+}
+
+static inline void pio_serialiser_program_init(PIO pio, uint sm, uint offset, uint data_pin, float clk_div) {
+    pio_gpio_init(pio, data_pin);
+    pio_sm_set_consecutive_pindirs(pio, sm, data_pin, 1, true);
+    pio_sm_config c = pio_serialiser_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, data_pin, 1);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    sm_config_set_clkdiv(&c, clk_div);
+    sm_config_set_out_shift(&c, true, true, 32);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/pwm.pio b/src/hal/pio/assembler/comparison_tests/pwm.pio
new file mode 100644
index 000000000..d0f2bcbf2
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/pwm.pio
@@ -0,0 +1,31 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+; Side-set pin 0 is used for PWM output
+
+.program pwm
+.side_set 1 opt
+
+    pull noblock    side 0 ; Pull from FIFO to OSR if available, else copy X to OSR.
+    mov x, osr             ; Copy most-recently-pulled value back to scratch X
+    mov y, isr             ; ISR contains PWM period. Y used as counter.
+countloop:
+    jmp x!=y noset         ; Set pin high if X == Y, keep the two paths length matched
+    jmp skip        side 1
+noset:
+    nop                    ; Single dummy cycle to keep the two paths the same length
+skip:
+    jmp y-- countloop      ; Loop until Y hits 0, then pull a fresh PWM value from FIFO
+
+% c-sdk {
+static inline void pwm_program_init(PIO pio, uint sm, uint offset, uint pin) {
+   pio_gpio_init(pio, pin);
+   pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+   pio_sm_config c = pwm_program_get_default_config(offset);
+   sm_config_set_sideset_pins(&c, pin);
+   pio_sm_init(pio, sm, offset, &c);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/pwm.pio.h b/src/hal/pio/assembler/comparison_tests/pwm.pio.h
new file mode 100644
index 000000000..7d738a020
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/pwm.pio.h
@@ -0,0 +1,53 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// --- //
+// pwm //
+// --- //
+
+#define pwm_wrap_target 0
+#define pwm_wrap 6
+
+static const uint16_t pwm_program_instructions[] = {
+            //     .wrap_target
+    0x9080, //  0: pull   noblock         side 0     
+    0xa027, //  1: mov    x, osr                     
+    0xa046, //  2: mov    y, isr                     
+    0x00a5, //  3: jmp    x != y, 5                  
+    0x1806, //  4: jmp    6               side 1     
+    0xa042, //  5: nop                               
+    0x0083, //  6: jmp    y--, 3                     
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program pwm_program = {
+    .instructions = pwm_program_instructions,
+    .length = 7,
+    .origin = -1,
+};
+
+static inline pio_sm_config pwm_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + pwm_wrap_target, offset + pwm_wrap);
+    sm_config_set_sideset(&c, 2, true, false);
+    return c;
+}
+
+static inline void pwm_program_init(PIO pio, uint sm, uint offset, uint pin) {
+   pio_gpio_init(pio, pin);
+   pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+   pio_sm_config c = pwm_program_get_default_config(offset);
+   sm_config_set_sideset_pins(&c, pin);
+   pio_sm_init(pio, sm, offset, &c);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/quadrature_encoder.pio b/src/hal/pio/assembler/comparison_tests/quadrature_encoder.pio
new file mode 100644
index 000000000..d245d4b69
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/quadrature_encoder.pio
@@ -0,0 +1,165 @@
+;
+; Copyright (c) 2021 pmarques-dev @ github
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program quadrature_encoder
+
+; this code must be loaded into address 0, but at 29 instructions, it probably
+; wouldn't be able to share space with other programs anyway
+.origin 0
+
+
+; the code works by running a loop that continuously shifts the 2 phase pins into
+; ISR and looks at the lower 4 bits to do a computed jump to an instruction that
+; does the proper "do nothing" | "increment" | "decrement" action for that pin
+; state change (or no change)
+
+; ISR holds the last state of the 2 pins during most of the code. The Y register
+; keeps the current encoder count and is incremented / decremented according to
+; the steps sampled
+
+; writing any non zero value to the TX FIFO makes the state machine push the
+; current count to RX FIFO between 6 to 18 clocks afterwards. The worst case
+; sampling loop takes 14 cycles, so this program is able to read step rates up
+; to sysclk / 14  (e.g., sysclk 125MHz, max step rate = 8.9 Msteps/sec)
+
+
+; 00 state
+	JMP update	; read 00
+	JMP decrement	; read 01
+	JMP increment	; read 10
+	JMP update	; read 11
+
+; 01 state
+	JMP increment	; read 00
+	JMP update	; read 01
+	JMP update	; read 10
+	JMP decrement	; read 11
+
+; 10 state
+	JMP decrement	; read 00
+	JMP update	; read 01
+	JMP update	; read 10
+	JMP increment	; read 11
+
+; to reduce code size, the last 2 states are implemented in place and become the
+; target for the other jumps
+
+; 11 state
+	JMP update	; read 00
+	JMP increment	; read 01
+decrement:
+	; note: the target of this instruction must be the next address, so that
+	; the effect of the instruction does not depend on the value of Y. The
+	; same is true for the "JMP X--" below. Basically "JMP Y--, "
+	; is just a pure "decrement Y" instruction, with no other side effects
+	JMP Y--, update	; read 10
+
+	; this is where the main loop starts
+.wrap_target
+update:
+	; we start by checking the TX FIFO to see if the main code is asking for
+	; the current count after the PULL noblock, OSR will have either 0 if
+	; there was nothing or the value that was there
+	SET X, 0
+	PULL noblock
+
+	; since there are not many free registers, and PULL is done into OSR, we
+	; have to do some juggling to avoid losing the state information and
+	; still place the values where we need them
+	MOV X, OSR
+	MOV OSR, ISR
+
+	; the main code did not ask for the count, so just go to "sample_pins"
+	JMP !X, sample_pins
+
+	; if it did ask for the count, then we push it
+	MOV ISR, Y	; we trash ISR, but we already have a copy in OSR
+	PUSH
+
+sample_pins:
+	; we shift into ISR the last state of the 2 input pins (now in OSR) and
+	; the new state of the 2 pins, thus producing the 4 bit target for the
+	; computed jump into the correct action for this state
+	MOV ISR, NULL
+	IN OSR, 2
+	IN PINS, 2
+	MOV PC, ISR
+
+	; the PIO does not have a increment instruction, so to do that we do a
+	; negate, decrement, negate sequence
+increment:
+	MOV X, !Y
+	JMP X--, increment_cont
+increment_cont:
+	MOV Y, !X
+.wrap	; the .wrap here avoids one jump instruction and saves a cycle too
+
+
+
+% c-sdk {
+
+#include "hardware/clocks.h"
+#include "hardware/gpio.h"
+
+// max_step_rate is used to lower the clock of the state machine to save power
+// if the application doesn't require a very high sampling rate. Passing zero
+// will set the clock to the maximum, which gives a max step rate of around
+// 8.9 Msteps/sec at 125MHz
+
+static inline void quadrature_encoder_program_init(PIO pio, uint sm, uint offset, uint pin, int max_step_rate)
+{
+	pio_sm_set_consecutive_pindirs(pio, sm, pin, 2, false);
+	gpio_pull_up(pin);
+	gpio_pull_up(pin + 1);
+
+	pio_sm_config c = quadrature_encoder_program_get_default_config(offset);
+	sm_config_set_in_pins(&c, pin); // for WAIT, IN
+	sm_config_set_jmp_pin(&c, pin); // for JMP
+	// shift to left, autopull disabled
+	sm_config_set_in_shift(&c, false, false, 32);
+	// don't join FIFO's
+	sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_NONE);
+
+	// passing "0" as the sample frequency,
+	if (max_step_rate == 0) {
+		sm_config_set_clkdiv(&c, 1.0);
+	} else {
+		// one state machine loop takes at most 14 cycles
+		float div = (float)clock_get_hz(clk_sys) / (14 * max_step_rate);
+		sm_config_set_clkdiv(&c, div);
+	}
+
+	pio_sm_init(pio, sm, offset, &c);
+	pio_sm_set_enabled(pio, sm, true);
+}
+
+
+// When requesting the current count we may have to wait a few cycles (average
+// ~11 sysclk cycles) for the state machine to reply. If we are reading multiple
+// encoders, we may request them all in one go and then fetch them all, thus
+// avoiding doing the wait multiple times. If we are reading just one encoder,
+// we can use the "get_count" function to request and wait
+
+static inline void quadrature_encoder_request_count(PIO pio, uint sm)
+{
+	pio->txf[sm] = 1;
+}
+
+static inline int32_t quadrature_encoder_fetch_count(PIO pio, uint sm)
+{
+	while (pio_sm_is_rx_fifo_empty(pio, sm))
+		tight_loop_contents();
+	return pio->rxf[sm];
+}
+
+static inline int32_t quadrature_encoder_get_count(PIO pio, uint sm)
+{
+	quadrature_encoder_request_count(pio, sm);
+	return quadrature_encoder_fetch_count(pio, sm);
+}
+
+%}
+
diff --git a/src/hal/pio/assembler/comparison_tests/quadrature_encoder.pio.h b/src/hal/pio/assembler/comparison_tests/quadrature_encoder.pio.h
new file mode 100644
index 000000000..4cc4bb325
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/quadrature_encoder.pio.h
@@ -0,0 +1,116 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ------------------ //
+// quadrature_encoder //
+// ------------------ //
+
+#define quadrature_encoder_wrap_target 15
+#define quadrature_encoder_wrap 28
+
+static const uint16_t quadrature_encoder_program_instructions[] = {
+    0x000f, //  0: jmp    15                         
+    0x000e, //  1: jmp    14                         
+    0x001a, //  2: jmp    26                         
+    0x000f, //  3: jmp    15                         
+    0x001a, //  4: jmp    26                         
+    0x000f, //  5: jmp    15                         
+    0x000f, //  6: jmp    15                         
+    0x000e, //  7: jmp    14                         
+    0x000e, //  8: jmp    14                         
+    0x000f, //  9: jmp    15                         
+    0x000f, // 10: jmp    15                         
+    0x001a, // 11: jmp    26                         
+    0x000f, // 12: jmp    15                         
+    0x001a, // 13: jmp    26                         
+    0x008f, // 14: jmp    y--, 15                    
+            //     .wrap_target
+    0xe020, // 15: set    x, 0                       
+    0x8080, // 16: pull   noblock                    
+    0xa027, // 17: mov    x, osr                     
+    0xa0e6, // 18: mov    osr, isr                   
+    0x0036, // 19: jmp    !x, 22                     
+    0xa0c2, // 20: mov    isr, y                     
+    0x8020, // 21: push   block                      
+    0xa0c3, // 22: mov    isr, null                  
+    0x40e2, // 23: in     osr, 2                     
+    0x4002, // 24: in     pins, 2                    
+    0xa0a6, // 25: mov    pc, isr                    
+    0xa02a, // 26: mov    x, !y                      
+    0x005c, // 27: jmp    x--, 28                    
+    0xa049, // 28: mov    y, !x                      
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program quadrature_encoder_program = {
+    .instructions = quadrature_encoder_program_instructions,
+    .length = 29,
+    .origin = 0,
+};
+
+static inline pio_sm_config quadrature_encoder_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + quadrature_encoder_wrap_target, offset + quadrature_encoder_wrap);
+    return c;
+}
+
+#include "hardware/clocks.h"
+#include "hardware/gpio.h"
+// max_step_rate is used to lower the clock of the state machine to save power
+// if the application doesn't require a very high sampling rate. Passing zero
+// will set the clock to the maximum, which gives a max step rate of around
+// 8.9 Msteps/sec at 125MHz
+static inline void quadrature_encoder_program_init(PIO pio, uint sm, uint offset, uint pin, int max_step_rate)
+{
+	pio_sm_set_consecutive_pindirs(pio, sm, pin, 2, false);
+	gpio_pull_up(pin);
+	gpio_pull_up(pin + 1);
+	pio_sm_config c = quadrature_encoder_program_get_default_config(offset);
+	sm_config_set_in_pins(&c, pin); // for WAIT, IN
+	sm_config_set_jmp_pin(&c, pin); // for JMP
+	// shift to left, autopull disabled
+	sm_config_set_in_shift(&c, false, false, 32);
+	// don't join FIFO's
+	sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_NONE);
+	// passing "0" as the sample frequency,
+	if (max_step_rate == 0) {
+		sm_config_set_clkdiv(&c, 1.0);
+	} else {
+		// one state machine loop takes at most 14 cycles
+		float div = (float)clock_get_hz(clk_sys) / (14 * max_step_rate);
+		sm_config_set_clkdiv(&c, div);
+	}
+	pio_sm_init(pio, sm, offset, &c);
+	pio_sm_set_enabled(pio, sm, true);
+}
+// When requesting the current count we may have to wait a few cycles (average
+// ~11 sysclk cycles) for the state machine to reply. If we are reading multiple
+// encoders, we may request them all in one go and then fetch them all, thus
+// avoiding doing the wait multiple times. If we are reading just one encoder,
+// we can use the "get_count" function to request and wait
+static inline void quadrature_encoder_request_count(PIO pio, uint sm)
+{
+	pio->txf[sm] = 1;
+}
+static inline int32_t quadrature_encoder_fetch_count(PIO pio, uint sm)
+{
+	while (pio_sm_is_rx_fifo_empty(pio, sm))
+		tight_loop_contents();
+	return pio->rxf[sm];
+}
+static inline int32_t quadrature_encoder_get_count(PIO pio, uint sm)
+{
+	quadrature_encoder_request_count(pio, sm);
+	return quadrature_encoder_fetch_count(pio, sm);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/resistor_dac.pio b/src/hal/pio/assembler/comparison_tests/resistor_dac.pio
new file mode 100644
index 000000000..2dca1f1d1
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/resistor_dac.pio
@@ -0,0 +1,38 @@
+;
+; Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program resistor_dac_5bit
+
+; Drive one of the 5-bit resistor DACs on the VGA reference board. (this isn't
+; a good way to do VGA -- just want a nice sawtooth for the ADC example!)
+
+    out pins, 5
+
+
+
+% c-sdk {
+#include "hardware/clocks.h"
+static inline void resistor_dac_5bit_program_init(PIO pio, uint sm, uint offset,
+        uint sample_rate_hz, uint pin_base) {
+
+    pio_sm_set_pins_with_mask(pio, sm, 0, 0x1fu << pin_base);
+    pio_sm_set_pindirs_with_mask(pio, sm, ~0u, 0x1fu << pin_base);
+    for (int i = 0; i < 5; ++i)
+        pio_gpio_init(pio, pin_base + i);
+
+    pio_sm_config c = resistor_dac_5bit_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, pin_base, 5);
+    // Shift to right, autopull threshold 5
+    sm_config_set_out_shift(&c, true, true, 5);
+    // Deeper FIFO as we're not doing any RX
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    float div = (float)clock_get_hz(clk_sys) / sample_rate_hz;
+    sm_config_set_clkdiv(&c, div);
+
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/resistor_dac.pio.h b/src/hal/pio/assembler/comparison_tests/resistor_dac.pio.h
new file mode 100644
index 000000000..df80791c1
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/resistor_dac.pio.h
@@ -0,0 +1,57 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ----------------- //
+// resistor_dac_5bit //
+// ----------------- //
+
+#define resistor_dac_5bit_wrap_target 0
+#define resistor_dac_5bit_wrap 0
+
+static const uint16_t resistor_dac_5bit_program_instructions[] = {
+            //     .wrap_target
+    0x6005, //  0: out    pins, 5                    
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program resistor_dac_5bit_program = {
+    .instructions = resistor_dac_5bit_program_instructions,
+    .length = 1,
+    .origin = -1,
+};
+
+static inline pio_sm_config resistor_dac_5bit_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + resistor_dac_5bit_wrap_target, offset + resistor_dac_5bit_wrap);
+    return c;
+}
+
+#include "hardware/clocks.h"
+static inline void resistor_dac_5bit_program_init(PIO pio, uint sm, uint offset,
+        uint sample_rate_hz, uint pin_base) {
+    pio_sm_set_pins_with_mask(pio, sm, 0, 0x1fu << pin_base);
+    pio_sm_set_pindirs_with_mask(pio, sm, ~0u, 0x1fu << pin_base);
+    for (int i = 0; i < 5; ++i)
+        pio_gpio_init(pio, pin_base + i);
+    pio_sm_config c = resistor_dac_5bit_program_get_default_config(offset);
+    sm_config_set_out_pins(&c, pin_base, 5);
+    // Shift to right, autopull threshold 5
+    sm_config_set_out_shift(&c, true, true, 5);
+    // Deeper FIFO as we're not doing any RX
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    float div = (float)clock_get_hz(clk_sys) / sample_rate_hz;
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/spi.pio b/src/hal/pio/assembler/comparison_tests/spi.pio
new file mode 100644
index 000000000..eba785eaa
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/spi.pio
@@ -0,0 +1,168 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+; These programs implement full-duplex SPI, with a SCK period of 4 clock
+; cycles. A different program is provided for each value of CPHA, and CPOL is
+; achieved using the hardware GPIO inversion available in the IO controls.
+;
+; Transmit-only SPI can go twice as fast -- see the ST7789 example!
+
+
+.program spi_cpha0
+.side_set 1
+
+; Pin assignments:
+; - SCK is side-set pin 0
+; - MOSI is OUT pin 0
+; - MISO is IN pin 0
+;
+; Autopush and autopull must be enabled, and the serial frame size is set by
+; configuring the push/pull threshold. Shift left/right is fine, but you must
+; justify the data yourself. This is done most conveniently for frame sizes of
+; 8 or 16 bits by using the narrow store replication and narrow load byte
+; picking behaviour of RP2040's IO fabric.
+
+; Clock phase = 0: data is captured on the leading edge of each SCK pulse, and
+; transitions on the trailing edge, or some time before the first leading edge.
+
+    out pins, 1 side 0 [1] ; Stall here on empty (sideset proceeds even if
+    in pins, 1  side 1 [1] ; instruction stalls, so we stall with SCK low)
+
+.program spi_cpha1
+.side_set 1
+
+; Clock phase = 1: data transitions on the leading edge of each SCK pulse, and
+; is captured on the trailing edge.
+
+    out x, 1    side 0     ; Stall here on empty (keep SCK deasserted)
+    mov pins, x side 1 [1] ; Output data, assert SCK (mov pins uses OUT mapping)
+    in pins, 1  side 0     ; Input data, deassert SCK
+
+% c-sdk {
+#include "hardware/gpio.h"
+static inline void pio_spi_init(PIO pio, uint sm, uint prog_offs, uint n_bits,
+        float clkdiv, bool cpha, bool cpol, uint pin_sck, uint pin_mosi, uint pin_miso) {
+    pio_sm_config c = cpha ? spi_cpha1_program_get_default_config(prog_offs) : spi_cpha0_program_get_default_config(prog_offs);
+    sm_config_set_out_pins(&c, pin_mosi, 1);
+    sm_config_set_in_pins(&c, pin_miso);
+    sm_config_set_sideset_pins(&c, pin_sck);
+    // Only support MSB-first in this example code (shift to left, auto push/pull, threshold=nbits)
+    sm_config_set_out_shift(&c, false, true, n_bits);
+    sm_config_set_in_shift(&c, false, true, n_bits);
+    sm_config_set_clkdiv(&c, clkdiv);
+
+    // MOSI, SCK output are low, MISO is input
+    pio_sm_set_pins_with_mask(pio, sm, 0, (1u << pin_sck) | (1u << pin_mosi));
+    pio_sm_set_pindirs_with_mask(pio, sm, (1u << pin_sck) | (1u << pin_mosi), (1u << pin_sck) | (1u << pin_mosi) | (1u << pin_miso));
+    pio_gpio_init(pio, pin_mosi);
+    pio_gpio_init(pio, pin_miso);
+    pio_gpio_init(pio, pin_sck);
+
+    // The pin muxes can be configured to invert the output (among other things
+    // and this is a cheesy way to get CPOL=1
+    gpio_set_outover(pin_sck, cpol ? GPIO_OVERRIDE_INVERT : GPIO_OVERRIDE_NORMAL);
+    // SPI is synchronous, so bypass input synchroniser to reduce input delay.
+    hw_set_bits(&pio->input_sync_bypass, 1u << pin_miso);
+
+    pio_sm_init(pio, sm, prog_offs, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
+
+; SPI with Chip Select
+; -----------------------------------------------------------------------------
+;
+; For your amusement, here are some SPI programs with an automatic chip select
+; (asserted once data appears in TX FIFO, deasserts when FIFO bottoms out, has
+; a nice front/back porch).
+;
+; The number of bits per FIFO entry is configured via the Y register
+; and the autopush/pull threshold. From 2 to 32 bits.
+;
+; Pin assignments:
+; - SCK is side-set bit 0
+; - CSn is side-set bit 1
+; - MOSI is OUT bit 0 (host-to-device)
+; - MISO is IN bit 0 (device-to-host)
+;
+; This program only supports one chip select -- use GPIO if more are needed
+;
+; Provide a variation for each possibility of CPHA; for CPOL we can just
+; invert SCK in the IO muxing controls (downstream from PIO)
+
+
+; CPHA=0: data is captured on the leading edge of each SCK pulse (including
+; the first pulse), and transitions on the trailing edge
+
+.program spi_cpha0_cs
+.side_set 2
+
+.wrap_target
+bitloop:
+    out pins, 1        side 0x0 [1]
+    in pins, 1         side 0x1
+    jmp x-- bitloop    side 0x1
+
+    out pins, 1        side 0x0
+    mov x, y           side 0x0     ; Reload bit counter from Y
+    in pins, 1         side 0x1
+    jmp !osre bitloop  side 0x1     ; Fall-through if TXF empties
+
+    nop                side 0x0 [1] ; CSn back porch
+public entry_point:                 ; Must set X,Y to n-2 before starting!
+    pull ifempty       side 0x2 [1] ; Block with CSn high (minimum 2 cycles)
+.wrap                               ; Note ifempty to avoid time-of-check race
+
+; CPHA=1: data transitions on the leading edge of each SCK pulse, and is
+; captured on the trailing edge
+
+.program spi_cpha1_cs
+.side_set 2
+
+.wrap_target
+bitloop:
+    out pins, 1        side 0x1 [1]
+    in pins, 1         side 0x0
+    jmp x-- bitloop    side 0x0
+
+    out pins, 1        side 0x1
+    mov x, y           side 0x1
+    in pins, 1         side 0x0
+    jmp !osre bitloop  side 0x0
+
+public entry_point:                 ; Must set X,Y to n-2 before starting!
+    pull ifempty       side 0x2 [1] ; Block with CSn high (minimum 2 cycles)
+    nop                side 0x0 [1]; CSn front porch
+.wrap
+
+% c-sdk {
+#include "hardware/gpio.h"
+static inline void pio_spi_cs_init(PIO pio, uint sm, uint prog_offs, uint n_bits, float clkdiv, bool cpha, bool cpol,
+        uint pin_sck, uint pin_mosi, uint pin_miso) {
+    pio_sm_config c = cpha ? spi_cpha1_cs_program_get_default_config(prog_offs) : spi_cpha0_cs_program_get_default_config(prog_offs);
+    sm_config_set_out_pins(&c, pin_mosi, 1);
+    sm_config_set_in_pins(&c, pin_miso);
+    sm_config_set_sideset_pins(&c, pin_sck);
+    sm_config_set_out_shift(&c, false, true, n_bits);
+    sm_config_set_in_shift(&c, false, true, n_bits);
+    sm_config_set_clkdiv(&c, clkdiv);
+
+    pio_sm_set_pins_with_mask(pio, sm, (2u << pin_sck), (3u << pin_sck) | (1u << pin_mosi));
+    pio_sm_set_pindirs_with_mask(pio, sm, (3u << pin_sck) | (1u << pin_mosi), (3u << pin_sck) | (1u << pin_mosi) | (1u << pin_miso));
+    pio_gpio_init(pio, pin_mosi);
+    pio_gpio_init(pio, pin_miso);
+    pio_gpio_init(pio, pin_sck);
+    pio_gpio_init(pio, pin_sck + 1);
+    gpio_set_outover(pin_sck, cpol ? GPIO_OVERRIDE_INVERT : GPIO_OVERRIDE_NORMAL);
+    hw_set_bits(&pio->input_sync_bypass, 1u << pin_miso);
+
+    uint entry_point = prog_offs + (cpha ? spi_cpha1_cs_offset_entry_point : spi_cpha0_cs_offset_entry_point);
+    pio_sm_init(pio, sm, entry_point, &c);
+    pio_sm_exec(pio, sm, pio_encode_set(pio_x, n_bits - 2));
+    pio_sm_exec(pio, sm, pio_encode_set(pio_y, n_bits - 2));
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/spi.pio.h b/src/hal/pio/assembler/comparison_tests/spi.pio.h
new file mode 100644
index 000000000..22aa805a0
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/spi.pio.h
@@ -0,0 +1,198 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// --------- //
+// spi_cpha0 //
+// --------- //
+
+#define spi_cpha0_wrap_target 0
+#define spi_cpha0_wrap 1
+
+static const uint16_t spi_cpha0_program_instructions[] = {
+            //     .wrap_target
+    0x6101, //  0: out    pins, 1         side 0 [1] 
+    0x5101, //  1: in     pins, 1         side 1 [1] 
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program spi_cpha0_program = {
+    .instructions = spi_cpha0_program_instructions,
+    .length = 2,
+    .origin = -1,
+};
+
+static inline pio_sm_config spi_cpha0_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + spi_cpha0_wrap_target, offset + spi_cpha0_wrap);
+    sm_config_set_sideset(&c, 1, false, false);
+    return c;
+}
+#endif
+
+// --------- //
+// spi_cpha1 //
+// --------- //
+
+#define spi_cpha1_wrap_target 0
+#define spi_cpha1_wrap 2
+
+static const uint16_t spi_cpha1_program_instructions[] = {
+            //     .wrap_target
+    0x6021, //  0: out    x, 1            side 0     
+    0xb101, //  1: mov    pins, x         side 1 [1] 
+    0x4001, //  2: in     pins, 1         side 0     
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program spi_cpha1_program = {
+    .instructions = spi_cpha1_program_instructions,
+    .length = 3,
+    .origin = -1,
+};
+
+static inline pio_sm_config spi_cpha1_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + spi_cpha1_wrap_target, offset + spi_cpha1_wrap);
+    sm_config_set_sideset(&c, 1, false, false);
+    return c;
+}
+
+#include "hardware/gpio.h"
+static inline void pio_spi_init(PIO pio, uint sm, uint prog_offs, uint n_bits,
+        float clkdiv, bool cpha, bool cpol, uint pin_sck, uint pin_mosi, uint pin_miso) {
+    pio_sm_config c = cpha ? spi_cpha1_program_get_default_config(prog_offs) : spi_cpha0_program_get_default_config(prog_offs);
+    sm_config_set_out_pins(&c, pin_mosi, 1);
+    sm_config_set_in_pins(&c, pin_miso);
+    sm_config_set_sideset_pins(&c, pin_sck);
+    // Only support MSB-first in this example code (shift to left, auto push/pull, threshold=nbits)
+    sm_config_set_out_shift(&c, false, true, n_bits);
+    sm_config_set_in_shift(&c, false, true, n_bits);
+    sm_config_set_clkdiv(&c, clkdiv);
+    // MOSI, SCK output are low, MISO is input
+    pio_sm_set_pins_with_mask(pio, sm, 0, (1u << pin_sck) | (1u << pin_mosi));
+    pio_sm_set_pindirs_with_mask(pio, sm, (1u << pin_sck) | (1u << pin_mosi), (1u << pin_sck) | (1u << pin_mosi) | (1u << pin_miso));
+    pio_gpio_init(pio, pin_mosi);
+    pio_gpio_init(pio, pin_miso);
+    pio_gpio_init(pio, pin_sck);
+    // The pin muxes can be configured to invert the output (among other things
+    // and this is a cheesy way to get CPOL=1
+    gpio_set_outover(pin_sck, cpol ? GPIO_OVERRIDE_INVERT : GPIO_OVERRIDE_NORMAL);
+    // SPI is synchronous, so bypass input synchroniser to reduce input delay.
+    hw_set_bits(&pio->input_sync_bypass, 1u << pin_miso);
+    pio_sm_init(pio, sm, prog_offs, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
+// ------------ //
+// spi_cpha0_cs //
+// ------------ //
+
+#define spi_cpha0_cs_wrap_target 0
+#define spi_cpha0_cs_wrap 8
+
+#define spi_cpha0_cs_offset_entry_point 8u
+
+static const uint16_t spi_cpha0_cs_program_instructions[] = {
+            //     .wrap_target
+    0x6101, //  0: out    pins, 1         side 0 [1] 
+    0x4801, //  1: in     pins, 1         side 1     
+    0x0840, //  2: jmp    x--, 0          side 1     
+    0x6001, //  3: out    pins, 1         side 0     
+    0xa022, //  4: mov    x, y            side 0     
+    0x4801, //  5: in     pins, 1         side 1     
+    0x08e0, //  6: jmp    !osre, 0        side 1     
+    0xa142, //  7: nop                    side 0 [1] 
+    0x91e0, //  8: pull   ifempty block   side 2 [1] 
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program spi_cpha0_cs_program = {
+    .instructions = spi_cpha0_cs_program_instructions,
+    .length = 9,
+    .origin = -1,
+};
+
+static inline pio_sm_config spi_cpha0_cs_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + spi_cpha0_cs_wrap_target, offset + spi_cpha0_cs_wrap);
+    sm_config_set_sideset(&c, 2, false, false);
+    return c;
+}
+#endif
+
+// ------------ //
+// spi_cpha1_cs //
+// ------------ //
+
+#define spi_cpha1_cs_wrap_target 0
+#define spi_cpha1_cs_wrap 8
+
+#define spi_cpha1_cs_offset_entry_point 7u
+
+static const uint16_t spi_cpha1_cs_program_instructions[] = {
+            //     .wrap_target
+    0x6901, //  0: out    pins, 1         side 1 [1] 
+    0x4001, //  1: in     pins, 1         side 0     
+    0x0040, //  2: jmp    x--, 0          side 0     
+    0x6801, //  3: out    pins, 1         side 1     
+    0xa822, //  4: mov    x, y            side 1     
+    0x4001, //  5: in     pins, 1         side 0     
+    0x00e0, //  6: jmp    !osre, 0        side 0     
+    0x91e0, //  7: pull   ifempty block   side 2 [1] 
+    0xa142, //  8: nop                    side 0 [1] 
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program spi_cpha1_cs_program = {
+    .instructions = spi_cpha1_cs_program_instructions,
+    .length = 9,
+    .origin = -1,
+};
+
+static inline pio_sm_config spi_cpha1_cs_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + spi_cpha1_cs_wrap_target, offset + spi_cpha1_cs_wrap);
+    sm_config_set_sideset(&c, 2, false, false);
+    return c;
+}
+
+#include "hardware/gpio.h"
+static inline void pio_spi_cs_init(PIO pio, uint sm, uint prog_offs, uint n_bits, float clkdiv, bool cpha, bool cpol,
+        uint pin_sck, uint pin_mosi, uint pin_miso) {
+    pio_sm_config c = cpha ? spi_cpha1_cs_program_get_default_config(prog_offs) : spi_cpha0_cs_program_get_default_config(prog_offs);
+    sm_config_set_out_pins(&c, pin_mosi, 1);
+    sm_config_set_in_pins(&c, pin_miso);
+    sm_config_set_sideset_pins(&c, pin_sck);
+    sm_config_set_out_shift(&c, false, true, n_bits);
+    sm_config_set_in_shift(&c, false, true, n_bits);
+    sm_config_set_clkdiv(&c, clkdiv);
+    pio_sm_set_pins_with_mask(pio, sm, (2u << pin_sck), (3u << pin_sck) | (1u << pin_mosi));
+    pio_sm_set_pindirs_with_mask(pio, sm, (3u << pin_sck) | (1u << pin_mosi), (3u << pin_sck) | (1u << pin_mosi) | (1u << pin_miso));
+    pio_gpio_init(pio, pin_mosi);
+    pio_gpio_init(pio, pin_miso);
+    pio_gpio_init(pio, pin_sck);
+    pio_gpio_init(pio, pin_sck + 1);
+    gpio_set_outover(pin_sck, cpol ? GPIO_OVERRIDE_INVERT : GPIO_OVERRIDE_NORMAL);
+    hw_set_bits(&pio->input_sync_bypass, 1u << pin_miso);
+    uint entry_point = prog_offs + (cpha ? spi_cpha1_cs_offset_entry_point : spi_cpha0_cs_offset_entry_point);
+    pio_sm_init(pio, sm, entry_point, &c);
+    pio_sm_exec(pio, sm, pio_encode_set(pio_x, n_bits - 2));
+    pio_sm_exec(pio, sm, pio_encode_set(pio_y, n_bits - 2));
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave.pio b/src/hal/pio/assembler/comparison_tests/squarewave.pio
new file mode 100644
index 000000000..405c89972
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/squarewave.pio
@@ -0,0 +1,13 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program squarewave
+    set pindirs, 1   ; Set pin to output
+again:
+    set pins, 1 [1]  ; Drive pin high and then delay for one cycle
+    set pins, 0      ; Drive pin low
+    jmp again        ; Set PC to label `again`
+
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave.pio.h b/src/hal/pio/assembler/comparison_tests/squarewave.pio.h
new file mode 100644
index 000000000..9ec7ea659
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/squarewave.pio.h
@@ -0,0 +1,40 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ---------- //
+// squarewave //
+// ---------- //
+
+#define squarewave_wrap_target 0
+#define squarewave_wrap 3
+
+static const uint16_t squarewave_program_instructions[] = {
+            //     .wrap_target
+    0xe081, //  0: set    pindirs, 1                 
+    0xe101, //  1: set    pins, 1                [1] 
+    0xe000, //  2: set    pins, 0                    
+    0x0001, //  3: jmp    1                          
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program squarewave_program = {
+    .instructions = squarewave_program_instructions,
+    .length = 4,
+    .origin = -1,
+};
+
+static inline pio_sm_config squarewave_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + squarewave_wrap_target, offset + squarewave_wrap);
+    return c;
+}
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio b/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio
new file mode 100644
index 000000000..26162fadb
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio
@@ -0,0 +1,19 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+; Note that if you modify squarewave.c to include this program, you'll also
+; need to set the wrap registers yourself. This would be handled for you by
+; squarewave_program_get_default_config().
+
+
+.program squarewave_fast
+; Like squarewave_wrap, but remove the delay cycles so we can run twice as fast.
+    set pindirs, 1   ; Set pin to output
+.wrap_target
+	set pins, 1      ; Drive pin high
+	set pins, 0      ; Drive pin low
+.wrap
+
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio.h b/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio.h
new file mode 100644
index 000000000..686209cd3
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio.h
@@ -0,0 +1,39 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// --------------- //
+// squarewave_fast //
+// --------------- //
+
+#define squarewave_fast_wrap_target 1
+#define squarewave_fast_wrap 2
+
+static const uint16_t squarewave_fast_program_instructions[] = {
+    0xe081, //  0: set    pindirs, 1                 
+            //     .wrap_target
+    0xe001, //  1: set    pins, 1                    
+    0xe000, //  2: set    pins, 0                    
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program squarewave_fast_program = {
+    .instructions = squarewave_fast_program_instructions,
+    .length = 3,
+    .origin = -1,
+};
+
+static inline pio_sm_config squarewave_fast_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + squarewave_fast_wrap_target, offset + squarewave_fast_wrap);
+    return c;
+}
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave_test.pio b/src/hal/pio/assembler/comparison_tests/squarewave_test.pio
new file mode 100644
index 000000000..1b3e2904f
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/squarewave_test.pio
@@ -0,0 +1,12 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program squarewave
+set pindirs, 1   ; Set pin to output
+again: set pins, 1 [1]  ; Drive pin high and then delay for one cycle
+    set pins, 0      ; Drive pin low
+    jmp again        ; Set PC to label `again`
+
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio b/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio
new file mode 100644
index 000000000..100f09cf1
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio
@@ -0,0 +1,19 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+; Note that if you modify squarewave.c to include this program, you'll also
+; need to set the wrap registers yourself. This would be handled for you by
+; squarewave_program_get_default_config().
+
+.program squarewave_wrap
+; Like squarewave, but use the state machine's .wrap hardware instead of an
+; explicit jmp. This is a free (0-cycle) unconditional jump.
+
+    set pindirs, 1   ; Set pin to output
+.wrap_target
+	set pins, 1 [1]  ; Drive pin high and then delay for one cycle
+	set pins, 0 [1]  ; Drive pin low and then delay for one cycle
+.wrap
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio.h b/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio.h
new file mode 100644
index 000000000..ff90703ce
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio.h
@@ -0,0 +1,39 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// --------------- //
+// squarewave_wrap //
+// --------------- //
+
+#define squarewave_wrap_wrap_target 1
+#define squarewave_wrap_wrap 2
+
+static const uint16_t squarewave_wrap_program_instructions[] = {
+    0xe081, //  0: set    pindirs, 1                 
+            //     .wrap_target
+    0xe101, //  1: set    pins, 1                [1] 
+    0xe100, //  2: set    pins, 0                [1] 
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program squarewave_wrap_program = {
+    .instructions = squarewave_wrap_program_instructions,
+    .length = 3,
+    .origin = -1,
+};
+
+static inline pio_sm_config squarewave_wrap_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + squarewave_wrap_wrap_target, offset + squarewave_wrap_wrap);
+    return c;
+}
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio b/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio
new file mode 100644
index 000000000..aa35c683f
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio
@@ -0,0 +1,57 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program st7789_lcd
+.side_set 1
+
+; This is just a simple clocked serial TX. At 125 MHz system clock we can
+; sustain up to 62.5 Mbps.
+; Data on OUT pin 0
+; Clock on side-set pin 0
+
+.wrap_target
+    out pins, 1   side 0 ; stall here if no data (clock low)
+    nop           side 1
+.wrap
+
+% c-sdk {
+// For optimal use of DMA bandwidth we would use an autopull threshold of 32,
+// but we are using a threshold of 8 here (consume 1 byte from each FIFO entry
+// and discard the remainder) to make things easier for software on the other side
+
+static inline void st7789_lcd_program_init(PIO pio, uint sm, uint offset, uint data_pin, uint clk_pin, float clk_div) {
+    pio_gpio_init(pio, data_pin);
+    pio_gpio_init(pio, clk_pin);
+    pio_sm_set_consecutive_pindirs(pio, sm, data_pin, 1, true);
+    pio_sm_set_consecutive_pindirs(pio, sm, clk_pin, 1, true);
+    pio_sm_config c = st7789_lcd_program_get_default_config(offset);
+    sm_config_set_sideset_pins(&c, clk_pin);
+    sm_config_set_out_pins(&c, data_pin, 1);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    sm_config_set_clkdiv(&c, clk_div);
+    sm_config_set_out_shift(&c, false, true, 8);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+// Making use of the narrow store replication behaviour on RP2040 to get the
+// data left-justified (as we are using shift-to-left to get MSB-first serial)
+
+static inline void st7789_lcd_put(PIO pio, uint sm, uint8_t x) {
+    while (pio_sm_is_tx_fifo_full(pio, sm))
+        ;
+    *(volatile uint8_t*)&pio->txf[sm] = x;
+}
+
+// SM is done when it stalls on an empty FIFO
+
+static inline void st7789_lcd_wait_idle(PIO pio, uint sm) {
+    uint32_t sm_stall_mask = 1u << (sm + PIO_FDEBUG_TXSTALL_LSB);
+    pio->fdebug = sm_stall_mask;
+    while (!(pio->fdebug & sm_stall_mask))
+        ;
+}
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio.h b/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio.h
new file mode 100644
index 000000000..c77167ea2
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio.h
@@ -0,0 +1,72 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ---------- //
+// st7789_lcd //
+// ---------- //
+
+#define st7789_lcd_wrap_target 0
+#define st7789_lcd_wrap 1
+
+static const uint16_t st7789_lcd_program_instructions[] = {
+            //     .wrap_target
+    0x6001, //  0: out    pins, 1         side 0     
+    0xb042, //  1: nop                    side 1     
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program st7789_lcd_program = {
+    .instructions = st7789_lcd_program_instructions,
+    .length = 2,
+    .origin = -1,
+};
+
+static inline pio_sm_config st7789_lcd_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + st7789_lcd_wrap_target, offset + st7789_lcd_wrap);
+    sm_config_set_sideset(&c, 1, false, false);
+    return c;
+}
+
+// For optimal use of DMA bandwidth we would use an autopull threshold of 32,
+// but we are using a threshold of 8 here (consume 1 byte from each FIFO entry
+// and discard the remainder) to make things easier for software on the other side
+static inline void st7789_lcd_program_init(PIO pio, uint sm, uint offset, uint data_pin, uint clk_pin, float clk_div) {
+    pio_gpio_init(pio, data_pin);
+    pio_gpio_init(pio, clk_pin);
+    pio_sm_set_consecutive_pindirs(pio, sm, data_pin, 1, true);
+    pio_sm_set_consecutive_pindirs(pio, sm, clk_pin, 1, true);
+    pio_sm_config c = st7789_lcd_program_get_default_config(offset);
+    sm_config_set_sideset_pins(&c, clk_pin);
+    sm_config_set_out_pins(&c, data_pin, 1);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    sm_config_set_clkdiv(&c, clk_div);
+    sm_config_set_out_shift(&c, false, true, 8);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+// Making use of the narrow store replication behaviour on RP2040 to get the
+// data left-justified (as we are using shift-to-left to get MSB-first serial)
+static inline void st7789_lcd_put(PIO pio, uint sm, uint8_t x) {
+    while (pio_sm_is_tx_fifo_full(pio, sm))
+        ;
+    *(volatile uint8_t*)&pio->txf[sm] = x;
+}
+// SM is done when it stalls on an empty FIFO
+static inline void st7789_lcd_wait_idle(PIO pio, uint sm) {
+    uint32_t sm_stall_mask = 1u << (sm + PIO_FDEBUG_TXSTALL_LSB);
+    pio->fdebug = sm_stall_mask;
+    while (!(pio->fdebug & sm_stall_mask))
+        ;
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/uart_rx.pio b/src/hal/pio/assembler/comparison_tests/uart_rx.pio
new file mode 100644
index 000000000..54a6577c1
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/uart_rx.pio
@@ -0,0 +1,94 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program uart_rx_mini
+
+; Minimum viable 8n1 UART receiver. Wait for the start bit, then sample 8 bits
+; with the correct timing.
+; IN pin 0 is mapped to the GPIO used as UART RX.
+; Autopush must be enabled, with a threshold of 8.
+
+    wait 0 pin 0        ; Wait for start bit
+    set x, 7 [10]       ; Preload bit counter, delay until eye of first data bit
+bitloop:                ; Loop 8 times
+    in pins, 1          ; Sample data
+    jmp x-- bitloop [6] ; Each iteration is 8 cycles
+
+% c-sdk {
+#include "hardware/clocks.h"
+#include "hardware/gpio.h"
+
+static inline void uart_rx_mini_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) {
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    pio_gpio_init(pio, pin);
+    gpio_pull_up(pin);
+
+    pio_sm_config c = uart_rx_mini_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, pin); // for WAIT, IN
+    // Shift to right, autopush enabled
+    sm_config_set_in_shift(&c, true, true, 8);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    // SM transmits 1 bit per 8 execution cycles.
+    float div = (float)clock_get_hz(clk_sys) / (8 * baud);
+    sm_config_set_clkdiv(&c, div);
+    
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
+
+.program uart_rx
+
+; Slightly more fleshed-out 8n1 UART receiver which handles framing errors and
+; break conditions more gracefully.
+; IN pin 0 and JMP pin are both mapped to the GPIO used as UART RX.
+
+start:
+    wait 0 pin 0        ; Stall until start bit is asserted
+    set x, 7    [10]    ; Preload bit counter, then delay until halfway through
+bitloop:                ; the first data bit (12 cycles incl wait, set).
+    in pins, 1          ; Shift data bit into ISR
+    jmp x-- bitloop [6] ; Loop 8 times, each loop iteration is 8 cycles
+    jmp pin good_stop   ; Check stop bit (should be high)
+
+    irq 4 rel           ; Either a framing error or a break. Set a sticky flag,
+    wait 1 pin 0        ; and wait for line to return to idle state.
+    jmp start           ; Don't push data if we didn't see good framing.
+
+good_stop:              ; No delay before returning to start; a little slack is
+    push                ; important in case the TX clock is slightly too fast.
+
+
+% c-sdk {
+static inline void uart_rx_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) {
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    pio_gpio_init(pio, pin);
+    gpio_pull_up(pin);
+
+    pio_sm_config c = uart_rx_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, pin); // for WAIT, IN
+    sm_config_set_jmp_pin(&c, pin); // for JMP
+    // Shift to right, autopush disabled
+    sm_config_set_in_shift(&c, true, false, 32);
+    // Deeper FIFO as we're not doing any TX
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    // SM transmits 1 bit per 8 execution cycles.
+    float div = (float)clock_get_hz(clk_sys) / (8 * baud);
+    sm_config_set_clkdiv(&c, div);
+    
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+static inline char uart_rx_program_getc(PIO pio, uint sm) {
+    // 8-bit read from the uppermost byte of the FIFO, as data is left-justified
+    io_rw_8 *rxfifo_shift = (io_rw_8*)&pio->rxf[sm] + 3;
+    while (pio_sm_is_rx_fifo_empty(pio, sm))
+        tight_loop_contents();
+    return (char)*rxfifo_shift;
+}
+
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/uart_rx.pio.h b/src/hal/pio/assembler/comparison_tests/uart_rx.pio.h
new file mode 100644
index 000000000..b6b5da611
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/uart_rx.pio.h
@@ -0,0 +1,120 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ------------ //
+// uart_rx_mini //
+// ------------ //
+
+#define uart_rx_mini_wrap_target 0
+#define uart_rx_mini_wrap 3
+
+static const uint16_t uart_rx_mini_program_instructions[] = {
+            //     .wrap_target
+    0x2020, //  0: wait   0 pin, 0                   
+    0xea27, //  1: set    x, 7                   [10]
+    0x4001, //  2: in     pins, 1                    
+    0x0642, //  3: jmp    x--, 2                 [6] 
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program uart_rx_mini_program = {
+    .instructions = uart_rx_mini_program_instructions,
+    .length = 4,
+    .origin = -1,
+};
+
+static inline pio_sm_config uart_rx_mini_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + uart_rx_mini_wrap_target, offset + uart_rx_mini_wrap);
+    return c;
+}
+
+#include "hardware/clocks.h"
+#include "hardware/gpio.h"
+static inline void uart_rx_mini_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) {
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    pio_gpio_init(pio, pin);
+    gpio_pull_up(pin);
+    pio_sm_config c = uart_rx_mini_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, pin); // for WAIT, IN
+    // Shift to right, autopush enabled
+    sm_config_set_in_shift(&c, true, true, 8);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    // SM transmits 1 bit per 8 execution cycles.
+    float div = (float)clock_get_hz(clk_sys) / (8 * baud);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+#endif
+
+// ------- //
+// uart_rx //
+// ------- //
+
+#define uart_rx_wrap_target 0
+#define uart_rx_wrap 8
+
+static const uint16_t uart_rx_program_instructions[] = {
+            //     .wrap_target
+    0x2020, //  0: wait   0 pin, 0                   
+    0xea27, //  1: set    x, 7                   [10]
+    0x4001, //  2: in     pins, 1                    
+    0x0642, //  3: jmp    x--, 2                 [6] 
+    0x00c8, //  4: jmp    pin, 8                     
+    0xc014, //  5: irq    nowait 4 rel               
+    0x20a0, //  6: wait   1 pin, 0                   
+    0x0000, //  7: jmp    0                          
+    0x8020, //  8: push   block                      
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program uart_rx_program = {
+    .instructions = uart_rx_program_instructions,
+    .length = 9,
+    .origin = -1,
+};
+
+static inline pio_sm_config uart_rx_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + uart_rx_wrap_target, offset + uart_rx_wrap);
+    return c;
+}
+
+static inline void uart_rx_program_init(PIO pio, uint sm, uint offset, uint pin, uint baud) {
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, false);
+    pio_gpio_init(pio, pin);
+    gpio_pull_up(pin);
+    pio_sm_config c = uart_rx_program_get_default_config(offset);
+    sm_config_set_in_pins(&c, pin); // for WAIT, IN
+    sm_config_set_jmp_pin(&c, pin); // for JMP
+    // Shift to right, autopush disabled
+    sm_config_set_in_shift(&c, true, false, 32);
+    // Deeper FIFO as we're not doing any TX
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_RX);
+    // SM transmits 1 bit per 8 execution cycles.
+    float div = (float)clock_get_hz(clk_sys) / (8 * baud);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+static inline char uart_rx_program_getc(PIO pio, uint sm) {
+    // 8-bit read from the uppermost byte of the FIFO, as data is left-justified
+    io_rw_8 *rxfifo_shift = (io_rw_8*)&pio->rxf[sm] + 3;
+    while (pio_sm_is_rx_fifo_empty(pio, sm))
+        tight_loop_contents();
+    return (char)*rxfifo_shift;
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/uart_tx.pio b/src/hal/pio/assembler/comparison_tests/uart_tx.pio
new file mode 100644
index 000000000..b1320f676
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/uart_tx.pio
@@ -0,0 +1,61 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program uart_tx
+.side_set 1 opt
+
+; An 8n1 UART transmit program.
+; OUT pin 0 and side-set pin 0 are both mapped to UART TX pin.
+
+    pull       side 1 [7]  ; Assert stop bit, or stall with line in idle state
+    set x, 7   side 0 [7]  ; Preload bit counter, assert start bit for 8 clocks
+bitloop:                   ; This loop will run 8 times (8n1 UART)
+    out pins, 1            ; Shift 1 bit from OSR to the first OUT pin
+    jmp x-- bitloop   [6]  ; Each loop iteration is 8 cycles.
+
+
+% c-sdk {
+#include "hardware/clocks.h"
+
+static inline void uart_tx_program_init(PIO pio, uint sm, uint offset, uint pin_tx, uint baud) {
+    // Tell PIO to initially drive output-high on the selected pin, then map PIO
+    // onto that pin with the IO muxes.
+    pio_sm_set_pins_with_mask(pio, sm, 1u << pin_tx, 1u << pin_tx);
+    pio_sm_set_pindirs_with_mask(pio, sm, 1u << pin_tx, 1u << pin_tx);
+    pio_gpio_init(pio, pin_tx);
+
+    pio_sm_config c = uart_tx_program_get_default_config(offset);
+
+    // OUT shifts to right, no autopull
+    sm_config_set_out_shift(&c, true, false, 32);
+
+    // We are mapping both OUT and side-set to the same pin, because sometimes
+    // we need to assert user data onto the pin (with OUT) and sometimes
+    // assert constant values (start/stop bit)
+    sm_config_set_out_pins(&c, pin_tx, 1);
+    sm_config_set_sideset_pins(&c, pin_tx);
+
+    // We only need TX, so get an 8-deep FIFO!
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+
+    // SM transmits 1 bit per 8 execution cycles.
+    float div = (float)clock_get_hz(clk_sys) / (8 * baud);
+    sm_config_set_clkdiv(&c, div);
+
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+
+static inline void uart_tx_program_putc(PIO pio, uint sm, char c) {
+    pio_sm_put_blocking(pio, sm, (uint32_t)c);
+}
+
+static inline void uart_tx_program_puts(PIO pio, uint sm, const char *s) {
+    while (*s)
+        uart_tx_program_putc(pio, sm, *s++);
+}
+
+%}
diff --git a/src/hal/pio/assembler/comparison_tests/uart_tx.pio.h b/src/hal/pio/assembler/comparison_tests/uart_tx.pio.h
new file mode 100644
index 000000000..ff9b7d2a5
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/uart_tx.pio.h
@@ -0,0 +1,73 @@
+// -------------------------------------------------- //
+// This file is autogenerated by pioasm; do not edit! //
+// -------------------------------------------------- //
+
+#pragma once
+
+#if !PICO_NO_HARDWARE
+#include "hardware/pio.h"
+#endif
+
+// ------- //
+// uart_tx //
+// ------- //
+
+#define uart_tx_wrap_target 0
+#define uart_tx_wrap 3
+
+static const uint16_t uart_tx_program_instructions[] = {
+            //     .wrap_target
+    0x9fa0, //  0: pull   block           side 1 [7] 
+    0xf727, //  1: set    x, 7            side 0 [7] 
+    0x6001, //  2: out    pins, 1                    
+    0x0642, //  3: jmp    x--, 2                 [6] 
+            //     .wrap
+};
+
+#if !PICO_NO_HARDWARE
+static const struct pio_program uart_tx_program = {
+    .instructions = uart_tx_program_instructions,
+    .length = 4,
+    .origin = -1,
+};
+
+static inline pio_sm_config uart_tx_program_get_default_config(uint offset) {
+    pio_sm_config c = pio_get_default_sm_config();
+    sm_config_set_wrap(&c, offset + uart_tx_wrap_target, offset + uart_tx_wrap);
+    sm_config_set_sideset(&c, 2, true, false);
+    return c;
+}
+
+#include "hardware/clocks.h"
+static inline void uart_tx_program_init(PIO pio, uint sm, uint offset, uint pin_tx, uint baud) {
+    // Tell PIO to initially drive output-high on the selected pin, then map PIO
+    // onto that pin with the IO muxes.
+    pio_sm_set_pins_with_mask(pio, sm, 1u << pin_tx, 1u << pin_tx);
+    pio_sm_set_pindirs_with_mask(pio, sm, 1u << pin_tx, 1u << pin_tx);
+    pio_gpio_init(pio, pin_tx);
+    pio_sm_config c = uart_tx_program_get_default_config(offset);
+    // OUT shifts to right, no autopull
+    sm_config_set_out_shift(&c, true, false, 32);
+    // We are mapping both OUT and side-set to the same pin, because sometimes
+    // we need to assert user data onto the pin (with OUT) and sometimes
+    // assert constant values (start/stop bit)
+    sm_config_set_out_pins(&c, pin_tx, 1);
+    sm_config_set_sideset_pins(&c, pin_tx);
+    // We only need TX, so get an 8-deep FIFO!
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+    // SM transmits 1 bit per 8 execution cycles.
+    float div = (float)clock_get_hz(clk_sys) / (8 * baud);
+    sm_config_set_clkdiv(&c, div);
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+static inline void uart_tx_program_putc(PIO pio, uint sm, char c) {
+    pio_sm_put_blocking(pio, sm, (uint32_t)c);
+}
+static inline void uart_tx_program_puts(PIO pio, uint sm, const char *s) {
+    while (*s)
+        uart_tx_program_putc(pio, sm, *s++);
+}
+
+#endif
+
diff --git a/src/hal/pio/assembler/comparison_tests/ws2812.pio b/src/hal/pio/assembler/comparison_tests/ws2812.pio
new file mode 100644
index 000000000..3c31fd6c9
--- /dev/null
+++ b/src/hal/pio/assembler/comparison_tests/ws2812.pio
@@ -0,0 +1,85 @@
+;
+; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+;
+; SPDX-License-Identifier: BSD-3-Clause
+;
+
+.program ws2812
+.side_set 1
+
+.define public T1 2
+.define public T2 5
+.define public T3 3
+
+.lang_opt python sideset_init = pico.PIO.OUT_HIGH
+.lang_opt python out_init     = pico.PIO.OUT_HIGH
+.lang_opt python out_shiftdir = 1
+
+.wrap_target
+bitloop:
+    out x, 1       side 0 [T3 - 1] ; Side-set still takes place when instruction stalls
+    jmp !x do_zero side 1 [T1 - 1] ; Branch on the bit we shifted out. Positive pulse
+do_one:
+    jmp  bitloop   side 1 [T2 - 1] ; Continue driving high, for a long pulse
+do_zero:
+    nop            side 0 [T2 - 1] ; Or drive low, for a short pulse
+.wrap
+
+% c-sdk {
+#include "hardware/clocks.h"
+
+static inline void ws2812_program_init(PIO pio, uint sm, uint offset, uint pin, float freq, bool rgbw) {
+
+    pio_gpio_init(pio, pin);
+    pio_sm_set_consecutive_pindirs(pio, sm, pin, 1, true);
+
+    pio_sm_config c = ws2812_program_get_default_config(offset);
+    sm_config_set_sideset_pins(&c, pin);
+    sm_config_set_out_shift(&c, false, true, rgbw ? 32 : 24);
+    sm_config_set_fifo_join(&c, PIO_FIFO_JOIN_TX);
+
+    int cycles_per_bit = ws2812_T1 + ws2812_T2 + ws2812_T3;
+    float div = clock_get_hz(clk_sys) / (freq * cycles_per_bit);
+    sm_config_set_clkdiv(&c, div);
+
+    pio_sm_init(pio, sm, offset, &c);
+    pio_sm_set_enabled(pio, sm, true);
+}
+%}
+
+.program ws2812_parallel
+
+.define public T1 2
+.define public T2 5
+.define public T3 3
+
+.wrap_target
+    out x, 32
+    mov pins, !null [T1-1]
+    mov pins, x     [T2-1]
+    mov pins, null  [T3-2]
+.wrap
+
+% c-sdk {
+#include "hardware/clocks.h"
+
+static inline void ws2812_parallel_program_init(PIO pio, uint sm, uint offset, uint pin_base, uint pin_count, float freq) {
+    for(uint i=pin_base; i |int| @intCast(T, int),
+                .string => |str| outer: for (define_lists) |defines| {
+                    for (defines) |define| {
+                        if (std.mem.eql(u8, str, define.name)) {
+                            if (define.value > std.math.maxInt(T)) {
+                                diags.* = Diagnostics.init(
+                                    index,
+                                    "{s}'s value ({}) is too large to fit in {} bits",
+                                    .{ str, define.value, @bitSizeOf(T) },
+                                );
+
+                                break :outer error.TooBig;
+                            }
+
+                            break :outer @intCast(T, define.value);
+                        }
+                    }
+                } else {
+                    diags.* = Diagnostics.init(index, "define '{s}' not found", .{
+                        str,
+                    });
+
+                    break :outer error.DefineNotFound;
+                },
+                .expression => |expr_str| {
+                    const expr = try Expression.tokenize(expr_str, index, diags);
+                    const result = try expr.evaluate(define_lists, diags);
+                    if (result < 0 or result > std.math.maxInt(T)) {
+                        diags.* = Diagnostics.init(
+                            index,
+                            "value of {} does not fit in a u{}",
+                            .{
+                                result, @bitSizeOf(T),
+                            },
+                        );
+                    }
+
+                    return @intCast(T, result);
+                },
+            };
+        }
+
+        fn evaluate(
+            self: *Self,
+            comptime T: type,
+            program: BoundedProgram,
+            value: Value,
+            index: u32,
+            diags: *?Diagnostics,
+        ) !T {
+            return evaluate_impl(T, &.{
+                self.output.global_defines.slice(),
+                self.output.private_defines.slice(),
+                program.defines.slice(),
+                program.private_defines.slice(),
+            }, value, index, diags);
+        }
+
+        fn evaluate_target(
+            self: *Self,
+            program: BoundedProgram,
+            target: []const u8,
+            index: u32,
+            diags: *?Diagnostics,
+        ) !u5 {
+            return for (program.labels.slice()) |label| {
+                if (std.mem.eql(u8, target, label.name))
+                    break label.index;
+            } else try self.evaluate(u5, program, try Value.from_string(target), index, diags);
+        }
+
+        fn evaluate_global(
+            self: *Self,
+            comptime T: type,
+            value: Value,
+            index: u32,
+            diags: *?Diagnostics,
+        ) !T {
+            return evaluate_impl(T, &.{
+                self.output.global_defines.slice(),
+                self.output.private_defines.slice(),
+            }, value, index, diags);
+        }
+
+        fn encode_globals(self: *Self, diags: *?Diagnostics) !void {
+            assert(self.index == 0);
+
+            // read defines until program is had
+            while (self.peek_token()) |token| switch (token.data) {
+                .define => |define| {
+                    const result = DefineWithIndex{
+                        .name = define.name,
+                        .value = try self.evaluate_global(i128, define.value, token.index, diags),
+                        .index = define.index,
+                    };
+
+                    if (define.public)
+                        try self.output.global_defines.append(result)
+                    else
+                        try self.output.private_defines.append(result);
+
+                    self.consume(1);
+                },
+                .program => break,
+                else => return error.InvalidTokenInGlobalSpace,
+            };
+        }
+
+        fn encode_program_init(self: *Self, program: *BoundedProgram, diags: *?Diagnostics) !void {
+            while (self.peek_token()) |token| {
+                switch (token.data) {
+                    .program, .label, .instruction, .word, .wrap_target => break,
+                    .define => |define| {
+                        const result = DefineWithIndex{
+                            .name = define.name,
+                            .value = try self.evaluate(i128, program.*, define.value, token.index, diags),
+                            .index = define.index,
+                        };
+
+                        if (define.public)
+                            try program.defines.append(result)
+                        else
+                            try program.private_defines.append(result);
+
+                        self.consume(1);
+                    },
+                    .origin => |value| {
+                        program.origin = try self.evaluate(u5, program.*, value, token.index, diags);
+                        self.consume(1);
+                    },
+                    .side_set => |side_set| {
+                        program.side_set = .{
+                            .count = try self.evaluate(u3, program.*, side_set.count, token.index, diags),
+                            .optional = side_set.opt,
+                            .pindirs = side_set.pindirs,
+                        };
+                        self.consume(1);
+                    },
+                    // ignore
+                    .lang_opt => self.consume(1),
+                    .wrap => unreachable,
+                }
+            }
+        }
+
+        fn encode_instruction(
+            self: *Self,
+            program: *BoundedProgram,
+            token: Token.Instruction,
+            token_index: u32,
+            diags: *?Diagnostics,
+        ) !void {
+            // guaranteed to be an instruction variant
+            const payload: Instruction.Payload = switch (token.payload) {
+                .nop => .{
+                    .mov = .{
+                        .destination = .y,
+                        .operation = .none,
+                        .source = .y,
+                    },
+                },
+                .jmp => |jmp| .{
+                    .jmp = .{
+                        .condition = jmp.condition,
+                        .address = try self.evaluate_target(program.*, jmp.target, token_index, diags),
+                    },
+                },
+                .wait => |wait| .{
+                    .wait = .{
+                        .polarity = wait.polarity,
+                        .source = wait.source,
+                        .index = try self.evaluate(u5, program.*, wait.num, token_index, diags),
+                    },
+                },
+                .in => |in| .{
+                    .in = .{
+                        .source = in.source,
+                        .bit_count = in.bit_count,
+                    },
+                },
+                .out => |out| .{
+                    .out = .{
+                        .destination = out.destination,
+                        .bit_count = out.bit_count,
+                    },
+                },
+                .push => |push| .{
+                    .push = .{
+                        .if_full = @boolToInt(push.iffull),
+                        .block = @boolToInt(push.block),
+                    },
+                },
+                .pull => |pull| .{
+                    .pull = .{
+                        .if_empty = @boolToInt(pull.ifempty),
+                        .block = @boolToInt(pull.block),
+                    },
+                },
+                .mov => |mov| .{
+                    .mov = .{
+                        .destination = mov.destination,
+                        .operation = mov.operation,
+                        .source = mov.source,
+                    },
+                },
+                .irq => |irq| blk: {
+                    const irq_num = try self.evaluate(u5, program.*, irq.num, token_index, diags);
+                    break :blk .{
+                        .irq = .{
+                            .clear = @boolToInt(irq.clear),
+                            .wait = @boolToInt(irq.wait),
+                            .index = if (irq.rel)
+                                @as(u5, 0x10) | irq_num
+                            else
+                                irq_num,
+                        },
+                    };
+                },
+                .set => |set| .{
+                    .set = .{
+                        .destination = set.destination,
+                        .data = try self.evaluate(u5, program.*, set.value, token_index, diags),
+                    },
+                },
+            };
+
+            const tag: Instruction.Tag = switch (token.payload) {
+                .nop => .mov,
+                .jmp => .jmp,
+                .wait => .wait,
+                .in => .in,
+                .out => .out,
+                .push => .push_pull,
+                .pull => .push_pull,
+                .mov => .mov,
+                .irq => .irq,
+                .set => .set,
+            };
+
+            if (program.side_set) |side_set| {
+                if (!side_set.optional and token.side_set == null) {
+                    diags.* = Diagnostics.init(token_index, "'side' must be specified for this instruction because 'opt' was not specied in the .side_set directive", .{});
+                    return error.InvalidSideSet;
+                }
+            } else {
+                if (token.side_set != null) {
+                    diags.* = Diagnostics.init(token_index, ".side_set directive must be specified for program to use side_set", .{});
+                    return error.InvalidSideSet;
+                }
+            }
+
+            const side_set: ?u5 = if (token.side_set) |s|
+                try self.evaluate(u5, program.*, s, token_index, diags)
+            else
+                null;
+
+            const delay: ?u5 = if (token.delay) |d|
+                try self.evaluate(u5, program.*, d, token_index, diags)
+            else
+                null;
+
+            const delay_side_set = try calc_delay_side_set(
+                program.side_set,
+                side_set,
+                delay,
+            );
+
+            try program.instructions.append(Instruction{
+                .tag = tag,
+                .payload = payload,
+                .delay_side_set = delay_side_set,
+            });
+        }
+
+        fn calc_delay_side_set(
+            program_settings: ?SideSet,
+            side_set_opt: ?u5,
+            delay_opt: ?u5,
+        ) !u5 {
+            // TODO: error for side_set/delay collision
+            const delay: u5 = if (delay_opt) |delay| delay else 0;
+            return if (program_settings) |settings|
+                if (settings.optional)
+                    if (side_set_opt) |side_set|
+                        0x10 | (side_set << @as(u3, 4) - settings.count) | delay
+                    else
+                        delay
+                else
+                    (side_set_opt.? << @as(u3, 5) - settings.count) | delay
+            else
+                delay;
+        }
+
+        fn encode_instruction_body(self: *Self, program: *BoundedProgram, diags: *?Diagnostics) !void {
+            // first scan through body for labels
+            var instr_index: u5 = 0;
+            for (self.tokens[self.index..]) |token| {
+                switch (token.data) {
+                    .label => |label| try program.labels.append(.{
+                        .name = label.name,
+                        .public = label.public,
+                        .index = instr_index,
+                    }),
+                    .instruction, .word => instr_index += 1,
+                    .wrap_target => {
+                        if (program.wrap_target != null) {
+                            diags.* = Diagnostics.init(token.index, "wrap_target already set for this program", .{});
+                            return error.WrapTargetAlreadySet;
+                        }
+
+                        program.wrap_target = instr_index;
+                    },
+                    .wrap => {
+                        if (program.wrap != null) {
+                            diags.* = Diagnostics.init(token.index, "wrap already set for this program", .{});
+                            return error.WrapAlreadySet;
+                        }
+
+                        program.wrap = instr_index - 1;
+                    },
+                    .program => break,
+                    else => unreachable, // invalid
+                }
+            }
+
+            // encode instructions, labels will be populated
+            for (self.tokens[self.index..], self.index..) |token, i| {
+                switch (token.data) {
+                    .instruction => |instr| try self.encode_instruction(program, instr, token.index, diags),
+                    .word => |word| try program.instructions.append(
+                        @bitCast(Instruction, try self.evaluate(u16, program.*, word, token.index, diags)),
+                    ),
+                    // already processed
+                    .label, .wrap_target, .wrap => {},
+                    .program => {
+                        self.index = @intCast(u32, i);
+                        break;
+                    },
+
+                    else => unreachable, // invalid
+                }
+            } else if (self.tokens.len > 0)
+                self.index = @intCast(u32, self.tokens.len);
+        }
+
+        fn encode_program(self: *Self, diags: *?Diagnostics) !?BoundedProgram {
+            const program_token = self.get_token() orelse return null;
+            if (program_token.data != .program)
+                return error.ExpectedProgramToken;
+
+            var program = BoundedProgram{
+                .name = program_token.data.program,
+                .defines = BoundedDefines.init(0) catch unreachable,
+                .private_defines = BoundedDefines.init(0) catch unreachable,
+                .instructions = BoundedInstructions.init(0) catch unreachable,
+                .labels = BoundedLabels.init(0) catch unreachable,
+                .side_set = null,
+                .origin = null,
+                .wrap_target = null,
+                .wrap = null,
+            };
+
+            try self.encode_program_init(&program, diags);
+            try self.encode_instruction_body(&program, diags);
+
+            return program;
+        }
+
+        fn encode_output(self: *Self, diags: *?Diagnostics) !Self.Output {
+            try self.encode_globals(diags);
+
+            while (try self.encode_program(diags)) |program|
+                try self.output.programs.append(program);
+
+            return self.output;
+        }
+    };
+}
+
+pub const Instruction = packed struct(u16) {
+    payload: Payload,
+    delay_side_set: u5,
+    tag: Tag,
+
+    pub const Payload = packed union {
+        jmp: Jmp,
+        wait: Wait,
+        in: In,
+        out: Out,
+        push: Push,
+        pull: Pull,
+        mov: Mov,
+        irq: Irq,
+        set: Set,
+    };
+
+    pub const Tag = enum(u3) {
+        jmp,
+        wait,
+        in,
+        out,
+        push_pull,
+        mov,
+        irq,
+        set,
+    };
+
+    pub const Jmp = packed struct(u8) {
+        address: u5,
+        condition: Token.Instruction.Jmp.Condition,
+    };
+
+    pub const Wait = packed struct(u8) {
+        index: u5,
+        source: Token.Instruction.Wait.Source,
+        polarity: u1,
+    };
+
+    pub const In = packed struct(u8) {
+        bit_count: u5,
+        source: Token.Instruction.In.Source,
+    };
+
+    pub const Out = packed struct(u8) {
+        bit_count: u5,
+        destination: Token.Instruction.Out.Destination,
+    };
+
+    pub const Push = packed struct(u8) {
+        _reserved0: u5 = 0,
+        block: u1,
+        if_full: u1,
+        _reserved1: u1 = 0,
+    };
+
+    pub const Pull = packed struct(u8) {
+        _reserved0: u5 = 0,
+        block: u1,
+        if_empty: u1,
+        _reserved1: u1 = 1,
+    };
+
+    pub const Mov = packed struct(u8) {
+        source: Token.Instruction.Mov.Source,
+        operation: Token.Instruction.Mov.Operation,
+        destination: Token.Instruction.Mov.Destination,
+    };
+
+    pub const Irq = packed struct(u8) {
+        index: u5,
+        wait: u1,
+        clear: u1,
+        reserved: u1 = 0,
+    };
+
+    pub const Set = packed struct(u8) {
+        data: u5,
+        destination: Token.Instruction.Set.Destination,
+    };
+};
+
+//==============================================================================
+// Encoder Tests
+//==============================================================================
+
+const expect = std.testing.expect;
+const expectEqual = std.testing.expectEqual;
+const expectEqualStrings = std.testing.expectEqualStrings;
+
+fn encode_bounded_output_impl(source: []const u8, diags: *?assembler.Diagnostics) !Encoder(.{}).Output {
+    const tokens = try tokenizer.tokenize(source, diags, .{});
+    var encoder = Encoder(.{}).init(tokens.slice());
+    return try encoder.encode_output(diags);
+}
+
+fn encode_bounded_output(source: []const u8) !Encoder(.{}).Output {
+    var diags: ?assembler.Diagnostics = null;
+    return encode_bounded_output_impl(source, &diags) catch |err| if (diags) |d| blk: {
+        std.log.err("error at index {}: {s}", .{ d.index, d.message.slice() });
+        break :blk err;
+    } else err;
+}
+
+test "encode.define" {
+    const output = try encode_bounded_output(".define foo 5");
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 1), output.private_defines.len);
+    try expectEqual(@as(usize, 0), output.programs.len);
+
+    try expectEqualStrings("foo", output.private_defines.get(0).name);
+    try expectEqual(@as(i128, 5), output.private_defines.get(0).value);
+}
+
+test "encode.define.public" {
+    const output = try encode_bounded_output(".define PUBLIC foo 5");
+
+    try expectEqual(@as(usize, 1), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 0), output.programs.len);
+}
+
+test "encode.program.empty" {
+    const output = try encode_bounded_output(".program arst");
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    try expectEqualStrings("arst", output.programs.get(0).name);
+    try expectEqual(@as(usize, 0), output.programs.get(0).instructions.len);
+}
+
+test "encode.program.define" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\.define bruh 7
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+    try expectEqualStrings("arst", program.name);
+    try expectEqual(@as(usize, 0), program.instructions.len);
+
+    const define = program.private_defines.get(0);
+    try expectEqualStrings("bruh", define.name);
+    try expectEqual(@as(i128, 7), define.value);
+}
+
+test "encode.program.define.public" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\.define public bruh 7
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+    try expectEqualStrings("arst", program.name);
+    try expectEqual(@as(usize, 0), program.instructions.len);
+
+    const define = program.defines.get(0);
+    try expectEqualStrings("bruh", define.name);
+    try expectEqual(@as(i128, 7), define.value);
+}
+
+test "encode.program.define.namespaced" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\.define public bruh 7
+        \\.program what
+        \\.define public hi 8
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 2), output.programs.len);
+
+    const program_arst = output.programs.get(0);
+    try expectEqualStrings("arst", program_arst.name);
+    try expectEqual(@as(usize, 0), program_arst.instructions.len);
+
+    const define_bruh = program_arst.defines.get(0);
+    try expectEqualStrings("bruh", define_bruh.name);
+    try expectEqual(@as(i128, 7), define_bruh.value);
+
+    const program_what = output.programs.get(1);
+    try expectEqualStrings("what", program_what.name);
+    try expectEqual(@as(usize, 0), program_what.instructions.len);
+
+    const define_hi = program_what.defines.get(0);
+    try expectEqualStrings("hi", define_hi.name);
+    try expectEqual(@as(i128, 8), define_hi.value);
+}
+
+test "encode.origin" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\.origin 0
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+    try expectEqualStrings("arst", program.name);
+    try expectEqual(@as(usize, 0), program.instructions.len);
+
+    try expectEqual(@as(?u5, 0), program.origin);
+}
+
+test "encode.wrap_target" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\nop
+        \\.wrap_target
+        \\nop
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+    try expectEqualStrings("arst", program.name);
+    try expectEqual(@as(usize, 2), program.instructions.len);
+
+    try expectEqual(@as(?u5, 1), program.wrap_target);
+}
+
+test "encode.wrap" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\nop
+        \\.wrap
+        \\nop
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+    try expectEqualStrings("arst", program.name);
+    try expectEqual(@as(usize, 2), program.instructions.len);
+
+    try expectEqual(@as(?u5, 0), program.wrap);
+}
+
+test "encode.side_set" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\.side_set 1
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+    try expectEqual(@as(?u5, 1), program.side_set.?.count);
+}
+
+test "encode.side_set.opt" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\.side_set 1 opt
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+    try expectEqual(@as(?u5, 1), program.side_set.?.count);
+    try expect(program.side_set.?.optional);
+}
+
+test "encode.side_set.pindirs" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\.side_set 1 pindirs
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+    try expectEqual(@as(?u5, 1), program.side_set.?.count);
+    try expect(program.side_set.?.pindirs);
+}
+
+test "encode.label" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\nop
+        \\my_label:
+        \\nop
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+    try expectEqual(@as(usize, 1), program.labels.len);
+
+    const label = program.labels.get(0);
+    try expectEqualStrings("my_label", label.name);
+    try expectEqual(@as(u32, 1), label.index);
+    try expectEqual(false, label.public);
+}
+
+test "encode.label.public" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\nop
+        \\nop
+        \\public my_label:
+        \\nop
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+    try expectEqual(@as(usize, 1), program.labels.len);
+
+    const label = program.labels.get(0);
+    try expectEqualStrings("my_label", label.name);
+    try expectEqual(@as(u32, 2), label.index);
+    try expectEqual(true, label.public);
+}
+
+test "encode.side_set.bits" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\.side_set 1 opt
+        \\nop side 1
+        \\nop [1]
+        \\nop side 0 [1]
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+
+    const instr0 = program.instructions.get(0);
+    try expectEqual(@as(u5, 0x18), instr0.delay_side_set);
+
+    const instr1 = program.instructions.get(1);
+    try expectEqual(@as(u5, 0x1), instr1.delay_side_set);
+
+    const instr2 = program.instructions.get(2);
+    try expectEqual(@as(u5, 0x11), instr2.delay_side_set);
+}
+
+test "encode.evaluate.global" {
+    const output = try encode_bounded_output(
+        \\.define NUM 5
+        \\.define public FOO NUM
+    );
+
+    try expectEqual(@as(usize, 1), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.global_defines.len);
+    try expectEqualStrings("FOO", output.global_defines.get(0).name);
+    try expectEqual(@as(i128, 5), output.global_defines.get(0).value);
+}
+
+test "encode.evaluate.addition" {
+    const output = try encode_bounded_output(
+        \\.define public FOO (1+5)
+    );
+
+    try expectEqual(@as(usize, 1), output.global_defines.len);
+    try expectEqualStrings("FOO", output.global_defines.get(0).name);
+    try expectEqual(@as(i128, 6), output.global_defines.get(0).value);
+}
+
+test "encode.evaluate.subtraction" {
+    const output = try encode_bounded_output(
+        \\.define public FOO (5-1)
+    );
+
+    try expectEqual(@as(usize, 1), output.global_defines.len);
+    try expectEqualStrings("FOO", output.global_defines.get(0).name);
+    try expectEqual(@as(i128, 4), output.global_defines.get(0).value);
+}
+
+test "encode.evaluate.multiplication" {
+    const output = try encode_bounded_output(
+        \\.define public FOO (5*2)
+    );
+
+    try expectEqual(@as(usize, 1), output.global_defines.len);
+    try expectEqualStrings("FOO", output.global_defines.get(0).name);
+    try expectEqual(@as(i128, 10), output.global_defines.get(0).value);
+}
+
+test "encode.evaluate.division" {
+    const output = try encode_bounded_output(
+        \\.define public FOO (6/2)
+    );
+
+    try expectEqual(@as(usize, 1), output.global_defines.len);
+    try expectEqualStrings("FOO", output.global_defines.get(0).name);
+    try expectEqual(@as(i128, 3), output.global_defines.get(0).value);
+}
+
+test "encode.evaluate.bit reversal" {
+    const output = try encode_bounded_output(
+        \\.define public FOO ::1
+    );
+
+    try expectEqual(@as(usize, 1), output.global_defines.len);
+    try expectEqualStrings("FOO", output.global_defines.get(0).name);
+    try expectEqual(@as(i128, 0x80000000), output.global_defines.get(0).value);
+}
+
+test "encode.jmp.label" {
+    const output = try encode_bounded_output(
+        \\.program arst
+        \\nop
+        \\my_label:
+        \\nop
+        \\nop
+        \\jmp my_label
+    );
+
+    try expectEqual(@as(usize, 0), output.global_defines.len);
+    try expectEqual(@as(usize, 0), output.private_defines.len);
+    try expectEqual(@as(usize, 1), output.programs.len);
+
+    const program = output.programs.get(0);
+    try expectEqual(@as(usize, 1), program.labels.len);
+
+    const label = program.labels.get(0);
+    try expectEqualStrings("my_label", label.name);
+    try expectEqual(@as(u32, 1), label.index);
+    try expectEqual(false, label.public);
+
+    const instr = program.instructions.get(3);
+    try expectEqual(Instruction.Tag.jmp, instr.tag);
+    try expectEqual(@as(u5, 0), instr.delay_side_set);
+    try expectEqual(Token.Instruction.Jmp.Condition.always, instr.payload.jmp.condition);
+    try expectEqual(@as(u5, 1), instr.payload.jmp.address);
+}
+
+//test "encode.error.duplicated program name" {}
+//test "encode.error.duplicated define" {}
+//test "encode.error.multiple side_set" {}
+//test "encode.error.label with no instruction" {}
+//test "encode.error.label with no instruction" {}
+
+// Test Plan
+// =========
+//
+// - .program name validation
+// - .origin in program init and in program body
+// - .side_set must be in the program init
+// - .wrap_target must come before an instruction, defaults to start of a program
+// - .wrap_target must only be used once in a program
+// - .wrap must be placed after an instruction, defaults to end of a program
+// - .wrap must only be used once in a program
+// -
+//
diff --git a/src/hal/pio/assembler/tokenizer.zig b/src/hal/pio/assembler/tokenizer.zig
new file mode 100644
index 000000000..cc360f50f
--- /dev/null
+++ b/src/hal/pio/assembler/tokenizer.zig
@@ -0,0 +1,1947 @@
+const std = @import("std");
+const assert = std.debug.assert;
+
+const assembler = @import("../assembler.zig");
+const Diagnostics = assembler.Diagnostics;
+
+const Expression = @import("Expression.zig");
+
+pub const Options = struct {
+    capacity: u32 = 256,
+};
+
+pub fn tokenize(
+    source: []const u8,
+    diags: *?assembler.Diagnostics,
+    comptime options: Options,
+) !std.BoundedArray(Token, options.capacity) {
+    var tokens = std.BoundedArray(Token, options.capacity).init(0) catch unreachable;
+    var tokenizer = Tokenizer.init(source);
+    while (try tokenizer.next(diags)) |token|
+        try tokens.append(token);
+
+    return tokens;
+}
+
+pub const Value = union(enum) {
+    // integer, hex, binary
+    integer: u32,
+    // either a symbol or label
+    string: []const u8,
+    expression: []const u8,
+
+    pub fn format(
+        value: Value,
+        comptime fmt: []const u8,
+        options: std.fmt.FormatOptions,
+        writer: anytype,
+    ) !void {
+        _ = fmt;
+        _ = options;
+        switch (value) {
+            .string => |str| try writer.print("\"{s}\"", .{str}),
+            .expression => |expr| try writer.print("{s}", .{expr}),
+            .integer => |int| try writer.print("{}", .{int}),
+        }
+    }
+
+    pub fn from_string(str: []const u8) !Value {
+        return Value{
+            .integer = std.fmt.parseInt(u32, str, 0) catch {
+                return Value{
+                    .string = str,
+                };
+            },
+        };
+    }
+};
+
+// the characters we're interested in are:
+// ';' -> line comment
+// '/' -> '/' -> line comment
+// '/' -> '*' -> block comment
+// '%' ->  ->  ->  -> '{' -> code block
+// '.' -> directive
+pub const Tokenizer = struct {
+    source: []const u8,
+    index: u32,
+
+    pub fn format(
+        self: Tokenizer,
+        comptime fmt: []const u8,
+        options: std.fmt.FormatOptions,
+        writer: anytype,
+    ) !void {
+        _ = fmt;
+        _ = options;
+
+        try writer.print(
+            \\parser:
+            \\  index: {}
+            \\
+            \\
+        , .{self.index});
+
+        var printed_cursor = false;
+        var line_it = std.mem.tokenize(u8, self.source, "\n\r");
+        while (line_it.next()) |line| {
+            try writer.print("{s}\n", .{line});
+            if (!printed_cursor and line_it.index > self.index) {
+                try writer.writeByteNTimes(' ', line.len - (line_it.index - self.index));
+                try writer.writeAll("\x1b[30;42;1m^\x1b[0m\n");
+                printed_cursor = true;
+            }
+        }
+    }
+
+    fn init(source: []const u8) Tokenizer {
+        return Tokenizer{
+            .source = source,
+            .index = 0,
+        };
+    }
+
+    fn consume(self: *Tokenizer, count: u32) void {
+        assert(self.index < self.source.len);
+        self.index += count;
+    }
+
+    fn peek(self: Tokenizer) ?u8 {
+        return if (self.index < self.source.len)
+            self.source[self.index]
+        else
+            null;
+    }
+
+    fn get(self: *Tokenizer) ?u8 {
+        return if (self.index < self.source.len) blk: {
+            defer self.index += 1;
+            break :blk self.source[self.index];
+        } else null;
+    }
+
+    fn skip_line(self: *Tokenizer) void {
+        while (self.get()) |c|
+            if (c == '\n')
+                return;
+    }
+
+    fn skip_until_end_of_comment_block(self: *Tokenizer) void {
+        while (self.get()) |c| {
+            if (c == '*') {
+                if (self.peek()) |p| {
+                    self.consume(1);
+                    if (p == '/') {
+                        return;
+                    }
+                }
+            }
+        }
+    }
+
+    fn skip_until_end_of_code_block(self: *Tokenizer) void {
+        // TODO: assert we have the code identifier and open curly bracket
+        while (self.get()) |c| {
+            if (c == '%') {
+                if (self.peek()) |p| {
+                    self.consume(1);
+                    if (p == '}') {
+                        return;
+                    }
+                }
+            }
+        }
+    }
+
+    fn read_until_whitespace_or_end(self: *Tokenizer) ![]const u8 {
+        const start = self.index;
+        var end: ?u32 = null;
+        while (self.peek()) |p| {
+            switch (p) {
+                ' ', '\n', '\r', '\t', ',' => {
+                    end = self.index;
+                    break;
+                },
+                else => self.consume(1),
+            }
+        } else end = self.index;
+
+        return self.source[start .. end orelse return error.EndOfStream];
+    }
+
+    fn skip_whitespace(self: *Tokenizer) void {
+        while (self.peek()) |p| {
+            switch (p) {
+                ' ', '\t', '\r', '\n', ',' => self.consume(1),
+                else => return,
+            }
+        }
+    }
+
+    /// returns array of args
+    fn get_args(self: *Tokenizer, comptime num: u32, diags: *?Diagnostics) TokenizeError![num]?[]const u8 {
+        var args: [num]?[]const u8 = undefined;
+        for (&args) |*arg|
+            arg.* = try self.get_arg(diags);
+
+        return args;
+    }
+
+    const PeekResult = struct {
+        str: []const u8,
+        start: u32,
+    };
+
+    fn peek_arg(self: *Tokenizer, diags: *?Diagnostics) TokenizeError!?PeekResult {
+        var tmp_index = self.index;
+        return self.peek_arg_impl(&tmp_index, diags);
+    }
+
+    fn consume_peek(self: *Tokenizer, result: PeekResult) void {
+        assert(self.index <= result.start);
+        self.index = result.start + @intCast(u32, result.str.len);
+    }
+
+    /// gets next arg without consuming the stream
+    fn peek_arg_impl(
+        self: *Tokenizer,
+        index: *u32,
+        diags: *?Diagnostics,
+    ) TokenizeError!?PeekResult {
+
+        // skip whitespace
+        while (index.* < self.source.len) {
+            switch (self.source[index.*]) {
+                ' ', '\t', ',' => index.* += 1,
+                else => break,
+            }
+        }
+
+        if (index.* == self.source.len)
+            return null;
+
+        const start = index.*;
+        const end = end: {
+            break :end switch (self.source[start]) {
+                '(' => blk: {
+                    var depth: u32 = 0;
+                    break :blk while (index.* < self.source.len) : (index.* += 1) {
+                        switch (self.source[index.*]) {
+                            '(' => depth += 1,
+                            ')' => {
+                                depth -= 1;
+
+                                if (depth == 0) {
+                                    index.* += 1;
+                                    break index.*;
+                                }
+                            },
+                            else => {},
+                        }
+                    } else {
+                        diags.* = Diagnostics.init(start, "mismatched parenthesis", .{});
+                        return error.InvalidExpression;
+                    };
+                },
+                '[' => while (index.* < self.source.len) : (index.* += 1) {
+                    if (self.source[index.*] == ']') {
+                        index.* += 1;
+                        break index.*;
+                    }
+                } else {
+                    diags.* = Diagnostics.init(start, "mismatched parenthesis", .{});
+                    return error.InvalidExpression;
+                },
+                else => while (index.* < self.source.len) {
+                    switch (self.source[index.*]) {
+                        // ; and / are to stop at comments
+                        ' ', '\t', '\r', '\n', ',', ';', '/' => break index.*,
+                        else => index.* += 1,
+                    }
+                } else index.*,
+            };
+        };
+
+        return if (start != end)
+            PeekResult{
+                .str = self.source[start..end],
+                .start = start,
+            }
+        else
+            null;
+    }
+
+    fn get_arg(self: *Tokenizer, diags: *?Diagnostics) TokenizeError!?[]const u8 {
+        return if (try self.peek_arg_impl(&self.index, diags)) |result|
+            result.str
+        else
+            null;
+    }
+
+    const Identifier = struct {
+        index: u32,
+        str: []const u8,
+    };
+
+    fn get_identifier(self: *Tokenizer) TokenizeError!Identifier {
+        self.skip_whitespace();
+        return Identifier{
+            .index = self.index,
+            .str = try self.read_until_whitespace_or_end(),
+        };
+    }
+
+    const TokenizeError = error{
+        EndOfStream,
+        NoValue,
+        NotAnExpression,
+        Overflow,
+        InvalidCharacter,
+        InvalidSource,
+        InvalidCondition,
+        MissingArg,
+        InvalidDestination,
+        InvalidOperation,
+        InvalidExpression,
+        TooBig,
+    };
+
+    fn get_program(self: *Tokenizer, index: u32, diags: *?Diagnostics) TokenizeError!Token {
+        const name = (try self.get_arg(diags)) orelse {
+            diags.* = Diagnostics.init(index, "missing program name", .{});
+            return error.MissingArg;
+        };
+        return Token{
+            .index = index,
+            .data = .{ .program = name },
+        };
+    }
+
+    fn assert_is_lower(str: []const u8) void {
+        for (str) |c|
+            assert(std.ascii.isLower(c));
+    }
+
+    fn eql_lower(comptime lhs: []const u8, rhs: []const u8) bool {
+        assert_is_lower(lhs);
+        if (lhs.len != rhs.len)
+            return false;
+
+        var buf: [lhs.len]u8 = undefined;
+        for (&buf, rhs) |*b, r|
+            b.* = std.ascii.toLower(r);
+
+        return std.mem.eql(u8, &buf, lhs);
+    }
+
+    fn get_define(self: *Tokenizer, index: u32, diags: *?Diagnostics) TokenizeError!Token {
+        const maybe_public = try self.get_identifier();
+        var is_public = eql_lower("public", maybe_public.str);
+
+        const name = if (is_public)
+            try self.get_identifier()
+        else
+            maybe_public;
+
+        return Token{
+            .index = index,
+            .data = .{
+                .define = .{
+                    .name = name.str,
+                    .value = Value{
+                        .expression = (try self.get_arg(diags)) orelse {
+                            diags.* = Diagnostics.init(index, "failed to get expression", .{});
+                            return error.InvalidExpression;
+                        },
+                    },
+                    .public = is_public,
+                    .index = name.index,
+                },
+            },
+        };
+    }
+
+    fn get_expression(self: *Tokenizer) TokenizeError!Value {
+        const start = self.index;
+        var count: u32 = 1;
+
+        if (self.get()) |c|
+            if (c != '(')
+                return error.NotAnExpression;
+
+        while (self.get()) |c| {
+            switch (c) {
+                '(' => count += 1,
+                ')' => {
+                    count -= 1;
+                },
+                else => {},
+            }
+
+            if (count == 0) {
+                return Value{
+                    .expression = self.source[start..self.index],
+                };
+            }
+        } else {
+            return error.NotAnExpression;
+        }
+    }
+
+    fn get_value(self: *Tokenizer) TokenizeError!Value {
+        self.skip_whitespace();
+
+        if (self.peek()) |p|
+            if (p == '(')
+                return try self.get_expression()
+            else {
+                const identifier = try self.get_identifier();
+                return try Value.from_string(identifier.str);
+            }
+        else
+            return error.NoValue;
+    }
+
+    fn get_origin(self: *Tokenizer, index: u32, diags: *?Diagnostics) TokenizeError!Token {
+        _ = diags;
+        return Token{
+            .index = index,
+            .data = .{
+                .origin = try self.get_value(),
+            },
+        };
+    }
+
+    fn get_side_set(self: *Tokenizer, index: u32, diags: *?Diagnostics) TokenizeError!Token {
+        const args = try self.get_args(3, diags);
+        const count = try Value.from_string(args[0] orelse {
+            diags.* = Diagnostics.init(index, "missing count", .{});
+            return error.MissingArg;
+        });
+        var opt = false;
+        var pindirs = false;
+
+        if (args[1]) |arg| {
+            if (std.mem.eql(u8, "opt", arg))
+                opt = true
+            else if (std.mem.eql(u8, "pindirs", arg))
+                pindirs = true;
+        }
+
+        if (args[2]) |arg| {
+            if (std.mem.eql(u8, "pindirs", arg))
+                pindirs = true;
+        }
+
+        return Token{
+            .index = index,
+            .data = .{
+                .side_set = .{
+                    .count = count,
+                    .opt = opt,
+                    .pindirs = pindirs,
+                },
+            },
+        };
+    }
+
+    fn get_wrap_target(_: *Tokenizer, index: u32, _: *?Diagnostics) TokenizeError!Token {
+        return Token{
+            .index = index,
+            .data = .{ .wrap_target = {} },
+        };
+    }
+
+    fn get_wrap(_: *Tokenizer, index: u32, _: *?Diagnostics) TokenizeError!Token {
+        return Token{
+            .index = index,
+            .data = .{ .wrap = {} },
+        };
+    }
+
+    fn get_lang_opt(self: *Tokenizer, index: u32, diags: *?Diagnostics) TokenizeError!Token {
+        _ = diags;
+        return Token{
+            .index = index,
+            .data = .{
+                .lang_opt = .{
+                    .lang = (try self.get_identifier()).str,
+                    .name = (try self.get_identifier()).str,
+                    .option = (try self.get_identifier()).str,
+                },
+            },
+        };
+    }
+
+    fn get_word(self: *Tokenizer, index: u32, diags: *?Diagnostics) TokenizeError!Token {
+        _ = diags;
+        return Token{
+            .index = index,
+            .data = .{ .word = try self.get_value() },
+        };
+    }
+
+    const directives = std.ComptimeStringMap(*const fn (*Tokenizer, u32, *?Diagnostics) TokenizeError!Token, .{
+        .{ "program", get_program },
+        .{ "define", get_define },
+        .{ "origin", get_origin },
+        .{ "side_set", get_side_set },
+        .{ "wrap_target", get_wrap_target },
+        .{ "wrap", get_wrap },
+        .{ "lang_opt", get_lang_opt },
+        .{ "word", get_word },
+    });
+
+    fn get_directive(self: *Tokenizer, diags: *?Diagnostics) !Token {
+        const index = self.index;
+        const identifier = try self.read_until_whitespace_or_end();
+        return if (directives.get(identifier)) |handler| ret: {
+            const ret = try handler(self, index, diags);
+            self.skip_line();
+            break :ret ret;
+        } else error.InvalidDirective;
+    }
+
+    fn get_nop(_: *Tokenizer, _: *?Diagnostics) TokenizeError!Token.Instruction.Payload {
+        return Token.Instruction.Payload{
+            .nop = {},
+        };
+    }
+
+    fn target_from_string(str: []const u8) TokenizeError!Token.Instruction.Jmp.Target {
+        const value = Value.from_string(str);
+        return Token.Instruction.Payload{
+            .jmp = .{
+                .condition = .always,
+                .target = switch (value) {
+                    .string => |label| Token.Instruction.Jmp.Target{
+                        .label = label,
+                    },
+                    else => Token.Instruction.Jmp.Target{
+                        .value = value,
+                    },
+                },
+            },
+        };
+    }
+
+    fn get_jmp(self: *Tokenizer, diags: *?Diagnostics) TokenizeError!Token.Instruction.Payload {
+        const Condition = Token.Instruction.Jmp.Condition;
+        const conditions = std.ComptimeStringMap(Condition, .{
+            .{ "!x", .x_is_zero },
+            .{ "x--", .x_dec },
+            .{ "!y", .y_is_zero },
+            .{ "y--", .y_dec },
+            .{ "x!=y", .x_is_not_y },
+            .{ "pin", .pin },
+            .{ "!osre", .osre_not_empty },
+        });
+
+        const maybe_cond = (try self.get_arg(diags)) orelse return error.MissingArg;
+        const maybe_cond_lower = try lowercase_bounded(256, maybe_cond);
+        const cond: Condition = conditions.get(maybe_cond_lower.slice()) orelse .always;
+        const target_str = if (cond == .always)
+            maybe_cond
+        else
+            (try self.get_arg(diags)) orelse return error.MissingArg;
+
+        return Token.Instruction.Payload{
+            .jmp = .{ .condition = cond, .target = target_str },
+        };
+    }
+
+    fn get_wait(self: *Tokenizer, diags: *?Diagnostics) TokenizeError!Token.Instruction.Payload {
+        const polarity = try std.fmt.parseInt(u1, (try self.get_arg(diags)) orelse return error.MissingArg, 0);
+        const source_str = (try self.get_arg(diags)) orelse return error.MissingArg;
+        const pin = try Value.from_string((try self.get_arg(diags)) orelse return error.MissingArg);
+
+        var buf: [8]u8 = undefined;
+        for (source_str, 0..) |c, i|
+            buf[i] = std.ascii.toLower(c);
+
+        const source_lower = buf[0..source_str.len];
+        const source: Token.Instruction.Wait.Source =
+            if (std.mem.eql(u8, "gpio", source_lower))
+            .gpio
+        else if (std.mem.eql(u8, "pin", source_lower))
+            .pin
+        else if (std.mem.eql(u8, "irq", source_lower))
+            .irq
+        else
+            return error.InvalidSource;
+
+        const rel: bool = if (source == .irq)
+            if (try self.peek_arg(diags)) |rel_result| blk: {
+                const is_rel = std.mem.eql(u8, "rel", rel_result.str);
+                if (is_rel)
+                    self.consume_peek(rel_result);
+
+                break :blk is_rel;
+            } else false
+        else
+            false;
+
+        return Token.Instruction.Payload{
+            .wait = .{
+                .polarity = polarity,
+                .source = source,
+                .num = pin,
+                .rel = rel,
+            },
+        };
+    }
+
+    /// get the lowercase of a string, returns an error if it's too big
+    fn lowercase_bounded(comptime max_size: usize, str: []const u8) TokenizeError!std.BoundedArray(u8, max_size) {
+        if (str.len > max_size)
+            return error.TooBig;
+
+        var ret = std.BoundedArray(u8, max_size).init(0) catch unreachable;
+        for (str) |c|
+            try ret.append(std.ascii.toLower(c));
+
+        return ret;
+    }
+
+    // TODO: I need to take a break. There is no rush to finish this. The thing
+    // I need to keep in mind with `get_args()` is that I must only consume the
+    // args that are used. side set and delay may be on the same line
+
+    fn get_in(self: *Tokenizer, diags: *?Diagnostics) TokenizeError!Token.Instruction.Payload {
+        const source_str = (try self.get_arg(diags)) orelse return error.MissingArg;
+        const bit_count_str = (try self.get_arg(diags)) orelse return error.MissingArg;
+
+        const source_lower = try lowercase_bounded(256, source_str);
+        const bit_count_tmp = try std.fmt.parseInt(u6, bit_count_str, 0);
+        const bit_count = if (bit_count_tmp == 32)
+            @as(u5, 0)
+        else
+            @intCast(u5, bit_count_tmp);
+
+        return Token.Instruction.Payload{
+            .in = .{
+                .source = std.meta.stringToEnum(Token.Instruction.In.Source, source_lower.slice()) orelse return error.InvalidSource,
+                .bit_count = bit_count,
+            },
+        };
+    }
+
+    fn get_out(self: *Tokenizer, diags: *?Diagnostics) TokenizeError!Token.Instruction.Payload {
+        const dest_src = (try self.get_arg(diags)) orelse return error.MissingArg;
+        const bit_count_str = (try self.get_arg(diags)) orelse return error.MissingArg;
+
+        const dest_lower = try lowercase_bounded(256, dest_src);
+        const bit_count_tmp = try std.fmt.parseInt(u6, bit_count_str, 0);
+        const bit_count = if (bit_count_tmp == 32)
+            @as(u5, 0)
+        else
+            @intCast(u5, bit_count_tmp);
+
+        return Token.Instruction.Payload{
+            .out = .{
+                .destination = std.meta.stringToEnum(Token.Instruction.Out.Destination, dest_lower.slice()) orelse return error.InvalidDestination,
+                .bit_count = bit_count,
+            },
+        };
+    }
+
+    fn block_from_peek(self: *Tokenizer, result: PeekResult) TokenizeError!bool {
+        const block_lower = try lowercase_bounded(256, result.str);
+        const is_block = std.mem.eql(u8, "block", block_lower.slice());
+        const is_noblock = std.mem.eql(u8, "noblock", block_lower.slice());
+
+        if (is_block or is_noblock)
+            self.consume_peek(result);
+
+        return if (is_block)
+            true
+        else if (is_noblock)
+            false
+        else
+            true;
+    }
+
+    fn get_push(self: *Tokenizer, diags: *?Diagnostics) TokenizeError!Token.Instruction.Payload {
+        return if (try self.peek_arg(diags)) |first_result| ret: {
+            const lower = try lowercase_bounded(256, first_result.str);
+            const iffull = std.mem.eql(u8, "iffull", lower.slice());
+
+            const block: bool = if (iffull) blk: {
+                self.consume_peek(first_result);
+                break :blk if (try self.peek_arg(diags)) |block_result|
+                    try self.block_from_peek(block_result)
+                else
+                    true;
+            } else try self.block_from_peek(first_result);
+
+            break :ret Token.Instruction.Payload{
+                .push = .{
+                    .iffull = iffull,
+                    .block = block,
+                },
+            };
+        } else Token.Instruction.Payload{
+            .push = .{
+                .iffull = false,
+                .block = true,
+            },
+        };
+    }
+
+    fn get_pull(self: *Tokenizer, diags: *?Diagnostics) TokenizeError!Token.Instruction.Payload {
+        return if (try self.peek_arg(diags)) |first_result| ret: {
+            const lower = try lowercase_bounded(256, first_result.str);
+            const ifempty = std.mem.eql(u8, "ifempty", lower.slice());
+
+            const block: bool = if (ifempty) blk: {
+                self.consume_peek(first_result);
+                break :blk if (try self.peek_arg(diags)) |block_result|
+                    try self.block_from_peek(block_result)
+                else
+                    true;
+            } else try self.block_from_peek(first_result);
+
+            break :ret Token.Instruction.Payload{
+                .pull = .{
+                    .ifempty = ifempty,
+                    .block = block,
+                },
+            };
+        } else Token.Instruction.Payload{
+            .pull = .{
+                .ifempty = false,
+                .block = true,
+            },
+        };
+    }
+
+    fn get_mov(self: *Tokenizer, diags: *?Diagnostics) TokenizeError!Token.Instruction.Payload {
+        const dest_str = (try self.get_arg(diags)) orelse return error.MissingArg;
+        const dest_lower = try lowercase_bounded(256, dest_str);
+        const destination = std.meta.stringToEnum(Token.Instruction.Mov.Destination, dest_lower.slice()) orelse return error.InvalidDestination;
+
+        const second = try self.get_arg(diags) orelse return error.MissingArg;
+        const op_prefixed: ?[]const u8 = if (std.mem.startsWith(u8, second, "!"))
+            "!"
+        else if (std.mem.startsWith(u8, second, "~"))
+            "~"
+        else if (std.mem.startsWith(u8, second, "::"))
+            "::"
+        else
+            null;
+
+        const source_str = if (op_prefixed) |op_str|
+            if (second.len == op_str.len)
+                (try self.get_arg(diags)) orelse return error.MissingArg
+            else
+                second[op_str.len..]
+        else
+            second;
+
+        const source_lower = try lowercase_bounded(256, source_str);
+        const source = std.meta.stringToEnum(Token.Instruction.Mov.Source, source_lower.slice()) orelse return error.InvalidSource;
+        const operation: Token.Instruction.Mov.Operation = if (op_prefixed) |op_str|
+            if (std.mem.eql(u8, "!", op_str))
+                .invert
+            else if (std.mem.eql(u8, "~", op_str))
+                .invert
+            else if (std.mem.eql(u8, "::", op_str))
+                .bit_reverse
+            else
+                return error.InvalidOperation
+        else
+            .none;
+
+        return Token.Instruction.Payload{
+            .mov = .{
+                .destination = destination,
+                .source = source,
+                .operation = operation,
+            },
+        };
+    }
+
+    fn get_irq(self: *Tokenizer, diags: *?Diagnostics) TokenizeError!Token.Instruction.Payload {
+        const first = (try self.get_arg(diags)) orelse return error.MissingArg;
+
+        var clear = false;
+        var wait = false;
+        var has_mode = false;
+        const first_lower = try lowercase_bounded(256, first);
+        if (std.mem.eql(u8, "set", first_lower.slice())) {
+            has_mode = true;
+            // do nothing
+        } else if (std.mem.eql(u8, "nowait", first_lower.slice())) {
+            has_mode = true;
+            // do nothing
+        } else if (std.mem.eql(u8, "wait", first_lower.slice())) {
+            has_mode = true;
+            wait = true;
+        } else if (std.mem.eql(u8, "clear", first_lower.slice())) {
+            has_mode = true;
+            clear = true;
+        }
+
+        const num = Value{
+            .expression = if (has_mode)
+                (try self.get_arg(diags)) orelse {
+                    diags.* = Diagnostics.init(self.index, "irq (mode)  (rel): failed to get num argument", .{});
+                    return error.MissingArg;
+                }
+            else
+                first,
+        };
+
+        const rel: bool = if (try self.peek_arg(diags)) |result| blk: {
+            const rel_lower = try lowercase_bounded(256, result.str);
+            const is_rel = std.mem.eql(u8, "rel", rel_lower.slice());
+            if (is_rel)
+                self.consume_peek(result);
+
+            break :blk is_rel;
+        } else false;
+
+        return Token.Instruction.Payload{
+            .irq = .{
+                .clear = clear,
+                .wait = wait,
+                .num = num,
+                .rel = rel,
+            },
+        };
+    }
+
+    fn get_set(self: *Tokenizer, diags: *?Diagnostics) TokenizeError!Token.Instruction.Payload {
+        const dest_str = (try self.get_arg(diags)) orelse {
+            diags.* = Diagnostics.init(0, "missing destination", .{});
+            return error.MissingArg;
+        };
+        const value = try self.get_value();
+
+        const dest_lower = try lowercase_bounded(256, dest_str);
+
+        return Token.Instruction.Payload{
+            .set = .{
+                .destination = std.meta.stringToEnum(Token.Instruction.Set.Destination, dest_lower.slice()) orelse return error.InvalidDestination,
+                .value = value,
+            },
+        };
+    }
+
+    const instructions = std.ComptimeStringMap(*const fn (*Tokenizer, *?Diagnostics) TokenizeError!Token.Instruction.Payload, .{
+        .{ "nop", get_nop },
+        .{ "jmp", get_jmp },
+        .{ "wait", get_wait },
+        .{ "in", get_in },
+        .{ "out", get_out },
+        .{ "push", get_push },
+        .{ "pull", get_pull },
+        .{ "mov", get_mov },
+        .{ "irq", get_irq },
+        .{ "set", get_set },
+    });
+
+    fn get_instruction(self: *Tokenizer, name: Identifier, diags: *?Diagnostics) !Token {
+        const name_lower = try lowercase_bounded(256, name.str);
+        const payload = if (instructions.get(name_lower.slice())) |handler|
+            try handler(self, diags)
+        else {
+            diags.* = Diagnostics.init(name.index, "invalid instruction", .{});
+            return error.InvalidInstruction;
+        };
+
+        var side_set: ?Value = null;
+        var delay: ?Value = null;
+
+        if (try self.peek_arg(diags)) |result| {
+            if (eql_lower("side", result.str)) {
+                self.consume_peek(result);
+
+                const side_set_str = (try self.get_arg(diags)) orelse return error.MissingArg;
+                side_set = Value{ .expression = side_set_str };
+            } else if (std.mem.startsWith(u8, result.str, "[") and std.mem.endsWith(u8, result.str, "]")) {
+                self.consume_peek(result);
+                delay = Value{ .expression = result.str[1 .. result.str.len - 1] };
+            }
+        }
+
+        if (try self.peek_arg(diags)) |result| {
+            if (eql_lower("side", result.str)) {
+                self.consume_peek(result);
+
+                const side_set_str = (try self.get_arg(diags)) orelse return error.MissingArg;
+                assert(side_set == null);
+                side_set = Value{ .expression = side_set_str };
+            } else if (std.mem.startsWith(u8, result.str, "[") and std.mem.endsWith(u8, result.str, "]")) {
+                self.consume_peek(result);
+                assert(delay == null);
+                delay = Value{
+                    .expression = result.str[1 .. result.str.len - 1],
+                };
+            }
+        }
+
+        self.skip_line();
+        return Token{
+            .index = name.index,
+            .data = .{
+                .instruction = .{
+                    .payload = payload,
+                    .side_set = side_set,
+                    .delay = delay,
+                },
+            },
+        };
+    }
+
+    fn next(self: *Tokenizer, diags: *?assembler.Diagnostics) !?Token {
+        while (self.peek()) |p| {
+            switch (p) {
+                ' ', '\t', '\n', '\r', ',' => self.consume(1),
+                ';' => self.skip_line(),
+                '/' => {
+                    self.consume(1);
+                    if (self.peek()) |p2| {
+                        self.consume(1);
+                        switch (p2) {
+                            '/' => self.skip_line(),
+                            '*' => self.skip_until_end_of_comment_block(),
+                            else => unreachable,
+                        }
+                    } else return null;
+                },
+                '%' => {
+                    self.consume(1);
+                    self.skip_until_end_of_code_block();
+                },
+                '.' => {
+                    self.consume(1);
+                    return try self.get_directive(diags);
+                },
+                'a'...'z', 'A'...'Z', '0'...'9', '_' => {
+                    const first = try self.get_identifier();
+
+                    // definitely a label
+                    return if (eql_lower("public", first.str))
+                        Token{
+                            .index = first.index,
+                            .data = .{
+                                .label = .{
+                                    .public = true,
+                                    .name = blk: {
+                                        const tmp = (try self.get_identifier()).str;
+                                        break :blk tmp[0 .. tmp.len - 1];
+                                    },
+                                },
+                            },
+                        }
+                    else if (std.mem.endsWith(u8, first.str, ":"))
+                        Token{
+                            .index = first.index,
+                            .data = .{
+                                .label = .{
+                                    .name = first.str[0 .. first.str.len - 1],
+                                },
+                            },
+                        }
+                    else
+                        try self.get_instruction(first, diags);
+                },
+                else => return error.Unhandled,
+            }
+        }
+
+        return null;
+    }
+};
+
+pub const Token = struct {
+    index: u32,
+    data: union(enum) {
+        program: []const u8,
+        define: Token.Define,
+        origin: Value,
+        side_set: SideSet,
+        wrap_target: void,
+        wrap: void,
+        lang_opt: LangOpt,
+        word: Value,
+        label: Label,
+        instruction: Instruction,
+    },
+
+    pub const Tag = std.meta.Tag(std.meta.FieldType(Token, .data));
+
+    pub const Label = struct {
+        name: []const u8,
+        public: bool = false,
+    };
+
+    // TODO: use Value instead of numbers
+    pub const Instruction = struct {
+        payload: Payload,
+        side_set: ?Value = null,
+        // TODO: delay can look like [T1-1], so we could consider the square
+        // brackets to be an expression
+        delay: ?Value = null,
+
+        pub const Payload = union(enum) {
+            nop: void,
+            jmp: Jmp,
+            wait: Wait,
+            in: In,
+            out: Out,
+            push: Push,
+            pull: Pull,
+            mov: Mov,
+            irq: Irq,
+            set: Set,
+        };
+
+        pub const Jmp = struct {
+            condition: Condition,
+            target: []const u8,
+
+            pub const Condition = enum(u3) {
+                always = 0b000,
+                x_is_zero = 0b001, // !X
+                x_dec = 0b010, // X--
+                y_is_zero = 0b011, // !Y
+                y_dec = 0b100, // Y--
+                x_is_not_y = 0b101, //X!=Y
+                pin = 0b110, // PIN
+                osre_not_empty = 0b111, // !OSRE
+            };
+        };
+
+        pub const Wait = struct {
+            polarity: u1,
+            source: Source,
+            num: Value,
+            rel: bool,
+
+            pub const Source = enum(u2) {
+                gpio = 0b00,
+                pin = 0b01,
+                irq = 0b10,
+            };
+        };
+
+        pub const In = struct {
+            source: Source,
+            bit_count: u5,
+
+            pub const Source = enum(u3) {
+                pins = 0b00,
+                x = 0b001,
+                y = 0b010,
+                null = 0b011,
+                isr = 0b110,
+                osr = 0b111,
+            };
+        };
+
+        pub const Out = struct {
+            destination: Destination,
+            bit_count: u5,
+
+            pub const Destination = enum(u3) {
+                pins = 0b000,
+                x = 0b001,
+                y = 0b010,
+                null = 0b011,
+                pindirs = 0b100,
+                pc = 0b101,
+                isr = 0b110,
+                exec = 0b111,
+            };
+        };
+
+        pub const Push = struct {
+            block: bool,
+            iffull: bool,
+        };
+
+        pub const Pull = struct {
+            block: bool,
+            ifempty: bool,
+        };
+
+        pub const Mov = struct {
+            destination: Destination,
+            operation: Operation,
+            source: Source,
+
+            pub const Destination = enum(u3) {
+                pins = 0b000,
+                x = 0b001,
+                y = 0b010,
+                exec = 0b100,
+                pc = 0b101,
+                isr = 0b110,
+                osr = 0b111,
+            };
+
+            pub const Operation = enum(u2) {
+                none = 0b00,
+                invert = 0b01,
+                bit_reverse = 0b10,
+            };
+
+            pub const Source = enum(u3) {
+                pins = 0b00,
+                x = 0b001,
+                y = 0b010,
+                null = 0b011,
+                status = 0b101,
+                isr = 0b110,
+                osr = 0b111,
+            };
+        };
+
+        pub const Irq = struct {
+            clear: bool,
+            wait: bool,
+            num: Value,
+            rel: bool,
+        };
+
+        pub const Set = struct {
+            destination: Destination,
+            value: Value,
+
+            pub const Destination = enum(u3) {
+                pins = 0b000,
+                x = 0b001,
+                y = 0b010,
+                pindirs = 0b100,
+            };
+        };
+    };
+
+    pub const Define = struct {
+        name: []const u8,
+        value: Value,
+        public: bool = false,
+        index: u32,
+    };
+
+    pub const SideSet = struct {
+        count: Value,
+        opt: bool = false,
+        pindirs: bool = false,
+    };
+
+    pub const LangOpt = struct {
+        lang: []const u8,
+        name: []const u8,
+        option: []const u8,
+    };
+};
+
+//==============================================================================
+// Tokenization Tests
+//==============================================================================
+
+const expect = std.testing.expect;
+const expectEqual = std.testing.expectEqual;
+const expectEqualStrings = std.testing.expectEqualStrings;
+
+const DirectiveTag = @typeInfo(Token.Directive).Union.tag_type.?;
+const PayloadTag = @typeInfo(Token.Instruction.Payload).Union.tag_type.?;
+
+fn expect_program(expected: []const u8, actual: Token) !void {
+    try expectEqual(Token.Tag.program, actual.data);
+    try expectEqualStrings(expected, actual.data.program);
+}
+
+fn expect_value(expected: Value, actual: Value) !void {
+    switch (expected) {
+        .integer => |int| try expectEqual(int, actual.integer),
+        .string => |str| try expectEqualStrings(str, actual.string),
+        .expression => |expr| try expectEqualStrings(expr, actual.expression),
+    }
+}
+
+fn expect_opt_value(expected: ?Value, actual: ?Value) !void {
+    if (expected != null)
+        switch (expected.?) {
+            .integer => |int| try expectEqual(int, actual.?.integer),
+            .string => |str| try expectEqualStrings(str, actual.?.string),
+            .expression => |expr| try expectEqualStrings(expr, actual.?.expression),
+        };
+}
+
+fn expect_define(expected: Token.Define, actual: Token) !void {
+    try expectEqual(Token.Tag.define, actual.data);
+
+    const define = actual.data.define;
+    try expectEqualStrings(expected.name, define.name);
+    try expect_value(expected.value, define.value);
+}
+
+fn expect_origin(expected: Value, actual: Token) !void {
+    try expectEqual(Token.Tag.origin, actual.data);
+    try expect_value(expected, actual.data.origin);
+}
+
+fn expect_side_set(expected: Token.SideSet, actual: Token) !void {
+    try expectEqual(Token.Tag.side_set, actual.data);
+
+    const side_set = actual.data.side_set;
+    try expect_value(expected.count, side_set.count);
+    try expectEqual(expected.opt, side_set.opt);
+    try expectEqual(expected.pindirs, side_set.pindirs);
+}
+
+fn expect_wrap_target(actual: Token) !void {
+    try expectEqual(Token.Tag.wrap_target, actual.data);
+}
+
+fn expect_wrap(actual: Token) !void {
+    try expectEqual(Token.Tag.wrap, actual.data);
+}
+
+fn expect_lang_opt(expected: Token.LangOpt, actual: Token) !void {
+    try expectEqual(Token.Tag.lang_opt, actual.data);
+
+    const lang_opt = actual.data.lang_opt;
+    try expectEqualStrings(expected.lang, lang_opt.lang);
+    try expectEqualStrings(expected.name, lang_opt.name);
+    try expectEqualStrings(expected.option, lang_opt.option);
+}
+
+fn expect_word(expected: Value, actual: Token) !void {
+    try expectEqual(Token.Tag.word, actual.data);
+    try expect_value(expected, actual.data.word);
+}
+
+fn expect_label(expected: Token.Label, actual: Token) !void {
+    try expectEqual(Token.Tag.label, actual.data);
+
+    const label = actual.data.label;
+    try expectEqual(expected.public, label.public);
+    try expectEqualStrings(expected.name, label.name);
+}
+
+const ExpectedNopInstr = struct {
+    delay: ?Value = null,
+    side_set: ?Value = null,
+};
+
+fn expect_instr_nop(expected: ExpectedNopInstr, actual: Token) !void {
+    try expectEqual(Token.Tag.instruction, actual.data);
+    try expectEqual(PayloadTag.nop, actual.data.instruction.payload);
+
+    const instr = actual.data.instruction;
+    try expect_opt_value(expected.delay, instr.delay);
+    try expect_opt_value(expected.side_set, instr.side_set);
+}
+
+const ExpectedSetInstr = struct {
+    dest: Token.Instruction.Set.Destination,
+    value: Value,
+    delay: ?Value = null,
+    side_set: ?Value = null,
+};
+
+fn expect_instr_set(expected: ExpectedSetInstr, actual: Token) !void {
+    try expectEqual(Token.Tag.instruction, actual.data);
+    try expectEqual(PayloadTag.set, actual.data.instruction.payload);
+
+    const instr = actual.data.instruction;
+    try expect_opt_value(expected.delay, instr.delay);
+    try expect_opt_value(expected.side_set, instr.side_set);
+
+    const set = instr.payload.set;
+    try expectEqual(expected.dest, set.destination);
+    try expect_value(expected.value, set.value);
+}
+
+const ExpectedJmpInstr = struct {
+    cond: Token.Instruction.Jmp.Condition = .always,
+    target: []const u8,
+    delay: ?Value = null,
+    side_set: ?Value = null,
+};
+
+fn expect_instr_jmp(expected: ExpectedJmpInstr, actual: Token) !void {
+    try expectEqual(Token.Tag.instruction, actual.data);
+    try expectEqual(PayloadTag.jmp, actual.data.instruction.payload);
+
+    const instr = actual.data.instruction;
+    try expect_opt_value(expected.delay, instr.delay);
+    try expect_opt_value(expected.side_set, instr.side_set);
+
+    const jmp = instr.payload.jmp;
+    try expectEqual(expected.cond, jmp.condition);
+    try expectEqualStrings(expected.target, jmp.target);
+}
+
+const ExpectedWaitInstr = struct {
+    polarity: u1,
+    source: Token.Instruction.Wait.Source,
+    num: Value,
+    // only valid for irq source
+    rel: bool = false,
+    delay: ?Value = null,
+    side_set: ?Value = null,
+};
+
+fn expect_instr_wait(expected: ExpectedWaitInstr, actual: Token) !void {
+    try expectEqual(Token.Tag.instruction, actual.data);
+    try expectEqual(PayloadTag.wait, actual.data.instruction.payload);
+
+    const instr = actual.data.instruction;
+    try expect_opt_value(expected.delay, instr.delay);
+    try expect_opt_value(expected.side_set, instr.side_set);
+
+    const wait = instr.payload.wait;
+    try expectEqual(expected.polarity, wait.polarity);
+    try expectEqual(expected.source, wait.source);
+    try expect_value(expected.num, wait.num);
+}
+
+const ExpectedInInstr = struct {
+    source: Token.Instruction.In.Source,
+    bit_count: u5,
+    delay: ?Value = null,
+    side_set: ?Value = null,
+};
+
+fn expect_instr_in(expected: ExpectedInInstr, actual: Token) !void {
+    try expectEqual(Token.Tag.instruction, actual.data);
+    try expectEqual(PayloadTag.in, actual.data.instruction.payload);
+
+    const instr = actual.data.instruction;
+    try expect_opt_value(expected.delay, instr.delay);
+    try expect_opt_value(expected.side_set, instr.side_set);
+
+    const in = instr.payload.in;
+    try expectEqual(expected.source, in.source);
+    try expectEqual(expected.bit_count, in.bit_count);
+}
+
+const ExpectedOutInstr = struct {
+    destination: Token.Instruction.Out.Destination,
+    bit_count: u5,
+    delay: ?Value = null,
+    side_set: ?Value = null,
+};
+
+fn expect_instr_out(expected: ExpectedOutInstr, actual: Token) !void {
+    try expectEqual(Token.Tag.instruction, actual.data);
+    try expectEqual(PayloadTag.out, actual.data.instruction.payload);
+
+    const instr = actual.data.instruction;
+    try expect_opt_value(expected.delay, instr.delay);
+    try expect_opt_value(expected.side_set, instr.side_set);
+
+    const out = instr.payload.out;
+    try expectEqual(expected.destination, out.destination);
+    try expectEqual(expected.bit_count, out.bit_count);
+}
+
+const ExpectedPushInstr = struct {
+    block: bool = true,
+    iffull: bool = false,
+    delay: ?Value = null,
+    side_set: ?Value = null,
+};
+
+fn expect_instr_push(expected: ExpectedPushInstr, actual: Token) !void {
+    try expectEqual(Token.Tag.instruction, actual.data);
+    try expectEqual(PayloadTag.push, actual.data.instruction.payload);
+
+    const instr = actual.data.instruction;
+    try expect_opt_value(expected.delay, instr.delay);
+    try expect_opt_value(expected.side_set, instr.side_set);
+
+    const push = instr.payload.push;
+    try expectEqual(expected.block, push.block);
+    try expectEqual(expected.iffull, push.iffull);
+}
+
+const ExpectedPullInstr = struct {
+    block: bool = true,
+    ifempty: bool = false,
+    delay: ?Value = null,
+    side_set: ?Value = null,
+};
+
+fn expect_instr_pull(expected: ExpectedPullInstr, actual: Token) !void {
+    try expectEqual(Token.Tag.instruction, actual.data);
+    try expectEqual(PayloadTag.pull, actual.data.instruction.payload);
+
+    const instr = actual.data.instruction;
+    try expect_opt_value(expected.delay, instr.delay);
+    try expect_opt_value(expected.side_set, instr.side_set);
+
+    const pull = instr.payload.pull;
+    try expectEqual(expected.block, pull.block);
+    try expectEqual(expected.ifempty, pull.ifempty);
+}
+
+const ExpectedMovInstr = struct {
+    source: Token.Instruction.Mov.Source,
+    destination: Token.Instruction.Mov.Destination,
+    operation: Token.Instruction.Mov.Operation = .none,
+    delay: ?Value = null,
+    side_set: ?Value = null,
+};
+
+fn expect_instr_mov(expected: ExpectedMovInstr, actual: Token) !void {
+    try expectEqual(Token.Tag.instruction, actual.data);
+    try expectEqual(PayloadTag.mov, actual.data.instruction.payload);
+
+    const instr = actual.data.instruction;
+    try expect_opt_value(expected.delay, instr.delay);
+    try expect_opt_value(expected.side_set, instr.side_set);
+
+    const mov = instr.payload.mov;
+    try expectEqual(expected.source, mov.source);
+    try expectEqual(expected.operation, mov.operation);
+    try expectEqual(expected.destination, mov.destination);
+}
+
+const ExpectedIrqInstr = struct {
+    clear: bool,
+    wait: bool,
+    num: u5,
+    rel: bool = false,
+    delay: ?Value = null,
+    side_set: ?Value = null,
+};
+
+fn expect_instr_irq(expected: ExpectedIrqInstr, actual: Token) !void {
+    try expectEqual(Token.Tag.instruction, actual.data);
+    try expectEqual(PayloadTag.irq, actual.data.instruction.payload);
+
+    const instr = actual.data.instruction;
+    try expect_opt_value(expected.delay, instr.delay);
+    try expect_opt_value(expected.side_set, instr.side_set);
+
+    const irq = instr.payload.irq;
+    try expectEqual(expected.clear, irq.clear);
+    try expectEqual(expected.wait, irq.wait);
+    try expectEqual(expected.rel, irq.rel);
+}
+
+fn bounded_tokenize(source: []const u8) !std.BoundedArray(Token, 256) {
+    var diags: ?assembler.Diagnostics = null;
+    return tokenize(source, &diags, .{}) catch |err| if (diags) |d| blk: {
+        std.log.err("error at index {}: {s}", .{ d.index, d.message.slice() });
+        break :blk err;
+    } else err;
+}
+
+test "tokenize.empty string" {
+    const tokens = try bounded_tokenize("");
+    try expectEqual(@as(usize, 0), tokens.len);
+}
+
+test "tokenize.whitespace" {
+    const tokens = try bounded_tokenize(" \t\r\n");
+    try expectEqual(@as(usize, 0), tokens.len);
+}
+
+test "tokenize.comma line comment" {
+    const tokens = try bounded_tokenize("; this is a line comment");
+
+    try expectEqual(@as(usize, 0), tokens.len);
+}
+
+test "tokenize.slash line comment" {
+    const tokens = try bounded_tokenize("// this is a line comment");
+
+    try expectEqual(@as(usize, 0), tokens.len);
+}
+
+test "tokenize.block comment" {
+    const tokens = try bounded_tokenize(
+        \\/* this is
+        \\   a block comment */
+    );
+
+    try expectEqual(@as(usize, 0), tokens.len);
+}
+
+test "tokenize.code block" {
+    const tokens = try bounded_tokenize(
+        \\% c-sdk {
+        \\   int foo;
+        \\%}
+    );
+
+    try expectEqual(@as(usize, 0), tokens.len);
+}
+
+test "tokenize.directive.program" {
+    const tokens = try bounded_tokenize(".program arst");
+    try expect_program("arst", tokens.get(0));
+}
+
+test "tokenize.directive.define" {
+    const tokens = try bounded_tokenize(".define symbol_name 1");
+
+    try expect_define(.{
+        .name = "symbol_name",
+        .value = .{ .expression = "1" },
+        .index = 8,
+    }, tokens.get(0));
+}
+
+test "tokenize.directive.define.public" {
+    const tokens = try bounded_tokenize(".define public symbol_name 0x1");
+
+    try expect_define(.{
+        .name = "symbol_name",
+        .value = .{ .expression = "0x1" },
+        .public = true,
+        .index = 15,
+    }, tokens.get(0));
+}
+
+test "tokenize.directive.define.with expression" {
+    const tokens = try bounded_tokenize(
+        \\.define symbol_name 0x1
+        \\.define something (symbol_name * 2)
+    );
+
+    try expect_define(.{
+        .name = "symbol_name",
+        .value = .{ .expression = "0x1" },
+        .index = 8,
+    }, tokens.get(0));
+
+    try expect_define(.{
+        .name = "something",
+        .value = .{ .expression = "(symbol_name * 2)" },
+        .index = 32,
+    }, tokens.get(1));
+}
+
+test "tokenize.directive.origin" {
+    const tokens = try bounded_tokenize(".origin 0x10");
+    try expect_origin(.{ .integer = 0x10 }, tokens.get(0));
+}
+
+test "tokenize.directive.side_set" {
+    const tokens = try bounded_tokenize(".side_set 1");
+    try expect_side_set(.{ .count = .{ .integer = 1 } }, tokens.get(0));
+}
+
+test "tokenize.directive.side_set.opt" {
+    const tokens = try bounded_tokenize(".side_set 1 opt");
+    try expect_side_set(.{ .count = .{ .integer = 1 }, .opt = true }, tokens.get(0));
+}
+
+test "tokenize.directive.side_set.pindirs" {
+    const tokens = try bounded_tokenize(".side_set 1 pindirs");
+    try expect_side_set(.{ .count = .{ .integer = 1 }, .pindirs = true }, tokens.get(0));
+}
+
+test "tokenize.directive.wrap_target" {
+    const tokens = try bounded_tokenize(".wrap_target");
+    try expect_wrap_target(tokens.get(0));
+}
+
+test "tokenize.directive.wrap" {
+    const tokens = try bounded_tokenize(".wrap");
+    try expect_wrap(tokens.get(0));
+}
+
+test "tokenize.directive.lang_opt" {
+    const tokens = try bounded_tokenize(".lang_opt c flag foo");
+    try expect_lang_opt(.{ .lang = "c", .name = "flag", .option = "foo" }, tokens.get(0));
+}
+
+test "tokenize.directive.word" {
+    const tokens = try bounded_tokenize(".word 0xaaaa");
+    try expect_word(.{ .integer = 0xaaaa }, tokens.get(0));
+}
+
+test "tokenize.label" {
+    const tokens = try bounded_tokenize("my_label:");
+    try expect_label(.{ .name = "my_label" }, tokens.get(0));
+}
+
+test "tokenize.label.public" {
+    const tokens = try bounded_tokenize("public my_label:");
+    try expect_label(.{ .name = "my_label", .public = true }, tokens.get(0));
+}
+
+test "tokenize.instr.nop" {
+    const tokens = try bounded_tokenize("nop");
+    try expect_instr_nop(.{}, tokens.get(0));
+}
+
+test "tokenize.instr.jmp.label" {
+    const tokens = try bounded_tokenize("jmp my_label");
+    try expect_instr_jmp(.{ .target = "my_label" }, tokens.get(0));
+}
+
+test "tokenize.instr.jmp.value" {
+    const tokens = try bounded_tokenize("jmp 0x2");
+    try expect_instr_jmp(.{ .target = "0x2" }, tokens.get(0));
+}
+
+test "tokenize.instr.jmp.conditions" {
+    const Condition = Token.Instruction.Jmp.Condition;
+    const cases = std.ComptimeStringMap(Condition, .{
+        .{ "!x", .x_is_zero },
+        .{ "x--", .x_dec },
+        .{ "!y", .y_is_zero },
+        .{ "y--", .y_dec },
+        .{ "x!=y", .x_is_not_y },
+        .{ "pin", .pin },
+        .{ "!osre", .osre_not_empty },
+    });
+
+    inline for (cases.kvs) |case| {
+        const op = case.key;
+        const cond = case.value;
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("jmp {s} my_label", .{op}));
+
+        try expect_instr_jmp(.{ .cond = cond, .target = "my_label" }, tokens.get(0));
+    }
+}
+
+test "tokenize.instr.wait" {
+    inline for (.{ "gpio", "pin", "irq" }) |source| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("wait 0 {s} 1", .{source}));
+        try expect_instr_wait(.{
+            .polarity = 0,
+            .source = @field(Token.Instruction.Wait.Source, source),
+            .num = .{ .integer = 1 },
+        }, tokens.get(0));
+    }
+}
+
+test "tokenize.instr.wait.irq.rel" {
+    const tokens = try bounded_tokenize("wait 1 irq 1 rel");
+    try expect_instr_wait(.{
+        .polarity = 1,
+        .source = .irq,
+        .num = .{ .integer = 1 },
+        .rel = true,
+    }, tokens.get(0));
+}
+
+test "tokenize.instr.in" {
+    inline for (.{
+        "pins",
+        "x",
+        "y",
+        "null",
+        "isr",
+        "osr",
+    }, 1..) |source, bit_count| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("in {s}, {}", .{
+            source,
+            bit_count,
+        }));
+
+        try expect_instr_in(.{
+            .source = @field(Token.Instruction.In.Source, source),
+            .bit_count = @intCast(u5, bit_count),
+        }, tokens.get(0));
+    }
+}
+
+test "tokenize.instr.out" {
+    inline for (.{
+        "pins",
+        "x",
+        "y",
+        "null",
+        "pindirs",
+        "pc",
+        "isr",
+        "exec",
+    }, 1..) |destination, bit_count| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("out {s}, {}", .{
+            destination,
+            bit_count,
+        }));
+
+        try expect_instr_out(.{
+            .destination = @field(Token.Instruction.Out.Destination, destination),
+            .bit_count = @intCast(u5, bit_count),
+        }, tokens.get(0));
+    }
+}
+
+test "tokenize.instr.push" {
+    const tokens = try bounded_tokenize("push");
+    try expect_instr_push(.{}, tokens.get(0));
+}
+
+test "tokenize.instr.push.block" {
+    const tokens = try bounded_tokenize("push block");
+    try expect_instr_push(.{
+        .block = true,
+    }, tokens.get(0));
+}
+
+test "tokenize.instr.push.noblock" {
+    const tokens = try bounded_tokenize("push noblock");
+    try expect_instr_push(.{
+        .block = false,
+    }, tokens.get(0));
+}
+
+test "tokenize.instr.push.iffull" {
+    const tokens = try bounded_tokenize("push iffull noblock");
+    try expect_instr_push(.{
+        .block = false,
+        .iffull = true,
+    }, tokens.get(0));
+}
+
+test "tokenize.instr.pull" {
+    const tokens = try bounded_tokenize("pull");
+    try expect_instr_pull(.{}, tokens.get(0));
+}
+
+test "tokenize.instr.pull.block" {
+    const tokens = try bounded_tokenize("pull block");
+    try expect_instr_pull(.{
+        .block = true,
+    }, tokens.get(0));
+}
+
+test "tokenize.instr.pull.noblock" {
+    const tokens = try bounded_tokenize("pull noblock");
+    try expect_instr_pull(.{
+        .block = false,
+    }, tokens.get(0));
+}
+
+test "tokenize.instr.pull.ifempty" {
+    const tokens = try bounded_tokenize("pull ifempty noblock");
+    try expect_instr_pull(.{
+        .block = false,
+        .ifempty = true,
+    }, tokens.get(0));
+}
+
+test "tokenize.instr.mov" {
+    inline for (.{
+        "pins",
+        "x",
+        "y",
+        "null",
+        "status",
+        "isr",
+        "osr",
+    }) |source| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("mov x {s}", .{source}));
+
+        try expect_instr_mov(.{
+            .source = @field(Token.Instruction.Mov.Source, source),
+            .destination = .x,
+        }, tokens.get(0));
+    }
+
+    inline for (.{
+        "pins",
+        "x",
+        "y",
+        "exec",
+        "pc",
+        "isr",
+        "osr",
+    }) |dest| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("mov {s} x", .{dest}));
+
+        try expect_instr_mov(.{
+            .source = .x,
+            .destination = @field(Token.Instruction.Mov.Destination, dest),
+        }, tokens.get(0));
+    }
+
+    const Operation = Token.Instruction.Mov.Operation;
+    const operations = std.ComptimeStringMap(Operation, .{
+        .{ "!", .invert },
+        .{ "~", .invert },
+        .{ "::", .bit_reverse },
+    });
+
+    inline for (.{ "", " " }) |space| {
+        inline for (operations.kvs) |kv| {
+            const str = kv.key;
+            const operation = kv.value;
+            const tokens = try bounded_tokenize(std.fmt.comptimePrint("mov x {s}{s}y", .{
+                str,
+                space,
+            }));
+
+            try expect_instr_mov(.{
+                .destination = .x,
+                .operation = operation,
+                .source = .y,
+            }, tokens.get(0));
+        }
+    }
+}
+
+test "tokenize.instr.irq" {
+    const ClearWait = struct {
+        clear: bool,
+        wait: bool,
+    };
+
+    const modes = std.ComptimeStringMap(ClearWait, .{
+        .{ "", .{ .clear = false, .wait = false } },
+        .{ "set", .{ .clear = false, .wait = false } },
+        .{ "nowait", .{ .clear = false, .wait = false } },
+        .{ "wait", .{ .clear = false, .wait = true } },
+        .{ "clear", .{ .clear = true, .wait = false } },
+    });
+
+    inline for (modes.kvs, 0..) |kv, num| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("irq {s} {}", .{
+            kv.key,
+            num,
+        }));
+
+        try expect_instr_irq(.{
+            .clear = kv.value.clear,
+            .wait = kv.value.wait,
+            .num = num,
+        }, tokens.get(0));
+    }
+}
+
+test "tokenize.instr.irq.rel" {
+    const tokens = try bounded_tokenize("irq set 2 rel");
+    try expect_instr_irq(.{
+        .clear = false,
+        .wait = false,
+        .num = 2,
+        .rel = true,
+    }, tokens.get(0));
+}
+
+test "tokenize.instr.set" {
+    inline for (.{
+        "pins",
+        "x",
+        "y",
+        "pindirs",
+    }) |dest| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("set {s}, 2", .{dest}));
+        try expect_instr_set(.{
+            .dest = @field(Token.Instruction.Set.Destination, dest),
+            .value = .{ .integer = 2 },
+        }, tokens.get(0));
+    }
+}
+
+test "tokenize.instr.set.with expression including define" {
+    const tokens = try bounded_tokenize("set X, (NUM_CYCLES - 1)         ; initialise the loop counter");
+    try expect_instr_set(.{
+        .dest = .x,
+        .value = .{ .expression = "(NUM_CYCLES - 1)" },
+    }, tokens.get(0));
+}
+
+const instruction_examples = .{
+    "nop",
+    "jmp arst",
+    "wait 0 gpio 1",
+    "in pins, 2",
+    "out pc, 1",
+    "push",
+    "pull",
+    "mov x y",
+    "irq 1",
+    "set pins 2",
+};
+
+test "tokenize.instr.label prefixed" {
+    inline for (instruction_examples) |instr| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("my_label: {s}", .{instr}));
+        try expectEqual(@as(usize, 2), tokens.len);
+        try expect_label(.{ .name = "my_label" }, tokens.get(0));
+    }
+}
+
+test "tokenize.instr.side_set" {
+    inline for (instruction_examples) |instr| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} side 0", .{instr}));
+        const token = tokens.get(0);
+        try expect_value(.{
+            .expression = "0",
+        }, token.data.instruction.side_set.?);
+        try expectEqual(@as(?Value, null), token.data.instruction.delay);
+    }
+}
+
+test "tokenize.instr.delay" {
+    inline for (instruction_examples) |instr| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} [1]", .{instr}));
+        const token = tokens.get(0);
+        try expectEqual(@as(?Value, null), token.data.instruction.side_set);
+        try expect_value(.{
+            .expression = "1",
+        }, token.data.instruction.delay.?);
+    }
+}
+
+test "tokenize.instr.delay.expression" {
+    inline for (instruction_examples) |instr| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} [T-1]", .{instr}));
+        const token = tokens.get(0);
+        try expectEqual(@as(?Value, null), token.data.instruction.side_set);
+        try expect_value(.{
+            .expression = "T-1",
+        }, token.data.instruction.delay.?);
+    }
+}
+
+test "tokenize.instr.side_set.expression" {
+    inline for (instruction_examples) |instr| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} side (N-1)", .{instr}));
+        const token = tokens.get(0);
+        try expect_value(.{
+            .expression = "(N-1)",
+        }, token.data.instruction.side_set.?);
+        try expectEqual(@as(?Value, null), token.data.instruction.delay);
+    }
+}
+
+test "tokenize.instr.side_set and delay" {
+    inline for (instruction_examples) |instr| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} side 1 [2]", .{instr}));
+        const token = tokens.get(0);
+        try expect_value(.{
+            .expression = "1",
+        }, token.data.instruction.side_set.?);
+        try expect_value(.{
+            .expression = "2",
+        }, token.data.instruction.delay.?);
+    }
+}
+
+test "tokenize.instr.side_set and delay reversed" {
+    inline for (instruction_examples) |instr| {
+        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} [2] side 1", .{instr}));
+        const token = tokens.get(0);
+        try expect_value(.{
+            .expression = "1",
+        }, token.data.instruction.side_set.?);
+        try expect_value(.{
+            .expression = "2",
+        }, token.data.instruction.delay.?);
+    }
+}
+
+test "tokenize.instr.comment with no whitespace" {
+    const tokens = try bounded_tokenize("nop side 0x0 [1]; CSn front porch");
+    try expect_instr_nop(.{
+        .side_set = .{ .expression = "0x0" },
+        .delay = .{ .expression = "1" },
+    }, tokens.get(0));
+}

From 08779dfe02e3edab69126b6a96b1742049f6987a Mon Sep 17 00:00:00 2001
From: Vlad Panazan 
Date: Tue, 11 Apr 2023 07:43:12 +0300
Subject: [PATCH 115/286] Add SPI read function (#38)

---
 deps/microzig    |  2 +-
 src/hal/pins.zig |  2 +-
 src/hal/spi.zig  | 43 ++++++++++++++++++++++++++++++++++---------
 3 files changed, 36 insertions(+), 11 deletions(-)

diff --git a/deps/microzig b/deps/microzig
index dabc9325c..ceaa9ddcb 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dabc9325cdee394ff66e28c91803cb814954b157
+Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e
diff --git a/src/hal/pins.zig b/src/hal/pins.zig
index 7a204b8d2..3ff924638 100644
--- a/src/hal/pins.zig
+++ b/src/hal/pins.zig
@@ -520,7 +520,7 @@ pub const GlobalConfiguration = struct {
                 if (@field(config, field.name)) |pin_config| {
                     const gpio_num = @enumToInt(@field(Pin, field.name));
                     const pull = pin_config.pull orelse continue;
-                    if (comptime pin_config.getDirection() != .in)
+                    if (comptime pin_config.get_direction() != .in)
                         @compileError("Only input pins can have pull up/down enabled");
 
                     gpio.set_pull(gpio_num, pull);
diff --git a/src/hal/spi.zig b/src/hal/spi.zig
index ea96f4099..002ccc4d7 100644
--- a/src/hal/spi.zig
+++ b/src/hal/spi.zig
@@ -8,6 +8,7 @@ const gpio = @import("gpio.zig");
 const clocks = @import("clocks.zig");
 const resets = @import("resets.zig");
 const time = @import("time.zig");
+const util = @import("util.zig");
 
 const SpiRegs = microzig.chip.types.peripherals.SPI0;
 
@@ -78,11 +79,11 @@ pub const SPI = enum {
         return spi;
     }
 
-    pub fn is_writable(spi: SPI) bool {
+    pub inline fn is_writable(spi: SPI) bool {
         return spi.get_regs().SSPSR.read().TNF == 1;
     }
 
-    pub fn is_readable(spi: SPI) bool {
+    pub inline fn is_readable(spi: SPI) bool {
         return spi.get_regs().SSPSR.read().RNE == 1;
     }
     pub fn transceive(spi: SPI, src: []const u8, dst: []u8) usize {
@@ -106,7 +107,7 @@ pub const SPI = enum {
 
         return src.len;
     }
-    // Write len bytes directly from src to the SPI, and discard any data received back
+    /// Write len bytes directly from src to the SPI, and discard any data received back
     pub fn write(spi: SPI, src: []const u8) usize {
         const spi_regs = spi.get_regs();
         // Write to TX FIFO whilst ignoring RX, then clean up afterward. When RX
@@ -114,26 +115,50 @@ pub const SPI = enum {
         // push-on-full, but continues shifting. Safe if SSPIMSC_RORIM is not set.
         for (src) |s| {
             while (!spi.is_writable()) {
-                std.log.debug("SPI not writable!", .{});
+                util.tight_loop_contents();
             }
             spi_regs.SSPDR.write_raw(s);
         }
         // Drain RX FIFO, then wait for shifting to finish (which may be *after*
         // TX FIFO drains), then drain RX FIFO again
         while (spi.is_readable()) {
-            _ = spi_regs.SSPDR.raw;
+            _ = spi_regs.SSPDR.read();
         }
-        while (spi.get_regs().SSPSR.read().BSY == 1) {
-            std.log.debug("SPI busy!", .{});
+        while (spi_regs.SSPSR.read().BSY == 1) {
+            util.tight_loop_contents();
         }
         while (spi.is_readable()) {
-            _ = spi_regs.SSPDR.raw;
+            _ = spi_regs.SSPDR.read();
         }
         // Don't leave overrun flag set
         peripherals.SPI0.SSPICR.modify(.{ .RORIC = 1 });
         return src.len;
     }
 
+    /// Read len bytes directly from the SPI to dst.
+    /// repeated_tx_data is output repeatedly on SO as data is read in from SI.
+    /// Generally this can be 0, but some devices require a specific value here,
+    /// e.g. SD cards expect 0xff
+    pub fn read(spi: SPI, repeated_tx_data: u8, dst: []u8) usize {
+        const spi_regs = spi.get_regs();
+        const fifo_depth = 8;
+        var rx_remaining = dst.len;
+        var tx_remaining = dst.len;
+
+        while (rx_remaining > 0 or tx_remaining > 0) {
+            if (tx_remaining > 0 and spi.is_writable() and rx_remaining < tx_remaining + fifo_depth) {
+                spi_regs.SSPDR.write_raw(repeated_tx_data);
+                tx_remaining -= 1;
+            }
+            if (rx_remaining > 0 and spi.is_readable()) {
+                const bytes = std.mem.asBytes(&spi_regs.SSPDR.read().DATA);
+                dst[dst.len - rx_remaining] = bytes[0];
+                rx_remaining -= 1;
+            }
+        }
+        return dst.len;
+    }
+
     fn set_baudrate(spi: SPI, baudrate: u32, freq_in: u32) u64 {
         const spi_regs = spi.get_regs();
         // Find smallest prescale value which puts output frequency in range of
@@ -143,9 +168,9 @@ pub const SPI = enum {
             if (freq_in < (prescale + 2) * 256 * baudrate) break;
         }
         std.debug.assert(prescale <= 254); //Freq too low
+
         // Find largest post-divide which makes output <= baudrate. Post-divide is
         // an integer in the range 1 to 256 inclusive.
-
         var postdiv: u64 = 256;
         while (postdiv > 1) : (postdiv -= 1) {
             if (freq_in / (prescale * (postdiv - 1)) > baudrate) break;

From ed60b5f2e72c8dc267c151e4fa73e1d9effb5ff6 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 12 Apr 2023 23:50:03 -0700
Subject: [PATCH 116/286] Pio updates (#41)

* program loading API

* build examples in CI

* build fixes
---
 .buildkite/pipeline.yml   |   5 +-
 build.zig                 |  13 +-
 examples/squarewave.zig   |  19 +-
 src/hal/pio.zig           | 512 ++++++++++++++++++++++++--------------
 src/hal/pio/assembler.zig |   4 +-
 5 files changed, 353 insertions(+), 200 deletions(-)

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
index 50f730f18..4e00ec296 100644
--- a/.buildkite/pipeline.yml
+++ b/.buildkite/pipeline.yml
@@ -1,2 +1,5 @@
 steps:
-  - command: zig build test
+  - name: Build Examples
+    command: zig build
+  - name: Test
+    command: zig build test
diff --git a/build.zig b/build.zig
index 21a91ff64..f9d372944 100644
--- a/build.zig
+++ b/build.zig
@@ -39,8 +39,8 @@ pub fn addPiPicoExecutable(
 // project requires multiple HALs, it accepts microzig as a param
 pub fn build(b: *Builder) !void {
     const optimize = b.standardOptimizeOption(.{});
-    //var examples = Examples.init(b, optimize);
-    //examples.install();
+    var examples = Examples.init(b, optimize);
+    examples.install(b);
 
     const pio_tests = b.addTest(.{
         .root_source_file = .{
@@ -51,7 +51,7 @@ pub fn build(b: *Builder) !void {
     pio_tests.addIncludePath("src/hal/pio/assembler");
 
     const test_step = b.step("test", "run unit tests");
-    test_step.dependOn(&pio_tests.run().step);
+    test_step.dependOn(&b.addRunArtifact(pio_tests).step);
 }
 
 fn root() []const u8 {
@@ -85,8 +85,9 @@ pub const Examples = struct {
         return ret;
     }
 
-    pub fn install(examples: *Examples) void {
-        inline for (@typeInfo(Examples).Struct.fields) |field|
-            @field(examples, field.name).install();
+    pub fn install(examples: *Examples, b: *Builder) void {
+        inline for (@typeInfo(Examples).Struct.fields) |field| {
+            b.installArtifact(@field(examples, field.name).inner);
+        }
     }
 };
diff --git a/examples/squarewave.zig b/examples/squarewave.zig
index b320681ed..74370003c 100644
--- a/examples/squarewave.zig
+++ b/examples/squarewave.zig
@@ -13,11 +13,12 @@ const squarewave_program = (rp2040.pio.assemble(
     \\    set pins, 1 [1]  ; Drive pin high and then delay for one cycle
     \\    set pins, 0      ; Drive pin low
     \\    jmp again        ; Set PC to label `again`
-) catch
+, .{}) catch
     @panic("failed to assemble program"))
     .get_program_by_name("squarewave");
 
 pub fn main() void {
+    gpio.reset();
     // Pick one PIO instance arbitrarily. We're also arbitrarily picking state
     // machine 0 on this PIO instance (the state machines are numbered 0 to 3
     // inclusive).
@@ -35,19 +36,27 @@ pub fn main() void {
     // speed down uniformly to meet some precise frequency target, e.g. for a
     // UART baud rate. This register has 16 integer divisor bits and 8
     // fractional divisor bits.
-    pio.set_clkdiv_int_frac(sm, 2, 0x80);
+    pio.sm_set_clkdiv(sm, .{
+        .int = 2,
+        .frac = 0x80,
+    });
 
     // There are five pin mapping groups (out, in, set, side-set, jmp pin)
     // which are used by different instructions or in different circumstances.
     // Here we're just using SET instructions. Configure state machine 0 SETs
     // to affect GPIO 0 only; then configure GPIO0 to be controlled by PIO0,
     // as opposed to e.g. the processors.
-    pio.set_out_pins(sm, 0, 1);
-    gpio.set_function(0, .pio0);
+    pio.gpio_init(0);
+    pio.sm_set_pin_mappings(sm, .{
+        .out = .{
+            .base = 0,
+            .count = 1,
+        },
+    });
 
     // Set the state machine running. The PIO CTRL register is global within a
     // PIO instance, so you can start/stop multiple state machines
     // simultaneously. We're using the register's hardware atomic set alias to
     // make one bit high without doing a read-modify-write on the register.
-    pio.set_enabled(sm, true);
+    pio.sm_set_enabled(sm, true);
 }
diff --git a/src/hal/pio.zig b/src/hal/pio.zig
index e37d713d9..22dc5a304 100644
--- a/src/hal/pio.zig
+++ b/src/hal/pio.zig
@@ -1,5 +1,6 @@
 //! A PIO instance can load a single `Bytecode`, it has to be loaded into memory
 const std = @import("std");
+const assert = std.debug.assert;
 
 const microzig = @import("microzig");
 const PIO = microzig.chip.types.peripherals.PIO0;
@@ -8,26 +9,19 @@ const PIO1 = microzig.chip.peripherals.PIO1;
 
 const gpio = @import("gpio.zig");
 const assembler = @import("pio/assembler.zig");
-pub const Bytecode = Bytecode;
-pub const Program = assembler.Program;
-pub const assemble = assembler.assemble;
+const encoder = @import("pio/assembler/encoder.zig");
 
+// global state for keeping track of used things
 var used_instruction_space: [2]u32 = [_]u32{ 0, 0 };
 var claimed_state_machines: [2]u4 = [_]u4{ 0, 0 };
 
-pub const Join = enum {
-    none,
-    rx,
-    tx,
-};
-
-pub const Status = enum {
-    rx_lessthan,
-    tx_lessthan,
-};
+pub const Instruction = encoder.Instruction;
+pub const Program = assembler.Program;
+pub const assemble = assembler.assemble;
 
-pub const Configuration = struct {
-    pin: u32,
+pub const Fifo = enum {
+    tx,
+    rx,
 };
 
 pub const StateMachine = enum(u2) {
@@ -37,6 +31,97 @@ pub const StateMachine = enum(u2) {
     sm3,
 };
 
+pub const Irq = enum {
+    irq0,
+    irq1,
+
+    pub const Regs = extern struct {
+        enable: @TypeOf(PIO0.IRQ0_INTE),
+        force: @TypeOf(PIO0.IRQ0_INTF),
+        status: @TypeOf(PIO0.IRQ0_INTS),
+    };
+
+    pub const Source = enum {
+        rx_not_empty,
+        tx_not_full,
+        // TODO: determine what this does, is it just a combination of the
+        // first two, or is it other things?
+        statemachine,
+    };
+};
+
+pub const StateMachineRegs = extern struct {
+    clkdiv: @TypeOf(PIO0.SM0_CLKDIV),
+    execctrl: @TypeOf(PIO0.SM0_EXECCTRL),
+    shiftctrl: @TypeOf(PIO0.SM0_SHIFTCTRL),
+    addr: @TypeOf(PIO0.SM0_ADDR),
+    instr: @TypeOf(PIO0.SM0_INSTR),
+    pinctrl: @TypeOf(PIO0.SM0_PINCTRL),
+};
+
+pub const ClkDivOptions = struct {
+    int: u16,
+    frac: u8,
+
+    pub fn from_float(div: f32) ClkDivOptions {
+        const fixed = @floatToInt(u24, div * 256);
+        return ClkDivOptions{
+            .int = @truncate(u16, fixed >> 8),
+            .frac = @truncate(u8, fixed),
+        };
+    }
+};
+
+pub const ExecOptions = struct {
+    wrap: u5,
+    wrap_target: u5,
+    side_pindir: bool,
+    side_set_optional: bool,
+};
+
+pub const ShiftOptions = struct {
+    autopush: bool = false,
+    autopull: bool = false,
+    in_shiftdir: Direction = .left,
+    out_shiftdir: Direction = .left,
+    push_threshold: u5 = 0,
+    pull_threshold: u5 = 0,
+    join_tx: bool = false,
+    join_rx: bool = false,
+
+    pub const Direction = enum(u1) {
+        left,
+        right,
+    };
+};
+
+pub fn PinMapping(comptime Count: type) type {
+    return struct {
+        base: u5 = 0,
+        count: Count = 0,
+    };
+}
+
+pub const PinMappingOptions = struct {
+    out: PinMapping(u6) = .{},
+    set: PinMapping(u3) = .{},
+    side_set: PinMapping(u3) = .{},
+    in_base: u5 = 0,
+};
+
+pub const StateMachineInitOptions = struct {
+    clkdiv: ClkDivOptions,
+    exec: ExecOptions,
+    shift: ShiftOptions = .{},
+    pin_mappings: PinMappingOptions = .{},
+};
+
+pub const LoadAndStartProgramOptions = struct {
+    clkdiv: ClkDivOptions,
+    shift: ShiftOptions = .{},
+    pin_mappings: PinMappingOptions = .{},
+};
+
 pub const Pio = enum(u1) {
     pio0 = 0,
     pio1 = 1,
@@ -60,11 +145,6 @@ pub const Pio = enum(u1) {
         });
     }
 
-    pub fn load(self: Pio, bytecode: Bytecode) !void {
-        _ = self;
-        _ = bytecode;
-    }
-
     fn can_add_program_at_offset(self: Pio, program: Program, offset: u5) bool {
         if (program.origin) |origin|
             if (origin != offset)
@@ -84,9 +164,10 @@ pub const Pio = enum(u1) {
                 origin
             else
                 error.NoSpace
-        else for (0..32 - program.isntruction.len) |i| {
-            if (self.can_add_program_at_offset(program, i))
-                break i;
+        else for (0..(32 - program.instructions.len)) |i| {
+            const offset = @intCast(u5, i);
+            if (self.can_add_program_at_offset(program, offset))
+                break offset;
         } else error.NoSpace;
     }
 
@@ -103,12 +184,13 @@ pub const Pio = enum(u1) {
     }
 
     /// Public functions will need to lock independently, so only exposing this function for now
-    pub fn add_program(self: Pio, program: Program) !void {
-        // TODO: const lock = hw.Lock.claim()
-        // defer lock.unlock();
+    pub fn add_program(self: Pio, program: Program) !u5 {
+        //const lock = hw.Lock.claim();
+        //defer lock.unlock();
 
-        const offset = try self.find_offset_for_program_unlocked();
-        try self.add_program_at_offset(program, offset);
+        const offset = try self.find_offset_for_program(program);
+        try self.add_program_at_offset_unlocked(program, offset);
+        return offset;
     }
 
     pub fn claim_unused_state_machine(self: Pio) !StateMachine {
@@ -125,15 +207,6 @@ pub const Pio = enum(u1) {
         } else error.NoSpace;
     }
 
-    pub const StateMachineRegs = extern struct {
-        clkdiv: @TypeOf(PIO0.SM0_CLKDIV),
-        execctrl: @TypeOf(PIO0.SM0_EXECCTRL),
-        shiftctrl: @TypeOf(PIO0.SM0_SHIFTCTRL),
-        addr: @TypeOf(PIO0.SM0_ADDR),
-        instr: @TypeOf(PIO0.SM0_INSTR),
-        pinctrl: @TypeOf(PIO0.SM0_PINCTRL),
-    };
-
     fn get_sm_regs(self: Pio, sm: StateMachine) *volatile StateMachineRegs {
         const pio_regs = self.get_regs();
         return switch (sm) {
@@ -144,71 +217,88 @@ pub const Pio = enum(u1) {
         };
     }
 
-    pub fn join_fifo(self: Pio, sm: StateMachine, join: Join) void {
-        const tx: u1 = switch (join) {
-            .tx => 1,
-            .rx => 0,
-            .none => 0,
-        };
-        const rx: u1 = switch (join) {
-            .tx => 0,
-            .rx => 1,
-            .none => 0,
+    fn get_irq_regs(self: Pio, irq: Irq) *volatile Irq.Regs {
+        const pio_regs = self.get_regs();
+        return switch (irq) {
+            .irq0 => @ptrCast(*volatile Irq.Regs, &pio_regs.IRQ0_INTE),
+            .irq1 => @ptrCast(*volatile Irq.Regs, &pio_regs.IRQ1_INTE),
         };
-
-        const sm_regs = self.get_sm_regs(sm);
-        sm_regs.shiftctrl.modify(.{
-            .FJOIN_TX = tx,
-            .FJOIN_RX = rx,
-        });
     }
 
-    pub fn set_clkdiv_int_frac(self: Pio, sm: StateMachine, div_int: u16, div_frac: u8) void {
-        if (div_int == 0 and div_frac != 0)
+    pub inline fn sm_set_clkdiv(self: Pio, sm: StateMachine, options: ClkDivOptions) void {
+        if (options.int == 0 and options.frac != 0)
             @panic("invalid params");
 
         const sm_regs = self.get_sm_regs(sm);
         sm_regs.clkdiv.write(.{
-            .INT = div_int,
-            .FRAC = div_frac,
+            .INT = options.int,
+            .FRAC = options.frac,
 
             .reserved8 = 0,
         });
     }
 
-    pub fn set_out_shift(self: Pio, sm: StateMachine, args: struct {
-        shift_right: bool,
-        autopull: bool,
-        pull_threshold: u5,
-    }) void {
+    pub inline fn sm_set_exec_options(self: Pio, sm: StateMachine, options: ExecOptions) void {
         const sm_regs = self.get_sm_regs(sm);
-        sm_regs.shiftctrl.modify(.{
-            .OUT_SHIFTDIR = @boolToInt(args.shift_right),
-            .AUTOPULL = @boolToInt(args.autopull),
-            .PULL_THRESH = args.pull_threshold,
+        sm_regs.execctrl.modify(.{
+            .WRAP_BOTTOM = options.wrap_target,
+            .WRAP_TOP = options.wrap,
+            .SIDE_PINDIR = @boolToInt(options.side_pindir),
+            .SIDE_EN = @boolToInt(options.side_set_optional),
+
+            // TODO: plug in rest of the options
+            // STATUS_N
+            // STATUS_SEL
+            // OUT_STICKY
+            // INLINE_OUT_EN
+            // OUT_EN_SEL
+            // JMP_PIN
+            // EXEC_STALLED
         });
     }
 
-    pub fn set_out_pins(self: Pio, sm: StateMachine, base: u5, count: u5) void {
+    pub inline fn sm_set_shift_options(self: Pio, sm: StateMachine, options: ShiftOptions) void {
         const sm_regs = self.get_sm_regs(sm);
-        sm_regs.pinctrl.modify(.{
-            .OUT_BASE = base,
-            .OUT_COUNT = count,
+        sm_regs.shiftctrl.write(.{
+            .AUTOPUSH = @boolToInt(options.autopush),
+            .AUTOPULL = @boolToInt(options.autopush),
+
+            .IN_SHIFTDIR = @enumToInt(options.in_shiftdir),
+            .OUT_SHIFTDIR = @enumToInt(options.out_shiftdir),
+
+            .PUSH_THRESH = options.push_threshold,
+            .PULL_THRESH = options.pull_threshold,
+
+            .FJOIN_TX = @boolToInt(options.join_tx),
+            .FJOIN_RX = @boolToInt(options.join_rx),
+
+            .reserved16 = 0,
         });
     }
 
-    pub fn set_sideset_pins(self: Pio, sm: StateMachine, base: u5) void {
+    pub inline fn sm_set_pin_mappings(self: Pio, sm: StateMachine, options: PinMappingOptions) void {
         const sm_regs = self.get_sm_regs(sm);
-        sm_regs.pinctrl.modify(.{ .SIDESET_BASE = base });
+        sm_regs.pinctrl.modify(.{
+            .OUT_BASE = options.out.base,
+            .OUT_COUNT = options.out.count,
+
+            .SET_BASE = options.set.base,
+            .SET_COUNT = options.set.count,
+
+            .SIDESET_BASE = options.side_set.base,
+            .SIDESET_COUNT = options.side_set.count,
+
+            .IN_BASE = options.in_base,
+        });
     }
 
-    pub fn is_tx_fifo_full(self: Pio, sm: StateMachine) bool {
+    pub inline fn sm_is_tx_fifo_full(self: Pio, sm: StateMachine) bool {
         const regs = self.get_regs();
         const txfull = regs.FSTAT.read().TXFULL;
         return (txfull & (@as(u4, 1) << @enumToInt(sm))) != 0;
     }
 
-    pub fn get_tx_fifo(self: Pio, sm: StateMachine) *volatile u32 {
+    pub inline fn sm_get_tx_fifo(self: Pio, sm: StateMachine) *volatile u32 {
         const regs = self.get_regs();
         return switch (sm) {
             .sm0 => ®s.TXF0,
@@ -218,33 +308,14 @@ pub const Pio = enum(u1) {
         };
     }
 
-    pub fn blocking_write(self: Pio, sm: StateMachine, value: u32) void {
-        while (self.is_tx_fifo_full(sm)) {}
+    pub inline fn sm_blocking_write(self: Pio, sm: StateMachine, value: u32) void {
+        while (self.sm_is_tx_fifo_full(sm)) {}
 
-        const fifo_ptr = self.get_tx_fifo(sm);
+        const fifo_ptr = self.sm_get_tx_fifo(sm);
         fifo_ptr.* = value;
     }
 
-    pub fn encode_jmp() void {}
-
-    //static inline uint _pio_encode_instr_and_args(enum pio_instr_bits instr_bits, uint arg1, uint arg2) {
-    //    valid_params_if(PIO_INSTRUCTIONS, arg1 <= 0x7);
-    //#if PARAM_ASSERTIONS_ENABLED(PIO_INSTRUCTIONS)
-    //    uint32_t major = _pio_major_instr_bits(instr_bits);
-    //    if (major == pio_instr_bits_in || major == pio_instr_bits_out) {
-    //        assert(arg2 && arg2 <= 32);
-    //    } else {
-    //        assert(arg2 <= 31);
-    //    }
-    //#endif
-    //    return instr_bits | (arg1 << 5u) | (arg2 & 0x1fu);
-    //}
-    //
-    //static inline uint pio_encode_jmp(uint addr) {
-    //    return _pio_encode_instr_and_args(pio_instr_bits_jmp, 0, addr);
-    //}
-
-    pub fn set_enabled(self: Pio, sm: StateMachine, enabled: bool) void {
+    pub inline fn sm_set_enabled(self: Pio, sm: StateMachine, enabled: bool) void {
         const regs = self.get_regs();
 
         var value = regs.CTRL.read();
@@ -256,103 +327,172 @@ pub const Pio = enum(u1) {
         regs.CTRL.write(value);
     }
 
-    pub fn sm_init(self: Pio, sm: StateMachine, initial_pc: u5, config: StateMachineRegs) void {
-        // Halt the machine, set some sensible defaults
-        self.set_enabled(sm, false);
+    inline fn sm_clear_debug(self: Pio, sm: StateMachine) void {
+        const regs = self.get_regs();
+        const mask: u4 = (@as(u4, 1) << @enumToInt(sm));
+
+        // write 1 to clear this register
+        regs.FDEBUG.modify(.{
+            .RXSTALL = mask,
+            .RXUNDER = mask,
+            .TXOVER = mask,
+            .TXSTALL = mask,
+        });
+    }
+
+    /// changing the state of fifos will clear them
+    pub fn sm_clear_fifos(self: Pio, sm: StateMachine) void {
+        const sm_regs = self.get_sm_regs(sm);
+        var shiftctrl = sm_regs.shiftctrl.read();
+        shiftctrl.FJOIN_TX ^= 1;
+        shiftctrl.FJOIN_RX ^= 1;
+        sm_regs.shiftctrl.write(shiftctrl);
+    }
+
+    pub fn sm_fifo_level(self: Pio, sm: StateMachine, fifo: Fifo) u4 {
+        const num = @enumToInt(sm);
+        const offset: u5 = switch (fifo) {
+            .tx => 0,
+            .rx => 4,
+        };
+
+        const regs = self.get_regs();
+        const levels = regs.FLEVEL.raw;
 
-        self.set_config(sm, config);
-        self.clear_fifos(sm);
+        return @truncate(u4, levels >> (@as(u5, 4) * num) + offset);
+    }
 
-        // Clear FIFO debug flags
-        //const uint32_t fdebug_sm_mask =
-        //        (1u << PIO_FDEBUG_TXOVER_LSB) |
-        //        (1u << PIO_FDEBUG_RXUNDER_LSB) |
-        //        (1u << PIO_FDEBUG_TXSTALL_LSB) |
-        //        (1u << PIO_FDEBUG_RXSTALL_LSB);
-        //pio->fdebug = fdebug_sm_mask << sm;
+    inline fn interrupt_bit_pos(
+        sm: StateMachine,
+        source: Irq.Source,
+    ) u5 {
+        return (@as(u5, 4) * @enumToInt(source)) + @enumToInt(sm);
+    }
+
+    pub inline fn sm_clear_interrupt(
+        self: Pio,
+        sm: StateMachine,
+        irq: Irq,
+        source: Irq.Source,
+    ) void {
+        // TODO: why does the raw interrupt register no have irq1/0?
+        _ = irq;
+        const regs = self.get_regs();
+        regs.INTR.raw &= ~(@as(u32, 1) << interrupt_bit_pos(sm, source));
+    }
+
+    // TODO: be able to disable an interrupt
+    pub inline fn sm_enable_interrupt(
+        self: Pio,
+        sm: StateMachine,
+        irq: Irq,
+        source: Irq.Source,
+    ) void {
+        const irq_regs = self.get_irq_regs(irq);
+        irq_regs.enable.raw |= @as(u32, 1) << interrupt_bit_pos(sm, source);
+    }
+
+    pub inline fn sm_restart(self: Pio, sm: StateMachine) void {
+        const mask: u4 = (@as(u4, 1) << @enumToInt(sm));
+        const regs = self.get_regs();
+        regs.CTRL.modify(.{
+            .SM_RESTART = mask,
+        });
+    }
+
+    pub inline fn sm_clkdiv_restart(self: Pio, sm: StateMachine) void {
+        const mask: u4 = (@as(u4, 1) << @enumToInt(sm));
+        const regs = self.get_regs();
+        regs.CTRL.modify(.{
+            .CLKDIV_RESTART = mask,
+        });
+    }
+
+    pub fn sm_init(
+        self: Pio,
+        sm: StateMachine,
+        initial_pc: u5,
+        options: StateMachineInitOptions,
+    ) void {
+        // Halt the machine, set some sensible defaults
+        self.sm_set_enabled(sm, false);
+        self.sm_set_pin_mappings(sm, options.pin_mappings);
+        self.sm_set_clkdiv(sm, options.clkdiv);
+        self.sm_set_exec_options(sm, options.exec);
+        self.sm_set_shift_options(sm, options.shift);
+
+        //self.set_config(sm, config);
+        self.sm_clear_fifos(sm);
+        self.sm_clear_debug(sm);
 
         // Finally, clear some internal SM state
-        self.restart(sm);
-        self.clkdiv_restart(sm);
-        self.exec(sm, encode_jmp(initial_pc));
+        self.sm_restart(sm);
+        self.sm_clkdiv_restart(sm);
+        self.sm_exec(sm, Instruction{
+            .tag = .jmp,
+
+            .delay_side_set = 0,
+            .payload = .{
+                .jmp = .{
+                    .address = initial_pc,
+                    .condition = .always,
+                },
+            },
+        });
+    }
+
+    pub fn sm_exec(self: Pio, sm: StateMachine, instruction: Instruction) void {
+        const sm_regs = self.get_sm_regs(sm);
+        sm_regs.instr.raw = @bitCast(u16, instruction);
     }
 
-    // state machine configuration helpers:
-    //
-    // - set_out_pins
-    // - set_set_pins
-    // - set_in_pins
-    // - set_sideset_pins
-    // - set_sideset
-    // - calculate_clkdiv_from_float
-    // - set_clkdiv
-    // - set_wrap
-    // - set_jmp_pin
-    // - set_in_shift
-    // - set_out_shift
-    // - set_fifo_join
-    // - set_out_special
-    // - set_mov_status
-    //
-    // PIO:
-    //
-    // - can_add_program
-    // - add_program_at_offset
-    // - add_program
-    // - remove_program
-    // - clear_instruction_memory
-    // - sm_init
-    // - sm_set_enabled
-    // - sm_mask_enabled
-    // - sm_restart
-    // - restart_sm_mask
-    // - sm_clkdiv_restart
-    // - clkdiv_restart_sm_mask
-    // - enable_sm_mask_in_sync
-    // - set_irq0_source_enabled
-    // - set_irq1_source_enabled
-    // - set_irq0_source_mask_enabled
-    // - set_irq1_source_mask_enabled
-    // - set_irqn_source_enabled
-    // - set_irqn_source_mask_enabled
-    // - interrupt_get
-    // - interrupt_clear
-    // - sm_get_pc
-    // - sm_exec
-    // - sm_is_exec_stalled
-    // - sm_exec_wait_blocking
-    // - sm_set_wrap
-    // - sm_set_out_pins
-    // - sm_set_set_pins
-    // - sm_set_in_pins
-    // - sm_set_sideset_pins
-    // - sm_put
-    // - sm_get
-    // - sm_is_rx_fifo_full
-    // - sm_is_rx_fifo_empty
-    // - sm_is_rx_fifo_level
-    // - sm_is_tx_fifo_full
-    // - sm_is_tx_fifo_empty
-    // - sm_is_tx_fifo_level
-    // - sm_put_blocking
-    // - sm_get_blocking
-    // - sm_drain_tx_fifo
-    // - sm_set_clkdiv_int_frac
-    // - sm_set_clkdiv
-    // - sm_clear_fifos
-    // - sm_set_pins
-    // - sm_set_pins_with_mask
-    // - sm_set_pindirs_with_mask
-    // - sm_set_consecutive_pindirs
-    // - sm_claim
-    // - claim_sm_mask
-    // - sm_unclaim
-    // - claim_unused_sm
-    // - sm_is_claimed
-    //
+    pub fn sm_load_and_start_program(
+        self: Pio,
+        sm: StateMachine,
+        program: Program,
+        options: LoadAndStartProgramOptions,
+    ) !void {
+        const expected_side_set_pins = if (program.side_set) |side_set|
+            if (side_set.optional)
+                side_set.count - 1
+            else
+                side_set.count
+        else
+            0;
+
+        assert(expected_side_set_pins == options.pin_mappings.side_set.count);
+
+        // TODO: check program settings vs pin mapping
+        const offset = try self.add_program(program);
+        self.sm_init(sm, offset, .{
+            .clkdiv = options.clkdiv,
+            .shift = options.shift,
+            .pin_mappings = options.pin_mappings,
+            .exec = .{
+                .wrap = if (program.wrap) |wrap|
+                    wrap
+                else
+                    offset + @intCast(u5, program.instructions.len),
+
+                .wrap_target = if (program.wrap_target) |wrap_target|
+                    wrap_target
+                else
+                    offset,
+
+                .side_pindir = if (program.side_set) |side_set|
+                    side_set.pindirs
+                else
+                    false,
+
+                .side_set_optional = if (program.side_set) |side_set|
+                    side_set.optional
+                else
+                    false,
+            },
+        });
+    }
 };
 
 test "pio" {
     std.testing.refAllDecls(assembler);
-    //std.testing.refAllDecls(@import("pio/test.zig"));
 }
diff --git a/src/hal/pio/assembler.zig b/src/hal/pio/assembler.zig
index d3596fd93..af4153add 100644
--- a/src/hal/pio/assembler.zig
+++ b/src/hal/pio/assembler.zig
@@ -22,7 +22,7 @@ pub const Program = struct {
     wrap: ?u5,
 
     pub fn get_mask(program: Program) u32 {
-        return (1 << program.instructions.len) - 1;
+        return (@as(u32, 1) << @intCast(u5, program.instructions.len)) - 1;
     }
 };
 
@@ -35,7 +35,7 @@ pub const Output = struct {
         comptime name: []const u8,
     ) Program {
         return for (output.programs) |program| {
-            if (std.mem.eql(u8, program.name, program))
+            if (std.mem.eql(u8, name, program.name))
                 break program;
         } else @panic(std.fmt.comptimePrint("program '{s}' not found", .{name}));
     }

From 344f60b864b925cf8510a17cb6591bfdbcd3cf86 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 13 Apr 2023 17:04:50 -0700
Subject: [PATCH 117/286] add comptime keyword where it's needed (#42)

---
 src/hal/pio/assembler/tokenizer.zig | 32 ++++++++++++++---------------
 1 file changed, 16 insertions(+), 16 deletions(-)

diff --git a/src/hal/pio/assembler/tokenizer.zig b/src/hal/pio/assembler/tokenizer.zig
index cc360f50f..62e4c0e1f 100644
--- a/src/hal/pio/assembler/tokenizer.zig
+++ b/src/hal/pio/assembler/tokenizer.zig
@@ -1601,7 +1601,7 @@ test "tokenize.instr.jmp.conditions" {
     inline for (cases.kvs) |case| {
         const op = case.key;
         const cond = case.value;
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("jmp {s} my_label", .{op}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("jmp {s} my_label", .{op}));
 
         try expect_instr_jmp(.{ .cond = cond, .target = "my_label" }, tokens.get(0));
     }
@@ -1609,7 +1609,7 @@ test "tokenize.instr.jmp.conditions" {
 
 test "tokenize.instr.wait" {
     inline for (.{ "gpio", "pin", "irq" }) |source| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("wait 0 {s} 1", .{source}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("wait 0 {s} 1", .{source}));
         try expect_instr_wait(.{
             .polarity = 0,
             .source = @field(Token.Instruction.Wait.Source, source),
@@ -1637,7 +1637,7 @@ test "tokenize.instr.in" {
         "isr",
         "osr",
     }, 1..) |source, bit_count| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("in {s}, {}", .{
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("in {s}, {}", .{
             source,
             bit_count,
         }));
@@ -1660,7 +1660,7 @@ test "tokenize.instr.out" {
         "isr",
         "exec",
     }, 1..) |destination, bit_count| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("out {s}, {}", .{
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("out {s}, {}", .{
             destination,
             bit_count,
         }));
@@ -1736,7 +1736,7 @@ test "tokenize.instr.mov" {
         "isr",
         "osr",
     }) |source| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("mov x {s}", .{source}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("mov x {s}", .{source}));
 
         try expect_instr_mov(.{
             .source = @field(Token.Instruction.Mov.Source, source),
@@ -1753,7 +1753,7 @@ test "tokenize.instr.mov" {
         "isr",
         "osr",
     }) |dest| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("mov {s} x", .{dest}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("mov {s} x", .{dest}));
 
         try expect_instr_mov(.{
             .source = .x,
@@ -1772,7 +1772,7 @@ test "tokenize.instr.mov" {
         inline for (operations.kvs) |kv| {
             const str = kv.key;
             const operation = kv.value;
-            const tokens = try bounded_tokenize(std.fmt.comptimePrint("mov x {s}{s}y", .{
+            const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("mov x {s}{s}y", .{
                 str,
                 space,
             }));
@@ -1801,7 +1801,7 @@ test "tokenize.instr.irq" {
     });
 
     inline for (modes.kvs, 0..) |kv, num| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("irq {s} {}", .{
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("irq {s} {}", .{
             kv.key,
             num,
         }));
@@ -1831,7 +1831,7 @@ test "tokenize.instr.set" {
         "y",
         "pindirs",
     }) |dest| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("set {s}, 2", .{dest}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("set {s}, 2", .{dest}));
         try expect_instr_set(.{
             .dest = @field(Token.Instruction.Set.Destination, dest),
             .value = .{ .integer = 2 },
@@ -1862,7 +1862,7 @@ const instruction_examples = .{
 
 test "tokenize.instr.label prefixed" {
     inline for (instruction_examples) |instr| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("my_label: {s}", .{instr}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("my_label: {s}", .{instr}));
         try expectEqual(@as(usize, 2), tokens.len);
         try expect_label(.{ .name = "my_label" }, tokens.get(0));
     }
@@ -1870,7 +1870,7 @@ test "tokenize.instr.label prefixed" {
 
 test "tokenize.instr.side_set" {
     inline for (instruction_examples) |instr| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} side 0", .{instr}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("{s} side 0", .{instr}));
         const token = tokens.get(0);
         try expect_value(.{
             .expression = "0",
@@ -1881,7 +1881,7 @@ test "tokenize.instr.side_set" {
 
 test "tokenize.instr.delay" {
     inline for (instruction_examples) |instr| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} [1]", .{instr}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("{s} [1]", .{instr}));
         const token = tokens.get(0);
         try expectEqual(@as(?Value, null), token.data.instruction.side_set);
         try expect_value(.{
@@ -1892,7 +1892,7 @@ test "tokenize.instr.delay" {
 
 test "tokenize.instr.delay.expression" {
     inline for (instruction_examples) |instr| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} [T-1]", .{instr}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("{s} [T-1]", .{instr}));
         const token = tokens.get(0);
         try expectEqual(@as(?Value, null), token.data.instruction.side_set);
         try expect_value(.{
@@ -1903,7 +1903,7 @@ test "tokenize.instr.delay.expression" {
 
 test "tokenize.instr.side_set.expression" {
     inline for (instruction_examples) |instr| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} side (N-1)", .{instr}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("{s} side (N-1)", .{instr}));
         const token = tokens.get(0);
         try expect_value(.{
             .expression = "(N-1)",
@@ -1914,7 +1914,7 @@ test "tokenize.instr.side_set.expression" {
 
 test "tokenize.instr.side_set and delay" {
     inline for (instruction_examples) |instr| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} side 1 [2]", .{instr}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("{s} side 1 [2]", .{instr}));
         const token = tokens.get(0);
         try expect_value(.{
             .expression = "1",
@@ -1927,7 +1927,7 @@ test "tokenize.instr.side_set and delay" {
 
 test "tokenize.instr.side_set and delay reversed" {
     inline for (instruction_examples) |instr| {
-        const tokens = try bounded_tokenize(std.fmt.comptimePrint("{s} [2] side 1", .{instr}));
+        const tokens = try bounded_tokenize(comptime std.fmt.comptimePrint("{s} [2] side 1", .{instr}));
         const token = tokens.get(0);
         try expect_value(.{
             .expression = "1",

From 0fbf9ba10617394d51e131b2b97954f836f81377 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 13 Apr 2023 22:23:32 -0700
Subject: [PATCH 118/286] Update microzig (#12)

* update microzig

* fixed build.zig

---------

Co-authored-by: mattnite 
---
 build.zig     | 4 ++--
 deps/microzig | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/build.zig b/build.zig
index 86ad2161d..56ed4e58a 100644
--- a/build.zig
+++ b/build.zig
@@ -18,7 +18,7 @@ pub fn build(b: *std.build.Builder) void {
             .backing = .{ .board = @field(boards, decl.name) },
             .optimize = optimize,
         });
-        exe.install();
+        exe.installArtifact(b);
     }
 
     inline for (@typeInfo(chips).Struct.decls) |decl| {
@@ -33,6 +33,6 @@ pub fn build(b: *std.build.Builder) void {
             .backing = .{ .chip = @field(chips, decl.name) },
             .optimize = optimize,
         });
-        exe.install();
+        exe.installArtifact(b);
     }
 }
diff --git a/deps/microzig b/deps/microzig
index 23482a698..ae6e61919 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7
+Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763

From 9a8df1477bd2753928cb55c5e4f1a13feb7a0590 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 13 Apr 2023 22:23:57 -0700
Subject: [PATCH 119/286] Update microzig (#12)

* update microzig

* fixed build.zig

---------

Co-authored-by: mattnite 
---
 build.zig     | 4 ++--
 deps/microzig | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/build.zig b/build.zig
index 86ad2161d..56ed4e58a 100644
--- a/build.zig
+++ b/build.zig
@@ -18,7 +18,7 @@ pub fn build(b: *std.build.Builder) void {
             .backing = .{ .board = @field(boards, decl.name) },
             .optimize = optimize,
         });
-        exe.install();
+        exe.installArtifact(b);
     }
 
     inline for (@typeInfo(chips).Struct.decls) |decl| {
@@ -33,6 +33,6 @@ pub fn build(b: *std.build.Builder) void {
             .backing = .{ .chip = @field(chips, decl.name) },
             .optimize = optimize,
         });
-        exe.install();
+        exe.installArtifact(b);
     }
 }
diff --git a/deps/microzig b/deps/microzig
index 23482a698..ae6e61919 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7
+Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763

From 541a3f8ed933bb36f88f238b263b66b0e1213845 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 13 Apr 2023 22:24:05 -0700
Subject: [PATCH 120/286] Update microzig (#12)

* update microzig

* fixed build.zig

---------

Co-authored-by: mattnite 
---
 build.zig     | 4 ++--
 deps/microzig | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/build.zig b/build.zig
index 86ad2161d..56ed4e58a 100644
--- a/build.zig
+++ b/build.zig
@@ -18,7 +18,7 @@ pub fn build(b: *std.build.Builder) void {
             .backing = .{ .board = @field(boards, decl.name) },
             .optimize = optimize,
         });
-        exe.install();
+        exe.installArtifact(b);
     }
 
     inline for (@typeInfo(chips).Struct.decls) |decl| {
@@ -33,6 +33,6 @@ pub fn build(b: *std.build.Builder) void {
             .backing = .{ .chip = @field(chips, decl.name) },
             .optimize = optimize,
         });
-        exe.install();
+        exe.installArtifact(b);
     }
 }
diff --git a/deps/microzig b/deps/microzig
index 23482a698..ae6e61919 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7
+Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763

From 6cb89c778de67ca8abb64c31ab60ec4c34c7f943 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 13 Apr 2023 22:24:12 -0700
Subject: [PATCH 121/286] Update microzig (#13)

* update microzig

* fixed build.zig

---------

Co-authored-by: mattnite 
---
 build.zig     | 2 +-
 deps/microzig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/build.zig b/build.zig
index f96f446c5..8cb289d70 100644
--- a/build.zig
+++ b/build.zig
@@ -15,5 +15,5 @@ pub fn build(b: *std.build.Builder) void {
         .backing = .{ .chip = chips.esp32_c3 },
         .optimize = optimize,
     });
-    exe.install();
+    exe.installArtifact(b);
 }
diff --git a/deps/microzig b/deps/microzig
index 23482a698..ae6e61919 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7
+Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763

From fa78bbfc4ab51ab46dbc9ad3ebd95cd0ea64a1d2 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 13 Apr 2023 22:24:28 -0700
Subject: [PATCH 122/286] update microzig (#43)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ceaa9ddcb..ae6e61919 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ceaa9ddcb080d0687ce2109f23db7db376ac911e
+Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763

From f1d338b3e22e0e484071559da696cbda5b46d253 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 13 Apr 2023 22:24:36 -0700
Subject: [PATCH 123/286] Update microzig (#12)

* update microzig

* fixed build.zig

---------

Co-authored-by: mattnite 
---
 build.zig     | 2 +-
 deps/microzig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/build.zig b/build.zig
index edb8df879..ff60e94a8 100644
--- a/build.zig
+++ b/build.zig
@@ -17,6 +17,6 @@ pub fn build(b: *std.build.Builder) void {
             .backing = .{ .chip = @field(chips, decl.name) },
             .optimize = optimize,
         });
-        exe.install();
+        exe.installArtifact(b);
     }
 }
diff --git a/deps/microzig b/deps/microzig
index 23482a698..ae6e61919 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7
+Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763

From 01dfc9aa1942e943507fb82de82604e18c9f793e Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 13 Apr 2023 22:24:43 -0700
Subject: [PATCH 124/286] Update microzig (#12)

* update microzig

* fixed build.zig

---------

Co-authored-by: mattnite 
---
 build.zig     | 4 ++--
 deps/microzig | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/build.zig b/build.zig
index 86ad2161d..56ed4e58a 100644
--- a/build.zig
+++ b/build.zig
@@ -18,7 +18,7 @@ pub fn build(b: *std.build.Builder) void {
             .backing = .{ .board = @field(boards, decl.name) },
             .optimize = optimize,
         });
-        exe.install();
+        exe.installArtifact(b);
     }
 
     inline for (@typeInfo(chips).Struct.decls) |decl| {
@@ -33,6 +33,6 @@ pub fn build(b: *std.build.Builder) void {
             .backing = .{ .chip = @field(chips, decl.name) },
             .optimize = optimize,
         });
-        exe.install();
+        exe.installArtifact(b);
     }
 }
diff --git a/deps/microzig b/deps/microzig
index 23482a698..ae6e61919 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 23482a6986252e0eeff54a04abc0aac8a08d25d7
+Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763

From 975e5e446c298f98c26573dad1198c1f6186e1a0 Mon Sep 17 00:00:00 2001
From: David Sugar 
Date: Sun, 23 Apr 2023 17:11:05 +0200
Subject: [PATCH 125/286] Random number generator (#46)

---
 build.zig           |  1 +
 examples/random.zig | 69 +++++++++++++++++++++++++++++++++++
 src/hal.zig         |  1 +
 src/hal/random.zig  | 87 +++++++++++++++++++++++++++++++++++++++++++++
 4 files changed, 158 insertions(+)
 create mode 100644 examples/random.zig
 create mode 100644 src/hal/random.zig

diff --git a/build.zig b/build.zig
index f9d372944..c54780cae 100644
--- a/build.zig
+++ b/build.zig
@@ -69,6 +69,7 @@ pub const Examples = struct {
     squarewave: *microzig.EmbeddedExecutable,
     //uart_pins: microzig.EmbeddedExecutable,
     flash_program: *microzig.EmbeddedExecutable,
+    random: *microzig.EmbeddedExecutable,
 
     pub fn init(b: *Builder, optimize: std.builtin.OptimizeMode) Examples {
         var ret: Examples = undefined;
diff --git a/examples/random.zig b/examples/random.zig
new file mode 100644
index 000000000..dbf00d5f0
--- /dev/null
+++ b/examples/random.zig
@@ -0,0 +1,69 @@
+//! Example that generates a 4 byte random number every second and outputs the result over UART
+
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const flash = rp2040.flash;
+const time = rp2040.time;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+const rand = rp2040.rand;
+
+const led = 25;
+const uart_id = 0;
+const baud_rate = 115200;
+const uart_tx_pin = 0;
+const uart_rx_pin = 1;
+
+pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
+    std.log.err("panic: {s}", .{message});
+    @breakpoint();
+    while (true) {}
+}
+
+pub const std_options = struct {
+    pub const log_level = .debug;
+    pub const logFn = rp2040.uart.log;
+};
+
+pub fn main() !void {
+    gpio.reset();
+    gpio.init(led);
+    gpio.set_direction(led, .out);
+    gpio.put(led, 1);
+
+    const uart = rp2040.uart.UART.init(uart_id, .{
+        .baud_rate = baud_rate,
+        .tx_pin = uart_tx_pin,
+        .rx_pin = uart_rx_pin,
+        .clock_config = rp2040.clock_config,
+    });
+
+    var ascon = rand.Ascon.init();
+    var rng = ascon.random();
+
+    rp2040.uart.init_logger(uart);
+
+    var buffer: [8]u8 = undefined;
+    var dist: [256]usize = .{0} ** 256;
+    var counter: usize = 0;
+
+    while (true) {
+        rng.bytes(buffer[0..]);
+        counter += 8;
+        for (buffer) |byte| {
+            dist[@intCast(usize, byte)] += 1;
+        }
+        std.log.info("Generate random number: {any}", .{buffer});
+
+        if (counter % 256 == 0) {
+            var i: usize = 0;
+            std.log.info("Distribution:", .{});
+            while (i < 256) : (i += 1) {
+                std.log.info("{} -> {}, {d:2}%", .{ i, dist[i], @intToFloat(f32, dist[i]) / @intToFloat(f32, counter) });
+            }
+        }
+        time.sleep_ms(1000);
+    }
+}
diff --git a/src/hal.zig b/src/hal.zig
index 5813cf947..1350d07be 100644
--- a/src/hal.zig
+++ b/src/hal.zig
@@ -16,6 +16,7 @@ pub const irq = @import("hal/irq.zig");
 pub const rom = @import("hal/rom.zig");
 pub const flash = @import("hal/flash.zig");
 pub const pio = @import("hal/pio.zig");
+pub const rand = @import("hal/random.zig");
 
 pub const clock_config = clocks.GlobalConfiguration.init(.{
     .ref = .{ .source = .src_xosc },
diff --git a/src/hal/random.zig b/src/hal/random.zig
new file mode 100644
index 000000000..3a292a628
--- /dev/null
+++ b/src/hal/random.zig
@@ -0,0 +1,87 @@
+//! Random number generator (RNG) using the Ascon CSPRNG
+
+const std = @import("std");
+const assert = std.debug.assert;
+const Random = std.rand.Random;
+
+const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+
+/// Wrapper around the Ascon CSPRNG with automatic reseed using the ROSC
+///
+/// ## Usage
+///
+/// ```zig
+/// var ascon = Ascon.init();
+/// var rng = ascon.random();
+/// ```
+///
+/// _WARNING_: This might not meet the requirements of randomness
+/// for security systems because the ROSC as entropy source can be
+/// compromised. However, it promises at least equal distribution.
+pub const Ascon = struct {
+    state: std.rand.Ascon,
+    counter: usize = 0,
+
+    const reseed_threshold = 4096;
+    const secret_seed_length = std.rand.Ascon.secret_seed_length;
+
+    pub fn init() @This() {
+        // Ensure that the system clocks run from the XOSC and/or PLLs
+        const ref_src = peripherals.CLOCKS.CLK_REF_CTRL.read().SRC.value;
+        const sys_clk_src = peripherals.CLOCKS.CLK_SYS_CTRL.read().SRC.value;
+        const aux_src = peripherals.CLOCKS.CLK_SYS_CTRL.read().AUXSRC.value;
+        assert((ref_src != .rosc_clksrc_ph and sys_clk_src == .clk_ref) or
+            (sys_clk_src == .clksrc_clk_sys_aux and aux_src != .rosc_clksrc));
+
+        // Get `secret_seed_length` random bytes from the ROSC ...
+        var b: [secret_seed_length]u8 = undefined;
+        rosc(&b);
+
+        return @This(){ .state = std.rand.Ascon.init(b) };
+    }
+
+    /// Returns a `std.rand.Random` structure backed by the current RNG
+    pub fn random(self: *@This()) Random {
+        return Random.init(self, fill);
+    }
+
+    /// Fills the buffer with random bytes
+    pub fn fill(self: *@This(), buf: []u8) void {
+        // Reseed every `secret_seed_length` bytes
+        if (self.counter > reseed_threshold) {
+            var b: [secret_seed_length]u8 = undefined;
+            rosc(&b);
+            self.state.addEntropy(&b);
+            self.counter = 0;
+        }
+        self.state.fill(buf);
+        self.counter += buf.len;
+    }
+
+    /// Fill the buffer with up to buffer.len random bytes
+    ///
+    /// rand uses the RANDOMBIT register of the ROSC as its source, i. e.,
+    /// the system clocks _MUST_ run from the XOSC and/or PLLs.
+    ///
+    /// _WARNING_: This function does not meet the requirements of randomness
+    /// for security systems because it can be compromised, but it may be useful
+    /// in less critical applications.
+    fn rosc(buffer: []u8) void {
+        const rosc_state = peripherals.ROSC.CTRL.read().ENABLE.value;
+        // Enable the ROSC so it generates random bits for us
+        peripherals.ROSC.CTRL.modify(.{ .ENABLE = .{ .value = .ENABLE } });
+        defer peripherals.ROSC.CTRL.modify(.{ .ENABLE = .{ .value = rosc_state } });
+
+        var i: usize = 0;
+        while (i < buffer.len) : (i += 1) {
+            // We poll RANDOMBIT eight times per cycle to build a random byte
+            var r: u8 = @intCast(u8, peripherals.ROSC.RANDOMBIT.read().RANDOMBIT);
+            var j: usize = 0;
+            while (j < 7) : (j += 1) {
+                r = (r << 1) | @intCast(u8, peripherals.ROSC.RANDOMBIT.read().RANDOMBIT);
+            }
+            buffer[i] = r;
+        }
+    }
+};

From b0b01570c1ac1fb3d606dd782ce6021bda565e1f Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 23 Apr 2023 11:55:47 -0700
Subject: [PATCH 126/286] update microzig (#47)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ae6e61919..dd491cc84 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763
+Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab

From 8b7cbf09d3a261a7d7b83cb9520d237126006c77 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 23 Apr 2023 11:56:04 -0700
Subject: [PATCH 127/286] update microzig (#14)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ae6e61919..dd491cc84 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763
+Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab

From c2c9cc4912a99e92a574a72f379494b4e9a40edf Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 23 Apr 2023 11:56:15 -0700
Subject: [PATCH 128/286] update microzig (#14)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ae6e61919..dd491cc84 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763
+Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab

From d96ce9cc50db93a416185d0eeff102322659227c Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 23 Apr 2023 11:56:24 -0700
Subject: [PATCH 129/286] update microzig (#14)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ae6e61919..dd491cc84 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763
+Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab

From 33a67724a7195e9acf1338d9f6b90e0d46f3179a Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 23 Apr 2023 11:56:32 -0700
Subject: [PATCH 130/286] update microzig (#14)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ae6e61919..dd491cc84 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763
+Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab

From c9ff9fcc404ee7121196279416d357689a7e1228 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 23 Apr 2023 11:56:42 -0700
Subject: [PATCH 131/286] update microzig (#15)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ae6e61919..dd491cc84 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763
+Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab

From dfeaf74bf96dfd199a64bcbe42c728a954e1eba0 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Sun, 23 Apr 2023 11:56:47 -0700
Subject: [PATCH 132/286] update microzig (#14)

---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index ae6e61919..dd491cc84 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit ae6e619197f5db4be18a4b8cf7bf4d1bde9e7763
+Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab

From 812fb44180d6d2ba141f0e7889e0c1e2345b52c2 Mon Sep 17 00:00:00 2001
From: David Sugar 
Date: Mon, 24 Apr 2023 16:45:24 +0200
Subject: [PATCH 133/286] USB Device (#40)

---
 build.zig                               |   4 +-
 examples/scripts/hid_test.py            |  29 ++
 examples/scripts/usb_device_loopback.py |  48 ++
 examples/usb_device.zig                 | 173 +++++++
 examples/usb_hid.zig                    | 188 +++++++
 src/hal.zig                             |   6 +
 src/hal/rom.zig                         |   6 +-
 src/hal/usb.zig                         | 647 ++++++++++++++++++++++++
 8 files changed, 1097 insertions(+), 4 deletions(-)
 create mode 100755 examples/scripts/hid_test.py
 create mode 100755 examples/scripts/usb_device_loopback.py
 create mode 100644 examples/usb_device.zig
 create mode 100644 examples/usb_hid.zig
 create mode 100644 src/hal/usb.zig

diff --git a/build.zig b/build.zig
index c54780cae..1ee7e1716 100644
--- a/build.zig
+++ b/build.zig
@@ -44,7 +44,7 @@ pub fn build(b: *Builder) !void {
 
     const pio_tests = b.addTest(.{
         .root_source_file = .{
-            .path = "src/hal/pio.zig",
+            .path = "src/hal.zig",
         },
         .optimize = optimize,
     });
@@ -69,6 +69,8 @@ pub const Examples = struct {
     squarewave: *microzig.EmbeddedExecutable,
     //uart_pins: microzig.EmbeddedExecutable,
     flash_program: *microzig.EmbeddedExecutable,
+    usb_device: *microzig.EmbeddedExecutable,
+    usb_hid: *microzig.EmbeddedExecutable,
     random: *microzig.EmbeddedExecutable,
 
     pub fn init(b: *Builder, optimize: std.builtin.OptimizeMode) Examples {
diff --git a/examples/scripts/hid_test.py b/examples/scripts/hid_test.py
new file mode 100755
index 000000000..ccc2dd093
--- /dev/null
+++ b/examples/scripts/hid_test.py
@@ -0,0 +1,29 @@
+#!/usr/bin/env python3
+
+# Install python3 HID package https://pypi.org/project/hid/
+import hid
+
+# default is TinyUSB (0xcafe), Adafruit (0x239a), RaspberryPi (0x2e8a), Espressif (0x303a) VID
+USB_VID = (0xcafe, 0x239a, 0x2e8a, 0x303a)
+
+print("VID list: " + ", ".join('%02x' % v for v in USB_VID))
+
+for vid in  USB_VID:
+    for dict in hid.enumerate(vid):
+        print(dict)
+        dev = hid.Device(dict['vendor_id'], dict['product_id'])
+        if dev:
+            while True:
+                inp = input("Send text to HID Device : ").encode('utf-8')
+                dev.write(inp)
+
+                x = 0
+                l = len(inp)
+                r = b""
+                while (x < l):
+                    str_in = dev.read(64)
+                    r += str_in
+                    x += 64
+
+                print("Received from HID Device:\n", r)
+                print("hex:\n", r.hex())
diff --git a/examples/scripts/usb_device_loopback.py b/examples/scripts/usb_device_loopback.py
new file mode 100755
index 000000000..82bf47899
--- /dev/null
+++ b/examples/scripts/usb_device_loopback.py
@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+
+#
+# Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# sudo pip3 install pyusb
+
+import usb.core
+import usb.util
+
+# find our device
+dev = usb.core.find(idVendor=0x0000, idProduct=0x0001)
+
+# was it found?
+if dev is None:
+    raise ValueError('Device not found')
+
+# get an endpoint instance
+cfg = dev.get_active_configuration()
+intf = cfg[(0, 0)]
+
+outep = usb.util.find_descriptor(
+    intf,
+    # match the first OUT endpoint
+    custom_match= \
+        lambda e: \
+            usb.util.endpoint_direction(e.bEndpointAddress) == \
+            usb.util.ENDPOINT_OUT)
+
+inep = usb.util.find_descriptor(
+    intf,
+    # match the first IN endpoint
+    custom_match= \
+        lambda e: \
+            usb.util.endpoint_direction(e.bEndpointAddress) == \
+            usb.util.ENDPOINT_IN)
+
+assert inep is not None
+assert outep is not None
+
+test_string = "Hello World!"
+outep.write(test_string)
+from_device = inep.read(len(test_string))
+
+print("Device Says: {}".format(''.join([chr(x) for x in from_device])))
diff --git a/examples/usb_device.zig b/examples/usb_device.zig
new file mode 100644
index 000000000..c86d5e140
--- /dev/null
+++ b/examples/usb_device.zig
@@ -0,0 +1,173 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const flash = rp2040.flash;
+const time = rp2040.time;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+const usb = rp2040.usb;
+
+const led = 25;
+const uart_id = 0;
+const baud_rate = 115200;
+const uart_tx_pin = 0;
+const uart_rx_pin = 1;
+
+// First we define two callbacks that will be used by the endpoints we define next...
+fn ep1_in_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
+    _ = data;
+    // The host has collected the data we repeated onto
+    // EP1! Set up to receive more data on EP1.
+    usb.Usb.callbacks.usb_start_rx(
+        dc.endpoints[2], // EP1_OUT_CFG,
+        64,
+    );
+}
+
+fn ep1_out_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
+    // We've gotten data from the host on our custom
+    // EP1! Set up EP1 to repeat it.
+    usb.Usb.callbacks.usb_start_tx(
+        dc.endpoints[3], // EP1_IN_CFG,
+        data,
+    );
+}
+
+// The endpoints EP0_IN and EP0_OUT are already defined but you can
+// add your own endpoints to...
+pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
+    .descriptor = &usb.EndpointDescriptor{
+        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .descriptor_type = usb.DescType.Endpoint,
+        .endpoint_address = usb.Dir.Out.endpoint(1),
+        .attributes = @enumToInt(usb.TransferType.Bulk),
+        .max_packet_size = 64,
+        .interval = 0,
+    },
+    .endpoint_control_index = 2,
+    .buffer_control_index = 3,
+    .data_buffer_index = 2,
+    .next_pid_1 = false,
+    // The callback will be executed if we got an interrupt on EP1_OUT
+    .callback = ep1_out_callback,
+};
+
+pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
+    .descriptor = &usb.EndpointDescriptor{
+        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .descriptor_type = usb.DescType.Endpoint,
+        .endpoint_address = usb.Dir.In.endpoint(1),
+        .attributes = @enumToInt(usb.TransferType.Bulk),
+        .max_packet_size = 64,
+        .interval = 0,
+    },
+    .endpoint_control_index = 1,
+    .buffer_control_index = 2,
+    .data_buffer_index = 3,
+    .next_pid_1 = false,
+    // The callback will be executed if we got an interrupt on EP1_IN
+    .callback = ep1_in_callback,
+};
+
+// This is our device configuration
+pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
+    .device_descriptor = &.{
+        .length = @intCast(u8, @sizeOf(usb.DeviceDescriptor)),
+        .descriptor_type = usb.DescType.Device,
+        .bcd_usb = 0x0110,
+        .device_class = 0,
+        .device_subclass = 0,
+        .device_protocol = 0,
+        .max_packet_size0 = 64,
+        .vendor = 0,
+        .product = 1,
+        .bcd_device = 0,
+        .manufacturer_s = 1,
+        .product_s = 2,
+        .serial_s = 0,
+        .num_configurations = 1,
+    },
+    .interface_descriptor = &.{
+        .length = @intCast(u8, @sizeOf(usb.InterfaceDescriptor)),
+        .descriptor_type = usb.DescType.Interface,
+        .interface_number = 0,
+        .alternate_setting = 0,
+        // We have two endpoints (EP0 IN/OUT don't count)
+        .num_endpoints = 2,
+        .interface_class = 0xff,
+        .interface_subclass = 0,
+        .interface_protocol = 0,
+        .interface_s = 0,
+    },
+    .config_descriptor = &.{
+        .length = @intCast(u8, @sizeOf(usb.ConfigurationDescriptor)),
+        .descriptor_type = usb.DescType.Config,
+        .total_length = @intCast(u8, @sizeOf(usb.ConfigurationDescriptor) + @sizeOf(usb.InterfaceDescriptor) + @sizeOf(usb.EndpointDescriptor) + @sizeOf(usb.EndpointDescriptor)),
+        .num_interfaces = 1,
+        .configuration_value = 1,
+        .configuration_s = 0,
+        .attributes = 0xc0,
+        .max_power = 0x32,
+    },
+    .lang_descriptor = "\x04\x03\x09\x04", // length || string descriptor (0x03) || Engl (0x0409)
+    .descriptor_strings = &.{
+        // ugly unicode :|
+        "R\x00a\x00s\x00p\x00b\x00e\x00r\x00r\x00y\x00 \x00P\x00i\x00",
+        "P\x00i\x00c\x00o\x00 \x00T\x00e\x00s\x00t\x00 \x00D\x00e\x00v\x00i\x00c\x00e\x00",
+    },
+    // Here we pass all endpoints to the config
+    // Dont forget to pass EP0_[IN|OUT] in the order seen below!
+    .endpoints = .{
+        &usb.EP0_OUT_CFG,
+        &usb.EP0_IN_CFG,
+        &EP1_OUT_CFG,
+        &EP1_IN_CFG,
+    },
+};
+
+pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
+    std.log.err("panic: {s}", .{message});
+    @breakpoint();
+    while (true) {}
+}
+
+pub const std_options = struct {
+    pub const log_level = .debug;
+    pub const logFn = rp2040.uart.log;
+};
+
+pub fn main() !void {
+    gpio.reset();
+    gpio.init(led);
+    gpio.set_direction(led, .out);
+    gpio.put(led, 1);
+
+    const uart = rp2040.uart.UART.init(uart_id, .{
+        .baud_rate = baud_rate,
+        .tx_pin = uart_tx_pin,
+        .rx_pin = uart_rx_pin,
+        .clock_config = rp2040.clock_config,
+    });
+
+    rp2040.uart.init_logger(uart);
+
+    // First we initialize the USB clock
+    rp2040.usb.Usb.init_clk();
+    // Then initialize the USB device using the configuration defined above
+    rp2040.usb.Usb.init_device(&DEVICE_CONFIGURATION) catch unreachable;
+    var old: u64 = time.get_time_since_boot().us_since_boot;
+    var new: u64 = 0;
+    while (true) {
+        // You can now poll for USB events
+        rp2040.usb.Usb.task(
+            false, // debug output over UART [Y/n]
+        ) catch unreachable;
+
+        new = time.get_time_since_boot().us_since_boot;
+        if (new - old > 500000) {
+            old = new;
+            gpio.toggle(led);
+        }
+    }
+}
diff --git a/examples/usb_hid.zig b/examples/usb_hid.zig
new file mode 100644
index 000000000..633add74f
--- /dev/null
+++ b/examples/usb_hid.zig
@@ -0,0 +1,188 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const flash = rp2040.flash;
+const time = rp2040.time;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+const usb = rp2040.usb;
+
+const led = 25;
+const uart_id = 0;
+const baud_rate = 115200;
+const uart_tx_pin = 0;
+const uart_rx_pin = 1;
+
+// First we define two callbacks that will be used by the endpoints we define next...
+fn ep1_in_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
+    _ = data;
+    // The host has collected the data we repeated onto
+    // EP1! Set up to receive more data on EP1.
+    usb.Usb.callbacks.usb_start_rx(
+        dc.endpoints[2], // EP1_OUT_CFG,
+        64,
+    );
+}
+
+fn ep1_out_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
+    // We've gotten data from the host on our custom
+    // EP1! Set up EP1 to repeat it.
+    usb.Usb.callbacks.usb_start_tx(
+        dc.endpoints[3], // EP1_IN_CFG,
+        data,
+    );
+}
+
+// The endpoints EP0_IN and EP0_OUT are already defined but you can
+// add your own endpoints to...
+pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
+    .descriptor = &usb.EndpointDescriptor{
+        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .descriptor_type = usb.DescType.Endpoint,
+        .endpoint_address = usb.Dir.Out.endpoint(1),
+        .attributes = @enumToInt(usb.TransferType.Interrupt),
+        .max_packet_size = 64,
+        .interval = 0,
+    },
+    .endpoint_control_index = 2,
+    .buffer_control_index = 3,
+    .data_buffer_index = 2,
+    .next_pid_1 = false,
+    // The callback will be executed if we got an interrupt on EP1_OUT
+    .callback = ep1_out_callback,
+};
+
+pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
+    .descriptor = &usb.EndpointDescriptor{
+        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .descriptor_type = usb.DescType.Endpoint,
+        .endpoint_address = usb.Dir.In.endpoint(1),
+        .attributes = @enumToInt(usb.TransferType.Interrupt),
+        .max_packet_size = 64,
+        .interval = 0,
+    },
+    .endpoint_control_index = 1,
+    .buffer_control_index = 2,
+    .data_buffer_index = 3,
+    .next_pid_1 = false,
+    // The callback will be executed if we got an interrupt on EP1_IN
+    .callback = ep1_in_callback,
+};
+
+// This is our device configuration
+pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
+    .device_descriptor = &.{
+        .length = @intCast(u8, @sizeOf(usb.DeviceDescriptor)),
+        .descriptor_type = usb.DescType.Device,
+        .bcd_usb = 0x0200,
+        .device_class = 0,
+        .device_subclass = 0,
+        .device_protocol = 0,
+        .max_packet_size0 = 64,
+        .vendor = 0xCafe,
+        .product = 1,
+        .bcd_device = 0x0100,
+        // Those are indices to the descriptor strings
+        // Make sure to provide enough string descriptors!
+        .manufacturer_s = 1,
+        .product_s = 2,
+        .serial_s = 3,
+        .num_configurations = 1,
+    },
+    .interface_descriptor = &.{
+        .length = @intCast(u8, @sizeOf(usb.InterfaceDescriptor)),
+        .descriptor_type = usb.DescType.Interface,
+        .interface_number = 0,
+        .alternate_setting = 0,
+        // We have two endpoints (EP0 IN/OUT don't count)
+        .num_endpoints = 2,
+        .interface_class = 3,
+        .interface_subclass = 0,
+        .interface_protocol = 0,
+        .interface_s = 0,
+    },
+    .config_descriptor = &.{
+        .length = @intCast(u8, @sizeOf(usb.ConfigurationDescriptor)),
+        .descriptor_type = usb.DescType.Config,
+        .total_length = @intCast(u8, @sizeOf(usb.ConfigurationDescriptor) + @sizeOf(usb.InterfaceDescriptor) + @sizeOf(usb.EndpointDescriptor) + @sizeOf(usb.EndpointDescriptor)),
+        .num_interfaces = 1,
+        .configuration_value = 1,
+        .configuration_s = 0,
+        .attributes = 0xc0,
+        .max_power = 0x32,
+    },
+    .lang_descriptor = "\x04\x03\x09\x04", // length || string descriptor (0x03) || Engl (0x0409)
+    .descriptor_strings = &.{
+        // ugly unicode :|
+        //"R\x00a\x00s\x00p\x00b\x00e\x00r\x00r\x00y\x00 \x00P\x00i\x00",
+        &usb.utf8ToUtf16Le("Raspberry Pi"),
+        //"P\x00i\x00c\x00o\x00 \x00T\x00e\x00s\x00t\x00 \x00D\x00e\x00v\x00i\x00c\x00e\x00",
+        &usb.utf8ToUtf16Le("Pico Test Device"),
+        //"c\x00a\x00f\x00e\x00b\x00a\x00b\x00e\x00",
+        &usb.utf8ToUtf16Le("cafebabe"),
+    },
+    .hid = .{
+        .hid_descriptor = &.{
+            .bcd_hid = 0x0111,
+            .country_code = 0,
+            .num_descriptors = 1,
+            .report_length = 34,
+        },
+        .report_descriptor = &usb.hid.ReportDescriptorFidoU2f,
+    },
+    // Here we pass all endpoints to the config
+    // Dont forget to pass EP0_[IN|OUT] in the order seen below!
+    .endpoints = .{
+        &usb.EP0_OUT_CFG,
+        &usb.EP0_IN_CFG,
+        &EP1_OUT_CFG,
+        &EP1_IN_CFG,
+    },
+};
+
+pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
+    std.log.err("panic: {s}", .{message});
+    @breakpoint();
+    while (true) {}
+}
+
+pub const std_options = struct {
+    pub const log_level = .debug;
+    pub const logFn = rp2040.uart.log;
+};
+
+pub fn main() !void {
+    gpio.reset();
+    gpio.init(led);
+    gpio.set_direction(led, .out);
+    gpio.put(led, 1);
+
+    const uart = rp2040.uart.UART.init(uart_id, .{
+        .baud_rate = baud_rate,
+        .tx_pin = uart_tx_pin,
+        .rx_pin = uart_rx_pin,
+        .clock_config = rp2040.clock_config,
+    });
+
+    rp2040.uart.init_logger(uart);
+
+    // First we initialize the USB clock
+    rp2040.usb.Usb.init_clk();
+    // Then initialize the USB device using the configuration defined above
+    rp2040.usb.Usb.init_device(&DEVICE_CONFIGURATION) catch unreachable;
+    var old: u64 = time.get_time_since_boot().us_since_boot;
+    var new: u64 = 0;
+    while (true) {
+        // You can now poll for USB events
+        rp2040.usb.Usb.task(
+            true, // debug output over UART [Y/n]
+        ) catch unreachable;
+
+        new = time.get_time_since_boot().us_since_boot;
+        if (new - old > 500000) {
+            old = new;
+            gpio.toggle(led);
+        }
+    }
+}
diff --git a/src/hal.zig b/src/hal.zig
index 1350d07be..c9ac98639 100644
--- a/src/hal.zig
+++ b/src/hal.zig
@@ -16,6 +16,7 @@ pub const irq = @import("hal/irq.zig");
 pub const rom = @import("hal/rom.zig");
 pub const flash = @import("hal/flash.zig");
 pub const pio = @import("hal/pio.zig");
+pub const usb = @import("hal/usb.zig");
 pub const rand = @import("hal/random.zig");
 
 pub const clock_config = clocks.GlobalConfiguration.init(.{
@@ -37,3 +38,8 @@ pub fn init() void {
 pub fn get_cpu_id() u32 {
     return SIO.CPUID.*;
 }
+
+test "hal tests" {
+    _ = pio;
+    _ = usb;
+}
diff --git a/src/hal/rom.zig b/src/hal/rom.zig
index 128c08549..b76eb80a6 100644
--- a/src/hal/rom.zig
+++ b/src/hal/rom.zig
@@ -47,9 +47,9 @@ pub const signatures = struct {
     /// Signature of memset4: Sets n bytes start at ptr to the value c and returns ptr; must be word (32-bit) aligned!
     const memset4 = fn (ptr: [*]u32, c: u8, n: u32) [*]u32;
     /// Signature of memcpy: Copies n bytes starting at src to dest and returns dest. The results are undefined if the regions overlap.
-    const memcpy = fn (dest: [*]u8, src: [*]u8, n: u32) [*]u8;
+    const memcpy = fn (dest: [*]u8, src: [*]const u8, n: u32) [*]u8;
     /// Signature of memcpy44: Copies n bytes starting at src to dest and returns dest; must be word (32-bit) aligned!
-    const memcpy44 = fn (dest: [*]u32, src: [*]u32, n: u32) [*]u8;
+    const memcpy44 = fn (dest: [*]u32, src: [*]const u32, n: u32) [*]u8;
     /// Signature of connect_internal_flash: Restore all QSPI pad controls to their default state, and connect the SSI to the QSPI pads
     const connect_internal_flash = fn () void;
     /// Signature of flash_exit_xip: First set up the SSI for serial-mode operations, then issue the fixed XIP exit sequence described in
@@ -189,7 +189,7 @@ pub fn memset(dest: []u8, c: u8) []u8 {
 }
 
 /// Copies n bytes from src to dest; The number of bytes copied is the size of the smaller slice
-pub fn memcpy(dest: []u8, src: []u8) []u8 {
+pub fn memcpy(dest: []u8, src: []const u8) []u8 {
     const S = struct {
         var f: ?*signatures.memcpy = null;
     };
diff --git a/src/hal/usb.zig b/src/hal/usb.zig
new file mode 100644
index 000000000..48538a48a
--- /dev/null
+++ b/src/hal/usb.zig
@@ -0,0 +1,647 @@
+//! USB device implementation
+//!
+//! Inspired by cbiffle's Rust [implementation](https://github.com/cbiffle/rp2040-usb-device-in-one-file/blob/main/src/main.rs)
+
+const std = @import("std");
+
+const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+
+/// Human Interface Device (HID)
+pub const usb = microzig.core.usb;
+pub const hid = usb.hid;
+
+const rom = @import("rom.zig");
+const resets = @import("resets.zig");
+
+pub const EP0_OUT_IDX = 0;
+pub const EP0_IN_IDX = 1;
+
+// +++++++++++++++++++++++++++++++++++++++++++++++++
+// User Interface
+// +++++++++++++++++++++++++++++++++++++++++++++++++
+
+/// The rp2040 usb device impl
+///
+/// We create a concrete implementaion by passing a handful
+/// of system specific functions to Usb(). Those functions
+/// are used by the abstract USB impl of microzig.
+pub const Usb = usb.Usb(F);
+
+pub const DeviceConfiguration = usb.DeviceConfiguration;
+pub const DeviceDescriptor = usb.DeviceDescriptor;
+pub const DescType = usb.DescType;
+pub const InterfaceDescriptor = usb.InterfaceDescriptor;
+pub const ConfigurationDescriptor = usb.ConfigurationDescriptor;
+pub const EndpointDescriptor = usb.EndpointDescriptor;
+pub const EndpointConfiguration = usb.EndpointConfiguration;
+pub const Dir = usb.Dir;
+pub const TransferType = usb.TransferType;
+
+pub const utf8ToUtf16Le = usb.utf8Toutf16Le;
+
+pub var EP0_OUT_CFG: usb.EndpointConfiguration = .{
+    .descriptor = &usb.EndpointDescriptor{
+        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .descriptor_type = usb.DescType.Endpoint,
+        .endpoint_address = usb.EP0_OUT_ADDR,
+        .attributes = @enumToInt(usb.TransferType.Control),
+        .max_packet_size = 64,
+        .interval = 0,
+    },
+    .endpoint_control_index = null,
+    .buffer_control_index = 1,
+    .data_buffer_index = 0,
+    .next_pid_1 = false,
+};
+
+pub var EP0_IN_CFG: usb.EndpointConfiguration = .{
+    .descriptor = &usb.EndpointDescriptor{
+        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .descriptor_type = usb.DescType.Endpoint,
+        .endpoint_address = usb.EP0_IN_ADDR,
+        .attributes = @enumToInt(usb.TransferType.Control),
+        .max_packet_size = 64,
+        .interval = 0,
+    },
+    .endpoint_control_index = null,
+    .buffer_control_index = 0,
+    .data_buffer_index = 0,
+    .next_pid_1 = false,
+};
+
+// +++++++++++++++++++++++++++++++++++++++++++++++++
+// Reference to endpoint buffers
+// +++++++++++++++++++++++++++++++++++++++++++++++++
+
+/// USB data buffers
+pub const buffers = struct {
+    // Address 0x100-0xfff (3840 bytes) can be used for data buffers.
+    const USBDPRAM_BASE = 0x50100100;
+    // Data buffers are 64 bytes long as this is the max normal packet size
+    const BUFFER_SIZE = 64;
+    /// EP0 buffer 0 (shared between in and out)
+    const USB_EP0_BUFFER0 = USBDPRAM_BASE;
+    /// Optional EP0 buffer 1
+    const USB_EP0_BUFFER1 = USBDPRAM_BASE + BUFFER_SIZE;
+    /// Data buffers
+    const USB_BUFFERS = USBDPRAM_BASE + (2 * BUFFER_SIZE);
+
+    /// Mapping to the different data buffers in DPSRAM
+    pub var B: usb.Buffers = .{
+        .ep0_buffer0 = @intToPtr([*]u8, USB_EP0_BUFFER0),
+        .ep0_buffer1 = @intToPtr([*]u8, USB_EP0_BUFFER1),
+        // We will initialize this comptime in a loop
+        .rest = .{
+            @intToPtr([*]u8, USB_BUFFERS + (0 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (1 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (2 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (3 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (4 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (5 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (6 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (7 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (8 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (9 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (10 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (11 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (12 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (13 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (14 * BUFFER_SIZE)),
+            @intToPtr([*]u8, USB_BUFFERS + (15 * BUFFER_SIZE)),
+        },
+    };
+};
+
+// +++++++++++++++++++++++++++++++++++++++++++++++++
+// Code
+// +++++++++++++++++++++++++++++++++++++++++++++++++
+
+/// A set of functions required by the abstract USB impl to
+/// create a concrete one.
+pub const F = struct {
+    /// Initialize the USB clock to 48 MHz
+    ///
+    /// This requres that the system clock has been set up before hand
+    /// using the 12 MHz crystal.
+    pub fn usb_init_clk() void {
+        // Bring PLL_USB up to 48MHz. PLL_USB is clocked from refclk, which we've
+        // already moved over to the 12MHz XOSC. We just need to make it x4 that
+        // clock.
+        //
+        // PLL_USB out of reset
+        resets.reset(&.{.pll_usb});
+        // Configure it:
+        //
+        // RFDIV = 1
+        // FBDIV = 100 => FOUTVC0 = 1200 MHz
+        peripherals.PLL_USB.CS.modify(.{ .REFDIV = 1 });
+        peripherals.PLL_USB.FBDIV_INT.modify(.{ .FBDIV_INT = 100 });
+        peripherals.PLL_USB.PWR.modify(.{ .PD = 0, .VCOPD = 0 });
+        // Wait for lock
+        while (peripherals.PLL_USB.CS.read().LOCK == 0) {}
+        // Set up post dividers to enable output
+        //
+        // POSTDIV1 = POSTDIV2 = 5
+        // PLL_USB FOUT = 1200 MHz / 25 = 48 MHz
+        peripherals.PLL_USB.PRIM.modify(.{ .POSTDIV1 = 5, .POSTDIV2 = 5 });
+        peripherals.PLL_USB.PWR.modify(.{ .POSTDIVPD = 0 });
+        // Switch usbclk to be derived from PLLUSB
+        peripherals.CLOCKS.CLK_USB_CTRL.modify(.{ .AUXSRC = .{ .value = .clksrc_pll_usb } });
+
+        // We now have the stable 48MHz reference clock required for USB:
+    }
+
+    pub fn usb_init_device(device_config: *usb.DeviceConfiguration) void {
+        // Bring USB out of reset
+        resets.reset(&.{.usbctrl});
+
+        // Clear the control portion of DPRAM. This may not be necessary -- the
+        // datasheet is ambiguous -- but the C examples do it, and so do we.
+        peripherals.USBCTRL_DPRAM.SETUP_PACKET_LOW.write_raw(0);
+        peripherals.USBCTRL_DPRAM.SETUP_PACKET_HIGH.write_raw(0);
+
+        peripherals.USBCTRL_DPRAM.EP1_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP1_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP2_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP2_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP3_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP3_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP4_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP4_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP5_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP5_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP6_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP6_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP7_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP7_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP8_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP8_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP9_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP9_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP10_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP10_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP11_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP11_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP12_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP12_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP13_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP13_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP14_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP14_OUT_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP15_IN_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP15_OUT_CONTROL.write_raw(0);
+
+        peripherals.USBCTRL_DPRAM.EP0_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP0_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP1_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP1_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP2_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP2_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP3_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP3_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP4_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP4_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP5_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP5_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP6_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP6_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP7_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP7_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP8_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP8_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP9_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP9_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP10_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP10_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP11_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP11_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP12_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP12_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP13_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP13_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP14_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP14_OUT_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP15_IN_BUFFER_CONTROL.write_raw(0);
+        peripherals.USBCTRL_DPRAM.EP15_OUT_BUFFER_CONTROL.write_raw(0);
+
+        // Mux the controller to the onboard USB PHY. I was surprised that there are
+        // alternatives to this, but, there are.
+        peripherals.USBCTRL_REGS.USB_MUXING.modify(.{
+            .TO_PHY = 1,
+            // This bit is also set in the SDK example, without any discussion. It's
+            // undocumented (being named does not count as being documented).
+            .SOFTCON = 1,
+        });
+
+        // Force VBUS detect. Not all RP2040 boards wire up VBUS detect, which would
+        // let us detect being plugged into a host (the Pi Pico, to its credit,
+        // does). For maximum compatibility, we'll set the hardware to always
+        // pretend VBUS has been detected.
+        peripherals.USBCTRL_REGS.USB_PWR.modify(.{
+            .VBUS_DETECT = 1,
+            .VBUS_DETECT_OVERRIDE_EN = 1,
+        });
+
+        // Enable controller in device mode.
+        peripherals.USBCTRL_REGS.MAIN_CTRL.modify(.{
+            .CONTROLLER_EN = 1,
+            .HOST_NDEVICE = 0,
+        });
+
+        // Request to have an interrupt (which really just means setting a bit in
+        // the `buff_status` register) every time a buffer moves through EP0.
+        peripherals.USBCTRL_REGS.SIE_CTRL.modify(.{
+            .EP0_INT_1BUF = 1,
+        });
+
+        // Enable interrupts (bits set in the `ints` register) for other conditions
+        // we use:
+        peripherals.USBCTRL_REGS.INTE.modify(.{
+            // A buffer is done
+            .BUFF_STATUS = 1,
+            // The host has reset us
+            .BUS_RESET = 1,
+            // We've gotten a setup request on EP0
+            .SETUP_REQ = 1,
+        });
+
+        // setup endpoints
+        for (device_config.endpoints) |ep| {
+            // EP0 doesn't have an endpoint control index; only process the other
+            // endpoints here.
+            if (ep.endpoint_control_index) |epci| {
+                // We need to compute the offset from the base of USB SRAM to the
+                // buffer we're choosing, because that's how the peripheral do.
+                const buf_base = @ptrToInt(buffers.B.get(ep.data_buffer_index));
+                const dpram_base = @ptrToInt(peripherals.USBCTRL_DPRAM);
+                // The offset _should_ fit in a u16, but if we've gotten something
+                // wrong in the past few lines, a common symptom will be integer
+                // overflow producing a Very Large Number,
+                const dpram_offset = @intCast(u16, buf_base - dpram_base);
+
+                // Configure the endpoint!
+                modify_endpoint_control(epci, .{
+                    .ENABLE = 1,
+                    // Please set the corresponding bit in buff_status when a
+                    // buffer is done, thx.
+                    .INTERRUPT_PER_BUFF = 1,
+                    // Select bulk vs control (or interrupt as soon as implemented).
+                    .ENDPOINT_TYPE = .{ .raw = @intCast(u2, ep.descriptor.attributes) },
+                    // And, designate our buffer by its offset.
+                    .BUFFER_ADDRESS = dpram_offset,
+                });
+            }
+        }
+
+        // Present full-speed device by enabling pullup on DP. This is the point
+        // where the host will notice our presence.
+        peripherals.USBCTRL_REGS.SIE_CTRL.modify(.{ .PULLUP_EN = 1 });
+    }
+
+    /// Configures a given endpoint to send data (device-to-host, IN) when the host
+    /// next asks for it.
+    ///
+    /// The contents of `buffer` will be _copied_ into USB SRAM, so you can
+    /// reuse `buffer` immediately after this returns. No need to wait for the
+    /// packet to be sent.
+    pub fn usb_start_tx(
+        ep: *usb.EndpointConfiguration,
+        buffer: []const u8,
+    ) void {
+        // It is technically possible to support longer buffers but this demo
+        // doesn't bother.
+        // TODO: assert!(buffer.len() <= 64);
+        // You should only be calling this on IN endpoints.
+        // TODO: assert!(UsbDir::of_endpoint_addr(ep.descriptor.endpoint_address) == UsbDir::In);
+
+        // Copy the given data into the corresponding ep buffer
+        const epbuffer = buffers.B.get(ep.data_buffer_index);
+        _ = rom.memcpy(epbuffer[0..buffer.len], buffer);
+
+        // Configure the IN:
+        const np: u1 = if (ep.next_pid_1) 1 else 0;
+
+        // The AVAILABLE bit in the buffer control register should be set
+        // separately to the rest of the data in the buffer control register,
+        // so that the rest of the data in the buffer control register is
+        // accurate when the AVAILABLE bit is set.
+
+        // Write the buffer information to the buffer control register
+        modify_buffer_control(ep.buffer_control_index, .{
+            .PID_0 = np, // DATA0/1, depending
+            .FULL_0 = 1, // We have put data in
+            .LENGTH_0 = @intCast(u10, buffer.len), // There are this many bytes
+        });
+
+        // Nop for some clock cycles
+        // use volatile so the compiler doesn't optimize the nops away
+        asm volatile (
+            \\ nop
+            \\ nop
+            \\ nop
+        );
+
+        // Set available bit
+        modify_buffer_control(ep.buffer_control_index, .{
+            .AVAILABLE_0 = 1, // The data is for the computer to use now
+        });
+
+        ep.next_pid_1 = !ep.next_pid_1;
+    }
+
+    pub fn usb_start_rx(
+        ep: *usb.EndpointConfiguration,
+        len: usize,
+    ) void {
+        // It is technically possible to support longer buffers but this demo
+        // doesn't bother.
+        // TODO: assert!(len <= 64);
+        // You should only be calling this on OUT endpoints.
+        // TODO: assert!(UsbDir::of_endpoint_addr(ep.descriptor.endpoint_address) == UsbDir::Out);
+
+        // Check which DATA0/1 PID this endpoint is expecting next.
+        const np: u1 = if (ep.next_pid_1) 1 else 0;
+        // Configure the OUT:
+        modify_buffer_control(ep.buffer_control_index, .{
+            .PID_0 = np, // DATA0/1 depending
+            .FULL_0 = 0, // Buffer is NOT full, we want the computer to fill it
+            .AVAILABLE_0 = 1, // It is, however, available to be filled
+            .LENGTH_0 = @intCast(u10, len), // Up tho this many bytes
+        });
+
+        // Flip the DATA0/1 PID for the next receive
+        ep.next_pid_1 = !ep.next_pid_1;
+    }
+
+    /// Check which interrupt flags are set
+    pub fn get_interrupts() usb.InterruptStatus {
+        const ints = peripherals.USBCTRL_REGS.INTS.read();
+
+        return .{
+            .BuffStatus = if (ints.BUFF_STATUS == 1) true else false,
+            .BusReset = if (ints.BUS_RESET == 1) true else false,
+            .DevConnDis = if (ints.DEV_CONN_DIS == 1) true else false,
+            .DevSuspend = if (ints.DEV_SUSPEND == 1) true else false,
+            .DevResumeFromHost = if (ints.DEV_RESUME_FROM_HOST == 1) true else false,
+            .SetupReq = if (ints.SETUP_REQ == 1) true else false,
+        };
+    }
+
+    /// Returns a received USB setup packet
+    ///
+    /// Side effect: The setup request status flag will be cleared
+    ///
+    /// One can assume that this function is only called if the
+    /// setup request falg is set.
+    pub fn get_setup_packet() usb.SetupPacket {
+        // Clear the status flag (write-one-to-clear)
+        peripherals.USBCTRL_REGS.SIE_STATUS.modify(.{ .SETUP_REC = 1 });
+
+        // This assumes that the setup packet is arriving on EP0, our
+        // control endpoint. Which it should be. We don't have any other
+        // Control endpoints.
+
+        // Copy the setup packet out of its dedicated buffer at the base of
+        // USB SRAM. The PAC models this buffer as two 32-bit registers,
+        // which is, like, not _wrong_ but slightly awkward since it means
+        // we can't just treat it as bytes. Instead, copy it out to a byte
+        // array.
+        var setup_packet: [8]u8 = .{0} ** 8;
+        const spl: u32 = peripherals.USBCTRL_DPRAM.SETUP_PACKET_LOW.raw;
+        const sph: u32 = peripherals.USBCTRL_DPRAM.SETUP_PACKET_HIGH.raw;
+        _ = rom.memcpy(setup_packet[0..4], std.mem.asBytes(&spl));
+        _ = rom.memcpy(setup_packet[4..8], std.mem.asBytes(&sph));
+        // Reinterpret as setup packet
+        return std.mem.bytesToValue(usb.SetupPacket, &setup_packet);
+    }
+
+    /// Called on a bus reset interrupt
+    pub fn bus_reset() void {
+        // Acknowledge by writing the write-one-to-clear status bit.
+        peripherals.USBCTRL_REGS.SIE_STATUS.modify(.{ .BUS_RESET = 1 });
+        peripherals.USBCTRL_REGS.ADDR_ENDP.modify(.{ .ADDRESS = 0 });
+    }
+
+    pub fn set_address(addr: u7) void {
+        peripherals.USBCTRL_REGS.ADDR_ENDP.modify(.{ .ADDRESS = addr });
+    }
+
+    pub fn get_EPBIter(dc: *const usb.DeviceConfiguration) usb.EPBIter {
+        return .{
+            .bufbits = peripherals.USBCTRL_REGS.BUFF_STATUS.raw,
+            .device_config = dc,
+            .next = next,
+        };
+    }
+};
+
+// +++++++++++++++++++++++++++++++++++++++++++++++++
+// Utility functions
+// +++++++++++++++++++++++++++++++++++++++++++++++++
+
+/// Check if the corresponding buffer is available
+pub fn buffer_available(
+    ep: *usb.EndpointConfiguration,
+) bool {
+    const rbc = read_raw_buffer_control(ep.buffer_control_index);
+    // Bit 11 of the EPn_X_BUFFER_CONTROL register represents the AVAILABLE_0 flag
+    return ((rbc & 0x400) == 0);
+}
+
+pub fn modify_buffer_control(
+    i: usize,
+    fields: anytype,
+) void {
+    // haven't found a better way to handle this
+    switch (i) {
+        0 => peripherals.USBCTRL_DPRAM.EP0_IN_BUFFER_CONTROL.modify(fields),
+        1 => peripherals.USBCTRL_DPRAM.EP0_OUT_BUFFER_CONTROL.modify(fields),
+        2 => peripherals.USBCTRL_DPRAM.EP1_IN_BUFFER_CONTROL.modify(fields),
+        3 => peripherals.USBCTRL_DPRAM.EP1_OUT_BUFFER_CONTROL.modify(fields),
+        4 => peripherals.USBCTRL_DPRAM.EP2_IN_BUFFER_CONTROL.modify(fields),
+        5 => peripherals.USBCTRL_DPRAM.EP2_OUT_BUFFER_CONTROL.modify(fields),
+        6 => peripherals.USBCTRL_DPRAM.EP3_IN_BUFFER_CONTROL.modify(fields),
+        7 => peripherals.USBCTRL_DPRAM.EP3_OUT_BUFFER_CONTROL.modify(fields),
+        8 => peripherals.USBCTRL_DPRAM.EP4_IN_BUFFER_CONTROL.modify(fields),
+        9 => peripherals.USBCTRL_DPRAM.EP4_OUT_BUFFER_CONTROL.modify(fields),
+        10 => peripherals.USBCTRL_DPRAM.EP5_IN_BUFFER_CONTROL.modify(fields),
+        11 => peripherals.USBCTRL_DPRAM.EP5_OUT_BUFFER_CONTROL.modify(fields),
+        12 => peripherals.USBCTRL_DPRAM.EP6_IN_BUFFER_CONTROL.modify(fields),
+        13 => peripherals.USBCTRL_DPRAM.EP6_OUT_BUFFER_CONTROL.modify(fields),
+        14 => peripherals.USBCTRL_DPRAM.EP7_IN_BUFFER_CONTROL.modify(fields),
+        15 => peripherals.USBCTRL_DPRAM.EP7_OUT_BUFFER_CONTROL.modify(fields),
+        16 => peripherals.USBCTRL_DPRAM.EP8_IN_BUFFER_CONTROL.modify(fields),
+        17 => peripherals.USBCTRL_DPRAM.EP8_OUT_BUFFER_CONTROL.modify(fields),
+        18 => peripherals.USBCTRL_DPRAM.EP9_IN_BUFFER_CONTROL.modify(fields),
+        19 => peripherals.USBCTRL_DPRAM.EP9_OUT_BUFFER_CONTROL.modify(fields),
+        20 => peripherals.USBCTRL_DPRAM.EP10_IN_BUFFER_CONTROL.modify(fields),
+        21 => peripherals.USBCTRL_DPRAM.EP10_OUT_BUFFER_CONTROL.modify(fields),
+        22 => peripherals.USBCTRL_DPRAM.EP11_IN_BUFFER_CONTROL.modify(fields),
+        23 => peripherals.USBCTRL_DPRAM.EP11_OUT_BUFFER_CONTROL.modify(fields),
+        24 => peripherals.USBCTRL_DPRAM.EP12_IN_BUFFER_CONTROL.modify(fields),
+        25 => peripherals.USBCTRL_DPRAM.EP12_OUT_BUFFER_CONTROL.modify(fields),
+        26 => peripherals.USBCTRL_DPRAM.EP13_IN_BUFFER_CONTROL.modify(fields),
+        27 => peripherals.USBCTRL_DPRAM.EP13_OUT_BUFFER_CONTROL.modify(fields),
+        28 => peripherals.USBCTRL_DPRAM.EP14_IN_BUFFER_CONTROL.modify(fields),
+        29 => peripherals.USBCTRL_DPRAM.EP14_OUT_BUFFER_CONTROL.modify(fields),
+        30 => peripherals.USBCTRL_DPRAM.EP15_IN_BUFFER_CONTROL.modify(fields),
+        31 => peripherals.USBCTRL_DPRAM.EP15_OUT_BUFFER_CONTROL.modify(fields),
+        else => {}, // TODO: We'll just ignore it for now
+    }
+}
+
+pub fn read_raw_buffer_control(
+    i: usize,
+) u32 {
+    // haven't found a better way to handle this
+    return switch (i) {
+        0 => peripherals.USBCTRL_DPRAM.EP0_IN_BUFFER_CONTROL.raw,
+        1 => peripherals.USBCTRL_DPRAM.EP0_OUT_BUFFER_CONTROL.raw,
+        2 => peripherals.USBCTRL_DPRAM.EP1_IN_BUFFER_CONTROL.raw,
+        3 => peripherals.USBCTRL_DPRAM.EP1_OUT_BUFFER_CONTROL.raw,
+        4 => peripherals.USBCTRL_DPRAM.EP2_IN_BUFFER_CONTROL.raw,
+        5 => peripherals.USBCTRL_DPRAM.EP2_OUT_BUFFER_CONTROL.raw,
+        6 => peripherals.USBCTRL_DPRAM.EP3_IN_BUFFER_CONTROL.raw,
+        7 => peripherals.USBCTRL_DPRAM.EP3_OUT_BUFFER_CONTROL.raw,
+        8 => peripherals.USBCTRL_DPRAM.EP4_IN_BUFFER_CONTROL.raw,
+        9 => peripherals.USBCTRL_DPRAM.EP4_OUT_BUFFER_CONTROL.raw,
+        10 => peripherals.USBCTRL_DPRAM.EP5_IN_BUFFER_CONTROL.raw,
+        11 => peripherals.USBCTRL_DPRAM.EP5_OUT_BUFFER_CONTROL.raw,
+        12 => peripherals.USBCTRL_DPRAM.EP6_IN_BUFFER_CONTROL.raw,
+        13 => peripherals.USBCTRL_DPRAM.EP6_OUT_BUFFER_CONTROL.raw,
+        14 => peripherals.USBCTRL_DPRAM.EP7_IN_BUFFER_CONTROL.raw,
+        15 => peripherals.USBCTRL_DPRAM.EP7_OUT_BUFFER_CONTROL.raw,
+        16 => peripherals.USBCTRL_DPRAM.EP8_IN_BUFFER_CONTROL.raw,
+        17 => peripherals.USBCTRL_DPRAM.EP8_OUT_BUFFER_CONTROL.raw,
+        18 => peripherals.USBCTRL_DPRAM.EP9_IN_BUFFER_CONTROL.raw,
+        19 => peripherals.USBCTRL_DPRAM.EP9_OUT_BUFFER_CONTROL.raw,
+        20 => peripherals.USBCTRL_DPRAM.EP10_IN_BUFFER_CONTROL.raw,
+        21 => peripherals.USBCTRL_DPRAM.EP10_OUT_BUFFER_CONTROL.raw,
+        22 => peripherals.USBCTRL_DPRAM.EP11_IN_BUFFER_CONTROL.raw,
+        23 => peripherals.USBCTRL_DPRAM.EP11_OUT_BUFFER_CONTROL.raw,
+        24 => peripherals.USBCTRL_DPRAM.EP12_IN_BUFFER_CONTROL.raw,
+        25 => peripherals.USBCTRL_DPRAM.EP12_OUT_BUFFER_CONTROL.raw,
+        26 => peripherals.USBCTRL_DPRAM.EP13_IN_BUFFER_CONTROL.raw,
+        27 => peripherals.USBCTRL_DPRAM.EP13_OUT_BUFFER_CONTROL.raw,
+        28 => peripherals.USBCTRL_DPRAM.EP14_IN_BUFFER_CONTROL.raw,
+        29 => peripherals.USBCTRL_DPRAM.EP14_OUT_BUFFER_CONTROL.raw,
+        30 => peripherals.USBCTRL_DPRAM.EP15_IN_BUFFER_CONTROL.raw,
+        31 => peripherals.USBCTRL_DPRAM.EP15_OUT_BUFFER_CONTROL.raw,
+        else => 0, // TODO: We'll just return 0 for now
+    };
+}
+
+pub fn modify_endpoint_control(
+    epci: usize,
+    fields: anytype,
+) void {
+    // haven't found a better way to handle this
+    switch (epci) {
+        1 => peripherals.USBCTRL_DPRAM.EP1_IN_CONTROL.modify(fields),
+        2 => peripherals.USBCTRL_DPRAM.EP1_OUT_CONTROL.modify(fields),
+        3 => peripherals.USBCTRL_DPRAM.EP2_IN_CONTROL.modify(fields),
+        4 => peripherals.USBCTRL_DPRAM.EP2_OUT_CONTROL.modify(fields),
+        5 => peripherals.USBCTRL_DPRAM.EP3_IN_CONTROL.modify(fields),
+        6 => peripherals.USBCTRL_DPRAM.EP3_OUT_CONTROL.modify(fields),
+        7 => peripherals.USBCTRL_DPRAM.EP4_IN_CONTROL.modify(fields),
+        8 => peripherals.USBCTRL_DPRAM.EP4_OUT_CONTROL.modify(fields),
+        9 => peripherals.USBCTRL_DPRAM.EP5_IN_CONTROL.modify(fields),
+        10 => peripherals.USBCTRL_DPRAM.EP5_OUT_CONTROL.modify(fields),
+        11 => peripherals.USBCTRL_DPRAM.EP6_IN_CONTROL.modify(fields),
+        12 => peripherals.USBCTRL_DPRAM.EP6_OUT_CONTROL.modify(fields),
+        13 => peripherals.USBCTRL_DPRAM.EP7_IN_CONTROL.modify(fields),
+        14 => peripherals.USBCTRL_DPRAM.EP7_OUT_CONTROL.modify(fields),
+        15 => peripherals.USBCTRL_DPRAM.EP8_IN_CONTROL.modify(fields),
+        16 => peripherals.USBCTRL_DPRAM.EP8_OUT_CONTROL.modify(fields),
+        17 => peripherals.USBCTRL_DPRAM.EP9_IN_CONTROL.modify(fields),
+        18 => peripherals.USBCTRL_DPRAM.EP9_OUT_CONTROL.modify(fields),
+        19 => peripherals.USBCTRL_DPRAM.EP10_IN_CONTROL.modify(fields),
+        20 => peripherals.USBCTRL_DPRAM.EP10_OUT_CONTROL.modify(fields),
+        21 => peripherals.USBCTRL_DPRAM.EP11_IN_CONTROL.modify(fields),
+        22 => peripherals.USBCTRL_DPRAM.EP11_OUT_CONTROL.modify(fields),
+        23 => peripherals.USBCTRL_DPRAM.EP12_IN_CONTROL.modify(fields),
+        24 => peripherals.USBCTRL_DPRAM.EP12_OUT_CONTROL.modify(fields),
+        25 => peripherals.USBCTRL_DPRAM.EP13_IN_CONTROL.modify(fields),
+        26 => peripherals.USBCTRL_DPRAM.EP13_OUT_CONTROL.modify(fields),
+        27 => peripherals.USBCTRL_DPRAM.EP14_IN_CONTROL.modify(fields),
+        28 => peripherals.USBCTRL_DPRAM.EP14_OUT_CONTROL.modify(fields),
+        29 => peripherals.USBCTRL_DPRAM.EP15_IN_CONTROL.modify(fields),
+        30 => peripherals.USBCTRL_DPRAM.EP15_OUT_CONTROL.modify(fields),
+        else => {}, // TODO: We'll just ignore it for now
+    }
+}
+
+// -----------------------------------------------------------
+
+pub fn next(self: *usb.EPBIter) ?usb.EPB {
+    if (self.last_bit) |lb| {
+        // Acknowledge the last handled buffer
+        peripherals.USBCTRL_REGS.BUFF_STATUS.write_raw(lb);
+        self.last_bit = null;
+    }
+    // All input buffers handled?
+    if (self.bufbits == 0) return null;
+
+    // Who's still outstanding? Find their bit index by counting how
+    // many LSBs are zero.
+    var lowbit_index: u5 = 0;
+    while ((self.bufbits >> lowbit_index) & 0x01 == 0) : (lowbit_index += 1) {}
+    // Remove their bit from our set.
+    const lowbit = @intCast(u32, 1) << lowbit_index;
+    self.last_bit = lowbit;
+    self.bufbits ^= lowbit;
+
+    // Here we exploit knowledge of the ordering of buffer control
+    // registers in the peripheral. Each endpoint has a pair of
+    // registers, so we can determine the endpoint number by:
+    const epnum = @intCast(u8, lowbit_index >> 1);
+    // Of the pair, the IN endpoint comes first, followed by OUT, so
+    // we can get the direction by:
+    const dir = if (lowbit_index & 1 == 0) usb.Dir.In else usb.Dir.Out;
+
+    const ep_addr = dir.endpoint(epnum);
+    // Process the buffer-done event.
+
+    // Process the buffer-done event.
+    //
+    // Scan the device table to figure out which endpoint struct
+    // corresponds to this address. We could use a smarter
+    // method here, but in practice, the number of endpoints is
+    // small so a linear scan doesn't kill us.
+    var endpoint: ?*usb.EndpointConfiguration = null;
+    for (self.device_config.endpoints) |ep| {
+        if (ep.descriptor.endpoint_address == ep_addr) {
+            endpoint = ep;
+            break;
+        }
+    }
+    // Buffer event for unknown EP?!
+    // TODO: if (endpoint == null) return EPBError.UnknownEndpoint;
+    // Read the buffer control register to check status.
+    const bc = read_raw_buffer_control(endpoint.?.buffer_control_index);
+
+    // We should only get here if we've been notified that
+    // the buffer is ours again. This is indicated by the hw
+    // _clearing_ the AVAILABLE bit.
+    //
+    // This ensures that we can return a shared reference to
+    // the databuffer contents without races.
+    // TODO: if ((bc & (1 << 10)) == 1) return EPBError.NotAvailable;
+
+    // Cool. Checks out.
+
+    // Get a pointer to the buffer in USB SRAM. This is the
+    // buffer _contents_. See the safety comments below.
+    const epbuffer = buffers.B.get(endpoint.?.data_buffer_index);
+
+    // Get the actual length of the data, which may be less
+    // than the buffer size.
+    const len = @intCast(usize, bc & 0x3ff);
+
+    // Copy the data from SRAM
+    return usb.EPB{
+        .endpoint = endpoint.?,
+        .buffer = epbuffer[0..len],
+    };
+}

From 5e5e11c80fb754e985c03a4e1051b674bb5f3177 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 25 Apr 2023 23:41:00 -0700
Subject: [PATCH 134/286] update microzig (#16)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index dd491cc84..658648b86 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab
+Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1

From a2fccb3c73e3ac01ec1adcdc285943d1f1a651c6 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 25 Apr 2023 23:41:08 -0700
Subject: [PATCH 135/286] update microzig (#48)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index dd491cc84..658648b86 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab
+Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1

From 4e2cdae13e35438ff72dcdc85c8bb4b51b46bd13 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 25 Apr 2023 23:41:16 -0700
Subject: [PATCH 136/286] update microzig (#15)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index dd491cc84..658648b86 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab
+Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1

From 734ed2f5d8d1f7c06573457ef2c689cf198a902c Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 25 Apr 2023 23:41:24 -0700
Subject: [PATCH 137/286] update microzig (#16)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index dd491cc84..658648b86 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab
+Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1

From b0642a90d88e999e0780951e926ac7d3c4f8b5a4 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 25 Apr 2023 23:41:40 -0700
Subject: [PATCH 138/286] update microzig (#15)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index dd491cc84..658648b86 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab
+Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1

From 78da6fd10c59c72fd3bc70afa49d8e21abd38067 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 25 Apr 2023 23:41:51 -0700
Subject: [PATCH 139/286] update microzig (#15)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index dd491cc84..658648b86 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab
+Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1

From 6a5f42a15c9ae5571b19dc23529c24c8446c0359 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 25 Apr 2023 23:41:59 -0700
Subject: [PATCH 140/286] update microzig (#15)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index dd491cc84..658648b86 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit dd491cc84fe034cb07f5b6cc6aa486d97e0ef7ab
+Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1

From a7f71cb0ca8a1c3909f9e00f6662e1d6b860f9d5 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 26 Apr 2023 00:29:05 -0700
Subject: [PATCH 141/286] update microzig (#17)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 658648b86..b5edf6da6 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1
+Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d

From cc882413bbc170789f71b634fa852f3aca0e935d Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 26 Apr 2023 00:29:15 -0700
Subject: [PATCH 142/286] update microzig (#17)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 658648b86..b5edf6da6 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1
+Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d

From c9943f54ef889e9be97781f8a379474743d33452 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 26 Apr 2023 00:29:22 -0700
Subject: [PATCH 143/286] update microzig (#17)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 658648b86..b5edf6da6 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1
+Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d

From bc4582cf4de165cf85ec8337a96dc9570129a629 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 26 Apr 2023 00:29:37 -0700
Subject: [PATCH 144/286] update microzig (#50)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 658648b86..b5edf6da6 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1
+Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d

From 15d9bae086de1a4c60ec9364cf636d71bf4f250d Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 26 Apr 2023 00:29:42 -0700
Subject: [PATCH 145/286] update microzig (#17)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 658648b86..b5edf6da6 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1
+Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d

From e8cf979268d7194d9f305fb0978243c14a57f024 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 26 Apr 2023 00:29:50 -0700
Subject: [PATCH 146/286] Update microzig (#18)

* update microzig

* update cpu

---------

Co-authored-by: mattnite 
---
 deps/microzig                | 2 +-
 src/cpus/espressif-riscv.zig | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/deps/microzig b/deps/microzig
index 658648b86..b5edf6da6 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1
+Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d
diff --git a/src/cpus/espressif-riscv.zig b/src/cpus/espressif-riscv.zig
index e20072daa..dc2edb769 100644
--- a/src/cpus/espressif-riscv.zig
+++ b/src/cpus/espressif-riscv.zig
@@ -29,11 +29,11 @@ pub inline fn clearStatusBit(comptime reg: StatusRegister, bits: u32) void {
     );
 }
 
-pub inline fn cli() void {
+pub inline fn disable_interrupts() void {
     clearStatusBit(.mstatus, 0x08);
 }
 
-pub inline fn sei() void {
+pub inline fn enable_interrupts() void {
     setStatusBit(.mstatus, 0x08);
 }
 
@@ -62,7 +62,7 @@ pub const startup_logic = struct {
     extern fn microzig_main() noreturn;
 
     export fn _start() linksection("microzig_flash_start") callconv(.Naked) noreturn {
-        microzig.cpu.cli();
+        microzig.cpu.disable_interrupts();
         asm volatile ("mv sp, %[eos]"
             :
             : [eos] "r" (@as(u32, microzig.config.end_of_stack)),

From b71c07281825713690af8f0b8293e2fbef7c94da Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 26 Apr 2023 00:30:00 -0700
Subject: [PATCH 147/286] update microzig (#18)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 658648b86..b5edf6da6 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 658648b86ba63762ac45665abe0a06ec279225b1
+Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d

From c1c19d221e85845e3874d39e8bc7597f54f59237 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 26 Apr 2023 01:02:09 -0700
Subject: [PATCH 148/286] Gpio api (#51)

* improve GPIO API

* fix test, update microzig

* first DMA functions, new abstraction for enumerating peripherals

* rebase main

* fix call to reset()
---
 examples/adc.zig                    |  18 +--
 examples/blinky_core1.zig           |  10 +-
 examples/flash_program.zig          |  16 +--
 examples/gpio_clk.zig               |   9 +-
 examples/random.zig                 |  16 +--
 examples/spi_master.zig             |   3 +-
 examples/squarewave.zig             | 103 +++++++++------
 examples/uart.zig                   |  20 ++-
 examples/usb_device.zig             |  18 ++-
 examples/usb_hid.zig                |  18 ++-
 src/hal.zig                         |  34 +++--
 src/hal/adc.zig                     |   5 +-
 src/hal/dma.zig                     | 131 ++++++++++++++++++
 src/hal/gpio.zig                    | 198 ++++++++++++++++++----------
 src/hal/hw.zig                      |  37 +++++-
 src/hal/pins.zig                    |  27 ++--
 src/hal/pio.zig                     | 156 +++++++++++++---------
 src/hal/pio/assembler.zig           |   4 +-
 src/hal/pio/assembler/encoder.zig   |  17 ++-
 src/hal/pio/assembler/tokenizer.zig |   8 +-
 src/hal/pll.zig                     |   2 +-
 src/hal/resets.zig                  | 150 ++++++++++++++++-----
 src/hal/spi.zig                     |  50 +++----
 src/hal/uart.zig                    |  55 ++++----
 src/hal/usb.zig                     |   4 +-
 25 files changed, 717 insertions(+), 392 deletions(-)
 create mode 100644 src/hal/dma.zig

diff --git a/examples/adc.zig b/examples/adc.zig
index 5d8f0c3eb..b6d6bf4ff 100644
--- a/examples/adc.zig
+++ b/examples/adc.zig
@@ -3,26 +3,22 @@
 const std = @import("std");
 const microzig = @import("microzig");
 const rp2040 = microzig.hal;
+const gpio = rp2040.gpio;
 const adc = rp2040.adc;
 const time = rp2040.time;
 
 const temp_sensor: adc.Input = .temperature_sensor;
-const uart_id = 0;
+const uart = rp2040.uart.num(0);
 const baud_rate = 115200;
-const uart_tx_pin = 0;
-const uart_rx_pin = 1;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
 
 pub const std_options = struct {
     pub const logFn = rp2040.uart.log;
 };
 
-pub fn init() void {
-    rp2040.clock_config.apply();
-    rp2040.gpio.reset();
-    adc.init();
-    temp_sensor.init();
-
-    const uart = rp2040.uart.UART.init(uart_id, .{
+pub fn main() void {
+    uart.apply(.{
         .baud_rate = baud_rate,
         .tx_pin = uart_tx_pin,
         .rx_pin = uart_rx_pin,
@@ -30,9 +26,7 @@ pub fn init() void {
     });
 
     rp2040.uart.init_logger(uart);
-}
 
-pub fn main() void {
     while (true) : (time.sleep_ms(1000)) {
         const sample = temp_sensor.read();
         std.log.info("temp value: {}", .{sample});
diff --git a/examples/blinky_core1.zig b/examples/blinky_core1.zig
index b3fdd04da..64f067468 100644
--- a/examples/blinky_core1.zig
+++ b/examples/blinky_core1.zig
@@ -6,21 +6,19 @@ const gpio = rp2040.gpio;
 const time = rp2040.time;
 const multicore = rp2040.multicore;
 
-const led = 25;
+const led = gpio.num(25);
 
 fn core1() void {
     while (true) {
-        gpio.put(led, 1);
+        led.put(1);
         time.sleep_ms(250);
-        gpio.put(led, 0);
+        led.put(0);
         time.sleep_ms(250);
     }
 }
 
 pub fn main() !void {
-    gpio.init(led);
-    gpio.set_direction(led, .out);
-
+    led.set_direction(.out);
     multicore.launch_core1(core1);
 
     while (true) {
diff --git a/examples/flash_program.zig b/examples/flash_program.zig
index 2fc5cc097..a2999c9d8 100644
--- a/examples/flash_program.zig
+++ b/examples/flash_program.zig
@@ -7,11 +7,11 @@ const time = rp2040.time;
 const gpio = rp2040.gpio;
 const clocks = rp2040.clocks;
 
-const led = 25;
-const uart_id = 0;
+const led = gpio.num(25);
+const uart = rp2040.uart.num(0);
 const baud_rate = 115200;
-const uart_tx_pin = 0;
-const uart_rx_pin = 1;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
 
 const flash_target_offset: u32 = 256 * 1024;
 const flash_target_contents = @intToPtr([*]const u8, rp2040.flash.XIP_BASE + flash_target_offset);
@@ -28,12 +28,10 @@ pub const std_options = struct {
 };
 
 pub fn main() !void {
-    gpio.reset();
-    gpio.init(led);
-    gpio.set_direction(led, .out);
-    gpio.put(led, 1);
+    led.set_direction(.out);
+    led.put(1);
 
-    const uart = rp2040.uart.UART.init(uart_id, .{
+    uart.apply(.{
         .baud_rate = baud_rate,
         .tx_pin = uart_tx_pin,
         .rx_pin = uart_rx_pin,
diff --git a/examples/gpio_clk.zig b/examples/gpio_clk.zig
index e66761c3b..dd2810242 100644
--- a/examples/gpio_clk.zig
+++ b/examples/gpio_clk.zig
@@ -4,18 +4,13 @@ const rp2040 = microzig.hal;
 const gpio = rp2040.gpio;
 const clocks = rp2040.clocks;
 
-const gpout0_pin = 21;
+const gpout0_pin = gpio.num(21);
 const clock_config = clocks.GlobalConfiguration.init(.{
     .sys = .{ .source = .src_xosc },
     .gpout0 = .{ .source = .clk_sys },
 });
 
-pub fn init() void {
-    clock_config.apply();
-    gpio.reset();
-}
-
 pub fn main() !void {
-    gpio.set_function(gpout0_pin, .gpck);
+    gpout0_pin.set_function(.gpck);
     while (true) {}
 }
diff --git a/examples/random.zig b/examples/random.zig
index dbf00d5f0..0645839d1 100644
--- a/examples/random.zig
+++ b/examples/random.zig
@@ -10,11 +10,11 @@ const gpio = rp2040.gpio;
 const clocks = rp2040.clocks;
 const rand = rp2040.rand;
 
-const led = 25;
-const uart_id = 0;
+const led = gpio.num(25);
+const uart = rp2040.uart.num(0);
 const baud_rate = 115200;
-const uart_tx_pin = 0;
-const uart_rx_pin = 1;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
 
 pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
     std.log.err("panic: {s}", .{message});
@@ -28,12 +28,10 @@ pub const std_options = struct {
 };
 
 pub fn main() !void {
-    gpio.reset();
-    gpio.init(led);
-    gpio.set_direction(led, .out);
-    gpio.put(led, 1);
+    led.set_direction(.out);
+    led.put(1);
 
-    const uart = rp2040.uart.UART.init(uart_id, .{
+    uart.apply(.{
         .baud_rate = baud_rate,
         .tx_pin = uart_tx_pin,
         .rx_pin = uart_rx_pin,
diff --git a/examples/spi_master.zig b/examples/spi_master.zig
index ba1c0c2db..c160fee96 100644
--- a/examples/spi_master.zig
+++ b/examples/spi_master.zig
@@ -8,11 +8,12 @@ const clocks = rp2040.clocks;
 const peripherals = microzig.chip.peripherals;
 
 const BUF_LEN = 0x100;
+const spi = rp2040.spi.num(0);
 
 // Communicate with another RP2040 over spi
 // Slave implementation: https://github.com/raspberrypi/pico-examples/blob/master/spi/spi_master_slave/spi_slave/spi_slave.c
 pub fn main() !void {
-    const spi = rp2040.spi.SPI.init(0, .{
+    spi.apply(.{
         .clock_config = rp2040.clock_config,
     });
     var out_buf: [BUF_LEN]u8 = .{ 0xAA, 0xBB, 0xCC, 0xDD } ** (BUF_LEN / 4);
diff --git a/examples/squarewave.zig b/examples/squarewave.zig
index 74370003c..0564b6259 100644
--- a/examples/squarewave.zig
+++ b/examples/squarewave.zig
@@ -6,57 +6,76 @@ const gpio = rp2040.gpio;
 const Pio = rp2040.pio.Pio;
 const StateMachine = rp2040.pio.StateMachine;
 
-const squarewave_program = (rp2040.pio.assemble(
+const squarewave_program = rp2040.pio.assemble(
+    \\;
+    \\; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+    \\;
+    \\; SPDX-License-Identifier: BSD-3-Clause
+    \\;
     \\.program squarewave
     \\    set pindirs, 1   ; Set pin to output
     \\again:
     \\    set pins, 1 [1]  ; Drive pin high and then delay for one cycle
     \\    set pins, 0      ; Drive pin low
     \\    jmp again        ; Set PC to label `again`
-, .{}) catch
-    @panic("failed to assemble program"))
-    .get_program_by_name("squarewave");
+, .{}).get_program_by_name("squarewave");
+
+// Pick one PIO instance arbitrarily. We're also arbitrarily picking state
+// machine 0 on this PIO instance (the state machines are numbered 0 to 3
+// inclusive).
+const pio: Pio = .pio0;
+const sm: StateMachine = .sm0;
 
 pub fn main() void {
-    gpio.reset();
-    // Pick one PIO instance arbitrarily. We're also arbitrarily picking state
-    // machine 0 on this PIO instance (the state machines are numbered 0 to 3
-    // inclusive).
-    const pio: Pio = .pio0;
-    const sm: StateMachine = .sm0;
-
-    // Load the assembled program directly into the PIO's instruction memory.
-    // Each PIO instance has a 32-slot instruction memory, which all 4 state
-    // machines can see. The system has write-only access.
-    for (squarewave_program.instructions, 0..) |insn, i|
-        pio.get_instruction_memory()[i] = insn;
-
-    // Configure state machine 0 to run at sysclk/2.5. The state machines can
-    // run as fast as one instruction per clock cycle, but we can scale their
-    // speed down uniformly to meet some precise frequency target, e.g. for a
-    // UART baud rate. This register has 16 integer divisor bits and 8
-    // fractional divisor bits.
-    pio.sm_set_clkdiv(sm, .{
-        .int = 2,
-        .frac = 0x80,
-    });
-
-    // There are five pin mapping groups (out, in, set, side-set, jmp pin)
-    // which are used by different instructions or in different circumstances.
-    // Here we're just using SET instructions. Configure state machine 0 SETs
-    // to affect GPIO 0 only; then configure GPIO0 to be controlled by PIO0,
-    // as opposed to e.g. the processors.
-    pio.gpio_init(0);
-    pio.sm_set_pin_mappings(sm, .{
-        .out = .{
-            .base = 0,
-            .count = 1,
+    pio.gpio_init(gpio.num(2));
+    pio.sm_load_and_start_program(sm, squarewave_program, .{
+        .clkdiv = rp2040.pio.ClkDivOptions.from_float(125),
+        .pin_mappings = .{
+            .set = .{
+                .base = 2,
+                .count = 1,
+            },
         },
-    });
+    }) catch unreachable;
 
-    // Set the state machine running. The PIO CTRL register is global within a
-    // PIO instance, so you can start/stop multiple state machines
-    // simultaneously. We're using the register's hardware atomic set alias to
-    // make one bit high without doing a read-modify-write on the register.
     pio.sm_set_enabled(sm, true);
+
+    while (true) {}
+
+    //// Load the assembled program directly into the PIO's instruction memory.
+    //// Each PIO instance has a 32-slot instruction memory, which all 4 state
+    //// machines can see. The system has write-only access.
+    //for (squarewave_program.instructions, 0..) |insn, i|
+    //    pio.get_instruction_memory()[i] = insn;
+
+    //// Configure state machine 0 to run at sysclk/2.5. The state machines can
+    //// run as fast as one instruction per clock cycle, but we can scale their
+    //// speed down uniformly to meet some precise frequency target, e.g. for a
+    //// UART baud rate. This register has 16 integer divisor bits and 8
+    //// fractional divisor bits.
+    //pio.sm_set_clkdiv(sm, .{
+    //    .int = 2,
+    //    .frac = 0x80,
+    //});
+
+    //// There are five pin mapping groups (out, in, set, side-set, jmp pin)
+    //// which are used by different instructions or in different circumstances.
+    //// Here we're just using SET instructions. Configure state machine 0 SETs
+    //// to affect GPIO 0 only; then configure GPIO0 to be controlled by PIO0,
+    //// as opposed to e.g. the processors.
+    //pio.gpio_init(2);
+    //pio.sm_set_pin_mappings(sm, .{
+    //    .out = .{
+    //        .base = 2,
+    //        .count = 1,
+    //    },
+    //});
+
+    //// Set the state machine running. The PIO CTRL register is global within a
+    //// PIO instance, so you can start/stop multiple state machines
+    //// simultaneously. We're using the register's hardware atomic set alias to
+    //// make one bit high without doing a read-modify-write on the register.
+    //pio.sm_set_enabled(sm, true);
+
+    //while (true) {}
 }
diff --git a/examples/uart.zig b/examples/uart.zig
index 57cf1c49f..6be3b3869 100644
--- a/examples/uart.zig
+++ b/examples/uart.zig
@@ -6,11 +6,11 @@ const time = rp2040.time;
 const gpio = rp2040.gpio;
 const clocks = rp2040.clocks;
 
-const led = 25;
-const uart_id = 0;
+const led = gpio.num(25);
+const uart = rp2040.uart.num(0);
 const baud_rate = 115200;
-const uart_tx_pin = 0;
-const uart_rx_pin = 1;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
 
 pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
     std.log.err("panic: {s}", .{message});
@@ -24,12 +24,10 @@ pub const std_options = struct {
 };
 
 pub fn main() !void {
-    gpio.reset();
-    gpio.init(led);
-    gpio.set_direction(led, .out);
-    gpio.put(led, 1);
+    led.set_direction(.out);
+    led.put(1);
 
-    const uart = rp2040.uart.UART.init(uart_id, .{
+    uart.apply(.{
         .baud_rate = baud_rate,
         .tx_pin = uart_tx_pin,
         .rx_pin = uart_rx_pin,
@@ -40,11 +38,11 @@ pub fn main() !void {
 
     var i: u32 = 0;
     while (true) : (i += 1) {
-        gpio.put(led, 1);
+        led.put(1);
         std.log.info("what {}", .{i});
         time.sleep_ms(500);
 
-        gpio.put(led, 0);
+        led.put(0);
         time.sleep_ms(500);
     }
 }
diff --git a/examples/usb_device.zig b/examples/usb_device.zig
index c86d5e140..3395286cd 100644
--- a/examples/usb_device.zig
+++ b/examples/usb_device.zig
@@ -8,11 +8,11 @@ const gpio = rp2040.gpio;
 const clocks = rp2040.clocks;
 const usb = rp2040.usb;
 
-const led = 25;
-const uart_id = 0;
+const led = gpio.num(25);
+const uart = rp2040.uart.num(0);
 const baud_rate = 115200;
-const uart_tx_pin = 0;
-const uart_rx_pin = 1;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
 
 // First we define two callbacks that will be used by the endpoints we define next...
 fn ep1_in_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
@@ -138,12 +138,10 @@ pub const std_options = struct {
 };
 
 pub fn main() !void {
-    gpio.reset();
-    gpio.init(led);
-    gpio.set_direction(led, .out);
-    gpio.put(led, 1);
+    led.set_direction(.out);
+    led.put(1);
 
-    const uart = rp2040.uart.UART.init(uart_id, .{
+    uart.apply(.{
         .baud_rate = baud_rate,
         .tx_pin = uart_tx_pin,
         .rx_pin = uart_rx_pin,
@@ -167,7 +165,7 @@ pub fn main() !void {
         new = time.get_time_since_boot().us_since_boot;
         if (new - old > 500000) {
             old = new;
-            gpio.toggle(led);
+            led.toggle();
         }
     }
 }
diff --git a/examples/usb_hid.zig b/examples/usb_hid.zig
index 633add74f..051ad746c 100644
--- a/examples/usb_hid.zig
+++ b/examples/usb_hid.zig
@@ -8,11 +8,11 @@ const gpio = rp2040.gpio;
 const clocks = rp2040.clocks;
 const usb = rp2040.usb;
 
-const led = 25;
-const uart_id = 0;
+const led = gpio.num(25);
+const uart = rp2040.uart.num(0);
 const baud_rate = 115200;
-const uart_tx_pin = 0;
-const uart_rx_pin = 1;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
 
 // First we define two callbacks that will be used by the endpoints we define next...
 fn ep1_in_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
@@ -153,12 +153,10 @@ pub const std_options = struct {
 };
 
 pub fn main() !void {
-    gpio.reset();
-    gpio.init(led);
-    gpio.set_direction(led, .out);
-    gpio.put(led, 1);
+    led.set_direction(.out);
+    led.put(1);
 
-    const uart = rp2040.uart.UART.init(uart_id, .{
+    uart.apply(.{
         .baud_rate = baud_rate,
         .tx_pin = uart_tx_pin,
         .rx_pin = uart_rx_pin,
@@ -182,7 +180,7 @@ pub fn main() !void {
         new = time.get_time_since_boot().us_since_boot;
         if (new - old > 500000) {
             old = new;
-            gpio.toggle(led);
+            led.toggle();
         }
     }
 }
diff --git a/src/hal.zig b/src/hal.zig
index c9ac98639..89e2b58a9 100644
--- a/src/hal.zig
+++ b/src/hal.zig
@@ -3,21 +3,22 @@ const microzig = @import("microzig");
 const SIO = microzig.chip.peripherals.SIO;
 
 pub const adc = @import("hal/adc.zig");
-pub const pins = @import("hal/pins.zig");
-pub const gpio = @import("hal/gpio.zig");
 pub const clocks = @import("hal/clocks.zig");
+pub const dma = @import("hal/dma.zig");
+pub const flash = @import("hal/flash.zig");
+pub const gpio = @import("hal/gpio.zig");
+pub const irq = @import("hal/irq.zig");
 pub const multicore = @import("hal/multicore.zig");
-pub const time = @import("hal/time.zig");
-pub const uart = @import("hal/uart.zig");
+pub const pins = @import("hal/pins.zig");
+pub const pio = @import("hal/pio.zig");
 pub const pwm = @import("hal/pwm.zig");
-pub const spi = @import("hal/spi.zig");
+pub const rand = @import("hal/random.zig");
 pub const resets = @import("hal/resets.zig");
-pub const irq = @import("hal/irq.zig");
 pub const rom = @import("hal/rom.zig");
-pub const flash = @import("hal/flash.zig");
-pub const pio = @import("hal/pio.zig");
+pub const spi = @import("hal/spi.zig");
+pub const time = @import("hal/time.zig");
+pub const uart = @import("hal/uart.zig");
 pub const usb = @import("hal/usb.zig");
-pub const rand = @import("hal/random.zig");
 
 pub const clock_config = clocks.GlobalConfiguration.init(.{
     .ref = .{ .source = .src_xosc },
@@ -32,7 +33,22 @@ pub const clock_config = clocks.GlobalConfiguration.init(.{
 });
 
 pub fn init() void {
+    // Reset all peripherals to put system into a known state, - except
+    // for QSPI pads and the XIP IO bank, as this is fatal if running from
+    // flash - and the PLLs, as this is fatal if clock muxing has not been
+    // reset on this boot - and USB, syscfg, as this disturbs USB-to-SWD
+    // on core 1
+    resets.reset_block(resets.masks.init);
+
+    // Remove reset from peripherals which are clocked only by clk_sys and
+    // clk_ref. Other peripherals stay in reset until we've configured
+    // clocks.
+    resets.unreset_block_wait(resets.masks.clocked_by_sys_and_ref);
+
     clock_config.apply();
+
+    // Peripheral clocks should now all be running
+    resets.unreset_block_wait(resets.masks.all);
 }
 
 pub fn get_cpu_id() u32 {
diff --git a/src/hal/adc.zig b/src/hal/adc.zig
index ba293b096..2f6b96b4a 100644
--- a/src/hal/adc.zig
+++ b/src/hal/adc.zig
@@ -43,9 +43,9 @@ pub const Input = enum(u3) {
         switch (input) {
             .temperature_sensor => set_temp_sensor_enabled(true),
             else => {
-                const gpio_num = @as(u32, @enumToInt(input)) + 26;
+                const pin = gpio.num(@as(u5, @enumToInt(input)) + 26);
+                pin.set_function(.null);
 
-                gpio.set_function(gpio_num, .null);
                 // TODO: implement these, otherwise adc isn't going to work.
                 //gpio.disablePulls(gpio_num);
                 //gpio.setInputEnabled(gpio_num, false);
@@ -105,7 +105,6 @@ pub const InputMask = InputMask: {
 
 /// Initialize ADC hardware
 pub fn init() void {
-    resets.reset(&.{.adc});
     ADC.CS.write(.{
         .EN = 1,
         .TS_EN = 0,
diff --git a/src/hal/dma.zig b/src/hal/dma.zig
new file mode 100644
index 000000000..248e333b0
--- /dev/null
+++ b/src/hal/dma.zig
@@ -0,0 +1,131 @@
+const std = @import("std");
+const assert = std.debug.assert;
+
+const microzig = @import("microzig");
+const chip = microzig.chip;
+const DMA = chip.peripherals.DMA;
+
+const hw = @import("hw.zig");
+
+var claimed_channels: u12 = 0;
+
+pub const Dreq = enum(u6) {
+    uart0_tx = 20,
+    uart1_tx = 21,
+    _,
+};
+
+pub fn num(n: u4) Channel {
+    assert(n < 12);
+
+    return @intToEnum(Channel, n);
+}
+
+pub fn claim_unused_channel() ?Channel {}
+
+pub const Channel = enum(u4) {
+    _,
+
+    /// panics if the channel is already claimed
+    pub fn claim(channel: Channel) void {
+        _ = channel;
+        @panic("TODO");
+    }
+
+    pub fn unclaim(channel: Channel) void {
+        _ = channel;
+        @panic("TODO");
+    }
+
+    pub fn is_claimed(channel: Channel) bool {
+        _ = channel;
+        @panic("TODO");
+    }
+
+    const Regs = extern struct {
+        read_addr: u32,
+        write_addr: u32,
+        trans_count: u32,
+        ctrl_trig: @TypeOf(DMA.CH0_CTRL_TRIG),
+
+        // alias 1
+        al1_ctrl: u32,
+        al1_read_addr: u32,
+        al1_write_addr: u32,
+        al1_trans_count: u32,
+
+        // alias 2
+        al2_ctrl: u32,
+        al2_read_addr: u32,
+        al2_write_addr: u32,
+        al2_trans_count: u32,
+
+        // alias 3
+        al3_ctrl: u32,
+        al3_read_addr: u32,
+        al3_write_addr: u32,
+        al3_trans_count: u32,
+    };
+
+    fn get_regs(channel: Channel) *volatile Regs {
+        const regs = @ptrCast(*volatile [12]Regs, &DMA.CH0_READ_ADDR);
+        return ®s[@enumToInt(channel)];
+    }
+
+    pub const TransferConfig = struct {
+        transfer_size_bytes: u3,
+        enable: bool,
+        read_increment: bool,
+        write_increment: bool,
+        dreq: Dreq,
+
+        // TODO:
+        // chain to
+        // ring
+        // byte swapping
+    };
+
+    pub fn trigger_transfer(
+        channel: Channel,
+        write_addr: u32,
+        read_addr: u32,
+        count: u32,
+        config: TransferConfig,
+    ) void {
+        const regs = channel.get_regs();
+        regs.read_addr = read_addr;
+        regs.write_addr = write_addr;
+        regs.trans_count = count;
+        regs.ctrl_trig.modify(.{
+            .EN = @boolToInt(config.enable),
+            .DATA_SIZE = .{
+                .value = .SIZE_BYTE,
+            },
+            .INCR_READ = @boolToInt(config.read_increment),
+            .INCR_WRITE = @boolToInt(config.write_increment),
+            .TREQ_SEL = .{
+                .raw = @enumToInt(config.dreq),
+            },
+        });
+    }
+
+    pub fn set_irq0_enabled(channel: Channel, enabled: bool) void {
+        if (enabled) {
+            const inte0_set = hw.set_alias_raw(&DMA.INTE0);
+            inte0_set.* = @as(u32, 1) << @enumToInt(channel);
+        } else {
+            const inte0_clear = hw.clear_alias_raw(&DMA.INTE0);
+            inte0_clear.* = @as(u32, 1) << @enumToInt(channel);
+        }
+    }
+
+    pub fn acknowledge_irq0(channel: Channel) void {
+        const ints0_set = hw.set_alias_raw(&DMA.INTS0);
+        ints0_set.* = @as(u32, 1) << @enumToInt(channel);
+    }
+
+    pub fn is_busy(channel: Channel) bool {
+        const regs = channel.get_regs();
+        return regs.ctrl_trig.read().BUSY == 1;
+    }
+};
diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig
index c0b6baeee..02f421e48 100644
--- a/src/hal/gpio.zig
+++ b/src/hal/gpio.zig
@@ -63,92 +63,147 @@ pub const Enabled = enum {
     enabled,
 };
 
-pub inline fn reset() void {
-    resets.reset(&.{ .io_bank0, .pads_bank0 });
-}
+pub const PullUpDown = enum {
+    up,
+    down,
+};
+
+pub fn num(n: u5) Pin {
+    if (n > 29)
+        @panic("the RP2040 only has GPIO 0-29");
 
-/// Initialize a GPIO, set func to SIO
-pub inline fn init(comptime gpio: u32) void {
-    const mask = 1 << gpio;
-    SIO.GPIO_OE_CLR.raw = mask;
-    SIO.GPIO_OUT_CLR.raw = mask;
-    set_function(gpio, .sio);
+    return @intToEnum(Pin, n);
 }
 
-/// Reset GPIO back to null function (disables it)
-pub inline fn deinit(comptime gpio: u32) void {
-    set_function(gpio, .null);
+pub fn mask(m: u32) Mask {
+    _ = m;
+    @panic("TODO");
 }
 
-pub const PullUpDown = enum {
-    up,
-    down,
+pub const Mask = enum(u30) {
+    _,
 };
 
-pub inline fn set_pull(comptime gpio: u32, mode: ?PullUpDown) void {
-    const gpio_name = comptime std.fmt.comptimePrint("GPIO{d}", .{gpio});
-    const gpio_regs = &@field(PADS_BANK0, gpio_name);
+pub const Pin = enum(u5) {
+    _,
+
+    pub const Regs = struct {
+        status: @TypeOf(IO_BANK0.GPIO0_STATUS),
+        ctrl: microzig.mmio.Mmio(packed struct(u32) {
+            FUNCSEL: packed union {
+                raw: u5,
+                value: Function,
+            },
+            reserved8: u3,
+            OUTOVER: packed union {
+                raw: u2,
+                value: Override,
+            },
+            reserved12: u2,
+            OEOVER: packed union {
+                raw: u2,
+                value: Override,
+            },
+            reserved16: u2,
+            INOVER: packed union {
+                raw: u2,
+                value: Override,
+            },
+            reserved28: u10,
+            IRQOVER: packed union {
+                raw: u2,
+                value: Override,
+            },
+            padding: u2,
+        }),
+    };
+
+    pub const PadsReg = @TypeOf(PADS_BANK0.GPIO0);
+
+    fn get_regs(gpio: Pin) *volatile Regs {
+        const regs = @ptrCast(*volatile [30]Regs, &IO_BANK0.GPIO0_STATUS);
+        return ®s[@enumToInt(gpio)];
+    }
 
-    if (mode == null) {
-        gpio_regs.modify(.{ .PUE = 0, .PDE = 0 });
-    } else switch (mode.?) {
-        .up => gpio_regs.modify(.{ .PUE = 1, .PDE = 0 }),
-        .down => gpio_regs.modify(.{ .PUE = 0, .PDE = 1 }),
+    fn get_pads_reg(gpio: Pin) *volatile PadsReg {
+        const regs = @ptrCast(*volatile [30]PadsReg, &PADS_BANK0.GPIO0);
+        return ®s[@enumToInt(gpio)];
     }
-}
 
-pub inline fn set_direction(comptime gpio: u32, direction: Direction) void {
-    const mask = 1 << gpio;
-    switch (direction) {
-        .in => SIO.GPIO_OE_CLR.raw = mask,
-        .out => SIO.GPIO_OE_SET.raw = mask,
+    pub fn mask(gpio: Pin) u32 {
+        return @as(u32, 1) << @enumToInt(gpio);
     }
-}
 
-/// Drive a single GPIO high/low
-pub inline fn put(comptime gpio: u32, value: u1) void {
-    std.log.debug("GPIO{} put: {}", .{ gpio, value });
-    const mask = 1 << gpio;
-    switch (value) {
-        0 => SIO.GPIO_OUT_CLR.raw = mask,
-        1 => SIO.GPIO_OUT_SET.raw = mask,
+    pub inline fn set_pull(gpio: Pin, mode: ?PullUpDown) void {
+        const pads_reg = gpio.get_pads_reg();
+
+        if (mode == null) {
+            pads_reg.modify(.{ .PUE = 0, .PDE = 0 });
+        } else switch (mode.?) {
+            .up => pads_reg.modify(.{ .PUE = 1, .PDE = 0 }),
+            .down => pads_reg.modify(.{ .PUE = 0, .PDE = 1 }),
+        }
     }
-}
 
-pub inline fn toggle(comptime gpio: u32) void {
-    SIO.GPIO_OUT_XOR.raw = (1 << gpio);
-}
+    pub inline fn set_direction(gpio: Pin, direction: Direction) void {
+        switch (direction) {
+            .in => SIO.GPIO_OE_CLR.raw = gpio.mask(),
+            .out => SIO.GPIO_OE_SET.raw = gpio.mask(),
+        }
+    }
 
-pub inline fn read(comptime gpio: u32) u1 {
-    const mask = 1 << gpio;
-    return if ((SIO.GPIO_IN.raw & mask) != 0)
-        1
-    else
-        0;
-}
+    /// Drive a single GPIO high/low
+    pub inline fn put(gpio: Pin, value: u1) void {
+        switch (value) {
+            0 => SIO.GPIO_OUT_CLR.raw = gpio.mask(),
+            1 => SIO.GPIO_OUT_SET.raw = gpio.mask(),
+        }
+    }
 
-pub inline fn set_function(comptime gpio: u32, function: Function) void {
-    const pad_bank_reg = comptime std.fmt.comptimePrint("GPIO{}", .{gpio});
-    @field(PADS_BANK0, pad_bank_reg).modify(.{
-        .IE = 1,
-        .OD = 0,
-    });
-
-    const io_bank_reg = comptime std.fmt.comptimePrint("GPIO{}_CTRL", .{gpio});
-    @field(IO_BANK0, io_bank_reg).write(.{
-        .FUNCSEL = .{ .raw = @enumToInt(function) },
-        .OUTOVER = .{ .value = .NORMAL },
-        .INOVER = .{ .value = .NORMAL },
-        .IRQOVER = .{ .value = .NORMAL },
-        .OEOVER = .{ .value = .NORMAL },
-
-        .reserved8 = 0,
-        .reserved12 = 0,
-        .reserved16 = 0,
-        .reserved28 = 0,
-        .padding = 0,
-    });
-}
+    pub inline fn toggle(gpio: Pin) void {
+        SIO.GPIO_OUT_XOR.raw = gpio.mask();
+    }
+
+    pub inline fn read(gpio: Pin) u1 {
+        return if ((SIO.GPIO_IN.raw & gpio.mask()) != 0)
+            1
+        else
+            0;
+    }
+
+    pub inline fn set_function(gpio: Pin, function: Function) void {
+        const pads_reg = gpio.get_pads_reg();
+        pads_reg.modify(.{
+            .IE = 1,
+            .OD = 0,
+        });
+
+        const regs = gpio.get_regs();
+        regs.ctrl.modify(.{
+            .FUNCSEL = .{ .value = function },
+            .OUTOVER = .{ .value = .normal },
+            .INOVER = .{ .value = .normal },
+            .IRQOVER = .{ .value = .normal },
+            .OEOVER = .{ .value = .normal },
+
+            .reserved8 = 0,
+            .reserved12 = 0,
+            .reserved16 = 0,
+            .reserved28 = 0,
+            .padding = 0,
+        });
+    }
+
+    //pub fn set_drive_strength(gpio: Gpio, drive: DriveStrength) void {
+    //    _ = drive;
+    //    const pads_reg = gpio.get_pads_reg();
+    //    pads_reg.modify(.{
+    //        .DRIVE = .{
+    //            .value = .@"12mA",
+    //        },
+    //    });
+    //}
+};
 
 // setting both uplls enables a "bus keep" function, a weak pull to whatever
 // is current high/low state of GPIO
@@ -165,7 +220,6 @@ pub inline fn set_function(comptime gpio: u32, function: Function) void {
 //pub fn setInputEnabled(gpio: u32, enabled: Enabled) void {}
 //pub fn setinputHysteresisEnabled(gpio: u32, enabled: Enabled) void {}
 //pub fn setSlewRate(gpio: u32, slew_rate: SlewRate) void {}
-//pub fn setDriveStrength(gpio: u32, drive: DriveStrength) void {}
+
 //pub fn setIrqEnabled(gpio: u32, events: IrqEvents) void {}
 //pub fn acknowledgeIrq(gpio: u32, events: IrqEvents) void {}
-
diff --git a/src/hal/hw.zig b/src/hal/hw.zig
index a44aff121..1017c8a6e 100644
--- a/src/hal/hw.zig
+++ b/src/hal/hw.zig
@@ -1,11 +1,44 @@
+const std = @import("std");
+const assert = std.debug.assert;
+
 pub const Lock = struct {
     impl: u32,
 
     pub fn claim() Lock {
-
+        @panic("TODO");
     }
 
     pub fn unlock(lock: Lock) void {
-
+        _ = lock;
+        @panic("TODO");
     }
 };
+
+const rw_bits = @as(u32, 0x0) << 12;
+const xor_bits = @as(u32, 0x1) << 12;
+const set_bits = @as(u32, 0x2) << 12;
+const clear_bits = @as(u32, 0x3) << 12;
+
+pub fn clear_alias_raw(ptr: anytype) *u32 {
+    return @intToPtr(*u32, @ptrToInt(ptr) | clear_bits);
+}
+
+pub fn set_alias_raw(ptr: anytype) *u32 {
+    return @intToPtr(*u32, @ptrToInt(ptr) | set_bits);
+}
+
+pub fn xor_alias_raw(ptr: anytype) *u32 {
+    return @intToPtr(*u32, @ptrToInt(ptr) | xor_bits);
+}
+
+pub fn clear_alias(ptr: anytype) @TypeOf(ptr) {
+    return @intToPtr(@TypeOf(ptr), @ptrToInt(ptr) | clear_bits);
+}
+
+pub fn set_alias(ptr: anytype) @TypeOf(ptr) {
+    return @intToPtr(@TypeOf(ptr), @ptrToInt(ptr) | set_bits);
+}
+
+pub fn xor_alias(ptr: anytype) @TypeOf(ptr) {
+    return @intToPtr(@TypeOf(ptr), @ptrToInt(ptr) | xor_bits);
+}
diff --git a/src/hal/pins.zig b/src/hal/pins.zig
index 3ff924638..a882df50f 100644
--- a/src/hal/pins.zig
+++ b/src/hal/pins.zig
@@ -315,24 +315,24 @@ const function_table = [@typeInfo(Function).Enum.fields.len][30]u1{
 pub fn GPIO(comptime num: u5, comptime direction: gpio.Direction) type {
     return switch (direction) {
         .in => struct {
-            const gpio_num = num;
+            const pin = gpio.num(num);
 
             pub inline fn read(self: @This()) u1 {
                 _ = self;
-                return gpio.read(gpio_num);
+                return pin.read();
             }
         },
         .out => struct {
-            const gpio_num = num;
+            const pin = gpio.num(num);
 
             pub inline fn put(self: @This(), value: u1) void {
                 _ = self;
-                gpio.put(gpio_num, value);
+                pin.put(value);
             }
 
             pub inline fn toggle(self: @This()) void {
                 _ = self;
-                gpio.toggle(gpio_num);
+                pin.toggle();
             }
         },
     };
@@ -473,7 +473,6 @@ pub const GlobalConfiguration = struct {
         // TODO: ensure only one instance of an input function exists
 
         const used_gpios = comptime input_gpios | output_gpios;
-        gpio.reset();
 
         if (used_gpios != 0) {
             SIO.GPIO_OE_CLR.raw = used_gpios;
@@ -482,7 +481,7 @@ pub const GlobalConfiguration = struct {
 
         inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| {
             if (@field(config, field.name)) |pin_config| {
-                const gpio_num = @enumToInt(@field(Pin, field.name));
+                const pin = gpio.num(@enumToInt(@field(Pin, field.name)));
                 const func = pin_config.function;
 
                 // xip = 0,
@@ -496,17 +495,17 @@ pub const GlobalConfiguration = struct {
                 // @"null" = 0x1f,
 
                 if (func == .SIO) {
-                    gpio.set_function(gpio_num, .sio);
+                    pin.set_function(.sio);
                 } else if (comptime func.is_pwm()) {
-                    gpio.set_function(gpio_num, .pwm);
+                    pin.set_function(.pwm);
                 } else if (comptime func.is_adc()) {
-                    gpio.set_function(gpio_num, .null);
+                    pin.set_function(.null);
                 } else if (comptime func.isUartTx() or func.isUartRx()) {
-                    gpio.set_function(gpio_num, .uart);
+                    pin.set_function(.uart);
                 } else {
                     @compileError(std.fmt.comptimePrint("Unimplemented pin function. Please implement setting pin function {s} for GPIO {}", .{
                         @tagName(func),
-                        gpio_num,
+                        @enumToInt(pin),
                     }));
                 }
             }
@@ -527,10 +526,6 @@ pub const GlobalConfiguration = struct {
                 };
         }
 
-        if (has_pwm) {
-            resets.reset(&.{.pwm});
-        }
-
         if (has_adc) {
             adc.init();
         }
diff --git a/src/hal/pio.zig b/src/hal/pio.zig
index 22dc5a304..2eb17096f 100644
--- a/src/hal/pio.zig
+++ b/src/hal/pio.zig
@@ -8,6 +8,8 @@ const PIO0 = microzig.chip.peripherals.PIO0;
 const PIO1 = microzig.chip.peripherals.PIO1;
 
 const gpio = @import("gpio.zig");
+const resets = @import("resets.zig");
+const hw = @import("hw.zig");
 const assembler = @import("pio/assembler.zig");
 const encoder = @import("pio/assembler/encoder.zig");
 
@@ -29,6 +31,19 @@ pub const StateMachine = enum(u2) {
     sm1,
     sm2,
     sm3,
+
+    pub const Regs = extern struct {
+        clkdiv: @TypeOf(PIO0.SM0_CLKDIV),
+        execctrl: @TypeOf(PIO0.SM0_EXECCTRL),
+        shiftctrl: @TypeOf(PIO0.SM0_SHIFTCTRL),
+        addr: @TypeOf(PIO0.SM0_ADDR),
+        instr: @TypeOf(PIO0.SM0_INSTR),
+        pinctrl: @TypeOf(PIO0.SM0_PINCTRL),
+    };
+
+    comptime {
+        assert(@sizeOf([2]Regs) == (4 * 6 * 2));
+    }
 };
 
 pub const Irq = enum {
@@ -41,6 +56,10 @@ pub const Irq = enum {
         status: @TypeOf(PIO0.IRQ0_INTS),
     };
 
+    comptime {
+        assert(@sizeOf([2]Regs) == (3 * 4 * 2));
+    }
+
     pub const Source = enum {
         rx_not_empty,
         tx_not_full,
@@ -50,18 +69,9 @@ pub const Irq = enum {
     };
 };
 
-pub const StateMachineRegs = extern struct {
-    clkdiv: @TypeOf(PIO0.SM0_CLKDIV),
-    execctrl: @TypeOf(PIO0.SM0_EXECCTRL),
-    shiftctrl: @TypeOf(PIO0.SM0_SHIFTCTRL),
-    addr: @TypeOf(PIO0.SM0_ADDR),
-    instr: @TypeOf(PIO0.SM0_INSTR),
-    pinctrl: @TypeOf(PIO0.SM0_PINCTRL),
-};
-
 pub const ClkDivOptions = struct {
-    int: u16,
-    frac: u8,
+    int: u16 = 1,
+    frac: u8 = 0,
 
     pub fn from_float(div: f32) ClkDivOptions {
         const fixed = @floatToInt(u24, div * 256);
@@ -73,18 +83,20 @@ pub const ClkDivOptions = struct {
 };
 
 pub const ExecOptions = struct {
-    wrap: u5,
-    wrap_target: u5,
-    side_pindir: bool,
-    side_set_optional: bool,
+    wrap: u5 = 31,
+    wrap_target: u5 = 0,
+    side_pindir: bool = false,
+    side_set_optional: bool = false,
 };
 
 pub const ShiftOptions = struct {
     autopush: bool = false,
     autopull: bool = false,
-    in_shiftdir: Direction = .left,
-    out_shiftdir: Direction = .left,
+    in_shiftdir: Direction = .right,
+    out_shiftdir: Direction = .right,
+    /// 0 means full 32-bits
     push_threshold: u5 = 0,
+    /// 0 means full 32-bits
     pull_threshold: u5 = 0,
     join_tx: bool = false,
     join_rx: bool = false,
@@ -104,16 +116,16 @@ pub fn PinMapping(comptime Count: type) type {
 
 pub const PinMappingOptions = struct {
     out: PinMapping(u6) = .{},
-    set: PinMapping(u3) = .{},
+    set: PinMapping(u3) = .{ .count = 5 },
     side_set: PinMapping(u3) = .{},
     in_base: u5 = 0,
 };
 
 pub const StateMachineInitOptions = struct {
-    clkdiv: ClkDivOptions,
-    exec: ExecOptions,
-    shift: ShiftOptions = .{},
+    clkdiv: ClkDivOptions = .{},
     pin_mappings: PinMappingOptions = .{},
+    exec: ExecOptions = .{},
+    shift: ShiftOptions = .{},
 };
 
 pub const LoadAndStartProgramOptions = struct {
@@ -126,6 +138,13 @@ pub const Pio = enum(u1) {
     pio0 = 0,
     pio1 = 1,
 
+    pub fn reset(self: Pio) void {
+        switch (self) {
+            .pio0 => resets.reset(&.{.pio0}),
+            .pio1 => resets.reset(&.{.pio1}),
+        }
+    }
+
     fn get_regs(self: Pio) *volatile PIO {
         return switch (self) {
             .pio0 => PIO0,
@@ -138,8 +157,8 @@ pub const Pio = enum(u1) {
         return @ptrCast(*volatile [32]u32, ®s.INSTR_MEM0);
     }
 
-    pub fn gpio_init(self: Pio, comptime pin: u5) void {
-        gpio.set_function(pin, switch (self) {
+    pub fn gpio_init(self: Pio, pin: gpio.Pin) void {
+        pin.set_function(switch (self) {
             .pio0 => .pio0,
             .pio1 => .pio1,
         });
@@ -207,25 +226,19 @@ pub const Pio = enum(u1) {
         } else error.NoSpace;
     }
 
-    fn get_sm_regs(self: Pio, sm: StateMachine) *volatile StateMachineRegs {
+    fn get_sm_regs(self: Pio, sm: StateMachine) *volatile StateMachine.Regs {
         const pio_regs = self.get_regs();
-        return switch (sm) {
-            .sm0 => @ptrCast(*volatile StateMachineRegs, &pio_regs.SM0_CLKDIV),
-            .sm1 => @ptrCast(*volatile StateMachineRegs, &pio_regs.SM1_CLKDIV),
-            .sm2 => @ptrCast(*volatile StateMachineRegs, &pio_regs.SM2_CLKDIV),
-            .sm3 => @ptrCast(*volatile StateMachineRegs, &pio_regs.SM3_CLKDIV),
-        };
+        const sm_regs = @ptrCast(*volatile [4]StateMachine.Regs, &pio_regs.SM0_CLKDIV);
+        return &sm_regs[@enumToInt(sm)];
     }
 
     fn get_irq_regs(self: Pio, irq: Irq) *volatile Irq.Regs {
         const pio_regs = self.get_regs();
-        return switch (irq) {
-            .irq0 => @ptrCast(*volatile Irq.Regs, &pio_regs.IRQ0_INTE),
-            .irq1 => @ptrCast(*volatile Irq.Regs, &pio_regs.IRQ1_INTE),
-        };
+        const irq_regs = @ptrCast(*volatile [2]Irq.Regs, &pio_regs.IRQ0_INTE);
+        return &irq_regs[@enumToInt(irq)];
     }
 
-    pub inline fn sm_set_clkdiv(self: Pio, sm: StateMachine, options: ClkDivOptions) void {
+    pub fn sm_set_clkdiv(self: Pio, sm: StateMachine, options: ClkDivOptions) void {
         if (options.int == 0 and options.frac != 0)
             @panic("invalid params");
 
@@ -238,7 +251,7 @@ pub const Pio = enum(u1) {
         });
     }
 
-    pub inline fn sm_set_exec_options(self: Pio, sm: StateMachine, options: ExecOptions) void {
+    pub fn sm_set_exec_options(self: Pio, sm: StateMachine, options: ExecOptions) void {
         const sm_regs = self.get_sm_regs(sm);
         sm_regs.execctrl.modify(.{
             .WRAP_BOTTOM = options.wrap_target,
@@ -257,11 +270,11 @@ pub const Pio = enum(u1) {
         });
     }
 
-    pub inline fn sm_set_shift_options(self: Pio, sm: StateMachine, options: ShiftOptions) void {
+    pub fn sm_set_shift_options(self: Pio, sm: StateMachine, options: ShiftOptions) void {
         const sm_regs = self.get_sm_regs(sm);
         sm_regs.shiftctrl.write(.{
             .AUTOPUSH = @boolToInt(options.autopush),
-            .AUTOPULL = @boolToInt(options.autopush),
+            .AUTOPULL = @boolToInt(options.autopull),
 
             .IN_SHIFTDIR = @enumToInt(options.in_shiftdir),
             .OUT_SHIFTDIR = @enumToInt(options.out_shiftdir),
@@ -276,7 +289,7 @@ pub const Pio = enum(u1) {
         });
     }
 
-    pub inline fn sm_set_pin_mappings(self: Pio, sm: StateMachine, options: PinMappingOptions) void {
+    pub fn sm_set_pin_mappings(self: Pio, sm: StateMachine, options: PinMappingOptions) void {
         const sm_regs = self.get_sm_regs(sm);
         sm_regs.pinctrl.modify(.{
             .OUT_BASE = options.out.base,
@@ -292,30 +305,32 @@ pub const Pio = enum(u1) {
         });
     }
 
-    pub inline fn sm_is_tx_fifo_full(self: Pio, sm: StateMachine) bool {
+    pub fn sm_is_tx_fifo_full(self: Pio, sm: StateMachine) bool {
         const regs = self.get_regs();
         const txfull = regs.FSTAT.read().TXFULL;
         return (txfull & (@as(u4, 1) << @enumToInt(sm))) != 0;
     }
 
-    pub inline fn sm_get_tx_fifo(self: Pio, sm: StateMachine) *volatile u32 {
+    pub fn sm_get_tx_fifo(self: Pio, sm: StateMachine) *volatile u32 {
         const regs = self.get_regs();
-        return switch (sm) {
-            .sm0 => ®s.TXF0,
-            .sm1 => ®s.TXF1,
-            .sm2 => ®s.TXF2,
-            .sm3 => ®s.TXF3,
-        };
+        const fifos = @ptrCast(*volatile [4]u32, ®s.TXF0);
+        return &fifos[@enumToInt(sm)];
     }
 
-    pub inline fn sm_blocking_write(self: Pio, sm: StateMachine, value: u32) void {
-        while (self.sm_is_tx_fifo_full(sm)) {}
-
+    /// this function writes to the TX FIFO without checking that it's
+    /// writable, if it's not then the value is ignored
+    pub fn sm_write(self: Pio, sm: StateMachine, value: u32) void {
         const fifo_ptr = self.sm_get_tx_fifo(sm);
         fifo_ptr.* = value;
     }
 
-    pub inline fn sm_set_enabled(self: Pio, sm: StateMachine, enabled: bool) void {
+    pub fn sm_blocking_write(self: Pio, sm: StateMachine, value: u32) void {
+        while (self.sm_is_tx_fifo_full(sm)) {}
+
+        self.sm_write(sm, value);
+    }
+
+    pub fn sm_set_enabled(self: Pio, sm: StateMachine, enabled: bool) void {
         const regs = self.get_regs();
 
         var value = regs.CTRL.read();
@@ -327,7 +342,7 @@ pub const Pio = enum(u1) {
         regs.CTRL.write(value);
     }
 
-    inline fn sm_clear_debug(self: Pio, sm: StateMachine) void {
+    fn sm_clear_debug(self: Pio, sm: StateMachine) void {
         const regs = self.get_regs();
         const mask: u4 = (@as(u4, 1) << @enumToInt(sm));
 
@@ -343,10 +358,22 @@ pub const Pio = enum(u1) {
     /// changing the state of fifos will clear them
     pub fn sm_clear_fifos(self: Pio, sm: StateMachine) void {
         const sm_regs = self.get_sm_regs(sm);
-        var shiftctrl = sm_regs.shiftctrl.read();
-        shiftctrl.FJOIN_TX ^= 1;
-        shiftctrl.FJOIN_RX ^= 1;
-        sm_regs.shiftctrl.write(shiftctrl);
+        const xor_shiftctrl = hw.xor_alias(&sm_regs.shiftctrl);
+        const mask = .{
+            .FJOIN_TX = 1,
+            .FJOIN_RX = 1,
+
+            .AUTOPUSH = 0,
+            .AUTOPULL = 0,
+            .IN_SHIFTDIR = 0,
+            .OUT_SHIFTDIR = 0,
+            .PUSH_THRESH = 0,
+            .PULL_THRESH = 0,
+            .reserved16 = 0,
+        };
+
+        xor_shiftctrl.write(mask);
+        xor_shiftctrl.write(mask);
     }
 
     pub fn sm_fifo_level(self: Pio, sm: StateMachine, fifo: Fifo) u4 {
@@ -362,14 +389,14 @@ pub const Pio = enum(u1) {
         return @truncate(u4, levels >> (@as(u5, 4) * num) + offset);
     }
 
-    inline fn interrupt_bit_pos(
+    fn interrupt_bit_pos(
         sm: StateMachine,
         source: Irq.Source,
     ) u5 {
         return (@as(u5, 4) * @enumToInt(source)) + @enumToInt(sm);
     }
 
-    pub inline fn sm_clear_interrupt(
+    pub fn sm_clear_interrupt(
         self: Pio,
         sm: StateMachine,
         irq: Irq,
@@ -378,11 +405,11 @@ pub const Pio = enum(u1) {
         // TODO: why does the raw interrupt register no have irq1/0?
         _ = irq;
         const regs = self.get_regs();
-        regs.INTR.raw &= ~(@as(u32, 1) << interrupt_bit_pos(sm, source));
+        regs.IRQ.raw |= @as(u32, 1) << interrupt_bit_pos(sm, source);
     }
 
     // TODO: be able to disable an interrupt
-    pub inline fn sm_enable_interrupt(
+    pub fn sm_enable_interrupt(
         self: Pio,
         sm: StateMachine,
         irq: Irq,
@@ -392,7 +419,7 @@ pub const Pio = enum(u1) {
         irq_regs.enable.raw |= @as(u32, 1) << interrupt_bit_pos(sm, source);
     }
 
-    pub inline fn sm_restart(self: Pio, sm: StateMachine) void {
+    pub fn sm_restart(self: Pio, sm: StateMachine) void {
         const mask: u4 = (@as(u4, 1) << @enumToInt(sm));
         const regs = self.get_regs();
         regs.CTRL.modify(.{
@@ -400,7 +427,7 @@ pub const Pio = enum(u1) {
         });
     }
 
-    pub inline fn sm_clkdiv_restart(self: Pio, sm: StateMachine) void {
+    pub fn sm_clkdiv_restart(self: Pio, sm: StateMachine) void {
         const mask: u4 = (@as(u4, 1) << @enumToInt(sm));
         const regs = self.get_regs();
         regs.CTRL.modify(.{
@@ -416,12 +443,11 @@ pub const Pio = enum(u1) {
     ) void {
         // Halt the machine, set some sensible defaults
         self.sm_set_enabled(sm, false);
-        self.sm_set_pin_mappings(sm, options.pin_mappings);
         self.sm_set_clkdiv(sm, options.clkdiv);
         self.sm_set_exec_options(sm, options.exec);
         self.sm_set_shift_options(sm, options.shift);
+        self.sm_set_pin_mappings(sm, options.pin_mappings);
 
-        //self.set_config(sm, config);
         self.sm_clear_fifos(sm);
         self.sm_clear_debug(sm);
 
@@ -480,7 +506,7 @@ pub const Pio = enum(u1) {
                     offset,
 
                 .side_pindir = if (program.side_set) |side_set|
-                    side_set.pindirs
+                    side_set.pindir
                 else
                     false,
 
diff --git a/src/hal/pio/assembler.zig b/src/hal/pio/assembler.zig
index af4153add..3cde6ee80 100644
--- a/src/hal/pio/assembler.zig
+++ b/src/hal/pio/assembler.zig
@@ -121,12 +121,12 @@ fn format_compile_error(comptime message: []const u8, comptime source: []const u
     });
 }
 
-pub fn assemble(comptime source: []const u8, comptime options: AssembleOptions) !Output {
+pub fn assemble(comptime source: []const u8, comptime options: AssembleOptions) Output {
     var diags: ?Diagnostics = null;
     return assemble_impl(source, &diags, options) catch |err| if (diags) |d|
         @compileError(format_compile_error(d.message.slice(), source, d.index))
     else
-        err;
+        @compileError(err);
 }
 
 test "tokenizer and encoder" {
diff --git a/src/hal/pio/assembler/encoder.zig b/src/hal/pio/assembler/encoder.zig
index a5625751b..e0bc74c9a 100644
--- a/src/hal/pio/assembler/encoder.zig
+++ b/src/hal/pio/assembler/encoder.zig
@@ -27,7 +27,7 @@ pub fn encode(
 pub const SideSet = struct {
     count: u3,
     optional: bool,
-    pindirs: bool,
+    pindir: bool,
 };
 
 pub const Define = struct {
@@ -76,15 +76,20 @@ pub fn Encoder(comptime options: Options) type {
             wrap: ?u5,
 
             pub fn to_exported_program(comptime bounded: BoundedProgram) assembler.Program {
+                comptime var program_name: [bounded.name.len]u8 = undefined;
+                std.mem.copy(u8, &program_name, bounded.name);
                 return assembler.Program{
-                    .name = bounded.name,
+                    .name = &program_name,
                     .defines = blk: {
                         var tmp = std.BoundedArray(assembler.Define, options.max_defines).init(0) catch unreachable;
-                        for (bounded.defines.slice()) |define|
+                        for (bounded.defines.slice()) |define| {
+                            comptime var define_name: [define.name.len]u8 = undefined;
+                            std.mem.copy(u8, &define_name, define.name);
                             tmp.append(.{
-                                .name = define.name,
+                                .name = &define_name,
                                 .value = @intCast(i64, define.value),
                             }) catch unreachable;
+                        }
 
                         break :blk tmp.slice();
                     },
@@ -281,7 +286,7 @@ pub fn Encoder(comptime options: Options) type {
                         program.side_set = .{
                             .count = try self.evaluate(u3, program.*, side_set.count, token.index, diags),
                             .optional = side_set.opt,
-                            .pindirs = side_set.pindirs,
+                            .pindir = side_set.pindir,
                         };
                         self.consume(1);
                     },
@@ -823,7 +828,7 @@ test "encode.side_set.pindirs" {
 
     const program = output.programs.get(0);
     try expectEqual(@as(?u5, 1), program.side_set.?.count);
-    try expect(program.side_set.?.pindirs);
+    try expect(program.side_set.?.pindir);
 }
 
 test "encode.label" {
diff --git a/src/hal/pio/assembler/tokenizer.zig b/src/hal/pio/assembler/tokenizer.zig
index 62e4c0e1f..29c596d2e 100644
--- a/src/hal/pio/assembler/tokenizer.zig
+++ b/src/hal/pio/assembler/tokenizer.zig
@@ -439,7 +439,7 @@ pub const Tokenizer = struct {
                 .side_set = .{
                     .count = count,
                     .opt = opt,
-                    .pindirs = pindirs,
+                    .pindir = pindirs,
                 },
             },
         };
@@ -1129,7 +1129,7 @@ pub const Token = struct {
     pub const SideSet = struct {
         count: Value,
         opt: bool = false,
-        pindirs: bool = false,
+        pindir: bool = false,
     };
 
     pub const LangOpt = struct {
@@ -1191,7 +1191,7 @@ fn expect_side_set(expected: Token.SideSet, actual: Token) !void {
     const side_set = actual.data.side_set;
     try expect_value(expected.count, side_set.count);
     try expectEqual(expected.opt, side_set.opt);
-    try expectEqual(expected.pindirs, side_set.pindirs);
+    try expectEqual(expected.pindir, side_set.pindir);
 }
 
 fn expect_wrap_target(actual: Token) !void {
@@ -1538,7 +1538,7 @@ test "tokenize.directive.side_set.opt" {
 
 test "tokenize.directive.side_set.pindirs" {
     const tokens = try bounded_tokenize(".side_set 1 pindirs");
-    try expect_side_set(.{ .count = .{ .integer = 1 }, .pindirs = true }, tokens.get(0));
+    try expect_side_set(.{ .count = .{ .integer = 1 }, .pindir = true }, tokens.get(0));
 }
 
 test "tokenize.directive.wrap_target" {
diff --git a/src/hal/pll.zig b/src/hal/pll.zig
index 62fd9ecd7..37570497b 100644
--- a/src/hal/pll.zig
+++ b/src/hal/pll.zig
@@ -19,7 +19,7 @@ pub const Configuration = struct {
     }
 };
 
-pub const PLL = enum {
+pub const PLL = enum(u1) {
     sys,
     usb,
 
diff --git a/src/hal/resets.zig b/src/hal/resets.zig
index 218e6b427..f25d55027 100644
--- a/src/hal/resets.zig
+++ b/src/hal/resets.zig
@@ -3,42 +3,39 @@ const EnumField = std.builtin.Type.EnumField;
 
 const microzig = @import("microzig");
 const RESETS = microzig.chip.peripherals.RESETS;
-const Mask = @TypeOf(RESETS.RESET).underlying_type;
-
-pub const Module = enum {
-    adc,
-    busctrl,
-    dma,
-    i2c0,
-    i2c1,
-    io_bank0,
-    io_qspi,
-    jtag,
-    pads_bank0,
-    pads_qspi,
-    pio0,
-    pio1,
-    pll_sys,
-    pll_usb,
-    pwm,
-    rtc,
-    spi0,
-    spi1,
-    syscfg,
-    sysinfo,
-    tbman,
-    timer,
-    uart0,
-    uart1,
-    usbctrl,
-};
 
-pub inline fn reset(comptime modules: []const Module) void {
-    comptime var mask = std.mem.zeroes(Mask);
+const hw = @import("hw.zig");
 
-    inline for (modules) |module|
-        @field(mask, @tagName(module)) = 1;
+pub const Mask = packed struct(u32) {
+    adc: bool = false,
+    busctrl: bool = false,
+    dma: bool = false,
+    i2c0: bool = false,
+    i2c1: bool = false,
+    io_bank0: bool = false,
+    io_qspi: bool = false,
+    jtag: bool = false,
+    pads_bank0: bool = false,
+    pads_qspi: bool = false,
+    pio0: bool = false,
+    pio1: bool = false,
+    pll_sys: bool = false,
+    pll_usb: bool = false,
+    pwm: bool = false,
+    rtc: bool = false,
+    spi0: bool = false,
+    spi1: bool = false,
+    syscfg: bool = false,
+    sysinfo: bool = false,
+    tbman: bool = false,
+    timer: bool = false,
+    uart0: bool = false,
+    uart1: bool = false,
+    usbctrl: bool = false,
+    padding: u7 = 0,
+};
 
+pub fn reset(mask: Mask) void {
     const raw_mask = @bitCast(u32, mask);
 
     RESETS.RESET.raw = raw_mask;
@@ -46,3 +43,90 @@ pub inline fn reset(comptime modules: []const Module) void {
 
     while ((RESETS.RESET_DONE.raw & raw_mask) != raw_mask) {}
 }
+
+pub fn reset_block(mask: Mask) void {
+    hw.set_alias_raw(&RESETS.RESET).* = @bitCast(u32, mask);
+}
+
+pub fn unreset_block(mask: Mask) void {
+    hw.clear_alias_raw(&RESETS.RESET).* = @bitCast(u32, mask);
+}
+
+pub fn unreset_block_wait(mask: Mask) void {
+    const raw_mask = @bitCast(u32, mask);
+    hw.clear_alias_raw(&RESETS.RESET).* = raw_mask;
+    while (RESETS.RESET_DONE.raw & raw_mask != raw_mask) {}
+}
+
+pub const masks = struct {
+    pub const init = Mask{
+        .adc = true,
+        .busctrl = true,
+        .dma = true,
+        .i2c0 = true,
+        .i2c1 = true,
+        .io_bank0 = true,
+        .jtag = true,
+        .pads_bank0 = true,
+        .pio0 = true,
+        .pio1 = true,
+        .pwm = true,
+        .rtc = true,
+        .spi0 = true,
+        .spi1 = true,
+        .sysinfo = true,
+        .tbman = true,
+        .timer = true,
+        .uart0 = true,
+        .uart1 = true,
+    };
+
+    pub const all = Mask{
+        .adc = true,
+        .busctrl = true,
+        .dma = true,
+        .i2c0 = true,
+        .i2c1 = true,
+        .io_bank0 = true,
+        .io_qspi = true,
+        .jtag = true,
+        .pads_bank0 = true,
+        .pads_qspi = true,
+        .pio0 = true,
+        .pio1 = true,
+        .pll_sys = true,
+        .pll_usb = true,
+        .pwm = true,
+        .rtc = true,
+        .spi0 = true,
+        .spi1 = true,
+        .syscfg = true,
+        .sysinfo = true,
+        .tbman = true,
+        .timer = true,
+        .uart0 = true,
+        .uart1 = true,
+        .usbctrl = true,
+    };
+
+    pub const clocked_by_sys_and_ref = Mask{
+        .busctrl = true,
+        .dma = true,
+        .i2c0 = true,
+        .i2c1 = true,
+        .io_bank0 = true,
+        .io_qspi = true,
+        .jtag = true,
+        .pads_bank0 = true,
+        .pads_qspi = true,
+        .pio0 = true,
+        .pio1 = true,
+        .pll_sys = true,
+        .pll_usb = true,
+        .pwm = true,
+        .syscfg = true,
+        .sysinfo = true,
+        .tbman = true,
+        .timer = true,
+    };
+};
diff --git a/src/hal/spi.zig b/src/hal/spi.zig
index 002ccc4d7..717060002 100644
--- a/src/hal/spi.zig
+++ b/src/hal/spi.zig
@@ -14,40 +14,28 @@ const SpiRegs = microzig.chip.types.peripherals.SPI0;
 
 pub const Config = struct {
     clock_config: clocks.GlobalConfiguration,
-    tx_pin: ?u32 = 19,
-    rx_pin: ?u32 = 16,
-    sck_pin: ?u32 = 18,
-    csn_pin: ?u32 = 17,
+    tx_pin: ?gpio.Pin = gpio.num(19),
+    rx_pin: ?gpio.Pin = gpio.num(16),
+    sck_pin: ?gpio.Pin = gpio.num(18),
+    csn_pin: ?gpio.Pin = gpio.num(17),
     baud_rate: u32 = 1000 * 1000,
 };
 
-pub const SPI = enum {
-    spi0,
-    spi1,
+pub fn num(n: u1) SPI {
+    return @intToEnum(SPI, n);
+}
+
+pub const SPI = enum(u1) {
+    _,
 
     fn get_regs(spi: SPI) *volatile SpiRegs {
-        return switch (spi) {
-            .spi0 => SPI0,
-            .spi1 => SPI1,
+        return switch (@enumToInt(spi)) {
+            0 => SPI0,
+            1 => SPI1,
         };
     }
 
-    pub fn reset(spi: SPI) void {
-        switch (spi) {
-            .spi0 => resets.reset(&.{.spi0}),
-            .spi1 => resets.reset(&.{.spi1}),
-        }
-    }
-
-    pub fn init(comptime id: u32, comptime config: Config) SPI {
-        const spi: SPI = switch (id) {
-            0 => .spi0,
-            1 => .spi1,
-            else => @compileError("there is only spi0 and spi1"),
-        };
-
-        spi.reset();
-
+    pub fn apply(spi: SPI, comptime config: Config) void {
         const peri_freq = config.clock_config.peri.?.output_freq;
         _ = spi.set_baudrate(config.baud_rate, peri_freq);
 
@@ -71,12 +59,10 @@ pub const SPI = enum {
             .SSE = 1,
         });
 
-        if (config.tx_pin) |pin| gpio.set_function(pin, .spi);
-        if (config.rx_pin) |pin| gpio.set_function(pin, .spi);
-        if (config.sck_pin) |pin| gpio.set_function(pin, .spi);
-        if (config.csn_pin) |pin| gpio.set_function(pin, .spi);
-
-        return spi;
+        if (config.tx_pin) |pin| pin.set_function(.spi);
+        if (config.rx_pin) |pin| pin.set_function(.spi);
+        if (config.sck_pin) |pin| pin.set_function(.spi);
+        if (config.csn_pin) |pin| pin.set_function(.spi);
     }
 
     pub inline fn is_writable(spi: SPI) bool {
diff --git a/src/hal/uart.zig b/src/hal/uart.zig
index f4c72c5a6..6a08b852d 100644
--- a/src/hal/uart.zig
+++ b/src/hal/uart.zig
@@ -8,6 +8,7 @@ const gpio = @import("gpio.zig");
 const clocks = @import("clocks.zig");
 const resets = @import("resets.zig");
 const time = @import("time.zig");
+const dma = @import("dma.zig");
 
 const assert = std.debug.assert;
 
@@ -33,17 +34,20 @@ pub const Parity = enum {
 
 pub const Config = struct {
     clock_config: clocks.GlobalConfiguration,
-    tx_pin: ?u32 = null,
-    rx_pin: ?u32 = null,
+    tx_pin: ?gpio.Pin = null,
+    rx_pin: ?gpio.Pin = null,
     baud_rate: u32,
     word_bits: WordBits = .eight,
     stop_bits: StopBits = .one,
     parity: Parity = .none,
 };
 
-pub const UART = enum {
-    uart0,
-    uart1,
+pub fn num(n: u1) UART {
+    return @intToEnum(UART, n);
+}
+
+pub const UART = enum(u1) {
+    _,
 
     const WriteError = error{};
     const ReadError = error{};
@@ -59,23 +63,15 @@ pub const UART = enum {
     }
 
     fn get_regs(uart: UART) *volatile UartRegs {
-        return switch (uart) {
-            .uart0 => UART0,
-            .uart1 => UART1,
+        return switch (@enumToInt(uart)) {
+            0 => UART0,
+            1 => UART1,
         };
     }
 
-    pub fn init(comptime id: u32, comptime config: Config) UART {
-        const uart: UART = switch (id) {
-            0 => .uart0,
-            1 => .uart1,
-            else => @compileError("there is only uart0 and uart1"),
-        };
-
+    pub fn apply(uart: UART, comptime config: Config) void {
         assert(config.baud_rate > 0);
 
-        uart.reset();
-
         const uart_regs = uart.get_regs();
         const peri_freq = config.clock_config.peri.?.output_freq;
         uart.set_baudrate(config.baud_rate, peri_freq);
@@ -96,10 +92,8 @@ pub const UART = enum {
         });
 
         // TODO comptime assertions
-        if (config.tx_pin) |tx_pin| gpio.set_function(tx_pin, .uart);
-        if (config.rx_pin) |rx_pin| gpio.set_function(rx_pin, .uart);
-
-        return uart;
+        if (config.tx_pin) |tx_pin| tx_pin.set_function(.uart);
+        if (config.rx_pin) |rx_pin| rx_pin.set_function(.uart);
     }
 
     pub fn is_readable(uart: UART) bool {
@@ -122,6 +116,18 @@ pub const UART = enum {
         return payload.len;
     }
 
+    pub fn tx_fifo(uart: UART) *volatile u32 {
+        const regs = uart.get_regs();
+        return @ptrCast(*volatile u32, ®s.UARTDR);
+    }
+
+    pub fn dreq_tx(uart: UART) dma.Dreq {
+        return switch (@enumToInt(uart)) {
+            0 => .uart0_tx,
+            1 => .uart1_tx,
+        };
+    }
+
     pub fn read(uart: UART, buffer: []u8) ReadError!usize {
         const uart_regs = uart.get_regs();
         for (buffer) |*byte| {
@@ -141,13 +147,6 @@ pub const UART = enum {
         return uart_regs.UARTDR.read().DATA;
     }
 
-    pub fn reset(uart: UART) void {
-        switch (uart) {
-            .uart0 => resets.reset(&.{.uart0}),
-            .uart1 => resets.reset(&.{.uart1}),
-        }
-    }
-
     pub fn set_format(
         uart: UART,
         word_bits: WordBits,
diff --git a/src/hal/usb.zig b/src/hal/usb.zig
index 48538a48a..e2147f536 100644
--- a/src/hal/usb.zig
+++ b/src/hal/usb.zig
@@ -130,7 +130,7 @@ pub const F = struct {
         // clock.
         //
         // PLL_USB out of reset
-        resets.reset(&.{.pll_usb});
+        resets.reset(.{ .pll_usb = true });
         // Configure it:
         //
         // RFDIV = 1
@@ -154,7 +154,7 @@ pub const F = struct {
 
     pub fn usb_init_device(device_config: *usb.DeviceConfiguration) void {
         // Bring USB out of reset
-        resets.reset(&.{.usbctrl});
+        resets.reset(.{ .usbctrl = true });
 
         // Clear the control portion of DPRAM. This may not be necessary -- the
         // datasheet is ambiguous -- but the C examples do it, and so do we.

From b4c58dbb04408398f563a4531a35fbf74d9b73e1 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 3 May 2023 21:40:05 -0700
Subject: [PATCH 149/286] update microzig (#18)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b5edf6da6..4e62e99e3 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d
+Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be

From c47778854f6e4f63facf40ada1b0aa0e1665767d Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 3 May 2023 21:40:13 -0700
Subject: [PATCH 150/286] update microzig (#19)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b5edf6da6..4e62e99e3 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d
+Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be

From b27a29460373971571052838457cbec46ee2b5d3 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 3 May 2023 21:40:19 -0700
Subject: [PATCH 151/286] update microzig (#19)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b5edf6da6..4e62e99e3 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d
+Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be

From f343617ca44ff2e750de273497663798b8a4afaa Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 3 May 2023 21:40:42 -0700
Subject: [PATCH 152/286] update microzig (#52)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b5edf6da6..4e62e99e3 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d
+Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be

From ddc3bb1608eef6d0be77e6d14cd62b483d05be1e Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 3 May 2023 21:40:48 -0700
Subject: [PATCH 153/286] update microzig (#19)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b5edf6da6..4e62e99e3 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d
+Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be

From aeadb4155451910e93b40b7d07bf9be7029c908a Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 3 May 2023 21:40:56 -0700
Subject: [PATCH 154/286] update microzig (#18)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b5edf6da6..4e62e99e3 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d
+Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be

From 5f9de91f22a0b1f9bec9bef7ed994c7c67104c57 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Wed, 3 May 2023 21:41:03 -0700
Subject: [PATCH 155/286] update microzig (#18)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index b5edf6da6..4e62e99e3 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit b5edf6da6b540215f03689c3cc07d00478255f7d
+Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be

From c74f6f06348773594e6311cdff0411298cfce578 Mon Sep 17 00:00:00 2001
From: joelpaulkoch <64319336+joelpaulkoch@users.noreply.github.com>
Date: Mon, 15 May 2023 04:48:21 +0200
Subject: [PATCH 156/286] Fix: call renamed is_uart functions (#55)

---
 src/hal/pins.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/hal/pins.zig b/src/hal/pins.zig
index a882df50f..1746409cc 100644
--- a/src/hal/pins.zig
+++ b/src/hal/pins.zig
@@ -500,7 +500,7 @@ pub const GlobalConfiguration = struct {
                     pin.set_function(.pwm);
                 } else if (comptime func.is_adc()) {
                     pin.set_function(.null);
-                } else if (comptime func.isUartTx() or func.isUartRx()) {
+                } else if (comptime func.is_uart_tx() or func.is_uart_rx()) {
                     pin.set_function(.uart);
                 } else {
                     @compileError(std.fmt.comptimePrint("Unimplemented pin function. Please implement setting pin function {s} for GPIO {}", .{

From 72f7689700141e99a1af77202e1aa22cd46f5418 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 21:47:29 -0700
Subject: [PATCH 157/286] update microzig (#19)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 4e62e99e3..958894191 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be
+Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5

From d90b4f6caf3739e5964b8d0005032dd7444c9ab8 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 21:47:36 -0700
Subject: [PATCH 158/286] update microzig (#20)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 4e62e99e3..958894191 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be
+Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5

From 81142fdfc0acc47a801866e99d14df15a0440f19 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 21:47:43 -0700
Subject: [PATCH 159/286] update microzig (#56)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 4e62e99e3..958894191 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be
+Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5

From a6fe2574628f265a9f943d1d3ea7049f27119d04 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 21:47:52 -0700
Subject: [PATCH 160/286] update microzig (#20)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 4e62e99e3..958894191 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be
+Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5

From 5c65e8ed193491a17100f926760afd01035250e0 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 21:48:08 -0700
Subject: [PATCH 161/286] update microzig (#19)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 4e62e99e3..958894191 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be
+Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5

From fd4cc4f07c889afc7e401d1dd7530b41838aa9e1 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 21:48:16 -0700
Subject: [PATCH 162/286] update microzig (#20)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 4e62e99e3..958894191 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be
+Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5

From 83443705dfe789b4996342f0af7e4e01bb9d1f73 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 21:48:23 -0700
Subject: [PATCH 163/286] update microzig (#19)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 4e62e99e3..958894191 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 4e62e99e3cf8ad2b8805bc6138c53995bd9745be
+Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5

From ed12908afc6c54973b4d7fe8d0725c1e0eba57a2 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 22:37:10 -0700
Subject: [PATCH 164/286] turn on PIO comparison tests (#58)

---
 src/hal/pio/assembler.zig                  | 2 +-
 src/hal/pio/assembler/comparison_tests.zig | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/hal/pio/assembler.zig b/src/hal/pio/assembler.zig
index 3cde6ee80..1c38816ff 100644
--- a/src/hal/pio/assembler.zig
+++ b/src/hal/pio/assembler.zig
@@ -136,5 +136,5 @@ test "tokenizer and encoder" {
 }
 
 test "comparison" {
-    //std.testing.refAllDecls(@import("assembler/comparison_tests.zig"));
+    std.testing.refAllDecls(@import("assembler/comparison_tests.zig"));
 }
diff --git a/src/hal/pio/assembler/comparison_tests.zig b/src/hal/pio/assembler/comparison_tests.zig
index 4a3946575..5a98c9385 100644
--- a/src/hal/pio/assembler/comparison_tests.zig
+++ b/src/hal/pio/assembler/comparison_tests.zig
@@ -31,7 +31,7 @@ const c = @cImport({
 });
 
 fn pio_comparison(comptime source: []const u8) !void {
-    const output = comptime assembler.assemble(source, .{}) catch unreachable;
+    const output = comptime assembler.assemble(source, .{});
     try std.testing.expect(output.programs.len > 0);
 
     inline for (output.programs) |program| {

From d05e8779b8d3d722540cb21af0a81a3826d46efb Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 22:37:20 -0700
Subject: [PATCH 165/286] workaround for compiler bug where volatile is not
 propagated over a field access (#57)

---
 src/hal/resets.zig | 11 ++++++++---
 1 file changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/hal/resets.zig b/src/hal/resets.zig
index f25d55027..a35ad79e9 100644
--- a/src/hal/resets.zig
+++ b/src/hal/resets.zig
@@ -44,18 +44,23 @@ pub fn reset(mask: Mask) void {
     while ((RESETS.RESET_DONE.raw & raw_mask) != raw_mask) {}
 }
 
-pub fn reset_block(mask: Mask) void {
+pub inline fn reset_block(mask: Mask) void {
     hw.set_alias_raw(&RESETS.RESET).* = @bitCast(u32, mask);
 }
 
-pub fn unreset_block(mask: Mask) void {
+pub inline fn unreset_block(mask: Mask) void {
     hw.clear_alias_raw(&RESETS.RESET).* = @bitCast(u32, mask);
 }
 
 pub fn unreset_block_wait(mask: Mask) void {
     const raw_mask = @bitCast(u32, mask);
     hw.clear_alias_raw(&RESETS.RESET).* = raw_mask;
-    while (RESETS.RESET_DONE.raw & raw_mask != raw_mask) {}
+
+    // have to bitcast after a read() instead of `RESETS.RESET_DONE.raw` due to
+    // some optimization bug. While loops will not be optimzed away if the
+    // condition has side effects like dereferencing a volatile pointer.
+    // It seems that volatile is not propagating correctly.
+    while (@bitCast(u32, RESETS.RESET_DONE.read()) & raw_mask != raw_mask) {}
 }
 
 pub const masks = struct {

From a2ccaff13fb971524bb9d4f54ec204413d6f2956 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 22:50:34 -0700
Subject: [PATCH 166/286] improve GPIO API (#59)

---
 src/hal/adc.zig    |  5 ++-
 src/hal/clocks.zig |  1 -
 src/hal/gpio.zig   | 79 ++++++++++++++++++++++++++--------------------
 src/hal/hw.zig     | 16 ++++++----
 src/hal/pins.zig   |  2 +-
 src/hal/spi.zig    |  6 ++--
 src/hal/util.zig   | 18 -----------
 7 files changed, 60 insertions(+), 67 deletions(-)
 delete mode 100644 src/hal/util.zig

diff --git a/src/hal/adc.zig b/src/hal/adc.zig
index 2f6b96b4a..a77b10223 100644
--- a/src/hal/adc.zig
+++ b/src/hal/adc.zig
@@ -5,9 +5,8 @@ const assert = std.debug.assert;
 
 const microzig = @import("microzig");
 const ADC = microzig.chip.peripherals.ADC;
-const rp2040 = microzig.hal;
-const gpio = rp2040.gpio;
-const resets = rp2040.resets;
+const gpio = @import("gpio.zig");
+const resets = @import("resets.zig");
 
 pub const temperature_sensor = struct {
     pub inline fn init() void {
diff --git a/src/hal/clocks.zig b/src/hal/clocks.zig
index 4a4980964..b13ebd3d8 100644
--- a/src/hal/clocks.zig
+++ b/src/hal/clocks.zig
@@ -1,7 +1,6 @@
 const std = @import("std");
 
 const pll = @import("pll.zig");
-const util = @import("util.zig");
 const assert = std.debug.assert;
 
 // TODO: remove
diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig
index 02f421e48..53d3b0bae 100644
--- a/src/hal/gpio.zig
+++ b/src/hal/gpio.zig
@@ -63,7 +63,7 @@ pub const Enabled = enum {
     enabled,
 };
 
-pub const PullUpDown = enum {
+pub const Pull = enum {
     up,
     down,
 };
@@ -76,12 +76,45 @@ pub fn num(n: u5) Pin {
 }
 
 pub fn mask(m: u32) Mask {
-    _ = m;
-    @panic("TODO");
+    return @intToEnum(Mask, m);
 }
 
 pub const Mask = enum(u30) {
     _,
+
+    pub fn set_function(self: Mask, function: Function) void {
+        const raw_mask = @enumToInt(self);
+        for (0..@bitSizeOf(Mask)) |i| {
+            const bit = @intCast(u5, i);
+            if (0 != raw_mask & (@as(u32, 1) << bit))
+                num(bit).set_function(function);
+        }
+    }
+
+    pub fn set_direction(self: Mask, direction: Direction) void {
+        const raw_mask = @enumToInt(self);
+        switch (direction) {
+            .out => SIO.GPIO_OE_SET.raw = raw_mask,
+            .in => SIO.GPIO_OE_CLR.raw = raw_mask,
+        }
+    }
+
+    pub fn set_pull(self: Mask, pull: ?Pull) void {
+        const raw_mask = @enumToInt(self);
+        for (0..@bitSizeOf(Mask)) |i| {
+            const bit = @intCast(u5, i);
+            if (0 != raw_mask & (@as(u32, 1) << bit))
+                num(bit).set_pull(pull);
+        }
+    }
+
+    pub fn put(self: Mask, value: u32) void {
+        SIO.GPIO_OUT_XOR.raw = (SIO.GPIO_OUT.raw ^ value) & @enumToInt(self);
+    }
+
+    pub fn read(self: Mask) u32 {
+        return SIO.GPIO_IN.raw & @enumToInt(self);
+    }
 };
 
 pub const Pin = enum(u5) {
@@ -134,12 +167,12 @@ pub const Pin = enum(u5) {
         return @as(u32, 1) << @enumToInt(gpio);
     }
 
-    pub inline fn set_pull(gpio: Pin, mode: ?PullUpDown) void {
+    pub inline fn set_pull(gpio: Pin, pull: ?Pull) void {
         const pads_reg = gpio.get_pads_reg();
 
-        if (mode == null) {
+        if (pull == null) {
             pads_reg.modify(.{ .PUE = 0, .PDE = 0 });
-        } else switch (mode.?) {
+        } else switch (pull.?) {
             .up => pads_reg.modify(.{ .PUE = 1, .PDE = 0 }),
             .down => pads_reg.modify(.{ .PUE = 0, .PDE = 1 }),
         }
@@ -171,6 +204,11 @@ pub const Pin = enum(u5) {
             0;
     }
 
+    pub inline fn set_input_enabled(pin: Pin, enabled: bool) void {
+        const pads_reg = pin.get_pads_reg();
+        pads_reg.modify(.{ .IE = @boolToInt(enabled) });
+    }
+
     pub inline fn set_function(gpio: Pin, function: Function) void {
         const pads_reg = gpio.get_pads_reg();
         pads_reg.modify(.{
@@ -193,33 +231,4 @@ pub const Pin = enum(u5) {
             .padding = 0,
         });
     }
-
-    //pub fn set_drive_strength(gpio: Gpio, drive: DriveStrength) void {
-    //    _ = drive;
-    //    const pads_reg = gpio.get_pads_reg();
-    //    pads_reg.modify(.{
-    //        .DRIVE = .{
-    //            .value = .@"12mA",
-    //        },
-    //    });
-    //}
 };
-
-// setting both uplls enables a "bus keep" function, a weak pull to whatever
-// is current high/low state of GPIO
-//pub fn setPulls(gpio: u32, up: bool, down: bool) void {}
-//
-//pub fn pullUp(gpio: u32) void {}
-//
-//pub fn pullDown(gpio: u32) void {}
-//pub fn disablePulls(gpio: u32) void {}
-//pub fn setIrqOver(gpio: u32, value: u32) void {}
-//pub fn setOutOver(gpio: u32, value: u32) void {}
-//pub fn setInOver(gpio: u32, value: u32) void {}
-//pub fn setOeOver(gpio: u32, value: u32) void {}
-//pub fn setInputEnabled(gpio: u32, enabled: Enabled) void {}
-//pub fn setinputHysteresisEnabled(gpio: u32, enabled: Enabled) void {}
-//pub fn setSlewRate(gpio: u32, slew_rate: SlewRate) void {}
-
-//pub fn setIrqEnabled(gpio: u32, events: IrqEvents) void {}
-//pub fn acknowledgeIrq(gpio: u32, events: IrqEvents) void {}
diff --git a/src/hal/hw.zig b/src/hal/hw.zig
index 1017c8a6e..89aee4549 100644
--- a/src/hal/hw.zig
+++ b/src/hal/hw.zig
@@ -19,16 +19,16 @@ const xor_bits = @as(u32, 0x1) << 12;
 const set_bits = @as(u32, 0x2) << 12;
 const clear_bits = @as(u32, 0x3) << 12;
 
-pub fn clear_alias_raw(ptr: anytype) *u32 {
-    return @intToPtr(*u32, @ptrToInt(ptr) | clear_bits);
+pub fn clear_alias_raw(ptr: anytype) *volatile u32 {
+    return @intToPtr(*volatile u32, @ptrToInt(ptr) | clear_bits);
 }
 
-pub fn set_alias_raw(ptr: anytype) *u32 {
-    return @intToPtr(*u32, @ptrToInt(ptr) | set_bits);
+pub fn set_alias_raw(ptr: anytype) *volatile u32 {
+    return @intToPtr(*volatile u32, @ptrToInt(ptr) | set_bits);
 }
 
-pub fn xor_alias_raw(ptr: anytype) *u32 {
-    return @intToPtr(*u32, @ptrToInt(ptr) | xor_bits);
+pub fn xor_alias_raw(ptr: anytype) *volatile u32 {
+    return @intToPtr(*volatile u32, @ptrToInt(ptr) | xor_bits);
 }
 
 pub fn clear_alias(ptr: anytype) @TypeOf(ptr) {
@@ -42,3 +42,7 @@ pub fn set_alias(ptr: anytype) @TypeOf(ptr) {
 pub fn xor_alias(ptr: anytype) @TypeOf(ptr) {
     return @intToPtr(@TypeOf(ptr), @ptrToInt(ptr) | xor_bits);
 }
+
+pub inline fn tight_loop_contents() void {
+    asm volatile ("" ::: "memory");
+}
diff --git a/src/hal/pins.zig b/src/hal/pins.zig
index 1746409cc..f23209255 100644
--- a/src/hal/pins.zig
+++ b/src/hal/pins.zig
@@ -48,7 +48,7 @@ pub const Pin = enum {
         function: Function = .SIO,
         direction: ?gpio.Direction = null,
         drive_strength: ?gpio.DriveStrength = null,
-        pull: ?gpio.PullUpDown = null,
+        pull: ?gpio.Pull = null,
         slew_rate: ?gpio.SlewRate = null,
         // input/output enable
         // schmitt trigger
diff --git a/src/hal/spi.zig b/src/hal/spi.zig
index 717060002..ee02131d7 100644
--- a/src/hal/spi.zig
+++ b/src/hal/spi.zig
@@ -8,7 +8,7 @@ const gpio = @import("gpio.zig");
 const clocks = @import("clocks.zig");
 const resets = @import("resets.zig");
 const time = @import("time.zig");
-const util = @import("util.zig");
+const hw = @import("hw.zig");
 
 const SpiRegs = microzig.chip.types.peripherals.SPI0;
 
@@ -101,7 +101,7 @@ pub const SPI = enum(u1) {
         // push-on-full, but continues shifting. Safe if SSPIMSC_RORIM is not set.
         for (src) |s| {
             while (!spi.is_writable()) {
-                util.tight_loop_contents();
+                hw.tight_loop_contents();
             }
             spi_regs.SSPDR.write_raw(s);
         }
@@ -111,7 +111,7 @@ pub const SPI = enum(u1) {
             _ = spi_regs.SSPDR.read();
         }
         while (spi_regs.SSPSR.read().BSY == 1) {
-            util.tight_loop_contents();
+            hw.tight_loop_contents();
         }
         while (spi.is_readable()) {
             _ = spi_regs.SSPDR.read();
diff --git a/src/hal/util.zig b/src/hal/util.zig
deleted file mode 100644
index 4f0d71c6c..000000000
--- a/src/hal/util.zig
+++ /dev/null
@@ -1,18 +0,0 @@
-pub fn xor_alias(ptr: anytype) @TypeOf(ptr) {
-    const xor_addr = @ptrToInt(ptr) | (1 << 12);
-    return @ptrCast(@TypeOf(ptr), xor_addr);
-}
-
-pub fn set_alias(ptr: anytype) @TypeOf(ptr) {
-    const set_addr = @ptrToInt(ptr) | (2 << 12);
-    return @ptrCast(@TypeOf(ptr), set_addr);
-}
-
-pub fn clear_alias(ptr: anytype) @TypeOf(ptr) {
-    const clear_addr = @ptrToInt(ptr) | (3 << 12);
-    return @ptrCast(@TypeOf(ptr), clear_addr);
-}
-
-pub inline fn tight_loop_contents() void {
-    asm volatile ("" ::: "memory");
-}

From 886234b88284bd90c951b930c98f28681140435b Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Mon, 15 May 2023 23:12:22 -0700
Subject: [PATCH 167/286] improve timer API (#60)

---
 examples/usb_device.zig |  4 ++--
 examples/usb_hid.zig    |  4 ++--
 src/hal/time.zig        | 35 +++++++++++++++++------------------
 src/hal/uart.zig        |  4 ++--
 4 files changed, 23 insertions(+), 24 deletions(-)

diff --git a/examples/usb_device.zig b/examples/usb_device.zig
index 3395286cd..252db521f 100644
--- a/examples/usb_device.zig
+++ b/examples/usb_device.zig
@@ -154,7 +154,7 @@ pub fn main() !void {
     rp2040.usb.Usb.init_clk();
     // Then initialize the USB device using the configuration defined above
     rp2040.usb.Usb.init_device(&DEVICE_CONFIGURATION) catch unreachable;
-    var old: u64 = time.get_time_since_boot().us_since_boot;
+    var old: u64 = time.get_time_since_boot().to_us();
     var new: u64 = 0;
     while (true) {
         // You can now poll for USB events
@@ -162,7 +162,7 @@ pub fn main() !void {
             false, // debug output over UART [Y/n]
         ) catch unreachable;
 
-        new = time.get_time_since_boot().us_since_boot;
+        new = time.get_time_since_boot().to_us();
         if (new - old > 500000) {
             old = new;
             led.toggle();
diff --git a/examples/usb_hid.zig b/examples/usb_hid.zig
index 051ad746c..a19a3e067 100644
--- a/examples/usb_hid.zig
+++ b/examples/usb_hid.zig
@@ -169,7 +169,7 @@ pub fn main() !void {
     rp2040.usb.Usb.init_clk();
     // Then initialize the USB device using the configuration defined above
     rp2040.usb.Usb.init_device(&DEVICE_CONFIGURATION) catch unreachable;
-    var old: u64 = time.get_time_since_boot().us_since_boot;
+    var old: u64 = time.get_time_since_boot().to_us();
     var new: u64 = 0;
     while (true) {
         // You can now poll for USB events
@@ -177,7 +177,7 @@ pub fn main() !void {
             true, // debug output over UART [Y/n]
         ) catch unreachable;
 
-        new = time.get_time_since_boot().us_since_boot;
+        new = time.get_time_since_boot().to_us();
         if (new - old > 500000) {
             old = new;
             led.toggle();
diff --git a/src/hal/time.zig b/src/hal/time.zig
index 3b568bf5a..d7f815bc4 100644
--- a/src/hal/time.zig
+++ b/src/hal/time.zig
@@ -1,8 +1,19 @@
 const microzig = @import("microzig");
 const TIMER = microzig.chip.peripherals.TIMER;
 
-pub const Absolute = struct {
-    us_since_boot: u64,
+/// Using an enum to make it a distinct type, the underlying number is
+/// time since boot in microseconds.
+pub const Absolute = enum(u64) {
+    _,
+
+    pub fn reached(time: Absolute) bool {
+        const now = get_time_since_boot();
+        return now.to_us() >= time.to_us();
+    }
+
+    pub fn to_us(time: Absolute) u64 {
+        return @enumToInt(time);
+    }
 };
 
 pub fn get_time_since_boot() Absolute {
@@ -12,23 +23,14 @@ pub fn get_time_since_boot() Absolute {
         var low_word = TIMER.TIMERAWL;
         const next_high_word = TIMER.TIMERAWH;
         if (next_high_word == high_word)
-            break Absolute{
-                .us_since_boot = @intCast(u64, high_word) << 32 | low_word,
-            };
+            break @intToEnum(Absolute, @intCast(u64, high_word) << 32 | low_word);
 
         high_word = next_high_word;
     } else unreachable;
 }
 
 pub fn make_timeout_us(timeout_us: u64) Absolute {
-    return Absolute{
-        .us_since_boot = get_time_since_boot().us_since_boot + timeout_us,
-    };
-}
-
-pub fn reached(time: Absolute) bool {
-    const now = get_time_since_boot();
-    return now.us_since_boot >= time.us_since_boot;
+    return @intToEnum(Absolute, get_time_since_boot().to_us() + timeout_us);
 }
 
 pub fn sleep_ms(time_ms: u32) void {
@@ -36,9 +38,6 @@ pub fn sleep_ms(time_ms: u32) void {
 }
 
 pub fn sleep_us(time_us: u64) void {
-    const end_time = Absolute{
-        .us_since_boot = time_us + get_time_since_boot().us_since_boot,
-    };
-
-    while (!reached(end_time)) {}
+    const end_time = make_timeout_us(time_us);
+    while (!end_time.reached()) {}
 }
diff --git a/src/hal/uart.zig b/src/hal/uart.zig
index 6a08b852d..b7a9b114f 100644
--- a/src/hal/uart.zig
+++ b/src/hal/uart.zig
@@ -219,8 +219,8 @@ pub fn log(
 
     if (uart_logger) |uart| {
         const current_time = time.get_time_since_boot();
-        const seconds = current_time.us_since_boot / std.time.us_per_s;
-        const microseconds = current_time.us_since_boot % std.time.us_per_s;
+        const seconds = current_time.to_us() / std.time.us_per_s;
+        const microseconds = current_time.to_us() % std.time.us_per_s;
 
         uart.print(prefix ++ format ++ "\r\n", .{ seconds, microseconds } ++ args) catch {};
     }

From abff6d1f4bec6804bd42b7dabaed3f6fae3f196d Mon Sep 17 00:00:00 2001
From: Vlad Panazan 
Date: Thu, 18 May 2023 00:39:54 +0300
Subject: [PATCH 168/286] add ws2812 pio example (#54)

---
 build.zig           |  1 +
 examples/ws2812.zig | 94 +++++++++++++++++++++++++++++++++++++++++++++
 src/hal/pio.zig     |  4 +-
 3 files changed, 97 insertions(+), 2 deletions(-)
 create mode 100644 examples/ws2812.zig

diff --git a/build.zig b/build.zig
index 1ee7e1716..4afab69d2 100644
--- a/build.zig
+++ b/build.zig
@@ -71,6 +71,7 @@ pub const Examples = struct {
     flash_program: *microzig.EmbeddedExecutable,
     usb_device: *microzig.EmbeddedExecutable,
     usb_hid: *microzig.EmbeddedExecutable,
+    ws2812: *microzig.EmbeddedExecutable,
     random: *microzig.EmbeddedExecutable,
 
     pub fn init(b: *Builder, optimize: std.builtin.OptimizeMode) Examples {
diff --git a/examples/ws2812.zig b/examples/ws2812.zig
new file mode 100644
index 000000000..e51d9730d
--- /dev/null
+++ b/examples/ws2812.zig
@@ -0,0 +1,94 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const rp2040 = microzig.hal;
+const gpio = rp2040.gpio;
+const Pio = rp2040.pio.Pio;
+const StateMachine = rp2040.pio.StateMachine;
+
+const ws2812_program = blk: {
+    @setEvalBranchQuota(5000);
+    break :blk rp2040.pio.assemble(
+        \\;
+        \\; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+        \\;
+        \\; SPDX-License-Identifier: BSD-3-Clause
+        \\;
+        \\.program ws2812
+        \\.side_set 1
+        \\
+        \\.define public T1 2
+        \\.define public T2 5
+        \\.define public T3 3
+        \\
+        \\.wrap_target
+        \\bitloop:
+        \\    out x, 1       side 0 [T3 - 1] ; Side-set still takes place when instruction stalls
+        \\    jmp !x do_zero side 1 [T1 - 1] ; Branch on the bit we shifted out. Positive pulse
+        \\do_one:
+        \\    jmp  bitloop   side 1 [T2 - 1] ; Continue driving high, for a long pulse
+        \\do_zero:
+        \\    nop            side 0 [T2 - 1] ; Or drive low, for a short pulse
+        \\.wrap
+    , .{}).get_program_by_name("ws2812");
+};
+
+const pio: Pio = .pio0;
+const sm: StateMachine = .sm0;
+const led_pin = gpio.num(23);
+
+pub fn main() void {
+    pio.gpio_init(led_pin);
+    sm_set_consecutive_pindirs(pio, sm, @enumToInt(led_pin), 1, true);
+
+    const cycles_per_bit: comptime_int = ws2812_program.defines[0].value + //T1
+        ws2812_program.defines[1].value + //T2
+        ws2812_program.defines[2].value; //T3
+    const div = @intToFloat(f32, rp2040.clock_config.sys.?.output_freq) /
+        (800_000 * cycles_per_bit);
+
+    pio.sm_load_and_start_program(sm, ws2812_program, .{
+        .clkdiv = rp2040.pio.ClkDivOptions.from_float(div),
+        .pin_mappings = .{
+            .side_set = .{
+                .base = @enumToInt(led_pin),
+                .count = 1,
+            },
+        },
+        .shift = .{
+            .out_shiftdir = .left,
+            .autopull = true,
+            .pull_threshold = 24,
+            .join_tx = true,
+        },
+    }) catch unreachable;
+    pio.sm_set_enabled(sm, true);
+
+    while (true) {
+        pio.sm_blocking_write(sm, 0x00ff00 << 8); //red
+        rp2040.time.sleep_ms(1000);
+        pio.sm_blocking_write(sm, 0xff0000 << 8); //green
+        rp2040.time.sleep_ms(1000);
+        pio.sm_blocking_write(sm, 0x0000ff << 8); //blue
+        rp2040.time.sleep_ms(1000);
+    }
+}
+
+fn sm_set_consecutive_pindirs(_pio: Pio, _sm: StateMachine, pin: u5, count: u3, is_out: bool) void {
+    const sm_regs = _pio.get_sm_regs(_sm);
+    const pinctrl_saved = sm_regs.pinctrl.raw;
+    sm_regs.pinctrl.modify(.{
+        .SET_BASE = pin,
+        .SET_COUNT = count,
+    });
+    _pio.sm_exec(_sm, rp2040.pio.Instruction{
+        .tag = .set,
+        .delay_side_set = 0,
+        .payload = .{
+            .set = .{
+                .data = @boolToInt(is_out),
+                .destination = .pindirs,
+            },
+        },
+    });
+    sm_regs.pinctrl.raw = pinctrl_saved;
+}
diff --git a/src/hal/pio.zig b/src/hal/pio.zig
index 2eb17096f..2943a3f26 100644
--- a/src/hal/pio.zig
+++ b/src/hal/pio.zig
@@ -226,7 +226,7 @@ pub const Pio = enum(u1) {
         } else error.NoSpace;
     }
 
-    fn get_sm_regs(self: Pio, sm: StateMachine) *volatile StateMachine.Regs {
+    pub fn get_sm_regs(self: Pio, sm: StateMachine) *volatile StateMachine.Regs {
         const pio_regs = self.get_regs();
         const sm_regs = @ptrCast(*volatile [4]StateMachine.Regs, &pio_regs.SM0_CLKDIV);
         return &sm_regs[@enumToInt(sm)];
@@ -480,7 +480,7 @@ pub const Pio = enum(u1) {
     ) !void {
         const expected_side_set_pins = if (program.side_set) |side_set|
             if (side_set.optional)
-                side_set.count - 1
+                side_set.count + 1
             else
                 side_set.count
         else

From d1e35696d430c10fa3b2346d3137a81c122dc90b Mon Sep 17 00:00:00 2001
From: Hubert Jasudowicz 
Date: Thu, 18 May 2023 09:24:18 +0200
Subject: [PATCH 169/286] examples: Set LED GPIO function (#61)

Set the pin function to SIO instead of null (default).
---
 examples/blinky_core1.zig  | 1 +
 examples/flash_program.zig | 1 +
 examples/random.zig        | 1 +
 examples/uart.zig          | 1 +
 examples/usb_device.zig    | 1 +
 examples/usb_hid.zig       | 1 +
 6 files changed, 6 insertions(+)

diff --git a/examples/blinky_core1.zig b/examples/blinky_core1.zig
index 64f067468..06157295b 100644
--- a/examples/blinky_core1.zig
+++ b/examples/blinky_core1.zig
@@ -18,6 +18,7 @@ fn core1() void {
 }
 
 pub fn main() !void {
+    led.set_function(.sio);
     led.set_direction(.out);
     multicore.launch_core1(core1);
 
diff --git a/examples/flash_program.zig b/examples/flash_program.zig
index a2999c9d8..4bae76959 100644
--- a/examples/flash_program.zig
+++ b/examples/flash_program.zig
@@ -28,6 +28,7 @@ pub const std_options = struct {
 };
 
 pub fn main() !void {
+    led.set_function(.sio);
     led.set_direction(.out);
     led.put(1);
 
diff --git a/examples/random.zig b/examples/random.zig
index 0645839d1..151482e2c 100644
--- a/examples/random.zig
+++ b/examples/random.zig
@@ -28,6 +28,7 @@ pub const std_options = struct {
 };
 
 pub fn main() !void {
+    led.set_function(.sio);
     led.set_direction(.out);
     led.put(1);
 
diff --git a/examples/uart.zig b/examples/uart.zig
index 6be3b3869..914b9ae98 100644
--- a/examples/uart.zig
+++ b/examples/uart.zig
@@ -24,6 +24,7 @@ pub const std_options = struct {
 };
 
 pub fn main() !void {
+    led.set_function(.sio);
     led.set_direction(.out);
     led.put(1);
 
diff --git a/examples/usb_device.zig b/examples/usb_device.zig
index 252db521f..27d961d11 100644
--- a/examples/usb_device.zig
+++ b/examples/usb_device.zig
@@ -138,6 +138,7 @@ pub const std_options = struct {
 };
 
 pub fn main() !void {
+    led.set_function(.sio);
     led.set_direction(.out);
     led.put(1);
 
diff --git a/examples/usb_hid.zig b/examples/usb_hid.zig
index a19a3e067..34b9a1205 100644
--- a/examples/usb_hid.zig
+++ b/examples/usb_hid.zig
@@ -153,6 +153,7 @@ pub const std_options = struct {
 };
 
 pub fn main() !void {
+    led.set_function(.sio);
     led.set_direction(.out);
     led.put(1);
 

From 7b7caa9eb40ca87db79958aeadd2e40155c1ab95 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 18 May 2023 20:51:23 -0700
Subject: [PATCH 170/286] improve ADC API (#62)

---
 examples/adc.zig |  12 +-
 src/hal/adc.zig  | 386 +++++++++++++++++++++++++++++++----------------
 2 files changed, 262 insertions(+), 136 deletions(-)

diff --git a/examples/adc.zig b/examples/adc.zig
index b6d6bf4ff..ff180dd53 100644
--- a/examples/adc.zig
+++ b/examples/adc.zig
@@ -7,7 +7,6 @@ const gpio = rp2040.gpio;
 const adc = rp2040.adc;
 const time = rp2040.time;
 
-const temp_sensor: adc.Input = .temperature_sensor;
 const uart = rp2040.uart.num(0);
 const baud_rate = 115200;
 const uart_tx_pin = gpio.num(0);
@@ -18,6 +17,10 @@ pub const std_options = struct {
 };
 
 pub fn main() void {
+    adc.apply(.{
+        .temp_sensor_enabled = true,
+    });
+
     uart.apply(.{
         .baud_rate = baud_rate,
         .tx_pin = uart_tx_pin,
@@ -26,9 +29,12 @@ pub fn main() void {
     });
 
     rp2040.uart.init_logger(uart);
-
     while (true) : (time.sleep_ms(1000)) {
-        const sample = temp_sensor.read();
+        const sample = adc.convert_one_shot_blocking(.temp_sensor) catch {
+            std.log.err("conversion failed!", .{});
+            continue;
+        };
+
         std.log.info("temp value: {}", .{sample});
     }
 }
diff --git a/src/hal/adc.zig b/src/hal/adc.zig
index a77b10223..592273bd4 100644
--- a/src/hal/adc.zig
+++ b/src/hal/adc.zig
@@ -7,196 +7,316 @@ const microzig = @import("microzig");
 const ADC = microzig.chip.peripherals.ADC;
 const gpio = @import("gpio.zig");
 const resets = @import("resets.zig");
+const clocks = @import("clocks.zig");
 
-pub const temperature_sensor = struct {
-    pub inline fn init() void {
-        set_temp_sensor_enabled(true);
-    }
-
-    pub inline fn deinit() void {
-        set_temp_sensor_enabled(false);
-    }
-
-    pub inline fn read_raw() u16 {
-        return Input.read(.temperature_sensor);
-    }
-
-    // One-shot conversion returning the temperature in Celcius
-    pub inline fn read(comptime T: type, comptime Vref: T) T {
-        // TODO: consider fixed-point
-        const raw = @intToFloat(T, read_raw());
-        const voltage: T = Vref * raw / 0x0fff;
-        return (27.0 - ((voltage - 0.706) / 0.001721));
-    }
+pub const Error = error{
+    /// ADC conversion failed, one such reason is that the controller failed to
+    /// converge on a result.
+    Conversion,
 };
 
-pub const Input = enum(u3) {
-    ain0,
-    ain1,
-    ain2,
-    ain3,
-    temperature_sensor,
-
-    /// Setup the GPIO pin as an ADC input
-    pub fn init(comptime input: Input) void {
-        switch (input) {
-            .temperature_sensor => set_temp_sensor_enabled(true),
-            else => {
-                const pin = gpio.num(@as(u5, @enumToInt(input)) + 26);
-                pin.set_function(.null);
-
-                // TODO: implement these, otherwise adc isn't going to work.
-                //gpio.disablePulls(gpio_num);
-                //gpio.setInputEnabled(gpio_num, false);
-            },
-        }
-    }
-
-    /// Disables temp sensor, otherwise it does nothing if the input is
-    /// one of the others.
-    pub inline fn deinit(input: Input) void {
-        switch (input) {
-            .temperature_sensor => set_temp_sensor_enabled(true),
-            else => {},
-        }
-    }
-
-    /// Single-shot, blocking conversion
-    pub fn read(input: Input) u12 {
-        // TODO: not sure if setting these during the same write is
-        // correct
-        ADC.CS.modify(.{
-            .AINSEL = @enumToInt(input),
-            .START_ONCE = 1,
-        });
-
-        // wait for the
-        while (ADC.CS.read().READY == 0) {}
-
-        return ADC.RESULT.read().RESULT;
-    }
-};
+/// temp_sensor is not valid because you can refer to it by name.
+pub fn input(n: u2) Input {
+    return @intToEnum(Input, n);
+}
 
-pub const InputMask = InputMask: {
-    const enum_fields = @typeInfo(Input).Enum.fields;
-    var fields: [enum_fields.len]std.builtin.Type.StructField = undefined;
-
-    const default_value: u1 = 0;
-    for (enum_fields, &fields) |enum_field, *field|
-        field = std.builtin.Type.StructField{
-            .name = enum_field.name,
-            .field_type = u1,
-            .default_value = &default_value,
-            .is_comptime = false,
-            .alignment = 1,
-        };
+/// Enable the ADC controller.
+pub fn set_enabled(enabled: bool) void {
+    ADC.CS.modify(.{ .EN = @boolToInt(enabled) });
+}
 
-    break :InputMask @Type(.{
-        .Struct = .{
-            .layout = .Packed,
-            .fields = &fields,
-            .backing_integer = std.meta.Int(.Unsigned, enum_fields.len),
-            .decls = &.{},
-            .is_tuple = false,
-        },
-    });
+const Config = struct {
+    /// Note that this frequency is the sample frequency of the controller, not
+    /// each input. So for 4 inputs in round-robin mode you'd see 1/4 sample
+    /// rate for a given put vs what is set here.
+    sample_frequency: ?u32 = null,
+    round_robin: ?InputMask = null,
+    fifo: ?fifo.Config = null,
+    temp_sensor_enabled: bool = false,
 };
 
-/// Initialize ADC hardware
-pub fn init() void {
+/// Applies configuration to ADC, leaves it in an enabled state by setting
+/// CS.EN = 1. The global clock configuration is not needed to configure the
+/// sample rate because the ADC hardware block requires a 48MHz clock.
+pub fn apply(config: Config) void {
     ADC.CS.write(.{
-        .EN = 1,
-        .TS_EN = 0,
+        .EN = 0,
+        .TS_EN = @boolToInt(config.temp_sensor_enabled),
         .START_ONCE = 0,
         .START_MANY = 0,
         .READY = 0,
+
         .ERR = 0,
         .ERR_STICKY = 0,
         .AINSEL = 0,
-        .RROBIN = 0,
+        .RROBIN = if (config.round_robin) |rr|
+            @bitCast(u5, rr)
+        else
+            0,
 
         .reserved8 = 0,
         .reserved12 = 0,
         .reserved16 = 0,
         .padding = 0,
     });
-    while (ADC.CS.read().READY == 0) {}
-}
 
-/// Enable/disable ADC interrupt
-pub inline fn irq_set_enabled(enable: bool) void {
-    // TODO: check if this works
-    ADC.INTE.write(.{ .FIFO = if (enable) @as(u1, 1) else @as(u1, 0) });
+    if (config.sample_frequency) |sample_frequency| {
+        const cycles = (48_000_000 * 256) / @as(u64, sample_frequency);
+        ADC.DIV.write(.{
+            .FRAC = @truncate(u8, cycles),
+            .INT = @intCast(u16, (cycles >> 8) - 1),
+
+            .padding = 0,
+        });
+    }
+
+    if (config.fifo) |fifo_config|
+        fifo.apply(fifo_config);
+
+    set_enabled(true);
 }
 
 /// Select analog input for next conversion.
-pub inline fn select_input(input: Input) void {
-    ADC.CS.modify(.{ .AINSEL = @enumToInt(input) });
+pub fn select_input(in: Input) void {
+    ADC.CS.modify(.{ .AINSEL = @enumToInt(in) });
 }
 
 /// Get the currently selected analog input. 0..3 are GPIO 26..29 respectively,
 /// 4 is the temperature sensor.
-pub inline fn get_selected_input() Input {
-    // TODO: ensure that the field shouldn't have other values
-    return @intToEnum(Input, ADC.CS.read().AINSEL);
+pub fn get_selected_input() Input {
+    const cs = ADC.SC.read();
+    return @intToEnum(Input, cs.AINSEL);
 }
 
+pub const Input = enum(u3) {
+    /// The temperature sensor must be enabled using
+    /// `set_temp_sensor_enabled()` in order to use it
+    temp_sensor = 5,
+    _,
+
+    /// Get the corresponding GPIO pin for an ADC input. Panics if you give it
+    /// temp_sensor.
+    pub fn get_gpio_pin(in: Input) gpio.Pin {
+        return switch (in) {
+            else => gpio.num(@as(u5, @enumToInt(in)) + 26),
+            .temp_sensor => @panic("temp_sensor doesn't have a pin"),
+        };
+    }
+
+    /// Prepares an ADC input's corresponding GPIO pin to be used as an analog
+    /// input.
+    pub fn configure_gpio_pin(in: Input) void {
+        switch (in) {
+            else => {
+                const pin = in.get_gpio_pin();
+                pin.set_function(.null);
+                pin.set_pull(null);
+                pin.set_input_enabled(false);
+            },
+            .temp_sensor => {},
+        }
+    }
+};
+
 /// Set to true to power on the temperature sensor.
-pub inline fn set_temp_sensor_enabled(enable: bool) void {
-    ADC.CS.modify(.{ .TS_EN = if (enable) @as(u1, 1) else @as(u1, 0) });
+pub fn set_temp_sensor_enabled(enable: bool) void {
+    ADC.CS.modify(.{ .TS_EN = @boolToInt(enable) });
+}
+
+/// T must be floating point.
+pub fn temp_sensor_result_to_celcius(comptime T: type, comptime vref: T, result: u12) T {
+    // TODO: consider fixed-point
+    const raw = @intToFloat(T, result);
+    const voltage: T = vref * raw / 0x0fff;
+    return (27.0 - ((voltage - 0.706) / 0.001721));
 }
 
+/// For selecting which inputs are to be used in round-robin mode
+pub const InputMask = packed struct(u5) {
+    ain0: bool = false,
+    ain1: bool = false,
+    ain2: bool = false,
+    ain3: bool = false,
+    temp_sensor: bool = false,
+};
+
 /// Sets which of the inputs are to be run in round-robin mode. Setting all to
 /// 0 will disable round-robin mode but `disableRoundRobin()` is provided so
 /// the user may be explicit.
-pub inline fn set_round_robin(comptime enabled_inputs: InputMask) void {
+pub fn round_robin_set(enabled_inputs: InputMask) void {
     ADC.CS.modify(.{ .RROBIN = @bitCast(u5, enabled_inputs) });
 }
 
 /// Disable round-robin sample mode.
-pub inline fn disable_round_robin() void {
+pub fn round_robin_disable() void {
     ADC.CS.modify(.{ .RROBIN = 0 });
 }
 
-/// Enable free-running sample mode.
-pub inline fn run(enable: bool) void {
-    ADC.CS.modify(.{ .START_MANY = if (enable) @as(u1, 1) else @as(u1, 0) });
+pub const Mode = enum {
+    one_shot,
+    free_running,
+};
+
+/// Start the ADC controller. There are three "modes" that the controller
+/// operates in:
+///
+/// - one shot: the input is selected and then conversion is started. The
+///   controller stops once the conversion is complete.
+///
+/// - free running single input: the input is selected and then the conversion
+///   is started. Once a conversion is complete the controller begins another
+///   on the same input.
+///
+/// - free running round-robin: a mask of which inputs to sample is set using
+///   `round_robin_set()`. Once conversion is completed for one input, a
+///   conversion is started for the next set input in the mask.
+pub fn start(mode: Mode) void {
+    switch (mode) {
+        .one_shot => ADC.CS.modify(.{
+            .START_ONCE = 1,
+        }),
+        .free_running => ADC.CS.modify(.{
+            .START_MANY = 1,
+        }),
+    }
+}
+
+/// Check whether the ADC controller has a conversion result
+pub fn is_ready() bool {
+    const cs = ADC.CS.read();
+    return cs.READY != 0;
 }
 
-pub inline fn set_clk_div() void {
-    @compileError("todo");
+/// Single-shot, blocking conversion
+pub fn convert_one_shot_blocking(in: Input) Error!u12 {
+    select_input(in);
+    start(.one_shot);
+
+    while (!is_ready()) {}
+
+    return read_result();
 }
 
-/// The fifo is 4 samples long, if a conversion is completed and the FIFO is
-/// full, the result is dropped.
+/// Read conversion result from ADC controller, this function assumes that the
+/// controller has a result ready.
+pub fn read_result() Error!u12 {
+    const cs = ADC.CS.read();
+    return if (cs.ERR == 1)
+        error.Conversion
+    else blk: {
+        const conversion = ADC.RESULT.read();
+        break :blk conversion.RESULT;
+    };
+}
+
+/// The ADC FIFO can store up to four conversion results. It must be enabled in
+/// order to use DREQ or IRQ driven streaming.
 pub const fifo = struct {
-    pub inline fn setup() void {
-        @compileError("todo");
-        // There are a number of considerations wrt DMA and error detection
+    // TODO: what happens when DMA and IRQ are enabled?
+    pub const Config = struct {
+        /// Assert DMA requests when the fifo contains data
+        dreq_enabled: bool = false,
+        /// Assert Interrupt when fifo contains data
+        irq_enabled: bool = false,
+        /// DREQ/IRQ asserted when level >= threshold
+        thresh: u4 = 0,
+        /// Shift the conversion so it's 8-bit, good for DMAing to a byte
+        /// buffer
+        shift: bool = false,
+    };
+
+    /// Apply ADC FIFO configuration and enable it
+    pub fn apply(config: fifo.Config) void {
+        ADC.FCS.write(.{
+            .DREQ_EN = @boolToInt(config.dreq_enabled),
+            .THRESH = config.thresh,
+            .SHIFT = @boolToInt(config.shift),
+
+            .EN = 1,
+            .EMPTY = 0,
+            .FULL = 0,
+            .LEVEL = 0,
+
+            // As far as it is known, there is zero cost to being able to
+            // report errors in the FIFO, so let's.
+            .ERR = 1,
+
+            // Writing 1 to these will clear them if they're already set
+            .UNDER = 1,
+            .OVER = 1,
+
+            .reserved8 = 0,
+            .reserved16 = 0,
+            .reserved24 = 0,
+            .padding = 0,
+        });
+
+        irq_set_enabled(config.irq_enabled);
+    }
+
+    // TODO: do we need to acknowledge an ADC interrupt?
+
+    /// Enable/disable ADC interrupt.
+    pub fn irq_set_enabled(enable: bool) void {
+        // TODO: check if this works
+        ADC.INTE.write(.{
+            .FIFO = @boolToInt(enable),
+            .padding = 0,
+        });
+    }
+
+    /// Check if the ADC FIFO is full.
+    pub fn is_full() bool {
+        const fsc = ADC.FSC.read();
+        return fsc.FULL != 0;
+    }
+
+    /// Check if the ADC FIFO is empty.
+    pub fn is_empty() bool {
+        const fsc = ADC.FSC.read();
+        return fsc.EMPTY != 0;
+    }
+
+    /// Get the number of conversion in the ADC FIFO.
+    pub fn get_level() u4 {
+        const fsc = ADC.FSC.read();
+        return fsc.LEVEL;
     }
 
-    /// Return true if FIFO is empty.
-    pub inline fn is_empty() bool {
-        @compileError("todo");
+    /// Check if the ADC FIFO has overflowed. When overflow happens, the new
+    /// conversion is discarded. This flag is sticky, to clear it call
+    /// `clear_overflowed()`.
+    pub fn has_overflowed() bool {
+        const fsc = ADC.FSC.read();
+        return fsc.OVER != 0;
     }
 
-    /// Read how many samples are in the FIFO.
-    pub inline fn get_level() u8 {
-        @compileError("todo");
+    /// Clear the overflow status flag if it is set.
+    pub fn clear_overflowed() void {
+        ADC.FSC.modify(.{ .OVER = 1 });
     }
 
-    /// Pop latest result from FIFO.
-    pub inline fn get() u16 {
-        @compileError("todo");
+    /// Check if the ADC FIFO has underflowed. This means that the FIFO
+    /// register was read while the FIFO was empty. This flag is sticky, to
+    /// clear it call `clear_underflowed()`.
+    pub fn has_underflowed() bool {
+        const fsc = ADC.FSC.read();
+        return fsc.UNDER != 0;
     }
 
-    /// Block until result is available in FIFO, then pop it.
-    pub inline fn get_blocking() u16 {
-        @compileError("todo");
+    /// Clear the underflow status flag if it is set.
+    pub fn clear_underflowed() void {
+        ADC.FSC.modify(.{ .UNDER = 1 });
     }
 
-    /// Wait for conversion to complete then discard results in FIFO.
-    pub inline fn drain() void {
-        @compileError("todo");
+    /// Pop conversion from ADC FIFO. This function assumes that the FIFO is
+    /// not empty.
+    pub fn pop() Error!u12 {
+        assert(!is_empty());
+        const result = ADC.FIFO.read();
+        return if (result.ERR == 1)
+            error.Conversion
+        else
+            result.VAL;
     }
 };

From 316e241a88fa3c131e22ea421123794eb67604a7 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 30 May 2023 22:31:44 -0700
Subject: [PATCH 171/286] DMA API, and time API improvements from SYCL 2023
 workshop (#63)

---
 src/hal/dma.zig  | 56 +++++++++++++++++++++++++++---------------------
 src/hal/time.zig | 52 ++++++++++++++++++++++++++++++++++++++++----
 2 files changed, 80 insertions(+), 28 deletions(-)

diff --git a/src/hal/dma.zig b/src/hal/dma.zig
index 248e333b0..ded0a8c04 100644
--- a/src/hal/dma.zig
+++ b/src/hal/dma.zig
@@ -7,7 +7,8 @@ const DMA = chip.peripherals.DMA;
 
 const hw = @import("hw.zig");
 
-var claimed_channels: u12 = 0;
+const num_channels = 12;
+var claimed_channels = std.PackedIntArray(bool, num_channels).initAllTo(false);
 
 pub const Dreq = enum(u6) {
     uart0_tx = 20,
@@ -15,31 +16,38 @@ pub const Dreq = enum(u6) {
     _,
 };
 
-pub fn num(n: u4) Channel {
-    assert(n < 12);
+pub fn channel(n: u4) Channel {
+    assert(n < num_channels);
 
     return @intToEnum(Channel, n);
 }
 
-pub fn claim_unused_channel() ?Channel {}
+pub fn claim_unused_channel() ?Channel {
+    for (0..num_channels) |i| {
+        if (claimed_channels.get(i)) {
+            claimed_channels.set(i, true);
+            return channel(i);
+        }
+    }
+
+    return null;
+}
 
 pub const Channel = enum(u4) {
     _,
 
     /// panics if the channel is already claimed
-    pub fn claim(channel: Channel) void {
-        _ = channel;
-        @panic("TODO");
+    pub fn claim(chan: Channel) void {
+        if (chan.is_claimed())
+            @panic("channel is already claimed!");
     }
 
-    pub fn unclaim(channel: Channel) void {
-        _ = channel;
-        @panic("TODO");
+    pub fn unclaim(chan: Channel) void {
+        claimed_channels.set(@enumToInt(chan), false);
     }
 
-    pub fn is_claimed(channel: Channel) bool {
-        _ = channel;
-        @panic("TODO");
+    pub fn is_claimed(chan: Channel) bool {
+        return claimed_channels.get(@enumToInt(chan));
     }
 
     const Regs = extern struct {
@@ -67,9 +75,9 @@ pub const Channel = enum(u4) {
         al3_trans_count: u32,
     };
 
-    fn get_regs(channel: Channel) *volatile Regs {
+    fn get_regs(chan: Channel) *volatile Regs {
         const regs = @ptrCast(*volatile [12]Regs, &DMA.CH0_READ_ADDR);
-        return ®s[@enumToInt(channel)];
+        return ®s[@enumToInt(chan)];
     }
 
     pub const TransferConfig = struct {
@@ -86,13 +94,13 @@ pub const Channel = enum(u4) {
     };
 
     pub fn trigger_transfer(
-        channel: Channel,
+        chan: Channel,
         write_addr: u32,
         read_addr: u32,
         count: u32,
         config: TransferConfig,
     ) void {
-        const regs = channel.get_regs();
+        const regs = chan.get_regs();
         regs.read_addr = read_addr;
         regs.write_addr = write_addr;
         regs.trans_count = count;
@@ -109,23 +117,23 @@ pub const Channel = enum(u4) {
         });
     }
 
-    pub fn set_irq0_enabled(channel: Channel, enabled: bool) void {
+    pub fn set_irq0_enabled(chan: Channel, enabled: bool) void {
         if (enabled) {
             const inte0_set = hw.set_alias_raw(&DMA.INTE0);
-            inte0_set.* = @as(u32, 1) << @enumToInt(channel);
+            inte0_set.* = @as(u32, 1) << @enumToInt(chan);
         } else {
             const inte0_clear = hw.clear_alias_raw(&DMA.INTE0);
-            inte0_clear.* = @as(u32, 1) << @enumToInt(channel);
+            inte0_clear.* = @as(u32, 1) << @enumToInt(chan);
         }
     }
 
-    pub fn acknowledge_irq0(channel: Channel) void {
+    pub fn acknowledge_irq0(chan: Channel) void {
         const ints0_set = hw.set_alias_raw(&DMA.INTS0);
-        ints0_set.* = @as(u32, 1) << @enumToInt(channel);
+        ints0_set.* = @as(u32, 1) << @enumToInt(chan);
     }
 
-    pub fn is_busy(channel: Channel) bool {
-        const regs = channel.get_regs();
+    pub fn is_busy(chan: Channel) bool {
+        const regs = chan.get_regs();
         return regs.ctrl_trig.read().BUSY == 1;
     }
 };
diff --git a/src/hal/time.zig b/src/hal/time.zig
index d7f815bc4..e6cace556 100644
--- a/src/hal/time.zig
+++ b/src/hal/time.zig
@@ -6,14 +6,58 @@ const TIMER = microzig.chip.peripherals.TIMER;
 pub const Absolute = enum(u64) {
     _,
 
-    pub fn reached(time: Absolute) bool {
-        const now = get_time_since_boot();
-        return now.to_us() >= time.to_us();
+    pub fn from_us(us: u64) Absolute {
+        return @intToEnum(Absolute, us);
     }
 
     pub fn to_us(time: Absolute) u64 {
         return @enumToInt(time);
     }
+
+    pub fn is_reached_by(deadline: Absolute, point: Absolute) bool {
+        return deadline.to_us() <= point.to_us();
+    }
+
+    pub fn is_reached(time: Absolute) bool {
+        const now = get_time_since_boot();
+        return time.is_reached_by(now);
+    }
+
+    pub fn diff(future: Absolute, past: Absolute) Duration {
+        return Duration.from_us(future.to_us() - past.to_us());
+    }
+
+    pub fn add_duration(time: Absolute, dur: Duration) Absolute {
+        return Absolute.from_us(time.to_us() + dur.to_us());
+    }
+};
+
+pub const Duration = enum(u64) {
+    _,
+
+    pub fn from_us(us: u64) Duration {
+        return @intToEnum(Duration, us);
+    }
+
+    pub fn from_ms(ms: u64) Duration {
+        return from_us(1000 * ms);
+    }
+
+    pub fn to_us(duration: Duration) u64 {
+        return @enumToInt(duration);
+    }
+
+    pub fn less_than(self: Duration, other: Duration) bool {
+        return self.to_us() < other.to_us();
+    }
+
+    pub fn minus(self: Duration, other: Duration) Duration {
+        return from_us(self.to_us() - other.to_us());
+    }
+
+    pub fn plus(self: Duration, other: Duration) Duration {
+        return from_us(self.to_us() + other.to_us());
+    }
 };
 
 pub fn get_time_since_boot() Absolute {
@@ -39,5 +83,5 @@ pub fn sleep_ms(time_ms: u32) void {
 
 pub fn sleep_us(time_us: u64) void {
     const end_time = make_timeout_us(time_us);
-    while (!end_time.reached()) {}
+    while (!end_time.is_reached()) {}
 }

From 371d4efde433a9dc87b9f6bc9c31ad491474f658 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sun, 25 Jun 2023 20:15:00 +0200
Subject: [PATCH 172/286] =?UTF-8?q?Runs=20zig=20fmt,=20implements=20a=20go?=
 =?UTF-8?q?od=20bunch=20of=20I=C2=B2C=20functions=20(#65)?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-authored-by: Felix "xq" Queißner 
---
 deps/microzig                     |   2 +-
 examples/flash_program.zig        |   2 +-
 examples/random.zig               |   2 +-
 examples/usb_device.zig           |   4 +-
 examples/usb_hid.zig              |   4 +-
 examples/ws2812.zig               |   8 +-
 src/chips/RP2040.zig              |  80 +++---
 src/hal.zig                       |   1 +
 src/hal/adc.zig                   |  22 +-
 src/hal/clocks.zig                |   4 +-
 src/hal/dma.zig                   |  22 +-
 src/hal/flash.zig                 |   4 +-
 src/hal/gpio.zig                  |  22 +-
 src/hal/hw.zig                    |  12 +-
 src/hal/i2c.zig                   | 413 ++++++++++++++++++++++++++++++
 src/hal/multicore.zig             |  10 +-
 src/hal/pins.zig                  |  12 +-
 src/hal/pio.zig                   |  50 ++--
 src/hal/pio/assembler/encoder.zig |  12 +-
 src/hal/pwm.zig                   |  10 +-
 src/hal/rom.zig                   |   6 +-
 src/hal/spi.zig                   |   4 +-
 src/hal/time.zig                  |  12 +-
 src/hal/uart.zig                  |   6 +-
 src/hal/usb.zig                   |  44 ++--
 25 files changed, 591 insertions(+), 177 deletions(-)
 create mode 100644 src/hal/i2c.zig

diff --git a/deps/microzig b/deps/microzig
index 958894191..a49fad973 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5
+Subproject commit a49fad973077dffd5fa0b392720295ad033f076e
diff --git a/examples/flash_program.zig b/examples/flash_program.zig
index 4bae76959..d38d0aea6 100644
--- a/examples/flash_program.zig
+++ b/examples/flash_program.zig
@@ -14,7 +14,7 @@ const uart_tx_pin = gpio.num(0);
 const uart_rx_pin = gpio.num(1);
 
 const flash_target_offset: u32 = 256 * 1024;
-const flash_target_contents = @intToPtr([*]const u8, rp2040.flash.XIP_BASE + flash_target_offset);
+const flash_target_contents = @ptrFromInt([*]const u8, rp2040.flash.XIP_BASE + flash_target_offset);
 
 pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
     std.log.err("panic: {s}", .{message});
diff --git a/examples/random.zig b/examples/random.zig
index 151482e2c..40d2f6816 100644
--- a/examples/random.zig
+++ b/examples/random.zig
@@ -60,7 +60,7 @@ pub fn main() !void {
             var i: usize = 0;
             std.log.info("Distribution:", .{});
             while (i < 256) : (i += 1) {
-                std.log.info("{} -> {}, {d:2}%", .{ i, dist[i], @intToFloat(f32, dist[i]) / @intToFloat(f32, counter) });
+                std.log.info("{} -> {}, {d:2}%", .{ i, dist[i], @floatFromInt(f32, dist[i]) / @floatFromInt(f32, counter) });
             }
         }
         time.sleep_ms(1000);
diff --git a/examples/usb_device.zig b/examples/usb_device.zig
index 27d961d11..d2b243d6a 100644
--- a/examples/usb_device.zig
+++ b/examples/usb_device.zig
@@ -41,7 +41,7 @@ pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
         .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.Dir.Out.endpoint(1),
-        .attributes = @enumToInt(usb.TransferType.Bulk),
+        .attributes = @intFromEnum(usb.TransferType.Bulk),
         .max_packet_size = 64,
         .interval = 0,
     },
@@ -58,7 +58,7 @@ pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
         .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.Dir.In.endpoint(1),
-        .attributes = @enumToInt(usb.TransferType.Bulk),
+        .attributes = @intFromEnum(usb.TransferType.Bulk),
         .max_packet_size = 64,
         .interval = 0,
     },
diff --git a/examples/usb_hid.zig b/examples/usb_hid.zig
index 34b9a1205..2eced2b41 100644
--- a/examples/usb_hid.zig
+++ b/examples/usb_hid.zig
@@ -41,7 +41,7 @@ pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
         .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.Dir.Out.endpoint(1),
-        .attributes = @enumToInt(usb.TransferType.Interrupt),
+        .attributes = @intFromEnum(usb.TransferType.Interrupt),
         .max_packet_size = 64,
         .interval = 0,
     },
@@ -58,7 +58,7 @@ pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
         .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.Dir.In.endpoint(1),
-        .attributes = @enumToInt(usb.TransferType.Interrupt),
+        .attributes = @intFromEnum(usb.TransferType.Interrupt),
         .max_packet_size = 64,
         .interval = 0,
     },
diff --git a/examples/ws2812.zig b/examples/ws2812.zig
index e51d9730d..f61204b3b 100644
--- a/examples/ws2812.zig
+++ b/examples/ws2812.zig
@@ -38,19 +38,19 @@ const led_pin = gpio.num(23);
 
 pub fn main() void {
     pio.gpio_init(led_pin);
-    sm_set_consecutive_pindirs(pio, sm, @enumToInt(led_pin), 1, true);
+    sm_set_consecutive_pindirs(pio, sm, @intFromEnum(led_pin), 1, true);
 
     const cycles_per_bit: comptime_int = ws2812_program.defines[0].value + //T1
         ws2812_program.defines[1].value + //T2
         ws2812_program.defines[2].value; //T3
-    const div = @intToFloat(f32, rp2040.clock_config.sys.?.output_freq) /
+    const div = @floatFromInt(f32, rp2040.clock_config.sys.?.output_freq) /
         (800_000 * cycles_per_bit);
 
     pio.sm_load_and_start_program(sm, ws2812_program, .{
         .clkdiv = rp2040.pio.ClkDivOptions.from_float(div),
         .pin_mappings = .{
             .side_set = .{
-                .base = @enumToInt(led_pin),
+                .base = @intFromEnum(led_pin),
                 .count = 1,
             },
         },
@@ -85,7 +85,7 @@ fn sm_set_consecutive_pindirs(_pio: Pio, _sm: StateMachine, pin: u5, count: u3,
         .delay_side_set = 0,
         .payload = .{
             .set = .{
-                .data = @boolToInt(is_out),
+                .data = @intFromBool(is_out),
                 .destination = .pindirs,
             },
         },
diff --git a/src/chips/RP2040.zig b/src/chips/RP2040.zig
index 62af336a8..74f613486 100644
--- a/src/chips/RP2040.zig
+++ b/src/chips/RP2040.zig
@@ -65,9 +65,9 @@ pub const devices = struct {
 
         pub const peripherals = struct {
             ///  System Control Space
-            pub const MPU = @intToPtr(*volatile types.peripherals.SCS, 0xd90);
+            pub const MPU = @ptrFromInt(*volatile types.peripherals.SCS, 0xd90);
             ///  QSPI flash execute-in-place block
-            pub const XIP_CTRL = @intToPtr(*volatile types.peripherals.XIP_CTRL, 0x14000000);
+            pub const XIP_CTRL = @ptrFromInt(*volatile types.peripherals.XIP_CTRL, 0x14000000);
             ///  DW_apb_ssi has the following features:
             ///  * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.
             ///  * APB3 and APB4 protocol support.
@@ -94,27 +94,27 @@ pub const devices = struct {
             ///  - Interrupt polarity – active high interrupt lines.
             ///  - Serial clock polarity – low serial-clock polarity directly after reset.
             ///  - Serial clock phase – capture on first edge of serial-clock directly after reset.
-            pub const XIP_SSI = @intToPtr(*volatile types.peripherals.XIP_SSI, 0x18000000);
-            pub const SYSINFO = @intToPtr(*volatile types.peripherals.SYSINFO, 0x40000000);
+            pub const XIP_SSI = @ptrFromInt(*volatile types.peripherals.XIP_SSI, 0x18000000);
+            pub const SYSINFO = @ptrFromInt(*volatile types.peripherals.SYSINFO, 0x40000000);
             ///  Register block for various chip control signals
-            pub const SYSCFG = @intToPtr(*volatile types.peripherals.SYSCFG, 0x40004000);
-            pub const CLOCKS = @intToPtr(*volatile types.peripherals.CLOCKS, 0x40008000);
-            pub const RESETS = @intToPtr(*volatile types.peripherals.RESETS, 0x4000c000);
-            pub const PSM = @intToPtr(*volatile types.peripherals.PSM, 0x40010000);
-            pub const IO_BANK0 = @intToPtr(*volatile types.peripherals.IO_BANK0, 0x40014000);
-            pub const IO_QSPI = @intToPtr(*volatile types.peripherals.IO_QSPI, 0x40018000);
-            pub const PADS_BANK0 = @intToPtr(*volatile types.peripherals.PADS_BANK0, 0x4001c000);
-            pub const PADS_QSPI = @intToPtr(*volatile types.peripherals.PADS_QSPI, 0x40020000);
+            pub const SYSCFG = @ptrFromInt(*volatile types.peripherals.SYSCFG, 0x40004000);
+            pub const CLOCKS = @ptrFromInt(*volatile types.peripherals.CLOCKS, 0x40008000);
+            pub const RESETS = @ptrFromInt(*volatile types.peripherals.RESETS, 0x4000c000);
+            pub const PSM = @ptrFromInt(*volatile types.peripherals.PSM, 0x40010000);
+            pub const IO_BANK0 = @ptrFromInt(*volatile types.peripherals.IO_BANK0, 0x40014000);
+            pub const IO_QSPI = @ptrFromInt(*volatile types.peripherals.IO_QSPI, 0x40018000);
+            pub const PADS_BANK0 = @ptrFromInt(*volatile types.peripherals.PADS_BANK0, 0x4001c000);
+            pub const PADS_QSPI = @ptrFromInt(*volatile types.peripherals.PADS_QSPI, 0x40020000);
             ///  Controls the crystal oscillator
-            pub const XOSC = @intToPtr(*volatile types.peripherals.XOSC, 0x40024000);
-            pub const PLL_SYS = @intToPtr(*volatile types.peripherals.PLL_SYS, 0x40028000);
-            pub const PLL_USB = @intToPtr(*volatile types.peripherals.PLL_SYS, 0x4002c000);
+            pub const XOSC = @ptrFromInt(*volatile types.peripherals.XOSC, 0x40024000);
+            pub const PLL_SYS = @ptrFromInt(*volatile types.peripherals.PLL_SYS, 0x40028000);
+            pub const PLL_USB = @ptrFromInt(*volatile types.peripherals.PLL_SYS, 0x4002c000);
             ///  Register block for busfabric control signals and performance counters
-            pub const BUSCTRL = @intToPtr(*volatile types.peripherals.BUSCTRL, 0x40030000);
-            pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x40034000);
-            pub const UART1 = @intToPtr(*volatile types.peripherals.UART0, 0x40038000);
-            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x4003c000);
-            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40040000);
+            pub const BUSCTRL = @ptrFromInt(*volatile types.peripherals.BUSCTRL, 0x40030000);
+            pub const UART0 = @ptrFromInt(*volatile types.peripherals.UART0, 0x40034000);
+            pub const UART1 = @ptrFromInt(*volatile types.peripherals.UART0, 0x40038000);
+            pub const SPI0 = @ptrFromInt(*volatile types.peripherals.SPI0, 0x4003c000);
+            pub const SPI1 = @ptrFromInt(*volatile types.peripherals.SPI0, 0x40040000);
             ///  DW_apb_i2c address block
             ///  List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
             ///  IC_ULTRA_FAST_MODE ................ 0x0
@@ -185,7 +185,7 @@ pub const devices = struct {
             ///  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
             ///  IC_DEFAULT_UFM_SPKLEN ............. 0x1
             ///  IC_TX_BUFFER_DEPTH ................ 16
-            pub const I2C0 = @intToPtr(*volatile types.peripherals.I2C0, 0x40044000);
+            pub const I2C0 = @ptrFromInt(*volatile types.peripherals.I2C0, 0x40044000);
             ///  DW_apb_i2c address block
             ///  List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
             ///  IC_ULTRA_FAST_MODE ................ 0x0
@@ -256,11 +256,11 @@ pub const devices = struct {
             ///  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
             ///  IC_DEFAULT_UFM_SPKLEN ............. 0x1
             ///  IC_TX_BUFFER_DEPTH ................ 16
-            pub const I2C1 = @intToPtr(*volatile types.peripherals.I2C0, 0x40048000);
+            pub const I2C1 = @ptrFromInt(*volatile types.peripherals.I2C0, 0x40048000);
             ///  Control and data interface to SAR ADC
-            pub const ADC = @intToPtr(*volatile types.peripherals.ADC, 0x4004c000);
+            pub const ADC = @ptrFromInt(*volatile types.peripherals.ADC, 0x4004c000);
             ///  Simple PWM
-            pub const PWM = @intToPtr(*volatile types.peripherals.PWM, 0x40050000);
+            pub const PWM = @ptrFromInt(*volatile types.peripherals.PWM, 0x40050000);
             ///  Controls time and alarms
             ///  time is a 64 bit value indicating the time in usec since power-on
             ///  timeh is the top 32 bits of time & timel is the bottom 32 bits
@@ -271,35 +271,35 @@ pub const devices = struct {
             ///  An alarm can be cancelled before it has finished by clearing the alarm_enable
             ///  When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared
             ///  To clear the interrupt write a 1 to the corresponding alarm_irq
-            pub const TIMER = @intToPtr(*volatile types.peripherals.TIMER, 0x40054000);
-            pub const WATCHDOG = @intToPtr(*volatile types.peripherals.WATCHDOG, 0x40058000);
+            pub const TIMER = @ptrFromInt(*volatile types.peripherals.TIMER, 0x40054000);
+            pub const WATCHDOG = @ptrFromInt(*volatile types.peripherals.WATCHDOG, 0x40058000);
             ///  Register block to control RTC
-            pub const RTC = @intToPtr(*volatile types.peripherals.RTC, 0x4005c000);
-            pub const ROSC = @intToPtr(*volatile types.peripherals.ROSC, 0x40060000);
+            pub const RTC = @ptrFromInt(*volatile types.peripherals.RTC, 0x4005c000);
+            pub const ROSC = @ptrFromInt(*volatile types.peripherals.ROSC, 0x40060000);
             ///  control and status for on-chip voltage regulator and chip level reset subsystem
-            pub const VREG_AND_CHIP_RESET = @intToPtr(*volatile types.peripherals.VREG_AND_CHIP_RESET, 0x40064000);
+            pub const VREG_AND_CHIP_RESET = @ptrFromInt(*volatile types.peripherals.VREG_AND_CHIP_RESET, 0x40064000);
             ///  Testbench manager. Allows the programmer to know what platform their software is running on.
-            pub const TBMAN = @intToPtr(*volatile types.peripherals.TBMAN, 0x4006c000);
+            pub const TBMAN = @ptrFromInt(*volatile types.peripherals.TBMAN, 0x4006c000);
             ///  DMA with separate read and write masters
-            pub const DMA = @intToPtr(*volatile types.peripherals.DMA, 0x50000000);
+            pub const DMA = @ptrFromInt(*volatile types.peripherals.DMA, 0x50000000);
             ///  DPRAM layout for USB device.
-            pub const USBCTRL_DPRAM = @intToPtr(*volatile types.peripherals.USBCTRL_DPRAM, 0x50100000);
+            pub const USBCTRL_DPRAM = @ptrFromInt(*volatile types.peripherals.USBCTRL_DPRAM, 0x50100000);
             ///  USB FS/LS controller device registers
-            pub const USBCTRL_REGS = @intToPtr(*volatile types.peripherals.USBCTRL_REGS, 0x50110000);
+            pub const USBCTRL_REGS = @ptrFromInt(*volatile types.peripherals.USBCTRL_REGS, 0x50110000);
             ///  Programmable IO block
-            pub const PIO0 = @intToPtr(*volatile types.peripherals.PIO0, 0x50200000);
+            pub const PIO0 = @ptrFromInt(*volatile types.peripherals.PIO0, 0x50200000);
             ///  Programmable IO block
-            pub const PIO1 = @intToPtr(*volatile types.peripherals.PIO0, 0x50300000);
+            pub const PIO1 = @ptrFromInt(*volatile types.peripherals.PIO0, 0x50300000);
             ///  Single-cycle IO block
             ///  Provides core-local and inter-core hardware for the two processors, with single-cycle access.
-            pub const SIO = @intToPtr(*volatile types.peripherals.SIO, 0xd0000000);
-            pub const PPB = @intToPtr(*volatile types.peripherals.PPB, 0xe0000000);
+            pub const SIO = @ptrFromInt(*volatile types.peripherals.SIO, 0xd0000000);
+            pub const PPB = @ptrFromInt(*volatile types.peripherals.PPB, 0xe0000000);
             ///  System Tick Timer
-            pub const SysTick = @intToPtr(*volatile types.peripherals.SysTick, 0xe000e010);
+            pub const SysTick = @ptrFromInt(*volatile types.peripherals.SysTick, 0xe000e010);
             ///  System Control Space
-            pub const NVIC = @intToPtr(*volatile types.peripherals.NVIC, 0xe000e100);
+            pub const NVIC = @ptrFromInt(*volatile types.peripherals.NVIC, 0xe000e100);
             ///  System Control Space
-            pub const SCB = @intToPtr(*volatile types.peripherals.SCB, 0xe000ed00);
+            pub const SCB = @ptrFromInt(*volatile types.peripherals.SCB, 0xe000ed00);
         };
     };
 };
diff --git a/src/hal.zig b/src/hal.zig
index 89e2b58a9..78ebcf2c0 100644
--- a/src/hal.zig
+++ b/src/hal.zig
@@ -16,6 +16,7 @@ pub const rand = @import("hal/random.zig");
 pub const resets = @import("hal/resets.zig");
 pub const rom = @import("hal/rom.zig");
 pub const spi = @import("hal/spi.zig");
+pub const i2c = @import("hal/i2c.zig");
 pub const time = @import("hal/time.zig");
 pub const uart = @import("hal/uart.zig");
 pub const usb = @import("hal/usb.zig");
diff --git a/src/hal/adc.zig b/src/hal/adc.zig
index 592273bd4..973db6320 100644
--- a/src/hal/adc.zig
+++ b/src/hal/adc.zig
@@ -17,12 +17,12 @@ pub const Error = error{
 
 /// temp_sensor is not valid because you can refer to it by name.
 pub fn input(n: u2) Input {
-    return @intToEnum(Input, n);
+    return @enumFromInt(Input, n);
 }
 
 /// Enable the ADC controller.
 pub fn set_enabled(enabled: bool) void {
-    ADC.CS.modify(.{ .EN = @boolToInt(enabled) });
+    ADC.CS.modify(.{ .EN = @intFromBool(enabled) });
 }
 
 const Config = struct {
@@ -41,7 +41,7 @@ const Config = struct {
 pub fn apply(config: Config) void {
     ADC.CS.write(.{
         .EN = 0,
-        .TS_EN = @boolToInt(config.temp_sensor_enabled),
+        .TS_EN = @intFromBool(config.temp_sensor_enabled),
         .START_ONCE = 0,
         .START_MANY = 0,
         .READY = 0,
@@ -78,14 +78,14 @@ pub fn apply(config: Config) void {
 
 /// Select analog input for next conversion.
 pub fn select_input(in: Input) void {
-    ADC.CS.modify(.{ .AINSEL = @enumToInt(in) });
+    ADC.CS.modify(.{ .AINSEL = @intFromEnum(in) });
 }
 
 /// Get the currently selected analog input. 0..3 are GPIO 26..29 respectively,
 /// 4 is the temperature sensor.
 pub fn get_selected_input() Input {
     const cs = ADC.SC.read();
-    return @intToEnum(Input, cs.AINSEL);
+    return @enumFromInt(Input, cs.AINSEL);
 }
 
 pub const Input = enum(u3) {
@@ -98,7 +98,7 @@ pub const Input = enum(u3) {
     /// temp_sensor.
     pub fn get_gpio_pin(in: Input) gpio.Pin {
         return switch (in) {
-            else => gpio.num(@as(u5, @enumToInt(in)) + 26),
+            else => gpio.num(@as(u5, @intFromEnum(in)) + 26),
             .temp_sensor => @panic("temp_sensor doesn't have a pin"),
         };
     }
@@ -120,13 +120,13 @@ pub const Input = enum(u3) {
 
 /// Set to true to power on the temperature sensor.
 pub fn set_temp_sensor_enabled(enable: bool) void {
-    ADC.CS.modify(.{ .TS_EN = @boolToInt(enable) });
+    ADC.CS.modify(.{ .TS_EN = @intFromBool(enable) });
 }
 
 /// T must be floating point.
 pub fn temp_sensor_result_to_celcius(comptime T: type, comptime vref: T, result: u12) T {
     // TODO: consider fixed-point
-    const raw = @intToFloat(T, result);
+    const raw = @floatFromInt(T, result);
     const voltage: T = vref * raw / 0x0fff;
     return (27.0 - ((voltage - 0.706) / 0.001721));
 }
@@ -228,9 +228,9 @@ pub const fifo = struct {
     /// Apply ADC FIFO configuration and enable it
     pub fn apply(config: fifo.Config) void {
         ADC.FCS.write(.{
-            .DREQ_EN = @boolToInt(config.dreq_enabled),
+            .DREQ_EN = @intFromBool(config.dreq_enabled),
             .THRESH = config.thresh,
-            .SHIFT = @boolToInt(config.shift),
+            .SHIFT = @intFromBool(config.shift),
 
             .EN = 1,
             .EMPTY = 0,
@@ -260,7 +260,7 @@ pub const fifo = struct {
     pub fn irq_set_enabled(enable: bool) void {
         // TODO: check if this works
         ADC.INTE.write(.{
-            .FIFO = @boolToInt(enable),
+            .FIFO = @intFromBool(enable),
             .padding = 0,
         });
     }
diff --git a/src/hal/clocks.zig b/src/hal/clocks.zig
index b13ebd3d8..cb5350f9e 100644
--- a/src/hal/clocks.zig
+++ b/src/hal/clocks.zig
@@ -86,7 +86,7 @@ pub const Generator = enum(u32) {
     const generators = @ptrCast(*volatile [@typeInfo(Generator).Enum.fields.len]GeneratorRegs, CLOCKS);
 
     fn get_regs(generator: Generator) *volatile GeneratorRegs {
-        return &generators[@enumToInt(generator)];
+        return &generators[@intFromEnum(generator)];
     }
 
     pub fn has_glitchless_mux(generator: Generator) bool {
@@ -666,7 +666,7 @@ pub fn count_frequency_khz(source: Source, comptime clock_config: GlobalConfigur
     CLOCKS.FC0_INTERVAL.raw = 10;
     CLOCKS.FC0_MIN_KHZ.raw = 0;
     CLOCKS.FC0_MAX_KHZ.raw = std.math.maxInt(u32);
-    CLOCKS.FC0_SRC.raw = @enumToInt(source);
+    CLOCKS.FC0_SRC.raw = @intFromEnum(source);
 
     while (CLOCKS.FC0_STATUS.read().DONE != 1) {}
 
diff --git a/src/hal/dma.zig b/src/hal/dma.zig
index ded0a8c04..35b285a5c 100644
--- a/src/hal/dma.zig
+++ b/src/hal/dma.zig
@@ -19,7 +19,7 @@ pub const Dreq = enum(u6) {
 pub fn channel(n: u4) Channel {
     assert(n < num_channels);
 
-    return @intToEnum(Channel, n);
+    return @enumFromInt(Channel, n);
 }
 
 pub fn claim_unused_channel() ?Channel {
@@ -43,11 +43,11 @@ pub const Channel = enum(u4) {
     }
 
     pub fn unclaim(chan: Channel) void {
-        claimed_channels.set(@enumToInt(chan), false);
+        claimed_channels.set(@intFromEnum(chan), false);
     }
 
     pub fn is_claimed(chan: Channel) bool {
-        return claimed_channels.get(@enumToInt(chan));
+        return claimed_channels.get(@intFromEnum(chan));
     }
 
     const Regs = extern struct {
@@ -77,7 +77,7 @@ pub const Channel = enum(u4) {
 
     fn get_regs(chan: Channel) *volatile Regs {
         const regs = @ptrCast(*volatile [12]Regs, &DMA.CH0_READ_ADDR);
-        return ®s[@enumToInt(chan)];
+        return ®s[@intFromEnum(chan)];
     }
 
     pub const TransferConfig = struct {
@@ -105,14 +105,14 @@ pub const Channel = enum(u4) {
         regs.write_addr = write_addr;
         regs.trans_count = count;
         regs.ctrl_trig.modify(.{
-            .EN = @boolToInt(config.enable),
+            .EN = @intFromBool(config.enable),
             .DATA_SIZE = .{
                 .value = .SIZE_BYTE,
             },
-            .INCR_READ = @boolToInt(config.read_increment),
-            .INCR_WRITE = @boolToInt(config.write_increment),
+            .INCR_READ = @intFromBool(config.read_increment),
+            .INCR_WRITE = @intFromBool(config.write_increment),
             .TREQ_SEL = .{
-                .raw = @enumToInt(config.dreq),
+                .raw = @intFromEnum(config.dreq),
             },
         });
     }
@@ -120,16 +120,16 @@ pub const Channel = enum(u4) {
     pub fn set_irq0_enabled(chan: Channel, enabled: bool) void {
         if (enabled) {
             const inte0_set = hw.set_alias_raw(&DMA.INTE0);
-            inte0_set.* = @as(u32, 1) << @enumToInt(chan);
+            inte0_set.* = @as(u32, 1) << @intFromEnum(chan);
         } else {
             const inte0_clear = hw.clear_alias_raw(&DMA.INTE0);
-            inte0_clear.* = @as(u32, 1) << @enumToInt(chan);
+            inte0_clear.* = @as(u32, 1) << @intFromEnum(chan);
         }
     }
 
     pub fn acknowledge_irq0(chan: Channel) void {
         const ints0_set = hw.set_alias_raw(&DMA.INTS0);
-        ints0_set.* = @as(u32, 1) << @enumToInt(chan);
+        ints0_set.* = @as(u32, 1) << @intFromEnum(chan);
     }
 
     pub fn is_busy(chan: Channel) bool {
diff --git a/src/hal/flash.zig b/src/hal/flash.zig
index a7404b120..cb86c72d3 100644
--- a/src/hal/flash.zig
+++ b/src/hal/flash.zig
@@ -23,7 +23,7 @@ pub const boot2 = struct {
     /// Copy the 2nd stage bootloader into memory
     pub fn flash_init() linksection(".time_critical") void {
         if (copyout_valid) return;
-        const bootloader = @intToPtr([*]u32, XIP_BASE);
+        const bootloader = @ptrFromInt([*]u32, XIP_BASE);
         var i: usize = 0;
         while (i < BOOT2_SIZE_BYTES) : (i += 1) {
             copyout[i] = bootloader[i];
@@ -55,7 +55,7 @@ pub fn range_erase(offset: u32, count: u32) linksection(".time_critical") void {
 
     rom.connect_internal_flash()();
     rom.flash_exit_xip()();
-    rom.flash_range_erase()(offset, count, BLOCK_SIZE, @enumToInt(Command.block_erase));
+    rom.flash_range_erase()(offset, count, BLOCK_SIZE, @intFromEnum(Command.block_erase));
     rom.flash_flush_cache()();
 
     boot2.flash_enable_xip();
diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig
index 53d3b0bae..3b9e5aea2 100644
--- a/src/hal/gpio.zig
+++ b/src/hal/gpio.zig
@@ -72,18 +72,18 @@ pub fn num(n: u5) Pin {
     if (n > 29)
         @panic("the RP2040 only has GPIO 0-29");
 
-    return @intToEnum(Pin, n);
+    return @enumFromInt(Pin, n);
 }
 
 pub fn mask(m: u32) Mask {
-    return @intToEnum(Mask, m);
+    return @enumFromInt(Mask, m);
 }
 
 pub const Mask = enum(u30) {
     _,
 
     pub fn set_function(self: Mask, function: Function) void {
-        const raw_mask = @enumToInt(self);
+        const raw_mask = @intFromEnum(self);
         for (0..@bitSizeOf(Mask)) |i| {
             const bit = @intCast(u5, i);
             if (0 != raw_mask & (@as(u32, 1) << bit))
@@ -92,7 +92,7 @@ pub const Mask = enum(u30) {
     }
 
     pub fn set_direction(self: Mask, direction: Direction) void {
-        const raw_mask = @enumToInt(self);
+        const raw_mask = @intFromEnum(self);
         switch (direction) {
             .out => SIO.GPIO_OE_SET.raw = raw_mask,
             .in => SIO.GPIO_OE_CLR.raw = raw_mask,
@@ -100,7 +100,7 @@ pub const Mask = enum(u30) {
     }
 
     pub fn set_pull(self: Mask, pull: ?Pull) void {
-        const raw_mask = @enumToInt(self);
+        const raw_mask = @intFromEnum(self);
         for (0..@bitSizeOf(Mask)) |i| {
             const bit = @intCast(u5, i);
             if (0 != raw_mask & (@as(u32, 1) << bit))
@@ -109,11 +109,11 @@ pub const Mask = enum(u30) {
     }
 
     pub fn put(self: Mask, value: u32) void {
-        SIO.GPIO_OUT_XOR.raw = (SIO.GPIO_OUT.raw ^ value) & @enumToInt(self);
+        SIO.GPIO_OUT_XOR.raw = (SIO.GPIO_OUT.raw ^ value) & @intFromEnum(self);
     }
 
     pub fn read(self: Mask) u32 {
-        return SIO.GPIO_IN.raw & @enumToInt(self);
+        return SIO.GPIO_IN.raw & @intFromEnum(self);
     }
 };
 
@@ -155,16 +155,16 @@ pub const Pin = enum(u5) {
 
     fn get_regs(gpio: Pin) *volatile Regs {
         const regs = @ptrCast(*volatile [30]Regs, &IO_BANK0.GPIO0_STATUS);
-        return ®s[@enumToInt(gpio)];
+        return ®s[@intFromEnum(gpio)];
     }
 
     fn get_pads_reg(gpio: Pin) *volatile PadsReg {
         const regs = @ptrCast(*volatile [30]PadsReg, &PADS_BANK0.GPIO0);
-        return ®s[@enumToInt(gpio)];
+        return ®s[@intFromEnum(gpio)];
     }
 
     pub fn mask(gpio: Pin) u32 {
-        return @as(u32, 1) << @enumToInt(gpio);
+        return @as(u32, 1) << @intFromEnum(gpio);
     }
 
     pub inline fn set_pull(gpio: Pin, pull: ?Pull) void {
@@ -206,7 +206,7 @@ pub const Pin = enum(u5) {
 
     pub inline fn set_input_enabled(pin: Pin, enabled: bool) void {
         const pads_reg = pin.get_pads_reg();
-        pads_reg.modify(.{ .IE = @boolToInt(enabled) });
+        pads_reg.modify(.{ .IE = @intFromBool(enabled) });
     }
 
     pub inline fn set_function(gpio: Pin, function: Function) void {
diff --git a/src/hal/hw.zig b/src/hal/hw.zig
index 89aee4549..28a198105 100644
--- a/src/hal/hw.zig
+++ b/src/hal/hw.zig
@@ -20,27 +20,27 @@ const set_bits = @as(u32, 0x2) << 12;
 const clear_bits = @as(u32, 0x3) << 12;
 
 pub fn clear_alias_raw(ptr: anytype) *volatile u32 {
-    return @intToPtr(*volatile u32, @ptrToInt(ptr) | clear_bits);
+    return @ptrFromInt(*volatile u32, @intFromPtr(ptr) | clear_bits);
 }
 
 pub fn set_alias_raw(ptr: anytype) *volatile u32 {
-    return @intToPtr(*volatile u32, @ptrToInt(ptr) | set_bits);
+    return @ptrFromInt(*volatile u32, @intFromPtr(ptr) | set_bits);
 }
 
 pub fn xor_alias_raw(ptr: anytype) *volatile u32 {
-    return @intToPtr(*volatile u32, @ptrToInt(ptr) | xor_bits);
+    return @ptrFromInt(*volatile u32, @intFromPtr(ptr) | xor_bits);
 }
 
 pub fn clear_alias(ptr: anytype) @TypeOf(ptr) {
-    return @intToPtr(@TypeOf(ptr), @ptrToInt(ptr) | clear_bits);
+    return @ptrFromInt(@TypeOf(ptr), @intFromPtr(ptr) | clear_bits);
 }
 
 pub fn set_alias(ptr: anytype) @TypeOf(ptr) {
-    return @intToPtr(@TypeOf(ptr), @ptrToInt(ptr) | set_bits);
+    return @ptrFromInt(@TypeOf(ptr), @intFromPtr(ptr) | set_bits);
 }
 
 pub fn xor_alias(ptr: anytype) @TypeOf(ptr) {
-    return @intToPtr(@TypeOf(ptr), @ptrToInt(ptr) | xor_bits);
+    return @ptrFromInt(@TypeOf(ptr), @intFromPtr(ptr) | xor_bits);
 }
 
 pub inline fn tight_loop_contents() void {
diff --git a/src/hal/i2c.zig b/src/hal/i2c.zig
new file mode 100644
index 000000000..cc7467ee8
--- /dev/null
+++ b/src/hal/i2c.zig
@@ -0,0 +1,413 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+const I2C0 = peripherals.I2C0;
+const I2C1 = peripherals.I2C1;
+
+const gpio = @import("gpio.zig");
+const clocks = @import("clocks.zig");
+const resets = @import("resets.zig");
+const time = @import("time.zig");
+const hw = @import("hw.zig");
+
+const I2cRegs = microzig.chip.types.peripherals.I2C0;
+
+pub const Config = struct {
+    clock_config: clocks.GlobalConfiguration,
+    sda_pin: ?gpio.Pin = gpio.num(20), // both pins only have I²C as alternate function
+    scl_pin: ?gpio.Pin = gpio.num(21), // both pins only have I²C as alternate function
+    baud_rate: u32 = 100_000,
+};
+
+pub fn num(n: u1) I2C {
+    return @enumFromInt(I2C, n);
+}
+
+pub const Address = enum(u7) {
+    _,
+
+    pub fn new(addr: u7) Address {
+        var a = @enumFromInt(Address, addr);
+        std.debug.assert(!a.is_reserved());
+        return a;
+    }
+
+    pub fn is_reserved(addr: Address) bool {
+        return ((@intFromEnum(addr) & 0x78) == 0) or ((@intFromEnum(addr) & 0x78) == 0x78);
+    }
+
+    pub fn format(addr: Address, fmt: []const u8, options: std.fmt.FormatOptions, writer: anytype) !void {
+        _ = fmt;
+        _ = options;
+        try writer.print("I2C(0x{X:0>2}", .{@intFromEnum(addr)});
+    }
+};
+
+pub const I2C = enum(u1) {
+    _,
+
+    fn get_regs(i2c: I2C) *volatile I2cRegs {
+        return switch (@intFromEnum(i2c)) {
+            0 => I2C0,
+            1 => I2C1,
+        };
+    }
+
+    fn disable(i2c: I2C) void {
+        i2c.get_regs().IC_ENABLE.write(.{
+            .ENABLE = .{ .value = .DISABLED },
+            .ABORT = .{ .value = .DISABLE },
+            .TX_CMD_BLOCK = .{ .value = .NOT_BLOCKED },
+            .padding = 0,
+        });
+    }
+
+    fn enable(i2c: I2C) void {
+        i2c.get_regs().IC_ENABLE.write(.{
+            .ENABLE = .{ .value = .ENABLED },
+            .ABORT = .{ .value = .DISABLE },
+            .TX_CMD_BLOCK = .{ .value = .NOT_BLOCKED },
+            .padding = 0,
+        });
+    }
+
+    /// Initialise the I2C HW block.
+    pub fn apply(i2c: I2C, comptime config: Config) u32 {
+        const peri_freq = (comptime config.clock_config.get_frequency(.clk_sys)) orelse @compileError("clk_sys must be set for I²C");
+
+        const regs = i2c.get_regs();
+
+        i2c.disable();
+
+        regs.IC_ENABLE.write(.{
+            .ENABLE = .{ .value = .DISABLED },
+            .ABORT = .{ .value = .DISABLE },
+            .TX_CMD_BLOCK = .{ .value = .NOT_BLOCKED },
+            .padding = 0,
+        });
+
+        // Configure as a fast-mode master with RepStart support, 7-bit addresses
+        regs.IC_CON.write(.{
+            .MASTER_MODE = .{ .value = .ENABLED },
+            .SPEED = .{ .value = .FAST },
+            .IC_RESTART_EN = .{ .value = .ENABLED },
+            .IC_SLAVE_DISABLE = .{ .value = .SLAVE_DISABLED },
+            .TX_EMPTY_CTRL = .{ .value = .ENABLED },
+
+            .IC_10BITADDR_SLAVE = .{ .raw = 0 },
+            .IC_10BITADDR_MASTER = .{ .raw = 0 },
+            .STOP_DET_IFADDRESSED = .{ .raw = 0 },
+            .RX_FIFO_FULL_HLD_CTRL = .{ .raw = 0 },
+            .STOP_DET_IF_MASTER_ACTIVE = 0,
+            .padding = 0,
+        });
+
+        // Set FIFO watermarks to 1 to make things simpler. This is encoded by a register value of 0.
+        regs.IC_RX_TL.write(.{ .RX_TL = 0, .padding = 0 });
+        regs.IC_TX_TL.write(.{ .TX_TL = 0, .padding = 0 });
+
+        // Always enable the DREQ signalling -- harmless if DMA isn't listening
+        regs.IC_DMA_CR.write(.{
+            .RDMAE = .{ .value = .ENABLED },
+            .TDMAE = .{ .value = .ENABLED },
+            .padding = 0,
+        });
+
+        if (config.sda_pin) |pin| {
+            pin.set_function(.i2c);
+            pin.set_pull(.up);
+            // TODO: Set slew rate
+        }
+        if (config.scl_pin) |pin| {
+            pin.set_function(.i2c);
+            pin.set_pull(.up);
+            // TODO: Set slew rate
+        }
+
+        // Re-sets regs.enable upon returning:
+        return i2c.set_baudrate(config.baud_rate, peri_freq);
+    }
+
+    /// Set I2C baudrate.
+    pub fn set_baudrate(i2c: I2C, baud_rate: u32, freq_in: u32) u32 {
+        std.debug.assert(baud_rate != 0);
+        // I2C is synchronous design that runs from clk_sys
+
+        const regs = i2c.get_regs();
+
+        // TODO there are some subtleties to I2C timing which we are completely ignoring here
+        const period: u32 = (freq_in + baud_rate / 2) / baud_rate;
+        const lcnt: u32 = period * 3 / 5; // oof this one hurts
+        const hcnt: u32 = period - lcnt;
+
+        // Check for out-of-range divisors:
+        std.debug.assert(hcnt <= std.math.maxInt(u16));
+        std.debug.assert(lcnt <= std.math.maxInt(u16));
+        std.debug.assert(hcnt >= 8);
+        std.debug.assert(lcnt >= 8);
+
+        // Per I2C-bus specification a device in standard or fast mode must
+        // internally provide a hold time of at least 300ns for the SDA signal to
+        // bridge the undefined region of the falling edge of SCL. A smaller hold
+        // time of 120ns is used for fast mode plus.
+        const sda_tx_hold_count: u32 = if (baud_rate < 1_000_000)
+            // sda_tx_hold_count = freq_in [cycles/s] * 300ns * (1s / 1e9ns)
+            // Reduce 300/1e9 to 3/1e7 to avoid numbers that don't fit in uint.
+            // Add 1 to avoid division truncation.
+            ((freq_in * 3) / 10000000) + 1
+        else
+            // sda_tx_hold_count = freq_in [cycles/s] * 120ns * (1s / 1e9ns)
+            // Reduce 120/1e9 to 3/25e6 to avoid numbers that don't fit in uint.
+            // Add 1 to avoid division truncation.
+            ((freq_in * 3) / 25000000) + 1;
+
+        std.debug.assert(sda_tx_hold_count <= lcnt - 2);
+
+        i2c.disable();
+
+        // Always use "fast" mode (<= 400 kHz, works fine for standard mode too)
+        regs.IC_CON.modify(.{ .SPEED = .{ .value = .FAST } });
+        regs.IC_FS_SCL_HCNT.write(.{ .IC_FS_SCL_HCNT = @intCast(u16, hcnt), .padding = 0 });
+        regs.IC_FS_SCL_LCNT.write(.{ .IC_FS_SCL_LCNT = @intCast(u16, lcnt), .padding = 0 });
+        regs.IC_FS_SPKLEN.write(.{ .IC_FS_SPKLEN = if (lcnt < 16) 1 else @intCast(u8, lcnt / 16), .padding = 0 });
+        regs.IC_SDA_HOLD.modify(.{ .IC_SDA_TX_HOLD = @intCast(u16, sda_tx_hold_count) });
+
+        i2c.enable();
+
+        return freq_in / period;
+    }
+
+    // /// Set I2C port to slave mode.
+    // pub fn set_slave_mode(i2c: I2C, slave: bool, addr: u8) void {
+    //     //
+    // }
+
+    pub const WriteBlockingUntilError = error{ DeviceNotPresent, NoAcknowledge, Timeout };
+
+    /// Attempt to write specified number of bytes to address, blocking until the specified absolute time is reached.
+    pub fn write_blocking_until(i2c: I2C, addr: Address, src: []const u8, until: time.Absolute) WriteBlockingUntilError!usize {
+        const Timeout = struct {
+            limit: time.Absolute,
+            inline fn perform(tc: @This()) !void {
+                if (tc.limit.is_reached())
+                    return error.Timeout;
+            }
+        };
+        return i2c.write_blocking_internal(addr, src, Timeout{ .limit = until });
+    }
+
+    pub const ReadBlockingUntilError = error{ DeviceNotPresent, NoAcknowledge, Timeout };
+
+    /// Attempt to read specified number of bytes from address, blocking until the specified absolute time is reached.
+    pub fn read_blocking_until(i2c: I2C, addr: Address, dst: []u8, until: time.Absolute) ReadBlockingUntilError!usize {
+        const Timeout = struct {
+            limit: time.Absolute,
+            inline fn perform(tc: @This()) !void {
+                if (tc.limit.is_reached())
+                    return error.Timeout;
+            }
+        };
+        return i2c.read_blocking_internal(addr, dst, Timeout{ .limit = until });
+    }
+
+    pub const WriteTimeoutUsError = error{ DeviceNotPresent, NoAcknowledge, Timeout };
+
+    /// Attempt to write specified number of bytes to address, with timeout.
+    pub fn write_timeout_us(i2c: I2C, addr: Address, src: []const u8, timeout: time.Duration) WriteTimeoutUsError!usize {
+        return i2c.write_blocking_until(addr, src, time.get_time_since_boot().add_duration(timeout));
+    }
+
+    pub const ReadTimeoutUsError = error{ DeviceNotPresent, NoAcknowledge, Timeout };
+
+    /// Attempt to read specified number of bytes from address, with timeout.
+    pub fn read_timeout_us(i2c: I2C, addr: Address, dst: []u8, timeout: time.Duration) ReadTimeoutUsError!usize {
+        return i2c.read_blocking_until(addr, dst, time.get_time_since_boot().add_duration(timeout));
+    }
+
+    /// Attempt to write specified number of bytes to address, blocking.
+    pub const WriteBlockingError = error{ DeviceNotPresent, NoAcknowledge, Unexpected };
+    pub fn write_blocking(i2c: I2C, addr: Address, src: []const u8) WriteBlockingError!usize {
+        const Timeout = struct {
+            inline fn perform(tc: @This()) !void {
+                _ = tc;
+            }
+        };
+        return try i2c.write_blocking_internal(addr, src, Timeout{});
+    }
+
+    /// Attempt to read specified number of bytes from address, blocking.
+    pub const ReadBlockingError = error{ DeviceNotPresent, NoAcknowledge, Unexpected };
+    pub fn read_blocking(i2c: I2C, addr: Address, dst: []u8) ReadBlockingError!usize {
+        const Timeout = struct {
+            inline fn perform(tc: @This()) !void {
+                _ = tc;
+            }
+        };
+        try i2c.read_blocking_internal(addr, dst, Timeout{});
+    }
+
+    /// Determine non-blocking write space available.
+    pub inline fn get_write_available(i2c: I2C) u5 {
+        return i2c.get_regs().IC_TXFLR.read().TXFLR;
+    }
+
+    /// Determine number of bytes received.
+    pub inline fn get_read_available(i2c: I2C) u5 {
+        return i2c.get_regs().IC_RXFLR.read().RXFLR;
+    }
+
+    // /// Write direct to TX FIFO.
+    // pub fn write_raw_blocking(i2c: I2C, src: []const u8) void {
+    //     //
+    // }
+
+    // /// Read direct from RX FIFO.
+    // pub fn read_raw_blocking(i2c: I2C, dst: []u8) void {
+    //     //
+    // }
+
+    // /// Pop a byte from I2C Rx FIFO.
+    // pub fn read_byte_raw(i2c: I2C) u8 {
+    //     //
+    // }
+
+    // /// Push a byte into I2C Tx FIFO.
+    // pub fn write_byte_raw(i2c: I2C, value: u8) void {
+    //     //
+    // }
+
+    // /// Return the DREQ to use for pacing transfers to/from a particular I2C instance.
+    // pub fn get_dreq(i2c: I2C, is_tx: bool) u32 {
+    //     //
+    // }
+
+    fn set_address(i2c: I2C, addr: Address) void {
+        i2c.disable();
+        i2c.get_regs().IC_TAR.write(.{
+            .IC_TAR = @intFromEnum(addr),
+            .GC_OR_START = .{ .value = .GENERAL_CALL },
+            .SPECIAL = .{ .value = .DISABLED },
+            .padding = 0,
+        });
+        i2c.enable();
+    }
+
+    fn write_blocking_internal(i2c: I2C, addr: Address, src: []const u8, timeout_check: anytype) !usize {
+        std.debug.assert(!addr.is_reserved());
+        // Synopsys hw accepts start/stop flags alongside data items in the same
+        // FIFO word, so no 0 byte transfers.
+        std.debug.assert(src.len > 0);
+
+        const regs = i2c.get_regs();
+
+        i2c.set_address(addr);
+
+        {
+            // If the transaction was aborted or if it completed
+            // successfully wait until the STOP condition has occured.
+            defer blk: {
+
+                // TODO Could there be an abort while waiting for the STOP
+                // condition here? If so, additional code would be needed here
+                // to take care of the abort.
+                while (regs.IC_RAW_INTR_STAT.read().STOP_DET.value == .INACTIVE) {
+                    timeout_check.perform() catch break :blk;
+                    hw.tight_loop_contents();
+                }
+
+                // If there was a timeout, don't attempt to do anything else.
+                _ = regs.IC_CLR_STOP_DET.read();
+            }
+
+            for (src, 0..) |byte, i| {
+                const first = (i == 0);
+                const last = (i == (src.len - 1));
+
+                regs.IC_DATA_CMD.write(.{
+                    .RESTART = .{ .raw = @intFromBool(first) }, // TODO: Implement non-restarting variant
+                    .STOP = .{ .raw = @intFromBool(last) }, // TODO: Implement non-restarting variant
+                    .CMD = .{ .value = .WRITE },
+                    .DAT = byte,
+
+                    .FIRST_DATA_BYTE = .{ .value = .INACTIVE },
+                    .padding = 0,
+                });
+
+                // Wait until the transmission of the address/data from the internal
+                // shift register has completed. For this to function correctly, the
+                // TX_EMPTY_CTRL flag in IC_CON must be set. The TX_EMPTY_CTRL flag
+                // was set in i2c_init.
+                while (regs.IC_RAW_INTR_STAT.read().TX_EMPTY.value == .INACTIVE) {
+                    try timeout_check.perform();
+                    hw.tight_loop_contents();
+                }
+
+                const abort_reason = regs.IC_TX_ABRT_SOURCE.read();
+                if (@bitCast(u32, abort_reason) != 0) {
+                    // Note clearing the abort flag also clears the reason, and
+                    // this instance of flag is clear-on-read! Note also the
+                    // IC_CLR_TX_ABRT register always reads as 0.
+                    _ = regs.IC_CLR_TX_ABRT.read();
+
+                    if (abort_reason.ABRT_7B_ADDR_NOACK.value == .ACTIVE) {
+                        // No reported errors - seems to happen if there is nothing connected to the bus.
+                        // Address byte not acknowledged
+                        return error.DeviceNotPresent;
+                    }
+                    if (abort_reason.ABRT_TXDATA_NOACK.value == .ABRT_TXDATA_NOACK_GENERATED) {
+                        // TODO: How to handle this, also possible to do "return i;" here to signal not everything was transferred
+                        return error.NoAcknowledge;
+                    }
+
+                    std.log.debug("unexpected i2c abort while writing to {}: {}", .{ addr, abort_reason });
+                    return error.Unexpected;
+                }
+            }
+        }
+
+        return src.len;
+    }
+
+    fn read_blocking_internal(i2c: I2C, addr: Address, dst: []u8, timeout_check: anytype) !usize {
+        std.debug.assert(!addr.is_reserved());
+
+        const regs = i2c.get_regs();
+
+        i2c.set_address(addr);
+
+        for (dst, 0..) |*byte, i| {
+            const first = (i == 0);
+            const last = (i == dst.len - 1);
+            while (i2c.get_write_available(i2c) == 0) {
+                hw.tight_loop_contents();
+            }
+
+            regs.IC_DATA_CMD.write(.{
+                .RESTART = .{ .raw = @intFromBool(first) }, // TODO: Implement non-restarting variant
+                .STOP = .{ .raw = @intFromBool(last) }, // TODO: Implement non-restarting variant
+                .CMD = .{ .value = .READ },
+
+                .DAT = 0,
+                .FIRST_DATA_BYTE = .{ .value = 0 },
+                .padding = 0,
+            });
+
+            while (i2c.get_read_available() == 0) {
+                const abort_reason = regs.IC_TX_ABRT_SOURCE.read();
+                const abort = (regs.IC_CLR_TX_ABRT.read().CLR_TX_ABRT != 0);
+                if (abort) {
+                    if (abort_reason.ABRT_7B_ADDR_NOACK.value == .ACTIVE)
+                        return error.DeviceNotPresent;
+                    std.log.debug("unexpected i2c abort while reading from {}: {}", .{ addr, abort_reason });
+                    return error.Unexpected;
+                }
+
+                try timeout_check.perform();
+            }
+
+            byte.* = regs.IC_DATA_CMD.read().DAT;
+        }
+
+        return dst.len;
+    }
+};
diff --git a/src/hal/multicore.zig b/src/hal/multicore.zig
index e3199d9af..bc2b4de78 100644
--- a/src/hal/multicore.zig
+++ b/src/hal/multicore.zig
@@ -70,7 +70,7 @@ pub fn launch_core1_with_stack(entrypoint: *const fn () void, stack: []u32) void
         fn wrapper(_: u32, _: u32, _: u32, _: u32, entry: u32, stack_base: [*]u32) callconv(.C) void {
             // TODO: protect stack using MPU
             _ = stack_base;
-            @intToPtr(*const fn () void, entry)();
+            @ptrFromInt(*const fn () void, entry)();
         }
     }.wrapper;
 
@@ -79,12 +79,12 @@ pub fn launch_core1_with_stack(entrypoint: *const fn () void, stack: []u32) void
     while (PSM.FRCE_OFF.read().proc1 != 1) microzig.cpu.nop();
     PSM.FRCE_OFF.modify(.{ .proc1 = 0 });
 
-    stack[stack.len - 2] = @ptrToInt(entrypoint);
-    stack[stack.len - 1] = @ptrToInt(stack.ptr);
+    stack[stack.len - 2] = @intFromPtr(entrypoint);
+    stack[stack.len - 1] = @intFromPtr(stack.ptr);
 
     // calculate top of the stack
     const stack_ptr: u32 =
-        @ptrToInt(stack.ptr) +
+        @intFromPtr(stack.ptr) +
         (stack.len - 2) * @sizeOf(u32); // pop the two elements we "pushed" above
 
     // after reseting core1 is waiting for this specific sequence
@@ -94,7 +94,7 @@ pub fn launch_core1_with_stack(entrypoint: *const fn () void, stack: []u32) void
         1,
         SCB.VTOR.raw,
         stack_ptr,
-        @ptrToInt(wrapper),
+        @intFromPtr(wrapper),
     };
 
     var seq: usize = 0;
diff --git a/src/hal/pins.zig b/src/hal/pins.zig
index f23209255..5de0810c3 100644
--- a/src/hal/pins.zig
+++ b/src/hal/pins.zig
@@ -355,7 +355,7 @@ pub fn Pins(comptime config: GlobalConfiguration) type {
 
                 if (pin_config.function == .SIO) {
                     pin_field.name = pin_config.name orelse field.name;
-                    pin_field.type = GPIO(@enumToInt(@field(Pin, field.name)), pin_config.direction orelse .in);
+                    pin_field.type = GPIO(@intFromEnum(@field(Pin, field.name)), pin_config.direction orelse .in);
                 } else if (pin_config.function.is_pwm()) {
                     pin_field.name = pin_config.name orelse @tagName(pin_config.function);
                     pin_field.type = pwm.Pwm(pin_config.function.pwm_slice(), pin_config.function.pwm_channel());
@@ -450,8 +450,8 @@ pub const GlobalConfiguration = struct {
         comptime {
             inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field|
                 if (@field(config, field.name)) |pin_config| {
-                    const gpio_num = @enumToInt(@field(Pin, field.name));
-                    if (0 == function_table[@enumToInt(pin_config.function)][gpio_num])
+                    const gpio_num = @intFromEnum(@field(Pin, field.name));
+                    if (0 == function_table[@intFromEnum(pin_config.function)][gpio_num])
                         @compileError(comptimePrint("{s} cannot be configured for {}", .{ field.name, pin_config.function }));
 
                     if (pin_config.function == .SIO) {
@@ -481,7 +481,7 @@ pub const GlobalConfiguration = struct {
 
         inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field| {
             if (@field(config, field.name)) |pin_config| {
-                const pin = gpio.num(@enumToInt(@field(Pin, field.name)));
+                const pin = gpio.num(@intFromEnum(@field(Pin, field.name)));
                 const func = pin_config.function;
 
                 // xip = 0,
@@ -505,7 +505,7 @@ pub const GlobalConfiguration = struct {
                 } else {
                     @compileError(std.fmt.comptimePrint("Unimplemented pin function. Please implement setting pin function {s} for GPIO {}", .{
                         @tagName(func),
-                        @enumToInt(pin),
+                        @intFromEnum(pin),
                     }));
                 }
             }
@@ -517,7 +517,7 @@ pub const GlobalConfiguration = struct {
         if (input_gpios != 0) {
             inline for (@typeInfo(GlobalConfiguration).Struct.fields) |field|
                 if (@field(config, field.name)) |pin_config| {
-                    const gpio_num = @enumToInt(@field(Pin, field.name));
+                    const gpio_num = @intFromEnum(@field(Pin, field.name));
                     const pull = pin_config.pull orelse continue;
                     if (comptime pin_config.get_direction() != .in)
                         @compileError("Only input pins can have pull up/down enabled");
diff --git a/src/hal/pio.zig b/src/hal/pio.zig
index 2943a3f26..6b7ca1fb6 100644
--- a/src/hal/pio.zig
+++ b/src/hal/pio.zig
@@ -74,7 +74,7 @@ pub const ClkDivOptions = struct {
     frac: u8 = 0,
 
     pub fn from_float(div: f32) ClkDivOptions {
-        const fixed = @floatToInt(u24, div * 256);
+        const fixed = @intFromFloat(u24, div * 256);
         return ClkDivOptions{
             .int = @truncate(u16, fixed >> 8),
             .frac = @truncate(u8, fixed),
@@ -169,7 +169,7 @@ pub const Pio = enum(u1) {
             if (origin != offset)
                 return false;
 
-        const used_mask = used_instruction_space[@enumToInt(self)];
+        const used_mask = used_instruction_space[@intFromEnum(self)];
         const program_mask = program.get_mask();
 
         // We can add the program if the masks don't overlap, if there is
@@ -199,7 +199,7 @@ pub const Pio = enum(u1) {
             instruction_memory[i] = insn;
 
         const program_mask = program.get_mask();
-        used_instruction_space[@enumToInt(self)] |= program_mask << offset;
+        used_instruction_space[@intFromEnum(self)] |= program_mask << offset;
     }
 
     /// Public functions will need to lock independently, so only exposing this function for now
@@ -216,12 +216,12 @@ pub const Pio = enum(u1) {
         // TODO: const lock = hw.Lock.claim()
         // defer lock.unlock();
 
-        const claimed_mask = claimed_state_machines[@enumToInt(self)];
+        const claimed_mask = claimed_state_machines[@intFromEnum(self)];
         return for (0..4) |i| {
             const sm_mask = (@as(u4, 1) << @intCast(u2, i));
             if (0 == (claimed_mask & sm_mask)) {
-                claimed_state_machines[@enumToInt(self)] |= sm_mask;
-                break @intToEnum(StateMachine, i);
+                claimed_state_machines[@intFromEnum(self)] |= sm_mask;
+                break @enumFromInt(StateMachine, i);
             }
         } else error.NoSpace;
     }
@@ -229,13 +229,13 @@ pub const Pio = enum(u1) {
     pub fn get_sm_regs(self: Pio, sm: StateMachine) *volatile StateMachine.Regs {
         const pio_regs = self.get_regs();
         const sm_regs = @ptrCast(*volatile [4]StateMachine.Regs, &pio_regs.SM0_CLKDIV);
-        return &sm_regs[@enumToInt(sm)];
+        return &sm_regs[@intFromEnum(sm)];
     }
 
     fn get_irq_regs(self: Pio, irq: Irq) *volatile Irq.Regs {
         const pio_regs = self.get_regs();
         const irq_regs = @ptrCast(*volatile [2]Irq.Regs, &pio_regs.IRQ0_INTE);
-        return &irq_regs[@enumToInt(irq)];
+        return &irq_regs[@intFromEnum(irq)];
     }
 
     pub fn sm_set_clkdiv(self: Pio, sm: StateMachine, options: ClkDivOptions) void {
@@ -256,8 +256,8 @@ pub const Pio = enum(u1) {
         sm_regs.execctrl.modify(.{
             .WRAP_BOTTOM = options.wrap_target,
             .WRAP_TOP = options.wrap,
-            .SIDE_PINDIR = @boolToInt(options.side_pindir),
-            .SIDE_EN = @boolToInt(options.side_set_optional),
+            .SIDE_PINDIR = @intFromBool(options.side_pindir),
+            .SIDE_EN = @intFromBool(options.side_set_optional),
 
             // TODO: plug in rest of the options
             // STATUS_N
@@ -273,17 +273,17 @@ pub const Pio = enum(u1) {
     pub fn sm_set_shift_options(self: Pio, sm: StateMachine, options: ShiftOptions) void {
         const sm_regs = self.get_sm_regs(sm);
         sm_regs.shiftctrl.write(.{
-            .AUTOPUSH = @boolToInt(options.autopush),
-            .AUTOPULL = @boolToInt(options.autopull),
+            .AUTOPUSH = @intFromBool(options.autopush),
+            .AUTOPULL = @intFromBool(options.autopull),
 
-            .IN_SHIFTDIR = @enumToInt(options.in_shiftdir),
-            .OUT_SHIFTDIR = @enumToInt(options.out_shiftdir),
+            .IN_SHIFTDIR = @intFromEnum(options.in_shiftdir),
+            .OUT_SHIFTDIR = @intFromEnum(options.out_shiftdir),
 
             .PUSH_THRESH = options.push_threshold,
             .PULL_THRESH = options.pull_threshold,
 
-            .FJOIN_TX = @boolToInt(options.join_tx),
-            .FJOIN_RX = @boolToInt(options.join_rx),
+            .FJOIN_TX = @intFromBool(options.join_tx),
+            .FJOIN_RX = @intFromBool(options.join_rx),
 
             .reserved16 = 0,
         });
@@ -308,13 +308,13 @@ pub const Pio = enum(u1) {
     pub fn sm_is_tx_fifo_full(self: Pio, sm: StateMachine) bool {
         const regs = self.get_regs();
         const txfull = regs.FSTAT.read().TXFULL;
-        return (txfull & (@as(u4, 1) << @enumToInt(sm))) != 0;
+        return (txfull & (@as(u4, 1) << @intFromEnum(sm))) != 0;
     }
 
     pub fn sm_get_tx_fifo(self: Pio, sm: StateMachine) *volatile u32 {
         const regs = self.get_regs();
         const fifos = @ptrCast(*volatile [4]u32, ®s.TXF0);
-        return &fifos[@enumToInt(sm)];
+        return &fifos[@intFromEnum(sm)];
     }
 
     /// this function writes to the TX FIFO without checking that it's
@@ -335,16 +335,16 @@ pub const Pio = enum(u1) {
 
         var value = regs.CTRL.read();
         if (enabled)
-            value.SM_ENABLE |= @as(u4, 1) << @enumToInt(sm)
+            value.SM_ENABLE |= @as(u4, 1) << @intFromEnum(sm)
         else
-            value.SM_ENABLE &= ~(@as(u4, 1) << @enumToInt(sm));
+            value.SM_ENABLE &= ~(@as(u4, 1) << @intFromEnum(sm));
 
         regs.CTRL.write(value);
     }
 
     fn sm_clear_debug(self: Pio, sm: StateMachine) void {
         const regs = self.get_regs();
-        const mask: u4 = (@as(u4, 1) << @enumToInt(sm));
+        const mask: u4 = (@as(u4, 1) << @intFromEnum(sm));
 
         // write 1 to clear this register
         regs.FDEBUG.modify(.{
@@ -377,7 +377,7 @@ pub const Pio = enum(u1) {
     }
 
     pub fn sm_fifo_level(self: Pio, sm: StateMachine, fifo: Fifo) u4 {
-        const num = @enumToInt(sm);
+        const num = @intFromEnum(sm);
         const offset: u5 = switch (fifo) {
             .tx => 0,
             .rx => 4,
@@ -393,7 +393,7 @@ pub const Pio = enum(u1) {
         sm: StateMachine,
         source: Irq.Source,
     ) u5 {
-        return (@as(u5, 4) * @enumToInt(source)) + @enumToInt(sm);
+        return (@as(u5, 4) * @intFromEnum(source)) + @intFromEnum(sm);
     }
 
     pub fn sm_clear_interrupt(
@@ -420,7 +420,7 @@ pub const Pio = enum(u1) {
     }
 
     pub fn sm_restart(self: Pio, sm: StateMachine) void {
-        const mask: u4 = (@as(u4, 1) << @enumToInt(sm));
+        const mask: u4 = (@as(u4, 1) << @intFromEnum(sm));
         const regs = self.get_regs();
         regs.CTRL.modify(.{
             .SM_RESTART = mask,
@@ -428,7 +428,7 @@ pub const Pio = enum(u1) {
     }
 
     pub fn sm_clkdiv_restart(self: Pio, sm: StateMachine) void {
-        const mask: u4 = (@as(u4, 1) << @enumToInt(sm));
+        const mask: u4 = (@as(u4, 1) << @intFromEnum(sm));
         const regs = self.get_regs();
         regs.CTRL.modify(.{
             .CLKDIV_RESTART = mask,
diff --git a/src/hal/pio/assembler/encoder.zig b/src/hal/pio/assembler/encoder.zig
index e0bc74c9a..502b37470 100644
--- a/src/hal/pio/assembler/encoder.zig
+++ b/src/hal/pio/assembler/encoder.zig
@@ -340,14 +340,14 @@ pub fn Encoder(comptime options: Options) type {
                 },
                 .push => |push| .{
                     .push = .{
-                        .if_full = @boolToInt(push.iffull),
-                        .block = @boolToInt(push.block),
+                        .if_full = @intFromBool(push.iffull),
+                        .block = @intFromBool(push.block),
                     },
                 },
                 .pull => |pull| .{
                     .pull = .{
-                        .if_empty = @boolToInt(pull.ifempty),
-                        .block = @boolToInt(pull.block),
+                        .if_empty = @intFromBool(pull.ifempty),
+                        .block = @intFromBool(pull.block),
                     },
                 },
                 .mov => |mov| .{
@@ -361,8 +361,8 @@ pub fn Encoder(comptime options: Options) type {
                     const irq_num = try self.evaluate(u5, program.*, irq.num, token_index, diags);
                     break :blk .{
                         .irq = .{
-                            .clear = @boolToInt(irq.clear),
-                            .wait = @boolToInt(irq.wait),
+                            .clear = @intFromBool(irq.clear),
+                            .wait = @intFromBool(irq.wait),
                             .index = if (irq.rel)
                                 @as(u5, 0x10) | irq_num
                             else
diff --git a/src/hal/pwm.zig b/src/hal/pwm.zig
index 7277b11e0..6e5fe1d3f 100644
--- a/src/hal/pwm.zig
+++ b/src/hal/pwm.zig
@@ -10,7 +10,7 @@ fn get_regs(comptime slice: u32) *volatile Regs {
     @import("std").debug.assert(slice < 8);
     const PwmType = microzig.chip.types.peripherals.PWM;
     const reg_diff = comptime @offsetOf(PwmType, "CH1_CSR") - @offsetOf(PwmType, "CH0_CSR");
-    return @intToPtr(*volatile Regs, @ptrToInt(PWM) + reg_diff * slice);
+    return @ptrFromInt(*volatile Regs, @intFromPtr(PWM) + reg_diff * slice);
 }
 
 pub fn Pwm(comptime slice_num: u32, comptime chan: Channel) type {
@@ -74,7 +74,7 @@ const Regs = extern struct {
 pub inline fn set_slice_phase_correct(comptime slice: u32, phase_correct: bool) void {
     log.debug("PWM{} set phase correct: {}", .{ slice, phase_correct });
     get_regs(slice).csr.modify(.{
-        .PH_CORRECT = @boolToInt(phase_correct),
+        .PH_CORRECT = @intFromBool(phase_correct),
     });
 }
 
@@ -89,7 +89,7 @@ pub inline fn set_slice_clk_div(comptime slice: u32, integer: u8, fraction: u4)
 pub inline fn set_slice_clk_div_mode(comptime slice: u32, mode: ClkDivMode) void {
     log.debug("PWM{} set clk div mode: {}", .{ slice, mode });
     get_regs(slice).csr.modify(.{
-        .DIVMODE = @enumToInt(mode),
+        .DIVMODE = @intFromEnum(mode),
     });
 }
 
@@ -100,10 +100,10 @@ pub inline fn set_channel_inversion(
 ) void {
     switch (channel) {
         .a => get_regs(slice).csr.modify(.{
-            .A_INV = @boolToInt(invert),
+            .A_INV = @intFromBool(invert),
         }),
         .b => get_regs(slice).csr.modifi(.{
-            .B_INV = @boolToInt(invert),
+            .B_INV = @intFromBool(invert),
         }),
     }
 }
diff --git a/src/hal/rom.zig b/src/hal/rom.zig
index b76eb80a6..7b2538750 100644
--- a/src/hal/rom.zig
+++ b/src/hal/rom.zig
@@ -100,8 +100,8 @@ pub fn rom_table_code(c1: u8, c2: u8) u32 {
 ///
 /// The converted pointer
 pub inline fn rom_hword_as_ptr(rom_addr: u32) *anyopaque {
-    const ptr_to_ptr = @intToPtr(*u16, rom_addr);
-    return @intToPtr(*anyopaque, @intCast(usize, ptr_to_ptr.*));
+    const ptr_to_ptr = @ptrFromInt(*u16, rom_addr);
+    return @ptrFromInt(*anyopaque, @intCast(usize, ptr_to_ptr.*));
 }
 
 /// Lookup a bootrom function by code (inline)
@@ -115,7 +115,7 @@ pub inline fn rom_hword_as_ptr(rom_addr: u32) *anyopaque {
 pub inline fn _rom_func_lookup(code: Code) *anyopaque {
     const rom_table_lookup = @ptrCast(*signatures.rom_table_lookup, rom_hword_as_ptr(0x18));
     const func_table = @ptrCast(*u16, @alignCast(2, rom_hword_as_ptr(0x14)));
-    return rom_table_lookup(func_table, @enumToInt(code));
+    return rom_table_lookup(func_table, @intFromEnum(code));
 }
 
 /// Lookup a bootrom function by code
diff --git a/src/hal/spi.zig b/src/hal/spi.zig
index ee02131d7..251b61bc7 100644
--- a/src/hal/spi.zig
+++ b/src/hal/spi.zig
@@ -22,14 +22,14 @@ pub const Config = struct {
 };
 
 pub fn num(n: u1) SPI {
-    return @intToEnum(SPI, n);
+    return @enumFromInt(SPI, n);
 }
 
 pub const SPI = enum(u1) {
     _,
 
     fn get_regs(spi: SPI) *volatile SpiRegs {
-        return switch (@enumToInt(spi)) {
+        return switch (@intFromEnum(spi)) {
             0 => SPI0,
             1 => SPI1,
         };
diff --git a/src/hal/time.zig b/src/hal/time.zig
index e6cace556..95691cc10 100644
--- a/src/hal/time.zig
+++ b/src/hal/time.zig
@@ -7,11 +7,11 @@ pub const Absolute = enum(u64) {
     _,
 
     pub fn from_us(us: u64) Absolute {
-        return @intToEnum(Absolute, us);
+        return @enumFromInt(Absolute, us);
     }
 
     pub fn to_us(time: Absolute) u64 {
-        return @enumToInt(time);
+        return @intFromEnum(time);
     }
 
     pub fn is_reached_by(deadline: Absolute, point: Absolute) bool {
@@ -36,7 +36,7 @@ pub const Duration = enum(u64) {
     _,
 
     pub fn from_us(us: u64) Duration {
-        return @intToEnum(Duration, us);
+        return @enumFromInt(Duration, us);
     }
 
     pub fn from_ms(ms: u64) Duration {
@@ -44,7 +44,7 @@ pub const Duration = enum(u64) {
     }
 
     pub fn to_us(duration: Duration) u64 {
-        return @enumToInt(duration);
+        return @intFromEnum(duration);
     }
 
     pub fn less_than(self: Duration, other: Duration) bool {
@@ -67,14 +67,14 @@ pub fn get_time_since_boot() Absolute {
         var low_word = TIMER.TIMERAWL;
         const next_high_word = TIMER.TIMERAWH;
         if (next_high_word == high_word)
-            break @intToEnum(Absolute, @intCast(u64, high_word) << 32 | low_word);
+            break @enumFromInt(Absolute, @intCast(u64, high_word) << 32 | low_word);
 
         high_word = next_high_word;
     } else unreachable;
 }
 
 pub fn make_timeout_us(timeout_us: u64) Absolute {
-    return @intToEnum(Absolute, get_time_since_boot().to_us() + timeout_us);
+    return @enumFromInt(Absolute, get_time_since_boot().to_us() + timeout_us);
 }
 
 pub fn sleep_ms(time_ms: u32) void {
diff --git a/src/hal/uart.zig b/src/hal/uart.zig
index b7a9b114f..678d9799d 100644
--- a/src/hal/uart.zig
+++ b/src/hal/uart.zig
@@ -43,7 +43,7 @@ pub const Config = struct {
 };
 
 pub fn num(n: u1) UART {
-    return @intToEnum(UART, n);
+    return @enumFromInt(UART, n);
 }
 
 pub const UART = enum(u1) {
@@ -63,7 +63,7 @@ pub const UART = enum(u1) {
     }
 
     fn get_regs(uart: UART) *volatile UartRegs {
-        return switch (@enumToInt(uart)) {
+        return switch (@intFromEnum(uart)) {
             0 => UART0,
             1 => UART1,
         };
@@ -122,7 +122,7 @@ pub const UART = enum(u1) {
     }
 
     pub fn dreq_tx(uart: UART) dma.Dreq {
-        return switch (@enumToInt(uart)) {
+        return switch (@intFromEnum(uart)) {
             0 => .uart0_tx,
             1 => .uart1_tx,
         };
diff --git a/src/hal/usb.zig b/src/hal/usb.zig
index e2147f536..60a9f6912 100644
--- a/src/hal/usb.zig
+++ b/src/hal/usb.zig
@@ -45,7 +45,7 @@ pub var EP0_OUT_CFG: usb.EndpointConfiguration = .{
         .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.EP0_OUT_ADDR,
-        .attributes = @enumToInt(usb.TransferType.Control),
+        .attributes = @intFromEnum(usb.TransferType.Control),
         .max_packet_size = 64,
         .interval = 0,
     },
@@ -60,7 +60,7 @@ pub var EP0_IN_CFG: usb.EndpointConfiguration = .{
         .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.EP0_IN_ADDR,
-        .attributes = @enumToInt(usb.TransferType.Control),
+        .attributes = @intFromEnum(usb.TransferType.Control),
         .max_packet_size = 64,
         .interval = 0,
     },
@@ -89,26 +89,26 @@ pub const buffers = struct {
 
     /// Mapping to the different data buffers in DPSRAM
     pub var B: usb.Buffers = .{
-        .ep0_buffer0 = @intToPtr([*]u8, USB_EP0_BUFFER0),
-        .ep0_buffer1 = @intToPtr([*]u8, USB_EP0_BUFFER1),
+        .ep0_buffer0 = @ptrFromInt([*]u8, USB_EP0_BUFFER0),
+        .ep0_buffer1 = @ptrFromInt([*]u8, USB_EP0_BUFFER1),
         // We will initialize this comptime in a loop
         .rest = .{
-            @intToPtr([*]u8, USB_BUFFERS + (0 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (1 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (2 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (3 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (4 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (5 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (6 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (7 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (8 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (9 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (10 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (11 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (12 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (13 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (14 * BUFFER_SIZE)),
-            @intToPtr([*]u8, USB_BUFFERS + (15 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (0 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (1 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (2 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (3 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (4 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (5 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (6 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (7 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (8 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (9 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (10 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (11 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (12 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (13 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (14 * BUFFER_SIZE)),
+            @ptrFromInt([*]u8, USB_BUFFERS + (15 * BUFFER_SIZE)),
         },
     };
 };
@@ -273,8 +273,8 @@ pub const F = struct {
             if (ep.endpoint_control_index) |epci| {
                 // We need to compute the offset from the base of USB SRAM to the
                 // buffer we're choosing, because that's how the peripheral do.
-                const buf_base = @ptrToInt(buffers.B.get(ep.data_buffer_index));
-                const dpram_base = @ptrToInt(peripherals.USBCTRL_DPRAM);
+                const buf_base = @intFromPtr(buffers.B.get(ep.data_buffer_index));
+                const dpram_base = @intFromPtr(peripherals.USBCTRL_DPRAM);
                 // The offset _should_ fit in a u16, but if we've gotten something
                 // wrong in the past few lines, a common symptom will be integer
                 // overflow producing a Very Large Number,

From 6e68f32b4bfab2c3756fc2250ab2e314d1837d7f Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 27 Jun 2023 20:31:39 -0700
Subject: [PATCH 173/286] update microzig (#20)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 958894191..9392fe0f7 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5
+Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791

From f74311e78502d500f4ae921549ce54a71c33b210 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 27 Jun 2023 20:31:52 -0700
Subject: [PATCH 174/286] update microzig (#23)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 958894191..9392fe0f7 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5
+Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791

From 32c4eacccf4ada2fa2110fc8555cc0151022cd29 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 27 Jun 2023 20:32:09 -0700
Subject: [PATCH 175/286] update microzig (#20)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 958894191..9392fe0f7 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5
+Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791

From f0441139a6718cec0ac92e6f6d99ba6563c4b0e4 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 27 Jun 2023 20:32:16 -0700
Subject: [PATCH 176/286] update microzig (#22)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 958894191..9392fe0f7 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5
+Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791

From c197a153127442e0e9af1456bc33faa45c2768dd Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 27 Jun 2023 20:32:24 -0700
Subject: [PATCH 177/286] update microzig (#67)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index a49fad973..9392fe0f7 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit a49fad973077dffd5fa0b392720295ad033f076e
+Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791

From e539cce4e54b27871d6ea69deaf1af23f594aa31 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 27 Jun 2023 20:32:35 -0700
Subject: [PATCH 178/286] update microzig (#20)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 958894191..9392fe0f7 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5
+Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791

From 7afd50f1a8bdd8c2d47a19728e7229249700898c Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 27 Jun 2023 20:32:46 -0700
Subject: [PATCH 179/286] update microzig (#22)

Co-authored-by: mattnite 
---
 deps/microzig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/deps/microzig b/deps/microzig
index 958894191..9392fe0f7 160000
--- a/deps/microzig
+++ b/deps/microzig
@@ -1 +1 @@
-Subproject commit 95889419155b7ffb1b11055549540096eaa2a6c5
+Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791

From 2b5c6096b03017748b0b5762657e5f3b2aa66533 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 27 Jun 2023 21:10:35 -0700
Subject: [PATCH 180/286] builtin type inference fix (#68)

---
 examples/flash_program.zig           |  2 +-
 examples/random.zig                  |  4 +-
 examples/squarewave.zig              | 29 +++++-----
 examples/usb_device.zig              | 12 ++---
 examples/usb_hid.zig                 | 12 ++---
 examples/ws2812.zig                  |  2 +-
 src/chips/RP2040.zig                 | 80 ++++++++++++++--------------
 src/hal/adc.zig                      | 14 ++---
 src/hal/clocks.zig                   |  4 +-
 src/hal/dma.zig                      |  4 +-
 src/hal/flash.zig                    |  2 +-
 src/hal/gpio.zig                     | 12 ++---
 src/hal/hw.zig                       | 12 ++---
 src/hal/i2c.zig                      | 14 ++---
 src/hal/multicore.zig                |  2 +-
 src/hal/pins.zig                     |  6 +--
 src/hal/pio.zig                      | 26 ++++-----
 src/hal/pio/assembler.zig            |  2 +-
 src/hal/pio/assembler/Expression.zig | 14 ++---
 src/hal/pio/assembler/encoder.zig    | 16 +++---
 src/hal/pio/assembler/tokenizer.zig  | 10 ++--
 src/hal/pwm.zig                      |  2 +-
 src/hal/random.zig                   |  4 +-
 src/hal/resets.zig                   | 10 ++--
 src/hal/rom.zig                      | 46 ++++++++--------
 src/hal/spi.zig                      |  6 +--
 src/hal/time.zig                     |  8 +--
 src/hal/uart.zig                     |  8 +--
 src/hal/usb.zig                      | 54 +++++++++----------
 29 files changed, 210 insertions(+), 207 deletions(-)

diff --git a/examples/flash_program.zig b/examples/flash_program.zig
index d38d0aea6..48754e165 100644
--- a/examples/flash_program.zig
+++ b/examples/flash_program.zig
@@ -14,7 +14,7 @@ const uart_tx_pin = gpio.num(0);
 const uart_rx_pin = gpio.num(1);
 
 const flash_target_offset: u32 = 256 * 1024;
-const flash_target_contents = @ptrFromInt([*]const u8, rp2040.flash.XIP_BASE + flash_target_offset);
+const flash_target_contents = @as([*]const u8, @ptrFromInt(rp2040.flash.XIP_BASE + flash_target_offset));
 
 pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
     std.log.err("panic: {s}", .{message});
diff --git a/examples/random.zig b/examples/random.zig
index 40d2f6816..34d03d1c7 100644
--- a/examples/random.zig
+++ b/examples/random.zig
@@ -52,7 +52,7 @@ pub fn main() !void {
         rng.bytes(buffer[0..]);
         counter += 8;
         for (buffer) |byte| {
-            dist[@intCast(usize, byte)] += 1;
+            dist[@as(usize, @intCast(byte))] += 1;
         }
         std.log.info("Generate random number: {any}", .{buffer});
 
@@ -60,7 +60,7 @@ pub fn main() !void {
             var i: usize = 0;
             std.log.info("Distribution:", .{});
             while (i < 256) : (i += 1) {
-                std.log.info("{} -> {}, {d:2}%", .{ i, dist[i], @floatFromInt(f32, dist[i]) / @floatFromInt(f32, counter) });
+                std.log.info("{} -> {}, {d:2}%", .{ i, dist[i], @as(f32, @floatFromInt(dist[i])) / @as(f32, @floatFromInt(counter)) });
             }
         }
         time.sleep_ms(1000);
diff --git a/examples/squarewave.zig b/examples/squarewave.zig
index 0564b6259..0894d9a0c 100644
--- a/examples/squarewave.zig
+++ b/examples/squarewave.zig
@@ -6,19 +6,22 @@ const gpio = rp2040.gpio;
 const Pio = rp2040.pio.Pio;
 const StateMachine = rp2040.pio.StateMachine;
 
-const squarewave_program = rp2040.pio.assemble(
-    \\;
-    \\; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
-    \\;
-    \\; SPDX-License-Identifier: BSD-3-Clause
-    \\;
-    \\.program squarewave
-    \\    set pindirs, 1   ; Set pin to output
-    \\again:
-    \\    set pins, 1 [1]  ; Drive pin high and then delay for one cycle
-    \\    set pins, 0      ; Drive pin low
-    \\    jmp again        ; Set PC to label `again`
-, .{}).get_program_by_name("squarewave");
+const squarewave_program = blk: {
+    @setEvalBranchQuota(2000);
+    break :blk rp2040.pio.assemble(
+        \\;
+        \\; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+        \\;
+        \\; SPDX-License-Identifier: BSD-3-Clause
+        \\;
+        \\.program squarewave
+        \\    set pindirs, 1   ; Set pin to output
+        \\again:
+        \\    set pins, 1 [1]  ; Drive pin high and then delay for one cycle
+        \\    set pins, 0      ; Drive pin low
+        \\    jmp again        ; Set PC to label `again`
+    , .{}).get_program_by_name("squarewave");
+};
 
 // Pick one PIO instance arbitrarily. We're also arbitrarily picking state
 // machine 0 on this PIO instance (the state machines are numbered 0 to 3
diff --git a/examples/usb_device.zig b/examples/usb_device.zig
index d2b243d6a..8f2d74e4f 100644
--- a/examples/usb_device.zig
+++ b/examples/usb_device.zig
@@ -38,7 +38,7 @@ fn ep1_out_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
 // add your own endpoints to...
 pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
     .descriptor = &usb.EndpointDescriptor{
-        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.Dir.Out.endpoint(1),
         .attributes = @intFromEnum(usb.TransferType.Bulk),
@@ -55,7 +55,7 @@ pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
 
 pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
     .descriptor = &usb.EndpointDescriptor{
-        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.Dir.In.endpoint(1),
         .attributes = @intFromEnum(usb.TransferType.Bulk),
@@ -73,7 +73,7 @@ pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
 // This is our device configuration
 pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
     .device_descriptor = &.{
-        .length = @intCast(u8, @sizeOf(usb.DeviceDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.DeviceDescriptor))),
         .descriptor_type = usb.DescType.Device,
         .bcd_usb = 0x0110,
         .device_class = 0,
@@ -89,7 +89,7 @@ pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
         .num_configurations = 1,
     },
     .interface_descriptor = &.{
-        .length = @intCast(u8, @sizeOf(usb.InterfaceDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.InterfaceDescriptor))),
         .descriptor_type = usb.DescType.Interface,
         .interface_number = 0,
         .alternate_setting = 0,
@@ -101,9 +101,9 @@ pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
         .interface_s = 0,
     },
     .config_descriptor = &.{
-        .length = @intCast(u8, @sizeOf(usb.ConfigurationDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor))),
         .descriptor_type = usb.DescType.Config,
-        .total_length = @intCast(u8, @sizeOf(usb.ConfigurationDescriptor) + @sizeOf(usb.InterfaceDescriptor) + @sizeOf(usb.EndpointDescriptor) + @sizeOf(usb.EndpointDescriptor)),
+        .total_length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor) + @sizeOf(usb.InterfaceDescriptor) + @sizeOf(usb.EndpointDescriptor) + @sizeOf(usb.EndpointDescriptor))),
         .num_interfaces = 1,
         .configuration_value = 1,
         .configuration_s = 0,
diff --git a/examples/usb_hid.zig b/examples/usb_hid.zig
index 2eced2b41..752111ad0 100644
--- a/examples/usb_hid.zig
+++ b/examples/usb_hid.zig
@@ -38,7 +38,7 @@ fn ep1_out_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
 // add your own endpoints to...
 pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
     .descriptor = &usb.EndpointDescriptor{
-        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.Dir.Out.endpoint(1),
         .attributes = @intFromEnum(usb.TransferType.Interrupt),
@@ -55,7 +55,7 @@ pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
 
 pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
     .descriptor = &usb.EndpointDescriptor{
-        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.Dir.In.endpoint(1),
         .attributes = @intFromEnum(usb.TransferType.Interrupt),
@@ -73,7 +73,7 @@ pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
 // This is our device configuration
 pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
     .device_descriptor = &.{
-        .length = @intCast(u8, @sizeOf(usb.DeviceDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.DeviceDescriptor))),
         .descriptor_type = usb.DescType.Device,
         .bcd_usb = 0x0200,
         .device_class = 0,
@@ -91,7 +91,7 @@ pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
         .num_configurations = 1,
     },
     .interface_descriptor = &.{
-        .length = @intCast(u8, @sizeOf(usb.InterfaceDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.InterfaceDescriptor))),
         .descriptor_type = usb.DescType.Interface,
         .interface_number = 0,
         .alternate_setting = 0,
@@ -103,9 +103,9 @@ pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
         .interface_s = 0,
     },
     .config_descriptor = &.{
-        .length = @intCast(u8, @sizeOf(usb.ConfigurationDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor))),
         .descriptor_type = usb.DescType.Config,
-        .total_length = @intCast(u8, @sizeOf(usb.ConfigurationDescriptor) + @sizeOf(usb.InterfaceDescriptor) + @sizeOf(usb.EndpointDescriptor) + @sizeOf(usb.EndpointDescriptor)),
+        .total_length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor) + @sizeOf(usb.InterfaceDescriptor) + @sizeOf(usb.EndpointDescriptor) + @sizeOf(usb.EndpointDescriptor))),
         .num_interfaces = 1,
         .configuration_value = 1,
         .configuration_s = 0,
diff --git a/examples/ws2812.zig b/examples/ws2812.zig
index f61204b3b..64fbac225 100644
--- a/examples/ws2812.zig
+++ b/examples/ws2812.zig
@@ -43,7 +43,7 @@ pub fn main() void {
     const cycles_per_bit: comptime_int = ws2812_program.defines[0].value + //T1
         ws2812_program.defines[1].value + //T2
         ws2812_program.defines[2].value; //T3
-    const div = @floatFromInt(f32, rp2040.clock_config.sys.?.output_freq) /
+    const div = @as(f32, @floatFromInt(rp2040.clock_config.sys.?.output_freq)) /
         (800_000 * cycles_per_bit);
 
     pio.sm_load_and_start_program(sm, ws2812_program, .{
diff --git a/src/chips/RP2040.zig b/src/chips/RP2040.zig
index 74f613486..a11f25564 100644
--- a/src/chips/RP2040.zig
+++ b/src/chips/RP2040.zig
@@ -65,9 +65,9 @@ pub const devices = struct {
 
         pub const peripherals = struct {
             ///  System Control Space
-            pub const MPU = @ptrFromInt(*volatile types.peripherals.SCS, 0xd90);
+            pub const MPU = @as(*volatile types.peripherals.SCS, @ptrFromInt(0xd90));
             ///  QSPI flash execute-in-place block
-            pub const XIP_CTRL = @ptrFromInt(*volatile types.peripherals.XIP_CTRL, 0x14000000);
+            pub const XIP_CTRL = @as(*volatile types.peripherals.XIP_CTRL, @ptrFromInt(0x14000000));
             ///  DW_apb_ssi has the following features:
             ///  * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.
             ///  * APB3 and APB4 protocol support.
@@ -94,27 +94,27 @@ pub const devices = struct {
             ///  - Interrupt polarity – active high interrupt lines.
             ///  - Serial clock polarity – low serial-clock polarity directly after reset.
             ///  - Serial clock phase – capture on first edge of serial-clock directly after reset.
-            pub const XIP_SSI = @ptrFromInt(*volatile types.peripherals.XIP_SSI, 0x18000000);
-            pub const SYSINFO = @ptrFromInt(*volatile types.peripherals.SYSINFO, 0x40000000);
+            pub const XIP_SSI = @as(*volatile types.peripherals.XIP_SSI, @ptrFromInt(0x18000000));
+            pub const SYSINFO = @as(*volatile types.peripherals.SYSINFO, @ptrFromInt(0x40000000));
             ///  Register block for various chip control signals
-            pub const SYSCFG = @ptrFromInt(*volatile types.peripherals.SYSCFG, 0x40004000);
-            pub const CLOCKS = @ptrFromInt(*volatile types.peripherals.CLOCKS, 0x40008000);
-            pub const RESETS = @ptrFromInt(*volatile types.peripherals.RESETS, 0x4000c000);
-            pub const PSM = @ptrFromInt(*volatile types.peripherals.PSM, 0x40010000);
-            pub const IO_BANK0 = @ptrFromInt(*volatile types.peripherals.IO_BANK0, 0x40014000);
-            pub const IO_QSPI = @ptrFromInt(*volatile types.peripherals.IO_QSPI, 0x40018000);
-            pub const PADS_BANK0 = @ptrFromInt(*volatile types.peripherals.PADS_BANK0, 0x4001c000);
-            pub const PADS_QSPI = @ptrFromInt(*volatile types.peripherals.PADS_QSPI, 0x40020000);
+            pub const SYSCFG = @as(*volatile types.peripherals.SYSCFG, @ptrFromInt(0x40004000));
+            pub const CLOCKS = @as(*volatile types.peripherals.CLOCKS, @ptrFromInt(0x40008000));
+            pub const RESETS = @as(*volatile types.peripherals.RESETS, @ptrFromInt(0x4000c000));
+            pub const PSM = @as(*volatile types.peripherals.PSM, @ptrFromInt(0x40010000));
+            pub const IO_BANK0 = @as(*volatile types.peripherals.IO_BANK0, @ptrFromInt(0x40014000));
+            pub const IO_QSPI = @as(*volatile types.peripherals.IO_QSPI, @ptrFromInt(0x40018000));
+            pub const PADS_BANK0 = @as(*volatile types.peripherals.PADS_BANK0, @ptrFromInt(0x4001c000));
+            pub const PADS_QSPI = @as(*volatile types.peripherals.PADS_QSPI, @ptrFromInt(0x40020000));
             ///  Controls the crystal oscillator
-            pub const XOSC = @ptrFromInt(*volatile types.peripherals.XOSC, 0x40024000);
-            pub const PLL_SYS = @ptrFromInt(*volatile types.peripherals.PLL_SYS, 0x40028000);
-            pub const PLL_USB = @ptrFromInt(*volatile types.peripherals.PLL_SYS, 0x4002c000);
+            pub const XOSC = @as(*volatile types.peripherals.XOSC, @ptrFromInt(0x40024000));
+            pub const PLL_SYS = @as(*volatile types.peripherals.PLL_SYS, @ptrFromInt(0x40028000));
+            pub const PLL_USB = @as(*volatile types.peripherals.PLL_SYS, @ptrFromInt(0x4002c000));
             ///  Register block for busfabric control signals and performance counters
-            pub const BUSCTRL = @ptrFromInt(*volatile types.peripherals.BUSCTRL, 0x40030000);
-            pub const UART0 = @ptrFromInt(*volatile types.peripherals.UART0, 0x40034000);
-            pub const UART1 = @ptrFromInt(*volatile types.peripherals.UART0, 0x40038000);
-            pub const SPI0 = @ptrFromInt(*volatile types.peripherals.SPI0, 0x4003c000);
-            pub const SPI1 = @ptrFromInt(*volatile types.peripherals.SPI0, 0x40040000);
+            pub const BUSCTRL = @as(*volatile types.peripherals.BUSCTRL, @ptrFromInt(0x40030000));
+            pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40034000));
+            pub const UART1 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40038000));
+            pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x4003c000));
+            pub const SPI1 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40040000));
             ///  DW_apb_i2c address block
             ///  List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
             ///  IC_ULTRA_FAST_MODE ................ 0x0
@@ -185,7 +185,7 @@ pub const devices = struct {
             ///  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
             ///  IC_DEFAULT_UFM_SPKLEN ............. 0x1
             ///  IC_TX_BUFFER_DEPTH ................ 16
-            pub const I2C0 = @ptrFromInt(*volatile types.peripherals.I2C0, 0x40044000);
+            pub const I2C0 = @as(*volatile types.peripherals.I2C0, @ptrFromInt(0x40044000));
             ///  DW_apb_i2c address block
             ///  List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
             ///  IC_ULTRA_FAST_MODE ................ 0x0
@@ -256,11 +256,11 @@ pub const devices = struct {
             ///  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
             ///  IC_DEFAULT_UFM_SPKLEN ............. 0x1
             ///  IC_TX_BUFFER_DEPTH ................ 16
-            pub const I2C1 = @ptrFromInt(*volatile types.peripherals.I2C0, 0x40048000);
+            pub const I2C1 = @as(*volatile types.peripherals.I2C0, @ptrFromInt(0x40048000));
             ///  Control and data interface to SAR ADC
-            pub const ADC = @ptrFromInt(*volatile types.peripherals.ADC, 0x4004c000);
+            pub const ADC = @as(*volatile types.peripherals.ADC, @ptrFromInt(0x4004c000));
             ///  Simple PWM
-            pub const PWM = @ptrFromInt(*volatile types.peripherals.PWM, 0x40050000);
+            pub const PWM = @as(*volatile types.peripherals.PWM, @ptrFromInt(0x40050000));
             ///  Controls time and alarms
             ///  time is a 64 bit value indicating the time in usec since power-on
             ///  timeh is the top 32 bits of time & timel is the bottom 32 bits
@@ -271,35 +271,35 @@ pub const devices = struct {
             ///  An alarm can be cancelled before it has finished by clearing the alarm_enable
             ///  When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared
             ///  To clear the interrupt write a 1 to the corresponding alarm_irq
-            pub const TIMER = @ptrFromInt(*volatile types.peripherals.TIMER, 0x40054000);
-            pub const WATCHDOG = @ptrFromInt(*volatile types.peripherals.WATCHDOG, 0x40058000);
+            pub const TIMER = @as(*volatile types.peripherals.TIMER, @ptrFromInt(0x40054000));
+            pub const WATCHDOG = @as(*volatile types.peripherals.WATCHDOG, @ptrFromInt(0x40058000));
             ///  Register block to control RTC
-            pub const RTC = @ptrFromInt(*volatile types.peripherals.RTC, 0x4005c000);
-            pub const ROSC = @ptrFromInt(*volatile types.peripherals.ROSC, 0x40060000);
+            pub const RTC = @as(*volatile types.peripherals.RTC, @ptrFromInt(0x4005c000));
+            pub const ROSC = @as(*volatile types.peripherals.ROSC, @ptrFromInt(0x40060000));
             ///  control and status for on-chip voltage regulator and chip level reset subsystem
-            pub const VREG_AND_CHIP_RESET = @ptrFromInt(*volatile types.peripherals.VREG_AND_CHIP_RESET, 0x40064000);
+            pub const VREG_AND_CHIP_RESET = @as(*volatile types.peripherals.VREG_AND_CHIP_RESET, @ptrFromInt(0x40064000));
             ///  Testbench manager. Allows the programmer to know what platform their software is running on.
-            pub const TBMAN = @ptrFromInt(*volatile types.peripherals.TBMAN, 0x4006c000);
+            pub const TBMAN = @as(*volatile types.peripherals.TBMAN, @ptrFromInt(0x4006c000));
             ///  DMA with separate read and write masters
-            pub const DMA = @ptrFromInt(*volatile types.peripherals.DMA, 0x50000000);
+            pub const DMA = @as(*volatile types.peripherals.DMA, @ptrFromInt(0x50000000));
             ///  DPRAM layout for USB device.
-            pub const USBCTRL_DPRAM = @ptrFromInt(*volatile types.peripherals.USBCTRL_DPRAM, 0x50100000);
+            pub const USBCTRL_DPRAM = @as(*volatile types.peripherals.USBCTRL_DPRAM, @ptrFromInt(0x50100000));
             ///  USB FS/LS controller device registers
-            pub const USBCTRL_REGS = @ptrFromInt(*volatile types.peripherals.USBCTRL_REGS, 0x50110000);
+            pub const USBCTRL_REGS = @as(*volatile types.peripherals.USBCTRL_REGS, @ptrFromInt(0x50110000));
             ///  Programmable IO block
-            pub const PIO0 = @ptrFromInt(*volatile types.peripherals.PIO0, 0x50200000);
+            pub const PIO0 = @as(*volatile types.peripherals.PIO0, @ptrFromInt(0x50200000));
             ///  Programmable IO block
-            pub const PIO1 = @ptrFromInt(*volatile types.peripherals.PIO0, 0x50300000);
+            pub const PIO1 = @as(*volatile types.peripherals.PIO0, @ptrFromInt(0x50300000));
             ///  Single-cycle IO block
             ///  Provides core-local and inter-core hardware for the two processors, with single-cycle access.
-            pub const SIO = @ptrFromInt(*volatile types.peripherals.SIO, 0xd0000000);
-            pub const PPB = @ptrFromInt(*volatile types.peripherals.PPB, 0xe0000000);
+            pub const SIO = @as(*volatile types.peripherals.SIO, @ptrFromInt(0xd0000000));
+            pub const PPB = @as(*volatile types.peripherals.PPB, @ptrFromInt(0xe0000000));
             ///  System Tick Timer
-            pub const SysTick = @ptrFromInt(*volatile types.peripherals.SysTick, 0xe000e010);
+            pub const SysTick = @as(*volatile types.peripherals.SysTick, @ptrFromInt(0xe000e010));
             ///  System Control Space
-            pub const NVIC = @ptrFromInt(*volatile types.peripherals.NVIC, 0xe000e100);
+            pub const NVIC = @as(*volatile types.peripherals.NVIC, @ptrFromInt(0xe000e100));
             ///  System Control Space
-            pub const SCB = @ptrFromInt(*volatile types.peripherals.SCB, 0xe000ed00);
+            pub const SCB = @as(*volatile types.peripherals.SCB, @ptrFromInt(0xe000ed00));
         };
     };
 };
diff --git a/src/hal/adc.zig b/src/hal/adc.zig
index 973db6320..e025a6373 100644
--- a/src/hal/adc.zig
+++ b/src/hal/adc.zig
@@ -17,7 +17,7 @@ pub const Error = error{
 
 /// temp_sensor is not valid because you can refer to it by name.
 pub fn input(n: u2) Input {
-    return @enumFromInt(Input, n);
+    return @as(Input, @enumFromInt(n));
 }
 
 /// Enable the ADC controller.
@@ -50,7 +50,7 @@ pub fn apply(config: Config) void {
         .ERR_STICKY = 0,
         .AINSEL = 0,
         .RROBIN = if (config.round_robin) |rr|
-            @bitCast(u5, rr)
+            @as(u5, @bitCast(rr))
         else
             0,
 
@@ -63,8 +63,8 @@ pub fn apply(config: Config) void {
     if (config.sample_frequency) |sample_frequency| {
         const cycles = (48_000_000 * 256) / @as(u64, sample_frequency);
         ADC.DIV.write(.{
-            .FRAC = @truncate(u8, cycles),
-            .INT = @intCast(u16, (cycles >> 8) - 1),
+            .FRAC = @as(u8, @truncate(cycles)),
+            .INT = @as(u16, @intCast((cycles >> 8) - 1)),
 
             .padding = 0,
         });
@@ -85,7 +85,7 @@ pub fn select_input(in: Input) void {
 /// 4 is the temperature sensor.
 pub fn get_selected_input() Input {
     const cs = ADC.SC.read();
-    return @enumFromInt(Input, cs.AINSEL);
+    return @as(Input, @enumFromInt(cs.AINSEL));
 }
 
 pub const Input = enum(u3) {
@@ -126,7 +126,7 @@ pub fn set_temp_sensor_enabled(enable: bool) void {
 /// T must be floating point.
 pub fn temp_sensor_result_to_celcius(comptime T: type, comptime vref: T, result: u12) T {
     // TODO: consider fixed-point
-    const raw = @floatFromInt(T, result);
+    const raw = @as(T, @floatFromInt(result));
     const voltage: T = vref * raw / 0x0fff;
     return (27.0 - ((voltage - 0.706) / 0.001721));
 }
@@ -144,7 +144,7 @@ pub const InputMask = packed struct(u5) {
 /// 0 will disable round-robin mode but `disableRoundRobin()` is provided so
 /// the user may be explicit.
 pub fn round_robin_set(enabled_inputs: InputMask) void {
-    ADC.CS.modify(.{ .RROBIN = @bitCast(u5, enabled_inputs) });
+    ADC.CS.modify(.{ .RROBIN = @as(u5, @bitCast(enabled_inputs)) });
 }
 
 /// Disable round-robin sample mode.
diff --git a/src/hal/clocks.zig b/src/hal/clocks.zig
index cb5350f9e..9a027aa76 100644
--- a/src/hal/clocks.zig
+++ b/src/hal/clocks.zig
@@ -83,7 +83,7 @@ pub const Generator = enum(u32) {
         assert(24 == @sizeOf([2]GeneratorRegs));
     }
 
-    const generators = @ptrCast(*volatile [@typeInfo(Generator).Enum.fields.len]GeneratorRegs, CLOCKS);
+    const generators = @as(*volatile [@typeInfo(Generator).Enum.fields.len]GeneratorRegs, @ptrCast(CLOCKS));
 
     fn get_regs(generator: Generator) *volatile GeneratorRegs {
         return &generators[@intFromEnum(generator)];
@@ -617,7 +617,7 @@ pub const Configuration = struct {
         // source frequency has to be faster because dividing will always reduce.
         assert(input.freq >= output_freq);
 
-        const div = @intCast(u32, (@intCast(u64, input.freq) << 8) / output_freq);
+        const div = @as(u32, @intCast((@as(u64, @intCast(input.freq)) << 8) / output_freq));
 
         // check divisor
         if (div > generator.get_div())
diff --git a/src/hal/dma.zig b/src/hal/dma.zig
index 35b285a5c..469966f2a 100644
--- a/src/hal/dma.zig
+++ b/src/hal/dma.zig
@@ -19,7 +19,7 @@ pub const Dreq = enum(u6) {
 pub fn channel(n: u4) Channel {
     assert(n < num_channels);
 
-    return @enumFromInt(Channel, n);
+    return @as(Channel, @enumFromInt(n));
 }
 
 pub fn claim_unused_channel() ?Channel {
@@ -76,7 +76,7 @@ pub const Channel = enum(u4) {
     };
 
     fn get_regs(chan: Channel) *volatile Regs {
-        const regs = @ptrCast(*volatile [12]Regs, &DMA.CH0_READ_ADDR);
+        const regs = @as(*volatile [12]Regs, @ptrCast(&DMA.CH0_READ_ADDR));
         return ®s[@intFromEnum(chan)];
     }
 
diff --git a/src/hal/flash.zig b/src/hal/flash.zig
index cb86c72d3..7ce32060d 100644
--- a/src/hal/flash.zig
+++ b/src/hal/flash.zig
@@ -23,7 +23,7 @@ pub const boot2 = struct {
     /// Copy the 2nd stage bootloader into memory
     pub fn flash_init() linksection(".time_critical") void {
         if (copyout_valid) return;
-        const bootloader = @ptrFromInt([*]u32, XIP_BASE);
+        const bootloader = @as([*]u32, @ptrFromInt(XIP_BASE));
         var i: usize = 0;
         while (i < BOOT2_SIZE_BYTES) : (i += 1) {
             copyout[i] = bootloader[i];
diff --git a/src/hal/gpio.zig b/src/hal/gpio.zig
index 3b9e5aea2..dffe3d1f4 100644
--- a/src/hal/gpio.zig
+++ b/src/hal/gpio.zig
@@ -72,11 +72,11 @@ pub fn num(n: u5) Pin {
     if (n > 29)
         @panic("the RP2040 only has GPIO 0-29");
 
-    return @enumFromInt(Pin, n);
+    return @as(Pin, @enumFromInt(n));
 }
 
 pub fn mask(m: u32) Mask {
-    return @enumFromInt(Mask, m);
+    return @as(Mask, @enumFromInt(m));
 }
 
 pub const Mask = enum(u30) {
@@ -85,7 +85,7 @@ pub const Mask = enum(u30) {
     pub fn set_function(self: Mask, function: Function) void {
         const raw_mask = @intFromEnum(self);
         for (0..@bitSizeOf(Mask)) |i| {
-            const bit = @intCast(u5, i);
+            const bit = @as(u5, @intCast(i));
             if (0 != raw_mask & (@as(u32, 1) << bit))
                 num(bit).set_function(function);
         }
@@ -102,7 +102,7 @@ pub const Mask = enum(u30) {
     pub fn set_pull(self: Mask, pull: ?Pull) void {
         const raw_mask = @intFromEnum(self);
         for (0..@bitSizeOf(Mask)) |i| {
-            const bit = @intCast(u5, i);
+            const bit = @as(u5, @intCast(i));
             if (0 != raw_mask & (@as(u32, 1) << bit))
                 num(bit).set_pull(pull);
         }
@@ -154,12 +154,12 @@ pub const Pin = enum(u5) {
     pub const PadsReg = @TypeOf(PADS_BANK0.GPIO0);
 
     fn get_regs(gpio: Pin) *volatile Regs {
-        const regs = @ptrCast(*volatile [30]Regs, &IO_BANK0.GPIO0_STATUS);
+        const regs = @as(*volatile [30]Regs, @ptrCast(&IO_BANK0.GPIO0_STATUS));
         return ®s[@intFromEnum(gpio)];
     }
 
     fn get_pads_reg(gpio: Pin) *volatile PadsReg {
-        const regs = @ptrCast(*volatile [30]PadsReg, &PADS_BANK0.GPIO0);
+        const regs = @as(*volatile [30]PadsReg, @ptrCast(&PADS_BANK0.GPIO0));
         return ®s[@intFromEnum(gpio)];
     }
 
diff --git a/src/hal/hw.zig b/src/hal/hw.zig
index 28a198105..8227027de 100644
--- a/src/hal/hw.zig
+++ b/src/hal/hw.zig
@@ -20,27 +20,27 @@ const set_bits = @as(u32, 0x2) << 12;
 const clear_bits = @as(u32, 0x3) << 12;
 
 pub fn clear_alias_raw(ptr: anytype) *volatile u32 {
-    return @ptrFromInt(*volatile u32, @intFromPtr(ptr) | clear_bits);
+    return @as(*volatile u32, @ptrFromInt(@intFromPtr(ptr) | clear_bits));
 }
 
 pub fn set_alias_raw(ptr: anytype) *volatile u32 {
-    return @ptrFromInt(*volatile u32, @intFromPtr(ptr) | set_bits);
+    return @as(*volatile u32, @ptrFromInt(@intFromPtr(ptr) | set_bits));
 }
 
 pub fn xor_alias_raw(ptr: anytype) *volatile u32 {
-    return @ptrFromInt(*volatile u32, @intFromPtr(ptr) | xor_bits);
+    return @as(*volatile u32, @ptrFromInt(@intFromPtr(ptr) | xor_bits));
 }
 
 pub fn clear_alias(ptr: anytype) @TypeOf(ptr) {
-    return @ptrFromInt(@TypeOf(ptr), @intFromPtr(ptr) | clear_bits);
+    return @as(@TypeOf(ptr), @ptrFromInt(@intFromPtr(ptr) | clear_bits));
 }
 
 pub fn set_alias(ptr: anytype) @TypeOf(ptr) {
-    return @ptrFromInt(@TypeOf(ptr), @intFromPtr(ptr) | set_bits);
+    return @as(@TypeOf(ptr), @ptrFromInt(@intFromPtr(ptr) | set_bits));
 }
 
 pub fn xor_alias(ptr: anytype) @TypeOf(ptr) {
-    return @ptrFromInt(@TypeOf(ptr), @intFromPtr(ptr) | xor_bits);
+    return @as(@TypeOf(ptr), @ptrFromInt(@intFromPtr(ptr) | xor_bits));
 }
 
 pub inline fn tight_loop_contents() void {
diff --git a/src/hal/i2c.zig b/src/hal/i2c.zig
index cc7467ee8..b000e35e6 100644
--- a/src/hal/i2c.zig
+++ b/src/hal/i2c.zig
@@ -20,14 +20,14 @@ pub const Config = struct {
 };
 
 pub fn num(n: u1) I2C {
-    return @enumFromInt(I2C, n);
+    return @as(I2C, @enumFromInt(n));
 }
 
 pub const Address = enum(u7) {
     _,
 
     pub fn new(addr: u7) Address {
-        var a = @enumFromInt(Address, addr);
+        var a = @as(Address, @enumFromInt(addr));
         std.debug.assert(!a.is_reserved());
         return a;
     }
@@ -167,10 +167,10 @@ pub const I2C = enum(u1) {
 
         // Always use "fast" mode (<= 400 kHz, works fine for standard mode too)
         regs.IC_CON.modify(.{ .SPEED = .{ .value = .FAST } });
-        regs.IC_FS_SCL_HCNT.write(.{ .IC_FS_SCL_HCNT = @intCast(u16, hcnt), .padding = 0 });
-        regs.IC_FS_SCL_LCNT.write(.{ .IC_FS_SCL_LCNT = @intCast(u16, lcnt), .padding = 0 });
-        regs.IC_FS_SPKLEN.write(.{ .IC_FS_SPKLEN = if (lcnt < 16) 1 else @intCast(u8, lcnt / 16), .padding = 0 });
-        regs.IC_SDA_HOLD.modify(.{ .IC_SDA_TX_HOLD = @intCast(u16, sda_tx_hold_count) });
+        regs.IC_FS_SCL_HCNT.write(.{ .IC_FS_SCL_HCNT = @as(u16, @intCast(hcnt)), .padding = 0 });
+        regs.IC_FS_SCL_LCNT.write(.{ .IC_FS_SCL_LCNT = @as(u16, @intCast(lcnt)), .padding = 0 });
+        regs.IC_FS_SPKLEN.write(.{ .IC_FS_SPKLEN = if (lcnt < 16) 1 else @as(u8, @intCast(lcnt / 16)), .padding = 0 });
+        regs.IC_SDA_HOLD.modify(.{ .IC_SDA_TX_HOLD = @as(u16, @intCast(sda_tx_hold_count)) });
 
         i2c.enable();
 
@@ -343,7 +343,7 @@ pub const I2C = enum(u1) {
                 }
 
                 const abort_reason = regs.IC_TX_ABRT_SOURCE.read();
-                if (@bitCast(u32, abort_reason) != 0) {
+                if (@as(u32, @bitCast(abort_reason)) != 0) {
                     // Note clearing the abort flag also clears the reason, and
                     // this instance of flag is clear-on-read! Note also the
                     // IC_CLR_TX_ABRT register always reads as 0.
diff --git a/src/hal/multicore.zig b/src/hal/multicore.zig
index bc2b4de78..1ca3ebbe2 100644
--- a/src/hal/multicore.zig
+++ b/src/hal/multicore.zig
@@ -70,7 +70,7 @@ pub fn launch_core1_with_stack(entrypoint: *const fn () void, stack: []u32) void
         fn wrapper(_: u32, _: u32, _: u32, _: u32, entry: u32, stack_base: [*]u32) callconv(.C) void {
             // TODO: protect stack using MPU
             _ = stack_base;
-            @ptrFromInt(*const fn () void, entry)();
+            @as(*const fn () void, @ptrFromInt(entry))();
         }
     }.wrapper;
 
diff --git a/src/hal/pins.zig b/src/hal/pins.zig
index 5de0810c3..3ca323865 100644
--- a/src/hal/pins.zig
+++ b/src/hal/pins.zig
@@ -362,13 +362,13 @@ pub fn Pins(comptime config: GlobalConfiguration) type {
                 } else if (pin_config.function.is_adc()) {
                     pin_field.name = pin_config.name orelse @tagName(pin_config.function);
                     pin_field.type = adc.Input;
-                    pin_field.default_value = @ptrCast(?*const anyopaque, switch (pin_config.function) {
+                    pin_field.default_value = @as(?*const anyopaque, @ptrCast(switch (pin_config.function) {
                         .ADC0 => &adc.Input.ain0,
                         .ADC1 => &adc.Input.ain1,
                         .ADC2 => &adc.Input.ain2,
                         .ADC3 => &adc.Input.ain3,
                         else => unreachable,
-                    });
+                    }));
                 } else {
                     continue;
                 }
@@ -536,7 +536,7 @@ pub const GlobalConfiguration = struct {
         var ret: Pins(config) = undefined;
         inline for (@typeInfo(Pins(config)).Struct.fields) |field| {
             if (field.default_value) |default_value| {
-                @field(ret, field.name) = @ptrCast(*const field.field_type, default_value).*;
+                @field(ret, field.name) = @as(*const field.field_type, @ptrCast(default_value)).*;
             } else {
                 @field(ret, field.name) = .{};
             }
diff --git a/src/hal/pio.zig b/src/hal/pio.zig
index 6b7ca1fb6..9472728d2 100644
--- a/src/hal/pio.zig
+++ b/src/hal/pio.zig
@@ -74,10 +74,10 @@ pub const ClkDivOptions = struct {
     frac: u8 = 0,
 
     pub fn from_float(div: f32) ClkDivOptions {
-        const fixed = @intFromFloat(u24, div * 256);
+        const fixed = @as(u24, @intFromFloat(div * 256));
         return ClkDivOptions{
-            .int = @truncate(u16, fixed >> 8),
-            .frac = @truncate(u8, fixed),
+            .int = @as(u16, @truncate(fixed >> 8)),
+            .frac = @as(u8, @truncate(fixed)),
         };
     }
 };
@@ -154,7 +154,7 @@ pub const Pio = enum(u1) {
 
     pub fn get_instruction_memory(self: Pio) *volatile [32]u32 {
         const regs = self.get_regs();
-        return @ptrCast(*volatile [32]u32, ®s.INSTR_MEM0);
+        return @as(*volatile [32]u32, @ptrCast(®s.INSTR_MEM0));
     }
 
     pub fn gpio_init(self: Pio, pin: gpio.Pin) void {
@@ -184,7 +184,7 @@ pub const Pio = enum(u1) {
             else
                 error.NoSpace
         else for (0..(32 - program.instructions.len)) |i| {
-            const offset = @intCast(u5, i);
+            const offset = @as(u5, @intCast(i));
             if (self.can_add_program_at_offset(program, offset))
                 break offset;
         } else error.NoSpace;
@@ -218,23 +218,23 @@ pub const Pio = enum(u1) {
 
         const claimed_mask = claimed_state_machines[@intFromEnum(self)];
         return for (0..4) |i| {
-            const sm_mask = (@as(u4, 1) << @intCast(u2, i));
+            const sm_mask = (@as(u4, 1) << @as(u2, @intCast(i)));
             if (0 == (claimed_mask & sm_mask)) {
                 claimed_state_machines[@intFromEnum(self)] |= sm_mask;
-                break @enumFromInt(StateMachine, i);
+                break @as(StateMachine, @enumFromInt(i));
             }
         } else error.NoSpace;
     }
 
     pub fn get_sm_regs(self: Pio, sm: StateMachine) *volatile StateMachine.Regs {
         const pio_regs = self.get_regs();
-        const sm_regs = @ptrCast(*volatile [4]StateMachine.Regs, &pio_regs.SM0_CLKDIV);
+        const sm_regs = @as(*volatile [4]StateMachine.Regs, @ptrCast(&pio_regs.SM0_CLKDIV));
         return &sm_regs[@intFromEnum(sm)];
     }
 
     fn get_irq_regs(self: Pio, irq: Irq) *volatile Irq.Regs {
         const pio_regs = self.get_regs();
-        const irq_regs = @ptrCast(*volatile [2]Irq.Regs, &pio_regs.IRQ0_INTE);
+        const irq_regs = @as(*volatile [2]Irq.Regs, @ptrCast(&pio_regs.IRQ0_INTE));
         return &irq_regs[@intFromEnum(irq)];
     }
 
@@ -313,7 +313,7 @@ pub const Pio = enum(u1) {
 
     pub fn sm_get_tx_fifo(self: Pio, sm: StateMachine) *volatile u32 {
         const regs = self.get_regs();
-        const fifos = @ptrCast(*volatile [4]u32, ®s.TXF0);
+        const fifos = @as(*volatile [4]u32, @ptrCast(®s.TXF0));
         return &fifos[@intFromEnum(sm)];
     }
 
@@ -386,7 +386,7 @@ pub const Pio = enum(u1) {
         const regs = self.get_regs();
         const levels = regs.FLEVEL.raw;
 
-        return @truncate(u4, levels >> (@as(u5, 4) * num) + offset);
+        return @as(u4, @truncate(levels >> (@as(u5, 4) * num) + offset));
     }
 
     fn interrupt_bit_pos(
@@ -469,7 +469,7 @@ pub const Pio = enum(u1) {
 
     pub fn sm_exec(self: Pio, sm: StateMachine, instruction: Instruction) void {
         const sm_regs = self.get_sm_regs(sm);
-        sm_regs.instr.raw = @bitCast(u16, instruction);
+        sm_regs.instr.raw = @as(u16, @bitCast(instruction));
     }
 
     pub fn sm_load_and_start_program(
@@ -498,7 +498,7 @@ pub const Pio = enum(u1) {
                 .wrap = if (program.wrap) |wrap|
                     wrap
                 else
-                    offset + @intCast(u5, program.instructions.len),
+                    offset + @as(u5, @intCast(program.instructions.len)),
 
                 .wrap_target = if (program.wrap_target) |wrap_target|
                     wrap_target
diff --git a/src/hal/pio/assembler.zig b/src/hal/pio/assembler.zig
index 1c38816ff..6c6be6f6f 100644
--- a/src/hal/pio/assembler.zig
+++ b/src/hal/pio/assembler.zig
@@ -22,7 +22,7 @@ pub const Program = struct {
     wrap: ?u5,
 
     pub fn get_mask(program: Program) u32 {
-        return (@as(u32, 1) << @intCast(u5, program.instructions.len)) - 1;
+        return (@as(u32, 1) << @as(u5, @intCast(program.instructions.len))) - 1;
     }
 };
 
diff --git a/src/hal/pio/assembler/Expression.zig b/src/hal/pio/assembler/Expression.zig
index 794b5c3b1..789fb78a4 100644
--- a/src/hal/pio/assembler/Expression.zig
+++ b/src/hal/pio/assembler/Expression.zig
@@ -123,7 +123,7 @@ fn trim_outer_parenthesis(str: []const u8) TrimResult {
 
     return TrimResult{
         .str = str[start..end],
-        .index = @intCast(u32, start),
+        .index = @as(u32, @intCast(start)),
     };
 }
 
@@ -142,9 +142,9 @@ fn recursive_tokenize(
 
     var parenthesis_found = false;
     var depth: u32 = 0;
-    var i = @intCast(i32, expr_str.len - 1);
+    var i = @as(i32, @intCast(expr_str.len - 1));
     outer: while (i >= 0) : (i -= 1) {
-        const idx = @intCast(u32, i);
+        const idx = @as(u32, @intCast(i));
         // TODO: how about if the expression is fully enveloped in parenthesis?
         switch (expr_str[idx]) {
             ')' => {
@@ -176,7 +176,7 @@ fn recursive_tokenize(
                 const is_negative = (i == 0) or is_negative: {
                     var j = i - 1;
                     while (j >= 0) : (j -= 1) {
-                        const jdx = @intCast(u32, j);
+                        const jdx = @as(u32, @intCast(j));
                         switch (expr_str[jdx]) {
                             ' ', '\t' => continue,
                             '+', '-', '*', '/' => continue :outer,
@@ -229,7 +229,7 @@ fn recursive_tokenize(
     } else {
         // if we hit this path, then the full string has been scanned, and no operators
         const trimmed = std.mem.trim(u8, expr_str, " \t");
-        const value_index = expr_index + @intCast(u32, std.mem.indexOf(u8, expr_str, trimmed).?);
+        const value_index = expr_index + @as(u32, @intCast(std.mem.indexOf(u8, expr_str, trimmed).?));
         try ops.append(.{
             .op = .value,
             .index = value_index,
@@ -242,7 +242,7 @@ fn recursive_tokenize(
     }
 
     if (depth != 0) {
-        diags.* = Diagnostics.init(expr_index + @intCast(u32, i), "mismatched parenthesis", .{});
+        diags.* = Diagnostics.init(expr_index + @as(u32, @intCast(i)), "mismatched parenthesis", .{});
         return error.MismatchedParenthesis;
     }
 }
@@ -349,7 +349,7 @@ fn recursive_evaluate(
             }
 
             break :blk .{
-                .value = @bitCast(i128, @bitReverse(@bitCast(u128, values[0].num)) >> (128 - 32)),
+                .value = @as(i128, @bitCast(@bitReverse(@as(u128, @bitCast(values[0].num))) >> (128 - 32))),
                 .index = values[0].index,
                 .consumed = .{
                     .ops = 2,
diff --git a/src/hal/pio/assembler/encoder.zig b/src/hal/pio/assembler/encoder.zig
index 502b37470..0d13c1b46 100644
--- a/src/hal/pio/assembler/encoder.zig
+++ b/src/hal/pio/assembler/encoder.zig
@@ -87,13 +87,13 @@ pub fn Encoder(comptime options: Options) type {
                             std.mem.copy(u8, &define_name, define.name);
                             tmp.append(.{
                                 .name = &define_name,
-                                .value = @intCast(i64, define.value),
+                                .value = @as(i64, @intCast(define.value)),
                             }) catch unreachable;
                         }
 
                         break :blk tmp.slice();
                     },
-                    .instructions = @ptrCast([]const u16, bounded.instructions.slice()),
+                    .instructions = @as([]const u16, @ptrCast(bounded.instructions.slice())),
                     .origin = bounded.origin,
                     .side_set = bounded.side_set,
                     .wrap_target = bounded.wrap_target,
@@ -152,7 +152,7 @@ pub fn Encoder(comptime options: Options) type {
             diags: *?Diagnostics,
         ) !T {
             return switch (value) {
-                .integer => |int| @intCast(T, int),
+                .integer => |int| @as(T, @intCast(int)),
                 .string => |str| outer: for (define_lists) |defines| {
                     for (defines) |define| {
                         if (std.mem.eql(u8, str, define.name)) {
@@ -166,7 +166,7 @@ pub fn Encoder(comptime options: Options) type {
                                 break :outer error.TooBig;
                             }
 
-                            break :outer @intCast(T, define.value);
+                            break :outer @as(T, @intCast(define.value));
                         }
                     }
                 } else {
@@ -189,7 +189,7 @@ pub fn Encoder(comptime options: Options) type {
                         );
                     }
 
-                    return @intCast(T, result);
+                    return @as(T, @intCast(result));
                 },
             };
         }
@@ -482,19 +482,19 @@ pub fn Encoder(comptime options: Options) type {
                 switch (token.data) {
                     .instruction => |instr| try self.encode_instruction(program, instr, token.index, diags),
                     .word => |word| try program.instructions.append(
-                        @bitCast(Instruction, try self.evaluate(u16, program.*, word, token.index, diags)),
+                        @as(Instruction, @bitCast(try self.evaluate(u16, program.*, word, token.index, diags))),
                     ),
                     // already processed
                     .label, .wrap_target, .wrap => {},
                     .program => {
-                        self.index = @intCast(u32, i);
+                        self.index = @as(u32, @intCast(i));
                         break;
                     },
 
                     else => unreachable, // invalid
                 }
             } else if (self.tokens.len > 0)
-                self.index = @intCast(u32, self.tokens.len);
+                self.index = @as(u32, @intCast(self.tokens.len));
         }
 
         fn encode_program(self: *Self, diags: *?Diagnostics) !?BoundedProgram {
diff --git a/src/hal/pio/assembler/tokenizer.zig b/src/hal/pio/assembler/tokenizer.zig
index 29c596d2e..2aef42830 100644
--- a/src/hal/pio/assembler/tokenizer.zig
+++ b/src/hal/pio/assembler/tokenizer.zig
@@ -199,7 +199,7 @@ pub const Tokenizer = struct {
 
     fn consume_peek(self: *Tokenizer, result: PeekResult) void {
         assert(self.index <= result.start);
-        self.index = result.start + @intCast(u32, result.str.len);
+        self.index = result.start + @as(u32, @intCast(result.str.len));
     }
 
     /// gets next arg without consuming the stream
@@ -616,7 +616,7 @@ pub const Tokenizer = struct {
         const bit_count = if (bit_count_tmp == 32)
             @as(u5, 0)
         else
-            @intCast(u5, bit_count_tmp);
+            @as(u5, @intCast(bit_count_tmp));
 
         return Token.Instruction.Payload{
             .in = .{
@@ -635,7 +635,7 @@ pub const Tokenizer = struct {
         const bit_count = if (bit_count_tmp == 32)
             @as(u5, 0)
         else
-            @intCast(u5, bit_count_tmp);
+            @as(u5, @intCast(bit_count_tmp));
 
         return Token.Instruction.Payload{
             .out = .{
@@ -1644,7 +1644,7 @@ test "tokenize.instr.in" {
 
         try expect_instr_in(.{
             .source = @field(Token.Instruction.In.Source, source),
-            .bit_count = @intCast(u5, bit_count),
+            .bit_count = @as(u5, @intCast(bit_count)),
         }, tokens.get(0));
     }
 }
@@ -1667,7 +1667,7 @@ test "tokenize.instr.out" {
 
         try expect_instr_out(.{
             .destination = @field(Token.Instruction.Out.Destination, destination),
-            .bit_count = @intCast(u5, bit_count),
+            .bit_count = @as(u5, @intCast(bit_count)),
         }, tokens.get(0));
     }
 }
diff --git a/src/hal/pwm.zig b/src/hal/pwm.zig
index 6e5fe1d3f..82c3756c4 100644
--- a/src/hal/pwm.zig
+++ b/src/hal/pwm.zig
@@ -10,7 +10,7 @@ fn get_regs(comptime slice: u32) *volatile Regs {
     @import("std").debug.assert(slice < 8);
     const PwmType = microzig.chip.types.peripherals.PWM;
     const reg_diff = comptime @offsetOf(PwmType, "CH1_CSR") - @offsetOf(PwmType, "CH0_CSR");
-    return @ptrFromInt(*volatile Regs, @intFromPtr(PWM) + reg_diff * slice);
+    return @as(*volatile Regs, @ptrFromInt(@intFromPtr(PWM) + reg_diff * slice));
 }
 
 pub fn Pwm(comptime slice_num: u32, comptime chan: Channel) type {
diff --git a/src/hal/random.zig b/src/hal/random.zig
index 3a292a628..b7f102f88 100644
--- a/src/hal/random.zig
+++ b/src/hal/random.zig
@@ -76,10 +76,10 @@ pub const Ascon = struct {
         var i: usize = 0;
         while (i < buffer.len) : (i += 1) {
             // We poll RANDOMBIT eight times per cycle to build a random byte
-            var r: u8 = @intCast(u8, peripherals.ROSC.RANDOMBIT.read().RANDOMBIT);
+            var r: u8 = @as(u8, @intCast(peripherals.ROSC.RANDOMBIT.read().RANDOMBIT));
             var j: usize = 0;
             while (j < 7) : (j += 1) {
-                r = (r << 1) | @intCast(u8, peripherals.ROSC.RANDOMBIT.read().RANDOMBIT);
+                r = (r << 1) | @as(u8, @intCast(peripherals.ROSC.RANDOMBIT.read().RANDOMBIT));
             }
             buffer[i] = r;
         }
diff --git a/src/hal/resets.zig b/src/hal/resets.zig
index a35ad79e9..3bffa6f6f 100644
--- a/src/hal/resets.zig
+++ b/src/hal/resets.zig
@@ -36,7 +36,7 @@ pub const Mask = packed struct(u32) {
 };
 
 pub fn reset(mask: Mask) void {
-    const raw_mask = @bitCast(u32, mask);
+    const raw_mask = @as(u32, @bitCast(mask));
 
     RESETS.RESET.raw = raw_mask;
     RESETS.RESET.raw = 0;
@@ -45,22 +45,22 @@ pub fn reset(mask: Mask) void {
 }
 
 pub inline fn reset_block(mask: Mask) void {
-    hw.set_alias_raw(&RESETS.RESET).* = @bitCast(u32, mask);
+    hw.set_alias_raw(&RESETS.RESET).* = @as(u32, @bitCast(mask));
 }
 
 pub inline fn unreset_block(mask: Mask) void {
-    hw.clear_alias_raw(&RESETS.RESET).* = @bitCast(u32, mask);
+    hw.clear_alias_raw(&RESETS.RESET).* = @as(u32, @bitCast(mask));
 }
 
 pub fn unreset_block_wait(mask: Mask) void {
-    const raw_mask = @bitCast(u32, mask);
+    const raw_mask = @as(u32, @bitCast(mask));
     hw.clear_alias_raw(&RESETS.RESET).* = raw_mask;
 
     // have to bitcast after a read() instead of `RESETS.RESET_DONE.raw` due to
     // some optimization bug. While loops will not be optimzed away if the
     // condition has side effects like dereferencing a volatile pointer.
     // It seems that volatile is not propagating correctly.
-    while (@bitCast(u32, RESETS.RESET_DONE.read()) & raw_mask != raw_mask) {}
+    while (@as(u32, @bitCast(RESETS.RESET_DONE.read())) & raw_mask != raw_mask) {}
 }
 
 pub const masks = struct {
diff --git a/src/hal/rom.zig b/src/hal/rom.zig
index 7b2538750..a3980741c 100644
--- a/src/hal/rom.zig
+++ b/src/hal/rom.zig
@@ -88,7 +88,7 @@ pub const signatures = struct {
 ///
 /// A 32 bit address pointing into bootrom
 pub fn rom_table_code(c1: u8, c2: u8) u32 {
-    return @intCast(u32, c1) | (@intCast(u32, c2) << 8);
+    return @as(u32, @intCast(c1)) | (@as(u32, @intCast(c2)) << 8);
 }
 
 /// Convert a 16 bit pointer stored at the given rom address into a pointer
@@ -100,8 +100,8 @@ pub fn rom_table_code(c1: u8, c2: u8) u32 {
 ///
 /// The converted pointer
 pub inline fn rom_hword_as_ptr(rom_addr: u32) *anyopaque {
-    const ptr_to_ptr = @ptrFromInt(*u16, rom_addr);
-    return @ptrFromInt(*anyopaque, @intCast(usize, ptr_to_ptr.*));
+    const ptr_to_ptr = @as(*u16, @ptrFromInt(rom_addr));
+    return @as(*anyopaque, @ptrFromInt(@as(usize, @intCast(ptr_to_ptr.*))));
 }
 
 /// Lookup a bootrom function by code (inline)
@@ -113,8 +113,8 @@ pub inline fn rom_hword_as_ptr(rom_addr: u32) *anyopaque {
 ///
 /// A anyopaque pointer to the function; must be cast by the caller
 pub inline fn _rom_func_lookup(code: Code) *anyopaque {
-    const rom_table_lookup = @ptrCast(*signatures.rom_table_lookup, rom_hword_as_ptr(0x18));
-    const func_table = @ptrCast(*u16, @alignCast(2, rom_hword_as_ptr(0x14)));
+    const rom_table_lookup = @as(*signatures.rom_table_lookup, @ptrCast(rom_hword_as_ptr(0x18)));
+    const func_table = @as(*u16, @ptrCast(@alignCast(rom_hword_as_ptr(0x14))));
     return rom_table_lookup(func_table, @intFromEnum(code));
 }
 
@@ -140,7 +140,7 @@ pub fn popcount32(value: u32) u32 {
         var f: ?*signatures.popcount32 = null;
     };
 
-    if (S.f == null) S.f = @ptrCast(*signatures.popcount32, _rom_func_lookup(Code.popcount32));
+    if (S.f == null) S.f = @as(*signatures.popcount32, @ptrCast(_rom_func_lookup(Code.popcount32)));
     return S.f.?(value);
 }
 
@@ -150,7 +150,7 @@ pub fn reverse32(value: u32) u32 {
         var f: ?*signatures.reverse32 = null;
     };
 
-    if (S.f == null) S.f = @ptrCast(*signatures.reverse32, _rom_func_lookup(Code.reverse32));
+    if (S.f == null) S.f = @as(*signatures.reverse32, @ptrCast(_rom_func_lookup(Code.reverse32)));
     return S.f.?(value);
 }
 
@@ -160,7 +160,7 @@ pub fn clz32(value: u32) u32 {
         var f: ?*signatures.clz32 = null;
     };
 
-    if (S.f == null) S.f = @ptrCast(*signatures.clz32, _rom_func_lookup(Code.clz32));
+    if (S.f == null) S.f = @as(*signatures.clz32, @ptrCast(_rom_func_lookup(Code.clz32)));
     return S.f.?(value);
 }
 
@@ -170,7 +170,7 @@ pub fn ctz32(value: u32) u32 {
         var f: ?*signatures.ctz32 = null;
     };
 
-    if (S.f == null) S.f = @ptrCast(*signatures.ctz32, _rom_func_lookup(Code.ctz32));
+    if (S.f == null) S.f = @as(*signatures.ctz32, @ptrCast(_rom_func_lookup(Code.ctz32)));
     return S.f.?(value);
 }
 
@@ -184,7 +184,7 @@ pub fn memset(dest: []u8, c: u8) []u8 {
         var f: ?*signatures.memset = null;
     };
 
-    if (S.f == null) S.f = @ptrCast(*signatures.memset, _rom_func_lookup(Code.memset));
+    if (S.f == null) S.f = @as(*signatures.memset, @ptrCast(_rom_func_lookup(Code.memset)));
     return S.f.?(dest.ptr, c, dest.len)[0..dest.len];
 }
 
@@ -196,7 +196,7 @@ pub fn memcpy(dest: []u8, src: []const u8) []u8 {
 
     const n = if (dest.len <= src.len) dest.len else src.len;
 
-    if (S.f == null) S.f = @ptrCast(*signatures.memcpy, _rom_func_lookup(Code.memcpy));
+    if (S.f == null) S.f = @as(*signatures.memcpy, @ptrCast(_rom_func_lookup(Code.memcpy)));
     return S.f.?(dest.ptr, src.ptr, n)[0..n];
 }
 
@@ -206,9 +206,9 @@ pub fn memcpy(dest: []u8, src: []const u8) []u8 {
 
 /// Restore all QSPI pad controls to their default state, and connect the SSI to the QSPI pads
 pub inline fn connect_internal_flash() *signatures.connect_internal_flash {
-    return @ptrCast(
+    return @as(
         *signatures.connect_internal_flash,
-        _rom_func_lookup(Code.connect_internal_flash),
+        @ptrCast(_rom_func_lookup(Code.connect_internal_flash)),
     );
 }
 
@@ -218,9 +218,9 @@ pub inline fn connect_internal_flash() *signatures.connect_internal_flash {
 /// SSI to XIP mode (e.g. by a call to _flash_flush_cache). This function configures
 /// the SSI with a fixed SCK clock divisor of /6.
 pub inline fn flash_exit_xip() *signatures.flash_exit_xip {
-    return @ptrCast(
+    return @as(
         *signatures.flash_exit_xip,
-        _rom_func_lookup(Code.flash_exit_xip),
+        @ptrCast(_rom_func_lookup(Code.flash_exit_xip)),
     );
 }
 
@@ -230,9 +230,9 @@ pub inline fn flash_exit_xip() *signatures.flash_exit_xip {
 /// possible, for much higher erase speed. addr must be aligned to a 4096-byte sector,
 /// and count must be a multiple of 4096 bytes.
 pub inline fn flash_range_erase() *signatures.flash_range_erase {
-    return @ptrCast(
+    return @as(
         *signatures.flash_range_erase,
-        _rom_func_lookup(Code.flash_range_erase),
+        @ptrCast(_rom_func_lookup(Code.flash_range_erase)),
     );
 }
 
@@ -240,18 +240,18 @@ pub inline fn flash_range_erase() *signatures.flash_range_erase {
 /// start of flash) and count bytes in size. addr must be aligned to a 256-byte
 /// boundary, and the length of data must be a multiple of 256.
 pub inline fn flash_range_program() *signatures.flash_range_program {
-    return @ptrCast(
+    return @as(
         *signatures.flash_range_program,
-        _rom_func_lookup(Code.flash_range_program),
+        @ptrCast(_rom_func_lookup(Code.flash_range_program)),
     );
 }
 
 /// Flush and enable the XIP cache. Also clears the IO forcing on QSPI CSn, so that
 /// the SSI can drive the flash chip select as normal.
 pub inline fn flash_flush_cache() *signatures.flash_flush_cache {
-    return @ptrCast(
+    return @as(
         *signatures.flash_flush_cache,
-        _rom_func_lookup(Code.flash_flush_cache),
+        @ptrCast(_rom_func_lookup(Code.flash_flush_cache)),
     );
 }
 
@@ -262,8 +262,8 @@ pub inline fn flash_flush_cache() *signatures.flash_flush_cache {
 /// visible to the debug host, without having to know exactly what kind of flash
 /// device is connected.
 pub inline fn flash_enter_cmd_xip() *signatures.flash_enter_cmd_xip {
-    return @ptrCast(
+    return @as(
         *signatures.flash_enter_cmd_xip,
-        _rom_func_lookup(Code.flash_enter_cmd_xip),
+        @ptrCast(_rom_func_lookup(Code.flash_enter_cmd_xip)),
     );
 }
diff --git a/src/hal/spi.zig b/src/hal/spi.zig
index 251b61bc7..b9b8891a1 100644
--- a/src/hal/spi.zig
+++ b/src/hal/spi.zig
@@ -22,7 +22,7 @@ pub const Config = struct {
 };
 
 pub fn num(n: u1) SPI {
-    return @enumFromInt(SPI, n);
+    return @as(SPI, @enumFromInt(n));
 }
 
 pub const SPI = enum(u1) {
@@ -161,8 +161,8 @@ pub const SPI = enum(u1) {
         while (postdiv > 1) : (postdiv -= 1) {
             if (freq_in / (prescale * (postdiv - 1)) > baudrate) break;
         }
-        spi_regs.SSPCPSR.modify(.{ .CPSDVSR = @intCast(u8, prescale) });
-        spi_regs.SSPCR0.modify(.{ .SCR = @intCast(u8, postdiv - 1) });
+        spi_regs.SSPCPSR.modify(.{ .CPSDVSR = @as(u8, @intCast(prescale)) });
+        spi_regs.SSPCR0.modify(.{ .SCR = @as(u8, @intCast(postdiv - 1)) });
 
         // Return the frequency we were able to achieve
         return freq_in / (prescale * postdiv);
diff --git a/src/hal/time.zig b/src/hal/time.zig
index 95691cc10..6bf69323d 100644
--- a/src/hal/time.zig
+++ b/src/hal/time.zig
@@ -7,7 +7,7 @@ pub const Absolute = enum(u64) {
     _,
 
     pub fn from_us(us: u64) Absolute {
-        return @enumFromInt(Absolute, us);
+        return @as(Absolute, @enumFromInt(us));
     }
 
     pub fn to_us(time: Absolute) u64 {
@@ -36,7 +36,7 @@ pub const Duration = enum(u64) {
     _,
 
     pub fn from_us(us: u64) Duration {
-        return @enumFromInt(Duration, us);
+        return @as(Duration, @enumFromInt(us));
     }
 
     pub fn from_ms(ms: u64) Duration {
@@ -67,14 +67,14 @@ pub fn get_time_since_boot() Absolute {
         var low_word = TIMER.TIMERAWL;
         const next_high_word = TIMER.TIMERAWH;
         if (next_high_word == high_word)
-            break @enumFromInt(Absolute, @intCast(u64, high_word) << 32 | low_word);
+            break @as(Absolute, @enumFromInt(@as(u64, @intCast(high_word)) << 32 | low_word));
 
         high_word = next_high_word;
     } else unreachable;
 }
 
 pub fn make_timeout_us(timeout_us: u64) Absolute {
-    return @enumFromInt(Absolute, get_time_since_boot().to_us() + timeout_us);
+    return @as(Absolute, @enumFromInt(get_time_since_boot().to_us() + timeout_us));
 }
 
 pub fn sleep_ms(time_ms: u32) void {
diff --git a/src/hal/uart.zig b/src/hal/uart.zig
index 678d9799d..5e4162cd3 100644
--- a/src/hal/uart.zig
+++ b/src/hal/uart.zig
@@ -43,7 +43,7 @@ pub const Config = struct {
 };
 
 pub fn num(n: u1) UART {
-    return @enumFromInt(UART, n);
+    return @as(UART, @enumFromInt(n));
 }
 
 pub const UART = enum(u1) {
@@ -118,7 +118,7 @@ pub const UART = enum(u1) {
 
     pub fn tx_fifo(uart: UART) *volatile u32 {
         const regs = uart.get_regs();
-        return @ptrCast(*volatile u32, ®s.UARTDR);
+        return @as(*volatile u32, @ptrCast(®s.UARTDR));
     }
 
     pub fn dreq_tx(uart: UART) dma.Dreq {
@@ -180,7 +180,7 @@ pub const UART = enum(u1) {
         assert(baud_rate > 0);
         const uart_regs = uart.get_regs();
         const baud_rate_div = (8 * peri_freq / baud_rate);
-        var baud_ibrd = @intCast(u16, baud_rate_div >> 7);
+        var baud_ibrd = @as(u16, @intCast(baud_rate_div >> 7));
 
         const baud_fbrd: u6 = if (baud_ibrd == 0) baud_fbrd: {
             baud_ibrd = 1;
@@ -188,7 +188,7 @@ pub const UART = enum(u1) {
         } else if (baud_ibrd >= 65535) baud_fbrd: {
             baud_ibrd = 65535;
             break :baud_fbrd 0;
-        } else @intCast(u6, ((@truncate(u7, baud_rate_div)) + 1) / 2);
+        } else @as(u6, @intCast(((@as(u7, @truncate(baud_rate_div))) + 1) / 2));
 
         uart_regs.UARTIBRD.write(.{ .BAUD_DIVINT = baud_ibrd, .padding = 0 });
         uart_regs.UARTFBRD.write(.{ .BAUD_DIVFRAC = baud_fbrd, .padding = 0 });
diff --git a/src/hal/usb.zig b/src/hal/usb.zig
index 60a9f6912..317704706 100644
--- a/src/hal/usb.zig
+++ b/src/hal/usb.zig
@@ -42,7 +42,7 @@ pub const utf8ToUtf16Le = usb.utf8Toutf16Le;
 
 pub var EP0_OUT_CFG: usb.EndpointConfiguration = .{
     .descriptor = &usb.EndpointDescriptor{
-        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.EP0_OUT_ADDR,
         .attributes = @intFromEnum(usb.TransferType.Control),
@@ -57,7 +57,7 @@ pub var EP0_OUT_CFG: usb.EndpointConfiguration = .{
 
 pub var EP0_IN_CFG: usb.EndpointConfiguration = .{
     .descriptor = &usb.EndpointDescriptor{
-        .length = @intCast(u8, @sizeOf(usb.EndpointDescriptor)),
+        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
         .descriptor_type = usb.DescType.Endpoint,
         .endpoint_address = usb.EP0_IN_ADDR,
         .attributes = @intFromEnum(usb.TransferType.Control),
@@ -89,26 +89,26 @@ pub const buffers = struct {
 
     /// Mapping to the different data buffers in DPSRAM
     pub var B: usb.Buffers = .{
-        .ep0_buffer0 = @ptrFromInt([*]u8, USB_EP0_BUFFER0),
-        .ep0_buffer1 = @ptrFromInt([*]u8, USB_EP0_BUFFER1),
+        .ep0_buffer0 = @as([*]u8, @ptrFromInt(USB_EP0_BUFFER0)),
+        .ep0_buffer1 = @as([*]u8, @ptrFromInt(USB_EP0_BUFFER1)),
         // We will initialize this comptime in a loop
         .rest = .{
-            @ptrFromInt([*]u8, USB_BUFFERS + (0 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (1 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (2 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (3 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (4 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (5 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (6 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (7 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (8 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (9 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (10 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (11 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (12 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (13 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (14 * BUFFER_SIZE)),
-            @ptrFromInt([*]u8, USB_BUFFERS + (15 * BUFFER_SIZE)),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (0 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (1 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (2 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (3 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (4 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (5 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (6 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (7 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (8 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (9 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (10 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (11 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (12 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (13 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (14 * BUFFER_SIZE))),
+            @as([*]u8, @ptrFromInt(USB_BUFFERS + (15 * BUFFER_SIZE))),
         },
     };
 };
@@ -278,7 +278,7 @@ pub const F = struct {
                 // The offset _should_ fit in a u16, but if we've gotten something
                 // wrong in the past few lines, a common symptom will be integer
                 // overflow producing a Very Large Number,
-                const dpram_offset = @intCast(u16, buf_base - dpram_base);
+                const dpram_offset = @as(u16, @intCast(buf_base - dpram_base));
 
                 // Configure the endpoint!
                 modify_endpoint_control(epci, .{
@@ -287,7 +287,7 @@ pub const F = struct {
                     // buffer is done, thx.
                     .INTERRUPT_PER_BUFF = 1,
                     // Select bulk vs control (or interrupt as soon as implemented).
-                    .ENDPOINT_TYPE = .{ .raw = @intCast(u2, ep.descriptor.attributes) },
+                    .ENDPOINT_TYPE = .{ .raw = @as(u2, @intCast(ep.descriptor.attributes)) },
                     // And, designate our buffer by its offset.
                     .BUFFER_ADDRESS = dpram_offset,
                 });
@@ -331,7 +331,7 @@ pub const F = struct {
         modify_buffer_control(ep.buffer_control_index, .{
             .PID_0 = np, // DATA0/1, depending
             .FULL_0 = 1, // We have put data in
-            .LENGTH_0 = @intCast(u10, buffer.len), // There are this many bytes
+            .LENGTH_0 = @as(u10, @intCast(buffer.len)), // There are this many bytes
         });
 
         // Nop for some clock cycles
@@ -367,7 +367,7 @@ pub const F = struct {
             .PID_0 = np, // DATA0/1 depending
             .FULL_0 = 0, // Buffer is NOT full, we want the computer to fill it
             .AVAILABLE_0 = 1, // It is, however, available to be filled
-            .LENGTH_0 = @intCast(u10, len), // Up tho this many bytes
+            .LENGTH_0 = @as(u10, @intCast(len)), // Up tho this many bytes
         });
 
         // Flip the DATA0/1 PID for the next receive
@@ -588,14 +588,14 @@ pub fn next(self: *usb.EPBIter) ?usb.EPB {
     var lowbit_index: u5 = 0;
     while ((self.bufbits >> lowbit_index) & 0x01 == 0) : (lowbit_index += 1) {}
     // Remove their bit from our set.
-    const lowbit = @intCast(u32, 1) << lowbit_index;
+    const lowbit = @as(u32, @intCast(1)) << lowbit_index;
     self.last_bit = lowbit;
     self.bufbits ^= lowbit;
 
     // Here we exploit knowledge of the ordering of buffer control
     // registers in the peripheral. Each endpoint has a pair of
     // registers, so we can determine the endpoint number by:
-    const epnum = @intCast(u8, lowbit_index >> 1);
+    const epnum = @as(u8, @intCast(lowbit_index >> 1));
     // Of the pair, the IN endpoint comes first, followed by OUT, so
     // we can get the direction by:
     const dir = if (lowbit_index & 1 == 0) usb.Dir.In else usb.Dir.Out;
@@ -637,7 +637,7 @@ pub fn next(self: *usb.EPBIter) ?usb.EPB {
 
     // Get the actual length of the data, which may be less
     // than the buffer size.
-    const len = @intCast(usize, bc & 0x3ff);
+    const len = @as(usize, @intCast(bc & 0x3ff));
 
     // Copy the data from SRAM
     return usb.EPB{

From 360655dbe23b2fd2350ebf2221496eada8b890b6 Mon Sep 17 00:00:00 2001
From: Vlad Panazan 
Date: Thu, 29 Jun 2023 22:53:47 +0200
Subject: [PATCH 181/286] use zig package manager (#70)

---
 .gitmodules    |  3 ---
 build.zig      |  2 +-
 build.zig.zon  | 11 +++++++++++
 deps/microzig  |  1 -
 src/boards.zig |  2 +-
 src/chips.zig  |  2 +-
 6 files changed, 14 insertions(+), 7 deletions(-)
 delete mode 100644 .gitmodules
 create mode 100644 build.zig.zon
 delete mode 160000 deps/microzig

diff --git a/.gitmodules b/.gitmodules
deleted file mode 100644
index 32e895ccb..000000000
--- a/.gitmodules
+++ /dev/null
@@ -1,3 +0,0 @@
-[submodule "deps/microzig"]
-	path = deps/microzig
-	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/build.zig b/build.zig
index 4afab69d2..c690810e8 100644
--- a/build.zig
+++ b/build.zig
@@ -4,7 +4,7 @@ const Pkg = std.build.Pkg;
 const comptimePrint = std.fmt.comptimePrint;
 const FileSource = std.build.FileSource;
 
-pub const microzig = @import("deps/microzig/build.zig");
+const microzig = @import("microzig");
 
 pub const chips = @import("src/chips.zig");
 pub const boards = @import("src/boards.zig");
diff --git a/build.zig.zon b/build.zig.zon
new file mode 100644
index 000000000..32cee6627
--- /dev/null
+++ b/build.zig.zon
@@ -0,0 +1,11 @@
+.{
+    .name = "rp2040",
+    .version = "0.0.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/9392fe0f7bddde26155c181ab80b70097b49c791.tar.gz",
+            .hash = "1220326148075cd017425e04356329c33c3e794d31a54bdafa46521fcfcc55b422a3",
+        },
+    },
+}
+
diff --git a/deps/microzig b/deps/microzig
deleted file mode 160000
index 9392fe0f7..000000000
--- a/deps/microzig
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791
diff --git a/src/boards.zig b/src/boards.zig
index ebbf0d8cc..d2af0ee1e 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/build.zig");
+const microzig = @import("microzig");
 const chips = @import("chips.zig");
 
 fn root_dir() []const u8 {
diff --git a/src/chips.zig b/src/chips.zig
index 8363cea7a..48b20e033 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/build.zig");
+const microzig = @import("microzig");
 
 fn root_dir() []const u8 {
     return std.fs.path.dirname(@src().file) orelse ".";

From 35e9757bdb9873ffd7a5d2c192842cf93b58c7e5 Mon Sep 17 00:00:00 2001
From: Vlad Panazan 
Date: Sat, 1 Jul 2023 15:22:51 +0200
Subject: [PATCH 182/286] fix i2c reading and add bus scan example (#71)

---
 build.zig                 |  1 +
 examples/i2c_bus_scan.zig | 44 +++++++++++++++++++++++++++++++++++++++
 src/hal/i2c.zig           | 13 +++++++-----
 3 files changed, 53 insertions(+), 5 deletions(-)
 create mode 100644 examples/i2c_bus_scan.zig

diff --git a/build.zig b/build.zig
index c690810e8..e75a1099a 100644
--- a/build.zig
+++ b/build.zig
@@ -63,6 +63,7 @@ pub const Examples = struct {
     blinky: *microzig.EmbeddedExecutable,
     blinky_core1: *microzig.EmbeddedExecutable,
     gpio_clk: *microzig.EmbeddedExecutable,
+    i2c_bus_scan: *microzig.EmbeddedExecutable,
     pwm: *microzig.EmbeddedExecutable,
     spi_master: *microzig.EmbeddedExecutable,
     uart: *microzig.EmbeddedExecutable,
diff --git a/examples/i2c_bus_scan.zig b/examples/i2c_bus_scan.zig
new file mode 100644
index 000000000..702bcefc3
--- /dev/null
+++ b/examples/i2c_bus_scan.zig
@@ -0,0 +1,44 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const i2c = rp2040.i2c;
+const gpio = rp2040.gpio;
+const peripherals = microzig.chip.peripherals;
+
+pub const std_options = struct {
+    pub const log_level = .info;
+    pub const logFn = rp2040.uart.log;
+};
+
+const uart = rp2040.uart.num(0);
+const i2c0 = i2c.num(0);
+
+pub fn main() !void {
+    uart.apply(.{
+        .baud_rate = 115200,
+        .tx_pin = gpio.num(0),
+        .rx_pin = gpio.num(1),
+        .clock_config = rp2040.clock_config,
+    });
+    rp2040.uart.init_logger(uart);
+
+    _ = i2c0.apply(.{
+        .clock_config = rp2040.clock_config,
+        .scl_pin = gpio.num(4),
+        .sda_pin = gpio.num(5),
+    });
+
+    for (0..std.math.maxInt(u7)) |addr| {
+        const a: i2c.Address = @enumFromInt(addr);
+
+        // Skip over any reserved addresses.
+        if (a.is_reserved()) continue;
+
+        var rx_data: [1]u8 = undefined;
+        _ = i2c0.read_blocking(a, &rx_data) catch continue;
+
+        std.log.info("I2C device found at address {X}.", .{addr});
+    }
+}
+
diff --git a/src/hal/i2c.zig b/src/hal/i2c.zig
index b000e35e6..a6c151741 100644
--- a/src/hal/i2c.zig
+++ b/src/hal/i2c.zig
@@ -243,12 +243,13 @@ pub const I2C = enum(u1) {
                 _ = tc;
             }
         };
-        try i2c.read_blocking_internal(addr, dst, Timeout{});
+        return i2c.read_blocking_internal(addr, dst, Timeout{});
     }
 
     /// Determine non-blocking write space available.
     pub inline fn get_write_available(i2c: I2C) u5 {
-        return i2c.get_regs().IC_TXFLR.read().TXFLR;
+        const IC_TX_BUFFER_DEPTH = 16;
+        return IC_TX_BUFFER_DEPTH - i2c.get_regs().IC_TXFLR.read().TXFLR;
     }
 
     /// Determine number of bytes received.
@@ -378,7 +379,7 @@ pub const I2C = enum(u1) {
         for (dst, 0..) |*byte, i| {
             const first = (i == 0);
             const last = (i == dst.len - 1);
-            while (i2c.get_write_available(i2c) == 0) {
+            while (i2c.get_write_available() == 0) {
                 hw.tight_loop_contents();
             }
 
@@ -388,11 +389,11 @@ pub const I2C = enum(u1) {
                 .CMD = .{ .value = .READ },
 
                 .DAT = 0,
-                .FIRST_DATA_BYTE = .{ .value = 0 },
+                .FIRST_DATA_BYTE = .{ .raw = 0 },
                 .padding = 0,
             });
 
-            while (i2c.get_read_available() == 0) {
+            while (true) {
                 const abort_reason = regs.IC_TX_ABRT_SOURCE.read();
                 const abort = (regs.IC_CLR_TX_ABRT.read().CLR_TX_ABRT != 0);
                 if (abort) {
@@ -403,6 +404,8 @@ pub const I2C = enum(u1) {
                 }
 
                 try timeout_check.perform();
+
+                if (i2c.get_read_available() != 0) break;
             }
 
             byte.* = regs.IC_DATA_CMD.read().DAT;

From d6b3be320f8f9dd0958a9ab460da991f57fd7722 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Mon, 24 Jul 2023 15:01:19 +0200
Subject: [PATCH 183/286] rp2040-flasher inital commit (#72)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-authored-by: Felix (xq) Queißner 
---
 build.zig              |  14 ++
 build.zig.zon          |   5 +-
 tools/rp2040-flash.zig | 331 +++++++++++++++++++++++++++++++++++++++++
 3 files changed, 349 insertions(+), 1 deletion(-)
 create mode 100644 tools/rp2040-flash.zig

diff --git a/build.zig b/build.zig
index e75a1099a..b9f2803ee 100644
--- a/build.zig
+++ b/build.zig
@@ -39,6 +39,10 @@ pub fn addPiPicoExecutable(
 // project requires multiple HALs, it accepts microzig as a param
 pub fn build(b: *Builder) !void {
     const optimize = b.standardOptimizeOption(.{});
+
+    const args_dep = b.dependency("args", .{});
+    const args_mod = args_dep.module("args");
+
     var examples = Examples.init(b, optimize);
     examples.install(b);
 
@@ -52,6 +56,16 @@ pub fn build(b: *Builder) !void {
 
     const test_step = b.step("test", "run unit tests");
     test_step.dependOn(&b.addRunArtifact(pio_tests).step);
+
+    const flash_tool = b.addExecutable(.{
+        .name = "rp2040-flash",
+        .optimize = .Debug,
+        .target = .{},
+        .root_source_file = .{ .path = "tools/rp2040-flash.zig" },
+    });
+    flash_tool.addModule("args", args_mod);
+
+    b.installArtifact(flash_tool);
 }
 
 fn root() []const u8 {
diff --git a/build.zig.zon b/build.zig.zon
index 32cee6627..d8db2dbc9 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -6,6 +6,9 @@
             .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/9392fe0f7bddde26155c181ab80b70097b49c791.tar.gz",
             .hash = "1220326148075cd017425e04356329c33c3e794d31a54bdafa46521fcfcc55b422a3",
         },
+        .args = .{
+            .url = "https://github.com/MasterQ32/zig-args/archive/91d1e89fb89a4d01dec7c9aec95b0a324080ebcc.tar.gz",
+            .hash = "12203d04cafc97f952d74cdb077e74c0ab3414f9f6b5fbd159112c62bfa584a0dbed",
+        },
     },
 }
-
diff --git a/tools/rp2040-flash.zig b/tools/rp2040-flash.zig
new file mode 100644
index 000000000..23b48acbf
--- /dev/null
+++ b/tools/rp2040-flash.zig
@@ -0,0 +1,331 @@
+const std = @import("std");
+const args_parser = @import("args");
+const builtin = @import("builtin");
+
+const CliOptions = struct {
+    help: bool = false,
+    device: ?[]const u8 = null,
+    wait: bool = false,
+
+    pub const shorthands = .{
+        .h = "help",
+        .d = "device",
+        .w = "wait",
+    };
+};
+
+const wait_device_ready_timeout = 60 * std.time.ns_per_s; // timeout until a device is found
+const wait_device_avail_timeout = 60 * std.time.ns_per_s; // timeout until a device is found
+const access_denied_limit = 20; // try that many times with AccessDenied before the user is informed
+
+fn print_usage(file: std.fs.File, exe: ?[]const u8) !void {
+    try file.writer().writeAll(exe orelse "rp2040-flash");
+    try file.writer().writeAll(
+        \\ [-h] [-d ] 
+        \\Flash your RP2040 devices easily via UF2 interface.
+        \\
+        \\Options:
+        \\  -h, --help          Shows this help text.
+        \\  -d, --device  Uses  as the UF2 device. Otherwise tries to auto-guess the correct device.
+        \\  -w, --wait          Waits 60 seconds until a device appears.
+        \\
+    );
+}
+
+pub fn main() !u8 {
+    const stderr = std.io.getStdErr();
+    const stdout = std.io.getStdOut();
+    const stdin = std.io.getStdIn();
+
+    var arena = std.heap.ArenaAllocator.init(std.heap.page_allocator);
+    defer _ = arena.deinit();
+
+    const allocator = arena.allocator();
+
+    var cli = args_parser.parseForCurrentProcess(CliOptions, allocator, .print) catch return 1;
+    defer cli.deinit();
+
+    if (cli.options.help) {
+        try print_usage(stdout, cli.executable_name);
+        return 0;
+    }
+
+    if (cli.positionals.len != 1) {
+        try print_usage(stderr, cli.executable_name);
+        return 1;
+    }
+
+    const uf2_file_path = cli.positionals[0];
+
+    var uf2_file = try std.fs.cwd().openFile(uf2_file_path, .{});
+    defer uf2_file.close();
+
+    const uf2_stat = try uf2_file.stat();
+    if ((uf2_stat.size % 512) != 0) {
+        std.log.warn("{s} does not have a size multiple of 512. might be corrupt!", .{uf2_file_path});
+    }
+
+    const file_valid = blk: {
+        try uf2_file.seekTo(0);
+
+        var file_valid = true;
+
+        while (file_valid) {
+            var block: [512]u8 = undefined;
+            const len = try uf2_file.read(&block);
+            if (len == 0)
+                break;
+
+            // 0    4   First magic number, 0x0A324655 ("UF2\n")
+            // 4    4   Second magic number, 0x9E5D5157
+            // 8    4   Flags
+            // 12   4   Address in flash where the data should be written
+            // 16   4   Number of bytes used in data (often 256)
+            // 20   4   Sequential block number; starts at 0
+            // 24   4   Total number of blocks in file
+            // 28   4   File size or board family ID or zero
+            //                          32   476 Data, padded with zeros
+            // 508  4   Final magic number, 0x0AB16F30
+
+            const first_magic_number = std.mem.readIntLittle(u32, block[0..][0..4]);
+            const second_magic_number = std.mem.readIntLittle(u32, block[4..][0..4]);
+            const final_magic_number = std.mem.readIntLittle(u32, block[508..][0..4]);
+
+            file_valid = file_valid and (first_magic_number == 0x0A324655);
+            file_valid = file_valid and (second_magic_number == 0x9E5D5157);
+            file_valid = file_valid and (final_magic_number == 0x0AB16F30);
+        }
+        break :blk file_valid;
+    };
+
+    if (file_valid == false) {
+        std.log.warn("{s} does not seem to be a valid UF2 file. Do you really want to flash it?", .{uf2_file_path});
+        while (true) {
+            try stderr.writer().writeAll("Flash? [jN]: ");
+
+            var buffer: [64]u8 = undefined;
+            const selection_or_null = try stdin.reader().readUntilDelimiterOrEof(&buffer, '\n');
+
+            const selection_str = std.mem.trim(u8, selection_or_null orelse "", "\r\n\t ");
+            if (selection_str.len == 0)
+                return 1;
+
+            if (std.ascii.eqlIgnoreCase(selection_str, "j"))
+                break;
+
+            if (std.ascii.eqlIgnoreCase(selection_str, "n"))
+                return 1;
+        }
+    }
+
+    try uf2_file.seekTo(0);
+
+    const detect_timeout = std.time.nanoTimestamp() + wait_device_avail_timeout;
+    var first_run = true;
+    const device_path = if (cli.options.device) |devname|
+        try allocator.dupe(u8, devname)
+    else while (true) {
+        if (std.time.nanoTimestamp() >= detect_timeout) {
+            try stderr.writeAll("failed to detect any RP2040 devices :(\n");
+
+            return 1;
+        }
+
+        const maybe_device = try autoDetectPico(allocator);
+
+        if (maybe_device) |device|
+            break device;
+
+        if (!cli.options.wait) {
+            try stderr.writeAll("failed to detect any RP2040 devices :(\n");
+            return 1;
+        }
+
+        if (first_run) {
+            try stderr.writeAll("failed to detect any RP2040 devices, waiting...\n");
+            first_run = false;
+        }
+
+        std.time.sleep(250 * std.time.ns_per_ms);
+    };
+
+    const connect_timeout = std.time.nanoTimestamp() + wait_device_ready_timeout;
+
+    var first_attempt = true;
+    var access_denied_counter: u32 = 0;
+    var last_err: anyerror = error.Unknown;
+    var device_file: std.fs.File = blk: while (std.time.nanoTimestamp() < connect_timeout) {
+        var device = std.fs.cwd().openFile(device_path, .{ .mode = .write_only }) catch |err| {
+            last_err = err;
+
+            switch (err) {
+                error.FileNotFound => {}, // just waiting for the device
+                error.AccessDenied => {
+                    access_denied_counter += 1;
+                    if (access_denied_counter >= access_denied_limit) {
+                        try stderr.writer().print("Could not open {s}: Access denied. Do you have write-access to the device?\n", .{device_path});
+                        return 1;
+                    }
+                },
+                else => |e| return e,
+            }
+
+            if (first_attempt) {
+                try stderr.writer().print("Waiting for {s}.", .{device_path});
+                first_attempt = false;
+            } else {
+                try stderr.writeAll(".");
+            }
+            std.time.sleep(250 * std.time.ns_per_ms);
+            continue;
+        };
+        try stderr.writeAll("\n");
+        break :blk device;
+    } else {
+        try stderr.writer().print("\nfailed to connect to {s}: {s}\n", .{ device_path, @errorName(last_err) });
+        return 1;
+    };
+    defer device_file.close();
+
+    try stderr.writeAll("Flashing");
+
+    {
+        try uf2_file.seekTo(0);
+
+        var block_num: u64 = 0;
+        while (true) {
+            try stderr.writeAll(".");
+
+            var block: [512]u8 = undefined;
+            const rd_len = try uf2_file.read(&block);
+            if (rd_len == 0)
+                break;
+            if (rd_len != block.len) {
+                try stderr.writer().print("\nFailed to read block {}: Only {} bytes read!\n", .{ block_num, rd_len });
+                return 1;
+            }
+
+            const wr_len = try device_file.write(&block);
+            if (wr_len != block.len) {
+                try stderr.writer().print("\nFailed to write block {}: Only {} bytes written!\n", .{ block_num, wr_len });
+                return 1;
+            }
+
+            block_num += 1;
+        }
+    }
+    try stderr.writeAll("\nDone.\n");
+
+    return 0;
+}
+
+fn autoDetectPico(allocator: std.mem.Allocator) !?[]const u8 {
+    switch (builtin.os.tag) {
+        .linux => {
+            const stdin = std.io.getStdIn();
+            const stderr = std.io.getStdErr();
+
+            const Device = struct {
+                name: []const u8,
+                path: []const u8,
+            };
+
+            var picos = std.ArrayList(Device).init(allocator);
+            defer picos.deinit();
+
+            var base_dir = try std.fs.openIterableDirAbsolute("/sys/block/", .{});
+            defer base_dir.close();
+
+            var iter = base_dir.iterate();
+
+            while (try iter.next()) |entry| {
+                var device_dir = try base_dir.dir.openDir(entry.name, .{});
+                defer device_dir.close();
+
+                const H = struct {
+                    fn isPicoDevice(dir: std.fs.Dir, allo: std.mem.Allocator) !?[]const u8 {
+                        // "/sys/block/*/removable" => "1"
+                        // "/sys/block/*/device/model" => "RP2"
+                        // "/sys/block/*/device/vendor" => "RPI"
+
+                        var buffer: [64]u8 = undefined;
+
+                        const removable = std.mem.trim(u8, try dir.readFile("removable", &buffer), "\r\n\t ");
+                        if (!std.mem.eql(u8, removable, "1"))
+                            return null;
+
+                        const device_model = std.mem.trim(u8, try dir.readFile("device/model", &buffer), "\r\n\t ");
+                        if (!std.mem.eql(u8, device_model, "RP2"))
+                            return null;
+
+                        const device_vendor = std.mem.trim(u8, try dir.readFile("device/vendor", &buffer), "\r\n\t ");
+                        if (!std.mem.eql(u8, device_vendor, "RPI"))
+                            return null;
+
+                        const device_id = std.mem.trim(u8, try dir.readFile("dev", &buffer), "\r\n\t ");
+
+                        return try std.fs.path.join(allo, &.{
+                            "/dev/block", device_id,
+                        });
+                    }
+                };
+
+                const maybe_device = H.isPicoDevice(device_dir, allocator) catch |err| {
+                    if (err != error.FileNotFound and err != error.AccessDenied) {
+                        std.log.err("failed to scan /sys/block/{s}: {s}", .{ entry.name, @errorName(err) });
+                    }
+                    continue;
+                };
+
+                if (maybe_device) |device_path| {
+                    try picos.append(Device{
+                        .name = try allocator.dupe(u8, entry.name),
+                        .path = device_path,
+                    });
+                }
+            }
+
+            if (picos.items.len == 0) {
+                return null;
+            }
+
+            var default_selection: usize = 0;
+
+            try stderr.writer().writeAll("Select your device:\n");
+            for (picos.items, 1..) |pico_dev, index| {
+                try stderr.writer().print("#{d: <2} {s}\n", .{ index, pico_dev.name });
+
+                if (default_selection == 0) {
+                    default_selection = index;
+                }
+            }
+
+            const selection = while (true) {
+                try stderr.writer().print("Select port [{}]: ", .{default_selection});
+
+                var buffer: [64]u8 = undefined;
+                const selection_or_null = try stdin.reader().readUntilDelimiterOrEof(&buffer, '\n');
+
+                const selection_str = std.mem.trim(u8, selection_or_null orelse break default_selection, "\r\n\t ");
+
+                if (selection_str.len == 0)
+                    break default_selection;
+
+                const selection = std.fmt.parseInt(usize, selection_str, 10) catch continue;
+
+                if (selection < 1 or selection > picos.items.len) {
+                    continue;
+                }
+
+                break selection;
+            };
+
+            return picos.items[selection - 1].path;
+        },
+
+        else => {
+            std.log.warn("Device auto-detection not implemented for {s}", .{@tagName(builtin.os.tag)});
+            return null;
+        },
+    }
+}

From 1cef56ad9d5df63af9c45f54a4983b36b0796f7f Mon Sep 17 00:00:00 2001
From: David Sugar 
Date: Mon, 31 Jul 2023 16:20:02 +0200
Subject: [PATCH 184/286] Enable XIP using stage 2 bootloader (#73)

* flash enable xip calls stage two bootloader using inline assembly

* flash erase/program now works in all modes (Debug, ReleaseSmall, ReleaseSafe, ReleaseFast)

* further docs added
---
 examples/flash_program.zig |  2 +-
 rp2040.ld                  |  2 +-
 src/hal/flash.zig          | 69 +++++++++++++++++++++++++++-----------
 3 files changed, 51 insertions(+), 22 deletions(-)

diff --git a/examples/flash_program.zig b/examples/flash_program.zig
index 48754e165..9fd13be06 100644
--- a/examples/flash_program.zig
+++ b/examples/flash_program.zig
@@ -62,7 +62,7 @@ pub fn main() !void {
 
     // Note that a whole number of pages (256 bytes) must be written at a time
     std.log.info("Programming target region...", .{});
-    flash.range_program(flash_target_offset, &data);
+    flash.range_program(flash_target_offset, data[0..]);
     std.log.info("Done. Read back target region:", .{});
     std.log.info("data: {s}", .{flash_target_contents[0..flash.PAGE_SIZE]});
 
diff --git a/rp2040.ld b/rp2040.ld
index cac0892e9..4517b362c 100644
--- a/rp2040.ld
+++ b/rp2040.ld
@@ -43,7 +43,7 @@ SECTIONS
   .data :
   {
      microzig_data_start = .;
-     *(.time_critical*)
+     KEEP(*(.time_critical*))
      *(.data*)
      microzig_data_end = .;
   } > ram0 AT> flash0
diff --git a/src/hal/flash.zig b/src/hal/flash.zig
index 7ce32060d..f10315e42 100644
--- a/src/hal/flash.zig
+++ b/src/hal/flash.zig
@@ -1,3 +1,4 @@
+//! See [rp2040 docs](https://datasheets.raspberrypi.com/rp2040/rp2040-datasheet.pdf), page 136.
 const rom = @import("rom.zig");
 
 pub const Command = enum(u8) {
@@ -12,33 +13,51 @@ pub const BLOCK_SIZE = 65536;
 /// Bus reads to a 16MB memory window start at this address
 pub const XIP_BASE = 0x10000000;
 
+/// Flash code related to the second stage boot loader
 pub const boot2 = struct {
-    /// Size of the second stage bootloader in bytes
-    const BOOT2_SIZE_BYTES = 64;
+    /// Size of the second stage bootloader in words
+    const BOOT2_SIZE_WORDS = 64;
 
     /// Buffer for the second stage bootloader
-    var copyout: [BOOT2_SIZE_BYTES]u32 = undefined;
+    ///
+    /// The only job of the second stage bootloader is to configure the SSI and
+    /// the external flash for the best possible execute-in-place (XIP) performance.
+    /// Until the SSI is correctly configured for the attached flash device, it's not
+    /// possible to access flash via the XIP address window, i.e., we have to copy
+    /// the bootloader into sram before calling `rom.flash_exit_xip`. This is required
+    /// if we want to erase and/or write to flash.
+    ///
+    /// At the end we can then just make a subroutine call to copyout, to configure
+    /// the SSI and flash. The second stage bootloader will return to the calling function
+    /// if a return address is provided in `lr`.
+    var copyout: [BOOT2_SIZE_WORDS]u32 = undefined;
     var copyout_valid: bool = false;
 
     /// Copy the 2nd stage bootloader into memory
-    pub fn flash_init() linksection(".time_critical") void {
+    ///
+    /// This is required by `_range_erase` and `_range_program` so we can later setup
+    /// XIP via the second stage bootloader.
+    pub export fn flash_init() linksection(".time_critical") void {
         if (copyout_valid) return;
         const bootloader = @as([*]u32, @ptrFromInt(XIP_BASE));
         var i: usize = 0;
-        while (i < BOOT2_SIZE_BYTES) : (i += 1) {
+        while (i < BOOT2_SIZE_WORDS) : (i += 1) {
             copyout[i] = bootloader[i];
         }
         copyout_valid = true;
     }
 
-    pub fn flash_enable_xip() linksection(".time_critical") void {
-        // TODO: use the second stage bootloader instead of cmd_xip
-        //const bootloader: []u32 = copyout[1..];
-
-        //const f = @ptrCast(*fn () void, bootloader.ptr);
-        //f();
-
-        rom.flash_enter_cmd_xip()();
+    /// Configure the SSI and the external flash for XIP by calling the second stage
+    /// bootloader that was copied out to `copyout`.
+    pub export fn flash_enable_xip() linksection(".time_critical") void {
+        // The bootloader is in thumb mode
+        asm volatile (
+            \\adds r0, #1
+            \\blx r0
+            :
+            : [copyout] "{r0}" (@intFromPtr(©out)),
+            : "r0", "lr"
+        );
     }
 };
 
@@ -46,12 +65,17 @@ pub const boot2 = struct {
 ///
 /// The offset must be aligned to a 4096-byte sector, and count must
 /// be a multiple of 4096 bytes!
-pub fn range_erase(offset: u32, count: u32) linksection(".time_critical") void {
+pub inline fn range_erase(offset: u32, count: u32) void {
+    // Do not inline `_range_erase`!
+    @call(.never_inline, _range_erase, .{ offset, count });
+}
+
+export fn _range_erase(offset: u32, count: u32) linksection(".time_critical") void {
     // TODO: add sanity checks, e.g., offset + count < flash size
 
-    boot2.flash_init();
+    asm volatile ("" ::: "memory"); // memory barrier
 
-    // TODO: __compiler_memory_barrier
+    boot2.flash_init();
 
     rom.connect_internal_flash()();
     rom.flash_exit_xip()();
@@ -65,16 +89,21 @@ pub fn range_erase(offset: u32, count: u32) linksection(".time_critical") void {
 ///
 /// The offset must be aligned to a 256-byte boundary, and the length of data
 /// must be a multiple of 256!
-pub fn range_program(offset: u32, data: []const u8) linksection(".time_critical") void {
+pub inline fn range_program(offset: u32, data: []const u8) void {
+    // Do not inline `_range_program`!
+    @call(.never_inline, _range_program, .{ offset, data.ptr, data.len });
+}
+
+export fn _range_program(offset: u32, data: [*]const u8, len: usize) linksection(".time_critical") void {
     // TODO: add sanity checks, e.g., offset + count < flash size
 
-    boot2.flash_init();
+    asm volatile ("" ::: "memory"); // memory barrier
 
-    // TODO: __compiler_memory_barrier
+    boot2.flash_init();
 
     rom.connect_internal_flash()();
     rom.flash_exit_xip()();
-    rom.flash_range_program()(offset, data.ptr, data.len);
+    rom.flash_range_program()(offset, data, len);
     rom.flash_flush_cache()();
 
     boot2.flash_enable_xip();

From 695d3dc0e440cd963125b2efb7e95e60dd8bf0f7 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 3 Aug 2023 21:24:21 -0700
Subject: [PATCH 185/286] SourceFile -> LazyFile (#75)

---
 .github/workflows/build.yml | 22 ++++++++++++++++++++++
 build.zig                   |  6 +++---
 build.zig.zon               |  4 ++--
 3 files changed, 27 insertions(+), 5 deletions(-)
 create mode 100644 .github/workflows/build.yml

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
new file mode 100644
index 000000000..220397351
--- /dev/null
+++ b/.github/workflows/build.yml
@@ -0,0 +1,22 @@
+name: Build
+on:
+  push:
+
+jobs:
+  build:
+    runs-on: ${{ matrix.os }}
+    strategy:
+      matrix:
+        os: [
+          linux-latest,
+          windows-latest,
+          macos-latest,
+        ]
+    steps:
+    - uses: actions/checkout@v2
+    - uses: goto-bus-stop/setup-zig@v1.3.0
+      with:
+        version: master
+
+    - name: Build and Unit Test
+      run: zig build test -Doptimize=ReleaseSmall
diff --git a/build.zig b/build.zig
index b9f2803ee..dacb22471 100644
--- a/build.zig
+++ b/build.zig
@@ -2,7 +2,7 @@ const std = @import("std");
 const Builder = std.build.Builder;
 const Pkg = std.build.Pkg;
 const comptimePrint = std.fmt.comptimePrint;
-const FileSource = std.build.FileSource;
+const LazyPath = std.build.LazyPath;
 
 const microzig = @import("microzig");
 
@@ -17,7 +17,7 @@ pub const BuildOptions = struct {
 
 pub const PicoExecutableOptions = struct {
     name: []const u8,
-    source_file: FileSource,
+    source_file: LazyPath,
     optimize: std.builtin.OptimizeMode = .Debug,
 };
 
@@ -52,7 +52,7 @@ pub fn build(b: *Builder) !void {
         },
         .optimize = optimize,
     });
-    pio_tests.addIncludePath("src/hal/pio/assembler");
+    pio_tests.addIncludePath(.{ .path = "src/hal/pio/assembler" });
 
     const test_step = b.step("test", "run unit tests");
     test_step.dependOn(&b.addRunArtifact(pio_tests).step);
diff --git a/build.zig.zon b/build.zig.zon
index d8db2dbc9..28bea9e6a 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -3,8 +3,8 @@
     .version = "0.0.0",
     .dependencies = .{
         .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/9392fe0f7bddde26155c181ab80b70097b49c791.tar.gz",
-            .hash = "1220326148075cd017425e04356329c33c3e794d31a54bdafa46521fcfcc55b422a3",
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/d4a48f65fac24dcfe789d217a9154086b6a011e5.tar.gz",
+            .hash = "1220fd3ad4f6a88f111791cb80de1fc388d0a51114ab376f2bf8351cd176747fa303",
         },
         .args = .{
             .url = "https://github.com/MasterQ32/zig-args/archive/91d1e89fb89a4d01dec7c9aec95b0a324080ebcc.tar.gz",

From 1dbdd0f80ea076cffeced5e9ca6e4322c2e6bc3e Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Thu, 3 Aug 2023 21:47:42 -0700
Subject: [PATCH 186/286] Fix eval branch quota for PIO comparison tests (#76)

---
 .github/workflows/build.yml                | 2 +-
 src/hal/pio/assembler/comparison_tests.zig | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 220397351..6801af685 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -8,7 +8,7 @@ jobs:
     strategy:
       matrix:
         os: [
-          linux-latest,
+          ubuntu-latest,
           windows-latest,
           macos-latest,
         ]
diff --git a/src/hal/pio/assembler/comparison_tests.zig b/src/hal/pio/assembler/comparison_tests.zig
index 5a98c9385..4bad38dcf 100644
--- a/src/hal/pio/assembler/comparison_tests.zig
+++ b/src/hal/pio/assembler/comparison_tests.zig
@@ -53,7 +53,7 @@ test "pio.comparison.addition" {
 }
 
 test "pio.comparison.apa102" {
-    @setEvalBranchQuota(10000);
+    @setEvalBranchQuota(11000);
     try pio_comparison(@embedFile("comparison_tests/apa102.pio"));
 }
 
@@ -153,7 +153,7 @@ test "pio.comparison.st7789_lcd" {
 }
 
 test "pio.comparison.uart_rx" {
-    @setEvalBranchQuota(10000);
+    @setEvalBranchQuota(11000);
     try pio_comparison(@embedFile("comparison_tests/uart_rx.pio"));
 }
 
@@ -163,6 +163,6 @@ test "pio.comparison.uart_tx" {
 }
 
 test "pio.comparison.ws2812" {
-    @setEvalBranchQuota(10000);
+    @setEvalBranchQuota(11000);
     try pio_comparison(@embedFile("comparison_tests/ws2812.pio"));
 }

From 6f201f7f4c4d3223eb1e30658a97c6776c82926a Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Fri, 4 Aug 2023 00:59:05 -0700
Subject: [PATCH 187/286] stabilize on 0.11.0 (#77)

---
 .github/workflows/build.yml | 2 +-
 README.adoc                 | 2 +-
 build.zig.zon               | 4 ++--
 3 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 6801af685..50ac1a489 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -16,7 +16,7 @@ jobs:
     - uses: actions/checkout@v2
     - uses: goto-bus-stop/setup-zig@v1.3.0
       with:
-        version: master
+        version: 0.11.0
 
     - name: Build and Unit Test
       run: zig build test -Doptimize=ReleaseSmall
diff --git a/README.adoc b/README.adoc
index fc0ca7fe8..38c63c607 100644
--- a/README.adoc
+++ b/README.adoc
@@ -4,4 +4,4 @@ HAL and register definitions for the RP2040.
 
 == What version of Zig to use
 
-Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+0.11.0
diff --git a/build.zig.zon b/build.zig.zon
index 28bea9e6a..cfb4ad4ce 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -3,8 +3,8 @@
     .version = "0.0.0",
     .dependencies = .{
         .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/d4a48f65fac24dcfe789d217a9154086b6a011e5.tar.gz",
-            .hash = "1220fd3ad4f6a88f111791cb80de1fc388d0a51114ab376f2bf8351cd176747fa303",
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
+            .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
         },
         .args = .{
             .url = "https://github.com/MasterQ32/zig-args/archive/91d1e89fb89a4d01dec7c9aec95b0a324080ebcc.tar.gz",

From c9e394c58ded14b70bb0dbe15145eda582dc8dfa Mon Sep 17 00:00:00 2001
From: binarycraft007 <107379182+binarycraft007@users.noreply.github.com>
Date: Sun, 13 Aug 2023 06:46:13 +0800
Subject: [PATCH 188/286] fix usage of @ptrCast and other fooToBar stuff, run
 with zig fmt (#18)

---
 src/chips/STM32F103.zig | 134 ++++++++++++++---------------
 src/chips/STM32F303.zig | 128 ++++++++++++++--------------
 src/chips/STM32F407.zig | 182 +++++++++++++++++++--------------------
 src/chips/STM32F429.zig | 184 ++++++++++++++++++++--------------------
 src/hals/STM32F303.zig  |  16 ++--
 src/hals/STM32F407.zig  |  22 ++---
 src/hals/STM32F429.zig  |   2 +-
 7 files changed, 334 insertions(+), 334 deletions(-)

diff --git a/src/chips/STM32F103.zig b/src/chips/STM32F103.zig
index f29fded29..5a174116b 100644
--- a/src/chips/STM32F103.zig
+++ b/src/chips/STM32F103.zig
@@ -112,139 +112,139 @@ pub const devices = struct {
 
         pub const peripherals = struct {
             ///  General purpose timer
-            pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000);
+            pub const TIM2 = @as(*volatile types.TIM2, @ptrFromInt(0x40000000));
             ///  General purpose timer
-            pub const TIM3 = @ptrCast(*volatile types.TIM2, 0x40000400);
+            pub const TIM3 = @as(*volatile types.TIM2, @ptrFromInt(0x40000400));
             ///  General purpose timer
-            pub const TIM4 = @ptrCast(*volatile types.TIM2, 0x40000800);
+            pub const TIM4 = @as(*volatile types.TIM2, @ptrFromInt(0x40000800));
             ///  General purpose timer
-            pub const TIM5 = @ptrCast(*volatile types.TIM2, 0x40000c00);
+            pub const TIM5 = @as(*volatile types.TIM2, @ptrFromInt(0x40000c00));
             ///  Basic timer
-            pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000);
+            pub const TIM6 = @as(*volatile types.TIM6, @ptrFromInt(0x40001000));
             ///  Basic timer
-            pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400);
+            pub const TIM7 = @as(*volatile types.TIM6, @ptrFromInt(0x40001400));
             ///  General purpose timer
-            pub const TIM12 = @ptrCast(*volatile types.TIM9, 0x40001800);
+            pub const TIM12 = @as(*volatile types.TIM9, @ptrFromInt(0x40001800));
             ///  General purpose timer
-            pub const TIM13 = @ptrCast(*volatile types.TIM10, 0x40001c00);
+            pub const TIM13 = @as(*volatile types.TIM10, @ptrFromInt(0x40001c00));
             ///  General purpose timer
-            pub const TIM14 = @ptrCast(*volatile types.TIM10, 0x40002000);
+            pub const TIM14 = @as(*volatile types.TIM10, @ptrFromInt(0x40002000));
             ///  Real time clock
-            pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800);
+            pub const RTC = @as(*volatile types.RTC, @ptrFromInt(0x40002800));
             ///  Window watchdog
-            pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00);
+            pub const WWDG = @as(*volatile types.WWDG, @ptrFromInt(0x40002c00));
             ///  Independent watchdog
-            pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000);
+            pub const IWDG = @as(*volatile types.IWDG, @ptrFromInt(0x40003000));
             ///  Serial peripheral interface
-            pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800);
+            pub const SPI2 = @as(*volatile types.SPI1, @ptrFromInt(0x40003800));
             ///  Serial peripheral interface
-            pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00);
+            pub const SPI3 = @as(*volatile types.SPI1, @ptrFromInt(0x40003c00));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART2 = @ptrCast(*volatile types.USART1, 0x40004400);
+            pub const USART2 = @as(*volatile types.USART1, @ptrFromInt(0x40004400));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART3 = @ptrCast(*volatile types.USART1, 0x40004800);
+            pub const USART3 = @as(*volatile types.USART1, @ptrFromInt(0x40004800));
             ///  Universal asynchronous receiver transmitter
-            pub const UART4 = @ptrCast(*volatile types.UART4, 0x40004c00);
+            pub const UART4 = @as(*volatile types.UART4, @ptrFromInt(0x40004c00));
             ///  Universal asynchronous receiver transmitter
-            pub const UART5 = @ptrCast(*volatile types.UART5, 0x40005000);
+            pub const UART5 = @as(*volatile types.UART5, @ptrFromInt(0x40005000));
             ///  Inter integrated circuit
-            pub const I2C1 = @ptrCast(*volatile types.I2C1, 0x40005400);
+            pub const I2C1 = @as(*volatile types.I2C1, @ptrFromInt(0x40005400));
             ///  Inter integrated circuit
-            pub const I2C2 = @ptrCast(*volatile types.I2C1, 0x40005800);
+            pub const I2C2 = @as(*volatile types.I2C1, @ptrFromInt(0x40005800));
             ///  Universal serial bus full-speed device interface
-            pub const USB = @ptrCast(*volatile types.USB, 0x40005c00);
+            pub const USB = @as(*volatile types.USB, @ptrFromInt(0x40005c00));
             ///  Controller area network
-            pub const CAN1 = @ptrCast(*volatile types.CAN1, 0x40006400);
+            pub const CAN1 = @as(*volatile types.CAN1, @ptrFromInt(0x40006400));
             ///  Controller area network
-            pub const CAN2 = @ptrCast(*volatile types.CAN1, 0x40006800);
+            pub const CAN2 = @as(*volatile types.CAN1, @ptrFromInt(0x40006800));
             ///  Backup registers
-            pub const BKP = @ptrCast(*volatile types.BKP, 0x40006c00);
+            pub const BKP = @as(*volatile types.BKP, @ptrFromInt(0x40006c00));
             ///  Power control
-            pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000);
+            pub const PWR = @as(*volatile types.PWR, @ptrFromInt(0x40007000));
             ///  Digital to analog converter
-            pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400);
+            pub const DAC = @as(*volatile types.DAC, @ptrFromInt(0x40007400));
             ///  Alternate function I/O
-            pub const AFIO = @ptrCast(*volatile types.AFIO, 0x40010000);
+            pub const AFIO = @as(*volatile types.AFIO, @ptrFromInt(0x40010000));
             ///  EXTI
-            pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40010400);
+            pub const EXTI = @as(*volatile types.EXTI, @ptrFromInt(0x40010400));
             ///  General purpose I/O
-            pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x40010800);
+            pub const GPIOA = @as(*volatile types.GPIOA, @ptrFromInt(0x40010800));
             ///  General purpose I/O
-            pub const GPIOB = @ptrCast(*volatile types.GPIOA, 0x40010c00);
+            pub const GPIOB = @as(*volatile types.GPIOA, @ptrFromInt(0x40010c00));
             ///  General purpose I/O
-            pub const GPIOC = @ptrCast(*volatile types.GPIOA, 0x40011000);
+            pub const GPIOC = @as(*volatile types.GPIOA, @ptrFromInt(0x40011000));
             ///  General purpose I/O
-            pub const GPIOD = @ptrCast(*volatile types.GPIOA, 0x40011400);
+            pub const GPIOD = @as(*volatile types.GPIOA, @ptrFromInt(0x40011400));
             ///  General purpose I/O
-            pub const GPIOE = @ptrCast(*volatile types.GPIOA, 0x40011800);
+            pub const GPIOE = @as(*volatile types.GPIOA, @ptrFromInt(0x40011800));
             ///  General purpose I/O
-            pub const GPIOF = @ptrCast(*volatile types.GPIOA, 0x40011c00);
+            pub const GPIOF = @as(*volatile types.GPIOA, @ptrFromInt(0x40011c00));
             ///  General purpose I/O
-            pub const GPIOG = @ptrCast(*volatile types.GPIOA, 0x40012000);
+            pub const GPIOG = @as(*volatile types.GPIOA, @ptrFromInt(0x40012000));
             ///  Analog to digital converter
-            pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x40012400);
+            pub const ADC1 = @as(*volatile types.ADC1, @ptrFromInt(0x40012400));
             ///  Analog to digital converter
-            pub const ADC2 = @ptrCast(*volatile types.ADC2, 0x40012800);
+            pub const ADC2 = @as(*volatile types.ADC2, @ptrFromInt(0x40012800));
             ///  Advanced timer
-            pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40012c00);
+            pub const TIM1 = @as(*volatile types.TIM1, @ptrFromInt(0x40012c00));
             ///  Serial peripheral interface
-            pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000);
+            pub const SPI1 = @as(*volatile types.SPI1, @ptrFromInt(0x40013000));
             ///  Advanced timer
-            pub const TIM8 = @ptrCast(*volatile types.TIM1, 0x40013400);
+            pub const TIM8 = @as(*volatile types.TIM1, @ptrFromInt(0x40013400));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART1 = @ptrCast(*volatile types.USART1, 0x40013800);
+            pub const USART1 = @as(*volatile types.USART1, @ptrFromInt(0x40013800));
             ///  Analog to digital converter
-            pub const ADC3 = @ptrCast(*volatile types.ADC2, 0x40013c00);
+            pub const ADC3 = @as(*volatile types.ADC2, @ptrFromInt(0x40013c00));
             ///  General purpose timer
-            pub const TIM9 = @ptrCast(*volatile types.TIM9, 0x40014c00);
+            pub const TIM9 = @as(*volatile types.TIM9, @ptrFromInt(0x40014c00));
             ///  General purpose timer
-            pub const TIM10 = @ptrCast(*volatile types.TIM10, 0x40015000);
+            pub const TIM10 = @as(*volatile types.TIM10, @ptrFromInt(0x40015000));
             ///  General purpose timer
-            pub const TIM11 = @ptrCast(*volatile types.TIM10, 0x40015400);
+            pub const TIM11 = @as(*volatile types.TIM10, @ptrFromInt(0x40015400));
             ///  Secure digital input/output interface
-            pub const SDIO = @ptrCast(*volatile types.SDIO, 0x40018000);
+            pub const SDIO = @as(*volatile types.SDIO, @ptrFromInt(0x40018000));
             ///  DMA controller
-            pub const DMA1 = @ptrCast(*volatile types.DMA1, 0x40020000);
+            pub const DMA1 = @as(*volatile types.DMA1, @ptrFromInt(0x40020000));
             ///  DMA controller
-            pub const DMA2 = @ptrCast(*volatile types.DMA1, 0x40020400);
+            pub const DMA2 = @as(*volatile types.DMA1, @ptrFromInt(0x40020400));
             ///  Reset and clock control
-            pub const RCC = @ptrCast(*volatile types.RCC, 0x40021000);
+            pub const RCC = @as(*volatile types.RCC, @ptrFromInt(0x40021000));
             ///  FLASH
-            pub const FLASH = @ptrCast(*volatile types.FLASH, 0x40022000);
+            pub const FLASH = @as(*volatile types.FLASH, @ptrFromInt(0x40022000));
             ///  CRC calculation unit
-            pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000);
+            pub const CRC = @as(*volatile types.CRC, @ptrFromInt(0x40023000));
             ///  Ethernet: media access control
-            pub const ETHERNET_MAC = @ptrCast(*volatile types.ETHERNET_MAC, 0x40028000);
+            pub const ETHERNET_MAC = @as(*volatile types.ETHERNET_MAC, @ptrFromInt(0x40028000));
             ///  Ethernet: MAC management counters
-            pub const ETHERNET_MMC = @ptrCast(*volatile types.ETHERNET_MMC, 0x40028100);
+            pub const ETHERNET_MMC = @as(*volatile types.ETHERNET_MMC, @ptrFromInt(0x40028100));
             ///  Ethernet: Precision time protocol
-            pub const ETHERNET_PTP = @ptrCast(*volatile types.ETHERNET_PTP, 0x40028700);
+            pub const ETHERNET_PTP = @as(*volatile types.ETHERNET_PTP, @ptrFromInt(0x40028700));
             ///  Ethernet: DMA controller operation
-            pub const ETHERNET_DMA = @ptrCast(*volatile types.ETHERNET_DMA, 0x40029000);
+            pub const ETHERNET_DMA = @as(*volatile types.ETHERNET_DMA, @ptrFromInt(0x40029000));
             ///  USB on the go full speed
-            pub const OTG_FS_GLOBAL = @ptrCast(*volatile types.OTG_FS_GLOBAL, 0x50000000);
+            pub const OTG_FS_GLOBAL = @as(*volatile types.OTG_FS_GLOBAL, @ptrFromInt(0x50000000));
             ///  USB on the go full speed
-            pub const OTG_FS_HOST = @ptrCast(*volatile types.OTG_FS_HOST, 0x50000400);
+            pub const OTG_FS_HOST = @as(*volatile types.OTG_FS_HOST, @ptrFromInt(0x50000400));
             ///  USB on the go full speed
-            pub const OTG_FS_DEVICE = @ptrCast(*volatile types.OTG_FS_DEVICE, 0x50000800);
+            pub const OTG_FS_DEVICE = @as(*volatile types.OTG_FS_DEVICE, @ptrFromInt(0x50000800));
             ///  USB on the go full speed
-            pub const OTG_FS_PWRCLK = @ptrCast(*volatile types.OTG_FS_PWRCLK, 0x50000e00);
+            pub const OTG_FS_PWRCLK = @as(*volatile types.OTG_FS_PWRCLK, @ptrFromInt(0x50000e00));
             ///  Flexible static memory controller
-            pub const FSMC = @ptrCast(*volatile types.FSMC, 0xa0000000);
+            pub const FSMC = @as(*volatile types.FSMC, @ptrFromInt(0xa0000000));
             ///  System control block ACTLR
-            pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008);
+            pub const SCB_ACTRL = @as(*volatile types.SCB_ACTRL, @ptrFromInt(0xe000e008));
             ///  SysTick timer
-            pub const STK = @ptrCast(*volatile types.STK, 0xe000e010);
+            pub const STK = @as(*volatile types.STK, @ptrFromInt(0xe000e010));
             ///  Nested Vectored Interrupt Controller
-            pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100);
+            pub const NVIC = @as(*volatile types.NVIC, @ptrFromInt(0xe000e100));
             ///  System control block
-            pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00);
+            pub const SCB = @as(*volatile types.SCB, @ptrFromInt(0xe000ed00));
             ///  Memory protection unit
-            pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90);
+            pub const MPU = @as(*volatile types.MPU, @ptrFromInt(0xe000ed90));
             ///  Nested vectored interrupt controller
-            pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00);
+            pub const NVIC_STIR = @as(*volatile types.NVIC_STIR, @ptrFromInt(0xe000ef00));
             ///  Debug support
-            pub const DBG = @ptrCast(*volatile types.DBG, 0xe0042000);
+            pub const DBG = @as(*volatile types.DBG, @ptrFromInt(0xe0042000));
         };
     };
 };
diff --git a/src/chips/STM32F303.zig b/src/chips/STM32F303.zig
index 4bb914c29..f897dc632 100644
--- a/src/chips/STM32F303.zig
+++ b/src/chips/STM32F303.zig
@@ -121,133 +121,133 @@ pub const devices = struct {
 
         pub const peripherals = struct {
             ///  General purpose timer
-            pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000);
+            pub const TIM2 = @as(*volatile types.TIM2, @ptrFromInt(0x40000000));
             ///  General purpose timer
-            pub const TIM3 = @ptrCast(*volatile types.TIM2, 0x40000400);
+            pub const TIM3 = @as(*volatile types.TIM2, @ptrFromInt(0x40000400));
             ///  General purpose timer
-            pub const TIM4 = @ptrCast(*volatile types.TIM2, 0x40000800);
+            pub const TIM4 = @as(*volatile types.TIM2, @ptrFromInt(0x40000800));
             ///  Basic timers
-            pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000);
+            pub const TIM6 = @as(*volatile types.TIM6, @ptrFromInt(0x40001000));
             ///  Basic timers
-            pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400);
+            pub const TIM7 = @as(*volatile types.TIM6, @ptrFromInt(0x40001400));
             ///  Real-time clock
-            pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800);
+            pub const RTC = @as(*volatile types.RTC, @ptrFromInt(0x40002800));
             ///  Window watchdog
-            pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00);
+            pub const WWDG = @as(*volatile types.WWDG, @ptrFromInt(0x40002c00));
             ///  Independent watchdog
-            pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000);
+            pub const IWDG = @as(*volatile types.IWDG, @ptrFromInt(0x40003000));
             ///  Serial peripheral interface/Inter-IC sound
-            pub const I2S2ext = @ptrCast(*volatile types.SPI1, 0x40003400);
+            pub const I2S2ext = @as(*volatile types.SPI1, @ptrFromInt(0x40003400));
             ///  Serial peripheral interface/Inter-IC sound
-            pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800);
+            pub const SPI2 = @as(*volatile types.SPI1, @ptrFromInt(0x40003800));
             ///  Serial peripheral interface/Inter-IC sound
-            pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00);
+            pub const SPI3 = @as(*volatile types.SPI1, @ptrFromInt(0x40003c00));
             ///  Serial peripheral interface/Inter-IC sound
-            pub const I2S3ext = @ptrCast(*volatile types.SPI1, 0x40004000);
+            pub const I2S3ext = @as(*volatile types.SPI1, @ptrFromInt(0x40004000));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART2 = @ptrCast(*volatile types.USART1, 0x40004400);
+            pub const USART2 = @as(*volatile types.USART1, @ptrFromInt(0x40004400));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART3 = @ptrCast(*volatile types.USART1, 0x40004800);
+            pub const USART3 = @as(*volatile types.USART1, @ptrFromInt(0x40004800));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART4 = @ptrCast(*volatile types.USART1, 0x40004c00);
+            pub const UART4 = @as(*volatile types.USART1, @ptrFromInt(0x40004c00));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART5 = @ptrCast(*volatile types.USART1, 0x40005000);
+            pub const UART5 = @as(*volatile types.USART1, @ptrFromInt(0x40005000));
             ///  Inter-integrated circuit
-            pub const I2C1 = @ptrCast(*volatile types.I2C1, 0x40005400);
+            pub const I2C1 = @as(*volatile types.I2C1, @ptrFromInt(0x40005400));
             ///  Inter-integrated circuit
-            pub const I2C2 = @ptrCast(*volatile types.I2C1, 0x40005800);
+            pub const I2C2 = @as(*volatile types.I2C1, @ptrFromInt(0x40005800));
             ///  Universal serial bus full-speed device interface
-            pub const USB_FS = @ptrCast(*volatile types.USB_FS, 0x40005c00);
+            pub const USB_FS = @as(*volatile types.USB_FS, @ptrFromInt(0x40005c00));
             ///  Controller area network
-            pub const CAN = @ptrCast(*volatile types.CAN, 0x40006400);
+            pub const CAN = @as(*volatile types.CAN, @ptrFromInt(0x40006400));
             ///  Power control
-            pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000);
+            pub const PWR = @as(*volatile types.PWR, @ptrFromInt(0x40007000));
             ///  Digital-to-analog converter
-            pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400);
+            pub const DAC = @as(*volatile types.DAC, @ptrFromInt(0x40007400));
             ///  Inter-integrated circuit
-            pub const I2C3 = @ptrCast(*volatile types.I2C1, 0x40007800);
+            pub const I2C3 = @as(*volatile types.I2C1, @ptrFromInt(0x40007800));
             ///  System configuration controller _Comparator and Operational amplifier
-            pub const SYSCFG_COMP_OPAMP = @ptrCast(*volatile types.SYSCFG_COMP_OPAMP, 0x40010000);
+            pub const SYSCFG_COMP_OPAMP = @as(*volatile types.SYSCFG_COMP_OPAMP, @ptrFromInt(0x40010000));
             ///  External interrupt/event controller
-            pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40010400);
+            pub const EXTI = @as(*volatile types.EXTI, @ptrFromInt(0x40010400));
             ///  Advanced timer
-            pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40012c00);
+            pub const TIM1 = @as(*volatile types.TIM1, @ptrFromInt(0x40012c00));
             ///  Serial peripheral interface/Inter-IC sound
-            pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000);
+            pub const SPI1 = @as(*volatile types.SPI1, @ptrFromInt(0x40013000));
             ///  Advanced-timers
-            pub const TIM8 = @ptrCast(*volatile types.TIM8, 0x40013400);
+            pub const TIM8 = @as(*volatile types.TIM8, @ptrFromInt(0x40013400));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART1 = @ptrCast(*volatile types.USART1, 0x40013800);
+            pub const USART1 = @as(*volatile types.USART1, @ptrFromInt(0x40013800));
             ///  Serial peripheral interface/Inter-IC sound
-            pub const SPI4 = @ptrCast(*volatile types.SPI1, 0x40013c00);
+            pub const SPI4 = @as(*volatile types.SPI1, @ptrFromInt(0x40013c00));
             ///  General purpose timers
-            pub const TIM15 = @ptrCast(*volatile types.TIM15, 0x40014000);
+            pub const TIM15 = @as(*volatile types.TIM15, @ptrFromInt(0x40014000));
             ///  General-purpose-timers
-            pub const TIM16 = @ptrCast(*volatile types.TIM16, 0x40014400);
+            pub const TIM16 = @as(*volatile types.TIM16, @ptrFromInt(0x40014400));
             ///  General purpose timer
-            pub const TIM17 = @ptrCast(*volatile types.TIM17, 0x40014800);
+            pub const TIM17 = @as(*volatile types.TIM17, @ptrFromInt(0x40014800));
             ///  Advanced timer
-            pub const TIM20 = @ptrCast(*volatile types.TIM1, 0x40015000);
+            pub const TIM20 = @as(*volatile types.TIM1, @ptrFromInt(0x40015000));
             ///  DMA controller 1
-            pub const DMA1 = @ptrCast(*volatile types.DMA1, 0x40020000);
+            pub const DMA1 = @as(*volatile types.DMA1, @ptrFromInt(0x40020000));
             ///  DMA controller 1
-            pub const DMA2 = @ptrCast(*volatile types.DMA1, 0x40020400);
+            pub const DMA2 = @as(*volatile types.DMA1, @ptrFromInt(0x40020400));
             ///  Reset and clock control
-            pub const RCC = @ptrCast(*volatile types.RCC, 0x40021000);
+            pub const RCC = @as(*volatile types.RCC, @ptrFromInt(0x40021000));
             ///  Flash
-            pub const Flash = @ptrCast(*volatile types.Flash, 0x40022000);
+            pub const Flash = @as(*volatile types.Flash, @ptrFromInt(0x40022000));
             ///  cyclic redundancy check calculation unit
-            pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000);
+            pub const CRC = @as(*volatile types.CRC, @ptrFromInt(0x40023000));
             ///  Touch sensing controller
-            pub const TSC = @ptrCast(*volatile types.TSC, 0x40024000);
+            pub const TSC = @as(*volatile types.TSC, @ptrFromInt(0x40024000));
             ///  General-purpose I/Os
-            pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x48000000);
+            pub const GPIOA = @as(*volatile types.GPIOA, @ptrFromInt(0x48000000));
             ///  General-purpose I/Os
-            pub const GPIOB = @ptrCast(*volatile types.GPIOB, 0x48000400);
+            pub const GPIOB = @as(*volatile types.GPIOB, @ptrFromInt(0x48000400));
             ///  General-purpose I/Os
-            pub const GPIOC = @ptrCast(*volatile types.GPIOB, 0x48000800);
+            pub const GPIOC = @as(*volatile types.GPIOB, @ptrFromInt(0x48000800));
             ///  General-purpose I/Os
-            pub const GPIOD = @ptrCast(*volatile types.GPIOB, 0x48000c00);
+            pub const GPIOD = @as(*volatile types.GPIOB, @ptrFromInt(0x48000c00));
             ///  General-purpose I/Os
-            pub const GPIOE = @ptrCast(*volatile types.GPIOB, 0x48001000);
+            pub const GPIOE = @as(*volatile types.GPIOB, @ptrFromInt(0x48001000));
             ///  General-purpose I/Os
-            pub const GPIOF = @ptrCast(*volatile types.GPIOB, 0x48001400);
+            pub const GPIOF = @as(*volatile types.GPIOB, @ptrFromInt(0x48001400));
             ///  General-purpose I/Os
-            pub const GPIOG = @ptrCast(*volatile types.GPIOB, 0x48001800);
+            pub const GPIOG = @as(*volatile types.GPIOB, @ptrFromInt(0x48001800));
             ///  General-purpose I/Os
-            pub const GPIOH = @ptrCast(*volatile types.GPIOB, 0x48001c00);
+            pub const GPIOH = @as(*volatile types.GPIOB, @ptrFromInt(0x48001c00));
             ///  Analog-to-Digital Converter
-            pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x50000000);
+            pub const ADC1 = @as(*volatile types.ADC1, @ptrFromInt(0x50000000));
             ///  Analog-to-Digital Converter
-            pub const ADC2 = @ptrCast(*volatile types.ADC1, 0x50000100);
+            pub const ADC2 = @as(*volatile types.ADC1, @ptrFromInt(0x50000100));
             ///  Analog-to-Digital Converter
-            pub const ADC1_2 = @ptrCast(*volatile types.ADC1_2, 0x50000300);
+            pub const ADC1_2 = @as(*volatile types.ADC1_2, @ptrFromInt(0x50000300));
             ///  Analog-to-Digital Converter
-            pub const ADC3 = @ptrCast(*volatile types.ADC1, 0x50000400);
+            pub const ADC3 = @as(*volatile types.ADC1, @ptrFromInt(0x50000400));
             ///  Analog-to-Digital Converter
-            pub const ADC4 = @ptrCast(*volatile types.ADC1, 0x50000500);
+            pub const ADC4 = @as(*volatile types.ADC1, @ptrFromInt(0x50000500));
             ///  Analog-to-Digital Converter
-            pub const ADC3_4 = @ptrCast(*volatile types.ADC1_2, 0x50000700);
+            pub const ADC3_4 = @as(*volatile types.ADC1_2, @ptrFromInt(0x50000700));
             ///  Flexible memory controller
-            pub const FMC = @ptrCast(*volatile types.FMC, 0xa0000400);
+            pub const FMC = @as(*volatile types.FMC, @ptrFromInt(0xa0000400));
             ///  System control block ACTLR
-            pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008);
+            pub const SCB_ACTRL = @as(*volatile types.SCB_ACTRL, @ptrFromInt(0xe000e008));
             ///  SysTick timer
-            pub const STK = @ptrCast(*volatile types.STK, 0xe000e010);
+            pub const STK = @as(*volatile types.STK, @ptrFromInt(0xe000e010));
             ///  Nested Vectored Interrupt Controller
-            pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100);
+            pub const NVIC = @as(*volatile types.NVIC, @ptrFromInt(0xe000e100));
             ///  System control block
-            pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00);
+            pub const SCB = @as(*volatile types.SCB, @ptrFromInt(0xe000ed00));
             ///  Floating point unit CPACR
-            pub const FPU_CPACR = @ptrCast(*volatile types.FPU_CPACR, 0xe000ed88);
+            pub const FPU_CPACR = @as(*volatile types.FPU_CPACR, @ptrFromInt(0xe000ed88));
             ///  Memory protection unit
-            pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90);
+            pub const MPU = @as(*volatile types.MPU, @ptrFromInt(0xe000ed90));
             ///  Nested vectored interrupt controller
-            pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00);
+            pub const NVIC_STIR = @as(*volatile types.NVIC_STIR, @ptrFromInt(0xe000ef00));
             ///  Floting point unit
-            pub const FPU = @ptrCast(*volatile types.FPU, 0xe000ef34);
+            pub const FPU = @as(*volatile types.FPU, @ptrFromInt(0xe000ef34));
             ///  Debug support
-            pub const DBGMCU = @ptrCast(*volatile types.DBGMCU, 0xe0042000);
+            pub const DBGMCU = @as(*volatile types.DBGMCU, @ptrFromInt(0xe0042000));
         };
     };
 };
diff --git a/src/chips/STM32F407.zig b/src/chips/STM32F407.zig
index bf7ea6912..c0d311a27 100644
--- a/src/chips/STM32F407.zig
+++ b/src/chips/STM32F407.zig
@@ -138,187 +138,187 @@ pub const devices = struct {
 
         pub const peripherals = struct {
             ///  General purpose timers
-            pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000);
+            pub const TIM2 = @as(*volatile types.TIM2, @ptrFromInt(0x40000000));
             ///  General purpose timers
-            pub const TIM3 = @ptrCast(*volatile types.TIM3, 0x40000400);
+            pub const TIM3 = @as(*volatile types.TIM3, @ptrFromInt(0x40000400));
             ///  General purpose timers
-            pub const TIM4 = @ptrCast(*volatile types.TIM3, 0x40000800);
+            pub const TIM4 = @as(*volatile types.TIM3, @ptrFromInt(0x40000800));
             ///  General-purpose-timers
-            pub const TIM5 = @ptrCast(*volatile types.TIM5, 0x40000c00);
+            pub const TIM5 = @as(*volatile types.TIM5, @ptrFromInt(0x40000c00));
             ///  Basic timers
-            pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000);
+            pub const TIM6 = @as(*volatile types.TIM6, @ptrFromInt(0x40001000));
             ///  Basic timers
-            pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400);
+            pub const TIM7 = @as(*volatile types.TIM6, @ptrFromInt(0x40001400));
             ///  General purpose timers
-            pub const TIM12 = @ptrCast(*volatile types.TIM9, 0x40001800);
+            pub const TIM12 = @as(*volatile types.TIM9, @ptrFromInt(0x40001800));
             ///  General-purpose-timers
-            pub const TIM13 = @ptrCast(*volatile types.TIM10, 0x40001c00);
+            pub const TIM13 = @as(*volatile types.TIM10, @ptrFromInt(0x40001c00));
             ///  General-purpose-timers
-            pub const TIM14 = @ptrCast(*volatile types.TIM10, 0x40002000);
+            pub const TIM14 = @as(*volatile types.TIM10, @ptrFromInt(0x40002000));
             ///  Real-time clock
-            pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800);
+            pub const RTC = @as(*volatile types.RTC, @ptrFromInt(0x40002800));
             ///  Window watchdog
-            pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00);
+            pub const WWDG = @as(*volatile types.WWDG, @ptrFromInt(0x40002c00));
             ///  Independent watchdog
-            pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000);
+            pub const IWDG = @as(*volatile types.IWDG, @ptrFromInt(0x40003000));
             ///  Serial peripheral interface
-            pub const I2S2ext = @ptrCast(*volatile types.SPI1, 0x40003400);
+            pub const I2S2ext = @as(*volatile types.SPI1, @ptrFromInt(0x40003400));
             ///  Serial peripheral interface
-            pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800);
+            pub const SPI2 = @as(*volatile types.SPI1, @ptrFromInt(0x40003800));
             ///  Serial peripheral interface
-            pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00);
+            pub const SPI3 = @as(*volatile types.SPI1, @ptrFromInt(0x40003c00));
             ///  Serial peripheral interface
-            pub const I2S3ext = @ptrCast(*volatile types.SPI1, 0x40004000);
+            pub const I2S3ext = @as(*volatile types.SPI1, @ptrFromInt(0x40004000));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART2 = @ptrCast(*volatile types.USART6, 0x40004400);
+            pub const USART2 = @as(*volatile types.USART6, @ptrFromInt(0x40004400));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART3 = @ptrCast(*volatile types.USART6, 0x40004800);
+            pub const USART3 = @as(*volatile types.USART6, @ptrFromInt(0x40004800));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART4 = @ptrCast(*volatile types.UART4, 0x40004c00);
+            pub const UART4 = @as(*volatile types.UART4, @ptrFromInt(0x40004c00));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART5 = @ptrCast(*volatile types.UART4, 0x40005000);
+            pub const UART5 = @as(*volatile types.UART4, @ptrFromInt(0x40005000));
             ///  Inter-integrated circuit
-            pub const I2C1 = @ptrCast(*volatile types.I2C3, 0x40005400);
+            pub const I2C1 = @as(*volatile types.I2C3, @ptrFromInt(0x40005400));
             ///  Inter-integrated circuit
-            pub const I2C2 = @ptrCast(*volatile types.I2C3, 0x40005800);
+            pub const I2C2 = @as(*volatile types.I2C3, @ptrFromInt(0x40005800));
             ///  Inter-integrated circuit
-            pub const I2C3 = @ptrCast(*volatile types.I2C3, 0x40005c00);
+            pub const I2C3 = @as(*volatile types.I2C3, @ptrFromInt(0x40005c00));
             ///  Controller area network
-            pub const CAN1 = @ptrCast(*volatile types.CAN1, 0x40006400);
+            pub const CAN1 = @as(*volatile types.CAN1, @ptrFromInt(0x40006400));
             ///  Controller area network
-            pub const CAN2 = @ptrCast(*volatile types.CAN1, 0x40006800);
+            pub const CAN2 = @as(*volatile types.CAN1, @ptrFromInt(0x40006800));
             ///  Power control
-            pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000);
+            pub const PWR = @as(*volatile types.PWR, @ptrFromInt(0x40007000));
             ///  Digital-to-analog converter
-            pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400);
+            pub const DAC = @as(*volatile types.DAC, @ptrFromInt(0x40007400));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART7 = @ptrCast(*volatile types.UART4, 0x40007800);
+            pub const UART7 = @as(*volatile types.UART4, @ptrFromInt(0x40007800));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART8 = @ptrCast(*volatile types.UART4, 0x40007c00);
+            pub const UART8 = @as(*volatile types.UART4, @ptrFromInt(0x40007c00));
             ///  Advanced-timers
-            pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40010000);
+            pub const TIM1 = @as(*volatile types.TIM1, @ptrFromInt(0x40010000));
             ///  Advanced-timers
-            pub const TIM8 = @ptrCast(*volatile types.TIM1, 0x40010400);
+            pub const TIM8 = @as(*volatile types.TIM1, @ptrFromInt(0x40010400));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART1 = @ptrCast(*volatile types.USART6, 0x40011000);
+            pub const USART1 = @as(*volatile types.USART6, @ptrFromInt(0x40011000));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART6 = @ptrCast(*volatile types.USART6, 0x40011400);
+            pub const USART6 = @as(*volatile types.USART6, @ptrFromInt(0x40011400));
             ///  Analog-to-digital converter
-            pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x40012000);
+            pub const ADC1 = @as(*volatile types.ADC1, @ptrFromInt(0x40012000));
             ///  Analog-to-digital converter
-            pub const ADC2 = @ptrCast(*volatile types.ADC1, 0x40012100);
+            pub const ADC2 = @as(*volatile types.ADC1, @ptrFromInt(0x40012100));
             ///  Analog-to-digital converter
-            pub const ADC3 = @ptrCast(*volatile types.ADC1, 0x40012200);
+            pub const ADC3 = @as(*volatile types.ADC1, @ptrFromInt(0x40012200));
             ///  Common ADC registers
-            pub const C_ADC = @ptrCast(*volatile types.C_ADC, 0x40012300);
+            pub const C_ADC = @as(*volatile types.C_ADC, @ptrFromInt(0x40012300));
             ///  Secure digital input/output interface
-            pub const SDIO = @ptrCast(*volatile types.SDIO, 0x40012c00);
+            pub const SDIO = @as(*volatile types.SDIO, @ptrFromInt(0x40012c00));
             ///  Serial peripheral interface
-            pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000);
+            pub const SPI1 = @as(*volatile types.SPI1, @ptrFromInt(0x40013000));
             ///  Serial peripheral interface
-            pub const SPI4 = @ptrCast(*volatile types.SPI1, 0x40013400);
+            pub const SPI4 = @as(*volatile types.SPI1, @ptrFromInt(0x40013400));
             ///  System configuration controller
-            pub const SYSCFG = @ptrCast(*volatile types.SYSCFG, 0x40013800);
+            pub const SYSCFG = @as(*volatile types.SYSCFG, @ptrFromInt(0x40013800));
             ///  External interrupt/event controller
-            pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40013c00);
+            pub const EXTI = @as(*volatile types.EXTI, @ptrFromInt(0x40013c00));
             ///  General purpose timers
-            pub const TIM9 = @ptrCast(*volatile types.TIM9, 0x40014000);
+            pub const TIM9 = @as(*volatile types.TIM9, @ptrFromInt(0x40014000));
             ///  General-purpose-timers
-            pub const TIM10 = @ptrCast(*volatile types.TIM10, 0x40014400);
+            pub const TIM10 = @as(*volatile types.TIM10, @ptrFromInt(0x40014400));
             ///  General-purpose-timers
-            pub const TIM11 = @ptrCast(*volatile types.TIM11, 0x40014800);
+            pub const TIM11 = @as(*volatile types.TIM11, @ptrFromInt(0x40014800));
             ///  Serial peripheral interface
-            pub const SPI5 = @ptrCast(*volatile types.SPI1, 0x40015000);
+            pub const SPI5 = @as(*volatile types.SPI1, @ptrFromInt(0x40015000));
             ///  Serial peripheral interface
-            pub const SPI6 = @ptrCast(*volatile types.SPI1, 0x40015400);
+            pub const SPI6 = @as(*volatile types.SPI1, @ptrFromInt(0x40015400));
             ///  Serial audio interface
-            pub const SAI1 = @ptrCast(*volatile types.SAI1, 0x40015800);
+            pub const SAI1 = @as(*volatile types.SAI1, @ptrFromInt(0x40015800));
             ///  LCD-TFT Controller
-            pub const LTDC = @ptrCast(*volatile types.LTDC, 0x40016800);
+            pub const LTDC = @as(*volatile types.LTDC, @ptrFromInt(0x40016800));
             ///  General-purpose I/Os
-            pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x40020000);
+            pub const GPIOA = @as(*volatile types.GPIOA, @ptrFromInt(0x40020000));
             ///  General-purpose I/Os
-            pub const GPIOB = @ptrCast(*volatile types.GPIOB, 0x40020400);
+            pub const GPIOB = @as(*volatile types.GPIOB, @ptrFromInt(0x40020400));
             ///  General-purpose I/Os
-            pub const GPIOC = @ptrCast(*volatile types.GPIOI, 0x40020800);
+            pub const GPIOC = @as(*volatile types.GPIOI, @ptrFromInt(0x40020800));
             ///  General-purpose I/Os
-            pub const GPIOD = @ptrCast(*volatile types.GPIOI, 0x40020c00);
+            pub const GPIOD = @as(*volatile types.GPIOI, @ptrFromInt(0x40020c00));
             ///  General-purpose I/Os
-            pub const GPIOE = @ptrCast(*volatile types.GPIOI, 0x40021000);
+            pub const GPIOE = @as(*volatile types.GPIOI, @ptrFromInt(0x40021000));
             ///  General-purpose I/Os
-            pub const GPIOF = @ptrCast(*volatile types.GPIOI, 0x40021400);
+            pub const GPIOF = @as(*volatile types.GPIOI, @ptrFromInt(0x40021400));
             ///  General-purpose I/Os
-            pub const GPIOG = @ptrCast(*volatile types.GPIOI, 0x40021800);
+            pub const GPIOG = @as(*volatile types.GPIOI, @ptrFromInt(0x40021800));
             ///  General-purpose I/Os
-            pub const GPIOH = @ptrCast(*volatile types.GPIOI, 0x40021c00);
+            pub const GPIOH = @as(*volatile types.GPIOI, @ptrFromInt(0x40021c00));
             ///  General-purpose I/Os
-            pub const GPIOI = @ptrCast(*volatile types.GPIOI, 0x40022000);
+            pub const GPIOI = @as(*volatile types.GPIOI, @ptrFromInt(0x40022000));
             ///  General-purpose I/Os
-            pub const GPIOJ = @ptrCast(*volatile types.GPIOI, 0x40022400);
+            pub const GPIOJ = @as(*volatile types.GPIOI, @ptrFromInt(0x40022400));
             ///  General-purpose I/Os
-            pub const GPIOK = @ptrCast(*volatile types.GPIOI, 0x40022800);
+            pub const GPIOK = @as(*volatile types.GPIOI, @ptrFromInt(0x40022800));
             ///  Cryptographic processor
-            pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000);
+            pub const CRC = @as(*volatile types.CRC, @ptrFromInt(0x40023000));
             ///  Reset and clock control
-            pub const RCC = @ptrCast(*volatile types.RCC, 0x40023800);
+            pub const RCC = @as(*volatile types.RCC, @ptrFromInt(0x40023800));
             ///  FLASH
-            pub const FLASH = @ptrCast(*volatile types.FLASH, 0x40023c00);
+            pub const FLASH = @as(*volatile types.FLASH, @ptrFromInt(0x40023c00));
             ///  DMA controller
-            pub const DMA1 = @ptrCast(*volatile types.DMA2, 0x40026000);
+            pub const DMA1 = @as(*volatile types.DMA2, @ptrFromInt(0x40026000));
             ///  DMA controller
-            pub const DMA2 = @ptrCast(*volatile types.DMA2, 0x40026400);
+            pub const DMA2 = @as(*volatile types.DMA2, @ptrFromInt(0x40026400));
             ///  Ethernet: media access control (MAC)
-            pub const Ethernet_MAC = @ptrCast(*volatile types.Ethernet_MAC, 0x40028000);
+            pub const Ethernet_MAC = @as(*volatile types.Ethernet_MAC, @ptrFromInt(0x40028000));
             ///  Ethernet: MAC management counters
-            pub const Ethernet_MMC = @ptrCast(*volatile types.Ethernet_MMC, 0x40028100);
+            pub const Ethernet_MMC = @as(*volatile types.Ethernet_MMC, @ptrFromInt(0x40028100));
             ///  Ethernet: Precision time protocol
-            pub const Ethernet_PTP = @ptrCast(*volatile types.Ethernet_PTP, 0x40028700);
+            pub const Ethernet_PTP = @as(*volatile types.Ethernet_PTP, @ptrFromInt(0x40028700));
             ///  Ethernet: DMA controller operation
-            pub const Ethernet_DMA = @ptrCast(*volatile types.Ethernet_DMA, 0x40029000);
+            pub const Ethernet_DMA = @as(*volatile types.Ethernet_DMA, @ptrFromInt(0x40029000));
             ///  USB on the go high speed
-            pub const OTG_HS_GLOBAL = @ptrCast(*volatile types.OTG_HS_GLOBAL, 0x40040000);
+            pub const OTG_HS_GLOBAL = @as(*volatile types.OTG_HS_GLOBAL, @ptrFromInt(0x40040000));
             ///  USB on the go high speed
-            pub const OTG_HS_HOST = @ptrCast(*volatile types.OTG_HS_HOST, 0x40040400);
+            pub const OTG_HS_HOST = @as(*volatile types.OTG_HS_HOST, @ptrFromInt(0x40040400));
             ///  USB on the go high speed
-            pub const OTG_HS_DEVICE = @ptrCast(*volatile types.OTG_HS_DEVICE, 0x40040800);
+            pub const OTG_HS_DEVICE = @as(*volatile types.OTG_HS_DEVICE, @ptrFromInt(0x40040800));
             ///  USB on the go high speed
-            pub const OTG_HS_PWRCLK = @ptrCast(*volatile types.OTG_HS_PWRCLK, 0x40040e00);
+            pub const OTG_HS_PWRCLK = @as(*volatile types.OTG_HS_PWRCLK, @ptrFromInt(0x40040e00));
             ///  USB on the go full speed
-            pub const OTG_FS_GLOBAL = @ptrCast(*volatile types.OTG_FS_GLOBAL, 0x50000000);
+            pub const OTG_FS_GLOBAL = @as(*volatile types.OTG_FS_GLOBAL, @ptrFromInt(0x50000000));
             ///  USB on the go full speed
-            pub const OTG_FS_HOST = @ptrCast(*volatile types.OTG_FS_HOST, 0x50000400);
+            pub const OTG_FS_HOST = @as(*volatile types.OTG_FS_HOST, @ptrFromInt(0x50000400));
             ///  USB on the go full speed
-            pub const OTG_FS_DEVICE = @ptrCast(*volatile types.OTG_FS_DEVICE, 0x50000800);
+            pub const OTG_FS_DEVICE = @as(*volatile types.OTG_FS_DEVICE, @ptrFromInt(0x50000800));
             ///  USB on the go full speed
-            pub const OTG_FS_PWRCLK = @ptrCast(*volatile types.OTG_FS_PWRCLK, 0x50000e00);
+            pub const OTG_FS_PWRCLK = @as(*volatile types.OTG_FS_PWRCLK, @ptrFromInt(0x50000e00));
             ///  Digital camera interface
-            pub const DCMI = @ptrCast(*volatile types.DCMI, 0x50050000);
+            pub const DCMI = @as(*volatile types.DCMI, @ptrFromInt(0x50050000));
             ///  Cryptographic processor
-            pub const CRYP = @ptrCast(*volatile types.CRYP, 0x50060000);
+            pub const CRYP = @as(*volatile types.CRYP, @ptrFromInt(0x50060000));
             ///  Hash processor
-            pub const HASH = @ptrCast(*volatile types.HASH, 0x50060400);
+            pub const HASH = @as(*volatile types.HASH, @ptrFromInt(0x50060400));
             ///  Random number generator
-            pub const RNG = @ptrCast(*volatile types.RNG, 0x50060800);
+            pub const RNG = @as(*volatile types.RNG, @ptrFromInt(0x50060800));
             ///  Flexible static memory controller
-            pub const FSMC = @ptrCast(*volatile types.FSMC, 0xa0000000);
+            pub const FSMC = @as(*volatile types.FSMC, @ptrFromInt(0xa0000000));
             ///  System control block ACTLR
-            pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008);
+            pub const SCB_ACTRL = @as(*volatile types.SCB_ACTRL, @ptrFromInt(0xe000e008));
             ///  SysTick timer
-            pub const STK = @ptrCast(*volatile types.STK, 0xe000e010);
+            pub const STK = @as(*volatile types.STK, @ptrFromInt(0xe000e010));
             ///  Nested Vectored Interrupt Controller
-            pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100);
+            pub const NVIC = @as(*volatile types.NVIC, @ptrFromInt(0xe000e100));
             ///  System control block
-            pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00);
+            pub const SCB = @as(*volatile types.SCB, @ptrFromInt(0xe000ed00));
             ///  Floating point unit CPACR
-            pub const FPU_CPACR = @ptrCast(*volatile types.FPU_CPACR, 0xe000ed88);
+            pub const FPU_CPACR = @as(*volatile types.FPU_CPACR, @ptrFromInt(0xe000ed88));
             ///  Memory protection unit
-            pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90);
+            pub const MPU = @as(*volatile types.MPU, @ptrFromInt(0xe000ed90));
             ///  Nested vectored interrupt controller
-            pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00);
+            pub const NVIC_STIR = @as(*volatile types.NVIC_STIR, @ptrFromInt(0xe000ef00));
             ///  Floting point unit
-            pub const FPU = @ptrCast(*volatile types.FPU, 0xe000ef34);
+            pub const FPU = @as(*volatile types.FPU, @ptrFromInt(0xe000ef34));
             ///  Debug support
-            pub const DBG = @ptrCast(*volatile types.DBG, 0xe0042000);
+            pub const DBG = @as(*volatile types.DBG, @ptrFromInt(0xe0042000));
         };
     };
 };
diff --git a/src/chips/STM32F429.zig b/src/chips/STM32F429.zig
index 73b943659..8638044a2 100644
--- a/src/chips/STM32F429.zig
+++ b/src/chips/STM32F429.zig
@@ -149,189 +149,189 @@ pub const devices = struct {
 
         pub const peripherals = struct {
             ///  General purpose timers
-            pub const TIM2 = @ptrCast(*volatile types.TIM2, 0x40000000);
+            pub const TIM2 = @as(*volatile types.TIM2, @ptrFromInt(0x40000000));
             ///  General purpose timers
-            pub const TIM3 = @ptrCast(*volatile types.TIM3, 0x40000400);
+            pub const TIM3 = @as(*volatile types.TIM3, @ptrFromInt(0x40000400));
             ///  General purpose timers
-            pub const TIM4 = @ptrCast(*volatile types.TIM3, 0x40000800);
+            pub const TIM4 = @as(*volatile types.TIM3, @ptrFromInt(0x40000800));
             ///  General-purpose-timers
-            pub const TIM5 = @ptrCast(*volatile types.TIM5, 0x40000c00);
+            pub const TIM5 = @as(*volatile types.TIM5, @ptrFromInt(0x40000c00));
             ///  Basic timers
-            pub const TIM6 = @ptrCast(*volatile types.TIM6, 0x40001000);
+            pub const TIM6 = @as(*volatile types.TIM6, @ptrFromInt(0x40001000));
             ///  Basic timers
-            pub const TIM7 = @ptrCast(*volatile types.TIM6, 0x40001400);
+            pub const TIM7 = @as(*volatile types.TIM6, @ptrFromInt(0x40001400));
             ///  General purpose timers
-            pub const TIM12 = @ptrCast(*volatile types.TIM9, 0x40001800);
+            pub const TIM12 = @as(*volatile types.TIM9, @ptrFromInt(0x40001800));
             ///  General-purpose-timers
-            pub const TIM13 = @ptrCast(*volatile types.TIM10, 0x40001c00);
+            pub const TIM13 = @as(*volatile types.TIM10, @ptrFromInt(0x40001c00));
             ///  General-purpose-timers
-            pub const TIM14 = @ptrCast(*volatile types.TIM10, 0x40002000);
+            pub const TIM14 = @as(*volatile types.TIM10, @ptrFromInt(0x40002000));
             ///  Real-time clock
-            pub const RTC = @ptrCast(*volatile types.RTC, 0x40002800);
+            pub const RTC = @as(*volatile types.RTC, @ptrFromInt(0x40002800));
             ///  Window watchdog
-            pub const WWDG = @ptrCast(*volatile types.WWDG, 0x40002c00);
+            pub const WWDG = @as(*volatile types.WWDG, @ptrFromInt(0x40002c00));
             ///  Independent watchdog
-            pub const IWDG = @ptrCast(*volatile types.IWDG, 0x40003000);
+            pub const IWDG = @as(*volatile types.IWDG, @ptrFromInt(0x40003000));
             ///  Serial peripheral interface
-            pub const I2S2ext = @ptrCast(*volatile types.SPI1, 0x40003400);
+            pub const I2S2ext = @as(*volatile types.SPI1, @ptrFromInt(0x40003400));
             ///  Serial peripheral interface
-            pub const SPI2 = @ptrCast(*volatile types.SPI1, 0x40003800);
+            pub const SPI2 = @as(*volatile types.SPI1, @ptrFromInt(0x40003800));
             ///  Serial peripheral interface
-            pub const SPI3 = @ptrCast(*volatile types.SPI1, 0x40003c00);
+            pub const SPI3 = @as(*volatile types.SPI1, @ptrFromInt(0x40003c00));
             ///  Serial peripheral interface
-            pub const I2S3ext = @ptrCast(*volatile types.SPI1, 0x40004000);
+            pub const I2S3ext = @as(*volatile types.SPI1, @ptrFromInt(0x40004000));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART2 = @ptrCast(*volatile types.USART6, 0x40004400);
+            pub const USART2 = @as(*volatile types.USART6, @ptrFromInt(0x40004400));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART3 = @ptrCast(*volatile types.USART6, 0x40004800);
+            pub const USART3 = @as(*volatile types.USART6, @ptrFromInt(0x40004800));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART4 = @ptrCast(*volatile types.UART4, 0x40004c00);
+            pub const UART4 = @as(*volatile types.UART4, @ptrFromInt(0x40004c00));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART5 = @ptrCast(*volatile types.UART4, 0x40005000);
+            pub const UART5 = @as(*volatile types.UART4, @ptrFromInt(0x40005000));
             ///  Inter-integrated circuit
-            pub const I2C1 = @ptrCast(*volatile types.I2C3, 0x40005400);
+            pub const I2C1 = @as(*volatile types.I2C3, @ptrFromInt(0x40005400));
             ///  Inter-integrated circuit
-            pub const I2C2 = @ptrCast(*volatile types.I2C3, 0x40005800);
+            pub const I2C2 = @as(*volatile types.I2C3, @ptrFromInt(0x40005800));
             ///  Inter-integrated circuit
-            pub const I2C3 = @ptrCast(*volatile types.I2C3, 0x40005c00);
+            pub const I2C3 = @as(*volatile types.I2C3, @ptrFromInt(0x40005c00));
             ///  Controller area network
-            pub const CAN1 = @ptrCast(*volatile types.CAN1, 0x40006400);
+            pub const CAN1 = @as(*volatile types.CAN1, @ptrFromInt(0x40006400));
             ///  Controller area network
-            pub const CAN2 = @ptrCast(*volatile types.CAN1, 0x40006800);
+            pub const CAN2 = @as(*volatile types.CAN1, @ptrFromInt(0x40006800));
             ///  Power control
-            pub const PWR = @ptrCast(*volatile types.PWR, 0x40007000);
+            pub const PWR = @as(*volatile types.PWR, @ptrFromInt(0x40007000));
             ///  Digital-to-analog converter
-            pub const DAC = @ptrCast(*volatile types.DAC, 0x40007400);
+            pub const DAC = @as(*volatile types.DAC, @ptrFromInt(0x40007400));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART7 = @ptrCast(*volatile types.USART6, 0x40007800);
+            pub const UART7 = @as(*volatile types.USART6, @ptrFromInt(0x40007800));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART8 = @ptrCast(*volatile types.USART6, 0x40007c00);
+            pub const UART8 = @as(*volatile types.USART6, @ptrFromInt(0x40007c00));
             ///  Advanced-timers
-            pub const TIM1 = @ptrCast(*volatile types.TIM1, 0x40010000);
+            pub const TIM1 = @as(*volatile types.TIM1, @ptrFromInt(0x40010000));
             ///  Advanced-timers
-            pub const TIM8 = @ptrCast(*volatile types.TIM1, 0x40010400);
+            pub const TIM8 = @as(*volatile types.TIM1, @ptrFromInt(0x40010400));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART1 = @ptrCast(*volatile types.USART6, 0x40011000);
+            pub const USART1 = @as(*volatile types.USART6, @ptrFromInt(0x40011000));
             ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART6 = @ptrCast(*volatile types.USART6, 0x40011400);
+            pub const USART6 = @as(*volatile types.USART6, @ptrFromInt(0x40011400));
             ///  Analog-to-digital converter
-            pub const ADC1 = @ptrCast(*volatile types.ADC1, 0x40012000);
+            pub const ADC1 = @as(*volatile types.ADC1, @ptrFromInt(0x40012000));
             ///  Analog-to-digital converter
-            pub const ADC2 = @ptrCast(*volatile types.ADC1, 0x40012100);
+            pub const ADC2 = @as(*volatile types.ADC1, @ptrFromInt(0x40012100));
             ///  Analog-to-digital converter
-            pub const ADC3 = @ptrCast(*volatile types.ADC1, 0x40012200);
+            pub const ADC3 = @as(*volatile types.ADC1, @ptrFromInt(0x40012200));
             ///  Common ADC registers
-            pub const C_ADC = @ptrCast(*volatile types.C_ADC, 0x40012300);
+            pub const C_ADC = @as(*volatile types.C_ADC, @ptrFromInt(0x40012300));
             ///  Secure digital input/output interface
-            pub const SDIO = @ptrCast(*volatile types.SDIO, 0x40012c00);
+            pub const SDIO = @as(*volatile types.SDIO, @ptrFromInt(0x40012c00));
             ///  Serial peripheral interface
-            pub const SPI1 = @ptrCast(*volatile types.SPI1, 0x40013000);
+            pub const SPI1 = @as(*volatile types.SPI1, @ptrFromInt(0x40013000));
             ///  Serial peripheral interface
-            pub const SPI4 = @ptrCast(*volatile types.SPI1, 0x40013400);
+            pub const SPI4 = @as(*volatile types.SPI1, @ptrFromInt(0x40013400));
             ///  System configuration controller
-            pub const SYSCFG = @ptrCast(*volatile types.SYSCFG, 0x40013800);
+            pub const SYSCFG = @as(*volatile types.SYSCFG, @ptrFromInt(0x40013800));
             ///  External interrupt/event controller
-            pub const EXTI = @ptrCast(*volatile types.EXTI, 0x40013c00);
+            pub const EXTI = @as(*volatile types.EXTI, @ptrFromInt(0x40013c00));
             ///  General purpose timers
-            pub const TIM9 = @ptrCast(*volatile types.TIM9, 0x40014000);
+            pub const TIM9 = @as(*volatile types.TIM9, @ptrFromInt(0x40014000));
             ///  General-purpose-timers
-            pub const TIM10 = @ptrCast(*volatile types.TIM10, 0x40014400);
+            pub const TIM10 = @as(*volatile types.TIM10, @ptrFromInt(0x40014400));
             ///  General-purpose-timers
-            pub const TIM11 = @ptrCast(*volatile types.TIM11, 0x40014800);
+            pub const TIM11 = @as(*volatile types.TIM11, @ptrFromInt(0x40014800));
             ///  Serial peripheral interface
-            pub const SPI5 = @ptrCast(*volatile types.SPI1, 0x40015000);
+            pub const SPI5 = @as(*volatile types.SPI1, @ptrFromInt(0x40015000));
             ///  Serial peripheral interface
-            pub const SPI6 = @ptrCast(*volatile types.SPI1, 0x40015400);
+            pub const SPI6 = @as(*volatile types.SPI1, @ptrFromInt(0x40015400));
             ///  Serial audio interface
-            pub const SAI = @ptrCast(*volatile types.SAI, 0x40015800);
+            pub const SAI = @as(*volatile types.SAI, @ptrFromInt(0x40015800));
             ///  LCD-TFT Controller
-            pub const LTDC = @ptrCast(*volatile types.LTDC, 0x40016800);
+            pub const LTDC = @as(*volatile types.LTDC, @ptrFromInt(0x40016800));
             ///  General-purpose I/Os
-            pub const GPIOA = @ptrCast(*volatile types.GPIOA, 0x40020000);
+            pub const GPIOA = @as(*volatile types.GPIOA, @ptrFromInt(0x40020000));
             ///  General-purpose I/Os
-            pub const GPIOB = @ptrCast(*volatile types.GPIOB, 0x40020400);
+            pub const GPIOB = @as(*volatile types.GPIOB, @ptrFromInt(0x40020400));
             ///  General-purpose I/Os
-            pub const GPIOC = @ptrCast(*volatile types.GPIOK, 0x40020800);
+            pub const GPIOC = @as(*volatile types.GPIOK, @ptrFromInt(0x40020800));
             ///  General-purpose I/Os
-            pub const GPIOD = @ptrCast(*volatile types.GPIOK, 0x40020c00);
+            pub const GPIOD = @as(*volatile types.GPIOK, @ptrFromInt(0x40020c00));
             ///  General-purpose I/Os
-            pub const GPIOE = @ptrCast(*volatile types.GPIOK, 0x40021000);
+            pub const GPIOE = @as(*volatile types.GPIOK, @ptrFromInt(0x40021000));
             ///  General-purpose I/Os
-            pub const GPIOF = @ptrCast(*volatile types.GPIOK, 0x40021400);
+            pub const GPIOF = @as(*volatile types.GPIOK, @ptrFromInt(0x40021400));
             ///  General-purpose I/Os
-            pub const GPIOG = @ptrCast(*volatile types.GPIOK, 0x40021800);
+            pub const GPIOG = @as(*volatile types.GPIOK, @ptrFromInt(0x40021800));
             ///  General-purpose I/Os
-            pub const GPIOH = @ptrCast(*volatile types.GPIOK, 0x40021c00);
+            pub const GPIOH = @as(*volatile types.GPIOK, @ptrFromInt(0x40021c00));
             ///  General-purpose I/Os
-            pub const GPIOI = @ptrCast(*volatile types.GPIOK, 0x40022000);
+            pub const GPIOI = @as(*volatile types.GPIOK, @ptrFromInt(0x40022000));
             ///  General-purpose I/Os
-            pub const GPIOJ = @ptrCast(*volatile types.GPIOK, 0x40022400);
+            pub const GPIOJ = @as(*volatile types.GPIOK, @ptrFromInt(0x40022400));
             ///  General-purpose I/Os
-            pub const GPIOK = @ptrCast(*volatile types.GPIOK, 0x40022800);
+            pub const GPIOK = @as(*volatile types.GPIOK, @ptrFromInt(0x40022800));
             ///  Cryptographic processor
-            pub const CRC = @ptrCast(*volatile types.CRC, 0x40023000);
+            pub const CRC = @as(*volatile types.CRC, @ptrFromInt(0x40023000));
             ///  Reset and clock control
-            pub const RCC = @ptrCast(*volatile types.RCC, 0x40023800);
+            pub const RCC = @as(*volatile types.RCC, @ptrFromInt(0x40023800));
             ///  FLASH
-            pub const FLASH = @ptrCast(*volatile types.FLASH, 0x40023c00);
+            pub const FLASH = @as(*volatile types.FLASH, @ptrFromInt(0x40023c00));
             ///  DMA controller
-            pub const DMA1 = @ptrCast(*volatile types.DMA2, 0x40026000);
+            pub const DMA1 = @as(*volatile types.DMA2, @ptrFromInt(0x40026000));
             ///  DMA controller
-            pub const DMA2 = @ptrCast(*volatile types.DMA2, 0x40026400);
+            pub const DMA2 = @as(*volatile types.DMA2, @ptrFromInt(0x40026400));
             ///  Ethernet: media access control (MAC)
-            pub const Ethernet_MAC = @ptrCast(*volatile types.Ethernet_MAC, 0x40028000);
+            pub const Ethernet_MAC = @as(*volatile types.Ethernet_MAC, @ptrFromInt(0x40028000));
             ///  Ethernet: MAC management counters
-            pub const Ethernet_MMC = @ptrCast(*volatile types.Ethernet_MMC, 0x40028100);
+            pub const Ethernet_MMC = @as(*volatile types.Ethernet_MMC, @ptrFromInt(0x40028100));
             ///  Ethernet: Precision time protocol
-            pub const Ethernet_PTP = @ptrCast(*volatile types.Ethernet_PTP, 0x40028700);
+            pub const Ethernet_PTP = @as(*volatile types.Ethernet_PTP, @ptrFromInt(0x40028700));
             ///  Ethernet: DMA controller operation
-            pub const Ethernet_DMA = @ptrCast(*volatile types.Ethernet_DMA, 0x40029000);
+            pub const Ethernet_DMA = @as(*volatile types.Ethernet_DMA, @ptrFromInt(0x40029000));
             ///  DMA2D controller
-            pub const DMA2D = @ptrCast(*volatile types.DMA2D, 0x4002b000);
+            pub const DMA2D = @as(*volatile types.DMA2D, @ptrFromInt(0x4002b000));
             ///  USB on the go high speed
-            pub const OTG_HS_GLOBAL = @ptrCast(*volatile types.OTG_HS_GLOBAL, 0x40040000);
+            pub const OTG_HS_GLOBAL = @as(*volatile types.OTG_HS_GLOBAL, @ptrFromInt(0x40040000));
             ///  USB on the go high speed
-            pub const OTG_HS_HOST = @ptrCast(*volatile types.OTG_HS_HOST, 0x40040400);
+            pub const OTG_HS_HOST = @as(*volatile types.OTG_HS_HOST, @ptrFromInt(0x40040400));
             ///  USB on the go high speed
-            pub const OTG_HS_DEVICE = @ptrCast(*volatile types.OTG_HS_DEVICE, 0x40040800);
+            pub const OTG_HS_DEVICE = @as(*volatile types.OTG_HS_DEVICE, @ptrFromInt(0x40040800));
             ///  USB on the go high speed
-            pub const OTG_HS_PWRCLK = @ptrCast(*volatile types.OTG_HS_PWRCLK, 0x40040e00);
+            pub const OTG_HS_PWRCLK = @as(*volatile types.OTG_HS_PWRCLK, @ptrFromInt(0x40040e00));
             ///  USB on the go full speed
-            pub const OTG_FS_GLOBAL = @ptrCast(*volatile types.OTG_FS_GLOBAL, 0x50000000);
+            pub const OTG_FS_GLOBAL = @as(*volatile types.OTG_FS_GLOBAL, @ptrFromInt(0x50000000));
             ///  USB on the go full speed
-            pub const OTG_FS_HOST = @ptrCast(*volatile types.OTG_FS_HOST, 0x50000400);
+            pub const OTG_FS_HOST = @as(*volatile types.OTG_FS_HOST, @ptrFromInt(0x50000400));
             ///  USB on the go full speed
-            pub const OTG_FS_DEVICE = @ptrCast(*volatile types.OTG_FS_DEVICE, 0x50000800);
+            pub const OTG_FS_DEVICE = @as(*volatile types.OTG_FS_DEVICE, @ptrFromInt(0x50000800));
             ///  USB on the go full speed
-            pub const OTG_FS_PWRCLK = @ptrCast(*volatile types.OTG_FS_PWRCLK, 0x50000e00);
+            pub const OTG_FS_PWRCLK = @as(*volatile types.OTG_FS_PWRCLK, @ptrFromInt(0x50000e00));
             ///  Digital camera interface
-            pub const DCMI = @ptrCast(*volatile types.DCMI, 0x50050000);
+            pub const DCMI = @as(*volatile types.DCMI, @ptrFromInt(0x50050000));
             ///  Cryptographic processor
-            pub const CRYP = @ptrCast(*volatile types.CRYP, 0x50060000);
+            pub const CRYP = @as(*volatile types.CRYP, @ptrFromInt(0x50060000));
             ///  Hash processor
-            pub const HASH = @ptrCast(*volatile types.HASH, 0x50060400);
+            pub const HASH = @as(*volatile types.HASH, @ptrFromInt(0x50060400));
             ///  Random number generator
-            pub const RNG = @ptrCast(*volatile types.RNG, 0x50060800);
+            pub const RNG = @as(*volatile types.RNG, @ptrFromInt(0x50060800));
             ///  Flexible memory controller
-            pub const FMC = @ptrCast(*volatile types.FMC, 0xa0000000);
+            pub const FMC = @as(*volatile types.FMC, @ptrFromInt(0xa0000000));
             ///  System control block ACTLR
-            pub const SCB_ACTRL = @ptrCast(*volatile types.SCB_ACTRL, 0xe000e008);
+            pub const SCB_ACTRL = @as(*volatile types.SCB_ACTRL, @ptrFromInt(0xe000e008));
             ///  SysTick timer
-            pub const STK = @ptrCast(*volatile types.STK, 0xe000e010);
+            pub const STK = @as(*volatile types.STK, @ptrFromInt(0xe000e010));
             ///  Nested Vectored Interrupt Controller
-            pub const NVIC = @ptrCast(*volatile types.NVIC, 0xe000e100);
+            pub const NVIC = @as(*volatile types.NVIC, @ptrFromInt(0xe000e100));
             ///  System control block
-            pub const SCB = @ptrCast(*volatile types.SCB, 0xe000ed00);
+            pub const SCB = @as(*volatile types.SCB, @ptrFromInt(0xe000ed00));
             ///  Floating point unit CPACR
-            pub const FPU_CPACR = @ptrCast(*volatile types.FPU_CPACR, 0xe000ed88);
+            pub const FPU_CPACR = @as(*volatile types.FPU_CPACR, @ptrFromInt(0xe000ed88));
             ///  Memory protection unit
-            pub const MPU = @ptrCast(*volatile types.MPU, 0xe000ed90);
+            pub const MPU = @as(*volatile types.MPU, @ptrFromInt(0xe000ed90));
             ///  Nested vectored interrupt controller
-            pub const NVIC_STIR = @ptrCast(*volatile types.NVIC_STIR, 0xe000ef00);
+            pub const NVIC_STIR = @as(*volatile types.NVIC_STIR, @ptrFromInt(0xe000ef00));
             ///  Floting point unit
-            pub const FPU = @ptrCast(*volatile types.FPU, 0xe000ef34);
+            pub const FPU = @as(*volatile types.FPU, @ptrFromInt(0xe000ef34));
             ///  Debug support
-            pub const DBG = @ptrCast(*volatile types.DBG, 0xe0042000);
+            pub const DBG = @as(*volatile types.DBG, @ptrFromInt(0xe0042000));
         };
     };
 };
diff --git a/src/hals/STM32F303.zig b/src/hals/STM32F303.zig
index 5c470c83b..17c6999bc 100644
--- a/src/hals/STM32F303.zig
+++ b/src/hals/STM32F303.zig
@@ -103,7 +103,7 @@ pub const gpio = struct {
     pub fn read(comptime pin: type) micro.gpio.State {
         const idr_reg = pin.gpio_port.IDR;
         const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()?
-        return @intToEnum(micro.gpio.State, reg_value);
+        return @as(micro.gpio.State, @enumFromInt(reg_value));
     }
 
     pub fn write(comptime pin: type, state: micro.gpio.State) void {
@@ -180,11 +180,11 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
 
             // set parity
             if (config.parity) |parity| {
-                USART1.CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) });
+                USART1.CR1.modify(.{ .PCE = 1, .PS = @intFromEnum(parity) });
             } else USART1.CR1.modify(.{ .PCE = 0 }); // no parity, probably the chip default
 
             // set number of stop bits
-            USART1.CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) });
+            USART1.CR2.modify(.{ .STOP = @intFromEnum(config.stop_bits) });
 
             // set the baud rate
             // TODO: Do not use the _board_'s frequency, but the _U(S)ARTx_ frequency
@@ -193,7 +193,7 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
             // if the board doesn't configure e.g. an HSE external crystal.
             // TODO: Do some checks to see if the baud rate is too high (or perhaps too low)
             // TODO: Do a rounding div, instead of a truncating div?
-            const usartdiv = @intCast(u16, @divTrunc(micro.clock.get().apb1, config.baud_rate));
+            const usartdiv = @as(u16, @intCast(@divTrunc(micro.clock.get().apb1, config.baud_rate)));
             USART1.BRR.raw = usartdiv;
             // Above, ignore the BRR struct fields DIV_Mantissa and DIV_Fraction,
             // those seem to be for another chipset; .svd file bug?
@@ -254,7 +254,7 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
         pub fn rx(self: Self) u8 {
             while (!self.can_read()) {} // Wait till the data is received
             const data_with_parity_bit: u9 = USART1.RDR.read().RDR;
-            return @intCast(u8, data_with_parity_bit & self.parity_read_mask);
+            return @as(u8, @intCast(data_with_parity_bit & self.parity_read_mask));
         }
     };
 }
@@ -429,7 +429,7 @@ pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type
                     .ADD10 = 0,
                     .SADD1 = self.address,
                     .RD_WRN = 1, // read
-                    .NBYTES = @intCast(u8, buffer.len),
+                    .NBYTES = @as(u8, @intCast(buffer.len)),
                 });
                 debug_print("I2C1 prepared for read of {} byte(s) from 0b{b:0<7}\r\n", .{ buffer.len, self.address });
 
@@ -556,7 +556,7 @@ pub fn SpiBus(comptime index: usize) type {
 
             // write
             const write_byte = if (optional_write_byte) |b| b else undefined; // dummy value
-            @bitCast([dr_byte_size]u8, SPI1.DR.*)[0] = write_byte;
+            @as([dr_byte_size]u8, @bitCast(SPI1.DR.*))[0] = write_byte;
             debug_print("Sent: {X:2}.\r\n", .{write_byte});
 
             // wait until read processed
@@ -568,7 +568,7 @@ pub fn SpiBus(comptime index: usize) type {
             // read
             var data_read = SPI1.DR.raw;
             _ = SPI1.SR.read(); // clear overrun flag
-            const dr_lsb = @bitCast([dr_byte_size]u8, data_read)[0];
+            const dr_lsb = @as([dr_byte_size]u8, @bitCast(data_read))[0];
             debug_print("Received: {X:2} (DR = {X:8}).\r\n", .{ dr_lsb, data_read });
             if (optional_read_pointer) |read_pointer| read_pointer.* = dr_lsb;
         }
diff --git a/src/hals/STM32F407.zig b/src/hals/STM32F407.zig
index f48e05c8d..6c4dd2047 100644
--- a/src/hals/STM32F407.zig
+++ b/src/hals/STM32F407.zig
@@ -111,16 +111,16 @@ pub const gpio = struct {
         set_reg_field(RCC.AHB1ENR, "GPIO" ++ pin.gpio_port_name ++ "EN", 1);
         set_reg_field(@field(pin.gpio_port, "MODER"), "MODER" ++ pin.suffix, 0b10);
         if (pin.pin_number < 8) {
-            set_reg_field(@field(pin.gpio_port, "AFRL"), "AFRL" ++ pin.suffix, @enumToInt(af));
+            set_reg_field(@field(pin.gpio_port, "AFRL"), "AFRL" ++ pin.suffix, @intFromEnum(af));
         } else {
-            set_reg_field(@field(pin.gpio_port, "AFRH"), "AFRH" ++ pin.suffix, @enumToInt(af));
+            set_reg_field(@field(pin.gpio_port, "AFRH"), "AFRH" ++ pin.suffix, @intFromEnum(af));
         }
     }
 
     pub fn read(comptime pin: type) micro.gpio.State {
         const idr_reg = pin.gpio_port.IDR;
         const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()?
-        return @intToEnum(micro.gpio.State, reg_value);
+        return @as(micro.gpio.State, @enumFromInt(reg_value));
     }
 
     pub fn write(comptime pin: type, state: micro.gpio.State) void {
@@ -278,11 +278,11 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
 
             // set parity
             if (config.parity) |parity| {
-                @field(peripherals, usart_name).CR1.modify(.{ .PCE = 1, .PS = @enumToInt(parity) });
+                @field(peripherals, usart_name).CR1.modify(.{ .PCE = 1, .PS = @intFromEnum(parity) });
             } // otherwise, no need to set no parity since we reset Control Registers above, and it's the default
 
             // set number of stop bits
-            @field(peripherals, usart_name).CR2.modify(.{ .STOP = @enumToInt(config.stop_bits) });
+            @field(peripherals, usart_name).CR2.modify(.{ .STOP = @intFromEnum(config.stop_bits) });
 
             // set the baud rate
             // Despite the reference manual talking about fractional calculation and other buzzwords,
@@ -297,7 +297,7 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
                 2...5 => clocks.apb1,
                 else => unreachable,
             };
-            const usartdiv = @intCast(u16, @divTrunc(bus_frequency, config.baud_rate));
+            const usartdiv = @as(u16, @intCast(@divTrunc(bus_frequency, config.baud_rate)));
             @field(peripherals, usart_name).BRR.raw = usartdiv;
 
             // enable USART, and its transmitter and receiver
@@ -355,7 +355,7 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
         pub fn rx(self: Self) u8 {
             while (!self.can_read()) {} // Wait till the data is received
             const data_with_parity_bit: u9 = @field(peripherals, usart_name).DR.read();
-            return @intCast(u8, data_with_parity_bit & self.parity_read_mask);
+            return @as(u8, @intCast(data_with_parity_bit & self.parity_read_mask));
         }
     };
 }
@@ -463,7 +463,7 @@ pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type
 
             // 4. Configure I2C timing
             const bus_frequency_hz = micro.clock.get().apb1;
-            const bus_frequency_mhz: u6 = @intCast(u6, @divExact(bus_frequency_hz, 1_000_000));
+            const bus_frequency_mhz: u6 = @as(u6, @intCast(@divExact(bus_frequency_hz, 1_000_000)));
 
             if (bus_frequency_mhz < 2 or bus_frequency_mhz > 50) {
                 return error.InvalidBusFrequency;
@@ -475,7 +475,7 @@ pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type
             switch (config.target_speed) {
                 10_000...100_000 => {
                     // CCR is bus_freq / (target_speed * 2). We use floor to avoid exceeding the target speed.
-                    const ccr = @intCast(u12, @divFloor(bus_frequency_hz, config.target_speed * 2));
+                    const ccr = @as(u12, @intCast(@divFloor(bus_frequency_hz, config.target_speed * 2)));
                     i2c_base.CCR.modify(.{ .CCR = ccr });
                     // Trise is bus frequency in Mhz + 1
                     i2c_base.TRISE.modify(bus_frequency_mhz + 1);
@@ -529,7 +529,7 @@ pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type
                 {}
 
                 // Write the address to bits 7..1, bit 0 stays at 0 to indicate write operation
-                i2c_base.DR.modify(@intCast(u8, self.address) << 1);
+                i2c_base.DR.modify(@as(u8, @intCast(self.address)) << 1);
 
                 // Wait for address confirmation
                 while (i2c_base.SR1.read().ADDR == 0) {}
@@ -584,7 +584,7 @@ pub fn I2CController(comptime index: usize, comptime pins: micro.i2c.Pins) type
                 {}
 
                 // Write the address to bits 7..1, bit 0 set to 1 to indicate read operation
-                i2c_base.DR.modify((@intCast(u8, self.address) << 1) | 1);
+                i2c_base.DR.modify((@as(u8, @intCast(self.address)) << 1) | 1);
 
                 // Wait for address confirmation
                 while (i2c_base.SR1.read().ADDR == 0) {}
diff --git a/src/hals/STM32F429.zig b/src/hals/STM32F429.zig
index 3aed96341..0f5204d79 100644
--- a/src/hals/STM32F429.zig
+++ b/src/hals/STM32F429.zig
@@ -80,7 +80,7 @@ pub const gpio = struct {
     pub fn read(comptime pin: type) micro.gpio.State {
         const idr_reg = pin.gpio_port.IDR;
         const reg_value = @field(idr_reg.read(), "IDR" ++ pin.suffix); // TODO extract to getRegField()?
-        return @intToEnum(micro.gpio.State, reg_value);
+        return @as(micro.gpio.State, @enumFromInt(reg_value));
     }
 
     pub fn write(comptime pin: type, state: micro.gpio.State) void {

From 03a53c756c0a54a04d43220696e9cd1946c1b30c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sat, 26 Aug 2023 00:01:43 +0200
Subject: [PATCH 189/286] Update to zig-0.11.0 (#24)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-authored-by: Felix "xq" Queißner 
---
 build.zig                    | 17 +++++++--
 build.zig.zon                | 10 +++++
 deps/microzig                |  1 -
 src/chips.zig                |  2 +-
 src/chips/ESP32_C3.zig       | 72 ++++++++++++++++++------------------
 src/cpus.zig                 |  2 +-
 src/cpus/espressif-riscv.zig |  2 +-
 src/example/blinky.zig       |  6 +--
 src/hals/ESP32_C3.zig        |  6 +--
 zpm.zig                      |  8 ----
 10 files changed, 69 insertions(+), 57 deletions(-)
 create mode 100644 build.zig.zon
 delete mode 160000 deps/microzig
 delete mode 100644 zpm.zig

diff --git a/build.zig b/build.zig
index 8cb289d70..e04ab94ae 100644
--- a/build.zig
+++ b/build.zig
@@ -1,10 +1,10 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/build.zig");
+const microzig = @import("microzig");
 
 pub const chips = @import("src/chips.zig");
 pub const cpus = @import("src/cpus.zig");
 
-pub fn build(b: *std.build.Builder) void {
+pub fn build(b: *std.Build) void {
     const optimize = b.standardOptimizeOption(.{});
 
     var exe = microzig.addEmbeddedExecutable(b, .{
@@ -15,5 +15,16 @@ pub fn build(b: *std.build.Builder) void {
         .backing = .{ .chip = chips.esp32_c3 },
         .optimize = optimize,
     });
-    exe.installArtifact(b);
+
+    const fw_objcopy = b.addObjCopy(exe.inner.getEmittedBin(), .{
+        .format = .bin,
+    });
+
+    const fw_bin = fw_objcopy.getOutput();
+
+    const install_fw_bin = b.addInstallFile(fw_bin, "firmware/blinky.bin");
+
+    b.getInstallStep().dependOn(&install_fw_bin.step);
+
+    b.installArtifact(exe.inner);
 }
diff --git a/build.zig.zon b/build.zig.zon
new file mode 100644
index 000000000..e8787ef0b
--- /dev/null
+++ b/build.zig.zon
@@ -0,0 +1,10 @@
+.{
+    .name = "microzig-espressif-esp",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
+            .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
+        },
+    },
+}
diff --git a/deps/microzig b/deps/microzig
deleted file mode 160000
index 9392fe0f7..000000000
--- a/deps/microzig
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791
diff --git a/src/chips.zig b/src/chips.zig
index 14769f383..3baa05a3d 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/build.zig");
+const microzig = @import("microzig");
 const cpus = @import("cpus.zig");
 
 fn root_dir() []const u8 {
diff --git a/src/chips/ESP32_C3.zig b/src/chips/ESP32_C3.zig
index 50a326366..8a632a07d 100644
--- a/src/chips/ESP32_C3.zig
+++ b/src/chips/ESP32_C3.zig
@@ -33,77 +33,77 @@ pub const devices = struct {
 
         pub const peripherals = struct {
             ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
-            pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x60000000);
+            pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x60000000));
             ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI1, 0x60002000);
+            pub const SPI1 = @as(*volatile types.peripherals.SPI1, @ptrFromInt(0x60002000));
             ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x60003000);
+            pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x60003000));
             ///  General Purpose Input/Output
-            pub const GPIO = @intToPtr(*volatile types.peripherals.GPIO, 0x60004000);
+            pub const GPIO = @as(*volatile types.peripherals.GPIO, @ptrFromInt(0x60004000));
             ///  Sigma-Delta Modulation
-            pub const GPIOSD = @intToPtr(*volatile types.peripherals.GPIOSD, 0x60004f00);
+            pub const GPIOSD = @as(*volatile types.peripherals.GPIOSD, @ptrFromInt(0x60004f00));
             ///  Real-Time Clock Control
-            pub const RTC_CNTL = @intToPtr(*volatile types.peripherals.RTC_CNTL, 0x60008000);
+            pub const RTC_CNTL = @as(*volatile types.peripherals.RTC_CNTL, @ptrFromInt(0x60008000));
             ///  eFuse Controller
-            pub const EFUSE = @intToPtr(*volatile types.peripherals.EFUSE, 0x60008800);
+            pub const EFUSE = @as(*volatile types.peripherals.EFUSE, @ptrFromInt(0x60008800));
             ///  Input/Output Multiplexer
-            pub const IO_MUX = @intToPtr(*volatile types.peripherals.IO_MUX, 0x60009000);
+            pub const IO_MUX = @as(*volatile types.peripherals.IO_MUX, @ptrFromInt(0x60009000));
             ///  Universal Host Controller Interface
-            pub const UHCI1 = @intToPtr(*volatile types.peripherals.UHCI0, 0x6000c000);
+            pub const UHCI1 = @as(*volatile types.peripherals.UHCI0, @ptrFromInt(0x6000c000));
             ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
-            pub const UART1 = @intToPtr(*volatile types.peripherals.UART0, 0x60010000);
+            pub const UART1 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x60010000));
             ///  I2C (Inter-Integrated Circuit) Controller
-            pub const I2C0 = @intToPtr(*volatile types.peripherals.I2C0, 0x60013000);
+            pub const I2C0 = @as(*volatile types.peripherals.I2C0, @ptrFromInt(0x60013000));
             ///  Universal Host Controller Interface
-            pub const UHCI0 = @intToPtr(*volatile types.peripherals.UHCI0, 0x60014000);
+            pub const UHCI0 = @as(*volatile types.peripherals.UHCI0, @ptrFromInt(0x60014000));
             ///  Remote Control Peripheral
-            pub const RMT = @intToPtr(*volatile types.peripherals.RMT, 0x60016000);
+            pub const RMT = @as(*volatile types.peripherals.RMT, @ptrFromInt(0x60016000));
             ///  LED Control PWM (Pulse Width Modulation)
-            pub const LEDC = @intToPtr(*volatile types.peripherals.LEDC, 0x60019000);
+            pub const LEDC = @as(*volatile types.peripherals.LEDC, @ptrFromInt(0x60019000));
             ///  Timer Group
-            pub const TIMG0 = @intToPtr(*volatile types.peripherals.TIMG0, 0x6001f000);
+            pub const TIMG0 = @as(*volatile types.peripherals.TIMG0, @ptrFromInt(0x6001f000));
             ///  Timer Group
-            pub const TIMG1 = @intToPtr(*volatile types.peripherals.TIMG0, 0x60020000);
+            pub const TIMG1 = @as(*volatile types.peripherals.TIMG0, @ptrFromInt(0x60020000));
             ///  System Timer
-            pub const SYSTIMER = @intToPtr(*volatile types.peripherals.SYSTIMER, 0x60023000);
+            pub const SYSTIMER = @as(*volatile types.peripherals.SYSTIMER, @ptrFromInt(0x60023000));
             ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI2, 0x60024000);
+            pub const SPI2 = @as(*volatile types.peripherals.SPI2, @ptrFromInt(0x60024000));
             ///  Advanced Peripheral Bus Controller
-            pub const APB_CTRL = @intToPtr(*volatile types.peripherals.APB_CTRL, 0x60026000);
+            pub const APB_CTRL = @as(*volatile types.peripherals.APB_CTRL, @ptrFromInt(0x60026000));
             ///  Hardware random number generator
-            pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x60026000);
+            pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x60026000));
             ///  Two-Wire Automotive Interface
-            pub const TWAI = @intToPtr(*volatile types.peripherals.TWAI, 0x6002b000);
+            pub const TWAI = @as(*volatile types.peripherals.TWAI, @ptrFromInt(0x6002b000));
             ///  I2S (Inter-IC Sound) Controller
-            pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x6002d000);
+            pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x6002d000));
             ///  AES (Advanced Encryption Standard) Accelerator
-            pub const AES = @intToPtr(*volatile types.peripherals.AES, 0x6003a000);
+            pub const AES = @as(*volatile types.peripherals.AES, @ptrFromInt(0x6003a000));
             ///  SHA (Secure Hash Algorithm) Accelerator
-            pub const SHA = @intToPtr(*volatile types.peripherals.SHA, 0x6003b000);
+            pub const SHA = @as(*volatile types.peripherals.SHA, @ptrFromInt(0x6003b000));
             ///  RSA (Rivest Shamir Adleman) Accelerator
-            pub const RSA = @intToPtr(*volatile types.peripherals.RSA, 0x6003c000);
+            pub const RSA = @as(*volatile types.peripherals.RSA, @ptrFromInt(0x6003c000));
             ///  Digital Signature
-            pub const DS = @intToPtr(*volatile types.peripherals.DS, 0x6003d000);
+            pub const DS = @as(*volatile types.peripherals.DS, @ptrFromInt(0x6003d000));
             ///  HMAC (Hash-based Message Authentication Code) Accelerator
-            pub const HMAC = @intToPtr(*volatile types.peripherals.HMAC, 0x6003e000);
+            pub const HMAC = @as(*volatile types.peripherals.HMAC, @ptrFromInt(0x6003e000));
             ///  DMA (Direct Memory Access) Controller
-            pub const DMA = @intToPtr(*volatile types.peripherals.DMA, 0x6003f000);
+            pub const DMA = @as(*volatile types.peripherals.DMA, @ptrFromInt(0x6003f000));
             ///  Successive Approximation Register Analog to Digital Converter
-            pub const APB_SARADC = @intToPtr(*volatile types.peripherals.APB_SARADC, 0x60040000);
+            pub const APB_SARADC = @as(*volatile types.peripherals.APB_SARADC, @ptrFromInt(0x60040000));
             ///  Full-speed USB Serial/JTAG Controller
-            pub const USB_DEVICE = @intToPtr(*volatile types.peripherals.USB_DEVICE, 0x60043000);
+            pub const USB_DEVICE = @as(*volatile types.peripherals.USB_DEVICE, @ptrFromInt(0x60043000));
             ///  System
-            pub const SYSTEM = @intToPtr(*volatile types.peripherals.SYSTEM, 0x600c0000);
+            pub const SYSTEM = @as(*volatile types.peripherals.SYSTEM, @ptrFromInt(0x600c0000));
             ///  Sensitive
-            pub const SENSITIVE = @intToPtr(*volatile types.peripherals.SENSITIVE, 0x600c1000);
+            pub const SENSITIVE = @as(*volatile types.peripherals.SENSITIVE, @ptrFromInt(0x600c1000));
             ///  Interrupt Core
-            pub const INTERRUPT_CORE0 = @intToPtr(*volatile types.peripherals.INTERRUPT_CORE0, 0x600c2000);
+            pub const INTERRUPT_CORE0 = @as(*volatile types.peripherals.INTERRUPT_CORE0, @ptrFromInt(0x600c2000));
             ///  External Memory
-            pub const EXTMEM = @intToPtr(*volatile types.peripherals.EXTMEM, 0x600c4000);
+            pub const EXTMEM = @as(*volatile types.peripherals.EXTMEM, @ptrFromInt(0x600c4000));
             ///  XTS-AES-128 Flash Encryption
-            pub const XTS_AES = @intToPtr(*volatile types.peripherals.XTS_AES, 0x600cc000);
+            pub const XTS_AES = @as(*volatile types.peripherals.XTS_AES, @ptrFromInt(0x600cc000));
             ///  Debug Assist
-            pub const ASSIST_DEBUG = @intToPtr(*volatile types.peripherals.ASSIST_DEBUG, 0x600ce000);
+            pub const ASSIST_DEBUG = @as(*volatile types.peripherals.ASSIST_DEBUG, @ptrFromInt(0x600ce000));
         };
     };
 };
diff --git a/src/cpus.zig b/src/cpus.zig
index b087d90a9..c8bda913e 100644
--- a/src/cpus.zig
+++ b/src/cpus.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("../deps/microzig/build.zig");
+const microzig = @import("microzig");
 
 fn root_dir() []const u8 {
     return std.fs.path.dirname(@src().file) orelse unreachable;
diff --git a/src/cpus/espressif-riscv.zig b/src/cpus/espressif-riscv.zig
index dc2edb769..5aab92d79 100644
--- a/src/cpus/espressif-riscv.zig
+++ b/src/cpus/espressif-riscv.zig
@@ -61,7 +61,7 @@ pub const startup_logic = struct {
 
     extern fn microzig_main() noreturn;
 
-    export fn _start() linksection("microzig_flash_start") callconv(.Naked) noreturn {
+    export fn _start() linksection("microzig_flash_start") callconv(.C) noreturn {
         microzig.cpu.disable_interrupts();
         asm volatile ("mv sp, %[eos]"
             :
diff --git a/src/example/blinky.zig b/src/example/blinky.zig
index 5ee1eefc5..811b04894 100644
--- a/src/example/blinky.zig
+++ b/src/example/blinky.zig
@@ -42,13 +42,13 @@ pub fn main() !void {
     while (true) {
         GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
         microzig.hal.uart.write(0, "R");
-        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        microzig.core.experimental.debug.busy_sleep(100_000);
         GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
         microzig.hal.uart.write(0, "G");
-        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        microzig.core.experimental.debug.busy_sleep(100_000);
         GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
         microzig.hal.uart.write(0, "B");
-        microzig.core.experimental.debug.busy_sleep(1_000_000);
+        microzig.core.experimental.debug.busy_sleep(100_000);
     }
 }
 
diff --git a/src/hals/ESP32_C3.zig b/src/hals/ESP32_C3.zig
index 516ed1524..a5e1bb9e7 100644
--- a/src/hals/ESP32_C3.zig
+++ b/src/hals/ESP32_C3.zig
@@ -21,9 +21,9 @@ pub const gpio = struct {
         assertRange(pin);
         GPIO.FUNC_OUT_SEL_CFG[pin].modify(.{
             .OUT_SEL = config.function,
-            .INV_SEL = @boolToInt(config.invert_function),
-            .OEN_SEL = @boolToInt(config.direct_io),
-            .OEN_INV_SEL = @boolToInt(config.invert_direct_io),
+            .INV_SEL = @intFromBool(config.invert_function),
+            .OEN_SEL = @intFromBool(config.direct_io),
+            .OEN_INV_SEL = @intFromBool(config.invert_direct_io),
         });
         switch (config.direction) {
             .input => GPIO.ENABLE.raw &= ~(@as(u32, 1) << pin),
diff --git a/zpm.zig b/zpm.zig
deleted file mode 100644
index 1dcd7b385..000000000
--- a/zpm.zig
+++ /dev/null
@@ -1,8 +0,0 @@
-//! This file is auto-generated by zpm-update and *should*
-//! not be changed. This file can be checked into your VCS
-//! and is able to work standalone.
-const std = @import("std");
-
-pub const sdks = struct {
-    pub const microzig = @import("vendor/microzig/src/main.zig");
-};

From 82c944b48ceb4814c6dac511f49a89c08a16a3e3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sat, 26 Aug 2023 00:29:02 +0200
Subject: [PATCH 190/286] Fixes (#25)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* Update to zig-0.11.0

* Removes unnecessary submodule

---------

Co-authored-by: Felix "xq" Queißner 
---
 .gitmodules     | 6 ------
 vendor/microzig | 1 -
 2 files changed, 7 deletions(-)
 delete mode 160000 vendor/microzig

diff --git a/.gitmodules b/.gitmodules
index 911b8cfac..e69de29bb 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,6 +0,0 @@
-[submodule "vendor/microzig"]
-	path = vendor/microzig
-	url = https://github.com/ZigEmbeddedGroup/microzig
-[submodule "deps/microzig"]
-	path = deps/microzig
-	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/vendor/microzig b/vendor/microzig
deleted file mode 160000
index 0d9721d90..000000000
--- a/vendor/microzig
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 0d9721d9070c356f4ffaf6f4a312bccdb574b8a9

From aceafa110ad6b4555c3850b54aba2392c1ef7d73 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sat, 26 Aug 2023 14:11:07 +0200
Subject: [PATCH 191/286] GitHub CI (#26)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* GitHub CI

* Update CI

---------

Co-authored-by: Felix "xq" Queißner 
---
 .buildkite/pipeline.yml     |  4 ----
 .github/workflows/build.yml | 19 +++++++++++++++++++
 2 files changed, 19 insertions(+), 4 deletions(-)
 delete mode 100644 .buildkite/pipeline.yml
 create mode 100644 .github/workflows/build.yml

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
deleted file mode 100644
index 7767bbb66..000000000
--- a/.buildkite/pipeline.yml
+++ /dev/null
@@ -1,4 +0,0 @@
-steps:
-  - group: Build
-    steps:
-    - command: zig build
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
new file mode 100644
index 000000000..63ea5331c
--- /dev/null
+++ b/.github/workflows/build.yml
@@ -0,0 +1,19 @@
+name: Build
+on:
+  push:
+
+jobs:
+  build:
+    runs-on: ${{ matrix.os }}
+    strategy:
+      matrix:
+        os: [ubuntu-latest, windows-latest, macos-latest]
+        optimize: [Debug, ReleaseSmall, ReleaseFast, ReleaseSafe]
+    steps:
+      - uses: actions/checkout@v2
+      - uses: goto-bus-stop/setup-zig@v2.1.1
+        with:
+          version: 0.11.0
+
+      - name: Build
+        run: zig build install "-Doptimize=${{matrix.optimize}}"

From 80e5e694203ca379fc0bab888614c850b7b0bb16 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sat, 26 Aug 2023 14:25:07 +0200
Subject: [PATCH 192/286] Updates to Zig 0.11.0 (#22)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-authored-by: Felix "xq" Queißner 
---
 .buildkite/pipeline.yml     |   6 --
 .github/FUNDING.yml         |   1 +
 .github/workflows/build.yml |  19 +++++
 build.zig                   |   5 +-
 build.zig.zon               |  10 +++
 deps/microzig               |   1 -
 src/chips.zig               |  21 ++---
 src/chips/nrf52.zig         | 132 ++++++++++++++++----------------
 src/chips/nrf52840.zig      | 148 ++++++++++++++++++------------------
 9 files changed, 179 insertions(+), 164 deletions(-)
 delete mode 100644 .buildkite/pipeline.yml
 create mode 100644 .github/FUNDING.yml
 create mode 100644 .github/workflows/build.yml
 create mode 100644 build.zig.zon
 delete mode 160000 deps/microzig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
deleted file mode 100644
index 5fd8795bc..000000000
--- a/.buildkite/pipeline.yml
+++ /dev/null
@@ -1,6 +0,0 @@
-steps:
-  - group: Build and Test
-    steps:
-    - command: zig build
-    - label: 🔨 Test
-      command: renode-test test/nrf52840.robot
diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml
new file mode 100644
index 000000000..85b5393bb
--- /dev/null
+++ b/.github/FUNDING.yml
@@ -0,0 +1 @@
+github: MasterQ32
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
new file mode 100644
index 000000000..63ea5331c
--- /dev/null
+++ b/.github/workflows/build.yml
@@ -0,0 +1,19 @@
+name: Build
+on:
+  push:
+
+jobs:
+  build:
+    runs-on: ${{ matrix.os }}
+    strategy:
+      matrix:
+        os: [ubuntu-latest, windows-latest, macos-latest]
+        optimize: [Debug, ReleaseSmall, ReleaseFast, ReleaseSafe]
+    steps:
+      - uses: actions/checkout@v2
+      - uses: goto-bus-stop/setup-zig@v2.1.1
+        with:
+          version: 0.11.0
+
+      - name: Build
+        run: zig build install "-Doptimize=${{matrix.optimize}}"
diff --git a/build.zig b/build.zig
index ff60e94a8..1e421fd6d 100644
--- a/build.zig
+++ b/build.zig
@@ -1,14 +1,11 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/build.zig");
+const microzig = @import("microzig");
 
 pub const chips = @import("src/chips.zig");
 
 pub fn build(b: *std.build.Builder) void {
     const optimize = b.standardOptimizeOption(.{});
     inline for (@typeInfo(chips).Struct.decls) |decl| {
-        if (!decl.is_pub)
-            continue;
-
         const exe = microzig.addEmbeddedExecutable(b, .{
             .name = decl.name ++ ".minimal",
             .source_file = .{
diff --git a/build.zig.zon b/build.zig.zon
new file mode 100644
index 000000000..f69b76de5
--- /dev/null
+++ b/build.zig.zon
@@ -0,0 +1,10 @@
+.{
+    .name = "microzig-nordic-nrf5x",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
+            .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
+        },
+    },
+}
diff --git a/deps/microzig b/deps/microzig
deleted file mode 160000
index 9392fe0f7..000000000
--- a/deps/microzig
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791
diff --git a/src/chips.zig b/src/chips.zig
index 2487aa066..f53d85b86 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const micro = @import("../deps/microzig/build.zig");
+const micro = @import("microzig");
 const Chip = micro.Chip;
 const MemoryRegion = micro.MemoryRegion;
 
@@ -9,19 +9,17 @@ fn root_dir() []const u8 {
 
 pub const nrf52840 = Chip{
     .name = "nrf52840",
-    .source = .{
-        .path = root_dir() ++ "/chips/nrf52840.zig",
-    },
-    .json_register_schema = .{
-        .path = root_dir() ++ "/chips.nrf52840.json",
-    },
+    .source = .{ .path = root_dir() ++ "/chips/nrf52840.zig" },
+    .json_register_schema = .{ .path = root_dir() ++ "/chips.nrf52840.json" },
     .cpu = micro.cpus.cortex_m4,
+
     .memory_regions = &.{
         MemoryRegion{ .offset = 0x00000000, .length = 0x100000, .kind = .flash },
         MemoryRegion{ .offset = 0x20000000, .length = 0x40000, .kind = .ram },
 
         // EXTFLASH
         MemoryRegion{ .offset = 0x12000000, .length = 0x8000000, .kind = .flash },
+
         // CODE_RAM
         MemoryRegion{ .offset = 0x800000, .length = 0x40000, .kind = .ram },
     },
@@ -29,13 +27,10 @@ pub const nrf52840 = Chip{
 
 pub const nrf52832 = Chip{
     .name = "nrf52",
-    .source = .{
-        .path = root_dir() ++ "/chips/nrf52.zig",
-    },
-    .json_register_schema = .{
-        .path = root_dir() ++ "/chips.nrf52.json",
-    },
+    .source = .{ .path = root_dir() ++ "/chips/nrf52.zig" },
+    .json_register_schema = .{ .path = root_dir() ++ "/chips.nrf52.json" },
     .cpu = micro.cpus.cortex_m4,
+
     .memory_regions = &.{
         MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash },
         MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram },
diff --git a/src/chips/nrf52.zig b/src/chips/nrf52.zig
index 1e3de3bc8..0f6b36873 100644
--- a/src/chips/nrf52.zig
+++ b/src/chips/nrf52.zig
@@ -104,137 +104,137 @@ pub const devices = struct {
 
         pub const peripherals = struct {
             ///  Factory Information Configuration Registers
-            pub const FICR = @intToPtr(*volatile types.peripherals.FICR, 0x10000000);
+            pub const FICR = @as(*volatile types.peripherals.FICR, @ptrFromInt(0x10000000));
             ///  User Information Configuration Registers
-            pub const UICR = @intToPtr(*volatile types.peripherals.UICR, 0x10001000);
+            pub const UICR = @as(*volatile types.peripherals.UICR, @ptrFromInt(0x10001000));
             ///  Block Protect
-            pub const BPROT = @intToPtr(*volatile types.peripherals.BPROT, 0x40000000);
+            pub const BPROT = @as(*volatile types.peripherals.BPROT, @ptrFromInt(0x40000000));
             ///  Power control
-            pub const POWER = @intToPtr(*volatile types.peripherals.POWER, 0x40000000);
+            pub const POWER = @as(*volatile types.peripherals.POWER, @ptrFromInt(0x40000000));
             ///  Clock control
-            pub const CLOCK = @intToPtr(*volatile types.peripherals.CLOCK, 0x40000000);
+            pub const CLOCK = @as(*volatile types.peripherals.CLOCK, @ptrFromInt(0x40000000));
             ///  2.4 GHz Radio
-            pub const RADIO = @intToPtr(*volatile types.peripherals.RADIO, 0x40001000);
+            pub const RADIO = @as(*volatile types.peripherals.RADIO, @ptrFromInt(0x40001000));
             ///  UART with EasyDMA
-            pub const UARTE0 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40002000);
+            pub const UARTE0 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40002000));
             ///  Universal Asynchronous Receiver/Transmitter
-            pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x40002000);
+            pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40002000));
             ///  Serial Peripheral Interface Master with EasyDMA 0
-            pub const SPIM0 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40003000);
+            pub const SPIM0 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40003000));
             ///  SPI Slave 0
-            pub const SPIS0 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40003000);
+            pub const SPIS0 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40003000));
             ///  I2C compatible Two-Wire Master Interface with EasyDMA 0
-            pub const TWIM0 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40003000);
+            pub const TWIM0 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40003000));
             ///  I2C compatible Two-Wire Slave Interface with EasyDMA 0
-            pub const TWIS0 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40003000);
+            pub const TWIS0 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40003000));
             ///  Serial Peripheral Interface 0
-            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003000);
+            pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40003000));
             ///  I2C compatible Two-Wire Interface 0
-            pub const TWI0 = @intToPtr(*volatile types.peripherals.TWI0, 0x40003000);
+            pub const TWI0 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40003000));
             ///  Serial Peripheral Interface Master with EasyDMA 1
-            pub const SPIM1 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40004000);
+            pub const SPIM1 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40004000));
             ///  SPI Slave 1
-            pub const SPIS1 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40004000);
+            pub const SPIS1 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40004000));
             ///  I2C compatible Two-Wire Master Interface with EasyDMA 1
-            pub const TWIM1 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40004000);
+            pub const TWIM1 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40004000));
             ///  I2C compatible Two-Wire Slave Interface with EasyDMA 1
-            pub const TWIS1 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40004000);
+            pub const TWIS1 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40004000));
             ///  Serial Peripheral Interface 1
-            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40004000);
+            pub const SPI1 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40004000));
             ///  I2C compatible Two-Wire Interface 1
-            pub const TWI1 = @intToPtr(*volatile types.peripherals.TWI0, 0x40004000);
+            pub const TWI1 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40004000));
             ///  NFC-A compatible radio
-            pub const NFCT = @intToPtr(*volatile types.peripherals.NFCT, 0x40005000);
+            pub const NFCT = @as(*volatile types.peripherals.NFCT, @ptrFromInt(0x40005000));
             ///  GPIO Tasks and Events
-            pub const GPIOTE = @intToPtr(*volatile types.peripherals.GPIOTE, 0x40006000);
+            pub const GPIOTE = @as(*volatile types.peripherals.GPIOTE, @ptrFromInt(0x40006000));
             ///  Analog to Digital Converter
-            pub const SAADC = @intToPtr(*volatile types.peripherals.SAADC, 0x40007000);
+            pub const SAADC = @as(*volatile types.peripherals.SAADC, @ptrFromInt(0x40007000));
             ///  Timer/Counter 0
-            pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40008000);
+            pub const TIMER0 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40008000));
             ///  Timer/Counter 1
-            pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40009000);
+            pub const TIMER1 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40009000));
             ///  Timer/Counter 2
-            pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4000a000);
+            pub const TIMER2 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4000a000));
             ///  Real time counter 0
-            pub const RTC0 = @intToPtr(*volatile types.peripherals.RTC0, 0x4000b000);
+            pub const RTC0 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x4000b000));
             ///  Temperature Sensor
-            pub const TEMP = @intToPtr(*volatile types.peripherals.TEMP, 0x4000c000);
+            pub const TEMP = @as(*volatile types.peripherals.TEMP, @ptrFromInt(0x4000c000));
             ///  Random Number Generator
-            pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x4000d000);
+            pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x4000d000));
             ///  AES ECB Mode Encryption
-            pub const ECB = @intToPtr(*volatile types.peripherals.ECB, 0x4000e000);
+            pub const ECB = @as(*volatile types.peripherals.ECB, @ptrFromInt(0x4000e000));
             ///  AES CCM Mode Encryption
-            pub const CCM = @intToPtr(*volatile types.peripherals.CCM, 0x4000f000);
+            pub const CCM = @as(*volatile types.peripherals.CCM, @ptrFromInt(0x4000f000));
             ///  Accelerated Address Resolver
-            pub const AAR = @intToPtr(*volatile types.peripherals.AAR, 0x4000f000);
+            pub const AAR = @as(*volatile types.peripherals.AAR, @ptrFromInt(0x4000f000));
             ///  Watchdog Timer
-            pub const WDT = @intToPtr(*volatile types.peripherals.WDT, 0x40010000);
+            pub const WDT = @as(*volatile types.peripherals.WDT, @ptrFromInt(0x40010000));
             ///  Real time counter 1
-            pub const RTC1 = @intToPtr(*volatile types.peripherals.RTC0, 0x40011000);
+            pub const RTC1 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40011000));
             ///  Quadrature Decoder
-            pub const QDEC = @intToPtr(*volatile types.peripherals.QDEC, 0x40012000);
+            pub const QDEC = @as(*volatile types.peripherals.QDEC, @ptrFromInt(0x40012000));
             ///  Comparator
-            pub const COMP = @intToPtr(*volatile types.peripherals.COMP, 0x40013000);
+            pub const COMP = @as(*volatile types.peripherals.COMP, @ptrFromInt(0x40013000));
             ///  Low Power Comparator
-            pub const LPCOMP = @intToPtr(*volatile types.peripherals.LPCOMP, 0x40013000);
+            pub const LPCOMP = @as(*volatile types.peripherals.LPCOMP, @ptrFromInt(0x40013000));
             ///  Software interrupt 0
-            pub const SWI0 = @intToPtr(*volatile types.peripherals.SWI0, 0x40014000);
+            pub const SWI0 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40014000));
             ///  Event Generator Unit 0
-            pub const EGU0 = @intToPtr(*volatile types.peripherals.EGU0, 0x40014000);
+            pub const EGU0 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40014000));
             ///  Software interrupt 1
-            pub const SWI1 = @intToPtr(*volatile types.peripherals.SWI0, 0x40015000);
+            pub const SWI1 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40015000));
             ///  Event Generator Unit 1
-            pub const EGU1 = @intToPtr(*volatile types.peripherals.EGU0, 0x40015000);
+            pub const EGU1 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40015000));
             ///  Software interrupt 2
-            pub const SWI2 = @intToPtr(*volatile types.peripherals.SWI0, 0x40016000);
+            pub const SWI2 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40016000));
             ///  Event Generator Unit 2
-            pub const EGU2 = @intToPtr(*volatile types.peripherals.EGU0, 0x40016000);
+            pub const EGU2 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40016000));
             ///  Software interrupt 3
-            pub const SWI3 = @intToPtr(*volatile types.peripherals.SWI0, 0x40017000);
+            pub const SWI3 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40017000));
             ///  Event Generator Unit 3
-            pub const EGU3 = @intToPtr(*volatile types.peripherals.EGU0, 0x40017000);
+            pub const EGU3 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40017000));
             ///  Software interrupt 4
-            pub const SWI4 = @intToPtr(*volatile types.peripherals.SWI0, 0x40018000);
+            pub const SWI4 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40018000));
             ///  Event Generator Unit 4
-            pub const EGU4 = @intToPtr(*volatile types.peripherals.EGU0, 0x40018000);
+            pub const EGU4 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40018000));
             ///  Software interrupt 5
-            pub const SWI5 = @intToPtr(*volatile types.peripherals.SWI0, 0x40019000);
+            pub const SWI5 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40019000));
             ///  Event Generator Unit 5
-            pub const EGU5 = @intToPtr(*volatile types.peripherals.EGU0, 0x40019000);
+            pub const EGU5 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40019000));
             ///  Timer/Counter 3
-            pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001a000);
+            pub const TIMER3 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001a000));
             ///  Timer/Counter 4
-            pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001b000);
+            pub const TIMER4 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001b000));
             ///  Pulse Width Modulation Unit 0
-            pub const PWM0 = @intToPtr(*volatile types.peripherals.PWM0, 0x4001c000);
+            pub const PWM0 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4001c000));
             ///  Pulse Density Modulation (Digital Microphone) Interface
-            pub const PDM = @intToPtr(*volatile types.peripherals.PDM, 0x4001d000);
+            pub const PDM = @as(*volatile types.peripherals.PDM, @ptrFromInt(0x4001d000));
             ///  Non Volatile Memory Controller
-            pub const NVMC = @intToPtr(*volatile types.peripherals.NVMC, 0x4001e000);
+            pub const NVMC = @as(*volatile types.peripherals.NVMC, @ptrFromInt(0x4001e000));
             ///  Programmable Peripheral Interconnect
-            pub const PPI = @intToPtr(*volatile types.peripherals.PPI, 0x4001f000);
+            pub const PPI = @as(*volatile types.peripherals.PPI, @ptrFromInt(0x4001f000));
             ///  Memory Watch Unit
-            pub const MWU = @intToPtr(*volatile types.peripherals.MWU, 0x40020000);
+            pub const MWU = @as(*volatile types.peripherals.MWU, @ptrFromInt(0x40020000));
             ///  Pulse Width Modulation Unit 1
-            pub const PWM1 = @intToPtr(*volatile types.peripherals.PWM0, 0x40021000);
+            pub const PWM1 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40021000));
             ///  Pulse Width Modulation Unit 2
-            pub const PWM2 = @intToPtr(*volatile types.peripherals.PWM0, 0x40022000);
+            pub const PWM2 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40022000));
             ///  Serial Peripheral Interface Master with EasyDMA 2
-            pub const SPIM2 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40023000);
+            pub const SPIM2 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40023000));
             ///  SPI Slave 2
-            pub const SPIS2 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40023000);
+            pub const SPIS2 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40023000));
             ///  Serial Peripheral Interface 2
-            pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40023000);
+            pub const SPI2 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40023000));
             ///  Real time counter 2
-            pub const RTC2 = @intToPtr(*volatile types.peripherals.RTC0, 0x40024000);
+            pub const RTC2 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40024000));
             ///  Inter-IC Sound
-            pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x40025000);
+            pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x40025000));
             ///  FPU
-            pub const FPU = @intToPtr(*volatile types.peripherals.FPU, 0x40026000);
+            pub const FPU = @as(*volatile types.peripherals.FPU, @ptrFromInt(0x40026000));
             ///  GPIO Port 1
-            pub const P0 = @intToPtr(*volatile types.peripherals.P0, 0x50000000);
+            pub const P0 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000000));
             ///  System Tick Timer
-            pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010);
+            pub const SysTick = @as(*volatile types.peripherals.SCS.SysTick, @ptrFromInt(0xe000e010));
         };
     };
 };
diff --git a/src/chips/nrf52840.zig b/src/chips/nrf52840.zig
index 8c1ffa2f4..955d043ff 100644
--- a/src/chips/nrf52840.zig
+++ b/src/chips/nrf52840.zig
@@ -112,153 +112,153 @@ pub const devices = struct {
 
         pub const peripherals = struct {
             ///  Factory information configuration registers
-            pub const FICR = @intToPtr(*volatile types.peripherals.FICR, 0x10000000);
+            pub const FICR = @as(*volatile types.peripherals.FICR, @ptrFromInt(0x10000000));
             ///  User information configuration registers
-            pub const UICR = @intToPtr(*volatile types.peripherals.UICR, 0x10001000);
+            pub const UICR = @as(*volatile types.peripherals.UICR, @ptrFromInt(0x10001000));
             ///  Clock control
-            pub const CLOCK = @intToPtr(*volatile types.peripherals.CLOCK, 0x40000000);
+            pub const CLOCK = @as(*volatile types.peripherals.CLOCK, @ptrFromInt(0x40000000));
             ///  Power control
-            pub const POWER = @intToPtr(*volatile types.peripherals.POWER, 0x40000000);
+            pub const POWER = @as(*volatile types.peripherals.POWER, @ptrFromInt(0x40000000));
             ///  2.4 GHz radio
-            pub const RADIO = @intToPtr(*volatile types.peripherals.RADIO, 0x40001000);
+            pub const RADIO = @as(*volatile types.peripherals.RADIO, @ptrFromInt(0x40001000));
             ///  Universal Asynchronous Receiver/Transmitter
-            pub const UART0 = @intToPtr(*volatile types.peripherals.UART0, 0x40002000);
+            pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40002000));
             ///  UART with EasyDMA 0
-            pub const UARTE0 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40002000);
+            pub const UARTE0 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40002000));
             ///  Serial Peripheral Interface 0
-            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003000);
+            pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40003000));
             ///  Serial Peripheral Interface Master with EasyDMA 0
-            pub const SPIM0 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40003000);
+            pub const SPIM0 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40003000));
             ///  SPI Slave 0
-            pub const SPIS0 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40003000);
+            pub const SPIS0 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40003000));
             ///  I2C compatible Two-Wire Interface 0
-            pub const TWI0 = @intToPtr(*volatile types.peripherals.TWI0, 0x40003000);
+            pub const TWI0 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40003000));
             ///  I2C compatible Two-Wire Master Interface with EasyDMA 0
-            pub const TWIM0 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40003000);
+            pub const TWIM0 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40003000));
             ///  I2C compatible Two-Wire Slave Interface with EasyDMA 0
-            pub const TWIS0 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40003000);
+            pub const TWIS0 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40003000));
             ///  Serial Peripheral Interface 1
-            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40004000);
+            pub const SPI1 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40004000));
             ///  Serial Peripheral Interface Master with EasyDMA 1
-            pub const SPIM1 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40004000);
+            pub const SPIM1 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40004000));
             ///  SPI Slave 1
-            pub const SPIS1 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40004000);
+            pub const SPIS1 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40004000));
             ///  I2C compatible Two-Wire Interface 1
-            pub const TWI1 = @intToPtr(*volatile types.peripherals.TWI0, 0x40004000);
+            pub const TWI1 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40004000));
             ///  I2C compatible Two-Wire Master Interface with EasyDMA 1
-            pub const TWIM1 = @intToPtr(*volatile types.peripherals.TWIM0, 0x40004000);
+            pub const TWIM1 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40004000));
             ///  I2C compatible Two-Wire Slave Interface with EasyDMA 1
-            pub const TWIS1 = @intToPtr(*volatile types.peripherals.TWIS0, 0x40004000);
+            pub const TWIS1 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40004000));
             ///  NFC-A compatible radio
-            pub const NFCT = @intToPtr(*volatile types.peripherals.NFCT, 0x40005000);
+            pub const NFCT = @as(*volatile types.peripherals.NFCT, @ptrFromInt(0x40005000));
             ///  GPIO Tasks and Events
-            pub const GPIOTE = @intToPtr(*volatile types.peripherals.GPIOTE, 0x40006000);
+            pub const GPIOTE = @as(*volatile types.peripherals.GPIOTE, @ptrFromInt(0x40006000));
             ///  Successive approximation register (SAR) analog-to-digital converter
-            pub const SAADC = @intToPtr(*volatile types.peripherals.SAADC, 0x40007000);
+            pub const SAADC = @as(*volatile types.peripherals.SAADC, @ptrFromInt(0x40007000));
             ///  Timer/Counter 0
-            pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40008000);
+            pub const TIMER0 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40008000));
             ///  Timer/Counter 1
-            pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40009000);
+            pub const TIMER1 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40009000));
             ///  Timer/Counter 2
-            pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4000a000);
+            pub const TIMER2 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4000a000));
             ///  Real time counter 0
-            pub const RTC0 = @intToPtr(*volatile types.peripherals.RTC0, 0x4000b000);
+            pub const RTC0 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x4000b000));
             ///  Temperature Sensor
-            pub const TEMP = @intToPtr(*volatile types.peripherals.TEMP, 0x4000c000);
+            pub const TEMP = @as(*volatile types.peripherals.TEMP, @ptrFromInt(0x4000c000));
             ///  Random Number Generator
-            pub const RNG = @intToPtr(*volatile types.peripherals.RNG, 0x4000d000);
+            pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x4000d000));
             ///  AES ECB Mode Encryption
-            pub const ECB = @intToPtr(*volatile types.peripherals.ECB, 0x4000e000);
+            pub const ECB = @as(*volatile types.peripherals.ECB, @ptrFromInt(0x4000e000));
             ///  Accelerated Address Resolver
-            pub const AAR = @intToPtr(*volatile types.peripherals.AAR, 0x4000f000);
+            pub const AAR = @as(*volatile types.peripherals.AAR, @ptrFromInt(0x4000f000));
             ///  AES CCM Mode Encryption
-            pub const CCM = @intToPtr(*volatile types.peripherals.CCM, 0x4000f000);
+            pub const CCM = @as(*volatile types.peripherals.CCM, @ptrFromInt(0x4000f000));
             ///  Watchdog Timer
-            pub const WDT = @intToPtr(*volatile types.peripherals.WDT, 0x40010000);
+            pub const WDT = @as(*volatile types.peripherals.WDT, @ptrFromInt(0x40010000));
             ///  Real time counter 1
-            pub const RTC1 = @intToPtr(*volatile types.peripherals.RTC0, 0x40011000);
+            pub const RTC1 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40011000));
             ///  Quadrature Decoder
-            pub const QDEC = @intToPtr(*volatile types.peripherals.QDEC, 0x40012000);
+            pub const QDEC = @as(*volatile types.peripherals.QDEC, @ptrFromInt(0x40012000));
             ///  Comparator
-            pub const COMP = @intToPtr(*volatile types.peripherals.COMP, 0x40013000);
+            pub const COMP = @as(*volatile types.peripherals.COMP, @ptrFromInt(0x40013000));
             ///  Low Power Comparator
-            pub const LPCOMP = @intToPtr(*volatile types.peripherals.LPCOMP, 0x40013000);
+            pub const LPCOMP = @as(*volatile types.peripherals.LPCOMP, @ptrFromInt(0x40013000));
             ///  Event Generator Unit 0
-            pub const EGU0 = @intToPtr(*volatile types.peripherals.EGU0, 0x40014000);
+            pub const EGU0 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40014000));
             ///  Software interrupt 0
-            pub const SWI0 = @intToPtr(*volatile types.peripherals.SWI0, 0x40014000);
+            pub const SWI0 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40014000));
             ///  Event Generator Unit 1
-            pub const EGU1 = @intToPtr(*volatile types.peripherals.EGU0, 0x40015000);
+            pub const EGU1 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40015000));
             ///  Software interrupt 1
-            pub const SWI1 = @intToPtr(*volatile types.peripherals.SWI0, 0x40015000);
+            pub const SWI1 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40015000));
             ///  Event Generator Unit 2
-            pub const EGU2 = @intToPtr(*volatile types.peripherals.EGU0, 0x40016000);
+            pub const EGU2 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40016000));
             ///  Software interrupt 2
-            pub const SWI2 = @intToPtr(*volatile types.peripherals.SWI0, 0x40016000);
+            pub const SWI2 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40016000));
             ///  Event Generator Unit 3
-            pub const EGU3 = @intToPtr(*volatile types.peripherals.EGU0, 0x40017000);
+            pub const EGU3 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40017000));
             ///  Software interrupt 3
-            pub const SWI3 = @intToPtr(*volatile types.peripherals.SWI0, 0x40017000);
+            pub const SWI3 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40017000));
             ///  Event Generator Unit 4
-            pub const EGU4 = @intToPtr(*volatile types.peripherals.EGU0, 0x40018000);
+            pub const EGU4 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40018000));
             ///  Software interrupt 4
-            pub const SWI4 = @intToPtr(*volatile types.peripherals.SWI0, 0x40018000);
+            pub const SWI4 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40018000));
             ///  Event Generator Unit 5
-            pub const EGU5 = @intToPtr(*volatile types.peripherals.EGU0, 0x40019000);
+            pub const EGU5 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40019000));
             ///  Software interrupt 5
-            pub const SWI5 = @intToPtr(*volatile types.peripherals.SWI0, 0x40019000);
+            pub const SWI5 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40019000));
             ///  Timer/Counter 3
-            pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001a000);
+            pub const TIMER3 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001a000));
             ///  Timer/Counter 4
-            pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER0, 0x4001b000);
+            pub const TIMER4 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001b000));
             ///  Pulse width modulation unit 0
-            pub const PWM0 = @intToPtr(*volatile types.peripherals.PWM0, 0x4001c000);
+            pub const PWM0 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4001c000));
             ///  Pulse Density Modulation (Digital Microphone) Interface
-            pub const PDM = @intToPtr(*volatile types.peripherals.PDM, 0x4001d000);
+            pub const PDM = @as(*volatile types.peripherals.PDM, @ptrFromInt(0x4001d000));
             ///  Access control lists
-            pub const ACL = @intToPtr(*volatile types.peripherals.ACL, 0x4001e000);
+            pub const ACL = @as(*volatile types.peripherals.ACL, @ptrFromInt(0x4001e000));
             ///  Non Volatile Memory Controller
-            pub const NVMC = @intToPtr(*volatile types.peripherals.NVMC, 0x4001e000);
+            pub const NVMC = @as(*volatile types.peripherals.NVMC, @ptrFromInt(0x4001e000));
             ///  Programmable Peripheral Interconnect
-            pub const PPI = @intToPtr(*volatile types.peripherals.PPI, 0x4001f000);
+            pub const PPI = @as(*volatile types.peripherals.PPI, @ptrFromInt(0x4001f000));
             ///  Memory Watch Unit
-            pub const MWU = @intToPtr(*volatile types.peripherals.MWU, 0x40020000);
+            pub const MWU = @as(*volatile types.peripherals.MWU, @ptrFromInt(0x40020000));
             ///  Pulse width modulation unit 1
-            pub const PWM1 = @intToPtr(*volatile types.peripherals.PWM0, 0x40021000);
+            pub const PWM1 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40021000));
             ///  Pulse width modulation unit 2
-            pub const PWM2 = @intToPtr(*volatile types.peripherals.PWM0, 0x40022000);
+            pub const PWM2 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40022000));
             ///  Serial Peripheral Interface 2
-            pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40023000);
+            pub const SPI2 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40023000));
             ///  Serial Peripheral Interface Master with EasyDMA 2
-            pub const SPIM2 = @intToPtr(*volatile types.peripherals.SPIM0, 0x40023000);
+            pub const SPIM2 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40023000));
             ///  SPI Slave 2
-            pub const SPIS2 = @intToPtr(*volatile types.peripherals.SPIS0, 0x40023000);
+            pub const SPIS2 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40023000));
             ///  Real time counter 2
-            pub const RTC2 = @intToPtr(*volatile types.peripherals.RTC0, 0x40024000);
+            pub const RTC2 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40024000));
             ///  Inter-IC Sound
-            pub const I2S = @intToPtr(*volatile types.peripherals.I2S, 0x40025000);
+            pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x40025000));
             ///  FPU
-            pub const FPU = @intToPtr(*volatile types.peripherals.FPU, 0x40026000);
+            pub const FPU = @as(*volatile types.peripherals.FPU, @ptrFromInt(0x40026000));
             ///  Universal serial bus device
-            pub const USBD = @intToPtr(*volatile types.peripherals.USBD, 0x40027000);
+            pub const USBD = @as(*volatile types.peripherals.USBD, @ptrFromInt(0x40027000));
             ///  UART with EasyDMA 1
-            pub const UARTE1 = @intToPtr(*volatile types.peripherals.UARTE0, 0x40028000);
+            pub const UARTE1 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40028000));
             ///  External flash interface
-            pub const QSPI = @intToPtr(*volatile types.peripherals.QSPI, 0x40029000);
+            pub const QSPI = @as(*volatile types.peripherals.QSPI, @ptrFromInt(0x40029000));
             ///  Pulse width modulation unit 3
-            pub const PWM3 = @intToPtr(*volatile types.peripherals.PWM0, 0x4002d000);
+            pub const PWM3 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4002d000));
             ///  Serial Peripheral Interface Master with EasyDMA 3
-            pub const SPIM3 = @intToPtr(*volatile types.peripherals.SPIM0, 0x4002f000);
+            pub const SPIM3 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x4002f000));
             ///  GPIO Port 1
-            pub const P0 = @intToPtr(*volatile types.peripherals.P0, 0x50000000);
+            pub const P0 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000000));
             ///  GPIO Port 2
-            pub const P1 = @intToPtr(*volatile types.peripherals.P0, 0x50000300);
+            pub const P1 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000300));
             ///  CRYPTOCELL HOST_RGF interface
-            pub const CC_HOST_RGF = @intToPtr(*volatile types.peripherals.CC_HOST_RGF, 0x5002a000);
+            pub const CC_HOST_RGF = @as(*volatile types.peripherals.CC_HOST_RGF, @ptrFromInt(0x5002a000));
             ///  ARM TrustZone CryptoCell register interface
-            pub const CRYPTOCELL = @intToPtr(*volatile types.peripherals.CRYPTOCELL, 0x5002a000);
+            pub const CRYPTOCELL = @as(*volatile types.peripherals.CRYPTOCELL, @ptrFromInt(0x5002a000));
             ///  System Tick Timer
-            pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010);
+            pub const SysTick = @as(*volatile types.peripherals.SCS.SysTick, @ptrFromInt(0xe000e010));
         };
     };
 };

From 081683a4518f173e3ce7e7886fbbf39939ce4aaf Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sat, 26 Aug 2023 18:09:30 +0200
Subject: [PATCH 193/286] Update to zig-0.11.0 (#24)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-authored-by: Felix "xq" Queißner 
---
 .buildkite/pipeline.yml     |  4 ----
 .github/workflows/build.yml | 19 +++++++++++++++++++
 .gitmodules                 |  3 ---
 build.zig                   |  8 +-------
 build.zig.zon               | 10 ++++++++++
 deps/microzig               |  1 -
 src/boards.zig              |  2 +-
 src/chips.zig               |  2 +-
 src/chips/ATmega328P.zig    | 34 +++++++++++++++++-----------------
 src/hals/ATmega328P.zig     | 16 ++++++++--------
 10 files changed, 57 insertions(+), 42 deletions(-)
 delete mode 100644 .buildkite/pipeline.yml
 create mode 100644 .github/workflows/build.yml
 create mode 100644 build.zig.zon
 delete mode 160000 deps/microzig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
deleted file mode 100644
index 24d964669..000000000
--- a/.buildkite/pipeline.yml
+++ /dev/null
@@ -1,4 +0,0 @@
-steps:
-  - group: Build
-    steps:
-    - command: zig build -Doptimize=ReleaseSmall
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
new file mode 100644
index 000000000..63ea5331c
--- /dev/null
+++ b/.github/workflows/build.yml
@@ -0,0 +1,19 @@
+name: Build
+on:
+  push:
+
+jobs:
+  build:
+    runs-on: ${{ matrix.os }}
+    strategy:
+      matrix:
+        os: [ubuntu-latest, windows-latest, macos-latest]
+        optimize: [Debug, ReleaseSmall, ReleaseFast, ReleaseSafe]
+    steps:
+      - uses: actions/checkout@v2
+      - uses: goto-bus-stop/setup-zig@v2.1.1
+        with:
+          version: 0.11.0
+
+      - name: Build
+        run: zig build install "-Doptimize=${{matrix.optimize}}"
diff --git a/.gitmodules b/.gitmodules
index 32e895ccb..e69de29bb 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +0,0 @@
-[submodule "deps/microzig"]
-	path = deps/microzig
-	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/build.zig b/build.zig
index 56ed4e58a..dd84d30ca 100644
--- a/build.zig
+++ b/build.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/build.zig");
+const microzig = @import("microzig");
 
 pub const boards = @import("src/boards.zig");
 pub const chips = @import("src/chips.zig");
@@ -7,9 +7,6 @@ pub const chips = @import("src/chips.zig");
 pub fn build(b: *std.build.Builder) void {
     const optimize = b.standardOptimizeOption(.{});
     inline for (@typeInfo(boards).Struct.decls) |decl| {
-        if (!decl.is_pub)
-            continue;
-
         const exe = microzig.addEmbeddedExecutable(b, .{
             .name = @field(boards, decl.name).name ++ ".minimal",
             .source_file = .{
@@ -22,9 +19,6 @@ pub fn build(b: *std.build.Builder) void {
     }
 
     inline for (@typeInfo(chips).Struct.decls) |decl| {
-        if (!decl.is_pub)
-            continue;
-
         const exe = microzig.addEmbeddedExecutable(b, .{
             .name = @field(chips, decl.name).name ++ ".minimal",
             .source_file = .{
diff --git a/build.zig.zon b/build.zig.zon
new file mode 100644
index 000000000..e8787ef0b
--- /dev/null
+++ b/build.zig.zon
@@ -0,0 +1,10 @@
+.{
+    .name = "microzig-espressif-esp",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
+            .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
+        },
+    },
+}
diff --git a/deps/microzig b/deps/microzig
deleted file mode 160000
index 9392fe0f7..000000000
--- a/deps/microzig
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791
diff --git a/src/boards.zig b/src/boards.zig
index 55fc2208e..0691ab575 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const micro = @import("../deps/microzig/build.zig");
+const micro = @import("microzig");
 const chips = @import("chips.zig");
 
 fn root_dir() []const u8 {
diff --git a/src/chips.zig b/src/chips.zig
index cc7816b83..a1c7d58f2 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const micro = @import("../deps/microzig/build.zig");
+const micro = @import("microzig");
 const Chip = micro.Chip;
 const MemoryRegion = micro.MemoryRegion;
 
diff --git a/src/chips/ATmega328P.zig b/src/chips/ATmega328P.zig
index 604b37fec..6ea04102c 100644
--- a/src/chips/ATmega328P.zig
+++ b/src/chips/ATmega328P.zig
@@ -67,39 +67,39 @@ pub const devices = struct {
 
         pub const peripherals = struct {
             ///  Fuses
-            pub const FUSE = @intToPtr(*volatile types.peripherals.FUSE, 0x0);
+            pub const FUSE = @as(*volatile types.peripherals.FUSE, @ptrFromInt(0x0));
             ///  Lockbits
-            pub const LOCKBIT = @intToPtr(*volatile types.peripherals.LOCKBIT, 0x0);
+            pub const LOCKBIT = @as(*volatile types.peripherals.LOCKBIT, @ptrFromInt(0x0));
             ///  I/O Port
-            pub const PORTB = @intToPtr(*volatile types.peripherals.PORT.PORTB, 0x23);
+            pub const PORTB = @as(*volatile types.peripherals.PORT.PORTB, @ptrFromInt(0x23));
             ///  I/O Port
-            pub const PORTC = @intToPtr(*volatile types.peripherals.PORT.PORTC, 0x26);
+            pub const PORTC = @as(*volatile types.peripherals.PORT.PORTC, @ptrFromInt(0x26));
             ///  I/O Port
-            pub const PORTD = @intToPtr(*volatile types.peripherals.PORT.PORTD, 0x29);
+            pub const PORTD = @as(*volatile types.peripherals.PORT.PORTD, @ptrFromInt(0x29));
             ///  Timer/Counter, 8-bit
-            pub const TC0 = @intToPtr(*volatile types.peripherals.TC8.TC0, 0x35);
+            pub const TC0 = @as(*volatile types.peripherals.TC8.TC0, @ptrFromInt(0x35));
             ///  Timer/Counter, 16-bit
-            pub const TC1 = @intToPtr(*volatile types.peripherals.TC16.TC1, 0x36);
+            pub const TC1 = @as(*volatile types.peripherals.TC16.TC1, @ptrFromInt(0x36));
             ///  Timer/Counter, 8-bit Async
-            pub const TC2 = @intToPtr(*volatile types.peripherals.TC8_ASYNC.TC2, 0x37);
+            pub const TC2 = @as(*volatile types.peripherals.TC8_ASYNC.TC2, @ptrFromInt(0x37));
             ///  External Interrupts
-            pub const EXINT = @intToPtr(*volatile types.peripherals.EXINT, 0x3b);
+            pub const EXINT = @as(*volatile types.peripherals.EXINT, @ptrFromInt(0x3b));
             ///  CPU Registers
-            pub const CPU = @intToPtr(*volatile types.peripherals.CPU, 0x3e);
+            pub const CPU = @as(*volatile types.peripherals.CPU, @ptrFromInt(0x3e));
             ///  EEPROM
-            pub const EEPROM = @intToPtr(*volatile types.peripherals.EEPROM, 0x3f);
+            pub const EEPROM = @as(*volatile types.peripherals.EEPROM, @ptrFromInt(0x3f));
             ///  Serial Peripheral Interface
-            pub const SPI = @intToPtr(*volatile types.peripherals.SPI, 0x4c);
+            pub const SPI = @as(*volatile types.peripherals.SPI, @ptrFromInt(0x4c));
             ///  Analog Comparator
-            pub const AC = @intToPtr(*volatile types.peripherals.AC, 0x50);
+            pub const AC = @as(*volatile types.peripherals.AC, @ptrFromInt(0x50));
             ///  Watchdog Timer
-            pub const WDT = @intToPtr(*volatile types.peripherals.WDT, 0x60);
+            pub const WDT = @as(*volatile types.peripherals.WDT, @ptrFromInt(0x60));
             ///  Analog-to-Digital Converter
-            pub const ADC = @intToPtr(*volatile types.peripherals.ADC, 0x78);
+            pub const ADC = @as(*volatile types.peripherals.ADC, @ptrFromInt(0x78));
             ///  Two Wire Serial Interface
-            pub const TWI = @intToPtr(*volatile types.peripherals.TWI, 0xb8);
+            pub const TWI = @as(*volatile types.peripherals.TWI, @ptrFromInt(0xb8));
             ///  USART
-            pub const USART0 = @intToPtr(*volatile types.peripherals.USART.USART0, 0xc0);
+            pub const USART0 = @as(*volatile types.peripherals.USART.USART0, @ptrFromInt(0xc0));
         };
     };
 };
diff --git a/src/hals/ATmega328P.zig b/src/hals/ATmega328P.zig
index 6e4ef9400..b74e6a9f8 100644
--- a/src/hals/ATmega328P.zig
+++ b/src/hals/ATmega328P.zig
@@ -34,14 +34,14 @@ pub const gpio = struct {
     fn regs(comptime desc: type) type {
         return struct {
             // io address
-            const pin_addr: u5 = 3 * @enumToInt(desc.port) + 0x00;
-            const dir_addr: u5 = 3 * @enumToInt(desc.port) + 0x01;
-            const port_addr: u5 = 3 * @enumToInt(desc.port) + 0x02;
+            const pin_addr: u5 = 3 * @intFromEnum(desc.port) + 0x00;
+            const dir_addr: u5 = 3 * @intFromEnum(desc.port) + 0x01;
+            const port_addr: u5 = 3 * @intFromEnum(desc.port) + 0x02;
 
             // ram mapping
-            const pin = @intToPtr(*volatile u8, 0x20 + @as(usize, pin_addr));
-            const dir = @intToPtr(*volatile u8, 0x20 + @as(usize, dir_addr));
-            const port = @intToPtr(*volatile u8, 0x20 + @as(usize, port_addr));
+            const pin = @as(*volatile u8, @ptrFromInt(0x20 + @as(usize, pin_addr)));
+            const dir = @as(*volatile u8, @ptrFromInt(0x20 + @as(usize, dir_addr)));
+            const port = @as(*volatile u8, @ptrFromInt(0x20 + @as(usize, port_addr)));
         };
     }
 
@@ -147,7 +147,7 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
             USART0.UCSR0B.write(.{
                 .TXB80 = 0, // we don't care about these btw
                 .RXB80 = 0, // we don't care about these btw
-                .UCSZ02 = @truncate(u1, (ucsz & 0x04) >> 2),
+                .UCSZ02 = @as(u1, @truncate((ucsz & 0x04) >> 2)),
                 .TXEN0 = 1,
                 .RXEN0 = 1,
                 .UDRIE0 = 0, // no interrupts
@@ -156,7 +156,7 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
             });
             USART0.UCSR0C.write(.{
                 .UCPOL0 = 0, // async mode
-                .UCSZ0 = @truncate(u2, (ucsz & 0x03) >> 0),
+                .UCSZ0 = @as(u2, @truncate((ucsz & 0x03) >> 0)),
                 .USBS0 = usbs,
                 .UPM0 = upm,
                 .UMSEL0 = umsel,

From 8885309e9c1f22425dca58f67afb315fdeb0e226 Mon Sep 17 00:00:00 2001
From: DEADBLACKCLOVER 
Date: Mon, 28 Aug 2023 00:36:35 +0700
Subject: [PATCH 194/286] Fix perform-flash.sh (#27)

---
 perform-flash.sh | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/perform-flash.sh b/perform-flash.sh
index ce1f5de72..f7bc87ddb 100755
--- a/perform-flash.sh
+++ b/perform-flash.sh
@@ -3,11 +3,11 @@
 set -e
 
 clear
-zig build -Drelease-small
+zig build -Doptimize=ReleaseSmall
 llvm-objdump -S ./zig-out/bin/esp-bringup > /tmp/dump.txt
 esptool.py \
   --port /dev/ttyUSB0 \
   --baud 115200 \
-  write_flash 0x00000000 zig-out/bin/firmware.bin \
+  write_flash 0x00000000 zig-out/firmware/blinky.bin \
   --verify
 picocom --baud 115200 /dev/ttyUSB0
\ No newline at end of file

From 2a0c0ff2814a716a163822211c2686d84801a97a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Tue, 12 Sep 2023 23:06:26 +0200
Subject: [PATCH 195/286] Implements proper support for different stage2
 bootloaders (#80)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-authored-by: Felix "xq" Queißner 
---
 README.adoc                              |    8 +
 build.zig                                |  153 ++-
 src/boards.zig                           |   64 +-
 src/boards/raspberry_pi_pico.zig         |   39 +-
 src/boards/shared/bootrom.zig            |   41 +
 src/boards/waveshare_rp2040_eth.zig      |    5 +
 src/boards/waveshare_rp2040_matrix.zig   |    5 +
 src/boards/waveshare_rp2040_plus_16m.zig |    5 +
 src/boards/waveshare_rp2040_plus_4m.zig  |    5 +
 src/bootroms/at25sf128a.S                |  278 ++++++
 src/bootroms/generic_03h.S               |   98 ++
 src/bootroms/is25lp080.S                 |  256 +++++
 src/bootroms/legacy.S                    |   26 +
 src/bootroms/shared/addressmap.h         |   73 ++
 src/bootroms/shared/asm_helper.S         |   41 +
 src/bootroms/shared/exit_from_boot2.S    |   28 +
 src/bootroms/shared/m0plus.h             | 1149 ++++++++++++++++++++++
 src/bootroms/shared/pads_qspi.h          |  454 +++++++++
 src/bootroms/shared/read_flash_sreg.S    |   30 +
 src/bootroms/shared/regs.h               |   11 +
 src/bootroms/shared/ssi.h                |  809 +++++++++++++++
 src/bootroms/shared/stage2.ld            |   31 +
 src/bootroms/shared/wait_ssi_ready.S     |   26 +
 src/bootroms/w25q080.S                   |  280 ++++++
 src/bootroms/w25x10cl.S                  |  191 ++++
 25 files changed, 4041 insertions(+), 65 deletions(-)
 create mode 100644 src/boards/shared/bootrom.zig
 create mode 100644 src/boards/waveshare_rp2040_eth.zig
 create mode 100644 src/boards/waveshare_rp2040_matrix.zig
 create mode 100644 src/boards/waveshare_rp2040_plus_16m.zig
 create mode 100644 src/boards/waveshare_rp2040_plus_4m.zig
 create mode 100644 src/bootroms/at25sf128a.S
 create mode 100644 src/bootroms/generic_03h.S
 create mode 100644 src/bootroms/is25lp080.S
 create mode 100644 src/bootroms/legacy.S
 create mode 100644 src/bootroms/shared/addressmap.h
 create mode 100644 src/bootroms/shared/asm_helper.S
 create mode 100644 src/bootroms/shared/exit_from_boot2.S
 create mode 100644 src/bootroms/shared/m0plus.h
 create mode 100644 src/bootroms/shared/pads_qspi.h
 create mode 100644 src/bootroms/shared/read_flash_sreg.S
 create mode 100644 src/bootroms/shared/regs.h
 create mode 100644 src/bootroms/shared/ssi.h
 create mode 100644 src/bootroms/shared/stage2.ld
 create mode 100644 src/bootroms/shared/wait_ssi_ready.S
 create mode 100644 src/bootroms/w25q080.S
 create mode 100644 src/bootroms/w25x10cl.S

diff --git a/README.adoc b/README.adoc
index 38c63c607..c31cb3dd8 100644
--- a/README.adoc
+++ b/README.adoc
@@ -5,3 +5,11 @@ HAL and register definitions for the RP2040.
 == What version of Zig to use
 
 0.11.0
+
+== Supported devices ==
+
+- Raspberry Pi Pico
+- (*experimental*) Waveshare RP2040-Plus (4M Flash)
+- (*experimental*) Waveshare RP2040-Plus (16M Flash)
+- (*experimental*) Waveshare RP2040-ETH Mini
+- (*experimental*) Waveshare RP2040-Matrix
diff --git a/build.zig b/build.zig
index dacb22471..1d4dd3c58 100644
--- a/build.zig
+++ b/build.zig
@@ -1,43 +1,121 @@
 const std = @import("std");
-const Builder = std.build.Builder;
-const Pkg = std.build.Pkg;
+const Build = std.Build;
 const comptimePrint = std.fmt.comptimePrint;
-const LazyPath = std.build.LazyPath;
 
 const microzig = @import("microzig");
 
 pub const chips = @import("src/chips.zig");
 pub const boards = @import("src/boards.zig");
 
-const linkerscript_path = root() ++ "rp2040.ld";
+const build_root = root();
 
-pub const BuildOptions = struct {
-    optimize: std.builtin.OptimizeMode,
+const linkerscript_path = build_root ++ "/rp2040.ld";
+
+pub const BootROM = union(enum) {
+    artifact: *std.build.CompileStep, // provide a custom startup code
+    blob: std.build.LazyPath, // just include a binary blob
+
+    // Pre-shipped ones:
+    at25sf128a,
+    generic_03h,
+    is25lp080,
+    w25q080,
+    w25x10cl,
+
+    // Use the old stage2 bootloader vendored with MicroZig till 2023-09-13
+    legacy,
 };
 
 pub const PicoExecutableOptions = struct {
     name: []const u8,
-    source_file: LazyPath,
+    source_file: std.Build.LazyPath,
     optimize: std.builtin.OptimizeMode = .Debug,
+
+    board: boards.Board = boards.raspberry_pi_pico,
+
+    bootrom: ?BootROM = null,
 };
 
-pub fn addPiPicoExecutable(
-    builder: *Builder,
+pub const addPiPicoExecutable = addExecutable; // Deprecated, use addExecutable!
+
+pub const Stage2Bootloader = struct {
+    bin: std.Build.LazyPath,
+    elf: ?std.Build.LazyPath,
+};
+
+pub fn getBootrom(b: *Build, rom: BootROM) Stage2Bootloader {
+    const rom_exe = switch (rom) {
+        .artifact => |artifact| artifact,
+        .blob => |blob| return Stage2Bootloader{
+            .bin = blob,
+            .elf = null,
+        },
+
+        else => blk: {
+            var target = chips.rp2040.cpu.target;
+            target.abi = .eabi;
+
+            const rom_path = b.pathFromRoot(b.fmt("{s}/src/bootroms/{s}.S", .{ build_root, @tagName(rom) }));
+
+            const rom_exe = b.addExecutable(.{
+                .name = b.fmt("stage2-{s}", .{@tagName(rom)}),
+                .optimize = .ReleaseSmall,
+                .target = target,
+                .root_source_file = null,
+            });
+            rom_exe.linkage = .static;
+            // rom_exe.pie = false;
+            // rom_exe.force_pic = false;
+            rom_exe.setLinkerScript(.{ .path = build_root ++ "/src/bootroms/shared/stage2.ld" });
+            rom_exe.addAssemblyFile(.{ .path = rom_path });
+
+            break :blk rom_exe;
+        },
+    };
+
+    const rom_objcopy = b.addObjCopy(rom_exe.getEmittedBin(), .{
+        .basename = b.fmt("{s}.bin", .{@tagName(rom)}),
+        .format = .bin,
+    });
+
+    return Stage2Bootloader{
+        .bin = rom_objcopy.getOutput(),
+        .elf = rom_exe.getEmittedBin(),
+    };
+}
+
+pub fn addExecutable(
+    b: *Build,
     opts: PicoExecutableOptions,
 ) *microzig.EmbeddedExecutable {
-    return microzig.addEmbeddedExecutable(builder, .{
+    var exe = microzig.addEmbeddedExecutable(b, .{
         .name = opts.name,
         .source_file = opts.source_file,
-        .backing = .{ .board = boards.raspberry_pi_pico },
+        .backing = .{ .board = opts.board.inner },
         .optimize = opts.optimize,
         .linkerscript_source_file = .{ .path = linkerscript_path },
     });
+
+    const i: *std.Build.CompileStep = exe.inner;
+
+    const bootrom_file = getBootrom(b, opts.bootrom orelse opts.board.bootrom);
+
+    // HACK: Inject the file as a dependency to MicroZig.board
+    i.modules.get("microzig").?.dependencies.get("board").?.dependencies.put(
+        "bootloader",
+        b.createModule(.{
+            .source_file = bootrom_file.bin,
+        }),
+    ) catch @panic("oom");
+    bootrom_file.bin.addStepDependencies(&i.step);
+
+    return exe;
 }
 
 // this build script is mostly for testing and verification of this
 // package. In an attempt to modularize -- designing for a case where a
 // project requires multiple HALs, it accepts microzig as a param
-pub fn build(b: *Builder) !void {
+pub fn build(b: *Build) !void {
     const optimize = b.standardOptimizeOption(.{});
 
     const args_dep = b.dependency("args", .{});
@@ -57,15 +135,40 @@ pub fn build(b: *Builder) !void {
     const test_step = b.step("test", "run unit tests");
     test_step.dependOn(&b.addRunArtifact(pio_tests).step);
 
-    const flash_tool = b.addExecutable(.{
-        .name = "rp2040-flash",
-        .optimize = .Debug,
-        .target = .{},
-        .root_source_file = .{ .path = "tools/rp2040-flash.zig" },
-    });
-    flash_tool.addModule("args", args_mod);
+    {
+        const flash_tool = b.addExecutable(.{
+            .name = "rp2040-flash",
+            .optimize = .Debug,
+            .target = .{},
+            .root_source_file = .{ .path = "tools/rp2040-flash.zig" },
+        });
+        flash_tool.addModule("args", args_mod);
 
-    b.installArtifact(flash_tool);
+        b.installArtifact(flash_tool);
+    }
+
+    // Install all bootroms for debugging and CI
+    inline for (comptime std.enums.values(std.meta.Tag(BootROM))) |rom| {
+        if (rom == .artifact or rom == .blob) {
+            continue;
+        }
+
+        if (rom == .is25lp080) {
+            // TODO: https://github.com/ZigEmbeddedGroup/raspberrypi-rp2040/issues/79
+            //  is25lp080.o:(text+0x16): has non-ABS relocation R_ARM_THM_CALL against symbol 'read_flash_sreg'
+            continue;
+        }
+
+        const files = getBootrom(b, rom);
+        if (files.elf) |elf| {
+            b.getInstallStep().dependOn(
+                &b.addInstallFileWithDir(elf, .{ .custom = "stage2" }, b.fmt("{s}.elf", .{@tagName(rom)})).step,
+            );
+        }
+        b.getInstallStep().dependOn(
+            &b.addInstallFileWithDir(files.bin, .{ .custom = "stage2" }, b.fmt("{s}.bin", .{@tagName(rom)})).step,
+        );
+    }
 }
 
 fn root() []const u8 {
@@ -89,12 +192,12 @@ pub const Examples = struct {
     ws2812: *microzig.EmbeddedExecutable,
     random: *microzig.EmbeddedExecutable,
 
-    pub fn init(b: *Builder, optimize: std.builtin.OptimizeMode) Examples {
+    pub fn init(b: *Build, optimize: std.builtin.OptimizeMode) Examples {
         var ret: Examples = undefined;
         inline for (@typeInfo(Examples).Struct.fields) |field| {
             const path = comptime root() ++ "examples/" ++ field.name ++ ".zig";
 
-            @field(ret, field.name) = addPiPicoExecutable(b, .{
+            @field(ret, field.name) = addExecutable(b, .{
                 .name = field.name,
                 .source_file = .{ .path = path },
                 .optimize = optimize,
@@ -104,9 +207,11 @@ pub const Examples = struct {
         return ret;
     }
 
-    pub fn install(examples: *Examples, b: *Builder) void {
+    pub fn install(examples: *Examples, b: *Build) void {
         inline for (@typeInfo(Examples).Struct.fields) |field| {
-            b.installArtifact(@field(examples, field.name).inner);
+            b.getInstallStep().dependOn(
+                &b.addInstallFileWithDir(@field(examples, field.name).inner.getEmittedBin(), .{ .custom = "firmware" }, field.name ++ ".elf").step,
+            );
         }
     }
 };
diff --git a/src/boards.zig b/src/boards.zig
index d2af0ee1e..8f68040ea 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -1,15 +1,69 @@
 const std = @import("std");
 const microzig = @import("microzig");
+const rp2040 = @import("../build.zig");
 const chips = @import("chips.zig");
 
 fn root_dir() []const u8 {
     return std.fs.path.dirname(@src().file) orelse ".";
 }
 
-const board_path = std.fmt.comptimePrint("{s}/boards/raspberry_pi_pico.zig", .{root_dir()});
+fn board_path(comptime path: []const u8) std.Build.LazyPath {
+    return .{
+        .path = std.fmt.comptimePrint("{s}/boards/{s}", .{ root_dir(), path }),
+    };
+}
+
+pub const Board = struct {
+    inner: microzig.Board,
+    bootrom: rp2040.BootROM,
+};
+
+// https://www.raspberrypi.com/products/raspberry-pi-pico/
+pub const raspberry_pi_pico = Board{
+    .inner = .{
+        .name = "Raspberry Pi Pico",
+        .source = board_path("raspberry_pi_pico.zig"),
+        .chip = chips.rp2040,
+    },
+    .bootrom = .w25q080,
+};
+
+// https://www.waveshare.com/rp2040-plus.htm
+pub const waveshare_rp2040_plus_4m = Board{
+    .inner = .{
+        .name = "Waveshare RP2040-Plus (4M Flash)",
+        .source = board_path("waveshare_rp2040_plus_4m.zig"),
+        .chip = chips.rp2040,
+    },
+    .bootrom = .w25q080,
+};
+
+// https://www.waveshare.com/rp2040-plus.htm
+pub const waveshare_rp2040_plus_16m = Board{
+    .inner = .{
+        .name = "Waveshare RP2040-Plus (16M Flash)",
+        .source = board_path("waveshare_rp2040_plus_16m.zig"),
+        .chip = chips.rp2040,
+    },
+    .bootrom = .w25q080,
+};
+
+// https://www.waveshare.com/rp2040-eth.htm
+pub const waveshare_rp2040_eth = Board{
+    .inner = .{
+        .name = "Waveshare RP2040-ETH Mini",
+        .source = board_path("waveshare_rp2040_eth.zig"),
+        .chip = chips.rp2040,
+    },
+    .bootrom = .w25q080,
+};
 
-pub const raspberry_pi_pico = microzig.Board{
-    .name = "Raspberry Pi Pico",
-    .source = .{ .path = board_path },
-    .chip = chips.rp2040,
+// https://www.waveshare.com/rp2040-matrix.htm
+pub const waveshare_rp2040_matrix = Board{
+    .inner = .{
+        .name = "Waveshare RP2040-Matrix",
+        .source = board_path("waveshare_rp2040_matrix.zig"),
+        .chip = chips.rp2040,
+    },
+    .bootrom = .w25q080,
 };
diff --git a/src/boards/raspberry_pi_pico.zig b/src/boards/raspberry_pi_pico.zig
index ca1a9014d..79d848c29 100644
--- a/src/boards/raspberry_pi_pico.zig
+++ b/src/boards/raspberry_pi_pico.zig
@@ -1,38 +1,5 @@
 pub const xosc_freq = 12_000_000;
 
-// TODO: improve interface so that user can use a custom implementation and
-// automatically checksum it.
-pub export const _BOOT2: [256]u8 linksection(".boot2") = [_]u8{
-    0x00, 0xb5, 0x32, 0x4b, 0x21, 0x20, 0x58, 0x60,
-    0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60,
-    0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2e, 0x4b,
-    0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61,
-    0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2b, 0x49,
-    0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20,
-    0x00, 0xf0, 0x44, 0xf8, 0x02, 0x22, 0x90, 0x42,
-    0x14, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0,
-    0x34, 0xf8, 0x19, 0x6e, 0x01, 0x21, 0x19, 0x66,
-    0x00, 0x20, 0x18, 0x66, 0x1a, 0x66, 0x00, 0xf0,
-    0x2c, 0xf8, 0x19, 0x6e, 0x19, 0x6e, 0x19, 0x6e,
-    0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21,
-    0x08, 0x42, 0xf9, 0xd1, 0x00, 0x21, 0x99, 0x60,
-    0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60,
-    0x1a, 0x49, 0x1b, 0x48, 0x01, 0x60, 0x01, 0x21,
-    0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0xa0, 0x21,
-    0x19, 0x66, 0x00, 0xf0, 0x12, 0xf8, 0x00, 0x21,
-    0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60,
-    0x01, 0x21, 0x99, 0x60, 0x01, 0xbc, 0x00, 0x28,
-    0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49,
-    0x08, 0x60, 0x03, 0xc8, 0x80, 0xf3, 0x08, 0x88,
-    0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20,
-    0x01, 0x42, 0xfb, 0xd0, 0x01, 0x20, 0x01, 0x42,
-    0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66,
-    0x18, 0x66, 0xff, 0xf7, 0xf2, 0xff, 0x18, 0x6e,
-    0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40,
-    0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00,
-    0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00,
-    0xf4, 0x00, 0x00, 0x18, 0x22, 0x20, 0x00, 0xa0,
-    0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0,
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-    0x00, 0x00, 0x00, 0x00, 0x74, 0xb2, 0x4e, 0x7a,
-};
+comptime {
+    _ = @import("shared/bootrom.zig");
+}
diff --git a/src/boards/shared/bootrom.zig b/src/boards/shared/bootrom.zig
new file mode 100644
index 000000000..e6e32af6a
--- /dev/null
+++ b/src/boards/shared/bootrom.zig
@@ -0,0 +1,41 @@
+const std = @import("std");
+
+comptime {
+    _ = stage2_bootloader;
+}
+
+export const stage2_bootloader: [256]u8 linksection(".boot2") = prepareBootSector(
+    @embedFile("bootloader"),
+);
+
+/// Create a new 
+fn prepareBootSector(comptime stage2_rom: []const u8) [256]u8 {
+    @setEvalBranchQuota(10_000);
+
+    var bootrom: [256]u8 = .{0xFF} ** 256;
+    @memcpy(bootrom[0..stage2_rom.len], stage2_rom);
+
+    // 2.8.1.3.1. Checksum
+    // The last four bytes of the image loaded from flash (which we hope is a valid flash second stage) are a CRC32 checksum
+    // of the first 252 bytes. The parameters of the checksum are:
+    // • Polynomial: 0x04c11db7
+    // • Input reflection: no
+    // • Output reflection: no
+    // • Initial value: 0xffffffff
+    // • Final XOR: 0x00000000
+    // • Checksum value appears as little-endian integer at end of image
+    // The Bootrom makes 128 attempts of approximately 4ms each for a total of approximately 0.5 seconds before giving up
+    // and dropping into USB code to load and checksum the second stage with varying SPI parameters. If it sees a checksum
+    // pass it will immediately jump into the 252-byte payload which contains the flash second stage.
+    const Hash = std.hash.crc.Crc(u32, .{
+        .polynomial = 0x04c11db7,
+        .initial = 0xffffffff,
+        .reflect_input = false,
+        .reflect_output = false,
+        .xor_output = 0x00000000,
+    });
+
+    std.mem.writeIntLittle(u32, bootrom[252..256], Hash.hash(bootrom[0..252]));
+
+    return bootrom;
+}
diff --git a/src/boards/waveshare_rp2040_eth.zig b/src/boards/waveshare_rp2040_eth.zig
new file mode 100644
index 000000000..79d848c29
--- /dev/null
+++ b/src/boards/waveshare_rp2040_eth.zig
@@ -0,0 +1,5 @@
+pub const xosc_freq = 12_000_000;
+
+comptime {
+    _ = @import("shared/bootrom.zig");
+}
diff --git a/src/boards/waveshare_rp2040_matrix.zig b/src/boards/waveshare_rp2040_matrix.zig
new file mode 100644
index 000000000..79d848c29
--- /dev/null
+++ b/src/boards/waveshare_rp2040_matrix.zig
@@ -0,0 +1,5 @@
+pub const xosc_freq = 12_000_000;
+
+comptime {
+    _ = @import("shared/bootrom.zig");
+}
diff --git a/src/boards/waveshare_rp2040_plus_16m.zig b/src/boards/waveshare_rp2040_plus_16m.zig
new file mode 100644
index 000000000..79d848c29
--- /dev/null
+++ b/src/boards/waveshare_rp2040_plus_16m.zig
@@ -0,0 +1,5 @@
+pub const xosc_freq = 12_000_000;
+
+comptime {
+    _ = @import("shared/bootrom.zig");
+}
diff --git a/src/boards/waveshare_rp2040_plus_4m.zig b/src/boards/waveshare_rp2040_plus_4m.zig
new file mode 100644
index 000000000..79d848c29
--- /dev/null
+++ b/src/boards/waveshare_rp2040_plus_4m.zig
@@ -0,0 +1,5 @@
+pub const xosc_freq = 12_000_000;
+
+comptime {
+    _ = @import("shared/bootrom.zig");
+}
diff --git a/src/bootroms/at25sf128a.S b/src/bootroms/at25sf128a.S
new file mode 100644
index 000000000..f8ecdc901
--- /dev/null
+++ b/src/bootroms/at25sf128a.S
@@ -0,0 +1,278 @@
+// ----------------------------------------------------------------------------
+// Second stage boot code
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device:      Adesto AT25SF128A
+//              Based on W25Q080 code: main difference is the QE bit is being set
+//              via command 0x31
+//
+// Description: Configures AT25SF128A to run in Quad I/O continuous read XIP mode
+//
+// Details:     * Check status register 2 to determine if QSPI mode is enabled,
+//                and perform an SR2 programming cycle if necessary.
+//              * Use SSI to perform a dummy 0xEB read command, with the mode
+//                continuation bits set, so that the flash will not require
+//                0xEB instruction prefix on subsequent reads.
+//              * Configure SSI to write address, mode bits, but no instruction.
+//                SSI + flash are now jointly in a state where continuous reads
+//                can take place.
+//              * Jump to exit pointer passed in via lr. Bootrom passes null,
+//                in which case this code uses a default 256 byte flash offset
+//
+// Building:    * This code must be position-independent, and use stack only
+//              * The code will be padded to a size of 256 bytes, including a
+//                4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "shared/asm_helper.S"
+#include "shared/regs.h"
+
+// ----------------------------------------------------------------------------
+// Config section
+// ----------------------------------------------------------------------------
+// It should be possible to support most flash devices by modifying this section
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be a positive, even integer.
+// The bootrom is very conservative with SPI frequency, but here we should be
+// as aggressive as possible.
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+#if PICO_FLASH_SPI_CLKDIV & 1
+#error PICO_FLASH_SPI_CLKDIV must be even
+#endif
+
+// Define interface width: single/dual/quad IO
+#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
+
+// For W25Q080 this is the "Read data fast quad IO" instruction:
+#define CMD_READ 0xeb
+
+// "Mode bits" are 8 special bits sent immediately after
+// the address bits in a "Read Data Fast Quad I/O" command sequence. 
+// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
+// next read does not require the 0xeb instruction prefix.
+#define MODE_CONTINUOUS_READ 0x20
+
+// The number of address + mode bits, divided by 4 (always 4, not function of
+// interface width).
+#define ADDR_L 8
+
+// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
+// are required.
+#define WAIT_CYCLES 4
+
+// If defined, we will read status reg, compare to SREG_DATA, and overwrite
+// with our value if the SR doesn't match.
+// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to
+// SR2 (31h cmd) as the latter command isn't supported by WX25Q080.
+// This isn't great because it will remove block protections.
+// A better solution is to use a volatile SR write if your device supports it.
+#define PROGRAM_STATUS_REG
+
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS2 0x35
+#define CMD_WRITE_STATUS 0x01
+#define CMD_WRITE_STATUS2 0x31
+#define SREG_DATA 0x02  // Enable quad-SPI mode
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+pico_default_asm_setup
+
+.section .text
+
+// The exit point is passed in lr. If entered from bootrom, this will be the
+// flash address immediately following this second stage (0x10000100).
+// Otherwise it will be a return address -- second stage being called as a
+// function by user code, after copying out of XIP region. r3 holds SSI base,
+// r0...2 used as temporaries. Other GPRs not used.
+regular_func _stage2_boot
+    push {lr}
+
+    // Set pad configuration:
+    // - SCLK 8mA drive, no slew limiting
+    // - SDx disable input Schmitt to reduce delay
+
+    ldr r3, =PADS_QSPI_BASE
+    movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS)
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
+    ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+    movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS
+    bics r0, r1
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
+
+    ldr r3, =XIP_SSI_BASE
+
+    // Disable SSI to allow further config
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Set baud rate
+    movs r1, #PICO_FLASH_SPI_CLKDIV
+    str r1, [r3, #SSI_BAUDR_OFFSET]
+
+    // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
+    // if the flash launches data on SCLK posedge, we capture it at the time that
+    // the next SCLK posedge is launched. This is shortly before that posedge
+    // arrives at the flash, so data hold time should be ok. For
+    // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
+
+    movs r1, #1
+    movs r2, #SSI_RX_SAMPLE_DLY_OFFSET  // == 0xf0 so need 8 bits of offset significance
+    str r1, [r3, r2]
+
+
+// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
+// (i.e. turn WPn and HOLDn into IO2/IO3)
+#ifdef PROGRAM_STATUS_REG
+program_sregs:
+#define CTRL0_SPI_TXRX \
+    (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
+    (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRL0_SPI_TXRX)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+     // Enable SSI and select slave 0
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Check whether SR needs updating
+    movs r0, #CMD_READ_STATUS2
+    bl read_flash_sreg
+    movs r2, #SREG_DATA
+    cmp r0, r2
+    beq skip_sreg_programming
+
+    // Send write enable command
+    movs r1, #CMD_WRITE_ENABLE
+    str r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll for completion and discard RX
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Send status write command followed by data bytes
+    movs r1, #CMD_WRITE_STATUS2
+    str r1, [r3, #SSI_DR0_OFFSET]
+    str r2, [r3, #SSI_DR0_OFFSET]
+
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll status register for write completion
+1:
+    movs r0, #CMD_READ_STATUS
+    bl read_flash_sreg
+    movs r1, #1
+    tst r0, r1
+    bne 1b
+
+skip_sreg_programming:
+
+    // Disable SSI again so that it can be reconfigured
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+#endif
+
+// Currently the flash expects an 8 bit serial command prefix on every
+// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O
+// command, with mode bits set such that the flash will not expect a serial
+// command prefix on *subsequent* transfers. We don't care about the results
+// of the read, the important part is the mode bits.
+
+dummy_read:
+#define CTRLR0_ENTER_XIP \
+    (FRAME_FORMAT                          /* Quad I/O mode */                \
+        << SSI_CTRLR0_SPI_FRF_LSB) |                                          \
+    (31 << SSI_CTRLR0_DFS_32_LSB)  |       /* 32 data bits */                 \
+    (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ     /* Send INST/ADDR, Receive Data */ \
+        << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRLR0_ENTER_XIP)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+    movs r1, #0x0                    // NDF=0 (single 32b read)
+    str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+#define SPI_CTRLR0_ENTER_XIP \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |     /* Address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_8B \
+        << SSI_SPI_CTRLR0_INST_L_LSB) |        /* 8-bit instruction */ \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A      /* Send Command in serial mode then address in Quad I/O mode */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_ENTER_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)  // SPI_CTRL0 Register
+    str r1, [r0]
+
+    movs r1, #1                      // Re-enable SSI
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    movs r1, #CMD_READ
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push SPI command into TX FIFO
+    movs r1, #MODE_CONTINUOUS_READ   // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push Address into TX FIFO - this will trigger the transaction
+
+    // Poll for completion
+    bl wait_ssi_ready
+
+// The flash is in a state where we can blast addresses in parallel, and get
+// parallel data back. Now configure the SSI to translate XIP bus accesses
+// into QSPI transfers of this form.
+
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Disable SSI (and clear FIFO) to allow further config
+
+// Note that the INST_L field is used to select what XIP data gets pushed into
+// the TX FIFO:
+//      INST_L_0_BITS   {ADDR[23:0],XIP_CMD[7:0]}       Load "mode bits" into XIP_CMD
+//      Anything else   {XIP_CMD[7:0],ADDR[23:0]}       Load SPI command into XIP_CMD
+configure_ssi:
+#define SPI_CTRLR0_XIP \
+    (MODE_CONTINUOUS_READ                      /* Mode bits to keep flash in continuous read mode */ \
+        << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |    /* Total number of address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |    /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_NONE          /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
+        << SSI_SPI_CTRLR0_INST_L_LSB) | \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A      /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+    str r1, [r0]
+
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Re-enable SSI
+
+// Bus accesses to the XIP window will now be transparently serviced by the
+// external flash on cache miss. We are ready to run code from flash.
+
+// Pull in standard exit routine
+#include "shared/exit_from_boot2.S"
+
+// Common functions
+#include "shared/wait_ssi_ready.S"
+#ifdef PROGRAM_STATUS_REG
+#include "shared/read_flash_sreg.S"
+#endif
+
+.global literals
+literals:
+.ltorg
+
+.end
diff --git a/src/bootroms/generic_03h.S b/src/bootroms/generic_03h.S
new file mode 100644
index 000000000..1599c7b04
--- /dev/null
+++ b/src/bootroms/generic_03h.S
@@ -0,0 +1,98 @@
+// ----------------------------------------------------------------------------
+// Second stage boot code
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device:      Anything which responds to 03h serial read command
+//
+// Details:     * Configure SSI to translate each APB read into a 03h command
+//              * 8 command clocks, 24 address clocks and 32 data clocks
+//              * This enables you to boot from almost anything: you can pretty
+//                much solder a potato to your PCB, or a piece of cheese
+//              * The tradeoff is performance around 3x worse than QSPI XIP
+//
+// Building:    * This code must be position-independent, and use stack only
+//              * The code will be padded to a size of 256 bytes, including a
+//                4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "shared/asm_helper.S"
+#include "shared/regs.h"
+
+pico_default_asm_setup
+
+// ----------------------------------------------------------------------------
+// Config section
+// ----------------------------------------------------------------------------
+// It should be possible to support most flash devices by modifying this section
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be a positive, even integer.
+// The bootrom is very conservative with SPI frequency, but here we should be
+// as aggressive as possible.
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+
+#define CMD_READ 0x03
+
+// Value is number of address bits divided by 4
+#define ADDR_L 6
+
+#define CTRLR0_XIP \
+    (SSI_CTRLR0_SPI_FRF_VALUE_STD << SSI_CTRLR0_SPI_FRF_LSB) |  /* Standard 1-bit SPI serial frames */ \
+    (31 << SSI_CTRLR0_DFS_32_LSB)  |                            /* 32 clocks per data frame */ \
+    (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ  << SSI_CTRLR0_TMOD_LSB) /* Send instr + addr, receive data */
+
+#define SPI_CTRLR0_XIP \
+    (CMD_READ << SSI_SPI_CTRLR0_XIP_CMD_LSB) |        /* Value of instruction prefix */ \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |           /* Total number of address + mode bits */ \
+    (2 << SSI_SPI_CTRLR0_INST_L_LSB) |                /* 8 bit command prefix (field value is bits divided by 4) */ \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A << SSI_SPI_CTRLR0_TRANS_TYPE_LSB) /* command and address both in serial format */
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+.section .text
+
+regular_func _stage2_boot
+    push {lr}
+
+    ldr r3, =XIP_SSI_BASE                // Use as base address where possible
+
+    // Disable SSI to allow further config
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Set baud rate
+    movs r1, #PICO_FLASH_SPI_CLKDIV
+    str r1, [r3, #SSI_BAUDR_OFFSET]
+
+    ldr r1, =(CTRLR0_XIP)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+    ldr r1, =(SPI_CTRLR0_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+    str r1, [r0]
+
+    // NDF=0 (single 32b read)
+    movs r1, #0x0
+    str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+    // Re-enable SSI
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+// We are now in XIP mode. Any bus accesses to the XIP address window will be
+// translated by the SSI into 03h read commands to the external flash (if cache is missed),
+// and the data will be returned to the bus.
+
+// Pull in standard exit routine
+#include "shared/exit_from_boot2.S"
+
+.global literals
+literals:
+.ltorg
+
+.end
diff --git a/src/bootroms/is25lp080.S b/src/bootroms/is25lp080.S
new file mode 100644
index 000000000..46f8c85a4
--- /dev/null
+++ b/src/bootroms/is25lp080.S
@@ -0,0 +1,256 @@
+// ----------------------------------------------------------------------------
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device:      ISSI IS25LP080D
+//              Based on W25Q080 code: main difference is the QE bit being in
+//              SR1 instead of SR2.
+//
+// Description: Configures IS25LP080D to run in Quad I/O continuous read XIP mode
+//
+// Details:     * Check status register to determine if QSPI mode is enabled,
+//                and perform an SR programming cycle if necessary.
+//              * Use SSI to perform a dummy 0xEB read command, with the mode
+//                continuation bits set, so that the flash will not require
+//                0xEB instruction prefix on subsequent reads.
+//              * Configure SSI to write address, mode bits, but no instruction.
+//                SSI + flash are now jointly in a state where continuous reads
+//                can take place.
+//              * Set VTOR = 0x10000100 (user vector table immediately after
+//                this boot2 image).
+//              * Read stack pointer (MSP) and reset vector from the flash
+//                vector table; set SP and jump, as though the processor had
+//                booted directly from flash.
+//
+// Building:    * This code must be linked to run at 0x20027f00
+//              * The code will be padded to a size of 256 bytes, including a
+//                4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "shared/asm_helper.S"
+#include "shared/regs.h"
+
+// ----------------------------------------------------------------------------
+// Config section
+// ----------------------------------------------------------------------------
+// It should be possible to support most flash devices by modifying this section
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be a positive, even integer.
+// The bootrom is very conservative with SPI frequency, but here we should be
+// as aggressive as possible.
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+
+
+// Define interface width: single/dual/quad IO
+#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
+
+// For W25Q080 this is the "Read data fast quad IO" instruction:
+#define CMD_READ 0xeb
+
+// "Mode bits" are 8 special bits sent immediately after
+// the address bits in a "Read Data Fast Quad I/O" command sequence. 
+// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
+// next read does not require the 0xeb instruction prefix.
+#define MODE_CONTINUOUS_READ 0xa0
+
+// The number of address + mode bits, divided by 4 (always 4, not function of
+// interface width).
+#define ADDR_L 8
+
+// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
+// are required.
+#define WAIT_CYCLES 4
+
+// If defined, we will read status reg, compare to SREG_DATA, and overwrite
+// with our value if the SR doesn't match.
+// This isn't great because it will remove block protections.
+// A better solution is to use a volatile SR write if your device supports it.
+#define PROGRAM_STATUS_REG
+
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_READ_STATUS 0x05
+#define CMD_WRITE_STATUS 0x01
+#define SREG_DATA 0x40  // Enable quad-SPI mode
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+pico_default_asm_setup
+
+.section text
+regular_func _stage2_boot
+    push {lr}
+
+    ldr r3, =XIP_SSI_BASE                // Use as base address where possible
+
+    // Disable SSI to allow further config
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Set baud rate
+    movs r1, #PICO_FLASH_SPI_CLKDIV
+    str r1, [r3, #SSI_BAUDR_OFFSET]
+
+// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
+// (i.e. turn WPn and HOLDn into IO2/IO3)
+#ifdef PROGRAM_STATUS_REG
+program_sregs:
+#define CTRL0_SPI_TXRX \
+    (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
+    (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRL0_SPI_TXRX)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+     // Enable SSI and select slave 0
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Check whether SR needs updating
+    ldr r0, =CMD_READ_STATUS
+    bl read_flash_sreg
+    ldr r2, =SREG_DATA
+    cmp r0, r2
+    beq skip_sreg_programming
+
+    // Send write enable command
+    movs r1, #CMD_WRITE_ENABLE
+    str r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll for completion and discard RX
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Send status write command followed by data bytes
+    movs r1, #CMD_WRITE_STATUS
+    str r1, [r3, #SSI_DR0_OFFSET]
+    movs r0, #0
+    str r2, [r3, #SSI_DR0_OFFSET]
+
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll status register for write completion
+1:
+    ldr r0, =CMD_READ_STATUS
+    bl read_flash_sreg
+    movs r1, #1
+    tst r0, r1
+    bne 1b
+
+skip_sreg_programming:
+
+    // Send a 0xA3 high-performance-mode instruction
+//    ldr r1, =0xa3
+//    str r1, [r3, #SSI_DR0_OFFSET]
+//    bl wait_ssi_ready
+
+    // Disable SSI again so that it can be reconfigured
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+#endif
+
+
+// First we need to send the initial command to get us in to Fast Read Quad I/O
+// mode.  As this transaction requires a command, we can't send it in XIP mode.
+// To enter Continuous Read mode as well we need to append 4'b0010 to the address
+// bits and then add a further 4 don't care bits.  We will construct this by
+// specifying a 28-bit address, with the least significant bits being 4'b0010.
+// This is just a dummy transaction so we'll perform a read from address zero
+// and then discard what comes back.  All we really care about is that at the
+// end of the transaction, the flash device is in Continuous Read mode
+// and from then on will only expect to receive addresses.
+dummy_read:
+#define CTRLR0_ENTER_XIP \
+    (FRAME_FORMAT                          /* Quad I/O mode */                \
+        << SSI_CTRLR0_SPI_FRF_LSB) |                                          \
+    (31 << SSI_CTRLR0_DFS_32_LSB)  |       /* 32 data bits */                 \
+    (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ     /* Send INST/ADDR, Receive Data */ \
+        << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRLR0_ENTER_XIP)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+    movs r1, #0x0                   // NDF=0 (single 32b read)
+    str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+#define SPI_CTRLR0_ENTER_XIP \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |     /* Address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_8B \
+        << SSI_SPI_CTRLR0_INST_L_LSB) |        /* 8-bit instruction */ \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A      /* Send Command in serial mode then address in Quad I/O mode */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_ENTER_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)  // SPI_CTRL0 Register
+    str r1, [r0]
+
+    movs r1, #1                     // Re-enable SSI
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    movs r1, #CMD_READ
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push SPI command into TX FIFO
+    movs r1, #MODE_CONTINUOUS_READ  // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push Address into TX FIFO - this will trigger the transaction
+
+    // Poll for completion
+    bl wait_ssi_ready
+
+// At this point CN# will be deasserted and the SPI clock will not be running.
+// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and
+// only expecting address bits after the next CN# assertion.  So long as we
+// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address
+// then the Winbond device will remain in continuous read mode.  This is the
+// ideal mode for Execute-In-Place.
+// (If we want to exit continuous read mode then we will need to switch back
+// to APM mode and generate a 28-bit address phase with the extra nibble set
+// to 4'b0000).
+
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Disable SSI (and clear FIFO) to allow further config
+
+// Note that the INST_L field is used to select what XIP data gets pushed into
+// the TX FIFO:
+//      INST_L_0_BITS   {ADDR[23:0],XIP_CMD[7:0]}       Load "mode bits" into XIP_CMD
+//      Anything else   {XIP_CMD[7:0],ADDR[23:0]}       Load SPI command into XIP_CMD
+configure_ssi:
+#define SPI_CTRLR0_XIP \
+    (MODE_CONTINUOUS_READ                      /* Mode bits to keep flash in continuous read mode */ \
+        << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |    /* Total number of address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |    /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_NONE          /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
+        << SSI_SPI_CTRLR0_INST_L_LSB) | \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A      /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+    str r1, [r0]
+
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Re-enable SSI
+
+// We are now in XIP mode, with all transactions using Dual I/O and only
+// needing to send 24-bit addresses (plus mode bits) for each read transaction.
+
+// Pull in standard exit routine
+#include "shared/exit_from_boot2.S"
+
+// Common functions
+#include "shared/wait_ssi_ready.S"
+#ifdef PROGRAM_STATUS_REG
+#include "shared/read_flash_sreg.S"
+#endif
+
+.global literals
+literals:
+.ltorg
+
+.end
diff --git a/src/bootroms/legacy.S b/src/bootroms/legacy.S
new file mode 100644
index 000000000..b2870c5e0
--- /dev/null
+++ b/src/bootroms/legacy.S
@@ -0,0 +1,26 @@
+
+// This is the legacy blob we used to ship in 
+// src/boards/raspberry_pi_pico.zig
+// Now it's generic over all boards we have.
+
+.text
+.global _stage2_boot
+_stage2_boot:
+.byte 0x00, 0xb5, 0x32, 0x4b, 0x21, 0x20, 0x58, 0x60, 0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60
+.byte 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2e, 0x4b, 0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61
+.byte 0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2b, 0x49, 0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20
+.byte 0x00, 0xf0, 0x44, 0xf8, 0x02, 0x22, 0x90, 0x42, 0x14, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0
+.byte 0x34, 0xf8, 0x19, 0x6e, 0x01, 0x21, 0x19, 0x66, 0x00, 0x20, 0x18, 0x66, 0x1a, 0x66, 0x00, 0xf0
+.byte 0x2c, 0xf8, 0x19, 0x6e, 0x19, 0x6e, 0x19, 0x6e, 0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21
+.byte 0x08, 0x42, 0xf9, 0xd1, 0x00, 0x21, 0x99, 0x60, 0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60
+.byte 0x1a, 0x49, 0x1b, 0x48, 0x01, 0x60, 0x01, 0x21, 0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0xa0, 0x21
+.byte 0x19, 0x66, 0x00, 0xf0, 0x12, 0xf8, 0x00, 0x21, 0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60
+.byte 0x01, 0x21, 0x99, 0x60, 0x01, 0xbc, 0x00, 0x28, 0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49
+.byte 0x08, 0x60, 0x03, 0xc8, 0x80, 0xf3, 0x08, 0x88, 0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20
+.byte 0x01, 0x42, 0xfb, 0xd0, 0x01, 0x20, 0x01, 0x42, 0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66
+.byte 0x18, 0x66, 0xff, 0xf7, 0xf2, 0xff, 0x18, 0x6e, 0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40
+.byte 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00, 0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00
+.byte 0xf4, 0x00, 0x00, 0x18, 0x22, 0x20, 0x00, 0xa0, 0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0
+.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x74, 0xb2, 0x4e, 0x7a 
+
+// last four bytes are checksum, also computed by microzig when embedding the bootrom.
diff --git a/src/bootroms/shared/addressmap.h b/src/bootroms/shared/addressmap.h
new file mode 100644
index 000000000..e8c5b4918
--- /dev/null
+++ b/src/bootroms/shared/addressmap.h
@@ -0,0 +1,73 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+#ifndef _ADDRESSMAP_H_
+#define _ADDRESSMAP_H_
+
+
+// Register address offsets for atomic RMW aliases
+#define REG_ALIAS_RW_BITS  (0x0u << 12u)
+#define REG_ALIAS_XOR_BITS (0x1u << 12u)
+#define REG_ALIAS_SET_BITS (0x2u << 12u)
+#define REG_ALIAS_CLR_BITS (0x3u << 12u)
+
+#define ROM_BASE _u(0x00000000)
+#define XIP_BASE _u(0x10000000)
+#define XIP_MAIN_BASE _u(0x10000000)
+#define XIP_NOALLOC_BASE _u(0x11000000)
+#define XIP_NOCACHE_BASE _u(0x12000000)
+#define XIP_NOCACHE_NOALLOC_BASE _u(0x13000000)
+#define XIP_CTRL_BASE _u(0x14000000)
+#define XIP_SRAM_BASE _u(0x15000000)
+#define XIP_SRAM_END _u(0x15004000)
+#define XIP_SSI_BASE _u(0x18000000)
+#define SRAM_BASE _u(0x20000000)
+#define SRAM_STRIPED_BASE _u(0x20000000)
+#define SRAM_STRIPED_END _u(0x20040000)
+#define SRAM4_BASE _u(0x20040000)
+#define SRAM5_BASE _u(0x20041000)
+#define SRAM_END _u(0x20042000)
+#define SRAM0_BASE _u(0x21000000)
+#define SRAM1_BASE _u(0x21010000)
+#define SRAM2_BASE _u(0x21020000)
+#define SRAM3_BASE _u(0x21030000)
+#define SYSINFO_BASE _u(0x40000000)
+#define SYSCFG_BASE _u(0x40004000)
+#define CLOCKS_BASE _u(0x40008000)
+#define RESETS_BASE _u(0x4000c000)
+#define PSM_BASE _u(0x40010000)
+#define IO_BANK0_BASE _u(0x40014000)
+#define IO_QSPI_BASE _u(0x40018000)
+#define PADS_BANK0_BASE _u(0x4001c000)
+#define PADS_QSPI_BASE _u(0x40020000)
+#define XOSC_BASE _u(0x40024000)
+#define PLL_SYS_BASE _u(0x40028000)
+#define PLL_USB_BASE _u(0x4002c000)
+#define BUSCTRL_BASE _u(0x40030000)
+#define UART0_BASE _u(0x40034000)
+#define UART1_BASE _u(0x40038000)
+#define SPI0_BASE _u(0x4003c000)
+#define SPI1_BASE _u(0x40040000)
+#define I2C0_BASE _u(0x40044000)
+#define I2C1_BASE _u(0x40048000)
+#define ADC_BASE _u(0x4004c000)
+#define PWM_BASE _u(0x40050000)
+#define TIMER_BASE _u(0x40054000)
+#define WATCHDOG_BASE _u(0x40058000)
+#define RTC_BASE _u(0x4005c000)
+#define ROSC_BASE _u(0x40060000)
+#define VREG_AND_CHIP_RESET_BASE _u(0x40064000)
+#define TBMAN_BASE _u(0x4006c000)
+#define DMA_BASE _u(0x50000000)
+#define USBCTRL_DPRAM_BASE _u(0x50100000)
+#define USBCTRL_BASE _u(0x50100000)
+#define USBCTRL_REGS_BASE _u(0x50110000)
+#define PIO0_BASE _u(0x50200000)
+#define PIO1_BASE _u(0x50300000)
+#define XIP_AUX_BASE _u(0x50400000)
+#define SIO_BASE _u(0xd0000000)
+#define PPB_BASE _u(0xe0000000)
+
+#endif // _ADDRESSMAP_H_
diff --git a/src/bootroms/shared/asm_helper.S b/src/bootroms/shared/asm_helper.S
new file mode 100644
index 000000000..8e2c37ae4
--- /dev/null
+++ b/src/bootroms/shared/asm_helper.S
@@ -0,0 +1,41 @@
+/*
+ * Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#include "regs.h"
+
+# note we don't do this by default in this file for backwards comaptibility with user code
+# that may include this file, but not use unified syntax. Note that this macro does equivalent
+# setup to the pico_default_asm macro for inline assembly in C code.
+.macro pico_default_asm_setup
+.syntax unified
+.cpu cortex-m0plus
+.thumb
+.endm
+
+// do not put align in here as it is used mid function sometimes
+.macro regular_func x
+.global \x
+.type \x,%function
+.thumb_func
+\x:
+.endm
+
+.macro regular_func_with_section x
+.section .text.\x
+regular_func \x
+.endm
+
+// do not put align in here as it is used mid function sometimes
+.macro wrapper_func x
+regular_func WRAPPER_FUNC_NAME(\x)
+.endm
+
+.macro __pre_init func, priority_string
+.section .preinit_array.\priority_string
+.align 2
+.word \func
+.endm
+
diff --git a/src/bootroms/shared/exit_from_boot2.S b/src/bootroms/shared/exit_from_boot2.S
new file mode 100644
index 000000000..a1fd2bce8
--- /dev/null
+++ b/src/bootroms/shared/exit_from_boot2.S
@@ -0,0 +1,28 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT2_HELPER_EXIT_FROM_BOOT2
+#define _BOOT2_HELPER_EXIT_FROM_BOOT2
+
+#include "regs.h"
+
+// If entered from the bootrom, lr (which we earlier pushed) will be 0,
+// and we vector through the table at the start of the main flash image.
+// Any regular function call will have a nonzero value for lr.
+check_return:
+    pop {r0}
+    cmp r0, #0
+    beq vector_into_flash
+    bx r0
+vector_into_flash:
+    ldr r0, =(XIP_BASE + 0x100)
+    ldr r1, =(PPB_BASE + M0PLUS_VTOR_OFFSET)
+    str r0, [r1]
+    ldmia r0, {r0, r1}
+    msr msp, r0
+    bx r1
+
+#endif
diff --git a/src/bootroms/shared/m0plus.h b/src/bootroms/shared/m0plus.h
new file mode 100644
index 000000000..cef5ab0a1
--- /dev/null
+++ b/src/bootroms/shared/m0plus.h
@@ -0,0 +1,1149 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : M0PLUS
+// Version        : 1
+// Bus type       : ahbl
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_M0PLUS_DEFINED
+#define HARDWARE_REGS_M0PLUS_DEFINED
+// =============================================================================
+// Register    : M0PLUS_SYST_CSR
+// Description : Use the SysTick Control and Status Register to enable the
+//               SysTick features.
+#define M0PLUS_SYST_CSR_OFFSET _u(0x0000e010)
+#define M0PLUS_SYST_CSR_BITS   _u(0x00010007)
+#define M0PLUS_SYST_CSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CSR_COUNTFLAG
+// Description : Returns 1 if timer counted to 0 since last time this was read.
+//               Clears on read by application or debugger.
+#define M0PLUS_SYST_CSR_COUNTFLAG_RESET  _u(0x0)
+#define M0PLUS_SYST_CSR_COUNTFLAG_BITS   _u(0x00010000)
+#define M0PLUS_SYST_CSR_COUNTFLAG_MSB    _u(16)
+#define M0PLUS_SYST_CSR_COUNTFLAG_LSB    _u(16)
+#define M0PLUS_SYST_CSR_COUNTFLAG_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CSR_CLKSOURCE
+// Description : SysTick clock source. Always reads as one if SYST_CALIB reports
+//               NOREF.
+//               Selects the SysTick timer clock source:
+//               0 = External reference clock.
+//               1 = Processor clock.
+#define M0PLUS_SYST_CSR_CLKSOURCE_RESET  _u(0x0)
+#define M0PLUS_SYST_CSR_CLKSOURCE_BITS   _u(0x00000004)
+#define M0PLUS_SYST_CSR_CLKSOURCE_MSB    _u(2)
+#define M0PLUS_SYST_CSR_CLKSOURCE_LSB    _u(2)
+#define M0PLUS_SYST_CSR_CLKSOURCE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CSR_TICKINT
+// Description : Enables SysTick exception request:
+//               0 = Counting down to zero does not assert the SysTick exception
+//               request.
+//               1 = Counting down to zero to asserts the SysTick exception
+//               request.
+#define M0PLUS_SYST_CSR_TICKINT_RESET  _u(0x0)
+#define M0PLUS_SYST_CSR_TICKINT_BITS   _u(0x00000002)
+#define M0PLUS_SYST_CSR_TICKINT_MSB    _u(1)
+#define M0PLUS_SYST_CSR_TICKINT_LSB    _u(1)
+#define M0PLUS_SYST_CSR_TICKINT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CSR_ENABLE
+// Description : Enable SysTick counter:
+//               0 = Counter disabled.
+//               1 = Counter enabled.
+#define M0PLUS_SYST_CSR_ENABLE_RESET  _u(0x0)
+#define M0PLUS_SYST_CSR_ENABLE_BITS   _u(0x00000001)
+#define M0PLUS_SYST_CSR_ENABLE_MSB    _u(0)
+#define M0PLUS_SYST_CSR_ENABLE_LSB    _u(0)
+#define M0PLUS_SYST_CSR_ENABLE_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SYST_RVR
+// Description : Use the SysTick Reload Value Register to specify the start
+//               value to load into the current value register when the counter
+//               reaches 0. It can be any value between 0 and 0x00FFFFFF. A
+//               start value of 0 is possible, but has no effect because the
+//               SysTick interrupt and COUNTFLAG are activated when counting
+//               from 1 to 0. The reset value of this register is UNKNOWN.
+//               To generate a multi-shot timer with a period of N processor
+//               clock cycles, use a RELOAD value of N-1. For example, if the
+//               SysTick interrupt is required every 100 clock pulses, set
+//               RELOAD to 99.
+#define M0PLUS_SYST_RVR_OFFSET _u(0x0000e014)
+#define M0PLUS_SYST_RVR_BITS   _u(0x00ffffff)
+#define M0PLUS_SYST_RVR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_RVR_RELOAD
+// Description : Value to load into the SysTick Current Value Register when the
+//               counter reaches 0.
+#define M0PLUS_SYST_RVR_RELOAD_RESET  _u(0x000000)
+#define M0PLUS_SYST_RVR_RELOAD_BITS   _u(0x00ffffff)
+#define M0PLUS_SYST_RVR_RELOAD_MSB    _u(23)
+#define M0PLUS_SYST_RVR_RELOAD_LSB    _u(0)
+#define M0PLUS_SYST_RVR_RELOAD_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SYST_CVR
+// Description : Use the SysTick Current Value Register to find the current
+//               value in the register. The reset value of this register is
+//               UNKNOWN.
+#define M0PLUS_SYST_CVR_OFFSET _u(0x0000e018)
+#define M0PLUS_SYST_CVR_BITS   _u(0x00ffffff)
+#define M0PLUS_SYST_CVR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CVR_CURRENT
+// Description : Reads return the current value of the SysTick counter. This
+//               register is write-clear. Writing to it with any value clears
+//               the register to 0. Clearing this register also clears the
+//               COUNTFLAG bit of the SysTick Control and Status Register.
+#define M0PLUS_SYST_CVR_CURRENT_RESET  _u(0x000000)
+#define M0PLUS_SYST_CVR_CURRENT_BITS   _u(0x00ffffff)
+#define M0PLUS_SYST_CVR_CURRENT_MSB    _u(23)
+#define M0PLUS_SYST_CVR_CURRENT_LSB    _u(0)
+#define M0PLUS_SYST_CVR_CURRENT_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SYST_CALIB
+// Description : Use the SysTick Calibration Value Register to enable software
+//               to scale to any required speed using divide and multiply.
+#define M0PLUS_SYST_CALIB_OFFSET _u(0x0000e01c)
+#define M0PLUS_SYST_CALIB_BITS   _u(0xc0ffffff)
+#define M0PLUS_SYST_CALIB_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CALIB_NOREF
+// Description : If reads as 1, the Reference clock is not provided - the
+//               CLKSOURCE bit of the SysTick Control and Status register will
+//               be forced to 1 and cannot be cleared to 0.
+#define M0PLUS_SYST_CALIB_NOREF_RESET  _u(0x0)
+#define M0PLUS_SYST_CALIB_NOREF_BITS   _u(0x80000000)
+#define M0PLUS_SYST_CALIB_NOREF_MSB    _u(31)
+#define M0PLUS_SYST_CALIB_NOREF_LSB    _u(31)
+#define M0PLUS_SYST_CALIB_NOREF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CALIB_SKEW
+// Description : If reads as 1, the calibration value for 10ms is inexact (due
+//               to clock frequency).
+#define M0PLUS_SYST_CALIB_SKEW_RESET  _u(0x0)
+#define M0PLUS_SYST_CALIB_SKEW_BITS   _u(0x40000000)
+#define M0PLUS_SYST_CALIB_SKEW_MSB    _u(30)
+#define M0PLUS_SYST_CALIB_SKEW_LSB    _u(30)
+#define M0PLUS_SYST_CALIB_SKEW_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SYST_CALIB_TENMS
+// Description : An optional Reload value to be used for 10ms (100Hz) timing,
+//               subject to system clock skew errors. If the value reads as 0,
+//               the calibration value is not known.
+#define M0PLUS_SYST_CALIB_TENMS_RESET  _u(0x000000)
+#define M0PLUS_SYST_CALIB_TENMS_BITS   _u(0x00ffffff)
+#define M0PLUS_SYST_CALIB_TENMS_MSB    _u(23)
+#define M0PLUS_SYST_CALIB_TENMS_LSB    _u(0)
+#define M0PLUS_SYST_CALIB_TENMS_ACCESS "RO"
+// =============================================================================
+// Register    : M0PLUS_NVIC_ISER
+// Description : Use the Interrupt Set-Enable Register to enable interrupts and
+//               determine which interrupts are currently enabled.
+//               If a pending interrupt is enabled, the NVIC activates the
+//               interrupt based on its priority. If an interrupt is not
+//               enabled, asserting its interrupt signal changes the interrupt
+//               state to pending, but the NVIC never activates the interrupt,
+//               regardless of its priority.
+#define M0PLUS_NVIC_ISER_OFFSET _u(0x0000e100)
+#define M0PLUS_NVIC_ISER_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ISER_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_ISER_SETENA
+// Description : Interrupt set-enable bits.
+//               Write:
+//               0 = No effect.
+//               1 = Enable interrupt.
+//               Read:
+//               0 = Interrupt disabled.
+//               1 = Interrupt enabled.
+#define M0PLUS_NVIC_ISER_SETENA_RESET  _u(0x00000000)
+#define M0PLUS_NVIC_ISER_SETENA_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ISER_SETENA_MSB    _u(31)
+#define M0PLUS_NVIC_ISER_SETENA_LSB    _u(0)
+#define M0PLUS_NVIC_ISER_SETENA_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_ICER
+// Description : Use the Interrupt Clear-Enable Registers to disable interrupts
+//               and determine which interrupts are currently enabled.
+#define M0PLUS_NVIC_ICER_OFFSET _u(0x0000e180)
+#define M0PLUS_NVIC_ICER_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ICER_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_ICER_CLRENA
+// Description : Interrupt clear-enable bits.
+//               Write:
+//               0 = No effect.
+//               1 = Disable interrupt.
+//               Read:
+//               0 = Interrupt disabled.
+//               1 = Interrupt enabled.
+#define M0PLUS_NVIC_ICER_CLRENA_RESET  _u(0x00000000)
+#define M0PLUS_NVIC_ICER_CLRENA_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ICER_CLRENA_MSB    _u(31)
+#define M0PLUS_NVIC_ICER_CLRENA_LSB    _u(0)
+#define M0PLUS_NVIC_ICER_CLRENA_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_ISPR
+// Description : The NVIC_ISPR forces interrupts into the pending state, and
+//               shows which interrupts are pending.
+#define M0PLUS_NVIC_ISPR_OFFSET _u(0x0000e200)
+#define M0PLUS_NVIC_ISPR_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ISPR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_ISPR_SETPEND
+// Description : Interrupt set-pending bits.
+//               Write:
+//               0 = No effect.
+//               1 = Changes interrupt state to pending.
+//               Read:
+//               0 = Interrupt is not pending.
+//               1 = Interrupt is pending.
+//               Note: Writing 1 to the NVIC_ISPR bit corresponding to:
+//               An interrupt that is pending has no effect.
+//               A disabled interrupt sets the state of that interrupt to
+//               pending.
+#define M0PLUS_NVIC_ISPR_SETPEND_RESET  _u(0x00000000)
+#define M0PLUS_NVIC_ISPR_SETPEND_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ISPR_SETPEND_MSB    _u(31)
+#define M0PLUS_NVIC_ISPR_SETPEND_LSB    _u(0)
+#define M0PLUS_NVIC_ISPR_SETPEND_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_ICPR
+// Description : Use the Interrupt Clear-Pending Register to clear pending
+//               interrupts and determine which interrupts are currently
+//               pending.
+#define M0PLUS_NVIC_ICPR_OFFSET _u(0x0000e280)
+#define M0PLUS_NVIC_ICPR_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ICPR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_ICPR_CLRPEND
+// Description : Interrupt clear-pending bits.
+//               Write:
+//               0 = No effect.
+//               1 = Removes pending state and interrupt.
+//               Read:
+//               0 = Interrupt is not pending.
+//               1 = Interrupt is pending.
+#define M0PLUS_NVIC_ICPR_CLRPEND_RESET  _u(0x00000000)
+#define M0PLUS_NVIC_ICPR_CLRPEND_BITS   _u(0xffffffff)
+#define M0PLUS_NVIC_ICPR_CLRPEND_MSB    _u(31)
+#define M0PLUS_NVIC_ICPR_CLRPEND_LSB    _u(0)
+#define M0PLUS_NVIC_ICPR_CLRPEND_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR0
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+//               Note: Writing 1 to an NVIC_ICPR bit does not affect the active
+//               state of the corresponding interrupt.
+//               These registers are only word-accessible
+#define M0PLUS_NVIC_IPR0_OFFSET _u(0x0000e400)
+#define M0PLUS_NVIC_IPR0_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR0_IP_3
+// Description : Priority of interrupt 3
+#define M0PLUS_NVIC_IPR0_IP_3_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_3_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR0_IP_3_MSB    _u(31)
+#define M0PLUS_NVIC_IPR0_IP_3_LSB    _u(30)
+#define M0PLUS_NVIC_IPR0_IP_3_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR0_IP_2
+// Description : Priority of interrupt 2
+#define M0PLUS_NVIC_IPR0_IP_2_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_2_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR0_IP_2_MSB    _u(23)
+#define M0PLUS_NVIC_IPR0_IP_2_LSB    _u(22)
+#define M0PLUS_NVIC_IPR0_IP_2_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR0_IP_1
+// Description : Priority of interrupt 1
+#define M0PLUS_NVIC_IPR0_IP_1_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_1_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR0_IP_1_MSB    _u(15)
+#define M0PLUS_NVIC_IPR0_IP_1_LSB    _u(14)
+#define M0PLUS_NVIC_IPR0_IP_1_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR0_IP_0
+// Description : Priority of interrupt 0
+#define M0PLUS_NVIC_IPR0_IP_0_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR0_IP_0_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR0_IP_0_MSB    _u(7)
+#define M0PLUS_NVIC_IPR0_IP_0_LSB    _u(6)
+#define M0PLUS_NVIC_IPR0_IP_0_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR1
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR1_OFFSET _u(0x0000e404)
+#define M0PLUS_NVIC_IPR1_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR1_IP_7
+// Description : Priority of interrupt 7
+#define M0PLUS_NVIC_IPR1_IP_7_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_7_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR1_IP_7_MSB    _u(31)
+#define M0PLUS_NVIC_IPR1_IP_7_LSB    _u(30)
+#define M0PLUS_NVIC_IPR1_IP_7_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR1_IP_6
+// Description : Priority of interrupt 6
+#define M0PLUS_NVIC_IPR1_IP_6_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_6_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR1_IP_6_MSB    _u(23)
+#define M0PLUS_NVIC_IPR1_IP_6_LSB    _u(22)
+#define M0PLUS_NVIC_IPR1_IP_6_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR1_IP_5
+// Description : Priority of interrupt 5
+#define M0PLUS_NVIC_IPR1_IP_5_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_5_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR1_IP_5_MSB    _u(15)
+#define M0PLUS_NVIC_IPR1_IP_5_LSB    _u(14)
+#define M0PLUS_NVIC_IPR1_IP_5_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR1_IP_4
+// Description : Priority of interrupt 4
+#define M0PLUS_NVIC_IPR1_IP_4_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR1_IP_4_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR1_IP_4_MSB    _u(7)
+#define M0PLUS_NVIC_IPR1_IP_4_LSB    _u(6)
+#define M0PLUS_NVIC_IPR1_IP_4_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR2
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR2_OFFSET _u(0x0000e408)
+#define M0PLUS_NVIC_IPR2_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR2_IP_11
+// Description : Priority of interrupt 11
+#define M0PLUS_NVIC_IPR2_IP_11_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_11_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR2_IP_11_MSB    _u(31)
+#define M0PLUS_NVIC_IPR2_IP_11_LSB    _u(30)
+#define M0PLUS_NVIC_IPR2_IP_11_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR2_IP_10
+// Description : Priority of interrupt 10
+#define M0PLUS_NVIC_IPR2_IP_10_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_10_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR2_IP_10_MSB    _u(23)
+#define M0PLUS_NVIC_IPR2_IP_10_LSB    _u(22)
+#define M0PLUS_NVIC_IPR2_IP_10_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR2_IP_9
+// Description : Priority of interrupt 9
+#define M0PLUS_NVIC_IPR2_IP_9_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_9_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR2_IP_9_MSB    _u(15)
+#define M0PLUS_NVIC_IPR2_IP_9_LSB    _u(14)
+#define M0PLUS_NVIC_IPR2_IP_9_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR2_IP_8
+// Description : Priority of interrupt 8
+#define M0PLUS_NVIC_IPR2_IP_8_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR2_IP_8_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR2_IP_8_MSB    _u(7)
+#define M0PLUS_NVIC_IPR2_IP_8_LSB    _u(6)
+#define M0PLUS_NVIC_IPR2_IP_8_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR3
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR3_OFFSET _u(0x0000e40c)
+#define M0PLUS_NVIC_IPR3_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR3_IP_15
+// Description : Priority of interrupt 15
+#define M0PLUS_NVIC_IPR3_IP_15_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_15_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR3_IP_15_MSB    _u(31)
+#define M0PLUS_NVIC_IPR3_IP_15_LSB    _u(30)
+#define M0PLUS_NVIC_IPR3_IP_15_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR3_IP_14
+// Description : Priority of interrupt 14
+#define M0PLUS_NVIC_IPR3_IP_14_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_14_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR3_IP_14_MSB    _u(23)
+#define M0PLUS_NVIC_IPR3_IP_14_LSB    _u(22)
+#define M0PLUS_NVIC_IPR3_IP_14_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR3_IP_13
+// Description : Priority of interrupt 13
+#define M0PLUS_NVIC_IPR3_IP_13_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_13_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR3_IP_13_MSB    _u(15)
+#define M0PLUS_NVIC_IPR3_IP_13_LSB    _u(14)
+#define M0PLUS_NVIC_IPR3_IP_13_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR3_IP_12
+// Description : Priority of interrupt 12
+#define M0PLUS_NVIC_IPR3_IP_12_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR3_IP_12_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR3_IP_12_MSB    _u(7)
+#define M0PLUS_NVIC_IPR3_IP_12_LSB    _u(6)
+#define M0PLUS_NVIC_IPR3_IP_12_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR4
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR4_OFFSET _u(0x0000e410)
+#define M0PLUS_NVIC_IPR4_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR4_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR4_IP_19
+// Description : Priority of interrupt 19
+#define M0PLUS_NVIC_IPR4_IP_19_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_19_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR4_IP_19_MSB    _u(31)
+#define M0PLUS_NVIC_IPR4_IP_19_LSB    _u(30)
+#define M0PLUS_NVIC_IPR4_IP_19_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR4_IP_18
+// Description : Priority of interrupt 18
+#define M0PLUS_NVIC_IPR4_IP_18_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_18_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR4_IP_18_MSB    _u(23)
+#define M0PLUS_NVIC_IPR4_IP_18_LSB    _u(22)
+#define M0PLUS_NVIC_IPR4_IP_18_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR4_IP_17
+// Description : Priority of interrupt 17
+#define M0PLUS_NVIC_IPR4_IP_17_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_17_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR4_IP_17_MSB    _u(15)
+#define M0PLUS_NVIC_IPR4_IP_17_LSB    _u(14)
+#define M0PLUS_NVIC_IPR4_IP_17_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR4_IP_16
+// Description : Priority of interrupt 16
+#define M0PLUS_NVIC_IPR4_IP_16_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR4_IP_16_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR4_IP_16_MSB    _u(7)
+#define M0PLUS_NVIC_IPR4_IP_16_LSB    _u(6)
+#define M0PLUS_NVIC_IPR4_IP_16_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR5
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR5_OFFSET _u(0x0000e414)
+#define M0PLUS_NVIC_IPR5_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR5_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR5_IP_23
+// Description : Priority of interrupt 23
+#define M0PLUS_NVIC_IPR5_IP_23_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_23_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR5_IP_23_MSB    _u(31)
+#define M0PLUS_NVIC_IPR5_IP_23_LSB    _u(30)
+#define M0PLUS_NVIC_IPR5_IP_23_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR5_IP_22
+// Description : Priority of interrupt 22
+#define M0PLUS_NVIC_IPR5_IP_22_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_22_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR5_IP_22_MSB    _u(23)
+#define M0PLUS_NVIC_IPR5_IP_22_LSB    _u(22)
+#define M0PLUS_NVIC_IPR5_IP_22_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR5_IP_21
+// Description : Priority of interrupt 21
+#define M0PLUS_NVIC_IPR5_IP_21_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_21_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR5_IP_21_MSB    _u(15)
+#define M0PLUS_NVIC_IPR5_IP_21_LSB    _u(14)
+#define M0PLUS_NVIC_IPR5_IP_21_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR5_IP_20
+// Description : Priority of interrupt 20
+#define M0PLUS_NVIC_IPR5_IP_20_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR5_IP_20_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR5_IP_20_MSB    _u(7)
+#define M0PLUS_NVIC_IPR5_IP_20_LSB    _u(6)
+#define M0PLUS_NVIC_IPR5_IP_20_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR6
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR6_OFFSET _u(0x0000e418)
+#define M0PLUS_NVIC_IPR6_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR6_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR6_IP_27
+// Description : Priority of interrupt 27
+#define M0PLUS_NVIC_IPR6_IP_27_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_27_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR6_IP_27_MSB    _u(31)
+#define M0PLUS_NVIC_IPR6_IP_27_LSB    _u(30)
+#define M0PLUS_NVIC_IPR6_IP_27_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR6_IP_26
+// Description : Priority of interrupt 26
+#define M0PLUS_NVIC_IPR6_IP_26_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_26_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR6_IP_26_MSB    _u(23)
+#define M0PLUS_NVIC_IPR6_IP_26_LSB    _u(22)
+#define M0PLUS_NVIC_IPR6_IP_26_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR6_IP_25
+// Description : Priority of interrupt 25
+#define M0PLUS_NVIC_IPR6_IP_25_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_25_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR6_IP_25_MSB    _u(15)
+#define M0PLUS_NVIC_IPR6_IP_25_LSB    _u(14)
+#define M0PLUS_NVIC_IPR6_IP_25_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR6_IP_24
+// Description : Priority of interrupt 24
+#define M0PLUS_NVIC_IPR6_IP_24_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR6_IP_24_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR6_IP_24_MSB    _u(7)
+#define M0PLUS_NVIC_IPR6_IP_24_LSB    _u(6)
+#define M0PLUS_NVIC_IPR6_IP_24_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_NVIC_IPR7
+// Description : Use the Interrupt Priority Registers to assign a priority from
+//               0 to 3 to each of the available interrupts. 0 is the highest
+//               priority, and 3 is the lowest.
+#define M0PLUS_NVIC_IPR7_OFFSET _u(0x0000e41c)
+#define M0PLUS_NVIC_IPR7_BITS   _u(0xc0c0c0c0)
+#define M0PLUS_NVIC_IPR7_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR7_IP_31
+// Description : Priority of interrupt 31
+#define M0PLUS_NVIC_IPR7_IP_31_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_31_BITS   _u(0xc0000000)
+#define M0PLUS_NVIC_IPR7_IP_31_MSB    _u(31)
+#define M0PLUS_NVIC_IPR7_IP_31_LSB    _u(30)
+#define M0PLUS_NVIC_IPR7_IP_31_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR7_IP_30
+// Description : Priority of interrupt 30
+#define M0PLUS_NVIC_IPR7_IP_30_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_30_BITS   _u(0x00c00000)
+#define M0PLUS_NVIC_IPR7_IP_30_MSB    _u(23)
+#define M0PLUS_NVIC_IPR7_IP_30_LSB    _u(22)
+#define M0PLUS_NVIC_IPR7_IP_30_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR7_IP_29
+// Description : Priority of interrupt 29
+#define M0PLUS_NVIC_IPR7_IP_29_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_29_BITS   _u(0x0000c000)
+#define M0PLUS_NVIC_IPR7_IP_29_MSB    _u(15)
+#define M0PLUS_NVIC_IPR7_IP_29_LSB    _u(14)
+#define M0PLUS_NVIC_IPR7_IP_29_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_NVIC_IPR7_IP_28
+// Description : Priority of interrupt 28
+#define M0PLUS_NVIC_IPR7_IP_28_RESET  _u(0x0)
+#define M0PLUS_NVIC_IPR7_IP_28_BITS   _u(0x000000c0)
+#define M0PLUS_NVIC_IPR7_IP_28_MSB    _u(7)
+#define M0PLUS_NVIC_IPR7_IP_28_LSB    _u(6)
+#define M0PLUS_NVIC_IPR7_IP_28_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_CPUID
+// Description : Read the CPU ID Base Register to determine: the ID number of
+//               the processor core, the version number of the processor core,
+//               the implementation details of the processor core.
+#define M0PLUS_CPUID_OFFSET _u(0x0000ed00)
+#define M0PLUS_CPUID_BITS   _u(0xffffffff)
+#define M0PLUS_CPUID_RESET  _u(0x410cc601)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CPUID_IMPLEMENTER
+// Description : Implementor code: 0x41 = ARM
+#define M0PLUS_CPUID_IMPLEMENTER_RESET  _u(0x41)
+#define M0PLUS_CPUID_IMPLEMENTER_BITS   _u(0xff000000)
+#define M0PLUS_CPUID_IMPLEMENTER_MSB    _u(31)
+#define M0PLUS_CPUID_IMPLEMENTER_LSB    _u(24)
+#define M0PLUS_CPUID_IMPLEMENTER_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CPUID_VARIANT
+// Description : Major revision number n in the rnpm revision status:
+//               0x0 = Revision 0.
+#define M0PLUS_CPUID_VARIANT_RESET  _u(0x0)
+#define M0PLUS_CPUID_VARIANT_BITS   _u(0x00f00000)
+#define M0PLUS_CPUID_VARIANT_MSB    _u(23)
+#define M0PLUS_CPUID_VARIANT_LSB    _u(20)
+#define M0PLUS_CPUID_VARIANT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CPUID_ARCHITECTURE
+// Description : Constant that defines the architecture of the processor:
+//               0xC = ARMv6-M architecture.
+#define M0PLUS_CPUID_ARCHITECTURE_RESET  _u(0xc)
+#define M0PLUS_CPUID_ARCHITECTURE_BITS   _u(0x000f0000)
+#define M0PLUS_CPUID_ARCHITECTURE_MSB    _u(19)
+#define M0PLUS_CPUID_ARCHITECTURE_LSB    _u(16)
+#define M0PLUS_CPUID_ARCHITECTURE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CPUID_PARTNO
+// Description : Number of processor within family: 0xC60 = Cortex-M0+
+#define M0PLUS_CPUID_PARTNO_RESET  _u(0xc60)
+#define M0PLUS_CPUID_PARTNO_BITS   _u(0x0000fff0)
+#define M0PLUS_CPUID_PARTNO_MSB    _u(15)
+#define M0PLUS_CPUID_PARTNO_LSB    _u(4)
+#define M0PLUS_CPUID_PARTNO_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CPUID_REVISION
+// Description : Minor revision number m in the rnpm revision status:
+//               0x1 = Patch 1.
+#define M0PLUS_CPUID_REVISION_RESET  _u(0x1)
+#define M0PLUS_CPUID_REVISION_BITS   _u(0x0000000f)
+#define M0PLUS_CPUID_REVISION_MSB    _u(3)
+#define M0PLUS_CPUID_REVISION_LSB    _u(0)
+#define M0PLUS_CPUID_REVISION_ACCESS "RO"
+// =============================================================================
+// Register    : M0PLUS_ICSR
+// Description : Use the Interrupt Control State Register to set a pending
+//               Non-Maskable Interrupt (NMI), set or clear a pending PendSV,
+//               set or clear a pending SysTick, check for pending exceptions,
+//               check the vector number of the highest priority pended
+//               exception, check the vector number of the active exception.
+#define M0PLUS_ICSR_OFFSET _u(0x0000ed04)
+#define M0PLUS_ICSR_BITS   _u(0x9edff1ff)
+#define M0PLUS_ICSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_NMIPENDSET
+// Description : Setting this bit will activate an NMI. Since NMI is the highest
+//               priority exception, it will activate as soon as it is
+//               registered.
+//               NMI set-pending bit.
+//               Write:
+//               0 = No effect.
+//               1 = Changes NMI exception state to pending.
+//               Read:
+//               0 = NMI exception is not pending.
+//               1 = NMI exception is pending.
+//               Because NMI is the highest-priority exception, normally the
+//               processor enters the NMI
+//               exception handler as soon as it detects a write of 1 to this
+//               bit. Entering the handler then clears
+//               this bit to 0. This means a read of this bit by the NMI
+//               exception handler returns 1 only if the
+//               NMI signal is reasserted while the processor is executing that
+//               handler.
+#define M0PLUS_ICSR_NMIPENDSET_RESET  _u(0x0)
+#define M0PLUS_ICSR_NMIPENDSET_BITS   _u(0x80000000)
+#define M0PLUS_ICSR_NMIPENDSET_MSB    _u(31)
+#define M0PLUS_ICSR_NMIPENDSET_LSB    _u(31)
+#define M0PLUS_ICSR_NMIPENDSET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_PENDSVSET
+// Description : PendSV set-pending bit.
+//               Write:
+//               0 = No effect.
+//               1 = Changes PendSV exception state to pending.
+//               Read:
+//               0 = PendSV exception is not pending.
+//               1 = PendSV exception is pending.
+//               Writing 1 to this bit is the only way to set the PendSV
+//               exception state to pending.
+#define M0PLUS_ICSR_PENDSVSET_RESET  _u(0x0)
+#define M0PLUS_ICSR_PENDSVSET_BITS   _u(0x10000000)
+#define M0PLUS_ICSR_PENDSVSET_MSB    _u(28)
+#define M0PLUS_ICSR_PENDSVSET_LSB    _u(28)
+#define M0PLUS_ICSR_PENDSVSET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_PENDSVCLR
+// Description : PendSV clear-pending bit.
+//               Write:
+//               0 = No effect.
+//               1 = Removes the pending state from the PendSV exception.
+#define M0PLUS_ICSR_PENDSVCLR_RESET  _u(0x0)
+#define M0PLUS_ICSR_PENDSVCLR_BITS   _u(0x08000000)
+#define M0PLUS_ICSR_PENDSVCLR_MSB    _u(27)
+#define M0PLUS_ICSR_PENDSVCLR_LSB    _u(27)
+#define M0PLUS_ICSR_PENDSVCLR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_PENDSTSET
+// Description : SysTick exception set-pending bit.
+//               Write:
+//               0 = No effect.
+//               1 = Changes SysTick exception state to pending.
+//               Read:
+//               0 = SysTick exception is not pending.
+//               1 = SysTick exception is pending.
+#define M0PLUS_ICSR_PENDSTSET_RESET  _u(0x0)
+#define M0PLUS_ICSR_PENDSTSET_BITS   _u(0x04000000)
+#define M0PLUS_ICSR_PENDSTSET_MSB    _u(26)
+#define M0PLUS_ICSR_PENDSTSET_LSB    _u(26)
+#define M0PLUS_ICSR_PENDSTSET_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_PENDSTCLR
+// Description : SysTick exception clear-pending bit.
+//               Write:
+//               0 = No effect.
+//               1 = Removes the pending state from the SysTick exception.
+//               This bit is WO. On a register read its value is Unknown.
+#define M0PLUS_ICSR_PENDSTCLR_RESET  _u(0x0)
+#define M0PLUS_ICSR_PENDSTCLR_BITS   _u(0x02000000)
+#define M0PLUS_ICSR_PENDSTCLR_MSB    _u(25)
+#define M0PLUS_ICSR_PENDSTCLR_LSB    _u(25)
+#define M0PLUS_ICSR_PENDSTCLR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_ISRPREEMPT
+// Description : The system can only access this bit when the core is halted. It
+//               indicates that a pending interrupt is to be taken in the next
+//               running cycle. If C_MASKINTS is clear in the Debug Halting
+//               Control and Status Register, the interrupt is serviced.
+#define M0PLUS_ICSR_ISRPREEMPT_RESET  _u(0x0)
+#define M0PLUS_ICSR_ISRPREEMPT_BITS   _u(0x00800000)
+#define M0PLUS_ICSR_ISRPREEMPT_MSB    _u(23)
+#define M0PLUS_ICSR_ISRPREEMPT_LSB    _u(23)
+#define M0PLUS_ICSR_ISRPREEMPT_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_ISRPENDING
+// Description : External interrupt pending flag
+#define M0PLUS_ICSR_ISRPENDING_RESET  _u(0x0)
+#define M0PLUS_ICSR_ISRPENDING_BITS   _u(0x00400000)
+#define M0PLUS_ICSR_ISRPENDING_MSB    _u(22)
+#define M0PLUS_ICSR_ISRPENDING_LSB    _u(22)
+#define M0PLUS_ICSR_ISRPENDING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_VECTPENDING
+// Description : Indicates the exception number for the highest priority pending
+//               exception: 0 = no pending exceptions. Non zero = The pending
+//               state includes the effect of memory-mapped enable and mask
+//               registers. It does not include the PRIMASK special-purpose
+//               register qualifier.
+#define M0PLUS_ICSR_VECTPENDING_RESET  _u(0x000)
+#define M0PLUS_ICSR_VECTPENDING_BITS   _u(0x001ff000)
+#define M0PLUS_ICSR_VECTPENDING_MSB    _u(20)
+#define M0PLUS_ICSR_VECTPENDING_LSB    _u(12)
+#define M0PLUS_ICSR_VECTPENDING_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_ICSR_VECTACTIVE
+// Description : Active exception number field. Reset clears the VECTACTIVE
+//               field.
+#define M0PLUS_ICSR_VECTACTIVE_RESET  _u(0x000)
+#define M0PLUS_ICSR_VECTACTIVE_BITS   _u(0x000001ff)
+#define M0PLUS_ICSR_VECTACTIVE_MSB    _u(8)
+#define M0PLUS_ICSR_VECTACTIVE_LSB    _u(0)
+#define M0PLUS_ICSR_VECTACTIVE_ACCESS "RO"
+// =============================================================================
+// Register    : M0PLUS_VTOR
+// Description : The VTOR holds the vector table offset address.
+#define M0PLUS_VTOR_OFFSET _u(0x0000ed08)
+#define M0PLUS_VTOR_BITS   _u(0xffffff00)
+#define M0PLUS_VTOR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_VTOR_TBLOFF
+// Description : Bits [31:8] of the indicate the vector table offset address.
+#define M0PLUS_VTOR_TBLOFF_RESET  _u(0x000000)
+#define M0PLUS_VTOR_TBLOFF_BITS   _u(0xffffff00)
+#define M0PLUS_VTOR_TBLOFF_MSB    _u(31)
+#define M0PLUS_VTOR_TBLOFF_LSB    _u(8)
+#define M0PLUS_VTOR_TBLOFF_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_AIRCR
+// Description : Use the Application Interrupt and Reset Control Register to:
+//               determine data endianness, clear all active state information
+//               from debug halt mode, request a system reset.
+#define M0PLUS_AIRCR_OFFSET _u(0x0000ed0c)
+#define M0PLUS_AIRCR_BITS   _u(0xffff8006)
+#define M0PLUS_AIRCR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_AIRCR_VECTKEY
+// Description : Register key:
+//               Reads as Unknown
+//               On writes, write 0x05FA to VECTKEY, otherwise the write is
+//               ignored.
+#define M0PLUS_AIRCR_VECTKEY_RESET  _u(0x0000)
+#define M0PLUS_AIRCR_VECTKEY_BITS   _u(0xffff0000)
+#define M0PLUS_AIRCR_VECTKEY_MSB    _u(31)
+#define M0PLUS_AIRCR_VECTKEY_LSB    _u(16)
+#define M0PLUS_AIRCR_VECTKEY_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_AIRCR_ENDIANESS
+// Description : Data endianness implemented:
+//               0 = Little-endian.
+#define M0PLUS_AIRCR_ENDIANESS_RESET  _u(0x0)
+#define M0PLUS_AIRCR_ENDIANESS_BITS   _u(0x00008000)
+#define M0PLUS_AIRCR_ENDIANESS_MSB    _u(15)
+#define M0PLUS_AIRCR_ENDIANESS_LSB    _u(15)
+#define M0PLUS_AIRCR_ENDIANESS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_AIRCR_SYSRESETREQ
+// Description : Writing 1 to this bit causes the SYSRESETREQ signal to the
+//               outer system to be asserted to request a reset. The intention
+//               is to force a large system reset of all major components except
+//               for debug. The C_HALT bit in the DHCSR is cleared as a result
+//               of the system reset requested. The debugger does not lose
+//               contact with the device.
+#define M0PLUS_AIRCR_SYSRESETREQ_RESET  _u(0x0)
+#define M0PLUS_AIRCR_SYSRESETREQ_BITS   _u(0x00000004)
+#define M0PLUS_AIRCR_SYSRESETREQ_MSB    _u(2)
+#define M0PLUS_AIRCR_SYSRESETREQ_LSB    _u(2)
+#define M0PLUS_AIRCR_SYSRESETREQ_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_AIRCR_VECTCLRACTIVE
+// Description : Clears all active state information for fixed and configurable
+//               exceptions. This bit: is self-clearing, can only be set by the
+//               DAP when the core is halted.  When set: clears all active
+//               exception status of the processor, forces a return to Thread
+//               mode, forces an IPSR of 0. A debugger must re-initialize the
+//               stack.
+#define M0PLUS_AIRCR_VECTCLRACTIVE_RESET  _u(0x0)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_BITS   _u(0x00000002)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_MSB    _u(1)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_LSB    _u(1)
+#define M0PLUS_AIRCR_VECTCLRACTIVE_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SCR
+// Description : System Control Register. Use the System Control Register for
+//               power-management functions: signal to the system when the
+//               processor can enter a low power state, control how the
+//               processor enters and exits low power states.
+#define M0PLUS_SCR_OFFSET _u(0x0000ed10)
+#define M0PLUS_SCR_BITS   _u(0x00000016)
+#define M0PLUS_SCR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SCR_SEVONPEND
+// Description : Send Event on Pending bit:
+//               0 = Only enabled interrupts or events can wakeup the processor,
+//               disabled interrupts are excluded.
+//               1 = Enabled events and all interrupts, including disabled
+//               interrupts, can wakeup the processor.
+//               When an event or interrupt becomes pending, the event signal
+//               wakes up the processor from WFE. If the
+//               processor is not waiting for an event, the event is registered
+//               and affects the next WFE.
+//               The processor also wakes up on execution of an SEV instruction
+//               or an external event.
+#define M0PLUS_SCR_SEVONPEND_RESET  _u(0x0)
+#define M0PLUS_SCR_SEVONPEND_BITS   _u(0x00000010)
+#define M0PLUS_SCR_SEVONPEND_MSB    _u(4)
+#define M0PLUS_SCR_SEVONPEND_LSB    _u(4)
+#define M0PLUS_SCR_SEVONPEND_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SCR_SLEEPDEEP
+// Description : Controls whether the processor uses sleep or deep sleep as its
+//               low power mode:
+//               0 = Sleep.
+//               1 = Deep sleep.
+#define M0PLUS_SCR_SLEEPDEEP_RESET  _u(0x0)
+#define M0PLUS_SCR_SLEEPDEEP_BITS   _u(0x00000004)
+#define M0PLUS_SCR_SLEEPDEEP_MSB    _u(2)
+#define M0PLUS_SCR_SLEEPDEEP_LSB    _u(2)
+#define M0PLUS_SCR_SLEEPDEEP_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SCR_SLEEPONEXIT
+// Description : Indicates sleep-on-exit when returning from Handler mode to
+//               Thread mode:
+//               0 = Do not sleep when returning to Thread mode.
+//               1 = Enter sleep, or deep sleep, on return from an ISR to Thread
+//               mode.
+//               Setting this bit to 1 enables an interrupt driven application
+//               to avoid returning to an empty main application.
+#define M0PLUS_SCR_SLEEPONEXIT_RESET  _u(0x0)
+#define M0PLUS_SCR_SLEEPONEXIT_BITS   _u(0x00000002)
+#define M0PLUS_SCR_SLEEPONEXIT_MSB    _u(1)
+#define M0PLUS_SCR_SLEEPONEXIT_LSB    _u(1)
+#define M0PLUS_SCR_SLEEPONEXIT_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_CCR
+// Description : The Configuration and Control Register permanently enables
+//               stack alignment and causes unaligned accesses to result in a
+//               Hard Fault.
+#define M0PLUS_CCR_OFFSET _u(0x0000ed14)
+#define M0PLUS_CCR_BITS   _u(0x00000208)
+#define M0PLUS_CCR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CCR_STKALIGN
+// Description : Always reads as one, indicates 8-byte stack alignment on
+//               exception entry. On exception entry, the processor uses bit[9]
+//               of the stacked PSR to indicate the stack alignment. On return
+//               from the exception it uses this stacked bit to restore the
+//               correct stack alignment.
+#define M0PLUS_CCR_STKALIGN_RESET  _u(0x0)
+#define M0PLUS_CCR_STKALIGN_BITS   _u(0x00000200)
+#define M0PLUS_CCR_STKALIGN_MSB    _u(9)
+#define M0PLUS_CCR_STKALIGN_LSB    _u(9)
+#define M0PLUS_CCR_STKALIGN_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_CCR_UNALIGN_TRP
+// Description : Always reads as one, indicates that all unaligned accesses
+//               generate a HardFault.
+#define M0PLUS_CCR_UNALIGN_TRP_RESET  _u(0x0)
+#define M0PLUS_CCR_UNALIGN_TRP_BITS   _u(0x00000008)
+#define M0PLUS_CCR_UNALIGN_TRP_MSB    _u(3)
+#define M0PLUS_CCR_UNALIGN_TRP_LSB    _u(3)
+#define M0PLUS_CCR_UNALIGN_TRP_ACCESS "RO"
+// =============================================================================
+// Register    : M0PLUS_SHPR2
+// Description : System handlers are a special class of exception handler that
+//               can have their priority set to any of the priority levels. Use
+//               the System Handler Priority Register 2 to set the priority of
+//               SVCall.
+#define M0PLUS_SHPR2_OFFSET _u(0x0000ed1c)
+#define M0PLUS_SHPR2_BITS   _u(0xc0000000)
+#define M0PLUS_SHPR2_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SHPR2_PRI_11
+// Description : Priority of system handler 11, SVCall
+#define M0PLUS_SHPR2_PRI_11_RESET  _u(0x0)
+#define M0PLUS_SHPR2_PRI_11_BITS   _u(0xc0000000)
+#define M0PLUS_SHPR2_PRI_11_MSB    _u(31)
+#define M0PLUS_SHPR2_PRI_11_LSB    _u(30)
+#define M0PLUS_SHPR2_PRI_11_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SHPR3
+// Description : System handlers are a special class of exception handler that
+//               can have their priority set to any of the priority levels. Use
+//               the System Handler Priority Register 3 to set the priority of
+//               PendSV and SysTick.
+#define M0PLUS_SHPR3_OFFSET _u(0x0000ed20)
+#define M0PLUS_SHPR3_BITS   _u(0xc0c00000)
+#define M0PLUS_SHPR3_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SHPR3_PRI_15
+// Description : Priority of system handler 15, SysTick
+#define M0PLUS_SHPR3_PRI_15_RESET  _u(0x0)
+#define M0PLUS_SHPR3_PRI_15_BITS   _u(0xc0000000)
+#define M0PLUS_SHPR3_PRI_15_MSB    _u(31)
+#define M0PLUS_SHPR3_PRI_15_LSB    _u(30)
+#define M0PLUS_SHPR3_PRI_15_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SHPR3_PRI_14
+// Description : Priority of system handler 14, PendSV
+#define M0PLUS_SHPR3_PRI_14_RESET  _u(0x0)
+#define M0PLUS_SHPR3_PRI_14_BITS   _u(0x00c00000)
+#define M0PLUS_SHPR3_PRI_14_MSB    _u(23)
+#define M0PLUS_SHPR3_PRI_14_LSB    _u(22)
+#define M0PLUS_SHPR3_PRI_14_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_SHCSR
+// Description : Use the System Handler Control and State Register to determine
+//               or clear the pending status of SVCall.
+#define M0PLUS_SHCSR_OFFSET _u(0x0000ed24)
+#define M0PLUS_SHCSR_BITS   _u(0x00008000)
+#define M0PLUS_SHCSR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_SHCSR_SVCALLPENDED
+// Description : Reads as 1 if SVCall is Pending.  Write 1 to set pending
+//               SVCall, write 0 to clear pending SVCall.
+#define M0PLUS_SHCSR_SVCALLPENDED_RESET  _u(0x0)
+#define M0PLUS_SHCSR_SVCALLPENDED_BITS   _u(0x00008000)
+#define M0PLUS_SHCSR_SVCALLPENDED_MSB    _u(15)
+#define M0PLUS_SHCSR_SVCALLPENDED_LSB    _u(15)
+#define M0PLUS_SHCSR_SVCALLPENDED_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_MPU_TYPE
+// Description : Read the MPU Type Register to determine if the processor
+//               implements an MPU, and how many regions the MPU supports.
+#define M0PLUS_MPU_TYPE_OFFSET _u(0x0000ed90)
+#define M0PLUS_MPU_TYPE_BITS   _u(0x00ffff01)
+#define M0PLUS_MPU_TYPE_RESET  _u(0x00000800)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_TYPE_IREGION
+// Description : Instruction region. Reads as zero as ARMv6-M only supports a
+//               unified MPU.
+#define M0PLUS_MPU_TYPE_IREGION_RESET  _u(0x00)
+#define M0PLUS_MPU_TYPE_IREGION_BITS   _u(0x00ff0000)
+#define M0PLUS_MPU_TYPE_IREGION_MSB    _u(23)
+#define M0PLUS_MPU_TYPE_IREGION_LSB    _u(16)
+#define M0PLUS_MPU_TYPE_IREGION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_TYPE_DREGION
+// Description : Number of regions supported by the MPU.
+#define M0PLUS_MPU_TYPE_DREGION_RESET  _u(0x08)
+#define M0PLUS_MPU_TYPE_DREGION_BITS   _u(0x0000ff00)
+#define M0PLUS_MPU_TYPE_DREGION_MSB    _u(15)
+#define M0PLUS_MPU_TYPE_DREGION_LSB    _u(8)
+#define M0PLUS_MPU_TYPE_DREGION_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_TYPE_SEPARATE
+// Description : Indicates support for separate instruction and data address
+//               maps. Reads as 0 as ARMv6-M only supports a unified MPU.
+#define M0PLUS_MPU_TYPE_SEPARATE_RESET  _u(0x0)
+#define M0PLUS_MPU_TYPE_SEPARATE_BITS   _u(0x00000001)
+#define M0PLUS_MPU_TYPE_SEPARATE_MSB    _u(0)
+#define M0PLUS_MPU_TYPE_SEPARATE_LSB    _u(0)
+#define M0PLUS_MPU_TYPE_SEPARATE_ACCESS "RO"
+// =============================================================================
+// Register    : M0PLUS_MPU_CTRL
+// Description : Use the MPU Control Register to enable and disable the MPU, and
+//               to control whether the default memory map is enabled as a
+//               background region for privileged accesses, and whether the MPU
+//               is enabled for HardFaults and NMIs.
+#define M0PLUS_MPU_CTRL_OFFSET _u(0x0000ed94)
+#define M0PLUS_MPU_CTRL_BITS   _u(0x00000007)
+#define M0PLUS_MPU_CTRL_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_CTRL_PRIVDEFENA
+// Description : Controls whether the default memory map is enabled as a
+//               background region for privileged accesses. This bit is ignored
+//               when ENABLE is clear.
+//               0 = If the MPU is enabled, disables use of the default memory
+//               map. Any memory access to a location not
+//               covered by any enabled region causes a fault.
+//               1 = If the MPU is enabled, enables use of the default memory
+//               map as a background region for privileged software accesses.
+//               When enabled, the background region acts as if it is region
+//               number -1. Any region that is defined and enabled has priority
+//               over this default map.
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_RESET  _u(0x0)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_BITS   _u(0x00000004)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_MSB    _u(2)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_LSB    _u(2)
+#define M0PLUS_MPU_CTRL_PRIVDEFENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_CTRL_HFNMIENA
+// Description : Controls the use of the MPU for HardFaults and NMIs. Setting
+//               this bit when ENABLE is clear results in UNPREDICTABLE
+//               behaviour.
+//               When the MPU is enabled:
+//               0 = MPU is disabled during HardFault and NMI handlers,
+//               regardless of the value of the ENABLE bit.
+//               1 = the MPU is enabled during HardFault and NMI handlers.
+#define M0PLUS_MPU_CTRL_HFNMIENA_RESET  _u(0x0)
+#define M0PLUS_MPU_CTRL_HFNMIENA_BITS   _u(0x00000002)
+#define M0PLUS_MPU_CTRL_HFNMIENA_MSB    _u(1)
+#define M0PLUS_MPU_CTRL_HFNMIENA_LSB    _u(1)
+#define M0PLUS_MPU_CTRL_HFNMIENA_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_CTRL_ENABLE
+// Description : Enables the MPU. If the MPU is disabled, privileged and
+//               unprivileged accesses use the default memory map.
+//               0 = MPU disabled.
+//               1 = MPU enabled.
+#define M0PLUS_MPU_CTRL_ENABLE_RESET  _u(0x0)
+#define M0PLUS_MPU_CTRL_ENABLE_BITS   _u(0x00000001)
+#define M0PLUS_MPU_CTRL_ENABLE_MSB    _u(0)
+#define M0PLUS_MPU_CTRL_ENABLE_LSB    _u(0)
+#define M0PLUS_MPU_CTRL_ENABLE_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_MPU_RNR
+// Description : Use the MPU Region Number Register to select the region
+//               currently accessed by MPU_RBAR and MPU_RASR.
+#define M0PLUS_MPU_RNR_OFFSET _u(0x0000ed98)
+#define M0PLUS_MPU_RNR_BITS   _u(0x0000000f)
+#define M0PLUS_MPU_RNR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RNR_REGION
+// Description : Indicates the MPU region referenced by the MPU_RBAR and
+//               MPU_RASR registers.
+//               The MPU supports 8 memory regions, so the permitted values of
+//               this field are 0-7.
+#define M0PLUS_MPU_RNR_REGION_RESET  _u(0x0)
+#define M0PLUS_MPU_RNR_REGION_BITS   _u(0x0000000f)
+#define M0PLUS_MPU_RNR_REGION_MSB    _u(3)
+#define M0PLUS_MPU_RNR_REGION_LSB    _u(0)
+#define M0PLUS_MPU_RNR_REGION_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_MPU_RBAR
+// Description : Read the MPU Region Base Address Register to determine the base
+//               address of the region identified by MPU_RNR. Write to update
+//               the base address of said region or that of a specified region,
+//               with whose number MPU_RNR will also be updated.
+#define M0PLUS_MPU_RBAR_OFFSET _u(0x0000ed9c)
+#define M0PLUS_MPU_RBAR_BITS   _u(0xffffff1f)
+#define M0PLUS_MPU_RBAR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RBAR_ADDR
+// Description : Base address of the region.
+#define M0PLUS_MPU_RBAR_ADDR_RESET  _u(0x000000)
+#define M0PLUS_MPU_RBAR_ADDR_BITS   _u(0xffffff00)
+#define M0PLUS_MPU_RBAR_ADDR_MSB    _u(31)
+#define M0PLUS_MPU_RBAR_ADDR_LSB    _u(8)
+#define M0PLUS_MPU_RBAR_ADDR_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RBAR_VALID
+// Description : On writes, indicates whether the write must update the base
+//               address of the region identified by the REGION field, updating
+//               the MPU_RNR to indicate this new region.
+//               Write:
+//               0 = MPU_RNR not changed, and the processor:
+//               Updates the base address for the region specified in the
+//               MPU_RNR.
+//               Ignores the value of the REGION field.
+//               1 = The processor:
+//               Updates the value of the MPU_RNR to the value of the REGION
+//               field.
+//               Updates the base address for the region specified in the REGION
+//               field.
+//               Always reads as zero.
+#define M0PLUS_MPU_RBAR_VALID_RESET  _u(0x0)
+#define M0PLUS_MPU_RBAR_VALID_BITS   _u(0x00000010)
+#define M0PLUS_MPU_RBAR_VALID_MSB    _u(4)
+#define M0PLUS_MPU_RBAR_VALID_LSB    _u(4)
+#define M0PLUS_MPU_RBAR_VALID_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RBAR_REGION
+// Description : On writes, specifies the number of the region whose base
+//               address to update provided VALID is set written as 1. On reads,
+//               returns bits [3:0] of MPU_RNR.
+#define M0PLUS_MPU_RBAR_REGION_RESET  _u(0x0)
+#define M0PLUS_MPU_RBAR_REGION_BITS   _u(0x0000000f)
+#define M0PLUS_MPU_RBAR_REGION_MSB    _u(3)
+#define M0PLUS_MPU_RBAR_REGION_LSB    _u(0)
+#define M0PLUS_MPU_RBAR_REGION_ACCESS "RW"
+// =============================================================================
+// Register    : M0PLUS_MPU_RASR
+// Description : Use the MPU Region Attribute and Size Register to define the
+//               size, access behaviour and memory type of the region identified
+//               by MPU_RNR, and enable that region.
+#define M0PLUS_MPU_RASR_OFFSET _u(0x0000eda0)
+#define M0PLUS_MPU_RASR_BITS   _u(0xffffff3f)
+#define M0PLUS_MPU_RASR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RASR_ATTRS
+// Description : The MPU Region Attribute field. Use to define the region
+//               attribute control.
+//               28 = XN: Instruction access disable bit:
+//               0 = Instruction fetches enabled.
+//               1 = Instruction fetches disabled.
+//               26:24 = AP: Access permission field
+//               18 = S: Shareable bit
+//               17 = C: Cacheable bit
+//               16 = B: Bufferable bit
+#define M0PLUS_MPU_RASR_ATTRS_RESET  _u(0x0000)
+#define M0PLUS_MPU_RASR_ATTRS_BITS   _u(0xffff0000)
+#define M0PLUS_MPU_RASR_ATTRS_MSB    _u(31)
+#define M0PLUS_MPU_RASR_ATTRS_LSB    _u(16)
+#define M0PLUS_MPU_RASR_ATTRS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RASR_SRD
+// Description : Subregion Disable. For regions of 256 bytes or larger, each bit
+//               of this field controls whether one of the eight equal
+//               subregions is enabled.
+#define M0PLUS_MPU_RASR_SRD_RESET  _u(0x00)
+#define M0PLUS_MPU_RASR_SRD_BITS   _u(0x0000ff00)
+#define M0PLUS_MPU_RASR_SRD_MSB    _u(15)
+#define M0PLUS_MPU_RASR_SRD_LSB    _u(8)
+#define M0PLUS_MPU_RASR_SRD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RASR_SIZE
+// Description : Indicates the region size. Region size in bytes = 2^(SIZE+1).
+//               The minimum permitted value is 7 (b00111) = 256Bytes
+#define M0PLUS_MPU_RASR_SIZE_RESET  _u(0x00)
+#define M0PLUS_MPU_RASR_SIZE_BITS   _u(0x0000003e)
+#define M0PLUS_MPU_RASR_SIZE_MSB    _u(5)
+#define M0PLUS_MPU_RASR_SIZE_LSB    _u(1)
+#define M0PLUS_MPU_RASR_SIZE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : M0PLUS_MPU_RASR_ENABLE
+// Description : Enables the region.
+#define M0PLUS_MPU_RASR_ENABLE_RESET  _u(0x0)
+#define M0PLUS_MPU_RASR_ENABLE_BITS   _u(0x00000001)
+#define M0PLUS_MPU_RASR_ENABLE_MSB    _u(0)
+#define M0PLUS_MPU_RASR_ENABLE_LSB    _u(0)
+#define M0PLUS_MPU_RASR_ENABLE_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_M0PLUS_DEFINED
diff --git a/src/bootroms/shared/pads_qspi.h b/src/bootroms/shared/pads_qspi.h
new file mode 100644
index 000000000..b3a09e900
--- /dev/null
+++ b/src/bootroms/shared/pads_qspi.h
@@ -0,0 +1,454 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : PADS_QSPI
+// Version        : 1
+// Bus type       : apb
+// Description    : None
+// =============================================================================
+#ifndef HARDWARE_REGS_PADS_QSPI_DEFINED
+#define HARDWARE_REGS_PADS_QSPI_DEFINED
+// =============================================================================
+// Register    : PADS_QSPI_VOLTAGE_SELECT
+// Description : Voltage select. Per bank control
+//               0x0 -> Set voltage to 3.3V (DVDD >= 2V5)
+//               0x1 -> Set voltage to 1.8V (DVDD <= 1V8)
+#define PADS_QSPI_VOLTAGE_SELECT_OFFSET    _u(0x00000000)
+#define PADS_QSPI_VOLTAGE_SELECT_BITS      _u(0x00000001)
+#define PADS_QSPI_VOLTAGE_SELECT_RESET     _u(0x00000000)
+#define PADS_QSPI_VOLTAGE_SELECT_MSB       _u(0)
+#define PADS_QSPI_VOLTAGE_SELECT_LSB       _u(0)
+#define PADS_QSPI_VOLTAGE_SELECT_ACCESS    "RW"
+#define PADS_QSPI_VOLTAGE_SELECT_VALUE_3V3 _u(0x0)
+#define PADS_QSPI_VOLTAGE_SELECT_VALUE_1V8 _u(0x1)
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SCLK
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SCLK_OFFSET _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SCLK_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SCLK_RESET  _u(0x00000056)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SCLK_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SCLK_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SCLK_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SD0
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD0_OFFSET _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD0_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD0_RESET  _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD0_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD0_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD0_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD0_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD0_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD0_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SD1
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD1_OFFSET _u(0x0000000c)
+#define PADS_QSPI_GPIO_QSPI_SD1_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD1_RESET  _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD1_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD1_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD1_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD1_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD1_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD1_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD1_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SD2
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD2_OFFSET _u(0x00000010)
+#define PADS_QSPI_GPIO_QSPI_SD2_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD2_RESET  _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD2_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD2_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD2_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD2_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD2_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD2_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD2_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SD3
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SD3_OFFSET _u(0x00000014)
+#define PADS_QSPI_GPIO_QSPI_SD3_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SD3_RESET  _u(0x00000052)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SD3_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SD3_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SD3_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SD3_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SD3_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SD3_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SD3_SLEWFAST_ACCESS "RW"
+// =============================================================================
+// Register    : PADS_QSPI_GPIO_QSPI_SS
+// Description : Pad control register
+#define PADS_QSPI_GPIO_QSPI_SS_OFFSET _u(0x00000018)
+#define PADS_QSPI_GPIO_QSPI_SS_BITS   _u(0x000000ff)
+#define PADS_QSPI_GPIO_QSPI_SS_RESET  _u(0x0000005a)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_OD
+// Description : Output disable. Has priority over output enable from
+//               peripherals
+#define PADS_QSPI_GPIO_QSPI_SS_OD_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_BITS   _u(0x00000080)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_MSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_LSB    _u(7)
+#define PADS_QSPI_GPIO_QSPI_SS_OD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_IE
+// Description : Input enable
+#define PADS_QSPI_GPIO_QSPI_SS_IE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_BITS   _u(0x00000040)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_MSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_LSB    _u(6)
+#define PADS_QSPI_GPIO_QSPI_SS_IE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_DRIVE
+// Description : Drive strength.
+//               0x0 -> 2mA
+//               0x1 -> 4mA
+//               0x2 -> 8mA
+//               0x3 -> 12mA
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_RESET      _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_BITS       _u(0x00000030)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_MSB        _u(5)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_LSB        _u(4)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_ACCESS     "RW"
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_2MA  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_4MA  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_8MA  _u(0x2)
+#define PADS_QSPI_GPIO_QSPI_SS_DRIVE_VALUE_12MA _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_PUE
+// Description : Pull up enable
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_BITS   _u(0x00000008)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_MSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_LSB    _u(3)
+#define PADS_QSPI_GPIO_QSPI_SS_PUE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_PDE
+// Description : Pull down enable
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_BITS   _u(0x00000004)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_MSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_LSB    _u(2)
+#define PADS_QSPI_GPIO_QSPI_SS_PDE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_SCHMITT
+// Description : Enable schmitt trigger
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_RESET  _u(0x1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_BITS   _u(0x00000002)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_MSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_LSB    _u(1)
+#define PADS_QSPI_GPIO_QSPI_SS_SCHMITT_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : PADS_QSPI_GPIO_QSPI_SS_SLEWFAST
+// Description : Slew rate control. 1 = Fast, 0 = Slow
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_RESET  _u(0x0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_BITS   _u(0x00000001)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_MSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_LSB    _u(0)
+#define PADS_QSPI_GPIO_QSPI_SS_SLEWFAST_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_PADS_QSPI_DEFINED
diff --git a/src/bootroms/shared/read_flash_sreg.S b/src/bootroms/shared/read_flash_sreg.S
new file mode 100644
index 000000000..1c68e49ba
--- /dev/null
+++ b/src/bootroms/shared/read_flash_sreg.S
@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT2_HELPER_READ_FLASH_SREG
+#define _BOOT2_HELPER_READ_FLASH_SREG
+
+#include "wait_ssi_ready.S"
+
+// Pass status read cmd into r0.
+// Returns status value in r0.
+.global read_flash_sreg
+.type read_flash_sreg,%function
+.thumb_func
+read_flash_sreg:
+    push {r1, lr}
+    str r0, [r3, #SSI_DR0_OFFSET]
+    // Dummy byte:
+    str r0, [r3, #SSI_DR0_OFFSET]
+    
+    bl wait_ssi_ready
+    // Discard first byte and combine the next two
+    ldr r0, [r3, #SSI_DR0_OFFSET]
+    ldr r0, [r3, #SSI_DR0_OFFSET]
+
+    pop {r1, pc}
+
+#endif
diff --git a/src/bootroms/shared/regs.h b/src/bootroms/shared/regs.h
new file mode 100644
index 000000000..d2bafd8d9
--- /dev/null
+++ b/src/bootroms/shared/regs.h
@@ -0,0 +1,11 @@
+#ifndef RP2040_STAGE2_REGS_H
+#define RP2040_STAGE2_REGS_H
+
+#define _u(x) x ## u
+
+#include "ssi.h"
+#include "pads_qspi.h"
+#include "addressmap.h"
+#include "m0plus.h"
+
+#endif // RP2040_STAGE2_REGS_H
\ No newline at end of file
diff --git a/src/bootroms/shared/ssi.h b/src/bootroms/shared/ssi.h
new file mode 100644
index 000000000..67fddc0a4
--- /dev/null
+++ b/src/bootroms/shared/ssi.h
@@ -0,0 +1,809 @@
+/**
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+// =============================================================================
+// Register block : SSI
+// Version        : 1
+// Bus type       : apb
+// Description    : DW_apb_ssi has the following features:
+//                  * APB interface – Allows for easy integration into a
+//                  DesignWare Synthesizable Components for AMBA 2
+//                  implementation.
+//                  * APB3 and APB4 protocol support.
+//                  * Scalable APB data bus width – Supports APB data bus widths
+//                  of 8, 16, and 32 bits.
+//                  * Serial-master or serial-slave operation – Enables serial
+//                  communication with serial-master or serial-slave peripheral
+//                  devices.
+//                  * Programmable Dual/Quad/Octal SPI support in Master Mode.
+//                  * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support -
+//                  Enables the DW_apb_ssi master to perform operations with the
+//                  device in DDR and RDS modes when working in Dual/Quad/Octal
+//                  mode of operation.
+//                  * Data Mask Support - Enables the DW_apb_ssi to selectively
+//                  update the bytes in the device. This feature is applicable
+//                  only in enhanced SPI modes.
+//                  * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi
+//                  master to behave as a memory mapped I/O and fetches the data
+//                  from the device based on the APB read request. This feature
+//                  is applicable only in enhanced SPI modes.
+//                  * DMA Controller Interface – Enables the DW_apb_ssi to
+//                  interface to a DMA controller over the bus using a
+//                  handshaking interface for transfer requests.
+//                  * Independent masking of interrupts – Master collision,
+//                  transmit FIFO overflow, transmit FIFO empty, receive FIFO
+//                  full, receive FIFO underflow, and receive FIFO overflow
+//                  interrupts can all be masked independently.
+//                  * Multi-master contention detection – Informs the processor
+//                  of multiple serial-master accesses on the serial bus.
+//                  * Bypass of meta-stability flip-flops for synchronous clocks
+//                  – When the APB clock (pclk) and the DW_apb_ssi serial clock
+//                  (ssi_clk) are synchronous, meta-stable flip-flops are not
+//                  used when transferring control signals across these clock
+//                  domains.
+//                  * Programmable delay on the sample time of the received
+//                  serial data bit (rxd); enables programmable control of
+//                  routing delays resulting in higher serial data-bit rates.
+//                  * Programmable features:
+//                  - Serial interface operation – Choice of Motorola SPI, Texas
+//                  Instruments Synchronous Serial Protocol or National
+//                  Semiconductor Microwire.
+//                  - Clock bit-rate – Dynamic control of the serial bit rate of
+//                  the data transfer; used in only serial-master mode of
+//                  operation.
+//                  - Data Item size (4 to 32 bits) – Item size of each data
+//                  transfer under the control of the programmer.
+//                  * Configured features:
+//                  - FIFO depth – 16 words deep. The FIFO width is fixed at 32
+//                  bits.
+//                  - 1 slave select output.
+//                  - Hardware slave-select – Dedicated hardware slave-select
+//                  line.
+//                  - Combined interrupt line - one combined interrupt line from
+//                  the DW_apb_ssi to the interrupt controller.
+//                  - Interrupt polarity – active high interrupt lines.
+//                  - Serial clock polarity – low serial-clock polarity directly
+//                  after reset.
+//                  - Serial clock phase – capture on first edge of serial-clock
+//                  directly after reset.
+// =============================================================================
+#ifndef HARDWARE_REGS_SSI_DEFINED
+#define HARDWARE_REGS_SSI_DEFINED
+// =============================================================================
+// Register    : SSI_CTRLR0
+// Description : Control register 0
+#define SSI_CTRLR0_OFFSET _u(0x00000000)
+#define SSI_CTRLR0_BITS   _u(0x017fffff)
+#define SSI_CTRLR0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SSTE
+// Description : Slave select toggle enable
+#define SSI_CTRLR0_SSTE_RESET  _u(0x0)
+#define SSI_CTRLR0_SSTE_BITS   _u(0x01000000)
+#define SSI_CTRLR0_SSTE_MSB    _u(24)
+#define SSI_CTRLR0_SSTE_LSB    _u(24)
+#define SSI_CTRLR0_SSTE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SPI_FRF
+// Description : SPI frame format
+//               0x0 -> Standard 1-bit SPI frame format; 1 bit per SCK,
+//               full-duplex
+//               0x1 -> Dual-SPI frame format; two bits per SCK, half-duplex
+//               0x2 -> Quad-SPI frame format; four bits per SCK, half-duplex
+#define SSI_CTRLR0_SPI_FRF_RESET      _u(0x0)
+#define SSI_CTRLR0_SPI_FRF_BITS       _u(0x00600000)
+#define SSI_CTRLR0_SPI_FRF_MSB        _u(22)
+#define SSI_CTRLR0_SPI_FRF_LSB        _u(21)
+#define SSI_CTRLR0_SPI_FRF_ACCESS     "RW"
+#define SSI_CTRLR0_SPI_FRF_VALUE_STD  _u(0x0)
+#define SSI_CTRLR0_SPI_FRF_VALUE_DUAL _u(0x1)
+#define SSI_CTRLR0_SPI_FRF_VALUE_QUAD _u(0x2)
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_DFS_32
+// Description : Data frame size in 32b transfer mode
+//               Value of n -> n+1 clocks per frame.
+#define SSI_CTRLR0_DFS_32_RESET  _u(0x00)
+#define SSI_CTRLR0_DFS_32_BITS   _u(0x001f0000)
+#define SSI_CTRLR0_DFS_32_MSB    _u(20)
+#define SSI_CTRLR0_DFS_32_LSB    _u(16)
+#define SSI_CTRLR0_DFS_32_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_CFS
+// Description : Control frame size
+//               Value of n -> n+1 clocks per frame.
+#define SSI_CTRLR0_CFS_RESET  _u(0x0)
+#define SSI_CTRLR0_CFS_BITS   _u(0x0000f000)
+#define SSI_CTRLR0_CFS_MSB    _u(15)
+#define SSI_CTRLR0_CFS_LSB    _u(12)
+#define SSI_CTRLR0_CFS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SRL
+// Description : Shift register loop (test mode)
+#define SSI_CTRLR0_SRL_RESET  _u(0x0)
+#define SSI_CTRLR0_SRL_BITS   _u(0x00000800)
+#define SSI_CTRLR0_SRL_MSB    _u(11)
+#define SSI_CTRLR0_SRL_LSB    _u(11)
+#define SSI_CTRLR0_SRL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SLV_OE
+// Description : Slave output enable
+#define SSI_CTRLR0_SLV_OE_RESET  _u(0x0)
+#define SSI_CTRLR0_SLV_OE_BITS   _u(0x00000400)
+#define SSI_CTRLR0_SLV_OE_MSB    _u(10)
+#define SSI_CTRLR0_SLV_OE_LSB    _u(10)
+#define SSI_CTRLR0_SLV_OE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_TMOD
+// Description : Transfer mode
+//               0x0 -> Both transmit and receive
+//               0x1 -> Transmit only (not for FRF == 0, standard SPI mode)
+//               0x2 -> Receive only (not for FRF == 0, standard SPI mode)
+//               0x3 -> EEPROM read mode (TX then RX; RX starts after control
+//               data TX'd)
+#define SSI_CTRLR0_TMOD_RESET             _u(0x0)
+#define SSI_CTRLR0_TMOD_BITS              _u(0x00000300)
+#define SSI_CTRLR0_TMOD_MSB               _u(9)
+#define SSI_CTRLR0_TMOD_LSB               _u(8)
+#define SSI_CTRLR0_TMOD_ACCESS            "RW"
+#define SSI_CTRLR0_TMOD_VALUE_TX_AND_RX   _u(0x0)
+#define SSI_CTRLR0_TMOD_VALUE_TX_ONLY     _u(0x1)
+#define SSI_CTRLR0_TMOD_VALUE_RX_ONLY     _u(0x2)
+#define SSI_CTRLR0_TMOD_VALUE_EEPROM_READ _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SCPOL
+// Description : Serial clock polarity
+#define SSI_CTRLR0_SCPOL_RESET  _u(0x0)
+#define SSI_CTRLR0_SCPOL_BITS   _u(0x00000080)
+#define SSI_CTRLR0_SCPOL_MSB    _u(7)
+#define SSI_CTRLR0_SCPOL_LSB    _u(7)
+#define SSI_CTRLR0_SCPOL_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_SCPH
+// Description : Serial clock phase
+#define SSI_CTRLR0_SCPH_RESET  _u(0x0)
+#define SSI_CTRLR0_SCPH_BITS   _u(0x00000040)
+#define SSI_CTRLR0_SCPH_MSB    _u(6)
+#define SSI_CTRLR0_SCPH_LSB    _u(6)
+#define SSI_CTRLR0_SCPH_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_FRF
+// Description : Frame format
+#define SSI_CTRLR0_FRF_RESET  _u(0x0)
+#define SSI_CTRLR0_FRF_BITS   _u(0x00000030)
+#define SSI_CTRLR0_FRF_MSB    _u(5)
+#define SSI_CTRLR0_FRF_LSB    _u(4)
+#define SSI_CTRLR0_FRF_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR0_DFS
+// Description : Data frame size
+#define SSI_CTRLR0_DFS_RESET  _u(0x0)
+#define SSI_CTRLR0_DFS_BITS   _u(0x0000000f)
+#define SSI_CTRLR0_DFS_MSB    _u(3)
+#define SSI_CTRLR0_DFS_LSB    _u(0)
+#define SSI_CTRLR0_DFS_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_CTRLR1
+// Description : Master Control register 1
+#define SSI_CTRLR1_OFFSET _u(0x00000004)
+#define SSI_CTRLR1_BITS   _u(0x0000ffff)
+#define SSI_CTRLR1_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_CTRLR1_NDF
+// Description : Number of data frames
+#define SSI_CTRLR1_NDF_RESET  _u(0x0000)
+#define SSI_CTRLR1_NDF_BITS   _u(0x0000ffff)
+#define SSI_CTRLR1_NDF_MSB    _u(15)
+#define SSI_CTRLR1_NDF_LSB    _u(0)
+#define SSI_CTRLR1_NDF_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_SSIENR
+// Description : SSI Enable
+#define SSI_SSIENR_OFFSET _u(0x00000008)
+#define SSI_SSIENR_BITS   _u(0x00000001)
+#define SSI_SSIENR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_SSIENR_SSI_EN
+// Description : SSI enable
+#define SSI_SSIENR_SSI_EN_RESET  _u(0x0)
+#define SSI_SSIENR_SSI_EN_BITS   _u(0x00000001)
+#define SSI_SSIENR_SSI_EN_MSB    _u(0)
+#define SSI_SSIENR_SSI_EN_LSB    _u(0)
+#define SSI_SSIENR_SSI_EN_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_MWCR
+// Description : Microwire Control
+#define SSI_MWCR_OFFSET _u(0x0000000c)
+#define SSI_MWCR_BITS   _u(0x00000007)
+#define SSI_MWCR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_MWCR_MHS
+// Description : Microwire handshaking
+#define SSI_MWCR_MHS_RESET  _u(0x0)
+#define SSI_MWCR_MHS_BITS   _u(0x00000004)
+#define SSI_MWCR_MHS_MSB    _u(2)
+#define SSI_MWCR_MHS_LSB    _u(2)
+#define SSI_MWCR_MHS_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_MWCR_MDD
+// Description : Microwire control
+#define SSI_MWCR_MDD_RESET  _u(0x0)
+#define SSI_MWCR_MDD_BITS   _u(0x00000002)
+#define SSI_MWCR_MDD_MSB    _u(1)
+#define SSI_MWCR_MDD_LSB    _u(1)
+#define SSI_MWCR_MDD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_MWCR_MWMOD
+// Description : Microwire transfer mode
+#define SSI_MWCR_MWMOD_RESET  _u(0x0)
+#define SSI_MWCR_MWMOD_BITS   _u(0x00000001)
+#define SSI_MWCR_MWMOD_MSB    _u(0)
+#define SSI_MWCR_MWMOD_LSB    _u(0)
+#define SSI_MWCR_MWMOD_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_SER
+// Description : Slave enable
+//               For each bit:
+//               0 -> slave not selected
+//               1 -> slave selected
+#define SSI_SER_OFFSET _u(0x00000010)
+#define SSI_SER_BITS   _u(0x00000001)
+#define SSI_SER_RESET  _u(0x00000000)
+#define SSI_SER_MSB    _u(0)
+#define SSI_SER_LSB    _u(0)
+#define SSI_SER_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_BAUDR
+// Description : Baud rate
+#define SSI_BAUDR_OFFSET _u(0x00000014)
+#define SSI_BAUDR_BITS   _u(0x0000ffff)
+#define SSI_BAUDR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_BAUDR_SCKDV
+// Description : SSI clock divider
+#define SSI_BAUDR_SCKDV_RESET  _u(0x0000)
+#define SSI_BAUDR_SCKDV_BITS   _u(0x0000ffff)
+#define SSI_BAUDR_SCKDV_MSB    _u(15)
+#define SSI_BAUDR_SCKDV_LSB    _u(0)
+#define SSI_BAUDR_SCKDV_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_TXFTLR
+// Description : TX FIFO threshold level
+#define SSI_TXFTLR_OFFSET _u(0x00000018)
+#define SSI_TXFTLR_BITS   _u(0x000000ff)
+#define SSI_TXFTLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_TXFTLR_TFT
+// Description : Transmit FIFO threshold
+#define SSI_TXFTLR_TFT_RESET  _u(0x00)
+#define SSI_TXFTLR_TFT_BITS   _u(0x000000ff)
+#define SSI_TXFTLR_TFT_MSB    _u(7)
+#define SSI_TXFTLR_TFT_LSB    _u(0)
+#define SSI_TXFTLR_TFT_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_RXFTLR
+// Description : RX FIFO threshold level
+#define SSI_RXFTLR_OFFSET _u(0x0000001c)
+#define SSI_RXFTLR_BITS   _u(0x000000ff)
+#define SSI_RXFTLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_RXFTLR_RFT
+// Description : Receive FIFO threshold
+#define SSI_RXFTLR_RFT_RESET  _u(0x00)
+#define SSI_RXFTLR_RFT_BITS   _u(0x000000ff)
+#define SSI_RXFTLR_RFT_MSB    _u(7)
+#define SSI_RXFTLR_RFT_LSB    _u(0)
+#define SSI_RXFTLR_RFT_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_TXFLR
+// Description : TX FIFO level
+#define SSI_TXFLR_OFFSET _u(0x00000020)
+#define SSI_TXFLR_BITS   _u(0x000000ff)
+#define SSI_TXFLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_TXFLR_TFTFL
+// Description : Transmit FIFO level
+#define SSI_TXFLR_TFTFL_RESET  _u(0x00)
+#define SSI_TXFLR_TFTFL_BITS   _u(0x000000ff)
+#define SSI_TXFLR_TFTFL_MSB    _u(7)
+#define SSI_TXFLR_TFTFL_LSB    _u(0)
+#define SSI_TXFLR_TFTFL_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_RXFLR
+// Description : RX FIFO level
+#define SSI_RXFLR_OFFSET _u(0x00000024)
+#define SSI_RXFLR_BITS   _u(0x000000ff)
+#define SSI_RXFLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_RXFLR_RXTFL
+// Description : Receive FIFO level
+#define SSI_RXFLR_RXTFL_RESET  _u(0x00)
+#define SSI_RXFLR_RXTFL_BITS   _u(0x000000ff)
+#define SSI_RXFLR_RXTFL_MSB    _u(7)
+#define SSI_RXFLR_RXTFL_LSB    _u(0)
+#define SSI_RXFLR_RXTFL_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_SR
+// Description : Status register
+#define SSI_SR_OFFSET _u(0x00000028)
+#define SSI_SR_BITS   _u(0x0000007f)
+#define SSI_SR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_DCOL
+// Description : Data collision error
+#define SSI_SR_DCOL_RESET  _u(0x0)
+#define SSI_SR_DCOL_BITS   _u(0x00000040)
+#define SSI_SR_DCOL_MSB    _u(6)
+#define SSI_SR_DCOL_LSB    _u(6)
+#define SSI_SR_DCOL_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_TXE
+// Description : Transmission error
+#define SSI_SR_TXE_RESET  _u(0x0)
+#define SSI_SR_TXE_BITS   _u(0x00000020)
+#define SSI_SR_TXE_MSB    _u(5)
+#define SSI_SR_TXE_LSB    _u(5)
+#define SSI_SR_TXE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_RFF
+// Description : Receive FIFO full
+#define SSI_SR_RFF_RESET  _u(0x0)
+#define SSI_SR_RFF_BITS   _u(0x00000010)
+#define SSI_SR_RFF_MSB    _u(4)
+#define SSI_SR_RFF_LSB    _u(4)
+#define SSI_SR_RFF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_RFNE
+// Description : Receive FIFO not empty
+#define SSI_SR_RFNE_RESET  _u(0x0)
+#define SSI_SR_RFNE_BITS   _u(0x00000008)
+#define SSI_SR_RFNE_MSB    _u(3)
+#define SSI_SR_RFNE_LSB    _u(3)
+#define SSI_SR_RFNE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_TFE
+// Description : Transmit FIFO empty
+#define SSI_SR_TFE_RESET  _u(0x0)
+#define SSI_SR_TFE_BITS   _u(0x00000004)
+#define SSI_SR_TFE_MSB    _u(2)
+#define SSI_SR_TFE_LSB    _u(2)
+#define SSI_SR_TFE_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_TFNF
+// Description : Transmit FIFO not full
+#define SSI_SR_TFNF_RESET  _u(0x0)
+#define SSI_SR_TFNF_BITS   _u(0x00000002)
+#define SSI_SR_TFNF_MSB    _u(1)
+#define SSI_SR_TFNF_LSB    _u(1)
+#define SSI_SR_TFNF_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SR_BUSY
+// Description : SSI busy flag
+#define SSI_SR_BUSY_RESET  _u(0x0)
+#define SSI_SR_BUSY_BITS   _u(0x00000001)
+#define SSI_SR_BUSY_MSB    _u(0)
+#define SSI_SR_BUSY_LSB    _u(0)
+#define SSI_SR_BUSY_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_IMR
+// Description : Interrupt mask
+#define SSI_IMR_OFFSET _u(0x0000002c)
+#define SSI_IMR_BITS   _u(0x0000003f)
+#define SSI_IMR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_MSTIM
+// Description : Multi-master contention interrupt mask
+#define SSI_IMR_MSTIM_RESET  _u(0x0)
+#define SSI_IMR_MSTIM_BITS   _u(0x00000020)
+#define SSI_IMR_MSTIM_MSB    _u(5)
+#define SSI_IMR_MSTIM_LSB    _u(5)
+#define SSI_IMR_MSTIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_RXFIM
+// Description : Receive FIFO full interrupt mask
+#define SSI_IMR_RXFIM_RESET  _u(0x0)
+#define SSI_IMR_RXFIM_BITS   _u(0x00000010)
+#define SSI_IMR_RXFIM_MSB    _u(4)
+#define SSI_IMR_RXFIM_LSB    _u(4)
+#define SSI_IMR_RXFIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_RXOIM
+// Description : Receive FIFO overflow interrupt mask
+#define SSI_IMR_RXOIM_RESET  _u(0x0)
+#define SSI_IMR_RXOIM_BITS   _u(0x00000008)
+#define SSI_IMR_RXOIM_MSB    _u(3)
+#define SSI_IMR_RXOIM_LSB    _u(3)
+#define SSI_IMR_RXOIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_RXUIM
+// Description : Receive FIFO underflow interrupt mask
+#define SSI_IMR_RXUIM_RESET  _u(0x0)
+#define SSI_IMR_RXUIM_BITS   _u(0x00000004)
+#define SSI_IMR_RXUIM_MSB    _u(2)
+#define SSI_IMR_RXUIM_LSB    _u(2)
+#define SSI_IMR_RXUIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_TXOIM
+// Description : Transmit FIFO overflow interrupt mask
+#define SSI_IMR_TXOIM_RESET  _u(0x0)
+#define SSI_IMR_TXOIM_BITS   _u(0x00000002)
+#define SSI_IMR_TXOIM_MSB    _u(1)
+#define SSI_IMR_TXOIM_LSB    _u(1)
+#define SSI_IMR_TXOIM_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_IMR_TXEIM
+// Description : Transmit FIFO empty interrupt mask
+#define SSI_IMR_TXEIM_RESET  _u(0x0)
+#define SSI_IMR_TXEIM_BITS   _u(0x00000001)
+#define SSI_IMR_TXEIM_MSB    _u(0)
+#define SSI_IMR_TXEIM_LSB    _u(0)
+#define SSI_IMR_TXEIM_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_ISR
+// Description : Interrupt status
+#define SSI_ISR_OFFSET _u(0x00000030)
+#define SSI_ISR_BITS   _u(0x0000003f)
+#define SSI_ISR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_MSTIS
+// Description : Multi-master contention interrupt status
+#define SSI_ISR_MSTIS_RESET  _u(0x0)
+#define SSI_ISR_MSTIS_BITS   _u(0x00000020)
+#define SSI_ISR_MSTIS_MSB    _u(5)
+#define SSI_ISR_MSTIS_LSB    _u(5)
+#define SSI_ISR_MSTIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_RXFIS
+// Description : Receive FIFO full interrupt status
+#define SSI_ISR_RXFIS_RESET  _u(0x0)
+#define SSI_ISR_RXFIS_BITS   _u(0x00000010)
+#define SSI_ISR_RXFIS_MSB    _u(4)
+#define SSI_ISR_RXFIS_LSB    _u(4)
+#define SSI_ISR_RXFIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_RXOIS
+// Description : Receive FIFO overflow interrupt status
+#define SSI_ISR_RXOIS_RESET  _u(0x0)
+#define SSI_ISR_RXOIS_BITS   _u(0x00000008)
+#define SSI_ISR_RXOIS_MSB    _u(3)
+#define SSI_ISR_RXOIS_LSB    _u(3)
+#define SSI_ISR_RXOIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_RXUIS
+// Description : Receive FIFO underflow interrupt status
+#define SSI_ISR_RXUIS_RESET  _u(0x0)
+#define SSI_ISR_RXUIS_BITS   _u(0x00000004)
+#define SSI_ISR_RXUIS_MSB    _u(2)
+#define SSI_ISR_RXUIS_LSB    _u(2)
+#define SSI_ISR_RXUIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_TXOIS
+// Description : Transmit FIFO overflow interrupt status
+#define SSI_ISR_TXOIS_RESET  _u(0x0)
+#define SSI_ISR_TXOIS_BITS   _u(0x00000002)
+#define SSI_ISR_TXOIS_MSB    _u(1)
+#define SSI_ISR_TXOIS_LSB    _u(1)
+#define SSI_ISR_TXOIS_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_ISR_TXEIS
+// Description : Transmit FIFO empty interrupt status
+#define SSI_ISR_TXEIS_RESET  _u(0x0)
+#define SSI_ISR_TXEIS_BITS   _u(0x00000001)
+#define SSI_ISR_TXEIS_MSB    _u(0)
+#define SSI_ISR_TXEIS_LSB    _u(0)
+#define SSI_ISR_TXEIS_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_RISR
+// Description : Raw interrupt status
+#define SSI_RISR_OFFSET _u(0x00000034)
+#define SSI_RISR_BITS   _u(0x0000003f)
+#define SSI_RISR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_MSTIR
+// Description : Multi-master contention raw interrupt status
+#define SSI_RISR_MSTIR_RESET  _u(0x0)
+#define SSI_RISR_MSTIR_BITS   _u(0x00000020)
+#define SSI_RISR_MSTIR_MSB    _u(5)
+#define SSI_RISR_MSTIR_LSB    _u(5)
+#define SSI_RISR_MSTIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_RXFIR
+// Description : Receive FIFO full raw interrupt status
+#define SSI_RISR_RXFIR_RESET  _u(0x0)
+#define SSI_RISR_RXFIR_BITS   _u(0x00000010)
+#define SSI_RISR_RXFIR_MSB    _u(4)
+#define SSI_RISR_RXFIR_LSB    _u(4)
+#define SSI_RISR_RXFIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_RXOIR
+// Description : Receive FIFO overflow raw interrupt status
+#define SSI_RISR_RXOIR_RESET  _u(0x0)
+#define SSI_RISR_RXOIR_BITS   _u(0x00000008)
+#define SSI_RISR_RXOIR_MSB    _u(3)
+#define SSI_RISR_RXOIR_LSB    _u(3)
+#define SSI_RISR_RXOIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_RXUIR
+// Description : Receive FIFO underflow raw interrupt status
+#define SSI_RISR_RXUIR_RESET  _u(0x0)
+#define SSI_RISR_RXUIR_BITS   _u(0x00000004)
+#define SSI_RISR_RXUIR_MSB    _u(2)
+#define SSI_RISR_RXUIR_LSB    _u(2)
+#define SSI_RISR_RXUIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_TXOIR
+// Description : Transmit FIFO overflow raw interrupt status
+#define SSI_RISR_TXOIR_RESET  _u(0x0)
+#define SSI_RISR_TXOIR_BITS   _u(0x00000002)
+#define SSI_RISR_TXOIR_MSB    _u(1)
+#define SSI_RISR_TXOIR_LSB    _u(1)
+#define SSI_RISR_TXOIR_ACCESS "RO"
+// -----------------------------------------------------------------------------
+// Field       : SSI_RISR_TXEIR
+// Description : Transmit FIFO empty raw interrupt status
+#define SSI_RISR_TXEIR_RESET  _u(0x0)
+#define SSI_RISR_TXEIR_BITS   _u(0x00000001)
+#define SSI_RISR_TXEIR_MSB    _u(0)
+#define SSI_RISR_TXEIR_LSB    _u(0)
+#define SSI_RISR_TXEIR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_TXOICR
+// Description : TX FIFO overflow interrupt clear
+//               Clear-on-read transmit FIFO overflow interrupt
+#define SSI_TXOICR_OFFSET _u(0x00000038)
+#define SSI_TXOICR_BITS   _u(0x00000001)
+#define SSI_TXOICR_RESET  _u(0x00000000)
+#define SSI_TXOICR_MSB    _u(0)
+#define SSI_TXOICR_LSB    _u(0)
+#define SSI_TXOICR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_RXOICR
+// Description : RX FIFO overflow interrupt clear
+//               Clear-on-read receive FIFO overflow interrupt
+#define SSI_RXOICR_OFFSET _u(0x0000003c)
+#define SSI_RXOICR_BITS   _u(0x00000001)
+#define SSI_RXOICR_RESET  _u(0x00000000)
+#define SSI_RXOICR_MSB    _u(0)
+#define SSI_RXOICR_LSB    _u(0)
+#define SSI_RXOICR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_RXUICR
+// Description : RX FIFO underflow interrupt clear
+//               Clear-on-read receive FIFO underflow interrupt
+#define SSI_RXUICR_OFFSET _u(0x00000040)
+#define SSI_RXUICR_BITS   _u(0x00000001)
+#define SSI_RXUICR_RESET  _u(0x00000000)
+#define SSI_RXUICR_MSB    _u(0)
+#define SSI_RXUICR_LSB    _u(0)
+#define SSI_RXUICR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_MSTICR
+// Description : Multi-master interrupt clear
+//               Clear-on-read multi-master contention interrupt
+#define SSI_MSTICR_OFFSET _u(0x00000044)
+#define SSI_MSTICR_BITS   _u(0x00000001)
+#define SSI_MSTICR_RESET  _u(0x00000000)
+#define SSI_MSTICR_MSB    _u(0)
+#define SSI_MSTICR_LSB    _u(0)
+#define SSI_MSTICR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_ICR
+// Description : Interrupt clear
+//               Clear-on-read all active interrupts
+#define SSI_ICR_OFFSET _u(0x00000048)
+#define SSI_ICR_BITS   _u(0x00000001)
+#define SSI_ICR_RESET  _u(0x00000000)
+#define SSI_ICR_MSB    _u(0)
+#define SSI_ICR_LSB    _u(0)
+#define SSI_ICR_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_DMACR
+// Description : DMA control
+#define SSI_DMACR_OFFSET _u(0x0000004c)
+#define SSI_DMACR_BITS   _u(0x00000003)
+#define SSI_DMACR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_DMACR_TDMAE
+// Description : Transmit DMA enable
+#define SSI_DMACR_TDMAE_RESET  _u(0x0)
+#define SSI_DMACR_TDMAE_BITS   _u(0x00000002)
+#define SSI_DMACR_TDMAE_MSB    _u(1)
+#define SSI_DMACR_TDMAE_LSB    _u(1)
+#define SSI_DMACR_TDMAE_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_DMACR_RDMAE
+// Description : Receive DMA enable
+#define SSI_DMACR_RDMAE_RESET  _u(0x0)
+#define SSI_DMACR_RDMAE_BITS   _u(0x00000001)
+#define SSI_DMACR_RDMAE_MSB    _u(0)
+#define SSI_DMACR_RDMAE_LSB    _u(0)
+#define SSI_DMACR_RDMAE_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_DMATDLR
+// Description : DMA TX data level
+#define SSI_DMATDLR_OFFSET _u(0x00000050)
+#define SSI_DMATDLR_BITS   _u(0x000000ff)
+#define SSI_DMATDLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_DMATDLR_DMATDL
+// Description : Transmit data watermark level
+#define SSI_DMATDLR_DMATDL_RESET  _u(0x00)
+#define SSI_DMATDLR_DMATDL_BITS   _u(0x000000ff)
+#define SSI_DMATDLR_DMATDL_MSB    _u(7)
+#define SSI_DMATDLR_DMATDL_LSB    _u(0)
+#define SSI_DMATDLR_DMATDL_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_DMARDLR
+// Description : DMA RX data level
+#define SSI_DMARDLR_OFFSET _u(0x00000054)
+#define SSI_DMARDLR_BITS   _u(0x000000ff)
+#define SSI_DMARDLR_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_DMARDLR_DMARDL
+// Description : Receive data watermark level (DMARDLR+1)
+#define SSI_DMARDLR_DMARDL_RESET  _u(0x00)
+#define SSI_DMARDLR_DMARDL_BITS   _u(0x000000ff)
+#define SSI_DMARDLR_DMARDL_MSB    _u(7)
+#define SSI_DMARDLR_DMARDL_LSB    _u(0)
+#define SSI_DMARDLR_DMARDL_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_IDR
+// Description : Identification register
+#define SSI_IDR_OFFSET _u(0x00000058)
+#define SSI_IDR_BITS   _u(0xffffffff)
+#define SSI_IDR_RESET  _u(0x51535049)
+// -----------------------------------------------------------------------------
+// Field       : SSI_IDR_IDCODE
+// Description : Peripheral dentification code
+#define SSI_IDR_IDCODE_RESET  _u(0x51535049)
+#define SSI_IDR_IDCODE_BITS   _u(0xffffffff)
+#define SSI_IDR_IDCODE_MSB    _u(31)
+#define SSI_IDR_IDCODE_LSB    _u(0)
+#define SSI_IDR_IDCODE_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_SSI_VERSION_ID
+// Description : Version ID
+#define SSI_SSI_VERSION_ID_OFFSET _u(0x0000005c)
+#define SSI_SSI_VERSION_ID_BITS   _u(0xffffffff)
+#define SSI_SSI_VERSION_ID_RESET  _u(0x3430312a)
+// -----------------------------------------------------------------------------
+// Field       : SSI_SSI_VERSION_ID_SSI_COMP_VERSION
+// Description : SNPS component version (format X.YY)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_RESET  _u(0x3430312a)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_BITS   _u(0xffffffff)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_MSB    _u(31)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_LSB    _u(0)
+#define SSI_SSI_VERSION_ID_SSI_COMP_VERSION_ACCESS "RO"
+// =============================================================================
+// Register    : SSI_DR0
+// Description : Data Register 0 (of 36)
+#define SSI_DR0_OFFSET _u(0x00000060)
+#define SSI_DR0_BITS   _u(0xffffffff)
+#define SSI_DR0_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_DR0_DR
+// Description : First data register of 36
+#define SSI_DR0_DR_RESET  _u(0x00000000)
+#define SSI_DR0_DR_BITS   _u(0xffffffff)
+#define SSI_DR0_DR_MSB    _u(31)
+#define SSI_DR0_DR_LSB    _u(0)
+#define SSI_DR0_DR_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_RX_SAMPLE_DLY
+// Description : RX sample delay
+#define SSI_RX_SAMPLE_DLY_OFFSET _u(0x000000f0)
+#define SSI_RX_SAMPLE_DLY_BITS   _u(0x000000ff)
+#define SSI_RX_SAMPLE_DLY_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_RX_SAMPLE_DLY_RSD
+// Description : RXD sample delay (in SCLK cycles)
+#define SSI_RX_SAMPLE_DLY_RSD_RESET  _u(0x00)
+#define SSI_RX_SAMPLE_DLY_RSD_BITS   _u(0x000000ff)
+#define SSI_RX_SAMPLE_DLY_RSD_MSB    _u(7)
+#define SSI_RX_SAMPLE_DLY_RSD_LSB    _u(0)
+#define SSI_RX_SAMPLE_DLY_RSD_ACCESS "RW"
+// =============================================================================
+// Register    : SSI_SPI_CTRLR0
+// Description : SPI control
+#define SSI_SPI_CTRLR0_OFFSET _u(0x000000f4)
+#define SSI_SPI_CTRLR0_BITS   _u(0xff07fb3f)
+#define SSI_SPI_CTRLR0_RESET  _u(0x03000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_XIP_CMD
+// Description : SPI Command to send in XIP mode (INST_L = 8-bit) or to append
+//               to Address (INST_L = 0-bit)
+#define SSI_SPI_CTRLR0_XIP_CMD_RESET  _u(0x03)
+#define SSI_SPI_CTRLR0_XIP_CMD_BITS   _u(0xff000000)
+#define SSI_SPI_CTRLR0_XIP_CMD_MSB    _u(31)
+#define SSI_SPI_CTRLR0_XIP_CMD_LSB    _u(24)
+#define SSI_SPI_CTRLR0_XIP_CMD_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_SPI_RXDS_EN
+// Description : Read data strobe enable
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_RESET  _u(0x0)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_BITS   _u(0x00040000)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_MSB    _u(18)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_LSB    _u(18)
+#define SSI_SPI_CTRLR0_SPI_RXDS_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_INST_DDR_EN
+// Description : Instruction DDR transfer enable
+#define SSI_SPI_CTRLR0_INST_DDR_EN_RESET  _u(0x0)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_BITS   _u(0x00020000)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_MSB    _u(17)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_LSB    _u(17)
+#define SSI_SPI_CTRLR0_INST_DDR_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_SPI_DDR_EN
+// Description : SPI DDR transfer enable
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_RESET  _u(0x0)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_BITS   _u(0x00010000)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_MSB    _u(16)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_LSB    _u(16)
+#define SSI_SPI_CTRLR0_SPI_DDR_EN_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_WAIT_CYCLES
+// Description : Wait cycles between control frame transmit and data reception
+//               (in SCLK cycles)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_RESET  _u(0x00)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_BITS   _u(0x0000f800)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_MSB    _u(15)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_LSB    _u(11)
+#define SSI_SPI_CTRLR0_WAIT_CYCLES_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_INST_L
+// Description : Instruction length (0/4/8/16b)
+//               0x0 -> No instruction
+//               0x1 -> 4-bit instruction
+//               0x2 -> 8-bit instruction
+//               0x3 -> 16-bit instruction
+#define SSI_SPI_CTRLR0_INST_L_RESET      _u(0x0)
+#define SSI_SPI_CTRLR0_INST_L_BITS       _u(0x00000300)
+#define SSI_SPI_CTRLR0_INST_L_MSB        _u(9)
+#define SSI_SPI_CTRLR0_INST_L_LSB        _u(8)
+#define SSI_SPI_CTRLR0_INST_L_ACCESS     "RW"
+#define SSI_SPI_CTRLR0_INST_L_VALUE_NONE _u(0x0)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_4B   _u(0x1)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_8B   _u(0x2)
+#define SSI_SPI_CTRLR0_INST_L_VALUE_16B  _u(0x3)
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_ADDR_L
+// Description : Address length (0b-60b in 4b increments)
+#define SSI_SPI_CTRLR0_ADDR_L_RESET  _u(0x0)
+#define SSI_SPI_CTRLR0_ADDR_L_BITS   _u(0x0000003c)
+#define SSI_SPI_CTRLR0_ADDR_L_MSB    _u(5)
+#define SSI_SPI_CTRLR0_ADDR_L_LSB    _u(2)
+#define SSI_SPI_CTRLR0_ADDR_L_ACCESS "RW"
+// -----------------------------------------------------------------------------
+// Field       : SSI_SPI_CTRLR0_TRANS_TYPE
+// Description : Address and instruction transfer format
+//               0x0 -> Command and address both in standard SPI frame format
+//               0x1 -> Command in standard SPI format, address in format
+//               specified by FRF
+//               0x2 -> Command and address both in format specified by FRF
+//               (e.g. Dual-SPI)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_RESET      _u(0x0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_BITS       _u(0x00000003)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_MSB        _u(1)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_LSB        _u(0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_ACCESS     "RW"
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C1A _u(0x0)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A _u(0x1)
+#define SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A _u(0x2)
+// =============================================================================
+// Register    : SSI_TXD_DRIVE_EDGE
+// Description : TX drive edge
+#define SSI_TXD_DRIVE_EDGE_OFFSET _u(0x000000f8)
+#define SSI_TXD_DRIVE_EDGE_BITS   _u(0x000000ff)
+#define SSI_TXD_DRIVE_EDGE_RESET  _u(0x00000000)
+// -----------------------------------------------------------------------------
+// Field       : SSI_TXD_DRIVE_EDGE_TDE
+// Description : TXD drive edge
+#define SSI_TXD_DRIVE_EDGE_TDE_RESET  _u(0x00)
+#define SSI_TXD_DRIVE_EDGE_TDE_BITS   _u(0x000000ff)
+#define SSI_TXD_DRIVE_EDGE_TDE_MSB    _u(7)
+#define SSI_TXD_DRIVE_EDGE_TDE_LSB    _u(0)
+#define SSI_TXD_DRIVE_EDGE_TDE_ACCESS "RW"
+// =============================================================================
+#endif // HARDWARE_REGS_SSI_DEFINED
diff --git a/src/bootroms/shared/stage2.ld b/src/bootroms/shared/stage2.ld
new file mode 100644
index 000000000..452281d12
--- /dev/null
+++ b/src/bootroms/shared/stage2.ld
@@ -0,0 +1,31 @@
+/*
+ * Target CPU:  ARM Cortex-M0+
+ * Target Chip: RP2040
+ */
+
+ENTRY(_stage2_boot);
+
+MEMORY
+{
+  flash0 (rx!w) : ORIGIN = 0x10000000, LENGTH = 0x00200000
+  ram0   (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00040000
+}
+
+SECTIONS
+{
+  .text : {
+    KEEP (*(.text))
+    *(.rodata*)
+  } > flash0
+
+  .ARM.exidx : {
+      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+  } >flash0
+
+
+  .data :
+  {
+     *(.data*)
+      *(.bss*)
+  } > ram0 /* AT> flash0 */
+}
diff --git a/src/bootroms/shared/wait_ssi_ready.S b/src/bootroms/shared/wait_ssi_ready.S
new file mode 100644
index 000000000..2e49b6489
--- /dev/null
+++ b/src/bootroms/shared/wait_ssi_ready.S
@@ -0,0 +1,26 @@
+/*
+ * Copyright (c) 2021 Raspberry Pi (Trading) Ltd.
+ *
+ * SPDX-License-Identifier: BSD-3-Clause
+ */
+
+#ifndef _BOOT2_HELPER_WAIT_SSI_READY
+#define _BOOT2_HELPER_WAIT_SSI_READY
+
+wait_ssi_ready:
+    push {r0, r1, lr}
+
+    // Command is complete when there is nothing left to send
+    // (TX FIFO empty) and SSI is no longer busy (CSn deasserted)
+1:
+    ldr r1, [r3, #SSI_SR_OFFSET]
+    movs r0, #SSI_SR_TFE_BITS
+    tst r1, r0
+    beq 1b
+    movs r0, #SSI_SR_BUSY_BITS
+    tst r1, r0
+    bne 1b
+
+    pop {r0, r1, pc}
+
+#endif
diff --git a/src/bootroms/w25q080.S b/src/bootroms/w25q080.S
new file mode 100644
index 000000000..566392632
--- /dev/null
+++ b/src/bootroms/w25q080.S
@@ -0,0 +1,280 @@
+// ----------------------------------------------------------------------------
+// Second stage boot code
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device:      Winbond W25Q080
+//              Also supports W25Q16JV (which has some different SR instructions)
+//              Also supports AT25SF081
+//              Also supports S25FL132K0
+//
+// Description: Configures W25Q080 to run in Quad I/O continuous read XIP mode
+//
+// Details:     * Check status register 2 to determine if QSPI mode is enabled,
+//                and perform an SR2 programming cycle if necessary.
+//              * Use SSI to perform a dummy 0xEB read command, with the mode
+//                continuation bits set, so that the flash will not require
+//                0xEB instruction prefix on subsequent reads.
+//              * Configure SSI to write address, mode bits, but no instruction.
+//                SSI + flash are now jointly in a state where continuous reads
+//                can take place.
+//              * Jump to exit pointer passed in via lr. Bootrom passes null,
+//                in which case this code uses a default 256 byte flash offset
+//
+// Building:    * This code must be position-independent, and use stack only
+//              * The code will be padded to a size of 256 bytes, including a
+//                4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "shared/asm_helper.S"
+#include "shared/regs.h"
+
+// ----------------------------------------------------------------------------
+// Config section
+// ----------------------------------------------------------------------------
+// It should be possible to support most flash devices by modifying this section
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be a positive, even integer.
+// The bootrom is very conservative with SPI frequency, but here we should be
+// as aggressive as possible.
+
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+#if PICO_FLASH_SPI_CLKDIV & 1
+#error PICO_FLASH_SPI_CLKDIV must be even
+#endif
+
+// Define interface width: single/dual/quad IO
+#define FRAME_FORMAT SSI_CTRLR0_SPI_FRF_VALUE_QUAD
+
+// For W25Q080 this is the "Read data fast quad IO" instruction:
+#define CMD_READ 0xeb
+
+// "Mode bits" are 8 special bits sent immediately after
+// the address bits in a "Read Data Fast Quad I/O" command sequence. 
+// On W25Q080, the four LSBs are don't care, and if MSBs == 0xa, the
+// next read does not require the 0xeb instruction prefix.
+#define MODE_CONTINUOUS_READ 0xa0
+
+// The number of address + mode bits, divided by 4 (always 4, not function of
+// interface width).
+#define ADDR_L 8
+
+// How many clocks of Hi-Z following the mode bits. For W25Q080, 4 dummy cycles
+// are required.
+#define WAIT_CYCLES 4
+
+// If defined, we will read status reg, compare to SREG_DATA, and overwrite
+// with our value if the SR doesn't match.
+// We do a two-byte write to SR1 (01h cmd) rather than a one-byte write to
+// SR2 (31h cmd) as the latter command isn't supported by WX25Q080.
+// This isn't great because it will remove block protections.
+// A better solution is to use a volatile SR write if your device supports it.
+#define PROGRAM_STATUS_REG
+
+#define CMD_WRITE_ENABLE 0x06
+#define CMD_READ_STATUS 0x05
+#define CMD_READ_STATUS2 0x35
+#define CMD_WRITE_STATUS 0x01
+#define SREG_DATA 0x02  // Enable quad-SPI mode
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+pico_default_asm_setup
+
+.section .text
+
+// The exit point is passed in lr. If entered from bootrom, this will be the
+// flash address immediately following this second stage (0x10000100).
+// Otherwise it will be a return address -- second stage being called as a
+// function by user code, after copying out of XIP region. r3 holds SSI base,
+// r0...2 used as temporaries. Other GPRs not used.
+regular_func _stage2_boot
+    push {lr}
+
+    // Set pad configuration:
+    // - SCLK 8mA drive, no slew limiting
+    // - SDx disable input Schmitt to reduce delay
+
+    ldr r3, =PADS_QSPI_BASE
+    movs r0, #(2 << PADS_QSPI_GPIO_QSPI_SCLK_DRIVE_LSB | PADS_QSPI_GPIO_QSPI_SCLK_SLEWFAST_BITS)
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SCLK_OFFSET]
+    ldr r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+    movs r1, #PADS_QSPI_GPIO_QSPI_SD0_SCHMITT_BITS
+    bics r0, r1
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD0_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD1_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD2_OFFSET]
+    str r0, [r3, #PADS_QSPI_GPIO_QSPI_SD3_OFFSET]
+
+    ldr r3, =XIP_SSI_BASE
+
+    // Disable SSI to allow further config
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Set baud rate
+    movs r1, #PICO_FLASH_SPI_CLKDIV
+    str r1, [r3, #SSI_BAUDR_OFFSET]
+
+    // Set 1-cycle sample delay. If PICO_FLASH_SPI_CLKDIV == 2 then this means,
+    // if the flash launches data on SCLK posedge, we capture it at the time that
+    // the next SCLK posedge is launched. This is shortly before that posedge
+    // arrives at the flash, so data hold time should be ok. For
+    // PICO_FLASH_SPI_CLKDIV > 2 this pretty much has no effect.
+
+    movs r1, #1
+    movs r2, #SSI_RX_SAMPLE_DLY_OFFSET  // == 0xf0 so need 8 bits of offset significance
+    str r1, [r3, r2]
+
+
+// On QSPI parts we usually need a 01h SR-write command to enable QSPI mode
+// (i.e. turn WPn and HOLDn into IO2/IO3)
+#ifdef PROGRAM_STATUS_REG
+program_sregs:
+#define CTRL0_SPI_TXRX \
+    (7 << SSI_CTRLR0_DFS_32_LSB) | /* 8 bits per data frame */ \
+    (SSI_CTRLR0_TMOD_VALUE_TX_AND_RX << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRL0_SPI_TXRX)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+     // Enable SSI and select slave 0
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    // Check whether SR needs updating
+    movs r0, #CMD_READ_STATUS2
+    bl read_flash_sreg
+    movs r2, #SREG_DATA
+    cmp r0, r2
+    beq skip_sreg_programming
+
+    // Send write enable command
+    movs r1, #CMD_WRITE_ENABLE
+    str r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll for completion and discard RX
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Send status write command followed by data bytes
+    movs r1, #CMD_WRITE_STATUS
+    str r1, [r3, #SSI_DR0_OFFSET]
+    movs r0, #0
+    str r0, [r3, #SSI_DR0_OFFSET]
+    str r2, [r3, #SSI_DR0_OFFSET]
+
+    bl wait_ssi_ready
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+    ldr r1, [r3, #SSI_DR0_OFFSET]
+
+    // Poll status register for write completion
+1:
+    movs r0, #CMD_READ_STATUS
+    bl read_flash_sreg
+    movs r1, #1
+    tst r0, r1
+    bne 1b
+
+skip_sreg_programming:
+
+    // Disable SSI again so that it can be reconfigured
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+#endif
+
+// Currently the flash expects an 8 bit serial command prefix on every
+// transfer, which is a waste of cycles. Perform a dummy Fast Read Quad I/O
+// command, with mode bits set such that the flash will not expect a serial
+// command prefix on *subsequent* transfers. We don't care about the results
+// of the read, the important part is the mode bits.
+
+dummy_read:
+#define CTRLR0_ENTER_XIP \
+    (FRAME_FORMAT                          /* Quad I/O mode */                \
+        << SSI_CTRLR0_SPI_FRF_LSB) |                                          \
+    (31 << SSI_CTRLR0_DFS_32_LSB)  |       /* 32 data bits */                 \
+    (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ     /* Send INST/ADDR, Receive Data */ \
+        << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRLR0_ENTER_XIP)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+    movs r1, #0x0                    // NDF=0 (single 32b read)
+    str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+#define SPI_CTRLR0_ENTER_XIP \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |     /* Address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) | /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_8B \
+        << SSI_SPI_CTRLR0_INST_L_LSB) |        /* 8-bit instruction */ \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A      /* Send Command in serial mode then address in Quad I/O mode */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_ENTER_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)  // SPI_CTRL0 Register
+    str r1, [r0]
+
+    movs r1, #1                      // Re-enable SSI
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    movs r1, #CMD_READ
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push SPI command into TX FIFO
+    movs r1, #MODE_CONTINUOUS_READ   // 32-bit: 24 address bits (we don't care, so 0) and M[7:4]=1010
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push Address into TX FIFO - this will trigger the transaction
+
+    // Poll for completion
+    bl wait_ssi_ready
+
+// The flash is in a state where we can blast addresses in parallel, and get
+// parallel data back. Now configure the SSI to translate XIP bus accesses
+// into QSPI transfers of this form.
+
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Disable SSI (and clear FIFO) to allow further config
+
+// Note that the INST_L field is used to select what XIP data gets pushed into
+// the TX FIFO:
+//      INST_L_0_BITS   {ADDR[23:0],XIP_CMD[7:0]}       Load "mode bits" into XIP_CMD
+//      Anything else   {XIP_CMD[7:0],ADDR[23:0]}       Load SPI command into XIP_CMD
+configure_ssi:
+#define SPI_CTRLR0_XIP \
+    (MODE_CONTINUOUS_READ                      /* Mode bits to keep flash in continuous read mode */ \
+        << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
+    (ADDR_L << SSI_SPI_CTRLR0_ADDR_L_LSB) |    /* Total number of address + mode bits */ \
+    (WAIT_CYCLES << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |    /* Hi-Z dummy clocks following address + mode */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_NONE          /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
+        << SSI_SPI_CTRLR0_INST_L_LSB) | \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A      /* Send Address in Quad I/O mode (and Command but that is zero bits long) */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+    str r1, [r0]
+
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Re-enable SSI
+
+// Bus accesses to the XIP window will now be transparently serviced by the
+// external flash on cache miss. We are ready to run code from flash.
+
+// Pull in standard exit routine
+#include "shared/exit_from_boot2.S"
+
+// Common functions
+#include "shared/wait_ssi_ready.S"
+#ifdef PROGRAM_STATUS_REG
+#include "shared/read_flash_sreg.S"
+#endif
+
+.global literals
+literals:
+.ltorg
+
+.end
diff --git a/src/bootroms/w25x10cl.S b/src/bootroms/w25x10cl.S
new file mode 100644
index 000000000..aab3f897f
--- /dev/null
+++ b/src/bootroms/w25x10cl.S
@@ -0,0 +1,191 @@
+// ----------------------------------------------------------------------------
+// Second stage boot code
+// Copyright (c) 2019-2021 Raspberry Pi (Trading) Ltd.
+// SPDX-License-Identifier: BSD-3-Clause
+//
+// Device:      Winbond W25X10CL
+//
+// Description: Configures W25X10CL to run in Dual I/O continuous read XIP mode
+//
+// Details:     * Disable SSI
+//              * Configure SSI to generate 8b command + 28b address + 2 wait,
+//                with address and data using dual SPI mode
+//              * Enable SSI
+//              * Generate dummy read with command = 0xBB, top 24b of address
+//                of 0x000000 followed by M[7:0]=0010zzzz (with the HiZ being
+//                generated by 2 wait cycles).  This leaves the W25X10CL in
+//                continuous read mode
+//              * Disable SSI
+//              * Configure SSI to generate 0b command + 28b address + 2 wait,
+//                with the extra 4 bits of address LSB being 0x2 to keep the
+//                W25X10CL in continuous read mode forever
+//              * Enable SSI
+//              * Set VTOR = 0x10000100
+//              * Read MSP reset vector from 0x10000100 and write to MSP (this
+//                will also enable XIP mode in the SSI wrapper)
+//              * Read PC reset vector from 0x10000104 and jump to it
+//
+// Building:    * This code must be linked to run at 0x20000000
+//              * The code will be padded to a size of 256 bytes, including a
+//                4-byte checksum. Therefore code size cannot exceed 252 bytes.
+// ----------------------------------------------------------------------------
+
+#include "shared/asm_helper.S"
+#include "shared/regs.h"
+
+// The serial flash interface will run at clk_sys/PICO_FLASH_SPI_CLKDIV.
+// This must be an even number.
+#ifndef PICO_FLASH_SPI_CLKDIV
+#define PICO_FLASH_SPI_CLKDIV 4
+#endif
+
+pico_default_asm_setup
+
+// ----------------------------------------------------------------------------
+// The "System Control Block" is a set of internal Cortex-M0+ control registers
+// that are memory mapped and accessed like any other H/W register.  They have
+// fixed addresses in the address map of every Cortex-M0+ system.
+// ----------------------------------------------------------------------------
+
+.equ SCB_VTOR,          0xE000ED08      // RW Vector Table Offset Register
+
+// ----------------------------------------------------------------------------
+// Winbond W25X10CL Supported Commands
+// Taken from "w25x10cl_reg_021714.pdf"
+// ----------------------------------------------------------------------------
+
+.equ W25X10CL_CMD_READ_DATA_FAST_DUAL_IO, 0xbb
+
+// ----------------------------------------------------------------------------
+// Winbond W25X10CL "Mode bits" are 8 special bits sent immediately after
+// the address bits in a "Read Data Fast Dual I/O" command sequence.
+// Of M[7:4], they say M[7:6] are reserved (set to zero), and bits M[3:0]
+// are don't care (we HiZ).  Only M[5:4] are used, and they must be set
+// to M[5:4] = 2'b10 to enable continuous read mode.
+// ----------------------------------------------------------------------------
+
+.equ W25X10CL_MODE_CONTINUOUS_READ,        0x20
+
+// ----------------------------------------------------------------------------
+// Start of 2nd Stage Boot Code
+// ----------------------------------------------------------------------------
+
+.org 0
+
+.section .text
+
+// This code will get copied to 0x20000000 and then executed
+
+regular_func _stage2_boot
+    push {lr}
+    ldr r3, =XIP_SSI_BASE                // Use as base address where possible
+
+// We are primarily interested in setting up Flash for DSPI XIP w/ continuous read
+
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET] // Disable SSI to allow further config
+
+// The Boot ROM sets a very conservative SPI clock frequency to be sure it can
+// read the initial 256 bytes from any device.  Here we can be more aggressive.
+
+    movs r1, #PICO_FLASH_SPI_CLKDIV
+    str r1, [r3, #SSI_BAUDR_OFFSET]  // Set SSI Clock
+
+// First we need to send the initial command to get us in to Fast Read Dual I/O
+// mode.  As this transaction requires a command, we can't send it in XIP mode.
+// To enter Continuous Read mode as well we need to append 4'b0010 to the address
+// bits and then add a further 4 don't care bits.  We will construct this by
+// specifying a 28-bit address, with the least significant bits being 4'b0010.
+// This is just a dummy transaction so we'll perform a read from address zero
+// and then discard what comes back.  All we really care about is that at the
+// end of the transaction, the Winbond W25X10CL device is in Continuous Read mode
+// and from then on will only expect to receive addresses.
+
+#define CTRLR0_ENTER_XIP \
+    (SSI_CTRLR0_SPI_FRF_VALUE_DUAL         /* Dual I/O mode */                \
+        << SSI_CTRLR0_SPI_FRF_LSB) |                                          \
+    (31 << SSI_CTRLR0_DFS_32_LSB)  |       /* 32 data bits */    \
+    (SSI_CTRLR0_TMOD_VALUE_EEPROM_READ     /* Send INST/ADDR, Receive Data */ \
+        << SSI_CTRLR0_TMOD_LSB)
+
+    ldr r1, =(CTRLR0_ENTER_XIP)
+    str r1, [r3, #SSI_CTRLR0_OFFSET]
+
+    movs r1, #0x0                   // NDF=0 (single 32b read)
+    str r1, [r3, #SSI_CTRLR1_OFFSET]
+
+#define SPI_CTRLR0_ENTER_XIP \
+    (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) |         /* Send 28 bits (24 address + 4 mode) */ \
+    (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |    /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_8B \
+        << SSI_SPI_CTRLR0_INST_L_LSB) |        /* 8-bit instruction */ \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_1C2A      /* Send Command in serial mode then address in Dual I/O mode */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_ENTER_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)  // SPI_CTRL0 Register
+    str r1, [r0]
+
+    movs r1, #1                     // Re-enable SSI
+    str r1, [r3, #SSI_SSIENR_OFFSET]
+
+    movs r1, #W25X10CL_CMD_READ_DATA_FAST_DUAL_IO   // 8b command = 0xBB
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push SPI command into TX FIFO
+    movs r1, #0x0000002             // 28-bit Address for dummy read = 0x000000 + 0x2 Mode bits to set M[5:4]=10
+    str r1, [r3, #SSI_DR0_OFFSET]   // Push Address into TX FIFO - this will trigger the transaction
+
+// Now we wait for the read transaction to complete by monitoring the SSI
+// status register and checking for the "RX FIFO Not Empty" flag to assert.
+
+    movs r1, #SSI_SR_RFNE_BITS
+00:
+    ldr r0, [r3, #SSI_SR_OFFSET]    // Read status register
+    tst r0, r1                      // RFNE status flag set?
+    beq 00b                         // If not then wait
+
+// At this point CN# will be deasserted and the SPI clock will not be running.
+// The Winbond WX25X10CL device will be in continuous read, dual I/O mode and
+// only expecting address bits after the next CN# assertion.  So long as we
+// send 4'b0010 (and 4 more dummy HiZ bits) after every subsequent 24b address
+// then the Winbond device will remain in continuous read mode.  This is the
+// ideal mode for Execute-In-Place.
+// (If we want to exit continuous read mode then we will need to switch back
+// to APM mode and generate a 28-bit address phase with the extra nibble set
+// to 4'b0000).
+
+    movs r1, #0
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Disable SSI (and clear FIFO) to allow further config
+
+// Note that the INST_L field is used to select what XIP data gets pushed into
+// the TX FIFO:
+//      INST_L_0_BITS   {ADDR[23:0],XIP_CMD[7:0]}       Load "mode bits" into XIP_CMD
+//      Anything else   {XIP_CMD[7:0],ADDR[23:0]}       Load SPI command into XIP_CMD
+
+#define SPI_CTRLR0_XIP \
+    (W25X10CL_MODE_CONTINUOUS_READ              /* Mode bits to keep Winbond in continuous read mode */ \
+        << SSI_SPI_CTRLR0_XIP_CMD_LSB) | \
+    (7 << SSI_SPI_CTRLR0_ADDR_L_LSB) |         /* Send 28 bits (24 address + 4 mode) */ \
+    (2 << SSI_SPI_CTRLR0_WAIT_CYCLES_LSB) |    /* Hi-Z the other 4 mode bits (2 cycles @ dual I/O = 4 bits) */ \
+    (SSI_SPI_CTRLR0_INST_L_VALUE_NONE          /* Do not send a command, instead send XIP_CMD as mode bits after address */ \
+        << SSI_SPI_CTRLR0_INST_L_LSB) | \
+    (SSI_SPI_CTRLR0_TRANS_TYPE_VALUE_2C2A      /* Send Address in Dual I/O mode (and Command but that is zero bits long) */ \
+        << SSI_SPI_CTRLR0_TRANS_TYPE_LSB)
+
+    ldr r1, =(SPI_CTRLR0_XIP)
+    ldr r0, =(XIP_SSI_BASE + SSI_SPI_CTRLR0_OFFSET)
+    str r1, [r0]
+
+    movs r1, #1
+    str r1, [r3, #SSI_SSIENR_OFFSET]   // Re-enable SSI
+
+// We are now in XIP mode, with all transactions using Dual I/O and only
+// needing to send 24-bit addresses (plus mode bits) for each read transaction.
+
+// Pull in standard exit routine
+#include "shared/exit_from_boot2.S"
+
+.global literals
+literals:
+.ltorg
+
+.end

From 193ce99c1888cc9c373aac1aa4f7c307d643bd1d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Tue, 19 Sep 2023 10:05:33 +0200
Subject: [PATCH 196/286] Bootstrap code

---
 .gitattributes              |  1 +
 .github/workflows/build.yml | 26 ++++++++++++++++++++++++++
 .gitignore                  |  3 +++
 build.zig                   | 19 +++++++++++++++++++
 build.zig.zon               | 14 ++++++++++++++
 ezpkg.sh                    |  5 +++++
 shell.nix                   |  8 ++++++++
 src/blinky.zig              | 20 ++++++++++++++++++++
 8 files changed, 96 insertions(+)
 create mode 100644 .gitattributes
 create mode 100644 .github/workflows/build.yml
 create mode 100644 .gitignore
 create mode 100644 build.zig
 create mode 100644 build.zig.zon
 create mode 100755 ezpkg.sh
 create mode 100644 shell.nix
 create mode 100644 src/blinky.zig

diff --git a/.gitattributes b/.gitattributes
new file mode 100644
index 000000000..0cb064aeb
--- /dev/null
+++ b/.gitattributes
@@ -0,0 +1 @@
+*.zig text=auto eol=lf
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
new file mode 100644
index 000000000..59cf509b7
--- /dev/null
+++ b/.github/workflows/build.yml
@@ -0,0 +1,26 @@
+name: Build
+on:
+  push:
+    branches: [main]
+  pull_request:
+    branches: [main]
+  schedule:
+    - cron: '0 0 * * *'
+
+jobs:
+  build:
+    runs-on: ${{ matrix.os }}
+    strategy:
+      matrix:
+        os: [windows-latest, macos-latest, linux-latest]
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v2
+
+      - name: Setup Zig
+        uses: goto-bus-stop/setup-zig@v2
+        with:
+          version: 0.11.0
+
+      - name: Build examples
+        run: zig build
diff --git a/.gitignore b/.gitignore
new file mode 100644
index 000000000..eacd52b70
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,3 @@
+zig-cache/
+dev-scripts/
+zig-out
diff --git a/build.zig b/build.zig
new file mode 100644
index 000000000..cac966e9c
--- /dev/null
+++ b/build.zig
@@ -0,0 +1,19 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const rp2040 = @import("rp2040");
+
+pub fn build(b: *std.Build) void {
+    const optimize = b.standardOptimizeOption(.{});
+
+    const firmware = microzig.addFirmware(b, .{
+        .name = "blinky",
+        .target = rp2040.chips.rp2040,
+        .optimize = optimize,
+        .source_file = .{ .path = "src/blinky.zig" },
+    });
+
+    microzig.installFirmware(firmware, .{
+        
+        .format = .uf2, // .dfu, .bin, .hex, .elf, …
+    });
+}
diff --git a/build.zig.zon b/build.zig.zon
new file mode 100644
index 000000000..d66119385
--- /dev/null
+++ b/build.zig.zon
@@ -0,0 +1,14 @@
+.{
+    .name = "microzig-examples",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/f0a6aa9ce1829df91f2d7f160bbc6f5bc41a3c80.tar.gz",
+            .hash = "12203f8cb7803a82dff1310ab0917055c0055bc7385f1321bbaf0de998b26a00b44d",
+        },
+        .rp2040 = .{
+            .url = "https://github.com/ZigEmbeddedGroup/raspberrypi-rp2040/archive/2a0c0ff2814a716a163822211c2686d84801a97a.tar.gz",
+            .hash = "12208735720ddf172a28943f1b17375f7b16370140be9c458f1482076025e465c3b0",
+        },
+    },
+}
diff --git a/ezpkg.sh b/ezpkg.sh
new file mode 100755
index 000000000..b1f61da0b
--- /dev/null
+++ b/ezpkg.sh
@@ -0,0 +1,5 @@
+#!/bin/sh
+
+exec ezpkg \
+    microzig=/home/felix/projects/zeg/microzig \
+    rp2040=/home/felix/projects/zeg/device-support-package/rp2040
\ No newline at end of file
diff --git a/shell.nix b/shell.nix
new file mode 100644
index 000000000..3c88ea05c
--- /dev/null
+++ b/shell.nix
@@ -0,0 +1,8 @@
+{pkgs ? import  {}}:
+pkgs.mkShell {
+  nativeBuildInputs = [
+    pkgs.zig_0_11_0
+    pkgs.picotool
+  ];
+  buildInputs = [];
+}
diff --git a/src/blinky.zig b/src/blinky.zig
new file mode 100644
index 000000000..5632fe349
--- /dev/null
+++ b/src/blinky.zig
@@ -0,0 +1,20 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const rp2040 = microzig.hal;
+const time = rp2040.time;
+
+const pin_config = rp2040.pins.GlobalConfiguration{
+    .GPIO25 = .{
+        .name = "led",
+        .direction = .out,
+    },
+};
+
+pub fn main() !void {
+    const pins = pin_config.apply();
+
+    while (true) {
+        pins.led.toggle();
+        time.sleep_ms(250);
+    }
+}

From e14f0a1e53002556e62928fc3848882cdaa7597a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Tue, 19 Sep 2023 10:10:15 +0200
Subject: [PATCH 197/286] Adds some documentation comments

---
 build.zig | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/build.zig b/build.zig
index cac966e9c..c351ebc29 100644
--- a/build.zig
+++ b/build.zig
@@ -5,15 +5,30 @@ const rp2040 = @import("rp2040");
 pub fn build(b: *std.Build) void {
     const optimize = b.standardOptimizeOption(.{});
 
+    // `addFirmware` basically works like addExecutable, but takes a
+    // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+    //
+    // The target will convey all necessary information on the chip,
+    // cpu and potentially the board as well.
     const firmware = microzig.addFirmware(b, .{
         .name = "blinky",
-        .target = rp2040.chips.rp2040,
+        .target = rp2040.boards.raspberrypi.pico,
         .optimize = optimize,
         .source_file = .{ .path = "src/blinky.zig" },
     });
 
+    // Pendant to `getEmittedBin()`: Always returns the path to the output elf file
+    _ = firmware.getEmittedElf();
+
+    // Extension of `getEmittedElf()` that will also convert the file to the given
+    // binary format.
+    _ = firmware.getEmittedBin(.uf2);
+
+    // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+    // and allows installing the firmware as a typical firmware file.
+    //
+    // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
     microzig.installFirmware(firmware, .{
-        
         .format = .uf2, // .dfu, .bin, .hex, .elf, …
     });
 }

From 8a124a68dbf0e6f6f0a576c16ca410788fe78d07 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Wed, 20 Sep 2023 00:42:15 +0200
Subject: [PATCH 198/286] First build again. No verification of 'works'

---
 .gitignore    |  1 +
 build.zig     | 12 ++++++------
 build.zig.zon |  8 ++++----
 3 files changed, 11 insertions(+), 10 deletions(-)

diff --git a/.gitignore b/.gitignore
index eacd52b70..f975728be 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,3 +1,4 @@
 zig-cache/
 dev-scripts/
 zig-out
+.envrc
diff --git a/build.zig b/build.zig
index c351ebc29..d9612882a 100644
--- a/build.zig
+++ b/build.zig
@@ -1,8 +1,10 @@
 const std = @import("std");
-const microzig = @import("microzig");
 const rp2040 = @import("rp2040");
+const microzig_build = @import("microzig");
 
 pub fn build(b: *std.Build) void {
+    const microzig = microzig_build.init(b, "microzig");
+
     const optimize = b.standardOptimizeOption(.{});
 
     // `addFirmware` basically works like addExecutable, but takes a
@@ -12,7 +14,7 @@ pub fn build(b: *std.Build) void {
     // cpu and potentially the board as well.
     const firmware = microzig.addFirmware(b, .{
         .name = "blinky",
-        .target = rp2040.boards.raspberrypi.pico,
+        .target = rp2040.boards.raspberry_pi.pico,
         .optimize = optimize,
         .source_file = .{ .path = "src/blinky.zig" },
     });
@@ -22,13 +24,11 @@ pub fn build(b: *std.Build) void {
 
     // Extension of `getEmittedElf()` that will also convert the file to the given
     // binary format.
-    _ = firmware.getEmittedBin(.uf2);
+    _ = firmware.getEmittedBin(null); // `null` is preferred format, in this case uf2
 
     // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
     // and allows installing the firmware as a typical firmware file.
     //
     // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
-    microzig.installFirmware(firmware, .{
-        .format = .uf2, // .dfu, .bin, .hex, .elf, …
-    });
+    microzig.installFirmware(b, firmware, .{});
 }
diff --git a/build.zig.zon b/build.zig.zon
index d66119385..c1350ee81 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -3,12 +3,12 @@
     .version = "0.1.0",
     .dependencies = .{
         .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/f0a6aa9ce1829df91f2d7f160bbc6f5bc41a3c80.tar.gz",
-            .hash = "12203f8cb7803a82dff1310ab0917055c0055bc7385f1321bbaf0de998b26a00b44d",
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/44ab82cac86ab7fbd4e6718021d51a2bb8c4a42c.tar.gz",
+            .hash = "122039437ab5c8946e3f1f77dec17092f0c6cae9fcd830bce89f03725e75a02d101b",
         },
         .rp2040 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/raspberrypi-rp2040/archive/2a0c0ff2814a716a163822211c2686d84801a97a.tar.gz",
-            .hash = "12208735720ddf172a28943f1b17375f7b16370140be9c458f1482076025e465c3b0",
+            .url = "https://github.com/ZigEmbeddedGroup/raspberrypi-rp2040/archive/b9c361be68215d48657ec3684c8a30ebbc74efd5.tar.gz",
+            .hash = "1220aa6da071763468a358e82af753db23513e12120cf749bdb8bb4f8ea2a8b6da7b",
         },
     },
 }

From 2b25d1fe1c56c60205283642c4fc5986ceb87357 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Wed, 20 Sep 2023 14:26:52 +0200
Subject: [PATCH 199/286] Adds building support for STM32

---
 README.md     |  1 +
 build.zig     | 66 ++++++++++++++++++++++++++++++++-------------------
 build.zig.zon | 12 ++++++----
 ezpkg.sh      |  6 ++++-
 src/empty.zig |  6 +++++
 5 files changed, 62 insertions(+), 29 deletions(-)
 create mode 100644 src/empty.zig

diff --git a/README.md b/README.md
index c3bfa2788..dda56835b 100644
--- a/README.md
+++ b/README.md
@@ -1,2 +1,3 @@
 # microzig-examples
+
 Examples for embedded zig!
diff --git a/build.zig b/build.zig
index d9612882a..9ed2c21b2 100644
--- a/build.zig
+++ b/build.zig
@@ -1,34 +1,52 @@
 const std = @import("std");
 const rp2040 = @import("rp2040");
-const microzig_build = @import("microzig");
+const stm32 = @import("stm32");
 
 pub fn build(b: *std.Build) void {
-    const microzig = microzig_build.init(b, "microzig");
-
+    const microzig = @import("microzig").init(b, "microzig");
     const optimize = b.standardOptimizeOption(.{});
 
-    // `addFirmware` basically works like addExecutable, but takes a
-    // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
-    //
-    // The target will convey all necessary information on the chip,
-    // cpu and potentially the board as well.
-    const firmware = microzig.addFirmware(b, .{
-        .name = "blinky",
-        .target = rp2040.boards.raspberry_pi.pico,
-        .optimize = optimize,
-        .source_file = .{ .path = "src/blinky.zig" },
-    });
+    const TargetDesc = struct {
+        target: @import("microzig").Target,
+        name: []const u8,
+    };
+
+    const available_targets = [_]TargetDesc{
+        // RP2040
+        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
+        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
+        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
+        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
 
-    // Pendant to `getEmittedBin()`: Always returns the path to the output elf file
-    _ = firmware.getEmittedElf();
+        // STM32
+        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
+        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
+        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
+        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
+        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
+        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
+        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
+        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
+    };
 
-    // Extension of `getEmittedElf()` that will also convert the file to the given
-    // binary format.
-    _ = firmware.getEmittedBin(null); // `null` is preferred format, in this case uf2
+    for (available_targets) |dest| {
+        // `addFirmware` basically works like addExecutable, but takes a
+        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+        //
+        // The target will convey all necessary information on the chip,
+        // cpu and potentially the board as well.
+        const firmware = microzig.addFirmware(b, .{
+            .name = b.fmt("empty-{s}", .{dest.name}),
+            .target = dest.target,
+            .optimize = optimize,
+            .source_file = .{ .path = "src/empty.zig" },
+        });
 
-    // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
-    // and allows installing the firmware as a typical firmware file.
-    //
-    // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
-    microzig.installFirmware(b, firmware, .{});
+        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+        // and allows installing the firmware as a typical firmware file.
+        //
+        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+        microzig.installFirmware(b, firmware, .{});
+    }
 }
diff --git a/build.zig.zon b/build.zig.zon
index c1350ee81..e44e0ba4e 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -3,12 +3,16 @@
     .version = "0.1.0",
     .dependencies = .{
         .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/44ab82cac86ab7fbd4e6718021d51a2bb8c4a42c.tar.gz",
-            .hash = "122039437ab5c8946e3f1f77dec17092f0c6cae9fcd830bce89f03725e75a02d101b",
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
+            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
         },
         .rp2040 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/raspberrypi-rp2040/archive/b9c361be68215d48657ec3684c8a30ebbc74efd5.tar.gz",
-            .hash = "1220aa6da071763468a358e82af753db23513e12120cf749bdb8bb4f8ea2a8b6da7b",
+            .url = "https://github.com/ZigEmbeddedGroup/raspberrypi-rp2040/archive/67d36eebb0fbd89633db1a51d6d2bcb049f2066a.tar.gz",
+            .hash = "122094bf268f45b188f3916f9e5964f4257414afaafba98a455ac47d25389a456832",
+        },
+        .stm32 = .{
+            .url = "https://github.com/ZigEmbeddedGroup/stmicro-stm32/archive/cb2893707efa6aa289fa72f02959ad5f2d9db2a1.tar.gz",
+            .hash = "12208cab5f60ef97cac4165ad694f3ba0c7b28f279538c1539b74f7c152f34fe306d",
         },
     },
 }
diff --git a/ezpkg.sh b/ezpkg.sh
index b1f61da0b..577c8b42e 100755
--- a/ezpkg.sh
+++ b/ezpkg.sh
@@ -2,4 +2,8 @@
 
 exec ezpkg \
     microzig=/home/felix/projects/zeg/microzig \
-    rp2040=/home/felix/projects/zeg/device-support-package/rp2040
\ No newline at end of file
+    microzig.uf2=/home/felix/projects/zeg/uf2 \
+    microzig.regz=/home/felix/projects/zeg/regz \
+    rp2040=/home/felix/projects/zeg/device-support-package/rp2040 \
+    stm32=/home/felix/projects/zeg/device-support-package/stmicro-stm32
+    
\ No newline at end of file
diff --git a/src/empty.zig b/src/empty.zig
new file mode 100644
index 000000000..7c6dbbe42
--- /dev/null
+++ b/src/empty.zig
@@ -0,0 +1,6 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+pub fn main() void {
+    //
+}

From 9e40dda94b40b9e00803d66e1f1f20b3454bb96c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Wed, 20 Sep 2023 17:50:55 +0200
Subject: [PATCH 200/286] Fixes CI runner

---
 .github/workflows/build.yml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 59cf509b7..193502363 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -12,7 +12,7 @@ jobs:
     runs-on: ${{ matrix.os }}
     strategy:
       matrix:
-        os: [windows-latest, macos-latest, linux-latest]
+        os: [windows-latest, macos-latest, ubuntu-latest]
     steps:
       - name: Checkout
         uses: actions/checkout@v2

From 991d757eff2aa6a36bfef74e239cdc1bdf84043f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 21 Sep 2023 10:19:02 +0200
Subject: [PATCH 201/286] Adds more working devices.

---
 .github/workflows/build.yml |  2 --
 build.zig                   | 25 +++++++++++++++++++++++++
 build.zig.zon               | 20 ++++++++++++++++++++
 ezpkg.sh                    |  8 ++++++--
 4 files changed, 51 insertions(+), 4 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 193502363..af725e66c 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -4,8 +4,6 @@ on:
     branches: [main]
   pull_request:
     branches: [main]
-  schedule:
-    - cron: '0 0 * * *'
 
 jobs:
   build:
diff --git a/build.zig b/build.zig
index 9ed2c21b2..3aeb29301 100644
--- a/build.zig
+++ b/build.zig
@@ -1,6 +1,9 @@
 const std = @import("std");
 const rp2040 = @import("rp2040");
 const stm32 = @import("stm32");
+const lpc = @import("lpc");
+const gd32 = @import("gd32");
+const nrf5x = @import("nrf5x");
 
 pub fn build(b: *std.Build) void {
     const microzig = @import("microzig").init(b, "microzig");
@@ -28,6 +31,28 @@ pub fn build(b: *std.Build) void {
         .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
         .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
         .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
+
+        // NXP LPC
+        // TODO: Add checksum postprocessing
+        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
+        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+
+        // GigaDevice GD32
+        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
+        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
+        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
+
+        // Nordic Nrf5x
+        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
+        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
+        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
+
+        // Espressif ESP
+        // .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
+        // TODO: Add support for Espressif Update Binaries
+
+        // Microchip ATmega
+        // TODO: Fix compiler bugs
     };
 
     for (available_targets) |dest| {
diff --git a/build.zig.zon b/build.zig.zon
index e44e0ba4e..1180edb52 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -14,5 +14,25 @@
             .url = "https://github.com/ZigEmbeddedGroup/stmicro-stm32/archive/cb2893707efa6aa289fa72f02959ad5f2d9db2a1.tar.gz",
             .hash = "12208cab5f60ef97cac4165ad694f3ba0c7b28f279538c1539b74f7c152f34fe306d",
         },
+        .lpc = .{
+            .url = "https://github.com/ZigEmbeddedGroup/nxp-lpc/archive/be4280a8b55690e8446fd4c3186dcd6673118cd3.tar.gz",
+            .hash = "1220891bc5fa43b30cd024a628f8915f54691e5664d2a34e6653bf92722b222b7c7e",
+        },
+        .gd32 = .{
+            .url = "https://github.com/ZigEmbeddedGroup/gigadevice-gd32/archive/9324753cc3b8e7afe83fcda085bcfe76681a3be3.tar.gz",
+            .hash = "122043ff4dcbc342f25dbb936b0d9eaa701ac3509e2cbe6764be37b90d31c7a385d0",
+        },
+        .nrf5x = .{
+            .url = "https://github.com/ZigEmbeddedGroup/nordic-nrf5x/archive/0ab136860ccf7eb1d07969c3ef523f3cd898e2ff.tar.gz",
+            .hash = "1220980da06f9634dcff06afefa7aa111bd030018fea49f79e86657dab69621e1d08",
+        },
+        .esp = .{
+            .url = "https://github.com/ZigEmbeddedGroup/espressif-esp/archive/f7e47d07996565036501f55ed781a5f6e786b2f7.tar.gz",
+            .hash = "12209b0365f56df4ce83b1300da86bef605bd299e94b87f373571351f71fa2ccd461",
+        },
+        .atmega = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microchip-atmega/archive/46dfd08ad13e0a9a84351cfd595b1e6e341d4839.tar.gz",
+            .hash = "1220b2df269bf997b77bebcebea63a8e39aea354a7075cf99878423e304394bc28eb",
+        },
     },
 }
diff --git a/ezpkg.sh b/ezpkg.sh
index 577c8b42e..caafa0365 100755
--- a/ezpkg.sh
+++ b/ezpkg.sh
@@ -5,5 +5,9 @@ exec ezpkg \
     microzig.uf2=/home/felix/projects/zeg/uf2 \
     microzig.regz=/home/felix/projects/zeg/regz \
     rp2040=/home/felix/projects/zeg/device-support-package/rp2040 \
-    stm32=/home/felix/projects/zeg/device-support-package/stmicro-stm32
-    
\ No newline at end of file
+    stm32=/home/felix/projects/zeg/device-support-package/stmicro-stm32 \
+    lpc=/home/felix/projects/zeg/device-support-package/nxp-lpc \
+    gd32=/home/felix/projects/zeg/device-support-package/gigadevice-gd32 \
+    esp=/home/felix/projects/zeg/device-support-package/espressif-esp \
+    nrf5x=/home/felix/projects/zeg/device-support-package/nordic-nrf5x \
+    atmega=/home/felix/projects/zeg/device-support-package/microchip-atmega 
\ No newline at end of file

From ca17420a81df7bec9382459970652e7dc79cfe26 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 21 Sep 2023 12:16:03 +0200
Subject: [PATCH 202/286] Adds more architectures

---
 build.zig     | 15 +++++++++++----
 build.zig.zon | 12 ++++++------
 shell.nix     |  1 +
 3 files changed, 18 insertions(+), 10 deletions(-)

diff --git a/build.zig b/build.zig
index 3aeb29301..406477261 100644
--- a/build.zig
+++ b/build.zig
@@ -4,6 +4,8 @@ const stm32 = @import("stm32");
 const lpc = @import("lpc");
 const gd32 = @import("gd32");
 const nrf5x = @import("nrf5x");
+const esp = @import("esp");
+const atmega = @import("atmega");
 
 pub fn build(b: *std.Build) void {
     const microzig = @import("microzig").init(b, "microzig");
@@ -33,7 +35,6 @@ pub fn build(b: *std.Build) void {
         .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
 
         // NXP LPC
-        // TODO: Add checksum postprocessing
         .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
         .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
 
@@ -47,12 +48,15 @@ pub fn build(b: *std.Build) void {
         .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
         .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
 
-        // Espressif ESP
-        // .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
-        // TODO: Add support for Espressif Update Binaries
+        // RISC-V Espressif ESP
+        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
 
         // Microchip ATmega
         // TODO: Fix compiler bugs
+        // - https://github.com/ziglang/zig/issues/17219
+        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
+        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
+        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
     };
 
     for (available_targets) |dest| {
@@ -73,5 +77,8 @@ pub fn build(b: *std.Build) void {
         //
         // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
         microzig.installFirmware(b, firmware, .{});
+
+        // For debugging, we also always install the firmware as an ELF file
+        microzig.installFirmware(b, firmware, .{ .format = .elf });
     }
 }
diff --git a/build.zig.zon b/build.zig.zon
index 1180edb52..716625979 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -15,8 +15,8 @@
             .hash = "12208cab5f60ef97cac4165ad694f3ba0c7b28f279538c1539b74f7c152f34fe306d",
         },
         .lpc = .{
-            .url = "https://github.com/ZigEmbeddedGroup/nxp-lpc/archive/be4280a8b55690e8446fd4c3186dcd6673118cd3.tar.gz",
-            .hash = "1220891bc5fa43b30cd024a628f8915f54691e5664d2a34e6653bf92722b222b7c7e",
+            .url = "https://github.com/ZigEmbeddedGroup/nxp-lpc/archive/130a1316c0892415e7da958a5e9548ed87bba54d.tar.gz",
+            .hash = "1220165879f85a1d51656d35b3963a95f3585dc665fc7414f76aa6aad4e6635536cf",
         },
         .gd32 = .{
             .url = "https://github.com/ZigEmbeddedGroup/gigadevice-gd32/archive/9324753cc3b8e7afe83fcda085bcfe76681a3be3.tar.gz",
@@ -27,12 +27,12 @@
             .hash = "1220980da06f9634dcff06afefa7aa111bd030018fea49f79e86657dab69621e1d08",
         },
         .esp = .{
-            .url = "https://github.com/ZigEmbeddedGroup/espressif-esp/archive/f7e47d07996565036501f55ed781a5f6e786b2f7.tar.gz",
-            .hash = "12209b0365f56df4ce83b1300da86bef605bd299e94b87f373571351f71fa2ccd461",
+            .url = "https://github.com/ZigEmbeddedGroup/espressif-esp/archive/59b8ca028915c0d6224ec88dbf4db19afbb559c0.tar.gz",
+            .hash = "1220f6e5f22416fdc63442cd8869fcaa35f9abf30d878ea3d80073176677dc6f8a65",
         },
         .atmega = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microchip-atmega/archive/46dfd08ad13e0a9a84351cfd595b1e6e341d4839.tar.gz",
-            .hash = "1220b2df269bf997b77bebcebea63a8e39aea354a7075cf99878423e304394bc28eb",
+            .url = "https://github.com/ZigEmbeddedGroup/microchip-atmega/archive/feefcb87a63c0aae31afb783d4e388e90c4d922f.tar.gz",
+            .hash = "1220048dc5d22729ee119a496f8b8ca3556838af1f3bd32ce6acd5f76480ec942965",
         },
     },
 }
diff --git a/shell.nix b/shell.nix
index 3c88ea05c..b1724c483 100644
--- a/shell.nix
+++ b/shell.nix
@@ -3,6 +3,7 @@ pkgs.mkShell {
   nativeBuildInputs = [
     pkgs.zig_0_11_0
     pkgs.picotool
+    pkgs.llvmPackages_16.bintools
   ];
   buildInputs = [];
 }

From 3bdb7381be3f066aa2ea0ed1c2c7ea796141ac55 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Fri, 22 Sep 2023 09:01:19 +0200
Subject: [PATCH 203/286] Microzig Generation 2 Build Interface  (#144)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* Starts to rework build framework.
* Fully reworks build API, builds with RP2040 again.
* Adds docs and doc generation.
* Renames source to register_definitions, makes Target.configure optional.
* Adds issue tracking links.
* Drops CI for now

---------

Co-authored-by: Felix "xq" Queißner 
---
 .buildkite/pipeline.yml             |    7 -
 .github/workflows/build.yml         |   24 -
 build.zig                           | 1063 ++++++++++++++++++++++-----
 build.zig.zon                       |   14 +
 src/{modules => }/cpus/avr5.zig     |    0
 src/{modules => }/cpus/cortex-m.zig |    0
 src/{modules => }/cpus/riscv32.zig  |    0
 src/modules/Board.zig               |    6 -
 src/modules/Chip.zig                |   44 --
 src/modules/Cpu.zig                 |    5 -
 src/modules/LinkerScriptStep.zig    |  172 -----
 src/modules/MemoryRegion.zig        |   18 -
 src/modules/cpus.zig                |   84 ---
 13 files changed, 911 insertions(+), 526 deletions(-)
 delete mode 100644 .buildkite/pipeline.yml
 delete mode 100644 .github/workflows/build.yml
 create mode 100644 build.zig.zon
 rename src/{modules => }/cpus/avr5.zig (100%)
 rename src/{modules => }/cpus/cortex-m.zig (100%)
 rename src/{modules => }/cpus/riscv32.zig (100%)
 delete mode 100644 src/modules/Board.zig
 delete mode 100644 src/modules/Chip.zig
 delete mode 100644 src/modules/Cpu.zig
 delete mode 100644 src/modules/LinkerScriptStep.zig
 delete mode 100644 src/modules/MemoryRegion.zig
 delete mode 100644 src/modules/cpus.zig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
deleted file mode 100644
index 723f5a248..000000000
--- a/.buildkite/pipeline.yml
+++ /dev/null
@@ -1,7 +0,0 @@
-steps:
-  - group: Build and Test
-    steps:
-    - label: Debug
-      command: zig build test
-    - label: ReleaseSmall
-      command: zig build test -Doptimize=ReleaseSmall
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
deleted file mode 100644
index e387a3874..000000000
--- a/.github/workflows/build.yml
+++ /dev/null
@@ -1,24 +0,0 @@
-name: Build
-on:
-  push:
-
-jobs:
-  build:
-    runs-on: ${{ matrix.os }}
-    strategy:
-      matrix:
-        os: [
-          ubuntu-latest,
-          windows-latest,
-          macos-latest,
-        ]
-    steps:
-    - uses: actions/checkout@v2
-
-    - name: Setup Zig
-      uses: goto-bus-stop/setup-zig@v1.3.0
-      with:
-        version: 0.11.0
-
-    - name: Build tests
-      run: zig build test -Doptimize=ReleaseSmall
diff --git a/build.zig b/build.zig
index f66b2b527..9b92d6b89 100644
--- a/build.zig
+++ b/build.zig
@@ -3,97 +3,419 @@
 //! This means we need to use addExecutable() instead of using
 
 const std = @import("std");
-const LibExeObjStep = std.Build.LibExeObjStep;
-const Module = std.Build.Module;
-const LazyPath = std.Build.LazyPath;
-const OptionsStep = std.Build.OptionsStep;
-const Build = std.Build;
-
-// alias for packages
-pub const LinkerScriptStep = @import("src/modules/LinkerScriptStep.zig");
-pub const cpus = @import("src/modules/cpus.zig");
-pub const Board = @import("src/modules/Board.zig");
-pub const Chip = @import("src/modules/Chip.zig");
-pub const Cpu = @import("src/modules/Cpu.zig");
-pub const MemoryRegion = @import("src/modules/MemoryRegion.zig");
-
-pub const Backing = union(enum) {
-    board: Board,
-    chip: Chip,
+const uf2 = @import("uf2");
+
+////////////////////////////////////////
+//      MicroZig Gen 2 Interface      //
+////////////////////////////////////////
+
+fn root() []const u8 {
+    return comptime (std.fs.path.dirname(@src().file) orelse ".");
+}
+const build_root = root();
+
+const MicroZig = @This();
+
+b: *std.Build,
+self: *std.Build.Dependency,
+
+/// Creates a new instance of the MicroZig build support.
+///
+/// This is necessary as we need to keep track of some internal state to prevent
+/// duplicated work per firmware built.
+pub fn init(b: *std.Build, dependency_name: []const u8) *MicroZig {
+    const mz = b.allocator.create(MicroZig) catch @panic("out of memory");
+    mz.* = MicroZig{
+        .b = b,
+        .self = b.dependency(dependency_name, .{}),
+    };
+    return mz;
+}
+
+/// This build script validates usage patterns we expect from MicroZig
+pub fn build(b: *std.Build) !void {
+    const uf2_dep = b.dependency("uf2", .{});
 
-    pub fn get_target(self: @This()) std.zig.CrossTarget {
-        return switch (self) {
-            .board => |brd| brd.chip.cpu.target,
-            .chip => |chip| chip.cpu.target,
+    const build_test = b.addTest(.{
+        .root_source_file = .{ .path = "build.zig" },
+    });
+
+    build_test.addAnonymousModule("uf2", .{
+        .source_file = .{ .cwd_relative = uf2_dep.builder.pathFromRoot("build.zig") },
+    });
+
+    const install_docs = b.addInstallDirectory(.{
+        .source_dir = build_test.getEmittedDocs(),
+        .install_dir = .prefix,
+        .install_subdir = "docs",
+    });
+
+    b.getInstallStep().dependOn(&install_docs.step);
+
+    // const backings = @import("test/backings.zig");
+    // const optimize = b.standardOptimizeOption(.{});
+
+    // const minimal = addEmbeddedExecutable(b, .{
+    //     .name = "minimal",
+    //     .source_file = .{
+    //         .path = comptime root_dir() ++ "/test/programs/minimal.zig",
+    //     },
+    //     .backing = backings.minimal,
+    //     .optimize = optimize,
+    // });
+
+    // const has_hal = addEmbeddedExecutable(b, .{
+    //     .name = "has_hal",
+    //     .source_file = .{
+    //         .path = comptime root_dir() ++ "/test/programs/has_hal.zig",
+    //     },
+    //     .backing = backings.has_hal,
+    //     .optimize = optimize,
+    // });
+
+    // const has_board = addEmbeddedExecutable(b, .{
+    //     .name = "has_board",
+    //     .source_file = .{
+    //         .path = comptime root_dir() ++ "/test/programs/has_board.zig",
+    //     },
+    //     .backing = backings.has_board,
+    //     .optimize = optimize,
+    // });
+
+    // const core_tests = b.addTest(.{
+    //     .root_source_file = .{
+    //         .path = comptime root_dir() ++ "/src/core.zig",
+    //     },
+    //     .optimize = optimize,
+    // });
+
+    // const test_step = b.step("test", "build test programs");
+    // test_step.dependOn(&minimal.inner.step);
+    // test_step.dependOn(&has_hal.inner.step);
+    // test_step.dependOn(&has_board.inner.step);
+    // test_step.dependOn(&b.addRunArtifact(core_tests).step);
+}
+
+/// The resulting binary format for the firmware file.
+/// A lot of embedded systems don't use plain ELF files, thus we provide means
+/// to convert the resulting ELF into other common formats.
+pub const BinaryFormat = union(enum) {
+    /// [Executable and Linkable Format](https://en.wikipedia.org/wiki/Executable_and_Linkable_Format), the standard output from the compiler.
+    elf,
+
+    /// A flat binary, contains only the loaded portions of the firmware with an unspecified base offset.
+    bin,
+
+    /// The [Intel HEX](https://en.wikipedia.org/wiki/Intel_HEX) format, contains
+    /// an ASCII description of what memory to load where.
+    hex,
+
+    /// A [Device Firmware Upgrade](https://www.usb.org/sites/default/files/DFU_1.1.pdf) file.
+    dfu,
+
+    /// The [USB Flashing Format (UF2)](https://github.com/microsoft/uf2) designed by Microsoft.
+    uf2: uf2.FamilyId,
+
+    /// The [firmware format](https://docs.espressif.com/projects/esptool/en/latest/esp32/advanced-topics/firmware-image-format.html) used by the [esptool](https://github.com/espressif/esptool) bootloader.
+    esp,
+
+    /// Custom option for non-standard formats.
+    custom: *Custom,
+
+    /// Returns the standard extension for the resulting binary file.
+    pub fn getExtension(format: BinaryFormat) []const u8 {
+        return switch (format) {
+            .elf => ".elf",
+            .bin => ".bin",
+            .hex => ".hex",
+            .dfu => ".dfu",
+            .uf2 => ".uf2",
+            .esp => ".bin",
+
+            .custom => |c| c.extension,
         };
     }
-};
 
-pub const EmbeddedExecutable = struct {
-    inner: *LibExeObjStep,
+    pub const Custom = struct {
+        /// The standard extension of the format.
+        extension: []const u8,
 
-    pub const AppDependencyOptions = struct {
-        depend_on_microzig: bool = false,
+        /// A function that will convert a given `elf` file into the custom output format.
+        ///
+        /// The `*Custom` format is passed so contextual information can be obtained by using
+        /// `@fieldParentPtr` to provide access to tooling.
+        convert: *const fn (*Custom, elf: std.Build.LazyPath) std.Build.LazyPath,
     };
 
-    pub fn addAppDependency(exe: *EmbeddedExecutable, name: []const u8, module: *Module, options: AppDependencyOptions) void {
-        if (options.depend_on_microzig) {
-            const microzig_module = exe.inner.modules.get("microzig").?;
-            module.dependencies.put("microzig", microzig_module) catch @panic("OOM");
+    const Enum = std.meta.Tag(BinaryFormat);
+
+    const Context = struct {
+        pub fn hash(self: @This(), fmt: BinaryFormat) u32 {
+            _ = self;
+
+            var hasher = std.hash.XxHash32.init(0x1337_42_21);
+
+            hasher.update(@tagName(fmt));
+
+            switch (fmt) {
+                .elf, .bin, .hex, .dfu, .esp => |val| {
+                    if (@TypeOf(val) != void) @compileError("Missing update: Context.hash now requires special care!");
+                },
+
+                .uf2 => |family_id| hasher.update(@tagName(family_id)),
+                .custom => |custom| hasher.update(std.mem.asBytes(custom)),
+            }
+
+            return hasher.final();
         }
 
-        const app_module = exe.inner.modules.get("app").?;
-        app_module.dependencies.put(name, module) catch @panic("OOM");
-    }
+        pub fn eql(self: @This(), fmt_a: BinaryFormat, fmt_b: BinaryFormat, index: usize) bool {
+            _ = self;
+            _ = index;
+            if (@as(BinaryFormat.Enum, fmt_a) != @as(BinaryFormat.Enum, fmt_b))
+                return false;
 
-    pub fn installArtifact(exe: *EmbeddedExecutable, b: *Build) void {
-        b.installArtifact(exe.inner);
-    }
+            return switch (fmt_a) {
+                .elf, .bin, .hex, .dfu, .esp => |val| {
+                    if (@TypeOf(val) != void) @compileError("Missing update: Context.eql now requires special care!");
+                    return true;
+                },
 
-    pub fn addIncludePath(exe: *EmbeddedExecutable, path: LazyPath) void {
-        exe.inner.addIncludePath(path);
-    }
+                .uf2 => |a| (a == fmt_b.uf2),
+                .custom => |a| (a == fmt_b.custom),
+            };
+        }
+    };
+};
 
-    pub fn addSystemIncludePath(exe: *EmbeddedExecutable, path: LazyPath) void {
-        return exe.inner.addSystemIncludePath(path);
+/// The CPU model a target uses.
+///
+/// The CPUs usually require special care on how to do interrupts, and getting an entry point.
+///
+/// MicroZig officially only supports the CPUs listed here, but other CPUs might be provided
+/// via the `custom` field.
+pub const CpuModel = union(enum) {
+    avr5,
+    cortex_m0,
+    cortex_m0plus,
+    cortex_m3,
+    cortex_m4,
+    riscv32_imac,
+
+    custom: *const Cpu,
+
+    pub fn getDescriptor(model: CpuModel) *const Cpu {
+        return switch (@as(std.meta.Tag(CpuModel), model)) {
+            inline else => |tag| &@field(cpus, @tagName(tag)),
+            .custom => model.custom,
+        };
     }
+};
 
-    pub fn addCSourceFile(exe: *EmbeddedExecutable, source: Build.Step.Compile.CSourceFile) void {
-        exe.inner.addCSourceFile(source);
-    }
+/// A cpu descriptor.
+pub const Cpu = struct {
+    /// Display name of the CPU.
+    name: []const u8,
 
-    pub fn addOptions(exe: *EmbeddedExecutable, module_name: []const u8, options: *OptionsStep) void {
-        exe.inner.addOptions(module_name, options);
-        const app_module = exe.inner.modules.get("app").?;
-        const opt_module = exe.inner.modules.get(module_name).?;
-        app_module.dependencies.put(module_name, opt_module) catch @panic("OOM");
-    }
+    /// Source file providing startup code and memory initialization routines.
+    source_file: std.build.LazyPath,
 
-    pub fn addObjectFile(exe: *EmbeddedExecutable, source: LazyPath) void {
-        exe.inner.addObjectFile(source);
-    }
+    /// The compiler target we use to compile all the code.
+    target: std.zig.CrossTarget,
 };
 
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
+/// A descriptor for memory regions in a microcontroller.
+pub const MemoryRegion = struct {
+    /// The type of the memory region for generating a proper linker script.
+    kind: Kind,
+    offset: u64,
+    length: u64,
+
+    pub const Kind = union(enum) {
+        /// This is a (normally) immutable memory region where the code is stored.
+        flash,
+
+        /// This is a mutable memory region for data storage.
+        ram,
+
+        /// This is a memory region that maps MMIO devices.
+        io,
+
+        /// This is a memory region that exists, but is reserved and must not be used.
+        reserved,
+
+        /// This is a memory region used for internal linking tasks required by the board support package.
+        private: PrivateRegion,
+    };
+
+    pub const PrivateRegion = struct {
+        /// The name of the memory region. Will not have an automatic numeric counter and must be unique.
+        name: []const u8,
+
+        /// Is the memory region executable?
+        executable: bool,
+
+        /// Is the memory region readable?
+        readable: bool,
 
-pub const EmbeddedExecutableOptions = struct {
+        /// Is the memory region writable?
+        writeable: bool,
+    };
+};
+
+/// Defines a custom microcontroller.
+pub const Chip = struct {
+    /// The display name of the controller.
     name: []const u8,
-    source_file: LazyPath,
-    backing: Backing,
-    optimize: std.builtin.OptimizeMode = .Debug,
-    linkerscript_source_file: ?LazyPath = null,
+
+    /// (optional) link to the documentation/vendor page of the controller.
+    url: ?[]const u8 = null,
+
+    /// The cpu model this controller uses.
+    cpu: CpuModel,
+
+    /// The provider for register definitions.
+    register_definition: union(enum) {
+        /// Use `regz` to create a zig file from a JSON schema.
+        json: std.Build.LazyPath,
+
+        /// Use `regz` to create a json file from a SVD schema.
+        svd: std.Build.LazyPath,
+
+        /// Use `regz` to create a zig file from an ATDF schema.
+        atdf: std.Build.LazyPath,
+
+        /// Use the provided file directly as the chip file.
+        zig: std.Build.LazyPath,
+    },
+
+    /// The memory regions that are present in this chip.
+    memory_regions: []const MemoryRegion,
 };
 
-pub fn addEmbeddedExecutable(b: *Build, opts: EmbeddedExecutableOptions) *EmbeddedExecutable {
-    const has_board = (opts.backing == .board);
-    const chip = switch (opts.backing) {
-        .chip => |chip| chip,
-        .board => |board| board.chip,
-    };
+/// Defines a hardware abstraction layer.
+pub const HardwareAbstractionLayer = struct {
+    /// Root source file for this HAL.
+    source_file: std.Build.LazyPath,
+};
+
+/// Provides a description of a board.
+///
+/// Boards provide additional information to a chip and HAL package.
+/// For example, they can list attached peripherials, external crystal frequencies,
+/// flash sizes, ...
+pub const BoardDefinition = struct {
+    /// Display name of the board
+    name: []const u8,
+
+    /// (optional) link to the documentation/vendor page of the board.
+    url: ?[]const u8 = null,
+
+    /// Provides the root file for the board definition.
+    source_file: std.Build.LazyPath,
+};
+
+/// The linker script used to link the firmware.
+pub const LinkerScript = union(enum) {
+    /// Auto-generated linker script derived from the memory regions of the chip.
+    generated,
+
+    /// Externally defined linker script.
+    source_file: std.build.LazyPath,
+};
+
+/// A compilation target for MicroZig. Provides information about the chip,
+/// hal, board and so on.
+///
+/// This is used instead of `std.zig.CrossTarget` to define a MicroZig Firmware.
+pub const Target = struct {
+    /// The preferred binary format of this MicroZig target. If `null`, the user must
+    /// explicitly give the `.format` field during a call to `getEmittedBin()` or installation steps.
+    preferred_format: ?BinaryFormat,
+
+    /// The chip this target uses,
+    chip: Chip,
+
+    /// Usually, embedded projects are single-threaded and single-core applications. Platforms that
+    /// support multiple CPUs should set this to `false`.
+    single_threaded: bool = true,
+
+    /// Determines whether the compiler_rt package is bundled with the application or not.
+    /// This should always be true except for platforms where compiler_rt cannot be built right now.
+    bundle_compiler_rt: bool = true,
+
+    /// (optional) Provides a default hardware abstraction layer that is used.
+    /// If `null`, no `microzig.hal` will be available.
+    hal: ?HardwareAbstractionLayer = null,
+
+    /// (optional) Provides description of external hardware and connected devices
+    /// like oscillators and such.
+    ///
+    /// This structure isn't used by MicroZig itself, but can be utilized from the HAL
+    /// if present.
+    board: ?BoardDefinition = null,
+
+    /// (optional) Provide a custom linker script for the hardware or define a custom generation.
+    linker_script: LinkerScript = .generated,
+
+    /// (optional) Further configures the created firmware depending on the chip and/or board settings.
+    /// This can be used to set/change additional properties on the created `*Firmware` object.
+    configure: ?*const fn (host_build: *std.Build, *Firmware) void = null,
 
-    const has_hal = chip.hal != null;
+    /// (optional) Post processing step that will patch up and modify the elf file if necessary.
+    binary_post_process: ?*const fn (host_build: *std.Build, std.Build.LazyPath) std.Build.LazyPath = null,
+};
+
+/// Options to the `addFirmware` function.
+pub const FirmwareOptions = struct {
+    /// The name of the firmware file.
+    name: []const u8,
+
+    /// The MicroZig target that the firmware is built for. Either a board or a chip.
+    target: Target,
+
+    /// The optimization level that should be used. Usually `ReleaseSmall` or `Debug` is a good choice.
+    /// Also using `std.Build.standardOptimizeOption` is a good idea.
+    optimize: std.builtin.OptimizeMode,
+
+    /// The root source file for the application. This is your `src/main.zig` file.
+    source_file: std.Build.LazyPath,
+
+    // Overrides:
+
+    /// If set, overrides the `single_threaded` property of the target.
+    single_threaded: ?bool = null,
+
+    /// If set, overrides the `bundle_compiler_rt` property of the target.
+    bundle_compiler_rt: ?bool = null,
+
+    /// If set, overrides the `hal` property of the target.
+    hal: ?HardwareAbstractionLayer = null,
+
+    /// If set, overrides the `board` property of the target.
+    board: ?BoardDefinition = null,
+
+    /// If set, overrides the `linker_script` property of the target.
+    linker_script: ?LinkerScript = null,
+};
+
+/// Declares a new MicroZig firmware file.
+pub fn addFirmware(
+    /// The MicroZig instance that should be used to create the firmware.
+    mz: *MicroZig,
+    /// The instance of the `build.zig` that is calling this function.
+    host_build: *std.Build,
+    /// Options that define how the firmware is built.
+    options: FirmwareOptions,
+) *Firmware {
+    const micro_build = mz.self.builder;
+
+    const chip = &options.target.chip;
+    const cpu = chip.cpu.getDescriptor();
+    const maybe_hal = options.hal orelse options.target.hal;
+    const maybe_board = options.board orelse options.target.board;
+
+    const linker_script = options.linker_script orelse options.target.linker_script;
 
     // TODO: let the user override which ram section to use the stack on,
     // for now just using the first ram section in the memory region list
@@ -104,142 +426,551 @@ pub fn addEmbeddedExecutable(b: *Build, opts: EmbeddedExecutableOptions) *Embedd
         } else @panic("no ram memory region found for setting the end-of-stack address");
     };
 
-    const config = b.addOptions();
-    config.addOption(bool, "has_hal", has_hal);
-    config.addOption(bool, "has_board", has_board);
-    if (has_board)
-        config.addOption([]const u8, "board_name", opts.backing.board.name);
+    // On demand, generate chip definitions via regz:
+    const chip_source = switch (chip.register_definition) {
+        .json, .atdf, .svd => |file| blk: {
+            const regz_exe = mz.dependency("regz", .{ .optimize = .ReleaseSafe }).artifact("regz");
+
+            const regz_gen = host_build.addRunArtifact(regz_exe);
+
+            regz_gen.addArg("--schema"); // Explicitly set schema type, one of: svd, atdf, json
+            regz_gen.addArg(@tagName(chip.register_definition));
+
+            regz_gen.addArg("--output_path"); // Write to a file
+            const zig_file = regz_gen.addOutputFileArg("chip.zig");
+
+            regz_gen.addFileArg(file);
+
+            break :blk zig_file;
+        },
+
+        .zig => |src| src,
+    };
+
+    const config = host_build.addOptions();
+    config.addOption(bool, "has_hal", (maybe_hal != null));
+    config.addOption(bool, "has_board", (maybe_board != null));
+
+    config.addOption(?[]const u8, "board_name", if (maybe_board) |brd| brd.name else null);
 
     config.addOption([]const u8, "chip_name", chip.name);
     config.addOption([]const u8, "cpu_name", chip.name);
     config.addOption(usize, "end_of_stack", first_ram.offset + first_ram.length);
 
-    const microzig_module = b.createModule(.{
-        .source_file = .{ .path = comptime std.fmt.comptimePrint("{s}/src/microzig.zig", .{root_dir()}) },
-    });
+    const fw: *Firmware = host_build.allocator.create(Firmware) catch @panic("out of memory");
+    fw.* = Firmware{
+        .mz = mz,
+        .host_build = host_build,
+        .artifact = host_build.addExecutable(.{
+            .name = options.name,
+            .optimize = options.optimize,
+            .target = cpu.target,
+            .linkage = .static,
+            .root_source_file = .{ .cwd_relative = mz.self.builder.pathFromRoot("src/start.zig") },
+        }),
+        .target = options.target,
+        .output_files = Firmware.OutputFileMap.init(host_build.allocator),
+
+        .config = config,
 
-    microzig_module.dependencies.put("config", b.createModule(.{
-        .source_file = config.getSource(),
-    })) catch unreachable;
+        .modules = .{
+            .microzig = micro_build.createModule(.{
+                .source_file = .{ .cwd_relative = micro_build.pathFromRoot("src/microzig.zig") },
+                .dependencies = &.{
+                    .{
+                        .name = "config",
+                        .module = micro_build.createModule(.{ .source_file = config.getSource() }),
+                    },
+                },
+            }),
+
+            .cpu = undefined,
+            .chip = undefined,
+
+            .board = null,
+            .hal = null,
 
-    microzig_module.dependencies.put("chip", b.createModule(.{
-        .source_file = chip.source,
+            .app = undefined,
+        },
+    };
+    errdefer fw.output_files.deinit();
+
+    fw.modules.chip = micro_build.createModule(.{
+        .source_file = chip_source,
         .dependencies = &.{
-            .{ .name = "microzig", .module = microzig_module },
+            .{ .name = "microzig", .module = fw.modules.microzig },
         },
-    })) catch unreachable;
+    });
+    fw.modules.microzig.dependencies.put("chip", fw.modules.chip) catch @panic("out of memory");
 
-    microzig_module.dependencies.put("cpu", b.createModule(.{
-        .source_file = chip.cpu.source,
+    fw.modules.cpu = micro_build.createModule(.{
+        .source_file = cpu.source_file,
         .dependencies = &.{
-            .{ .name = "microzig", .module = microzig_module },
+            .{ .name = "microzig", .module = fw.modules.microzig },
         },
-    })) catch unreachable;
+    });
+    fw.modules.microzig.dependencies.put("cpu", fw.modules.cpu) catch @panic("out of memory");
 
-    if (chip.hal) |hal_module_source| {
-        microzig_module.dependencies.put("hal", b.createModule(.{
-            .source_file = hal_module_source,
+    if (maybe_hal) |hal| {
+        fw.modules.hal = micro_build.createModule(.{
+            .source_file = hal.source_file,
             .dependencies = &.{
-                .{ .name = "microzig", .module = microzig_module },
+                .{ .name = "microzig", .module = fw.modules.microzig },
             },
-        })) catch unreachable;
+        });
+        fw.modules.microzig.dependencies.put("hal", fw.modules.hal.?) catch @panic("out of memory");
     }
 
-    switch (opts.backing) {
-        .board => |board| {
-            microzig_module.dependencies.put("board", b.createModule(.{
-                .source_file = board.source,
-                .dependencies = &.{
-                    .{ .name = "microzig", .module = microzig_module },
-                },
-            })) catch unreachable;
-        },
-        else => {},
+    if (maybe_board) |brd| {
+        fw.modules.board = micro_build.createModule(.{
+            .source_file = brd.source_file,
+            .dependencies = &.{
+                .{ .name = "microzig", .module = fw.modules.microzig },
+            },
+        });
+        fw.modules.microzig.dependencies.put("board", fw.modules.board.?) catch @panic("out of memory");
     }
 
-    const app_module = b.createModule(.{
-        .source_file = opts.source_file,
+    fw.modules.app = host_build.createModule(.{
+        .source_file = options.source_file,
         .dependencies = &.{
-            .{ .name = "microzig", .module = microzig_module },
+            .{ .name = "microzig", .module = fw.modules.microzig },
         },
     });
 
-    const exe = b.allocator.create(EmbeddedExecutable) catch unreachable;
-    exe.* = EmbeddedExecutable{
-        .inner = b.addExecutable(.{
-            .name = opts.name,
-            .root_source_file = .{ .path = comptime std.fmt.comptimePrint("{s}/src/start.zig", .{root_dir()}) },
-            .target = chip.cpu.target,
-            .optimize = opts.optimize,
-        }),
-    };
-    exe.inner.addModule("app", app_module);
-    exe.inner.addModule("microzig", microzig_module);
+    fw.artifact.addModule("app", fw.modules.app);
+    fw.artifact.addModule("microzig", fw.modules.microzig);
 
-    exe.inner.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded
+    fw.artifact.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded
+    fw.artifact.single_threaded = options.single_threaded orelse fw.target.single_threaded;
+    fw.artifact.bundle_compiler_rt = options.bundle_compiler_rt orelse fw.target.bundle_compiler_rt;
 
-    // might not be true for all machines (Pi Pico), but
-    // for the HAL it's true (it doesn't know the concept of threading)
-    exe.inner.single_threaded = true;
+    switch (linker_script) {
+        .generated => {
+            fw.artifact.setLinkerScript(
+                generateLinkerScript(host_build, chip.*) catch @panic("out of memory"),
+            );
+        },
 
-    if (opts.linkerscript_source_file) |linkerscript_source_file| {
-        exe.inner.setLinkerScriptPath(linkerscript_source_file);
-    } else {
-        const linkerscript = LinkerScriptStep.create(b, chip) catch unreachable;
-        exe.inner.setLinkerScriptPath(.{ .generated = &linkerscript.generated_file });
+        .source_file => |source| {
+            fw.artifact.setLinkerScriptPath(source);
+        },
     }
 
-    // TODO:
-    // - Generate the linker scripts from the "chip" or "board" module instead of using hardcoded ones.
-    //   - This requires building another tool that runs on the host that compiles those files and emits the linker script.
-    //    - src/tools/linkerscript-gen.zig is the source file for this
-    exe.inner.bundle_compiler_rt = (exe.inner.target.getCpuArch() != .avr); // don't bundle compiler_rt for AVR as it doesn't compile right now
+    if (options.target.configure) |configure| {
+        configure(host_build, fw);
+    }
 
-    return exe;
+    return fw;
 }
 
-/// This build script validates usage patterns we expect from MicroZig
-pub fn build(b: *Build) !void {
-    const backings = @import("test/backings.zig");
-    const optimize = b.standardOptimizeOption(.{});
-
-    const minimal = addEmbeddedExecutable(b, .{
-        .name = "minimal",
-        .source_file = .{
-            .path = comptime root_dir() ++ "/test/programs/minimal.zig",
-        },
-        .backing = backings.minimal,
-        .optimize = optimize,
+/// Configuration options for firmware installation.
+pub const InstallFirmwareOptions = struct {
+    /// Overrides the output format for the binary. If not set, the standard preferred file format for the firmware target is used.
+    format: ?BinaryFormat = null,
+};
+
+/// Adds a new dependency to the `install` step that will install the `firmware` into the folder `$prefix/firmware`.
+pub fn installFirmware(
+    /// The MicroZig instance that was used to create the firmware.
+    mz: *MicroZig,
+    /// The instance of the `build.zig` that should perform installation.
+    b: *std.Build,
+    /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
+    firmware: *Firmware,
+    /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
+    options: InstallFirmwareOptions,
+) void {
+    std.debug.assert(mz == firmware.mz);
+    const install_step = addInstallFirmware(mz, b, firmware, options);
+    b.getInstallStep().dependOn(&install_step.step);
+}
+
+/// Creates a new `std.Build.Step.InstallFile` instance that will install the given firmware to `$prefix/firmware`.
+///
+/// **NOTE:** This does not actually install the firmware yet. You have to add the returned step as a dependency to another step.
+///           If you want to just install the firmware, use `installFirmware` instead!
+pub fn addInstallFirmware(
+    /// The MicroZig instance that was used to create the firmware.
+    mz: *MicroZig,
+    /// The instance of the `build.zig` that should perform installation.
+    b: *std.Build,
+    /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
+    firmware: *Firmware,
+    /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
+    options: InstallFirmwareOptions,
+) *std.Build.Step.InstallFile {
+    const format = firmware.resolveFormat(options.format);
+
+    const basename = b.fmt("{s}{s}", .{
+        firmware.artifact.name,
+        format.getExtension(),
     });
 
-    const has_hal = addEmbeddedExecutable(b, .{
-        .name = "has_hal",
-        .source_file = .{
-            .path = comptime root_dir() ++ "/test/programs/has_hal.zig",
+    _ = mz;
+
+    return b.addInstallFileWithDir(firmware.getEmittedBin(format), .{ .custom = "firmware" }, basename);
+}
+
+/// Declaration of a firmware build.
+pub const Firmware = struct {
+    const OutputFileMap = std.ArrayHashMap(BinaryFormat, std.Build.LazyPath, BinaryFormat.Context, false);
+
+    const Modules = struct {
+        app: *std.Build.Module,
+        cpu: *std.Build.Module,
+        chip: *std.Build.Module,
+        board: ?*std.Build.Module,
+        hal: ?*std.Build.Module,
+        microzig: *std.Build.Module,
+    };
+
+    // privates:
+    mz: *MicroZig,
+    host_build: *std.Build,
+    target: Target,
+    output_files: OutputFileMap,
+
+    // publics:
+
+    /// The artifact that is built by Zig.
+    artifact: *std.Build.Step.Compile,
+
+    /// The options step that provides `microzig.config`. If you need custom configuration, you can add this here.
+    config: *std.Build.Step.Options,
+
+    /// Declaration of the MicroZig modules used by this firmware.
+    modules: Modules,
+
+    /// Path to the emitted elf file, if any.
+    emitted_elf: ?std.Build.LazyPath = null,
+
+    /// Returns the emitted ELF file for this firmware. This is useful if you need debug information
+    /// or want to use a debugger like Segger, ST-Link or similar.
+    ///
+    /// **NOTE:** This is similar, but not equivalent to `std.Build.Step.Compile.getEmittedBin`. The call on the compile step does
+    ///           not include post processing of the ELF files necessary by certain targets.
+    pub fn getEmittedElf(firmware: *Firmware) std.Build.LazyPath {
+        if (firmware.emitted_elf == null) {
+            const raw_elf = firmware.artifact.getEmittedBin();
+            firmware.emitted_elf = if (firmware.target.binary_post_process) |binary_post_process|
+                binary_post_process(firmware.host_build, raw_elf)
+            else
+                raw_elf;
+        }
+        return firmware.emitted_elf.?;
+    }
+
+    /// Returns the emitted binary for this firmware. The file is either in the preferred file format for
+    /// the target or in `format` if not null.
+    ///
+    /// **NOTE:** The file returned here is the same file that will be installed.
+    pub fn getEmittedBin(firmware: *Firmware, format: ?BinaryFormat) std.Build.LazyPath {
+        const actual_format = firmware.resolveFormat(format);
+
+        const gop = firmware.output_files.getOrPut(actual_format) catch @panic("out of memory");
+        if (!gop.found_existing) {
+            const elf_file = firmware.getEmittedElf();
+
+            const basename = firmware.host_build.fmt("{s}{s}", .{
+                firmware.artifact.name,
+                actual_format.getExtension(),
+            });
+
+            gop.value_ptr.* = switch (actual_format) {
+                .elf => elf_file,
+
+                .bin => blk: {
+                    const objcopy = firmware.host_build.addObjCopy(elf_file, .{
+                        .basename = basename,
+                        .format = .bin,
+                    });
+
+                    break :blk objcopy.getOutput();
+                },
+
+                .hex => blk: {
+                    const objcopy = firmware.host_build.addObjCopy(elf_file, .{
+                        .basename = basename,
+                        .format = .hex,
+                    });
+
+                    break :blk objcopy.getOutput();
+                },
+
+                .uf2 => |family_id| blk: {
+                    const uf2_exe = firmware.mz.dependency("uf2", .{ .optimize = .ReleaseSafe }).artifact("elf2uf2");
+
+                    const convert = firmware.host_build.addRunArtifact(uf2_exe);
+
+                    convert.addArg("--family-id");
+                    convert.addArg(firmware.host_build.fmt("0x{X:0>4}", .{@intFromEnum(family_id)}));
+
+                    convert.addArg("--elf-path");
+                    convert.addFileArg(elf_file);
+
+                    convert.addArg("--output-path");
+                    break :blk convert.addOutputFileArg(basename);
+                },
+
+                .dfu => buildConfigError(firmware.host_build, "DFU is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/145 for more details!", .{}),
+                .esp => buildConfigError(firmware.host_build, "ESP firmware image is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/146 for more details!", .{}),
+
+                .custom => |generator| generator.convert(generator, elf_file),
+            };
+        }
+        return gop.value_ptr.*;
+    }
+
+    pub const AppDependencyOptions = struct {
+        depend_on_microzig: bool = false,
+    };
+
+    /// Adds a regular dependency to your application.
+    pub fn addAppDependency(fw: *Firmware, name: []const u8, module: *std.Build.Module, options: AppDependencyOptions) void {
+        if (options.depend_on_microzig) {
+            module.dependencies.put("microzig", fw.modules.microzig) catch @panic("OOM");
+        }
+        fw.modules.app.dependencies.put(name, module) catch @panic("OOM");
+    }
+
+    pub fn addIncludePath(fw: *Firmware, path: std.Build.LazyPath) void {
+        fw.artifact.addIncludePath(path);
+    }
+
+    pub fn addSystemIncludePath(fw: *Firmware, path: std.Build.LazyPath) void {
+        fw.artifact.addSystemIncludePath(path);
+    }
+
+    pub fn addCSourceFile(fw: *Firmware, source: std.Build.Step.Compile.CSourceFile) void {
+        fw.artifact.addCSourceFile(source);
+    }
+
+    pub fn addOptions(fw: *Firmware, module_name: []const u8, options: *std.Build.OptionsStep) void {
+        fw.artifact.addOptions(module_name, options);
+        fw.modules.app.dependencies.put(
+            module_name,
+            fw.host_build.createModule(.{
+                .source_file = options.getOutput(),
+            }),
+        ) catch @panic("OOM");
+    }
+
+    pub fn addObjectFile(fw: *Firmware, source: std.Build.LazyPath) void {
+        fw.artifact.addObjectFile(source);
+    }
+
+    fn resolveFormat(firmware: *Firmware, format: ?BinaryFormat) BinaryFormat {
+        if (format) |fmt| return fmt;
+
+        if (firmware.target.preferred_format) |fmt| return fmt;
+
+        buildConfigError(firmware.host_build, "{s} has no preferred output format, please provide one in the `format` option.", .{
+            firmware.target.chip.name,
+        });
+    }
+};
+
+pub const cpus = struct {
+    pub const avr5 = Cpu{
+        .name = "AVR5",
+        .source_file = .{ .path = build_root ++ "/src/cpus/avr5.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .avr,
+            .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 },
+            .os_tag = .freestanding,
+            .abi = .eabi,
         },
-        .backing = backings.has_hal,
-        .optimize = optimize,
-    });
+    };
 
-    const has_board = addEmbeddedExecutable(b, .{
-        .name = "has_board",
-        .source_file = .{
-            .path = comptime root_dir() ++ "/test/programs/has_board.zig",
+    pub const cortex_m0 = Cpu{
+        .name = "ARM Cortex-M0",
+        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 },
+            .os_tag = .freestanding,
+            .abi = .none,
         },
-        .backing = backings.has_board,
-        .optimize = optimize,
-    });
+    };
+
+    pub const cortex_m0plus = Cpu{
+        .name = "ARM Cortex-M0+",
+        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus },
+            .os_tag = .freestanding,
+            .abi = .none,
+        },
+    };
+
+    pub const cortex_m3 = Cpu{
+        .name = "ARM Cortex-M3",
+        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 },
+            .os_tag = .freestanding,
+            .abi = .none,
+        },
+    };
+
+    pub const cortex_m4 = Cpu{
+        .name = "ARM Cortex-M4",
+        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 },
+            .os_tag = .freestanding,
+            .abi = .none,
+        },
+    };
 
-    const core_tests = b.addTest(.{
-        .root_source_file = .{
-            .path = comptime root_dir() ++ "/src/core.zig",
+    pub const riscv32_imac = Cpu{
+        .name = "RISC-V 32-bit",
+        .source_file = .{ .path = build_root ++ "/src/cpus/riscv32.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .riscv32,
+            .cpu_model = .{ .explicit = &std.Target.riscv.cpu.sifive_e21 },
+            .os_tag = .freestanding,
+            .abi = .none,
         },
-        .optimize = optimize,
+    };
+};
+
+fn buildConfigError(b: *std.Build, comptime fmt: []const u8, args: anytype) noreturn {
+    const msg = b.fmt(fmt, args);
+    @panic(msg);
+}
+
+fn dependency(mz: *MicroZig, name: []const u8, args: anytype) *std.Build.Dependency {
+    return mz.self.builder.dependency(name, args);
+}
+
+fn generateLinkerScript(b: *std.Build, chip: Chip) !std.Build.LazyPath {
+    const cpu = chip.cpu.getDescriptor();
+
+    var contents = std.ArrayList(u8).init(b.allocator);
+    const writer = contents.writer();
+    try writer.print(
+        \\/*
+        \\ * This file was auto-generated by microzig
+        \\ *
+        \\ * Target CPU:  {[cpu]s}
+        \\ * Target Chip: {[chip]s}
+        \\ */
+        \\
+        // This is not the "true" entry point, but there's no such thing on embedded platforms
+        // anyways. This is the logical entrypoint that should be invoked when
+        // stack, .data and .bss are set up and the CPU is ready to be used.
+        \\ENTRY(microzig_main);
+        \\
+        \\
+    , .{
+        .cpu = cpu.name,
+        .chip = chip.name,
     });
 
-    const test_step = b.step("test", "build test programs");
-    test_step.dependOn(&minimal.inner.step);
-    test_step.dependOn(&has_hal.inner.step);
-    test_step.dependOn(&has_board.inner.step);
-    test_step.dependOn(&b.addRunArtifact(core_tests).step);
+    try writer.writeAll("MEMORY\n{\n");
+    {
+        var counters = [4]usize{ 0, 0, 0, 0 };
+        for (chip.memory_regions) |region| {
+            // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k
+
+            switch (region.kind) {
+                .flash => {
+                    try writer.print("  flash{d}    (rx!w)", .{counters[0]});
+                    counters[0] += 1;
+                },
+
+                .ram => {
+                    try writer.print("  ram{d}      (rw!x)", .{counters[1]});
+                    counters[1] += 1;
+                },
+
+                .io => {
+                    try writer.print("  io{d}       (rw!x)", .{counters[2]});
+                    counters[2] += 1;
+                },
+
+                .reserved => {
+                    try writer.print("  reserved{d} (rw!x)", .{counters[3]});
+                    counters[3] += 1;
+                },
+
+                .private => |custom| {
+                    try writer.print("  {s} (", .{custom.name});
+                    if (custom.readable) try writer.writeAll("r");
+                    if (custom.writeable) try writer.writeAll("w");
+                    if (custom.executable) try writer.writeAll("x");
+
+                    if (!custom.readable or !custom.writeable or !custom.executable) {
+                        try writer.writeAll("!");
+                        if (!custom.readable) try writer.writeAll("r");
+                        if (!custom.writeable) try writer.writeAll("w");
+                        if (!custom.executable) try writer.writeAll("x");
+                    }
+                    try writer.writeAll(")");
+                },
+            }
+            try writer.print(" : ORIGIN = 0x{X:0>8}, LENGTH = 0x{X:0>8}\n", .{ region.offset, region.length });
+        }
+    }
+
+    try writer.writeAll("}\n\nSECTIONS\n{\n");
+    {
+        try writer.writeAll(
+            \\  .text :
+            \\  {
+            \\     KEEP(*(microzig_flash_start))
+            \\     *(.text*)
+            \\  } > flash0
+            \\
+            \\
+        );
+
+        switch (cpu.target.getCpuArch()) {
+            .arm, .thumb => try writer.writeAll(
+                \\  .ARM.exidx : {
+                \\      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+                \\  } >flash0
+                \\
+                \\
+            ),
+            else => {},
+        }
+
+        try writer.writeAll(
+            \\  .data :
+            \\  {
+            \\     microzig_data_start = .;
+            \\     *(.rodata*)
+            \\     *(.data*)
+            \\     microzig_data_end = .;
+            \\  } > ram0 AT> flash0
+            \\
+            \\  .bss (NOLOAD) :
+            \\  {
+            \\      microzig_bss_start = .;
+            \\      *(.bss*)
+            \\      microzig_bss_end = .;
+            \\  } > ram0
+            \\
+            \\  microzig_data_load_start = LOADADDR(.data);
+            \\
+        );
+    }
+    try writer.writeAll("}\n");
+
+    // TODO: Assert that the flash can actually hold all data!
+    // try writer.writeAll(
+    //     \\
+    //     \\  ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" );
+    //     \\
+    // );
+
+    const write = b.addWriteFiles();
+
+    return write.add("linker.ld", contents.items);
 }
diff --git a/build.zig.zon b/build.zig.zon
new file mode 100644
index 000000000..5f0ac76f9
--- /dev/null
+++ b/build.zig.zon
@@ -0,0 +1,14 @@
+.{
+    .name = "microzig",
+    .version = "0.1.0",
+    .dependencies = .{
+        .uf2 = .{
+            .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/c523a4d23469282f95658a879f5ba925757dc9d9.tar.gz",
+            .hash = "12208530bdc194e8c1f3405ad681a409c7fabfe82735cd3972ec07c221a7786db03a",
+        },
+        .regz = .{
+            .url = "https://github.com/ZigEmbeddedGroup/regz/archive/b0ded63fc284da0ed9f4776eb7d1c4ad7175622d.tar.gz",
+            .hash = "1220e9299f949d3566a1dc4dd62caf82a06bb6c8ad5a693e62117b0941da9dc55ea2",
+        },
+    },
+}
diff --git a/src/modules/cpus/avr5.zig b/src/cpus/avr5.zig
similarity index 100%
rename from src/modules/cpus/avr5.zig
rename to src/cpus/avr5.zig
diff --git a/src/modules/cpus/cortex-m.zig b/src/cpus/cortex-m.zig
similarity index 100%
rename from src/modules/cpus/cortex-m.zig
rename to src/cpus/cortex-m.zig
diff --git a/src/modules/cpus/riscv32.zig b/src/cpus/riscv32.zig
similarity index 100%
rename from src/modules/cpus/riscv32.zig
rename to src/cpus/riscv32.zig
diff --git a/src/modules/Board.zig b/src/modules/Board.zig
deleted file mode 100644
index 8e09b4aca..000000000
--- a/src/modules/Board.zig
+++ /dev/null
@@ -1,6 +0,0 @@
-const std = @import("std");
-const Chip = @import("Chip.zig");
-
-name: []const u8,
-source: std.build.LazyPath,
-chip: Chip,
diff --git a/src/modules/Chip.zig b/src/modules/Chip.zig
deleted file mode 100644
index 3676fc9b5..000000000
--- a/src/modules/Chip.zig
+++ /dev/null
@@ -1,44 +0,0 @@
-const std = @import("std");
-const LazyPath = std.build.LazyPath;
-
-const MemoryRegion = @import("MemoryRegion.zig");
-const Cpu = @import("Cpu.zig");
-
-const Chip = @This();
-
-name: []const u8,
-source: LazyPath,
-cpu: Cpu,
-hal: ?LazyPath = null,
-json_register_schema: ?LazyPath = null,
-memory_regions: []const MemoryRegion,
-
-pub fn from_standard_paths(comptime root_dir: []const u8, args: struct {
-    name: []const u8,
-    cpu: Cpu,
-    memory_regions: []const MemoryRegion,
-}) Chip {
-    return Chip{
-        .name = args.name,
-        .cpu = args.cpu,
-        .memory_regions = args.memory_regions,
-        .source = .{
-            .path = std.fmt.comptimePrint("{s}/chips/{s}.zig", .{
-                root_dir,
-                args.name,
-            }),
-        },
-        .hal = .{
-            .path = std.fmt.comptimePrint("{s}/hals/{s}.zig", .{
-                root_dir,
-                args.name,
-            }),
-        },
-        .json_register_schema = .{
-            .path = std.fmt.comptimePrint("{s}/chips/{s}.json", .{
-                root_dir,
-                args.name,
-            }),
-        },
-    };
-}
diff --git a/src/modules/Cpu.zig b/src/modules/Cpu.zig
deleted file mode 100644
index e4cd30773..000000000
--- a/src/modules/Cpu.zig
+++ /dev/null
@@ -1,5 +0,0 @@
-const std = @import("std");
-
-name: []const u8,
-source: std.build.LazyPath,
-target: std.zig.CrossTarget,
diff --git a/src/modules/LinkerScriptStep.zig b/src/modules/LinkerScriptStep.zig
deleted file mode 100644
index fb9227795..000000000
--- a/src/modules/LinkerScriptStep.zig
+++ /dev/null
@@ -1,172 +0,0 @@
-const std = @import("std");
-const MemoryRegion = @import("MemoryRegion.zig");
-const Chip = @import("Chip.zig");
-const Step = std.build.Step;
-const Build = std.Build;
-const GeneratedFile = std.build.GeneratedFile;
-
-const LinkerscriptStep = @This();
-
-step: Step,
-generated_file: std.build.GeneratedFile,
-chip: Chip,
-
-pub fn create(owner: *Build, chip: Chip) !*LinkerscriptStep {
-    var linkerscript = try owner.allocator.create(LinkerscriptStep);
-    linkerscript.* = LinkerscriptStep{
-        .step = Step.init(.{
-            .id = .custom,
-            .name = "linkerscript",
-            .owner = owner,
-            .makeFn = make,
-        }),
-        .generated_file = .{
-            .step = &linkerscript.step,
-        },
-        .chip = chip,
-    };
-
-    return linkerscript;
-}
-
-fn make(step: *Step, _: *std.Progress.Node) anyerror!void {
-    const linkerscript = @fieldParentPtr(LinkerscriptStep, "step", step);
-
-    const owner = linkerscript.step.owner;
-    const target = linkerscript.chip.cpu.target;
-
-    var contents = std.ArrayList(u8).init(owner.allocator);
-    const writer = contents.writer();
-    try writer.print(
-        \\/*
-        \\ * This file was auto-generated by microzig
-        \\ *
-        \\ * Target CPU:  {s}
-        \\ * Target Chip: {s}
-        \\ */
-        \\
-        // This is not the "true" entry point, but there's no such thing on embedded platforms
-        // anyways. This is the logical entrypoint that should be invoked when
-        // stack, .data and .bss are set up and the CPU is ready to be used.
-        \\ENTRY(microzig_main);
-        \\
-        \\
-    , .{ linkerscript.chip.cpu.name, linkerscript.chip.name });
-
-    try writer.writeAll("MEMORY\n{\n");
-    {
-        var counters = [2]usize{ 0, 0 };
-        for (linkerscript.chip.memory_regions) |region| {
-            // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k
-
-            switch (region.kind) {
-                .flash => {
-                    try writer.print("  flash{d} (rx!w)", .{counters[0]});
-                    counters[0] += 1;
-                },
-                .ram => {
-                    try writer.print("  ram{d}   (rw!x)", .{counters[1]});
-                    counters[1] += 1;
-                },
-                .custom => |custom| {
-                    try writer.print("  {s} (", .{custom.name});
-                    if (custom.readable) try writer.writeAll("r");
-                    if (custom.writeable) try writer.writeAll("w");
-                    if (custom.executable) try writer.writeAll("x");
-
-                    if (!custom.readable or !custom.writeable or !custom.executable) {
-                        try writer.writeAll("!");
-                        if (!custom.readable) try writer.writeAll("r");
-                        if (!custom.writeable) try writer.writeAll("w");
-                        if (!custom.executable) try writer.writeAll("x");
-                    }
-                    try writer.writeAll(")");
-                },
-            }
-            try writer.print(" : ORIGIN = 0x{X:0>8}, LENGTH = 0x{X:0>8}\n", .{ region.offset, region.length });
-        }
-    }
-
-    try writer.writeAll("}\n\nSECTIONS\n{\n");
-    {
-        try writer.writeAll(
-            \\  .text :
-            \\  {
-            \\     KEEP(*(microzig_flash_start))
-            \\     *(.text*)
-            \\  } > flash0
-            \\
-            \\
-        );
-
-        switch (target.getCpuArch()) {
-            .arm, .thumb => try writer.writeAll(
-                \\  .ARM.exidx : {
-                \\      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-                \\  } >flash0
-                \\
-                \\
-            ),
-            else => {},
-        }
-
-        try writer.writeAll(
-            \\  .data :
-            \\  {
-            \\     microzig_data_start = .;
-            \\     *(.rodata*)
-            \\     *(.data*)
-            \\     microzig_data_end = .;
-            \\  } > ram0 AT> flash0
-            \\
-            \\  .bss (NOLOAD) :
-            \\  {
-            \\      microzig_bss_start = .;
-            \\      *(.bss*)
-            \\      microzig_bss_end = .;
-            \\  } > ram0
-            \\
-            \\  microzig_data_load_start = LOADADDR(.data);
-            \\
-        );
-    }
-    try writer.writeAll("}\n");
-
-    // TODO: Assert that the flash can actually hold all data!
-    // try writer.writeAll(
-    //     \\
-    //     \\  ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" );
-    //     \\
-    // );
-
-    const filename = try std.fmt.allocPrint(owner.allocator, "{s}_{s}.ld", .{
-        linkerscript.chip.name,
-        linkerscript.chip.cpu.name,
-    });
-
-    var hash = owner.cache.hash;
-    hash.addBytes(linkerscript.chip.name);
-    hash.addBytes(linkerscript.chip.cpu.name);
-
-    // TODO: hash more information to reduce chance of collision
-    for (linkerscript.chip.memory_regions) |memory_region| {
-        hash.add(memory_region.offset);
-        hash.add(memory_region.length);
-    }
-
-    const digest = hash.final();
-    const dir_path = try owner.cache_root.join(owner.allocator, &.{
-        "microzig",
-        &digest,
-    });
-
-    var dir = try owner.cache_root.handle.makeOpenPath(dir_path, .{});
-    defer dir.close();
-
-    const file = try dir.createFile(filename, .{});
-    defer file.close();
-
-    try file.writeAll(contents.items);
-    const full_path = owner.pathJoin(&.{ dir_path, filename });
-    linkerscript.generated_file.path = full_path;
-}
diff --git a/src/modules/MemoryRegion.zig b/src/modules/MemoryRegion.zig
deleted file mode 100644
index 048b2b54a..000000000
--- a/src/modules/MemoryRegion.zig
+++ /dev/null
@@ -1,18 +0,0 @@
-//! This module is meant to be used to define linking apis
-
-kind: Kind,
-offset: u64,
-length: u64,
-
-pub const Kind = union(enum) {
-    flash,
-    ram,
-    custom: RegionSpec,
-};
-
-pub const RegionSpec = struct {
-    name: []const u8,
-    executable: bool,
-    readable: bool,
-    writeable: bool,
-};
diff --git a/src/modules/cpus.zig b/src/modules/cpus.zig
deleted file mode 100644
index a2cf39622..000000000
--- a/src/modules/cpus.zig
+++ /dev/null
@@ -1,84 +0,0 @@
-const std = @import("std");
-const Cpu = @import("Cpu.zig");
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse ".";
-}
-
-pub const avr5 = Cpu{
-    .name = "AVR5",
-    .source = .{
-        .path = std.fmt.comptimePrint("{s}/cpus/avr5.zig", .{root_dir()}),
-    },
-    .target = std.zig.CrossTarget{
-        .cpu_arch = .avr,
-        .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 },
-        .os_tag = .freestanding,
-        .abi = .eabi,
-    },
-};
-
-pub const cortex_m0 = Cpu{
-    .name = "ARM Cortex-M0",
-    .source = .{
-        .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}),
-    },
-    .target = std.zig.CrossTarget{
-        .cpu_arch = .thumb,
-        .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 },
-        .os_tag = .freestanding,
-        .abi = .none,
-    },
-};
-
-pub const cortex_m0plus = Cpu{
-    .name = "ARM Cortex-M0+",
-    .source = .{
-        .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}),
-    },
-    .target = std.zig.CrossTarget{
-        .cpu_arch = .thumb,
-        .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus },
-        .os_tag = .freestanding,
-        .abi = .none,
-    },
-};
-
-pub const cortex_m3 = Cpu{
-    .name = "ARM Cortex-M3",
-    .source = .{
-        .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}),
-    },
-    .target = std.zig.CrossTarget{
-        .cpu_arch = .thumb,
-        .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 },
-        .os_tag = .freestanding,
-        .abi = .none,
-    },
-};
-
-pub const cortex_m4 = Cpu{
-    .name = "ARM Cortex-M4",
-    .source = .{
-        .path = std.fmt.comptimePrint("{s}/cpus/cortex-m.zig", .{root_dir()}),
-    },
-    .target = std.zig.CrossTarget{
-        .cpu_arch = .thumb,
-        .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 },
-        .os_tag = .freestanding,
-        .abi = .none,
-    },
-};
-
-pub const riscv32_imac = Cpu{
-    .name = "RISC-V 32-bit",
-    .source = .{
-        .path = std.fmt.comptimePrint("{s}/cpus/riscv32.zig", .{root_dir()}),
-    },
-    .target = std.zig.CrossTarget{
-        .cpu_arch = .riscv32,
-        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.sifive_e21 },
-        .os_tag = .freestanding,
-        .abi = .none,
-    },
-};

From dbbbb1392f43eea0047aa1a6d91ae2c87d75ec9b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Fri, 22 Sep 2023 09:02:23 +0200
Subject: [PATCH 204/286] Microzig Generation 2 Build Interface  (#23)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* Rework for MicroZig Gen 2 Build
* Drops CI

---------

Co-authored-by: Felix "xq" Queißner 
---
 .github/FUNDING.yml            |     1 -
 .github/workflows/build.yml    |    19 -
 .gitmodules                    |     3 -
 build.zig                      |    74 +-
 build.zig.zon                  |     7 +-
 src/boards/nrf52840-dongle.zig |     1 +
 src/chips.zig                  |    38 -
 src/chips/nrf52.zig            | 16821 ------------------------
 src/chips/nrf52840.zig         | 21782 -------------------------------
 9 files changed, 62 insertions(+), 38684 deletions(-)
 delete mode 100644 .github/FUNDING.yml
 delete mode 100644 .github/workflows/build.yml
 create mode 100644 src/boards/nrf52840-dongle.zig
 delete mode 100644 src/chips.zig
 delete mode 100644 src/chips/nrf52.zig
 delete mode 100644 src/chips/nrf52840.zig

diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml
deleted file mode 100644
index 85b5393bb..000000000
--- a/.github/FUNDING.yml
+++ /dev/null
@@ -1 +0,0 @@
-github: MasterQ32
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
deleted file mode 100644
index 63ea5331c..000000000
--- a/.github/workflows/build.yml
+++ /dev/null
@@ -1,19 +0,0 @@
-name: Build
-on:
-  push:
-
-jobs:
-  build:
-    runs-on: ${{ matrix.os }}
-    strategy:
-      matrix:
-        os: [ubuntu-latest, windows-latest, macos-latest]
-        optimize: [Debug, ReleaseSmall, ReleaseFast, ReleaseSafe]
-    steps:
-      - uses: actions/checkout@v2
-      - uses: goto-bus-stop/setup-zig@v2.1.1
-        with:
-          version: 0.11.0
-
-      - name: Build
-        run: zig build install "-Doptimize=${{matrix.optimize}}"
diff --git a/.gitmodules b/.gitmodules
index 32e895ccb..e69de29bb 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +0,0 @@
-[submodule "deps/microzig"]
-	path = deps/microzig
-	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/build.zig b/build.zig
index 1e421fd6d..1690e0c7d 100644
--- a/build.zig
+++ b/build.zig
@@ -1,19 +1,65 @@
 const std = @import("std");
-const microzig = @import("microzig");
 
-pub const chips = @import("src/chips.zig");
+fn path(comptime suffix: []const u8) std.Build.LazyPath {
+    return .{
+        .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
+    };
+}
 
-pub fn build(b: *std.build.Builder) void {
-    const optimize = b.standardOptimizeOption(.{});
-    inline for (@typeInfo(chips).Struct.decls) |decl| {
-        const exe = microzig.addEmbeddedExecutable(b, .{
-            .name = decl.name ++ ".minimal",
-            .source_file = .{
-                .path = "test/programs/minimal.zig",
+pub const chips = struct {
+    pub const nrf52840 = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "nrf52840",
+            .url = "https://www.nordicsemi.com/products/nrf52840",
+            .cpu = .cortex_m4,
+            .register_definition = .{
+                .json = path("/src/chips/nrf52840.json"),
+            },
+            .memory_regions = &.{
+                .{ .offset = 0x00000000, .length = 0x100000, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 0x40000, .kind = .ram },
+
+                // EXTFLASH
+                .{ .offset = 0x12000000, .length = 0x8000000, .kind = .flash },
+
+                // CODE_RAM
+                .{ .offset = 0x800000, .length = 0x40000, .kind = .ram },
+            },
+        },
+    };
+
+    pub const nrf52832 = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "nrf52",
+            .url = "https://www.nordicsemi.com/products/nrf52832",
+            .cpu = .cortex_m4,
+            .register_definition = .{
+                .json = path("/src/chips/nrf52.json"),
+            },
+            .memory_regions = &.{
+                .{ .offset = 0x00000000, .length = 0x80000, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 0x10000, .kind = .ram },
+            },
+        },
+    };
+};
+
+pub const boards = struct {
+    pub const nordic = struct {
+        pub const nRF52840_Dongle = .{
+            .preferred_format = .elf,
+            .chip = chips.nrf52840.chip,
+            .board = .{
+                .name = "nRF52840 Dongle",
+                .url = "https://www.nordicsemi.com/Products/Development-hardware/nrf52840-dongle",
+                .source_file = path("/src/boards/nrf52840-dongle.zig"),
             },
-            .backing = .{ .chip = @field(chips, decl.name) },
-            .optimize = optimize,
-        });
-        exe.installArtifact(b);
-    }
+        };
+    };
+};
+
+pub fn build(b: *std.build.Builder) void {
+    _ = b;
 }
diff --git a/build.zig.zon b/build.zig.zon
index f69b76de5..64c0de6cc 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -1,10 +1,5 @@
 .{
     .name = "microzig-nordic-nrf5x",
     .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
-            .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
-        },
-    },
+    .dependencies = .{},
 }
diff --git a/src/boards/nrf52840-dongle.zig b/src/boards/nrf52840-dongle.zig
new file mode 100644
index 000000000..8bbed2fc5
--- /dev/null
+++ b/src/boards/nrf52840-dongle.zig
@@ -0,0 +1 @@
+// TODO: Implement board support
diff --git a/src/chips.zig b/src/chips.zig
deleted file mode 100644
index f53d85b86..000000000
--- a/src/chips.zig
+++ /dev/null
@@ -1,38 +0,0 @@
-const std = @import("std");
-const micro = @import("microzig");
-const Chip = micro.Chip;
-const MemoryRegion = micro.MemoryRegion;
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
-
-pub const nrf52840 = Chip{
-    .name = "nrf52840",
-    .source = .{ .path = root_dir() ++ "/chips/nrf52840.zig" },
-    .json_register_schema = .{ .path = root_dir() ++ "/chips.nrf52840.json" },
-    .cpu = micro.cpus.cortex_m4,
-
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x00000000, .length = 0x100000, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 0x40000, .kind = .ram },
-
-        // EXTFLASH
-        MemoryRegion{ .offset = 0x12000000, .length = 0x8000000, .kind = .flash },
-
-        // CODE_RAM
-        MemoryRegion{ .offset = 0x800000, .length = 0x40000, .kind = .ram },
-    },
-};
-
-pub const nrf52832 = Chip{
-    .name = "nrf52",
-    .source = .{ .path = root_dir() ++ "/chips/nrf52.zig" },
-    .json_register_schema = .{ .path = root_dir() ++ "/chips.nrf52.json" },
-    .cpu = micro.cpus.cortex_m4,
-
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x00000000, .length = 0x80000, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 0x10000, .kind = .ram },
-    },
-};
diff --git a/src/chips/nrf52.zig b/src/chips/nrf52.zig
deleted file mode 100644
index 0f6b36873..000000000
--- a/src/chips/nrf52.zig
+++ /dev/null
@@ -1,16821 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    ///  nRF52832 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller
-    pub const nrf52 = struct {
-        pub const properties = struct {
-            pub const @"cpu.nvic_prio_bits" = "3";
-            pub const @"cpu.mpu" = "1";
-            pub const @"cpu.fpu" = "1";
-            pub const @"cpu.revision" = "r0p1";
-            pub const @"cpu.vendor_systick_config" = "0";
-            pub const license =
-                \\
-                \\Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n
-                \\\n
-                \\Redistribution and use in source and binary forms, with or without\n
-                \\modification, are permitted provided that the following conditions are met:\n
-                \\\n
-                \\1. Redistributions of source code must retain the above copyright notice, this\n
-                \\   list of conditions and the following disclaimer.\n
-                \\\n
-                \\2. Redistributions in binary form must reproduce the above copyright\n
-                \\   notice, this list of conditions and the following disclaimer in the\n
-                \\   documentation and/or other materials provided with the distribution.\n
-                \\\n
-                \\3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
-                \\   contributors may be used to endorse or promote products derived from this\n
-                \\   software without specific prior written permission.\n
-                \\\n
-                \\THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
-                \\AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
-                \\IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
-                \\ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
-                \\LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
-                \\CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
-                \\SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
-                \\INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
-                \\CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
-                \\ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
-                \\POSSIBILITY OF SUCH DAMAGE.\n
-                \\        
-            ;
-            pub const @"cpu.name" = "CM4";
-            pub const @"cpu.endian" = "little";
-        };
-
-        pub const VectorTable = extern struct {
-            const Handler = micro.interrupt.Handler;
-            const unhandled = micro.interrupt.unhandled;
-
-            initial_stack_pointer: u32,
-            Reset: Handler = unhandled,
-            NMI: Handler = unhandled,
-            HardFault: Handler = unhandled,
-            MemManageFault: Handler = unhandled,
-            BusFault: Handler = unhandled,
-            UsageFault: Handler = unhandled,
-            reserved5: [4]u32 = undefined,
-            SVCall: Handler = unhandled,
-            DebugMonitor: Handler = unhandled,
-            reserved11: [1]u32 = undefined,
-            PendSV: Handler = unhandled,
-            SysTick: Handler = unhandled,
-            POWER_CLOCK: Handler = unhandled,
-            RADIO: Handler = unhandled,
-            UARTE0_UART0: Handler = unhandled,
-            SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: Handler = unhandled,
-            SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: Handler = unhandled,
-            NFCT: Handler = unhandled,
-            GPIOTE: Handler = unhandled,
-            SAADC: Handler = unhandled,
-            TIMER0: Handler = unhandled,
-            TIMER1: Handler = unhandled,
-            TIMER2: Handler = unhandled,
-            RTC0: Handler = unhandled,
-            TEMP: Handler = unhandled,
-            RNG: Handler = unhandled,
-            ECB: Handler = unhandled,
-            CCM_AAR: Handler = unhandled,
-            WDT: Handler = unhandled,
-            RTC1: Handler = unhandled,
-            QDEC: Handler = unhandled,
-            COMP_LPCOMP: Handler = unhandled,
-            SWI0_EGU0: Handler = unhandled,
-            SWI1_EGU1: Handler = unhandled,
-            SWI2_EGU2: Handler = unhandled,
-            SWI3_EGU3: Handler = unhandled,
-            SWI4_EGU4: Handler = unhandled,
-            SWI5_EGU5: Handler = unhandled,
-            TIMER3: Handler = unhandled,
-            TIMER4: Handler = unhandled,
-            PWM0: Handler = unhandled,
-            PDM: Handler = unhandled,
-            reserved44: [2]u32 = undefined,
-            MWU: Handler = unhandled,
-            PWM1: Handler = unhandled,
-            PWM2: Handler = unhandled,
-            SPIM2_SPIS2_SPI2: Handler = unhandled,
-            RTC2: Handler = unhandled,
-            I2S: Handler = unhandled,
-            FPU: Handler = unhandled,
-        };
-
-        pub const peripherals = struct {
-            ///  Factory Information Configuration Registers
-            pub const FICR = @as(*volatile types.peripherals.FICR, @ptrFromInt(0x10000000));
-            ///  User Information Configuration Registers
-            pub const UICR = @as(*volatile types.peripherals.UICR, @ptrFromInt(0x10001000));
-            ///  Block Protect
-            pub const BPROT = @as(*volatile types.peripherals.BPROT, @ptrFromInt(0x40000000));
-            ///  Power control
-            pub const POWER = @as(*volatile types.peripherals.POWER, @ptrFromInt(0x40000000));
-            ///  Clock control
-            pub const CLOCK = @as(*volatile types.peripherals.CLOCK, @ptrFromInt(0x40000000));
-            ///  2.4 GHz Radio
-            pub const RADIO = @as(*volatile types.peripherals.RADIO, @ptrFromInt(0x40001000));
-            ///  UART with EasyDMA
-            pub const UARTE0 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40002000));
-            ///  Universal Asynchronous Receiver/Transmitter
-            pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40002000));
-            ///  Serial Peripheral Interface Master with EasyDMA 0
-            pub const SPIM0 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40003000));
-            ///  SPI Slave 0
-            pub const SPIS0 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40003000));
-            ///  I2C compatible Two-Wire Master Interface with EasyDMA 0
-            pub const TWIM0 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40003000));
-            ///  I2C compatible Two-Wire Slave Interface with EasyDMA 0
-            pub const TWIS0 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40003000));
-            ///  Serial Peripheral Interface 0
-            pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40003000));
-            ///  I2C compatible Two-Wire Interface 0
-            pub const TWI0 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40003000));
-            ///  Serial Peripheral Interface Master with EasyDMA 1
-            pub const SPIM1 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40004000));
-            ///  SPI Slave 1
-            pub const SPIS1 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40004000));
-            ///  I2C compatible Two-Wire Master Interface with EasyDMA 1
-            pub const TWIM1 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40004000));
-            ///  I2C compatible Two-Wire Slave Interface with EasyDMA 1
-            pub const TWIS1 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40004000));
-            ///  Serial Peripheral Interface 1
-            pub const SPI1 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40004000));
-            ///  I2C compatible Two-Wire Interface 1
-            pub const TWI1 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40004000));
-            ///  NFC-A compatible radio
-            pub const NFCT = @as(*volatile types.peripherals.NFCT, @ptrFromInt(0x40005000));
-            ///  GPIO Tasks and Events
-            pub const GPIOTE = @as(*volatile types.peripherals.GPIOTE, @ptrFromInt(0x40006000));
-            ///  Analog to Digital Converter
-            pub const SAADC = @as(*volatile types.peripherals.SAADC, @ptrFromInt(0x40007000));
-            ///  Timer/Counter 0
-            pub const TIMER0 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40008000));
-            ///  Timer/Counter 1
-            pub const TIMER1 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40009000));
-            ///  Timer/Counter 2
-            pub const TIMER2 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4000a000));
-            ///  Real time counter 0
-            pub const RTC0 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x4000b000));
-            ///  Temperature Sensor
-            pub const TEMP = @as(*volatile types.peripherals.TEMP, @ptrFromInt(0x4000c000));
-            ///  Random Number Generator
-            pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x4000d000));
-            ///  AES ECB Mode Encryption
-            pub const ECB = @as(*volatile types.peripherals.ECB, @ptrFromInt(0x4000e000));
-            ///  AES CCM Mode Encryption
-            pub const CCM = @as(*volatile types.peripherals.CCM, @ptrFromInt(0x4000f000));
-            ///  Accelerated Address Resolver
-            pub const AAR = @as(*volatile types.peripherals.AAR, @ptrFromInt(0x4000f000));
-            ///  Watchdog Timer
-            pub const WDT = @as(*volatile types.peripherals.WDT, @ptrFromInt(0x40010000));
-            ///  Real time counter 1
-            pub const RTC1 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40011000));
-            ///  Quadrature Decoder
-            pub const QDEC = @as(*volatile types.peripherals.QDEC, @ptrFromInt(0x40012000));
-            ///  Comparator
-            pub const COMP = @as(*volatile types.peripherals.COMP, @ptrFromInt(0x40013000));
-            ///  Low Power Comparator
-            pub const LPCOMP = @as(*volatile types.peripherals.LPCOMP, @ptrFromInt(0x40013000));
-            ///  Software interrupt 0
-            pub const SWI0 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40014000));
-            ///  Event Generator Unit 0
-            pub const EGU0 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40014000));
-            ///  Software interrupt 1
-            pub const SWI1 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40015000));
-            ///  Event Generator Unit 1
-            pub const EGU1 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40015000));
-            ///  Software interrupt 2
-            pub const SWI2 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40016000));
-            ///  Event Generator Unit 2
-            pub const EGU2 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40016000));
-            ///  Software interrupt 3
-            pub const SWI3 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40017000));
-            ///  Event Generator Unit 3
-            pub const EGU3 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40017000));
-            ///  Software interrupt 4
-            pub const SWI4 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40018000));
-            ///  Event Generator Unit 4
-            pub const EGU4 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40018000));
-            ///  Software interrupt 5
-            pub const SWI5 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40019000));
-            ///  Event Generator Unit 5
-            pub const EGU5 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40019000));
-            ///  Timer/Counter 3
-            pub const TIMER3 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001a000));
-            ///  Timer/Counter 4
-            pub const TIMER4 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001b000));
-            ///  Pulse Width Modulation Unit 0
-            pub const PWM0 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4001c000));
-            ///  Pulse Density Modulation (Digital Microphone) Interface
-            pub const PDM = @as(*volatile types.peripherals.PDM, @ptrFromInt(0x4001d000));
-            ///  Non Volatile Memory Controller
-            pub const NVMC = @as(*volatile types.peripherals.NVMC, @ptrFromInt(0x4001e000));
-            ///  Programmable Peripheral Interconnect
-            pub const PPI = @as(*volatile types.peripherals.PPI, @ptrFromInt(0x4001f000));
-            ///  Memory Watch Unit
-            pub const MWU = @as(*volatile types.peripherals.MWU, @ptrFromInt(0x40020000));
-            ///  Pulse Width Modulation Unit 1
-            pub const PWM1 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40021000));
-            ///  Pulse Width Modulation Unit 2
-            pub const PWM2 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40022000));
-            ///  Serial Peripheral Interface Master with EasyDMA 2
-            pub const SPIM2 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40023000));
-            ///  SPI Slave 2
-            pub const SPIS2 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40023000));
-            ///  Serial Peripheral Interface 2
-            pub const SPI2 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40023000));
-            ///  Real time counter 2
-            pub const RTC2 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40024000));
-            ///  Inter-IC Sound
-            pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x40025000));
-            ///  FPU
-            pub const FPU = @as(*volatile types.peripherals.FPU, @ptrFromInt(0x40026000));
-            ///  GPIO Port 1
-            pub const P0 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000000));
-            ///  System Tick Timer
-            pub const SysTick = @as(*volatile types.peripherals.SCS.SysTick, @ptrFromInt(0xe000e010));
-        };
-    };
-};
-
-pub const types = struct {
-    pub const peripherals = struct {
-        ///  System Control Space
-        pub const SCS = struct {
-            ///  System Tick Timer
-            pub const SysTick = extern struct {
-                ///  SysTick Control and Status Register
-                CTRL: mmio.Mmio(packed struct(u32) {
-                    ENABLE: u1,
-                    TICKINT: u1,
-                    CLKSOURCE: u1,
-                    reserved16: u13,
-                    COUNTFLAG: u1,
-                    padding: u15,
-                }),
-                ///  SysTick Reload Value Register
-                LOAD: mmio.Mmio(packed struct(u32) {
-                    RELOAD: u24,
-                    padding: u8,
-                }),
-                ///  SysTick Current Value Register
-                VAL: mmio.Mmio(packed struct(u32) {
-                    CURRENT: u24,
-                    padding: u8,
-                }),
-                ///  SysTick Calibration Register
-                CALIB: mmio.Mmio(packed struct(u32) {
-                    TENMS: u24,
-                    reserved30: u6,
-                    SKEW: u1,
-                    NOREF: u1,
-                }),
-            };
-        };
-
-        ///  Factory Information Configuration Registers
-        pub const FICR = extern struct {
-            reserved16: [16]u8,
-            ///  Code memory page size
-            CODEPAGESIZE: mmio.Mmio(packed struct(u32) {
-                ///  Code memory page size
-                CODEPAGESIZE: u32,
-            }),
-            ///  Code memory size
-            CODESIZE: mmio.Mmio(packed struct(u32) {
-                ///  Code memory size in number of pages
-                CODESIZE: u32,
-            }),
-            reserved96: [72]u8,
-            ///  Description collection[0]: Device identifier
-            DEVICEID: [2]mmio.Mmio(packed struct(u32) {
-                ///  64 bit unique device identifier
-                DEVICEID: u32,
-            }),
-            reserved128: [24]u8,
-            ///  Description collection[0]: Encryption Root, word 0
-            ER: [4]mmio.Mmio(packed struct(u32) {
-                ///  Encryption Root, word n
-                ER: u32,
-            }),
-            ///  Description collection[0]: Identity Root, word 0
-            IR: [4]mmio.Mmio(packed struct(u32) {
-                ///  Identity Root, word n
-                IR: u32,
-            }),
-            ///  Device address type
-            DEVICEADDRTYPE: mmio.Mmio(packed struct(u32) {
-                ///  Device address type
-                DEVICEADDRTYPE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Public address
-                        Public = 0x0,
-                        ///  Random address
-                        Random = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Description collection[0]: Device address 0
-            DEVICEADDR: [2]mmio.Mmio(packed struct(u32) {
-                ///  48 bit device address
-                DEVICEADDR: u32,
-            }),
-        };
-
-        ///  User Information Configuration Registers
-        pub const UICR = extern struct {
-            ///  Unspecified
-            UNUSED0: u32,
-            ///  Unspecified
-            UNUSED1: u32,
-            ///  Unspecified
-            UNUSED2: u32,
-            reserved16: [4]u8,
-            ///  Unspecified
-            UNUSED3: u32,
-            ///  Description collection[0]: Reserved for Nordic firmware design
-            NRFFW: [15]mmio.Mmio(packed struct(u32) {
-                ///  Reserved for Nordic firmware design
-                NRFFW: u32,
-            }),
-            ///  Description collection[0]: Reserved for Nordic hardware design
-            NRFHW: [12]mmio.Mmio(packed struct(u32) {
-                ///  Reserved for Nordic hardware design
-                NRFHW: u32,
-            }),
-            ///  Description collection[0]: Reserved for customer
-            CUSTOMER: [32]mmio.Mmio(packed struct(u32) {
-                ///  Reserved for customer
-                CUSTOMER: u32,
-            }),
-            reserved512: [256]u8,
-            ///  Description collection[0]: Mapping of the nRESET function (see POWER chapter for details)
-            PSELRESET: [2]mmio.Mmio(packed struct(u32) {
-                ///  GPIO number P0.n onto which Reset is exposed
-                PIN: u6,
-                reserved31: u25,
-                ///  Connection
-                CONNECT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disconnect
-                        Disconnected = 0x1,
-                        ///  Connect
-                        Connected = 0x0,
-                    },
-                },
-            }),
-            ///  Access Port protection
-            APPROTECT: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable Access Port protection. Any other value than 0xFF being written to this field will enable protection.
-                PALL: packed union {
-                    raw: u8,
-                    value: enum(u8) {
-                        ///  Disable
-                        Disabled = 0xff,
-                        ///  Enable
-                        Enabled = 0x0,
-                        _,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
-            NFCPINS: mmio.Mmio(packed struct(u32) {
-                ///  Setting of pins dedicated to NFC functionality
-                PROTECT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Operation as GPIO pins. Same protection as normal GPIO pins
-                        Disabled = 0x0,
-                        ///  Operation as NFC antenna pins. Configures the protection for NFC operation
-                        NFC = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  Block Protect
-        pub const BPROT = extern struct {
-            reserved1536: [1536]u8,
-            ///  Block protect configuration register 0
-            CONFIG0: mmio.Mmio(packed struct(u32) {
-                ///  Enable protection for region 0. Write '0' has no effect.
-                REGION0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 1. Write '0' has no effect.
-                REGION1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 2. Write '0' has no effect.
-                REGION2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 3. Write '0' has no effect.
-                REGION3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 4. Write '0' has no effect.
-                REGION4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 5. Write '0' has no effect.
-                REGION5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 6. Write '0' has no effect.
-                REGION6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 7. Write '0' has no effect.
-                REGION7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 8. Write '0' has no effect.
-                REGION8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 9. Write '0' has no effect.
-                REGION9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 10. Write '0' has no effect.
-                REGION10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 11. Write '0' has no effect.
-                REGION11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 12. Write '0' has no effect.
-                REGION12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 13. Write '0' has no effect.
-                REGION13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 14. Write '0' has no effect.
-                REGION14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 15. Write '0' has no effect.
-                REGION15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 16. Write '0' has no effect.
-                REGION16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 17. Write '0' has no effect.
-                REGION17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 18. Write '0' has no effect.
-                REGION18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 19. Write '0' has no effect.
-                REGION19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 20. Write '0' has no effect.
-                REGION20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 21. Write '0' has no effect.
-                REGION21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 22. Write '0' has no effect.
-                REGION22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 23. Write '0' has no effect.
-                REGION23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 24. Write '0' has no effect.
-                REGION24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 25. Write '0' has no effect.
-                REGION25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 26. Write '0' has no effect.
-                REGION26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 27. Write '0' has no effect.
-                REGION27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 28. Write '0' has no effect.
-                REGION28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 29. Write '0' has no effect.
-                REGION29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 30. Write '0' has no effect.
-                REGION30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 31. Write '0' has no effect.
-                REGION31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enable
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            ///  Block protect configuration register 1
-            CONFIG1: mmio.Mmio(packed struct(u32) {
-                ///  Enable protection for region 32. Write '0' has no effect.
-                REGION32: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 33. Write '0' has no effect.
-                REGION33: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 34. Write '0' has no effect.
-                REGION34: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 35. Write '0' has no effect.
-                REGION35: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 36. Write '0' has no effect.
-                REGION36: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 37. Write '0' has no effect.
-                REGION37: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 38. Write '0' has no effect.
-                REGION38: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 39. Write '0' has no effect.
-                REGION39: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 40. Write '0' has no effect.
-                REGION40: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 41. Write '0' has no effect.
-                REGION41: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 42. Write '0' has no effect.
-                REGION42: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 43. Write '0' has no effect.
-                REGION43: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 44. Write '0' has no effect.
-                REGION44: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 45. Write '0' has no effect.
-                REGION45: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 46. Write '0' has no effect.
-                REGION46: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 47. Write '0' has no effect.
-                REGION47: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 48. Write '0' has no effect.
-                REGION48: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 49. Write '0' has no effect.
-                REGION49: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 50. Write '0' has no effect.
-                REGION50: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 51. Write '0' has no effect.
-                REGION51: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 52. Write '0' has no effect.
-                REGION52: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 53. Write '0' has no effect.
-                REGION53: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 54. Write '0' has no effect.
-                REGION54: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 55. Write '0' has no effect.
-                REGION55: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 56. Write '0' has no effect.
-                REGION56: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 57. Write '0' has no effect.
-                REGION57: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 58. Write '0' has no effect.
-                REGION58: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 59. Write '0' has no effect.
-                REGION59: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 60. Write '0' has no effect.
-                REGION60: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 61. Write '0' has no effect.
-                REGION61: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 62. Write '0' has no effect.
-                REGION62: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 63. Write '0' has no effect.
-                REGION63: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            ///  Disable protection mechanism in debug interface mode
-            DISABLEINDEBUG: mmio.Mmio(packed struct(u32) {
-                ///  Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode.
-                DISABLEINDEBUG: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable in debug
-                        Disabled = 0x1,
-                        ///  Enable in debug
-                        Enabled = 0x0,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Unspecified
-            UNUSED0: u32,
-            ///  Block protect configuration register 2
-            CONFIG2: mmio.Mmio(packed struct(u32) {
-                ///  Enable protection for region 64. Write '0' has no effect.
-                REGION64: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 65. Write '0' has no effect.
-                REGION65: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 66. Write '0' has no effect.
-                REGION66: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 67. Write '0' has no effect.
-                REGION67: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 68. Write '0' has no effect.
-                REGION68: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 69. Write '0' has no effect.
-                REGION69: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 70. Write '0' has no effect.
-                REGION70: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 71. Write '0' has no effect.
-                REGION71: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 72. Write '0' has no effect.
-                REGION72: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 73. Write '0' has no effect.
-                REGION73: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 74. Write '0' has no effect.
-                REGION74: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 75. Write '0' has no effect.
-                REGION75: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 76. Write '0' has no effect.
-                REGION76: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 77. Write '0' has no effect.
-                REGION77: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 78. Write '0' has no effect.
-                REGION78: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 79. Write '0' has no effect.
-                REGION79: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 80. Write '0' has no effect.
-                REGION80: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 81. Write '0' has no effect.
-                REGION81: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 82. Write '0' has no effect.
-                REGION82: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 83. Write '0' has no effect.
-                REGION83: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 84. Write '0' has no effect.
-                REGION84: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 85. Write '0' has no effect.
-                REGION85: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 86. Write '0' has no effect.
-                REGION86: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 87. Write '0' has no effect.
-                REGION87: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 88. Write '0' has no effect.
-                REGION88: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 89. Write '0' has no effect.
-                REGION89: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 90. Write '0' has no effect.
-                REGION90: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 91. Write '0' has no effect.
-                REGION91: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 92. Write '0' has no effect.
-                REGION92: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 93. Write '0' has no effect.
-                REGION93: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 94. Write '0' has no effect.
-                REGION94: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 95. Write '0' has no effect.
-                REGION95: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            ///  Block protect configuration register 3
-            CONFIG3: mmio.Mmio(packed struct(u32) {
-                ///  Enable protection for region 96. Write '0' has no effect.
-                REGION96: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 97. Write '0' has no effect.
-                REGION97: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 98. Write '0' has no effect.
-                REGION98: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 99. Write '0' has no effect.
-                REGION99: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 100. Write '0' has no effect.
-                REGION100: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 101. Write '0' has no effect.
-                REGION101: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 102. Write '0' has no effect.
-                REGION102: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 103. Write '0' has no effect.
-                REGION103: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 104. Write '0' has no effect.
-                REGION104: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 105. Write '0' has no effect.
-                REGION105: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 106. Write '0' has no effect.
-                REGION106: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 107. Write '0' has no effect.
-                REGION107: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 108. Write '0' has no effect.
-                REGION108: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 109. Write '0' has no effect.
-                REGION109: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 110. Write '0' has no effect.
-                REGION110: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 111. Write '0' has no effect.
-                REGION111: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 112. Write '0' has no effect.
-                REGION112: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 113. Write '0' has no effect.
-                REGION113: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 114. Write '0' has no effect.
-                REGION114: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 115. Write '0' has no effect.
-                REGION115: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 116. Write '0' has no effect.
-                REGION116: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 117. Write '0' has no effect.
-                REGION117: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 118. Write '0' has no effect.
-                REGION118: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 119. Write '0' has no effect.
-                REGION119: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 120. Write '0' has no effect.
-                REGION120: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 121. Write '0' has no effect.
-                REGION121: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 122. Write '0' has no effect.
-                REGION122: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 123. Write '0' has no effect.
-                REGION123: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 124. Write '0' has no effect.
-                REGION124: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 125. Write '0' has no effect.
-                REGION125: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 126. Write '0' has no effect.
-                REGION126: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable protection for region 127. Write '0' has no effect.
-                REGION127: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Protection disabled
-                        Disabled = 0x0,
-                        ///  Protection enabled
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-        };
-
-        ///  Power control
-        pub const POWER = extern struct {
-            reserved120: [120]u8,
-            ///  Enable constant latency mode
-            TASKS_CONSTLAT: u32,
-            ///  Enable low power mode (variable latency)
-            TASKS_LOWPWR: u32,
-            reserved264: [136]u8,
-            ///  Power failure warning
-            EVENTS_POFWARN: u32,
-            reserved276: [8]u8,
-            ///  CPU entered WFI/WFE sleep
-            EVENTS_SLEEPENTER: u32,
-            ///  CPU exited WFI/WFE sleep
-            EVENTS_SLEEPEXIT: u32,
-            reserved772: [488]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Write '1' to Enable interrupt for POFWARN event
-                POFWARN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved5: u2,
-                ///  Write '1' to Enable interrupt for SLEEPENTER event
-                SLEEPENTER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for SLEEPEXIT event
-                SLEEPEXIT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u25,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Write '1' to Disable interrupt for POFWARN event
-                POFWARN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved5: u2,
-                ///  Write '1' to Disable interrupt for SLEEPENTER event
-                SLEEPENTER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for SLEEPEXIT event
-                SLEEPEXIT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u25,
-            }),
-            reserved1024: [244]u8,
-            ///  Reset reason
-            RESETREAS: mmio.Mmio(packed struct(u32) {
-                ///  Reset from pin-reset detected
-                RESETPIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset from watchdog detected
-                DOG: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset from soft reset detected
-                SREQ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset from CPU lock-up detected
-                LOCKUP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                reserved16: u12,
-                ///  Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO
-                OFF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP
-                LPCOMP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode
-                DIF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset due to wake up from System OFF mode by NFC field detect
-                NFC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            reserved1064: [36]u8,
-            ///  Deprecated register - RAM status register
-            RAMSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  RAM block 0 is on or off/powering up
-                RAMBLOCK0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        Off = 0x0,
-                        ///  On
-                        On = 0x1,
-                    },
-                },
-                ///  RAM block 1 is on or off/powering up
-                RAMBLOCK1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        Off = 0x0,
-                        ///  On
-                        On = 0x1,
-                    },
-                },
-                ///  RAM block 2 is on or off/powering up
-                RAMBLOCK2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        Off = 0x0,
-                        ///  On
-                        On = 0x1,
-                    },
-                },
-                ///  RAM block 3 is on or off/powering up
-                RAMBLOCK3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        Off = 0x0,
-                        ///  On
-                        On = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1280: [212]u8,
-            ///  System OFF register
-            SYSTEMOFF: mmio.Mmio(packed struct(u32) {
-                ///  Enable System OFF mode
-                SYSTEMOFF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Enable System OFF mode
-                        Enter = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1296: [12]u8,
-            ///  Power failure comparator configuration
-            POFCON: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable power failure comparator
-                POF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Power failure comparator threshold setting
-                THRESHOLD: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Set threshold to 1.7 V
-                        V17 = 0x4,
-                        ///  Set threshold to 1.8 V
-                        V18 = 0x5,
-                        ///  Set threshold to 1.9 V
-                        V19 = 0x6,
-                        ///  Set threshold to 2.0 V
-                        V20 = 0x7,
-                        ///  Set threshold to 2.1 V
-                        V21 = 0x8,
-                        ///  Set threshold to 2.2 V
-                        V22 = 0x9,
-                        ///  Set threshold to 2.3 V
-                        V23 = 0xa,
-                        ///  Set threshold to 2.4 V
-                        V24 = 0xb,
-                        ///  Set threshold to 2.5 V
-                        V25 = 0xc,
-                        ///  Set threshold to 2.6 V
-                        V26 = 0xd,
-                        ///  Set threshold to 2.7 V
-                        V27 = 0xe,
-                        ///  Set threshold to 2.8 V
-                        V28 = 0xf,
-                        _,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved1308: [8]u8,
-            ///  General purpose retention register
-            GPREGRET: mmio.Mmio(packed struct(u32) {
-                ///  General purpose retention register
-                GPREGRET: u8,
-                padding: u24,
-            }),
-            ///  General purpose retention register
-            GPREGRET2: mmio.Mmio(packed struct(u32) {
-                ///  General purpose retention register
-                GPREGRET: u8,
-                padding: u24,
-            }),
-            ///  Deprecated register - RAM on/off register (this register is retained)
-            RAMON: mmio.Mmio(packed struct(u32) {
-                ///  Keep RAM block 0 on or off in system ON Mode
-                ONRAM0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        RAM0Off = 0x0,
-                        ///  On
-                        RAM0On = 0x1,
-                    },
-                },
-                ///  Keep RAM block 1 on or off in system ON Mode
-                ONRAM1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        RAM1Off = 0x0,
-                        ///  On
-                        RAM1On = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Keep retention on RAM block 0 when RAM block is switched off
-                OFFRAM0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        RAM0Off = 0x0,
-                        ///  On
-                        RAM0On = 0x1,
-                    },
-                },
-                ///  Keep retention on RAM block 1 when RAM block is switched off
-                OFFRAM1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        RAM1Off = 0x0,
-                        ///  On
-                        RAM1On = 0x1,
-                    },
-                },
-                padding: u14,
-            }),
-            reserved1364: [44]u8,
-            ///  Deprecated register - RAM on/off register (this register is retained)
-            RAMONB: mmio.Mmio(packed struct(u32) {
-                ///  Keep RAM block 2 on or off in system ON Mode
-                ONRAM2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        RAM2Off = 0x0,
-                        ///  On
-                        RAM2On = 0x1,
-                    },
-                },
-                ///  Keep RAM block 3 on or off in system ON Mode
-                ONRAM3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        RAM3Off = 0x0,
-                        ///  On
-                        RAM3On = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Keep retention on RAM block 2 when RAM block is switched off
-                OFFRAM2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        RAM2Off = 0x0,
-                        ///  On
-                        RAM2On = 0x1,
-                    },
-                },
-                ///  Keep retention on RAM block 3 when RAM block is switched off
-                OFFRAM3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        RAM3Off = 0x0,
-                        ///  On
-                        RAM3On = 0x1,
-                    },
-                },
-                padding: u14,
-            }),
-            reserved1400: [32]u8,
-            ///  DC/DC enable register
-            DCDCEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable DC/DC converter
-                DCDCEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  Clock control
-        pub const CLOCK = extern struct {
-            ///  Start HFCLK crystal oscillator
-            TASKS_HFCLKSTART: u32,
-            ///  Stop HFCLK crystal oscillator
-            TASKS_HFCLKSTOP: u32,
-            ///  Start LFCLK source
-            TASKS_LFCLKSTART: u32,
-            ///  Stop LFCLK source
-            TASKS_LFCLKSTOP: u32,
-            ///  Start calibration of LFRC oscillator
-            TASKS_CAL: u32,
-            ///  Start calibration timer
-            TASKS_CTSTART: u32,
-            ///  Stop calibration timer
-            TASKS_CTSTOP: u32,
-            reserved256: [228]u8,
-            ///  HFCLK oscillator started
-            EVENTS_HFCLKSTARTED: u32,
-            ///  LFCLK started
-            EVENTS_LFCLKSTARTED: u32,
-            reserved268: [4]u8,
-            ///  Calibration of LFCLK RC oscillator complete event
-            EVENTS_DONE: u32,
-            ///  Calibration timer timeout
-            EVENTS_CTTO: u32,
-            reserved772: [496]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for HFCLKSTARTED event
-                HFCLKSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for LFCLKSTARTED event
-                LFCLKSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved3: u1,
-                ///  Write '1' to Enable interrupt for DONE event
-                DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CTTO event
-                CTTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for HFCLKSTARTED event
-                HFCLKSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for LFCLKSTARTED event
-                LFCLKSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved3: u1,
-                ///  Write '1' to Disable interrupt for DONE event
-                DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CTTO event
-                CTTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved1032: [252]u8,
-            ///  Status indicating that HFCLKSTART task has been triggered
-            HFCLKRUN: mmio.Mmio(packed struct(u32) {
-                ///  HFCLKSTART task triggered or not
-                STATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Task not triggered
-                        NotTriggered = 0x0,
-                        ///  Task triggered
-                        Triggered = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  HFCLK status
-            HFCLKSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Source of HFCLK
-                SRC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  64 MHz internal oscillator (HFINT)
-                        RC = 0x0,
-                        ///  64 MHz crystal oscillator (HFXO)
-                        Xtal = 0x1,
-                    },
-                },
-                reserved16: u15,
-                ///  HFCLK state
-                STATE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  HFCLK not running
-                        NotRunning = 0x0,
-                        ///  HFCLK running
-                        Running = 0x1,
-                    },
-                },
-                padding: u15,
-            }),
-            reserved1044: [4]u8,
-            ///  Status indicating that LFCLKSTART task has been triggered
-            LFCLKRUN: mmio.Mmio(packed struct(u32) {
-                ///  LFCLKSTART task triggered or not
-                STATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Task not triggered
-                        NotTriggered = 0x0,
-                        ///  Task triggered
-                        Triggered = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  LFCLK status
-            LFCLKSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Source of LFCLK
-                SRC: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  32.768 kHz RC oscillator
-                        RC = 0x0,
-                        ///  32.768 kHz crystal oscillator
-                        Xtal = 0x1,
-                        ///  32.768 kHz synthesized from HFCLK
-                        Synth = 0x2,
-                        _,
-                    },
-                },
-                reserved16: u14,
-                ///  LFCLK state
-                STATE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  LFCLK not running
-                        NotRunning = 0x0,
-                        ///  LFCLK running
-                        Running = 0x1,
-                    },
-                },
-                padding: u15,
-            }),
-            ///  Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
-            LFCLKSRCCOPY: mmio.Mmio(packed struct(u32) {
-                ///  Clock source
-                SRC: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  32.768 kHz RC oscillator
-                        RC = 0x0,
-                        ///  32.768 kHz crystal oscillator
-                        Xtal = 0x1,
-                        ///  32.768 kHz synthesized from HFCLK
-                        Synth = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1304: [248]u8,
-            ///  Clock source for the LFCLK
-            LFCLKSRC: mmio.Mmio(packed struct(u32) {
-                ///  Clock source
-                SRC: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  32.768 kHz RC oscillator
-                        RC = 0x0,
-                        ///  32.768 kHz crystal oscillator
-                        Xtal = 0x1,
-                        ///  32.768 kHz synthesized from HFCLK
-                        Synth = 0x2,
-                        _,
-                    },
-                },
-                reserved16: u14,
-                ///  Enable or disable bypass of LFCLK crystal oscillator with external clock source
-                BYPASS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable (use with Xtal or low-swing external source)
-                        Disabled = 0x0,
-                        ///  Enable (use with rail-to-rail external source)
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable external source for LFCLK
-                EXTERNAL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable external source (use with Xtal)
-                        Disabled = 0x0,
-                        ///  Enable use of external source instead of Xtal (SRC needs to be set to Xtal)
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u14,
-            }),
-            reserved1336: [28]u8,
-            ///  Calibration timer interval
-            CTIV: mmio.Mmio(packed struct(u32) {
-                ///  Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.
-                CTIV: u7,
-                padding: u25,
-            }),
-            reserved1372: [32]u8,
-            ///  Clocking options for the Trace Port debug interface
-            TRACECONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two.
-                TRACEPORTSPEED: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  32 MHz Trace Port clock (TRACECLK = 16 MHz)
-                        @"32MHz" = 0x0,
-                        ///  16 MHz Trace Port clock (TRACECLK = 8 MHz)
-                        @"16MHz" = 0x1,
-                        ///  8 MHz Trace Port clock (TRACECLK = 4 MHz)
-                        @"8MHz" = 0x2,
-                        ///  4 MHz Trace Port clock (TRACECLK = 2 MHz)
-                        @"4MHz" = 0x3,
-                    },
-                },
-                reserved16: u14,
-                ///  Pin multiplexing of trace signals.
-                TRACEMUX: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  GPIOs multiplexed onto all trace-pins
-                        GPIO = 0x0,
-                        ///  SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins
-                        Serial = 0x1,
-                        ///  TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14.
-                        Parallel = 0x2,
-                        _,
-                    },
-                },
-                padding: u14,
-            }),
-        };
-
-        ///  2.4 GHz Radio
-        pub const RADIO = extern struct {
-            ///  Enable RADIO in TX mode
-            TASKS_TXEN: u32,
-            ///  Enable RADIO in RX mode
-            TASKS_RXEN: u32,
-            ///  Start RADIO
-            TASKS_START: u32,
-            ///  Stop RADIO
-            TASKS_STOP: u32,
-            ///  Disable RADIO
-            TASKS_DISABLE: u32,
-            ///  Start the RSSI and take one single sample of the receive signal strength.
-            TASKS_RSSISTART: u32,
-            ///  Stop the RSSI measurement
-            TASKS_RSSISTOP: u32,
-            ///  Start the bit counter
-            TASKS_BCSTART: u32,
-            ///  Stop the bit counter
-            TASKS_BCSTOP: u32,
-            reserved256: [220]u8,
-            ///  RADIO has ramped up and is ready to be started
-            EVENTS_READY: u32,
-            ///  Address sent or received
-            EVENTS_ADDRESS: u32,
-            ///  Packet payload sent or received
-            EVENTS_PAYLOAD: u32,
-            ///  Packet sent or received
-            EVENTS_END: u32,
-            ///  RADIO has been disabled
-            EVENTS_DISABLED: u32,
-            ///  A device address match occurred on the last received packet
-            EVENTS_DEVMATCH: u32,
-            ///  No device address match occurred on the last received packet
-            EVENTS_DEVMISS: u32,
-            ///  Sampling of receive signal strength complete.
-            EVENTS_RSSIEND: u32,
-            reserved296: [8]u8,
-            ///  Bit counter reached bit count value.
-            EVENTS_BCMATCH: u32,
-            reserved304: [4]u8,
-            ///  Packet received with CRC ok
-            EVENTS_CRCOK: u32,
-            ///  Packet received with CRC error
-            EVENTS_CRCERROR: u32,
-            reserved512: [200]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between READY event and START task
-                READY_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between END event and DISABLE task
-                END_DISABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between DISABLED event and TXEN task
-                DISABLED_TXEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between DISABLED event and RXEN task
-                DISABLED_RXEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between ADDRESS event and RSSISTART task
-                ADDRESS_RSSISTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between END event and START task
-                END_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between ADDRESS event and BCSTART task
-                ADDRESS_BCSTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                reserved8: u1,
-                ///  Shortcut between DISABLED event and RSSISTOP task
-                DISABLED_RSSISTOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for ADDRESS event
-                ADDRESS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for PAYLOAD event
-                PAYLOAD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for DISABLED event
-                DISABLED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for DEVMATCH event
-                DEVMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for DEVMISS event
-                DEVMISS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for RSSIEND event
-                RSSIEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u2,
-                ///  Write '1' to Enable interrupt for BCMATCH event
-                BCMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved12: u1,
-                ///  Write '1' to Enable interrupt for CRCOK event
-                CRCOK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CRCERROR event
-                CRCERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u18,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for ADDRESS event
-                ADDRESS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for PAYLOAD event
-                PAYLOAD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for DISABLED event
-                DISABLED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for DEVMATCH event
-                DEVMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for DEVMISS event
-                DEVMISS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for RSSIEND event
-                RSSIEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u2,
-                ///  Write '1' to Disable interrupt for BCMATCH event
-                BCMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved12: u1,
-                ///  Write '1' to Disable interrupt for CRCOK event
-                CRCOK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CRCERROR event
-                CRCERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u18,
-            }),
-            reserved1024: [244]u8,
-            ///  CRC status
-            CRCSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  CRC status of packet received
-                CRCSTATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Packet received with CRC error
-                        CRCError = 0x0,
-                        ///  Packet received with CRC ok
-                        CRCOk = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1032: [4]u8,
-            ///  Received address
-            RXMATCH: mmio.Mmio(packed struct(u32) {
-                ///  Received address
-                RXMATCH: u3,
-                padding: u29,
-            }),
-            ///  CRC field of previously received packet
-            RXCRC: mmio.Mmio(packed struct(u32) {
-                ///  CRC field of previously received packet
-                RXCRC: u24,
-                padding: u8,
-            }),
-            ///  Device address match index
-            DAI: mmio.Mmio(packed struct(u32) {
-                ///  Device address match index
-                DAI: u3,
-                padding: u29,
-            }),
-            reserved1284: [240]u8,
-            ///  Packet pointer
-            PACKETPTR: mmio.Mmio(packed struct(u32) {
-                ///  Packet pointer
-                PACKETPTR: u32,
-            }),
-            ///  Frequency
-            FREQUENCY: mmio.Mmio(packed struct(u32) {
-                ///  Radio channel frequency
-                FREQUENCY: u7,
-                reserved8: u1,
-                ///  Channel map selection.
-                MAP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Channel map between 2400 MHZ .. 2500 MHz
-                        Default = 0x0,
-                        ///  Channel map between 2360 MHZ .. 2460 MHz
-                        Low = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            ///  Output power
-            TXPOWER: mmio.Mmio(packed struct(u32) {
-                ///  RADIO output power.
-                TXPOWER: packed union {
-                    raw: u8,
-                    value: enum(u8) {
-                        ///  +4 dBm
-                        Pos4dBm = 0x4,
-                        ///  +3 dBm
-                        Pos3dBm = 0x3,
-                        ///  0 dBm
-                        @"0dBm" = 0x0,
-                        ///  -4 dBm
-                        Neg4dBm = 0xfc,
-                        ///  -8 dBm
-                        Neg8dBm = 0xf8,
-                        ///  -12 dBm
-                        Neg12dBm = 0xf4,
-                        ///  -16 dBm
-                        Neg16dBm = 0xf0,
-                        ///  -20 dBm
-                        Neg20dBm = 0xec,
-                        ///  Deprecated enumerator - -40 dBm
-                        Neg30dBm = 0xff,
-                        ///  -40 dBm
-                        Neg40dBm = 0xd8,
-                        _,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Data rate and modulation
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation.
-                MODE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  1 Mbit/s Nordic proprietary radio mode
-                        Nrf_1Mbit = 0x0,
-                        ///  2 Mbit/s Nordic proprietary radio mode
-                        Nrf_2Mbit = 0x1,
-                        ///  Deprecated enumerator - 250 kbit/s Nordic proprietary radio mode
-                        Nrf_250Kbit = 0x2,
-                        ///  1 Mbit/s Bluetooth Low Energy
-                        Ble_1Mbit = 0x3,
-                        ///  2 Mbit/s Bluetooth Low Energy
-                        Ble_2Mbit = 0x4,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Packet configuration register 0
-            PCNF0: mmio.Mmio(packed struct(u32) {
-                ///  Length on air of LENGTH field in number of bits.
-                LFLEN: u4,
-                reserved8: u4,
-                ///  Length on air of S0 field in number of bytes.
-                S0LEN: u1,
-                reserved16: u7,
-                ///  Length on air of S1 field in number of bits.
-                S1LEN: u4,
-                ///  Include or exclude S1 field in RAM
-                S1INCL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Include S1 field in RAM only if S1LEN > 0
-                        Automatic = 0x0,
-                        ///  Always include S1 field in RAM independent of S1LEN
-                        Include = 0x1,
-                    },
-                },
-                reserved24: u3,
-                ///  Length of preamble on air. Decision point: TASKS_START task
-                PLEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  8-bit preamble
-                        @"8bit" = 0x0,
-                        ///  16-bit preamble
-                        @"16bit" = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            ///  Packet configuration register 1
-            PCNF1: mmio.Mmio(packed struct(u32) {
-                ///  Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.
-                MAXLEN: u8,
-                ///  Static length in number of bytes
-                STATLEN: u8,
-                ///  Base address length in number of bytes
-                BALEN: u3,
-                reserved24: u5,
-                ///  On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.
-                ENDIAN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Least Significant bit on air first
-                        Little = 0x0,
-                        ///  Most significant bit on air first
-                        Big = 0x1,
-                    },
-                },
-                ///  Enable or disable packet whitening
-                WHITEEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u6,
-            }),
-            ///  Base address 0
-            BASE0: mmio.Mmio(packed struct(u32) {
-                ///  Base address 0
-                BASE0: u32,
-            }),
-            ///  Base address 1
-            BASE1: mmio.Mmio(packed struct(u32) {
-                ///  Base address 1
-                BASE1: u32,
-            }),
-            ///  Prefixes bytes for logical addresses 0-3
-            PREFIX0: mmio.Mmio(packed struct(u32) {
-                ///  Address prefix 0.
-                AP0: u8,
-                ///  Address prefix 1.
-                AP1: u8,
-                ///  Address prefix 2.
-                AP2: u8,
-                ///  Address prefix 3.
-                AP3: u8,
-            }),
-            ///  Prefixes bytes for logical addresses 4-7
-            PREFIX1: mmio.Mmio(packed struct(u32) {
-                ///  Address prefix 4.
-                AP4: u8,
-                ///  Address prefix 5.
-                AP5: u8,
-                ///  Address prefix 6.
-                AP6: u8,
-                ///  Address prefix 7.
-                AP7: u8,
-            }),
-            ///  Transmit address select
-            TXADDRESS: mmio.Mmio(packed struct(u32) {
-                ///  Transmit address select
-                TXADDRESS: u3,
-                padding: u29,
-            }),
-            ///  Receive address select
-            RXADDRESSES: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable reception on logical address 0.
-                ADDR0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 1.
-                ADDR1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 2.
-                ADDR2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 3.
-                ADDR3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 4.
-                ADDR4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 5.
-                ADDR5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 6.
-                ADDR6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 7.
-                ADDR7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  CRC configuration
-            CRCCNF: mmio.Mmio(packed struct(u32) {
-                ///  CRC length in number of bytes.
-                LEN: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  CRC length is zero and CRC calculation is disabled
-                        Disabled = 0x0,
-                        ///  CRC length is one byte and CRC calculation is enabled
-                        One = 0x1,
-                        ///  CRC length is two bytes and CRC calculation is enabled
-                        Two = 0x2,
-                        ///  CRC length is three bytes and CRC calculation is enabled
-                        Three = 0x3,
-                    },
-                },
-                reserved8: u6,
-                ///  Include or exclude packet address field out of CRC calculation.
-                SKIPADDR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  CRC calculation includes address field
-                        Include = 0x0,
-                        ///  CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.
-                        Skip = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            ///  CRC polynomial
-            CRCPOLY: mmio.Mmio(packed struct(u32) {
-                ///  CRC polynomial
-                CRCPOLY: u24,
-                padding: u8,
-            }),
-            ///  CRC initial value
-            CRCINIT: mmio.Mmio(packed struct(u32) {
-                ///  CRC initial value
-                CRCINIT: u24,
-                padding: u8,
-            }),
-            ///  Unspecified
-            UNUSED0: u32,
-            ///  Inter Frame Spacing in us
-            TIFS: mmio.Mmio(packed struct(u32) {
-                ///  Inter Frame Spacing in us
-                TIFS: u8,
-                padding: u24,
-            }),
-            ///  RSSI sample
-            RSSISAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  RSSI sample
-                RSSISAMPLE: u7,
-                padding: u25,
-            }),
-            reserved1360: [4]u8,
-            ///  Current radio state
-            STATE: mmio.Mmio(packed struct(u32) {
-                ///  Current radio state
-                STATE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  RADIO is in the Disabled state
-                        Disabled = 0x0,
-                        ///  RADIO is in the RXRU state
-                        RxRu = 0x1,
-                        ///  RADIO is in the RXIDLE state
-                        RxIdle = 0x2,
-                        ///  RADIO is in the RX state
-                        Rx = 0x3,
-                        ///  RADIO is in the RXDISABLED state
-                        RxDisable = 0x4,
-                        ///  RADIO is in the TXRU state
-                        TxRu = 0x9,
-                        ///  RADIO is in the TXIDLE state
-                        TxIdle = 0xa,
-                        ///  RADIO is in the TX state
-                        Tx = 0xb,
-                        ///  RADIO is in the TXDISABLED state
-                        TxDisable = 0xc,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Data whitening initial value
-            DATAWHITEIV: mmio.Mmio(packed struct(u32) {
-                ///  Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.
-                DATAWHITEIV: u7,
-                padding: u25,
-            }),
-            reserved1376: [8]u8,
-            ///  Bit counter compare
-            BCC: mmio.Mmio(packed struct(u32) {
-                ///  Bit counter compare
-                BCC: u32,
-            }),
-            reserved1536: [156]u8,
-            ///  Description collection[0]: Device address base segment 0
-            DAB: [8]mmio.Mmio(packed struct(u32) {
-                ///  Device address base segment 0
-                DAB: u32,
-            }),
-            ///  Description collection[0]: Device address prefix 0
-            DAP: [8]mmio.Mmio(packed struct(u32) {
-                ///  Device address prefix 0
-                DAP: u16,
-                padding: u16,
-            }),
-            ///  Device address match configuration
-            DACNF: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable device address matching using device address 0
-                ENA0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 1
-                ENA1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 2
-                ENA2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 3
-                ENA3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 4
-                ENA4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 5
-                ENA5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 6
-                ENA6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 7
-                ENA7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  TxAdd for device address 0
-                TXADD0: u1,
-                ///  TxAdd for device address 1
-                TXADD1: u1,
-                ///  TxAdd for device address 2
-                TXADD2: u1,
-                ///  TxAdd for device address 3
-                TXADD3: u1,
-                ///  TxAdd for device address 4
-                TXADD4: u1,
-                ///  TxAdd for device address 5
-                TXADD5: u1,
-                ///  TxAdd for device address 6
-                TXADD6: u1,
-                ///  TxAdd for device address 7
-                TXADD7: u1,
-                padding: u16,
-            }),
-            reserved1616: [12]u8,
-            ///  Radio mode configuration register 0
-            MODECNF0: mmio.Mmio(packed struct(u32) {
-                ///  Radio ramp-up time
-                RU: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Default ramp-up time (tRXEN), compatible with firmware written for nRF51
-                        Default = 0x0,
-                        ///  Fast ramp-up (tRXEN,FAST), see electrical specification for more information
-                        Fast = 0x1,
-                    },
-                },
-                reserved8: u7,
-                ///  Default TX value
-                DTX: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Transmit '1'
-                        B1 = 0x0,
-                        ///  Transmit '0'
-                        B0 = 0x1,
-                        ///  Transmit center frequency
-                        Center = 0x2,
-                        _,
-                    },
-                },
-                padding: u22,
-            }),
-            reserved4092: [2472]u8,
-            ///  Peripheral power control
-            POWER: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.
-                POWER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Peripheral is powered off
-                        Disabled = 0x0,
-                        ///  Peripheral is powered on
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  UART with EasyDMA
-        pub const UARTE0 = extern struct {
-            ///  Start UART receiver
-            TASKS_STARTRX: u32,
-            ///  Stop UART receiver
-            TASKS_STOPRX: u32,
-            ///  Start UART transmitter
-            TASKS_STARTTX: u32,
-            ///  Stop UART transmitter
-            TASKS_STOPTX: u32,
-            reserved44: [28]u8,
-            ///  Flush RX FIFO into RX buffer
-            TASKS_FLUSHRX: u32,
-            reserved256: [208]u8,
-            ///  CTS is activated (set low). Clear To Send.
-            EVENTS_CTS: u32,
-            ///  CTS is deactivated (set high). Not Clear To Send.
-            EVENTS_NCTS: u32,
-            ///  Data received in RXD (but potentially not yet transferred to Data RAM)
-            EVENTS_RXDRDY: u32,
-            reserved272: [4]u8,
-            ///  Receive buffer is filled up
-            EVENTS_ENDRX: u32,
-            reserved284: [8]u8,
-            ///  Data sent from TXD
-            EVENTS_TXDRDY: u32,
-            ///  Last TX byte transmitted
-            EVENTS_ENDTX: u32,
-            ///  Error detected
-            EVENTS_ERROR: u32,
-            reserved324: [28]u8,
-            ///  Receiver timeout
-            EVENTS_RXTO: u32,
-            reserved332: [4]u8,
-            ///  UART receiver has started
-            EVENTS_RXSTARTED: u32,
-            ///  UART transmitter has started
-            EVENTS_TXSTARTED: u32,
-            reserved344: [4]u8,
-            ///  Transmitter stopped
-            EVENTS_TXSTOPPED: u32,
-            reserved512: [164]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved5: u5,
-                ///  Shortcut between ENDRX event and STARTRX task
-                ENDRX_STARTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between ENDRX event and STOPRX task
-                ENDRX_STOPRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u25,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for CTS event
-                CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for NCTS event
-                NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for RXDRDY event
-                RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u1,
-                ///  Enable or disable interrupt for ENDRX event
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u2,
-                ///  Enable or disable interrupt for TXDRDY event
-                TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for ENDTX event
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved17: u7,
-                ///  Enable or disable interrupt for RXTO event
-                RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u1,
-                ///  Enable or disable interrupt for RXSTARTED event
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TXSTARTED event
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved22: u1,
-                ///  Enable or disable interrupt for TXSTOPPED event
-                TXSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u9,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for CTS event
-                CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for NCTS event
-                NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for RXDRDY event
-                RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u1,
-                ///  Write '1' to Enable interrupt for ENDRX event
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u2,
-                ///  Write '1' to Enable interrupt for TXDRDY event
-                TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for ENDTX event
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved17: u7,
-                ///  Write '1' to Enable interrupt for RXTO event
-                RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u1,
-                ///  Write '1' to Enable interrupt for RXSTARTED event
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TXSTARTED event
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved22: u1,
-                ///  Write '1' to Enable interrupt for TXSTOPPED event
-                TXSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u9,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for CTS event
-                CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for NCTS event
-                NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for RXDRDY event
-                RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u1,
-                ///  Write '1' to Disable interrupt for ENDRX event
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u2,
-                ///  Write '1' to Disable interrupt for TXDRDY event
-                TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for ENDTX event
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved17: u7,
-                ///  Write '1' to Disable interrupt for RXTO event
-                RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u1,
-                ///  Write '1' to Disable interrupt for RXSTARTED event
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TXSTARTED event
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved22: u1,
-                ///  Write '1' to Disable interrupt for TXSTOPPED event
-                TXSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u9,
-            }),
-            reserved1152: [372]u8,
-            ///  Error source
-            ERRORSRC: mmio.Mmio(packed struct(u32) {
-                ///  Overrun error
-                OVERRUN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Parity error
-                PARITY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Framing error occurred
-                FRAMING: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Break condition
-                BREAK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1280: [124]u8,
-            ///  Enable UART
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable UARTE
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable UARTE
-                        Disabled = 0x0,
-                        ///  Enable UARTE
-                        Enabled = 0x8,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1316: [32]u8,
-            ///  Baud rate. Accuracy depends on the HFCLK source selected.
-            BAUDRATE: mmio.Mmio(packed struct(u32) {
-                ///  Baud rate
-                BAUDRATE: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  1200 baud (actual rate: 1205)
-                        Baud1200 = 0x4f000,
-                        ///  2400 baud (actual rate: 2396)
-                        Baud2400 = 0x9d000,
-                        ///  4800 baud (actual rate: 4808)
-                        Baud4800 = 0x13b000,
-                        ///  9600 baud (actual rate: 9598)
-                        Baud9600 = 0x275000,
-                        ///  14400 baud (actual rate: 14401)
-                        Baud14400 = 0x3af000,
-                        ///  19200 baud (actual rate: 19208)
-                        Baud19200 = 0x4ea000,
-                        ///  28800 baud (actual rate: 28777)
-                        Baud28800 = 0x75c000,
-                        ///  31250 baud
-                        Baud31250 = 0x800000,
-                        ///  38400 baud (actual rate: 38369)
-                        Baud38400 = 0x9d0000,
-                        ///  56000 baud (actual rate: 55944)
-                        Baud56000 = 0xe50000,
-                        ///  57600 baud (actual rate: 57554)
-                        Baud57600 = 0xeb0000,
-                        ///  76800 baud (actual rate: 76923)
-                        Baud76800 = 0x13a9000,
-                        ///  115200 baud (actual rate: 115108)
-                        Baud115200 = 0x1d60000,
-                        ///  230400 baud (actual rate: 231884)
-                        Baud230400 = 0x3b00000,
-                        ///  250000 baud
-                        Baud250000 = 0x4000000,
-                        ///  460800 baud (actual rate: 457143)
-                        Baud460800 = 0x7400000,
-                        ///  921600 baud (actual rate: 941176)
-                        Baud921600 = 0xf000000,
-                        ///  1Mega baud
-                        Baud1M = 0x10000000,
-                        _,
-                    },
-                },
-            }),
-            reserved1388: [68]u8,
-            ///  Configuration of parity and hardware flow control
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Hardware flow control
-                HWFC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Parity
-                PARITY: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Exclude parity bit
-                        Excluded = 0x0,
-                        ///  Include parity bit
-                        Included = 0x7,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-        };
-
-        ///  Universal Asynchronous Receiver/Transmitter
-        pub const UART0 = extern struct {
-            ///  Start UART receiver
-            TASKS_STARTRX: u32,
-            ///  Stop UART receiver
-            TASKS_STOPRX: u32,
-            ///  Start UART transmitter
-            TASKS_STARTTX: u32,
-            ///  Stop UART transmitter
-            TASKS_STOPTX: u32,
-            reserved28: [12]u8,
-            ///  Suspend UART
-            TASKS_SUSPEND: u32,
-            reserved256: [224]u8,
-            ///  CTS is activated (set low). Clear To Send.
-            EVENTS_CTS: u32,
-            ///  CTS is deactivated (set high). Not Clear To Send.
-            EVENTS_NCTS: u32,
-            ///  Data received in RXD
-            EVENTS_RXDRDY: u32,
-            reserved284: [16]u8,
-            ///  Data sent from TXD
-            EVENTS_TXDRDY: u32,
-            reserved292: [4]u8,
-            ///  Error detected
-            EVENTS_ERROR: u32,
-            reserved324: [28]u8,
-            ///  Receiver timeout
-            EVENTS_RXTO: u32,
-            reserved512: [184]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                ///  Shortcut between CTS event and STARTRX task
-                CTS_STARTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between NCTS event and STOPRX task
-                NCTS_STOPRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for CTS event
-                CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for NCTS event
-                NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for RXDRDY event
-                RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u4,
-                ///  Write '1' to Enable interrupt for TXDRDY event
-                TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u1,
-                ///  Write '1' to Enable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved17: u7,
-                ///  Write '1' to Enable interrupt for RXTO event
-                RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u14,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for CTS event
-                CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for NCTS event
-                NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for RXDRDY event
-                RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u4,
-                ///  Write '1' to Disable interrupt for TXDRDY event
-                TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u1,
-                ///  Write '1' to Disable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved17: u7,
-                ///  Write '1' to Disable interrupt for RXTO event
-                RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u14,
-            }),
-            reserved1152: [372]u8,
-            ///  Error source
-            ERRORSRC: mmio.Mmio(packed struct(u32) {
-                ///  Overrun error
-                OVERRUN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Parity error
-                PARITY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Framing error occurred
-                FRAMING: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Break condition
-                BREAK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1280: [124]u8,
-            ///  Enable UART
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable UART
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable UART
-                        Disabled = 0x0,
-                        ///  Enable UART
-                        Enabled = 0x4,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1288: [4]u8,
-            ///  Pin select for RTS
-            PSELRTS: mmio.Mmio(packed struct(u32) {
-                ///  Pin number configuration for UART RTS signal
-                PSELRTS: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  Disconnect
-                        Disconnected = 0xffffffff,
-                        _,
-                    },
-                },
-            }),
-            ///  Pin select for TXD
-            PSELTXD: mmio.Mmio(packed struct(u32) {
-                ///  Pin number configuration for UART TXD signal
-                PSELTXD: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  Disconnect
-                        Disconnected = 0xffffffff,
-                        _,
-                    },
-                },
-            }),
-            ///  Pin select for CTS
-            PSELCTS: mmio.Mmio(packed struct(u32) {
-                ///  Pin number configuration for UART CTS signal
-                PSELCTS: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  Disconnect
-                        Disconnected = 0xffffffff,
-                        _,
-                    },
-                },
-            }),
-            ///  Pin select for RXD
-            PSELRXD: mmio.Mmio(packed struct(u32) {
-                ///  Pin number configuration for UART RXD signal
-                PSELRXD: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  Disconnect
-                        Disconnected = 0xffffffff,
-                        _,
-                    },
-                },
-            }),
-            ///  RXD register
-            RXD: mmio.Mmio(packed struct(u32) {
-                ///  RX data received in previous transfers, double buffered
-                RXD: u8,
-                padding: u24,
-            }),
-            ///  TXD register
-            TXD: mmio.Mmio(packed struct(u32) {
-                ///  TX data to be transferred
-                TXD: u8,
-                padding: u24,
-            }),
-            reserved1316: [4]u8,
-            ///  Baud rate
-            BAUDRATE: mmio.Mmio(packed struct(u32) {
-                ///  Baud rate
-                BAUDRATE: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  1200 baud (actual rate: 1205)
-                        Baud1200 = 0x4f000,
-                        ///  2400 baud (actual rate: 2396)
-                        Baud2400 = 0x9d000,
-                        ///  4800 baud (actual rate: 4808)
-                        Baud4800 = 0x13b000,
-                        ///  9600 baud (actual rate: 9598)
-                        Baud9600 = 0x275000,
-                        ///  14400 baud (actual rate: 14414)
-                        Baud14400 = 0x3b0000,
-                        ///  19200 baud (actual rate: 19208)
-                        Baud19200 = 0x4ea000,
-                        ///  28800 baud (actual rate: 28829)
-                        Baud28800 = 0x75f000,
-                        ///  31250 baud
-                        Baud31250 = 0x800000,
-                        ///  38400 baud (actual rate: 38462)
-                        Baud38400 = 0x9d5000,
-                        ///  56000 baud (actual rate: 55944)
-                        Baud56000 = 0xe50000,
-                        ///  57600 baud (actual rate: 57762)
-                        Baud57600 = 0xebf000,
-                        ///  76800 baud (actual rate: 76923)
-                        Baud76800 = 0x13a9000,
-                        ///  115200 baud (actual rate: 115942)
-                        Baud115200 = 0x1d7e000,
-                        ///  230400 baud (actual rate: 231884)
-                        Baud230400 = 0x3afb000,
-                        ///  250000 baud
-                        Baud250000 = 0x4000000,
-                        ///  460800 baud (actual rate: 470588)
-                        Baud460800 = 0x75f7000,
-                        ///  921600 baud (actual rate: 941176)
-                        Baud921600 = 0xebed000,
-                        ///  1Mega baud
-                        Baud1M = 0x10000000,
-                        _,
-                    },
-                },
-            }),
-            reserved1388: [68]u8,
-            ///  Configuration of parity and hardware flow control
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Hardware flow control
-                HWFC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Parity
-                PARITY: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Exclude parity bit
-                        Excluded = 0x0,
-                        ///  Include parity bit
-                        Included = 0x7,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-        };
-
-        ///  Serial Peripheral Interface Master with EasyDMA 0
-        pub const SPIM0 = extern struct {
-            reserved16: [16]u8,
-            ///  Start SPI transaction
-            TASKS_START: u32,
-            ///  Stop SPI transaction
-            TASKS_STOP: u32,
-            reserved28: [4]u8,
-            ///  Suspend SPI transaction
-            TASKS_SUSPEND: u32,
-            ///  Resume SPI transaction
-            TASKS_RESUME: u32,
-            reserved260: [224]u8,
-            ///  SPI transaction has stopped
-            EVENTS_STOPPED: u32,
-            reserved272: [8]u8,
-            ///  End of RXD buffer reached
-            EVENTS_ENDRX: u32,
-            reserved280: [4]u8,
-            ///  End of RXD buffer and TXD buffer reached
-            EVENTS_END: u32,
-            reserved288: [4]u8,
-            ///  End of TXD buffer reached
-            EVENTS_ENDTX: u32,
-            reserved332: [40]u8,
-            ///  Transaction started
-            EVENTS_STARTED: u32,
-            reserved512: [176]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved17: u17,
-                ///  Shortcut between END event and START task
-                END_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u14,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Enable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u2,
-                ///  Write '1' to Enable interrupt for ENDRX event
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved6: u1,
-                ///  Write '1' to Enable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved8: u1,
-                ///  Write '1' to Enable interrupt for ENDTX event
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u10,
-                ///  Write '1' to Enable interrupt for STARTED event
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u2,
-                ///  Write '1' to Disable interrupt for ENDRX event
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved6: u1,
-                ///  Write '1' to Disable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved8: u1,
-                ///  Write '1' to Disable interrupt for ENDTX event
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u10,
-                ///  Write '1' to Disable interrupt for STARTED event
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            reserved1280: [500]u8,
-            ///  Enable SPIM
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable SPIM
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable SPIM
-                        Disabled = 0x0,
-                        ///  Enable SPIM
-                        Enabled = 0x7,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1316: [32]u8,
-            ///  SPI frequency. Accuracy depends on the HFCLK source selected.
-            FREQUENCY: mmio.Mmio(packed struct(u32) {
-                ///  SPI master data rate
-                FREQUENCY: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  125 kbps
-                        K125 = 0x2000000,
-                        ///  250 kbps
-                        K250 = 0x4000000,
-                        ///  500 kbps
-                        K500 = 0x8000000,
-                        ///  1 Mbps
-                        M1 = 0x10000000,
-                        ///  2 Mbps
-                        M2 = 0x20000000,
-                        ///  4 Mbps
-                        M4 = 0x40000000,
-                        ///  8 Mbps
-                        M8 = 0x80000000,
-                        _,
-                    },
-                },
-            }),
-            reserved1364: [44]u8,
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Bit order
-                ORDER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Most significant bit shifted out first
-                        MsbFirst = 0x0,
-                        ///  Least significant bit shifted out first
-                        LsbFirst = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) phase
-                CPHA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Sample on leading edge of clock, shift serial data on trailing edge
-                        Leading = 0x0,
-                        ///  Sample on trailing edge of clock, shift serial data on leading edge
-                        Trailing = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) polarity
-                CPOL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Active high
-                        ActiveHigh = 0x0,
-                        ///  Active low
-                        ActiveLow = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1472: [104]u8,
-            ///  Over-read character. Character clocked out in case and over-read of the TXD buffer.
-            ORC: mmio.Mmio(packed struct(u32) {
-                ///  Over-read character. Character clocked out in case and over-read of the TXD buffer.
-                ORC: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  SPI Slave 0
-        pub const SPIS0 = extern struct {
-            reserved36: [36]u8,
-            ///  Acquire SPI semaphore
-            TASKS_ACQUIRE: u32,
-            ///  Release SPI semaphore, enabling the SPI slave to acquire it
-            TASKS_RELEASE: u32,
-            reserved260: [216]u8,
-            ///  Granted transaction completed
-            EVENTS_END: u32,
-            reserved272: [8]u8,
-            ///  End of RXD buffer reached
-            EVENTS_ENDRX: u32,
-            reserved296: [20]u8,
-            ///  Semaphore acquired
-            EVENTS_ACQUIRED: u32,
-            reserved512: [212]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Shortcut between END event and ACQUIRE task
-                END_ACQUIRE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Enable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u2,
-                ///  Write '1' to Enable interrupt for ENDRX event
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u5,
-                ///  Write '1' to Enable interrupt for ACQUIRED event
-                ACQUIRED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u21,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Disable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u2,
-                ///  Write '1' to Disable interrupt for ENDRX event
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u5,
-                ///  Write '1' to Disable interrupt for ACQUIRED event
-                ACQUIRED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u21,
-            }),
-            reserved1024: [244]u8,
-            ///  Semaphore status register
-            SEMSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Semaphore status
-                SEMSTAT: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Semaphore is free
-                        Free = 0x0,
-                        ///  Semaphore is assigned to CPU
-                        CPU = 0x1,
-                        ///  Semaphore is assigned to SPI slave
-                        SPIS = 0x2,
-                        ///  Semaphore is assigned to SPI but a handover to the CPU is pending
-                        CPUPending = 0x3,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1088: [60]u8,
-            ///  Status from last transaction
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  TX buffer over-read detected, and prevented
-                OVERREAD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  RX buffer overflow detected, and prevented
-                OVERFLOW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1280: [188]u8,
-            ///  Enable SPI slave
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable SPI slave
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable SPI slave
-                        Disabled = 0x0,
-                        ///  Enable SPI slave
-                        Enabled = 0x2,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1364: [80]u8,
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Bit order
-                ORDER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Most significant bit shifted out first
-                        MsbFirst = 0x0,
-                        ///  Least significant bit shifted out first
-                        LsbFirst = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) phase
-                CPHA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Sample on leading edge of clock, shift serial data on trailing edge
-                        Leading = 0x0,
-                        ///  Sample on trailing edge of clock, shift serial data on leading edge
-                        Trailing = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) polarity
-                CPOL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Active high
-                        ActiveHigh = 0x0,
-                        ///  Active low
-                        ActiveLow = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1372: [4]u8,
-            ///  Default character. Character clocked out in case of an ignored transaction.
-            DEF: mmio.Mmio(packed struct(u32) {
-                ///  Default character. Character clocked out in case of an ignored transaction.
-                DEF: u8,
-                padding: u24,
-            }),
-            reserved1472: [96]u8,
-            ///  Over-read character
-            ORC: mmio.Mmio(packed struct(u32) {
-                ///  Over-read character. Character clocked out after an over-read of the transmit buffer.
-                ORC: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  I2C compatible Two-Wire Master Interface with EasyDMA 0
-        pub const TWIM0 = extern struct {
-            ///  Start TWI receive sequence
-            TASKS_STARTRX: u32,
-            reserved8: [4]u8,
-            ///  Start TWI transmit sequence
-            TASKS_STARTTX: u32,
-            reserved20: [8]u8,
-            ///  Stop TWI transaction. Must be issued while the TWI master is not suspended.
-            TASKS_STOP: u32,
-            reserved28: [4]u8,
-            ///  Suspend TWI transaction
-            TASKS_SUSPEND: u32,
-            ///  Resume TWI transaction
-            TASKS_RESUME: u32,
-            reserved260: [224]u8,
-            ///  TWI stopped
-            EVENTS_STOPPED: u32,
-            reserved292: [28]u8,
-            ///  TWI error
-            EVENTS_ERROR: u32,
-            reserved328: [32]u8,
-            ///  Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
-            EVENTS_SUSPENDED: u32,
-            ///  Receive sequence started
-            EVENTS_RXSTARTED: u32,
-            ///  Transmit sequence started
-            EVENTS_TXSTARTED: u32,
-            reserved348: [8]u8,
-            ///  Byte boundary, starting to receive the last byte
-            EVENTS_LASTRX: u32,
-            ///  Byte boundary, starting to transmit the last byte
-            EVENTS_LASTTX: u32,
-            reserved512: [156]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved7: u7,
-                ///  Shortcut between LASTTX event and STARTRX task
-                LASTTX_STARTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between LASTTX event and SUSPEND task
-                LASTTX_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between LASTTX event and STOP task
-                LASTTX_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between LASTRX event and STARTTX task
-                LASTRX_STARTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                reserved12: u1,
-                ///  Shortcut between LASTRX event and STOP task
-                LASTRX_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u19,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Enable or disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Enable or disable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u8,
-                ///  Enable or disable interrupt for SUSPENDED event
-                SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for RXSTARTED event
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TXSTARTED event
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved23: u2,
-                ///  Enable or disable interrupt for LASTRX event
-                LASTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for LASTTX event
-                LASTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Enable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Write '1' to Enable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u8,
-                ///  Write '1' to Enable interrupt for SUSPENDED event
-                SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for RXSTARTED event
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TXSTARTED event
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved23: u2,
-                ///  Write '1' to Enable interrupt for LASTRX event
-                LASTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for LASTTX event
-                LASTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Write '1' to Disable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u8,
-                ///  Write '1' to Disable interrupt for SUSPENDED event
-                SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for RXSTARTED event
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TXSTARTED event
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved23: u2,
-                ///  Write '1' to Disable interrupt for LASTRX event
-                LASTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for LASTTX event
-                LASTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            reserved1220: [440]u8,
-            ///  Error source
-            ERRORSRC: mmio.Mmio(packed struct(u32) {
-                ///  Overrun error
-                OVERRUN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotReceived = 0x0,
-                        ///  Error occurred
-                        Received = 0x1,
-                    },
-                },
-                ///  NACK received after sending the address (write '1' to clear)
-                ANACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotReceived = 0x0,
-                        ///  Error occurred
-                        Received = 0x1,
-                    },
-                },
-                ///  NACK received after sending a data byte (write '1' to clear)
-                DNACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotReceived = 0x0,
-                        ///  Error occurred
-                        Received = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1280: [56]u8,
-            ///  Enable TWIM
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable TWIM
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable TWIM
-                        Disabled = 0x0,
-                        ///  Enable TWIM
-                        Enabled = 0x6,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1316: [32]u8,
-            ///  TWI frequency
-            FREQUENCY: mmio.Mmio(packed struct(u32) {
-                ///  TWI master clock frequency
-                FREQUENCY: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  100 kbps
-                        K100 = 0x1980000,
-                        ///  250 kbps
-                        K250 = 0x4000000,
-                        ///  400 kbps
-                        K400 = 0x6400000,
-                        _,
-                    },
-                },
-            }),
-            reserved1416: [96]u8,
-            ///  Address used in the TWI transfer
-            ADDRESS: mmio.Mmio(packed struct(u32) {
-                ///  Address used in the TWI transfer
-                ADDRESS: u7,
-                padding: u25,
-            }),
-        };
-
-        ///  I2C compatible Two-Wire Slave Interface with EasyDMA 0
-        pub const TWIS0 = extern struct {
-            reserved20: [20]u8,
-            ///  Stop TWI transaction
-            TASKS_STOP: u32,
-            reserved28: [4]u8,
-            ///  Suspend TWI transaction
-            TASKS_SUSPEND: u32,
-            ///  Resume TWI transaction
-            TASKS_RESUME: u32,
-            reserved48: [12]u8,
-            ///  Prepare the TWI slave to respond to a write command
-            TASKS_PREPARERX: u32,
-            ///  Prepare the TWI slave to respond to a read command
-            TASKS_PREPARETX: u32,
-            reserved260: [204]u8,
-            ///  TWI stopped
-            EVENTS_STOPPED: u32,
-            reserved292: [28]u8,
-            ///  TWI error
-            EVENTS_ERROR: u32,
-            reserved332: [36]u8,
-            ///  Receive sequence started
-            EVENTS_RXSTARTED: u32,
-            ///  Transmit sequence started
-            EVENTS_TXSTARTED: u32,
-            reserved356: [16]u8,
-            ///  Write command received
-            EVENTS_WRITE: u32,
-            ///  Read command received
-            EVENTS_READ: u32,
-            reserved512: [148]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved13: u13,
-                ///  Shortcut between WRITE event and SUSPEND task
-                WRITE_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between READ event and SUSPEND task
-                READ_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u17,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Enable or disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Enable or disable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u9,
-                ///  Enable or disable interrupt for RXSTARTED event
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TXSTARTED event
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved25: u4,
-                ///  Enable or disable interrupt for WRITE event
-                WRITE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for READ event
-                READ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u5,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Enable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Write '1' to Enable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u9,
-                ///  Write '1' to Enable interrupt for RXSTARTED event
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TXSTARTED event
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved25: u4,
-                ///  Write '1' to Enable interrupt for WRITE event
-                WRITE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for READ event
-                READ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u5,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Write '1' to Disable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u9,
-                ///  Write '1' to Disable interrupt for RXSTARTED event
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TXSTARTED event
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved25: u4,
-                ///  Write '1' to Disable interrupt for WRITE event
-                WRITE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for READ event
-                READ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u5,
-            }),
-            reserved1232: [452]u8,
-            ///  Error source
-            ERRORSRC: mmio.Mmio(packed struct(u32) {
-                ///  RX buffer overflow detected, and prevented
-                OVERFLOW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotDetected = 0x0,
-                        ///  Error occurred
-                        Detected = 0x1,
-                    },
-                },
-                reserved2: u1,
-                ///  NACK sent after receiving a data byte
-                DNACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotReceived = 0x0,
-                        ///  Error occurred
-                        Received = 0x1,
-                    },
-                },
-                ///  TX buffer over-read detected, and prevented
-                OVERREAD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotDetected = 0x0,
-                        ///  Error occurred
-                        Detected = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Status register indicating which address had a match
-            MATCH: mmio.Mmio(packed struct(u32) {
-                ///  Which of the addresses in {ADDRESS} matched the incoming address
-                MATCH: u1,
-                padding: u31,
-            }),
-            reserved1280: [40]u8,
-            ///  Enable TWIS
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable TWIS
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable TWIS
-                        Disabled = 0x0,
-                        ///  Enable TWIS
-                        Enabled = 0x9,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1416: [132]u8,
-            ///  Description collection[0]: TWI slave address 0
-            ADDRESS: [2]mmio.Mmio(packed struct(u32) {
-                ///  TWI slave address
-                ADDRESS: u7,
-                padding: u25,
-            }),
-            reserved1428: [4]u8,
-            ///  Configuration register for the address match mechanism
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable address matching on ADDRESS[0]
-                ADDRESS0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable address matching on ADDRESS[1]
-                ADDRESS1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1472: [40]u8,
-            ///  Over-read character. Character sent out in case of an over-read of the transmit buffer.
-            ORC: mmio.Mmio(packed struct(u32) {
-                ///  Over-read character. Character sent out in case of an over-read of the transmit buffer.
-                ORC: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  Serial Peripheral Interface 0
-        pub const SPI0 = extern struct {
-            reserved264: [264]u8,
-            ///  TXD byte sent and RXD byte received
-            EVENTS_READY: u32,
-            reserved772: [504]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Write '1' to Enable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Write '1' to Disable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1280: [500]u8,
-            ///  Enable SPI
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable SPI
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable SPI
-                        Disabled = 0x0,
-                        ///  Enable SPI
-                        Enabled = 0x1,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1304: [20]u8,
-            ///  RXD register
-            RXD: mmio.Mmio(packed struct(u32) {
-                ///  RX data received. Double buffered
-                RXD: u8,
-                padding: u24,
-            }),
-            ///  TXD register
-            TXD: mmio.Mmio(packed struct(u32) {
-                ///  TX data to send. Double buffered
-                TXD: u8,
-                padding: u24,
-            }),
-            reserved1316: [4]u8,
-            ///  SPI frequency
-            FREQUENCY: mmio.Mmio(packed struct(u32) {
-                ///  SPI master data rate
-                FREQUENCY: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  125 kbps
-                        K125 = 0x2000000,
-                        ///  250 kbps
-                        K250 = 0x4000000,
-                        ///  500 kbps
-                        K500 = 0x8000000,
-                        ///  1 Mbps
-                        M1 = 0x10000000,
-                        ///  2 Mbps
-                        M2 = 0x20000000,
-                        ///  4 Mbps
-                        M4 = 0x40000000,
-                        ///  8 Mbps
-                        M8 = 0x80000000,
-                        _,
-                    },
-                },
-            }),
-            reserved1364: [44]u8,
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Bit order
-                ORDER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Most significant bit shifted out first
-                        MsbFirst = 0x0,
-                        ///  Least significant bit shifted out first
-                        LsbFirst = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) phase
-                CPHA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Sample on leading edge of clock, shift serial data on trailing edge
-                        Leading = 0x0,
-                        ///  Sample on trailing edge of clock, shift serial data on leading edge
-                        Trailing = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) polarity
-                CPOL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Active high
-                        ActiveHigh = 0x0,
-                        ///  Active low
-                        ActiveLow = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-        };
-
-        ///  I2C compatible Two-Wire Interface 0
-        pub const TWI0 = extern struct {
-            ///  Start TWI receive sequence
-            TASKS_STARTRX: u32,
-            reserved8: [4]u8,
-            ///  Start TWI transmit sequence
-            TASKS_STARTTX: u32,
-            reserved20: [8]u8,
-            ///  Stop TWI transaction
-            TASKS_STOP: u32,
-            reserved28: [4]u8,
-            ///  Suspend TWI transaction
-            TASKS_SUSPEND: u32,
-            ///  Resume TWI transaction
-            TASKS_RESUME: u32,
-            reserved260: [224]u8,
-            ///  TWI stopped
-            EVENTS_STOPPED: u32,
-            ///  TWI RXD byte received
-            EVENTS_RXDREADY: u32,
-            reserved284: [16]u8,
-            ///  TWI TXD byte sent
-            EVENTS_TXDSENT: u32,
-            reserved292: [4]u8,
-            ///  TWI error
-            EVENTS_ERROR: u32,
-            reserved312: [16]u8,
-            ///  TWI byte boundary, generated before each byte that is sent or received
-            EVENTS_BB: u32,
-            reserved328: [12]u8,
-            ///  TWI entered the suspended state
-            EVENTS_SUSPENDED: u32,
-            reserved512: [180]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between BB event and SUSPEND task
-                BB_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between BB event and STOP task
-                BB_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Enable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for RXDREADY event
-                RXDREADY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u4,
-                ///  Write '1' to Enable interrupt for TXDSENT event
-                TXDSENT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u1,
-                ///  Write '1' to Enable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved14: u4,
-                ///  Write '1' to Enable interrupt for BB event
-                BB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u3,
-                ///  Write '1' to Enable interrupt for SUSPENDED event
-                SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u13,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for RXDREADY event
-                RXDREADY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u4,
-                ///  Write '1' to Disable interrupt for TXDSENT event
-                TXDSENT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u1,
-                ///  Write '1' to Disable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved14: u4,
-                ///  Write '1' to Disable interrupt for BB event
-                BB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u3,
-                ///  Write '1' to Disable interrupt for SUSPENDED event
-                SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u13,
-            }),
-            reserved1220: [440]u8,
-            ///  Error source
-            ERRORSRC: mmio.Mmio(packed struct(u32) {
-                ///  Overrun error
-                OVERRUN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: no overrun occured
-                        NotPresent = 0x0,
-                        ///  Read: overrun occured
-                        Present = 0x1,
-                    },
-                },
-                ///  NACK received after sending the address (write '1' to clear)
-                ANACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  NACK received after sending a data byte (write '1' to clear)
-                DNACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1280: [56]u8,
-            ///  Enable TWI
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable TWI
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable TWI
-                        Disabled = 0x0,
-                        ///  Enable TWI
-                        Enabled = 0x5,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1288: [4]u8,
-            ///  Pin select for SCL
-            PSELSCL: mmio.Mmio(packed struct(u32) {
-                ///  Pin number configuration for TWI SCL signal
-                PSELSCL: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  Disconnect
-                        Disconnected = 0xffffffff,
-                        _,
-                    },
-                },
-            }),
-            ///  Pin select for SDA
-            PSELSDA: mmio.Mmio(packed struct(u32) {
-                ///  Pin number configuration for TWI SDA signal
-                PSELSDA: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  Disconnect
-                        Disconnected = 0xffffffff,
-                        _,
-                    },
-                },
-            }),
-            reserved1304: [8]u8,
-            ///  RXD register
-            RXD: mmio.Mmio(packed struct(u32) {
-                ///  RXD register
-                RXD: u8,
-                padding: u24,
-            }),
-            ///  TXD register
-            TXD: mmio.Mmio(packed struct(u32) {
-                ///  TXD register
-                TXD: u8,
-                padding: u24,
-            }),
-            reserved1316: [4]u8,
-            ///  TWI frequency
-            FREQUENCY: mmio.Mmio(packed struct(u32) {
-                ///  TWI master clock frequency
-                FREQUENCY: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  100 kbps
-                        K100 = 0x1980000,
-                        ///  250 kbps
-                        K250 = 0x4000000,
-                        ///  400 kbps (actual rate 410.256 kbps)
-                        K400 = 0x6680000,
-                        _,
-                    },
-                },
-            }),
-            reserved1416: [96]u8,
-            ///  Address used in the TWI transfer
-            ADDRESS: mmio.Mmio(packed struct(u32) {
-                ///  Address used in the TWI transfer
-                ADDRESS: u7,
-                padding: u25,
-            }),
-        };
-
-        ///  GPIO Port 1
-        pub const P0 = extern struct {
-            reserved1284: [1284]u8,
-            ///  Write GPIO port
-            OUT: mmio.Mmio(packed struct(u32) {
-                ///  Pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-            }),
-            ///  Set individual bits in GPIO port
-            OUTSET: mmio.Mmio(packed struct(u32) {
-                ///  Pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-            }),
-            ///  Clear individual bits in GPIO port
-            OUTCLR: mmio.Mmio(packed struct(u32) {
-                ///  Pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-            }),
-            ///  Read GPIO port
-            IN: mmio.Mmio(packed struct(u32) {
-                ///  Pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-            }),
-            ///  Direction of GPIO pins
-            DIR: mmio.Mmio(packed struct(u32) {
-                ///  Pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-            }),
-            ///  DIR set register
-            DIRSET: mmio.Mmio(packed struct(u32) {
-                ///  Set as output pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-            }),
-            ///  DIR clear register
-            DIRCLR: mmio.Mmio(packed struct(u32) {
-                ///  Set as input pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-            }),
-            ///  Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers
-            LATCH: mmio.Mmio(packed struct(u32) {
-                ///  Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-            }),
-            ///  Select between default DETECT signal behaviour and LDETECT mode
-            DETECTMODE: mmio.Mmio(packed struct(u32) {
-                ///  Select between default DETECT signal behaviour and LDETECT mode
-                DETECTMODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  DETECT directly connected to PIN DETECT signals
-                        Default = 0x0,
-                        ///  Use the latched LDETECT behaviour
-                        LDETECT = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1792: [472]u8,
-            ///  Description collection[0]: Configuration of GPIO pins
-            PIN_CNF: [32]mmio.Mmio(packed struct(u32) {
-                ///  Pin direction. Same physical register as DIR register
-                DIR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Configure pin as an input pin
-                        Input = 0x0,
-                        ///  Configure pin as an output pin
-                        Output = 0x1,
-                    },
-                },
-                ///  Connect or disconnect input buffer
-                INPUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Connect input buffer
-                        Connect = 0x0,
-                        ///  Disconnect input buffer
-                        Disconnect = 0x1,
-                    },
-                },
-                ///  Pull configuration
-                PULL: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  No pull
-                        Disabled = 0x0,
-                        ///  Pull down on pin
-                        Pulldown = 0x1,
-                        ///  Pull up on pin
-                        Pullup = 0x3,
-                        _,
-                    },
-                },
-                reserved8: u4,
-                ///  Drive configuration
-                DRIVE: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Standard '0', standard '1'
-                        S0S1 = 0x0,
-                        ///  High drive '0', standard '1'
-                        H0S1 = 0x1,
-                        ///  Standard '0', high drive '1'
-                        S0H1 = 0x2,
-                        ///  High drive '0', high 'drive '1''
-                        H0H1 = 0x3,
-                        ///  Disconnect '0' standard '1' (normally used for wired-or connections)
-                        D0S1 = 0x4,
-                        ///  Disconnect '0', high drive '1' (normally used for wired-or connections)
-                        D0H1 = 0x5,
-                        ///  Standard '0'. disconnect '1' (normally used for wired-and connections)
-                        S0D1 = 0x6,
-                        ///  High drive '0', disconnect '1' (normally used for wired-and connections)
-                        H0D1 = 0x7,
-                    },
-                },
-                reserved16: u5,
-                ///  Pin sensing mechanism
-                SENSE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Sense for high level
-                        High = 0x2,
-                        ///  Sense for low level
-                        Low = 0x3,
-                        _,
-                    },
-                },
-                padding: u14,
-            }),
-        };
-
-        ///  FPU
-        pub const FPU = extern struct {
-            ///  Unused.
-            UNUSED: u32,
-        };
-
-        ///  Inter-IC Sound
-        pub const I2S = extern struct {
-            ///  Starts continuous I2S transfer. Also starts MCK generator when this is enabled.
-            TASKS_START: u32,
-            ///  Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the {event:STOPPED} event to be generated.
-            TASKS_STOP: u32,
-            reserved260: [252]u8,
-            ///  The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.
-            EVENTS_RXPTRUPD: u32,
-            ///  I2S transfer stopped.
-            EVENTS_STOPPED: u32,
-            reserved276: [8]u8,
-            ///  The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
-            EVENTS_TXPTRUPD: u32,
-            reserved768: [488]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Enable or disable interrupt for RXPTRUPD event
-                RXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved5: u2,
-                ///  Enable or disable interrupt for TXPTRUPD event
-                TXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u26,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Enable interrupt for RXPTRUPD event
-                RXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved5: u2,
-                ///  Write '1' to Enable interrupt for TXPTRUPD event
-                TXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u26,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Disable interrupt for RXPTRUPD event
-                RXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved5: u2,
-                ///  Write '1' to Disable interrupt for TXPTRUPD event
-                TXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u26,
-            }),
-            reserved1280: [500]u8,
-            ///  Enable I2S module.
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable I2S module.
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  Event Generator Unit 0
-        pub const EGU0 = extern struct {
-            ///  Description collection[0]: Trigger 0 for triggering the corresponding TRIGGERED[0] event
-            TASKS_TRIGGER: [16]u32,
-            reserved256: [192]u8,
-            ///  Description collection[0]: Event number 0 generated by triggering the corresponding TRIGGER[0] task
-            EVENTS_TRIGGERED: [16]u32,
-            reserved768: [448]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for TRIGGERED[0] event
-                TRIGGERED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[1] event
-                TRIGGERED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[2] event
-                TRIGGERED2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[3] event
-                TRIGGERED3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[4] event
-                TRIGGERED4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[5] event
-                TRIGGERED5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[6] event
-                TRIGGERED6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[7] event
-                TRIGGERED7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[8] event
-                TRIGGERED8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[9] event
-                TRIGGERED9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[10] event
-                TRIGGERED10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[11] event
-                TRIGGERED11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[12] event
-                TRIGGERED12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[13] event
-                TRIGGERED13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[14] event
-                TRIGGERED14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TRIGGERED[15] event
-                TRIGGERED15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u16,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for TRIGGERED[0] event
-                TRIGGERED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[1] event
-                TRIGGERED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[2] event
-                TRIGGERED2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[3] event
-                TRIGGERED3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[4] event
-                TRIGGERED4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[5] event
-                TRIGGERED5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[6] event
-                TRIGGERED6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[7] event
-                TRIGGERED7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[8] event
-                TRIGGERED8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[9] event
-                TRIGGERED9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[10] event
-                TRIGGERED10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[11] event
-                TRIGGERED11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[12] event
-                TRIGGERED12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[13] event
-                TRIGGERED13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[14] event
-                TRIGGERED14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TRIGGERED[15] event
-                TRIGGERED15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u16,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for TRIGGERED[0] event
-                TRIGGERED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[1] event
-                TRIGGERED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[2] event
-                TRIGGERED2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[3] event
-                TRIGGERED3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[4] event
-                TRIGGERED4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[5] event
-                TRIGGERED5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[6] event
-                TRIGGERED6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[7] event
-                TRIGGERED7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[8] event
-                TRIGGERED8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[9] event
-                TRIGGERED9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[10] event
-                TRIGGERED10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[11] event
-                TRIGGERED11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[12] event
-                TRIGGERED12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[13] event
-                TRIGGERED13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[14] event
-                TRIGGERED14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TRIGGERED[15] event
-                TRIGGERED15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u16,
-            }),
-        };
-
-        ///  Memory Watch Unit
-        pub const MWU = extern struct {
-            reserved768: [768]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for REGION[0].WA event
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for REGION[0].RA event
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for REGION[1].WA event
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for REGION[1].RA event
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for REGION[2].WA event
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for REGION[2].RA event
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for REGION[3].WA event
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for REGION[3].RA event
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Enable or disable interrupt for PREGION[0].WA event
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for PREGION[0].RA event
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for PREGION[1].WA event
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for PREGION[1].RA event
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for REGION[0].WA event
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for REGION[0].RA event
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for REGION[1].WA event
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for REGION[1].RA event
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for REGION[2].WA event
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for REGION[2].RA event
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for REGION[3].WA event
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for REGION[3].RA event
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Write '1' to Enable interrupt for PREGION[0].WA event
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for PREGION[0].RA event
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for PREGION[1].WA event
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for PREGION[1].RA event
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for REGION[0].WA event
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for REGION[0].RA event
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for REGION[1].WA event
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for REGION[1].RA event
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for REGION[2].WA event
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for REGION[2].RA event
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for REGION[3].WA event
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for REGION[3].RA event
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Write '1' to Disable interrupt for PREGION[0].WA event
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for PREGION[0].RA event
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for PREGION[1].WA event
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for PREGION[1].RA event
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            reserved800: [20]u8,
-            ///  Enable or disable non-maskable interrupt
-            NMIEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable non-maskable interrupt for REGION[0].WA event
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable non-maskable interrupt for REGION[0].RA event
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable non-maskable interrupt for REGION[1].WA event
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable non-maskable interrupt for REGION[1].RA event
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable non-maskable interrupt for REGION[2].WA event
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable non-maskable interrupt for REGION[2].RA event
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable non-maskable interrupt for REGION[3].WA event
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable non-maskable interrupt for REGION[3].RA event
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Enable or disable non-maskable interrupt for PREGION[0].WA event
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable non-maskable interrupt for PREGION[0].RA event
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable non-maskable interrupt for PREGION[1].WA event
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable non-maskable interrupt for PREGION[1].RA event
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Enable non-maskable interrupt
-            NMIENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable non-maskable interrupt for REGION[0].WA event
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable non-maskable interrupt for REGION[0].RA event
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable non-maskable interrupt for REGION[1].WA event
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable non-maskable interrupt for REGION[1].RA event
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable non-maskable interrupt for REGION[2].WA event
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable non-maskable interrupt for REGION[2].RA event
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable non-maskable interrupt for REGION[3].WA event
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable non-maskable interrupt for REGION[3].RA event
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Write '1' to Enable non-maskable interrupt for PREGION[0].WA event
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable non-maskable interrupt for PREGION[0].RA event
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable non-maskable interrupt for PREGION[1].WA event
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable non-maskable interrupt for PREGION[1].RA event
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Disable non-maskable interrupt
-            NMIENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable non-maskable interrupt for REGION[0].WA event
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable non-maskable interrupt for REGION[0].RA event
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable non-maskable interrupt for REGION[1].WA event
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable non-maskable interrupt for REGION[1].RA event
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable non-maskable interrupt for REGION[2].WA event
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable non-maskable interrupt for REGION[2].RA event
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable non-maskable interrupt for REGION[3].WA event
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable non-maskable interrupt for REGION[3].RA event
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Write '1' to Disable non-maskable interrupt for PREGION[0].WA event
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable non-maskable interrupt for PREGION[0].RA event
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable non-maskable interrupt for PREGION[1].WA event
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable non-maskable interrupt for PREGION[1].RA event
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            reserved1296: [484]u8,
-            ///  Enable/disable regions watch
-            REGIONEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable/disable write access watch in region[0]
-                RGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this region
-                        Disable = 0x0,
-                        ///  Enable write access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in region[0]
-                RGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this region
-                        Disable = 0x0,
-                        ///  Enable read access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable write access watch in region[1]
-                RGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this region
-                        Disable = 0x0,
-                        ///  Enable write access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in region[1]
-                RGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this region
-                        Disable = 0x0,
-                        ///  Enable read access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable write access watch in region[2]
-                RGN2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this region
-                        Disable = 0x0,
-                        ///  Enable write access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in region[2]
-                RGN2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this region
-                        Disable = 0x0,
-                        ///  Enable read access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable write access watch in region[3]
-                RGN3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this region
-                        Disable = 0x0,
-                        ///  Enable write access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in region[3]
-                RGN3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this region
-                        Disable = 0x0,
-                        ///  Enable read access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Enable/disable write access watch in PREGION[0]
-                PRGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this PREGION
-                        Disable = 0x0,
-                        ///  Enable write access watch in this PREGION
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in PREGION[0]
-                PRGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this PREGION
-                        Disable = 0x0,
-                        ///  Enable read access watch in this PREGION
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable write access watch in PREGION[1]
-                PRGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this PREGION
-                        Disable = 0x0,
-                        ///  Enable write access watch in this PREGION
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in PREGION[1]
-                PRGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this PREGION
-                        Disable = 0x0,
-                        ///  Enable read access watch in this PREGION
-                        Enable = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Enable regions watch
-            REGIONENSET: mmio.Mmio(packed struct(u32) {
-                ///  Enable write access watch in region[0]
-                RGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in region[0]
-                RGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable write access watch in region[1]
-                RGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in region[1]
-                RGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable write access watch in region[2]
-                RGN2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in region[2]
-                RGN2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable write access watch in region[3]
-                RGN3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in region[3]
-                RGN3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Enable write access watch in PREGION[0]
-                PRGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in PREGION[0]
-                PRGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable write access watch in PREGION[1]
-                PRGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in PREGION[1]
-                PRGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Disable regions watch
-            REGIONENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Disable write access watch in region[0]
-                RGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in region[0]
-                RGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable write access watch in region[1]
-                RGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in region[1]
-                RGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable write access watch in region[2]
-                RGN2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in region[2]
-                RGN2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable write access watch in region[3]
-                RGN3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in region[3]
-                RGN3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Disable write access watch in PREGION[0]
-                PRGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in PREGION[0]
-                PRGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable write access watch in PREGION[1]
-                PRGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in PREGION[1]
-                PRGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-        };
-
-        ///  Programmable Peripheral Interconnect
-        pub const PPI = extern struct {
-            reserved1280: [1280]u8,
-            ///  Channel enable register
-            CHEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable channel 0
-                CH0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 1
-                CH1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 2
-                CH2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 3
-                CH3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 4
-                CH4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 5
-                CH5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 6
-                CH6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 7
-                CH7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 8
-                CH8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 9
-                CH9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 10
-                CH10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 11
-                CH11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 12
-                CH12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 13
-                CH13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 14
-                CH14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 15
-                CH15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 16
-                CH16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 17
-                CH17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 18
-                CH18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 19
-                CH19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 20
-                CH20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 21
-                CH21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 22
-                CH22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 23
-                CH23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 24
-                CH24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 25
-                CH25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 26
-                CH26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 27
-                CH27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 28
-                CH28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 29
-                CH29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 30
-                CH30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 31
-                CH31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            ///  Channel enable set register
-            CHENSET: mmio.Mmio(packed struct(u32) {
-                ///  Channel 0 enable set register. Writing '0' has no effect
-                CH0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 1 enable set register. Writing '0' has no effect
-                CH1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 2 enable set register. Writing '0' has no effect
-                CH2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 3 enable set register. Writing '0' has no effect
-                CH3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 4 enable set register. Writing '0' has no effect
-                CH4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 5 enable set register. Writing '0' has no effect
-                CH5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 6 enable set register. Writing '0' has no effect
-                CH6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 7 enable set register. Writing '0' has no effect
-                CH7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 8 enable set register. Writing '0' has no effect
-                CH8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 9 enable set register. Writing '0' has no effect
-                CH9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 10 enable set register. Writing '0' has no effect
-                CH10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 11 enable set register. Writing '0' has no effect
-                CH11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 12 enable set register. Writing '0' has no effect
-                CH12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 13 enable set register. Writing '0' has no effect
-                CH13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 14 enable set register. Writing '0' has no effect
-                CH14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 15 enable set register. Writing '0' has no effect
-                CH15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 16 enable set register. Writing '0' has no effect
-                CH16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 17 enable set register. Writing '0' has no effect
-                CH17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 18 enable set register. Writing '0' has no effect
-                CH18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 19 enable set register. Writing '0' has no effect
-                CH19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 20 enable set register. Writing '0' has no effect
-                CH20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 21 enable set register. Writing '0' has no effect
-                CH21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 22 enable set register. Writing '0' has no effect
-                CH22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 23 enable set register. Writing '0' has no effect
-                CH23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 24 enable set register. Writing '0' has no effect
-                CH24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 25 enable set register. Writing '0' has no effect
-                CH25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 26 enable set register. Writing '0' has no effect
-                CH26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 27 enable set register. Writing '0' has no effect
-                CH27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 28 enable set register. Writing '0' has no effect
-                CH28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 29 enable set register. Writing '0' has no effect
-                CH29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 30 enable set register. Writing '0' has no effect
-                CH30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 31 enable set register. Writing '0' has no effect
-                CH31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            ///  Channel enable clear register
-            CHENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Channel 0 enable clear register. Writing '0' has no effect
-                CH0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 1 enable clear register. Writing '0' has no effect
-                CH1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 2 enable clear register. Writing '0' has no effect
-                CH2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 3 enable clear register. Writing '0' has no effect
-                CH3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 4 enable clear register. Writing '0' has no effect
-                CH4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 5 enable clear register. Writing '0' has no effect
-                CH5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 6 enable clear register. Writing '0' has no effect
-                CH6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 7 enable clear register. Writing '0' has no effect
-                CH7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 8 enable clear register. Writing '0' has no effect
-                CH8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 9 enable clear register. Writing '0' has no effect
-                CH9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 10 enable clear register. Writing '0' has no effect
-                CH10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 11 enable clear register. Writing '0' has no effect
-                CH11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 12 enable clear register. Writing '0' has no effect
-                CH12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 13 enable clear register. Writing '0' has no effect
-                CH13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 14 enable clear register. Writing '0' has no effect
-                CH14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 15 enable clear register. Writing '0' has no effect
-                CH15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 16 enable clear register. Writing '0' has no effect
-                CH16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 17 enable clear register. Writing '0' has no effect
-                CH17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 18 enable clear register. Writing '0' has no effect
-                CH18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 19 enable clear register. Writing '0' has no effect
-                CH19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 20 enable clear register. Writing '0' has no effect
-                CH20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 21 enable clear register. Writing '0' has no effect
-                CH21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 22 enable clear register. Writing '0' has no effect
-                CH22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 23 enable clear register. Writing '0' has no effect
-                CH23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 24 enable clear register. Writing '0' has no effect
-                CH24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 25 enable clear register. Writing '0' has no effect
-                CH25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 26 enable clear register. Writing '0' has no effect
-                CH26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 27 enable clear register. Writing '0' has no effect
-                CH27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 28 enable clear register. Writing '0' has no effect
-                CH28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 29 enable clear register. Writing '0' has no effect
-                CH29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 30 enable clear register. Writing '0' has no effect
-                CH30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 31 enable clear register. Writing '0' has no effect
-                CH31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            reserved2048: [756]u8,
-            ///  Description collection[0]: Channel group 0
-            CHG: [6]mmio.Mmio(packed struct(u32) {
-                ///  Include or exclude channel 0
-                CH0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 1
-                CH1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 2
-                CH2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 3
-                CH3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 4
-                CH4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 5
-                CH5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 6
-                CH6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 7
-                CH7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 8
-                CH8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 9
-                CH9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 10
-                CH10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 11
-                CH11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 12
-                CH12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 13
-                CH13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 14
-                CH14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 15
-                CH15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 16
-                CH16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 17
-                CH17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 18
-                CH18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 19
-                CH19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 20
-                CH20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 21
-                CH21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 22
-                CH22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 23
-                CH23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 24
-                CH24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 25
-                CH25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 26
-                CH26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 27
-                CH27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 28
-                CH28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 29
-                CH29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 30
-                CH30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 31
-                CH31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-            }),
-        };
-
-        ///  NFC-A compatible radio
-        pub const NFCT = extern struct {
-            ///  Activate NFC peripheral for incoming and outgoing frames, change state to activated
-            TASKS_ACTIVATE: u32,
-            ///  Disable NFC peripheral
-            TASKS_DISABLE: u32,
-            ///  Enable NFC sense field mode, change state to sense mode
-            TASKS_SENSE: u32,
-            ///  Start transmission of a outgoing frame, change state to transmit
-            TASKS_STARTTX: u32,
-            reserved28: [12]u8,
-            ///  Initializes the EasyDMA for receive.
-            TASKS_ENABLERXDATA: u32,
-            reserved36: [4]u8,
-            ///  Force state machine to IDLE state
-            TASKS_GOIDLE: u32,
-            ///  Force state machine to SLEEP_A state
-            TASKS_GOSLEEP: u32,
-            reserved256: [212]u8,
-            ///  The NFC peripheral is ready to receive and send frames
-            EVENTS_READY: u32,
-            ///  Remote NFC field detected
-            EVENTS_FIELDDETECTED: u32,
-            ///  Remote NFC field lost
-            EVENTS_FIELDLOST: u32,
-            ///  Marks the start of the first symbol of a transmitted frame
-            EVENTS_TXFRAMESTART: u32,
-            ///  Marks the end of the last transmitted on-air symbol of a frame
-            EVENTS_TXFRAMEEND: u32,
-            ///  Marks the end of the first symbol of a received frame
-            EVENTS_RXFRAMESTART: u32,
-            ///  Received data have been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer
-            EVENTS_RXFRAMEEND: u32,
-            ///  NFC error reported. The ERRORSTATUS register contains details on the source of the error.
-            EVENTS_ERROR: u32,
-            reserved296: [8]u8,
-            ///  NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.
-            EVENTS_RXERROR: u32,
-            ///  RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.
-            EVENTS_ENDRX: u32,
-            ///  Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer
-            EVENTS_ENDTX: u32,
-            reserved312: [4]u8,
-            ///  Auto collision resolution process has started
-            EVENTS_AUTOCOLRESSTARTED: u32,
-            reserved328: [12]u8,
-            ///  NFC Auto collision resolution error reported.
-            EVENTS_COLLISION: u32,
-            ///  NFC Auto collision resolution successfully completed
-            EVENTS_SELECTED: u32,
-            ///  EasyDMA is ready to receive or send frames.
-            EVENTS_STARTED: u32,
-            reserved512: [172]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between FIELDDETECTED event and ACTIVATE task
-                FIELDDETECTED_ACTIVATE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between FIELDLOST event and SENSE task
-                FIELDLOST_SENSE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for FIELDDETECTED event
-                FIELDDETECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for FIELDLOST event
-                FIELDLOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TXFRAMESTART event
-                TXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for TXFRAMEEND event
-                TXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for RXFRAMESTART event
-                RXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for RXFRAMEEND event
-                RXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u2,
-                ///  Enable or disable interrupt for RXERROR event
-                RXERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for ENDRX event
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for ENDTX event
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved14: u1,
-                ///  Enable or disable interrupt for AUTOCOLRESSTARTED event
-                AUTOCOLRESSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u3,
-                ///  Enable or disable interrupt for COLLISION event
-                COLLISION: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for SELECTED event
-                SELECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for STARTED event
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u11,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for FIELDDETECTED event
-                FIELDDETECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for FIELDLOST event
-                FIELDLOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TXFRAMESTART event
-                TXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for TXFRAMEEND event
-                TXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for RXFRAMESTART event
-                RXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for RXFRAMEEND event
-                RXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u2,
-                ///  Write '1' to Enable interrupt for RXERROR event
-                RXERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for ENDRX event
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for ENDTX event
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved14: u1,
-                ///  Write '1' to Enable interrupt for AUTOCOLRESSTARTED event
-                AUTOCOLRESSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u3,
-                ///  Write '1' to Enable interrupt for COLLISION event
-                COLLISION: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for SELECTED event
-                SELECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for STARTED event
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u11,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for FIELDDETECTED event
-                FIELDDETECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for FIELDLOST event
-                FIELDLOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TXFRAMESTART event
-                TXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for TXFRAMEEND event
-                TXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for RXFRAMESTART event
-                RXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for RXFRAMEEND event
-                RXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u2,
-                ///  Write '1' to Disable interrupt for RXERROR event
-                RXERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for ENDRX event
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for ENDTX event
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved14: u1,
-                ///  Write '1' to Disable interrupt for AUTOCOLRESSTARTED event
-                AUTOCOLRESSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u3,
-                ///  Write '1' to Disable interrupt for COLLISION event
-                COLLISION: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for SELECTED event
-                SELECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for STARTED event
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u11,
-            }),
-            reserved1028: [248]u8,
-            ///  NFC Error Status register
-            ERRORSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX
-                FRAMEDELAYTIMEOUT: u1,
-                reserved2: u1,
-                ///  Field level is too high at max load resistance
-                NFCFIELDTOOSTRONG: u1,
-                ///  Field level is too low at min load resistance
-                NFCFIELDTOOWEAK: u1,
-                padding: u28,
-            }),
-            reserved1072: [40]u8,
-            ///  Current value driven to the NFC Load Control
-            CURRENTLOADCTRL: mmio.Mmio(packed struct(u32) {
-                ///  Current value driven to the NFC Load Control
-                CURRENTLOADCTRL: u6,
-                padding: u26,
-            }),
-            reserved1084: [8]u8,
-            ///  Indicates the presence or not of a valid field
-            FIELDPRESENT: mmio.Mmio(packed struct(u32) {
-                ///  Indicates the presence or not of a valid field. Available only in the activated state.
-                FIELDPRESENT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No valid field detected
-                        NoField = 0x0,
-                        ///  Valid field detected
-                        FieldPresent = 0x1,
-                    },
-                },
-                ///  Indicates if the low level has locked to the field
-                LOCKDETECT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not locked to field
-                        NotLocked = 0x0,
-                        ///  Locked to field
-                        Locked = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1284: [196]u8,
-            ///  Minimum frame delay
-            FRAMEDELAYMIN: mmio.Mmio(packed struct(u32) {
-                ///  Minimum frame delay in number of 13.56 MHz clocks
-                FRAMEDELAYMIN: u16,
-                padding: u16,
-            }),
-            ///  Maximum frame delay
-            FRAMEDELAYMAX: mmio.Mmio(packed struct(u32) {
-                ///  Maximum frame delay in number of 13.56 MHz clocks
-                FRAMEDELAYMAX: u16,
-                padding: u16,
-            }),
-            ///  Configuration register for the Frame Delay Timer
-            FRAMEDELAYMODE: mmio.Mmio(packed struct(u32) {
-                ///  Configuration register for the Frame Delay Timer
-                FRAMEDELAYMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout.
-                        FreeRun = 0x0,
-                        ///  Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX
-                        Window = 0x1,
-                        ///  Frame is transmitted exactly at FRAMEDELAYMAX
-                        ExactVal = 0x2,
-                        ///  Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX
-                        WindowGrid = 0x3,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Packet pointer for TXD and RXD data storage in Data RAM
-            PACKETPTR: mmio.Mmio(packed struct(u32) {
-                ///  Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address.
-                PTR: u32,
-            }),
-            ///  Size of allocated for TXD and RXD data storage buffer in Data RAM
-            MAXLEN: mmio.Mmio(packed struct(u32) {
-                ///  Size of allocated for TXD and RXD data storage buffer in Data RAM
-                MAXLEN: u9,
-                padding: u23,
-            }),
-            reserved1424: [120]u8,
-            ///  Last NFCID1 part (4, 7 or 10 bytes ID)
-            NFCID1_LAST: mmio.Mmio(packed struct(u32) {
-                ///  NFCID1 byte Z (very last byte sent)
-                NFCID1_Z: u8,
-                ///  NFCID1 byte Y
-                NFCID1_Y: u8,
-                ///  NFCID1 byte X
-                NFCID1_X: u8,
-                ///  NFCID1 byte W
-                NFCID1_W: u8,
-            }),
-            ///  Second last NFCID1 part (7 or 10 bytes ID)
-            NFCID1_2ND_LAST: mmio.Mmio(packed struct(u32) {
-                ///  NFCID1 byte V
-                NFCID1_V: u8,
-                ///  NFCID1 byte U
-                NFCID1_U: u8,
-                ///  NFCID1 byte T
-                NFCID1_T: u8,
-                padding: u8,
-            }),
-            ///  Third last NFCID1 part (10 bytes ID)
-            NFCID1_3RD_LAST: mmio.Mmio(packed struct(u32) {
-                ///  NFCID1 byte S
-                NFCID1_S: u8,
-                ///  NFCID1 byte R
-                NFCID1_R: u8,
-                ///  NFCID1 byte Q
-                NFCID1_Q: u8,
-                padding: u8,
-            }),
-            reserved1440: [4]u8,
-            ///  NFC-A SENS_RES auto-response settings
-            SENSRES: mmio.Mmio(packed struct(u32) {
-                ///  Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
-                BITFRAMESDD: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        ///  SDD pattern 00000
-                        SDD00000 = 0x0,
-                        ///  SDD pattern 00001
-                        SDD00001 = 0x1,
-                        ///  SDD pattern 00010
-                        SDD00010 = 0x2,
-                        ///  SDD pattern 00100
-                        SDD00100 = 0x4,
-                        ///  SDD pattern 01000
-                        SDD01000 = 0x8,
-                        ///  SDD pattern 10000
-                        SDD10000 = 0x10,
-                        _,
-                    },
-                },
-                ///  Reserved for future use. Shall be 0.
-                RFU5: u1,
-                ///  NFCID1 size. This value is used by the Auto collision resolution engine.
-                NFCIDSIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  NFCID1 size: single (4 bytes)
-                        NFCID1Single = 0x0,
-                        ///  NFCID1 size: double (7 bytes)
-                        NFCID1Double = 0x1,
-                        ///  NFCID1 size: triple (10 bytes)
-                        NFCID1Triple = 0x2,
-                        _,
-                    },
-                },
-                ///  Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
-                PLATFCONFIG: u4,
-                ///  Reserved for future use. Shall be 0.
-                RFU74: u4,
-                padding: u16,
-            }),
-            ///  NFC-A SEL_RES auto-response settings
-            SELRES: mmio.Mmio(packed struct(u32) {
-                ///  Reserved for future use. Shall be 0.
-                RFU10: u2,
-                ///  Cascade bit (controlled by hardware, write has no effect)
-                CASCADE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  NFCID1 complete
-                        Complete = 0x0,
-                        ///  NFCID1 not complete
-                        NotComplete = 0x1,
-                    },
-                },
-                ///  Reserved for future use. Shall be 0.
-                RFU43: u2,
-                ///  Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
-                PROTOCOL: u2,
-                ///  Reserved for future use. Shall be 0.
-                RFU7: u1,
-                padding: u24,
-            }),
-        };
-
-        ///  GPIO Tasks and Events
-        pub const GPIOTE = extern struct {
-            ///  Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY.
-            TASKS_OUT: [8]u32,
-            reserved48: [16]u8,
-            ///  Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it high.
-            TASKS_SET: [8]u32,
-            reserved96: [16]u8,
-            ///  Description collection[0]: Task for writing to pin specified in CONFIG[0].PSEL. Action on pin is to set it low.
-            TASKS_CLR: [8]u32,
-            reserved256: [128]u8,
-            ///  Description collection[0]: Event generated from pin specified in CONFIG[0].PSEL
-            EVENTS_IN: [8]u32,
-            reserved380: [92]u8,
-            ///  Event generated from multiple input GPIO pins with SENSE mechanism enabled
-            EVENTS_PORT: u32,
-            reserved772: [388]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for IN[0] event
-                IN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for IN[1] event
-                IN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for IN[2] event
-                IN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for IN[3] event
-                IN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for IN[4] event
-                IN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for IN[5] event
-                IN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for IN[6] event
-                IN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for IN[7] event
-                IN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved31: u23,
-                ///  Write '1' to Enable interrupt for PORT event
-                PORT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for IN[0] event
-                IN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for IN[1] event
-                IN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for IN[2] event
-                IN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for IN[3] event
-                IN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for IN[4] event
-                IN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for IN[5] event
-                IN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for IN[6] event
-                IN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for IN[7] event
-                IN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved31: u23,
-                ///  Write '1' to Disable interrupt for PORT event
-                PORT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            reserved1296: [516]u8,
-            ///  Description collection[0]: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
-            CONFIG: [8]mmio.Mmio(packed struct(u32) {
-                ///  Mode
-                MODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.
-                        Disabled = 0x0,
-                        ///  Event mode
-                        Event = 0x1,
-                        ///  Task mode
-                        Task = 0x3,
-                        _,
-                    },
-                },
-                reserved8: u6,
-                ///  GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event
-                PSEL: u5,
-                reserved16: u3,
-                ///  When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
-                POLARITY: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.
-                        None = 0x0,
-                        ///  Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.
-                        LoToHi = 0x1,
-                        ///  Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.
-                        HiToLo = 0x2,
-                        ///  Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.
-                        Toggle = 0x3,
-                    },
-                },
-                reserved20: u2,
-                ///  When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
-                OUTINIT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Task mode: Initial value of pin before task triggering is low
-                        Low = 0x0,
-                        ///  Task mode: Initial value of pin before task triggering is high
-                        High = 0x1,
-                    },
-                },
-                padding: u11,
-            }),
-        };
-
-        ///  Analog to Digital Converter
-        pub const SAADC = extern struct {
-            ///  Start the ADC and prepare the result buffer in RAM
-            TASKS_START: u32,
-            ///  Take one ADC sample, if scan is enabled all channels are sampled
-            TASKS_SAMPLE: u32,
-            ///  Stop the ADC and terminate any on-going conversion
-            TASKS_STOP: u32,
-            ///  Starts offset auto-calibration
-            TASKS_CALIBRATEOFFSET: u32,
-            reserved256: [240]u8,
-            ///  The ADC has started
-            EVENTS_STARTED: u32,
-            ///  The ADC has filled up the Result buffer
-            EVENTS_END: u32,
-            ///  A conversion task has been completed. Depending on the mode, multiple conversions might be needed for a result to be transferred to RAM.
-            EVENTS_DONE: u32,
-            ///  A result is ready to get transferred to RAM.
-            EVENTS_RESULTDONE: u32,
-            ///  Calibration is complete
-            EVENTS_CALIBRATEDONE: u32,
-            ///  The ADC has stopped
-            EVENTS_STOPPED: u32,
-            reserved768: [488]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for STARTED event
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for DONE event
-                DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for RESULTDONE event
-                RESULTDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CALIBRATEDONE event
-                CALIBRATEDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[0].LIMITH event
-                CH0LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[0].LIMITL event
-                CH0LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[1].LIMITH event
-                CH1LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[1].LIMITL event
-                CH1LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[2].LIMITH event
-                CH2LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[2].LIMITL event
-                CH2LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[3].LIMITH event
-                CH3LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[3].LIMITL event
-                CH3LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[4].LIMITH event
-                CH4LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[4].LIMITL event
-                CH4LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[5].LIMITH event
-                CH5LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[5].LIMITL event
-                CH5LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[6].LIMITH event
-                CH6LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[6].LIMITL event
-                CH6LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[7].LIMITH event
-                CH7LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CH[7].LIMITL event
-                CH7LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u10,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for STARTED event
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for DONE event
-                DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for RESULTDONE event
-                RESULTDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CALIBRATEDONE event
-                CALIBRATEDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[0].LIMITH event
-                CH0LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[0].LIMITL event
-                CH0LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[1].LIMITH event
-                CH1LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[1].LIMITL event
-                CH1LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[2].LIMITH event
-                CH2LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[2].LIMITL event
-                CH2LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[3].LIMITH event
-                CH3LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[3].LIMITL event
-                CH3LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[4].LIMITH event
-                CH4LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[4].LIMITL event
-                CH4LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[5].LIMITH event
-                CH5LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[5].LIMITL event
-                CH5LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[6].LIMITH event
-                CH6LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[6].LIMITL event
-                CH6LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[7].LIMITH event
-                CH7LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CH[7].LIMITL event
-                CH7LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u10,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for STARTED event
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for DONE event
-                DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for RESULTDONE event
-                RESULTDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CALIBRATEDONE event
-                CALIBRATEDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[0].LIMITH event
-                CH0LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[0].LIMITL event
-                CH0LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[1].LIMITH event
-                CH1LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[1].LIMITL event
-                CH1LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[2].LIMITH event
-                CH2LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[2].LIMITL event
-                CH2LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[3].LIMITH event
-                CH3LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[3].LIMITL event
-                CH3LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[4].LIMITH event
-                CH4LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[4].LIMITL event
-                CH4LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[5].LIMITH event
-                CH5LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[5].LIMITL event
-                CH5LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[6].LIMITH event
-                CH6LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[6].LIMITL event
-                CH6LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[7].LIMITH event
-                CH7LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CH[7].LIMITL event
-                CH7LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u10,
-            }),
-            reserved1024: [244]u8,
-            ///  Status
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  Status
-                STATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  ADC is ready. No on-going conversion.
-                        Ready = 0x0,
-                        ///  ADC is busy. Conversion in progress.
-                        Busy = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1280: [252]u8,
-            ///  Enable or disable ADC
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable ADC
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable ADC
-                        Disabled = 0x0,
-                        ///  Enable ADC
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1520: [236]u8,
-            ///  Resolution configuration
-            RESOLUTION: mmio.Mmio(packed struct(u32) {
-                ///  Set the resolution
-                VAL: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  8 bit
-                        @"8bit" = 0x0,
-                        ///  10 bit
-                        @"10bit" = 0x1,
-                        ///  12 bit
-                        @"12bit" = 0x2,
-                        ///  14 bit
-                        @"14bit" = 0x3,
-                        _,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.
-            OVERSAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  Oversample control
-                OVERSAMPLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Bypass oversampling
-                        Bypass = 0x0,
-                        ///  Oversample 2x
-                        Over2x = 0x1,
-                        ///  Oversample 4x
-                        Over4x = 0x2,
-                        ///  Oversample 8x
-                        Over8x = 0x3,
-                        ///  Oversample 16x
-                        Over16x = 0x4,
-                        ///  Oversample 32x
-                        Over32x = 0x5,
-                        ///  Oversample 64x
-                        Over64x = 0x6,
-                        ///  Oversample 128x
-                        Over128x = 0x7,
-                        ///  Oversample 256x
-                        Over256x = 0x8,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Controls normal or continuous sample rate
-            SAMPLERATE: mmio.Mmio(packed struct(u32) {
-                ///  Capture and compare value. Sample rate is 16 MHz/CC
-                CC: u11,
-                reserved12: u1,
-                ///  Select mode for sample rate control
-                MODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Rate is controlled from SAMPLE task
-                        Task = 0x0,
-                        ///  Rate is controlled from local timer (use CC to control the rate)
-                        Timers = 0x1,
-                    },
-                },
-                padding: u19,
-            }),
-        };
-
-        ///  Timer/Counter 0
-        pub const TIMER0 = extern struct {
-            ///  Start Timer
-            TASKS_START: u32,
-            ///  Stop Timer
-            TASKS_STOP: u32,
-            ///  Increment Timer (Counter mode only)
-            TASKS_COUNT: u32,
-            ///  Clear time
-            TASKS_CLEAR: u32,
-            ///  Deprecated register - Shut down timer
-            TASKS_SHUTDOWN: u32,
-            reserved64: [44]u8,
-            ///  Description collection[0]: Capture Timer value to CC[0] register
-            TASKS_CAPTURE: [6]u32,
-            reserved320: [232]u8,
-            ///  Description collection[0]: Compare event on CC[0] match
-            EVENTS_COMPARE: [6]u32,
-            reserved512: [168]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between COMPARE[0] event and CLEAR task
-                COMPARE0_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between COMPARE[1] event and CLEAR task
-                COMPARE1_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between COMPARE[2] event and CLEAR task
-                COMPARE2_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between COMPARE[3] event and CLEAR task
-                COMPARE3_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between COMPARE[4] event and CLEAR task
-                COMPARE4_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between COMPARE[5] event and CLEAR task
-                COMPARE5_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                reserved8: u2,
-                ///  Shortcut between COMPARE[0] event and STOP task
-                COMPARE0_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between COMPARE[1] event and STOP task
-                COMPARE1_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between COMPARE[2] event and STOP task
-                COMPARE2_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between COMPARE[3] event and STOP task
-                COMPARE3_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between COMPARE[4] event and STOP task
-                COMPARE4_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between COMPARE[5] event and STOP task
-                COMPARE5_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u18,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  Write '1' to Enable interrupt for COMPARE[0] event
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for COMPARE[1] event
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for COMPARE[2] event
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for COMPARE[3] event
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for COMPARE[4] event
-                COMPARE4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for COMPARE[5] event
-                COMPARE5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u10,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  Write '1' to Disable interrupt for COMPARE[0] event
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for COMPARE[1] event
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for COMPARE[2] event
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for COMPARE[3] event
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for COMPARE[4] event
-                COMPARE4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for COMPARE[5] event
-                COMPARE5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u10,
-            }),
-            reserved1284: [504]u8,
-            ///  Timer mode selection
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Timer mode
-                MODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Select Timer mode
-                        Timer = 0x0,
-                        ///  Deprecated enumerator - Select Counter mode
-                        Counter = 0x1,
-                        ///  Select Low Power Counter mode
-                        LowPowerCounter = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Configure the number of bits used by the TIMER
-            BITMODE: mmio.Mmio(packed struct(u32) {
-                ///  Timer bit width
-                BITMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  16 bit timer bit width
-                        @"16Bit" = 0x0,
-                        ///  8 bit timer bit width
-                        @"08Bit" = 0x1,
-                        ///  24 bit timer bit width
-                        @"24Bit" = 0x2,
-                        ///  32 bit timer bit width
-                        @"32Bit" = 0x3,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1296: [4]u8,
-            ///  Timer prescaler register
-            PRESCALER: mmio.Mmio(packed struct(u32) {
-                ///  Prescaler value
-                PRESCALER: u4,
-                padding: u28,
-            }),
-            reserved1344: [44]u8,
-            ///  Description collection[0]: Capture/Compare register 0
-            CC: [6]mmio.Mmio(packed struct(u32) {
-                ///  Capture/Compare value
-                CC: u32,
-            }),
-        };
-
-        ///  Non Volatile Memory Controller
-        pub const NVMC = extern struct {
-            reserved1024: [1024]u8,
-            ///  Ready flag
-            READY: mmio.Mmio(packed struct(u32) {
-                ///  NVMC is ready or busy
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  NVMC is busy (on-going write or erase operation)
-                        Busy = 0x0,
-                        ///  NVMC is ready
-                        Ready = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1284: [256]u8,
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.
-                WEN: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Read only access
-                        Ren = 0x0,
-                        ///  Write Enabled
-                        Wen = 0x1,
-                        ///  Erase enabled
-                        Een = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Register for erasing a page in Code area
-            ERASEPAGE: mmio.Mmio(packed struct(u32) {
-                ///  Register for starting erase of a page in Code area
-                ERASEPAGE: u32,
-            }),
-            ///  Register for erasing all non-volatile user memory
-            ERASEALL: mmio.Mmio(packed struct(u32) {
-                ///  Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.
-                ERASEALL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No operation
-                        NoOperation = 0x0,
-                        ///  Start chip erase
-                        Erase = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Deprecated register - Register for erasing a page in Code area. Equivalent to ERASEPAGE.
-            ERASEPCR0: mmio.Mmio(packed struct(u32) {
-                ///  Register for starting erase of a page in Code area. Equivalent to ERASEPAGE.
-                ERASEPCR0: u32,
-            }),
-            ///  Register for erasing User Information Configuration Registers
-            ERASEUICR: mmio.Mmio(packed struct(u32) {
-                ///  Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased.
-                ERASEUICR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No operation
-                        NoOperation = 0x0,
-                        ///  Start erase of UICR
-                        Erase = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1344: [40]u8,
-            ///  I-Code cache configuration register.
-            ICACHECNF: mmio.Mmio(packed struct(u32) {
-                ///  Cache enable
-                CACHEEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable cache. Invalidates all cache entries.
-                        Disabled = 0x0,
-                        ///  Enable cache
-                        Enabled = 0x1,
-                    },
-                },
-                reserved8: u7,
-                ///  Cache profiling enable
-                CACHEPROFEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable cache profiling
-                        Disabled = 0x0,
-                        ///  Enable cache profiling
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            reserved1352: [4]u8,
-            ///  I-Code cache hit counter.
-            IHIT: mmio.Mmio(packed struct(u32) {
-                ///  Number of cache hits
-                HITS: u32,
-            }),
-            ///  I-Code cache miss counter.
-            IMISS: mmio.Mmio(packed struct(u32) {
-                ///  Number of cache misses
-                MISSES: u32,
-            }),
-        };
-
-        ///  Pulse Density Modulation (Digital Microphone) Interface
-        pub const PDM = extern struct {
-            ///  Starts continuous PDM transfer
-            TASKS_START: u32,
-            ///  Stops PDM transfer
-            TASKS_STOP: u32,
-            reserved256: [248]u8,
-            ///  PDM transfer has started
-            EVENTS_STARTED: u32,
-            ///  PDM transfer has finished
-            EVENTS_STOPPED: u32,
-            ///  The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM
-            EVENTS_END: u32,
-            reserved768: [500]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for STARTED event
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for STARTED event
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for STARTED event
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1280: [500]u8,
-            ///  PDM module enable register
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable PDM module
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  PDM clock generator control
-            PDMCLKCTRL: mmio.Mmio(packed struct(u32) {
-                ///  PDM_CLK frequency
-                FREQ: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  PDM_CLK = 32 MHz / 32 = 1.000 MHz
-                        @"1000K" = 0x8000000,
-                        ///  PDM_CLK = 32 MHz / 31 = 1.032 MHz
-                        Default = 0x8400000,
-                        ///  PDM_CLK = 32 MHz / 30 = 1.067 MHz
-                        @"1067K" = 0x8800000,
-                        _,
-                    },
-                },
-            }),
-            ///  Defines the routing of the connected PDM microphones' signals
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Mono or stereo operation
-                OPERATION: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]
-                        Stereo = 0x0,
-                        ///  Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]
-                        Mono = 0x1,
-                    },
-                },
-                ///  Defines on which PDM_CLK edge Left (or mono) is sampled
-                EDGE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Left (or mono) is sampled on falling edge of PDM_CLK
-                        LeftFalling = 0x0,
-                        ///  Left (or mono) is sampled on rising edge of PDM_CLK
-                        LeftRising = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1304: [12]u8,
-            ///  Left output gain adjustment
-            GAINL: mmio.Mmio(packed struct(u32) {
-                ///  Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust
-                GAINL: packed union {
-                    raw: u7,
-                    value: enum(u7) {
-                        ///  -20dB gain adjustment (minimum)
-                        MinGain = 0x0,
-                        ///  0dB gain adjustment ('2500 RMS' requirement)
-                        DefaultGain = 0x28,
-                        ///  +20dB gain adjustment (maximum)
-                        MaxGain = 0x50,
-                        _,
-                    },
-                },
-                padding: u25,
-            }),
-            ///  Right output gain adjustment
-            GAINR: mmio.Mmio(packed struct(u32) {
-                ///  Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)
-                GAINR: packed union {
-                    raw: u8,
-                    value: enum(u8) {
-                        ///  -20dB gain adjustment (minimum)
-                        MinGain = 0x0,
-                        ///  0dB gain adjustment ('2500 RMS' requirement)
-                        DefaultGain = 0x28,
-                        ///  +20dB gain adjustment (maximum)
-                        MaxGain = 0x50,
-                        _,
-                    },
-                },
-                padding: u24,
-            }),
-        };
-
-        ///  Real time counter 0
-        pub const RTC0 = extern struct {
-            ///  Start RTC COUNTER
-            TASKS_START: u32,
-            ///  Stop RTC COUNTER
-            TASKS_STOP: u32,
-            ///  Clear RTC COUNTER
-            TASKS_CLEAR: u32,
-            ///  Set COUNTER to 0xFFFFF0
-            TASKS_TRIGOVRFLW: u32,
-            reserved256: [240]u8,
-            ///  Event on COUNTER increment
-            EVENTS_TICK: u32,
-            ///  Event on COUNTER overflow
-            EVENTS_OVRFLW: u32,
-            reserved320: [56]u8,
-            ///  Description collection[0]: Compare event on CC[0] match
-            EVENTS_COMPARE: [4]u32,
-            reserved772: [436]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for TICK event
-                TICK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for OVRFLW event
-                OVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Write '1' to Enable interrupt for COMPARE[0] event
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for COMPARE[1] event
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for COMPARE[2] event
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for COMPARE[3] event
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for TICK event
-                TICK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for OVRFLW event
-                OVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Write '1' to Disable interrupt for COMPARE[0] event
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for COMPARE[1] event
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for COMPARE[2] event
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for COMPARE[3] event
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            reserved832: [52]u8,
-            ///  Enable or disable event routing
-            EVTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable event routing for TICK event
-                TICK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable event routing for OVRFLW event
-                OVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Enable or disable event routing for COMPARE[0] event
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable event routing for COMPARE[1] event
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable event routing for COMPARE[2] event
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable event routing for COMPARE[3] event
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            ///  Enable event routing
-            EVTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable event routing for TICK event
-                TICK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable event routing for OVRFLW event
-                OVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Write '1' to Enable event routing for COMPARE[0] event
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable event routing for COMPARE[1] event
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable event routing for COMPARE[2] event
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable event routing for COMPARE[3] event
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            ///  Disable event routing
-            EVTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable event routing for TICK event
-                TICK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable event routing for OVRFLW event
-                OVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Write '1' to Disable event routing for COMPARE[0] event
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable event routing for COMPARE[1] event
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable event routing for COMPARE[2] event
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable event routing for COMPARE[3] event
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            reserved1284: [440]u8,
-            ///  Current COUNTER value
-            COUNTER: mmio.Mmio(packed struct(u32) {
-                ///  Counter value
-                COUNTER: u24,
-                padding: u8,
-            }),
-            ///  12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped
-            PRESCALER: mmio.Mmio(packed struct(u32) {
-                ///  Prescaler value
-                PRESCALER: u12,
-                padding: u20,
-            }),
-            reserved1344: [52]u8,
-            ///  Description collection[0]: Compare register 0
-            CC: [4]mmio.Mmio(packed struct(u32) {
-                ///  Compare value
-                COMPARE: u24,
-                padding: u8,
-            }),
-        };
-
-        ///  Temperature Sensor
-        pub const TEMP = extern struct {
-            ///  Start temperature measurement
-            TASKS_START: u32,
-            ///  Stop temperature measurement
-            TASKS_STOP: u32,
-            reserved256: [248]u8,
-            ///  Temperature measurement complete, data ready
-            EVENTS_DATARDY: u32,
-            reserved772: [512]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for DATARDY event
-                DATARDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for DATARDY event
-                DATARDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1288: [508]u8,
-            ///  Temperature in degC (0.25deg steps)
-            TEMP: mmio.Mmio(packed struct(u32) {
-                ///  Temperature in degC (0.25deg steps)
-                TEMP: u32,
-            }),
-            reserved1312: [20]u8,
-            ///  Slope of 1st piece wise linear function
-            A0: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 1st piece wise linear function
-                A0: u12,
-                padding: u20,
-            }),
-            ///  Slope of 2nd piece wise linear function
-            A1: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 2nd piece wise linear function
-                A1: u12,
-                padding: u20,
-            }),
-            ///  Slope of 3rd piece wise linear function
-            A2: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 3rd piece wise linear function
-                A2: u12,
-                padding: u20,
-            }),
-            ///  Slope of 4th piece wise linear function
-            A3: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 4th piece wise linear function
-                A3: u12,
-                padding: u20,
-            }),
-            ///  Slope of 5th piece wise linear function
-            A4: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 5th piece wise linear function
-                A4: u12,
-                padding: u20,
-            }),
-            ///  Slope of 6th piece wise linear function
-            A5: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 6th piece wise linear function
-                A5: u12,
-                padding: u20,
-            }),
-            reserved1344: [8]u8,
-            ///  y-intercept of 1st piece wise linear function
-            B0: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 1st piece wise linear function
-                B0: u14,
-                padding: u18,
-            }),
-            ///  y-intercept of 2nd piece wise linear function
-            B1: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 2nd piece wise linear function
-                B1: u14,
-                padding: u18,
-            }),
-            ///  y-intercept of 3rd piece wise linear function
-            B2: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 3rd piece wise linear function
-                B2: u14,
-                padding: u18,
-            }),
-            ///  y-intercept of 4th piece wise linear function
-            B3: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 4th piece wise linear function
-                B3: u14,
-                padding: u18,
-            }),
-            ///  y-intercept of 5th piece wise linear function
-            B4: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 5th piece wise linear function
-                B4: u14,
-                padding: u18,
-            }),
-            ///  y-intercept of 6th piece wise linear function
-            B5: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 6th piece wise linear function
-                B5: u14,
-                padding: u18,
-            }),
-            reserved1376: [8]u8,
-            ///  End point of 1st piece wise linear function
-            T0: mmio.Mmio(packed struct(u32) {
-                ///  End point of 1st piece wise linear function
-                T0: u8,
-                padding: u24,
-            }),
-            ///  End point of 2nd piece wise linear function
-            T1: mmio.Mmio(packed struct(u32) {
-                ///  End point of 2nd piece wise linear function
-                T1: u8,
-                padding: u24,
-            }),
-            ///  End point of 3rd piece wise linear function
-            T2: mmio.Mmio(packed struct(u32) {
-                ///  End point of 3rd piece wise linear function
-                T2: u8,
-                padding: u24,
-            }),
-            ///  End point of 4th piece wise linear function
-            T3: mmio.Mmio(packed struct(u32) {
-                ///  End point of 4th piece wise linear function
-                T3: u8,
-                padding: u24,
-            }),
-            ///  End point of 5th piece wise linear function
-            T4: mmio.Mmio(packed struct(u32) {
-                ///  End point of 5th piece wise linear function
-                T4: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  Random Number Generator
-        pub const RNG = extern struct {
-            ///  Task starting the random number generator
-            TASKS_START: u32,
-            ///  Task stopping the random number generator
-            TASKS_STOP: u32,
-            reserved256: [248]u8,
-            ///  Event being generated for every new random number written to the VALUE register
-            EVENTS_VALRDY: u32,
-            reserved512: [252]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between VALRDY event and STOP task
-                VALRDY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for VALRDY event
-                VALRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for VALRDY event
-                VALRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1284: [504]u8,
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Bias correction
-                DERCEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Output random number
-            VALUE: mmio.Mmio(packed struct(u32) {
-                ///  Generated random number
-                VALUE: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  AES ECB Mode Encryption
-        pub const ECB = extern struct {
-            ///  Start ECB block encrypt
-            TASKS_STARTECB: u32,
-            ///  Abort a possible executing ECB operation
-            TASKS_STOPECB: u32,
-            reserved256: [248]u8,
-            ///  ECB block encrypt complete
-            EVENTS_ENDECB: u32,
-            ///  ECB block encrypt aborted because of a STOPECB task or due to an error
-            EVENTS_ERRORECB: u32,
-            reserved772: [508]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for ENDECB event
-                ENDECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for ERRORECB event
-                ERRORECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for ENDECB event
-                ENDECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for ERRORECB event
-                ERRORECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1284: [504]u8,
-            ///  ECB block encrypt memory pointers
-            ECBDATAPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to the ECB data structure (see Table 1 ECB data structure overview)
-                ECBDATAPTR: u32,
-            }),
-        };
-
-        ///  AES CCM Mode Encryption
-        pub const CCM = extern struct {
-            ///  Start generation of key-stream. This operation will stop by itself when completed.
-            TASKS_KSGEN: u32,
-            ///  Start encryption/decryption. This operation will stop by itself when completed.
-            TASKS_CRYPT: u32,
-            ///  Stop encryption/decryption
-            TASKS_STOP: u32,
-            reserved256: [244]u8,
-            ///  Key-stream generation complete
-            EVENTS_ENDKSGEN: u32,
-            ///  Encrypt/decrypt complete
-            EVENTS_ENDCRYPT: u32,
-            ///  CCM error event
-            EVENTS_ERROR: u32,
-            reserved512: [244]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between ENDKSGEN event and CRYPT task
-                ENDKSGEN_CRYPT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for ENDKSGEN event
-                ENDKSGEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for ENDCRYPT event
-                ENDCRYPT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for ENDKSGEN event
-                ENDKSGEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for ENDCRYPT event
-                ENDCRYPT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for ERROR event
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1024: [244]u8,
-            ///  MIC check result
-            MICSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  The result of the MIC check performed during the previous decryption operation
-                MICSTATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  MIC check failed
-                        CheckFailed = 0x0,
-                        ///  MIC check passed
-                        CheckPassed = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1280: [252]u8,
-            ///  Enable
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable CCM
-                ENABLE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Operation mode
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  The mode of operation to be used
-                MODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  AES CCM packet encryption mode
-                        Encryption = 0x0,
-                        ///  AES CCM packet decryption mode
-                        Decryption = 0x1,
-                    },
-                },
-                reserved16: u15,
-                ///  Data rate that the CCM shall run in synch with
-                DATARATE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  In synch with 1 Mbit data rate
-                        @"1Mbit" = 0x0,
-                        ///  In synch with 2 Mbit data rate
-                        @"2Mbit" = 0x1,
-                    },
-                },
-                reserved24: u7,
-                ///  Packet length configuration
-                LENGTH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Default length. Effective length of LENGTH field is 5-bit
-                        Default = 0x0,
-                        ///  Extended length. Effective length of LENGTH field is 8-bit
-                        Extended = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            ///  Pointer to data structure holding AES key and NONCE vector
-            CNFPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)
-                CNFPTR: u32,
-            }),
-            ///  Input pointer
-            INPTR: mmio.Mmio(packed struct(u32) {
-                ///  Input pointer
-                INPTR: u32,
-            }),
-            ///  Output pointer
-            OUTPTR: mmio.Mmio(packed struct(u32) {
-                ///  Output pointer
-                OUTPTR: u32,
-            }),
-            ///  Pointer to data area used for temporary storage
-            SCRATCHPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.
-                SCRATCHPTR: u32,
-            }),
-        };
-
-        ///  Accelerated Address Resolver
-        pub const AAR = extern struct {
-            ///  Start resolving addresses based on IRKs specified in the IRK data structure
-            TASKS_START: u32,
-            reserved8: [4]u8,
-            ///  Stop resolving addresses
-            TASKS_STOP: u32,
-            reserved256: [244]u8,
-            ///  Address resolution procedure complete
-            EVENTS_END: u32,
-            ///  Address resolved
-            EVENTS_RESOLVED: u32,
-            ///  Address not resolved
-            EVENTS_NOTRESOLVED: u32,
-            reserved772: [504]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for RESOLVED event
-                RESOLVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for NOTRESOLVED event
-                NOTRESOLVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for END event
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for RESOLVED event
-                RESOLVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for NOTRESOLVED event
-                NOTRESOLVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1024: [244]u8,
-            ///  Resolution status
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  The IRK that was used last time an address was resolved
-                STATUS: u4,
-                padding: u28,
-            }),
-            reserved1280: [252]u8,
-            ///  Enable AAR
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable AAR
-                ENABLE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x3,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Number of IRKs
-            NIRK: mmio.Mmio(packed struct(u32) {
-                ///  Number of Identity root keys available in the IRK data structure
-                NIRK: u5,
-                padding: u27,
-            }),
-            ///  Pointer to IRK data structure
-            IRKPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to the IRK data structure
-                IRKPTR: u32,
-            }),
-            reserved1296: [4]u8,
-            ///  Pointer to the resolvable address
-            ADDRPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to the resolvable address (6-bytes)
-                ADDRPTR: u32,
-            }),
-            ///  Pointer to data area used for temporary storage
-            SCRATCHPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved.
-                SCRATCHPTR: u32,
-            }),
-        };
-
-        ///  Watchdog Timer
-        pub const WDT = extern struct {
-            ///  Start the watchdog
-            TASKS_START: u32,
-            reserved256: [252]u8,
-            ///  Watchdog timeout
-            EVENTS_TIMEOUT: u32,
-            reserved772: [512]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for TIMEOUT event
-                TIMEOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for TIMEOUT event
-                TIMEOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1024: [244]u8,
-            ///  Run status
-            RUNSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  Indicates whether or not the watchdog is running
-                RUNSTATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Watchdog not running
-                        NotRunning = 0x0,
-                        ///  Watchdog is running
-                        Running = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Request status
-            REQSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  Request status for RR[0] register
-                RR0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[0] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[0] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[1] register
-                RR1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[1] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[1] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[2] register
-                RR2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[2] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[2] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[3] register
-                RR3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[3] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[3] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[4] register
-                RR4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[4] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[4] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[5] register
-                RR5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[5] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[5] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[6] register
-                RR6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[6] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[6] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[7] register
-                RR7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[7] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[7] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            reserved1284: [252]u8,
-            ///  Counter reload value
-            CRV: mmio.Mmio(packed struct(u32) {
-                ///  Counter reload value in number of cycles of the 32.768 kHz clock
-                CRV: u32,
-            }),
-            ///  Enable register for reload request registers
-            RREN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable RR[0] register
-                RR0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[0] register
-                        Disabled = 0x0,
-                        ///  Enable RR[0] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[1] register
-                RR1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[1] register
-                        Disabled = 0x0,
-                        ///  Enable RR[1] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[2] register
-                RR2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[2] register
-                        Disabled = 0x0,
-                        ///  Enable RR[2] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[3] register
-                RR3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[3] register
-                        Disabled = 0x0,
-                        ///  Enable RR[3] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[4] register
-                RR4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[4] register
-                        Disabled = 0x0,
-                        ///  Enable RR[4] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[5] register
-                RR5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[5] register
-                        Disabled = 0x0,
-                        ///  Enable RR[5] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[6] register
-                RR6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[6] register
-                        Disabled = 0x0,
-                        ///  Enable RR[6] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[7] register
-                RR7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[7] register
-                        Disabled = 0x0,
-                        ///  Enable RR[7] register
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Configure the watchdog to either be paused, or kept running, while the CPU is sleeping
-                SLEEP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pause watchdog while the CPU is sleeping
-                        Pause = 0x0,
-                        ///  Keep the watchdog running while the CPU is sleeping
-                        Run = 0x1,
-                    },
-                },
-                reserved3: u2,
-                ///  Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger
-                HALT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pause watchdog while the CPU is halted by the debugger
-                        Pause = 0x0,
-                        ///  Keep the watchdog running while the CPU is halted by the debugger
-                        Run = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1536: [240]u8,
-            ///  Description collection[0]: Reload request 0
-            RR: [8]mmio.Mmio(packed struct(u32) {
-                ///  Reload request register
-                RR: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  Value to request a reload of the watchdog timer
-                        Reload = 0x6e524635,
-                        _,
-                    },
-                },
-            }),
-        };
-
-        ///  Pulse Width Modulation Unit 0
-        pub const PWM0 = extern struct {
-            reserved4: [4]u8,
-            ///  Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
-            TASKS_STOP: u32,
-            ///  Description collection[0]: Loads the first PWM value on all enabled channels from sequence 0, and starts playing that sequence at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes PWM generation to start it was not running.
-            TASKS_SEQSTART: [2]u32,
-            ///  Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start it was not running.
-            TASKS_NEXTSTEP: u32,
-            reserved260: [240]u8,
-            ///  Response to STOP task, emitted when PWM pulses are no longer generated
-            EVENTS_STOPPED: u32,
-            ///  Description collection[0]: First PWM period started on sequence 0
-            EVENTS_SEQSTARTED: [2]u32,
-            ///  Description collection[0]: Emitted at end of every sequence 0, when last value from RAM has been applied to wave counter
-            EVENTS_SEQEND: [2]u32,
-            ///  Emitted at the end of each PWM period
-            EVENTS_PWMPERIODEND: u32,
-            ///  Concatenated sequences have been played the amount of times defined in LOOP.CNT
-            EVENTS_LOOPSDONE: u32,
-            reserved512: [224]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between SEQEND[0] event and STOP task
-                SEQEND0_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between SEQEND[1] event and STOP task
-                SEQEND1_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between LOOPSDONE event and SEQSTART[0] task
-                LOOPSDONE_SEQSTART0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between LOOPSDONE event and SEQSTART[1] task
-                LOOPSDONE_SEQSTART1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between LOOPSDONE event and STOP task
-                LOOPSDONE_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Enable or disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for SEQSTARTED[0] event
-                SEQSTARTED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for SEQSTARTED[1] event
-                SEQSTARTED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for SEQEND[0] event
-                SEQEND0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for SEQEND[1] event
-                SEQEND1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for PWMPERIODEND event
-                PWMPERIODEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for LOOPSDONE event
-                LOOPSDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Enable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for SEQSTARTED[0] event
-                SEQSTARTED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for SEQSTARTED[1] event
-                SEQSTARTED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for SEQEND[0] event
-                SEQEND0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for SEQEND[1] event
-                SEQEND1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for PWMPERIODEND event
-                PWMPERIODEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for LOOPSDONE event
-                LOOPSDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to Disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for SEQSTARTED[0] event
-                SEQSTARTED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for SEQSTARTED[1] event
-                SEQSTARTED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for SEQEND[0] event
-                SEQEND0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for SEQEND[1] event
-                SEQEND1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for PWMPERIODEND event
-                PWMPERIODEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for LOOPSDONE event
-                LOOPSDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            reserved1280: [500]u8,
-            ///  PWM module enable register
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable PWM module
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Selects operating mode of the wave counter
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Selects up or up and down as wave counter mode
-                UPDOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Up counter - edge aligned PWM duty-cycle
-                        Up = 0x0,
-                        ///  Up and down counter - center aligned PWM duty cycle
-                        UpAndDown = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Value up to which the pulse generator counter counts
-            COUNTERTOP: mmio.Mmio(packed struct(u32) {
-                ///  Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used.
-                COUNTERTOP: u15,
-                padding: u17,
-            }),
-            ///  Configuration for PWM_CLK
-            PRESCALER: mmio.Mmio(packed struct(u32) {
-                ///  Pre-scaler of PWM_CLK
-                PRESCALER: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Divide by 1 (16MHz)
-                        DIV_1 = 0x0,
-                        ///  Divide by 2 ( 8MHz)
-                        DIV_2 = 0x1,
-                        ///  Divide by 4 ( 4MHz)
-                        DIV_4 = 0x2,
-                        ///  Divide by 8 ( 2MHz)
-                        DIV_8 = 0x3,
-                        ///  Divide by 16 ( 1MHz)
-                        DIV_16 = 0x4,
-                        ///  Divide by 32 ( 500kHz)
-                        DIV_32 = 0x5,
-                        ///  Divide by 64 ( 250kHz)
-                        DIV_64 = 0x6,
-                        ///  Divide by 128 ( 125kHz)
-                        DIV_128 = 0x7,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Configuration of the decoder
-            DECODER: mmio.Mmio(packed struct(u32) {
-                ///  How a sequence is read from RAM and spread to the compare register
-                LOAD: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  1st half word (16-bit) used in all PWM channels 0..3
-                        Common = 0x0,
-                        ///  1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3
-                        Grouped = 0x1,
-                        ///  1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3
-                        Individual = 0x2,
-                        ///  1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP
-                        WaveForm = 0x3,
-                    },
-                },
-                reserved8: u6,
-                ///  Selects source for advancing the active sequence
-                MODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  SEQ[n].REFRESH is used to determine loading internal compare registers
-                        RefreshCount = 0x0,
-                        ///  NEXTSTEP task causes a new value to be loaded to internal compare registers
-                        NextStep = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            ///  Amount of playback of a loop
-            LOOP: mmio.Mmio(packed struct(u32) {
-                ///  Amount of playback of pattern cycles
-                CNT: packed union {
-                    raw: u16,
-                    value: enum(u16) {
-                        ///  Looping disabled (stop at the end of the sequence)
-                        Disabled = 0x0,
-                        _,
-                    },
-                },
-                padding: u16,
-            }),
-        };
-
-        ///  Quadrature Decoder
-        pub const QDEC = extern struct {
-            ///  Task starting the quadrature decoder
-            TASKS_START: u32,
-            ///  Task stopping the quadrature decoder
-            TASKS_STOP: u32,
-            ///  Read and clear ACC and ACCDBL
-            TASKS_READCLRACC: u32,
-            ///  Read and clear ACC
-            TASKS_RDCLRACC: u32,
-            ///  Read and clear ACCDBL
-            TASKS_RDCLRDBL: u32,
-            reserved256: [236]u8,
-            ///  Event being generated for every new sample value written to the SAMPLE register
-            EVENTS_SAMPLERDY: u32,
-            ///  Non-null report ready
-            EVENTS_REPORTRDY: u32,
-            ///  ACC or ACCDBL register overflow
-            EVENTS_ACCOF: u32,
-            ///  Double displacement(s) detected
-            EVENTS_DBLRDY: u32,
-            ///  QDEC has been stopped
-            EVENTS_STOPPED: u32,
-            reserved512: [236]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between REPORTRDY event and READCLRACC task
-                REPORTRDY_READCLRACC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between SAMPLERDY event and STOP task
-                SAMPLERDY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between REPORTRDY event and RDCLRACC task
-                REPORTRDY_RDCLRACC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between REPORTRDY event and STOP task
-                REPORTRDY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between DBLRDY event and RDCLRDBL task
-                DBLRDY_RDCLRDBL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between DBLRDY event and STOP task
-                DBLRDY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between SAMPLERDY event and READCLRACC task
-                SAMPLERDY_READCLRACC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u25,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for SAMPLERDY event
-                SAMPLERDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for REPORTRDY event
-                REPORTRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for ACCOF event
-                ACCOF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for DBLRDY event
-                DBLRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for SAMPLERDY event
-                SAMPLERDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for REPORTRDY event
-                REPORTRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for ACCOF event
-                ACCOF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for DBLRDY event
-                DBLRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for STOPPED event
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved1280: [500]u8,
-            ///  Enable the quadrature decoder
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable the quadrature decoder
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  LED output pin polarity
-            LEDPOL: mmio.Mmio(packed struct(u32) {
-                ///  LED output pin polarity
-                LEDPOL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Led active on output pin low
-                        ActiveLow = 0x0,
-                        ///  Led active on output pin high
-                        ActiveHigh = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Sample period
-            SAMPLEPER: mmio.Mmio(packed struct(u32) {
-                ///  Sample period. The SAMPLE register will be updated for every new sample
-                SAMPLEPER: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  128 us
-                        @"128us" = 0x0,
-                        ///  256 us
-                        @"256us" = 0x1,
-                        ///  512 us
-                        @"512us" = 0x2,
-                        ///  1024 us
-                        @"1024us" = 0x3,
-                        ///  2048 us
-                        @"2048us" = 0x4,
-                        ///  4096 us
-                        @"4096us" = 0x5,
-                        ///  8192 us
-                        @"8192us" = 0x6,
-                        ///  16384 us
-                        @"16384us" = 0x7,
-                        ///  32768 us
-                        @"32ms" = 0x8,
-                        ///  65536 us
-                        @"65ms" = 0x9,
-                        ///  131072 us
-                        @"131ms" = 0xa,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Motion sample value
-            SAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  Last motion sample
-                SAMPLE: u32,
-            }),
-            ///  Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
-            REPORTPER: mmio.Mmio(packed struct(u32) {
-                ///  Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated
-                REPORTPER: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  10 samples / report
-                        @"10Smpl" = 0x0,
-                        ///  40 samples / report
-                        @"40Smpl" = 0x1,
-                        ///  80 samples / report
-                        @"80Smpl" = 0x2,
-                        ///  120 samples / report
-                        @"120Smpl" = 0x3,
-                        ///  160 samples / report
-                        @"160Smpl" = 0x4,
-                        ///  200 samples / report
-                        @"200Smpl" = 0x5,
-                        ///  240 samples / report
-                        @"240Smpl" = 0x6,
-                        ///  280 samples / report
-                        @"280Smpl" = 0x7,
-                        ///  1 sample / report
-                        @"1Smpl" = 0x8,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Register accumulating the valid transitions
-            ACC: mmio.Mmio(packed struct(u32) {
-                ///  Register accumulating all valid samples (not double transition) read from the SAMPLE register
-                ACC: u32,
-            }),
-            ///  Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
-            ACCREAD: mmio.Mmio(packed struct(u32) {
-                ///  Snapshot of the ACC register.
-                ACCREAD: u32,
-            }),
-            reserved1320: [12]u8,
-            ///  Enable input debounce filters
-            DBFEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable input debounce filters
-                DBFEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Debounce input filters disabled
-                        Disabled = 0x0,
-                        ///  Debounce input filters enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1344: [20]u8,
-            ///  Time period the LED is switched ON prior to sampling
-            LEDPRE: mmio.Mmio(packed struct(u32) {
-                ///  Period in us the LED is switched on prior to sampling
-                LEDPRE: u9,
-                padding: u23,
-            }),
-            ///  Register accumulating the number of detected double transitions
-            ACCDBL: mmio.Mmio(packed struct(u32) {
-                ///  Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).
-                ACCDBL: u4,
-                padding: u28,
-            }),
-            ///  Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
-            ACCDBLREAD: mmio.Mmio(packed struct(u32) {
-                ///  Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered.
-                ACCDBLREAD: u4,
-                padding: u28,
-            }),
-        };
-
-        ///  Comparator
-        pub const COMP = extern struct {
-            ///  Start comparator
-            TASKS_START: u32,
-            ///  Stop comparator
-            TASKS_STOP: u32,
-            ///  Sample comparator value
-            TASKS_SAMPLE: u32,
-            reserved256: [244]u8,
-            ///  COMP is ready and output is valid
-            EVENTS_READY: u32,
-            ///  Downward crossing
-            EVENTS_DOWN: u32,
-            ///  Upward crossing
-            EVENTS_UP: u32,
-            ///  Downward or upward crossing
-            EVENTS_CROSS: u32,
-            reserved512: [240]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between READY event and SAMPLE task
-                READY_SAMPLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between READY event and STOP task
-                READY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between DOWN event and STOP task
-                DOWN_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between UP event and STOP task
-                UP_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between CROSS event and STOP task
-                CROSS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for DOWN event
-                DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for UP event
-                UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for CROSS event
-                CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for DOWN event
-                DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for UP event
-                UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CROSS event
-                CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for DOWN event
-                DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for UP event
-                UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CROSS event
-                CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1024: [244]u8,
-            ///  Compare result
-            RESULT: mmio.Mmio(packed struct(u32) {
-                ///  Result of last compare. Decision point SAMPLE task.
-                RESULT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Input voltage is below the threshold (VIN+ < VIN-)
-                        Below = 0x0,
-                        ///  Input voltage is above the threshold (VIN+ > VIN-)
-                        Above = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1280: [252]u8,
-            ///  COMP enable
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable COMP
-                ENABLE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Pin select
-            PSEL: mmio.Mmio(packed struct(u32) {
-                ///  Analog pin select
-                PSEL: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  AIN0 selected as analog input
-                        AnalogInput0 = 0x0,
-                        ///  AIN1 selected as analog input
-                        AnalogInput1 = 0x1,
-                        ///  AIN2 selected as analog input
-                        AnalogInput2 = 0x2,
-                        ///  AIN3 selected as analog input
-                        AnalogInput3 = 0x3,
-                        ///  AIN4 selected as analog input
-                        AnalogInput4 = 0x4,
-                        ///  AIN5 selected as analog input
-                        AnalogInput5 = 0x5,
-                        ///  AIN6 selected as analog input
-                        AnalogInput6 = 0x6,
-                        ///  AIN7 selected as analog input
-                        AnalogInput7 = 0x7,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Reference source select for single-ended mode
-            REFSEL: mmio.Mmio(packed struct(u32) {
-                ///  Reference select
-                REFSEL: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  VREF = internal 1.2 V reference (VDD >= 1.7 V)
-                        Int1V2 = 0x0,
-                        ///  VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)
-                        Int1V8 = 0x1,
-                        ///  VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)
-                        Int2V4 = 0x2,
-                        ///  VREF = VDD
-                        VDD = 0x4,
-                        ///  VREF = AREF (VDD >= VREF >= AREFMIN)
-                        ARef = 0x7,
-                        _,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  External reference select
-            EXTREFSEL: mmio.Mmio(packed struct(u32) {
-                ///  External analog reference select
-                EXTREFSEL: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Use AIN0 as external analog reference
-                        AnalogReference0 = 0x0,
-                        ///  Use AIN1 as external analog reference
-                        AnalogReference1 = 0x1,
-                        ///  Use AIN2 as external analog reference
-                        AnalogReference2 = 0x2,
-                        ///  Use AIN3 as external analog reference
-                        AnalogReference3 = 0x3,
-                        ///  Use AIN4 as external analog reference
-                        AnalogReference4 = 0x4,
-                        ///  Use AIN5 as external analog reference
-                        AnalogReference5 = 0x5,
-                        ///  Use AIN6 as external analog reference
-                        AnalogReference6 = 0x6,
-                        ///  Use AIN7 as external analog reference
-                        AnalogReference7 = 0x7,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1328: [32]u8,
-            ///  Threshold configuration for hysteresis unit
-            TH: mmio.Mmio(packed struct(u32) {
-                ///  VDOWN = (THDOWN+1)/64*VREF
-                THDOWN: u6,
-                reserved8: u2,
-                ///  VUP = (THUP+1)/64*VREF
-                THUP: u6,
-                padding: u18,
-            }),
-            ///  Mode configuration
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Speed and power modes
-                SP: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Low-power mode
-                        Low = 0x0,
-                        ///  Normal mode
-                        Normal = 0x1,
-                        ///  High-speed mode
-                        High = 0x2,
-                        _,
-                    },
-                },
-                reserved8: u6,
-                ///  Main operation modes
-                MAIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Single-ended mode
-                        SE = 0x0,
-                        ///  Differential mode
-                        Diff = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            ///  Comparator hysteresis enable
-            HYST: mmio.Mmio(packed struct(u32) {
-                ///  Comparator hysteresis
-                HYST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Comparator hysteresis disabled
-                        NoHyst = 0x0,
-                        ///  Comparator hysteresis enabled
-                        Hyst50mV = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Current source select on analog input
-            ISOURCE: mmio.Mmio(packed struct(u32) {
-                ///  Comparator hysteresis
-                ISOURCE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Current source disabled
-                        Off = 0x0,
-                        ///  Current source enabled (+/- 2.5 uA)
-                        Ien2mA5 = 0x1,
-                        ///  Current source enabled (+/- 5 uA)
-                        Ien5mA = 0x2,
-                        ///  Current source enabled (+/- 10 uA)
-                        Ien10mA = 0x3,
-                    },
-                },
-                padding: u30,
-            }),
-        };
-
-        ///  Low Power Comparator
-        pub const LPCOMP = extern struct {
-            ///  Start comparator
-            TASKS_START: u32,
-            ///  Stop comparator
-            TASKS_STOP: u32,
-            ///  Sample comparator value
-            TASKS_SAMPLE: u32,
-            reserved256: [244]u8,
-            ///  LPCOMP is ready and output is valid
-            EVENTS_READY: u32,
-            ///  Downward crossing
-            EVENTS_DOWN: u32,
-            ///  Upward crossing
-            EVENTS_UP: u32,
-            ///  Downward or upward crossing
-            EVENTS_CROSS: u32,
-            reserved512: [240]u8,
-            ///  Shortcut register
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between READY event and SAMPLE task
-                READY_SAMPLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between READY event and STOP task
-                READY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between DOWN event and STOP task
-                DOWN_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between UP event and STOP task
-                UP_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between CROSS event and STOP task
-                CROSS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Enable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for DOWN event
-                DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for UP event
-                UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Enable interrupt for CROSS event
-                CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to Disable interrupt for READY event
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for DOWN event
-                DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for UP event
-                UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to Disable interrupt for CROSS event
-                CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1024: [244]u8,
-            ///  Compare result
-            RESULT: mmio.Mmio(packed struct(u32) {
-                ///  Result of last compare. Decision point SAMPLE task.
-                RESULT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Input voltage is below the reference threshold (VIN+ < VIN-).
-                        Below = 0x0,
-                        ///  Input voltage is above the reference threshold (VIN+ > VIN-).
-                        Above = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1280: [252]u8,
-            ///  Enable LPCOMP
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable LPCOMP
-                ENABLE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Input pin select
-            PSEL: mmio.Mmio(packed struct(u32) {
-                ///  Analog pin select
-                PSEL: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  AIN0 selected as analog input
-                        AnalogInput0 = 0x0,
-                        ///  AIN1 selected as analog input
-                        AnalogInput1 = 0x1,
-                        ///  AIN2 selected as analog input
-                        AnalogInput2 = 0x2,
-                        ///  AIN3 selected as analog input
-                        AnalogInput3 = 0x3,
-                        ///  AIN4 selected as analog input
-                        AnalogInput4 = 0x4,
-                        ///  AIN5 selected as analog input
-                        AnalogInput5 = 0x5,
-                        ///  AIN6 selected as analog input
-                        AnalogInput6 = 0x6,
-                        ///  AIN7 selected as analog input
-                        AnalogInput7 = 0x7,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Reference select
-            REFSEL: mmio.Mmio(packed struct(u32) {
-                ///  Reference select
-                REFSEL: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  VDD * 1/8 selected as reference
-                        Ref1_8Vdd = 0x0,
-                        ///  VDD * 2/8 selected as reference
-                        Ref2_8Vdd = 0x1,
-                        ///  VDD * 3/8 selected as reference
-                        Ref3_8Vdd = 0x2,
-                        ///  VDD * 4/8 selected as reference
-                        Ref4_8Vdd = 0x3,
-                        ///  VDD * 5/8 selected as reference
-                        Ref5_8Vdd = 0x4,
-                        ///  VDD * 6/8 selected as reference
-                        Ref6_8Vdd = 0x5,
-                        ///  VDD * 7/8 selected as reference
-                        Ref7_8Vdd = 0x6,
-                        ///  External analog reference selected
-                        ARef = 0x7,
-                        ///  VDD * 1/16 selected as reference
-                        Ref1_16Vdd = 0x8,
-                        ///  VDD * 3/16 selected as reference
-                        Ref3_16Vdd = 0x9,
-                        ///  VDD * 5/16 selected as reference
-                        Ref5_16Vdd = 0xa,
-                        ///  VDD * 7/16 selected as reference
-                        Ref7_16Vdd = 0xb,
-                        ///  VDD * 9/16 selected as reference
-                        Ref9_16Vdd = 0xc,
-                        ///  VDD * 11/16 selected as reference
-                        Ref11_16Vdd = 0xd,
-                        ///  VDD * 13/16 selected as reference
-                        Ref13_16Vdd = 0xe,
-                        ///  VDD * 15/16 selected as reference
-                        Ref15_16Vdd = 0xf,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  External reference select
-            EXTREFSEL: mmio.Mmio(packed struct(u32) {
-                ///  External analog reference select
-                EXTREFSEL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Use AIN0 as external analog reference
-                        AnalogReference0 = 0x0,
-                        ///  Use AIN1 as external analog reference
-                        AnalogReference1 = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1312: [16]u8,
-            ///  Analog detect configuration
-            ANADETECT: mmio.Mmio(packed struct(u32) {
-                ///  Analog detect configuration
-                ANADETECT: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Generate ANADETECT on crossing, both upward crossing and downward crossing
-                        Cross = 0x0,
-                        ///  Generate ANADETECT on upward crossing only
-                        Up = 0x1,
-                        ///  Generate ANADETECT on downward crossing only
-                        Down = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1336: [20]u8,
-            ///  Comparator hysteresis enable
-            HYST: mmio.Mmio(packed struct(u32) {
-                ///  Comparator hysteresis enable
-                HYST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Comparator hysteresis disabled
-                        NoHyst = 0x0,
-                        ///  Comparator hysteresis disabled (typ. 50 mV)
-                        Hyst50mV = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  Software interrupt 0
-        pub const SWI0 = extern struct {
-            ///  Unused.
-            UNUSED: u32,
-        };
-    };
-};
diff --git a/src/chips/nrf52840.zig b/src/chips/nrf52840.zig
deleted file mode 100644
index 955d043ff..000000000
--- a/src/chips/nrf52840.zig
+++ /dev/null
@@ -1,21782 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    ///  nRF52840 reference description for radio MCU with ARM 32-bit Cortex-M4 Microcontroller
-    pub const nrf52840 = struct {
-        pub const properties = struct {
-            pub const @"cpu.nvic_prio_bits" = "3";
-            pub const @"cpu.mpu" = "1";
-            pub const @"cpu.fpu" = "1";
-            pub const @"cpu.revision" = "r0p1";
-            pub const @"cpu.vendor_systick_config" = "0";
-            pub const license =
-                \\
-                \\Copyright (c) 2010 - 2021, Nordic Semiconductor ASA All rights reserved.\n
-                \\\n
-                \\Redistribution and use in source and binary forms, with or without\n
-                \\modification, are permitted provided that the following conditions are met:\n
-                \\\n
-                \\1. Redistributions of source code must retain the above copyright notice, this\n
-                \\   list of conditions and the following disclaimer.\n
-                \\\n
-                \\2. Redistributions in binary form must reproduce the above copyright\n
-                \\   notice, this list of conditions and the following disclaimer in the\n
-                \\   documentation and/or other materials provided with the distribution.\n
-                \\\n
-                \\3. Neither the name of Nordic Semiconductor ASA nor the names of its\n
-                \\   contributors may be used to endorse or promote products derived from this\n
-                \\   software without specific prior written permission.\n
-                \\\n
-                \\THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"\n
-                \\AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE\n
-                \\IMPLIED WARRANTIES OF MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE\n
-                \\ARE DISCLAIMED. IN NO EVENT SHALL NORDIC SEMICONDUCTOR ASA OR CONTRIBUTORS BE\n
-                \\LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR\n
-                \\CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF\n
-                \\SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS\n
-                \\INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN\n
-                \\CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)\n
-                \\ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE\n
-                \\POSSIBILITY OF SUCH DAMAGE.\n
-                \\        
-            ;
-            pub const @"cpu.name" = "CM4";
-            pub const @"cpu.endian" = "little";
-        };
-
-        pub const VectorTable = extern struct {
-            const Handler = micro.interrupt.Handler;
-            const unhandled = micro.interrupt.unhandled;
-
-            initial_stack_pointer: u32,
-            Reset: Handler = unhandled,
-            NMI: Handler = unhandled,
-            HardFault: Handler = unhandled,
-            MemManageFault: Handler = unhandled,
-            BusFault: Handler = unhandled,
-            UsageFault: Handler = unhandled,
-            reserved5: [4]u32 = undefined,
-            SVCall: Handler = unhandled,
-            DebugMonitor: Handler = unhandled,
-            reserved11: [1]u32 = undefined,
-            PendSV: Handler = unhandled,
-            SysTick: Handler = unhandled,
-            POWER_CLOCK: Handler = unhandled,
-            RADIO: Handler = unhandled,
-            UARTE0_UART0: Handler = unhandled,
-            SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0: Handler = unhandled,
-            SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1: Handler = unhandled,
-            NFCT: Handler = unhandled,
-            GPIOTE: Handler = unhandled,
-            SAADC: Handler = unhandled,
-            TIMER0: Handler = unhandled,
-            TIMER1: Handler = unhandled,
-            TIMER2: Handler = unhandled,
-            RTC0: Handler = unhandled,
-            TEMP: Handler = unhandled,
-            RNG: Handler = unhandled,
-            ECB: Handler = unhandled,
-            CCM_AAR: Handler = unhandled,
-            WDT: Handler = unhandled,
-            RTC1: Handler = unhandled,
-            QDEC: Handler = unhandled,
-            COMP_LPCOMP: Handler = unhandled,
-            SWI0_EGU0: Handler = unhandled,
-            SWI1_EGU1: Handler = unhandled,
-            SWI2_EGU2: Handler = unhandled,
-            SWI3_EGU3: Handler = unhandled,
-            SWI4_EGU4: Handler = unhandled,
-            SWI5_EGU5: Handler = unhandled,
-            TIMER3: Handler = unhandled,
-            TIMER4: Handler = unhandled,
-            PWM0: Handler = unhandled,
-            PDM: Handler = unhandled,
-            reserved44: [2]u32 = undefined,
-            MWU: Handler = unhandled,
-            PWM1: Handler = unhandled,
-            PWM2: Handler = unhandled,
-            SPIM2_SPIS2_SPI2: Handler = unhandled,
-            RTC2: Handler = unhandled,
-            I2S: Handler = unhandled,
-            FPU: Handler = unhandled,
-            USBD: Handler = unhandled,
-            UARTE1: Handler = unhandled,
-            QSPI: Handler = unhandled,
-            CRYPTOCELL: Handler = unhandled,
-            reserved57: [2]u32 = undefined,
-            PWM3: Handler = unhandled,
-            reserved60: [1]u32 = undefined,
-            SPIM3: Handler = unhandled,
-        };
-
-        pub const peripherals = struct {
-            ///  Factory information configuration registers
-            pub const FICR = @as(*volatile types.peripherals.FICR, @ptrFromInt(0x10000000));
-            ///  User information configuration registers
-            pub const UICR = @as(*volatile types.peripherals.UICR, @ptrFromInt(0x10001000));
-            ///  Clock control
-            pub const CLOCK = @as(*volatile types.peripherals.CLOCK, @ptrFromInt(0x40000000));
-            ///  Power control
-            pub const POWER = @as(*volatile types.peripherals.POWER, @ptrFromInt(0x40000000));
-            ///  2.4 GHz radio
-            pub const RADIO = @as(*volatile types.peripherals.RADIO, @ptrFromInt(0x40001000));
-            ///  Universal Asynchronous Receiver/Transmitter
-            pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40002000));
-            ///  UART with EasyDMA 0
-            pub const UARTE0 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40002000));
-            ///  Serial Peripheral Interface 0
-            pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40003000));
-            ///  Serial Peripheral Interface Master with EasyDMA 0
-            pub const SPIM0 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40003000));
-            ///  SPI Slave 0
-            pub const SPIS0 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40003000));
-            ///  I2C compatible Two-Wire Interface 0
-            pub const TWI0 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40003000));
-            ///  I2C compatible Two-Wire Master Interface with EasyDMA 0
-            pub const TWIM0 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40003000));
-            ///  I2C compatible Two-Wire Slave Interface with EasyDMA 0
-            pub const TWIS0 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40003000));
-            ///  Serial Peripheral Interface 1
-            pub const SPI1 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40004000));
-            ///  Serial Peripheral Interface Master with EasyDMA 1
-            pub const SPIM1 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40004000));
-            ///  SPI Slave 1
-            pub const SPIS1 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40004000));
-            ///  I2C compatible Two-Wire Interface 1
-            pub const TWI1 = @as(*volatile types.peripherals.TWI0, @ptrFromInt(0x40004000));
-            ///  I2C compatible Two-Wire Master Interface with EasyDMA 1
-            pub const TWIM1 = @as(*volatile types.peripherals.TWIM0, @ptrFromInt(0x40004000));
-            ///  I2C compatible Two-Wire Slave Interface with EasyDMA 1
-            pub const TWIS1 = @as(*volatile types.peripherals.TWIS0, @ptrFromInt(0x40004000));
-            ///  NFC-A compatible radio
-            pub const NFCT = @as(*volatile types.peripherals.NFCT, @ptrFromInt(0x40005000));
-            ///  GPIO Tasks and Events
-            pub const GPIOTE = @as(*volatile types.peripherals.GPIOTE, @ptrFromInt(0x40006000));
-            ///  Successive approximation register (SAR) analog-to-digital converter
-            pub const SAADC = @as(*volatile types.peripherals.SAADC, @ptrFromInt(0x40007000));
-            ///  Timer/Counter 0
-            pub const TIMER0 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40008000));
-            ///  Timer/Counter 1
-            pub const TIMER1 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x40009000));
-            ///  Timer/Counter 2
-            pub const TIMER2 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4000a000));
-            ///  Real time counter 0
-            pub const RTC0 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x4000b000));
-            ///  Temperature Sensor
-            pub const TEMP = @as(*volatile types.peripherals.TEMP, @ptrFromInt(0x4000c000));
-            ///  Random Number Generator
-            pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x4000d000));
-            ///  AES ECB Mode Encryption
-            pub const ECB = @as(*volatile types.peripherals.ECB, @ptrFromInt(0x4000e000));
-            ///  Accelerated Address Resolver
-            pub const AAR = @as(*volatile types.peripherals.AAR, @ptrFromInt(0x4000f000));
-            ///  AES CCM Mode Encryption
-            pub const CCM = @as(*volatile types.peripherals.CCM, @ptrFromInt(0x4000f000));
-            ///  Watchdog Timer
-            pub const WDT = @as(*volatile types.peripherals.WDT, @ptrFromInt(0x40010000));
-            ///  Real time counter 1
-            pub const RTC1 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40011000));
-            ///  Quadrature Decoder
-            pub const QDEC = @as(*volatile types.peripherals.QDEC, @ptrFromInt(0x40012000));
-            ///  Comparator
-            pub const COMP = @as(*volatile types.peripherals.COMP, @ptrFromInt(0x40013000));
-            ///  Low Power Comparator
-            pub const LPCOMP = @as(*volatile types.peripherals.LPCOMP, @ptrFromInt(0x40013000));
-            ///  Event Generator Unit 0
-            pub const EGU0 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40014000));
-            ///  Software interrupt 0
-            pub const SWI0 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40014000));
-            ///  Event Generator Unit 1
-            pub const EGU1 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40015000));
-            ///  Software interrupt 1
-            pub const SWI1 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40015000));
-            ///  Event Generator Unit 2
-            pub const EGU2 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40016000));
-            ///  Software interrupt 2
-            pub const SWI2 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40016000));
-            ///  Event Generator Unit 3
-            pub const EGU3 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40017000));
-            ///  Software interrupt 3
-            pub const SWI3 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40017000));
-            ///  Event Generator Unit 4
-            pub const EGU4 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40018000));
-            ///  Software interrupt 4
-            pub const SWI4 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40018000));
-            ///  Event Generator Unit 5
-            pub const EGU5 = @as(*volatile types.peripherals.EGU0, @ptrFromInt(0x40019000));
-            ///  Software interrupt 5
-            pub const SWI5 = @as(*volatile types.peripherals.SWI0, @ptrFromInt(0x40019000));
-            ///  Timer/Counter 3
-            pub const TIMER3 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001a000));
-            ///  Timer/Counter 4
-            pub const TIMER4 = @as(*volatile types.peripherals.TIMER0, @ptrFromInt(0x4001b000));
-            ///  Pulse width modulation unit 0
-            pub const PWM0 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4001c000));
-            ///  Pulse Density Modulation (Digital Microphone) Interface
-            pub const PDM = @as(*volatile types.peripherals.PDM, @ptrFromInt(0x4001d000));
-            ///  Access control lists
-            pub const ACL = @as(*volatile types.peripherals.ACL, @ptrFromInt(0x4001e000));
-            ///  Non Volatile Memory Controller
-            pub const NVMC = @as(*volatile types.peripherals.NVMC, @ptrFromInt(0x4001e000));
-            ///  Programmable Peripheral Interconnect
-            pub const PPI = @as(*volatile types.peripherals.PPI, @ptrFromInt(0x4001f000));
-            ///  Memory Watch Unit
-            pub const MWU = @as(*volatile types.peripherals.MWU, @ptrFromInt(0x40020000));
-            ///  Pulse width modulation unit 1
-            pub const PWM1 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40021000));
-            ///  Pulse width modulation unit 2
-            pub const PWM2 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x40022000));
-            ///  Serial Peripheral Interface 2
-            pub const SPI2 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40023000));
-            ///  Serial Peripheral Interface Master with EasyDMA 2
-            pub const SPIM2 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x40023000));
-            ///  SPI Slave 2
-            pub const SPIS2 = @as(*volatile types.peripherals.SPIS0, @ptrFromInt(0x40023000));
-            ///  Real time counter 2
-            pub const RTC2 = @as(*volatile types.peripherals.RTC0, @ptrFromInt(0x40024000));
-            ///  Inter-IC Sound
-            pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x40025000));
-            ///  FPU
-            pub const FPU = @as(*volatile types.peripherals.FPU, @ptrFromInt(0x40026000));
-            ///  Universal serial bus device
-            pub const USBD = @as(*volatile types.peripherals.USBD, @ptrFromInt(0x40027000));
-            ///  UART with EasyDMA 1
-            pub const UARTE1 = @as(*volatile types.peripherals.UARTE0, @ptrFromInt(0x40028000));
-            ///  External flash interface
-            pub const QSPI = @as(*volatile types.peripherals.QSPI, @ptrFromInt(0x40029000));
-            ///  Pulse width modulation unit 3
-            pub const PWM3 = @as(*volatile types.peripherals.PWM0, @ptrFromInt(0x4002d000));
-            ///  Serial Peripheral Interface Master with EasyDMA 3
-            pub const SPIM3 = @as(*volatile types.peripherals.SPIM0, @ptrFromInt(0x4002f000));
-            ///  GPIO Port 1
-            pub const P0 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000000));
-            ///  GPIO Port 2
-            pub const P1 = @as(*volatile types.peripherals.P0, @ptrFromInt(0x50000300));
-            ///  CRYPTOCELL HOST_RGF interface
-            pub const CC_HOST_RGF = @as(*volatile types.peripherals.CC_HOST_RGF, @ptrFromInt(0x5002a000));
-            ///  ARM TrustZone CryptoCell register interface
-            pub const CRYPTOCELL = @as(*volatile types.peripherals.CRYPTOCELL, @ptrFromInt(0x5002a000));
-            ///  System Tick Timer
-            pub const SysTick = @as(*volatile types.peripherals.SCS.SysTick, @ptrFromInt(0xe000e010));
-        };
-    };
-};
-
-pub const types = struct {
-    pub const peripherals = struct {
-        ///  System Control Space
-        pub const SCS = struct {
-            ///  System Tick Timer
-            pub const SysTick = extern struct {
-                ///  SysTick Control and Status Register
-                CTRL: mmio.Mmio(packed struct(u32) {
-                    ENABLE: u1,
-                    TICKINT: u1,
-                    CLKSOURCE: u1,
-                    reserved16: u13,
-                    COUNTFLAG: u1,
-                    padding: u15,
-                }),
-                ///  SysTick Reload Value Register
-                LOAD: mmio.Mmio(packed struct(u32) {
-                    RELOAD: u24,
-                    padding: u8,
-                }),
-                ///  SysTick Current Value Register
-                VAL: mmio.Mmio(packed struct(u32) {
-                    CURRENT: u24,
-                    padding: u8,
-                }),
-                ///  SysTick Calibration Register
-                CALIB: mmio.Mmio(packed struct(u32) {
-                    TENMS: u24,
-                    reserved30: u6,
-                    SKEW: u1,
-                    NOREF: u1,
-                }),
-            };
-        };
-
-        ///  Factory information configuration registers
-        pub const FICR = extern struct {
-            reserved16: [16]u8,
-            ///  Code memory page size
-            CODEPAGESIZE: mmio.Mmio(packed struct(u32) {
-                ///  Code memory page size
-                CODEPAGESIZE: u32,
-            }),
-            ///  Code memory size
-            CODESIZE: mmio.Mmio(packed struct(u32) {
-                ///  Code memory size in number of pages
-                CODESIZE: u32,
-            }),
-            reserved96: [72]u8,
-            ///  Description collection: Device identifier
-            DEVICEID: [2]mmio.Mmio(packed struct(u32) {
-                ///  64 bit unique device identifier
-                DEVICEID: u32,
-            }),
-            reserved128: [24]u8,
-            ///  Description collection: Encryption root, word n
-            ER: [4]mmio.Mmio(packed struct(u32) {
-                ///  Encryption root, word n
-                ER: u32,
-            }),
-            ///  Description collection: Identity Root, word n
-            IR: [4]mmio.Mmio(packed struct(u32) {
-                ///  Identity Root, word n
-                IR: u32,
-            }),
-            ///  Device address type
-            DEVICEADDRTYPE: mmio.Mmio(packed struct(u32) {
-                ///  Device address type
-                DEVICEADDRTYPE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Public address
-                        Public = 0x0,
-                        ///  Random address
-                        Random = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Description collection: Device address n
-            DEVICEADDR: [2]mmio.Mmio(packed struct(u32) {
-                ///  48 bit device address
-                DEVICEADDR: u32,
-            }),
-            reserved848: [676]u8,
-            ///  Description collection: Production test signature n
-            PRODTEST: [3]mmio.Mmio(packed struct(u32) {
-                ///  Production test signature n
-                PRODTEST: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  Production tests done
-                        Done = 0xbb42319f,
-                        ///  Production tests not done
-                        NotDone = 0xffffffff,
-                        _,
-                    },
-                },
-            }),
-        };
-
-        ///  User information configuration registers
-        pub const UICR = extern struct {
-            reserved20: [20]u8,
-            ///  Description collection: Reserved for Nordic firmware design
-            NRFFW: [13]mmio.Mmio(packed struct(u32) {
-                ///  Reserved for Nordic firmware design
-                NRFFW: u32,
-            }),
-            reserved80: [8]u8,
-            ///  Description collection: Reserved for Nordic hardware design
-            NRFHW: [12]mmio.Mmio(packed struct(u32) {
-                ///  Reserved for Nordic hardware design
-                NRFHW: u32,
-            }),
-            ///  Description collection: Reserved for customer
-            CUSTOMER: [32]mmio.Mmio(packed struct(u32) {
-                ///  Reserved for customer
-                CUSTOMER: u32,
-            }),
-            reserved512: [256]u8,
-            ///  Description collection: Mapping of the nRESET function (see POWER chapter for details)
-            PSELRESET: [2]mmio.Mmio(packed struct(u32) {
-                ///  GPIO pin number onto which nRESET is exposed
-                PIN: u5,
-                ///  Port number onto which nRESET is exposed
-                PORT: u1,
-                reserved31: u25,
-                ///  Connection
-                CONNECT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disconnect
-                        Disconnected = 0x1,
-                        ///  Connect
-                        Connected = 0x0,
-                    },
-                },
-            }),
-            ///  Access port protection
-            APPROTECT: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable access port protection.
-                PALL: packed union {
-                    raw: u8,
-                    value: enum(u8) {
-                        ///  Disable
-                        Disabled = 0xff,
-                        ///  Enable
-                        Enabled = 0x0,
-                        _,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Setting of pins dedicated to NFC functionality: NFC antenna or GPIO
-            NFCPINS: mmio.Mmio(packed struct(u32) {
-                ///  Setting of pins dedicated to NFC functionality
-                PROTECT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Operation as GPIO pins. Same protection as normal GPIO pins
-                        Disabled = 0x0,
-                        ///  Operation as NFC antenna pins. Configures the protection for NFC operation
-                        NFC = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Processor debug control
-            DEBUGCTRL: mmio.Mmio(packed struct(u32) {
-                ///  Configure CPU non-intrusive debug features
-                CPUNIDEN: packed union {
-                    raw: u8,
-                    value: enum(u8) {
-                        ///  Enable CPU ITM and ETM functionality (default behavior)
-                        Enabled = 0xff,
-                        ///  Disable CPU ITM and ETM functionality
-                        Disabled = 0x0,
-                        _,
-                    },
-                },
-                ///  Configure CPU flash patch and breakpoint (FPB) unit behavior
-                CPUFPBEN: packed union {
-                    raw: u8,
-                    value: enum(u8) {
-                        ///  Enable CPU FPB unit (default behavior)
-                        Enabled = 0xff,
-                        ///  Disable CPU FPB unit. Writes into the FPB registers will be ignored.
-                        Disabled = 0x0,
-                        _,
-                    },
-                },
-                padding: u16,
-            }),
-            reserved772: [240]u8,
-            ///  GPIO reference voltage / external output supply voltage in high voltage mode
-            REGOUT0: mmio.Mmio(packed struct(u32) {
-                ///  Output voltage from of REG0 regulator stage. The maximum output voltage from this stage is given as VDDH - VEXDIF.
-                VOUT: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  1.8 V
-                        @"1V8" = 0x0,
-                        ///  2.1 V
-                        @"2V1" = 0x1,
-                        ///  2.4 V
-                        @"2V4" = 0x2,
-                        ///  2.7 V
-                        @"2V7" = 0x3,
-                        ///  3.0 V
-                        @"3V0" = 0x4,
-                        ///  3.3 V
-                        @"3V3" = 0x5,
-                        ///  Default voltage: 1.8 V
-                        DEFAULT = 0x7,
-                        _,
-                    },
-                },
-                padding: u29,
-            }),
-        };
-
-        ///  Clock control
-        pub const CLOCK = extern struct {
-            ///  Start HFXO crystal oscillator
-            TASKS_HFCLKSTART: mmio.Mmio(packed struct(u32) {
-                ///  Start HFXO crystal oscillator
-                TASKS_HFCLKSTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop HFXO crystal oscillator
-            TASKS_HFCLKSTOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop HFXO crystal oscillator
-                TASKS_HFCLKSTOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start LFCLK
-            TASKS_LFCLKSTART: mmio.Mmio(packed struct(u32) {
-                ///  Start LFCLK
-                TASKS_LFCLKSTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop LFCLK
-            TASKS_LFCLKSTOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop LFCLK
-                TASKS_LFCLKSTOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start calibration of LFRC
-            TASKS_CAL: mmio.Mmio(packed struct(u32) {
-                ///  Start calibration of LFRC
-                TASKS_CAL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start calibration timer
-            TASKS_CTSTART: mmio.Mmio(packed struct(u32) {
-                ///  Start calibration timer
-                TASKS_CTSTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop calibration timer
-            TASKS_CTSTOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop calibration timer
-                TASKS_CTSTOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [228]u8,
-            ///  HFXO crystal oscillator started
-            EVENTS_HFCLKSTARTED: mmio.Mmio(packed struct(u32) {
-                ///  HFXO crystal oscillator started
-                EVENTS_HFCLKSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  LFCLK started
-            EVENTS_LFCLKSTARTED: mmio.Mmio(packed struct(u32) {
-                ///  LFCLK started
-                EVENTS_LFCLKSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved268: [4]u8,
-            ///  Calibration of LFRC completed
-            EVENTS_DONE: mmio.Mmio(packed struct(u32) {
-                ///  Calibration of LFRC completed
-                EVENTS_DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Calibration timer timeout
-            EVENTS_CTTO: mmio.Mmio(packed struct(u32) {
-                ///  Calibration timer timeout
-                EVENTS_CTTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved296: [20]u8,
-            ///  Calibration timer has been started and is ready to process new tasks
-            EVENTS_CTSTARTED: mmio.Mmio(packed struct(u32) {
-                ///  Calibration timer has been started and is ready to process new tasks
-                EVENTS_CTSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Calibration timer has been stopped and is ready to process new tasks
-            EVENTS_CTSTOPPED: mmio.Mmio(packed struct(u32) {
-                ///  Calibration timer has been stopped and is ready to process new tasks
-                EVENTS_CTSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [468]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event HFCLKSTARTED
-                HFCLKSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event LFCLKSTARTED
-                LFCLKSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved3: u1,
-                ///  Write '1' to enable interrupt for event DONE
-                DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CTTO
-                CTTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u5,
-                ///  Write '1' to enable interrupt for event CTSTARTED
-                CTSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CTSTOPPED
-                CTSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u20,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event HFCLKSTARTED
-                HFCLKSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event LFCLKSTARTED
-                LFCLKSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved3: u1,
-                ///  Write '1' to disable interrupt for event DONE
-                DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CTTO
-                CTTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u5,
-                ///  Write '1' to disable interrupt for event CTSTARTED
-                CTSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CTSTOPPED
-                CTSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u20,
-            }),
-            reserved1032: [252]u8,
-            ///  Status indicating that HFCLKSTART task has been triggered
-            HFCLKRUN: mmio.Mmio(packed struct(u32) {
-                ///  HFCLKSTART task triggered or not
-                STATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Task not triggered
-                        NotTriggered = 0x0,
-                        ///  Task triggered
-                        Triggered = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  HFCLK status
-            HFCLKSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Source of HFCLK
-                SRC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  64 MHz internal oscillator (HFINT)
-                        RC = 0x0,
-                        ///  64 MHz crystal oscillator (HFXO)
-                        Xtal = 0x1,
-                    },
-                },
-                reserved16: u15,
-                ///  HFCLK state
-                STATE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  HFCLK not running
-                        NotRunning = 0x0,
-                        ///  HFCLK running
-                        Running = 0x1,
-                    },
-                },
-                padding: u15,
-            }),
-            reserved1044: [4]u8,
-            ///  Status indicating that LFCLKSTART task has been triggered
-            LFCLKRUN: mmio.Mmio(packed struct(u32) {
-                ///  LFCLKSTART task triggered or not
-                STATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Task not triggered
-                        NotTriggered = 0x0,
-                        ///  Task triggered
-                        Triggered = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  LFCLK status
-            LFCLKSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Source of LFCLK
-                SRC: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  32.768 kHz RC oscillator (LFRC)
-                        RC = 0x0,
-                        ///  32.768 kHz crystal oscillator (LFXO)
-                        Xtal = 0x1,
-                        ///  32.768 kHz synthesized from HFCLK (LFSYNT)
-                        Synth = 0x2,
-                        _,
-                    },
-                },
-                reserved16: u14,
-                ///  LFCLK state
-                STATE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  LFCLK not running
-                        NotRunning = 0x0,
-                        ///  LFCLK running
-                        Running = 0x1,
-                    },
-                },
-                padding: u15,
-            }),
-            ///  Copy of LFCLKSRC register, set when LFCLKSTART task was triggered
-            LFCLKSRCCOPY: mmio.Mmio(packed struct(u32) {
-                ///  Clock source
-                SRC: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  32.768 kHz RC oscillator (LFRC)
-                        RC = 0x0,
-                        ///  32.768 kHz crystal oscillator (LFXO)
-                        Xtal = 0x1,
-                        ///  32.768 kHz synthesized from HFCLK (LFSYNT)
-                        Synth = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1304: [248]u8,
-            ///  Clock source for the LFCLK
-            LFCLKSRC: mmio.Mmio(packed struct(u32) {
-                ///  Clock source
-                SRC: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  32.768 kHz RC oscillator (LFRC)
-                        RC = 0x0,
-                        ///  32.768 kHz crystal oscillator (LFXO)
-                        Xtal = 0x1,
-                        ///  32.768 kHz synthesized from HFCLK (LFSYNT)
-                        Synth = 0x2,
-                        _,
-                    },
-                },
-                reserved16: u14,
-                ///  Enable or disable bypass of LFCLK crystal oscillator with external clock source
-                BYPASS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable (use with Xtal or low-swing external source)
-                        Disabled = 0x0,
-                        ///  Enable (use with rail-to-rail external source)
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable external source for LFCLK
-                EXTERNAL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable external source (use with Xtal)
-                        Disabled = 0x0,
-                        ///  Enable use of external source instead of Xtal (SRC needs to be set to Xtal)
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u14,
-            }),
-            reserved1320: [12]u8,
-            ///  HFXO debounce time. The HFXO is started by triggering the TASKS_HFCLKSTART task.
-            HFXODEBOUNCE: mmio.Mmio(packed struct(u32) {
-                ///  HFXO debounce time. Debounce time = HFXODEBOUNCE * 16 us.
-                HFXODEBOUNCE: packed union {
-                    raw: u8,
-                    value: enum(u8) {
-                        ///  256 us debounce time. Recommended for TSX-3225, FA-20H and FA-128 crystals.
-                        Db256us = 0x10,
-                        ///  1024 us debounce time. Recommended for NX1612AA and NX1210AB crystals.
-                        Db1024us = 0x40,
-                        _,
-                    },
-                },
-                padding: u24,
-            }),
-            reserved1336: [12]u8,
-            ///  Calibration timer interval
-            CTIV: mmio.Mmio(packed struct(u32) {
-                ///  Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds.
-                CTIV: u7,
-                padding: u25,
-            }),
-            reserved1372: [32]u8,
-            ///  Clocking options for the trace port debug interface
-            TRACECONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Speed of trace port clock. Note that the TRACECLK pin will output this clock divided by two.
-                TRACEPORTSPEED: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  32 MHz trace port clock (TRACECLK = 16 MHz)
-                        @"32MHz" = 0x0,
-                        ///  16 MHz trace port clock (TRACECLK = 8 MHz)
-                        @"16MHz" = 0x1,
-                        ///  8 MHz trace port clock (TRACECLK = 4 MHz)
-                        @"8MHz" = 0x2,
-                        ///  4 MHz trace port clock (TRACECLK = 2 MHz)
-                        @"4MHz" = 0x3,
-                    },
-                },
-                reserved16: u14,
-                ///  Pin multiplexing of trace signals. See pin assignment chapter for more details.
-                TRACEMUX: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  No trace signals routed to pins. All pins can be used as regular GPIOs.
-                        GPIO = 0x0,
-                        ///  SWO trace signal routed to pin. Remaining pins can be used as regular GPIOs.
-                        Serial = 0x1,
-                        ///  All trace signals (TRACECLK and TRACEDATA[n]) routed to pins.
-                        Parallel = 0x2,
-                        _,
-                    },
-                },
-                padding: u14,
-            }),
-            reserved1460: [84]u8,
-            ///  LFRC mode configuration
-            LFRCMODE: mmio.Mmio(packed struct(u32) {
-                ///  Set LFRC mode
-                MODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Normal mode
-                        Normal = 0x0,
-                        ///  Ultra-low power mode (ULP)
-                        ULP = 0x1,
-                    },
-                },
-                reserved16: u15,
-                ///  Active LFRC mode. This field is read only.
-                STATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Normal mode
-                        Normal = 0x0,
-                        ///  Ultra-low power mode (ULP)
-                        ULP = 0x1,
-                    },
-                },
-                padding: u15,
-            }),
-        };
-
-        ///  Power control
-        pub const POWER = extern struct {
-            reserved120: [120]u8,
-            ///  Enable Constant Latency mode
-            TASKS_CONSTLAT: mmio.Mmio(packed struct(u32) {
-                ///  Enable Constant Latency mode
-                TASKS_CONSTLAT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Enable Low-power mode (variable latency)
-            TASKS_LOWPWR: mmio.Mmio(packed struct(u32) {
-                ///  Enable Low-power mode (variable latency)
-                TASKS_LOWPWR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved264: [136]u8,
-            ///  Power failure warning
-            EVENTS_POFWARN: mmio.Mmio(packed struct(u32) {
-                ///  Power failure warning
-                EVENTS_POFWARN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved276: [8]u8,
-            ///  CPU entered WFI/WFE sleep
-            EVENTS_SLEEPENTER: mmio.Mmio(packed struct(u32) {
-                ///  CPU entered WFI/WFE sleep
-                EVENTS_SLEEPENTER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  CPU exited WFI/WFE sleep
-            EVENTS_SLEEPEXIT: mmio.Mmio(packed struct(u32) {
-                ///  CPU exited WFI/WFE sleep
-                EVENTS_SLEEPEXIT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Voltage supply detected on VBUS
-            EVENTS_USBDETECTED: mmio.Mmio(packed struct(u32) {
-                ///  Voltage supply detected on VBUS
-                EVENTS_USBDETECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Voltage supply removed from VBUS
-            EVENTS_USBREMOVED: mmio.Mmio(packed struct(u32) {
-                ///  Voltage supply removed from VBUS
-                EVENTS_USBREMOVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  USB 3.3 V supply ready
-            EVENTS_USBPWRRDY: mmio.Mmio(packed struct(u32) {
-                ///  USB 3.3 V supply ready
-                EVENTS_USBPWRRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [476]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Write '1' to enable interrupt for event POFWARN
-                POFWARN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved5: u2,
-                ///  Write '1' to enable interrupt for event SLEEPENTER
-                SLEEPENTER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event SLEEPEXIT
-                SLEEPEXIT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event USBDETECTED
-                USBDETECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event USBREMOVED
-                USBREMOVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event USBPWRRDY
-                USBPWRRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u22,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Write '1' to disable interrupt for event POFWARN
-                POFWARN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved5: u2,
-                ///  Write '1' to disable interrupt for event SLEEPENTER
-                SLEEPENTER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event SLEEPEXIT
-                SLEEPEXIT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event USBDETECTED
-                USBDETECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event USBREMOVED
-                USBREMOVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event USBPWRRDY
-                USBPWRRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u22,
-            }),
-            reserved1024: [244]u8,
-            ///  Reset reason
-            RESETREAS: mmio.Mmio(packed struct(u32) {
-                ///  Reset from pin-reset detected
-                RESETPIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset from watchdog detected
-                DOG: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset from soft reset detected
-                SREQ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset from CPU lock-up detected
-                LOCKUP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                reserved16: u12,
-                ///  Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO
-                OFF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP
-                LPCOMP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode
-                DIF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset due to wake up from System OFF mode by NFC field detect
-                NFC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Reset due to wake up from System OFF mode by VBUS rising into valid range
-                VBUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not detected
-                        NotDetected = 0x0,
-                        ///  Detected
-                        Detected = 0x1,
-                    },
-                },
-                padding: u11,
-            }),
-            reserved1064: [36]u8,
-            ///  Deprecated register - RAM status register
-            RAMSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  RAM block 0 is on or off/powering up
-                RAMBLOCK0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        Off = 0x0,
-                        ///  On
-                        On = 0x1,
-                    },
-                },
-                ///  RAM block 1 is on or off/powering up
-                RAMBLOCK1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        Off = 0x0,
-                        ///  On
-                        On = 0x1,
-                    },
-                },
-                ///  RAM block 2 is on or off/powering up
-                RAMBLOCK2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        Off = 0x0,
-                        ///  On
-                        On = 0x1,
-                    },
-                },
-                ///  RAM block 3 is on or off/powering up
-                RAMBLOCK3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Off
-                        Off = 0x0,
-                        ///  On
-                        On = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1080: [12]u8,
-            ///  USB supply status
-            USBREGSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  VBUS input detection status (USBDETECTED and USBREMOVED events are derived from this information)
-                VBUSDETECT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  VBUS voltage below valid threshold
-                        NoVbus = 0x0,
-                        ///  VBUS voltage above valid threshold
-                        VbusPresent = 0x1,
-                    },
-                },
-                ///  USB supply output settling time elapsed
-                OUTPUTRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  USBREG output settling time not elapsed
-                        NotReady = 0x0,
-                        ///  USBREG output settling time elapsed (same information as USBPWRRDY event)
-                        Ready = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1280: [196]u8,
-            ///  System OFF register
-            SYSTEMOFF: mmio.Mmio(packed struct(u32) {
-                ///  Enable System OFF mode
-                SYSTEMOFF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Enable System OFF mode
-                        Enter = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1296: [12]u8,
-            ///  Power-fail comparator configuration
-            POFCON: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable power failure warning
-                POF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Power-fail comparator threshold setting. This setting applies both for normal voltage mode (supply connected to both VDD and VDDH) and high voltage mode (supply connected to VDDH only). Values 0-3 set threshold below 1.7 V and should not be used as brown out detection will be activated before power failure warning on such low voltages.
-                THRESHOLD: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Set threshold to 1.7 V
-                        V17 = 0x4,
-                        ///  Set threshold to 1.8 V
-                        V18 = 0x5,
-                        ///  Set threshold to 1.9 V
-                        V19 = 0x6,
-                        ///  Set threshold to 2.0 V
-                        V20 = 0x7,
-                        ///  Set threshold to 2.1 V
-                        V21 = 0x8,
-                        ///  Set threshold to 2.2 V
-                        V22 = 0x9,
-                        ///  Set threshold to 2.3 V
-                        V23 = 0xa,
-                        ///  Set threshold to 2.4 V
-                        V24 = 0xb,
-                        ///  Set threshold to 2.5 V
-                        V25 = 0xc,
-                        ///  Set threshold to 2.6 V
-                        V26 = 0xd,
-                        ///  Set threshold to 2.7 V
-                        V27 = 0xe,
-                        ///  Set threshold to 2.8 V
-                        V28 = 0xf,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                ///  Power-fail comparator threshold setting for high voltage mode (supply connected to VDDH only). This setting does not apply for normal voltage mode (supply connected to both VDD and VDDH).
-                THRESHOLDVDDH: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Set threshold to 2.7 V
-                        V27 = 0x0,
-                        ///  Set threshold to 2.8 V
-                        V28 = 0x1,
-                        ///  Set threshold to 2.9 V
-                        V29 = 0x2,
-                        ///  Set threshold to 3.0 V
-                        V30 = 0x3,
-                        ///  Set threshold to 3.1 V
-                        V31 = 0x4,
-                        ///  Set threshold to 3.2 V
-                        V32 = 0x5,
-                        ///  Set threshold to 3.3 V
-                        V33 = 0x6,
-                        ///  Set threshold to 3.4 V
-                        V34 = 0x7,
-                        ///  Set threshold to 3.5 V
-                        V35 = 0x8,
-                        ///  Set threshold to 3.6 V
-                        V36 = 0x9,
-                        ///  Set threshold to 3.7 V
-                        V37 = 0xa,
-                        ///  Set threshold to 3.8 V
-                        V38 = 0xb,
-                        ///  Set threshold to 3.9 V
-                        V39 = 0xc,
-                        ///  Set threshold to 4.0 V
-                        V40 = 0xd,
-                        ///  Set threshold to 4.1 V
-                        V41 = 0xe,
-                        ///  Set threshold to 4.2 V
-                        V42 = 0xf,
-                    },
-                },
-                padding: u20,
-            }),
-            reserved1308: [8]u8,
-            ///  General purpose retention register
-            GPREGRET: mmio.Mmio(packed struct(u32) {
-                ///  General purpose retention register
-                GPREGRET: u8,
-                padding: u24,
-            }),
-            ///  General purpose retention register
-            GPREGRET2: mmio.Mmio(packed struct(u32) {
-                ///  General purpose retention register
-                GPREGRET: u8,
-                padding: u24,
-            }),
-            reserved1400: [84]u8,
-            ///  Enable DC/DC converter for REG1 stage
-            DCDCEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable DC/DC converter for REG1 stage.
-                DCDCEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1408: [4]u8,
-            ///  Enable DC/DC converter for REG0 stage
-            DCDCEN0: mmio.Mmio(packed struct(u32) {
-                ///  Enable DC/DC converter for REG0 stage.
-                DCDCEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1600: [188]u8,
-            ///  Main supply status
-            MAINREGSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  Main supply status
-                MAINREGSTATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Normal voltage mode. Voltage supplied on VDD.
-                        Normal = 0x0,
-                        ///  High voltage mode. Voltage supplied on VDDH.
-                        High = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  GPIO Port 1
-        pub const P0 = extern struct {
-            reserved1284: [1284]u8,
-            ///  Write GPIO port
-            OUT: mmio.Mmio(packed struct(u32) {
-                ///  Pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin driver is low
-                        Low = 0x0,
-                        ///  Pin driver is high
-                        High = 0x1,
-                    },
-                },
-            }),
-            ///  Set individual bits in GPIO port
-            OUTSET: mmio.Mmio(packed struct(u32) {
-                ///  Pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-            }),
-            ///  Clear individual bits in GPIO port
-            OUTCLR: mmio.Mmio(packed struct(u32) {
-                ///  Pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin driver is low
-                        Low = 0x0,
-                        ///  Read: pin driver is high
-                        High = 0x1,
-                    },
-                },
-            }),
-            ///  Read GPIO port
-            IN: mmio.Mmio(packed struct(u32) {
-                ///  Pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-                ///  Pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin input is low
-                        Low = 0x0,
-                        ///  Pin input is high
-                        High = 0x1,
-                    },
-                },
-            }),
-            ///  Direction of GPIO pins
-            DIR: mmio.Mmio(packed struct(u32) {
-                ///  Pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pin set as input
-                        Input = 0x0,
-                        ///  Pin set as output
-                        Output = 0x1,
-                    },
-                },
-            }),
-            ///  DIR set register
-            DIRSET: mmio.Mmio(packed struct(u32) {
-                ///  Set as output pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as output pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-            }),
-            ///  DIR clear register
-            DIRCLR: mmio.Mmio(packed struct(u32) {
-                ///  Set as input pin 0
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 1
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 2
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 3
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 4
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 5
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 6
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 7
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 8
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 9
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 10
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 11
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 12
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 13
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 14
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 15
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 16
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 17
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 18
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 19
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 20
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 21
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 22
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 23
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 24
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 25
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 26
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 27
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 28
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 29
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 30
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-                ///  Set as input pin 31
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: pin set as input
-                        Input = 0x0,
-                        ///  Read: pin set as output
-                        Output = 0x1,
-                    },
-                },
-            }),
-            ///  Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers
-            LATCH: mmio.Mmio(packed struct(u32) {
-                ///  Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear.
-                PIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear.
-                PIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear.
-                PIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear.
-                PIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear.
-                PIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear.
-                PIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear.
-                PIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear.
-                PIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear.
-                PIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear.
-                PIN9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear.
-                PIN10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear.
-                PIN11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear.
-                PIN12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear.
-                PIN13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear.
-                PIN14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear.
-                PIN15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear.
-                PIN16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear.
-                PIN17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear.
-                PIN18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear.
-                PIN19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear.
-                PIN20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear.
-                PIN21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear.
-                PIN22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear.
-                PIN23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear.
-                PIN24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear.
-                PIN25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear.
-                PIN26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear.
-                PIN27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear.
-                PIN28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear.
-                PIN29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear.
-                PIN30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-                ///  Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear.
-                PIN31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Criteria has not been met
-                        NotLatched = 0x0,
-                        ///  Criteria has been met
-                        Latched = 0x1,
-                    },
-                },
-            }),
-            ///  Select between default DETECT signal behaviour and LDETECT mode
-            DETECTMODE: mmio.Mmio(packed struct(u32) {
-                ///  Select between default DETECT signal behaviour and LDETECT mode
-                DETECTMODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  DETECT directly connected to PIN DETECT signals
-                        Default = 0x0,
-                        ///  Use the latched LDETECT behaviour
-                        LDETECT = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1792: [472]u8,
-            ///  Description collection: Configuration of GPIO pins
-            PIN_CNF: [32]mmio.Mmio(packed struct(u32) {
-                ///  Pin direction. Same physical register as DIR register
-                DIR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Configure pin as an input pin
-                        Input = 0x0,
-                        ///  Configure pin as an output pin
-                        Output = 0x1,
-                    },
-                },
-                ///  Connect or disconnect input buffer
-                INPUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Connect input buffer
-                        Connect = 0x0,
-                        ///  Disconnect input buffer
-                        Disconnect = 0x1,
-                    },
-                },
-                ///  Pull configuration
-                PULL: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  No pull
-                        Disabled = 0x0,
-                        ///  Pull down on pin
-                        Pulldown = 0x1,
-                        ///  Pull up on pin
-                        Pullup = 0x3,
-                        _,
-                    },
-                },
-                reserved8: u4,
-                ///  Drive configuration
-                DRIVE: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Standard '0', standard '1'
-                        S0S1 = 0x0,
-                        ///  High drive '0', standard '1'
-                        H0S1 = 0x1,
-                        ///  Standard '0', high drive '1'
-                        S0H1 = 0x2,
-                        ///  High drive '0', high 'drive '1''
-                        H0H1 = 0x3,
-                        ///  Disconnect '0' standard '1' (normally used for wired-or connections)
-                        D0S1 = 0x4,
-                        ///  Disconnect '0', high drive '1' (normally used for wired-or connections)
-                        D0H1 = 0x5,
-                        ///  Standard '0'. disconnect '1' (normally used for wired-and connections)
-                        S0D1 = 0x6,
-                        ///  High drive '0', disconnect '1' (normally used for wired-and connections)
-                        H0D1 = 0x7,
-                    },
-                },
-                reserved16: u5,
-                ///  Pin sensing mechanism
-                SENSE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Sense for high level
-                        High = 0x2,
-                        ///  Sense for low level
-                        Low = 0x3,
-                        _,
-                    },
-                },
-                padding: u14,
-            }),
-        };
-
-        ///  Access control lists
-        pub const ACL = struct {};
-
-        ///  2.4 GHz radio
-        pub const RADIO = extern struct {
-            ///  Enable RADIO in TX mode
-            TASKS_TXEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable RADIO in TX mode
-                TASKS_TXEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Enable RADIO in RX mode
-            TASKS_RXEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable RADIO in RX mode
-                TASKS_RXEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start RADIO
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Start RADIO
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop RADIO
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop RADIO
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Disable RADIO
-            TASKS_DISABLE: mmio.Mmio(packed struct(u32) {
-                ///  Disable RADIO
-                TASKS_DISABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start the RSSI and take one single sample of the receive signal strength
-            TASKS_RSSISTART: mmio.Mmio(packed struct(u32) {
-                ///  Start the RSSI and take one single sample of the receive signal strength
-                TASKS_RSSISTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop the RSSI measurement
-            TASKS_RSSISTOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop the RSSI measurement
-                TASKS_RSSISTOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start the bit counter
-            TASKS_BCSTART: mmio.Mmio(packed struct(u32) {
-                ///  Start the bit counter
-                TASKS_BCSTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop the bit counter
-            TASKS_BCSTOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop the bit counter
-                TASKS_BCSTOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start the energy detect measurement used in IEEE 802.15.4 mode
-            TASKS_EDSTART: mmio.Mmio(packed struct(u32) {
-                ///  Start the energy detect measurement used in IEEE 802.15.4 mode
-                TASKS_EDSTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop the energy detect measurement
-            TASKS_EDSTOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop the energy detect measurement
-                TASKS_EDSTOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start the clear channel assessment used in IEEE 802.15.4 mode
-            TASKS_CCASTART: mmio.Mmio(packed struct(u32) {
-                ///  Start the clear channel assessment used in IEEE 802.15.4 mode
-                TASKS_CCASTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop the clear channel assessment
-            TASKS_CCASTOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop the clear channel assessment
-                TASKS_CCASTOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [204]u8,
-            ///  RADIO has ramped up and is ready to be started
-            EVENTS_READY: mmio.Mmio(packed struct(u32) {
-                ///  RADIO has ramped up and is ready to be started
-                EVENTS_READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Address sent or received
-            EVENTS_ADDRESS: mmio.Mmio(packed struct(u32) {
-                ///  Address sent or received
-                EVENTS_ADDRESS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Packet payload sent or received
-            EVENTS_PAYLOAD: mmio.Mmio(packed struct(u32) {
-                ///  Packet payload sent or received
-                EVENTS_PAYLOAD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Packet sent or received
-            EVENTS_END: mmio.Mmio(packed struct(u32) {
-                ///  Packet sent or received
-                EVENTS_END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  RADIO has been disabled
-            EVENTS_DISABLED: mmio.Mmio(packed struct(u32) {
-                ///  RADIO has been disabled
-                EVENTS_DISABLED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  A device address match occurred on the last received packet
-            EVENTS_DEVMATCH: mmio.Mmio(packed struct(u32) {
-                ///  A device address match occurred on the last received packet
-                EVENTS_DEVMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  No device address match occurred on the last received packet
-            EVENTS_DEVMISS: mmio.Mmio(packed struct(u32) {
-                ///  No device address match occurred on the last received packet
-                EVENTS_DEVMISS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Sampling of receive signal strength complete
-            EVENTS_RSSIEND: mmio.Mmio(packed struct(u32) {
-                ///  Sampling of receive signal strength complete
-                EVENTS_RSSIEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved296: [8]u8,
-            ///  Bit counter reached bit count value
-            EVENTS_BCMATCH: mmio.Mmio(packed struct(u32) {
-                ///  Bit counter reached bit count value
-                EVENTS_BCMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved304: [4]u8,
-            ///  Packet received with CRC ok
-            EVENTS_CRCOK: mmio.Mmio(packed struct(u32) {
-                ///  Packet received with CRC ok
-                EVENTS_CRCOK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Packet received with CRC error
-            EVENTS_CRCERROR: mmio.Mmio(packed struct(u32) {
-                ///  Packet received with CRC error
-                EVENTS_CRCERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  IEEE 802.15.4 length field received
-            EVENTS_FRAMESTART: mmio.Mmio(packed struct(u32) {
-                ///  IEEE 802.15.4 length field received
-                EVENTS_FRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.
-            EVENTS_EDEND: mmio.Mmio(packed struct(u32) {
-                ///  Sampling of energy detection complete. A new ED sample is ready for readout from the RADIO.EDSAMPLE register.
-                EVENTS_EDEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  The sampling of energy detection has stopped
-            EVENTS_EDSTOPPED: mmio.Mmio(packed struct(u32) {
-                ///  The sampling of energy detection has stopped
-                EVENTS_EDSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Wireless medium in idle - clear to send
-            EVENTS_CCAIDLE: mmio.Mmio(packed struct(u32) {
-                ///  Wireless medium in idle - clear to send
-                EVENTS_CCAIDLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Wireless medium busy - do not send
-            EVENTS_CCABUSY: mmio.Mmio(packed struct(u32) {
-                ///  Wireless medium busy - do not send
-                EVENTS_CCABUSY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  The CCA has stopped
-            EVENTS_CCASTOPPED: mmio.Mmio(packed struct(u32) {
-                ///  The CCA has stopped
-                EVENTS_CCASTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
-            EVENTS_RATEBOOST: mmio.Mmio(packed struct(u32) {
-                ///  Ble_LR CI field received, receive mode is changed from Ble_LR125Kbit to Ble_LR500Kbit.
-                EVENTS_RATEBOOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  RADIO has ramped up and is ready to be started TX path
-            EVENTS_TXREADY: mmio.Mmio(packed struct(u32) {
-                ///  RADIO has ramped up and is ready to be started TX path
-                EVENTS_TXREADY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  RADIO has ramped up and is ready to be started RX path
-            EVENTS_RXREADY: mmio.Mmio(packed struct(u32) {
-                ///  RADIO has ramped up and is ready to be started RX path
-                EVENTS_RXREADY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  MAC header match found
-            EVENTS_MHRMATCH: mmio.Mmio(packed struct(u32) {
-                ///  MAC header match found
-                EVENTS_MHRMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved360: [8]u8,
-            ///  Preamble indicator.
-            EVENTS_SYNC: mmio.Mmio(packed struct(u32) {
-                ///  Preamble indicator.
-                EVENTS_SYNC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air.
-            EVENTS_PHYEND: mmio.Mmio(packed struct(u32) {
-                ///  Generated in Ble_LR125Kbit, Ble_LR500Kbit and Ieee802154_250Kbit modes when last bit is sent on air.
-                EVENTS_PHYEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [144]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between event READY and task START
-                READY_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event END and task DISABLE
-                END_DISABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event DISABLED and task TXEN
-                DISABLED_TXEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event DISABLED and task RXEN
-                DISABLED_RXEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event ADDRESS and task RSSISTART
-                ADDRESS_RSSISTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event END and task START
-                END_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event ADDRESS and task BCSTART
-                ADDRESS_BCSTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                reserved8: u1,
-                ///  Shortcut between event DISABLED and task RSSISTOP
-                DISABLED_RSSISTOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                reserved11: u2,
-                ///  Shortcut between event RXREADY and task CCASTART
-                RXREADY_CCASTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event CCAIDLE and task TXEN
-                CCAIDLE_TXEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event CCABUSY and task DISABLE
-                CCABUSY_DISABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event FRAMESTART and task BCSTART
-                FRAMESTART_BCSTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event READY and task EDSTART
-                READY_EDSTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event EDEND and task DISABLE
-                EDEND_DISABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event CCAIDLE and task STOP
-                CCAIDLE_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event TXREADY and task START
-                TXREADY_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event RXREADY and task START
-                RXREADY_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event PHYEND and task DISABLE
-                PHYEND_DISABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event PHYEND and task START
-                PHYEND_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u10,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ADDRESS
-                ADDRESS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event PAYLOAD
-                PAYLOAD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event DISABLED
-                DISABLED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event DEVMATCH
-                DEVMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event DEVMISS
-                DEVMISS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event RSSIEND
-                RSSIEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u2,
-                ///  Write '1' to enable interrupt for event BCMATCH
-                BCMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved12: u1,
-                ///  Write '1' to enable interrupt for event CRCOK
-                CRCOK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CRCERROR
-                CRCERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event FRAMESTART
-                FRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event EDEND
-                EDEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event EDSTOPPED
-                EDSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CCAIDLE
-                CCAIDLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CCABUSY
-                CCABUSY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CCASTOPPED
-                CCASTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event RATEBOOST
-                RATEBOOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TXREADY
-                TXREADY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event RXREADY
-                RXREADY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event MHRMATCH
-                MHRMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved26: u2,
-                ///  Write '1' to enable interrupt for event SYNC
-                SYNC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event PHYEND
-                PHYEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ADDRESS
-                ADDRESS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event PAYLOAD
-                PAYLOAD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event DISABLED
-                DISABLED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event DEVMATCH
-                DEVMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event DEVMISS
-                DEVMISS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event RSSIEND
-                RSSIEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u2,
-                ///  Write '1' to disable interrupt for event BCMATCH
-                BCMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved12: u1,
-                ///  Write '1' to disable interrupt for event CRCOK
-                CRCOK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CRCERROR
-                CRCERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event FRAMESTART
-                FRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event EDEND
-                EDEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event EDSTOPPED
-                EDSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CCAIDLE
-                CCAIDLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CCABUSY
-                CCABUSY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CCASTOPPED
-                CCASTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event RATEBOOST
-                RATEBOOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TXREADY
-                TXREADY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event RXREADY
-                RXREADY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event MHRMATCH
-                MHRMATCH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved26: u2,
-                ///  Write '1' to disable interrupt for event SYNC
-                SYNC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event PHYEND
-                PHYEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            reserved1024: [244]u8,
-            ///  CRC status
-            CRCSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  CRC status of packet received
-                CRCSTATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Packet received with CRC error
-                        CRCError = 0x0,
-                        ///  Packet received with CRC ok
-                        CRCOk = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1032: [4]u8,
-            ///  Received address
-            RXMATCH: mmio.Mmio(packed struct(u32) {
-                ///  Received address
-                RXMATCH: u3,
-                padding: u29,
-            }),
-            ///  CRC field of previously received packet
-            RXCRC: mmio.Mmio(packed struct(u32) {
-                ///  CRC field of previously received packet
-                RXCRC: u24,
-                padding: u8,
-            }),
-            ///  Device address match index
-            DAI: mmio.Mmio(packed struct(u32) {
-                ///  Device address match index
-                DAI: u3,
-                padding: u29,
-            }),
-            ///  Payload status
-            PDUSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Status on payload length vs. PCNF1.MAXLEN
-                PDUSTAT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Payload less than PCNF1.MAXLEN
-                        LessThan = 0x0,
-                        ///  Payload greater than PCNF1.MAXLEN
-                        GreaterThan = 0x1,
-                    },
-                },
-                ///  Status on what rate packet is received with in Long Range
-                CISTAT: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Frame is received at 125kbps
-                        LR125kbit = 0x0,
-                        ///  Frame is received at 500kbps
-                        LR500kbit = 0x1,
-                        _,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1284: [236]u8,
-            ///  Packet pointer
-            PACKETPTR: mmio.Mmio(packed struct(u32) {
-                ///  Packet pointer
-                PACKETPTR: u32,
-            }),
-            ///  Frequency
-            FREQUENCY: mmio.Mmio(packed struct(u32) {
-                ///  Radio channel frequency
-                FREQUENCY: u7,
-                reserved8: u1,
-                ///  Channel map selection.
-                MAP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Channel map between 2400 MHZ .. 2500 MHz
-                        Default = 0x0,
-                        ///  Channel map between 2360 MHZ .. 2460 MHz
-                        Low = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            ///  Output power
-            TXPOWER: mmio.Mmio(packed struct(u32) {
-                ///  RADIO output power
-                TXPOWER: packed union {
-                    raw: u8,
-                    value: enum(u8) {
-                        ///  +8 dBm
-                        Pos8dBm = 0x8,
-                        ///  +7 dBm
-                        Pos7dBm = 0x7,
-                        ///  +6 dBm
-                        Pos6dBm = 0x6,
-                        ///  +5 dBm
-                        Pos5dBm = 0x5,
-                        ///  +4 dBm
-                        Pos4dBm = 0x4,
-                        ///  +3 dBm
-                        Pos3dBm = 0x3,
-                        ///  +2 dBm
-                        Pos2dBm = 0x2,
-                        ///  0 dBm
-                        @"0dBm" = 0x0,
-                        ///  -4 dBm
-                        Neg4dBm = 0xfc,
-                        ///  -8 dBm
-                        Neg8dBm = 0xf8,
-                        ///  -12 dBm
-                        Neg12dBm = 0xf4,
-                        ///  -16 dBm
-                        Neg16dBm = 0xf0,
-                        ///  -20 dBm
-                        Neg20dBm = 0xec,
-                        ///  Deprecated enumerator - -40 dBm
-                        Neg30dBm = 0xe2,
-                        ///  -40 dBm
-                        Neg40dBm = 0xd8,
-                        _,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Data rate and modulation
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Radio data rate and modulation setting. The radio supports frequency-shift keying (FSK) modulation.
-                MODE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  1 Mbit/s Nordic proprietary radio mode
-                        Nrf_1Mbit = 0x0,
-                        ///  2 Mbit/s Nordic proprietary radio mode
-                        Nrf_2Mbit = 0x1,
-                        ///  1 Mbit/s BLE
-                        Ble_1Mbit = 0x3,
-                        ///  2 Mbit/s BLE
-                        Ble_2Mbit = 0x4,
-                        ///  Long range 125 kbit/s TX, 125 kbit/s and 500 kbit/s RX
-                        Ble_LR125Kbit = 0x5,
-                        ///  Long range 500 kbit/s TX, 125 kbit/s and 500 kbit/s RX
-                        Ble_LR500Kbit = 0x6,
-                        ///  IEEE 802.15.4-2006 250 kbit/s
-                        Ieee802154_250Kbit = 0xf,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Packet configuration register 0
-            PCNF0: mmio.Mmio(packed struct(u32) {
-                ///  Length on air of LENGTH field in number of bits.
-                LFLEN: u4,
-                reserved8: u4,
-                ///  Length on air of S0 field in number of bytes.
-                S0LEN: u1,
-                reserved16: u7,
-                ///  Length on air of S1 field in number of bits.
-                S1LEN: u4,
-                ///  Include or exclude S1 field in RAM
-                S1INCL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Include S1 field in RAM only if S1LEN > 0
-                        Automatic = 0x0,
-                        ///  Always include S1 field in RAM independent of S1LEN
-                        Include = 0x1,
-                    },
-                },
-                reserved22: u1,
-                ///  Length of code indicator - long range
-                CILEN: u2,
-                ///  Length of preamble on air. Decision point: TASKS_START task
-                PLEN: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  8-bit preamble
-                        @"8bit" = 0x0,
-                        ///  16-bit preamble
-                        @"16bit" = 0x1,
-                        ///  32-bit zero preamble - used for IEEE 802.15.4
-                        @"32bitZero" = 0x2,
-                        ///  Preamble - used for BLE long range
-                        LongRange = 0x3,
-                    },
-                },
-                ///  Indicates if LENGTH field contains CRC or not
-                CRCINC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  LENGTH does not contain CRC
-                        Exclude = 0x0,
-                        ///  LENGTH includes CRC
-                        Include = 0x1,
-                    },
-                },
-                reserved29: u2,
-                ///  Length of TERM field in Long Range operation
-                TERMLEN: u2,
-                padding: u1,
-            }),
-            ///  Packet configuration register 1
-            PCNF1: mmio.Mmio(packed struct(u32) {
-                ///  Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN.
-                MAXLEN: u8,
-                ///  Static length in number of bytes
-                STATLEN: u8,
-                ///  Base address length in number of bytes
-                BALEN: u3,
-                reserved24: u5,
-                ///  On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields.
-                ENDIAN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Least significant bit on air first
-                        Little = 0x0,
-                        ///  Most significant bit on air first
-                        Big = 0x1,
-                    },
-                },
-                ///  Enable or disable packet whitening
-                WHITEEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u6,
-            }),
-            ///  Base address 0
-            BASE0: mmio.Mmio(packed struct(u32) {
-                ///  Base address 0
-                BASE0: u32,
-            }),
-            ///  Base address 1
-            BASE1: mmio.Mmio(packed struct(u32) {
-                ///  Base address 1
-                BASE1: u32,
-            }),
-            ///  Prefixes bytes for logical addresses 0-3
-            PREFIX0: mmio.Mmio(packed struct(u32) {
-                ///  Address prefix 0.
-                AP0: u8,
-                ///  Address prefix 1.
-                AP1: u8,
-                ///  Address prefix 2.
-                AP2: u8,
-                ///  Address prefix 3.
-                AP3: u8,
-            }),
-            ///  Prefixes bytes for logical addresses 4-7
-            PREFIX1: mmio.Mmio(packed struct(u32) {
-                ///  Address prefix 4.
-                AP4: u8,
-                ///  Address prefix 5.
-                AP5: u8,
-                ///  Address prefix 6.
-                AP6: u8,
-                ///  Address prefix 7.
-                AP7: u8,
-            }),
-            ///  Transmit address select
-            TXADDRESS: mmio.Mmio(packed struct(u32) {
-                ///  Transmit address select
-                TXADDRESS: u3,
-                padding: u29,
-            }),
-            ///  Receive address select
-            RXADDRESSES: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable reception on logical address 0.
-                ADDR0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 1.
-                ADDR1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 2.
-                ADDR2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 3.
-                ADDR3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 4.
-                ADDR4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 5.
-                ADDR5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 6.
-                ADDR6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable reception on logical address 7.
-                ADDR7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  CRC configuration
-            CRCCNF: mmio.Mmio(packed struct(u32) {
-                ///  CRC length in number of bytes.
-                LEN: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  CRC length is zero and CRC calculation is disabled
-                        Disabled = 0x0,
-                        ///  CRC length is one byte and CRC calculation is enabled
-                        One = 0x1,
-                        ///  CRC length is two bytes and CRC calculation is enabled
-                        Two = 0x2,
-                        ///  CRC length is three bytes and CRC calculation is enabled
-                        Three = 0x3,
-                    },
-                },
-                reserved8: u6,
-                ///  Include or exclude packet address field out of CRC calculation.
-                SKIPADDR: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  CRC calculation includes address field
-                        Include = 0x0,
-                        ///  CRC calculation does not include address field. The CRC calculation will start at the first byte after the address.
-                        Skip = 0x1,
-                        ///  CRC calculation as per 802.15.4 standard. Starting at first byte after length field.
-                        Ieee802154 = 0x2,
-                        _,
-                    },
-                },
-                padding: u22,
-            }),
-            ///  CRC polynomial
-            CRCPOLY: mmio.Mmio(packed struct(u32) {
-                ///  CRC polynomial
-                CRCPOLY: u24,
-                padding: u8,
-            }),
-            ///  CRC initial value
-            CRCINIT: mmio.Mmio(packed struct(u32) {
-                ///  CRC initial value
-                CRCINIT: u24,
-                padding: u8,
-            }),
-            reserved1348: [4]u8,
-            ///  Interframe spacing in us
-            TIFS: mmio.Mmio(packed struct(u32) {
-                ///  Interframe spacing in us
-                TIFS: u10,
-                padding: u22,
-            }),
-            ///  RSSI sample
-            RSSISAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  RSSI sample
-                RSSISAMPLE: u7,
-                padding: u25,
-            }),
-            reserved1360: [4]u8,
-            ///  Current radio state
-            STATE: mmio.Mmio(packed struct(u32) {
-                ///  Current radio state
-                STATE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  RADIO is in the Disabled state
-                        Disabled = 0x0,
-                        ///  RADIO is in the RXRU state
-                        RxRu = 0x1,
-                        ///  RADIO is in the RXIDLE state
-                        RxIdle = 0x2,
-                        ///  RADIO is in the RX state
-                        Rx = 0x3,
-                        ///  RADIO is in the RXDISABLED state
-                        RxDisable = 0x4,
-                        ///  RADIO is in the TXRU state
-                        TxRu = 0x9,
-                        ///  RADIO is in the TXIDLE state
-                        TxIdle = 0xa,
-                        ///  RADIO is in the TX state
-                        Tx = 0xb,
-                        ///  RADIO is in the TXDISABLED state
-                        TxDisable = 0xc,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Data whitening initial value
-            DATAWHITEIV: mmio.Mmio(packed struct(u32) {
-                ///  Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'.
-                DATAWHITEIV: u7,
-                padding: u25,
-            }),
-            reserved1376: [8]u8,
-            ///  Bit counter compare
-            BCC: mmio.Mmio(packed struct(u32) {
-                ///  Bit counter compare
-                BCC: u32,
-            }),
-            reserved1536: [156]u8,
-            ///  Description collection: Device address base segment n
-            DAB: [8]mmio.Mmio(packed struct(u32) {
-                ///  Device address base segment n
-                DAB: u32,
-            }),
-            ///  Description collection: Device address prefix n
-            DAP: [8]mmio.Mmio(packed struct(u32) {
-                ///  Device address prefix n
-                DAP: u16,
-                padding: u16,
-            }),
-            ///  Device address match configuration
-            DACNF: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable device address matching using device address 0
-                ENA0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 1
-                ENA1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 2
-                ENA2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 3
-                ENA3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 4
-                ENA4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 5
-                ENA5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 6
-                ENA6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable device address matching using device address 7
-                ENA7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  TxAdd for device address 0
-                TXADD0: u1,
-                ///  TxAdd for device address 1
-                TXADD1: u1,
-                ///  TxAdd for device address 2
-                TXADD2: u1,
-                ///  TxAdd for device address 3
-                TXADD3: u1,
-                ///  TxAdd for device address 4
-                TXADD4: u1,
-                ///  TxAdd for device address 5
-                TXADD5: u1,
-                ///  TxAdd for device address 6
-                TXADD6: u1,
-                ///  TxAdd for device address 7
-                TXADD7: u1,
-                padding: u16,
-            }),
-            ///  Search pattern configuration
-            MHRMATCHCONF: mmio.Mmio(packed struct(u32) {
-                ///  Search pattern configuration
-                MHRMATCHCONF: u32,
-            }),
-            ///  Pattern mask
-            MHRMATCHMAS: mmio.Mmio(packed struct(u32) {
-                ///  Pattern mask
-                MHRMATCHMAS: u32,
-            }),
-            reserved1616: [4]u8,
-            ///  Radio mode configuration register 0
-            MODECNF0: mmio.Mmio(packed struct(u32) {
-                ///  Radio ramp-up time
-                RU: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Default ramp-up time (tRXEN and tTXEN), compatible with firmware written for nRF51
-                        Default = 0x0,
-                        ///  Fast ramp-up (tRXEN,FAST and tTXEN,FAST), see electrical specification for more information
-                        Fast = 0x1,
-                    },
-                },
-                reserved8: u7,
-                ///  Default TX value
-                DTX: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Transmit '1'
-                        B1 = 0x0,
-                        ///  Transmit '0'
-                        B0 = 0x1,
-                        ///  Transmit center frequency
-                        Center = 0x2,
-                        _,
-                    },
-                },
-                padding: u22,
-            }),
-            reserved1632: [12]u8,
-            ///  IEEE 802.15.4 start of frame delimiter
-            SFD: mmio.Mmio(packed struct(u32) {
-                ///  IEEE 802.15.4 start of frame delimiter
-                SFD: u8,
-                padding: u24,
-            }),
-            ///  IEEE 802.15.4 energy detect loop count
-            EDCNT: mmio.Mmio(packed struct(u32) {
-                ///  IEEE 802.15.4 energy detect loop count
-                EDCNT: u21,
-                padding: u11,
-            }),
-            ///  IEEE 802.15.4 energy detect level
-            EDSAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  IEEE 802.15.4 energy detect level
-                EDLVL: u8,
-                padding: u24,
-            }),
-            ///  IEEE 802.15.4 clear channel assessment control
-            CCACTRL: mmio.Mmio(packed struct(u32) {
-                ///  CCA mode of operation
-                CCAMODE: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Energy above threshold
-                        EdMode = 0x0,
-                        ///  Carrier seen
-                        CarrierMode = 0x1,
-                        ///  Energy above threshold AND carrier seen
-                        CarrierAndEdMode = 0x2,
-                        ///  Energy above threshold OR carrier seen
-                        CarrierOrEdMode = 0x3,
-                        ///  Energy above threshold test mode that will abort when first ED measurement over threshold is seen. No averaging.
-                        EdModeTest1 = 0x4,
-                        _,
-                    },
-                },
-                reserved8: u5,
-                ///  CCA energy busy threshold. Used in all the CCA modes except CarrierMode.
-                CCAEDTHRES: u8,
-                ///  CCA correlator busy threshold. Only relevant to CarrierMode, CarrierAndEdMode and CarrierOrEdMode.
-                CCACORRTHRES: u8,
-                ///  Limit for occurances above CCACORRTHRES. When not equal to zero the corrolator based signal detect is enabled.
-                CCACORRCNT: u8,
-            }),
-            reserved4092: [2444]u8,
-            ///  Peripheral power control
-            POWER: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again.
-                POWER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Peripheral is powered off
-                        Disabled = 0x0,
-                        ///  Peripheral is powered on
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  Universal Asynchronous Receiver/Transmitter
-        pub const UART0 = extern struct {
-            ///  Start UART receiver
-            TASKS_STARTRX: mmio.Mmio(packed struct(u32) {
-                ///  Start UART receiver
-                TASKS_STARTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop UART receiver
-            TASKS_STOPRX: mmio.Mmio(packed struct(u32) {
-                ///  Stop UART receiver
-                TASKS_STOPRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start UART transmitter
-            TASKS_STARTTX: mmio.Mmio(packed struct(u32) {
-                ///  Start UART transmitter
-                TASKS_STARTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop UART transmitter
-            TASKS_STOPTX: mmio.Mmio(packed struct(u32) {
-                ///  Stop UART transmitter
-                TASKS_STOPTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved28: [12]u8,
-            ///  Suspend UART
-            TASKS_SUSPEND: mmio.Mmio(packed struct(u32) {
-                ///  Suspend UART
-                TASKS_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [224]u8,
-            ///  CTS is activated (set low). Clear To Send.
-            EVENTS_CTS: mmio.Mmio(packed struct(u32) {
-                ///  CTS is activated (set low). Clear To Send.
-                EVENTS_CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  CTS is deactivated (set high). Not Clear To Send.
-            EVENTS_NCTS: mmio.Mmio(packed struct(u32) {
-                ///  CTS is deactivated (set high). Not Clear To Send.
-                EVENTS_NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Data received in RXD
-            EVENTS_RXDRDY: mmio.Mmio(packed struct(u32) {
-                ///  Data received in RXD
-                EVENTS_RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved284: [16]u8,
-            ///  Data sent from TXD
-            EVENTS_TXDRDY: mmio.Mmio(packed struct(u32) {
-                ///  Data sent from TXD
-                EVENTS_TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved292: [4]u8,
-            ///  Error detected
-            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
-                ///  Error detected
-                EVENTS_ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved324: [28]u8,
-            ///  Receiver timeout
-            EVENTS_RXTO: mmio.Mmio(packed struct(u32) {
-                ///  Receiver timeout
-                EVENTS_RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [184]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                ///  Shortcut between event CTS and task STARTRX
-                CTS_STARTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event NCTS and task STOPRX
-                NCTS_STOPRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event CTS
-                CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event NCTS
-                NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event RXDRDY
-                RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u4,
-                ///  Write '1' to enable interrupt for event TXDRDY
-                TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u1,
-                ///  Write '1' to enable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved17: u7,
-                ///  Write '1' to enable interrupt for event RXTO
-                RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u14,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event CTS
-                CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event NCTS
-                NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event RXDRDY
-                RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u4,
-                ///  Write '1' to disable interrupt for event TXDRDY
-                TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u1,
-                ///  Write '1' to disable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved17: u7,
-                ///  Write '1' to disable interrupt for event RXTO
-                RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u14,
-            }),
-            reserved1152: [372]u8,
-            ///  Error source
-            ERRORSRC: mmio.Mmio(packed struct(u32) {
-                ///  Overrun error
-                OVERRUN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Parity error
-                PARITY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Framing error occurred
-                FRAMING: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Break condition
-                BREAK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1280: [124]u8,
-            ///  Enable UART
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable UART
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable UART
-                        Disabled = 0x0,
-                        ///  Enable UART
-                        Enabled = 0x4,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1304: [20]u8,
-            ///  RXD register
-            RXD: mmio.Mmio(packed struct(u32) {
-                ///  RX data received in previous transfers, double buffered
-                RXD: u8,
-                padding: u24,
-            }),
-            ///  TXD register
-            TXD: mmio.Mmio(packed struct(u32) {
-                ///  TX data to be transferred
-                TXD: u8,
-                padding: u24,
-            }),
-            reserved1316: [4]u8,
-            ///  Baud rate. Accuracy depends on the HFCLK source selected.
-            BAUDRATE: mmio.Mmio(packed struct(u32) {
-                ///  Baud rate
-                BAUDRATE: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  1200 baud (actual rate: 1205)
-                        Baud1200 = 0x4f000,
-                        ///  2400 baud (actual rate: 2396)
-                        Baud2400 = 0x9d000,
-                        ///  4800 baud (actual rate: 4808)
-                        Baud4800 = 0x13b000,
-                        ///  9600 baud (actual rate: 9598)
-                        Baud9600 = 0x275000,
-                        ///  14400 baud (actual rate: 14414)
-                        Baud14400 = 0x3b0000,
-                        ///  19200 baud (actual rate: 19208)
-                        Baud19200 = 0x4ea000,
-                        ///  28800 baud (actual rate: 28829)
-                        Baud28800 = 0x75f000,
-                        ///  31250 baud
-                        Baud31250 = 0x800000,
-                        ///  38400 baud (actual rate: 38462)
-                        Baud38400 = 0x9d5000,
-                        ///  56000 baud (actual rate: 55944)
-                        Baud56000 = 0xe50000,
-                        ///  57600 baud (actual rate: 57762)
-                        Baud57600 = 0xebf000,
-                        ///  76800 baud (actual rate: 76923)
-                        Baud76800 = 0x13a9000,
-                        ///  115200 baud (actual rate: 115942)
-                        Baud115200 = 0x1d7e000,
-                        ///  230400 baud (actual rate: 231884)
-                        Baud230400 = 0x3afb000,
-                        ///  250000 baud
-                        Baud250000 = 0x4000000,
-                        ///  460800 baud (actual rate: 470588)
-                        Baud460800 = 0x75f7000,
-                        ///  921600 baud (actual rate: 941176)
-                        Baud921600 = 0xebed000,
-                        ///  1Mega baud
-                        Baud1M = 0x10000000,
-                        _,
-                    },
-                },
-            }),
-            reserved1388: [68]u8,
-            ///  Configuration of parity and hardware flow control
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Hardware flow control
-                HWFC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Parity
-                PARITY: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Exclude parity bit
-                        Excluded = 0x0,
-                        ///  Include parity bit
-                        Included = 0x7,
-                        _,
-                    },
-                },
-                ///  Stop bits
-                STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  One stop bit
-                        One = 0x0,
-                        ///  Two stop bits
-                        Two = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-        };
-
-        ///  UART with EasyDMA 0
-        pub const UARTE0 = extern struct {
-            ///  Start UART receiver
-            TASKS_STARTRX: mmio.Mmio(packed struct(u32) {
-                ///  Start UART receiver
-                TASKS_STARTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop UART receiver
-            TASKS_STOPRX: mmio.Mmio(packed struct(u32) {
-                ///  Stop UART receiver
-                TASKS_STOPRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start UART transmitter
-            TASKS_STARTTX: mmio.Mmio(packed struct(u32) {
-                ///  Start UART transmitter
-                TASKS_STARTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop UART transmitter
-            TASKS_STOPTX: mmio.Mmio(packed struct(u32) {
-                ///  Stop UART transmitter
-                TASKS_STOPTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved44: [28]u8,
-            ///  Flush RX FIFO into RX buffer
-            TASKS_FLUSHRX: mmio.Mmio(packed struct(u32) {
-                ///  Flush RX FIFO into RX buffer
-                TASKS_FLUSHRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [208]u8,
-            ///  CTS is activated (set low). Clear To Send.
-            EVENTS_CTS: mmio.Mmio(packed struct(u32) {
-                ///  CTS is activated (set low). Clear To Send.
-                EVENTS_CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  CTS is deactivated (set high). Not Clear To Send.
-            EVENTS_NCTS: mmio.Mmio(packed struct(u32) {
-                ///  CTS is deactivated (set high). Not Clear To Send.
-                EVENTS_NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Data received in RXD (but potentially not yet transferred to Data RAM)
-            EVENTS_RXDRDY: mmio.Mmio(packed struct(u32) {
-                ///  Data received in RXD (but potentially not yet transferred to Data RAM)
-                EVENTS_RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved272: [4]u8,
-            ///  Receive buffer is filled up
-            EVENTS_ENDRX: mmio.Mmio(packed struct(u32) {
-                ///  Receive buffer is filled up
-                EVENTS_ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved284: [8]u8,
-            ///  Data sent from TXD
-            EVENTS_TXDRDY: mmio.Mmio(packed struct(u32) {
-                ///  Data sent from TXD
-                EVENTS_TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Last TX byte transmitted
-            EVENTS_ENDTX: mmio.Mmio(packed struct(u32) {
-                ///  Last TX byte transmitted
-                EVENTS_ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Error detected
-            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
-                ///  Error detected
-                EVENTS_ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved324: [28]u8,
-            ///  Receiver timeout
-            EVENTS_RXTO: mmio.Mmio(packed struct(u32) {
-                ///  Receiver timeout
-                EVENTS_RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved332: [4]u8,
-            ///  UART receiver has started
-            EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) {
-                ///  UART receiver has started
-                EVENTS_RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  UART transmitter has started
-            EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) {
-                ///  UART transmitter has started
-                EVENTS_TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved344: [4]u8,
-            ///  Transmitter stopped
-            EVENTS_TXSTOPPED: mmio.Mmio(packed struct(u32) {
-                ///  Transmitter stopped
-                EVENTS_TXSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [164]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved5: u5,
-                ///  Shortcut between event ENDRX and task STARTRX
-                ENDRX_STARTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event ENDRX and task STOPRX
-                ENDRX_STOPRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u25,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for event CTS
-                CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event NCTS
-                NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event RXDRDY
-                RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u1,
-                ///  Enable or disable interrupt for event ENDRX
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u2,
-                ///  Enable or disable interrupt for event TXDRDY
-                TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDTX
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved17: u7,
-                ///  Enable or disable interrupt for event RXTO
-                RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u1,
-                ///  Enable or disable interrupt for event RXSTARTED
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TXSTARTED
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved22: u1,
-                ///  Enable or disable interrupt for event TXSTOPPED
-                TXSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u9,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event CTS
-                CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event NCTS
-                NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event RXDRDY
-                RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u1,
-                ///  Write '1' to enable interrupt for event ENDRX
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u2,
-                ///  Write '1' to enable interrupt for event TXDRDY
-                TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDTX
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved17: u7,
-                ///  Write '1' to enable interrupt for event RXTO
-                RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u1,
-                ///  Write '1' to enable interrupt for event RXSTARTED
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TXSTARTED
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved22: u1,
-                ///  Write '1' to enable interrupt for event TXSTOPPED
-                TXSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u9,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event CTS
-                CTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event NCTS
-                NCTS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event RXDRDY
-                RXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u1,
-                ///  Write '1' to disable interrupt for event ENDRX
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u2,
-                ///  Write '1' to disable interrupt for event TXDRDY
-                TXDRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDTX
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved17: u7,
-                ///  Write '1' to disable interrupt for event RXTO
-                RXTO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u1,
-                ///  Write '1' to disable interrupt for event RXSTARTED
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TXSTARTED
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved22: u1,
-                ///  Write '1' to disable interrupt for event TXSTOPPED
-                TXSTOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u9,
-            }),
-            reserved1152: [372]u8,
-            ///  Error source Note : this register is read / write one to clear.
-            ERRORSRC: mmio.Mmio(packed struct(u32) {
-                ///  Overrun error
-                OVERRUN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Parity error
-                PARITY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Framing error occurred
-                FRAMING: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  Break condition
-                BREAK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1280: [124]u8,
-            ///  Enable UART
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable UARTE
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable UARTE
-                        Disabled = 0x0,
-                        ///  Enable UARTE
-                        Enabled = 0x8,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1316: [32]u8,
-            ///  Baud rate. Accuracy depends on the HFCLK source selected.
-            BAUDRATE: mmio.Mmio(packed struct(u32) {
-                ///  Baud rate
-                BAUDRATE: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  1200 baud (actual rate: 1205)
-                        Baud1200 = 0x4f000,
-                        ///  2400 baud (actual rate: 2396)
-                        Baud2400 = 0x9d000,
-                        ///  4800 baud (actual rate: 4808)
-                        Baud4800 = 0x13b000,
-                        ///  9600 baud (actual rate: 9598)
-                        Baud9600 = 0x275000,
-                        ///  14400 baud (actual rate: 14401)
-                        Baud14400 = 0x3af000,
-                        ///  19200 baud (actual rate: 19208)
-                        Baud19200 = 0x4ea000,
-                        ///  28800 baud (actual rate: 28777)
-                        Baud28800 = 0x75c000,
-                        ///  31250 baud
-                        Baud31250 = 0x800000,
-                        ///  38400 baud (actual rate: 38369)
-                        Baud38400 = 0x9d0000,
-                        ///  56000 baud (actual rate: 55944)
-                        Baud56000 = 0xe50000,
-                        ///  57600 baud (actual rate: 57554)
-                        Baud57600 = 0xeb0000,
-                        ///  76800 baud (actual rate: 76923)
-                        Baud76800 = 0x13a9000,
-                        ///  115200 baud (actual rate: 115108)
-                        Baud115200 = 0x1d60000,
-                        ///  230400 baud (actual rate: 231884)
-                        Baud230400 = 0x3b00000,
-                        ///  250000 baud
-                        Baud250000 = 0x4000000,
-                        ///  460800 baud (actual rate: 457143)
-                        Baud460800 = 0x7400000,
-                        ///  921600 baud (actual rate: 941176)
-                        Baud921600 = 0xf000000,
-                        ///  1Mega baud
-                        Baud1M = 0x10000000,
-                        _,
-                    },
-                },
-            }),
-            reserved1388: [68]u8,
-            ///  Configuration of parity and hardware flow control
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Hardware flow control
-                HWFC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Parity
-                PARITY: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Exclude parity bit
-                        Excluded = 0x0,
-                        ///  Include even parity bit
-                        Included = 0x7,
-                        _,
-                    },
-                },
-                ///  Stop bits
-                STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  One stop bit
-                        One = 0x0,
-                        ///  Two stop bits
-                        Two = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-        };
-
-        ///  Serial Peripheral Interface 0
-        pub const SPI0 = extern struct {
-            reserved264: [264]u8,
-            ///  TXD byte sent and RXD byte received
-            EVENTS_READY: mmio.Mmio(packed struct(u32) {
-                ///  TXD byte sent and RXD byte received
-                EVENTS_READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [504]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Write '1' to enable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Write '1' to disable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1280: [500]u8,
-            ///  Enable SPI
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable SPI
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable SPI
-                        Disabled = 0x0,
-                        ///  Enable SPI
-                        Enabled = 0x1,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1304: [20]u8,
-            ///  RXD register
-            RXD: mmio.Mmio(packed struct(u32) {
-                ///  RX data received. Double buffered
-                RXD: u8,
-                padding: u24,
-            }),
-            ///  TXD register
-            TXD: mmio.Mmio(packed struct(u32) {
-                ///  TX data to send. Double buffered
-                TXD: u8,
-                padding: u24,
-            }),
-            reserved1316: [4]u8,
-            ///  SPI frequency. Accuracy depends on the HFCLK source selected.
-            FREQUENCY: mmio.Mmio(packed struct(u32) {
-                ///  SPI master data rate
-                FREQUENCY: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  125 kbps
-                        K125 = 0x2000000,
-                        ///  250 kbps
-                        K250 = 0x4000000,
-                        ///  500 kbps
-                        K500 = 0x8000000,
-                        ///  1 Mbps
-                        M1 = 0x10000000,
-                        ///  2 Mbps
-                        M2 = 0x20000000,
-                        ///  4 Mbps
-                        M4 = 0x40000000,
-                        ///  8 Mbps
-                        M8 = 0x80000000,
-                        _,
-                    },
-                },
-            }),
-            reserved1364: [44]u8,
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Bit order
-                ORDER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Most significant bit shifted out first
-                        MsbFirst = 0x0,
-                        ///  Least significant bit shifted out first
-                        LsbFirst = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) phase
-                CPHA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Sample on leading edge of clock, shift serial data on trailing edge
-                        Leading = 0x0,
-                        ///  Sample on trailing edge of clock, shift serial data on leading edge
-                        Trailing = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) polarity
-                CPOL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Active high
-                        ActiveHigh = 0x0,
-                        ///  Active low
-                        ActiveLow = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-        };
-
-        ///  Serial Peripheral Interface Master with EasyDMA 0
-        pub const SPIM0 = extern struct {
-            reserved16: [16]u8,
-            ///  Start SPI transaction
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Start SPI transaction
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop SPI transaction
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop SPI transaction
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved28: [4]u8,
-            ///  Suspend SPI transaction
-            TASKS_SUSPEND: mmio.Mmio(packed struct(u32) {
-                ///  Suspend SPI transaction
-                TASKS_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Resume SPI transaction
-            TASKS_RESUME: mmio.Mmio(packed struct(u32) {
-                ///  Resume SPI transaction
-                TASKS_RESUME: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved260: [224]u8,
-            ///  SPI transaction has stopped
-            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
-                ///  SPI transaction has stopped
-                EVENTS_STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved272: [8]u8,
-            ///  End of RXD buffer reached
-            EVENTS_ENDRX: mmio.Mmio(packed struct(u32) {
-                ///  End of RXD buffer reached
-                EVENTS_ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved280: [4]u8,
-            ///  End of RXD buffer and TXD buffer reached
-            EVENTS_END: mmio.Mmio(packed struct(u32) {
-                ///  End of RXD buffer and TXD buffer reached
-                EVENTS_END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved288: [4]u8,
-            ///  End of TXD buffer reached
-            EVENTS_ENDTX: mmio.Mmio(packed struct(u32) {
-                ///  End of TXD buffer reached
-                EVENTS_ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved332: [40]u8,
-            ///  Transaction started
-            EVENTS_STARTED: mmio.Mmio(packed struct(u32) {
-                ///  Transaction started
-                EVENTS_STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [176]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved17: u17,
-                ///  Shortcut between event END and task START
-                END_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u14,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to enable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u2,
-                ///  Write '1' to enable interrupt for event ENDRX
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved6: u1,
-                ///  Write '1' to enable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved8: u1,
-                ///  Write '1' to enable interrupt for event ENDTX
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u10,
-                ///  Write '1' to enable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u2,
-                ///  Write '1' to disable interrupt for event ENDRX
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved6: u1,
-                ///  Write '1' to disable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved8: u1,
-                ///  Write '1' to disable interrupt for event ENDTX
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u10,
-                ///  Write '1' to disable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            reserved1024: [244]u8,
-            ///  Stall status for EasyDMA RAM accesses. The fields in this register is set to STALL by hardware whenever a stall occurres and can be cleared (set to NOSTALL) by the CPU.
-            STALLSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Stall status for EasyDMA RAM reads
-                TX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No stall
-                        NOSTALL = 0x0,
-                        ///  A stall has occurred
-                        STALL = 0x1,
-                    },
-                },
-                ///  Stall status for EasyDMA RAM writes
-                RX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No stall
-                        NOSTALL = 0x0,
-                        ///  A stall has occurred
-                        STALL = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1280: [252]u8,
-            ///  Enable SPIM
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable SPIM
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable SPIM
-                        Disabled = 0x0,
-                        ///  Enable SPIM
-                        Enabled = 0x7,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1316: [32]u8,
-            ///  SPI frequency. Accuracy depends on the HFCLK source selected.
-            FREQUENCY: mmio.Mmio(packed struct(u32) {
-                ///  SPI master data rate
-                FREQUENCY: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  125 kbps
-                        K125 = 0x2000000,
-                        ///  250 kbps
-                        K250 = 0x4000000,
-                        ///  500 kbps
-                        K500 = 0x8000000,
-                        ///  1 Mbps
-                        M1 = 0x10000000,
-                        ///  2 Mbps
-                        M2 = 0x20000000,
-                        ///  4 Mbps
-                        M4 = 0x40000000,
-                        ///  8 Mbps
-                        M8 = 0x80000000,
-                        ///  16 Mbps
-                        M16 = 0xa000000,
-                        ///  32 Mbps
-                        M32 = 0x14000000,
-                        _,
-                    },
-                },
-            }),
-            reserved1364: [44]u8,
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Bit order
-                ORDER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Most significant bit shifted out first
-                        MsbFirst = 0x0,
-                        ///  Least significant bit shifted out first
-                        LsbFirst = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) phase
-                CPHA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Sample on leading edge of clock, shift serial data on trailing edge
-                        Leading = 0x0,
-                        ///  Sample on trailing edge of clock, shift serial data on leading edge
-                        Trailing = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) polarity
-                CPOL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Active high
-                        ActiveHigh = 0x0,
-                        ///  Active low
-                        ActiveLow = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1384: [16]u8,
-            ///  Polarity of CSN output
-            CSNPOL: mmio.Mmio(packed struct(u32) {
-                ///  Polarity of CSN output
-                CSNPOL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Active low (idle state high)
-                        LOW = 0x0,
-                        ///  Active high (idle state low)
-                        HIGH = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Pin select for DCX signal
-            PSELDCX: mmio.Mmio(packed struct(u32) {
-                ///  Pin number
-                PIN: u5,
-                ///  Port number
-                PORT: u1,
-                reserved31: u25,
-                ///  Connection
-                CONNECT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disconnect
-                        Disconnected = 0x1,
-                        ///  Connect
-                        Connected = 0x0,
-                    },
-                },
-            }),
-            ///  DCX configuration
-            DCXCNT: mmio.Mmio(packed struct(u32) {
-                ///  This register specifies the number of command bytes preceding the data bytes. The PSEL.DCX line will be low during transmission of command bytes and high during transmission of data bytes. Value 0xF indicates that all bytes are command bytes.
-                DCXCNT: u4,
-                padding: u28,
-            }),
-            reserved1472: [76]u8,
-            ///  Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT
-            ORC: mmio.Mmio(packed struct(u32) {
-                ///  Byte transmitted after TXD.MAXCNT bytes have been transmitted in the case when RXD.MAXCNT is greater than TXD.MAXCNT.
-                ORC: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  SPI Slave 0
-        pub const SPIS0 = extern struct {
-            reserved36: [36]u8,
-            ///  Acquire SPI semaphore
-            TASKS_ACQUIRE: mmio.Mmio(packed struct(u32) {
-                ///  Acquire SPI semaphore
-                TASKS_ACQUIRE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Release SPI semaphore, enabling the SPI slave to acquire it
-            TASKS_RELEASE: mmio.Mmio(packed struct(u32) {
-                ///  Release SPI semaphore, enabling the SPI slave to acquire it
-                TASKS_RELEASE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved260: [216]u8,
-            ///  Granted transaction completed
-            EVENTS_END: mmio.Mmio(packed struct(u32) {
-                ///  Granted transaction completed
-                EVENTS_END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved272: [8]u8,
-            ///  End of RXD buffer reached
-            EVENTS_ENDRX: mmio.Mmio(packed struct(u32) {
-                ///  End of RXD buffer reached
-                EVENTS_ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved296: [20]u8,
-            ///  Semaphore acquired
-            EVENTS_ACQUIRED: mmio.Mmio(packed struct(u32) {
-                ///  Semaphore acquired
-                EVENTS_ACQUIRED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [212]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Shortcut between event END and task ACQUIRE
-                END_ACQUIRE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to enable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u2,
-                ///  Write '1' to enable interrupt for event ENDRX
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u5,
-                ///  Write '1' to enable interrupt for event ACQUIRED
-                ACQUIRED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u21,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to disable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved4: u2,
-                ///  Write '1' to disable interrupt for event ENDRX
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u5,
-                ///  Write '1' to disable interrupt for event ACQUIRED
-                ACQUIRED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u21,
-            }),
-            reserved1024: [244]u8,
-            ///  Semaphore status register
-            SEMSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Semaphore status
-                SEMSTAT: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Semaphore is free
-                        Free = 0x0,
-                        ///  Semaphore is assigned to CPU
-                        CPU = 0x1,
-                        ///  Semaphore is assigned to SPI slave
-                        SPIS = 0x2,
-                        ///  Semaphore is assigned to SPI but a handover to the CPU is pending
-                        CPUPending = 0x3,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1088: [60]u8,
-            ///  Status from last transaction
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  TX buffer over-read detected, and prevented
-                OVERREAD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  RX buffer overflow detected, and prevented
-                OVERFLOW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1280: [188]u8,
-            ///  Enable SPI slave
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable SPI slave
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable SPI slave
-                        Disabled = 0x0,
-                        ///  Enable SPI slave
-                        Enabled = 0x2,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1364: [80]u8,
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Bit order
-                ORDER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Most significant bit shifted out first
-                        MsbFirst = 0x0,
-                        ///  Least significant bit shifted out first
-                        LsbFirst = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) phase
-                CPHA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Sample on leading edge of clock, shift serial data on trailing edge
-                        Leading = 0x0,
-                        ///  Sample on trailing edge of clock, shift serial data on leading edge
-                        Trailing = 0x1,
-                    },
-                },
-                ///  Serial clock (SCK) polarity
-                CPOL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Active high
-                        ActiveHigh = 0x0,
-                        ///  Active low
-                        ActiveLow = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1372: [4]u8,
-            ///  Default character. Character clocked out in case of an ignored transaction.
-            DEF: mmio.Mmio(packed struct(u32) {
-                ///  Default character. Character clocked out in case of an ignored transaction.
-                DEF: u8,
-                padding: u24,
-            }),
-            reserved1472: [96]u8,
-            ///  Over-read character
-            ORC: mmio.Mmio(packed struct(u32) {
-                ///  Over-read character. Character clocked out after an over-read of the transmit buffer.
-                ORC: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  I2C compatible Two-Wire Interface 0
-        pub const TWI0 = extern struct {
-            ///  Start TWI receive sequence
-            TASKS_STARTRX: mmio.Mmio(packed struct(u32) {
-                ///  Start TWI receive sequence
-                TASKS_STARTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved8: [4]u8,
-            ///  Start TWI transmit sequence
-            TASKS_STARTTX: mmio.Mmio(packed struct(u32) {
-                ///  Start TWI transmit sequence
-                TASKS_STARTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved20: [8]u8,
-            ///  Stop TWI transaction
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop TWI transaction
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved28: [4]u8,
-            ///  Suspend TWI transaction
-            TASKS_SUSPEND: mmio.Mmio(packed struct(u32) {
-                ///  Suspend TWI transaction
-                TASKS_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Resume TWI transaction
-            TASKS_RESUME: mmio.Mmio(packed struct(u32) {
-                ///  Resume TWI transaction
-                TASKS_RESUME: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved260: [224]u8,
-            ///  TWI stopped
-            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
-                ///  TWI stopped
-                EVENTS_STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  TWI RXD byte received
-            EVENTS_RXDREADY: mmio.Mmio(packed struct(u32) {
-                ///  TWI RXD byte received
-                EVENTS_RXDREADY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved284: [16]u8,
-            ///  TWI TXD byte sent
-            EVENTS_TXDSENT: mmio.Mmio(packed struct(u32) {
-                ///  TWI TXD byte sent
-                EVENTS_TXDSENT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved292: [4]u8,
-            ///  TWI error
-            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
-                ///  TWI error
-                EVENTS_ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved312: [16]u8,
-            ///  TWI byte boundary, generated before each byte that is sent or received
-            EVENTS_BB: mmio.Mmio(packed struct(u32) {
-                ///  TWI byte boundary, generated before each byte that is sent or received
-                EVENTS_BB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved328: [12]u8,
-            ///  TWI entered the suspended state
-            EVENTS_SUSPENDED: mmio.Mmio(packed struct(u32) {
-                ///  TWI entered the suspended state
-                EVENTS_SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [180]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between event BB and task SUSPEND
-                BB_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event BB and task STOP
-                BB_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to enable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event RXDREADY
-                RXDREADY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u4,
-                ///  Write '1' to enable interrupt for event TXDSENT
-                TXDSENT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u1,
-                ///  Write '1' to enable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved14: u4,
-                ///  Write '1' to enable interrupt for event BB
-                BB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u3,
-                ///  Write '1' to enable interrupt for event SUSPENDED
-                SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u13,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event RXDREADY
-                RXDREADY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved7: u4,
-                ///  Write '1' to disable interrupt for event TXDSENT
-                TXDSENT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u1,
-                ///  Write '1' to disable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved14: u4,
-                ///  Write '1' to disable interrupt for event BB
-                BB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u3,
-                ///  Write '1' to disable interrupt for event SUSPENDED
-                SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u13,
-            }),
-            reserved1220: [440]u8,
-            ///  Error source
-            ERRORSRC: mmio.Mmio(packed struct(u32) {
-                ///  Overrun error
-                OVERRUN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: no overrun occured
-                        NotPresent = 0x0,
-                        ///  Read: overrun occured
-                        Present = 0x1,
-                    },
-                },
-                ///  NACK received after sending the address (write '1' to clear)
-                ANACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                ///  NACK received after sending a data byte (write '1' to clear)
-                DNACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: error not present
-                        NotPresent = 0x0,
-                        ///  Read: error present
-                        Present = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1280: [56]u8,
-            ///  Enable TWI
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable TWI
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable TWI
-                        Disabled = 0x0,
-                        ///  Enable TWI
-                        Enabled = 0x5,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1304: [20]u8,
-            ///  RXD register
-            RXD: mmio.Mmio(packed struct(u32) {
-                ///  RXD register
-                RXD: u8,
-                padding: u24,
-            }),
-            ///  TXD register
-            TXD: mmio.Mmio(packed struct(u32) {
-                ///  TXD register
-                TXD: u8,
-                padding: u24,
-            }),
-            reserved1316: [4]u8,
-            ///  TWI frequency. Accuracy depends on the HFCLK source selected.
-            FREQUENCY: mmio.Mmio(packed struct(u32) {
-                ///  TWI master clock frequency
-                FREQUENCY: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  100 kbps
-                        K100 = 0x1980000,
-                        ///  250 kbps
-                        K250 = 0x4000000,
-                        ///  400 kbps (actual rate 410.256 kbps)
-                        K400 = 0x6680000,
-                        _,
-                    },
-                },
-            }),
-            reserved1416: [96]u8,
-            ///  Address used in the TWI transfer
-            ADDRESS: mmio.Mmio(packed struct(u32) {
-                ///  Address used in the TWI transfer
-                ADDRESS: u7,
-                padding: u25,
-            }),
-        };
-
-        ///  I2C compatible Two-Wire Master Interface with EasyDMA 0
-        pub const TWIM0 = extern struct {
-            ///  Start TWI receive sequence
-            TASKS_STARTRX: mmio.Mmio(packed struct(u32) {
-                ///  Start TWI receive sequence
-                TASKS_STARTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved8: [4]u8,
-            ///  Start TWI transmit sequence
-            TASKS_STARTTX: mmio.Mmio(packed struct(u32) {
-                ///  Start TWI transmit sequence
-                TASKS_STARTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved20: [8]u8,
-            ///  Stop TWI transaction. Must be issued while the TWI master is not suspended.
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop TWI transaction. Must be issued while the TWI master is not suspended.
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved28: [4]u8,
-            ///  Suspend TWI transaction
-            TASKS_SUSPEND: mmio.Mmio(packed struct(u32) {
-                ///  Suspend TWI transaction
-                TASKS_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Resume TWI transaction
-            TASKS_RESUME: mmio.Mmio(packed struct(u32) {
-                ///  Resume TWI transaction
-                TASKS_RESUME: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved260: [224]u8,
-            ///  TWI stopped
-            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
-                ///  TWI stopped
-                EVENTS_STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved292: [28]u8,
-            ///  TWI error
-            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
-                ///  TWI error
-                EVENTS_ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved328: [32]u8,
-            ///  Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
-            EVENTS_SUSPENDED: mmio.Mmio(packed struct(u32) {
-                ///  Last byte has been sent out after the SUSPEND task has been issued, TWI traffic is now suspended.
-                EVENTS_SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Receive sequence started
-            EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) {
-                ///  Receive sequence started
-                EVENTS_RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Transmit sequence started
-            EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) {
-                ///  Transmit sequence started
-                EVENTS_TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved348: [8]u8,
-            ///  Byte boundary, starting to receive the last byte
-            EVENTS_LASTRX: mmio.Mmio(packed struct(u32) {
-                ///  Byte boundary, starting to receive the last byte
-                EVENTS_LASTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Byte boundary, starting to transmit the last byte
-            EVENTS_LASTTX: mmio.Mmio(packed struct(u32) {
-                ///  Byte boundary, starting to transmit the last byte
-                EVENTS_LASTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [156]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved7: u7,
-                ///  Shortcut between event LASTTX and task STARTRX
-                LASTTX_STARTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event LASTTX and task SUSPEND
-                LASTTX_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event LASTTX and task STOP
-                LASTTX_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event LASTRX and task STARTTX
-                LASTRX_STARTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event LASTRX and task SUSPEND
-                LASTRX_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event LASTRX and task STOP
-                LASTRX_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u19,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Enable or disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Enable or disable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u8,
-                ///  Enable or disable interrupt for event SUSPENDED
-                SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event RXSTARTED
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TXSTARTED
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved23: u2,
-                ///  Enable or disable interrupt for event LASTRX
-                LASTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event LASTTX
-                LASTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to enable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Write '1' to enable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u8,
-                ///  Write '1' to enable interrupt for event SUSPENDED
-                SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event RXSTARTED
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TXSTARTED
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved23: u2,
-                ///  Write '1' to enable interrupt for event LASTRX
-                LASTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event LASTTX
-                LASTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Write '1' to disable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u8,
-                ///  Write '1' to disable interrupt for event SUSPENDED
-                SUSPENDED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event RXSTARTED
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TXSTARTED
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved23: u2,
-                ///  Write '1' to disable interrupt for event LASTRX
-                LASTRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event LASTTX
-                LASTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            reserved1220: [440]u8,
-            ///  Error source
-            ERRORSRC: mmio.Mmio(packed struct(u32) {
-                ///  Overrun error
-                OVERRUN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotReceived = 0x0,
-                        ///  Error occurred
-                        Received = 0x1,
-                    },
-                },
-                ///  NACK received after sending the address (write '1' to clear)
-                ANACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotReceived = 0x0,
-                        ///  Error occurred
-                        Received = 0x1,
-                    },
-                },
-                ///  NACK received after sending a data byte (write '1' to clear)
-                DNACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotReceived = 0x0,
-                        ///  Error occurred
-                        Received = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1280: [56]u8,
-            ///  Enable TWIM
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable TWIM
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable TWIM
-                        Disabled = 0x0,
-                        ///  Enable TWIM
-                        Enabled = 0x6,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1316: [32]u8,
-            ///  TWI frequency. Accuracy depends on the HFCLK source selected.
-            FREQUENCY: mmio.Mmio(packed struct(u32) {
-                ///  TWI master clock frequency
-                FREQUENCY: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  100 kbps
-                        K100 = 0x1980000,
-                        ///  250 kbps
-                        K250 = 0x4000000,
-                        ///  400 kbps
-                        K400 = 0x6400000,
-                        _,
-                    },
-                },
-            }),
-            reserved1416: [96]u8,
-            ///  Address used in the TWI transfer
-            ADDRESS: mmio.Mmio(packed struct(u32) {
-                ///  Address used in the TWI transfer
-                ADDRESS: u7,
-                padding: u25,
-            }),
-        };
-
-        ///  I2C compatible Two-Wire Slave Interface with EasyDMA 0
-        pub const TWIS0 = extern struct {
-            reserved20: [20]u8,
-            ///  Stop TWI transaction
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop TWI transaction
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved28: [4]u8,
-            ///  Suspend TWI transaction
-            TASKS_SUSPEND: mmio.Mmio(packed struct(u32) {
-                ///  Suspend TWI transaction
-                TASKS_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Resume TWI transaction
-            TASKS_RESUME: mmio.Mmio(packed struct(u32) {
-                ///  Resume TWI transaction
-                TASKS_RESUME: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved48: [12]u8,
-            ///  Prepare the TWI slave to respond to a write command
-            TASKS_PREPARERX: mmio.Mmio(packed struct(u32) {
-                ///  Prepare the TWI slave to respond to a write command
-                TASKS_PREPARERX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Prepare the TWI slave to respond to a read command
-            TASKS_PREPARETX: mmio.Mmio(packed struct(u32) {
-                ///  Prepare the TWI slave to respond to a read command
-                TASKS_PREPARETX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved260: [204]u8,
-            ///  TWI stopped
-            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
-                ///  TWI stopped
-                EVENTS_STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved292: [28]u8,
-            ///  TWI error
-            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
-                ///  TWI error
-                EVENTS_ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved332: [36]u8,
-            ///  Receive sequence started
-            EVENTS_RXSTARTED: mmio.Mmio(packed struct(u32) {
-                ///  Receive sequence started
-                EVENTS_RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Transmit sequence started
-            EVENTS_TXSTARTED: mmio.Mmio(packed struct(u32) {
-                ///  Transmit sequence started
-                EVENTS_TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved356: [16]u8,
-            ///  Write command received
-            EVENTS_WRITE: mmio.Mmio(packed struct(u32) {
-                ///  Write command received
-                EVENTS_WRITE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Read command received
-            EVENTS_READ: mmio.Mmio(packed struct(u32) {
-                ///  Read command received
-                EVENTS_READ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [148]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                reserved13: u13,
-                ///  Shortcut between event WRITE and task SUSPEND
-                WRITE_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event READ and task SUSPEND
-                READ_SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u17,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Enable or disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Enable or disable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u9,
-                ///  Enable or disable interrupt for event RXSTARTED
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TXSTARTED
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved25: u4,
-                ///  Enable or disable interrupt for event WRITE
-                WRITE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event READ
-                READ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u5,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to enable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Write '1' to enable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u9,
-                ///  Write '1' to enable interrupt for event RXSTARTED
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TXSTARTED
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved25: u4,
-                ///  Write '1' to enable interrupt for event WRITE
-                WRITE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event READ
-                READ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u5,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved9: u7,
-                ///  Write '1' to disable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved19: u9,
-                ///  Write '1' to disable interrupt for event RXSTARTED
-                RXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TXSTARTED
-                TXSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved25: u4,
-                ///  Write '1' to disable interrupt for event WRITE
-                WRITE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event READ
-                READ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u5,
-            }),
-            reserved1232: [452]u8,
-            ///  Error source
-            ERRORSRC: mmio.Mmio(packed struct(u32) {
-                ///  RX buffer overflow detected, and prevented
-                OVERFLOW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotDetected = 0x0,
-                        ///  Error occurred
-                        Detected = 0x1,
-                    },
-                },
-                reserved2: u1,
-                ///  NACK sent after receiving a data byte
-                DNACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotReceived = 0x0,
-                        ///  Error occurred
-                        Received = 0x1,
-                    },
-                },
-                ///  TX buffer over-read detected, and prevented
-                OVERREAD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Error did not occur
-                        NotDetected = 0x0,
-                        ///  Error occurred
-                        Detected = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Status register indicating which address had a match
-            MATCH: mmio.Mmio(packed struct(u32) {
-                ///  Which of the addresses in {ADDRESS} matched the incoming address
-                MATCH: u1,
-                padding: u31,
-            }),
-            reserved1280: [40]u8,
-            ///  Enable TWIS
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable TWIS
-                ENABLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Disable TWIS
-                        Disabled = 0x0,
-                        ///  Enable TWIS
-                        Enabled = 0x9,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1416: [132]u8,
-            ///  Description collection: TWI slave address n
-            ADDRESS: [2]mmio.Mmio(packed struct(u32) {
-                ///  TWI slave address
-                ADDRESS: u7,
-                padding: u25,
-            }),
-            reserved1428: [4]u8,
-            ///  Configuration register for the address match mechanism
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable address matching on ADDRESS[0]
-                ADDRESS0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable address matching on ADDRESS[1]
-                ADDRESS1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1472: [40]u8,
-            ///  Over-read character. Character sent out in case of an over-read of the transmit buffer.
-            ORC: mmio.Mmio(packed struct(u32) {
-                ///  Over-read character. Character sent out in case of an over-read of the transmit buffer.
-                ORC: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  Pulse Density Modulation (Digital Microphone) Interface
-        pub const PDM = extern struct {
-            ///  Starts continuous PDM transfer
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Starts continuous PDM transfer
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stops PDM transfer
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stops PDM transfer
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [248]u8,
-            ///  PDM transfer has started
-            EVENTS_STARTED: mmio.Mmio(packed struct(u32) {
-                ///  PDM transfer has started
-                EVENTS_STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  PDM transfer has finished
-            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
-                ///  PDM transfer has finished
-                EVENTS_STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM
-            EVENTS_END: mmio.Mmio(packed struct(u32) {
-                ///  The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM
-                EVENTS_END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved768: [500]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1280: [500]u8,
-            ///  PDM module enable register
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable PDM module
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  PDM clock generator control
-            PDMCLKCTRL: mmio.Mmio(packed struct(u32) {
-                ///  PDM_CLK frequency
-                FREQ: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  PDM_CLK = 32 MHz / 32 = 1.000 MHz
-                        @"1000K" = 0x8000000,
-                        ///  PDM_CLK = 32 MHz / 31 = 1.032 MHz. Nominal clock for RATIO=Ratio64.
-                        Default = 0x8400000,
-                        ///  PDM_CLK = 32 MHz / 30 = 1.067 MHz
-                        @"1067K" = 0x8800000,
-                        ///  PDM_CLK = 32 MHz / 26 = 1.231 MHz
-                        @"1231K" = 0x9800000,
-                        ///  PDM_CLK = 32 MHz / 25 = 1.280 MHz. Nominal clock for RATIO=Ratio80.
-                        @"1280K" = 0xa000000,
-                        ///  PDM_CLK = 32 MHz / 24 = 1.333 MHz
-                        @"1333K" = 0xa800000,
-                        _,
-                    },
-                },
-            }),
-            ///  Defines the routing of the connected PDM microphones' signals
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Mono or stereo operation
-                OPERATION: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0]
-                        Stereo = 0x0,
-                        ///  Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0]
-                        Mono = 0x1,
-                    },
-                },
-                ///  Defines on which PDM_CLK edge Left (or mono) is sampled
-                EDGE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Left (or mono) is sampled on falling edge of PDM_CLK
-                        LeftFalling = 0x0,
-                        ///  Left (or mono) is sampled on rising edge of PDM_CLK
-                        LeftRising = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1304: [12]u8,
-            ///  Left output gain adjustment
-            GAINL: mmio.Mmio(packed struct(u32) {
-                ///  Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00 -20 dB gain adjust 0x01 -19.5 dB gain adjust (...) 0x27 -0.5 dB gain adjust 0x28 0 dB gain adjust 0x29 +0.5 dB gain adjust (...) 0x4F +19.5 dB gain adjust 0x50 +20 dB gain adjust
-                GAINL: packed union {
-                    raw: u7,
-                    value: enum(u7) {
-                        ///  -20dB gain adjustment (minimum)
-                        MinGain = 0x0,
-                        ///  0dB gain adjustment
-                        DefaultGain = 0x28,
-                        ///  +20dB gain adjustment (maximum)
-                        MaxGain = 0x50,
-                        _,
-                    },
-                },
-                padding: u25,
-            }),
-            ///  Right output gain adjustment
-            GAINR: mmio.Mmio(packed struct(u32) {
-                ///  Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters)
-                GAINR: packed union {
-                    raw: u7,
-                    value: enum(u7) {
-                        ///  -20dB gain adjustment (minimum)
-                        MinGain = 0x0,
-                        ///  0dB gain adjustment
-                        DefaultGain = 0x28,
-                        ///  +20dB gain adjustment (maximum)
-                        MaxGain = 0x50,
-                        _,
-                    },
-                },
-                padding: u25,
-            }),
-            ///  Selects the ratio between PDM_CLK and output sample rate. Change PDMCLKCTRL accordingly.
-            RATIO: mmio.Mmio(packed struct(u32) {
-                ///  Selects the ratio between PDM_CLK and output sample rate
-                RATIO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Ratio of 64
-                        Ratio64 = 0x0,
-                        ///  Ratio of 80
-                        Ratio80 = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  ARM TrustZone CryptoCell register interface
-        pub const CRYPTOCELL = extern struct {
-            reserved1280: [1280]u8,
-            ///  Enable CRYPTOCELL subsystem
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable the CRYPTOCELL subsystem
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  CRYPTOCELL subsystem disabled
-                        Disabled = 0x0,
-                        ///  CRYPTOCELL subsystem enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  CRYPTOCELL HOST_RGF interface
-        pub const CC_HOST_RGF = extern struct {
-            reserved6712: [6712]u8,
-            ///  AES hardware key select
-            HOST_CRYPTOKEY_SEL: mmio.Mmio(packed struct(u32) {
-                ///  Select the source of the HW key that is used by the AES engine
-                HOST_CRYPTOKEY_SEL: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Use device root key K_DR from CRYPTOCELL AO power domain
-                        K_DR = 0x0,
-                        ///  Use hard-coded RTL key K_PRTL
-                        K_PRTL = 0x1,
-                        ///  Use provided session key
-                        Session = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved6732: [16]u8,
-            ///  This write-once register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.
-            HOST_IOT_KPRTL_LOCK: mmio.Mmio(packed struct(u32) {
-                ///  This register is the K_PRTL lock register. When this register is set, K_PRTL can not be used and a zeroed key will be used instead. The value of this register is saved in the CRYPTOCELL AO power domain.
-                HOST_IOT_KPRTL_LOCK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  K_PRTL can be selected for use from register HOST_CRYPTOKEY_SEL
-                        Disabled = 0x0,
-                        ///  K_PRTL has been locked until next power-on reset (POR). If K_PRTL is selected anyway, a zeroed key will be used instead.
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  This register holds bits 31:0 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain. Reading from this address returns the K_DR valid status indicating if K_DR is successfully retained.
-            HOST_IOT_KDR0: mmio.Mmio(packed struct(u32) {
-                ///  Write: K_DR bits 31:0 Read: 0x00000000 when 128-bit K_DR key value is not yet retained in the CRYPTOCELL AO power domain Read: 0x00000001 when 128-bit K_DR key value is successfully retained in the CRYPTOCELL AO power domain
-                HOST_IOT_KDR0: u32,
-            }),
-            ///  This register holds bits 63:32 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.
-            HOST_IOT_KDR1: mmio.Mmio(packed struct(u32) {
-                ///  K_DR bits 63:32
-                HOST_IOT_KDR1: u32,
-            }),
-            ///  This register holds bits 95:64 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.
-            HOST_IOT_KDR2: mmio.Mmio(packed struct(u32) {
-                ///  K_DR bits 95:64
-                HOST_IOT_KDR2: u32,
-            }),
-            ///  This register holds bits 127:96 of K_DR. The value of this register is saved in the CRYPTOCELL AO power domain.
-            HOST_IOT_KDR3: mmio.Mmio(packed struct(u32) {
-                ///  K_DR bits 127:96
-                HOST_IOT_KDR3: u32,
-            }),
-            ///  Controls lifecycle state (LCS) for CRYPTOCELL subsystem
-            HOST_IOT_LCS: mmio.Mmio(packed struct(u32) {
-                ///  Lifecycle state value. This field is write-once per reset.
-                LCS: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  CC310 operates in debug mode
-                        Debug = 0x0,
-                        ///  CC310 operates in secure mode
-                        Secure = 0x2,
-                        _,
-                    },
-                },
-                reserved8: u5,
-                ///  This field is read-only and indicates if CRYPTOCELL LCS has been successfully configured since last reset
-                LCS_IS_VALID: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  A valid LCS is not yet retained in the CRYPTOCELL AO power domain
-                        Invalid = 0x0,
-                        ///  A valid LCS is successfully retained in the CRYPTOCELL AO power domain
-                        Valid = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-        };
-
-        ///  External flash interface
-        pub const QSPI = extern struct {
-            ///  Activate QSPI interface
-            TASKS_ACTIVATE: mmio.Mmio(packed struct(u32) {
-                ///  Activate QSPI interface
-                TASKS_ACTIVATE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start transfer from external flash memory to internal RAM
-            TASKS_READSTART: mmio.Mmio(packed struct(u32) {
-                ///  Start transfer from external flash memory to internal RAM
-                TASKS_READSTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start transfer from internal RAM to external flash memory
-            TASKS_WRITESTART: mmio.Mmio(packed struct(u32) {
-                ///  Start transfer from internal RAM to external flash memory
-                TASKS_WRITESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start external flash memory erase operation
-            TASKS_ERASESTART: mmio.Mmio(packed struct(u32) {
-                ///  Start external flash memory erase operation
-                TASKS_ERASESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Deactivate QSPI interface
-            TASKS_DEACTIVATE: mmio.Mmio(packed struct(u32) {
-                ///  Deactivate QSPI interface
-                TASKS_DEACTIVATE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [236]u8,
-            ///  QSPI peripheral is ready. This event will be generated as a response to any QSPI task.
-            EVENTS_READY: mmio.Mmio(packed struct(u32) {
-                ///  QSPI peripheral is ready. This event will be generated as a response to any QSPI task.
-                EVENTS_READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved768: [508]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1280: [500]u8,
-            ///  Enable QSPI peripheral and acquire the pins selected in PSELn registers
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable QSPI
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable QSPI
-                        Disabled = 0x0,
-                        ///  Enable QSPI
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1344: [60]u8,
-            ///  Address offset into the external memory for Execute in Place operation.
-            XIPOFFSET: mmio.Mmio(packed struct(u32) {
-                ///  Address offset into the external memory for Execute in Place operation. Value must be a multiple of 4.
-                XIPOFFSET: u32,
-            }),
-            ///  Interface configuration.
-            IFCONFIG0: mmio.Mmio(packed struct(u32) {
-                ///  Configure number of data lines and opcode used for reading.
-                READOC: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Single data line SPI. FAST_READ (opcode 0x0B).
-                        FASTREAD = 0x0,
-                        ///  Dual data line SPI. READ2O (opcode 0x3B).
-                        READ2O = 0x1,
-                        ///  Dual data line SPI. READ2IO (opcode 0xBB).
-                        READ2IO = 0x2,
-                        ///  Quad data line SPI. READ4O (opcode 0x6B).
-                        READ4O = 0x3,
-                        ///  Quad data line SPI. READ4IO (opcode 0xEB).
-                        READ4IO = 0x4,
-                        _,
-                    },
-                },
-                ///  Configure number of data lines and opcode used for writing.
-                WRITEOC: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Single data line SPI. PP (opcode 0x02).
-                        PP = 0x0,
-                        ///  Dual data line SPI. PP2O (opcode 0xA2).
-                        PP2O = 0x1,
-                        ///  Quad data line SPI. PP4O (opcode 0x32).
-                        PP4O = 0x2,
-                        ///  Quad data line SPI. PP4IO (opcode 0x38).
-                        PP4IO = 0x3,
-                        _,
-                    },
-                },
-                ///  Addressing mode.
-                ADDRMODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  24-bit addressing.
-                        @"24BIT" = 0x0,
-                        ///  32-bit addressing.
-                        @"32BIT" = 0x1,
-                    },
-                },
-                ///  Enable deep power-down mode (DPM) feature.
-                DPMENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable DPM feature.
-                        Disable = 0x0,
-                        ///  Enable DPM feature.
-                        Enable = 0x1,
-                    },
-                },
-                reserved12: u4,
-                ///  Page size for commands PP, PP2O, PP4O and PP4IO.
-                PPSIZE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  256 bytes.
-                        @"256Bytes" = 0x0,
-                        ///  512 bytes.
-                        @"512Bytes" = 0x1,
-                    },
-                },
-                padding: u19,
-            }),
-            reserved1536: [184]u8,
-            ///  Interface configuration.
-            IFCONFIG1: mmio.Mmio(packed struct(u32) {
-                ///  Minimum amount of time that the CSN pin must stay high before it can go low again. Value is specified in number of 16 MHz periods (62.5 ns).
-                SCKDELAY: u8,
-                reserved24: u16,
-                ///  Enter/exit deep power-down mode (DPM) for external flash memory.
-                DPMEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exit DPM.
-                        Exit = 0x0,
-                        ///  Enter DPM.
-                        Enter = 0x1,
-                    },
-                },
-                ///  Select SPI mode.
-                SPIMODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Mode 0: Data are captured on the clock rising edge and data is output on a falling edge. Base level of clock is 0 (CPOL=0, CPHA=0).
-                        MODE0 = 0x0,
-                        ///  Mode 3: Data are captured on the clock falling edge and data is output on a rising edge. Base level of clock is 1 (CPOL=1, CPHA=1).
-                        MODE3 = 0x1,
-                    },
-                },
-                reserved28: u2,
-                ///  SCK frequency is given as 32 MHz / (SCKFREQ + 1).
-                SCKFREQ: u4,
-            }),
-            ///  Status register.
-            STATUS: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Deep power-down mode (DPM) status of external flash.
-                DPM: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  External flash is not in DPM.
-                        Disabled = 0x0,
-                        ///  External flash is in DPM.
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Ready status.
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  QSPI peripheral is ready. It is allowed to trigger new tasks, writing custom instructions or enter/exit DPM.
-                        READY = 0x1,
-                        ///  QSPI peripheral is busy. It is not allowed to trigger any new tasks, writing custom instructions or enter/exit DPM.
-                        BUSY = 0x0,
-                    },
-                },
-                reserved24: u20,
-                ///  Value of external flash device Status Register. When the external flash has two bytes status register this field includes the value of the low byte.
-                SREG: u8,
-            }),
-            reserved1556: [12]u8,
-            ///  Set the duration required to enter/exit deep power-down mode (DPM).
-            DPMDUR: mmio.Mmio(packed struct(u32) {
-                ///  Duration needed by external flash to enter DPM. Duration is given as ENTER * 256 * 62.5 ns.
-                ENTER: u16,
-                ///  Duration needed by external flash to exit DPM. Duration is given as EXIT * 256 * 62.5 ns.
-                EXIT: u16,
-            }),
-            reserved1572: [12]u8,
-            ///  Extended address configuration.
-            ADDRCONF: mmio.Mmio(packed struct(u32) {
-                ///  Opcode that enters the 32-bit addressing mode.
-                OPCODE: u8,
-                ///  Byte 0 following opcode.
-                BYTE0: u8,
-                ///  Byte 1 following byte 0.
-                BYTE1: u8,
-                ///  Extended addressing mode.
-                MODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Do not send any instruction.
-                        NoInstr = 0x0,
-                        ///  Send opcode.
-                        Opcode = 0x1,
-                        ///  Send opcode, byte0.
-                        OpByte0 = 0x2,
-                        ///  Send opcode, byte0, byte1.
-                        All = 0x3,
-                    },
-                },
-                ///  Wait for write complete before sending command.
-                WIPWAIT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No wait.
-                        Disable = 0x0,
-                        ///  Wait.
-                        Enable = 0x1,
-                    },
-                },
-                ///  Send WREN (write enable opcode 0x06) before instruction.
-                WREN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Do not send WREN.
-                        Disable = 0x0,
-                        ///  Send WREN.
-                        Enable = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            reserved1588: [12]u8,
-            ///  Custom instruction configuration register.
-            CINSTRCONF: mmio.Mmio(packed struct(u32) {
-                ///  Opcode of Custom instruction.
-                OPCODE: u8,
-                ///  Length of custom instruction in number of bytes.
-                LENGTH: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Send opcode only.
-                        @"1B" = 0x1,
-                        ///  Send opcode, CINSTRDAT0.BYTE0.
-                        @"2B" = 0x2,
-                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE1.
-                        @"3B" = 0x3,
-                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE2.
-                        @"4B" = 0x4,
-                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT0.BYTE3.
-                        @"5B" = 0x5,
-                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE4.
-                        @"6B" = 0x6,
-                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE5.
-                        @"7B" = 0x7,
-                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE6.
-                        @"8B" = 0x8,
-                        ///  Send opcode, CINSTRDAT0.BYTE0 -> CINSTRDAT1.BYTE7.
-                        @"9B" = 0x9,
-                        _,
-                    },
-                },
-                ///  Level of the IO2 pin (if connected) during transmission of custom instruction.
-                LIO2: u1,
-                ///  Level of the IO3 pin (if connected) during transmission of custom instruction.
-                LIO3: u1,
-                ///  Wait for write complete before sending command.
-                WIPWAIT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No wait.
-                        Disable = 0x0,
-                        ///  Wait.
-                        Enable = 0x1,
-                    },
-                },
-                ///  Send WREN (write enable opcode 0x06) before instruction.
-                WREN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Do not send WREN.
-                        Disable = 0x0,
-                        ///  Send WREN.
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable long frame mode. When enabled, a custom instruction transaction has to be ended by writing the LFSTOP field.
-                LFEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Long frame mode disabled
-                        Disable = 0x0,
-                        ///  Long frame mode enabled
-                        Enable = 0x1,
-                    },
-                },
-                ///  Stop (finalize) long frame transaction
-                LFSTOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Stop
-                        Stop = 0x1,
-                        _,
-                    },
-                },
-                padding: u14,
-            }),
-            ///  Custom instruction data register 0.
-            CINSTRDAT0: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 0
-                BYTE0: u8,
-                ///  Data byte 1
-                BYTE1: u8,
-                ///  Data byte 2
-                BYTE2: u8,
-                ///  Data byte 3
-                BYTE3: u8,
-            }),
-            ///  Custom instruction data register 1.
-            CINSTRDAT1: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 4
-                BYTE4: u8,
-                ///  Data byte 5
-                BYTE5: u8,
-                ///  Data byte 6
-                BYTE6: u8,
-                ///  Data byte 7
-                BYTE7: u8,
-            }),
-            ///  SPI interface timing.
-            IFTIMING: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Timing related to sampling of the input serial data. The value of RXDELAY specifies the number of 64 MHz cycles (15.625 ns) delay from the the rising edge of the SPI Clock (SCK) until the input serial data is sampled. As en example, if set to 0 the input serial data is sampled on the rising edge of SCK.
-                RXDELAY: u3,
-                padding: u21,
-            }),
-        };
-
-        ///  Pulse width modulation unit 0
-        pub const PWM0 = extern struct {
-            reserved4: [4]u8,
-            ///  Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stops PWM pulse generation on all channels at the end of current PWM period, and stops sequence playback
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Description collection: Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.
-            TASKS_SEQSTART: [2]mmio.Mmio(packed struct(u32) {
-                ///  Loads the first PWM value on all enabled channels from sequence n, and starts playing that sequence at the rate defined in SEQ[n]REFRESH and/or DECODER.MODE. Causes PWM generation to start if not running.
-                TASKS_SEQSTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.
-            TASKS_NEXTSTEP: mmio.Mmio(packed struct(u32) {
-                ///  Steps by one value in the current sequence on all enabled channels if DECODER.MODE=NextStep. Does not cause PWM generation to start if not running.
-                TASKS_NEXTSTEP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved260: [240]u8,
-            ///  Response to STOP task, emitted when PWM pulses are no longer generated
-            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
-                ///  Response to STOP task, emitted when PWM pulses are no longer generated
-                EVENTS_STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Description collection: First PWM period started on sequence n
-            EVENTS_SEQSTARTED: [2]mmio.Mmio(packed struct(u32) {
-                ///  First PWM period started on sequence n
-                EVENTS_SEQSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Description collection: Emitted at end of every sequence n, when last value from RAM has been applied to wave counter
-            EVENTS_SEQEND: [2]mmio.Mmio(packed struct(u32) {
-                ///  Emitted at end of every sequence n, when last value from RAM has been applied to wave counter
-                EVENTS_SEQEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Emitted at the end of each PWM period
-            EVENTS_PWMPERIODEND: mmio.Mmio(packed struct(u32) {
-                ///  Emitted at the end of each PWM period
-                EVENTS_PWMPERIODEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Concatenated sequences have been played the amount of times defined in LOOP.CNT
-            EVENTS_LOOPSDONE: mmio.Mmio(packed struct(u32) {
-                ///  Concatenated sequences have been played the amount of times defined in LOOP.CNT
-                EVENTS_LOOPSDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [224]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between event SEQEND[0] and task STOP
-                SEQEND0_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event SEQEND[1] and task STOP
-                SEQEND1_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event LOOPSDONE and task SEQSTART[0]
-                LOOPSDONE_SEQSTART0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event LOOPSDONE and task SEQSTART[1]
-                LOOPSDONE_SEQSTART1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event LOOPSDONE and task STOP
-                LOOPSDONE_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Enable or disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event SEQSTARTED[0]
-                SEQSTARTED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event SEQSTARTED[1]
-                SEQSTARTED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event SEQEND[0]
-                SEQEND0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event SEQEND[1]
-                SEQEND1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event PWMPERIODEND
-                PWMPERIODEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event LOOPSDONE
-                LOOPSDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to enable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event SEQSTARTED[0]
-                SEQSTARTED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event SEQSTARTED[1]
-                SEQSTARTED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event SEQEND[0]
-                SEQEND0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event SEQEND[1]
-                SEQEND1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event PWMPERIODEND
-                PWMPERIODEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event LOOPSDONE
-                LOOPSDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event SEQSTARTED[0]
-                SEQSTARTED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event SEQSTARTED[1]
-                SEQSTARTED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event SEQEND[0]
-                SEQEND0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event SEQEND[1]
-                SEQEND1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event PWMPERIODEND
-                PWMPERIODEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event LOOPSDONE
-                LOOPSDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            reserved1280: [500]u8,
-            ///  PWM module enable register
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable PWM module
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Selects operating mode of the wave counter
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Selects up mode or up-and-down mode for the counter
-                UPDOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Up counter, edge-aligned PWM duty cycle
-                        Up = 0x0,
-                        ///  Up and down counter, center-aligned PWM duty cycle
-                        UpAndDown = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Value up to which the pulse generator counter counts
-            COUNTERTOP: mmio.Mmio(packed struct(u32) {
-                ///  Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM are used.
-                COUNTERTOP: u15,
-                padding: u17,
-            }),
-            ///  Configuration for PWM_CLK
-            PRESCALER: mmio.Mmio(packed struct(u32) {
-                ///  Prescaler of PWM_CLK
-                PRESCALER: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Divide by 1 (16 MHz)
-                        DIV_1 = 0x0,
-                        ///  Divide by 2 (8 MHz)
-                        DIV_2 = 0x1,
-                        ///  Divide by 4 (4 MHz)
-                        DIV_4 = 0x2,
-                        ///  Divide by 8 (2 MHz)
-                        DIV_8 = 0x3,
-                        ///  Divide by 16 (1 MHz)
-                        DIV_16 = 0x4,
-                        ///  Divide by 32 (500 kHz)
-                        DIV_32 = 0x5,
-                        ///  Divide by 64 (250 kHz)
-                        DIV_64 = 0x6,
-                        ///  Divide by 128 (125 kHz)
-                        DIV_128 = 0x7,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Configuration of the decoder
-            DECODER: mmio.Mmio(packed struct(u32) {
-                ///  How a sequence is read from RAM and spread to the compare register
-                LOAD: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  1st half word (16-bit) used in all PWM channels 0..3
-                        Common = 0x0,
-                        ///  1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3
-                        Grouped = 0x1,
-                        ///  1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3
-                        Individual = 0x2,
-                        ///  1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP
-                        WaveForm = 0x3,
-                    },
-                },
-                reserved8: u6,
-                ///  Selects source for advancing the active sequence
-                MODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  SEQ[n].REFRESH is used to determine loading internal compare registers
-                        RefreshCount = 0x0,
-                        ///  NEXTSTEP task causes a new value to be loaded to internal compare registers
-                        NextStep = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            ///  Number of playbacks of a loop
-            LOOP: mmio.Mmio(packed struct(u32) {
-                ///  Number of playbacks of pattern cycles
-                CNT: packed union {
-                    raw: u16,
-                    value: enum(u16) {
-                        ///  Looping disabled (stop at the end of the sequence)
-                        Disabled = 0x0,
-                        _,
-                    },
-                },
-                padding: u16,
-            }),
-        };
-
-        ///  Universal serial bus device
-        pub const USBD = extern struct {
-            reserved4: [4]u8,
-            ///  Description collection: Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host
-            TASKS_STARTEPIN: [8]mmio.Mmio(packed struct(u32) {
-                ///  Captures the EPIN[n].PTR and EPIN[n].MAXCNT registers values, and enables endpoint IN n to respond to traffic from host
-                TASKS_STARTEPIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint
-            TASKS_STARTISOIN: mmio.Mmio(packed struct(u32) {
-                ///  Captures the ISOIN.PTR and ISOIN.MAXCNT registers values, and enables sending data on ISO endpoint
-                TASKS_STARTISOIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Description collection: Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host
-            TASKS_STARTEPOUT: [8]mmio.Mmio(packed struct(u32) {
-                ///  Captures the EPOUT[n].PTR and EPOUT[n].MAXCNT registers values, and enables endpoint n to respond to traffic from host
-                TASKS_STARTEPOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint
-            TASKS_STARTISOOUT: mmio.Mmio(packed struct(u32) {
-                ///  Captures the ISOOUT.PTR and ISOOUT.MAXCNT registers values, and enables receiving of data on ISO endpoint
-                TASKS_STARTISOOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Allows OUT data stage on control endpoint 0
-            TASKS_EP0RCVOUT: mmio.Mmio(packed struct(u32) {
-                ///  Allows OUT data stage on control endpoint 0
-                TASKS_EP0RCVOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Allows status stage on control endpoint 0
-            TASKS_EP0STATUS: mmio.Mmio(packed struct(u32) {
-                ///  Allows status stage on control endpoint 0
-                TASKS_EP0STATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stalls data and status stage on control endpoint 0
-            TASKS_EP0STALL: mmio.Mmio(packed struct(u32) {
-                ///  Stalls data and status stage on control endpoint 0
-                TASKS_EP0STALL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Forces D+ and D- lines into the state defined in the DPDMVALUE register
-            TASKS_DPDMDRIVE: mmio.Mmio(packed struct(u32) {
-                ///  Forces D+ and D- lines into the state defined in the DPDMVALUE register
-                TASKS_DPDMDRIVE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stops forcing D+ and D- lines into any state (USB engine takes control)
-            TASKS_DPDMNODRIVE: mmio.Mmio(packed struct(u32) {
-                ///  Stops forcing D+ and D- lines into any state (USB engine takes control)
-                TASKS_DPDMNODRIVE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [160]u8,
-            ///  Signals that a USB reset condition has been detected on USB lines
-            EVENTS_USBRESET: mmio.Mmio(packed struct(u32) {
-                ///  Signals that a USB reset condition has been detected on USB lines
-                EVENTS_USBRESET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register
-            EVENTS_STARTED: mmio.Mmio(packed struct(u32) {
-                ///  Confirms that the EPIN[n].PTR and EPIN[n].MAXCNT, or EPOUT[n].PTR and EPOUT[n].MAXCNT registers have been captured on all endpoints reported in the EPSTATUS register
-                EVENTS_STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Description collection: The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
-            EVENTS_ENDEPIN: [8]mmio.Mmio(packed struct(u32) {
-                ///  The whole EPIN[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
-                EVENTS_ENDEPIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  An acknowledged data transfer has taken place on the control endpoint
-            EVENTS_EP0DATADONE: mmio.Mmio(packed struct(u32) {
-                ///  An acknowledged data transfer has taken place on the control endpoint
-                EVENTS_EP0DATADONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software.
-            EVENTS_ENDISOIN: mmio.Mmio(packed struct(u32) {
-                ///  The whole ISOIN buffer has been consumed. The RAM buffer can be accessed safely by software.
-                EVENTS_ENDISOIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Description collection: The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
-            EVENTS_ENDEPOUT: [8]mmio.Mmio(packed struct(u32) {
-                ///  The whole EPOUT[n] buffer has been consumed. The RAM buffer can be accessed safely by software.
-                EVENTS_ENDEPOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software.
-            EVENTS_ENDISOOUT: mmio.Mmio(packed struct(u32) {
-                ///  The whole ISOOUT buffer has been consumed. The RAM buffer can be accessed safely by software.
-                EVENTS_ENDISOOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Signals that a SOF (start of frame) condition has been detected on USB lines
-            EVENTS_SOF: mmio.Mmio(packed struct(u32) {
-                ///  Signals that a SOF (start of frame) condition has been detected on USB lines
-                EVENTS_SOF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause.
-            EVENTS_USBEVENT: mmio.Mmio(packed struct(u32) {
-                ///  An event or an error not covered by specific events has occurred. Check EVENTCAUSE register to find the cause.
-                EVENTS_USBEVENT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  A valid SETUP token has been received (and acknowledged) on the control endpoint
-            EVENTS_EP0SETUP: mmio.Mmio(packed struct(u32) {
-                ///  A valid SETUP token has been received (and acknowledged) on the control endpoint
-                EVENTS_EP0SETUP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register
-            EVENTS_EPDATA: mmio.Mmio(packed struct(u32) {
-                ///  A data transfer has occurred on a data endpoint, indicated by the EPDATASTATUS register
-                EVENTS_EPDATA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [156]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between event EP0DATADONE and task STARTEPIN[0]
-                EP0DATADONE_STARTEPIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event EP0DATADONE and task STARTEPOUT[0]
-                EP0DATADONE_STARTEPOUT0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event EP0DATADONE and task EP0STATUS
-                EP0DATADONE_EP0STATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event ENDEPOUT[0] and task EP0STATUS
-                ENDEPOUT0_EP0STATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event ENDEPOUT[0] and task EP0RCVOUT
-                ENDEPOUT0_EP0RCVOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for event USBRESET
-                USBRESET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPIN[0]
-                ENDEPIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPIN[1]
-                ENDEPIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPIN[2]
-                ENDEPIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPIN[3]
-                ENDEPIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPIN[4]
-                ENDEPIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPIN[5]
-                ENDEPIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPIN[6]
-                ENDEPIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPIN[7]
-                ENDEPIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event EP0DATADONE
-                EP0DATADONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDISOIN
-                ENDISOIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPOUT[0]
-                ENDEPOUT0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPOUT[1]
-                ENDEPOUT1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPOUT[2]
-                ENDEPOUT2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPOUT[3]
-                ENDEPOUT3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPOUT[4]
-                ENDEPOUT4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPOUT[5]
-                ENDEPOUT5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPOUT[6]
-                ENDEPOUT6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDEPOUT[7]
-                ENDEPOUT7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDISOOUT
-                ENDISOOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event SOF
-                SOF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event USBEVENT
-                USBEVENT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event EP0SETUP
-                EP0SETUP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event EPDATA
-                EPDATA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event USBRESET
-                USBRESET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPIN[0]
-                ENDEPIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPIN[1]
-                ENDEPIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPIN[2]
-                ENDEPIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPIN[3]
-                ENDEPIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPIN[4]
-                ENDEPIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPIN[5]
-                ENDEPIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPIN[6]
-                ENDEPIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPIN[7]
-                ENDEPIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event EP0DATADONE
-                EP0DATADONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDISOIN
-                ENDISOIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPOUT[0]
-                ENDEPOUT0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPOUT[1]
-                ENDEPOUT1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPOUT[2]
-                ENDEPOUT2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPOUT[3]
-                ENDEPOUT3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPOUT[4]
-                ENDEPOUT4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPOUT[5]
-                ENDEPOUT5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPOUT[6]
-                ENDEPOUT6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDEPOUT[7]
-                ENDEPOUT7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDISOOUT
-                ENDISOOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event SOF
-                SOF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event USBEVENT
-                USBEVENT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event EP0SETUP
-                EP0SETUP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event EPDATA
-                EPDATA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event USBRESET
-                USBRESET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPIN[0]
-                ENDEPIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPIN[1]
-                ENDEPIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPIN[2]
-                ENDEPIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPIN[3]
-                ENDEPIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPIN[4]
-                ENDEPIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPIN[5]
-                ENDEPIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPIN[6]
-                ENDEPIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPIN[7]
-                ENDEPIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event EP0DATADONE
-                EP0DATADONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDISOIN
-                ENDISOIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPOUT[0]
-                ENDEPOUT0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPOUT[1]
-                ENDEPOUT1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPOUT[2]
-                ENDEPOUT2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPOUT[3]
-                ENDEPOUT3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPOUT[4]
-                ENDEPOUT4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPOUT[5]
-                ENDEPOUT5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPOUT[6]
-                ENDEPOUT6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDEPOUT[7]
-                ENDEPOUT7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDISOOUT
-                ENDISOOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event SOF
-                SOF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event USBEVENT
-                USBEVENT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event EP0SETUP
-                EP0SETUP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event EPDATA
-                EPDATA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            reserved1024: [244]u8,
-            ///  Details on what caused the USBEVENT event
-            EVENTCAUSE: mmio.Mmio(packed struct(u32) {
-                ///  CRC error was detected on isochronous OUT endpoint 8. Write '1' to clear.
-                ISOOUTCRC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No error detected
-                        NotDetected = 0x0,
-                        ///  Error detected
-                        Detected = 0x1,
-                    },
-                },
-                reserved8: u7,
-                ///  Signals that USB lines have been idle long enough for the device to enter suspend. Write '1' to clear.
-                SUSPEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Suspend not detected
-                        NotDetected = 0x0,
-                        ///  Suspend detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  Signals that a RESUME condition (K state or activity restart) has been detected on USB lines. Write '1' to clear.
-                RESUME: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Resume not detected
-                        NotDetected = 0x0,
-                        ///  Resume detected
-                        Detected = 0x1,
-                    },
-                },
-                ///  USB MAC has been woken up and operational. Write '1' to clear.
-                USBWUALLOWED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Wake up not allowed
-                        NotAllowed = 0x0,
-                        ///  Wake up allowed
-                        Allowed = 0x1,
-                    },
-                },
-                ///  USB device is ready for normal operation. Write '1' to clear.
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  USBEVENT was not issued due to USBD peripheral ready
-                        NotDetected = 0x0,
-                        ///  USBD peripheral is ready
-                        Ready = 0x1,
-                    },
-                },
-                padding: u20,
-            }),
-            reserved1128: [100]u8,
-            ///  Provides information on which endpoint's EasyDMA registers have been captured
-            EPSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPIN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPIN8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                reserved16: u7,
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPOUT0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPOUT1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPOUT2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPOUT3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPOUT4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPOUT5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPOUT6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPOUT7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Captured state of endpoint's EasyDMA registers. Write '1' to clear.
-                EPOUT8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  EasyDMA registers have not been captured for this endpoint
-                        NoData = 0x0,
-                        ///  EasyDMA registers have been captured for this endpoint
-                        DataDone = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            ///  Provides information on which endpoint(s) an acknowledged data transfer has occurred (EPDATA event)
-            EPDATASTATUS: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
-                EPIN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotDone = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
-                EPIN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotDone = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
-                EPIN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotDone = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
-                EPIN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotDone = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
-                EPIN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotDone = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
-                EPIN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotDone = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        DataDone = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this IN endpoint. Write '1' to clear.
-                EPIN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotDone = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        DataDone = 0x1,
-                    },
-                },
-                reserved17: u9,
-                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
-                EPOUT1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotStarted = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        Started = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
-                EPOUT2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotStarted = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        Started = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
-                EPOUT3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotStarted = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        Started = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
-                EPOUT4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotStarted = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        Started = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
-                EPOUT5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotStarted = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        Started = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
-                EPOUT6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotStarted = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        Started = 0x1,
-                    },
-                },
-                ///  Acknowledged data transfer on this OUT endpoint. Write '1' to clear.
-                EPOUT7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No acknowledged data transfer on this endpoint
-                        NotStarted = 0x0,
-                        ///  Acknowledged data transfer on this endpoint has occurred
-                        Started = 0x1,
-                    },
-                },
-                padding: u8,
-            }),
-            ///  Device USB address
-            USBADDR: mmio.Mmio(packed struct(u32) {
-                ///  Device USB address
-                ADDR: u7,
-                padding: u25,
-            }),
-            reserved1152: [12]u8,
-            ///  SETUP data, byte 0, bmRequestType
-            BMREQUESTTYPE: mmio.Mmio(packed struct(u32) {
-                ///  Data transfer type
-                RECIPIENT: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        ///  Device
-                        Device = 0x0,
-                        ///  Interface
-                        Interface = 0x1,
-                        ///  Endpoint
-                        Endpoint = 0x2,
-                        ///  Other
-                        Other = 0x3,
-                        _,
-                    },
-                },
-                ///  Data transfer type
-                TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Standard
-                        Standard = 0x0,
-                        ///  Class
-                        Class = 0x1,
-                        ///  Vendor
-                        Vendor = 0x2,
-                        _,
-                    },
-                },
-                ///  Data transfer direction
-                DIRECTION: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Host-to-device
-                        HostToDevice = 0x0,
-                        ///  Device-to-host
-                        DeviceToHost = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  SETUP data, byte 1, bRequest
-            BREQUEST: mmio.Mmio(packed struct(u32) {
-                ///  SETUP data, byte 1, bRequest. Values provided for standard requests only, user must implement class and vendor values.
-                BREQUEST: packed union {
-                    raw: u8,
-                    value: enum(u8) {
-                        ///  Standard request GET_STATUS
-                        STD_GET_STATUS = 0x0,
-                        ///  Standard request CLEAR_FEATURE
-                        STD_CLEAR_FEATURE = 0x1,
-                        ///  Standard request SET_FEATURE
-                        STD_SET_FEATURE = 0x3,
-                        ///  Standard request SET_ADDRESS
-                        STD_SET_ADDRESS = 0x5,
-                        ///  Standard request GET_DESCRIPTOR
-                        STD_GET_DESCRIPTOR = 0x6,
-                        ///  Standard request SET_DESCRIPTOR
-                        STD_SET_DESCRIPTOR = 0x7,
-                        ///  Standard request GET_CONFIGURATION
-                        STD_GET_CONFIGURATION = 0x8,
-                        ///  Standard request SET_CONFIGURATION
-                        STD_SET_CONFIGURATION = 0x9,
-                        ///  Standard request GET_INTERFACE
-                        STD_GET_INTERFACE = 0xa,
-                        ///  Standard request SET_INTERFACE
-                        STD_SET_INTERFACE = 0xb,
-                        ///  Standard request SYNCH_FRAME
-                        STD_SYNCH_FRAME = 0xc,
-                        _,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  SETUP data, byte 2, LSB of wValue
-            WVALUEL: mmio.Mmio(packed struct(u32) {
-                ///  SETUP data, byte 2, LSB of wValue
-                WVALUEL: u8,
-                padding: u24,
-            }),
-            ///  SETUP data, byte 3, MSB of wValue
-            WVALUEH: mmio.Mmio(packed struct(u32) {
-                ///  SETUP data, byte 3, MSB of wValue
-                WVALUEH: u8,
-                padding: u24,
-            }),
-            ///  SETUP data, byte 4, LSB of wIndex
-            WINDEXL: mmio.Mmio(packed struct(u32) {
-                ///  SETUP data, byte 4, LSB of wIndex
-                WINDEXL: u8,
-                padding: u24,
-            }),
-            ///  SETUP data, byte 5, MSB of wIndex
-            WINDEXH: mmio.Mmio(packed struct(u32) {
-                ///  SETUP data, byte 5, MSB of wIndex
-                WINDEXH: u8,
-                padding: u24,
-            }),
-            ///  SETUP data, byte 6, LSB of wLength
-            WLENGTHL: mmio.Mmio(packed struct(u32) {
-                ///  SETUP data, byte 6, LSB of wLength
-                WLENGTHL: u8,
-                padding: u24,
-            }),
-            ///  SETUP data, byte 7, MSB of wLength
-            WLENGTHH: mmio.Mmio(packed struct(u32) {
-                ///  SETUP data, byte 7, MSB of wLength
-                WLENGTHH: u8,
-                padding: u24,
-            }),
-            reserved1280: [96]u8,
-            ///  Enable USB
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable USB
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  USB peripheral is disabled
-                        Disabled = 0x0,
-                        ///  USB peripheral is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Control of the USB pull-up
-            USBPULLUP: mmio.Mmio(packed struct(u32) {
-                ///  Control of the USB pull-up on the D+ line
-                CONNECT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pull-up is disconnected
-                        Disabled = 0x0,
-                        ///  Pull-up is connected to D+
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  State D+ and D- lines will be forced into by the DPDMDRIVE task. The DPDMNODRIVE task reverts the control of the lines to MAC IP (no forcing).
-            DPDMVALUE: mmio.Mmio(packed struct(u32) {
-                ///  State D+ and D- lines will be forced into by the DPDMDRIVE task
-                STATE: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        ///  D+ forced low, D- forced high (K state) for a timing preset in hardware (50 us or 5 ms, depending on bus state)
-                        Resume = 0x1,
-                        ///  D+ forced high, D- forced low (J state)
-                        J = 0x2,
-                        ///  D+ forced low, D- forced high (K state)
-                        K = 0x4,
-                        _,
-                    },
-                },
-                padding: u27,
-            }),
-            ///  Data toggle control and status
-            DTOGGLE: mmio.Mmio(packed struct(u32) {
-                ///  Select bulk endpoint number
-                EP: u3,
-                reserved7: u4,
-                ///  Selects IN or OUT endpoint
-                IO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Selects OUT endpoint
-                        Out = 0x0,
-                        ///  Selects IN endpoint
-                        In = 0x1,
-                    },
-                },
-                ///  Data toggle value
-                VALUE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  No action on data toggle when writing the register with this value
-                        Nop = 0x0,
-                        ///  Data toggle is DATA0 on endpoint set by EP and IO
-                        Data0 = 0x1,
-                        ///  Data toggle is DATA1 on endpoint set by EP and IO
-                        Data1 = 0x2,
-                        _,
-                    },
-                },
-                padding: u22,
-            }),
-            ///  Endpoint IN enable
-            EPINEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable IN endpoint 0
-                IN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint IN 0 (no response to IN tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint IN 0 (response to IN tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable IN endpoint 1
-                IN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint IN 1 (no response to IN tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint IN 1 (response to IN tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable IN endpoint 2
-                IN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint IN 2 (no response to IN tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint IN 2 (response to IN tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable IN endpoint 3
-                IN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint IN 3 (no response to IN tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint IN 3 (response to IN tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable IN endpoint 4
-                IN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint IN 4 (no response to IN tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint IN 4 (response to IN tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable IN endpoint 5
-                IN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint IN 5 (no response to IN tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint IN 5 (response to IN tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable IN endpoint 6
-                IN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint IN 6 (no response to IN tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint IN 6 (response to IN tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable IN endpoint 7
-                IN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint IN 7 (no response to IN tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint IN 7 (response to IN tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable ISO IN endpoint
-                ISOIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable ISO IN endpoint 8
-                        Disable = 0x0,
-                        ///  Enable ISO IN endpoint 8
-                        Enable = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            ///  Endpoint OUT enable
-            EPOUTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable OUT endpoint 0
-                OUT0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint OUT 0 (no response to OUT tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint OUT 0 (response to OUT tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable OUT endpoint 1
-                OUT1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint OUT 1 (no response to OUT tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint OUT 1 (response to OUT tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable OUT endpoint 2
-                OUT2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint OUT 2 (no response to OUT tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint OUT 2 (response to OUT tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable OUT endpoint 3
-                OUT3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint OUT 3 (no response to OUT tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint OUT 3 (response to OUT tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable OUT endpoint 4
-                OUT4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint OUT 4 (no response to OUT tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint OUT 4 (response to OUT tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable OUT endpoint 5
-                OUT5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint OUT 5 (no response to OUT tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint OUT 5 (response to OUT tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable OUT endpoint 6
-                OUT6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint OUT 6 (no response to OUT tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint OUT 6 (response to OUT tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable OUT endpoint 7
-                OUT7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable endpoint OUT 7 (no response to OUT tokens)
-                        Disable = 0x0,
-                        ///  Enable endpoint OUT 7 (response to OUT tokens)
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable ISO OUT endpoint 8
-                ISOOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable ISO OUT endpoint 8
-                        Disable = 0x0,
-                        ///  Enable ISO OUT endpoint 8
-                        Enable = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            ///  STALL endpoints
-            EPSTALL: mmio.Mmio(packed struct(u32) {
-                ///  Select endpoint number
-                EP: u3,
-                reserved7: u4,
-                ///  Selects IN or OUT endpoint
-                IO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Selects OUT endpoint
-                        Out = 0x0,
-                        ///  Selects IN endpoint
-                        In = 0x1,
-                    },
-                },
-                ///  Stall selected endpoint
-                STALL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Don't stall selected endpoint
-                        UnStall = 0x0,
-                        ///  Stall selected endpoint
-                        Stall = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            ///  Controls the split of ISO buffers
-            ISOSPLIT: mmio.Mmio(packed struct(u32) {
-                ///  Controls the split of ISO buffers
-                SPLIT: packed union {
-                    raw: u16,
-                    value: enum(u16) {
-                        ///  Full buffer dedicated to either iso IN or OUT
-                        OneDir = 0x0,
-                        ///  Lower half for IN, upper half for OUT
-                        HalfIN = 0x80,
-                        _,
-                    },
-                },
-                padding: u16,
-            }),
-            ///  Returns the current value of the start of frame counter
-            FRAMECNTR: mmio.Mmio(packed struct(u32) {
-                ///  Returns the current value of the start of frame counter
-                FRAMECNTR: u11,
-                padding: u21,
-            }),
-            reserved1324: [8]u8,
-            ///  Controls USBD peripheral low power mode during USB suspend
-            LOWPOWER: mmio.Mmio(packed struct(u32) {
-                ///  Controls USBD peripheral low-power mode during USB suspend
-                LOWPOWER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Software must write this value to exit low power mode and before performing a remote wake-up
-                        ForceNormal = 0x0,
-                        ///  Software must write this value to enter low power mode after DMA and software have finished interacting with the USB peripheral
-                        LowPower = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent
-            ISOINCONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Controls the response of the ISO IN endpoint to an IN token when no data is ready to be sent
-                RESPONSE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Endpoint does not respond in that case
-                        NoResp = 0x0,
-                        ///  Endpoint responds with a zero-length data packet in that case
-                        ZeroData = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  NFC-A compatible radio
-        pub const NFCT = extern struct {
-            ///  Activate NFCT peripheral for incoming and outgoing frames, change state to activated
-            TASKS_ACTIVATE: mmio.Mmio(packed struct(u32) {
-                ///  Activate NFCT peripheral for incoming and outgoing frames, change state to activated
-                TASKS_ACTIVATE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Disable NFCT peripheral
-            TASKS_DISABLE: mmio.Mmio(packed struct(u32) {
-                ///  Disable NFCT peripheral
-                TASKS_DISABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Enable NFC sense field mode, change state to sense mode
-            TASKS_SENSE: mmio.Mmio(packed struct(u32) {
-                ///  Enable NFC sense field mode, change state to sense mode
-                TASKS_SENSE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start transmission of an outgoing frame, change state to transmit
-            TASKS_STARTTX: mmio.Mmio(packed struct(u32) {
-                ///  Start transmission of an outgoing frame, change state to transmit
-                TASKS_STARTTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved28: [12]u8,
-            ///  Initializes the EasyDMA for receive.
-            TASKS_ENABLERXDATA: mmio.Mmio(packed struct(u32) {
-                ///  Initializes the EasyDMA for receive.
-                TASKS_ENABLERXDATA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved36: [4]u8,
-            ///  Force state machine to IDLE state
-            TASKS_GOIDLE: mmio.Mmio(packed struct(u32) {
-                ///  Force state machine to IDLE state
-                TASKS_GOIDLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Force state machine to SLEEP_A state
-            TASKS_GOSLEEP: mmio.Mmio(packed struct(u32) {
-                ///  Force state machine to SLEEP_A state
-                TASKS_GOSLEEP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [212]u8,
-            ///  The NFCT peripheral is ready to receive and send frames
-            EVENTS_READY: mmio.Mmio(packed struct(u32) {
-                ///  The NFCT peripheral is ready to receive and send frames
-                EVENTS_READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Remote NFC field detected
-            EVENTS_FIELDDETECTED: mmio.Mmio(packed struct(u32) {
-                ///  Remote NFC field detected
-                EVENTS_FIELDDETECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Remote NFC field lost
-            EVENTS_FIELDLOST: mmio.Mmio(packed struct(u32) {
-                ///  Remote NFC field lost
-                EVENTS_FIELDLOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Marks the start of the first symbol of a transmitted frame
-            EVENTS_TXFRAMESTART: mmio.Mmio(packed struct(u32) {
-                ///  Marks the start of the first symbol of a transmitted frame
-                EVENTS_TXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Marks the end of the last transmitted on-air symbol of a frame
-            EVENTS_TXFRAMEEND: mmio.Mmio(packed struct(u32) {
-                ///  Marks the end of the last transmitted on-air symbol of a frame
-                EVENTS_TXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Marks the end of the first symbol of a received frame
-            EVENTS_RXFRAMESTART: mmio.Mmio(packed struct(u32) {
-                ///  Marks the end of the first symbol of a received frame
-                EVENTS_RXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer
-            EVENTS_RXFRAMEEND: mmio.Mmio(packed struct(u32) {
-                ///  Received data has been checked (CRC, parity) and transferred to RAM, and EasyDMA has ended accessing the RX buffer
-                EVENTS_RXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  NFC error reported. The ERRORSTATUS register contains details on the source of the error.
-            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
-                ///  NFC error reported. The ERRORSTATUS register contains details on the source of the error.
-                EVENTS_ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved296: [8]u8,
-            ///  NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.
-            EVENTS_RXERROR: mmio.Mmio(packed struct(u32) {
-                ///  NFC RX frame error reported. The FRAMESTATUS.RX register contains details on the source of the error.
-                EVENTS_RXERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.
-            EVENTS_ENDRX: mmio.Mmio(packed struct(u32) {
-                ///  RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.
-                EVENTS_ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer
-            EVENTS_ENDTX: mmio.Mmio(packed struct(u32) {
-                ///  Transmission of data in RAM has ended, and EasyDMA has ended accessing the TX buffer
-                EVENTS_ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved312: [4]u8,
-            ///  Auto collision resolution process has started
-            EVENTS_AUTOCOLRESSTARTED: mmio.Mmio(packed struct(u32) {
-                ///  Auto collision resolution process has started
-                EVENTS_AUTOCOLRESSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved328: [12]u8,
-            ///  NFC auto collision resolution error reported.
-            EVENTS_COLLISION: mmio.Mmio(packed struct(u32) {
-                ///  NFC auto collision resolution error reported.
-                EVENTS_COLLISION: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  NFC auto collision resolution successfully completed
-            EVENTS_SELECTED: mmio.Mmio(packed struct(u32) {
-                ///  NFC auto collision resolution successfully completed
-                EVENTS_SELECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  EasyDMA is ready to receive or send frames.
-            EVENTS_STARTED: mmio.Mmio(packed struct(u32) {
-                ///  EasyDMA is ready to receive or send frames.
-                EVENTS_STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [172]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between event FIELDDETECTED and task ACTIVATE
-                FIELDDETECTED_ACTIVATE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event FIELDLOST and task SENSE
-                FIELDLOST_SENSE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                reserved5: u3,
-                ///  Shortcut between event TXFRAMEEND and task ENABLERXDATA
-                TXFRAMEEND_ENABLERXDATA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u26,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event FIELDDETECTED
-                FIELDDETECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event FIELDLOST
-                FIELDLOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TXFRAMESTART
-                TXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TXFRAMEEND
-                TXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event RXFRAMESTART
-                RXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event RXFRAMEEND
-                RXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u2,
-                ///  Enable or disable interrupt for event RXERROR
-                RXERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDRX
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event ENDTX
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved14: u1,
-                ///  Enable or disable interrupt for event AUTOCOLRESSTARTED
-                AUTOCOLRESSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u3,
-                ///  Enable or disable interrupt for event COLLISION
-                COLLISION: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event SELECTED
-                SELECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u11,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event FIELDDETECTED
-                FIELDDETECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event FIELDLOST
-                FIELDLOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TXFRAMESTART
-                TXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TXFRAMEEND
-                TXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event RXFRAMESTART
-                RXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event RXFRAMEEND
-                RXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u2,
-                ///  Write '1' to enable interrupt for event RXERROR
-                RXERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDRX
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDTX
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved14: u1,
-                ///  Write '1' to enable interrupt for event AUTOCOLRESSTARTED
-                AUTOCOLRESSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u3,
-                ///  Write '1' to enable interrupt for event COLLISION
-                COLLISION: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event SELECTED
-                SELECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u11,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event FIELDDETECTED
-                FIELDDETECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event FIELDLOST
-                FIELDLOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TXFRAMESTART
-                TXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TXFRAMEEND
-                TXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event RXFRAMESTART
-                RXFRAMESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event RXFRAMEEND
-                RXFRAMEEND: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved10: u2,
-                ///  Write '1' to disable interrupt for event RXERROR
-                RXERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDRX
-                ENDRX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDTX
-                ENDTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved14: u1,
-                ///  Write '1' to disable interrupt for event AUTOCOLRESSTARTED
-                AUTOCOLRESSTARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved18: u3,
-                ///  Write '1' to disable interrupt for event COLLISION
-                COLLISION: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event SELECTED
-                SELECTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u11,
-            }),
-            reserved1028: [248]u8,
-            ///  NFC Error Status register
-            ERRORSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX
-                FRAMEDELAYTIMEOUT: u1,
-                padding: u31,
-            }),
-            reserved1040: [8]u8,
-            ///  NfcTag state register
-            NFCTAGSTATE: mmio.Mmio(packed struct(u32) {
-                ///  NfcTag state
-                NFCTAGSTATE: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Disabled or sense
-                        Disabled = 0x0,
-                        ///  RampUp
-                        RampUp = 0x2,
-                        ///  Idle
-                        Idle = 0x3,
-                        ///  Receive
-                        Receive = 0x4,
-                        ///  FrameDelay
-                        FrameDelay = 0x5,
-                        ///  Transmit
-                        Transmit = 0x6,
-                        _,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1056: [12]u8,
-            ///  Sleep state during automatic collision resolution
-            SLEEPSTATE: mmio.Mmio(packed struct(u32) {
-                ///  Reflects the sleep state during automatic collision resolution. Set to IDLE by a GOIDLE task. Set to SLEEP_A when a valid SLEEP_REQ frame is received or by a GOSLEEP task.
-                SLEEPSTATE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  State is IDLE.
-                        Idle = 0x0,
-                        ///  State is SLEEP_A.
-                        SleepA = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1084: [24]u8,
-            ///  Indicates the presence or not of a valid field
-            FIELDPRESENT: mmio.Mmio(packed struct(u32) {
-                ///  Indicates if a valid field is present. Available only in the activated state.
-                FIELDPRESENT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No valid field detected
-                        NoField = 0x0,
-                        ///  Valid field detected
-                        FieldPresent = 0x1,
-                    },
-                },
-                ///  Indicates if the low level has locked to the field
-                LOCKDETECT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Not locked to field
-                        NotLocked = 0x0,
-                        ///  Locked to field
-                        Locked = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1284: [196]u8,
-            ///  Minimum frame delay
-            FRAMEDELAYMIN: mmio.Mmio(packed struct(u32) {
-                ///  Minimum frame delay in number of 13.56 MHz clocks
-                FRAMEDELAYMIN: u16,
-                padding: u16,
-            }),
-            ///  Maximum frame delay
-            FRAMEDELAYMAX: mmio.Mmio(packed struct(u32) {
-                ///  Maximum frame delay in number of 13.56 MHz clocks
-                FRAMEDELAYMAX: u20,
-                padding: u12,
-            }),
-            ///  Configuration register for the Frame Delay Timer
-            FRAMEDELAYMODE: mmio.Mmio(packed struct(u32) {
-                ///  Configuration register for the Frame Delay Timer
-                FRAMEDELAYMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout.
-                        FreeRun = 0x0,
-                        ///  Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX
-                        Window = 0x1,
-                        ///  Frame is transmitted exactly at FRAMEDELAYMAX
-                        ExactVal = 0x2,
-                        ///  Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX
-                        WindowGrid = 0x3,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Packet pointer for TXD and RXD data storage in Data RAM
-            PACKETPTR: mmio.Mmio(packed struct(u32) {
-                ///  Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte-aligned RAM address.
-                PTR: u32,
-            }),
-            ///  Size of the RAM buffer allocated to TXD and RXD data storage each
-            MAXLEN: mmio.Mmio(packed struct(u32) {
-                ///  Size of the RAM buffer allocated to TXD and RXD data storage each
-                MAXLEN: u9,
-                padding: u23,
-            }),
-            reserved1424: [120]u8,
-            ///  Last NFCID1 part (4, 7 or 10 bytes ID)
-            NFCID1_LAST: mmio.Mmio(packed struct(u32) {
-                ///  NFCID1 byte Z (very last byte sent)
-                NFCID1_Z: u8,
-                ///  NFCID1 byte Y
-                NFCID1_Y: u8,
-                ///  NFCID1 byte X
-                NFCID1_X: u8,
-                ///  NFCID1 byte W
-                NFCID1_W: u8,
-            }),
-            ///  Second last NFCID1 part (7 or 10 bytes ID)
-            NFCID1_2ND_LAST: mmio.Mmio(packed struct(u32) {
-                ///  NFCID1 byte V
-                NFCID1_V: u8,
-                ///  NFCID1 byte U
-                NFCID1_U: u8,
-                ///  NFCID1 byte T
-                NFCID1_T: u8,
-                padding: u8,
-            }),
-            ///  Third last NFCID1 part (10 bytes ID)
-            NFCID1_3RD_LAST: mmio.Mmio(packed struct(u32) {
-                ///  NFCID1 byte S
-                NFCID1_S: u8,
-                ///  NFCID1 byte R
-                NFCID1_R: u8,
-                ///  NFCID1 byte Q
-                NFCID1_Q: u8,
-                padding: u8,
-            }),
-            ///  Controls the auto collision resolution function. This setting must be done before the NFCT peripheral is enabled.
-            AUTOCOLRESCONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Enables/disables auto collision resolution
-                MODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Auto collision resolution enabled
-                        Enabled = 0x0,
-                        ///  Auto collision resolution disabled
-                        Disabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  NFC-A SENS_RES auto-response settings
-            SENSRES: mmio.Mmio(packed struct(u32) {
-                ///  Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
-                BITFRAMESDD: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        ///  SDD pattern 00000
-                        SDD00000 = 0x0,
-                        ///  SDD pattern 00001
-                        SDD00001 = 0x1,
-                        ///  SDD pattern 00010
-                        SDD00010 = 0x2,
-                        ///  SDD pattern 00100
-                        SDD00100 = 0x4,
-                        ///  SDD pattern 01000
-                        SDD01000 = 0x8,
-                        ///  SDD pattern 10000
-                        SDD10000 = 0x10,
-                        _,
-                    },
-                },
-                ///  Reserved for future use. Shall be 0.
-                RFU5: u1,
-                ///  NFCID1 size. This value is used by the auto collision resolution engine.
-                NFCIDSIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  NFCID1 size: single (4 bytes)
-                        NFCID1Single = 0x0,
-                        ///  NFCID1 size: double (7 bytes)
-                        NFCID1Double = 0x1,
-                        ///  NFCID1 size: triple (10 bytes)
-                        NFCID1Triple = 0x2,
-                        _,
-                    },
-                },
-                ///  Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
-                PLATFCONFIG: u4,
-                ///  Reserved for future use. Shall be 0.
-                RFU74: u4,
-                padding: u16,
-            }),
-            ///  NFC-A SEL_RES auto-response settings
-            SELRES: mmio.Mmio(packed struct(u32) {
-                ///  Reserved for future use. Shall be 0.
-                RFU10: u2,
-                ///  Cascade as defined by the b3 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification (controlled by hardware, shall be 0)
-                CASCADE: u1,
-                ///  Reserved for future use. Shall be 0.
-                RFU43: u2,
-                ///  Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification
-                PROTOCOL: u2,
-                ///  Reserved for future use. Shall be 0.
-                RFU7: u1,
-                padding: u24,
-            }),
-        };
-
-        ///  GPIO Tasks and Events
-        pub const GPIOTE = extern struct {
-            ///  Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
-            TASKS_OUT: [8]mmio.Mmio(packed struct(u32) {
-                ///  Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is configured in CONFIG[n].POLARITY.
-                TASKS_OUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved48: [16]u8,
-            ///  Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
-            TASKS_SET: [8]mmio.Mmio(packed struct(u32) {
-                ///  Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it high.
-                TASKS_SET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved96: [16]u8,
-            ///  Description collection: Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
-            TASKS_CLR: [8]mmio.Mmio(packed struct(u32) {
-                ///  Task for writing to pin specified in CONFIG[n].PSEL. Action on pin is to set it low.
-                TASKS_CLR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [128]u8,
-            ///  Description collection: Event generated from pin specified in CONFIG[n].PSEL
-            EVENTS_IN: [8]mmio.Mmio(packed struct(u32) {
-                ///  Event generated from pin specified in CONFIG[n].PSEL
-                EVENTS_IN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved380: [92]u8,
-            ///  Event generated from multiple input GPIO pins with SENSE mechanism enabled
-            EVENTS_PORT: mmio.Mmio(packed struct(u32) {
-                ///  Event generated from multiple input GPIO pins with SENSE mechanism enabled
-                EVENTS_PORT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [388]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event IN[0]
-                IN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event IN[1]
-                IN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event IN[2]
-                IN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event IN[3]
-                IN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event IN[4]
-                IN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event IN[5]
-                IN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event IN[6]
-                IN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event IN[7]
-                IN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved31: u23,
-                ///  Write '1' to enable interrupt for event PORT
-                PORT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event IN[0]
-                IN0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event IN[1]
-                IN1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event IN[2]
-                IN2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event IN[3]
-                IN3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event IN[4]
-                IN4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event IN[5]
-                IN5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event IN[6]
-                IN6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event IN[7]
-                IN7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved31: u23,
-                ///  Write '1' to disable interrupt for event PORT
-                PORT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            reserved1296: [516]u8,
-            ///  Description collection: Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event
-            CONFIG: [8]mmio.Mmio(packed struct(u32) {
-                ///  Mode
-                MODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module.
-                        Disabled = 0x0,
-                        ///  Event mode
-                        Event = 0x1,
-                        ///  Task mode
-                        Task = 0x3,
-                        _,
-                    },
-                },
-                reserved8: u6,
-                ///  GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event
-                PSEL: u5,
-                ///  Port number
-                PORT: u1,
-                reserved16: u2,
-                ///  When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event.
-                POLARITY: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity.
-                        None = 0x0,
-                        ///  Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin.
-                        LoToHi = 0x1,
-                        ///  Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin.
-                        HiToLo = 0x2,
-                        ///  Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin.
-                        Toggle = 0x3,
-                    },
-                },
-                reserved20: u2,
-                ///  When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect.
-                OUTINIT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Task mode: Initial value of pin before task triggering is low
-                        Low = 0x0,
-                        ///  Task mode: Initial value of pin before task triggering is high
-                        High = 0x1,
-                    },
-                },
-                padding: u11,
-            }),
-        };
-
-        ///  Successive approximation register (SAR) analog-to-digital converter
-        pub const SAADC = extern struct {
-            ///  Starts the SAADC and prepares the result buffer in RAM
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Starts the SAADC and prepares the result buffer in RAM
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Takes one SAADC sample
-            TASKS_SAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  Takes one SAADC sample
-                TASKS_SAMPLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stops the SAADC and terminates all on-going conversions
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stops the SAADC and terminates all on-going conversions
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Starts offset auto-calibration
-            TASKS_CALIBRATEOFFSET: mmio.Mmio(packed struct(u32) {
-                ///  Starts offset auto-calibration
-                TASKS_CALIBRATEOFFSET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [240]u8,
-            ///  The SAADC has started
-            EVENTS_STARTED: mmio.Mmio(packed struct(u32) {
-                ///  The SAADC has started
-                EVENTS_STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  The SAADC has filled up the result buffer
-            EVENTS_END: mmio.Mmio(packed struct(u32) {
-                ///  The SAADC has filled up the result buffer
-                EVENTS_END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.
-            EVENTS_DONE: mmio.Mmio(packed struct(u32) {
-                ///  A conversion task has been completed. Depending on the configuration, multiple conversions might be needed for a result to be transferred to RAM.
-                EVENTS_DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Result ready for transfer to RAM
-            EVENTS_RESULTDONE: mmio.Mmio(packed struct(u32) {
-                ///  Result ready for transfer to RAM
-                EVENTS_RESULTDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Calibration is complete
-            EVENTS_CALIBRATEDONE: mmio.Mmio(packed struct(u32) {
-                ///  Calibration is complete
-                EVENTS_CALIBRATEDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  The SAADC has stopped
-            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
-                ///  The SAADC has stopped
-                EVENTS_STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved768: [488]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event DONE
-                DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event RESULTDONE
-                RESULTDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CALIBRATEDONE
-                CALIBRATEDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH0LIMITH
-                CH0LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH0LIMITL
-                CH0LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH1LIMITH
-                CH1LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH1LIMITL
-                CH1LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH2LIMITH
-                CH2LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH2LIMITL
-                CH2LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH3LIMITH
-                CH3LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH3LIMITL
-                CH3LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH4LIMITH
-                CH4LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH4LIMITL
-                CH4LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH5LIMITH
-                CH5LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH5LIMITL
-                CH5LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH6LIMITH
-                CH6LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH6LIMITL
-                CH6LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH7LIMITH
-                CH7LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CH7LIMITL
-                CH7LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u10,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event DONE
-                DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event RESULTDONE
-                RESULTDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CALIBRATEDONE
-                CALIBRATEDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH0LIMITH
-                CH0LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH0LIMITL
-                CH0LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH1LIMITH
-                CH1LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH1LIMITL
-                CH1LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH2LIMITH
-                CH2LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH2LIMITL
-                CH2LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH3LIMITH
-                CH3LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH3LIMITL
-                CH3LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH4LIMITH
-                CH4LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH4LIMITL
-                CH4LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH5LIMITH
-                CH5LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH5LIMITL
-                CH5LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH6LIMITH
-                CH6LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH6LIMITL
-                CH6LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH7LIMITH
-                CH7LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CH7LIMITL
-                CH7LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u10,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event STARTED
-                STARTED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event DONE
-                DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event RESULTDONE
-                RESULTDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CALIBRATEDONE
-                CALIBRATEDONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH0LIMITH
-                CH0LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH0LIMITL
-                CH0LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH1LIMITH
-                CH1LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH1LIMITL
-                CH1LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH2LIMITH
-                CH2LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH2LIMITL
-                CH2LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH3LIMITH
-                CH3LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH3LIMITL
-                CH3LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH4LIMITH
-                CH4LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH4LIMITL
-                CH4LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH5LIMITH
-                CH5LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH5LIMITL
-                CH5LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH6LIMITH
-                CH6LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH6LIMITL
-                CH6LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH7LIMITH
-                CH7LIMITH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CH7LIMITL
-                CH7LIMITL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u10,
-            }),
-            reserved1024: [244]u8,
-            ///  Status
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  Status
-                STATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  SAADC is ready. No on-going conversions.
-                        Ready = 0x0,
-                        ///  SAADC is busy. Conversion in progress.
-                        Busy = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1280: [252]u8,
-            ///  Enable or disable SAADC
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable SAADC
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable SAADC
-                        Disabled = 0x0,
-                        ///  Enable SAADC
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1520: [236]u8,
-            ///  Resolution configuration
-            RESOLUTION: mmio.Mmio(packed struct(u32) {
-                ///  Set the resolution
-                VAL: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  8 bits
-                        @"8bit" = 0x0,
-                        ///  10 bits
-                        @"10bit" = 0x1,
-                        ///  12 bits
-                        @"12bit" = 0x2,
-                        ///  14 bits
-                        @"14bit" = 0x3,
-                        _,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Oversampling configuration. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used.
-            OVERSAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  Oversample control
-                OVERSAMPLE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Bypass oversampling
-                        Bypass = 0x0,
-                        ///  Oversample 2x
-                        Over2x = 0x1,
-                        ///  Oversample 4x
-                        Over4x = 0x2,
-                        ///  Oversample 8x
-                        Over8x = 0x3,
-                        ///  Oversample 16x
-                        Over16x = 0x4,
-                        ///  Oversample 32x
-                        Over32x = 0x5,
-                        ///  Oversample 64x
-                        Over64x = 0x6,
-                        ///  Oversample 128x
-                        Over128x = 0x7,
-                        ///  Oversample 256x
-                        Over256x = 0x8,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Controls normal or continuous sample rate
-            SAMPLERATE: mmio.Mmio(packed struct(u32) {
-                ///  Capture and compare value. Sample rate is 16 MHz/CC
-                CC: u11,
-                reserved12: u1,
-                ///  Select mode for sample rate control
-                MODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Rate is controlled from SAMPLE task
-                        Task = 0x0,
-                        ///  Rate is controlled from local timer (use CC to control the rate)
-                        Timers = 0x1,
-                    },
-                },
-                padding: u19,
-            }),
-        };
-
-        ///  Timer/Counter 0
-        pub const TIMER0 = extern struct {
-            ///  Start Timer
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Start Timer
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop Timer
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop Timer
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Increment Timer (Counter mode only)
-            TASKS_COUNT: mmio.Mmio(packed struct(u32) {
-                ///  Increment Timer (Counter mode only)
-                TASKS_COUNT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Clear time
-            TASKS_CLEAR: mmio.Mmio(packed struct(u32) {
-                ///  Clear time
-                TASKS_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Deprecated register - Shut down timer
-            TASKS_SHUTDOWN: mmio.Mmio(packed struct(u32) {
-                ///  Deprecated field - Shut down timer
-                TASKS_SHUTDOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved64: [44]u8,
-            ///  Description collection: Capture Timer value to CC[n] register
-            TASKS_CAPTURE: [6]mmio.Mmio(packed struct(u32) {
-                ///  Capture Timer value to CC[n] register
-                TASKS_CAPTURE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved320: [232]u8,
-            ///  Description collection: Compare event on CC[n] match
-            EVENTS_COMPARE: [6]mmio.Mmio(packed struct(u32) {
-                ///  Compare event on CC[n] match
-                EVENTS_COMPARE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [168]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between event COMPARE[0] and task CLEAR
-                COMPARE0_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event COMPARE[1] and task CLEAR
-                COMPARE1_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event COMPARE[2] and task CLEAR
-                COMPARE2_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event COMPARE[3] and task CLEAR
-                COMPARE3_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event COMPARE[4] and task CLEAR
-                COMPARE4_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event COMPARE[5] and task CLEAR
-                COMPARE5_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                reserved8: u2,
-                ///  Shortcut between event COMPARE[0] and task STOP
-                COMPARE0_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event COMPARE[1] and task STOP
-                COMPARE1_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event COMPARE[2] and task STOP
-                COMPARE2_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event COMPARE[3] and task STOP
-                COMPARE3_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event COMPARE[4] and task STOP
-                COMPARE4_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event COMPARE[5] and task STOP
-                COMPARE5_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u18,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  Write '1' to enable interrupt for event COMPARE[0]
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event COMPARE[1]
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event COMPARE[2]
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event COMPARE[3]
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event COMPARE[4]
-                COMPARE4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event COMPARE[5]
-                COMPARE5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u10,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  Write '1' to disable interrupt for event COMPARE[0]
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event COMPARE[1]
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event COMPARE[2]
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event COMPARE[3]
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event COMPARE[4]
-                COMPARE4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event COMPARE[5]
-                COMPARE5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u10,
-            }),
-            reserved1284: [504]u8,
-            ///  Timer mode selection
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Timer mode
-                MODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Select Timer mode
-                        Timer = 0x0,
-                        ///  Deprecated enumerator - Select Counter mode
-                        Counter = 0x1,
-                        ///  Select Low Power Counter mode
-                        LowPowerCounter = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Configure the number of bits used by the TIMER
-            BITMODE: mmio.Mmio(packed struct(u32) {
-                ///  Timer bit width
-                BITMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  16 bit timer bit width
-                        @"16Bit" = 0x0,
-                        ///  8 bit timer bit width
-                        @"08Bit" = 0x1,
-                        ///  24 bit timer bit width
-                        @"24Bit" = 0x2,
-                        ///  32 bit timer bit width
-                        @"32Bit" = 0x3,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1296: [4]u8,
-            ///  Timer prescaler register
-            PRESCALER: mmio.Mmio(packed struct(u32) {
-                ///  Prescaler value
-                PRESCALER: u4,
-                padding: u28,
-            }),
-            reserved1344: [44]u8,
-            ///  Description collection: Capture/Compare register n
-            CC: [6]mmio.Mmio(packed struct(u32) {
-                ///  Capture/Compare value
-                CC: u32,
-            }),
-        };
-
-        ///  FPU
-        pub const FPU = extern struct {
-            ///  Unused.
-            UNUSED: u32,
-        };
-
-        ///  Inter-IC Sound
-        pub const I2S = extern struct {
-            ///  Starts continuous I2S transfer. Also starts MCK generator when this is enabled.
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Starts continuous I2S transfer. Also starts MCK generator when this is enabled.
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stops I2S transfer. Also stops MCK generator. Triggering this task will cause the STOPPED event to be generated.
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved260: [252]u8,
-            ///  The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.
-            EVENTS_RXPTRUPD: mmio.Mmio(packed struct(u32) {
-                ///  The RXD.PTR register has been copied to internal double-buffers. When the I2S module is started and RX is enabled, this event will be generated for every RXTXD.MAXCNT words that are received on the SDIN pin.
-                EVENTS_RXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  I2S transfer stopped.
-            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
-                ///  I2S transfer stopped.
-                EVENTS_STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved276: [8]u8,
-            ///  The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
-            EVENTS_TXPTRUPD: mmio.Mmio(packed struct(u32) {
-                ///  The TDX.PTR register has been copied to internal double-buffers. When the I2S module is started and TX is enabled, this event will be generated for every RXTXD.MAXCNT words that are sent on the SDOUT pin.
-                EVENTS_TXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved768: [488]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Enable or disable interrupt for event RXPTRUPD
-                RXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved5: u2,
-                ///  Enable or disable interrupt for event TXPTRUPD
-                TXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u26,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to enable interrupt for event RXPTRUPD
-                RXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved5: u2,
-                ///  Write '1' to enable interrupt for event TXPTRUPD
-                TXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u26,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Write '1' to disable interrupt for event RXPTRUPD
-                RXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved5: u2,
-                ///  Write '1' to disable interrupt for event TXPTRUPD
-                TXPTRUPD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u26,
-            }),
-            reserved1280: [500]u8,
-            ///  Enable I2S module.
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable I2S module.
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  Real time counter 0
-        pub const RTC0 = extern struct {
-            ///  Start RTC COUNTER
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Start RTC COUNTER
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop RTC COUNTER
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop RTC COUNTER
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Clear RTC COUNTER
-            TASKS_CLEAR: mmio.Mmio(packed struct(u32) {
-                ///  Clear RTC COUNTER
-                TASKS_CLEAR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Set COUNTER to 0xFFFFF0
-            TASKS_TRIGOVRFLW: mmio.Mmio(packed struct(u32) {
-                ///  Set COUNTER to 0xFFFFF0
-                TASKS_TRIGOVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [240]u8,
-            ///  Event on COUNTER increment
-            EVENTS_TICK: mmio.Mmio(packed struct(u32) {
-                ///  Event on COUNTER increment
-                EVENTS_TICK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Event on COUNTER overflow
-            EVENTS_OVRFLW: mmio.Mmio(packed struct(u32) {
-                ///  Event on COUNTER overflow
-                EVENTS_OVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved320: [56]u8,
-            ///  Description collection: Compare event on CC[n] match
-            EVENTS_COMPARE: [4]mmio.Mmio(packed struct(u32) {
-                ///  Compare event on CC[n] match
-                EVENTS_COMPARE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [436]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event TICK
-                TICK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event OVRFLW
-                OVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Write '1' to enable interrupt for event COMPARE[0]
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event COMPARE[1]
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event COMPARE[2]
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event COMPARE[3]
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event TICK
-                TICK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event OVRFLW
-                OVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Write '1' to disable interrupt for event COMPARE[0]
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event COMPARE[1]
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event COMPARE[2]
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event COMPARE[3]
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            reserved832: [52]u8,
-            ///  Enable or disable event routing
-            EVTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable event routing for event TICK
-                TICK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Disable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable event routing for event OVRFLW
-                OVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Disable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Enable or disable event routing for event COMPARE[0]
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Disable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable event routing for event COMPARE[1]
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Disable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable event routing for event COMPARE[2]
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Disable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable event routing for event COMPARE[3]
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Disable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            ///  Enable event routing
-            EVTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable event routing for event TICK
-                TICK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable event routing for event OVRFLW
-                OVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Write '1' to enable event routing for event COMPARE[0]
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable event routing for event COMPARE[1]
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable event routing for event COMPARE[2]
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable event routing for event COMPARE[3]
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            ///  Disable event routing
-            EVTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable event routing for event TICK
-                TICK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable event routing for event OVRFLW
-                OVRFLW: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved16: u14,
-                ///  Write '1' to disable event routing for event COMPARE[0]
-                COMPARE0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable event routing for event COMPARE[1]
-                COMPARE1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable event routing for event COMPARE[2]
-                COMPARE2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable event routing for event COMPARE[3]
-                COMPARE3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u12,
-            }),
-            reserved1284: [440]u8,
-            ///  Current COUNTER value
-            COUNTER: mmio.Mmio(packed struct(u32) {
-                ///  Counter value
-                COUNTER: u24,
-                padding: u8,
-            }),
-            ///  12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped
-            PRESCALER: mmio.Mmio(packed struct(u32) {
-                ///  Prescaler value
-                PRESCALER: u12,
-                padding: u20,
-            }),
-            reserved1344: [52]u8,
-            ///  Description collection: Compare register n
-            CC: [4]mmio.Mmio(packed struct(u32) {
-                ///  Compare value
-                COMPARE: u24,
-                padding: u8,
-            }),
-        };
-
-        ///  Temperature Sensor
-        pub const TEMP = extern struct {
-            ///  Start temperature measurement
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Start temperature measurement
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop temperature measurement
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop temperature measurement
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [248]u8,
-            ///  Temperature measurement complete, data ready
-            EVENTS_DATARDY: mmio.Mmio(packed struct(u32) {
-                ///  Temperature measurement complete, data ready
-                EVENTS_DATARDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [512]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event DATARDY
-                DATARDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event DATARDY
-                DATARDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1288: [508]u8,
-            ///  Temperature in degC (0.25deg steps)
-            TEMP: mmio.Mmio(packed struct(u32) {
-                ///  Temperature in degC (0.25deg steps)
-                TEMP: u32,
-            }),
-            reserved1312: [20]u8,
-            ///  Slope of 1st piece wise linear function
-            A0: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 1st piece wise linear function
-                A0: u12,
-                padding: u20,
-            }),
-            ///  Slope of 2nd piece wise linear function
-            A1: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 2nd piece wise linear function
-                A1: u12,
-                padding: u20,
-            }),
-            ///  Slope of 3rd piece wise linear function
-            A2: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 3rd piece wise linear function
-                A2: u12,
-                padding: u20,
-            }),
-            ///  Slope of 4th piece wise linear function
-            A3: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 4th piece wise linear function
-                A3: u12,
-                padding: u20,
-            }),
-            ///  Slope of 5th piece wise linear function
-            A4: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 5th piece wise linear function
-                A4: u12,
-                padding: u20,
-            }),
-            ///  Slope of 6th piece wise linear function
-            A5: mmio.Mmio(packed struct(u32) {
-                ///  Slope of 6th piece wise linear function
-                A5: u12,
-                padding: u20,
-            }),
-            reserved1344: [8]u8,
-            ///  y-intercept of 1st piece wise linear function
-            B0: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 1st piece wise linear function
-                B0: u14,
-                padding: u18,
-            }),
-            ///  y-intercept of 2nd piece wise linear function
-            B1: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 2nd piece wise linear function
-                B1: u14,
-                padding: u18,
-            }),
-            ///  y-intercept of 3rd piece wise linear function
-            B2: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 3rd piece wise linear function
-                B2: u14,
-                padding: u18,
-            }),
-            ///  y-intercept of 4th piece wise linear function
-            B3: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 4th piece wise linear function
-                B3: u14,
-                padding: u18,
-            }),
-            ///  y-intercept of 5th piece wise linear function
-            B4: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 5th piece wise linear function
-                B4: u14,
-                padding: u18,
-            }),
-            ///  y-intercept of 6th piece wise linear function
-            B5: mmio.Mmio(packed struct(u32) {
-                ///  y-intercept of 6th piece wise linear function
-                B5: u14,
-                padding: u18,
-            }),
-            reserved1376: [8]u8,
-            ///  End point of 1st piece wise linear function
-            T0: mmio.Mmio(packed struct(u32) {
-                ///  End point of 1st piece wise linear function
-                T0: u8,
-                padding: u24,
-            }),
-            ///  End point of 2nd piece wise linear function
-            T1: mmio.Mmio(packed struct(u32) {
-                ///  End point of 2nd piece wise linear function
-                T1: u8,
-                padding: u24,
-            }),
-            ///  End point of 3rd piece wise linear function
-            T2: mmio.Mmio(packed struct(u32) {
-                ///  End point of 3rd piece wise linear function
-                T2: u8,
-                padding: u24,
-            }),
-            ///  End point of 4th piece wise linear function
-            T3: mmio.Mmio(packed struct(u32) {
-                ///  End point of 4th piece wise linear function
-                T3: u8,
-                padding: u24,
-            }),
-            ///  End point of 5th piece wise linear function
-            T4: mmio.Mmio(packed struct(u32) {
-                ///  End point of 5th piece wise linear function
-                T4: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  Random Number Generator
-        pub const RNG = extern struct {
-            ///  Task starting the random number generator
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Task starting the random number generator
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Task stopping the random number generator
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Task stopping the random number generator
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [248]u8,
-            ///  Event being generated for every new random number written to the VALUE register
-            EVENTS_VALRDY: mmio.Mmio(packed struct(u32) {
-                ///  Event being generated for every new random number written to the VALUE register
-                EVENTS_VALRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [252]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between event VALRDY and task STOP
-                VALRDY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event VALRDY
-                VALRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event VALRDY
-                VALRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1284: [504]u8,
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Bias correction
-                DERCEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disabled
-                        Disabled = 0x0,
-                        ///  Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Output random number
-            VALUE: mmio.Mmio(packed struct(u32) {
-                ///  Generated random number
-                VALUE: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  AES ECB Mode Encryption
-        pub const ECB = extern struct {
-            ///  Start ECB block encrypt
-            TASKS_STARTECB: mmio.Mmio(packed struct(u32) {
-                ///  Start ECB block encrypt
-                TASKS_STARTECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Abort a possible executing ECB operation
-            TASKS_STOPECB: mmio.Mmio(packed struct(u32) {
-                ///  Abort a possible executing ECB operation
-                TASKS_STOPECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [248]u8,
-            ///  ECB block encrypt complete
-            EVENTS_ENDECB: mmio.Mmio(packed struct(u32) {
-                ///  ECB block encrypt complete
-                EVENTS_ENDECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  ECB block encrypt aborted because of a STOPECB task or due to an error
-            EVENTS_ERRORECB: mmio.Mmio(packed struct(u32) {
-                ///  ECB block encrypt aborted because of a STOPECB task or due to an error
-                EVENTS_ERRORECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [508]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event ENDECB
-                ENDECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ERRORECB
-                ERRORECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event ENDECB
-                ENDECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ERRORECB
-                ERRORECB: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1284: [504]u8,
-            ///  ECB block encrypt memory pointers
-            ECBDATAPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to the ECB data structure (see Table 1 ECB data structure overview)
-                ECBDATAPTR: u32,
-            }),
-        };
-
-        ///  Accelerated Address Resolver
-        pub const AAR = extern struct {
-            ///  Start resolving addresses based on IRKs specified in the IRK data structure
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Start resolving addresses based on IRKs specified in the IRK data structure
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved8: [4]u8,
-            ///  Stop resolving addresses
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop resolving addresses
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [244]u8,
-            ///  Address resolution procedure complete
-            EVENTS_END: mmio.Mmio(packed struct(u32) {
-                ///  Address resolution procedure complete
-                EVENTS_END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Address resolved
-            EVENTS_RESOLVED: mmio.Mmio(packed struct(u32) {
-                ///  Address resolved
-                EVENTS_RESOLVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Address not resolved
-            EVENTS_NOTRESOLVED: mmio.Mmio(packed struct(u32) {
-                ///  Address not resolved
-                EVENTS_NOTRESOLVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [504]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event RESOLVED
-                RESOLVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event NOTRESOLVED
-                NOTRESOLVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event END
-                END: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event RESOLVED
-                RESOLVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event NOTRESOLVED
-                NOTRESOLVED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1024: [244]u8,
-            ///  Resolution status
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  The IRK that was used last time an address was resolved
-                STATUS: u4,
-                padding: u28,
-            }),
-            reserved1280: [252]u8,
-            ///  Enable AAR
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable AAR
-                ENABLE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x3,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Number of IRKs
-            NIRK: mmio.Mmio(packed struct(u32) {
-                ///  Number of Identity root keys available in the IRK data structure
-                NIRK: u5,
-                padding: u27,
-            }),
-            ///  Pointer to IRK data structure
-            IRKPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to the IRK data structure
-                IRKPTR: u32,
-            }),
-            reserved1296: [4]u8,
-            ///  Pointer to the resolvable address
-            ADDRPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to the resolvable address (6-bytes)
-                ADDRPTR: u32,
-            }),
-            ///  Pointer to data area used for temporary storage
-            SCRATCHPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to a scratch data area used for temporary storage during resolution. A space of minimum 3 bytes must be reserved.
-                SCRATCHPTR: u32,
-            }),
-        };
-
-        ///  AES CCM Mode Encryption
-        pub const CCM = extern struct {
-            ///  Start generation of key-stream. This operation will stop by itself when completed.
-            TASKS_KSGEN: mmio.Mmio(packed struct(u32) {
-                ///  Start generation of key-stream. This operation will stop by itself when completed.
-                TASKS_KSGEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Start encryption/decryption. This operation will stop by itself when completed.
-            TASKS_CRYPT: mmio.Mmio(packed struct(u32) {
-                ///  Start encryption/decryption. This operation will stop by itself when completed.
-                TASKS_CRYPT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop encryption/decryption
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop encryption/decryption
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption
-            TASKS_RATEOVERRIDE: mmio.Mmio(packed struct(u32) {
-                ///  Override DATARATE setting in MODE register with the contents of the RATEOVERRIDE register for any ongoing encryption/decryption
-                TASKS_RATEOVERRIDE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [240]u8,
-            ///  Key-stream generation complete
-            EVENTS_ENDKSGEN: mmio.Mmio(packed struct(u32) {
-                ///  Key-stream generation complete
-                EVENTS_ENDKSGEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Encrypt/decrypt complete
-            EVENTS_ENDCRYPT: mmio.Mmio(packed struct(u32) {
-                ///  Encrypt/decrypt complete
-                EVENTS_ENDCRYPT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Deprecated register - CCM error event
-            EVENTS_ERROR: mmio.Mmio(packed struct(u32) {
-                ///  Deprecated field - CCM error event
-                EVENTS_ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [244]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between event ENDKSGEN and task CRYPT
-                ENDKSGEN_CRYPT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event ENDKSGEN
-                ENDKSGEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ENDCRYPT
-                ENDCRYPT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Deprecated intsetfield - Write '1' to enable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event ENDKSGEN
-                ENDKSGEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ENDCRYPT
-                ENDCRYPT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Deprecated intclrfield - Write '1' to disable interrupt for event ERROR
-                ERROR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1024: [244]u8,
-            ///  MIC check result
-            MICSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  The result of the MIC check performed during the previous decryption operation
-                MICSTATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  MIC check failed
-                        CheckFailed = 0x0,
-                        ///  MIC check passed
-                        CheckPassed = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1280: [252]u8,
-            ///  Enable
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable CCM
-                ENABLE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Operation mode
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  The mode of operation to be used. The settings in this register apply whenever either the KSGEN or CRYPT tasks are triggered.
-                MODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  AES CCM packet encryption mode
-                        Encryption = 0x0,
-                        ///  AES CCM packet decryption mode
-                        Decryption = 0x1,
-                    },
-                },
-                reserved16: u15,
-                ///  Radio data rate that the CCM shall run synchronous with
-                DATARATE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  1 Mbps
-                        @"1Mbit" = 0x0,
-                        ///  2 Mbps
-                        @"2Mbit" = 0x1,
-                        ///  125 Kbps
-                        @"125Kbps" = 0x2,
-                        ///  500 Kbps
-                        @"500Kbps" = 0x3,
-                    },
-                },
-                reserved24: u6,
-                ///  Packet length configuration
-                LENGTH: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Default length. Effective length of LENGTH field in encrypted/decrypted packet is 5 bits. A key-stream for packet payloads up to 27 bytes will be generated.
-                        Default = 0x0,
-                        ///  Extended length. Effective length of LENGTH field in encrypted/decrypted packet is 8 bits. A key-stream for packet payloads up to MAXPACKETSIZE bytes will be generated.
-                        Extended = 0x1,
-                    },
-                },
-                padding: u7,
-            }),
-            ///  Pointer to data structure holding AES key and NONCE vector
-            CNFPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview)
-                CNFPTR: u32,
-            }),
-            ///  Input pointer
-            INPTR: mmio.Mmio(packed struct(u32) {
-                ///  Input pointer
-                INPTR: u32,
-            }),
-            ///  Output pointer
-            OUTPTR: mmio.Mmio(packed struct(u32) {
-                ///  Output pointer
-                OUTPTR: u32,
-            }),
-            ///  Pointer to data area used for temporary storage
-            SCRATCHPTR: mmio.Mmio(packed struct(u32) {
-                ///  Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption.
-                SCRATCHPTR: u32,
-            }),
-            ///  Length of key-stream generated when MODE.LENGTH = Extended.
-            MAXPACKETSIZE: mmio.Mmio(packed struct(u32) {
-                ///  Length of key-stream generated when MODE.LENGTH = Extended. This value must be greater or equal to the subsequent packet payload to be encrypted/decrypted.
-                MAXPACKETSIZE: u8,
-                padding: u24,
-            }),
-            ///  Data rate override setting.
-            RATEOVERRIDE: mmio.Mmio(packed struct(u32) {
-                ///  Data rate override setting.
-                RATEOVERRIDE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  1 Mbps
-                        @"1Mbit" = 0x0,
-                        ///  2 Mbps
-                        @"2Mbit" = 0x1,
-                        ///  125 Kbps
-                        @"125Kbps" = 0x2,
-                        ///  500 Kbps
-                        @"500Kbps" = 0x3,
-                    },
-                },
-                padding: u30,
-            }),
-        };
-
-        ///  Watchdog Timer
-        pub const WDT = extern struct {
-            ///  Start the watchdog
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Start the watchdog
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [252]u8,
-            ///  Watchdog timeout
-            EVENTS_TIMEOUT: mmio.Mmio(packed struct(u32) {
-                ///  Watchdog timeout
-                EVENTS_TIMEOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved772: [512]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event TIMEOUT
-                TIMEOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event TIMEOUT
-                TIMEOUT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1024: [244]u8,
-            ///  Run status
-            RUNSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  Indicates whether or not the watchdog is running
-                RUNSTATUS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Watchdog not running
-                        NotRunning = 0x0,
-                        ///  Watchdog is running
-                        Running = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Request status
-            REQSTATUS: mmio.Mmio(packed struct(u32) {
-                ///  Request status for RR[0] register
-                RR0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[0] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[0] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[1] register
-                RR1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[1] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[1] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[2] register
-                RR2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[2] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[2] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[3] register
-                RR3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[3] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[3] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[4] register
-                RR4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[4] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[4] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[5] register
-                RR5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[5] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[5] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[6] register
-                RR6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[6] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[6] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                ///  Request status for RR[7] register
-                RR7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RR[7] register is not enabled, or are already requesting reload
-                        DisabledOrRequested = 0x0,
-                        ///  RR[7] register is enabled, and are not yet requesting reload
-                        EnabledAndUnrequested = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            reserved1284: [252]u8,
-            ///  Counter reload value
-            CRV: mmio.Mmio(packed struct(u32) {
-                ///  Counter reload value in number of cycles of the 32.768 kHz clock
-                CRV: u32,
-            }),
-            ///  Enable register for reload request registers
-            RREN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable RR[0] register
-                RR0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[0] register
-                        Disabled = 0x0,
-                        ///  Enable RR[0] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[1] register
-                RR1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[1] register
-                        Disabled = 0x0,
-                        ///  Enable RR[1] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[2] register
-                RR2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[2] register
-                        Disabled = 0x0,
-                        ///  Enable RR[2] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[3] register
-                RR3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[3] register
-                        Disabled = 0x0,
-                        ///  Enable RR[3] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[4] register
-                RR4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[4] register
-                        Disabled = 0x0,
-                        ///  Enable RR[4] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[5] register
-                RR5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[5] register
-                        Disabled = 0x0,
-                        ///  Enable RR[5] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[6] register
-                RR6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[6] register
-                        Disabled = 0x0,
-                        ///  Enable RR[6] register
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable RR[7] register
-                RR7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable RR[7] register
-                        Disabled = 0x0,
-                        ///  Enable RR[7] register
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Configure the watchdog to either be paused, or kept running, while the CPU is sleeping
-                SLEEP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pause watchdog while the CPU is sleeping
-                        Pause = 0x0,
-                        ///  Keep the watchdog running while the CPU is sleeping
-                        Run = 0x1,
-                    },
-                },
-                reserved3: u2,
-                ///  Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger
-                HALT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Pause watchdog while the CPU is halted by the debugger
-                        Pause = 0x0,
-                        ///  Keep the watchdog running while the CPU is halted by the debugger
-                        Run = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1536: [240]u8,
-            ///  Description collection: Reload request n
-            RR: [8]mmio.Mmio(packed struct(u32) {
-                ///  Reload request register
-                RR: packed union {
-                    raw: u32,
-                    value: enum(u32) {
-                        ///  Value to request a reload of the watchdog timer
-                        Reload = 0x6e524635,
-                        _,
-                    },
-                },
-            }),
-        };
-
-        ///  Memory Watch Unit
-        pub const MWU = extern struct {
-            reserved768: [768]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for event REGION0WA
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION0RA
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION1WA
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION1RA
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION2WA
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION2RA
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION3WA
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION3RA
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Enable or disable interrupt for event PREGION0WA
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event PREGION0RA
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event PREGION1WA
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event PREGION1RA
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event REGION0WA
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION0RA
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION1WA
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION1RA
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION2WA
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION2RA
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION3WA
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION3RA
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Write '1' to enable interrupt for event PREGION0WA
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event PREGION0RA
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event PREGION1WA
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event PREGION1RA
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event REGION0WA
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION0RA
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION1WA
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION1RA
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION2WA
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION2RA
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION3WA
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION3RA
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Write '1' to disable interrupt for event PREGION0WA
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event PREGION0RA
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event PREGION1WA
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event PREGION1RA
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            reserved800: [20]u8,
-            ///  Enable or disable interrupt
-            NMIEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for event REGION0WA
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION0RA
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION1WA
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION1RA
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION2WA
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION2RA
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION3WA
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event REGION3RA
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Enable or disable interrupt for event PREGION0WA
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event PREGION0RA
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event PREGION1WA
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event PREGION1RA
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Enable interrupt
-            NMIENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event REGION0WA
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION0RA
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION1WA
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION1RA
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION2WA
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION2RA
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION3WA
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REGION3RA
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Write '1' to enable interrupt for event PREGION0WA
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event PREGION0RA
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event PREGION1WA
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event PREGION1RA
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Disable interrupt
-            NMIENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event REGION0WA
-                REGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION0RA
-                REGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION1WA
-                REGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION1RA
-                REGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION2WA
-                REGION2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION2RA
-                REGION2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION3WA
-                REGION3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REGION3RA
-                REGION3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Write '1' to disable interrupt for event PREGION0WA
-                PREGION0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event PREGION0RA
-                PREGION0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event PREGION1WA
-                PREGION1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event PREGION1RA
-                PREGION1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            reserved1296: [484]u8,
-            ///  Enable/disable regions watch
-            REGIONEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable/disable write access watch in region[0]
-                RGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this region
-                        Disable = 0x0,
-                        ///  Enable write access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in region[0]
-                RGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this region
-                        Disable = 0x0,
-                        ///  Enable read access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable write access watch in region[1]
-                RGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this region
-                        Disable = 0x0,
-                        ///  Enable write access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in region[1]
-                RGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this region
-                        Disable = 0x0,
-                        ///  Enable read access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable write access watch in region[2]
-                RGN2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this region
-                        Disable = 0x0,
-                        ///  Enable write access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in region[2]
-                RGN2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this region
-                        Disable = 0x0,
-                        ///  Enable read access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable write access watch in region[3]
-                RGN3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this region
-                        Disable = 0x0,
-                        ///  Enable write access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in region[3]
-                RGN3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this region
-                        Disable = 0x0,
-                        ///  Enable read access watch in this region
-                        Enable = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Enable/disable write access watch in PREGION[0]
-                PRGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this PREGION
-                        Disable = 0x0,
-                        ///  Enable write access watch in this PREGION
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in PREGION[0]
-                PRGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this PREGION
-                        Disable = 0x0,
-                        ///  Enable read access watch in this PREGION
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable write access watch in PREGION[1]
-                PRGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable write access watch in this PREGION
-                        Disable = 0x0,
-                        ///  Enable write access watch in this PREGION
-                        Enable = 0x1,
-                    },
-                },
-                ///  Enable/disable read access watch in PREGION[1]
-                PRGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable read access watch in this PREGION
-                        Disable = 0x0,
-                        ///  Enable read access watch in this PREGION
-                        Enable = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Enable regions watch
-            REGIONENSET: mmio.Mmio(packed struct(u32) {
-                ///  Enable write access watch in region[0]
-                RGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in region[0]
-                RGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable write access watch in region[1]
-                RGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in region[1]
-                RGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable write access watch in region[2]
-                RGN2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in region[2]
-                RGN2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable write access watch in region[3]
-                RGN3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in region[3]
-                RGN3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Enable write access watch in PREGION[0]
-                PRGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in PREGION[0]
-                PRGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable write access watch in PREGION[1]
-                PRGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable read access watch in PREGION[1]
-                PRGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-            ///  Disable regions watch
-            REGIONENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Disable write access watch in region[0]
-                RGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in region[0]
-                RGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable write access watch in region[1]
-                RGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in region[1]
-                RGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable write access watch in region[2]
-                RGN2WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in region[2]
-                RGN2RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable write access watch in region[3]
-                RGN3WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in region[3]
-                RGN3RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this region is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this region is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                reserved24: u16,
-                ///  Disable write access watch in PREGION[0]
-                PRGN0WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in PREGION[0]
-                PRGN0RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable write access watch in PREGION[1]
-                PRGN1WA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Write access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Write access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Disable read access watch in PREGION[1]
-                PRGN1RA: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read access watch in this PREGION is disabled
-                        Disabled = 0x0,
-                        ///  Read access watch in this PREGION is enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u4,
-            }),
-        };
-
-        ///  Quadrature Decoder
-        pub const QDEC = extern struct {
-            ///  Task starting the quadrature decoder
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Task starting the quadrature decoder
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Task stopping the quadrature decoder
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Task stopping the quadrature decoder
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Read and clear ACC and ACCDBL
-            TASKS_READCLRACC: mmio.Mmio(packed struct(u32) {
-                ///  Read and clear ACC and ACCDBL
-                TASKS_READCLRACC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Read and clear ACC
-            TASKS_RDCLRACC: mmio.Mmio(packed struct(u32) {
-                ///  Read and clear ACC
-                TASKS_RDCLRACC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Read and clear ACCDBL
-            TASKS_RDCLRDBL: mmio.Mmio(packed struct(u32) {
-                ///  Read and clear ACCDBL
-                TASKS_RDCLRDBL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [236]u8,
-            ///  Event being generated for every new sample value written to the SAMPLE register
-            EVENTS_SAMPLERDY: mmio.Mmio(packed struct(u32) {
-                ///  Event being generated for every new sample value written to the SAMPLE register
-                EVENTS_SAMPLERDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Non-null report ready
-            EVENTS_REPORTRDY: mmio.Mmio(packed struct(u32) {
-                ///  Non-null report ready
-                EVENTS_REPORTRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  ACC or ACCDBL register overflow
-            EVENTS_ACCOF: mmio.Mmio(packed struct(u32) {
-                ///  ACC or ACCDBL register overflow
-                EVENTS_ACCOF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Double displacement(s) detected
-            EVENTS_DBLRDY: mmio.Mmio(packed struct(u32) {
-                ///  Double displacement(s) detected
-                EVENTS_DBLRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  QDEC has been stopped
-            EVENTS_STOPPED: mmio.Mmio(packed struct(u32) {
-                ///  QDEC has been stopped
-                EVENTS_STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [236]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between event REPORTRDY and task READCLRACC
-                REPORTRDY_READCLRACC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event SAMPLERDY and task STOP
-                SAMPLERDY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event REPORTRDY and task RDCLRACC
-                REPORTRDY_RDCLRACC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event REPORTRDY and task STOP
-                REPORTRDY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event DBLRDY and task RDCLRDBL
-                DBLRDY_RDCLRDBL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event DBLRDY and task STOP
-                DBLRDY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event SAMPLERDY and task READCLRACC
-                SAMPLERDY_READCLRACC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u25,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event SAMPLERDY
-                SAMPLERDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event REPORTRDY
-                REPORTRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event ACCOF
-                ACCOF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event DBLRDY
-                DBLRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event SAMPLERDY
-                SAMPLERDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event REPORTRDY
-                REPORTRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event ACCOF
-                ACCOF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event DBLRDY
-                DBLRDY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event STOPPED
-                STOPPED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved1280: [500]u8,
-            ///  Enable the quadrature decoder
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable the quadrature decoder
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  LED output pin polarity
-            LEDPOL: mmio.Mmio(packed struct(u32) {
-                ///  LED output pin polarity
-                LEDPOL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Led active on output pin low
-                        ActiveLow = 0x0,
-                        ///  Led active on output pin high
-                        ActiveHigh = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Sample period
-            SAMPLEPER: mmio.Mmio(packed struct(u32) {
-                ///  Sample period. The SAMPLE register will be updated for every new sample
-                SAMPLEPER: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  128 us
-                        @"128us" = 0x0,
-                        ///  256 us
-                        @"256us" = 0x1,
-                        ///  512 us
-                        @"512us" = 0x2,
-                        ///  1024 us
-                        @"1024us" = 0x3,
-                        ///  2048 us
-                        @"2048us" = 0x4,
-                        ///  4096 us
-                        @"4096us" = 0x5,
-                        ///  8192 us
-                        @"8192us" = 0x6,
-                        ///  16384 us
-                        @"16384us" = 0x7,
-                        ///  32768 us
-                        @"32ms" = 0x8,
-                        ///  65536 us
-                        @"65ms" = 0x9,
-                        ///  131072 us
-                        @"131ms" = 0xa,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Motion sample value
-            SAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  Last motion sample
-                SAMPLE: u32,
-            }),
-            ///  Number of samples to be taken before REPORTRDY and DBLRDY events can be generated
-            REPORTPER: mmio.Mmio(packed struct(u32) {
-                ///  Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated
-                REPORTPER: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  10 samples / report
-                        @"10Smpl" = 0x0,
-                        ///  40 samples / report
-                        @"40Smpl" = 0x1,
-                        ///  80 samples / report
-                        @"80Smpl" = 0x2,
-                        ///  120 samples / report
-                        @"120Smpl" = 0x3,
-                        ///  160 samples / report
-                        @"160Smpl" = 0x4,
-                        ///  200 samples / report
-                        @"200Smpl" = 0x5,
-                        ///  240 samples / report
-                        @"240Smpl" = 0x6,
-                        ///  280 samples / report
-                        @"280Smpl" = 0x7,
-                        ///  1 sample / report
-                        @"1Smpl" = 0x8,
-                        _,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Register accumulating the valid transitions
-            ACC: mmio.Mmio(packed struct(u32) {
-                ///  Register accumulating all valid samples (not double transition) read from the SAMPLE register
-                ACC: u32,
-            }),
-            ///  Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task
-            ACCREAD: mmio.Mmio(packed struct(u32) {
-                ///  Snapshot of the ACC register.
-                ACCREAD: u32,
-            }),
-            reserved1320: [12]u8,
-            ///  Enable input debounce filters
-            DBFEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable input debounce filters
-                DBFEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Debounce input filters disabled
-                        Disabled = 0x0,
-                        ///  Debounce input filters enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1344: [20]u8,
-            ///  Time period the LED is switched ON prior to sampling
-            LEDPRE: mmio.Mmio(packed struct(u32) {
-                ///  Period in us the LED is switched on prior to sampling
-                LEDPRE: u9,
-                padding: u23,
-            }),
-            ///  Register accumulating the number of detected double transitions
-            ACCDBL: mmio.Mmio(packed struct(u32) {
-                ///  Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ).
-                ACCDBL: u4,
-                padding: u28,
-            }),
-            ///  Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task
-            ACCDBLREAD: mmio.Mmio(packed struct(u32) {
-                ///  Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered.
-                ACCDBLREAD: u4,
-                padding: u28,
-            }),
-        };
-
-        ///  Comparator
-        pub const COMP = extern struct {
-            ///  Start comparator
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Start comparator
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop comparator
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop comparator
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Sample comparator value
-            TASKS_SAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  Sample comparator value
-                TASKS_SAMPLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [244]u8,
-            ///  COMP is ready and output is valid
-            EVENTS_READY: mmio.Mmio(packed struct(u32) {
-                ///  COMP is ready and output is valid
-                EVENTS_READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Downward crossing
-            EVENTS_DOWN: mmio.Mmio(packed struct(u32) {
-                ///  Downward crossing
-                EVENTS_DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Upward crossing
-            EVENTS_UP: mmio.Mmio(packed struct(u32) {
-                ///  Upward crossing
-                EVENTS_UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Downward or upward crossing
-            EVENTS_CROSS: mmio.Mmio(packed struct(u32) {
-                ///  Downward or upward crossing
-                EVENTS_CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [240]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between event READY and task SAMPLE
-                READY_SAMPLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event READY and task STOP
-                READY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event DOWN and task STOP
-                DOWN_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event UP and task STOP
-                UP_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event CROSS and task STOP
-                CROSS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved768: [252]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event DOWN
-                DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event UP
-                UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event CROSS
-                CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event DOWN
-                DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event UP
-                UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CROSS
-                CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event DOWN
-                DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event UP
-                UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CROSS
-                CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1024: [244]u8,
-            ///  Compare result
-            RESULT: mmio.Mmio(packed struct(u32) {
-                ///  Result of last compare. Decision point SAMPLE task.
-                RESULT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Input voltage is below the threshold (VIN+ < VIN-)
-                        Below = 0x0,
-                        ///  Input voltage is above the threshold (VIN+ > VIN-)
-                        Above = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1280: [252]u8,
-            ///  COMP enable
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable COMP
-                ENABLE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Pin select
-            PSEL: mmio.Mmio(packed struct(u32) {
-                ///  Analog pin select
-                PSEL: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  AIN0 selected as analog input
-                        AnalogInput0 = 0x0,
-                        ///  AIN1 selected as analog input
-                        AnalogInput1 = 0x1,
-                        ///  AIN2 selected as analog input
-                        AnalogInput2 = 0x2,
-                        ///  AIN3 selected as analog input
-                        AnalogInput3 = 0x3,
-                        ///  AIN4 selected as analog input
-                        AnalogInput4 = 0x4,
-                        ///  AIN5 selected as analog input
-                        AnalogInput5 = 0x5,
-                        ///  AIN6 selected as analog input
-                        AnalogInput6 = 0x6,
-                        ///  AIN7 selected as analog input
-                        AnalogInput7 = 0x7,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Reference source select for single-ended mode
-            REFSEL: mmio.Mmio(packed struct(u32) {
-                ///  Reference select
-                REFSEL: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  VREF = internal 1.2 V reference (VDD >= 1.7 V)
-                        Int1V2 = 0x0,
-                        ///  VREF = internal 1.8 V reference (VDD >= VREF + 0.2 V)
-                        Int1V8 = 0x1,
-                        ///  VREF = internal 2.4 V reference (VDD >= VREF + 0.2 V)
-                        Int2V4 = 0x2,
-                        ///  VREF = VDD
-                        VDD = 0x4,
-                        ///  VREF = AREF (VDD >= VREF >= AREFMIN)
-                        ARef = 0x5,
-                        _,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  External reference select
-            EXTREFSEL: mmio.Mmio(packed struct(u32) {
-                ///  External analog reference select
-                EXTREFSEL: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  Use AIN0 as external analog reference
-                        AnalogReference0 = 0x0,
-                        ///  Use AIN1 as external analog reference
-                        AnalogReference1 = 0x1,
-                        ///  Use AIN2 as external analog reference
-                        AnalogReference2 = 0x2,
-                        ///  Use AIN3 as external analog reference
-                        AnalogReference3 = 0x3,
-                        ///  Use AIN4 as external analog reference
-                        AnalogReference4 = 0x4,
-                        ///  Use AIN5 as external analog reference
-                        AnalogReference5 = 0x5,
-                        ///  Use AIN6 as external analog reference
-                        AnalogReference6 = 0x6,
-                        ///  Use AIN7 as external analog reference
-                        AnalogReference7 = 0x7,
-                    },
-                },
-                padding: u29,
-            }),
-            reserved1328: [32]u8,
-            ///  Threshold configuration for hysteresis unit
-            TH: mmio.Mmio(packed struct(u32) {
-                ///  VDOWN = (THDOWN+1)/64*VREF
-                THDOWN: u6,
-                reserved8: u2,
-                ///  VUP = (THUP+1)/64*VREF
-                THUP: u6,
-                padding: u18,
-            }),
-            ///  Mode configuration
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Speed and power modes
-                SP: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Low-power mode
-                        Low = 0x0,
-                        ///  Normal mode
-                        Normal = 0x1,
-                        ///  High-speed mode
-                        High = 0x2,
-                        _,
-                    },
-                },
-                reserved8: u6,
-                ///  Main operation modes
-                MAIN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Single-ended mode
-                        SE = 0x0,
-                        ///  Differential mode
-                        Diff = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            ///  Comparator hysteresis enable
-            HYST: mmio.Mmio(packed struct(u32) {
-                ///  Comparator hysteresis
-                HYST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Comparator hysteresis disabled
-                        NoHyst = 0x0,
-                        ///  Comparator hysteresis enabled
-                        Hyst50mV = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  Low Power Comparator
-        pub const LPCOMP = extern struct {
-            ///  Start comparator
-            TASKS_START: mmio.Mmio(packed struct(u32) {
-                ///  Start comparator
-                TASKS_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Stop comparator
-            TASKS_STOP: mmio.Mmio(packed struct(u32) {
-                ///  Stop comparator
-                TASKS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Sample comparator value
-            TASKS_SAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  Sample comparator value
-                TASKS_SAMPLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [244]u8,
-            ///  LPCOMP is ready and output is valid
-            EVENTS_READY: mmio.Mmio(packed struct(u32) {
-                ///  LPCOMP is ready and output is valid
-                EVENTS_READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Downward crossing
-            EVENTS_DOWN: mmio.Mmio(packed struct(u32) {
-                ///  Downward crossing
-                EVENTS_DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Upward crossing
-            EVENTS_UP: mmio.Mmio(packed struct(u32) {
-                ///  Upward crossing
-                EVENTS_UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Downward or upward crossing
-            EVENTS_CROSS: mmio.Mmio(packed struct(u32) {
-                ///  Downward or upward crossing
-                EVENTS_CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved512: [240]u8,
-            ///  Shortcuts between local events and tasks
-            SHORTS: mmio.Mmio(packed struct(u32) {
-                ///  Shortcut between event READY and task SAMPLE
-                READY_SAMPLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event READY and task STOP
-                READY_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event DOWN and task STOP
-                DOWN_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event UP and task STOP
-                UP_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Shortcut between event CROSS and task STOP
-                CROSS_STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable shortcut
-                        Disabled = 0x0,
-                        ///  Enable shortcut
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u27,
-            }),
-            reserved772: [256]u8,
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event DOWN
-                DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event UP
-                UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event CROSS
-                CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event READY
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event DOWN
-                DOWN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event UP
-                UP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event CROSS
-                CROSS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u28,
-            }),
-            reserved1024: [244]u8,
-            ///  Compare result
-            RESULT: mmio.Mmio(packed struct(u32) {
-                ///  Result of last compare. Decision point SAMPLE task.
-                RESULT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Input voltage is below the reference threshold (VIN+ < VIN-).
-                        Below = 0x0,
-                        ///  Input voltage is above the reference threshold (VIN+ > VIN-).
-                        Above = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1280: [252]u8,
-            ///  Enable LPCOMP
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable LPCOMP
-                ENABLE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Input pin select
-            PSEL: mmio.Mmio(packed struct(u32) {
-                ///  Analog pin select
-                PSEL: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        ///  AIN0 selected as analog input
-                        AnalogInput0 = 0x0,
-                        ///  AIN1 selected as analog input
-                        AnalogInput1 = 0x1,
-                        ///  AIN2 selected as analog input
-                        AnalogInput2 = 0x2,
-                        ///  AIN3 selected as analog input
-                        AnalogInput3 = 0x3,
-                        ///  AIN4 selected as analog input
-                        AnalogInput4 = 0x4,
-                        ///  AIN5 selected as analog input
-                        AnalogInput5 = 0x5,
-                        ///  AIN6 selected as analog input
-                        AnalogInput6 = 0x6,
-                        ///  AIN7 selected as analog input
-                        AnalogInput7 = 0x7,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  Reference select
-            REFSEL: mmio.Mmio(packed struct(u32) {
-                ///  Reference select
-                REFSEL: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  VDD * 1/8 selected as reference
-                        Ref1_8Vdd = 0x0,
-                        ///  VDD * 2/8 selected as reference
-                        Ref2_8Vdd = 0x1,
-                        ///  VDD * 3/8 selected as reference
-                        Ref3_8Vdd = 0x2,
-                        ///  VDD * 4/8 selected as reference
-                        Ref4_8Vdd = 0x3,
-                        ///  VDD * 5/8 selected as reference
-                        Ref5_8Vdd = 0x4,
-                        ///  VDD * 6/8 selected as reference
-                        Ref6_8Vdd = 0x5,
-                        ///  VDD * 7/8 selected as reference
-                        Ref7_8Vdd = 0x6,
-                        ///  External analog reference selected
-                        ARef = 0x7,
-                        ///  VDD * 1/16 selected as reference
-                        Ref1_16Vdd = 0x8,
-                        ///  VDD * 3/16 selected as reference
-                        Ref3_16Vdd = 0x9,
-                        ///  VDD * 5/16 selected as reference
-                        Ref5_16Vdd = 0xa,
-                        ///  VDD * 7/16 selected as reference
-                        Ref7_16Vdd = 0xb,
-                        ///  VDD * 9/16 selected as reference
-                        Ref9_16Vdd = 0xc,
-                        ///  VDD * 11/16 selected as reference
-                        Ref11_16Vdd = 0xd,
-                        ///  VDD * 13/16 selected as reference
-                        Ref13_16Vdd = 0xe,
-                        ///  VDD * 15/16 selected as reference
-                        Ref15_16Vdd = 0xf,
-                    },
-                },
-                padding: u28,
-            }),
-            ///  External reference select
-            EXTREFSEL: mmio.Mmio(packed struct(u32) {
-                ///  External analog reference select
-                EXTREFSEL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Use AIN0 as external analog reference
-                        AnalogReference0 = 0x0,
-                        ///  Use AIN1 as external analog reference
-                        AnalogReference1 = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1312: [16]u8,
-            ///  Analog detect configuration
-            ANADETECT: mmio.Mmio(packed struct(u32) {
-                ///  Analog detect configuration
-                ANADETECT: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Generate ANADETECT on crossing, both upward crossing and downward crossing
-                        Cross = 0x0,
-                        ///  Generate ANADETECT on upward crossing only
-                        Up = 0x1,
-                        ///  Generate ANADETECT on downward crossing only
-                        Down = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            reserved1336: [20]u8,
-            ///  Comparator hysteresis enable
-            HYST: mmio.Mmio(packed struct(u32) {
-                ///  Comparator hysteresis enable
-                HYST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Comparator hysteresis disabled
-                        Disabled = 0x0,
-                        ///  Comparator hysteresis enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-        };
-
-        ///  Event Generator Unit 0
-        pub const EGU0 = extern struct {
-            ///  Description collection: Trigger n for triggering the corresponding TRIGGERED[n] event
-            TASKS_TRIGGER: [16]mmio.Mmio(packed struct(u32) {
-                ///  Trigger n for triggering the corresponding TRIGGERED[n] event
-                TASKS_TRIGGER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Trigger task
-                        Trigger = 0x1,
-                        _,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved256: [192]u8,
-            ///  Description collection: Event number n generated by triggering the corresponding TRIGGER[n] task
-            EVENTS_TRIGGERED: [16]mmio.Mmio(packed struct(u32) {
-                ///  Event number n generated by triggering the corresponding TRIGGER[n] task
-                EVENTS_TRIGGERED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Event not generated
-                        NotGenerated = 0x0,
-                        ///  Event generated
-                        Generated = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved768: [448]u8,
-            ///  Enable or disable interrupt
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable interrupt for event TRIGGERED[0]
-                TRIGGERED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[1]
-                TRIGGERED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[2]
-                TRIGGERED2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[3]
-                TRIGGERED3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[4]
-                TRIGGERED4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[5]
-                TRIGGERED5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[6]
-                TRIGGERED6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[7]
-                TRIGGERED7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[8]
-                TRIGGERED8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[9]
-                TRIGGERED9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[10]
-                TRIGGERED10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[11]
-                TRIGGERED11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[12]
-                TRIGGERED12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[13]
-                TRIGGERED13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[14]
-                TRIGGERED14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable interrupt for event TRIGGERED[15]
-                TRIGGERED15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable
-                        Disabled = 0x0,
-                        ///  Enable
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u16,
-            }),
-            ///  Enable interrupt
-            INTENSET: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to enable interrupt for event TRIGGERED[0]
-                TRIGGERED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[1]
-                TRIGGERED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[2]
-                TRIGGERED2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[3]
-                TRIGGERED3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[4]
-                TRIGGERED4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[5]
-                TRIGGERED5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[6]
-                TRIGGERED6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[7]
-                TRIGGERED7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[8]
-                TRIGGERED8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[9]
-                TRIGGERED9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[10]
-                TRIGGERED10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[11]
-                TRIGGERED11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[12]
-                TRIGGERED12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[13]
-                TRIGGERED13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[14]
-                TRIGGERED14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to enable interrupt for event TRIGGERED[15]
-                TRIGGERED15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u16,
-            }),
-            ///  Disable interrupt
-            INTENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Write '1' to disable interrupt for event TRIGGERED[0]
-                TRIGGERED0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[1]
-                TRIGGERED1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[2]
-                TRIGGERED2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[3]
-                TRIGGERED3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[4]
-                TRIGGERED4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[5]
-                TRIGGERED5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[6]
-                TRIGGERED6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[7]
-                TRIGGERED7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[8]
-                TRIGGERED8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[9]
-                TRIGGERED9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[10]
-                TRIGGERED10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[11]
-                TRIGGERED11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[12]
-                TRIGGERED12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[13]
-                TRIGGERED13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[14]
-                TRIGGERED14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Write '1' to disable interrupt for event TRIGGERED[15]
-                TRIGGERED15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: Disabled
-                        Disabled = 0x0,
-                        ///  Read: Enabled
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u16,
-            }),
-        };
-
-        ///  Software interrupt 0
-        pub const SWI0 = extern struct {
-            ///  Unused.
-            UNUSED: u32,
-        };
-
-        ///  Programmable Peripheral Interconnect
-        pub const PPI = extern struct {
-            reserved1280: [1280]u8,
-            ///  Channel enable register
-            CHEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable or disable channel 0
-                CH0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 1
-                CH1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 2
-                CH2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 3
-                CH3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 4
-                CH4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 5
-                CH5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 6
-                CH6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 7
-                CH7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 8
-                CH8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 9
-                CH9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 10
-                CH10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 11
-                CH11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 12
-                CH12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 13
-                CH13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 14
-                CH14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 15
-                CH15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 16
-                CH16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 17
-                CH17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 18
-                CH18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 19
-                CH19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 20
-                CH20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 21
-                CH21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 22
-                CH22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 23
-                CH23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 24
-                CH24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 25
-                CH25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 26
-                CH26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 27
-                CH27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 28
-                CH28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 29
-                CH29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 30
-                CH30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Enable or disable channel 31
-                CH31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable channel
-                        Disabled = 0x0,
-                        ///  Enable channel
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            ///  Channel enable set register
-            CHENSET: mmio.Mmio(packed struct(u32) {
-                ///  Channel 0 enable set register. Writing '0' has no effect
-                CH0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 1 enable set register. Writing '0' has no effect
-                CH1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 2 enable set register. Writing '0' has no effect
-                CH2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 3 enable set register. Writing '0' has no effect
-                CH3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 4 enable set register. Writing '0' has no effect
-                CH4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 5 enable set register. Writing '0' has no effect
-                CH5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 6 enable set register. Writing '0' has no effect
-                CH6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 7 enable set register. Writing '0' has no effect
-                CH7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 8 enable set register. Writing '0' has no effect
-                CH8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 9 enable set register. Writing '0' has no effect
-                CH9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 10 enable set register. Writing '0' has no effect
-                CH10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 11 enable set register. Writing '0' has no effect
-                CH11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 12 enable set register. Writing '0' has no effect
-                CH12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 13 enable set register. Writing '0' has no effect
-                CH13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 14 enable set register. Writing '0' has no effect
-                CH14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 15 enable set register. Writing '0' has no effect
-                CH15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 16 enable set register. Writing '0' has no effect
-                CH16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 17 enable set register. Writing '0' has no effect
-                CH17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 18 enable set register. Writing '0' has no effect
-                CH18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 19 enable set register. Writing '0' has no effect
-                CH19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 20 enable set register. Writing '0' has no effect
-                CH20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 21 enable set register. Writing '0' has no effect
-                CH21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 22 enable set register. Writing '0' has no effect
-                CH22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 23 enable set register. Writing '0' has no effect
-                CH23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 24 enable set register. Writing '0' has no effect
-                CH24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 25 enable set register. Writing '0' has no effect
-                CH25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 26 enable set register. Writing '0' has no effect
-                CH26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 27 enable set register. Writing '0' has no effect
-                CH27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 28 enable set register. Writing '0' has no effect
-                CH28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 29 enable set register. Writing '0' has no effect
-                CH29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 30 enable set register. Writing '0' has no effect
-                CH30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 31 enable set register. Writing '0' has no effect
-                CH31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            ///  Channel enable clear register
-            CHENCLR: mmio.Mmio(packed struct(u32) {
-                ///  Channel 0 enable clear register. Writing '0' has no effect
-                CH0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 1 enable clear register. Writing '0' has no effect
-                CH1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 2 enable clear register. Writing '0' has no effect
-                CH2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 3 enable clear register. Writing '0' has no effect
-                CH3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 4 enable clear register. Writing '0' has no effect
-                CH4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 5 enable clear register. Writing '0' has no effect
-                CH5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 6 enable clear register. Writing '0' has no effect
-                CH6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 7 enable clear register. Writing '0' has no effect
-                CH7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 8 enable clear register. Writing '0' has no effect
-                CH8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 9 enable clear register. Writing '0' has no effect
-                CH9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 10 enable clear register. Writing '0' has no effect
-                CH10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 11 enable clear register. Writing '0' has no effect
-                CH11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 12 enable clear register. Writing '0' has no effect
-                CH12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 13 enable clear register. Writing '0' has no effect
-                CH13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 14 enable clear register. Writing '0' has no effect
-                CH14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 15 enable clear register. Writing '0' has no effect
-                CH15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 16 enable clear register. Writing '0' has no effect
-                CH16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 17 enable clear register. Writing '0' has no effect
-                CH17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 18 enable clear register. Writing '0' has no effect
-                CH18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 19 enable clear register. Writing '0' has no effect
-                CH19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 20 enable clear register. Writing '0' has no effect
-                CH20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 21 enable clear register. Writing '0' has no effect
-                CH21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 22 enable clear register. Writing '0' has no effect
-                CH22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 23 enable clear register. Writing '0' has no effect
-                CH23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 24 enable clear register. Writing '0' has no effect
-                CH24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 25 enable clear register. Writing '0' has no effect
-                CH25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 26 enable clear register. Writing '0' has no effect
-                CH26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 27 enable clear register. Writing '0' has no effect
-                CH27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 28 enable clear register. Writing '0' has no effect
-                CH28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 29 enable clear register. Writing '0' has no effect
-                CH29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 30 enable clear register. Writing '0' has no effect
-                CH30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-                ///  Channel 31 enable clear register. Writing '0' has no effect
-                CH31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Read: channel disabled
-                        Disabled = 0x0,
-                        ///  Read: channel enabled
-                        Enabled = 0x1,
-                    },
-                },
-            }),
-            reserved2048: [756]u8,
-            ///  Description collection: Channel group n
-            CHG: [6]mmio.Mmio(packed struct(u32) {
-                ///  Include or exclude channel 0
-                CH0: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 1
-                CH1: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 2
-                CH2: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 3
-                CH3: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 4
-                CH4: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 5
-                CH5: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 6
-                CH6: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 7
-                CH7: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 8
-                CH8: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 9
-                CH9: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 10
-                CH10: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 11
-                CH11: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 12
-                CH12: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 13
-                CH13: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 14
-                CH14: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 15
-                CH15: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 16
-                CH16: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 17
-                CH17: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 18
-                CH18: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 19
-                CH19: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 20
-                CH20: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 21
-                CH21: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 22
-                CH22: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 23
-                CH23: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 24
-                CH24: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 25
-                CH25: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 26
-                CH26: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 27
-                CH27: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 28
-                CH28: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 29
-                CH29: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 30
-                CH30: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-                ///  Include or exclude channel 31
-                CH31: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Exclude
-                        Excluded = 0x0,
-                        ///  Include
-                        Included = 0x1,
-                    },
-                },
-            }),
-        };
-
-        ///  Non Volatile Memory Controller
-        pub const NVMC = extern struct {
-            reserved1024: [1024]u8,
-            ///  Ready flag
-            READY: mmio.Mmio(packed struct(u32) {
-                ///  NVMC is ready or busy
-                READY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  NVMC is busy (on-going write or erase operation)
-                        Busy = 0x0,
-                        ///  NVMC is ready
-                        Ready = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1032: [4]u8,
-            ///  Ready flag
-            READYNEXT: mmio.Mmio(packed struct(u32) {
-                ///  NVMC can accept a new write operation
-                READYNEXT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  NVMC cannot accept any write operation
-                        Busy = 0x0,
-                        ///  NVMC is ready
-                        Ready = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            reserved1284: [248]u8,
-            ///  Configuration register
-            CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated.
-                WEN: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Read only access
-                        Ren = 0x0,
-                        ///  Write enabled
-                        Wen = 0x1,
-                        ///  Erase enabled
-                        Een = 0x2,
-                        _,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  Register for erasing a page in code area
-            ERASEPAGE: mmio.Mmio(packed struct(u32) {
-                ///  Register for starting erase of a page in code area
-                ERASEPAGE: u32,
-            }),
-            ///  Register for erasing all non-volatile user memory
-            ERASEALL: mmio.Mmio(packed struct(u32) {
-                ///  Erase all non-volatile memory including UICR registers. Note that the erase must be enabled using CONFIG.WEN before the non-volatile memory can be erased.
-                ERASEALL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No operation
-                        NoOperation = 0x0,
-                        ///  Start chip erase
-                        Erase = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Deprecated register - Register for erasing a page in code area. Equivalent to ERASEPAGE.
-            ERASEPCR0: mmio.Mmio(packed struct(u32) {
-                ///  Register for starting erase of a page in code area. Equivalent to ERASEPAGE.
-                ERASEPCR0: u32,
-            }),
-            ///  Register for erasing user information configuration registers
-            ERASEUICR: mmio.Mmio(packed struct(u32) {
-                ///  Register starting erase of all user information configuration registers. Note that the erase must be enabled using CONFIG.WEN before the UICR can be erased.
-                ERASEUICR: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  No operation
-                        NoOperation = 0x0,
-                        ///  Start erase of UICR
-                        Erase = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Register for partial erase of a page in code area
-            ERASEPAGEPARTIAL: mmio.Mmio(packed struct(u32) {
-                ///  Register for starting partial erase of a page in code area
-                ERASEPAGEPARTIAL: u32,
-            }),
-            ///  Register for partial erase configuration
-            ERASEPAGEPARTIALCFG: mmio.Mmio(packed struct(u32) {
-                ///  Duration of the partial erase in milliseconds
-                DURATION: u7,
-                padding: u25,
-            }),
-            reserved1344: [32]u8,
-            ///  I-code cache configuration register.
-            ICACHECNF: mmio.Mmio(packed struct(u32) {
-                ///  Cache enable
-                CACHEEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable cache. Invalidates all cache entries.
-                        Disabled = 0x0,
-                        ///  Enable cache
-                        Enabled = 0x1,
-                    },
-                },
-                reserved8: u7,
-                ///  Cache profiling enable
-                CACHEPROFEN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disable cache profiling
-                        Disabled = 0x0,
-                        ///  Enable cache profiling
-                        Enabled = 0x1,
-                    },
-                },
-                padding: u23,
-            }),
-            reserved1352: [4]u8,
-            ///  I-code cache hit counter.
-            IHIT: mmio.Mmio(packed struct(u32) {
-                ///  Number of cache hits
-                HITS: u32,
-            }),
-            ///  I-code cache miss counter.
-            IMISS: mmio.Mmio(packed struct(u32) {
-                ///  Number of cache misses
-                MISSES: u32,
-            }),
-        };
-    };
-};

From 597843c4c1759dd62baf0cbec9e4d0a391c4586c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Fri, 22 Sep 2023 09:02:37 +0200
Subject: [PATCH 205/286] Microzig Generation 2 Build Interface  (#26)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* Drops microzig dependency
* Starts to port to MicroZig Build Gen 2
* Drops CI

---------

Co-authored-by: Felix "xq" Queißner 
---
 .github/workflows/build.yml |   19 -
 build.zig                   |  102 ++-
 build.zig.zon               |    7 +-
 src/boards.zig              |   12 -
 src/chips.zig               |    9 -
 src/chips/ATmega328P.zig    | 1388 -----------------------------------
 6 files changed, 78 insertions(+), 1459 deletions(-)
 delete mode 100644 .github/workflows/build.yml
 delete mode 100644 src/chips/ATmega328P.zig

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
deleted file mode 100644
index 63ea5331c..000000000
--- a/.github/workflows/build.yml
+++ /dev/null
@@ -1,19 +0,0 @@
-name: Build
-on:
-  push:
-
-jobs:
-  build:
-    runs-on: ${{ matrix.os }}
-    strategy:
-      matrix:
-        os: [ubuntu-latest, windows-latest, macos-latest]
-        optimize: [Debug, ReleaseSmall, ReleaseFast, ReleaseSafe]
-    steps:
-      - uses: actions/checkout@v2
-      - uses: goto-bus-stop/setup-zig@v2.1.1
-        with:
-          version: 0.11.0
-
-      - name: Build
-        run: zig build install "-Doptimize=${{matrix.optimize}}"
diff --git a/build.zig b/build.zig
index dd84d30ca..19ba0769f 100644
--- a/build.zig
+++ b/build.zig
@@ -1,32 +1,84 @@
 const std = @import("std");
-const microzig = @import("microzig");
 
-pub const boards = @import("src/boards.zig");
-pub const chips = @import("src/chips.zig");
+fn path(comptime suffix: []const u8) std.Build.LazyPath {
+    return .{
+        .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
+    };
+}
 
-pub fn build(b: *std.build.Builder) void {
-    const optimize = b.standardOptimizeOption(.{});
-    inline for (@typeInfo(boards).Struct.decls) |decl| {
-        const exe = microzig.addEmbeddedExecutable(b, .{
-            .name = @field(boards, decl.name).name ++ ".minimal",
-            .source_file = .{
-                .path = "test/programs/minimal.zig",
+const hal = .{
+    .source_file = path("/src/hals/ATmega328P.zig"),
+};
+
+pub const chips = struct {
+    pub const atmega328p = .{
+        .preferred_format = .hex,
+        .chip = .{
+            .name = "ATmega328P",
+            .url = "https://www.microchip.com/en-us/product/atmega328p",
+            .cpu = .avr5,
+            .register_definition = .{
+                .json = path("/src/chips/ATmega328P.json"),
             },
-            .backing = .{ .board = @field(boards, decl.name) },
-            .optimize = optimize,
-        });
-        exe.installArtifact(b);
-    }
+            .memory_regions = &.{
+                .{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash },
+                .{ .offset = 0x800100, .length = 2048, .kind = .ram },
+            },
+        },
+        .hal = hal,
+    };
+};
 
-    inline for (@typeInfo(chips).Struct.decls) |decl| {
-        const exe = microzig.addEmbeddedExecutable(b, .{
-            .name = @field(chips, decl.name).name ++ ".minimal",
-            .source_file = .{
-                .path = "test/programs/minimal.zig",
+pub const boards = struct {
+    pub const arduino = struct {
+        pub const nano = .{
+            .preferred_format = .hex,
+            .chip = chips.atmega328p.chip,
+            .hal = hal,
+            .board = .{
+                .name = "Arduino Nano",
+                .url = "https://docs.arduino.cc/hardware/nano",
+                .source_file = path("/src/boards/arduino_nano.zig"),
             },
-            .backing = .{ .chip = @field(chips, decl.name) },
-            .optimize = optimize,
-        });
-        exe.installArtifact(b);
-    }
+        };
+
+        pub const uno_rev3 = .{
+            .preferred_format = .hex,
+            .chip = chips.atmega328p.chip,
+            .hal = hal,
+            .board = .{
+                .name = "Arduino Uno",
+                .url = "https://docs.arduino.cc/hardware/uno-rev3",
+                .source_file = path("/src/boards/arduino_uno.zig"),
+            },
+        };
+    };
+};
+
+pub fn build(b: *std.build.Builder) void {
+    _ = b;
+    // const optimize = b.standardOptimizeOption(.{});
+    // inline for (@typeInfo(boards).Struct.decls) |decl| {
+    //     const exe = microzig.addEmbeddedExecutable(b, .{
+    //         .name = @field(boards, decl.name).name ++ ".minimal",
+    //         .source_file = .{
+    //             .path = "test/programs/minimal.zig",
+    //         },
+    //         .backing = .{ .board = @field(boards, decl.name) },
+    //         .optimize = optimize,
+    //     });
+    //     exe.installArtifact(b);
+    // }
+
+    // inline for (@typeInfo(chips).Struct.decls) |decl| {
+    //     const exe = microzig.addEmbeddedExecutable(b, .{
+    //         .name = @field(chips, decl.name).name ++ ".minimal",
+    //         .source_file = .{
+    //             .path = "test/programs/minimal.zig",
+    //         },
+    //         .backing = .{ .chip = @field(chips, decl.name) },
+    //         .optimize = optimize,
+    //     });
+    //     exe.installArtifact(b);
+    // }
 }
diff --git a/build.zig.zon b/build.zig.zon
index e8787ef0b..fd45779e6 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -1,10 +1,5 @@
 .{
     .name = "microzig-espressif-esp",
     .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
-            .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
-        },
-    },
+    .dependencies = .{},
 }
diff --git a/src/boards.zig b/src/boards.zig
index 0691ab575..a6be3d0b4 100644
--- a/src/boards.zig
+++ b/src/boards.zig
@@ -5,15 +5,3 @@ const chips = @import("chips.zig");
 fn root_dir() []const u8 {
     return std.fs.path.dirname(@src().file) orelse unreachable;
 }
-
-pub const arduino_nano = micro.Board{
-    .name = "Arduino Nano",
-    .source = .{ .path = root_dir() ++ "/boards/arduino_nano.zig" },
-    .chip = chips.atmega328p,
-};
-
-pub const arduino_uno = micro.Board{
-    .name = "Arduino Uno",
-    .source = .{ .path = root_dir() ++ "/boards/arduino_uno.zig" },
-    .chip = chips.atmega328p,
-};
diff --git a/src/chips.zig b/src/chips.zig
index a1c7d58f2..c46427f7d 100644
--- a/src/chips.zig
+++ b/src/chips.zig
@@ -6,12 +6,3 @@ const MemoryRegion = micro.MemoryRegion;
 fn root_dir() []const u8 {
     return std.fs.path.dirname(@src().file) orelse ".";
 }
-
-pub const atmega328p = Chip.from_standard_paths(root_dir(), .{
-    .name = "ATmega328P",
-    .cpu = micro.cpus.avr5,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x000000, .length = 32 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x800100, .length = 2048, .kind = .ram },
-    },
-});
diff --git a/src/chips/ATmega328P.zig b/src/chips/ATmega328P.zig
deleted file mode 100644
index 6ea04102c..000000000
--- a/src/chips/ATmega328P.zig
+++ /dev/null
@@ -1,1388 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    pub const ATmega328P = struct {
-        pub const properties = struct {
-            pub const family = "megaAVR";
-            pub const arch = "AVR8";
-        };
-
-        pub const VectorTable = extern struct {
-            const Handler = micro.interrupt.Handler;
-            const unhandled = micro.interrupt.unhandled;
-
-            RESET: Handler = unhandled,
-            ///  External Interrupt Request 0
-            INT0: Handler = unhandled,
-            ///  External Interrupt Request 1
-            INT1: Handler = unhandled,
-            ///  Pin Change Interrupt Request 0
-            PCINT0: Handler = unhandled,
-            ///  Pin Change Interrupt Request 1
-            PCINT1: Handler = unhandled,
-            ///  Pin Change Interrupt Request 2
-            PCINT2: Handler = unhandled,
-            ///  Watchdog Time-out Interrupt
-            WDT: Handler = unhandled,
-            ///  Timer/Counter2 Compare Match A
-            TIMER2_COMPA: Handler = unhandled,
-            ///  Timer/Counter2 Compare Match B
-            TIMER2_COMPB: Handler = unhandled,
-            ///  Timer/Counter2 Overflow
-            TIMER2_OVF: Handler = unhandled,
-            ///  Timer/Counter1 Capture Event
-            TIMER1_CAPT: Handler = unhandled,
-            ///  Timer/Counter1 Compare Match A
-            TIMER1_COMPA: Handler = unhandled,
-            ///  Timer/Counter1 Compare Match B
-            TIMER1_COMPB: Handler = unhandled,
-            ///  Timer/Counter1 Overflow
-            TIMER1_OVF: Handler = unhandled,
-            ///  TimerCounter0 Compare Match A
-            TIMER0_COMPA: Handler = unhandled,
-            ///  TimerCounter0 Compare Match B
-            TIMER0_COMPB: Handler = unhandled,
-            ///  Timer/Couner0 Overflow
-            TIMER0_OVF: Handler = unhandled,
-            ///  SPI Serial Transfer Complete
-            SPI_STC: Handler = unhandled,
-            ///  USART Rx Complete
-            USART_RX: Handler = unhandled,
-            ///  USART, Data Register Empty
-            USART_UDRE: Handler = unhandled,
-            ///  USART Tx Complete
-            USART_TX: Handler = unhandled,
-            ///  ADC Conversion Complete
-            ADC: Handler = unhandled,
-            ///  EEPROM Ready
-            EE_READY: Handler = unhandled,
-            ///  Analog Comparator
-            ANALOG_COMP: Handler = unhandled,
-            ///  Two-wire Serial Interface
-            TWI: Handler = unhandled,
-            ///  Store Program Memory Read
-            SPM_Ready: Handler = unhandled,
-        };
-
-        pub const peripherals = struct {
-            ///  Fuses
-            pub const FUSE = @as(*volatile types.peripherals.FUSE, @ptrFromInt(0x0));
-            ///  Lockbits
-            pub const LOCKBIT = @as(*volatile types.peripherals.LOCKBIT, @ptrFromInt(0x0));
-            ///  I/O Port
-            pub const PORTB = @as(*volatile types.peripherals.PORT.PORTB, @ptrFromInt(0x23));
-            ///  I/O Port
-            pub const PORTC = @as(*volatile types.peripherals.PORT.PORTC, @ptrFromInt(0x26));
-            ///  I/O Port
-            pub const PORTD = @as(*volatile types.peripherals.PORT.PORTD, @ptrFromInt(0x29));
-            ///  Timer/Counter, 8-bit
-            pub const TC0 = @as(*volatile types.peripherals.TC8.TC0, @ptrFromInt(0x35));
-            ///  Timer/Counter, 16-bit
-            pub const TC1 = @as(*volatile types.peripherals.TC16.TC1, @ptrFromInt(0x36));
-            ///  Timer/Counter, 8-bit Async
-            pub const TC2 = @as(*volatile types.peripherals.TC8_ASYNC.TC2, @ptrFromInt(0x37));
-            ///  External Interrupts
-            pub const EXINT = @as(*volatile types.peripherals.EXINT, @ptrFromInt(0x3b));
-            ///  CPU Registers
-            pub const CPU = @as(*volatile types.peripherals.CPU, @ptrFromInt(0x3e));
-            ///  EEPROM
-            pub const EEPROM = @as(*volatile types.peripherals.EEPROM, @ptrFromInt(0x3f));
-            ///  Serial Peripheral Interface
-            pub const SPI = @as(*volatile types.peripherals.SPI, @ptrFromInt(0x4c));
-            ///  Analog Comparator
-            pub const AC = @as(*volatile types.peripherals.AC, @ptrFromInt(0x50));
-            ///  Watchdog Timer
-            pub const WDT = @as(*volatile types.peripherals.WDT, @ptrFromInt(0x60));
-            ///  Analog-to-Digital Converter
-            pub const ADC = @as(*volatile types.peripherals.ADC, @ptrFromInt(0x78));
-            ///  Two Wire Serial Interface
-            pub const TWI = @as(*volatile types.peripherals.TWI, @ptrFromInt(0xb8));
-            ///  USART
-            pub const USART0 = @as(*volatile types.peripherals.USART.USART0, @ptrFromInt(0xc0));
-        };
-    };
-};
-
-pub const types = struct {
-    pub const peripherals = struct {
-        ///  Fuses
-        pub const FUSE = extern struct {
-            pub const ENUM_SUT_CKSEL = enum(u6) {
-                ///  Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
-                EXTCLK_6CK_14CK_0MS = 0x0,
-                ///  Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
-                EXTCLK_6CK_14CK_4MS1 = 0x10,
-                ///  Ext. Clock; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
-                EXTCLK_6CK_14CK_65MS = 0x20,
-                ///  Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
-                INTRCOSC_8MHZ_6CK_14CK_0MS = 0x2,
-                ///  Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
-                INTRCOSC_8MHZ_6CK_14CK_4MS1 = 0x12,
-                ///  Int. RC Osc. 8 MHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
-                INTRCOSC_8MHZ_6CK_14CK_65MS = 0x22,
-                ///  Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 0 ms
-                INTRCOSC_128KHZ_6CK_14CK_0MS = 0x3,
-                ///  Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 4.1 ms
-                INTRCOSC_128KHZ_6CK_14CK_4MS1 = 0x13,
-                ///  Int. RC Osc. 128kHz; Start-up time PWRDWN/RESET: 6 CK/14 CK + 65 ms
-                INTRCOSC_128KHZ_6CK_14CK_65MS = 0x23,
-                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 0 ms
-                EXTLOFXTAL_1KCK_14CK_0MS = 0x4,
-                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 4.1 ms
-                EXTLOFXTAL_1KCK_14CK_4MS1 = 0x14,
-                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 1K CK/14 CK + 65 ms
-                EXTLOFXTAL_1KCK_14CK_65MS = 0x24,
-                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 0 ms
-                EXTLOFXTAL_32KCK_14CK_0MS = 0x5,
-                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 4.1 ms
-                EXTLOFXTAL_32KCK_14CK_4MS1 = 0x15,
-                ///  Ext. Low-Freq. Crystal; Start-up time PWRDWN/RESET: 32K CK/14 CK + 65 ms
-                EXTLOFXTAL_32KCK_14CK_65MS = 0x25,
-                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
-                EXTFSXTAL_258CK_14CK_4MS1 = 0x6,
-                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
-                EXTFSXTAL_258CK_14CK_65MS = 0x16,
-                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
-                EXTFSXTAL_1KCK_14CK_0MS = 0x26,
-                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
-                EXTFSXTAL_1KCK_14CK_4MS1 = 0x36,
-                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
-                EXTFSXTAL_1KCK_14CK_65MS = 0x7,
-                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
-                EXTFSXTAL_16KCK_14CK_0MS = 0x17,
-                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
-                EXTFSXTAL_16KCK_14CK_4MS1 = 0x27,
-                ///  Ext. Full-swing Crystal; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
-                EXTFSXTAL_16KCK_14CK_65MS = 0x37,
-                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
-                EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_4MS1 = 0x8,
-                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
-                EXTXOSC_0MHZ4_0MHZ9_258CK_14CK_65MS = 0x18,
-                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
-                EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_0MS = 0x28,
-                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
-                EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_4MS1 = 0x38,
-                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
-                EXTXOSC_0MHZ4_0MHZ9_1KCK_14CK_65MS = 0x9,
-                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
-                EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_0MS = 0x19,
-                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
-                EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_4MS1 = 0x29,
-                ///  Ext. Crystal Osc. 0.4-0.9 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
-                EXTXOSC_0MHZ4_0MHZ9_16KCK_14CK_65MS = 0x39,
-                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
-                EXTXOSC_0MHZ9_3MHZ_258CK_14CK_4MS1 = 0xa,
-                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
-                EXTXOSC_0MHZ9_3MHZ_258CK_14CK_65MS = 0x1a,
-                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
-                EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_0MS = 0x2a,
-                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
-                EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_4MS1 = 0x3a,
-                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
-                EXTXOSC_0MHZ9_3MHZ_1KCK_14CK_65MS = 0xb,
-                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
-                EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_0MS = 0x1b,
-                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
-                EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_4MS1 = 0x2b,
-                ///  Ext. Crystal Osc. 0.9-3.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
-                EXTXOSC_0MHZ9_3MHZ_16KCK_14CK_65MS = 0x3b,
-                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
-                EXTXOSC_3MHZ_8MHZ_258CK_14CK_4MS1 = 0xc,
-                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
-                EXTXOSC_3MHZ_8MHZ_258CK_14CK_65MS = 0x1c,
-                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
-                EXTXOSC_3MHZ_8MHZ_1KCK_14CK_0MS = 0x2c,
-                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
-                EXTXOSC_3MHZ_8MHZ_1KCK_14CK_4MS1 = 0x3c,
-                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
-                EXTXOSC_3MHZ_8MHZ_1KCK_14CK_65MS = 0xd,
-                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
-                EXTXOSC_3MHZ_8MHZ_16KCK_14CK_0MS = 0x1d,
-                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
-                EXTXOSC_3MHZ_8MHZ_16KCK_14CK_4MS1 = 0x2d,
-                ///  Ext. Crystal Osc. 3.0-8.0 MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
-                EXTXOSC_3MHZ_8MHZ_16KCK_14CK_65MS = 0x3d,
-                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 4.1 ms
-                EXTXOSC_8MHZ_XX_258CK_14CK_4MS1 = 0xe,
-                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 258 CK/14 CK + 65 ms
-                EXTXOSC_8MHZ_XX_258CK_14CK_65MS = 0x1e,
-                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 0 ms
-                EXTXOSC_8MHZ_XX_1KCK_14CK_0MS = 0x2e,
-                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 4.1 ms
-                EXTXOSC_8MHZ_XX_1KCK_14CK_4MS1 = 0x3e,
-                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 1K CK /14 CK + 65 ms
-                EXTXOSC_8MHZ_XX_1KCK_14CK_65MS = 0xf,
-                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 0 ms
-                EXTXOSC_8MHZ_XX_16KCK_14CK_0MS = 0x1f,
-                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 4.1 ms
-                EXTXOSC_8MHZ_XX_16KCK_14CK_4MS1 = 0x2f,
-                ///  Ext. Crystal Osc. 8.0- MHz; Start-up time PWRDWN/RESET: 16K CK/14 CK + 65 ms
-                EXTXOSC_8MHZ_XX_16KCK_14CK_65MS = 0x3f,
-                _,
-            };
-
-            pub const ENUM_BODLEVEL = enum(u3) {
-                ///  Brown-out detection at VCC=4.3 V
-                @"4V3" = 0x4,
-                ///  Brown-out detection at VCC=2.7 V
-                @"2V7" = 0x5,
-                ///  Brown-out detection at VCC=1.8 V
-                @"1V8" = 0x6,
-                ///  Brown-out detection disabled
-                DISABLED = 0x7,
-                _,
-            };
-
-            pub const ENUM_BOOTSZ = enum(u2) {
-                ///  Boot Flash size=256 words start address=$3F00
-                @"256W_3F00" = 0x3,
-                ///  Boot Flash size=512 words start address=$3E00
-                @"512W_3E00" = 0x2,
-                ///  Boot Flash size=1024 words start address=$3C00
-                @"1024W_3C00" = 0x1,
-                ///  Boot Flash size=2048 words start address=$3800
-                @"2048W_3800" = 0x0,
-            };
-
-            LOW: mmio.Mmio(packed struct(u8) {
-                ///  Select Clock Source
-                SUT_CKSEL: packed union {
-                    raw: u6,
-                    value: ENUM_SUT_CKSEL,
-                },
-                ///  Clock output on PORTB0
-                CKOUT: u1,
-                ///  Divide clock by 8 internally
-                CKDIV8: u1,
-            }),
-            HIGH: mmio.Mmio(packed struct(u8) {
-                ///  Boot Reset vector Enabled
-                BOOTRST: u1,
-                ///  Select boot size
-                BOOTSZ: packed union {
-                    raw: u2,
-                    value: ENUM_BOOTSZ,
-                },
-                ///  Preserve EEPROM through the Chip Erase cycle
-                EESAVE: u1,
-                ///  Watch-dog Timer always on
-                WDTON: u1,
-                ///  Serial program downloading (SPI) enabled
-                SPIEN: u1,
-                ///  Debug Wire enable
-                DWEN: u1,
-                ///  Reset Disabled (Enable PC6 as i/o pin)
-                RSTDISBL: u1,
-            }),
-            EXTENDED: mmio.Mmio(packed struct(u8) {
-                ///  Brown-out Detector trigger level
-                BODLEVEL: packed union {
-                    raw: u3,
-                    value: ENUM_BODLEVEL,
-                },
-                padding: u5,
-            }),
-        };
-
-        ///  Lockbits
-        pub const LOCKBIT = extern struct {
-            pub const ENUM_LB = enum(u2) {
-                ///  Further programming and verification disabled
-                PROG_VER_DISABLED = 0x0,
-                ///  Further programming disabled
-                PROG_DISABLED = 0x2,
-                ///  No memory lock features enabled
-                NO_LOCK = 0x3,
-                _,
-            };
-
-            pub const ENUM_BLB = enum(u2) {
-                ///  LPM and SPM prohibited in Application Section
-                LPM_SPM_DISABLE = 0x0,
-                ///  LPM prohibited in Application Section
-                LPM_DISABLE = 0x1,
-                ///  SPM prohibited in Application Section
-                SPM_DISABLE = 0x2,
-                ///  No lock on SPM and LPM in Application Section
-                NO_LOCK = 0x3,
-            };
-
-            pub const ENUM_BLB2 = enum(u2) {
-                ///  LPM and SPM prohibited in Boot Section
-                LPM_SPM_DISABLE = 0x0,
-                ///  LPM prohibited in Boot Section
-                LPM_DISABLE = 0x1,
-                ///  SPM prohibited in Boot Section
-                SPM_DISABLE = 0x2,
-                ///  No lock on SPM and LPM in Boot Section
-                NO_LOCK = 0x3,
-            };
-
-            LOCKBIT: mmio.Mmio(packed struct(u8) {
-                ///  Memory Lock
-                LB: packed union {
-                    raw: u2,
-                    value: ENUM_LB,
-                },
-                ///  Boot Loader Protection Mode
-                BLB0: packed union {
-                    raw: u2,
-                    value: ENUM_BLB,
-                },
-                ///  Boot Loader Protection Mode
-                BLB1: packed union {
-                    raw: u2,
-                    value: ENUM_BLB2,
-                },
-                padding: u2,
-            }),
-        };
-
-        ///  USART
-        pub const USART = struct {
-            pub const COMM_USART_MODE_2BIT = enum(u2) {
-                ///  Asynchronous USART
-                ASYNCHRONOUS_USART = 0x0,
-                ///  Synchronous USART
-                SYNCHRONOUS_USART = 0x1,
-                ///  Master SPI
-                MASTER_SPI = 0x3,
-                _,
-            };
-
-            pub const COMM_UPM_PARITY_MODE = enum(u2) {
-                ///  Disabled
-                DISABLED = 0x0,
-                ///  Reserved
-                RESERVED = 0x1,
-                ///  Enabled, Even Parity
-                ENABLED_EVEN_PARITY = 0x2,
-                ///  Enabled, Odd Parity
-                ENABLED_ODD_PARITY = 0x3,
-            };
-
-            pub const COMM_STOP_BIT_SEL = enum(u1) {
-                ///  1-bit
-                @"1_BIT" = 0x0,
-                ///  2-bit
-                @"2_BIT" = 0x1,
-            };
-
-            ///  USART
-            pub const USART0 = extern struct {
-                ///  USART Control and Status Register A
-                UCSR0A: mmio.Mmio(packed struct(u8) {
-                    ///  Multi-processor Communication Mode
-                    MPCM0: u1,
-                    ///  Double the USART transmission speed
-                    U2X0: u1,
-                    ///  Parity Error
-                    UPE0: u1,
-                    ///  Data overRun
-                    DOR0: u1,
-                    ///  Framing Error
-                    FE0: u1,
-                    ///  USART Data Register Empty
-                    UDRE0: u1,
-                    ///  USART Transmitt Complete
-                    TXC0: u1,
-                    ///  USART Receive Complete
-                    RXC0: u1,
-                }),
-                ///  USART Control and Status Register B
-                UCSR0B: mmio.Mmio(packed struct(u8) {
-                    ///  Transmit Data Bit 8
-                    TXB80: u1,
-                    ///  Receive Data Bit 8
-                    RXB80: u1,
-                    ///  Character Size - together with UCSZ0 in UCSR0C
-                    UCSZ02: u1,
-                    ///  Transmitter Enable
-                    TXEN0: u1,
-                    ///  Receiver Enable
-                    RXEN0: u1,
-                    ///  USART Data register Empty Interrupt Enable
-                    UDRIE0: u1,
-                    ///  TX Complete Interrupt Enable
-                    TXCIE0: u1,
-                    ///  RX Complete Interrupt Enable
-                    RXCIE0: u1,
-                }),
-                ///  USART Control and Status Register C
-                UCSR0C: mmio.Mmio(packed struct(u8) {
-                    ///  Clock Polarity
-                    UCPOL0: u1,
-                    ///  Character Size - together with UCSZ2 in UCSR0B
-                    UCSZ0: u2,
-                    ///  Stop Bit Select
-                    USBS0: packed union {
-                        raw: u1,
-                        value: COMM_STOP_BIT_SEL,
-                    },
-                    ///  Parity Mode Bits
-                    UPM0: packed union {
-                        raw: u2,
-                        value: COMM_UPM_PARITY_MODE,
-                    },
-                    ///  USART Mode Select
-                    UMSEL0: packed union {
-                        raw: u2,
-                        value: COMM_USART_MODE_2BIT,
-                    },
-                }),
-                reserved4: [1]u8,
-                ///  USART Baud Rate Register Bytes
-                UBRR0: u16,
-                ///  USART I/O Data Register
-                UDR0: u8,
-            };
-        };
-
-        ///  Two Wire Serial Interface
-        pub const TWI = extern struct {
-            pub const COMM_TWI_PRESACLE = enum(u2) {
-                ///  1
-                @"1" = 0x0,
-                ///  4
-                @"4" = 0x1,
-                ///  16
-                @"16" = 0x2,
-                ///  64
-                @"64" = 0x3,
-            };
-
-            ///  TWI Bit Rate register
-            TWBR: u8,
-            ///  TWI Status Register
-            TWSR: mmio.Mmio(packed struct(u8) {
-                ///  TWI Prescaler
-                TWPS: packed union {
-                    raw: u2,
-                    value: COMM_TWI_PRESACLE,
-                },
-                reserved3: u1,
-                ///  TWI Status
-                TWS: u5,
-            }),
-            ///  TWI (Slave) Address register
-            TWAR: mmio.Mmio(packed struct(u8) {
-                ///  TWI General Call Recognition Enable Bit
-                TWGCE: u1,
-                ///  TWI (Slave) Address register Bits
-                TWA: u7,
-            }),
-            ///  TWI Data register
-            TWDR: u8,
-            ///  TWI Control Register
-            TWCR: mmio.Mmio(packed struct(u8) {
-                ///  TWI Interrupt Enable
-                TWIE: u1,
-                reserved2: u1,
-                ///  TWI Enable Bit
-                TWEN: u1,
-                ///  TWI Write Collition Flag
-                TWWC: u1,
-                ///  TWI Stop Condition Bit
-                TWSTO: u1,
-                ///  TWI Start Condition Bit
-                TWSTA: u1,
-                ///  TWI Enable Acknowledge Bit
-                TWEA: u1,
-                ///  TWI Interrupt Flag
-                TWINT: u1,
-            }),
-            ///  TWI (Slave) Address Mask Register
-            TWAMR: mmio.Mmio(packed struct(u8) {
-                reserved1: u1,
-                TWAM: u7,
-            }),
-        };
-
-        ///  Timer/Counter, 16-bit
-        pub const TC16 = struct {
-            pub const CLK_SEL_3BIT_EXT = enum(u3) {
-                ///  No Clock Source (Stopped)
-                NO_CLOCK_SOURCE_STOPPED = 0x0,
-                ///  Running, No Prescaling
-                RUNNING_NO_PRESCALING = 0x1,
-                ///  Running, CLK/8
-                RUNNING_CLK_8 = 0x2,
-                ///  Running, CLK/64
-                RUNNING_CLK_64 = 0x3,
-                ///  Running, CLK/256
-                RUNNING_CLK_256 = 0x4,
-                ///  Running, CLK/1024
-                RUNNING_CLK_1024 = 0x5,
-                ///  Running, ExtClk Tn Falling Edge
-                RUNNING_EXTCLK_TN_FALLING_EDGE = 0x6,
-                ///  Running, ExtClk Tn Rising Edge
-                RUNNING_EXTCLK_TN_RISING_EDGE = 0x7,
-            };
-
-            ///  Timer/Counter, 16-bit
-            pub const TC1 = extern struct {
-                ///  Timer/Counter Interrupt Flag register
-                TIFR1: mmio.Mmio(packed struct(u8) {
-                    ///  Timer/Counter1 Overflow Flag
-                    TOV1: u1,
-                    ///  Output Compare Flag 1A
-                    OCF1A: u1,
-                    ///  Output Compare Flag 1B
-                    OCF1B: u1,
-                    reserved5: u2,
-                    ///  Input Capture Flag 1
-                    ICF1: u1,
-                    padding: u2,
-                }),
-                reserved13: [12]u8,
-                ///  General Timer/Counter Control Register
-                GTCCR: mmio.Mmio(packed struct(u8) {
-                    ///  Prescaler Reset Timer/Counter1 and Timer/Counter0
-                    PSRSYNC: u1,
-                    reserved7: u6,
-                    ///  Timer/Counter Synchronization Mode
-                    TSM: u1,
-                }),
-                reserved57: [43]u8,
-                ///  Timer/Counter Interrupt Mask Register
-                TIMSK1: mmio.Mmio(packed struct(u8) {
-                    ///  Timer/Counter1 Overflow Interrupt Enable
-                    TOIE1: u1,
-                    ///  Timer/Counter1 Output CompareA Match Interrupt Enable
-                    OCIE1A: u1,
-                    ///  Timer/Counter1 Output CompareB Match Interrupt Enable
-                    OCIE1B: u1,
-                    reserved5: u2,
-                    ///  Timer/Counter1 Input Capture Interrupt Enable
-                    ICIE1: u1,
-                    padding: u2,
-                }),
-                reserved74: [16]u8,
-                ///  Timer/Counter1 Control Register A
-                TCCR1A: mmio.Mmio(packed struct(u8) {
-                    ///  Waveform Generation Mode
-                    WGM1: u2,
-                    reserved4: u2,
-                    ///  Compare Output Mode 1B, bits
-                    COM1B: u2,
-                    ///  Compare Output Mode 1A, bits
-                    COM1A: u2,
-                }),
-                ///  Timer/Counter1 Control Register B
-                TCCR1B: mmio.Mmio(packed struct(u8) {
-                    ///  Prescaler source of Timer/Counter 1
-                    CS1: packed union {
-                        raw: u3,
-                        value: CLK_SEL_3BIT_EXT,
-                    },
-                    ///  Waveform Generation Mode
-                    WGM1: u2,
-                    reserved6: u1,
-                    ///  Input Capture 1 Edge Select
-                    ICES1: u1,
-                    ///  Input Capture 1 Noise Canceler
-                    ICNC1: u1,
-                }),
-                ///  Timer/Counter1 Control Register C
-                TCCR1C: mmio.Mmio(packed struct(u8) {
-                    reserved6: u6,
-                    FOC1B: u1,
-                    FOC1A: u1,
-                }),
-                reserved78: [1]u8,
-                ///  Timer/Counter1 Bytes
-                TCNT1: u16,
-                ///  Timer/Counter1 Input Capture Register Bytes
-                ICR1: u16,
-                ///  Timer/Counter1 Output Compare Register Bytes
-                OCR1A: u16,
-                ///  Timer/Counter1 Output Compare Register Bytes
-                OCR1B: u16,
-            };
-        };
-
-        ///  Timer/Counter, 8-bit Async
-        pub const TC8_ASYNC = struct {
-            pub const CLK_SEL_3BIT = enum(u3) {
-                ///  No Clock Source (Stopped)
-                NO_CLOCK_SOURCE_STOPPED = 0x0,
-                ///  Running, No Prescaling
-                RUNNING_NO_PRESCALING = 0x1,
-                ///  Running, CLK/8
-                RUNNING_CLK_8 = 0x2,
-                ///  Running, CLK/32
-                RUNNING_CLK_32 = 0x3,
-                ///  Running, CLK/64
-                RUNNING_CLK_64 = 0x4,
-                ///  Running, CLK/128
-                RUNNING_CLK_128 = 0x5,
-                ///  Running, CLK/256
-                RUNNING_CLK_256 = 0x6,
-                ///  Running, CLK/1024
-                RUNNING_CLK_1024 = 0x7,
-            };
-
-            ///  Timer/Counter, 8-bit Async
-            pub const TC2 = extern struct {
-                ///  Timer/Counter Interrupt Flag Register
-                TIFR2: mmio.Mmio(packed struct(u8) {
-                    ///  Timer/Counter2 Overflow Flag
-                    TOV2: u1,
-                    ///  Output Compare Flag 2A
-                    OCF2A: u1,
-                    ///  Output Compare Flag 2B
-                    OCF2B: u1,
-                    padding: u5,
-                }),
-                reserved12: [11]u8,
-                ///  General Timer Counter Control register
-                GTCCR: mmio.Mmio(packed struct(u8) {
-                    reserved1: u1,
-                    ///  Prescaler Reset Timer/Counter2
-                    PSRASY: u1,
-                    reserved7: u5,
-                    ///  Timer/Counter Synchronization Mode
-                    TSM: u1,
-                }),
-                reserved57: [44]u8,
-                ///  Timer/Counter Interrupt Mask register
-                TIMSK2: mmio.Mmio(packed struct(u8) {
-                    ///  Timer/Counter2 Overflow Interrupt Enable
-                    TOIE2: u1,
-                    ///  Timer/Counter2 Output Compare Match A Interrupt Enable
-                    OCIE2A: u1,
-                    ///  Timer/Counter2 Output Compare Match B Interrupt Enable
-                    OCIE2B: u1,
-                    padding: u5,
-                }),
-                reserved121: [63]u8,
-                ///  Timer/Counter2 Control Register A
-                TCCR2A: mmio.Mmio(packed struct(u8) {
-                    ///  Waveform Genration Mode
-                    WGM2: u2,
-                    reserved4: u2,
-                    ///  Compare Output Mode bits
-                    COM2B: u2,
-                    ///  Compare Output Mode bits
-                    COM2A: u2,
-                }),
-                ///  Timer/Counter2 Control Register B
-                TCCR2B: mmio.Mmio(packed struct(u8) {
-                    ///  Clock Select bits
-                    CS2: packed union {
-                        raw: u3,
-                        value: CLK_SEL_3BIT,
-                    },
-                    ///  Waveform Generation Mode
-                    WGM22: u1,
-                    reserved6: u2,
-                    ///  Force Output Compare B
-                    FOC2B: u1,
-                    ///  Force Output Compare A
-                    FOC2A: u1,
-                }),
-                ///  Timer/Counter2
-                TCNT2: u8,
-                ///  Timer/Counter2 Output Compare Register A
-                OCR2A: u8,
-                ///  Timer/Counter2 Output Compare Register B
-                OCR2B: u8,
-                reserved127: [1]u8,
-                ///  Asynchronous Status Register
-                ASSR: mmio.Mmio(packed struct(u8) {
-                    ///  Timer/Counter Control Register2 Update Busy
-                    TCR2BUB: u1,
-                    ///  Timer/Counter Control Register2 Update Busy
-                    TCR2AUB: u1,
-                    ///  Output Compare Register 2 Update Busy
-                    OCR2BUB: u1,
-                    ///  Output Compare Register2 Update Busy
-                    OCR2AUB: u1,
-                    ///  Timer/Counter2 Update Busy
-                    TCN2UB: u1,
-                    ///  Asynchronous Timer/Counter2
-                    AS2: u1,
-                    ///  Enable External Clock Input
-                    EXCLK: u1,
-                    padding: u1,
-                }),
-            };
-        };
-
-        ///  Analog-to-Digital Converter
-        pub const ADC = extern struct {
-            pub const ANALOG_ADC_V_REF3 = enum(u2) {
-                ///  AREF, Internal Vref turned off
-                AREF_INTERNAL_VREF_TURNED_OFF = 0x0,
-                ///  AVCC with external capacitor at AREF pin
-                AVCC_WITH_EXTERNAL_CAPACITOR_AT_AREF_PIN = 0x1,
-                ///  Reserved
-                RESERVED = 0x2,
-                ///  Internal 1.1V Voltage Reference with external capacitor at AREF pin
-                INTERNAL_1_1V_VOLTAGE_REFERENCE_WITH_EXTERNAL_CAPACITOR_AT_AREF_PIN = 0x3,
-            };
-
-            pub const ADC_MUX_SINGLE = enum(u4) {
-                ///  ADC Single Ended Input pin 0
-                ADC0 = 0x0,
-                ///  ADC Single Ended Input pin 1
-                ADC1 = 0x1,
-                ///  ADC Single Ended Input pin 2
-                ADC2 = 0x2,
-                ///  ADC Single Ended Input pin 3
-                ADC3 = 0x3,
-                ///  ADC Single Ended Input pin 4
-                ADC4 = 0x4,
-                ///  ADC Single Ended Input pin 5
-                ADC5 = 0x5,
-                ///  ADC Single Ended Input pin 6
-                ADC6 = 0x6,
-                ///  ADC Single Ended Input pin 7
-                ADC7 = 0x7,
-                ///  Temperature sensor
-                TEMPSENS = 0x8,
-                ///  Internal Reference (VBG)
-                ADC_VBG = 0xe,
-                ///  0V (GND)
-                ADC_GND = 0xf,
-                _,
-            };
-
-            pub const ANALOG_ADC_PRESCALER = enum(u3) {
-                ///  2
-                @"2" = 0x0,
-                ///  2
-                @"2" = 0x1,
-                ///  4
-                @"4" = 0x2,
-                ///  8
-                @"8" = 0x3,
-                ///  16
-                @"16" = 0x4,
-                ///  32
-                @"32" = 0x5,
-                ///  64
-                @"64" = 0x6,
-                ///  128
-                @"128" = 0x7,
-            };
-
-            pub const ANALOG_ADC_AUTO_TRIGGER = enum(u3) {
-                ///  Free Running mode
-                FREE_RUNNING_MODE = 0x0,
-                ///  Analog Comparator
-                ANALOG_COMPARATOR = 0x1,
-                ///  External Interrupt Request 0
-                EXTERNAL_INTERRUPT_REQUEST_0 = 0x2,
-                ///  Timer/Counter0 Compare Match A
-                TIMER_COUNTER0_COMPARE_MATCH_A = 0x3,
-                ///  Timer/Counter0 Overflow
-                TIMER_COUNTER0_OVERFLOW = 0x4,
-                ///  Timer/Counter1 Compare Match B
-                TIMER_COUNTER1_COMPARE_MATCH_B = 0x5,
-                ///  Timer/Counter1 Overflow
-                TIMER_COUNTER1_OVERFLOW = 0x6,
-                ///  Timer/Counter1 Capture Event
-                TIMER_COUNTER1_CAPTURE_EVENT = 0x7,
-            };
-
-            ///  ADC Data Register Bytes
-            ADC: u16,
-            ///  The ADC Control and Status register A
-            ADCSRA: mmio.Mmio(packed struct(u8) {
-                ///  ADC Prescaler Select Bits
-                ADPS: packed union {
-                    raw: u3,
-                    value: ANALOG_ADC_PRESCALER,
-                },
-                ///  ADC Interrupt Enable
-                ADIE: u1,
-                ///  ADC Interrupt Flag
-                ADIF: u1,
-                ///  ADC Auto Trigger Enable
-                ADATE: u1,
-                ///  ADC Start Conversion
-                ADSC: u1,
-                ///  ADC Enable
-                ADEN: u1,
-            }),
-            ///  The ADC Control and Status register B
-            ADCSRB: mmio.Mmio(packed struct(u8) {
-                ///  ADC Auto Trigger Source bits
-                ADTS: packed union {
-                    raw: u3,
-                    value: ANALOG_ADC_AUTO_TRIGGER,
-                },
-                reserved6: u3,
-                ACME: u1,
-                padding: u1,
-            }),
-            ///  The ADC multiplexer Selection Register
-            ADMUX: mmio.Mmio(packed struct(u8) {
-                ///  Analog Channel Selection Bits
-                MUX: packed union {
-                    raw: u4,
-                    value: ADC_MUX_SINGLE,
-                },
-                reserved5: u1,
-                ///  Left Adjust Result
-                ADLAR: u1,
-                ///  Reference Selection Bits
-                REFS: packed union {
-                    raw: u2,
-                    value: ANALOG_ADC_V_REF3,
-                },
-            }),
-            reserved6: [1]u8,
-            ///  Digital Input Disable Register
-            DIDR0: mmio.Mmio(packed struct(u8) {
-                ADC0D: u1,
-                ADC1D: u1,
-                ADC2D: u1,
-                ADC3D: u1,
-                ADC4D: u1,
-                ADC5D: u1,
-                padding: u2,
-            }),
-        };
-
-        ///  Analog Comparator
-        pub const AC = extern struct {
-            pub const ANALOG_COMP_INTERRUPT = enum(u2) {
-                ///  Interrupt on Toggle
-                INTERRUPT_ON_TOGGLE = 0x0,
-                ///  Reserved
-                RESERVED = 0x1,
-                ///  Interrupt on Falling Edge
-                INTERRUPT_ON_FALLING_EDGE = 0x2,
-                ///  Interrupt on Rising Edge
-                INTERRUPT_ON_RISING_EDGE = 0x3,
-            };
-
-            ///  Analog Comparator Control And Status Register
-            ACSR: mmio.Mmio(packed struct(u8) {
-                ///  Analog Comparator Interrupt Mode Select bits
-                ACIS: packed union {
-                    raw: u2,
-                    value: ANALOG_COMP_INTERRUPT,
-                },
-                ///  Analog Comparator Input Capture Enable
-                ACIC: u1,
-                ///  Analog Comparator Interrupt Enable
-                ACIE: u1,
-                ///  Analog Comparator Interrupt Flag
-                ACI: u1,
-                ///  Analog Compare Output
-                ACO: u1,
-                ///  Analog Comparator Bandgap Select
-                ACBG: u1,
-                ///  Analog Comparator Disable
-                ACD: u1,
-            }),
-            reserved47: [46]u8,
-            ///  Digital Input Disable Register 1
-            DIDR1: mmio.Mmio(packed struct(u8) {
-                ///  AIN0 Digital Input Disable
-                AIN0D: u1,
-                ///  AIN1 Digital Input Disable
-                AIN1D: u1,
-                padding: u6,
-            }),
-        };
-
-        ///  I/O Port
-        pub const PORT = struct {
-            ///  I/O Port
-            pub const PORTB = extern struct {
-                ///  Port B Input Pins
-                PINB: u8,
-                ///  Port B Data Direction Register
-                DDRB: u8,
-                ///  Port B Data Register
-                PORTB: u8,
-            };
-
-            ///  I/O Port
-            pub const PORTC = extern struct {
-                ///  Port C Input Pins
-                PINC: u8,
-                ///  Port C Data Direction Register
-                DDRC: u8,
-                ///  Port C Data Register
-                PORTC: u8,
-            };
-
-            ///  I/O Port
-            pub const PORTD = extern struct {
-                ///  Port D Input Pins
-                PIND: u8,
-                ///  Port D Data Direction Register
-                DDRD: u8,
-                ///  Port D Data Register
-                PORTD: u8,
-            };
-        };
-
-        ///  Timer/Counter, 8-bit
-        pub const TC8 = struct {
-            pub const CLK_SEL_3BIT_EXT = enum(u3) {
-                ///  No Clock Source (Stopped)
-                NO_CLOCK_SOURCE_STOPPED = 0x0,
-                ///  Running, No Prescaling
-                RUNNING_NO_PRESCALING = 0x1,
-                ///  Running, CLK/8
-                RUNNING_CLK_8 = 0x2,
-                ///  Running, CLK/64
-                RUNNING_CLK_64 = 0x3,
-                ///  Running, CLK/256
-                RUNNING_CLK_256 = 0x4,
-                ///  Running, CLK/1024
-                RUNNING_CLK_1024 = 0x5,
-                ///  Running, ExtClk Tn Falling Edge
-                RUNNING_EXTCLK_TN_FALLING_EDGE = 0x6,
-                ///  Running, ExtClk Tn Rising Edge
-                RUNNING_EXTCLK_TN_RISING_EDGE = 0x7,
-            };
-
-            ///  Timer/Counter, 8-bit
-            pub const TC0 = extern struct {
-                ///  Timer/Counter0 Interrupt Flag register
-                TIFR0: mmio.Mmio(packed struct(u8) {
-                    ///  Timer/Counter0 Overflow Flag
-                    TOV0: u1,
-                    ///  Timer/Counter0 Output Compare Flag 0A
-                    OCF0A: u1,
-                    ///  Timer/Counter0 Output Compare Flag 0B
-                    OCF0B: u1,
-                    padding: u5,
-                }),
-                reserved14: [13]u8,
-                ///  General Timer/Counter Control Register
-                GTCCR: mmio.Mmio(packed struct(u8) {
-                    ///  Prescaler Reset Timer/Counter1 and Timer/Counter0
-                    PSRSYNC: u1,
-                    reserved7: u6,
-                    ///  Timer/Counter Synchronization Mode
-                    TSM: u1,
-                }),
-                ///  Timer/Counter Control Register A
-                TCCR0A: mmio.Mmio(packed struct(u8) {
-                    ///  Waveform Generation Mode
-                    WGM0: u2,
-                    reserved4: u2,
-                    ///  Compare Output Mode, Fast PWm
-                    COM0B: u2,
-                    ///  Compare Output Mode, Phase Correct PWM Mode
-                    COM0A: u2,
-                }),
-                ///  Timer/Counter Control Register B
-                TCCR0B: mmio.Mmio(packed struct(u8) {
-                    ///  Clock Select
-                    CS0: packed union {
-                        raw: u3,
-                        value: CLK_SEL_3BIT_EXT,
-                    },
-                    WGM02: u1,
-                    reserved6: u2,
-                    ///  Force Output Compare B
-                    FOC0B: u1,
-                    ///  Force Output Compare A
-                    FOC0A: u1,
-                }),
-                ///  Timer/Counter0
-                TCNT0: u8,
-                ///  Timer/Counter0 Output Compare Register
-                OCR0A: u8,
-                ///  Timer/Counter0 Output Compare Register
-                OCR0B: u8,
-                reserved57: [37]u8,
-                ///  Timer/Counter0 Interrupt Mask Register
-                TIMSK0: mmio.Mmio(packed struct(u8) {
-                    ///  Timer/Counter0 Overflow Interrupt Enable
-                    TOIE0: u1,
-                    ///  Timer/Counter0 Output Compare Match A Interrupt Enable
-                    OCIE0A: u1,
-                    ///  Timer/Counter0 Output Compare Match B Interrupt Enable
-                    OCIE0B: u1,
-                    padding: u5,
-                }),
-            };
-        };
-
-        ///  External Interrupts
-        pub const EXINT = extern struct {
-            ///  Interrupt Sense Control
-            pub const INTERRUPT_SENSE_CONTROL = enum(u2) {
-                ///  Low Level of INTX
-                LOW_LEVEL_OF_INTX = 0x0,
-                ///  Any Logical Change of INTX
-                ANY_LOGICAL_CHANGE_OF_INTX = 0x1,
-                ///  Falling Edge of INTX
-                FALLING_EDGE_OF_INTX = 0x2,
-                ///  Rising Edge of INTX
-                RISING_EDGE_OF_INTX = 0x3,
-            };
-
-            ///  Pin Change Interrupt Flag Register
-            PCIFR: mmio.Mmio(packed struct(u8) {
-                ///  Pin Change Interrupt Flags
-                PCIF: u3,
-                padding: u5,
-            }),
-            ///  External Interrupt Flag Register
-            EIFR: mmio.Mmio(packed struct(u8) {
-                ///  External Interrupt Flags
-                INTF: u2,
-                padding: u6,
-            }),
-            ///  External Interrupt Mask Register
-            EIMSK: mmio.Mmio(packed struct(u8) {
-                ///  External Interrupt Request 1 Enable
-                INT: u2,
-                padding: u6,
-            }),
-            reserved45: [42]u8,
-            ///  Pin Change Interrupt Control Register
-            PCICR: mmio.Mmio(packed struct(u8) {
-                ///  Pin Change Interrupt Enables
-                PCIE: u3,
-                padding: u5,
-            }),
-            ///  External Interrupt Control Register
-            EICRA: mmio.Mmio(packed struct(u8) {
-                ///  External Interrupt Sense Control 0 Bits
-                ISC0: packed union {
-                    raw: u2,
-                    value: INTERRUPT_SENSE_CONTROL,
-                },
-                ///  External Interrupt Sense Control 1 Bits
-                ISC1: packed union {
-                    raw: u2,
-                    value: INTERRUPT_SENSE_CONTROL,
-                },
-                padding: u4,
-            }),
-            reserved48: [1]u8,
-            ///  Pin Change Mask Register 0
-            PCMSK0: mmio.Mmio(packed struct(u8) {
-                ///  Pin Change Enable Masks
-                PCINT: u8,
-            }),
-            ///  Pin Change Mask Register 1
-            PCMSK1: mmio.Mmio(packed struct(u8) {
-                ///  Pin Change Enable Masks
-                PCINT: u7,
-                padding: u1,
-            }),
-            ///  Pin Change Mask Register 2
-            PCMSK2: mmio.Mmio(packed struct(u8) {
-                ///  Pin Change Enable Masks
-                PCINT: u8,
-            }),
-        };
-
-        ///  Serial Peripheral Interface
-        pub const SPI = extern struct {
-            pub const COMM_SCK_RATE_3BIT = enum(u2) {
-                ///  fosc/2 or fosc/4
-                FOSC_2_OR_FOSC_4 = 0x0,
-                ///  fosc/8 or fosc/16
-                FOSC_8_OR_FOSC_16 = 0x1,
-                ///  fosc/32 or fosc/64
-                FOSC_32_OR_FOSC_64 = 0x2,
-                ///  fosc/64 or fosc/128
-                FOSC_64_OR_FOSC_128 = 0x3,
-            };
-
-            ///  SPI Control Register
-            SPCR: mmio.Mmio(packed struct(u8) {
-                ///  SPI Clock Rate Selects
-                SPR: packed union {
-                    raw: u2,
-                    value: COMM_SCK_RATE_3BIT,
-                },
-                ///  Clock Phase
-                CPHA: u1,
-                ///  Clock polarity
-                CPOL: u1,
-                ///  Master/Slave Select
-                MSTR: u1,
-                ///  Data Order
-                DORD: u1,
-                ///  SPI Enable
-                SPE: u1,
-                ///  SPI Interrupt Enable
-                SPIE: u1,
-            }),
-            ///  SPI Status Register
-            SPSR: mmio.Mmio(packed struct(u8) {
-                ///  Double SPI Speed Bit
-                SPI2X: u1,
-                reserved6: u5,
-                ///  Write Collision Flag
-                WCOL: u1,
-                ///  SPI Interrupt Flag
-                SPIF: u1,
-            }),
-            ///  SPI Data Register
-            SPDR: u8,
-        };
-
-        ///  Watchdog Timer
-        pub const WDT = extern struct {
-            pub const WDOG_TIMER_PRESCALE_4BITS = enum(u4) {
-                ///  Oscillator Cycles 2K
-                OSCILLATOR_CYCLES_2K = 0x0,
-                ///  Oscillator Cycles 4K
-                OSCILLATOR_CYCLES_4K = 0x1,
-                ///  Oscillator Cycles 8K
-                OSCILLATOR_CYCLES_8K = 0x2,
-                ///  Oscillator Cycles 16K
-                OSCILLATOR_CYCLES_16K = 0x3,
-                ///  Oscillator Cycles 32K
-                OSCILLATOR_CYCLES_32K = 0x4,
-                ///  Oscillator Cycles 64K
-                OSCILLATOR_CYCLES_64K = 0x5,
-                ///  Oscillator Cycles 128K
-                OSCILLATOR_CYCLES_128K = 0x6,
-                ///  Oscillator Cycles 256K
-                OSCILLATOR_CYCLES_256K = 0x7,
-                ///  Oscillator Cycles 512K
-                OSCILLATOR_CYCLES_512K = 0x8,
-                ///  Oscillator Cycles 1024K
-                OSCILLATOR_CYCLES_1024K = 0x9,
-                _,
-            };
-
-            ///  Watchdog Timer Control Register
-            WDTCSR: mmio.Mmio(packed struct(u8) {
-                ///  Watchdog Timer Prescaler Bits
-                WDP_bit0: u1,
-                ///  Watchdog Timer Prescaler Bits
-                WDP_bit1: u1,
-                ///  Watchdog Timer Prescaler Bits
-                WDP_bit2: u1,
-                ///  Watch Dog Enable
-                WDE: u1,
-                ///  Watchdog Change Enable
-                WDCE: u1,
-                ///  Watchdog Timer Prescaler Bits
-                WDP_bit3: u1,
-                ///  Watchdog Timeout Interrupt Enable
-                WDIE: u1,
-                ///  Watchdog Timeout Interrupt Flag
-                WDIF: u1,
-            }),
-        };
-
-        ///  CPU Registers
-        pub const CPU = extern struct {
-            pub const CPU_CLK_PRESCALE_4_BITS_SMALL = enum(u4) {
-                ///  1
-                @"1" = 0x0,
-                ///  2
-                @"2" = 0x1,
-                ///  4
-                @"4" = 0x2,
-                ///  8
-                @"8" = 0x3,
-                ///  16
-                @"16" = 0x4,
-                ///  32
-                @"32" = 0x5,
-                ///  64
-                @"64" = 0x6,
-                ///  128
-                @"128" = 0x7,
-                ///  256
-                @"256" = 0x8,
-                _,
-            };
-
-            pub const CPU_SLEEP_MODE_3BITS2 = enum(u3) {
-                ///  Idle
-                IDLE = 0x0,
-                ///  ADC Noise Reduction (If Available)
-                ADC = 0x1,
-                ///  Power Down
-                PDOWN = 0x2,
-                ///  Power Save
-                PSAVE = 0x3,
-                ///  Reserved
-                VAL_0x04 = 0x4,
-                ///  Reserved
-                VAL_0x05 = 0x5,
-                ///  Standby
-                STDBY = 0x6,
-                ///  Extended Standby
-                ESTDBY = 0x7,
-            };
-
-            ///  Oscillator Calibration Values
-            pub const OSCCAL_VALUE_ADDRESSES = enum(u1) {
-                ///  8.0 MHz
-                @"8_0_MHz" = 0x0,
-                _,
-            };
-
-            ///  General Purpose I/O Register 0
-            GPIOR0: u8,
-            reserved12: [11]u8,
-            ///  General Purpose I/O Register 1
-            GPIOR1: u8,
-            ///  General Purpose I/O Register 2
-            GPIOR2: u8,
-            reserved21: [7]u8,
-            ///  Sleep Mode Control Register
-            SMCR: mmio.Mmio(packed struct(u8) {
-                ///  Sleep Enable
-                SE: u1,
-                ///  Sleep Mode Select Bits
-                SM: packed union {
-                    raw: u3,
-                    value: CPU_SLEEP_MODE_3BITS2,
-                },
-                padding: u4,
-            }),
-            ///  MCU Status Register
-            MCUSR: mmio.Mmio(packed struct(u8) {
-                ///  Power-on reset flag
-                PORF: u1,
-                ///  External Reset Flag
-                EXTRF: u1,
-                ///  Brown-out Reset Flag
-                BORF: u1,
-                ///  Watchdog Reset Flag
-                WDRF: u1,
-                padding: u4,
-            }),
-            ///  MCU Control Register
-            MCUCR: mmio.Mmio(packed struct(u8) {
-                IVCE: u1,
-                IVSEL: u1,
-                reserved4: u2,
-                PUD: u1,
-                ///  BOD Sleep Enable
-                BODSE: u1,
-                ///  BOD Sleep
-                BODS: u1,
-                padding: u1,
-            }),
-            reserved25: [1]u8,
-            ///  Store Program Memory Control and Status Register
-            SPMCSR: mmio.Mmio(packed struct(u8) {
-                ///  Store Program Memory
-                SPMEN: u1,
-                ///  Page Erase
-                PGERS: u1,
-                ///  Page Write
-                PGWRT: u1,
-                ///  Boot Lock Bit Set
-                BLBSET: u1,
-                ///  Read-While-Write section read enable
-                RWWSRE: u1,
-                ///  Signature Row Read
-                SIGRD: u1,
-                ///  Read-While-Write Section Busy
-                RWWSB: u1,
-                ///  SPM Interrupt Enable
-                SPMIE: u1,
-            }),
-            reserved31: [5]u8,
-            ///  Stack Pointer
-            SP: u16,
-            ///  Status Register
-            SREG: mmio.Mmio(packed struct(u8) {
-                ///  Carry Flag
-                C: u1,
-                ///  Zero Flag
-                Z: u1,
-                ///  Negative Flag
-                N: u1,
-                ///  Two's Complement Overflow Flag
-                V: u1,
-                ///  Sign Bit
-                S: u1,
-                ///  Half Carry Flag
-                H: u1,
-                ///  Bit Copy Storage
-                T: u1,
-                ///  Global Interrupt Enable
-                I: u1,
-            }),
-            reserved35: [1]u8,
-            ///  Clock Prescale Register
-            CLKPR: mmio.Mmio(packed struct(u8) {
-                ///  Clock Prescaler Select Bits
-                CLKPS: packed union {
-                    raw: u4,
-                    value: CPU_CLK_PRESCALE_4_BITS_SMALL,
-                },
-                reserved7: u3,
-                ///  Clock Prescaler Change Enable
-                CLKPCE: u1,
-            }),
-            reserved38: [2]u8,
-            ///  Power Reduction Register
-            PRR: mmio.Mmio(packed struct(u8) {
-                ///  Power Reduction ADC
-                PRADC: u1,
-                ///  Power Reduction USART
-                PRUSART0: u1,
-                ///  Power Reduction Serial Peripheral Interface
-                PRSPI: u1,
-                ///  Power Reduction Timer/Counter1
-                PRTIM1: u1,
-                reserved5: u1,
-                ///  Power Reduction Timer/Counter0
-                PRTIM0: u1,
-                ///  Power Reduction Timer/Counter2
-                PRTIM2: u1,
-                ///  Power Reduction TWI
-                PRTWI: u1,
-            }),
-            reserved40: [1]u8,
-            ///  Oscillator Calibration Value
-            OSCCAL: mmio.Mmio(packed struct(u8) {
-                ///  Oscillator Calibration
-                OSCCAL: u8,
-            }),
-        };
-
-        ///  EEPROM
-        pub const EEPROM = extern struct {
-            pub const EEP_MODE = enum(u2) {
-                ///  Erase and Write in one operation
-                ERASE_AND_WRITE_IN_ONE_OPERATION = 0x0,
-                ///  Erase Only
-                ERASE_ONLY = 0x1,
-                ///  Write Only
-                WRITE_ONLY = 0x2,
-                _,
-            };
-
-            ///  EEPROM Control Register
-            EECR: mmio.Mmio(packed struct(u8) {
-                ///  EEPROM Read Enable
-                EERE: u1,
-                ///  EEPROM Write Enable
-                EEPE: u1,
-                ///  EEPROM Master Write Enable
-                EEMPE: u1,
-                ///  EEPROM Ready Interrupt Enable
-                EERIE: u1,
-                ///  EEPROM Programming Mode Bits
-                EEPM: packed union {
-                    raw: u2,
-                    value: EEP_MODE,
-                },
-                padding: u2,
-            }),
-            ///  EEPROM Data Register
-            EEDR: u8,
-            ///  EEPROM Address Register Bytes
-            EEAR: u16,
-        };
-    };
-};

From d9cbc3654e2925dfdf2ccf4cd8179728dbc2d0bb Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Fri, 22 Sep 2023 09:02:51 +0200
Subject: [PATCH 206/286] Microzig Generation 2 Build Interface  (#82)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* Starts to rework build framework.
* First building version.
* Documents paths to supported devices.
* Tiny fix for MicroZig.
* Drops CI

---------

Co-authored-by: Felix "xq" Queißner 
---
 .buildkite/pipeline.yml     |     5 -
 .github/workflows/build.yml |    22 -
 README.adoc                 |    12 +-
 build.zig                   |   382 +-
 build.zig.zon               |     8 +-
 src/boards.zig              |    69 -
 src/bootroms/w25q32jvssiq.S |    42 +
 src/chips.zig               |    25 -
 src/chips/RP2040.zig        | 18145 ----------------------------------
 9 files changed, 288 insertions(+), 18422 deletions(-)
 delete mode 100644 .buildkite/pipeline.yml
 delete mode 100644 .github/workflows/build.yml
 delete mode 100644 src/boards.zig
 create mode 100644 src/bootroms/w25q32jvssiq.S
 delete mode 100644 src/chips.zig
 delete mode 100644 src/chips/RP2040.zig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
deleted file mode 100644
index 4e00ec296..000000000
--- a/.buildkite/pipeline.yml
+++ /dev/null
@@ -1,5 +0,0 @@
-steps:
-  - name: Build Examples
-    command: zig build
-  - name: Test
-    command: zig build test
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
deleted file mode 100644
index 50ac1a489..000000000
--- a/.github/workflows/build.yml
+++ /dev/null
@@ -1,22 +0,0 @@
-name: Build
-on:
-  push:
-
-jobs:
-  build:
-    runs-on: ${{ matrix.os }}
-    strategy:
-      matrix:
-        os: [
-          ubuntu-latest,
-          windows-latest,
-          macos-latest,
-        ]
-    steps:
-    - uses: actions/checkout@v2
-    - uses: goto-bus-stop/setup-zig@v1.3.0
-      with:
-        version: 0.11.0
-
-    - name: Build and Unit Test
-      run: zig build test -Doptimize=ReleaseSmall
diff --git a/README.adoc b/README.adoc
index c31cb3dd8..8b6358dae 100644
--- a/README.adoc
+++ b/README.adoc
@@ -8,8 +8,10 @@ HAL and register definitions for the RP2040.
 
 == Supported devices ==
 
-- Raspberry Pi Pico
-- (*experimental*) Waveshare RP2040-Plus (4M Flash)
-- (*experimental*) Waveshare RP2040-Plus (16M Flash)
-- (*experimental*) Waveshare RP2040-ETH Mini
-- (*experimental*) Waveshare RP2040-Matrix
+- Raspberry Pi RP2040 (`chips.rp2040`)
+- Raspberry Pi Pico (`boards.raspberry_pi.pico`)
+- (*experimental*) Waveshare RP2040-Plus (4M Flash) (`boards.waveshare.rp2040_plus_4m`)
+- (*experimental*) Waveshare RP2040-Plus (16M Flash) (`boards.waveshare.rp2040_plus_16m`)
+- (*experimental*) Waveshare RP2040-ETH Mini (`boards.waveshare.rp2040_eth`)
+- (*experimental*) Waveshare RP2040-Matrix (`boards.waveshare.rp2040_matrix`)
+
diff --git a/build.zig b/build.zig
index 1d4dd3c58..cb3c13fcf 100644
--- a/build.zig
+++ b/build.zig
@@ -1,15 +1,101 @@
 const std = @import("std");
-const Build = std.Build;
-const comptimePrint = std.fmt.comptimePrint;
+const microzig = @import("root").dependencies.imports.microzig; // HACK: Please import MicroZig always under the name `microzig`. Otherwise the RP2040 module will fail to be properly imported.
 
-const microzig = @import("microzig");
+fn root() []const u8 {
+    return comptime (std.fs.path.dirname(@src().file) orelse ".");
+}
+const build_root = root();
 
-pub const chips = @import("src/chips.zig");
-pub const boards = @import("src/boards.zig");
+////////////////////////////////////////
+//      MicroZig Gen 2 Interface      //
+////////////////////////////////////////
 
-const build_root = root();
+pub fn build(b: *std.Build) !void {
+    //  Dummy func to make package manager happy
+    _ = b;
+}
+
+pub const chips = struct {
+    // Note: This chip has no flash support defined and requires additional configuration!
+    pub const rp2040 = .{
+        .preferred_format = .{ .uf2 = .RP2040 },
+        .chip = chip,
+        .hal = hal,
+        .board = null,
+        .linker_script = linker_script,
+    };
+};
+
+pub const boards = struct {
+    pub const raspberry_pi = struct {
+        pub const pico = .{
+            .preferred_format = .{ .uf2 = .RP2040 },
+            .chip = chip,
+            .hal = hal,
+            .linker_script = linker_script,
+            .board = .{
+                .name = "RaspberryPi Pico",
+                .source_file = .{ .cwd_relative = build_root ++ "/src/boards/raspberry_pi_pico.zig" },
+                .url = "https://www.raspberrypi.com/products/raspberry-pi-pico/",
+            },
+            .configure = rp2040_configure(.w25q080),
+        };
+    };
 
-const linkerscript_path = build_root ++ "/rp2040.ld";
+    pub const waveshare = struct {
+        pub const rp2040_plus_4m = .{
+            .preferred_format = .{ .uf2 = .RP2040 },
+            .chip = chip,
+            .hal = hal,
+            .linker_script = linker_script,
+            .board = .{
+                .name = "Waveshare RP2040-Plus (4M Flash)",
+                .source_file = .{ .cwd_relative = build_root ++ "/src/boards/waveshare_rp2040_plus_4m.zig" },
+                .url = "https://www.waveshare.com/rp2040-plus.htm",
+            },
+            .configure = rp2040_configure(.w25q080),
+        };
+
+        pub const rp2040_plus_16m = .{
+            .preferred_format = .{ .uf2 = .RP2040 },
+            .chip = chip,
+            .hal = hal,
+            .linker_script = linker_script,
+            .board = .{
+                .name = "Waveshare RP2040-Plus (16M Flash)",
+                .source_file = .{ .cwd_relative = build_root ++ "/src/boards/waveshare_rp2040_plus_16m.zig" },
+                .url = "https://www.waveshare.com/rp2040-plus.htm",
+            },
+            .configure = rp2040_configure(.w25q080),
+        };
+
+        pub const rp2040_eth = .{
+            .preferred_format = .{ .uf2 = .RP2040 },
+            .chip = chip,
+            .hal = hal,
+            .linker_script = linker_script,
+            .board = .{
+                .name = "Waveshare RP2040-ETH Mini",
+                .source_file = .{ .cwd_relative = build_root ++ "/src/boards/waveshare_rp2040_eth.zig" },
+                .url = "https://www.waveshare.com/rp2040-eth.htm",
+            },
+            .configure = rp2040_configure(.w25q080),
+        };
+
+        pub const rp2040_matrix = .{
+            .preferred_format = .{ .uf2 = .RP2040 },
+            .chip = chip,
+            .hal = hal,
+            .linker_script = linker_script,
+            .board = .{
+                .name = "Waveshare RP2040-Matrix",
+                .source_file = .{ .cwd_relative = build_root ++ "/src/boards/waveshare_rp2040_matrix.zig" },
+                .url = "https://www.waveshare.com/rp2040-matrix.htm",
+            },
+            .configure = rp2040_configure(.w25q080),
+        };
+    };
+};
 
 pub const BootROM = union(enum) {
     artifact: *std.build.CompileStep, // provide a custom startup code
@@ -26,24 +112,54 @@ pub const BootROM = union(enum) {
     legacy,
 };
 
-pub const PicoExecutableOptions = struct {
-    name: []const u8,
-    source_file: std.Build.LazyPath,
-    optimize: std.builtin.OptimizeMode = .Debug,
+const linker_script = .{
+    .source_file = .{ .cwd_relative = build_root ++ "/rp2040.ld" },
+};
 
-    board: boards.Board = boards.raspberry_pi_pico,
+const hal = .{
+    .source_file = .{ .cwd_relative = build_root ++ "/src/hal.zig" },
+};
 
-    bootrom: ?BootROM = null,
+const chip = .{
+    .name = "RP2040",
+    .url = "https://www.raspberrypi.com/products/rp2040/",
+    .cpu = .cortex_m0plus,
+    .register_definition = .{
+        .json = .{ .cwd_relative = build_root ++ "/src/chips/RP2040.json" },
+    },
+    .memory_regions = &.{
+        .{ .kind = .flash, .offset = 0x10000100, .length = (2048 * 1024) - 256 },
+        .{ .kind = .flash, .offset = 0x10000000, .length = 256 },
+        .{ .kind = .ram, .offset = 0x20000000, .length = 256 * 1024 },
+    },
 };
 
-pub const addPiPicoExecutable = addExecutable; // Deprecated, use addExecutable!
+/// Returns a configuration function that will add the provided `BootROM` to the firmware.
+pub fn rp2040_configure(comptime bootrom: BootROM) *const fn (host_build: *std.Build, *microzig.Firmware) void {
+    const T = struct {
+        fn configure(host_build: *std.Build, fw: *microzig.Firmware) void {
+            const bootrom_file = getBootrom(host_build, bootrom);
+
+            // HACK: Inject the file as a dependency to MicroZig.board
+            fw.modules.board.?.dependencies.put(
+                "bootloader",
+                host_build.createModule(.{
+                    .source_file = bootrom_file.bin,
+                }),
+            ) catch @panic("oom");
+            bootrom_file.bin.addStepDependencies(&fw.artifact.step);
+        }
+    };
+
+    return T.configure;
+}
 
 pub const Stage2Bootloader = struct {
     bin: std.Build.LazyPath,
     elf: ?std.Build.LazyPath,
 };
 
-pub fn getBootrom(b: *Build, rom: BootROM) Stage2Bootloader {
+pub fn getBootrom(b: *std.Build, rom: BootROM) Stage2Bootloader {
     const rom_exe = switch (rom) {
         .artifact => |artifact| artifact,
         .blob => |blob| return Stage2Bootloader{
@@ -52,7 +168,7 @@ pub fn getBootrom(b: *Build, rom: BootROM) Stage2Bootloader {
         },
 
         else => blk: {
-            var target = chips.rp2040.cpu.target;
+            var target = @as(microzig.CpuModel, chip.cpu).getDescriptor().target;
             target.abi = .eabi;
 
             const rom_path = b.pathFromRoot(b.fmt("{s}/src/bootroms/{s}.S", .{ build_root, @tagName(rom) }));
@@ -84,134 +200,106 @@ pub fn getBootrom(b: *Build, rom: BootROM) Stage2Bootloader {
     };
 }
 
-pub fn addExecutable(
-    b: *Build,
-    opts: PicoExecutableOptions,
-) *microzig.EmbeddedExecutable {
-    var exe = microzig.addEmbeddedExecutable(b, .{
-        .name = opts.name,
-        .source_file = opts.source_file,
-        .backing = .{ .board = opts.board.inner },
-        .optimize = opts.optimize,
-        .linkerscript_source_file = .{ .path = linkerscript_path },
-    });
-
-    const i: *std.Build.CompileStep = exe.inner;
-
-    const bootrom_file = getBootrom(b, opts.bootrom orelse opts.board.bootrom);
-
-    // HACK: Inject the file as a dependency to MicroZig.board
-    i.modules.get("microzig").?.dependencies.get("board").?.dependencies.put(
-        "bootloader",
-        b.createModule(.{
-            .source_file = bootrom_file.bin,
-        }),
-    ) catch @panic("oom");
-    bootrom_file.bin.addStepDependencies(&i.step);
-
-    return exe;
-}
-
-// this build script is mostly for testing and verification of this
-// package. In an attempt to modularize -- designing for a case where a
-// project requires multiple HALs, it accepts microzig as a param
-pub fn build(b: *Build) !void {
-    const optimize = b.standardOptimizeOption(.{});
-
-    const args_dep = b.dependency("args", .{});
-    const args_mod = args_dep.module("args");
-
-    var examples = Examples.init(b, optimize);
-    examples.install(b);
-
-    const pio_tests = b.addTest(.{
-        .root_source_file = .{
-            .path = "src/hal.zig",
-        },
-        .optimize = optimize,
-    });
-    pio_tests.addIncludePath(.{ .path = "src/hal/pio/assembler" });
-
-    const test_step = b.step("test", "run unit tests");
-    test_step.dependOn(&b.addRunArtifact(pio_tests).step);
-
-    {
-        const flash_tool = b.addExecutable(.{
-            .name = "rp2040-flash",
-            .optimize = .Debug,
-            .target = .{},
-            .root_source_file = .{ .path = "tools/rp2040-flash.zig" },
-        });
-        flash_tool.addModule("args", args_mod);
-
-        b.installArtifact(flash_tool);
-    }
-
-    // Install all bootroms for debugging and CI
-    inline for (comptime std.enums.values(std.meta.Tag(BootROM))) |rom| {
-        if (rom == .artifact or rom == .blob) {
-            continue;
-        }
-
-        if (rom == .is25lp080) {
-            // TODO: https://github.com/ZigEmbeddedGroup/raspberrypi-rp2040/issues/79
-            //  is25lp080.o:(text+0x16): has non-ABS relocation R_ARM_THM_CALL against symbol 'read_flash_sreg'
-            continue;
-        }
-
-        const files = getBootrom(b, rom);
-        if (files.elf) |elf| {
-            b.getInstallStep().dependOn(
-                &b.addInstallFileWithDir(elf, .{ .custom = "stage2" }, b.fmt("{s}.elf", .{@tagName(rom)})).step,
-            );
-        }
-        b.getInstallStep().dependOn(
-            &b.addInstallFileWithDir(files.bin, .{ .custom = "stage2" }, b.fmt("{s}.bin", .{@tagName(rom)})).step,
-        );
-    }
-}
-
-fn root() []const u8 {
-    return comptime (std.fs.path.dirname(@src().file) orelse ".") ++ "/";
-}
-
-pub const Examples = struct {
-    adc: *microzig.EmbeddedExecutable,
-    blinky: *microzig.EmbeddedExecutable,
-    blinky_core1: *microzig.EmbeddedExecutable,
-    gpio_clk: *microzig.EmbeddedExecutable,
-    i2c_bus_scan: *microzig.EmbeddedExecutable,
-    pwm: *microzig.EmbeddedExecutable,
-    spi_master: *microzig.EmbeddedExecutable,
-    uart: *microzig.EmbeddedExecutable,
-    squarewave: *microzig.EmbeddedExecutable,
-    //uart_pins: microzig.EmbeddedExecutable,
-    flash_program: *microzig.EmbeddedExecutable,
-    usb_device: *microzig.EmbeddedExecutable,
-    usb_hid: *microzig.EmbeddedExecutable,
-    ws2812: *microzig.EmbeddedExecutable,
-    random: *microzig.EmbeddedExecutable,
-
-    pub fn init(b: *Build, optimize: std.builtin.OptimizeMode) Examples {
-        var ret: Examples = undefined;
-        inline for (@typeInfo(Examples).Struct.fields) |field| {
-            const path = comptime root() ++ "examples/" ++ field.name ++ ".zig";
-
-            @field(ret, field.name) = addExecutable(b, .{
-                .name = field.name,
-                .source_file = .{ .path = path },
-                .optimize = optimize,
-            });
-        }
-
-        return ret;
-    }
-
-    pub fn install(examples: *Examples, b: *Build) void {
-        inline for (@typeInfo(Examples).Struct.fields) |field| {
-            b.getInstallStep().dependOn(
-                &b.addInstallFileWithDir(@field(examples, field.name).inner.getEmittedBin(), .{ .custom = "firmware" }, field.name ++ ".elf").step,
-            );
-        }
-    }
-};
+/////////////////////////////////////////
+//      MicroZig Legacy Interface      //
+/////////////////////////////////////////
+
+// // this build script is mostly for testing and verification of this
+// // package. In an attempt to modularize -- designing for a case where a
+// // project requires multiple HALs, it accepts microzig as a param
+// pub fn build(b: *Build) !void {
+//     const optimize = b.standardOptimizeOption(.{});
+
+//     const args_dep = b.dependency("args", .{});
+//     const args_mod = args_dep.module("args");
+
+//     var examples = Examples.init(b, optimize);
+//     examples.install(b);
+
+//     const pio_tests = b.addTest(.{
+//         .root_source_file = .{
+//             .path = "src/hal.zig",
+//         },
+//         .optimize = optimize,
+//     });
+//     pio_tests.addIncludePath(.{ .path = "src/hal/pio/assembler" });
+
+//     const test_step = b.step("test", "run unit tests");
+//     test_step.dependOn(&b.addRunArtifact(pio_tests).step);
+
+//     {
+//         const flash_tool = b.addExecutable(.{
+//             .name = "rp2040-flash",
+//             .optimize = .Debug,
+//             .target = .{},
+//             .root_source_file = .{ .path = "tools/rp2040-flash.zig" },
+//         });
+//         flash_tool.addModule("args", args_mod);
+
+//         b.installArtifact(flash_tool);
+//     }
+
+//     // Install all bootroms for debugging and CI
+//     inline for (comptime std.enums.values(std.meta.Tag(BootROM))) |rom| {
+//         if (rom == .artifact or rom == .blob) {
+//             continue;
+//         }
+
+//         if (rom == .is25lp080) {
+//             // TODO: https://github.com/ZigEmbeddedGroup/raspberrypi-rp2040/issues/79
+//             //  is25lp080.o:(text+0x16): has non-ABS relocation R_ARM_THM_CALL against symbol 'read_flash_sreg'
+//             continue;
+//         }
+
+//         const files = getBootrom(b, rom);
+//         if (files.elf) |elf| {
+//             b.getInstallStep().dependOn(
+//                 &b.addInstallFileWithDir(elf, .{ .custom = "stage2" }, b.fmt("{s}.elf", .{@tagName(rom)})).step,
+//             );
+//         }
+//         b.getInstallStep().dependOn(
+//             &b.addInstallFileWithDir(files.bin, .{ .custom = "stage2" }, b.fmt("{s}.bin", .{@tagName(rom)})).step,
+//         );
+//     }
+// }
+
+// pub const Examples = struct {
+//     adc: *microzig.EmbeddedExecutable,
+//     blinky: *microzig.EmbeddedExecutable,
+//     blinky_core1: *microzig.EmbeddedExecutable,
+//     gpio_clk: *microzig.EmbeddedExecutable,
+//     i2c_bus_scan: *microzig.EmbeddedExecutable,
+//     pwm: *microzig.EmbeddedExecutable,
+//     spi_master: *microzig.EmbeddedExecutable,
+//     uart: *microzig.EmbeddedExecutable,
+//     squarewave: *microzig.EmbeddedExecutable,
+//     //uart_pins: microzig.EmbeddedExecutable,
+//     flash_program: *microzig.EmbeddedExecutable,
+//     usb_device: *microzig.EmbeddedExecutable,
+//     usb_hid: *microzig.EmbeddedExecutable,
+//     ws2812: *microzig.EmbeddedExecutable,
+//     random: *microzig.EmbeddedExecutable,
+
+//     pub fn init(b: *Build, optimize: std.builtin.OptimizeMode) Examples {
+//         var ret: Examples = undefined;
+//         inline for (@typeInfo(Examples).Struct.fields) |field| {
+//             const path = comptime root() ++ "examples/" ++ field.name ++ ".zig";
+
+//             @field(ret, field.name) = addExecutable(b, .{
+//                 .name = field.name,
+//                 .source_file = .{ .path = path },
+//                 .optimize = optimize,
+//             });
+//         }
+
+//         return ret;
+//     }
+
+//     pub fn install(examples: *Examples, b: *Build) void {
+//         inline for (@typeInfo(Examples).Struct.fields) |field| {
+//             b.getInstallStep().dependOn(
+//                 &b.addInstallFileWithDir(@field(examples, field.name).inner.getEmittedBin(), .{ .custom = "firmware" }, field.name ++ ".elf").step,
+//             );
+//         }
+//     }
+// };
diff --git a/build.zig.zon b/build.zig.zon
index cfb4ad4ce..9fb27651e 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -2,10 +2,10 @@
     .name = "rp2040",
     .version = "0.0.0",
     .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
-            .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
-        },
+        // .microzig = .{
+        //     .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
+        //     .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
+        // },
         .args = .{
             .url = "https://github.com/MasterQ32/zig-args/archive/91d1e89fb89a4d01dec7c9aec95b0a324080ebcc.tar.gz",
             .hash = "12203d04cafc97f952d74cdb077e74c0ab3414f9f6b5fbd159112c62bfa584a0dbed",
diff --git a/src/boards.zig b/src/boards.zig
deleted file mode 100644
index 8f68040ea..000000000
--- a/src/boards.zig
+++ /dev/null
@@ -1,69 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-const rp2040 = @import("../build.zig");
-const chips = @import("chips.zig");
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse ".";
-}
-
-fn board_path(comptime path: []const u8) std.Build.LazyPath {
-    return .{
-        .path = std.fmt.comptimePrint("{s}/boards/{s}", .{ root_dir(), path }),
-    };
-}
-
-pub const Board = struct {
-    inner: microzig.Board,
-    bootrom: rp2040.BootROM,
-};
-
-// https://www.raspberrypi.com/products/raspberry-pi-pico/
-pub const raspberry_pi_pico = Board{
-    .inner = .{
-        .name = "Raspberry Pi Pico",
-        .source = board_path("raspberry_pi_pico.zig"),
-        .chip = chips.rp2040,
-    },
-    .bootrom = .w25q080,
-};
-
-// https://www.waveshare.com/rp2040-plus.htm
-pub const waveshare_rp2040_plus_4m = Board{
-    .inner = .{
-        .name = "Waveshare RP2040-Plus (4M Flash)",
-        .source = board_path("waveshare_rp2040_plus_4m.zig"),
-        .chip = chips.rp2040,
-    },
-    .bootrom = .w25q080,
-};
-
-// https://www.waveshare.com/rp2040-plus.htm
-pub const waveshare_rp2040_plus_16m = Board{
-    .inner = .{
-        .name = "Waveshare RP2040-Plus (16M Flash)",
-        .source = board_path("waveshare_rp2040_plus_16m.zig"),
-        .chip = chips.rp2040,
-    },
-    .bootrom = .w25q080,
-};
-
-// https://www.waveshare.com/rp2040-eth.htm
-pub const waveshare_rp2040_eth = Board{
-    .inner = .{
-        .name = "Waveshare RP2040-ETH Mini",
-        .source = board_path("waveshare_rp2040_eth.zig"),
-        .chip = chips.rp2040,
-    },
-    .bootrom = .w25q080,
-};
-
-// https://www.waveshare.com/rp2040-matrix.htm
-pub const waveshare_rp2040_matrix = Board{
-    .inner = .{
-        .name = "Waveshare RP2040-Matrix",
-        .source = board_path("waveshare_rp2040_matrix.zig"),
-        .chip = chips.rp2040,
-    },
-    .bootrom = .w25q080,
-};
diff --git a/src/bootroms/w25q32jvssiq.S b/src/bootroms/w25q32jvssiq.S
new file mode 100644
index 000000000..a122d72dd
--- /dev/null
+++ b/src/bootroms/w25q32jvssiq.S
@@ -0,0 +1,42 @@
+
+// This blob was read from the original RP2040-ETH board
+// and is assumed to be working with the W25Q32JVSSIQ flash.
+
+.text
+.global _stage2_boot
+_stage2_boot:
+
+// 00000000  00 b5 32 4b 21 20 58 60  98 68 02 21 88 43 98 60  |..2K! X`.h.!.C.`|
+// 00000010  d8 60 18 61 58 61 2e 4b  00 21 99 60 02 21 59 61  |.`.aXa.K.!.`.!Ya|
+// 00000020  01 21 f0 22 99 50 2b 49  19 60 01 21 99 60 35 20  |.!.".P+I.`.!.`5 |
+// 00000030  00 f0 44 f8 02 22 90 42  14 d0 06 21 19 66 00 f0  |..D..".B...!.f..|
+// 00000040  34 f8 19 6e 01 21 19 66  00 20 18 66 1a 66 00 f0  |4..n.!.f. .f.f..|
+// 00000050  2c f8 19 6e 19 6e 19 6e  05 20 00 f0 2f f8 01 21  |,..n.n.n. ../..!|
+// 00000060  08 42 f9 d1 00 21 99 60  1b 49 19 60 00 21 59 60  |.B...!.`.I.`.!Y`|
+// 00000070  1a 49 1b 48 01 60 01 21  99 60 eb 21 19 66 a0 21  |.I.H.`.!.`.!.f.!|
+// 00000080  19 66 00 f0 12 f8 00 21  99 60 16 49 14 48 01 60  |.f.....!.`.I.H.`|
+// 00000090  01 21 99 60 01 bc 00 28  00 d0 00 47 12 48 13 49  |.!.`...(...G.H.I|
+// 000000a0  08 60 03 c8 80 f3 08 88  08 47 03 b5 99 6a 04 20  |.`.......G...j. |
+// 000000b0  01 42 fb d0 01 20 01 42  f8 d1 03 bd 02 b5 18 66  |.B... .B.......f|
+// 000000c0  18 66 ff f7 f2 ff 18 6e  18 6e 02 bd 00 00 02 40  |.f.....n.n.....@|
+// 000000d0  00 00 00 18 00 00 07 00  00 03 5f 00 21 22 00 00  |.........._.!"..|
+// 000000e0  f4 00 00 18 22 20 00 a0  00 01 00 10 08 ed 00 e0  |...." ..........|
+// 000000f0  00 00 00 00 00 00 00 00  00 00 00 00 74 b2 4e 7a  |............t.Nz|
+
+.byte 0x00, 0xb5, 0x32, 0x4b, 0x21, 0x20, 0x58, 0x60,   0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60
+.byte 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2e, 0x4b,   0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61
+.byte 0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x2b, 0x49,   0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20
+.byte 0x00, 0xf0, 0x44, 0xf8, 0x02, 0x22, 0x90, 0x42,   0x14, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0
+.byte 0x34, 0xf8, 0x19, 0x6e, 0x01, 0x21, 0x19, 0x66,   0x00, 0x20, 0x18, 0x66, 0x1a, 0x66, 0x00, 0xf0
+.byte 0x2c, 0xf8, 0x19, 0x6e, 0x19, 0x6e, 0x19, 0x6e,   0x05, 0x20, 0x00, 0xf0, 0x2f, 0xf8, 0x01, 0x21
+.byte 0x08, 0x42, 0xf9, 0xd1, 0x00, 0x21, 0x99, 0x60,   0x1b, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60
+.byte 0x1a, 0x49, 0x1b, 0x48, 0x01, 0x60, 0x01, 0x21,   0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0xa0, 0x21
+.byte 0x19, 0x66, 0x00, 0xf0, 0x12, 0xf8, 0x00, 0x21,   0x99, 0x60, 0x16, 0x49, 0x14, 0x48, 0x01, 0x60
+.byte 0x01, 0x21, 0x99, 0x60, 0x01, 0xbc, 0x00, 0x28,   0x00, 0xd0, 0x00, 0x47, 0x12, 0x48, 0x13, 0x49
+.byte 0x08, 0x60, 0x03, 0xc8, 0x80, 0xf3, 0x08, 0x88,   0x08, 0x47, 0x03, 0xb5, 0x99, 0x6a, 0x04, 0x20
+.byte 0x01, 0x42, 0xfb, 0xd0, 0x01, 0x20, 0x01, 0x42,   0xf8, 0xd1, 0x03, 0xbd, 0x02, 0xb5, 0x18, 0x66
+.byte 0x18, 0x66, 0xff, 0xf7, 0xf2, 0xff, 0x18, 0x6e,   0x18, 0x6e, 0x02, 0xbd, 0x00, 0x00, 0x02, 0x40
+.byte 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00,   0x00, 0x03, 0x5f, 0x00, 0x21, 0x22, 0x00, 0x00
+.byte 0xf4, 0x00, 0x00, 0x18, 0x22, 0x20, 0x00, 0xa0,   0x00, 0x01, 0x00, 0x10, 0x08, 0xed, 0x00, 0xe0
+.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,   0x00, 0x00, 0x00, 0x00, 0x74, 0xb2, 0x4e, 0x7a
+
diff --git a/src/chips.zig b/src/chips.zig
deleted file mode 100644
index 48b20e033..000000000
--- a/src/chips.zig
+++ /dev/null
@@ -1,25 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse ".";
-}
-
-const chip_path = std.fmt.comptimePrint("{s}/chips/RP2040.zig", .{root_dir()});
-const hal_path = std.fmt.comptimePrint("{s}/hal.zig", .{root_dir()});
-const json_register_schema_path = std.fmt.comptimePrint("{s}/chips/RP2040.json", .{root_dir()});
-
-pub const rp2040 = microzig.Chip{
-    .name = "RP2040",
-    .source = .{ .path = chip_path },
-    .hal = .{ .path = hal_path },
-    .cpu = microzig.cpus.cortex_m0plus,
-    .memory_regions = &.{
-        .{ .kind = .flash, .offset = 0x10000100, .length = (2048 * 1024) - 256 },
-        .{ .kind = .flash, .offset = 0x10000000, .length = 256 },
-        .{ .kind = .ram, .offset = 0x20000000, .length = 256 * 1024 },
-    },
-    .json_register_schema = .{
-        .path = json_register_schema_path,
-    },
-};
diff --git a/src/chips/RP2040.zig b/src/chips/RP2040.zig
deleted file mode 100644
index a11f25564..000000000
--- a/src/chips/RP2040.zig
+++ /dev/null
@@ -1,18145 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    pub const RP2040 = struct {
-        pub const properties = struct {
-            pub const @"cpu.nvic_prio_bits" = "2";
-            pub const @"cpu.mpu" = "true";
-            pub const @"cpu.fpu" = "false";
-            pub const @"cpu.num_interrupts" = "26";
-            pub const @"cpu.vtor" = "1";
-            pub const @"cpu.revision" = "r0p1";
-            pub const @"cpu.vendor_systick_config" = "false";
-            pub const license =
-                \\
-                \\    Copyright (c) 2020 Raspberry Pi (Trading) Ltd. \n
-                \\    \n
-                \\    SPDX-License-Identifier: BSD-3-Clause
-                \\  
-            ;
-            pub const @"cpu.name" = "CM0PLUS";
-            pub const @"cpu.endian" = "little";
-        };
-
-        pub const VectorTable = extern struct {
-            const Handler = micro.interrupt.Handler;
-            const unhandled = micro.interrupt.unhandled;
-
-            initial_stack_pointer: u32,
-            Reset: Handler = unhandled,
-            NMI: Handler = unhandled,
-            HardFault: Handler = unhandled,
-            reserved2: [7]u32 = undefined,
-            SVCall: Handler = unhandled,
-            reserved10: [2]u32 = undefined,
-            PendSV: Handler = unhandled,
-            SysTick: Handler = unhandled,
-            TIMER_IRQ_0: Handler = unhandled,
-            TIMER_IRQ_1: Handler = unhandled,
-            TIMER_IRQ_2: Handler = unhandled,
-            TIMER_IRQ_3: Handler = unhandled,
-            PWM_IRQ_WRAP: Handler = unhandled,
-            USBCTRL_IRQ: Handler = unhandled,
-            XIP_IRQ: Handler = unhandled,
-            PIO0_IRQ_0: Handler = unhandled,
-            PIO0_IRQ_1: Handler = unhandled,
-            PIO1_IRQ_0: Handler = unhandled,
-            PIO1_IRQ_1: Handler = unhandled,
-            DMA_IRQ_0: Handler = unhandled,
-            DMA_IRQ_1: Handler = unhandled,
-            IO_IRQ_BANK0: Handler = unhandled,
-            IO_IRQ_QSPI: Handler = unhandled,
-            SIO_IRQ_PROC0: Handler = unhandled,
-            SIO_IRQ_PROC1: Handler = unhandled,
-            CLOCKS_IRQ: Handler = unhandled,
-            SPI0_IRQ: Handler = unhandled,
-            SPI1_IRQ: Handler = unhandled,
-            UART0_IRQ: Handler = unhandled,
-            UART1_IRQ: Handler = unhandled,
-            ADC_IRQ_FIFO: Handler = unhandled,
-            I2C0_IRQ: Handler = unhandled,
-            I2C1_IRQ: Handler = unhandled,
-            RTC_IRQ: Handler = unhandled,
-        };
-
-        pub const peripherals = struct {
-            ///  System Control Space
-            pub const MPU = @as(*volatile types.peripherals.SCS, @ptrFromInt(0xd90));
-            ///  QSPI flash execute-in-place block
-            pub const XIP_CTRL = @as(*volatile types.peripherals.XIP_CTRL, @ptrFromInt(0x14000000));
-            ///  DW_apb_ssi has the following features:
-            ///  * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.
-            ///  * APB3 and APB4 protocol support.
-            ///  * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.
-            ///  * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.
-            ///  * Programmable Dual/Quad/Octal SPI support in Master Mode.
-            ///  * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.
-            ///  * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.
-            ///  * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.
-            ///  * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.
-            ///  * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.
-            ///  * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.
-            ///  * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.
-            ///  * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.
-            ///  * Programmable features:
-            ///  - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.
-            ///  - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.
-            ///  - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.
-            ///  * Configured features:
-            ///  - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.
-            ///  - 1 slave select output.
-            ///  - Hardware slave-select – Dedicated hardware slave-select line.
-            ///  - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.
-            ///  - Interrupt polarity – active high interrupt lines.
-            ///  - Serial clock polarity – low serial-clock polarity directly after reset.
-            ///  - Serial clock phase – capture on first edge of serial-clock directly after reset.
-            pub const XIP_SSI = @as(*volatile types.peripherals.XIP_SSI, @ptrFromInt(0x18000000));
-            pub const SYSINFO = @as(*volatile types.peripherals.SYSINFO, @ptrFromInt(0x40000000));
-            ///  Register block for various chip control signals
-            pub const SYSCFG = @as(*volatile types.peripherals.SYSCFG, @ptrFromInt(0x40004000));
-            pub const CLOCKS = @as(*volatile types.peripherals.CLOCKS, @ptrFromInt(0x40008000));
-            pub const RESETS = @as(*volatile types.peripherals.RESETS, @ptrFromInt(0x4000c000));
-            pub const PSM = @as(*volatile types.peripherals.PSM, @ptrFromInt(0x40010000));
-            pub const IO_BANK0 = @as(*volatile types.peripherals.IO_BANK0, @ptrFromInt(0x40014000));
-            pub const IO_QSPI = @as(*volatile types.peripherals.IO_QSPI, @ptrFromInt(0x40018000));
-            pub const PADS_BANK0 = @as(*volatile types.peripherals.PADS_BANK0, @ptrFromInt(0x4001c000));
-            pub const PADS_QSPI = @as(*volatile types.peripherals.PADS_QSPI, @ptrFromInt(0x40020000));
-            ///  Controls the crystal oscillator
-            pub const XOSC = @as(*volatile types.peripherals.XOSC, @ptrFromInt(0x40024000));
-            pub const PLL_SYS = @as(*volatile types.peripherals.PLL_SYS, @ptrFromInt(0x40028000));
-            pub const PLL_USB = @as(*volatile types.peripherals.PLL_SYS, @ptrFromInt(0x4002c000));
-            ///  Register block for busfabric control signals and performance counters
-            pub const BUSCTRL = @as(*volatile types.peripherals.BUSCTRL, @ptrFromInt(0x40030000));
-            pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40034000));
-            pub const UART1 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x40038000));
-            pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x4003c000));
-            pub const SPI1 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x40040000));
-            ///  DW_apb_i2c address block
-            ///  List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
-            ///  IC_ULTRA_FAST_MODE ................ 0x0
-            ///  IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
-            ///  IC_UFM_SCL_LOW_COUNT .............. 0x0008
-            ///  IC_UFM_SCL_HIGH_COUNT ............. 0x0006
-            ///  IC_TX_TL .......................... 0x0
-            ///  IC_TX_CMD_BLOCK ................... 0x1
-            ///  IC_HAS_DMA ........................ 0x1
-            ///  IC_HAS_ASYNC_FIFO ................. 0x0
-            ///  IC_SMBUS_ARP ...................... 0x0
-            ///  IC_FIRST_DATA_BYTE_STATUS ......... 0x1
-            ///  IC_INTR_IO ........................ 0x1
-            ///  IC_MASTER_MODE .................... 0x1
-            ///  IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
-            ///  IC_INTR_POL ....................... 0x1
-            ///  IC_OPTIONAL_SAR ................... 0x0
-            ///  IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
-            ///  IC_DEFAULT_SLAVE_ADDR ............. 0x055
-            ///  IC_DEFAULT_HS_SPKLEN .............. 0x1
-            ///  IC_FS_SCL_HIGH_COUNT .............. 0x0006
-            ///  IC_HS_SCL_LOW_COUNT ............... 0x0008
-            ///  IC_DEVICE_ID_VALUE ................ 0x0
-            ///  IC_10BITADDR_MASTER ............... 0x0
-            ///  IC_CLK_FREQ_OPTIMIZATION .......... 0x0
-            ///  IC_DEFAULT_FS_SPKLEN .............. 0x7
-            ///  IC_ADD_ENCODED_PARAMS ............. 0x0
-            ///  IC_DEFAULT_SDA_HOLD ............... 0x000001
-            ///  IC_DEFAULT_SDA_SETUP .............. 0x64
-            ///  IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
-            ///  IC_CLOCK_PERIOD ................... 100
-            ///  IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
-            ///  IC_RESTART_EN ..................... 0x1
-            ///  IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
-            ///  IC_BUS_CLEAR_FEATURE .............. 0x0
-            ///  IC_CAP_LOADING .................... 100
-            ///  IC_FS_SCL_LOW_COUNT ............... 0x000d
-            ///  APB_DATA_WIDTH .................... 32
-            ///  IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
-            ///  IC_SLV_DATA_NACK_ONLY ............. 0x1
-            ///  IC_10BITADDR_SLAVE ................ 0x0
-            ///  IC_CLK_TYPE ....................... 0x0
-            ///  IC_SMBUS_UDID_MSB ................. 0x0
-            ///  IC_SMBUS_SUSPEND_ALERT ............ 0x0
-            ///  IC_HS_SCL_HIGH_COUNT .............. 0x0006
-            ///  IC_SLV_RESTART_DET_EN ............. 0x1
-            ///  IC_SMBUS .......................... 0x0
-            ///  IC_OPTIONAL_SAR_DEFAULT ........... 0x0
-            ///  IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
-            ///  IC_USE_COUNTS ..................... 0x0
-            ///  IC_RX_BUFFER_DEPTH ................ 16
-            ///  IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
-            ///  IC_RX_FULL_HLD_BUS_EN ............. 0x1
-            ///  IC_SLAVE_DISABLE .................. 0x1
-            ///  IC_RX_TL .......................... 0x0
-            ///  IC_DEVICE_ID ...................... 0x0
-            ///  IC_HC_COUNT_VALUES ................ 0x0
-            ///  I2C_DYNAMIC_TAR_UPDATE ............ 0
-            ///  IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
-            ///  IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
-            ///  IC_HS_MASTER_CODE ................. 0x1
-            ///  IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
-            ///  IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
-            ///  IC_SS_SCL_HIGH_COUNT .............. 0x0028
-            ///  IC_SS_SCL_LOW_COUNT ............... 0x002f
-            ///  IC_MAX_SPEED_MODE ................. 0x2
-            ///  IC_STAT_FOR_CLK_STRETCH ........... 0x0
-            ///  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
-            ///  IC_DEFAULT_UFM_SPKLEN ............. 0x1
-            ///  IC_TX_BUFFER_DEPTH ................ 16
-            pub const I2C0 = @as(*volatile types.peripherals.I2C0, @ptrFromInt(0x40044000));
-            ///  DW_apb_i2c address block
-            ///  List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
-            ///  IC_ULTRA_FAST_MODE ................ 0x0
-            ///  IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
-            ///  IC_UFM_SCL_LOW_COUNT .............. 0x0008
-            ///  IC_UFM_SCL_HIGH_COUNT ............. 0x0006
-            ///  IC_TX_TL .......................... 0x0
-            ///  IC_TX_CMD_BLOCK ................... 0x1
-            ///  IC_HAS_DMA ........................ 0x1
-            ///  IC_HAS_ASYNC_FIFO ................. 0x0
-            ///  IC_SMBUS_ARP ...................... 0x0
-            ///  IC_FIRST_DATA_BYTE_STATUS ......... 0x1
-            ///  IC_INTR_IO ........................ 0x1
-            ///  IC_MASTER_MODE .................... 0x1
-            ///  IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
-            ///  IC_INTR_POL ....................... 0x1
-            ///  IC_OPTIONAL_SAR ................... 0x0
-            ///  IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
-            ///  IC_DEFAULT_SLAVE_ADDR ............. 0x055
-            ///  IC_DEFAULT_HS_SPKLEN .............. 0x1
-            ///  IC_FS_SCL_HIGH_COUNT .............. 0x0006
-            ///  IC_HS_SCL_LOW_COUNT ............... 0x0008
-            ///  IC_DEVICE_ID_VALUE ................ 0x0
-            ///  IC_10BITADDR_MASTER ............... 0x0
-            ///  IC_CLK_FREQ_OPTIMIZATION .......... 0x0
-            ///  IC_DEFAULT_FS_SPKLEN .............. 0x7
-            ///  IC_ADD_ENCODED_PARAMS ............. 0x0
-            ///  IC_DEFAULT_SDA_HOLD ............... 0x000001
-            ///  IC_DEFAULT_SDA_SETUP .............. 0x64
-            ///  IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
-            ///  IC_CLOCK_PERIOD ................... 100
-            ///  IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
-            ///  IC_RESTART_EN ..................... 0x1
-            ///  IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
-            ///  IC_BUS_CLEAR_FEATURE .............. 0x0
-            ///  IC_CAP_LOADING .................... 100
-            ///  IC_FS_SCL_LOW_COUNT ............... 0x000d
-            ///  APB_DATA_WIDTH .................... 32
-            ///  IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
-            ///  IC_SLV_DATA_NACK_ONLY ............. 0x1
-            ///  IC_10BITADDR_SLAVE ................ 0x0
-            ///  IC_CLK_TYPE ....................... 0x0
-            ///  IC_SMBUS_UDID_MSB ................. 0x0
-            ///  IC_SMBUS_SUSPEND_ALERT ............ 0x0
-            ///  IC_HS_SCL_HIGH_COUNT .............. 0x0006
-            ///  IC_SLV_RESTART_DET_EN ............. 0x1
-            ///  IC_SMBUS .......................... 0x0
-            ///  IC_OPTIONAL_SAR_DEFAULT ........... 0x0
-            ///  IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
-            ///  IC_USE_COUNTS ..................... 0x0
-            ///  IC_RX_BUFFER_DEPTH ................ 16
-            ///  IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
-            ///  IC_RX_FULL_HLD_BUS_EN ............. 0x1
-            ///  IC_SLAVE_DISABLE .................. 0x1
-            ///  IC_RX_TL .......................... 0x0
-            ///  IC_DEVICE_ID ...................... 0x0
-            ///  IC_HC_COUNT_VALUES ................ 0x0
-            ///  I2C_DYNAMIC_TAR_UPDATE ............ 0
-            ///  IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
-            ///  IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
-            ///  IC_HS_MASTER_CODE ................. 0x1
-            ///  IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
-            ///  IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
-            ///  IC_SS_SCL_HIGH_COUNT .............. 0x0028
-            ///  IC_SS_SCL_LOW_COUNT ............... 0x002f
-            ///  IC_MAX_SPEED_MODE ................. 0x2
-            ///  IC_STAT_FOR_CLK_STRETCH ........... 0x0
-            ///  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
-            ///  IC_DEFAULT_UFM_SPKLEN ............. 0x1
-            ///  IC_TX_BUFFER_DEPTH ................ 16
-            pub const I2C1 = @as(*volatile types.peripherals.I2C0, @ptrFromInt(0x40048000));
-            ///  Control and data interface to SAR ADC
-            pub const ADC = @as(*volatile types.peripherals.ADC, @ptrFromInt(0x4004c000));
-            ///  Simple PWM
-            pub const PWM = @as(*volatile types.peripherals.PWM, @ptrFromInt(0x40050000));
-            ///  Controls time and alarms
-            ///  time is a 64 bit value indicating the time in usec since power-on
-            ///  timeh is the top 32 bits of time & timel is the bottom 32 bits
-            ///  to change time write to timelw before timehw
-            ///  to read time read from timelr before timehr
-            ///  An alarm is set by setting alarm_enable and writing to the corresponding alarm register
-            ///  When an alarm is pending, the corresponding alarm_running signal will be high
-            ///  An alarm can be cancelled before it has finished by clearing the alarm_enable
-            ///  When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared
-            ///  To clear the interrupt write a 1 to the corresponding alarm_irq
-            pub const TIMER = @as(*volatile types.peripherals.TIMER, @ptrFromInt(0x40054000));
-            pub const WATCHDOG = @as(*volatile types.peripherals.WATCHDOG, @ptrFromInt(0x40058000));
-            ///  Register block to control RTC
-            pub const RTC = @as(*volatile types.peripherals.RTC, @ptrFromInt(0x4005c000));
-            pub const ROSC = @as(*volatile types.peripherals.ROSC, @ptrFromInt(0x40060000));
-            ///  control and status for on-chip voltage regulator and chip level reset subsystem
-            pub const VREG_AND_CHIP_RESET = @as(*volatile types.peripherals.VREG_AND_CHIP_RESET, @ptrFromInt(0x40064000));
-            ///  Testbench manager. Allows the programmer to know what platform their software is running on.
-            pub const TBMAN = @as(*volatile types.peripherals.TBMAN, @ptrFromInt(0x4006c000));
-            ///  DMA with separate read and write masters
-            pub const DMA = @as(*volatile types.peripherals.DMA, @ptrFromInt(0x50000000));
-            ///  DPRAM layout for USB device.
-            pub const USBCTRL_DPRAM = @as(*volatile types.peripherals.USBCTRL_DPRAM, @ptrFromInt(0x50100000));
-            ///  USB FS/LS controller device registers
-            pub const USBCTRL_REGS = @as(*volatile types.peripherals.USBCTRL_REGS, @ptrFromInt(0x50110000));
-            ///  Programmable IO block
-            pub const PIO0 = @as(*volatile types.peripherals.PIO0, @ptrFromInt(0x50200000));
-            ///  Programmable IO block
-            pub const PIO1 = @as(*volatile types.peripherals.PIO0, @ptrFromInt(0x50300000));
-            ///  Single-cycle IO block
-            ///  Provides core-local and inter-core hardware for the two processors, with single-cycle access.
-            pub const SIO = @as(*volatile types.peripherals.SIO, @ptrFromInt(0xd0000000));
-            pub const PPB = @as(*volatile types.peripherals.PPB, @ptrFromInt(0xe0000000));
-            ///  System Tick Timer
-            pub const SysTick = @as(*volatile types.peripherals.SysTick, @ptrFromInt(0xe000e010));
-            ///  System Control Space
-            pub const NVIC = @as(*volatile types.peripherals.NVIC, @ptrFromInt(0xe000e100));
-            ///  System Control Space
-            pub const SCB = @as(*volatile types.peripherals.SCB, @ptrFromInt(0xe000ed00));
-        };
-    };
-};
-
-pub const types = struct {
-    pub const peripherals = struct {
-        ///  System Tick Timer
-        pub const SysTick = extern struct {
-            ///  SysTick Control and Status Register
-            CTRL: mmio.Mmio(packed struct(u32) {
-                ENABLE: u1,
-                TICKINT: u1,
-                CLKSOURCE: u1,
-                reserved16: u13,
-                COUNTFLAG: u1,
-                padding: u15,
-            }),
-            ///  SysTick Reload Value Register
-            LOAD: mmio.Mmio(packed struct(u32) {
-                RELOAD: u24,
-                padding: u8,
-            }),
-            ///  SysTick Current Value Register
-            VAL: mmio.Mmio(packed struct(u32) {
-                CURRENT: u24,
-                padding: u8,
-            }),
-            ///  SysTick Calibration Register
-            CALIB: mmio.Mmio(packed struct(u32) {
-                TENMS: u24,
-                reserved30: u6,
-                SKEW: u1,
-                NOREF: u1,
-            }),
-        };
-
-        ///  System Control Block
-        pub const SCB = extern struct {
-            CPUID: mmio.Mmio(packed struct(u32) {
-                REVISION: u4,
-                PARTNO: u12,
-                ARCHITECTURE: u4,
-                VARIANT: u4,
-                IMPLEMENTER: u8,
-            }),
-            ///  Interrupt Control and State Register
-            ICSR: mmio.Mmio(packed struct(u32) {
-                VECTACTIVE: u9,
-                reserved12: u3,
-                VECTPENDING: u9,
-                reserved22: u1,
-                ISRPENDING: u1,
-                ISRPREEMPT: u1,
-                reserved25: u1,
-                PENDSTCLR: u1,
-                PENDSTSET: u1,
-                PENDSVCLR: u1,
-                PENDSVSET: u1,
-                reserved31: u2,
-                NMIPENDSET: u1,
-            }),
-            ///  Vector Table Offset Register
-            VTOR: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                TBLOFF: u24,
-            }),
-            ///  Application Interrupt and Reset Control Register
-            AIRCR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                VECTCLRACTIVE: u1,
-                SYSRESETREQ: u1,
-                reserved15: u12,
-                ENDIANESS: u1,
-                VECTKEY: u16,
-            }),
-            ///  System Control Register
-            SCR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                SLEEPONEXIT: u1,
-                SLEEPDEEP: u1,
-                reserved4: u1,
-                SEVONPEND: u1,
-                padding: u27,
-            }),
-            ///  Configuration Control Register
-            CCR: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                UNALIGN_TRP: u1,
-                reserved9: u5,
-                STKALIGN: u1,
-                padding: u22,
-            }),
-            reserved28: [4]u8,
-            ///  System Handlers Priority Registers. [0] is RESERVED
-            SHP: u32,
-            reserved36: [4]u8,
-            ///  System Handler Control and State Register
-            SHCSR: mmio.Mmio(packed struct(u32) {
-                reserved15: u15,
-                SVCALLPENDED: u1,
-                padding: u16,
-            }),
-        };
-
-        ///  Nested Vectored Interrupt Controller
-        pub const NVIC = extern struct {
-            ///  Interrupt Set Enable Register
-            ISER: mmio.Mmio(packed struct(u32) {
-                TIMER_IRQ_0: u1,
-                TIMER_IRQ_1: u1,
-                TIMER_IRQ_2: u1,
-                TIMER_IRQ_3: u1,
-                PWM_IRQ_WRAP: u1,
-                USBCTRL_IRQ: u1,
-                XIP_IRQ: u1,
-                PIO0_IRQ_0: u1,
-                PIO0_IRQ_1: u1,
-                PIO1_IRQ_0: u1,
-                PIO1_IRQ_1: u1,
-                DMA_IRQ_0: u1,
-                DMA_IRQ_1: u1,
-                IO_IRQ_BANK0: u1,
-                IO_IRQ_QSPI: u1,
-                SIO_IRQ_PROC0: u1,
-                SIO_IRQ_PROC1: u1,
-                CLOCKS_IRQ: u1,
-                SPI0_IRQ: u1,
-                SPI1_IRQ: u1,
-                UART0_IRQ: u1,
-                UART1_IRQ: u1,
-                ADC_IRQ_FIFO: u1,
-                I2C0_IRQ: u1,
-                I2C1_IRQ: u1,
-                RTC_IRQ: u1,
-                padding: u6,
-            }),
-            reserved128: [124]u8,
-            ///  Interrupt Clear Enable Register
-            ICER: mmio.Mmio(packed struct(u32) {
-                TIMER_IRQ_0: u1,
-                TIMER_IRQ_1: u1,
-                TIMER_IRQ_2: u1,
-                TIMER_IRQ_3: u1,
-                PWM_IRQ_WRAP: u1,
-                USBCTRL_IRQ: u1,
-                XIP_IRQ: u1,
-                PIO0_IRQ_0: u1,
-                PIO0_IRQ_1: u1,
-                PIO1_IRQ_0: u1,
-                PIO1_IRQ_1: u1,
-                DMA_IRQ_0: u1,
-                DMA_IRQ_1: u1,
-                IO_IRQ_BANK0: u1,
-                IO_IRQ_QSPI: u1,
-                SIO_IRQ_PROC0: u1,
-                SIO_IRQ_PROC1: u1,
-                CLOCKS_IRQ: u1,
-                SPI0_IRQ: u1,
-                SPI1_IRQ: u1,
-                UART0_IRQ: u1,
-                UART1_IRQ: u1,
-                ADC_IRQ_FIFO: u1,
-                I2C0_IRQ: u1,
-                I2C1_IRQ: u1,
-                RTC_IRQ: u1,
-                padding: u6,
-            }),
-            reserved256: [124]u8,
-            ///  Interrupt Set Pending Register
-            ISPR: mmio.Mmio(packed struct(u32) {
-                TIMER_IRQ_0: u1,
-                TIMER_IRQ_1: u1,
-                TIMER_IRQ_2: u1,
-                TIMER_IRQ_3: u1,
-                PWM_IRQ_WRAP: u1,
-                USBCTRL_IRQ: u1,
-                XIP_IRQ: u1,
-                PIO0_IRQ_0: u1,
-                PIO0_IRQ_1: u1,
-                PIO1_IRQ_0: u1,
-                PIO1_IRQ_1: u1,
-                DMA_IRQ_0: u1,
-                DMA_IRQ_1: u1,
-                IO_IRQ_BANK0: u1,
-                IO_IRQ_QSPI: u1,
-                SIO_IRQ_PROC0: u1,
-                SIO_IRQ_PROC1: u1,
-                CLOCKS_IRQ: u1,
-                SPI0_IRQ: u1,
-                SPI1_IRQ: u1,
-                UART0_IRQ: u1,
-                UART1_IRQ: u1,
-                ADC_IRQ_FIFO: u1,
-                I2C0_IRQ: u1,
-                I2C1_IRQ: u1,
-                RTC_IRQ: u1,
-                padding: u6,
-            }),
-            reserved384: [124]u8,
-            ///  Interrupt Clear Pending Register
-            ICPR: mmio.Mmio(packed struct(u32) {
-                TIMER_IRQ_0: u1,
-                TIMER_IRQ_1: u1,
-                TIMER_IRQ_2: u1,
-                TIMER_IRQ_3: u1,
-                PWM_IRQ_WRAP: u1,
-                USBCTRL_IRQ: u1,
-                XIP_IRQ: u1,
-                PIO0_IRQ_0: u1,
-                PIO0_IRQ_1: u1,
-                PIO1_IRQ_0: u1,
-                PIO1_IRQ_1: u1,
-                DMA_IRQ_0: u1,
-                DMA_IRQ_1: u1,
-                IO_IRQ_BANK0: u1,
-                IO_IRQ_QSPI: u1,
-                SIO_IRQ_PROC0: u1,
-                SIO_IRQ_PROC1: u1,
-                CLOCKS_IRQ: u1,
-                SPI0_IRQ: u1,
-                SPI1_IRQ: u1,
-                UART0_IRQ: u1,
-                UART1_IRQ: u1,
-                ADC_IRQ_FIFO: u1,
-                I2C0_IRQ: u1,
-                I2C1_IRQ: u1,
-                RTC_IRQ: u1,
-                padding: u6,
-            }),
-            reserved768: [380]u8,
-            ///  Interrupt Priority Register
-            IPR0: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                TIMER_IRQ_0: u2,
-                reserved14: u6,
-                TIMER_IRQ_1: u2,
-                reserved22: u6,
-                TIMER_IRQ_2: u2,
-                reserved30: u6,
-                TIMER_IRQ_3: u2,
-            }),
-            ///  Interrupt Priority Register
-            IPR1: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                PWM_IRQ_WRAP: u2,
-                reserved14: u6,
-                USBCTRL_IRQ: u2,
-                reserved22: u6,
-                XIP_IRQ: u2,
-                reserved30: u6,
-                PIO0_IRQ_0: u2,
-            }),
-            ///  Interrupt Priority Register
-            IPR2: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                PIO0_IRQ_1: u2,
-                reserved14: u6,
-                PIO1_IRQ_0: u2,
-                reserved22: u6,
-                PIO1_IRQ_1: u2,
-                reserved30: u6,
-                DMA_IRQ_0: u2,
-            }),
-            ///  Interrupt Priority Register
-            IPR3: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                DMA_IRQ_1: u2,
-                reserved14: u6,
-                IO_IRQ_BANK0: u2,
-                reserved22: u6,
-                IO_IRQ_QSPI: u2,
-                reserved30: u6,
-                SIO_IRQ_PROC0: u2,
-            }),
-            ///  Interrupt Priority Register
-            IPR4: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                SIO_IRQ_PROC1: u2,
-                reserved14: u6,
-                CLOCKS_IRQ: u2,
-                reserved22: u6,
-                SPI0_IRQ: u2,
-                reserved30: u6,
-                SPI1_IRQ: u2,
-            }),
-            ///  Interrupt Priority Register
-            IPR5: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                UART0_IRQ: u2,
-                reserved14: u6,
-                UART1_IRQ: u2,
-                reserved22: u6,
-                ADC_IRQ_FIFO: u2,
-                reserved30: u6,
-                I2C0_IRQ: u2,
-            }),
-            ///  Interrupt Priority Register
-            IPR6: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                I2C1_IRQ: u2,
-                reserved14: u6,
-                RTC_IRQ: u2,
-                padding: u16,
-            }),
-            ///  Interrupt Priority Register
-            IPR7: u32,
-        };
-
-        ///  Memory Protection Unit
-        pub const MPU = extern struct {
-            ///  MPU Type Register
-            TYPE: mmio.Mmio(packed struct(u32) {
-                SEPARATE: u1,
-                reserved8: u7,
-                DREGION: u8,
-                IREGION: u8,
-                padding: u8,
-            }),
-            ///  MPU Control Register
-            CTRL: mmio.Mmio(packed struct(u32) {
-                ENABLE: u1,
-                HFNMIENA: u1,
-                PRIVDEFENA: u1,
-                padding: u29,
-            }),
-            ///  MPU Region RNRber Register
-            RNR: mmio.Mmio(packed struct(u32) {
-                REGION: u8,
-                padding: u24,
-            }),
-            ///  MPU Region Base Address Register
-            RBAR: mmio.Mmio(packed struct(u32) {
-                REGION: u4,
-                VALID: u1,
-                reserved8: u3,
-                ADDR: u24,
-            }),
-            ///  MPU Region Attribute and Size Register
-            RASR: mmio.Mmio(packed struct(u32) {
-                ENABLE: u1,
-                SIZE: u5,
-                reserved8: u2,
-                SRD: u8,
-                B: u1,
-                C: u1,
-                S: u1,
-                TEX: u3,
-                reserved24: u2,
-                AP: u3,
-                reserved28: u1,
-                XN: u1,
-                padding: u3,
-            }),
-        };
-
-        ///  QSPI flash execute-in-place block
-        pub const XIP_CTRL = extern struct {
-            ///  Cache control
-            CTRL: mmio.Mmio(packed struct(u32) {
-                ///  When 1, enable the cache. When the cache is disabled, all XIP accesses
-                ///  will go straight to the flash, without querying the cache. When enabled,
-                ///  cacheable XIP accesses will query the cache, and the flash will
-                ///  not be accessed if the tag matches and the valid bit is set.
-                ///  If the cache is enabled, cache-as-SRAM accesses have no effect on the
-                ///  cache data RAM, and will produce a bus error response.
-                EN: u1,
-                ///  When 1, writes to any alias other than 0x0 (caching, allocating)
-                ///  will produce a bus fault. When 0, these writes are silently ignored.
-                ///  In either case, writes to the 0x0 alias will deallocate on tag match,
-                ///  as usual.
-                ERR_BADWRITE: u1,
-                reserved3: u1,
-                ///  When 1, the cache memories are powered down. They retain state,
-                ///  but can not be accessed. This reduces static power dissipation.
-                ///  Writing 1 to this bit forces CTRL_EN to 0, i.e. the cache cannot
-                ///  be enabled when powered down.
-                ///  Cache-as-SRAM accesses will produce a bus error response when
-                ///  the cache is powered down.
-                POWER_DOWN: u1,
-                padding: u28,
-            }),
-            ///  Cache Flush control
-            FLUSH: mmio.Mmio(packed struct(u32) {
-                ///  Write 1 to flush the cache. This clears the tag memory, but
-                ///  the data memory retains its contents. (This means cache-as-SRAM
-                ///  contents is not affected by flush or reset.)
-                ///  Reading will hold the bus (stall the processor) until the flush
-                ///  completes. Alternatively STAT can be polled until completion.
-                FLUSH: u1,
-                padding: u31,
-            }),
-            ///  Cache Status
-            STAT: mmio.Mmio(packed struct(u32) {
-                ///  Reads as 0 while a cache flush is in progress, and 1 otherwise.
-                ///  The cache is flushed whenever the XIP block is reset, and also
-                ///  when requested via the FLUSH register.
-                FLUSH_READY: u1,
-                ///  When 1, indicates the XIP streaming FIFO is completely empty.
-                FIFO_EMPTY: u1,
-                ///  When 1, indicates the XIP streaming FIFO is completely full.
-                ///  The streaming FIFO is 2 entries deep, so the full and empty
-                ///  flag allow its level to be ascertained.
-                FIFO_FULL: u1,
-                padding: u29,
-            }),
-            ///  Cache Hit counter
-            ///  A 32 bit saturating counter that increments upon each cache hit,
-            ///  i.e. when an XIP access is serviced directly from cached data.
-            ///  Write any value to clear.
-            CTR_HIT: u32,
-            ///  Cache Access counter
-            ///  A 32 bit saturating counter that increments upon each XIP access,
-            ///  whether the cache is hit or not. This includes noncacheable accesses.
-            ///  Write any value to clear.
-            CTR_ACC: u32,
-            ///  FIFO stream address
-            STREAM_ADDR: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  The address of the next word to be streamed from flash to the streaming FIFO.
-                ///  Increments automatically after each flash access.
-                ///  Write the initial access address here before starting a streaming read.
-                STREAM_ADDR: u30,
-            }),
-            ///  FIFO stream control
-            STREAM_CTR: mmio.Mmio(packed struct(u32) {
-                ///  Write a nonzero value to start a streaming read. This will then
-                ///  progress in the background, using flash idle cycles to transfer
-                ///  a linear data block from flash to the streaming FIFO.
-                ///  Decrements automatically (1 at a time) as the stream
-                ///  progresses, and halts on reaching 0.
-                ///  Write 0 to halt an in-progress stream, and discard any in-flight
-                ///  read, so that a new stream can immediately be started (after
-                ///  draining the FIFO and reinitialising STREAM_ADDR)
-                STREAM_CTR: u22,
-                padding: u10,
-            }),
-            ///  FIFO stream data
-            ///  Streamed data is buffered here, for retrieval by the system DMA.
-            ///  This FIFO can also be accessed via the XIP_AUX slave, to avoid exposing
-            ///  the DMA to bus stalls caused by other XIP traffic.
-            STREAM_FIFO: u32,
-        };
-
-        ///  DW_apb_ssi has the following features:
-        ///  * APB interface – Allows for easy integration into a DesignWare Synthesizable Components for AMBA 2 implementation.
-        ///  * APB3 and APB4 protocol support.
-        ///  * Scalable APB data bus width – Supports APB data bus widths of 8, 16, and 32 bits.
-        ///  * Serial-master or serial-slave operation – Enables serial communication with serial-master or serial-slave peripheral devices.
-        ///  * Programmable Dual/Quad/Octal SPI support in Master Mode.
-        ///  * Dual Data Rate (DDR) and Read Data Strobe (RDS) Support - Enables the DW_apb_ssi master to perform operations with the device in DDR and RDS modes when working in Dual/Quad/Octal mode of operation.
-        ///  * Data Mask Support - Enables the DW_apb_ssi to selectively update the bytes in the device. This feature is applicable only in enhanced SPI modes.
-        ///  * eXecute-In-Place (XIP) support - Enables the DW_apb_ssi master to behave as a memory mapped I/O and fetches the data from the device based on the APB read request. This feature is applicable only in enhanced SPI modes.
-        ///  * DMA Controller Interface – Enables the DW_apb_ssi to interface to a DMA controller over the bus using a handshaking interface for transfer requests.
-        ///  * Independent masking of interrupts – Master collision, transmit FIFO overflow, transmit FIFO empty, receive FIFO full, receive FIFO underflow, and receive FIFO overflow interrupts can all be masked independently.
-        ///  * Multi-master contention detection – Informs the processor of multiple serial-master accesses on the serial bus.
-        ///  * Bypass of meta-stability flip-flops for synchronous clocks – When the APB clock (pclk) and the DW_apb_ssi serial clock (ssi_clk) are synchronous, meta-stable flip-flops are not used when transferring control signals across these clock domains.
-        ///  * Programmable delay on the sample time of the received serial data bit (rxd); enables programmable control of routing delays resulting in higher serial data-bit rates.
-        ///  * Programmable features:
-        ///  - Serial interface operation – Choice of Motorola SPI, Texas Instruments Synchronous Serial Protocol or National Semiconductor Microwire.
-        ///  - Clock bit-rate – Dynamic control of the serial bit rate of the data transfer; used in only serial-master mode of operation.
-        ///  - Data Item size (4 to 32 bits) – Item size of each data transfer under the control of the programmer.
-        ///  * Configured features:
-        ///  - FIFO depth – 16 words deep. The FIFO width is fixed at 32 bits.
-        ///  - 1 slave select output.
-        ///  - Hardware slave-select – Dedicated hardware slave-select line.
-        ///  - Combined interrupt line - one combined interrupt line from the DW_apb_ssi to the interrupt controller.
-        ///  - Interrupt polarity – active high interrupt lines.
-        ///  - Serial clock polarity – low serial-clock polarity directly after reset.
-        ///  - Serial clock phase – capture on first edge of serial-clock directly after reset.
-        pub const XIP_SSI = extern struct {
-            ///  Control register 0
-            CTRLR0: mmio.Mmio(packed struct(u32) {
-                ///  Data frame size
-                DFS: u4,
-                ///  Frame format
-                FRF: u2,
-                ///  Serial clock phase
-                SCPH: u1,
-                ///  Serial clock polarity
-                SCPOL: u1,
-                ///  Transfer mode
-                TMOD: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Both transmit and receive
-                        TX_AND_RX = 0x0,
-                        ///  Transmit only (not for FRF == 0, standard SPI mode)
-                        TX_ONLY = 0x1,
-                        ///  Receive only (not for FRF == 0, standard SPI mode)
-                        RX_ONLY = 0x2,
-                        ///  EEPROM read mode (TX then RX; RX starts after control data TX'd)
-                        EEPROM_READ = 0x3,
-                    },
-                },
-                ///  Slave output enable
-                SLV_OE: u1,
-                ///  Shift register loop (test mode)
-                SRL: u1,
-                ///  Control frame size
-                ///  Value of n -> n+1 clocks per frame.
-                CFS: u4,
-                ///  Data frame size in 32b transfer mode
-                ///  Value of n -> n+1 clocks per frame.
-                DFS_32: u5,
-                ///  SPI frame format
-                SPI_FRF: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Standard 1-bit SPI frame format; 1 bit per SCK, full-duplex
-                        STD = 0x0,
-                        ///  Dual-SPI frame format; two bits per SCK, half-duplex
-                        DUAL = 0x1,
-                        ///  Quad-SPI frame format; four bits per SCK, half-duplex
-                        QUAD = 0x2,
-                        _,
-                    },
-                },
-                reserved24: u1,
-                ///  Slave select toggle enable
-                SSTE: u1,
-                padding: u7,
-            }),
-            ///  Master Control register 1
-            CTRLR1: mmio.Mmio(packed struct(u32) {
-                ///  Number of data frames
-                NDF: u16,
-                padding: u16,
-            }),
-            ///  SSI Enable
-            SSIENR: mmio.Mmio(packed struct(u32) {
-                ///  SSI enable
-                SSI_EN: u1,
-                padding: u31,
-            }),
-            ///  Microwire Control
-            MWCR: mmio.Mmio(packed struct(u32) {
-                ///  Microwire transfer mode
-                MWMOD: u1,
-                ///  Microwire control
-                MDD: u1,
-                ///  Microwire handshaking
-                MHS: u1,
-                padding: u29,
-            }),
-            ///  Slave enable
-            SER: mmio.Mmio(packed struct(u32) {
-                ///  For each bit:
-                ///  0 -> slave not selected
-                ///  1 -> slave selected
-                SER: u1,
-                padding: u31,
-            }),
-            ///  Baud rate
-            BAUDR: mmio.Mmio(packed struct(u32) {
-                ///  SSI clock divider
-                SCKDV: u16,
-                padding: u16,
-            }),
-            ///  TX FIFO threshold level
-            TXFTLR: mmio.Mmio(packed struct(u32) {
-                ///  Transmit FIFO threshold
-                TFT: u8,
-                padding: u24,
-            }),
-            ///  RX FIFO threshold level
-            RXFTLR: mmio.Mmio(packed struct(u32) {
-                ///  Receive FIFO threshold
-                RFT: u8,
-                padding: u24,
-            }),
-            ///  TX FIFO level
-            TXFLR: mmio.Mmio(packed struct(u32) {
-                ///  Transmit FIFO level
-                TFTFL: u8,
-                padding: u24,
-            }),
-            ///  RX FIFO level
-            RXFLR: mmio.Mmio(packed struct(u32) {
-                ///  Receive FIFO level
-                RXTFL: u8,
-                padding: u24,
-            }),
-            ///  Status register
-            SR: mmio.Mmio(packed struct(u32) {
-                ///  SSI busy flag
-                BUSY: u1,
-                ///  Transmit FIFO not full
-                TFNF: u1,
-                ///  Transmit FIFO empty
-                TFE: u1,
-                ///  Receive FIFO not empty
-                RFNE: u1,
-                ///  Receive FIFO full
-                RFF: u1,
-                ///  Transmission error
-                TXE: u1,
-                ///  Data collision error
-                DCOL: u1,
-                padding: u25,
-            }),
-            ///  Interrupt mask
-            IMR: mmio.Mmio(packed struct(u32) {
-                ///  Transmit FIFO empty interrupt mask
-                TXEIM: u1,
-                ///  Transmit FIFO overflow interrupt mask
-                TXOIM: u1,
-                ///  Receive FIFO underflow interrupt mask
-                RXUIM: u1,
-                ///  Receive FIFO overflow interrupt mask
-                RXOIM: u1,
-                ///  Receive FIFO full interrupt mask
-                RXFIM: u1,
-                ///  Multi-master contention interrupt mask
-                MSTIM: u1,
-                padding: u26,
-            }),
-            ///  Interrupt status
-            ISR: mmio.Mmio(packed struct(u32) {
-                ///  Transmit FIFO empty interrupt status
-                TXEIS: u1,
-                ///  Transmit FIFO overflow interrupt status
-                TXOIS: u1,
-                ///  Receive FIFO underflow interrupt status
-                RXUIS: u1,
-                ///  Receive FIFO overflow interrupt status
-                RXOIS: u1,
-                ///  Receive FIFO full interrupt status
-                RXFIS: u1,
-                ///  Multi-master contention interrupt status
-                MSTIS: u1,
-                padding: u26,
-            }),
-            ///  Raw interrupt status
-            RISR: mmio.Mmio(packed struct(u32) {
-                ///  Transmit FIFO empty raw interrupt status
-                TXEIR: u1,
-                ///  Transmit FIFO overflow raw interrupt status
-                TXOIR: u1,
-                ///  Receive FIFO underflow raw interrupt status
-                RXUIR: u1,
-                ///  Receive FIFO overflow raw interrupt status
-                RXOIR: u1,
-                ///  Receive FIFO full raw interrupt status
-                RXFIR: u1,
-                ///  Multi-master contention raw interrupt status
-                MSTIR: u1,
-                padding: u26,
-            }),
-            ///  TX FIFO overflow interrupt clear
-            TXOICR: mmio.Mmio(packed struct(u32) {
-                ///  Clear-on-read transmit FIFO overflow interrupt
-                TXOICR: u1,
-                padding: u31,
-            }),
-            ///  RX FIFO overflow interrupt clear
-            RXOICR: mmio.Mmio(packed struct(u32) {
-                ///  Clear-on-read receive FIFO overflow interrupt
-                RXOICR: u1,
-                padding: u31,
-            }),
-            ///  RX FIFO underflow interrupt clear
-            RXUICR: mmio.Mmio(packed struct(u32) {
-                ///  Clear-on-read receive FIFO underflow interrupt
-                RXUICR: u1,
-                padding: u31,
-            }),
-            ///  Multi-master interrupt clear
-            MSTICR: mmio.Mmio(packed struct(u32) {
-                ///  Clear-on-read multi-master contention interrupt
-                MSTICR: u1,
-                padding: u31,
-            }),
-            ///  Interrupt clear
-            ICR: mmio.Mmio(packed struct(u32) {
-                ///  Clear-on-read all active interrupts
-                ICR: u1,
-                padding: u31,
-            }),
-            ///  DMA control
-            DMACR: mmio.Mmio(packed struct(u32) {
-                ///  Receive DMA enable
-                RDMAE: u1,
-                ///  Transmit DMA enable
-                TDMAE: u1,
-                padding: u30,
-            }),
-            ///  DMA TX data level
-            DMATDLR: mmio.Mmio(packed struct(u32) {
-                ///  Transmit data watermark level
-                DMATDL: u8,
-                padding: u24,
-            }),
-            ///  DMA RX data level
-            DMARDLR: mmio.Mmio(packed struct(u32) {
-                ///  Receive data watermark level (DMARDLR+1)
-                DMARDL: u8,
-                padding: u24,
-            }),
-            ///  Identification register
-            IDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral dentification code
-                IDCODE: u32,
-            }),
-            ///  Version ID
-            SSI_VERSION_ID: mmio.Mmio(packed struct(u32) {
-                ///  SNPS component version (format X.YY)
-                SSI_COMP_VERSION: u32,
-            }),
-            ///  Data Register 0 (of 36)
-            DR0: mmio.Mmio(packed struct(u32) {
-                ///  First data register of 36
-                DR: u32,
-            }),
-            reserved240: [140]u8,
-            ///  RX sample delay
-            RX_SAMPLE_DLY: mmio.Mmio(packed struct(u32) {
-                ///  RXD sample delay (in SCLK cycles)
-                RSD: u8,
-                padding: u24,
-            }),
-            ///  SPI control
-            SPI_CTRLR0: mmio.Mmio(packed struct(u32) {
-                ///  Address and instruction transfer format
-                TRANS_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Command and address both in standard SPI frame format
-                        @"1C1A" = 0x0,
-                        ///  Command in standard SPI format, address in format specified by FRF
-                        @"1C2A" = 0x1,
-                        ///  Command and address both in format specified by FRF (e.g. Dual-SPI)
-                        @"2C2A" = 0x2,
-                        _,
-                    },
-                },
-                ///  Address length (0b-60b in 4b increments)
-                ADDR_L: u4,
-                reserved8: u2,
-                ///  Instruction length (0/4/8/16b)
-                INST_L: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  No instruction
-                        NONE = 0x0,
-                        ///  4-bit instruction
-                        @"4B" = 0x1,
-                        ///  8-bit instruction
-                        @"8B" = 0x2,
-                        ///  16-bit instruction
-                        @"16B" = 0x3,
-                    },
-                },
-                reserved11: u1,
-                ///  Wait cycles between control frame transmit and data reception (in SCLK cycles)
-                WAIT_CYCLES: u5,
-                ///  SPI DDR transfer enable
-                SPI_DDR_EN: u1,
-                ///  Instruction DDR transfer enable
-                INST_DDR_EN: u1,
-                ///  Read data strobe enable
-                SPI_RXDS_EN: u1,
-                reserved24: u5,
-                ///  SPI Command to send in XIP mode (INST_L = 8-bit) or to append to Address (INST_L = 0-bit)
-                XIP_CMD: u8,
-            }),
-            ///  TX drive edge
-            TXD_DRIVE_EDGE: mmio.Mmio(packed struct(u32) {
-                ///  TXD drive edge
-                TDE: u8,
-                padding: u24,
-            }),
-        };
-
-        pub const SYSINFO = extern struct {
-            ///  JEDEC JEP-106 compliant chip identifier.
-            CHIP_ID: mmio.Mmio(packed struct(u32) {
-                MANUFACTURER: u12,
-                PART: u16,
-                REVISION: u4,
-            }),
-            ///  Platform register. Allows software to know what environment it is running in.
-            PLATFORM: mmio.Mmio(packed struct(u32) {
-                FPGA: u1,
-                ASIC: u1,
-                padding: u30,
-            }),
-            reserved64: [56]u8,
-            ///  Git hash of the chip source. Used to identify chip version.
-            GITREF_RP2040: u32,
-        };
-
-        ///  Register block for various chip control signals
-        pub const SYSCFG = extern struct {
-            ///  Processor core 0 NMI source mask
-            ///  Set a bit high to enable NMI from that IRQ
-            PROC0_NMI_MASK: u32,
-            ///  Processor core 1 NMI source mask
-            ///  Set a bit high to enable NMI from that IRQ
-            PROC1_NMI_MASK: u32,
-            ///  Configuration for processors
-            PROC_CONFIG: mmio.Mmio(packed struct(u32) {
-                ///  Indication that proc0 has halted
-                PROC0_HALTED: u1,
-                ///  Indication that proc1 has halted
-                PROC1_HALTED: u1,
-                reserved24: u22,
-                ///  Configure proc0 DAP instance ID.
-                ///  Recommend that this is NOT changed until you require debug access in multi-chip environment
-                ///  WARNING: do not set to 15 as this is reserved for RescueDP
-                PROC0_DAP_INSTID: u4,
-                ///  Configure proc1 DAP instance ID.
-                ///  Recommend that this is NOT changed until you require debug access in multi-chip environment
-                ///  WARNING: do not set to 15 as this is reserved for RescueDP
-                PROC1_DAP_INSTID: u4,
-            }),
-            ///  For each bit, if 1, bypass the input synchronizer between that GPIO
-            ///  and the GPIO input register in the SIO. The input synchronizers should
-            ///  generally be unbypassed, to avoid injecting metastabilities into processors.
-            ///  If you're feeling brave, you can bypass to save two cycles of input
-            ///  latency. This register applies to GPIO 0...29.
-            PROC_IN_SYNC_BYPASS: mmio.Mmio(packed struct(u32) {
-                PROC_IN_SYNC_BYPASS: u30,
-                padding: u2,
-            }),
-            ///  For each bit, if 1, bypass the input synchronizer between that GPIO
-            ///  and the GPIO input register in the SIO. The input synchronizers should
-            ///  generally be unbypassed, to avoid injecting metastabilities into processors.
-            ///  If you're feeling brave, you can bypass to save two cycles of input
-            ///  latency. This register applies to GPIO 30...35 (the QSPI IOs).
-            PROC_IN_SYNC_BYPASS_HI: mmio.Mmio(packed struct(u32) {
-                PROC_IN_SYNC_BYPASS_HI: u6,
-                padding: u26,
-            }),
-            ///  Directly control the SWD debug port of either processor
-            DBGFORCE: mmio.Mmio(packed struct(u32) {
-                ///  Observe the value of processor 0 SWDIO output.
-                PROC0_SWDO: u1,
-                ///  Directly drive processor 0 SWDIO input, if PROC0_ATTACH is set
-                PROC0_SWDI: u1,
-                ///  Directly drive processor 0 SWCLK, if PROC0_ATTACH is set
-                PROC0_SWCLK: u1,
-                ///  Attach processor 0 debug port to syscfg controls, and disconnect it from external SWD pads.
-                PROC0_ATTACH: u1,
-                ///  Observe the value of processor 1 SWDIO output.
-                PROC1_SWDO: u1,
-                ///  Directly drive processor 1 SWDIO input, if PROC1_ATTACH is set
-                PROC1_SWDI: u1,
-                ///  Directly drive processor 1 SWCLK, if PROC1_ATTACH is set
-                PROC1_SWCLK: u1,
-                ///  Attach processor 1 debug port to syscfg controls, and disconnect it from external SWD pads.
-                PROC1_ATTACH: u1,
-                padding: u24,
-            }),
-            ///  Control power downs to memories. Set high to power down memories.
-            ///  Use with extreme caution
-            MEMPOWERDOWN: mmio.Mmio(packed struct(u32) {
-                SRAM0: u1,
-                SRAM1: u1,
-                SRAM2: u1,
-                SRAM3: u1,
-                SRAM4: u1,
-                SRAM5: u1,
-                USB: u1,
-                ROM: u1,
-                padding: u24,
-            }),
-        };
-
-        pub const CLOCKS = extern struct {
-            ///  Clock control, can be changed on-the-fly (except for auxsrc)
-            CLK_GPOUT0_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved5: u5,
-                ///  Selects the auxiliary clock source, will glitch when switching
-                AUXSRC: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        clksrc_pll_sys = 0x0,
-                        clksrc_gpin0 = 0x1,
-                        clksrc_gpin1 = 0x2,
-                        clksrc_pll_usb = 0x3,
-                        rosc_clksrc = 0x4,
-                        xosc_clksrc = 0x5,
-                        clk_sys = 0x6,
-                        clk_usb = 0x7,
-                        clk_adc = 0x8,
-                        clk_rtc = 0x9,
-                        clk_ref = 0xa,
-                        _,
-                    },
-                },
-                reserved10: u1,
-                ///  Asynchronously kills the clock generator
-                KILL: u1,
-                ///  Starts and stops the clock generator cleanly
-                ENABLE: u1,
-                ///  Enables duty cycle correction for odd divisors
-                DC50: u1,
-                reserved16: u3,
-                ///  This delays the enable signal by up to 3 cycles of the input clock
-                ///  This must be set before the clock is enabled to have any effect
-                PHASE: u2,
-                reserved20: u2,
-                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
-                ///  This can be done at any time
-                NUDGE: u1,
-                padding: u11,
-            }),
-            ///  Clock divisor, can be changed on-the-fly
-            CLK_GPOUT0_DIV: mmio.Mmio(packed struct(u32) {
-                ///  Fractional component of the divisor
-                FRAC: u8,
-                ///  Integer component of the divisor, 0 -> divide by 2^16
-                INT: u24,
-            }),
-            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
-            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
-            CLK_GPOUT0_SELECTED: u32,
-            ///  Clock control, can be changed on-the-fly (except for auxsrc)
-            CLK_GPOUT1_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved5: u5,
-                ///  Selects the auxiliary clock source, will glitch when switching
-                AUXSRC: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        clksrc_pll_sys = 0x0,
-                        clksrc_gpin0 = 0x1,
-                        clksrc_gpin1 = 0x2,
-                        clksrc_pll_usb = 0x3,
-                        rosc_clksrc = 0x4,
-                        xosc_clksrc = 0x5,
-                        clk_sys = 0x6,
-                        clk_usb = 0x7,
-                        clk_adc = 0x8,
-                        clk_rtc = 0x9,
-                        clk_ref = 0xa,
-                        _,
-                    },
-                },
-                reserved10: u1,
-                ///  Asynchronously kills the clock generator
-                KILL: u1,
-                ///  Starts and stops the clock generator cleanly
-                ENABLE: u1,
-                ///  Enables duty cycle correction for odd divisors
-                DC50: u1,
-                reserved16: u3,
-                ///  This delays the enable signal by up to 3 cycles of the input clock
-                ///  This must be set before the clock is enabled to have any effect
-                PHASE: u2,
-                reserved20: u2,
-                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
-                ///  This can be done at any time
-                NUDGE: u1,
-                padding: u11,
-            }),
-            ///  Clock divisor, can be changed on-the-fly
-            CLK_GPOUT1_DIV: mmio.Mmio(packed struct(u32) {
-                ///  Fractional component of the divisor
-                FRAC: u8,
-                ///  Integer component of the divisor, 0 -> divide by 2^16
-                INT: u24,
-            }),
-            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
-            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
-            CLK_GPOUT1_SELECTED: u32,
-            ///  Clock control, can be changed on-the-fly (except for auxsrc)
-            CLK_GPOUT2_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved5: u5,
-                ///  Selects the auxiliary clock source, will glitch when switching
-                AUXSRC: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        clksrc_pll_sys = 0x0,
-                        clksrc_gpin0 = 0x1,
-                        clksrc_gpin1 = 0x2,
-                        clksrc_pll_usb = 0x3,
-                        rosc_clksrc_ph = 0x4,
-                        xosc_clksrc = 0x5,
-                        clk_sys = 0x6,
-                        clk_usb = 0x7,
-                        clk_adc = 0x8,
-                        clk_rtc = 0x9,
-                        clk_ref = 0xa,
-                        _,
-                    },
-                },
-                reserved10: u1,
-                ///  Asynchronously kills the clock generator
-                KILL: u1,
-                ///  Starts and stops the clock generator cleanly
-                ENABLE: u1,
-                ///  Enables duty cycle correction for odd divisors
-                DC50: u1,
-                reserved16: u3,
-                ///  This delays the enable signal by up to 3 cycles of the input clock
-                ///  This must be set before the clock is enabled to have any effect
-                PHASE: u2,
-                reserved20: u2,
-                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
-                ///  This can be done at any time
-                NUDGE: u1,
-                padding: u11,
-            }),
-            ///  Clock divisor, can be changed on-the-fly
-            CLK_GPOUT2_DIV: mmio.Mmio(packed struct(u32) {
-                ///  Fractional component of the divisor
-                FRAC: u8,
-                ///  Integer component of the divisor, 0 -> divide by 2^16
-                INT: u24,
-            }),
-            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
-            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
-            CLK_GPOUT2_SELECTED: u32,
-            ///  Clock control, can be changed on-the-fly (except for auxsrc)
-            CLK_GPOUT3_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved5: u5,
-                ///  Selects the auxiliary clock source, will glitch when switching
-                AUXSRC: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        clksrc_pll_sys = 0x0,
-                        clksrc_gpin0 = 0x1,
-                        clksrc_gpin1 = 0x2,
-                        clksrc_pll_usb = 0x3,
-                        rosc_clksrc_ph = 0x4,
-                        xosc_clksrc = 0x5,
-                        clk_sys = 0x6,
-                        clk_usb = 0x7,
-                        clk_adc = 0x8,
-                        clk_rtc = 0x9,
-                        clk_ref = 0xa,
-                        _,
-                    },
-                },
-                reserved10: u1,
-                ///  Asynchronously kills the clock generator
-                KILL: u1,
-                ///  Starts and stops the clock generator cleanly
-                ENABLE: u1,
-                ///  Enables duty cycle correction for odd divisors
-                DC50: u1,
-                reserved16: u3,
-                ///  This delays the enable signal by up to 3 cycles of the input clock
-                ///  This must be set before the clock is enabled to have any effect
-                PHASE: u2,
-                reserved20: u2,
-                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
-                ///  This can be done at any time
-                NUDGE: u1,
-                padding: u11,
-            }),
-            ///  Clock divisor, can be changed on-the-fly
-            CLK_GPOUT3_DIV: mmio.Mmio(packed struct(u32) {
-                ///  Fractional component of the divisor
-                FRAC: u8,
-                ///  Integer component of the divisor, 0 -> divide by 2^16
-                INT: u24,
-            }),
-            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
-            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
-            CLK_GPOUT3_SELECTED: u32,
-            ///  Clock control, can be changed on-the-fly (except for auxsrc)
-            CLK_REF_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Selects the clock source glitchlessly, can be changed on-the-fly
-                SRC: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        rosc_clksrc_ph = 0x0,
-                        clksrc_clk_ref_aux = 0x1,
-                        xosc_clksrc = 0x2,
-                        _,
-                    },
-                },
-                reserved5: u3,
-                ///  Selects the auxiliary clock source, will glitch when switching
-                AUXSRC: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        clksrc_pll_usb = 0x0,
-                        clksrc_gpin0 = 0x1,
-                        clksrc_gpin1 = 0x2,
-                        _,
-                    },
-                },
-                padding: u25,
-            }),
-            ///  Clock divisor, can be changed on-the-fly
-            CLK_REF_DIV: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Integer component of the divisor, 0 -> divide by 2^16
-                INT: u2,
-                padding: u22,
-            }),
-            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
-            ///  The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.
-            CLK_REF_SELECTED: u32,
-            ///  Clock control, can be changed on-the-fly (except for auxsrc)
-            CLK_SYS_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Selects the clock source glitchlessly, can be changed on-the-fly
-                SRC: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        clk_ref = 0x0,
-                        clksrc_clk_sys_aux = 0x1,
-                    },
-                },
-                reserved5: u4,
-                ///  Selects the auxiliary clock source, will glitch when switching
-                AUXSRC: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        clksrc_pll_sys = 0x0,
-                        clksrc_pll_usb = 0x1,
-                        rosc_clksrc = 0x2,
-                        xosc_clksrc = 0x3,
-                        clksrc_gpin0 = 0x4,
-                        clksrc_gpin1 = 0x5,
-                        _,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Clock divisor, can be changed on-the-fly
-            CLK_SYS_DIV: mmio.Mmio(packed struct(u32) {
-                ///  Fractional component of the divisor
-                FRAC: u8,
-                ///  Integer component of the divisor, 0 -> divide by 2^16
-                INT: u24,
-            }),
-            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
-            ///  The glitchless multiplexer does not switch instantaneously (to avoid glitches), so software should poll this register to wait for the switch to complete. This register contains one decoded bit for each of the clock sources enumerated in the CTRL SRC field. At most one of these bits will be set at any time, indicating that clock is currently present at the output of the glitchless mux. Whilst switching is in progress, this register may briefly show all-0s.
-            CLK_SYS_SELECTED: u32,
-            ///  Clock control, can be changed on-the-fly (except for auxsrc)
-            CLK_PERI_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved5: u5,
-                ///  Selects the auxiliary clock source, will glitch when switching
-                AUXSRC: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        clk_sys = 0x0,
-                        clksrc_pll_sys = 0x1,
-                        clksrc_pll_usb = 0x2,
-                        rosc_clksrc_ph = 0x3,
-                        xosc_clksrc = 0x4,
-                        clksrc_gpin0 = 0x5,
-                        clksrc_gpin1 = 0x6,
-                        _,
-                    },
-                },
-                reserved10: u2,
-                ///  Asynchronously kills the clock generator
-                KILL: u1,
-                ///  Starts and stops the clock generator cleanly
-                ENABLE: u1,
-                padding: u20,
-            }),
-            reserved80: [4]u8,
-            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
-            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
-            CLK_PERI_SELECTED: u32,
-            ///  Clock control, can be changed on-the-fly (except for auxsrc)
-            CLK_USB_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved5: u5,
-                ///  Selects the auxiliary clock source, will glitch when switching
-                AUXSRC: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        clksrc_pll_usb = 0x0,
-                        clksrc_pll_sys = 0x1,
-                        rosc_clksrc_ph = 0x2,
-                        xosc_clksrc = 0x3,
-                        clksrc_gpin0 = 0x4,
-                        clksrc_gpin1 = 0x5,
-                        _,
-                    },
-                },
-                reserved10: u2,
-                ///  Asynchronously kills the clock generator
-                KILL: u1,
-                ///  Starts and stops the clock generator cleanly
-                ENABLE: u1,
-                reserved16: u4,
-                ///  This delays the enable signal by up to 3 cycles of the input clock
-                ///  This must be set before the clock is enabled to have any effect
-                PHASE: u2,
-                reserved20: u2,
-                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
-                ///  This can be done at any time
-                NUDGE: u1,
-                padding: u11,
-            }),
-            ///  Clock divisor, can be changed on-the-fly
-            CLK_USB_DIV: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Integer component of the divisor, 0 -> divide by 2^16
-                INT: u2,
-                padding: u22,
-            }),
-            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
-            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
-            CLK_USB_SELECTED: u32,
-            ///  Clock control, can be changed on-the-fly (except for auxsrc)
-            CLK_ADC_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved5: u5,
-                ///  Selects the auxiliary clock source, will glitch when switching
-                AUXSRC: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        clksrc_pll_usb = 0x0,
-                        clksrc_pll_sys = 0x1,
-                        rosc_clksrc_ph = 0x2,
-                        xosc_clksrc = 0x3,
-                        clksrc_gpin0 = 0x4,
-                        clksrc_gpin1 = 0x5,
-                        _,
-                    },
-                },
-                reserved10: u2,
-                ///  Asynchronously kills the clock generator
-                KILL: u1,
-                ///  Starts and stops the clock generator cleanly
-                ENABLE: u1,
-                reserved16: u4,
-                ///  This delays the enable signal by up to 3 cycles of the input clock
-                ///  This must be set before the clock is enabled to have any effect
-                PHASE: u2,
-                reserved20: u2,
-                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
-                ///  This can be done at any time
-                NUDGE: u1,
-                padding: u11,
-            }),
-            ///  Clock divisor, can be changed on-the-fly
-            CLK_ADC_DIV: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Integer component of the divisor, 0 -> divide by 2^16
-                INT: u2,
-                padding: u22,
-            }),
-            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
-            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
-            CLK_ADC_SELECTED: u32,
-            ///  Clock control, can be changed on-the-fly (except for auxsrc)
-            CLK_RTC_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved5: u5,
-                ///  Selects the auxiliary clock source, will glitch when switching
-                AUXSRC: packed union {
-                    raw: u3,
-                    value: enum(u3) {
-                        clksrc_pll_usb = 0x0,
-                        clksrc_pll_sys = 0x1,
-                        rosc_clksrc_ph = 0x2,
-                        xosc_clksrc = 0x3,
-                        clksrc_gpin0 = 0x4,
-                        clksrc_gpin1 = 0x5,
-                        _,
-                    },
-                },
-                reserved10: u2,
-                ///  Asynchronously kills the clock generator
-                KILL: u1,
-                ///  Starts and stops the clock generator cleanly
-                ENABLE: u1,
-                reserved16: u4,
-                ///  This delays the enable signal by up to 3 cycles of the input clock
-                ///  This must be set before the clock is enabled to have any effect
-                PHASE: u2,
-                reserved20: u2,
-                ///  An edge on this signal shifts the phase of the output by 1 cycle of the input clock
-                ///  This can be done at any time
-                NUDGE: u1,
-                padding: u11,
-            }),
-            ///  Clock divisor, can be changed on-the-fly
-            CLK_RTC_DIV: mmio.Mmio(packed struct(u32) {
-                ///  Fractional component of the divisor
-                FRAC: u8,
-                ///  Integer component of the divisor, 0 -> divide by 2^16
-                INT: u24,
-            }),
-            ///  Indicates which SRC is currently selected by the glitchless mux (one-hot).
-            ///  This slice does not have a glitchless mux (only the AUX_SRC field is present, not SRC) so this register is hardwired to 0x1.
-            CLK_RTC_SELECTED: u32,
-            CLK_SYS_RESUS_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  This is expressed as a number of clk_ref cycles
-                ///  and must be >= 2x clk_ref_freq/min_clk_tst_freq
-                TIMEOUT: u8,
-                ///  Enable resus
-                ENABLE: u1,
-                reserved12: u3,
-                ///  Force a resus, for test purposes only
-                FRCE: u1,
-                reserved16: u3,
-                ///  For clearing the resus after the fault that triggered it has been corrected
-                CLEAR: u1,
-                padding: u15,
-            }),
-            CLK_SYS_RESUS_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  Clock has been resuscitated, correct the error then send ctrl_clear=1
-                RESUSSED: u1,
-                padding: u31,
-            }),
-            ///  Reference clock frequency in kHz
-            FC0_REF_KHZ: mmio.Mmio(packed struct(u32) {
-                FC0_REF_KHZ: u20,
-                padding: u12,
-            }),
-            ///  Minimum pass frequency in kHz. This is optional. Set to 0 if you are not using the pass/fail flags
-            FC0_MIN_KHZ: mmio.Mmio(packed struct(u32) {
-                FC0_MIN_KHZ: u25,
-                padding: u7,
-            }),
-            ///  Maximum pass frequency in kHz. This is optional. Set to 0x1ffffff if you are not using the pass/fail flags
-            FC0_MAX_KHZ: mmio.Mmio(packed struct(u32) {
-                FC0_MAX_KHZ: u25,
-                padding: u7,
-            }),
-            ///  Delays the start of frequency counting to allow the mux to settle
-            ///  Delay is measured in multiples of the reference clock period
-            FC0_DELAY: mmio.Mmio(packed struct(u32) {
-                FC0_DELAY: u3,
-                padding: u29,
-            }),
-            ///  The test interval is 0.98us * 2**interval, but let's call it 1us * 2**interval
-            ///  The default gives a test interval of 250us
-            FC0_INTERVAL: mmio.Mmio(packed struct(u32) {
-                FC0_INTERVAL: u4,
-                padding: u28,
-            }),
-            ///  Clock sent to frequency counter, set to 0 when not required
-            ///  Writing to this register initiates the frequency count
-            FC0_SRC: mmio.Mmio(packed struct(u32) {
-                FC0_SRC: packed union {
-                    raw: u8,
-                    value: enum(u8) {
-                        NULL = 0x0,
-                        pll_sys_clksrc_primary = 0x1,
-                        pll_usb_clksrc_primary = 0x2,
-                        rosc_clksrc = 0x3,
-                        rosc_clksrc_ph = 0x4,
-                        xosc_clksrc = 0x5,
-                        clksrc_gpin0 = 0x6,
-                        clksrc_gpin1 = 0x7,
-                        clk_ref = 0x8,
-                        clk_sys = 0x9,
-                        clk_peri = 0xa,
-                        clk_usb = 0xb,
-                        clk_adc = 0xc,
-                        clk_rtc = 0xd,
-                        _,
-                    },
-                },
-                padding: u24,
-            }),
-            ///  Frequency counter status
-            FC0_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  Test passed
-                PASS: u1,
-                reserved4: u3,
-                ///  Test complete
-                DONE: u1,
-                reserved8: u3,
-                ///  Test running
-                RUNNING: u1,
-                reserved12: u3,
-                ///  Waiting for test clock to start
-                WAITING: u1,
-                reserved16: u3,
-                ///  Test failed
-                FAIL: u1,
-                reserved20: u3,
-                ///  Test clock slower than expected, only valid when status_done=1
-                SLOW: u1,
-                reserved24: u3,
-                ///  Test clock faster than expected, only valid when status_done=1
-                FAST: u1,
-                reserved28: u3,
-                ///  Test clock stopped during test
-                DIED: u1,
-                padding: u3,
-            }),
-            ///  Result of frequency measurement, only valid when status_done=1
-            FC0_RESULT: mmio.Mmio(packed struct(u32) {
-                FRAC: u5,
-                KHZ: u25,
-                padding: u2,
-            }),
-            ///  enable clock in wake mode
-            WAKE_EN0: mmio.Mmio(packed struct(u32) {
-                clk_sys_clocks: u1,
-                clk_adc_adc: u1,
-                clk_sys_adc: u1,
-                clk_sys_busctrl: u1,
-                clk_sys_busfabric: u1,
-                clk_sys_dma: u1,
-                clk_sys_i2c0: u1,
-                clk_sys_i2c1: u1,
-                clk_sys_io: u1,
-                clk_sys_jtag: u1,
-                clk_sys_vreg_and_chip_reset: u1,
-                clk_sys_pads: u1,
-                clk_sys_pio0: u1,
-                clk_sys_pio1: u1,
-                clk_sys_pll_sys: u1,
-                clk_sys_pll_usb: u1,
-                clk_sys_psm: u1,
-                clk_sys_pwm: u1,
-                clk_sys_resets: u1,
-                clk_sys_rom: u1,
-                clk_sys_rosc: u1,
-                clk_rtc_rtc: u1,
-                clk_sys_rtc: u1,
-                clk_sys_sio: u1,
-                clk_peri_spi0: u1,
-                clk_sys_spi0: u1,
-                clk_peri_spi1: u1,
-                clk_sys_spi1: u1,
-                clk_sys_sram0: u1,
-                clk_sys_sram1: u1,
-                clk_sys_sram2: u1,
-                clk_sys_sram3: u1,
-            }),
-            ///  enable clock in wake mode
-            WAKE_EN1: mmio.Mmio(packed struct(u32) {
-                clk_sys_sram4: u1,
-                clk_sys_sram5: u1,
-                clk_sys_syscfg: u1,
-                clk_sys_sysinfo: u1,
-                clk_sys_tbman: u1,
-                clk_sys_timer: u1,
-                clk_peri_uart0: u1,
-                clk_sys_uart0: u1,
-                clk_peri_uart1: u1,
-                clk_sys_uart1: u1,
-                clk_sys_usbctrl: u1,
-                clk_usb_usbctrl: u1,
-                clk_sys_watchdog: u1,
-                clk_sys_xip: u1,
-                clk_sys_xosc: u1,
-                padding: u17,
-            }),
-            ///  enable clock in sleep mode
-            SLEEP_EN0: mmio.Mmio(packed struct(u32) {
-                clk_sys_clocks: u1,
-                clk_adc_adc: u1,
-                clk_sys_adc: u1,
-                clk_sys_busctrl: u1,
-                clk_sys_busfabric: u1,
-                clk_sys_dma: u1,
-                clk_sys_i2c0: u1,
-                clk_sys_i2c1: u1,
-                clk_sys_io: u1,
-                clk_sys_jtag: u1,
-                clk_sys_vreg_and_chip_reset: u1,
-                clk_sys_pads: u1,
-                clk_sys_pio0: u1,
-                clk_sys_pio1: u1,
-                clk_sys_pll_sys: u1,
-                clk_sys_pll_usb: u1,
-                clk_sys_psm: u1,
-                clk_sys_pwm: u1,
-                clk_sys_resets: u1,
-                clk_sys_rom: u1,
-                clk_sys_rosc: u1,
-                clk_rtc_rtc: u1,
-                clk_sys_rtc: u1,
-                clk_sys_sio: u1,
-                clk_peri_spi0: u1,
-                clk_sys_spi0: u1,
-                clk_peri_spi1: u1,
-                clk_sys_spi1: u1,
-                clk_sys_sram0: u1,
-                clk_sys_sram1: u1,
-                clk_sys_sram2: u1,
-                clk_sys_sram3: u1,
-            }),
-            ///  enable clock in sleep mode
-            SLEEP_EN1: mmio.Mmio(packed struct(u32) {
-                clk_sys_sram4: u1,
-                clk_sys_sram5: u1,
-                clk_sys_syscfg: u1,
-                clk_sys_sysinfo: u1,
-                clk_sys_tbman: u1,
-                clk_sys_timer: u1,
-                clk_peri_uart0: u1,
-                clk_sys_uart0: u1,
-                clk_peri_uart1: u1,
-                clk_sys_uart1: u1,
-                clk_sys_usbctrl: u1,
-                clk_usb_usbctrl: u1,
-                clk_sys_watchdog: u1,
-                clk_sys_xip: u1,
-                clk_sys_xosc: u1,
-                padding: u17,
-            }),
-            ///  indicates the state of the clock enable
-            ENABLED0: mmio.Mmio(packed struct(u32) {
-                clk_sys_clocks: u1,
-                clk_adc_adc: u1,
-                clk_sys_adc: u1,
-                clk_sys_busctrl: u1,
-                clk_sys_busfabric: u1,
-                clk_sys_dma: u1,
-                clk_sys_i2c0: u1,
-                clk_sys_i2c1: u1,
-                clk_sys_io: u1,
-                clk_sys_jtag: u1,
-                clk_sys_vreg_and_chip_reset: u1,
-                clk_sys_pads: u1,
-                clk_sys_pio0: u1,
-                clk_sys_pio1: u1,
-                clk_sys_pll_sys: u1,
-                clk_sys_pll_usb: u1,
-                clk_sys_psm: u1,
-                clk_sys_pwm: u1,
-                clk_sys_resets: u1,
-                clk_sys_rom: u1,
-                clk_sys_rosc: u1,
-                clk_rtc_rtc: u1,
-                clk_sys_rtc: u1,
-                clk_sys_sio: u1,
-                clk_peri_spi0: u1,
-                clk_sys_spi0: u1,
-                clk_peri_spi1: u1,
-                clk_sys_spi1: u1,
-                clk_sys_sram0: u1,
-                clk_sys_sram1: u1,
-                clk_sys_sram2: u1,
-                clk_sys_sram3: u1,
-            }),
-            ///  indicates the state of the clock enable
-            ENABLED1: mmio.Mmio(packed struct(u32) {
-                clk_sys_sram4: u1,
-                clk_sys_sram5: u1,
-                clk_sys_syscfg: u1,
-                clk_sys_sysinfo: u1,
-                clk_sys_tbman: u1,
-                clk_sys_timer: u1,
-                clk_peri_uart0: u1,
-                clk_sys_uart0: u1,
-                clk_peri_uart1: u1,
-                clk_sys_uart1: u1,
-                clk_sys_usbctrl: u1,
-                clk_usb_usbctrl: u1,
-                clk_sys_watchdog: u1,
-                clk_sys_xip: u1,
-                clk_sys_xosc: u1,
-                padding: u17,
-            }),
-            ///  Raw Interrupts
-            INTR: mmio.Mmio(packed struct(u32) {
-                CLK_SYS_RESUS: u1,
-                padding: u31,
-            }),
-            ///  Interrupt Enable
-            INTE: mmio.Mmio(packed struct(u32) {
-                CLK_SYS_RESUS: u1,
-                padding: u31,
-            }),
-            ///  Interrupt Force
-            INTF: mmio.Mmio(packed struct(u32) {
-                CLK_SYS_RESUS: u1,
-                padding: u31,
-            }),
-            ///  Interrupt status after masking & forcing
-            INTS: mmio.Mmio(packed struct(u32) {
-                CLK_SYS_RESUS: u1,
-                padding: u31,
-            }),
-        };
-
-        pub const RESETS = extern struct {
-            ///  Reset control. If a bit is set it means the peripheral is in reset. 0 means the peripheral's reset is deasserted.
-            RESET: mmio.Mmio(packed struct(u32) {
-                adc: u1,
-                busctrl: u1,
-                dma: u1,
-                i2c0: u1,
-                i2c1: u1,
-                io_bank0: u1,
-                io_qspi: u1,
-                jtag: u1,
-                pads_bank0: u1,
-                pads_qspi: u1,
-                pio0: u1,
-                pio1: u1,
-                pll_sys: u1,
-                pll_usb: u1,
-                pwm: u1,
-                rtc: u1,
-                spi0: u1,
-                spi1: u1,
-                syscfg: u1,
-                sysinfo: u1,
-                tbman: u1,
-                timer: u1,
-                uart0: u1,
-                uart1: u1,
-                usbctrl: u1,
-                padding: u7,
-            }),
-            ///  Watchdog select. If a bit is set then the watchdog will reset this peripheral when the watchdog fires.
-            WDSEL: mmio.Mmio(packed struct(u32) {
-                adc: u1,
-                busctrl: u1,
-                dma: u1,
-                i2c0: u1,
-                i2c1: u1,
-                io_bank0: u1,
-                io_qspi: u1,
-                jtag: u1,
-                pads_bank0: u1,
-                pads_qspi: u1,
-                pio0: u1,
-                pio1: u1,
-                pll_sys: u1,
-                pll_usb: u1,
-                pwm: u1,
-                rtc: u1,
-                spi0: u1,
-                spi1: u1,
-                syscfg: u1,
-                sysinfo: u1,
-                tbman: u1,
-                timer: u1,
-                uart0: u1,
-                uart1: u1,
-                usbctrl: u1,
-                padding: u7,
-            }),
-            ///  Reset done. If a bit is set then a reset done signal has been returned by the peripheral. This indicates that the peripheral's registers are ready to be accessed.
-            RESET_DONE: mmio.Mmio(packed struct(u32) {
-                adc: u1,
-                busctrl: u1,
-                dma: u1,
-                i2c0: u1,
-                i2c1: u1,
-                io_bank0: u1,
-                io_qspi: u1,
-                jtag: u1,
-                pads_bank0: u1,
-                pads_qspi: u1,
-                pio0: u1,
-                pio1: u1,
-                pll_sys: u1,
-                pll_usb: u1,
-                pwm: u1,
-                rtc: u1,
-                spi0: u1,
-                spi1: u1,
-                syscfg: u1,
-                sysinfo: u1,
-                tbman: u1,
-                timer: u1,
-                uart0: u1,
-                uart1: u1,
-                usbctrl: u1,
-                padding: u7,
-            }),
-        };
-
-        pub const PSM = extern struct {
-            ///  Force block out of reset (i.e. power it on)
-            FRCE_ON: mmio.Mmio(packed struct(u32) {
-                rosc: u1,
-                xosc: u1,
-                clocks: u1,
-                resets: u1,
-                busfabric: u1,
-                rom: u1,
-                sram0: u1,
-                sram1: u1,
-                sram2: u1,
-                sram3: u1,
-                sram4: u1,
-                sram5: u1,
-                xip: u1,
-                vreg_and_chip_reset: u1,
-                sio: u1,
-                proc0: u1,
-                proc1: u1,
-                padding: u15,
-            }),
-            ///  Force into reset (i.e. power it off)
-            FRCE_OFF: mmio.Mmio(packed struct(u32) {
-                rosc: u1,
-                xosc: u1,
-                clocks: u1,
-                resets: u1,
-                busfabric: u1,
-                rom: u1,
-                sram0: u1,
-                sram1: u1,
-                sram2: u1,
-                sram3: u1,
-                sram4: u1,
-                sram5: u1,
-                xip: u1,
-                vreg_and_chip_reset: u1,
-                sio: u1,
-                proc0: u1,
-                proc1: u1,
-                padding: u15,
-            }),
-            ///  Set to 1 if this peripheral should be reset when the watchdog fires.
-            WDSEL: mmio.Mmio(packed struct(u32) {
-                rosc: u1,
-                xosc: u1,
-                clocks: u1,
-                resets: u1,
-                busfabric: u1,
-                rom: u1,
-                sram0: u1,
-                sram1: u1,
-                sram2: u1,
-                sram3: u1,
-                sram4: u1,
-                sram5: u1,
-                xip: u1,
-                vreg_and_chip_reset: u1,
-                sio: u1,
-                proc0: u1,
-                proc1: u1,
-                padding: u15,
-            }),
-            ///  Indicates the peripheral's registers are ready to access.
-            DONE: mmio.Mmio(packed struct(u32) {
-                rosc: u1,
-                xosc: u1,
-                clocks: u1,
-                resets: u1,
-                busfabric: u1,
-                rom: u1,
-                sram0: u1,
-                sram1: u1,
-                sram2: u1,
-                sram3: u1,
-                sram4: u1,
-                sram5: u1,
-                xip: u1,
-                vreg_and_chip_reset: u1,
-                sio: u1,
-                proc0: u1,
-                proc1: u1,
-                padding: u15,
-            }),
-        };
-
-        pub const IO_BANK0 = extern struct {
-            ///  GPIO status
-            GPIO0_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO0_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        jtag_tck = 0x0,
-                        spi0_rx = 0x1,
-                        uart0_tx = 0x2,
-                        i2c0_sda = 0x3,
-                        pwm_a_0 = 0x4,
-                        sio_0 = 0x5,
-                        pio0_0 = 0x6,
-                        pio1_0 = 0x7,
-                        usb_muxing_overcurr_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO1_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO1_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        jtag_tms = 0x0,
-                        spi0_ss_n = 0x1,
-                        uart0_rx = 0x2,
-                        i2c0_scl = 0x3,
-                        pwm_b_0 = 0x4,
-                        sio_1 = 0x5,
-                        pio0_1 = 0x6,
-                        pio1_1 = 0x7,
-                        usb_muxing_vbus_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO2_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO2_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        jtag_tdi = 0x0,
-                        spi0_sclk = 0x1,
-                        uart0_cts = 0x2,
-                        i2c1_sda = 0x3,
-                        pwm_a_1 = 0x4,
-                        sio_2 = 0x5,
-                        pio0_2 = 0x6,
-                        pio1_2 = 0x7,
-                        usb_muxing_vbus_en = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO3_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO3_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        jtag_tdo = 0x0,
-                        spi0_tx = 0x1,
-                        uart0_rts = 0x2,
-                        i2c1_scl = 0x3,
-                        pwm_b_1 = 0x4,
-                        sio_3 = 0x5,
-                        pio0_3 = 0x6,
-                        pio1_3 = 0x7,
-                        usb_muxing_overcurr_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO4_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO4_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_rx = 0x1,
-                        uart1_tx = 0x2,
-                        i2c0_sda = 0x3,
-                        pwm_a_2 = 0x4,
-                        sio_4 = 0x5,
-                        pio0_4 = 0x6,
-                        pio1_4 = 0x7,
-                        usb_muxing_vbus_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO5_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO5_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_ss_n = 0x1,
-                        uart1_rx = 0x2,
-                        i2c0_scl = 0x3,
-                        pwm_b_2 = 0x4,
-                        sio_5 = 0x5,
-                        pio0_5 = 0x6,
-                        pio1_5 = 0x7,
-                        usb_muxing_vbus_en = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO6_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO6_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_sclk = 0x1,
-                        uart1_cts = 0x2,
-                        i2c1_sda = 0x3,
-                        pwm_a_3 = 0x4,
-                        sio_6 = 0x5,
-                        pio0_6 = 0x6,
-                        pio1_6 = 0x7,
-                        usb_muxing_extphy_softcon = 0x8,
-                        usb_muxing_overcurr_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO7_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO7_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_tx = 0x1,
-                        uart1_rts = 0x2,
-                        i2c1_scl = 0x3,
-                        pwm_b_3 = 0x4,
-                        sio_7 = 0x5,
-                        pio0_7 = 0x6,
-                        pio1_7 = 0x7,
-                        usb_muxing_extphy_oe_n = 0x8,
-                        usb_muxing_vbus_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO8_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO8_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_rx = 0x1,
-                        uart1_tx = 0x2,
-                        i2c0_sda = 0x3,
-                        pwm_a_4 = 0x4,
-                        sio_8 = 0x5,
-                        pio0_8 = 0x6,
-                        pio1_8 = 0x7,
-                        usb_muxing_extphy_rcv = 0x8,
-                        usb_muxing_vbus_en = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO9_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO9_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_ss_n = 0x1,
-                        uart1_rx = 0x2,
-                        i2c0_scl = 0x3,
-                        pwm_b_4 = 0x4,
-                        sio_9 = 0x5,
-                        pio0_9 = 0x6,
-                        pio1_9 = 0x7,
-                        usb_muxing_extphy_vp = 0x8,
-                        usb_muxing_overcurr_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO10_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO10_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_sclk = 0x1,
-                        uart1_cts = 0x2,
-                        i2c1_sda = 0x3,
-                        pwm_a_5 = 0x4,
-                        sio_10 = 0x5,
-                        pio0_10 = 0x6,
-                        pio1_10 = 0x7,
-                        usb_muxing_extphy_vm = 0x8,
-                        usb_muxing_vbus_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO11_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO11_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_tx = 0x1,
-                        uart1_rts = 0x2,
-                        i2c1_scl = 0x3,
-                        pwm_b_5 = 0x4,
-                        sio_11 = 0x5,
-                        pio0_11 = 0x6,
-                        pio1_11 = 0x7,
-                        usb_muxing_extphy_suspnd = 0x8,
-                        usb_muxing_vbus_en = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO12_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO12_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_rx = 0x1,
-                        uart0_tx = 0x2,
-                        i2c0_sda = 0x3,
-                        pwm_a_6 = 0x4,
-                        sio_12 = 0x5,
-                        pio0_12 = 0x6,
-                        pio1_12 = 0x7,
-                        usb_muxing_extphy_speed = 0x8,
-                        usb_muxing_overcurr_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO13_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO13_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_ss_n = 0x1,
-                        uart0_rx = 0x2,
-                        i2c0_scl = 0x3,
-                        pwm_b_6 = 0x4,
-                        sio_13 = 0x5,
-                        pio0_13 = 0x6,
-                        pio1_13 = 0x7,
-                        usb_muxing_extphy_vpo = 0x8,
-                        usb_muxing_vbus_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO14_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO14_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_sclk = 0x1,
-                        uart0_cts = 0x2,
-                        i2c1_sda = 0x3,
-                        pwm_a_7 = 0x4,
-                        sio_14 = 0x5,
-                        pio0_14 = 0x6,
-                        pio1_14 = 0x7,
-                        usb_muxing_extphy_vmo = 0x8,
-                        usb_muxing_vbus_en = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO15_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO15_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_tx = 0x1,
-                        uart0_rts = 0x2,
-                        i2c1_scl = 0x3,
-                        pwm_b_7 = 0x4,
-                        sio_15 = 0x5,
-                        pio0_15 = 0x6,
-                        pio1_15 = 0x7,
-                        usb_muxing_digital_dp = 0x8,
-                        usb_muxing_overcurr_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO16_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO16_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_rx = 0x1,
-                        uart0_tx = 0x2,
-                        i2c0_sda = 0x3,
-                        pwm_a_0 = 0x4,
-                        sio_16 = 0x5,
-                        pio0_16 = 0x6,
-                        pio1_16 = 0x7,
-                        usb_muxing_digital_dm = 0x8,
-                        usb_muxing_vbus_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO17_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO17_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_ss_n = 0x1,
-                        uart0_rx = 0x2,
-                        i2c0_scl = 0x3,
-                        pwm_b_0 = 0x4,
-                        sio_17 = 0x5,
-                        pio0_17 = 0x6,
-                        pio1_17 = 0x7,
-                        usb_muxing_vbus_en = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO18_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO18_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_sclk = 0x1,
-                        uart0_cts = 0x2,
-                        i2c1_sda = 0x3,
-                        pwm_a_1 = 0x4,
-                        sio_18 = 0x5,
-                        pio0_18 = 0x6,
-                        pio1_18 = 0x7,
-                        usb_muxing_overcurr_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO19_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO19_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_tx = 0x1,
-                        uart0_rts = 0x2,
-                        i2c1_scl = 0x3,
-                        pwm_b_1 = 0x4,
-                        sio_19 = 0x5,
-                        pio0_19 = 0x6,
-                        pio1_19 = 0x7,
-                        usb_muxing_vbus_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO20_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO20_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_rx = 0x1,
-                        uart1_tx = 0x2,
-                        i2c0_sda = 0x3,
-                        pwm_a_2 = 0x4,
-                        sio_20 = 0x5,
-                        pio0_20 = 0x6,
-                        pio1_20 = 0x7,
-                        clocks_gpin_0 = 0x8,
-                        usb_muxing_vbus_en = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO21_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO21_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_ss_n = 0x1,
-                        uart1_rx = 0x2,
-                        i2c0_scl = 0x3,
-                        pwm_b_2 = 0x4,
-                        sio_21 = 0x5,
-                        pio0_21 = 0x6,
-                        pio1_21 = 0x7,
-                        clocks_gpout_0 = 0x8,
-                        usb_muxing_overcurr_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO22_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO22_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_sclk = 0x1,
-                        uart1_cts = 0x2,
-                        i2c1_sda = 0x3,
-                        pwm_a_3 = 0x4,
-                        sio_22 = 0x5,
-                        pio0_22 = 0x6,
-                        pio1_22 = 0x7,
-                        clocks_gpin_1 = 0x8,
-                        usb_muxing_vbus_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO23_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO23_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi0_tx = 0x1,
-                        uart1_rts = 0x2,
-                        i2c1_scl = 0x3,
-                        pwm_b_3 = 0x4,
-                        sio_23 = 0x5,
-                        pio0_23 = 0x6,
-                        pio1_23 = 0x7,
-                        clocks_gpout_1 = 0x8,
-                        usb_muxing_vbus_en = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO24_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO24_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_rx = 0x1,
-                        uart1_tx = 0x2,
-                        i2c0_sda = 0x3,
-                        pwm_a_4 = 0x4,
-                        sio_24 = 0x5,
-                        pio0_24 = 0x6,
-                        pio1_24 = 0x7,
-                        clocks_gpout_2 = 0x8,
-                        usb_muxing_overcurr_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO25_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO25_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_ss_n = 0x1,
-                        uart1_rx = 0x2,
-                        i2c0_scl = 0x3,
-                        pwm_b_4 = 0x4,
-                        sio_25 = 0x5,
-                        pio0_25 = 0x6,
-                        pio1_25 = 0x7,
-                        clocks_gpout_3 = 0x8,
-                        usb_muxing_vbus_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO26_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO26_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_sclk = 0x1,
-                        uart1_cts = 0x2,
-                        i2c1_sda = 0x3,
-                        pwm_a_5 = 0x4,
-                        sio_26 = 0x5,
-                        pio0_26 = 0x6,
-                        pio1_26 = 0x7,
-                        usb_muxing_vbus_en = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO27_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO27_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_tx = 0x1,
-                        uart1_rts = 0x2,
-                        i2c1_scl = 0x3,
-                        pwm_b_5 = 0x4,
-                        sio_27 = 0x5,
-                        pio0_27 = 0x6,
-                        pio1_27 = 0x7,
-                        usb_muxing_overcurr_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO28_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO28_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_rx = 0x1,
-                        uart0_tx = 0x2,
-                        i2c0_sda = 0x3,
-                        pwm_a_6 = 0x4,
-                        sio_28 = 0x5,
-                        pio0_28 = 0x6,
-                        pio1_28 = 0x7,
-                        usb_muxing_vbus_detect = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO29_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO29_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        spi1_ss_n = 0x1,
-                        uart0_rx = 0x2,
-                        i2c0_scl = 0x3,
-                        pwm_b_6 = 0x4,
-                        sio_29 = 0x5,
-                        pio0_29 = 0x6,
-                        pio1_29 = 0x7,
-                        usb_muxing_vbus_en = 0x9,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  Raw Interrupts
-            INTR0: mmio.Mmio(packed struct(u32) {
-                GPIO0_LEVEL_LOW: u1,
-                GPIO0_LEVEL_HIGH: u1,
-                GPIO0_EDGE_LOW: u1,
-                GPIO0_EDGE_HIGH: u1,
-                GPIO1_LEVEL_LOW: u1,
-                GPIO1_LEVEL_HIGH: u1,
-                GPIO1_EDGE_LOW: u1,
-                GPIO1_EDGE_HIGH: u1,
-                GPIO2_LEVEL_LOW: u1,
-                GPIO2_LEVEL_HIGH: u1,
-                GPIO2_EDGE_LOW: u1,
-                GPIO2_EDGE_HIGH: u1,
-                GPIO3_LEVEL_LOW: u1,
-                GPIO3_LEVEL_HIGH: u1,
-                GPIO3_EDGE_LOW: u1,
-                GPIO3_EDGE_HIGH: u1,
-                GPIO4_LEVEL_LOW: u1,
-                GPIO4_LEVEL_HIGH: u1,
-                GPIO4_EDGE_LOW: u1,
-                GPIO4_EDGE_HIGH: u1,
-                GPIO5_LEVEL_LOW: u1,
-                GPIO5_LEVEL_HIGH: u1,
-                GPIO5_EDGE_LOW: u1,
-                GPIO5_EDGE_HIGH: u1,
-                GPIO6_LEVEL_LOW: u1,
-                GPIO6_LEVEL_HIGH: u1,
-                GPIO6_EDGE_LOW: u1,
-                GPIO6_EDGE_HIGH: u1,
-                GPIO7_LEVEL_LOW: u1,
-                GPIO7_LEVEL_HIGH: u1,
-                GPIO7_EDGE_LOW: u1,
-                GPIO7_EDGE_HIGH: u1,
-            }),
-            ///  Raw Interrupts
-            INTR1: mmio.Mmio(packed struct(u32) {
-                GPIO8_LEVEL_LOW: u1,
-                GPIO8_LEVEL_HIGH: u1,
-                GPIO8_EDGE_LOW: u1,
-                GPIO8_EDGE_HIGH: u1,
-                GPIO9_LEVEL_LOW: u1,
-                GPIO9_LEVEL_HIGH: u1,
-                GPIO9_EDGE_LOW: u1,
-                GPIO9_EDGE_HIGH: u1,
-                GPIO10_LEVEL_LOW: u1,
-                GPIO10_LEVEL_HIGH: u1,
-                GPIO10_EDGE_LOW: u1,
-                GPIO10_EDGE_HIGH: u1,
-                GPIO11_LEVEL_LOW: u1,
-                GPIO11_LEVEL_HIGH: u1,
-                GPIO11_EDGE_LOW: u1,
-                GPIO11_EDGE_HIGH: u1,
-                GPIO12_LEVEL_LOW: u1,
-                GPIO12_LEVEL_HIGH: u1,
-                GPIO12_EDGE_LOW: u1,
-                GPIO12_EDGE_HIGH: u1,
-                GPIO13_LEVEL_LOW: u1,
-                GPIO13_LEVEL_HIGH: u1,
-                GPIO13_EDGE_LOW: u1,
-                GPIO13_EDGE_HIGH: u1,
-                GPIO14_LEVEL_LOW: u1,
-                GPIO14_LEVEL_HIGH: u1,
-                GPIO14_EDGE_LOW: u1,
-                GPIO14_EDGE_HIGH: u1,
-                GPIO15_LEVEL_LOW: u1,
-                GPIO15_LEVEL_HIGH: u1,
-                GPIO15_EDGE_LOW: u1,
-                GPIO15_EDGE_HIGH: u1,
-            }),
-            ///  Raw Interrupts
-            INTR2: mmio.Mmio(packed struct(u32) {
-                GPIO16_LEVEL_LOW: u1,
-                GPIO16_LEVEL_HIGH: u1,
-                GPIO16_EDGE_LOW: u1,
-                GPIO16_EDGE_HIGH: u1,
-                GPIO17_LEVEL_LOW: u1,
-                GPIO17_LEVEL_HIGH: u1,
-                GPIO17_EDGE_LOW: u1,
-                GPIO17_EDGE_HIGH: u1,
-                GPIO18_LEVEL_LOW: u1,
-                GPIO18_LEVEL_HIGH: u1,
-                GPIO18_EDGE_LOW: u1,
-                GPIO18_EDGE_HIGH: u1,
-                GPIO19_LEVEL_LOW: u1,
-                GPIO19_LEVEL_HIGH: u1,
-                GPIO19_EDGE_LOW: u1,
-                GPIO19_EDGE_HIGH: u1,
-                GPIO20_LEVEL_LOW: u1,
-                GPIO20_LEVEL_HIGH: u1,
-                GPIO20_EDGE_LOW: u1,
-                GPIO20_EDGE_HIGH: u1,
-                GPIO21_LEVEL_LOW: u1,
-                GPIO21_LEVEL_HIGH: u1,
-                GPIO21_EDGE_LOW: u1,
-                GPIO21_EDGE_HIGH: u1,
-                GPIO22_LEVEL_LOW: u1,
-                GPIO22_LEVEL_HIGH: u1,
-                GPIO22_EDGE_LOW: u1,
-                GPIO22_EDGE_HIGH: u1,
-                GPIO23_LEVEL_LOW: u1,
-                GPIO23_LEVEL_HIGH: u1,
-                GPIO23_EDGE_LOW: u1,
-                GPIO23_EDGE_HIGH: u1,
-            }),
-            ///  Raw Interrupts
-            INTR3: mmio.Mmio(packed struct(u32) {
-                GPIO24_LEVEL_LOW: u1,
-                GPIO24_LEVEL_HIGH: u1,
-                GPIO24_EDGE_LOW: u1,
-                GPIO24_EDGE_HIGH: u1,
-                GPIO25_LEVEL_LOW: u1,
-                GPIO25_LEVEL_HIGH: u1,
-                GPIO25_EDGE_LOW: u1,
-                GPIO25_EDGE_HIGH: u1,
-                GPIO26_LEVEL_LOW: u1,
-                GPIO26_LEVEL_HIGH: u1,
-                GPIO26_EDGE_LOW: u1,
-                GPIO26_EDGE_HIGH: u1,
-                GPIO27_LEVEL_LOW: u1,
-                GPIO27_LEVEL_HIGH: u1,
-                GPIO27_EDGE_LOW: u1,
-                GPIO27_EDGE_HIGH: u1,
-                GPIO28_LEVEL_LOW: u1,
-                GPIO28_LEVEL_HIGH: u1,
-                GPIO28_EDGE_LOW: u1,
-                GPIO28_EDGE_HIGH: u1,
-                GPIO29_LEVEL_LOW: u1,
-                GPIO29_LEVEL_HIGH: u1,
-                GPIO29_EDGE_LOW: u1,
-                GPIO29_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Enable for proc0
-            PROC0_INTE0: mmio.Mmio(packed struct(u32) {
-                GPIO0_LEVEL_LOW: u1,
-                GPIO0_LEVEL_HIGH: u1,
-                GPIO0_EDGE_LOW: u1,
-                GPIO0_EDGE_HIGH: u1,
-                GPIO1_LEVEL_LOW: u1,
-                GPIO1_LEVEL_HIGH: u1,
-                GPIO1_EDGE_LOW: u1,
-                GPIO1_EDGE_HIGH: u1,
-                GPIO2_LEVEL_LOW: u1,
-                GPIO2_LEVEL_HIGH: u1,
-                GPIO2_EDGE_LOW: u1,
-                GPIO2_EDGE_HIGH: u1,
-                GPIO3_LEVEL_LOW: u1,
-                GPIO3_LEVEL_HIGH: u1,
-                GPIO3_EDGE_LOW: u1,
-                GPIO3_EDGE_HIGH: u1,
-                GPIO4_LEVEL_LOW: u1,
-                GPIO4_LEVEL_HIGH: u1,
-                GPIO4_EDGE_LOW: u1,
-                GPIO4_EDGE_HIGH: u1,
-                GPIO5_LEVEL_LOW: u1,
-                GPIO5_LEVEL_HIGH: u1,
-                GPIO5_EDGE_LOW: u1,
-                GPIO5_EDGE_HIGH: u1,
-                GPIO6_LEVEL_LOW: u1,
-                GPIO6_LEVEL_HIGH: u1,
-                GPIO6_EDGE_LOW: u1,
-                GPIO6_EDGE_HIGH: u1,
-                GPIO7_LEVEL_LOW: u1,
-                GPIO7_LEVEL_HIGH: u1,
-                GPIO7_EDGE_LOW: u1,
-                GPIO7_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Enable for proc0
-            PROC0_INTE1: mmio.Mmio(packed struct(u32) {
-                GPIO8_LEVEL_LOW: u1,
-                GPIO8_LEVEL_HIGH: u1,
-                GPIO8_EDGE_LOW: u1,
-                GPIO8_EDGE_HIGH: u1,
-                GPIO9_LEVEL_LOW: u1,
-                GPIO9_LEVEL_HIGH: u1,
-                GPIO9_EDGE_LOW: u1,
-                GPIO9_EDGE_HIGH: u1,
-                GPIO10_LEVEL_LOW: u1,
-                GPIO10_LEVEL_HIGH: u1,
-                GPIO10_EDGE_LOW: u1,
-                GPIO10_EDGE_HIGH: u1,
-                GPIO11_LEVEL_LOW: u1,
-                GPIO11_LEVEL_HIGH: u1,
-                GPIO11_EDGE_LOW: u1,
-                GPIO11_EDGE_HIGH: u1,
-                GPIO12_LEVEL_LOW: u1,
-                GPIO12_LEVEL_HIGH: u1,
-                GPIO12_EDGE_LOW: u1,
-                GPIO12_EDGE_HIGH: u1,
-                GPIO13_LEVEL_LOW: u1,
-                GPIO13_LEVEL_HIGH: u1,
-                GPIO13_EDGE_LOW: u1,
-                GPIO13_EDGE_HIGH: u1,
-                GPIO14_LEVEL_LOW: u1,
-                GPIO14_LEVEL_HIGH: u1,
-                GPIO14_EDGE_LOW: u1,
-                GPIO14_EDGE_HIGH: u1,
-                GPIO15_LEVEL_LOW: u1,
-                GPIO15_LEVEL_HIGH: u1,
-                GPIO15_EDGE_LOW: u1,
-                GPIO15_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Enable for proc0
-            PROC0_INTE2: mmio.Mmio(packed struct(u32) {
-                GPIO16_LEVEL_LOW: u1,
-                GPIO16_LEVEL_HIGH: u1,
-                GPIO16_EDGE_LOW: u1,
-                GPIO16_EDGE_HIGH: u1,
-                GPIO17_LEVEL_LOW: u1,
-                GPIO17_LEVEL_HIGH: u1,
-                GPIO17_EDGE_LOW: u1,
-                GPIO17_EDGE_HIGH: u1,
-                GPIO18_LEVEL_LOW: u1,
-                GPIO18_LEVEL_HIGH: u1,
-                GPIO18_EDGE_LOW: u1,
-                GPIO18_EDGE_HIGH: u1,
-                GPIO19_LEVEL_LOW: u1,
-                GPIO19_LEVEL_HIGH: u1,
-                GPIO19_EDGE_LOW: u1,
-                GPIO19_EDGE_HIGH: u1,
-                GPIO20_LEVEL_LOW: u1,
-                GPIO20_LEVEL_HIGH: u1,
-                GPIO20_EDGE_LOW: u1,
-                GPIO20_EDGE_HIGH: u1,
-                GPIO21_LEVEL_LOW: u1,
-                GPIO21_LEVEL_HIGH: u1,
-                GPIO21_EDGE_LOW: u1,
-                GPIO21_EDGE_HIGH: u1,
-                GPIO22_LEVEL_LOW: u1,
-                GPIO22_LEVEL_HIGH: u1,
-                GPIO22_EDGE_LOW: u1,
-                GPIO22_EDGE_HIGH: u1,
-                GPIO23_LEVEL_LOW: u1,
-                GPIO23_LEVEL_HIGH: u1,
-                GPIO23_EDGE_LOW: u1,
-                GPIO23_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Enable for proc0
-            PROC0_INTE3: mmio.Mmio(packed struct(u32) {
-                GPIO24_LEVEL_LOW: u1,
-                GPIO24_LEVEL_HIGH: u1,
-                GPIO24_EDGE_LOW: u1,
-                GPIO24_EDGE_HIGH: u1,
-                GPIO25_LEVEL_LOW: u1,
-                GPIO25_LEVEL_HIGH: u1,
-                GPIO25_EDGE_LOW: u1,
-                GPIO25_EDGE_HIGH: u1,
-                GPIO26_LEVEL_LOW: u1,
-                GPIO26_LEVEL_HIGH: u1,
-                GPIO26_EDGE_LOW: u1,
-                GPIO26_EDGE_HIGH: u1,
-                GPIO27_LEVEL_LOW: u1,
-                GPIO27_LEVEL_HIGH: u1,
-                GPIO27_EDGE_LOW: u1,
-                GPIO27_EDGE_HIGH: u1,
-                GPIO28_LEVEL_LOW: u1,
-                GPIO28_LEVEL_HIGH: u1,
-                GPIO28_EDGE_LOW: u1,
-                GPIO28_EDGE_HIGH: u1,
-                GPIO29_LEVEL_LOW: u1,
-                GPIO29_LEVEL_HIGH: u1,
-                GPIO29_EDGE_LOW: u1,
-                GPIO29_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Force for proc0
-            PROC0_INTF0: mmio.Mmio(packed struct(u32) {
-                GPIO0_LEVEL_LOW: u1,
-                GPIO0_LEVEL_HIGH: u1,
-                GPIO0_EDGE_LOW: u1,
-                GPIO0_EDGE_HIGH: u1,
-                GPIO1_LEVEL_LOW: u1,
-                GPIO1_LEVEL_HIGH: u1,
-                GPIO1_EDGE_LOW: u1,
-                GPIO1_EDGE_HIGH: u1,
-                GPIO2_LEVEL_LOW: u1,
-                GPIO2_LEVEL_HIGH: u1,
-                GPIO2_EDGE_LOW: u1,
-                GPIO2_EDGE_HIGH: u1,
-                GPIO3_LEVEL_LOW: u1,
-                GPIO3_LEVEL_HIGH: u1,
-                GPIO3_EDGE_LOW: u1,
-                GPIO3_EDGE_HIGH: u1,
-                GPIO4_LEVEL_LOW: u1,
-                GPIO4_LEVEL_HIGH: u1,
-                GPIO4_EDGE_LOW: u1,
-                GPIO4_EDGE_HIGH: u1,
-                GPIO5_LEVEL_LOW: u1,
-                GPIO5_LEVEL_HIGH: u1,
-                GPIO5_EDGE_LOW: u1,
-                GPIO5_EDGE_HIGH: u1,
-                GPIO6_LEVEL_LOW: u1,
-                GPIO6_LEVEL_HIGH: u1,
-                GPIO6_EDGE_LOW: u1,
-                GPIO6_EDGE_HIGH: u1,
-                GPIO7_LEVEL_LOW: u1,
-                GPIO7_LEVEL_HIGH: u1,
-                GPIO7_EDGE_LOW: u1,
-                GPIO7_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Force for proc0
-            PROC0_INTF1: mmio.Mmio(packed struct(u32) {
-                GPIO8_LEVEL_LOW: u1,
-                GPIO8_LEVEL_HIGH: u1,
-                GPIO8_EDGE_LOW: u1,
-                GPIO8_EDGE_HIGH: u1,
-                GPIO9_LEVEL_LOW: u1,
-                GPIO9_LEVEL_HIGH: u1,
-                GPIO9_EDGE_LOW: u1,
-                GPIO9_EDGE_HIGH: u1,
-                GPIO10_LEVEL_LOW: u1,
-                GPIO10_LEVEL_HIGH: u1,
-                GPIO10_EDGE_LOW: u1,
-                GPIO10_EDGE_HIGH: u1,
-                GPIO11_LEVEL_LOW: u1,
-                GPIO11_LEVEL_HIGH: u1,
-                GPIO11_EDGE_LOW: u1,
-                GPIO11_EDGE_HIGH: u1,
-                GPIO12_LEVEL_LOW: u1,
-                GPIO12_LEVEL_HIGH: u1,
-                GPIO12_EDGE_LOW: u1,
-                GPIO12_EDGE_HIGH: u1,
-                GPIO13_LEVEL_LOW: u1,
-                GPIO13_LEVEL_HIGH: u1,
-                GPIO13_EDGE_LOW: u1,
-                GPIO13_EDGE_HIGH: u1,
-                GPIO14_LEVEL_LOW: u1,
-                GPIO14_LEVEL_HIGH: u1,
-                GPIO14_EDGE_LOW: u1,
-                GPIO14_EDGE_HIGH: u1,
-                GPIO15_LEVEL_LOW: u1,
-                GPIO15_LEVEL_HIGH: u1,
-                GPIO15_EDGE_LOW: u1,
-                GPIO15_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Force for proc0
-            PROC0_INTF2: mmio.Mmio(packed struct(u32) {
-                GPIO16_LEVEL_LOW: u1,
-                GPIO16_LEVEL_HIGH: u1,
-                GPIO16_EDGE_LOW: u1,
-                GPIO16_EDGE_HIGH: u1,
-                GPIO17_LEVEL_LOW: u1,
-                GPIO17_LEVEL_HIGH: u1,
-                GPIO17_EDGE_LOW: u1,
-                GPIO17_EDGE_HIGH: u1,
-                GPIO18_LEVEL_LOW: u1,
-                GPIO18_LEVEL_HIGH: u1,
-                GPIO18_EDGE_LOW: u1,
-                GPIO18_EDGE_HIGH: u1,
-                GPIO19_LEVEL_LOW: u1,
-                GPIO19_LEVEL_HIGH: u1,
-                GPIO19_EDGE_LOW: u1,
-                GPIO19_EDGE_HIGH: u1,
-                GPIO20_LEVEL_LOW: u1,
-                GPIO20_LEVEL_HIGH: u1,
-                GPIO20_EDGE_LOW: u1,
-                GPIO20_EDGE_HIGH: u1,
-                GPIO21_LEVEL_LOW: u1,
-                GPIO21_LEVEL_HIGH: u1,
-                GPIO21_EDGE_LOW: u1,
-                GPIO21_EDGE_HIGH: u1,
-                GPIO22_LEVEL_LOW: u1,
-                GPIO22_LEVEL_HIGH: u1,
-                GPIO22_EDGE_LOW: u1,
-                GPIO22_EDGE_HIGH: u1,
-                GPIO23_LEVEL_LOW: u1,
-                GPIO23_LEVEL_HIGH: u1,
-                GPIO23_EDGE_LOW: u1,
-                GPIO23_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Force for proc0
-            PROC0_INTF3: mmio.Mmio(packed struct(u32) {
-                GPIO24_LEVEL_LOW: u1,
-                GPIO24_LEVEL_HIGH: u1,
-                GPIO24_EDGE_LOW: u1,
-                GPIO24_EDGE_HIGH: u1,
-                GPIO25_LEVEL_LOW: u1,
-                GPIO25_LEVEL_HIGH: u1,
-                GPIO25_EDGE_LOW: u1,
-                GPIO25_EDGE_HIGH: u1,
-                GPIO26_LEVEL_LOW: u1,
-                GPIO26_LEVEL_HIGH: u1,
-                GPIO26_EDGE_LOW: u1,
-                GPIO26_EDGE_HIGH: u1,
-                GPIO27_LEVEL_LOW: u1,
-                GPIO27_LEVEL_HIGH: u1,
-                GPIO27_EDGE_LOW: u1,
-                GPIO27_EDGE_HIGH: u1,
-                GPIO28_LEVEL_LOW: u1,
-                GPIO28_LEVEL_HIGH: u1,
-                GPIO28_EDGE_LOW: u1,
-                GPIO28_EDGE_HIGH: u1,
-                GPIO29_LEVEL_LOW: u1,
-                GPIO29_LEVEL_HIGH: u1,
-                GPIO29_EDGE_LOW: u1,
-                GPIO29_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt status after masking & forcing for proc0
-            PROC0_INTS0: mmio.Mmio(packed struct(u32) {
-                GPIO0_LEVEL_LOW: u1,
-                GPIO0_LEVEL_HIGH: u1,
-                GPIO0_EDGE_LOW: u1,
-                GPIO0_EDGE_HIGH: u1,
-                GPIO1_LEVEL_LOW: u1,
-                GPIO1_LEVEL_HIGH: u1,
-                GPIO1_EDGE_LOW: u1,
-                GPIO1_EDGE_HIGH: u1,
-                GPIO2_LEVEL_LOW: u1,
-                GPIO2_LEVEL_HIGH: u1,
-                GPIO2_EDGE_LOW: u1,
-                GPIO2_EDGE_HIGH: u1,
-                GPIO3_LEVEL_LOW: u1,
-                GPIO3_LEVEL_HIGH: u1,
-                GPIO3_EDGE_LOW: u1,
-                GPIO3_EDGE_HIGH: u1,
-                GPIO4_LEVEL_LOW: u1,
-                GPIO4_LEVEL_HIGH: u1,
-                GPIO4_EDGE_LOW: u1,
-                GPIO4_EDGE_HIGH: u1,
-                GPIO5_LEVEL_LOW: u1,
-                GPIO5_LEVEL_HIGH: u1,
-                GPIO5_EDGE_LOW: u1,
-                GPIO5_EDGE_HIGH: u1,
-                GPIO6_LEVEL_LOW: u1,
-                GPIO6_LEVEL_HIGH: u1,
-                GPIO6_EDGE_LOW: u1,
-                GPIO6_EDGE_HIGH: u1,
-                GPIO7_LEVEL_LOW: u1,
-                GPIO7_LEVEL_HIGH: u1,
-                GPIO7_EDGE_LOW: u1,
-                GPIO7_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt status after masking & forcing for proc0
-            PROC0_INTS1: mmio.Mmio(packed struct(u32) {
-                GPIO8_LEVEL_LOW: u1,
-                GPIO8_LEVEL_HIGH: u1,
-                GPIO8_EDGE_LOW: u1,
-                GPIO8_EDGE_HIGH: u1,
-                GPIO9_LEVEL_LOW: u1,
-                GPIO9_LEVEL_HIGH: u1,
-                GPIO9_EDGE_LOW: u1,
-                GPIO9_EDGE_HIGH: u1,
-                GPIO10_LEVEL_LOW: u1,
-                GPIO10_LEVEL_HIGH: u1,
-                GPIO10_EDGE_LOW: u1,
-                GPIO10_EDGE_HIGH: u1,
-                GPIO11_LEVEL_LOW: u1,
-                GPIO11_LEVEL_HIGH: u1,
-                GPIO11_EDGE_LOW: u1,
-                GPIO11_EDGE_HIGH: u1,
-                GPIO12_LEVEL_LOW: u1,
-                GPIO12_LEVEL_HIGH: u1,
-                GPIO12_EDGE_LOW: u1,
-                GPIO12_EDGE_HIGH: u1,
-                GPIO13_LEVEL_LOW: u1,
-                GPIO13_LEVEL_HIGH: u1,
-                GPIO13_EDGE_LOW: u1,
-                GPIO13_EDGE_HIGH: u1,
-                GPIO14_LEVEL_LOW: u1,
-                GPIO14_LEVEL_HIGH: u1,
-                GPIO14_EDGE_LOW: u1,
-                GPIO14_EDGE_HIGH: u1,
-                GPIO15_LEVEL_LOW: u1,
-                GPIO15_LEVEL_HIGH: u1,
-                GPIO15_EDGE_LOW: u1,
-                GPIO15_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt status after masking & forcing for proc0
-            PROC0_INTS2: mmio.Mmio(packed struct(u32) {
-                GPIO16_LEVEL_LOW: u1,
-                GPIO16_LEVEL_HIGH: u1,
-                GPIO16_EDGE_LOW: u1,
-                GPIO16_EDGE_HIGH: u1,
-                GPIO17_LEVEL_LOW: u1,
-                GPIO17_LEVEL_HIGH: u1,
-                GPIO17_EDGE_LOW: u1,
-                GPIO17_EDGE_HIGH: u1,
-                GPIO18_LEVEL_LOW: u1,
-                GPIO18_LEVEL_HIGH: u1,
-                GPIO18_EDGE_LOW: u1,
-                GPIO18_EDGE_HIGH: u1,
-                GPIO19_LEVEL_LOW: u1,
-                GPIO19_LEVEL_HIGH: u1,
-                GPIO19_EDGE_LOW: u1,
-                GPIO19_EDGE_HIGH: u1,
-                GPIO20_LEVEL_LOW: u1,
-                GPIO20_LEVEL_HIGH: u1,
-                GPIO20_EDGE_LOW: u1,
-                GPIO20_EDGE_HIGH: u1,
-                GPIO21_LEVEL_LOW: u1,
-                GPIO21_LEVEL_HIGH: u1,
-                GPIO21_EDGE_LOW: u1,
-                GPIO21_EDGE_HIGH: u1,
-                GPIO22_LEVEL_LOW: u1,
-                GPIO22_LEVEL_HIGH: u1,
-                GPIO22_EDGE_LOW: u1,
-                GPIO22_EDGE_HIGH: u1,
-                GPIO23_LEVEL_LOW: u1,
-                GPIO23_LEVEL_HIGH: u1,
-                GPIO23_EDGE_LOW: u1,
-                GPIO23_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt status after masking & forcing for proc0
-            PROC0_INTS3: mmio.Mmio(packed struct(u32) {
-                GPIO24_LEVEL_LOW: u1,
-                GPIO24_LEVEL_HIGH: u1,
-                GPIO24_EDGE_LOW: u1,
-                GPIO24_EDGE_HIGH: u1,
-                GPIO25_LEVEL_LOW: u1,
-                GPIO25_LEVEL_HIGH: u1,
-                GPIO25_EDGE_LOW: u1,
-                GPIO25_EDGE_HIGH: u1,
-                GPIO26_LEVEL_LOW: u1,
-                GPIO26_LEVEL_HIGH: u1,
-                GPIO26_EDGE_LOW: u1,
-                GPIO26_EDGE_HIGH: u1,
-                GPIO27_LEVEL_LOW: u1,
-                GPIO27_LEVEL_HIGH: u1,
-                GPIO27_EDGE_LOW: u1,
-                GPIO27_EDGE_HIGH: u1,
-                GPIO28_LEVEL_LOW: u1,
-                GPIO28_LEVEL_HIGH: u1,
-                GPIO28_EDGE_LOW: u1,
-                GPIO28_EDGE_HIGH: u1,
-                GPIO29_LEVEL_LOW: u1,
-                GPIO29_LEVEL_HIGH: u1,
-                GPIO29_EDGE_LOW: u1,
-                GPIO29_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Enable for proc1
-            PROC1_INTE0: mmio.Mmio(packed struct(u32) {
-                GPIO0_LEVEL_LOW: u1,
-                GPIO0_LEVEL_HIGH: u1,
-                GPIO0_EDGE_LOW: u1,
-                GPIO0_EDGE_HIGH: u1,
-                GPIO1_LEVEL_LOW: u1,
-                GPIO1_LEVEL_HIGH: u1,
-                GPIO1_EDGE_LOW: u1,
-                GPIO1_EDGE_HIGH: u1,
-                GPIO2_LEVEL_LOW: u1,
-                GPIO2_LEVEL_HIGH: u1,
-                GPIO2_EDGE_LOW: u1,
-                GPIO2_EDGE_HIGH: u1,
-                GPIO3_LEVEL_LOW: u1,
-                GPIO3_LEVEL_HIGH: u1,
-                GPIO3_EDGE_LOW: u1,
-                GPIO3_EDGE_HIGH: u1,
-                GPIO4_LEVEL_LOW: u1,
-                GPIO4_LEVEL_HIGH: u1,
-                GPIO4_EDGE_LOW: u1,
-                GPIO4_EDGE_HIGH: u1,
-                GPIO5_LEVEL_LOW: u1,
-                GPIO5_LEVEL_HIGH: u1,
-                GPIO5_EDGE_LOW: u1,
-                GPIO5_EDGE_HIGH: u1,
-                GPIO6_LEVEL_LOW: u1,
-                GPIO6_LEVEL_HIGH: u1,
-                GPIO6_EDGE_LOW: u1,
-                GPIO6_EDGE_HIGH: u1,
-                GPIO7_LEVEL_LOW: u1,
-                GPIO7_LEVEL_HIGH: u1,
-                GPIO7_EDGE_LOW: u1,
-                GPIO7_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Enable for proc1
-            PROC1_INTE1: mmio.Mmio(packed struct(u32) {
-                GPIO8_LEVEL_LOW: u1,
-                GPIO8_LEVEL_HIGH: u1,
-                GPIO8_EDGE_LOW: u1,
-                GPIO8_EDGE_HIGH: u1,
-                GPIO9_LEVEL_LOW: u1,
-                GPIO9_LEVEL_HIGH: u1,
-                GPIO9_EDGE_LOW: u1,
-                GPIO9_EDGE_HIGH: u1,
-                GPIO10_LEVEL_LOW: u1,
-                GPIO10_LEVEL_HIGH: u1,
-                GPIO10_EDGE_LOW: u1,
-                GPIO10_EDGE_HIGH: u1,
-                GPIO11_LEVEL_LOW: u1,
-                GPIO11_LEVEL_HIGH: u1,
-                GPIO11_EDGE_LOW: u1,
-                GPIO11_EDGE_HIGH: u1,
-                GPIO12_LEVEL_LOW: u1,
-                GPIO12_LEVEL_HIGH: u1,
-                GPIO12_EDGE_LOW: u1,
-                GPIO12_EDGE_HIGH: u1,
-                GPIO13_LEVEL_LOW: u1,
-                GPIO13_LEVEL_HIGH: u1,
-                GPIO13_EDGE_LOW: u1,
-                GPIO13_EDGE_HIGH: u1,
-                GPIO14_LEVEL_LOW: u1,
-                GPIO14_LEVEL_HIGH: u1,
-                GPIO14_EDGE_LOW: u1,
-                GPIO14_EDGE_HIGH: u1,
-                GPIO15_LEVEL_LOW: u1,
-                GPIO15_LEVEL_HIGH: u1,
-                GPIO15_EDGE_LOW: u1,
-                GPIO15_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Enable for proc1
-            PROC1_INTE2: mmio.Mmio(packed struct(u32) {
-                GPIO16_LEVEL_LOW: u1,
-                GPIO16_LEVEL_HIGH: u1,
-                GPIO16_EDGE_LOW: u1,
-                GPIO16_EDGE_HIGH: u1,
-                GPIO17_LEVEL_LOW: u1,
-                GPIO17_LEVEL_HIGH: u1,
-                GPIO17_EDGE_LOW: u1,
-                GPIO17_EDGE_HIGH: u1,
-                GPIO18_LEVEL_LOW: u1,
-                GPIO18_LEVEL_HIGH: u1,
-                GPIO18_EDGE_LOW: u1,
-                GPIO18_EDGE_HIGH: u1,
-                GPIO19_LEVEL_LOW: u1,
-                GPIO19_LEVEL_HIGH: u1,
-                GPIO19_EDGE_LOW: u1,
-                GPIO19_EDGE_HIGH: u1,
-                GPIO20_LEVEL_LOW: u1,
-                GPIO20_LEVEL_HIGH: u1,
-                GPIO20_EDGE_LOW: u1,
-                GPIO20_EDGE_HIGH: u1,
-                GPIO21_LEVEL_LOW: u1,
-                GPIO21_LEVEL_HIGH: u1,
-                GPIO21_EDGE_LOW: u1,
-                GPIO21_EDGE_HIGH: u1,
-                GPIO22_LEVEL_LOW: u1,
-                GPIO22_LEVEL_HIGH: u1,
-                GPIO22_EDGE_LOW: u1,
-                GPIO22_EDGE_HIGH: u1,
-                GPIO23_LEVEL_LOW: u1,
-                GPIO23_LEVEL_HIGH: u1,
-                GPIO23_EDGE_LOW: u1,
-                GPIO23_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Enable for proc1
-            PROC1_INTE3: mmio.Mmio(packed struct(u32) {
-                GPIO24_LEVEL_LOW: u1,
-                GPIO24_LEVEL_HIGH: u1,
-                GPIO24_EDGE_LOW: u1,
-                GPIO24_EDGE_HIGH: u1,
-                GPIO25_LEVEL_LOW: u1,
-                GPIO25_LEVEL_HIGH: u1,
-                GPIO25_EDGE_LOW: u1,
-                GPIO25_EDGE_HIGH: u1,
-                GPIO26_LEVEL_LOW: u1,
-                GPIO26_LEVEL_HIGH: u1,
-                GPIO26_EDGE_LOW: u1,
-                GPIO26_EDGE_HIGH: u1,
-                GPIO27_LEVEL_LOW: u1,
-                GPIO27_LEVEL_HIGH: u1,
-                GPIO27_EDGE_LOW: u1,
-                GPIO27_EDGE_HIGH: u1,
-                GPIO28_LEVEL_LOW: u1,
-                GPIO28_LEVEL_HIGH: u1,
-                GPIO28_EDGE_LOW: u1,
-                GPIO28_EDGE_HIGH: u1,
-                GPIO29_LEVEL_LOW: u1,
-                GPIO29_LEVEL_HIGH: u1,
-                GPIO29_EDGE_LOW: u1,
-                GPIO29_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Force for proc1
-            PROC1_INTF0: mmio.Mmio(packed struct(u32) {
-                GPIO0_LEVEL_LOW: u1,
-                GPIO0_LEVEL_HIGH: u1,
-                GPIO0_EDGE_LOW: u1,
-                GPIO0_EDGE_HIGH: u1,
-                GPIO1_LEVEL_LOW: u1,
-                GPIO1_LEVEL_HIGH: u1,
-                GPIO1_EDGE_LOW: u1,
-                GPIO1_EDGE_HIGH: u1,
-                GPIO2_LEVEL_LOW: u1,
-                GPIO2_LEVEL_HIGH: u1,
-                GPIO2_EDGE_LOW: u1,
-                GPIO2_EDGE_HIGH: u1,
-                GPIO3_LEVEL_LOW: u1,
-                GPIO3_LEVEL_HIGH: u1,
-                GPIO3_EDGE_LOW: u1,
-                GPIO3_EDGE_HIGH: u1,
-                GPIO4_LEVEL_LOW: u1,
-                GPIO4_LEVEL_HIGH: u1,
-                GPIO4_EDGE_LOW: u1,
-                GPIO4_EDGE_HIGH: u1,
-                GPIO5_LEVEL_LOW: u1,
-                GPIO5_LEVEL_HIGH: u1,
-                GPIO5_EDGE_LOW: u1,
-                GPIO5_EDGE_HIGH: u1,
-                GPIO6_LEVEL_LOW: u1,
-                GPIO6_LEVEL_HIGH: u1,
-                GPIO6_EDGE_LOW: u1,
-                GPIO6_EDGE_HIGH: u1,
-                GPIO7_LEVEL_LOW: u1,
-                GPIO7_LEVEL_HIGH: u1,
-                GPIO7_EDGE_LOW: u1,
-                GPIO7_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Force for proc1
-            PROC1_INTF1: mmio.Mmio(packed struct(u32) {
-                GPIO8_LEVEL_LOW: u1,
-                GPIO8_LEVEL_HIGH: u1,
-                GPIO8_EDGE_LOW: u1,
-                GPIO8_EDGE_HIGH: u1,
-                GPIO9_LEVEL_LOW: u1,
-                GPIO9_LEVEL_HIGH: u1,
-                GPIO9_EDGE_LOW: u1,
-                GPIO9_EDGE_HIGH: u1,
-                GPIO10_LEVEL_LOW: u1,
-                GPIO10_LEVEL_HIGH: u1,
-                GPIO10_EDGE_LOW: u1,
-                GPIO10_EDGE_HIGH: u1,
-                GPIO11_LEVEL_LOW: u1,
-                GPIO11_LEVEL_HIGH: u1,
-                GPIO11_EDGE_LOW: u1,
-                GPIO11_EDGE_HIGH: u1,
-                GPIO12_LEVEL_LOW: u1,
-                GPIO12_LEVEL_HIGH: u1,
-                GPIO12_EDGE_LOW: u1,
-                GPIO12_EDGE_HIGH: u1,
-                GPIO13_LEVEL_LOW: u1,
-                GPIO13_LEVEL_HIGH: u1,
-                GPIO13_EDGE_LOW: u1,
-                GPIO13_EDGE_HIGH: u1,
-                GPIO14_LEVEL_LOW: u1,
-                GPIO14_LEVEL_HIGH: u1,
-                GPIO14_EDGE_LOW: u1,
-                GPIO14_EDGE_HIGH: u1,
-                GPIO15_LEVEL_LOW: u1,
-                GPIO15_LEVEL_HIGH: u1,
-                GPIO15_EDGE_LOW: u1,
-                GPIO15_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Force for proc1
-            PROC1_INTF2: mmio.Mmio(packed struct(u32) {
-                GPIO16_LEVEL_LOW: u1,
-                GPIO16_LEVEL_HIGH: u1,
-                GPIO16_EDGE_LOW: u1,
-                GPIO16_EDGE_HIGH: u1,
-                GPIO17_LEVEL_LOW: u1,
-                GPIO17_LEVEL_HIGH: u1,
-                GPIO17_EDGE_LOW: u1,
-                GPIO17_EDGE_HIGH: u1,
-                GPIO18_LEVEL_LOW: u1,
-                GPIO18_LEVEL_HIGH: u1,
-                GPIO18_EDGE_LOW: u1,
-                GPIO18_EDGE_HIGH: u1,
-                GPIO19_LEVEL_LOW: u1,
-                GPIO19_LEVEL_HIGH: u1,
-                GPIO19_EDGE_LOW: u1,
-                GPIO19_EDGE_HIGH: u1,
-                GPIO20_LEVEL_LOW: u1,
-                GPIO20_LEVEL_HIGH: u1,
-                GPIO20_EDGE_LOW: u1,
-                GPIO20_EDGE_HIGH: u1,
-                GPIO21_LEVEL_LOW: u1,
-                GPIO21_LEVEL_HIGH: u1,
-                GPIO21_EDGE_LOW: u1,
-                GPIO21_EDGE_HIGH: u1,
-                GPIO22_LEVEL_LOW: u1,
-                GPIO22_LEVEL_HIGH: u1,
-                GPIO22_EDGE_LOW: u1,
-                GPIO22_EDGE_HIGH: u1,
-                GPIO23_LEVEL_LOW: u1,
-                GPIO23_LEVEL_HIGH: u1,
-                GPIO23_EDGE_LOW: u1,
-                GPIO23_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Force for proc1
-            PROC1_INTF3: mmio.Mmio(packed struct(u32) {
-                GPIO24_LEVEL_LOW: u1,
-                GPIO24_LEVEL_HIGH: u1,
-                GPIO24_EDGE_LOW: u1,
-                GPIO24_EDGE_HIGH: u1,
-                GPIO25_LEVEL_LOW: u1,
-                GPIO25_LEVEL_HIGH: u1,
-                GPIO25_EDGE_LOW: u1,
-                GPIO25_EDGE_HIGH: u1,
-                GPIO26_LEVEL_LOW: u1,
-                GPIO26_LEVEL_HIGH: u1,
-                GPIO26_EDGE_LOW: u1,
-                GPIO26_EDGE_HIGH: u1,
-                GPIO27_LEVEL_LOW: u1,
-                GPIO27_LEVEL_HIGH: u1,
-                GPIO27_EDGE_LOW: u1,
-                GPIO27_EDGE_HIGH: u1,
-                GPIO28_LEVEL_LOW: u1,
-                GPIO28_LEVEL_HIGH: u1,
-                GPIO28_EDGE_LOW: u1,
-                GPIO28_EDGE_HIGH: u1,
-                GPIO29_LEVEL_LOW: u1,
-                GPIO29_LEVEL_HIGH: u1,
-                GPIO29_EDGE_LOW: u1,
-                GPIO29_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt status after masking & forcing for proc1
-            PROC1_INTS0: mmio.Mmio(packed struct(u32) {
-                GPIO0_LEVEL_LOW: u1,
-                GPIO0_LEVEL_HIGH: u1,
-                GPIO0_EDGE_LOW: u1,
-                GPIO0_EDGE_HIGH: u1,
-                GPIO1_LEVEL_LOW: u1,
-                GPIO1_LEVEL_HIGH: u1,
-                GPIO1_EDGE_LOW: u1,
-                GPIO1_EDGE_HIGH: u1,
-                GPIO2_LEVEL_LOW: u1,
-                GPIO2_LEVEL_HIGH: u1,
-                GPIO2_EDGE_LOW: u1,
-                GPIO2_EDGE_HIGH: u1,
-                GPIO3_LEVEL_LOW: u1,
-                GPIO3_LEVEL_HIGH: u1,
-                GPIO3_EDGE_LOW: u1,
-                GPIO3_EDGE_HIGH: u1,
-                GPIO4_LEVEL_LOW: u1,
-                GPIO4_LEVEL_HIGH: u1,
-                GPIO4_EDGE_LOW: u1,
-                GPIO4_EDGE_HIGH: u1,
-                GPIO5_LEVEL_LOW: u1,
-                GPIO5_LEVEL_HIGH: u1,
-                GPIO5_EDGE_LOW: u1,
-                GPIO5_EDGE_HIGH: u1,
-                GPIO6_LEVEL_LOW: u1,
-                GPIO6_LEVEL_HIGH: u1,
-                GPIO6_EDGE_LOW: u1,
-                GPIO6_EDGE_HIGH: u1,
-                GPIO7_LEVEL_LOW: u1,
-                GPIO7_LEVEL_HIGH: u1,
-                GPIO7_EDGE_LOW: u1,
-                GPIO7_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt status after masking & forcing for proc1
-            PROC1_INTS1: mmio.Mmio(packed struct(u32) {
-                GPIO8_LEVEL_LOW: u1,
-                GPIO8_LEVEL_HIGH: u1,
-                GPIO8_EDGE_LOW: u1,
-                GPIO8_EDGE_HIGH: u1,
-                GPIO9_LEVEL_LOW: u1,
-                GPIO9_LEVEL_HIGH: u1,
-                GPIO9_EDGE_LOW: u1,
-                GPIO9_EDGE_HIGH: u1,
-                GPIO10_LEVEL_LOW: u1,
-                GPIO10_LEVEL_HIGH: u1,
-                GPIO10_EDGE_LOW: u1,
-                GPIO10_EDGE_HIGH: u1,
-                GPIO11_LEVEL_LOW: u1,
-                GPIO11_LEVEL_HIGH: u1,
-                GPIO11_EDGE_LOW: u1,
-                GPIO11_EDGE_HIGH: u1,
-                GPIO12_LEVEL_LOW: u1,
-                GPIO12_LEVEL_HIGH: u1,
-                GPIO12_EDGE_LOW: u1,
-                GPIO12_EDGE_HIGH: u1,
-                GPIO13_LEVEL_LOW: u1,
-                GPIO13_LEVEL_HIGH: u1,
-                GPIO13_EDGE_LOW: u1,
-                GPIO13_EDGE_HIGH: u1,
-                GPIO14_LEVEL_LOW: u1,
-                GPIO14_LEVEL_HIGH: u1,
-                GPIO14_EDGE_LOW: u1,
-                GPIO14_EDGE_HIGH: u1,
-                GPIO15_LEVEL_LOW: u1,
-                GPIO15_LEVEL_HIGH: u1,
-                GPIO15_EDGE_LOW: u1,
-                GPIO15_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt status after masking & forcing for proc1
-            PROC1_INTS2: mmio.Mmio(packed struct(u32) {
-                GPIO16_LEVEL_LOW: u1,
-                GPIO16_LEVEL_HIGH: u1,
-                GPIO16_EDGE_LOW: u1,
-                GPIO16_EDGE_HIGH: u1,
-                GPIO17_LEVEL_LOW: u1,
-                GPIO17_LEVEL_HIGH: u1,
-                GPIO17_EDGE_LOW: u1,
-                GPIO17_EDGE_HIGH: u1,
-                GPIO18_LEVEL_LOW: u1,
-                GPIO18_LEVEL_HIGH: u1,
-                GPIO18_EDGE_LOW: u1,
-                GPIO18_EDGE_HIGH: u1,
-                GPIO19_LEVEL_LOW: u1,
-                GPIO19_LEVEL_HIGH: u1,
-                GPIO19_EDGE_LOW: u1,
-                GPIO19_EDGE_HIGH: u1,
-                GPIO20_LEVEL_LOW: u1,
-                GPIO20_LEVEL_HIGH: u1,
-                GPIO20_EDGE_LOW: u1,
-                GPIO20_EDGE_HIGH: u1,
-                GPIO21_LEVEL_LOW: u1,
-                GPIO21_LEVEL_HIGH: u1,
-                GPIO21_EDGE_LOW: u1,
-                GPIO21_EDGE_HIGH: u1,
-                GPIO22_LEVEL_LOW: u1,
-                GPIO22_LEVEL_HIGH: u1,
-                GPIO22_EDGE_LOW: u1,
-                GPIO22_EDGE_HIGH: u1,
-                GPIO23_LEVEL_LOW: u1,
-                GPIO23_LEVEL_HIGH: u1,
-                GPIO23_EDGE_LOW: u1,
-                GPIO23_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt status after masking & forcing for proc1
-            PROC1_INTS3: mmio.Mmio(packed struct(u32) {
-                GPIO24_LEVEL_LOW: u1,
-                GPIO24_LEVEL_HIGH: u1,
-                GPIO24_EDGE_LOW: u1,
-                GPIO24_EDGE_HIGH: u1,
-                GPIO25_LEVEL_LOW: u1,
-                GPIO25_LEVEL_HIGH: u1,
-                GPIO25_EDGE_LOW: u1,
-                GPIO25_EDGE_HIGH: u1,
-                GPIO26_LEVEL_LOW: u1,
-                GPIO26_LEVEL_HIGH: u1,
-                GPIO26_EDGE_LOW: u1,
-                GPIO26_EDGE_HIGH: u1,
-                GPIO27_LEVEL_LOW: u1,
-                GPIO27_LEVEL_HIGH: u1,
-                GPIO27_EDGE_LOW: u1,
-                GPIO27_EDGE_HIGH: u1,
-                GPIO28_LEVEL_LOW: u1,
-                GPIO28_LEVEL_HIGH: u1,
-                GPIO28_EDGE_LOW: u1,
-                GPIO28_EDGE_HIGH: u1,
-                GPIO29_LEVEL_LOW: u1,
-                GPIO29_LEVEL_HIGH: u1,
-                GPIO29_EDGE_LOW: u1,
-                GPIO29_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Enable for dormant_wake
-            DORMANT_WAKE_INTE0: mmio.Mmio(packed struct(u32) {
-                GPIO0_LEVEL_LOW: u1,
-                GPIO0_LEVEL_HIGH: u1,
-                GPIO0_EDGE_LOW: u1,
-                GPIO0_EDGE_HIGH: u1,
-                GPIO1_LEVEL_LOW: u1,
-                GPIO1_LEVEL_HIGH: u1,
-                GPIO1_EDGE_LOW: u1,
-                GPIO1_EDGE_HIGH: u1,
-                GPIO2_LEVEL_LOW: u1,
-                GPIO2_LEVEL_HIGH: u1,
-                GPIO2_EDGE_LOW: u1,
-                GPIO2_EDGE_HIGH: u1,
-                GPIO3_LEVEL_LOW: u1,
-                GPIO3_LEVEL_HIGH: u1,
-                GPIO3_EDGE_LOW: u1,
-                GPIO3_EDGE_HIGH: u1,
-                GPIO4_LEVEL_LOW: u1,
-                GPIO4_LEVEL_HIGH: u1,
-                GPIO4_EDGE_LOW: u1,
-                GPIO4_EDGE_HIGH: u1,
-                GPIO5_LEVEL_LOW: u1,
-                GPIO5_LEVEL_HIGH: u1,
-                GPIO5_EDGE_LOW: u1,
-                GPIO5_EDGE_HIGH: u1,
-                GPIO6_LEVEL_LOW: u1,
-                GPIO6_LEVEL_HIGH: u1,
-                GPIO6_EDGE_LOW: u1,
-                GPIO6_EDGE_HIGH: u1,
-                GPIO7_LEVEL_LOW: u1,
-                GPIO7_LEVEL_HIGH: u1,
-                GPIO7_EDGE_LOW: u1,
-                GPIO7_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Enable for dormant_wake
-            DORMANT_WAKE_INTE1: mmio.Mmio(packed struct(u32) {
-                GPIO8_LEVEL_LOW: u1,
-                GPIO8_LEVEL_HIGH: u1,
-                GPIO8_EDGE_LOW: u1,
-                GPIO8_EDGE_HIGH: u1,
-                GPIO9_LEVEL_LOW: u1,
-                GPIO9_LEVEL_HIGH: u1,
-                GPIO9_EDGE_LOW: u1,
-                GPIO9_EDGE_HIGH: u1,
-                GPIO10_LEVEL_LOW: u1,
-                GPIO10_LEVEL_HIGH: u1,
-                GPIO10_EDGE_LOW: u1,
-                GPIO10_EDGE_HIGH: u1,
-                GPIO11_LEVEL_LOW: u1,
-                GPIO11_LEVEL_HIGH: u1,
-                GPIO11_EDGE_LOW: u1,
-                GPIO11_EDGE_HIGH: u1,
-                GPIO12_LEVEL_LOW: u1,
-                GPIO12_LEVEL_HIGH: u1,
-                GPIO12_EDGE_LOW: u1,
-                GPIO12_EDGE_HIGH: u1,
-                GPIO13_LEVEL_LOW: u1,
-                GPIO13_LEVEL_HIGH: u1,
-                GPIO13_EDGE_LOW: u1,
-                GPIO13_EDGE_HIGH: u1,
-                GPIO14_LEVEL_LOW: u1,
-                GPIO14_LEVEL_HIGH: u1,
-                GPIO14_EDGE_LOW: u1,
-                GPIO14_EDGE_HIGH: u1,
-                GPIO15_LEVEL_LOW: u1,
-                GPIO15_LEVEL_HIGH: u1,
-                GPIO15_EDGE_LOW: u1,
-                GPIO15_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Enable for dormant_wake
-            DORMANT_WAKE_INTE2: mmio.Mmio(packed struct(u32) {
-                GPIO16_LEVEL_LOW: u1,
-                GPIO16_LEVEL_HIGH: u1,
-                GPIO16_EDGE_LOW: u1,
-                GPIO16_EDGE_HIGH: u1,
-                GPIO17_LEVEL_LOW: u1,
-                GPIO17_LEVEL_HIGH: u1,
-                GPIO17_EDGE_LOW: u1,
-                GPIO17_EDGE_HIGH: u1,
-                GPIO18_LEVEL_LOW: u1,
-                GPIO18_LEVEL_HIGH: u1,
-                GPIO18_EDGE_LOW: u1,
-                GPIO18_EDGE_HIGH: u1,
-                GPIO19_LEVEL_LOW: u1,
-                GPIO19_LEVEL_HIGH: u1,
-                GPIO19_EDGE_LOW: u1,
-                GPIO19_EDGE_HIGH: u1,
-                GPIO20_LEVEL_LOW: u1,
-                GPIO20_LEVEL_HIGH: u1,
-                GPIO20_EDGE_LOW: u1,
-                GPIO20_EDGE_HIGH: u1,
-                GPIO21_LEVEL_LOW: u1,
-                GPIO21_LEVEL_HIGH: u1,
-                GPIO21_EDGE_LOW: u1,
-                GPIO21_EDGE_HIGH: u1,
-                GPIO22_LEVEL_LOW: u1,
-                GPIO22_LEVEL_HIGH: u1,
-                GPIO22_EDGE_LOW: u1,
-                GPIO22_EDGE_HIGH: u1,
-                GPIO23_LEVEL_LOW: u1,
-                GPIO23_LEVEL_HIGH: u1,
-                GPIO23_EDGE_LOW: u1,
-                GPIO23_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Enable for dormant_wake
-            DORMANT_WAKE_INTE3: mmio.Mmio(packed struct(u32) {
-                GPIO24_LEVEL_LOW: u1,
-                GPIO24_LEVEL_HIGH: u1,
-                GPIO24_EDGE_LOW: u1,
-                GPIO24_EDGE_HIGH: u1,
-                GPIO25_LEVEL_LOW: u1,
-                GPIO25_LEVEL_HIGH: u1,
-                GPIO25_EDGE_LOW: u1,
-                GPIO25_EDGE_HIGH: u1,
-                GPIO26_LEVEL_LOW: u1,
-                GPIO26_LEVEL_HIGH: u1,
-                GPIO26_EDGE_LOW: u1,
-                GPIO26_EDGE_HIGH: u1,
-                GPIO27_LEVEL_LOW: u1,
-                GPIO27_LEVEL_HIGH: u1,
-                GPIO27_EDGE_LOW: u1,
-                GPIO27_EDGE_HIGH: u1,
-                GPIO28_LEVEL_LOW: u1,
-                GPIO28_LEVEL_HIGH: u1,
-                GPIO28_EDGE_LOW: u1,
-                GPIO28_EDGE_HIGH: u1,
-                GPIO29_LEVEL_LOW: u1,
-                GPIO29_LEVEL_HIGH: u1,
-                GPIO29_EDGE_LOW: u1,
-                GPIO29_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Force for dormant_wake
-            DORMANT_WAKE_INTF0: mmio.Mmio(packed struct(u32) {
-                GPIO0_LEVEL_LOW: u1,
-                GPIO0_LEVEL_HIGH: u1,
-                GPIO0_EDGE_LOW: u1,
-                GPIO0_EDGE_HIGH: u1,
-                GPIO1_LEVEL_LOW: u1,
-                GPIO1_LEVEL_HIGH: u1,
-                GPIO1_EDGE_LOW: u1,
-                GPIO1_EDGE_HIGH: u1,
-                GPIO2_LEVEL_LOW: u1,
-                GPIO2_LEVEL_HIGH: u1,
-                GPIO2_EDGE_LOW: u1,
-                GPIO2_EDGE_HIGH: u1,
-                GPIO3_LEVEL_LOW: u1,
-                GPIO3_LEVEL_HIGH: u1,
-                GPIO3_EDGE_LOW: u1,
-                GPIO3_EDGE_HIGH: u1,
-                GPIO4_LEVEL_LOW: u1,
-                GPIO4_LEVEL_HIGH: u1,
-                GPIO4_EDGE_LOW: u1,
-                GPIO4_EDGE_HIGH: u1,
-                GPIO5_LEVEL_LOW: u1,
-                GPIO5_LEVEL_HIGH: u1,
-                GPIO5_EDGE_LOW: u1,
-                GPIO5_EDGE_HIGH: u1,
-                GPIO6_LEVEL_LOW: u1,
-                GPIO6_LEVEL_HIGH: u1,
-                GPIO6_EDGE_LOW: u1,
-                GPIO6_EDGE_HIGH: u1,
-                GPIO7_LEVEL_LOW: u1,
-                GPIO7_LEVEL_HIGH: u1,
-                GPIO7_EDGE_LOW: u1,
-                GPIO7_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Force for dormant_wake
-            DORMANT_WAKE_INTF1: mmio.Mmio(packed struct(u32) {
-                GPIO8_LEVEL_LOW: u1,
-                GPIO8_LEVEL_HIGH: u1,
-                GPIO8_EDGE_LOW: u1,
-                GPIO8_EDGE_HIGH: u1,
-                GPIO9_LEVEL_LOW: u1,
-                GPIO9_LEVEL_HIGH: u1,
-                GPIO9_EDGE_LOW: u1,
-                GPIO9_EDGE_HIGH: u1,
-                GPIO10_LEVEL_LOW: u1,
-                GPIO10_LEVEL_HIGH: u1,
-                GPIO10_EDGE_LOW: u1,
-                GPIO10_EDGE_HIGH: u1,
-                GPIO11_LEVEL_LOW: u1,
-                GPIO11_LEVEL_HIGH: u1,
-                GPIO11_EDGE_LOW: u1,
-                GPIO11_EDGE_HIGH: u1,
-                GPIO12_LEVEL_LOW: u1,
-                GPIO12_LEVEL_HIGH: u1,
-                GPIO12_EDGE_LOW: u1,
-                GPIO12_EDGE_HIGH: u1,
-                GPIO13_LEVEL_LOW: u1,
-                GPIO13_LEVEL_HIGH: u1,
-                GPIO13_EDGE_LOW: u1,
-                GPIO13_EDGE_HIGH: u1,
-                GPIO14_LEVEL_LOW: u1,
-                GPIO14_LEVEL_HIGH: u1,
-                GPIO14_EDGE_LOW: u1,
-                GPIO14_EDGE_HIGH: u1,
-                GPIO15_LEVEL_LOW: u1,
-                GPIO15_LEVEL_HIGH: u1,
-                GPIO15_EDGE_LOW: u1,
-                GPIO15_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Force for dormant_wake
-            DORMANT_WAKE_INTF2: mmio.Mmio(packed struct(u32) {
-                GPIO16_LEVEL_LOW: u1,
-                GPIO16_LEVEL_HIGH: u1,
-                GPIO16_EDGE_LOW: u1,
-                GPIO16_EDGE_HIGH: u1,
-                GPIO17_LEVEL_LOW: u1,
-                GPIO17_LEVEL_HIGH: u1,
-                GPIO17_EDGE_LOW: u1,
-                GPIO17_EDGE_HIGH: u1,
-                GPIO18_LEVEL_LOW: u1,
-                GPIO18_LEVEL_HIGH: u1,
-                GPIO18_EDGE_LOW: u1,
-                GPIO18_EDGE_HIGH: u1,
-                GPIO19_LEVEL_LOW: u1,
-                GPIO19_LEVEL_HIGH: u1,
-                GPIO19_EDGE_LOW: u1,
-                GPIO19_EDGE_HIGH: u1,
-                GPIO20_LEVEL_LOW: u1,
-                GPIO20_LEVEL_HIGH: u1,
-                GPIO20_EDGE_LOW: u1,
-                GPIO20_EDGE_HIGH: u1,
-                GPIO21_LEVEL_LOW: u1,
-                GPIO21_LEVEL_HIGH: u1,
-                GPIO21_EDGE_LOW: u1,
-                GPIO21_EDGE_HIGH: u1,
-                GPIO22_LEVEL_LOW: u1,
-                GPIO22_LEVEL_HIGH: u1,
-                GPIO22_EDGE_LOW: u1,
-                GPIO22_EDGE_HIGH: u1,
-                GPIO23_LEVEL_LOW: u1,
-                GPIO23_LEVEL_HIGH: u1,
-                GPIO23_EDGE_LOW: u1,
-                GPIO23_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt Force for dormant_wake
-            DORMANT_WAKE_INTF3: mmio.Mmio(packed struct(u32) {
-                GPIO24_LEVEL_LOW: u1,
-                GPIO24_LEVEL_HIGH: u1,
-                GPIO24_EDGE_LOW: u1,
-                GPIO24_EDGE_HIGH: u1,
-                GPIO25_LEVEL_LOW: u1,
-                GPIO25_LEVEL_HIGH: u1,
-                GPIO25_EDGE_LOW: u1,
-                GPIO25_EDGE_HIGH: u1,
-                GPIO26_LEVEL_LOW: u1,
-                GPIO26_LEVEL_HIGH: u1,
-                GPIO26_EDGE_LOW: u1,
-                GPIO26_EDGE_HIGH: u1,
-                GPIO27_LEVEL_LOW: u1,
-                GPIO27_LEVEL_HIGH: u1,
-                GPIO27_EDGE_LOW: u1,
-                GPIO27_EDGE_HIGH: u1,
-                GPIO28_LEVEL_LOW: u1,
-                GPIO28_LEVEL_HIGH: u1,
-                GPIO28_EDGE_LOW: u1,
-                GPIO28_EDGE_HIGH: u1,
-                GPIO29_LEVEL_LOW: u1,
-                GPIO29_LEVEL_HIGH: u1,
-                GPIO29_EDGE_LOW: u1,
-                GPIO29_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt status after masking & forcing for dormant_wake
-            DORMANT_WAKE_INTS0: mmio.Mmio(packed struct(u32) {
-                GPIO0_LEVEL_LOW: u1,
-                GPIO0_LEVEL_HIGH: u1,
-                GPIO0_EDGE_LOW: u1,
-                GPIO0_EDGE_HIGH: u1,
-                GPIO1_LEVEL_LOW: u1,
-                GPIO1_LEVEL_HIGH: u1,
-                GPIO1_EDGE_LOW: u1,
-                GPIO1_EDGE_HIGH: u1,
-                GPIO2_LEVEL_LOW: u1,
-                GPIO2_LEVEL_HIGH: u1,
-                GPIO2_EDGE_LOW: u1,
-                GPIO2_EDGE_HIGH: u1,
-                GPIO3_LEVEL_LOW: u1,
-                GPIO3_LEVEL_HIGH: u1,
-                GPIO3_EDGE_LOW: u1,
-                GPIO3_EDGE_HIGH: u1,
-                GPIO4_LEVEL_LOW: u1,
-                GPIO4_LEVEL_HIGH: u1,
-                GPIO4_EDGE_LOW: u1,
-                GPIO4_EDGE_HIGH: u1,
-                GPIO5_LEVEL_LOW: u1,
-                GPIO5_LEVEL_HIGH: u1,
-                GPIO5_EDGE_LOW: u1,
-                GPIO5_EDGE_HIGH: u1,
-                GPIO6_LEVEL_LOW: u1,
-                GPIO6_LEVEL_HIGH: u1,
-                GPIO6_EDGE_LOW: u1,
-                GPIO6_EDGE_HIGH: u1,
-                GPIO7_LEVEL_LOW: u1,
-                GPIO7_LEVEL_HIGH: u1,
-                GPIO7_EDGE_LOW: u1,
-                GPIO7_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt status after masking & forcing for dormant_wake
-            DORMANT_WAKE_INTS1: mmio.Mmio(packed struct(u32) {
-                GPIO8_LEVEL_LOW: u1,
-                GPIO8_LEVEL_HIGH: u1,
-                GPIO8_EDGE_LOW: u1,
-                GPIO8_EDGE_HIGH: u1,
-                GPIO9_LEVEL_LOW: u1,
-                GPIO9_LEVEL_HIGH: u1,
-                GPIO9_EDGE_LOW: u1,
-                GPIO9_EDGE_HIGH: u1,
-                GPIO10_LEVEL_LOW: u1,
-                GPIO10_LEVEL_HIGH: u1,
-                GPIO10_EDGE_LOW: u1,
-                GPIO10_EDGE_HIGH: u1,
-                GPIO11_LEVEL_LOW: u1,
-                GPIO11_LEVEL_HIGH: u1,
-                GPIO11_EDGE_LOW: u1,
-                GPIO11_EDGE_HIGH: u1,
-                GPIO12_LEVEL_LOW: u1,
-                GPIO12_LEVEL_HIGH: u1,
-                GPIO12_EDGE_LOW: u1,
-                GPIO12_EDGE_HIGH: u1,
-                GPIO13_LEVEL_LOW: u1,
-                GPIO13_LEVEL_HIGH: u1,
-                GPIO13_EDGE_LOW: u1,
-                GPIO13_EDGE_HIGH: u1,
-                GPIO14_LEVEL_LOW: u1,
-                GPIO14_LEVEL_HIGH: u1,
-                GPIO14_EDGE_LOW: u1,
-                GPIO14_EDGE_HIGH: u1,
-                GPIO15_LEVEL_LOW: u1,
-                GPIO15_LEVEL_HIGH: u1,
-                GPIO15_EDGE_LOW: u1,
-                GPIO15_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt status after masking & forcing for dormant_wake
-            DORMANT_WAKE_INTS2: mmio.Mmio(packed struct(u32) {
-                GPIO16_LEVEL_LOW: u1,
-                GPIO16_LEVEL_HIGH: u1,
-                GPIO16_EDGE_LOW: u1,
-                GPIO16_EDGE_HIGH: u1,
-                GPIO17_LEVEL_LOW: u1,
-                GPIO17_LEVEL_HIGH: u1,
-                GPIO17_EDGE_LOW: u1,
-                GPIO17_EDGE_HIGH: u1,
-                GPIO18_LEVEL_LOW: u1,
-                GPIO18_LEVEL_HIGH: u1,
-                GPIO18_EDGE_LOW: u1,
-                GPIO18_EDGE_HIGH: u1,
-                GPIO19_LEVEL_LOW: u1,
-                GPIO19_LEVEL_HIGH: u1,
-                GPIO19_EDGE_LOW: u1,
-                GPIO19_EDGE_HIGH: u1,
-                GPIO20_LEVEL_LOW: u1,
-                GPIO20_LEVEL_HIGH: u1,
-                GPIO20_EDGE_LOW: u1,
-                GPIO20_EDGE_HIGH: u1,
-                GPIO21_LEVEL_LOW: u1,
-                GPIO21_LEVEL_HIGH: u1,
-                GPIO21_EDGE_LOW: u1,
-                GPIO21_EDGE_HIGH: u1,
-                GPIO22_LEVEL_LOW: u1,
-                GPIO22_LEVEL_HIGH: u1,
-                GPIO22_EDGE_LOW: u1,
-                GPIO22_EDGE_HIGH: u1,
-                GPIO23_LEVEL_LOW: u1,
-                GPIO23_LEVEL_HIGH: u1,
-                GPIO23_EDGE_LOW: u1,
-                GPIO23_EDGE_HIGH: u1,
-            }),
-            ///  Interrupt status after masking & forcing for dormant_wake
-            DORMANT_WAKE_INTS3: mmio.Mmio(packed struct(u32) {
-                GPIO24_LEVEL_LOW: u1,
-                GPIO24_LEVEL_HIGH: u1,
-                GPIO24_EDGE_LOW: u1,
-                GPIO24_EDGE_HIGH: u1,
-                GPIO25_LEVEL_LOW: u1,
-                GPIO25_LEVEL_HIGH: u1,
-                GPIO25_EDGE_LOW: u1,
-                GPIO25_EDGE_HIGH: u1,
-                GPIO26_LEVEL_LOW: u1,
-                GPIO26_LEVEL_HIGH: u1,
-                GPIO26_EDGE_LOW: u1,
-                GPIO26_EDGE_HIGH: u1,
-                GPIO27_LEVEL_LOW: u1,
-                GPIO27_LEVEL_HIGH: u1,
-                GPIO27_EDGE_LOW: u1,
-                GPIO27_EDGE_HIGH: u1,
-                GPIO28_LEVEL_LOW: u1,
-                GPIO28_LEVEL_HIGH: u1,
-                GPIO28_EDGE_LOW: u1,
-                GPIO28_EDGE_HIGH: u1,
-                GPIO29_LEVEL_LOW: u1,
-                GPIO29_LEVEL_HIGH: u1,
-                GPIO29_EDGE_LOW: u1,
-                GPIO29_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-        };
-
-        pub const IO_QSPI = extern struct {
-            ///  GPIO status
-            GPIO_QSPI_SCLK_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO_QSPI_SCLK_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        xip_sclk = 0x0,
-                        sio_30 = 0x5,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO_QSPI_SS_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO_QSPI_SS_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        xip_ss_n = 0x0,
-                        sio_31 = 0x5,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO_QSPI_SD0_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO_QSPI_SD0_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        xip_sd0 = 0x0,
-                        sio_32 = 0x5,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO_QSPI_SD1_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO_QSPI_SD1_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        xip_sd1 = 0x0,
-                        sio_33 = 0x5,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO_QSPI_SD2_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO_QSPI_SD2_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        xip_sd2 = 0x0,
-                        sio_34 = 0x5,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  GPIO status
-            GPIO_QSPI_SD3_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  output signal from selected peripheral, before register override is applied
-                OUTFROMPERI: u1,
-                ///  output signal to pad after register override is applied
-                OUTTOPAD: u1,
-                reserved12: u2,
-                ///  output enable from selected peripheral, before register override is applied
-                OEFROMPERI: u1,
-                ///  output enable to pad after register override is applied
-                OETOPAD: u1,
-                reserved17: u3,
-                ///  input signal from pad, before override is applied
-                INFROMPAD: u1,
-                reserved19: u1,
-                ///  input signal to peripheral, after override is applied
-                INTOPERI: u1,
-                reserved24: u4,
-                ///  interrupt from pad before override is applied
-                IRQFROMPAD: u1,
-                reserved26: u1,
-                ///  interrupt to processors, after override is applied
-                IRQTOPROC: u1,
-                padding: u5,
-            }),
-            ///  GPIO control including function select and overrides.
-            GPIO_QSPI_SD3_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  0-31 -> selects pin function according to the gpio table
-                ///  31 == NULL
-                FUNCSEL: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        xip_sd3 = 0x0,
-                        sio_35 = 0x5,
-                        null = 0x1f,
-                        _,
-                    },
-                },
-                reserved8: u3,
-                OUTOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  drive output low
-                        LOW = 0x2,
-                        ///  drive output high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved12: u2,
-                OEOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  drive output enable from peripheral signal selected by funcsel
-                        NORMAL = 0x0,
-                        ///  drive output enable from inverse of peripheral signal selected by funcsel
-                        INVERT = 0x1,
-                        ///  disable output
-                        DISABLE = 0x2,
-                        ///  enable output
-                        ENABLE = 0x3,
-                    },
-                },
-                reserved16: u2,
-                INOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the peri input
-                        NORMAL = 0x0,
-                        ///  invert the peri input
-                        INVERT = 0x1,
-                        ///  drive peri input low
-                        LOW = 0x2,
-                        ///  drive peri input high
-                        HIGH = 0x3,
-                    },
-                },
-                reserved28: u10,
-                IRQOVER: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  don't invert the interrupt
-                        NORMAL = 0x0,
-                        ///  invert the interrupt
-                        INVERT = 0x1,
-                        ///  drive interrupt low
-                        LOW = 0x2,
-                        ///  drive interrupt high
-                        HIGH = 0x3,
-                    },
-                },
-                padding: u2,
-            }),
-            ///  Raw Interrupts
-            INTR: mmio.Mmio(packed struct(u32) {
-                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-                GPIO_QSPI_SCLK_EDGE_LOW: u1,
-                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-                GPIO_QSPI_SS_LEVEL_LOW: u1,
-                GPIO_QSPI_SS_LEVEL_HIGH: u1,
-                GPIO_QSPI_SS_EDGE_LOW: u1,
-                GPIO_QSPI_SS_EDGE_HIGH: u1,
-                GPIO_QSPI_SD0_LEVEL_LOW: u1,
-                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD0_EDGE_LOW: u1,
-                GPIO_QSPI_SD0_EDGE_HIGH: u1,
-                GPIO_QSPI_SD1_LEVEL_LOW: u1,
-                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD1_EDGE_LOW: u1,
-                GPIO_QSPI_SD1_EDGE_HIGH: u1,
-                GPIO_QSPI_SD2_LEVEL_LOW: u1,
-                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD2_EDGE_LOW: u1,
-                GPIO_QSPI_SD2_EDGE_HIGH: u1,
-                GPIO_QSPI_SD3_LEVEL_LOW: u1,
-                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD3_EDGE_LOW: u1,
-                GPIO_QSPI_SD3_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Enable for proc0
-            PROC0_INTE: mmio.Mmio(packed struct(u32) {
-                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-                GPIO_QSPI_SCLK_EDGE_LOW: u1,
-                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-                GPIO_QSPI_SS_LEVEL_LOW: u1,
-                GPIO_QSPI_SS_LEVEL_HIGH: u1,
-                GPIO_QSPI_SS_EDGE_LOW: u1,
-                GPIO_QSPI_SS_EDGE_HIGH: u1,
-                GPIO_QSPI_SD0_LEVEL_LOW: u1,
-                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD0_EDGE_LOW: u1,
-                GPIO_QSPI_SD0_EDGE_HIGH: u1,
-                GPIO_QSPI_SD1_LEVEL_LOW: u1,
-                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD1_EDGE_LOW: u1,
-                GPIO_QSPI_SD1_EDGE_HIGH: u1,
-                GPIO_QSPI_SD2_LEVEL_LOW: u1,
-                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD2_EDGE_LOW: u1,
-                GPIO_QSPI_SD2_EDGE_HIGH: u1,
-                GPIO_QSPI_SD3_LEVEL_LOW: u1,
-                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD3_EDGE_LOW: u1,
-                GPIO_QSPI_SD3_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Force for proc0
-            PROC0_INTF: mmio.Mmio(packed struct(u32) {
-                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-                GPIO_QSPI_SCLK_EDGE_LOW: u1,
-                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-                GPIO_QSPI_SS_LEVEL_LOW: u1,
-                GPIO_QSPI_SS_LEVEL_HIGH: u1,
-                GPIO_QSPI_SS_EDGE_LOW: u1,
-                GPIO_QSPI_SS_EDGE_HIGH: u1,
-                GPIO_QSPI_SD0_LEVEL_LOW: u1,
-                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD0_EDGE_LOW: u1,
-                GPIO_QSPI_SD0_EDGE_HIGH: u1,
-                GPIO_QSPI_SD1_LEVEL_LOW: u1,
-                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD1_EDGE_LOW: u1,
-                GPIO_QSPI_SD1_EDGE_HIGH: u1,
-                GPIO_QSPI_SD2_LEVEL_LOW: u1,
-                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD2_EDGE_LOW: u1,
-                GPIO_QSPI_SD2_EDGE_HIGH: u1,
-                GPIO_QSPI_SD3_LEVEL_LOW: u1,
-                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD3_EDGE_LOW: u1,
-                GPIO_QSPI_SD3_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt status after masking & forcing for proc0
-            PROC0_INTS: mmio.Mmio(packed struct(u32) {
-                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-                GPIO_QSPI_SCLK_EDGE_LOW: u1,
-                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-                GPIO_QSPI_SS_LEVEL_LOW: u1,
-                GPIO_QSPI_SS_LEVEL_HIGH: u1,
-                GPIO_QSPI_SS_EDGE_LOW: u1,
-                GPIO_QSPI_SS_EDGE_HIGH: u1,
-                GPIO_QSPI_SD0_LEVEL_LOW: u1,
-                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD0_EDGE_LOW: u1,
-                GPIO_QSPI_SD0_EDGE_HIGH: u1,
-                GPIO_QSPI_SD1_LEVEL_LOW: u1,
-                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD1_EDGE_LOW: u1,
-                GPIO_QSPI_SD1_EDGE_HIGH: u1,
-                GPIO_QSPI_SD2_LEVEL_LOW: u1,
-                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD2_EDGE_LOW: u1,
-                GPIO_QSPI_SD2_EDGE_HIGH: u1,
-                GPIO_QSPI_SD3_LEVEL_LOW: u1,
-                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD3_EDGE_LOW: u1,
-                GPIO_QSPI_SD3_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Enable for proc1
-            PROC1_INTE: mmio.Mmio(packed struct(u32) {
-                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-                GPIO_QSPI_SCLK_EDGE_LOW: u1,
-                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-                GPIO_QSPI_SS_LEVEL_LOW: u1,
-                GPIO_QSPI_SS_LEVEL_HIGH: u1,
-                GPIO_QSPI_SS_EDGE_LOW: u1,
-                GPIO_QSPI_SS_EDGE_HIGH: u1,
-                GPIO_QSPI_SD0_LEVEL_LOW: u1,
-                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD0_EDGE_LOW: u1,
-                GPIO_QSPI_SD0_EDGE_HIGH: u1,
-                GPIO_QSPI_SD1_LEVEL_LOW: u1,
-                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD1_EDGE_LOW: u1,
-                GPIO_QSPI_SD1_EDGE_HIGH: u1,
-                GPIO_QSPI_SD2_LEVEL_LOW: u1,
-                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD2_EDGE_LOW: u1,
-                GPIO_QSPI_SD2_EDGE_HIGH: u1,
-                GPIO_QSPI_SD3_LEVEL_LOW: u1,
-                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD3_EDGE_LOW: u1,
-                GPIO_QSPI_SD3_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Force for proc1
-            PROC1_INTF: mmio.Mmio(packed struct(u32) {
-                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-                GPIO_QSPI_SCLK_EDGE_LOW: u1,
-                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-                GPIO_QSPI_SS_LEVEL_LOW: u1,
-                GPIO_QSPI_SS_LEVEL_HIGH: u1,
-                GPIO_QSPI_SS_EDGE_LOW: u1,
-                GPIO_QSPI_SS_EDGE_HIGH: u1,
-                GPIO_QSPI_SD0_LEVEL_LOW: u1,
-                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD0_EDGE_LOW: u1,
-                GPIO_QSPI_SD0_EDGE_HIGH: u1,
-                GPIO_QSPI_SD1_LEVEL_LOW: u1,
-                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD1_EDGE_LOW: u1,
-                GPIO_QSPI_SD1_EDGE_HIGH: u1,
-                GPIO_QSPI_SD2_LEVEL_LOW: u1,
-                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD2_EDGE_LOW: u1,
-                GPIO_QSPI_SD2_EDGE_HIGH: u1,
-                GPIO_QSPI_SD3_LEVEL_LOW: u1,
-                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD3_EDGE_LOW: u1,
-                GPIO_QSPI_SD3_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt status after masking & forcing for proc1
-            PROC1_INTS: mmio.Mmio(packed struct(u32) {
-                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-                GPIO_QSPI_SCLK_EDGE_LOW: u1,
-                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-                GPIO_QSPI_SS_LEVEL_LOW: u1,
-                GPIO_QSPI_SS_LEVEL_HIGH: u1,
-                GPIO_QSPI_SS_EDGE_LOW: u1,
-                GPIO_QSPI_SS_EDGE_HIGH: u1,
-                GPIO_QSPI_SD0_LEVEL_LOW: u1,
-                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD0_EDGE_LOW: u1,
-                GPIO_QSPI_SD0_EDGE_HIGH: u1,
-                GPIO_QSPI_SD1_LEVEL_LOW: u1,
-                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD1_EDGE_LOW: u1,
-                GPIO_QSPI_SD1_EDGE_HIGH: u1,
-                GPIO_QSPI_SD2_LEVEL_LOW: u1,
-                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD2_EDGE_LOW: u1,
-                GPIO_QSPI_SD2_EDGE_HIGH: u1,
-                GPIO_QSPI_SD3_LEVEL_LOW: u1,
-                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD3_EDGE_LOW: u1,
-                GPIO_QSPI_SD3_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Enable for dormant_wake
-            DORMANT_WAKE_INTE: mmio.Mmio(packed struct(u32) {
-                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-                GPIO_QSPI_SCLK_EDGE_LOW: u1,
-                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-                GPIO_QSPI_SS_LEVEL_LOW: u1,
-                GPIO_QSPI_SS_LEVEL_HIGH: u1,
-                GPIO_QSPI_SS_EDGE_LOW: u1,
-                GPIO_QSPI_SS_EDGE_HIGH: u1,
-                GPIO_QSPI_SD0_LEVEL_LOW: u1,
-                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD0_EDGE_LOW: u1,
-                GPIO_QSPI_SD0_EDGE_HIGH: u1,
-                GPIO_QSPI_SD1_LEVEL_LOW: u1,
-                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD1_EDGE_LOW: u1,
-                GPIO_QSPI_SD1_EDGE_HIGH: u1,
-                GPIO_QSPI_SD2_LEVEL_LOW: u1,
-                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD2_EDGE_LOW: u1,
-                GPIO_QSPI_SD2_EDGE_HIGH: u1,
-                GPIO_QSPI_SD3_LEVEL_LOW: u1,
-                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD3_EDGE_LOW: u1,
-                GPIO_QSPI_SD3_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt Force for dormant_wake
-            DORMANT_WAKE_INTF: mmio.Mmio(packed struct(u32) {
-                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-                GPIO_QSPI_SCLK_EDGE_LOW: u1,
-                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-                GPIO_QSPI_SS_LEVEL_LOW: u1,
-                GPIO_QSPI_SS_LEVEL_HIGH: u1,
-                GPIO_QSPI_SS_EDGE_LOW: u1,
-                GPIO_QSPI_SS_EDGE_HIGH: u1,
-                GPIO_QSPI_SD0_LEVEL_LOW: u1,
-                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD0_EDGE_LOW: u1,
-                GPIO_QSPI_SD0_EDGE_HIGH: u1,
-                GPIO_QSPI_SD1_LEVEL_LOW: u1,
-                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD1_EDGE_LOW: u1,
-                GPIO_QSPI_SD1_EDGE_HIGH: u1,
-                GPIO_QSPI_SD2_LEVEL_LOW: u1,
-                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD2_EDGE_LOW: u1,
-                GPIO_QSPI_SD2_EDGE_HIGH: u1,
-                GPIO_QSPI_SD3_LEVEL_LOW: u1,
-                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD3_EDGE_LOW: u1,
-                GPIO_QSPI_SD3_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-            ///  Interrupt status after masking & forcing for dormant_wake
-            DORMANT_WAKE_INTS: mmio.Mmio(packed struct(u32) {
-                GPIO_QSPI_SCLK_LEVEL_LOW: u1,
-                GPIO_QSPI_SCLK_LEVEL_HIGH: u1,
-                GPIO_QSPI_SCLK_EDGE_LOW: u1,
-                GPIO_QSPI_SCLK_EDGE_HIGH: u1,
-                GPIO_QSPI_SS_LEVEL_LOW: u1,
-                GPIO_QSPI_SS_LEVEL_HIGH: u1,
-                GPIO_QSPI_SS_EDGE_LOW: u1,
-                GPIO_QSPI_SS_EDGE_HIGH: u1,
-                GPIO_QSPI_SD0_LEVEL_LOW: u1,
-                GPIO_QSPI_SD0_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD0_EDGE_LOW: u1,
-                GPIO_QSPI_SD0_EDGE_HIGH: u1,
-                GPIO_QSPI_SD1_LEVEL_LOW: u1,
-                GPIO_QSPI_SD1_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD1_EDGE_LOW: u1,
-                GPIO_QSPI_SD1_EDGE_HIGH: u1,
-                GPIO_QSPI_SD2_LEVEL_LOW: u1,
-                GPIO_QSPI_SD2_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD2_EDGE_LOW: u1,
-                GPIO_QSPI_SD2_EDGE_HIGH: u1,
-                GPIO_QSPI_SD3_LEVEL_LOW: u1,
-                GPIO_QSPI_SD3_LEVEL_HIGH: u1,
-                GPIO_QSPI_SD3_EDGE_LOW: u1,
-                GPIO_QSPI_SD3_EDGE_HIGH: u1,
-                padding: u8,
-            }),
-        };
-
-        pub const PADS_BANK0 = extern struct {
-            ///  Voltage select. Per bank control
-            VOLTAGE_SELECT: mmio.Mmio(packed struct(u32) {
-                VOLTAGE_SELECT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Set voltage to 3.3V (DVDD >= 2V5)
-                        @"3v3" = 0x0,
-                        ///  Set voltage to 1.8V (DVDD <= 1V8)
-                        @"1v8" = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Pad control register
-            GPIO0: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO1: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO2: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO3: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO4: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO5: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO6: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO7: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO8: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO9: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO10: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO11: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO12: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO13: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO14: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO15: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO16: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO17: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO18: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO19: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO20: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO21: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO22: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO23: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO24: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO25: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO26: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO27: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO28: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO29: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            SWCLK: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            SWD: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-        };
-
-        pub const PADS_QSPI = extern struct {
-            ///  Voltage select. Per bank control
-            VOLTAGE_SELECT: mmio.Mmio(packed struct(u32) {
-                VOLTAGE_SELECT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Set voltage to 3.3V (DVDD >= 2V5)
-                        @"3v3" = 0x0,
-                        ///  Set voltage to 1.8V (DVDD <= 1V8)
-                        @"1v8" = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  Pad control register
-            GPIO_QSPI_SCLK: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO_QSPI_SD0: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO_QSPI_SD1: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO_QSPI_SD2: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO_QSPI_SD3: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-            ///  Pad control register
-            GPIO_QSPI_SS: mmio.Mmio(packed struct(u32) {
-                ///  Slew rate control. 1 = Fast, 0 = Slow
-                SLEWFAST: u1,
-                ///  Enable schmitt trigger
-                SCHMITT: u1,
-                ///  Pull down enable
-                PDE: u1,
-                ///  Pull up enable
-                PUE: u1,
-                ///  Drive strength.
-                DRIVE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"2mA" = 0x0,
-                        @"4mA" = 0x1,
-                        @"8mA" = 0x2,
-                        @"12mA" = 0x3,
-                    },
-                },
-                ///  Input enable
-                IE: u1,
-                ///  Output disable. Has priority over output enable from peripherals
-                OD: u1,
-                padding: u24,
-            }),
-        };
-
-        ///  Controls the crystal oscillator
-        pub const XOSC = extern struct {
-            ///  Crystal Oscillator Control
-            CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Frequency range. This resets to 0xAA0 and cannot be changed.
-                FREQ_RANGE: packed union {
-                    raw: u12,
-                    value: enum(u12) {
-                        @"1_15MHZ" = 0xaa0,
-                        RESERVED_1 = 0xaa1,
-                        RESERVED_2 = 0xaa2,
-                        RESERVED_3 = 0xaa3,
-                        _,
-                    },
-                },
-                ///  On power-up this field is initialised to DISABLE and the chip runs from the ROSC.
-                ///  If the chip has subsequently been programmed to run from the XOSC then setting this field to DISABLE may lock-up the chip. If this is a concern then run the clk_ref from the ROSC and enable the clk_sys RESUS feature.
-                ///  The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.
-                ENABLE: packed union {
-                    raw: u12,
-                    value: enum(u12) {
-                        DISABLE = 0xd1e,
-                        ENABLE = 0xfab,
-                        _,
-                    },
-                },
-                padding: u8,
-            }),
-            ///  Crystal Oscillator Status
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  The current frequency range setting, always reads 0
-                FREQ_RANGE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"1_15MHZ" = 0x0,
-                        RESERVED_1 = 0x1,
-                        RESERVED_2 = 0x2,
-                        RESERVED_3 = 0x3,
-                    },
-                },
-                reserved12: u10,
-                ///  Oscillator is enabled but not necessarily running and stable, resets to 0
-                ENABLED: u1,
-                reserved24: u11,
-                ///  An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or DORMANT
-                BADWRITE: u1,
-                reserved31: u6,
-                ///  Oscillator is running and stable
-                STABLE: u1,
-            }),
-            ///  Crystal Oscillator pause control
-            ///  This is used to save power by pausing the XOSC
-            ///  On power-up this field is initialised to WAKE
-            ///  An invalid write will also select WAKE
-            ///  WARNING: stop the PLLs before selecting dormant mode
-            ///  WARNING: setup the irq before selecting dormant mode
-            DORMANT: u32,
-            ///  Controls the startup delay
-            STARTUP: mmio.Mmio(packed struct(u32) {
-                ///  in multiples of 256*xtal_period. The reset value of 0xc4 corresponds to approx 50 000 cycles.
-                DELAY: u14,
-                reserved20: u6,
-                ///  Multiplies the startup_delay by 4. This is of little value to the user given that the delay can be programmed directly.
-                X4: u1,
-                padding: u11,
-            }),
-            reserved28: [12]u8,
-            ///  A down counter running at the xosc frequency which counts to zero and stops.
-            ///  To start the counter write a non-zero value.
-            ///  Can be used for short software pauses when setting up time sensitive hardware.
-            COUNT: mmio.Mmio(packed struct(u32) {
-                COUNT: u8,
-                padding: u24,
-            }),
-        };
-
-        pub const PLL_SYS = extern struct {
-            ///  Control and Status
-            ///  GENERAL CONSTRAINTS:
-            ///  Reference clock frequency min=5MHz, max=800MHz
-            ///  Feedback divider min=16, max=320
-            ///  VCO frequency min=400MHz, max=1600MHz
-            CS: mmio.Mmio(packed struct(u32) {
-                ///  Divides the PLL input reference clock.
-                ///  Behaviour is undefined for div=0.
-                ///  PLL output will be unpredictable during refdiv changes, wait for lock=1 before using it.
-                REFDIV: u6,
-                reserved8: u2,
-                ///  Passes the reference clock to the output instead of the divided VCO. The VCO continues to run so the user can switch between the reference clock and the divided VCO but the output will glitch when doing so.
-                BYPASS: u1,
-                reserved31: u22,
-                ///  PLL is locked
-                LOCK: u1,
-            }),
-            ///  Controls the PLL power modes.
-            PWR: mmio.Mmio(packed struct(u32) {
-                ///  PLL powerdown
-                ///  To save power set high when PLL output not required.
-                PD: u1,
-                reserved2: u1,
-                ///  PLL DSM powerdown
-                ///  Nothing is achieved by setting this low.
-                DSMPD: u1,
-                ///  PLL post divider powerdown
-                ///  To save power set high when PLL output not required or bypass=1.
-                POSTDIVPD: u1,
-                reserved5: u1,
-                ///  PLL VCO powerdown
-                ///  To save power set high when PLL output not required or bypass=1.
-                VCOPD: u1,
-                padding: u26,
-            }),
-            ///  Feedback divisor
-            ///  (note: this PLL does not support fractional division)
-            FBDIV_INT: mmio.Mmio(packed struct(u32) {
-                ///  see ctrl reg description for constraints
-                FBDIV_INT: u12,
-                padding: u20,
-            }),
-            ///  Controls the PLL post dividers for the primary output
-            ///  (note: this PLL does not have a secondary output)
-            ///  the primary output is driven from VCO divided by postdiv1*postdiv2
-            PRIM: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  divide by 1-7
-                POSTDIV2: u3,
-                reserved16: u1,
-                ///  divide by 1-7
-                POSTDIV1: u3,
-                padding: u13,
-            }),
-        };
-
-        pub const PPB = extern struct {
-            reserved57360: [57360]u8,
-            ///  Use the SysTick Control and Status Register to enable the SysTick features.
-            SYST_CSR: mmio.Mmio(packed struct(u32) {
-                ///  Enable SysTick counter:
-                ///  0 = Counter disabled.
-                ///  1 = Counter enabled.
-                ENABLE: u1,
-                ///  Enables SysTick exception request:
-                ///  0 = Counting down to zero does not assert the SysTick exception request.
-                ///  1 = Counting down to zero to asserts the SysTick exception request.
-                TICKINT: u1,
-                ///  SysTick clock source. Always reads as one if SYST_CALIB reports NOREF.
-                ///  Selects the SysTick timer clock source:
-                ///  0 = External reference clock.
-                ///  1 = Processor clock.
-                CLKSOURCE: u1,
-                reserved16: u13,
-                ///  Returns 1 if timer counted to 0 since last time this was read. Clears on read by application or debugger.
-                COUNTFLAG: u1,
-                padding: u15,
-            }),
-            ///  Use the SysTick Reload Value Register to specify the start value to load into the current value register when the counter reaches 0. It can be any value between 0 and 0x00FFFFFF. A start value of 0 is possible, but has no effect because the SysTick interrupt and COUNTFLAG are activated when counting from 1 to 0. The reset value of this register is UNKNOWN.
-            ///  To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD value of N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOAD to 99.
-            SYST_RVR: mmio.Mmio(packed struct(u32) {
-                ///  Value to load into the SysTick Current Value Register when the counter reaches 0.
-                RELOAD: u24,
-                padding: u8,
-            }),
-            ///  Use the SysTick Current Value Register to find the current value in the register. The reset value of this register is UNKNOWN.
-            SYST_CVR: mmio.Mmio(packed struct(u32) {
-                ///  Reads return the current value of the SysTick counter. This register is write-clear. Writing to it with any value clears the register to 0. Clearing this register also clears the COUNTFLAG bit of the SysTick Control and Status Register.
-                CURRENT: u24,
-                padding: u8,
-            }),
-            ///  Use the SysTick Calibration Value Register to enable software to scale to any required speed using divide and multiply.
-            SYST_CALIB: mmio.Mmio(packed struct(u32) {
-                ///  An optional Reload value to be used for 10ms (100Hz) timing, subject to system clock skew errors. If the value reads as 0, the calibration value is not known.
-                TENMS: u24,
-                reserved30: u6,
-                ///  If reads as 1, the calibration value for 10ms is inexact (due to clock frequency).
-                SKEW: u1,
-                ///  If reads as 1, the Reference clock is not provided - the CLKSOURCE bit of the SysTick Control and Status register will be forced to 1 and cannot be cleared to 0.
-                NOREF: u1,
-            }),
-            reserved57600: [224]u8,
-            ///  Use the Interrupt Set-Enable Register to enable interrupts and determine which interrupts are currently enabled.
-            ///  If a pending interrupt is enabled, the NVIC activates the interrupt based on its priority. If an interrupt is not enabled, asserting its interrupt signal changes the interrupt state to pending, but the NVIC never activates the interrupt, regardless of its priority.
-            NVIC_ISER: mmio.Mmio(packed struct(u32) {
-                ///  Interrupt set-enable bits.
-                ///  Write:
-                ///  0 = No effect.
-                ///  1 = Enable interrupt.
-                ///  Read:
-                ///  0 = Interrupt disabled.
-                ///  1 = Interrupt enabled.
-                SETENA: u32,
-            }),
-            reserved57728: [124]u8,
-            ///  Use the Interrupt Clear-Enable Registers to disable interrupts and determine which interrupts are currently enabled.
-            NVIC_ICER: mmio.Mmio(packed struct(u32) {
-                ///  Interrupt clear-enable bits.
-                ///  Write:
-                ///  0 = No effect.
-                ///  1 = Disable interrupt.
-                ///  Read:
-                ///  0 = Interrupt disabled.
-                ///  1 = Interrupt enabled.
-                CLRENA: u32,
-            }),
-            reserved57856: [124]u8,
-            ///  The NVIC_ISPR forces interrupts into the pending state, and shows which interrupts are pending.
-            NVIC_ISPR: mmio.Mmio(packed struct(u32) {
-                ///  Interrupt set-pending bits.
-                ///  Write:
-                ///  0 = No effect.
-                ///  1 = Changes interrupt state to pending.
-                ///  Read:
-                ///  0 = Interrupt is not pending.
-                ///  1 = Interrupt is pending.
-                ///  Note: Writing 1 to the NVIC_ISPR bit corresponding to:
-                ///  An interrupt that is pending has no effect.
-                ///  A disabled interrupt sets the state of that interrupt to pending.
-                SETPEND: u32,
-            }),
-            reserved57984: [124]u8,
-            ///  Use the Interrupt Clear-Pending Register to clear pending interrupts and determine which interrupts are currently pending.
-            NVIC_ICPR: mmio.Mmio(packed struct(u32) {
-                ///  Interrupt clear-pending bits.
-                ///  Write:
-                ///  0 = No effect.
-                ///  1 = Removes pending state and interrupt.
-                ///  Read:
-                ///  0 = Interrupt is not pending.
-                ///  1 = Interrupt is pending.
-                CLRPEND: u32,
-            }),
-            reserved58368: [380]u8,
-            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
-            ///  Note: Writing 1 to an NVIC_ICPR bit does not affect the active state of the corresponding interrupt.
-            ///  These registers are only word-accessible
-            NVIC_IPR0: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  Priority of interrupt 0
-                IP_0: u2,
-                reserved14: u6,
-                ///  Priority of interrupt 1
-                IP_1: u2,
-                reserved22: u6,
-                ///  Priority of interrupt 2
-                IP_2: u2,
-                reserved30: u6,
-                ///  Priority of interrupt 3
-                IP_3: u2,
-            }),
-            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
-            NVIC_IPR1: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  Priority of interrupt 4
-                IP_4: u2,
-                reserved14: u6,
-                ///  Priority of interrupt 5
-                IP_5: u2,
-                reserved22: u6,
-                ///  Priority of interrupt 6
-                IP_6: u2,
-                reserved30: u6,
-                ///  Priority of interrupt 7
-                IP_7: u2,
-            }),
-            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
-            NVIC_IPR2: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  Priority of interrupt 8
-                IP_8: u2,
-                reserved14: u6,
-                ///  Priority of interrupt 9
-                IP_9: u2,
-                reserved22: u6,
-                ///  Priority of interrupt 10
-                IP_10: u2,
-                reserved30: u6,
-                ///  Priority of interrupt 11
-                IP_11: u2,
-            }),
-            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
-            NVIC_IPR3: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  Priority of interrupt 12
-                IP_12: u2,
-                reserved14: u6,
-                ///  Priority of interrupt 13
-                IP_13: u2,
-                reserved22: u6,
-                ///  Priority of interrupt 14
-                IP_14: u2,
-                reserved30: u6,
-                ///  Priority of interrupt 15
-                IP_15: u2,
-            }),
-            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
-            NVIC_IPR4: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  Priority of interrupt 16
-                IP_16: u2,
-                reserved14: u6,
-                ///  Priority of interrupt 17
-                IP_17: u2,
-                reserved22: u6,
-                ///  Priority of interrupt 18
-                IP_18: u2,
-                reserved30: u6,
-                ///  Priority of interrupt 19
-                IP_19: u2,
-            }),
-            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
-            NVIC_IPR5: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  Priority of interrupt 20
-                IP_20: u2,
-                reserved14: u6,
-                ///  Priority of interrupt 21
-                IP_21: u2,
-                reserved22: u6,
-                ///  Priority of interrupt 22
-                IP_22: u2,
-                reserved30: u6,
-                ///  Priority of interrupt 23
-                IP_23: u2,
-            }),
-            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
-            NVIC_IPR6: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  Priority of interrupt 24
-                IP_24: u2,
-                reserved14: u6,
-                ///  Priority of interrupt 25
-                IP_25: u2,
-                reserved22: u6,
-                ///  Priority of interrupt 26
-                IP_26: u2,
-                reserved30: u6,
-                ///  Priority of interrupt 27
-                IP_27: u2,
-            }),
-            ///  Use the Interrupt Priority Registers to assign a priority from 0 to 3 to each of the available interrupts. 0 is the highest priority, and 3 is the lowest.
-            NVIC_IPR7: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  Priority of interrupt 28
-                IP_28: u2,
-                reserved14: u6,
-                ///  Priority of interrupt 29
-                IP_29: u2,
-                reserved22: u6,
-                ///  Priority of interrupt 30
-                IP_30: u2,
-                reserved30: u6,
-                ///  Priority of interrupt 31
-                IP_31: u2,
-            }),
-            reserved60672: [2272]u8,
-            ///  Read the CPU ID Base Register to determine: the ID number of the processor core, the version number of the processor core, the implementation details of the processor core.
-            CPUID: mmio.Mmio(packed struct(u32) {
-                ///  Minor revision number m in the rnpm revision status:
-                ///  0x1 = Patch 1.
-                REVISION: u4,
-                ///  Number of processor within family: 0xC60 = Cortex-M0+
-                PARTNO: u12,
-                ///  Constant that defines the architecture of the processor:
-                ///  0xC = ARMv6-M architecture.
-                ARCHITECTURE: u4,
-                ///  Major revision number n in the rnpm revision status:
-                ///  0x0 = Revision 0.
-                VARIANT: u4,
-                ///  Implementor code: 0x41 = ARM
-                IMPLEMENTER: u8,
-            }),
-            ///  Use the Interrupt Control State Register to set a pending Non-Maskable Interrupt (NMI), set or clear a pending PendSV, set or clear a pending SysTick, check for pending exceptions, check the vector number of the highest priority pended exception, check the vector number of the active exception.
-            ICSR: mmio.Mmio(packed struct(u32) {
-                ///  Active exception number field. Reset clears the VECTACTIVE field.
-                VECTACTIVE: u9,
-                reserved12: u3,
-                ///  Indicates the exception number for the highest priority pending exception: 0 = no pending exceptions. Non zero = The pending state includes the effect of memory-mapped enable and mask registers. It does not include the PRIMASK special-purpose register qualifier.
-                VECTPENDING: u9,
-                reserved22: u1,
-                ///  External interrupt pending flag
-                ISRPENDING: u1,
-                ///  The system can only access this bit when the core is halted. It indicates that a pending interrupt is to be taken in the next running cycle. If C_MASKINTS is clear in the Debug Halting Control and Status Register, the interrupt is serviced.
-                ISRPREEMPT: u1,
-                reserved25: u1,
-                ///  SysTick exception clear-pending bit.
-                ///  Write:
-                ///  0 = No effect.
-                ///  1 = Removes the pending state from the SysTick exception.
-                ///  This bit is WO. On a register read its value is Unknown.
-                PENDSTCLR: u1,
-                ///  SysTick exception set-pending bit.
-                ///  Write:
-                ///  0 = No effect.
-                ///  1 = Changes SysTick exception state to pending.
-                ///  Read:
-                ///  0 = SysTick exception is not pending.
-                ///  1 = SysTick exception is pending.
-                PENDSTSET: u1,
-                ///  PendSV clear-pending bit.
-                ///  Write:
-                ///  0 = No effect.
-                ///  1 = Removes the pending state from the PendSV exception.
-                PENDSVCLR: u1,
-                ///  PendSV set-pending bit.
-                ///  Write:
-                ///  0 = No effect.
-                ///  1 = Changes PendSV exception state to pending.
-                ///  Read:
-                ///  0 = PendSV exception is not pending.
-                ///  1 = PendSV exception is pending.
-                ///  Writing 1 to this bit is the only way to set the PendSV exception state to pending.
-                PENDSVSET: u1,
-                reserved31: u2,
-                ///  Setting this bit will activate an NMI. Since NMI is the highest priority exception, it will activate as soon as it is registered.
-                ///  NMI set-pending bit.
-                ///  Write:
-                ///  0 = No effect.
-                ///  1 = Changes NMI exception state to pending.
-                ///  Read:
-                ///  0 = NMI exception is not pending.
-                ///  1 = NMI exception is pending.
-                ///  Because NMI is the highest-priority exception, normally the processor enters the NMI
-                ///  exception handler as soon as it detects a write of 1 to this bit. Entering the handler then clears
-                ///  this bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if the
-                ///  NMI signal is reasserted while the processor is executing that handler.
-                NMIPENDSET: u1,
-            }),
-            ///  The VTOR holds the vector table offset address.
-            VTOR: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Bits [31:8] of the indicate the vector table offset address.
-                TBLOFF: u24,
-            }),
-            ///  Use the Application Interrupt and Reset Control Register to: determine data endianness, clear all active state information from debug halt mode, request a system reset.
-            AIRCR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Clears all active state information for fixed and configurable exceptions. This bit: is self-clearing, can only be set by the DAP when the core is halted. When set: clears all active exception status of the processor, forces a return to Thread mode, forces an IPSR of 0. A debugger must re-initialize the stack.
-                VECTCLRACTIVE: u1,
-                ///  Writing 1 to this bit causes the SYSRESETREQ signal to the outer system to be asserted to request a reset. The intention is to force a large system reset of all major components except for debug. The C_HALT bit in the DHCSR is cleared as a result of the system reset requested. The debugger does not lose contact with the device.
-                SYSRESETREQ: u1,
-                reserved15: u12,
-                ///  Data endianness implemented:
-                ///  0 = Little-endian.
-                ENDIANESS: u1,
-                ///  Register key:
-                ///  Reads as Unknown
-                ///  On writes, write 0x05FA to VECTKEY, otherwise the write is ignored.
-                VECTKEY: u16,
-            }),
-            ///  System Control Register. Use the System Control Register for power-management functions: signal to the system when the processor can enter a low power state, control how the processor enters and exits low power states.
-            SCR: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Indicates sleep-on-exit when returning from Handler mode to Thread mode:
-                ///  0 = Do not sleep when returning to Thread mode.
-                ///  1 = Enter sleep, or deep sleep, on return from an ISR to Thread mode.
-                ///  Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty main application.
-                SLEEPONEXIT: u1,
-                ///  Controls whether the processor uses sleep or deep sleep as its low power mode:
-                ///  0 = Sleep.
-                ///  1 = Deep sleep.
-                SLEEPDEEP: u1,
-                reserved4: u1,
-                ///  Send Event on Pending bit:
-                ///  0 = Only enabled interrupts or events can wakeup the processor, disabled interrupts are excluded.
-                ///  1 = Enabled events and all interrupts, including disabled interrupts, can wakeup the processor.
-                ///  When an event or interrupt becomes pending, the event signal wakes up the processor from WFE. If the
-                ///  processor is not waiting for an event, the event is registered and affects the next WFE.
-                ///  The processor also wakes up on execution of an SEV instruction or an external event.
-                SEVONPEND: u1,
-                padding: u27,
-            }),
-            ///  The Configuration and Control Register permanently enables stack alignment and causes unaligned accesses to result in a Hard Fault.
-            CCR: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                ///  Always reads as one, indicates that all unaligned accesses generate a HardFault.
-                UNALIGN_TRP: u1,
-                reserved9: u5,
-                ///  Always reads as one, indicates 8-byte stack alignment on exception entry. On exception entry, the processor uses bit[9] of the stacked PSR to indicate the stack alignment. On return from the exception it uses this stacked bit to restore the correct stack alignment.
-                STKALIGN: u1,
-                padding: u22,
-            }),
-            reserved60700: [4]u8,
-            ///  System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 2 to set the priority of SVCall.
-            SHPR2: mmio.Mmio(packed struct(u32) {
-                reserved30: u30,
-                ///  Priority of system handler 11, SVCall
-                PRI_11: u2,
-            }),
-            ///  System handlers are a special class of exception handler that can have their priority set to any of the priority levels. Use the System Handler Priority Register 3 to set the priority of PendSV and SysTick.
-            SHPR3: mmio.Mmio(packed struct(u32) {
-                reserved22: u22,
-                ///  Priority of system handler 14, PendSV
-                PRI_14: u2,
-                reserved30: u6,
-                ///  Priority of system handler 15, SysTick
-                PRI_15: u2,
-            }),
-            ///  Use the System Handler Control and State Register to determine or clear the pending status of SVCall.
-            SHCSR: mmio.Mmio(packed struct(u32) {
-                reserved15: u15,
-                ///  Reads as 1 if SVCall is Pending. Write 1 to set pending SVCall, write 0 to clear pending SVCall.
-                SVCALLPENDED: u1,
-                padding: u16,
-            }),
-            reserved60816: [104]u8,
-            ///  Read the MPU Type Register to determine if the processor implements an MPU, and how many regions the MPU supports.
-            MPU_TYPE: mmio.Mmio(packed struct(u32) {
-                ///  Indicates support for separate instruction and data address maps. Reads as 0 as ARMv6-M only supports a unified MPU.
-                SEPARATE: u1,
-                reserved8: u7,
-                ///  Number of regions supported by the MPU.
-                DREGION: u8,
-                ///  Instruction region. Reads as zero as ARMv6-M only supports a unified MPU.
-                IREGION: u8,
-                padding: u8,
-            }),
-            ///  Use the MPU Control Register to enable and disable the MPU, and to control whether the default memory map is enabled as a background region for privileged accesses, and whether the MPU is enabled for HardFaults and NMIs.
-            MPU_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Enables the MPU. If the MPU is disabled, privileged and unprivileged accesses use the default memory map.
-                ///  0 = MPU disabled.
-                ///  1 = MPU enabled.
-                ENABLE: u1,
-                ///  Controls the use of the MPU for HardFaults and NMIs. Setting this bit when ENABLE is clear results in UNPREDICTABLE behaviour.
-                ///  When the MPU is enabled:
-                ///  0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit.
-                ///  1 = the MPU is enabled during HardFault and NMI handlers.
-                HFNMIENA: u1,
-                ///  Controls whether the default memory map is enabled as a background region for privileged accesses. This bit is ignored when ENABLE is clear.
-                ///  0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location not
-                ///  covered by any enabled region causes a fault.
-                ///  1 = If the MPU is enabled, enables use of the default memory map as a background region for privileged software accesses.
-                ///  When enabled, the background region acts as if it is region number -1. Any region that is defined and enabled has priority over this default map.
-                PRIVDEFENA: u1,
-                padding: u29,
-            }),
-            ///  Use the MPU Region Number Register to select the region currently accessed by MPU_RBAR and MPU_RASR.
-            MPU_RNR: mmio.Mmio(packed struct(u32) {
-                ///  Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.
-                ///  The MPU supports 8 memory regions, so the permitted values of this field are 0-7.
-                REGION: u4,
-                padding: u28,
-            }),
-            ///  Read the MPU Region Base Address Register to determine the base address of the region identified by MPU_RNR. Write to update the base address of said region or that of a specified region, with whose number MPU_RNR will also be updated.
-            MPU_RBAR: mmio.Mmio(packed struct(u32) {
-                ///  On writes, specifies the number of the region whose base address to update provided VALID is set written as 1. On reads, returns bits [3:0] of MPU_RNR.
-                REGION: u4,
-                ///  On writes, indicates whether the write must update the base address of the region identified by the REGION field, updating the MPU_RNR to indicate this new region.
-                ///  Write:
-                ///  0 = MPU_RNR not changed, and the processor:
-                ///  Updates the base address for the region specified in the MPU_RNR.
-                ///  Ignores the value of the REGION field.
-                ///  1 = The processor:
-                ///  Updates the value of the MPU_RNR to the value of the REGION field.
-                ///  Updates the base address for the region specified in the REGION field.
-                ///  Always reads as zero.
-                VALID: u1,
-                reserved8: u3,
-                ///  Base address of the region.
-                ADDR: u24,
-            }),
-            ///  Use the MPU Region Attribute and Size Register to define the size, access behaviour and memory type of the region identified by MPU_RNR, and enable that region.
-            MPU_RASR: mmio.Mmio(packed struct(u32) {
-                ///  Enables the region.
-                ENABLE: u1,
-                ///  Indicates the region size. Region size in bytes = 2^(SIZE+1). The minimum permitted value is 7 (b00111) = 256Bytes
-                SIZE: u5,
-                reserved8: u2,
-                ///  Subregion Disable. For regions of 256 bytes or larger, each bit of this field controls whether one of the eight equal subregions is enabled.
-                SRD: u8,
-                ///  The MPU Region Attribute field. Use to define the region attribute control.
-                ///  28 = XN: Instruction access disable bit:
-                ///  0 = Instruction fetches enabled.
-                ///  1 = Instruction fetches disabled.
-                ///  26:24 = AP: Access permission field
-                ///  18 = S: Shareable bit
-                ///  17 = C: Cacheable bit
-                ///  16 = B: Bufferable bit
-                ATTRS: u16,
-            }),
-        };
-
-        ///  Register block for busfabric control signals and performance counters
-        pub const BUSCTRL = extern struct {
-            ///  Set the priority of each master for bus arbitration.
-            BUS_PRIORITY: mmio.Mmio(packed struct(u32) {
-                ///  0 - low priority, 1 - high priority
-                PROC0: u1,
-                reserved4: u3,
-                ///  0 - low priority, 1 - high priority
-                PROC1: u1,
-                reserved8: u3,
-                ///  0 - low priority, 1 - high priority
-                DMA_R: u1,
-                reserved12: u3,
-                ///  0 - low priority, 1 - high priority
-                DMA_W: u1,
-                padding: u19,
-            }),
-            ///  Bus priority acknowledge
-            BUS_PRIORITY_ACK: mmio.Mmio(packed struct(u32) {
-                ///  Goes to 1 once all arbiters have registered the new global priority levels.
-                ///  Arbiters update their local priority when servicing a new nonsequential access.
-                ///  In normal circumstances this will happen almost immediately.
-                BUS_PRIORITY_ACK: u1,
-                padding: u31,
-            }),
-            ///  Bus fabric performance counter 0
-            PERFCTR0: mmio.Mmio(packed struct(u32) {
-                ///  Busfabric saturating performance counter 0
-                ///  Count some event signal from the busfabric arbiters.
-                ///  Write any value to clear. Select an event to count using PERFSEL0
-                PERFCTR0: u24,
-                padding: u8,
-            }),
-            ///  Bus fabric performance event select for PERFCTR0
-            PERFSEL0: mmio.Mmio(packed struct(u32) {
-                ///  Select an event for PERFCTR0. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
-                PERFSEL0: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        apb_contested = 0x0,
-                        apb = 0x1,
-                        fastperi_contested = 0x2,
-                        fastperi = 0x3,
-                        sram5_contested = 0x4,
-                        sram5 = 0x5,
-                        sram4_contested = 0x6,
-                        sram4 = 0x7,
-                        sram3_contested = 0x8,
-                        sram3 = 0x9,
-                        sram2_contested = 0xa,
-                        sram2 = 0xb,
-                        sram1_contested = 0xc,
-                        sram1 = 0xd,
-                        sram0_contested = 0xe,
-                        sram0 = 0xf,
-                        xip_main_contested = 0x10,
-                        xip_main = 0x11,
-                        rom_contested = 0x12,
-                        rom = 0x13,
-                        _,
-                    },
-                },
-                padding: u27,
-            }),
-            ///  Bus fabric performance counter 1
-            PERFCTR1: mmio.Mmio(packed struct(u32) {
-                ///  Busfabric saturating performance counter 1
-                ///  Count some event signal from the busfabric arbiters.
-                ///  Write any value to clear. Select an event to count using PERFSEL1
-                PERFCTR1: u24,
-                padding: u8,
-            }),
-            ///  Bus fabric performance event select for PERFCTR1
-            PERFSEL1: mmio.Mmio(packed struct(u32) {
-                ///  Select an event for PERFCTR1. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
-                PERFSEL1: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        apb_contested = 0x0,
-                        apb = 0x1,
-                        fastperi_contested = 0x2,
-                        fastperi = 0x3,
-                        sram5_contested = 0x4,
-                        sram5 = 0x5,
-                        sram4_contested = 0x6,
-                        sram4 = 0x7,
-                        sram3_contested = 0x8,
-                        sram3 = 0x9,
-                        sram2_contested = 0xa,
-                        sram2 = 0xb,
-                        sram1_contested = 0xc,
-                        sram1 = 0xd,
-                        sram0_contested = 0xe,
-                        sram0 = 0xf,
-                        xip_main_contested = 0x10,
-                        xip_main = 0x11,
-                        rom_contested = 0x12,
-                        rom = 0x13,
-                        _,
-                    },
-                },
-                padding: u27,
-            }),
-            ///  Bus fabric performance counter 2
-            PERFCTR2: mmio.Mmio(packed struct(u32) {
-                ///  Busfabric saturating performance counter 2
-                ///  Count some event signal from the busfabric arbiters.
-                ///  Write any value to clear. Select an event to count using PERFSEL2
-                PERFCTR2: u24,
-                padding: u8,
-            }),
-            ///  Bus fabric performance event select for PERFCTR2
-            PERFSEL2: mmio.Mmio(packed struct(u32) {
-                ///  Select an event for PERFCTR2. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
-                PERFSEL2: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        apb_contested = 0x0,
-                        apb = 0x1,
-                        fastperi_contested = 0x2,
-                        fastperi = 0x3,
-                        sram5_contested = 0x4,
-                        sram5 = 0x5,
-                        sram4_contested = 0x6,
-                        sram4 = 0x7,
-                        sram3_contested = 0x8,
-                        sram3 = 0x9,
-                        sram2_contested = 0xa,
-                        sram2 = 0xb,
-                        sram1_contested = 0xc,
-                        sram1 = 0xd,
-                        sram0_contested = 0xe,
-                        sram0 = 0xf,
-                        xip_main_contested = 0x10,
-                        xip_main = 0x11,
-                        rom_contested = 0x12,
-                        rom = 0x13,
-                        _,
-                    },
-                },
-                padding: u27,
-            }),
-            ///  Bus fabric performance counter 3
-            PERFCTR3: mmio.Mmio(packed struct(u32) {
-                ///  Busfabric saturating performance counter 3
-                ///  Count some event signal from the busfabric arbiters.
-                ///  Write any value to clear. Select an event to count using PERFSEL3
-                PERFCTR3: u24,
-                padding: u8,
-            }),
-            ///  Bus fabric performance event select for PERFCTR3
-            PERFSEL3: mmio.Mmio(packed struct(u32) {
-                ///  Select an event for PERFCTR3. Count either contested accesses, or all accesses, on a downstream port of the main crossbar.
-                PERFSEL3: packed union {
-                    raw: u5,
-                    value: enum(u5) {
-                        apb_contested = 0x0,
-                        apb = 0x1,
-                        fastperi_contested = 0x2,
-                        fastperi = 0x3,
-                        sram5_contested = 0x4,
-                        sram5 = 0x5,
-                        sram4_contested = 0x6,
-                        sram4 = 0x7,
-                        sram3_contested = 0x8,
-                        sram3 = 0x9,
-                        sram2_contested = 0xa,
-                        sram2 = 0xb,
-                        sram1_contested = 0xc,
-                        sram1 = 0xd,
-                        sram0_contested = 0xe,
-                        sram0 = 0xf,
-                        xip_main_contested = 0x10,
-                        xip_main = 0x11,
-                        rom_contested = 0x12,
-                        rom = 0x13,
-                        _,
-                    },
-                },
-                padding: u27,
-            }),
-        };
-
-        pub const UART0 = extern struct {
-            ///  Data Register, UARTDR
-            UARTDR: mmio.Mmio(packed struct(u32) {
-                ///  Receive (read) data character. Transmit (write) data character.
-                DATA: u8,
-                ///  Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). In FIFO mode, this error is associated with the character at the top of the FIFO.
-                FE: u1,
-                ///  Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. In FIFO mode, this error is associated with the character at the top of the FIFO.
-                PE: u1,
-                ///  Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity and stop bits). In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.
-                BE: u1,
-                ///  Overrun error. This bit is set to 1 if data is received and the receive FIFO is already full. This is cleared to 0 once there is an empty space in the FIFO and a new character can be written to it.
-                OE: u1,
-                padding: u20,
-            }),
-            ///  Receive Status Register/Error Clear Register, UARTRSR/UARTECR
-            UARTRSR: mmio.Mmio(packed struct(u32) {
-                ///  Framing error. When set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1). This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
-                FE: u1,
-                ///  Parity error. When set to 1, it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the Line Control Register, UARTLCR_H. This bit is cleared to 0 by a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO.
-                PE: u1,
-                ///  Break error. This bit is set to 1 if a break condition was detected, indicating that the received data input was held LOW for longer than a full-word transmission time (defined as start, data, parity, and stop bits). This bit is cleared to 0 after a write to UARTECR. In FIFO mode, this error is associated with the character at the top of the FIFO. When a break occurs, only one 0 character is loaded into the FIFO. The next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.
-                BE: u1,
-                ///  Overrun error. This bit is set to 1 if data is received and the FIFO is already full. This bit is cleared to 0 by a write to UARTECR. The FIFO contents remain valid because no more data is written when the FIFO is full, only the contents of the shift register are overwritten. The CPU must now read the data, to empty the FIFO.
-                OE: u1,
-                padding: u28,
-            }),
-            reserved24: [16]u8,
-            ///  Flag Register, UARTFR
-            UARTFR: mmio.Mmio(packed struct(u32) {
-                ///  Clear to send. This bit is the complement of the UART clear to send, nUARTCTS, modem status input. That is, the bit is 1 when nUARTCTS is LOW.
-                CTS: u1,
-                ///  Data set ready. This bit is the complement of the UART data set ready, nUARTDSR, modem status input. That is, the bit is 1 when nUARTDSR is LOW.
-                DSR: u1,
-                ///  Data carrier detect. This bit is the complement of the UART data carrier detect, nUARTDCD, modem status input. That is, the bit is 1 when nUARTDCD is LOW.
-                DCD: u1,
-                ///  UART busy. If this bit is set to 1, the UART is busy transmitting data. This bit remains set until the complete byte, including all the stop bits, has been sent from the shift register. This bit is set as soon as the transmit FIFO becomes non-empty, regardless of whether the UART is enabled or not.
-                BUSY: u1,
-                ///  Receive FIFO empty. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is empty. If the FIFO is enabled, the RXFE bit is set when the receive FIFO is empty.
-                RXFE: u1,
-                ///  Transmit FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the transmit holding register is full. If the FIFO is enabled, the TXFF bit is set when the transmit FIFO is full.
-                TXFF: u1,
-                ///  Receive FIFO full. The meaning of this bit depends on the state of the FEN bit in the UARTLCR_H Register. If the FIFO is disabled, this bit is set when the receive holding register is full. If the FIFO is enabled, the RXFF bit is set when the receive FIFO is full.
-                RXFF: u1,
-                ///  Transmit FIFO empty. The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_H. If the FIFO is disabled, this bit is set when the transmit holding register is empty. If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.
-                TXFE: u1,
-                ///  Ring indicator. This bit is the complement of the UART ring indicator, nUARTRI, modem status input. That is, the bit is 1 when nUARTRI is LOW.
-                RI: u1,
-                padding: u23,
-            }),
-            reserved32: [4]u8,
-            ///  IrDA Low-Power Counter Register, UARTILPR
-            UARTILPR: mmio.Mmio(packed struct(u32) {
-                ///  8-bit low-power divisor value. These bits are cleared to 0 at reset.
-                ILPDVSR: u8,
-                padding: u24,
-            }),
-            ///  Integer Baud Rate Register, UARTIBRD
-            UARTIBRD: mmio.Mmio(packed struct(u32) {
-                ///  The integer baud rate divisor. These bits are cleared to 0 on reset.
-                BAUD_DIVINT: u16,
-                padding: u16,
-            }),
-            ///  Fractional Baud Rate Register, UARTFBRD
-            UARTFBRD: mmio.Mmio(packed struct(u32) {
-                ///  The fractional baud rate divisor. These bits are cleared to 0 on reset.
-                BAUD_DIVFRAC: u6,
-                padding: u26,
-            }),
-            ///  Line Control Register, UARTLCR_H
-            UARTLCR_H: mmio.Mmio(packed struct(u32) {
-                ///  Send break. If this bit is set to 1, a low-level is continually output on the UARTTXD output, after completing transmission of the current character. For the proper execution of the break command, the software must set this bit for at least two complete frames. For normal use, this bit must be cleared to 0.
-                BRK: u1,
-                ///  Parity enable: 0 = parity is disabled and no parity bit added to the data frame 1 = parity checking and generation is enabled.
-                PEN: u1,
-                ///  Even parity select. Controls the type of parity the UART uses during transmission and reception: 0 = odd parity. The UART generates or checks for an odd number of 1s in the data and parity bits. 1 = even parity. The UART generates or checks for an even number of 1s in the data and parity bits. This bit has no effect when the PEN bit disables parity checking and generation.
-                EPS: u1,
-                ///  Two stop bits select. If this bit is set to 1, two stop bits are transmitted at the end of the frame. The receive logic does not check for two stop bits being received.
-                STP2: u1,
-                ///  Enable FIFOs: 0 = FIFOs are disabled (character mode) that is, the FIFOs become 1-byte-deep holding registers 1 = transmit and receive FIFO buffers are enabled (FIFO mode).
-                FEN: u1,
-                ///  Word length. These bits indicate the number of data bits transmitted or received in a frame as follows: b11 = 8 bits b10 = 7 bits b01 = 6 bits b00 = 5 bits.
-                WLEN: u2,
-                ///  Stick parity select. 0 = stick parity is disabled 1 = either: * if the EPS bit is 0 then the parity bit is transmitted and checked as a 1 * if the EPS bit is 1 then the parity bit is transmitted and checked as a 0. This bit has no effect when the PEN bit disables parity checking and generation.
-                SPS: u1,
-                padding: u24,
-            }),
-            ///  Control Register, UARTCR
-            UARTCR: mmio.Mmio(packed struct(u32) {
-                ///  UART enable: 0 = UART is disabled. If the UART is disabled in the middle of transmission or reception, it completes the current character before stopping. 1 = the UART is enabled. Data transmission and reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit.
-                UARTEN: u1,
-                ///  SIR enable: 0 = IrDA SIR ENDEC is disabled. nSIROUT remains LOW (no light pulse generated), and signal transitions on SIRIN have no effect. 1 = IrDA SIR ENDEC is enabled. Data is transmitted and received on nSIROUT and SIRIN. UARTTXD remains HIGH, in the marking state. Signal transitions on UARTRXD or modem status inputs have no effect. This bit has no effect if the UARTEN bit disables the UART.
-                SIREN: u1,
-                ///  SIR low-power IrDA mode. This bit selects the IrDA encoding mode. If this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3 / 16th of the bit period. If this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the IrLPBaud16 input signal, regardless of the selected bit rate. Setting this bit uses less power, but might reduce transmission distances.
-                SIRLP: u1,
-                reserved7: u4,
-                ///  Loopback enable. If this bit is set to 1 and the SIREN bit is set to 1 and the SIRTEST bit in the Test Control Register, UARTTCR is set to 1, then the nSIROUT path is inverted, and fed through to the SIRIN path. The SIRTEST bit in the test register must be set to 1 to override the normal half-duplex SIR operation. This must be the requirement for accessing the test registers during normal operation, and SIRTEST must be cleared to 0 when loopback testing is finished. This feature reduces the amount of external coupling required during system test. If this bit is set to 1, and the SIRTEST bit is set to 0, the UARTTXD path is fed through to the UARTRXD path. In either SIR mode or UART mode, when this bit is set, the modem outputs are also fed through to the modem inputs. This bit is cleared to 0 on reset, to disable loopback.
-                LBE: u1,
-                ///  Transmit enable. If this bit is set to 1, the transmit section of the UART is enabled. Data transmission occurs for either UART signals, or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of transmission, it completes the current character before stopping.
-                TXE: u1,
-                ///  Receive enable. If this bit is set to 1, the receive section of the UART is enabled. Data reception occurs for either UART signals or SIR signals depending on the setting of the SIREN bit. When the UART is disabled in the middle of reception, it completes the current character before stopping.
-                RXE: u1,
-                ///  Data transmit ready. This bit is the complement of the UART data transmit ready, nUARTDTR, modem status output. That is, when the bit is programmed to a 1 then nUARTDTR is LOW.
-                DTR: u1,
-                ///  Request to send. This bit is the complement of the UART request to send, nUARTRTS, modem status output. That is, when the bit is programmed to a 1 then nUARTRTS is LOW.
-                RTS: u1,
-                ///  This bit is the complement of the UART Out1 (nUARTOut1) modem status output. That is, when the bit is programmed to a 1 the output is 0. For DTE this can be used as Data Carrier Detect (DCD).
-                OUT1: u1,
-                ///  This bit is the complement of the UART Out2 (nUARTOut2) modem status output. That is, when the bit is programmed to a 1, the output is 0. For DTE this can be used as Ring Indicator (RI).
-                OUT2: u1,
-                ///  RTS hardware flow control enable. If this bit is set to 1, RTS hardware flow control is enabled. Data is only requested when there is space in the receive FIFO for it to be received.
-                RTSEN: u1,
-                ///  CTS hardware flow control enable. If this bit is set to 1, CTS hardware flow control is enabled. Data is only transmitted when the nUARTCTS signal is asserted.
-                CTSEN: u1,
-                padding: u16,
-            }),
-            ///  Interrupt FIFO Level Select Register, UARTIFLS
-            UARTIFLS: mmio.Mmio(packed struct(u32) {
-                ///  Transmit interrupt FIFO level select. The trigger points for the transmit interrupt are as follows: b000 = Transmit FIFO becomes <= 1 / 8 full b001 = Transmit FIFO becomes <= 1 / 4 full b010 = Transmit FIFO becomes <= 1 / 2 full b011 = Transmit FIFO becomes <= 3 / 4 full b100 = Transmit FIFO becomes <= 7 / 8 full b101-b111 = reserved.
-                TXIFLSEL: u3,
-                ///  Receive interrupt FIFO level select. The trigger points for the receive interrupt are as follows: b000 = Receive FIFO becomes >= 1 / 8 full b001 = Receive FIFO becomes >= 1 / 4 full b010 = Receive FIFO becomes >= 1 / 2 full b011 = Receive FIFO becomes >= 3 / 4 full b100 = Receive FIFO becomes >= 7 / 8 full b101-b111 = reserved.
-                RXIFLSEL: u3,
-                padding: u26,
-            }),
-            ///  Interrupt Mask Set/Clear Register, UARTIMSC
-            UARTIMSC: mmio.Mmio(packed struct(u32) {
-                ///  nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt. On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.
-                RIMIM: u1,
-                ///  nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt. On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.
-                CTSMIM: u1,
-                ///  nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt. On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.
-                DCDMIM: u1,
-                ///  nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt. On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.
-                DSRMIM: u1,
-                ///  Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt. On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.
-                RXIM: u1,
-                ///  Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt. On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.
-                TXIM: u1,
-                ///  Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt. On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.
-                RTIM: u1,
-                ///  Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt. On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.
-                FEIM: u1,
-                ///  Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt. On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.
-                PEIM: u1,
-                ///  Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt. On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.
-                BEIM: u1,
-                ///  Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt. On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.
-                OEIM: u1,
-                padding: u21,
-            }),
-            ///  Raw Interrupt Status Register, UARTRIS
-            UARTRIS: mmio.Mmio(packed struct(u32) {
-                ///  nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.
-                RIRMIS: u1,
-                ///  nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.
-                CTSRMIS: u1,
-                ///  nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.
-                DCDRMIS: u1,
-                ///  nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.
-                DSRRMIS: u1,
-                ///  Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.
-                RXRIS: u1,
-                ///  Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.
-                TXRIS: u1,
-                ///  Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt. a
-                RTRIS: u1,
-                ///  Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.
-                FERIS: u1,
-                ///  Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.
-                PERIS: u1,
-                ///  Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.
-                BERIS: u1,
-                ///  Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.
-                OERIS: u1,
-                padding: u21,
-            }),
-            ///  Masked Interrupt Status Register, UARTMIS
-            UARTMIS: mmio.Mmio(packed struct(u32) {
-                ///  nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.
-                RIMMIS: u1,
-                ///  nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.
-                CTSMMIS: u1,
-                ///  nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.
-                DCDMMIS: u1,
-                ///  nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.
-                DSRMMIS: u1,
-                ///  Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.
-                RXMIS: u1,
-                ///  Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.
-                TXMIS: u1,
-                ///  Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.
-                RTMIS: u1,
-                ///  Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.
-                FEMIS: u1,
-                ///  Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.
-                PEMIS: u1,
-                ///  Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.
-                BEMIS: u1,
-                ///  Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.
-                OEMIS: u1,
-                padding: u21,
-            }),
-            ///  Interrupt Clear Register, UARTICR
-            UARTICR: mmio.Mmio(packed struct(u32) {
-                ///  nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.
-                RIMIC: u1,
-                ///  nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.
-                CTSMIC: u1,
-                ///  nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.
-                DCDMIC: u1,
-                ///  nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.
-                DSRMIC: u1,
-                ///  Receive interrupt clear. Clears the UARTRXINTR interrupt.
-                RXIC: u1,
-                ///  Transmit interrupt clear. Clears the UARTTXINTR interrupt.
-                TXIC: u1,
-                ///  Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.
-                RTIC: u1,
-                ///  Framing error interrupt clear. Clears the UARTFEINTR interrupt.
-                FEIC: u1,
-                ///  Parity error interrupt clear. Clears the UARTPEINTR interrupt.
-                PEIC: u1,
-                ///  Break error interrupt clear. Clears the UARTBEINTR interrupt.
-                BEIC: u1,
-                ///  Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
-                OEIC: u1,
-                padding: u21,
-            }),
-            ///  DMA Control Register, UARTDMACR
-            UARTDMACR: mmio.Mmio(packed struct(u32) {
-                ///  Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
-                RXDMAE: u1,
-                ///  Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
-                TXDMAE: u1,
-                ///  DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.
-                DMAONERR: u1,
-                padding: u29,
-            }),
-            reserved4064: [3988]u8,
-            ///  UARTPeriphID0 Register
-            UARTPERIPHID0: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x11
-                PARTNUMBER0: u8,
-                padding: u24,
-            }),
-            ///  UARTPeriphID1 Register
-            UARTPERIPHID1: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x0
-                PARTNUMBER1: u4,
-                ///  These bits read back as 0x1
-                DESIGNER0: u4,
-                padding: u24,
-            }),
-            ///  UARTPeriphID2 Register
-            UARTPERIPHID2: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x4
-                DESIGNER1: u4,
-                ///  This field depends on the revision of the UART: r1p0 0x0 r1p1 0x1 r1p3 0x2 r1p4 0x2 r1p5 0x3
-                REVISION: u4,
-                padding: u24,
-            }),
-            ///  UARTPeriphID3 Register
-            UARTPERIPHID3: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x00
-                CONFIGURATION: u8,
-                padding: u24,
-            }),
-            ///  UARTPCellID0 Register
-            UARTPCELLID0: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x0D
-                UARTPCELLID0: u8,
-                padding: u24,
-            }),
-            ///  UARTPCellID1 Register
-            UARTPCELLID1: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0xF0
-                UARTPCELLID1: u8,
-                padding: u24,
-            }),
-            ///  UARTPCellID2 Register
-            UARTPCELLID2: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x05
-                UARTPCELLID2: u8,
-                padding: u24,
-            }),
-            ///  UARTPCellID3 Register
-            UARTPCELLID3: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0xB1
-                UARTPCELLID3: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  Single-cycle IO block
-        ///  Provides core-local and inter-core hardware for the two processors, with single-cycle access.
-        pub const SIO = extern struct {
-            ///  Processor core identifier
-            ///  Value is 0 when read from processor core 0, and 1 when read from processor core 1.
-            CPUID: u32,
-            ///  Input value for GPIO pins
-            GPIO_IN: mmio.Mmio(packed struct(u32) {
-                ///  Input value for GPIO0...29
-                GPIO_IN: u30,
-                padding: u2,
-            }),
-            ///  Input value for QSPI pins
-            GPIO_HI_IN: mmio.Mmio(packed struct(u32) {
-                ///  Input value on QSPI IO in order 0..5: SCLK, SSn, SD0, SD1, SD2, SD3
-                GPIO_HI_IN: u6,
-                padding: u26,
-            }),
-            reserved16: [4]u8,
-            ///  GPIO output value
-            GPIO_OUT: mmio.Mmio(packed struct(u32) {
-                ///  Set output level (1/0 -> high/low) for GPIO0...29.
-                ///  Reading back gives the last value written, NOT the input value from the pins.
-                ///  If core 0 and core 1 both write to GPIO_OUT simultaneously (or to a SET/CLR/XOR alias),
-                ///  the result is as though the write from core 0 took place first,
-                ///  and the write from core 1 was then applied to that intermediate result.
-                GPIO_OUT: u30,
-                padding: u2,
-            }),
-            ///  GPIO output value set
-            GPIO_OUT_SET: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bit-set on GPIO_OUT, i.e. `GPIO_OUT |= wdata`
-                GPIO_OUT_SET: u30,
-                padding: u2,
-            }),
-            ///  GPIO output value clear
-            GPIO_OUT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bit-clear on GPIO_OUT, i.e. `GPIO_OUT &= ~wdata`
-                GPIO_OUT_CLR: u30,
-                padding: u2,
-            }),
-            ///  GPIO output value XOR
-            GPIO_OUT_XOR: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bitwise XOR on GPIO_OUT, i.e. `GPIO_OUT ^= wdata`
-                GPIO_OUT_XOR: u30,
-                padding: u2,
-            }),
-            ///  GPIO output enable
-            GPIO_OE: mmio.Mmio(packed struct(u32) {
-                ///  Set output enable (1/0 -> output/input) for GPIO0...29.
-                ///  Reading back gives the last value written.
-                ///  If core 0 and core 1 both write to GPIO_OE simultaneously (or to a SET/CLR/XOR alias),
-                ///  the result is as though the write from core 0 took place first,
-                ///  and the write from core 1 was then applied to that intermediate result.
-                GPIO_OE: u30,
-                padding: u2,
-            }),
-            ///  GPIO output enable set
-            GPIO_OE_SET: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bit-set on GPIO_OE, i.e. `GPIO_OE |= wdata`
-                GPIO_OE_SET: u30,
-                padding: u2,
-            }),
-            ///  GPIO output enable clear
-            GPIO_OE_CLR: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bit-clear on GPIO_OE, i.e. `GPIO_OE &= ~wdata`
-                GPIO_OE_CLR: u30,
-                padding: u2,
-            }),
-            ///  GPIO output enable XOR
-            GPIO_OE_XOR: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bitwise XOR on GPIO_OE, i.e. `GPIO_OE ^= wdata`
-                GPIO_OE_XOR: u30,
-                padding: u2,
-            }),
-            ///  QSPI output value
-            GPIO_HI_OUT: mmio.Mmio(packed struct(u32) {
-                ///  Set output level (1/0 -> high/low) for QSPI IO0...5.
-                ///  Reading back gives the last value written, NOT the input value from the pins.
-                ///  If core 0 and core 1 both write to GPIO_HI_OUT simultaneously (or to a SET/CLR/XOR alias),
-                ///  the result is as though the write from core 0 took place first,
-                ///  and the write from core 1 was then applied to that intermediate result.
-                GPIO_HI_OUT: u6,
-                padding: u26,
-            }),
-            ///  QSPI output value set
-            GPIO_HI_OUT_SET: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bit-set on GPIO_HI_OUT, i.e. `GPIO_HI_OUT |= wdata`
-                GPIO_HI_OUT_SET: u6,
-                padding: u26,
-            }),
-            ///  QSPI output value clear
-            GPIO_HI_OUT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bit-clear on GPIO_HI_OUT, i.e. `GPIO_HI_OUT &= ~wdata`
-                GPIO_HI_OUT_CLR: u6,
-                padding: u26,
-            }),
-            ///  QSPI output value XOR
-            GPIO_HI_OUT_XOR: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bitwise XOR on GPIO_HI_OUT, i.e. `GPIO_HI_OUT ^= wdata`
-                GPIO_HI_OUT_XOR: u6,
-                padding: u26,
-            }),
-            ///  QSPI output enable
-            GPIO_HI_OE: mmio.Mmio(packed struct(u32) {
-                ///  Set output enable (1/0 -> output/input) for QSPI IO0...5.
-                ///  Reading back gives the last value written.
-                ///  If core 0 and core 1 both write to GPIO_HI_OE simultaneously (or to a SET/CLR/XOR alias),
-                ///  the result is as though the write from core 0 took place first,
-                ///  and the write from core 1 was then applied to that intermediate result.
-                GPIO_HI_OE: u6,
-                padding: u26,
-            }),
-            ///  QSPI output enable set
-            GPIO_HI_OE_SET: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bit-set on GPIO_HI_OE, i.e. `GPIO_HI_OE |= wdata`
-                GPIO_HI_OE_SET: u6,
-                padding: u26,
-            }),
-            ///  QSPI output enable clear
-            GPIO_HI_OE_CLR: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bit-clear on GPIO_HI_OE, i.e. `GPIO_HI_OE &= ~wdata`
-                GPIO_HI_OE_CLR: u6,
-                padding: u26,
-            }),
-            ///  QSPI output enable XOR
-            GPIO_HI_OE_XOR: mmio.Mmio(packed struct(u32) {
-                ///  Perform an atomic bitwise XOR on GPIO_HI_OE, i.e. `GPIO_HI_OE ^= wdata`
-                GPIO_HI_OE_XOR: u6,
-                padding: u26,
-            }),
-            ///  Status register for inter-core FIFOs (mailboxes).
-            ///  There is one FIFO in the core 0 -> core 1 direction, and one core 1 -> core 0. Both are 32 bits wide and 8 words deep.
-            ///  Core 0 can see the read side of the 1->0 FIFO (RX), and the write side of 0->1 FIFO (TX).
-            ///  Core 1 can see the read side of the 0->1 FIFO (RX), and the write side of 1->0 FIFO (TX).
-            ///  The SIO IRQ for each core is the logical OR of the VLD, WOF and ROE fields of its FIFO_ST register.
-            FIFO_ST: mmio.Mmio(packed struct(u32) {
-                ///  Value is 1 if this core's RX FIFO is not empty (i.e. if FIFO_RD is valid)
-                VLD: u1,
-                ///  Value is 1 if this core's TX FIFO is not full (i.e. if FIFO_WR is ready for more data)
-                RDY: u1,
-                ///  Sticky flag indicating the TX FIFO was written when full. This write was ignored by the FIFO.
-                WOF: u1,
-                ///  Sticky flag indicating the RX FIFO was read when empty. This read was ignored by the FIFO.
-                ROE: u1,
-                padding: u28,
-            }),
-            ///  Write access to this core's TX FIFO
-            FIFO_WR: u32,
-            ///  Read access to this core's RX FIFO
-            FIFO_RD: u32,
-            ///  Spinlock state
-            ///  A bitmap containing the state of all 32 spinlocks (1=locked).
-            ///  Mainly intended for debugging.
-            SPINLOCK_ST: u32,
-            ///  Divider unsigned dividend
-            ///  Write to the DIVIDEND operand of the divider, i.e. the p in `p / q`.
-            ///  Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
-            ///  UDIVIDEND/SDIVIDEND are aliases of the same internal register. The U alias starts an
-            ///  unsigned calculation, and the S alias starts a signed calculation.
-            DIV_UDIVIDEND: u32,
-            ///  Divider unsigned divisor
-            ///  Write to the DIVISOR operand of the divider, i.e. the q in `p / q`.
-            ///  Any operand write starts a new calculation. The results appear in QUOTIENT, REMAINDER.
-            ///  UDIVISOR/SDIVISOR are aliases of the same internal register. The U alias starts an
-            ///  unsigned calculation, and the S alias starts a signed calculation.
-            DIV_UDIVISOR: u32,
-            ///  Divider signed dividend
-            ///  The same as UDIVIDEND, but starts a signed calculation, rather than unsigned.
-            DIV_SDIVIDEND: u32,
-            ///  Divider signed divisor
-            ///  The same as UDIVISOR, but starts a signed calculation, rather than unsigned.
-            DIV_SDIVISOR: u32,
-            ///  Divider result quotient
-            ///  The result of `DIVIDEND / DIVISOR` (division). Contents undefined while CSR_READY is low.
-            ///  For signed calculations, QUOTIENT is negative when the signs of DIVIDEND and DIVISOR differ.
-            ///  This register can be written to directly, for context save/restore purposes. This halts any
-            ///  in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
-            ///  Reading from QUOTIENT clears the CSR_DIRTY flag, so should read results in the order
-            ///  REMAINDER, QUOTIENT if CSR_DIRTY is used.
-            DIV_QUOTIENT: u32,
-            ///  Divider result remainder
-            ///  The result of `DIVIDEND % DIVISOR` (modulo). Contents undefined while CSR_READY is low.
-            ///  For signed calculations, REMAINDER is negative only when DIVIDEND is negative.
-            ///  This register can be written to directly, for context save/restore purposes. This halts any
-            ///  in-progress calculation and sets the CSR_READY and CSR_DIRTY flags.
-            DIV_REMAINDER: u32,
-            ///  Control and status register for divider.
-            DIV_CSR: mmio.Mmio(packed struct(u32) {
-                ///  Reads as 0 when a calculation is in progress, 1 otherwise.
-                ///  Writing an operand (xDIVIDEND, xDIVISOR) will immediately start a new calculation, no
-                ///  matter if one is already in progress.
-                ///  Writing to a result register will immediately terminate any in-progress calculation
-                ///  and set the READY and DIRTY flags.
-                READY: u1,
-                ///  Changes to 1 when any register is written, and back to 0 when QUOTIENT is read.
-                ///  Software can use this flag to make save/restore more efficient (skip if not DIRTY).
-                ///  If the flag is used in this way, it's recommended to either read QUOTIENT only,
-                ///  or REMAINDER and then QUOTIENT, to prevent data loss on context switch.
-                DIRTY: u1,
-                padding: u30,
-            }),
-            reserved128: [4]u8,
-            ///  Read/write access to accumulator 0
-            INTERP0_ACCUM0: u32,
-            ///  Read/write access to accumulator 1
-            INTERP0_ACCUM1: u32,
-            ///  Read/write access to BASE0 register.
-            INTERP0_BASE0: u32,
-            ///  Read/write access to BASE1 register.
-            INTERP0_BASE1: u32,
-            ///  Read/write access to BASE2 register.
-            INTERP0_BASE2: u32,
-            ///  Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
-            INTERP0_POP_LANE0: u32,
-            ///  Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
-            INTERP0_POP_LANE1: u32,
-            ///  Read FULL result, and simultaneously write lane results to both accumulators (POP).
-            INTERP0_POP_FULL: u32,
-            ///  Read LANE0 result, without altering any internal state (PEEK).
-            INTERP0_PEEK_LANE0: u32,
-            ///  Read LANE1 result, without altering any internal state (PEEK).
-            INTERP0_PEEK_LANE1: u32,
-            ///  Read FULL result, without altering any internal state (PEEK).
-            INTERP0_PEEK_FULL: u32,
-            ///  Control register for lane 0
-            INTERP0_CTRL_LANE0: mmio.Mmio(packed struct(u32) {
-                ///  Logical right-shift applied to accumulator before masking
-                SHIFT: u5,
-                ///  The least-significant bit allowed to pass by the mask (inclusive)
-                MASK_LSB: u5,
-                ///  The most-significant bit allowed to pass by the mask (inclusive)
-                ///  Setting MSB < LSB may cause chip to turn inside-out
-                MASK_MSB: u5,
-                ///  If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
-                ///  before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
-                SIGNED: u1,
-                ///  If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.
-                ///  Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
-                CROSS_INPUT: u1,
-                ///  If 1, feed the opposite lane's result into this lane's accumulator on POP.
-                CROSS_RESULT: u1,
-                ///  If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
-                ADD_RAW: u1,
-                ///  ORed into bits 29:28 of the lane result presented to the processor on the bus.
-                ///  No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
-                ///  of pointers into flash or SRAM.
-                FORCE_MSB: u2,
-                ///  Only present on INTERP0 on each core. If BLEND mode is enabled:
-                ///  - LANE1 result is a linear interpolation between BASE0 and BASE1, controlled
-                ///  by the 8 LSBs of lane 1 shift and mask value (a fractional number between
-                ///  0 and 255/256ths)
-                ///  - LANE0 result does not have BASE0 added (yields only the 8 LSBs of lane 1 shift+mask value)
-                ///  - FULL result does not have lane 1 shift+mask value added (BASE2 + lane 0 shift+mask)
-                ///  LANE1 SIGNED flag controls whether the interpolation is signed or unsigned.
-                BLEND: u1,
-                reserved23: u1,
-                ///  Indicates if any masked-off MSBs in ACCUM0 are set.
-                OVERF0: u1,
-                ///  Indicates if any masked-off MSBs in ACCUM1 are set.
-                OVERF1: u1,
-                ///  Set if either OVERF0 or OVERF1 is set.
-                OVERF: u1,
-                padding: u6,
-            }),
-            ///  Control register for lane 1
-            INTERP0_CTRL_LANE1: mmio.Mmio(packed struct(u32) {
-                ///  Logical right-shift applied to accumulator before masking
-                SHIFT: u5,
-                ///  The least-significant bit allowed to pass by the mask (inclusive)
-                MASK_LSB: u5,
-                ///  The most-significant bit allowed to pass by the mask (inclusive)
-                ///  Setting MSB < LSB may cause chip to turn inside-out
-                MASK_MSB: u5,
-                ///  If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
-                ///  before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.
-                SIGNED: u1,
-                ///  If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.
-                ///  Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
-                CROSS_INPUT: u1,
-                ///  If 1, feed the opposite lane's result into this lane's accumulator on POP.
-                CROSS_RESULT: u1,
-                ///  If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
-                ADD_RAW: u1,
-                ///  ORed into bits 29:28 of the lane result presented to the processor on the bus.
-                ///  No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
-                ///  of pointers into flash or SRAM.
-                FORCE_MSB: u2,
-                padding: u11,
-            }),
-            ///  Values written here are atomically added to ACCUM0
-            ///  Reading yields lane 0's raw shift and mask value (BASE0 not added).
-            INTERP0_ACCUM0_ADD: mmio.Mmio(packed struct(u32) {
-                INTERP0_ACCUM0_ADD: u24,
-                padding: u8,
-            }),
-            ///  Values written here are atomically added to ACCUM1
-            ///  Reading yields lane 1's raw shift and mask value (BASE1 not added).
-            INTERP0_ACCUM1_ADD: mmio.Mmio(packed struct(u32) {
-                INTERP0_ACCUM1_ADD: u24,
-                padding: u8,
-            }),
-            ///  On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
-            ///  Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.
-            INTERP0_BASE_1AND0: u32,
-            ///  Read/write access to accumulator 0
-            INTERP1_ACCUM0: u32,
-            ///  Read/write access to accumulator 1
-            INTERP1_ACCUM1: u32,
-            ///  Read/write access to BASE0 register.
-            INTERP1_BASE0: u32,
-            ///  Read/write access to BASE1 register.
-            INTERP1_BASE1: u32,
-            ///  Read/write access to BASE2 register.
-            INTERP1_BASE2: u32,
-            ///  Read LANE0 result, and simultaneously write lane results to both accumulators (POP).
-            INTERP1_POP_LANE0: u32,
-            ///  Read LANE1 result, and simultaneously write lane results to both accumulators (POP).
-            INTERP1_POP_LANE1: u32,
-            ///  Read FULL result, and simultaneously write lane results to both accumulators (POP).
-            INTERP1_POP_FULL: u32,
-            ///  Read LANE0 result, without altering any internal state (PEEK).
-            INTERP1_PEEK_LANE0: u32,
-            ///  Read LANE1 result, without altering any internal state (PEEK).
-            INTERP1_PEEK_LANE1: u32,
-            ///  Read FULL result, without altering any internal state (PEEK).
-            INTERP1_PEEK_FULL: u32,
-            ///  Control register for lane 0
-            INTERP1_CTRL_LANE0: mmio.Mmio(packed struct(u32) {
-                ///  Logical right-shift applied to accumulator before masking
-                SHIFT: u5,
-                ///  The least-significant bit allowed to pass by the mask (inclusive)
-                MASK_LSB: u5,
-                ///  The most-significant bit allowed to pass by the mask (inclusive)
-                ///  Setting MSB < LSB may cause chip to turn inside-out
-                MASK_MSB: u5,
-                ///  If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
-                ///  before adding to BASE0, and LANE0 PEEK/POP appear extended to 32 bits when read by processor.
-                SIGNED: u1,
-                ///  If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.
-                ///  Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
-                CROSS_INPUT: u1,
-                ///  If 1, feed the opposite lane's result into this lane's accumulator on POP.
-                CROSS_RESULT: u1,
-                ///  If 1, mask + shift is bypassed for LANE0 result. This does not affect FULL result.
-                ADD_RAW: u1,
-                ///  ORed into bits 29:28 of the lane result presented to the processor on the bus.
-                ///  No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
-                ///  of pointers into flash or SRAM.
-                FORCE_MSB: u2,
-                reserved22: u1,
-                ///  Only present on INTERP1 on each core. If CLAMP mode is enabled:
-                ///  - LANE0 result is shifted and masked ACCUM0, clamped by a lower bound of
-                ///  BASE0 and an upper bound of BASE1.
-                ///  - Signedness of these comparisons is determined by LANE0_CTRL_SIGNED
-                CLAMP: u1,
-                ///  Indicates if any masked-off MSBs in ACCUM0 are set.
-                OVERF0: u1,
-                ///  Indicates if any masked-off MSBs in ACCUM1 are set.
-                OVERF1: u1,
-                ///  Set if either OVERF0 or OVERF1 is set.
-                OVERF: u1,
-                padding: u6,
-            }),
-            ///  Control register for lane 1
-            INTERP1_CTRL_LANE1: mmio.Mmio(packed struct(u32) {
-                ///  Logical right-shift applied to accumulator before masking
-                SHIFT: u5,
-                ///  The least-significant bit allowed to pass by the mask (inclusive)
-                MASK_LSB: u5,
-                ///  The most-significant bit allowed to pass by the mask (inclusive)
-                ///  Setting MSB < LSB may cause chip to turn inside-out
-                MASK_MSB: u5,
-                ///  If SIGNED is set, the shifted and masked accumulator value is sign-extended to 32 bits
-                ///  before adding to BASE1, and LANE1 PEEK/POP appear extended to 32 bits when read by processor.
-                SIGNED: u1,
-                ///  If 1, feed the opposite lane's accumulator into this lane's shift + mask hardware.
-                ///  Takes effect even if ADD_RAW is set (the CROSS_INPUT mux is before the shift+mask bypass)
-                CROSS_INPUT: u1,
-                ///  If 1, feed the opposite lane's result into this lane's accumulator on POP.
-                CROSS_RESULT: u1,
-                ///  If 1, mask + shift is bypassed for LANE1 result. This does not affect FULL result.
-                ADD_RAW: u1,
-                ///  ORed into bits 29:28 of the lane result presented to the processor on the bus.
-                ///  No effect on the internal 32-bit datapath. Handy for using a lane to generate sequence
-                ///  of pointers into flash or SRAM.
-                FORCE_MSB: u2,
-                padding: u11,
-            }),
-            ///  Values written here are atomically added to ACCUM0
-            ///  Reading yields lane 0's raw shift and mask value (BASE0 not added).
-            INTERP1_ACCUM0_ADD: mmio.Mmio(packed struct(u32) {
-                INTERP1_ACCUM0_ADD: u24,
-                padding: u8,
-            }),
-            ///  Values written here are atomically added to ACCUM1
-            ///  Reading yields lane 1's raw shift and mask value (BASE1 not added).
-            INTERP1_ACCUM1_ADD: mmio.Mmio(packed struct(u32) {
-                INTERP1_ACCUM1_ADD: u24,
-                padding: u8,
-            }),
-            ///  On write, the lower 16 bits go to BASE0, upper bits to BASE1 simultaneously.
-            ///  Each half is sign-extended to 32 bits if that lane's SIGNED flag is set.
-            INTERP1_BASE_1AND0: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK0: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK1: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK2: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK3: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK4: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK5: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK6: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK7: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK8: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK9: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK10: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK11: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK12: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK13: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK14: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK15: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK16: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK17: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK18: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK19: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK20: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK21: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK22: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK23: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK24: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK25: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK26: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK27: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK28: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK29: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK30: u32,
-            ///  Reading from a spinlock address will:
-            ///  - Return 0 if lock is already locked
-            ///  - Otherwise return nonzero, and simultaneously claim the lock
-            ///  Writing (any value) releases the lock.
-            ///  If core 0 and core 1 attempt to claim the same lock simultaneously, core 0 wins.
-            ///  The value returned on success is 0x1 << lock number.
-            SPINLOCK31: u32,
-        };
-
-        pub const SPI0 = extern struct {
-            ///  Control register 0, SSPCR0 on page 3-4
-            SSPCR0: mmio.Mmio(packed struct(u32) {
-                ///  Data Size Select: 0000 Reserved, undefined operation. 0001 Reserved, undefined operation. 0010 Reserved, undefined operation. 0011 4-bit data. 0100 5-bit data. 0101 6-bit data. 0110 7-bit data. 0111 8-bit data. 1000 9-bit data. 1001 10-bit data. 1010 11-bit data. 1011 12-bit data. 1100 13-bit data. 1101 14-bit data. 1110 15-bit data. 1111 16-bit data.
-                DSS: u4,
-                ///  Frame format: 00 Motorola SPI frame format. 01 TI synchronous serial frame format. 10 National Microwire frame format. 11 Reserved, undefined operation.
-                FRF: u2,
-                ///  SSPCLKOUT polarity, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.
-                SPO: u1,
-                ///  SSPCLKOUT phase, applicable to Motorola SPI frame format only. See Motorola SPI frame format on page 2-10.
-                SPH: u1,
-                ///  Serial clock rate. The value SCR is used to generate the transmit and receive bit rate of the PrimeCell SSP. The bit rate is: F SSPCLK CPSDVSR x (1+SCR) where CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and SCR is a value from 0-255.
-                SCR: u8,
-                padding: u16,
-            }),
-            ///  Control register 1, SSPCR1 on page 3-5
-            SSPCR1: mmio.Mmio(packed struct(u32) {
-                ///  Loop back mode: 0 Normal serial port operation enabled. 1 Output of transmit serial shifter is connected to input of receive serial shifter internally.
-                LBM: u1,
-                ///  Synchronous serial port enable: 0 SSP operation disabled. 1 SSP operation enabled.
-                SSE: u1,
-                ///  Master or slave mode select. This bit can be modified only when the PrimeCell SSP is disabled, SSE=0: 0 Device configured as master, default. 1 Device configured as slave.
-                MS: u1,
-                ///  Slave-mode output disable. This bit is relevant only in the slave mode, MS=1. In multiple-slave systems, it is possible for an PrimeCell SSP master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line. In such systems the RXD lines from multiple slaves could be tied together. To operate in such systems, the SOD bit can be set if the PrimeCell SSP slave is not supposed to drive the SSPTXD line: 0 SSP can drive the SSPTXD output in slave mode. 1 SSP must not drive the SSPTXD output in slave mode.
-                SOD: u1,
-                padding: u28,
-            }),
-            ///  Data register, SSPDR on page 3-6
-            SSPDR: mmio.Mmio(packed struct(u32) {
-                ///  Transmit/Receive FIFO: Read Receive FIFO. Write Transmit FIFO. You must right-justify data when the PrimeCell SSP is programmed for a data size that is less than 16 bits. Unused bits at the top are ignored by transmit logic. The receive logic automatically right-justifies.
-                DATA: u16,
-                padding: u16,
-            }),
-            ///  Status register, SSPSR on page 3-7
-            SSPSR: mmio.Mmio(packed struct(u32) {
-                ///  Transmit FIFO empty, RO: 0 Transmit FIFO is not empty. 1 Transmit FIFO is empty.
-                TFE: u1,
-                ///  Transmit FIFO not full, RO: 0 Transmit FIFO is full. 1 Transmit FIFO is not full.
-                TNF: u1,
-                ///  Receive FIFO not empty, RO: 0 Receive FIFO is empty. 1 Receive FIFO is not empty.
-                RNE: u1,
-                ///  Receive FIFO full, RO: 0 Receive FIFO is not full. 1 Receive FIFO is full.
-                RFF: u1,
-                ///  PrimeCell SSP busy flag, RO: 0 SSP is idle. 1 SSP is currently transmitting and/or receiving a frame or the transmit FIFO is not empty.
-                BSY: u1,
-                padding: u27,
-            }),
-            ///  Clock prescale register, SSPCPSR on page 3-8
-            SSPCPSR: mmio.Mmio(packed struct(u32) {
-                ///  Clock prescale divisor. Must be an even number from 2-254, depending on the frequency of SSPCLK. The least significant bit always returns zero on reads.
-                CPSDVSR: u8,
-                padding: u24,
-            }),
-            ///  Interrupt mask set or clear register, SSPIMSC on page 3-9
-            SSPIMSC: mmio.Mmio(packed struct(u32) {
-                ///  Receive overrun interrupt mask: 0 Receive FIFO written to while full condition interrupt is masked. 1 Receive FIFO written to while full condition interrupt is not masked.
-                RORIM: u1,
-                ///  Receive timeout interrupt mask: 0 Receive FIFO not empty and no read prior to timeout period interrupt is masked. 1 Receive FIFO not empty and no read prior to timeout period interrupt is not masked.
-                RTIM: u1,
-                ///  Receive FIFO interrupt mask: 0 Receive FIFO half full or less condition interrupt is masked. 1 Receive FIFO half full or less condition interrupt is not masked.
-                RXIM: u1,
-                ///  Transmit FIFO interrupt mask: 0 Transmit FIFO half empty or less condition interrupt is masked. 1 Transmit FIFO half empty or less condition interrupt is not masked.
-                TXIM: u1,
-                padding: u28,
-            }),
-            ///  Raw interrupt status register, SSPRIS on page 3-10
-            SSPRIS: mmio.Mmio(packed struct(u32) {
-                ///  Gives the raw interrupt state, prior to masking, of the SSPRORINTR interrupt
-                RORRIS: u1,
-                ///  Gives the raw interrupt state, prior to masking, of the SSPRTINTR interrupt
-                RTRIS: u1,
-                ///  Gives the raw interrupt state, prior to masking, of the SSPRXINTR interrupt
-                RXRIS: u1,
-                ///  Gives the raw interrupt state, prior to masking, of the SSPTXINTR interrupt
-                TXRIS: u1,
-                padding: u28,
-            }),
-            ///  Masked interrupt status register, SSPMIS on page 3-11
-            SSPMIS: mmio.Mmio(packed struct(u32) {
-                ///  Gives the receive over run masked interrupt status, after masking, of the SSPRORINTR interrupt
-                RORMIS: u1,
-                ///  Gives the receive timeout masked interrupt state, after masking, of the SSPRTINTR interrupt
-                RTMIS: u1,
-                ///  Gives the receive FIFO masked interrupt state, after masking, of the SSPRXINTR interrupt
-                RXMIS: u1,
-                ///  Gives the transmit FIFO masked interrupt state, after masking, of the SSPTXINTR interrupt
-                TXMIS: u1,
-                padding: u28,
-            }),
-            ///  Interrupt clear register, SSPICR on page 3-11
-            SSPICR: mmio.Mmio(packed struct(u32) {
-                ///  Clears the SSPRORINTR interrupt
-                RORIC: u1,
-                ///  Clears the SSPRTINTR interrupt
-                RTIC: u1,
-                padding: u30,
-            }),
-            ///  DMA control register, SSPDMACR on page 3-12
-            SSPDMACR: mmio.Mmio(packed struct(u32) {
-                ///  Receive DMA Enable. If this bit is set to 1, DMA for the receive FIFO is enabled.
-                RXDMAE: u1,
-                ///  Transmit DMA Enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
-                TXDMAE: u1,
-                padding: u30,
-            }),
-            reserved4064: [4024]u8,
-            ///  Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-            SSPPERIPHID0: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x22
-                PARTNUMBER0: u8,
-                padding: u24,
-            }),
-            ///  Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-            SSPPERIPHID1: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x0
-                PARTNUMBER1: u4,
-                ///  These bits read back as 0x1
-                DESIGNER0: u4,
-                padding: u24,
-            }),
-            ///  Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-            SSPPERIPHID2: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x4
-                DESIGNER1: u4,
-                ///  These bits return the peripheral revision
-                REVISION: u4,
-                padding: u24,
-            }),
-            ///  Peripheral identification registers, SSPPeriphID0-3 on page 3-13
-            SSPPERIPHID3: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x00
-                CONFIGURATION: u8,
-                padding: u24,
-            }),
-            ///  PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-            SSPPCELLID0: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x0D
-                SSPPCELLID0: u8,
-                padding: u24,
-            }),
-            ///  PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-            SSPPCELLID1: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0xF0
-                SSPPCELLID1: u8,
-                padding: u24,
-            }),
-            ///  PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-            SSPPCELLID2: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0x05
-                SSPPCELLID2: u8,
-                padding: u24,
-            }),
-            ///  PrimeCell identification registers, SSPPCellID0-3 on page 3-16
-            SSPPCELLID3: mmio.Mmio(packed struct(u32) {
-                ///  These bits read back as 0xB1
-                SSPPCELLID3: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  USB FS/LS controller device registers
-        pub const USBCTRL_REGS = extern struct {
-            ///  Device address and endpoint control
-            ADDR_ENDP: mmio.Mmio(packed struct(u32) {
-                ///  In device mode, the address that the device should respond to. Set in response to a SET_ADDR setup packet from the host. In host mode set to the address of the device to communicate with.
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Device endpoint to send data to. Only valid for HOST mode.
-                ENDPOINT: u4,
-                padding: u12,
-            }),
-            ///  Interrupt endpoint 1. Only valid for HOST mode.
-            ADDR_ENDP1: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 2. Only valid for HOST mode.
-            ADDR_ENDP2: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 3. Only valid for HOST mode.
-            ADDR_ENDP3: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 4. Only valid for HOST mode.
-            ADDR_ENDP4: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 5. Only valid for HOST mode.
-            ADDR_ENDP5: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 6. Only valid for HOST mode.
-            ADDR_ENDP6: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 7. Only valid for HOST mode.
-            ADDR_ENDP7: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 8. Only valid for HOST mode.
-            ADDR_ENDP8: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 9. Only valid for HOST mode.
-            ADDR_ENDP9: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 10. Only valid for HOST mode.
-            ADDR_ENDP10: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 11. Only valid for HOST mode.
-            ADDR_ENDP11: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 12. Only valid for HOST mode.
-            ADDR_ENDP12: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 13. Only valid for HOST mode.
-            ADDR_ENDP13: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 14. Only valid for HOST mode.
-            ADDR_ENDP14: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Interrupt endpoint 15. Only valid for HOST mode.
-            ADDR_ENDP15: mmio.Mmio(packed struct(u32) {
-                ///  Device address
-                ADDRESS: u7,
-                reserved16: u9,
-                ///  Endpoint number of the interrupt endpoint
-                ENDPOINT: u4,
-                reserved25: u5,
-                ///  Direction of the interrupt endpoint. In=0, Out=1
-                INTEP_DIR: u1,
-                ///  Interrupt EP requires preamble (is a low speed device on a full speed hub)
-                INTEP_PREAMBLE: u1,
-                padding: u5,
-            }),
-            ///  Main control register
-            MAIN_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Enable controller
-                CONTROLLER_EN: u1,
-                ///  Device mode = 0, Host mode = 1
-                HOST_NDEVICE: u1,
-                reserved31: u29,
-                ///  Reduced timings for simulation
-                SIM_TIMING: u1,
-            }),
-            ///  Set the SOF (Start of Frame) frame number in the host controller. The SOF packet is sent every 1ms and the host will increment the frame number by 1 each time.
-            SOF_WR: mmio.Mmio(packed struct(u32) {
-                COUNT: u11,
-                padding: u21,
-            }),
-            ///  Read the last SOF (Start of Frame) frame number seen. In device mode the last SOF received from the host. In host mode the last SOF sent by the host.
-            SOF_RD: mmio.Mmio(packed struct(u32) {
-                COUNT: u11,
-                padding: u21,
-            }),
-            ///  SIE control register
-            SIE_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Host: Start transaction
-                START_TRANS: u1,
-                ///  Host: Send Setup packet
-                SEND_SETUP: u1,
-                ///  Host: Send transaction (OUT from host)
-                SEND_DATA: u1,
-                ///  Host: Receive transaction (IN to host)
-                RECEIVE_DATA: u1,
-                ///  Host: Stop transaction
-                STOP_TRANS: u1,
-                reserved6: u1,
-                ///  Host: Preable enable for LS device on FS hub
-                PREAMBLE_EN: u1,
-                reserved8: u1,
-                ///  Host: Delay packet(s) until after SOF
-                SOF_SYNC: u1,
-                ///  Host: Enable SOF generation (for full speed bus)
-                SOF_EN: u1,
-                ///  Host: Enable keep alive packet (for low speed bus)
-                KEEP_ALIVE_EN: u1,
-                ///  Host: Enable VBUS
-                VBUS_EN: u1,
-                ///  Device: Remote wakeup. Device can initiate its own resume after suspend.
-                RESUME: u1,
-                ///  Host: Reset bus
-                RESET_BUS: u1,
-                reserved15: u1,
-                ///  Host: Enable pull down resistors
-                PULLDOWN_EN: u1,
-                ///  Device: Enable pull up resistor
-                PULLUP_EN: u1,
-                ///  Device: Pull-up strength (0=1K2, 1=2k3)
-                RPU_OPT: u1,
-                ///  Power down bus transceiver
-                TRANSCEIVER_PD: u1,
-                reserved24: u5,
-                ///  Direct control of DM
-                DIRECT_DM: u1,
-                ///  Direct control of DP
-                DIRECT_DP: u1,
-                ///  Direct bus drive enable
-                DIRECT_EN: u1,
-                ///  Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a NAK
-                EP0_INT_NAK: u1,
-                ///  Device: Set bit in BUFF_STATUS for every 2 buffers completed on EP0
-                EP0_INT_2BUF: u1,
-                ///  Device: Set bit in BUFF_STATUS for every buffer completed on EP0
-                EP0_INT_1BUF: u1,
-                ///  Device: EP0 single buffered = 0, double buffered = 1
-                EP0_DOUBLE_BUF: u1,
-                ///  Device: Set bit in EP_STATUS_STALL_NAK when EP0 sends a STALL
-                EP0_INT_STALL: u1,
-            }),
-            ///  SIE status register
-            SIE_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  Device: VBUS Detected
-                VBUS_DETECTED: u1,
-                reserved2: u1,
-                ///  USB bus line state
-                LINE_STATE: u2,
-                ///  Bus in suspended state. Valid for device and host. Host and device will go into suspend if neither Keep Alive / SOF frames are enabled.
-                SUSPENDED: u1,
-                reserved8: u3,
-                ///  Host: device speed. Disconnected = 00, LS = 01, FS = 10
-                SPEED: u2,
-                ///  VBUS over current detected
-                VBUS_OVER_CURR: u1,
-                ///  Host: Device has initiated a remote resume. Device: host has initiated a resume.
-                RESUME: u1,
-                reserved16: u4,
-                ///  Device: connected
-                CONNECTED: u1,
-                ///  Device: Setup packet received
-                SETUP_REC: u1,
-                ///  Transaction complete.
-                ///  Raised by device if:
-                ///  * An IN or OUT packet is sent with the `LAST_BUFF` bit set in the buffer control register
-                ///  Raised by host if:
-                ///  * A setup packet is sent when no data in or data out transaction follows * An IN packet is received and the `LAST_BUFF` bit is set in the buffer control register * An IN packet is received with zero length * An OUT packet is sent and the `LAST_BUFF` bit is set
-                TRANS_COMPLETE: u1,
-                ///  Device: bus reset received
-                BUS_RESET: u1,
-                reserved24: u4,
-                ///  CRC Error. Raised by the Serial RX engine.
-                CRC_ERROR: u1,
-                ///  Bit Stuff Error. Raised by the Serial RX engine.
-                BIT_STUFF_ERROR: u1,
-                ///  RX overflow is raised by the Serial RX engine if the incoming data is too fast.
-                RX_OVERFLOW: u1,
-                ///  RX timeout is raised by both the host and device if an ACK is not received in the maximum time specified by the USB spec.
-                RX_TIMEOUT: u1,
-                ///  Host: NAK received
-                NAK_REC: u1,
-                ///  Host: STALL received
-                STALL_REC: u1,
-                ///  ACK received. Raised by both host and device.
-                ACK_REC: u1,
-                ///  Data Sequence Error.
-                ///  The device can raise a sequence error in the following conditions:
-                ///  * A SETUP packet is received followed by a DATA1 packet (data phase should always be DATA0) * An OUT packet is received from the host but doesn't match the data pid in the buffer control register read from DPSRAM
-                ///  The host can raise a data sequence error in the following conditions:
-                ///  * An IN packet from the device has the wrong data PID
-                DATA_SEQ_ERROR: u1,
-            }),
-            ///  interrupt endpoint control register
-            INT_EP_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Host: Enable interrupt endpoint 1 -> 15
-                INT_EP_ACTIVE: u15,
-                padding: u16,
-            }),
-            ///  Buffer status register. A bit set here indicates that a buffer has completed on the endpoint (if the buffer interrupt is enabled). It is possible for 2 buffers to be completed, so clearing the buffer status bit may instantly re set it on the next clock cycle.
-            BUFF_STATUS: mmio.Mmio(packed struct(u32) {
-                EP0_IN: u1,
-                EP0_OUT: u1,
-                EP1_IN: u1,
-                EP1_OUT: u1,
-                EP2_IN: u1,
-                EP2_OUT: u1,
-                EP3_IN: u1,
-                EP3_OUT: u1,
-                EP4_IN: u1,
-                EP4_OUT: u1,
-                EP5_IN: u1,
-                EP5_OUT: u1,
-                EP6_IN: u1,
-                EP6_OUT: u1,
-                EP7_IN: u1,
-                EP7_OUT: u1,
-                EP8_IN: u1,
-                EP8_OUT: u1,
-                EP9_IN: u1,
-                EP9_OUT: u1,
-                EP10_IN: u1,
-                EP10_OUT: u1,
-                EP11_IN: u1,
-                EP11_OUT: u1,
-                EP12_IN: u1,
-                EP12_OUT: u1,
-                EP13_IN: u1,
-                EP13_OUT: u1,
-                EP14_IN: u1,
-                EP14_OUT: u1,
-                EP15_IN: u1,
-                EP15_OUT: u1,
-            }),
-            ///  Which of the double buffers should be handled. Only valid if using an interrupt per buffer (i.e. not per 2 buffers). Not valid for host interrupt endpoint polling because they are only single buffered.
-            BUFF_CPU_SHOULD_HANDLE: mmio.Mmio(packed struct(u32) {
-                EP0_IN: u1,
-                EP0_OUT: u1,
-                EP1_IN: u1,
-                EP1_OUT: u1,
-                EP2_IN: u1,
-                EP2_OUT: u1,
-                EP3_IN: u1,
-                EP3_OUT: u1,
-                EP4_IN: u1,
-                EP4_OUT: u1,
-                EP5_IN: u1,
-                EP5_OUT: u1,
-                EP6_IN: u1,
-                EP6_OUT: u1,
-                EP7_IN: u1,
-                EP7_OUT: u1,
-                EP8_IN: u1,
-                EP8_OUT: u1,
-                EP9_IN: u1,
-                EP9_OUT: u1,
-                EP10_IN: u1,
-                EP10_OUT: u1,
-                EP11_IN: u1,
-                EP11_OUT: u1,
-                EP12_IN: u1,
-                EP12_OUT: u1,
-                EP13_IN: u1,
-                EP13_OUT: u1,
-                EP14_IN: u1,
-                EP14_OUT: u1,
-                EP15_IN: u1,
-                EP15_OUT: u1,
-            }),
-            ///  Device only: Can be set to ignore the buffer control register for this endpoint in case you would like to revoke a buffer. A NAK will be sent for every access to the endpoint until this bit is cleared. A corresponding bit in `EP_ABORT_DONE` is set when it is safe to modify the buffer control register.
-            EP_ABORT: mmio.Mmio(packed struct(u32) {
-                EP0_IN: u1,
-                EP0_OUT: u1,
-                EP1_IN: u1,
-                EP1_OUT: u1,
-                EP2_IN: u1,
-                EP2_OUT: u1,
-                EP3_IN: u1,
-                EP3_OUT: u1,
-                EP4_IN: u1,
-                EP4_OUT: u1,
-                EP5_IN: u1,
-                EP5_OUT: u1,
-                EP6_IN: u1,
-                EP6_OUT: u1,
-                EP7_IN: u1,
-                EP7_OUT: u1,
-                EP8_IN: u1,
-                EP8_OUT: u1,
-                EP9_IN: u1,
-                EP9_OUT: u1,
-                EP10_IN: u1,
-                EP10_OUT: u1,
-                EP11_IN: u1,
-                EP11_OUT: u1,
-                EP12_IN: u1,
-                EP12_OUT: u1,
-                EP13_IN: u1,
-                EP13_OUT: u1,
-                EP14_IN: u1,
-                EP14_OUT: u1,
-                EP15_IN: u1,
-                EP15_OUT: u1,
-            }),
-            ///  Device only: Used in conjunction with `EP_ABORT`. Set once an endpoint is idle so the programmer knows it is safe to modify the buffer control register.
-            EP_ABORT_DONE: mmio.Mmio(packed struct(u32) {
-                EP0_IN: u1,
-                EP0_OUT: u1,
-                EP1_IN: u1,
-                EP1_OUT: u1,
-                EP2_IN: u1,
-                EP2_OUT: u1,
-                EP3_IN: u1,
-                EP3_OUT: u1,
-                EP4_IN: u1,
-                EP4_OUT: u1,
-                EP5_IN: u1,
-                EP5_OUT: u1,
-                EP6_IN: u1,
-                EP6_OUT: u1,
-                EP7_IN: u1,
-                EP7_OUT: u1,
-                EP8_IN: u1,
-                EP8_OUT: u1,
-                EP9_IN: u1,
-                EP9_OUT: u1,
-                EP10_IN: u1,
-                EP10_OUT: u1,
-                EP11_IN: u1,
-                EP11_OUT: u1,
-                EP12_IN: u1,
-                EP12_OUT: u1,
-                EP13_IN: u1,
-                EP13_OUT: u1,
-                EP14_IN: u1,
-                EP14_OUT: u1,
-                EP15_IN: u1,
-                EP15_OUT: u1,
-            }),
-            ///  Device: this bit must be set in conjunction with the `STALL` bit in the buffer control register to send a STALL on EP0. The device controller clears these bits when a SETUP packet is received because the USB spec requires that a STALL condition is cleared when a SETUP packet is received.
-            EP_STALL_ARM: mmio.Mmio(packed struct(u32) {
-                EP0_IN: u1,
-                EP0_OUT: u1,
-                padding: u30,
-            }),
-            ///  Used by the host controller. Sets the wait time in microseconds before trying again if the device replies with a NAK.
-            NAK_POLL: mmio.Mmio(packed struct(u32) {
-                ///  NAK polling interval for a low speed device
-                DELAY_LS: u10,
-                reserved16: u6,
-                ///  NAK polling interval for a full speed device
-                DELAY_FS: u10,
-                padding: u6,
-            }),
-            ///  Device: bits are set when the `IRQ_ON_NAK` or `IRQ_ON_STALL` bits are set. For EP0 this comes from `SIE_CTRL`. For all other endpoints it comes from the endpoint control register.
-            EP_STATUS_STALL_NAK: mmio.Mmio(packed struct(u32) {
-                EP0_IN: u1,
-                EP0_OUT: u1,
-                EP1_IN: u1,
-                EP1_OUT: u1,
-                EP2_IN: u1,
-                EP2_OUT: u1,
-                EP3_IN: u1,
-                EP3_OUT: u1,
-                EP4_IN: u1,
-                EP4_OUT: u1,
-                EP5_IN: u1,
-                EP5_OUT: u1,
-                EP6_IN: u1,
-                EP6_OUT: u1,
-                EP7_IN: u1,
-                EP7_OUT: u1,
-                EP8_IN: u1,
-                EP8_OUT: u1,
-                EP9_IN: u1,
-                EP9_OUT: u1,
-                EP10_IN: u1,
-                EP10_OUT: u1,
-                EP11_IN: u1,
-                EP11_OUT: u1,
-                EP12_IN: u1,
-                EP12_OUT: u1,
-                EP13_IN: u1,
-                EP13_OUT: u1,
-                EP14_IN: u1,
-                EP14_OUT: u1,
-                EP15_IN: u1,
-                EP15_OUT: u1,
-            }),
-            ///  Where to connect the USB controller. Should be to_phy by default.
-            USB_MUXING: mmio.Mmio(packed struct(u32) {
-                TO_PHY: u1,
-                TO_EXTPHY: u1,
-                TO_DIGITAL_PAD: u1,
-                SOFTCON: u1,
-                padding: u28,
-            }),
-            ///  Overrides for the power signals in the event that the VBUS signals are not hooked up to GPIO. Set the value of the override and then the override enable to switch over to the override value.
-            USB_PWR: mmio.Mmio(packed struct(u32) {
-                VBUS_EN: u1,
-                VBUS_EN_OVERRIDE_EN: u1,
-                VBUS_DETECT: u1,
-                VBUS_DETECT_OVERRIDE_EN: u1,
-                OVERCURR_DETECT: u1,
-                OVERCURR_DETECT_EN: u1,
-                padding: u26,
-            }),
-            ///  This register allows for direct control of the USB phy. Use in conjunction with usbphy_direct_override register to enable each override bit.
-            USBPHY_DIRECT: mmio.Mmio(packed struct(u32) {
-                ///  Enable the second DP pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2
-                DP_PULLUP_HISEL: u1,
-                ///  DP pull up enable
-                DP_PULLUP_EN: u1,
-                ///  DP pull down enable
-                DP_PULLDN_EN: u1,
-                reserved4: u1,
-                ///  Enable the second DM pull up resistor. 0 - Pull = Rpu2; 1 - Pull = Rpu1 + Rpu2
-                DM_PULLUP_HISEL: u1,
-                ///  DM pull up enable
-                DM_PULLUP_EN: u1,
-                ///  DM pull down enable
-                DM_PULLDN_EN: u1,
-                reserved8: u1,
-                ///  Output enable. If TX_DIFFMODE=1, OE for DPP/DPM diff pair. 0 - DPP/DPM in Hi-Z state; 1 - DPP/DPM driving
-                ///  If TX_DIFFMODE=0, OE for DPP only. 0 - DPP in Hi-Z state; 1 - DPP driving
-                TX_DP_OE: u1,
-                ///  Output enable. If TX_DIFFMODE=1, Ignored.
-                ///  If TX_DIFFMODE=0, OE for DPM only. 0 - DPM in Hi-Z state; 1 - DPM driving
-                TX_DM_OE: u1,
-                ///  Output data. If TX_DIFFMODE=1, Drives DPP/DPM diff pair. TX_DP_OE=1 to enable drive. DPP=TX_DP, DPM=~TX_DP
-                ///  If TX_DIFFMODE=0, Drives DPP only. TX_DP_OE=1 to enable drive. DPP=TX_DP
-                TX_DP: u1,
-                ///  Output data. TX_DIFFMODE=1, Ignored
-                ///  TX_DIFFMODE=0, Drives DPM only. TX_DM_OE=1 to enable drive. DPM=TX_DM
-                TX_DM: u1,
-                ///  RX power down override (if override enable is set). 1 = powered down.
-                RX_PD: u1,
-                ///  TX power down override (if override enable is set). 1 = powered down.
-                TX_PD: u1,
-                ///  TX_FSSLEW=0: Low speed slew rate
-                ///  TX_FSSLEW=1: Full speed slew rate
-                TX_FSSLEW: u1,
-                ///  TX_DIFFMODE=0: Single ended mode
-                ///  TX_DIFFMODE=1: Differential drive mode (TX_DM, TX_DM_OE ignored)
-                TX_DIFFMODE: u1,
-                ///  Differential RX
-                RX_DD: u1,
-                ///  DPP pin state
-                RX_DP: u1,
-                ///  DPM pin state
-                RX_DM: u1,
-                ///  DP overcurrent
-                DP_OVCN: u1,
-                ///  DM overcurrent
-                DM_OVCN: u1,
-                ///  DP over voltage
-                DP_OVV: u1,
-                ///  DM over voltage
-                DM_OVV: u1,
-                padding: u9,
-            }),
-            ///  Override enable for each control in usbphy_direct
-            USBPHY_DIRECT_OVERRIDE: mmio.Mmio(packed struct(u32) {
-                DP_PULLUP_HISEL_OVERRIDE_EN: u1,
-                DM_PULLUP_HISEL_OVERRIDE_EN: u1,
-                DP_PULLUP_EN_OVERRIDE_EN: u1,
-                DP_PULLDN_EN_OVERRIDE_EN: u1,
-                DM_PULLDN_EN_OVERRIDE_EN: u1,
-                TX_DP_OE_OVERRIDE_EN: u1,
-                TX_DM_OE_OVERRIDE_EN: u1,
-                TX_DP_OVERRIDE_EN: u1,
-                TX_DM_OVERRIDE_EN: u1,
-                RX_PD_OVERRIDE_EN: u1,
-                TX_PD_OVERRIDE_EN: u1,
-                TX_FSSLEW_OVERRIDE_EN: u1,
-                DM_PULLUP_OVERRIDE_EN: u1,
-                reserved15: u2,
-                TX_DIFFMODE_OVERRIDE_EN: u1,
-                padding: u16,
-            }),
-            ///  Used to adjust trim values of USB phy pull down resistors.
-            USBPHY_TRIM: mmio.Mmio(packed struct(u32) {
-                ///  Value to drive to USB PHY
-                ///  DP pulldown resistor trim control
-                ///  Experimental data suggests that the reset value will work, but this register allows adjustment if required
-                DP_PULLDN_TRIM: u5,
-                reserved8: u3,
-                ///  Value to drive to USB PHY
-                ///  DM pulldown resistor trim control
-                ///  Experimental data suggests that the reset value will work, but this register allows adjustment if required
-                DM_PULLDN_TRIM: u5,
-                padding: u19,
-            }),
-            reserved140: [4]u8,
-            ///  Raw Interrupts
-            INTR: mmio.Mmio(packed struct(u32) {
-                ///  Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
-                HOST_CONN_DIS: u1,
-                ///  Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
-                HOST_RESUME: u1,
-                ///  Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
-                HOST_SOF: u1,
-                ///  Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
-                TRANS_COMPLETE: u1,
-                ///  Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
-                BUFF_STATUS: u1,
-                ///  Source: SIE_STATUS.DATA_SEQ_ERROR
-                ERROR_DATA_SEQ: u1,
-                ///  Source: SIE_STATUS.RX_TIMEOUT
-                ERROR_RX_TIMEOUT: u1,
-                ///  Source: SIE_STATUS.RX_OVERFLOW
-                ERROR_RX_OVERFLOW: u1,
-                ///  Source: SIE_STATUS.BIT_STUFF_ERROR
-                ERROR_BIT_STUFF: u1,
-                ///  Source: SIE_STATUS.CRC_ERROR
-                ERROR_CRC: u1,
-                ///  Source: SIE_STATUS.STALL_REC
-                STALL: u1,
-                ///  Source: SIE_STATUS.VBUS_DETECTED
-                VBUS_DETECT: u1,
-                ///  Source: SIE_STATUS.BUS_RESET
-                BUS_RESET: u1,
-                ///  Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
-                DEV_CONN_DIS: u1,
-                ///  Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
-                DEV_SUSPEND: u1,
-                ///  Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
-                DEV_RESUME_FROM_HOST: u1,
-                ///  Device. Source: SIE_STATUS.SETUP_REC
-                SETUP_REQ: u1,
-                ///  Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
-                DEV_SOF: u1,
-                ///  Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
-                ABORT_DONE: u1,
-                ///  Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
-                EP_STALL_NAK: u1,
-                padding: u12,
-            }),
-            ///  Interrupt Enable
-            INTE: mmio.Mmio(packed struct(u32) {
-                ///  Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
-                HOST_CONN_DIS: u1,
-                ///  Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
-                HOST_RESUME: u1,
-                ///  Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
-                HOST_SOF: u1,
-                ///  Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
-                TRANS_COMPLETE: u1,
-                ///  Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
-                BUFF_STATUS: u1,
-                ///  Source: SIE_STATUS.DATA_SEQ_ERROR
-                ERROR_DATA_SEQ: u1,
-                ///  Source: SIE_STATUS.RX_TIMEOUT
-                ERROR_RX_TIMEOUT: u1,
-                ///  Source: SIE_STATUS.RX_OVERFLOW
-                ERROR_RX_OVERFLOW: u1,
-                ///  Source: SIE_STATUS.BIT_STUFF_ERROR
-                ERROR_BIT_STUFF: u1,
-                ///  Source: SIE_STATUS.CRC_ERROR
-                ERROR_CRC: u1,
-                ///  Source: SIE_STATUS.STALL_REC
-                STALL: u1,
-                ///  Source: SIE_STATUS.VBUS_DETECTED
-                VBUS_DETECT: u1,
-                ///  Source: SIE_STATUS.BUS_RESET
-                BUS_RESET: u1,
-                ///  Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
-                DEV_CONN_DIS: u1,
-                ///  Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
-                DEV_SUSPEND: u1,
-                ///  Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
-                DEV_RESUME_FROM_HOST: u1,
-                ///  Device. Source: SIE_STATUS.SETUP_REC
-                SETUP_REQ: u1,
-                ///  Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
-                DEV_SOF: u1,
-                ///  Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
-                ABORT_DONE: u1,
-                ///  Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
-                EP_STALL_NAK: u1,
-                padding: u12,
-            }),
-            ///  Interrupt Force
-            INTF: mmio.Mmio(packed struct(u32) {
-                ///  Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
-                HOST_CONN_DIS: u1,
-                ///  Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
-                HOST_RESUME: u1,
-                ///  Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
-                HOST_SOF: u1,
-                ///  Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
-                TRANS_COMPLETE: u1,
-                ///  Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
-                BUFF_STATUS: u1,
-                ///  Source: SIE_STATUS.DATA_SEQ_ERROR
-                ERROR_DATA_SEQ: u1,
-                ///  Source: SIE_STATUS.RX_TIMEOUT
-                ERROR_RX_TIMEOUT: u1,
-                ///  Source: SIE_STATUS.RX_OVERFLOW
-                ERROR_RX_OVERFLOW: u1,
-                ///  Source: SIE_STATUS.BIT_STUFF_ERROR
-                ERROR_BIT_STUFF: u1,
-                ///  Source: SIE_STATUS.CRC_ERROR
-                ERROR_CRC: u1,
-                ///  Source: SIE_STATUS.STALL_REC
-                STALL: u1,
-                ///  Source: SIE_STATUS.VBUS_DETECTED
-                VBUS_DETECT: u1,
-                ///  Source: SIE_STATUS.BUS_RESET
-                BUS_RESET: u1,
-                ///  Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
-                DEV_CONN_DIS: u1,
-                ///  Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
-                DEV_SUSPEND: u1,
-                ///  Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
-                DEV_RESUME_FROM_HOST: u1,
-                ///  Device. Source: SIE_STATUS.SETUP_REC
-                SETUP_REQ: u1,
-                ///  Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
-                DEV_SOF: u1,
-                ///  Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
-                ABORT_DONE: u1,
-                ///  Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
-                EP_STALL_NAK: u1,
-                padding: u12,
-            }),
-            ///  Interrupt status after masking & forcing
-            INTS: mmio.Mmio(packed struct(u32) {
-                ///  Host: raised when a device is connected or disconnected (i.e. when SIE_STATUS.SPEED changes). Cleared by writing to SIE_STATUS.SPEED
-                HOST_CONN_DIS: u1,
-                ///  Host: raised when a device wakes up the host. Cleared by writing to SIE_STATUS.RESUME
-                HOST_RESUME: u1,
-                ///  Host: raised every time the host sends a SOF (Start of Frame). Cleared by reading SOF_RD
-                HOST_SOF: u1,
-                ///  Raised every time SIE_STATUS.TRANS_COMPLETE is set. Clear by writing to this bit.
-                TRANS_COMPLETE: u1,
-                ///  Raised when any bit in BUFF_STATUS is set. Clear by clearing all bits in BUFF_STATUS.
-                BUFF_STATUS: u1,
-                ///  Source: SIE_STATUS.DATA_SEQ_ERROR
-                ERROR_DATA_SEQ: u1,
-                ///  Source: SIE_STATUS.RX_TIMEOUT
-                ERROR_RX_TIMEOUT: u1,
-                ///  Source: SIE_STATUS.RX_OVERFLOW
-                ERROR_RX_OVERFLOW: u1,
-                ///  Source: SIE_STATUS.BIT_STUFF_ERROR
-                ERROR_BIT_STUFF: u1,
-                ///  Source: SIE_STATUS.CRC_ERROR
-                ERROR_CRC: u1,
-                ///  Source: SIE_STATUS.STALL_REC
-                STALL: u1,
-                ///  Source: SIE_STATUS.VBUS_DETECTED
-                VBUS_DETECT: u1,
-                ///  Source: SIE_STATUS.BUS_RESET
-                BUS_RESET: u1,
-                ///  Set when the device connection state changes. Cleared by writing to SIE_STATUS.CONNECTED
-                DEV_CONN_DIS: u1,
-                ///  Set when the device suspend state changes. Cleared by writing to SIE_STATUS.SUSPENDED
-                DEV_SUSPEND: u1,
-                ///  Set when the device receives a resume from the host. Cleared by writing to SIE_STATUS.RESUME
-                DEV_RESUME_FROM_HOST: u1,
-                ///  Device. Source: SIE_STATUS.SETUP_REC
-                SETUP_REQ: u1,
-                ///  Set every time the device receives a SOF (Start of Frame) packet. Cleared by reading SOF_RD
-                DEV_SOF: u1,
-                ///  Raised when any bit in ABORT_DONE is set. Clear by clearing all bits in ABORT_DONE.
-                ABORT_DONE: u1,
-                ///  Raised when any bit in EP_STATUS_STALL_NAK is set. Clear by clearing all bits in EP_STATUS_STALL_NAK.
-                EP_STALL_NAK: u1,
-                padding: u12,
-            }),
-        };
-
-        ///  DW_apb_i2c address block
-        ///  List of configuration constants for the Synopsys I2C hardware (you may see references to these in I2C register header; these are *fixed* values, set at hardware design time):
-        ///  IC_ULTRA_FAST_MODE ................ 0x0
-        ///  IC_UFM_TBUF_CNT_DEFAULT ........... 0x8
-        ///  IC_UFM_SCL_LOW_COUNT .............. 0x0008
-        ///  IC_UFM_SCL_HIGH_COUNT ............. 0x0006
-        ///  IC_TX_TL .......................... 0x0
-        ///  IC_TX_CMD_BLOCK ................... 0x1
-        ///  IC_HAS_DMA ........................ 0x1
-        ///  IC_HAS_ASYNC_FIFO ................. 0x0
-        ///  IC_SMBUS_ARP ...................... 0x0
-        ///  IC_FIRST_DATA_BYTE_STATUS ......... 0x1
-        ///  IC_INTR_IO ........................ 0x1
-        ///  IC_MASTER_MODE .................... 0x1
-        ///  IC_DEFAULT_ACK_GENERAL_CALL ....... 0x1
-        ///  IC_INTR_POL ....................... 0x1
-        ///  IC_OPTIONAL_SAR ................... 0x0
-        ///  IC_DEFAULT_TAR_SLAVE_ADDR ......... 0x055
-        ///  IC_DEFAULT_SLAVE_ADDR ............. 0x055
-        ///  IC_DEFAULT_HS_SPKLEN .............. 0x1
-        ///  IC_FS_SCL_HIGH_COUNT .............. 0x0006
-        ///  IC_HS_SCL_LOW_COUNT ............... 0x0008
-        ///  IC_DEVICE_ID_VALUE ................ 0x0
-        ///  IC_10BITADDR_MASTER ............... 0x0
-        ///  IC_CLK_FREQ_OPTIMIZATION .......... 0x0
-        ///  IC_DEFAULT_FS_SPKLEN .............. 0x7
-        ///  IC_ADD_ENCODED_PARAMS ............. 0x0
-        ///  IC_DEFAULT_SDA_HOLD ............... 0x000001
-        ///  IC_DEFAULT_SDA_SETUP .............. 0x64
-        ///  IC_AVOID_RX_FIFO_FLUSH_ON_TX_ABRT . 0x0
-        ///  IC_CLOCK_PERIOD ................... 100
-        ///  IC_EMPTYFIFO_HOLD_MASTER_EN ....... 1
-        ///  IC_RESTART_EN ..................... 0x1
-        ///  IC_TX_CMD_BLOCK_DEFAULT ........... 0x0
-        ///  IC_BUS_CLEAR_FEATURE .............. 0x0
-        ///  IC_CAP_LOADING .................... 100
-        ///  IC_FS_SCL_LOW_COUNT ............... 0x000d
-        ///  APB_DATA_WIDTH .................... 32
-        ///  IC_SDA_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
-        ///  IC_SLV_DATA_NACK_ONLY ............. 0x1
-        ///  IC_10BITADDR_SLAVE ................ 0x0
-        ///  IC_CLK_TYPE ....................... 0x0
-        ///  IC_SMBUS_UDID_MSB ................. 0x0
-        ///  IC_SMBUS_SUSPEND_ALERT ............ 0x0
-        ///  IC_HS_SCL_HIGH_COUNT .............. 0x0006
-        ///  IC_SLV_RESTART_DET_EN ............. 0x1
-        ///  IC_SMBUS .......................... 0x0
-        ///  IC_OPTIONAL_SAR_DEFAULT ........... 0x0
-        ///  IC_PERSISTANT_SLV_ADDR_DEFAULT .... 0x0
-        ///  IC_USE_COUNTS ..................... 0x0
-        ///  IC_RX_BUFFER_DEPTH ................ 16
-        ///  IC_SCL_STUCK_TIMEOUT_DEFAULT ...... 0xffffffff
-        ///  IC_RX_FULL_HLD_BUS_EN ............. 0x1
-        ///  IC_SLAVE_DISABLE .................. 0x1
-        ///  IC_RX_TL .......................... 0x0
-        ///  IC_DEVICE_ID ...................... 0x0
-        ///  IC_HC_COUNT_VALUES ................ 0x0
-        ///  I2C_DYNAMIC_TAR_UPDATE ............ 0
-        ///  IC_SMBUS_CLK_LOW_MEXT_DEFAULT ..... 0xffffffff
-        ///  IC_SMBUS_CLK_LOW_SEXT_DEFAULT ..... 0xffffffff
-        ///  IC_HS_MASTER_CODE ................. 0x1
-        ///  IC_SMBUS_RST_IDLE_CNT_DEFAULT ..... 0xffff
-        ///  IC_SMBUS_UDID_LSB_DEFAULT ......... 0xffffffff
-        ///  IC_SS_SCL_HIGH_COUNT .............. 0x0028
-        ///  IC_SS_SCL_LOW_COUNT ............... 0x002f
-        ///  IC_MAX_SPEED_MODE ................. 0x2
-        ///  IC_STAT_FOR_CLK_STRETCH ........... 0x0
-        ///  IC_STOP_DET_IF_MASTER_ACTIVE ...... 0x0
-        ///  IC_DEFAULT_UFM_SPKLEN ............. 0x1
-        ///  IC_TX_BUFFER_DEPTH ................ 16
-        pub const I2C0 = extern struct {
-            ///  I2C Control Register. This register can be written only when the DW_apb_i2c is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
-            ///  Read/Write Access: - bit 10 is read only. - bit 11 is read only - bit 16 is read only - bit 17 is read only - bits 18 and 19 are read only.
-            IC_CON: mmio.Mmio(packed struct(u32) {
-                ///  This bit controls whether the DW_apb_i2c master is enabled.
-                ///  NOTE: Software should ensure that if this bit is written with '1' then bit 6 should also be written with a '1'.
-                MASTER_MODE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Master mode is disabled
-                        DISABLED = 0x0,
-                        ///  Master mode is enabled
-                        ENABLED = 0x1,
-                    },
-                },
-                ///  These bits control at which speed the DW_apb_i2c operates; its setting is relevant only if one is operating the DW_apb_i2c in master mode. Hardware protects against illegal values being programmed by software. These bits must be programmed appropriately for slave mode also, as it is used to capture correct value of spike filter as per the speed mode.
-                ///  This register should be programmed only with a value in the range of 1 to IC_MAX_SPEED_MODE; otherwise, hardware updates this register with the value of IC_MAX_SPEED_MODE.
-                ///  1: standard mode (100 kbit/s)
-                ///  2: fast mode (<=400 kbit/s) or fast mode plus (<=1000Kbit/s)
-                ///  3: high speed mode (3.4 Mbit/s)
-                ///  Note: This field is not applicable when IC_ULTRA_FAST_MODE=1
-                SPEED: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Standard Speed mode of operation
-                        STANDARD = 0x1,
-                        ///  Fast or Fast Plus mode of operation
-                        FAST = 0x2,
-                        ///  High Speed mode of operation
-                        HIGH = 0x3,
-                        _,
-                    },
-                },
-                ///  When acting as a slave, this bit controls whether the DW_apb_i2c responds to 7- or 10-bit addresses. - 0: 7-bit addressing. The DW_apb_i2c ignores transactions that involve 10-bit addressing; for 7-bit addressing, only the lower 7 bits of the IC_SAR register are compared. - 1: 10-bit addressing. The DW_apb_i2c responds to only 10-bit addressing transfers that match the full 10 bits of the IC_SAR register.
-                IC_10BITADDR_SLAVE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Slave 7Bit addressing
-                        ADDR_7BITS = 0x0,
-                        ///  Slave 10Bit addressing
-                        ADDR_10BITS = 0x1,
-                    },
-                },
-                ///  Controls whether the DW_apb_i2c starts its transfers in 7- or 10-bit addressing mode when acting as a master. - 0: 7-bit addressing - 1: 10-bit addressing
-                IC_10BITADDR_MASTER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Master 7Bit addressing mode
-                        ADDR_7BITS = 0x0,
-                        ///  Master 10Bit addressing mode
-                        ADDR_10BITS = 0x1,
-                    },
-                },
-                ///  Determines whether RESTART conditions may be sent when acting as a master. Some older slaves do not support handling RESTART conditions; however, RESTART conditions are used in several DW_apb_i2c operations. When RESTART is disabled, the master is prohibited from performing the following functions: - Sending a START BYTE - Performing any high-speed mode operation - High-speed mode operation - Performing direction changes in combined format mode - Performing a read operation with a 10-bit address By replacing RESTART condition followed by a STOP and a subsequent START condition, split operations are broken down into multiple DW_apb_i2c transfers. If the above operations are performed, it will result in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register.
-                ///  Reset value: ENABLED
-                IC_RESTART_EN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Master restart disabled
-                        DISABLED = 0x0,
-                        ///  Master restart enabled
-                        ENABLED = 0x1,
-                    },
-                },
-                ///  This bit controls whether I2C has its slave disabled, which means once the presetn signal is applied, then this bit is set and the slave is disabled.
-                ///  If this bit is set (slave is disabled), DW_apb_i2c functions only as a master and does not perform any action that requires a slave.
-                ///  NOTE: Software should ensure that if this bit is written with 0, then bit 0 should also be written with a 0.
-                IC_SLAVE_DISABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Slave mode is enabled
-                        SLAVE_ENABLED = 0x0,
-                        ///  Slave mode is disabled
-                        SLAVE_DISABLED = 0x1,
-                    },
-                },
-                ///  In slave mode: - 1'b1: issues the STOP_DET interrupt only when it is addressed. - 1'b0: issues the STOP_DET irrespective of whether it's addressed or not. Reset value: 0x0
-                ///  NOTE: During a general call address, this slave does not issue the STOP_DET interrupt if STOP_DET_IF_ADDRESSED = 1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR).
-                STOP_DET_IFADDRESSED: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  slave issues STOP_DET intr always
-                        DISABLED = 0x0,
-                        ///  slave issues STOP_DET intr only if addressed
-                        ENABLED = 0x1,
-                    },
-                },
-                ///  This bit controls the generation of the TX_EMPTY interrupt, as described in the IC_RAW_INTR_STAT register.
-                ///  Reset value: 0x0.
-                TX_EMPTY_CTRL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Default behaviour of TX_EMPTY interrupt
-                        DISABLED = 0x0,
-                        ///  Controlled generation of TX_EMPTY interrupt
-                        ENABLED = 0x1,
-                    },
-                },
-                ///  This bit controls whether DW_apb_i2c should hold the bus when the Rx FIFO is physically full to its RX_BUFFER_DEPTH, as described in the IC_RX_FULL_HLD_BUS_EN parameter.
-                ///  Reset value: 0x0.
-                RX_FIFO_FULL_HLD_CTRL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Overflow when RX_FIFO is full
-                        DISABLED = 0x0,
-                        ///  Hold bus when RX_FIFO is full
-                        ENABLED = 0x1,
-                    },
-                },
-                ///  Master issues the STOP_DET interrupt irrespective of whether master is active or not
-                STOP_DET_IF_MASTER_ACTIVE: u1,
-                padding: u21,
-            }),
-            ///  I2C Target Address Register
-            ///  This register is 12 bits wide, and bits 31:12 are reserved. This register can be written to only when IC_ENABLE[0] is set to 0.
-            ///  Note: If the software or application is aware that the DW_apb_i2c is not using the TAR address for the pending commands in the Tx FIFO, then it is possible to update the TAR address even while the Tx FIFO has entries (IC_STATUS[2]= 0). - It is not necessary to perform any write to this register if DW_apb_i2c is enabled as an I2C slave only.
-            IC_TAR: mmio.Mmio(packed struct(u32) {
-                ///  This is the target address for any master transaction. When transmitting a General Call, these bits are ignored. To generate a START BYTE, the CPU needs to write only once into these bits.
-                ///  If the IC_TAR and IC_SAR are the same, loopback exists but the FIFOs are shared between master and slave, so full loopback is not feasible. Only one direction loopback mode is supported (simplex), not duplex. A master cannot transmit to itself; it can transmit to only a slave.
-                IC_TAR: u10,
-                ///  If bit 11 (SPECIAL) is set to 1 and bit 13(Device-ID) is set to 0, then this bit indicates whether a General Call or START byte command is to be performed by the DW_apb_i2c. - 0: General Call Address - after issuing a General Call, only writes may be performed. Attempting to issue a read command results in setting bit 6 (TX_ABRT) of the IC_RAW_INTR_STAT register. The DW_apb_i2c remains in General Call mode until the SPECIAL bit value (bit 11) is cleared. - 1: START BYTE Reset value: 0x0
-                GC_OR_START: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  GENERAL_CALL byte transmission
-                        GENERAL_CALL = 0x0,
-                        ///  START byte transmission
-                        START_BYTE = 0x1,
-                    },
-                },
-                ///  This bit indicates whether software performs a Device-ID or General Call or START BYTE command. - 0: ignore bit 10 GC_OR_START and use IC_TAR normally - 1: perform special I2C command as specified in Device_ID or GC_OR_START bit Reset value: 0x0
-                SPECIAL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Disables programming of GENERAL_CALL or START_BYTE transmission
-                        DISABLED = 0x0,
-                        ///  Enables programming of GENERAL_CALL or START_BYTE transmission
-                        ENABLED = 0x1,
-                    },
-                },
-                padding: u20,
-            }),
-            ///  I2C Slave Address Register
-            IC_SAR: mmio.Mmio(packed struct(u32) {
-                ///  The IC_SAR holds the slave address when the I2C is operating as a slave. For 7-bit addressing, only IC_SAR[6:0] is used.
-                ///  This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
-                ///  Note: The default values cannot be any of the reserved address locations: that is, 0x00 to 0x07, or 0x78 to 0x7f. The correct operation of the device is not guaranteed if you program the IC_SAR or IC_TAR to a reserved value. Refer to <> for a complete list of these reserved values.
-                IC_SAR: u10,
-                padding: u22,
-            }),
-            reserved16: [4]u8,
-            ///  I2C Rx/Tx Data Buffer and Command Register; this is the register the CPU writes to when filling the TX FIFO and the CPU reads from when retrieving bytes from RX FIFO.
-            ///  The size of the register changes as follows:
-            ///  Write: - 11 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=1 - 9 bits when IC_EMPTYFIFO_HOLD_MASTER_EN=0 Read: - 12 bits when IC_FIRST_DATA_BYTE_STATUS = 1 - 8 bits when IC_FIRST_DATA_BYTE_STATUS = 0 Note: In order for the DW_apb_i2c to continue acknowledging reads, a read command should be written for every byte that is to be received; otherwise the DW_apb_i2c will stop acknowledging.
-            IC_DATA_CMD: mmio.Mmio(packed struct(u32) {
-                ///  This register contains the data to be transmitted or received on the I2C bus. If you are writing to this register and want to perform a read, bits 7:0 (DAT) are ignored by the DW_apb_i2c. However, when you read this register, these bits return the value of data received on the DW_apb_i2c interface.
-                ///  Reset value: 0x0
-                DAT: u8,
-                ///  This bit controls whether a read or a write is performed. This bit does not control the direction when the DW_apb_i2con acts as a slave. It controls only the direction when it acts as a master.
-                ///  When a command is entered in the TX FIFO, this bit distinguishes the write and read commands. In slave-receiver mode, this bit is a 'don't care' because writes to this register are not required. In slave-transmitter mode, a '0' indicates that the data in IC_DATA_CMD is to be transmitted.
-                ///  When programming this bit, you should remember the following: attempting to perform a read operation after a General Call command has been sent results in a TX_ABRT interrupt (bit 6 of the IC_RAW_INTR_STAT register), unless bit 11 (SPECIAL) in the IC_TAR register has been cleared. If a '1' is written to this bit after receiving a RD_REQ interrupt, then a TX_ABRT interrupt occurs.
-                ///  Reset value: 0x0
-                CMD: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Master Write Command
-                        WRITE = 0x0,
-                        ///  Master Read Command
-                        READ = 0x1,
-                    },
-                },
-                ///  This bit controls whether a STOP is issued after the byte is sent or received.
-                ///  - 1 - STOP is issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master immediately tries to start a new transfer by issuing a START and arbitrating for the bus. - 0 - STOP is not issued after this byte, regardless of whether or not the Tx FIFO is empty. If the Tx FIFO is not empty, the master continues the current transfer by sending/receiving data bytes according to the value of the CMD bit. If the Tx FIFO is empty, the master holds the SCL line low and stalls the bus until a new command is available in the Tx FIFO. Reset value: 0x0
-                STOP: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Don't Issue STOP after this command
-                        DISABLE = 0x0,
-                        ///  Issue STOP after this command
-                        ENABLE = 0x1,
-                    },
-                },
-                ///  This bit controls whether a RESTART is issued before the byte is sent or received.
-                ///  1 - If IC_RESTART_EN is 1, a RESTART is issued before the data is sent/received (according to the value of CMD), regardless of whether or not the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
-                ///  0 - If IC_RESTART_EN is 1, a RESTART is issued only if the transfer direction is changing from the previous command; if IC_RESTART_EN is 0, a STOP followed by a START is issued instead.
-                ///  Reset value: 0x0
-                RESTART: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Don't Issue RESTART before this command
-                        DISABLE = 0x0,
-                        ///  Issue RESTART before this command
-                        ENABLE = 0x1,
-                    },
-                },
-                ///  Indicates the first data byte received after the address phase for receive transfer in Master receiver or Slave receiver mode.
-                ///  Reset value : 0x0
-                ///  NOTE: In case of APB_DATA_WIDTH=8,
-                ///  1. The user has to perform two APB Reads to IC_DATA_CMD in order to get status on 11 bit.
-                ///  2. In order to read the 11 bit, the user has to perform the first data byte read [7:0] (offset 0x10) and then perform the second read [15:8] (offset 0x11) in order to know the status of 11 bit (whether the data received in previous read is a first data byte or not).
-                ///  3. The 11th bit is an optional read field, user can ignore 2nd byte read [15:8] (offset 0x11) if not interested in FIRST_DATA_BYTE status.
-                FIRST_DATA_BYTE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Sequential data byte received
-                        INACTIVE = 0x0,
-                        ///  Non sequential data byte received
-                        ACTIVE = 0x1,
-                    },
-                },
-                padding: u20,
-            }),
-            ///  Standard Speed I2C Clock SCL High Count Register
-            IC_SS_SCL_HCNT: mmio.Mmio(packed struct(u32) {
-                ///  This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'.
-                ///  This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
-                ///  The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.
-                ///  NOTE: This register must not be programmed to a value higher than 65525, because DW_apb_i2c uses a 16-bit counter to flag an I2C bus idle condition when this counter reaches a value of IC_SS_SCL_HCNT + 10.
-                IC_SS_SCL_HCNT: u16,
-                padding: u16,
-            }),
-            ///  Standard Speed I2C Clock SCL Low Count Register
-            IC_SS_SCL_LCNT: mmio.Mmio(packed struct(u32) {
-                ///  This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for standard speed. For more information, refer to 'IC_CLK Frequency Configuration'
-                ///  This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
-                ///  The minimum valid value is 8; hardware prevents values less than this being written, and if attempted, results in 8 being set. For designs with APB_DATA_WIDTH = 8, the order of programming is important to ensure the correct operation of DW_apb_i2c. The lower byte must be programmed first, and then the upper byte is programmed.
-                IC_SS_SCL_LCNT: u16,
-                padding: u16,
-            }),
-            ///  Fast Mode or Fast Mode Plus I2C Clock SCL High Count Register
-            IC_FS_SCL_HCNT: mmio.Mmio(packed struct(u32) {
-                ///  This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock high-period count for fast mode or fast mode plus. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.
-                ///  This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard. This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
-                ///  The minimum valid value is 6; hardware prevents values less than this being written, and if attempted results in 6 being set. For designs with APB_DATA_WIDTH == 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed.
-                IC_FS_SCL_HCNT: u16,
-                padding: u16,
-            }),
-            ///  Fast Mode or Fast Mode Plus I2C Clock SCL Low Count Register
-            IC_FS_SCL_LCNT: mmio.Mmio(packed struct(u32) {
-                ///  This register must be set before any I2C bus transaction can take place to ensure proper I/O timing. This register sets the SCL clock low period count for fast speed. It is used in high-speed mode to send the Master Code and START BYTE or General CALL. For more information, refer to 'IC_CLK Frequency Configuration'.
-                ///  This register goes away and becomes read-only returning 0s if IC_MAX_SPEED_MODE = standard.
-                ///  This register can be written only when the I2C interface is disabled, which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect.
-                ///  The minimum valid value is 8; hardware prevents values less than this being written, and if attempted results in 8 being set. For designs with APB_DATA_WIDTH = 8 the order of programming is important to ensure the correct operation of the DW_apb_i2c. The lower byte must be programmed first. Then the upper byte is programmed. If the value is less than 8 then the count value gets changed to 8.
-                IC_FS_SCL_LCNT: u16,
-                padding: u16,
-            }),
-            reserved44: [8]u8,
-            ///  I2C Interrupt Status Register
-            ///  Each bit in this register has a corresponding mask bit in the IC_INTR_MASK register. These bits are cleared by reading the matching interrupt clear register. The unmasked raw versions of these bits are available in the IC_RAW_INTR_STAT register.
-            IC_INTR_STAT: mmio.Mmio(packed struct(u32) {
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_RX_UNDER bit.
-                ///  Reset value: 0x0
-                R_RX_UNDER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RX_UNDER interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  RX_UNDER interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_RX_OVER bit.
-                ///  Reset value: 0x0
-                R_RX_OVER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_RX_OVER interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_RX_OVER interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_RX_FULL bit.
-                ///  Reset value: 0x0
-                R_RX_FULL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_RX_FULL interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_RX_FULL interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_TX_OVER bit.
-                ///  Reset value: 0x0
-                R_TX_OVER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_TX_OVER interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_TX_OVER interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_TX_EMPTY bit.
-                ///  Reset value: 0x0
-                R_TX_EMPTY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_TX_EMPTY interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_TX_EMPTY interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_RD_REQ bit.
-                ///  Reset value: 0x0
-                R_RD_REQ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_RD_REQ interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_RD_REQ interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_TX_ABRT bit.
-                ///  Reset value: 0x0
-                R_TX_ABRT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_TX_ABRT interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_TX_ABRT interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_RX_DONE bit.
-                ///  Reset value: 0x0
-                R_RX_DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_RX_DONE interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_RX_DONE interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_ACTIVITY bit.
-                ///  Reset value: 0x0
-                R_ACTIVITY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_ACTIVITY interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_ACTIVITY interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_STOP_DET bit.
-                ///  Reset value: 0x0
-                R_STOP_DET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_STOP_DET interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_STOP_DET interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_START_DET bit.
-                ///  Reset value: 0x0
-                R_START_DET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_START_DET interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_START_DET interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_GEN_CALL bit.
-                ///  Reset value: 0x0
-                R_GEN_CALL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_GEN_CALL interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_GEN_CALL interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  See IC_RAW_INTR_STAT for a detailed description of R_RESTART_DET bit.
-                ///  Reset value: 0x0
-                R_RESTART_DET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  R_RESTART_DET interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  R_RESTART_DET interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                padding: u19,
-            }),
-            ///  I2C Interrupt Mask Register.
-            ///  These bits mask their corresponding interrupt status bits. This register is active low; a value of 0 masks the interrupt, whereas a value of 1 unmasks the interrupt.
-            IC_INTR_MASK: mmio.Mmio(packed struct(u32) {
-                ///  This bit masks the R_RX_UNDER interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x1
-                M_RX_UNDER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RX_UNDER interrupt is masked
-                        ENABLED = 0x0,
-                        ///  RX_UNDER interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_RX_OVER interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x1
-                M_RX_OVER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RX_OVER interrupt is masked
-                        ENABLED = 0x0,
-                        ///  RX_OVER interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_RX_FULL interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x1
-                M_RX_FULL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RX_FULL interrupt is masked
-                        ENABLED = 0x0,
-                        ///  RX_FULL interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_TX_OVER interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x1
-                M_TX_OVER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  TX_OVER interrupt is masked
-                        ENABLED = 0x0,
-                        ///  TX_OVER interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_TX_EMPTY interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x1
-                M_TX_EMPTY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  TX_EMPTY interrupt is masked
-                        ENABLED = 0x0,
-                        ///  TX_EMPTY interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_RD_REQ interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x1
-                M_RD_REQ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RD_REQ interrupt is masked
-                        ENABLED = 0x0,
-                        ///  RD_REQ interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_TX_ABRT interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x1
-                M_TX_ABRT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  TX_ABORT interrupt is masked
-                        ENABLED = 0x0,
-                        ///  TX_ABORT interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_RX_DONE interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x1
-                M_RX_DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RX_DONE interrupt is masked
-                        ENABLED = 0x0,
-                        ///  RX_DONE interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_ACTIVITY interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x0
-                M_ACTIVITY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  ACTIVITY interrupt is masked
-                        ENABLED = 0x0,
-                        ///  ACTIVITY interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_STOP_DET interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x0
-                M_STOP_DET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  STOP_DET interrupt is masked
-                        ENABLED = 0x0,
-                        ///  STOP_DET interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_START_DET interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x0
-                M_START_DET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  START_DET interrupt is masked
-                        ENABLED = 0x0,
-                        ///  START_DET interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_GEN_CALL interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x1
-                M_GEN_CALL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  GEN_CALL interrupt is masked
-                        ENABLED = 0x0,
-                        ///  GEN_CALL interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                ///  This bit masks the R_RESTART_DET interrupt in IC_INTR_STAT register.
-                ///  Reset value: 0x0
-                M_RESTART_DET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RESTART_DET interrupt is masked
-                        ENABLED = 0x0,
-                        ///  RESTART_DET interrupt is unmasked
-                        DISABLED = 0x1,
-                    },
-                },
-                padding: u19,
-            }),
-            ///  I2C Raw Interrupt Status Register
-            ///  Unlike the IC_INTR_STAT register, these bits are not masked so they always show the true status of the DW_apb_i2c.
-            IC_RAW_INTR_STAT: mmio.Mmio(packed struct(u32) {
-                ///  Set if the processor attempts to read the receive buffer when it is empty by reading from the IC_DATA_CMD register. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
-                ///  Reset value: 0x0
-                RX_UNDER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RX_UNDER interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  RX_UNDER interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  Set if the receive buffer is completely filled to IC_RX_BUFFER_DEPTH and an additional byte is received from an external I2C device. The DW_apb_i2c acknowledges this, but any data bytes received after the FIFO is full are lost. If the module is disabled (IC_ENABLE[0]=0), this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
-                ///  Note: If bit 9 of the IC_CON register (RX_FIFO_FULL_HLD_CTRL) is programmed to HIGH, then the RX_OVER interrupt never occurs, because the Rx FIFO never overflows.
-                ///  Reset value: 0x0
-                RX_OVER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RX_OVER interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  RX_OVER interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  Set when the receive buffer reaches or goes above the RX_TL threshold in the IC_RX_TL register. It is automatically cleared by hardware when buffer level goes below the threshold. If the module is disabled (IC_ENABLE[0]=0), the RX FIFO is flushed and held in reset; therefore the RX FIFO is not full. So this bit is cleared once the IC_ENABLE bit 0 is programmed with a 0, regardless of the activity that continues.
-                ///  Reset value: 0x0
-                RX_FULL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RX_FULL interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  RX_FULL interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  Set during transmit if the transmit buffer is filled to IC_TX_BUFFER_DEPTH and the processor attempts to issue another I2C command by writing to the IC_DATA_CMD register. When the module is disabled, this bit keeps its level until the master or slave state machines go into idle, and when ic_en goes to 0, this interrupt is cleared.
-                ///  Reset value: 0x0
-                TX_OVER: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  TX_OVER interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  TX_OVER interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  The behavior of the TX_EMPTY interrupt status differs based on the TX_EMPTY_CTRL selection in the IC_CON register. - When TX_EMPTY_CTRL = 0: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register. - When TX_EMPTY_CTRL = 1: This bit is set to 1 when the transmit buffer is at or below the threshold value set in the IC_TX_TL register and the transmission of the address/data from the internal shift register for the most recently popped command is completed. It is automatically cleared by hardware when the buffer level goes above the threshold. When IC_ENABLE[0] is set to 0, the TX FIFO is flushed and held in reset. There the TX FIFO looks like it has no data within it, so this bit is set to 1, provided there is activity in the master or slave state machines. When there is no longer any activity, then with ic_en=0, this bit is set to 0.
-                ///  Reset value: 0x0.
-                TX_EMPTY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  TX_EMPTY interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  TX_EMPTY interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  This bit is set to 1 when DW_apb_i2c is acting as a slave and another I2C master is attempting to read data from DW_apb_i2c. The DW_apb_i2c holds the I2C bus in a wait state (SCL=0) until this interrupt is serviced, which means that the slave has been addressed by a remote master that is asking for data to be transferred. The processor must respond to this interrupt and then write the requested data to the IC_DATA_CMD register. This bit is set to 0 just after the processor reads the IC_CLR_RD_REQ register.
-                ///  Reset value: 0x0
-                RD_REQ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RD_REQ interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  RD_REQ interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  This bit indicates if DW_apb_i2c, as an I2C transmitter, is unable to complete the intended actions on the contents of the transmit FIFO. This situation can occur both as an I2C master or an I2C slave, and is referred to as a 'transmit abort'. When this bit is set to 1, the IC_TX_ABRT_SOURCE register indicates the reason why the transmit abort takes places.
-                ///  Note: The DW_apb_i2c flushes/resets/empties the TX_FIFO and RX_FIFO whenever there is a transmit abort caused by any of the events tracked by the IC_TX_ABRT_SOURCE register. The FIFOs remains in this flushed state until the register IC_CLR_TX_ABRT is read. Once this read is performed, the Tx FIFO is then ready to accept more data bytes from the APB interface.
-                ///  Reset value: 0x0
-                TX_ABRT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  TX_ABRT interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  TX_ABRT interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  When the DW_apb_i2c is acting as a slave-transmitter, this bit is set to 1 if the master does not acknowledge a transmitted byte. This occurs on the last byte of the transmission, indicating that the transmission is done.
-                ///  Reset value: 0x0
-                RX_DONE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RX_DONE interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  RX_DONE interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  This bit captures DW_apb_i2c activity and stays set until it is cleared. There are four ways to clear it: - Disabling the DW_apb_i2c - Reading the IC_CLR_ACTIVITY register - Reading the IC_CLR_INTR register - System reset Once this bit is set, it stays set unless one of the four methods is used to clear it. Even if the DW_apb_i2c module is idle, this bit remains set until cleared, indicating that there was activity on the bus.
-                ///  Reset value: 0x0
-                ACTIVITY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RAW_INTR_ACTIVITY interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  RAW_INTR_ACTIVITY interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  Indicates whether a STOP condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
-                ///  In Slave Mode: - If IC_CON[7]=1'b1 (STOP_DET_IFADDRESSED), the STOP_DET interrupt will be issued only if slave is addressed. Note: During a general call address, this slave does not issue a STOP_DET interrupt if STOP_DET_IF_ADDRESSED=1'b1, even if the slave responds to the general call address by generating ACK. The STOP_DET interrupt is generated only when the transmitted address matches the slave address (SAR). - If IC_CON[7]=1'b0 (STOP_DET_IFADDRESSED), the STOP_DET interrupt is issued irrespective of whether it is being addressed. In Master Mode: - If IC_CON[10]=1'b1 (STOP_DET_IF_MASTER_ACTIVE),the STOP_DET interrupt will be issued only if Master is active. - If IC_CON[10]=1'b0 (STOP_DET_IFADDRESSED),the STOP_DET interrupt will be issued irrespective of whether master is active or not. Reset value: 0x0
-                STOP_DET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  STOP_DET interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  STOP_DET interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  Indicates whether a START or RESTART condition has occurred on the I2C interface regardless of whether DW_apb_i2c is operating in slave or master mode.
-                ///  Reset value: 0x0
-                START_DET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  START_DET interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  START_DET interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  Set only when a General Call address is received and it is acknowledged. It stays set until it is cleared either by disabling DW_apb_i2c or when the CPU reads bit 0 of the IC_CLR_GEN_CALL register. DW_apb_i2c stores the received data in the Rx buffer.
-                ///  Reset value: 0x0
-                GEN_CALL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  GEN_CALL interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  GEN_CALL interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  Indicates whether a RESTART condition has occurred on the I2C interface when DW_apb_i2c is operating in Slave mode and the slave is being addressed. Enabled only when IC_SLV_RESTART_DET_EN=1.
-                ///  Note: However, in high-speed mode or during a START BYTE transfer, the RESTART comes before the address field as per the I2C protocol. In this case, the slave is not the addressed slave when the RESTART is issued, therefore DW_apb_i2c does not generate the RESTART_DET interrupt.
-                ///  Reset value: 0x0
-                RESTART_DET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  RESTART_DET interrupt is inactive
-                        INACTIVE = 0x0,
-                        ///  RESTART_DET interrupt is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                padding: u19,
-            }),
-            ///  I2C Receive FIFO Threshold Register
-            IC_RX_TL: mmio.Mmio(packed struct(u32) {
-                ///  Receive FIFO Threshold Level.
-                ///  Controls the level of entries (or above) that triggers the RX_FULL interrupt (bit 2 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that hardware does not allow this value to be set to a value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 1 entry, and a value of 255 sets the threshold for 256 entries.
-                RX_TL: u8,
-                padding: u24,
-            }),
-            ///  I2C Transmit FIFO Threshold Register
-            IC_TX_TL: mmio.Mmio(packed struct(u32) {
-                ///  Transmit FIFO Threshold Level.
-                ///  Controls the level of entries (or below) that trigger the TX_EMPTY interrupt (bit 4 in IC_RAW_INTR_STAT register). The valid range is 0-255, with the additional restriction that it may not be set to value larger than the depth of the buffer. If an attempt is made to do that, the actual value set will be the maximum depth of the buffer. A value of 0 sets the threshold for 0 entries, and a value of 255 sets the threshold for 255 entries.
-                TX_TL: u8,
-                padding: u24,
-            }),
-            ///  Clear Combined and Individual Interrupt Register
-            IC_CLR_INTR: mmio.Mmio(packed struct(u32) {
-                ///  Read this register to clear the combined interrupt, all individual interrupts, and the IC_TX_ABRT_SOURCE register. This bit does not clear hardware clearable interrupts but software clearable interrupts. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
-                ///  Reset value: 0x0
-                CLR_INTR: u1,
-                padding: u31,
-            }),
-            ///  Clear RX_UNDER Interrupt Register
-            IC_CLR_RX_UNDER: mmio.Mmio(packed struct(u32) {
-                ///  Read this register to clear the RX_UNDER interrupt (bit 0) of the IC_RAW_INTR_STAT register.
-                ///  Reset value: 0x0
-                CLR_RX_UNDER: u1,
-                padding: u31,
-            }),
-            ///  Clear RX_OVER Interrupt Register
-            IC_CLR_RX_OVER: mmio.Mmio(packed struct(u32) {
-                ///  Read this register to clear the RX_OVER interrupt (bit 1) of the IC_RAW_INTR_STAT register.
-                ///  Reset value: 0x0
-                CLR_RX_OVER: u1,
-                padding: u31,
-            }),
-            ///  Clear TX_OVER Interrupt Register
-            IC_CLR_TX_OVER: mmio.Mmio(packed struct(u32) {
-                ///  Read this register to clear the TX_OVER interrupt (bit 3) of the IC_RAW_INTR_STAT register.
-                ///  Reset value: 0x0
-                CLR_TX_OVER: u1,
-                padding: u31,
-            }),
-            ///  Clear RD_REQ Interrupt Register
-            IC_CLR_RD_REQ: mmio.Mmio(packed struct(u32) {
-                ///  Read this register to clear the RD_REQ interrupt (bit 5) of the IC_RAW_INTR_STAT register.
-                ///  Reset value: 0x0
-                CLR_RD_REQ: u1,
-                padding: u31,
-            }),
-            ///  Clear TX_ABRT Interrupt Register
-            IC_CLR_TX_ABRT: mmio.Mmio(packed struct(u32) {
-                ///  Read this register to clear the TX_ABRT interrupt (bit 6) of the IC_RAW_INTR_STAT register, and the IC_TX_ABRT_SOURCE register. This also releases the TX FIFO from the flushed/reset state, allowing more writes to the TX FIFO. Refer to Bit 9 of the IC_TX_ABRT_SOURCE register for an exception to clearing IC_TX_ABRT_SOURCE.
-                ///  Reset value: 0x0
-                CLR_TX_ABRT: u1,
-                padding: u31,
-            }),
-            ///  Clear RX_DONE Interrupt Register
-            IC_CLR_RX_DONE: mmio.Mmio(packed struct(u32) {
-                ///  Read this register to clear the RX_DONE interrupt (bit 7) of the IC_RAW_INTR_STAT register.
-                ///  Reset value: 0x0
-                CLR_RX_DONE: u1,
-                padding: u31,
-            }),
-            ///  Clear ACTIVITY Interrupt Register
-            IC_CLR_ACTIVITY: mmio.Mmio(packed struct(u32) {
-                ///  Reading this register clears the ACTIVITY interrupt if the I2C is not active anymore. If the I2C module is still active on the bus, the ACTIVITY interrupt bit continues to be set. It is automatically cleared by hardware if the module is disabled and if there is no further activity on the bus. The value read from this register to get status of the ACTIVITY interrupt (bit 8) of the IC_RAW_INTR_STAT register.
-                ///  Reset value: 0x0
-                CLR_ACTIVITY: u1,
-                padding: u31,
-            }),
-            ///  Clear STOP_DET Interrupt Register
-            IC_CLR_STOP_DET: mmio.Mmio(packed struct(u32) {
-                ///  Read this register to clear the STOP_DET interrupt (bit 9) of the IC_RAW_INTR_STAT register.
-                ///  Reset value: 0x0
-                CLR_STOP_DET: u1,
-                padding: u31,
-            }),
-            ///  Clear START_DET Interrupt Register
-            IC_CLR_START_DET: mmio.Mmio(packed struct(u32) {
-                ///  Read this register to clear the START_DET interrupt (bit 10) of the IC_RAW_INTR_STAT register.
-                ///  Reset value: 0x0
-                CLR_START_DET: u1,
-                padding: u31,
-            }),
-            ///  Clear GEN_CALL Interrupt Register
-            IC_CLR_GEN_CALL: mmio.Mmio(packed struct(u32) {
-                ///  Read this register to clear the GEN_CALL interrupt (bit 11) of IC_RAW_INTR_STAT register.
-                ///  Reset value: 0x0
-                CLR_GEN_CALL: u1,
-                padding: u31,
-            }),
-            ///  I2C Enable Register
-            IC_ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Controls whether the DW_apb_i2c is enabled. - 0: Disables DW_apb_i2c (TX and RX FIFOs are held in an erased state) - 1: Enables DW_apb_i2c Software can disable DW_apb_i2c while it is active. However, it is important that care be taken to ensure that DW_apb_i2c is disabled properly. A recommended procedure is described in 'Disabling DW_apb_i2c'.
-                ///  When DW_apb_i2c is disabled, the following occurs: - The TX FIFO and RX FIFO get flushed. - Status bits in the IC_INTR_STAT register are still active until DW_apb_i2c goes into IDLE state. If the module is transmitting, it stops as well as deletes the contents of the transmit buffer after the current transfer is complete. If the module is receiving, the DW_apb_i2c stops the current transfer at the end of the current byte and does not acknowledge the transfer.
-                ///  In systems with asynchronous pclk and ic_clk when IC_CLK_TYPE parameter set to asynchronous (1), there is a two ic_clk delay when enabling or disabling the DW_apb_i2c. For a detailed description on how to disable DW_apb_i2c, refer to 'Disabling DW_apb_i2c'
-                ///  Reset value: 0x0
-                ENABLE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  I2C is disabled
-                        DISABLED = 0x0,
-                        ///  I2C is enabled
-                        ENABLED = 0x1,
-                    },
-                },
-                ///  When set, the controller initiates the transfer abort. - 0: ABORT not initiated or ABORT done - 1: ABORT operation in progress The software can abort the I2C transfer in master mode by setting this bit. The software can set this bit only when ENABLE is already set; otherwise, the controller ignores any write to ABORT bit. The software cannot clear the ABORT bit once set. In response to an ABORT, the controller issues a STOP and flushes the Tx FIFO after completing the current transfer, then sets the TX_ABORT interrupt after the abort operation. The ABORT bit is cleared automatically after the abort operation.
-                ///  For a detailed description on how to abort I2C transfers, refer to 'Aborting I2C Transfers'.
-                ///  Reset value: 0x0
-                ABORT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  ABORT operation not in progress
-                        DISABLE = 0x0,
-                        ///  ABORT operation in progress
-                        ENABLED = 0x1,
-                    },
-                },
-                ///  In Master mode: - 1'b1: Blocks the transmission of data on I2C bus even if Tx FIFO has data to transmit. - 1'b0: The transmission of data starts on I2C bus automatically, as soon as the first data is available in the Tx FIFO. Note: To block the execution of Master commands, set the TX_CMD_BLOCK bit only when Tx FIFO is empty (IC_STATUS[2]==1) and Master is in Idle state (IC_STATUS[5] == 0). Any further commands put in the Tx FIFO are not executed until TX_CMD_BLOCK bit is unset. Reset value: IC_TX_CMD_BLOCK_DEFAULT
-                TX_CMD_BLOCK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Tx Command execution not blocked
-                        NOT_BLOCKED = 0x0,
-                        ///  Tx Command execution blocked
-                        BLOCKED = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  I2C Status Register
-            ///  This is a read-only register used to indicate the current transfer status and FIFO status. The status register may be read at any time. None of the bits in this register request an interrupt.
-            ///  When the I2C is disabled by writing 0 in bit 0 of the IC_ENABLE register: - Bits 1 and 2 are set to 1 - Bits 3 and 10 are set to 0 When the master or slave state machines goes to idle and ic_en=0: - Bits 5 and 6 are set to 0
-            IC_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  I2C Activity Status. Reset value: 0x0
-                ACTIVITY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  I2C is idle
-                        INACTIVE = 0x0,
-                        ///  I2C is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  Transmit FIFO Not Full. Set when the transmit FIFO contains one or more empty locations, and is cleared when the FIFO is full. - 0: Transmit FIFO is full - 1: Transmit FIFO is not full Reset value: 0x1
-                TFNF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Tx FIFO is full
-                        FULL = 0x0,
-                        ///  Tx FIFO not full
-                        NOT_FULL = 0x1,
-                    },
-                },
-                ///  Transmit FIFO Completely Empty. When the transmit FIFO is completely empty, this bit is set. When it contains one or more valid entries, this bit is cleared. This bit field does not request an interrupt. - 0: Transmit FIFO is not empty - 1: Transmit FIFO is empty Reset value: 0x1
-                TFE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Tx FIFO not empty
-                        NON_EMPTY = 0x0,
-                        ///  Tx FIFO is empty
-                        EMPTY = 0x1,
-                    },
-                },
-                ///  Receive FIFO Not Empty. This bit is set when the receive FIFO contains one or more entries; it is cleared when the receive FIFO is empty. - 0: Receive FIFO is empty - 1: Receive FIFO is not empty Reset value: 0x0
-                RFNE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Rx FIFO is empty
-                        EMPTY = 0x0,
-                        ///  Rx FIFO not empty
-                        NOT_EMPTY = 0x1,
-                    },
-                },
-                ///  Receive FIFO Completely Full. When the receive FIFO is completely full, this bit is set. When the receive FIFO contains one or more empty location, this bit is cleared. - 0: Receive FIFO is not full - 1: Receive FIFO is full Reset value: 0x0
-                RFF: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Rx FIFO not full
-                        NOT_FULL = 0x0,
-                        ///  Rx FIFO is full
-                        FULL = 0x1,
-                    },
-                },
-                ///  Master FSM Activity Status. When the Master Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Master FSM is in IDLE state so the Master part of DW_apb_i2c is not Active - 1: Master FSM is not in IDLE state so the Master part of DW_apb_i2c is Active Note: IC_STATUS[0]-that is, ACTIVITY bit-is the OR of SLV_ACTIVITY and MST_ACTIVITY bits.
-                ///  Reset value: 0x0
-                MST_ACTIVITY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Master is idle
-                        IDLE = 0x0,
-                        ///  Master not idle
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  Slave FSM Activity Status. When the Slave Finite State Machine (FSM) is not in the IDLE state, this bit is set. - 0: Slave FSM is in IDLE state so the Slave part of DW_apb_i2c is not Active - 1: Slave FSM is not in IDLE state so the Slave part of DW_apb_i2c is Active Reset value: 0x0
-                SLV_ACTIVITY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Slave is idle
-                        IDLE = 0x0,
-                        ///  Slave not idle
-                        ACTIVE = 0x1,
-                    },
-                },
-                padding: u25,
-            }),
-            ///  I2C Transmit FIFO Level Register This register contains the number of valid data entries in the transmit FIFO buffer. It is cleared whenever: - The I2C is disabled - There is a transmit abort - that is, TX_ABRT bit is set in the IC_RAW_INTR_STAT register - The slave bulk transmit mode is aborted The register increments whenever data is placed into the transmit FIFO and decrements when data is taken from the transmit FIFO.
-            IC_TXFLR: mmio.Mmio(packed struct(u32) {
-                ///  Transmit FIFO Level. Contains the number of valid data entries in the transmit FIFO.
-                ///  Reset value: 0x0
-                TXFLR: u5,
-                padding: u27,
-            }),
-            ///  I2C Receive FIFO Level Register This register contains the number of valid data entries in the receive FIFO buffer. It is cleared whenever: - The I2C is disabled - Whenever there is a transmit abort caused by any of the events tracked in IC_TX_ABRT_SOURCE The register increments whenever data is placed into the receive FIFO and decrements when data is taken from the receive FIFO.
-            IC_RXFLR: mmio.Mmio(packed struct(u32) {
-                ///  Receive FIFO Level. Contains the number of valid data entries in the receive FIFO.
-                ///  Reset value: 0x0
-                RXFLR: u5,
-                padding: u27,
-            }),
-            ///  I2C SDA Hold Time Length Register
-            ///  The bits [15:0] of this register are used to control the hold time of SDA during transmit in both slave and master mode (after SCL goes from HIGH to LOW).
-            ///  The bits [23:16] of this register are used to extend the SDA transition (if any) whenever SCL is HIGH in the receiver in either master or slave mode.
-            ///  Writes to this register succeed only when IC_ENABLE[0]=0.
-            ///  The values in this register are in units of ic_clk period. The value programmed in IC_SDA_TX_HOLD must be greater than the minimum hold time in each mode (one cycle in master mode, seven cycles in slave mode) for the value to be implemented.
-            ///  The programmed SDA hold time during transmit (IC_SDA_TX_HOLD) cannot exceed at any time the duration of the low part of scl. Therefore the programmed value cannot be larger than N_SCL_LOW-2, where N_SCL_LOW is the duration of the low part of the scl period measured in ic_clk cycles.
-            IC_SDA_HOLD: mmio.Mmio(packed struct(u32) {
-                ///  Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a transmitter.
-                ///  Reset value: IC_DEFAULT_SDA_HOLD[15:0].
-                IC_SDA_TX_HOLD: u16,
-                ///  Sets the required SDA hold time in units of ic_clk period, when DW_apb_i2c acts as a receiver.
-                ///  Reset value: IC_DEFAULT_SDA_HOLD[23:16].
-                IC_SDA_RX_HOLD: u8,
-                padding: u8,
-            }),
-            ///  I2C Transmit Abort Source Register
-            ///  This register has 32 bits that indicate the source of the TX_ABRT bit. Except for Bit 9, this register is cleared whenever the IC_CLR_TX_ABRT register or the IC_CLR_INTR register is read. To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; RESTART must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]).
-            ///  Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, Bit 9 clears for one cycle and is then re-asserted.
-            IC_TX_ABRT_SOURCE: mmio.Mmio(packed struct(u32) {
-                ///  This field indicates that the Master is in 7-bit addressing mode and the address sent was not acknowledged by any slave.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-                ABRT_7B_ADDR_NOACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  This abort is not generated
-                        INACTIVE = 0x0,
-                        ///  This abort is generated because of NOACK for 7-bit address
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  This field indicates that the Master is in 10-bit address mode and the first 10-bit address byte was not acknowledged by any slave.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-                ABRT_10ADDR1_NOACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  This abort is not generated
-                        INACTIVE = 0x0,
-                        ///  Byte 1 of 10Bit Address not ACKed by any slave
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  This field indicates that the Master is in 10-bit address mode and that the second address byte of the 10-bit address was not acknowledged by any slave.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-                ABRT_10ADDR2_NOACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  This abort is not generated
-                        INACTIVE = 0x0,
-                        ///  Byte 2 of 10Bit Address not ACKed by any slave
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  This field indicates the master-mode only bit. When the master receives an acknowledgement for the address, but when it sends data byte(s) following the address, it did not receive an acknowledge from the remote slave(s).
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Transmitter
-                ABRT_TXDATA_NOACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Transmitted data non-ACKed by addressed slave-scenario not present
-                        ABRT_TXDATA_NOACK_VOID = 0x0,
-                        ///  Transmitted data not ACKed by addressed slave
-                        ABRT_TXDATA_NOACK_GENERATED = 0x1,
-                    },
-                },
-                ///  This field indicates that DW_apb_i2c in master mode has sent a General Call and no slave on the bus acknowledged the General Call.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Transmitter
-                ABRT_GCALL_NOACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  GCALL not ACKed by any slave-scenario not present
-                        ABRT_GCALL_NOACK_VOID = 0x0,
-                        ///  GCALL not ACKed by any slave
-                        ABRT_GCALL_NOACK_GENERATED = 0x1,
-                    },
-                },
-                ///  This field indicates that DW_apb_i2c in the master mode has sent a General Call but the user programmed the byte following the General Call to be a read from the bus (IC_DATA_CMD[9] is set to 1).
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Transmitter
-                ABRT_GCALL_READ: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  GCALL is followed by read from bus-scenario not present
-                        ABRT_GCALL_READ_VOID = 0x0,
-                        ///  GCALL is followed by read from bus
-                        ABRT_GCALL_READ_GENERATED = 0x1,
-                    },
-                },
-                ///  This field indicates that the Master is in High Speed mode and the High Speed Master code was acknowledged (wrong behavior).
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master
-                ABRT_HS_ACKDET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  HS Master code ACKed in HS Mode- scenario not present
-                        ABRT_HS_ACK_VOID = 0x0,
-                        ///  HS Master code ACKed in HS Mode
-                        ABRT_HS_ACK_GENERATED = 0x1,
-                    },
-                },
-                ///  This field indicates that the Master has sent a START Byte and the START Byte was acknowledged (wrong behavior).
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master
-                ABRT_SBYTE_ACKDET: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  ACK detected for START byte- scenario not present
-                        ABRT_SBYTE_ACKDET_VOID = 0x0,
-                        ///  ACK detected for START byte
-                        ABRT_SBYTE_ACKDET_GENERATED = 0x1,
-                    },
-                },
-                ///  This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to use the master to transfer data in High Speed mode.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-                ABRT_HS_NORSTRT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  User trying to switch Master to HS mode when RESTART disabled- scenario not present
-                        ABRT_HS_NORSTRT_VOID = 0x0,
-                        ///  User trying to switch Master to HS mode when RESTART disabled
-                        ABRT_HS_NORSTRT_GENERATED = 0x1,
-                    },
-                },
-                ///  To clear Bit 9, the source of the ABRT_SBYTE_NORSTRT must be fixed first; restart must be enabled (IC_CON[5]=1), the SPECIAL bit must be cleared (IC_TAR[11]), or the GC_OR_START bit must be cleared (IC_TAR[10]). Once the source of the ABRT_SBYTE_NORSTRT is fixed, then this bit can be cleared in the same manner as other bits in this register. If the source of the ABRT_SBYTE_NORSTRT is not fixed before attempting to clear this bit, bit 9 clears for one cycle and then gets reasserted. When this field is set to 1, the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the user is trying to send a START Byte.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master
-                ABRT_SBYTE_NORSTRT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  User trying to send START byte when RESTART disabled- scenario not present
-                        ABRT_SBYTE_NORSTRT_VOID = 0x0,
-                        ///  User trying to send START byte when RESTART disabled
-                        ABRT_SBYTE_NORSTRT_GENERATED = 0x1,
-                    },
-                },
-                ///  This field indicates that the restart is disabled (IC_RESTART_EN bit (IC_CON[5]) =0) and the master sends a read command in 10-bit addressing mode.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Receiver
-                ABRT_10B_RD_NORSTRT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Master not trying to read in 10Bit addressing mode when RESTART disabled
-                        ABRT_10B_RD_VOID = 0x0,
-                        ///  Master trying to read in 10Bit addressing mode when RESTART disabled
-                        ABRT_10B_RD_GENERATED = 0x1,
-                    },
-                },
-                ///  This field indicates that the User tries to initiate a Master operation with the Master mode disabled.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Transmitter or Master-Receiver
-                ABRT_MASTER_DIS: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  User initiating master operation when MASTER disabled- scenario not present
-                        ABRT_MASTER_DIS_VOID = 0x0,
-                        ///  User initiating master operation when MASTER disabled
-                        ABRT_MASTER_DIS_GENERATED = 0x1,
-                    },
-                },
-                ///  This field specifies that the Master has lost arbitration, or if IC_TX_ABRT_SOURCE[14] is also set, then the slave transmitter has lost arbitration.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
-                ARB_LOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Master or Slave-Transmitter lost arbitration- scenario not present
-                        ABRT_LOST_VOID = 0x0,
-                        ///  Master or Slave-Transmitter lost arbitration
-                        ABRT_LOST_GENERATED = 0x1,
-                    },
-                },
-                ///  This field specifies that the Slave has received a read command and some data exists in the TX FIFO, so the slave issues a TX_ABRT interrupt to flush old data in TX FIFO.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Slave-Transmitter
-                ABRT_SLVFLUSH_TXFIFO: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Slave flushes existing data in TX-FIFO upon getting read command- scenario not present
-                        ABRT_SLVFLUSH_TXFIFO_VOID = 0x0,
-                        ///  Slave flushes existing data in TX-FIFO upon getting read command
-                        ABRT_SLVFLUSH_TXFIFO_GENERATED = 0x1,
-                    },
-                },
-                ///  This field indicates that a Slave has lost the bus while transmitting data to a remote master. IC_TX_ABRT_SOURCE[12] is set at the same time. Note: Even though the slave never 'owns' the bus, something could go wrong on the bus. This is a fail safe check. For instance, during a data transmission at the low-to-high transition of SCL, if what is on the data bus is not what is supposed to be transmitted, then DW_apb_i2c no longer own the bus.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Slave-Transmitter
-                ABRT_SLV_ARBLOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Slave lost arbitration to remote master- scenario not present
-                        ABRT_SLV_ARBLOST_VOID = 0x0,
-                        ///  Slave lost arbitration to remote master
-                        ABRT_SLV_ARBLOST_GENERATED = 0x1,
-                    },
-                },
-                ///  1: When the processor side responds to a slave mode request for data to be transmitted to a remote master and user writes a 1 in CMD (bit 8) of IC_DATA_CMD register.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Slave-Transmitter
-                ABRT_SLVRD_INTX: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Slave trying to transmit to remote master in read mode- scenario not present
-                        ABRT_SLVRD_INTX_VOID = 0x0,
-                        ///  Slave trying to transmit to remote master in read mode
-                        ABRT_SLVRD_INTX_GENERATED = 0x1,
-                    },
-                },
-                ///  This is a master-mode-only bit. Master has detected the transfer abort (IC_ENABLE[1])
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Transmitter
-                ABRT_USER_ABRT: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Transfer abort detected by master- scenario not present
-                        ABRT_USER_ABRT_VOID = 0x0,
-                        ///  Transfer abort detected by master
-                        ABRT_USER_ABRT_GENERATED = 0x1,
-                    },
-                },
-                reserved23: u6,
-                ///  This field indicates the number of Tx FIFO Data Commands which are flushed due to TX_ABRT interrupt. It is cleared whenever I2C is disabled.
-                ///  Reset value: 0x0
-                ///  Role of DW_apb_i2c: Master-Transmitter or Slave-Transmitter
-                TX_FLUSH_CNT: u9,
-            }),
-            ///  Generate Slave Data NACK Register
-            ///  The register is used to generate a NACK for the data part of a transfer when DW_apb_i2c is acting as a slave-receiver. This register only exists when the IC_SLV_DATA_NACK_ONLY parameter is set to 1. When this parameter disabled, this register does not exist and writing to the register's address has no effect.
-            ///  A write can occur on this register if both of the following conditions are met: - DW_apb_i2c is disabled (IC_ENABLE[0] = 0) - Slave part is inactive (IC_STATUS[6] = 0) Note: The IC_STATUS[6] is a register read-back location for the internal slv_activity signal; the user should poll this before writing the ic_slv_data_nack_only bit.
-            IC_SLV_DATA_NACK_ONLY: mmio.Mmio(packed struct(u32) {
-                ///  Generate NACK. This NACK generation only occurs when DW_apb_i2c is a slave-receiver. If this register is set to a value of 1, it can only generate a NACK after a data byte is received; hence, the data transfer is aborted and the data received is not pushed to the receive buffer.
-                ///  When the register is set to a value of 0, it generates NACK/ACK, depending on normal criteria. - 1: generate NACK after data byte received - 0: generate NACK/ACK normally Reset value: 0x0
-                NACK: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Slave receiver generates NACK normally
-                        DISABLED = 0x0,
-                        ///  Slave receiver generates NACK upon data reception only
-                        ENABLED = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  DMA Control Register
-            ///  The register is used to enable the DMA Controller interface operation. There is a separate bit for transmit and receive. This can be programmed regardless of the state of IC_ENABLE.
-            IC_DMA_CR: mmio.Mmio(packed struct(u32) {
-                ///  Receive DMA Enable. This bit enables/disables the receive FIFO DMA channel. Reset value: 0x0
-                RDMAE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Receive FIFO DMA channel disabled
-                        DISABLED = 0x0,
-                        ///  Receive FIFO DMA channel enabled
-                        ENABLED = 0x1,
-                    },
-                },
-                ///  Transmit DMA Enable. This bit enables/disables the transmit FIFO DMA channel. Reset value: 0x0
-                TDMAE: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  transmit FIFO DMA channel disabled
-                        DISABLED = 0x0,
-                        ///  Transmit FIFO DMA channel enabled
-                        ENABLED = 0x1,
-                    },
-                },
-                padding: u30,
-            }),
-            ///  DMA Transmit Data Level Register
-            IC_DMA_TDLR: mmio.Mmio(packed struct(u32) {
-                ///  Transmit Data Level. This bit field controls the level at which a DMA request is made by the transmit logic. It is equal to the watermark level; that is, the dma_tx_req signal is generated when the number of valid data entries in the transmit FIFO is equal to or below this field value, and TDMAE = 1.
-                ///  Reset value: 0x0
-                DMATDL: u4,
-                padding: u28,
-            }),
-            ///  I2C Receive Data Level Register
-            IC_DMA_RDLR: mmio.Mmio(packed struct(u32) {
-                ///  Receive Data Level. This bit field controls the level at which a DMA request is made by the receive logic. The watermark level = DMARDL+1; that is, dma_rx_req is generated when the number of valid data entries in the receive FIFO is equal to or more than this field value + 1, and RDMAE =1. For instance, when DMARDL is 0, then dma_rx_req is asserted when 1 or more data entries are present in the receive FIFO.
-                ///  Reset value: 0x0
-                DMARDL: u4,
-                padding: u28,
-            }),
-            ///  I2C SDA Setup Register
-            ///  This register controls the amount of time delay (in terms of number of ic_clk clock periods) introduced in the rising edge of SCL - relative to SDA changing - when DW_apb_i2c services a read request in a slave-transmitter operation. The relevant I2C requirement is tSU:DAT (note 4) as detailed in the I2C Bus Specification. This register must be programmed with a value equal to or greater than 2.
-            ///  Writes to this register succeed only when IC_ENABLE[0] = 0.
-            ///  Note: The length of setup time is calculated using [(IC_SDA_SETUP - 1) * (ic_clk_period)], so if the user requires 10 ic_clk periods of setup time, they should program a value of 11. The IC_SDA_SETUP register is only used by the DW_apb_i2c when operating as a slave transmitter.
-            IC_SDA_SETUP: mmio.Mmio(packed struct(u32) {
-                ///  SDA Setup. It is recommended that if the required delay is 1000ns, then for an ic_clk frequency of 10 MHz, IC_SDA_SETUP should be programmed to a value of 11. IC_SDA_SETUP must be programmed with a minimum value of 2.
-                SDA_SETUP: u8,
-                padding: u24,
-            }),
-            ///  I2C ACK General Call Register
-            ///  The register controls whether DW_apb_i2c responds with a ACK or NACK when it receives an I2C General Call address.
-            ///  This register is applicable only when the DW_apb_i2c is in slave mode.
-            IC_ACK_GENERAL_CALL: mmio.Mmio(packed struct(u32) {
-                ///  ACK General Call. When set to 1, DW_apb_i2c responds with a ACK (by asserting ic_data_oe) when it receives a General Call. Otherwise, DW_apb_i2c responds with a NACK (by negating ic_data_oe).
-                ACK_GEN_CALL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Generate NACK for a General Call
-                        DISABLED = 0x0,
-                        ///  Generate ACK for a General Call
-                        ENABLED = 0x1,
-                    },
-                },
-                padding: u31,
-            }),
-            ///  I2C Enable Status Register
-            ///  The register is used to report the DW_apb_i2c hardware status when the IC_ENABLE[0] register is set from 1 to 0; that is, when DW_apb_i2c is disabled.
-            ///  If IC_ENABLE[0] has been set to 1, bits 2:1 are forced to 0, and bit 0 is forced to 1.
-            ///  If IC_ENABLE[0] has been set to 0, bits 2:1 is only be valid as soon as bit 0 is read as '0'.
-            ///  Note: When IC_ENABLE[0] has been set to 0, a delay occurs for bit 0 to be read as 0 because disabling the DW_apb_i2c depends on I2C bus activities.
-            IC_ENABLE_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  ic_en Status. This bit always reflects the value driven on the output port ic_en. - When read as 1, DW_apb_i2c is deemed to be in an enabled state. - When read as 0, DW_apb_i2c is deemed completely inactive. Note: The CPU can safely read this bit anytime. When this bit is read as 0, the CPU can safely read SLV_RX_DATA_LOST (bit 2) and SLV_DISABLED_WHILE_BUSY (bit 1).
-                ///  Reset value: 0x0
-                IC_EN: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  I2C disabled
-                        DISABLED = 0x0,
-                        ///  I2C enabled
-                        ENABLED = 0x1,
-                    },
-                },
-                ///  Slave Disabled While Busy (Transmit, Receive). This bit indicates if a potential or active Slave operation has been aborted due to the setting bit 0 of the IC_ENABLE register from 1 to 0. This bit is set when the CPU writes a 0 to the IC_ENABLE register while:
-                ///  (a) DW_apb_i2c is receiving the address byte of the Slave-Transmitter operation from a remote master;
-                ///  OR,
-                ///  (b) address and data bytes of the Slave-Receiver operation from a remote master.
-                ///  When read as 1, DW_apb_i2c is deemed to have forced a NACK during any part of an I2C transfer, irrespective of whether the I2C address matches the slave address set in DW_apb_i2c (IC_SAR register) OR if the transfer is completed before IC_ENABLE is set to 0 but has not taken effect.
-                ///  Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit will also be set to 1.
-                ///  When read as 0, DW_apb_i2c is deemed to have been disabled when there is master activity, or when the I2C bus is idle.
-                ///  Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
-                ///  Reset value: 0x0
-                SLV_DISABLED_WHILE_BUSY: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Slave is disabled when it is idle
-                        INACTIVE = 0x0,
-                        ///  Slave is disabled when it is active
-                        ACTIVE = 0x1,
-                    },
-                },
-                ///  Slave Received Data Lost. This bit indicates if a Slave-Receiver operation has been aborted with at least one data byte received from an I2C transfer due to the setting bit 0 of IC_ENABLE from 1 to 0. When read as 1, DW_apb_i2c is deemed to have been actively engaged in an aborted I2C transfer (with matching address) and the data phase of the I2C transfer has been entered, even though a data byte has been responded with a NACK.
-                ///  Note: If the remote I2C master terminates the transfer with a STOP condition before the DW_apb_i2c has a chance to NACK a transfer, and IC_ENABLE[0] has been set to 0, then this bit is also set to 1.
-                ///  When read as 0, DW_apb_i2c is deemed to have been disabled without being actively involved in the data phase of a Slave-Receiver transfer.
-                ///  Note: The CPU can safely read this bit when IC_EN (bit 0) is read as 0.
-                ///  Reset value: 0x0
-                SLV_RX_DATA_LOST: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  Slave RX Data is not lost
-                        INACTIVE = 0x0,
-                        ///  Slave RX Data is lost
-                        ACTIVE = 0x1,
-                    },
-                },
-                padding: u29,
-            }),
-            ///  I2C SS, FS or FM+ spike suppression limit
-            ///  This register is used to store the duration, measured in ic_clk cycles, of the longest spike that is filtered out by the spike suppression logic when the component is operating in SS, FS or FM+ modes. The relevant I2C requirement is tSP (table 4) as detailed in the I2C Bus Specification. This register must be programmed with a minimum value of 1.
-            IC_FS_SPKLEN: mmio.Mmio(packed struct(u32) {
-                ///  This register must be set before any I2C bus transaction can take place to ensure stable operation. This register sets the duration, measured in ic_clk cycles, of the longest spike in the SCL or SDA lines that will be filtered out by the spike suppression logic. This register can be written only when the I2C interface is disabled which corresponds to the IC_ENABLE[0] register being set to 0. Writes at other times have no effect. The minimum valid value is 1; hardware prevents values less than this being written, and if attempted results in 1 being set. or more information, refer to 'Spike Suppression'.
-                IC_FS_SPKLEN: u8,
-                padding: u24,
-            }),
-            reserved168: [4]u8,
-            ///  Clear RESTART_DET Interrupt Register
-            IC_CLR_RESTART_DET: mmio.Mmio(packed struct(u32) {
-                ///  Read this register to clear the RESTART_DET interrupt (bit 12) of IC_RAW_INTR_STAT register.
-                ///  Reset value: 0x0
-                CLR_RESTART_DET: u1,
-                padding: u31,
-            }),
-            reserved244: [72]u8,
-            ///  Component Parameter Register 1
-            ///  Note This register is not implemented and therefore reads as 0. If it was implemented it would be a constant read-only register that contains encoded information about the component's parameter settings. Fields shown below are the settings for those parameters
-            IC_COMP_PARAM_1: mmio.Mmio(packed struct(u32) {
-                ///  APB data bus width is 32 bits
-                APB_DATA_WIDTH: u2,
-                ///  MAX SPEED MODE = FAST MODE
-                MAX_SPEED_MODE: u2,
-                ///  Programmable count values for each mode.
-                HC_COUNT_VALUES: u1,
-                ///  COMBINED Interrupt outputs
-                INTR_IO: u1,
-                ///  DMA handshaking signals are enabled
-                HAS_DMA: u1,
-                ///  Encoded parameters not visible
-                ADD_ENCODED_PARAMS: u1,
-                ///  RX Buffer Depth = 16
-                RX_BUFFER_DEPTH: u8,
-                ///  TX Buffer Depth = 16
-                TX_BUFFER_DEPTH: u8,
-                padding: u8,
-            }),
-            ///  I2C Component Version Register
-            IC_COMP_VERSION: mmio.Mmio(packed struct(u32) {
-                IC_COMP_VERSION: u32,
-            }),
-            ///  I2C Component Type Register
-            IC_COMP_TYPE: mmio.Mmio(packed struct(u32) {
-                ///  Designware Component Type number = 0x44_57_01_40. This assigned unique hex value is constant and is derived from the two ASCII letters 'DW' followed by a 16-bit unsigned number.
-                IC_COMP_TYPE: u32,
-            }),
-        };
-
-        ///  Programmable IO block
-        pub const PIO0 = extern struct {
-            ///  PIO control register
-            CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Enable/disable each of the four state machines by writing 1/0 to each of these four bits. When disabled, a state machine will cease executing instructions, except those written directly to SMx_INSTR by the system. Multiple bits can be set/cleared at once to run/halt multiple state machines simultaneously.
-                SM_ENABLE: u4,
-                ///  Write 1 to instantly clear internal SM state which may be otherwise difficult to access and will affect future execution.
-                ///  Specifically, the following are cleared: input and output shift counters; the contents of the input shift register; the delay counter; the waiting-on-IRQ state; any stalled instruction written to SMx_INSTR or run by OUT/MOV EXEC; any pin write left asserted due to OUT_STICKY.
-                SM_RESTART: u4,
-                ///  Restart a state machine's clock divider from an initial phase of 0. Clock dividers are free-running, so once started, their output (including fractional jitter) is completely determined by the integer/fractional divisor configured in SMx_CLKDIV. This means that, if multiple clock dividers with the same divisor are restarted simultaneously, by writing multiple 1 bits to this field, the execution clocks of those state machines will run in precise lockstep.
-                ///  Note that setting/clearing SM_ENABLE does not stop the clock divider from running, so once multiple state machines' clocks are synchronised, it is safe to disable/reenable a state machine, whilst keeping the clock dividers in sync.
-                ///  Note also that CLKDIV_RESTART can be written to whilst the state machine is running, and this is useful to resynchronise clock dividers after the divisors (SMx_CLKDIV) have been changed on-the-fly.
-                CLKDIV_RESTART: u4,
-                padding: u20,
-            }),
-            ///  FIFO status register
-            FSTAT: mmio.Mmio(packed struct(u32) {
-                ///  State machine RX FIFO is full
-                RXFULL: u4,
-                reserved8: u4,
-                ///  State machine RX FIFO is empty
-                RXEMPTY: u4,
-                reserved16: u4,
-                ///  State machine TX FIFO is full
-                TXFULL: u4,
-                reserved24: u4,
-                ///  State machine TX FIFO is empty
-                TXEMPTY: u4,
-                padding: u4,
-            }),
-            ///  FIFO debug register
-            FDEBUG: mmio.Mmio(packed struct(u32) {
-                ///  State machine has stalled on full RX FIFO during a blocking PUSH, or an IN with autopush enabled. This flag is also set when a nonblocking PUSH to a full FIFO took place, in which case the state machine has dropped data. Write 1 to clear.
-                RXSTALL: u4,
-                reserved8: u4,
-                ///  RX FIFO underflow (i.e. read-on-empty by the system) has occurred. Write 1 to clear. Note that read-on-empty does not perturb the state of the FIFO in any way, but the data returned by reading from an empty FIFO is undefined, so this flag generally only becomes set due to some kind of software error.
-                RXUNDER: u4,
-                reserved16: u4,
-                ///  TX FIFO overflow (i.e. write-on-full by the system) has occurred. Write 1 to clear. Note that write-on-full does not alter the state or contents of the FIFO in any way, but the data that the system attempted to write is dropped, so if this flag is set, your software has quite likely dropped some data on the floor.
-                TXOVER: u4,
-                reserved24: u4,
-                ///  State machine has stalled on empty TX FIFO during a blocking PULL, or an OUT with autopull enabled. Write 1 to clear.
-                TXSTALL: u4,
-                padding: u4,
-            }),
-            ///  FIFO levels
-            FLEVEL: mmio.Mmio(packed struct(u32) {
-                TX0: u4,
-                RX0: u4,
-                TX1: u4,
-                RX1: u4,
-                TX2: u4,
-                RX2: u4,
-                TX3: u4,
-                RX3: u4,
-            }),
-            ///  Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-            TXF0: u32,
-            ///  Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-            TXF1: u32,
-            ///  Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-            TXF2: u32,
-            ///  Direct write access to the TX FIFO for this state machine. Each write pushes one word to the FIFO. Attempting to write to a full FIFO has no effect on the FIFO state or contents, and sets the sticky FDEBUG_TXOVER error flag for this FIFO.
-            TXF3: u32,
-            ///  Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
-            RXF0: u32,
-            ///  Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
-            RXF1: u32,
-            ///  Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
-            RXF2: u32,
-            ///  Direct read access to the RX FIFO for this state machine. Each read pops one word from the FIFO. Attempting to read from an empty FIFO has no effect on the FIFO state, and sets the sticky FDEBUG_RXUNDER error flag for this FIFO. The data returned to the system on a read from an empty FIFO is undefined.
-            RXF3: u32,
-            ///  State machine IRQ flags register. Write 1 to clear. There are 8 state machine IRQ flags, which can be set, cleared, and waited on by the state machines. There's no fixed association between flags and state machines -- any state machine can use any flag.
-            ///  Any of the 8 flags can be used for timing synchronisation between state machines, using IRQ and WAIT instructions. The lower four of these flags are also routed out to system-level interrupt requests, alongside FIFO status interrupts -- see e.g. IRQ0_INTE.
-            IRQ: mmio.Mmio(packed struct(u32) {
-                IRQ: u8,
-                padding: u24,
-            }),
-            ///  Writing a 1 to each of these bits will forcibly assert the corresponding IRQ. Note this is different to the INTF register: writing here affects PIO internal state. INTF just asserts the processor-facing IRQ signal for testing ISRs, and is not visible to the state machines.
-            IRQ_FORCE: mmio.Mmio(packed struct(u32) {
-                IRQ_FORCE: u8,
-                padding: u24,
-            }),
-            ///  There is a 2-flipflop synchronizer on each GPIO input, which protects PIO logic from metastabilities. This increases input delay, and for fast synchronous IO (e.g. SPI) these synchronizers may need to be bypassed. Each bit in this register corresponds to one GPIO.
-            ///  0 -> input is synchronized (default)
-            ///  1 -> synchronizer is bypassed
-            ///  If in doubt, leave this register as all zeroes.
-            INPUT_SYNC_BYPASS: u32,
-            ///  Read to sample the pad output values PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.
-            DBG_PADOUT: u32,
-            ///  Read to sample the pad output enables (direction) PIO is currently driving to the GPIOs. On RP2040 there are 30 GPIOs, so the two most significant bits are hardwired to 0.
-            DBG_PADOE: u32,
-            ///  The PIO hardware has some free parameters that may vary between chip products.
-            ///  These should be provided in the chip datasheet, but are also exposed here.
-            DBG_CFGINFO: mmio.Mmio(packed struct(u32) {
-                ///  The depth of the state machine TX/RX FIFOs, measured in words.
-                ///  Joining fifos via SHIFTCTRL_FJOIN gives one FIFO with double
-                ///  this depth.
-                FIFO_DEPTH: u6,
-                reserved8: u2,
-                ///  The number of state machines this PIO instance is equipped with.
-                SM_COUNT: u4,
-                reserved16: u4,
-                ///  The size of the instruction memory, measured in units of one instruction
-                IMEM_SIZE: u6,
-                padding: u10,
-            }),
-            ///  Write-only access to instruction memory location 0
-            INSTR_MEM0: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM0: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 1
-            INSTR_MEM1: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM1: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 2
-            INSTR_MEM2: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM2: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 3
-            INSTR_MEM3: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM3: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 4
-            INSTR_MEM4: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM4: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 5
-            INSTR_MEM5: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM5: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 6
-            INSTR_MEM6: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM6: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 7
-            INSTR_MEM7: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM7: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 8
-            INSTR_MEM8: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM8: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 9
-            INSTR_MEM9: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM9: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 10
-            INSTR_MEM10: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM10: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 11
-            INSTR_MEM11: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM11: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 12
-            INSTR_MEM12: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM12: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 13
-            INSTR_MEM13: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM13: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 14
-            INSTR_MEM14: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM14: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 15
-            INSTR_MEM15: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM15: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 16
-            INSTR_MEM16: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM16: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 17
-            INSTR_MEM17: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM17: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 18
-            INSTR_MEM18: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM18: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 19
-            INSTR_MEM19: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM19: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 20
-            INSTR_MEM20: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM20: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 21
-            INSTR_MEM21: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM21: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 22
-            INSTR_MEM22: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM22: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 23
-            INSTR_MEM23: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM23: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 24
-            INSTR_MEM24: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM24: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 25
-            INSTR_MEM25: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM25: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 26
-            INSTR_MEM26: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM26: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 27
-            INSTR_MEM27: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM27: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 28
-            INSTR_MEM28: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM28: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 29
-            INSTR_MEM29: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM29: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 30
-            INSTR_MEM30: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM30: u16,
-                padding: u16,
-            }),
-            ///  Write-only access to instruction memory location 31
-            INSTR_MEM31: mmio.Mmio(packed struct(u32) {
-                INSTR_MEM31: u16,
-                padding: u16,
-            }),
-            ///  Clock divisor register for state machine 0
-            ///  Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-            SM0_CLKDIV: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Fractional part of clock divisor
-                FRAC: u8,
-                ///  Effective frequency is sysclk/(int + frac/256).
-                ///  Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-                INT: u16,
-            }),
-            ///  Execution/behavioural settings for state machine 0
-            SM0_EXECCTRL: mmio.Mmio(packed struct(u32) {
-                ///  Comparison level for the MOV x, STATUS instruction
-                STATUS_N: u4,
-                ///  Comparison used for the MOV x, STATUS instruction.
-                STATUS_SEL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  All-ones if TX FIFO level < N, otherwise all-zeroes
-                        TXLEVEL = 0x0,
-                        ///  All-ones if RX FIFO level < N, otherwise all-zeroes
-                        RXLEVEL = 0x1,
-                    },
-                },
-                reserved7: u2,
-                ///  After reaching wrap_top, execution is wrapped to this address.
-                WRAP_BOTTOM: u5,
-                ///  After reaching this address, execution is wrapped to wrap_bottom.
-                ///  If the instruction is a jump, and the jump condition is true, the jump takes priority.
-                WRAP_TOP: u5,
-                ///  Continuously assert the most recent OUT/SET to the pins
-                OUT_STICKY: u1,
-                ///  If 1, use a bit of OUT data as an auxiliary write enable
-                ///  When used in conjunction with OUT_STICKY, writes with an enable of 0 will
-                ///  deassert the latest pin write. This can create useful masking/override behaviour
-                ///  due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-                INLINE_OUT_EN: u1,
-                ///  Which data bit to use for inline OUT enable
-                OUT_EN_SEL: u5,
-                ///  The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-                JMP_PIN: u5,
-                ///  If 1, side-set data is asserted to pin directions, instead of pin values
-                SIDE_PINDIR: u1,
-                ///  If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-                SIDE_EN: u1,
-                ///  If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
-                EXEC_STALLED: u1,
-            }),
-            ///  Control behaviour of the input/output shift registers for state machine 0
-            SM0_SHIFTCTRL: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-                AUTOPUSH: u1,
-                ///  Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
-                AUTOPULL: u1,
-                ///  1 = shift input shift register to right (data enters from left). 0 = to left.
-                IN_SHIFTDIR: u1,
-                ///  1 = shift out of output shift register to right. 0 = to left.
-                OUT_SHIFTDIR: u1,
-                ///  Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.
-                ///  Write 0 for value of 32.
-                PUSH_THRESH: u5,
-                ///  Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.
-                ///  Write 0 for value of 32.
-                PULL_THRESH: u5,
-                ///  When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.
-                ///  RX FIFO is disabled as a result (always reads as both full and empty).
-                ///  FIFOs are flushed when this bit is changed.
-                FJOIN_TX: u1,
-                ///  When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.
-                ///  TX FIFO is disabled as a result (always reads as both full and empty).
-                ///  FIFOs are flushed when this bit is changed.
-                FJOIN_RX: u1,
-            }),
-            ///  Current instruction address of state machine 0
-            SM0_ADDR: mmio.Mmio(packed struct(u32) {
-                SM0_ADDR: u5,
-                padding: u27,
-            }),
-            ///  Read to see the instruction currently addressed by state machine 0's program counter
-            ///  Write to execute an instruction immediately (including jumps) and then resume execution.
-            SM0_INSTR: mmio.Mmio(packed struct(u32) {
-                SM0_INSTR: u16,
-                padding: u16,
-            }),
-            ///  State machine pin control
-            SM0_PINCTRL: mmio.Mmio(packed struct(u32) {
-                ///  The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
-                OUT_BASE: u5,
-                ///  The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
-                SET_BASE: u5,
-                ///  The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
-                SIDESET_BASE: u5,
-                ///  The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
-                IN_BASE: u5,
-                ///  The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
-                OUT_COUNT: u6,
-                ///  The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-                SET_COUNT: u3,
-                ///  The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
-                SIDESET_COUNT: u3,
-            }),
-            ///  Clock divisor register for state machine 1
-            ///  Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-            SM1_CLKDIV: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Fractional part of clock divisor
-                FRAC: u8,
-                ///  Effective frequency is sysclk/(int + frac/256).
-                ///  Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-                INT: u16,
-            }),
-            ///  Execution/behavioural settings for state machine 1
-            SM1_EXECCTRL: mmio.Mmio(packed struct(u32) {
-                ///  Comparison level for the MOV x, STATUS instruction
-                STATUS_N: u4,
-                ///  Comparison used for the MOV x, STATUS instruction.
-                STATUS_SEL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  All-ones if TX FIFO level < N, otherwise all-zeroes
-                        TXLEVEL = 0x0,
-                        ///  All-ones if RX FIFO level < N, otherwise all-zeroes
-                        RXLEVEL = 0x1,
-                    },
-                },
-                reserved7: u2,
-                ///  After reaching wrap_top, execution is wrapped to this address.
-                WRAP_BOTTOM: u5,
-                ///  After reaching this address, execution is wrapped to wrap_bottom.
-                ///  If the instruction is a jump, and the jump condition is true, the jump takes priority.
-                WRAP_TOP: u5,
-                ///  Continuously assert the most recent OUT/SET to the pins
-                OUT_STICKY: u1,
-                ///  If 1, use a bit of OUT data as an auxiliary write enable
-                ///  When used in conjunction with OUT_STICKY, writes with an enable of 0 will
-                ///  deassert the latest pin write. This can create useful masking/override behaviour
-                ///  due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-                INLINE_OUT_EN: u1,
-                ///  Which data bit to use for inline OUT enable
-                OUT_EN_SEL: u5,
-                ///  The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-                JMP_PIN: u5,
-                ///  If 1, side-set data is asserted to pin directions, instead of pin values
-                SIDE_PINDIR: u1,
-                ///  If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-                SIDE_EN: u1,
-                ///  If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
-                EXEC_STALLED: u1,
-            }),
-            ///  Control behaviour of the input/output shift registers for state machine 1
-            SM1_SHIFTCTRL: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-                AUTOPUSH: u1,
-                ///  Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
-                AUTOPULL: u1,
-                ///  1 = shift input shift register to right (data enters from left). 0 = to left.
-                IN_SHIFTDIR: u1,
-                ///  1 = shift out of output shift register to right. 0 = to left.
-                OUT_SHIFTDIR: u1,
-                ///  Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.
-                ///  Write 0 for value of 32.
-                PUSH_THRESH: u5,
-                ///  Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.
-                ///  Write 0 for value of 32.
-                PULL_THRESH: u5,
-                ///  When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.
-                ///  RX FIFO is disabled as a result (always reads as both full and empty).
-                ///  FIFOs are flushed when this bit is changed.
-                FJOIN_TX: u1,
-                ///  When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.
-                ///  TX FIFO is disabled as a result (always reads as both full and empty).
-                ///  FIFOs are flushed when this bit is changed.
-                FJOIN_RX: u1,
-            }),
-            ///  Current instruction address of state machine 1
-            SM1_ADDR: mmio.Mmio(packed struct(u32) {
-                SM1_ADDR: u5,
-                padding: u27,
-            }),
-            ///  Read to see the instruction currently addressed by state machine 1's program counter
-            ///  Write to execute an instruction immediately (including jumps) and then resume execution.
-            SM1_INSTR: mmio.Mmio(packed struct(u32) {
-                SM1_INSTR: u16,
-                padding: u16,
-            }),
-            ///  State machine pin control
-            SM1_PINCTRL: mmio.Mmio(packed struct(u32) {
-                ///  The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
-                OUT_BASE: u5,
-                ///  The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
-                SET_BASE: u5,
-                ///  The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
-                SIDESET_BASE: u5,
-                ///  The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
-                IN_BASE: u5,
-                ///  The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
-                OUT_COUNT: u6,
-                ///  The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-                SET_COUNT: u3,
-                ///  The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
-                SIDESET_COUNT: u3,
-            }),
-            ///  Clock divisor register for state machine 2
-            ///  Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-            SM2_CLKDIV: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Fractional part of clock divisor
-                FRAC: u8,
-                ///  Effective frequency is sysclk/(int + frac/256).
-                ///  Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-                INT: u16,
-            }),
-            ///  Execution/behavioural settings for state machine 2
-            SM2_EXECCTRL: mmio.Mmio(packed struct(u32) {
-                ///  Comparison level for the MOV x, STATUS instruction
-                STATUS_N: u4,
-                ///  Comparison used for the MOV x, STATUS instruction.
-                STATUS_SEL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  All-ones if TX FIFO level < N, otherwise all-zeroes
-                        TXLEVEL = 0x0,
-                        ///  All-ones if RX FIFO level < N, otherwise all-zeroes
-                        RXLEVEL = 0x1,
-                    },
-                },
-                reserved7: u2,
-                ///  After reaching wrap_top, execution is wrapped to this address.
-                WRAP_BOTTOM: u5,
-                ///  After reaching this address, execution is wrapped to wrap_bottom.
-                ///  If the instruction is a jump, and the jump condition is true, the jump takes priority.
-                WRAP_TOP: u5,
-                ///  Continuously assert the most recent OUT/SET to the pins
-                OUT_STICKY: u1,
-                ///  If 1, use a bit of OUT data as an auxiliary write enable
-                ///  When used in conjunction with OUT_STICKY, writes with an enable of 0 will
-                ///  deassert the latest pin write. This can create useful masking/override behaviour
-                ///  due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-                INLINE_OUT_EN: u1,
-                ///  Which data bit to use for inline OUT enable
-                OUT_EN_SEL: u5,
-                ///  The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-                JMP_PIN: u5,
-                ///  If 1, side-set data is asserted to pin directions, instead of pin values
-                SIDE_PINDIR: u1,
-                ///  If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-                SIDE_EN: u1,
-                ///  If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
-                EXEC_STALLED: u1,
-            }),
-            ///  Control behaviour of the input/output shift registers for state machine 2
-            SM2_SHIFTCTRL: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-                AUTOPUSH: u1,
-                ///  Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
-                AUTOPULL: u1,
-                ///  1 = shift input shift register to right (data enters from left). 0 = to left.
-                IN_SHIFTDIR: u1,
-                ///  1 = shift out of output shift register to right. 0 = to left.
-                OUT_SHIFTDIR: u1,
-                ///  Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.
-                ///  Write 0 for value of 32.
-                PUSH_THRESH: u5,
-                ///  Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.
-                ///  Write 0 for value of 32.
-                PULL_THRESH: u5,
-                ///  When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.
-                ///  RX FIFO is disabled as a result (always reads as both full and empty).
-                ///  FIFOs are flushed when this bit is changed.
-                FJOIN_TX: u1,
-                ///  When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.
-                ///  TX FIFO is disabled as a result (always reads as both full and empty).
-                ///  FIFOs are flushed when this bit is changed.
-                FJOIN_RX: u1,
-            }),
-            ///  Current instruction address of state machine 2
-            SM2_ADDR: mmio.Mmio(packed struct(u32) {
-                SM2_ADDR: u5,
-                padding: u27,
-            }),
-            ///  Read to see the instruction currently addressed by state machine 2's program counter
-            ///  Write to execute an instruction immediately (including jumps) and then resume execution.
-            SM2_INSTR: mmio.Mmio(packed struct(u32) {
-                SM2_INSTR: u16,
-                padding: u16,
-            }),
-            ///  State machine pin control
-            SM2_PINCTRL: mmio.Mmio(packed struct(u32) {
-                ///  The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
-                OUT_BASE: u5,
-                ///  The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
-                SET_BASE: u5,
-                ///  The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
-                SIDESET_BASE: u5,
-                ///  The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
-                IN_BASE: u5,
-                ///  The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
-                OUT_COUNT: u6,
-                ///  The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-                SET_COUNT: u3,
-                ///  The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
-                SIDESET_COUNT: u3,
-            }),
-            ///  Clock divisor register for state machine 3
-            ///  Frequency = clock freq / (CLKDIV_INT + CLKDIV_FRAC / 256)
-            SM3_CLKDIV: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Fractional part of clock divisor
-                FRAC: u8,
-                ///  Effective frequency is sysclk/(int + frac/256).
-                ///  Value of 0 is interpreted as 65536. If INT is 0, FRAC must also be 0.
-                INT: u16,
-            }),
-            ///  Execution/behavioural settings for state machine 3
-            SM3_EXECCTRL: mmio.Mmio(packed struct(u32) {
-                ///  Comparison level for the MOV x, STATUS instruction
-                STATUS_N: u4,
-                ///  Comparison used for the MOV x, STATUS instruction.
-                STATUS_SEL: packed union {
-                    raw: u1,
-                    value: enum(u1) {
-                        ///  All-ones if TX FIFO level < N, otherwise all-zeroes
-                        TXLEVEL = 0x0,
-                        ///  All-ones if RX FIFO level < N, otherwise all-zeroes
-                        RXLEVEL = 0x1,
-                    },
-                },
-                reserved7: u2,
-                ///  After reaching wrap_top, execution is wrapped to this address.
-                WRAP_BOTTOM: u5,
-                ///  After reaching this address, execution is wrapped to wrap_bottom.
-                ///  If the instruction is a jump, and the jump condition is true, the jump takes priority.
-                WRAP_TOP: u5,
-                ///  Continuously assert the most recent OUT/SET to the pins
-                OUT_STICKY: u1,
-                ///  If 1, use a bit of OUT data as an auxiliary write enable
-                ///  When used in conjunction with OUT_STICKY, writes with an enable of 0 will
-                ///  deassert the latest pin write. This can create useful masking/override behaviour
-                ///  due to the priority ordering of state machine pin writes (SM0 < SM1 < ...)
-                INLINE_OUT_EN: u1,
-                ///  Which data bit to use for inline OUT enable
-                OUT_EN_SEL: u5,
-                ///  The GPIO number to use as condition for JMP PIN. Unaffected by input mapping.
-                JMP_PIN: u5,
-                ///  If 1, side-set data is asserted to pin directions, instead of pin values
-                SIDE_PINDIR: u1,
-                ///  If 1, the MSB of the Delay/Side-set instruction field is used as side-set enable, rather than a side-set data bit. This allows instructions to perform side-set optionally, rather than on every instruction, but the maximum possible side-set width is reduced from 5 to 4. Note that the value of PINCTRL_SIDESET_COUNT is inclusive of this enable bit.
-                SIDE_EN: u1,
-                ///  If 1, an instruction written to SMx_INSTR is stalled, and latched by the state machine. Will clear to 0 once this instruction completes.
-                EXEC_STALLED: u1,
-            }),
-            ///  Control behaviour of the input/output shift registers for state machine 3
-            SM3_SHIFTCTRL: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  Push automatically when the input shift register is filled, i.e. on an IN instruction which causes the input shift counter to reach or exceed PUSH_THRESH.
-                AUTOPUSH: u1,
-                ///  Pull automatically when the output shift register is emptied, i.e. on or following an OUT instruction which causes the output shift counter to reach or exceed PULL_THRESH.
-                AUTOPULL: u1,
-                ///  1 = shift input shift register to right (data enters from left). 0 = to left.
-                IN_SHIFTDIR: u1,
-                ///  1 = shift out of output shift register to right. 0 = to left.
-                OUT_SHIFTDIR: u1,
-                ///  Number of bits shifted into ISR before autopush, or conditional push (PUSH IFFULL), will take place.
-                ///  Write 0 for value of 32.
-                PUSH_THRESH: u5,
-                ///  Number of bits shifted out of OSR before autopull, or conditional pull (PULL IFEMPTY), will take place.
-                ///  Write 0 for value of 32.
-                PULL_THRESH: u5,
-                ///  When 1, TX FIFO steals the RX FIFO's storage, and becomes twice as deep.
-                ///  RX FIFO is disabled as a result (always reads as both full and empty).
-                ///  FIFOs are flushed when this bit is changed.
-                FJOIN_TX: u1,
-                ///  When 1, RX FIFO steals the TX FIFO's storage, and becomes twice as deep.
-                ///  TX FIFO is disabled as a result (always reads as both full and empty).
-                ///  FIFOs are flushed when this bit is changed.
-                FJOIN_RX: u1,
-            }),
-            ///  Current instruction address of state machine 3
-            SM3_ADDR: mmio.Mmio(packed struct(u32) {
-                SM3_ADDR: u5,
-                padding: u27,
-            }),
-            ///  Read to see the instruction currently addressed by state machine 3's program counter
-            ///  Write to execute an instruction immediately (including jumps) and then resume execution.
-            SM3_INSTR: mmio.Mmio(packed struct(u32) {
-                SM3_INSTR: u16,
-                padding: u16,
-            }),
-            ///  State machine pin control
-            SM3_PINCTRL: mmio.Mmio(packed struct(u32) {
-                ///  The lowest-numbered pin that will be affected by an OUT PINS, OUT PINDIRS or MOV PINS instruction. The data written to this pin will always be the least-significant bit of the OUT or MOV data.
-                OUT_BASE: u5,
-                ///  The lowest-numbered pin that will be affected by a SET PINS or SET PINDIRS instruction. The data written to this pin is the least-significant bit of the SET data.
-                SET_BASE: u5,
-                ///  The lowest-numbered pin that will be affected by a side-set operation. The MSBs of an instruction's side-set/delay field (up to 5, determined by SIDESET_COUNT) are used for side-set data, with the remaining LSBs used for delay. The least-significant bit of the side-set portion is the bit written to this pin, with more-significant bits written to higher-numbered pins.
-                SIDESET_BASE: u5,
-                ///  The pin which is mapped to the least-significant bit of a state machine's IN data bus. Higher-numbered pins are mapped to consecutively more-significant data bits, with a modulo of 32 applied to pin number.
-                IN_BASE: u5,
-                ///  The number of pins asserted by an OUT PINS, OUT PINDIRS or MOV PINS instruction. In the range 0 to 32 inclusive.
-                OUT_COUNT: u6,
-                ///  The number of pins asserted by a SET. In the range 0 to 5 inclusive.
-                SET_COUNT: u3,
-                ///  The number of MSBs of the Delay/Side-set instruction field which are used for side-set. Inclusive of the enable bit, if present. Minimum of 0 (all delay bits, no side-set) and maximum of 5 (all side-set, no delay).
-                SIDESET_COUNT: u3,
-            }),
-            ///  Raw Interrupts
-            INTR: mmio.Mmio(packed struct(u32) {
-                SM0_RXNEMPTY: u1,
-                SM1_RXNEMPTY: u1,
-                SM2_RXNEMPTY: u1,
-                SM3_RXNEMPTY: u1,
-                SM0_TXNFULL: u1,
-                SM1_TXNFULL: u1,
-                SM2_TXNFULL: u1,
-                SM3_TXNFULL: u1,
-                SM0: u1,
-                SM1: u1,
-                SM2: u1,
-                SM3: u1,
-                padding: u20,
-            }),
-            ///  Interrupt Enable for irq0
-            IRQ0_INTE: mmio.Mmio(packed struct(u32) {
-                SM0_RXNEMPTY: u1,
-                SM1_RXNEMPTY: u1,
-                SM2_RXNEMPTY: u1,
-                SM3_RXNEMPTY: u1,
-                SM0_TXNFULL: u1,
-                SM1_TXNFULL: u1,
-                SM2_TXNFULL: u1,
-                SM3_TXNFULL: u1,
-                SM0: u1,
-                SM1: u1,
-                SM2: u1,
-                SM3: u1,
-                padding: u20,
-            }),
-            ///  Interrupt Force for irq0
-            IRQ0_INTF: mmio.Mmio(packed struct(u32) {
-                SM0_RXNEMPTY: u1,
-                SM1_RXNEMPTY: u1,
-                SM2_RXNEMPTY: u1,
-                SM3_RXNEMPTY: u1,
-                SM0_TXNFULL: u1,
-                SM1_TXNFULL: u1,
-                SM2_TXNFULL: u1,
-                SM3_TXNFULL: u1,
-                SM0: u1,
-                SM1: u1,
-                SM2: u1,
-                SM3: u1,
-                padding: u20,
-            }),
-            ///  Interrupt status after masking & forcing for irq0
-            IRQ0_INTS: mmio.Mmio(packed struct(u32) {
-                SM0_RXNEMPTY: u1,
-                SM1_RXNEMPTY: u1,
-                SM2_RXNEMPTY: u1,
-                SM3_RXNEMPTY: u1,
-                SM0_TXNFULL: u1,
-                SM1_TXNFULL: u1,
-                SM2_TXNFULL: u1,
-                SM3_TXNFULL: u1,
-                SM0: u1,
-                SM1: u1,
-                SM2: u1,
-                SM3: u1,
-                padding: u20,
-            }),
-            ///  Interrupt Enable for irq1
-            IRQ1_INTE: mmio.Mmio(packed struct(u32) {
-                SM0_RXNEMPTY: u1,
-                SM1_RXNEMPTY: u1,
-                SM2_RXNEMPTY: u1,
-                SM3_RXNEMPTY: u1,
-                SM0_TXNFULL: u1,
-                SM1_TXNFULL: u1,
-                SM2_TXNFULL: u1,
-                SM3_TXNFULL: u1,
-                SM0: u1,
-                SM1: u1,
-                SM2: u1,
-                SM3: u1,
-                padding: u20,
-            }),
-            ///  Interrupt Force for irq1
-            IRQ1_INTF: mmio.Mmio(packed struct(u32) {
-                SM0_RXNEMPTY: u1,
-                SM1_RXNEMPTY: u1,
-                SM2_RXNEMPTY: u1,
-                SM3_RXNEMPTY: u1,
-                SM0_TXNFULL: u1,
-                SM1_TXNFULL: u1,
-                SM2_TXNFULL: u1,
-                SM3_TXNFULL: u1,
-                SM0: u1,
-                SM1: u1,
-                SM2: u1,
-                SM3: u1,
-                padding: u20,
-            }),
-            ///  Interrupt status after masking & forcing for irq1
-            IRQ1_INTS: mmio.Mmio(packed struct(u32) {
-                SM0_RXNEMPTY: u1,
-                SM1_RXNEMPTY: u1,
-                SM2_RXNEMPTY: u1,
-                SM3_RXNEMPTY: u1,
-                SM0_TXNFULL: u1,
-                SM1_TXNFULL: u1,
-                SM2_TXNFULL: u1,
-                SM3_TXNFULL: u1,
-                SM0: u1,
-                SM1: u1,
-                SM2: u1,
-                SM3: u1,
-                padding: u20,
-            }),
-        };
-
-        ///  Control and data interface to SAR ADC
-        pub const ADC = extern struct {
-            ///  ADC Control and Status
-            CS: mmio.Mmio(packed struct(u32) {
-                ///  Power on ADC and enable its clock.
-                ///  1 - enabled. 0 - disabled.
-                EN: u1,
-                ///  Power on temperature sensor. 1 - enabled. 0 - disabled.
-                TS_EN: u1,
-                ///  Start a single conversion. Self-clearing. Ignored if start_many is asserted.
-                START_ONCE: u1,
-                ///  Continuously perform conversions whilst this bit is 1. A new conversion will start immediately after the previous finishes.
-                START_MANY: u1,
-                reserved8: u4,
-                ///  1 if the ADC is ready to start a new conversion. Implies any previous conversion has completed.
-                ///  0 whilst conversion in progress.
-                READY: u1,
-                ///  The most recent ADC conversion encountered an error; result is undefined or noisy.
-                ERR: u1,
-                ///  Some past ADC conversion encountered an error. Write 1 to clear.
-                ERR_STICKY: u1,
-                reserved12: u1,
-                ///  Select analog mux input. Updated automatically in round-robin mode.
-                AINSEL: u3,
-                reserved16: u1,
-                ///  Round-robin sampling. 1 bit per channel. Set all bits to 0 to disable.
-                ///  Otherwise, the ADC will cycle through each enabled channel in a round-robin fashion.
-                ///  The first channel to be sampled will be the one currently indicated by AINSEL.
-                ///  AINSEL will be updated after each conversion with the newly-selected channel.
-                RROBIN: u5,
-                padding: u11,
-            }),
-            ///  Result of most recent ADC conversion
-            RESULT: mmio.Mmio(packed struct(u32) {
-                RESULT: u12,
-                padding: u20,
-            }),
-            ///  FIFO control and status
-            FCS: mmio.Mmio(packed struct(u32) {
-                ///  If 1: write result to the FIFO after each conversion.
-                EN: u1,
-                ///  If 1: FIFO results are right-shifted to be one byte in size. Enables DMA to byte buffers.
-                SHIFT: u1,
-                ///  If 1: conversion error bit appears in the FIFO alongside the result
-                ERR: u1,
-                ///  If 1: assert DMA requests when FIFO contains data
-                DREQ_EN: u1,
-                reserved8: u4,
-                EMPTY: u1,
-                FULL: u1,
-                ///  1 if the FIFO has been underflowed. Write 1 to clear.
-                UNDER: u1,
-                ///  1 if the FIFO has been overflowed. Write 1 to clear.
-                OVER: u1,
-                reserved16: u4,
-                ///  The number of conversion results currently waiting in the FIFO
-                LEVEL: u4,
-                reserved24: u4,
-                ///  DREQ/IRQ asserted when level >= threshold
-                THRESH: u4,
-                padding: u4,
-            }),
-            ///  Conversion result FIFO
-            FIFO: mmio.Mmio(packed struct(u32) {
-                VAL: u12,
-                reserved15: u3,
-                ///  1 if this particular sample experienced a conversion error. Remains in the same location if the sample is shifted.
-                ERR: u1,
-                padding: u16,
-            }),
-            ///  Clock divider. If non-zero, CS_START_MANY will start conversions
-            ///  at regular intervals rather than back-to-back.
-            ///  The divider is reset when either of these fields are written.
-            ///  Total period is 1 + INT + FRAC / 256
-            DIV: mmio.Mmio(packed struct(u32) {
-                ///  Fractional part of clock divisor. First-order delta-sigma.
-                FRAC: u8,
-                ///  Integer part of clock divisor.
-                INT: u16,
-                padding: u8,
-            }),
-            ///  Raw Interrupts
-            INTR: mmio.Mmio(packed struct(u32) {
-                ///  Triggered when the sample FIFO reaches a certain level.
-                ///  This level can be programmed via the FCS_THRESH field.
-                FIFO: u1,
-                padding: u31,
-            }),
-            ///  Interrupt Enable
-            INTE: mmio.Mmio(packed struct(u32) {
-                ///  Triggered when the sample FIFO reaches a certain level.
-                ///  This level can be programmed via the FCS_THRESH field.
-                FIFO: u1,
-                padding: u31,
-            }),
-            ///  Interrupt Force
-            INTF: mmio.Mmio(packed struct(u32) {
-                ///  Triggered when the sample FIFO reaches a certain level.
-                ///  This level can be programmed via the FCS_THRESH field.
-                FIFO: u1,
-                padding: u31,
-            }),
-            ///  Interrupt status after masking & forcing
-            INTS: mmio.Mmio(packed struct(u32) {
-                ///  Triggered when the sample FIFO reaches a certain level.
-                ///  This level can be programmed via the FCS_THRESH field.
-                FIFO: u1,
-                padding: u31,
-            }),
-        };
-
-        ///  Simple PWM
-        pub const PWM = extern struct {
-            ///  Control and status register
-            CH0_CSR: mmio.Mmio(packed struct(u32) {
-                ///  Enable the PWM channel.
-                EN: u1,
-                ///  1: Enable phase-correct modulation. 0: Trailing-edge
-                PH_CORRECT: u1,
-                ///  Invert output A
-                A_INV: u1,
-                ///  Invert output B
-                B_INV: u1,
-                DIVMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Free-running counting at rate dictated by fractional divider
-                        div = 0x0,
-                        ///  Fractional divider operation is gated by the PWM B pin.
-                        level = 0x1,
-                        ///  Counter advances with each rising edge of the PWM B pin.
-                        rise = 0x2,
-                        ///  Counter advances with each falling edge of the PWM B pin.
-                        fall = 0x3,
-                    },
-                },
-                ///  Retard the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
-                PH_RET: u1,
-                ///  Advance the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
-                ///  at less than full speed (div_int + div_frac / 16 > 1)
-                PH_ADV: u1,
-                padding: u24,
-            }),
-            ///  INT and FRAC form a fixed-point fractional number.
-            ///  Counting rate is system clock frequency divided by this number.
-            ///  Fractional division uses simple 1st-order sigma-delta.
-            CH0_DIV: mmio.Mmio(packed struct(u32) {
-                FRAC: u4,
-                INT: u8,
-                padding: u20,
-            }),
-            ///  Direct access to the PWM counter
-            CH0_CTR: mmio.Mmio(packed struct(u32) {
-                CH0_CTR: u16,
-                padding: u16,
-            }),
-            ///  Counter compare values
-            CH0_CC: mmio.Mmio(packed struct(u32) {
-                A: u16,
-                B: u16,
-            }),
-            ///  Counter wrap value
-            CH0_TOP: mmio.Mmio(packed struct(u32) {
-                CH0_TOP: u16,
-                padding: u16,
-            }),
-            ///  Control and status register
-            CH1_CSR: mmio.Mmio(packed struct(u32) {
-                ///  Enable the PWM channel.
-                EN: u1,
-                ///  1: Enable phase-correct modulation. 0: Trailing-edge
-                PH_CORRECT: u1,
-                ///  Invert output A
-                A_INV: u1,
-                ///  Invert output B
-                B_INV: u1,
-                DIVMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Free-running counting at rate dictated by fractional divider
-                        div = 0x0,
-                        ///  Fractional divider operation is gated by the PWM B pin.
-                        level = 0x1,
-                        ///  Counter advances with each rising edge of the PWM B pin.
-                        rise = 0x2,
-                        ///  Counter advances with each falling edge of the PWM B pin.
-                        fall = 0x3,
-                    },
-                },
-                ///  Retard the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
-                PH_RET: u1,
-                ///  Advance the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
-                ///  at less than full speed (div_int + div_frac / 16 > 1)
-                PH_ADV: u1,
-                padding: u24,
-            }),
-            ///  INT and FRAC form a fixed-point fractional number.
-            ///  Counting rate is system clock frequency divided by this number.
-            ///  Fractional division uses simple 1st-order sigma-delta.
-            CH1_DIV: mmio.Mmio(packed struct(u32) {
-                FRAC: u4,
-                INT: u8,
-                padding: u20,
-            }),
-            ///  Direct access to the PWM counter
-            CH1_CTR: mmio.Mmio(packed struct(u32) {
-                CH1_CTR: u16,
-                padding: u16,
-            }),
-            ///  Counter compare values
-            CH1_CC: mmio.Mmio(packed struct(u32) {
-                A: u16,
-                B: u16,
-            }),
-            ///  Counter wrap value
-            CH1_TOP: mmio.Mmio(packed struct(u32) {
-                CH1_TOP: u16,
-                padding: u16,
-            }),
-            ///  Control and status register
-            CH2_CSR: mmio.Mmio(packed struct(u32) {
-                ///  Enable the PWM channel.
-                EN: u1,
-                ///  1: Enable phase-correct modulation. 0: Trailing-edge
-                PH_CORRECT: u1,
-                ///  Invert output A
-                A_INV: u1,
-                ///  Invert output B
-                B_INV: u1,
-                DIVMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Free-running counting at rate dictated by fractional divider
-                        div = 0x0,
-                        ///  Fractional divider operation is gated by the PWM B pin.
-                        level = 0x1,
-                        ///  Counter advances with each rising edge of the PWM B pin.
-                        rise = 0x2,
-                        ///  Counter advances with each falling edge of the PWM B pin.
-                        fall = 0x3,
-                    },
-                },
-                ///  Retard the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
-                PH_RET: u1,
-                ///  Advance the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
-                ///  at less than full speed (div_int + div_frac / 16 > 1)
-                PH_ADV: u1,
-                padding: u24,
-            }),
-            ///  INT and FRAC form a fixed-point fractional number.
-            ///  Counting rate is system clock frequency divided by this number.
-            ///  Fractional division uses simple 1st-order sigma-delta.
-            CH2_DIV: mmio.Mmio(packed struct(u32) {
-                FRAC: u4,
-                INT: u8,
-                padding: u20,
-            }),
-            ///  Direct access to the PWM counter
-            CH2_CTR: mmio.Mmio(packed struct(u32) {
-                CH2_CTR: u16,
-                padding: u16,
-            }),
-            ///  Counter compare values
-            CH2_CC: mmio.Mmio(packed struct(u32) {
-                A: u16,
-                B: u16,
-            }),
-            ///  Counter wrap value
-            CH2_TOP: mmio.Mmio(packed struct(u32) {
-                CH2_TOP: u16,
-                padding: u16,
-            }),
-            ///  Control and status register
-            CH3_CSR: mmio.Mmio(packed struct(u32) {
-                ///  Enable the PWM channel.
-                EN: u1,
-                ///  1: Enable phase-correct modulation. 0: Trailing-edge
-                PH_CORRECT: u1,
-                ///  Invert output A
-                A_INV: u1,
-                ///  Invert output B
-                B_INV: u1,
-                DIVMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Free-running counting at rate dictated by fractional divider
-                        div = 0x0,
-                        ///  Fractional divider operation is gated by the PWM B pin.
-                        level = 0x1,
-                        ///  Counter advances with each rising edge of the PWM B pin.
-                        rise = 0x2,
-                        ///  Counter advances with each falling edge of the PWM B pin.
-                        fall = 0x3,
-                    },
-                },
-                ///  Retard the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
-                PH_RET: u1,
-                ///  Advance the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
-                ///  at less than full speed (div_int + div_frac / 16 > 1)
-                PH_ADV: u1,
-                padding: u24,
-            }),
-            ///  INT and FRAC form a fixed-point fractional number.
-            ///  Counting rate is system clock frequency divided by this number.
-            ///  Fractional division uses simple 1st-order sigma-delta.
-            CH3_DIV: mmio.Mmio(packed struct(u32) {
-                FRAC: u4,
-                INT: u8,
-                padding: u20,
-            }),
-            ///  Direct access to the PWM counter
-            CH3_CTR: mmio.Mmio(packed struct(u32) {
-                CH3_CTR: u16,
-                padding: u16,
-            }),
-            ///  Counter compare values
-            CH3_CC: mmio.Mmio(packed struct(u32) {
-                A: u16,
-                B: u16,
-            }),
-            ///  Counter wrap value
-            CH3_TOP: mmio.Mmio(packed struct(u32) {
-                CH3_TOP: u16,
-                padding: u16,
-            }),
-            ///  Control and status register
-            CH4_CSR: mmio.Mmio(packed struct(u32) {
-                ///  Enable the PWM channel.
-                EN: u1,
-                ///  1: Enable phase-correct modulation. 0: Trailing-edge
-                PH_CORRECT: u1,
-                ///  Invert output A
-                A_INV: u1,
-                ///  Invert output B
-                B_INV: u1,
-                DIVMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Free-running counting at rate dictated by fractional divider
-                        div = 0x0,
-                        ///  Fractional divider operation is gated by the PWM B pin.
-                        level = 0x1,
-                        ///  Counter advances with each rising edge of the PWM B pin.
-                        rise = 0x2,
-                        ///  Counter advances with each falling edge of the PWM B pin.
-                        fall = 0x3,
-                    },
-                },
-                ///  Retard the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
-                PH_RET: u1,
-                ///  Advance the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
-                ///  at less than full speed (div_int + div_frac / 16 > 1)
-                PH_ADV: u1,
-                padding: u24,
-            }),
-            ///  INT and FRAC form a fixed-point fractional number.
-            ///  Counting rate is system clock frequency divided by this number.
-            ///  Fractional division uses simple 1st-order sigma-delta.
-            CH4_DIV: mmio.Mmio(packed struct(u32) {
-                FRAC: u4,
-                INT: u8,
-                padding: u20,
-            }),
-            ///  Direct access to the PWM counter
-            CH4_CTR: mmio.Mmio(packed struct(u32) {
-                CH4_CTR: u16,
-                padding: u16,
-            }),
-            ///  Counter compare values
-            CH4_CC: mmio.Mmio(packed struct(u32) {
-                A: u16,
-                B: u16,
-            }),
-            ///  Counter wrap value
-            CH4_TOP: mmio.Mmio(packed struct(u32) {
-                CH4_TOP: u16,
-                padding: u16,
-            }),
-            ///  Control and status register
-            CH5_CSR: mmio.Mmio(packed struct(u32) {
-                ///  Enable the PWM channel.
-                EN: u1,
-                ///  1: Enable phase-correct modulation. 0: Trailing-edge
-                PH_CORRECT: u1,
-                ///  Invert output A
-                A_INV: u1,
-                ///  Invert output B
-                B_INV: u1,
-                DIVMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Free-running counting at rate dictated by fractional divider
-                        div = 0x0,
-                        ///  Fractional divider operation is gated by the PWM B pin.
-                        level = 0x1,
-                        ///  Counter advances with each rising edge of the PWM B pin.
-                        rise = 0x2,
-                        ///  Counter advances with each falling edge of the PWM B pin.
-                        fall = 0x3,
-                    },
-                },
-                ///  Retard the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
-                PH_RET: u1,
-                ///  Advance the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
-                ///  at less than full speed (div_int + div_frac / 16 > 1)
-                PH_ADV: u1,
-                padding: u24,
-            }),
-            ///  INT and FRAC form a fixed-point fractional number.
-            ///  Counting rate is system clock frequency divided by this number.
-            ///  Fractional division uses simple 1st-order sigma-delta.
-            CH5_DIV: mmio.Mmio(packed struct(u32) {
-                FRAC: u4,
-                INT: u8,
-                padding: u20,
-            }),
-            ///  Direct access to the PWM counter
-            CH5_CTR: mmio.Mmio(packed struct(u32) {
-                CH5_CTR: u16,
-                padding: u16,
-            }),
-            ///  Counter compare values
-            CH5_CC: mmio.Mmio(packed struct(u32) {
-                A: u16,
-                B: u16,
-            }),
-            ///  Counter wrap value
-            CH5_TOP: mmio.Mmio(packed struct(u32) {
-                CH5_TOP: u16,
-                padding: u16,
-            }),
-            ///  Control and status register
-            CH6_CSR: mmio.Mmio(packed struct(u32) {
-                ///  Enable the PWM channel.
-                EN: u1,
-                ///  1: Enable phase-correct modulation. 0: Trailing-edge
-                PH_CORRECT: u1,
-                ///  Invert output A
-                A_INV: u1,
-                ///  Invert output B
-                B_INV: u1,
-                DIVMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Free-running counting at rate dictated by fractional divider
-                        div = 0x0,
-                        ///  Fractional divider operation is gated by the PWM B pin.
-                        level = 0x1,
-                        ///  Counter advances with each rising edge of the PWM B pin.
-                        rise = 0x2,
-                        ///  Counter advances with each falling edge of the PWM B pin.
-                        fall = 0x3,
-                    },
-                },
-                ///  Retard the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
-                PH_RET: u1,
-                ///  Advance the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
-                ///  at less than full speed (div_int + div_frac / 16 > 1)
-                PH_ADV: u1,
-                padding: u24,
-            }),
-            ///  INT and FRAC form a fixed-point fractional number.
-            ///  Counting rate is system clock frequency divided by this number.
-            ///  Fractional division uses simple 1st-order sigma-delta.
-            CH6_DIV: mmio.Mmio(packed struct(u32) {
-                FRAC: u4,
-                INT: u8,
-                padding: u20,
-            }),
-            ///  Direct access to the PWM counter
-            CH6_CTR: mmio.Mmio(packed struct(u32) {
-                CH6_CTR: u16,
-                padding: u16,
-            }),
-            ///  Counter compare values
-            CH6_CC: mmio.Mmio(packed struct(u32) {
-                A: u16,
-                B: u16,
-            }),
-            ///  Counter wrap value
-            CH6_TOP: mmio.Mmio(packed struct(u32) {
-                CH6_TOP: u16,
-                padding: u16,
-            }),
-            ///  Control and status register
-            CH7_CSR: mmio.Mmio(packed struct(u32) {
-                ///  Enable the PWM channel.
-                EN: u1,
-                ///  1: Enable phase-correct modulation. 0: Trailing-edge
-                PH_CORRECT: u1,
-                ///  Invert output A
-                A_INV: u1,
-                ///  Invert output B
-                B_INV: u1,
-                DIVMODE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        ///  Free-running counting at rate dictated by fractional divider
-                        div = 0x0,
-                        ///  Fractional divider operation is gated by the PWM B pin.
-                        level = 0x1,
-                        ///  Counter advances with each rising edge of the PWM B pin.
-                        rise = 0x2,
-                        ///  Counter advances with each falling edge of the PWM B pin.
-                        fall = 0x3,
-                    },
-                },
-                ///  Retard the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running.
-                PH_RET: u1,
-                ///  Advance the phase of the counter by 1 count, while it is running.
-                ///  Self-clearing. Write a 1, and poll until low. Counter must be running
-                ///  at less than full speed (div_int + div_frac / 16 > 1)
-                PH_ADV: u1,
-                padding: u24,
-            }),
-            ///  INT and FRAC form a fixed-point fractional number.
-            ///  Counting rate is system clock frequency divided by this number.
-            ///  Fractional division uses simple 1st-order sigma-delta.
-            CH7_DIV: mmio.Mmio(packed struct(u32) {
-                FRAC: u4,
-                INT: u8,
-                padding: u20,
-            }),
-            ///  Direct access to the PWM counter
-            CH7_CTR: mmio.Mmio(packed struct(u32) {
-                CH7_CTR: u16,
-                padding: u16,
-            }),
-            ///  Counter compare values
-            CH7_CC: mmio.Mmio(packed struct(u32) {
-                A: u16,
-                B: u16,
-            }),
-            ///  Counter wrap value
-            CH7_TOP: mmio.Mmio(packed struct(u32) {
-                CH7_TOP: u16,
-                padding: u16,
-            }),
-            ///  This register aliases the CSR_EN bits for all channels.
-            ///  Writing to this register allows multiple channels to be enabled
-            ///  or disabled simultaneously, so they can run in perfect sync.
-            ///  For each channel, there is only one physical EN register bit,
-            ///  which can be accessed through here or CHx_CSR.
-            EN: mmio.Mmio(packed struct(u32) {
-                CH0: u1,
-                CH1: u1,
-                CH2: u1,
-                CH3: u1,
-                CH4: u1,
-                CH5: u1,
-                CH6: u1,
-                CH7: u1,
-                padding: u24,
-            }),
-            ///  Raw Interrupts
-            INTR: mmio.Mmio(packed struct(u32) {
-                CH0: u1,
-                CH1: u1,
-                CH2: u1,
-                CH3: u1,
-                CH4: u1,
-                CH5: u1,
-                CH6: u1,
-                CH7: u1,
-                padding: u24,
-            }),
-            ///  Interrupt Enable
-            INTE: mmio.Mmio(packed struct(u32) {
-                CH0: u1,
-                CH1: u1,
-                CH2: u1,
-                CH3: u1,
-                CH4: u1,
-                CH5: u1,
-                CH6: u1,
-                CH7: u1,
-                padding: u24,
-            }),
-            ///  Interrupt Force
-            INTF: mmio.Mmio(packed struct(u32) {
-                CH0: u1,
-                CH1: u1,
-                CH2: u1,
-                CH3: u1,
-                CH4: u1,
-                CH5: u1,
-                CH6: u1,
-                CH7: u1,
-                padding: u24,
-            }),
-            ///  Interrupt status after masking & forcing
-            INTS: mmio.Mmio(packed struct(u32) {
-                CH0: u1,
-                CH1: u1,
-                CH2: u1,
-                CH3: u1,
-                CH4: u1,
-                CH5: u1,
-                CH6: u1,
-                CH7: u1,
-                padding: u24,
-            }),
-        };
-
-        ///  Controls time and alarms
-        ///  time is a 64 bit value indicating the time in usec since power-on
-        ///  timeh is the top 32 bits of time & timel is the bottom 32 bits
-        ///  to change time write to timelw before timehw
-        ///  to read time read from timelr before timehr
-        ///  An alarm is set by setting alarm_enable and writing to the corresponding alarm register
-        ///  When an alarm is pending, the corresponding alarm_running signal will be high
-        ///  An alarm can be cancelled before it has finished by clearing the alarm_enable
-        ///  When an alarm fires, the corresponding alarm_irq is set and alarm_running is cleared
-        ///  To clear the interrupt write a 1 to the corresponding alarm_irq
-        pub const TIMER = extern struct {
-            ///  Write to bits 63:32 of time
-            ///  always write timelw before timehw
-            TIMEHW: u32,
-            ///  Write to bits 31:0 of time
-            ///  writes do not get copied to time until timehw is written
-            TIMELW: u32,
-            ///  Read from bits 63:32 of time
-            ///  always read timelr before timehr
-            TIMEHR: u32,
-            ///  Read from bits 31:0 of time
-            TIMELR: u32,
-            ///  Arm alarm 0, and configure the time it will fire.
-            ///  Once armed, the alarm fires when TIMER_ALARM0 == TIMELR.
-            ///  The alarm will disarm itself once it fires, and can
-            ///  be disarmed early using the ARMED status register.
-            ALARM0: u32,
-            ///  Arm alarm 1, and configure the time it will fire.
-            ///  Once armed, the alarm fires when TIMER_ALARM1 == TIMELR.
-            ///  The alarm will disarm itself once it fires, and can
-            ///  be disarmed early using the ARMED status register.
-            ALARM1: u32,
-            ///  Arm alarm 2, and configure the time it will fire.
-            ///  Once armed, the alarm fires when TIMER_ALARM2 == TIMELR.
-            ///  The alarm will disarm itself once it fires, and can
-            ///  be disarmed early using the ARMED status register.
-            ALARM2: u32,
-            ///  Arm alarm 3, and configure the time it will fire.
-            ///  Once armed, the alarm fires when TIMER_ALARM3 == TIMELR.
-            ///  The alarm will disarm itself once it fires, and can
-            ///  be disarmed early using the ARMED status register.
-            ALARM3: u32,
-            ///  Indicates the armed/disarmed status of each alarm.
-            ///  A write to the corresponding ALARMx register arms the alarm.
-            ///  Alarms automatically disarm upon firing, but writing ones here
-            ///  will disarm immediately without waiting to fire.
-            ARMED: mmio.Mmio(packed struct(u32) {
-                ARMED: u4,
-                padding: u28,
-            }),
-            ///  Raw read from bits 63:32 of time (no side effects)
-            TIMERAWH: u32,
-            ///  Raw read from bits 31:0 of time (no side effects)
-            TIMERAWL: u32,
-            ///  Set bits high to enable pause when the corresponding debug ports are active
-            DBGPAUSE: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Pause when processor 0 is in debug mode
-                DBG0: u1,
-                ///  Pause when processor 1 is in debug mode
-                DBG1: u1,
-                padding: u29,
-            }),
-            ///  Set high to pause the timer
-            PAUSE: mmio.Mmio(packed struct(u32) {
-                PAUSE: u1,
-                padding: u31,
-            }),
-            ///  Raw Interrupts
-            INTR: mmio.Mmio(packed struct(u32) {
-                ALARM_0: u1,
-                ALARM_1: u1,
-                ALARM_2: u1,
-                ALARM_3: u1,
-                padding: u28,
-            }),
-            ///  Interrupt Enable
-            INTE: mmio.Mmio(packed struct(u32) {
-                ALARM_0: u1,
-                ALARM_1: u1,
-                ALARM_2: u1,
-                ALARM_3: u1,
-                padding: u28,
-            }),
-            ///  Interrupt Force
-            INTF: mmio.Mmio(packed struct(u32) {
-                ALARM_0: u1,
-                ALARM_1: u1,
-                ALARM_2: u1,
-                ALARM_3: u1,
-                padding: u28,
-            }),
-            ///  Interrupt status after masking & forcing
-            INTS: mmio.Mmio(packed struct(u32) {
-                ALARM_0: u1,
-                ALARM_1: u1,
-                ALARM_2: u1,
-                ALARM_3: u1,
-                padding: u28,
-            }),
-        };
-
-        pub const WATCHDOG = extern struct {
-            ///  Watchdog control
-            ///  The rst_wdsel register determines which subsystems are reset when the watchdog is triggered.
-            ///  The watchdog can be triggered in software.
-            CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Indicates the number of ticks / 2 (see errata RP2040-E1) before a watchdog reset will be triggered
-                TIME: u24,
-                ///  Pause the watchdog timer when JTAG is accessing the bus fabric
-                PAUSE_JTAG: u1,
-                ///  Pause the watchdog timer when processor 0 is in debug mode
-                PAUSE_DBG0: u1,
-                ///  Pause the watchdog timer when processor 1 is in debug mode
-                PAUSE_DBG1: u1,
-                reserved30: u3,
-                ///  When not enabled the watchdog timer is paused
-                ENABLE: u1,
-                ///  Trigger a watchdog reset
-                TRIGGER: u1,
-            }),
-            ///  Load the watchdog timer. The maximum setting is 0xffffff which corresponds to 0xffffff / 2 ticks before triggering a watchdog reset (see errata RP2040-E1).
-            LOAD: mmio.Mmio(packed struct(u32) {
-                LOAD: u24,
-                padding: u8,
-            }),
-            ///  Logs the reason for the last reset. Both bits are zero for the case of a hardware reset.
-            REASON: mmio.Mmio(packed struct(u32) {
-                TIMER: u1,
-                FORCE: u1,
-                padding: u30,
-            }),
-            ///  Scratch register. Information persists through soft reset of the chip.
-            SCRATCH0: u32,
-            ///  Scratch register. Information persists through soft reset of the chip.
-            SCRATCH1: u32,
-            ///  Scratch register. Information persists through soft reset of the chip.
-            SCRATCH2: u32,
-            ///  Scratch register. Information persists through soft reset of the chip.
-            SCRATCH3: u32,
-            ///  Scratch register. Information persists through soft reset of the chip.
-            SCRATCH4: u32,
-            ///  Scratch register. Information persists through soft reset of the chip.
-            SCRATCH5: u32,
-            ///  Scratch register. Information persists through soft reset of the chip.
-            SCRATCH6: u32,
-            ///  Scratch register. Information persists through soft reset of the chip.
-            SCRATCH7: u32,
-            ///  Controls the tick generator
-            TICK: mmio.Mmio(packed struct(u32) {
-                ///  Total number of clk_tick cycles before the next tick.
-                CYCLES: u9,
-                ///  start / stop tick generation
-                ENABLE: u1,
-                ///  Is the tick generator running?
-                RUNNING: u1,
-                ///  Count down timer: the remaining number clk_tick cycles before the next tick is generated.
-                COUNT: u9,
-                padding: u12,
-            }),
-        };
-
-        ///  Register block to control RTC
-        pub const RTC = extern struct {
-            ///  Divider minus 1 for the 1 second counter. Safe to change the value when RTC is not enabled.
-            CLKDIV_M1: mmio.Mmio(packed struct(u32) {
-                CLKDIV_M1: u16,
-                padding: u16,
-            }),
-            ///  RTC setup register 0
-            SETUP_0: mmio.Mmio(packed struct(u32) {
-                ///  Day of the month (1..31)
-                DAY: u5,
-                reserved8: u3,
-                ///  Month (1..12)
-                MONTH: u4,
-                ///  Year
-                YEAR: u12,
-                padding: u8,
-            }),
-            ///  RTC setup register 1
-            SETUP_1: mmio.Mmio(packed struct(u32) {
-                ///  Seconds
-                SEC: u6,
-                reserved8: u2,
-                ///  Minutes
-                MIN: u6,
-                reserved16: u2,
-                ///  Hours
-                HOUR: u5,
-                reserved24: u3,
-                ///  Day of the week: 1-Monday...0-Sunday ISO 8601 mod 7
-                DOTW: u3,
-                padding: u5,
-            }),
-            ///  RTC Control and status
-            CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Enable RTC
-                RTC_ENABLE: u1,
-                ///  RTC enabled (running)
-                RTC_ACTIVE: u1,
-                reserved4: u2,
-                ///  Load RTC
-                LOAD: u1,
-                reserved8: u3,
-                ///  If set, leapyear is forced off.
-                ///  Useful for years divisible by 100 but not by 400
-                FORCE_NOTLEAPYEAR: u1,
-                padding: u23,
-            }),
-            ///  Interrupt setup register 0
-            IRQ_SETUP_0: mmio.Mmio(packed struct(u32) {
-                ///  Day of the month (1..31)
-                DAY: u5,
-                reserved8: u3,
-                ///  Month (1..12)
-                MONTH: u4,
-                ///  Year
-                YEAR: u12,
-                ///  Enable day matching
-                DAY_ENA: u1,
-                ///  Enable month matching
-                MONTH_ENA: u1,
-                ///  Enable year matching
-                YEAR_ENA: u1,
-                reserved28: u1,
-                ///  Global match enable. Don't change any other value while this one is enabled
-                MATCH_ENA: u1,
-                MATCH_ACTIVE: u1,
-                padding: u2,
-            }),
-            ///  Interrupt setup register 1
-            IRQ_SETUP_1: mmio.Mmio(packed struct(u32) {
-                ///  Seconds
-                SEC: u6,
-                reserved8: u2,
-                ///  Minutes
-                MIN: u6,
-                reserved16: u2,
-                ///  Hours
-                HOUR: u5,
-                reserved24: u3,
-                ///  Day of the week
-                DOTW: u3,
-                reserved28: u1,
-                ///  Enable second matching
-                SEC_ENA: u1,
-                ///  Enable minute matching
-                MIN_ENA: u1,
-                ///  Enable hour matching
-                HOUR_ENA: u1,
-                ///  Enable day of the week matching
-                DOTW_ENA: u1,
-            }),
-            ///  RTC register 1.
-            RTC_1: mmio.Mmio(packed struct(u32) {
-                ///  Day of the month (1..31)
-                DAY: u5,
-                reserved8: u3,
-                ///  Month (1..12)
-                MONTH: u4,
-                ///  Year
-                YEAR: u12,
-                padding: u8,
-            }),
-            ///  RTC register 0
-            ///  Read this before RTC 1!
-            RTC_0: mmio.Mmio(packed struct(u32) {
-                ///  Seconds
-                SEC: u6,
-                reserved8: u2,
-                ///  Minutes
-                MIN: u6,
-                reserved16: u2,
-                ///  Hours
-                HOUR: u5,
-                reserved24: u3,
-                ///  Day of the week
-                DOTW: u3,
-                padding: u5,
-            }),
-            ///  Raw Interrupts
-            INTR: mmio.Mmio(packed struct(u32) {
-                RTC: u1,
-                padding: u31,
-            }),
-            ///  Interrupt Enable
-            INTE: mmio.Mmio(packed struct(u32) {
-                RTC: u1,
-                padding: u31,
-            }),
-            ///  Interrupt Force
-            INTF: mmio.Mmio(packed struct(u32) {
-                RTC: u1,
-                padding: u31,
-            }),
-            ///  Interrupt status after masking & forcing
-            INTS: mmio.Mmio(packed struct(u32) {
-                RTC: u1,
-                padding: u31,
-            }),
-        };
-
-        pub const ROSC = extern struct {
-            ///  Ring Oscillator control
-            CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Controls the number of delay stages in the ROSC ring
-                ///  LOW uses stages 0 to 7
-                ///  MEDIUM uses stages 0 to 5
-                ///  HIGH uses stages 0 to 3
-                ///  TOOHIGH uses stages 0 to 1 and should not be used because its frequency exceeds design specifications
-                ///  The clock output will not glitch when changing the range up one step at a time
-                ///  The clock output will glitch when changing the range down
-                ///  Note: the values here are gray coded which is why HIGH comes before TOOHIGH
-                FREQ_RANGE: packed union {
-                    raw: u12,
-                    value: enum(u12) {
-                        LOW = 0xfa4,
-                        MEDIUM = 0xfa5,
-                        HIGH = 0xfa7,
-                        TOOHIGH = 0xfa6,
-                        _,
-                    },
-                },
-                ///  On power-up this field is initialised to ENABLE
-                ///  The system clock must be switched to another source before setting this field to DISABLE otherwise the chip will lock up
-                ///  The 12-bit code is intended to give some protection against accidental writes. An invalid setting will enable the oscillator.
-                ENABLE: packed union {
-                    raw: u12,
-                    value: enum(u12) {
-                        DISABLE = 0xd1e,
-                        ENABLE = 0xfab,
-                        _,
-                    },
-                },
-                padding: u8,
-            }),
-            ///  The FREQA & FREQB registers control the frequency by controlling the drive strength of each stage
-            ///  The drive strength has 4 levels determined by the number of bits set
-            ///  Increasing the number of bits set increases the drive strength and increases the oscillation frequency
-            ///  0 bits set is the default drive strength
-            ///  1 bit set doubles the drive strength
-            ///  2 bits set triples drive strength
-            ///  3 bits set quadruples drive strength
-            FREQA: mmio.Mmio(packed struct(u32) {
-                ///  Stage 0 drive strength
-                DS0: u3,
-                reserved4: u1,
-                ///  Stage 1 drive strength
-                DS1: u3,
-                reserved8: u1,
-                ///  Stage 2 drive strength
-                DS2: u3,
-                reserved12: u1,
-                ///  Stage 3 drive strength
-                DS3: u3,
-                reserved16: u1,
-                ///  Set to 0x9696 to apply the settings
-                ///  Any other value in this field will set all drive strengths to 0
-                PASSWD: packed union {
-                    raw: u16,
-                    value: enum(u16) {
-                        PASS = 0x9696,
-                        _,
-                    },
-                },
-            }),
-            ///  For a detailed description see freqa register
-            FREQB: mmio.Mmio(packed struct(u32) {
-                ///  Stage 4 drive strength
-                DS4: u3,
-                reserved4: u1,
-                ///  Stage 5 drive strength
-                DS5: u3,
-                reserved8: u1,
-                ///  Stage 6 drive strength
-                DS6: u3,
-                reserved12: u1,
-                ///  Stage 7 drive strength
-                DS7: u3,
-                reserved16: u1,
-                ///  Set to 0x9696 to apply the settings
-                ///  Any other value in this field will set all drive strengths to 0
-                PASSWD: packed union {
-                    raw: u16,
-                    value: enum(u16) {
-                        PASS = 0x9696,
-                        _,
-                    },
-                },
-            }),
-            ///  Ring Oscillator pause control
-            ///  This is used to save power by pausing the ROSC
-            ///  On power-up this field is initialised to WAKE
-            ///  An invalid write will also select WAKE
-            ///  Warning: setup the irq before selecting dormant mode
-            DORMANT: u32,
-            ///  Controls the output divider
-            DIV: mmio.Mmio(packed struct(u32) {
-                ///  set to 0xaa0 + div where
-                ///  div = 0 divides by 32
-                ///  div = 1-31 divides by div
-                ///  any other value sets div=31
-                ///  this register resets to div=16
-                DIV: packed union {
-                    raw: u12,
-                    value: enum(u12) {
-                        PASS = 0xaa0,
-                        _,
-                    },
-                },
-                padding: u20,
-            }),
-            ///  Controls the phase shifted output
-            PHASE: mmio.Mmio(packed struct(u32) {
-                ///  phase shift the phase-shifted output by SHIFT input clocks
-                ///  this can be changed on-the-fly
-                ///  must be set to 0 before setting div=1
-                SHIFT: u2,
-                ///  invert the phase-shifted output
-                ///  this is ignored when div=1
-                FLIP: u1,
-                ///  enable the phase-shifted output
-                ///  this can be changed on-the-fly
-                ENABLE: u1,
-                ///  set to 0xaa
-                ///  any other value enables the output with shift=0
-                PASSWD: u8,
-                padding: u20,
-            }),
-            ///  Ring Oscillator Status
-            STATUS: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Oscillator is enabled but not necessarily running and stable
-                ///  this resets to 0 but transitions to 1 during chip startup
-                ENABLED: u1,
-                reserved16: u3,
-                ///  post-divider is running
-                ///  this resets to 0 but transitions to 1 during chip startup
-                DIV_RUNNING: u1,
-                reserved24: u7,
-                ///  An invalid value has been written to CTRL_ENABLE or CTRL_FREQ_RANGE or FREQA or FREQB or DIV or PHASE or DORMANT
-                BADWRITE: u1,
-                reserved31: u6,
-                ///  Oscillator is running and stable
-                STABLE: u1,
-            }),
-            ///  This just reads the state of the oscillator output so randomness is compromised if the ring oscillator is stopped or run at a harmonic of the bus frequency
-            RANDOMBIT: mmio.Mmio(packed struct(u32) {
-                RANDOMBIT: u1,
-                padding: u31,
-            }),
-            ///  A down counter running at the ROSC frequency which counts to zero and stops.
-            ///  To start the counter write a non-zero value.
-            ///  Can be used for short software pauses when setting up time sensitive hardware.
-            COUNT: mmio.Mmio(packed struct(u32) {
-                COUNT: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  control and status for on-chip voltage regulator and chip level reset subsystem
-        pub const VREG_AND_CHIP_RESET = extern struct {
-            ///  Voltage regulator control and status
-            VREG: mmio.Mmio(packed struct(u32) {
-                ///  enable
-                ///  0=not enabled, 1=enabled
-                EN: u1,
-                ///  high impedance mode select
-                ///  0=not in high impedance mode, 1=in high impedance mode
-                HIZ: u1,
-                reserved4: u2,
-                ///  output voltage select
-                ///  0000 to 0101 - 0.80V
-                ///  0110 - 0.85V
-                ///  0111 - 0.90V
-                ///  1000 - 0.95V
-                ///  1001 - 1.00V
-                ///  1010 - 1.05V
-                ///  1011 - 1.10V (default)
-                ///  1100 - 1.15V
-                ///  1101 - 1.20V
-                ///  1110 - 1.25V
-                ///  1111 - 1.30V
-                VSEL: u4,
-                reserved12: u4,
-                ///  regulation status
-                ///  0=not in regulation, 1=in regulation
-                ROK: u1,
-                padding: u19,
-            }),
-            ///  brown-out detection control
-            BOD: mmio.Mmio(packed struct(u32) {
-                ///  enable
-                ///  0=not enabled, 1=enabled
-                EN: u1,
-                reserved4: u3,
-                ///  threshold select
-                ///  0000 - 0.473V
-                ///  0001 - 0.516V
-                ///  0010 - 0.559V
-                ///  0011 - 0.602V
-                ///  0100 - 0.645V
-                ///  0101 - 0.688V
-                ///  0110 - 0.731V
-                ///  0111 - 0.774V
-                ///  1000 - 0.817V
-                ///  1001 - 0.860V (default)
-                ///  1010 - 0.903V
-                ///  1011 - 0.946V
-                ///  1100 - 0.989V
-                ///  1101 - 1.032V
-                ///  1110 - 1.075V
-                ///  1111 - 1.118V
-                VSEL: u4,
-                padding: u24,
-            }),
-            ///  Chip reset control and status
-            CHIP_RESET: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Last reset was from the power-on reset or brown-out detection blocks
-                HAD_POR: u1,
-                reserved16: u7,
-                ///  Last reset was from the RUN pin
-                HAD_RUN: u1,
-                reserved20: u3,
-                ///  Last reset was from the debug port
-                HAD_PSM_RESTART: u1,
-                reserved24: u3,
-                ///  This is set by psm_restart from the debugger.
-                ///  Its purpose is to branch bootcode to a safe mode when the debugger has issued a psm_restart in order to recover from a boot lock-up.
-                ///  In the safe mode the debugger can repair the boot code, clear this flag then reboot the processor.
-                PSM_RESTART_FLAG: u1,
-                padding: u7,
-            }),
-        };
-
-        ///  Testbench manager. Allows the programmer to know what platform their software is running on.
-        pub const TBMAN = extern struct {
-            ///  Indicates the type of platform in use
-            PLATFORM: mmio.Mmio(packed struct(u32) {
-                ///  Indicates the platform is an ASIC
-                ASIC: u1,
-                ///  Indicates the platform is an FPGA
-                FPGA: u1,
-                padding: u30,
-            }),
-        };
-
-        ///  DMA with separate read and write masters
-        pub const DMA = extern struct {
-            ///  DMA Channel 0 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH0_READ_ADDR: u32,
-            ///  DMA Channel 0 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH0_WRITE_ADDR: u32,
-            ///  DMA Channel 0 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH0_TRANS_COUNT: u32,
-            ///  DMA Channel 0 Control and Status
-            CH0_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 0 CTRL register
-            CH0_AL1_CTRL: u32,
-            ///  Alias for channel 0 READ_ADDR register
-            CH0_AL1_READ_ADDR: u32,
-            ///  Alias for channel 0 WRITE_ADDR register
-            CH0_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 0 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH0_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 0 CTRL register
-            CH0_AL2_CTRL: u32,
-            ///  Alias for channel 0 TRANS_COUNT register
-            CH0_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 0 READ_ADDR register
-            CH0_AL2_READ_ADDR: u32,
-            ///  Alias for channel 0 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH0_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 0 CTRL register
-            CH0_AL3_CTRL: u32,
-            ///  Alias for channel 0 WRITE_ADDR register
-            CH0_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 0 TRANS_COUNT register
-            CH0_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 0 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH0_AL3_READ_ADDR_TRIG: u32,
-            ///  DMA Channel 1 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH1_READ_ADDR: u32,
-            ///  DMA Channel 1 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH1_WRITE_ADDR: u32,
-            ///  DMA Channel 1 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH1_TRANS_COUNT: u32,
-            ///  DMA Channel 1 Control and Status
-            CH1_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 1 CTRL register
-            CH1_AL1_CTRL: u32,
-            ///  Alias for channel 1 READ_ADDR register
-            CH1_AL1_READ_ADDR: u32,
-            ///  Alias for channel 1 WRITE_ADDR register
-            CH1_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 1 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH1_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 1 CTRL register
-            CH1_AL2_CTRL: u32,
-            ///  Alias for channel 1 TRANS_COUNT register
-            CH1_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 1 READ_ADDR register
-            CH1_AL2_READ_ADDR: u32,
-            ///  Alias for channel 1 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH1_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 1 CTRL register
-            CH1_AL3_CTRL: u32,
-            ///  Alias for channel 1 WRITE_ADDR register
-            CH1_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 1 TRANS_COUNT register
-            CH1_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 1 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH1_AL3_READ_ADDR_TRIG: u32,
-            ///  DMA Channel 2 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH2_READ_ADDR: u32,
-            ///  DMA Channel 2 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH2_WRITE_ADDR: u32,
-            ///  DMA Channel 2 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH2_TRANS_COUNT: u32,
-            ///  DMA Channel 2 Control and Status
-            CH2_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 2 CTRL register
-            CH2_AL1_CTRL: u32,
-            ///  Alias for channel 2 READ_ADDR register
-            CH2_AL1_READ_ADDR: u32,
-            ///  Alias for channel 2 WRITE_ADDR register
-            CH2_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 2 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH2_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 2 CTRL register
-            CH2_AL2_CTRL: u32,
-            ///  Alias for channel 2 TRANS_COUNT register
-            CH2_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 2 READ_ADDR register
-            CH2_AL2_READ_ADDR: u32,
-            ///  Alias for channel 2 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH2_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 2 CTRL register
-            CH2_AL3_CTRL: u32,
-            ///  Alias for channel 2 WRITE_ADDR register
-            CH2_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 2 TRANS_COUNT register
-            CH2_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 2 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH2_AL3_READ_ADDR_TRIG: u32,
-            ///  DMA Channel 3 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH3_READ_ADDR: u32,
-            ///  DMA Channel 3 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH3_WRITE_ADDR: u32,
-            ///  DMA Channel 3 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH3_TRANS_COUNT: u32,
-            ///  DMA Channel 3 Control and Status
-            CH3_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 3 CTRL register
-            CH3_AL1_CTRL: u32,
-            ///  Alias for channel 3 READ_ADDR register
-            CH3_AL1_READ_ADDR: u32,
-            ///  Alias for channel 3 WRITE_ADDR register
-            CH3_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 3 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH3_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 3 CTRL register
-            CH3_AL2_CTRL: u32,
-            ///  Alias for channel 3 TRANS_COUNT register
-            CH3_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 3 READ_ADDR register
-            CH3_AL2_READ_ADDR: u32,
-            ///  Alias for channel 3 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH3_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 3 CTRL register
-            CH3_AL3_CTRL: u32,
-            ///  Alias for channel 3 WRITE_ADDR register
-            CH3_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 3 TRANS_COUNT register
-            CH3_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 3 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH3_AL3_READ_ADDR_TRIG: u32,
-            ///  DMA Channel 4 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH4_READ_ADDR: u32,
-            ///  DMA Channel 4 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH4_WRITE_ADDR: u32,
-            ///  DMA Channel 4 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH4_TRANS_COUNT: u32,
-            ///  DMA Channel 4 Control and Status
-            CH4_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 4 CTRL register
-            CH4_AL1_CTRL: u32,
-            ///  Alias for channel 4 READ_ADDR register
-            CH4_AL1_READ_ADDR: u32,
-            ///  Alias for channel 4 WRITE_ADDR register
-            CH4_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 4 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH4_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 4 CTRL register
-            CH4_AL2_CTRL: u32,
-            ///  Alias for channel 4 TRANS_COUNT register
-            CH4_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 4 READ_ADDR register
-            CH4_AL2_READ_ADDR: u32,
-            ///  Alias for channel 4 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH4_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 4 CTRL register
-            CH4_AL3_CTRL: u32,
-            ///  Alias for channel 4 WRITE_ADDR register
-            CH4_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 4 TRANS_COUNT register
-            CH4_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 4 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH4_AL3_READ_ADDR_TRIG: u32,
-            ///  DMA Channel 5 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH5_READ_ADDR: u32,
-            ///  DMA Channel 5 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH5_WRITE_ADDR: u32,
-            ///  DMA Channel 5 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH5_TRANS_COUNT: u32,
-            ///  DMA Channel 5 Control and Status
-            CH5_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 5 CTRL register
-            CH5_AL1_CTRL: u32,
-            ///  Alias for channel 5 READ_ADDR register
-            CH5_AL1_READ_ADDR: u32,
-            ///  Alias for channel 5 WRITE_ADDR register
-            CH5_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 5 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH5_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 5 CTRL register
-            CH5_AL2_CTRL: u32,
-            ///  Alias for channel 5 TRANS_COUNT register
-            CH5_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 5 READ_ADDR register
-            CH5_AL2_READ_ADDR: u32,
-            ///  Alias for channel 5 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH5_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 5 CTRL register
-            CH5_AL3_CTRL: u32,
-            ///  Alias for channel 5 WRITE_ADDR register
-            CH5_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 5 TRANS_COUNT register
-            CH5_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 5 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH5_AL3_READ_ADDR_TRIG: u32,
-            ///  DMA Channel 6 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH6_READ_ADDR: u32,
-            ///  DMA Channel 6 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH6_WRITE_ADDR: u32,
-            ///  DMA Channel 6 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH6_TRANS_COUNT: u32,
-            ///  DMA Channel 6 Control and Status
-            CH6_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 6 CTRL register
-            CH6_AL1_CTRL: u32,
-            ///  Alias for channel 6 READ_ADDR register
-            CH6_AL1_READ_ADDR: u32,
-            ///  Alias for channel 6 WRITE_ADDR register
-            CH6_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 6 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH6_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 6 CTRL register
-            CH6_AL2_CTRL: u32,
-            ///  Alias for channel 6 TRANS_COUNT register
-            CH6_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 6 READ_ADDR register
-            CH6_AL2_READ_ADDR: u32,
-            ///  Alias for channel 6 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH6_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 6 CTRL register
-            CH6_AL3_CTRL: u32,
-            ///  Alias for channel 6 WRITE_ADDR register
-            CH6_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 6 TRANS_COUNT register
-            CH6_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 6 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH6_AL3_READ_ADDR_TRIG: u32,
-            ///  DMA Channel 7 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH7_READ_ADDR: u32,
-            ///  DMA Channel 7 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH7_WRITE_ADDR: u32,
-            ///  DMA Channel 7 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH7_TRANS_COUNT: u32,
-            ///  DMA Channel 7 Control and Status
-            CH7_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 7 CTRL register
-            CH7_AL1_CTRL: u32,
-            ///  Alias for channel 7 READ_ADDR register
-            CH7_AL1_READ_ADDR: u32,
-            ///  Alias for channel 7 WRITE_ADDR register
-            CH7_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 7 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH7_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 7 CTRL register
-            CH7_AL2_CTRL: u32,
-            ///  Alias for channel 7 TRANS_COUNT register
-            CH7_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 7 READ_ADDR register
-            CH7_AL2_READ_ADDR: u32,
-            ///  Alias for channel 7 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH7_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 7 CTRL register
-            CH7_AL3_CTRL: u32,
-            ///  Alias for channel 7 WRITE_ADDR register
-            CH7_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 7 TRANS_COUNT register
-            CH7_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 7 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH7_AL3_READ_ADDR_TRIG: u32,
-            ///  DMA Channel 8 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH8_READ_ADDR: u32,
-            ///  DMA Channel 8 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH8_WRITE_ADDR: u32,
-            ///  DMA Channel 8 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH8_TRANS_COUNT: u32,
-            ///  DMA Channel 8 Control and Status
-            CH8_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 8 CTRL register
-            CH8_AL1_CTRL: u32,
-            ///  Alias for channel 8 READ_ADDR register
-            CH8_AL1_READ_ADDR: u32,
-            ///  Alias for channel 8 WRITE_ADDR register
-            CH8_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 8 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH8_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 8 CTRL register
-            CH8_AL2_CTRL: u32,
-            ///  Alias for channel 8 TRANS_COUNT register
-            CH8_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 8 READ_ADDR register
-            CH8_AL2_READ_ADDR: u32,
-            ///  Alias for channel 8 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH8_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 8 CTRL register
-            CH8_AL3_CTRL: u32,
-            ///  Alias for channel 8 WRITE_ADDR register
-            CH8_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 8 TRANS_COUNT register
-            CH8_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 8 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH8_AL3_READ_ADDR_TRIG: u32,
-            ///  DMA Channel 9 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH9_READ_ADDR: u32,
-            ///  DMA Channel 9 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH9_WRITE_ADDR: u32,
-            ///  DMA Channel 9 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH9_TRANS_COUNT: u32,
-            ///  DMA Channel 9 Control and Status
-            CH9_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 9 CTRL register
-            CH9_AL1_CTRL: u32,
-            ///  Alias for channel 9 READ_ADDR register
-            CH9_AL1_READ_ADDR: u32,
-            ///  Alias for channel 9 WRITE_ADDR register
-            CH9_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 9 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH9_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 9 CTRL register
-            CH9_AL2_CTRL: u32,
-            ///  Alias for channel 9 TRANS_COUNT register
-            CH9_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 9 READ_ADDR register
-            CH9_AL2_READ_ADDR: u32,
-            ///  Alias for channel 9 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH9_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 9 CTRL register
-            CH9_AL3_CTRL: u32,
-            ///  Alias for channel 9 WRITE_ADDR register
-            CH9_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 9 TRANS_COUNT register
-            CH9_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 9 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH9_AL3_READ_ADDR_TRIG: u32,
-            ///  DMA Channel 10 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH10_READ_ADDR: u32,
-            ///  DMA Channel 10 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH10_WRITE_ADDR: u32,
-            ///  DMA Channel 10 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH10_TRANS_COUNT: u32,
-            ///  DMA Channel 10 Control and Status
-            CH10_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 10 CTRL register
-            CH10_AL1_CTRL: u32,
-            ///  Alias for channel 10 READ_ADDR register
-            CH10_AL1_READ_ADDR: u32,
-            ///  Alias for channel 10 WRITE_ADDR register
-            CH10_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 10 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH10_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 10 CTRL register
-            CH10_AL2_CTRL: u32,
-            ///  Alias for channel 10 TRANS_COUNT register
-            CH10_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 10 READ_ADDR register
-            CH10_AL2_READ_ADDR: u32,
-            ///  Alias for channel 10 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH10_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 10 CTRL register
-            CH10_AL3_CTRL: u32,
-            ///  Alias for channel 10 WRITE_ADDR register
-            CH10_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 10 TRANS_COUNT register
-            CH10_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 10 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH10_AL3_READ_ADDR_TRIG: u32,
-            ///  DMA Channel 11 Read Address pointer
-            ///  This register updates automatically each time a read completes. The current value is the next address to be read by this channel.
-            CH11_READ_ADDR: u32,
-            ///  DMA Channel 11 Write Address pointer
-            ///  This register updates automatically each time a write completes. The current value is the next address to be written by this channel.
-            CH11_WRITE_ADDR: u32,
-            ///  DMA Channel 11 Transfer Count
-            ///  Program the number of bus transfers a channel will perform before halting. Note that, if transfers are larger than one byte in size, this is not equal to the number of bytes transferred (see CTRL_DATA_SIZE).
-            ///  When the channel is active, reading this register shows the number of transfers remaining, updating automatically each time a write transfer completes.
-            ///  Writing this register sets the RELOAD value for the transfer counter. Each time this channel is triggered, the RELOAD value is copied into the live transfer counter. The channel can be started multiple times, and will perform the same number of transfers each time, as programmed by most recent write.
-            ///  The RELOAD value can be observed at CHx_DBG_TCR. If TRANS_COUNT is used as a trigger, the written value is used immediately as the length of the new transfer sequence, as well as being written to RELOAD.
-            CH11_TRANS_COUNT: u32,
-            ///  DMA Channel 11 Control and Status
-            CH11_CTRL_TRIG: mmio.Mmio(packed struct(u32) {
-                ///  DMA Channel Enable.
-                ///  When 1, the channel will respond to triggering events, which will cause it to become BUSY and start transferring data. When 0, the channel will ignore triggers, stop issuing transfers, and pause the current transfer sequence (i.e. BUSY will remain high if already high)
-                EN: u1,
-                ///  HIGH_PRIORITY gives a channel preferential treatment in issue scheduling: in each scheduling round, all high priority channels are considered first, and then only a single low priority channel, before returning to the high priority channels.
-                ///  This only affects the order in which the DMA schedules channels. The DMA's bus priority is not changed. If the DMA is not saturated then a low priority channel will see no loss of throughput.
-                HIGH_PRIORITY: u1,
-                ///  Set the size of each bus transfer (byte/halfword/word). READ_ADDR and WRITE_ADDR advance by this amount (1/2/4 bytes) with each transfer.
-                DATA_SIZE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        SIZE_BYTE = 0x0,
-                        SIZE_HALFWORD = 0x1,
-                        SIZE_WORD = 0x2,
-                        _,
-                    },
-                },
-                ///  If 1, the read address increments with each transfer. If 0, each read is directed to the same, initial address.
-                ///  Generally this should be disabled for peripheral-to-memory transfers.
-                INCR_READ: u1,
-                ///  If 1, the write address increments with each transfer. If 0, each write is directed to the same, initial address.
-                ///  Generally this should be disabled for memory-to-peripheral transfers.
-                INCR_WRITE: u1,
-                ///  Size of address wrap region. If 0, don't wrap. For values n > 0, only the lower n bits of the address will change. This wraps the address on a (1 << n) byte boundary, facilitating access to naturally-aligned ring buffers.
-                ///  Ring sizes between 2 and 32768 bytes are possible. This can apply to either read or write addresses, based on value of RING_SEL.
-                RING_SIZE: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        RING_NONE = 0x0,
-                        _,
-                    },
-                },
-                ///  Select whether RING_SIZE applies to read or write addresses.
-                ///  If 0, read addresses are wrapped on a (1 << RING_SIZE) boundary. If 1, write addresses are wrapped.
-                RING_SEL: u1,
-                ///  When this channel completes, it will trigger the channel indicated by CHAIN_TO. Disable by setting CHAIN_TO = _(this channel)_.
-                CHAIN_TO: u4,
-                ///  Select a Transfer Request signal.
-                ///  The channel uses the transfer request signal to pace its data transfer rate. Sources for TREQ signals are internal (TIMERS) or external (DREQ, a Data Request from the system).
-                ///  0x0 to 0x3a -> select DREQ n as TREQ
-                TREQ_SEL: packed union {
-                    raw: u6,
-                    value: enum(u6) {
-                        ///  Select Timer 0 as TREQ
-                        TIMER0 = 0x3b,
-                        ///  Select Timer 1 as TREQ
-                        TIMER1 = 0x3c,
-                        ///  Select Timer 2 as TREQ (Optional)
-                        TIMER2 = 0x3d,
-                        ///  Select Timer 3 as TREQ (Optional)
-                        TIMER3 = 0x3e,
-                        ///  Permanent request, for unpaced transfers.
-                        PERMANENT = 0x3f,
-                        _,
-                    },
-                },
-                ///  In QUIET mode, the channel does not generate IRQs at the end of every transfer block. Instead, an IRQ is raised when NULL is written to a trigger register, indicating the end of a control block chain.
-                ///  This reduces the number of interrupts to be serviced by the CPU when transferring a DMA chain of many small control blocks.
-                IRQ_QUIET: u1,
-                ///  Apply byte-swap transformation to DMA data.
-                ///  For byte data, this has no effect. For halfword data, the two bytes of each halfword are swapped. For word data, the four bytes of each word are swapped to reverse order.
-                BSWAP: u1,
-                ///  If 1, this channel's data transfers are visible to the sniff hardware, and each transfer will advance the state of the checksum. This only applies if the sniff hardware is enabled, and has this channel selected.
-                ///  This allows checksum to be enabled or disabled on a per-control- block basis.
-                SNIFF_EN: u1,
-                ///  This flag goes high when the channel starts a new transfer sequence, and low when the last transfer of that sequence completes. Clearing EN while BUSY is high pauses the channel, and BUSY will stay high while paused.
-                ///  To terminate a sequence early (and clear the BUSY flag), see CHAN_ABORT.
-                BUSY: u1,
-                reserved29: u4,
-                ///  If 1, the channel received a write bus error. Write one to clear.
-                ///  WRITE_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 5 transfers later)
-                WRITE_ERROR: u1,
-                ///  If 1, the channel received a read bus error. Write one to clear.
-                ///  READ_ADDR shows the approximate address where the bus error was encountered (will not to be earlier, or more than 3 transfers later)
-                READ_ERROR: u1,
-                ///  Logical OR of the READ_ERROR and WRITE_ERROR flags. The channel halts when it encounters any bus error, and always raises its channel IRQ flag.
-                AHB_ERROR: u1,
-            }),
-            ///  Alias for channel 11 CTRL register
-            CH11_AL1_CTRL: u32,
-            ///  Alias for channel 11 READ_ADDR register
-            CH11_AL1_READ_ADDR: u32,
-            ///  Alias for channel 11 WRITE_ADDR register
-            CH11_AL1_WRITE_ADDR: u32,
-            ///  Alias for channel 11 TRANS_COUNT register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH11_AL1_TRANS_COUNT_TRIG: u32,
-            ///  Alias for channel 11 CTRL register
-            CH11_AL2_CTRL: u32,
-            ///  Alias for channel 11 TRANS_COUNT register
-            CH11_AL2_TRANS_COUNT: u32,
-            ///  Alias for channel 11 READ_ADDR register
-            CH11_AL2_READ_ADDR: u32,
-            ///  Alias for channel 11 WRITE_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH11_AL2_WRITE_ADDR_TRIG: u32,
-            ///  Alias for channel 11 CTRL register
-            CH11_AL3_CTRL: u32,
-            ///  Alias for channel 11 WRITE_ADDR register
-            CH11_AL3_WRITE_ADDR: u32,
-            ///  Alias for channel 11 TRANS_COUNT register
-            CH11_AL3_TRANS_COUNT: u32,
-            ///  Alias for channel 11 READ_ADDR register
-            ///  This is a trigger register (0xc). Writing a nonzero value will
-            ///  reload the channel counter and start the channel.
-            CH11_AL3_READ_ADDR_TRIG: u32,
-            reserved1024: [256]u8,
-            ///  Interrupt Status (raw)
-            INTR: mmio.Mmio(packed struct(u32) {
-                ///  Raw interrupt status for DMA Channels 0..15. Bit n corresponds to channel n. Ignores any masking or forcing. Channel interrupts can be cleared by writing a bit mask to INTR, INTS0 or INTS1.
-                ///  Channel interrupts can be routed to either of two system-level IRQs based on INTE0 and INTE1.
-                ///  This can be used vector different channel interrupts to different ISRs: this might be done to allow NVIC IRQ preemption for more time-critical channels, or to spread IRQ load across different cores.
-                ///  It is also valid to ignore this behaviour and just use INTE0/INTS0/IRQ 0.
-                INTR: u16,
-                padding: u16,
-            }),
-            ///  Interrupt Enables for IRQ 0
-            INTE0: mmio.Mmio(packed struct(u32) {
-                ///  Set bit n to pass interrupts from channel n to DMA IRQ 0.
-                INTE0: u16,
-                padding: u16,
-            }),
-            ///  Force Interrupts
-            INTF0: mmio.Mmio(packed struct(u32) {
-                ///  Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.
-                INTF0: u16,
-                padding: u16,
-            }),
-            ///  Interrupt Status for IRQ 0
-            INTS0: mmio.Mmio(packed struct(u32) {
-                ///  Indicates active channel interrupt requests which are currently causing IRQ 0 to be asserted.
-                ///  Channel interrupts can be cleared by writing a bit mask here.
-                INTS0: u16,
-                padding: u16,
-            }),
-            reserved1044: [4]u8,
-            ///  Interrupt Enables for IRQ 1
-            INTE1: mmio.Mmio(packed struct(u32) {
-                ///  Set bit n to pass interrupts from channel n to DMA IRQ 1.
-                INTE1: u16,
-                padding: u16,
-            }),
-            ///  Force Interrupts for IRQ 1
-            INTF1: mmio.Mmio(packed struct(u32) {
-                ///  Write 1s to force the corresponding bits in INTE0. The interrupt remains asserted until INTF0 is cleared.
-                INTF1: u16,
-                padding: u16,
-            }),
-            ///  Interrupt Status (masked) for IRQ 1
-            INTS1: mmio.Mmio(packed struct(u32) {
-                ///  Indicates active channel interrupt requests which are currently causing IRQ 1 to be asserted.
-                ///  Channel interrupts can be cleared by writing a bit mask here.
-                INTS1: u16,
-                padding: u16,
-            }),
-            ///  Pacing (X/Y) Fractional Timer
-            ///  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
-            TIMER0: mmio.Mmio(packed struct(u32) {
-                ///  Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
-                Y: u16,
-                ///  Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
-                X: u16,
-            }),
-            ///  Pacing (X/Y) Fractional Timer
-            ///  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
-            TIMER1: mmio.Mmio(packed struct(u32) {
-                ///  Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
-                Y: u16,
-                ///  Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
-                X: u16,
-            }),
-            ///  Pacing (X/Y) Fractional Timer
-            ///  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
-            TIMER2: mmio.Mmio(packed struct(u32) {
-                ///  Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
-                Y: u16,
-                ///  Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
-                X: u16,
-            }),
-            ///  Pacing (X/Y) Fractional Timer
-            ///  The pacing timer produces TREQ assertions at a rate set by ((X/Y) * sys_clk). This equation is evaluated every sys_clk cycles and therefore can only generate TREQs at a rate of 1 per sys_clk (i.e. permanent TREQ) or less.
-            TIMER3: mmio.Mmio(packed struct(u32) {
-                ///  Pacing Timer Divisor. Specifies the Y value for the (X/Y) fractional timer.
-                Y: u16,
-                ///  Pacing Timer Dividend. Specifies the X value for the (X/Y) fractional timer.
-                X: u16,
-            }),
-            ///  Trigger one or more channels simultaneously
-            MULTI_CHAN_TRIGGER: mmio.Mmio(packed struct(u32) {
-                ///  Each bit in this register corresponds to a DMA channel. Writing a 1 to the relevant bit is the same as writing to that channel's trigger register; the channel will start if it is currently enabled and not already busy.
-                MULTI_CHAN_TRIGGER: u16,
-                padding: u16,
-            }),
-            ///  Sniffer Control
-            SNIFF_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Enable sniffer
-                EN: u1,
-                ///  DMA channel for Sniffer to observe
-                DMACH: u4,
-                CALC: packed union {
-                    raw: u4,
-                    value: enum(u4) {
-                        ///  Calculate a CRC-32 (IEEE802.3 polynomial)
-                        CRC32 = 0x0,
-                        ///  Calculate a CRC-32 (IEEE802.3 polynomial) with bit reversed data
-                        CRC32R = 0x1,
-                        ///  Calculate a CRC-16-CCITT
-                        CRC16 = 0x2,
-                        ///  Calculate a CRC-16-CCITT with bit reversed data
-                        CRC16R = 0x3,
-                        ///  XOR reduction over all data. == 1 if the total 1 population count is odd.
-                        EVEN = 0xe,
-                        ///  Calculate a simple 32-bit checksum (addition with a 32 bit accumulator)
-                        SUM = 0xf,
-                        _,
-                    },
-                },
-                ///  Locally perform a byte reverse on the sniffed data, before feeding into checksum.
-                ///  Note that the sniff hardware is downstream of the DMA channel byteswap performed in the read master: if channel CTRL_BSWAP and SNIFF_CTRL_BSWAP are both enabled, their effects cancel from the sniffer's point of view.
-                BSWAP: u1,
-                ///  If set, the result appears bit-reversed when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.
-                OUT_REV: u1,
-                ///  If set, the result appears inverted (bitwise complement) when read. This does not affect the way the checksum is calculated; the result is transformed on-the-fly between the result register and the bus.
-                OUT_INV: u1,
-                padding: u20,
-            }),
-            ///  Data accumulator for sniff hardware
-            ///  Write an initial seed value here before starting a DMA transfer on the channel indicated by SNIFF_CTRL_DMACH. The hardware will update this register each time it observes a read from the indicated channel. Once the channel completes, the final result can be read from this register.
-            SNIFF_DATA: u32,
-            reserved1088: [4]u8,
-            ///  Debug RAF, WAF, TDF levels
-            FIFO_LEVELS: mmio.Mmio(packed struct(u32) {
-                ///  Current Transfer-Data-FIFO fill level
-                TDF_LVL: u8,
-                ///  Current Write-Address-FIFO fill level
-                WAF_LVL: u8,
-                ///  Current Read-Address-FIFO fill level
-                RAF_LVL: u8,
-                padding: u8,
-            }),
-            ///  Abort an in-progress transfer sequence on one or more channels
-            CHAN_ABORT: mmio.Mmio(packed struct(u32) {
-                ///  Each bit corresponds to a channel. Writing a 1 aborts whatever transfer sequence is in progress on that channel. The bit will remain high until any in-flight transfers have been flushed through the address and data FIFOs.
-                ///  After writing, this register must be polled until it returns all-zero. Until this point, it is unsafe to restart the channel.
-                CHAN_ABORT: u16,
-                padding: u16,
-            }),
-            ///  The number of channels this DMA instance is equipped with. This DMA supports up to 16 hardware channels, but can be configured with as few as one, to minimise silicon area.
-            N_CHANNELS: mmio.Mmio(packed struct(u32) {
-                N_CHANNELS: u5,
-                padding: u27,
-            }),
-            reserved2048: [948]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH0_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH0_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH0_DBG_TCR: u32,
-            reserved2112: [56]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH1_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH1_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH1_DBG_TCR: u32,
-            reserved2176: [56]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH2_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH2_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH2_DBG_TCR: u32,
-            reserved2240: [56]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH3_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH3_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH3_DBG_TCR: u32,
-            reserved2304: [56]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH4_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH4_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH4_DBG_TCR: u32,
-            reserved2368: [56]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH5_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH5_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH5_DBG_TCR: u32,
-            reserved2432: [56]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH6_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH6_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH6_DBG_TCR: u32,
-            reserved2496: [56]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH7_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH7_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH7_DBG_TCR: u32,
-            reserved2560: [56]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH8_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH8_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH8_DBG_TCR: u32,
-            reserved2624: [56]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH9_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH9_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH9_DBG_TCR: u32,
-            reserved2688: [56]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH10_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH10_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH10_DBG_TCR: u32,
-            reserved2752: [56]u8,
-            ///  Read: get channel DREQ counter (i.e. how many accesses the DMA expects it can perform on the peripheral without overflow/underflow. Write any value: clears the counter, and cause channel to re-initiate DREQ handshake.
-            CH11_DBG_CTDREQ: mmio.Mmio(packed struct(u32) {
-                CH11_DBG_CTDREQ: u6,
-                padding: u26,
-            }),
-            ///  Read to get channel TRANS_COUNT reload value, i.e. the length of the next transfer
-            CH11_DBG_TCR: u32,
-        };
-
-        ///  DPRAM layout for USB device.
-        pub const USBCTRL_DPRAM = extern struct {
-            ///  Bytes 0-3 of the SETUP packet from the host.
-            SETUP_PACKET_LOW: mmio.Mmio(packed struct(u32) {
-                BMREQUESTTYPE: u8,
-                BREQUEST: u8,
-                WVALUE: u16,
-            }),
-            ///  Bytes 4-7 of the setup packet from the host.
-            SETUP_PACKET_HIGH: mmio.Mmio(packed struct(u32) {
-                WINDEX: u16,
-                WLENGTH: u16,
-            }),
-            EP1_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP1_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP2_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP2_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP3_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP3_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP4_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP4_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP5_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP5_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP6_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP6_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP7_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP7_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP8_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP8_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP9_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP9_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP10_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP10_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP11_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP11_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP12_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP12_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP13_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP13_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP14_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP14_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP15_IN_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            EP15_OUT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  64 byte aligned buffer address for this EP (bits 0-5 are ignored). Relative to the start of the DPRAM.
-                BUFFER_ADDRESS: u16,
-                ///  Trigger an interrupt if a NAK is sent. Intended for debug only.
-                INTERRUPT_ON_NAK: u1,
-                ///  Trigger an interrupt if a STALL is sent. Intended for debug only.
-                INTERRUPT_ON_STALL: u1,
-                reserved26: u8,
-                ENDPOINT_TYPE: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        Control = 0x0,
-                        Isochronous = 0x1,
-                        Bulk = 0x2,
-                        Interrupt = 0x3,
-                    },
-                },
-                ///  Trigger an interrupt each time both buffers are done. Only valid in double buffered mode.
-                INTERRUPT_PER_DOUBLE_BUFF: u1,
-                ///  Trigger an interrupt each time a buffer is done.
-                INTERRUPT_PER_BUFF: u1,
-                ///  This endpoint is double buffered.
-                DOUBLE_BUFFERED: u1,
-                ///  Enable this endpoint. The device will not reply to any packets for this endpoint if this bit is not set.
-                ENABLE: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP0_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP0_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP1_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP1_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP2_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP2_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP3_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP3_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP4_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP4_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP5_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP5_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP6_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP6_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP7_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP7_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP8_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP8_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP9_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP9_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP10_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP10_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP11_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP11_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP12_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP12_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP13_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP13_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP14_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP14_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP15_IN_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-            ///  Buffer control for both buffers of an endpoint. Fields ending in a _1 are for buffer 1.
-            ///  Fields ending in a _0 are for buffer 0. Buffer 1 controls are only valid if the endpoint is in double buffered mode.
-            EP15_OUT_BUFFER_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  The length of the data in buffer 0.
-                LENGTH_0: u10,
-                ///  Buffer 0 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_0: u1,
-                ///  Reply with a stall (valid for both buffers).
-                STALL: u1,
-                ///  Reset the buffer selector to buffer 0.
-                RESET: u1,
-                ///  The data pid of buffer 0.
-                PID_0: u1,
-                ///  Buffer 0 is the last buffer of the transfer.
-                LAST_0: u1,
-                ///  Buffer 0 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_0: u1,
-                ///  The length of the data in buffer 1.
-                LENGTH_1: u10,
-                ///  Buffer 1 is available. This bit is set to indicate the buffer can be used by the controller. The controller clears the available bit when writing the status back.
-                AVAILABLE_1: u1,
-                ///  The number of bytes buffer 1 is offset from buffer 0 in Isochronous mode. Only valid in double buffered mode for an Isochronous endpoint.
-                ///  For a non Isochronous endpoint the offset is always 64 bytes.
-                DOUBLE_BUFFER_ISO_OFFSET: packed union {
-                    raw: u2,
-                    value: enum(u2) {
-                        @"128" = 0x0,
-                        @"256" = 0x1,
-                        @"512" = 0x2,
-                        @"1024" = 0x3,
-                    },
-                },
-                ///  The data pid of buffer 1.
-                PID_1: u1,
-                ///  Buffer 1 is the last buffer of the transfer.
-                LAST_1: u1,
-                ///  Buffer 1 is full. For an IN transfer (TX to the host) the bit is set to indicate the data is valid. For an OUT transfer (RX from the host) this bit should be left as a 0. The host will set it when it has filled the buffer with data.
-                FULL_1: u1,
-            }),
-        };
-    };
-};

From e018e7ec6f3a483d3d3baa25506448b8cb532648 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Fri, 22 Sep 2023 09:03:15 +0200
Subject: [PATCH 207/286] Microzig Generation 2 Build Interface  (#28)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* Removes old build code.
* Makes basic build work again.
* First build
* Drops CI

---------

Co-authored-by: Felix "xq" Queißner 
---
 .github/FUNDING.yml                   |     1 -
 .github/workflows/build.yml           |    19 -
 build.zig                             |    82 +-
 build.zig.zon                         |     7 +-
 src/chips.zig                         |    23 -
 esp32c3.svd => src/chips/ESP32-C3.svd |     0
 src/chips/ESP32_C3.json               | 33570 ------------------------
 src/chips/ESP32_C3.zig                | 12378 ---------
 src/cpus.zig                          |    23 -
 9 files changed, 64 insertions(+), 46039 deletions(-)
 delete mode 100644 .github/FUNDING.yml
 delete mode 100644 .github/workflows/build.yml
 delete mode 100644 src/chips.zig
 rename esp32c3.svd => src/chips/ESP32-C3.svd (100%)
 delete mode 100644 src/chips/ESP32_C3.json
 delete mode 100644 src/chips/ESP32_C3.zig
 delete mode 100644 src/cpus.zig

diff --git a/.github/FUNDING.yml b/.github/FUNDING.yml
deleted file mode 100644
index 85b5393bb..000000000
--- a/.github/FUNDING.yml
+++ /dev/null
@@ -1 +0,0 @@
-github: MasterQ32
diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
deleted file mode 100644
index 63ea5331c..000000000
--- a/.github/workflows/build.yml
+++ /dev/null
@@ -1,19 +0,0 @@
-name: Build
-on:
-  push:
-
-jobs:
-  build:
-    runs-on: ${{ matrix.os }}
-    strategy:
-      matrix:
-        os: [ubuntu-latest, windows-latest, macos-latest]
-        optimize: [Debug, ReleaseSmall, ReleaseFast, ReleaseSafe]
-    steps:
-      - uses: actions/checkout@v2
-      - uses: goto-bus-stop/setup-zig@v2.1.1
-        with:
-          version: 0.11.0
-
-      - name: Build
-        run: zig build install "-Doptimize=${{matrix.optimize}}"
diff --git a/build.zig b/build.zig
index e04ab94ae..089066cbd 100644
--- a/build.zig
+++ b/build.zig
@@ -1,30 +1,74 @@
 const std = @import("std");
-const microzig = @import("microzig");
 
-pub const chips = @import("src/chips.zig");
-pub const cpus = @import("src/cpus.zig");
+fn path(comptime suffix: []const u8) std.Build.LazyPath {
+    return .{
+        .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
+    };
+}
 
-pub fn build(b: *std.Build) void {
-    const optimize = b.standardOptimizeOption(.{});
+const esp_riscv = .{
+    .name = "Espressif RISC-V",
+    .source_file = path("/src/cpus/espressif-riscv.zig"),
+    .target = std.zig.CrossTarget{
+        .cpu_arch = .riscv32,
+        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
+        .cpu_features_add = std.Target.riscv.featureSet(&.{
+            std.Target.riscv.Feature.c,
+            std.Target.riscv.Feature.m,
+        }),
+        .os_tag = .freestanding,
+        .abi = .eabi,
+    },
+};
+
+const hal = .{
+    .source_file = path("/src/hals/ESP32_C3.zig"),
+};
+
+pub const chips = struct {
+    pub const esp32_c3 = .{
+        .preferred_format = .bin, // TODO: Exchange FLAT format with .esp format
+        .chip = .{
+            .name = "ESP32-C3",
+            .url = "https://www.espressif.com/en/products/socs/esp32-c3",
+
+            .cpu = .{ .custom = &esp_riscv },
 
-    var exe = microzig.addEmbeddedExecutable(b, .{
-        .name = "esp-bringup",
-        .source_file = .{
-            .path = "src/example/blinky.zig",
+            .register_definition = .{
+                .svd = path("/src/chips/ESP32-C3.svd"),
+            },
+
+            .memory_regions = &.{
+                .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
+                .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
+            },
         },
-        .backing = .{ .chip = chips.esp32_c3 },
-        .optimize = optimize,
-    });
+        .hal = hal,
+    };
+};
+
+pub fn build(b: *std.Build) void {
+    _ = b;
+    // const optimize = b.standardOptimizeOption(.{});
+
+    // var exe = microzig.addEmbeddedExecutable(b, .{
+    //     .name = "esp-bringup",
+    //     .source_file = .{
+    //         .path = "src/example/blinky.zig",
+    //     },
+    //     .backing = .{ .chip = chips.esp32_c3 },
+    //     .optimize = optimize,
+    // });
 
-    const fw_objcopy = b.addObjCopy(exe.inner.getEmittedBin(), .{
-        .format = .bin,
-    });
+    // const fw_objcopy = b.addObjCopy(exe.inner.getEmittedBin(), .{
+    //     .format = .bin,
+    // });
 
-    const fw_bin = fw_objcopy.getOutput();
+    // const fw_bin = fw_objcopy.getOutput();
 
-    const install_fw_bin = b.addInstallFile(fw_bin, "firmware/blinky.bin");
+    // const install_fw_bin = b.addInstallFile(fw_bin, "firmware/blinky.bin");
 
-    b.getInstallStep().dependOn(&install_fw_bin.step);
+    // b.getInstallStep().dependOn(&install_fw_bin.step);
 
-    b.installArtifact(exe.inner);
+    // b.installArtifact(exe.inner);
 }
diff --git a/build.zig.zon b/build.zig.zon
index e8787ef0b..fd45779e6 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -1,10 +1,5 @@
 .{
     .name = "microzig-espressif-esp",
     .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/0b3be0a4cc7e6d45714cb09961efc771e364723c.tar.gz",
-            .hash = "1220ada6d01db7b3d0aa8642df89b1af9ee71b681438249e9a7efb2275fc4cf32152",
-        },
-    },
+    .dependencies = .{},
 }
diff --git a/src/chips.zig b/src/chips.zig
deleted file mode 100644
index 3baa05a3d..000000000
--- a/src/chips.zig
+++ /dev/null
@@ -1,23 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-const cpus = @import("cpus.zig");
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
-
-pub const esp32_c3 = microzig.Chip{
-    .name = "ESP32-C3",
-    .source = .{
-        .path = root_dir() ++ "/chips/ESP32_C3.zig",
-    },
-    .hal = .{
-        .path = root_dir() ++ "/hals/ESP32_C3.zig",
-    },
-
-    .cpu = cpus.esp32_c3,
-    .memory_regions = &.{
-        .{ .kind = .flash, .offset = 0x4200_0000, .length = 0x0080_0000 }, // external memory, ibus
-        .{ .kind = .ram, .offset = 0x3FC8_0000, .length = 0x0006_0000 }, // sram 1, data bus
-    },
-};
diff --git a/esp32c3.svd b/src/chips/ESP32-C3.svd
similarity index 100%
rename from esp32c3.svd
rename to src/chips/ESP32-C3.svd
diff --git a/src/chips/ESP32_C3.json b/src/chips/ESP32_C3.json
deleted file mode 100644
index 4691dc788..000000000
--- a/src/chips/ESP32_C3.json
+++ /dev/null
@@ -1,33570 +0,0 @@
-{
-  "version": "0.1.0",
-  "types": {
-    "peripherals": {
-      "AES": {
-        "description": "AES (Advanced Encryption Standard) Accelerator",
-        "children": {
-          "registers": {
-            "KEY_0": {
-              "description": "Key material key_0 configure register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_0": {
-                    "description": "This bits stores key_0 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_1": {
-              "description": "Key material key_1 configure register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_1": {
-                    "description": "This bits stores key_1 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_2": {
-              "description": "Key material key_2 configure register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_2": {
-                    "description": "This bits stores key_2 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_3": {
-              "description": "Key material key_3 configure register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_3": {
-                    "description": "This bits stores key_3 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_4": {
-              "description": "Key material key_4 configure register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_4": {
-                    "description": "This bits stores key_4 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_5": {
-              "description": "Key material key_5 configure register",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_5": {
-                    "description": "This bits stores key_5 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_6": {
-              "description": "Key material key_6 configure register",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_6": {
-                    "description": "This bits stores key_6 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "KEY_7": {
-              "description": "Key material key_7 configure register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_7": {
-                    "description": "This bits stores key_7 that is a part of key material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_IN_0": {
-              "description": "source text material text_in_0 configure register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_IN_0": {
-                    "description": "This bits stores text_in_0 that is a part of source text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_IN_1": {
-              "description": "source text material text_in_1 configure register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_IN_1": {
-                    "description": "This bits stores text_in_1 that is a part of source text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_IN_2": {
-              "description": "source text material text_in_2 configure register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_IN_2": {
-                    "description": "This bits stores text_in_2 that is a part of source text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_IN_3": {
-              "description": "source text material text_in_3 configure register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_IN_3": {
-                    "description": "This bits stores text_in_3 that is a part of source text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_OUT_0": {
-              "description": "result text material text_out_0 configure register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_OUT_0": {
-                    "description": "This bits stores text_out_0 that is a part of result text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_OUT_1": {
-              "description": "result text material text_out_1 configure register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_OUT_1": {
-                    "description": "This bits stores text_out_1 that is a part of result text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_OUT_2": {
-              "description": "result text material text_out_2 configure register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_OUT_2": {
-                    "description": "This bits stores text_out_2 that is a part of result text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TEXT_OUT_3": {
-              "description": "result text material text_out_3 configure register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TEXT_OUT_3": {
-                    "description": "This bits stores text_out_3 that is a part of result text material.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "MODE": {
-              "description": "AES Mode register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MODE": {
-                    "description": "This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.",
-                    "offset": 0,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "ENDIAN": {
-              "description": "AES Endian configure register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENDIAN": {
-                    "description": "endian. [1:0] key endian, [3:2] text_in endian or in_stream endian,  [5:4] text_out endian or out_stream endian",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "TRIGGER": {
-              "description": "AES trigger register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TRIGGER": {
-                    "description": "Set this bit to start AES calculation.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STATE": {
-              "description": "AES state register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATE": {
-                    "description": "Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IV_MEM": {
-              "description": "The memory that stores initialization vector",
-              "offset": 80,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "H_MEM": {
-              "description": "The memory that stores GCM hash subkey",
-              "offset": 96,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "J0_MEM": {
-              "description": "The memory that stores J0",
-              "offset": 112,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "T0_MEM": {
-              "description": "The memory that stores T0",
-              "offset": 128,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "DMA_ENABLE": {
-              "description": "DMA-AES working mode register",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_ENABLE": {
-                    "description": "1'b0: typical AES working mode, 1'b1: DMA-AES working mode.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BLOCK_MODE": {
-              "description": "AES cipher block mode register",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BLOCK_MODE": {
-                    "description": "Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.",
-                    "offset": 0,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "BLOCK_NUM": {
-              "description": "AES block number register",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BLOCK_NUM": {
-                    "description": "Those bits stores the number of Plaintext/ciphertext block.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "INC_SEL": {
-              "description": "Standard incrementing function configure register",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INC_SEL": {
-                    "description": "This bit decides the standard incrementing function. 0: INC32. 1: INC128.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "AAD_BLOCK_NUM": {
-              "description": "Additional Authential Data block number register",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AAD_BLOCK_NUM": {
-                    "description": "Those bits stores the number of AAD block.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REMAINDER_BIT_NUM": {
-              "description": "AES remainder bit number register",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REMAINDER_BIT_NUM": {
-                    "description": "Those bits stores the number of remainder bit.",
-                    "offset": 0,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "CONTINUE": {
-              "description": "AES continue register",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CONTINUE": {
-                    "description": "Set this bit to continue GCM operation.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_CLEAR": {
-              "description": "AES Interrupt clear register",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INT_CLEAR": {
-                    "description": "Set this bit to clear the AES interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "AES Interrupt enable register",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INT_ENA": {
-                    "description": "Set this bit to enable interrupt that occurs when DMA-AES calculation is done.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "AES version control register",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 538513936,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "This bits stores the version information of AES.",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "DMA_EXIT": {
-              "description": "AES-DMA exit config",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_EXIT": {
-                    "description": "Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "APB_CTRL": {
-        "description": "Advanced Peripheral Bus Controller",
-        "children": {
-          "registers": {
-            "SYSCLK_CONF": {
-              "description": "APB_CTRL_SYSCLK_CONF_REG",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRE_DIV_CNT": {
-                    "description": "reg_pre_div_cnt",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "CLK_320M_EN": {
-                    "description": "reg_clk_320m_en",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "RST_TICK_CNT": {
-                    "description": "reg_rst_tick_cnt",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TICK_CONF": {
-              "description": "APB_CTRL_TICK_CONF_REG",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 67367,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XTAL_TICK_NUM": {
-                    "description": "reg_xtal_tick_num",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CK8M_TICK_NUM": {
-                    "description": "reg_ck8m_tick_num",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "TICK_ENABLE": {
-                    "description": "reg_tick_enable",
-                    "offset": 16,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLK_OUT_EN": {
-              "description": "APB_CTRL_CLK_OUT_EN_REG",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 2047,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK20_OEN": {
-                    "description": "reg_clk20_oen",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CLK22_OEN": {
-                    "description": "reg_clk22_oen",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CLK44_OEN": {
-                    "description": "reg_clk44_oen",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CLK_BB_OEN": {
-                    "description": "reg_clk_bb_oen",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CLK80_OEN": {
-                    "description": "reg_clk80_oen",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CLK160_OEN": {
-                    "description": "reg_clk160_oen",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CLK_320M_OEN": {
-                    "description": "reg_clk_320m_oen",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CLK_ADC_INF_OEN": {
-                    "description": "reg_clk_adc_inf_oen",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CLK_DAC_CPU_OEN": {
-                    "description": "reg_clk_dac_cpu_oen",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "CLK40X_BB_OEN": {
-                    "description": "reg_clk40x_bb_oen",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CLK_XTAL_OEN": {
-                    "description": "reg_clk_xtal_oen",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "WIFI_BB_CFG": {
-              "description": "APB_CTRL_WIFI_BB_CFG_REG",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WIFI_BB_CFG": {
-                    "description": "reg_wifi_bb_cfg",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WIFI_BB_CFG_2": {
-              "description": "APB_CTRL_WIFI_BB_CFG_2_REG",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WIFI_BB_CFG_2": {
-                    "description": "reg_wifi_bb_cfg_2",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WIFI_CLK_EN": {
-              "description": "APB_CTRL_WIFI_CLK_EN_REG",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 4294762544,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WIFI_CLK_EN": {
-                    "description": "reg_wifi_clk_en",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WIFI_RST_EN": {
-              "description": "APB_CTRL_WIFI_RST_EN_REG",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WIFI_RST": {
-                    "description": "reg_wifi_rst",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "HOST_INF_SEL": {
-              "description": "APB_CTRL_HOST_INF_SEL_REG",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_IO_SWAP": {
-                    "description": "reg_peri_io_swap",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "EXT_MEM_PMS_LOCK": {
-              "description": "APB_CTRL_EXT_MEM_PMS_LOCK_REG",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "EXT_MEM_PMS_LOCK": {
-                    "description": "reg_ext_mem_pms_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FLASH_ACE0_ATTR": {
-              "description": "APB_CTRL_FLASH_ACE0_ATTR_REG",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE0_ATTR": {
-                    "description": "reg_flash_ace0_attr",
-                    "offset": 0,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "FLASH_ACE1_ATTR": {
-              "description": "APB_CTRL_FLASH_ACE1_ATTR_REG",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE1_ATTR": {
-                    "description": "reg_flash_ace1_attr",
-                    "offset": 0,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "FLASH_ACE2_ATTR": {
-              "description": "APB_CTRL_FLASH_ACE2_ATTR_REG",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE2_ATTR": {
-                    "description": "reg_flash_ace2_attr",
-                    "offset": 0,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "FLASH_ACE3_ATTR": {
-              "description": "APB_CTRL_FLASH_ACE3_ATTR_REG",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE3_ATTR": {
-                    "description": "reg_flash_ace3_attr",
-                    "offset": 0,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "FLASH_ACE0_ADDR": {
-              "description": "APB_CTRL_FLASH_ACE0_ADDR_REG",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "S": {
-                    "description": "reg_flash_ace0_addr_s",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "FLASH_ACE1_ADDR": {
-              "description": "APB_CTRL_FLASH_ACE1_ADDR_REG",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 4194304,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "S": {
-                    "description": "reg_flash_ace1_addr_s",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "FLASH_ACE2_ADDR": {
-              "description": "APB_CTRL_FLASH_ACE2_ADDR_REG",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "S": {
-                    "description": "reg_flash_ace2_addr_s",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "FLASH_ACE3_ADDR": {
-              "description": "APB_CTRL_FLASH_ACE3_ADDR_REG",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 12582912,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "S": {
-                    "description": "reg_flash_ace3_addr_s",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "FLASH_ACE0_SIZE": {
-              "description": "APB_CTRL_FLASH_ACE0_SIZE_REG",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 1024,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE0_SIZE": {
-                    "description": "reg_flash_ace0_size",
-                    "offset": 0,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "FLASH_ACE1_SIZE": {
-              "description": "APB_CTRL_FLASH_ACE1_SIZE_REG",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 1024,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE1_SIZE": {
-                    "description": "reg_flash_ace1_size",
-                    "offset": 0,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "FLASH_ACE2_SIZE": {
-              "description": "APB_CTRL_FLASH_ACE2_SIZE_REG",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 1024,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE2_SIZE": {
-                    "description": "reg_flash_ace2_size",
-                    "offset": 0,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "FLASH_ACE3_SIZE": {
-              "description": "APB_CTRL_FLASH_ACE3_SIZE_REG",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 1024,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_ACE3_SIZE": {
-                    "description": "reg_flash_ace3_size",
-                    "offset": 0,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "SPI_MEM_PMS_CTRL": {
-              "description": "APB_CTRL_SPI_MEM_PMS_CTRL_REG",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_MEM_REJECT_INT": {
-                    "description": "reg_spi_mem_reject_int",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SPI_MEM_REJECT_CLR": {
-                    "description": "reg_spi_mem_reject_clr",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SPI_MEM_REJECT_CDE": {
-                    "description": "reg_spi_mem_reject_cde",
-                    "offset": 2,
-                    "size": 5,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SPI_MEM_REJECT_ADDR": {
-              "description": "APB_CTRL_SPI_MEM_REJECT_ADDR_REG",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_MEM_REJECT_ADDR": {
-                    "description": "reg_spi_mem_reject_addr",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SDIO_CTRL": {
-              "description": "APB_CTRL_SDIO_CTRL_REG",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SDIO_WIN_ACCESS_EN": {
-                    "description": "reg_sdio_win_access_en",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "REDCY_SIG0": {
-              "description": "APB_CTRL_REDCY_SIG0_REG",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REDCY_SIG0": {
-                    "description": "reg_redcy_sig0",
-                    "offset": 0,
-                    "size": 31
-                  },
-                  "REDCY_ANDOR": {
-                    "description": "reg_redcy_andor",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "REDCY_SIG1": {
-              "description": "APB_CTRL_REDCY_SIG1_REG",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REDCY_SIG1": {
-                    "description": "reg_redcy_sig1",
-                    "offset": 0,
-                    "size": 31
-                  },
-                  "REDCY_NANDOR": {
-                    "description": "reg_redcy_nandor",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "FRONT_END_MEM_PD": {
-              "description": "APB_CTRL_FRONT_END_MEM_PD_REG",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 21,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AGC_MEM_FORCE_PU": {
-                    "description": "reg_agc_mem_force_pu",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "AGC_MEM_FORCE_PD": {
-                    "description": "reg_agc_mem_force_pd",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "PBUS_MEM_FORCE_PU": {
-                    "description": "reg_pbus_mem_force_pu",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "PBUS_MEM_FORCE_PD": {
-                    "description": "reg_pbus_mem_force_pd",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "DC_MEM_FORCE_PU": {
-                    "description": "reg_dc_mem_force_pu",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "DC_MEM_FORCE_PD": {
-                    "description": "reg_dc_mem_force_pd",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RETENTION_CTRL": {
-              "description": "APB_CTRL_RETENTION_CTRL_REG",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RETENTION_LINK_ADDR": {
-                    "description": "reg_retention_link_addr",
-                    "offset": 0,
-                    "size": 27
-                  },
-                  "NOBYPASS_CPU_ISO_RST": {
-                    "description": "reg_nobypass_cpu_iso_rst",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLKGATE_FORCE_ON": {
-              "description": "APB_CTRL_CLKGATE_FORCE_ON_REG",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ROM_CLKGATE_FORCE_ON": {
-                    "description": "reg_rom_clkgate_force_on",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SRAM_CLKGATE_FORCE_ON": {
-                    "description": "reg_sram_clkgate_force_on",
-                    "offset": 2,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "MEM_POWER_DOWN": {
-              "description": "APB_CTRL_MEM_POWER_DOWN_REG",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ROM_POWER_DOWN": {
-                    "description": "reg_rom_power_down",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SRAM_POWER_DOWN": {
-                    "description": "reg_sram_power_down",
-                    "offset": 2,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "MEM_POWER_UP": {
-              "description": "APB_CTRL_MEM_POWER_UP_REG",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ROM_POWER_UP": {
-                    "description": "reg_rom_power_up",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SRAM_POWER_UP": {
-                    "description": "reg_sram_power_up",
-                    "offset": 2,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "RND_DATA": {
-              "description": "APB_CTRL_RND_DATA_REG",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RND_DATA": {
-                    "description": "reg_rnd_data",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_CONFIG": {
-              "description": "APB_CTRL_PERI_BACKUP_CONFIG_REG",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 25728,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_BACKUP_FLOW_ERR": {
-                    "description": "reg_peri_backup_flow_err",
-                    "offset": 1,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "PERI_BACKUP_BURST_LIMIT": {
-                    "description": "reg_peri_backup_burst_limit",
-                    "offset": 4,
-                    "size": 5
-                  },
-                  "PERI_BACKUP_TOUT_THRES": {
-                    "description": "reg_peri_backup_tout_thres",
-                    "offset": 9,
-                    "size": 10
-                  },
-                  "PERI_BACKUP_SIZE": {
-                    "description": "reg_peri_backup_size",
-                    "offset": 19,
-                    "size": 10
-                  },
-                  "PERI_BACKUP_START": {
-                    "description": "reg_peri_backup_start",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PERI_BACKUP_TO_MEM": {
-                    "description": "reg_peri_backup_to_mem",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "PERI_BACKUP_ENA": {
-                    "description": "reg_peri_backup_ena",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_APB_ADDR": {
-              "description": "APB_CTRL_PERI_BACKUP_APB_ADDR_REG",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_APB_START_ADDR": {
-                    "description": "reg_backup_apb_start_addr",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_MEM_ADDR": {
-              "description": "APB_CTRL_PERI_BACKUP_MEM_ADDR_REG",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_MEM_START_ADDR": {
-                    "description": "reg_backup_mem_start_addr",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_INT_RAW": {
-              "description": "APB_CTRL_PERI_BACKUP_INT_RAW_REG",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_BACKUP_DONE_INT_RAW": {
-                    "description": "reg_peri_backup_done_int_raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PERI_BACKUP_ERR_INT_RAW": {
-                    "description": "reg_peri_backup_err_int_raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_INT_ST": {
-              "description": "APB_CTRL_PERI_BACKUP_INT_ST_REG",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_BACKUP_DONE_INT_ST": {
-                    "description": "reg_peri_backup_done_int_st",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PERI_BACKUP_ERR_INT_ST": {
-                    "description": "reg_peri_backup_err_int_st",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_INT_ENA": {
-              "description": "APB_CTRL_PERI_BACKUP_INT_ENA_REG",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_BACKUP_DONE_INT_ENA": {
-                    "description": "reg_peri_backup_done_int_ena",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PERI_BACKUP_ERR_INT_ENA": {
-                    "description": "reg_peri_backup_err_int_ena",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERI_BACKUP_INT_CLR": {
-              "description": "APB_CTRL_PERI_BACKUP_INT_CLR_REG",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_BACKUP_DONE_INT_CLR": {
-                    "description": "reg_peri_backup_done_int_clr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PERI_BACKUP_ERR_INT_CLR": {
-                    "description": "reg_peri_backup_err_int_clr",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "APB_CTRL_DATE_REG",
-              "offset": 1020,
-              "size": 32,
-              "reset_value": 33583632,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "reg_dateVersion control",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "APB_SARADC": {
-        "description": "Successive Approximation Register Analog to Digital Converter",
-        "children": {
-          "registers": {
-            "CTRL": {
-              "description": "digital saradc configure register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1073971776,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_START_FORCE": {
-                    "description": "select software enable saradc sample",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SARADC_START": {
-                    "description": "software enable saradc sample",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SARADC_SAR_CLK_GATED": {
-                    "description": "SAR clock gated",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SARADC_SAR_CLK_DIV": {
-                    "description": "SAR clock divider",
-                    "offset": 7,
-                    "size": 8
-                  },
-                  "SARADC_SAR_PATT_LEN": {
-                    "description": "0 ~ 15 means length 1 ~ 16",
-                    "offset": 15,
-                    "size": 3
-                  },
-                  "SARADC_SAR_PATT_P_CLEAR": {
-                    "description": "clear the pointer of pattern table for DIG ADC1 CTRL",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "SARADC_XPD_SAR_FORCE": {
-                    "description": "force option to xpd sar blocks",
-                    "offset": 27,
-                    "size": 2
-                  },
-                  "SARADC_WAIT_ARB_CYCLE": {
-                    "description": "wait arbit signal stable after sar_done",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CTRL2": {
-              "description": "digital saradc configure register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 41470,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_MEAS_NUM_LIMIT": {
-                    "description": "enable max meas num",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SARADC_MAX_MEAS_NUM": {
-                    "description": "max conversion number",
-                    "offset": 1,
-                    "size": 8
-                  },
-                  "SARADC_SAR1_INV": {
-                    "description": "1: data to DIG ADC1 CTRL is inverted, otherwise not",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "SARADC_SAR2_INV": {
-                    "description": "1: data to DIG ADC2 CTRL is inverted, otherwise not",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "SARADC_TIMER_TARGET": {
-                    "description": "to set saradc timer target",
-                    "offset": 12,
-                    "size": 12
-                  },
-                  "SARADC_TIMER_EN": {
-                    "description": "to enable saradc timer trigger",
-                    "offset": 24,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FILTER_CTRL1": {
-              "description": "digital saradc configure register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_FILTER_FACTOR1": {
-                    "description": "Factor of saradc filter1",
-                    "offset": 26,
-                    "size": 3
-                  },
-                  "APB_SARADC_FILTER_FACTOR0": {
-                    "description": "Factor of saradc filter0",
-                    "offset": 29,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "FSM_WAIT": {
-              "description": "digital saradc configure register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 16713736,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_XPD_WAIT": {
-                    "description": "saradc_xpd_wait",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "SARADC_RSTB_WAIT": {
-                    "description": "saradc_rstb_wait",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "SARADC_STANDBY_WAIT": {
-                    "description": "saradc_standby_wait",
-                    "offset": 16,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "SAR1_STATUS": {
-              "description": "digital saradc configure register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_SAR1_STATUS": {
-                    "description": "saradc1 status about data and channel",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SAR2_STATUS": {
-              "description": "digital saradc configure register",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_SAR2_STATUS": {
-                    "description": "saradc2 status about data and channel",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SAR_PATT_TAB1": {
-              "description": "digital saradc configure register",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_SAR_PATT_TAB1": {
-                    "description": "item 0 ~ 3 for pattern table 1 (each item one byte)",
-                    "offset": 0,
-                    "size": 24
-                  }
-                }
-              }
-            },
-            "SAR_PATT_TAB2": {
-              "description": "digital saradc configure register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_SAR_PATT_TAB2": {
-                    "description": "Item 4 ~ 7 for pattern table 1 (each item one byte)",
-                    "offset": 0,
-                    "size": 24
-                  }
-                }
-              }
-            },
-            "ONETIME_SAMPLE": {
-              "description": "digital saradc configure register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 436207616,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SARADC_ONETIME_ATTEN": {
-                    "description": "configure onetime atten",
-                    "offset": 23,
-                    "size": 2
-                  },
-                  "SARADC_ONETIME_CHANNEL": {
-                    "description": "configure onetime channel",
-                    "offset": 25,
-                    "size": 4
-                  },
-                  "SARADC_ONETIME_START": {
-                    "description": "trigger adc onetime sample",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "SARADC2_ONETIME_SAMPLE": {
-                    "description": "enable adc2 onetime sample",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SARADC1_ONETIME_SAMPLE": {
-                    "description": "enable adc1 onetime sample",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ARB_CTRL": {
-              "description": "digital saradc configure register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 2304,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ADC_ARB_APB_FORCE": {
-                    "description": "adc2 arbiter force to enableapb controller",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "ADC_ARB_RTC_FORCE": {
-                    "description": "adc2 arbiter force to enable rtc controller",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "ADC_ARB_WIFI_FORCE": {
-                    "description": "adc2 arbiter force to enable wifi controller",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "ADC_ARB_GRANT_FORCE": {
-                    "description": "adc2 arbiter force grant",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "ADC_ARB_APB_PRIORITY": {
-                    "description": "Set adc2 arbiterapb priority",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "ADC_ARB_RTC_PRIORITY": {
-                    "description": "Set adc2 arbiter rtc priority",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "ADC_ARB_WIFI_PRIORITY": {
-                    "description": "Set adc2 arbiter wifi priority",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "ADC_ARB_FIX_PRIORITY": {
-                    "description": "adc2 arbiter uses fixed priority",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FILTER_CTRL0": {
-              "description": "digital saradc configure register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 57933824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_FILTER_CHANNEL1": {
-                    "description": "configure filter1 to adc channel",
-                    "offset": 18,
-                    "size": 4
-                  },
-                  "APB_SARADC_FILTER_CHANNEL0": {
-                    "description": "configure filter0 to adc channel",
-                    "offset": 22,
-                    "size": 4
-                  },
-                  "APB_SARADC_FILTER_RESET": {
-                    "description": "enable apb_adc1_filter",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SAR1DATA_STATUS": {
-              "description": "digital saradc configure register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC1_DATA": {
-                    "description": "saradc1 data",
-                    "offset": 0,
-                    "size": 17,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SAR2DATA_STATUS": {
-              "description": "digital saradc configure register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC2_DATA": {
-                    "description": "saradc2 data",
-                    "offset": 0,
-                    "size": 17,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "THRES0_CTRL": {
-              "description": "digital saradc configure register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 262125,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES0_CHANNEL": {
-                    "description": "configure thres0 to adc channel",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "APB_SARADC_THRES0_HIGH": {
-                    "description": "saradc thres0 monitor thres",
-                    "offset": 5,
-                    "size": 13
-                  },
-                  "APB_SARADC_THRES0_LOW": {
-                    "description": "saradc thres0 monitor thres",
-                    "offset": 18,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "THRES1_CTRL": {
-              "description": "digital saradc configure register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 262125,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES1_CHANNEL": {
-                    "description": "configure thres1 to adc channel",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "APB_SARADC_THRES1_HIGH": {
-                    "description": "saradc thres1 monitor thres",
-                    "offset": 5,
-                    "size": 13
-                  },
-                  "APB_SARADC_THRES1_LOW": {
-                    "description": "saradc thres1 monitor thres",
-                    "offset": 18,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "THRES_CTRL": {
-              "description": "digital saradc configure register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES_ALL_EN": {
-                    "description": "enable thres to all channel",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "APB_SARADC_THRES1_EN": {
-                    "description": "enable thres1",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "APB_SARADC_THRES0_EN": {
-                    "description": "enable thres0",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "digital saradc int register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES1_LOW_INT_ENA": {
-                    "description": "saradc thres1 low  interrupt enable",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "APB_SARADC_THRES0_LOW_INT_ENA": {
-                    "description": "saradc thres0 low interrupt enable",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "APB_SARADC_THRES1_HIGH_INT_ENA": {
-                    "description": "saradc thres1 high interrupt enable",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "APB_SARADC_THRES0_HIGH_INT_ENA": {
-                    "description": "saradc thres0 high interrupt enable",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "APB_SARADC2_DONE_INT_ENA": {
-                    "description": "saradc2 done interrupt enable",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "APB_SARADC1_DONE_INT_ENA": {
-                    "description": "saradc1 done interrupt enable",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "digital saradc int register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES1_LOW_INT_RAW": {
-                    "description": "saradc thres1 low  interrupt raw",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES0_LOW_INT_RAW": {
-                    "description": "saradc thres0 low interrupt raw",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES1_HIGH_INT_RAW": {
-                    "description": "saradc thres1 high interrupt raw",
-                    "offset": 28,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES0_HIGH_INT_RAW": {
-                    "description": "saradc thres0 high interrupt raw",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC2_DONE_INT_RAW": {
-                    "description": "saradc2 done interrupt raw",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC1_DONE_INT_RAW": {
-                    "description": "saradc1 done interrupt raw",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "digital saradc int register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES1_LOW_INT_ST": {
-                    "description": "saradc thres1 low  interrupt state",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES0_LOW_INT_ST": {
-                    "description": "saradc thres0 low interrupt state",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES1_HIGH_INT_ST": {
-                    "description": "saradc thres1 high interrupt state",
-                    "offset": 28,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC_THRES0_HIGH_INT_ST": {
-                    "description": "saradc thres0 high interrupt state",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC2_DONE_INT_ST": {
-                    "description": "saradc2 done interrupt state",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_SARADC1_DONE_INT_ST": {
-                    "description": "saradc1 done interrupt state",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "digital saradc int register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_THRES1_LOW_INT_CLR": {
-                    "description": "saradc thres1 low  interrupt clear",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_SARADC_THRES0_LOW_INT_CLR": {
-                    "description": "saradc thres0 low interrupt clear",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_SARADC_THRES1_HIGH_INT_CLR": {
-                    "description": "saradc thres1 high interrupt clear",
-                    "offset": 28,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_SARADC_THRES0_HIGH_INT_CLR": {
-                    "description": "saradc thres0 high interrupt clear",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_SARADC2_DONE_INT_CLR": {
-                    "description": "saradc2 done interrupt clear",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_SARADC1_DONE_INT_CLR": {
-                    "description": "saradc1 done interrupt clear",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DMA_CONF": {
-              "description": "digital saradc configure register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 255,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_ADC_EOF_NUM": {
-                    "description": "the dma_in_suc_eof gen when sample cnt = spi_eof_num",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "APB_ADC_RESET_FSM": {
-                    "description": "reset_apb_adc_state",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "APB_ADC_TRANS": {
-                    "description": "enable apb_adc use spi_dma",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLKM_CONF": {
-              "description": "digital saradc configure register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 4,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLKM_DIV_NUM": {
-                    "description": "Integral I2S clock divider value",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CLKM_DIV_B": {
-                    "description": "Fractional clock divider numerator value",
-                    "offset": 8,
-                    "size": 6
-                  },
-                  "CLKM_DIV_A": {
-                    "description": "Fractional clock divider denominator value",
-                    "offset": 14,
-                    "size": 6
-                  },
-                  "CLK_EN": {
-                    "description": "reg clk en",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "CLK_SEL": {
-                    "description": "Set this bit to enable clk_apll",
-                    "offset": 21,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "APB_TSENS_CTRL": {
-              "description": "digital tsens configure register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 98304,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TSENS_OUT": {
-                    "description": "temperature sensor data out",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "read-only"
-                  },
-                  "TSENS_IN_INV": {
-                    "description": "invert temperature sensor data",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "TSENS_CLK_DIV": {
-                    "description": "temperature sensor clock divider",
-                    "offset": 14,
-                    "size": 8
-                  },
-                  "TSENS_PU": {
-                    "description": "temperature sensor power up",
-                    "offset": 22,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TSENS_CTRL2": {
-              "description": "digital tsens configure register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 16386,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TSENS_XPD_WAIT": {
-                    "description": "the time that power up tsens need wait",
-                    "offset": 0,
-                    "size": 12
-                  },
-                  "TSENS_XPD_FORCE": {
-                    "description": "force power up tsens",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "TSENS_CLK_INV": {
-                    "description": "inv tsens clk",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "TSENS_CLK_SEL": {
-                    "description": "tsens clk select",
-                    "offset": 15,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CALI": {
-              "description": "digital saradc configure register",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 32768,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_SARADC_CALI_CFG": {
-                    "description": "saradc cali factor",
-                    "offset": 0,
-                    "size": 17
-                  }
-                }
-              }
-            },
-            "CTRL_DATE": {
-              "description": "version",
-              "offset": 1020,
-              "size": 32,
-              "reset_value": 33583473,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "version",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "ASSIST_DEBUG": {
-        "description": "Debug Assist",
-        "children": {
-          "registers": {
-            "C0RE_0_MONTR_ENA": {
-              "description": "ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_RD_ENA": {
-                    "description": "reg_core_0_area_dram0_0_rd_ena",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_0_WR_ENA": {
-                    "description": "reg_core_0_area_dram0_0_wr_ena",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_RD_ENA": {
-                    "description": "reg_core_0_area_dram0_1_rd_ena",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_WR_ENA": {
-                    "description": "reg_core_0_area_dram0_1_wr_ena",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_RD_ENA": {
-                    "description": "reg_core_0_area_pif_0_rd_ena",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_WR_ENA": {
-                    "description": "reg_core_0_area_pif_0_wr_ena",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_RD_ENA": {
-                    "description": "reg_core_0_area_pif_1_rd_ena",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_WR_ENA": {
-                    "description": "reg_core_0_area_pif_1_wr_ena",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MIN_ENA": {
-                    "description": "reg_core_0_sp_spill_min_ena",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MAX_ENA": {
-                    "description": "reg_core_0_sp_spill_max_ena",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CORE_0_IRAM0_EXCEPTION_MONITOR_ENA": {
-                    "description": "reg_core_0_iram0_exception_monitor_ena",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CORE_0_DRAM0_EXCEPTION_MONITOR_ENA": {
-                    "description": "reg_core_0_dram0_exception_monitor_ena",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_INTR_RAW": {
-              "description": "ASSIST_DEBUG_CORE_0_INTR_RAW_REG",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_RD_RAW": {
-                    "description": "reg_core_0_area_dram0_0_rd_raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_DRAM0_0_WR_RAW": {
-                    "description": "reg_core_0_area_dram0_0_wr_raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_DRAM0_1_RD_RAW": {
-                    "description": "reg_core_0_area_dram0_1_rd_raw",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_DRAM0_1_WR_RAW": {
-                    "description": "reg_core_0_area_dram0_1_wr_raw",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_PIF_0_RD_RAW": {
-                    "description": "reg_core_0_area_pif_0_rd_raw",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_PIF_0_WR_RAW": {
-                    "description": "reg_core_0_area_pif_0_wr_raw",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_PIF_1_RD_RAW": {
-                    "description": "reg_core_0_area_pif_1_rd_raw",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_AREA_PIF_1_WR_RAW": {
-                    "description": "reg_core_0_area_pif_1_wr_raw",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_SP_SPILL_MIN_RAW": {
-                    "description": "reg_core_0_sp_spill_min_raw",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_SP_SPILL_MAX_RAW": {
-                    "description": "reg_core_0_sp_spill_max_raw",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_EXCEPTION_MONITOR_RAW": {
-                    "description": "reg_core_0_iram0_exception_monitor_raw",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_EXCEPTION_MONITOR_RAW": {
-                    "description": "reg_core_0_dram0_exception_monitor_raw",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_INTR_ENA": {
-              "description": "ASSIST_DEBUG_CORE_0_INTR_ENA_REG",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_RD_INTR_ENA": {
-                    "description": "reg_core_0_area_dram0_0_rd_intr_ena",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_0_WR_INTR_ENA": {
-                    "description": "reg_core_0_area_dram0_0_wr_intr_ena",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_RD_INTR_ENA": {
-                    "description": "reg_core_0_area_dram0_1_rd_intr_ena",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_WR_INTR_ENA": {
-                    "description": "reg_core_0_area_dram0_1_wr_intr_ena",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_RD_INTR_ENA": {
-                    "description": "reg_core_0_area_pif_0_rd_intr_ena",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_WR_INTR_ENA": {
-                    "description": "reg_core_0_area_pif_0_wr_intr_ena",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_RD_INTR_ENA": {
-                    "description": "reg_core_0_area_pif_1_rd_intr_ena",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_WR_INTR_ENA": {
-                    "description": "reg_core_0_area_pif_1_wr_intr_ena",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MIN_INTR_ENA": {
-                    "description": "reg_core_0_sp_spill_min_intr_ena",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MAX_INTR_ENA": {
-                    "description": "reg_core_0_sp_spill_max_intr_ena",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CORE_0_IRAM0_EXCEPTION_MONITOR_RLS": {
-                    "description": "reg_core_0_iram0_exception_monitor_ena",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CORE_0_DRAM0_EXCEPTION_MONITOR_RLS": {
-                    "description": "reg_core_0_dram0_exception_monitor_ena",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_INTR_CLR": {
-              "description": "ASSIST_DEBUG_CORE_0_INTR_CLR_REG",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_RD_CLR": {
-                    "description": "reg_core_0_area_dram0_0_rd_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_0_WR_CLR": {
-                    "description": "reg_core_0_area_dram0_0_wr_clr",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_RD_CLR": {
-                    "description": "reg_core_0_area_dram0_1_rd_clr",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_DRAM0_1_WR_CLR": {
-                    "description": "reg_core_0_area_dram0_1_wr_clr",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_RD_CLR": {
-                    "description": "reg_core_0_area_pif_0_rd_clr",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_0_WR_CLR": {
-                    "description": "reg_core_0_area_pif_0_wr_clr",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_RD_CLR": {
-                    "description": "reg_core_0_area_pif_1_rd_clr",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CORE_0_AREA_PIF_1_WR_CLR": {
-                    "description": "reg_core_0_area_pif_1_wr_clr",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MIN_CLR": {
-                    "description": "reg_core_0_sp_spill_min_clr",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "CORE_0_SP_SPILL_MAX_CLR": {
-                    "description": "reg_core_0_sp_spill_max_clr",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CORE_0_IRAM0_EXCEPTION_MONITOR_CLR": {
-                    "description": "reg_core_0_iram0_exception_monitor_clr",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CORE_0_DRAM0_EXCEPTION_MONITOR_CLR": {
-                    "description": "reg_core_0_dram0_exception_monitor_clr",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_DRAM0_0_MIN": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_MIN": {
-                    "description": "reg_core_0_area_dram0_0_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_DRAM0_0_MAX": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_0_MAX": {
-                    "description": "reg_core_0_area_dram0_0_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_DRAM0_1_MIN": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_1_MIN": {
-                    "description": "reg_core_0_area_dram0_1_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_DRAM0_1_MAX": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_DRAM0_1_MAX": {
-                    "description": "reg_core_0_area_dram0_1_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_PIF_0_MIN": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_PIF_0_MIN": {
-                    "description": "reg_core_0_area_pif_0_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_PIF_0_MAX": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_PIF_0_MAX": {
-                    "description": "reg_core_0_area_pif_0_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_PIF_1_MIN": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_PIF_1_MIN": {
-                    "description": "reg_core_0_area_pif_1_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_PIF_1_MAX": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_PIF_1_MAX": {
-                    "description": "reg_core_0_area_pif_1_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_PC": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_PC_REG",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_PC": {
-                    "description": "reg_core_0_area_pc",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_AREA_SP": {
-              "description": "ASSIST_DEBUG_CORE_0_AREA_SP_REG",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_AREA_SP": {
-                    "description": "reg_core_0_area_sp",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_SP_MIN": {
-              "description": "ASSIST_DEBUG_CORE_0_SP_MIN_REG",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_SP_MIN": {
-                    "description": "reg_core_0_sp_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_SP_MAX": {
-              "description": "ASSIST_DEBUG_CORE_0_SP_MAX_REG",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_SP_MAX": {
-                    "description": "reg_core_0_sp_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CORE_0_SP_PC": {
-              "description": "ASSIST_DEBUG_CORE_0_SP_PC_REG",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_SP_PC": {
-                    "description": "reg_core_0_sp_pc",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_RCD_EN": {
-              "description": "ASSIST_DEBUG_CORE_0_RCD_EN_REG",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_RCD_RECORDEN": {
-                    "description": "reg_core_0_rcd_recorden",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_RCD_PDEBUGEN": {
-                    "description": "reg_core_0_rcd_pdebugen",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_RCD_PDEBUGPC": {
-              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_RCD_PDEBUGPC": {
-                    "description": "reg_core_0_rcd_pdebugpc",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_RCD_PDEBUGSP": {
-              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_RCD_PDEBUGSP": {
-                    "description": "reg_core_0_rcd_pdebugsp",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_EXCEPTION_MONITOR_0": {
-              "description": "ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_RECORDING_ADDR_0": {
-                    "description": "reg_core_0_iram0_recording_addr_0",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_RECORDING_WR_0": {
-                    "description": "reg_core_0_iram0_recording_wr_0",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_RECORDING_LOADSTORE_0": {
-                    "description": "reg_core_0_iram0_recording_loadstore_0",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_EXCEPTION_MONITOR_1": {
-              "description": "ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_RECORDING_ADDR_1": {
-                    "description": "reg_core_0_iram0_recording_addr_1",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_RECORDING_WR_1": {
-                    "description": "reg_core_0_iram0_recording_wr_1",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_RECORDING_LOADSTORE_1": {
-                    "description": "reg_core_0_iram0_recording_loadstore_1",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_EXCEPTION_MONITOR_0": {
-              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_RECORDING_ADDR_0": {
-                    "description": "reg_core_0_dram0_recording_addr_0",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_RECORDING_WR_0": {
-                    "description": "reg_core_0_dram0_recording_wr_0",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_RECORDING_BYTEEN_0": {
-                    "description": "reg_core_0_dram0_recording_byteen_0",
-                    "offset": 25,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_EXCEPTION_MONITOR_1": {
-              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_RECORDING_PC_0": {
-                    "description": "reg_core_0_dram0_recording_pc_0",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_EXCEPTION_MONITOR_2": {
-              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_RECORDING_ADDR_1": {
-                    "description": "reg_core_0_dram0_recording_addr_1",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_RECORDING_WR_1": {
-                    "description": "reg_core_0_dram0_recording_wr_1",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_RECORDING_BYTEEN_1": {
-                    "description": "reg_core_0_dram0_recording_byteen_1",
-                    "offset": 25,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_EXCEPTION_MONITOR_3": {
-              "description": "ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_RECORDING_PC_1": {
-                    "description": "reg_core_0_dram0_recording_pc_1",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0": {
-              "description": "ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0": {
-                    "description": "reg_core_x_iram0_dram0_limit_cycle_0",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1": {
-              "description": "ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1": {
-                    "description": "reg_core_x_iram0_dram0_limit_cycle_1",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "LOG_SETTING": {
-              "description": "ASSIST_DEBUG_LOG_SETTING",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 128,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_ENA": {
-                    "description": "reg_log_ena",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "LOG_MODE": {
-                    "description": "reg_log_mode",
-                    "offset": 3,
-                    "size": 4
-                  },
-                  "LOG_MEM_LOOP_ENABLE": {
-                    "description": "reg_log_mem_loop_enable",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LOG_DATA_0": {
-              "description": "ASSIST_DEBUG_LOG_DATA_0_REG",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_DATA_0": {
-                    "description": "reg_log_data_0",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOG_DATA_MASK": {
-              "description": "ASSIST_DEBUG_LOG_DATA_MASK_REG",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_DATA_SIZE": {
-                    "description": "reg_log_data_size",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "LOG_MIN": {
-              "description": "ASSIST_DEBUG_LOG_MIN_REG",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MIN": {
-                    "description": "reg_log_min",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOG_MAX": {
-              "description": "ASSIST_DEBUG_LOG_MAX_REG",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MAX": {
-                    "description": "reg_log_max",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOG_MEM_START": {
-              "description": "ASSIST_DEBUG_LOG_MEM_START_REG",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MEM_START": {
-                    "description": "reg_log_mem_start",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOG_MEM_END": {
-              "description": "ASSIST_DEBUG_LOG_MEM_END_REG",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MEM_END": {
-                    "description": "reg_log_mem_end",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOG_MEM_WRITING_ADDR": {
-              "description": "ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MEM_WRITING_ADDR": {
-                    "description": "reg_log_mem_writing_addr",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LOG_MEM_FULL_FLAG": {
-              "description": "ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LOG_MEM_FULL_FLAG": {
-                    "description": "reg_log_mem_full_flag",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CLR_LOG_MEM_FULL_FLAG": {
-                    "description": "reg_clr_log_mem_full_flag",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "C0RE_0_LASTPC_BEFORE_EXCEPTION": {
-              "description": "ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_LASTPC_BEFORE_EXC": {
-                    "description": "reg_core_0_lastpc_before_exc",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "C0RE_0_DEBUG_MODE": {
-              "description": "ASSIST_DEBUG_C0RE_0_DEBUG_MODE",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DEBUG_MODE": {
-                    "description": "reg_core_0_debug_mode",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DEBUG_MODULE_ACTIVE": {
-                    "description": "reg_core_0_debug_module_active",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "ASSIST_DEBUG_DATE_REG",
-              "offset": 508,
-              "size": 32,
-              "reset_value": 33587216,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ASSIST_DEBUG_DATE": {
-                    "description": "reg_assist_debug_date",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "DMA": {
-        "description": "DMA (Direct Memory Access) Controller",
-        "children": {
-          "registers": {
-            "INT_RAW_CH0": {
-              "description": "DMA_INT_RAW_CH0_REG.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH0_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH0_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH0_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH0_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH0_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST_CH0": {
-              "description": "DMA_INT_ST_CH0_REG.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH0_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA_CH0": {
-              "description": "DMA_INT_ENA_CH0_REG.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_SUC_EOF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "IN_ERR_EOF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_DONE_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUT_EOF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "IN_DSCR_ERR_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "OUT_DSCR_ERR_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "IN_DSCR_EMPTY_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "OUT_TOTAL_EOF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "INFIFO_OVF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "INFIFO_UDF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "OUTFIFO_OVF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "OUTFIFO_UDF_CH0_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR_CH0": {
-              "description": "DMA_INT_CLR_CH0_REG.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_SUC_EOF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_ERR_EOF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DONE_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_EOF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_ERR_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DSCR_ERR_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_EMPTY_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_TOTAL_EOF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_OVF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_UDF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_OVF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_UDF_CH0_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW_CH1": {
-              "description": "DMA_INT_RAW_CH1_REG.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH1_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH1_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH1_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH1_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST_CH1": {
-              "description": "DMA_INT_ST_CH1_REG.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH1_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA_CH1": {
-              "description": "DMA_INT_ENA_CH1_REG.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_SUC_EOF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "IN_ERR_EOF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_DONE_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUT_EOF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "IN_DSCR_ERR_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "OUT_DSCR_ERR_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "IN_DSCR_EMPTY_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "OUT_TOTAL_EOF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "INFIFO_OVF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "INFIFO_UDF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "OUTFIFO_OVF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "OUTFIFO_UDF_CH1_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR_CH1": {
-              "description": "DMA_INT_CLR_CH1_REG.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_SUC_EOF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_ERR_EOF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DONE_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_EOF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_ERR_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DSCR_ERR_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_EMPTY_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_TOTAL_EOF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_OVF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_UDF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_OVF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_UDF_CH1_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW_CH2": {
-              "description": "DMA_INT_RAW_CH2_REG.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH2_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH2_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH2_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH2_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH2_INT_RAW": {
-                    "description": "This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST_CH2": {
-              "description": "DMA_INT_ST_CH2_REG.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_SUC_EOF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_ERR_EOF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DONE_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_ERR_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_ERR_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_EMPTY_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_TOTAL_EOF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_OVF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_UDF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_OVF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_UDF_CH2_INT_ST": {
-                    "description": "The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA_CH2": {
-              "description": "DMA_INT_ENA_CH2_REG.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_SUC_EOF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "IN_ERR_EOF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_DONE_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUT_EOF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "IN_DSCR_ERR_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "OUT_DSCR_ERR_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "IN_DSCR_EMPTY_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "OUT_TOTAL_EOF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "INFIFO_OVF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "INFIFO_UDF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "OUTFIFO_OVF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "OUTFIFO_UDF_CH2_INT_ENA": {
-                    "description": "The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR_CH2": {
-              "description": "DMA_INT_CLR_CH2_REG.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_DONE_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DONE_CH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_SUC_EOF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_ERR_EOF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DONE_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DONE_CH_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_EOF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_EOF_CH_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_ERR_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_DSCR_ERR_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_DSCR_EMPTY_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_TOTAL_EOF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_OVF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "INFIFO_UDF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_OVF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTFIFO_UDF_CH2_INT_CLR": {
-                    "description": "Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "AHB_TEST": {
-              "description": "DMA_AHB_TEST_REG.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AHB_TESTMODE": {
-                    "description": "reserved",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "AHB_TESTADDR": {
-                    "description": "reserved",
-                    "offset": 4,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "MISC_CONF": {
-              "description": "DMA_MISC_CONF_REG.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AHBM_RST_INTER": {
-                    "description": "Set this bit, then clear this bit to reset the internal ahb FSM.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ARB_PRI_DIS": {
-                    "description": "Set this bit to disable priority arbitration function.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "DMA_DATE_REG.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 33587792,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "register version.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "IN_CONF0_CH0": {
-              "description": "DMA_IN_CONF0_CH0_REG.",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_RST_CH0": {
-                    "description": "This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_LOOP_TEST_CH0": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "INDSCR_BURST_EN_CH0": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IN_DATA_BURST_EN_CH0": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MEM_TRANS_EN_CH0": {
-                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
-                    "offset": 4,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_CONF1_CH0": {
-              "description": "DMA_IN_CONF1_CH0_REG.",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_CHECK_OWNER_CH0": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INFIFO_STATUS_CH0": {
-              "description": "DMA_INFIFO_STATUS_CH0_REG.",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 125829123,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_FULL_CH0": {
-                    "description": "L1 Rx FIFO full signal for Rx channel 0.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_EMPTY_CH0": {
-                    "description": "L1 Rx FIFO empty signal for Rx channel 0.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_CNT_CH0": {
-                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_1B_CH0": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_2B_CH0": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_3B_CH0": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_4B_CH0": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_BUF_HUNGRY_CH0": {
-                    "description": "reserved",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_POP_CH0": {
-              "description": "DMA_IN_POP_CH0_REG.",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_RDATA_CH0": {
-                    "description": "This register stores the data popping from DMA FIFO.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  },
-                  "INFIFO_POP_CH0": {
-                    "description": "Set this bit to pop data from DMA FIFO.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_LINK_CH0": {
-              "description": "DMA_IN_LINK_CH0_REG.",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 17825792,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_ADDR_CH0": {
-                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "INLINK_AUTO_RET_CH0": {
-                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "INLINK_STOP_CH0": {
-                    "description": "Set this bit to stop dealing with the inlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "INLINK_START_CH0": {
-                    "description": "Set this bit to start dealing with the inlink descriptors.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "INLINK_RESTART_CH0": {
-                    "description": "Set this bit to mount a new inlink descriptor.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "INLINK_PARK_CH0": {
-                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_STATE_CH0": {
-              "description": "DMA_IN_STATE_CH0_REG.",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_ADDR_CH0": {
-                    "description": "This register stores the current inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_STATE_CH0": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_STATE_CH0": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_SUC_EOF_DES_ADDR_CH0": {
-              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_SUC_EOF_DES_ADDR_CH0": {
-                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_ERR_EOF_DES_ADDR_CH0": {
-              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_ERR_EOF_DES_ADDR_CH0": {
-                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_CH0": {
-              "description": "DMA_IN_DSCR_CH0_REG.",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_CH0": {
-                    "description": "The address of the current inlink descriptor x.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF0_CH0": {
-              "description": "DMA_IN_DSCR_BF0_CH0_REG.",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF0_CH0": {
-                    "description": "The address of the last inlink descriptor x-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF1_CH0": {
-              "description": "DMA_IN_DSCR_BF1_CH0_REG.",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF1_CH0": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_PRI_CH0": {
-              "description": "DMA_IN_PRI_CH0_REG.",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_PRI_CH0": {
-                    "description": "The priority of Rx channel 0. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "IN_PERI_SEL_CH0": {
-              "description": "DMA_IN_PERI_SEL_CH0_REG.",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_IN_SEL_CH0": {
-                    "description": "This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "OUT_CONF0_CH0": {
-              "description": "DMA_OUT_CONF0_CH0_REG.",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_RST_CH0": {
-                    "description": "This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "OUT_LOOP_TEST_CH0": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "OUT_AUTO_WRBACK_CH0": {
-                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_EOF_MODE_CH0": {
-                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUTDSCR_BURST_EN_CH0": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "OUT_DATA_BURST_EN_CH0": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_CONF1_CH0": {
-              "description": "DMA_OUT_CONF1_CH0_REG.",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_CHECK_OWNER_CH0": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUTFIFO_STATUS_CH0": {
-              "description": "DMA_OUTFIFO_STATUS_CH0_REG.",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 125829122,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_FULL_CH0": {
-                    "description": "L1 Tx FIFO full signal for Tx channel 0.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_EMPTY_CH0": {
-                    "description": "L1 Tx FIFO empty signal for Tx channel 0.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_CNT_CH0": {
-                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_1B_CH0": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_2B_CH0": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_3B_CH0": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_4B_CH0": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PUSH_CH0": {
-              "description": "DMA_OUT_PUSH_CH0_REG.",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_WDATA_CH0": {
-                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "OUTFIFO_PUSH_CH0": {
-                    "description": "Set this bit to push data into DMA FIFO.",
-                    "offset": 9,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_LINK_CH0": {
-              "description": "DMA_OUT_LINK_CH0_REG.",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_ADDR_CH0": {
-                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "OUTLINK_STOP_CH0": {
-                    "description": "Set this bit to stop dealing with the outlink descriptors.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "OUTLINK_START_CH0": {
-                    "description": "Set this bit to start dealing with the outlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "OUTLINK_RESTART_CH0": {
-                    "description": "Set this bit to restart a new outlink from the last address.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "OUTLINK_PARK_CH0": {
-                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_STATE_CH0": {
-              "description": "DMA_OUT_STATE_CH0_REG.",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_ADDR_CH0": {
-                    "description": "This register stores the current outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_STATE_CH0": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_STATE_CH0": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_DES_ADDR_CH0": {
-              "description": "DMA_OUT_EOF_DES_ADDR_CH0_REG.",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_DES_ADDR_CH0": {
-                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_BFR_DES_ADDR_CH0": {
-              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_BFR_DES_ADDR_CH0": {
-                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_CH0": {
-              "description": "DMA_OUT_DSCR_CH0_REG.",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_CH0": {
-                    "description": "The address of the current outlink descriptor y.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF0_CH0": {
-              "description": "DMA_OUT_DSCR_BF0_CH0_REG.",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF0_CH0": {
-                    "description": "The address of the last outlink descriptor y-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF1_CH0": {
-              "description": "DMA_OUT_DSCR_BF1_CH0_REG.",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF1_CH0": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PRI_CH0": {
-              "description": "DMA_OUT_PRI_CH0_REG.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_PRI_CH0": {
-                    "description": "The priority of Tx channel 0. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "OUT_PERI_SEL_CH0": {
-              "description": "DMA_OUT_PERI_SEL_CH0_REG.",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_OUT_SEL_CH0": {
-                    "description": "This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "IN_CONF0_CH1": {
-              "description": "DMA_IN_CONF0_CH1_REG.",
-              "offset": 304,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_RST_CH1": {
-                    "description": "This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_LOOP_TEST_CH1": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "INDSCR_BURST_EN_CH1": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IN_DATA_BURST_EN_CH1": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MEM_TRANS_EN_CH1": {
-                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
-                    "offset": 4,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_CONF1_CH1": {
-              "description": "DMA_IN_CONF1_CH1_REG.",
-              "offset": 308,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_CHECK_OWNER_CH1": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INFIFO_STATUS_CH1": {
-              "description": "DMA_INFIFO_STATUS_CH1_REG.",
-              "offset": 312,
-              "size": 32,
-              "reset_value": 125829123,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_FULL_CH1": {
-                    "description": "L1 Rx FIFO full signal for Rx channel 1.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_EMPTY_CH1": {
-                    "description": "L1 Rx FIFO empty signal for Rx channel 1.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_CNT_CH1": {
-                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_1B_CH1": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_2B_CH1": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_3B_CH1": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_4B_CH1": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_BUF_HUNGRY_CH1": {
-                    "description": "reserved",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_POP_CH1": {
-              "description": "DMA_IN_POP_CH1_REG.",
-              "offset": 316,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_RDATA_CH1": {
-                    "description": "This register stores the data popping from DMA FIFO.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  },
-                  "INFIFO_POP_CH1": {
-                    "description": "Set this bit to pop data from DMA FIFO.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_LINK_CH1": {
-              "description": "DMA_IN_LINK_CH1_REG.",
-              "offset": 320,
-              "size": 32,
-              "reset_value": 17825792,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_ADDR_CH1": {
-                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "INLINK_AUTO_RET_CH1": {
-                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "INLINK_STOP_CH1": {
-                    "description": "Set this bit to stop dealing with the inlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "INLINK_START_CH1": {
-                    "description": "Set this bit to start dealing with the inlink descriptors.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "INLINK_RESTART_CH1": {
-                    "description": "Set this bit to mount a new inlink descriptor.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "INLINK_PARK_CH1": {
-                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_STATE_CH1": {
-              "description": "DMA_IN_STATE_CH1_REG.",
-              "offset": 324,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_ADDR_CH1": {
-                    "description": "This register stores the current inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_STATE_CH1": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_STATE_CH1": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_SUC_EOF_DES_ADDR_CH1": {
-              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.",
-              "offset": 328,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_SUC_EOF_DES_ADDR_CH1": {
-                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_ERR_EOF_DES_ADDR_CH1": {
-              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.",
-              "offset": 332,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_ERR_EOF_DES_ADDR_CH1": {
-                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_CH1": {
-              "description": "DMA_IN_DSCR_CH1_REG.",
-              "offset": 336,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_CH1": {
-                    "description": "The address of the current inlink descriptor x.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF0_CH1": {
-              "description": "DMA_IN_DSCR_BF0_CH1_REG.",
-              "offset": 340,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF0_CH1": {
-                    "description": "The address of the last inlink descriptor x-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF1_CH1": {
-              "description": "DMA_IN_DSCR_BF1_CH1_REG.",
-              "offset": 344,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF1_CH1": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_PRI_CH1": {
-              "description": "DMA_IN_PRI_CH1_REG.",
-              "offset": 348,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_PRI_CH1": {
-                    "description": "The priority of Rx channel 1. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "IN_PERI_SEL_CH1": {
-              "description": "DMA_IN_PERI_SEL_CH1_REG.",
-              "offset": 352,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_IN_SEL_CH1": {
-                    "description": "This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "OUT_CONF0_CH1": {
-              "description": "DMA_OUT_CONF0_CH1_REG.",
-              "offset": 400,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_RST_CH1": {
-                    "description": "This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "OUT_LOOP_TEST_CH1": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "OUT_AUTO_WRBACK_CH1": {
-                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_EOF_MODE_CH1": {
-                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUTDSCR_BURST_EN_CH1": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "OUT_DATA_BURST_EN_CH1": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_CONF1_CH1": {
-              "description": "DMA_OUT_CONF1_CH1_REG.",
-              "offset": 404,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_CHECK_OWNER_CH1": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUTFIFO_STATUS_CH1": {
-              "description": "DMA_OUTFIFO_STATUS_CH1_REG.",
-              "offset": 408,
-              "size": 32,
-              "reset_value": 125829122,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_FULL_CH1": {
-                    "description": "L1 Tx FIFO full signal for Tx channel 1.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_EMPTY_CH1": {
-                    "description": "L1 Tx FIFO empty signal for Tx channel 1.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_CNT_CH1": {
-                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_1B_CH1": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_2B_CH1": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_3B_CH1": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_4B_CH1": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PUSH_CH1": {
-              "description": "DMA_OUT_PUSH_CH1_REG.",
-              "offset": 412,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_WDATA_CH1": {
-                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "OUTFIFO_PUSH_CH1": {
-                    "description": "Set this bit to push data into DMA FIFO.",
-                    "offset": 9,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_LINK_CH1": {
-              "description": "DMA_OUT_LINK_CH1_REG.",
-              "offset": 416,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_ADDR_CH1": {
-                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "OUTLINK_STOP_CH1": {
-                    "description": "Set this bit to stop dealing with the outlink descriptors.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "OUTLINK_START_CH1": {
-                    "description": "Set this bit to start dealing with the outlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "OUTLINK_RESTART_CH1": {
-                    "description": "Set this bit to restart a new outlink from the last address.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "OUTLINK_PARK_CH1": {
-                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_STATE_CH1": {
-              "description": "DMA_OUT_STATE_CH1_REG.",
-              "offset": 420,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_ADDR_CH1": {
-                    "description": "This register stores the current outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_STATE_CH1": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_STATE_CH1": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_DES_ADDR_CH1": {
-              "description": "DMA_OUT_EOF_DES_ADDR_CH1_REG.",
-              "offset": 424,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_DES_ADDR_CH1": {
-                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_BFR_DES_ADDR_CH1": {
-              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.",
-              "offset": 428,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_BFR_DES_ADDR_CH1": {
-                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_CH1": {
-              "description": "DMA_OUT_DSCR_CH1_REG.",
-              "offset": 432,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_CH1": {
-                    "description": "The address of the current outlink descriptor y.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF0_CH1": {
-              "description": "DMA_OUT_DSCR_BF0_CH1_REG.",
-              "offset": 436,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF0_CH1": {
-                    "description": "The address of the last outlink descriptor y-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF1_CH1": {
-              "description": "DMA_OUT_DSCR_BF1_CH1_REG.",
-              "offset": 440,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF1_CH1": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PRI_CH1": {
-              "description": "DMA_OUT_PRI_CH1_REG.",
-              "offset": 444,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_PRI_CH1": {
-                    "description": "The priority of Tx channel 1. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "OUT_PERI_SEL_CH1": {
-              "description": "DMA_OUT_PERI_SEL_CH1_REG.",
-              "offset": 448,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_OUT_SEL_CH1": {
-                    "description": "This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "IN_CONF0_CH2": {
-              "description": "DMA_IN_CONF0_CH2_REG.",
-              "offset": 496,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_RST_CH2": {
-                    "description": "This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "IN_LOOP_TEST_CH2": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "INDSCR_BURST_EN_CH2": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IN_DATA_BURST_EN_CH2": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MEM_TRANS_EN_CH2": {
-                    "description": "Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.",
-                    "offset": 4,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_CONF1_CH2": {
-              "description": "DMA_IN_CONF1_CH2_REG.",
-              "offset": 500,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_CHECK_OWNER_CH2": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INFIFO_STATUS_CH2": {
-              "description": "DMA_INFIFO_STATUS_CH2_REG.",
-              "offset": 504,
-              "size": 32,
-              "reset_value": 125829123,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_FULL_CH2": {
-                    "description": "L1 Rx FIFO full signal for Rx channel 2.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_EMPTY_CH2": {
-                    "description": "L1 Rx FIFO empty signal for Rx channel 2.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "INFIFO_CNT_CH2": {
-                    "description": "The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_1B_CH2": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_2B_CH2": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_3B_CH2": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_REMAIN_UNDER_4B_CH2": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_BUF_HUNGRY_CH2": {
-                    "description": "reserved",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_POP_CH2": {
-              "description": "DMA_IN_POP_CH2_REG.",
-              "offset": 508,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INFIFO_RDATA_CH2": {
-                    "description": "This register stores the data popping from DMA FIFO.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  },
-                  "INFIFO_POP_CH2": {
-                    "description": "Set this bit to pop data from DMA FIFO.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IN_LINK_CH2": {
-              "description": "DMA_IN_LINK_CH2_REG.",
-              "offset": 512,
-              "size": 32,
-              "reset_value": 17825792,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_ADDR_CH2": {
-                    "description": "This register stores the 20 least significant bits of the first inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "INLINK_AUTO_RET_CH2": {
-                    "description": "Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "INLINK_STOP_CH2": {
-                    "description": "Set this bit to stop dealing with the inlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "INLINK_START_CH2": {
-                    "description": "Set this bit to start dealing with the inlink descriptors.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "INLINK_RESTART_CH2": {
-                    "description": "Set this bit to mount a new inlink descriptor.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "INLINK_PARK_CH2": {
-                    "description": "1: the inlink descriptor's FSM is in idle state.  0: the inlink descriptor's FSM is working.",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_STATE_CH2": {
-              "description": "DMA_IN_STATE_CH2_REG.",
-              "offset": 516,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_ADDR_CH2": {
-                    "description": "This register stores the current inlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "IN_DSCR_STATE_CH2": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_STATE_CH2": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_SUC_EOF_DES_ADDR_CH2": {
-              "description": "DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.",
-              "offset": 520,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_SUC_EOF_DES_ADDR_CH2": {
-                    "description": "This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_ERR_EOF_DES_ADDR_CH2": {
-              "description": "DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.",
-              "offset": 524,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_ERR_EOF_DES_ADDR_CH2": {
-                    "description": "This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_CH2": {
-              "description": "DMA_IN_DSCR_CH2_REG.",
-              "offset": 528,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_CH2": {
-                    "description": "The address of the current inlink descriptor x.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF0_CH2": {
-              "description": "DMA_IN_DSCR_BF0_CH2_REG.",
-              "offset": 532,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF0_CH2": {
-                    "description": "The address of the last inlink descriptor x-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_DSCR_BF1_CH2": {
-              "description": "DMA_IN_DSCR_BF1_CH2_REG.",
-              "offset": 536,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INLINK_DSCR_BF1_CH2": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_PRI_CH2": {
-              "description": "DMA_IN_PRI_CH2_REG.",
-              "offset": 540,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_PRI_CH2": {
-                    "description": "The priority of Rx channel 2. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "IN_PERI_SEL_CH2": {
-              "description": "DMA_IN_PERI_SEL_CH2_REG.",
-              "offset": 544,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_IN_SEL_CH2": {
-                    "description": "This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "OUT_CONF0_CH2": {
-              "description": "DMA_OUT_CONF0_CH2_REG.",
-              "offset": 592,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_RST_CH2": {
-                    "description": "This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "OUT_LOOP_TEST_CH2": {
-                    "description": "reserved",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "OUT_AUTO_WRBACK_CH2": {
-                    "description": "Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OUT_EOF_MODE_CH2": {
-                    "description": "EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "OUTDSCR_BURST_EN_CH2": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "OUT_DATA_BURST_EN_CH2": {
-                    "description": "Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_CONF1_CH2": {
-              "description": "DMA_OUT_CONF1_CH2_REG.",
-              "offset": 596,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_CHECK_OWNER_CH2": {
-                    "description": "Set this bit to enable checking the owner attribute of the link descriptor.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUTFIFO_STATUS_CH2": {
-              "description": "DMA_OUTFIFO_STATUS_CH2_REG.",
-              "offset": 600,
-              "size": 32,
-              "reset_value": 125829122,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_FULL_CH2": {
-                    "description": "L1 Tx FIFO full signal for Tx channel 2.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_EMPTY_CH2": {
-                    "description": "L1 Tx FIFO empty signal for Tx channel 2.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTFIFO_CNT_CH2": {
-                    "description": "The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.",
-                    "offset": 2,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_1B_CH2": {
-                    "description": "reserved",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_2B_CH2": {
-                    "description": "reserved",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_3B_CH2": {
-                    "description": "reserved",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_REMAIN_UNDER_4B_CH2": {
-                    "description": "reserved",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PUSH_CH2": {
-              "description": "DMA_OUT_PUSH_CH2_REG.",
-              "offset": 604,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTFIFO_WDATA_CH2": {
-                    "description": "This register stores the data that need to be pushed into DMA FIFO.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "OUTFIFO_PUSH_CH2": {
-                    "description": "Set this bit to push data into DMA FIFO.",
-                    "offset": 9,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "OUT_LINK_CH2": {
-              "description": "DMA_OUT_LINK_CH2_REG.",
-              "offset": 608,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_ADDR_CH2": {
-                    "description": "This register stores the 20 least significant bits of the first outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 20
-                  },
-                  "OUTLINK_STOP_CH2": {
-                    "description": "Set this bit to stop dealing with the outlink descriptors.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "OUTLINK_START_CH2": {
-                    "description": "Set this bit to start dealing with the outlink descriptors.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "OUTLINK_RESTART_CH2": {
-                    "description": "Set this bit to restart a new outlink from the last address.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "OUTLINK_PARK_CH2": {
-                    "description": "1: the outlink descriptor's FSM is in idle state.  0: the outlink descriptor's FSM is working.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_STATE_CH2": {
-              "description": "DMA_OUT_STATE_CH2_REG.",
-              "offset": 612,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_ADDR_CH2": {
-                    "description": "This register stores the current outlink descriptor's address.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "OUT_DSCR_STATE_CH2": {
-                    "description": "reserved",
-                    "offset": 18,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_STATE_CH2": {
-                    "description": "reserved",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_DES_ADDR_CH2": {
-              "description": "DMA_OUT_EOF_DES_ADDR_CH2_REG.",
-              "offset": 616,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_DES_ADDR_CH2": {
-                    "description": "This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EOF_BFR_DES_ADDR_CH2": {
-              "description": "DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.",
-              "offset": 620,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EOF_BFR_DES_ADDR_CH2": {
-                    "description": "This register stores the address of the outlink descriptor before the last outlink descriptor.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_CH2": {
-              "description": "DMA_OUT_DSCR_CH2_REG.",
-              "offset": 624,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_CH2": {
-                    "description": "The address of the current outlink descriptor y.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF0_CH2": {
-              "description": "DMA_OUT_DSCR_BF0_CH2_REG.",
-              "offset": 628,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF0_CH2": {
-                    "description": "The address of the last outlink descriptor y-1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_DSCR_BF1_CH2": {
-              "description": "DMA_OUT_DSCR_BF1_CH2_REG.",
-              "offset": 632,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUTLINK_DSCR_BF1_CH2": {
-                    "description": "The address of the second-to-last inlink descriptor x-2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_PRI_CH2": {
-              "description": "DMA_OUT_PRI_CH2_REG.",
-              "offset": 636,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_PRI_CH2": {
-                    "description": "The priority of Tx channel 2. The larger of the value, the higher of the priority.",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "OUT_PERI_SEL_CH2": {
-              "description": "DMA_OUT_PERI_SEL_CH2_REG.",
-              "offset": 640,
-              "size": 32,
-              "reset_value": 63,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PERI_OUT_SEL_CH2": {
-                    "description": "This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "DS": {
-        "description": "Digital Signature",
-        "children": {
-          "registers": {
-            "Y_MEM": {
-              "description": "memory that stores Y",
-              "offset": 0,
-              "size": 8,
-              "count": 512,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "M_MEM": {
-              "description": "memory that stores M",
-              "offset": 512,
-              "size": 8,
-              "count": 512,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "RB_MEM": {
-              "description": "memory that stores Rb",
-              "offset": 1024,
-              "size": 8,
-              "count": 512,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "BOX_MEM": {
-              "description": "memory that stores BOX",
-              "offset": 1536,
-              "size": 8,
-              "count": 48,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "X_MEM": {
-              "description": "memory that stores X",
-              "offset": 2048,
-              "size": 8,
-              "count": 512,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "Z_MEM": {
-              "description": "memory that stores Z",
-              "offset": 2560,
-              "size": 8,
-              "count": 512,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "SET_START": {
-              "description": "DS start control register",
-              "offset": 3584,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_START": {
-                    "description": "set this bit to start DS operation.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_CONTINUE": {
-              "description": "DS continue control register",
-              "offset": 3588,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_CONTINUE": {
-                    "description": "set this bit to continue DS operation.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_FINISH": {
-              "description": "DS finish control register",
-              "offset": 3592,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_FINISH": {
-                    "description": "Set this bit to finish DS process.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "QUERY_BUSY": {
-              "description": "DS query busy register",
-              "offset": 3596,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "QUERY_BUSY": {
-                    "description": "digital signature state. 1'b0: idle, 1'b1: busy",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "QUERY_KEY_WRONG": {
-              "description": "DS query key-wrong counter register",
-              "offset": 3600,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "QUERY_KEY_WRONG": {
-                    "description": "digital signature key wrong counter",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "QUERY_CHECK": {
-              "description": "DS query check result register",
-              "offset": 3604,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MD_ERROR": {
-                    "description": "MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PADDING_BAD": {
-                    "description": "padding checkout result. 1'b0: a good padding, 1'b1: a bad padding",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "DS version control register",
-              "offset": 3616,
-              "size": 32,
-              "reset_value": 538969624,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "ds version information",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "EFUSE": {
-        "description": "eFuse Controller",
-        "children": {
-          "registers": {
-            "PGM_DATA0": {
-              "description": "Register 0 that stores data to be programmed.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_0": {
-                    "description": "The content of the 0th 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA1": {
-              "description": "Register 1 that stores data to be programmed.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_1": {
-                    "description": "The content of the 1st 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA2": {
-              "description": "Register 2 that stores data to be programmed.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_2": {
-                    "description": "The content of the 2nd 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA3": {
-              "description": "Register 3 that stores data to be programmed.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_3": {
-                    "description": "The content of the 3rd 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA4": {
-              "description": "Register 4 that stores data to be programmed.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_4": {
-                    "description": "The content of the 4th 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA5": {
-              "description": "Register 5 that stores data to be programmed.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_5": {
-                    "description": "The content of the 5th 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA6": {
-              "description": "Register 6 that stores data to be programmed.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_6": {
-                    "description": "The content of the 6th 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_DATA7": {
-              "description": "Register 7 that stores data to be programmed.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_DATA_7": {
-                    "description": "The content of the 7th 32-bit data to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_CHECK_VALUE0": {
-              "description": "Register 0 that stores the RS code to be programmed.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_RS_DATA_0": {
-                    "description": "The content of the 0th 32-bit RS code to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_CHECK_VALUE1": {
-              "description": "Register 1 that stores the RS code to be programmed.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_RS_DATA_1": {
-                    "description": "The content of the 1st 32-bit RS code to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PGM_CHECK_VALUE2": {
-              "description": "Register 2 that stores the RS code to be programmed.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PGM_RS_DATA_2": {
-                    "description": "The content of the 2nd 32-bit RS code to be programmed.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "RD_WR_DIS": {
-              "description": "BLOCK0 data register 0.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WR_DIS": {
-                    "description": "Disable programming of individual eFuses.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_DATA0": {
-              "description": "BLOCK0 data register 1.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RD_DIS": {
-                    "description": "Set this bit to disable reading from BlOCK4-10.",
-                    "offset": 0,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "DIS_RTC_RAM_BOOT": {
-                    "description": "Set this bit to disable boot from RTC RAM.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_ICACHE": {
-                    "description": "Set this bit to disable Icache.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_JTAG": {
-                    "description": "Set this bit to disable function of usb switch to jtag in module of usb device.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_DOWNLOAD_ICACHE": {
-                    "description": "Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_DEVICE": {
-                    "description": "Set this bit to disable usb device.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_FORCE_DOWNLOAD": {
-                    "description": "Set this bit to disable the function that forces chip into download mode.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED6": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_CAN": {
-                    "description": "Set this bit to disable CAN function.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "JTAG_SEL_ENABLE": {
-                    "description": "Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SOFT_DIS_JTAG": {
-                    "description": "Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.",
-                    "offset": 16,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "DIS_PAD_JTAG": {
-                    "description": "Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_DOWNLOAD_MANUAL_ENCRYPT": {
-                    "description": "Set this bit to disable flash encryption when in download boot modes.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "USB_DREFH": {
-                    "description": "Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.",
-                    "offset": 21,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "USB_DREFL": {
-                    "description": "Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.",
-                    "offset": 23,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "USB_EXCHG_PINS": {
-                    "description": "Set this bit to exchange USB D+ and D- pins.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "VDD_SPI_AS_GPIO": {
-                    "description": "Set this bit to vdd spi pin function as gpio.",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BTLC_GPIO_ENABLE": {
-                    "description": "Enable btlc gpio.",
-                    "offset": 27,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "POWERGLITCH_EN": {
-                    "description": "Set this bit to enable power glitch function.",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "POWER_GLITCH_DSENSE": {
-                    "description": "Sample delay configuration of power glitch.",
-                    "offset": 30,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_DATA1": {
-              "description": "BLOCK0 data register 2.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RPT4_RESERVED2": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "WDT_DELAY_SEL": {
-                    "description": "Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.",
-                    "offset": 16,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "SPI_BOOT_CRYPT_CNT": {
-                    "description": "Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.",
-                    "offset": 18,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE0": {
-                    "description": "Set this bit to enable revoking first secure boot key.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE1": {
-                    "description": "Set this bit to enable revoking second secure boot key.",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE2": {
-                    "description": "Set this bit to enable revoking third secure boot key.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_0": {
-                    "description": "Purpose of Key0.",
-                    "offset": 24,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_1": {
-                    "description": "Purpose of Key1.",
-                    "offset": 28,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_DATA2": {
-              "description": "BLOCK0 data register 3.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_PURPOSE_2": {
-                    "description": "Purpose of Key2.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_3": {
-                    "description": "Purpose of Key3.",
-                    "offset": 4,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_4": {
-                    "description": "Purpose of Key4.",
-                    "offset": 8,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_5": {
-                    "description": "Purpose of Key5.",
-                    "offset": 12,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED3": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 16,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_EN": {
-                    "description": "Set this bit to enable secure boot.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_AGGRESSIVE_REVOKE": {
-                    "description": "Set this bit to enable revoking aggressive secure boot.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED0": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 22,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "FLASH_TPUW": {
-                    "description": "Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.",
-                    "offset": 28,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_DATA3": {
-              "description": "BLOCK0 data register 4.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIS_DOWNLOAD_MODE": {
-                    "description": "Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_LEGACY_SPI_BOOT": {
-                    "description": "Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "UART_PRINT_CHANNEL": {
-                    "description": "Selectes the default UART print channel. 0: UART0. 1: UART1.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_ECC_MODE": {
-                    "description": "Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_DOWNLOAD_MODE": {
-                    "description": "Set this bit to disable UART download mode through USB.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ENABLE_SECURITY_DOWNLOAD": {
-                    "description": "Set this bit to enable secure UART download mode.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "UART_PRINT_CONTROL": {
-                    "description": "Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.",
-                    "offset": 6,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "PIN_POWER_SELECTION": {
-                    "description": "GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_TYPE": {
-                    "description": "Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_PAGE_SIZE": {
-                    "description": "Set Flash page size.",
-                    "offset": 10,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "FLASH_ECC_EN": {
-                    "description": "Set 1 to enable ECC for flash boot.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FORCE_SEND_RESUME": {
-                    "description": "Set this bit to force ROM code to send a resume command during SPI boot.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_VERSION": {
-                    "description": "Secure version (used by ESP-IDF anti-rollback feature).",
-                    "offset": 14,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED1": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 30,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_DATA4": {
-              "description": "BLOCK0 data register 5.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RPT4_RESERVED4": {
-                    "description": "Reserved (used for four backups method).",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_0": {
-              "description": "BLOCK1 data register 0.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MAC_0": {
-                    "description": "Stores the low 32 bits of MAC address.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_1": {
-              "description": "BLOCK1 data register 1.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MAC_1": {
-                    "description": "Stores the high 16 bits of MAC address.",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "SPI_PAD_CONF_0": {
-                    "description": "Stores the zeroth part of SPI_PAD_CONF.",
-                    "offset": 16,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_2": {
-              "description": "BLOCK1 data register 2.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_PAD_CONF_1": {
-                    "description": "Stores the first part of SPI_PAD_CONF.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_3": {
-              "description": "BLOCK1 data register 3.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_PAD_CONF_2": {
-                    "description": "Stores the second part of SPI_PAD_CONF.",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  },
-                  "SYS_DATA_PART0_0": {
-                    "description": "Stores the fist 14 bits of the zeroth part of system data.",
-                    "offset": 18,
-                    "size": 14,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_4": {
-              "description": "BLOCK1 data register 4.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART0_1": {
-                    "description": "Stores the fist 32 bits of the zeroth part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_MAC_SPI_SYS_5": {
-              "description": "BLOCK1 data register 5.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART0_2": {
-                    "description": "Stores the second 32 bits of the zeroth part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA0": {
-              "description": "Register 0 of BLOCK2 (system).",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_0": {
-                    "description": "Stores the zeroth 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA1": {
-              "description": "Register 1 of BLOCK2 (system).",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_1": {
-                    "description": "Stores the first 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA2": {
-              "description": "Register 2 of BLOCK2 (system).",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_2": {
-                    "description": "Stores the second 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA3": {
-              "description": "Register 3 of BLOCK2 (system).",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_3": {
-                    "description": "Stores the third 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA4": {
-              "description": "Register 4 of BLOCK2 (system).",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_4": {
-                    "description": "Stores the fourth 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA5": {
-              "description": "Register 5 of BLOCK2 (system).",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_5": {
-                    "description": "Stores the fifth 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA6": {
-              "description": "Register 6 of BLOCK2 (system).",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_6": {
-                    "description": "Stores the sixth 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART1_DATA7": {
-              "description": "Register 7 of BLOCK2 (system).",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART1_7": {
-                    "description": "Stores the seventh 32 bits of the first part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA0": {
-              "description": "Register 0 of BLOCK3 (user).",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA0": {
-                    "description": "Stores the zeroth 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA1": {
-              "description": "Register 1 of BLOCK3 (user).",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA1": {
-                    "description": "Stores the first 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA2": {
-              "description": "Register 2 of BLOCK3 (user).",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA2": {
-                    "description": "Stores the second 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA3": {
-              "description": "Register 3 of BLOCK3 (user).",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA3": {
-                    "description": "Stores the third 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA4": {
-              "description": "Register 4 of BLOCK3 (user).",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA4": {
-                    "description": "Stores the fourth 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA5": {
-              "description": "Register 5 of BLOCK3 (user).",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA5": {
-                    "description": "Stores the fifth 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA6": {
-              "description": "Register 6 of BLOCK3 (user).",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA6": {
-                    "description": "Stores the sixth 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_USR_DATA7": {
-              "description": "Register 7 of BLOCK3 (user).",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DATA7": {
-                    "description": "Stores the seventh 32 bits of BLOCK3 (user).",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA0": {
-              "description": "Register 0 of BLOCK4 (KEY0).",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA1": {
-              "description": "Register 1 of BLOCK4 (KEY0).",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA1": {
-                    "description": "Stores the first 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA2": {
-              "description": "Register 2 of BLOCK4 (KEY0).",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA2": {
-                    "description": "Stores the second 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA3": {
-              "description": "Register 3 of BLOCK4 (KEY0).",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA3": {
-                    "description": "Stores the third 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA4": {
-              "description": "Register 4 of BLOCK4 (KEY0).",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA5": {
-              "description": "Register 5 of BLOCK4 (KEY0).",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA6": {
-              "description": "Register 6 of BLOCK4 (KEY0).",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY0_DATA7": {
-              "description": "Register 7 of BLOCK4 (KEY0).",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY0_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY0.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA0": {
-              "description": "Register 0 of BLOCK5 (KEY1).",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA1": {
-              "description": "Register 1 of BLOCK5 (KEY1).",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA1": {
-                    "description": "Stores the first 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA2": {
-              "description": "Register 2 of BLOCK5 (KEY1).",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA2": {
-                    "description": "Stores the second 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA3": {
-              "description": "Register 3 of BLOCK5 (KEY1).",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA3": {
-                    "description": "Stores the third 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA4": {
-              "description": "Register 4 of BLOCK5 (KEY1).",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA5": {
-              "description": "Register 5 of BLOCK5 (KEY1).",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA6": {
-              "description": "Register 6 of BLOCK5 (KEY1).",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY1_DATA7": {
-              "description": "Register 7 of BLOCK5 (KEY1).",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY1_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY1.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA0": {
-              "description": "Register 0 of BLOCK6 (KEY2).",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA1": {
-              "description": "Register 1 of BLOCK6 (KEY2).",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA1": {
-                    "description": "Stores the first 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA2": {
-              "description": "Register 2 of BLOCK6 (KEY2).",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA2": {
-                    "description": "Stores the second 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA3": {
-              "description": "Register 3 of BLOCK6 (KEY2).",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA3": {
-                    "description": "Stores the third 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA4": {
-              "description": "Register 4 of BLOCK6 (KEY2).",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA5": {
-              "description": "Register 5 of BLOCK6 (KEY2).",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA6": {
-              "description": "Register 6 of BLOCK6 (KEY2).",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY2_DATA7": {
-              "description": "Register 7 of BLOCK6 (KEY2).",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY2_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY2.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA0": {
-              "description": "Register 0 of BLOCK7 (KEY3).",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA1": {
-              "description": "Register 1 of BLOCK7 (KEY3).",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA1": {
-                    "description": "Stores the first 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA2": {
-              "description": "Register 2 of BLOCK7 (KEY3).",
-              "offset": 260,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA2": {
-                    "description": "Stores the second 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA3": {
-              "description": "Register 3 of BLOCK7 (KEY3).",
-              "offset": 264,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA3": {
-                    "description": "Stores the third 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA4": {
-              "description": "Register 4 of BLOCK7 (KEY3).",
-              "offset": 268,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA5": {
-              "description": "Register 5 of BLOCK7 (KEY3).",
-              "offset": 272,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA6": {
-              "description": "Register 6 of BLOCK7 (KEY3).",
-              "offset": 276,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY3_DATA7": {
-              "description": "Register 7 of BLOCK7 (KEY3).",
-              "offset": 280,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY3_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY3.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA0": {
-              "description": "Register 0 of BLOCK8 (KEY4).",
-              "offset": 284,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA1": {
-              "description": "Register 1 of BLOCK8 (KEY4).",
-              "offset": 288,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA1": {
-                    "description": "Stores the first 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA2": {
-              "description": "Register 2 of BLOCK8 (KEY4).",
-              "offset": 292,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA2": {
-                    "description": "Stores the second 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA3": {
-              "description": "Register 3 of BLOCK8 (KEY4).",
-              "offset": 296,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA3": {
-                    "description": "Stores the third 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA4": {
-              "description": "Register 4 of BLOCK8 (KEY4).",
-              "offset": 300,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA5": {
-              "description": "Register 5 of BLOCK8 (KEY4).",
-              "offset": 304,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA6": {
-              "description": "Register 6 of BLOCK8 (KEY4).",
-              "offset": 308,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY4_DATA7": {
-              "description": "Register 7 of BLOCK8 (KEY4).",
-              "offset": 312,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY4_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY4.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA0": {
-              "description": "Register 0 of BLOCK9 (KEY5).",
-              "offset": 316,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA0": {
-                    "description": "Stores the zeroth 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA1": {
-              "description": "Register 1 of BLOCK9 (KEY5).",
-              "offset": 320,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA1": {
-                    "description": "Stores the first 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA2": {
-              "description": "Register 2 of BLOCK9 (KEY5).",
-              "offset": 324,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA2": {
-                    "description": "Stores the second 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA3": {
-              "description": "Register 3 of BLOCK9 (KEY5).",
-              "offset": 328,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA3": {
-                    "description": "Stores the third 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA4": {
-              "description": "Register 4 of BLOCK9 (KEY5).",
-              "offset": 332,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA4": {
-                    "description": "Stores the fourth 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA5": {
-              "description": "Register 5 of BLOCK9 (KEY5).",
-              "offset": 336,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA5": {
-                    "description": "Stores the fifth 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA6": {
-              "description": "Register 6 of BLOCK9 (KEY5).",
-              "offset": 340,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA6": {
-                    "description": "Stores the sixth 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_KEY5_DATA7": {
-              "description": "Register 7 of BLOCK9 (KEY5).",
-              "offset": 344,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_DATA7": {
-                    "description": "Stores the seventh 32 bits of KEY5.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA0": {
-              "description": "Register 0 of BLOCK10 (system).",
-              "offset": 348,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_0": {
-                    "description": "Stores the 0th 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA1": {
-              "description": "Register 1 of BLOCK9 (KEY5).",
-              "offset": 352,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_1": {
-                    "description": "Stores the 1st 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA2": {
-              "description": "Register 2 of BLOCK10 (system).",
-              "offset": 356,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_2": {
-                    "description": "Stores the 2nd 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA3": {
-              "description": "Register 3 of BLOCK10 (system).",
-              "offset": 360,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_3": {
-                    "description": "Stores the 3rd 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA4": {
-              "description": "Register 4 of BLOCK10 (system).",
-              "offset": 364,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_4": {
-                    "description": "Stores the 4th 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA5": {
-              "description": "Register 5 of BLOCK10 (system).",
-              "offset": 368,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_5": {
-                    "description": "Stores the 5th 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA6": {
-              "description": "Register 6 of BLOCK10 (system).",
-              "offset": 372,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_6": {
-                    "description": "Stores the 6th 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_SYS_PART2_DATA7": {
-              "description": "Register 7 of BLOCK10 (system).",
-              "offset": 376,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYS_DATA_PART2_7": {
-                    "description": "Stores the 7th 32 bits of the 2nd part of system data.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_ERR0": {
-              "description": "Programming error record register 0 of BLOCK0.",
-              "offset": 380,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RD_DIS_ERR": {
-                    "description": "If any bit in RD_DIS is 1, then it indicates a programming error.",
-                    "offset": 0,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "DIS_RTC_RAM_BOOT_ERR": {
-                    "description": "If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_ICACHE_ERR": {
-                    "description": "If DIS_ICACHE is 1, then it indicates a programming error.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_JTAG_ERR": {
-                    "description": "If DIS_USB_JTAG is 1, then it indicates a programming error.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_DOWNLOAD_ICACHE_ERR": {
-                    "description": "If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_DEVICE_ERR": {
-                    "description": "If DIS_USB_DEVICE is 1, then it indicates a programming error.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_FORCE_DOWNLOAD_ERR": {
-                    "description": "If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED6_ERR": {
-                    "description": "Reserved.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_CAN_ERR": {
-                    "description": "If DIS_CAN is 1, then it indicates a programming error.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "JTAG_SEL_ENABLE_ERR": {
-                    "description": "If JTAG_SEL_ENABLE is 1, then it indicates a programming error.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SOFT_DIS_JTAG_ERR": {
-                    "description": "If SOFT_DIS_JTAG is 1, then it indicates a programming error.",
-                    "offset": 16,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "DIS_PAD_JTAG_ERR": {
-                    "description": "If DIS_PAD_JTAG is 1, then it indicates a programming error.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR": {
-                    "description": "If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "USB_DREFH_ERR": {
-                    "description": "If any bit in USB_DREFH is 1, then it indicates a programming error.",
-                    "offset": 21,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "USB_DREFL_ERR": {
-                    "description": "If any bit in USB_DREFL is 1, then it indicates a programming error.",
-                    "offset": 23,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "USB_EXCHG_PINS_ERR": {
-                    "description": "If USB_EXCHG_PINS is 1, then it indicates a programming error.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "VDD_SPI_AS_GPIO_ERR": {
-                    "description": "If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BTLC_GPIO_ENABLE_ERR": {
-                    "description": "If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.",
-                    "offset": 27,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "POWERGLITCH_EN_ERR": {
-                    "description": "If POWERGLITCH_EN is 1, then it indicates a programming error.",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "POWER_GLITCH_DSENSE_ERR": {
-                    "description": "If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.",
-                    "offset": 30,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_ERR1": {
-              "description": "Programming error record register 1 of BLOCK0.",
-              "offset": 384,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RPT4_RESERVED2_ERR": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "WDT_DELAY_SEL_ERR": {
-                    "description": "If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.",
-                    "offset": 16,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "SPI_BOOT_CRYPT_CNT_ERR": {
-                    "description": "If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.",
-                    "offset": 18,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE0_ERR": {
-                    "description": "If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE1_ERR": {
-                    "description": "If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_KEY_REVOKE2_ERR": {
-                    "description": "If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_0_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.",
-                    "offset": 24,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_1_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.",
-                    "offset": 28,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_ERR2": {
-              "description": "Programming error record register 2 of BLOCK0.",
-              "offset": 388,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_PURPOSE_2_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_3_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.",
-                    "offset": 4,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_4_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.",
-                    "offset": 8,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "KEY_PURPOSE_5_ERR": {
-                    "description": "If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.",
-                    "offset": 12,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED3_ERR": {
-                    "description": "Reserved.",
-                    "offset": 16,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_EN_ERR": {
-                    "description": "If SECURE_BOOT_EN is 1, then it indicates a programming error.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_BOOT_AGGRESSIVE_REVOKE_ERR": {
-                    "description": "If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED0_ERR": {
-                    "description": "Reserved.",
-                    "offset": 22,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "FLASH_TPUW_ERR": {
-                    "description": "If any bit in FLASH_TPUM is 1, then it indicates a programming error.",
-                    "offset": 28,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_ERR3": {
-              "description": "Programming error record register 3 of BLOCK0.",
-              "offset": 392,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIS_DOWNLOAD_MODE_ERR": {
-                    "description": "If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_LEGACY_SPI_BOOT_ERR": {
-                    "description": "If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "UART_PRINT_CHANNEL_ERR": {
-                    "description": "If UART_PRINT_CHANNEL is 1, then it indicates a programming error.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_ECC_MODE_ERR": {
-                    "description": "If FLASH_ECC_MODE is 1, then it indicates a programming error.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIS_USB_DOWNLOAD_MODE_ERR": {
-                    "description": "If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ENABLE_SECURITY_DOWNLOAD_ERR": {
-                    "description": "If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "UART_PRINT_CONTROL_ERR": {
-                    "description": "If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.",
-                    "offset": 6,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "PIN_POWER_SELECTION_ERR": {
-                    "description": "If PIN_POWER_SELECTION is 1, then it indicates a programming error.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_TYPE_ERR": {
-                    "description": "If FLASH_TYPE is 1, then it indicates a programming error.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FLASH_PAGE_SIZE_ERR": {
-                    "description": "If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.",
-                    "offset": 10,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "FLASH_ECC_EN_ERR": {
-                    "description": "If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FORCE_SEND_RESUME_ERR": {
-                    "description": "If FORCE_SEND_RESUME is 1, then it indicates a programming error.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SECURE_VERSION_ERR": {
-                    "description": "If any bit in SECURE_VERSION is 1, then it indicates a programming error.",
-                    "offset": 14,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "RPT4_RESERVED1_ERR": {
-                    "description": "Reserved.",
-                    "offset": 30,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_REPEAT_ERR4": {
-              "description": "Programming error record register 4 of BLOCK0.",
-              "offset": 400,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RPT4_RESERVED4_ERR": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 24,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_RS_ERR0": {
-              "description": "Programming error record register 0 of BLOCK1-10.",
-              "offset": 448,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MAC_SPI_8M_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "MAC_SPI_8M_FAIL": {
-                    "description": "0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SYS_PART1_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 4,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "SYS_PART1_FAIL": {
-                    "description": "0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "USR_DATA_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 8,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "USR_DATA_FAIL": {
-                    "description": "0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY0_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 12,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY0_FAIL": {
-                    "description": "0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY1_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 16,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY1_FAIL": {
-                    "description": "0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY2_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY2_FAIL": {
-                    "description": "0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY3_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 24,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY3_FAIL": {
-                    "description": "0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "KEY4_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 28,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY4_FAIL": {
-                    "description": "0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RD_RS_ERR1": {
-              "description": "Programming error record register 1 of BLOCK1-10.",
-              "offset": 452,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY5_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "KEY5_FAIL": {
-                    "description": "0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SYS_PART2_ERR_NUM": {
-                    "description": "The value of this signal means the number of error bytes.",
-                    "offset": 4,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "SYS_PART2_FAIL": {
-                    "description": "0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLK": {
-              "description": "eFuse clcok configuration register.",
-              "offset": 456,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "EFUSE_MEM_FORCE_PD": {
-                    "description": "Set this bit to force eFuse SRAM into power-saving mode.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MEM_CLK_FORCE_ON": {
-                    "description": "Set this bit and force to activate clock signal of eFuse SRAM.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "EFUSE_MEM_FORCE_PU": {
-                    "description": "Set this bit to force eFuse SRAM into working mode.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "EN": {
-                    "description": "Set this bit and force to enable clock signal of eFuse memory.",
-                    "offset": 16,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CONF": {
-              "description": "eFuse operation mode configuraiton register;",
-              "offset": 460,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OP_CODE": {
-                    "description": "0x5A5A: Operate programming command 0x5AA5: Operate read command.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "STATUS": {
-              "description": "eFuse status register.",
-              "offset": 464,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATE": {
-                    "description": "Indicates the state of the eFuse state machine.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "OTP_LOAD_SW": {
-                    "description": "The value of OTP_LOAD_SW.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OTP_VDDQ_C_SYNC2": {
-                    "description": "The value of OTP_VDDQ_C_SYNC2.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OTP_STROBE_SW": {
-                    "description": "The value of OTP_STROBE_SW.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OTP_CSB_SW": {
-                    "description": "The value of OTP_CSB_SW.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OTP_PGENB_SW": {
-                    "description": "The value of OTP_PGENB_SW.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OTP_VDDQ_IS_SW": {
-                    "description": "The value of OTP_VDDQ_IS_SW.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "REPEAT_ERR_CNT": {
-                    "description": "Indicates the number of error bits during programming BLOCK0.",
-                    "offset": 10,
-                    "size": 8,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CMD": {
-              "description": "eFuse command register.",
-              "offset": 468,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_CMD": {
-                    "description": "Set this bit to send read command.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PGM_CMD": {
-                    "description": "Set this bit to send programming command.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "BLK_NUM": {
-                    "description": "The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.",
-                    "offset": 2,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "eFuse raw interrupt register.",
-              "offset": 472,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_DONE_INT_RAW": {
-                    "description": "The raw bit signal for read_done interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PGM_DONE_INT_RAW": {
-                    "description": "The raw bit signal for pgm_done interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "eFuse interrupt status register.",
-              "offset": 476,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_DONE_INT_ST": {
-                    "description": "The status signal for read_done interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PGM_DONE_INT_ST": {
-                    "description": "The status signal for pgm_done interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "eFuse interrupt enable register.",
-              "offset": 480,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_DONE_INT_ENA": {
-                    "description": "The enable signal for read_done interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PGM_DONE_INT_ENA": {
-                    "description": "The enable signal for pgm_done interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "eFuse interrupt clear register.",
-              "offset": 484,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_DONE_INT_CLR": {
-                    "description": "The clear signal for read_done interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PGM_DONE_INT_CLR": {
-                    "description": "The clear signal for pgm_done interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DAC_CONF": {
-              "description": "Controls the eFuse programming voltage.",
-              "offset": 488,
-              "size": 32,
-              "reset_value": 130588,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DAC_CLK_DIV": {
-                    "description": "Controls the division factor of the rising clock of the programming voltage.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "DAC_CLK_PAD_SEL": {
-                    "description": "Don't care.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DAC_NUM": {
-                    "description": "Controls the rising period of the programming voltage.",
-                    "offset": 9,
-                    "size": 8
-                  },
-                  "OE_CLR": {
-                    "description": "Reduces the power supply of the programming voltage.",
-                    "offset": 17,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RD_TIM_CONF": {
-              "description": "Configures read timing parameters.",
-              "offset": 492,
-              "size": 32,
-              "reset_value": 301989888,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "READ_INIT_NUM": {
-                    "description": "Configures the initial read time of eFuse.",
-                    "offset": 24,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "WR_TIM_CONF1": {
-              "description": "Configurarion register 1 of eFuse programming timing parameters.",
-              "offset": 496,
-              "size": 32,
-              "reset_value": 2654208,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PWR_ON_NUM": {
-                    "description": "Configures the power up time for VDDQ.",
-                    "offset": 8,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "WR_TIM_CONF2": {
-              "description": "Configurarion register 2 of eFuse programming timing parameters.",
-              "offset": 500,
-              "size": 32,
-              "reset_value": 400,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PWR_OFF_NUM": {
-                    "description": "Configures the power outage time for VDDQ.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "eFuse version register.",
-              "offset": 508,
-              "size": 32,
-              "reset_value": 33583616,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "Stores eFuse version.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "EXTMEM": {
-        "description": "External Memory",
-        "children": {
-          "registers": {
-            "ICACHE_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_ENABLE": {
-                    "description": "The bit is used to activate the data cache. 0: disable, 1: enable",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_CTRL1": {
-              "description": "This description will be updated in the near future.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SHUT_IBUS": {
-                    "description": "The bit is used to disable core0 ibus, 0: enable, 1: disable",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_SHUT_DBUS": {
-                    "description": "The bit is used to disable core1 ibus, 0: enable, 1: disable",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_TAG_POWER_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 5,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_TAG_MEM_FORCE_ON": {
-                    "description": "The bit is used to close clock gating of  icache tag memory. 1: close gating, 0: open clock gating.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_TAG_MEM_FORCE_PD": {
-                    "description": "The bit is used to power  icache tag memory down, 0: follow rtc_lslp, 1: power down",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ICACHE_TAG_MEM_FORCE_PU": {
-                    "description": "The bit is used to power  icache tag memory up, 0: follow rtc_lslp, 1: power up",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOCK_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOCK_SCT0_EN": {
-                    "description": "The bit is used to enable the first section of prelock function.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_PRELOCK_SCT1_EN": {
-                    "description": "The bit is used to enable the second section of prelock function.",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOCK_SCT0_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOCK_SCT0_ADDR": {
-                    "description": "The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOCK_SCT1_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOCK_SCT1_ADDR": {
-                    "description": "The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOCK_SCT_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOCK_SCT1_SIZE": {
-                    "description": "The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "ICACHE_PRELOCK_SCT0_SIZE": {
-                    "description": "The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "ICACHE_LOCK_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 4,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_LOCK_ENA": {
-                    "description": "The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_UNLOCK_ENA": {
-                    "description": "The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ICACHE_LOCK_DONE": {
-                    "description": "The bit is used to indicate unlock/lock operation is finished.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ICACHE_LOCK_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_LOCK_ADDR": {
-                    "description": "The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_LOCK_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_LOCK_SIZE": {
-                    "description": "The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "ICACHE_SYNC_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_INVALIDATE_ENA": {
-                    "description": "The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_SYNC_DONE": {
-                    "description": "The bit is used to indicate invalidate operation is finished.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ICACHE_SYNC_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_ADDR": {
-                    "description": "The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_SYNC_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_SIZE": {
-                    "description": "The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.",
-                    "offset": 0,
-                    "size": 23
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOAD_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOAD_ENA": {
-                    "description": "The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_PRELOAD_DONE": {
-                    "description": "The bit is used to indicate preload operation is finished.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ICACHE_PRELOAD_ORDER": {
-                    "description": "The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOAD_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOAD_ADDR": {
-                    "description": "The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOAD_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOAD_SIZE": {
-                    "description": "The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "ICACHE_AUTOLOAD_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_AUTOLOAD_SCT0_ENA": {
-                    "description": "The bits are used to enable the first section for autoload operation.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_AUTOLOAD_SCT1_ENA": {
-                    "description": "The bits are used to enable the second section for autoload operation.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ICACHE_AUTOLOAD_ENA": {
-                    "description": "The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "ICACHE_AUTOLOAD_DONE": {
-                    "description": "The bit is used to indicate autoload operation is finished.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ICACHE_AUTOLOAD_ORDER": {
-                    "description": "The bits are used to configure the direction of autoload. 1: descending, 0: ascending.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "ICACHE_AUTOLOAD_RQST": {
-                    "description": "The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.",
-                    "offset": 5,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "ICACHE_AUTOLOAD_SCT0_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_AUTOLOAD_SCT0_ADDR": {
-                    "description": "The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_AUTOLOAD_SCT0_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_AUTOLOAD_SCT0_SIZE": {
-                    "description": "The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.",
-                    "offset": 0,
-                    "size": 27
-                  }
-                }
-              }
-            },
-            "ICACHE_AUTOLOAD_SCT1_ADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_AUTOLOAD_SCT1_ADDR": {
-                    "description": "The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ICACHE_AUTOLOAD_SCT1_SIZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_AUTOLOAD_SCT1_SIZE": {
-                    "description": "The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.",
-                    "offset": 0,
-                    "size": 27
-                  }
-                }
-              }
-            },
-            "IBUS_TO_FLASH_START_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 1107296256,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_TO_FLASH_START_VADDR": {
-                    "description": "The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "IBUS_TO_FLASH_END_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 1115684863,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_TO_FLASH_END_VADDR": {
-                    "description": "The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "DBUS_TO_FLASH_START_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 1006632960,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_TO_FLASH_START_VADDR": {
-                    "description": "The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "DBUS_TO_FLASH_END_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 1015021567,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_TO_FLASH_END_VADDR": {
-                    "description": "The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CACHE_ACS_CNT_CLR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_ACS_CNT_CLR": {
-                    "description": "The bit is used to clear ibus counter.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DBUS_ACS_CNT_CLR": {
-                    "description": "The bit is used to clear dbus counter.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "IBUS_ACS_MISS_CNT": {
-              "description": "This description will be updated in the near future.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_ACS_MISS_CNT": {
-                    "description": "The bits are used to count the number of the cache miss caused by ibus access flash.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IBUS_ACS_CNT": {
-              "description": "This description will be updated in the near future.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_ACS_CNT": {
-                    "description": "The bits are used to count the number of ibus access flash through icache.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DBUS_ACS_FLASH_MISS_CNT": {
-              "description": "This description will be updated in the near future.",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_ACS_FLASH_MISS_CNT": {
-                    "description": "The bits are used to count the number of the cache miss caused by dbus access flash.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DBUS_ACS_CNT": {
-              "description": "This description will be updated in the near future.",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_ACS_CNT": {
-                    "description": "The bits are used to count the number of dbus access flash through icache.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_ILG_INT_ENA": {
-              "description": "This description will be updated in the near future.",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_OP_FAULT_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by sync configurations fault.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_PRELOAD_OP_FAULT_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by preload configurations fault.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "MMU_ENTRY_FAULT_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by mmu entry fault.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "IBUS_CNT_OVF_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by ibus counter overflow.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "DBUS_CNT_OVF_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by dbus counter overflow.",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_ILG_INT_CLR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_OP_FAULT_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by sync configurations fault.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "ICACHE_PRELOAD_OP_FAULT_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by preload configurations fault.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MMU_ENTRY_FAULT_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by mmu entry fault.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IBUS_CNT_OVF_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by ibus counter overflow.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DBUS_CNT_OVF_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by dbus counter overflow.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CACHE_ILG_INT_ST": {
-              "description": "This description will be updated in the near future.",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_OP_FAULT_ST": {
-                    "description": "The bit is used to indicate interrupt by sync configurations fault.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ICACHE_PRELOAD_OP_FAULT_ST": {
-                    "description": "The bit is used to indicate interrupt by preload configurations fault.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MMU_ENTRY_FAULT_ST": {
-                    "description": "The bit is used to indicate interrupt by mmu entry fault.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IBUS_ACS_CNT_OVF_ST": {
-                    "description": "The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IBUS_ACS_MISS_CNT_OVF_ST": {
-                    "description": "The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DBUS_ACS_CNT_OVF_ST": {
-                    "description": "The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DBUS_ACS_FLASH_MISS_CNT_OVF_ST": {
-                    "description": "The bit is used to indicate interrupt by dbus access flash miss counter overflow.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE0_ACS_CACHE_INT_ENA": {
-              "description": "This description will be updated in the near future.",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_IBUS_ACS_MSK_IC_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE0_IBUS_WR_IC_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by ibus trying to write icache",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CORE0_IBUS_REJECT_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by authentication fail.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CORE0_DBUS_ACS_MSK_IC_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CORE0_DBUS_REJECT_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by authentication fail.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CORE0_DBUS_WR_IC_INT_ENA": {
-                    "description": "The bit is used to enable interrupt by dbus trying to write icache",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE0_ACS_CACHE_INT_CLR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_IBUS_ACS_MSK_IC_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CORE0_IBUS_WR_IC_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by ibus trying to write icache",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CORE0_IBUS_REJECT_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by authentication fail.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CORE0_DBUS_ACS_MSK_IC_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CORE0_DBUS_REJECT_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by authentication fail.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CORE0_DBUS_WR_IC_INT_CLR": {
-                    "description": "The bit is used to clear interrupt by dbus trying to write icache",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CORE0_ACS_CACHE_INT_ST": {
-              "description": "This description will be updated in the near future.",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_IBUS_ACS_MSK_ICACHE_ST": {
-                    "description": "The bit is used to indicate interrupt by cpu access  icache while the core0_ibus is disabled or icache is disabled which include speculative access.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE0_IBUS_WR_ICACHE_ST": {
-                    "description": "The bit is used to indicate interrupt by ibus trying to write icache",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE0_IBUS_REJECT_ST": {
-                    "description": "The bit is used to indicate interrupt by authentication fail.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE0_DBUS_ACS_MSK_ICACHE_ST": {
-                    "description": "The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE0_DBUS_REJECT_ST": {
-                    "description": "The bit is used to indicate interrupt by authentication fail.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE0_DBUS_WR_ICACHE_ST": {
-                    "description": "The bit is used to indicate interrupt by dbus trying to write icache",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE0_DBUS_REJECT_ST": {
-              "description": "This description will be updated in the near future.",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_DBUS_ATTR": {
-                    "description": "The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "CORE0_DBUS_WORLD": {
-                    "description": "The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE0_DBUS_REJECT_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_DBUS_VADDR": {
-                    "description": "The bits are used to indicate the virtual address of CPU access dbus when authentication fail.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE0_IBUS_REJECT_ST": {
-              "description": "This description will be updated in the near future.",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_IBUS_ATTR": {
-                    "description": "The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "CORE0_IBUS_WORLD": {
-                    "description": "The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE0_IBUS_REJECT_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE0_IBUS_VADDR": {
-                    "description": "The bits are used to indicate the virtual address of CPU access  ibus when authentication fail.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_FAULT_CONTENT": {
-              "description": "This description will be updated in the near future.",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_MMU_FAULT_CONTENT": {
-                    "description": "The bits are used to indicate the content of mmu entry which cause mmu fault..",
-                    "offset": 0,
-                    "size": 10,
-                    "access": "read-only"
-                  },
-                  "CACHE_MMU_FAULT_CODE": {
-                    "description": "The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.",
-                    "offset": 10,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_FAULT_VADDR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_MMU_FAULT_VADDR": {
-                    "description": "The bits are used to indicate the virtual address which cause mmu fault..",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_WRAP_AROUND_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_FLASH_WRAP_AROUND": {
-                    "description": "The bit is used to enable wrap around mode when read data from flash.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_POWER_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 5,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_MMU_MEM_FORCE_ON": {
-                    "description": "The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CACHE_MMU_MEM_FORCE_PD": {
-                    "description": "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CACHE_MMU_MEM_FORCE_PU": {
-                    "description": "The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_STATE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_STATE": {
-                    "description": "The bit is used to indicate whether  icache main fsm is in idle state or not. 1: in idle state,  0: not in idle state",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RECORD_DISABLE_DB_ENCRYPT": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "RECORD_DISABLE_G0CB_DECRYPT": {
-                    "description": "Reserved.",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON": {
-              "description": "This description will be updated in the near future.",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 7,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_FORCE_ON_MANUAL_CRYPT": {
-                    "description": "The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CLK_FORCE_ON_AUTO_CRYPT": {
-                    "description": "The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CLK_FORCE_ON_CRYPT": {
-                    "description": "The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_PRELOAD_INT_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOAD_INT_ST": {
-                    "description": "The bit is used to indicate the interrupt by  icache pre-load done.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ICACHE_PRELOAD_INT_ENA": {
-                    "description": "The bit is used to enable the interrupt by  icache pre-load done.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ICACHE_PRELOAD_INT_CLR": {
-                    "description": "The bit is used to clear the interrupt by  icache pre-load done.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CACHE_SYNC_INT_CTRL": {
-              "description": "This description will be updated in the near future.",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_INT_ST": {
-                    "description": "The bit is used to indicate the interrupt by  icache sync done.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ICACHE_SYNC_INT_ENA": {
-                    "description": "The bit is used to enable the interrupt by  icache sync done.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ICACHE_SYNC_INT_CLR": {
-                    "description": "The bit is used to clear the interrupt by  icache sync done.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_OWNER": {
-              "description": "This description will be updated in the near future.",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_MMU_OWNER": {
-                    "description": "The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CACHE_CONF_MISC": {
-              "description": "This description will be updated in the near future.",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 7,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT": {
-                    "description": "The bit is used to disable checking mmu entry fault by preload operation.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT": {
-                    "description": "The bit is used to disable checking mmu entry fault by sync operation.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CACHE_TRACE_ENA": {
-                    "description": "The bit is used to enable cache trace function.",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ICACHE_FREEZE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENA": {
-                    "description": "The bit is used to enable icache freeze mode",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MODE": {
-                    "description": "The bit is used to configure freeze mode, 0:  assert busy if CPU miss 1: assert hit if CPU miss",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "DONE": {
-                    "description": "The bit is used to indicate icache freeze success",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ICACHE_ATOMIC_OPERATE_ENA": {
-              "description": "This description will be updated in the near future.",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_ATOMIC_OPERATE_ENA": {
-                    "description": "The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_REQUEST": {
-              "description": "This description will be updated in the near future.",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BYPASS": {
-                    "description": "The bit is used to disable request recording which could cause performance issue",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IBUS_PMS_TBL_LOCK": {
-              "description": "This description will be updated in the near future.",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_PMS_LOCK": {
-                    "description": "The bit is used to configure the ibus permission control section boundary0",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "IBUS_PMS_TBL_BOUNDARY0": {
-              "description": "This description will be updated in the near future.",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_PMS_BOUNDARY0": {
-                    "description": "The bit is used to configure the ibus permission control section boundary0",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "IBUS_PMS_TBL_BOUNDARY1": {
-              "description": "This description will be updated in the near future.",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_PMS_BOUNDARY1": {
-                    "description": "The bit is used to configure the ibus permission control section boundary1",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "IBUS_PMS_TBL_BOUNDARY2": {
-              "description": "This description will be updated in the near future.",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_PMS_BOUNDARY2": {
-                    "description": "The bit is used to configure the ibus permission control section boundary2",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "IBUS_PMS_TBL_ATTR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 255,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IBUS_PMS_SCT1_ATTR": {
-                    "description": "The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "IBUS_PMS_SCT2_ATTR": {
-                    "description": "The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1",
-                    "offset": 4,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "DBUS_PMS_TBL_LOCK": {
-              "description": "This description will be updated in the near future.",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_PMS_LOCK": {
-                    "description": "The bit is used to configure the ibus permission control section boundary0",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DBUS_PMS_TBL_BOUNDARY0": {
-              "description": "This description will be updated in the near future.",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_PMS_BOUNDARY0": {
-                    "description": "The bit is used to configure the dbus permission control section boundary0",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "DBUS_PMS_TBL_BOUNDARY1": {
-              "description": "This description will be updated in the near future.",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_PMS_BOUNDARY1": {
-                    "description": "The bit is used to configure the dbus permission control section boundary1",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "DBUS_PMS_TBL_BOUNDARY2": {
-              "description": "This description will be updated in the near future.",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 2048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_PMS_BOUNDARY2": {
-                    "description": "The bit is used to configure the dbus permission control section boundary2",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "DBUS_PMS_TBL_ATTR": {
-              "description": "This description will be updated in the near future.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 15,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DBUS_PMS_SCT1_ATTR": {
-                    "description": "The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DBUS_PMS_SCT2_ATTR": {
-                    "description": "The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1",
-                    "offset": 2,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "clock gate enable.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "REG_DATE": {
-              "description": "This description will be updated in the near future.",
-              "offset": 1020,
-              "size": 32,
-              "reset_value": 33583456,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "version information",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "GPIO": {
-        "description": "General Purpose Input/Output",
-        "children": {
-          "registers": {
-            "BT_SELECT": {
-              "description": "GPIO bit select register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_SEL": {
-                    "description": "GPIO bit select register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "OUT": {
-              "description": "GPIO output register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA_ORIG": {
-                    "description": "GPIO output register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26
-                  }
-                }
-              }
-            },
-            "OUT_W1TS": {
-              "description": "GPIO output set register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_W1TS": {
-                    "description": "GPIO output set register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "OUT_W1TC": {
-              "description": "GPIO output clear register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_W1TC": {
-                    "description": "GPIO output clear register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SDIO_SELECT": {
-              "description": "GPIO sdio select register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SDIO_SEL": {
-                    "description": "GPIO sdio select register",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "ENABLE": {
-              "description": "GPIO output enable register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "GPIO output enable register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26
-                  }
-                }
-              }
-            },
-            "ENABLE_W1TS": {
-              "description": "GPIO output enable set register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENABLE_W1TS": {
-                    "description": "GPIO output enable set register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "ENABLE_W1TC": {
-              "description": "GPIO output enable clear register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENABLE_W1TC": {
-                    "description": "GPIO output enable clear register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STRAP": {
-              "description": "pad strapping register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STRAPPING": {
-                    "description": "pad strapping register",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN": {
-              "description": "GPIO input register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA_NEXT": {
-                    "description": "GPIO input register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "STATUS": {
-              "description": "GPIO interrupt status register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERRUPT": {
-                    "description": "GPIO interrupt status register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26
-                  }
-                }
-              }
-            },
-            "STATUS_W1TS": {
-              "description": "GPIO interrupt status set register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATUS_W1TS": {
-                    "description": "GPIO interrupt status set register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STATUS_W1TC": {
-              "description": "GPIO interrupt status clear register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATUS_W1TC": {
-                    "description": "GPIO interrupt status clear register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "PCPU_INT": {
-              "description": "GPIO PRO_CPU interrupt status register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PROCPU_INT": {
-                    "description": "GPIO PRO_CPU interrupt status register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PCPU_NMI_INT": {
-              "description": "GPIO PRO_CPU(not shielded) interrupt status register",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PROCPU_NMI_INT": {
-                    "description": "GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CPUSDIO_INT": {
-              "description": "GPIO CPUSDIO interrupt status register",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SDIO_INT": {
-                    "description": "GPIO CPUSDIO interrupt status register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PIN": {
-              "description": "GPIO pin configuration register",
-              "offset": 116,
-              "size": 32,
-              "count": 26,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PIN_SYNC2_BYPASS": {
-                    "description": "set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "PIN_PAD_DRIVER": {
-                    "description": "set this bit to select pad driver. 1:open-drain. :normal.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "PIN_SYNC1_BYPASS": {
-                    "description": "set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.",
-                    "offset": 3,
-                    "size": 2
-                  },
-                  "PIN_INT_TYPE": {
-                    "description": "set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level",
-                    "offset": 7,
-                    "size": 3
-                  },
-                  "PIN_WAKEUP_ENABLE": {
-                    "description": "set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "PIN_CONFIG": {
-                    "description": "reserved",
-                    "offset": 11,
-                    "size": 2
-                  },
-                  "PIN_INT_ENA": {
-                    "description": "set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.",
-                    "offset": 13,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "STATUS_NEXT": {
-              "description": "GPIO interrupt source register",
-              "offset": 332,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATUS_INTERRUPT_NEXT": {
-                    "description": "GPIO interrupt source register for GPIO0-25",
-                    "offset": 0,
-                    "size": 26,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "FUNC_IN_SEL_CFG": {
-              "description": "GPIO input function configuration register",
-              "offset": 340,
-              "size": 32,
-              "count": 128,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_SEL": {
-                    "description": "set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level.",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "IN_INV_SEL": {
-                    "description": "set this bit to invert input signal. 1:invert. :not invert.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "SEL": {
-                    "description": "set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.",
-                    "offset": 6,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FUNC_OUT_SEL_CFG": {
-              "description": "GPIO output function select register",
-              "offset": 1364,
-              "size": 32,
-              "count": 26,
-              "reset_value": 128,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_SEL": {
-                    "description": "The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "INV_SEL": {
-                    "description": "set this bit to invert output signal.1:invert.:not invert.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "OEN_SEL": {
-                    "description": "set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "OEN_INV_SEL": {
-                    "description": "set this bit to invert output enable signal.1:invert.:not invert.",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "GPIO clock gate register",
-              "offset": 1580,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "set this bit to enable GPIO clock gate",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "REG_DATE": {
-              "description": "GPIO version register",
-              "offset": 1788,
-              "size": 32,
-              "reset_value": 33579312,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REG_DATE": {
-                    "description": "version register",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "GPIOSD": {
-        "description": "Sigma-Delta Modulation",
-        "children": {
-          "registers": {
-            "SIGMADELTA": {
-              "description": "Duty Cycle Configure Register of SDM%s",
-              "offset": 0,
-              "size": 32,
-              "count": 4,
-              "reset_value": 65280,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SD0_IN": {
-                    "description": "This field is used to configure the duty cycle of sigma delta modulation output.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "SD0_PRESCALE": {
-                    "description": "This field is used to set a divider value to divide APB clock.",
-                    "offset": 8,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "SIGMADELTA_CG": {
-              "description": "Clock Gating Configure Register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "Clock enable bit of configuration registers for sigma delta modulation.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SIGMADELTA_MISC": {
-              "description": "MISC Register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FUNCTION_CLK_EN": {
-                    "description": "Clock enable bit of sigma delta modulation.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SPI_SWAP": {
-                    "description": "Reserved.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SIGMADELTA_VERSION": {
-              "description": "Version Control Register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 33579568,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "GPIO_SD_DATE": {
-                    "description": "Version control register.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "HMAC": {
-        "description": "HMAC (Hash-based Message Authentication Code) Accelerator",
-        "children": {
-          "registers": {
-            "SET_START": {
-              "description": "Process control register 0.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_START": {
-                    "description": "Start hmac operation.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_PARA_PURPOSE": {
-              "description": "Configure purpose.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PURPOSE_SET": {
-                    "description": "Set hmac parameter purpose.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_PARA_KEY": {
-              "description": "Configure key.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "KEY_SET": {
-                    "description": "Set hmac parameter key.",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_PARA_FINISH": {
-              "description": "Finish initial configuration.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_PARA_END": {
-                    "description": "Finish hmac configuration.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_MESSAGE_ONE": {
-              "description": "Process control register 1.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_TEXT_ONE": {
-                    "description": "Call SHA to calculate one message block.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_MESSAGE_ING": {
-              "description": "Process control register 2.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_TEXT_ING": {
-                    "description": "Continue typical hmac.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_MESSAGE_END": {
-              "description": "Process control register 3.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_TEXT_END": {
-                    "description": "Start hardware padding.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_RESULT_FINISH": {
-              "description": "Process control register 4.",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_RESULT_END": {
-                    "description": "After read result from upstream, then let hmac back to idle.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_INVALIDATE_JTAG": {
-              "description": "Invalidate register 0.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_INVALIDATE_JTAG": {
-                    "description": "Clear result from hmac downstream JTAG.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_INVALIDATE_DS": {
-              "description": "Invalidate register 1.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_INVALIDATE_DS": {
-                    "description": "Clear result from hmac downstream DS.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "QUERY_ERROR": {
-              "description": "Error register.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "QUREY_CHECK": {
-                    "description": "Hmac configuration state. 0: key are agree with purpose. 1: error",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "QUERY_BUSY": {
-              "description": "Busy register.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUSY_STATE": {
-                    "description": "Hmac state. 1'b0: idle. 1'b1: busy",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "WR_MESSAGE_MEM": {
-              "description": "Message block memory.",
-              "offset": 128,
-              "size": 8,
-              "count": 64,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "RD_RESULT_MEM": {
-              "description": "Result from upstream.",
-              "offset": 192,
-              "size": 8,
-              "count": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "SET_MESSAGE_PAD": {
-              "description": "Process control register 5.",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_TEXT_PAD": {
-                    "description": "Start software padding.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "ONE_BLOCK": {
-              "description": "Process control register 6.",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_ONE_BLOCK": {
-                    "description": "Don't have to do padding.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SOFT_JTAG_CTRL": {
-              "description": "Jtag register 0.",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SOFT_JTAG_CTRL": {
-                    "description": "Turn on JTAG verification.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "WR_JTAG": {
-              "description": "Jtag register 1.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WR_JTAG": {
-                    "description": "32-bit of key to be compared.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "write-only"
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "I2C0": {
-        "description": "I2C (Inter-Integrated Circuit) Controller",
-        "children": {
-          "registers": {
-            "SCL_LOW_PERIOD": {
-              "description": "I2C_SCL_LOW_PERIOD_REG",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_LOW_PERIOD": {
-                    "description": "reg_scl_low_period",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "CTR": {
-              "description": "I2C_CTR_REG",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 523,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SDA_FORCE_OUT": {
-                    "description": "reg_sda_force_out",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SCL_FORCE_OUT": {
-                    "description": "reg_scl_force_out",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SAMPLE_SCL_LEVEL": {
-                    "description": "reg_sample_scl_level",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RX_FULL_ACK_LEVEL": {
-                    "description": "reg_rx_full_ack_level",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MS_MODE": {
-                    "description": "reg_ms_mode",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "TRANS_START": {
-                    "description": "reg_trans_start",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_LSB_FIRST": {
-                    "description": "reg_tx_lsb_first",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "RX_LSB_FIRST": {
-                    "description": "reg_rx_lsb_first",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "ARBITRATION_EN": {
-                    "description": "reg_arbitration_en",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "FSM_RST": {
-                    "description": "reg_fsm_rst",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CONF_UPGATE": {
-                    "description": "reg_conf_upgate",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_TX_AUTO_START_EN": {
-                    "description": "reg_slv_tx_auto_start_en",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "ADDR_10BIT_RW_CHECK_EN": {
-                    "description": "reg_addr_10bit_rw_check_en",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "ADDR_BROADCASTING_EN": {
-                    "description": "reg_addr_broadcasting_en",
-                    "offset": 14,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SR": {
-              "description": "I2C_SR_REG",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 49152,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RESP_REC": {
-                    "description": "reg_resp_rec",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLAVE_RW": {
-                    "description": "reg_slave_rw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ARB_LOST": {
-                    "description": "reg_arb_lost",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BUS_BUSY": {
-                    "description": "reg_bus_busy",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLAVE_ADDRESSED": {
-                    "description": "reg_slave_addressed",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_CNT": {
-                    "description": "reg_rxfifo_cnt",
-                    "offset": 8,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "STRETCH_CAUSE": {
-                    "description": "reg_stretch_cause",
-                    "offset": 14,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_CNT": {
-                    "description": "reg_txfifo_cnt",
-                    "offset": 18,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "SCL_MAIN_STATE_LAST": {
-                    "description": "reg_scl_main_state_last",
-                    "offset": 24,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "SCL_STATE_LAST": {
-                    "description": "reg_scl_state_last",
-                    "offset": 28,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "TO": {
-              "description": "I2C_TO_REG",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 16,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME_OUT_VALUE": {
-                    "description": "reg_time_out_value",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "TIME_OUT_EN": {
-                    "description": "reg_time_out_en",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLAVE_ADDR": {
-              "description": "I2C_SLAVE_ADDR_REG",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLAVE_ADDR": {
-                    "description": "reg_slave_addr",
-                    "offset": 0,
-                    "size": 15
-                  },
-                  "ADDR_10BIT_EN": {
-                    "description": "reg_addr_10bit_en",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FIFO_ST": {
-              "description": "I2C_FIFO_ST_REG",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_RADDR": {
-                    "description": "reg_rxfifo_raddr",
-                    "offset": 0,
-                    "size": 5,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_WADDR": {
-                    "description": "reg_rxfifo_waddr",
-                    "offset": 5,
-                    "size": 5,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_RADDR": {
-                    "description": "reg_txfifo_raddr",
-                    "offset": 10,
-                    "size": 5,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_WADDR": {
-                    "description": "reg_txfifo_waddr",
-                    "offset": 15,
-                    "size": 5,
-                    "access": "read-only"
-                  },
-                  "SLAVE_RW_POINT": {
-                    "description": "reg_slave_rw_point",
-                    "offset": 22,
-                    "size": 8,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "FIFO_CONF": {
-              "description": "I2C_FIFO_CONF_REG",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 16523,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_WM_THRHD": {
-                    "description": "reg_rxfifo_wm_thrhd",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "TXFIFO_WM_THRHD": {
-                    "description": "reg_txfifo_wm_thrhd",
-                    "offset": 5,
-                    "size": 5
-                  },
-                  "NONFIFO_EN": {
-                    "description": "reg_nonfifo_en",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "FIFO_ADDR_CFG_EN": {
-                    "description": "reg_fifo_addr_cfg_en",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "RX_FIFO_RST": {
-                    "description": "reg_rx_fifo_rst",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TX_FIFO_RST": {
-                    "description": "reg_tx_fifo_rst",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "FIFO_PRT_EN": {
-                    "description": "reg_fifo_prt_en",
-                    "offset": 14,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATA": {
-              "description": "I2C_FIFO_DATA_REG",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FIFO_RDATA": {
-                    "description": "reg_fifo_rdata",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "I2C_INT_RAW_REG",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_WM_INT_RAW": {
-                    "description": "reg_rxfifo_wm_int_raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_WM_INT_RAW": {
-                    "description": "reg_txfifo_wm_int_raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_OVF_INT_RAW": {
-                    "description": "reg_rxfifo_ovf_int_raw",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "END_DETECT_INT_RAW": {
-                    "description": "reg_end_detect_int_raw",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BYTE_TRANS_DONE_INT_RAW": {
-                    "description": "reg_byte_trans_done_int_raw",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ARBITRATION_LOST_INT_RAW": {
-                    "description": "reg_arbitration_lost_int_raw",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_TXFIFO_UDF_INT_RAW": {
-                    "description": "reg_mst_txfifo_udf_int_raw",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TRANS_COMPLETE_INT_RAW": {
-                    "description": "reg_trans_complete_int_raw",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TIME_OUT_INT_RAW": {
-                    "description": "reg_time_out_int_raw",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TRANS_START_INT_RAW": {
-                    "description": "reg_trans_start_int_raw",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "NACK_INT_RAW": {
-                    "description": "reg_nack_int_raw",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_OVF_INT_RAW": {
-                    "description": "reg_txfifo_ovf_int_raw",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_UDF_INT_RAW": {
-                    "description": "reg_rxfifo_udf_int_raw",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SCL_ST_TO_INT_RAW": {
-                    "description": "reg_scl_st_to_int_raw",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SCL_MAIN_ST_TO_INT_RAW": {
-                    "description": "reg_scl_main_st_to_int_raw",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DET_START_INT_RAW": {
-                    "description": "reg_det_start_int_raw",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLAVE_STRETCH_INT_RAW": {
-                    "description": "reg_slave_stretch_int_raw",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "GENERAL_CALL_INT_RAW": {
-                    "description": "reg_general_call_int_raw",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "I2C_INT_CLR_REG",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_WM_INT_CLR": {
-                    "description": "reg_rxfifo_wm_int_clr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TXFIFO_WM_INT_CLR": {
-                    "description": "reg_txfifo_wm_int_clr",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RXFIFO_OVF_INT_CLR": {
-                    "description": "reg_rxfifo_ovf_int_clr",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "END_DETECT_INT_CLR": {
-                    "description": "reg_end_detect_int_clr",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "BYTE_TRANS_DONE_INT_CLR": {
-                    "description": "reg_byte_trans_done_int_clr",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "ARBITRATION_LOST_INT_CLR": {
-                    "description": "reg_arbitration_lost_int_clr",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MST_TXFIFO_UDF_INT_CLR": {
-                    "description": "reg_mst_txfifo_udf_int_clr",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TRANS_COMPLETE_INT_CLR": {
-                    "description": "reg_trans_complete_int_clr",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TIME_OUT_INT_CLR": {
-                    "description": "reg_time_out_int_clr",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TRANS_START_INT_CLR": {
-                    "description": "reg_trans_start_int_clr",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "NACK_INT_CLR": {
-                    "description": "reg_nack_int_clr",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TXFIFO_OVF_INT_CLR": {
-                    "description": "reg_txfifo_ovf_int_clr",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RXFIFO_UDF_INT_CLR": {
-                    "description": "reg_rxfifo_udf_int_clr",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SCL_ST_TO_INT_CLR": {
-                    "description": "reg_scl_st_to_int_clr",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SCL_MAIN_ST_TO_INT_CLR": {
-                    "description": "reg_scl_main_st_to_int_clr",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DET_START_INT_CLR": {
-                    "description": "reg_det_start_int_clr",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLAVE_STRETCH_INT_CLR": {
-                    "description": "reg_slave_stretch_int_clr",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "GENERAL_CALL_INT_CLR": {
-                    "description": "reg_general_call_int_clr",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "I2C_INT_ENA_REG",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_WM_INT_ENA": {
-                    "description": "reg_rxfifo_wm_int_ena",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TXFIFO_WM_INT_ENA": {
-                    "description": "reg_txfifo_wm_int_ena",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RXFIFO_OVF_INT_ENA": {
-                    "description": "reg_rxfifo_ovf_int_ena",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "END_DETECT_INT_ENA": {
-                    "description": "reg_end_detect_int_ena",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "BYTE_TRANS_DONE_INT_ENA": {
-                    "description": "reg_byte_trans_done_int_ena",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "ARBITRATION_LOST_INT_ENA": {
-                    "description": "reg_arbitration_lost_int_ena",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "MST_TXFIFO_UDF_INT_ENA": {
-                    "description": "reg_mst_txfifo_udf_int_ena",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "TRANS_COMPLETE_INT_ENA": {
-                    "description": "reg_trans_complete_int_ena",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "TIME_OUT_INT_ENA": {
-                    "description": "reg_time_out_int_ena",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "TRANS_START_INT_ENA": {
-                    "description": "reg_trans_start_int_ena",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "NACK_INT_ENA": {
-                    "description": "reg_nack_int_ena",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "TXFIFO_OVF_INT_ENA": {
-                    "description": "reg_txfifo_ovf_int_ena",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "RXFIFO_UDF_INT_ENA": {
-                    "description": "reg_rxfifo_udf_int_ena",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "SCL_ST_TO_INT_ENA": {
-                    "description": "reg_scl_st_to_int_ena",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "SCL_MAIN_ST_TO_INT_ENA": {
-                    "description": "reg_scl_main_st_to_int_ena",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "DET_START_INT_ENA": {
-                    "description": "reg_det_start_int_ena",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SLAVE_STRETCH_INT_ENA": {
-                    "description": "reg_slave_stretch_int_ena",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "GENERAL_CALL_INT_ENA": {
-                    "description": "reg_general_call_int_ena",
-                    "offset": 17,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_STATUS": {
-              "description": "I2C_INT_STATUS_REG",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_WM_INT_ST": {
-                    "description": "reg_rxfifo_wm_int_st",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_WM_INT_ST": {
-                    "description": "reg_txfifo_wm_int_st",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_OVF_INT_ST": {
-                    "description": "reg_rxfifo_ovf_int_st",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "END_DETECT_INT_ST": {
-                    "description": "reg_end_detect_int_st",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BYTE_TRANS_DONE_INT_ST": {
-                    "description": "reg_byte_trans_done_int_st",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ARBITRATION_LOST_INT_ST": {
-                    "description": "reg_arbitration_lost_int_st",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_TXFIFO_UDF_INT_ST": {
-                    "description": "reg_mst_txfifo_udf_int_st",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TRANS_COMPLETE_INT_ST": {
-                    "description": "reg_trans_complete_int_st",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TIME_OUT_INT_ST": {
-                    "description": "reg_time_out_int_st",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TRANS_START_INT_ST": {
-                    "description": "reg_trans_start_int_st",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "NACK_INT_ST": {
-                    "description": "reg_nack_int_st",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_OVF_INT_ST": {
-                    "description": "reg_txfifo_ovf_int_st",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_UDF_INT_ST": {
-                    "description": "reg_rxfifo_udf_int_st",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SCL_ST_TO_INT_ST": {
-                    "description": "reg_scl_st_to_int_st",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SCL_MAIN_ST_TO_INT_ST": {
-                    "description": "reg_scl_main_st_to_int_st",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DET_START_INT_ST": {
-                    "description": "reg_det_start_int_st",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLAVE_STRETCH_INT_ST": {
-                    "description": "reg_slave_stretch_int_st",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "GENERAL_CALL_INT_ST": {
-                    "description": "reg_general_call_int_st",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SDA_HOLD": {
-              "description": "I2C_SDA_HOLD_REG",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_sda_hold_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "SDA_SAMPLE": {
-              "description": "I2C_SDA_SAMPLE_REG",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_sda_sample_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "SCL_HIGH_PERIOD": {
-              "description": "I2C_SCL_HIGH_PERIOD_REG",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_HIGH_PERIOD": {
-                    "description": "reg_scl_high_period",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "SCL_WAIT_HIGH_PERIOD": {
-                    "description": "reg_scl_wait_high_period",
-                    "offset": 9,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "SCL_START_HOLD": {
-              "description": "I2C_SCL_START_HOLD_REG",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_scl_start_hold_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "SCL_RSTART_SETUP": {
-              "description": "I2C_SCL_RSTART_SETUP_REG",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_scl_rstart_setup_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "SCL_STOP_HOLD": {
-              "description": "I2C_SCL_STOP_HOLD_REG",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_scl_stop_hold_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "SCL_STOP_SETUP": {
-              "description": "I2C_SCL_STOP_SETUP_REG",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME": {
-                    "description": "reg_scl_stop_setup_time",
-                    "offset": 0,
-                    "size": 9
-                  }
-                }
-              }
-            },
-            "FILTER_CFG": {
-              "description": "I2C_FILTER_CFG_REG",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 768,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_FILTER_THRES": {
-                    "description": "reg_scl_filter_thres",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "SDA_FILTER_THRES": {
-                    "description": "reg_sda_filter_thres",
-                    "offset": 4,
-                    "size": 4
-                  },
-                  "SCL_FILTER_EN": {
-                    "description": "reg_scl_filter_en",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "SDA_FILTER_EN": {
-                    "description": "reg_sda_filter_en",
-                    "offset": 9,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLK_CONF": {
-              "description": "I2C_CLK_CONF_REG",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 2097152,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCLK_DIV_NUM": {
-                    "description": "reg_sclk_div_num",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "SCLK_DIV_A": {
-                    "description": "reg_sclk_div_a",
-                    "offset": 8,
-                    "size": 6
-                  },
-                  "SCLK_DIV_B": {
-                    "description": "reg_sclk_div_b",
-                    "offset": 14,
-                    "size": 6
-                  },
-                  "SCLK_SEL": {
-                    "description": "reg_sclk_sel",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "SCLK_ACTIVE": {
-                    "description": "reg_sclk_active",
-                    "offset": 21,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "COMD": {
-              "description": "I2C_COMD%s_REG",
-              "offset": 88,
-              "size": 32,
-              "count": 8,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMMAND": {
-                    "description": "reg_command",
-                    "offset": 0,
-                    "size": 14
-                  },
-                  "COMMAND_DONE": {
-                    "description": "reg_command_done",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SCL_ST_TIME_OUT": {
-              "description": "I2C_SCL_ST_TIME_OUT_REG",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 16,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_ST_TO_I2C": {
-                    "description": "reg_scl_st_to_regno more than 23",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SCL_MAIN_ST_TIME_OUT": {
-              "description": "I2C_SCL_MAIN_ST_TIME_OUT_REG",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 16,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_MAIN_ST_TO_I2C": {
-                    "description": "reg_scl_main_st_to_regno more than 23",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SCL_SP_CONF": {
-              "description": "I2C_SCL_SP_CONF_REG",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCL_RST_SLV_EN": {
-                    "description": "reg_scl_rst_slv_en",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SCL_RST_SLV_NUM": {
-                    "description": "reg_scl_rst_slv_num",
-                    "offset": 1,
-                    "size": 5
-                  },
-                  "SCL_PD_EN": {
-                    "description": "reg_scl_pd_en",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SDA_PD_EN": {
-                    "description": "reg_sda_pd_en",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SCL_STRETCH_CONF": {
-              "description": "I2C_SCL_STRETCH_CONF_REG",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STRETCH_PROTECT_NUM": {
-                    "description": "reg_stretch_protect_num",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "SLAVE_SCL_STRETCH_EN": {
-                    "description": "reg_slave_scl_stretch_en",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "SLAVE_SCL_STRETCH_CLR": {
-                    "description": "reg_slave_scl_stretch_clr",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLAVE_BYTE_ACK_CTL_EN": {
-                    "description": "reg_slave_byte_ack_ctl_en",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "SLAVE_BYTE_ACK_LVL": {
-                    "description": "reg_slave_byte_ack_lvl",
-                    "offset": 13,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "I2C_DATE_REG",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 537330177,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "reg_date",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TXFIFO_START_ADDR": {
-              "description": "I2C_TXFIFO_START_ADDR_REG",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TXFIFO_START_ADDR": {
-                    "description": "reg_txfifo_start_addr.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RXFIFO_START_ADDR": {
-              "description": "I2C_RXFIFO_START_ADDR_REG",
-              "offset": 384,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_START_ADDR": {
-                    "description": "reg_rxfifo_start_addr.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "I2S": {
-        "description": "I2S (Inter-IC Sound) Controller",
-        "children": {
-          "registers": {
-            "INT_RAW": {
-              "description": "I2S interrupt raw register, valid in level.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_DONE_INT_RAW": {
-                    "description": "The raw interrupt status bit  for the i2s_rx_done_int interrupt",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_DONE_INT_RAW": {
-                    "description": "The raw interrupt status bit  for the i2s_tx_done_int interrupt",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RX_HUNG_INT_RAW": {
-                    "description": "The raw interrupt status bit  for the i2s_rx_hung_int interrupt",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_HUNG_INT_RAW": {
-                    "description": "The raw interrupt status bit  for the i2s_tx_hung_int interrupt",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "I2S interrupt status register.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_DONE_INT_ST": {
-                    "description": "The masked interrupt status bit  for the i2s_rx_done_int interrupt",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_DONE_INT_ST": {
-                    "description": "The masked interrupt status bit  for the i2s_tx_done_int interrupt",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RX_HUNG_INT_ST": {
-                    "description": "The masked interrupt status bit  for the i2s_rx_hung_int interrupt",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_HUNG_INT_ST": {
-                    "description": "The masked interrupt status bit  for the i2s_tx_hung_int interrupt",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "I2S interrupt enable register.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_DONE_INT_ENA": {
-                    "description": "The interrupt enable bit  for the i2s_rx_done_int interrupt",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_DONE_INT_ENA": {
-                    "description": "The interrupt enable bit  for the i2s_tx_done_int interrupt",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RX_HUNG_INT_ENA": {
-                    "description": "The interrupt enable bit  for the i2s_rx_hung_int interrupt",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "TX_HUNG_INT_ENA": {
-                    "description": "The interrupt enable bit  for the i2s_tx_hung_int interrupt",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "I2S interrupt clear register.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_DONE_INT_CLR": {
-                    "description": "Set this bit to clear the i2s_rx_done_int interrupt",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_DONE_INT_CLR": {
-                    "description": "Set this bit to clear the i2s_tx_done_int interrupt",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RX_HUNG_INT_CLR": {
-                    "description": "Set this bit to clear the i2s_rx_hung_int interrupt",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_HUNG_INT_CLR": {
-                    "description": "Set this bit to clear the i2s_tx_hung_int interrupt",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "RX_CONF": {
-              "description": "I2S RX configure register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 38400,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_RESET": {
-                    "description": "Set this bit to reset receiver",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RX_FIFO_RESET": {
-                    "description": "Set this bit to reset Rx AFIFO",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RX_START": {
-                    "description": "Set this bit to start receiving data",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RX_SLAVE_MOD": {
-                    "description": "Set this bit to enable slave receiver mode",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RX_MONO": {
-                    "description": "Set this bit to enable receiver  in mono mode",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "RX_BIG_ENDIAN": {
-                    "description": "I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RX_UPDATE": {
-                    "description": "Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "RX_MONO_FST_VLD": {
-                    "description": "1: The first channel data value is valid in I2S RX mono mode.   0: The second channel data value is valid in I2S RX mono mode.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "RX_PCM_CONF": {
-                    "description": "I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "RX_PCM_BYPASS": {
-                    "description": "Set this bit to bypass Compress/Decompress module for received data.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "RX_STOP_MODE": {
-                    "description": "0  : I2S Rx only stop when reg_rx_start is cleared.   1: Stop when reg_rx_start is 0 or in_suc_eof is 1.   2:  Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.",
-                    "offset": 13,
-                    "size": 2
-                  },
-                  "RX_LEFT_ALIGN": {
-                    "description": "1: I2S RX left alignment mode. 0: I2S RX right alignment mode.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RX_24_FILL_EN": {
-                    "description": "1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "RX_WS_IDLE_POL": {
-                    "description": "0: WS should be 0 when receiving left channel data, and WS is 1in right channel.  1: WS should be 1 when receiving left channel data, and WS is 0in right channel.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "RX_BIT_ORDER": {
-                    "description": "I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "RX_TDM_EN": {
-                    "description": "1: Enable I2S TDM Rx mode . 0: Disable.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "RX_PDM_EN": {
-                    "description": "1: Enable I2S PDM Rx mode . 0: Disable.",
-                    "offset": 20,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_CONF": {
-              "description": "I2S TX configure register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 45568,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_RESET": {
-                    "description": "Set this bit to reset transmitter",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_FIFO_RESET": {
-                    "description": "Set this bit to reset Tx AFIFO",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_START": {
-                    "description": "Set this bit to start transmitting data",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "TX_SLAVE_MOD": {
-                    "description": "Set this bit to enable slave transmitter mode",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "TX_MONO": {
-                    "description": "Set this bit to enable transmitter in mono mode",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "TX_CHAN_EQUAL": {
-                    "description": "1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "TX_BIG_ENDIAN": {
-                    "description": "I2S Tx byte endian, 1: low addr value to high addr.  0: low addr with low addr value.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "TX_UPDATE": {
-                    "description": "Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "TX_MONO_FST_VLD": {
-                    "description": "1: The first channel data value is valid in I2S TX mono mode.   0: The second channel data value is valid in I2S TX mono mode.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "TX_PCM_CONF": {
-                    "description": "I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "TX_PCM_BYPASS": {
-                    "description": "Set this bit to bypass  Compress/Decompress module for transmitted data.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TX_STOP_EN": {
-                    "description": "Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "TX_LEFT_ALIGN": {
-                    "description": "1: I2S TX left alignment mode. 0: I2S TX right alignment mode.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "TX_24_FILL_EN": {
-                    "description": "1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "TX_WS_IDLE_POL": {
-                    "description": "0: WS should be 0 when sending left channel data, and WS is 1in right channel.  1: WS should be 1 when sending left channel data, and WS is 0in right channel.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "TX_BIT_ORDER": {
-                    "description": "I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "TX_TDM_EN": {
-                    "description": "1: Enable I2S TDM Tx mode . 0: Disable.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "TX_PDM_EN": {
-                    "description": "1: Enable I2S PDM Tx mode . 0: Disable.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "TX_CHAN_MOD": {
-                    "description": "I2S transmitter channel mode configuration bits.",
-                    "offset": 24,
-                    "size": 3
-                  },
-                  "SIG_LOOPBACK": {
-                    "description": "Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RX_CONF1": {
-              "description": "I2S RX configure register 1",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 792584960,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_TDM_WS_WIDTH": {
-                    "description": "The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck",
-                    "offset": 0,
-                    "size": 7
-                  },
-                  "RX_BCK_DIV_NUM": {
-                    "description": "Bit clock configuration bits in receiver mode.",
-                    "offset": 7,
-                    "size": 6
-                  },
-                  "RX_BITS_MOD": {
-                    "description": "Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.",
-                    "offset": 13,
-                    "size": 5
-                  },
-                  "RX_HALF_SAMPLE_BITS": {
-                    "description": "I2S Rx half sample bits -1.",
-                    "offset": 18,
-                    "size": 6
-                  },
-                  "RX_TDM_CHAN_BITS": {
-                    "description": "The Rx bit number for each channel minus 1in TDM mode.",
-                    "offset": 24,
-                    "size": 5
-                  },
-                  "RX_MSB_SHIFT": {
-                    "description": "Set this bit to enable receiver in Phillips standard mode",
-                    "offset": 29,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_CONF1": {
-              "description": "I2S TX configure register 1",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 1866326784,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_TDM_WS_WIDTH": {
-                    "description": "The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck",
-                    "offset": 0,
-                    "size": 7
-                  },
-                  "TX_BCK_DIV_NUM": {
-                    "description": "Bit clock configuration bits in transmitter mode.",
-                    "offset": 7,
-                    "size": 6
-                  },
-                  "TX_BITS_MOD": {
-                    "description": "Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.",
-                    "offset": 13,
-                    "size": 5
-                  },
-                  "TX_HALF_SAMPLE_BITS": {
-                    "description": "I2S Tx half sample bits -1.",
-                    "offset": 18,
-                    "size": 6
-                  },
-                  "TX_TDM_CHAN_BITS": {
-                    "description": "The Tx bit number for each channel minus 1in TDM mode.",
-                    "offset": 24,
-                    "size": 5
-                  },
-                  "TX_MSB_SHIFT": {
-                    "description": "Set this bit to enable transmitter in Phillips standard mode",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "TX_BCK_NO_DLY": {
-                    "description": "1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.",
-                    "offset": 30,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RX_CLKM_CONF": {
-              "description": "I2S RX clock configure register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_CLKM_DIV_NUM": {
-                    "description": "Integral I2S clock divider value",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "RX_CLK_ACTIVE": {
-                    "description": "I2S Rx module clock enable signal.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "RX_CLK_SEL": {
-                    "description": "Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.",
-                    "offset": 27,
-                    "size": 2
-                  },
-                  "MCLK_SEL": {
-                    "description": "0: UseI2S Tx module clock as I2S_MCLK_OUT.  1: UseI2S Rx module clock as I2S_MCLK_OUT.",
-                    "offset": 29,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_CLKM_CONF": {
-              "description": "I2S TX clock configure register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_CLKM_DIV_NUM": {
-                    "description": "Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div.  So the average combination will be:  for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "TX_CLK_ACTIVE": {
-                    "description": "I2S Tx module clock enable signal.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "TX_CLK_SEL": {
-                    "description": "Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.",
-                    "offset": 27,
-                    "size": 2
-                  },
-                  "CLK_EN": {
-                    "description": "Set this bit to enable clk gate",
-                    "offset": 29,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RX_CLKM_DIV_CONF": {
-              "description": "I2S RX module clock divider configure register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 512,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_CLKM_DIV_Z": {
-                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "RX_CLKM_DIV_Y": {
-                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).",
-                    "offset": 9,
-                    "size": 9
-                  },
-                  "RX_CLKM_DIV_X": {
-                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.",
-                    "offset": 18,
-                    "size": 9
-                  },
-                  "RX_CLKM_DIV_YN1": {
-                    "description": "For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_CLKM_DIV_CONF": {
-              "description": "I2S TX module clock divider configure register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 512,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_CLKM_DIV_Z": {
-                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "TX_CLKM_DIV_Y": {
-                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).",
-                    "offset": 9,
-                    "size": 9
-                  },
-                  "TX_CLKM_DIV_X": {
-                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.",
-                    "offset": 18,
-                    "size": 9
-                  },
-                  "TX_CLKM_DIV_YN1": {
-                    "description": "For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_PCM2PDM_CONF": {
-              "description": "I2S TX PCM2PDM configuration register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 4890628,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_PDM_HP_BYPASS": {
-                    "description": "I2S TX PDM bypass hp filter or not. The option has been removed.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_PDM_SINC_OSR2": {
-                    "description": "I2S TX PDM OSR2 value",
-                    "offset": 1,
-                    "size": 4
-                  },
-                  "TX_PDM_PRESCALE": {
-                    "description": "I2S TX PDM prescale for sigmadelta",
-                    "offset": 5,
-                    "size": 8
-                  },
-                  "TX_PDM_HP_IN_SHIFT": {
-                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
-                    "offset": 13,
-                    "size": 2
-                  },
-                  "TX_PDM_LP_IN_SHIFT": {
-                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
-                    "offset": 15,
-                    "size": 2
-                  },
-                  "TX_PDM_SINC_IN_SHIFT": {
-                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
-                    "offset": 17,
-                    "size": 2
-                  },
-                  "TX_PDM_SIGMADELTA_IN_SHIFT": {
-                    "description": "I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4",
-                    "offset": 19,
-                    "size": 2
-                  },
-                  "TX_PDM_SIGMADELTA_DITHER2": {
-                    "description": "I2S TX PDM sigmadelta dither2 value",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "TX_PDM_SIGMADELTA_DITHER": {
-                    "description": "I2S TX PDM sigmadelta dither value",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "TX_PDM_DAC_2OUT_EN": {
-                    "description": "I2S TX PDM dac mode enable",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TX_PDM_DAC_MODE_EN": {
-                    "description": "I2S TX PDM dac 2channel enable",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "PCM2PDM_CONV_EN": {
-                    "description": "I2S TX PDM Converter enable",
-                    "offset": 25,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_PCM2PDM_CONF1": {
-              "description": "I2S TX PCM2PDM configuration register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 66552768,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_PDM_FP": {
-                    "description": "I2S TX PDM Fp",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "TX_PDM_FS": {
-                    "description": "I2S TX PDM Fs",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "TX_IIR_HP_MULT12_5": {
-                    "description": "The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])",
-                    "offset": 20,
-                    "size": 3
-                  },
-                  "TX_IIR_HP_MULT12_0": {
-                    "description": "The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])",
-                    "offset": 23,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "RX_TDM_CTRL": {
-              "description": "I2S TX TDM mode control register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 65535,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_TDM_PDM_CHAN0_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0:  Disable, just input 0 in this channel.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN1_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0:  Disable, just input 0 in this channel.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN2_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0:  Disable, just input 0 in this channel.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN3_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0:  Disable, just input 0 in this channel.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN4_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0:  Disable, just input 0 in this channel.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN5_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0:  Disable, just input 0 in this channel.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN6_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0:  Disable, just input 0 in this channel.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "RX_TDM_PDM_CHAN7_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0:  Disable, just input 0 in this channel.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN8_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 8. 0:  Disable, just input 0 in this channel.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN9_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 9. 0:  Disable, just input 0 in this channel.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN10_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 10. 0:  Disable, just input 0 in this channel.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN11_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 11. 0:  Disable, just input 0 in this channel.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN12_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 12. 0:  Disable, just input 0 in this channel.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN13_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 13. 0:  Disable, just input 0 in this channel.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN14_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 14. 0:  Disable, just input 0 in this channel.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "RX_TDM_CHAN15_EN": {
-                    "description": "1: Enable the valid data input of I2S RX TDM channel 15. 0:  Disable, just input 0 in this channel.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RX_TDM_TOT_CHAN_NUM": {
-                    "description": "The total channel number of I2S TX TDM mode.",
-                    "offset": 16,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "TX_TDM_CTRL": {
-              "description": "I2S TX TDM mode control register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 65535,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_TDM_CHAN0_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 0. 0:  Disable, just output 0 in this channel.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN1_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 1. 0:  Disable, just output 0 in this channel.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN2_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 2. 0:  Disable, just output 0 in this channel.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN3_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 3. 0:  Disable, just output 0 in this channel.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN4_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 4. 0:  Disable, just output 0 in this channel.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN5_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 5. 0:  Disable, just output 0 in this channel.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN6_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 6. 0:  Disable, just output 0 in this channel.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN7_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 7. 0:  Disable, just output 0 in this channel.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN8_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 8. 0:  Disable, just output 0 in this channel.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN9_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 9. 0:  Disable, just output 0 in this channel.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN10_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 10. 0:  Disable, just output 0 in this channel.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN11_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 11. 0:  Disable, just output 0 in this channel.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN12_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 12. 0:  Disable, just output 0 in this channel.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN13_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 13. 0:  Disable, just output 0 in this channel.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN14_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 14. 0:  Disable, just output 0 in this channel.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "TX_TDM_CHAN15_EN": {
-                    "description": "1: Enable the valid data output of I2S TX TDM channel 15. 0:  Disable, just output 0 in this channel.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "TX_TDM_TOT_CHAN_NUM": {
-                    "description": "The total channel number of I2S TX TDM mode.",
-                    "offset": 16,
-                    "size": 4
-                  },
-                  "TX_TDM_SKIP_MSK_EN": {
-                    "description": "When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1)  channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.",
-                    "offset": 20,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RX_TIMING": {
-              "description": "I2S RX timing control register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_SD_IN_DM": {
-                    "description": "The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "RX_WS_OUT_DM": {
-                    "description": "The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "RX_BCK_OUT_DM": {
-                    "description": "The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 20,
-                    "size": 2
-                  },
-                  "RX_WS_IN_DM": {
-                    "description": "The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "RX_BCK_IN_DM": {
-                    "description": "The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 28,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "TX_TIMING": {
-              "description": "I2S TX timing control register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_SD_OUT_DM": {
-                    "description": "The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "TX_SD1_OUT_DM": {
-                    "description": "The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "TX_WS_OUT_DM": {
-                    "description": "The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "TX_BCK_OUT_DM": {
-                    "description": "The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 20,
-                    "size": 2
-                  },
-                  "TX_WS_IN_DM": {
-                    "description": "The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "TX_BCK_IN_DM": {
-                    "description": "The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge.  2: delay by neg edge. 3: not used.",
-                    "offset": 28,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "LC_HUNG_CONF": {
-              "description": "I2S HUNG configure register.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 2064,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LC_FIFO_TIMEOUT": {
-                    "description": "the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "LC_FIFO_TIMEOUT_SHIFT": {
-                    "description": "The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift",
-                    "offset": 8,
-                    "size": 3
-                  },
-                  "LC_FIFO_TIMEOUT_ENA": {
-                    "description": "The enable bit for FIFO timeout",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RXEOF_NUM": {
-              "description": "I2S RX data number control register.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 64,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_EOF_NUM": {
-                    "description": "The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "CONF_SIGLE_DATA": {
-              "description": "I2S signal data register",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SINGLE_DATA": {
-                    "description": "The configured constant channel data to be sent out.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STATE": {
-              "description": "I2S TX status register",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_IDLE": {
-                    "description": "1: i2s_tx is idle state. 0: i2s_tx is working.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "Version control register",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 33583648,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "I2S version control register",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "INTERRUPT_CORE0": {
-        "description": "Interrupt Core",
-        "children": {
-          "registers": {
-            "MAC_INTR_MAP": {
-              "description": "mac intr map register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MAC_INTR_MAP": {
-                    "description": "core0_mac_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "MAC_NMI_MAP": {
-              "description": "mac nmi_intr map register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MAC_NMI_MAP": {
-                    "description": "reg_core0_mac_nmi_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "PWR_INTR_MAP": {
-              "description": "pwr intr map register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PWR_INTR_MAP": {
-                    "description": "reg_core0_pwr_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "BB_INT_MAP": {
-              "description": "bb intr map register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BB_INT_MAP": {
-                    "description": "reg_core0_bb_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "BT_MAC_INT_MAP": {
-              "description": "bt intr map register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_MAC_INT_MAP": {
-                    "description": "reg_core0_bt_mac_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "BT_BB_INT_MAP": {
-              "description": "bb_bt intr map register",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_BB_INT_MAP": {
-                    "description": "reg_core0_bt_bb_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "BT_BB_NMI_MAP": {
-              "description": "bb_bt_nmi intr map register",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_BB_NMI_MAP": {
-                    "description": "reg_core0_bt_bb_nmi_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RWBT_IRQ_MAP": {
-              "description": "rwbt intr map register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RWBT_IRQ_MAP": {
-                    "description": "reg_core0_rwbt_irq_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RWBLE_IRQ_MAP": {
-              "description": "rwble intr map register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RWBLE_IRQ_MAP": {
-                    "description": "reg_core0_rwble_irq_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RWBT_NMI_MAP": {
-              "description": "rwbt_nmi intr map register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RWBT_NMI_MAP": {
-                    "description": "reg_core0_rwbt_nmi_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RWBLE_NMI_MAP": {
-              "description": "rwble_nmi intr map register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RWBLE_NMI_MAP": {
-                    "description": "reg_core0_rwble_nmi_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "I2C_MST_INT_MAP": {
-              "description": "i2c intr map register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "I2C_MST_INT_MAP": {
-                    "description": "reg_core0_i2c_mst_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SLC0_INTR_MAP": {
-              "description": "slc0 intr map register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLC0_INTR_MAP": {
-                    "description": "reg_core0_slc0_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SLC1_INTR_MAP": {
-              "description": "slc1 intr map register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLC1_INTR_MAP": {
-                    "description": "reg_core0_slc1_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "APB_CTRL_INTR_MAP": {
-              "description": "apb_ctrl intr map register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_CTRL_INTR_MAP": {
-                    "description": "reg_core0_apb_ctrl_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "UHCI0_INTR_MAP": {
-              "description": "uchi0 intr map register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "UHCI0_INTR_MAP": {
-                    "description": "reg_core0_uhci0_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "GPIO_INTERRUPT_PRO_MAP": {
-              "description": "gpio intr map register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "GPIO_INTERRUPT_PRO_MAP": {
-                    "description": "reg_core0_gpio_interrupt_pro_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "GPIO_INTERRUPT_PRO_NMI_MAP": {
-              "description": "gpio_pro intr map register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "GPIO_INTERRUPT_PRO_NMI_MAP": {
-                    "description": "reg_core0_gpio_interrupt_pro_nmi_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SPI_INTR_1_MAP": {
-              "description": "gpio_pro_nmi intr map register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_INTR_1_MAP": {
-                    "description": "reg_core0_spi_intr_1_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SPI_INTR_2_MAP": {
-              "description": "spi1 intr map register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_INTR_2_MAP": {
-                    "description": "reg_core0_spi_intr_2_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "I2S1_INT_MAP": {
-              "description": "spi2 intr map register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "I2S1_INT_MAP": {
-                    "description": "reg_core0_i2s1_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "UART_INTR_MAP": {
-              "description": "i2s1 intr map register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "UART_INTR_MAP": {
-                    "description": "reg_core0_uart_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "UART1_INTR_MAP": {
-              "description": "uart1 intr map register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "UART1_INTR_MAP": {
-                    "description": "reg_core0_uart1_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "LEDC_INT_MAP": {
-              "description": "ledc intr map register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LEDC_INT_MAP": {
-                    "description": "reg_core0_ledc_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "EFUSE_INT_MAP": {
-              "description": "efuse intr map register",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "EFUSE_INT_MAP": {
-                    "description": "reg_core0_efuse_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CAN_INT_MAP": {
-              "description": "can intr map register",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CAN_INT_MAP": {
-                    "description": "reg_core0_can_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "USB_INTR_MAP": {
-              "description": "usb intr map register",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USB_INTR_MAP": {
-                    "description": "reg_core0_usb_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RTC_CORE_INTR_MAP": {
-              "description": "rtc intr map register",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CORE_INTR_MAP": {
-                    "description": "reg_core0_rtc_core_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RMT_INTR_MAP": {
-              "description": "rmt intr map register",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RMT_INTR_MAP": {
-                    "description": "reg_core0_rmt_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "I2C_EXT0_INTR_MAP": {
-              "description": "i2c intr map register",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "I2C_EXT0_INTR_MAP": {
-                    "description": "reg_core0_i2c_ext0_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TIMER_INT1_MAP": {
-              "description": "timer1 intr map register",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_INT1_MAP": {
-                    "description": "reg_core0_timer_int1_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TIMER_INT2_MAP": {
-              "description": "timer2 intr map register",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_INT2_MAP": {
-                    "description": "reg_core0_timer_int2_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TG_T0_INT_MAP": {
-              "description": "tg to intr map register",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TG_T0_INT_MAP": {
-                    "description": "reg_core0_tg_t0_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TG_WDT_INT_MAP": {
-              "description": "tg wdt intr map register",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TG_WDT_INT_MAP": {
-                    "description": "reg_core0_tg_wdt_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TG1_T0_INT_MAP": {
-              "description": "tg1 to intr map register",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TG1_T0_INT_MAP": {
-                    "description": "reg_core0_tg1_t0_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TG1_WDT_INT_MAP": {
-              "description": "tg1 wdt intr map register",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TG1_WDT_INT_MAP": {
-                    "description": "reg_core0_tg1_wdt_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CACHE_IA_INT_MAP": {
-              "description": "cache ia intr map register",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_IA_INT_MAP": {
-                    "description": "reg_core0_cache_ia_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SYSTIMER_TARGET0_INT_MAP": {
-              "description": "systimer intr map register",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYSTIMER_TARGET0_INT_MAP": {
-                    "description": "reg_core0_systimer_target0_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SYSTIMER_TARGET1_INT_MAP": {
-              "description": "systimer target1 intr map register",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYSTIMER_TARGET1_INT_MAP": {
-                    "description": "reg_core0_systimer_target1_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SYSTIMER_TARGET2_INT_MAP": {
-              "description": "systimer target2 intr map register",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYSTIMER_TARGET2_INT_MAP": {
-                    "description": "reg_core0_systimer_target2_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SPI_MEM_REJECT_INTR_MAP": {
-              "description": "spi mem reject intr map register",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI_MEM_REJECT_INTR_MAP": {
-                    "description": "reg_core0_spi_mem_reject_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "ICACHE_PRELOAD_INT_MAP": {
-              "description": "icache perload intr map register",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_PRELOAD_INT_MAP": {
-                    "description": "reg_core0_icache_preload_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "ICACHE_SYNC_INT_MAP": {
-              "description": "icache sync intr map register",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_SYNC_INT_MAP": {
-                    "description": "reg_core0_icache_sync_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "APB_ADC_INT_MAP": {
-              "description": "adc intr map register",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_ADC_INT_MAP": {
-                    "description": "reg_core0_apb_adc_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "DMA_CH0_INT_MAP": {
-              "description": "dma ch0 intr map register",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_CH0_INT_MAP": {
-                    "description": "reg_core0_dma_ch0_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "DMA_CH1_INT_MAP": {
-              "description": "dma ch1 intr map register",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_CH1_INT_MAP": {
-                    "description": "reg_core0_dma_ch1_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "DMA_CH2_INT_MAP": {
-              "description": "dma ch2 intr map register",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_CH2_INT_MAP": {
-                    "description": "reg_core0_dma_ch2_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "RSA_INT_MAP": {
-              "description": "rsa intr map register",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RSA_INT_MAP": {
-                    "description": "reg_core0_rsa_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "AES_INT_MAP": {
-              "description": "aes intr map register",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AES_INT_MAP": {
-                    "description": "reg_core0_aes_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "SHA_INT_MAP": {
-              "description": "sha intr map register",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SHA_INT_MAP": {
-                    "description": "reg_core0_sha_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_0_MAP": {
-              "description": "cpu from cpu 0 intr map register",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_0_MAP": {
-                    "description": "reg_core0_cpu_intr_from_cpu_0_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_1_MAP": {
-              "description": "cpu from cpu 0 intr map register",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_1_MAP": {
-                    "description": "reg_core0_cpu_intr_from_cpu_1_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_2_MAP": {
-              "description": "cpu from cpu 1 intr map register",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_2_MAP": {
-                    "description": "reg_core0_cpu_intr_from_cpu_2_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_3_MAP": {
-              "description": "cpu from cpu 3 intr map register",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_3_MAP": {
-                    "description": "reg_core0_cpu_intr_from_cpu_3_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "ASSIST_DEBUG_INTR_MAP": {
-              "description": "assist debug intr map register",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ASSIST_DEBUG_INTR_MAP": {
-                    "description": "reg_core0_assist_debug_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP": {
-              "description": "dma pms violatile intr map register",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP": {
-                    "description": "reg_core0_dma_apbperi_pms_monitor_violate_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
-              "description": "iram0 pms violatile intr map register",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
-                    "description": "reg_core0_core_0_iram0_pms_monitor_violate_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
-              "description": "mac intr map register",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP": {
-                    "description": "reg_core0_core_0_dram0_pms_monitor_violate_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP": {
-              "description": "mac intr map register",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP": {
-                    "description": "reg_core0_core_0_pif_pms_monitor_violate_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP": {
-              "description": "mac intr map register",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP": {
-                    "description": "reg_core0_core_0_pif_pms_monitor_violate_size_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "BACKUP_PMS_VIOLATE_INTR_MAP": {
-              "description": "mac intr map register",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_PMS_VIOLATE_INTR_MAP": {
-                    "description": "reg_core0_backup_pms_violate_intr_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "CACHE_CORE0_ACS_INT_MAP": {
-              "description": "mac intr map register",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_CORE0_ACS_INT_MAP": {
-                    "description": "reg_core0_cache_core0_acs_int_map",
-                    "offset": 0,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "INTR_STATUS_REG_0": {
-              "description": "mac intr map register",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTR_STATUS_0": {
-                    "description": "reg_core0_intr_status_0",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INTR_STATUS_REG_1": {
-              "description": "mac intr map register",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTR_STATUS_1": {
-                    "description": "reg_core0_intr_status_1",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "mac intr map register",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REG_CLK_EN": {
-                    "description": "reg_core0_reg_clk_en",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_INT_ENABLE": {
-              "description": "mac intr map register",
-              "offset": 260,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INT_ENABLE": {
-                    "description": "reg_core0_cpu_int_enable",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CPU_INT_TYPE": {
-              "description": "mac intr map register",
-              "offset": 264,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INT_TYPE": {
-                    "description": "reg_core0_cpu_int_type",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CPU_INT_CLEAR": {
-              "description": "mac intr map register",
-              "offset": 268,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INT_CLEAR": {
-                    "description": "reg_core0_cpu_int_clear",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CPU_INT_EIP_STATUS": {
-              "description": "mac intr map register",
-              "offset": 272,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INT_EIP_STATUS": {
-                    "description": "reg_core0_cpu_int_eip_status",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_0": {
-              "description": "mac intr map register",
-              "offset": 276,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_0_MAP": {
-                    "description": "reg_core0_cpu_pri_0_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_1": {
-              "description": "mac intr map register",
-              "offset": 280,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_1_MAP": {
-                    "description": "reg_core0_cpu_pri_1_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_2": {
-              "description": "mac intr map register",
-              "offset": 284,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_2_MAP": {
-                    "description": "reg_core0_cpu_pri_2_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_3": {
-              "description": "mac intr map register",
-              "offset": 288,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_3_MAP": {
-                    "description": "reg_core0_cpu_pri_3_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_4": {
-              "description": "mac intr map register",
-              "offset": 292,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_4_MAP": {
-                    "description": "reg_core0_cpu_pri_4_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_5": {
-              "description": "mac intr map register",
-              "offset": 296,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_5_MAP": {
-                    "description": "reg_core0_cpu_pri_5_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_6": {
-              "description": "mac intr map register",
-              "offset": 300,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_6_MAP": {
-                    "description": "reg_core0_cpu_pri_6_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_7": {
-              "description": "mac intr map register",
-              "offset": 304,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_7_MAP": {
-                    "description": "reg_core0_cpu_pri_7_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_8": {
-              "description": "mac intr map register",
-              "offset": 308,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_8_MAP": {
-                    "description": "reg_core0_cpu_pri_8_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_9": {
-              "description": "mac intr map register",
-              "offset": 312,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_9_MAP": {
-                    "description": "reg_core0_cpu_pri_9_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_10": {
-              "description": "mac intr map register",
-              "offset": 316,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_10_MAP": {
-                    "description": "reg_core0_cpu_pri_10_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_11": {
-              "description": "mac intr map register",
-              "offset": 320,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_11_MAP": {
-                    "description": "reg_core0_cpu_pri_11_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_12": {
-              "description": "mac intr map register",
-              "offset": 324,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_12_MAP": {
-                    "description": "reg_core0_cpu_pri_12_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_13": {
-              "description": "mac intr map register",
-              "offset": 328,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_13_MAP": {
-                    "description": "reg_core0_cpu_pri_13_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_14": {
-              "description": "mac intr map register",
-              "offset": 332,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_14_MAP": {
-                    "description": "reg_core0_cpu_pri_14_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_15": {
-              "description": "mac intr map register",
-              "offset": 336,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_15_MAP": {
-                    "description": "reg_core0_cpu_pri_15_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_16": {
-              "description": "mac intr map register",
-              "offset": 340,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_16_MAP": {
-                    "description": "reg_core0_cpu_pri_16_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_17": {
-              "description": "mac intr map register",
-              "offset": 344,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_17_MAP": {
-                    "description": "reg_core0_cpu_pri_17_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_18": {
-              "description": "mac intr map register",
-              "offset": 348,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_18_MAP": {
-                    "description": "reg_core0_cpu_pri_18_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_19": {
-              "description": "mac intr map register",
-              "offset": 352,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_19_MAP": {
-                    "description": "reg_core0_cpu_pri_19_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_20": {
-              "description": "mac intr map register",
-              "offset": 356,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_20_MAP": {
-                    "description": "reg_core0_cpu_pri_20_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_21": {
-              "description": "mac intr map register",
-              "offset": 360,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_21_MAP": {
-                    "description": "reg_core0_cpu_pri_21_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_22": {
-              "description": "mac intr map register",
-              "offset": 364,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_22_MAP": {
-                    "description": "reg_core0_cpu_pri_22_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_23": {
-              "description": "mac intr map register",
-              "offset": 368,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_23_MAP": {
-                    "description": "reg_core0_cpu_pri_23_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_24": {
-              "description": "mac intr map register",
-              "offset": 372,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_24_MAP": {
-                    "description": "reg_core0_cpu_pri_24_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_25": {
-              "description": "mac intr map register",
-              "offset": 376,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_25_MAP": {
-                    "description": "reg_core0_cpu_pri_25_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_26": {
-              "description": "mac intr map register",
-              "offset": 380,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_26_MAP": {
-                    "description": "reg_core0_cpu_pri_26_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_27": {
-              "description": "mac intr map register",
-              "offset": 384,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_27_MAP": {
-                    "description": "reg_core0_cpu_pri_27_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_28": {
-              "description": "mac intr map register",
-              "offset": 388,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_28_MAP": {
-                    "description": "reg_core0_cpu_pri_28_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_29": {
-              "description": "mac intr map register",
-              "offset": 392,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_29_MAP": {
-                    "description": "reg_core0_cpu_pri_29_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_30": {
-              "description": "mac intr map register",
-              "offset": 396,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_30_MAP": {
-                    "description": "reg_core0_cpu_pri_30_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_PRI_31": {
-              "description": "mac intr map register",
-              "offset": 400,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_PRI_31_MAP": {
-                    "description": "reg_core0_cpu_pri_31_map",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "CPU_INT_THRESH": {
-              "description": "mac intr map register",
-              "offset": 404,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INT_THRESH": {
-                    "description": "reg_core0_cpu_int_thresh",
-                    "offset": 0,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "INTERRUPT_REG_DATE": {
-              "description": "mac intr map register",
-              "offset": 2044,
-              "size": 32,
-              "reset_value": 33583632,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERRUPT_REG_DATE": {
-                    "description": "reg_core0_interrupt_reg_date",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "IO_MUX": {
-        "description": "Input/Output Multiplexer",
-        "children": {
-          "registers": {
-            "PIN_CTRL": {
-              "description": "Clock Output Configuration Register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 2047,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_OUT1": {
-                    "description": "If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "CLK_OUT2": {
-                    "description": "If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.",
-                    "offset": 4,
-                    "size": 4
-                  },
-                  "CLK_OUT3": {
-                    "description": "If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.",
-                    "offset": 8,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "GPIO": {
-              "description": "IO MUX Configure Register for pad XTAL_32K_P",
-              "offset": 4,
-              "size": 32,
-              "count": 22,
-              "reset_value": 2816,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MCU_OE": {
-                    "description": "Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SLP_SEL": {
-                    "description": "Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "MCU_WPD": {
-                    "description": "Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "MCU_WPU": {
-                    "description": "Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MCU_IE": {
-                    "description": "Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "FUN_WPD": {
-                    "description": "Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FUN_WPU": {
-                    "description": "Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "FUN_IE": {
-                    "description": "Input enable of the pad. 1: input enabled; 0: input disabled.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "FUN_DRV": {
-                    "description": "Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "MCU_SEL": {
-                    "description": "Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.",
-                    "offset": 12,
-                    "size": 3
-                  },
-                  "FILTER_EN": {
-                    "description": "Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.",
-                    "offset": 15,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "IO MUX Version Control Register",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 33579088,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REG_DATE": {
-                    "description": "Version control register",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "LEDC": {
-        "description": "LED Control PWM (Pulse Width Modulation)",
-        "children": {
-          "registers": {
-            "LSCH0_CONF0": {
-              "description": "LEDC_LSCH0_CONF0.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH0": {
-                    "description": "reg_timer_sel_lsch0.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH0": {
-                    "description": "reg_sig_out_en_lsch0.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH0": {
-                    "description": "reg_idle_lv_lsch0.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH0": {
-                    "description": "reg_para_up_lsch0.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH0": {
-                    "description": "reg_ovf_num_lsch0.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH0": {
-                    "description": "reg_ovf_cnt_en_lsch0.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH0": {
-                    "description": "reg_ovf_cnt_reset_lsch0.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH0_HPOINT": {
-              "description": "LEDC_LSCH0_HPOINT.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH0": {
-                    "description": "reg_hpoint_lsch0.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH0_DUTY": {
-              "description": "LEDC_LSCH0_DUTY.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH0": {
-                    "description": "reg_duty_lsch0.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH0_CONF1": {
-              "description": "LEDC_LSCH0_CONF1.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH0": {
-                    "description": "reg_duty_scale_lsch0.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH0": {
-                    "description": "reg_duty_cycle_lsch0.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH0": {
-                    "description": "reg_duty_num_lsch0.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH0": {
-                    "description": "reg_duty_inc_lsch0.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH0": {
-                    "description": "reg_duty_start_lsch0.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH0_DUTY_R": {
-              "description": "LEDC_LSCH0_DUTY_R.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH0_R": {
-                    "description": "reg_duty_lsch0_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSCH1_CONF0": {
-              "description": "LEDC_LSCH1_CONF0.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH1": {
-                    "description": "reg_timer_sel_lsch1.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH1": {
-                    "description": "reg_sig_out_en_lsch1.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH1": {
-                    "description": "reg_idle_lv_lsch1.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH1": {
-                    "description": "reg_para_up_lsch1.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH1": {
-                    "description": "reg_ovf_num_lsch1.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH1": {
-                    "description": "reg_ovf_cnt_en_lsch1.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH1": {
-                    "description": "reg_ovf_cnt_reset_lsch1.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH1_HPOINT": {
-              "description": "LEDC_LSCH1_HPOINT.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH1": {
-                    "description": "reg_hpoint_lsch1.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH1_DUTY": {
-              "description": "LEDC_LSCH1_DUTY.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH1": {
-                    "description": "reg_duty_lsch1.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH1_CONF1": {
-              "description": "LEDC_LSCH1_CONF1.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH1": {
-                    "description": "reg_duty_scale_lsch1.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH1": {
-                    "description": "reg_duty_cycle_lsch1.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH1": {
-                    "description": "reg_duty_num_lsch1.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH1": {
-                    "description": "reg_duty_inc_lsch1.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH1": {
-                    "description": "reg_duty_start_lsch1.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH1_DUTY_R": {
-              "description": "LEDC_LSCH1_DUTY_R.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH1_R": {
-                    "description": "reg_duty_lsch1_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSCH2_CONF0": {
-              "description": "LEDC_LSCH2_CONF0.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH2": {
-                    "description": "reg_timer_sel_lsch2.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH2": {
-                    "description": "reg_sig_out_en_lsch2.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH2": {
-                    "description": "reg_idle_lv_lsch2.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH2": {
-                    "description": "reg_para_up_lsch2.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH2": {
-                    "description": "reg_ovf_num_lsch2.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH2": {
-                    "description": "reg_ovf_cnt_en_lsch2.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH2": {
-                    "description": "reg_ovf_cnt_reset_lsch2.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH2_HPOINT": {
-              "description": "LEDC_LSCH2_HPOINT.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH2": {
-                    "description": "reg_hpoint_lsch2.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH2_DUTY": {
-              "description": "LEDC_LSCH2_DUTY.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH2": {
-                    "description": "reg_duty_lsch2.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH2_CONF1": {
-              "description": "LEDC_LSCH2_CONF1.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH2": {
-                    "description": "reg_duty_scale_lsch2.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH2": {
-                    "description": "reg_duty_cycle_lsch2.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH2": {
-                    "description": "reg_duty_num_lsch2.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH2": {
-                    "description": "reg_duty_inc_lsch2.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH2": {
-                    "description": "reg_duty_start_lsch2.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH2_DUTY_R": {
-              "description": "LEDC_LSCH2_DUTY_R.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH2_R": {
-                    "description": "reg_duty_lsch2_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSCH3_CONF0": {
-              "description": "LEDC_LSCH3_CONF0.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH3": {
-                    "description": "reg_timer_sel_lsch3.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH3": {
-                    "description": "reg_sig_out_en_lsch3.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH3": {
-                    "description": "reg_idle_lv_lsch3.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH3": {
-                    "description": "reg_para_up_lsch3.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH3": {
-                    "description": "reg_ovf_num_lsch3.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH3": {
-                    "description": "reg_ovf_cnt_en_lsch3.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH3": {
-                    "description": "reg_ovf_cnt_reset_lsch3.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH3_HPOINT": {
-              "description": "LEDC_LSCH3_HPOINT.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH3": {
-                    "description": "reg_hpoint_lsch3.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH3_DUTY": {
-              "description": "LEDC_LSCH3_DUTY.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH3": {
-                    "description": "reg_duty_lsch3.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH3_CONF1": {
-              "description": "LEDC_LSCH3_CONF1.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH3": {
-                    "description": "reg_duty_scale_lsch3.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH3": {
-                    "description": "reg_duty_cycle_lsch3.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH3": {
-                    "description": "reg_duty_num_lsch3.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH3": {
-                    "description": "reg_duty_inc_lsch3.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH3": {
-                    "description": "reg_duty_start_lsch3.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH3_DUTY_R": {
-              "description": "LEDC_LSCH3_DUTY_R.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH3_R": {
-                    "description": "reg_duty_lsch3_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSCH4_CONF0": {
-              "description": "LEDC_LSCH4_CONF0.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH4": {
-                    "description": "reg_timer_sel_lsch4.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH4": {
-                    "description": "reg_sig_out_en_lsch4.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH4": {
-                    "description": "reg_idle_lv_lsch4.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH4": {
-                    "description": "reg_para_up_lsch4.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH4": {
-                    "description": "reg_ovf_num_lsch4.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH4": {
-                    "description": "reg_ovf_cnt_en_lsch4.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH4": {
-                    "description": "reg_ovf_cnt_reset_lsch4.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH4_HPOINT": {
-              "description": "LEDC_LSCH4_HPOINT.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH4": {
-                    "description": "reg_hpoint_lsch4.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH4_DUTY": {
-              "description": "LEDC_LSCH4_DUTY.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH4": {
-                    "description": "reg_duty_lsch4.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH4_CONF1": {
-              "description": "LEDC_LSCH4_CONF1.",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH4": {
-                    "description": "reg_duty_scale_lsch4.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH4": {
-                    "description": "reg_duty_cycle_lsch4.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH4": {
-                    "description": "reg_duty_num_lsch4.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH4": {
-                    "description": "reg_duty_inc_lsch4.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH4": {
-                    "description": "reg_duty_start_lsch4.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH4_DUTY_R": {
-              "description": "LEDC_LSCH4_DUTY_R.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH4_R": {
-                    "description": "reg_duty_lsch4_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSCH5_CONF0": {
-              "description": "LEDC_LSCH5_CONF0.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SEL_LSCH5": {
-                    "description": "reg_timer_sel_lsch5.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SIG_OUT_EN_LSCH5": {
-                    "description": "reg_sig_out_en_lsch5.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "IDLE_LV_LSCH5": {
-                    "description": "reg_idle_lv_lsch5.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PARA_UP_LSCH5": {
-                    "description": "reg_para_up_lsch5.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_NUM_LSCH5": {
-                    "description": "reg_ovf_num_lsch5.",
-                    "offset": 5,
-                    "size": 10
-                  },
-                  "OVF_CNT_EN_LSCH5": {
-                    "description": "reg_ovf_cnt_en_lsch5.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "OVF_CNT_RESET_LSCH5": {
-                    "description": "reg_ovf_cnt_reset_lsch5.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSCH5_HPOINT": {
-              "description": "LEDC_LSCH5_HPOINT.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "HPOINT_LSCH5": {
-                    "description": "reg_hpoint_lsch5.",
-                    "offset": 0,
-                    "size": 14
-                  }
-                }
-              }
-            },
-            "LSCH5_DUTY": {
-              "description": "LEDC_LSCH5_DUTY.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH5": {
-                    "description": "reg_duty_lsch5.",
-                    "offset": 0,
-                    "size": 19
-                  }
-                }
-              }
-            },
-            "LSCH5_CONF1": {
-              "description": "LEDC_LSCH5_CONF1.",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 1073741824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_SCALE_LSCH5": {
-                    "description": "reg_duty_scale_lsch5.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "DUTY_CYCLE_LSCH5": {
-                    "description": "reg_duty_cycle_lsch5.",
-                    "offset": 10,
-                    "size": 10
-                  },
-                  "DUTY_NUM_LSCH5": {
-                    "description": "reg_duty_num_lsch5.",
-                    "offset": 20,
-                    "size": 10
-                  },
-                  "DUTY_INC_LSCH5": {
-                    "description": "reg_duty_inc_lsch5.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DUTY_START_LSCH5": {
-                    "description": "reg_duty_start_lsch5.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LSCH5_DUTY_R": {
-              "description": "LEDC_LSCH5_DUTY_R.",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUTY_LSCH5_R": {
-                    "description": "reg_duty_lsch5_r.",
-                    "offset": 0,
-                    "size": 19,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER0_CONF": {
-              "description": "LEDC_LSTIMER0_CONF.",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_DUTY_RES": {
-                    "description": "reg_lstimer0_duty_res.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "CLK_DIV_LSTIMER0": {
-                    "description": "reg_clk_div_lstimer0.",
-                    "offset": 4,
-                    "size": 18
-                  },
-                  "LSTIMER0_PAUSE": {
-                    "description": "reg_lstimer0_pause.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "LSTIMER0_RST": {
-                    "description": "reg_lstimer0_rst.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TICK_SEL_LSTIMER0": {
-                    "description": "reg_tick_sel_lstimer0.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "LSTIMER0_PARA_UP": {
-                    "description": "reg_lstimer0_para_up.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER0_VALUE": {
-              "description": "LEDC_LSTIMER0_VALUE.",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_CNT": {
-                    "description": "reg_lstimer0_cnt.",
-                    "offset": 0,
-                    "size": 14,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER1_CONF": {
-              "description": "LEDC_LSTIMER1_CONF.",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER1_DUTY_RES": {
-                    "description": "reg_lstimer1_duty_res.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "CLK_DIV_LSTIMER1": {
-                    "description": "reg_clk_div_lstimer1.",
-                    "offset": 4,
-                    "size": 18
-                  },
-                  "LSTIMER1_PAUSE": {
-                    "description": "reg_lstimer1_pause.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "LSTIMER1_RST": {
-                    "description": "reg_lstimer1_rst.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TICK_SEL_LSTIMER1": {
-                    "description": "reg_tick_sel_lstimer1.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "LSTIMER1_PARA_UP": {
-                    "description": "reg_lstimer1_para_up.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER1_VALUE": {
-              "description": "LEDC_LSTIMER1_VALUE.",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER1_CNT": {
-                    "description": "reg_lstimer1_cnt.",
-                    "offset": 0,
-                    "size": 14,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER2_CONF": {
-              "description": "LEDC_LSTIMER2_CONF.",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER2_DUTY_RES": {
-                    "description": "reg_lstimer2_duty_res.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "CLK_DIV_LSTIMER2": {
-                    "description": "reg_clk_div_lstimer2.",
-                    "offset": 4,
-                    "size": 18
-                  },
-                  "LSTIMER2_PAUSE": {
-                    "description": "reg_lstimer2_pause.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "LSTIMER2_RST": {
-                    "description": "reg_lstimer2_rst.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TICK_SEL_LSTIMER2": {
-                    "description": "reg_tick_sel_lstimer2.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "LSTIMER2_PARA_UP": {
-                    "description": "reg_lstimer2_para_up.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER2_VALUE": {
-              "description": "LEDC_LSTIMER2_VALUE.",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER2_CNT": {
-                    "description": "reg_lstimer2_cnt.",
-                    "offset": 0,
-                    "size": 14,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER3_CONF": {
-              "description": "LEDC_LSTIMER3_CONF.",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 8388608,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER3_DUTY_RES": {
-                    "description": "reg_lstimer3_duty_res.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "CLK_DIV_LSTIMER3": {
-                    "description": "reg_clk_div_lstimer3.",
-                    "offset": 4,
-                    "size": 18
-                  },
-                  "LSTIMER3_PAUSE": {
-                    "description": "reg_lstimer3_pause.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "LSTIMER3_RST": {
-                    "description": "reg_lstimer3_rst.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TICK_SEL_LSTIMER3": {
-                    "description": "reg_tick_sel_lstimer3.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "LSTIMER3_PARA_UP": {
-                    "description": "reg_lstimer3_para_up.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "LSTIMER3_VALUE": {
-              "description": "LEDC_LSTIMER3_VALUE.",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER3_CNT": {
-                    "description": "reg_lstimer3_cnt.",
-                    "offset": 0,
-                    "size": 14,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "LEDC_INT_RAW.",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_OVF_INT_RAW": {
-                    "description": "reg_lstimer0_ovf_int_raw.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER1_OVF_INT_RAW": {
-                    "description": "reg_lstimer1_ovf_int_raw.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER2_OVF_INT_RAW": {
-                    "description": "reg_lstimer2_ovf_int_raw.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER3_OVF_INT_RAW": {
-                    "description": "reg_lstimer3_ovf_int_raw.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH0_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch0_int_raw.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH1_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch1_int_raw.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH2_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch2_int_raw.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH3_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch3_int_raw.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH4_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch4_int_raw.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH5_INT_RAW": {
-                    "description": "reg_duty_chng_end_lsch5_int_raw.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH0_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch0_int_raw.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH1_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch1_int_raw.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH2_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch2_int_raw.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH3_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch3_int_raw.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH4_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch4_int_raw.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH5_INT_RAW": {
-                    "description": "reg_ovf_cnt_lsch5_int_raw.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "LEDC_INT_ST.",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_OVF_INT_ST": {
-                    "description": "reg_lstimer0_ovf_int_st.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER1_OVF_INT_ST": {
-                    "description": "reg_lstimer1_ovf_int_st.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER2_OVF_INT_ST": {
-                    "description": "reg_lstimer2_ovf_int_st.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "LSTIMER3_OVF_INT_ST": {
-                    "description": "reg_lstimer3_ovf_int_st.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH0_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch0_int_st.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH1_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch1_int_st.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH2_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch2_int_st.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH3_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch3_int_st.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH4_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch4_int_st.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DUTY_CHNG_END_LSCH5_INT_ST": {
-                    "description": "reg_duty_chng_end_lsch5_int_st.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH0_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch0_int_st.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH1_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch1_int_st.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH2_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch2_int_st.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH3_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch3_int_st.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH4_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch4_int_st.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVF_CNT_LSCH5_INT_ST": {
-                    "description": "reg_ovf_cnt_lsch5_int_st.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "LEDC_INT_ENA.",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_OVF_INT_ENA": {
-                    "description": "reg_lstimer0_ovf_int_ena.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "LSTIMER1_OVF_INT_ENA": {
-                    "description": "reg_lstimer1_ovf_int_ena.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "LSTIMER2_OVF_INT_ENA": {
-                    "description": "reg_lstimer2_ovf_int_ena.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "LSTIMER3_OVF_INT_ENA": {
-                    "description": "reg_lstimer3_ovf_int_ena.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH0_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch0_int_ena.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH1_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch1_int_ena.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH2_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch2_int_ena.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH3_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch3_int_ena.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH4_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch4_int_ena.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DUTY_CHNG_END_LSCH5_INT_ENA": {
-                    "description": "reg_duty_chng_end_lsch5_int_ena.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH0_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch0_int_ena.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH1_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch1_int_ena.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH2_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch2_int_ena.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH3_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch3_int_ena.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH4_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch4_int_ena.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "OVF_CNT_LSCH5_INT_ENA": {
-                    "description": "reg_ovf_cnt_lsch5_int_ena.",
-                    "offset": 15,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "LEDC_INT_CLR.",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSTIMER0_OVF_INT_CLR": {
-                    "description": "reg_lstimer0_ovf_int_clr.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "LSTIMER1_OVF_INT_CLR": {
-                    "description": "reg_lstimer1_ovf_int_clr.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "LSTIMER2_OVF_INT_CLR": {
-                    "description": "reg_lstimer2_ovf_int_clr.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "LSTIMER3_OVF_INT_CLR": {
-                    "description": "reg_lstimer3_ovf_int_clr.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH0_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch0_int_clr.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH1_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch1_int_clr.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH2_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch2_int_clr.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH3_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch3_int_clr.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH4_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch4_int_clr.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DUTY_CHNG_END_LSCH5_INT_CLR": {
-                    "description": "reg_duty_chng_end_lsch5_int_clr.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH0_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch0_int_clr.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH1_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch1_int_clr.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH2_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch2_int_clr.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH3_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch3_int_clr.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH4_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch4_int_clr.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OVF_CNT_LSCH5_INT_CLR": {
-                    "description": "reg_ovf_cnt_lsch5_int_clr.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CONF": {
-              "description": "LEDC_CONF.",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_CLK_SEL": {
-                    "description": "reg_apb_clk_sel.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "LEDC_DATE.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 419829504,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LEDC_DATE": {
-                    "description": "reg_ledc_date.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "RMT": {
-        "description": "Remote Control Peripheral",
-        "children": {
-          "registers": {
-            "CH0DATA": {
-              "description": "RMT_CH0DATA_REG.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CH1DATA": {
-              "description": "RMT_CH1DATA_REG.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CH2DATA": {
-              "description": "RMT_CH2DATA_REG.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CH3DATA": {
-              "description": "RMT_CH3DATA_REG.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "Reserved.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CH2CONF1": {
-              "description": "RMT_CH2CONF1_REG.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 488,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_EN": {
-                    "description": "reg_rx_en_ch2.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MEM_WR_RST": {
-                    "description": "reg_mem_wr_rst_ch2.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_MEM_RST": {
-                    "description": "reg_apb_mem_rst_ch2.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MEM_OWNER": {
-                    "description": "reg_mem_owner_ch2.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RX_FILTER_EN": {
-                    "description": "reg_rx_filter_en_ch2.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RX_FILTER_THRES": {
-                    "description": "reg_rx_filter_thres_ch2.",
-                    "offset": 5,
-                    "size": 8
-                  },
-                  "MEM_RX_WRAP_EN": {
-                    "description": "reg_mem_rx_wrap_en_ch2.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "AFIFO_RST": {
-                    "description": "reg_afifo_rst_ch2.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CONF_UPDATE": {
-                    "description": "reg_conf_update_ch2.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CH3CONF1": {
-              "description": "RMT_CH3CONF1_REG.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 488,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_EN": {
-                    "description": "reg_rx_en_ch3.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MEM_WR_RST": {
-                    "description": "reg_mem_wr_rst_ch3.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB_MEM_RST": {
-                    "description": "reg_apb_mem_rst_ch3.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MEM_OWNER": {
-                    "description": "reg_mem_owner_ch3.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RX_FILTER_EN": {
-                    "description": "reg_rx_filter_en_ch3.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RX_FILTER_THRES": {
-                    "description": "reg_rx_filter_thres_ch3.",
-                    "offset": 5,
-                    "size": 8
-                  },
-                  "MEM_RX_WRAP_EN": {
-                    "description": "reg_mem_rx_wrap_en_ch3.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "AFIFO_RST": {
-                    "description": "reg_afifo_rst_ch3.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CONF_UPDATE": {
-                    "description": "reg_conf_update_ch3.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CH0STATUS": {
-              "description": "RMT_CH0STATUS_REG.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MEM_RADDR_EX": {
-                    "description": "reg_mem_raddr_ex_ch0.",
-                    "offset": 0,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "STATE": {
-                    "description": "reg_state_ch0.",
-                    "offset": 9,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_WADDR": {
-                    "description": "reg_apb_mem_waddr_ch0.",
-                    "offset": 12,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RD_ERR": {
-                    "description": "reg_apb_mem_rd_err_ch0.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MEM_EMPTY": {
-                    "description": "reg_mem_empty_ch0.",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_WR_ERR": {
-                    "description": "reg_apb_mem_wr_err_ch0.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RADDR": {
-                    "description": "reg_apb_mem_raddr_ch0.",
-                    "offset": 24,
-                    "size": 8,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CH1STATUS": {
-              "description": "RMT_CH1STATUS_REG.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MEM_RADDR_EX": {
-                    "description": "reg_mem_raddr_ex_ch1.",
-                    "offset": 0,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "STATE": {
-                    "description": "reg_state_ch1.",
-                    "offset": 9,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_WADDR": {
-                    "description": "reg_apb_mem_waddr_ch1.",
-                    "offset": 12,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RD_ERR": {
-                    "description": "reg_apb_mem_rd_err_ch1.",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MEM_EMPTY": {
-                    "description": "reg_mem_empty_ch1.",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_WR_ERR": {
-                    "description": "reg_apb_mem_wr_err_ch1.",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RADDR": {
-                    "description": "reg_apb_mem_raddr_ch1.",
-                    "offset": 24,
-                    "size": 8,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CH2STATUS": {
-              "description": "RMT_CH2STATUS_REG.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MEM_WADDR_EX": {
-                    "description": "reg_mem_waddr_ex_ch2.",
-                    "offset": 0,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RADDR": {
-                    "description": "reg_apb_mem_raddr_ch2.",
-                    "offset": 12,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "STATE": {
-                    "description": "reg_state_ch2.",
-                    "offset": 22,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "MEM_OWNER_ERR": {
-                    "description": "reg_mem_owner_err_ch2.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MEM_FULL": {
-                    "description": "reg_mem_full_ch2.",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RD_ERR": {
-                    "description": "reg_apb_mem_rd_err_ch2.",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CH3STATUS": {
-              "description": "RMT_CH3STATUS_REG.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MEM_WADDR_EX": {
-                    "description": "reg_mem_waddr_ex_ch3.",
-                    "offset": 0,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RADDR": {
-                    "description": "reg_apb_mem_raddr_ch3.",
-                    "offset": 12,
-                    "size": 9,
-                    "access": "read-only"
-                  },
-                  "STATE": {
-                    "description": "reg_state_ch3.",
-                    "offset": 22,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "MEM_OWNER_ERR": {
-                    "description": "reg_mem_owner_err_ch3.",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MEM_FULL": {
-                    "description": "reg_mem_full_ch3.",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APB_MEM_RD_ERR": {
-                    "description": "reg_apb_mem_rd_err_ch3.",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "RMT_INT_RAW_REG.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CH2_RX_THR_EVENT_INT_RAW": {
-                    "description": "reg_ch2_rx_thr_event_int_raw.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CH3_RX_THR_EVENT_INT_RAW": {
-                    "description": "reg_ch3_rx_thr_event_int_raw.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "RMT_INT_ST_REG.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CH2_RX_THR_EVENT_INT_ST": {
-                    "description": "reg_ch2_rx_thr_event_int_st.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CH3_RX_THR_EVENT_INT_ST": {
-                    "description": "reg_ch3_rx_thr_event_int_st.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "RMT_INT_ENA_REG.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CH2_RX_THR_EVENT_INT_ENA": {
-                    "description": "reg_ch2_rx_thr_event_int_ena.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CH3_RX_THR_EVENT_INT_ENA": {
-                    "description": "reg_ch3_rx_thr_event_int_ena.",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "RMT_INT_CLR_REG.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CH2_RX_THR_EVENT_INT_CLR": {
-                    "description": "reg_ch2_rx_thr_event_int_clr.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CH3_RX_THR_EVENT_INT_CLR": {
-                    "description": "reg_ch3_rx_thr_event_int_clr.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CH0CARRIER_DUTY": {
-              "description": "RMT_CH0CARRIER_DUTY_REG.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 4194368,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CARRIER_LOW": {
-                    "description": "reg_carrier_low_ch0.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "CARRIER_HIGH": {
-                    "description": "reg_carrier_high_ch0.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "CH1CARRIER_DUTY": {
-              "description": "RMT_CH1CARRIER_DUTY_REG.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 4194368,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CARRIER_LOW": {
-                    "description": "reg_carrier_low_ch1.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "CARRIER_HIGH": {
-                    "description": "reg_carrier_high_ch1.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "CH2_RX_CARRIER_RM": {
-              "description": "RMT_CH2_RX_CARRIER_RM_REG.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CARRIER_LOW_THRES": {
-                    "description": "reg_carrier_low_thres_ch2.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "CARRIER_HIGH_THRES": {
-                    "description": "reg_carrier_high_thres_ch2.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "CH3_RX_CARRIER_RM": {
-              "description": "RMT_CH3_RX_CARRIER_RM_REG.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CARRIER_LOW_THRES": {
-                    "description": "reg_carrier_low_thres_ch3.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "CARRIER_HIGH_THRES": {
-                    "description": "reg_carrier_high_thres_ch3.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "SYS_CONF": {
-              "description": "RMT_SYS_CONF_REG.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 83886096,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_FIFO_MASK": {
-                    "description": "reg_apb_fifo_mask.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MEM_CLK_FORCE_ON": {
-                    "description": "reg_mem_clk_force_on.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "MEM_FORCE_PD": {
-                    "description": "reg_rmt_mem_force_pd.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "MEM_FORCE_PU": {
-                    "description": "reg_rmt_mem_force_pu.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SCLK_DIV_NUM": {
-                    "description": "reg_rmt_sclk_div_num.",
-                    "offset": 4,
-                    "size": 8
-                  },
-                  "SCLK_DIV_A": {
-                    "description": "reg_rmt_sclk_div_a.",
-                    "offset": 12,
-                    "size": 6
-                  },
-                  "SCLK_DIV_B": {
-                    "description": "reg_rmt_sclk_div_b.",
-                    "offset": 18,
-                    "size": 6
-                  },
-                  "SCLK_SEL": {
-                    "description": "reg_rmt_sclk_sel.",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "SCLK_ACTIVE": {
-                    "description": "reg_rmt_sclk_active.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_SIM": {
-              "description": "RMT_TX_SIM_REG.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_SIM_CH0": {
-                    "description": "reg_rmt_tx_sim_ch0.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_SIM_CH1": {
-                    "description": "reg_rmt_tx_sim_ch1.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "TX_SIM_EN": {
-                    "description": "reg_rmt_tx_sim_en.",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "REF_CNT_RST": {
-              "description": "RMT_REF_CNT_RST_REG.",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CH0": {
-                    "description": "reg_ref_cnt_rst_ch0.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CH1": {
-                    "description": "reg_ref_cnt_rst_ch1.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CH2": {
-                    "description": "reg_ref_cnt_rst_ch2.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CH3": {
-                    "description": "reg_ref_cnt_rst_ch3.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "RMT_DATE_REG.",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 33579569,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "reg_rmt_date.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "RNG": {
-        "description": "Hardware random number generator",
-        "children": {
-          "registers": {
-            "DATA": {
-              "description": "Random number data",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            }
-          }
-        }
-      },
-      "RSA": {
-        "description": "RSA (Rivest Shamir Adleman) Accelerator",
-        "children": {
-          "registers": {
-            "M_MEM": {
-              "description": "The memory that stores M",
-              "offset": 0,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "Z_MEM": {
-              "description": "The memory that stores Z",
-              "offset": 512,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "Y_MEM": {
-              "description": "The memory that stores Y",
-              "offset": 1024,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "X_MEM": {
-              "description": "The memory that stores X",
-              "offset": 1536,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "M_PRIME": {
-              "description": "RSA M_prime register",
-              "offset": 2048,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "M_PRIME": {
-                    "description": "Those bits stores m'",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "MODE": {
-              "description": "RSA mode register",
-              "offset": 2052,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MODE": {
-                    "description": "rsa mode (rsa length).",
-                    "offset": 0,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "QUERY_CLEAN": {
-              "description": "RSA query clean register",
-              "offset": 2056,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "QUERY_CLEAN": {
-                    "description": "query clean",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SET_START_MODEXP": {
-              "description": "RSA modular exponentiation trigger register.",
-              "offset": 2060,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_START_MODEXP": {
-                    "description": "start modular exponentiation",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_START_MODMULT": {
-              "description": "RSA modular multiplication trigger register.",
-              "offset": 2064,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_START_MODMULT": {
-                    "description": "start modular multiplication",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SET_START_MULT": {
-              "description": "RSA normal multiplication trigger register.",
-              "offset": 2068,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SET_START_MULT": {
-                    "description": "start multiplicaiton",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "QUERY_IDLE": {
-              "description": "RSA query idle register",
-              "offset": 2072,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "QUERY_IDLE": {
-                    "description": "query rsa idle. 1'b0: busy, 1'b1: idle",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "RSA interrupt clear register",
-              "offset": 2076,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLEAR_INTERRUPT": {
-                    "description": "set this bit to clear RSA interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CONSTANT_TIME": {
-              "description": "RSA constant time option register",
-              "offset": 2080,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CONSTANT_TIME": {
-                    "description": "Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SEARCH_ENABLE": {
-              "description": "RSA search option",
-              "offset": 2084,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEARCH_ENABLE": {
-                    "description": "Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SEARCH_POS": {
-              "description": "RSA search position configure register",
-              "offset": 2088,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEARCH_POS": {
-                    "description": "Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "RSA interrupt enable register",
-              "offset": 2092,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INT_ENA": {
-                    "description": "Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "RSA version control register",
-              "offset": 2096,
-              "size": 32,
-              "reset_value": 538969624,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "rsa version information",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "RTC_CNTL": {
-        "description": "Real-Time Clock Control",
-        "children": {
-          "registers": {
-            "OPTIONS0": {
-              "description": "rtc configure register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 469803008,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SW_STALL_APPCPU_C0": {
-                    "description": "{reg_sw_stall_appcpu_c1[5:0],  reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "SW_STALL_PROCPU_C0": {
-                    "description": "{reg_sw_stall_procpu_c1[5:0],  reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "SW_APPCPU_RST": {
-                    "description": "APP CPU SW reset",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SW_PROCPU_RST": {
-                    "description": "PRO CPU SW reset",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "BB_I2C_FORCE_PD": {
-                    "description": "BB_I2C force power down",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "BB_I2C_FORCE_PU": {
-                    "description": "BB_I2C force power up",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "BBPLL_I2C_FORCE_PD": {
-                    "description": "BB_PLL _I2C force power down",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "BBPLL_I2C_FORCE_PU": {
-                    "description": "BB_PLL_I2C force power up",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "BBPLL_FORCE_PD": {
-                    "description": "BB_PLL force power down",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "BBPLL_FORCE_PU": {
-                    "description": "BB_PLL force power up",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "XTL_FORCE_PD": {
-                    "description": "crystall force power down",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "XTL_FORCE_PU": {
-                    "description": "crystall force power up",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "XTL_EN_WAIT": {
-                    "description": "wait bias_sleep and current source wakeup",
-                    "offset": 14,
-                    "size": 4
-                  },
-                  "XTL_EXT_CTR_SEL": {
-                    "description": "analog configure",
-                    "offset": 20,
-                    "size": 3
-                  },
-                  "XTL_FORCE_ISO": {
-                    "description": "analog configure",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "PLL_FORCE_ISO": {
-                    "description": "analog configure",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "ANALOG_FORCE_ISO": {
-                    "description": "analog configure",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "XTL_FORCE_NOISO": {
-                    "description": "analog configure",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "PLL_FORCE_NOISO": {
-                    "description": "analog configure",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "ANALOG_FORCE_NOISO": {
-                    "description": "analog configure",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_RST": {
-                    "description": "digital wrap force reset in deep sleep",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_NORST": {
-                    "description": "digital core force no reset in deep sleep",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SW_SYS_RST": {
-                    "description": "SW system reset",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "SLP_TIMER0": {
-              "description": "rtc configure register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_VAL_LO": {
-                    "description": "configure the  sleep time",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "SLP_TIMER1": {
-              "description": "rtc configure register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_VAL_HI": {
-                    "description": "RTC sleep timer high 16 bits",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "RTC_MAIN_TIMER_ALARM_EN": {
-                    "description": "timer alarm enable bit",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "TIME_UPDATE": {
-              "description": "rtc configure register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_SYS_STALL": {
-                    "description": "Enable to record system stall time",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "TIMER_XTL_OFF": {
-                    "description": "Enable to record 40M XTAL OFF time",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "TIMER_SYS_RST": {
-                    "description": "enable to record system reset time",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "RTC_TIME_UPDATE": {
-                    "description": "Set 1: to update register with RTC timer",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "TIME_LOW0": {
-              "description": "rtc configure register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_TIMER_VALUE0_LOW": {
-                    "description": "RTC timer low 32 bits",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "TIME_HIGH0": {
-              "description": "rtc configure register",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_TIMER_VALUE0_HIGH": {
-                    "description": "RTC timer high 16 bits",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "STATE0": {
-              "description": "rtc configure register",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SW_CPU_INT": {
-                    "description": "rtc software interrupt to main cpu",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_SLP_REJECT_CAUSE_CLR": {
-                    "description": "clear rtc sleep reject cause",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APB2RTC_BRIDGE_SEL": {
-                    "description": "1: APB to RTC using bridge",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "SDIO_ACTIVE_IND": {
-                    "description": "SDIO active indication",
-                    "offset": 28,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLP_WAKEUP": {
-                    "description": "leep wakeup bit",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "SLP_REJECT": {
-                    "description": "leep reject bit",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SLEEP_EN": {
-                    "description": "sleep enable bit",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TIMER1": {
-              "description": "rtc configure register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 672400387,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_STALL_EN": {
-                    "description": "CPU stall enable bit",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CPU_STALL_WAIT": {
-                    "description": "CPU stall wait cycles in fast_clk_rtc",
-                    "offset": 1,
-                    "size": 5
-                  },
-                  "CK8M_WAIT": {
-                    "description": "CK8M wait cycles in slow_clk_rtc",
-                    "offset": 6,
-                    "size": 8
-                  },
-                  "XTL_BUF_WAIT": {
-                    "description": "XTAL wait cycles in slow_clk_rtc",
-                    "offset": 14,
-                    "size": 10
-                  },
-                  "PLL_BUF_WAIT": {
-                    "description": "PLL wait cycles in slow_clk_rtc",
-                    "offset": 24,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "TIMER2": {
-              "description": "rtc configure register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 16777216,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MIN_TIME_CK8M_OFF": {
-                    "description": "minimal cycles in slow_clk_rtc for CK8M in power down state",
-                    "offset": 24,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "TIMER3": {
-              "description": "rtc configure register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 168299016,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WIFI_WAIT_TIMER": {
-                    "description": "wifi power domain wakeup time",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "WIFI_POWERUP_TIMER": {
-                    "description": "wifi power domain power on time",
-                    "offset": 9,
-                    "size": 7
-                  },
-                  "BT_WAIT_TIMER": {
-                    "description": "bt power domain wakeup time",
-                    "offset": 16,
-                    "size": 9
-                  },
-                  "BT_POWERUP_TIMER": {
-                    "description": "bt power domain power on time",
-                    "offset": 25,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "TIMER4": {
-              "description": "rtc configure register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 270535176,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_TOP_WAIT_TIMER": {
-                    "description": "cpu top power domain wakeup time",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "CPU_TOP_POWERUP_TIMER": {
-                    "description": "cpu top power domain power on time",
-                    "offset": 9,
-                    "size": 7
-                  },
-                  "DG_WRAP_WAIT_TIMER": {
-                    "description": "digital wrap power domain wakeup time",
-                    "offset": 16,
-                    "size": 9
-                  },
-                  "DG_WRAP_POWERUP_TIMER": {
-                    "description": "digital wrap power domain power on time",
-                    "offset": 25,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "TIMER5": {
-              "description": "rtc configure register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 32768,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MIN_SLP_VAL": {
-                    "description": "minimal sleep cycles in slow_clk_rtc",
-                    "offset": 8,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "TIMER6": {
-              "description": "rtc configure register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 168296448,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DG_PERI_WAIT_TIMER": {
-                    "description": "digital peri power domain wakeup time",
-                    "offset": 16,
-                    "size": 9
-                  },
-                  "DG_PERI_POWERUP_TIMER": {
-                    "description": "digital peri power domain power on time",
-                    "offset": 25,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "ANA_CONF": {
-              "description": "rtc configure register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 12845056,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RESET_POR_FORCE_PD": {
-                    "description": "force no bypass i2c power on reset",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "RESET_POR_FORCE_PU": {
-                    "description": "force bypass i2c power on reset",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "GLITCH_RST_EN": {
-                    "description": "enable glitch reset",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "SAR_I2C_PU": {
-                    "description": "PLLA force power up",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "PLLA_FORCE_PD": {
-                    "description": "PLLA force power down",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "PLLA_FORCE_PU": {
-                    "description": "PLLA force power up",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "BBPLL_CAL_SLP_START": {
-                    "description": "start BBPLL calibration during sleep",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "PVTMON_PU": {
-                    "description": "1: PVTMON power up",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "TXRF_I2C_PU": {
-                    "description": "1: TXRF_I2C power up",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "RFRX_PBUS_PU": {
-                    "description": "1: RFRX_PBUS power up",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "CKGEN_I2C_PU": {
-                    "description": "1: CKGEN_I2C power up",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "PLL_I2C_PU": {
-                    "description": "power up pll i2c",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RESET_STATE": {
-              "description": "rtc configure register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 12288,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RESET_CAUSE_PROCPU": {
-                    "description": "reset cause of PRO CPU",
-                    "offset": 0,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "RESET_CAUSE_APPCPU": {
-                    "description": "reset cause of APP CPU",
-                    "offset": 6,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "STAT_VECTOR_SEL_APPCPU": {
-                    "description": "APP CPU state vector sel",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "STAT_VECTOR_SEL_PROCPU": {
-                    "description": "PRO CPU state vector sel",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "ALL_RESET_FLAG_PROCPU": {
-                    "description": "PRO CPU reset_flag",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ALL_RESET_FLAG_APPCPU": {
-                    "description": "APP CPU reset flag",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ALL_RESET_FLAG_CLR_PROCPU": {
-                    "description": "clear PRO CPU reset_flag",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "ALL_RESET_FLAG_CLR_APPCPU": {
-                    "description": "clear APP CPU reset flag",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OCD_HALT_ON_RESET_APPCPU": {
-                    "description": "APPCPU OcdHaltOnReset",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "OCD_HALT_ON_RESET_PROCPU": {
-                    "description": "PROCPU OcdHaltOnReset",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "JTAG_RESET_FLAG_PROCPU": {
-                    "description": "configure jtag reset configure",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "JTAG_RESET_FLAG_APPCPU": {
-                    "description": "configure jtag reset configure",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "JTAG_RESET_FLAG_CLR_PROCPU": {
-                    "description": "configure jtag reset configure",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "JTAG_RESET_FLAG_CLR_APPCPU": {
-                    "description": "configure jtag reset configure",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_DRESET_MASK_APPCPU": {
-                    "description": "configure dreset configure",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "RTC_DRESET_MASK_PROCPU": {
-                    "description": "configure dreset configure",
-                    "offset": 25,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "WAKEUP_STATE": {
-              "description": "rtc configure register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 393216,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_WAKEUP_ENA": {
-                    "description": "wakeup enable bitmap",
-                    "offset": 15,
-                    "size": 17
-                  }
-                }
-              }
-            },
-            "INT_ENA_RTC": {
-              "description": "rtc configure register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_ENA": {
-                    "description": "enable sleep wakeup interrupt",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SLP_REJECT_INT_ENA": {
-                    "description": "enable sleep reject interrupt",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RTC_WDT_INT_ENA": {
-                    "description": "enable RTC WDT interrupt",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RTC_BROWN_OUT_INT_ENA": {
-                    "description": "enable brown out interrupt",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "RTC_MAIN_TIMER_INT_ENA": {
-                    "description": "enable RTC main timer interrupt",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "RTC_SWD_INT_ENA": {
-                    "description": "enable super watch dog interrupt",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RTC_XTAL32K_DEAD_INT_ENA": {
-                    "description": "enable xtal32k_dead  interrupt",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "RTC_GLITCH_DET_INT_ENA": {
-                    "description": "enbale gitch det interrupt",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "RTC_BBPLL_CAL_INT_ENA": {
-                    "description": "enbale bbpll cal end interrupt",
-                    "offset": 20,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_RAW_RTC": {
-              "description": "rtc configure register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_RAW": {
-                    "description": "sleep wakeup interrupt raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLP_REJECT_INT_RAW": {
-                    "description": "sleep reject interrupt raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_WDT_INT_RAW": {
-                    "description": "RTC WDT interrupt raw",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_BROWN_OUT_INT_RAW": {
-                    "description": "brown out interrupt raw",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_TIMER_INT_RAW": {
-                    "description": "RTC main timer interrupt raw",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_SWD_INT_RAW": {
-                    "description": "super watch dog interrupt raw",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_XTAL32K_DEAD_INT_RAW": {
-                    "description": "xtal32k dead detection interrupt raw",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_GLITCH_DET_INT_RAW": {
-                    "description": "glitch_det_interrupt_raw",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_BBPLL_CAL_INT_RAW": {
-                    "description": "bbpll cal end interrupt state",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST_RTC": {
-              "description": "rtc configure register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_ST": {
-                    "description": "sleep wakeup interrupt state",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLP_REJECT_INT_ST": {
-                    "description": "sleep reject interrupt state",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_WDT_INT_ST": {
-                    "description": "RTC WDT interrupt state",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_BROWN_OUT_INT_ST": {
-                    "description": "brown out interrupt state",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_TIMER_INT_ST": {
-                    "description": "RTC main timer interrupt state",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_SWD_INT_ST": {
-                    "description": "super watch dog interrupt state",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_XTAL32K_DEAD_INT_ST": {
-                    "description": "xtal32k dead detection interrupt state",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_GLITCH_DET_INT_ST": {
-                    "description": "glitch_det_interrupt state",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_BBPLL_CAL_INT_ST": {
-                    "description": "bbpll cal end interrupt state",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR_RTC": {
-              "description": "rtc configure register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_CLR": {
-                    "description": "Clear sleep wakeup interrupt state",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLP_REJECT_INT_CLR": {
-                    "description": "Clear sleep reject interrupt state",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_WDT_INT_CLR": {
-                    "description": "Clear RTC WDT interrupt state",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BROWN_OUT_INT_CLR": {
-                    "description": "Clear brown out interrupt state",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_MAIN_TIMER_INT_CLR": {
-                    "description": "Clear RTC main timer interrupt state",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_SWD_INT_CLR": {
-                    "description": "Clear super watch dog interrupt state",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_XTAL32K_DEAD_INT_CLR": {
-                    "description": "Clear RTC WDT interrupt state",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_GLITCH_DET_INT_CLR": {
-                    "description": "Clear glitch det interrupt state",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BBPLL_CAL_INT_CLR": {
-                    "description": "clear bbpll cal end interrupt state",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STORE0": {
-              "description": "rtc configure register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH0": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE1": {
-              "description": "rtc configure register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH1": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE2": {
-              "description": "rtc configure register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH2": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE3": {
-              "description": "rtc configure register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH3": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "EXT_XTL_CONF": {
-              "description": "rtc configure register",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 420992,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XTAL32K_WDT_EN": {
-                    "description": "xtal 32k watch dog enable",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "XTAL32K_WDT_CLK_FO": {
-                    "description": "xtal 32k watch dog clock force on",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "XTAL32K_WDT_RESET": {
-                    "description": "xtal 32k watch dog sw reset",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "XTAL32K_EXT_CLK_FO": {
-                    "description": "xtal 32k external xtal clock force on",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "XTAL32K_AUTO_BACKUP": {
-                    "description": "xtal 32k switch to back up clock when xtal is dead",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "XTAL32K_AUTO_RESTART": {
-                    "description": "xtal 32k restart xtal when xtal is dead",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "XTAL32K_AUTO_RETURN": {
-                    "description": "xtal 32k switch back xtal when xtal is restarted",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "XTAL32K_XPD_FORCE": {
-                    "description": "Xtal 32k xpd control by sw or fsm",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "ENCKINIT_XTAL_32K": {
-                    "description": "apply an internal clock to help xtal 32k to start",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DBUF_XTAL_32K": {
-                    "description": "0: single-end buffer 1: differential buffer",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "DGM_XTAL_32K": {
-                    "description": "xtal_32k gm control",
-                    "offset": 10,
-                    "size": 3
-                  },
-                  "DRES_XTAL_32K": {
-                    "description": "DRES_XTAL_32K",
-                    "offset": 13,
-                    "size": 3
-                  },
-                  "XPD_XTAL_32K": {
-                    "description": "XPD_XTAL_32K",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "DAC_XTAL_32K": {
-                    "description": "DAC_XTAL_32K",
-                    "offset": 17,
-                    "size": 3
-                  },
-                  "RTC_WDT_STATE": {
-                    "description": "state of 32k_wdt",
-                    "offset": 20,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "RTC_XTAL32K_GPIO_SEL": {
-                    "description": "XTAL_32K sel. 0: external XTAL_32K",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "XTL_EXT_CTR_LV": {
-                    "description": "0: power down XTAL at high level",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "XTL_EXT_CTR_EN": {
-                    "description": "enable gpio configure xtal power on",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "EXT_WAKEUP_CONF": {
-              "description": "rtc configure register",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "GPIO_WAKEUP_FILTER": {
-                    "description": "enable filter for gpio wakeup event",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLP_REJECT_CONF": {
-              "description": "rtc configure register",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SLEEP_REJECT_ENA": {
-                    "description": "sleep reject enable",
-                    "offset": 12,
-                    "size": 18
-                  },
-                  "LIGHT_SLP_REJECT_EN": {
-                    "description": "enable reject for light sleep",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DEEP_SLP_REJECT_EN": {
-                    "description": "enable reject for deep sleep",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_PERIOD_CONF": {
-              "description": "rtc configure register",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CPUSEL_CONF": {
-                    "description": "CPU sel option",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "RTC_CPUPERIOD_SEL": {
-                    "description": "CPU clk sel option",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CLK_CONF": {
-              "description": "rtc configure register",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 290992664,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "EFUSE_CLK_FORCE_GATING": {
-                    "description": "efuse_clk_force_gating",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "EFUSE_CLK_FORCE_NOGATING": {
-                    "description": "efuse_clk_force_nogating",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CK8M_DIV_SEL_VLD": {
-                    "description": "used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CK8M_DIV": {
-                    "description": "CK8M_D256_OUT divider. 00: div128",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "ENB_CK8M": {
-                    "description": "disable CK8M and CK8M_D256_OUT",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "ENB_CK8M_DIV": {
-                    "description": "1: CK8M_D256_OUT is actually CK8M",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "DIG_XTAL32K_EN": {
-                    "description": "enable CK_XTAL_32K for digital core (no relationship with RTC core)",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DIG_CLK8M_D256_EN": {
-                    "description": "enable CK8M_D256_OUT for digital core (no relationship with RTC core)",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "DIG_CLK8M_EN": {
-                    "description": "enable CK8M for digital core (no relationship with RTC core)",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CK8M_DIV_SEL": {
-                    "description": "divider = reg_ck8m_div_sel + 1",
-                    "offset": 12,
-                    "size": 3
-                  },
-                  "XTAL_FORCE_NOGATING": {
-                    "description": "XTAL force no gating during sleep",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "CK8M_FORCE_NOGATING": {
-                    "description": "CK8M force no gating during sleep",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "CK8M_DFREQ": {
-                    "description": "CK8M_DFREQ",
-                    "offset": 17,
-                    "size": 8
-                  },
-                  "CK8M_FORCE_PD": {
-                    "description": "CK8M force power down",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "CK8M_FORCE_PU": {
-                    "description": "CK8M force power up",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "XTAL_GLOBAL_FORCE_GATING": {
-                    "description": "force enable xtal clk gating",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "XTAL_GLOBAL_FORCE_NOGATING": {
-                    "description": "force bypass xtal clk gating",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "FAST_CLK_RTC_SEL": {
-                    "description": "fast_clk_rtc sel. 0: XTAL div 4",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "ANA_CLK_RTC_SEL": {
-                    "description": "slelect rtc slow clk",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "SLOW_CLK_CONF": {
-              "description": "rtc configure register",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 4194304,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_ANA_CLK_DIV_VLD": {
-                    "description": "used to sync div bus. clear vld before set reg_rtc_ana_clk_div",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "RTC_ANA_CLK_DIV": {
-                    "description": "the clk divider num of RTC_CLK",
-                    "offset": 23,
-                    "size": 8
-                  },
-                  "RTC_SLOW_CLK_NEXT_EDGE": {
-                    "description": "flag rtc_slow_clk_next_edge",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SDIO_CONF": {
-              "description": "rtc configure register",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 179355146,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SDIO_TIMER_TARGET": {
-                    "description": "timer count to apply reg_sdio_dcap after sdio power on",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "SDIO_DTHDRV": {
-                    "description": "Tieh = 1 mode drive ability. Initially set to 0 to limit charge current",
-                    "offset": 9,
-                    "size": 2
-                  },
-                  "SDIO_DCAP": {
-                    "description": "ability to prevent LDO from overshoot",
-                    "offset": 11,
-                    "size": 2
-                  },
-                  "SDIO_INITI": {
-                    "description": "add resistor from ldo output to ground. 0: no res",
-                    "offset": 13,
-                    "size": 2
-                  },
-                  "SDIO_EN_INITI": {
-                    "description": "0 to set init[1:0]=0",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SDIO_DCURLIM": {
-                    "description": "tune current limit threshold when tieh = 0. About 800mA/(8+d)",
-                    "offset": 16,
-                    "size": 3
-                  },
-                  "SDIO_MODECURLIM": {
-                    "description": "select current limit mode",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "SDIO_ENCURLIM": {
-                    "description": "enable current limit",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "SDIO_REG_PD_EN": {
-                    "description": "power down SDIO_REG in sleep. Only active when reg_sdio_force = 0",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "SDIO_FORCE": {
-                    "description": "1: use SW option to control SDIO_REG",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "SDIO_TIEH": {
-                    "description": "SW option for SDIO_TIEH. Only active when reg_sdio_force = 1",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "_1P8_READY": {
-                    "description": "read only register for REG1P8_READY",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DREFL_SDIO": {
-                    "description": "SW option for DREFL_SDIO. Only active when reg_sdio_force = 1",
-                    "offset": 25,
-                    "size": 2
-                  },
-                  "DREFM_SDIO": {
-                    "description": "SW option for DREFM_SDIO. Only active when reg_sdio_force = 1",
-                    "offset": 27,
-                    "size": 2
-                  },
-                  "DREFH_SDIO": {
-                    "description": "SW option for DREFH_SDIO. Only active when reg_sdio_force = 1",
-                    "offset": 29,
-                    "size": 2
-                  },
-                  "XPD_SDIO": {
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BIAS_CONF": {
-              "description": "rtc configure register",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 67584,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DG_VDD_DRV_B_SLP": {
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "DG_VDD_DRV_B_SLP_EN": {
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "BIAS_BUF_IDLE": {
-                    "description": "bias buf when rtc in normal work state",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "BIAS_BUF_WAKE": {
-                    "description": "bias buf when rtc in wakeup state",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "BIAS_BUF_DEEP_SLP": {
-                    "description": "bias buf when rtc in sleep state",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "BIAS_BUF_MONITOR": {
-                    "description": "bias buf when rtc in monitor state",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "PD_CUR_DEEP_SLP": {
-                    "description": "xpd cur when rtc in sleep_state",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "PD_CUR_MONITOR": {
-                    "description": "xpd cur when rtc in monitor state",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "BIAS_SLEEP_DEEP_SLP": {
-                    "description": "bias_sleep when rtc in sleep_state",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "BIAS_SLEEP_MONITOR": {
-                    "description": "bias_sleep when rtc in monitor state",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "DBG_ATTEN_DEEP_SLP": {
-                    "description": "DBG_ATTEN when rtc in sleep state",
-                    "offset": 18,
-                    "size": 4
-                  },
-                  "DBG_ATTEN_MONITOR": {
-                    "description": "DBG_ATTEN when rtc in monitor state",
-                    "offset": 22,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "RTC_CNTL": {
-              "description": "rtc configure register",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 2684354560,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIG_REG_CAL_EN": {
-                    "description": "software enable digital regulator cali",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "SCK_DCAP": {
-                    "description": "SCK_DCAP",
-                    "offset": 14,
-                    "size": 8
-                  },
-                  "DBOOST_FORCE_PD": {
-                    "description": "RTC_DBOOST force power down",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "DBOOST_FORCE_PU": {
-                    "description": "RTC_DBOOST force power up",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "REGULATOR_FORCE_PD": {
-                    "description": "RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "REGULATOR_FORCE_PU": {
-                    "description": "RTC_REG force power up",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PWC": {
-              "description": "rtc configure register",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_PAD_FORCE_HOLD": {
-                    "description": "rtc pad force hold",
-                    "offset": 21,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DIG_PWC": {
-              "description": "rtc configure register",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 5591056,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "VDD_SPI_PWR_DRV": {
-                    "description": "vdd_spi drv's software value",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "VDD_SPI_PWR_FORCE": {
-                    "description": "vdd_spi drv use software value",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "LSLP_MEM_FORCE_PD": {
-                    "description": "memories in digital core force PD in sleep",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "LSLP_MEM_FORCE_PU": {
-                    "description": "memories in digital core force PU in sleep",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "BT_FORCE_PD": {
-                    "description": "bt force power down",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "BT_FORCE_PU": {
-                    "description": "bt force power up",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "DG_PERI_FORCE_PD": {
-                    "description": "digital peri force power down",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "DG_PERI_FORCE_PU": {
-                    "description": "digital peri force power up",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "RTC_FASTMEM_FORCE_LPD": {
-                    "description": "fastmemory  retention mode in sleep",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RTC_FASTMEM_FORCE_LPU": {
-                    "description": "fastmemory donlt entry retention mode in sleep",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "WIFI_FORCE_PD": {
-                    "description": "wifi force power down",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "WIFI_FORCE_PU": {
-                    "description": "wifi force power up",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_PD": {
-                    "description": "digital core force power down",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_PU": {
-                    "description": "digital core force power up",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "CPU_TOP_FORCE_PD": {
-                    "description": "cpu core force power down",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "CPU_TOP_FORCE_PU": {
-                    "description": "cpu force power up",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "BT_PD_EN": {
-                    "description": "enable power down bt in sleep",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "DG_PERI_PD_EN": {
-                    "description": "enable power down digital peri in sleep",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "CPU_TOP_PD_EN": {
-                    "description": "enable power down cpu in sleep",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "WIFI_PD_EN": {
-                    "description": "enable power down wifi in sleep",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DG_WRAP_PD_EN": {
-                    "description": "enable power down digital wrap in sleep",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DIG_ISO": {
-              "description": "rtc configure register",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 2860535936,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FORCE_OFF": {
-                    "description": "DIG_ISO force off",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FORCE_ON": {
-                    "description": "DIG_ISO force on",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DG_PAD_AUTOHOLD": {
-                    "description": "read only register to indicate digital pad auto-hold status",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CLR_DG_PAD_AUTOHOLD": {
-                    "description": "wtite only register to clear digital pad auto-hold",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DG_PAD_AUTOHOLD_EN": {
-                    "description": "digital pad enable auto-hold",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "DG_PAD_FORCE_NOISO": {
-                    "description": "digital pad force no ISO",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "DG_PAD_FORCE_ISO": {
-                    "description": "digital pad force ISO",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "DG_PAD_FORCE_UNHOLD": {
-                    "description": "digital pad force un-hold",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "DG_PAD_FORCE_HOLD": {
-                    "description": "digital pad force hold",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "BT_FORCE_ISO": {
-                    "description": "bt force ISO",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "BT_FORCE_NOISO": {
-                    "description": "bt force no ISO",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "DG_PERI_FORCE_ISO": {
-                    "description": "Digital peri force ISO",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "DG_PERI_FORCE_NOISO": {
-                    "description": "digital peri force no ISO",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "CPU_TOP_FORCE_ISO": {
-                    "description": "cpu force ISO",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "CPU_TOP_FORCE_NOISO": {
-                    "description": "cpu force no ISO",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "WIFI_FORCE_ISO": {
-                    "description": "wifi force ISO",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "WIFI_FORCE_NOISO": {
-                    "description": "wifi force no ISO",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_ISO": {
-                    "description": "digital core force ISO",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DG_WRAP_FORCE_NOISO": {
-                    "description": "digital core force no ISO",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "WDTCONFIG0": {
-              "description": "rtc configure register",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 78356,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_CHIP_RESET_WIDTH": {
-                    "description": "chip reset siginal pulse width",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "WDT_CHIP_RESET_EN": {
-                    "description": "wdt reset whole chip enable",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "WDT_PAUSE_IN_SLP": {
-                    "description": "pause WDT in sleep",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "WDT_APPCPU_RESET_EN": {
-                    "description": "enable WDT reset APP CPU",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "WDT_PROCPU_RESET_EN": {
-                    "description": "enable WDT reset PRO CPU",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "WDT_FLASHBOOT_MOD_EN": {
-                    "description": "enable WDT in flash boot",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "WDT_SYS_RESET_LENGTH": {
-                    "description": "system reset counter length",
-                    "offset": 13,
-                    "size": 3
-                  },
-                  "WDT_CPU_RESET_LENGTH": {
-                    "description": "CPU reset counter length",
-                    "offset": 16,
-                    "size": 3
-                  },
-                  "WDT_STG3": {
-                    "description": "1: interrupt stage en",
-                    "offset": 19,
-                    "size": 3
-                  },
-                  "WDT_STG2": {
-                    "description": "1: interrupt stage en",
-                    "offset": 22,
-                    "size": 3
-                  },
-                  "WDT_STG1": {
-                    "description": "1: interrupt stage en",
-                    "offset": 25,
-                    "size": 3
-                  },
-                  "WDT_STG0": {
-                    "description": "1: interrupt stage en",
-                    "offset": 28,
-                    "size": 3
-                  },
-                  "WDT_EN": {
-                    "description": "enable rtc wdt",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "WDTCONFIG1": {
-              "description": "rtc configure register",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 200000,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG0_HOLD": {
-                    "description": "the hold time of stage0",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG2": {
-              "description": "rtc configure register",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 80000,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG1_HOLD": {
-                    "description": "the hold time of stage1",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG3": {
-              "description": "rtc configure register",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG2_HOLD": {
-                    "description": "the hold time of stage2",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG4": {
-              "description": "rtc configure register",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG3_HOLD": {
-                    "description": "the hold time of stage3",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTFEED": {
-              "description": "rtc configure register",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_WDT_FEED": {
-                    "description": "sw feed rtc wdt",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "WDTWPROTECT": {
-              "description": "rtc configure register",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_WKEY": {
-                    "description": "the key of rtc wdt",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "SWD_CONF": {
-              "description": "rtc configure register",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 78643200,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SWD_RESET_FLAG": {
-                    "description": "swd reset flag",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SWD_FEED_INT": {
-                    "description": "swd interrupt for feeding",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SWD_BYPASS_RST": {
-                    "description": "Bypass swd rst",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "SWD_SIGNAL_WIDTH": {
-                    "description": "adjust signal width send to swd",
-                    "offset": 18,
-                    "size": 10
-                  },
-                  "SWD_RST_FLAG_CLR": {
-                    "description": "reset swd reset flag",
-                    "offset": 28,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SWD_FEED": {
-                    "description": "Sw feed swd",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SWD_DISABLE": {
-                    "description": "disabel SWD",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SWD_AUTO_FEED_EN": {
-                    "description": "automatically feed swd when int comes",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SWD_WPROTECT": {
-              "description": "rtc configure register",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SWD_WKEY": {
-                    "description": "the key of super wdt",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "SW_CPU_STALL": {
-              "description": "rtc configure register",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SW_STALL_APPCPU_C1": {
-                    "description": "{reg_sw_stall_appcpu_c1[5:0]",
-                    "offset": 20,
-                    "size": 6
-                  },
-                  "SW_STALL_PROCPU_C1": {
-                    "description": "stall cpu by software",
-                    "offset": 26,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "STORE4": {
-              "description": "rtc configure register",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH4": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE5": {
-              "description": "rtc configure register",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH5": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE6": {
-              "description": "rtc configure register",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH6": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "STORE7": {
-              "description": "rtc configure register",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_SCRATCH7": {
-                    "description": "reserved register",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "LOW_POWER_ST": {
-              "description": "rtc configure register",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XPD_ROM0": {
-                    "description": "rom0 power down",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "XPD_DIG_DCDC": {
-                    "description": "External DCDC power down",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_PERI_ISO": {
-                    "description": "rtc peripheral iso",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "XPD_RTC_PERI": {
-                    "description": "rtc peripheral power down",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WIFI_ISO": {
-                    "description": "wifi iso",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "XPD_WIFI": {
-                    "description": "wifi wrap power down",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DIG_ISO": {
-                    "description": "digital wrap iso",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "XPD_DIG": {
-                    "description": "digital wrap power down",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_TOUCH_STATE_START": {
-                    "description": "touch should start to work",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_TOUCH_STATE_SWITCH": {
-                    "description": "touch is about to working. Switch rtc main state",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_TOUCH_STATE_SLP": {
-                    "description": "touch is in sleep state",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_TOUCH_STATE_DONE": {
-                    "description": "touch is done",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_COCPU_STATE_START": {
-                    "description": "ulp/cocpu should start to work",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_COCPU_STATE_SWITCH": {
-                    "description": "ulp/cocpu is about to working. Switch rtc main state",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_COCPU_STATE_SLP": {
-                    "description": "ulp/cocpu is in sleep state",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_COCPU_STATE_DONE": {
-                    "description": "ulp/cocpu is done",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_XTAL_ISO": {
-                    "description": "no use any more",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_PLL_ON": {
-                    "description": "rtc main state machine is in states that pll should be running",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_RDY_FOR_WAKEUP": {
-                    "description": "rtc is ready to receive wake up trigger from wake up source",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_WAIT_END": {
-                    "description": "rtc main state machine has been waited for some cycles",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_IN_WAKEUP_STATE": {
-                    "description": "rtc main state machine is in the states of wakeup process",
-                    "offset": 21,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_IN_LOW_POWER_STATE": {
-                    "description": "rtc main state machine is in the states of low power",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_IN_WAIT_8M": {
-                    "description": "rtc main state machine is in wait 8m state",
-                    "offset": 23,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_IN_WAIT_PLL": {
-                    "description": "rtc main state machine is in wait pll state",
-                    "offset": 24,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_IN_WAIT_XTL": {
-                    "description": "rtc main state machine is in wait xtal state",
-                    "offset": 25,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_IN_SLP": {
-                    "description": "rtc main state machine is in sleep state",
-                    "offset": 26,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE_IN_IDLE": {
-                    "description": "rtc main state machine is in idle state",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_MAIN_STATE": {
-                    "description": "rtc main state machine status",
-                    "offset": 28,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DIAG0": {
-              "description": "rtc configure register",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_LOW_POWER_DIAG1": {
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "PAD_HOLD": {
-              "description": "rtc configure register",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_GPIO_PIN0_HOLD": {
-                    "description": "the hold configure of rtc gpio0",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN1_HOLD": {
-                    "description": "the hold configure of rtc gpio1",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN2_HOLD": {
-                    "description": "the hold configure of rtc gpio2",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN3_HOLD": {
-                    "description": "the hold configure of rtc gpio3",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN4_HOLD": {
-                    "description": "the hold configure of rtc gpio4",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN5_HOLD": {
-                    "description": "the hold configure of rtc gpio5",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DIG_PAD_HOLD": {
-              "description": "rtc configure register",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIG_PAD_HOLD": {
-                    "description": "the configure of digital pad",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "BROWN_OUT": {
-              "description": "rtc configure register",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 1140785168,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INT_WAIT": {
-                    "description": "brown out interrupt wait cycles",
-                    "offset": 4,
-                    "size": 10
-                  },
-                  "CLOSE_FLASH_ENA": {
-                    "description": "enable close flash when brown out happens",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "PD_RF_ENA": {
-                    "description": "enable power down RF when brown out happens",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RST_WAIT": {
-                    "description": "brown out reset wait cycles",
-                    "offset": 16,
-                    "size": 10
-                  },
-                  "RST_ENA": {
-                    "description": "enable brown out reset",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "RST_SEL": {
-                    "description": "1:  4-pos reset",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "ANA_RST_EN": {
-                    "description": "brown_out origin reset enable",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "CNT_CLR": {
-                    "description": "clear brown out counter",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "ENA": {
-                    "description": "enable brown out",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "DET": {
-                    "description": "the flag of brown det from analog",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "TIME_LOW1": {
-              "description": "rtc configure register",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_TIMER_VALUE1_LOW": {
-                    "description": "RTC timer low 32 bits",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "TIME_HIGH1": {
-              "description": "rtc configure register",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_TIMER_VALUE1_HIGH": {
-                    "description": "RTC timer high 16 bits",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "XTAL32K_CLK_FACTOR": {
-              "description": "rtc configure register",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XTAL32K_CLK_FACTOR": {
-                    "description": "xtal 32k watch dog backup clock factor",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "XTAL32K_CONF": {
-              "description": "rtc configure register",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 267386880,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XTAL32K_RETURN_WAIT": {
-                    "description": "cycles to wait to return noral xtal 32k",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "XTAL32K_RESTART_WAIT": {
-                    "description": "cycles to wait to repower on xtal 32k",
-                    "offset": 4,
-                    "size": 16
-                  },
-                  "XTAL32K_WDT_TIMEOUT": {
-                    "description": "If no clock detected for this amount of time",
-                    "offset": 20,
-                    "size": 8
-                  },
-                  "XTAL32K_STABLE_THRES": {
-                    "description": "if restarted xtal32k period is smaller than this",
-                    "offset": 28,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "USB_CONF": {
-              "description": "rtc configure register",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IO_MUX_RESET_DISABLE": {
-                    "description": "disable io_mux reset",
-                    "offset": 18,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLP_REJECT_CAUSE": {
-              "description": "RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REJECT_CAUSE": {
-                    "description": "sleep reject cause",
-                    "offset": 0,
-                    "size": 18,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OPTION1": {
-              "description": "rtc configure register",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FORCE_DOWNLOAD_BOOT": {
-                    "description": "force chip entry download mode",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLP_WAKEUP_CAUSE": {
-              "description": "RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WAKEUP_CAUSE": {
-                    "description": "sleep wakeup cause",
-                    "offset": 0,
-                    "size": 17,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ULP_CP_TIMER_1": {
-              "description": "rtc configure register",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 51200,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ULP_CP_TIMER_SLP_CYCLE": {
-                    "description": "sleep cycles for ULP-coprocessor timer",
-                    "offset": 8,
-                    "size": 24
-                  }
-                }
-              }
-            },
-            "INT_ENA_RTC_W1TS": {
-              "description": "rtc configure register",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_ENA_W1TS": {
-                    "description": "enable sleep wakeup interrupt",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLP_REJECT_INT_ENA_W1TS": {
-                    "description": "enable sleep reject interrupt",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_WDT_INT_ENA_W1TS": {
-                    "description": "enable RTC WDT interrupt",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BROWN_OUT_INT_ENA_W1TS": {
-                    "description": "enable brown out interrupt",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_MAIN_TIMER_INT_ENA_W1TS": {
-                    "description": "enable RTC main timer interrupt",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_SWD_INT_ENA_W1TS": {
-                    "description": "enable super watch dog interrupt",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_XTAL32K_DEAD_INT_ENA_W1TS": {
-                    "description": "enable xtal32k_dead  interrupt",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_GLITCH_DET_INT_ENA_W1TS": {
-                    "description": "enbale gitch det interrupt",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BBPLL_CAL_INT_ENA_W1TS": {
-                    "description": "enbale bbpll cal interrupt",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA_RTC_W1TC": {
-              "description": "rtc configure register",
-              "offset": 260,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLP_WAKEUP_INT_ENA_W1TC": {
-                    "description": "clear sleep wakeup interrupt enable",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLP_REJECT_INT_ENA_W1TC": {
-                    "description": "clear sleep reject interrupt enable",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_WDT_INT_ENA_W1TC": {
-                    "description": "clear RTC WDT interrupt enable",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BROWN_OUT_INT_ENA_W1TC": {
-                    "description": "clear brown out interrupt enable",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_MAIN_TIMER_INT_ENA_W1TC": {
-                    "description": "Clear RTC main timer interrupt enable",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_SWD_INT_ENA_W1TC": {
-                    "description": "clear super watch dog interrupt enable",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_XTAL32K_DEAD_INT_ENA_W1TC": {
-                    "description": "clear xtal32k_dead  interrupt enable",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_GLITCH_DET_INT_ENA_W1TC": {
-                    "description": "clear gitch det interrupt enable",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RTC_BBPLL_CAL_INT_ENA_W1TC": {
-                    "description": "clear bbpll cal interrupt enable",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "RETENTION_CTRL": {
-              "description": "rtc configure register",
-              "offset": 264,
-              "size": 32,
-              "reset_value": 2697986048,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RETENTION_CLK_SEL": {
-                    "description": "Retention clk sel",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "RETENTION_DONE_WAIT": {
-                    "description": "Retention done wait time",
-                    "offset": 19,
-                    "size": 3
-                  },
-                  "RETENTION_CLKOFF_WAIT": {
-                    "description": "Retention clkoff wait time",
-                    "offset": 22,
-                    "size": 4
-                  },
-                  "RETENTION_EN": {
-                    "description": "enable cpu retention when light sleep",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "RETENTION_WAIT": {
-                    "description": "wait cycles for rention operation",
-                    "offset": 27,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "FIB_SEL": {
-              "description": "rtc configure register",
-              "offset": 268,
-              "size": 32,
-              "reset_value": 7,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_FIB_SEL": {
-                    "description": "select use analog fib signal",
-                    "offset": 0,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "GPIO_WAKEUP": {
-              "description": "rtc configure register",
-              "offset": 272,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_GPIO_WAKEUP_STATUS": {
-                    "description": "rtc gpio wakeup flag",
-                    "offset": 0,
-                    "size": 6,
-                    "access": "read-only"
-                  },
-                  "RTC_GPIO_WAKEUP_STATUS_CLR": {
-                    "description": "clear rtc gpio wakeup flag",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN_CLK_GATE": {
-                    "description": "enable rtc io clk gate",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN5_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 8,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN4_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 11,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN3_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 14,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN2_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 17,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN1_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 20,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN0_INT_TYPE": {
-                    "description": "configure gpio wakeup type",
-                    "offset": 23,
-                    "size": 3
-                  },
-                  "RTC_GPIO_PIN5_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio5",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN4_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio4",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN3_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio3",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN2_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio2",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN1_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio1",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN0_WAKEUP_ENABLE": {
-                    "description": "enable wakeup from rtc gpio0",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DBG_SEL": {
-              "description": "rtc configure register",
-              "offset": 276,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_DEBUG_12M_NO_GATING": {
-                    "description": "use for debug",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RTC_DEBUG_BIT_SEL": {
-                    "description": "use for debug",
-                    "offset": 2,
-                    "size": 5
-                  },
-                  "RTC_DEBUG_SEL0": {
-                    "description": "use for debug",
-                    "offset": 7,
-                    "size": 5
-                  },
-                  "RTC_DEBUG_SEL1": {
-                    "description": "use for debug",
-                    "offset": 12,
-                    "size": 5
-                  },
-                  "RTC_DEBUG_SEL2": {
-                    "description": "use for debug",
-                    "offset": 17,
-                    "size": 5
-                  },
-                  "RTC_DEBUG_SEL3": {
-                    "description": "use for debug",
-                    "offset": 22,
-                    "size": 5
-                  },
-                  "RTC_DEBUG_SEL4": {
-                    "description": "use for debug",
-                    "offset": 27,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "DBG_MAP": {
-              "description": "rtc configure register",
-              "offset": 280,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_GPIO_PIN5_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN4_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN3_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN2_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN1_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN0_MUX_SEL": {
-                    "description": "use for debug",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RTC_GPIO_PIN5_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 8,
-                    "size": 4
-                  },
-                  "RTC_GPIO_PIN4_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 12,
-                    "size": 4
-                  },
-                  "RTC_GPIO_PIN3_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 16,
-                    "size": 4
-                  },
-                  "RTC_GPIO_PIN2_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 20,
-                    "size": 4
-                  },
-                  "RTC_GPIO_PIN1_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 24,
-                    "size": 4
-                  },
-                  "RTC_GPIO_PIN0_FUN_SEL": {
-                    "description": "use for debug",
-                    "offset": 28,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "SENSOR_CTRL": {
-              "description": "rtc configure register",
-              "offset": 284,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SAR2_PWDET_CCT": {
-                    "description": "reg_sar2_pwdet_cct",
-                    "offset": 27,
-                    "size": 3
-                  },
-                  "FORCE_XPD_SAR": {
-                    "description": "force power up SAR",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DBG_SAR_SEL": {
-              "description": "rtc configure register",
-              "offset": 288,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SAR_DEBUG_SEL": {
-                    "description": "use for debug",
-                    "offset": 27,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "PG_CTRL": {
-              "description": "rtc configure register",
-              "offset": 292,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "POWER_GLITCH_DSENSE": {
-                    "description": "power glitch desense",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "POWER_GLITCH_FORCE_PD": {
-                    "description": "force disable power glitch",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "POWER_GLITCH_FORCE_PU": {
-                    "description": "force enable power glitch",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "POWER_GLITCH_EFUSE_SEL": {
-                    "description": "use efuse value control power glitch enable",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "POWER_GLITCH_EN": {
-                    "description": "enable power glitch",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "rtc configure register",
-              "offset": 508,
-              "size": 32,
-              "reset_value": 33583728,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CNTL_DATE": {
-                    "description": "verision",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SENSITIVE": {
-        "description": "Sensitive",
-        "children": {
-          "registers": {
-            "ROM_TABLE_LOCK": {
-              "description": "SENSITIVE_ROM_TABLE_LOCK_REG",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ROM_TABLE_LOCK": {
-                    "description": "rom_table_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ROM_TABLE": {
-              "description": "SENSITIVE_ROM_TABLE_REG",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ROM_TABLE": {
-                    "description": "rom_table",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "PRIVILEGE_MODE_SEL_LOCK": {
-              "description": "SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRIVILEGE_MODE_SEL_LOCK": {
-                    "description": "privilege_mode_sel_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PRIVILEGE_MODE_SEL": {
-              "description": "SENSITIVE_PRIVILEGE_MODE_SEL_REG",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRIVILEGE_MODE_SEL": {
-                    "description": "privilege_mode_sel",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "APB_PERIPHERAL_ACCESS_0": {
-              "description": "SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_PERIPHERAL_ACCESS_LOCK": {
-                    "description": "apb_peripheral_access_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "APB_PERIPHERAL_ACCESS_1": {
-              "description": "SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_PERIPHERAL_ACCESS_SPLIT_BURST": {
-                    "description": "apb_peripheral_access_split_burst",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INTERNAL_SRAM_USAGE_0": {
-              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_0_REG",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERNAL_SRAM_USAGE_LOCK": {
-                    "description": "internal_sram_usage_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INTERNAL_SRAM_USAGE_1": {
-              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_1_REG",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 15,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERNAL_SRAM_USAGE_CPU_CACHE": {
-                    "description": "internal_sram_usage_cpu_cache",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "INTERNAL_SRAM_USAGE_CPU_SRAM": {
-                    "description": "internal_sram_usage_cpu_sram",
-                    "offset": 1,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "INTERNAL_SRAM_USAGE_3": {
-              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_3_REG",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM": {
-                    "description": "internal_sram_usage_mac_dump_sram",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "INTERNAL_SRAM_ALLOC_MAC_DUMP": {
-                    "description": "internal_sram_alloc_mac_dump",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INTERNAL_SRAM_USAGE_4": {
-              "description": "SENSITIVE_INTERNAL_SRAM_USAGE_4_REG",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERNAL_SRAM_USAGE_LOG_SRAM": {
-                    "description": "internal_sram_usage_log_sram",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_TAG_ACCESS_0": {
-              "description": "SENSITIVE_CACHE_TAG_ACCESS_0_REG",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_TAG_ACCESS_LOCK": {
-                    "description": "cache_tag_access_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_TAG_ACCESS_1": {
-              "description": "SENSITIVE_CACHE_TAG_ACCESS_1_REG",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 15,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRO_I_TAG_RD_ACS": {
-                    "description": "pro_i_tag_rd_acs",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PRO_I_TAG_WR_ACS": {
-                    "description": "pro_i_tag_wr_acs",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "PRO_D_TAG_RD_ACS": {
-                    "description": "pro_d_tag_rd_acs",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "PRO_D_TAG_WR_ACS": {
-                    "description": "pro_d_tag_wr_acs",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_ACCESS_0": {
-              "description": "SENSITIVE_CACHE_MMU_ACCESS_0_REG",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_MMU_ACCESS_LOCK": {
-                    "description": "cache_mmu_access_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_MMU_ACCESS_1": {
-              "description": "SENSITIVE_CACHE_MMU_ACCESS_1_REG",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRO_MMU_RD_ACS": {
-                    "description": "pro_mmu_rd_acs",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PRO_MMU_WR_ACS": {
-                    "description": "pro_mmu_wr_acs",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_SPI2_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_spi2_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_SPI2_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_I2S0_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_I2S0_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_MAC_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_mac_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_MAC_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_mac_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_backup_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_backup_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_LC_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_lc_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_LC_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_lc_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_AES_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_aes_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_AES_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_aes_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_SHA_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_sha_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_SHA_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_sha_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 1044735,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_PMS_MONITOR_0": {
-              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_PMS_MONITOR_LOCK": {
-                    "description": "dma_apbperi_pms_monitor_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_PMS_MONITOR_1": {
-              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR": {
-                    "description": "dma_apbperi_pms_monitor_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_EN": {
-                    "description": "dma_apbperi_pms_monitor_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_PMS_MONITOR_2": {
-              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR": {
-                    "description": "dma_apbperi_pms_monitor_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
-                    "description": "dma_apbperi_pms_monitor_violate_status_world",
-                    "offset": 1,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
-                    "description": "dma_apbperi_pms_monitor_violate_status_addr",
-                    "offset": 3,
-                    "size": 24,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DMA_APBPERI_PMS_MONITOR_3": {
-              "description": "SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR": {
-                    "description": "dma_apbperi_pms_monitor_violate_status_wr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN": {
-                    "description": "dma_apbperi_pms_monitor_violate_status_byteen",
-                    "offset": 1,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK": {
-                    "description": "core_x_iram0_dram0_dma_split_line_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0": {
-                    "description": "core_x_iram0_dram0_dma_sram_category_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1": {
-                    "description": "core_x_iram0_dram0_dma_sram_category_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2": {
-                    "description": "core_x_iram0_dram0_dma_sram_category_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR": {
-                    "description": "core_x_iram0_dram0_dma_sram_splitaddr",
-                    "offset": 14,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0": {
-                    "description": "core_x_iram0_sram_line_0_category_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1": {
-                    "description": "core_x_iram0_sram_line_0_category_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2": {
-                    "description": "core_x_iram0_sram_line_0_category_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR": {
-                    "description": "core_x_iram0_sram_line_0_splitaddr",
-                    "offset": 14,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0": {
-                    "description": "core_x_iram0_sram_line_1_category_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1": {
-                    "description": "core_x_iram0_sram_line_1_category_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2": {
-                    "description": "core_x_iram0_sram_line_1_category_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR": {
-                    "description": "core_x_iram0_sram_line_1_splitaddr",
-                    "offset": 14,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0": {
-                    "description": "core_x_dram0_dma_sram_line_0_category_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1": {
-                    "description": "core_x_dram0_dma_sram_line_0_category_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2": {
-                    "description": "core_x_dram0_dma_sram_line_0_category_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR": {
-                    "description": "core_x_dram0_dma_sram_line_0_splitaddr",
-                    "offset": 14,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5": {
-              "description": "SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0": {
-                    "description": "core_x_dram0_dma_sram_line_1_category_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1": {
-                    "description": "core_x_dram0_dma_sram_line_1_category_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2": {
-                    "description": "core_x_dram0_dma_sram_line_1_category_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR": {
-                    "description": "core_x_dram0_dma_sram_line_1_splitaddr",
-                    "offset": 14,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_LOCK": {
-                    "description": "core_x_iram0_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 1867775,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_0",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_1",
-                    "offset": 3,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_2",
-                    "offset": 6,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_1_pms_3",
-                    "offset": 9,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0",
-                    "offset": 12,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS": {
-                    "description": "core_x_iram0_pms_constrain_rom_world_1_pms",
-                    "offset": 18,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "CORE_X_IRAM0_PMS_CONSTRAIN_2": {
-              "description": "SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 1867775,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_1",
-                    "offset": 3,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_2",
-                    "offset": 6,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_0_pms_3",
-                    "offset": 9,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0": {
-                    "description": "core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0",
-                    "offset": 12,
-                    "size": 3
-                  },
-                  "CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS": {
-                    "description": "core_x_iram0_pms_constrain_rom_world_0_pms",
-                    "offset": 18,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_PMS_MONITOR_0": {
-              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_PMS_MONITOR_LOCK": {
-                    "description": "core_0_iram0_pms_monitor_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_PMS_MONITOR_1": {
-              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR": {
-                    "description": "core_0_iram0_pms_monitor_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN": {
-                    "description": "core_0_iram0_pms_monitor_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_IRAM0_PMS_MONITOR_2": {
-              "description": "SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR": {
-                    "description": "core_0_iram0_pms_monitor_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR": {
-                    "description": "core_0_iram0_pms_monitor_violate_status_wr",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE": {
-                    "description": "core_0_iram0_pms_monitor_violate_status_loadstore",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
-                    "description": "core_0_iram0_pms_monitor_violate_status_world",
-                    "offset": 3,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
-                    "description": "core_0_iram0_pms_monitor_violate_status_addr",
-                    "offset": 5,
-                    "size": 24,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_X_DRAM0_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_LOCK": {
-                    "description": "core_x_dram0_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_X_DRAM0_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 252702975,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_0_pms_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_0",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_2",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3": {
-                    "description": "core_x_dram0_pms_constrain_sram_world_1_pms_3",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS": {
-                    "description": "core_x_dram0_pms_constrain_rom_world_0_pms",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS": {
-                    "description": "core_x_dram0_pms_constrain_rom_world_1_pms",
-                    "offset": 26,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_PMS_MONITOR_0": {
-              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_PMS_MONITOR_LOCK": {
-                    "description": "core_0_dram0_pms_monitor_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_PMS_MONITOR_1": {
-              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR": {
-                    "description": "core_0_dram0_pms_monitor_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN": {
-                    "description": "core_0_dram0_pms_monitor_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_PMS_MONITOR_2": {
-              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR": {
-                    "description": "core_0_dram0_pms_monitor_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK": {
-                    "description": "core_0_dram0_pms_monitor_violate_status_lock",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD": {
-                    "description": "core_0_dram0_pms_monitor_violate_status_world",
-                    "offset": 2,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR": {
-                    "description": "core_0_dram0_pms_monitor_violate_status_addr",
-                    "offset": 4,
-                    "size": 24,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_DRAM0_PMS_MONITOR_3": {
-              "description": "SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR": {
-                    "description": "core_0_dram0_pms_monitor_violate_status_wr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN": {
-                    "description": "core_0_dram0_pms_monitor_violate_status_byteen",
-                    "offset": 1,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG",
-              "offset": 216,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_LOCK": {
-                    "description": "core_0_pif_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 3473932287,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART": {
-                    "description": "core_0_pif_pms_constrain_world_0_uart",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1": {
-                    "description": "core_0_pif_pms_constrain_world_0_g0spi_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0": {
-                    "description": "core_0_pif_pms_constrain_world_0_g0spi_0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO": {
-                    "description": "core_0_pif_pms_constrain_world_0_gpio",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2": {
-                    "description": "core_0_pif_pms_constrain_world_0_fe2",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE": {
-                    "description": "core_0_pif_pms_constrain_world_0_fe",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER": {
-                    "description": "core_0_pif_pms_constrain_world_0_timer",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC": {
-                    "description": "core_0_pif_pms_constrain_world_0_rtc",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX": {
-                    "description": "core_0_pif_pms_constrain_world_0_io_mux",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG": {
-                    "description": "core_0_pif_pms_constrain_world_0_wdg",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC": {
-                    "description": "core_0_pif_pms_constrain_world_0_misc",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C": {
-                    "description": "core_0_pif_pms_constrain_world_0_i2c",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1": {
-                    "description": "core_0_pif_pms_constrain_world_0_uart1",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_2": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 4240641267,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT": {
-                    "description": "core_0_pif_pms_constrain_world_0_bt",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0": {
-                    "description": "core_0_pif_pms_constrain_world_0_i2c_ext0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0": {
-                    "description": "core_0_pif_pms_constrain_world_0_uhci0",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT": {
-                    "description": "core_0_pif_pms_constrain_world_0_rmt",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC": {
-                    "description": "core_0_pif_pms_constrain_world_0_ledc",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB": {
-                    "description": "core_0_pif_pms_constrain_world_0_bb",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP": {
-                    "description": "core_0_pif_pms_constrain_world_0_timergroup",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1": {
-                    "description": "core_0_pif_pms_constrain_world_0_timergroup1",
-                    "offset": 28,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER": {
-                    "description": "core_0_pif_pms_constrain_world_0_systimer",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_3": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 1019268147,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2": {
-                    "description": "core_0_pif_pms_constrain_world_0_spi_2",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL": {
-                    "description": "core_0_pif_pms_constrain_world_0_apb_ctrl",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN": {
-                    "description": "core_0_pif_pms_constrain_world_0_can",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1": {
-                    "description": "core_0_pif_pms_constrain_world_0_i2s1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT": {
-                    "description": "core_0_pif_pms_constrain_world_0_rwbt",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC": {
-                    "description": "core_0_pif_pms_constrain_world_0_wifimac",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR": {
-                    "description": "core_0_pif_pms_constrain_world_0_pwr",
-                    "offset": 28,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_4": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 4294964220,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP": {
-                    "description": "core_0_pif_pms_constrain_world_0_usb_wrap",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI": {
-                    "description": "core_0_pif_pms_constrain_world_0_crypto_peri",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA": {
-                    "description": "core_0_pif_pms_constrain_world_0_crypto_dma",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC": {
-                    "description": "core_0_pif_pms_constrain_world_0_apb_adc",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR": {
-                    "description": "core_0_pif_pms_constrain_world_0_bt_pwr",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE": {
-                    "description": "core_0_pif_pms_constrain_world_0_usb_device",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM": {
-                    "description": "core_0_pif_pms_constrain_world_0_system",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE": {
-                    "description": "core_0_pif_pms_constrain_world_0_sensitive",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT": {
-                    "description": "core_0_pif_pms_constrain_world_0_interrupt",
-                    "offset": 20,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY": {
-                    "description": "core_0_pif_pms_constrain_world_0_dma_copy",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG": {
-                    "description": "core_0_pif_pms_constrain_world_0_cache_config",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD": {
-                    "description": "core_0_pif_pms_constrain_world_0_ad",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO": {
-                    "description": "core_0_pif_pms_constrain_world_0_dio",
-                    "offset": 28,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER": {
-                    "description": "core_0_pif_pms_constrain_world_0_world_controller",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_5": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG",
-              "offset": 236,
-              "size": 32,
-              "reset_value": 3473932287,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART": {
-                    "description": "core_0_pif_pms_constrain_world_1_uart",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1": {
-                    "description": "core_0_pif_pms_constrain_world_1_g0spi_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0": {
-                    "description": "core_0_pif_pms_constrain_world_1_g0spi_0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO": {
-                    "description": "core_0_pif_pms_constrain_world_1_gpio",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2": {
-                    "description": "core_0_pif_pms_constrain_world_1_fe2",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE": {
-                    "description": "core_0_pif_pms_constrain_world_1_fe",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER": {
-                    "description": "core_0_pif_pms_constrain_world_1_timer",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC": {
-                    "description": "core_0_pif_pms_constrain_world_1_rtc",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX": {
-                    "description": "core_0_pif_pms_constrain_world_1_io_mux",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG": {
-                    "description": "core_0_pif_pms_constrain_world_1_wdg",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC": {
-                    "description": "core_0_pif_pms_constrain_world_1_misc",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C": {
-                    "description": "core_0_pif_pms_constrain_world_1_i2c",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1": {
-                    "description": "core_0_pif_pms_constrain_world_1_uart1",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_6": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 4240641267,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT": {
-                    "description": "core_0_pif_pms_constrain_world_1_bt",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0": {
-                    "description": "core_0_pif_pms_constrain_world_1_i2c_ext0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0": {
-                    "description": "core_0_pif_pms_constrain_world_1_uhci0",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT": {
-                    "description": "core_0_pif_pms_constrain_world_1_rmt",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC": {
-                    "description": "core_0_pif_pms_constrain_world_1_ledc",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB": {
-                    "description": "core_0_pif_pms_constrain_world_1_bb",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP": {
-                    "description": "core_0_pif_pms_constrain_world_1_timergroup",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1": {
-                    "description": "core_0_pif_pms_constrain_world_1_timergroup1",
-                    "offset": 28,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER": {
-                    "description": "core_0_pif_pms_constrain_world_1_systimer",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_7": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG",
-              "offset": 244,
-              "size": 32,
-              "reset_value": 1019268147,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2": {
-                    "description": "core_0_pif_pms_constrain_world_1_spi_2",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL": {
-                    "description": "core_0_pif_pms_constrain_world_1_apb_ctrl",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN": {
-                    "description": "core_0_pif_pms_constrain_world_1_can",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1": {
-                    "description": "core_0_pif_pms_constrain_world_1_i2s1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT": {
-                    "description": "core_0_pif_pms_constrain_world_1_rwbt",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC": {
-                    "description": "core_0_pif_pms_constrain_world_1_wifimac",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR": {
-                    "description": "core_0_pif_pms_constrain_world_1_pwr",
-                    "offset": 28,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_8": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 4294964220,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP": {
-                    "description": "core_0_pif_pms_constrain_world_1_usb_wrap",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI": {
-                    "description": "core_0_pif_pms_constrain_world_1_crypto_peri",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA": {
-                    "description": "core_0_pif_pms_constrain_world_1_crypto_dma",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC": {
-                    "description": "core_0_pif_pms_constrain_world_1_apb_adc",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR": {
-                    "description": "core_0_pif_pms_constrain_world_1_bt_pwr",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE": {
-                    "description": "core_0_pif_pms_constrain_world_1_usb_device",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM": {
-                    "description": "core_0_pif_pms_constrain_world_1_system",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE": {
-                    "description": "core_0_pif_pms_constrain_world_1_sensitive",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT": {
-                    "description": "core_0_pif_pms_constrain_world_1_interrupt",
-                    "offset": 20,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY": {
-                    "description": "core_0_pif_pms_constrain_world_1_dma_copy",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG": {
-                    "description": "core_0_pif_pms_constrain_world_1_cache_config",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD": {
-                    "description": "core_0_pif_pms_constrain_world_1_ad",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO": {
-                    "description": "core_0_pif_pms_constrain_world_1_dio",
-                    "offset": 28,
-                    "size": 2
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER": {
-                    "description": "core_0_pif_pms_constrain_world_1_world_controller",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_9": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 4194303,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_spltaddr_world_0",
-                    "offset": 0,
-                    "size": 11
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_spltaddr_world_1",
-                    "offset": 11,
-                    "size": 11
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_CONSTRAIN_10": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG",
-              "offset": 256,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_world_0_l",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_world_0_h",
-                    "offset": 3,
-                    "size": 3
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_world_1_l",
-                    "offset": 6,
-                    "size": 3
-                  },
-                  "CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H": {
-                    "description": "core_0_pif_pms_constrain_rtcfast_world_1_h",
-                    "offset": 9,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_0_REG",
-              "offset": 260,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_LOCK": {
-                    "description": "region_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_1_REG",
-              "offset": 264,
-              "size": 32,
-              "reset_value": 16383,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_0": {
-                    "description": "region_pms_constrain_world_0_area_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_1": {
-                    "description": "region_pms_constrain_world_0_area_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_2": {
-                    "description": "region_pms_constrain_world_0_area_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_3": {
-                    "description": "region_pms_constrain_world_0_area_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_4": {
-                    "description": "region_pms_constrain_world_0_area_4",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_5": {
-                    "description": "region_pms_constrain_world_0_area_5",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_0_AREA_6": {
-                    "description": "region_pms_constrain_world_0_area_6",
-                    "offset": 12,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_2": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_2_REG",
-              "offset": 268,
-              "size": 32,
-              "reset_value": 16383,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_0": {
-                    "description": "region_pms_constrain_world_1_area_0",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_1": {
-                    "description": "region_pms_constrain_world_1_area_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_2": {
-                    "description": "region_pms_constrain_world_1_area_2",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_3": {
-                    "description": "region_pms_constrain_world_1_area_3",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_4": {
-                    "description": "region_pms_constrain_world_1_area_4",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_5": {
-                    "description": "region_pms_constrain_world_1_area_5",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "REGION_PMS_CONSTRAIN_WORLD_1_AREA_6": {
-                    "description": "region_pms_constrain_world_1_area_6",
-                    "offset": 12,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_3": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_3_REG",
-              "offset": 272,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_0": {
-                    "description": "region_pms_constrain_addr_0",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_4": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_4_REG",
-              "offset": 276,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_1": {
-                    "description": "region_pms_constrain_addr_1",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_5": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_5_REG",
-              "offset": 280,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_2": {
-                    "description": "region_pms_constrain_addr_2",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_6": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_6_REG",
-              "offset": 284,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_3": {
-                    "description": "region_pms_constrain_addr_3",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_7": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_7_REG",
-              "offset": 288,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_4": {
-                    "description": "region_pms_constrain_addr_4",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_8": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_8_REG",
-              "offset": 292,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_5": {
-                    "description": "region_pms_constrain_addr_5",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_9": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_9_REG",
-              "offset": 296,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_6": {
-                    "description": "region_pms_constrain_addr_6",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "REGION_PMS_CONSTRAIN_10": {
-              "description": "SENSITIVE_REGION_PMS_CONSTRAIN_10_REG",
-              "offset": 300,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REGION_PMS_CONSTRAIN_ADDR_7": {
-                    "description": "region_pms_constrain_addr_7",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_0": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG",
-              "offset": 304,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_LOCK": {
-                    "description": "core_0_pif_pms_monitor_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_1": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG",
-              "offset": 308,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR": {
-                    "description": "core_0_pif_pms_monitor_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_EN": {
-                    "description": "core_0_pif_pms_monitor_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_2": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG",
-              "offset": 312,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR": {
-                    "description": "core_0_pif_pms_monitor_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0": {
-                    "description": "core_0_pif_pms_monitor_violate_status_hport_0",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE": {
-                    "description": "core_0_pif_pms_monitor_violate_status_hsize",
-                    "offset": 2,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE": {
-                    "description": "core_0_pif_pms_monitor_violate_status_hwrite",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD": {
-                    "description": "core_0_pif_pms_monitor_violate_status_hworld",
-                    "offset": 6,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_3": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG",
-              "offset": 316,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR": {
-                    "description": "core_0_pif_pms_monitor_violate_status_haddr",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_4": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG",
-              "offset": 320,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_5": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG",
-              "offset": 324,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_status_hsize",
-                    "offset": 1,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_status_hworld",
-                    "offset": 3,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CORE_0_PIF_PMS_MONITOR_6": {
-              "description": "SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG",
-              "offset": 328,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR": {
-                    "description": "core_0_pif_pms_monitor_nonword_violate_status_haddr",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_CONSTRAIN_0": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG",
-              "offset": 332,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_CONSTRAIN_LOCK": {
-                    "description": "backup_bus_pms_constrain_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_CONSTRAIN_1": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG",
-              "offset": 336,
-              "size": 32,
-              "reset_value": 3473932287,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_CONSTRAIN_UART": {
-                    "description": "backup_bus_pms_constrain_uart",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1": {
-                    "description": "backup_bus_pms_constrain_g0spi_1",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0": {
-                    "description": "backup_bus_pms_constrain_g0spi_0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_GPIO": {
-                    "description": "backup_bus_pms_constrain_gpio",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_FE2": {
-                    "description": "backup_bus_pms_constrain_fe2",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_FE": {
-                    "description": "backup_bus_pms_constrain_fe",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_TIMER": {
-                    "description": "backup_bus_pms_constrain_timer",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_RTC": {
-                    "description": "backup_bus_pms_constrain_rtc",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_IO_MUX": {
-                    "description": "backup_bus_pms_constrain_io_mux",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_WDG": {
-                    "description": "backup_bus_pms_constrain_wdg",
-                    "offset": 18,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_MISC": {
-                    "description": "backup_bus_pms_constrain_misc",
-                    "offset": 24,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_I2C": {
-                    "description": "backup_bus_pms_constrain_i2c",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_UART1": {
-                    "description": "backup_bus_pms_constrain_uart1",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_CONSTRAIN_2": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG",
-              "offset": 340,
-              "size": 32,
-              "reset_value": 4240641267,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_CONSTRAIN_BT": {
-                    "description": "backup_bus_pms_constrain_bt",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0": {
-                    "description": "backup_bus_pms_constrain_i2c_ext0",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_UHCI0": {
-                    "description": "backup_bus_pms_constrain_uhci0",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_RMT": {
-                    "description": "backup_bus_pms_constrain_rmt",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_LEDC": {
-                    "description": "backup_bus_pms_constrain_ledc",
-                    "offset": 16,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_BB": {
-                    "description": "backup_bus_pms_constrain_bb",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP": {
-                    "description": "backup_bus_pms_constrain_timergroup",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1": {
-                    "description": "backup_bus_pms_constrain_timergroup1",
-                    "offset": 28,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER": {
-                    "description": "backup_bus_pms_constrain_systimer",
-                    "offset": 30,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_CONSTRAIN_3": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG",
-              "offset": 344,
-              "size": 32,
-              "reset_value": 1019268147,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_CONSTRAIN_SPI_2": {
-                    "description": "backup_bus_pms_constrain_spi_2",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL": {
-                    "description": "backup_bus_pms_constrain_apb_ctrl",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_CAN": {
-                    "description": "backup_bus_pms_constrain_can",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_I2S1": {
-                    "description": "backup_bus_pms_constrain_i2s1",
-                    "offset": 14,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_RWBT": {
-                    "description": "backup_bus_pms_constrain_rwbt",
-                    "offset": 22,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC": {
-                    "description": "backup_bus_pms_constrain_wifimac",
-                    "offset": 26,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_PWR": {
-                    "description": "backup_bus_pms_constrain_pwr",
-                    "offset": 28,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_CONSTRAIN_4": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG",
-              "offset": 348,
-              "size": 32,
-              "reset_value": 62460,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP": {
-                    "description": "backup_bus_pms_constrain_usb_wrap",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI": {
-                    "description": "backup_bus_pms_constrain_crypto_peri",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA": {
-                    "description": "backup_bus_pms_constrain_crypto_dma",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_APB_ADC": {
-                    "description": "backup_bus_pms_constrain_apb_adc",
-                    "offset": 8,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_BT_PWR": {
-                    "description": "backup_bus_pms_constrain_bt_pwr",
-                    "offset": 12,
-                    "size": 2
-                  },
-                  "BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE": {
-                    "description": "backup_bus_pms_constrain_usb_device",
-                    "offset": 14,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_MONITOR_0": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG",
-              "offset": 352,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_MONITOR_LOCK": {
-                    "description": "backup_bus_pms_monitor_lock",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_MONITOR_1": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG",
-              "offset": 356,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR": {
-                    "description": "backup_bus_pms_monitor_violate_clr",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_EN": {
-                    "description": "backup_bus_pms_monitor_violate_en",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_MONITOR_2": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG",
-              "offset": 360,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR": {
-                    "description": "backup_bus_pms_monitor_violate_intr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS": {
-                    "description": "backup_bus_pms_monitor_violate_status_htrans",
-                    "offset": 1,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE": {
-                    "description": "backup_bus_pms_monitor_violate_status_hsize",
-                    "offset": 3,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE": {
-                    "description": "backup_bus_pms_monitor_violate_status_hwrite",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "BACKUP_BUS_PMS_MONITOR_3": {
-              "description": "SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG",
-              "offset": 364,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR": {
-                    "description": "backup_bus_pms_monitor_violate_haddr",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "SENSITIVE_CLOCK_GATE_REG",
-              "offset": 368,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "clk_en",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "SENSITIVE_DATE_REG",
-              "offset": 4092,
-              "size": 32,
-              "reset_value": 33620480,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "reg_date",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SHA": {
-        "description": "SHA (Secure Hash Algorithm) Accelerator",
-        "children": {
-          "registers": {
-            "MODE": {
-              "description": "Initial configuration register.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MODE": {
-                    "description": "Sha mode.",
-                    "offset": 0,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "T_STRING": {
-              "description": "SHA 512/t configuration register 0.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T_STRING": {
-                    "description": "Sha t_string (used if and only if mode == SHA_512/t).",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "T_LENGTH": {
-              "description": "SHA 512/t configuration register 1.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T_LENGTH": {
-                    "description": "Sha t_length (used if and only if mode == SHA_512/t).",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "DMA_BLOCK_NUM": {
-              "description": "DMA configuration register 0.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_BLOCK_NUM": {
-                    "description": "Dma-sha block number.",
-                    "offset": 0,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "START": {
-              "description": "Typical SHA configuration register 0.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "START": {
-                    "description": "Reserved.",
-                    "offset": 1,
-                    "size": 31,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CONTINUE": {
-              "description": "Typical SHA configuration register 1.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CONTINUE": {
-                    "description": "Reserved.",
-                    "offset": 1,
-                    "size": 31,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "BUSY": {
-              "description": "Busy register.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATE": {
-                    "description": "Sha busy state. 1'b0: idle. 1'b1: busy.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DMA_START": {
-              "description": "DMA configuration register 1.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_START": {
-                    "description": "Start dma-sha.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DMA_CONTINUE": {
-              "description": "DMA configuration register 2.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_CONTINUE": {
-                    "description": "Continue dma-sha.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CLEAR_IRQ": {
-              "description": "Interrupt clear register.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLEAR_INTERRUPT": {
-                    "description": "Clear sha interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "IRQ_ENA": {
-              "description": "Interrupt enable register.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "INTERRUPT_ENA": {
-                    "description": "Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "Date register.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 538969622,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "Sha date information/ sha version information.",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "H_MEM": {
-              "description": "Sha H memory which contains intermediate hash or finial hash.",
-              "offset": 64,
-              "size": 8,
-              "count": 64,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "M_MEM": {
-              "description": "Sha M memory which contains message.",
-              "offset": 128,
-              "size": 8,
-              "count": 64,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            }
-          }
-        }
-      },
-      "SPI0": {
-        "description": "SPI (Serial Peripheral Interface) Controller",
-        "children": {
-          "registers": {
-            "CTRL": {
-              "description": "SPI0 control register.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 2891776,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FDUMMY_OUT": {
-                    "description": "In the dummy phase the signal level of spi is output by the spi controller.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FCMD_DUAL": {
-                    "description": "Apply 2 signals during command phase 1:enable 0: disable",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FCMD_QUAD": {
-                    "description": "Apply 4 signals during command phase 1:enable 0: disable",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "FASTRD_MODE": {
-                    "description": "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "FREAD_DUAL": {
-                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "Q_POL": {
-                    "description": "The bit is used to set MISO line polarity, 1: high 0, low",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "D_POL": {
-                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "FREAD_QUAD": {
-                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "WP": {
-                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "FREAD_DIO": {
-                    "description": "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "FREAD_QIO": {
-                    "description": "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.",
-                    "offset": 24,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CTRL1": {
-              "description": "SPI0 control1 register.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_MODE": {
-                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "RXFIFO_RST": {
-                    "description": "SPI0 RX FIFO reset signal.",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CTRL2": {
-              "description": "SPI0 control2 register.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 33,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CS_SETUP_TIME": {
-                    "description": "(cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "CS_HOLD_TIME": {
-                    "description": "Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.",
-                    "offset": 5,
-                    "size": 5
-                  },
-                  "CS_HOLD_DELAY": {
-                    "description": "These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.",
-                    "offset": 25,
-                    "size": 6
-                  },
-                  "SYNC_RESET": {
-                    "description": "The FSM will be reset.",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CLOCK": {
-              "description": "SPI clock division control register.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 196867,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLKCNT_L": {
-                    "description": "In the master mode it must be equal to spi_mem_clkcnt_N.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CLKCNT_H": {
-                    "description": "In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "CLKCNT_N": {
-                    "description": "In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)",
-                    "offset": 16,
-                    "size": 8
-                  },
-                  "CLK_EQU_SYSCLK": {
-                    "description": "Set this bit in 1-division mode.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER": {
-              "description": "SPI0 user register.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CS_HOLD": {
-                    "description": "spi cs keep low when spi is in  done  phase. 1: enable 0: disable.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CS_SETUP": {
-                    "description": "spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "CK_OUT_EDGE": {
-                    "description": "the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "USR_DUMMY_IDLE": {
-                    "description": "spi clock is disable in dummy phase when the bit is enable.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "USR_DUMMY": {
-                    "description": "This bit enable the dummy phase of an operation.",
-                    "offset": 29,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER1": {
-              "description": "SPI0 user1 register.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 1543503879,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DUMMY_CYCLELEN": {
-                    "description": "The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).",
-                    "offset": 0,
-                    "size": 6
-                  },
-                  "USR_ADDR_BITLEN": {
-                    "description": "The length in bits of address phase. The register value shall be (bit_num-1).",
-                    "offset": 26,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "USER2": {
-              "description": "SPI0 user2 register.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 1879048192,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_COMMAND_VALUE": {
-                    "description": "The value of  command.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "USR_COMMAND_BITLEN": {
-                    "description": "The length in bits of command phase. The register value shall be (bit_num-1)",
-                    "offset": 28,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "RD_STATUS": {
-              "description": "SPI0 read control register.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WB_MODE": {
-                    "description": "Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.",
-                    "offset": 16,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "MISC": {
-              "description": "SPI0 misc register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TRANS_END": {
-                    "description": "The bit is used to indicate the  spi0_mst_st controlled transmitting is done.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "TRANS_END_INT_ENA": {
-                    "description": "The bit is used to enable the interrupt of  spi0_mst_st controlled transmitting is done.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CSPI_ST_TRANS_END": {
-                    "description": "The bit is used to indicate the  spi0_slv_st controlled transmitting is done.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CSPI_ST_TRANS_END_INT_ENA": {
-                    "description": "The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CK_IDLE_EDGE": {
-                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CS_KEEP_ACTIVE": {
-                    "description": "spi cs line keep low when the bit is set.",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_FCTRL": {
-              "description": "SPI0 bit mode control register.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_REQ_EN": {
-                    "description": "For SPI0, Cache access enable, 1: enable, 0:disable.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CACHE_USR_ADDR_4BYTE": {
-                    "description": "For SPI0,  cache  read flash with 4 bytes address, 1: enable, 0:disable.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CACHE_FLASH_USR_CMD": {
-                    "description": "For SPI0,  cache  read flash for user define command, 1: enable, 0:disable.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "FDIN_DUAL": {
-                    "description": "For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FDOUT_DUAL": {
-                    "description": "For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "FADDR_DUAL": {
-                    "description": "For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "FDIN_QUAD": {
-                    "description": "For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "FDOUT_QUAD": {
-                    "description": "For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FADDR_QUAD": {
-                    "description": "For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FSM": {
-              "description": "SPI0 FSM status register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 512,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CSPI_ST": {
-                    "description": "The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "EM_ST": {
-                    "description": "The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.",
-                    "offset": 4,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "CSPI_LOCK_DELAY_TIME": {
-                    "description": "The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.",
-                    "offset": 7,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "TIMING_CALI": {
-              "description": "SPI0 timing calibration register",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMING_CLK_ENA": {
-                    "description": "The bit is used to enable timing adjust clock for all reading operations.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TIMING_CALI": {
-                    "description": "The bit is used to enable timing auto-calibration for all reading operations.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "EXTRA_DUMMY_CYCLELEN": {
-                    "description": "add extra dummy spi clock cycle length for spi clock calibration.",
-                    "offset": 2,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "DIN_MODE": {
-              "description": "SPI0 input delay mode control register",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIN0_MODE": {
-                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DIN1_MODE": {
-                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DIN2_MODE": {
-                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DIN3_MODE": {
-                    "description": "the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb,  3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge,  6: input with the spi_clk low edge",
-                    "offset": 6,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DIN_NUM": {
-              "description": "SPI0 input delay number control register",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIN0_NUM": {
-                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DIN1_NUM": {
-                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DIN2_NUM": {
-                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DIN3_NUM": {
-                    "description": "the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...",
-                    "offset": 6,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DOUT_MODE": {
-              "description": "SPI0 output delay mode control register",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DOUT0_MODE": {
-                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DOUT1_MODE": {
-                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "DOUT2_MODE": {
-                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "DOUT3_MODE": {
-                    "description": "the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "SPI0 clk_gate register",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "Register clock gate enable signal. 1: Enable. 0: Disable.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CORE_CLK_SEL": {
-              "description": "SPI0 module clock select register",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI01_CLK_SEL": {
-                    "description": "When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel:  0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz.  2: SPI0/1 module clock (clk) 160MHz. 3: Not used.",
-                    "offset": 0,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "Version control register",
-              "offset": 1020,
-              "size": 32,
-              "reset_value": 33583408,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "SPI register version.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SPI1": {
-        "description": "SPI (Serial Peripheral Interface) Controller",
-        "children": {
-          "registers": {
-            "CMD": {
-              "description": "SPI1 memory command register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SPI1_MST_ST": {
-                    "description": "The current status of SPI1 master FSM.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "MSPI_ST": {
-                    "description": "The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.",
-                    "offset": 4,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "FLASH_PE": {
-                    "description": "In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "USR": {
-                    "description": "User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "FLASH_HPM": {
-                    "description": "Drive Flash into high performance mode.  The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "FLASH_RES": {
-                    "description": "This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "FLASH_DP": {
-                    "description": "Drive Flash into power down.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "FLASH_CE": {
-                    "description": "Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "FLASH_BE": {
-                    "description": "Block erase enable(32KB) .  Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "FLASH_SE": {
-                    "description": "Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "FLASH_PP": {
-                    "description": "Page program enable(1 byte ~256 bytes data to be programmed). Page program operation  will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "FLASH_WRSR": {
-                    "description": "Write status register enable.   Write status operation  will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "FLASH_RDSR": {
-                    "description": "Read status register-1.  Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "FLASH_RDID": {
-                    "description": "Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "FLASH_WRDI": {
-                    "description": "Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "FLASH_WREN": {
-                    "description": "Write flash enable.  Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "FLASH_READ": {
-                    "description": "Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ADDR": {
-              "description": "SPI1 address register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_ADDR_VALUE": {
-                    "description": "In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CTRL": {
-              "description": "SPI1 control register.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 2924544,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FDUMMY_OUT": {
-                    "description": "In the dummy phase the signal level of spi is output by the spi controller.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FCMD_DUAL": {
-                    "description": "Apply 2 signals during command phase 1:enable 0: disable",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FCMD_QUAD": {
-                    "description": "Apply 4 signals during command phase 1:enable 0: disable",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "FCS_CRC_EN": {
-                    "description": "For SPI1,  initialize crc32 module before writing encrypted data to flash. Active low.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "TX_CRC_EN": {
-                    "description": "For SPI1,  enable crc32 when writing encrypted data to flash. 1: enable 0:disable",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "FASTRD_MODE": {
-                    "description": "This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "FREAD_DUAL": {
-                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "RESANDRES": {
-                    "description": "The Device ID is read out to SPI_MEM_RD_STATUS register,  this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "Q_POL": {
-                    "description": "The bit is used to set MISO line polarity, 1: high 0, low",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "D_POL": {
-                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "FREAD_QUAD": {
-                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "WP": {
-                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "WRSR_2B": {
-                    "description": "two bytes data will be written to status register when it is set. 1: enable 0: disable.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "FREAD_DIO": {
-                    "description": "In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "FREAD_QIO": {
-                    "description": "In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.",
-                    "offset": 24,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CTRL1": {
-              "description": "SPI1 control1 register.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 4092,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_MODE": {
-                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CS_HOLD_DLY_RES": {
-                    "description": "After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.",
-                    "offset": 2,
-                    "size": 10
-                  }
-                }
-              }
-            },
-            "CTRL2": {
-              "description": "SPI1 control2 register.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYNC_RESET": {
-                    "description": "The FSM will be reset.",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CLOCK": {
-              "description": "SPI1 clock division control register.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 196867,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLKCNT_L": {
-                    "description": "In the master mode it must be equal to spi_mem_clkcnt_N.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CLKCNT_H": {
-                    "description": "In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "CLKCNT_N": {
-                    "description": "In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)",
-                    "offset": 16,
-                    "size": 8
-                  },
-                  "CLK_EQU_SYSCLK": {
-                    "description": "reserved",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER": {
-              "description": "SPI1 user register.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 2147483648,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CK_OUT_EDGE": {
-                    "description": "the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "FWRITE_DUAL": {
-                    "description": "In the write operations read-data phase apply 2 signals",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "FWRITE_QUAD": {
-                    "description": "In the write operations read-data phase apply 4 signals",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "FWRITE_DIO": {
-                    "description": "In the write operations address phase and read-data phase apply 2 signals.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "FWRITE_QIO": {
-                    "description": "In the write operations address phase and read-data phase apply 4 signals.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "USR_MISO_HIGHPART": {
-                    "description": "read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "USR_MOSI_HIGHPART": {
-                    "description": "write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "USR_DUMMY_IDLE": {
-                    "description": "SPI clock is disable in dummy phase when the bit is enable.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "USR_MOSI": {
-                    "description": "This bit enable the write-data phase of an operation.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "USR_MISO": {
-                    "description": "This bit enable the read-data phase of an operation.",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "USR_DUMMY": {
-                    "description": "This bit enable the dummy phase of an operation.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "USR_ADDR": {
-                    "description": "This bit enable the address phase of an operation.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "USR_COMMAND": {
-                    "description": "This bit enable the command phase of an operation.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER1": {
-              "description": "SPI1 user1 register.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 1543503879,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DUMMY_CYCLELEN": {
-                    "description": "The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).",
-                    "offset": 0,
-                    "size": 6
-                  },
-                  "USR_ADDR_BITLEN": {
-                    "description": "The length in bits of address phase. The register value shall be (bit_num-1).",
-                    "offset": 26,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "USER2": {
-              "description": "SPI1 user2 register.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 1879048192,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_COMMAND_VALUE": {
-                    "description": "The value of  command.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "USR_COMMAND_BITLEN": {
-                    "description": "The length in bits of command phase. The register value shall be (bit_num-1)",
-                    "offset": 28,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "MOSI_DLEN": {
-              "description": "SPI1 send data bit length control register.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_MOSI_DBITLEN": {
-                    "description": "The length in bits of write-data. The register value shall be (bit_num-1).",
-                    "offset": 0,
-                    "size": 10
-                  }
-                }
-              }
-            },
-            "MISO_DLEN": {
-              "description": "SPI1 receive data bit length control register.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_MISO_DBITLEN": {
-                    "description": "The length in bits of  read-data. The register value shall be (bit_num-1).",
-                    "offset": 0,
-                    "size": 10
-                  }
-                }
-              }
-            },
-            "RD_STATUS": {
-              "description": "SPI1 status register.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATUS": {
-                    "description": "The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "WB_MODE": {
-                    "description": "Mode bits in the flash fast read mode  it is combined with spi_mem_fastrd_mode bit.",
-                    "offset": 16,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "MISC": {
-              "description": "SPI1 misc register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CS0_DIS": {
-                    "description": "SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CS1_DIS": {
-                    "description": "SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CK_IDLE_EDGE": {
-                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "CS_KEEP_ACTIVE": {
-                    "description": "spi cs line keep low when the bit is set.",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TX_CRC": {
-              "description": "SPI1 TX CRC data register.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 4294967295,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATA": {
-                    "description": "For SPI1, the value of crc32.",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CACHE_FCTRL": {
-              "description": "SPI1 bit mode control register.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CACHE_USR_ADDR_4BYTE": {
-                    "description": "For SPI1,  cache  read flash with 4 bytes address, 1: enable, 0:disable.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "FDIN_DUAL": {
-                    "description": "For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FDOUT_DUAL": {
-                    "description": "For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "FADDR_DUAL": {
-                    "description": "For SPI1, address phase apply 2 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_dio.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "FDIN_QUAD": {
-                    "description": "For SPI1, din phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "FDOUT_QUAD": {
-                    "description": "For SPI1, dout phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "FADDR_QUAD": {
-                    "description": "For SPI1, address phase apply 4 signals. 1: enable 0: disable.  The bit is the same with spi_mem_fread_qio.",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "W0": {
-              "description": "SPI1 memory data buffer0",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF0": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W1": {
-              "description": "SPI1 memory data buffer1",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF1": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W2": {
-              "description": "SPI1 memory data buffer2",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF2": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W3": {
-              "description": "SPI1 memory data buffer3",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF3": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W4": {
-              "description": "SPI1 memory data buffer4",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF4": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W5": {
-              "description": "SPI1 memory data buffer5",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF5": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W6": {
-              "description": "SPI1 memory data buffer6",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF6": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W7": {
-              "description": "SPI1 memory data buffer7",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF7": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W8": {
-              "description": "SPI1 memory data buffer8",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF8": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W9": {
-              "description": "SPI1 memory data buffer9",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF9": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W10": {
-              "description": "SPI1 memory data buffer10",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF10": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W11": {
-              "description": "SPI1 memory data buffer11",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF11": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W12": {
-              "description": "SPI1 memory data buffer12",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF12": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W13": {
-              "description": "SPI1 memory data buffer13",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF13": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W14": {
-              "description": "SPI1 memory data buffer14",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF14": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W15": {
-              "description": "SPI1 memory data buffer15",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF15": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "FLASH_WAITI_CTRL": {
-              "description": "SPI1 wait idle control register",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 20,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WAITI_DUMMY": {
-                    "description": "The dummy phase enable when wait flash idle (RDSR)",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "WAITI_CMD": {
-                    "description": "The command to wait flash idle(RDSR).",
-                    "offset": 2,
-                    "size": 8
-                  },
-                  "WAITI_DUMMY_CYCLELEN": {
-                    "description": "The dummy cycle length when wait flash idle(RDSR).",
-                    "offset": 10,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "FLASH_SUS_CTRL": {
-              "description": "SPI1 flash suspend control register",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 134225920,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_PER": {
-                    "description": "program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "FLASH_PES": {
-                    "description": "program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "FLASH_PER_WAIT_EN": {
-                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "FLASH_PES_WAIT_EN": {
-                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PES_PER_EN": {
-                    "description": "Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "FLASH_PES_EN": {
-                    "description": "Set this bit to enable Auto-suspending function.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "PESR_END_MSK": {
-                    "description": "The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].",
-                    "offset": 6,
-                    "size": 16
-                  },
-                  "RD_SUS_2B": {
-                    "description": "1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0:  Read one byte when check flash SUS/SUS1/SUS2 status bit",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "PER_END_EN": {
-                    "description": "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "PES_END_EN": {
-                    "description": "1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "SUS_TIMEOUT_CNT": {
-                    "description": "When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.",
-                    "offset": 25,
-                    "size": 7
-                  }
-                }
-              }
-            },
-            "FLASH_SUS_CMD": {
-              "description": "SPI1 flash suspend command register",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 357754,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_PER_COMMAND": {
-                    "description": "Program/Erase resume command.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "FLASH_PES_COMMAND": {
-                    "description": "Program/Erase suspend command.",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "WAIT_PESR_COMMAND": {
-                    "description": "Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "SUS_STATUS": {
-              "description": "SPI1 flash suspend status register",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "FLASH_SUS": {
-                    "description": "The status of flash suspend, only used in SPI1.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "WAIT_PESR_CMD_2B": {
-                    "description": "1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "FLASH_HPM_DLY_128": {
-                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "FLASH_RES_DLY_128": {
-                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FLASH_DP_DLY_128": {
-                    "description": "1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "FLASH_PER_DLY_128": {
-                    "description": "Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "FLASH_PES_DLY_128": {
-                    "description": "Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SPI0_LOCK_EN": {
-                    "description": "1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TIMING_CALI": {
-              "description": "SPI1 timing control register",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMING_CALI": {
-                    "description": "The bit is used to enable timing auto-calibration for all reading operations.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "EXTRA_DUMMY_CYCLELEN": {
-                    "description": "add extra dummy spi clock cycle length for spi clock calibration.",
-                    "offset": 2,
-                    "size": 3
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "SPI1 interrupt enable register",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PER_END_INT_ENA": {
-                    "description": "The enable bit for SPI_MEM_PER_END_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PES_END_INT_ENA": {
-                    "description": "The enable bit for SPI_MEM_PES_END_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "WPE_END_INT_ENA": {
-                    "description": "The enable bit for SPI_MEM_WPE_END_INT interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "SLV_ST_END_INT_ENA": {
-                    "description": "The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "MST_ST_END_INT_ENA": {
-                    "description": "The enable bit for SPI_MEM_MST_ST_END_INT interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "SPI1 interrupt clear register",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PER_END_INT_CLR": {
-                    "description": "The clear bit for SPI_MEM_PER_END_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PES_END_INT_CLR": {
-                    "description": "The clear bit for SPI_MEM_PES_END_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "WPE_END_INT_CLR": {
-                    "description": "The clear bit for SPI_MEM_WPE_END_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_ST_END_INT_CLR": {
-                    "description": "The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MST_ST_END_INT_CLR": {
-                    "description": "The clear bit for SPI_MEM_MST_ST_END_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "SPI1 interrupt raw register",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PER_END_INT_RAW": {
-                    "description": "The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PES_END_INT_RAW": {
-                    "description": "The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WPE_END_INT_RAW": {
-                    "description": "The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_ST_END_INT_RAW": {
-                    "description": "The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_ST_END_INT_RAW": {
-                    "description": "The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "SPI1 interrupt status register",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PER_END_INT_ST": {
-                    "description": "The status bit for SPI_MEM_PER_END_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PES_END_INT_ST": {
-                    "description": "The status bit for SPI_MEM_PES_END_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WPE_END_INT_ST": {
-                    "description": "The status bit for SPI_MEM_WPE_END_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_ST_END_INT_ST": {
-                    "description": "The status bit for SPI_MEM_SLV_ST_END_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_ST_END_INT_ST": {
-                    "description": "The status bit for SPI_MEM_MST_ST_END_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "SPI1 clk_gate register",
-              "offset": 220,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "Register clock gate enable signal. 1: Enable. 0: Disable.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "Version control register",
-              "offset": 1020,
-              "size": 32,
-              "reset_value": 33583472,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "Version control register",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SPI2": {
-        "description": "SPI (Serial Peripheral Interface) Controller",
-        "children": {
-          "registers": {
-            "CMD": {
-              "description": "Command control register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CONF_BITLEN": {
-                    "description": "Define the APB cycles of  SPI_CONF state. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 18
-                  },
-                  "UPDATE": {
-                    "description": "Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "USR": {
-                    "description": "User define command enable.  An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.",
-                    "offset": 24,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ADDR": {
-              "description": "Address value register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_ADDR_VALUE": {
-                    "description": "Address to slave. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "CTRL": {
-              "description": "SPI control register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 3932160,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DUMMY_OUT": {
-                    "description": "In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "FADDR_DUAL": {
-                    "description": "Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "FADDR_QUAD": {
-                    "description": "Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "FCMD_DUAL": {
-                    "description": "Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "FCMD_QUAD": {
-                    "description": "Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "FREAD_DUAL": {
-                    "description": "In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "FREAD_QUAD": {
-                    "description": "In the read operations read-data phase apply 4 signals. 1: enable 0: disable.  Can be configured in CONF state.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "Q_POL": {
-                    "description": "The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "D_POL": {
-                    "description": "The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "HOLD_POL": {
-                    "description": "SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "WP_POL": {
-                    "description": "Write protect signal output when SPI is idle.  1: output high, 0: output low.  Can be configured in CONF state.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "RD_BIT_ORDER": {
-                    "description": "In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "WR_BIT_ORDER": {
-                    "description": "In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.",
-                    "offset": 26,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CLOCK": {
-              "description": "SPI clock control register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 2147496003,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLKCNT_L": {
-                    "description": "In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 6
-                  },
-                  "CLKCNT_H": {
-                    "description": "In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 6
-                  },
-                  "CLKCNT_N": {
-                    "description": "In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.",
-                    "offset": 12,
-                    "size": 6
-                  },
-                  "CLKDIV_PRE": {
-                    "description": "In the master mode it is pre-divider of spi_clk.  Can be configured in CONF state.",
-                    "offset": 18,
-                    "size": 4
-                  },
-                  "CLK_EQU_SYSCLK": {
-                    "description": "In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER": {
-              "description": "SPI USER control register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 2147483840,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DOUTDIN": {
-                    "description": "Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "QPI_MODE": {
-                    "description": "Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "TSCK_I_EDGE": {
-                    "description": "In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CS_HOLD": {
-                    "description": "spi cs keep low when spi is in  done  phase. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CS_SETUP": {
-                    "description": "spi cs is enable when spi is in  prepare  phase. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RSCK_I_EDGE": {
-                    "description": "In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "CK_OUT_EDGE": {
-                    "description": "the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "FWRITE_DUAL": {
-                    "description": "In the write operations read-data phase apply 2 signals. Can be configured in CONF state.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "FWRITE_QUAD": {
-                    "description": "In the write operations read-data phase apply 4 signals. Can be configured in CONF state.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "USR_CONF_NXT": {
-                    "description": "1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SIO": {
-                    "description": "Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "USR_MISO_HIGHPART": {
-                    "description": "read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "USR_MOSI_HIGHPART": {
-                    "description": "write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable.  Can be configured in CONF state.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "USR_DUMMY_IDLE": {
-                    "description": "spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "USR_MOSI": {
-                    "description": "This bit enable the write-data phase of an operation. Can be configured in CONF state.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "USR_MISO": {
-                    "description": "This bit enable the read-data phase of an operation. Can be configured in CONF state.",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "USR_DUMMY": {
-                    "description": "This bit enable the dummy phase of an operation. Can be configured in CONF state.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "USR_ADDR": {
-                    "description": "This bit enable the address phase of an operation. Can be configured in CONF state.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "USR_COMMAND": {
-                    "description": "This bit enable the command phase of an operation. Can be configured in CONF state.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "USER1": {
-              "description": "SPI USER control register 1",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 3091267591,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_DUMMY_CYCLELEN": {
-                    "description": "The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "MST_WFULL_ERR_END_EN": {
-                    "description": "1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "CS_SETUP_TIME": {
-                    "description": "(cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.",
-                    "offset": 17,
-                    "size": 5
-                  },
-                  "CS_HOLD_TIME": {
-                    "description": "delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.",
-                    "offset": 22,
-                    "size": 5
-                  },
-                  "USR_ADDR_BITLEN": {
-                    "description": "The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.",
-                    "offset": 27,
-                    "size": 5
-                  }
-                }
-              }
-            },
-            "USER2": {
-              "description": "SPI USER control register 2",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 2013265920,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USR_COMMAND_VALUE": {
-                    "description": "The value of  command. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 16
-                  },
-                  "MST_REMPTY_ERR_END_EN": {
-                    "description": "1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "USR_COMMAND_BITLEN": {
-                    "description": "The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.",
-                    "offset": 28,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "MS_DLEN": {
-              "description": "SPI data bit length control register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MS_DATA_BITLEN": {
-                    "description": "The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 18
-                  }
-                }
-              }
-            },
-            "MISC": {
-              "description": "SPI misc register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 62,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CS0_DIS": {
-                    "description": "SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CS1_DIS": {
-                    "description": "SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CS2_DIS": {
-                    "description": "SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CS3_DIS": {
-                    "description": "SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CS4_DIS": {
-                    "description": "SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CS5_DIS": {
-                    "description": "SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CK_DIS": {
-                    "description": "1: spi clk out disable,  0: spi clk out enable. Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "MASTER_CS_POL": {
-                    "description": "In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.",
-                    "offset": 7,
-                    "size": 6
-                  },
-                  "SLAVE_CS_POL": {
-                    "description": "spi slave input cs polarity select. 1: inv  0: not change. Can be configured in CONF state.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "CK_IDLE_EDGE": {
-                    "description": "1: spi clk line is high when idle     0: spi clk line is low when idle. Can be configured in CONF state.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "CS_KEEP_ACTIVE": {
-                    "description": "spi cs line keep low when the bit is set. Can be configured in CONF state.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "QUAD_DIN_PIN_SWAP": {
-                    "description": "1:  spi quad input swap enable  0:  spi quad input swap disable. Can be configured in CONF state.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DIN_MODE": {
-              "description": "SPI input delay mode configuration",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIN0_MODE": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DIN1_MODE": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DIN2_MODE": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DIN3_MODE": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 2
-                  },
-                  "TIMING_HCLK_ACTIVE": {
-                    "description": "1:enable hclk in SPI input timing module.  0: disable it. Can be configured in CONF state.",
-                    "offset": 16,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DIN_NUM": {
-              "description": "SPI input delay number configuration",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DIN0_NUM": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "DIN1_NUM": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "DIN2_NUM": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "DIN3_NUM": {
-                    "description": "the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...  Can be configured in CONF state.",
-                    "offset": 6,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "DOUT_MODE": {
-              "description": "SPI output delay mode configuration",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DOUT0_MODE": {
-                    "description": "The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DOUT1_MODE": {
-                    "description": "The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "DOUT2_MODE": {
-                    "description": "The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "DOUT3_MODE": {
-                    "description": "The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_CONF": {
-              "description": "SPI DMA control register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_SLV_SEG_TRANS_EN": {
-                    "description": "Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "SLV_RX_SEG_TRANS_CLR_EN": {
-                    "description": "1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "SLV_TX_SEG_TRANS_CLR_EN": {
-                    "description": "1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "RX_EOF_EN": {
-                    "description": "1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition.  0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "DMA_RX_ENA": {
-                    "description": "Set this bit to enable SPI DMA controlled receive data mode.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "DMA_TX_ENA": {
-                    "description": "Set this bit to enable SPI DMA controlled send data mode.",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "RX_AFIFO_RST": {
-                    "description": "Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "BUF_AFIFO_RST": {
-                    "description": "Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DMA_AFIFO_RST": {
-                    "description": "Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DMA_INT_ENA": {
-              "description": "SPI DMA interrupt enable register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_INFIFO_FULL_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DMA_OUTFIFO_EMPTY_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SLV_EX_QPI_INT_ENA": {
-                    "description": "The enable bit for SPI slave Ex_QPI interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "SLV_EN_QPI_INT_ENA": {
-                    "description": "The enable bit for SPI slave En_QPI interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SLV_CMD7_INT_ENA": {
-                    "description": "The enable bit for SPI slave CMD7 interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "SLV_CMD8_INT_ENA": {
-                    "description": "The enable bit for SPI slave CMD8 interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "SLV_CMD9_INT_ENA": {
-                    "description": "The enable bit for SPI slave CMD9 interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SLV_CMDA_INT_ENA": {
-                    "description": "The enable bit for SPI slave CMDA interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "SLV_RD_DMA_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "SLV_WR_DMA_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "SLV_RD_BUF_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "SLV_WR_BUF_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "TRANS_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_TRANS_DONE_INT interrupt.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "DMA_SEG_TRANS_DONE_INT_ENA": {
-                    "description": "The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "SEG_MAGIC_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "SLV_BUF_ADDR_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SLV_CMD_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_SLV_CMD_ERR_INT interrupt.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "MST_RX_AFIFO_WFULL_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "MST_TX_AFIFO_REMPTY_ERR_INT_ENA": {
-                    "description": "The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "APP2_INT_ENA": {
-                    "description": "The enable bit for SPI_APP2_INT interrupt.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "APP1_INT_ENA": {
-                    "description": "The enable bit for SPI_APP1_INT interrupt.",
-                    "offset": 20,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_INT_CLR": {
-              "description": "SPI DMA interrupt clear register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_INFIFO_FULL_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DMA_OUTFIFO_EMPTY_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_EX_QPI_INT_CLR": {
-                    "description": "The clear bit for SPI slave Ex_QPI interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_EN_QPI_INT_CLR": {
-                    "description": "The clear bit for SPI slave En_QPI interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_CMD7_INT_CLR": {
-                    "description": "The clear bit for SPI slave CMD7 interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_CMD8_INT_CLR": {
-                    "description": "The clear bit for SPI slave CMD8 interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_CMD9_INT_CLR": {
-                    "description": "The clear bit for SPI slave CMD9 interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_CMDA_INT_CLR": {
-                    "description": "The clear bit for SPI slave CMDA interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_RD_DMA_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_WR_DMA_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_RD_BUF_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_WR_BUF_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TRANS_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_TRANS_DONE_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DMA_SEG_TRANS_DONE_INT_CLR": {
-                    "description": "The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SEG_MAGIC_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_BUF_ADDR_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SLV_CMD_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_SLV_CMD_ERR_INT interrupt.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MST_RX_AFIFO_WFULL_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MST_TX_AFIFO_REMPTY_ERR_INT_CLR": {
-                    "description": "The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APP2_INT_CLR": {
-                    "description": "The clear bit for SPI_APP2_INT interrupt.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APP1_INT_CLR": {
-                    "description": "The clear bit for SPI_APP1_INT interrupt.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DMA_INT_RAW": {
-              "description": "SPI DMA interrupt raw register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_INFIFO_FULL_ERR_INT_RAW": {
-                    "description": "1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data.  0: Others.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DMA_OUTFIFO_EMPTY_ERR_INT_RAW": {
-                    "description": "1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode.  0: Others.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SLV_EX_QPI_INT_RAW": {
-                    "description": "The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "SLV_EN_QPI_INT_RAW": {
-                    "description": "The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SLV_CMD7_INT_RAW": {
-                    "description": "The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "SLV_CMD8_INT_RAW": {
-                    "description": "The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "SLV_CMD9_INT_RAW": {
-                    "description": "The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SLV_CMDA_INT_RAW": {
-                    "description": "The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "SLV_RD_DMA_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "SLV_WR_DMA_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "SLV_RD_BUF_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "SLV_WR_BUF_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "TRANS_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "DMA_SEG_TRANS_DONE_INT_RAW": {
-                    "description": "The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1:  spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory.  0:  seg-conf-trans or seg-trans is not ended or not occurred.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "SEG_MAGIC_ERR_INT_RAW": {
-                    "description": "The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "SLV_BUF_ADDR_ERR_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SLV_CMD_ERR_INT_RAW": {
-                    "description": "The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "MST_RX_AFIFO_WFULL_ERR_INT_RAW": {
-                    "description": "The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "MST_TX_AFIFO_REMPTY_ERR_INT_RAW": {
-                    "description": "The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "APP2_INT_RAW": {
-                    "description": "The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "APP1_INT_RAW": {
-                    "description": "The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.",
-                    "offset": 20,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DMA_INT_ST": {
-              "description": "SPI DMA interrupt status register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DMA_INFIFO_FULL_ERR_INT_ST": {
-                    "description": "The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DMA_OUTFIFO_EMPTY_ERR_INT_ST": {
-                    "description": "The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_EX_QPI_INT_ST": {
-                    "description": "The status bit for SPI slave Ex_QPI interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_EN_QPI_INT_ST": {
-                    "description": "The status bit for SPI slave En_QPI interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_CMD7_INT_ST": {
-                    "description": "The status bit for SPI slave CMD7 interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_CMD8_INT_ST": {
-                    "description": "The status bit for SPI slave CMD8 interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_CMD9_INT_ST": {
-                    "description": "The status bit for SPI slave CMD9 interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_CMDA_INT_ST": {
-                    "description": "The status bit for SPI slave CMDA interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_RD_DMA_DONE_INT_ST": {
-                    "description": "The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_WR_DMA_DONE_INT_ST": {
-                    "description": "The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_RD_BUF_DONE_INT_ST": {
-                    "description": "The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_WR_BUF_DONE_INT_ST": {
-                    "description": "The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TRANS_DONE_INT_ST": {
-                    "description": "The status bit for SPI_TRANS_DONE_INT interrupt.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DMA_SEG_TRANS_DONE_INT_ST": {
-                    "description": "The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SEG_MAGIC_ERR_INT_ST": {
-                    "description": "The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_BUF_ADDR_ERR_INT_ST": {
-                    "description": "The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SLV_CMD_ERR_INT_ST": {
-                    "description": "The status bit for SPI_SLV_CMD_ERR_INT interrupt.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_RX_AFIFO_WFULL_ERR_INT_ST": {
-                    "description": "The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MST_TX_AFIFO_REMPTY_ERR_INT_ST": {
-                    "description": "The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APP2_INT_ST": {
-                    "description": "The status bit for SPI_APP2_INT interrupt.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APP1_INT_ST": {
-                    "description": "The status bit for SPI_APP1_INT interrupt.",
-                    "offset": 20,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "W0": {
-              "description": "SPI CPU-controlled buffer0",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF0": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W1": {
-              "description": "SPI CPU-controlled buffer1",
-              "offset": 156,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF1": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W2": {
-              "description": "SPI CPU-controlled buffer2",
-              "offset": 160,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF2": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W3": {
-              "description": "SPI CPU-controlled buffer3",
-              "offset": 164,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF3": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W4": {
-              "description": "SPI CPU-controlled buffer4",
-              "offset": 168,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF4": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W5": {
-              "description": "SPI CPU-controlled buffer5",
-              "offset": 172,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF5": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W6": {
-              "description": "SPI CPU-controlled buffer6",
-              "offset": 176,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF6": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W7": {
-              "description": "SPI CPU-controlled buffer7",
-              "offset": 180,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF7": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W8": {
-              "description": "SPI CPU-controlled buffer8",
-              "offset": 184,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF8": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W9": {
-              "description": "SPI CPU-controlled buffer9",
-              "offset": 188,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF9": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W10": {
-              "description": "SPI CPU-controlled buffer10",
-              "offset": 192,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF10": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W11": {
-              "description": "SPI CPU-controlled buffer11",
-              "offset": 196,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF11": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W12": {
-              "description": "SPI CPU-controlled buffer12",
-              "offset": 200,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF12": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W13": {
-              "description": "SPI CPU-controlled buffer13",
-              "offset": 204,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF13": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W14": {
-              "description": "SPI CPU-controlled buffer14",
-              "offset": 208,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF14": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "W15": {
-              "description": "SPI CPU-controlled buffer15",
-              "offset": 212,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BUF15": {
-                    "description": "data buffer",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "SLAVE": {
-              "description": "SPI slave control register",
-              "offset": 224,
-              "size": 32,
-              "reset_value": 41943040,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_MODE": {
-                    "description": "SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "CLK_MODE_13": {
-                    "description": "{CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7].  0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RSCK_DATA_OUT": {
-                    "description": "It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge   0: output data at tsck posedge",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SLV_RDDMA_BITLEN_EN": {
-                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "SLV_WRDMA_BITLEN_EN": {
-                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "SLV_RDBUF_BITLEN_EN": {
-                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "SLV_WRBUF_BITLEN_EN": {
-                    "description": "1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "DMA_SEG_MAGIC_VALUE": {
-                    "description": "The magic value of BM table in master DMA seg-trans.",
-                    "offset": 22,
-                    "size": 4
-                  },
-                  "MODE": {
-                    "description": "Set SPI work mode. 1: slave mode 0: master mode.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "SOFT_RESET": {
-                    "description": "Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.",
-                    "offset": 27,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "USR_CONF": {
-                    "description": "1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.",
-                    "offset": 28,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLAVE1": {
-              "description": "SPI slave control register 1",
-              "offset": 228,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SLV_DATA_BITLEN": {
-                    "description": "The transferred data bit length in SPI slave FD and HD mode.",
-                    "offset": 0,
-                    "size": 18
-                  },
-                  "SLV_LAST_COMMAND": {
-                    "description": "In the slave mode it is the value of command.",
-                    "offset": 18,
-                    "size": 8
-                  },
-                  "SLV_LAST_ADDR": {
-                    "description": "In the slave mode it is the value of address.",
-                    "offset": 26,
-                    "size": 6
-                  }
-                }
-              }
-            },
-            "CLK_GATE": {
-              "description": "SPI module clock and register clock control",
-              "offset": 232,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "Set this bit to enable clk gate",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "MST_CLK_ACTIVE": {
-                    "description": "Set this bit to power on the SPI module clock.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "MST_CLK_SEL": {
-                    "description": "This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "Version control",
-              "offset": 240,
-              "size": 32,
-              "reset_value": 33583648,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "SPI register version.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SYSTEM": {
-        "description": "System",
-        "children": {
-          "registers": {
-            "CPU_PERI_CLK_EN": {
-              "description": "cpu_peripheral clock gating register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN_ASSIST_DEBUG": {
-                    "description": "reg_clk_en_assist_debug",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CLK_EN_DEDICATED_GPIO": {
-                    "description": "reg_clk_en_dedicated_gpio",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_PERI_RST_EN": {
-              "description": "cpu_peripheral reset register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 192,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RST_EN_ASSIST_DEBUG": {
-                    "description": "reg_rst_en_assist_debug",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "RST_EN_DEDICATED_GPIO": {
-                    "description": "reg_rst_en_dedicated_gpio",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_PER_CONF": {
-              "description": "cpu clock config register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 12,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPUPERIOD_SEL": {
-                    "description": "reg_cpuperiod_sel",
-                    "offset": 0,
-                    "size": 2
-                  },
-                  "PLL_FREQ_SEL": {
-                    "description": "reg_pll_freq_sel",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CPU_WAIT_MODE_FORCE_ON": {
-                    "description": "reg_cpu_wait_mode_force_on",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CPU_WAITI_DELAY_NUM": {
-                    "description": "reg_cpu_waiti_delay_num",
-                    "offset": 4,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "MEM_PD_MASK": {
-              "description": "memory power down mask register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LSLP_MEM_PD_MASK": {
-                    "description": "reg_lslp_mem_pd_mask",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERIP_CLK_EN0": {
-              "description": "peripheral clock gating register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 4190232687,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMERS_CLK_EN": {
-                    "description": "reg_timers_clk_en",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SPI01_CLK_EN": {
-                    "description": "reg_spi01_clk_en",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "UART_CLK_EN": {
-                    "description": "reg_uart_clk_en",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "WDG_CLK_EN": {
-                    "description": "reg_wdg_clk_en",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "I2S0_CLK_EN": {
-                    "description": "reg_i2s0_clk_en",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "UART1_CLK_EN": {
-                    "description": "reg_uart1_clk_en",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "SPI2_CLK_EN": {
-                    "description": "reg_spi2_clk_en",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "I2C_EXT0_CLK_EN": {
-                    "description": "reg_ext0_clk_en",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "UHCI0_CLK_EN": {
-                    "description": "reg_uhci0_clk_en",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "RMT_CLK_EN": {
-                    "description": "reg_rmt_clk_en",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "PCNT_CLK_EN": {
-                    "description": "reg_pcnt_clk_en",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "LEDC_CLK_EN": {
-                    "description": "reg_ledc_clk_en",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "UHCI1_CLK_EN": {
-                    "description": "reg_uhci1_clk_en",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TIMERGROUP_CLK_EN": {
-                    "description": "reg_timergroup_clk_en",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "EFUSE_CLK_EN": {
-                    "description": "reg_efuse_clk_en",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "TIMERGROUP1_CLK_EN": {
-                    "description": "reg_timergroup1_clk_en",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SPI3_CLK_EN": {
-                    "description": "reg_spi3_clk_en",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "PWM0_CLK_EN": {
-                    "description": "reg_pwm0_clk_en",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "EXT1_CLK_EN": {
-                    "description": "reg_ext1_clk_en",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "CAN_CLK_EN": {
-                    "description": "reg_can_clk_en",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "PWM1_CLK_EN": {
-                    "description": "reg_pwm1_clk_en",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "I2S1_CLK_EN": {
-                    "description": "reg_i2s1_clk_en",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "SPI2_DMA_CLK_EN": {
-                    "description": "reg_spi2_dma_clk_en",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "USB_DEVICE_CLK_EN": {
-                    "description": "reg_usb_device_clk_en",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "UART_MEM_CLK_EN": {
-                    "description": "reg_uart_mem_clk_en",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "PWM2_CLK_EN": {
-                    "description": "reg_pwm2_clk_en",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "PWM3_CLK_EN": {
-                    "description": "reg_pwm3_clk_en",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "SPI3_DMA_CLK_EN": {
-                    "description": "reg_spi3_dma_clk_en",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "APB_SARADC_CLK_EN": {
-                    "description": "reg_apb_saradc_clk_en",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "SYSTIMER_CLK_EN": {
-                    "description": "reg_systimer_clk_en",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "ADC2_ARB_CLK_EN": {
-                    "description": "reg_adc2_arb_clk_en",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SPI4_CLK_EN": {
-                    "description": "reg_spi4_clk_en",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERIP_CLK_EN1": {
-              "description": "peripheral clock gating register",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 512,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CRYPTO_AES_CLK_EN": {
-                    "description": "reg_crypto_aes_clk_en",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CRYPTO_SHA_CLK_EN": {
-                    "description": "reg_crypto_sha_clk_en",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CRYPTO_RSA_CLK_EN": {
-                    "description": "reg_crypto_rsa_clk_en",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CRYPTO_DS_CLK_EN": {
-                    "description": "reg_crypto_ds_clk_en",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CRYPTO_HMAC_CLK_EN": {
-                    "description": "reg_crypto_hmac_clk_en",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "DMA_CLK_EN": {
-                    "description": "reg_dma_clk_en",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SDIO_HOST_CLK_EN": {
-                    "description": "reg_sdio_host_clk_en",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "LCD_CAM_CLK_EN": {
-                    "description": "reg_lcd_cam_clk_en",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "UART2_CLK_EN": {
-                    "description": "reg_uart2_clk_en",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "TSENS_CLK_EN": {
-                    "description": "reg_tsens_clk_en",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERIP_RST_EN0": {
-              "description": "reserved",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMERS_RST": {
-                    "description": "reg_timers_rst",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SPI01_RST": {
-                    "description": "reg_spi01_rst",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "UART_RST": {
-                    "description": "reg_uart_rst",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "WDG_RST": {
-                    "description": "reg_wdg_rst",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "I2S0_RST": {
-                    "description": "reg_i2s0_rst",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "UART1_RST": {
-                    "description": "reg_uart1_rst",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "SPI2_RST": {
-                    "description": "reg_spi2_rst",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "I2C_EXT0_RST": {
-                    "description": "reg_ext0_rst",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "UHCI0_RST": {
-                    "description": "reg_uhci0_rst",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "RMT_RST": {
-                    "description": "reg_rmt_rst",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "PCNT_RST": {
-                    "description": "reg_pcnt_rst",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "LEDC_RST": {
-                    "description": "reg_ledc_rst",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "UHCI1_RST": {
-                    "description": "reg_uhci1_rst",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TIMERGROUP_RST": {
-                    "description": "reg_timergroup_rst",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "EFUSE_RST": {
-                    "description": "reg_efuse_rst",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "TIMERGROUP1_RST": {
-                    "description": "reg_timergroup1_rst",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "SPI3_RST": {
-                    "description": "reg_spi3_rst",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "PWM0_RST": {
-                    "description": "reg_pwm0_rst",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "EXT1_RST": {
-                    "description": "reg_ext1_rst",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "CAN_RST": {
-                    "description": "reg_can_rst",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "PWM1_RST": {
-                    "description": "reg_pwm1_rst",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "I2S1_RST": {
-                    "description": "reg_i2s1_rst",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "SPI2_DMA_RST": {
-                    "description": "reg_spi2_dma_rst",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "USB_DEVICE_RST": {
-                    "description": "reg_usb_device_rst",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "UART_MEM_RST": {
-                    "description": "reg_uart_mem_rst",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "PWM2_RST": {
-                    "description": "reg_pwm2_rst",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "PWM3_RST": {
-                    "description": "reg_pwm3_rst",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "SPI3_DMA_RST": {
-                    "description": "reg_spi3_dma_rst",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "APB_SARADC_RST": {
-                    "description": "reg_apb_saradc_rst",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "SYSTIMER_RST": {
-                    "description": "reg_systimer_rst",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "ADC2_ARB_RST": {
-                    "description": "reg_adc2_arb_rst",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "SPI4_RST": {
-                    "description": "reg_spi4_rst",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PERIP_RST_EN1": {
-              "description": "peripheral reset register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 510,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CRYPTO_AES_RST": {
-                    "description": "reg_crypto_aes_rst",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CRYPTO_SHA_RST": {
-                    "description": "reg_crypto_sha_rst",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "CRYPTO_RSA_RST": {
-                    "description": "reg_crypto_rsa_rst",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "CRYPTO_DS_RST": {
-                    "description": "reg_crypto_ds_rst",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CRYPTO_HMAC_RST": {
-                    "description": "reg_crypto_hmac_rst",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "DMA_RST": {
-                    "description": "reg_dma_rst",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SDIO_HOST_RST": {
-                    "description": "reg_sdio_host_rst",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "LCD_CAM_RST": {
-                    "description": "reg_lcd_cam_rst",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "UART2_RST": {
-                    "description": "reg_uart2_rst",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "TSENS_RST": {
-                    "description": "reg_tsens_rst",
-                    "offset": 10,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BT_LPCK_DIV_INT": {
-              "description": "clock config register",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 255,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_LPCK_DIV_NUM": {
-                    "description": "reg_bt_lpck_div_num",
-                    "offset": 0,
-                    "size": 12
-                  }
-                }
-              }
-            },
-            "BT_LPCK_DIV_FRAC": {
-              "description": "clock config register",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 33558529,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BT_LPCK_DIV_B": {
-                    "description": "reg_bt_lpck_div_b",
-                    "offset": 0,
-                    "size": 12
-                  },
-                  "BT_LPCK_DIV_A": {
-                    "description": "reg_bt_lpck_div_a",
-                    "offset": 12,
-                    "size": 12
-                  },
-                  "LPCLK_SEL_RTC_SLOW": {
-                    "description": "reg_lpclk_sel_rtc_slow",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "LPCLK_SEL_8M": {
-                    "description": "reg_lpclk_sel_8m",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "LPCLK_SEL_XTAL": {
-                    "description": "reg_lpclk_sel_xtal",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "LPCLK_SEL_XTAL32K": {
-                    "description": "reg_lpclk_sel_xtal32k",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "LPCLK_RTC_EN": {
-                    "description": "reg_lpclk_rtc_en",
-                    "offset": 28,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_0": {
-              "description": "interrupt generate register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_0": {
-                    "description": "reg_cpu_intr_from_cpu_0",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_1": {
-              "description": "interrupt generate register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_1": {
-                    "description": "reg_cpu_intr_from_cpu_1",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_2": {
-              "description": "interrupt generate register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_2": {
-                    "description": "reg_cpu_intr_from_cpu_2",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CPU_INTR_FROM_CPU_3": {
-              "description": "interrupt generate register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CPU_INTR_FROM_CPU_3": {
-                    "description": "reg_cpu_intr_from_cpu_3",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RSA_PD_CTRL": {
-              "description": "rsa memory power control register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RSA_MEM_PD": {
-                    "description": "reg_rsa_mem_pd",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "RSA_MEM_FORCE_PU": {
-                    "description": "reg_rsa_mem_force_pu",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RSA_MEM_FORCE_PD": {
-                    "description": "reg_rsa_mem_force_pd",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "EDMA_CTRL": {
-              "description": "edma clcok and reset register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "EDMA_CLK_ON": {
-                    "description": "reg_edma_clk_on",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "EDMA_RESET": {
-                    "description": "reg_edma_reset",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CACHE_CONTROL": {
-              "description": "cache control register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 5,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ICACHE_CLK_ON": {
-                    "description": "reg_icache_clk_on",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ICACHE_RESET": {
-                    "description": "reg_icache_reset",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "DCACHE_CLK_ON": {
-                    "description": "reg_dcache_clk_on",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "DCACHE_RESET": {
-                    "description": "reg_dcache_reset",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL": {
-              "description": "SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENABLE_SPI_MANUAL_ENCRYPT": {
-                    "description": "reg_enable_spi_manual_encrypt",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "ENABLE_DOWNLOAD_DB_ENCRYPT": {
-                    "description": "reg_enable_download_db_encrypt",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ENABLE_DOWNLOAD_G0CB_DECRYPT": {
-                    "description": "reg_enable_download_g0cb_decrypt",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "ENABLE_DOWNLOAD_MANUAL_ENCRYPT": {
-                    "description": "reg_enable_download_manual_encrypt",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RTC_FASTMEM_CONFIG": {
-              "description": "fast memory config register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 2146435072,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_MEM_CRC_START": {
-                    "description": "reg_rtc_mem_crc_start",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "RTC_MEM_CRC_ADDR": {
-                    "description": "reg_rtc_mem_crc_addr",
-                    "offset": 9,
-                    "size": 11
-                  },
-                  "RTC_MEM_CRC_LEN": {
-                    "description": "reg_rtc_mem_crc_len",
-                    "offset": 20,
-                    "size": 11
-                  },
-                  "RTC_MEM_CRC_FINISH": {
-                    "description": "reg_rtc_mem_crc_finish",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RTC_FASTMEM_CRC": {
-              "description": "reserved",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_MEM_CRC_RES": {
-                    "description": "reg_rtc_mem_crc_res",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "REDUNDANT_ECO_CTRL": {
-              "description": "eco register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "REDUNDANT_ECO_DRIVE": {
-                    "description": "reg_redundant_eco_drive",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "REDUNDANT_ECO_RESULT": {
-                    "description": "reg_redundant_eco_result",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLOCK_GATE": {
-              "description": "clock gating register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "reg_clk_en",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SYSCLK_CONF": {
-              "description": "system clock config register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRE_DIV_CNT": {
-                    "description": "reg_pre_div_cnt",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "SOC_CLK_SEL": {
-                    "description": "reg_soc_clk_sel",
-                    "offset": 10,
-                    "size": 2
-                  },
-                  "CLK_XTAL_FREQ": {
-                    "description": "reg_clk_xtal_freq",
-                    "offset": 12,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "CLK_DIV_EN": {
-                    "description": "reg_clk_div_en",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "MEM_PVT": {
-              "description": "mem pvt register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MEM_PATH_LEN": {
-                    "description": "reg_mem_path_len",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "MEM_ERR_CNT_CLR": {
-                    "description": "reg_mem_err_cnt_clr",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "MONITOR_EN": {
-                    "description": "reg_mem_pvt_monitor_en",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "MEM_TIMING_ERR_CNT": {
-                    "description": "reg_mem_timing_err_cnt",
-                    "offset": 6,
-                    "size": 16,
-                    "access": "read-only"
-                  },
-                  "MEM_VT_SEL": {
-                    "description": "reg_mem_vt_sel",
-                    "offset": 22,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "COMB_PVT_LVT_CONF": {
-              "description": "mem pvt register",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_PATH_LEN_LVT": {
-                    "description": "reg_comb_path_len_lvt",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "COMB_ERR_CNT_CLR_LVT": {
-                    "description": "reg_comb_err_cnt_clr_lvt",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "COMB_PVT_MONITOR_EN_LVT": {
-                    "description": "reg_comb_pvt_monitor_en_lvt",
-                    "offset": 6,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "COMB_PVT_NVT_CONF": {
-              "description": "mem pvt register",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_PATH_LEN_NVT": {
-                    "description": "reg_comb_path_len_nvt",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "COMB_ERR_CNT_CLR_NVT": {
-                    "description": "reg_comb_err_cnt_clr_nvt",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "COMB_PVT_MONITOR_EN_NVT": {
-                    "description": "reg_comb_pvt_monitor_en_nvt",
-                    "offset": 6,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "COMB_PVT_HVT_CONF": {
-              "description": "mem pvt register",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 3,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_PATH_LEN_HVT": {
-                    "description": "reg_comb_path_len_hvt",
-                    "offset": 0,
-                    "size": 5
-                  },
-                  "COMB_ERR_CNT_CLR_HVT": {
-                    "description": "reg_comb_err_cnt_clr_hvt",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "COMB_PVT_MONITOR_EN_HVT": {
-                    "description": "reg_comb_pvt_monitor_en_hvt",
-                    "offset": 6,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_LVT_SITE0": {
-              "description": "mem pvt register",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_LVT_SITE0": {
-                    "description": "reg_comb_timing_err_cnt_lvt_site0",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_NVT_SITE0": {
-              "description": "mem pvt register",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_NVT_SITE0": {
-                    "description": "reg_comb_timing_err_cnt_nvt_site0",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_HVT_SITE0": {
-              "description": "mem pvt register",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_HVT_SITE0": {
-                    "description": "reg_comb_timing_err_cnt_hvt_site0",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_LVT_SITE1": {
-              "description": "mem pvt register",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_LVT_SITE1": {
-                    "description": "reg_comb_timing_err_cnt_lvt_site1",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_NVT_SITE1": {
-              "description": "mem pvt register",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_NVT_SITE1": {
-                    "description": "reg_comb_timing_err_cnt_nvt_site1",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_HVT_SITE1": {
-              "description": "mem pvt register",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_HVT_SITE1": {
-                    "description": "reg_comb_timing_err_cnt_hvt_site1",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_LVT_SITE2": {
-              "description": "mem pvt register",
-              "offset": 132,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_LVT_SITE2": {
-                    "description": "reg_comb_timing_err_cnt_lvt_site2",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_NVT_SITE2": {
-              "description": "mem pvt register",
-              "offset": 136,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_NVT_SITE2": {
-                    "description": "reg_comb_timing_err_cnt_nvt_site2",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_HVT_SITE2": {
-              "description": "mem pvt register",
-              "offset": 140,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_HVT_SITE2": {
-                    "description": "reg_comb_timing_err_cnt_hvt_site2",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_LVT_SITE3": {
-              "description": "mem pvt register",
-              "offset": 144,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_LVT_SITE3": {
-                    "description": "reg_comb_timing_err_cnt_lvt_site3",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_NVT_SITE3": {
-              "description": "mem pvt register",
-              "offset": 148,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_NVT_SITE3": {
-                    "description": "reg_comb_timing_err_cnt_nvt_site3",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMB_PVT_ERR_HVT_SITE3": {
-              "description": "mem pvt register",
-              "offset": 152,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "COMB_TIMING_ERR_CNT_HVT_SITE3": {
-                    "description": "reg_comb_timing_err_cnt_hvt_site3",
-                    "offset": 0,
-                    "size": 16,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "SYSTEM_REG_DATE": {
-              "description": "Version register",
-              "offset": 4092,
-              "size": 32,
-              "reset_value": 33583440,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYSTEM_REG_DATE": {
-                    "description": "reg_system_reg_date",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "SYSTIMER": {
-        "description": "System Timer",
-        "children": {
-          "registers": {
-            "CONF": {
-              "description": "SYSTIMER_CONF.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1174405120,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SYSTIMER_CLK_FO": {
-                    "description": "systimer clock force on",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TARGET2_WORK_EN": {
-                    "description": "target2 work enable",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "TARGET1_WORK_EN": {
-                    "description": "target1 work enable",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TARGET0_WORK_EN": {
-                    "description": "target0 work enable",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "TIMER_UNIT1_CORE1_STALL_EN": {
-                    "description": "If timer unit1 is stalled when core1 stalled",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "TIMER_UNIT1_CORE0_STALL_EN": {
-                    "description": "If timer unit1 is stalled when core0 stalled",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "TIMER_UNIT0_CORE1_STALL_EN": {
-                    "description": "If timer unit0 is stalled when core1 stalled",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "TIMER_UNIT0_CORE0_STALL_EN": {
-                    "description": "If timer unit0 is stalled when core0 stalled",
-                    "offset": 28,
-                    "size": 1
-                  },
-                  "TIMER_UNIT1_WORK_EN": {
-                    "description": "timer unit1 work enable",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "TIMER_UNIT0_WORK_EN": {
-                    "description": "timer unit0 work enable",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "register file clk gating",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "UNIT0_OP": {
-              "description": "SYSTIMER_UNIT0_OP.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_VALUE_VALID": {
-                    "description": "reg_timer_unit0_value_valid",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TIMER_UNIT0_UPDATE": {
-                    "description": "update timer_unit0",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "UNIT1_OP": {
-              "description": "SYSTIMER_UNIT1_OP.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_VALUE_VALID": {
-                    "description": "timer value is sync and valid",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TIMER_UNIT1_UPDATE": {
-                    "description": "update timer unit1",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "UNIT0_LOAD_HI": {
-              "description": "SYSTIMER_UNIT0_LOAD_HI.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_LOAD_HI": {
-                    "description": "timer unit0 load high 32 bit",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "UNIT0_LOAD_LO": {
-              "description": "SYSTIMER_UNIT0_LOAD_LO.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_LOAD_LO": {
-                    "description": "timer unit0 load low 32 bit",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "UNIT1_LOAD_HI": {
-              "description": "SYSTIMER_UNIT1_LOAD_HI.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_LOAD_HI": {
-                    "description": "timer unit1 load high 32 bit",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "UNIT1_LOAD_LO": {
-              "description": "SYSTIMER_UNIT1_LOAD_LO.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_LOAD_LO": {
-                    "description": "timer unit1 load low 32 bit",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TARGET0_HI": {
-              "description": "SYSTIMER_TARGET0_HI.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET0_HI": {
-                    "description": "timer taget0 high 32 bit",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "TARGET0_LO": {
-              "description": "SYSTIMER_TARGET0_LO.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET0_LO": {
-                    "description": "timer taget0 low 32 bit",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TARGET1_HI": {
-              "description": "SYSTIMER_TARGET1_HI.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET1_HI": {
-                    "description": "timer taget1 high 32 bit",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "TARGET1_LO": {
-              "description": "SYSTIMER_TARGET1_LO.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET1_LO": {
-                    "description": "timer taget1 low 32 bit",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TARGET2_HI": {
-              "description": "SYSTIMER_TARGET2_HI.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET2_HI": {
-                    "description": "timer taget2 high 32 bit",
-                    "offset": 0,
-                    "size": 20
-                  }
-                }
-              }
-            },
-            "TARGET2_LO": {
-              "description": "SYSTIMER_TARGET2_LO.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_TARGET2_LO": {
-                    "description": "timer taget2 low 32 bit",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "TARGET0_CONF": {
-              "description": "SYSTIMER_TARGET0_CONF.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET0_PERIOD": {
-                    "description": "target0 period",
-                    "offset": 0,
-                    "size": 26
-                  },
-                  "TARGET0_PERIOD_MODE": {
-                    "description": "Set target0 to period mode",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "TARGET0_TIMER_UNIT_SEL": {
-                    "description": "select which unit to compare",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TARGET1_CONF": {
-              "description": "SYSTIMER_TARGET1_CONF.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET1_PERIOD": {
-                    "description": "target1 period",
-                    "offset": 0,
-                    "size": 26
-                  },
-                  "TARGET1_PERIOD_MODE": {
-                    "description": "Set target1 to period mode",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "TARGET1_TIMER_UNIT_SEL": {
-                    "description": "select which unit to compare",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TARGET2_CONF": {
-              "description": "SYSTIMER_TARGET2_CONF.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET2_PERIOD": {
-                    "description": "target2 period",
-                    "offset": 0,
-                    "size": 26
-                  },
-                  "TARGET2_PERIOD_MODE": {
-                    "description": "Set target2 to period mode",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "TARGET2_TIMER_UNIT_SEL": {
-                    "description": "select which unit to compare",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "UNIT0_VALUE_HI": {
-              "description": "SYSTIMER_UNIT0_VALUE_HI.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_VALUE_HI": {
-                    "description": "timer read value high 32bit",
-                    "offset": 0,
-                    "size": 20,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "UNIT0_VALUE_LO": {
-              "description": "SYSTIMER_UNIT0_VALUE_LO.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_VALUE_LO": {
-                    "description": "timer read value low 32bit",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "UNIT1_VALUE_HI": {
-              "description": "SYSTIMER_UNIT1_VALUE_HI.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_VALUE_HI": {
-                    "description": "timer read value high 32bit",
-                    "offset": 0,
-                    "size": 20,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "UNIT1_VALUE_LO": {
-              "description": "SYSTIMER_UNIT1_VALUE_LO.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_VALUE_LO": {
-                    "description": "timer read value low 32bit",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "COMP0_LOAD": {
-              "description": "SYSTIMER_COMP0_LOAD.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_COMP0_LOAD": {
-                    "description": "timer comp0 load value",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "COMP1_LOAD": {
-              "description": "SYSTIMER_COMP1_LOAD.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_COMP1_LOAD": {
-                    "description": "timer comp1 load value",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "COMP2_LOAD": {
-              "description": "SYSTIMER_COMP2_LOAD.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_COMP2_LOAD": {
-                    "description": "timer comp2 load value",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "UNIT0_LOAD": {
-              "description": "SYSTIMER_UNIT0_LOAD.",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT0_LOAD": {
-                    "description": "timer unit0 load value",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "UNIT1_LOAD": {
-              "description": "SYSTIMER_UNIT1_LOAD.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIMER_UNIT1_LOAD": {
-                    "description": "timer unit1 load value",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "SYSTIMER_INT_ENA.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET0_INT_ENA": {
-                    "description": "interupt0 enable",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TARGET1_INT_ENA": {
-                    "description": "interupt1 enable",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "TARGET2_INT_ENA": {
-                    "description": "interupt2 enable",
-                    "offset": 2,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "SYSTIMER_INT_RAW.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET0_INT_RAW": {
-                    "description": "interupt0 raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TARGET1_INT_RAW": {
-                    "description": "interupt1 raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TARGET2_INT_RAW": {
-                    "description": "interupt2 raw",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "SYSTIMER_INT_CLR.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET0_INT_CLR": {
-                    "description": "interupt0 clear",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TARGET1_INT_CLR": {
-                    "description": "interupt1 clear",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TARGET2_INT_CLR": {
-                    "description": "interupt2 clear",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "SYSTIMER_INT_ST.",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TARGET0_INT_ST": {
-                    "description": "reg_target0_int_st",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TARGET1_INT_ST": {
-                    "description": "reg_target1_int_st",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TARGET2_INT_ST": {
-                    "description": "reg_target2_int_st",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "SYSTIMER_DATE.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 33579377,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "reg_date",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "TIMG0": {
-        "description": "Timer Group",
-        "children": {
-          "registers": {
-            "T0CONFIG": {
-              "description": "TIMG_T0CONFIG_REG.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1610620928,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_USE_XTAL": {
-                    "description": "reg_t0_use_xtal.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "T0_ALARM_EN": {
-                    "description": "reg_t0_alarm_en.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "T0_DIVCNT_RST": {
-                    "description": "reg_t0_divcnt_rst.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "T0_DIVIDER": {
-                    "description": "reg_t0_divider.",
-                    "offset": 13,
-                    "size": 16
-                  },
-                  "T0_AUTORELOAD": {
-                    "description": "reg_t0_autoreload.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "T0_INCREASE": {
-                    "description": "reg_t0_increase.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "T0_EN": {
-                    "description": "reg_t0_en.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "T0LO": {
-              "description": "TIMG_T0LO_REG.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_LO": {
-                    "description": "t0_lo",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "T0HI": {
-              "description": "TIMG_T0HI_REG.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_HI": {
-                    "description": "t0_hi",
-                    "offset": 0,
-                    "size": 22,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "T0UPDATE": {
-              "description": "TIMG_T0UPDATE_REG.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_UPDATE": {
-                    "description": "t0_update",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "T0ALARMLO": {
-              "description": "TIMG_T0ALARMLO_REG.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_ALARM_LO": {
-                    "description": "reg_t0_alarm_lo.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "T0ALARMHI": {
-              "description": "TIMG_T0ALARMHI_REG.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_ALARM_HI": {
-                    "description": "reg_t0_alarm_hi.",
-                    "offset": 0,
-                    "size": 22
-                  }
-                }
-              }
-            },
-            "T0LOADLO": {
-              "description": "TIMG_T0LOADLO_REG.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_LOAD_LO": {
-                    "description": "reg_t0_load_lo.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "T0LOADHI": {
-              "description": "TIMG_T0LOADHI_REG.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_LOAD_HI": {
-                    "description": "reg_t0_load_hi.",
-                    "offset": 0,
-                    "size": 22
-                  }
-                }
-              }
-            },
-            "T0LOAD": {
-              "description": "TIMG_T0LOAD_REG.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_LOAD": {
-                    "description": "t0_load",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "WDTCONFIG0": {
-              "description": "TIMG_WDTCONFIG0_REG.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 311296,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_APPCPU_RESET_EN": {
-                    "description": "reg_wdt_appcpu_reset_en.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "WDT_PROCPU_RESET_EN": {
-                    "description": "reg_wdt_procpu_reset_en.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "WDT_FLASHBOOT_MOD_EN": {
-                    "description": "reg_wdt_flashboot_mod_en.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "WDT_SYS_RESET_LENGTH": {
-                    "description": "reg_wdt_sys_reset_length.",
-                    "offset": 15,
-                    "size": 3
-                  },
-                  "WDT_CPU_RESET_LENGTH": {
-                    "description": "reg_wdt_cpu_reset_length.",
-                    "offset": 18,
-                    "size": 3
-                  },
-                  "WDT_USE_XTAL": {
-                    "description": "reg_wdt_use_xtal.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "WDT_CONF_UPDATE_EN": {
-                    "description": "reg_wdt_conf_update_en.",
-                    "offset": 22,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "WDT_STG3": {
-                    "description": "reg_wdt_stg3.",
-                    "offset": 23,
-                    "size": 2
-                  },
-                  "WDT_STG2": {
-                    "description": "reg_wdt_stg2.",
-                    "offset": 25,
-                    "size": 2
-                  },
-                  "WDT_STG1": {
-                    "description": "reg_wdt_stg1.",
-                    "offset": 27,
-                    "size": 2
-                  },
-                  "WDT_STG0": {
-                    "description": "reg_wdt_stg0.",
-                    "offset": 29,
-                    "size": 2
-                  },
-                  "WDT_EN": {
-                    "description": "reg_wdt_en.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "WDTCONFIG1": {
-              "description": "TIMG_WDTCONFIG1_REG.",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 65536,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_DIVCNT_RST": {
-                    "description": "reg_wdt_divcnt_rst.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "WDT_CLK_PRESCALE": {
-                    "description": "reg_wdt_clk_prescale.",
-                    "offset": 16,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "WDTCONFIG2": {
-              "description": "TIMG_WDTCONFIG2_REG.",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 26000000,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG0_HOLD": {
-                    "description": "reg_wdt_stg0_hold.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG3": {
-              "description": "TIMG_WDTCONFIG3_REG.",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 134217727,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG1_HOLD": {
-                    "description": "reg_wdt_stg1_hold.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG4": {
-              "description": "TIMG_WDTCONFIG4_REG.",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 1048575,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG2_HOLD": {
-                    "description": "reg_wdt_stg2_hold.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTCONFIG5": {
-              "description": "TIMG_WDTCONFIG5_REG.",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 1048575,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_STG3_HOLD": {
-                    "description": "reg_wdt_stg3_hold.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "WDTFEED": {
-              "description": "TIMG_WDTFEED_REG.",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_FEED": {
-                    "description": "wdt_feed",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "WDTWPROTECT": {
-              "description": "TIMG_WDTWPROTECT_REG.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 1356348065,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_WKEY": {
-                    "description": "reg_wdt_wkey.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "RTCCALICFG": {
-              "description": "TIMG_RTCCALICFG_REG.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 77824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CALI_START_CYCLING": {
-                    "description": "reg_rtc_cali_start_cycling.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "RTC_CALI_CLK_SEL": {
-                    "description": "reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k",
-                    "offset": 13,
-                    "size": 2
-                  },
-                  "RTC_CALI_RDY": {
-                    "description": "rtc_cali_rdy",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_CALI_MAX": {
-                    "description": "reg_rtc_cali_max.",
-                    "offset": 16,
-                    "size": 15
-                  },
-                  "RTC_CALI_START": {
-                    "description": "reg_rtc_cali_start.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "RTCCALICFG1": {
-              "description": "TIMG_RTCCALICFG1_REG.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CALI_CYCLING_DATA_VLD": {
-                    "description": "rtc_cali_cycling_data_vld",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_CALI_VALUE": {
-                    "description": "rtc_cali_value",
-                    "offset": 7,
-                    "size": 25,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA_TIMERS": {
-              "description": "INT_ENA_TIMG_REG",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_INT_ENA": {
-                    "description": "t0_int_ena",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "WDT_INT_ENA": {
-                    "description": "wdt_int_ena",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_RAW_TIMERS": {
-              "description": "INT_RAW_TIMG_REG",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_INT_RAW": {
-                    "description": "t0_int_raw",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WDT_INT_RAW": {
-                    "description": "wdt_int_raw",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST_TIMERS": {
-              "description": "INT_ST_TIMG_REG",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_INT_ST": {
-                    "description": "t0_int_st",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WDT_INT_ST": {
-                    "description": "wdt_int_st",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_CLR_TIMERS": {
-              "description": "INT_CLR_TIMG_REG",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "T0_INT_CLR": {
-                    "description": "t0_int_clr",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "WDT_INT_CLR": {
-                    "description": "wdt_int_clr",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "RTCCALICFG2": {
-              "description": "TIMG_RTCCALICFG2_REG.",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 4294967192,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RTC_CALI_TIMEOUT": {
-                    "description": "timeoutindicator",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTC_CALI_TIMEOUT_RST_CNT": {
-                    "description": "reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset",
-                    "offset": 3,
-                    "size": 4
-                  },
-                  "RTC_CALI_TIMEOUT_THRES": {
-                    "description": "reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold",
-                    "offset": 7,
-                    "size": 25
-                  }
-                }
-              }
-            },
-            "NTIMG_DATE": {
-              "description": "TIMG_NTIMG_DATE_REG.",
-              "offset": 248,
-              "size": 32,
-              "reset_value": 33579409,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "NTIMGS_DATE": {
-                    "description": "reg_ntimers_date.",
-                    "offset": 0,
-                    "size": 28
-                  }
-                }
-              }
-            },
-            "REGCLK": {
-              "description": "TIMG_REGCLK_REG.",
-              "offset": 252,
-              "size": 32,
-              "reset_value": 1610612736,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WDT_CLK_IS_ACTIVE": {
-                    "description": "reg_wdt_clk_is_active.",
-                    "offset": 29,
-                    "size": 1
-                  },
-                  "TIMER_CLK_IS_ACTIVE": {
-                    "description": "reg_timer_clk_is_active.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "reg_clk_en.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "XTS_AES": {
-        "description": "XTS-AES-128 Flash Encryption",
-        "children": {
-          "registers": {
-            "PLAIN_MEM": {
-              "description": "The memory that stores plaintext",
-              "offset": 0,
-              "size": 8,
-              "count": 16,
-              "reset_value": 0,
-              "reset_mask": 4294967295
-            },
-            "LINESIZE": {
-              "description": "XTS-AES line-size register",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "LINESIZE": {
-                    "description": "This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DESTINATION": {
-              "description": "XTS-AES destination register",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DESTINATION": {
-                    "description": "This bit stores the destination. 0: flash(default). 1: reserved.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "PHYSICAL_ADDRESS": {
-              "description": "XTS-AES physical address register",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PHYSICAL_ADDRESS": {
-                    "description": "Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            },
-            "TRIGGER": {
-              "description": "XTS-AES trigger register",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TRIGGER": {
-                    "description": "Set this bit to start manual encryption calculation",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "RELEASE": {
-              "description": "XTS-AES release register",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RELEASE": {
-                    "description": "Set this bit to release the manual encrypted result, after that the result will be visible to spi",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DESTROY": {
-              "description": "XTS-AES destroy register",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DESTROY": {
-                    "description": "Set this bit to destroy XTS-AES result.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STATE": {
-              "description": "XTS-AES status register",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "STATE": {
-                    "description": "Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "XTS-AES version control register",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 538969635,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "Those bits stores the version information of XTS-AES.",
-                    "offset": 0,
-                    "size": 30
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "TWAI": {
-        "description": "Two-Wire Automotive Interface",
-        "children": {
-          "registers": {
-            "MODE": {
-              "description": "Mode Register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RESET_MODE": {
-                    "description": "This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "LISTEN_ONLY_MODE": {
-                    "description": "1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SELF_TEST_MODE": {
-                    "description": "1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RX_FILTER_MODE": {
-                    "description": "This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CMD": {
-              "description": "Command Register",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_REQ": {
-                    "description": "Set the bit to 1 to allow the driving nodes start transmission.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "ABORT_TX": {
-                    "description": "Set the bit to 1 to cancel a pending transmission request.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RELEASE_BUF": {
-                    "description": "Set the bit to 1 to release the RX buffer.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CLR_OVERRUN": {
-                    "description": "Set the bit to 1 to clear the data overrun status bit.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SELF_RX_REQ": {
-                    "description": "Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "STATUS": {
-              "description": "Status register",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_BUF_ST": {
-                    "description": "1: The data in the RX buffer is not empty, with at least one received data packet.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVERRUN_ST": {
-                    "description": "1: The RX FIFO is full and data overrun has occurred.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_BUF_ST": {
-                    "description": "1: The TX buffer is empty, the CPU may write a message into it.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_COMPLETE": {
-                    "description": "1: The TWAI controller has successfully received a packet from the bus.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RX_ST": {
-                    "description": "1: The TWAI Controller is receiving a message from the bus.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_ST": {
-                    "description": "1: The TWAI Controller is transmitting a message to the bus.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ERR_ST": {
-                    "description": "1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BUS_OFF_ST": {
-                    "description": "1: In bus-off status, the TWAI Controller is no longer involved in bus activities.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "MISS_ST": {
-                    "description": "This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "Interrupt Register",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_INT_ST": {
-                    "description": "Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_INT_ST": {
-                    "description": "Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ERR_WARN_INT_ST": {
-                    "description": "Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OVERRUN_INT_ST": {
-                    "description": "Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ERR_PASSIVE_INT_ST": {
-                    "description": "Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ARB_LOST_INT_ST": {
-                    "description": "Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BUS_ERR_INT_ST": {
-                    "description": "Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "Interrupt Enable Register",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_INT_ENA": {
-                    "description": "Set this bit to 1 to enable receive interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_INT_ENA": {
-                    "description": "Set this bit to 1 to enable transmit interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "ERR_WARN_INT_ENA": {
-                    "description": "Set this bit to 1 to enable error warning interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "OVERRUN_INT_ENA": {
-                    "description": "Set this bit to 1 to enable data overrun interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "ERR_PASSIVE_INT_ENA": {
-                    "description": "Set this bit to 1 to enable error passive interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "ARB_LOST_INT_ENA": {
-                    "description": "Set this bit to 1 to enable arbitration lost interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "BUS_ERR_INT_ENA": {
-                    "description": "Set this bit to 1 to enable error interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "BUS_TIMING_0": {
-              "description": "Bus Timing Register 0",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "BAUD_PRESC": {
-                    "description": "Baud Rate Prescaler, determines the frequency dividing ratio.",
-                    "offset": 0,
-                    "size": 13
-                  },
-                  "SYNC_JUMP_WIDTH": {
-                    "description": "Synchronization Jump Width (SJW), 1 \\verb+~+ 14 Tq wide.",
-                    "offset": 14,
-                    "size": 2
-                  }
-                }
-              }
-            },
-            "BUS_TIMING_1": {
-              "description": "Bus Timing Register 1",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TIME_SEG1": {
-                    "description": "The width of PBS1.",
-                    "offset": 0,
-                    "size": 4
-                  },
-                  "TIME_SEG2": {
-                    "description": "The width of PBS2.",
-                    "offset": 4,
-                    "size": 3
-                  },
-                  "TIME_SAMP": {
-                    "description": "The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ARB_LOST_CAP": {
-              "description": "Arbitration Lost Capture Register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ARB_LOST_CAP": {
-                    "description": "This register contains information about the bit position of lost arbitration.",
-                    "offset": 0,
-                    "size": 5,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ERR_CODE_CAP": {
-              "description": "Error Code Capture Register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ECC_SEGMENT": {
-                    "description": "This register contains information about the location of errors, see Table 181 for details.",
-                    "offset": 0,
-                    "size": 5,
-                    "access": "read-only"
-                  },
-                  "ECC_DIRECTION": {
-                    "description": "This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "ECC_TYPE": {
-                    "description": "This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error",
-                    "offset": 6,
-                    "size": 2,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ERR_WARNING_LIMIT": {
-              "description": "Error Warning Limit Register",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 96,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ERR_WARNING_LIMIT": {
-                    "description": "Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "RX_ERR_CNT": {
-              "description": "Receive Error Counter Register",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_ERR_CNT": {
-                    "description": "The RX error counter register, reflects value changes under reception status.",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "TX_ERR_CNT": {
-              "description": "Transmit Error Counter Register",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_ERR_CNT": {
-                    "description": "The TX error counter register, reflects value changes under transmission status.",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "DATA_0": {
-              "description": "Data register 0",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_0": {
-                    "description": "In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_1": {
-              "description": "Data register 1",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_1": {
-                    "description": "In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_2": {
-              "description": "Data register 2",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_2": {
-                    "description": "In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_3": {
-              "description": "Data register 3",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_3": {
-                    "description": "In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_4": {
-              "description": "Data register 4",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_4": {
-                    "description": "In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_5": {
-              "description": "Data register 5",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_5": {
-                    "description": "In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_6": {
-              "description": "Data register 6",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_6": {
-                    "description": "In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_7": {
-              "description": "Data register 7",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_7": {
-                    "description": "In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_8": {
-              "description": "Data register 8",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_8": {
-                    "description": "Stored the 8th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_9": {
-              "description": "Data register 9",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_9": {
-                    "description": "Stored the 9th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_10": {
-              "description": "Data register 10",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_10": {
-                    "description": "Stored the 10th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_11": {
-              "description": "Data register 11",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_11": {
-                    "description": "Stored the 11th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "DATA_12": {
-              "description": "Data register 12",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BYTE_12": {
-                    "description": "Stored the 12th byte information of the data to be transmitted under operating mode.",
-                    "offset": 0,
-                    "size": 8,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "RX_MESSAGE_CNT": {
-              "description": "Receive Message Counter Register",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_MESSAGE_COUNTER": {
-                    "description": "This register reflects the number of messages available within the RX FIFO.",
-                    "offset": 0,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLOCK_DIVIDER": {
-              "description": "Clock Divider register",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CD": {
-                    "description": "These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CLOCK_OFF": {
-                    "description": "This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "UART0": {
-        "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
-        "children": {
-          "registers": {
-            "FIFO": {
-              "description": "FIFO data register",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_RD_BYTE": {
-                    "description": "UART 0 accesses FIFO via this register.",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "Raw interrupt status",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_FULL_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_EMPTY_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PARITY_ERR_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a parity error in the data.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FRM_ERR_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a data frame error .",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_OVF_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DSR_CHG_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CTS_CHG_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BRK_DET_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_TOUT_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SW_XON_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SW_XOFF_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "GLITCH_DET_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_BRK_DONE_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when transmitter completes  sending  NULL characters, after all data in Tx-FIFO are sent.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_BRK_IDLE_DONE_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the  last data.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_DONE_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_PARITY_ERR_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_FRM_ERR_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_CLASH_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "AT_CMD_CHAR_DET_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WAKEUP_INT_RAW": {
-                    "description": "This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "Masked interrupt status",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_FULL_INT_ST": {
-                    "description": "This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_EMPTY_INT_ST": {
-                    "description": "This is the status bit for  txfifo_empty_int_raw  when txfifo_empty_int_ena is set to 1.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PARITY_ERR_INT_ST": {
-                    "description": "This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "FRM_ERR_INT_ST": {
-                    "description": "This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_OVF_INT_ST": {
-                    "description": "This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "DSR_CHG_INT_ST": {
-                    "description": "This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CTS_CHG_INT_ST": {
-                    "description": "This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "BRK_DET_INT_ST": {
-                    "description": "This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXFIFO_TOUT_INT_ST": {
-                    "description": "This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SW_XON_INT_ST": {
-                    "description": "This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SW_XOFF_INT_ST": {
-                    "description": "This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "GLITCH_DET_INT_ST": {
-                    "description": "This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_BRK_DONE_INT_ST": {
-                    "description": "This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_BRK_IDLE_DONE_INT_ST": {
-                    "description": "This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_DONE_INT_ST": {
-                    "description": "This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_PARITY_ERR_INT_ST": {
-                    "description": "This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_FRM_ERR_INT_ST": {
-                    "description": "This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RS485_CLASH_INT_ST": {
-                    "description": "This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "AT_CMD_CHAR_DET_INT_ST": {
-                    "description": "This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "WAKEUP_INT_ST": {
-                    "description": "This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "Interrupt enable bits",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_FULL_INT_ENA": {
-                    "description": "This is the enable bit for rxfifo_full_int_st register.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TXFIFO_EMPTY_INT_ENA": {
-                    "description": "This is the enable bit for txfifo_empty_int_st register.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "PARITY_ERR_INT_ENA": {
-                    "description": "This is the enable bit for parity_err_int_st register.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "FRM_ERR_INT_ENA": {
-                    "description": "This is the enable bit for frm_err_int_st register.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RXFIFO_OVF_INT_ENA": {
-                    "description": "This is the enable bit for rxfifo_ovf_int_st register.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "DSR_CHG_INT_ENA": {
-                    "description": "This is the enable bit for dsr_chg_int_st register.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CTS_CHG_INT_ENA": {
-                    "description": "This is the enable bit for cts_chg_int_st register.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "BRK_DET_INT_ENA": {
-                    "description": "This is the enable bit for brk_det_int_st register.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "RXFIFO_TOUT_INT_ENA": {
-                    "description": "This is the enable bit for rxfifo_tout_int_st register.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "SW_XON_INT_ENA": {
-                    "description": "This is the enable bit for sw_xon_int_st register.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "SW_XOFF_INT_ENA": {
-                    "description": "This is the enable bit for sw_xoff_int_st register.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "GLITCH_DET_INT_ENA": {
-                    "description": "This is the enable bit for glitch_det_int_st register.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "TX_BRK_DONE_INT_ENA": {
-                    "description": "This is the enable bit for tx_brk_done_int_st register.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "TX_BRK_IDLE_DONE_INT_ENA": {
-                    "description": "This is the enable bit for tx_brk_idle_done_int_st register.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "TX_DONE_INT_ENA": {
-                    "description": "This is the enable bit for tx_done_int_st register.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "RS485_PARITY_ERR_INT_ENA": {
-                    "description": "This is the enable bit for rs485_parity_err_int_st register.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "RS485_FRM_ERR_INT_ENA": {
-                    "description": "This is the enable bit for rs485_parity_err_int_st register.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "RS485_CLASH_INT_ENA": {
-                    "description": "This is the enable bit for rs485_clash_int_st register.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "AT_CMD_CHAR_DET_INT_ENA": {
-                    "description": "This is the enable bit for at_cmd_char_det_int_st register.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "WAKEUP_INT_ENA": {
-                    "description": "This is the enable bit for uart_wakeup_int_st register.",
-                    "offset": 19,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "Interrupt clear bits",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_FULL_INT_CLR": {
-                    "description": "Set this bit to clear the rxfifo_full_int_raw interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TXFIFO_EMPTY_INT_CLR": {
-                    "description": "Set this bit to clear txfifo_empty_int_raw interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PARITY_ERR_INT_CLR": {
-                    "description": "Set this bit to clear parity_err_int_raw interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "FRM_ERR_INT_CLR": {
-                    "description": "Set this bit to clear frm_err_int_raw interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RXFIFO_OVF_INT_CLR": {
-                    "description": "Set this bit to clear rxfifo_ovf_int_raw interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "DSR_CHG_INT_CLR": {
-                    "description": "Set this bit to clear the dsr_chg_int_raw interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CTS_CHG_INT_CLR": {
-                    "description": "Set this bit to clear the cts_chg_int_raw interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "BRK_DET_INT_CLR": {
-                    "description": "Set this bit to clear the brk_det_int_raw interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RXFIFO_TOUT_INT_CLR": {
-                    "description": "Set this bit to clear the rxfifo_tout_int_raw interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SW_XON_INT_CLR": {
-                    "description": "Set this bit to clear the sw_xon_int_raw interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SW_XOFF_INT_CLR": {
-                    "description": "Set this bit to clear the sw_xoff_int_raw interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "GLITCH_DET_INT_CLR": {
-                    "description": "Set this bit to clear the glitch_det_int_raw interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_BRK_DONE_INT_CLR": {
-                    "description": "Set this bit to clear the tx_brk_done_int_raw interrupt..",
-                    "offset": 12,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_BRK_IDLE_DONE_INT_CLR": {
-                    "description": "Set this bit to clear the tx_brk_idle_done_int_raw interrupt.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_DONE_INT_CLR": {
-                    "description": "Set this bit to clear the tx_done_int_raw interrupt.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RS485_PARITY_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the rs485_parity_err_int_raw interrupt.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RS485_FRM_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the rs485_frm_err_int_raw interrupt.",
-                    "offset": 16,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RS485_CLASH_INT_CLR": {
-                    "description": "Set this bit to clear the rs485_clash_int_raw interrupt.",
-                    "offset": 17,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "AT_CMD_CHAR_DET_INT_CLR": {
-                    "description": "Set this bit to clear the at_cmd_char_det_int_raw interrupt.",
-                    "offset": 18,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "WAKEUP_INT_CLR": {
-                    "description": "Set this bit to clear the uart_wakeup_int_raw interrupt.",
-                    "offset": 19,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CLKDIV": {
-              "description": "Clock divider configuration",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 694,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLKDIV": {
-                    "description": "The integral part of the frequency divider factor.",
-                    "offset": 0,
-                    "size": 12
-                  },
-                  "FRAG": {
-                    "description": "The decimal part of the frequency divider factor.",
-                    "offset": 20,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "RX_FILT": {
-              "description": "Rx Filter configuration",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "GLITCH_FILT": {
-                    "description": "when input pulse width is lower than this value, the pulse is ignored.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "GLITCH_FILT_EN": {
-                    "description": "Set this bit to enable Rx signal filter.",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "STATUS": {
-              "description": "UART status register",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 3758145536,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_CNT": {
-                    "description": "Stores the byte number of valid data in Rx-FIFO.",
-                    "offset": 0,
-                    "size": 10,
-                    "access": "read-only"
-                  },
-                  "DSRN": {
-                    "description": "The register represent the level value of the internal uart dsr signal.",
-                    "offset": 13,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CTSN": {
-                    "description": "This register represent the level value of the internal uart cts signal.",
-                    "offset": 14,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RXD": {
-                    "description": "This register represent the  level value of the internal uart rxd signal.",
-                    "offset": 15,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXFIFO_CNT": {
-                    "description": "Stores the byte number of data in Tx-FIFO.",
-                    "offset": 16,
-                    "size": 10,
-                    "access": "read-only"
-                  },
-                  "DTRN": {
-                    "description": "This bit represents the level of the internal uart dtr signal.",
-                    "offset": 29,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RTSN": {
-                    "description": "This bit represents the level of the internal uart rts signal.",
-                    "offset": 30,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TXD": {
-                    "description": "This bit represents the  level of the internal uart txd signal.",
-                    "offset": 31,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CONF0": {
-              "description": "a",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 268435484,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PARITY": {
-                    "description": "This register is used to configure the parity check mode.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "PARITY_EN": {
-                    "description": "Set this bit to enable uart parity check.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "BIT_NUM": {
-                    "description": "This register is used to set the length of data.",
-                    "offset": 2,
-                    "size": 2
-                  },
-                  "STOP_BIT_NUM": {
-                    "description": "This register is used to set the length of  stop bit.",
-                    "offset": 4,
-                    "size": 2
-                  },
-                  "SW_RTS": {
-                    "description": "This register is used to configure the software rts signal which is used in software flow control.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "SW_DTR": {
-                    "description": "This register is used to configure the software dtr signal which is used in software flow control.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "TXD_BRK": {
-                    "description": "Set this bit to enbale transmitter to  send NULL when the process of sending data is done.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "IRDA_DPLX": {
-                    "description": "Set this bit to enable IrDA loopback mode.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "IRDA_TX_EN": {
-                    "description": "This is the start enable bit for IrDA transmitter.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "IRDA_WCTL": {
-                    "description": "1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "IRDA_TX_INV": {
-                    "description": "Set this bit to invert the level of  IrDA transmitter.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "IRDA_RX_INV": {
-                    "description": "Set this bit to invert the level of IrDA receiver.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "LOOPBACK": {
-                    "description": "Set this bit to enable uart loopback test mode.",
-                    "offset": 14,
-                    "size": 1
-                  },
-                  "TX_FLOW_EN": {
-                    "description": "Set this bit to enable flow control function for transmitter.",
-                    "offset": 15,
-                    "size": 1
-                  },
-                  "IRDA_EN": {
-                    "description": "Set this bit to enable IrDA protocol.",
-                    "offset": 16,
-                    "size": 1
-                  },
-                  "RXFIFO_RST": {
-                    "description": "Set this bit to reset the uart receive-FIFO.",
-                    "offset": 17,
-                    "size": 1
-                  },
-                  "TXFIFO_RST": {
-                    "description": "Set this bit to reset the uart transmit-FIFO.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "RXD_INV": {
-                    "description": "Set this bit to inverse the level value of uart rxd signal.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "CTS_INV": {
-                    "description": "Set this bit to inverse the level value of uart cts signal.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "DSR_INV": {
-                    "description": "Set this bit to inverse the level value of uart dsr signal.",
-                    "offset": 21,
-                    "size": 1
-                  },
-                  "TXD_INV": {
-                    "description": "Set this bit to inverse the level value of uart txd signal.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "RTS_INV": {
-                    "description": "Set this bit to inverse the level value of uart rts signal.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "DTR_INV": {
-                    "description": "Set this bit to inverse the level value of uart dtr signal.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "ERR_WR_MASK": {
-                    "description": "1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the  received data is wrong.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "AUTOBAUD_EN": {
-                    "description": "This is the enable bit for detecting baudrate.",
-                    "offset": 27,
-                    "size": 1
-                  },
-                  "MEM_CLK_EN": {
-                    "description": "UART memory clock gate enable signal.",
-                    "offset": 28,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "CONF1": {
-              "description": "Configuration register 1",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 49248,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXFIFO_FULL_THRHD": {
-                    "description": "It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "TXFIFO_EMPTY_THRHD": {
-                    "description": "It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.",
-                    "offset": 9,
-                    "size": 9
-                  },
-                  "DIS_RX_DAT_OVF": {
-                    "description": "Disable UART Rx data overflow detect.",
-                    "offset": 18,
-                    "size": 1
-                  },
-                  "RX_TOUT_FLOW_DIS": {
-                    "description": "Set this bit to stop accumulating idle_cnt when hardware flow control works.",
-                    "offset": 19,
-                    "size": 1
-                  },
-                  "RX_FLOW_EN": {
-                    "description": "This is the flow enable bit for UART receiver.",
-                    "offset": 20,
-                    "size": 1
-                  },
-                  "RX_TOUT_EN": {
-                    "description": "This is the enble bit for uart receiver's timeout function.",
-                    "offset": 21,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "LOWPULSE": {
-              "description": "Autobaud minimum low pulse duration register",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MIN_CNT": {
-                    "description": "This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "HIGHPULSE": {
-              "description": "Autobaud minimum high pulse duration register",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "MIN_CNT": {
-                    "description": "This register stores  the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "RXD_CNT": {
-              "description": "Autobaud edge change count register",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RXD_EDGE_CNT": {
-                    "description": "This register stores the count of rxd edge change. It is used in baud rate-detect process.",
-                    "offset": 0,
-                    "size": 10,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "FLOW_CONF": {
-              "description": "Software flow-control configuration",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SW_FLOW_CON_EN": {
-                    "description": "Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "XONOFF_DEL": {
-                    "description": "Set this bit to remove flow control char from the received data.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "FORCE_XON": {
-                    "description": "Set this bit to enable the transmitter to go on sending data.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "FORCE_XOFF": {
-                    "description": "Set this bit to stop the  transmitter from sending data.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SEND_XON": {
-                    "description": "Set this bit to send Xon char. It is cleared by hardware automatically.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "SEND_XOFF": {
-                    "description": "Set this bit to send Xoff char. It is cleared by hardware automatically.",
-                    "offset": 5,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "SLEEP_CONF": {
-              "description": "Sleep-mode configuration",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 240,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ACTIVE_THRESHOLD": {
-                    "description": "The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.",
-                    "offset": 0,
-                    "size": 10
-                  }
-                }
-              }
-            },
-            "SWFC_CONF0": {
-              "description": "Software flow-control character configuration",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 9952,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XOFF_THRESHOLD": {
-                    "description": "When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "XOFF_CHAR": {
-                    "description": "This register stores the Xoff flow control char.",
-                    "offset": 9,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "SWFC_CONF1": {
-              "description": "Software flow-control character configuration",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 8704,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "XON_THRESHOLD": {
-                    "description": "When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.",
-                    "offset": 0,
-                    "size": 9
-                  },
-                  "XON_CHAR": {
-                    "description": "This register stores the Xon flow control char.",
-                    "offset": 9,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "TXBRK_CONF": {
-              "description": "Tx Break character configuration",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 10,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_BRK_NUM": {
-                    "description": "This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "IDLE_CONF": {
-              "description": "Frame-end idle configuration",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 262400,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_IDLE_THRHD": {
-                    "description": "It will produce frame end signal when receiver takes more time to receive one byte data than this register value.",
-                    "offset": 0,
-                    "size": 10
-                  },
-                  "TX_IDLE_NUM": {
-                    "description": "This register is used to configure the duration time between transfers.",
-                    "offset": 10,
-                    "size": 10
-                  }
-                }
-              }
-            },
-            "RS485_CONF": {
-              "description": "RS485 mode configuration",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RS485_EN": {
-                    "description": "Set this bit to choose the rs485 mode.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "DL0_EN": {
-                    "description": "Set this bit to delay the stop bit by 1 bit.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "DL1_EN": {
-                    "description": "Set this bit to delay the stop bit by 1 bit.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "RS485TX_RX_EN": {
-                    "description": "Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RS485RXBY_TX_EN": {
-                    "description": "1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RS485_RX_DLY_NUM": {
-                    "description": "This register is used to delay the receiver's internal data signal.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "RS485_TX_DLY_NUM": {
-                    "description": "This register is used to delay the transmitter's internal data signal.",
-                    "offset": 6,
-                    "size": 4
-                  }
-                }
-              }
-            },
-            "AT_CMD_PRECNT": {
-              "description": "Pre-sequence timing configuration",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 2305,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PRE_IDLE_NUM": {
-                    "description": "This register is used to configure the idle duration time before the first at_cmd is received by receiver.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "AT_CMD_POSTCNT": {
-              "description": "Post-sequence timing configuration",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 2305,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "POST_IDLE_NUM": {
-                    "description": "This register is used to configure the duration time between the last at_cmd and the next data.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "AT_CMD_GAPTOUT": {
-              "description": "Timeout configuration",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 11,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_GAP_TOUT": {
-                    "description": "This register is used to configure the duration time between the at_cmd chars.",
-                    "offset": 0,
-                    "size": 16
-                  }
-                }
-              }
-            },
-            "AT_CMD_CHAR": {
-              "description": "AT escape sequence detection configuration",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 811,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "AT_CMD_CHAR": {
-                    "description": "This register is used to configure the content of at_cmd char.",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "CHAR_NUM": {
-                    "description": "This register is used to configure the num of continuous at_cmd chars received by receiver.",
-                    "offset": 8,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "MEM_CONF": {
-              "description": "UART threshold and allocation configuration",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 655378,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_SIZE": {
-                    "description": "This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.",
-                    "offset": 1,
-                    "size": 3
-                  },
-                  "TX_SIZE": {
-                    "description": "This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.",
-                    "offset": 4,
-                    "size": 3
-                  },
-                  "RX_FLOW_THRHD": {
-                    "description": "This register is used to configure the maximum amount of data that can be received  when hardware flow control works.",
-                    "offset": 7,
-                    "size": 9
-                  },
-                  "RX_TOUT_THRHD": {
-                    "description": "This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.",
-                    "offset": 16,
-                    "size": 10
-                  },
-                  "MEM_FORCE_PD": {
-                    "description": "Set this bit to force power down UART memory.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "MEM_FORCE_PU": {
-                    "description": "Set this bit to force power up UART memory.",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "MEM_TX_STATUS": {
-              "description": "Tx-FIFO write and read offset address.",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_TX_WADDR": {
-                    "description": "This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.",
-                    "offset": 0,
-                    "size": 10,
-                    "access": "read-only"
-                  },
-                  "TX_RADDR": {
-                    "description": "This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.",
-                    "offset": 11,
-                    "size": 10,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "MEM_RX_STATUS": {
-              "description": "Rx-FIFO write and read offset address.",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 524544,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "APB_RX_RADDR": {
-                    "description": "This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.",
-                    "offset": 0,
-                    "size": 10,
-                    "access": "read-only"
-                  },
-                  "RX_WADDR": {
-                    "description": "This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.",
-                    "offset": 11,
-                    "size": 10,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "FSM_STATUS": {
-              "description": "UART transmit and receive status.",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ST_URX_OUT": {
-                    "description": "This is the status register of receiver.",
-                    "offset": 0,
-                    "size": 4,
-                    "access": "read-only"
-                  },
-                  "ST_UTX_OUT": {
-                    "description": "This is the status register of transmitter.",
-                    "offset": 4,
-                    "size": 4,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "POSPULSE": {
-              "description": "Autobaud high pulse register",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "POSEDGE_MIN_CNT": {
-                    "description": "This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "NEGPULSE": {
-              "description": "Autobaud low pulse register",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 4095,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "NEGEDGE_MIN_CNT": {
-                    "description": "This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.",
-                    "offset": 0,
-                    "size": 12,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "CLK_CONF": {
-              "description": "UART core clock configuration",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 57675776,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SCLK_DIV_B": {
-                    "description": "The  denominator of the frequency divider factor.",
-                    "offset": 0,
-                    "size": 6
-                  },
-                  "SCLK_DIV_A": {
-                    "description": "The numerator of the frequency divider factor.",
-                    "offset": 6,
-                    "size": 6
-                  },
-                  "SCLK_DIV_NUM": {
-                    "description": "The integral part of the frequency divider factor.",
-                    "offset": 12,
-                    "size": 8
-                  },
-                  "SCLK_SEL": {
-                    "description": "UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.",
-                    "offset": 20,
-                    "size": 2
-                  },
-                  "SCLK_EN": {
-                    "description": "Set this bit to enable UART Tx/Rx clock.",
-                    "offset": 22,
-                    "size": 1
-                  },
-                  "RST_CORE": {
-                    "description": "Write 1 then write 0 to this bit, reset UART Tx/Rx.",
-                    "offset": 23,
-                    "size": 1
-                  },
-                  "TX_SCLK_EN": {
-                    "description": "Set this bit to enable UART Tx clock.",
-                    "offset": 24,
-                    "size": 1
-                  },
-                  "RX_SCLK_EN": {
-                    "description": "Set this bit to enable UART Rx clock.",
-                    "offset": 25,
-                    "size": 1
-                  },
-                  "TX_RST_CORE": {
-                    "description": "Write 1 then write 0 to this bit, reset UART Tx.",
-                    "offset": 26,
-                    "size": 1
-                  },
-                  "RX_RST_CORE": {
-                    "description": "Write 1 then write 0 to this bit, reset UART Rx.",
-                    "offset": 27,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "UART Version register",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 33587824,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "This is the version register.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ID": {
-              "description": "UART ID register",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 1073743104,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ID": {
-                    "description": "This register is used to configure the uart_id.",
-                    "offset": 0,
-                    "size": 30
-                  },
-                  "HIGH_SPEED": {
-                    "description": "This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.",
-                    "offset": 30,
-                    "size": 1
-                  },
-                  "REG_UPDATE": {
-                    "description": "Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.",
-                    "offset": 31,
-                    "size": 1
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "USB_DEVICE": {
-        "description": "Full-speed USB Serial/JTAG Controller",
-        "children": {
-          "registers": {
-            "EP1": {
-              "description": "USB_DEVICE_EP1_REG.",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RDWR_BYTE": {
-                    "description": "Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.",
-                    "offset": 0,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "EP1_CONF": {
-              "description": "USB_DEVICE_EP1_CONF_REG.",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "WR_DONE": {
-                    "description": "Set this bit to indicate writing byte data to UART Tx FIFO is done.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SERIAL_IN_EP_DATA_FREE": {
-                    "description": "1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SERIAL_OUT_EP_DATA_AVAIL": {
-                    "description": "1'b1: Indicate there is data in UART Rx FIFO.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "USB_DEVICE_INT_RAW_REG.",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "JTAG_IN_FLUSH_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SOF_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when SOF frame is received.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SERIAL_OUT_RECV_PKT_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SERIAL_IN_EMPTY_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PID_ERR_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when pid error is detected.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CRC5_ERR_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when CRC5 error is detected.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CRC16_ERR_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when CRC16 error is detected.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "STUFF_ERR_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when stuff error is detected.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_TOKEN_REC_IN_EP1_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "USB_BUS_RESET_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when usb bus reset is detected.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EP1_ZERO_PAYLOAD_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EP2_ZERO_PAYLOAD_INT_RAW": {
-                    "description": "The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "USB_DEVICE_INT_ST_REG.",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "JTAG_IN_FLUSH_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SOF_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SERIAL_OUT_RECV_PKT_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SERIAL_IN_EMPTY_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "PID_ERR_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CRC5_ERR_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "CRC16_ERR_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "STUFF_ERR_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_TOKEN_REC_IN_EP1_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "USB_BUS_RESET_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EP1_ZERO_PAYLOAD_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EP2_ZERO_PAYLOAD_INT_ST": {
-                    "description": "The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "USB_DEVICE_INT_ENA_REG.",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "JTAG_IN_FLUSH_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "SOF_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "SERIAL_OUT_RECV_PKT_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "SERIAL_IN_EMPTY_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "PID_ERR_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "CRC5_ERR_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "CRC16_ERR_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "STUFF_ERR_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "IN_TOKEN_REC_IN_EP1_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "USB_BUS_RESET_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "OUT_EP1_ZERO_PAYLOAD_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "OUT_EP2_ZERO_PAYLOAD_INT_ENA": {
-                    "description": "The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 11,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "USB_DEVICE_INT_CLR_REG.",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "JTAG_IN_FLUSH_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SOF_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SERIAL_OUT_RECV_PKT_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SERIAL_IN_EMPTY_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "PID_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CRC5_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "CRC16_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "STUFF_ERR_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "IN_TOKEN_REC_IN_EP1_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "USB_BUS_RESET_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.",
-                    "offset": 9,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_EP1_ZERO_PAYLOAD_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 10,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUT_EP2_ZERO_PAYLOAD_INT_CLR": {
-                    "description": "Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.",
-                    "offset": 11,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CONF0": {
-              "description": "USB_DEVICE_CONF0_REG.",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 16896,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PHY_SEL": {
-                    "description": "Select internal/external PHY",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "EXCHG_PINS_OVERRIDE": {
-                    "description": "Enable software control USB D+ D- exchange",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "EXCHG_PINS": {
-                    "description": "USB D+ D- exchange",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "VREFH": {
-                    "description": "Control single-end input high threshold,1.76V to 2V, step 80mV",
-                    "offset": 3,
-                    "size": 2
-                  },
-                  "VREFL": {
-                    "description": "Control single-end input low threshold,0.8V to 1.04V, step 80mV",
-                    "offset": 5,
-                    "size": 2
-                  },
-                  "VREF_OVERRIDE": {
-                    "description": "Enable software control input  threshold",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "PAD_PULL_OVERRIDE": {
-                    "description": "Enable software control USB D+ D- pullup pulldown",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "DP_PULLUP": {
-                    "description": "Control USB D+ pull up.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "DP_PULLDOWN": {
-                    "description": "Control USB D+ pull down.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "DM_PULLUP": {
-                    "description": "Control USB D- pull up.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "DM_PULLDOWN": {
-                    "description": "Control USB D- pull down.",
-                    "offset": 12,
-                    "size": 1
-                  },
-                  "PULLUP_VALUE": {
-                    "description": "Control pull up value.",
-                    "offset": 13,
-                    "size": 1
-                  },
-                  "USB_PAD_ENABLE": {
-                    "description": "Enable USB pad function.",
-                    "offset": 14,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "TEST": {
-              "description": "USB_DEVICE_TEST_REG.",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENABLE": {
-                    "description": "Enable test of the USB pad",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "USB_OE": {
-                    "description": "USB pad oen in test",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "TX_DP": {
-                    "description": "USB D+ tx value in test",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "TX_DM": {
-                    "description": "USB D- tx value in test",
-                    "offset": 3,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "JFIFO_ST": {
-              "description": "USB_DEVICE_JFIFO_ST_REG.",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 68,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_FIFO_CNT": {
-                    "description": "JTAT in fifo counter.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_FIFO_EMPTY": {
-                    "description": "1: JTAG in fifo is empty.",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_FIFO_FULL": {
-                    "description": "1: JTAG in fifo is full.",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_FIFO_CNT": {
-                    "description": "JTAT out fifo counter.",
-                    "offset": 4,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_FIFO_EMPTY": {
-                    "description": "1: JTAG out fifo is empty.",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_FIFO_FULL": {
-                    "description": "1: JTAG out fifo is full.",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "IN_FIFO_RESET": {
-                    "description": "Write 1 to reset JTAG in fifo.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "OUT_FIFO_RESET": {
-                    "description": "Write 1 to reset JTAG out fifo.",
-                    "offset": 9,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "FRAM_NUM": {
-              "description": "USB_DEVICE_FRAM_NUM_REG.",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SOF_FRAME_INDEX": {
-                    "description": "Frame index of received SOF frame.",
-                    "offset": 0,
-                    "size": 11,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_EP0_ST": {
-              "description": "USB_DEVICE_IN_EP0_ST_REG.",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_EP0_STATE": {
-                    "description": "State of IN Endpoint 0.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_EP0_WR_ADDR": {
-                    "description": "Write data address of IN endpoint 0.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "IN_EP0_RD_ADDR": {
-                    "description": "Read data address of IN endpoint 0.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_EP1_ST": {
-              "description": "USB_DEVICE_IN_EP1_ST_REG.",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_EP1_STATE": {
-                    "description": "State of IN Endpoint 1.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_EP1_WR_ADDR": {
-                    "description": "Write data address of IN endpoint 1.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "IN_EP1_RD_ADDR": {
-                    "description": "Read data address of IN endpoint 1.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_EP2_ST": {
-              "description": "USB_DEVICE_IN_EP2_ST_REG.",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_EP2_STATE": {
-                    "description": "State of IN Endpoint 2.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_EP2_WR_ADDR": {
-                    "description": "Write data address of IN endpoint 2.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "IN_EP2_RD_ADDR": {
-                    "description": "Read data address of IN endpoint 2.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "IN_EP3_ST": {
-              "description": "USB_DEVICE_IN_EP3_ST_REG.",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 1,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "IN_EP3_STATE": {
-                    "description": "State of IN Endpoint 3.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "IN_EP3_WR_ADDR": {
-                    "description": "Write data address of IN endpoint 3.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "IN_EP3_RD_ADDR": {
-                    "description": "Read data address of IN endpoint 3.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EP0_ST": {
-              "description": "USB_DEVICE_OUT_EP0_ST_REG.",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EP0_STATE": {
-                    "description": "State of OUT Endpoint 0.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_EP0_WR_ADDR": {
-                    "description": "Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "OUT_EP0_RD_ADDR": {
-                    "description": "Read data address of OUT endpoint 0.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EP1_ST": {
-              "description": "USB_DEVICE_OUT_EP1_ST_REG.",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EP1_STATE": {
-                    "description": "State of OUT Endpoint 1.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_EP1_WR_ADDR": {
-                    "description": "Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "OUT_EP1_RD_ADDR": {
-                    "description": "Read data address of OUT endpoint 1.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "OUT_EP1_REC_DATA_CNT": {
-                    "description": "Data count in OUT endpoint 1 when one packet is received.",
-                    "offset": 16,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "OUT_EP2_ST": {
-              "description": "USB_DEVICE_OUT_EP2_ST_REG.",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "OUT_EP2_STATE": {
-                    "description": "State of OUT Endpoint 2.",
-                    "offset": 0,
-                    "size": 2,
-                    "access": "read-only"
-                  },
-                  "OUT_EP2_WR_ADDR": {
-                    "description": "Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.",
-                    "offset": 2,
-                    "size": 7,
-                    "access": "read-only"
-                  },
-                  "OUT_EP2_RD_ADDR": {
-                    "description": "Read data address of OUT endpoint 2.",
-                    "offset": 9,
-                    "size": 7,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "MISC_CONF": {
-              "description": "USB_DEVICE_MISC_CONF_REG.",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CLK_EN": {
-                    "description": "1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.",
-                    "offset": 0,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "MEM_CONF": {
-              "description": "USB_DEVICE_MEM_CONF_REG.",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 2,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "USB_MEM_PD": {
-                    "description": "1: power down usb memory.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "USB_MEM_CLK_EN": {
-                    "description": "1: Force clock on for usb memory.",
-                    "offset": 1,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "USB_DEVICE_DATE_REG.",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 33583872,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "register version.",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            }
-          }
-        }
-      },
-      "UHCI0": {
-        "description": "Universal Host Controller Interface",
-        "children": {
-          "registers": {
-            "CONF0": {
-              "description": "a",
-              "offset": 0,
-              "size": 32,
-              "reset_value": 1760,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_RST": {
-                    "description": "Write 1, then write 0 to this bit to reset decode state machine.",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "RX_RST": {
-                    "description": "Write 1, then write 0 to this bit to reset encode state machine.",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "UART0_CE": {
-                    "description": "Set this bit to link up HCI and UART0.",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "UART1_CE": {
-                    "description": "Set this bit to link up HCI and UART1.",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SEPER_EN": {
-                    "description": "Set this bit to separate the data frame using a special char.",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "HEAD_EN": {
-                    "description": "Set this bit to encode the data packet with a formatting header.",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "CRC_REC_EN": {
-                    "description": "Set this bit to enable UHCI to receive the 16 bit CRC.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "UART_IDLE_EOF_EN": {
-                    "description": "If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.",
-                    "offset": 8,
-                    "size": 1
-                  },
-                  "LEN_EOF_EN": {
-                    "description": "If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.",
-                    "offset": 9,
-                    "size": 1
-                  },
-                  "ENCODE_CRC_EN": {
-                    "description": "Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.",
-                    "offset": 10,
-                    "size": 1
-                  },
-                  "CLK_EN": {
-                    "description": "1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "UART_RX_BRK_EOF_EN": {
-                    "description": "If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.",
-                    "offset": 12,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_RAW": {
-              "description": "a",
-              "offset": 4,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_START_INT_RAW": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_START_INT_RAW": {
-                    "description": "a",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RX_HUNG_INT_RAW": {
-                    "description": "a",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_HUNG_INT_RAW": {
-                    "description": "a",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SEND_S_REG_Q_INT_RAW": {
-                    "description": "a",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SEND_A_REG_Q_INT_RAW": {
-                    "description": "a",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUT_EOF_INT_RAW": {
-                    "description": "This is the interrupt raw bit. Triggered when there are some errors in EOF in the",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APP_CTRL0_INT_RAW": {
-                    "description": "Soft control int raw bit.",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "APP_CTRL1_INT_RAW": {
-                    "description": "Soft control int raw bit.",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_ST": {
-              "description": "a",
-              "offset": 8,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_START_INT_ST": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_START_INT_ST": {
-                    "description": "a",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "RX_HUNG_INT_ST": {
-                    "description": "a",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "TX_HUNG_INT_ST": {
-                    "description": "a",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SEND_S_REG_Q_INT_ST": {
-                    "description": "a",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "SEND_A_REG_Q_INT_ST": {
-                    "description": "a",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "OUTLINK_EOF_ERR_INT_ST": {
-                    "description": "a",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APP_CTRL0_INT_ST": {
-                    "description": "a",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "read-only"
-                  },
-                  "APP_CTRL1_INT_ST": {
-                    "description": "a",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "INT_ENA": {
-              "description": "a",
-              "offset": 12,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_START_INT_ENA": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_START_INT_ENA": {
-                    "description": "a",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "RX_HUNG_INT_ENA": {
-                    "description": "a",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "TX_HUNG_INT_ENA": {
-                    "description": "a",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "SEND_S_REG_Q_INT_ENA": {
-                    "description": "a",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "SEND_A_REG_Q_INT_ENA": {
-                    "description": "a",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "OUTLINK_EOF_ERR_INT_ENA": {
-                    "description": "a",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "APP_CTRL0_INT_ENA": {
-                    "description": "a",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "APP_CTRL1_INT_ENA": {
-                    "description": "a",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "INT_CLR": {
-              "description": "a",
-              "offset": 16,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_START_INT_CLR": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_START_INT_CLR": {
-                    "description": "a",
-                    "offset": 1,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "RX_HUNG_INT_CLR": {
-                    "description": "a",
-                    "offset": 2,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "TX_HUNG_INT_CLR": {
-                    "description": "a",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SEND_S_REG_Q_INT_CLR": {
-                    "description": "a",
-                    "offset": 4,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "SEND_A_REG_Q_INT_CLR": {
-                    "description": "a",
-                    "offset": 5,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "OUTLINK_EOF_ERR_INT_CLR": {
-                    "description": "a",
-                    "offset": 6,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APP_CTRL0_INT_CLR": {
-                    "description": "a",
-                    "offset": 7,
-                    "size": 1,
-                    "access": "write-only"
-                  },
-                  "APP_CTRL1_INT_CLR": {
-                    "description": "a",
-                    "offset": 8,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "CONF1": {
-              "description": "a",
-              "offset": 20,
-              "size": 32,
-              "reset_value": 51,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "CHECK_SUM_EN": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "CHECK_SEQ_EN": {
-                    "description": "a",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "CRC_DISABLE": {
-                    "description": "a",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "SAVE_HEAD": {
-                    "description": "a",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "TX_CHECK_SUM_RE": {
-                    "description": "a",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "TX_ACK_NUM_RE": {
-                    "description": "a",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "WAIT_SW_START": {
-                    "description": "a",
-                    "offset": 7,
-                    "size": 1
-                  },
-                  "SW_START": {
-                    "description": "a",
-                    "offset": 8,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "STATE0": {
-              "description": "a",
-              "offset": 24,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_ERR_CAUSE": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "read-only"
-                  },
-                  "DECODE_STATE": {
-                    "description": "a",
-                    "offset": 3,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "STATE1": {
-              "description": "a",
-              "offset": 28,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ENCODE_STATE": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 3,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "ESCAPE_CONF": {
-              "description": "a",
-              "offset": 32,
-              "size": 32,
-              "reset_value": 51,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TX_C0_ESC_EN": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 1
-                  },
-                  "TX_DB_ESC_EN": {
-                    "description": "a",
-                    "offset": 1,
-                    "size": 1
-                  },
-                  "TX_11_ESC_EN": {
-                    "description": "a",
-                    "offset": 2,
-                    "size": 1
-                  },
-                  "TX_13_ESC_EN": {
-                    "description": "a",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "RX_C0_ESC_EN": {
-                    "description": "a",
-                    "offset": 4,
-                    "size": 1
-                  },
-                  "RX_DB_ESC_EN": {
-                    "description": "a",
-                    "offset": 5,
-                    "size": 1
-                  },
-                  "RX_11_ESC_EN": {
-                    "description": "a",
-                    "offset": 6,
-                    "size": 1
-                  },
-                  "RX_13_ESC_EN": {
-                    "description": "a",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "HUNG_CONF": {
-              "description": "a",
-              "offset": 36,
-              "size": 32,
-              "reset_value": 8456208,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "TXFIFO_TIMEOUT": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "TXFIFO_TIMEOUT_SHIFT": {
-                    "description": "a",
-                    "offset": 8,
-                    "size": 3
-                  },
-                  "TXFIFO_TIMEOUT_ENA": {
-                    "description": "a",
-                    "offset": 11,
-                    "size": 1
-                  },
-                  "RXFIFO_TIMEOUT": {
-                    "description": "a",
-                    "offset": 12,
-                    "size": 8
-                  },
-                  "RXFIFO_TIMEOUT_SHIFT": {
-                    "description": "a",
-                    "offset": 20,
-                    "size": 3
-                  },
-                  "RXFIFO_TIMEOUT_ENA": {
-                    "description": "a",
-                    "offset": 23,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "ACK_NUM": {
-              "description": "a",
-              "offset": 40,
-              "size": 32,
-              "reset_value": 8,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ACK_NUM": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "LOAD": {
-                    "description": "a",
-                    "offset": 3,
-                    "size": 1,
-                    "access": "write-only"
-                  }
-                }
-              }
-            },
-            "RX_HEAD": {
-              "description": "a",
-              "offset": 44,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "RX_HEAD": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32,
-                    "access": "read-only"
-                  }
-                }
-              }
-            },
-            "QUICK_SENT": {
-              "description": "a",
-              "offset": 48,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SINGLE_SEND_NUM": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 3
-                  },
-                  "SINGLE_SEND_EN": {
-                    "description": "a",
-                    "offset": 3,
-                    "size": 1
-                  },
-                  "ALWAYS_SEND_NUM": {
-                    "description": "a",
-                    "offset": 4,
-                    "size": 3
-                  },
-                  "ALWAYS_SEND_EN": {
-                    "description": "a",
-                    "offset": 7,
-                    "size": 1
-                  }
-                }
-              }
-            },
-            "REG_Q0_WORD0": {
-              "description": "a",
-              "offset": 52,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q0_WORD0": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q0_WORD1": {
-              "description": "a",
-              "offset": 56,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q0_WORD1": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q1_WORD0": {
-              "description": "a",
-              "offset": 60,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q1_WORD0": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q1_WORD1": {
-              "description": "a",
-              "offset": 64,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q1_WORD1": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q2_WORD0": {
-              "description": "a",
-              "offset": 68,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q2_WORD0": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q2_WORD1": {
-              "description": "a",
-              "offset": 72,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q2_WORD1": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q3_WORD0": {
-              "description": "a",
-              "offset": 76,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q3_WORD0": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q3_WORD1": {
-              "description": "a",
-              "offset": 80,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q3_WORD1": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q4_WORD0": {
-              "description": "a",
-              "offset": 84,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q4_WORD0": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q4_WORD1": {
-              "description": "a",
-              "offset": 88,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q4_WORD1": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q5_WORD0": {
-              "description": "a",
-              "offset": 92,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q5_WORD0": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q5_WORD1": {
-              "description": "a",
-              "offset": 96,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q5_WORD1": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q6_WORD0": {
-              "description": "a",
-              "offset": 100,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q6_WORD0": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "REG_Q6_WORD1": {
-              "description": "a",
-              "offset": 104,
-              "size": 32,
-              "reset_value": 0,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEND_Q6_WORD1": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            },
-            "ESC_CONF0": {
-              "description": "a",
-              "offset": 108,
-              "size": 32,
-              "reset_value": 14474176,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "SEPER_CHAR": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "SEPER_ESC_CHAR0": {
-                    "description": "a",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "SEPER_ESC_CHAR1": {
-                    "description": "a",
-                    "offset": 16,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "ESC_CONF1": {
-              "description": "a",
-              "offset": 112,
-              "size": 32,
-              "reset_value": 14539739,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ESC_SEQ0": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "ESC_SEQ0_CHAR0": {
-                    "description": "a",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "ESC_SEQ0_CHAR1": {
-                    "description": "a",
-                    "offset": 16,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "ESC_CONF2": {
-              "description": "a",
-              "offset": 116,
-              "size": 32,
-              "reset_value": 14605073,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ESC_SEQ1": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "ESC_SEQ1_CHAR0": {
-                    "description": "a",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "ESC_SEQ1_CHAR1": {
-                    "description": "a",
-                    "offset": 16,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "ESC_CONF3": {
-              "description": "a",
-              "offset": 120,
-              "size": 32,
-              "reset_value": 14670611,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "ESC_SEQ2": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 8
-                  },
-                  "ESC_SEQ2_CHAR0": {
-                    "description": "a",
-                    "offset": 8,
-                    "size": 8
-                  },
-                  "ESC_SEQ2_CHAR1": {
-                    "description": "a",
-                    "offset": 16,
-                    "size": 8
-                  }
-                }
-              }
-            },
-            "PKT_THRES": {
-              "description": "a",
-              "offset": 124,
-              "size": 32,
-              "reset_value": 128,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "PKT_THRS": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 13
-                  }
-                }
-              }
-            },
-            "DATE": {
-              "description": "a",
-              "offset": 128,
-              "size": 32,
-              "reset_value": 33583472,
-              "reset_mask": 4294967295,
-              "children": {
-                "fields": {
-                  "DATE": {
-                    "description": "a",
-                    "offset": 0,
-                    "size": 32
-                  }
-                }
-              }
-            }
-          }
-        }
-      }
-    }
-  },
-  "devices": {
-    "ESP32-C3": {
-      "arch": "unknown",
-      "description": "32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)",
-      "properties": {
-        "cpu.mpuPresent": "false",
-        "cpu.nvicPrioBits": "4",
-        "cpu.vendorSystickConfig": "false",
-        "cpu.revision": "r0p0",
-        "cpu.endian": "little",
-        "license": "\n    Copyright 2022 Espressif Systems (Shanghai) PTE LTD\n\n    Licensed under the Apache License, Version 2.0 (the \"License\");\n    you may not use this file except in compliance with the License.\n    You may obtain a copy of the License at\n\n        http://www.apache.org/licenses/LICENSE-2.0\n\n    Unless required by applicable law or agreed to in writing, software\n    distributed under the License is distributed on an \"AS IS\" BASIS,\n    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n    See the License for the specific language governing permissions and\n    limitations under the License.\n",
-        "cpu.name": "RV32IMC",
-        "cpu.fpuPresent": "false"
-      },
-      "children": {
-        "interrupts": {
-          "AES": {
-            "index": 48
-          },
-          "APB_ADC": {
-            "index": 43
-          },
-          "ASSIST_DEBUG": {
-            "index": 54
-          },
-          "DMA_CH0": {
-            "index": 44
-          },
-          "DMA_CH1": {
-            "index": 45
-          },
-          "DMA_CH2": {
-            "index": 46
-          },
-          "EFUSE": {
-            "index": 24
-          },
-          "GPIO": {
-            "index": 16
-          },
-          "GPIO_NMI": {
-            "index": 17
-          },
-          "I2C_EXT0": {
-            "index": 29
-          },
-          "I2S": {
-            "index": 20
-          },
-          "LEDC": {
-            "index": 23
-          },
-          "RMT": {
-            "index": 28
-          },
-          "RSA": {
-            "index": 47
-          },
-          "RTC_CORE": {
-            "index": 27
-          },
-          "SHA": {
-            "index": 49
-          },
-          "SPI2": {
-            "index": 19
-          },
-          "SYSTIMER_TARGET0": {
-            "index": 37
-          },
-          "SYSTIMER_TARGET1": {
-            "index": 38
-          },
-          "SYSTIMER_TARGET2": {
-            "index": 39
-          },
-          "TG0_T0_LEVEL": {
-            "index": 32
-          },
-          "TG0_WDT_LEVEL": {
-            "index": 33
-          },
-          "TG1_T0_LEVEL": {
-            "index": 34
-          },
-          "TG1_WDT_LEVEL": {
-            "index": 35
-          },
-          "TWAI": {
-            "index": 25
-          },
-          "UART0": {
-            "index": 21
-          },
-          "UART1": {
-            "index": 22
-          },
-          "UHCI0": {
-            "index": 15
-          },
-          "USB_SERIAL_JTAG": {
-            "index": 26
-          }
-        },
-        "peripheral_instances": {
-          "AES": {
-            "description": "AES (Advanced Encryption Standard) Accelerator",
-            "offset": 1610850304,
-            "type": "types.peripherals.AES"
-          },
-          "APB_CTRL": {
-            "description": "Advanced Peripheral Bus Controller",
-            "offset": 1610768384,
-            "type": "types.peripherals.APB_CTRL"
-          },
-          "APB_SARADC": {
-            "description": "Successive Approximation Register Analog to Digital Converter",
-            "offset": 1610874880,
-            "type": "types.peripherals.APB_SARADC"
-          },
-          "ASSIST_DEBUG": {
-            "description": "Debug Assist",
-            "offset": 1611456512,
-            "type": "types.peripherals.ASSIST_DEBUG"
-          },
-          "DMA": {
-            "description": "DMA (Direct Memory Access) Controller",
-            "offset": 1610870784,
-            "type": "types.peripherals.DMA"
-          },
-          "DS": {
-            "description": "Digital Signature",
-            "offset": 1610862592,
-            "type": "types.peripherals.DS"
-          },
-          "EFUSE": {
-            "description": "eFuse Controller",
-            "offset": 1610647552,
-            "type": "types.peripherals.EFUSE"
-          },
-          "EXTMEM": {
-            "description": "External Memory",
-            "offset": 1611415552,
-            "type": "types.peripherals.EXTMEM"
-          },
-          "GPIO": {
-            "description": "General Purpose Input/Output",
-            "offset": 1610629120,
-            "type": "types.peripherals.GPIO"
-          },
-          "GPIOSD": {
-            "description": "Sigma-Delta Modulation",
-            "offset": 1610632960,
-            "type": "types.peripherals.GPIOSD"
-          },
-          "HMAC": {
-            "description": "HMAC (Hash-based Message Authentication Code) Accelerator",
-            "offset": 1610866688,
-            "type": "types.peripherals.HMAC"
-          },
-          "I2C0": {
-            "description": "I2C (Inter-Integrated Circuit) Controller",
-            "offset": 1610690560,
-            "type": "types.peripherals.I2C0"
-          },
-          "I2S": {
-            "description": "I2S (Inter-IC Sound) Controller",
-            "offset": 1610797056,
-            "type": "types.peripherals.I2S"
-          },
-          "INTERRUPT_CORE0": {
-            "description": "Interrupt Core",
-            "offset": 1611407360,
-            "type": "types.peripherals.INTERRUPT_CORE0"
-          },
-          "IO_MUX": {
-            "description": "Input/Output Multiplexer",
-            "offset": 1610649600,
-            "type": "types.peripherals.IO_MUX"
-          },
-          "LEDC": {
-            "description": "LED Control PWM (Pulse Width Modulation)",
-            "offset": 1610715136,
-            "type": "types.peripherals.LEDC"
-          },
-          "RMT": {
-            "description": "Remote Control Peripheral",
-            "offset": 1610702848,
-            "type": "types.peripherals.RMT"
-          },
-          "RNG": {
-            "description": "Hardware random number generator",
-            "offset": 1610768384,
-            "type": "types.peripherals.RNG"
-          },
-          "RSA": {
-            "description": "RSA (Rivest Shamir Adleman) Accelerator",
-            "offset": 1610858496,
-            "type": "types.peripherals.RSA"
-          },
-          "RTC_CNTL": {
-            "description": "Real-Time Clock Control",
-            "offset": 1610645504,
-            "type": "types.peripherals.RTC_CNTL"
-          },
-          "SENSITIVE": {
-            "description": "Sensitive",
-            "offset": 1611403264,
-            "type": "types.peripherals.SENSITIVE"
-          },
-          "SHA": {
-            "description": "SHA (Secure Hash Algorithm) Accelerator",
-            "offset": 1610854400,
-            "type": "types.peripherals.SHA"
-          },
-          "SPI0": {
-            "description": "SPI (Serial Peripheral Interface) Controller",
-            "offset": 1610625024,
-            "type": "types.peripherals.SPI0"
-          },
-          "SPI1": {
-            "description": "SPI (Serial Peripheral Interface) Controller",
-            "offset": 1610620928,
-            "type": "types.peripherals.SPI1"
-          },
-          "SPI2": {
-            "description": "SPI (Serial Peripheral Interface) Controller",
-            "offset": 1610760192,
-            "type": "types.peripherals.SPI2"
-          },
-          "SYSTEM": {
-            "description": "System",
-            "offset": 1611399168,
-            "type": "types.peripherals.SYSTEM"
-          },
-          "SYSTIMER": {
-            "description": "System Timer",
-            "offset": 1610756096,
-            "type": "types.peripherals.SYSTIMER"
-          },
-          "TIMG0": {
-            "description": "Timer Group",
-            "offset": 1610739712,
-            "type": "types.peripherals.TIMG0"
-          },
-          "TIMG1": {
-            "description": "Timer Group",
-            "offset": 1610743808,
-            "type": "types.peripherals.TIMG0"
-          },
-          "TWAI": {
-            "description": "Two-Wire Automotive Interface",
-            "offset": 1610788864,
-            "type": "types.peripherals.TWAI"
-          },
-          "UART0": {
-            "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
-            "offset": 1610612736,
-            "type": "types.peripherals.UART0"
-          },
-          "UART1": {
-            "description": "UART (Universal Asynchronous Receiver-Transmitter) Controller",
-            "offset": 1610678272,
-            "type": "types.peripherals.UART0"
-          },
-          "UHCI0": {
-            "description": "Universal Host Controller Interface",
-            "offset": 1610694656,
-            "type": "types.peripherals.UHCI0"
-          },
-          "UHCI1": {
-            "description": "Universal Host Controller Interface",
-            "offset": 1610661888,
-            "type": "types.peripherals.UHCI0"
-          },
-          "USB_DEVICE": {
-            "description": "Full-speed USB Serial/JTAG Controller",
-            "offset": 1610887168,
-            "type": "types.peripherals.USB_DEVICE"
-          },
-          "XTS_AES": {
-            "description": "XTS-AES-128 Flash Encryption",
-            "offset": 1611448320,
-            "type": "types.peripherals.XTS_AES"
-          }
-        }
-      }
-    }
-  }
-}
\ No newline at end of file
diff --git a/src/chips/ESP32_C3.zig b/src/chips/ESP32_C3.zig
deleted file mode 100644
index 8a632a07d..000000000
--- a/src/chips/ESP32_C3.zig
+++ /dev/null
@@ -1,12378 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    ///  32-bit RISC-V MCU & 2.4 GHz Wi-Fi & Bluetooth 5 (LE)
-    pub const @"ESP32-C3" = struct {
-        pub const properties = struct {
-            pub const @"cpu.mpuPresent" = "false";
-            pub const @"cpu.nvicPrioBits" = "4";
-            pub const @"cpu.vendorSystickConfig" = "false";
-            pub const @"cpu.revision" = "r0p0";
-            pub const @"cpu.endian" = "little";
-            pub const license =
-                \\
-                \\    Copyright 2022 Espressif Systems (Shanghai) PTE LTD
-                \\
-                \\    Licensed under the Apache License, Version 2.0 (the "License");
-                \\    you may not use this file except in compliance with the License.
-                \\    You may obtain a copy of the License at
-                \\
-                \\        http://www.apache.org/licenses/LICENSE-2.0
-                \\
-                \\    Unless required by applicable law or agreed to in writing, software
-                \\    distributed under the License is distributed on an "AS IS" BASIS,
-                \\    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-                \\    See the License for the specific language governing permissions and
-                \\    limitations under the License.
-                \\
-            ;
-            pub const @"cpu.name" = "RV32IMC";
-            pub const @"cpu.fpuPresent" = "false";
-        };
-
-        pub const peripherals = struct {
-            ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
-            pub const UART0 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x60000000));
-            ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI1 = @as(*volatile types.peripherals.SPI1, @ptrFromInt(0x60002000));
-            ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI0 = @as(*volatile types.peripherals.SPI0, @ptrFromInt(0x60003000));
-            ///  General Purpose Input/Output
-            pub const GPIO = @as(*volatile types.peripherals.GPIO, @ptrFromInt(0x60004000));
-            ///  Sigma-Delta Modulation
-            pub const GPIOSD = @as(*volatile types.peripherals.GPIOSD, @ptrFromInt(0x60004f00));
-            ///  Real-Time Clock Control
-            pub const RTC_CNTL = @as(*volatile types.peripherals.RTC_CNTL, @ptrFromInt(0x60008000));
-            ///  eFuse Controller
-            pub const EFUSE = @as(*volatile types.peripherals.EFUSE, @ptrFromInt(0x60008800));
-            ///  Input/Output Multiplexer
-            pub const IO_MUX = @as(*volatile types.peripherals.IO_MUX, @ptrFromInt(0x60009000));
-            ///  Universal Host Controller Interface
-            pub const UHCI1 = @as(*volatile types.peripherals.UHCI0, @ptrFromInt(0x6000c000));
-            ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
-            pub const UART1 = @as(*volatile types.peripherals.UART0, @ptrFromInt(0x60010000));
-            ///  I2C (Inter-Integrated Circuit) Controller
-            pub const I2C0 = @as(*volatile types.peripherals.I2C0, @ptrFromInt(0x60013000));
-            ///  Universal Host Controller Interface
-            pub const UHCI0 = @as(*volatile types.peripherals.UHCI0, @ptrFromInt(0x60014000));
-            ///  Remote Control Peripheral
-            pub const RMT = @as(*volatile types.peripherals.RMT, @ptrFromInt(0x60016000));
-            ///  LED Control PWM (Pulse Width Modulation)
-            pub const LEDC = @as(*volatile types.peripherals.LEDC, @ptrFromInt(0x60019000));
-            ///  Timer Group
-            pub const TIMG0 = @as(*volatile types.peripherals.TIMG0, @ptrFromInt(0x6001f000));
-            ///  Timer Group
-            pub const TIMG1 = @as(*volatile types.peripherals.TIMG0, @ptrFromInt(0x60020000));
-            ///  System Timer
-            pub const SYSTIMER = @as(*volatile types.peripherals.SYSTIMER, @ptrFromInt(0x60023000));
-            ///  SPI (Serial Peripheral Interface) Controller
-            pub const SPI2 = @as(*volatile types.peripherals.SPI2, @ptrFromInt(0x60024000));
-            ///  Advanced Peripheral Bus Controller
-            pub const APB_CTRL = @as(*volatile types.peripherals.APB_CTRL, @ptrFromInt(0x60026000));
-            ///  Hardware random number generator
-            pub const RNG = @as(*volatile types.peripherals.RNG, @ptrFromInt(0x60026000));
-            ///  Two-Wire Automotive Interface
-            pub const TWAI = @as(*volatile types.peripherals.TWAI, @ptrFromInt(0x6002b000));
-            ///  I2S (Inter-IC Sound) Controller
-            pub const I2S = @as(*volatile types.peripherals.I2S, @ptrFromInt(0x6002d000));
-            ///  AES (Advanced Encryption Standard) Accelerator
-            pub const AES = @as(*volatile types.peripherals.AES, @ptrFromInt(0x6003a000));
-            ///  SHA (Secure Hash Algorithm) Accelerator
-            pub const SHA = @as(*volatile types.peripherals.SHA, @ptrFromInt(0x6003b000));
-            ///  RSA (Rivest Shamir Adleman) Accelerator
-            pub const RSA = @as(*volatile types.peripherals.RSA, @ptrFromInt(0x6003c000));
-            ///  Digital Signature
-            pub const DS = @as(*volatile types.peripherals.DS, @ptrFromInt(0x6003d000));
-            ///  HMAC (Hash-based Message Authentication Code) Accelerator
-            pub const HMAC = @as(*volatile types.peripherals.HMAC, @ptrFromInt(0x6003e000));
-            ///  DMA (Direct Memory Access) Controller
-            pub const DMA = @as(*volatile types.peripherals.DMA, @ptrFromInt(0x6003f000));
-            ///  Successive Approximation Register Analog to Digital Converter
-            pub const APB_SARADC = @as(*volatile types.peripherals.APB_SARADC, @ptrFromInt(0x60040000));
-            ///  Full-speed USB Serial/JTAG Controller
-            pub const USB_DEVICE = @as(*volatile types.peripherals.USB_DEVICE, @ptrFromInt(0x60043000));
-            ///  System
-            pub const SYSTEM = @as(*volatile types.peripherals.SYSTEM, @ptrFromInt(0x600c0000));
-            ///  Sensitive
-            pub const SENSITIVE = @as(*volatile types.peripherals.SENSITIVE, @ptrFromInt(0x600c1000));
-            ///  Interrupt Core
-            pub const INTERRUPT_CORE0 = @as(*volatile types.peripherals.INTERRUPT_CORE0, @ptrFromInt(0x600c2000));
-            ///  External Memory
-            pub const EXTMEM = @as(*volatile types.peripherals.EXTMEM, @ptrFromInt(0x600c4000));
-            ///  XTS-AES-128 Flash Encryption
-            pub const XTS_AES = @as(*volatile types.peripherals.XTS_AES, @ptrFromInt(0x600cc000));
-            ///  Debug Assist
-            pub const ASSIST_DEBUG = @as(*volatile types.peripherals.ASSIST_DEBUG, @ptrFromInt(0x600ce000));
-        };
-    };
-};
-
-pub const types = struct {
-    pub const peripherals = struct {
-        ///  AES (Advanced Encryption Standard) Accelerator
-        pub const AES = extern struct {
-            ///  Key material key_0 configure register
-            KEY_0: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_0 that is a part of key material.
-                KEY_0: u32,
-            }),
-            ///  Key material key_1 configure register
-            KEY_1: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_1 that is a part of key material.
-                KEY_1: u32,
-            }),
-            ///  Key material key_2 configure register
-            KEY_2: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_2 that is a part of key material.
-                KEY_2: u32,
-            }),
-            ///  Key material key_3 configure register
-            KEY_3: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_3 that is a part of key material.
-                KEY_3: u32,
-            }),
-            ///  Key material key_4 configure register
-            KEY_4: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_4 that is a part of key material.
-                KEY_4: u32,
-            }),
-            ///  Key material key_5 configure register
-            KEY_5: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_5 that is a part of key material.
-                KEY_5: u32,
-            }),
-            ///  Key material key_6 configure register
-            KEY_6: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_6 that is a part of key material.
-                KEY_6: u32,
-            }),
-            ///  Key material key_7 configure register
-            KEY_7: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores key_7 that is a part of key material.
-                KEY_7: u32,
-            }),
-            ///  source text material text_in_0 configure register
-            TEXT_IN_0: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_in_0 that is a part of source text material.
-                TEXT_IN_0: u32,
-            }),
-            ///  source text material text_in_1 configure register
-            TEXT_IN_1: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_in_1 that is a part of source text material.
-                TEXT_IN_1: u32,
-            }),
-            ///  source text material text_in_2 configure register
-            TEXT_IN_2: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_in_2 that is a part of source text material.
-                TEXT_IN_2: u32,
-            }),
-            ///  source text material text_in_3 configure register
-            TEXT_IN_3: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_in_3 that is a part of source text material.
-                TEXT_IN_3: u32,
-            }),
-            ///  result text material text_out_0 configure register
-            TEXT_OUT_0: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_out_0 that is a part of result text material.
-                TEXT_OUT_0: u32,
-            }),
-            ///  result text material text_out_1 configure register
-            TEXT_OUT_1: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_out_1 that is a part of result text material.
-                TEXT_OUT_1: u32,
-            }),
-            ///  result text material text_out_2 configure register
-            TEXT_OUT_2: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_out_2 that is a part of result text material.
-                TEXT_OUT_2: u32,
-            }),
-            ///  result text material text_out_3 configure register
-            TEXT_OUT_3: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores text_out_3 that is a part of result text material.
-                TEXT_OUT_3: u32,
-            }),
-            ///  AES Mode register
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  This bits decides which one operation mode will be used. 3'd0: AES-EN-128, 3'd1: AES-EN-192, 3'd2: AES-EN-256, 3'd4: AES-DE-128, 3'd5: AES-DE-192, 3'd6: AES-DE-256.
-                MODE: u3,
-                padding: u29,
-            }),
-            ///  AES Endian configure register
-            ENDIAN: mmio.Mmio(packed struct(u32) {
-                ///  endian. [1:0] key endian, [3:2] text_in endian or in_stream endian, [5:4] text_out endian or out_stream endian
-                ENDIAN: u6,
-                padding: u26,
-            }),
-            ///  AES trigger register
-            TRIGGER: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to start AES calculation.
-                TRIGGER: u1,
-                padding: u31,
-            }),
-            ///  AES state register
-            STATE: mmio.Mmio(packed struct(u32) {
-                ///  Those bits shows AES status. For typical AES, 0: idle, 1: busy. For DMA-AES, 0: idle, 1: busy, 2: calculation_done.
-                STATE: u2,
-                padding: u30,
-            }),
-            ///  The memory that stores initialization vector
-            IV_MEM: [16]u8,
-            ///  The memory that stores GCM hash subkey
-            H_MEM: [16]u8,
-            ///  The memory that stores J0
-            J0_MEM: [16]u8,
-            ///  The memory that stores T0
-            T0_MEM: [16]u8,
-            ///  DMA-AES working mode register
-            DMA_ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  1'b0: typical AES working mode, 1'b1: DMA-AES working mode.
-                DMA_ENABLE: u1,
-                padding: u31,
-            }),
-            ///  AES cipher block mode register
-            BLOCK_MODE: mmio.Mmio(packed struct(u32) {
-                ///  Those bits decides which block mode will be used. 0x0: ECB, 0x1: CBC, 0x2: OFB, 0x3: CTR, 0x4: CFB-8, 0x5: CFB-128, 0x6: GCM, 0x7: reserved.
-                BLOCK_MODE: u3,
-                padding: u29,
-            }),
-            ///  AES block number register
-            BLOCK_NUM: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores the number of Plaintext/ciphertext block.
-                BLOCK_NUM: u32,
-            }),
-            ///  Standard incrementing function configure register
-            INC_SEL: mmio.Mmio(packed struct(u32) {
-                ///  This bit decides the standard incrementing function. 0: INC32. 1: INC128.
-                INC_SEL: u1,
-                padding: u31,
-            }),
-            ///  Additional Authential Data block number register
-            AAD_BLOCK_NUM: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores the number of AAD block.
-                AAD_BLOCK_NUM: u32,
-            }),
-            ///  AES remainder bit number register
-            REMAINDER_BIT_NUM: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores the number of remainder bit.
-                REMAINDER_BIT_NUM: u7,
-                padding: u25,
-            }),
-            ///  AES continue register
-            CONTINUE: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to continue GCM operation.
-                CONTINUE: u1,
-                padding: u31,
-            }),
-            ///  AES Interrupt clear register
-            INT_CLEAR: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the AES interrupt.
-                INT_CLEAR: u1,
-                padding: u31,
-            }),
-            ///  AES Interrupt enable register
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to enable interrupt that occurs when DMA-AES calculation is done.
-                INT_ENA: u1,
-                padding: u31,
-            }),
-            ///  AES version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  This bits stores the version information of AES.
-                DATE: u30,
-                padding: u2,
-            }),
-            ///  AES-DMA exit config
-            DMA_EXIT: mmio.Mmio(packed struct(u32) {
-                ///  Set this register to leave calculation done stage. Recommend to use it after software finishes reading DMA's output buffer.
-                DMA_EXIT: u1,
-                padding: u31,
-            }),
-        };
-
-        ///  Advanced Peripheral Bus Controller
-        pub const APB_CTRL = extern struct {
-            ///  APB_CTRL_SYSCLK_CONF_REG
-            SYSCLK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_pre_div_cnt
-                PRE_DIV_CNT: u10,
-                ///  reg_clk_320m_en
-                CLK_320M_EN: u1,
-                ///  reg_clk_en
-                CLK_EN: u1,
-                ///  reg_rst_tick_cnt
-                RST_TICK_CNT: u1,
-                padding: u19,
-            }),
-            ///  APB_CTRL_TICK_CONF_REG
-            TICK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_xtal_tick_num
-                XTAL_TICK_NUM: u8,
-                ///  reg_ck8m_tick_num
-                CK8M_TICK_NUM: u8,
-                ///  reg_tick_enable
-                TICK_ENABLE: u1,
-                padding: u15,
-            }),
-            ///  APB_CTRL_CLK_OUT_EN_REG
-            CLK_OUT_EN: mmio.Mmio(packed struct(u32) {
-                ///  reg_clk20_oen
-                CLK20_OEN: u1,
-                ///  reg_clk22_oen
-                CLK22_OEN: u1,
-                ///  reg_clk44_oen
-                CLK44_OEN: u1,
-                ///  reg_clk_bb_oen
-                CLK_BB_OEN: u1,
-                ///  reg_clk80_oen
-                CLK80_OEN: u1,
-                ///  reg_clk160_oen
-                CLK160_OEN: u1,
-                ///  reg_clk_320m_oen
-                CLK_320M_OEN: u1,
-                ///  reg_clk_adc_inf_oen
-                CLK_ADC_INF_OEN: u1,
-                ///  reg_clk_dac_cpu_oen
-                CLK_DAC_CPU_OEN: u1,
-                ///  reg_clk40x_bb_oen
-                CLK40X_BB_OEN: u1,
-                ///  reg_clk_xtal_oen
-                CLK_XTAL_OEN: u1,
-                padding: u21,
-            }),
-            ///  APB_CTRL_WIFI_BB_CFG_REG
-            WIFI_BB_CFG: mmio.Mmio(packed struct(u32) {
-                ///  reg_wifi_bb_cfg
-                WIFI_BB_CFG: u32,
-            }),
-            ///  APB_CTRL_WIFI_BB_CFG_2_REG
-            WIFI_BB_CFG_2: mmio.Mmio(packed struct(u32) {
-                ///  reg_wifi_bb_cfg_2
-                WIFI_BB_CFG_2: u32,
-            }),
-            ///  APB_CTRL_WIFI_CLK_EN_REG
-            WIFI_CLK_EN: mmio.Mmio(packed struct(u32) {
-                ///  reg_wifi_clk_en
-                WIFI_CLK_EN: u32,
-            }),
-            ///  APB_CTRL_WIFI_RST_EN_REG
-            WIFI_RST_EN: mmio.Mmio(packed struct(u32) {
-                ///  reg_wifi_rst
-                WIFI_RST: u32,
-            }),
-            ///  APB_CTRL_HOST_INF_SEL_REG
-            HOST_INF_SEL: mmio.Mmio(packed struct(u32) {
-                ///  reg_peri_io_swap
-                PERI_IO_SWAP: u8,
-                padding: u24,
-            }),
-            ///  APB_CTRL_EXT_MEM_PMS_LOCK_REG
-            EXT_MEM_PMS_LOCK: mmio.Mmio(packed struct(u32) {
-                ///  reg_ext_mem_pms_lock
-                EXT_MEM_PMS_LOCK: u1,
-                padding: u31,
-            }),
-            reserved40: [4]u8,
-            ///  APB_CTRL_FLASH_ACE0_ATTR_REG
-            FLASH_ACE0_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace0_attr
-                FLASH_ACE0_ATTR: u2,
-                padding: u30,
-            }),
-            ///  APB_CTRL_FLASH_ACE1_ATTR_REG
-            FLASH_ACE1_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace1_attr
-                FLASH_ACE1_ATTR: u2,
-                padding: u30,
-            }),
-            ///  APB_CTRL_FLASH_ACE2_ATTR_REG
-            FLASH_ACE2_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace2_attr
-                FLASH_ACE2_ATTR: u2,
-                padding: u30,
-            }),
-            ///  APB_CTRL_FLASH_ACE3_ATTR_REG
-            FLASH_ACE3_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace3_attr
-                FLASH_ACE3_ATTR: u2,
-                padding: u30,
-            }),
-            ///  APB_CTRL_FLASH_ACE0_ADDR_REG
-            FLASH_ACE0_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace0_addr_s
-                S: u32,
-            }),
-            ///  APB_CTRL_FLASH_ACE1_ADDR_REG
-            FLASH_ACE1_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace1_addr_s
-                S: u32,
-            }),
-            ///  APB_CTRL_FLASH_ACE2_ADDR_REG
-            FLASH_ACE2_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace2_addr_s
-                S: u32,
-            }),
-            ///  APB_CTRL_FLASH_ACE3_ADDR_REG
-            FLASH_ACE3_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace3_addr_s
-                S: u32,
-            }),
-            ///  APB_CTRL_FLASH_ACE0_SIZE_REG
-            FLASH_ACE0_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace0_size
-                FLASH_ACE0_SIZE: u13,
-                padding: u19,
-            }),
-            ///  APB_CTRL_FLASH_ACE1_SIZE_REG
-            FLASH_ACE1_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace1_size
-                FLASH_ACE1_SIZE: u13,
-                padding: u19,
-            }),
-            ///  APB_CTRL_FLASH_ACE2_SIZE_REG
-            FLASH_ACE2_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace2_size
-                FLASH_ACE2_SIZE: u13,
-                padding: u19,
-            }),
-            ///  APB_CTRL_FLASH_ACE3_SIZE_REG
-            FLASH_ACE3_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  reg_flash_ace3_size
-                FLASH_ACE3_SIZE: u13,
-                padding: u19,
-            }),
-            reserved136: [48]u8,
-            ///  APB_CTRL_SPI_MEM_PMS_CTRL_REG
-            SPI_MEM_PMS_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_spi_mem_reject_int
-                SPI_MEM_REJECT_INT: u1,
-                ///  reg_spi_mem_reject_clr
-                SPI_MEM_REJECT_CLR: u1,
-                ///  reg_spi_mem_reject_cde
-                SPI_MEM_REJECT_CDE: u5,
-                padding: u25,
-            }),
-            ///  APB_CTRL_SPI_MEM_REJECT_ADDR_REG
-            SPI_MEM_REJECT_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_spi_mem_reject_addr
-                SPI_MEM_REJECT_ADDR: u32,
-            }),
-            ///  APB_CTRL_SDIO_CTRL_REG
-            SDIO_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_sdio_win_access_en
-                SDIO_WIN_ACCESS_EN: u1,
-                padding: u31,
-            }),
-            ///  APB_CTRL_REDCY_SIG0_REG
-            REDCY_SIG0: mmio.Mmio(packed struct(u32) {
-                ///  reg_redcy_sig0
-                REDCY_SIG0: u31,
-                ///  reg_redcy_andor
-                REDCY_ANDOR: u1,
-            }),
-            ///  APB_CTRL_REDCY_SIG1_REG
-            REDCY_SIG1: mmio.Mmio(packed struct(u32) {
-                ///  reg_redcy_sig1
-                REDCY_SIG1: u31,
-                ///  reg_redcy_nandor
-                REDCY_NANDOR: u1,
-            }),
-            ///  APB_CTRL_FRONT_END_MEM_PD_REG
-            FRONT_END_MEM_PD: mmio.Mmio(packed struct(u32) {
-                ///  reg_agc_mem_force_pu
-                AGC_MEM_FORCE_PU: u1,
-                ///  reg_agc_mem_force_pd
-                AGC_MEM_FORCE_PD: u1,
-                ///  reg_pbus_mem_force_pu
-                PBUS_MEM_FORCE_PU: u1,
-                ///  reg_pbus_mem_force_pd
-                PBUS_MEM_FORCE_PD: u1,
-                ///  reg_dc_mem_force_pu
-                DC_MEM_FORCE_PU: u1,
-                ///  reg_dc_mem_force_pd
-                DC_MEM_FORCE_PD: u1,
-                padding: u26,
-            }),
-            ///  APB_CTRL_RETENTION_CTRL_REG
-            RETENTION_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_retention_link_addr
-                RETENTION_LINK_ADDR: u27,
-                ///  reg_nobypass_cpu_iso_rst
-                NOBYPASS_CPU_ISO_RST: u1,
-                padding: u4,
-            }),
-            ///  APB_CTRL_CLKGATE_FORCE_ON_REG
-            CLKGATE_FORCE_ON: mmio.Mmio(packed struct(u32) {
-                ///  reg_rom_clkgate_force_on
-                ROM_CLKGATE_FORCE_ON: u2,
-                ///  reg_sram_clkgate_force_on
-                SRAM_CLKGATE_FORCE_ON: u4,
-                padding: u26,
-            }),
-            ///  APB_CTRL_MEM_POWER_DOWN_REG
-            MEM_POWER_DOWN: mmio.Mmio(packed struct(u32) {
-                ///  reg_rom_power_down
-                ROM_POWER_DOWN: u2,
-                ///  reg_sram_power_down
-                SRAM_POWER_DOWN: u4,
-                padding: u26,
-            }),
-            ///  APB_CTRL_MEM_POWER_UP_REG
-            MEM_POWER_UP: mmio.Mmio(packed struct(u32) {
-                ///  reg_rom_power_up
-                ROM_POWER_UP: u2,
-                ///  reg_sram_power_up
-                SRAM_POWER_UP: u4,
-                padding: u26,
-            }),
-            ///  APB_CTRL_RND_DATA_REG
-            RND_DATA: mmio.Mmio(packed struct(u32) {
-                ///  reg_rnd_data
-                RND_DATA: u32,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_CONFIG_REG
-            PERI_BACKUP_CONFIG: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  reg_peri_backup_flow_err
-                PERI_BACKUP_FLOW_ERR: u2,
-                reserved4: u1,
-                ///  reg_peri_backup_burst_limit
-                PERI_BACKUP_BURST_LIMIT: u5,
-                ///  reg_peri_backup_tout_thres
-                PERI_BACKUP_TOUT_THRES: u10,
-                ///  reg_peri_backup_size
-                PERI_BACKUP_SIZE: u10,
-                ///  reg_peri_backup_start
-                PERI_BACKUP_START: u1,
-                ///  reg_peri_backup_to_mem
-                PERI_BACKUP_TO_MEM: u1,
-                ///  reg_peri_backup_ena
-                PERI_BACKUP_ENA: u1,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_APB_ADDR_REG
-            PERI_BACKUP_APB_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_backup_apb_start_addr
-                BACKUP_APB_START_ADDR: u32,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_MEM_ADDR_REG
-            PERI_BACKUP_MEM_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_backup_mem_start_addr
-                BACKUP_MEM_START_ADDR: u32,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_INT_RAW_REG
-            PERI_BACKUP_INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  reg_peri_backup_done_int_raw
-                PERI_BACKUP_DONE_INT_RAW: u1,
-                ///  reg_peri_backup_err_int_raw
-                PERI_BACKUP_ERR_INT_RAW: u1,
-                padding: u30,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_INT_ST_REG
-            PERI_BACKUP_INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  reg_peri_backup_done_int_st
-                PERI_BACKUP_DONE_INT_ST: u1,
-                ///  reg_peri_backup_err_int_st
-                PERI_BACKUP_ERR_INT_ST: u1,
-                padding: u30,
-            }),
-            ///  APB_CTRL_PERI_BACKUP_INT_ENA_REG
-            PERI_BACKUP_INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  reg_peri_backup_done_int_ena
-                PERI_BACKUP_DONE_INT_ENA: u1,
-                ///  reg_peri_backup_err_int_ena
-                PERI_BACKUP_ERR_INT_ENA: u1,
-                padding: u30,
-            }),
-            reserved208: [4]u8,
-            ///  APB_CTRL_PERI_BACKUP_INT_CLR_REG
-            PERI_BACKUP_INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  reg_peri_backup_done_int_clr
-                PERI_BACKUP_DONE_INT_CLR: u1,
-                ///  reg_peri_backup_err_int_clr
-                PERI_BACKUP_ERR_INT_CLR: u1,
-                padding: u30,
-            }),
-            reserved1020: [808]u8,
-            ///  APB_CTRL_DATE_REG
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_dateVersion control
-                DATE: u32,
-            }),
-        };
-
-        ///  Successive Approximation Register Analog to Digital Converter
-        pub const APB_SARADC = extern struct {
-            ///  digital saradc configure register
-            CTRL: mmio.Mmio(packed struct(u32) {
-                ///  select software enable saradc sample
-                SARADC_START_FORCE: u1,
-                ///  software enable saradc sample
-                SARADC_START: u1,
-                reserved6: u4,
-                ///  SAR clock gated
-                SARADC_SAR_CLK_GATED: u1,
-                ///  SAR clock divider
-                SARADC_SAR_CLK_DIV: u8,
-                ///  0 ~ 15 means length 1 ~ 16
-                SARADC_SAR_PATT_LEN: u3,
-                reserved23: u5,
-                ///  clear the pointer of pattern table for DIG ADC1 CTRL
-                SARADC_SAR_PATT_P_CLEAR: u1,
-                reserved27: u3,
-                ///  force option to xpd sar blocks
-                SARADC_XPD_SAR_FORCE: u2,
-                reserved30: u1,
-                ///  wait arbit signal stable after sar_done
-                SARADC_WAIT_ARB_CYCLE: u2,
-            }),
-            ///  digital saradc configure register
-            CTRL2: mmio.Mmio(packed struct(u32) {
-                ///  enable max meas num
-                SARADC_MEAS_NUM_LIMIT: u1,
-                ///  max conversion number
-                SARADC_MAX_MEAS_NUM: u8,
-                ///  1: data to DIG ADC1 CTRL is inverted, otherwise not
-                SARADC_SAR1_INV: u1,
-                ///  1: data to DIG ADC2 CTRL is inverted, otherwise not
-                SARADC_SAR2_INV: u1,
-                reserved12: u1,
-                ///  to set saradc timer target
-                SARADC_TIMER_TARGET: u12,
-                ///  to enable saradc timer trigger
-                SARADC_TIMER_EN: u1,
-                padding: u7,
-            }),
-            ///  digital saradc configure register
-            FILTER_CTRL1: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  Factor of saradc filter1
-                APB_SARADC_FILTER_FACTOR1: u3,
-                ///  Factor of saradc filter0
-                APB_SARADC_FILTER_FACTOR0: u3,
-            }),
-            ///  digital saradc configure register
-            FSM_WAIT: mmio.Mmio(packed struct(u32) {
-                ///  saradc_xpd_wait
-                SARADC_XPD_WAIT: u8,
-                ///  saradc_rstb_wait
-                SARADC_RSTB_WAIT: u8,
-                ///  saradc_standby_wait
-                SARADC_STANDBY_WAIT: u8,
-                padding: u8,
-            }),
-            ///  digital saradc configure register
-            SAR1_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  saradc1 status about data and channel
-                SARADC_SAR1_STATUS: u32,
-            }),
-            ///  digital saradc configure register
-            SAR2_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  saradc2 status about data and channel
-                SARADC_SAR2_STATUS: u32,
-            }),
-            ///  digital saradc configure register
-            SAR_PATT_TAB1: mmio.Mmio(packed struct(u32) {
-                ///  item 0 ~ 3 for pattern table 1 (each item one byte)
-                SARADC_SAR_PATT_TAB1: u24,
-                padding: u8,
-            }),
-            ///  digital saradc configure register
-            SAR_PATT_TAB2: mmio.Mmio(packed struct(u32) {
-                ///  Item 4 ~ 7 for pattern table 1 (each item one byte)
-                SARADC_SAR_PATT_TAB2: u24,
-                padding: u8,
-            }),
-            ///  digital saradc configure register
-            ONETIME_SAMPLE: mmio.Mmio(packed struct(u32) {
-                reserved23: u23,
-                ///  configure onetime atten
-                SARADC_ONETIME_ATTEN: u2,
-                ///  configure onetime channel
-                SARADC_ONETIME_CHANNEL: u4,
-                ///  trigger adc onetime sample
-                SARADC_ONETIME_START: u1,
-                ///  enable adc2 onetime sample
-                SARADC2_ONETIME_SAMPLE: u1,
-                ///  enable adc1 onetime sample
-                SARADC1_ONETIME_SAMPLE: u1,
-            }),
-            ///  digital saradc configure register
-            ARB_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  adc2 arbiter force to enableapb controller
-                ADC_ARB_APB_FORCE: u1,
-                ///  adc2 arbiter force to enable rtc controller
-                ADC_ARB_RTC_FORCE: u1,
-                ///  adc2 arbiter force to enable wifi controller
-                ADC_ARB_WIFI_FORCE: u1,
-                ///  adc2 arbiter force grant
-                ADC_ARB_GRANT_FORCE: u1,
-                ///  Set adc2 arbiterapb priority
-                ADC_ARB_APB_PRIORITY: u2,
-                ///  Set adc2 arbiter rtc priority
-                ADC_ARB_RTC_PRIORITY: u2,
-                ///  Set adc2 arbiter wifi priority
-                ADC_ARB_WIFI_PRIORITY: u2,
-                ///  adc2 arbiter uses fixed priority
-                ADC_ARB_FIX_PRIORITY: u1,
-                padding: u19,
-            }),
-            ///  digital saradc configure register
-            FILTER_CTRL0: mmio.Mmio(packed struct(u32) {
-                reserved18: u18,
-                ///  configure filter1 to adc channel
-                APB_SARADC_FILTER_CHANNEL1: u4,
-                ///  configure filter0 to adc channel
-                APB_SARADC_FILTER_CHANNEL0: u4,
-                reserved31: u5,
-                ///  enable apb_adc1_filter
-                APB_SARADC_FILTER_RESET: u1,
-            }),
-            ///  digital saradc configure register
-            SAR1DATA_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  saradc1 data
-                APB_SARADC1_DATA: u17,
-                padding: u15,
-            }),
-            ///  digital saradc configure register
-            SAR2DATA_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  saradc2 data
-                APB_SARADC2_DATA: u17,
-                padding: u15,
-            }),
-            ///  digital saradc configure register
-            THRES0_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  configure thres0 to adc channel
-                APB_SARADC_THRES0_CHANNEL: u4,
-                reserved5: u1,
-                ///  saradc thres0 monitor thres
-                APB_SARADC_THRES0_HIGH: u13,
-                ///  saradc thres0 monitor thres
-                APB_SARADC_THRES0_LOW: u13,
-                padding: u1,
-            }),
-            ///  digital saradc configure register
-            THRES1_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  configure thres1 to adc channel
-                APB_SARADC_THRES1_CHANNEL: u4,
-                reserved5: u1,
-                ///  saradc thres1 monitor thres
-                APB_SARADC_THRES1_HIGH: u13,
-                ///  saradc thres1 monitor thres
-                APB_SARADC_THRES1_LOW: u13,
-                padding: u1,
-            }),
-            ///  digital saradc configure register
-            THRES_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved27: u27,
-                ///  enable thres to all channel
-                APB_SARADC_THRES_ALL_EN: u1,
-                reserved30: u2,
-                ///  enable thres1
-                APB_SARADC_THRES1_EN: u1,
-                ///  enable thres0
-                APB_SARADC_THRES0_EN: u1,
-            }),
-            ///  digital saradc int register
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  saradc thres1 low interrupt enable
-                APB_SARADC_THRES1_LOW_INT_ENA: u1,
-                ///  saradc thres0 low interrupt enable
-                APB_SARADC_THRES0_LOW_INT_ENA: u1,
-                ///  saradc thres1 high interrupt enable
-                APB_SARADC_THRES1_HIGH_INT_ENA: u1,
-                ///  saradc thres0 high interrupt enable
-                APB_SARADC_THRES0_HIGH_INT_ENA: u1,
-                ///  saradc2 done interrupt enable
-                APB_SARADC2_DONE_INT_ENA: u1,
-                ///  saradc1 done interrupt enable
-                APB_SARADC1_DONE_INT_ENA: u1,
-            }),
-            ///  digital saradc int register
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  saradc thres1 low interrupt raw
-                APB_SARADC_THRES1_LOW_INT_RAW: u1,
-                ///  saradc thres0 low interrupt raw
-                APB_SARADC_THRES0_LOW_INT_RAW: u1,
-                ///  saradc thres1 high interrupt raw
-                APB_SARADC_THRES1_HIGH_INT_RAW: u1,
-                ///  saradc thres0 high interrupt raw
-                APB_SARADC_THRES0_HIGH_INT_RAW: u1,
-                ///  saradc2 done interrupt raw
-                APB_SARADC2_DONE_INT_RAW: u1,
-                ///  saradc1 done interrupt raw
-                APB_SARADC1_DONE_INT_RAW: u1,
-            }),
-            ///  digital saradc int register
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  saradc thres1 low interrupt state
-                APB_SARADC_THRES1_LOW_INT_ST: u1,
-                ///  saradc thres0 low interrupt state
-                APB_SARADC_THRES0_LOW_INT_ST: u1,
-                ///  saradc thres1 high interrupt state
-                APB_SARADC_THRES1_HIGH_INT_ST: u1,
-                ///  saradc thres0 high interrupt state
-                APB_SARADC_THRES0_HIGH_INT_ST: u1,
-                ///  saradc2 done interrupt state
-                APB_SARADC2_DONE_INT_ST: u1,
-                ///  saradc1 done interrupt state
-                APB_SARADC1_DONE_INT_ST: u1,
-            }),
-            ///  digital saradc int register
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  saradc thres1 low interrupt clear
-                APB_SARADC_THRES1_LOW_INT_CLR: u1,
-                ///  saradc thres0 low interrupt clear
-                APB_SARADC_THRES0_LOW_INT_CLR: u1,
-                ///  saradc thres1 high interrupt clear
-                APB_SARADC_THRES1_HIGH_INT_CLR: u1,
-                ///  saradc thres0 high interrupt clear
-                APB_SARADC_THRES0_HIGH_INT_CLR: u1,
-                ///  saradc2 done interrupt clear
-                APB_SARADC2_DONE_INT_CLR: u1,
-                ///  saradc1 done interrupt clear
-                APB_SARADC1_DONE_INT_CLR: u1,
-            }),
-            ///  digital saradc configure register
-            DMA_CONF: mmio.Mmio(packed struct(u32) {
-                ///  the dma_in_suc_eof gen when sample cnt = spi_eof_num
-                APB_ADC_EOF_NUM: u16,
-                reserved30: u14,
-                ///  reset_apb_adc_state
-                APB_ADC_RESET_FSM: u1,
-                ///  enable apb_adc use spi_dma
-                APB_ADC_TRANS: u1,
-            }),
-            ///  digital saradc configure register
-            CLKM_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Integral I2S clock divider value
-                CLKM_DIV_NUM: u8,
-                ///  Fractional clock divider numerator value
-                CLKM_DIV_B: u6,
-                ///  Fractional clock divider denominator value
-                CLKM_DIV_A: u6,
-                ///  reg clk en
-                CLK_EN: u1,
-                ///  Set this bit to enable clk_apll
-                CLK_SEL: u2,
-                padding: u9,
-            }),
-            ///  digital tsens configure register
-            APB_TSENS_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  temperature sensor data out
-                TSENS_OUT: u8,
-                reserved13: u5,
-                ///  invert temperature sensor data
-                TSENS_IN_INV: u1,
-                ///  temperature sensor clock divider
-                TSENS_CLK_DIV: u8,
-                ///  temperature sensor power up
-                TSENS_PU: u1,
-                padding: u9,
-            }),
-            ///  digital tsens configure register
-            TSENS_CTRL2: mmio.Mmio(packed struct(u32) {
-                ///  the time that power up tsens need wait
-                TSENS_XPD_WAIT: u12,
-                ///  force power up tsens
-                TSENS_XPD_FORCE: u2,
-                ///  inv tsens clk
-                TSENS_CLK_INV: u1,
-                ///  tsens clk select
-                TSENS_CLK_SEL: u1,
-                padding: u16,
-            }),
-            ///  digital saradc configure register
-            CALI: mmio.Mmio(packed struct(u32) {
-                ///  saradc cali factor
-                APB_SARADC_CALI_CFG: u17,
-                padding: u15,
-            }),
-            reserved1020: [920]u8,
-            ///  version
-            CTRL_DATE: mmio.Mmio(packed struct(u32) {
-                ///  version
-                DATE: u32,
-            }),
-        };
-
-        ///  Debug Assist
-        pub const ASSIST_DEBUG = extern struct {
-            ///  ASSIST_DEBUG_C0RE_0_MONTR_ENA_REG
-            C0RE_0_MONTR_ENA: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_rd_ena
-                CORE_0_AREA_DRAM0_0_RD_ENA: u1,
-                ///  reg_core_0_area_dram0_0_wr_ena
-                CORE_0_AREA_DRAM0_0_WR_ENA: u1,
-                ///  reg_core_0_area_dram0_1_rd_ena
-                CORE_0_AREA_DRAM0_1_RD_ENA: u1,
-                ///  reg_core_0_area_dram0_1_wr_ena
-                CORE_0_AREA_DRAM0_1_WR_ENA: u1,
-                ///  reg_core_0_area_pif_0_rd_ena
-                CORE_0_AREA_PIF_0_RD_ENA: u1,
-                ///  reg_core_0_area_pif_0_wr_ena
-                CORE_0_AREA_PIF_0_WR_ENA: u1,
-                ///  reg_core_0_area_pif_1_rd_ena
-                CORE_0_AREA_PIF_1_RD_ENA: u1,
-                ///  reg_core_0_area_pif_1_wr_ena
-                CORE_0_AREA_PIF_1_WR_ENA: u1,
-                ///  reg_core_0_sp_spill_min_ena
-                CORE_0_SP_SPILL_MIN_ENA: u1,
-                ///  reg_core_0_sp_spill_max_ena
-                CORE_0_SP_SPILL_MAX_ENA: u1,
-                ///  reg_core_0_iram0_exception_monitor_ena
-                CORE_0_IRAM0_EXCEPTION_MONITOR_ENA: u1,
-                ///  reg_core_0_dram0_exception_monitor_ena
-                CORE_0_DRAM0_EXCEPTION_MONITOR_ENA: u1,
-                padding: u20,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_INTR_RAW_REG
-            CORE_0_INTR_RAW: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_rd_raw
-                CORE_0_AREA_DRAM0_0_RD_RAW: u1,
-                ///  reg_core_0_area_dram0_0_wr_raw
-                CORE_0_AREA_DRAM0_0_WR_RAW: u1,
-                ///  reg_core_0_area_dram0_1_rd_raw
-                CORE_0_AREA_DRAM0_1_RD_RAW: u1,
-                ///  reg_core_0_area_dram0_1_wr_raw
-                CORE_0_AREA_DRAM0_1_WR_RAW: u1,
-                ///  reg_core_0_area_pif_0_rd_raw
-                CORE_0_AREA_PIF_0_RD_RAW: u1,
-                ///  reg_core_0_area_pif_0_wr_raw
-                CORE_0_AREA_PIF_0_WR_RAW: u1,
-                ///  reg_core_0_area_pif_1_rd_raw
-                CORE_0_AREA_PIF_1_RD_RAW: u1,
-                ///  reg_core_0_area_pif_1_wr_raw
-                CORE_0_AREA_PIF_1_WR_RAW: u1,
-                ///  reg_core_0_sp_spill_min_raw
-                CORE_0_SP_SPILL_MIN_RAW: u1,
-                ///  reg_core_0_sp_spill_max_raw
-                CORE_0_SP_SPILL_MAX_RAW: u1,
-                ///  reg_core_0_iram0_exception_monitor_raw
-                CORE_0_IRAM0_EXCEPTION_MONITOR_RAW: u1,
-                ///  reg_core_0_dram0_exception_monitor_raw
-                CORE_0_DRAM0_EXCEPTION_MONITOR_RAW: u1,
-                padding: u20,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_INTR_ENA_REG
-            CORE_0_INTR_ENA: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_rd_intr_ena
-                CORE_0_AREA_DRAM0_0_RD_INTR_ENA: u1,
-                ///  reg_core_0_area_dram0_0_wr_intr_ena
-                CORE_0_AREA_DRAM0_0_WR_INTR_ENA: u1,
-                ///  reg_core_0_area_dram0_1_rd_intr_ena
-                CORE_0_AREA_DRAM0_1_RD_INTR_ENA: u1,
-                ///  reg_core_0_area_dram0_1_wr_intr_ena
-                CORE_0_AREA_DRAM0_1_WR_INTR_ENA: u1,
-                ///  reg_core_0_area_pif_0_rd_intr_ena
-                CORE_0_AREA_PIF_0_RD_INTR_ENA: u1,
-                ///  reg_core_0_area_pif_0_wr_intr_ena
-                CORE_0_AREA_PIF_0_WR_INTR_ENA: u1,
-                ///  reg_core_0_area_pif_1_rd_intr_ena
-                CORE_0_AREA_PIF_1_RD_INTR_ENA: u1,
-                ///  reg_core_0_area_pif_1_wr_intr_ena
-                CORE_0_AREA_PIF_1_WR_INTR_ENA: u1,
-                ///  reg_core_0_sp_spill_min_intr_ena
-                CORE_0_SP_SPILL_MIN_INTR_ENA: u1,
-                ///  reg_core_0_sp_spill_max_intr_ena
-                CORE_0_SP_SPILL_MAX_INTR_ENA: u1,
-                ///  reg_core_0_iram0_exception_monitor_ena
-                CORE_0_IRAM0_EXCEPTION_MONITOR_RLS: u1,
-                ///  reg_core_0_dram0_exception_monitor_ena
-                CORE_0_DRAM0_EXCEPTION_MONITOR_RLS: u1,
-                padding: u20,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_INTR_CLR_REG
-            CORE_0_INTR_CLR: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_rd_clr
-                CORE_0_AREA_DRAM0_0_RD_CLR: u1,
-                ///  reg_core_0_area_dram0_0_wr_clr
-                CORE_0_AREA_DRAM0_0_WR_CLR: u1,
-                ///  reg_core_0_area_dram0_1_rd_clr
-                CORE_0_AREA_DRAM0_1_RD_CLR: u1,
-                ///  reg_core_0_area_dram0_1_wr_clr
-                CORE_0_AREA_DRAM0_1_WR_CLR: u1,
-                ///  reg_core_0_area_pif_0_rd_clr
-                CORE_0_AREA_PIF_0_RD_CLR: u1,
-                ///  reg_core_0_area_pif_0_wr_clr
-                CORE_0_AREA_PIF_0_WR_CLR: u1,
-                ///  reg_core_0_area_pif_1_rd_clr
-                CORE_0_AREA_PIF_1_RD_CLR: u1,
-                ///  reg_core_0_area_pif_1_wr_clr
-                CORE_0_AREA_PIF_1_WR_CLR: u1,
-                ///  reg_core_0_sp_spill_min_clr
-                CORE_0_SP_SPILL_MIN_CLR: u1,
-                ///  reg_core_0_sp_spill_max_clr
-                CORE_0_SP_SPILL_MAX_CLR: u1,
-                ///  reg_core_0_iram0_exception_monitor_clr
-                CORE_0_IRAM0_EXCEPTION_MONITOR_CLR: u1,
-                ///  reg_core_0_dram0_exception_monitor_clr
-                CORE_0_DRAM0_EXCEPTION_MONITOR_CLR: u1,
-                padding: u20,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MIN_REG
-            CORE_0_AREA_DRAM0_0_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_min
-                CORE_0_AREA_DRAM0_0_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_0_MAX_REG
-            CORE_0_AREA_DRAM0_0_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_0_max
-                CORE_0_AREA_DRAM0_0_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MIN_REG
-            CORE_0_AREA_DRAM0_1_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_1_min
-                CORE_0_AREA_DRAM0_1_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_DRAM0_1_MAX_REG
-            CORE_0_AREA_DRAM0_1_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_dram0_1_max
-                CORE_0_AREA_DRAM0_1_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_0_MIN_REG
-            CORE_0_AREA_PIF_0_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_pif_0_min
-                CORE_0_AREA_PIF_0_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_0_MAX_REG
-            CORE_0_AREA_PIF_0_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_pif_0_max
-                CORE_0_AREA_PIF_0_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_1_MIN_REG
-            CORE_0_AREA_PIF_1_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_pif_1_min
-                CORE_0_AREA_PIF_1_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_PIF_1_MAX_REG
-            CORE_0_AREA_PIF_1_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_pif_1_max
-                CORE_0_AREA_PIF_1_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_PC_REG
-            CORE_0_AREA_PC: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_pc
-                CORE_0_AREA_PC: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_AREA_SP_REG
-            CORE_0_AREA_SP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_area_sp
-                CORE_0_AREA_SP: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_SP_MIN_REG
-            CORE_0_SP_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_sp_min
-                CORE_0_SP_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_SP_MAX_REG
-            CORE_0_SP_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_sp_max
-                CORE_0_SP_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_SP_PC_REG
-            CORE_0_SP_PC: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_sp_pc
-                CORE_0_SP_PC: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_RCD_EN_REG
-            CORE_0_RCD_EN: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_rcd_recorden
-                CORE_0_RCD_RECORDEN: u1,
-                ///  reg_core_0_rcd_pdebugen
-                CORE_0_RCD_PDEBUGEN: u1,
-                padding: u30,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGPC_REG
-            CORE_0_RCD_PDEBUGPC: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_rcd_pdebugpc
-                CORE_0_RCD_PDEBUGPC: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
-            CORE_0_RCD_PDEBUGSP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_rcd_pdebugsp
-                CORE_0_RCD_PDEBUGSP: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_RCD_PDEBUGSP_REG
-            CORE_0_IRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_iram0_recording_addr_0
-                CORE_0_IRAM0_RECORDING_ADDR_0: u24,
-                ///  reg_core_0_iram0_recording_wr_0
-                CORE_0_IRAM0_RECORDING_WR_0: u1,
-                ///  reg_core_0_iram0_recording_loadstore_0
-                CORE_0_IRAM0_RECORDING_LOADSTORE_0: u1,
-                padding: u6,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_IRAM0_EXCEPTION_MONITOR_1_REG
-            CORE_0_IRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_iram0_recording_addr_1
-                CORE_0_IRAM0_RECORDING_ADDR_1: u24,
-                ///  reg_core_0_iram0_recording_wr_1
-                CORE_0_IRAM0_RECORDING_WR_1: u1,
-                ///  reg_core_0_iram0_recording_loadstore_1
-                CORE_0_IRAM0_RECORDING_LOADSTORE_1: u1,
-                padding: u6,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_0_REG
-            CORE_0_DRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_dram0_recording_addr_0
-                CORE_0_DRAM0_RECORDING_ADDR_0: u24,
-                ///  reg_core_0_dram0_recording_wr_0
-                CORE_0_DRAM0_RECORDING_WR_0: u1,
-                ///  reg_core_0_dram0_recording_byteen_0
-                CORE_0_DRAM0_RECORDING_BYTEEN_0: u4,
-                padding: u3,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
-            CORE_0_DRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_dram0_recording_pc_0
-                CORE_0_DRAM0_RECORDING_PC_0: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_1_REG
-            CORE_0_DRAM0_EXCEPTION_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_dram0_recording_addr_1
-                CORE_0_DRAM0_RECORDING_ADDR_1: u24,
-                ///  reg_core_0_dram0_recording_wr_1
-                CORE_0_DRAM0_RECORDING_WR_1: u1,
-                ///  reg_core_0_dram0_recording_byteen_1
-                CORE_0_DRAM0_RECORDING_BYTEEN_1: u4,
-                padding: u3,
-            }),
-            ///  ASSIST_DEBUG_CORE_0_DRAM0_EXCEPTION_MONITOR_3_REG
-            CORE_0_DRAM0_EXCEPTION_MONITOR_3: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_dram0_recording_pc_1
-                CORE_0_DRAM0_RECORDING_PC_1: u32,
-            }),
-            ///  ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0_REG
-            CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_x_iram0_dram0_limit_cycle_0
-                CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_0: u20,
-                padding: u12,
-            }),
-            ///  ASSIST_DEBUG_CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1_REG
-            CORE_X_IRAM0_DRAM0_EXCEPTION_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_x_iram0_dram0_limit_cycle_1
-                CORE_X_IRAM0_DRAM0_LIMIT_CYCLE_1: u20,
-                padding: u12,
-            }),
-            ///  ASSIST_DEBUG_LOG_SETTING
-            LOG_SETTING: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_ena
-                LOG_ENA: u3,
-                ///  reg_log_mode
-                LOG_MODE: u4,
-                ///  reg_log_mem_loop_enable
-                LOG_MEM_LOOP_ENABLE: u1,
-                padding: u24,
-            }),
-            ///  ASSIST_DEBUG_LOG_DATA_0_REG
-            LOG_DATA_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_data_0
-                LOG_DATA_0: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_DATA_MASK_REG
-            LOG_DATA_MASK: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_data_size
-                LOG_DATA_SIZE: u16,
-                padding: u16,
-            }),
-            ///  ASSIST_DEBUG_LOG_MIN_REG
-            LOG_MIN: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_min
-                LOG_MIN: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_MAX_REG
-            LOG_MAX: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_max
-                LOG_MAX: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_MEM_START_REG
-            LOG_MEM_START: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_mem_start
-                LOG_MEM_START: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_MEM_END_REG
-            LOG_MEM_END: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_mem_end
-                LOG_MEM_END: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_MEM_WRITING_ADDR_REG
-            LOG_MEM_WRITING_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_mem_writing_addr
-                LOG_MEM_WRITING_ADDR: u32,
-            }),
-            ///  ASSIST_DEBUG_LOG_MEM_FULL_FLAG_REG
-            LOG_MEM_FULL_FLAG: mmio.Mmio(packed struct(u32) {
-                ///  reg_log_mem_full_flag
-                LOG_MEM_FULL_FLAG: u1,
-                ///  reg_clr_log_mem_full_flag
-                CLR_LOG_MEM_FULL_FLAG: u1,
-                padding: u30,
-            }),
-            ///  ASSIST_DEBUG_C0RE_0_LASTPC_BEFORE_EXCEPTION
-            C0RE_0_LASTPC_BEFORE_EXCEPTION: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_lastpc_before_exc
-                CORE_0_LASTPC_BEFORE_EXC: u32,
-            }),
-            ///  ASSIST_DEBUG_C0RE_0_DEBUG_MODE
-            C0RE_0_DEBUG_MODE: mmio.Mmio(packed struct(u32) {
-                ///  reg_core_0_debug_mode
-                CORE_0_DEBUG_MODE: u1,
-                ///  reg_core_0_debug_module_active
-                CORE_0_DEBUG_MODULE_ACTIVE: u1,
-                padding: u30,
-            }),
-            reserved508: [352]u8,
-            ///  ASSIST_DEBUG_DATE_REG
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_assist_debug_date
-                ASSIST_DEBUG_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  DMA (Direct Memory Access) Controller
-        pub const DMA = extern struct {
-            ///  DMA_INT_RAW_CH0_REG.
-            INT_RAW_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0.
-                IN_DONE_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 0. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 0.
-                IN_SUC_EOF_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 0. For other peripherals, this raw interrupt is reserved.
-                IN_ERR_EOF_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 0.
-                OUT_DONE_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 0.
-                OUT_EOF_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 0.
-                IN_DSCR_ERR_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 0.
-                OUT_DSCR_ERR_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 0.
-                IN_DSCR_EMPTY_CH0_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 0.
-                OUT_TOTAL_EOF_CH0_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is overflow.
-                INFIFO_OVF_CH0_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 0 is underflow.
-                INFIFO_UDF_CH0_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is overflow.
-                OUTFIFO_OVF_CH0_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 0 is underflow.
-                OUTFIFO_UDF_CH0_INT_RAW: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ST_CH0_REG.
-            INT_ST_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH0_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH0_INT_ST: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ENA_CH0_REG.
-            INT_ENA_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH0_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH0_INT_ENA: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_CLR_CH0_REG.
-            INT_CLR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH0_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH0_INT_CLR: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_RAW_CH1_REG.
-            INT_RAW_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1.
-                IN_DONE_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 1. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 1.
-                IN_SUC_EOF_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 1. For other peripherals, this raw interrupt is reserved.
-                IN_ERR_EOF_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 1.
-                OUT_DONE_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 1.
-                OUT_EOF_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 1.
-                IN_DSCR_ERR_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 1.
-                OUT_DSCR_ERR_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 1.
-                IN_DSCR_EMPTY_CH1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 1.
-                OUT_TOTAL_EOF_CH1_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is overflow.
-                INFIFO_OVF_CH1_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 1 is underflow.
-                INFIFO_UDF_CH1_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is overflow.
-                OUTFIFO_OVF_CH1_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 1 is underflow.
-                OUTFIFO_UDF_CH1_INT_RAW: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ST_CH1_REG.
-            INT_ST_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH1_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH1_INT_ST: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ENA_CH1_REG.
-            INT_ENA_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH1_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH1_INT_ENA: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_CLR_CH1_REG.
-            INT_CLR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH1_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH1_INT_CLR: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_RAW_CH2_REG.
-            INT_RAW_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2.
-                IN_DONE_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received for Rx channel 2. For UHCI0, the raw interrupt bit turns to high level when the last data pointed by one inlink descriptor has been received and no data error is detected for Rx channel 2.
-                IN_SUC_EOF_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data error is detected only in the case that the peripheral is UHCI0 for Rx channel 2. For other peripherals, this raw interrupt is reserved.
-                IN_ERR_EOF_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been transmitted to peripherals for Tx channel 2.
-                OUT_DONE_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when the last data pointed by one outlink descriptor has been read from memory for Tx channel 2.
-                OUT_EOF_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting inlink descriptor error, including owner error, the second and third word error of inlink descriptor for Rx channel 2.
-                IN_DSCR_ERR_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when detecting outlink descriptor error, including owner error, the second and third word error of outlink descriptor for Tx channel 2.
-                OUT_DSCR_ERR_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when Rx buffer pointed by inlink is full and receiving data is not completed, but there is no more inlink for Rx channel 2.
-                IN_DSCR_EMPTY_CH2_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when data corresponding a outlink (includes one link descriptor or few link descriptors) is transmitted out for Tx channel 2.
-                OUT_TOTAL_EOF_CH2_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is overflow.
-                INFIFO_OVF_CH2_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Rx channel 2 is underflow.
-                INFIFO_UDF_CH2_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is overflow.
-                OUTFIFO_OVF_CH2_INT_RAW: u1,
-                ///  This raw interrupt bit turns to high level when level 1 fifo of Tx channel 2 is underflow.
-                OUTFIFO_UDF_CH2_INT_RAW: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ST_CH2_REG.
-            INT_ST_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt status bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH2_INT_ST: u1,
-                ///  The raw interrupt status bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH2_INT_ST: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_ENA_CH2_REG.
-            INT_ENA_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The interrupt enable bit for the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH2_INT_ENA: u1,
-                ///  The interrupt enable bit for the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH2_INT_ENA: u1,
-                padding: u19,
-            }),
-            ///  DMA_INT_CLR_CH2_REG.
-            INT_CLR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the IN_DONE_CH_INT interrupt.
-                IN_DONE_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the IN_SUC_EOF_CH_INT interrupt.
-                IN_SUC_EOF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the IN_ERR_EOF_CH_INT interrupt.
-                IN_ERR_EOF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DONE_CH_INT interrupt.
-                OUT_DONE_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_EOF_CH_INT interrupt.
-                OUT_EOF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_ERR_CH_INT interrupt.
-                IN_DSCR_ERR_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_DSCR_ERR_CH_INT interrupt.
-                OUT_DSCR_ERR_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the IN_DSCR_EMPTY_CH_INT interrupt.
-                IN_DSCR_EMPTY_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUT_TOTAL_EOF_CH_INT interrupt.
-                OUT_TOTAL_EOF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_OVF_L1_CH_INT interrupt.
-                INFIFO_OVF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the INFIFO_UDF_L1_CH_INT interrupt.
-                INFIFO_UDF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_OVF_L1_CH_INT interrupt.
-                OUTFIFO_OVF_CH2_INT_CLR: u1,
-                ///  Set this bit to clear the OUTFIFO_UDF_L1_CH_INT interrupt.
-                OUTFIFO_UDF_CH2_INT_CLR: u1,
-                padding: u19,
-            }),
-            reserved64: [16]u8,
-            ///  DMA_AHB_TEST_REG.
-            AHB_TEST: mmio.Mmio(packed struct(u32) {
-                ///  reserved
-                AHB_TESTMODE: u3,
-                reserved4: u1,
-                ///  reserved
-                AHB_TESTADDR: u2,
-                padding: u26,
-            }),
-            ///  DMA_MISC_CONF_REG.
-            MISC_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit, then clear this bit to reset the internal ahb FSM.
-                AHBM_RST_INTER: u1,
-                reserved2: u1,
-                ///  Set this bit to disable priority arbitration function.
-                ARB_PRI_DIS: u1,
-                ///  reg_clk_en
-                CLK_EN: u1,
-                padding: u28,
-            }),
-            ///  DMA_DATE_REG.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  register version.
-                DATE: u32,
-            }),
-            reserved112: [36]u8,
-            ///  DMA_IN_CONF0_CH0_REG.
-            IN_CONF0_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 0 Rx FSM and Rx FIFO pointer.
-                IN_RST_CH0: u1,
-                ///  reserved
-                IN_LOOP_TEST_CH0: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 reading link descriptor when accessing internal SRAM.
-                INDSCR_BURST_EN_CH0: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 0 receiving data when accessing internal SRAM.
-                IN_DATA_BURST_EN_CH0: u1,
-                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
-                MEM_TRANS_EN_CH0: u1,
-                padding: u27,
-            }),
-            ///  DMA_IN_CONF1_CH0_REG.
-            IN_CONF1_CH0: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                IN_CHECK_OWNER_CH0: u1,
-                padding: u19,
-            }),
-            ///  DMA_INFIFO_STATUS_CH0_REG.
-            INFIFO_STATUS_CH0: mmio.Mmio(packed struct(u32) {
-                ///  L1 Rx FIFO full signal for Rx channel 0.
-                INFIFO_FULL_CH0: u1,
-                ///  L1 Rx FIFO empty signal for Rx channel 0.
-                INFIFO_EMPTY_CH0: u1,
-                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 0.
-                INFIFO_CNT_CH0: u6,
-                reserved23: u15,
-                ///  reserved
-                IN_REMAIN_UNDER_1B_CH0: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_2B_CH0: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_3B_CH0: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_4B_CH0: u1,
-                ///  reserved
-                IN_BUF_HUNGRY_CH0: u1,
-                padding: u4,
-            }),
-            ///  DMA_IN_POP_CH0_REG.
-            IN_POP_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data popping from DMA FIFO.
-                INFIFO_RDATA_CH0: u12,
-                ///  Set this bit to pop data from DMA FIFO.
-                INFIFO_POP_CH0: u1,
-                padding: u19,
-            }),
-            ///  DMA_IN_LINK_CH0_REG.
-            IN_LINK_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
-                INLINK_ADDR_CH0: u20,
-                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
-                INLINK_AUTO_RET_CH0: u1,
-                ///  Set this bit to stop dealing with the inlink descriptors.
-                INLINK_STOP_CH0: u1,
-                ///  Set this bit to start dealing with the inlink descriptors.
-                INLINK_START_CH0: u1,
-                ///  Set this bit to mount a new inlink descriptor.
-                INLINK_RESTART_CH0: u1,
-                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
-                INLINK_PARK_CH0: u1,
-                padding: u7,
-            }),
-            ///  DMA_IN_STATE_CH0_REG.
-            IN_STATE_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current inlink descriptor's address.
-                INLINK_DSCR_ADDR_CH0: u18,
-                ///  reserved
-                IN_DSCR_STATE_CH0: u2,
-                ///  reserved
-                IN_STATE_CH0: u3,
-                padding: u9,
-            }),
-            ///  DMA_IN_SUC_EOF_DES_ADDR_CH0_REG.
-            IN_SUC_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
-                IN_SUC_EOF_DES_ADDR_CH0: u32,
-            }),
-            ///  DMA_IN_ERR_EOF_DES_ADDR_CH0_REG.
-            IN_ERR_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
-                IN_ERR_EOF_DES_ADDR_CH0: u32,
-            }),
-            ///  DMA_IN_DSCR_CH0_REG.
-            IN_DSCR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current inlink descriptor x.
-                INLINK_DSCR_CH0: u32,
-            }),
-            ///  DMA_IN_DSCR_BF0_CH0_REG.
-            IN_DSCR_BF0_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last inlink descriptor x-1.
-                INLINK_DSCR_BF0_CH0: u32,
-            }),
-            ///  DMA_IN_DSCR_BF1_CH0_REG.
-            IN_DSCR_BF1_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                INLINK_DSCR_BF1_CH0: u32,
-            }),
-            ///  DMA_IN_PRI_CH0_REG.
-            IN_PRI_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Rx channel 0. The larger of the value, the higher of the priority.
-                RX_PRI_CH0: u4,
-                padding: u28,
-            }),
-            ///  DMA_IN_PERI_SEL_CH0_REG.
-            IN_PERI_SEL_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Rx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_IN_SEL_CH0: u6,
-                padding: u26,
-            }),
-            reserved208: [44]u8,
-            ///  DMA_OUT_CONF0_CH0_REG.
-            OUT_CONF0_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 0 Tx FSM and Tx FIFO pointer.
-                OUT_RST_CH0: u1,
-                ///  reserved
-                OUT_LOOP_TEST_CH0: u1,
-                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
-                OUT_AUTO_WRBACK_CH0: u1,
-                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 0 is generated when data need to transmit has been popped from FIFO in DMA
-                OUT_EOF_MODE_CH0: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 reading link descriptor when accessing internal SRAM.
-                OUTDSCR_BURST_EN_CH0: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 0 transmitting data when accessing internal SRAM.
-                OUT_DATA_BURST_EN_CH0: u1,
-                padding: u26,
-            }),
-            ///  DMA_OUT_CONF1_CH0_REG.
-            OUT_CONF1_CH0: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                OUT_CHECK_OWNER_CH0: u1,
-                padding: u19,
-            }),
-            ///  DMA_OUTFIFO_STATUS_CH0_REG.
-            OUTFIFO_STATUS_CH0: mmio.Mmio(packed struct(u32) {
-                ///  L1 Tx FIFO full signal for Tx channel 0.
-                OUTFIFO_FULL_CH0: u1,
-                ///  L1 Tx FIFO empty signal for Tx channel 0.
-                OUTFIFO_EMPTY_CH0: u1,
-                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 0.
-                OUTFIFO_CNT_CH0: u6,
-                reserved23: u15,
-                ///  reserved
-                OUT_REMAIN_UNDER_1B_CH0: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_2B_CH0: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_3B_CH0: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_4B_CH0: u1,
-                padding: u5,
-            }),
-            ///  DMA_OUT_PUSH_CH0_REG.
-            OUT_PUSH_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data that need to be pushed into DMA FIFO.
-                OUTFIFO_WDATA_CH0: u9,
-                ///  Set this bit to push data into DMA FIFO.
-                OUTFIFO_PUSH_CH0: u1,
-                padding: u22,
-            }),
-            ///  DMA_OUT_LINK_CH0_REG.
-            OUT_LINK_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
-                OUTLINK_ADDR_CH0: u20,
-                ///  Set this bit to stop dealing with the outlink descriptors.
-                OUTLINK_STOP_CH0: u1,
-                ///  Set this bit to start dealing with the outlink descriptors.
-                OUTLINK_START_CH0: u1,
-                ///  Set this bit to restart a new outlink from the last address.
-                OUTLINK_RESTART_CH0: u1,
-                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
-                OUTLINK_PARK_CH0: u1,
-                padding: u8,
-            }),
-            ///  DMA_OUT_STATE_CH0_REG.
-            OUT_STATE_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current outlink descriptor's address.
-                OUTLINK_DSCR_ADDR_CH0: u18,
-                ///  reserved
-                OUT_DSCR_STATE_CH0: u2,
-                ///  reserved
-                OUT_STATE_CH0: u3,
-                padding: u9,
-            }),
-            ///  DMA_OUT_EOF_DES_ADDR_CH0_REG.
-            OUT_EOF_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
-                OUT_EOF_DES_ADDR_CH0: u32,
-            }),
-            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH0_REG.
-            OUT_EOF_BFR_DES_ADDR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
-                OUT_EOF_BFR_DES_ADDR_CH0: u32,
-            }),
-            ///  DMA_OUT_DSCR_CH0_REG.
-            OUT_DSCR_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current outlink descriptor y.
-                OUTLINK_DSCR_CH0: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF0_CH0_REG.
-            OUT_DSCR_BF0_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last outlink descriptor y-1.
-                OUTLINK_DSCR_BF0_CH0: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF1_CH0_REG.
-            OUT_DSCR_BF1_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                OUTLINK_DSCR_BF1_CH0: u32,
-            }),
-            ///  DMA_OUT_PRI_CH0_REG.
-            OUT_PRI_CH0: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Tx channel 0. The larger of the value, the higher of the priority.
-                TX_PRI_CH0: u4,
-                padding: u28,
-            }),
-            ///  DMA_OUT_PERI_SEL_CH0_REG.
-            OUT_PERI_SEL_CH0: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Tx channel 0. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_OUT_SEL_CH0: u6,
-                padding: u26,
-            }),
-            reserved304: [44]u8,
-            ///  DMA_IN_CONF0_CH1_REG.
-            IN_CONF0_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 1 Rx FSM and Rx FIFO pointer.
-                IN_RST_CH1: u1,
-                ///  reserved
-                IN_LOOP_TEST_CH1: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 1 reading link descriptor when accessing internal SRAM.
-                INDSCR_BURST_EN_CH1: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 1 receiving data when accessing internal SRAM.
-                IN_DATA_BURST_EN_CH1: u1,
-                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
-                MEM_TRANS_EN_CH1: u1,
-                padding: u27,
-            }),
-            ///  DMA_IN_CONF1_CH1_REG.
-            IN_CONF1_CH1: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                IN_CHECK_OWNER_CH1: u1,
-                padding: u19,
-            }),
-            ///  DMA_INFIFO_STATUS_CH1_REG.
-            INFIFO_STATUS_CH1: mmio.Mmio(packed struct(u32) {
-                ///  L1 Rx FIFO full signal for Rx channel 1.
-                INFIFO_FULL_CH1: u1,
-                ///  L1 Rx FIFO empty signal for Rx channel 1.
-                INFIFO_EMPTY_CH1: u1,
-                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 1.
-                INFIFO_CNT_CH1: u6,
-                reserved23: u15,
-                ///  reserved
-                IN_REMAIN_UNDER_1B_CH1: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_2B_CH1: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_3B_CH1: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_4B_CH1: u1,
-                ///  reserved
-                IN_BUF_HUNGRY_CH1: u1,
-                padding: u4,
-            }),
-            ///  DMA_IN_POP_CH1_REG.
-            IN_POP_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data popping from DMA FIFO.
-                INFIFO_RDATA_CH1: u12,
-                ///  Set this bit to pop data from DMA FIFO.
-                INFIFO_POP_CH1: u1,
-                padding: u19,
-            }),
-            ///  DMA_IN_LINK_CH1_REG.
-            IN_LINK_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
-                INLINK_ADDR_CH1: u20,
-                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
-                INLINK_AUTO_RET_CH1: u1,
-                ///  Set this bit to stop dealing with the inlink descriptors.
-                INLINK_STOP_CH1: u1,
-                ///  Set this bit to start dealing with the inlink descriptors.
-                INLINK_START_CH1: u1,
-                ///  Set this bit to mount a new inlink descriptor.
-                INLINK_RESTART_CH1: u1,
-                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
-                INLINK_PARK_CH1: u1,
-                padding: u7,
-            }),
-            ///  DMA_IN_STATE_CH1_REG.
-            IN_STATE_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current inlink descriptor's address.
-                INLINK_DSCR_ADDR_CH1: u18,
-                ///  reserved
-                IN_DSCR_STATE_CH1: u2,
-                ///  reserved
-                IN_STATE_CH1: u3,
-                padding: u9,
-            }),
-            ///  DMA_IN_SUC_EOF_DES_ADDR_CH1_REG.
-            IN_SUC_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
-                IN_SUC_EOF_DES_ADDR_CH1: u32,
-            }),
-            ///  DMA_IN_ERR_EOF_DES_ADDR_CH1_REG.
-            IN_ERR_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
-                IN_ERR_EOF_DES_ADDR_CH1: u32,
-            }),
-            ///  DMA_IN_DSCR_CH1_REG.
-            IN_DSCR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current inlink descriptor x.
-                INLINK_DSCR_CH1: u32,
-            }),
-            ///  DMA_IN_DSCR_BF0_CH1_REG.
-            IN_DSCR_BF0_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last inlink descriptor x-1.
-                INLINK_DSCR_BF0_CH1: u32,
-            }),
-            ///  DMA_IN_DSCR_BF1_CH1_REG.
-            IN_DSCR_BF1_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                INLINK_DSCR_BF1_CH1: u32,
-            }),
-            ///  DMA_IN_PRI_CH1_REG.
-            IN_PRI_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Rx channel 1. The larger of the value, the higher of the priority.
-                RX_PRI_CH1: u4,
-                padding: u28,
-            }),
-            ///  DMA_IN_PERI_SEL_CH1_REG.
-            IN_PERI_SEL_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Rx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_IN_SEL_CH1: u6,
-                padding: u26,
-            }),
-            reserved400: [44]u8,
-            ///  DMA_OUT_CONF0_CH1_REG.
-            OUT_CONF0_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 1 Tx FSM and Tx FIFO pointer.
-                OUT_RST_CH1: u1,
-                ///  reserved
-                OUT_LOOP_TEST_CH1: u1,
-                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
-                OUT_AUTO_WRBACK_CH1: u1,
-                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 1 is generated when data need to transmit has been popped from FIFO in DMA
-                OUT_EOF_MODE_CH1: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 reading link descriptor when accessing internal SRAM.
-                OUTDSCR_BURST_EN_CH1: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 1 transmitting data when accessing internal SRAM.
-                OUT_DATA_BURST_EN_CH1: u1,
-                padding: u26,
-            }),
-            ///  DMA_OUT_CONF1_CH1_REG.
-            OUT_CONF1_CH1: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                OUT_CHECK_OWNER_CH1: u1,
-                padding: u19,
-            }),
-            ///  DMA_OUTFIFO_STATUS_CH1_REG.
-            OUTFIFO_STATUS_CH1: mmio.Mmio(packed struct(u32) {
-                ///  L1 Tx FIFO full signal for Tx channel 1.
-                OUTFIFO_FULL_CH1: u1,
-                ///  L1 Tx FIFO empty signal for Tx channel 1.
-                OUTFIFO_EMPTY_CH1: u1,
-                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 1.
-                OUTFIFO_CNT_CH1: u6,
-                reserved23: u15,
-                ///  reserved
-                OUT_REMAIN_UNDER_1B_CH1: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_2B_CH1: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_3B_CH1: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_4B_CH1: u1,
-                padding: u5,
-            }),
-            ///  DMA_OUT_PUSH_CH1_REG.
-            OUT_PUSH_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data that need to be pushed into DMA FIFO.
-                OUTFIFO_WDATA_CH1: u9,
-                ///  Set this bit to push data into DMA FIFO.
-                OUTFIFO_PUSH_CH1: u1,
-                padding: u22,
-            }),
-            ///  DMA_OUT_LINK_CH1_REG.
-            OUT_LINK_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
-                OUTLINK_ADDR_CH1: u20,
-                ///  Set this bit to stop dealing with the outlink descriptors.
-                OUTLINK_STOP_CH1: u1,
-                ///  Set this bit to start dealing with the outlink descriptors.
-                OUTLINK_START_CH1: u1,
-                ///  Set this bit to restart a new outlink from the last address.
-                OUTLINK_RESTART_CH1: u1,
-                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
-                OUTLINK_PARK_CH1: u1,
-                padding: u8,
-            }),
-            ///  DMA_OUT_STATE_CH1_REG.
-            OUT_STATE_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current outlink descriptor's address.
-                OUTLINK_DSCR_ADDR_CH1: u18,
-                ///  reserved
-                OUT_DSCR_STATE_CH1: u2,
-                ///  reserved
-                OUT_STATE_CH1: u3,
-                padding: u9,
-            }),
-            ///  DMA_OUT_EOF_DES_ADDR_CH1_REG.
-            OUT_EOF_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
-                OUT_EOF_DES_ADDR_CH1: u32,
-            }),
-            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH1_REG.
-            OUT_EOF_BFR_DES_ADDR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
-                OUT_EOF_BFR_DES_ADDR_CH1: u32,
-            }),
-            ///  DMA_OUT_DSCR_CH1_REG.
-            OUT_DSCR_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current outlink descriptor y.
-                OUTLINK_DSCR_CH1: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF0_CH1_REG.
-            OUT_DSCR_BF0_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last outlink descriptor y-1.
-                OUTLINK_DSCR_BF0_CH1: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF1_CH1_REG.
-            OUT_DSCR_BF1_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                OUTLINK_DSCR_BF1_CH1: u32,
-            }),
-            ///  DMA_OUT_PRI_CH1_REG.
-            OUT_PRI_CH1: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Tx channel 1. The larger of the value, the higher of the priority.
-                TX_PRI_CH1: u4,
-                padding: u28,
-            }),
-            ///  DMA_OUT_PERI_SEL_CH1_REG.
-            OUT_PERI_SEL_CH1: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Tx channel 1. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_OUT_SEL_CH1: u6,
-                padding: u26,
-            }),
-            reserved496: [44]u8,
-            ///  DMA_IN_CONF0_CH2_REG.
-            IN_CONF0_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 2 Rx FSM and Rx FIFO pointer.
-                IN_RST_CH2: u1,
-                ///  reserved
-                IN_LOOP_TEST_CH2: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 2 reading link descriptor when accessing internal SRAM.
-                INDSCR_BURST_EN_CH2: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Rx channel 2 receiving data when accessing internal SRAM.
-                IN_DATA_BURST_EN_CH2: u1,
-                ///  Set this bit 1 to enable automatic transmitting data from memory to memory via DMA.
-                MEM_TRANS_EN_CH2: u1,
-                padding: u27,
-            }),
-            ///  DMA_IN_CONF1_CH2_REG.
-            IN_CONF1_CH2: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                IN_CHECK_OWNER_CH2: u1,
-                padding: u19,
-            }),
-            ///  DMA_INFIFO_STATUS_CH2_REG.
-            INFIFO_STATUS_CH2: mmio.Mmio(packed struct(u32) {
-                ///  L1 Rx FIFO full signal for Rx channel 2.
-                INFIFO_FULL_CH2: u1,
-                ///  L1 Rx FIFO empty signal for Rx channel 2.
-                INFIFO_EMPTY_CH2: u1,
-                ///  The register stores the byte number of the data in L1 Rx FIFO for Rx channel 2.
-                INFIFO_CNT_CH2: u6,
-                reserved23: u15,
-                ///  reserved
-                IN_REMAIN_UNDER_1B_CH2: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_2B_CH2: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_3B_CH2: u1,
-                ///  reserved
-                IN_REMAIN_UNDER_4B_CH2: u1,
-                ///  reserved
-                IN_BUF_HUNGRY_CH2: u1,
-                padding: u4,
-            }),
-            ///  DMA_IN_POP_CH2_REG.
-            IN_POP_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data popping from DMA FIFO.
-                INFIFO_RDATA_CH2: u12,
-                ///  Set this bit to pop data from DMA FIFO.
-                INFIFO_POP_CH2: u1,
-                padding: u19,
-            }),
-            ///  DMA_IN_LINK_CH2_REG.
-            IN_LINK_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first inlink descriptor's address.
-                INLINK_ADDR_CH2: u20,
-                ///  Set this bit to return to current inlink descriptor's address, when there are some errors in current receiving data.
-                INLINK_AUTO_RET_CH2: u1,
-                ///  Set this bit to stop dealing with the inlink descriptors.
-                INLINK_STOP_CH2: u1,
-                ///  Set this bit to start dealing with the inlink descriptors.
-                INLINK_START_CH2: u1,
-                ///  Set this bit to mount a new inlink descriptor.
-                INLINK_RESTART_CH2: u1,
-                ///  1: the inlink descriptor's FSM is in idle state. 0: the inlink descriptor's FSM is working.
-                INLINK_PARK_CH2: u1,
-                padding: u7,
-            }),
-            ///  DMA_IN_STATE_CH2_REG.
-            IN_STATE_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current inlink descriptor's address.
-                INLINK_DSCR_ADDR_CH2: u18,
-                ///  reserved
-                IN_DSCR_STATE_CH2: u2,
-                ///  reserved
-                IN_STATE_CH2: u3,
-                padding: u9,
-            }),
-            ///  DMA_IN_SUC_EOF_DES_ADDR_CH2_REG.
-            IN_SUC_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when the EOF bit in this descriptor is 1.
-                IN_SUC_EOF_DES_ADDR_CH2: u32,
-            }),
-            ///  DMA_IN_ERR_EOF_DES_ADDR_CH2_REG.
-            IN_ERR_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the inlink descriptor when there are some errors in current receiving data. Only used when peripheral is UHCI0.
-                IN_ERR_EOF_DES_ADDR_CH2: u32,
-            }),
-            ///  DMA_IN_DSCR_CH2_REG.
-            IN_DSCR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current inlink descriptor x.
-                INLINK_DSCR_CH2: u32,
-            }),
-            ///  DMA_IN_DSCR_BF0_CH2_REG.
-            IN_DSCR_BF0_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last inlink descriptor x-1.
-                INLINK_DSCR_BF0_CH2: u32,
-            }),
-            ///  DMA_IN_DSCR_BF1_CH2_REG.
-            IN_DSCR_BF1_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                INLINK_DSCR_BF1_CH2: u32,
-            }),
-            ///  DMA_IN_PRI_CH2_REG.
-            IN_PRI_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Rx channel 2. The larger of the value, the higher of the priority.
-                RX_PRI_CH2: u4,
-                padding: u28,
-            }),
-            ///  DMA_IN_PERI_SEL_CH2_REG.
-            IN_PERI_SEL_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Rx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_IN_SEL_CH2: u6,
-                padding: u26,
-            }),
-            reserved592: [44]u8,
-            ///  DMA_OUT_CONF0_CH2_REG.
-            OUT_CONF0_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to reset DMA channel 2 Tx FSM and Tx FIFO pointer.
-                OUT_RST_CH2: u1,
-                ///  reserved
-                OUT_LOOP_TEST_CH2: u1,
-                ///  Set this bit to enable automatic outlink-writeback when all the data in tx buffer has been transmitted.
-                OUT_AUTO_WRBACK_CH2: u1,
-                ///  EOF flag generation mode when transmitting data. 1: EOF flag for Tx channel 2 is generated when data need to transmit has been popped from FIFO in DMA
-                OUT_EOF_MODE_CH2: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 reading link descriptor when accessing internal SRAM.
-                OUTDSCR_BURST_EN_CH2: u1,
-                ///  Set this bit to 1 to enable INCR burst transfer for Tx channel 2 transmitting data when accessing internal SRAM.
-                OUT_DATA_BURST_EN_CH2: u1,
-                padding: u26,
-            }),
-            ///  DMA_OUT_CONF1_CH2_REG.
-            OUT_CONF1_CH2: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  Set this bit to enable checking the owner attribute of the link descriptor.
-                OUT_CHECK_OWNER_CH2: u1,
-                padding: u19,
-            }),
-            ///  DMA_OUTFIFO_STATUS_CH2_REG.
-            OUTFIFO_STATUS_CH2: mmio.Mmio(packed struct(u32) {
-                ///  L1 Tx FIFO full signal for Tx channel 2.
-                OUTFIFO_FULL_CH2: u1,
-                ///  L1 Tx FIFO empty signal for Tx channel 2.
-                OUTFIFO_EMPTY_CH2: u1,
-                ///  The register stores the byte number of the data in L1 Tx FIFO for Tx channel 2.
-                OUTFIFO_CNT_CH2: u6,
-                reserved23: u15,
-                ///  reserved
-                OUT_REMAIN_UNDER_1B_CH2: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_2B_CH2: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_3B_CH2: u1,
-                ///  reserved
-                OUT_REMAIN_UNDER_4B_CH2: u1,
-                padding: u5,
-            }),
-            ///  DMA_OUT_PUSH_CH2_REG.
-            OUT_PUSH_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the data that need to be pushed into DMA FIFO.
-                OUTFIFO_WDATA_CH2: u9,
-                ///  Set this bit to push data into DMA FIFO.
-                OUTFIFO_PUSH_CH2: u1,
-                padding: u22,
-            }),
-            ///  DMA_OUT_LINK_CH2_REG.
-            OUT_LINK_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the 20 least significant bits of the first outlink descriptor's address.
-                OUTLINK_ADDR_CH2: u20,
-                ///  Set this bit to stop dealing with the outlink descriptors.
-                OUTLINK_STOP_CH2: u1,
-                ///  Set this bit to start dealing with the outlink descriptors.
-                OUTLINK_START_CH2: u1,
-                ///  Set this bit to restart a new outlink from the last address.
-                OUTLINK_RESTART_CH2: u1,
-                ///  1: the outlink descriptor's FSM is in idle state. 0: the outlink descriptor's FSM is working.
-                OUTLINK_PARK_CH2: u1,
-                padding: u8,
-            }),
-            ///  DMA_OUT_STATE_CH2_REG.
-            OUT_STATE_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the current outlink descriptor's address.
-                OUTLINK_DSCR_ADDR_CH2: u18,
-                ///  reserved
-                OUT_DSCR_STATE_CH2: u2,
-                ///  reserved
-                OUT_STATE_CH2: u3,
-                padding: u9,
-            }),
-            ///  DMA_OUT_EOF_DES_ADDR_CH2_REG.
-            OUT_EOF_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor when the EOF bit in this descriptor is 1.
-                OUT_EOF_DES_ADDR_CH2: u32,
-            }),
-            ///  DMA_OUT_EOF_BFR_DES_ADDR_CH2_REG.
-            OUT_EOF_BFR_DES_ADDR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the address of the outlink descriptor before the last outlink descriptor.
-                OUT_EOF_BFR_DES_ADDR_CH2: u32,
-            }),
-            ///  DMA_OUT_DSCR_CH2_REG.
-            OUT_DSCR_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the current outlink descriptor y.
-                OUTLINK_DSCR_CH2: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF0_CH2_REG.
-            OUT_DSCR_BF0_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the last outlink descriptor y-1.
-                OUTLINK_DSCR_BF0_CH2: u32,
-            }),
-            ///  DMA_OUT_DSCR_BF1_CH2_REG.
-            OUT_DSCR_BF1_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The address of the second-to-last inlink descriptor x-2.
-                OUTLINK_DSCR_BF1_CH2: u32,
-            }),
-            ///  DMA_OUT_PRI_CH2_REG.
-            OUT_PRI_CH2: mmio.Mmio(packed struct(u32) {
-                ///  The priority of Tx channel 2. The larger of the value, the higher of the priority.
-                TX_PRI_CH2: u4,
-                padding: u28,
-            }),
-            ///  DMA_OUT_PERI_SEL_CH2_REG.
-            OUT_PERI_SEL_CH2: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to select peripheral for Tx channel 2. 0:SPI2. 1: reserved. 2: UHCI0. 3: I2S0. 4: reserved. 5: reserved. 6: AES. 7: SHA. 8: ADC_DAC.
-                PERI_OUT_SEL_CH2: u6,
-                padding: u26,
-            }),
-        };
-
-        ///  Digital Signature
-        pub const DS = extern struct {
-            ///  memory that stores Y
-            Y_MEM: [512]u8,
-            ///  memory that stores M
-            M_MEM: [512]u8,
-            ///  memory that stores Rb
-            RB_MEM: [512]u8,
-            ///  memory that stores BOX
-            BOX_MEM: [48]u8,
-            reserved2048: [464]u8,
-            ///  memory that stores X
-            X_MEM: [512]u8,
-            ///  memory that stores Z
-            Z_MEM: [512]u8,
-            reserved3584: [512]u8,
-            ///  DS start control register
-            SET_START: mmio.Mmio(packed struct(u32) {
-                ///  set this bit to start DS operation.
-                SET_START: u1,
-                padding: u31,
-            }),
-            ///  DS continue control register
-            SET_CONTINUE: mmio.Mmio(packed struct(u32) {
-                ///  set this bit to continue DS operation.
-                SET_CONTINUE: u1,
-                padding: u31,
-            }),
-            ///  DS finish control register
-            SET_FINISH: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to finish DS process.
-                SET_FINISH: u1,
-                padding: u31,
-            }),
-            ///  DS query busy register
-            QUERY_BUSY: mmio.Mmio(packed struct(u32) {
-                ///  digital signature state. 1'b0: idle, 1'b1: busy
-                QUERY_BUSY: u1,
-                padding: u31,
-            }),
-            ///  DS query key-wrong counter register
-            QUERY_KEY_WRONG: mmio.Mmio(packed struct(u32) {
-                ///  digital signature key wrong counter
-                QUERY_KEY_WRONG: u4,
-                padding: u28,
-            }),
-            ///  DS query check result register
-            QUERY_CHECK: mmio.Mmio(packed struct(u32) {
-                ///  MD checkout result. 1'b0: MD check pass, 1'b1: MD check fail
-                MD_ERROR: u1,
-                ///  padding checkout result. 1'b0: a good padding, 1'b1: a bad padding
-                PADDING_BAD: u1,
-                padding: u30,
-            }),
-            reserved3616: [8]u8,
-            ///  DS version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  ds version information
-                DATE: u30,
-                padding: u2,
-            }),
-        };
-
-        ///  eFuse Controller
-        pub const EFUSE = extern struct {
-            ///  Register 0 that stores data to be programmed.
-            PGM_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 0th 32-bit data to be programmed.
-                PGM_DATA_0: u32,
-            }),
-            ///  Register 1 that stores data to be programmed.
-            PGM_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 1st 32-bit data to be programmed.
-                PGM_DATA_1: u32,
-            }),
-            ///  Register 2 that stores data to be programmed.
-            PGM_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 2nd 32-bit data to be programmed.
-                PGM_DATA_2: u32,
-            }),
-            ///  Register 3 that stores data to be programmed.
-            PGM_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 3rd 32-bit data to be programmed.
-                PGM_DATA_3: u32,
-            }),
-            ///  Register 4 that stores data to be programmed.
-            PGM_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 4th 32-bit data to be programmed.
-                PGM_DATA_4: u32,
-            }),
-            ///  Register 5 that stores data to be programmed.
-            PGM_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 5th 32-bit data to be programmed.
-                PGM_DATA_5: u32,
-            }),
-            ///  Register 6 that stores data to be programmed.
-            PGM_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 6th 32-bit data to be programmed.
-                PGM_DATA_6: u32,
-            }),
-            ///  Register 7 that stores data to be programmed.
-            PGM_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 7th 32-bit data to be programmed.
-                PGM_DATA_7: u32,
-            }),
-            ///  Register 0 that stores the RS code to be programmed.
-            PGM_CHECK_VALUE0: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 0th 32-bit RS code to be programmed.
-                PGM_RS_DATA_0: u32,
-            }),
-            ///  Register 1 that stores the RS code to be programmed.
-            PGM_CHECK_VALUE1: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 1st 32-bit RS code to be programmed.
-                PGM_RS_DATA_1: u32,
-            }),
-            ///  Register 2 that stores the RS code to be programmed.
-            PGM_CHECK_VALUE2: mmio.Mmio(packed struct(u32) {
-                ///  The content of the 2nd 32-bit RS code to be programmed.
-                PGM_RS_DATA_2: u32,
-            }),
-            ///  BLOCK0 data register 0.
-            RD_WR_DIS: mmio.Mmio(packed struct(u32) {
-                ///  Disable programming of individual eFuses.
-                WR_DIS: u32,
-            }),
-            ///  BLOCK0 data register 1.
-            RD_REPEAT_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to disable reading from BlOCK4-10.
-                RD_DIS: u7,
-                ///  Set this bit to disable boot from RTC RAM.
-                DIS_RTC_RAM_BOOT: u1,
-                ///  Set this bit to disable Icache.
-                DIS_ICACHE: u1,
-                ///  Set this bit to disable function of usb switch to jtag in module of usb device.
-                DIS_USB_JTAG: u1,
-                ///  Set this bit to disable Icache in download mode (boot_mode[3:0] is 0, 1, 2, 3, 6, 7).
-                DIS_DOWNLOAD_ICACHE: u1,
-                ///  Set this bit to disable usb device.
-                DIS_USB_DEVICE: u1,
-                ///  Set this bit to disable the function that forces chip into download mode.
-                DIS_FORCE_DOWNLOAD: u1,
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED6: u1,
-                ///  Set this bit to disable CAN function.
-                DIS_CAN: u1,
-                ///  Set this bit to enable selection between usb_to_jtag and pad_to_jtag through strapping gpio10 when both reg_dis_usb_jtag and reg_dis_pad_jtag are equal to 0.
-                JTAG_SEL_ENABLE: u1,
-                ///  Set these bits to disable JTAG in the soft way (odd number 1 means disable ). JTAG can be enabled in HMAC module.
-                SOFT_DIS_JTAG: u3,
-                ///  Set this bit to disable JTAG in the hard way. JTAG is disabled permanently.
-                DIS_PAD_JTAG: u1,
-                ///  Set this bit to disable flash encryption when in download boot modes.
-                DIS_DOWNLOAD_MANUAL_ENCRYPT: u1,
-                ///  Controls single-end input threshold vrefh, 1.76 V to 2 V with step of 80 mV, stored in eFuse.
-                USB_DREFH: u2,
-                ///  Controls single-end input threshold vrefl, 0.8 V to 1.04 V with step of 80 mV, stored in eFuse.
-                USB_DREFL: u2,
-                ///  Set this bit to exchange USB D+ and D- pins.
-                USB_EXCHG_PINS: u1,
-                ///  Set this bit to vdd spi pin function as gpio.
-                VDD_SPI_AS_GPIO: u1,
-                ///  Enable btlc gpio.
-                BTLC_GPIO_ENABLE: u2,
-                ///  Set this bit to enable power glitch function.
-                POWERGLITCH_EN: u1,
-                ///  Sample delay configuration of power glitch.
-                POWER_GLITCH_DSENSE: u2,
-            }),
-            ///  BLOCK0 data register 2.
-            RD_REPEAT_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED2: u16,
-                ///  Selects RTC watchdog timeout threshold, in unit of slow clock cycle. 0: 40000. 1: 80000. 2: 160000. 3:320000.
-                WDT_DELAY_SEL: u2,
-                ///  Set this bit to enable SPI boot encrypt/decrypt. Odd number of 1: enable. even number of 1: disable.
-                SPI_BOOT_CRYPT_CNT: u3,
-                ///  Set this bit to enable revoking first secure boot key.
-                SECURE_BOOT_KEY_REVOKE0: u1,
-                ///  Set this bit to enable revoking second secure boot key.
-                SECURE_BOOT_KEY_REVOKE1: u1,
-                ///  Set this bit to enable revoking third secure boot key.
-                SECURE_BOOT_KEY_REVOKE2: u1,
-                ///  Purpose of Key0.
-                KEY_PURPOSE_0: u4,
-                ///  Purpose of Key1.
-                KEY_PURPOSE_1: u4,
-            }),
-            ///  BLOCK0 data register 3.
-            RD_REPEAT_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Purpose of Key2.
-                KEY_PURPOSE_2: u4,
-                ///  Purpose of Key3.
-                KEY_PURPOSE_3: u4,
-                ///  Purpose of Key4.
-                KEY_PURPOSE_4: u4,
-                ///  Purpose of Key5.
-                KEY_PURPOSE_5: u4,
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED3: u4,
-                ///  Set this bit to enable secure boot.
-                SECURE_BOOT_EN: u1,
-                ///  Set this bit to enable revoking aggressive secure boot.
-                SECURE_BOOT_AGGRESSIVE_REVOKE: u1,
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED0: u6,
-                ///  Configures flash waiting time after power-up, in unit of ms. If the value is less than 15, the waiting time is the configurable value; Otherwise, the waiting time is twice the configurable value.
-                FLASH_TPUW: u4,
-            }),
-            ///  BLOCK0 data register 4.
-            RD_REPEAT_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to disable download mode (boot_mode[3:0] = 0, 1, 2, 3, 6, 7).
-                DIS_DOWNLOAD_MODE: u1,
-                ///  Set this bit to disable Legacy SPI boot mode (boot_mode[3:0] = 4).
-                DIS_LEGACY_SPI_BOOT: u1,
-                ///  Selectes the default UART print channel. 0: UART0. 1: UART1.
-                UART_PRINT_CHANNEL: u1,
-                ///  Set ECC mode in ROM, 0: ROM would Enable Flash ECC 16to18 byte mode. 1:ROM would use 16to17 byte mode.
-                FLASH_ECC_MODE: u1,
-                ///  Set this bit to disable UART download mode through USB.
-                DIS_USB_DOWNLOAD_MODE: u1,
-                ///  Set this bit to enable secure UART download mode.
-                ENABLE_SECURITY_DOWNLOAD: u1,
-                ///  Set the default UARTboot message output mode. 00: Enabled. 01: Enabled when GPIO8 is low at reset. 10: Enabled when GPIO8 is high at reset. 11:disabled.
-                UART_PRINT_CONTROL: u2,
-                ///  GPIO33-GPIO37 power supply selection in ROM code. 0: VDD3P3_CPU. 1: VDD_SPI.
-                PIN_POWER_SELECTION: u1,
-                ///  Set the maximum lines of SPI flash. 0: four lines. 1: eight lines.
-                FLASH_TYPE: u1,
-                ///  Set Flash page size.
-                FLASH_PAGE_SIZE: u2,
-                ///  Set 1 to enable ECC for flash boot.
-                FLASH_ECC_EN: u1,
-                ///  Set this bit to force ROM code to send a resume command during SPI boot.
-                FORCE_SEND_RESUME: u1,
-                ///  Secure version (used by ESP-IDF anti-rollback feature).
-                SECURE_VERSION: u16,
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED1: u2,
-            }),
-            ///  BLOCK0 data register 5.
-            RD_REPEAT_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Reserved (used for four backups method).
-                RPT4_RESERVED4: u24,
-                padding: u8,
-            }),
-            ///  BLOCK1 data register 0.
-            RD_MAC_SPI_SYS_0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the low 32 bits of MAC address.
-                MAC_0: u32,
-            }),
-            ///  BLOCK1 data register 1.
-            RD_MAC_SPI_SYS_1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the high 16 bits of MAC address.
-                MAC_1: u16,
-                ///  Stores the zeroth part of SPI_PAD_CONF.
-                SPI_PAD_CONF_0: u16,
-            }),
-            ///  BLOCK1 data register 2.
-            RD_MAC_SPI_SYS_2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first part of SPI_PAD_CONF.
-                SPI_PAD_CONF_1: u32,
-            }),
-            ///  BLOCK1 data register 3.
-            RD_MAC_SPI_SYS_3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second part of SPI_PAD_CONF.
-                SPI_PAD_CONF_2: u18,
-                ///  Stores the fist 14 bits of the zeroth part of system data.
-                SYS_DATA_PART0_0: u14,
-            }),
-            ///  BLOCK1 data register 4.
-            RD_MAC_SPI_SYS_4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fist 32 bits of the zeroth part of system data.
-                SYS_DATA_PART0_1: u32,
-            }),
-            ///  BLOCK1 data register 5.
-            RD_MAC_SPI_SYS_5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of the zeroth part of system data.
-                SYS_DATA_PART0_2: u32,
-            }),
-            ///  Register 0 of BLOCK2 (system).
-            RD_SYS_PART1_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of the first part of system data.
-                SYS_DATA_PART1_0: u32,
-            }),
-            ///  Register 1 of BLOCK2 (system).
-            RD_SYS_PART1_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of the first part of system data.
-                SYS_DATA_PART1_1: u32,
-            }),
-            ///  Register 2 of BLOCK2 (system).
-            RD_SYS_PART1_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of the first part of system data.
-                SYS_DATA_PART1_2: u32,
-            }),
-            ///  Register 3 of BLOCK2 (system).
-            RD_SYS_PART1_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of the first part of system data.
-                SYS_DATA_PART1_3: u32,
-            }),
-            ///  Register 4 of BLOCK2 (system).
-            RD_SYS_PART1_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of the first part of system data.
-                SYS_DATA_PART1_4: u32,
-            }),
-            ///  Register 5 of BLOCK2 (system).
-            RD_SYS_PART1_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of the first part of system data.
-                SYS_DATA_PART1_5: u32,
-            }),
-            ///  Register 6 of BLOCK2 (system).
-            RD_SYS_PART1_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of the first part of system data.
-                SYS_DATA_PART1_6: u32,
-            }),
-            ///  Register 7 of BLOCK2 (system).
-            RD_SYS_PART1_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of the first part of system data.
-                SYS_DATA_PART1_7: u32,
-            }),
-            ///  Register 0 of BLOCK3 (user).
-            RD_USR_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of BLOCK3 (user).
-                USR_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK3 (user).
-            RD_USR_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of BLOCK3 (user).
-                USR_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK3 (user).
-            RD_USR_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of BLOCK3 (user).
-                USR_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK3 (user).
-            RD_USR_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of BLOCK3 (user).
-                USR_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK3 (user).
-            RD_USR_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of BLOCK3 (user).
-                USR_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK3 (user).
-            RD_USR_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of BLOCK3 (user).
-                USR_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK3 (user).
-            RD_USR_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of BLOCK3 (user).
-                USR_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK3 (user).
-            RD_USR_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of BLOCK3 (user).
-                USR_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK4 (KEY0).
-            RD_KEY0_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY0.
-                KEY0_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK4 (KEY0).
-            RD_KEY0_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY0.
-                KEY0_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK4 (KEY0).
-            RD_KEY0_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY0.
-                KEY0_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK4 (KEY0).
-            RD_KEY0_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY0.
-                KEY0_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK4 (KEY0).
-            RD_KEY0_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY0.
-                KEY0_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK4 (KEY0).
-            RD_KEY0_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY0.
-                KEY0_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK4 (KEY0).
-            RD_KEY0_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY0.
-                KEY0_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK4 (KEY0).
-            RD_KEY0_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY0.
-                KEY0_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK5 (KEY1).
-            RD_KEY1_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY1.
-                KEY1_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK5 (KEY1).
-            RD_KEY1_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY1.
-                KEY1_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK5 (KEY1).
-            RD_KEY1_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY1.
-                KEY1_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK5 (KEY1).
-            RD_KEY1_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY1.
-                KEY1_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK5 (KEY1).
-            RD_KEY1_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY1.
-                KEY1_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK5 (KEY1).
-            RD_KEY1_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY1.
-                KEY1_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK5 (KEY1).
-            RD_KEY1_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY1.
-                KEY1_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK5 (KEY1).
-            RD_KEY1_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY1.
-                KEY1_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK6 (KEY2).
-            RD_KEY2_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY2.
-                KEY2_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK6 (KEY2).
-            RD_KEY2_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY2.
-                KEY2_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK6 (KEY2).
-            RD_KEY2_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY2.
-                KEY2_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK6 (KEY2).
-            RD_KEY2_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY2.
-                KEY2_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK6 (KEY2).
-            RD_KEY2_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY2.
-                KEY2_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK6 (KEY2).
-            RD_KEY2_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY2.
-                KEY2_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK6 (KEY2).
-            RD_KEY2_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY2.
-                KEY2_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK6 (KEY2).
-            RD_KEY2_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY2.
-                KEY2_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK7 (KEY3).
-            RD_KEY3_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY3.
-                KEY3_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK7 (KEY3).
-            RD_KEY3_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY3.
-                KEY3_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK7 (KEY3).
-            RD_KEY3_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY3.
-                KEY3_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK7 (KEY3).
-            RD_KEY3_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY3.
-                KEY3_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK7 (KEY3).
-            RD_KEY3_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY3.
-                KEY3_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK7 (KEY3).
-            RD_KEY3_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY3.
-                KEY3_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK7 (KEY3).
-            RD_KEY3_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY3.
-                KEY3_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK7 (KEY3).
-            RD_KEY3_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY3.
-                KEY3_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK8 (KEY4).
-            RD_KEY4_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY4.
-                KEY4_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK8 (KEY4).
-            RD_KEY4_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY4.
-                KEY4_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK8 (KEY4).
-            RD_KEY4_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY4.
-                KEY4_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK8 (KEY4).
-            RD_KEY4_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY4.
-                KEY4_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK8 (KEY4).
-            RD_KEY4_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY4.
-                KEY4_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK8 (KEY4).
-            RD_KEY4_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY4.
-                KEY4_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK8 (KEY4).
-            RD_KEY4_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY4.
-                KEY4_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK8 (KEY4).
-            RD_KEY4_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY4.
-                KEY4_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK9 (KEY5).
-            RD_KEY5_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the zeroth 32 bits of KEY5.
-                KEY5_DATA0: u32,
-            }),
-            ///  Register 1 of BLOCK9 (KEY5).
-            RD_KEY5_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the first 32 bits of KEY5.
-                KEY5_DATA1: u32,
-            }),
-            ///  Register 2 of BLOCK9 (KEY5).
-            RD_KEY5_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the second 32 bits of KEY5.
-                KEY5_DATA2: u32,
-            }),
-            ///  Register 3 of BLOCK9 (KEY5).
-            RD_KEY5_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the third 32 bits of KEY5.
-                KEY5_DATA3: u32,
-            }),
-            ///  Register 4 of BLOCK9 (KEY5).
-            RD_KEY5_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fourth 32 bits of KEY5.
-                KEY5_DATA4: u32,
-            }),
-            ///  Register 5 of BLOCK9 (KEY5).
-            RD_KEY5_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the fifth 32 bits of KEY5.
-                KEY5_DATA5: u32,
-            }),
-            ///  Register 6 of BLOCK9 (KEY5).
-            RD_KEY5_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the sixth 32 bits of KEY5.
-                KEY5_DATA6: u32,
-            }),
-            ///  Register 7 of BLOCK9 (KEY5).
-            RD_KEY5_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the seventh 32 bits of KEY5.
-                KEY5_DATA7: u32,
-            }),
-            ///  Register 0 of BLOCK10 (system).
-            RD_SYS_PART2_DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 0th 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_0: u32,
-            }),
-            ///  Register 1 of BLOCK9 (KEY5).
-            RD_SYS_PART2_DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 1st 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_1: u32,
-            }),
-            ///  Register 2 of BLOCK10 (system).
-            RD_SYS_PART2_DATA2: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 2nd 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_2: u32,
-            }),
-            ///  Register 3 of BLOCK10 (system).
-            RD_SYS_PART2_DATA3: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 3rd 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_3: u32,
-            }),
-            ///  Register 4 of BLOCK10 (system).
-            RD_SYS_PART2_DATA4: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 4th 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_4: u32,
-            }),
-            ///  Register 5 of BLOCK10 (system).
-            RD_SYS_PART2_DATA5: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 5th 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_5: u32,
-            }),
-            ///  Register 6 of BLOCK10 (system).
-            RD_SYS_PART2_DATA6: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 6th 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_6: u32,
-            }),
-            ///  Register 7 of BLOCK10 (system).
-            RD_SYS_PART2_DATA7: mmio.Mmio(packed struct(u32) {
-                ///  Stores the 7th 32 bits of the 2nd part of system data.
-                SYS_DATA_PART2_7: u32,
-            }),
-            ///  Programming error record register 0 of BLOCK0.
-            RD_REPEAT_ERR0: mmio.Mmio(packed struct(u32) {
-                ///  If any bit in RD_DIS is 1, then it indicates a programming error.
-                RD_DIS_ERR: u7,
-                ///  If DIS_RTC_RAM_BOOT is 1, then it indicates a programming error.
-                DIS_RTC_RAM_BOOT_ERR: u1,
-                ///  If DIS_ICACHE is 1, then it indicates a programming error.
-                DIS_ICACHE_ERR: u1,
-                ///  If DIS_USB_JTAG is 1, then it indicates a programming error.
-                DIS_USB_JTAG_ERR: u1,
-                ///  If DIS_DOWNLOAD_ICACHE is 1, then it indicates a programming error.
-                DIS_DOWNLOAD_ICACHE_ERR: u1,
-                ///  If DIS_USB_DEVICE is 1, then it indicates a programming error.
-                DIS_USB_DEVICE_ERR: u1,
-                ///  If DIS_FORCE_DOWNLOAD is 1, then it indicates a programming error.
-                DIS_FORCE_DOWNLOAD_ERR: u1,
-                ///  Reserved.
-                RPT4_RESERVED6_ERR: u1,
-                ///  If DIS_CAN is 1, then it indicates a programming error.
-                DIS_CAN_ERR: u1,
-                ///  If JTAG_SEL_ENABLE is 1, then it indicates a programming error.
-                JTAG_SEL_ENABLE_ERR: u1,
-                ///  If SOFT_DIS_JTAG is 1, then it indicates a programming error.
-                SOFT_DIS_JTAG_ERR: u3,
-                ///  If DIS_PAD_JTAG is 1, then it indicates a programming error.
-                DIS_PAD_JTAG_ERR: u1,
-                ///  If DIS_DOWNLOAD_MANUAL_ENCRYPT is 1, then it indicates a programming error.
-                DIS_DOWNLOAD_MANUAL_ENCRYPT_ERR: u1,
-                ///  If any bit in USB_DREFH is 1, then it indicates a programming error.
-                USB_DREFH_ERR: u2,
-                ///  If any bit in USB_DREFL is 1, then it indicates a programming error.
-                USB_DREFL_ERR: u2,
-                ///  If USB_EXCHG_PINS is 1, then it indicates a programming error.
-                USB_EXCHG_PINS_ERR: u1,
-                ///  If VDD_SPI_AS_GPIO is 1, then it indicates a programming error.
-                VDD_SPI_AS_GPIO_ERR: u1,
-                ///  If any bit in BTLC_GPIO_ENABLE is 1, then it indicates a programming error.
-                BTLC_GPIO_ENABLE_ERR: u2,
-                ///  If POWERGLITCH_EN is 1, then it indicates a programming error.
-                POWERGLITCH_EN_ERR: u1,
-                ///  If any bit in POWER_GLITCH_DSENSE is 1, then it indicates a programming error.
-                POWER_GLITCH_DSENSE_ERR: u2,
-            }),
-            ///  Programming error record register 1 of BLOCK0.
-            RD_REPEAT_ERR1: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                RPT4_RESERVED2_ERR: u16,
-                ///  If any bit in WDT_DELAY_SEL is 1, then it indicates a programming error.
-                WDT_DELAY_SEL_ERR: u2,
-                ///  If any bit in SPI_BOOT_CRYPT_CNT is 1, then it indicates a programming error.
-                SPI_BOOT_CRYPT_CNT_ERR: u3,
-                ///  If SECURE_BOOT_KEY_REVOKE0 is 1, then it indicates a programming error.
-                SECURE_BOOT_KEY_REVOKE0_ERR: u1,
-                ///  If SECURE_BOOT_KEY_REVOKE1 is 1, then it indicates a programming error.
-                SECURE_BOOT_KEY_REVOKE1_ERR: u1,
-                ///  If SECURE_BOOT_KEY_REVOKE2 is 1, then it indicates a programming error.
-                SECURE_BOOT_KEY_REVOKE2_ERR: u1,
-                ///  If any bit in KEY_PURPOSE_0 is 1, then it indicates a programming error.
-                KEY_PURPOSE_0_ERR: u4,
-                ///  If any bit in KEY_PURPOSE_1 is 1, then it indicates a programming error.
-                KEY_PURPOSE_1_ERR: u4,
-            }),
-            ///  Programming error record register 2 of BLOCK0.
-            RD_REPEAT_ERR2: mmio.Mmio(packed struct(u32) {
-                ///  If any bit in KEY_PURPOSE_2 is 1, then it indicates a programming error.
-                KEY_PURPOSE_2_ERR: u4,
-                ///  If any bit in KEY_PURPOSE_3 is 1, then it indicates a programming error.
-                KEY_PURPOSE_3_ERR: u4,
-                ///  If any bit in KEY_PURPOSE_4 is 1, then it indicates a programming error.
-                KEY_PURPOSE_4_ERR: u4,
-                ///  If any bit in KEY_PURPOSE_5 is 1, then it indicates a programming error.
-                KEY_PURPOSE_5_ERR: u4,
-                ///  Reserved.
-                RPT4_RESERVED3_ERR: u4,
-                ///  If SECURE_BOOT_EN is 1, then it indicates a programming error.
-                SECURE_BOOT_EN_ERR: u1,
-                ///  If SECURE_BOOT_AGGRESSIVE_REVOKE is 1, then it indicates a programming error.
-                SECURE_BOOT_AGGRESSIVE_REVOKE_ERR: u1,
-                ///  Reserved.
-                RPT4_RESERVED0_ERR: u6,
-                ///  If any bit in FLASH_TPUM is 1, then it indicates a programming error.
-                FLASH_TPUW_ERR: u4,
-            }),
-            ///  Programming error record register 3 of BLOCK0.
-            RD_REPEAT_ERR3: mmio.Mmio(packed struct(u32) {
-                ///  If DIS_DOWNLOAD_MODE is 1, then it indicates a programming error.
-                DIS_DOWNLOAD_MODE_ERR: u1,
-                ///  If DIS_LEGACY_SPI_BOOT is 1, then it indicates a programming error.
-                DIS_LEGACY_SPI_BOOT_ERR: u1,
-                ///  If UART_PRINT_CHANNEL is 1, then it indicates a programming error.
-                UART_PRINT_CHANNEL_ERR: u1,
-                ///  If FLASH_ECC_MODE is 1, then it indicates a programming error.
-                FLASH_ECC_MODE_ERR: u1,
-                ///  If DIS_USB_DOWNLOAD_MODE is 1, then it indicates a programming error.
-                DIS_USB_DOWNLOAD_MODE_ERR: u1,
-                ///  If ENABLE_SECURITY_DOWNLOAD is 1, then it indicates a programming error.
-                ENABLE_SECURITY_DOWNLOAD_ERR: u1,
-                ///  If any bit in UART_PRINT_CONTROL is 1, then it indicates a programming error.
-                UART_PRINT_CONTROL_ERR: u2,
-                ///  If PIN_POWER_SELECTION is 1, then it indicates a programming error.
-                PIN_POWER_SELECTION_ERR: u1,
-                ///  If FLASH_TYPE is 1, then it indicates a programming error.
-                FLASH_TYPE_ERR: u1,
-                ///  If any bits in FLASH_PAGE_SIZE is 1, then it indicates a programming error.
-                FLASH_PAGE_SIZE_ERR: u2,
-                ///  If FLASH_ECC_EN_ERR is 1, then it indicates a programming error.
-                FLASH_ECC_EN_ERR: u1,
-                ///  If FORCE_SEND_RESUME is 1, then it indicates a programming error.
-                FORCE_SEND_RESUME_ERR: u1,
-                ///  If any bit in SECURE_VERSION is 1, then it indicates a programming error.
-                SECURE_VERSION_ERR: u16,
-                ///  Reserved.
-                RPT4_RESERVED1_ERR: u2,
-            }),
-            reserved400: [4]u8,
-            ///  Programming error record register 4 of BLOCK0.
-            RD_REPEAT_ERR4: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                RPT4_RESERVED4_ERR: u24,
-                padding: u8,
-            }),
-            reserved448: [44]u8,
-            ///  Programming error record register 0 of BLOCK1-10.
-            RD_RS_ERR0: mmio.Mmio(packed struct(u32) {
-                ///  The value of this signal means the number of error bytes.
-                MAC_SPI_8M_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of MAC_SPI_8M is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
-                MAC_SPI_8M_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                SYS_PART1_NUM: u3,
-                ///  0: Means no failure and that the data of system part1 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
-                SYS_PART1_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                USR_DATA_ERR_NUM: u3,
-                ///  0: Means no failure and that the user data is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
-                USR_DATA_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                KEY0_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of key0 is reliable 1: Means that programming key0 failed and the number of error bytes is over 6.
-                KEY0_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                KEY1_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of key1 is reliable 1: Means that programming key1 failed and the number of error bytes is over 6.
-                KEY1_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                KEY2_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of key2 is reliable 1: Means that programming key2 failed and the number of error bytes is over 6.
-                KEY2_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                KEY3_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of key3 is reliable 1: Means that programming key3 failed and the number of error bytes is over 6.
-                KEY3_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                KEY4_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of key4 is reliable 1: Means that programming key4 failed and the number of error bytes is over 6.
-                KEY4_FAIL: u1,
-            }),
-            ///  Programming error record register 1 of BLOCK1-10.
-            RD_RS_ERR1: mmio.Mmio(packed struct(u32) {
-                ///  The value of this signal means the number of error bytes.
-                KEY5_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of KEY5 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
-                KEY5_FAIL: u1,
-                ///  The value of this signal means the number of error bytes.
-                SYS_PART2_ERR_NUM: u3,
-                ///  0: Means no failure and that the data of system part2 is reliable 1: Means that programming user data failed and the number of error bytes is over 6.
-                SYS_PART2_FAIL: u1,
-                padding: u24,
-            }),
-            ///  eFuse clcok configuration register.
-            CLK: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to force eFuse SRAM into power-saving mode.
-                EFUSE_MEM_FORCE_PD: u1,
-                ///  Set this bit and force to activate clock signal of eFuse SRAM.
-                MEM_CLK_FORCE_ON: u1,
-                ///  Set this bit to force eFuse SRAM into working mode.
-                EFUSE_MEM_FORCE_PU: u1,
-                reserved16: u13,
-                ///  Set this bit and force to enable clock signal of eFuse memory.
-                EN: u1,
-                padding: u15,
-            }),
-            ///  eFuse operation mode configuraiton register;
-            CONF: mmio.Mmio(packed struct(u32) {
-                ///  0x5A5A: Operate programming command 0x5AA5: Operate read command.
-                OP_CODE: u16,
-                padding: u16,
-            }),
-            ///  eFuse status register.
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  Indicates the state of the eFuse state machine.
-                STATE: u4,
-                ///  The value of OTP_LOAD_SW.
-                OTP_LOAD_SW: u1,
-                ///  The value of OTP_VDDQ_C_SYNC2.
-                OTP_VDDQ_C_SYNC2: u1,
-                ///  The value of OTP_STROBE_SW.
-                OTP_STROBE_SW: u1,
-                ///  The value of OTP_CSB_SW.
-                OTP_CSB_SW: u1,
-                ///  The value of OTP_PGENB_SW.
-                OTP_PGENB_SW: u1,
-                ///  The value of OTP_VDDQ_IS_SW.
-                OTP_VDDQ_IS_SW: u1,
-                ///  Indicates the number of error bits during programming BLOCK0.
-                REPEAT_ERR_CNT: u8,
-                padding: u14,
-            }),
-            ///  eFuse command register.
-            CMD: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to send read command.
-                READ_CMD: u1,
-                ///  Set this bit to send programming command.
-                PGM_CMD: u1,
-                ///  The serial number of the block to be programmed. Value 0-10 corresponds to block number 0-10, respectively.
-                BLK_NUM: u4,
-                padding: u26,
-            }),
-            ///  eFuse raw interrupt register.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  The raw bit signal for read_done interrupt.
-                READ_DONE_INT_RAW: u1,
-                ///  The raw bit signal for pgm_done interrupt.
-                PGM_DONE_INT_RAW: u1,
-                padding: u30,
-            }),
-            ///  eFuse interrupt status register.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The status signal for read_done interrupt.
-                READ_DONE_INT_ST: u1,
-                ///  The status signal for pgm_done interrupt.
-                PGM_DONE_INT_ST: u1,
-                padding: u30,
-            }),
-            ///  eFuse interrupt enable register.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The enable signal for read_done interrupt.
-                READ_DONE_INT_ENA: u1,
-                ///  The enable signal for pgm_done interrupt.
-                PGM_DONE_INT_ENA: u1,
-                padding: u30,
-            }),
-            ///  eFuse interrupt clear register.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The clear signal for read_done interrupt.
-                READ_DONE_INT_CLR: u1,
-                ///  The clear signal for pgm_done interrupt.
-                PGM_DONE_INT_CLR: u1,
-                padding: u30,
-            }),
-            ///  Controls the eFuse programming voltage.
-            DAC_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Controls the division factor of the rising clock of the programming voltage.
-                DAC_CLK_DIV: u8,
-                ///  Don't care.
-                DAC_CLK_PAD_SEL: u1,
-                ///  Controls the rising period of the programming voltage.
-                DAC_NUM: u8,
-                ///  Reduces the power supply of the programming voltage.
-                OE_CLR: u1,
-                padding: u14,
-            }),
-            ///  Configures read timing parameters.
-            RD_TIM_CONF: mmio.Mmio(packed struct(u32) {
-                reserved24: u24,
-                ///  Configures the initial read time of eFuse.
-                READ_INIT_NUM: u8,
-            }),
-            ///  Configurarion register 1 of eFuse programming timing parameters.
-            WR_TIM_CONF1: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  Configures the power up time for VDDQ.
-                PWR_ON_NUM: u16,
-                padding: u8,
-            }),
-            ///  Configurarion register 2 of eFuse programming timing parameters.
-            WR_TIM_CONF2: mmio.Mmio(packed struct(u32) {
-                ///  Configures the power outage time for VDDQ.
-                PWR_OFF_NUM: u16,
-                padding: u16,
-            }),
-            reserved508: [4]u8,
-            ///  eFuse version register.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  Stores eFuse version.
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  External Memory
-        pub const EXTMEM = extern struct {
-            ///  This description will be updated in the near future.
-            ICACHE_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to activate the data cache. 0: disable, 1: enable
-                ICACHE_ENABLE: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_CTRL1: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to disable core0 ibus, 0: enable, 1: disable
-                ICACHE_SHUT_IBUS: u1,
-                ///  The bit is used to disable core1 ibus, 0: enable, 1: disable
-                ICACHE_SHUT_DBUS: u1,
-                padding: u30,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_TAG_POWER_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to close clock gating of icache tag memory. 1: close gating, 0: open clock gating.
-                ICACHE_TAG_MEM_FORCE_ON: u1,
-                ///  The bit is used to power icache tag memory down, 0: follow rtc_lslp, 1: power down
-                ICACHE_TAG_MEM_FORCE_PD: u1,
-                ///  The bit is used to power icache tag memory up, 0: follow rtc_lslp, 1: power up
-                ICACHE_TAG_MEM_FORCE_PU: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOCK_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable the first section of prelock function.
-                ICACHE_PRELOCK_SCT0_EN: u1,
-                ///  The bit is used to enable the second section of prelock function.
-                ICACHE_PRELOCK_SCT1_EN: u1,
-                padding: u30,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOCK_SCT0_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the first start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT0_SIZE_REG
-                ICACHE_PRELOCK_SCT0_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOCK_SCT1_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the second start virtual address of data prelock, which is combined with ICACHE_PRELOCK_SCT1_SIZE_REG
-                ICACHE_PRELOCK_SCT1_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOCK_SCT_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the second length of data locking, which is combined with ICACHE_PRELOCK_SCT1_ADDR_REG
-                ICACHE_PRELOCK_SCT1_SIZE: u16,
-                ///  The bits are used to configure the first length of data locking, which is combined with ICACHE_PRELOCK_SCT0_ADDR_REG
-                ICACHE_PRELOCK_SCT0_SIZE: u16,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_LOCK_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable lock operation. It will be cleared by hardware after lock operation done.
-                ICACHE_LOCK_ENA: u1,
-                ///  The bit is used to enable unlock operation. It will be cleared by hardware after unlock operation done.
-                ICACHE_UNLOCK_ENA: u1,
-                ///  The bit is used to indicate unlock/lock operation is finished.
-                ICACHE_LOCK_DONE: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_LOCK_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address for lock operations. It should be combined with ICACHE_LOCK_SIZE_REG.
-                ICACHE_LOCK_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_LOCK_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the length for lock operations. The bits are the counts of cache block. It should be combined with ICACHE_LOCK_ADDR_REG.
-                ICACHE_LOCK_SIZE: u16,
-                padding: u16,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_SYNC_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable invalidate operation. It will be cleared by hardware after invalidate operation done.
-                ICACHE_INVALIDATE_ENA: u1,
-                ///  The bit is used to indicate invalidate operation is finished.
-                ICACHE_SYNC_DONE: u1,
-                padding: u30,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_SYNC_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address for clean operations. It should be combined with ICACHE_SYNC_SIZE_REG.
-                ICACHE_SYNC_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_SYNC_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the length for sync operations. The bits are the counts of cache block. It should be combined with ICACHE_SYNC_ADDR_REG.
-                ICACHE_SYNC_SIZE: u23,
-                padding: u9,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOAD_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable preload operation. It will be cleared by hardware after preload operation done.
-                ICACHE_PRELOAD_ENA: u1,
-                ///  The bit is used to indicate preload operation is finished.
-                ICACHE_PRELOAD_DONE: u1,
-                ///  The bit is used to configure the direction of preload operation. 1: descending, 0: ascending.
-                ICACHE_PRELOAD_ORDER: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOAD_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address for preload operation. It should be combined with ICACHE_PRELOAD_SIZE_REG.
-                ICACHE_PRELOAD_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_PRELOAD_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the length for preload operation. The bits are the counts of cache block. It should be combined with ICACHE_PRELOAD_ADDR_REG..
-                ICACHE_PRELOAD_SIZE: u16,
-                padding: u16,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_AUTOLOAD_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to enable the first section for autoload operation.
-                ICACHE_AUTOLOAD_SCT0_ENA: u1,
-                ///  The bits are used to enable the second section for autoload operation.
-                ICACHE_AUTOLOAD_SCT1_ENA: u1,
-                ///  The bit is used to enable and disable autoload operation. It is combined with icache_autoload_done. 1: enable, 0: disable.
-                ICACHE_AUTOLOAD_ENA: u1,
-                ///  The bit is used to indicate autoload operation is finished.
-                ICACHE_AUTOLOAD_DONE: u1,
-                ///  The bits are used to configure the direction of autoload. 1: descending, 0: ascending.
-                ICACHE_AUTOLOAD_ORDER: u1,
-                ///  The bits are used to configure trigger conditions for autoload. 0/3: cache miss, 1: cache hit, 2: both cache miss and hit.
-                ICACHE_AUTOLOAD_RQST: u2,
-                padding: u25,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_AUTOLOAD_SCT0_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
-                ICACHE_AUTOLOAD_SCT0_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_AUTOLOAD_SCT0_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the length of the first section for autoload operation. It should be combined with icache_autoload_sct0_ena.
-                ICACHE_AUTOLOAD_SCT0_SIZE: u27,
-                padding: u5,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_AUTOLOAD_SCT1_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
-                ICACHE_AUTOLOAD_SCT1_ADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_AUTOLOAD_SCT1_SIZE: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the length of the second section for autoload operation. It should be combined with icache_autoload_sct1_ena.
-                ICACHE_AUTOLOAD_SCT1_SIZE: u27,
-                padding: u5,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_TO_FLASH_START_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
-                IBUS_TO_FLASH_START_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_TO_FLASH_END_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the end virtual address of ibus to access flash. The register is used to give constraints to ibus access counter.
-                IBUS_TO_FLASH_END_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_TO_FLASH_START_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the start virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
-                DBUS_TO_FLASH_START_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_TO_FLASH_END_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to configure the end virtual address of dbus to access flash. The register is used to give constraints to dbus access counter.
-                DBUS_TO_FLASH_END_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ACS_CNT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to clear ibus counter.
-                IBUS_ACS_CNT_CLR: u1,
-                ///  The bit is used to clear dbus counter.
-                DBUS_ACS_CNT_CLR: u1,
-                padding: u30,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_ACS_MISS_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to count the number of the cache miss caused by ibus access flash.
-                IBUS_ACS_MISS_CNT: u32,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_ACS_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to count the number of ibus access flash through icache.
-                IBUS_ACS_CNT: u32,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_ACS_FLASH_MISS_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to count the number of the cache miss caused by dbus access flash.
-                DBUS_ACS_FLASH_MISS_CNT: u32,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_ACS_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to count the number of dbus access flash through icache.
-                DBUS_ACS_CNT: u32,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ILG_INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable interrupt by sync configurations fault.
-                ICACHE_SYNC_OP_FAULT_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by preload configurations fault.
-                ICACHE_PRELOAD_OP_FAULT_INT_ENA: u1,
-                reserved5: u3,
-                ///  The bit is used to enable interrupt by mmu entry fault.
-                MMU_ENTRY_FAULT_INT_ENA: u1,
-                reserved7: u1,
-                ///  The bit is used to enable interrupt by ibus counter overflow.
-                IBUS_CNT_OVF_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by dbus counter overflow.
-                DBUS_CNT_OVF_INT_ENA: u1,
-                padding: u23,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ILG_INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to clear interrupt by sync configurations fault.
-                ICACHE_SYNC_OP_FAULT_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by preload configurations fault.
-                ICACHE_PRELOAD_OP_FAULT_INT_CLR: u1,
-                reserved5: u3,
-                ///  The bit is used to clear interrupt by mmu entry fault.
-                MMU_ENTRY_FAULT_INT_CLR: u1,
-                reserved7: u1,
-                ///  The bit is used to clear interrupt by ibus counter overflow.
-                IBUS_CNT_OVF_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by dbus counter overflow.
-                DBUS_CNT_OVF_INT_CLR: u1,
-                padding: u23,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ILG_INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to indicate interrupt by sync configurations fault.
-                ICACHE_SYNC_OP_FAULT_ST: u1,
-                ///  The bit is used to indicate interrupt by preload configurations fault.
-                ICACHE_PRELOAD_OP_FAULT_ST: u1,
-                reserved5: u3,
-                ///  The bit is used to indicate interrupt by mmu entry fault.
-                MMU_ENTRY_FAULT_ST: u1,
-                reserved7: u1,
-                ///  The bit is used to indicate interrupt by ibus access flash/spiram counter overflow.
-                IBUS_ACS_CNT_OVF_ST: u1,
-                ///  The bit is used to indicate interrupt by ibus access flash/spiram miss counter overflow.
-                IBUS_ACS_MISS_CNT_OVF_ST: u1,
-                ///  The bit is used to indicate interrupt by dbus access flash/spiram counter overflow.
-                DBUS_ACS_CNT_OVF_ST: u1,
-                ///  The bit is used to indicate interrupt by dbus access flash miss counter overflow.
-                DBUS_ACS_FLASH_MISS_CNT_OVF_ST: u1,
-                padding: u21,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_ACS_CACHE_INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable interrupt by cpu access icache while the corresponding ibus is disabled which include speculative access.
-                CORE0_IBUS_ACS_MSK_IC_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by ibus trying to write icache
-                CORE0_IBUS_WR_IC_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by authentication fail.
-                CORE0_IBUS_REJECT_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by cpu access icache while the corresponding dbus is disabled which include speculative access.
-                CORE0_DBUS_ACS_MSK_IC_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by authentication fail.
-                CORE0_DBUS_REJECT_INT_ENA: u1,
-                ///  The bit is used to enable interrupt by dbus trying to write icache
-                CORE0_DBUS_WR_IC_INT_ENA: u1,
-                padding: u26,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_ACS_CACHE_INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to clear interrupt by cpu access icache while the corresponding ibus is disabled or icache is disabled which include speculative access.
-                CORE0_IBUS_ACS_MSK_IC_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by ibus trying to write icache
-                CORE0_IBUS_WR_IC_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by authentication fail.
-                CORE0_IBUS_REJECT_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by cpu access icache while the corresponding dbus is disabled or icache is disabled which include speculative access.
-                CORE0_DBUS_ACS_MSK_IC_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by authentication fail.
-                CORE0_DBUS_REJECT_INT_CLR: u1,
-                ///  The bit is used to clear interrupt by dbus trying to write icache
-                CORE0_DBUS_WR_IC_INT_CLR: u1,
-                padding: u26,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_ACS_CACHE_INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to indicate interrupt by cpu access icache while the core0_ibus is disabled or icache is disabled which include speculative access.
-                CORE0_IBUS_ACS_MSK_ICACHE_ST: u1,
-                ///  The bit is used to indicate interrupt by ibus trying to write icache
-                CORE0_IBUS_WR_ICACHE_ST: u1,
-                ///  The bit is used to indicate interrupt by authentication fail.
-                CORE0_IBUS_REJECT_ST: u1,
-                ///  The bit is used to indicate interrupt by cpu access icache while the core0_dbus is disabled or icache is disabled which include speculative access.
-                CORE0_DBUS_ACS_MSK_ICACHE_ST: u1,
-                ///  The bit is used to indicate interrupt by authentication fail.
-                CORE0_DBUS_REJECT_ST: u1,
-                ///  The bit is used to indicate interrupt by dbus trying to write icache
-                CORE0_DBUS_WR_ICACHE_ST: u1,
-                padding: u26,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_DBUS_REJECT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the attribute of CPU access dbus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able, 4: write-able.
-                CORE0_DBUS_ATTR: u3,
-                ///  The bit is used to indicate the world of CPU access dbus when authentication fail. 0: WORLD0, 1: WORLD1
-                CORE0_DBUS_WORLD: u1,
-                padding: u28,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_DBUS_REJECT_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the virtual address of CPU access dbus when authentication fail.
-                CORE0_DBUS_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_IBUS_REJECT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the attribute of CPU access ibus when authentication fail. 0: invalidate, 1: execute-able, 2: read-able
-                CORE0_IBUS_ATTR: u3,
-                ///  The bit is used to indicate the world of CPU access ibus when authentication fail. 0: WORLD0, 1: WORLD1
-                CORE0_IBUS_WORLD: u1,
-                padding: u28,
-            }),
-            ///  This description will be updated in the near future.
-            CORE0_IBUS_REJECT_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the virtual address of CPU access ibus when authentication fail.
-                CORE0_IBUS_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_MMU_FAULT_CONTENT: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the content of mmu entry which cause mmu fault..
-                CACHE_MMU_FAULT_CONTENT: u10,
-                ///  The right-most 3 bits are used to indicate the operations which cause mmu fault occurrence. 0: default, 1: cpu miss, 2: preload miss, 3: writeback, 4: cpu miss evict recovery address, 5: load miss evict recovery address, 6: external dma tx, 7: external dma rx. The most significant bit is used to indicate this operation occurs in which one icache.
-                CACHE_MMU_FAULT_CODE: u4,
-                padding: u18,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_MMU_FAULT_VADDR: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to indicate the virtual address which cause mmu fault..
-                CACHE_MMU_FAULT_VADDR: u32,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_WRAP_AROUND_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable wrap around mode when read data from flash.
-                CACHE_FLASH_WRAP_AROUND: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_MMU_POWER_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable clock gating to save power when access mmu memory, 0: enable, 1: disable
-                CACHE_MMU_MEM_FORCE_ON: u1,
-                ///  The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power down
-                CACHE_MMU_MEM_FORCE_PD: u1,
-                ///  The bit is used to power mmu memory down, 0: follow_rtc_lslp_pd, 1: power up
-                CACHE_MMU_MEM_FORCE_PU: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_STATE: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to indicate whether icache main fsm is in idle state or not. 1: in idle state, 0: not in idle state
-                ICACHE_STATE: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ENCRYPT_DECRYPT_RECORD_DISABLE: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                RECORD_DISABLE_DB_ENCRYPT: u1,
-                ///  Reserved.
-                RECORD_DISABLE_G0CB_DECRYPT: u1,
-                padding: u30,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_ENCRYPT_DECRYPT_CLK_FORCE_ON: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to close clock gating of manual crypt clock. 1: close gating, 0: open clock gating.
-                CLK_FORCE_ON_MANUAL_CRYPT: u1,
-                ///  The bit is used to close clock gating of automatic crypt clock. 1: close gating, 0: open clock gating.
-                CLK_FORCE_ON_AUTO_CRYPT: u1,
-                ///  The bit is used to close clock gating of external memory encrypt and decrypt clock. 1: close gating, 0: open clock gating.
-                CLK_FORCE_ON_CRYPT: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_PRELOAD_INT_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to indicate the interrupt by icache pre-load done.
-                ICACHE_PRELOAD_INT_ST: u1,
-                ///  The bit is used to enable the interrupt by icache pre-load done.
-                ICACHE_PRELOAD_INT_ENA: u1,
-                ///  The bit is used to clear the interrupt by icache pre-load done.
-                ICACHE_PRELOAD_INT_CLR: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_SYNC_INT_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to indicate the interrupt by icache sync done.
-                ICACHE_SYNC_INT_ST: u1,
-                ///  The bit is used to enable the interrupt by icache sync done.
-                ICACHE_SYNC_INT_ENA: u1,
-                ///  The bit is used to clear the interrupt by icache sync done.
-                ICACHE_SYNC_INT_CLR: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_MMU_OWNER: mmio.Mmio(packed struct(u32) {
-                ///  The bits are used to specify the owner of MMU.bit0/bit2: ibus, bit1/bit3: dbus
-                CACHE_MMU_OWNER: u4,
-                padding: u28,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_CONF_MISC: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to disable checking mmu entry fault by preload operation.
-                CACHE_IGNORE_PRELOAD_MMU_ENTRY_FAULT: u1,
-                ///  The bit is used to disable checking mmu entry fault by sync operation.
-                CACHE_IGNORE_SYNC_MMU_ENTRY_FAULT: u1,
-                ///  The bit is used to enable cache trace function.
-                CACHE_TRACE_ENA: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_FREEZE: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable icache freeze mode
-                ENA: u1,
-                ///  The bit is used to configure freeze mode, 0: assert busy if CPU miss 1: assert hit if CPU miss
-                MODE: u1,
-                ///  The bit is used to indicate icache freeze success
-                DONE: u1,
-                padding: u29,
-            }),
-            ///  This description will be updated in the near future.
-            ICACHE_ATOMIC_OPERATE_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to activate icache atomic operation protection. In this case, sync/lock operation can not interrupt miss-work. This feature does not work during invalidateAll operation.
-                ICACHE_ATOMIC_OPERATE_ENA: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            CACHE_REQUEST: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to disable request recording which could cause performance issue
-                BYPASS: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_PMS_TBL_LOCK: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the ibus permission control section boundary0
-                IBUS_PMS_LOCK: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_PMS_TBL_BOUNDARY0: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the ibus permission control section boundary0
-                IBUS_PMS_BOUNDARY0: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_PMS_TBL_BOUNDARY1: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the ibus permission control section boundary1
-                IBUS_PMS_BOUNDARY1: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_PMS_TBL_BOUNDARY2: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the ibus permission control section boundary2
-                IBUS_PMS_BOUNDARY2: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            IBUS_PMS_TBL_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure attribute of the ibus permission control section1, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
-                IBUS_PMS_SCT1_ATTR: u4,
-                ///  The bit is used to configure attribute of the ibus permission control section2, bit0: fetch in world0, bit1: load in world0, bit2: fetch in world1, bit3: load in world1
-                IBUS_PMS_SCT2_ATTR: u4,
-                padding: u24,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_PMS_TBL_LOCK: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the ibus permission control section boundary0
-                DBUS_PMS_LOCK: u1,
-                padding: u31,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_PMS_TBL_BOUNDARY0: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the dbus permission control section boundary0
-                DBUS_PMS_BOUNDARY0: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_PMS_TBL_BOUNDARY1: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the dbus permission control section boundary1
-                DBUS_PMS_BOUNDARY1: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_PMS_TBL_BOUNDARY2: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure the dbus permission control section boundary2
-                DBUS_PMS_BOUNDARY2: u12,
-                padding: u20,
-            }),
-            ///  This description will be updated in the near future.
-            DBUS_PMS_TBL_ATTR: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to configure attribute of the dbus permission control section1, bit0: load in world0, bit2: load in world1
-                DBUS_PMS_SCT1_ATTR: u2,
-                ///  The bit is used to configure attribute of the dbus permission control section2, bit0: load in world0, bit2: load in world1
-                DBUS_PMS_SCT2_ATTR: u2,
-                padding: u28,
-            }),
-            ///  This description will be updated in the near future.
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  clock gate enable.
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            reserved1020: [760]u8,
-            ///  This description will be updated in the near future.
-            REG_DATE: mmio.Mmio(packed struct(u32) {
-                ///  version information
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  General Purpose Input/Output
-        pub const GPIO = extern struct {
-            ///  GPIO bit select register
-            BT_SELECT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO bit select register
-                BT_SEL: u32,
-            }),
-            ///  GPIO output register
-            OUT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output register for GPIO0-25
-                DATA_ORIG: u26,
-                padding: u6,
-            }),
-            ///  GPIO output set register
-            OUT_W1TS: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output set register for GPIO0-25
-                OUT_W1TS: u26,
-                padding: u6,
-            }),
-            ///  GPIO output clear register
-            OUT_W1TC: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output clear register for GPIO0-25
-                OUT_W1TC: u26,
-                padding: u6,
-            }),
-            reserved28: [12]u8,
-            ///  GPIO sdio select register
-            SDIO_SELECT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO sdio select register
-                SDIO_SEL: u8,
-                padding: u24,
-            }),
-            ///  GPIO output enable register
-            ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output enable register for GPIO0-25
-                DATA: u26,
-                padding: u6,
-            }),
-            ///  GPIO output enable set register
-            ENABLE_W1TS: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output enable set register for GPIO0-25
-                ENABLE_W1TS: u26,
-                padding: u6,
-            }),
-            ///  GPIO output enable clear register
-            ENABLE_W1TC: mmio.Mmio(packed struct(u32) {
-                ///  GPIO output enable clear register for GPIO0-25
-                ENABLE_W1TC: u26,
-                padding: u6,
-            }),
-            reserved56: [12]u8,
-            ///  pad strapping register
-            STRAP: mmio.Mmio(packed struct(u32) {
-                ///  pad strapping register
-                STRAPPING: u16,
-                padding: u16,
-            }),
-            ///  GPIO input register
-            IN: mmio.Mmio(packed struct(u32) {
-                ///  GPIO input register for GPIO0-25
-                DATA_NEXT: u26,
-                padding: u6,
-            }),
-            reserved68: [4]u8,
-            ///  GPIO interrupt status register
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  GPIO interrupt status register for GPIO0-25
-                INTERRUPT: u26,
-                padding: u6,
-            }),
-            ///  GPIO interrupt status set register
-            STATUS_W1TS: mmio.Mmio(packed struct(u32) {
-                ///  GPIO interrupt status set register for GPIO0-25
-                STATUS_W1TS: u26,
-                padding: u6,
-            }),
-            ///  GPIO interrupt status clear register
-            STATUS_W1TC: mmio.Mmio(packed struct(u32) {
-                ///  GPIO interrupt status clear register for GPIO0-25
-                STATUS_W1TC: u26,
-                padding: u6,
-            }),
-            reserved92: [12]u8,
-            ///  GPIO PRO_CPU interrupt status register
-            PCPU_INT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO PRO_CPU interrupt status register for GPIO0-25
-                PROCPU_INT: u26,
-                padding: u6,
-            }),
-            ///  GPIO PRO_CPU(not shielded) interrupt status register
-            PCPU_NMI_INT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO PRO_CPU(not shielded) interrupt status register for GPIO0-25
-                PROCPU_NMI_INT: u26,
-                padding: u6,
-            }),
-            ///  GPIO CPUSDIO interrupt status register
-            CPUSDIO_INT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO CPUSDIO interrupt status register for GPIO0-25
-                SDIO_INT: u26,
-                padding: u6,
-            }),
-            reserved116: [12]u8,
-            ///  GPIO pin configuration register
-            PIN: [26]mmio.Mmio(packed struct(u32) {
-                ///  set GPIO input_sync2 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
-                PIN_SYNC2_BYPASS: u2,
-                ///  set this bit to select pad driver. 1:open-drain. :normal.
-                PIN_PAD_DRIVER: u1,
-                ///  set GPIO input_sync1 signal mode. :disable. 1:trigger at negedge. 2or3:trigger at posedge.
-                PIN_SYNC1_BYPASS: u2,
-                reserved7: u2,
-                ///  set this value to choose interrupt mode. :disable GPIO interrupt. 1:trigger at posedge. 2:trigger at negedge. 3:trigger at any edge. 4:valid at low level. 5:valid at high level
-                PIN_INT_TYPE: u3,
-                ///  set this bit to enable GPIO wakeup.(can only wakeup CPU from Light-sleep Mode)
-                PIN_WAKEUP_ENABLE: u1,
-                ///  reserved
-                PIN_CONFIG: u2,
-                ///  set bit 13 to enable CPU interrupt. set bit 14 to enable CPU(not shielded) interrupt.
-                PIN_INT_ENA: u5,
-                padding: u14,
-            }),
-            reserved332: [112]u8,
-            ///  GPIO interrupt source register
-            STATUS_NEXT: mmio.Mmio(packed struct(u32) {
-                ///  GPIO interrupt source register for GPIO0-25
-                STATUS_INTERRUPT_NEXT: u26,
-                padding: u6,
-            }),
-            reserved340: [4]u8,
-            ///  GPIO input function configuration register
-            FUNC_IN_SEL_CFG: [128]mmio.Mmio(packed struct(u32) {
-                ///  set this value: s=-53: connect GPIO[s] to this port. s=x38: set this port always high level. s=x3C: set this port always low level.
-                IN_SEL: u5,
-                ///  set this bit to invert input signal. 1:invert. :not invert.
-                IN_INV_SEL: u1,
-                ///  set this bit to bypass GPIO. 1:do not bypass GPIO. :bypass GPIO.
-                SEL: u1,
-                padding: u25,
-            }),
-            reserved1364: [512]u8,
-            ///  GPIO output function select register
-            FUNC_OUT_SEL_CFG: [26]mmio.Mmio(packed struct(u32) {
-                ///  The value of the bits: <=s<=256. Set the value to select output signal. s=-255: output of GPIO[n] equals input of peripheral[s]. s=256: output of GPIO[n] equals GPIO_OUT_REG[n].
-                OUT_SEL: u8,
-                ///  set this bit to invert output signal.1:invert.:not invert.
-                INV_SEL: u1,
-                ///  set this bit to select output enable signal.1:use GPIO_ENABLE_REG[n] as output enable signal.:use peripheral output enable signal.
-                OEN_SEL: u1,
-                ///  set this bit to invert output enable signal.1:invert.:not invert.
-                OEN_INV_SEL: u1,
-                padding: u21,
-            }),
-            reserved1580: [112]u8,
-            ///  GPIO clock gate register
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  set this bit to enable GPIO clock gate
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            reserved1788: [204]u8,
-            ///  GPIO version register
-            REG_DATE: mmio.Mmio(packed struct(u32) {
-                ///  version register
-                REG_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  Sigma-Delta Modulation
-        pub const GPIOSD = extern struct {
-            ///  Duty Cycle Configure Register of SDM%s
-            SIGMADELTA: [4]mmio.Mmio(packed struct(u32) {
-                ///  This field is used to configure the duty cycle of sigma delta modulation output.
-                SD0_IN: u8,
-                ///  This field is used to set a divider value to divide APB clock.
-                SD0_PRESCALE: u8,
-                padding: u16,
-            }),
-            reserved32: [16]u8,
-            ///  Clock Gating Configure Register
-            SIGMADELTA_CG: mmio.Mmio(packed struct(u32) {
-                reserved31: u31,
-                ///  Clock enable bit of configuration registers for sigma delta modulation.
-                CLK_EN: u1,
-            }),
-            ///  MISC Register
-            SIGMADELTA_MISC: mmio.Mmio(packed struct(u32) {
-                reserved30: u30,
-                ///  Clock enable bit of sigma delta modulation.
-                FUNCTION_CLK_EN: u1,
-                ///  Reserved.
-                SPI_SWAP: u1,
-            }),
-            ///  Version Control Register
-            SIGMADELTA_VERSION: mmio.Mmio(packed struct(u32) {
-                ///  Version control register.
-                GPIO_SD_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  HMAC (Hash-based Message Authentication Code) Accelerator
-        pub const HMAC = extern struct {
-            reserved64: [64]u8,
-            ///  Process control register 0.
-            SET_START: mmio.Mmio(packed struct(u32) {
-                ///  Start hmac operation.
-                SET_START: u1,
-                padding: u31,
-            }),
-            ///  Configure purpose.
-            SET_PARA_PURPOSE: mmio.Mmio(packed struct(u32) {
-                ///  Set hmac parameter purpose.
-                PURPOSE_SET: u4,
-                padding: u28,
-            }),
-            ///  Configure key.
-            SET_PARA_KEY: mmio.Mmio(packed struct(u32) {
-                ///  Set hmac parameter key.
-                KEY_SET: u3,
-                padding: u29,
-            }),
-            ///  Finish initial configuration.
-            SET_PARA_FINISH: mmio.Mmio(packed struct(u32) {
-                ///  Finish hmac configuration.
-                SET_PARA_END: u1,
-                padding: u31,
-            }),
-            ///  Process control register 1.
-            SET_MESSAGE_ONE: mmio.Mmio(packed struct(u32) {
-                ///  Call SHA to calculate one message block.
-                SET_TEXT_ONE: u1,
-                padding: u31,
-            }),
-            ///  Process control register 2.
-            SET_MESSAGE_ING: mmio.Mmio(packed struct(u32) {
-                ///  Continue typical hmac.
-                SET_TEXT_ING: u1,
-                padding: u31,
-            }),
-            ///  Process control register 3.
-            SET_MESSAGE_END: mmio.Mmio(packed struct(u32) {
-                ///  Start hardware padding.
-                SET_TEXT_END: u1,
-                padding: u31,
-            }),
-            ///  Process control register 4.
-            SET_RESULT_FINISH: mmio.Mmio(packed struct(u32) {
-                ///  After read result from upstream, then let hmac back to idle.
-                SET_RESULT_END: u1,
-                padding: u31,
-            }),
-            ///  Invalidate register 0.
-            SET_INVALIDATE_JTAG: mmio.Mmio(packed struct(u32) {
-                ///  Clear result from hmac downstream JTAG.
-                SET_INVALIDATE_JTAG: u1,
-                padding: u31,
-            }),
-            ///  Invalidate register 1.
-            SET_INVALIDATE_DS: mmio.Mmio(packed struct(u32) {
-                ///  Clear result from hmac downstream DS.
-                SET_INVALIDATE_DS: u1,
-                padding: u31,
-            }),
-            ///  Error register.
-            QUERY_ERROR: mmio.Mmio(packed struct(u32) {
-                ///  Hmac configuration state. 0: key are agree with purpose. 1: error
-                QUREY_CHECK: u1,
-                padding: u31,
-            }),
-            ///  Busy register.
-            QUERY_BUSY: mmio.Mmio(packed struct(u32) {
-                ///  Hmac state. 1'b0: idle. 1'b1: busy
-                BUSY_STATE: u1,
-                padding: u31,
-            }),
-            reserved128: [16]u8,
-            ///  Message block memory.
-            WR_MESSAGE_MEM: [64]u8,
-            ///  Result from upstream.
-            RD_RESULT_MEM: [32]u8,
-            reserved240: [16]u8,
-            ///  Process control register 5.
-            SET_MESSAGE_PAD: mmio.Mmio(packed struct(u32) {
-                ///  Start software padding.
-                SET_TEXT_PAD: u1,
-                padding: u31,
-            }),
-            ///  Process control register 6.
-            ONE_BLOCK: mmio.Mmio(packed struct(u32) {
-                ///  Don't have to do padding.
-                SET_ONE_BLOCK: u1,
-                padding: u31,
-            }),
-            ///  Jtag register 0.
-            SOFT_JTAG_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  Turn on JTAG verification.
-                SOFT_JTAG_CTRL: u1,
-                padding: u31,
-            }),
-            ///  Jtag register 1.
-            WR_JTAG: mmio.Mmio(packed struct(u32) {
-                ///  32-bit of key to be compared.
-                WR_JTAG: u32,
-            }),
-        };
-
-        ///  I2C (Inter-Integrated Circuit) Controller
-        pub const I2C0 = extern struct {
-            ///  I2C_SCL_LOW_PERIOD_REG
-            SCL_LOW_PERIOD: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_low_period
-                SCL_LOW_PERIOD: u9,
-                padding: u23,
-            }),
-            ///  I2C_CTR_REG
-            CTR: mmio.Mmio(packed struct(u32) {
-                ///  reg_sda_force_out
-                SDA_FORCE_OUT: u1,
-                ///  reg_scl_force_out
-                SCL_FORCE_OUT: u1,
-                ///  reg_sample_scl_level
-                SAMPLE_SCL_LEVEL: u1,
-                ///  reg_rx_full_ack_level
-                RX_FULL_ACK_LEVEL: u1,
-                ///  reg_ms_mode
-                MS_MODE: u1,
-                ///  reg_trans_start
-                TRANS_START: u1,
-                ///  reg_tx_lsb_first
-                TX_LSB_FIRST: u1,
-                ///  reg_rx_lsb_first
-                RX_LSB_FIRST: u1,
-                ///  reg_clk_en
-                CLK_EN: u1,
-                ///  reg_arbitration_en
-                ARBITRATION_EN: u1,
-                ///  reg_fsm_rst
-                FSM_RST: u1,
-                ///  reg_conf_upgate
-                CONF_UPGATE: u1,
-                ///  reg_slv_tx_auto_start_en
-                SLV_TX_AUTO_START_EN: u1,
-                ///  reg_addr_10bit_rw_check_en
-                ADDR_10BIT_RW_CHECK_EN: u1,
-                ///  reg_addr_broadcasting_en
-                ADDR_BROADCASTING_EN: u1,
-                padding: u17,
-            }),
-            ///  I2C_SR_REG
-            SR: mmio.Mmio(packed struct(u32) {
-                ///  reg_resp_rec
-                RESP_REC: u1,
-                ///  reg_slave_rw
-                SLAVE_RW: u1,
-                reserved3: u1,
-                ///  reg_arb_lost
-                ARB_LOST: u1,
-                ///  reg_bus_busy
-                BUS_BUSY: u1,
-                ///  reg_slave_addressed
-                SLAVE_ADDRESSED: u1,
-                reserved8: u2,
-                ///  reg_rxfifo_cnt
-                RXFIFO_CNT: u6,
-                ///  reg_stretch_cause
-                STRETCH_CAUSE: u2,
-                reserved18: u2,
-                ///  reg_txfifo_cnt
-                TXFIFO_CNT: u6,
-                ///  reg_scl_main_state_last
-                SCL_MAIN_STATE_LAST: u3,
-                reserved28: u1,
-                ///  reg_scl_state_last
-                SCL_STATE_LAST: u3,
-                padding: u1,
-            }),
-            ///  I2C_TO_REG
-            TO: mmio.Mmio(packed struct(u32) {
-                ///  reg_time_out_value
-                TIME_OUT_VALUE: u5,
-                ///  reg_time_out_en
-                TIME_OUT_EN: u1,
-                padding: u26,
-            }),
-            ///  I2C_SLAVE_ADDR_REG
-            SLAVE_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_slave_addr
-                SLAVE_ADDR: u15,
-                reserved31: u16,
-                ///  reg_addr_10bit_en
-                ADDR_10BIT_EN: u1,
-            }),
-            ///  I2C_FIFO_ST_REG
-            FIFO_ST: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_raddr
-                RXFIFO_RADDR: u5,
-                ///  reg_rxfifo_waddr
-                RXFIFO_WADDR: u5,
-                ///  reg_txfifo_raddr
-                TXFIFO_RADDR: u5,
-                ///  reg_txfifo_waddr
-                TXFIFO_WADDR: u5,
-                reserved22: u2,
-                ///  reg_slave_rw_point
-                SLAVE_RW_POINT: u8,
-                padding: u2,
-            }),
-            ///  I2C_FIFO_CONF_REG
-            FIFO_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_wm_thrhd
-                RXFIFO_WM_THRHD: u5,
-                ///  reg_txfifo_wm_thrhd
-                TXFIFO_WM_THRHD: u5,
-                ///  reg_nonfifo_en
-                NONFIFO_EN: u1,
-                ///  reg_fifo_addr_cfg_en
-                FIFO_ADDR_CFG_EN: u1,
-                ///  reg_rx_fifo_rst
-                RX_FIFO_RST: u1,
-                ///  reg_tx_fifo_rst
-                TX_FIFO_RST: u1,
-                ///  reg_fifo_prt_en
-                FIFO_PRT_EN: u1,
-                padding: u17,
-            }),
-            ///  I2C_FIFO_DATA_REG
-            DATA: mmio.Mmio(packed struct(u32) {
-                ///  reg_fifo_rdata
-                FIFO_RDATA: u8,
-                padding: u24,
-            }),
-            ///  I2C_INT_RAW_REG
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_wm_int_raw
-                RXFIFO_WM_INT_RAW: u1,
-                ///  reg_txfifo_wm_int_raw
-                TXFIFO_WM_INT_RAW: u1,
-                ///  reg_rxfifo_ovf_int_raw
-                RXFIFO_OVF_INT_RAW: u1,
-                ///  reg_end_detect_int_raw
-                END_DETECT_INT_RAW: u1,
-                ///  reg_byte_trans_done_int_raw
-                BYTE_TRANS_DONE_INT_RAW: u1,
-                ///  reg_arbitration_lost_int_raw
-                ARBITRATION_LOST_INT_RAW: u1,
-                ///  reg_mst_txfifo_udf_int_raw
-                MST_TXFIFO_UDF_INT_RAW: u1,
-                ///  reg_trans_complete_int_raw
-                TRANS_COMPLETE_INT_RAW: u1,
-                ///  reg_time_out_int_raw
-                TIME_OUT_INT_RAW: u1,
-                ///  reg_trans_start_int_raw
-                TRANS_START_INT_RAW: u1,
-                ///  reg_nack_int_raw
-                NACK_INT_RAW: u1,
-                ///  reg_txfifo_ovf_int_raw
-                TXFIFO_OVF_INT_RAW: u1,
-                ///  reg_rxfifo_udf_int_raw
-                RXFIFO_UDF_INT_RAW: u1,
-                ///  reg_scl_st_to_int_raw
-                SCL_ST_TO_INT_RAW: u1,
-                ///  reg_scl_main_st_to_int_raw
-                SCL_MAIN_ST_TO_INT_RAW: u1,
-                ///  reg_det_start_int_raw
-                DET_START_INT_RAW: u1,
-                ///  reg_slave_stretch_int_raw
-                SLAVE_STRETCH_INT_RAW: u1,
-                ///  reg_general_call_int_raw
-                GENERAL_CALL_INT_RAW: u1,
-                padding: u14,
-            }),
-            ///  I2C_INT_CLR_REG
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_wm_int_clr
-                RXFIFO_WM_INT_CLR: u1,
-                ///  reg_txfifo_wm_int_clr
-                TXFIFO_WM_INT_CLR: u1,
-                ///  reg_rxfifo_ovf_int_clr
-                RXFIFO_OVF_INT_CLR: u1,
-                ///  reg_end_detect_int_clr
-                END_DETECT_INT_CLR: u1,
-                ///  reg_byte_trans_done_int_clr
-                BYTE_TRANS_DONE_INT_CLR: u1,
-                ///  reg_arbitration_lost_int_clr
-                ARBITRATION_LOST_INT_CLR: u1,
-                ///  reg_mst_txfifo_udf_int_clr
-                MST_TXFIFO_UDF_INT_CLR: u1,
-                ///  reg_trans_complete_int_clr
-                TRANS_COMPLETE_INT_CLR: u1,
-                ///  reg_time_out_int_clr
-                TIME_OUT_INT_CLR: u1,
-                ///  reg_trans_start_int_clr
-                TRANS_START_INT_CLR: u1,
-                ///  reg_nack_int_clr
-                NACK_INT_CLR: u1,
-                ///  reg_txfifo_ovf_int_clr
-                TXFIFO_OVF_INT_CLR: u1,
-                ///  reg_rxfifo_udf_int_clr
-                RXFIFO_UDF_INT_CLR: u1,
-                ///  reg_scl_st_to_int_clr
-                SCL_ST_TO_INT_CLR: u1,
-                ///  reg_scl_main_st_to_int_clr
-                SCL_MAIN_ST_TO_INT_CLR: u1,
-                ///  reg_det_start_int_clr
-                DET_START_INT_CLR: u1,
-                ///  reg_slave_stretch_int_clr
-                SLAVE_STRETCH_INT_CLR: u1,
-                ///  reg_general_call_int_clr
-                GENERAL_CALL_INT_CLR: u1,
-                padding: u14,
-            }),
-            ///  I2C_INT_ENA_REG
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_wm_int_ena
-                RXFIFO_WM_INT_ENA: u1,
-                ///  reg_txfifo_wm_int_ena
-                TXFIFO_WM_INT_ENA: u1,
-                ///  reg_rxfifo_ovf_int_ena
-                RXFIFO_OVF_INT_ENA: u1,
-                ///  reg_end_detect_int_ena
-                END_DETECT_INT_ENA: u1,
-                ///  reg_byte_trans_done_int_ena
-                BYTE_TRANS_DONE_INT_ENA: u1,
-                ///  reg_arbitration_lost_int_ena
-                ARBITRATION_LOST_INT_ENA: u1,
-                ///  reg_mst_txfifo_udf_int_ena
-                MST_TXFIFO_UDF_INT_ENA: u1,
-                ///  reg_trans_complete_int_ena
-                TRANS_COMPLETE_INT_ENA: u1,
-                ///  reg_time_out_int_ena
-                TIME_OUT_INT_ENA: u1,
-                ///  reg_trans_start_int_ena
-                TRANS_START_INT_ENA: u1,
-                ///  reg_nack_int_ena
-                NACK_INT_ENA: u1,
-                ///  reg_txfifo_ovf_int_ena
-                TXFIFO_OVF_INT_ENA: u1,
-                ///  reg_rxfifo_udf_int_ena
-                RXFIFO_UDF_INT_ENA: u1,
-                ///  reg_scl_st_to_int_ena
-                SCL_ST_TO_INT_ENA: u1,
-                ///  reg_scl_main_st_to_int_ena
-                SCL_MAIN_ST_TO_INT_ENA: u1,
-                ///  reg_det_start_int_ena
-                DET_START_INT_ENA: u1,
-                ///  reg_slave_stretch_int_ena
-                SLAVE_STRETCH_INT_ENA: u1,
-                ///  reg_general_call_int_ena
-                GENERAL_CALL_INT_ENA: u1,
-                padding: u14,
-            }),
-            ///  I2C_INT_STATUS_REG
-            INT_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_wm_int_st
-                RXFIFO_WM_INT_ST: u1,
-                ///  reg_txfifo_wm_int_st
-                TXFIFO_WM_INT_ST: u1,
-                ///  reg_rxfifo_ovf_int_st
-                RXFIFO_OVF_INT_ST: u1,
-                ///  reg_end_detect_int_st
-                END_DETECT_INT_ST: u1,
-                ///  reg_byte_trans_done_int_st
-                BYTE_TRANS_DONE_INT_ST: u1,
-                ///  reg_arbitration_lost_int_st
-                ARBITRATION_LOST_INT_ST: u1,
-                ///  reg_mst_txfifo_udf_int_st
-                MST_TXFIFO_UDF_INT_ST: u1,
-                ///  reg_trans_complete_int_st
-                TRANS_COMPLETE_INT_ST: u1,
-                ///  reg_time_out_int_st
-                TIME_OUT_INT_ST: u1,
-                ///  reg_trans_start_int_st
-                TRANS_START_INT_ST: u1,
-                ///  reg_nack_int_st
-                NACK_INT_ST: u1,
-                ///  reg_txfifo_ovf_int_st
-                TXFIFO_OVF_INT_ST: u1,
-                ///  reg_rxfifo_udf_int_st
-                RXFIFO_UDF_INT_ST: u1,
-                ///  reg_scl_st_to_int_st
-                SCL_ST_TO_INT_ST: u1,
-                ///  reg_scl_main_st_to_int_st
-                SCL_MAIN_ST_TO_INT_ST: u1,
-                ///  reg_det_start_int_st
-                DET_START_INT_ST: u1,
-                ///  reg_slave_stretch_int_st
-                SLAVE_STRETCH_INT_ST: u1,
-                ///  reg_general_call_int_st
-                GENERAL_CALL_INT_ST: u1,
-                padding: u14,
-            }),
-            ///  I2C_SDA_HOLD_REG
-            SDA_HOLD: mmio.Mmio(packed struct(u32) {
-                ///  reg_sda_hold_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_SDA_SAMPLE_REG
-            SDA_SAMPLE: mmio.Mmio(packed struct(u32) {
-                ///  reg_sda_sample_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_SCL_HIGH_PERIOD_REG
-            SCL_HIGH_PERIOD: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_high_period
-                SCL_HIGH_PERIOD: u9,
-                ///  reg_scl_wait_high_period
-                SCL_WAIT_HIGH_PERIOD: u7,
-                padding: u16,
-            }),
-            reserved64: [4]u8,
-            ///  I2C_SCL_START_HOLD_REG
-            SCL_START_HOLD: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_start_hold_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_SCL_RSTART_SETUP_REG
-            SCL_RSTART_SETUP: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_rstart_setup_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_SCL_STOP_HOLD_REG
-            SCL_STOP_HOLD: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_stop_hold_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_SCL_STOP_SETUP_REG
-            SCL_STOP_SETUP: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_stop_setup_time
-                TIME: u9,
-                padding: u23,
-            }),
-            ///  I2C_FILTER_CFG_REG
-            FILTER_CFG: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_filter_thres
-                SCL_FILTER_THRES: u4,
-                ///  reg_sda_filter_thres
-                SDA_FILTER_THRES: u4,
-                ///  reg_scl_filter_en
-                SCL_FILTER_EN: u1,
-                ///  reg_sda_filter_en
-                SDA_FILTER_EN: u1,
-                padding: u22,
-            }),
-            ///  I2C_CLK_CONF_REG
-            CLK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_sclk_div_num
-                SCLK_DIV_NUM: u8,
-                ///  reg_sclk_div_a
-                SCLK_DIV_A: u6,
-                ///  reg_sclk_div_b
-                SCLK_DIV_B: u6,
-                ///  reg_sclk_sel
-                SCLK_SEL: u1,
-                ///  reg_sclk_active
-                SCLK_ACTIVE: u1,
-                padding: u10,
-            }),
-            ///  I2C_COMD%s_REG
-            COMD: [8]mmio.Mmio(packed struct(u32) {
-                ///  reg_command
-                COMMAND: u14,
-                reserved31: u17,
-                ///  reg_command_done
-                COMMAND_DONE: u1,
-            }),
-            ///  I2C_SCL_ST_TIME_OUT_REG
-            SCL_ST_TIME_OUT: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_st_to_regno more than 23
-                SCL_ST_TO_I2C: u5,
-                padding: u27,
-            }),
-            ///  I2C_SCL_MAIN_ST_TIME_OUT_REG
-            SCL_MAIN_ST_TIME_OUT: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_main_st_to_regno more than 23
-                SCL_MAIN_ST_TO_I2C: u5,
-                padding: u27,
-            }),
-            ///  I2C_SCL_SP_CONF_REG
-            SCL_SP_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_scl_rst_slv_en
-                SCL_RST_SLV_EN: u1,
-                ///  reg_scl_rst_slv_num
-                SCL_RST_SLV_NUM: u5,
-                ///  reg_scl_pd_en
-                SCL_PD_EN: u1,
-                ///  reg_sda_pd_en
-                SDA_PD_EN: u1,
-                padding: u24,
-            }),
-            ///  I2C_SCL_STRETCH_CONF_REG
-            SCL_STRETCH_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_stretch_protect_num
-                STRETCH_PROTECT_NUM: u10,
-                ///  reg_slave_scl_stretch_en
-                SLAVE_SCL_STRETCH_EN: u1,
-                ///  reg_slave_scl_stretch_clr
-                SLAVE_SCL_STRETCH_CLR: u1,
-                ///  reg_slave_byte_ack_ctl_en
-                SLAVE_BYTE_ACK_CTL_EN: u1,
-                ///  reg_slave_byte_ack_lvl
-                SLAVE_BYTE_ACK_LVL: u1,
-                padding: u18,
-            }),
-            reserved248: [112]u8,
-            ///  I2C_DATE_REG
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_date
-                DATE: u32,
-            }),
-            reserved256: [4]u8,
-            ///  I2C_TXFIFO_START_ADDR_REG
-            TXFIFO_START_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_txfifo_start_addr.
-                TXFIFO_START_ADDR: u32,
-            }),
-            reserved384: [124]u8,
-            ///  I2C_RXFIFO_START_ADDR_REG
-            RXFIFO_START_ADDR: mmio.Mmio(packed struct(u32) {
-                ///  reg_rxfifo_start_addr.
-                RXFIFO_START_ADDR: u32,
-            }),
-        };
-
-        ///  I2S (Inter-IC Sound) Controller
-        pub const I2S = extern struct {
-            reserved12: [12]u8,
-            ///  I2S interrupt raw register, valid in level.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt status bit for the i2s_rx_done_int interrupt
-                RX_DONE_INT_RAW: u1,
-                ///  The raw interrupt status bit for the i2s_tx_done_int interrupt
-                TX_DONE_INT_RAW: u1,
-                ///  The raw interrupt status bit for the i2s_rx_hung_int interrupt
-                RX_HUNG_INT_RAW: u1,
-                ///  The raw interrupt status bit for the i2s_tx_hung_int interrupt
-                TX_HUNG_INT_RAW: u1,
-                padding: u28,
-            }),
-            ///  I2S interrupt status register.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The masked interrupt status bit for the i2s_rx_done_int interrupt
-                RX_DONE_INT_ST: u1,
-                ///  The masked interrupt status bit for the i2s_tx_done_int interrupt
-                TX_DONE_INT_ST: u1,
-                ///  The masked interrupt status bit for the i2s_rx_hung_int interrupt
-                RX_HUNG_INT_ST: u1,
-                ///  The masked interrupt status bit for the i2s_tx_hung_int interrupt
-                TX_HUNG_INT_ST: u1,
-                padding: u28,
-            }),
-            ///  I2S interrupt enable register.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The interrupt enable bit for the i2s_rx_done_int interrupt
-                RX_DONE_INT_ENA: u1,
-                ///  The interrupt enable bit for the i2s_tx_done_int interrupt
-                TX_DONE_INT_ENA: u1,
-                ///  The interrupt enable bit for the i2s_rx_hung_int interrupt
-                RX_HUNG_INT_ENA: u1,
-                ///  The interrupt enable bit for the i2s_tx_hung_int interrupt
-                TX_HUNG_INT_ENA: u1,
-                padding: u28,
-            }),
-            ///  I2S interrupt clear register.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the i2s_rx_done_int interrupt
-                RX_DONE_INT_CLR: u1,
-                ///  Set this bit to clear the i2s_tx_done_int interrupt
-                TX_DONE_INT_CLR: u1,
-                ///  Set this bit to clear the i2s_rx_hung_int interrupt
-                RX_HUNG_INT_CLR: u1,
-                ///  Set this bit to clear the i2s_tx_hung_int interrupt
-                TX_HUNG_INT_CLR: u1,
-                padding: u28,
-            }),
-            reserved32: [4]u8,
-            ///  I2S RX configure register
-            RX_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to reset receiver
-                RX_RESET: u1,
-                ///  Set this bit to reset Rx AFIFO
-                RX_FIFO_RESET: u1,
-                ///  Set this bit to start receiving data
-                RX_START: u1,
-                ///  Set this bit to enable slave receiver mode
-                RX_SLAVE_MOD: u1,
-                reserved5: u1,
-                ///  Set this bit to enable receiver in mono mode
-                RX_MONO: u1,
-                reserved7: u1,
-                ///  I2S Rx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
-                RX_BIG_ENDIAN: u1,
-                ///  Set 1 to update I2S RX registers from APB clock domain to I2S RX clock domain. This bit will be cleared by hardware after update register done.
-                RX_UPDATE: u1,
-                ///  1: The first channel data value is valid in I2S RX mono mode. 0: The second channel data value is valid in I2S RX mono mode.
-                RX_MONO_FST_VLD: u1,
-                ///  I2S RX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-                RX_PCM_CONF: u2,
-                ///  Set this bit to bypass Compress/Decompress module for received data.
-                RX_PCM_BYPASS: u1,
-                ///  0 : I2S Rx only stop when reg_rx_start is cleared. 1: Stop when reg_rx_start is 0 or in_suc_eof is 1. 2: Stop I2S RX when reg_rx_start is 0 or RX FIFO is full.
-                RX_STOP_MODE: u2,
-                ///  1: I2S RX left alignment mode. 0: I2S RX right alignment mode.
-                RX_LEFT_ALIGN: u1,
-                ///  1: store 24 channel bits to 32 bits. 0:store 24 channel bits to 24 bits.
-                RX_24_FILL_EN: u1,
-                ///  0: WS should be 0 when receiving left channel data, and WS is 1in right channel. 1: WS should be 1 when receiving left channel data, and WS is 0in right channel.
-                RX_WS_IDLE_POL: u1,
-                ///  I2S Rx bit endian. 1:small endian, the LSB is received first. 0:big endian, the MSB is received first.
-                RX_BIT_ORDER: u1,
-                ///  1: Enable I2S TDM Rx mode . 0: Disable.
-                RX_TDM_EN: u1,
-                ///  1: Enable I2S PDM Rx mode . 0: Disable.
-                RX_PDM_EN: u1,
-                padding: u11,
-            }),
-            ///  I2S TX configure register
-            TX_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to reset transmitter
-                TX_RESET: u1,
-                ///  Set this bit to reset Tx AFIFO
-                TX_FIFO_RESET: u1,
-                ///  Set this bit to start transmitting data
-                TX_START: u1,
-                ///  Set this bit to enable slave transmitter mode
-                TX_SLAVE_MOD: u1,
-                reserved5: u1,
-                ///  Set this bit to enable transmitter in mono mode
-                TX_MONO: u1,
-                ///  1: The value of Left channel data is equal to the value of right channel data in I2S TX mono mode or TDM channel select mode. 0: The invalid channel data is reg_i2s_single_data in I2S TX mono mode or TDM channel select mode.
-                TX_CHAN_EQUAL: u1,
-                ///  I2S Tx byte endian, 1: low addr value to high addr. 0: low addr with low addr value.
-                TX_BIG_ENDIAN: u1,
-                ///  Set 1 to update I2S TX registers from APB clock domain to I2S TX clock domain. This bit will be cleared by hardware after update register done.
-                TX_UPDATE: u1,
-                ///  1: The first channel data value is valid in I2S TX mono mode. 0: The second channel data value is valid in I2S TX mono mode.
-                TX_MONO_FST_VLD: u1,
-                ///  I2S TX compress/decompress configuration bit. & 0 (atol): A-Law decompress, 1 (ltoa) : A-Law compress, 2 (utol) : u-Law decompress, 3 (ltou) : u-Law compress. &
-                TX_PCM_CONF: u2,
-                ///  Set this bit to bypass Compress/Decompress module for transmitted data.
-                TX_PCM_BYPASS: u1,
-                ///  Set this bit to stop disable output BCK signal and WS signal when tx FIFO is emtpy
-                TX_STOP_EN: u1,
-                reserved15: u1,
-                ///  1: I2S TX left alignment mode. 0: I2S TX right alignment mode.
-                TX_LEFT_ALIGN: u1,
-                ///  1: Sent 32 bits in 24 channel bits mode. 0: Sent 24 bits in 24 channel bits mode
-                TX_24_FILL_EN: u1,
-                ///  0: WS should be 0 when sending left channel data, and WS is 1in right channel. 1: WS should be 1 when sending left channel data, and WS is 0in right channel.
-                TX_WS_IDLE_POL: u1,
-                ///  I2S Tx bit endian. 1:small endian, the LSB is sent first. 0:big endian, the MSB is sent first.
-                TX_BIT_ORDER: u1,
-                ///  1: Enable I2S TDM Tx mode . 0: Disable.
-                TX_TDM_EN: u1,
-                ///  1: Enable I2S PDM Tx mode . 0: Disable.
-                TX_PDM_EN: u1,
-                reserved24: u3,
-                ///  I2S transmitter channel mode configuration bits.
-                TX_CHAN_MOD: u3,
-                ///  Enable signal loop back mode with transmitter module and receiver module sharing the same WS and BCK signals.
-                SIG_LOOPBACK: u1,
-                padding: u4,
-            }),
-            ///  I2S RX configure register 1
-            RX_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  The width of rx_ws_out in TDM mode is (I2S_RX_TDM_WS_WIDTH[6:0] +1) * T_bck
-                RX_TDM_WS_WIDTH: u7,
-                ///  Bit clock configuration bits in receiver mode.
-                RX_BCK_DIV_NUM: u6,
-                ///  Set the bits to configure the valid data bit length of I2S receiver channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
-                RX_BITS_MOD: u5,
-                ///  I2S Rx half sample bits -1.
-                RX_HALF_SAMPLE_BITS: u6,
-                ///  The Rx bit number for each channel minus 1in TDM mode.
-                RX_TDM_CHAN_BITS: u5,
-                ///  Set this bit to enable receiver in Phillips standard mode
-                RX_MSB_SHIFT: u1,
-                padding: u2,
-            }),
-            ///  I2S TX configure register 1
-            TX_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  The width of tx_ws_out in TDM mode is (I2S_TX_TDM_WS_WIDTH[6:0] +1) * T_bck
-                TX_TDM_WS_WIDTH: u7,
-                ///  Bit clock configuration bits in transmitter mode.
-                TX_BCK_DIV_NUM: u6,
-                ///  Set the bits to configure the valid data bit length of I2S transmitter channel. 7: all the valid channel data is in 8-bit-mode. 15: all the valid channel data is in 16-bit-mode. 23: all the valid channel data is in 24-bit-mode. 31:all the valid channel data is in 32-bit-mode.
-                TX_BITS_MOD: u5,
-                ///  I2S Tx half sample bits -1.
-                TX_HALF_SAMPLE_BITS: u6,
-                ///  The Tx bit number for each channel minus 1in TDM mode.
-                TX_TDM_CHAN_BITS: u5,
-                ///  Set this bit to enable transmitter in Phillips standard mode
-                TX_MSB_SHIFT: u1,
-                ///  1: BCK is not delayed to generate pos/neg edge in master mode. 0: BCK is delayed to generate pos/neg edge in master mode.
-                TX_BCK_NO_DLY: u1,
-                padding: u1,
-            }),
-            ///  I2S RX clock configure register
-            RX_CLKM_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Integral I2S clock divider value
-                RX_CLKM_DIV_NUM: u8,
-                reserved26: u18,
-                ///  I2S Rx module clock enable signal.
-                RX_CLK_ACTIVE: u1,
-                ///  Select I2S Rx module source clock. 0: no clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
-                RX_CLK_SEL: u2,
-                ///  0: UseI2S Tx module clock as I2S_MCLK_OUT. 1: UseI2S Rx module clock as I2S_MCLK_OUT.
-                MCLK_SEL: u1,
-                padding: u2,
-            }),
-            ///  I2S TX clock configure register
-            TX_CLKM_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Integral I2S TX clock divider value. f_I2S_CLK = f_I2S_CLK_S/(N+b/a). There will be (a-b) * n-div and b * (n+1)-div. So the average combination will be: for b <= a/2, z * [x * n-div + (n+1)-div] + y * n-div. For b > a/2, z * [n-div + x * (n+1)-div] + y * (n+1)-div.
-                TX_CLKM_DIV_NUM: u8,
-                reserved26: u18,
-                ///  I2S Tx module clock enable signal.
-                TX_CLK_ACTIVE: u1,
-                ///  Select I2S Tx module source clock. 0: XTAL clock. 1: APLL. 2: CLK160. 3: I2S_MCLK_in.
-                TX_CLK_SEL: u2,
-                ///  Set this bit to enable clk gate
-                CLK_EN: u1,
-                padding: u2,
-            }),
-            ///  I2S RX module clock divider configure register
-            RX_CLKM_DIV_CONF: mmio.Mmio(packed struct(u32) {
-                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_RX_CLKM_DIV_Z is (a-b).
-                RX_CLKM_DIV_Z: u9,
-                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_RX_CLKM_DIV_Y is (a%(a-b)).
-                RX_CLKM_DIV_Y: u9,
-                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_RX_CLKM_DIV_X is (a/(a-b)) - 1.
-                RX_CLKM_DIV_X: u9,
-                ///  For b <= a/2, the value of I2S_RX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_RX_CLKM_DIV_YN1 is 1.
-                RX_CLKM_DIV_YN1: u1,
-                padding: u4,
-            }),
-            ///  I2S TX module clock divider configure register
-            TX_CLKM_DIV_CONF: mmio.Mmio(packed struct(u32) {
-                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_Z is b. For b > a/2, the value of I2S_TX_CLKM_DIV_Z is (a-b).
-                TX_CLKM_DIV_Z: u9,
-                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_Y is (a%b) . For b > a/2, the value of I2S_TX_CLKM_DIV_Y is (a%(a-b)).
-                TX_CLKM_DIV_Y: u9,
-                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_X is (a/b) - 1. For b > a/2, the value of I2S_TX_CLKM_DIV_X is (a/(a-b)) - 1.
-                TX_CLKM_DIV_X: u9,
-                ///  For b <= a/2, the value of I2S_TX_CLKM_DIV_YN1 is 0 . For b > a/2, the value of I2S_TX_CLKM_DIV_YN1 is 1.
-                TX_CLKM_DIV_YN1: u1,
-                padding: u4,
-            }),
-            ///  I2S TX PCM2PDM configuration register
-            TX_PCM2PDM_CONF: mmio.Mmio(packed struct(u32) {
-                ///  I2S TX PDM bypass hp filter or not. The option has been removed.
-                TX_PDM_HP_BYPASS: u1,
-                ///  I2S TX PDM OSR2 value
-                TX_PDM_SINC_OSR2: u4,
-                ///  I2S TX PDM prescale for sigmadelta
-                TX_PDM_PRESCALE: u8,
-                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-                TX_PDM_HP_IN_SHIFT: u2,
-                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-                TX_PDM_LP_IN_SHIFT: u2,
-                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-                TX_PDM_SINC_IN_SHIFT: u2,
-                ///  I2S TX PDM sigmadelta scale shift number: 0:/2 , 1:x1 , 2:x2 , 3: x4
-                TX_PDM_SIGMADELTA_IN_SHIFT: u2,
-                ///  I2S TX PDM sigmadelta dither2 value
-                TX_PDM_SIGMADELTA_DITHER2: u1,
-                ///  I2S TX PDM sigmadelta dither value
-                TX_PDM_SIGMADELTA_DITHER: u1,
-                ///  I2S TX PDM dac mode enable
-                TX_PDM_DAC_2OUT_EN: u1,
-                ///  I2S TX PDM dac 2channel enable
-                TX_PDM_DAC_MODE_EN: u1,
-                ///  I2S TX PDM Converter enable
-                PCM2PDM_CONV_EN: u1,
-                padding: u6,
-            }),
-            ///  I2S TX PCM2PDM configuration register
-            TX_PCM2PDM_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  I2S TX PDM Fp
-                TX_PDM_FP: u10,
-                ///  I2S TX PDM Fs
-                TX_PDM_FS: u10,
-                ///  The fourth parameter of PDM TX IIR_HP filter stage 2 is (504 + I2S_TX_IIR_HP_MULT12_5[2:0])
-                TX_IIR_HP_MULT12_5: u3,
-                ///  The fourth parameter of PDM TX IIR_HP filter stage 1 is (504 + I2S_TX_IIR_HP_MULT12_0[2:0])
-                TX_IIR_HP_MULT12_0: u3,
-                padding: u6,
-            }),
-            reserved80: [8]u8,
-            ///  I2S TX TDM mode control register
-            RX_TDM_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 0. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN0_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 1. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN1_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 2. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN2_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 3. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN3_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 4. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN4_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 5. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN5_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 6. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN6_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM or PDM channel 7. 0: Disable, just input 0 in this channel.
-                RX_TDM_PDM_CHAN7_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 8. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN8_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 9. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN9_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 10. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN10_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 11. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN11_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 12. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN12_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 13. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN13_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 14. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN14_EN: u1,
-                ///  1: Enable the valid data input of I2S RX TDM channel 15. 0: Disable, just input 0 in this channel.
-                RX_TDM_CHAN15_EN: u1,
-                ///  The total channel number of I2S TX TDM mode.
-                RX_TDM_TOT_CHAN_NUM: u4,
-                padding: u12,
-            }),
-            ///  I2S TX TDM mode control register
-            TX_TDM_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  1: Enable the valid data output of I2S TX TDM channel 0. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN0_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 1. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN1_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 2. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN2_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 3. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN3_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 4. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN4_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 5. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN5_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 6. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN6_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 7. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN7_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 8. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN8_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 9. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN9_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 10. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN10_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 11. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN11_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 12. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN12_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 13. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN13_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 14. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN14_EN: u1,
-                ///  1: Enable the valid data output of I2S TX TDM channel 15. 0: Disable, just output 0 in this channel.
-                TX_TDM_CHAN15_EN: u1,
-                ///  The total channel number of I2S TX TDM mode.
-                TX_TDM_TOT_CHAN_NUM: u4,
-                ///  When DMA TX buffer stores the data of (REG_TX_TDM_TOT_CHAN_NUM + 1) channels, and only the data of the enabled channels is sent, then this bit should be set. Clear it when all the data stored in DMA TX buffer is for enabled channels.
-                TX_TDM_SKIP_MSK_EN: u1,
-                padding: u11,
-            }),
-            ///  I2S RX timing control register
-            RX_TIMING: mmio.Mmio(packed struct(u32) {
-                ///  The delay mode of I2S Rx SD input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                RX_SD_IN_DM: u2,
-                reserved16: u14,
-                ///  The delay mode of I2S Rx WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                RX_WS_OUT_DM: u2,
-                reserved20: u2,
-                ///  The delay mode of I2S Rx BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                RX_BCK_OUT_DM: u2,
-                reserved24: u2,
-                ///  The delay mode of I2S Rx WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                RX_WS_IN_DM: u2,
-                reserved28: u2,
-                ///  The delay mode of I2S Rx BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                RX_BCK_IN_DM: u2,
-                padding: u2,
-            }),
-            ///  I2S TX timing control register
-            TX_TIMING: mmio.Mmio(packed struct(u32) {
-                ///  The delay mode of I2S TX SD output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_SD_OUT_DM: u2,
-                reserved4: u2,
-                ///  The delay mode of I2S TX SD1 output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_SD1_OUT_DM: u2,
-                reserved16: u10,
-                ///  The delay mode of I2S TX WS output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_WS_OUT_DM: u2,
-                reserved20: u2,
-                ///  The delay mode of I2S TX BCK output signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_BCK_OUT_DM: u2,
-                reserved24: u2,
-                ///  The delay mode of I2S TX WS input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_WS_IN_DM: u2,
-                reserved28: u2,
-                ///  The delay mode of I2S TX BCK input signal. 0: bypass. 1: delay by pos edge. 2: delay by neg edge. 3: not used.
-                TX_BCK_IN_DM: u2,
-                padding: u2,
-            }),
-            ///  I2S HUNG configure register.
-            LC_HUNG_CONF: mmio.Mmio(packed struct(u32) {
-                ///  the i2s_tx_hung_int interrupt or the i2s_rx_hung_int interrupt will be triggered when fifo hung counter is equal to this value
-                LC_FIFO_TIMEOUT: u8,
-                ///  The bits are used to scale tick counter threshold. The tick counter is reset when counter value >= 88000/2^i2s_lc_fifo_timeout_shift
-                LC_FIFO_TIMEOUT_SHIFT: u3,
-                ///  The enable bit for FIFO timeout
-                LC_FIFO_TIMEOUT_ENA: u1,
-                padding: u20,
-            }),
-            ///  I2S RX data number control register.
-            RXEOF_NUM: mmio.Mmio(packed struct(u32) {
-                ///  The receive data bit length is (I2S_RX_BITS_MOD[4:0] + 1) * (REG_RX_EOF_NUM[11:0] + 1) . It will trigger in_suc_eof interrupt in the configured DMA RX channel.
-                RX_EOF_NUM: u12,
-                padding: u20,
-            }),
-            ///  I2S signal data register
-            CONF_SIGLE_DATA: mmio.Mmio(packed struct(u32) {
-                ///  The configured constant channel data to be sent out.
-                SINGLE_DATA: u32,
-            }),
-            ///  I2S TX status register
-            STATE: mmio.Mmio(packed struct(u32) {
-                ///  1: i2s_tx is idle state. 0: i2s_tx is working.
-                TX_IDLE: u1,
-                padding: u31,
-            }),
-            reserved128: [16]u8,
-            ///  Version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  I2S version control register
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  Interrupt Core
-        pub const INTERRUPT_CORE0 = extern struct {
-            ///  mac intr map register
-            MAC_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  core0_mac_intr_map
-                MAC_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac nmi_intr map register
-            MAC_NMI_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_mac_nmi_map
-                MAC_NMI_MAP: u5,
-                padding: u27,
-            }),
-            ///  pwr intr map register
-            PWR_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_pwr_intr_map
-                PWR_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  bb intr map register
-            BB_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_bb_int_map
-                BB_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  bt intr map register
-            BT_MAC_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_bt_mac_int_map
-                BT_MAC_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  bb_bt intr map register
-            BT_BB_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_bt_bb_int_map
-                BT_BB_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  bb_bt_nmi intr map register
-            BT_BB_NMI_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_bt_bb_nmi_map
-                BT_BB_NMI_MAP: u5,
-                padding: u27,
-            }),
-            ///  rwbt intr map register
-            RWBT_IRQ_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rwbt_irq_map
-                RWBT_IRQ_MAP: u5,
-                padding: u27,
-            }),
-            ///  rwble intr map register
-            RWBLE_IRQ_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rwble_irq_map
-                RWBLE_IRQ_MAP: u5,
-                padding: u27,
-            }),
-            ///  rwbt_nmi intr map register
-            RWBT_NMI_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rwbt_nmi_map
-                RWBT_NMI_MAP: u5,
-                padding: u27,
-            }),
-            ///  rwble_nmi intr map register
-            RWBLE_NMI_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rwble_nmi_map
-                RWBLE_NMI_MAP: u5,
-                padding: u27,
-            }),
-            ///  i2c intr map register
-            I2C_MST_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_i2c_mst_int_map
-                I2C_MST_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  slc0 intr map register
-            SLC0_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_slc0_intr_map
-                SLC0_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  slc1 intr map register
-            SLC1_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_slc1_intr_map
-                SLC1_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  apb_ctrl intr map register
-            APB_CTRL_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_apb_ctrl_intr_map
-                APB_CTRL_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  uchi0 intr map register
-            UHCI0_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_uhci0_intr_map
-                UHCI0_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  gpio intr map register
-            GPIO_INTERRUPT_PRO_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_gpio_interrupt_pro_map
-                GPIO_INTERRUPT_PRO_MAP: u5,
-                padding: u27,
-            }),
-            ///  gpio_pro intr map register
-            GPIO_INTERRUPT_PRO_NMI_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_gpio_interrupt_pro_nmi_map
-                GPIO_INTERRUPT_PRO_NMI_MAP: u5,
-                padding: u27,
-            }),
-            ///  gpio_pro_nmi intr map register
-            SPI_INTR_1_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_spi_intr_1_map
-                SPI_INTR_1_MAP: u5,
-                padding: u27,
-            }),
-            ///  spi1 intr map register
-            SPI_INTR_2_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_spi_intr_2_map
-                SPI_INTR_2_MAP: u5,
-                padding: u27,
-            }),
-            ///  spi2 intr map register
-            I2S1_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_i2s1_int_map
-                I2S1_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  i2s1 intr map register
-            UART_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_uart_intr_map
-                UART_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  uart1 intr map register
-            UART1_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_uart1_intr_map
-                UART1_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  ledc intr map register
-            LEDC_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_ledc_int_map
-                LEDC_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  efuse intr map register
-            EFUSE_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_efuse_int_map
-                EFUSE_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  can intr map register
-            CAN_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_can_int_map
-                CAN_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  usb intr map register
-            USB_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_usb_intr_map
-                USB_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  rtc intr map register
-            RTC_CORE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rtc_core_intr_map
-                RTC_CORE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  rmt intr map register
-            RMT_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rmt_intr_map
-                RMT_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  i2c intr map register
-            I2C_EXT0_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_i2c_ext0_intr_map
-                I2C_EXT0_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  timer1 intr map register
-            TIMER_INT1_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_timer_int1_map
-                TIMER_INT1_MAP: u5,
-                padding: u27,
-            }),
-            ///  timer2 intr map register
-            TIMER_INT2_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_timer_int2_map
-                TIMER_INT2_MAP: u5,
-                padding: u27,
-            }),
-            ///  tg to intr map register
-            TG_T0_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_tg_t0_int_map
-                TG_T0_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  tg wdt intr map register
-            TG_WDT_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_tg_wdt_int_map
-                TG_WDT_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  tg1 to intr map register
-            TG1_T0_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_tg1_t0_int_map
-                TG1_T0_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  tg1 wdt intr map register
-            TG1_WDT_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_tg1_wdt_int_map
-                TG1_WDT_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  cache ia intr map register
-            CACHE_IA_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cache_ia_int_map
-                CACHE_IA_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  systimer intr map register
-            SYSTIMER_TARGET0_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_systimer_target0_int_map
-                SYSTIMER_TARGET0_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  systimer target1 intr map register
-            SYSTIMER_TARGET1_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_systimer_target1_int_map
-                SYSTIMER_TARGET1_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  systimer target2 intr map register
-            SYSTIMER_TARGET2_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_systimer_target2_int_map
-                SYSTIMER_TARGET2_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  spi mem reject intr map register
-            SPI_MEM_REJECT_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_spi_mem_reject_intr_map
-                SPI_MEM_REJECT_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  icache perload intr map register
-            ICACHE_PRELOAD_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_icache_preload_int_map
-                ICACHE_PRELOAD_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  icache sync intr map register
-            ICACHE_SYNC_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_icache_sync_int_map
-                ICACHE_SYNC_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  adc intr map register
-            APB_ADC_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_apb_adc_int_map
-                APB_ADC_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  dma ch0 intr map register
-            DMA_CH0_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_dma_ch0_int_map
-                DMA_CH0_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  dma ch1 intr map register
-            DMA_CH1_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_dma_ch1_int_map
-                DMA_CH1_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  dma ch2 intr map register
-            DMA_CH2_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_dma_ch2_int_map
-                DMA_CH2_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  rsa intr map register
-            RSA_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_rsa_int_map
-                RSA_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  aes intr map register
-            AES_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_aes_int_map
-                AES_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  sha intr map register
-            SHA_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_sha_int_map
-                SHA_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  cpu from cpu 0 intr map register
-            CPU_INTR_FROM_CPU_0_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_intr_from_cpu_0_map
-                CPU_INTR_FROM_CPU_0_MAP: u5,
-                padding: u27,
-            }),
-            ///  cpu from cpu 0 intr map register
-            CPU_INTR_FROM_CPU_1_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_intr_from_cpu_1_map
-                CPU_INTR_FROM_CPU_1_MAP: u5,
-                padding: u27,
-            }),
-            ///  cpu from cpu 1 intr map register
-            CPU_INTR_FROM_CPU_2_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_intr_from_cpu_2_map
-                CPU_INTR_FROM_CPU_2_MAP: u5,
-                padding: u27,
-            }),
-            ///  cpu from cpu 3 intr map register
-            CPU_INTR_FROM_CPU_3_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_intr_from_cpu_3_map
-                CPU_INTR_FROM_CPU_3_MAP: u5,
-                padding: u27,
-            }),
-            ///  assist debug intr map register
-            ASSIST_DEBUG_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_assist_debug_intr_map
-                ASSIST_DEBUG_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  dma pms violatile intr map register
-            DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_dma_apbperi_pms_monitor_violate_intr_map
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  iram0 pms violatile intr map register
-            CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_core_0_iram0_pms_monitor_violate_intr_map
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_core_0_dram0_pms_monitor_violate_intr_map
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_core_0_pif_pms_monitor_violate_intr_map
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_core_0_pif_pms_monitor_violate_size_intr_map
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_SIZE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            BACKUP_PMS_VIOLATE_INTR_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_backup_pms_violate_intr_map
-                BACKUP_PMS_VIOLATE_INTR_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            CACHE_CORE0_ACS_INT_MAP: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cache_core0_acs_int_map
-                CACHE_CORE0_ACS_INT_MAP: u5,
-                padding: u27,
-            }),
-            ///  mac intr map register
-            INTR_STATUS_REG_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_intr_status_0
-                INTR_STATUS_0: u32,
-            }),
-            ///  mac intr map register
-            INTR_STATUS_REG_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_intr_status_1
-                INTR_STATUS_1: u32,
-            }),
-            ///  mac intr map register
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_reg_clk_en
-                REG_CLK_EN: u1,
-                padding: u31,
-            }),
-            ///  mac intr map register
-            CPU_INT_ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_int_enable
-                CPU_INT_ENABLE: u32,
-            }),
-            ///  mac intr map register
-            CPU_INT_TYPE: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_int_type
-                CPU_INT_TYPE: u32,
-            }),
-            ///  mac intr map register
-            CPU_INT_CLEAR: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_int_clear
-                CPU_INT_CLEAR: u32,
-            }),
-            ///  mac intr map register
-            CPU_INT_EIP_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_int_eip_status
-                CPU_INT_EIP_STATUS: u32,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_0_map
-                CPU_PRI_0_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_1_map
-                CPU_PRI_1_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_2: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_2_map
-                CPU_PRI_2_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_3: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_3_map
-                CPU_PRI_3_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_4: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_4_map
-                CPU_PRI_4_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_5: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_5_map
-                CPU_PRI_5_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_6: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_6_map
-                CPU_PRI_6_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_7: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_7_map
-                CPU_PRI_7_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_8: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_8_map
-                CPU_PRI_8_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_9: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_9_map
-                CPU_PRI_9_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_10: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_10_map
-                CPU_PRI_10_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_11: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_11_map
-                CPU_PRI_11_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_12: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_12_map
-                CPU_PRI_12_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_13: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_13_map
-                CPU_PRI_13_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_14: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_14_map
-                CPU_PRI_14_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_15: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_15_map
-                CPU_PRI_15_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_16: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_16_map
-                CPU_PRI_16_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_17: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_17_map
-                CPU_PRI_17_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_18: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_18_map
-                CPU_PRI_18_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_19: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_19_map
-                CPU_PRI_19_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_20: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_20_map
-                CPU_PRI_20_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_21: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_21_map
-                CPU_PRI_21_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_22: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_22_map
-                CPU_PRI_22_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_23: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_23_map
-                CPU_PRI_23_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_24: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_24_map
-                CPU_PRI_24_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_25: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_25_map
-                CPU_PRI_25_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_26: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_26_map
-                CPU_PRI_26_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_27: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_27_map
-                CPU_PRI_27_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_28: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_28_map
-                CPU_PRI_28_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_29: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_29_map
-                CPU_PRI_29_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_30: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_30_map
-                CPU_PRI_30_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_PRI_31: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_pri_31_map
-                CPU_PRI_31_MAP: u4,
-                padding: u28,
-            }),
-            ///  mac intr map register
-            CPU_INT_THRESH: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_cpu_int_thresh
-                CPU_INT_THRESH: u4,
-                padding: u28,
-            }),
-            reserved2044: [1636]u8,
-            ///  mac intr map register
-            INTERRUPT_REG_DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_core0_interrupt_reg_date
-                INTERRUPT_REG_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  Input/Output Multiplexer
-        pub const IO_MUX = extern struct {
-            ///  Clock Output Configuration Register
-            PIN_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  If you want to output clock for I2S to CLK_OUT_out1, set this register to 0x0. CLK_OUT_out1 can be found in peripheral output signals.
-                CLK_OUT1: u4,
-                ///  If you want to output clock for I2S to CLK_OUT_out2, set this register to 0x0. CLK_OUT_out2 can be found in peripheral output signals.
-                CLK_OUT2: u4,
-                ///  If you want to output clock for I2S to CLK_OUT_out3, set this register to 0x0. CLK_OUT_out3 can be found in peripheral output signals.
-                CLK_OUT3: u4,
-                padding: u20,
-            }),
-            ///  IO MUX Configure Register for pad XTAL_32K_P
-            GPIO: [22]mmio.Mmio(packed struct(u32) {
-                ///  Output enable of the pad in sleep mode. 1: output enabled; 0: output disabled.
-                MCU_OE: u1,
-                ///  Sleep mode selection of this pad. Set to 1 to put the pad in pad mode.
-                SLP_SEL: u1,
-                ///  Pull-down enable of the pad in sleep mode. 1: internal pull-down enabled; 0: internal pull-down disabled.
-                MCU_WPD: u1,
-                ///  Pull-up enable of the pad during sleep mode. 1: internal pull-up enabled; 0: internal pull-up disabled.
-                MCU_WPU: u1,
-                ///  Input enable of the pad during sleep mode. 1: input enabled; 0: input disabled.
-                MCU_IE: u1,
-                reserved7: u2,
-                ///  Pull-down enable of the pad. 1: internal pull-down enabled; 0: internal pull-down disabled.
-                FUN_WPD: u1,
-                ///  Pull-up enable of the pad. 1: internal pull-up enabled; 0: internal pull-up disabled.
-                FUN_WPU: u1,
-                ///  Input enable of the pad. 1: input enabled; 0: input disabled.
-                FUN_IE: u1,
-                ///  Select the drive strength of the pad. 0: ~5 mA; 1: ~10mA; 2: ~20mA; 3: ~40mA.
-                FUN_DRV: u2,
-                ///  Select IO MUX function for this signal. 0: Select Function 1; 1: Select Function 2; etc.
-                MCU_SEL: u3,
-                ///  Enable filter for pin input signals. 1: Filter enabled; 2: Filter disabled.
-                FILTER_EN: u1,
-                padding: u16,
-            }),
-            reserved252: [160]u8,
-            ///  IO MUX Version Control Register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  Version control register
-                REG_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  LED Control PWM (Pulse Width Modulation)
-        pub const LEDC = extern struct {
-            ///  LEDC_LSCH0_CONF0.
-            LSCH0_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch0.
-                TIMER_SEL_LSCH0: u2,
-                ///  reg_sig_out_en_lsch0.
-                SIG_OUT_EN_LSCH0: u1,
-                ///  reg_idle_lv_lsch0.
-                IDLE_LV_LSCH0: u1,
-                ///  reg_para_up_lsch0.
-                PARA_UP_LSCH0: u1,
-                ///  reg_ovf_num_lsch0.
-                OVF_NUM_LSCH0: u10,
-                ///  reg_ovf_cnt_en_lsch0.
-                OVF_CNT_EN_LSCH0: u1,
-                ///  reg_ovf_cnt_reset_lsch0.
-                OVF_CNT_RESET_LSCH0: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH0_HPOINT.
-            LSCH0_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch0.
-                HPOINT_LSCH0: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH0_DUTY.
-            LSCH0_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch0.
-                DUTY_LSCH0: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH0_CONF1.
-            LSCH0_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch0.
-                DUTY_SCALE_LSCH0: u10,
-                ///  reg_duty_cycle_lsch0.
-                DUTY_CYCLE_LSCH0: u10,
-                ///  reg_duty_num_lsch0.
-                DUTY_NUM_LSCH0: u10,
-                ///  reg_duty_inc_lsch0.
-                DUTY_INC_LSCH0: u1,
-                ///  reg_duty_start_lsch0.
-                DUTY_START_LSCH0: u1,
-            }),
-            ///  LEDC_LSCH0_DUTY_R.
-            LSCH0_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch0_r.
-                DUTY_LSCH0_R: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH1_CONF0.
-            LSCH1_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch1.
-                TIMER_SEL_LSCH1: u2,
-                ///  reg_sig_out_en_lsch1.
-                SIG_OUT_EN_LSCH1: u1,
-                ///  reg_idle_lv_lsch1.
-                IDLE_LV_LSCH1: u1,
-                ///  reg_para_up_lsch1.
-                PARA_UP_LSCH1: u1,
-                ///  reg_ovf_num_lsch1.
-                OVF_NUM_LSCH1: u10,
-                ///  reg_ovf_cnt_en_lsch1.
-                OVF_CNT_EN_LSCH1: u1,
-                ///  reg_ovf_cnt_reset_lsch1.
-                OVF_CNT_RESET_LSCH1: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH1_HPOINT.
-            LSCH1_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch1.
-                HPOINT_LSCH1: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH1_DUTY.
-            LSCH1_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch1.
-                DUTY_LSCH1: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH1_CONF1.
-            LSCH1_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch1.
-                DUTY_SCALE_LSCH1: u10,
-                ///  reg_duty_cycle_lsch1.
-                DUTY_CYCLE_LSCH1: u10,
-                ///  reg_duty_num_lsch1.
-                DUTY_NUM_LSCH1: u10,
-                ///  reg_duty_inc_lsch1.
-                DUTY_INC_LSCH1: u1,
-                ///  reg_duty_start_lsch1.
-                DUTY_START_LSCH1: u1,
-            }),
-            ///  LEDC_LSCH1_DUTY_R.
-            LSCH1_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch1_r.
-                DUTY_LSCH1_R: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH2_CONF0.
-            LSCH2_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch2.
-                TIMER_SEL_LSCH2: u2,
-                ///  reg_sig_out_en_lsch2.
-                SIG_OUT_EN_LSCH2: u1,
-                ///  reg_idle_lv_lsch2.
-                IDLE_LV_LSCH2: u1,
-                ///  reg_para_up_lsch2.
-                PARA_UP_LSCH2: u1,
-                ///  reg_ovf_num_lsch2.
-                OVF_NUM_LSCH2: u10,
-                ///  reg_ovf_cnt_en_lsch2.
-                OVF_CNT_EN_LSCH2: u1,
-                ///  reg_ovf_cnt_reset_lsch2.
-                OVF_CNT_RESET_LSCH2: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH2_HPOINT.
-            LSCH2_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch2.
-                HPOINT_LSCH2: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH2_DUTY.
-            LSCH2_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch2.
-                DUTY_LSCH2: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH2_CONF1.
-            LSCH2_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch2.
-                DUTY_SCALE_LSCH2: u10,
-                ///  reg_duty_cycle_lsch2.
-                DUTY_CYCLE_LSCH2: u10,
-                ///  reg_duty_num_lsch2.
-                DUTY_NUM_LSCH2: u10,
-                ///  reg_duty_inc_lsch2.
-                DUTY_INC_LSCH2: u1,
-                ///  reg_duty_start_lsch2.
-                DUTY_START_LSCH2: u1,
-            }),
-            ///  LEDC_LSCH2_DUTY_R.
-            LSCH2_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch2_r.
-                DUTY_LSCH2_R: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH3_CONF0.
-            LSCH3_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch3.
-                TIMER_SEL_LSCH3: u2,
-                ///  reg_sig_out_en_lsch3.
-                SIG_OUT_EN_LSCH3: u1,
-                ///  reg_idle_lv_lsch3.
-                IDLE_LV_LSCH3: u1,
-                ///  reg_para_up_lsch3.
-                PARA_UP_LSCH3: u1,
-                ///  reg_ovf_num_lsch3.
-                OVF_NUM_LSCH3: u10,
-                ///  reg_ovf_cnt_en_lsch3.
-                OVF_CNT_EN_LSCH3: u1,
-                ///  reg_ovf_cnt_reset_lsch3.
-                OVF_CNT_RESET_LSCH3: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH3_HPOINT.
-            LSCH3_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch3.
-                HPOINT_LSCH3: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH3_DUTY.
-            LSCH3_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch3.
-                DUTY_LSCH3: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH3_CONF1.
-            LSCH3_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch3.
-                DUTY_SCALE_LSCH3: u10,
-                ///  reg_duty_cycle_lsch3.
-                DUTY_CYCLE_LSCH3: u10,
-                ///  reg_duty_num_lsch3.
-                DUTY_NUM_LSCH3: u10,
-                ///  reg_duty_inc_lsch3.
-                DUTY_INC_LSCH3: u1,
-                ///  reg_duty_start_lsch3.
-                DUTY_START_LSCH3: u1,
-            }),
-            ///  LEDC_LSCH3_DUTY_R.
-            LSCH3_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch3_r.
-                DUTY_LSCH3_R: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH4_CONF0.
-            LSCH4_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch4.
-                TIMER_SEL_LSCH4: u2,
-                ///  reg_sig_out_en_lsch4.
-                SIG_OUT_EN_LSCH4: u1,
-                ///  reg_idle_lv_lsch4.
-                IDLE_LV_LSCH4: u1,
-                ///  reg_para_up_lsch4.
-                PARA_UP_LSCH4: u1,
-                ///  reg_ovf_num_lsch4.
-                OVF_NUM_LSCH4: u10,
-                ///  reg_ovf_cnt_en_lsch4.
-                OVF_CNT_EN_LSCH4: u1,
-                ///  reg_ovf_cnt_reset_lsch4.
-                OVF_CNT_RESET_LSCH4: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH4_HPOINT.
-            LSCH4_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch4.
-                HPOINT_LSCH4: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH4_DUTY.
-            LSCH4_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch4.
-                DUTY_LSCH4: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH4_CONF1.
-            LSCH4_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch4.
-                DUTY_SCALE_LSCH4: u10,
-                ///  reg_duty_cycle_lsch4.
-                DUTY_CYCLE_LSCH4: u10,
-                ///  reg_duty_num_lsch4.
-                DUTY_NUM_LSCH4: u10,
-                ///  reg_duty_inc_lsch4.
-                DUTY_INC_LSCH4: u1,
-                ///  reg_duty_start_lsch4.
-                DUTY_START_LSCH4: u1,
-            }),
-            ///  LEDC_LSCH4_DUTY_R.
-            LSCH4_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch4_r.
-                DUTY_LSCH4_R: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH5_CONF0.
-            LSCH5_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timer_sel_lsch5.
-                TIMER_SEL_LSCH5: u2,
-                ///  reg_sig_out_en_lsch5.
-                SIG_OUT_EN_LSCH5: u1,
-                ///  reg_idle_lv_lsch5.
-                IDLE_LV_LSCH5: u1,
-                ///  reg_para_up_lsch5.
-                PARA_UP_LSCH5: u1,
-                ///  reg_ovf_num_lsch5.
-                OVF_NUM_LSCH5: u10,
-                ///  reg_ovf_cnt_en_lsch5.
-                OVF_CNT_EN_LSCH5: u1,
-                ///  reg_ovf_cnt_reset_lsch5.
-                OVF_CNT_RESET_LSCH5: u1,
-                padding: u15,
-            }),
-            ///  LEDC_LSCH5_HPOINT.
-            LSCH5_HPOINT: mmio.Mmio(packed struct(u32) {
-                ///  reg_hpoint_lsch5.
-                HPOINT_LSCH5: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSCH5_DUTY.
-            LSCH5_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch5.
-                DUTY_LSCH5: u19,
-                padding: u13,
-            }),
-            ///  LEDC_LSCH5_CONF1.
-            LSCH5_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_scale_lsch5.
-                DUTY_SCALE_LSCH5: u10,
-                ///  reg_duty_cycle_lsch5.
-                DUTY_CYCLE_LSCH5: u10,
-                ///  reg_duty_num_lsch5.
-                DUTY_NUM_LSCH5: u10,
-                ///  reg_duty_inc_lsch5.
-                DUTY_INC_LSCH5: u1,
-                ///  reg_duty_start_lsch5.
-                DUTY_START_LSCH5: u1,
-            }),
-            ///  LEDC_LSCH5_DUTY_R.
-            LSCH5_DUTY_R: mmio.Mmio(packed struct(u32) {
-                ///  reg_duty_lsch5_r.
-                DUTY_LSCH5_R: u19,
-                padding: u13,
-            }),
-            reserved160: [40]u8,
-            ///  LEDC_LSTIMER0_CONF.
-            LSTIMER0_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_duty_res.
-                LSTIMER0_DUTY_RES: u4,
-                ///  reg_clk_div_lstimer0.
-                CLK_DIV_LSTIMER0: u18,
-                ///  reg_lstimer0_pause.
-                LSTIMER0_PAUSE: u1,
-                ///  reg_lstimer0_rst.
-                LSTIMER0_RST: u1,
-                ///  reg_tick_sel_lstimer0.
-                TICK_SEL_LSTIMER0: u1,
-                ///  reg_lstimer0_para_up.
-                LSTIMER0_PARA_UP: u1,
-                padding: u6,
-            }),
-            ///  LEDC_LSTIMER0_VALUE.
-            LSTIMER0_VALUE: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_cnt.
-                LSTIMER0_CNT: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSTIMER1_CONF.
-            LSTIMER1_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer1_duty_res.
-                LSTIMER1_DUTY_RES: u4,
-                ///  reg_clk_div_lstimer1.
-                CLK_DIV_LSTIMER1: u18,
-                ///  reg_lstimer1_pause.
-                LSTIMER1_PAUSE: u1,
-                ///  reg_lstimer1_rst.
-                LSTIMER1_RST: u1,
-                ///  reg_tick_sel_lstimer1.
-                TICK_SEL_LSTIMER1: u1,
-                ///  reg_lstimer1_para_up.
-                LSTIMER1_PARA_UP: u1,
-                padding: u6,
-            }),
-            ///  LEDC_LSTIMER1_VALUE.
-            LSTIMER1_VALUE: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer1_cnt.
-                LSTIMER1_CNT: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSTIMER2_CONF.
-            LSTIMER2_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer2_duty_res.
-                LSTIMER2_DUTY_RES: u4,
-                ///  reg_clk_div_lstimer2.
-                CLK_DIV_LSTIMER2: u18,
-                ///  reg_lstimer2_pause.
-                LSTIMER2_PAUSE: u1,
-                ///  reg_lstimer2_rst.
-                LSTIMER2_RST: u1,
-                ///  reg_tick_sel_lstimer2.
-                TICK_SEL_LSTIMER2: u1,
-                ///  reg_lstimer2_para_up.
-                LSTIMER2_PARA_UP: u1,
-                padding: u6,
-            }),
-            ///  LEDC_LSTIMER2_VALUE.
-            LSTIMER2_VALUE: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer2_cnt.
-                LSTIMER2_CNT: u14,
-                padding: u18,
-            }),
-            ///  LEDC_LSTIMER3_CONF.
-            LSTIMER3_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer3_duty_res.
-                LSTIMER3_DUTY_RES: u4,
-                ///  reg_clk_div_lstimer3.
-                CLK_DIV_LSTIMER3: u18,
-                ///  reg_lstimer3_pause.
-                LSTIMER3_PAUSE: u1,
-                ///  reg_lstimer3_rst.
-                LSTIMER3_RST: u1,
-                ///  reg_tick_sel_lstimer3.
-                TICK_SEL_LSTIMER3: u1,
-                ///  reg_lstimer3_para_up.
-                LSTIMER3_PARA_UP: u1,
-                padding: u6,
-            }),
-            ///  LEDC_LSTIMER3_VALUE.
-            LSTIMER3_VALUE: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer3_cnt.
-                LSTIMER3_CNT: u14,
-                padding: u18,
-            }),
-            ///  LEDC_INT_RAW.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_ovf_int_raw.
-                LSTIMER0_OVF_INT_RAW: u1,
-                ///  reg_lstimer1_ovf_int_raw.
-                LSTIMER1_OVF_INT_RAW: u1,
-                ///  reg_lstimer2_ovf_int_raw.
-                LSTIMER2_OVF_INT_RAW: u1,
-                ///  reg_lstimer3_ovf_int_raw.
-                LSTIMER3_OVF_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch0_int_raw.
-                DUTY_CHNG_END_LSCH0_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch1_int_raw.
-                DUTY_CHNG_END_LSCH1_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch2_int_raw.
-                DUTY_CHNG_END_LSCH2_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch3_int_raw.
-                DUTY_CHNG_END_LSCH3_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch4_int_raw.
-                DUTY_CHNG_END_LSCH4_INT_RAW: u1,
-                ///  reg_duty_chng_end_lsch5_int_raw.
-                DUTY_CHNG_END_LSCH5_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch0_int_raw.
-                OVF_CNT_LSCH0_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch1_int_raw.
-                OVF_CNT_LSCH1_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch2_int_raw.
-                OVF_CNT_LSCH2_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch3_int_raw.
-                OVF_CNT_LSCH3_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch4_int_raw.
-                OVF_CNT_LSCH4_INT_RAW: u1,
-                ///  reg_ovf_cnt_lsch5_int_raw.
-                OVF_CNT_LSCH5_INT_RAW: u1,
-                padding: u16,
-            }),
-            ///  LEDC_INT_ST.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_ovf_int_st.
-                LSTIMER0_OVF_INT_ST: u1,
-                ///  reg_lstimer1_ovf_int_st.
-                LSTIMER1_OVF_INT_ST: u1,
-                ///  reg_lstimer2_ovf_int_st.
-                LSTIMER2_OVF_INT_ST: u1,
-                ///  reg_lstimer3_ovf_int_st.
-                LSTIMER3_OVF_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch0_int_st.
-                DUTY_CHNG_END_LSCH0_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch1_int_st.
-                DUTY_CHNG_END_LSCH1_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch2_int_st.
-                DUTY_CHNG_END_LSCH2_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch3_int_st.
-                DUTY_CHNG_END_LSCH3_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch4_int_st.
-                DUTY_CHNG_END_LSCH4_INT_ST: u1,
-                ///  reg_duty_chng_end_lsch5_int_st.
-                DUTY_CHNG_END_LSCH5_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch0_int_st.
-                OVF_CNT_LSCH0_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch1_int_st.
-                OVF_CNT_LSCH1_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch2_int_st.
-                OVF_CNT_LSCH2_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch3_int_st.
-                OVF_CNT_LSCH3_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch4_int_st.
-                OVF_CNT_LSCH4_INT_ST: u1,
-                ///  reg_ovf_cnt_lsch5_int_st.
-                OVF_CNT_LSCH5_INT_ST: u1,
-                padding: u16,
-            }),
-            ///  LEDC_INT_ENA.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_ovf_int_ena.
-                LSTIMER0_OVF_INT_ENA: u1,
-                ///  reg_lstimer1_ovf_int_ena.
-                LSTIMER1_OVF_INT_ENA: u1,
-                ///  reg_lstimer2_ovf_int_ena.
-                LSTIMER2_OVF_INT_ENA: u1,
-                ///  reg_lstimer3_ovf_int_ena.
-                LSTIMER3_OVF_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch0_int_ena.
-                DUTY_CHNG_END_LSCH0_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch1_int_ena.
-                DUTY_CHNG_END_LSCH1_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch2_int_ena.
-                DUTY_CHNG_END_LSCH2_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch3_int_ena.
-                DUTY_CHNG_END_LSCH3_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch4_int_ena.
-                DUTY_CHNG_END_LSCH4_INT_ENA: u1,
-                ///  reg_duty_chng_end_lsch5_int_ena.
-                DUTY_CHNG_END_LSCH5_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch0_int_ena.
-                OVF_CNT_LSCH0_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch1_int_ena.
-                OVF_CNT_LSCH1_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch2_int_ena.
-                OVF_CNT_LSCH2_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch3_int_ena.
-                OVF_CNT_LSCH3_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch4_int_ena.
-                OVF_CNT_LSCH4_INT_ENA: u1,
-                ///  reg_ovf_cnt_lsch5_int_ena.
-                OVF_CNT_LSCH5_INT_ENA: u1,
-                padding: u16,
-            }),
-            ///  LEDC_INT_CLR.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  reg_lstimer0_ovf_int_clr.
-                LSTIMER0_OVF_INT_CLR: u1,
-                ///  reg_lstimer1_ovf_int_clr.
-                LSTIMER1_OVF_INT_CLR: u1,
-                ///  reg_lstimer2_ovf_int_clr.
-                LSTIMER2_OVF_INT_CLR: u1,
-                ///  reg_lstimer3_ovf_int_clr.
-                LSTIMER3_OVF_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch0_int_clr.
-                DUTY_CHNG_END_LSCH0_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch1_int_clr.
-                DUTY_CHNG_END_LSCH1_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch2_int_clr.
-                DUTY_CHNG_END_LSCH2_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch3_int_clr.
-                DUTY_CHNG_END_LSCH3_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch4_int_clr.
-                DUTY_CHNG_END_LSCH4_INT_CLR: u1,
-                ///  reg_duty_chng_end_lsch5_int_clr.
-                DUTY_CHNG_END_LSCH5_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch0_int_clr.
-                OVF_CNT_LSCH0_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch1_int_clr.
-                OVF_CNT_LSCH1_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch2_int_clr.
-                OVF_CNT_LSCH2_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch3_int_clr.
-                OVF_CNT_LSCH3_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch4_int_clr.
-                OVF_CNT_LSCH4_INT_CLR: u1,
-                ///  reg_ovf_cnt_lsch5_int_clr.
-                OVF_CNT_LSCH5_INT_CLR: u1,
-                padding: u16,
-            }),
-            ///  LEDC_CONF.
-            CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_apb_clk_sel.
-                APB_CLK_SEL: u2,
-                reserved31: u29,
-                ///  reg_clk_en.
-                CLK_EN: u1,
-            }),
-            reserved252: [40]u8,
-            ///  LEDC_DATE.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_ledc_date.
-                LEDC_DATE: u32,
-            }),
-        };
-
-        ///  Remote Control Peripheral
-        pub const RMT = extern struct {
-            ///  RMT_CH0DATA_REG.
-            CH0DATA: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                DATA: u32,
-            }),
-            ///  RMT_CH1DATA_REG.
-            CH1DATA: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                DATA: u32,
-            }),
-            ///  RMT_CH2DATA_REG.
-            CH2DATA: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                DATA: u32,
-            }),
-            ///  RMT_CH3DATA_REG.
-            CH3DATA: mmio.Mmio(packed struct(u32) {
-                ///  Reserved.
-                DATA: u32,
-            }),
-            reserved28: [12]u8,
-            ///  RMT_CH2CONF1_REG.
-            CH2CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_rx_en_ch2.
-                RX_EN: u1,
-                ///  reg_mem_wr_rst_ch2.
-                MEM_WR_RST: u1,
-                ///  reg_apb_mem_rst_ch2.
-                APB_MEM_RST: u1,
-                ///  reg_mem_owner_ch2.
-                MEM_OWNER: u1,
-                ///  reg_rx_filter_en_ch2.
-                RX_FILTER_EN: u1,
-                ///  reg_rx_filter_thres_ch2.
-                RX_FILTER_THRES: u8,
-                ///  reg_mem_rx_wrap_en_ch2.
-                MEM_RX_WRAP_EN: u1,
-                ///  reg_afifo_rst_ch2.
-                AFIFO_RST: u1,
-                ///  reg_conf_update_ch2.
-                CONF_UPDATE: u1,
-                padding: u16,
-            }),
-            reserved36: [4]u8,
-            ///  RMT_CH3CONF1_REG.
-            CH3CONF1: mmio.Mmio(packed struct(u32) {
-                ///  reg_rx_en_ch3.
-                RX_EN: u1,
-                ///  reg_mem_wr_rst_ch3.
-                MEM_WR_RST: u1,
-                ///  reg_apb_mem_rst_ch3.
-                APB_MEM_RST: u1,
-                ///  reg_mem_owner_ch3.
-                MEM_OWNER: u1,
-                ///  reg_rx_filter_en_ch3.
-                RX_FILTER_EN: u1,
-                ///  reg_rx_filter_thres_ch3.
-                RX_FILTER_THRES: u8,
-                ///  reg_mem_rx_wrap_en_ch3.
-                MEM_RX_WRAP_EN: u1,
-                ///  reg_afifo_rst_ch3.
-                AFIFO_RST: u1,
-                ///  reg_conf_update_ch3.
-                CONF_UPDATE: u1,
-                padding: u16,
-            }),
-            ///  RMT_CH0STATUS_REG.
-            CH0STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_mem_raddr_ex_ch0.
-                MEM_RADDR_EX: u9,
-                ///  reg_state_ch0.
-                STATE: u3,
-                ///  reg_apb_mem_waddr_ch0.
-                APB_MEM_WADDR: u9,
-                ///  reg_apb_mem_rd_err_ch0.
-                APB_MEM_RD_ERR: u1,
-                ///  reg_mem_empty_ch0.
-                MEM_EMPTY: u1,
-                ///  reg_apb_mem_wr_err_ch0.
-                APB_MEM_WR_ERR: u1,
-                ///  reg_apb_mem_raddr_ch0.
-                APB_MEM_RADDR: u8,
-            }),
-            ///  RMT_CH1STATUS_REG.
-            CH1STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_mem_raddr_ex_ch1.
-                MEM_RADDR_EX: u9,
-                ///  reg_state_ch1.
-                STATE: u3,
-                ///  reg_apb_mem_waddr_ch1.
-                APB_MEM_WADDR: u9,
-                ///  reg_apb_mem_rd_err_ch1.
-                APB_MEM_RD_ERR: u1,
-                ///  reg_mem_empty_ch1.
-                MEM_EMPTY: u1,
-                ///  reg_apb_mem_wr_err_ch1.
-                APB_MEM_WR_ERR: u1,
-                ///  reg_apb_mem_raddr_ch1.
-                APB_MEM_RADDR: u8,
-            }),
-            ///  RMT_CH2STATUS_REG.
-            CH2STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_mem_waddr_ex_ch2.
-                MEM_WADDR_EX: u9,
-                reserved12: u3,
-                ///  reg_apb_mem_raddr_ch2.
-                APB_MEM_RADDR: u9,
-                reserved22: u1,
-                ///  reg_state_ch2.
-                STATE: u3,
-                ///  reg_mem_owner_err_ch2.
-                MEM_OWNER_ERR: u1,
-                ///  reg_mem_full_ch2.
-                MEM_FULL: u1,
-                ///  reg_apb_mem_rd_err_ch2.
-                APB_MEM_RD_ERR: u1,
-                padding: u4,
-            }),
-            ///  RMT_CH3STATUS_REG.
-            CH3STATUS: mmio.Mmio(packed struct(u32) {
-                ///  reg_mem_waddr_ex_ch3.
-                MEM_WADDR_EX: u9,
-                reserved12: u3,
-                ///  reg_apb_mem_raddr_ch3.
-                APB_MEM_RADDR: u9,
-                reserved22: u1,
-                ///  reg_state_ch3.
-                STATE: u3,
-                ///  reg_mem_owner_err_ch3.
-                MEM_OWNER_ERR: u1,
-                ///  reg_mem_full_ch3.
-                MEM_FULL: u1,
-                ///  reg_apb_mem_rd_err_ch3.
-                APB_MEM_RD_ERR: u1,
-                padding: u4,
-            }),
-            ///  RMT_INT_RAW_REG.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                reserved10: u10,
-                ///  reg_ch2_rx_thr_event_int_raw.
-                CH2_RX_THR_EVENT_INT_RAW: u1,
-                ///  reg_ch3_rx_thr_event_int_raw.
-                CH3_RX_THR_EVENT_INT_RAW: u1,
-                padding: u20,
-            }),
-            ///  RMT_INT_ST_REG.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                reserved10: u10,
-                ///  reg_ch2_rx_thr_event_int_st.
-                CH2_RX_THR_EVENT_INT_ST: u1,
-                ///  reg_ch3_rx_thr_event_int_st.
-                CH3_RX_THR_EVENT_INT_ST: u1,
-                padding: u20,
-            }),
-            ///  RMT_INT_ENA_REG.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                reserved10: u10,
-                ///  reg_ch2_rx_thr_event_int_ena.
-                CH2_RX_THR_EVENT_INT_ENA: u1,
-                ///  reg_ch3_rx_thr_event_int_ena.
-                CH3_RX_THR_EVENT_INT_ENA: u1,
-                padding: u20,
-            }),
-            ///  RMT_INT_CLR_REG.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                reserved10: u10,
-                ///  reg_ch2_rx_thr_event_int_clr.
-                CH2_RX_THR_EVENT_INT_CLR: u1,
-                ///  reg_ch3_rx_thr_event_int_clr.
-                CH3_RX_THR_EVENT_INT_CLR: u1,
-                padding: u20,
-            }),
-            ///  RMT_CH0CARRIER_DUTY_REG.
-            CH0CARRIER_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_carrier_low_ch0.
-                CARRIER_LOW: u16,
-                ///  reg_carrier_high_ch0.
-                CARRIER_HIGH: u16,
-            }),
-            ///  RMT_CH1CARRIER_DUTY_REG.
-            CH1CARRIER_DUTY: mmio.Mmio(packed struct(u32) {
-                ///  reg_carrier_low_ch1.
-                CARRIER_LOW: u16,
-                ///  reg_carrier_high_ch1.
-                CARRIER_HIGH: u16,
-            }),
-            ///  RMT_CH2_RX_CARRIER_RM_REG.
-            CH2_RX_CARRIER_RM: mmio.Mmio(packed struct(u32) {
-                ///  reg_carrier_low_thres_ch2.
-                CARRIER_LOW_THRES: u16,
-                ///  reg_carrier_high_thres_ch2.
-                CARRIER_HIGH_THRES: u16,
-            }),
-            ///  RMT_CH3_RX_CARRIER_RM_REG.
-            CH3_RX_CARRIER_RM: mmio.Mmio(packed struct(u32) {
-                ///  reg_carrier_low_thres_ch3.
-                CARRIER_LOW_THRES: u16,
-                ///  reg_carrier_high_thres_ch3.
-                CARRIER_HIGH_THRES: u16,
-            }),
-            reserved104: [16]u8,
-            ///  RMT_SYS_CONF_REG.
-            SYS_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_apb_fifo_mask.
-                APB_FIFO_MASK: u1,
-                ///  reg_mem_clk_force_on.
-                MEM_CLK_FORCE_ON: u1,
-                ///  reg_rmt_mem_force_pd.
-                MEM_FORCE_PD: u1,
-                ///  reg_rmt_mem_force_pu.
-                MEM_FORCE_PU: u1,
-                ///  reg_rmt_sclk_div_num.
-                SCLK_DIV_NUM: u8,
-                ///  reg_rmt_sclk_div_a.
-                SCLK_DIV_A: u6,
-                ///  reg_rmt_sclk_div_b.
-                SCLK_DIV_B: u6,
-                ///  reg_rmt_sclk_sel.
-                SCLK_SEL: u2,
-                ///  reg_rmt_sclk_active.
-                SCLK_ACTIVE: u1,
-                reserved31: u4,
-                ///  reg_clk_en.
-                CLK_EN: u1,
-            }),
-            ///  RMT_TX_SIM_REG.
-            TX_SIM: mmio.Mmio(packed struct(u32) {
-                ///  reg_rmt_tx_sim_ch0.
-                TX_SIM_CH0: u1,
-                ///  reg_rmt_tx_sim_ch1.
-                TX_SIM_CH1: u1,
-                ///  reg_rmt_tx_sim_en.
-                TX_SIM_EN: u1,
-                padding: u29,
-            }),
-            ///  RMT_REF_CNT_RST_REG.
-            REF_CNT_RST: mmio.Mmio(packed struct(u32) {
-                ///  reg_ref_cnt_rst_ch0.
-                CH0: u1,
-                ///  reg_ref_cnt_rst_ch1.
-                CH1: u1,
-                ///  reg_ref_cnt_rst_ch2.
-                CH2: u1,
-                ///  reg_ref_cnt_rst_ch3.
-                CH3: u1,
-                padding: u28,
-            }),
-            reserved204: [88]u8,
-            ///  RMT_DATE_REG.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_rmt_date.
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  Hardware random number generator
-        pub const RNG = extern struct {
-            reserved176: [176]u8,
-            ///  Random number data
-            DATA: u32,
-        };
-
-        ///  RSA (Rivest Shamir Adleman) Accelerator
-        pub const RSA = extern struct {
-            ///  The memory that stores M
-            M_MEM: [16]u8,
-            reserved512: [496]u8,
-            ///  The memory that stores Z
-            Z_MEM: [16]u8,
-            reserved1024: [496]u8,
-            ///  The memory that stores Y
-            Y_MEM: [16]u8,
-            reserved1536: [496]u8,
-            ///  The memory that stores X
-            X_MEM: [16]u8,
-            reserved2048: [496]u8,
-            ///  RSA M_prime register
-            M_PRIME: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores m'
-                M_PRIME: u32,
-            }),
-            ///  RSA mode register
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  rsa mode (rsa length).
-                MODE: u7,
-                padding: u25,
-            }),
-            ///  RSA query clean register
-            QUERY_CLEAN: mmio.Mmio(packed struct(u32) {
-                ///  query clean
-                QUERY_CLEAN: u1,
-                padding: u31,
-            }),
-            ///  RSA modular exponentiation trigger register.
-            SET_START_MODEXP: mmio.Mmio(packed struct(u32) {
-                ///  start modular exponentiation
-                SET_START_MODEXP: u1,
-                padding: u31,
-            }),
-            ///  RSA modular multiplication trigger register.
-            SET_START_MODMULT: mmio.Mmio(packed struct(u32) {
-                ///  start modular multiplication
-                SET_START_MODMULT: u1,
-                padding: u31,
-            }),
-            ///  RSA normal multiplication trigger register.
-            SET_START_MULT: mmio.Mmio(packed struct(u32) {
-                ///  start multiplicaiton
-                SET_START_MULT: u1,
-                padding: u31,
-            }),
-            ///  RSA query idle register
-            QUERY_IDLE: mmio.Mmio(packed struct(u32) {
-                ///  query rsa idle. 1'b0: busy, 1'b1: idle
-                QUERY_IDLE: u1,
-                padding: u31,
-            }),
-            ///  RSA interrupt clear register
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  set this bit to clear RSA interrupt.
-                CLEAR_INTERRUPT: u1,
-                padding: u31,
-            }),
-            ///  RSA constant time option register
-            CONSTANT_TIME: mmio.Mmio(packed struct(u32) {
-                ///  Configure this bit to 0 for acceleration. 0: with acceleration, 1: without acceleration(defalut).
-                CONSTANT_TIME: u1,
-                padding: u31,
-            }),
-            ///  RSA search option
-            SEARCH_ENABLE: mmio.Mmio(packed struct(u32) {
-                ///  Configure this bit to 1 for acceleration. 1: with acceleration, 0: without acceleration(default). This option should be used together with RSA_SEARCH_POS.
-                SEARCH_ENABLE: u1,
-                padding: u31,
-            }),
-            ///  RSA search position configure register
-            SEARCH_POS: mmio.Mmio(packed struct(u32) {
-                ///  Configure this field to set search position. This field should be used together with RSA_SEARCH_ENABLE. The field is only meaningful when RSA_SEARCH_ENABLE is high.
-                SEARCH_POS: u12,
-                padding: u20,
-            }),
-            ///  RSA interrupt enable register
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to enable interrupt that occurs when rsa calculation is done. 1'b0: disable, 1'b1: enable(default).
-                INT_ENA: u1,
-                padding: u31,
-            }),
-            ///  RSA version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  rsa version information
-                DATE: u30,
-                padding: u2,
-            }),
-        };
-
-        ///  Real-Time Clock Control
-        pub const RTC_CNTL = extern struct {
-            ///  rtc configure register
-            OPTIONS0: mmio.Mmio(packed struct(u32) {
-                ///  {reg_sw_stall_appcpu_c1[5:0], reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU
-                SW_STALL_APPCPU_C0: u2,
-                ///  {reg_sw_stall_procpu_c1[5:0], reg_sw_stall_procpu_c0[1:0]} == 0x86 will stall PRO CPU
-                SW_STALL_PROCPU_C0: u2,
-                ///  APP CPU SW reset
-                SW_APPCPU_RST: u1,
-                ///  PRO CPU SW reset
-                SW_PROCPU_RST: u1,
-                ///  BB_I2C force power down
-                BB_I2C_FORCE_PD: u1,
-                ///  BB_I2C force power up
-                BB_I2C_FORCE_PU: u1,
-                ///  BB_PLL _I2C force power down
-                BBPLL_I2C_FORCE_PD: u1,
-                ///  BB_PLL_I2C force power up
-                BBPLL_I2C_FORCE_PU: u1,
-                ///  BB_PLL force power down
-                BBPLL_FORCE_PD: u1,
-                ///  BB_PLL force power up
-                BBPLL_FORCE_PU: u1,
-                ///  crystall force power down
-                XTL_FORCE_PD: u1,
-                ///  crystall force power up
-                XTL_FORCE_PU: u1,
-                ///  wait bias_sleep and current source wakeup
-                XTL_EN_WAIT: u4,
-                reserved20: u2,
-                ///  analog configure
-                XTL_EXT_CTR_SEL: u3,
-                ///  analog configure
-                XTL_FORCE_ISO: u1,
-                ///  analog configure
-                PLL_FORCE_ISO: u1,
-                ///  analog configure
-                ANALOG_FORCE_ISO: u1,
-                ///  analog configure
-                XTL_FORCE_NOISO: u1,
-                ///  analog configure
-                PLL_FORCE_NOISO: u1,
-                ///  analog configure
-                ANALOG_FORCE_NOISO: u1,
-                ///  digital wrap force reset in deep sleep
-                DG_WRAP_FORCE_RST: u1,
-                ///  digital core force no reset in deep sleep
-                DG_WRAP_FORCE_NORST: u1,
-                ///  SW system reset
-                SW_SYS_RST: u1,
-            }),
-            ///  rtc configure register
-            SLP_TIMER0: mmio.Mmio(packed struct(u32) {
-                ///  configure the sleep time
-                SLP_VAL_LO: u32,
-            }),
-            ///  rtc configure register
-            SLP_TIMER1: mmio.Mmio(packed struct(u32) {
-                ///  RTC sleep timer high 16 bits
-                SLP_VAL_HI: u16,
-                ///  timer alarm enable bit
-                RTC_MAIN_TIMER_ALARM_EN: u1,
-                padding: u15,
-            }),
-            ///  rtc configure register
-            TIME_UPDATE: mmio.Mmio(packed struct(u32) {
-                reserved27: u27,
-                ///  Enable to record system stall time
-                TIMER_SYS_STALL: u1,
-                ///  Enable to record 40M XTAL OFF time
-                TIMER_XTL_OFF: u1,
-                ///  enable to record system reset time
-                TIMER_SYS_RST: u1,
-                reserved31: u1,
-                ///  Set 1: to update register with RTC timer
-                RTC_TIME_UPDATE: u1,
-            }),
-            ///  rtc configure register
-            TIME_LOW0: mmio.Mmio(packed struct(u32) {
-                ///  RTC timer low 32 bits
-                RTC_TIMER_VALUE0_LOW: u32,
-            }),
-            ///  rtc configure register
-            TIME_HIGH0: mmio.Mmio(packed struct(u32) {
-                ///  RTC timer high 16 bits
-                RTC_TIMER_VALUE0_HIGH: u16,
-                padding: u16,
-            }),
-            ///  rtc configure register
-            STATE0: mmio.Mmio(packed struct(u32) {
-                ///  rtc software interrupt to main cpu
-                RTC_SW_CPU_INT: u1,
-                ///  clear rtc sleep reject cause
-                RTC_SLP_REJECT_CAUSE_CLR: u1,
-                reserved22: u20,
-                ///  1: APB to RTC using bridge
-                APB2RTC_BRIDGE_SEL: u1,
-                reserved28: u5,
-                ///  SDIO active indication
-                SDIO_ACTIVE_IND: u1,
-                ///  leep wakeup bit
-                SLP_WAKEUP: u1,
-                ///  leep reject bit
-                SLP_REJECT: u1,
-                ///  sleep enable bit
-                SLEEP_EN: u1,
-            }),
-            ///  rtc configure register
-            TIMER1: mmio.Mmio(packed struct(u32) {
-                ///  CPU stall enable bit
-                CPU_STALL_EN: u1,
-                ///  CPU stall wait cycles in fast_clk_rtc
-                CPU_STALL_WAIT: u5,
-                ///  CK8M wait cycles in slow_clk_rtc
-                CK8M_WAIT: u8,
-                ///  XTAL wait cycles in slow_clk_rtc
-                XTL_BUF_WAIT: u10,
-                ///  PLL wait cycles in slow_clk_rtc
-                PLL_BUF_WAIT: u8,
-            }),
-            ///  rtc configure register
-            TIMER2: mmio.Mmio(packed struct(u32) {
-                reserved24: u24,
-                ///  minimal cycles in slow_clk_rtc for CK8M in power down state
-                MIN_TIME_CK8M_OFF: u8,
-            }),
-            ///  rtc configure register
-            TIMER3: mmio.Mmio(packed struct(u32) {
-                ///  wifi power domain wakeup time
-                WIFI_WAIT_TIMER: u9,
-                ///  wifi power domain power on time
-                WIFI_POWERUP_TIMER: u7,
-                ///  bt power domain wakeup time
-                BT_WAIT_TIMER: u9,
-                ///  bt power domain power on time
-                BT_POWERUP_TIMER: u7,
-            }),
-            ///  rtc configure register
-            TIMER4: mmio.Mmio(packed struct(u32) {
-                ///  cpu top power domain wakeup time
-                CPU_TOP_WAIT_TIMER: u9,
-                ///  cpu top power domain power on time
-                CPU_TOP_POWERUP_TIMER: u7,
-                ///  digital wrap power domain wakeup time
-                DG_WRAP_WAIT_TIMER: u9,
-                ///  digital wrap power domain power on time
-                DG_WRAP_POWERUP_TIMER: u7,
-            }),
-            ///  rtc configure register
-            TIMER5: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  minimal sleep cycles in slow_clk_rtc
-                MIN_SLP_VAL: u8,
-                padding: u16,
-            }),
-            ///  rtc configure register
-            TIMER6: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  digital peri power domain wakeup time
-                DG_PERI_WAIT_TIMER: u9,
-                ///  digital peri power domain power on time
-                DG_PERI_POWERUP_TIMER: u7,
-            }),
-            ///  rtc configure register
-            ANA_CONF: mmio.Mmio(packed struct(u32) {
-                reserved18: u18,
-                ///  force no bypass i2c power on reset
-                RESET_POR_FORCE_PD: u1,
-                ///  force bypass i2c power on reset
-                RESET_POR_FORCE_PU: u1,
-                ///  enable glitch reset
-                GLITCH_RST_EN: u1,
-                reserved22: u1,
-                ///  PLLA force power up
-                SAR_I2C_PU: u1,
-                ///  PLLA force power down
-                PLLA_FORCE_PD: u1,
-                ///  PLLA force power up
-                PLLA_FORCE_PU: u1,
-                ///  start BBPLL calibration during sleep
-                BBPLL_CAL_SLP_START: u1,
-                ///  1: PVTMON power up
-                PVTMON_PU: u1,
-                ///  1: TXRF_I2C power up
-                TXRF_I2C_PU: u1,
-                ///  1: RFRX_PBUS power up
-                RFRX_PBUS_PU: u1,
-                reserved30: u1,
-                ///  1: CKGEN_I2C power up
-                CKGEN_I2C_PU: u1,
-                ///  power up pll i2c
-                PLL_I2C_PU: u1,
-            }),
-            ///  rtc configure register
-            RESET_STATE: mmio.Mmio(packed struct(u32) {
-                ///  reset cause of PRO CPU
-                RESET_CAUSE_PROCPU: u6,
-                ///  reset cause of APP CPU
-                RESET_CAUSE_APPCPU: u6,
-                ///  APP CPU state vector sel
-                STAT_VECTOR_SEL_APPCPU: u1,
-                ///  PRO CPU state vector sel
-                STAT_VECTOR_SEL_PROCPU: u1,
-                ///  PRO CPU reset_flag
-                ALL_RESET_FLAG_PROCPU: u1,
-                ///  APP CPU reset flag
-                ALL_RESET_FLAG_APPCPU: u1,
-                ///  clear PRO CPU reset_flag
-                ALL_RESET_FLAG_CLR_PROCPU: u1,
-                ///  clear APP CPU reset flag
-                ALL_RESET_FLAG_CLR_APPCPU: u1,
-                ///  APPCPU OcdHaltOnReset
-                OCD_HALT_ON_RESET_APPCPU: u1,
-                ///  PROCPU OcdHaltOnReset
-                OCD_HALT_ON_RESET_PROCPU: u1,
-                ///  configure jtag reset configure
-                JTAG_RESET_FLAG_PROCPU: u1,
-                ///  configure jtag reset configure
-                JTAG_RESET_FLAG_APPCPU: u1,
-                ///  configure jtag reset configure
-                JTAG_RESET_FLAG_CLR_PROCPU: u1,
-                ///  configure jtag reset configure
-                JTAG_RESET_FLAG_CLR_APPCPU: u1,
-                ///  configure dreset configure
-                RTC_DRESET_MASK_APPCPU: u1,
-                ///  configure dreset configure
-                RTC_DRESET_MASK_PROCPU: u1,
-                padding: u6,
-            }),
-            ///  rtc configure register
-            WAKEUP_STATE: mmio.Mmio(packed struct(u32) {
-                reserved15: u15,
-                ///  wakeup enable bitmap
-                RTC_WAKEUP_ENA: u17,
-            }),
-            ///  rtc configure register
-            INT_ENA_RTC: mmio.Mmio(packed struct(u32) {
-                ///  enable sleep wakeup interrupt
-                SLP_WAKEUP_INT_ENA: u1,
-                ///  enable sleep reject interrupt
-                SLP_REJECT_INT_ENA: u1,
-                reserved3: u1,
-                ///  enable RTC WDT interrupt
-                RTC_WDT_INT_ENA: u1,
-                reserved9: u5,
-                ///  enable brown out interrupt
-                RTC_BROWN_OUT_INT_ENA: u1,
-                ///  enable RTC main timer interrupt
-                RTC_MAIN_TIMER_INT_ENA: u1,
-                reserved15: u4,
-                ///  enable super watch dog interrupt
-                RTC_SWD_INT_ENA: u1,
-                ///  enable xtal32k_dead interrupt
-                RTC_XTAL32K_DEAD_INT_ENA: u1,
-                reserved19: u2,
-                ///  enbale gitch det interrupt
-                RTC_GLITCH_DET_INT_ENA: u1,
-                ///  enbale bbpll cal end interrupt
-                RTC_BBPLL_CAL_INT_ENA: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            INT_RAW_RTC: mmio.Mmio(packed struct(u32) {
-                ///  sleep wakeup interrupt raw
-                SLP_WAKEUP_INT_RAW: u1,
-                ///  sleep reject interrupt raw
-                SLP_REJECT_INT_RAW: u1,
-                reserved3: u1,
-                ///  RTC WDT interrupt raw
-                RTC_WDT_INT_RAW: u1,
-                reserved9: u5,
-                ///  brown out interrupt raw
-                RTC_BROWN_OUT_INT_RAW: u1,
-                ///  RTC main timer interrupt raw
-                RTC_MAIN_TIMER_INT_RAW: u1,
-                reserved15: u4,
-                ///  super watch dog interrupt raw
-                RTC_SWD_INT_RAW: u1,
-                ///  xtal32k dead detection interrupt raw
-                RTC_XTAL32K_DEAD_INT_RAW: u1,
-                reserved19: u2,
-                ///  glitch_det_interrupt_raw
-                RTC_GLITCH_DET_INT_RAW: u1,
-                ///  bbpll cal end interrupt state
-                RTC_BBPLL_CAL_INT_RAW: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            INT_ST_RTC: mmio.Mmio(packed struct(u32) {
-                ///  sleep wakeup interrupt state
-                SLP_WAKEUP_INT_ST: u1,
-                ///  sleep reject interrupt state
-                SLP_REJECT_INT_ST: u1,
-                reserved3: u1,
-                ///  RTC WDT interrupt state
-                RTC_WDT_INT_ST: u1,
-                reserved9: u5,
-                ///  brown out interrupt state
-                RTC_BROWN_OUT_INT_ST: u1,
-                ///  RTC main timer interrupt state
-                RTC_MAIN_TIMER_INT_ST: u1,
-                reserved15: u4,
-                ///  super watch dog interrupt state
-                RTC_SWD_INT_ST: u1,
-                ///  xtal32k dead detection interrupt state
-                RTC_XTAL32K_DEAD_INT_ST: u1,
-                reserved19: u2,
-                ///  glitch_det_interrupt state
-                RTC_GLITCH_DET_INT_ST: u1,
-                ///  bbpll cal end interrupt state
-                RTC_BBPLL_CAL_INT_ST: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            INT_CLR_RTC: mmio.Mmio(packed struct(u32) {
-                ///  Clear sleep wakeup interrupt state
-                SLP_WAKEUP_INT_CLR: u1,
-                ///  Clear sleep reject interrupt state
-                SLP_REJECT_INT_CLR: u1,
-                reserved3: u1,
-                ///  Clear RTC WDT interrupt state
-                RTC_WDT_INT_CLR: u1,
-                reserved9: u5,
-                ///  Clear brown out interrupt state
-                RTC_BROWN_OUT_INT_CLR: u1,
-                ///  Clear RTC main timer interrupt state
-                RTC_MAIN_TIMER_INT_CLR: u1,
-                reserved15: u4,
-                ///  Clear super watch dog interrupt state
-                RTC_SWD_INT_CLR: u1,
-                ///  Clear RTC WDT interrupt state
-                RTC_XTAL32K_DEAD_INT_CLR: u1,
-                reserved19: u2,
-                ///  Clear glitch det interrupt state
-                RTC_GLITCH_DET_INT_CLR: u1,
-                ///  clear bbpll cal end interrupt state
-                RTC_BBPLL_CAL_INT_CLR: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            STORE0: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH0: u32,
-            }),
-            ///  rtc configure register
-            STORE1: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH1: u32,
-            }),
-            ///  rtc configure register
-            STORE2: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH2: u32,
-            }),
-            ///  rtc configure register
-            STORE3: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH3: u32,
-            }),
-            ///  rtc configure register
-            EXT_XTL_CONF: mmio.Mmio(packed struct(u32) {
-                ///  xtal 32k watch dog enable
-                XTAL32K_WDT_EN: u1,
-                ///  xtal 32k watch dog clock force on
-                XTAL32K_WDT_CLK_FO: u1,
-                ///  xtal 32k watch dog sw reset
-                XTAL32K_WDT_RESET: u1,
-                ///  xtal 32k external xtal clock force on
-                XTAL32K_EXT_CLK_FO: u1,
-                ///  xtal 32k switch to back up clock when xtal is dead
-                XTAL32K_AUTO_BACKUP: u1,
-                ///  xtal 32k restart xtal when xtal is dead
-                XTAL32K_AUTO_RESTART: u1,
-                ///  xtal 32k switch back xtal when xtal is restarted
-                XTAL32K_AUTO_RETURN: u1,
-                ///  Xtal 32k xpd control by sw or fsm
-                XTAL32K_XPD_FORCE: u1,
-                ///  apply an internal clock to help xtal 32k to start
-                ENCKINIT_XTAL_32K: u1,
-                ///  0: single-end buffer 1: differential buffer
-                DBUF_XTAL_32K: u1,
-                ///  xtal_32k gm control
-                DGM_XTAL_32K: u3,
-                ///  DRES_XTAL_32K
-                DRES_XTAL_32K: u3,
-                ///  XPD_XTAL_32K
-                XPD_XTAL_32K: u1,
-                ///  DAC_XTAL_32K
-                DAC_XTAL_32K: u3,
-                ///  state of 32k_wdt
-                RTC_WDT_STATE: u3,
-                ///  XTAL_32K sel. 0: external XTAL_32K
-                RTC_XTAL32K_GPIO_SEL: u1,
-                reserved30: u6,
-                ///  0: power down XTAL at high level
-                XTL_EXT_CTR_LV: u1,
-                ///  enable gpio configure xtal power on
-                XTL_EXT_CTR_EN: u1,
-            }),
-            ///  rtc configure register
-            EXT_WAKEUP_CONF: mmio.Mmio(packed struct(u32) {
-                reserved31: u31,
-                ///  enable filter for gpio wakeup event
-                GPIO_WAKEUP_FILTER: u1,
-            }),
-            ///  rtc configure register
-            SLP_REJECT_CONF: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  sleep reject enable
-                RTC_SLEEP_REJECT_ENA: u18,
-                ///  enable reject for light sleep
-                LIGHT_SLP_REJECT_EN: u1,
-                ///  enable reject for deep sleep
-                DEEP_SLP_REJECT_EN: u1,
-            }),
-            ///  rtc configure register
-            CPU_PERIOD_CONF: mmio.Mmio(packed struct(u32) {
-                reserved29: u29,
-                ///  CPU sel option
-                RTC_CPUSEL_CONF: u1,
-                ///  CPU clk sel option
-                RTC_CPUPERIOD_SEL: u2,
-            }),
-            ///  rtc configure register
-            CLK_CONF: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  efuse_clk_force_gating
-                EFUSE_CLK_FORCE_GATING: u1,
-                ///  efuse_clk_force_nogating
-                EFUSE_CLK_FORCE_NOGATING: u1,
-                ///  used to sync reg_ck8m_div_sel bus. Clear vld before set reg_ck8m_div_sel
-                CK8M_DIV_SEL_VLD: u1,
-                ///  CK8M_D256_OUT divider. 00: div128
-                CK8M_DIV: u2,
-                ///  disable CK8M and CK8M_D256_OUT
-                ENB_CK8M: u1,
-                ///  1: CK8M_D256_OUT is actually CK8M
-                ENB_CK8M_DIV: u1,
-                ///  enable CK_XTAL_32K for digital core (no relationship with RTC core)
-                DIG_XTAL32K_EN: u1,
-                ///  enable CK8M_D256_OUT for digital core (no relationship with RTC core)
-                DIG_CLK8M_D256_EN: u1,
-                ///  enable CK8M for digital core (no relationship with RTC core)
-                DIG_CLK8M_EN: u1,
-                reserved12: u1,
-                ///  divider = reg_ck8m_div_sel + 1
-                CK8M_DIV_SEL: u3,
-                ///  XTAL force no gating during sleep
-                XTAL_FORCE_NOGATING: u1,
-                ///  CK8M force no gating during sleep
-                CK8M_FORCE_NOGATING: u1,
-                ///  CK8M_DFREQ
-                CK8M_DFREQ: u8,
-                ///  CK8M force power down
-                CK8M_FORCE_PD: u1,
-                ///  CK8M force power up
-                CK8M_FORCE_PU: u1,
-                ///  force enable xtal clk gating
-                XTAL_GLOBAL_FORCE_GATING: u1,
-                ///  force bypass xtal clk gating
-                XTAL_GLOBAL_FORCE_NOGATING: u1,
-                ///  fast_clk_rtc sel. 0: XTAL div 4
-                FAST_CLK_RTC_SEL: u1,
-                ///  slelect rtc slow clk
-                ANA_CLK_RTC_SEL: u2,
-            }),
-            ///  rtc configure register
-            SLOW_CLK_CONF: mmio.Mmio(packed struct(u32) {
-                reserved22: u22,
-                ///  used to sync div bus. clear vld before set reg_rtc_ana_clk_div
-                RTC_ANA_CLK_DIV_VLD: u1,
-                ///  the clk divider num of RTC_CLK
-                RTC_ANA_CLK_DIV: u8,
-                ///  flag rtc_slow_clk_next_edge
-                RTC_SLOW_CLK_NEXT_EDGE: u1,
-            }),
-            ///  rtc configure register
-            SDIO_CONF: mmio.Mmio(packed struct(u32) {
-                ///  timer count to apply reg_sdio_dcap after sdio power on
-                SDIO_TIMER_TARGET: u8,
-                reserved9: u1,
-                ///  Tieh = 1 mode drive ability. Initially set to 0 to limit charge current
-                SDIO_DTHDRV: u2,
-                ///  ability to prevent LDO from overshoot
-                SDIO_DCAP: u2,
-                ///  add resistor from ldo output to ground. 0: no res
-                SDIO_INITI: u2,
-                ///  0 to set init[1:0]=0
-                SDIO_EN_INITI: u1,
-                ///  tune current limit threshold when tieh = 0. About 800mA/(8+d)
-                SDIO_DCURLIM: u3,
-                ///  select current limit mode
-                SDIO_MODECURLIM: u1,
-                ///  enable current limit
-                SDIO_ENCURLIM: u1,
-                ///  power down SDIO_REG in sleep. Only active when reg_sdio_force = 0
-                SDIO_REG_PD_EN: u1,
-                ///  1: use SW option to control SDIO_REG
-                SDIO_FORCE: u1,
-                ///  SW option for SDIO_TIEH. Only active when reg_sdio_force = 1
-                SDIO_TIEH: u1,
-                ///  read only register for REG1P8_READY
-                _1P8_READY: u1,
-                ///  SW option for DREFL_SDIO. Only active when reg_sdio_force = 1
-                DREFL_SDIO: u2,
-                ///  SW option for DREFM_SDIO. Only active when reg_sdio_force = 1
-                DREFM_SDIO: u2,
-                ///  SW option for DREFH_SDIO. Only active when reg_sdio_force = 1
-                DREFH_SDIO: u2,
-                XPD_SDIO: u1,
-            }),
-            ///  rtc configure register
-            BIAS_CONF: mmio.Mmio(packed struct(u32) {
-                DG_VDD_DRV_B_SLP: u8,
-                DG_VDD_DRV_B_SLP_EN: u1,
-                reserved10: u1,
-                ///  bias buf when rtc in normal work state
-                BIAS_BUF_IDLE: u1,
-                ///  bias buf when rtc in wakeup state
-                BIAS_BUF_WAKE: u1,
-                ///  bias buf when rtc in sleep state
-                BIAS_BUF_DEEP_SLP: u1,
-                ///  bias buf when rtc in monitor state
-                BIAS_BUF_MONITOR: u1,
-                ///  xpd cur when rtc in sleep_state
-                PD_CUR_DEEP_SLP: u1,
-                ///  xpd cur when rtc in monitor state
-                PD_CUR_MONITOR: u1,
-                ///  bias_sleep when rtc in sleep_state
-                BIAS_SLEEP_DEEP_SLP: u1,
-                ///  bias_sleep when rtc in monitor state
-                BIAS_SLEEP_MONITOR: u1,
-                ///  DBG_ATTEN when rtc in sleep state
-                DBG_ATTEN_DEEP_SLP: u4,
-                ///  DBG_ATTEN when rtc in monitor state
-                DBG_ATTEN_MONITOR: u4,
-                padding: u6,
-            }),
-            ///  rtc configure register
-            RTC_CNTL: mmio.Mmio(packed struct(u32) {
-                reserved7: u7,
-                ///  software enable digital regulator cali
-                DIG_REG_CAL_EN: u1,
-                reserved14: u6,
-                ///  SCK_DCAP
-                SCK_DCAP: u8,
-                reserved28: u6,
-                ///  RTC_DBOOST force power down
-                DBOOST_FORCE_PD: u1,
-                ///  RTC_DBOOST force power up
-                DBOOST_FORCE_PU: u1,
-                ///  RTC_REG force power down (for RTC_REG power down means decrease the voltage to 0.8v or lower )
-                REGULATOR_FORCE_PD: u1,
-                ///  RTC_REG force power up
-                REGULATOR_FORCE_PU: u1,
-            }),
-            ///  rtc configure register
-            PWC: mmio.Mmio(packed struct(u32) {
-                reserved21: u21,
-                ///  rtc pad force hold
-                RTC_PAD_FORCE_HOLD: u1,
-                padding: u10,
-            }),
-            ///  rtc configure register
-            DIG_PWC: mmio.Mmio(packed struct(u32) {
-                ///  vdd_spi drv's software value
-                VDD_SPI_PWR_DRV: u2,
-                ///  vdd_spi drv use software value
-                VDD_SPI_PWR_FORCE: u1,
-                ///  memories in digital core force PD in sleep
-                LSLP_MEM_FORCE_PD: u1,
-                ///  memories in digital core force PU in sleep
-                LSLP_MEM_FORCE_PU: u1,
-                reserved11: u6,
-                ///  bt force power down
-                BT_FORCE_PD: u1,
-                ///  bt force power up
-                BT_FORCE_PU: u1,
-                ///  digital peri force power down
-                DG_PERI_FORCE_PD: u1,
-                ///  digital peri force power up
-                DG_PERI_FORCE_PU: u1,
-                ///  fastmemory retention mode in sleep
-                RTC_FASTMEM_FORCE_LPD: u1,
-                ///  fastmemory donlt entry retention mode in sleep
-                RTC_FASTMEM_FORCE_LPU: u1,
-                ///  wifi force power down
-                WIFI_FORCE_PD: u1,
-                ///  wifi force power up
-                WIFI_FORCE_PU: u1,
-                ///  digital core force power down
-                DG_WRAP_FORCE_PD: u1,
-                ///  digital core force power up
-                DG_WRAP_FORCE_PU: u1,
-                ///  cpu core force power down
-                CPU_TOP_FORCE_PD: u1,
-                ///  cpu force power up
-                CPU_TOP_FORCE_PU: u1,
-                reserved27: u4,
-                ///  enable power down bt in sleep
-                BT_PD_EN: u1,
-                ///  enable power down digital peri in sleep
-                DG_PERI_PD_EN: u1,
-                ///  enable power down cpu in sleep
-                CPU_TOP_PD_EN: u1,
-                ///  enable power down wifi in sleep
-                WIFI_PD_EN: u1,
-                ///  enable power down digital wrap in sleep
-                DG_WRAP_PD_EN: u1,
-            }),
-            ///  rtc configure register
-            DIG_ISO: mmio.Mmio(packed struct(u32) {
-                reserved7: u7,
-                ///  DIG_ISO force off
-                FORCE_OFF: u1,
-                ///  DIG_ISO force on
-                FORCE_ON: u1,
-                ///  read only register to indicate digital pad auto-hold status
-                DG_PAD_AUTOHOLD: u1,
-                ///  wtite only register to clear digital pad auto-hold
-                CLR_DG_PAD_AUTOHOLD: u1,
-                ///  digital pad enable auto-hold
-                DG_PAD_AUTOHOLD_EN: u1,
-                ///  digital pad force no ISO
-                DG_PAD_FORCE_NOISO: u1,
-                ///  digital pad force ISO
-                DG_PAD_FORCE_ISO: u1,
-                ///  digital pad force un-hold
-                DG_PAD_FORCE_UNHOLD: u1,
-                ///  digital pad force hold
-                DG_PAD_FORCE_HOLD: u1,
-                reserved22: u6,
-                ///  bt force ISO
-                BT_FORCE_ISO: u1,
-                ///  bt force no ISO
-                BT_FORCE_NOISO: u1,
-                ///  Digital peri force ISO
-                DG_PERI_FORCE_ISO: u1,
-                ///  digital peri force no ISO
-                DG_PERI_FORCE_NOISO: u1,
-                ///  cpu force ISO
-                CPU_TOP_FORCE_ISO: u1,
-                ///  cpu force no ISO
-                CPU_TOP_FORCE_NOISO: u1,
-                ///  wifi force ISO
-                WIFI_FORCE_ISO: u1,
-                ///  wifi force no ISO
-                WIFI_FORCE_NOISO: u1,
-                ///  digital core force ISO
-                DG_WRAP_FORCE_ISO: u1,
-                ///  digital core force no ISO
-                DG_WRAP_FORCE_NOISO: u1,
-            }),
-            ///  rtc configure register
-            WDTCONFIG0: mmio.Mmio(packed struct(u32) {
-                ///  chip reset siginal pulse width
-                WDT_CHIP_RESET_WIDTH: u8,
-                ///  wdt reset whole chip enable
-                WDT_CHIP_RESET_EN: u1,
-                ///  pause WDT in sleep
-                WDT_PAUSE_IN_SLP: u1,
-                ///  enable WDT reset APP CPU
-                WDT_APPCPU_RESET_EN: u1,
-                ///  enable WDT reset PRO CPU
-                WDT_PROCPU_RESET_EN: u1,
-                ///  enable WDT in flash boot
-                WDT_FLASHBOOT_MOD_EN: u1,
-                ///  system reset counter length
-                WDT_SYS_RESET_LENGTH: u3,
-                ///  CPU reset counter length
-                WDT_CPU_RESET_LENGTH: u3,
-                ///  1: interrupt stage en
-                WDT_STG3: u3,
-                ///  1: interrupt stage en
-                WDT_STG2: u3,
-                ///  1: interrupt stage en
-                WDT_STG1: u3,
-                ///  1: interrupt stage en
-                WDT_STG0: u3,
-                ///  enable rtc wdt
-                WDT_EN: u1,
-            }),
-            ///  rtc configure register
-            WDTCONFIG1: mmio.Mmio(packed struct(u32) {
-                ///  the hold time of stage0
-                WDT_STG0_HOLD: u32,
-            }),
-            ///  rtc configure register
-            WDTCONFIG2: mmio.Mmio(packed struct(u32) {
-                ///  the hold time of stage1
-                WDT_STG1_HOLD: u32,
-            }),
-            ///  rtc configure register
-            WDTCONFIG3: mmio.Mmio(packed struct(u32) {
-                ///  the hold time of stage2
-                WDT_STG2_HOLD: u32,
-            }),
-            ///  rtc configure register
-            WDTCONFIG4: mmio.Mmio(packed struct(u32) {
-                ///  the hold time of stage3
-                WDT_STG3_HOLD: u32,
-            }),
-            ///  rtc configure register
-            WDTFEED: mmio.Mmio(packed struct(u32) {
-                reserved31: u31,
-                ///  sw feed rtc wdt
-                RTC_WDT_FEED: u1,
-            }),
-            ///  rtc configure register
-            WDTWPROTECT: mmio.Mmio(packed struct(u32) {
-                ///  the key of rtc wdt
-                WDT_WKEY: u32,
-            }),
-            ///  rtc configure register
-            SWD_CONF: mmio.Mmio(packed struct(u32) {
-                ///  swd reset flag
-                SWD_RESET_FLAG: u1,
-                ///  swd interrupt for feeding
-                SWD_FEED_INT: u1,
-                reserved17: u15,
-                ///  Bypass swd rst
-                SWD_BYPASS_RST: u1,
-                ///  adjust signal width send to swd
-                SWD_SIGNAL_WIDTH: u10,
-                ///  reset swd reset flag
-                SWD_RST_FLAG_CLR: u1,
-                ///  Sw feed swd
-                SWD_FEED: u1,
-                ///  disabel SWD
-                SWD_DISABLE: u1,
-                ///  automatically feed swd when int comes
-                SWD_AUTO_FEED_EN: u1,
-            }),
-            ///  rtc configure register
-            SWD_WPROTECT: mmio.Mmio(packed struct(u32) {
-                ///  the key of super wdt
-                SWD_WKEY: u32,
-            }),
-            ///  rtc configure register
-            SW_CPU_STALL: mmio.Mmio(packed struct(u32) {
-                reserved20: u20,
-                ///  {reg_sw_stall_appcpu_c1[5:0]
-                SW_STALL_APPCPU_C1: u6,
-                ///  stall cpu by software
-                SW_STALL_PROCPU_C1: u6,
-            }),
-            ///  rtc configure register
-            STORE4: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH4: u32,
-            }),
-            ///  rtc configure register
-            STORE5: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH5: u32,
-            }),
-            ///  rtc configure register
-            STORE6: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH6: u32,
-            }),
-            ///  rtc configure register
-            STORE7: mmio.Mmio(packed struct(u32) {
-                ///  reserved register
-                RTC_SCRATCH7: u32,
-            }),
-            ///  rtc configure register
-            LOW_POWER_ST: mmio.Mmio(packed struct(u32) {
-                ///  rom0 power down
-                XPD_ROM0: u1,
-                reserved2: u1,
-                ///  External DCDC power down
-                XPD_DIG_DCDC: u1,
-                ///  rtc peripheral iso
-                RTC_PERI_ISO: u1,
-                ///  rtc peripheral power down
-                XPD_RTC_PERI: u1,
-                ///  wifi iso
-                WIFI_ISO: u1,
-                ///  wifi wrap power down
-                XPD_WIFI: u1,
-                ///  digital wrap iso
-                DIG_ISO: u1,
-                ///  digital wrap power down
-                XPD_DIG: u1,
-                ///  touch should start to work
-                RTC_TOUCH_STATE_START: u1,
-                ///  touch is about to working. Switch rtc main state
-                RTC_TOUCH_STATE_SWITCH: u1,
-                ///  touch is in sleep state
-                RTC_TOUCH_STATE_SLP: u1,
-                ///  touch is done
-                RTC_TOUCH_STATE_DONE: u1,
-                ///  ulp/cocpu should start to work
-                RTC_COCPU_STATE_START: u1,
-                ///  ulp/cocpu is about to working. Switch rtc main state
-                RTC_COCPU_STATE_SWITCH: u1,
-                ///  ulp/cocpu is in sleep state
-                RTC_COCPU_STATE_SLP: u1,
-                ///  ulp/cocpu is done
-                RTC_COCPU_STATE_DONE: u1,
-                ///  no use any more
-                RTC_MAIN_STATE_XTAL_ISO: u1,
-                ///  rtc main state machine is in states that pll should be running
-                RTC_MAIN_STATE_PLL_ON: u1,
-                ///  rtc is ready to receive wake up trigger from wake up source
-                RTC_RDY_FOR_WAKEUP: u1,
-                ///  rtc main state machine has been waited for some cycles
-                RTC_MAIN_STATE_WAIT_END: u1,
-                ///  rtc main state machine is in the states of wakeup process
-                RTC_IN_WAKEUP_STATE: u1,
-                ///  rtc main state machine is in the states of low power
-                RTC_IN_LOW_POWER_STATE: u1,
-                ///  rtc main state machine is in wait 8m state
-                RTC_MAIN_STATE_IN_WAIT_8M: u1,
-                ///  rtc main state machine is in wait pll state
-                RTC_MAIN_STATE_IN_WAIT_PLL: u1,
-                ///  rtc main state machine is in wait xtal state
-                RTC_MAIN_STATE_IN_WAIT_XTL: u1,
-                ///  rtc main state machine is in sleep state
-                RTC_MAIN_STATE_IN_SLP: u1,
-                ///  rtc main state machine is in idle state
-                RTC_MAIN_STATE_IN_IDLE: u1,
-                ///  rtc main state machine status
-                RTC_MAIN_STATE: u4,
-            }),
-            ///  rtc configure register
-            DIAG0: mmio.Mmio(packed struct(u32) {
-                RTC_LOW_POWER_DIAG1: u32,
-            }),
-            ///  rtc configure register
-            PAD_HOLD: mmio.Mmio(packed struct(u32) {
-                ///  the hold configure of rtc gpio0
-                RTC_GPIO_PIN0_HOLD: u1,
-                ///  the hold configure of rtc gpio1
-                RTC_GPIO_PIN1_HOLD: u1,
-                ///  the hold configure of rtc gpio2
-                RTC_GPIO_PIN2_HOLD: u1,
-                ///  the hold configure of rtc gpio3
-                RTC_GPIO_PIN3_HOLD: u1,
-                ///  the hold configure of rtc gpio4
-                RTC_GPIO_PIN4_HOLD: u1,
-                ///  the hold configure of rtc gpio5
-                RTC_GPIO_PIN5_HOLD: u1,
-                padding: u26,
-            }),
-            ///  rtc configure register
-            DIG_PAD_HOLD: mmio.Mmio(packed struct(u32) {
-                ///  the configure of digital pad
-                DIG_PAD_HOLD: u32,
-            }),
-            ///  rtc configure register
-            BROWN_OUT: mmio.Mmio(packed struct(u32) {
-                reserved4: u4,
-                ///  brown out interrupt wait cycles
-                INT_WAIT: u10,
-                ///  enable close flash when brown out happens
-                CLOSE_FLASH_ENA: u1,
-                ///  enable power down RF when brown out happens
-                PD_RF_ENA: u1,
-                ///  brown out reset wait cycles
-                RST_WAIT: u10,
-                ///  enable brown out reset
-                RST_ENA: u1,
-                ///  1: 4-pos reset
-                RST_SEL: u1,
-                ///  brown_out origin reset enable
-                ANA_RST_EN: u1,
-                ///  clear brown out counter
-                CNT_CLR: u1,
-                ///  enable brown out
-                ENA: u1,
-                ///  the flag of brown det from analog
-                DET: u1,
-            }),
-            ///  rtc configure register
-            TIME_LOW1: mmio.Mmio(packed struct(u32) {
-                ///  RTC timer low 32 bits
-                RTC_TIMER_VALUE1_LOW: u32,
-            }),
-            ///  rtc configure register
-            TIME_HIGH1: mmio.Mmio(packed struct(u32) {
-                ///  RTC timer high 16 bits
-                RTC_TIMER_VALUE1_HIGH: u16,
-                padding: u16,
-            }),
-            ///  rtc configure register
-            XTAL32K_CLK_FACTOR: mmio.Mmio(packed struct(u32) {
-                ///  xtal 32k watch dog backup clock factor
-                XTAL32K_CLK_FACTOR: u32,
-            }),
-            ///  rtc configure register
-            XTAL32K_CONF: mmio.Mmio(packed struct(u32) {
-                ///  cycles to wait to return noral xtal 32k
-                XTAL32K_RETURN_WAIT: u4,
-                ///  cycles to wait to repower on xtal 32k
-                XTAL32K_RESTART_WAIT: u16,
-                ///  If no clock detected for this amount of time
-                XTAL32K_WDT_TIMEOUT: u8,
-                ///  if restarted xtal32k period is smaller than this
-                XTAL32K_STABLE_THRES: u4,
-            }),
-            ///  rtc configure register
-            USB_CONF: mmio.Mmio(packed struct(u32) {
-                reserved18: u18,
-                ///  disable io_mux reset
-                IO_MUX_RESET_DISABLE: u1,
-                padding: u13,
-            }),
-            ///  RTC_CNTL_RTC_SLP_REJECT_CAUSE_REG
-            SLP_REJECT_CAUSE: mmio.Mmio(packed struct(u32) {
-                ///  sleep reject cause
-                REJECT_CAUSE: u18,
-                padding: u14,
-            }),
-            ///  rtc configure register
-            OPTION1: mmio.Mmio(packed struct(u32) {
-                ///  force chip entry download mode
-                FORCE_DOWNLOAD_BOOT: u1,
-                padding: u31,
-            }),
-            ///  RTC_CNTL_RTC_SLP_WAKEUP_CAUSE_REG
-            SLP_WAKEUP_CAUSE: mmio.Mmio(packed struct(u32) {
-                ///  sleep wakeup cause
-                WAKEUP_CAUSE: u17,
-                padding: u15,
-            }),
-            ///  rtc configure register
-            ULP_CP_TIMER_1: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  sleep cycles for ULP-coprocessor timer
-                ULP_CP_TIMER_SLP_CYCLE: u24,
-            }),
-            ///  rtc configure register
-            INT_ENA_RTC_W1TS: mmio.Mmio(packed struct(u32) {
-                ///  enable sleep wakeup interrupt
-                SLP_WAKEUP_INT_ENA_W1TS: u1,
-                ///  enable sleep reject interrupt
-                SLP_REJECT_INT_ENA_W1TS: u1,
-                reserved3: u1,
-                ///  enable RTC WDT interrupt
-                RTC_WDT_INT_ENA_W1TS: u1,
-                reserved9: u5,
-                ///  enable brown out interrupt
-                RTC_BROWN_OUT_INT_ENA_W1TS: u1,
-                ///  enable RTC main timer interrupt
-                RTC_MAIN_TIMER_INT_ENA_W1TS: u1,
-                reserved15: u4,
-                ///  enable super watch dog interrupt
-                RTC_SWD_INT_ENA_W1TS: u1,
-                ///  enable xtal32k_dead interrupt
-                RTC_XTAL32K_DEAD_INT_ENA_W1TS: u1,
-                reserved19: u2,
-                ///  enbale gitch det interrupt
-                RTC_GLITCH_DET_INT_ENA_W1TS: u1,
-                ///  enbale bbpll cal interrupt
-                RTC_BBPLL_CAL_INT_ENA_W1TS: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            INT_ENA_RTC_W1TC: mmio.Mmio(packed struct(u32) {
-                ///  clear sleep wakeup interrupt enable
-                SLP_WAKEUP_INT_ENA_W1TC: u1,
-                ///  clear sleep reject interrupt enable
-                SLP_REJECT_INT_ENA_W1TC: u1,
-                reserved3: u1,
-                ///  clear RTC WDT interrupt enable
-                RTC_WDT_INT_ENA_W1TC: u1,
-                reserved9: u5,
-                ///  clear brown out interrupt enable
-                RTC_BROWN_OUT_INT_ENA_W1TC: u1,
-                ///  Clear RTC main timer interrupt enable
-                RTC_MAIN_TIMER_INT_ENA_W1TC: u1,
-                reserved15: u4,
-                ///  clear super watch dog interrupt enable
-                RTC_SWD_INT_ENA_W1TC: u1,
-                ///  clear xtal32k_dead interrupt enable
-                RTC_XTAL32K_DEAD_INT_ENA_W1TC: u1,
-                reserved19: u2,
-                ///  clear gitch det interrupt enable
-                RTC_GLITCH_DET_INT_ENA_W1TC: u1,
-                ///  clear bbpll cal interrupt enable
-                RTC_BBPLL_CAL_INT_ENA_W1TC: u1,
-                padding: u11,
-            }),
-            ///  rtc configure register
-            RETENTION_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved18: u18,
-                ///  Retention clk sel
-                RETENTION_CLK_SEL: u1,
-                ///  Retention done wait time
-                RETENTION_DONE_WAIT: u3,
-                ///  Retention clkoff wait time
-                RETENTION_CLKOFF_WAIT: u4,
-                ///  enable cpu retention when light sleep
-                RETENTION_EN: u1,
-                ///  wait cycles for rention operation
-                RETENTION_WAIT: u5,
-            }),
-            ///  rtc configure register
-            FIB_SEL: mmio.Mmio(packed struct(u32) {
-                ///  select use analog fib signal
-                RTC_FIB_SEL: u3,
-                padding: u29,
-            }),
-            ///  rtc configure register
-            GPIO_WAKEUP: mmio.Mmio(packed struct(u32) {
-                ///  rtc gpio wakeup flag
-                RTC_GPIO_WAKEUP_STATUS: u6,
-                ///  clear rtc gpio wakeup flag
-                RTC_GPIO_WAKEUP_STATUS_CLR: u1,
-                ///  enable rtc io clk gate
-                RTC_GPIO_PIN_CLK_GATE: u1,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN5_INT_TYPE: u3,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN4_INT_TYPE: u3,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN3_INT_TYPE: u3,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN2_INT_TYPE: u3,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN1_INT_TYPE: u3,
-                ///  configure gpio wakeup type
-                RTC_GPIO_PIN0_INT_TYPE: u3,
-                ///  enable wakeup from rtc gpio5
-                RTC_GPIO_PIN5_WAKEUP_ENABLE: u1,
-                ///  enable wakeup from rtc gpio4
-                RTC_GPIO_PIN4_WAKEUP_ENABLE: u1,
-                ///  enable wakeup from rtc gpio3
-                RTC_GPIO_PIN3_WAKEUP_ENABLE: u1,
-                ///  enable wakeup from rtc gpio2
-                RTC_GPIO_PIN2_WAKEUP_ENABLE: u1,
-                ///  enable wakeup from rtc gpio1
-                RTC_GPIO_PIN1_WAKEUP_ENABLE: u1,
-                ///  enable wakeup from rtc gpio0
-                RTC_GPIO_PIN0_WAKEUP_ENABLE: u1,
-            }),
-            ///  rtc configure register
-            DBG_SEL: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  use for debug
-                RTC_DEBUG_12M_NO_GATING: u1,
-                ///  use for debug
-                RTC_DEBUG_BIT_SEL: u5,
-                ///  use for debug
-                RTC_DEBUG_SEL0: u5,
-                ///  use for debug
-                RTC_DEBUG_SEL1: u5,
-                ///  use for debug
-                RTC_DEBUG_SEL2: u5,
-                ///  use for debug
-                RTC_DEBUG_SEL3: u5,
-                ///  use for debug
-                RTC_DEBUG_SEL4: u5,
-            }),
-            ///  rtc configure register
-            DBG_MAP: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  use for debug
-                RTC_GPIO_PIN5_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN4_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN3_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN2_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN1_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN0_MUX_SEL: u1,
-                ///  use for debug
-                RTC_GPIO_PIN5_FUN_SEL: u4,
-                ///  use for debug
-                RTC_GPIO_PIN4_FUN_SEL: u4,
-                ///  use for debug
-                RTC_GPIO_PIN3_FUN_SEL: u4,
-                ///  use for debug
-                RTC_GPIO_PIN2_FUN_SEL: u4,
-                ///  use for debug
-                RTC_GPIO_PIN1_FUN_SEL: u4,
-                ///  use for debug
-                RTC_GPIO_PIN0_FUN_SEL: u4,
-            }),
-            ///  rtc configure register
-            SENSOR_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved27: u27,
-                ///  reg_sar2_pwdet_cct
-                SAR2_PWDET_CCT: u3,
-                ///  force power up SAR
-                FORCE_XPD_SAR: u2,
-            }),
-            ///  rtc configure register
-            DBG_SAR_SEL: mmio.Mmio(packed struct(u32) {
-                reserved27: u27,
-                ///  use for debug
-                SAR_DEBUG_SEL: u5,
-            }),
-            ///  rtc configure register
-            PG_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved26: u26,
-                ///  power glitch desense
-                POWER_GLITCH_DSENSE: u2,
-                ///  force disable power glitch
-                POWER_GLITCH_FORCE_PD: u1,
-                ///  force enable power glitch
-                POWER_GLITCH_FORCE_PU: u1,
-                ///  use efuse value control power glitch enable
-                POWER_GLITCH_EFUSE_SEL: u1,
-                ///  enable power glitch
-                POWER_GLITCH_EN: u1,
-            }),
-            reserved508: [212]u8,
-            ///  rtc configure register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  verision
-                RTC_CNTL_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  Sensitive
-        pub const SENSITIVE = extern struct {
-            ///  SENSITIVE_ROM_TABLE_LOCK_REG
-            ROM_TABLE_LOCK: mmio.Mmio(packed struct(u32) {
-                ///  rom_table_lock
-                ROM_TABLE_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_ROM_TABLE_REG
-            ROM_TABLE: mmio.Mmio(packed struct(u32) {
-                ///  rom_table
-                ROM_TABLE: u32,
-            }),
-            ///  SENSITIVE_PRIVILEGE_MODE_SEL_LOCK_REG
-            PRIVILEGE_MODE_SEL_LOCK: mmio.Mmio(packed struct(u32) {
-                ///  privilege_mode_sel_lock
-                PRIVILEGE_MODE_SEL_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_PRIVILEGE_MODE_SEL_REG
-            PRIVILEGE_MODE_SEL: mmio.Mmio(packed struct(u32) {
-                ///  privilege_mode_sel
-                PRIVILEGE_MODE_SEL: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_APB_PERIPHERAL_ACCESS_0_REG
-            APB_PERIPHERAL_ACCESS_0: mmio.Mmio(packed struct(u32) {
-                ///  apb_peripheral_access_lock
-                APB_PERIPHERAL_ACCESS_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_APB_PERIPHERAL_ACCESS_1_REG
-            APB_PERIPHERAL_ACCESS_1: mmio.Mmio(packed struct(u32) {
-                ///  apb_peripheral_access_split_burst
-                APB_PERIPHERAL_ACCESS_SPLIT_BURST: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_INTERNAL_SRAM_USAGE_0_REG
-            INTERNAL_SRAM_USAGE_0: mmio.Mmio(packed struct(u32) {
-                ///  internal_sram_usage_lock
-                INTERNAL_SRAM_USAGE_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_INTERNAL_SRAM_USAGE_1_REG
-            INTERNAL_SRAM_USAGE_1: mmio.Mmio(packed struct(u32) {
-                ///  internal_sram_usage_cpu_cache
-                INTERNAL_SRAM_USAGE_CPU_CACHE: u1,
-                ///  internal_sram_usage_cpu_sram
-                INTERNAL_SRAM_USAGE_CPU_SRAM: u3,
-                padding: u28,
-            }),
-            ///  SENSITIVE_INTERNAL_SRAM_USAGE_3_REG
-            INTERNAL_SRAM_USAGE_3: mmio.Mmio(packed struct(u32) {
-                ///  internal_sram_usage_mac_dump_sram
-                INTERNAL_SRAM_USAGE_MAC_DUMP_SRAM: u3,
-                ///  internal_sram_alloc_mac_dump
-                INTERNAL_SRAM_ALLOC_MAC_DUMP: u1,
-                padding: u28,
-            }),
-            ///  SENSITIVE_INTERNAL_SRAM_USAGE_4_REG
-            INTERNAL_SRAM_USAGE_4: mmio.Mmio(packed struct(u32) {
-                ///  internal_sram_usage_log_sram
-                INTERNAL_SRAM_USAGE_LOG_SRAM: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CACHE_TAG_ACCESS_0_REG
-            CACHE_TAG_ACCESS_0: mmio.Mmio(packed struct(u32) {
-                ///  cache_tag_access_lock
-                CACHE_TAG_ACCESS_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CACHE_TAG_ACCESS_1_REG
-            CACHE_TAG_ACCESS_1: mmio.Mmio(packed struct(u32) {
-                ///  pro_i_tag_rd_acs
-                PRO_I_TAG_RD_ACS: u1,
-                ///  pro_i_tag_wr_acs
-                PRO_I_TAG_WR_ACS: u1,
-                ///  pro_d_tag_rd_acs
-                PRO_D_TAG_RD_ACS: u1,
-                ///  pro_d_tag_wr_acs
-                PRO_D_TAG_WR_ACS: u1,
-                padding: u28,
-            }),
-            ///  SENSITIVE_CACHE_MMU_ACCESS_0_REG
-            CACHE_MMU_ACCESS_0: mmio.Mmio(packed struct(u32) {
-                ///  cache_mmu_access_lock
-                CACHE_MMU_ACCESS_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CACHE_MMU_ACCESS_1_REG
-            CACHE_MMU_ACCESS_1: mmio.Mmio(packed struct(u32) {
-                ///  pro_mmu_rd_acs
-                PRO_MMU_RD_ACS: u1,
-                ///  pro_mmu_wr_acs
-                PRO_MMU_WR_ACS: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_spi2_pms_constrain_lock
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_SPI2_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_SPI2_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_spi2_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_SPI2_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_uchi0_pms_constrain_lock
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_UCHI0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_uchi0_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_UCHI0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_i2s0_pms_constrain_lock
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_I2S0_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_I2S0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_i2s0_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_I2S0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_mac_pms_constrain_lock
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_MAC_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_MAC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_mac_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_MAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_backup_pms_constrain_lock
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_BACKUP_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_backup_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_BACKUP_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_LC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_lc_pms_constrain_lock
-                DMA_APBPERI_LC_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_LC_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_LC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_lc_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_LC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_AES_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_aes_pms_constrain_lock
-                DMA_APBPERI_AES_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_AES_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_AES_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_aes_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_AES_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_sha_pms_constrain_lock
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_SHA_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_SHA_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_sha_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_SHA_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0_REG
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_adc_dac_pms_constrain_lock
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1_REG
-            DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_0
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_1
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_2
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_0_pms_3
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_0
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_1
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_2
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  dma_apbperi_adc_dac_pms_constrain_sram_world_1_pms_3
-                DMA_APBPERI_ADC_DAC_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                padding: u12,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_0_REG
-            DMA_APBPERI_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_pms_monitor_lock
-                DMA_APBPERI_PMS_MONITOR_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_1_REG
-            DMA_APBPERI_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_pms_monitor_violate_clr
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_CLR: u1,
-                ///  dma_apbperi_pms_monitor_violate_en
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_2_REG
-            DMA_APBPERI_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_pms_monitor_violate_intr
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_INTR: u1,
-                ///  dma_apbperi_pms_monitor_violate_status_world
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-                ///  dma_apbperi_pms_monitor_violate_status_addr
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-                padding: u5,
-            }),
-            ///  SENSITIVE_DMA_APBPERI_PMS_MONITOR_3_REG
-            DMA_APBPERI_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
-                ///  dma_apbperi_pms_monitor_violate_status_wr
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-                ///  dma_apbperi_pms_monitor_violate_status_byteen
-                DMA_APBPERI_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
-                padding: u27,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_dram0_dma_split_line_constrain_lock
-                CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_dram0_dma_sram_category_0
-                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_0: u2,
-                ///  core_x_iram0_dram0_dma_sram_category_1
-                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_1: u2,
-                ///  core_x_iram0_dram0_dma_sram_category_2
-                CORE_X_IRAM0_DRAM0_DMA_SRAM_CATEGORY_2: u2,
-                reserved14: u8,
-                ///  core_x_iram0_dram0_dma_sram_splitaddr
-                CORE_X_IRAM0_DRAM0_DMA_SRAM_SPLITADDR: u8,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_sram_line_0_category_0
-                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_0: u2,
-                ///  core_x_iram0_sram_line_0_category_1
-                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_1: u2,
-                ///  core_x_iram0_sram_line_0_category_2
-                CORE_X_IRAM0_SRAM_LINE_0_CATEGORY_2: u2,
-                reserved14: u8,
-                ///  core_x_iram0_sram_line_0_splitaddr
-                CORE_X_IRAM0_SRAM_LINE_0_SPLITADDR: u8,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_sram_line_1_category_0
-                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_0: u2,
-                ///  core_x_iram0_sram_line_1_category_1
-                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_1: u2,
-                ///  core_x_iram0_sram_line_1_category_2
-                CORE_X_IRAM0_SRAM_LINE_1_CATEGORY_2: u2,
-                reserved14: u8,
-                ///  core_x_iram0_sram_line_1_splitaddr
-                CORE_X_IRAM0_SRAM_LINE_1_SPLITADDR: u8,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
-                ///  core_x_dram0_dma_sram_line_0_category_0
-                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_0: u2,
-                ///  core_x_dram0_dma_sram_line_0_category_1
-                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_1: u2,
-                ///  core_x_dram0_dma_sram_line_0_category_2
-                CORE_X_DRAM0_DMA_SRAM_LINE_0_CATEGORY_2: u2,
-                reserved14: u8,
-                ///  core_x_dram0_dma_sram_line_0_splitaddr
-                CORE_X_DRAM0_DMA_SRAM_LINE_0_SPLITADDR: u8,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5_REG
-            CORE_X_IRAM0_DRAM0_DMA_SPLIT_LINE_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
-                ///  core_x_dram0_dma_sram_line_1_category_0
-                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_0: u2,
-                ///  core_x_dram0_dma_sram_line_1_category_1
-                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_1: u2,
-                ///  core_x_dram0_dma_sram_line_1_category_2
-                CORE_X_DRAM0_DMA_SRAM_LINE_1_CATEGORY_2: u2,
-                reserved14: u8,
-                ///  core_x_dram0_dma_sram_line_1_splitaddr
-                CORE_X_DRAM0_DMA_SRAM_LINE_1_SPLITADDR: u8,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_0_REG
-            CORE_X_IRAM0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_pms_constrain_lock
-                CORE_X_IRAM0_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_1_REG
-            CORE_X_IRAM0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_pms_constrain_sram_world_1_pms_0
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_1_pms_1
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_1_pms_2
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_1_pms_3
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_1_cachedataarray_pms_0
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_CACHEDATAARRAY_PMS_0: u3,
-                reserved18: u3,
-                ///  core_x_iram0_pms_constrain_rom_world_1_pms
-                CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u3,
-                padding: u11,
-            }),
-            ///  SENSITIVE_CORE_X_IRAM0_PMS_CONSTRAIN_2_REG
-            CORE_X_IRAM0_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
-                ///  core_x_iram0_pms_constrain_sram_world_0_pms_0
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_0_pms_1
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_0_pms_2
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_0_pms_3
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u3,
-                ///  core_x_iram0_pms_constrain_sram_world_0_cachedataarray_pms_0
-                CORE_X_IRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_CACHEDATAARRAY_PMS_0: u3,
-                reserved18: u3,
-                ///  core_x_iram0_pms_constrain_rom_world_0_pms
-                CORE_X_IRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u3,
-                padding: u11,
-            }),
-            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_0_REG
-            CORE_0_IRAM0_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  core_0_iram0_pms_monitor_lock
-                CORE_0_IRAM0_PMS_MONITOR_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_1_REG
-            CORE_0_IRAM0_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  core_0_iram0_pms_monitor_violate_clr
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
-                ///  core_0_iram0_pms_monitor_violate_en
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_CORE_0_IRAM0_PMS_MONITOR_2_REG
-            CORE_0_IRAM0_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  core_0_iram0_pms_monitor_violate_intr
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
-                ///  core_0_iram0_pms_monitor_violate_status_wr
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-                ///  core_0_iram0_pms_monitor_violate_status_loadstore
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_LOADSTORE: u1,
-                ///  core_0_iram0_pms_monitor_violate_status_world
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-                ///  core_0_iram0_pms_monitor_violate_status_addr
-                CORE_0_IRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-                padding: u3,
-            }),
-            ///  SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_0_REG
-            CORE_X_DRAM0_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  core_x_dram0_pms_constrain_lock
-                CORE_X_DRAM0_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_X_DRAM0_PMS_CONSTRAIN_1_REG
-            CORE_X_DRAM0_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  core_x_dram0_pms_constrain_sram_world_0_pms_0
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_0: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_0_pms_1
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_1: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_0_pms_2
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_2: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_0_pms_3
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_0_PMS_3: u2,
-                reserved12: u4,
-                ///  core_x_dram0_pms_constrain_sram_world_1_pms_0
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_0: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_1_pms_1
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_1: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_1_pms_2
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_2: u2,
-                ///  core_x_dram0_pms_constrain_sram_world_1_pms_3
-                CORE_X_DRAM0_PMS_CONSTRAIN_SRAM_WORLD_1_PMS_3: u2,
-                reserved24: u4,
-                ///  core_x_dram0_pms_constrain_rom_world_0_pms
-                CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_0_PMS: u2,
-                ///  core_x_dram0_pms_constrain_rom_world_1_pms
-                CORE_X_DRAM0_PMS_CONSTRAIN_ROM_WORLD_1_PMS: u2,
-                padding: u4,
-            }),
-            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_0_REG
-            CORE_0_DRAM0_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  core_0_dram0_pms_monitor_lock
-                CORE_0_DRAM0_PMS_MONITOR_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_1_REG
-            CORE_0_DRAM0_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  core_0_dram0_pms_monitor_violate_clr
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_CLR: u1,
-                ///  core_0_dram0_pms_monitor_violate_en
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_2_REG
-            CORE_0_DRAM0_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  core_0_dram0_pms_monitor_violate_intr
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_INTR: u1,
-                ///  core_0_dram0_pms_monitor_violate_status_lock
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_LOCK: u1,
-                ///  core_0_dram0_pms_monitor_violate_status_world
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WORLD: u2,
-                ///  core_0_dram0_pms_monitor_violate_status_addr
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_ADDR: u24,
-                padding: u4,
-            }),
-            ///  SENSITIVE_CORE_0_DRAM0_PMS_MONITOR_3_REG
-            CORE_0_DRAM0_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
-                ///  core_0_dram0_pms_monitor_violate_status_wr
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_WR: u1,
-                ///  core_0_dram0_pms_monitor_violate_status_byteen
-                CORE_0_DRAM0_PMS_MONITOR_VIOLATE_STATUS_BYTEEN: u4,
-                padding: u27,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_0_REG
-            CORE_0_PIF_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_lock
-                CORE_0_PIF_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_1_REG
-            CORE_0_PIF_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_0_uart
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART: u2,
-                ///  core_0_pif_pms_constrain_world_0_g0spi_1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_1: u2,
-                ///  core_0_pif_pms_constrain_world_0_g0spi_0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_G0SPI_0: u2,
-                ///  core_0_pif_pms_constrain_world_0_gpio
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_GPIO: u2,
-                ///  core_0_pif_pms_constrain_world_0_fe2
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE2: u2,
-                ///  core_0_pif_pms_constrain_world_0_fe
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_FE: u2,
-                ///  core_0_pif_pms_constrain_world_0_timer
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMER: u2,
-                ///  core_0_pif_pms_constrain_world_0_rtc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RTC: u2,
-                ///  core_0_pif_pms_constrain_world_0_io_mux
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_IO_MUX: u2,
-                ///  core_0_pif_pms_constrain_world_0_wdg
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WDG: u2,
-                reserved24: u4,
-                ///  core_0_pif_pms_constrain_world_0_misc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_MISC: u2,
-                ///  core_0_pif_pms_constrain_world_0_i2c
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C: u2,
-                reserved30: u2,
-                ///  core_0_pif_pms_constrain_world_0_uart1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UART1: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_2_REG
-            CORE_0_PIF_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_0_bt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT: u2,
-                reserved4: u2,
-                ///  core_0_pif_pms_constrain_world_0_i2c_ext0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2C_EXT0: u2,
-                ///  core_0_pif_pms_constrain_world_0_uhci0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_UHCI0: u2,
-                reserved10: u2,
-                ///  core_0_pif_pms_constrain_world_0_rmt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RMT: u2,
-                reserved16: u4,
-                ///  core_0_pif_pms_constrain_world_0_ledc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_LEDC: u2,
-                reserved22: u4,
-                ///  core_0_pif_pms_constrain_world_0_bb
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BB: u2,
-                reserved26: u2,
-                ///  core_0_pif_pms_constrain_world_0_timergroup
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP: u2,
-                ///  core_0_pif_pms_constrain_world_0_timergroup1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_TIMERGROUP1: u2,
-                ///  core_0_pif_pms_constrain_world_0_systimer
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTIMER: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_3_REG
-            CORE_0_PIF_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_0_spi_2
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SPI_2: u2,
-                reserved4: u2,
-                ///  core_0_pif_pms_constrain_world_0_apb_ctrl
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_CTRL: u2,
-                reserved10: u4,
-                ///  core_0_pif_pms_constrain_world_0_can
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CAN: u2,
-                reserved14: u2,
-                ///  core_0_pif_pms_constrain_world_0_i2s1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_I2S1: u2,
-                reserved22: u6,
-                ///  core_0_pif_pms_constrain_world_0_rwbt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_RWBT: u2,
-                reserved26: u2,
-                ///  core_0_pif_pms_constrain_world_0_wifimac
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WIFIMAC: u2,
-                ///  core_0_pif_pms_constrain_world_0_pwr
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_PWR: u2,
-                padding: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_4_REG
-            CORE_0_PIF_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  core_0_pif_pms_constrain_world_0_usb_wrap
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_WRAP: u2,
-                ///  core_0_pif_pms_constrain_world_0_crypto_peri
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_PERI: u2,
-                ///  core_0_pif_pms_constrain_world_0_crypto_dma
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CRYPTO_DMA: u2,
-                ///  core_0_pif_pms_constrain_world_0_apb_adc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_APB_ADC: u2,
-                reserved12: u2,
-                ///  core_0_pif_pms_constrain_world_0_bt_pwr
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_BT_PWR: u2,
-                ///  core_0_pif_pms_constrain_world_0_usb_device
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_USB_DEVICE: u2,
-                ///  core_0_pif_pms_constrain_world_0_system
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SYSTEM: u2,
-                ///  core_0_pif_pms_constrain_world_0_sensitive
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_SENSITIVE: u2,
-                ///  core_0_pif_pms_constrain_world_0_interrupt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_INTERRUPT: u2,
-                ///  core_0_pif_pms_constrain_world_0_dma_copy
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DMA_COPY: u2,
-                ///  core_0_pif_pms_constrain_world_0_cache_config
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_CACHE_CONFIG: u2,
-                ///  core_0_pif_pms_constrain_world_0_ad
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_AD: u2,
-                ///  core_0_pif_pms_constrain_world_0_dio
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_DIO: u2,
-                ///  core_0_pif_pms_constrain_world_0_world_controller
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_0_WORLD_CONTROLLER: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_5_REG
-            CORE_0_PIF_PMS_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_1_uart
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART: u2,
-                ///  core_0_pif_pms_constrain_world_1_g0spi_1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_1: u2,
-                ///  core_0_pif_pms_constrain_world_1_g0spi_0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_G0SPI_0: u2,
-                ///  core_0_pif_pms_constrain_world_1_gpio
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_GPIO: u2,
-                ///  core_0_pif_pms_constrain_world_1_fe2
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE2: u2,
-                ///  core_0_pif_pms_constrain_world_1_fe
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_FE: u2,
-                ///  core_0_pif_pms_constrain_world_1_timer
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMER: u2,
-                ///  core_0_pif_pms_constrain_world_1_rtc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RTC: u2,
-                ///  core_0_pif_pms_constrain_world_1_io_mux
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_IO_MUX: u2,
-                ///  core_0_pif_pms_constrain_world_1_wdg
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WDG: u2,
-                reserved24: u4,
-                ///  core_0_pif_pms_constrain_world_1_misc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_MISC: u2,
-                ///  core_0_pif_pms_constrain_world_1_i2c
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C: u2,
-                reserved30: u2,
-                ///  core_0_pif_pms_constrain_world_1_uart1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UART1: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_6_REG
-            CORE_0_PIF_PMS_CONSTRAIN_6: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_1_bt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT: u2,
-                reserved4: u2,
-                ///  core_0_pif_pms_constrain_world_1_i2c_ext0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2C_EXT0: u2,
-                ///  core_0_pif_pms_constrain_world_1_uhci0
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_UHCI0: u2,
-                reserved10: u2,
-                ///  core_0_pif_pms_constrain_world_1_rmt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RMT: u2,
-                reserved16: u4,
-                ///  core_0_pif_pms_constrain_world_1_ledc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_LEDC: u2,
-                reserved22: u4,
-                ///  core_0_pif_pms_constrain_world_1_bb
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BB: u2,
-                reserved26: u2,
-                ///  core_0_pif_pms_constrain_world_1_timergroup
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP: u2,
-                ///  core_0_pif_pms_constrain_world_1_timergroup1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_TIMERGROUP1: u2,
-                ///  core_0_pif_pms_constrain_world_1_systimer
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTIMER: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_7_REG
-            CORE_0_PIF_PMS_CONSTRAIN_7: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_world_1_spi_2
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SPI_2: u2,
-                reserved4: u2,
-                ///  core_0_pif_pms_constrain_world_1_apb_ctrl
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_CTRL: u2,
-                reserved10: u4,
-                ///  core_0_pif_pms_constrain_world_1_can
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CAN: u2,
-                reserved14: u2,
-                ///  core_0_pif_pms_constrain_world_1_i2s1
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_I2S1: u2,
-                reserved22: u6,
-                ///  core_0_pif_pms_constrain_world_1_rwbt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_RWBT: u2,
-                reserved26: u2,
-                ///  core_0_pif_pms_constrain_world_1_wifimac
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WIFIMAC: u2,
-                ///  core_0_pif_pms_constrain_world_1_pwr
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_PWR: u2,
-                padding: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_8_REG
-            CORE_0_PIF_PMS_CONSTRAIN_8: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  core_0_pif_pms_constrain_world_1_usb_wrap
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_WRAP: u2,
-                ///  core_0_pif_pms_constrain_world_1_crypto_peri
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_PERI: u2,
-                ///  core_0_pif_pms_constrain_world_1_crypto_dma
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CRYPTO_DMA: u2,
-                ///  core_0_pif_pms_constrain_world_1_apb_adc
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_APB_ADC: u2,
-                reserved12: u2,
-                ///  core_0_pif_pms_constrain_world_1_bt_pwr
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_BT_PWR: u2,
-                ///  core_0_pif_pms_constrain_world_1_usb_device
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_USB_DEVICE: u2,
-                ///  core_0_pif_pms_constrain_world_1_system
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SYSTEM: u2,
-                ///  core_0_pif_pms_constrain_world_1_sensitive
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_SENSITIVE: u2,
-                ///  core_0_pif_pms_constrain_world_1_interrupt
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_INTERRUPT: u2,
-                ///  core_0_pif_pms_constrain_world_1_dma_copy
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DMA_COPY: u2,
-                ///  core_0_pif_pms_constrain_world_1_cache_config
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_CACHE_CONFIG: u2,
-                ///  core_0_pif_pms_constrain_world_1_ad
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_AD: u2,
-                ///  core_0_pif_pms_constrain_world_1_dio
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_DIO: u2,
-                ///  core_0_pif_pms_constrain_world_1_world_controller
-                CORE_0_PIF_PMS_CONSTRAIN_WORLD_1_WORLD_CONTROLLER: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_9_REG
-            CORE_0_PIF_PMS_CONSTRAIN_9: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_rtcfast_spltaddr_world_0
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_0: u11,
-                ///  core_0_pif_pms_constrain_rtcfast_spltaddr_world_1
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_SPLTADDR_WORLD_1: u11,
-                padding: u10,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_CONSTRAIN_10_REG
-            CORE_0_PIF_PMS_CONSTRAIN_10: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_constrain_rtcfast_world_0_l
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_L: u3,
-                ///  core_0_pif_pms_constrain_rtcfast_world_0_h
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_0_H: u3,
-                ///  core_0_pif_pms_constrain_rtcfast_world_1_l
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_L: u3,
-                ///  core_0_pif_pms_constrain_rtcfast_world_1_h
-                CORE_0_PIF_PMS_CONSTRAIN_RTCFAST_WORLD_1_H: u3,
-                padding: u20,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_0_REG
-            REGION_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_lock
-                REGION_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_1_REG
-            REGION_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_world_0_area_0
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_0: u2,
-                ///  region_pms_constrain_world_0_area_1
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_1: u2,
-                ///  region_pms_constrain_world_0_area_2
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_2: u2,
-                ///  region_pms_constrain_world_0_area_3
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_3: u2,
-                ///  region_pms_constrain_world_0_area_4
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_4: u2,
-                ///  region_pms_constrain_world_0_area_5
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_5: u2,
-                ///  region_pms_constrain_world_0_area_6
-                REGION_PMS_CONSTRAIN_WORLD_0_AREA_6: u2,
-                padding: u18,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_2_REG
-            REGION_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_world_1_area_0
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_0: u2,
-                ///  region_pms_constrain_world_1_area_1
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_1: u2,
-                ///  region_pms_constrain_world_1_area_2
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_2: u2,
-                ///  region_pms_constrain_world_1_area_3
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_3: u2,
-                ///  region_pms_constrain_world_1_area_4
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_4: u2,
-                ///  region_pms_constrain_world_1_area_5
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_5: u2,
-                ///  region_pms_constrain_world_1_area_6
-                REGION_PMS_CONSTRAIN_WORLD_1_AREA_6: u2,
-                padding: u18,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_3_REG
-            REGION_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_0
-                REGION_PMS_CONSTRAIN_ADDR_0: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_4_REG
-            REGION_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_1
-                REGION_PMS_CONSTRAIN_ADDR_1: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_5_REG
-            REGION_PMS_CONSTRAIN_5: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_2
-                REGION_PMS_CONSTRAIN_ADDR_2: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_6_REG
-            REGION_PMS_CONSTRAIN_6: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_3
-                REGION_PMS_CONSTRAIN_ADDR_3: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_7_REG
-            REGION_PMS_CONSTRAIN_7: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_4
-                REGION_PMS_CONSTRAIN_ADDR_4: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_8_REG
-            REGION_PMS_CONSTRAIN_8: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_5
-                REGION_PMS_CONSTRAIN_ADDR_5: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_9_REG
-            REGION_PMS_CONSTRAIN_9: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_6
-                REGION_PMS_CONSTRAIN_ADDR_6: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_REGION_PMS_CONSTRAIN_10_REG
-            REGION_PMS_CONSTRAIN_10: mmio.Mmio(packed struct(u32) {
-                ///  region_pms_constrain_addr_7
-                REGION_PMS_CONSTRAIN_ADDR_7: u30,
-                padding: u2,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_0_REG
-            CORE_0_PIF_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_lock
-                CORE_0_PIF_PMS_MONITOR_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_1_REG
-            CORE_0_PIF_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_violate_clr
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_CLR: u1,
-                ///  core_0_pif_pms_monitor_violate_en
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_2_REG
-            CORE_0_PIF_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_violate_intr
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_INTR: u1,
-                ///  core_0_pif_pms_monitor_violate_status_hport_0
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HPORT_0: u1,
-                ///  core_0_pif_pms_monitor_violate_status_hsize
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
-                ///  core_0_pif_pms_monitor_violate_status_hwrite
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
-                ///  core_0_pif_pms_monitor_violate_status_hworld
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HWORLD: u2,
-                padding: u24,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_3_REG
-            CORE_0_PIF_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_violate_status_haddr
-                CORE_0_PIF_PMS_MONITOR_VIOLATE_STATUS_HADDR: u32,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_4_REG
-            CORE_0_PIF_PMS_MONITOR_4: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_nonword_violate_clr
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_CLR: u1,
-                ///  core_0_pif_pms_monitor_nonword_violate_en
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_5_REG
-            CORE_0_PIF_PMS_MONITOR_5: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_nonword_violate_intr
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_INTR: u1,
-                ///  core_0_pif_pms_monitor_nonword_violate_status_hsize
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HSIZE: u2,
-                ///  core_0_pif_pms_monitor_nonword_violate_status_hworld
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HWORLD: u2,
-                padding: u27,
-            }),
-            ///  SENSITIVE_CORE_0_PIF_PMS_MONITOR_6_REG
-            CORE_0_PIF_PMS_MONITOR_6: mmio.Mmio(packed struct(u32) {
-                ///  core_0_pif_pms_monitor_nonword_violate_status_haddr
-                CORE_0_PIF_PMS_MONITOR_NONWORD_VIOLATE_STATUS_HADDR: u32,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_0_REG
-            BACKUP_BUS_PMS_CONSTRAIN_0: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_constrain_lock
-                BACKUP_BUS_PMS_CONSTRAIN_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_1_REG
-            BACKUP_BUS_PMS_CONSTRAIN_1: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_constrain_uart
-                BACKUP_BUS_PMS_CONSTRAIN_UART: u2,
-                ///  backup_bus_pms_constrain_g0spi_1
-                BACKUP_BUS_PMS_CONSTRAIN_G0SPI_1: u2,
-                ///  backup_bus_pms_constrain_g0spi_0
-                BACKUP_BUS_PMS_CONSTRAIN_G0SPI_0: u2,
-                ///  backup_bus_pms_constrain_gpio
-                BACKUP_BUS_PMS_CONSTRAIN_GPIO: u2,
-                ///  backup_bus_pms_constrain_fe2
-                BACKUP_BUS_PMS_CONSTRAIN_FE2: u2,
-                ///  backup_bus_pms_constrain_fe
-                BACKUP_BUS_PMS_CONSTRAIN_FE: u2,
-                ///  backup_bus_pms_constrain_timer
-                BACKUP_BUS_PMS_CONSTRAIN_TIMER: u2,
-                ///  backup_bus_pms_constrain_rtc
-                BACKUP_BUS_PMS_CONSTRAIN_RTC: u2,
-                ///  backup_bus_pms_constrain_io_mux
-                BACKUP_BUS_PMS_CONSTRAIN_IO_MUX: u2,
-                ///  backup_bus_pms_constrain_wdg
-                BACKUP_BUS_PMS_CONSTRAIN_WDG: u2,
-                reserved24: u4,
-                ///  backup_bus_pms_constrain_misc
-                BACKUP_BUS_PMS_CONSTRAIN_MISC: u2,
-                ///  backup_bus_pms_constrain_i2c
-                BACKUP_BUS_PMS_CONSTRAIN_I2C: u2,
-                reserved30: u2,
-                ///  backup_bus_pms_constrain_uart1
-                BACKUP_BUS_PMS_CONSTRAIN_UART1: u2,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_2_REG
-            BACKUP_BUS_PMS_CONSTRAIN_2: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_constrain_bt
-                BACKUP_BUS_PMS_CONSTRAIN_BT: u2,
-                reserved4: u2,
-                ///  backup_bus_pms_constrain_i2c_ext0
-                BACKUP_BUS_PMS_CONSTRAIN_I2C_EXT0: u2,
-                ///  backup_bus_pms_constrain_uhci0
-                BACKUP_BUS_PMS_CONSTRAIN_UHCI0: u2,
-                reserved10: u2,
-                ///  backup_bus_pms_constrain_rmt
-                BACKUP_BUS_PMS_CONSTRAIN_RMT: u2,
-                reserved16: u4,
-                ///  backup_bus_pms_constrain_ledc
-                BACKUP_BUS_PMS_CONSTRAIN_LEDC: u2,
-                reserved22: u4,
-                ///  backup_bus_pms_constrain_bb
-                BACKUP_BUS_PMS_CONSTRAIN_BB: u2,
-                reserved26: u2,
-                ///  backup_bus_pms_constrain_timergroup
-                BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP: u2,
-                ///  backup_bus_pms_constrain_timergroup1
-                BACKUP_BUS_PMS_CONSTRAIN_TIMERGROUP1: u2,
-                ///  backup_bus_pms_constrain_systimer
-                BACKUP_BUS_PMS_CONSTRAIN_SYSTIMER: u2,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_3_REG
-            BACKUP_BUS_PMS_CONSTRAIN_3: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_constrain_spi_2
-                BACKUP_BUS_PMS_CONSTRAIN_SPI_2: u2,
-                reserved4: u2,
-                ///  backup_bus_pms_constrain_apb_ctrl
-                BACKUP_BUS_PMS_CONSTRAIN_APB_CTRL: u2,
-                reserved10: u4,
-                ///  backup_bus_pms_constrain_can
-                BACKUP_BUS_PMS_CONSTRAIN_CAN: u2,
-                reserved14: u2,
-                ///  backup_bus_pms_constrain_i2s1
-                BACKUP_BUS_PMS_CONSTRAIN_I2S1: u2,
-                reserved22: u6,
-                ///  backup_bus_pms_constrain_rwbt
-                BACKUP_BUS_PMS_CONSTRAIN_RWBT: u2,
-                reserved26: u2,
-                ///  backup_bus_pms_constrain_wifimac
-                BACKUP_BUS_PMS_CONSTRAIN_WIFIMAC: u2,
-                ///  backup_bus_pms_constrain_pwr
-                BACKUP_BUS_PMS_CONSTRAIN_PWR: u2,
-                padding: u2,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_CONSTRAIN_4_REG
-            BACKUP_BUS_PMS_CONSTRAIN_4: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  backup_bus_pms_constrain_usb_wrap
-                BACKUP_BUS_PMS_CONSTRAIN_USB_WRAP: u2,
-                ///  backup_bus_pms_constrain_crypto_peri
-                BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_PERI: u2,
-                ///  backup_bus_pms_constrain_crypto_dma
-                BACKUP_BUS_PMS_CONSTRAIN_CRYPTO_DMA: u2,
-                ///  backup_bus_pms_constrain_apb_adc
-                BACKUP_BUS_PMS_CONSTRAIN_APB_ADC: u2,
-                reserved12: u2,
-                ///  backup_bus_pms_constrain_bt_pwr
-                BACKUP_BUS_PMS_CONSTRAIN_BT_PWR: u2,
-                ///  backup_bus_pms_constrain_usb_device
-                BACKUP_BUS_PMS_CONSTRAIN_USB_DEVICE: u2,
-                padding: u16,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_0_REG
-            BACKUP_BUS_PMS_MONITOR_0: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_monitor_lock
-                BACKUP_BUS_PMS_MONITOR_LOCK: u1,
-                padding: u31,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_1_REG
-            BACKUP_BUS_PMS_MONITOR_1: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_monitor_violate_clr
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_CLR: u1,
-                ///  backup_bus_pms_monitor_violate_en
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_EN: u1,
-                padding: u30,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_2_REG
-            BACKUP_BUS_PMS_MONITOR_2: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_monitor_violate_intr
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_INTR: u1,
-                ///  backup_bus_pms_monitor_violate_status_htrans
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HTRANS: u2,
-                ///  backup_bus_pms_monitor_violate_status_hsize
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HSIZE: u3,
-                ///  backup_bus_pms_monitor_violate_status_hwrite
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_STATUS_HWRITE: u1,
-                padding: u25,
-            }),
-            ///  SENSITIVE_BACKUP_BUS_PMS_MONITOR_3_REG
-            BACKUP_BUS_PMS_MONITOR_3: mmio.Mmio(packed struct(u32) {
-                ///  backup_bus_pms_monitor_violate_haddr
-                BACKUP_BUS_PMS_MONITOR_VIOLATE_HADDR: u32,
-            }),
-            ///  SENSITIVE_CLOCK_GATE_REG
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  clk_en
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            reserved4092: [3720]u8,
-            ///  SENSITIVE_DATE_REG
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_date
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  SHA (Secure Hash Algorithm) Accelerator
-        pub const SHA = extern struct {
-            ///  Initial configuration register.
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  Sha mode.
-                MODE: u3,
-                padding: u29,
-            }),
-            ///  SHA 512/t configuration register 0.
-            T_STRING: mmio.Mmio(packed struct(u32) {
-                ///  Sha t_string (used if and only if mode == SHA_512/t).
-                T_STRING: u32,
-            }),
-            ///  SHA 512/t configuration register 1.
-            T_LENGTH: mmio.Mmio(packed struct(u32) {
-                ///  Sha t_length (used if and only if mode == SHA_512/t).
-                T_LENGTH: u6,
-                padding: u26,
-            }),
-            ///  DMA configuration register 0.
-            DMA_BLOCK_NUM: mmio.Mmio(packed struct(u32) {
-                ///  Dma-sha block number.
-                DMA_BLOCK_NUM: u6,
-                padding: u26,
-            }),
-            ///  Typical SHA configuration register 0.
-            START: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Reserved.
-                START: u31,
-            }),
-            ///  Typical SHA configuration register 1.
-            CONTINUE: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Reserved.
-                CONTINUE: u31,
-            }),
-            ///  Busy register.
-            BUSY: mmio.Mmio(packed struct(u32) {
-                ///  Sha busy state. 1'b0: idle. 1'b1: busy.
-                STATE: u1,
-                padding: u31,
-            }),
-            ///  DMA configuration register 1.
-            DMA_START: mmio.Mmio(packed struct(u32) {
-                ///  Start dma-sha.
-                DMA_START: u1,
-                padding: u31,
-            }),
-            ///  DMA configuration register 2.
-            DMA_CONTINUE: mmio.Mmio(packed struct(u32) {
-                ///  Continue dma-sha.
-                DMA_CONTINUE: u1,
-                padding: u31,
-            }),
-            ///  Interrupt clear register.
-            CLEAR_IRQ: mmio.Mmio(packed struct(u32) {
-                ///  Clear sha interrupt.
-                CLEAR_INTERRUPT: u1,
-                padding: u31,
-            }),
-            ///  Interrupt enable register.
-            IRQ_ENA: mmio.Mmio(packed struct(u32) {
-                ///  Sha interrupt enable register. 1'b0: disable(default). 1'b1: enable.
-                INTERRUPT_ENA: u1,
-                padding: u31,
-            }),
-            ///  Date register.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  Sha date information/ sha version information.
-                DATE: u30,
-                padding: u2,
-            }),
-            reserved64: [16]u8,
-            ///  Sha H memory which contains intermediate hash or finial hash.
-            H_MEM: [64]u8,
-            ///  Sha M memory which contains message.
-            M_MEM: [64]u8,
-        };
-
-        ///  SPI (Serial Peripheral Interface) Controller
-        pub const SPI0 = extern struct {
-            reserved8: [8]u8,
-            ///  SPI0 control register.
-            CTRL: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                ///  In the dummy phase the signal level of spi is output by the spi controller.
-                FDUMMY_OUT: u1,
-                reserved7: u3,
-                ///  Apply 2 signals during command phase 1:enable 0: disable
-                FCMD_DUAL: u1,
-                ///  Apply 4 signals during command phase 1:enable 0: disable
-                FCMD_QUAD: u1,
-                reserved13: u4,
-                ///  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
-                FASTRD_MODE: u1,
-                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
-                FREAD_DUAL: u1,
-                reserved18: u3,
-                ///  The bit is used to set MISO line polarity, 1: high 0, low
-                Q_POL: u1,
-                ///  The bit is used to set MOSI line polarity, 1: high 0, low
-                D_POL: u1,
-                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
-                FREAD_QUAD: u1,
-                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low.
-                WP: u1,
-                reserved23: u1,
-                ///  In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
-                FREAD_DIO: u1,
-                ///  In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
-                FREAD_QIO: u1,
-                padding: u7,
-            }),
-            ///  SPI0 control1 register.
-            CTRL1: mmio.Mmio(packed struct(u32) {
-                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
-                CLK_MODE: u2,
-                reserved30: u28,
-                ///  SPI0 RX FIFO reset signal.
-                RXFIFO_RST: u1,
-                padding: u1,
-            }),
-            ///  SPI0 control2 register.
-            CTRL2: mmio.Mmio(packed struct(u32) {
-                ///  (cycles-1) of prepare phase by spi clock this bits are combined with spi_mem_cs_setup bit.
-                CS_SETUP_TIME: u5,
-                ///  Spi cs signal is delayed to inactive by spi clock this bits are combined with spi_mem_cs_hold bit.
-                CS_HOLD_TIME: u5,
-                reserved25: u15,
-                ///  These bits are used to set the minimum CS high time tSHSL between SPI burst transfer when accesses to flash. tSHSL is (SPI_MEM_CS_HOLD_DELAY[5:0] + 1) MSPI core clock cycles.
-                CS_HOLD_DELAY: u6,
-                ///  The FSM will be reset.
-                SYNC_RESET: u1,
-            }),
-            ///  SPI clock division control register.
-            CLOCK: mmio.Mmio(packed struct(u32) {
-                ///  In the master mode it must be equal to spi_mem_clkcnt_N.
-                CLKCNT_L: u8,
-                ///  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
-                CLKCNT_H: u8,
-                ///  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
-                CLKCNT_N: u8,
-                reserved31: u7,
-                ///  Set this bit in 1-division mode.
-                CLK_EQU_SYSCLK: u1,
-            }),
-            ///  SPI0 user register.
-            USER: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  spi cs keep low when spi is in done phase. 1: enable 0: disable.
-                CS_HOLD: u1,
-                ///  spi cs is enable when spi is in prepare phase. 1: enable 0: disable.
-                CS_SETUP: u1,
-                reserved9: u1,
-                ///  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
-                CK_OUT_EDGE: u1,
-                reserved26: u16,
-                ///  spi clock is disable in dummy phase when the bit is enable.
-                USR_DUMMY_IDLE: u1,
-                reserved29: u2,
-                ///  This bit enable the dummy phase of an operation.
-                USR_DUMMY: u1,
-                padding: u2,
-            }),
-            ///  SPI0 user1 register.
-            USER1: mmio.Mmio(packed struct(u32) {
-                ///  The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
-                USR_DUMMY_CYCLELEN: u6,
-                reserved26: u20,
-                ///  The length in bits of address phase. The register value shall be (bit_num-1).
-                USR_ADDR_BITLEN: u6,
-            }),
-            ///  SPI0 user2 register.
-            USER2: mmio.Mmio(packed struct(u32) {
-                ///  The value of command.
-                USR_COMMAND_VALUE: u16,
-                reserved28: u12,
-                ///  The length in bits of command phase. The register value shall be (bit_num-1)
-                USR_COMMAND_BITLEN: u4,
-            }),
-            reserved44: [8]u8,
-            ///  SPI0 read control register.
-            RD_STATUS: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
-                WB_MODE: u8,
-                padding: u8,
-            }),
-            reserved52: [4]u8,
-            ///  SPI0 misc register
-            MISC: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                ///  The bit is used to indicate the spi0_mst_st controlled transmitting is done.
-                TRANS_END: u1,
-                ///  The bit is used to enable the interrupt of spi0_mst_st controlled transmitting is done.
-                TRANS_END_INT_ENA: u1,
-                ///  The bit is used to indicate the spi0_slv_st controlled transmitting is done.
-                CSPI_ST_TRANS_END: u1,
-                ///  The bit is used to enable the interrupt of spi0_slv_st controlled transmitting is done.
-                CSPI_ST_TRANS_END_INT_ENA: u1,
-                reserved9: u2,
-                ///  1: spi clk line is high when idle 0: spi clk line is low when idle
-                CK_IDLE_EDGE: u1,
-                ///  spi cs line keep low when the bit is set.
-                CS_KEEP_ACTIVE: u1,
-                padding: u21,
-            }),
-            reserved60: [4]u8,
-            ///  SPI0 bit mode control register.
-            CACHE_FCTRL: mmio.Mmio(packed struct(u32) {
-                ///  For SPI0, Cache access enable, 1: enable, 0:disable.
-                CACHE_REQ_EN: u1,
-                ///  For SPI0, cache read flash with 4 bytes address, 1: enable, 0:disable.
-                CACHE_USR_ADDR_4BYTE: u1,
-                ///  For SPI0, cache read flash for user define command, 1: enable, 0:disable.
-                CACHE_FLASH_USR_CMD: u1,
-                ///  For SPI0 flash, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FDIN_DUAL: u1,
-                ///  For SPI0 flash, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FDOUT_DUAL: u1,
-                ///  For SPI0 flash, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FADDR_DUAL: u1,
-                ///  For SPI0 flash, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FDIN_QUAD: u1,
-                ///  For SPI0 flash, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FDOUT_QUAD: u1,
-                ///  For SPI0 flash, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FADDR_QUAD: u1,
-                padding: u23,
-            }),
-            reserved84: [20]u8,
-            ///  SPI0 FSM status register
-            FSM: mmio.Mmio(packed struct(u32) {
-                ///  The current status of SPI0 slave FSM: spi0_slv_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
-                CSPI_ST: u4,
-                ///  The current status of SPI0 master FSM: spi0_mst_st. 0: idle state, 1:EM_CACHE_GRANT , 2: program/erase suspend state, 3: SPI0 read data state, 4: wait cache/EDMA sent data is stored in SPI0 TX FIFO, 5: SPI0 write data state.
-                EM_ST: u3,
-                ///  The lock delay time of SPI0/1 arbiter by spi0_slv_st, after PER is sent by SPI1.
-                CSPI_LOCK_DELAY_TIME: u5,
-                padding: u20,
-            }),
-            reserved168: [80]u8,
-            ///  SPI0 timing calibration register
-            TIMING_CALI: mmio.Mmio(packed struct(u32) {
-                ///  The bit is used to enable timing adjust clock for all reading operations.
-                TIMING_CLK_ENA: u1,
-                ///  The bit is used to enable timing auto-calibration for all reading operations.
-                TIMING_CALI: u1,
-                ///  add extra dummy spi clock cycle length for spi clock calibration.
-                EXTRA_DUMMY_CYCLELEN: u3,
-                padding: u27,
-            }),
-            ///  SPI0 input delay mode control register
-            DIN_MODE: mmio.Mmio(packed struct(u32) {
-                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
-                DIN0_MODE: u2,
-                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
-                DIN1_MODE: u2,
-                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
-                DIN2_MODE: u2,
-                ///  the input signals are delayed by system clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the posedge of clk_160, 4 input with the negedge of clk_160, 5: input with the spi_clk high edge, 6: input with the spi_clk low edge
-                DIN3_MODE: u2,
-                padding: u24,
-            }),
-            ///  SPI0 input delay number control register
-            DIN_NUM: mmio.Mmio(packed struct(u32) {
-                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
-                DIN0_NUM: u2,
-                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
-                DIN1_NUM: u2,
-                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
-                DIN2_NUM: u2,
-                ///  the input signals are delayed by system clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,...
-                DIN3_NUM: u2,
-                padding: u24,
-            }),
-            ///  SPI0 output delay mode control register
-            DOUT_MODE: mmio.Mmio(packed struct(u32) {
-                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
-                DOUT0_MODE: u1,
-                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
-                DOUT1_MODE: u1,
-                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
-                DOUT2_MODE: u1,
-                ///  the output signals are delayed by system clock cycles, 0: output without delayed, 1: output with the posedge of clk_apb,2 output with the negedge of clk_apb, 3: output with the posedge of clk_160,4 output with the negedge of clk_160,5: output with the spi_clk high edge ,6: output with the spi_clk low edge
-                DOUT3_MODE: u1,
-                padding: u28,
-            }),
-            reserved220: [36]u8,
-            ///  SPI0 clk_gate register
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  Register clock gate enable signal. 1: Enable. 0: Disable.
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            ///  SPI0 module clock select register
-            CORE_CLK_SEL: mmio.Mmio(packed struct(u32) {
-                ///  When the digital system clock selects PLL clock and the frequency of PLL clock is 480MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 120MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used. When the digital system clock selects PLL clock and the frequency of PLL clock is 320MHz, the value of reg_spi01_clk_sel: 0: SPI0/1 module clock (clk) is 80MHz. 1: SPI0/1 module clock (clk) is 80MHz. 2: SPI0/1 module clock (clk) 160MHz. 3: Not used.
-                SPI01_CLK_SEL: u2,
-                padding: u30,
-            }),
-            reserved1020: [792]u8,
-            ///  Version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  SPI register version.
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  SPI (Serial Peripheral Interface) Controller
-        pub const SPI1 = extern struct {
-            ///  SPI1 memory command register
-            CMD: mmio.Mmio(packed struct(u32) {
-                ///  The current status of SPI1 master FSM.
-                SPI1_MST_ST: u4,
-                ///  The current status of SPI1 slave FSM: mspi_st. 0: idle state, 1: preparation state, 2: send command state, 3: send address state, 4: wait state, 5: read data state, 6:write data state, 7: done state, 8: read data end state.
-                MSPI_ST: u4,
-                reserved17: u9,
-                ///  In user mode, it is set to indicate that program/erase operation will be triggered. The bit is combined with spi_mem_usr bit. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_PE: u1,
-                ///  User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                USR: u1,
-                ///  Drive Flash into high performance mode. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_HPM: u1,
-                ///  This bit combined with reg_resandres bit releases Flash from the power-down state or high performance mode and obtains the devices ID. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_RES: u1,
-                ///  Drive Flash into power down. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_DP: u1,
-                ///  Chip erase enable. Chip erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_CE: u1,
-                ///  Block erase enable(32KB) . Block erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_BE: u1,
-                ///  Sector erase enable(4KB). Sector erase operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_SE: u1,
-                ///  Page program enable(1 byte ~256 bytes data to be programmed). Page program operation will be triggered when the bit is set. The bit will be cleared once the operation done .1: enable 0: disable.
-                FLASH_PP: u1,
-                ///  Write status register enable. Write status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_WRSR: u1,
-                ///  Read status register-1. Read status operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_RDSR: u1,
-                ///  Read JEDEC ID . Read ID command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
-                FLASH_RDID: u1,
-                ///  Write flash disable. Write disable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
-                FLASH_WRDI: u1,
-                ///  Write flash enable. Write enable command will be sent when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
-                FLASH_WREN: u1,
-                ///  Read flash enable. Read flash operation will be triggered when the bit is set. The bit will be cleared once the operation done. 1: enable 0: disable.
-                FLASH_READ: u1,
-            }),
-            ///  SPI1 address register
-            ADDR: mmio.Mmio(packed struct(u32) {
-                ///  In user mode, it is the memory address. other then the bit0-bit23 is the memory address, the bit24-bit31 are the byte length of a transfer.
-                USR_ADDR_VALUE: u32,
-            }),
-            ///  SPI1 control register.
-            CTRL: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                ///  In the dummy phase the signal level of spi is output by the spi controller.
-                FDUMMY_OUT: u1,
-                reserved7: u3,
-                ///  Apply 2 signals during command phase 1:enable 0: disable
-                FCMD_DUAL: u1,
-                ///  Apply 4 signals during command phase 1:enable 0: disable
-                FCMD_QUAD: u1,
-                reserved10: u1,
-                ///  For SPI1, initialize crc32 module before writing encrypted data to flash. Active low.
-                FCS_CRC_EN: u1,
-                ///  For SPI1, enable crc32 when writing encrypted data to flash. 1: enable 0:disable
-                TX_CRC_EN: u1,
-                reserved13: u1,
-                ///  This bit enable the bits: spi_mem_fread_qio, spi_mem_fread_dio, spi_mem_fread_qout and spi_mem_fread_dout. 1: enable 0: disable.
-                FASTRD_MODE: u1,
-                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable.
-                FREAD_DUAL: u1,
-                ///  The Device ID is read out to SPI_MEM_RD_STATUS register, this bit combine with spi_mem_flash_res bit. 1: enable 0: disable.
-                RESANDRES: u1,
-                reserved18: u2,
-                ///  The bit is used to set MISO line polarity, 1: high 0, low
-                Q_POL: u1,
-                ///  The bit is used to set MOSI line polarity, 1: high 0, low
-                D_POL: u1,
-                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable.
-                FREAD_QUAD: u1,
-                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low.
-                WP: u1,
-                ///  two bytes data will be written to status register when it is set. 1: enable 0: disable.
-                WRSR_2B: u1,
-                ///  In the read operations address phase and read-data phase apply 2 signals. 1: enable 0: disable.
-                FREAD_DIO: u1,
-                ///  In the read operations address phase and read-data phase apply 4 signals. 1: enable 0: disable.
-                FREAD_QIO: u1,
-                padding: u7,
-            }),
-            ///  SPI1 control1 register.
-            CTRL1: mmio.Mmio(packed struct(u32) {
-                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on.
-                CLK_MODE: u2,
-                ///  After RES/DP/HPM command is sent, SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 512) SPI_CLK cycles.
-                CS_HOLD_DLY_RES: u10,
-                padding: u20,
-            }),
-            ///  SPI1 control2 register.
-            CTRL2: mmio.Mmio(packed struct(u32) {
-                reserved31: u31,
-                ///  The FSM will be reset.
-                SYNC_RESET: u1,
-            }),
-            ///  SPI1 clock division control register.
-            CLOCK: mmio.Mmio(packed struct(u32) {
-                ///  In the master mode it must be equal to spi_mem_clkcnt_N.
-                CLKCNT_L: u8,
-                ///  In the master mode it must be floor((spi_mem_clkcnt_N+1)/2-1).
-                CLKCNT_H: u8,
-                ///  In the master mode it is the divider of spi_mem_clk. So spi_mem_clk frequency is system/(spi_mem_clkcnt_N+1)
-                CLKCNT_N: u8,
-                reserved31: u7,
-                ///  reserved
-                CLK_EQU_SYSCLK: u1,
-            }),
-            ///  SPI1 user register.
-            USER: mmio.Mmio(packed struct(u32) {
-                reserved9: u9,
-                ///  the bit combined with spi_mem_mosi_delay_mode bits to set mosi signal delay mode.
-                CK_OUT_EDGE: u1,
-                reserved12: u2,
-                ///  In the write operations read-data phase apply 2 signals
-                FWRITE_DUAL: u1,
-                ///  In the write operations read-data phase apply 4 signals
-                FWRITE_QUAD: u1,
-                ///  In the write operations address phase and read-data phase apply 2 signals.
-                FWRITE_DIO: u1,
-                ///  In the write operations address phase and read-data phase apply 4 signals.
-                FWRITE_QIO: u1,
-                reserved24: u8,
-                ///  read-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
-                USR_MISO_HIGHPART: u1,
-                ///  write-data phase only access to high-part of the buffer spi_mem_w8~spi_mem_w15. 1: enable 0: disable.
-                USR_MOSI_HIGHPART: u1,
-                ///  SPI clock is disable in dummy phase when the bit is enable.
-                USR_DUMMY_IDLE: u1,
-                ///  This bit enable the write-data phase of an operation.
-                USR_MOSI: u1,
-                ///  This bit enable the read-data phase of an operation.
-                USR_MISO: u1,
-                ///  This bit enable the dummy phase of an operation.
-                USR_DUMMY: u1,
-                ///  This bit enable the address phase of an operation.
-                USR_ADDR: u1,
-                ///  This bit enable the command phase of an operation.
-                USR_COMMAND: u1,
-            }),
-            ///  SPI1 user1 register.
-            USER1: mmio.Mmio(packed struct(u32) {
-                ///  The length in spi_mem_clk cycles of dummy phase. The register value shall be (cycle_num-1).
-                USR_DUMMY_CYCLELEN: u6,
-                reserved26: u20,
-                ///  The length in bits of address phase. The register value shall be (bit_num-1).
-                USR_ADDR_BITLEN: u6,
-            }),
-            ///  SPI1 user2 register.
-            USER2: mmio.Mmio(packed struct(u32) {
-                ///  The value of command.
-                USR_COMMAND_VALUE: u16,
-                reserved28: u12,
-                ///  The length in bits of command phase. The register value shall be (bit_num-1)
-                USR_COMMAND_BITLEN: u4,
-            }),
-            ///  SPI1 send data bit length control register.
-            MOSI_DLEN: mmio.Mmio(packed struct(u32) {
-                ///  The length in bits of write-data. The register value shall be (bit_num-1).
-                USR_MOSI_DBITLEN: u10,
-                padding: u22,
-            }),
-            ///  SPI1 receive data bit length control register.
-            MISO_DLEN: mmio.Mmio(packed struct(u32) {
-                ///  The length in bits of read-data. The register value shall be (bit_num-1).
-                USR_MISO_DBITLEN: u10,
-                padding: u22,
-            }),
-            ///  SPI1 status register.
-            RD_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  The value is stored when set spi_mem_flash_rdsr bit and spi_mem_flash_res bit.
-                STATUS: u16,
-                ///  Mode bits in the flash fast read mode it is combined with spi_mem_fastrd_mode bit.
-                WB_MODE: u8,
-                padding: u8,
-            }),
-            reserved52: [4]u8,
-            ///  SPI1 misc register
-            MISC: mmio.Mmio(packed struct(u32) {
-                ///  SPI_CS0 pin enable, 1: disable SPI_CS0, 0: SPI_CS0 pin is active to select SPI device, such as flash, external RAM and so on.
-                CS0_DIS: u1,
-                ///  SPI_CS1 pin enable, 1: disable SPI_CS1, 0: SPI_CS1 pin is active to select SPI device, such as flash, external RAM and so on.
-                CS1_DIS: u1,
-                reserved9: u7,
-                ///  1: spi clk line is high when idle 0: spi clk line is low when idle
-                CK_IDLE_EDGE: u1,
-                ///  spi cs line keep low when the bit is set.
-                CS_KEEP_ACTIVE: u1,
-                padding: u21,
-            }),
-            ///  SPI1 TX CRC data register.
-            TX_CRC: mmio.Mmio(packed struct(u32) {
-                ///  For SPI1, the value of crc32.
-                DATA: u32,
-            }),
-            ///  SPI1 bit mode control register.
-            CACHE_FCTRL: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  For SPI1, cache read flash with 4 bytes address, 1: enable, 0:disable.
-                CACHE_USR_ADDR_4BYTE: u1,
-                reserved3: u1,
-                ///  For SPI1, din phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FDIN_DUAL: u1,
-                ///  For SPI1, dout phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FDOUT_DUAL: u1,
-                ///  For SPI1, address phase apply 2 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_dio.
-                FADDR_DUAL: u1,
-                ///  For SPI1, din phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FDIN_QUAD: u1,
-                ///  For SPI1, dout phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FDOUT_QUAD: u1,
-                ///  For SPI1, address phase apply 4 signals. 1: enable 0: disable. The bit is the same with spi_mem_fread_qio.
-                FADDR_QUAD: u1,
-                padding: u23,
-            }),
-            reserved88: [24]u8,
-            ///  SPI1 memory data buffer0
-            W0: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF0: u32,
-            }),
-            ///  SPI1 memory data buffer1
-            W1: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF1: u32,
-            }),
-            ///  SPI1 memory data buffer2
-            W2: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF2: u32,
-            }),
-            ///  SPI1 memory data buffer3
-            W3: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF3: u32,
-            }),
-            ///  SPI1 memory data buffer4
-            W4: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF4: u32,
-            }),
-            ///  SPI1 memory data buffer5
-            W5: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF5: u32,
-            }),
-            ///  SPI1 memory data buffer6
-            W6: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF6: u32,
-            }),
-            ///  SPI1 memory data buffer7
-            W7: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF7: u32,
-            }),
-            ///  SPI1 memory data buffer8
-            W8: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF8: u32,
-            }),
-            ///  SPI1 memory data buffer9
-            W9: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF9: u32,
-            }),
-            ///  SPI1 memory data buffer10
-            W10: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF10: u32,
-            }),
-            ///  SPI1 memory data buffer11
-            W11: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF11: u32,
-            }),
-            ///  SPI1 memory data buffer12
-            W12: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF12: u32,
-            }),
-            ///  SPI1 memory data buffer13
-            W13: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF13: u32,
-            }),
-            ///  SPI1 memory data buffer14
-            W14: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF14: u32,
-            }),
-            ///  SPI1 memory data buffer15
-            W15: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF15: u32,
-            }),
-            ///  SPI1 wait idle control register
-            FLASH_WAITI_CTRL: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  The dummy phase enable when wait flash idle (RDSR)
-                WAITI_DUMMY: u1,
-                ///  The command to wait flash idle(RDSR).
-                WAITI_CMD: u8,
-                ///  The dummy cycle length when wait flash idle(RDSR).
-                WAITI_DUMMY_CYCLELEN: u6,
-                padding: u16,
-            }),
-            ///  SPI1 flash suspend control register
-            FLASH_SUS_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  program erase resume bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_PER: u1,
-                ///  program erase suspend bit, program erase suspend operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable.
-                FLASH_PES: u1,
-                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase resume command is sent. 0: SPI1 does not wait after program erase resume command is sent.
-                FLASH_PER_WAIT_EN: u1,
-                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4 or *128) SPI_CLK cycles after program erase suspend command is sent. 0: SPI1 does not wait after program erase suspend command is sent.
-                FLASH_PES_WAIT_EN: u1,
-                ///  Set this bit to enable PES end triggers PER transfer option. If this bit is 0, application should send PER after PES is done.
-                PES_PER_EN: u1,
-                ///  Set this bit to enable Auto-suspending function.
-                FLASH_PES_EN: u1,
-                ///  The mask value when check SUS/SUS1/SUS2 status bit. If the read status value is status_in[15:0](only status_in[7:0] is valid when only one byte of data is read out, status_in[15:0] is valid when two bytes of data are read out), SUS/SUS1/SUS2 = status_in[15:0]^ SPI_MEM_PESR_END_MSK[15:0].
-                PESR_END_MSK: u16,
-                ///  1: Read two bytes when check flash SUS/SUS1/SUS2 status bit. 0: Read one byte when check flash SUS/SUS1/SUS2 status bit
-                RD_SUS_2B: u1,
-                ///  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the resume status of flash. 0: Only need to check WIP is 0.
-                PER_END_EN: u1,
-                ///  1: Both WIP and SUS/SUS1/SUS2 bits should be checked to insure the suspend status of flash. 0: Only need to check WIP is 0.
-                PES_END_EN: u1,
-                ///  When SPI1 checks SUS/SUS1/SUS2 bits fail for SPI_MEM_SUS_TIMEOUT_CNT[6:0] times, it will be treated as check pass.
-                SUS_TIMEOUT_CNT: u7,
-            }),
-            ///  SPI1 flash suspend command register
-            FLASH_SUS_CMD: mmio.Mmio(packed struct(u32) {
-                ///  Program/Erase resume command.
-                FLASH_PER_COMMAND: u8,
-                ///  Program/Erase suspend command.
-                FLASH_PES_COMMAND: u8,
-                ///  Flash SUS/SUS1/SUS2 status bit read command. The command should be sent when SUS/SUS1/SUS2 bit should be checked to insure the suspend or resume status of flash.
-                WAIT_PESR_COMMAND: u16,
-            }),
-            ///  SPI1 flash suspend status register
-            SUS_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  The status of flash suspend, only used in SPI1.
-                FLASH_SUS: u1,
-                ///  1: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[15:0] to check SUS/SUS1/SUS2 bit. 0: SPI1 sends out SPI_MEM_WAIT_PESR_COMMAND[7:0] to check SUS/SUS1/SUS2 bit.
-                WAIT_PESR_CMD_2B: u1,
-                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after HPM command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after HPM command is sent.
-                FLASH_HPM_DLY_128: u1,
-                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after RES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after RES command is sent.
-                FLASH_RES_DLY_128: u1,
-                ///  1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after DP command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after DP command is sent.
-                FLASH_DP_DLY_128: u1,
-                ///  Valid when SPI_MEM_FLASH_PER_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PER command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PER command is sent.
-                FLASH_PER_DLY_128: u1,
-                ///  Valid when SPI_MEM_FLASH_PES_WAIT_EN is 1. 1: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 128) SPI_CLK cycles after PES command is sent. 0: SPI1 waits (SPI_MEM_CS_HOLD_DELAY_RES[9:0] * 4) SPI_CLK cycles after PES command is sent.
-                FLASH_PES_DLY_128: u1,
-                ///  1: Enable SPI0 lock SPI0/1 arbiter option. 0: Disable it.
-                SPI0_LOCK_EN: u1,
-                padding: u24,
-            }),
-            ///  SPI1 timing control register
-            TIMING_CALI: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  The bit is used to enable timing auto-calibration for all reading operations.
-                TIMING_CALI: u1,
-                ///  add extra dummy spi clock cycle length for spi clock calibration.
-                EXTRA_DUMMY_CYCLELEN: u3,
-                padding: u27,
-            }),
-            reserved192: [20]u8,
-            ///  SPI1 interrupt enable register
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The enable bit for SPI_MEM_PER_END_INT interrupt.
-                PER_END_INT_ENA: u1,
-                ///  The enable bit for SPI_MEM_PES_END_INT interrupt.
-                PES_END_INT_ENA: u1,
-                ///  The enable bit for SPI_MEM_WPE_END_INT interrupt.
-                WPE_END_INT_ENA: u1,
-                ///  The enable bit for SPI_MEM_SLV_ST_END_INT interrupt.
-                SLV_ST_END_INT_ENA: u1,
-                ///  The enable bit for SPI_MEM_MST_ST_END_INT interrupt.
-                MST_ST_END_INT_ENA: u1,
-                padding: u27,
-            }),
-            ///  SPI1 interrupt clear register
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The clear bit for SPI_MEM_PER_END_INT interrupt.
-                PER_END_INT_CLR: u1,
-                ///  The clear bit for SPI_MEM_PES_END_INT interrupt.
-                PES_END_INT_CLR: u1,
-                ///  The clear bit for SPI_MEM_WPE_END_INT interrupt.
-                WPE_END_INT_CLR: u1,
-                ///  The clear bit for SPI_MEM_SLV_ST_END_INT interrupt.
-                SLV_ST_END_INT_CLR: u1,
-                ///  The clear bit for SPI_MEM_MST_ST_END_INT interrupt.
-                MST_ST_END_INT_CLR: u1,
-                padding: u27,
-            }),
-            ///  SPI1 interrupt raw register
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  The raw bit for SPI_MEM_PER_END_INT interrupt. 1: Triggered when Auto Resume command (0x7A) is sent and flash is resumed. 0: Others.
-                PER_END_INT_RAW: u1,
-                ///  The raw bit for SPI_MEM_PES_END_INT interrupt.1: Triggered when Auto Suspend command (0x75) is sent and flash is suspended. 0: Others.
-                PES_END_INT_RAW: u1,
-                ///  The raw bit for SPI_MEM_WPE_END_INT interrupt. 1: Triggered when WRSR/PP/SE/BE/CE is sent and flash is already idle. 0: Others.
-                WPE_END_INT_RAW: u1,
-                ///  The raw bit for SPI_MEM_SLV_ST_END_INT interrupt. 1: Triggered when spi1_slv_st is changed from non idle state to idle state. It means that SPI_CS raises high. 0: Others
-                SLV_ST_END_INT_RAW: u1,
-                ///  The raw bit for SPI_MEM_MST_ST_END_INT interrupt. 1: Triggered when spi1_mst_st is changed from non idle state to idle state. 0: Others.
-                MST_ST_END_INT_RAW: u1,
-                padding: u27,
-            }),
-            ///  SPI1 interrupt status register
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The status bit for SPI_MEM_PER_END_INT interrupt.
-                PER_END_INT_ST: u1,
-                ///  The status bit for SPI_MEM_PES_END_INT interrupt.
-                PES_END_INT_ST: u1,
-                ///  The status bit for SPI_MEM_WPE_END_INT interrupt.
-                WPE_END_INT_ST: u1,
-                ///  The status bit for SPI_MEM_SLV_ST_END_INT interrupt.
-                SLV_ST_END_INT_ST: u1,
-                ///  The status bit for SPI_MEM_MST_ST_END_INT interrupt.
-                MST_ST_END_INT_ST: u1,
-                padding: u27,
-            }),
-            reserved220: [12]u8,
-            ///  SPI1 clk_gate register
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  Register clock gate enable signal. 1: Enable. 0: Disable.
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            reserved1020: [796]u8,
-            ///  Version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  Version control register
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  SPI (Serial Peripheral Interface) Controller
-        pub const SPI2 = extern struct {
-            ///  Command control register
-            CMD: mmio.Mmio(packed struct(u32) {
-                ///  Define the APB cycles of SPI_CONF state. Can be configured in CONF state.
-                CONF_BITLEN: u18,
-                reserved23: u5,
-                ///  Set this bit to synchronize SPI registers from APB clock domain into SPI module clock domain, which is only used in SPI master mode.
-                UPDATE: u1,
-                ///  User define command enable. An operation will be triggered when the bit is set. The bit will be cleared once the operation done.1: enable 0: disable. Can not be changed by CONF_buf.
-                USR: u1,
-                padding: u7,
-            }),
-            ///  Address value register
-            ADDR: mmio.Mmio(packed struct(u32) {
-                ///  Address to slave. Can be configured in CONF state.
-                USR_ADDR_VALUE: u32,
-            }),
-            ///  SPI control register
-            CTRL: mmio.Mmio(packed struct(u32) {
-                reserved3: u3,
-                ///  In the dummy phase the signal level of spi is output by the spi controller. Can be configured in CONF state.
-                DUMMY_OUT: u1,
-                reserved5: u1,
-                ///  Apply 2 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
-                FADDR_DUAL: u1,
-                ///  Apply 4 signals during addr phase 1:enable 0: disable. Can be configured in CONF state.
-                FADDR_QUAD: u1,
-                reserved8: u1,
-                ///  Apply 2 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
-                FCMD_DUAL: u1,
-                ///  Apply 4 signals during command phase 1:enable 0: disable. Can be configured in CONF state.
-                FCMD_QUAD: u1,
-                reserved14: u4,
-                ///  In the read operations, read-data phase apply 2 signals. 1: enable 0: disable. Can be configured in CONF state.
-                FREAD_DUAL: u1,
-                ///  In the read operations read-data phase apply 4 signals. 1: enable 0: disable. Can be configured in CONF state.
-                FREAD_QUAD: u1,
-                reserved18: u2,
-                ///  The bit is used to set MISO line polarity, 1: high 0, low. Can be configured in CONF state.
-                Q_POL: u1,
-                ///  The bit is used to set MOSI line polarity, 1: high 0, low. Can be configured in CONF state.
-                D_POL: u1,
-                ///  SPI_HOLD output value when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
-                HOLD_POL: u1,
-                ///  Write protect signal output when SPI is idle. 1: output high, 0: output low. Can be configured in CONF state.
-                WP_POL: u1,
-                reserved25: u3,
-                ///  In read-data (MISO) phase 1: LSB first 0: MSB first. Can be configured in CONF state.
-                RD_BIT_ORDER: u1,
-                ///  In command address write-data (MOSI) phases 1: LSB firs 0: MSB first. Can be configured in CONF state.
-                WR_BIT_ORDER: u1,
-                padding: u5,
-            }),
-            ///  SPI clock control register
-            CLOCK: mmio.Mmio(packed struct(u32) {
-                ///  In the master mode it must be equal to spi_clkcnt_N. In the slave mode it must be 0. Can be configured in CONF state.
-                CLKCNT_L: u6,
-                ///  In the master mode it must be floor((spi_clkcnt_N+1)/2-1). In the slave mode it must be 0. Can be configured in CONF state.
-                CLKCNT_H: u6,
-                ///  In the master mode it is the divider of spi_clk. So spi_clk frequency is system/(spi_clkdiv_pre+1)/(spi_clkcnt_N+1). Can be configured in CONF state.
-                CLKCNT_N: u6,
-                ///  In the master mode it is pre-divider of spi_clk. Can be configured in CONF state.
-                CLKDIV_PRE: u4,
-                reserved31: u9,
-                ///  In the master mode 1: spi_clk is eqaul to system 0: spi_clk is divided from system clock. Can be configured in CONF state.
-                CLK_EQU_SYSCLK: u1,
-            }),
-            ///  SPI USER control register
-            USER: mmio.Mmio(packed struct(u32) {
-                ///  Set the bit to enable full duplex communication. 1: enable 0: disable. Can be configured in CONF state.
-                DOUTDIN: u1,
-                reserved3: u2,
-                ///  Both for master mode and slave mode. 1: spi controller is in QPI mode. 0: others. Can be configured in CONF state.
-                QPI_MODE: u1,
-                reserved5: u1,
-                ///  In the slave mode, this bit can be used to change the polarity of tsck. 0: tsck = spi_ck_i. 1:tsck = !spi_ck_i.
-                TSCK_I_EDGE: u1,
-                ///  spi cs keep low when spi is in done phase. 1: enable 0: disable. Can be configured in CONF state.
-                CS_HOLD: u1,
-                ///  spi cs is enable when spi is in prepare phase. 1: enable 0: disable. Can be configured in CONF state.
-                CS_SETUP: u1,
-                ///  In the slave mode, this bit can be used to change the polarity of rsck. 0: rsck = !spi_ck_i. 1:rsck = spi_ck_i.
-                RSCK_I_EDGE: u1,
-                ///  the bit combined with spi_mosi_delay_mode bits to set mosi signal delay mode. Can be configured in CONF state.
-                CK_OUT_EDGE: u1,
-                reserved12: u2,
-                ///  In the write operations read-data phase apply 2 signals. Can be configured in CONF state.
-                FWRITE_DUAL: u1,
-                ///  In the write operations read-data phase apply 4 signals. Can be configured in CONF state.
-                FWRITE_QUAD: u1,
-                reserved15: u1,
-                ///  1: Enable the DMA CONF phase of next seg-trans operation, which means seg-trans will continue. 0: The seg-trans will end after the current SPI seg-trans or this is not seg-trans mode. Can be configured in CONF state.
-                USR_CONF_NXT: u1,
-                reserved17: u1,
-                ///  Set the bit to enable 3-line half duplex communication mosi and miso signals share the same pin. 1: enable 0: disable. Can be configured in CONF state.
-                SIO: u1,
-                reserved24: u6,
-                ///  read-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
-                USR_MISO_HIGHPART: u1,
-                ///  write-data phase only access to high-part of the buffer spi_w8~spi_w15. 1: enable 0: disable. Can be configured in CONF state.
-                USR_MOSI_HIGHPART: u1,
-                ///  spi clock is disable in dummy phase when the bit is enable. Can be configured in CONF state.
-                USR_DUMMY_IDLE: u1,
-                ///  This bit enable the write-data phase of an operation. Can be configured in CONF state.
-                USR_MOSI: u1,
-                ///  This bit enable the read-data phase of an operation. Can be configured in CONF state.
-                USR_MISO: u1,
-                ///  This bit enable the dummy phase of an operation. Can be configured in CONF state.
-                USR_DUMMY: u1,
-                ///  This bit enable the address phase of an operation. Can be configured in CONF state.
-                USR_ADDR: u1,
-                ///  This bit enable the command phase of an operation. Can be configured in CONF state.
-                USR_COMMAND: u1,
-            }),
-            ///  SPI USER control register 1
-            USER1: mmio.Mmio(packed struct(u32) {
-                ///  The length in spi_clk cycles of dummy phase. The register value shall be (cycle_num-1). Can be configured in CONF state.
-                USR_DUMMY_CYCLELEN: u8,
-                reserved16: u8,
-                ///  1: SPI transfer is ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI RX AFIFO wfull error is valid in GP-SPI master FD/HD-mode.
-                MST_WFULL_ERR_END_EN: u1,
-                ///  (cycles+1) of prepare phase by spi clock this bits are combined with spi_cs_setup bit. Can be configured in CONF state.
-                CS_SETUP_TIME: u5,
-                ///  delay cycles of cs pin by spi clock this bits are combined with spi_cs_hold bit. Can be configured in CONF state.
-                CS_HOLD_TIME: u5,
-                ///  The length in bits of address phase. The register value shall be (bit_num-1). Can be configured in CONF state.
-                USR_ADDR_BITLEN: u5,
-            }),
-            ///  SPI USER control register 2
-            USER2: mmio.Mmio(packed struct(u32) {
-                ///  The value of command. Can be configured in CONF state.
-                USR_COMMAND_VALUE: u16,
-                reserved27: u11,
-                ///  1: SPI transfer is ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode. 0: SPI transfer is not ended when SPI TX AFIFO read empty error is valid in GP-SPI master FD/HD-mode.
-                MST_REMPTY_ERR_END_EN: u1,
-                ///  The length in bits of command phase. The register value shall be (bit_num-1). Can be configured in CONF state.
-                USR_COMMAND_BITLEN: u4,
-            }),
-            ///  SPI data bit length control register
-            MS_DLEN: mmio.Mmio(packed struct(u32) {
-                ///  The value of these bits is the configured SPI transmission data bit length in master mode DMA controlled transfer or CPU controlled transfer. The value is also the configured bit length in slave mode DMA RX controlled transfer. The register value shall be (bit_num-1). Can be configured in CONF state.
-                MS_DATA_BITLEN: u18,
-                padding: u14,
-            }),
-            ///  SPI misc register
-            MISC: mmio.Mmio(packed struct(u32) {
-                ///  SPI CS0 pin enable, 1: disable CS0, 0: spi_cs0 signal is from/to CS0 pin. Can be configured in CONF state.
-                CS0_DIS: u1,
-                ///  SPI CS1 pin enable, 1: disable CS1, 0: spi_cs1 signal is from/to CS1 pin. Can be configured in CONF state.
-                CS1_DIS: u1,
-                ///  SPI CS2 pin enable, 1: disable CS2, 0: spi_cs2 signal is from/to CS2 pin. Can be configured in CONF state.
-                CS2_DIS: u1,
-                ///  SPI CS3 pin enable, 1: disable CS3, 0: spi_cs3 signal is from/to CS3 pin. Can be configured in CONF state.
-                CS3_DIS: u1,
-                ///  SPI CS4 pin enable, 1: disable CS4, 0: spi_cs4 signal is from/to CS4 pin. Can be configured in CONF state.
-                CS4_DIS: u1,
-                ///  SPI CS5 pin enable, 1: disable CS5, 0: spi_cs5 signal is from/to CS5 pin. Can be configured in CONF state.
-                CS5_DIS: u1,
-                ///  1: spi clk out disable, 0: spi clk out enable. Can be configured in CONF state.
-                CK_DIS: u1,
-                ///  In the master mode the bits are the polarity of spi cs line, the value is equivalent to spi_cs ^ spi_master_cs_pol. Can be configured in CONF state.
-                MASTER_CS_POL: u6,
-                reserved23: u10,
-                ///  spi slave input cs polarity select. 1: inv 0: not change. Can be configured in CONF state.
-                SLAVE_CS_POL: u1,
-                reserved29: u5,
-                ///  1: spi clk line is high when idle 0: spi clk line is low when idle. Can be configured in CONF state.
-                CK_IDLE_EDGE: u1,
-                ///  spi cs line keep low when the bit is set. Can be configured in CONF state.
-                CS_KEEP_ACTIVE: u1,
-                ///  1: spi quad input swap enable 0: spi quad input swap disable. Can be configured in CONF state.
-                QUAD_DIN_PIN_SWAP: u1,
-            }),
-            ///  SPI input delay mode configuration
-            DIN_MODE: mmio.Mmio(packed struct(u32) {
-                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-                DIN0_MODE: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-                DIN1_MODE: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-                DIN2_MODE: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: input without delayed, 1: input with the posedge of clk_apb,2 input with the negedge of clk_apb, 3: input with the spi_clk. Can be configured in CONF state.
-                DIN3_MODE: u2,
-                reserved16: u8,
-                ///  1:enable hclk in SPI input timing module. 0: disable it. Can be configured in CONF state.
-                TIMING_HCLK_ACTIVE: u1,
-                padding: u15,
-            }),
-            ///  SPI input delay number configuration
-            DIN_NUM: mmio.Mmio(packed struct(u32) {
-                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
-                DIN0_NUM: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
-                DIN1_NUM: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
-                DIN2_NUM: u2,
-                ///  the input signals are delayed by SPI module clock cycles, 0: delayed by 1 cycle, 1: delayed by 2 cycles,... Can be configured in CONF state.
-                DIN3_NUM: u2,
-                padding: u24,
-            }),
-            ///  SPI output delay mode configuration
-            DOUT_MODE: mmio.Mmio(packed struct(u32) {
-                ///  The output signal 0 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
-                DOUT0_MODE: u1,
-                ///  The output signal 1 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
-                DOUT1_MODE: u1,
-                ///  The output signal 2 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
-                DOUT2_MODE: u1,
-                ///  The output signal 3 is delayed by the SPI module clock, 0: output without delayed, 1: output delay for a SPI module clock cycle at its negative edge. Can be configured in CONF state.
-                DOUT3_MODE: u1,
-                padding: u28,
-            }),
-            ///  SPI DMA control register
-            DMA_CONF: mmio.Mmio(packed struct(u32) {
-                reserved18: u18,
-                ///  Enable dma segment transfer in spi dma half slave mode. 1: enable. 0: disable.
-                DMA_SLV_SEG_TRANS_EN: u1,
-                ///  1: spi_dma_infifo_full_vld is cleared by spi slave cmd 5. 0: spi_dma_infifo_full_vld is cleared by spi_trans_done.
-                SLV_RX_SEG_TRANS_CLR_EN: u1,
-                ///  1: spi_dma_outfifo_empty_vld is cleared by spi slave cmd 6. 0: spi_dma_outfifo_empty_vld is cleared by spi_trans_done.
-                SLV_TX_SEG_TRANS_CLR_EN: u1,
-                ///  1: spi_dma_inlink_eof is set when the number of dma pushed data bytes is equal to the value of spi_slv/mst_dma_rd_bytelen[19:0] in spi dma transition. 0: spi_dma_inlink_eof is set by spi_trans_done in non-seg-trans or spi_dma_seg_trans_done in seg-trans.
-                RX_EOF_EN: u1,
-                reserved27: u5,
-                ///  Set this bit to enable SPI DMA controlled receive data mode.
-                DMA_RX_ENA: u1,
-                ///  Set this bit to enable SPI DMA controlled send data mode.
-                DMA_TX_ENA: u1,
-                ///  Set this bit to reset RX AFIFO, which is used to receive data in SPI master and slave mode transfer.
-                RX_AFIFO_RST: u1,
-                ///  Set this bit to reset BUF TX AFIFO, which is used send data out in SPI slave CPU controlled mode transfer and master mode transfer.
-                BUF_AFIFO_RST: u1,
-                ///  Set this bit to reset DMA TX AFIFO, which is used to send data out in SPI slave DMA controlled mode transfer.
-                DMA_AFIFO_RST: u1,
-            }),
-            ///  SPI DMA interrupt enable register
-            DMA_INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The enable bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-                DMA_INFIFO_FULL_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-                DMA_OUTFIFO_EMPTY_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI slave Ex_QPI interrupt.
-                SLV_EX_QPI_INT_ENA: u1,
-                ///  The enable bit for SPI slave En_QPI interrupt.
-                SLV_EN_QPI_INT_ENA: u1,
-                ///  The enable bit for SPI slave CMD7 interrupt.
-                SLV_CMD7_INT_ENA: u1,
-                ///  The enable bit for SPI slave CMD8 interrupt.
-                SLV_CMD8_INT_ENA: u1,
-                ///  The enable bit for SPI slave CMD9 interrupt.
-                SLV_CMD9_INT_ENA: u1,
-                ///  The enable bit for SPI slave CMDA interrupt.
-                SLV_CMDA_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-                SLV_RD_DMA_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-                SLV_WR_DMA_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-                SLV_RD_BUF_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-                SLV_WR_BUF_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_TRANS_DONE_INT interrupt.
-                TRANS_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-                DMA_SEG_TRANS_DONE_INT_ENA: u1,
-                ///  The enable bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-                SEG_MAGIC_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-                SLV_BUF_ADDR_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_SLV_CMD_ERR_INT interrupt.
-                SLV_CMD_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-                MST_RX_AFIFO_WFULL_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-                MST_TX_AFIFO_REMPTY_ERR_INT_ENA: u1,
-                ///  The enable bit for SPI_APP2_INT interrupt.
-                APP2_INT_ENA: u1,
-                ///  The enable bit for SPI_APP1_INT interrupt.
-                APP1_INT_ENA: u1,
-                padding: u11,
-            }),
-            ///  SPI DMA interrupt clear register
-            DMA_INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  The clear bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-                DMA_INFIFO_FULL_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-                DMA_OUTFIFO_EMPTY_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI slave Ex_QPI interrupt.
-                SLV_EX_QPI_INT_CLR: u1,
-                ///  The clear bit for SPI slave En_QPI interrupt.
-                SLV_EN_QPI_INT_CLR: u1,
-                ///  The clear bit for SPI slave CMD7 interrupt.
-                SLV_CMD7_INT_CLR: u1,
-                ///  The clear bit for SPI slave CMD8 interrupt.
-                SLV_CMD8_INT_CLR: u1,
-                ///  The clear bit for SPI slave CMD9 interrupt.
-                SLV_CMD9_INT_CLR: u1,
-                ///  The clear bit for SPI slave CMDA interrupt.
-                SLV_CMDA_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-                SLV_RD_DMA_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-                SLV_WR_DMA_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-                SLV_RD_BUF_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-                SLV_WR_BUF_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_TRANS_DONE_INT interrupt.
-                TRANS_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-                DMA_SEG_TRANS_DONE_INT_CLR: u1,
-                ///  The clear bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-                SEG_MAGIC_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-                SLV_BUF_ADDR_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_SLV_CMD_ERR_INT interrupt.
-                SLV_CMD_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-                MST_RX_AFIFO_WFULL_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-                MST_TX_AFIFO_REMPTY_ERR_INT_CLR: u1,
-                ///  The clear bit for SPI_APP2_INT interrupt.
-                APP2_INT_CLR: u1,
-                ///  The clear bit for SPI_APP1_INT interrupt.
-                APP1_INT_CLR: u1,
-                padding: u11,
-            }),
-            ///  SPI DMA interrupt raw register
-            DMA_INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  1: The current data rate of DMA Rx is smaller than that of SPI, which will lose the receive data. 0: Others.
-                DMA_INFIFO_FULL_ERR_INT_RAW: u1,
-                ///  1: The current data rate of DMA TX is smaller than that of SPI. SPI will stop in master mode and send out all 0 in slave mode. 0: Others.
-                DMA_OUTFIFO_EMPTY_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI slave Ex_QPI interrupt. 1: SPI slave mode Ex_QPI transmission is ended. 0: Others.
-                SLV_EX_QPI_INT_RAW: u1,
-                ///  The raw bit for SPI slave En_QPI interrupt. 1: SPI slave mode En_QPI transmission is ended. 0: Others.
-                SLV_EN_QPI_INT_RAW: u1,
-                ///  The raw bit for SPI slave CMD7 interrupt. 1: SPI slave mode CMD7 transmission is ended. 0: Others.
-                SLV_CMD7_INT_RAW: u1,
-                ///  The raw bit for SPI slave CMD8 interrupt. 1: SPI slave mode CMD8 transmission is ended. 0: Others.
-                SLV_CMD8_INT_RAW: u1,
-                ///  The raw bit for SPI slave CMD9 interrupt. 1: SPI slave mode CMD9 transmission is ended. 0: Others.
-                SLV_CMD9_INT_RAW: u1,
-                ///  The raw bit for SPI slave CMDA interrupt. 1: SPI slave mode CMDA transmission is ended. 0: Others.
-                SLV_CMDA_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_RD_DMA_DONE_INT interrupt. 1: SPI slave mode Rd_DMA transmission is ended. 0: Others.
-                SLV_RD_DMA_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_WR_DMA_DONE_INT interrupt. 1: SPI slave mode Wr_DMA transmission is ended. 0: Others.
-                SLV_WR_DMA_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_RD_BUF_DONE_INT interrupt. 1: SPI slave mode Rd_BUF transmission is ended. 0: Others.
-                SLV_RD_BUF_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_WR_BUF_DONE_INT interrupt. 1: SPI slave mode Wr_BUF transmission is ended. 0: Others.
-                SLV_WR_BUF_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_TRANS_DONE_INT interrupt. 1: SPI master mode transmission is ended. 0: others.
-                TRANS_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt. 1: spi master DMA full-duplex/half-duplex seg-conf-trans ends or slave half-duplex seg-trans ends. And data has been pushed to corresponding memory. 0: seg-conf-trans or seg-trans is not ended or not occurred.
-                DMA_SEG_TRANS_DONE_INT_RAW: u1,
-                ///  The raw bit for SPI_SEG_MAGIC_ERR_INT interrupt. 1: The magic value in CONF buffer is error in the DMA seg-conf-trans. 0: others.
-                SEG_MAGIC_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt. 1: The accessing data address of the current SPI slave mode CPU controlled FD, Wr_BUF or Rd_BUF transmission is bigger than 63. 0: Others.
-                SLV_BUF_ADDR_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI_SLV_CMD_ERR_INT interrupt. 1: The slave command value in the current SPI slave HD mode transmission is not supported. 0: Others.
-                SLV_CMD_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt. 1: There is a RX AFIFO write-full error when SPI inputs data in master mode. 0: Others.
-                MST_RX_AFIFO_WFULL_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt. 1: There is a TX BUF AFIFO read-empty error when SPI outputs data in master mode. 0: Others.
-                MST_TX_AFIFO_REMPTY_ERR_INT_RAW: u1,
-                ///  The raw bit for SPI_APP2_INT interrupt. The value is only controlled by application.
-                APP2_INT_RAW: u1,
-                ///  The raw bit for SPI_APP1_INT interrupt. The value is only controlled by application.
-                APP1_INT_RAW: u1,
-                padding: u11,
-            }),
-            ///  SPI DMA interrupt status register
-            DMA_INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The status bit for SPI_DMA_INFIFO_FULL_ERR_INT interrupt.
-                DMA_INFIFO_FULL_ERR_INT_ST: u1,
-                ///  The status bit for SPI_DMA_OUTFIFO_EMPTY_ERR_INT interrupt.
-                DMA_OUTFIFO_EMPTY_ERR_INT_ST: u1,
-                ///  The status bit for SPI slave Ex_QPI interrupt.
-                SLV_EX_QPI_INT_ST: u1,
-                ///  The status bit for SPI slave En_QPI interrupt.
-                SLV_EN_QPI_INT_ST: u1,
-                ///  The status bit for SPI slave CMD7 interrupt.
-                SLV_CMD7_INT_ST: u1,
-                ///  The status bit for SPI slave CMD8 interrupt.
-                SLV_CMD8_INT_ST: u1,
-                ///  The status bit for SPI slave CMD9 interrupt.
-                SLV_CMD9_INT_ST: u1,
-                ///  The status bit for SPI slave CMDA interrupt.
-                SLV_CMDA_INT_ST: u1,
-                ///  The status bit for SPI_SLV_RD_DMA_DONE_INT interrupt.
-                SLV_RD_DMA_DONE_INT_ST: u1,
-                ///  The status bit for SPI_SLV_WR_DMA_DONE_INT interrupt.
-                SLV_WR_DMA_DONE_INT_ST: u1,
-                ///  The status bit for SPI_SLV_RD_BUF_DONE_INT interrupt.
-                SLV_RD_BUF_DONE_INT_ST: u1,
-                ///  The status bit for SPI_SLV_WR_BUF_DONE_INT interrupt.
-                SLV_WR_BUF_DONE_INT_ST: u1,
-                ///  The status bit for SPI_TRANS_DONE_INT interrupt.
-                TRANS_DONE_INT_ST: u1,
-                ///  The status bit for SPI_DMA_SEG_TRANS_DONE_INT interrupt.
-                DMA_SEG_TRANS_DONE_INT_ST: u1,
-                ///  The status bit for SPI_SEG_MAGIC_ERR_INT interrupt.
-                SEG_MAGIC_ERR_INT_ST: u1,
-                ///  The status bit for SPI_SLV_BUF_ADDR_ERR_INT interrupt.
-                SLV_BUF_ADDR_ERR_INT_ST: u1,
-                ///  The status bit for SPI_SLV_CMD_ERR_INT interrupt.
-                SLV_CMD_ERR_INT_ST: u1,
-                ///  The status bit for SPI_MST_RX_AFIFO_WFULL_ERR_INT interrupt.
-                MST_RX_AFIFO_WFULL_ERR_INT_ST: u1,
-                ///  The status bit for SPI_MST_TX_AFIFO_REMPTY_ERR_INT interrupt.
-                MST_TX_AFIFO_REMPTY_ERR_INT_ST: u1,
-                ///  The status bit for SPI_APP2_INT interrupt.
-                APP2_INT_ST: u1,
-                ///  The status bit for SPI_APP1_INT interrupt.
-                APP1_INT_ST: u1,
-                padding: u11,
-            }),
-            reserved152: [84]u8,
-            ///  SPI CPU-controlled buffer0
-            W0: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF0: u32,
-            }),
-            ///  SPI CPU-controlled buffer1
-            W1: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF1: u32,
-            }),
-            ///  SPI CPU-controlled buffer2
-            W2: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF2: u32,
-            }),
-            ///  SPI CPU-controlled buffer3
-            W3: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF3: u32,
-            }),
-            ///  SPI CPU-controlled buffer4
-            W4: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF4: u32,
-            }),
-            ///  SPI CPU-controlled buffer5
-            W5: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF5: u32,
-            }),
-            ///  SPI CPU-controlled buffer6
-            W6: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF6: u32,
-            }),
-            ///  SPI CPU-controlled buffer7
-            W7: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF7: u32,
-            }),
-            ///  SPI CPU-controlled buffer8
-            W8: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF8: u32,
-            }),
-            ///  SPI CPU-controlled buffer9
-            W9: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF9: u32,
-            }),
-            ///  SPI CPU-controlled buffer10
-            W10: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF10: u32,
-            }),
-            ///  SPI CPU-controlled buffer11
-            W11: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF11: u32,
-            }),
-            ///  SPI CPU-controlled buffer12
-            W12: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF12: u32,
-            }),
-            ///  SPI CPU-controlled buffer13
-            W13: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF13: u32,
-            }),
-            ///  SPI CPU-controlled buffer14
-            W14: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF14: u32,
-            }),
-            ///  SPI CPU-controlled buffer15
-            W15: mmio.Mmio(packed struct(u32) {
-                ///  data buffer
-                BUF15: u32,
-            }),
-            reserved224: [8]u8,
-            ///  SPI slave control register
-            SLAVE: mmio.Mmio(packed struct(u32) {
-                ///  SPI clock mode bits. 0: SPI clock is off when CS inactive 1: SPI clock is delayed one cycle after CS inactive 2: SPI clock is delayed two cycles after CS inactive 3: SPI clock is alwasy on. Can be configured in CONF state.
-                CLK_MODE: u2,
-                ///  {CPOL, CPHA},1: support spi clk mode 1 and 3, first edge output data B[0]/B[7]. 0: support spi clk mode 0 and 2, first edge output data B[1]/B[6].
-                CLK_MODE_13: u1,
-                ///  It saves half a cycle when tsck is the same as rsck. 1: output data at rsck posedge 0: output data at tsck posedge
-                RSCK_DATA_OUT: u1,
-                reserved8: u4,
-                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in DMA controlled mode(Rd_DMA). 0: others
-                SLV_RDDMA_BITLEN_EN: u1,
-                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in DMA controlled mode(Wr_DMA). 0: others
-                SLV_WRDMA_BITLEN_EN: u1,
-                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-read-slave data length in CPU controlled mode(Rd_BUF). 0: others
-                SLV_RDBUF_BITLEN_EN: u1,
-                ///  1: SPI_SLV_DATA_BITLEN stores data bit length of master-write-to-slave data length in CPU controlled mode(Wr_BUF). 0: others
-                SLV_WRBUF_BITLEN_EN: u1,
-                reserved22: u10,
-                ///  The magic value of BM table in master DMA seg-trans.
-                DMA_SEG_MAGIC_VALUE: u4,
-                ///  Set SPI work mode. 1: slave mode 0: master mode.
-                MODE: u1,
-                ///  Software reset enable, reset the spi clock line cs line and data lines. Can be configured in CONF state.
-                SOFT_RESET: u1,
-                ///  1: Enable the DMA CONF phase of current seg-trans operation, which means seg-trans will start. 0: This is not seg-trans mode.
-                USR_CONF: u1,
-                padding: u3,
-            }),
-            ///  SPI slave control register 1
-            SLAVE1: mmio.Mmio(packed struct(u32) {
-                ///  The transferred data bit length in SPI slave FD and HD mode.
-                SLV_DATA_BITLEN: u18,
-                ///  In the slave mode it is the value of command.
-                SLV_LAST_COMMAND: u8,
-                ///  In the slave mode it is the value of address.
-                SLV_LAST_ADDR: u6,
-            }),
-            ///  SPI module clock and register clock control
-            CLK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to enable clk gate
-                CLK_EN: u1,
-                ///  Set this bit to power on the SPI module clock.
-                MST_CLK_ACTIVE: u1,
-                ///  This bit is used to select SPI module clock source in master mode. 1: PLL_CLK_80M. 0: XTAL CLK.
-                MST_CLK_SEL: u1,
-                padding: u29,
-            }),
-            reserved240: [4]u8,
-            ///  Version control
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  SPI register version.
-                DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  System
-        pub const SYSTEM = extern struct {
-            ///  cpu_peripheral clock gating register
-            CPU_PERI_CLK_EN: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  reg_clk_en_assist_debug
-                CLK_EN_ASSIST_DEBUG: u1,
-                ///  reg_clk_en_dedicated_gpio
-                CLK_EN_DEDICATED_GPIO: u1,
-                padding: u24,
-            }),
-            ///  cpu_peripheral reset register
-            CPU_PERI_RST_EN: mmio.Mmio(packed struct(u32) {
-                reserved6: u6,
-                ///  reg_rst_en_assist_debug
-                RST_EN_ASSIST_DEBUG: u1,
-                ///  reg_rst_en_dedicated_gpio
-                RST_EN_DEDICATED_GPIO: u1,
-                padding: u24,
-            }),
-            ///  cpu clock config register
-            CPU_PER_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_cpuperiod_sel
-                CPUPERIOD_SEL: u2,
-                ///  reg_pll_freq_sel
-                PLL_FREQ_SEL: u1,
-                ///  reg_cpu_wait_mode_force_on
-                CPU_WAIT_MODE_FORCE_ON: u1,
-                ///  reg_cpu_waiti_delay_num
-                CPU_WAITI_DELAY_NUM: u4,
-                padding: u24,
-            }),
-            ///  memory power down mask register
-            MEM_PD_MASK: mmio.Mmio(packed struct(u32) {
-                ///  reg_lslp_mem_pd_mask
-                LSLP_MEM_PD_MASK: u1,
-                padding: u31,
-            }),
-            ///  peripheral clock gating register
-            PERIP_CLK_EN0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timers_clk_en
-                TIMERS_CLK_EN: u1,
-                ///  reg_spi01_clk_en
-                SPI01_CLK_EN: u1,
-                ///  reg_uart_clk_en
-                UART_CLK_EN: u1,
-                ///  reg_wdg_clk_en
-                WDG_CLK_EN: u1,
-                ///  reg_i2s0_clk_en
-                I2S0_CLK_EN: u1,
-                ///  reg_uart1_clk_en
-                UART1_CLK_EN: u1,
-                ///  reg_spi2_clk_en
-                SPI2_CLK_EN: u1,
-                ///  reg_ext0_clk_en
-                I2C_EXT0_CLK_EN: u1,
-                ///  reg_uhci0_clk_en
-                UHCI0_CLK_EN: u1,
-                ///  reg_rmt_clk_en
-                RMT_CLK_EN: u1,
-                ///  reg_pcnt_clk_en
-                PCNT_CLK_EN: u1,
-                ///  reg_ledc_clk_en
-                LEDC_CLK_EN: u1,
-                ///  reg_uhci1_clk_en
-                UHCI1_CLK_EN: u1,
-                ///  reg_timergroup_clk_en
-                TIMERGROUP_CLK_EN: u1,
-                ///  reg_efuse_clk_en
-                EFUSE_CLK_EN: u1,
-                ///  reg_timergroup1_clk_en
-                TIMERGROUP1_CLK_EN: u1,
-                ///  reg_spi3_clk_en
-                SPI3_CLK_EN: u1,
-                ///  reg_pwm0_clk_en
-                PWM0_CLK_EN: u1,
-                ///  reg_ext1_clk_en
-                EXT1_CLK_EN: u1,
-                ///  reg_can_clk_en
-                CAN_CLK_EN: u1,
-                ///  reg_pwm1_clk_en
-                PWM1_CLK_EN: u1,
-                ///  reg_i2s1_clk_en
-                I2S1_CLK_EN: u1,
-                ///  reg_spi2_dma_clk_en
-                SPI2_DMA_CLK_EN: u1,
-                ///  reg_usb_device_clk_en
-                USB_DEVICE_CLK_EN: u1,
-                ///  reg_uart_mem_clk_en
-                UART_MEM_CLK_EN: u1,
-                ///  reg_pwm2_clk_en
-                PWM2_CLK_EN: u1,
-                ///  reg_pwm3_clk_en
-                PWM3_CLK_EN: u1,
-                ///  reg_spi3_dma_clk_en
-                SPI3_DMA_CLK_EN: u1,
-                ///  reg_apb_saradc_clk_en
-                APB_SARADC_CLK_EN: u1,
-                ///  reg_systimer_clk_en
-                SYSTIMER_CLK_EN: u1,
-                ///  reg_adc2_arb_clk_en
-                ADC2_ARB_CLK_EN: u1,
-                ///  reg_spi4_clk_en
-                SPI4_CLK_EN: u1,
-            }),
-            ///  peripheral clock gating register
-            PERIP_CLK_EN1: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  reg_crypto_aes_clk_en
-                CRYPTO_AES_CLK_EN: u1,
-                ///  reg_crypto_sha_clk_en
-                CRYPTO_SHA_CLK_EN: u1,
-                ///  reg_crypto_rsa_clk_en
-                CRYPTO_RSA_CLK_EN: u1,
-                ///  reg_crypto_ds_clk_en
-                CRYPTO_DS_CLK_EN: u1,
-                ///  reg_crypto_hmac_clk_en
-                CRYPTO_HMAC_CLK_EN: u1,
-                ///  reg_dma_clk_en
-                DMA_CLK_EN: u1,
-                ///  reg_sdio_host_clk_en
-                SDIO_HOST_CLK_EN: u1,
-                ///  reg_lcd_cam_clk_en
-                LCD_CAM_CLK_EN: u1,
-                ///  reg_uart2_clk_en
-                UART2_CLK_EN: u1,
-                ///  reg_tsens_clk_en
-                TSENS_CLK_EN: u1,
-                padding: u21,
-            }),
-            ///  reserved
-            PERIP_RST_EN0: mmio.Mmio(packed struct(u32) {
-                ///  reg_timers_rst
-                TIMERS_RST: u1,
-                ///  reg_spi01_rst
-                SPI01_RST: u1,
-                ///  reg_uart_rst
-                UART_RST: u1,
-                ///  reg_wdg_rst
-                WDG_RST: u1,
-                ///  reg_i2s0_rst
-                I2S0_RST: u1,
-                ///  reg_uart1_rst
-                UART1_RST: u1,
-                ///  reg_spi2_rst
-                SPI2_RST: u1,
-                ///  reg_ext0_rst
-                I2C_EXT0_RST: u1,
-                ///  reg_uhci0_rst
-                UHCI0_RST: u1,
-                ///  reg_rmt_rst
-                RMT_RST: u1,
-                ///  reg_pcnt_rst
-                PCNT_RST: u1,
-                ///  reg_ledc_rst
-                LEDC_RST: u1,
-                ///  reg_uhci1_rst
-                UHCI1_RST: u1,
-                ///  reg_timergroup_rst
-                TIMERGROUP_RST: u1,
-                ///  reg_efuse_rst
-                EFUSE_RST: u1,
-                ///  reg_timergroup1_rst
-                TIMERGROUP1_RST: u1,
-                ///  reg_spi3_rst
-                SPI3_RST: u1,
-                ///  reg_pwm0_rst
-                PWM0_RST: u1,
-                ///  reg_ext1_rst
-                EXT1_RST: u1,
-                ///  reg_can_rst
-                CAN_RST: u1,
-                ///  reg_pwm1_rst
-                PWM1_RST: u1,
-                ///  reg_i2s1_rst
-                I2S1_RST: u1,
-                ///  reg_spi2_dma_rst
-                SPI2_DMA_RST: u1,
-                ///  reg_usb_device_rst
-                USB_DEVICE_RST: u1,
-                ///  reg_uart_mem_rst
-                UART_MEM_RST: u1,
-                ///  reg_pwm2_rst
-                PWM2_RST: u1,
-                ///  reg_pwm3_rst
-                PWM3_RST: u1,
-                ///  reg_spi3_dma_rst
-                SPI3_DMA_RST: u1,
-                ///  reg_apb_saradc_rst
-                APB_SARADC_RST: u1,
-                ///  reg_systimer_rst
-                SYSTIMER_RST: u1,
-                ///  reg_adc2_arb_rst
-                ADC2_ARB_RST: u1,
-                ///  reg_spi4_rst
-                SPI4_RST: u1,
-            }),
-            ///  peripheral reset register
-            PERIP_RST_EN1: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  reg_crypto_aes_rst
-                CRYPTO_AES_RST: u1,
-                ///  reg_crypto_sha_rst
-                CRYPTO_SHA_RST: u1,
-                ///  reg_crypto_rsa_rst
-                CRYPTO_RSA_RST: u1,
-                ///  reg_crypto_ds_rst
-                CRYPTO_DS_RST: u1,
-                ///  reg_crypto_hmac_rst
-                CRYPTO_HMAC_RST: u1,
-                ///  reg_dma_rst
-                DMA_RST: u1,
-                ///  reg_sdio_host_rst
-                SDIO_HOST_RST: u1,
-                ///  reg_lcd_cam_rst
-                LCD_CAM_RST: u1,
-                ///  reg_uart2_rst
-                UART2_RST: u1,
-                ///  reg_tsens_rst
-                TSENS_RST: u1,
-                padding: u21,
-            }),
-            ///  clock config register
-            BT_LPCK_DIV_INT: mmio.Mmio(packed struct(u32) {
-                ///  reg_bt_lpck_div_num
-                BT_LPCK_DIV_NUM: u12,
-                padding: u20,
-            }),
-            ///  clock config register
-            BT_LPCK_DIV_FRAC: mmio.Mmio(packed struct(u32) {
-                ///  reg_bt_lpck_div_b
-                BT_LPCK_DIV_B: u12,
-                ///  reg_bt_lpck_div_a
-                BT_LPCK_DIV_A: u12,
-                ///  reg_lpclk_sel_rtc_slow
-                LPCLK_SEL_RTC_SLOW: u1,
-                ///  reg_lpclk_sel_8m
-                LPCLK_SEL_8M: u1,
-                ///  reg_lpclk_sel_xtal
-                LPCLK_SEL_XTAL: u1,
-                ///  reg_lpclk_sel_xtal32k
-                LPCLK_SEL_XTAL32K: u1,
-                ///  reg_lpclk_rtc_en
-                LPCLK_RTC_EN: u1,
-                padding: u3,
-            }),
-            ///  interrupt generate register
-            CPU_INTR_FROM_CPU_0: mmio.Mmio(packed struct(u32) {
-                ///  reg_cpu_intr_from_cpu_0
-                CPU_INTR_FROM_CPU_0: u1,
-                padding: u31,
-            }),
-            ///  interrupt generate register
-            CPU_INTR_FROM_CPU_1: mmio.Mmio(packed struct(u32) {
-                ///  reg_cpu_intr_from_cpu_1
-                CPU_INTR_FROM_CPU_1: u1,
-                padding: u31,
-            }),
-            ///  interrupt generate register
-            CPU_INTR_FROM_CPU_2: mmio.Mmio(packed struct(u32) {
-                ///  reg_cpu_intr_from_cpu_2
-                CPU_INTR_FROM_CPU_2: u1,
-                padding: u31,
-            }),
-            ///  interrupt generate register
-            CPU_INTR_FROM_CPU_3: mmio.Mmio(packed struct(u32) {
-                ///  reg_cpu_intr_from_cpu_3
-                CPU_INTR_FROM_CPU_3: u1,
-                padding: u31,
-            }),
-            ///  rsa memory power control register
-            RSA_PD_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_rsa_mem_pd
-                RSA_MEM_PD: u1,
-                ///  reg_rsa_mem_force_pu
-                RSA_MEM_FORCE_PU: u1,
-                ///  reg_rsa_mem_force_pd
-                RSA_MEM_FORCE_PD: u1,
-                padding: u29,
-            }),
-            ///  edma clcok and reset register
-            EDMA_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_edma_clk_on
-                EDMA_CLK_ON: u1,
-                ///  reg_edma_reset
-                EDMA_RESET: u1,
-                padding: u30,
-            }),
-            ///  cache control register
-            CACHE_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  reg_icache_clk_on
-                ICACHE_CLK_ON: u1,
-                ///  reg_icache_reset
-                ICACHE_RESET: u1,
-                ///  reg_dcache_clk_on
-                DCACHE_CLK_ON: u1,
-                ///  reg_dcache_reset
-                DCACHE_RESET: u1,
-                padding: u28,
-            }),
-            ///  SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG
-            EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL: mmio.Mmio(packed struct(u32) {
-                ///  reg_enable_spi_manual_encrypt
-                ENABLE_SPI_MANUAL_ENCRYPT: u1,
-                ///  reg_enable_download_db_encrypt
-                ENABLE_DOWNLOAD_DB_ENCRYPT: u1,
-                ///  reg_enable_download_g0cb_decrypt
-                ENABLE_DOWNLOAD_G0CB_DECRYPT: u1,
-                ///  reg_enable_download_manual_encrypt
-                ENABLE_DOWNLOAD_MANUAL_ENCRYPT: u1,
-                padding: u28,
-            }),
-            ///  fast memory config register
-            RTC_FASTMEM_CONFIG: mmio.Mmio(packed struct(u32) {
-                reserved8: u8,
-                ///  reg_rtc_mem_crc_start
-                RTC_MEM_CRC_START: u1,
-                ///  reg_rtc_mem_crc_addr
-                RTC_MEM_CRC_ADDR: u11,
-                ///  reg_rtc_mem_crc_len
-                RTC_MEM_CRC_LEN: u11,
-                ///  reg_rtc_mem_crc_finish
-                RTC_MEM_CRC_FINISH: u1,
-            }),
-            ///  reserved
-            RTC_FASTMEM_CRC: mmio.Mmio(packed struct(u32) {
-                ///  reg_rtc_mem_crc_res
-                RTC_MEM_CRC_RES: u32,
-            }),
-            ///  eco register
-            REDUNDANT_ECO_CTRL: mmio.Mmio(packed struct(u32) {
-                ///  reg_redundant_eco_drive
-                REDUNDANT_ECO_DRIVE: u1,
-                ///  reg_redundant_eco_result
-                REDUNDANT_ECO_RESULT: u1,
-                padding: u30,
-            }),
-            ///  clock gating register
-            CLOCK_GATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_clk_en
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            ///  system clock config register
-            SYSCLK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_pre_div_cnt
-                PRE_DIV_CNT: u10,
-                ///  reg_soc_clk_sel
-                SOC_CLK_SEL: u2,
-                ///  reg_clk_xtal_freq
-                CLK_XTAL_FREQ: u7,
-                ///  reg_clk_div_en
-                CLK_DIV_EN: u1,
-                padding: u12,
-            }),
-            ///  mem pvt register
-            MEM_PVT: mmio.Mmio(packed struct(u32) {
-                ///  reg_mem_path_len
-                MEM_PATH_LEN: u4,
-                ///  reg_mem_err_cnt_clr
-                MEM_ERR_CNT_CLR: u1,
-                ///  reg_mem_pvt_monitor_en
-                MONITOR_EN: u1,
-                ///  reg_mem_timing_err_cnt
-                MEM_TIMING_ERR_CNT: u16,
-                ///  reg_mem_vt_sel
-                MEM_VT_SEL: u2,
-                padding: u8,
-            }),
-            ///  mem pvt register
-            COMB_PVT_LVT_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_path_len_lvt
-                COMB_PATH_LEN_LVT: u5,
-                ///  reg_comb_err_cnt_clr_lvt
-                COMB_ERR_CNT_CLR_LVT: u1,
-                ///  reg_comb_pvt_monitor_en_lvt
-                COMB_PVT_MONITOR_EN_LVT: u1,
-                padding: u25,
-            }),
-            ///  mem pvt register
-            COMB_PVT_NVT_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_path_len_nvt
-                COMB_PATH_LEN_NVT: u5,
-                ///  reg_comb_err_cnt_clr_nvt
-                COMB_ERR_CNT_CLR_NVT: u1,
-                ///  reg_comb_pvt_monitor_en_nvt
-                COMB_PVT_MONITOR_EN_NVT: u1,
-                padding: u25,
-            }),
-            ///  mem pvt register
-            COMB_PVT_HVT_CONF: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_path_len_hvt
-                COMB_PATH_LEN_HVT: u5,
-                ///  reg_comb_err_cnt_clr_hvt
-                COMB_ERR_CNT_CLR_HVT: u1,
-                ///  reg_comb_pvt_monitor_en_hvt
-                COMB_PVT_MONITOR_EN_HVT: u1,
-                padding: u25,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_LVT_SITE0: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_lvt_site0
-                COMB_TIMING_ERR_CNT_LVT_SITE0: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_NVT_SITE0: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_nvt_site0
-                COMB_TIMING_ERR_CNT_NVT_SITE0: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_HVT_SITE0: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_hvt_site0
-                COMB_TIMING_ERR_CNT_HVT_SITE0: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_LVT_SITE1: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_lvt_site1
-                COMB_TIMING_ERR_CNT_LVT_SITE1: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_NVT_SITE1: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_nvt_site1
-                COMB_TIMING_ERR_CNT_NVT_SITE1: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_HVT_SITE1: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_hvt_site1
-                COMB_TIMING_ERR_CNT_HVT_SITE1: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_LVT_SITE2: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_lvt_site2
-                COMB_TIMING_ERR_CNT_LVT_SITE2: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_NVT_SITE2: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_nvt_site2
-                COMB_TIMING_ERR_CNT_NVT_SITE2: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_HVT_SITE2: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_hvt_site2
-                COMB_TIMING_ERR_CNT_HVT_SITE2: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_LVT_SITE3: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_lvt_site3
-                COMB_TIMING_ERR_CNT_LVT_SITE3: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_NVT_SITE3: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_nvt_site3
-                COMB_TIMING_ERR_CNT_NVT_SITE3: u16,
-                padding: u16,
-            }),
-            ///  mem pvt register
-            COMB_PVT_ERR_HVT_SITE3: mmio.Mmio(packed struct(u32) {
-                ///  reg_comb_timing_err_cnt_hvt_site3
-                COMB_TIMING_ERR_CNT_HVT_SITE3: u16,
-                padding: u16,
-            }),
-            reserved4092: [3936]u8,
-            ///  Version register
-            SYSTEM_REG_DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_system_reg_date
-                SYSTEM_REG_DATE: u28,
-                padding: u4,
-            }),
-        };
-
-        ///  System Timer
-        pub const SYSTIMER = extern struct {
-            ///  SYSTIMER_CONF.
-            CONF: mmio.Mmio(packed struct(u32) {
-                ///  systimer clock force on
-                SYSTIMER_CLK_FO: u1,
-                reserved22: u21,
-                ///  target2 work enable
-                TARGET2_WORK_EN: u1,
-                ///  target1 work enable
-                TARGET1_WORK_EN: u1,
-                ///  target0 work enable
-                TARGET0_WORK_EN: u1,
-                ///  If timer unit1 is stalled when core1 stalled
-                TIMER_UNIT1_CORE1_STALL_EN: u1,
-                ///  If timer unit1 is stalled when core0 stalled
-                TIMER_UNIT1_CORE0_STALL_EN: u1,
-                ///  If timer unit0 is stalled when core1 stalled
-                TIMER_UNIT0_CORE1_STALL_EN: u1,
-                ///  If timer unit0 is stalled when core0 stalled
-                TIMER_UNIT0_CORE0_STALL_EN: u1,
-                ///  timer unit1 work enable
-                TIMER_UNIT1_WORK_EN: u1,
-                ///  timer unit0 work enable
-                TIMER_UNIT0_WORK_EN: u1,
-                ///  register file clk gating
-                CLK_EN: u1,
-            }),
-            ///  SYSTIMER_UNIT0_OP.
-            UNIT0_OP: mmio.Mmio(packed struct(u32) {
-                reserved29: u29,
-                ///  reg_timer_unit0_value_valid
-                TIMER_UNIT0_VALUE_VALID: u1,
-                ///  update timer_unit0
-                TIMER_UNIT0_UPDATE: u1,
-                padding: u1,
-            }),
-            ///  SYSTIMER_UNIT1_OP.
-            UNIT1_OP: mmio.Mmio(packed struct(u32) {
-                reserved29: u29,
-                ///  timer value is sync and valid
-                TIMER_UNIT1_VALUE_VALID: u1,
-                ///  update timer unit1
-                TIMER_UNIT1_UPDATE: u1,
-                padding: u1,
-            }),
-            ///  SYSTIMER_UNIT0_LOAD_HI.
-            UNIT0_LOAD_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer unit0 load high 32 bit
-                TIMER_UNIT0_LOAD_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_UNIT0_LOAD_LO.
-            UNIT0_LOAD_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer unit0 load low 32 bit
-                TIMER_UNIT0_LOAD_LO: u32,
-            }),
-            ///  SYSTIMER_UNIT1_LOAD_HI.
-            UNIT1_LOAD_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer unit1 load high 32 bit
-                TIMER_UNIT1_LOAD_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_UNIT1_LOAD_LO.
-            UNIT1_LOAD_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer unit1 load low 32 bit
-                TIMER_UNIT1_LOAD_LO: u32,
-            }),
-            ///  SYSTIMER_TARGET0_HI.
-            TARGET0_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer taget0 high 32 bit
-                TIMER_TARGET0_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_TARGET0_LO.
-            TARGET0_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer taget0 low 32 bit
-                TIMER_TARGET0_LO: u32,
-            }),
-            ///  SYSTIMER_TARGET1_HI.
-            TARGET1_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer taget1 high 32 bit
-                TIMER_TARGET1_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_TARGET1_LO.
-            TARGET1_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer taget1 low 32 bit
-                TIMER_TARGET1_LO: u32,
-            }),
-            ///  SYSTIMER_TARGET2_HI.
-            TARGET2_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer taget2 high 32 bit
-                TIMER_TARGET2_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_TARGET2_LO.
-            TARGET2_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer taget2 low 32 bit
-                TIMER_TARGET2_LO: u32,
-            }),
-            ///  SYSTIMER_TARGET0_CONF.
-            TARGET0_CONF: mmio.Mmio(packed struct(u32) {
-                ///  target0 period
-                TARGET0_PERIOD: u26,
-                reserved30: u4,
-                ///  Set target0 to period mode
-                TARGET0_PERIOD_MODE: u1,
-                ///  select which unit to compare
-                TARGET0_TIMER_UNIT_SEL: u1,
-            }),
-            ///  SYSTIMER_TARGET1_CONF.
-            TARGET1_CONF: mmio.Mmio(packed struct(u32) {
-                ///  target1 period
-                TARGET1_PERIOD: u26,
-                reserved30: u4,
-                ///  Set target1 to period mode
-                TARGET1_PERIOD_MODE: u1,
-                ///  select which unit to compare
-                TARGET1_TIMER_UNIT_SEL: u1,
-            }),
-            ///  SYSTIMER_TARGET2_CONF.
-            TARGET2_CONF: mmio.Mmio(packed struct(u32) {
-                ///  target2 period
-                TARGET2_PERIOD: u26,
-                reserved30: u4,
-                ///  Set target2 to period mode
-                TARGET2_PERIOD_MODE: u1,
-                ///  select which unit to compare
-                TARGET2_TIMER_UNIT_SEL: u1,
-            }),
-            ///  SYSTIMER_UNIT0_VALUE_HI.
-            UNIT0_VALUE_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer read value high 32bit
-                TIMER_UNIT0_VALUE_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_UNIT0_VALUE_LO.
-            UNIT0_VALUE_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer read value low 32bit
-                TIMER_UNIT0_VALUE_LO: u32,
-            }),
-            ///  SYSTIMER_UNIT1_VALUE_HI.
-            UNIT1_VALUE_HI: mmio.Mmio(packed struct(u32) {
-                ///  timer read value high 32bit
-                TIMER_UNIT1_VALUE_HI: u20,
-                padding: u12,
-            }),
-            ///  SYSTIMER_UNIT1_VALUE_LO.
-            UNIT1_VALUE_LO: mmio.Mmio(packed struct(u32) {
-                ///  timer read value low 32bit
-                TIMER_UNIT1_VALUE_LO: u32,
-            }),
-            ///  SYSTIMER_COMP0_LOAD.
-            COMP0_LOAD: mmio.Mmio(packed struct(u32) {
-                ///  timer comp0 load value
-                TIMER_COMP0_LOAD: u1,
-                padding: u31,
-            }),
-            ///  SYSTIMER_COMP1_LOAD.
-            COMP1_LOAD: mmio.Mmio(packed struct(u32) {
-                ///  timer comp1 load value
-                TIMER_COMP1_LOAD: u1,
-                padding: u31,
-            }),
-            ///  SYSTIMER_COMP2_LOAD.
-            COMP2_LOAD: mmio.Mmio(packed struct(u32) {
-                ///  timer comp2 load value
-                TIMER_COMP2_LOAD: u1,
-                padding: u31,
-            }),
-            ///  SYSTIMER_UNIT0_LOAD.
-            UNIT0_LOAD: mmio.Mmio(packed struct(u32) {
-                ///  timer unit0 load value
-                TIMER_UNIT0_LOAD: u1,
-                padding: u31,
-            }),
-            ///  SYSTIMER_UNIT1_LOAD.
-            UNIT1_LOAD: mmio.Mmio(packed struct(u32) {
-                ///  timer unit1 load value
-                TIMER_UNIT1_LOAD: u1,
-                padding: u31,
-            }),
-            ///  SYSTIMER_INT_ENA.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  interupt0 enable
-                TARGET0_INT_ENA: u1,
-                ///  interupt1 enable
-                TARGET1_INT_ENA: u1,
-                ///  interupt2 enable
-                TARGET2_INT_ENA: u1,
-                padding: u29,
-            }),
-            ///  SYSTIMER_INT_RAW.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  interupt0 raw
-                TARGET0_INT_RAW: u1,
-                ///  interupt1 raw
-                TARGET1_INT_RAW: u1,
-                ///  interupt2 raw
-                TARGET2_INT_RAW: u1,
-                padding: u29,
-            }),
-            ///  SYSTIMER_INT_CLR.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  interupt0 clear
-                TARGET0_INT_CLR: u1,
-                ///  interupt1 clear
-                TARGET1_INT_CLR: u1,
-                ///  interupt2 clear
-                TARGET2_INT_CLR: u1,
-                padding: u29,
-            }),
-            ///  SYSTIMER_INT_ST.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  reg_target0_int_st
-                TARGET0_INT_ST: u1,
-                ///  reg_target1_int_st
-                TARGET1_INT_ST: u1,
-                ///  reg_target2_int_st
-                TARGET2_INT_ST: u1,
-                padding: u29,
-            }),
-            reserved252: [136]u8,
-            ///  SYSTIMER_DATE.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_date
-                DATE: u32,
-            }),
-        };
-
-        ///  Timer Group
-        pub const TIMG0 = extern struct {
-            ///  TIMG_T0CONFIG_REG.
-            T0CONFIG: mmio.Mmio(packed struct(u32) {
-                reserved9: u9,
-                ///  reg_t0_use_xtal.
-                T0_USE_XTAL: u1,
-                ///  reg_t0_alarm_en.
-                T0_ALARM_EN: u1,
-                reserved12: u1,
-                ///  reg_t0_divcnt_rst.
-                T0_DIVCNT_RST: u1,
-                ///  reg_t0_divider.
-                T0_DIVIDER: u16,
-                ///  reg_t0_autoreload.
-                T0_AUTORELOAD: u1,
-                ///  reg_t0_increase.
-                T0_INCREASE: u1,
-                ///  reg_t0_en.
-                T0_EN: u1,
-            }),
-            ///  TIMG_T0LO_REG.
-            T0LO: mmio.Mmio(packed struct(u32) {
-                ///  t0_lo
-                T0_LO: u32,
-            }),
-            ///  TIMG_T0HI_REG.
-            T0HI: mmio.Mmio(packed struct(u32) {
-                ///  t0_hi
-                T0_HI: u22,
-                padding: u10,
-            }),
-            ///  TIMG_T0UPDATE_REG.
-            T0UPDATE: mmio.Mmio(packed struct(u32) {
-                reserved31: u31,
-                ///  t0_update
-                T0_UPDATE: u1,
-            }),
-            ///  TIMG_T0ALARMLO_REG.
-            T0ALARMLO: mmio.Mmio(packed struct(u32) {
-                ///  reg_t0_alarm_lo.
-                T0_ALARM_LO: u32,
-            }),
-            ///  TIMG_T0ALARMHI_REG.
-            T0ALARMHI: mmio.Mmio(packed struct(u32) {
-                ///  reg_t0_alarm_hi.
-                T0_ALARM_HI: u22,
-                padding: u10,
-            }),
-            ///  TIMG_T0LOADLO_REG.
-            T0LOADLO: mmio.Mmio(packed struct(u32) {
-                ///  reg_t0_load_lo.
-                T0_LOAD_LO: u32,
-            }),
-            ///  TIMG_T0LOADHI_REG.
-            T0LOADHI: mmio.Mmio(packed struct(u32) {
-                ///  reg_t0_load_hi.
-                T0_LOAD_HI: u22,
-                padding: u10,
-            }),
-            ///  TIMG_T0LOAD_REG.
-            T0LOAD: mmio.Mmio(packed struct(u32) {
-                ///  t0_load
-                T0_LOAD: u32,
-            }),
-            reserved72: [36]u8,
-            ///  TIMG_WDTCONFIG0_REG.
-            WDTCONFIG0: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  reg_wdt_appcpu_reset_en.
-                WDT_APPCPU_RESET_EN: u1,
-                ///  reg_wdt_procpu_reset_en.
-                WDT_PROCPU_RESET_EN: u1,
-                ///  reg_wdt_flashboot_mod_en.
-                WDT_FLASHBOOT_MOD_EN: u1,
-                ///  reg_wdt_sys_reset_length.
-                WDT_SYS_RESET_LENGTH: u3,
-                ///  reg_wdt_cpu_reset_length.
-                WDT_CPU_RESET_LENGTH: u3,
-                ///  reg_wdt_use_xtal.
-                WDT_USE_XTAL: u1,
-                ///  reg_wdt_conf_update_en.
-                WDT_CONF_UPDATE_EN: u1,
-                ///  reg_wdt_stg3.
-                WDT_STG3: u2,
-                ///  reg_wdt_stg2.
-                WDT_STG2: u2,
-                ///  reg_wdt_stg1.
-                WDT_STG1: u2,
-                ///  reg_wdt_stg0.
-                WDT_STG0: u2,
-                ///  reg_wdt_en.
-                WDT_EN: u1,
-            }),
-            ///  TIMG_WDTCONFIG1_REG.
-            WDTCONFIG1: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_divcnt_rst.
-                WDT_DIVCNT_RST: u1,
-                reserved16: u15,
-                ///  reg_wdt_clk_prescale.
-                WDT_CLK_PRESCALE: u16,
-            }),
-            ///  TIMG_WDTCONFIG2_REG.
-            WDTCONFIG2: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_stg0_hold.
-                WDT_STG0_HOLD: u32,
-            }),
-            ///  TIMG_WDTCONFIG3_REG.
-            WDTCONFIG3: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_stg1_hold.
-                WDT_STG1_HOLD: u32,
-            }),
-            ///  TIMG_WDTCONFIG4_REG.
-            WDTCONFIG4: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_stg2_hold.
-                WDT_STG2_HOLD: u32,
-            }),
-            ///  TIMG_WDTCONFIG5_REG.
-            WDTCONFIG5: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_stg3_hold.
-                WDT_STG3_HOLD: u32,
-            }),
-            ///  TIMG_WDTFEED_REG.
-            WDTFEED: mmio.Mmio(packed struct(u32) {
-                ///  wdt_feed
-                WDT_FEED: u32,
-            }),
-            ///  TIMG_WDTWPROTECT_REG.
-            WDTWPROTECT: mmio.Mmio(packed struct(u32) {
-                ///  reg_wdt_wkey.
-                WDT_WKEY: u32,
-            }),
-            ///  TIMG_RTCCALICFG_REG.
-            RTCCALICFG: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  reg_rtc_cali_start_cycling.
-                RTC_CALI_START_CYCLING: u1,
-                ///  reg_rtc_cali_clk_sel.0:rtcslowclock.1:clk_80m.2:xtal_32k
-                RTC_CALI_CLK_SEL: u2,
-                ///  rtc_cali_rdy
-                RTC_CALI_RDY: u1,
-                ///  reg_rtc_cali_max.
-                RTC_CALI_MAX: u15,
-                ///  reg_rtc_cali_start.
-                RTC_CALI_START: u1,
-            }),
-            ///  TIMG_RTCCALICFG1_REG.
-            RTCCALICFG1: mmio.Mmio(packed struct(u32) {
-                ///  rtc_cali_cycling_data_vld
-                RTC_CALI_CYCLING_DATA_VLD: u1,
-                reserved7: u6,
-                ///  rtc_cali_value
-                RTC_CALI_VALUE: u25,
-            }),
-            ///  INT_ENA_TIMG_REG
-            INT_ENA_TIMERS: mmio.Mmio(packed struct(u32) {
-                ///  t0_int_ena
-                T0_INT_ENA: u1,
-                ///  wdt_int_ena
-                WDT_INT_ENA: u1,
-                padding: u30,
-            }),
-            ///  INT_RAW_TIMG_REG
-            INT_RAW_TIMERS: mmio.Mmio(packed struct(u32) {
-                ///  t0_int_raw
-                T0_INT_RAW: u1,
-                ///  wdt_int_raw
-                WDT_INT_RAW: u1,
-                padding: u30,
-            }),
-            ///  INT_ST_TIMG_REG
-            INT_ST_TIMERS: mmio.Mmio(packed struct(u32) {
-                ///  t0_int_st
-                T0_INT_ST: u1,
-                ///  wdt_int_st
-                WDT_INT_ST: u1,
-                padding: u30,
-            }),
-            ///  INT_CLR_TIMG_REG
-            INT_CLR_TIMERS: mmio.Mmio(packed struct(u32) {
-                ///  t0_int_clr
-                T0_INT_CLR: u1,
-                ///  wdt_int_clr
-                WDT_INT_CLR: u1,
-                padding: u30,
-            }),
-            ///  TIMG_RTCCALICFG2_REG.
-            RTCCALICFG2: mmio.Mmio(packed struct(u32) {
-                ///  timeoutindicator
-                RTC_CALI_TIMEOUT: u1,
-                reserved3: u2,
-                ///  reg_rtc_cali_timeout_rst_cnt.Cyclesthatreleasecalibrationtimeoutreset
-                RTC_CALI_TIMEOUT_RST_CNT: u4,
-                ///  reg_rtc_cali_timeout_thres.timeoutifcalivaluecountsoverthreshold
-                RTC_CALI_TIMEOUT_THRES: u25,
-            }),
-            reserved248: [116]u8,
-            ///  TIMG_NTIMG_DATE_REG.
-            NTIMG_DATE: mmio.Mmio(packed struct(u32) {
-                ///  reg_ntimers_date.
-                NTIMGS_DATE: u28,
-                padding: u4,
-            }),
-            ///  TIMG_REGCLK_REG.
-            REGCLK: mmio.Mmio(packed struct(u32) {
-                reserved29: u29,
-                ///  reg_wdt_clk_is_active.
-                WDT_CLK_IS_ACTIVE: u1,
-                ///  reg_timer_clk_is_active.
-                TIMER_CLK_IS_ACTIVE: u1,
-                ///  reg_clk_en.
-                CLK_EN: u1,
-            }),
-        };
-
-        ///  XTS-AES-128 Flash Encryption
-        pub const XTS_AES = extern struct {
-            ///  The memory that stores plaintext
-            PLAIN_MEM: [16]u8,
-            reserved64: [48]u8,
-            ///  XTS-AES line-size register
-            LINESIZE: mmio.Mmio(packed struct(u32) {
-                ///  This bit stores the line size parameter. 0: 16Byte, 1: 32Byte.
-                LINESIZE: u1,
-                padding: u31,
-            }),
-            ///  XTS-AES destination register
-            DESTINATION: mmio.Mmio(packed struct(u32) {
-                ///  This bit stores the destination. 0: flash(default). 1: reserved.
-                DESTINATION: u1,
-                padding: u31,
-            }),
-            ///  XTS-AES physical address register
-            PHYSICAL_ADDRESS: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores the physical address. If linesize is 16-byte, the physical address should be aligned of 16 bytes. If linesize is 32-byte, the physical address should be aligned of 32 bytes.
-                PHYSICAL_ADDRESS: u30,
-                padding: u2,
-            }),
-            ///  XTS-AES trigger register
-            TRIGGER: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to start manual encryption calculation
-                TRIGGER: u1,
-                padding: u31,
-            }),
-            ///  XTS-AES release register
-            RELEASE: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to release the manual encrypted result, after that the result will be visible to spi
-                RELEASE: u1,
-                padding: u31,
-            }),
-            ///  XTS-AES destroy register
-            DESTROY: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to destroy XTS-AES result.
-                DESTROY: u1,
-                padding: u31,
-            }),
-            ///  XTS-AES status register
-            STATE: mmio.Mmio(packed struct(u32) {
-                ///  Those bits shows XTS-AES status. 0=IDLE, 1=WORK, 2=RELEASE, 3=USE. IDLE means that XTS-AES is idle. WORK means that XTS-AES is busy with calculation. RELEASE means the encrypted result is generated but not visible to mspi. USE means that the encrypted result is visible to mspi.
-                STATE: u2,
-                padding: u30,
-            }),
-            ///  XTS-AES version control register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  Those bits stores the version information of XTS-AES.
-                DATE: u30,
-                padding: u2,
-            }),
-        };
-
-        ///  Two-Wire Automotive Interface
-        pub const TWAI = extern struct {
-            ///  Mode Register
-            MODE: mmio.Mmio(packed struct(u32) {
-                ///  This bit is used to configure the operating mode of the TWAI Controller. 1: Reset mode; 0: Operating mode.
-                RESET_MODE: u1,
-                ///  1: Listen only mode. In this mode the nodes will only receive messages from the bus, without generating the acknowledge signal nor updating the RX error counter.
-                LISTEN_ONLY_MODE: u1,
-                ///  1: Self test mode. In this mode the TX nodes can perform a successful transmission without receiving the acknowledge signal. This mode is often used to test a single node with the self reception request command.
-                SELF_TEST_MODE: u1,
-                ///  This bit is used to configure the filter mode. 0: Dual filter mode; 1: Single filter mode.
-                RX_FILTER_MODE: u1,
-                padding: u28,
-            }),
-            ///  Command Register
-            CMD: mmio.Mmio(packed struct(u32) {
-                ///  Set the bit to 1 to allow the driving nodes start transmission.
-                TX_REQ: u1,
-                ///  Set the bit to 1 to cancel a pending transmission request.
-                ABORT_TX: u1,
-                ///  Set the bit to 1 to release the RX buffer.
-                RELEASE_BUF: u1,
-                ///  Set the bit to 1 to clear the data overrun status bit.
-                CLR_OVERRUN: u1,
-                ///  Self reception request command. Set the bit to 1 to allow a message be transmitted and received simultaneously.
-                SELF_RX_REQ: u1,
-                padding: u27,
-            }),
-            ///  Status register
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  1: The data in the RX buffer is not empty, with at least one received data packet.
-                RX_BUF_ST: u1,
-                ///  1: The RX FIFO is full and data overrun has occurred.
-                OVERRUN_ST: u1,
-                ///  1: The TX buffer is empty, the CPU may write a message into it.
-                TX_BUF_ST: u1,
-                ///  1: The TWAI controller has successfully received a packet from the bus.
-                TX_COMPLETE: u1,
-                ///  1: The TWAI Controller is receiving a message from the bus.
-                RX_ST: u1,
-                ///  1: The TWAI Controller is transmitting a message to the bus.
-                TX_ST: u1,
-                ///  1: At least one of the RX/TX error counter has reached or exceeded the value set in register TWAI_ERR_WARNING_LIMIT_REG.
-                ERR_ST: u1,
-                ///  1: In bus-off status, the TWAI Controller is no longer involved in bus activities.
-                BUS_OFF_ST: u1,
-                ///  This bit reflects whether the data packet in the RX FIFO is complete. 1: The current packet is missing; 0: The current packet is complete
-                MISS_ST: u1,
-                padding: u23,
-            }),
-            ///  Interrupt Register
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  Receive interrupt. If this bit is set to 1, it indicates there are messages to be handled in the RX FIFO.
-                RX_INT_ST: u1,
-                ///  Transmit interrupt. If this bit is set to 1, it indicates the message transmitting mis- sion is finished and a new transmission is able to execute.
-                TX_INT_ST: u1,
-                ///  Error warning interrupt. If this bit is set to 1, it indicates the error status signal and the bus-off status signal of Status register have changed (e.g., switched from 0 to 1 or from 1 to 0).
-                ERR_WARN_INT_ST: u1,
-                ///  Data overrun interrupt. If this bit is set to 1, it indicates a data overrun interrupt is generated in the RX FIFO.
-                OVERRUN_INT_ST: u1,
-                reserved5: u1,
-                ///  Error passive interrupt. If this bit is set to 1, it indicates the TWAI Controller is switched between error active status and error passive status due to the change of error counters.
-                ERR_PASSIVE_INT_ST: u1,
-                ///  Arbitration lost interrupt. If this bit is set to 1, it indicates an arbitration lost interrupt is generated.
-                ARB_LOST_INT_ST: u1,
-                ///  Error interrupt. If this bit is set to 1, it indicates an error is detected on the bus.
-                BUS_ERR_INT_ST: u1,
-                padding: u24,
-            }),
-            ///  Interrupt Enable Register
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to 1 to enable receive interrupt.
-                RX_INT_ENA: u1,
-                ///  Set this bit to 1 to enable transmit interrupt.
-                TX_INT_ENA: u1,
-                ///  Set this bit to 1 to enable error warning interrupt.
-                ERR_WARN_INT_ENA: u1,
-                ///  Set this bit to 1 to enable data overrun interrupt.
-                OVERRUN_INT_ENA: u1,
-                reserved5: u1,
-                ///  Set this bit to 1 to enable error passive interrupt.
-                ERR_PASSIVE_INT_ENA: u1,
-                ///  Set this bit to 1 to enable arbitration lost interrupt.
-                ARB_LOST_INT_ENA: u1,
-                ///  Set this bit to 1 to enable error interrupt.
-                BUS_ERR_INT_ENA: u1,
-                padding: u24,
-            }),
-            reserved24: [4]u8,
-            ///  Bus Timing Register 0
-            BUS_TIMING_0: mmio.Mmio(packed struct(u32) {
-                ///  Baud Rate Prescaler, determines the frequency dividing ratio.
-                BAUD_PRESC: u13,
-                reserved14: u1,
-                ///  Synchronization Jump Width (SJW), 1 \verb+~+ 14 Tq wide.
-                SYNC_JUMP_WIDTH: u2,
-                padding: u16,
-            }),
-            ///  Bus Timing Register 1
-            BUS_TIMING_1: mmio.Mmio(packed struct(u32) {
-                ///  The width of PBS1.
-                TIME_SEG1: u4,
-                ///  The width of PBS2.
-                TIME_SEG2: u3,
-                ///  The number of sample points. 0: the bus is sampled once; 1: the bus is sampled three times
-                TIME_SAMP: u1,
-                padding: u24,
-            }),
-            reserved44: [12]u8,
-            ///  Arbitration Lost Capture Register
-            ARB_LOST_CAP: mmio.Mmio(packed struct(u32) {
-                ///  This register contains information about the bit position of lost arbitration.
-                ARB_LOST_CAP: u5,
-                padding: u27,
-            }),
-            ///  Error Code Capture Register
-            ERR_CODE_CAP: mmio.Mmio(packed struct(u32) {
-                ///  This register contains information about the location of errors, see Table 181 for details.
-                ECC_SEGMENT: u5,
-                ///  This register contains information about transmission direction of the node when error occurs. 1: Error occurs when receiving a message; 0: Error occurs when transmitting a message
-                ECC_DIRECTION: u1,
-                ///  This register contains information about error types: 00: bit error; 01: form error; 10: stuff error; 11: other type of error
-                ECC_TYPE: u2,
-                padding: u24,
-            }),
-            ///  Error Warning Limit Register
-            ERR_WARNING_LIMIT: mmio.Mmio(packed struct(u32) {
-                ///  Error warning threshold. In the case when any of a error counter value exceeds the threshold, or all the error counter values are below the threshold, an error warning interrupt will be triggered (given the enable signal is valid).
-                ERR_WARNING_LIMIT: u8,
-                padding: u24,
-            }),
-            ///  Receive Error Counter Register
-            RX_ERR_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The RX error counter register, reflects value changes under reception status.
-                RX_ERR_CNT: u8,
-                padding: u24,
-            }),
-            ///  Transmit Error Counter Register
-            TX_ERR_CNT: mmio.Mmio(packed struct(u32) {
-                ///  The TX error counter register, reflects value changes under transmission status.
-                TX_ERR_CNT: u8,
-                padding: u24,
-            }),
-            ///  Data register 0
-            DATA_0: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance code register 0 with R/W Permission. In operation mode, it stores the 0th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_0: u8,
-                padding: u24,
-            }),
-            ///  Data register 1
-            DATA_1: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance code register 1 with R/W Permission. In operation mode, it stores the 1st byte information of the data to be transmitted under operating mode.
-                TX_BYTE_1: u8,
-                padding: u24,
-            }),
-            ///  Data register 2
-            DATA_2: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance code register 2 with R/W Permission. In operation mode, it stores the 2nd byte information of the data to be transmitted under operating mode.
-                TX_BYTE_2: u8,
-                padding: u24,
-            }),
-            ///  Data register 3
-            DATA_3: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance code register 3 with R/W Permission. In operation mode, it stores the 3rd byte information of the data to be transmitted under operating mode.
-                TX_BYTE_3: u8,
-                padding: u24,
-            }),
-            ///  Data register 4
-            DATA_4: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance mask register 0 with R/W Permission. In operation mode, it stores the 4th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_4: u8,
-                padding: u24,
-            }),
-            ///  Data register 5
-            DATA_5: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance mask register 1 with R/W Permission. In operation mode, it stores the 5th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_5: u8,
-                padding: u24,
-            }),
-            ///  Data register 6
-            DATA_6: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance mask register 2 with R/W Permission. In operation mode, it stores the 6th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_6: u8,
-                padding: u24,
-            }),
-            ///  Data register 7
-            DATA_7: mmio.Mmio(packed struct(u32) {
-                ///  In reset mode, it is acceptance mask register 3 with R/W Permission. In operation mode, it stores the 7th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_7: u8,
-                padding: u24,
-            }),
-            ///  Data register 8
-            DATA_8: mmio.Mmio(packed struct(u32) {
-                ///  Stored the 8th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_8: u8,
-                padding: u24,
-            }),
-            ///  Data register 9
-            DATA_9: mmio.Mmio(packed struct(u32) {
-                ///  Stored the 9th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_9: u8,
-                padding: u24,
-            }),
-            ///  Data register 10
-            DATA_10: mmio.Mmio(packed struct(u32) {
-                ///  Stored the 10th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_10: u8,
-                padding: u24,
-            }),
-            ///  Data register 11
-            DATA_11: mmio.Mmio(packed struct(u32) {
-                ///  Stored the 11th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_11: u8,
-                padding: u24,
-            }),
-            ///  Data register 12
-            DATA_12: mmio.Mmio(packed struct(u32) {
-                ///  Stored the 12th byte information of the data to be transmitted under operating mode.
-                TX_BYTE_12: u8,
-                padding: u24,
-            }),
-            ///  Receive Message Counter Register
-            RX_MESSAGE_CNT: mmio.Mmio(packed struct(u32) {
-                ///  This register reflects the number of messages available within the RX FIFO.
-                RX_MESSAGE_COUNTER: u7,
-                padding: u25,
-            }),
-            reserved124: [4]u8,
-            ///  Clock Divider register
-            CLOCK_DIVIDER: mmio.Mmio(packed struct(u32) {
-                ///  These bits are used to configure frequency dividing coefficients of the external CLKOUT pin.
-                CD: u8,
-                ///  This bit can be configured under reset mode. 1: Disable the external CLKOUT pin; 0: Enable the external CLKOUT pin
-                CLOCK_OFF: u1,
-                padding: u23,
-            }),
-        };
-
-        ///  UART (Universal Asynchronous Receiver-Transmitter) Controller
-        pub const UART0 = extern struct {
-            ///  FIFO data register
-            FIFO: mmio.Mmio(packed struct(u32) {
-                ///  UART 0 accesses FIFO via this register.
-                RXFIFO_RD_BYTE: u8,
-                padding: u24,
-            }),
-            ///  Raw interrupt status
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  This interrupt raw bit turns to high level when receiver receives more data than what rxfifo_full_thrhd specifies.
-                RXFIFO_FULL_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when the amount of data in Tx-FIFO is less than what txfifo_empty_thrhd specifies .
-                TXFIFO_EMPTY_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a parity error in the data.
-                PARITY_ERR_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a data frame error .
-                FRM_ERR_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver receives more data than the FIFO can store.
-                RXFIFO_OVF_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects the edge change of DSRn signal.
-                DSR_CHG_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects the edge change of CTSn signal.
-                CTS_CHG_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a 0 after the stop bit.
-                BRK_DET_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver takes more time than rx_tout_thrhd to receive a byte.
-                RXFIFO_TOUT_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver recevies Xon char when uart_sw_flow_con_en is set to 1.
-                SW_XON_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver receives Xoff char when uart_sw_flow_con_en is set to 1.
-                SW_XOFF_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a glitch in the middle of a start bit.
-                GLITCH_DET_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when transmitter completes sending NULL characters, after all data in Tx-FIFO are sent.
-                TX_BRK_DONE_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when transmitter has kept the shortest duration after sending the last data.
-                TX_BRK_IDLE_DONE_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when transmitter has send out all data in FIFO.
-                TX_DONE_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a parity error from the echo of transmitter in rs485 mode.
-                RS485_PARITY_ERR_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects a data frame error from the echo of transmitter in rs485 mode.
-                RS485_FRM_ERR_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when detects a clash between transmitter and receiver in rs485 mode.
-                RS485_CLASH_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when receiver detects the configured at_cmd char.
-                AT_CMD_CHAR_DET_INT_RAW: u1,
-                ///  This interrupt raw bit turns to high level when input rxd edge changes more times than what reg_active_threshold specifies in light sleeping mode.
-                WAKEUP_INT_RAW: u1,
-                padding: u12,
-            }),
-            ///  Masked interrupt status
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  This is the status bit for rxfifo_full_int_raw when rxfifo_full_int_ena is set to 1.
-                RXFIFO_FULL_INT_ST: u1,
-                ///  This is the status bit for txfifo_empty_int_raw when txfifo_empty_int_ena is set to 1.
-                TXFIFO_EMPTY_INT_ST: u1,
-                ///  This is the status bit for parity_err_int_raw when parity_err_int_ena is set to 1.
-                PARITY_ERR_INT_ST: u1,
-                ///  This is the status bit for frm_err_int_raw when frm_err_int_ena is set to 1.
-                FRM_ERR_INT_ST: u1,
-                ///  This is the status bit for rxfifo_ovf_int_raw when rxfifo_ovf_int_ena is set to 1.
-                RXFIFO_OVF_INT_ST: u1,
-                ///  This is the status bit for dsr_chg_int_raw when dsr_chg_int_ena is set to 1.
-                DSR_CHG_INT_ST: u1,
-                ///  This is the status bit for cts_chg_int_raw when cts_chg_int_ena is set to 1.
-                CTS_CHG_INT_ST: u1,
-                ///  This is the status bit for brk_det_int_raw when brk_det_int_ena is set to 1.
-                BRK_DET_INT_ST: u1,
-                ///  This is the status bit for rxfifo_tout_int_raw when rxfifo_tout_int_ena is set to 1.
-                RXFIFO_TOUT_INT_ST: u1,
-                ///  This is the status bit for sw_xon_int_raw when sw_xon_int_ena is set to 1.
-                SW_XON_INT_ST: u1,
-                ///  This is the status bit for sw_xoff_int_raw when sw_xoff_int_ena is set to 1.
-                SW_XOFF_INT_ST: u1,
-                ///  This is the status bit for glitch_det_int_raw when glitch_det_int_ena is set to 1.
-                GLITCH_DET_INT_ST: u1,
-                ///  This is the status bit for tx_brk_done_int_raw when tx_brk_done_int_ena is set to 1.
-                TX_BRK_DONE_INT_ST: u1,
-                ///  This is the stauts bit for tx_brk_idle_done_int_raw when tx_brk_idle_done_int_ena is set to 1.
-                TX_BRK_IDLE_DONE_INT_ST: u1,
-                ///  This is the status bit for tx_done_int_raw when tx_done_int_ena is set to 1.
-                TX_DONE_INT_ST: u1,
-                ///  This is the status bit for rs485_parity_err_int_raw when rs485_parity_int_ena is set to 1.
-                RS485_PARITY_ERR_INT_ST: u1,
-                ///  This is the status bit for rs485_frm_err_int_raw when rs485_fm_err_int_ena is set to 1.
-                RS485_FRM_ERR_INT_ST: u1,
-                ///  This is the status bit for rs485_clash_int_raw when rs485_clash_int_ena is set to 1.
-                RS485_CLASH_INT_ST: u1,
-                ///  This is the status bit for at_cmd_det_int_raw when at_cmd_char_det_int_ena is set to 1.
-                AT_CMD_CHAR_DET_INT_ST: u1,
-                ///  This is the status bit for uart_wakeup_int_raw when uart_wakeup_int_ena is set to 1.
-                WAKEUP_INT_ST: u1,
-                padding: u12,
-            }),
-            ///  Interrupt enable bits
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  This is the enable bit for rxfifo_full_int_st register.
-                RXFIFO_FULL_INT_ENA: u1,
-                ///  This is the enable bit for txfifo_empty_int_st register.
-                TXFIFO_EMPTY_INT_ENA: u1,
-                ///  This is the enable bit for parity_err_int_st register.
-                PARITY_ERR_INT_ENA: u1,
-                ///  This is the enable bit for frm_err_int_st register.
-                FRM_ERR_INT_ENA: u1,
-                ///  This is the enable bit for rxfifo_ovf_int_st register.
-                RXFIFO_OVF_INT_ENA: u1,
-                ///  This is the enable bit for dsr_chg_int_st register.
-                DSR_CHG_INT_ENA: u1,
-                ///  This is the enable bit for cts_chg_int_st register.
-                CTS_CHG_INT_ENA: u1,
-                ///  This is the enable bit for brk_det_int_st register.
-                BRK_DET_INT_ENA: u1,
-                ///  This is the enable bit for rxfifo_tout_int_st register.
-                RXFIFO_TOUT_INT_ENA: u1,
-                ///  This is the enable bit for sw_xon_int_st register.
-                SW_XON_INT_ENA: u1,
-                ///  This is the enable bit for sw_xoff_int_st register.
-                SW_XOFF_INT_ENA: u1,
-                ///  This is the enable bit for glitch_det_int_st register.
-                GLITCH_DET_INT_ENA: u1,
-                ///  This is the enable bit for tx_brk_done_int_st register.
-                TX_BRK_DONE_INT_ENA: u1,
-                ///  This is the enable bit for tx_brk_idle_done_int_st register.
-                TX_BRK_IDLE_DONE_INT_ENA: u1,
-                ///  This is the enable bit for tx_done_int_st register.
-                TX_DONE_INT_ENA: u1,
-                ///  This is the enable bit for rs485_parity_err_int_st register.
-                RS485_PARITY_ERR_INT_ENA: u1,
-                ///  This is the enable bit for rs485_parity_err_int_st register.
-                RS485_FRM_ERR_INT_ENA: u1,
-                ///  This is the enable bit for rs485_clash_int_st register.
-                RS485_CLASH_INT_ENA: u1,
-                ///  This is the enable bit for at_cmd_char_det_int_st register.
-                AT_CMD_CHAR_DET_INT_ENA: u1,
-                ///  This is the enable bit for uart_wakeup_int_st register.
-                WAKEUP_INT_ENA: u1,
-                padding: u12,
-            }),
-            ///  Interrupt clear bits
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the rxfifo_full_int_raw interrupt.
-                RXFIFO_FULL_INT_CLR: u1,
-                ///  Set this bit to clear txfifo_empty_int_raw interrupt.
-                TXFIFO_EMPTY_INT_CLR: u1,
-                ///  Set this bit to clear parity_err_int_raw interrupt.
-                PARITY_ERR_INT_CLR: u1,
-                ///  Set this bit to clear frm_err_int_raw interrupt.
-                FRM_ERR_INT_CLR: u1,
-                ///  Set this bit to clear rxfifo_ovf_int_raw interrupt.
-                RXFIFO_OVF_INT_CLR: u1,
-                ///  Set this bit to clear the dsr_chg_int_raw interrupt.
-                DSR_CHG_INT_CLR: u1,
-                ///  Set this bit to clear the cts_chg_int_raw interrupt.
-                CTS_CHG_INT_CLR: u1,
-                ///  Set this bit to clear the brk_det_int_raw interrupt.
-                BRK_DET_INT_CLR: u1,
-                ///  Set this bit to clear the rxfifo_tout_int_raw interrupt.
-                RXFIFO_TOUT_INT_CLR: u1,
-                ///  Set this bit to clear the sw_xon_int_raw interrupt.
-                SW_XON_INT_CLR: u1,
-                ///  Set this bit to clear the sw_xoff_int_raw interrupt.
-                SW_XOFF_INT_CLR: u1,
-                ///  Set this bit to clear the glitch_det_int_raw interrupt.
-                GLITCH_DET_INT_CLR: u1,
-                ///  Set this bit to clear the tx_brk_done_int_raw interrupt..
-                TX_BRK_DONE_INT_CLR: u1,
-                ///  Set this bit to clear the tx_brk_idle_done_int_raw interrupt.
-                TX_BRK_IDLE_DONE_INT_CLR: u1,
-                ///  Set this bit to clear the tx_done_int_raw interrupt.
-                TX_DONE_INT_CLR: u1,
-                ///  Set this bit to clear the rs485_parity_err_int_raw interrupt.
-                RS485_PARITY_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the rs485_frm_err_int_raw interrupt.
-                RS485_FRM_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the rs485_clash_int_raw interrupt.
-                RS485_CLASH_INT_CLR: u1,
-                ///  Set this bit to clear the at_cmd_char_det_int_raw interrupt.
-                AT_CMD_CHAR_DET_INT_CLR: u1,
-                ///  Set this bit to clear the uart_wakeup_int_raw interrupt.
-                WAKEUP_INT_CLR: u1,
-                padding: u12,
-            }),
-            ///  Clock divider configuration
-            CLKDIV: mmio.Mmio(packed struct(u32) {
-                ///  The integral part of the frequency divider factor.
-                CLKDIV: u12,
-                reserved20: u8,
-                ///  The decimal part of the frequency divider factor.
-                FRAG: u4,
-                padding: u8,
-            }),
-            ///  Rx Filter configuration
-            RX_FILT: mmio.Mmio(packed struct(u32) {
-                ///  when input pulse width is lower than this value, the pulse is ignored.
-                GLITCH_FILT: u8,
-                ///  Set this bit to enable Rx signal filter.
-                GLITCH_FILT_EN: u1,
-                padding: u23,
-            }),
-            ///  UART status register
-            STATUS: mmio.Mmio(packed struct(u32) {
-                ///  Stores the byte number of valid data in Rx-FIFO.
-                RXFIFO_CNT: u10,
-                reserved13: u3,
-                ///  The register represent the level value of the internal uart dsr signal.
-                DSRN: u1,
-                ///  This register represent the level value of the internal uart cts signal.
-                CTSN: u1,
-                ///  This register represent the level value of the internal uart rxd signal.
-                RXD: u1,
-                ///  Stores the byte number of data in Tx-FIFO.
-                TXFIFO_CNT: u10,
-                reserved29: u3,
-                ///  This bit represents the level of the internal uart dtr signal.
-                DTRN: u1,
-                ///  This bit represents the level of the internal uart rts signal.
-                RTSN: u1,
-                ///  This bit represents the level of the internal uart txd signal.
-                TXD: u1,
-            }),
-            ///  a
-            CONF0: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the parity check mode.
-                PARITY: u1,
-                ///  Set this bit to enable uart parity check.
-                PARITY_EN: u1,
-                ///  This register is used to set the length of data.
-                BIT_NUM: u2,
-                ///  This register is used to set the length of stop bit.
-                STOP_BIT_NUM: u2,
-                ///  This register is used to configure the software rts signal which is used in software flow control.
-                SW_RTS: u1,
-                ///  This register is used to configure the software dtr signal which is used in software flow control.
-                SW_DTR: u1,
-                ///  Set this bit to enbale transmitter to send NULL when the process of sending data is done.
-                TXD_BRK: u1,
-                ///  Set this bit to enable IrDA loopback mode.
-                IRDA_DPLX: u1,
-                ///  This is the start enable bit for IrDA transmitter.
-                IRDA_TX_EN: u1,
-                ///  1'h1: The IrDA transmitter's 11th bit is the same as 10th bit. 1'h0: Set IrDA transmitter's 11th bit to 0.
-                IRDA_WCTL: u1,
-                ///  Set this bit to invert the level of IrDA transmitter.
-                IRDA_TX_INV: u1,
-                ///  Set this bit to invert the level of IrDA receiver.
-                IRDA_RX_INV: u1,
-                ///  Set this bit to enable uart loopback test mode.
-                LOOPBACK: u1,
-                ///  Set this bit to enable flow control function for transmitter.
-                TX_FLOW_EN: u1,
-                ///  Set this bit to enable IrDA protocol.
-                IRDA_EN: u1,
-                ///  Set this bit to reset the uart receive-FIFO.
-                RXFIFO_RST: u1,
-                ///  Set this bit to reset the uart transmit-FIFO.
-                TXFIFO_RST: u1,
-                ///  Set this bit to inverse the level value of uart rxd signal.
-                RXD_INV: u1,
-                ///  Set this bit to inverse the level value of uart cts signal.
-                CTS_INV: u1,
-                ///  Set this bit to inverse the level value of uart dsr signal.
-                DSR_INV: u1,
-                ///  Set this bit to inverse the level value of uart txd signal.
-                TXD_INV: u1,
-                ///  Set this bit to inverse the level value of uart rts signal.
-                RTS_INV: u1,
-                ///  Set this bit to inverse the level value of uart dtr signal.
-                DTR_INV: u1,
-                ///  1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
-                CLK_EN: u1,
-                ///  1'h1: Receiver stops storing data into FIFO when data is wrong. 1'h0: Receiver stores the data even if the received data is wrong.
-                ERR_WR_MASK: u1,
-                ///  This is the enable bit for detecting baudrate.
-                AUTOBAUD_EN: u1,
-                ///  UART memory clock gate enable signal.
-                MEM_CLK_EN: u1,
-                padding: u3,
-            }),
-            ///  Configuration register 1
-            CONF1: mmio.Mmio(packed struct(u32) {
-                ///  It will produce rxfifo_full_int interrupt when receiver receives more data than this register value.
-                RXFIFO_FULL_THRHD: u9,
-                ///  It will produce txfifo_empty_int interrupt when the data amount in Tx-FIFO is less than this register value.
-                TXFIFO_EMPTY_THRHD: u9,
-                ///  Disable UART Rx data overflow detect.
-                DIS_RX_DAT_OVF: u1,
-                ///  Set this bit to stop accumulating idle_cnt when hardware flow control works.
-                RX_TOUT_FLOW_DIS: u1,
-                ///  This is the flow enable bit for UART receiver.
-                RX_FLOW_EN: u1,
-                ///  This is the enble bit for uart receiver's timeout function.
-                RX_TOUT_EN: u1,
-                padding: u10,
-            }),
-            ///  Autobaud minimum low pulse duration register
-            LOWPULSE: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the value of the minimum duration time of the low level pulse. It is used in baud rate-detect process.
-                MIN_CNT: u12,
-                padding: u20,
-            }),
-            ///  Autobaud minimum high pulse duration register
-            HIGHPULSE: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the value of the maxinum duration time for the high level pulse. It is used in baud rate-detect process.
-                MIN_CNT: u12,
-                padding: u20,
-            }),
-            ///  Autobaud edge change count register
-            RXD_CNT: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the count of rxd edge change. It is used in baud rate-detect process.
-                RXD_EDGE_CNT: u10,
-                padding: u22,
-            }),
-            ///  Software flow-control configuration
-            FLOW_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to enable software flow control. It is used with register sw_xon or sw_xoff.
-                SW_FLOW_CON_EN: u1,
-                ///  Set this bit to remove flow control char from the received data.
-                XONOFF_DEL: u1,
-                ///  Set this bit to enable the transmitter to go on sending data.
-                FORCE_XON: u1,
-                ///  Set this bit to stop the transmitter from sending data.
-                FORCE_XOFF: u1,
-                ///  Set this bit to send Xon char. It is cleared by hardware automatically.
-                SEND_XON: u1,
-                ///  Set this bit to send Xoff char. It is cleared by hardware automatically.
-                SEND_XOFF: u1,
-                padding: u26,
-            }),
-            ///  Sleep-mode configuration
-            SLEEP_CONF: mmio.Mmio(packed struct(u32) {
-                ///  The uart is activated from light sleeping mode when the input rxd edge changes more times than this register value.
-                ACTIVE_THRESHOLD: u10,
-                padding: u22,
-            }),
-            ///  Software flow-control character configuration
-            SWFC_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  When the data amount in Rx-FIFO is more than this register value with uart_sw_flow_con_en set to 1, it will send a Xoff char.
-                XOFF_THRESHOLD: u9,
-                ///  This register stores the Xoff flow control char.
-                XOFF_CHAR: u8,
-                padding: u15,
-            }),
-            ///  Software flow-control character configuration
-            SWFC_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  When the data amount in Rx-FIFO is less than this register value with uart_sw_flow_con_en set to 1, it will send a Xon char.
-                XON_THRESHOLD: u9,
-                ///  This register stores the Xon flow control char.
-                XON_CHAR: u8,
-                padding: u15,
-            }),
-            ///  Tx Break character configuration
-            TXBRK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the number of 0 to be sent after the process of sending data is done. It is active when txd_brk is set to 1.
-                TX_BRK_NUM: u8,
-                padding: u24,
-            }),
-            ///  Frame-end idle configuration
-            IDLE_CONF: mmio.Mmio(packed struct(u32) {
-                ///  It will produce frame end signal when receiver takes more time to receive one byte data than this register value.
-                RX_IDLE_THRHD: u10,
-                ///  This register is used to configure the duration time between transfers.
-                TX_IDLE_NUM: u10,
-                padding: u12,
-            }),
-            ///  RS485 mode configuration
-            RS485_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to choose the rs485 mode.
-                RS485_EN: u1,
-                ///  Set this bit to delay the stop bit by 1 bit.
-                DL0_EN: u1,
-                ///  Set this bit to delay the stop bit by 1 bit.
-                DL1_EN: u1,
-                ///  Set this bit to enable receiver could receive data when the transmitter is transmitting data in rs485 mode.
-                RS485TX_RX_EN: u1,
-                ///  1'h1: enable rs485 transmitter to send data when rs485 receiver line is busy.
-                RS485RXBY_TX_EN: u1,
-                ///  This register is used to delay the receiver's internal data signal.
-                RS485_RX_DLY_NUM: u1,
-                ///  This register is used to delay the transmitter's internal data signal.
-                RS485_TX_DLY_NUM: u4,
-                padding: u22,
-            }),
-            ///  Pre-sequence timing configuration
-            AT_CMD_PRECNT: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the idle duration time before the first at_cmd is received by receiver.
-                PRE_IDLE_NUM: u16,
-                padding: u16,
-            }),
-            ///  Post-sequence timing configuration
-            AT_CMD_POSTCNT: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the duration time between the last at_cmd and the next data.
-                POST_IDLE_NUM: u16,
-                padding: u16,
-            }),
-            ///  Timeout configuration
-            AT_CMD_GAPTOUT: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the duration time between the at_cmd chars.
-                RX_GAP_TOUT: u16,
-                padding: u16,
-            }),
-            ///  AT escape sequence detection configuration
-            AT_CMD_CHAR: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the content of at_cmd char.
-                AT_CMD_CHAR: u8,
-                ///  This register is used to configure the num of continuous at_cmd chars received by receiver.
-                CHAR_NUM: u8,
-                padding: u16,
-            }),
-            ///  UART threshold and allocation configuration
-            MEM_CONF: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  This register is used to configure the amount of mem allocated for receive-FIFO. The default number is 128 bytes.
-                RX_SIZE: u3,
-                ///  This register is used to configure the amount of mem allocated for transmit-FIFO. The default number is 128 bytes.
-                TX_SIZE: u3,
-                ///  This register is used to configure the maximum amount of data that can be received when hardware flow control works.
-                RX_FLOW_THRHD: u9,
-                ///  This register is used to configure the threshold time that receiver takes to receive one byte. The rxfifo_tout_int interrupt will be trigger when the receiver takes more time to receive one byte with rx_tout_en set to 1.
-                RX_TOUT_THRHD: u10,
-                ///  Set this bit to force power down UART memory.
-                MEM_FORCE_PD: u1,
-                ///  Set this bit to force power up UART memory.
-                MEM_FORCE_PU: u1,
-                padding: u4,
-            }),
-            ///  Tx-FIFO write and read offset address.
-            MEM_TX_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the offset address in Tx-FIFO when software writes Tx-FIFO via APB.
-                APB_TX_WADDR: u10,
-                reserved11: u1,
-                ///  This register stores the offset address in Tx-FIFO when Tx-FSM reads data via Tx-FIFO_Ctrl.
-                TX_RADDR: u10,
-                padding: u11,
-            }),
-            ///  Rx-FIFO write and read offset address.
-            MEM_RX_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the offset address in RX-FIFO when software reads data from Rx-FIFO via APB. UART0 is 10'h100. UART1 is 10'h180.
-                APB_RX_RADDR: u10,
-                reserved11: u1,
-                ///  This register stores the offset address in Rx-FIFO when Rx-FIFO_Ctrl writes Rx-FIFO. UART0 is 10'h100. UART1 is 10'h180.
-                RX_WADDR: u10,
-                padding: u11,
-            }),
-            ///  UART transmit and receive status.
-            FSM_STATUS: mmio.Mmio(packed struct(u32) {
-                ///  This is the status register of receiver.
-                ST_URX_OUT: u4,
-                ///  This is the status register of transmitter.
-                ST_UTX_OUT: u4,
-                padding: u24,
-            }),
-            ///  Autobaud high pulse register
-            POSPULSE: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the minimal input clock count between two positive edges. It is used in boudrate-detect process.
-                POSEDGE_MIN_CNT: u12,
-                padding: u20,
-            }),
-            ///  Autobaud low pulse register
-            NEGPULSE: mmio.Mmio(packed struct(u32) {
-                ///  This register stores the minimal input clock count between two negative edges. It is used in boudrate-detect process.
-                NEGEDGE_MIN_CNT: u12,
-                padding: u20,
-            }),
-            ///  UART core clock configuration
-            CLK_CONF: mmio.Mmio(packed struct(u32) {
-                ///  The denominator of the frequency divider factor.
-                SCLK_DIV_B: u6,
-                ///  The numerator of the frequency divider factor.
-                SCLK_DIV_A: u6,
-                ///  The integral part of the frequency divider factor.
-                SCLK_DIV_NUM: u8,
-                ///  UART clock source select. 1: 80Mhz, 2: 8Mhz, 3: XTAL.
-                SCLK_SEL: u2,
-                ///  Set this bit to enable UART Tx/Rx clock.
-                SCLK_EN: u1,
-                ///  Write 1 then write 0 to this bit, reset UART Tx/Rx.
-                RST_CORE: u1,
-                ///  Set this bit to enable UART Tx clock.
-                TX_SCLK_EN: u1,
-                ///  Set this bit to enable UART Rx clock.
-                RX_SCLK_EN: u1,
-                ///  Write 1 then write 0 to this bit, reset UART Tx.
-                TX_RST_CORE: u1,
-                ///  Write 1 then write 0 to this bit, reset UART Rx.
-                RX_RST_CORE: u1,
-                padding: u4,
-            }),
-            ///  UART Version register
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  This is the version register.
-                DATE: u32,
-            }),
-            ///  UART ID register
-            ID: mmio.Mmio(packed struct(u32) {
-                ///  This register is used to configure the uart_id.
-                ID: u30,
-                ///  This bit used to select synchronize mode. 1: Registers are auto synchronized into UART Core clock and UART core should be keep the same with APB clock. 0: After configure registers, software needs to write 1 to UART_REG_UPDATE to synchronize registers.
-                HIGH_SPEED: u1,
-                ///  Software write 1 would synchronize registers into UART Core clock domain and would be cleared by hardware after synchronization is done.
-                REG_UPDATE: u1,
-            }),
-        };
-
-        ///  Full-speed USB Serial/JTAG Controller
-        pub const USB_DEVICE = extern struct {
-            ///  USB_DEVICE_EP1_REG.
-            EP1: mmio.Mmio(packed struct(u32) {
-                ///  Write and read byte data to/from UART Tx/Rx FIFO through this field. When USB_DEVICE_SERIAL_IN_EMPTY_INT is set, then user can write data (up to 64 bytes) into UART Tx FIFO. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is set, user can check USB_DEVICE_OUT_EP1_WR_ADDR USB_DEVICE_OUT_EP0_RD_ADDR to know how many data is received, then read data from UART Rx FIFO.
-                RDWR_BYTE: u8,
-                padding: u24,
-            }),
-            ///  USB_DEVICE_EP1_CONF_REG.
-            EP1_CONF: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to indicate writing byte data to UART Tx FIFO is done.
-                WR_DONE: u1,
-                ///  1'b1: Indicate UART Tx FIFO is not full and can write data into in. After writing USB_DEVICE_WR_DONE, this bit would be 0 until data in UART Tx FIFO is read by USB Host.
-                SERIAL_IN_EP_DATA_FREE: u1,
-                ///  1'b1: Indicate there is data in UART Rx FIFO.
-                SERIAL_OUT_EP_DATA_AVAIL: u1,
-                padding: u29,
-            }),
-            ///  USB_DEVICE_INT_RAW_REG.
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt bit turns to high level when flush cmd is received for IN endpoint 2 of JTAG.
-                JTAG_IN_FLUSH_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when SOF frame is received.
-                SOF_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when Serial Port OUT Endpoint received one packet.
-                SERIAL_OUT_RECV_PKT_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when Serial Port IN Endpoint is empty.
-                SERIAL_IN_EMPTY_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when pid error is detected.
-                PID_ERR_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when CRC5 error is detected.
-                CRC5_ERR_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when CRC16 error is detected.
-                CRC16_ERR_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when stuff error is detected.
-                STUFF_ERR_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when IN token for IN endpoint 1 is received.
-                IN_TOKEN_REC_IN_EP1_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when usb bus reset is detected.
-                USB_BUS_RESET_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when OUT endpoint 1 received packet with zero palyload.
-                OUT_EP1_ZERO_PAYLOAD_INT_RAW: u1,
-                ///  The raw interrupt bit turns to high level when OUT endpoint 2 received packet with zero palyload.
-                OUT_EP2_ZERO_PAYLOAD_INT_RAW: u1,
-                padding: u20,
-            }),
-            ///  USB_DEVICE_INT_ST_REG.
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  The raw interrupt status bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-                JTAG_IN_FLUSH_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_SOF_INT interrupt.
-                SOF_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-                SERIAL_OUT_RECV_PKT_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-                SERIAL_IN_EMPTY_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_PID_ERR_INT interrupt.
-                PID_ERR_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
-                CRC5_ERR_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
-                CRC16_ERR_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
-                STUFF_ERR_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
-                IN_TOKEN_REC_IN_EP1_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-                USB_BUS_RESET_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP1_ZERO_PAYLOAD_INT_ST: u1,
-                ///  The raw interrupt status bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP2_ZERO_PAYLOAD_INT_ST: u1,
-                padding: u20,
-            }),
-            ///  USB_DEVICE_INT_ENA_REG.
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  The interrupt enable bit for the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-                JTAG_IN_FLUSH_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_SOF_INT interrupt.
-                SOF_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-                SERIAL_OUT_RECV_PKT_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-                SERIAL_IN_EMPTY_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_PID_ERR_INT interrupt.
-                PID_ERR_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_CRC5_ERR_INT interrupt.
-                CRC5_ERR_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_CRC16_ERR_INT interrupt.
-                CRC16_ERR_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_STUFF_ERR_INT interrupt.
-                STUFF_ERR_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_IN_TOKEN_REC_IN_EP1_INT interrupt.
-                IN_TOKEN_REC_IN_EP1_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-                USB_BUS_RESET_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP1_ZERO_PAYLOAD_INT_ENA: u1,
-                ///  The interrupt enable bit for the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP2_ZERO_PAYLOAD_INT_ENA: u1,
-                padding: u20,
-            }),
-            ///  USB_DEVICE_INT_CLR_REG.
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  Set this bit to clear the USB_DEVICE_JTAG_IN_FLUSH_INT interrupt.
-                JTAG_IN_FLUSH_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_JTAG_SOF_INT interrupt.
-                SOF_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_SERIAL_OUT_RECV_PKT_INT interrupt.
-                SERIAL_OUT_RECV_PKT_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_SERIAL_IN_EMPTY_INT interrupt.
-                SERIAL_IN_EMPTY_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_PID_ERR_INT interrupt.
-                PID_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_CRC5_ERR_INT interrupt.
-                CRC5_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_CRC16_ERR_INT interrupt.
-                CRC16_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_STUFF_ERR_INT interrupt.
-                STUFF_ERR_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_IN_TOKEN_IN_EP1_INT interrupt.
-                IN_TOKEN_REC_IN_EP1_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_USB_BUS_RESET_INT interrupt.
-                USB_BUS_RESET_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_OUT_EP1_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP1_ZERO_PAYLOAD_INT_CLR: u1,
-                ///  Set this bit to clear the USB_DEVICE_OUT_EP2_ZERO_PAYLOAD_INT interrupt.
-                OUT_EP2_ZERO_PAYLOAD_INT_CLR: u1,
-                padding: u20,
-            }),
-            ///  USB_DEVICE_CONF0_REG.
-            CONF0: mmio.Mmio(packed struct(u32) {
-                ///  Select internal/external PHY
-                PHY_SEL: u1,
-                ///  Enable software control USB D+ D- exchange
-                EXCHG_PINS_OVERRIDE: u1,
-                ///  USB D+ D- exchange
-                EXCHG_PINS: u1,
-                ///  Control single-end input high threshold,1.76V to 2V, step 80mV
-                VREFH: u2,
-                ///  Control single-end input low threshold,0.8V to 1.04V, step 80mV
-                VREFL: u2,
-                ///  Enable software control input threshold
-                VREF_OVERRIDE: u1,
-                ///  Enable software control USB D+ D- pullup pulldown
-                PAD_PULL_OVERRIDE: u1,
-                ///  Control USB D+ pull up.
-                DP_PULLUP: u1,
-                ///  Control USB D+ pull down.
-                DP_PULLDOWN: u1,
-                ///  Control USB D- pull up.
-                DM_PULLUP: u1,
-                ///  Control USB D- pull down.
-                DM_PULLDOWN: u1,
-                ///  Control pull up value.
-                PULLUP_VALUE: u1,
-                ///  Enable USB pad function.
-                USB_PAD_ENABLE: u1,
-                padding: u17,
-            }),
-            ///  USB_DEVICE_TEST_REG.
-            TEST: mmio.Mmio(packed struct(u32) {
-                ///  Enable test of the USB pad
-                ENABLE: u1,
-                ///  USB pad oen in test
-                USB_OE: u1,
-                ///  USB D+ tx value in test
-                TX_DP: u1,
-                ///  USB D- tx value in test
-                TX_DM: u1,
-                padding: u28,
-            }),
-            ///  USB_DEVICE_JFIFO_ST_REG.
-            JFIFO_ST: mmio.Mmio(packed struct(u32) {
-                ///  JTAT in fifo counter.
-                IN_FIFO_CNT: u2,
-                ///  1: JTAG in fifo is empty.
-                IN_FIFO_EMPTY: u1,
-                ///  1: JTAG in fifo is full.
-                IN_FIFO_FULL: u1,
-                ///  JTAT out fifo counter.
-                OUT_FIFO_CNT: u2,
-                ///  1: JTAG out fifo is empty.
-                OUT_FIFO_EMPTY: u1,
-                ///  1: JTAG out fifo is full.
-                OUT_FIFO_FULL: u1,
-                ///  Write 1 to reset JTAG in fifo.
-                IN_FIFO_RESET: u1,
-                ///  Write 1 to reset JTAG out fifo.
-                OUT_FIFO_RESET: u1,
-                padding: u22,
-            }),
-            ///  USB_DEVICE_FRAM_NUM_REG.
-            FRAM_NUM: mmio.Mmio(packed struct(u32) {
-                ///  Frame index of received SOF frame.
-                SOF_FRAME_INDEX: u11,
-                padding: u21,
-            }),
-            ///  USB_DEVICE_IN_EP0_ST_REG.
-            IN_EP0_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of IN Endpoint 0.
-                IN_EP0_STATE: u2,
-                ///  Write data address of IN endpoint 0.
-                IN_EP0_WR_ADDR: u7,
-                ///  Read data address of IN endpoint 0.
-                IN_EP0_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_IN_EP1_ST_REG.
-            IN_EP1_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of IN Endpoint 1.
-                IN_EP1_STATE: u2,
-                ///  Write data address of IN endpoint 1.
-                IN_EP1_WR_ADDR: u7,
-                ///  Read data address of IN endpoint 1.
-                IN_EP1_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_IN_EP2_ST_REG.
-            IN_EP2_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of IN Endpoint 2.
-                IN_EP2_STATE: u2,
-                ///  Write data address of IN endpoint 2.
-                IN_EP2_WR_ADDR: u7,
-                ///  Read data address of IN endpoint 2.
-                IN_EP2_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_IN_EP3_ST_REG.
-            IN_EP3_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of IN Endpoint 3.
-                IN_EP3_STATE: u2,
-                ///  Write data address of IN endpoint 3.
-                IN_EP3_WR_ADDR: u7,
-                ///  Read data address of IN endpoint 3.
-                IN_EP3_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_OUT_EP0_ST_REG.
-            OUT_EP0_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of OUT Endpoint 0.
-                OUT_EP0_STATE: u2,
-                ///  Write data address of OUT endpoint 0. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP0_WR_ADDR-2 bytes data in OUT EP0.
-                OUT_EP0_WR_ADDR: u7,
-                ///  Read data address of OUT endpoint 0.
-                OUT_EP0_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_OUT_EP1_ST_REG.
-            OUT_EP1_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of OUT Endpoint 1.
-                OUT_EP1_STATE: u2,
-                ///  Write data address of OUT endpoint 1. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP1_WR_ADDR-2 bytes data in OUT EP1.
-                OUT_EP1_WR_ADDR: u7,
-                ///  Read data address of OUT endpoint 1.
-                OUT_EP1_RD_ADDR: u7,
-                ///  Data count in OUT endpoint 1 when one packet is received.
-                OUT_EP1_REC_DATA_CNT: u7,
-                padding: u9,
-            }),
-            ///  USB_DEVICE_OUT_EP2_ST_REG.
-            OUT_EP2_ST: mmio.Mmio(packed struct(u32) {
-                ///  State of OUT Endpoint 2.
-                OUT_EP2_STATE: u2,
-                ///  Write data address of OUT endpoint 2. When USB_DEVICE_SERIAL_OUT_RECV_PKT_INT is detected, there are USB_DEVICE_OUT_EP2_WR_ADDR-2 bytes data in OUT EP2.
-                OUT_EP2_WR_ADDR: u7,
-                ///  Read data address of OUT endpoint 2.
-                OUT_EP2_RD_ADDR: u7,
-                padding: u16,
-            }),
-            ///  USB_DEVICE_MISC_CONF_REG.
-            MISC_CONF: mmio.Mmio(packed struct(u32) {
-                ///  1'h1: Force clock on for register. 1'h0: Support clock only when application writes registers.
-                CLK_EN: u1,
-                padding: u31,
-            }),
-            ///  USB_DEVICE_MEM_CONF_REG.
-            MEM_CONF: mmio.Mmio(packed struct(u32) {
-                ///  1: power down usb memory.
-                USB_MEM_PD: u1,
-                ///  1: Force clock on for usb memory.
-                USB_MEM_CLK_EN: u1,
-                padding: u30,
-            }),
-            reserved128: [52]u8,
-            ///  USB_DEVICE_DATE_REG.
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  register version.
-                DATE: u32,
-            }),
-        };
-
-        ///  Universal Host Controller Interface
-        pub const UHCI0 = extern struct {
-            ///  a
-            CONF0: mmio.Mmio(packed struct(u32) {
-                ///  Write 1, then write 0 to this bit to reset decode state machine.
-                TX_RST: u1,
-                ///  Write 1, then write 0 to this bit to reset encode state machine.
-                RX_RST: u1,
-                ///  Set this bit to link up HCI and UART0.
-                UART0_CE: u1,
-                ///  Set this bit to link up HCI and UART1.
-                UART1_CE: u1,
-                reserved5: u1,
-                ///  Set this bit to separate the data frame using a special char.
-                SEPER_EN: u1,
-                ///  Set this bit to encode the data packet with a formatting header.
-                HEAD_EN: u1,
-                ///  Set this bit to enable UHCI to receive the 16 bit CRC.
-                CRC_REC_EN: u1,
-                ///  If this bit is set to 1, UHCI will end the payload receiving process when UART has been in idle state.
-                UART_IDLE_EOF_EN: u1,
-                ///  If this bit is set to 1, UHCI decoder receiving payload data is end when the receiving byte count has reached the specified value. The value is payload length indicated by UHCI packet header when UHCI_HEAD_EN is 1 or the value is configuration value when UHCI_HEAD_EN is 0. If this bit is set to 0, UHCI decoder receiving payload data is end when 0xc0 is received.
-                LEN_EOF_EN: u1,
-                ///  Set this bit to enable data integrity checking by appending a 16 bit CCITT-CRC to end of the payload.
-                ENCODE_CRC_EN: u1,
-                ///  1'b1: Force clock on for register. 1'b0: Support clock only when application writes registers.
-                CLK_EN: u1,
-                ///  If this bit is set to 1, UHCI will end payload receive process when NULL frame is received by UART.
-                UART_RX_BRK_EOF_EN: u1,
-                padding: u19,
-            }),
-            ///  a
-            INT_RAW: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_START_INT_RAW: u1,
-                ///  a
-                TX_START_INT_RAW: u1,
-                ///  a
-                RX_HUNG_INT_RAW: u1,
-                ///  a
-                TX_HUNG_INT_RAW: u1,
-                ///  a
-                SEND_S_REG_Q_INT_RAW: u1,
-                ///  a
-                SEND_A_REG_Q_INT_RAW: u1,
-                ///  This is the interrupt raw bit. Triggered when there are some errors in EOF in the
-                OUT_EOF_INT_RAW: u1,
-                ///  Soft control int raw bit.
-                APP_CTRL0_INT_RAW: u1,
-                ///  Soft control int raw bit.
-                APP_CTRL1_INT_RAW: u1,
-                padding: u23,
-            }),
-            ///  a
-            INT_ST: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_START_INT_ST: u1,
-                ///  a
-                TX_START_INT_ST: u1,
-                ///  a
-                RX_HUNG_INT_ST: u1,
-                ///  a
-                TX_HUNG_INT_ST: u1,
-                ///  a
-                SEND_S_REG_Q_INT_ST: u1,
-                ///  a
-                SEND_A_REG_Q_INT_ST: u1,
-                ///  a
-                OUTLINK_EOF_ERR_INT_ST: u1,
-                ///  a
-                APP_CTRL0_INT_ST: u1,
-                ///  a
-                APP_CTRL1_INT_ST: u1,
-                padding: u23,
-            }),
-            ///  a
-            INT_ENA: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_START_INT_ENA: u1,
-                ///  a
-                TX_START_INT_ENA: u1,
-                ///  a
-                RX_HUNG_INT_ENA: u1,
-                ///  a
-                TX_HUNG_INT_ENA: u1,
-                ///  a
-                SEND_S_REG_Q_INT_ENA: u1,
-                ///  a
-                SEND_A_REG_Q_INT_ENA: u1,
-                ///  a
-                OUTLINK_EOF_ERR_INT_ENA: u1,
-                ///  a
-                APP_CTRL0_INT_ENA: u1,
-                ///  a
-                APP_CTRL1_INT_ENA: u1,
-                padding: u23,
-            }),
-            ///  a
-            INT_CLR: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_START_INT_CLR: u1,
-                ///  a
-                TX_START_INT_CLR: u1,
-                ///  a
-                RX_HUNG_INT_CLR: u1,
-                ///  a
-                TX_HUNG_INT_CLR: u1,
-                ///  a
-                SEND_S_REG_Q_INT_CLR: u1,
-                ///  a
-                SEND_A_REG_Q_INT_CLR: u1,
-                ///  a
-                OUTLINK_EOF_ERR_INT_CLR: u1,
-                ///  a
-                APP_CTRL0_INT_CLR: u1,
-                ///  a
-                APP_CTRL1_INT_CLR: u1,
-                padding: u23,
-            }),
-            ///  a
-            CONF1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                CHECK_SUM_EN: u1,
-                ///  a
-                CHECK_SEQ_EN: u1,
-                ///  a
-                CRC_DISABLE: u1,
-                ///  a
-                SAVE_HEAD: u1,
-                ///  a
-                TX_CHECK_SUM_RE: u1,
-                ///  a
-                TX_ACK_NUM_RE: u1,
-                reserved7: u1,
-                ///  a
-                WAIT_SW_START: u1,
-                ///  a
-                SW_START: u1,
-                padding: u23,
-            }),
-            ///  a
-            STATE0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_ERR_CAUSE: u3,
-                ///  a
-                DECODE_STATE: u3,
-                padding: u26,
-            }),
-            ///  a
-            STATE1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                ENCODE_STATE: u3,
-                padding: u29,
-            }),
-            ///  a
-            ESCAPE_CONF: mmio.Mmio(packed struct(u32) {
-                ///  a
-                TX_C0_ESC_EN: u1,
-                ///  a
-                TX_DB_ESC_EN: u1,
-                ///  a
-                TX_11_ESC_EN: u1,
-                ///  a
-                TX_13_ESC_EN: u1,
-                ///  a
-                RX_C0_ESC_EN: u1,
-                ///  a
-                RX_DB_ESC_EN: u1,
-                ///  a
-                RX_11_ESC_EN: u1,
-                ///  a
-                RX_13_ESC_EN: u1,
-                padding: u24,
-            }),
-            ///  a
-            HUNG_CONF: mmio.Mmio(packed struct(u32) {
-                ///  a
-                TXFIFO_TIMEOUT: u8,
-                ///  a
-                TXFIFO_TIMEOUT_SHIFT: u3,
-                ///  a
-                TXFIFO_TIMEOUT_ENA: u1,
-                ///  a
-                RXFIFO_TIMEOUT: u8,
-                ///  a
-                RXFIFO_TIMEOUT_SHIFT: u3,
-                ///  a
-                RXFIFO_TIMEOUT_ENA: u1,
-                padding: u8,
-            }),
-            ///  a
-            ACK_NUM: mmio.Mmio(packed struct(u32) {
-                ///  a
-                ACK_NUM: u3,
-                ///  a
-                LOAD: u1,
-                padding: u28,
-            }),
-            ///  a
-            RX_HEAD: mmio.Mmio(packed struct(u32) {
-                ///  a
-                RX_HEAD: u32,
-            }),
-            ///  a
-            QUICK_SENT: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SINGLE_SEND_NUM: u3,
-                ///  a
-                SINGLE_SEND_EN: u1,
-                ///  a
-                ALWAYS_SEND_NUM: u3,
-                ///  a
-                ALWAYS_SEND_EN: u1,
-                padding: u24,
-            }),
-            ///  a
-            REG_Q0_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q0_WORD0: u32,
-            }),
-            ///  a
-            REG_Q0_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q0_WORD1: u32,
-            }),
-            ///  a
-            REG_Q1_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q1_WORD0: u32,
-            }),
-            ///  a
-            REG_Q1_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q1_WORD1: u32,
-            }),
-            ///  a
-            REG_Q2_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q2_WORD0: u32,
-            }),
-            ///  a
-            REG_Q2_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q2_WORD1: u32,
-            }),
-            ///  a
-            REG_Q3_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q3_WORD0: u32,
-            }),
-            ///  a
-            REG_Q3_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q3_WORD1: u32,
-            }),
-            ///  a
-            REG_Q4_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q4_WORD0: u32,
-            }),
-            ///  a
-            REG_Q4_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q4_WORD1: u32,
-            }),
-            ///  a
-            REG_Q5_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q5_WORD0: u32,
-            }),
-            ///  a
-            REG_Q5_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q5_WORD1: u32,
-            }),
-            ///  a
-            REG_Q6_WORD0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q6_WORD0: u32,
-            }),
-            ///  a
-            REG_Q6_WORD1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEND_Q6_WORD1: u32,
-            }),
-            ///  a
-            ESC_CONF0: mmio.Mmio(packed struct(u32) {
-                ///  a
-                SEPER_CHAR: u8,
-                ///  a
-                SEPER_ESC_CHAR0: u8,
-                ///  a
-                SEPER_ESC_CHAR1: u8,
-                padding: u8,
-            }),
-            ///  a
-            ESC_CONF1: mmio.Mmio(packed struct(u32) {
-                ///  a
-                ESC_SEQ0: u8,
-                ///  a
-                ESC_SEQ0_CHAR0: u8,
-                ///  a
-                ESC_SEQ0_CHAR1: u8,
-                padding: u8,
-            }),
-            ///  a
-            ESC_CONF2: mmio.Mmio(packed struct(u32) {
-                ///  a
-                ESC_SEQ1: u8,
-                ///  a
-                ESC_SEQ1_CHAR0: u8,
-                ///  a
-                ESC_SEQ1_CHAR1: u8,
-                padding: u8,
-            }),
-            ///  a
-            ESC_CONF3: mmio.Mmio(packed struct(u32) {
-                ///  a
-                ESC_SEQ2: u8,
-                ///  a
-                ESC_SEQ2_CHAR0: u8,
-                ///  a
-                ESC_SEQ2_CHAR1: u8,
-                padding: u8,
-            }),
-            ///  a
-            PKT_THRES: mmio.Mmio(packed struct(u32) {
-                ///  a
-                PKT_THRS: u13,
-                padding: u19,
-            }),
-            ///  a
-            DATE: mmio.Mmio(packed struct(u32) {
-                ///  a
-                DATE: u32,
-            }),
-        };
-    };
-};
diff --git a/src/cpus.zig b/src/cpus.zig
deleted file mode 100644
index c8bda913e..000000000
--- a/src/cpus.zig
+++ /dev/null
@@ -1,23 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
-
-pub const esp32_c3 = microzig.Cpu{
-    .name = "Espressif RISC-V",
-    .source = .{
-        .path = root_dir() ++ "/cpus/espressif-riscv.zig",
-    },
-    .target = std.zig.CrossTarget{
-        .cpu_arch = .riscv32,
-        .cpu_model = .{ .explicit = &std.Target.riscv.cpu.generic_rv32 },
-        .cpu_features_add = std.Target.riscv.featureSet(&.{
-            std.Target.riscv.Feature.c,
-            std.Target.riscv.Feature.m,
-        }),
-        .os_tag = .freestanding,
-        .abi = .eabi,
-    },
-};

From 696e309f6d80d873d9bbefeaad56b395366c851c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Fri, 22 Sep 2023 09:03:33 +0200
Subject: [PATCH 208/286] Microzig Generation 2 Build Interface  (#21)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* MicroZig Gen 2 interface
* Adds ELF patching to handle the checksum requirement

---------

Co-authored-by: Felix "xq" Queißner 
---
 .gitmodules             |     3 -
 build.zig               |   119 +-
 deps/microzig           |     1 -
 src/boards.zig          |    13 -
 src/chips.zig           |    18 -
 src/chips/LPC176x5x.zig | 12741 --------------------------------------
 src/hals/LPC176x5x.zig  |    20 +-
 src/tools/patchelf.zig  |    66 +
 8 files changed, 164 insertions(+), 12817 deletions(-)
 delete mode 160000 deps/microzig
 delete mode 100644 src/boards.zig
 delete mode 100644 src/chips.zig
 delete mode 100644 src/chips/LPC176x5x.zig
 create mode 100644 src/tools/patchelf.zig

diff --git a/.gitmodules b/.gitmodules
index 32e895ccb..e69de29bb 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +0,0 @@
-[submodule "deps/microzig"]
-	path = deps/microzig
-	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/build.zig b/build.zig
index 56ed4e58a..639a034ce 100644
--- a/build.zig
+++ b/build.zig
@@ -1,38 +1,95 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/build.zig");
 
-pub const boards = @import("src/boards.zig");
-pub const chips = @import("src/chips.zig");
+fn path(comptime suffix: []const u8) std.Build.LazyPath {
+    return .{
+        .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
+    };
+}
 
-pub fn build(b: *std.build.Builder) void {
-    const optimize = b.standardOptimizeOption(.{});
-    inline for (@typeInfo(boards).Struct.decls) |decl| {
-        if (!decl.is_pub)
-            continue;
+const hal = .{
+    .source_file = path("/src/hals/LPC176x5x.zig"),
+};
 
-        const exe = microzig.addEmbeddedExecutable(b, .{
-            .name = @field(boards, decl.name).name ++ ".minimal",
-            .source_file = .{
-                .path = "test/programs/minimal.zig",
+pub const chips = struct {
+    pub const lpc176x5x = .{
+        .preferred_format = .elf,
+        .chip = .{
+            // TODO: Separate over those chips, this is not generic!
+            .name = "LPC176x5x",
+            .cpu = .cortex_m3,
+            .memory_regions = &.{
+                .{ .offset = 0x00000000, .length = 512 * 1024, .kind = .flash },
+                .{ .offset = 0x10000000, .length = 32 * 1024, .kind = .ram },
+                .{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram },
+            },
+            .register_definition = .{
+                .json = path("/src/chips/LPC176x5x.json"),
             },
-            .backing = .{ .board = @field(boards, decl.name) },
-            .optimize = optimize,
-        });
-        exe.installArtifact(b);
-    }
-
-    inline for (@typeInfo(chips).Struct.decls) |decl| {
-        if (!decl.is_pub)
-            continue;
-
-        const exe = microzig.addEmbeddedExecutable(b, .{
-            .name = @field(chips, decl.name).name ++ ".minimal",
-            .source_file = .{
-                .path = "test/programs/minimal.zig",
+        },
+        .hal = hal,
+        .binary_post_process = postprocess,
+    };
+};
+
+pub const boards = struct {
+    pub const mbed = struct {
+        pub const lpc1768 = .{
+            .preferred_format = .hex,
+            .chip = chips.lpc176x5x.chip,
+            .hal = hal,
+            .board = .{
+                .name = "mbed LPC1768",
+                .url = "https://os.mbed.com/platforms/mbed-LPC1768/",
+                .source_file = path("/src/boards/mbed_LPC1768.zig"),
             },
-            .backing = .{ .chip = @field(chips, decl.name) },
-            .optimize = optimize,
-        });
-        exe.installArtifact(b);
-    }
+            .binary_post_process = postprocess,
+        };
+    };
+};
+
+/// Post-processes an ELF file to add a checksum over the first 8 words so the
+/// cpu will properly boot.
+fn postprocess(b: *std.Build, input: std.Build.LazyPath) std.Build.LazyPath {
+    const patchelf = b.addExecutable(.{
+        .name = "lpc176x5x-patchelf",
+        .root_source_file = path("/src/tools/patchelf.zig"),
+    });
+
+    const patch = b.addRunArtifact(patchelf);
+    patch.addFileArg(input);
+    return patch.addOutputFileArg("firmware.elf");
+}
+
+pub fn build(b: *std.Build) void {
+    _ = b;
+    // const optimize = b.standardOptimizeOption(.{});
+    // inline for (@typeInfo(boards).Struct.decls) |decl| {
+    //     if (!decl.is_pub)
+    //         continue;
+
+    //     const exe = microzig.addEmbeddedExecutable(b, .{
+    //         .name = @field(boards, decl.name).name ++ ".minimal",
+    //         .source_file = .{
+    //             .path = "test/programs/minimal.zig",
+    //         },
+    //         .backing = .{ .board = @field(boards, decl.name) },
+    //         .optimize = optimize,
+    //     });
+    //     exe.installArtifact(b);
+    // }
+
+    // inline for (@typeInfo(chips).Struct.decls) |decl| {
+    //     if (!decl.is_pub)
+    //         continue;
+
+    //     const exe = microzig.addEmbeddedExecutable(b, .{
+    //         .name = @field(chips, decl.name).name ++ ".minimal",
+    //         .source_file = .{
+    //             .path = "test/programs/minimal.zig",
+    //         },
+    //         .backing = .{ .chip = @field(chips, decl.name) },
+    //         .optimize = optimize,
+    //     });
+    //     exe.installArtifact(b);
+    // }
 }
diff --git a/deps/microzig b/deps/microzig
deleted file mode 160000
index 9392fe0f7..000000000
--- a/deps/microzig
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791
diff --git a/src/boards.zig b/src/boards.zig
deleted file mode 100644
index 9890a0c00..000000000
--- a/src/boards.zig
+++ /dev/null
@@ -1,13 +0,0 @@
-const std = @import("std");
-const micro = @import("../deps/microzig/build.zig");
-const chips = @import("chips.zig");
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse ".";
-}
-
-pub const mbed_lpc1768 = micro.Board{
-    .name = "mbed LPC1768",
-    .source = .{ .path = root_dir() ++ "/boards/mbed_LPC1768.zig" },
-    .chip = chips.lpc176x5x,
-};
diff --git a/src/chips.zig b/src/chips.zig
deleted file mode 100644
index 741fabadb..000000000
--- a/src/chips.zig
+++ /dev/null
@@ -1,18 +0,0 @@
-const std = @import("std");
-const micro = @import("../deps/microzig/build.zig");
-const Chip = micro.Chip;
-const MemoryRegion = micro.MemoryRegion;
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
-
-pub const lpc176x5x = Chip.from_standard_paths(root_dir(), .{
-    .name = "LPC176x5x",
-    .cpu = micro.cpus.cortex_m3,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x00000000, .length = 512 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x10000000, .length = 32 * 1024, .kind = .ram },
-        MemoryRegion{ .offset = 0x2007C000, .length = 32 * 1024, .kind = .ram },
-    },
-});
diff --git a/src/chips/LPC176x5x.zig b/src/chips/LPC176x5x.zig
deleted file mode 100644
index 34e166cb0..000000000
--- a/src/chips/LPC176x5x.zig
+++ /dev/null
@@ -1,12741 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    ///  LPC176x/LPC175x M3
-    pub const LPC176x5x = struct {
-        pub const properties = struct {
-            pub const @"cpu.nvic_prio_bits" = "5";
-            pub const @"cpu.mpu" = "1";
-            pub const @"cpu.fpu" = "0";
-            pub const @"cpu.revision" = "r0p0";
-            pub const @"cpu.vendor_systick_config" = "0";
-            pub const @"cpu.endian" = "little";
-            pub const @"cpu.name" = "CM3";
-        };
-
-        pub const VectorTable = extern struct {
-            const Handler = micro.interrupt.Handler;
-            const unhandled = micro.interrupt.unhandled;
-
-            initial_stack_pointer: u32,
-            Reset: Handler = unhandled,
-            NMI: Handler = unhandled,
-            HardFault: Handler = unhandled,
-            MemManageFault: Handler = unhandled,
-            BusFault: Handler = unhandled,
-            UsageFault: Handler = unhandled,
-            reserved5: [4]u32 = undefined,
-            SVCall: Handler = unhandled,
-            DebugMonitor: Handler = unhandled,
-            reserved11: [1]u32 = undefined,
-            PendSV: Handler = unhandled,
-            SysTick: Handler = unhandled,
-            WDT: Handler = unhandled,
-            TIMER0: Handler = unhandled,
-            TIMER1: Handler = unhandled,
-            TIMER2: Handler = unhandled,
-            TIMER3: Handler = unhandled,
-            UART0: Handler = unhandled,
-            UART1: Handler = unhandled,
-            UART2: Handler = unhandled,
-            UART3: Handler = unhandled,
-            PWM1: Handler = unhandled,
-            I2C0: Handler = unhandled,
-            I2C1: Handler = unhandled,
-            I2C2: Handler = unhandled,
-            SPI: Handler = unhandled,
-            SSP0: Handler = unhandled,
-            SSP1: Handler = unhandled,
-            reserved30: [1]u32 = undefined,
-            RTC: Handler = unhandled,
-            EINT0: Handler = unhandled,
-            reserved33: [3]u32 = undefined,
-            ADC: Handler = unhandled,
-            reserved37: [1]u32 = undefined,
-            USB: Handler = unhandled,
-            CAN: Handler = unhandled,
-            DMA: Handler = unhandled,
-            I2S: Handler = unhandled,
-            ENET: Handler = unhandled,
-            RIT: Handler = unhandled,
-            MCPWM: Handler = unhandled,
-            QEI: Handler = unhandled,
-            reserved46: [2]u32 = undefined,
-            CANActivity: Handler = unhandled,
-        };
-
-        pub const peripherals = struct {
-            ///  General Purpose I/O
-            pub const GPIO = @ptrCast(*volatile types.GPIO, 0x2009c000);
-            ///  Watchdog Timer (WDT)
-            pub const WDT = @ptrCast(*volatile types.WDT, 0x40000000);
-            ///  Timer0/1/2/3
-            pub const TIMER0 = @ptrCast(*volatile types.TIMER0, 0x40004000);
-            ///  Timer0/1/2/3
-            pub const TIMER1 = @ptrCast(*volatile types.TIMER0, 0x40008000);
-            ///  UART0/2/3
-            pub const UART0 = @ptrCast(*volatile types.UART0, 0x4000c000);
-            ///  UART1
-            pub const UART1 = @ptrCast(*volatile types.UART1, 0x40010000);
-            ///  Pulse Width Modulators (PWM1)
-            pub const PWM1 = @ptrCast(*volatile types.PWM1, 0x40018000);
-            ///  I2C bus interface
-            pub const I2C0 = @ptrCast(*volatile types.I2C0, 0x4001c000);
-            ///  SPI
-            pub const SPI = @ptrCast(*volatile types.SPI, 0x40020000);
-            ///  Real Time Clock (RTC)
-            pub const RTC = @ptrCast(*volatile types.RTC, 0x40024000);
-            ///  GPIO
-            pub const GPIOINT = @ptrCast(*volatile types.GPIOINT, 0x40028080);
-            ///  Pin connect block
-            pub const PINCONNECT = @ptrCast(*volatile types.PINCONNECT, 0x4002c000);
-            ///  SSP1 controller
-            pub const SSP1 = @ptrCast(*volatile types.SSP1, 0x40030000);
-            ///  Analog-to-Digital Converter (ADC)
-            pub const ADC = @ptrCast(*volatile types.ADC, 0x40034000);
-            ///  CAN acceptance filter RAM
-            pub const CANAFRAM = @ptrCast(*volatile types.CANAFRAM, 0x40038000);
-            ///  CAN controller acceptance filter
-            pub const CANAF = @ptrCast(*volatile types.CANAF, 0x4003c000);
-            ///  Central CAN controller
-            pub const CCAN = @ptrCast(*volatile types.CCAN, 0x40040000);
-            ///  CAN1 controller
-            pub const CAN1 = @ptrCast(*volatile types.CAN1, 0x40044000);
-            ///  CAN1 controller
-            pub const CAN2 = @ptrCast(*volatile types.CAN1, 0x40048000);
-            ///  I2C bus interface
-            pub const I2C1 = @ptrCast(*volatile types.I2C0, 0x4005c000);
-            ///  SSP controller
-            pub const SSP0 = @ptrCast(*volatile types.SSP1, 0x40088000);
-            ///  Digital-to-Analog Converter (DAC)
-            pub const DAC = @ptrCast(*volatile types.DAC, 0x4008c000);
-            ///  Timer0/1/2/3
-            pub const TIMER2 = @ptrCast(*volatile types.TIMER0, 0x40090000);
-            ///  Timer0/1/2/3
-            pub const TIMER3 = @ptrCast(*volatile types.TIMER0, 0x40094000);
-            ///  UART0/2/3
-            pub const UART2 = @ptrCast(*volatile types.UART0, 0x40098000);
-            ///  UART0/2/3
-            pub const UART3 = @ptrCast(*volatile types.UART0, 0x4009c000);
-            ///  I2C bus interface
-            pub const I2C2 = @ptrCast(*volatile types.I2C0, 0x400a0000);
-            ///  I2S interface
-            pub const I2S = @ptrCast(*volatile types.I2S, 0x400a8000);
-            ///  Repetitive Interrupt Timer (RIT)
-            pub const RITIMER = @ptrCast(*volatile types.RITIMER, 0x400b0000);
-            ///  Motor Control PWM
-            pub const MCPWM = @ptrCast(*volatile types.MCPWM, 0x400b8000);
-            ///  Quadrature Encoder Interface (QEI)
-            pub const QEI = @ptrCast(*volatile types.QEI, 0x400bc000);
-            ///  System and clock control
-            pub const SYSCON = @ptrCast(*volatile types.SYSCON, 0x400fc000);
-            ///  Ethernet
-            pub const EMAC = @ptrCast(*volatile types.EMAC, 0x50000000);
-            ///  General purpose DMA controller
-            pub const GPDMA = @ptrCast(*volatile types.GPDMA, 0x50004000);
-            ///  USB device/host/OTG controller
-            pub const USB = @ptrCast(*volatile types.USB, 0x50008000);
-        };
-    };
-};
-
-pub const types = struct {
-    ///  Watchdog Timer (WDT)
-    pub const WDT = extern struct {
-        ///  Watchdog mode register. This register determines the basic mode and status of the Watchdog Timer.
-        MOD: mmio.Mmio(packed struct(u32) {
-            ///  Watchdog enable bit. This bit is Set Only.
-            WDEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The watchdog timer is stopped.
-                    STOP = 0x0,
-                    ///  The watchdog timer is running.
-                    RUN = 0x1,
-                },
-            },
-            ///  Watchdog reset enable bit. This bit is Set Only. See Table 652.
-            WDRESET: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A watchdog timeout will not cause a chip reset.
-                    NORESET = 0x0,
-                    ///  A watchdog timeout will cause a chip reset.
-                    RESET = 0x1,
-                },
-            },
-            ///  Watchdog time-out flag. Set when the watchdog timer times out, cleared by software.
-            WDTOF: u1,
-            ///  Watchdog interrupt flag. Cleared by software.
-            WDINT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u28,
-        }),
-        ///  Watchdog timer constant register. The value in this register determines the time-out value.
-        TC: mmio.Mmio(packed struct(u32) {
-            ///  Watchdog time-out interval.
-            Count: u32,
-        }),
-        ///  Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in WDTC.
-        FEED: mmio.Mmio(packed struct(u32) {
-            ///  Feed value should be 0xAA followed by 0x55.
-            Feed: u8,
-            padding: u24,
-        }),
-        ///  Watchdog timer value register. This register reads out the current value of the Watchdog timer.
-        TV: mmio.Mmio(packed struct(u32) {
-            ///  Counter timer value.
-            Count: u32,
-        }),
-        ///  Watchdog clock select register.
-        CLKSEL: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u30,
-            ///  If this bit is set to one writing to this register does not affect bit 0. The clock source can only be changed by first clearing this bit, then writing the new value of bit 0.
-            LOCK: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This bit is set to 0 on any reset. It cannot be cleared by software.
-                    UNLOCKED = 0x0,
-                    ///  Software can set this bit to 1 at any time. Once WDLOCK is set, the bits of this register cannot be modified.
-                    LOCKED = 0x1,
-                },
-            },
-        }),
-    };
-
-    ///  Timer0/1/2/3
-    pub const TIMER0 = extern struct {
-        ///  Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending.
-        IR: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt flag for match channel 0.
-            MR0INT: u1,
-            ///  Interrupt flag for match channel 1.
-            MR1INT: u1,
-            ///  Interrupt flag for match channel 2.
-            MR2INT: u1,
-            ///  Interrupt flag for match channel 3.
-            MR3INT: u1,
-            ///  Interrupt flag for capture channel 0 event.
-            CR0INT: u1,
-            ///  Interrupt flag for capture channel 1 event.
-            CR1INT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u26,
-        }),
-        ///  Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR.
-        TCR: mmio.Mmio(packed struct(u32) {
-            ///  When one, the Timer Counter and Prescale Counter are enabled for counting. When zero, the counters are disabled.
-            CEN: u1,
-            ///  When one, the Timer Counter and the Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until TCR[1] is returned to zero.
-            CRST: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u30,
-        }),
-        ///  Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
-        TC: mmio.Mmio(packed struct(u32) {
-            ///  Timer counter value.
-            TC: u32,
-        }),
-        ///  Prescale Register. When the Prescale Counter (PC) is equal to this value, the next clock increments the TC and clears the PC.
-        PR: mmio.Mmio(packed struct(u32) {
-            ///  Prescale counter maximum value.
-            PM: u32,
-        }),
-        ///  Prescale Counter. The 32 bit PC is a counter which is incremented to the value stored in PR. When the value in PR is reached, the TC is incremented and the PC is cleared. The PC is observable and controllable through the bus interface.
-        PC: mmio.Mmio(packed struct(u32) {
-            ///  Prescale counter value.
-            PC: u32,
-        }),
-        ///  Match Control Register. The MCR is used to control if an interrupt is generated and if the TC is reset when a Match occurs.
-        MCR: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt on MR0
-            MR0I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt is generated when MR0 matches the value in the TC.
-                    INTERRUPT_IS_GENERAT = 0x1,
-                    ///  Interrupt is disabled
-                    INTERRUPT_IS_DISABLE = 0x0,
-                },
-            },
-            ///  Reset on MR0
-            MR0R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  TC will be reset if MR0 matches it.
-                    TC_WILL_BE_RESET_IF_ = 0x1,
-                    ///  Feature disabled.
-                    FEATURE_DISABLED_ = 0x0,
-                },
-            },
-            ///  Stop on MR0
-            MR0S: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  TC and PC will be stopped and TCR[0] will be set to 0 if MR0 matches the TC.
-                    TC_AND_PC_WILL_BE_ST = 0x1,
-                    ///  Feature disabled.
-                    FEATURE_DISABLED_ = 0x0,
-                },
-            },
-            ///  Interrupt on MR1
-            MR1I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt is generated when MR1 matches the value in the TC.
-                    INTERRUPT_IS_GENERAT = 0x1,
-                    ///  Interrupt is disabled.
-                    INTERRUPT_IS_DISABLE = 0x0,
-                },
-            },
-            ///  Reset on MR1
-            MR1R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  TC will be reset if MR1 matches it.
-                    TC_WILL_BE_RESET_IF_ = 0x1,
-                    ///  Feature disabled.
-                    FEATURE_DISABLED_ = 0x0,
-                },
-            },
-            ///  Stop on MR1
-            MR1S: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  TC and PC will be stopped and TCR[0] will be set to 0 if MR1 matches the TC.
-                    TC_AND_PC_WILL_BE_ST = 0x1,
-                    ///  Feature disabled.
-                    FEATURE_DISABLED_ = 0x0,
-                },
-            },
-            ///  Interrupt on MR2
-            MR2I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt is generated when MR2 matches the value in the TC.
-                    INTERRUPT_IS_GENERAT = 0x1,
-                    ///  Interrupt is disabled
-                    INTERRUPT_IS_DISABLE = 0x0,
-                },
-            },
-            ///  Reset on MR2
-            MR2R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  TC will be reset if MR2 matches it.
-                    TC_WILL_BE_RESET_IF_ = 0x1,
-                    ///  Feature disabled.
-                    FEATURE_DISABLED_ = 0x0,
-                },
-            },
-            ///  Stop on MR2.
-            MR2S: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  TC and PC will be stopped and TCR[0] will be set to 0 if MR2 matches the TC
-                    TC_AND_PC_WILL_BE_ST = 0x1,
-                    ///  Feature disabled.
-                    FEATURE_DISABLED_ = 0x0,
-                },
-            },
-            ///  Interrupt on MR3
-            MR3I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt is generated when MR3 matches the value in the TC.
-                    INTERRUPT_IS_GENERAT = 0x1,
-                    ///  This interrupt is disabled
-                    THIS_INTERRUPT_IS_DI = 0x0,
-                },
-            },
-            ///  Reset on MR3
-            MR3R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  TC will be reset if MR3 matches it.
-                    TC_WILL_BE_RESET_IF_ = 0x1,
-                    ///  Feature disabled.
-                    FEATURE_DISABLED_ = 0x0,
-                },
-            },
-            ///  Stop on MR3
-            MR3S: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  TC and PC will be stopped and TCR[0] will be set to 0 if MR3 matches the TC.
-                    TC_AND_PC_WILL_BE_ST = 0x1,
-                    ///  Feature disabled.
-                    FEATURE_DISABLED_ = 0x0,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u20,
-        }),
-        reserved40: [16]u8,
-        ///  Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place.
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Capture on CAPn.0 rising edge
-            CAP0RE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A sequence of 0 then 1 on CAPn.0 will cause CR0 to be loaded with the contents of TC.
-                    ENABLE = 0x1,
-                    ///  This feature is disabled.
-                    DISABLE = 0x0,
-                },
-            },
-            ///  Capture on CAPn.0 falling edge
-            CAP0FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A sequence of 1 then 0 on CAPn.0 will cause CR0 to be loaded with the contents of TC.
-                    ENABLE = 0x1,
-                    ///  This feature is disabled.
-                    DISABLE = 0x0,
-                },
-            },
-            ///  Interrupt on CAPn.0 event
-            CAP0I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A CR0 load due to a CAPn.0 event will generate an interrupt.
-                    ENABLE = 0x1,
-                    ///  This feature is disabled.
-                    DISABLE = 0x0,
-                },
-            },
-            ///  Capture on CAPn.1 rising edge
-            CAP1RE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A sequence of 0 then 1 on CAPn.1 will cause CR1 to be loaded with the contents of TC.
-                    ENABLE = 0x1,
-                    ///  This feature is disabled.
-                    DISABLE = 0x0,
-                },
-            },
-            ///  Capture on CAPn.1 falling edge
-            CAP1FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A sequence of 1 then 0 on CAPn.1 will cause CR1 to be loaded with the contents of TC.
-                    ENABLE = 0x1,
-                    ///  This feature is disabled.
-                    DISABLE = 0x0,
-                },
-            },
-            ///  Interrupt on CAPn.1 event
-            CAP1I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A CR1 load due to a CAPn.1 event will generate an interrupt.
-                    ENABLE = 0x1,
-                    ///  This feature is disabled.
-                    DISABLE = 0x0,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u26,
-        }),
-        reserved60: [16]u8,
-        ///  External Match Register. The EMR controls the external match pins.
-        EMR: mmio.Mmio(packed struct(u32) {
-            ///  External Match 0. When a match occurs between the TC and MR0, this bit can either toggle, go low, go high, or do nothing, depending on bits 5:4 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).
-            EM0: u1,
-            ///  External Match 1. When a match occurs between the TC and MR1, this bit can either toggle, go low, go high, or do nothing, depending on bits 7:6 of this register. This bit can be driven onto a MATn.1 pin, in a positive-logic manner (0 = low, 1 = high).
-            EM1: u1,
-            ///  External Match 2. When a match occurs between the TC and MR2, this bit can either toggle, go low, go high, or do nothing, depending on bits 9:8 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).
-            EM2: u1,
-            ///  External Match 3. When a match occurs between the TC and MR3, this bit can either toggle, go low, go high, or do nothing, depending on bits 11:10 of this register. This bit can be driven onto a MATn.0 pin, in a positive-logic manner (0 = low, 1 = high).
-            EM3: u1,
-            ///  External Match Control 0. Determines the functionality of External Match 0.
-            EMC0: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Do Nothing.
-                    DO_NOTHING_ = 0x0,
-                    ///  Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
-                    CLEAR_THE_CORRESPOND = 0x1,
-                    ///  Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
-                    SET_THE_CORRESPONDIN = 0x2,
-                    ///  Toggle the corresponding External Match bit/output.
-                    TOGGLE_THE_CORRESPON = 0x3,
-                },
-            },
-            ///  External Match Control 1. Determines the functionality of External Match 1.
-            EMC1: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Do Nothing.
-                    DO_NOTHING_ = 0x0,
-                    ///  Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
-                    CLEAR_THE_CORRESPOND = 0x1,
-                    ///  Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
-                    SET_THE_CORRESPONDIN = 0x2,
-                    ///  Toggle the corresponding External Match bit/output.
-                    TOGGLE_THE_CORRESPON = 0x3,
-                },
-            },
-            ///  External Match Control 2. Determines the functionality of External Match 2.
-            EMC2: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Do Nothing.
-                    DO_NOTHING_ = 0x0,
-                    ///  Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
-                    CLEAR_THE_CORRESPOND = 0x1,
-                    ///  Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
-                    SET_THE_CORRESPONDIN = 0x2,
-                    ///  Toggle the corresponding External Match bit/output.
-                    TOGGLE_THE_CORRESPON = 0x3,
-                },
-            },
-            ///  External Match Control 3. Determines the functionality of External Match 3.
-            EMC3: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Do Nothing.
-                    DO_NOTHING_ = 0x0,
-                    ///  Clear the corresponding External Match bit/output to 0 (MATn.m pin is LOW if pinned out).
-                    CLEAR_THE_CORRESPOND = 0x1,
-                    ///  Set the corresponding External Match bit/output to 1 (MATn.m pin is HIGH if pinned out).
-                    SET_THE_CORRESPONDIN = 0x2,
-                    ///  Toggle the corresponding External Match bit/output.
-                    TOGGLE_THE_CORRESPON = 0x3,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u20,
-        }),
-        reserved112: [48]u8,
-        ///  Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
-        CTCR: mmio.Mmio(packed struct(u32) {
-            ///  Counter/Timer Mode This field selects which rising PCLK edges can increment Timer's Prescale Counter (PC), or clear PC and increment Timer Counter (TC). Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale Register.
-            CTMODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Timer Mode: every rising PCLK edge
-                    TIMER_MODE_EVERY_RI = 0x0,
-                    ///  Counter Mode: TC is incremented on rising edges on the CAP input selected by bits 3:2.
-                    RISING = 0x1,
-                    ///  Counter Mode: TC is incremented on falling edges on the CAP input selected by bits 3:2.
-                    FALLING = 0x2,
-                    ///  Counter Mode: TC is incremented on both edges on the CAP input selected by bits 3:2.
-                    DUALEDGE = 0x3,
-                },
-            },
-            ///  Count Input Select When bits 1:0 in this register are not 00, these bits select which CAP pin is sampled for clocking. Note: If Counter mode is selected for a particular CAPn input in the TnCTCR, the 3 bits for that input in the Capture Control Register (TnCCR) must be programmed as 000. However, capture and/or interrupt can be selected for the other 3 CAPn inputs in the same timer.
-            CINSEL: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CAPn.0 for TIMERn
-                    CAPN_0_FOR_TIMERN = 0x0,
-                    ///  CAPn.1 for TIMERn
-                    CAPN_1_FOR_TIMERN = 0x1,
-                    _,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u28,
-        }),
-    };
-
-    ///  General Purpose I/O
-    pub const GPIO = struct {};
-
-    ///  UART0/2/3
-    pub const UART0 = extern struct {
-        ///  Receiver Buffer Register. Contains the next received character to be read (DLAB =0).
-        RBR: mmio.Mmio(packed struct(u32) {
-            ///  The UARTn Receiver Buffer Register contains the oldest received byte in the UARTn Rx FIFO.
-            RBR: u8,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider (DLAB =1).
-        DLM: mmio.Mmio(packed struct(u32) {
-            ///  The UARTn Divisor Latch MSB Register, along with the U0DLL register, determines the baud rate of the UARTn.
-            DLMSB: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  Interrupt ID Register. Identifies which interrupt(s) are pending.
-        IIR: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt status. Note that UnIIR[0] is active low. The pending interrupt can be determined by evaluating UnIIR[3:1].
-            INTSTATUS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  At least one interrupt is pending.
-                    AT_LEAST_ONE_INTERRU = 0x0,
-                    ///  No interrupt is pending.
-                    NO_INTERRUPT_IS_PEND = 0x1,
-                },
-            },
-            ///  Interrupt identification. UnIER[3:1] identifies an interrupt corresponding to the UARTn Rx or TX FIFO. All other combinations of UnIER[3:1] not listed below are reserved (000,100,101,111).
-            INTID: packed union {
-                raw: u3,
-                value: enum(u3) {
-                    ///  1 - Receive Line Status (RLS).
-                    @"1_RECEIVE_LINE_S" = 0x3,
-                    ///  2a - Receive Data Available (RDA).
-                    @"2A__RECEIVE_DATA_AV" = 0x2,
-                    ///  2b - Character Time-out Indicator (CTI).
-                    @"2B__CHARACTER_TIME_" = 0x6,
-                    ///  3 - THRE Interrupt
-                    @"3_THRE_INTERRUPT" = 0x1,
-                    _,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  Copies of UnFCR[0].
-            FIFOENABLE: u2,
-            ///  End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
-            ABEOINT: u1,
-            ///  Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.
-            ABTOINT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u22,
-        }),
-        ///  Line Control Register. Contains controls for frame formatting and break generation.
-        LCR: mmio.Mmio(packed struct(u32) {
-            ///  Word Length Select.
-            WLS: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  5-bit character length
-                    @"5_BIT_CHARACTER_LENG" = 0x0,
-                    ///  6-bit character length
-                    @"6_BIT_CHARACTER_LENG" = 0x1,
-                    ///  7-bit character length
-                    @"7_BIT_CHARACTER_LENG" = 0x2,
-                    ///  8-bit character length
-                    @"8_BIT_CHARACTER_LENG" = 0x3,
-                },
-            },
-            ///  Stop Bit Select
-            SBS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  1 stop bit.
-                    @"1_STOP_BIT_" = 0x0,
-                    ///  2 stop bits (1.5 if UnLCR[1:0]=00).
-                    @"2_STOP_BITS_1_5_IF_" = 0x1,
-                },
-            },
-            ///  Parity Enable.
-            PE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable parity generation and checking.
-                    DISABLE_PARITY_GENER = 0x0,
-                    ///  Enable parity generation and checking.
-                    ENABLE_PARITY_GENERA = 0x1,
-                },
-            },
-            ///  Parity Select
-            PS: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
-                    ODD_PARITY_NUMBER_O = 0x0,
-                    ///  Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.
-                    EVEN_PARITY_NUMBER_ = 0x1,
-                    ///  Forced 1 stick parity.
-                    FORCED_1_STICK_PARIT = 0x2,
-                    ///  Forced 0 stick parity.
-                    FORCED_0_STICK_PARIT = 0x3,
-                },
-            },
-            ///  Break Control
-            BC: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable break transmission.
-                    DISABLE_BREAK_TRANSM = 0x0,
-                    ///  Enable break transmission. Output pin UARTn TXD is forced to logic 0 when UnLCR[6] is active high.
-                    ENABLE_BREAK_TRANSMI = 0x1,
-                },
-            },
-            ///  Divisor Latch Access Bit
-            DLAB: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable access to Divisor Latches.
-                    DISABLE_ACCESS_TO_DI = 0x0,
-                    ///  Enable access to Divisor Latches.
-                    ENABLE_ACCESS_TO_DIV = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        reserved20: [4]u8,
-        ///  Line Status Register. Contains flags for transmit and receive status, including line errors.
-        LSR: mmio.Mmio(packed struct(u32) {
-            ///  Receiver Data Ready. UnLSR[0] is set when the UnRBR holds an unread character and is cleared when the UARTn RBR FIFO is empty.
-            RDR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The UARTn receiver FIFO is empty.
-                    EMPTY = 0x0,
-                    ///  The UARTn receiver FIFO is not empty.
-                    NOTEMPTY = 0x1,
-                },
-            },
-            ///  Overrun Error. The overrun error condition is set as soon as it occurs. An UnLSR read clears UnLSR[1]. UnLSR[1] is set when UARTn RSR has a new character assembled and the UARTn RBR FIFO is full. In this case, the UARTn RBR FIFO will not be overwritten and the character in the UARTn RSR will be lost.
-            OE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Overrun error status is inactive.
-                    INACTIVE = 0x0,
-                    ///  Overrun error status is active.
-                    ACTIVE = 0x1,
-                },
-            },
-            ///  Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An UnLSR read clears UnLSR[2]. Time of parity error detection is dependent on UnFCR[0]. Note: A parity error is associated with the character at the top of the UARTn RBR FIFO.
-            PE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Parity error status is inactive.
-                    INACTIVE = 0x0,
-                    ///  Parity error status is active.
-                    ACTIVE = 0x1,
-                },
-            },
-            ///  Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An UnLSR read clears UnLSR[3]. The time of the framing error detection is dependent on UnFCR[0]. Upon detection of a framing error, the Rx will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UARTn RBR FIFO.
-            FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Framing error status is inactive.
-                    INACTIVE = 0x0,
-                    ///  Framing error status is active.
-                    ACTIVE = 0x1,
-                },
-            },
-            ///  Break Interrupt. When RXDn is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXDn goes to marking state (all ones). An UnLSR read clears this status bit. The time of break detection is dependent on UnFCR[0]. Note: The break interrupt is associated with the character at the top of the UARTn RBR FIFO.
-            BI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Break interrupt status is inactive.
-                    INACTIVE = 0x0,
-                    ///  Break interrupt status is active.
-                    ACTIVE = 0x1,
-                },
-            },
-            ///  Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UARTn THR and is cleared on a UnTHR write.
-            THRE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  UnTHR contains valid data.
-                    VALIDDATA = 0x0,
-                    ///  UnTHR is empty.
-                    EMPTY = 0x1,
-                },
-            },
-            ///  Transmitter Empty. TEMT is set when both UnTHR and UnTSR are empty; TEMT is cleared when either the UnTSR or the UnTHR contain valid data.
-            TEMT: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  UnTHR and/or the UnTSR contains valid data.
-                    VALIDDATA = 0x0,
-                    ///  UnTHR and the UnTSR are empty.
-                    EMPTY = 0x1,
-                },
-            },
-            ///  Error in RX FIFO . UnLSR[7] is set when a character with a Rx error such as framing error, parity error or break interrupt, is loaded into the UnRBR. This bit is cleared when the UnLSR register is read and there are no subsequent errors in the UARTn FIFO.
-            RXFE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  UnRBR contains no UARTn RX errors or UnFCR[0]=0.
-                    NOERROR = 0x0,
-                    ///  UARTn RBR contains at least one UARTn RX error.
-                    ERRORS = 0x1,
-                },
-            },
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        reserved28: [4]u8,
-        ///  Scratch Pad Register. 8-bit temporary storage for software.
-        SCR: mmio.Mmio(packed struct(u32) {
-            ///  A readable, writable byte.
-            PAD: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  Auto-baud Control Register. Contains controls for the auto-baud feature.
-        ACR: mmio.Mmio(packed struct(u32) {
-            ///  Start bit. This bit is automatically cleared after auto-baud completion.
-            START: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Auto-baud stop (auto-baud is not running).
-                    AUTO_BAUD_STOP_AUTO = 0x0,
-                    ///  Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.
-                    AUTO_BAUD_START_AUT = 0x1,
-                },
-            },
-            ///  Auto-baud mode select bit.
-            MODE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Mode 0.
-                    MODE_0_ = 0x0,
-                    ///  Mode 1.
-                    MODE_1_ = 0x1,
-                },
-            },
-            ///  Restart bit.
-            AUTORESTART: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No restart.
-                    NO_RESTART_ = 0x0,
-                    ///  Restart in case of time-out (counter restarts at next UARTn Rx falling edge)
-                    RESTART_IN_CASE_OF_T = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u5,
-            ///  End of auto-baud interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.
-            ABEOINTCLR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No impact.
-                    NO_IMPACT_ = 0x0,
-                    ///  Clear the corresponding interrupt in the IIR.
-                    CLEAR_THE_CORRESPOND = 0x1,
-                },
-            },
-            ///  Auto-baud time-out interrupt clear bit (write-only accessible). Writing a 1 will clear the corresponding interrupt in the UnIIR. Writing a 0 has no impact.
-            ABTOINTCLR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No impact.
-                    NO_IMPACT_ = 0x0,
-                    ///  Clear the corresponding interrupt in the IIR.
-                    CLEAR_THE_CORRESPOND = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u22,
-        }),
-        reserved40: [4]u8,
-        ///  Fractional Divider Register. Generates a clock input for the baud rate divider.
-        FDR: mmio.Mmio(packed struct(u32) {
-            ///  Baud-rate generation pre-scaler divisor value. If this field is 0, fractional baud-rate generator will not impact the UARTn baudrate.
-            DIVADDVAL: u4,
-            ///  Baud-rate pre-scaler multiplier value. This field must be greater or equal 1 for UARTn to operate properly, regardless of whether the fractional baud-rate generator is used or not.
-            MULVAL: u4,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        reserved48: [4]u8,
-        ///  Transmit Enable Register. Turns off UART transmitter for use with software flow control.
-        TER: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u7,
-            ///  When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit is cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software implementing software-handshaking can clear this bit when it receives an XOFF character (DC3). Software can set this bit again when it receives an XON (DC1) character.
-            TXEN: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        reserved76: [24]u8,
-        ///  RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
-        RS485CTRL: mmio.Mmio(packed struct(u32) {
-            ///  NMM enable.
-            NMMEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  RS-485/EIA-485 Normal Multidrop Mode (NMM) is disabled.
-                    DISABLED = 0x0,
-                    ///  RS-485/EIA-485 Normal Multidrop Mode (NMM) is enabled. In this mode, an address is detected when a received byte has the parity bit = 1, generating a received data interrupt. See Section 18.6.16 RS-485/EIA-485 modes of operation.
-                    ENABLED = 0x1,
-                },
-            },
-            ///  Receiver enable.
-            RXDIS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The receiver is enabled.
-                    ENABLED = 0x0,
-                    ///  The receiver is disabled.
-                    DISABLED = 0x1,
-                },
-            },
-            ///  AAD enable.
-            AADEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Auto Address Detect (AAD) is disabled.
-                    DISABLED = 0x0,
-                    ///  Auto Address Detect (AAD) is enabled.
-                    ENABLED = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  Direction control enable.
-            DCTRL: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable Auto Direction Control.
-                    DISABLE_AUTO_DIRECTI = 0x0,
-                    ///  Enable Auto Direction Control.
-                    ENABLE_AUTO_DIRECTIO = 0x1,
-                },
-            },
-            ///  Direction control pin polarity. This bit reverses the polarity of the direction control signal on the Un_OE pin.
-            OINV: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.
-                    DIRLOW = 0x0,
-                    ///  The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.
-                    DIRHIGH = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u26,
-        }),
-        ///  RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
-        RS485ADRMATCH: mmio.Mmio(packed struct(u32) {
-            ///  Contains the address match value.
-            ADRMATCH: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  RS-485/EIA-485 direction control delay.
-        RS485DLY: mmio.Mmio(packed struct(u32) {
-            ///  Contains the direction control (UnOE) delay value. This register works in conjunction with an 8-bit counter.
-            DLY: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-    };
-
-    ///  UART1
-    pub const UART1 = extern struct {
-        ///  DLAB =0 Receiver Buffer Register. Contains the next received character to be read.
-        RBR: mmio.Mmio(packed struct(u32) {
-            ///  The UART1 Receiver Buffer Register contains the oldest received byte in the UART1 RX FIFO.
-            RBR: u8,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  DLAB =1. Divisor Latch MSB. Most significant byte of the baud rate divisor value. The full divisor is used to generate a baud rate from the fractional rate divider.
-        DLM: mmio.Mmio(packed struct(u32) {
-            ///  The UART1 Divisor Latch MSB Register, along with the U1DLL register, determines the baud rate of the UART1.
-            DLMSB: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  Interrupt ID Register. Identifies which interrupt(s) are pending.
-        IIR: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt status. Note that IIR[0] is active low. The pending interrupt can be determined by evaluating IIR[3:1].
-            INTSTATUS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  At least one interrupt is pending.
-                    AT_LEAST_ONE_INTERRU = 0x0,
-                    ///  No interrupt is pending.
-                    NO_INTERRUPT_IS_PEND = 0x1,
-                },
-            },
-            ///  Interrupt identification. IER[3:1] identifies an interrupt corresponding to the UART1 Rx or TX FIFO. All other combinations of IER[3:1] not listed below are reserved (100,101,111).
-            INTID: packed union {
-                raw: u3,
-                value: enum(u3) {
-                    ///  1 - Receive Line Status (RLS).
-                    RLS = 0x3,
-                    ///  2a - Receive Data Available (RDA).
-                    RDA = 0x2,
-                    ///  2b - Character Time-out Indicator (CTI).
-                    CTI = 0x6,
-                    ///  3 - THRE Interrupt.
-                    THRE = 0x1,
-                    ///  4 - Modem Interrupt.
-                    MODEM = 0x0,
-                    _,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u2,
-            ///  Copies of FCR[0].
-            FIFOENABLE: u2,
-            ///  End of auto-baud interrupt. True if auto-baud has finished successfully and interrupt is enabled.
-            ABEOINT: u1,
-            ///  Auto-baud time-out interrupt. True if auto-baud has timed out and interrupt is enabled.
-            ABTOINT: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u22,
-        }),
-        ///  Line Control Register. Contains controls for frame formatting and break generation.
-        LCR: mmio.Mmio(packed struct(u32) {
-            ///  Word Length Select.
-            WLS: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  5-bit character length.
-                    @"5_BIT_CHARACTER_LENG" = 0x0,
-                    ///  6-bit character length.
-                    @"6_BIT_CHARACTER_LENG" = 0x1,
-                    ///  7-bit character length.
-                    @"7_BIT_CHARACTER_LENG" = 0x2,
-                    ///  8-bit character length.
-                    @"8_BIT_CHARACTER_LENG" = 0x3,
-                },
-            },
-            ///  Stop Bit Select.
-            SBS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  1 stop bit.
-                    @"1_STOP_BIT_" = 0x0,
-                    ///  2 stop bits (1.5 if LCR[1:0]=00).
-                    @"2_STOP_BITS_1_5_IF_" = 0x1,
-                },
-            },
-            ///  Parity Enable.
-            PE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable parity generation and checking.
-                    DISABLE_PARITY_GENER = 0x0,
-                    ///  Enable parity generation and checking.
-                    ENABLE_PARITY_GENERA = 0x1,
-                },
-            },
-            ///  Parity Select.
-            PS: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Odd parity. Number of 1s in the transmitted character and the attached parity bit will be odd.
-                    ODD_PARITY_NUMBER_O = 0x0,
-                    ///  Even Parity. Number of 1s in the transmitted character and the attached parity bit will be even.
-                    EVEN_PARITY_NUMBER_ = 0x1,
-                    ///  Forced 1 stick parity.
-                    FORCED1STICK_PAR = 0x2,
-                    ///  Forced 0 stick parity.
-                    FORCED0STICK_PAR = 0x3,
-                },
-            },
-            ///  Break Control.
-            BC: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable break transmission.
-                    DISABLE_BREAK_TRANSM = 0x0,
-                    ///  Enable break transmission. Output pin UART1 TXD is forced to logic 0 when LCR[6] is active high.
-                    ENABLE_BREAK_TRANSMI = 0x1,
-                },
-            },
-            ///  Divisor Latch Access Bit (DLAB)
-            DLAB: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable access to Divisor Latches.
-                    DISABLE_ACCESS_TO_DI = 0x0,
-                    ///  Enable access to Divisor Latches.
-                    ENABLE_ACCESS_TO_DIV = 0x1,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  Modem Control Register. Contains controls for flow control handshaking and loopback mode.
-        MCR: mmio.Mmio(packed struct(u32) {
-            ///  DTR Control. Source for modem output pin, DTR. This bit reads as 0 when modem loopback mode is active.
-            DTRCTRL: u1,
-            ///  RTS Control. Source for modem output pin RTS. This bit reads as 0 when modem loopback mode is active.
-            RTSCTRL: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u2,
-            ///  Loopback Mode Select. The modem loopback mode provides a mechanism to perform diagnostic loopback testing. Serial data from the transmitter is connected internally to serial input of the receiver. Input pin, RXD1, has no effect on loopback and output pin, TXD1 is held in marking state. The 4 modem inputs (CTS, DSR, RI and DCD) are disconnected externally. Externally, the modem outputs (RTS, DTR) are set inactive. Internally, the 4 modem outputs are connected to the 4 modem inputs. As a result of these connections, the upper 4 bits of the MSR will be driven by the lower 4 bits of the MCR rather than the 4 modem inputs in normal mode. This permits modem status interrupts to be generated in loopback mode by writing the lower 4 bits of MCR.
-            LMS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable modem loopback mode.
-                    DISABLE_MODEM_LOOPBA = 0x0,
-                    ///  Enable modem loopback mode.
-                    ENABLE_MODEM_LOOPBAC = 0x1,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u1,
-            ///  RTS enable.
-            RTSEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable auto-rts flow control.
-                    DISABLE_AUTO_RTS_FLO = 0x0,
-                    ///  Enable auto-rts flow control.
-                    ENABLE_AUTO_RTS_FLOW = 0x1,
-                },
-            },
-            ///  CTS enable.
-            CTSEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable auto-cts flow control.
-                    DISABLE_AUTO_CTS_FLO = 0x0,
-                    ///  Enable auto-cts flow control.
-                    ENABLE_AUTO_CTS_FLOW = 0x1,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  Line Status Register. Contains flags for transmit and receive status, including line errors.
-        LSR: mmio.Mmio(packed struct(u32) {
-            ///  Receiver Data Ready. LSR[0] is set when the RBR holds an unread character and is cleared when the UART1 RBR FIFO is empty.
-            RDR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The UART1 receiver FIFO is empty.
-                    EMPTY = 0x0,
-                    ///  The UART1 receiver FIFO is not empty.
-                    NOTEMPTY = 0x1,
-                },
-            },
-            ///  Overrun Error. The overrun error condition is set as soon as it occurs. An LSR read clears LSR[1]. LSR[1] is set when UART1 RSR has a new character assembled and the UART1 RBR FIFO is full. In this case, the UART1 RBR FIFO will not be overwritten and the character in the UART1 RSR will be lost.
-            OE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Overrun error status is inactive.
-                    INACTIVE = 0x0,
-                    ///  Overrun error status is active.
-                    ACTIVE = 0x1,
-                },
-            },
-            ///  Parity Error. When the parity bit of a received character is in the wrong state, a parity error occurs. An LSR read clears LSR[2]. Time of parity error detection is dependent on FCR[0]. Note: A parity error is associated with the character at the top of the UART1 RBR FIFO.
-            PE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Parity error status is inactive.
-                    INACTIVE = 0x0,
-                    ///  Parity error status is active.
-                    ACTIVE = 0x1,
-                },
-            },
-            ///  Framing Error. When the stop bit of a received character is a logic 0, a framing error occurs. An LSR read clears LSR[3]. The time of the framing error detection is dependent on FCR0. Upon detection of a framing error, the RX will attempt to resynchronize to the data and assume that the bad stop bit is actually an early start bit. However, it cannot be assumed that the next received byte will be correct even if there is no Framing Error. Note: A framing error is associated with the character at the top of the UART1 RBR FIFO.
-            FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Framing error status is inactive.
-                    INACTIVE = 0x0,
-                    ///  Framing error status is active.
-                    ACTIVE = 0x1,
-                },
-            },
-            ///  Break Interrupt. When RXD1 is held in the spacing state (all zeroes) for one full character transmission (start, data, parity, stop), a break interrupt occurs. Once the break condition has been detected, the receiver goes idle until RXD1 goes to marking state (all ones). An LSR read clears this status bit. The time of break detection is dependent on FCR[0]. Note: The break interrupt is associated with the character at the top of the UART1 RBR FIFO.
-            BI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Break interrupt status is inactive.
-                    INACTIVE = 0x0,
-                    ///  Break interrupt status is active.
-                    ACTIVE = 0x1,
-                },
-            },
-            ///  Transmitter Holding Register Empty. THRE is set immediately upon detection of an empty UART1 THR and is cleared on a THR write.
-            THRE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  THR contains valid data.
-                    VALID = 0x0,
-                    ///  THR is empty.
-                    THR_IS_EMPTY_ = 0x1,
-                },
-            },
-            ///  Transmitter Empty. TEMT is set when both THR and TSR are empty; TEMT is cleared when either the TSR or the THR contain valid data.
-            TEMT: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  THR and/or the TSR contains valid data.
-                    VALID = 0x0,
-                    ///  THR and the TSR are empty.
-                    EMPTY = 0x1,
-                },
-            },
-            ///  Error in RX FIFO. LSR[7] is set when a character with a RX error such as framing error, parity error or break interrupt, is loaded into the RBR. This bit is cleared when the LSR register is read and there are no subsequent errors in the UART1 FIFO.
-            RXFE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  RBR contains no UART1 RX errors or FCR[0]=0.
-                    NOERROR = 0x0,
-                    ///  UART1 RBR contains at least one UART1 RX error.
-                    ERRORS = 0x1,
-                },
-            },
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  Modem Status Register. Contains handshake signal status flags.
-        MSR: mmio.Mmio(packed struct(u32) {
-            ///  Delta CTS. Set upon state change of input CTS. Cleared on an MSR read.
-            DCTS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No change detected on modem input, CTS.
-                    NO_CHANGE_DETECTED_O = 0x0,
-                    ///  State change detected on modem input, CTS.
-                    STATE_CHANGE_DETECTE = 0x1,
-                },
-            },
-            ///  Delta DSR. Set upon state change of input DSR. Cleared on an MSR read.
-            DDSR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No change detected on modem input, DSR.
-                    NO_CHANGE_DETECTED_O = 0x0,
-                    ///  State change detected on modem input, DSR.
-                    STATE_CHANGE_DETECTE = 0x1,
-                },
-            },
-            ///  Trailing Edge RI. Set upon low to high transition of input RI. Cleared on an MSR read.
-            TERI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No change detected on modem input, RI.
-                    NO_CHANGE_DETECTED_O = 0x0,
-                    ///  Low-to-high transition detected on RI.
-                    LOW_TO_HIGH_TRANSITI = 0x1,
-                },
-            },
-            ///  Delta DCD. Set upon state change of input DCD. Cleared on an MSR read.
-            DDCD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No change detected on modem input, DCD.
-                    NO_CHANGE_DETECTED_O = 0x0,
-                    ///  State change detected on modem input, DCD.
-                    STATE_CHANGE_DETECTE = 0x1,
-                },
-            },
-            ///  Clear To Send State. Complement of input signal CTS. This bit is connected to MCR[1] in modem loopback mode.
-            CTS: u1,
-            ///  Data Set Ready State. Complement of input signal DSR. This bit is connected to MCR[0] in modem loopback mode.
-            DSR: u1,
-            ///  Ring Indicator State. Complement of input RI. This bit is connected to MCR[2] in modem loopback mode.
-            RI: u1,
-            ///  Data Carrier Detect State. Complement of input DCD. This bit is connected to MCR[3] in modem loopback mode.
-            DCD: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  Scratch Pad Register. 8-bit temporary storage for software.
-        SCR: mmio.Mmio(packed struct(u32) {
-            ///  A readable, writable byte.
-            Pad: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  Auto-baud Control Register. Contains controls for the auto-baud feature.
-        ACR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-baud start bit. This bit is automatically cleared after auto-baud completion.
-            START: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Auto-baud stop (auto-baud is not running).
-                    STOP = 0x0,
-                    ///  Auto-baud start (auto-baud is running). Auto-baud run bit. This bit is automatically cleared after auto-baud completion.
-                    START = 0x1,
-                },
-            },
-            ///  Auto-baud mode select bit.
-            MODE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Mode 0.
-                    MODE_0_ = 0x0,
-                    ///  Mode 1.
-                    MODE_1_ = 0x1,
-                },
-            },
-            ///  Auto-baud restart bit.
-            AUTORESTART: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No restart
-                    NO_RESTART = 0x0,
-                    ///  Restart in case of time-out (counter restarts at next UART1 Rx falling edge)
-                    RESTART_IN_CASE_OF_T = 0x1,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u5,
-            ///  End of auto-baud interrupt clear bit (write-only).
-            ABEOINTCLR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Writing a 0 has no impact.
-                    WRITING_A_0_HAS_NO_I = 0x0,
-                    ///  Writing a 1 will clear the corresponding interrupt in the IIR.
-                    WRITING_A_1_WILL_CLE = 0x1,
-                },
-            },
-            ///  Auto-baud time-out interrupt clear bit (write-only).
-            ABTOINTCLR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Writing a 0 has no impact.
-                    WRITING_A_0_HAS_NO_I = 0x0,
-                    ///  Writing a 1 will clear the corresponding interrupt in the IIR.
-                    WRITING_A_1_WILL_CLE = 0x1,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u22,
-        }),
-        reserved40: [4]u8,
-        ///  Fractional Divider Register. Generates a clock input for the baud rate divider.
-        FDR: mmio.Mmio(packed struct(u32) {
-            ///  Baud rate generation pre-scaler divisor value. If this field is 0, fractional baud rate generator will not impact the UART1 baud rate.
-            DIVADDVAL: u4,
-            ///  Baud rate pre-scaler multiplier value. This field must be greater or equal 1 for UART1 to operate properly, regardless of whether the fractional baud rate generator is used or not.
-            MULVAL: u4,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        reserved48: [4]u8,
-        ///  Transmit Enable Register. Turns off UART transmitter for use with software flow control.
-        TER: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u7,
-            ///  When this bit is 1, as it is after a Reset, data written to the THR is output on the TXD pin as soon as any preceding data has been sent. If this bit cleared to 0 while a character is being sent, the transmission of that character is completed, but no further characters are sent until this bit is set again. In other words, a 0 in this bit blocks the transfer of characters from the THR or TX FIFO into the transmit shift register. Software can clear this bit when it detects that the a hardware-handshaking TX-permit signal (CTS) has gone false, or with software handshaking, when it receives an XOFF character (DC3). Software can set this bit again when it detects that the TX-permit signal has gone true, or when it receives an XON (DC1) character.
-            TXEN: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        reserved76: [24]u8,
-        ///  RS-485/EIA-485 Control. Contains controls to configure various aspects of RS-485/EIA-485 modes.
-        RS485CTRL: mmio.Mmio(packed struct(u32) {
-            ///  RS-485/EIA-485 Normal Multidrop Mode (NMM) mode select.
-            NMMEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Enabled. In this mode, an address is detected when a received byte causes the UART to set the parity error and generate an interrupt.
-                    ENABLED_IN_THIS_MOD = 0x1,
-                },
-            },
-            ///  Receive enable.
-            RXDIS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Enabled.
-                    ENABLED_ = 0x0,
-                    ///  Disabled.
-                    DISABLED_ = 0x1,
-                },
-            },
-            ///  Auto Address Detect (AAD) enable.
-            AADEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Enabled.
-                    ENABLED_ = 0x1,
-                },
-            },
-            ///  Direction control.
-            SEL: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  RTS. If direction control is enabled (bit DCTRL = 1), pin RTS is used for direction control.
-                    RTS_IF_DIRECTION_CO = 0x0,
-                    ///  DTR. If direction control is enabled (bit DCTRL = 1), pin DTR is used for direction control.
-                    DTR_IF_DIRECTION_CO = 0x1,
-                },
-            },
-            ///  Direction control enable.
-            DCTRL: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable Auto Direction Control.
-                    DISABLE_AUTO_DIRECTI = 0x0,
-                    ///  Enable Auto Direction Control.
-                    ENABLE_AUTO_DIRECTIO = 0x1,
-                },
-            },
-            ///  Polarity. This bit reverses the polarity of the direction control signal on the RTS (or DTR) pin.
-            OINV: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  LOW. The direction control pin will be driven to logic 0 when the transmitter has data to be sent. It will be driven to logic 1 after the last bit of data has been transmitted.
-                    LOW_THE_DIRECTION_C = 0x0,
-                    ///  HIGH. The direction control pin will be driven to logic 1 when the transmitter has data to be sent. It will be driven to logic 0 after the last bit of data has been transmitted.
-                    HIGH_THE_DIRECTION_ = 0x1,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u26,
-        }),
-        ///  RS-485/EIA-485 address match. Contains the address match value for RS-485/EIA-485 mode.
-        RS485ADRMATCH: mmio.Mmio(packed struct(u32) {
-            ///  Contains the address match value.
-            ADRMATCH: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  RS-485/EIA-485 direction control delay.
-        RS485DLY: mmio.Mmio(packed struct(u32) {
-            ///  Contains the direction control (RTS or DTR) delay value. This register works in conjunction with an 8-bit counter.
-            DLY: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-    };
-
-    ///  Pulse Width Modulators (PWM1)
-    pub const PWM1 = extern struct {
-        ///  Interrupt Register. The IR can be written to clear interrupts, or read to identify which PWM interrupt sources are pending.
-        IR: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt flag for PWM match channel 0.
-            PWMMR0INT: u1,
-            ///  Interrupt flag for PWM match channel 1.
-            PWMMR1INT: u1,
-            ///  Interrupt flag for PWM match channel 2.
-            PWMMR2INT: u1,
-            ///  Interrupt flag for PWM match channel 3.
-            PWMMR3INT: u1,
-            ///  Interrupt flag for capture input 0
-            PWMCAP0INT: u1,
-            ///  Interrupt flag for capture input 1 (available in PWM1IR only; this bit is reserved in PWM0IR).
-            PWMCAP1INT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  Interrupt flag for PWM match channel 4.
-            PWMMR4INT: u1,
-            ///  Interrupt flag for PWM match channel 5.
-            PWMMR5INT: u1,
-            ///  Interrupt flag for PWM match channel 6.
-            PWMMR6INT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u21,
-        }),
-        ///  Timer Control Register. The TCR is used to control the Timer Counter functions.
-        TCR: mmio.Mmio(packed struct(u32) {
-            ///  Counter Enable
-            CE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The PWM Timer Counter and PWM Prescale Counter are enabled for counting.
-                    THE_PWM_TIMER_COUNTE = 0x1,
-                    ///  The counters are disabled.
-                    THE_COUNTERS_ARE_DIS = 0x0,
-                },
-            },
-            ///  Counter Reset
-            CR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The PWM Timer Counter and the PWM Prescale Counter are synchronously reset on the next positive edge of PCLK. The counters remain reset until this bit is returned to zero.
-                    THE_PWM_TIMER_COUNTE = 0x1,
-                    ///  Clear reset.
-                    CLEAR_RESET_ = 0x0,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  PWM Enable
-            PWMEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  PWM mode is enabled (counter resets to 1). PWM mode causes the shadow registers to operate in connection with the Match registers. A program write to a Match register will not have an effect on the Match result until the corresponding bit in PWMLER has been set, followed by the occurrence of a PWM Match 0 event. Note that the PWM Match register that determines the PWM rate (PWM Match Register 0 - MR0) must be set up prior to the PWM being enabled. Otherwise a Match event will not occur to cause shadow register contents to become effective.
-                    PWM_MODE_IS_ENABLED_ = 0x1,
-                    ///  Timer mode is enabled (counter resets to 0).
-                    TIMER_MODE_IS_ENABLE = 0x0,
-                },
-            },
-            ///  Master Disable (PWM0 only). The two PWMs may be synchronized using the Master Disable control bit. The Master disable bit of the Master PWM (PWM0 module) controls a secondary enable input to both PWMs, as shown in Figure 141. This bit has no function in the Slave PWM (PWM1).
-            MDIS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Master use. PWM0 is the master, and both PWMs are enabled for counting.
-                    MASTER_USE_PWM0_IS_ = 0x1,
-                    ///  Individual use. The PWMs are used independently, and the individual Counter Enable bits are used to control the PWMs.
-                    INDIVIDUAL_USE_THE_ = 0x0,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u27,
-        }),
-        ///  Timer Counter. The 32 bit TC is incremented every PR+1 cycles of PCLK. The TC is controlled through the TCR.
-        TC: mmio.Mmio(packed struct(u32) {
-            ///  Timer counter value.
-            TC: u32,
-        }),
-        ///  Prescale Register. Determines how often the PWM counter is incremented.
-        PR: mmio.Mmio(packed struct(u32) {
-            ///  Prescale counter maximum value.
-            PM: u32,
-        }),
-        ///  Prescale Counter. Prescaler for the main PWM counter.
-        PC: mmio.Mmio(packed struct(u32) {
-            ///  Prescale counter value.
-            PC: u32,
-        }),
-        ///  Match Control Register. The MCR is used to control whether an interrupt is generated and if the PWM counter is reset when a Match occurs.
-        MCR: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt PWM0
-            PWMMR0I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Interrupt on PWMMR0: an interrupt is generated when PWMMR0 matches the value in the PWMTC.
-                    INTERRUPT_ON_PWMMR0 = 0x1,
-                },
-            },
-            ///  Reset PWM0
-            PWMMR0R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Reset on PWMMR0: the PWMTC will be reset if PWMMR0 matches it.
-                    RESET_ON_PWMMR0_THE = 0x1,
-                },
-            },
-            ///  Stop PWM0
-            PWMMR0S: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled
-                    DISABLED = 0x0,
-                    ///  Stop on PWMMR0: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.
-                    STOP_ON_PWMMR0_THE_ = 0x1,
-                },
-            },
-            ///  Interrupt PWM1
-            PWMMR1I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Interrupt on PWMMR1: an interrupt is generated when PWMMR1 matches the value in the PWMTC.
-                    INTERRUPT_ON_PWMMR1 = 0x1,
-                },
-            },
-            ///  Reset PWM1
-            PWMMR1R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Reset on PWMMR1: the PWMTC will be reset if PWMMR1 matches it.
-                    RESET_ON_PWMMR1_THE = 0x1,
-                },
-            },
-            ///  Stop PWM1
-            PWMMR1S: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled
-                    DISABLED = 0x0,
-                    ///  Stop on PWMMR1: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR1 matches the PWMTC.
-                    STOP_ON_PWMMR1_THE_ = 0x1,
-                },
-            },
-            ///  Interrupt PWM0
-            PWMMR2I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Interrupt on PWMMR2: an interrupt is generated when PWMMR2 matches the value in the PWMTC.
-                    INTERRUPT_ON_PWMMR2 = 0x1,
-                },
-            },
-            ///  Reset PWM0
-            PWMMR2R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Reset on PWMMR2: the PWMTC will be reset if PWMMR2 matches it.
-                    RESET_ON_PWMMR2_THE = 0x1,
-                },
-            },
-            ///  Stop PWM0
-            PWMMR2S: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled
-                    DISABLED = 0x0,
-                    ///  Stop on PWMMR2: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.
-                    STOP_ON_PWMMR2_THE_ = 0x1,
-                },
-            },
-            ///  Interrupt PWM3
-            PWMMR3I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Interrupt on PWMMR3: an interrupt is generated when PWMMR3 matches the value in the PWMTC.
-                    INTERRUPT_ON_PWMMR3 = 0x1,
-                },
-            },
-            ///  Reset PWM3
-            PWMMR3R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Reset on PWMMR3: the PWMTC will be reset if PWMMR3 matches it.
-                    RESET_ON_PWMMR3_THE = 0x1,
-                },
-            },
-            ///  Stop PWM0
-            PWMMR3S: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled
-                    DISABLED = 0x0,
-                    ///  Stop on PWMMR3: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR0 matches the PWMTC.
-                    STOP_ON_PWMMR3_THE_ = 0x1,
-                },
-            },
-            ///  Interrupt PWM4
-            PWMMR4I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Interrupt on PWMMR4: an interrupt is generated when PWMMR4 matches the value in the PWMTC.
-                    INTERRUPT_ON_PWMMR4 = 0x1,
-                },
-            },
-            ///  Reset PWM4
-            PWMMR4R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Reset on PWMMR4: the PWMTC will be reset if PWMMR4 matches it.
-                    RESET_ON_PWMMR4_THE = 0x1,
-                },
-            },
-            ///  Stop PWM4
-            PWMMR4S: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled
-                    DISABLED = 0x0,
-                    ///  Stop on PWMMR4: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR4 matches the PWMTC.
-                    STOP_ON_PWMMR4_THE_ = 0x1,
-                },
-            },
-            ///  Interrupt PWM5
-            PWMMR5I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Interrupt on PWMMR5: an interrupt is generated when PWMMR5 matches the value in the PWMTC.
-                    INTERRUPT_ON_PWMMR5 = 0x1,
-                },
-            },
-            ///  Reset PWM5
-            PWMMR5R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Reset on PWMMR5: the PWMTC will be reset if PWMMR5 matches it.
-                    RESET_ON_PWMMR5_THE = 0x1,
-                },
-            },
-            ///  Stop PWM5
-            PWMMR5S: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled
-                    DISABLED = 0x0,
-                    ///  Stop on PWMMR5: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR5 matches the PWMTC.
-                    STOP_ON_PWMMR5_THE_ = 0x1,
-                },
-            },
-            ///  Interrupt PWM6
-            PWMMR6I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Interrupt on PWMMR6: an interrupt is generated when PWMMR6 matches the value in the PWMTC.
-                    INTERRUPT_ON_PWMMR6 = 0x1,
-                },
-            },
-            ///  Reset PWM6
-            PWMMR6R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Reset on PWMMR6: the PWMTC will be reset if PWMMR6 matches it.
-                    RESET_ON_PWMMR6_THE = 0x1,
-                },
-            },
-            ///  Stop PWM6
-            PWMMR6S: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled
-                    DISABLED = 0x0,
-                    ///  Stop on PWMMR6: the PWMTC and PWMPC will be stopped and PWMTCR bit 0 will be set to 0 if PWMMR6 matches the PWMTC.
-                    STOP_ON_PWMMR6_THE_ = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u11,
-        }),
-        reserved40: [16]u8,
-        ///  Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated for a capture event.
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Capture on PWMn_CAP0 rising edge
-            CAP0_R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled. This feature is disabled.
-                    DISABLED_THIS_FEATU = 0x0,
-                    ///  Rising edge. A synchronously sampled rising edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of the TC.
-                    RISING_EDGE_A_SYNCH = 0x1,
-                },
-            },
-            ///  Capture on PWMn_CAP0 falling edge
-            CAP0_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled. This feature is disabled.
-                    DISABLED_THIS_FEATU = 0x0,
-                    ///  Falling edge. A synchronously sampled falling edge on PWMn_CAP0 will cause CR0 to be loaded with the contents of TC.
-                    FALLING_EDGE_A_SYNC = 0x1,
-                },
-            },
-            ///  Interrupt on PWMn_CAP0 event
-            CAP0_I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled. This feature is disabled.
-                    DISABLED_THIS_FEATU = 0x0,
-                    ///  Interrupt. A CR0 load due to a PWMn_CAP0 event will generate an interrupt.
-                    INTERRUPT_A_CR0_LOA = 0x1,
-                },
-            },
-            ///  Capture on PWMn_CAP1 rising edge. Reserved for PWM0.
-            CAP1_R: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled. This feature is disabled.
-                    DISABLED_THIS_FEATU = 0x0,
-                    ///  Rising edge. A synchronously sampled rising edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of the TC.
-                    RISING_EDGE_A_SYNCH = 0x1,
-                },
-            },
-            ///  Capture on PWMn_CAP1 falling edge. Reserved for PWM0.
-            CAP1_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled. This feature is disabled.
-                    DISABLED_THIS_FEATU = 0x0,
-                    ///  Falling edge. A synchronously sampled falling edge on PWMn_CAP1 will cause CR1 to be loaded with the contents of TC.
-                    FALLING_EDGE_A_SYNC = 0x1,
-                },
-            },
-            ///  Interrupt on PWMn_CAP1 event. Reserved for PWM0.
-            CAP1_I: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled. This feature is disabled.
-                    DISABLED_THIS_FEATU = 0x0,
-                    ///  Interrupt. A CR1 load due to a PWMn_CAP1 event will generate an interrupt.
-                    INTERRUPT_A_CR1_LOA = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u26,
-        }),
-        reserved76: [32]u8,
-        ///  PWM Control Register. Enables PWM outputs and selects either single edge or double edge controlled PWM outputs.
-        PCR: mmio.Mmio(packed struct(u32) {
-            ///  Reserved.
-            RESERVED: u2,
-            ///  PWM[2] output single/double edge mode control.
-            PWMSEL2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Single edge controlled mode is selected.
-                    SINGLE_EDGE_CONTROLL = 0x0,
-                    ///  Double edge controlled mode is selected.
-                    DOUBLE_EDGE_CONTROLL = 0x1,
-                },
-            },
-            ///  PWM[3] output edge control.
-            PWMSEL3: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Single edge controlled mode is selected.
-                    SINGLE_EDGE_CONTROLL = 0x0,
-                    ///  Double edge controlled mode is selected.
-                    DOUBLE_EDGE_CONTROLL = 0x1,
-                },
-            },
-            ///  PWM[4] output edge control.
-            PWMSEL4: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Single edge controlled mode is selected.
-                    SINGLE_EDGE_CONTROLL = 0x0,
-                    ///  Double edge controlled mode is selected.
-                    DOUBLE_EDGE_CONTROLL = 0x1,
-                },
-            },
-            ///  PWM[5] output edge control.
-            PWMSEL5: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Single edge controlled mode is selected.
-                    SINGLE_EDGE_CONTROLL = 0x0,
-                    ///  Double edge controlled mode is selected.
-                    DOUBLE_EDGE_CONTROLL = 0x1,
-                },
-            },
-            ///  PWM[6] output edge control.
-            PWMSEL6: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Single edge controlled mode is selected.
-                    SINGLE_EDGE_CONTROLL = 0x0,
-                    ///  Double edge controlled mode is selected.
-                    DOUBLE_EDGE_CONTROLL = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  PWM[1] output enable control.
-            PWMENA1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The PWM output is disabled.
-                    THE_PWM_OUTPUT_IS_DI = 0x0,
-                    ///  The PWM output is enabled.
-                    THE_PWM_OUTPUT_IS_EN = 0x1,
-                },
-            },
-            ///  PWM[2] output enable control.
-            PWMENA2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The PWM output is disabled.
-                    THE_PWM_OUTPUT_IS_DI = 0x0,
-                    ///  The PWM output is enabled.
-                    THE_PWM_OUTPUT_IS_EN = 0x1,
-                },
-            },
-            ///  PWM[3] output enable control.
-            PWMENA3: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The PWM output is disabled.
-                    THE_PWM_OUTPUT_IS_DI = 0x0,
-                    ///  The PWM output is enabled.
-                    THE_PWM_OUTPUT_IS_EN = 0x1,
-                },
-            },
-            ///  PWM[4] output enable control.
-            PWMENA4: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The PWM output is disabled.
-                    THE_PWM_OUTPUT_IS_DI = 0x0,
-                    ///  The PWM output is enabled.
-                    THE_PWM_OUTPUT_IS_EN = 0x1,
-                },
-            },
-            ///  PWM[5] output enable control.
-            PWMENA5: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The PWM output is disabled.
-                    THE_PWM_OUTPUT_IS_DI = 0x0,
-                    ///  The PWM output is enabled.
-                    THE_PWM_OUTPUT_IS_EN = 0x1,
-                },
-            },
-            ///  PWM[6] output enable control. See PWMENA1 for details.
-            PWMENA6: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The PWM output is disabled.
-                    THE_PWM_OUTPUT_IS_DI = 0x0,
-                    ///  The PWM output is enabled.
-                    THE_PWM_OUTPUT_IS_EN = 0x1,
-                },
-            },
-            ///  Unused, always zero.
-            RESERVED: u17,
-        }),
-        ///  Load Enable Register. Enables use of updated PWM match values.
-        LER: mmio.Mmio(packed struct(u32) {
-            ///  Enable PWM Match 0 Latch. PWM MR0 register update control. Writing a one to this bit allows the last value written to the PWM Match Register 0 to be become effective when the timer is next reset by a PWM Match event. See Section 27.6.7.
-            MAT0LATCHEN: u1,
-            ///  Enable PWM Match 1 Latch. PWM MR1 register update control. See bit 0 for details.
-            MAT1LATCHEN: u1,
-            ///  Enable PWM Match 2 Latch. PWM MR2 register update control. See bit 0 for details.
-            MAT2LATCHEN: u1,
-            ///  Enable PWM Match 3 Latch. PWM MR3 register update control. See bit 0 for details.
-            MAT3LATCHEN: u1,
-            ///  Enable PWM Match 4 Latch. PWM MR4 register update control. See bit 0 for details.
-            MAT4LATCHEN: u1,
-            ///  Enable PWM Match 5 Latch. PWM MR5 register update control. See bit 0 for details.
-            MAT5LATCHEN: u1,
-            ///  Enable PWM Match 6 Latch. PWM MR6 register update control. See bit 0 for details.
-            MAT6LATCHEN: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u25,
-        }),
-        reserved112: [28]u8,
-        ///  Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting.
-        CTCR: mmio.Mmio(packed struct(u32) {
-            ///  Counter/ Timer Mode
-            MOD: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Timer Mode: the TC is incremented when the Prescale Counter matches the Prescale register.
-                    TIMER_MODE_THE_TC_I = 0x0,
-                    ///  Rising edge counter Mode: the TC is incremented on rising edges of the PWM_CAP input selected by bits 3:2.
-                    RISING_EDGE_COUNTER_ = 0x1,
-                    ///  Falling edge counter Mode: the TC is incremented on falling edges of the PWM_CAP input selected by bits 3:2.
-                    FALLING_EDGE_COUNTER = 0x2,
-                    ///  Dual edge counter Mode: the TC is incremented on both edges of the PWM_CAP input selected by bits 3:2.
-                    DUAL_EDGE_COUNTER_MO = 0x3,
-                },
-            },
-            ///  Count Input Select. When bits 1:0 are not 00, these bits select which PWM_CAP pin carries the signal used to increment the TC. Other combinations are reserved.
-            CIS: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  For PWM0: 00 = PWM0_CAP0 (Other combinations are reserved) For PWM1: 00 = PWM1_CAP0, 01 = PWM1_CAP1 (Other combinations are reserved)
-                    FOR_PWM0_00_EQ_PWM0_ = 0x0,
-                    _,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u28,
-        }),
-    };
-
-    ///  I2C bus interface
-    pub const I2C0 = extern struct {
-        ///  I2C Control Set Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is set. Writing a zero has no effect on the corresponding bit in the I2C control register.
-        CONSET: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u2,
-            ///  Assert acknowledge flag.
-            AA: u1,
-            ///  I2C interrupt flag.
-            SI: u1,
-            ///  STOP flag.
-            STO: u1,
-            ///  START flag.
-            STA: u1,
-            ///  I2C interface enable.
-            I2EN: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u25,
-        }),
-        ///  I2C Status Register. During I2C operation, this register provides detailed status codes that allow software to determine the next action needed.
-        STAT: mmio.Mmio(packed struct(u32) {
-            ///  These bits are unused and are always 0.
-            RESERVED: u3,
-            ///  These bits give the actual status information about the I 2C interface.
-            Status: u5,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  I2C Data Register. During master or slave transmit mode, data to be transmitted is written to this register. During master or slave receive mode, data that has been received may be read from this register.
-        DAT: mmio.Mmio(packed struct(u32) {
-            ///  This register holds data values that have been received or are to be transmitted.
-            Data: u8,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  I2C Slave Address Register 0. Contains the 7-bit slave address for operation of the I2C interface in slave mode, and is not used in master mode. The least significant bit determines whether a slave responds to the General Call address.
-        ADR0: mmio.Mmio(packed struct(u32) {
-            ///  General Call enable bit.
-            GC: u1,
-            ///  The I2C device address for slave mode.
-            Address: u7,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  SCH Duty Cycle Register High Half Word. Determines the high time of the I2C clock.
-        SCLH: mmio.Mmio(packed struct(u32) {
-            ///  Count for SCL HIGH time period selection.
-            SCLH: u16,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u16,
-        }),
-        ///  SCL Duty Cycle Register Low Half Word. Determines the low time of the I2C clock. SCLL and SCLH together determine the clock frequency generated by an I2C master and certain times used in slave mode.
-        SCLL: mmio.Mmio(packed struct(u32) {
-            ///  Count for SCL low time period selection.
-            SCLL: u16,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u16,
-        }),
-        ///  I2C Control Clear Register. When a one is written to a bit of this register, the corresponding bit in the I2C control register is cleared. Writing a zero has no effect on the corresponding bit in the I2C control register.
-        CONCLR: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u2,
-            ///  Assert acknowledge Clear bit.
-            AAC: u1,
-            ///  I2C interrupt Clear bit.
-            SIC: u1,
-            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u1,
-            ///  START flag Clear bit.
-            STAC: u1,
-            ///  I2C interface Disable bit.
-            I2ENC: u1,
-            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  Monitor mode control register.
-        MMCTRL: mmio.Mmio(packed struct(u32) {
-            ///  Monitor mode enable.
-            MM_ENA: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Monitor mode disabled.
-                    MONITOR_MODE_DISABLE = 0x0,
-                    ///  The I 2C module will enter monitor mode. In this mode the SDA output will be forced high. This will prevent the I2C module from outputting data of any kind (including ACK) onto the I2C data bus. Depending on the state of the ENA_SCL bit, the output may be also forced high, preventing the module from having control over the I2C clock line.
-                    THE_I_2C_MODULE_WILL = 0x1,
-                },
-            },
-            ///  SCL output enable.
-            ENA_SCL: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  When this bit is cleared to 0, the SCL output will be forced high when the module is in monitor mode. As described above, this will prevent the module from having any control over the I2C clock line.
-                    WHEN_THIS_BIT_IS_CLE = 0x0,
-                    ///  When this bit is set, the I2C module may exercise the same control over the clock line that it would in normal operation. This means that, acting as a slave peripheral, the I2C module can stretch the clock line (hold it low) until it has had time to respond to an I2C interrupt.[1]
-                    WHEN_THIS_BIT_IS_SET = 0x1,
-                },
-            },
-            ///  Select interrupt register match.
-            MATCH_ALL: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  When this bit is cleared, an interrupt will only be generated when a match occurs to one of the (up-to) four address registers described above. That is, the module will respond as a normal slave as far as address-recognition is concerned.
-                    WHEN_THIS_BIT_IS_CLE = 0x0,
-                    ///  When this bit is set to 1 and the I2C is in monitor mode, an interrupt will be generated on ANY address received. This will enable the part to monitor all traffic on the bus.
-                    WHEN_THIS_BIT_IS_SET = 0x1,
-                },
-            },
-            ///  Reserved. The value read from reserved bits is not defined.
-            RESERVED: u29,
-        }),
-        reserved44: [12]u8,
-        ///  Data buffer register. The contents of the 8 MSBs of the DAT shift register will be transferred to the DATA_BUFFER automatically after every nine bits (8 bits of data plus ACK or NACK) has been received on the bus.
-        DATA_BUFFER: mmio.Mmio(packed struct(u32) {
-            ///  This register holds contents of the 8 MSBs of the DAT shift register.
-            Data: u8,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-    };
-
-    ///  SPI
-    pub const SPI = extern struct {
-        ///  SPI Control Register. This register controls the operation of the SPI.
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u2,
-            ///  The SPI controller sends and receives 8 bits of data per transfer.
-            BITENABLE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The SPI controller sends and receives the number of bits selected by bits 11:8.
-                    THE_SPI_CONTROLLER_S = 0x1,
-                    _,
-                },
-            },
-            ///  Clock phase control determines the relationship between the data and the clock on SPI transfers, and controls when a slave transfer is defined as starting and ending.
-            CPHA: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Data is sampled on the first clock edge of SCK. A transfer starts and ends with activation and deactivation of the SSEL signal.
-                    FIRST_EDGE = 0x0,
-                    ///  Data is sampled on the second clock edge of the SCK. A transfer starts with the first clock edge, and ends with the last sampling edge when the SSEL signal is active.
-                    SECOND_EDGE = 0x1,
-                },
-            },
-            ///  Clock polarity control.
-            CPOL: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  SCK is active high.
-                    SCK_IS_ACTIVE_HIGH_ = 0x0,
-                    ///  SCK is active low.
-                    SCK_IS_ACTIVE_LOW_ = 0x1,
-                },
-            },
-            ///  Master mode select.
-            MSTR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The SPI operates in Slave mode.
-                    SLAVE = 0x0,
-                    ///  The SPI operates in Master mode.
-                    MASTER = 0x1,
-                },
-            },
-            ///  LSB First controls which direction each byte is shifted when transferred.
-            LSBF: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  SPI data is transferred MSB (bit 7) first.
-                    MSB = 0x0,
-                    ///  SPI data is transferred LSB (bit 0) first.
-                    LSB = 0x1,
-                },
-            },
-            ///  Serial peripheral interrupt enable.
-            SPIE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  SPI interrupts are inhibited.
-                    INTBLOCK = 0x0,
-                    ///  A hardware interrupt is generated each time the SPIF or MODF bits are activated.
-                    HWINT = 0x1,
-                },
-            },
-            ///  When bit 2 of this register is 1, this field controls the number of bits per transfer:
-            BITS: packed union {
-                raw: u4,
-                value: enum(u4) {
-                    ///  8 bits per transfer
-                    @"8_BITS_PER_TRANSFER" = 0x8,
-                    ///  9 bits per transfer
-                    @"9_BITS_PER_TRANSFER" = 0x9,
-                    ///  10 bits per transfer
-                    @"10_BITS_PER_TRANSFER" = 0xa,
-                    ///  11 bits per transfer
-                    @"11_BITS_PER_TRANSFER" = 0xb,
-                    ///  12 bits per transfer
-                    @"12_BITS_PER_TRANSFER" = 0xc,
-                    ///  13 bits per transfer
-                    @"13_BITS_PER_TRANSFER" = 0xd,
-                    ///  14 bits per transfer
-                    @"14_BITS_PER_TRANSFER" = 0xe,
-                    ///  15 bits per transfer
-                    @"15_BITS_PER_TRANSFER" = 0xf,
-                    ///  16 bits per transfer
-                    @"16_BITS_PER_TRANSFER" = 0x0,
-                    _,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u20,
-        }),
-        ///  SPI Status Register. This register shows the status of the SPI.
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u3,
-            ///  Slave abort. When 1, this bit indicates that a slave abort has occurred. This bit is cleared by reading this register.
-            ABRT: u1,
-            ///  Mode fault. when 1, this bit indicates that a Mode fault error has occurred. This bit is cleared by reading this register, then writing the SPI0 control register.
-            MODF: u1,
-            ///  Read overrun. When 1, this bit indicates that a read overrun has occurred. This bit is cleared by reading this register.
-            ROVR: u1,
-            ///  Write collision. When 1, this bit indicates that a write collision has occurred. This bit is cleared by reading this register, then accessing the SPI Data Register.
-            WCOL: u1,
-            ///  SPI transfer complete flag. When 1, this bit indicates when a SPI data transfer is complete. When a master, this bit is set at the end of the last cycle of the transfer. When a slave, this bit is set on the last data sampling edge of the SCK. This bit is cleared by first reading this register, then accessing the SPI Data Register. Note: this is not the SPI interrupt flag. This flag is found in the SPINT register.
-            SPIF: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  SPI Data Register. This bi-directional register provides the transmit and receive data for the SPI. Transmit data is provided to the SPI0 by writing to this register. Data received by the SPI0 can be read from this register.
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  SPI Bi-directional data port.
-            DATALOW: u8,
-            ///  If bit 2 of the SPCR is 1 and bits 11:8 are other than 1000, some or all of these bits contain the additional transmit and receive bits. When less than 16 bits are selected, the more significant among these bits read as zeroes.
-            DATAHIGH: u8,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u16,
-        }),
-        ///  SPI Clock Counter Register. This register controls the frequency of a master's SCK0.
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  SPI0 Clock counter setting.
-            COUNTER: u8,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        reserved28: [12]u8,
-        ///  SPI Interrupt Flag. This register contains the interrupt flag for the SPI interface.
-        INT: mmio.Mmio(packed struct(u32) {
-            ///  SPI interrupt flag. Set by the SPI interface to generate an interrupt. Cleared by writing a 1 to this bit. Note: this bit will be set once when SPIE = 1 and at least one of SPIF and WCOL bits is 1. However, only when the SPI Interrupt bit is set and SPI0 Interrupt is enabled in the NVIC, SPI based interrupt can be processed by interrupt handling software.
-            SPIF: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u7,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-    };
-
-    ///  Real Time Clock (RTC)
-    pub const RTC = extern struct {
-        ///  Interrupt Location Register
-        ILR: mmio.Mmio(packed struct(u32) {
-            ///  When one, the Counter Increment Interrupt block generated an interrupt. Writing a one to this bit location clears the counter increment interrupt.
-            RTCCIF: u1,
-            ///  When one, the alarm registers generated an interrupt. Writing a one to this bit location clears the alarm interrupt.
-            RTCALF: u1,
-            reserved21: u19,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u11,
-        }),
-        reserved8: [4]u8,
-        ///  Clock Control Register
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Clock Enable.
-            CLKEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The time counters are enabled.
-                    THE_TIME_COUNTERS_AR = 0x1,
-                    ///  The time counters are disabled so that they may be initialized.
-                    THE_TIME_COUNTERS_AR = 0x0,
-                },
-            },
-            ///  CTC Reset.
-            CTCRST: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  When one, the elements in the internal oscillator divider are reset, and remain reset until CCR[1] is changed to zero. This is the divider that generates the 1 Hz clock from the 32.768 kHz crystal. The state of the divider is not visible to software.
-                    RESET = 0x1,
-                    ///  No effect.
-                    NO_EFFECT_ = 0x0,
-                },
-            },
-            ///  Internal test mode controls. These bits must be 0 for normal RTC operation.
-            RESERVED: u2,
-            ///  Calibration counter enable.
-            CCALEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The calibration counter is disabled and reset to zero.
-                    THE_CALIBRATION_COUN = 0x1,
-                    ///  The calibration counter is enabled and counting, using the 1 Hz clock. When the calibration counter is equal to the value of the CALIBRATION register, the counter resets and repeats counting up to the value of the CALIBRATION register. See Section 30.6.4.2 and Section 30.6.5.
-                    THE_CALIBRATION_COUN = 0x0,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u27,
-        }),
-        ///  Counter Increment Interrupt Register
-        CIIR: mmio.Mmio(packed struct(u32) {
-            ///  When 1, an increment of the Second value generates an interrupt.
-            IMSEC: u1,
-            ///  When 1, an increment of the Minute value generates an interrupt.
-            IMMIN: u1,
-            ///  When 1, an increment of the Hour value generates an interrupt.
-            IMHOUR: u1,
-            ///  When 1, an increment of the Day of Month value generates an interrupt.
-            IMDOM: u1,
-            ///  When 1, an increment of the Day of Week value generates an interrupt.
-            IMDOW: u1,
-            ///  When 1, an increment of the Day of Year value generates an interrupt.
-            IMDOY: u1,
-            ///  When 1, an increment of the Month value generates an interrupt.
-            IMMON: u1,
-            ///  When 1, an increment of the Year value generates an interrupt.
-            IMYEAR: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  Alarm Mask Register
-        AMR: mmio.Mmio(packed struct(u32) {
-            ///  When 1, the Second value is not compared for the alarm.
-            AMRSEC: u1,
-            ///  When 1, the Minutes value is not compared for the alarm.
-            AMRMIN: u1,
-            ///  When 1, the Hour value is not compared for the alarm.
-            AMRHOUR: u1,
-            ///  When 1, the Day of Month value is not compared for the alarm.
-            AMRDOM: u1,
-            ///  When 1, the Day of Week value is not compared for the alarm.
-            AMRDOW: u1,
-            ///  When 1, the Day of Year value is not compared for the alarm.
-            AMRDOY: u1,
-            ///  When 1, the Month value is not compared for the alarm.
-            AMRMON: u1,
-            ///  When 1, the Year value is not compared for the alarm.
-            AMRYEAR: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  Consolidated Time Register 0
-        CTIME0: mmio.Mmio(packed struct(u32) {
-            ///  Seconds value in the range of 0 to 59
-            SECONDS: u6,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u2,
-            ///  Minutes value in the range of 0 to 59
-            MINUTES: u6,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u2,
-            ///  Hours value in the range of 0 to 23
-            HOURS: u5,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u3,
-            ///  Day of week value in the range of 0 to 6
-            DOW: u3,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u5,
-        }),
-        ///  Consolidated Time Register 1
-        CTIME1: mmio.Mmio(packed struct(u32) {
-            ///  Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).
-            DOM: u5,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u3,
-            ///  Month value in the range of 1 to 12.
-            MONTH: u4,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u4,
-            ///  Year value in the range of 0 to 4095.
-            YEAR: u12,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u4,
-        }),
-        ///  Consolidated Time Register 2
-        CTIME2: mmio.Mmio(packed struct(u32) {
-            ///  Day of year value in the range of 1 to 365 (366 for leap years).
-            DOY: u12,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u20,
-        }),
-        ///  Seconds Counter
-        SEC: mmio.Mmio(packed struct(u32) {
-            ///  Seconds value in the range of 0 to 59
-            SECONDS: u6,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u26,
-        }),
-        ///  Minutes Register
-        MIN: mmio.Mmio(packed struct(u32) {
-            ///  Minutes value in the range of 0 to 59
-            MINUTES: u6,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u26,
-        }),
-        ///  Hours Register
-        HRS: mmio.Mmio(packed struct(u32) {
-            ///  Hours value in the range of 0 to 23
-            HOURS: u5,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u27,
-        }),
-        ///  Day of Month Register
-        DOM: mmio.Mmio(packed struct(u32) {
-            ///  Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).
-            DOM: u5,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u27,
-        }),
-        ///  Day of Week Register
-        DOW: mmio.Mmio(packed struct(u32) {
-            ///  Day of week value in the range of 0 to 6.
-            DOW: u3,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u29,
-        }),
-        ///  Day of Year Register
-        DOY: mmio.Mmio(packed struct(u32) {
-            ///  Day of year value in the range of 1 to 365 (366 for leap years).
-            DOY: u9,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u23,
-        }),
-        ///  Months Register
-        MONTH: mmio.Mmio(packed struct(u32) {
-            ///  Month value in the range of 1 to 12.
-            MONTH: u4,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        ///  Years Register
-        YEAR: mmio.Mmio(packed struct(u32) {
-            ///  Year value in the range of 0 to 4095.
-            YEAR: u12,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u20,
-        }),
-        ///  Calibration Value Register
-        CALIBRATION: mmio.Mmio(packed struct(u32) {
-            ///  If enabled, the calibration counter counts up to this value. The maximum value is 131, 072 corresponding to about 36.4 hours. Calibration is disabled if CALVAL = 0.
-            CALVAL: u17,
-            ///  Calibration direction
-            CALDIR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Backward calibration. When CALVAL is equal to the calibration counter, the RTC timers will stop incrementing for 1 second.
-                    BACKWARD_CALIBRATION = 0x1,
-                    ///  Forward calibration. When CALVAL is equal to the calibration counter, the RTC timers will jump by 2 seconds.
-                    FORWARD_CALIBRATION_ = 0x0,
-                },
-            },
-            padding: u14,
-        }),
-        reserved88: [20]u8,
-        ///  RTC Auxiliary Enable register
-        RTC_AUXEN: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u4,
-            ///  Oscillator Fail Detect interrupt enable. When 0: the RTC Oscillator Fail detect interrupt is disabled. When 1: the RTC Oscillator Fail detect interrupt is enabled. See Section 30.6.2.5.
-            RTC_OSCFEN: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u27,
-        }),
-        ///  RTC Auxiliary control register
-        RTC_AUX: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u4,
-            ///  RTC Oscillator Fail detect flag. Read: this bit is set if the RTC oscillator stops, and when RTC power is first turned on. An interrupt will occur when this bit is set, the RTC_OSCFEN bit in RTC_AUXEN is a 1, and the RTC interrupt is enabled in the NVIC. Write: writing a 1 to this bit clears the flag.
-            RTC_OSCF: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  When 0: the RTC_ALARM pin reflects the RTC alarm status. When 1: the RTC_ALARM pin indicates Deep Power-down mode.
-            RTC_PDOUT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u25,
-        }),
-        ///  Alarm value for Seconds
-        ASEC: mmio.Mmio(packed struct(u32) {
-            ///  Seconds value in the range of 0 to 59
-            SECONDS: u6,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u26,
-        }),
-        ///  Alarm value for Minutes
-        AMIN: mmio.Mmio(packed struct(u32) {
-            ///  Minutes value in the range of 0 to 59
-            MINUTES: u6,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u26,
-        }),
-        ///  Alarm value for Hours
-        AHRS: mmio.Mmio(packed struct(u32) {
-            ///  Hours value in the range of 0 to 23
-            HOURS: u5,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u27,
-        }),
-        ///  Alarm value for Day of Month
-        ADOM: mmio.Mmio(packed struct(u32) {
-            ///  Day of month value in the range of 1 to 28, 29, 30, or 31 (depending on the month and whether it is a leap year).
-            DOM: u5,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u27,
-        }),
-        ///  Alarm value for Day of Week
-        ADOW: mmio.Mmio(packed struct(u32) {
-            ///  Day of week value in the range of 0 to 6.
-            DOW: u3,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u29,
-        }),
-        ///  Alarm value for Day of Year
-        ADOY: mmio.Mmio(packed struct(u32) {
-            ///  Day of year value in the range of 1 to 365 (366 for leap years).
-            DOY: u9,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u23,
-        }),
-        ///  Alarm value for Months
-        AMON: mmio.Mmio(packed struct(u32) {
-            ///  Month value in the range of 1 to 12.
-            MONTH: u4,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        ///  Alarm value for Year
-        AYRS: mmio.Mmio(packed struct(u32) {
-            ///  Year value in the range of 0 to 4095.
-            YEAR: u12,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u20,
-        }),
-    };
-
-    ///  GPIO
-    pub const GPIOINT = extern struct {
-        ///  GPIO overall Interrupt Status.
-        STATUS: mmio.Mmio(packed struct(u32) {
-            ///  Port 0 GPIO interrupt pending.
-            P0INT: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No pending interrupts on Port 0.
-                    NO_PENDING_INTERRUPT = 0x0,
-                    ///  At least one pending interrupt on Port 0.
-                    AT_LEAST_ONE_PENDING = 0x1,
-                },
-            },
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u1,
-            ///  Port 2 GPIO interrupt pending.
-            P2INT: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No pending interrupts on Port 2.
-                    NO_PENDING_INTERRUPT = 0x0,
-                    ///  At least one pending interrupt on Port 2.
-                    AT_LEAST_ONE_PENDING = 0x1,
-                },
-            },
-            padding: u29,
-        }),
-        ///  GPIO Interrupt Status for Rising edge for Port 0.
-        STATR0: mmio.Mmio(packed struct(u32) {
-            ///  Status of Rising Edge Interrupt for P0[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_0REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_1REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_2REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_3REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_4REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_5REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_6REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_7REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_8REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_9REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_10REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_11REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_12REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_13REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[14]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_14REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[15]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_15REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[16]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_16REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[17]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_17REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[18]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_18REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[19]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_19REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[20]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_20REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[21]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_21REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[22]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_22REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[23]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_23REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[24]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_24REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[25]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_25REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[26]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_26REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[27]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_27REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[28]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_28REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[29]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_29REI: u1,
-            ///  Status of Rising Edge Interrupt for P0[30]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P0_30REI: u1,
-            ///  Reserved.
-            RESERVED: u1,
-        }),
-        ///  GPIO Interrupt Status for Falling edge for Port 0.
-        STATF0: mmio.Mmio(packed struct(u32) {
-            ///  Status of Falling Edge Interrupt for P0[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_0FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_1FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_2FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_3FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_4FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_5FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_6FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_7FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_8FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_9FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_10FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_11FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_12FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_13FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[14]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_14FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[15]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_15FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[16]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_16FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[17]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_17FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[18]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_18FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[19]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_19FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[20]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_20FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[21]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_21FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[22]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_22FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[23]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_23FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[24]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_24FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[25]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_25FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[26]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_26FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[27]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_27FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[28]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_28FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[29]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_29FEI: u1,
-            ///  Status of Falling Edge Interrupt for P0[30]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P0_30FEI: u1,
-            ///  Reserved.
-            RESERVED: u1,
-        }),
-        ///  GPIO Interrupt Clear.
-        CLR0: mmio.Mmio(packed struct(u32) {
-            ///  Clear GPIO port Interrupts for P0[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_0CI: u1,
-            ///  Clear GPIO port Interrupts for P0[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_1CI: u1,
-            ///  Clear GPIO port Interrupts for P0[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_2CI: u1,
-            ///  Clear GPIO port Interrupts for P0[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_3CI: u1,
-            ///  Clear GPIO port Interrupts for P0[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_4CI: u1,
-            ///  Clear GPIO port Interrupts for P0[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_5CI: u1,
-            ///  Clear GPIO port Interrupts for P0[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_6CI: u1,
-            ///  Clear GPIO port Interrupts for P0[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_7CI: u1,
-            ///  Clear GPIO port Interrupts for P0[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_8CI: u1,
-            ///  Clear GPIO port Interrupts for P0[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_9CI: u1,
-            ///  Clear GPIO port Interrupts for P0[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_10CI: u1,
-            ///  Clear GPIO port Interrupts for P0[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_11CI: u1,
-            ///  Clear GPIO port Interrupts for P0[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_12CI: u1,
-            ///  Clear GPIO port Interrupts for P0[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_13CI: u1,
-            ///  Clear GPIO port Interrupts for P0[14]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_14CI: u1,
-            ///  Clear GPIO port Interrupts for P0[15]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_15CI: u1,
-            ///  Clear GPIO port Interrupts for P0[16]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_16CI: u1,
-            ///  Clear GPIO port Interrupts for P0[17]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_17CI: u1,
-            ///  Clear GPIO port Interrupts for P0[18]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_18CI: u1,
-            ///  Clear GPIO port Interrupts for P0[19]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_19CI: u1,
-            ///  Clear GPIO port Interrupts for P0[20]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_20CI: u1,
-            ///  Clear GPIO port Interrupts for P0[21]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_21CI: u1,
-            ///  Clear GPIO port Interrupts for P0[22]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_22CI: u1,
-            ///  Clear GPIO port Interrupts for P0[23]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_23CI: u1,
-            ///  Clear GPIO port Interrupts for P0[24]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_24CI: u1,
-            ///  Clear GPIO port Interrupts for P0[25]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_25CI: u1,
-            ///  Clear GPIO port Interrupts for P0[26]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_26CI: u1,
-            ///  Clear GPIO port Interrupts for P0[27]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_27CI: u1,
-            ///  Clear GPIO port Interrupts for P0[28]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_28CI: u1,
-            ///  Clear GPIO port Interrupts for P0[29]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_29CI: u1,
-            ///  Clear GPIO port Interrupts for P0[30]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P0_30CI: u1,
-            ///  Reserved.
-            RESERVED: u1,
-        }),
-        ///  GPIO Interrupt Enable for Rising edge for Port 0.
-        ENR0: mmio.Mmio(packed struct(u32) {
-            ///  Enable rising edge interrupt for P0[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_0ER: u1,
-            ///  Enable rising edge interrupt for P0[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_1ER: u1,
-            ///  Enable rising edge interrupt for P0[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_2ER: u1,
-            ///  Enable rising edge interrupt for P0[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_3ER: u1,
-            ///  Enable rising edge interrupt for P0[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_4ER: u1,
-            ///  Enable rising edge interrupt for P0[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_5ER: u1,
-            ///  Enable rising edge interrupt for P0[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_6ER: u1,
-            ///  Enable rising edge interrupt for P0[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_7ER: u1,
-            ///  Enable rising edge interrupt for P0[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_8ER: u1,
-            ///  Enable rising edge interrupt for P0[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_9ER: u1,
-            ///  Enable rising edge interrupt for P0[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_10ER: u1,
-            ///  Enable rising edge interrupt for P0[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_11ER: u1,
-            ///  Enable rising edge interrupt for P0[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_12ER: u1,
-            ///  Enable rising edge interrupt for P0[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_13ER: u1,
-            ///  Enable rising edge interrupt for P0[14]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_14ER: u1,
-            ///  Enable rising edge interrupt for P0[15]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_15ER: u1,
-            ///  Enable rising edge interrupt for P0[16]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_16ER: u1,
-            ///  Enable rising edge interrupt for P0[17]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_17ER: u1,
-            ///  Enable rising edge interrupt for P0[18]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_18ER: u1,
-            ///  Enable rising edge interrupt for P0[19]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_19ER: u1,
-            ///  Enable rising edge interrupt for P0[20]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_20ER: u1,
-            ///  Enable rising edge interrupt for P0[21]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_21ER: u1,
-            ///  Enable rising edge interrupt for P0[22]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_22ER: u1,
-            ///  Enable rising edge interrupt for P0[23]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_23ER: u1,
-            ///  Enable rising edge interrupt for P0[24]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_24ER: u1,
-            ///  Enable rising edge interrupt for P0[25]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_25ER: u1,
-            ///  Enable rising edge interrupt for P0[26]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_26ER: u1,
-            ///  Enable rising edge interrupt for P0[27]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_27ER: u1,
-            ///  Enable rising edge interrupt for P0[28]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_28ER: u1,
-            ///  Enable rising edge interrupt for P0[29]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_29ER: u1,
-            ///  Enable rising edge interrupt for P0[30]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P0_30ER: u1,
-            ///  Reserved.
-            RESERVED: u1,
-        }),
-        ///  GPIO Interrupt Enable for Falling edge for Port 0.
-        ENF0: mmio.Mmio(packed struct(u32) {
-            ///  Enable falling edge interrupt for P0[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_0EF: u1,
-            ///  Enable falling edge interrupt for P0[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_1EF: u1,
-            ///  Enable falling edge interrupt for P0[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_2EF: u1,
-            ///  Enable falling edge interrupt for P0[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_3EF: u1,
-            ///  Enable falling edge interrupt for P0[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_4EF: u1,
-            ///  Enable falling edge interrupt for P0[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_5EF: u1,
-            ///  Enable falling edge interrupt for P0[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_6EF: u1,
-            ///  Enable falling edge interrupt for P0[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_7EF: u1,
-            ///  Enable falling edge interrupt for P0[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_8EF: u1,
-            ///  Enable falling edge interrupt for P0[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_9EF: u1,
-            ///  Enable falling edge interrupt for P0[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_10EF: u1,
-            ///  Enable falling edge interrupt for P0[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_11EF: u1,
-            ///  Enable falling edge interrupt for P0[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_12EF: u1,
-            ///  Enable falling edge interrupt for P0[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_13EF: u1,
-            ///  Enable falling edge interrupt for P0[14]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_14EF: u1,
-            ///  Enable falling edge interrupt for P0[15]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_15EF: u1,
-            ///  Enable falling edge interrupt for P0[16]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_16EF: u1,
-            ///  Enable falling edge interrupt for P0[17]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_17EF: u1,
-            ///  Enable falling edge interrupt for P0[18]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_18EF: u1,
-            ///  Enable falling edge interrupt for P0[19]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_19EF: u1,
-            ///  Enable falling edge interrupt for P0[20]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_20EF: u1,
-            ///  Enable falling edge interrupt for P0[21]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_21EF: u1,
-            ///  Enable falling edge interrupt for P0[22]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_22EF: u1,
-            ///  Enable falling edge interrupt for P0[23]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_23EF: u1,
-            ///  Enable falling edge interrupt for P0[24]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_24EF: u1,
-            ///  Enable falling edge interrupt for P0[25]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_25EF: u1,
-            ///  Enable falling edge interrupt for P0[26]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_26EF: u1,
-            ///  Enable falling edge interrupt for P0[27]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_27EF: u1,
-            ///  Enable falling edge interrupt for P0[28]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_28EF: u1,
-            ///  Enable falling edge interrupt for P0[29]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_29EF: u1,
-            ///  Enable falling edge interrupt for P0[30]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P0_30EF: u1,
-            ///  Reserved.
-            RESERVED: u1,
-        }),
-        reserved36: [12]u8,
-        ///  GPIO Interrupt Status for Rising edge for Port 0.
-        STATR2: mmio.Mmio(packed struct(u32) {
-            ///  Status of Rising Edge Interrupt for P2[0]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_0REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[1]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_1REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[2]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_2REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[3]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_3REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[4]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_4REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[5]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_5REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[6]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_6REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[7]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_7REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[8]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_8REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[9]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_9REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[10]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_10REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[11]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_11REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[12]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_12REI: u1,
-            ///  Status of Rising Edge Interrupt for P2[13]. 0 = No rising edge detected. 1 = Rising edge interrupt generated.
-            P2_13REI: u1,
-            ///  Reserved.
-            RESERVED: u18,
-        }),
-        ///  GPIO Interrupt Status for Falling edge for Port 0.
-        STATF2: mmio.Mmio(packed struct(u32) {
-            ///  Status of Falling Edge Interrupt for P2[0]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_0FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[1]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_1FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[2]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_2FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[3]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_3FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[4]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_4FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[5]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_5FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[6]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_6FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[7]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_7FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[8]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_8FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[9]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_9FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[10]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_10FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[11]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_11FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[12]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_12FEI: u1,
-            ///  Status of Falling Edge Interrupt for P2[13]. 0 = No falling edge detected. 1 = Falling edge interrupt generated.
-            P2_13FEI: u1,
-            ///  Reserved.
-            RESERVED: u18,
-        }),
-        ///  GPIO Interrupt Clear.
-        CLR2: mmio.Mmio(packed struct(u32) {
-            ///  Clear GPIO port Interrupts for P2[0]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_0CI: u1,
-            ///  Clear GPIO port Interrupts for P2[1]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_1CI: u1,
-            ///  Clear GPIO port Interrupts for P2[2]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_2CI: u1,
-            ///  Clear GPIO port Interrupts for P2[3]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_3CI: u1,
-            ///  Clear GPIO port Interrupts for P2[4]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_4CI: u1,
-            ///  Clear GPIO port Interrupts for P2[5]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_5CI: u1,
-            ///  Clear GPIO port Interrupts for P2[6]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_6CI: u1,
-            ///  Clear GPIO port Interrupts for P2[7]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_7CI: u1,
-            ///  Clear GPIO port Interrupts for P2[8]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_8CI: u1,
-            ///  Clear GPIO port Interrupts for P2[9]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_9CI: u1,
-            ///  Clear GPIO port Interrupts for P2[10]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_10CI: u1,
-            ///  Clear GPIO port Interrupts for P2[11]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_11CI: u1,
-            ///  Clear GPIO port Interrupts for P2[12]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_12CI: u1,
-            ///  Clear GPIO port Interrupts for P2[13]. 0 = No effect. 1 = Clear corresponding bits in IOnINTSTATR and IOnSTATF.
-            P2_13CI: u1,
-            ///  Reserved.
-            RESERVED: u18,
-        }),
-        ///  GPIO Interrupt Enable for Rising edge for Port 0.
-        ENR2: mmio.Mmio(packed struct(u32) {
-            ///  Enable rising edge interrupt for P2[0]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_0ER: u1,
-            ///  Enable rising edge interrupt for P2[1]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_1ER: u1,
-            ///  Enable rising edge interrupt for P2[2]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_2ER: u1,
-            ///  Enable rising edge interrupt for P2[3]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_3ER: u1,
-            ///  Enable rising edge interrupt for P2[4]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_4ER: u1,
-            ///  Enable rising edge interrupt for P2[5]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_5ER: u1,
-            ///  Enable rising edge interrupt for P2[6]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_6ER: u1,
-            ///  Enable rising edge interrupt for P2[7]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_7ER: u1,
-            ///  Enable rising edge interrupt for P2[8]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_8ER: u1,
-            ///  Enable rising edge interrupt for P2[9]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_9ER: u1,
-            ///  Enable rising edge interrupt for P2[10]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_10ER: u1,
-            ///  Enable rising edge interrupt for P2[11]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_11ER: u1,
-            ///  Enable rising edge interrupt for P2[12]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_12ER: u1,
-            ///  Enable rising edge interrupt for P2[13]. 0 = Disable rising edge interrupt. 1 = Enable rising edge interrupt.
-            P2_13ER: u1,
-            ///  Reserved.
-            RESERVED: u18,
-        }),
-        ///  GPIO Interrupt Enable for Falling edge for Port 0.
-        ENF2: mmio.Mmio(packed struct(u32) {
-            ///  Enable falling edge interrupt for P2[0]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_0EF: u1,
-            ///  Enable falling edge interrupt for P2[1]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_1EF: u1,
-            ///  Enable falling edge interrupt for P2[2]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_2EF: u1,
-            ///  Enable falling edge interrupt for P2[3]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_3EF: u1,
-            ///  Enable falling edge interrupt for P2[4]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_4EF: u1,
-            ///  Enable falling edge interrupt for P2[5]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_5EF: u1,
-            ///  Enable falling edge interrupt for P2[6]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_6EF: u1,
-            ///  Enable falling edge interrupt for P2[7]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_7EF: u1,
-            ///  Enable falling edge interrupt for P2[8]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_8EF: u1,
-            ///  Enable falling edge interrupt for P2[9]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_9EF: u1,
-            ///  Enable falling edge interrupt for P2[10]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_10EF: u1,
-            ///  Enable falling edge interrupt for P2[11]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_11EF: u1,
-            ///  Enable falling edge interrupt for P2[12]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_12EF: u1,
-            ///  Enable falling edge interrupt for P2[13]. 0 = Disable falling edge interrupt. 1 = Enable falling edge interrupt.
-            P2_13EF: u1,
-            ///  Reserved.
-            RESERVED: u18,
-        }),
-    };
-
-    ///  Pin connect block
-    pub const PINCONNECT = extern struct {
-        ///  Pin function select register 0.
-        PINSEL0: mmio.Mmio(packed struct(u32) {
-            ///  Pin function select P0.0.
-            P0_0: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.0
-                    GPIO_P0 = 0x0,
-                    ///  RD1
-                    RD1 = 0x1,
-                    ///  TXD3
-                    TXD3 = 0x2,
-                    ///  SDA1
-                    SDA1 = 0x3,
-                },
-            },
-            ///  Pin function select P0.1.
-            P0_1: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.1
-                    GPIO_P0 = 0x0,
-                    ///  TD1
-                    TD1 = 0x1,
-                    ///  RXD3
-                    RXD3 = 0x2,
-                    ///  SCL1
-                    SCL1 = 0x3,
-                },
-            },
-            ///  Pin function select P0.2.
-            P0_2: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.2
-                    GPIO_P0 = 0x0,
-                    ///  TXD0
-                    TXD0 = 0x1,
-                    ///  AD0.7
-                    AD0 = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P0.3.
-            P0_3: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.3.
-                    GPIO_P0 = 0x0,
-                    ///  RXD0
-                    RXD0 = 0x1,
-                    ///  AD0.6
-                    AD0 = 0x2,
-                    ///  Reserved.
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P0.4.
-            P0_4: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.4.
-                    GPIO_P0 = 0x0,
-                    ///  I2SRX_CLK
-                    I2SRX_CLK = 0x1,
-                    ///  RD2
-                    RD2 = 0x2,
-                    ///  CAP2.0
-                    CAP2 = 0x3,
-                },
-            },
-            ///  Pin function select P0.5.
-            P0_5: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.5.
-                    GPIO_P0 = 0x0,
-                    ///  I2SRX_WS
-                    I2SRX_WS = 0x1,
-                    ///  TD2
-                    TD2 = 0x2,
-                    ///  CAP2.1
-                    CAP2 = 0x3,
-                },
-            },
-            ///  Pin function select P0.6.
-            P0_6: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.6.
-                    GPIO_P0 = 0x0,
-                    ///  I2SRX_SDA
-                    I2SRX_SDA = 0x1,
-                    ///  SSEL1
-                    SSEL1 = 0x2,
-                    ///  MAT2.0
-                    MAT2 = 0x3,
-                },
-            },
-            ///  Pin function select P0.7.
-            P0_7: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.7.
-                    GPIO_P0 = 0x0,
-                    ///  I2STX_CLK
-                    I2STX_CLK = 0x1,
-                    ///  SCK1
-                    SCK1 = 0x2,
-                    ///  MAT2.1
-                    MAT2 = 0x3,
-                },
-            },
-            ///  Pin function select P0.8.
-            P0_8: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.8.
-                    GPIO_P0 = 0x0,
-                    ///  I2STX_WS
-                    I2STX_WS = 0x1,
-                    ///  MISO1
-                    MISO1 = 0x2,
-                    ///  MAT2.2
-                    MAT2 = 0x3,
-                },
-            },
-            ///  Pin function select P0.9.
-            P0_9: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.9
-                    GPIO_P0 = 0x0,
-                    ///  I2STX_SDA
-                    I2STX_SDA = 0x1,
-                    ///  MOSI1
-                    MOSI1 = 0x2,
-                    ///  MAT2.3
-                    MAT2 = 0x3,
-                },
-            },
-            ///  Pin function select P0.10.
-            P0_10: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.10
-                    GPIO_P0 = 0x0,
-                    ///  TXD2
-                    TXD2 = 0x1,
-                    ///  SDA2
-                    SDA2 = 0x2,
-                    ///  MAT3.0
-                    MAT3 = 0x3,
-                },
-            },
-            ///  Pin function select P0.11.
-            P0_11: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.11
-                    GPIO_P0 = 0x0,
-                    ///  RXD2
-                    RXD2 = 0x1,
-                    ///  SCL2
-                    SCL2 = 0x2,
-                    ///  MAT3.1
-                    MAT3 = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u6,
-            ///  Pin function select P0.15.
-            P0_15: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.15
-                    GPIO_P0 = 0x0,
-                    ///  TXD1
-                    TXD1 = 0x1,
-                    ///  SCK0
-                    SCK0 = 0x2,
-                    ///  SCK
-                    SCK = 0x3,
-                },
-            },
-        }),
-        ///  Pin function select register 1.
-        PINSEL1: mmio.Mmio(packed struct(u32) {
-            ///  Pin function select P0.16.
-            P0_16: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.16
-                    GPIO_P0 = 0x0,
-                    ///  RXD1
-                    RXD1 = 0x1,
-                    ///  SSEL0
-                    SSEL0 = 0x2,
-                    ///  SSEL
-                    SSEL = 0x3,
-                },
-            },
-            ///  Pin function select P0.17.
-            P0_17: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.17
-                    GPIO_P0 = 0x0,
-                    ///  CTS1
-                    CTS1 = 0x1,
-                    ///  MISO0
-                    MISO0 = 0x2,
-                    ///  MISO
-                    MISO = 0x3,
-                },
-            },
-            ///  Pin function select P0.18.
-            P0_18: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.18
-                    GPIO_P0 = 0x0,
-                    ///  DCD1
-                    DCD1 = 0x1,
-                    ///  MOSI0
-                    MOSI0 = 0x2,
-                    ///  MOSI
-                    MOSI = 0x3,
-                },
-            },
-            ///  Pin function select P019.
-            P0_19: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.19.
-                    GPIO_P0 = 0x0,
-                    ///  DSR1
-                    DSR1 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  SDA1
-                    SDA1 = 0x3,
-                },
-            },
-            ///  Pin function select P0.20.
-            P0_20: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.20.
-                    GPIO_P0 = 0x0,
-                    ///  DTR1
-                    DTR1 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  SCL1
-                    SCL1 = 0x3,
-                },
-            },
-            ///  Pin function select P0.21.
-            P0_21: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO Port 0.21.
-                    GPIO_PORT_0 = 0x0,
-                    ///  RI1
-                    RI1 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  RD1
-                    RD1 = 0x3,
-                },
-            },
-            ///  Pin function select P022
-            P0_22: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.22.
-                    GPIO_P0 = 0x0,
-                    ///  RTS1
-                    RTS1 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  TD1
-                    TD1 = 0x3,
-                },
-            },
-            ///  Pin function select P023.
-            P0_23: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.23.
-                    GPIO_P0 = 0x0,
-                    ///  AD0.0
-                    AD0 = 0x1,
-                    ///  I2SRX_CLK
-                    I2SRX_CLK = 0x2,
-                    ///  CAP3.0
-                    CAP3 = 0x3,
-                },
-            },
-            ///  Pin function select P0.24.
-            P0_24: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.24.
-                    GPIO_P0 = 0x0,
-                    ///  AD0.1
-                    AD0 = 0x1,
-                    ///  I2SRX_WS
-                    I2SRX_WS = 0x2,
-                    ///  CAP3.1
-                    CAP3 = 0x3,
-                },
-            },
-            ///  Pin function select P0.25.
-            P0_25: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.25
-                    GPIO_P0 = 0x0,
-                    ///  AD0.2
-                    AD0 = 0x1,
-                    ///  I2SRX_SDA
-                    I2SRX_SDA = 0x2,
-                    ///  TXD3
-                    TXD3 = 0x3,
-                },
-            },
-            ///  Pin function select P0.26.
-            P0_26: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.26
-                    GPIO_P0 = 0x0,
-                    ///  AD0.3
-                    AD0 = 0x1,
-                    ///  AOUT
-                    AOUT = 0x2,
-                    ///  RXD3
-                    RXD3 = 0x3,
-                },
-            },
-            ///  Pin function select P0.27.
-            P0_27: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.27
-                    GPIO_P0 = 0x0,
-                    ///  SDA0
-                    SDA0 = 0x1,
-                    ///  USB_SDA
-                    USB_SDA = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P0.28.
-            P0_28: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.28
-                    GPIO_P0 = 0x0,
-                    ///  SCL0
-                    SCL0 = 0x1,
-                    ///  USB_SCL
-                    USB_SCL = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P0.29
-            P0_29: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.29
-                    GPIO_P0 = 0x0,
-                    ///  USB_D+
-                    USB_DP = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P0.30.
-            P0_30: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P0.30
-                    GPIO_P0 = 0x0,
-                    ///  USB_D-
-                    USB_DM = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Reserved
-            RESERVED: u2,
-        }),
-        ///  Pin function select register 2.
-        PINSEL2: mmio.Mmio(packed struct(u32) {
-            ///  Pin function select P1.0.
-            P1_0: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.0
-                    GPIO_P1 = 0x0,
-                    ///  ENET_TXD0
-                    ENET_TXD0 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P1.1.
-            P1_1: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.1
-                    GPIO_P1 = 0x0,
-                    ///  ENET_TXD1
-                    ENET_TXD1 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u4,
-            ///  Pin function select P1.4.
-            P1_4: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.4.
-                    GPIO_P1 = 0x0,
-                    ///  ENET_TX_EN
-                    ENET_TX_EN = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u6,
-            ///  Pin function select P1.8.
-            P1_8: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.8.
-                    GPIO_P1 = 0x0,
-                    ///  ENET_CRS
-                    ENET_CRS = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P1.9.
-            P1_9: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO Port 1.9
-                    GPIO_PORT_1 = 0x0,
-                    ///  ENET_RXD0
-                    ENET_RXD0 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P1.10.
-            P1_10: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.10
-                    GPIO_P1 = 0x0,
-                    ///  ENET_RXD1
-                    ENET_RXD1 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P1.14.
-            P1_14: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.14
-                    GPIO_P1 = 0x0,
-                    ///  ENET_RX_ER
-                    ENET_RX_ER = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u6,
-            ///  Pin function select P1.15.
-            P1_15: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.15
-                    GPIO_P1 = 0x0,
-                    ///  ENET_REF_CLK
-                    ENET_REF_CLK = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-        }),
-        ///  Pin function select register 3.
-        PINSEL3: mmio.Mmio(packed struct(u32) {
-            ///  Pin function select P1.16.
-            P1_16: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.16
-                    GPIO_P1 = 0x0,
-                    ///  ENET_MDC
-                    ENET_MDC = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P1.17.
-            P1_17: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.17
-                    GPIO_P1 = 0x0,
-                    ///  ENET_MDIO
-                    ENET_MDIO = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P1.18.
-            P1_18: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.18
-                    GPIO_P1 = 0x0,
-                    ///  USB_UP_LED
-                    USB_UP_LED = 0x1,
-                    ///  PWM1.1
-                    PWM1 = 0x2,
-                    ///  CAP1.0
-                    CAP1 = 0x3,
-                },
-            },
-            ///  Pin function select P1.19.
-            P1_19: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.19.
-                    GPIO_P1 = 0x0,
-                    ///  MCOA0
-                    MCOA0 = 0x1,
-                    ///  USB_PPWR
-                    USB_PPWR = 0x2,
-                    ///  CAP1.1
-                    CAP1 = 0x3,
-                },
-            },
-            ///  Pin function select P1.20.
-            P1_20: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.20.
-                    GPIO_P1 = 0x0,
-                    ///  MCI0
-                    MCI0 = 0x1,
-                    ///  PWM1.2
-                    PWM1 = 0x2,
-                    ///  SCK0
-                    SCK0 = 0x3,
-                },
-            },
-            ///  Pin function select P1.21.
-            P1_21: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.21.
-                    GPIO_P1 = 0x0,
-                    ///  MCABORT
-                    MCABORT = 0x1,
-                    ///  PWM1.3
-                    PWM1 = 0x2,
-                    ///  SSEL0
-                    SSEL0 = 0x3,
-                },
-            },
-            ///  Pin function select P1.22
-            P1_22: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.22.
-                    GPIO_P1 = 0x0,
-                    ///  MCOB0
-                    MCOB0 = 0x1,
-                    ///  USB_PWRD
-                    USB_PWRD = 0x2,
-                    ///  MAT1.0
-                    MAT1 = 0x3,
-                },
-            },
-            ///  Pin function select P1.23.
-            P1_23: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.23.
-                    GPIO_P1 = 0x0,
-                    ///  MCI1
-                    MCI1 = 0x1,
-                    ///  PWM1.4
-                    PWM1 = 0x2,
-                    ///  MISO0
-                    MISO0 = 0x3,
-                },
-            },
-            ///  Pin function select P1.24.
-            P1_24: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.24.
-                    GPIO_P1 = 0x0,
-                    ///  MCI2
-                    MCI2 = 0x1,
-                    ///  PWM1.5
-                    PWM1 = 0x2,
-                    ///  MOSI0
-                    MOSI0 = 0x3,
-                },
-            },
-            ///  Pin function select P1.25.
-            P1_25: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.25
-                    GPIO_P1 = 0x0,
-                    ///  MCOA1
-                    MCOA1 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  MAT1.1
-                    MAT1 = 0x3,
-                },
-            },
-            ///  Pin function select P1.26.
-            P1_26: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.26
-                    GPIO_P1 = 0x0,
-                    ///  MCOB1
-                    MCOB1 = 0x1,
-                    ///  PWM1.6
-                    PWM1 = 0x2,
-                    ///  CAP0.0
-                    CAP0 = 0x3,
-                },
-            },
-            ///  Pin function select P1.27.
-            P1_27: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.27
-                    GPIO_P1 = 0x0,
-                    ///  CLKOUT
-                    CLKOUT = 0x1,
-                    ///  USB_OVRCR
-                    USB_OVRCR = 0x2,
-                    ///  CAP0.1
-                    CAP0 = 0x3,
-                },
-            },
-            ///  Pin function select P1.28.
-            P1_28: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.28
-                    GPIO_P1 = 0x0,
-                    ///  MCOA2
-                    MCOA2 = 0x1,
-                    ///  PCAP1.0
-                    PCAP1 = 0x2,
-                    ///  MAT0.0
-                    MAT0 = 0x3,
-                },
-            },
-            ///  Pin function select P1.29
-            P1_29: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.29
-                    GPIO_P1 = 0x0,
-                    ///  MCOB2
-                    MCOB2 = 0x1,
-                    ///  PCAP1.1
-                    PCAP1 = 0x2,
-                    ///  MAT0.1
-                    MAT0 = 0x3,
-                },
-            },
-            ///  Pin function select P1.30.
-            P1_30: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P1.30
-                    GPIO_P1 = 0x0,
-                    ///  Reserved
-                    RESERVED = 0x1,
-                    ///  VBUS
-                    VBUS = 0x2,
-                    ///  AD0.4
-                    AD0 = 0x3,
-                },
-            },
-            ///  Pin function select P1.31.
-            P1_31: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO Port 1.31
-                    GPIO_PORT_1 = 0x0,
-                    ///  Reserved
-                    RESERVED = 0x1,
-                    ///  SCK1
-                    SCK1 = 0x2,
-                    ///  AD0.5
-                    AD0 = 0x3,
-                },
-            },
-        }),
-        ///  Pin function select register 4
-        PINSEL4: mmio.Mmio(packed struct(u32) {
-            ///  Pin function select P2.0.
-            P2_0: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.0
-                    GPIO_P2 = 0x0,
-                    ///  PWM1.1
-                    PWM1 = 0x1,
-                    ///  TXD1
-                    TXD1 = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P2.1.
-            P2_1: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.1
-                    GPIO_P2 = 0x0,
-                    ///  PWM1.2
-                    PWM1 = 0x1,
-                    ///  RXD1
-                    RXD1 = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P2.2.
-            P2_2: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.2
-                    GPIO_P2 = 0x0,
-                    ///  PWM1.3
-                    PWM1 = 0x1,
-                    ///  CTS1
-                    CTS1 = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P2.3.
-            P2_3: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.3.
-                    GPIO_P2 = 0x0,
-                    ///  PWM1.4
-                    PWM1 = 0x1,
-                    ///  DCD1
-                    DCD1 = 0x2,
-                    ///  Reserved.
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P2.4.
-            P2_4: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.4.
-                    GPIO_P2 = 0x0,
-                    ///  PWM1.5
-                    PWM1 = 0x1,
-                    ///  DSR1
-                    DSR1 = 0x2,
-                    ///  Reserved.
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P2.5.
-            P2_5: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.5.
-                    GPIO_P2 = 0x0,
-                    ///  PWM1.6
-                    PWM1 = 0x1,
-                    ///  DTR1
-                    DTR1 = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P2.6.
-            P2_6: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.6.
-                    GPIO_P2 = 0x0,
-                    ///  PCAP1.0
-                    PCAP1 = 0x1,
-                    ///  RI1
-                    RI1 = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P2.7.
-            P2_7: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.7.
-                    GPIO_P2 = 0x0,
-                    ///  RD2
-                    RD2 = 0x1,
-                    ///  RTS1
-                    RTS1 = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P2.8.
-            P2_8: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.8.
-                    GPIO_P2 = 0x0,
-                    ///  TD2
-                    TD2 = 0x1,
-                    ///  TXD2
-                    TXD2 = 0x2,
-                    ///  ENET_MDC
-                    ENET_MDC = 0x3,
-                },
-            },
-            ///  Pin function select P2.9.
-            P2_9: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.9
-                    GPIO_P2 = 0x0,
-                    ///  USB_CONNECT
-                    USB_CONNECT = 0x1,
-                    ///  RXD2
-                    RXD2 = 0x2,
-                    ///  ENET_MDIO
-                    ENET_MDIO = 0x3,
-                },
-            },
-            ///  Pin function select P2.10.
-            P2_10: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.10
-                    GPIO_P2 = 0x0,
-                    ///  EINT0
-                    EINT0 = 0x1,
-                    ///  NMI
-                    NMI = 0x2,
-                    ///  Reserved
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Pin function select P2.11.
-            P2_11: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.11
-                    GPIO_P2 = 0x0,
-                    ///  EINT1
-                    EINT1 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  I2STX_CLK
-                    I2STX_CLK = 0x3,
-                },
-            },
-            ///  Pin function select P2.12.
-            P2_12: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.12
-                    GPIO_P2 = 0x0,
-                    ///  EINT2
-                    EINT2 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  I2STX_WS
-                    I2STX_WS = 0x3,
-                },
-            },
-            ///  Pin function select P2.13.
-            P2_13: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P2.13
-                    GPIO_P2 = 0x0,
-                    ///  EINT3
-                    EINT3 = 0x1,
-                    ///  Reserved
-                    RESERVED = 0x2,
-                    ///  I2STX_SDA
-                    I2STX_SDA = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u4,
-        }),
-        reserved28: [8]u8,
-        ///  Pin function select register 7
-        PINSEL7: mmio.Mmio(packed struct(u32) {
-            ///  Reserved.
-            RESERVED: u18,
-            ///  Pin function select P3.25.
-            P3_25: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P3.25
-                    GPIO_P3 = 0x0,
-                    ///  Reserved
-                    RESERVED = 0x1,
-                    ///  MAT0.0
-                    MAT0 = 0x2,
-                    ///  PWM1.2
-                    PWM1 = 0x3,
-                },
-            },
-            ///  Pin function select P3.26.
-            P3_26: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P3.26
-                    GPIO_P3 = 0x0,
-                    ///  STCLK
-                    STCLK = 0x1,
-                    ///  MAT0.1
-                    MAT0 = 0x2,
-                    ///  PWM1.3
-                    PWM1 = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u10,
-        }),
-        reserved36: [4]u8,
-        ///  Pin function select register 9
-        PINSEL9: mmio.Mmio(packed struct(u32) {
-            ///  Reserved.
-            RESERVED: u24,
-            ///  Pin function select P4.28.
-            P4_28: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P4.28
-                    GPIO_P4 = 0x0,
-                    ///  RX_MCLK
-                    RX_MCLK = 0x1,
-                    ///  MAT2.0
-                    MAT2 = 0x2,
-                    ///  TXD3
-                    TXD3 = 0x3,
-                },
-            },
-            ///  Pin function select P4.29.
-            P4_29: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  GPIO P4.29
-                    GPIO_P4 = 0x0,
-                    ///  TX_MCLK
-                    TX_MCLK = 0x1,
-                    ///  MAT2.1
-                    MAT2 = 0x2,
-                    ///  RXD3
-                    RXD3 = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u4,
-        }),
-        ///  Pin function select register 10
-        PINSEL10: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Software should not write 1 to these bits.
-            RESERVED: u3,
-            ///  TPIU interface pins control.
-            TPIUCTRL: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled. TPIU interface is disabled.
-                    DISABLED = 0x0,
-                    ///  Enabled. TPIU interface is enabled. TPIU signals are available on the pins hosting them regardless of the PINSEL4 content.
-                    ENABLED = 0x1,
-                },
-            },
-            ///  Reserved. Software should not write 1 to these bits.
-            RESERVED: u28,
-        }),
-        reserved64: [20]u8,
-        ///  Pin mode select register 0
-        PINMODE0: mmio.Mmio(packed struct(u32) {
-            ///  Port 0 pin 0 on-chip pull-up/down resistor control.
-            P0_00MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.0 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.0 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.0 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.0 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 0 pin 1 control.
-            P0_01MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.1 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.1 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.1 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.1 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 0 pin 2 control.
-            P0_02MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.2 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.2 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.2 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.2 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 0 pin 3 control.
-            P0_03MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.3 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.3 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.3 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.3 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 0 pin 4 control.
-            P0_04MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.4 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.4 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.4 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.4 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 0 pin 5 control.
-            P0_05MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.5 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.5 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.5 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.5 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 0 pin 6 control.
-            P0_06MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.6 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Disabled. Repeater. P0.6 pin has repeater mode enabled.
-                    DISABLED = 0x1,
-                    ///  Disabled. P0.6 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.6 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 0 pin 7 control.
-            P0_07MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.7 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.7 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.7 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.7 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 0 pin 8 control.
-            P0_08MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.8 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.8 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.8 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.8 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 0 pin 9 control.
-            P0_09MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.9 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.9 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.9 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.9 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 0 pin 10 control.
-            P0_10MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.10 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.10 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.10 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.10 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 0 pin 11 control.
-            P0_11MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.11 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.11 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.11 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.11 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u6,
-            ///  Port 0 pin 15 control.
-            P0_15MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.15 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.15 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.15 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.15 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-        }),
-        ///  Pin mode select register 1
-        PINMODE1: mmio.Mmio(packed struct(u32) {
-            ///  Port 1 pin 16 control.
-            P0_16MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.16 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.16 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.16 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.16 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 17 control.
-            P0_17MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.17 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.17 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.17 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.17 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 18 control.
-            P0_18MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.18 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.18 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.18 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.18 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 19 control.
-            P0_19MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.19 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.19 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.19 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.19 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 20 control.
-            P0_20MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.20 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.20 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.20 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.20 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 21 control.
-            P0_21MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.21 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.21 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.21 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.21 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 22 control.
-            P0_22MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.22 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.22 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.22 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.22 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 23 control.
-            P0_23MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.23 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.23 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.23 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.23 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 24 control.
-            P0_24MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.24 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.24 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.24 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.24 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 25 control.
-            P0_25MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.25 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.25 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.25 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.25 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 26 control.
-            P0_26MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P0.26 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P0.26 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P0.26 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P0.26 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u8,
-            ///  Reserved.
-            RESERVED: u2,
-        }),
-        ///  Pin mode select register 2
-        PINMODE2: mmio.Mmio(packed struct(u32) {
-            ///  Port 1 pin 0 control.
-            P1_00MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.0 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.0 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.0 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.0 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 1 control.
-            P1_01MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.1 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.1 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.1 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.1 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u4,
-            ///  Port 1 pin 4 control.
-            P1_04MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.4 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.4 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.4 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.4 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u6,
-            ///  Port 1 pin 8 control.
-            P1_08MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.8 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.8 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.8 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.8 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 9 control.
-            P1_09MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.9 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.9 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.9 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.9 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 10 control.
-            P1_10MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.10 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.10 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.10 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.10 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u6,
-            ///  Port 1 pin 14 control.
-            P1_14MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.14 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.14 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.14 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.14 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 15 control.
-            P1_15MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.15 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.15 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.15 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.15 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-        }),
-        ///  Pin mode select register 3.
-        PINMODE3: mmio.Mmio(packed struct(u32) {
-            ///  Port 1 pin 16 control.
-            P1_16MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.16 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.16 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.16 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.16 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 17 control.
-            P1_17MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.17 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.17 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.17 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.17 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 18 control.
-            P1_18MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.18 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.18 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.18 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.18 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 19 control.
-            P1_19MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.19 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.19 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.19 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.19 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 20 control.
-            P1_20MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.20 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.20 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.20 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.20 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 21 control.
-            P1_21MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.21 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.21 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.21 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.21 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 22 control.
-            P1_22MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.22 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.22 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.22 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.22 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 23 control.
-            P1_23MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.23 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.23 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.23 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.23 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 24 control.
-            P1_24MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.24 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.24 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.24 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.24 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 25 control.
-            P1_25MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.25 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.25 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.25 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.25 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 26 control.
-            P1_26MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.26 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.26 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.26 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.26 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 27 control.
-            P1_27MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.27 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.27 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.27 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.27 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 28 control.
-            P1_28MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.28 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.28 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.28 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.28 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 29 control.
-            P1_29MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.29 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.29 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.29 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.29 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 30 control.
-            P1_30MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.30 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.30 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.30 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.30 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 1 pin 31 control.
-            P1_31MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P1.31 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P1.31 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P1.31 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P1.31 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-        }),
-        ///  Pin mode select register 4
-        PINMODE4: mmio.Mmio(packed struct(u32) {
-            ///  Port 2 pin 0 control.
-            P2_00MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.0 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.0 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.0 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.0 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 1 control.
-            P2_01MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.1 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.1 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.1 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.1 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 2 control.
-            P2_02MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.2 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.2 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.2 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.2 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 3 control.
-            P2_03MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.3 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.3 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.3 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.3 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 4 control.
-            P2_04MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.4 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.4 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.4 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.4 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 5 control.
-            P2_05MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.5 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.5 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.5 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.5 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 6 control.
-            P2_06MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.6 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.6 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.6 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.6 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 7 control.
-            P2_07MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.7 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.7 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.7 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.7 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 8 control.
-            P2_08MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.8 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.8 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.8 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.8 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 9 control.
-            P2_09MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.9 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.9 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.9 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.9 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 10 control.
-            P2_10MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.10 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.10 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.10 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.10 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 11 control.
-            P2_11MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.11 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.11 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.11 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.11 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 12 control.
-            P2_12MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.12 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.12 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.12 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.12 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 2 pin 13 control.
-            P2_13MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P2.13 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P2.13 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P2.13 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P2.13 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u4,
-        }),
-        reserved92: [8]u8,
-        ///  Pin mode select register 7
-        PINMODE7: mmio.Mmio(packed struct(u32) {
-            ///  Reserved
-            RESERVED: u18,
-            ///  Port 3 pin 25 control.
-            P3_25MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P3.25 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P3.25 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P3.25 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P3.25 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 3 pin 26 control.
-            P3_26MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P3.26 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P3.26 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P3.26 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P3.26 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u10,
-        }),
-        reserved100: [4]u8,
-        ///  Pin mode select register 9
-        PINMODE9: mmio.Mmio(packed struct(u32) {
-            ///  Reserved.
-            RESERVED: u24,
-            ///  Port 4 pin 28 control.
-            P4_28MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P4.28 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P4.28 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P4.28 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P4.28 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Port 4 pin 29 control.
-            P4_29MODE: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Pull-up. P4.29 pin has a pull-up resistor enabled.
-                    PULL_UP = 0x0,
-                    ///  Repeater. P4.29 pin has repeater mode enabled.
-                    REPEATER = 0x1,
-                    ///  Disabled. P4.29 pin has neither pull-up nor pull-down.
-                    DISABLED = 0x2,
-                    ///  Pull-down. P4.29 has a pull-down resistor enabled.
-                    PULL_DOWN = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u4,
-        }),
-        ///  Open drain mode control register 0
-        PINMODE_OD0: mmio.Mmio(packed struct(u32) {
-            ///  Port 0 pin 0 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
-            P0_00OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.0 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.0 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 1 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
-            P0_01OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.1 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.1 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 2 open drain mode control
-            P0_02OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.2 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.2 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 3 open drain mode control
-            P0_03OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.3 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.3 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 4 open drain mode control
-            P0_04OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.4 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.4 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 5 open drain mode control
-            P0_05OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.5 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.5 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 6 open drain mode control
-            P0_06OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.6 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.6 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 7 open drain mode control
-            P0_07OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.7 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.7 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 8 open drain mode control
-            P0_08OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.8 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.8 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 9 open drain mode control
-            P0_09OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.9 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.9 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 10 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
-            P0_10OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.10 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.10 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 11 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
-            P0_11OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.11 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.11 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u3,
-            ///  Port 0 pin 15 open drain mode control
-            P0_15OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.15 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.15 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 16 open drain mode control
-            P0_16OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.16 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.16 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 17 open drain mode control
-            P0_17OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.17 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.17 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 18 open drain mode control
-            P0_18OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.18 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.18 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 19 open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
-            P0_19OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.19 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.19 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 20open drain mode control. Pins may potentially be used for I2C-buses using standard port pins. If so, they should be configured for open drain mode via the related bits in PINMODE_OD0.
-            P0_20OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.20 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.20 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 21 open drain mode control
-            P0_21OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.21 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.21 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 22 open drain mode control
-            P0_22OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.22 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.22 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 23 open drain mode control
-            P0_23OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.23 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.23 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 24open drain mode control
-            P0_24OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.23 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.23 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 25 open drain mode control
-            P0_25OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.25 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.25 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 26 open drain mode control
-            P0_26OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.26 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.26 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u2,
-            ///  Port 0 pin 29 open drain mode control
-            P0_29OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.29 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.29 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 0 pin 30 open drain mode control
-            P0_30OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P0.30 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P0.30 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u1,
-        }),
-        ///  Open drain mode control register 1
-        PINMODE_OD1: mmio.Mmio(packed struct(u32) {
-            ///  Port 1 pin 0 open drain mode control.
-            P1_00OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.0 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.0 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 1 open drain mode control, see P1.00OD
-            P1_01OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.1 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.1 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u2,
-            ///  Port 1 pin 4 open drain mode control, see P1.00OD
-            P1_04OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.4 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.4 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u3,
-            ///  Port 1 pin 8 open drain mode control, see P1.00OD
-            P1_08OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.8 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.8 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 9 open drain mode control, see P1.00OD
-            P1_09OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.9 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.9 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 10 open drain mode control, see P1.00OD
-            P1_10OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.10 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.10 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u3,
-            ///  Port 1 pin 14 open drain mode control, see P1.00OD
-            P1_14OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.14 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.14 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 15 open drain mode control, see P1.00OD
-            P1_15OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.15 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.15 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 16 open drain mode control, see P1.00OD
-            P1_16OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.16 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.16 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 17 open drain mode control, see P1.00OD
-            P1_17OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.17 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.17 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 18 open drain mode control, see P1.00OD
-            P1_18OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.18 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.18 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 19 open drain mode control, see P1.00OD
-            P1_19OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.19 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.19 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 20open drain mode control, see P1.00OD
-            P1_20OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.20 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.20 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 21 open drain mode control, see P1.00OD
-            P1_21OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.21 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.21 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 22 open drain mode control, see P1.00OD
-            P1_22OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.22 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.22 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 23 open drain mode control, see P1.00OD
-            P1_23OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.23 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.23 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 24open drain mode control, see P1.00OD
-            P1_24OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.24 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.24 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 25 open drain mode control, see P1.00OD
-            P1_25OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.25 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.25 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 26 open drain mode control, see P1.00OD
-            P1_26OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.26 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.26 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 27 open drain mode control, see P1.00OD
-            P1_27OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.27 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.27 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 28 open drain mode control, see P1.00OD
-            P1_28OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.28 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.28 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 29 open drain mode control, see P1.00OD
-            P1_29OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.29 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.29 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 30 open drain mode control, see P1.00OD
-            P1_30OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.30 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.30 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 1 pin 31 open drain mode control.
-            P1_31OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P1.31 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P1.31 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-        }),
-        ///  Open drain mode control register 2
-        PINMODE_OD2: mmio.Mmio(packed struct(u32) {
-            ///  Port 2 pin 0 open drain mode control.
-            P2_00OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.0 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.0 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 1 open drain mode control, see P2.00OD
-            P2_01OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.1 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.1p in is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 2 open drain mode control, see P2.00OD
-            P2_02OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.2 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.2 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 3 open drain mode control, see P2.00OD
-            P2_03OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.3 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.3 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 4 open drain mode control, see P2.00OD
-            P2_04OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.4 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.4 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 5 open drain mode control, see P2.00OD
-            P2_05OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.5 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.5 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 6 open drain mode control, see P2.00OD
-            P2_06OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.6 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.6 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 7 open drain mode control, see P2.00OD
-            P2_07OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.7 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.7 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 8 open drain mode control, see P2.00OD
-            P2_08OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.8 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.8 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 9 open drain mode control, see P2.00OD
-            P2_09OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.9 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.9 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 10 open drain mode control, see P2.00OD
-            P2_10OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.10 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.10 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 11 open drain mode control, see P2.00OD
-            P2_11OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.11 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.11 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 12 open drain mode control, see P2.00OD
-            P2_12OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.12 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.12 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 2 pin 13 open drain mode control, see P2.00OD
-            P2_13OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P2.13 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P2.13 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u18,
-        }),
-        ///  Open drain mode control register 3
-        PINMODE_OD3: mmio.Mmio(packed struct(u32) {
-            ///  Reserved.
-            RESERVED: u25,
-            ///  Port 3 pin 25 open drain mode control.
-            P3_25OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P3.25 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P3.25 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 3 pin 26 open drain mode control, see P3.25OD
-            P3_26OD: u1,
-            ///  Reserved.
-            RESERVED: u5,
-        }),
-        ///  Open drain mode control register 4
-        PINMODE_OD4: mmio.Mmio(packed struct(u32) {
-            ///  Reserved.
-            RESERVED: u28,
-            ///  Port 4 pin 28 open drain mode control.
-            P4_28OD: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. P4.28 pin is in the normal (not open drain) mode.
-                    NORMAL = 0x0,
-                    ///  Open-drain. P4.28 pin is in the open drain mode.
-                    OPEN_DRAIN = 0x1,
-                },
-            },
-            ///  Port 4 pin 29 open drain mode control, see P4.28OD
-            P4_29OD: u1,
-            ///  Reserved.
-            RESERVED: u2,
-        }),
-        ///  I2C Pin Configuration register
-        I2CPADCFG: mmio.Mmio(packed struct(u32) {
-            ///  Drive mode control for the SDA0 pin, P0.27.
-            SDADRV0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Standard. The SDA0 pin is in the standard drive mode.
-                    STANDARD = 0x0,
-                    ///  Fast-mode plus. The SDA0 pin is in Fast Mode Plus drive mode.
-                    FAST_MODE_PLUS = 0x1,
-                },
-            },
-            ///  I 2C filter mode control for the SDA0 pin, P0.27.
-            SDAI2C0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Enabled. The SDA0 pin has I2C glitch filtering and slew rate control enabled.
-                    ENABLED = 0x0,
-                    ///  Disabled. The SDA0 pin has I2C glitch filtering and slew rate control disabled.
-                    DISABLED = 0x1,
-                },
-            },
-            ///  Drive mode control for the SCL0 pin, P0.28.
-            SCLDRV0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Standard. The SCL0 pin is in the standard drive mode.
-                    STANDARD = 0x0,
-                    ///  Fast-mode plus. The SCL0 pin is in Fast Mode Plus drive mode.
-                    FAST_MODE_PLUS = 0x1,
-                },
-            },
-            ///  I 2C filter mode control for the SCL0 pin, P0.28.
-            SCLI2C0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Enabled. The SCL0 pin has I2C glitch filtering and slew rate control enabled.
-                    ENABLED = 0x0,
-                    ///  Disabled. The SCL0 pin has I2C glitch filtering and slew rate control disabled.
-                    DISABLED = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u28,
-        }),
-    };
-
-    ///  SSP1 controller
-    pub const SSP1 = extern struct {
-        ///  Control Register 0. Selects the serial clock rate, bus type, and data size.
-        CR0: mmio.Mmio(packed struct(u32) {
-            ///  Data Size Select. This field controls the number of bits transferred in each frame. Values 0000-0010 are not supported and should not be used.
-            DSS: packed union {
-                raw: u4,
-                value: enum(u4) {
-                    ///  4-bit transfer
-                    @"4_BIT_TRANSFER" = 0x3,
-                    ///  5-bit transfer
-                    @"5_BIT_TRANSFER" = 0x4,
-                    ///  6-bit transfer
-                    @"6_BIT_TRANSFER" = 0x5,
-                    ///  7-bit transfer
-                    @"7_BIT_TRANSFER" = 0x6,
-                    ///  8-bit transfer
-                    @"8_BIT_TRANSFER" = 0x7,
-                    ///  9-bit transfer
-                    @"9_BIT_TRANSFER" = 0x8,
-                    ///  10-bit transfer
-                    @"10_BIT_TRANSFER" = 0x9,
-                    ///  11-bit transfer
-                    @"11_BIT_TRANSFER" = 0xa,
-                    ///  12-bit transfer
-                    @"12_BIT_TRANSFER" = 0xb,
-                    ///  13-bit transfer
-                    @"13_BIT_TRANSFER" = 0xc,
-                    ///  14-bit transfer
-                    @"14_BIT_TRANSFER" = 0xd,
-                    ///  15-bit transfer
-                    @"15_BIT_TRANSFER" = 0xe,
-                    ///  16-bit transfer
-                    @"16_BIT_TRANSFER" = 0xf,
-                    _,
-                },
-            },
-            ///  Frame Format.
-            FRF: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  SPI
-                    SPI = 0x0,
-                    ///  TI
-                    TI = 0x1,
-                    ///  Microwire
-                    MICROWIRE = 0x2,
-                    ///  This combination is not supported and should not be used.
-                    THIS_COMBINATION_IS_ = 0x3,
-                },
-            },
-            ///  Clock Out Polarity. This bit is only used in SPI mode.
-            CPOL: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  SSP controller maintains the bus clock low between frames.
-                    BUS_LOW = 0x0,
-                    ///  SSP controller maintains the bus clock high between frames.
-                    BUS_HIGH = 0x1,
-                },
-            },
-            ///  Clock Out Phase. This bit is only used in SPI mode.
-            CPHA: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  SSP controller captures serial data on the first clock transition of the frame, that is, the transition away from the inter-frame state of the clock line.
-                    FIRST_CLOCK = 0x0,
-                    ///  SSP controller captures serial data on the second clock transition of the frame, that is, the transition back to the inter-frame state of the clock line.
-                    SECOND_CLOCK = 0x1,
-                },
-            },
-            ///  Serial Clock Rate. The number of prescaler-output clocks per bit on the bus, minus one. Given that CPSDVSR is the prescale divider, and the APB clock PCLK clocks the prescaler, the bit frequency is PCLK / (CPSDVSR X [SCR+1]).
-            SCR: u8,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u16,
-        }),
-        ///  Control Register 1. Selects master/slave and other modes.
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Loop Back Mode.
-            LBM: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  During normal operation.
-                    NORMAL = 0x0,
-                    ///  Serial input is taken from the serial output (MOSI or MISO) rather than the serial input pin (MISO or MOSI respectively).
-                    OUPTU = 0x1,
-                },
-            },
-            ///  SSP Enable.
-            SSE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The SSP controller is disabled.
-                    DISABLED = 0x0,
-                    ///  The SSP controller will interact with other devices on the serial bus. Software should write the appropriate control information to the other SSP registers and interrupt controller registers, before setting this bit.
-                    ENABLED = 0x1,
-                },
-            },
-            ///  Master/Slave Mode.This bit can only be written when the SSE bit is 0.
-            MS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The SSP controller acts as a master on the bus, driving the SCLK, MOSI, and SSEL lines and receiving the MISO line.
-                    MASTER = 0x0,
-                    ///  The SSP controller acts as a slave on the bus, driving MISO line and receiving SCLK, MOSI, and SSEL lines.
-                    SLAVE = 0x1,
-                },
-            },
-            ///  Slave Output Disable. This bit is relevant only in slave mode (MS = 1). If it is 1, this blocks this SSP controller from driving the transmit data line (MISO).
-            SOD: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        ///  Data Register. Writes fill the transmit FIFO, and reads empty the receive FIFO.
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Write: software can write data to be sent in a future frame to this register whenever the TNF bit in the Status register is 1, indicating that the Tx FIFO is not full. If the Tx FIFO was previously empty and the SSP controller is not busy on the bus, transmission of the data will begin immediately. Otherwise the data written to this register will be sent as soon as all previous data has been sent (and received). If the data length is less than 16 bits, software must right-justify the data written to this register. Read: software can read data from this register whenever the RNE bit in the Status register is 1, indicating that the Rx FIFO is not empty. When software reads this register, the SSP controller returns data from the least recent frame in the Rx FIFO. If the data length is less than 16 bits, the data is right-justified in this field with higher order bits filled with 0s.
-            DATA: u16,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u16,
-        }),
-        ///  Status Register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Transmit FIFO Empty. This bit is 1 is the Transmit FIFO is empty, 0 if not.
-            TFE: u1,
-            ///  Transmit FIFO Not Full. This bit is 0 if the Tx FIFO is full, 1 if not.
-            TNF: u1,
-            ///  Receive FIFO Not Empty. This bit is 0 if the Receive FIFO is empty, 1 if not.
-            RNE: u1,
-            ///  Receive FIFO Full. This bit is 1 if the Receive FIFO is full, 0 if not.
-            RFF: u1,
-            ///  Busy. This bit is 0 if the SSPn controller is idle, or 1 if it is currently sending/receiving a frame and/or the Tx FIFO is not empty.
-            BSY: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u27,
-        }),
-        ///  Clock Prescale Register
-        CPSR: mmio.Mmio(packed struct(u32) {
-            ///  This even value between 2 and 254, by which PCLK is divided to yield the prescaler output clock. Bit 0 always reads as 0.
-            CPSDVSR: u8,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  Interrupt Mask Set and Clear Register
-        IMSC: mmio.Mmio(packed struct(u32) {
-            ///  Software should set this bit to enable interrupt when a Receive Overrun occurs, that is, when the Rx FIFO is full and another frame is completely received. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
-            RORIM: u1,
-            ///  Software should set this bit to enable interrupt when a Receive Time-out condition occurs. A Receive Time-out occurs when the Rx FIFO is not empty, and no has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
-            RTIM: u1,
-            ///  Software should set this bit to enable interrupt when the Rx FIFO is at least half full.
-            RXIM: u1,
-            ///  Software should set this bit to enable interrupt when the Tx FIFO is at least half empty.
-            TXIM: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        ///  Raw Interrupt Status Register
-        RIS: mmio.Mmio(packed struct(u32) {
-            ///  This bit is 1 if another frame was completely received while the RxFIFO was full. The ARM spec implies that the preceding frame data is overwritten by the new frame data when this occurs.
-            RORRIS: u1,
-            ///  This bit is 1 if the Rx FIFO is not empty, and has not been read for a time-out period. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
-            RTRIS: u1,
-            ///  This bit is 1 if the Rx FIFO is at least half full.
-            RXRIS: u1,
-            ///  This bit is 1 if the Tx FIFO is at least half empty.
-            TXRIS: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        ///  Masked Interrupt Status Register
-        MIS: mmio.Mmio(packed struct(u32) {
-            ///  This bit is 1 if another frame was completely received while the RxFIFO was full, and this interrupt is enabled.
-            RORMIS: u1,
-            ///  This bit is 1 if the Rx FIFO is not empty, has not been read for a time-out period, and this interrupt is enabled. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR X [SCR+1]).
-            RTMIS: u1,
-            ///  This bit is 1 if the Rx FIFO is at least half full, and this interrupt is enabled.
-            RXMIS: u1,
-            ///  This bit is 1 if the Tx FIFO is at least half empty, and this interrupt is enabled.
-            TXMIS: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        ///  SSPICR Interrupt Clear Register
-        ICR: mmio.Mmio(packed struct(u32) {
-            ///  Writing a 1 to this bit clears the frame was received when RxFIFO was full interrupt.
-            RORIC: u1,
-            ///  Writing a 1 to this bit clears the Rx FIFO was not empty and has not been read for a time-out period interrupt. The time-out period is the same for master and slave modes and is determined by the SSP bit rate: 32 bits at PCLK / (CPSDVSR / [SCR+1]).
-            RTIC: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u30,
-        }),
-        ///  SSP0 DMA control register
-        DMACR: mmio.Mmio(packed struct(u32) {
-            ///  Receive DMA Enable. When this bit is set to one 1, DMA for the receive FIFO is enabled, otherwise receive DMA is disabled.
-            RXDMAE: u1,
-            ///  Transmit DMA Enable. When this bit is set to one 1, DMA for the transmit FIFO is enabled, otherwise transmit DMA is disabled
-            TXDMAE: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u30,
-        }),
-    };
-
-    ///  Analog-to-Digital Converter (ADC)
-    pub const ADC = extern struct {
-        ///  A/D Control Register. The ADCR register must be written to select the operating mode before A/D conversion can occur.
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Selects which of the AD0[7:0] pins is (are) to be sampled and converted. For AD0, bit 0 selects Pin AD0[0], and bit 7 selects pin AD0[7]. In software-controlled mode, only one of these bits should be 1. In hardware scan mode, any value containing 1 to 8 ones is allowed. All zeroes is equivalent to 0x01.
-            SEL: u8,
-            ///  The APB clock (PCLK) is divided by (this value plus one) to produce the clock for the A/D converter, which should be less than or equal to 12.4 MHz. Typically, software should program the smallest value in this field that yields a clock of 12.4 MHz or slightly less, but in certain cases (such as a high-impedance analog source) a slower clock may be desirable.
-            CLKDIV: u8,
-            ///  Burst mode
-            BURST: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The AD converter does repeated conversions at up to 400 kHz, scanning (if necessary) through the pins selected by bits set to ones in the SEL field. The first conversion after the start corresponds to the least-significant 1 in the SEL field, then higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by clearing this bit, but the conversion that's in progress when this bit is cleared will be completed. START bits must be 000 when BURST = 1 or conversions will not start.
-                    BURST = 0x1,
-                    ///  Conversions are software controlled and require 31 clocks.
-                    SW = 0x0,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u4,
-            ///  Power down mode
-            PDN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The A/D converter is operational.
-                    POWERED = 0x1,
-                    ///  The A/D converter is in power-down mode.
-                    POWERDOWN = 0x0,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  When the BURST bit is 0, these bits control whether and when an A/D conversion is started:
-            START: packed union {
-                raw: u3,
-                value: enum(u3) {
-                    ///  No start (this value should be used when clearing PDN to 0).
-                    NO_START_THIS_VALUE = 0x0,
-                    ///  Start conversion now.
-                    START_CONVERSION_NOW = 0x1,
-                    ///  Start conversion when the edge selected by bit 27 occurs on the P2[10] pin.
-                    P2_10 = 0x2,
-                    ///  Start conversion when the edge selected by bit 27 occurs on the P1[27] pin.
-                    P1_27 = 0x3,
-                    ///  Start conversion when the edge selected by bit 27 occurs on MAT0.1. Note that this does not require that the MAT0.1 function appear on a device pin.
-                    MAT0_1 = 0x4,
-                    ///  Start conversion when the edge selected by bit 27 occurs on MAT0.3. Note that it is not possible to cause the MAT0.3 function to appear on a device pin.
-                    MAT0_3 = 0x5,
-                    ///  Start conversion when the edge selected by bit 27 occurs on MAT1.0. Note that this does not require that the MAT1.0 function appear on a device pin.
-                    MAT1_0 = 0x6,
-                    ///  Start conversion when the edge selected by bit 27 occurs on MAT1.1. Note that this does not require that the MAT1.1 function appear on a device pin.
-                    MAT1_1 = 0x7,
-                },
-            },
-            ///  This bit is significant only when the START field contains 010-111. In these cases:
-            EDGE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Start conversion on a falling edge on the selected CAP/MAT signal.
-                    FALLLING = 0x1,
-                    ///  Start conversion on a rising edge on the selected CAP/MAT signal.
-                    RISING = 0x0,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u4,
-        }),
-        ///  A/D Global Data Register. This register contains the ADC's DONE bit and the result of the most recent A/D conversion.
-        GDR: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u4,
-            ///  When DONE is 1, this field contains a binary fraction representing the voltage on the AD0[n] pin selected by the SEL field, as it falls within the range of VREFP to VSS. Zero in the field indicates that the voltage on the input pin was less than, equal to, or close to that on VSS, while 0xFFF indicates that the voltage on the input was close to, equal to, or greater than that on VREFP.
-            RESULT: u12,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u8,
-            ///  These bits contain the channel from which the RESULT bits were converted (e.g. 000 identifies channel 0, 001 channel 1...).
-            CHN: u3,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u3,
-            ///  This bit is 1 in burst mode if the results of one or more conversions was (were) lost and overwritten before the conversion that produced the result in the RESULT bits. This bit is cleared by reading this register.
-            OVERRUN: u1,
-            ///  This bit is set to 1 when an A/D conversion completes. It is cleared when this register is read and when the ADCR is written. If the ADCR is written while a conversion is still in progress, this bit is set and a new conversion is started.
-            DONE: u1,
-        }),
-        reserved12: [4]u8,
-        ///  A/D Interrupt Enable Register. This register contains enable bits that allow the DONE flag of each A/D channel to be included or excluded from contributing to the generation of an A/D interrupt.
-        INTEN: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt enable
-            ADINTEN0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Completion of a conversion on ADC channel 0 will not generate an interrupt.
-                    DISABLE = 0x0,
-                    ///  Completion of a conversion on ADC channel 0 will generate an interrupt.
-                    ENABLE = 0x1,
-                },
-            },
-            ///  Interrupt enable
-            ADINTEN1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Completion of a conversion on ADC channel 1 will not generate an interrupt.
-                    DISABLE = 0x0,
-                    ///  Completion of a conversion on ADC channel 1 will generate an interrupt.
-                    ENABLE = 0x1,
-                },
-            },
-            ///  Interrupt enable
-            ADINTEN2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Completion of a conversion on ADC channel 2 will not generate an interrupt.
-                    DISABLE = 0x0,
-                    ///  Completion of a conversion on ADC channel 2 will generate an interrupt.
-                    ENABLE = 0x1,
-                },
-            },
-            ///  Interrupt enable
-            ADINTEN3: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Completion of a conversion on ADC channel 3 will not generate an interrupt.
-                    DISABLE = 0x0,
-                    ///  Completion of a conversion on ADC channel 3 will generate an interrupt.
-                    ENABLE = 0x1,
-                },
-            },
-            ///  Interrupt enable
-            ADINTEN4: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Completion of a conversion on ADC channel 4 will not generate an interrupt.
-                    DISABLE = 0x0,
-                    ///  Completion of a conversion on ADC channel 4 will generate an interrupt.
-                    ENABLE = 0x1,
-                },
-            },
-            ///  Interrupt enable
-            ADINTEN5: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Completion of a conversion on ADC channel 5 will not generate an interrupt.
-                    DISABLE = 0x0,
-                    ///  Completion of a conversion on ADC channel 5 will generate an interrupt.
-                    ENABLE = 0x1,
-                },
-            },
-            ///  Interrupt enable
-            ADINTEN6: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Completion of a conversion on ADC channel 6 will not generate an interrupt.
-                    DISABLE = 0x0,
-                    ///  Completion of a conversion on ADC channel 6 will generate an interrupt.
-                    ENABLE = 0x1,
-                },
-            },
-            ///  Interrupt enable
-            ADINTEN7: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Completion of a conversion on ADC channel 7 will not generate an interrupt.
-                    DISABLE = 0x0,
-                    ///  Completion of a conversion on ADC channel 7 will generate an interrupt.
-                    ENABLE = 0x1,
-                },
-            },
-            ///  Interrupt enable
-            ADGINTEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Only the individual ADC channels enabled by ADINTEN7:0 will generate interrupts.
-                    CHANNELS = 0x0,
-                    ///  The global DONE flag in ADDR is enabled to generate an interrupt in addition to any individual ADC channels that are enabled to generate interrupts.
-                    GLOBAL = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u23,
-        }),
-        reserved48: [32]u8,
-        ///  A/D Status Register. This register contains DONE and OVERRUN flags for all of the A/D channels, as well as the A/D interrupt/DMA flag.
-        STAT: mmio.Mmio(packed struct(u32) {
-            ///  This bit mirrors the DONE status flag from the result register for A/D channel 0.
-            DONE0: u1,
-            ///  This bit mirrors the DONE status flag from the result register for A/D channel 1.
-            DONE1: u1,
-            ///  This bit mirrors the DONE status flag from the result register for A/D channel 2.
-            DONE2: u1,
-            ///  This bit mirrors the DONE status flag from the result register for A/D channel 3.
-            DONE3: u1,
-            ///  This bit mirrors the DONE status flag from the result register for A/D channel 4.
-            DONE4: u1,
-            ///  This bit mirrors the DONE status flag from the result register for A/D channel 5.
-            DONE5: u1,
-            ///  This bit mirrors the DONE status flag from the result register for A/D channel 6.
-            DONE6: u1,
-            ///  This bit mirrors the DONE status flag from the result register for A/D channel 7.
-            DONE7: u1,
-            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 0.
-            OVERRUN0: u1,
-            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 1.
-            OVERRUN1: u1,
-            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 2.
-            OVERRUN2: u1,
-            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 3.
-            OVERRUN3: u1,
-            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 4.
-            OVERRUN4: u1,
-            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 5.
-            OVERRUN5: u1,
-            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 6.
-            OVERRUN6: u1,
-            ///  This bit mirrors the OVERRRUN status flag from the result register for A/D channel 7.
-            OVERRUN7: u1,
-            ///  This bit is the A/D interrupt flag. It is one when any of the individual A/D channel Done flags is asserted and enabled to contribute to the A/D interrupt via the ADINTEN register.
-            ADINT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u15,
-        }),
-        ///  ADC trim register.
-        TRM: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u4,
-            ///  Offset trim bits for ADC operation. Initialized by the boot code. Can be overwritten by the user.
-            ADCOFFS: u4,
-            ///  written-to by boot code. Can not be overwritten by the user. These bits are locked after boot code write.
-            TRIM: u4,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u20,
-        }),
-    };
-
-    ///  CAN acceptance filter RAM
-    pub const CANAFRAM = struct {};
-
-    ///  CAN controller acceptance filter
-    pub const CANAF = extern struct {
-        ///  Acceptance Filter Register
-        AFMR: mmio.Mmio(packed struct(u32) {
-            ///  if AccBP is 0, the Acceptance Filter is not operational. All Rx messages on all CAN buses are ignored.
-            ACCOFF: u1,
-            ///  All Rx messages are accepted on enabled CAN controllers. Software must set this bit before modifying the contents of any of the registers described below, and before modifying the contents of Lookup Table RAM in any way other than setting or clearing Disable bits in Standard Identifier entries. When both this bit and AccOff are 0, the Acceptance filter operates to screen received CAN Identifiers.
-            ACCBP: u1,
-            ///  FullCAN mode
-            EFCAN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Software must read all messages for all enabled IDs on all enabled CAN buses, from the receiving CAN controllers.
-                    SOFTWARE_MUST_READ_A = 0x0,
-                    ///  The Acceptance Filter itself will take care of receiving and storing messages for selected Standard ID values on selected CAN buses. See Section 21.16 FullCAN mode on page 576.
-                    THE_ACCEPTANCE_FILTE = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u29,
-        }),
-        ///  Standard Frame Individual Start Address Register
-        SFF_SA: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  The start address of the table of individual Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the SFF_GRP_sa register described below. For compatibility with possible future devices, write zeroes in bits 31:11 and 1:0 of this register. If the eFCAN bit in the AFMR is 1, this value also indicates the size of the table of Standard IDs which the Acceptance Filter will search and (if found) automatically store received messages in Acceptance Filter RAM.
-            SFF_SA: u9,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u21,
-        }),
-        ///  Standard Frame Group Start Address Register
-        SFF_GRP_SA: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  The start address of the table of grouped Standard Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_sa register described below. The largest value that should be written to this register is 0x800, when only the Standard Individual table is used, and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.
-            SFF_GRP_SA: u10,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u20,
-        }),
-        ///  Extended Frame Start Address Register
-        EFF_SA: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  The start address of the table of individual Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the EFF_GRP_sa register described below. The largest value that should be written to this register is 0x800, when both Extended Tables are empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:11 and 1:0 of this register.
-            EFF_SA: u9,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u21,
-        }),
-        ///  Extended Frame Group Start Address Register
-        EFF_GRP_SA: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  The start address of the table of grouped Extended Identifiers in AF Lookup RAM. If the table is empty, write the same value in this register and the ENDofTable register described below. The largest value that should be written to this register is 0x800, when this table is empty and the last word (address 0x7FC) in AF Lookup Table RAM is used. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register.
-            EFF_GRP_SA: u10,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u20,
-        }),
-        ///  End of AF Tables register
-        ENDOFTABLE: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  The address above the last active address in the last active AF table. For compatibility with possible future devices, please write zeroes in bits 31:12 and 1:0 of this register. If the eFCAN bit in the AFMR is 0, the largest value that should be written to this register is 0x800, which allows the last word (address 0x7FC) in AF Lookup Table RAM to be used. If the eFCAN bit in the AFMR is 1, this value marks the start of the area of Acceptance Filter RAM, into which the Acceptance Filter will automatically receive messages for selected IDs on selected CAN buses. In this case, the maximum value that should be written to this register is 0x800 minus 6 times the value in SFF_sa. This allows 12 bytes of message storage between this address and the end of Acceptance Filter RAM, for each Standard ID that is specified between the start of Acceptance Filter RAM, and the next active AF table.
-            ENDOFTABLE: u10,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u20,
-        }),
-        ///  LUT Error Address register
-        LUTERRAD: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  It the LUT Error bit (below) is 1, this read-only field contains the address in AF Lookup Table RAM, at which the Acceptance Filter encountered an error in the content of the tables.
-            LUTERRAD: u9,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u21,
-        }),
-        ///  LUT Error Register
-        LUTERR: mmio.Mmio(packed struct(u32) {
-            ///  This read-only bit is set to 1 if the Acceptance Filter encounters an error in the content of the tables in AF RAM. It is cleared when software reads the LUTerrAd register. This condition is ORed with the other CAN interrupts from the CAN controllers, to produce the request that is connected to the NVIC.
-            LUTERR: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u31,
-        }),
-        ///  FullCAN interrupt enable register
-        FCANIE: mmio.Mmio(packed struct(u32) {
-            ///  Global FullCAN Interrupt Enable. When 1, this interrupt is enabled.
-            FCANIE: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u31,
-        }),
-        ///  FullCAN interrupt and capture register0
-        FCANIC0: mmio.Mmio(packed struct(u32) {
-            ///  FullCan Interrupt Pending 0 = FullCan Interrupt Pending bit 0. 1 = FullCan Interrupt Pending bit 1. ... 31 = FullCan Interrupt Pending bit 31.
-            INTPND: u32,
-        }),
-        ///  FullCAN interrupt and capture register1
-        FCANIC1: mmio.Mmio(packed struct(u32) {
-            ///  FullCan Interrupt Pending bit 32. 0 = FullCan Interrupt Pending bit 32. 1 = FullCan Interrupt Pending bit 33. ... 31 = FullCan Interrupt Pending bit 63.
-            IntPnd32: u32,
-        }),
-    };
-
-    ///  Central CAN controller
-    pub const CCAN = extern struct {
-        ///  CAN Central Transmit Status Register
-        TXSR: mmio.Mmio(packed struct(u32) {
-            ///  When 1, the CAN controller 1 is sending a message (same as TS in the CAN1GSR).
-            TS1: u1,
-            ///  When 1, the CAN controller 2 is sending a message (same as TS in the CAN2GSR)
-            TS2: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u6,
-            ///  When 1, all 3 Tx Buffers of the CAN1 controller are available to the CPU (same as TBS in CAN1GSR).
-            TBS1: u1,
-            ///  When 1, all 3 Tx Buffers of the CAN2 controller are available to the CPU (same as TBS in CAN2GSR).
-            TBS2: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u6,
-            ///  When 1, all requested transmissions have been completed successfully by the CAN1 controller (same as TCS in CAN1GSR).
-            TCS1: u1,
-            ///  When 1, all requested transmissions have been completed successfully by the CAN2 controller (same as TCS in CAN2GSR).
-            TCS2: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u14,
-        }),
-        ///  CAN Central Receive Status Register
-        RXSR: mmio.Mmio(packed struct(u32) {
-            ///  When 1, CAN1 is receiving a message (same as RS in CAN1GSR).
-            RS1: u1,
-            ///  When 1, CAN2 is receiving a message (same as RS in CAN2GSR).
-            RS2: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u6,
-            ///  When 1, a received message is available in the CAN1 controller (same as RBS in CAN1GSR).
-            RB1: u1,
-            ///  When 1, a received message is available in the CAN2 controller (same as RBS in CAN2GSR).
-            RB2: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u6,
-            ///  When 1, a message was lost because the preceding message to CAN1 controller was not read out quickly enough (same as DOS in CAN1GSR).
-            DOS1: u1,
-            ///  When 1, a message was lost because the preceding message to CAN2 controller was not read out quickly enough (same as DOS in CAN2GSR).
-            DOS2: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u14,
-        }),
-        ///  CAN Central Miscellaneous Register
-        MSR: mmio.Mmio(packed struct(u32) {
-            ///  When 1, one or both of the CAN1 Tx and Rx Error Counters has reached the limit set in the CAN1EWL register (same as ES in CAN1GSR)
-            E1: u1,
-            ///  When 1, one or both of the CAN2 Tx and Rx Error Counters has reached the limit set in the CAN2EWL register (same as ES in CAN2GSR)
-            E2: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u6,
-            ///  When 1, the CAN1 controller is currently involved in bus activities (same as BS in CAN1GSR).
-            BS1: u1,
-            ///  When 1, the CAN2 controller is currently involved in bus activities (same as BS in CAN2GSR).
-            BS2: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u22,
-        }),
-    };
-
-    ///  CAN1 controller
-    pub const CAN1 = extern struct {
-        ///  Controls the operating mode of the CAN Controller.
-        MOD: mmio.Mmio(packed struct(u32) {
-            ///  Reset Mode.
-            RM: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal.The CAN Controller is in the Operating Mode, and certain registers can not be written.
-                    NORMAL_THE_CAN_CONTR = 0x0,
-                    ///  Reset. CAN operation is disabled, writable registers can be written and the current transmission/reception of a message is aborted.
-                    RESET_CAN_OPERATION = 0x1,
-                },
-            },
-            ///  Listen Only Mode.
-            LOM: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. The CAN controller acknowledges a successfully received message on the CAN bus. The error counters are stopped at the current value.
-                    NORMAL_THE_CAN_CONT = 0x0,
-                    ///  Listen only. The controller gives no acknowledgment, even if a message is successfully received. Messages cannot be sent, and the controller operates in error passive mode. This mode is intended for software bit rate detection and hot plugging.
-                    LISTEN_ONLY_THE_CON = 0x1,
-                },
-            },
-            ///  Self Test Mode.
-            STM: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Normal. A transmitted message must be acknowledged to be considered successful.
-                    NORMAL_A_TRANSMITTE = 0x0,
-                    ///  Self test. The controller will consider a Tx message successful even if there is no acknowledgment received. In this mode a full node test is possible without any other active node on the bus using the SRR bit in CANxCMR.
-                    SELF_TEST_THE_CONTR = 0x1,
-                },
-            },
-            ///  Transmit Priority Mode.
-            TPM: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  CAN ID. The transmit priority for 3 Transmit Buffers depends on the CAN Identifier.
-                    CAN_ID_THE_TRANSMIT = 0x0,
-                    ///  Local priority. The transmit priority for 3 Transmit Buffers depends on the contents of the Tx Priority register within the Transmit Buffer.
-                    LOCAL_PRIORITY_THE_ = 0x1,
-                },
-            },
-            ///  Sleep Mode.
-            SM: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Wake-up. Normal operation.
-                    WAKE_UP_NORMAL_OPER = 0x0,
-                    ///  Sleep. The CAN controller enters Sleep Mode if no CAN interrupt is pending and there is no bus activity. See the Sleep Mode description Section 21.8.2 on page 565.
-                    SLEEP_THE_CAN_CONTR = 0x1,
-                },
-            },
-            ///  Receive Polarity Mode.
-            RPM: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Low active. RD input is active Low (dominant bit = 0).
-                    LOW_ACTIVE_RD_INPUT = 0x0,
-                    ///  High active. RD input is active High (dominant bit = 1) -- reverse polarity.
-                    HIGH_ACTIVE_RD_INPU = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  Test Mode.
-            TM: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled. Normal operation.
-                    DISABLED_NORMAL_OPE = 0x0,
-                    ///  Enabled. The TD pin will reflect the bit, detected on RD pin, with the next positive edge of the system clock.
-                    ENABLED_THE_TD_PIN_ = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  Command bits that affect the state of the CAN Controller
-        CMR: mmio.Mmio(packed struct(u32) {
-            ///  Transmission Request.
-            TR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Absent.No transmission request.
-                    ABSENT_NO_TRANSMISSI = 0x0,
-                    ///  Present. The message, previously written to the CANxTFI, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer. If at two or all three of STB1, STB2 and STB3 bits are selected when TR=1 is written, Transmit Buffer will be selected based on the chosen priority scheme (for details see Section 21.5.3 Transmit Buffers (TXB))
-                    PRESENT_THE_MESSAGE = 0x1,
-                },
-            },
-            ///  Abort Transmission.
-            AT: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No action. Do not abort the transmission.
-                    NO_ACTION_DO_NOT_AB = 0x0,
-                    ///  Present. if not already in progress, a pending Transmission Request for the selected Transmit Buffer is cancelled.
-                    PRESENT_IF_NOT_ALRE = 0x1,
-                },
-            },
-            ///  Release Receive Buffer.
-            RRB: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No action. Do not release the receive buffer.
-                    NO_ACTION_DO_NOT_RE = 0x0,
-                    ///  Released. The information in the Receive Buffer (consisting of CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers) is released, and becomes eligible for replacement by the next received frame. If the next received frame is not available, writing this command clears the RBS bit in the Status Register(s).
-                    RELEASED_THE_INFORM = 0x1,
-                },
-            },
-            ///  Clear Data Overrun.
-            CDO: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No action. Do not clear the data overrun bit.
-                    NO_ACTION_DO_NOT_CL = 0x0,
-                    ///  Clear. The Data Overrun bit in Status Register(s) is cleared.
-                    CLEAR_THE_DATA_OVER = 0x1,
-                },
-            },
-            ///  Self Reception Request.
-            SRR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Absent. No self reception request.
-                    ABSENT_NO_SELF_RECE = 0x0,
-                    ///  Present. The message, previously written to the CANxTFS, CANxTID, and optionally the CANxTDA and CANxTDB registers, is queued for transmission from the selected Transmit Buffer and received simultaneously. This differs from the TR bit above in that the receiver is not disabled during the transmission, so that it receives the message if its Identifier is recognized by the Acceptance Filter.
-                    PRESENT_THE_MESSAGE = 0x1,
-                },
-            },
-            ///  Select Tx Buffer 1.
-            STB1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Not selected. Tx Buffer 1 is not selected for transmission.
-                    NOT_SELECTED_TX_BUF = 0x0,
-                    ///  Selected. Tx Buffer 1 is selected for transmission.
-                    SELECTED_TX_BUFFER_ = 0x1,
-                },
-            },
-            ///  Select Tx Buffer 2.
-            STB2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Not selected. Tx Buffer 2 is not selected for transmission.
-                    NOT_SELECTED_TX_BUF = 0x0,
-                    ///  Selected. Tx Buffer 2 is selected for transmission.
-                    SELECTED_TX_BUFFER_ = 0x1,
-                },
-            },
-            ///  Select Tx Buffer 3.
-            STB3: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Not selected. Tx Buffer 3 is not selected for transmission.
-                    NOT_SELECTED_TX_BUF = 0x0,
-                    ///  Selected. Tx Buffer 3 is selected for transmission.
-                    SELECTED_TX_BUFFER_ = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  Global Controller Status and Error Counters. The error counters can only be written when RM in CANMOD is 1.
-        GSR: mmio.Mmio(packed struct(u32) {
-            ///  Receive Buffer Status. After reading all messages and releasing their memory space with the command 'Release Receive Buffer,' this bit is cleared.
-            RBS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Empty. No message is available.
-                    EMPTY_NO_MESSAGE_IS = 0x0,
-                    ///  Full. At least one complete message is received by the Double Receive Buffer and available in the CANxRFS, CANxRID, and if applicable the CANxRDA and CANxRDB registers. This bit is cleared by the Release Receive Buffer command in CANxCMR, if no subsequent received message is available.
-                    FULL_AT_LEAST_ONE_C = 0x1,
-                },
-            },
-            ///  Data Overrun Status. If there is not enough space to store the message within the Receive Buffer, that message is dropped and the Data Overrun condition is signalled to the CPU in the moment this message becomes valid. If this message is not completed successfully (e.g. because of an error), no overrun condition is signalled.
-            DOS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Absent. No data overrun has occurred since the last Clear Data Overrun command was given/written to CANxCMR (or since Reset).
-                    ABSENT_NO_DATA_OVER = 0x0,
-                    ///  Overrun. A message was lost because the preceding message to this CAN controller was not read and released quickly enough (there was not enough space for a new message in the Double Receive Buffer).
-                    OVERRUN_A_MESSAGE_W = 0x1,
-                },
-            },
-            ///  Transmit Buffer Status.
-            TBS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Locked. At least one of the Transmit Buffers is not available for the CPU, i.e. at least one previously queued message for this CAN controller has not yet been sent, and therefore software should not write to the CANxTFI, CANxTID, CANxTDA, nor CANxTDB registers of that (those) Tx buffer(s).
-                    LOCKED_AT_LEAST_ONE = 0x0,
-                    ///  Released. All three Transmit Buffers are available for the CPU. No transmit message is pending for this CAN controller (in any of the 3 Tx buffers), and software may write to any of the CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.
-                    RELEASED_ALL_THREE_ = 0x1,
-                },
-            },
-            ///  Transmit Complete Status. The Transmission Complete Status bit is set '0' (incomplete) whenever the Transmission Request bit or the Self Reception Request bit is set '1' at least for one of the three Transmit Buffers. The Transmission Complete Status bit will remain '0' until all messages are transmitted successfully.
-            TCS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Incomplete. At least one requested transmission has not been successfully completed yet.
-                    INCOMPLETE_AT_LEAST = 0x0,
-                    ///  Complete. All requested transmission(s) has (have) been successfully completed.
-                    COMPLETE_ALL_REQUES = 0x1,
-                },
-            },
-            ///  Receive Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.
-            RS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Idle. The CAN controller is idle.
-                    IDLE_THE_CAN_CONTRO = 0x0,
-                    ///  Receive. The CAN controller is receiving a message.
-                    RECEIVE_THE_CAN_CON = 0x1,
-                },
-            },
-            ///  Transmit Status. If both the Receive Status and the Transmit Status bits are '0' (idle), the CAN-Bus is idle. If both bits are set, the controller is waiting to become idle again. After hardware reset 11 consecutive recessive bits have to be detected until idle status is reached. After Bus-off this will take 128 times of 11 consecutive recessive bits.
-            TS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Idle. The CAN controller is idle.
-                    IDLE_THE_CAN_CONTRO = 0x0,
-                    ///  Transmit. The CAN controller is sending a message.
-                    TRANSMIT_THE_CAN_CO = 0x1,
-                },
-            },
-            ///  Error Status. Errors detected during reception or transmission will effect the error counters according to the CAN specification. The Error Status bit is set when at least one of the error counters has reached or exceeded the Error Warning Limit. An Error Warning Interrupt is generated, if enabled. The default value of the Error Warning Limit after hardware reset is 96 decimal, see also Section 21.7.7 CAN Error Warning Limit register (CAN1EWL - 0x4004 4018, CAN2EWL - 0x4004 8018).
-            ES: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  OK. Both error counters are below the Error Warning Limit.
-                    OK_BOTH_ERROR_COUNT = 0x0,
-                    ///  Error. One or both of the Transmit and Receive Error Counters has reached the limit set in the Error Warning Limit register.
-                    ERROR_ONE_OR_BOTH_O = 0x1,
-                },
-            },
-            ///  Bus Status. Mode bit '1' (present) and an Error Warning Interrupt is generated, if enabled. Afterwards the Transmit Error Counter is set to '127', and the Receive Error Counter is cleared. It will stay in this mode until the CPU clears the Reset Mode bit. Once this is completed the CAN Controller will wait the minimum protocol-defined time (128 occurrences of the Bus-Free signal) counting down the Transmit Error Counter. After that, the Bus Status bit is cleared (Bus-On), the Error Status bit is set '0' (ok), the Error Counters are reset, and an Error Warning Interrupt is generated, if enabled. Reading the TX Error Counter during this time gives information about the status of the Bus-Off recovery.
-            BS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Bus-on. The CAN Controller is involved in bus activities
-                    BUS_ON_THE_CAN_CONT = 0x0,
-                    ///  Bus-off. The CAN controller is currently not involved/prohibited from bus activity because the Transmit Error Counter reached its limiting value of 255.
-                    BUS_OFF_THE_CAN_CON = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u8,
-            ///  The current value of the Rx Error Counter (an 8-bit value).
-            RXERR: u8,
-            ///  The current value of the Tx Error Counter (an 8-bit value).
-            TXERR: u8,
-        }),
-        ///  Interrupt status, Arbitration Lost Capture, Error Code Capture
-        ICR: mmio.Mmio(packed struct(u32) {
-            ///  Receive Interrupt. This bit is set whenever the RBS bit in CANxSR and the RIE bit in CANxIER are both 1, indicating that a new message was received and stored in the Receive Buffer. The Receive Interrupt Bit is not cleared upon a read access to the Interrupt Register. Giving the Command Release Receive Buffer will clear RI temporarily. If there is another message available within the Receive Buffer after the release command, RI is set again. Otherwise RI remains cleared.
-            RI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Reset
-                    RESET = 0x0,
-                    ///  Set
-                    SET = 0x1,
-                },
-            },
-            ///  Transmit Interrupt 1. This bit is set when the TBS1 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB1 was successfully transmitted or aborted), indicating that Transmit buffer 1 is available, and the TIE1 bit in CANxIER is 1.
-            TI1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Reset
-                    RESET = 0x0,
-                    ///  Set
-                    SET = 0x1,
-                },
-            },
-            ///  Error Warning Interrupt. This bit is set on every change (set or clear) of either the Error Status or Bus Status bit in CANxSR and the EIE bit bit is set within the Interrupt Enable Register at the time of the change.
-            EI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Reset
-                    RESET = 0x0,
-                    ///  Set
-                    SET = 0x1,
-                },
-            },
-            ///  Data Overrun Interrupt. This bit is set when the DOS bit in CANxSR goes from 0 to 1 and the DOIE bit in CANxIER is 1.
-            DOI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Reset
-                    RESET = 0x0,
-                    ///  Set
-                    SET = 0x1,
-                },
-            },
-            ///  Wake-Up Interrupt. This bit is set if the CAN controller is sleeping and bus activity is detected and the WUIE bit in CANxIER is 1. A Wake-Up Interrupt is also generated if the CPU tries to set the Sleep bit while the CAN controller is involved in bus activities or a CAN Interrupt is pending. The WUI flag can also get asserted when the according enable bit WUIE is not set. In this case a Wake-Up Interrupt does not get asserted.
-            WUI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Reset
-                    RESET = 0x0,
-                    ///  Set
-                    SET = 0x1,
-                },
-            },
-            ///  Error Passive Interrupt. This bit is set if the EPIE bit in CANxIER is 1, and the CAN controller switches between Error Passive and Error Active mode in either direction. This is the case when the CAN Controller has reached the Error Passive Status (at least one error counter exceeds the CAN protocol defined level of 127) or if the CAN Controller is in Error Passive Status and enters the Error Active Status again.
-            EPI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Reset
-                    RESET = 0x0,
-                    ///  Set
-                    SET = 0x1,
-                },
-            },
-            ///  Arbitration Lost Interrupt. This bit is set if the ALIE bit in CANxIER is 1, and the CAN controller loses arbitration while attempting to transmit. In this case the CAN node becomes a receiver.
-            ALI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Reset
-                    RESET = 0x0,
-                    ///  Set
-                    SET = 0x1,
-                },
-            },
-            ///  Bus Error Interrupt -- this bit is set if the BEIE bit in CANxIER is 1, and the CAN controller detects an error on the bus.
-            BEI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Reset
-                    RESET = 0x0,
-                    ///  Set
-                    SET = 0x1,
-                },
-            },
-            ///  ID Ready Interrupt -- this bit is set if the IDIE bit in CANxIER is 1, and a CAN Identifier has been received (a message was successfully transmitted or aborted). This bit is set whenever a message was successfully transmitted or aborted and the IDIE bit is set in the IER register.
-            IDI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Reset
-                    RESET = 0x0,
-                    ///  Set
-                    SET = 0x1,
-                },
-            },
-            ///  Transmit Interrupt 2. This bit is set when the TBS2 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB2 was successfully transmitted or aborted), indicating that Transmit buffer 2 is available, and the TIE2 bit in CANxIER is 1.
-            TI2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Reset
-                    RESET = 0x0,
-                    ///  Set
-                    SET = 0x1,
-                },
-            },
-            ///  Transmit Interrupt 3. This bit is set when the TBS3 bit in CANxSR goes from 0 to 1 (whenever a message out of TXB3 was successfully transmitted or aborted), indicating that Transmit buffer 3 is available, and the TIE3 bit in CANxIER is 1.
-            TI3: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Reset
-                    RESET = 0x0,
-                    ///  Set
-                    SET = 0x1,
-                },
-            },
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u5,
-            ///  Error Code Capture: when the CAN controller detects a bus error, the location of the error within the frame is captured in this field. The value reflects an internal state variable, and as a result is not very linear: 00011 = Start of Frame 00010 = ID28 ... ID21 00110 = ID20 ... ID18 00100 = SRTR Bit 00101 = IDE bit 00111 = ID17 ... 13 01111 = ID12 ... ID5 01110 = ID4 ... ID0 01100 = RTR Bit 01101 = Reserved Bit 1 01001 = Reserved Bit 0 01011 = Data Length Code 01010 = Data Field 01000 = CRC Sequence 11000 = CRC Delimiter 11001 = Acknowledge Slot 11011 = Acknowledge Delimiter 11010 = End of Frame 10010 = Intermission Whenever a bus error occurs, the corresponding bus error interrupt is forced, if enabled. At the same time, the current position of the Bit Stream Processor is captured into the Error Code Capture Register. The content within this register is fixed until the user software has read out its content once. From now on, the capture mechanism is activated again, i.e. reading the CANxICR enables another Bus Error Interrupt.
-            ERRBIT4_0: u5,
-            ///  When the CAN controller detects a bus error, the direction of the current bit is captured in this bit.
-            ERRDIR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Error occurred during transmitting.
-                    ERROR_OCCURRED_DURIN = 0x0,
-                    ///  Error occurred during receiving.
-                    ERROR_OCCURRED_DURIN = 0x1,
-                },
-            },
-            ///  When the CAN controller detects a bus error, the type of error is captured in this field:
-            ERRC1_0: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Bit error
-                    BIT_ERROR = 0x0,
-                    ///  Form error
-                    FORM_ERROR = 0x1,
-                    ///  Stuff error
-                    STUFF_ERROR = 0x2,
-                    ///  Other error
-                    OTHER_ERROR = 0x3,
-                },
-            },
-            ///  Each time arbitration is lost while trying to send on the CAN, the bit number within the frame is captured into this field. After the content of ALCBIT is read, the ALI bit is cleared and a new Arbitration Lost interrupt can occur. 00 = arbitration lost in the first bit (MS) of identifier ... 11 = arbitration lost in SRTS bit (RTR bit for standard frame messages) 12 = arbitration lost in IDE bit 13 = arbitration lost in 12th bit of identifier (extended frame only) ... 30 = arbitration lost in last bit of identifier (extended frame only) 31 = arbitration lost in RTR bit (extended frame only) On arbitration lost, the corresponding arbitration lost interrupt is forced, if enabled. At that time, the current bit position of the Bit Stream Processor is captured into the Arbitration Lost Capture Register. The content within this register is fixed until the user application has read out its contents once. From now on, the capture mechanism is activated again.
-            ALCBIT: u8,
-        }),
-        ///  Interrupt Enable
-        IER: mmio.Mmio(packed struct(u32) {
-            ///  Receiver Interrupt Enable. When the Receive Buffer Status is 'full', the CAN Controller requests the respective interrupt.
-            RIE: u1,
-            ///  Transmit Interrupt Enable for Buffer1. When a message has been successfully transmitted out of TXB1 or Transmit Buffer 1 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.
-            TIE1: u1,
-            ///  Error Warning Interrupt Enable. If the Error or Bus Status change (see Status Register), the CAN Controller requests the respective interrupt.
-            EIE: u1,
-            ///  Data Overrun Interrupt Enable. If the Data Overrun Status bit is set (see Status Register), the CAN Controller requests the respective interrupt.
-            DOIE: u1,
-            ///  Wake-Up Interrupt Enable. If the sleeping CAN controller wakes up, the respective interrupt is requested.
-            WUIE: u1,
-            ///  Error Passive Interrupt Enable. If the error status of the CAN Controller changes from error active to error passive or vice versa, the respective interrupt is requested.
-            EPIE: u1,
-            ///  Arbitration Lost Interrupt Enable. If the CAN Controller has lost arbitration, the respective interrupt is requested.
-            ALIE: u1,
-            ///  Bus Error Interrupt Enable. If a bus error has been detected, the CAN Controller requests the respective interrupt.
-            BEIE: u1,
-            ///  ID Ready Interrupt Enable. When a CAN identifier has been received, the CAN Controller requests the respective interrupt.
-            IDIE: u1,
-            ///  Transmit Interrupt Enable for Buffer2. When a message has been successfully transmitted out of TXB2 or Transmit Buffer 2 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.
-            TIE2: u1,
-            ///  Transmit Interrupt Enable for Buffer3. When a message has been successfully transmitted out of TXB3 or Transmit Buffer 3 is accessible again (e.g. after an Abort Transmission command), the CAN Controller requests the respective interrupt.
-            TIE3: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u21,
-        }),
-        ///  Bus Timing. Can only be written when RM in CANMOD is 1.
-        BTR: mmio.Mmio(packed struct(u32) {
-            ///  Baud Rate Prescaler. The APB clock is divided by (this value plus one) to produce the CAN clock.
-            BRP: u10,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u4,
-            ///  The Synchronization Jump Width is (this value plus one) CAN clocks.
-            SJW: u2,
-            ///  The delay from the nominal Sync point to the sample point is (this value plus one) CAN clocks.
-            TESG1: u4,
-            ///  The delay from the sample point to the next nominal sync point is (this value plus one) CAN clocks. The nominal CAN bit time is (this value plus the value in TSEG1 plus 3) CAN clocks.
-            TESG2: u3,
-            ///  Sampling
-            SAM: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The bus is sampled once (recommended for high speed buses)
-                    THE_BUS_IS_SAMPLED_O = 0x0,
-                    ///  The bus is sampled 3 times (recommended for low to medium speed buses to filter spikes on the bus-line)
-                    THE_BUS_IS_SAMPLED_3 = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u8,
-        }),
-        ///  Error Warning Limit. Can only be written when RM in CANMOD is 1.
-        EWL: mmio.Mmio(packed struct(u32) {
-            ///  During CAN operation, this value is compared to both the Tx and Rx Error Counters. If either of these counter matches this value, the Error Status (ES) bit in CANSR is set.
-            EWL: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  Status Register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
-            RBS_1: u1,
-            ///  Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
-            DOS_1: u1,
-            ///  Transmit Buffer Status 1.
-            TBS1_1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Locked. Software cannot access the Tx Buffer 1 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.
-                    LOCKED_SOFTWARE_CAN = 0x0,
-                    ///  Released. Software may write a message into the Transmit Buffer 1 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.
-                    RELEASED_SOFTWARE_M = 0x1,
-                },
-            },
-            ///  Transmission Complete Status.
-            TCS1_1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Incomplete. The previously requested transmission for Tx Buffer 1 is not complete.
-                    INCOMPLETE_THE_PREV = 0x0,
-                    ///  Complete. The previously requested transmission for Tx Buffer 1 has been successfully completed.
-                    COMPLETE_THE_PREVIO = 0x1,
-                },
-            },
-            ///  Receive Status. This bit is identical to the RS bit in the GSR.
-            RS_1: u1,
-            ///  Transmit Status 1.
-            TS1_1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Idle. There is no transmission from Tx Buffer 1.
-                    IDLE_THERE_IS_NO_TR = 0x0,
-                    ///  Transmit. The CAN Controller is transmitting a message from Tx Buffer 1.
-                    TRANSMIT_THE_CAN_CO = 0x1,
-                },
-            },
-            ///  Error Status. This bit is identical to the ES bit in the CANxGSR.
-            ES_1: u1,
-            ///  Bus Status. This bit is identical to the BS bit in the CANxGSR.
-            BS_1: u1,
-            ///  Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
-            RBS_2: u1,
-            ///  Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
-            DOS_2: u1,
-            ///  Transmit Buffer Status 2.
-            TBS2_2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Locked. Software cannot access the Tx Buffer 2 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.
-                    LOCKED_SOFTWARE_CAN = 0x0,
-                    ///  Released. Software may write a message into the Transmit Buffer 2 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.
-                    RELEASED_SOFTWARE_M = 0x1,
-                },
-            },
-            ///  Transmission Complete Status.
-            TCS2_2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Incomplete. The previously requested transmission for Tx Buffer 2 is not complete.
-                    INCOMPLETE_THE_PREV = 0x0,
-                    ///  Complete. The previously requested transmission for Tx Buffer 2 has been successfully completed.
-                    COMPLETE_THE_PREVIO = 0x1,
-                },
-            },
-            ///  Receive Status. This bit is identical to the RS bit in the GSR.
-            RS_2: u1,
-            ///  Transmit Status 2.
-            TS2_2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Idle. There is no transmission from Tx Buffer 2.
-                    IDLE_THERE_IS_NO_TR = 0x0,
-                    ///  Transmit. The CAN Controller is transmitting a message from Tx Buffer 2.
-                    TRANSMIT_THE_CAN_CO = 0x1,
-                },
-            },
-            ///  Error Status. This bit is identical to the ES bit in the CANxGSR.
-            ES_2: u1,
-            ///  Bus Status. This bit is identical to the BS bit in the CANxGSR.
-            BS_2: u1,
-            ///  Receive Buffer Status. This bit is identical to the RBS bit in the CANxGSR.
-            RBS_3: u1,
-            ///  Data Overrun Status. This bit is identical to the DOS bit in the CANxGSR.
-            DOS_3: u1,
-            ///  Transmit Buffer Status 3.
-            TBS3_3: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Locked. Software cannot access the Tx Buffer 3 nor write to the corresponding CANxTFI, CANxTID, CANxTDA, and CANxTDB registers because a message is either waiting for transmission or is in transmitting process.
-                    LOCKED_SOFTWARE_CAN = 0x0,
-                    ///  Released. Software may write a message into the Transmit Buffer 3 and its CANxTFI, CANxTID, CANxTDA, and CANxTDB registers.
-                    RELEASED_SOFTWARE_M = 0x1,
-                },
-            },
-            ///  Transmission Complete Status.
-            TCS3_3: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Incomplete. The previously requested transmission for Tx Buffer 3 is not complete.
-                    INCOMPLETE_THE_PREV = 0x0,
-                    ///  Complete. The previously requested transmission for Tx Buffer 3 has been successfully completed.
-                    COMPLETE_THE_PREVIO = 0x1,
-                },
-            },
-            ///  Receive Status. This bit is identical to the RS bit in the GSR.
-            RS_3: u1,
-            ///  Transmit Status 3.
-            TS3_3: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Idle. There is no transmission from Tx Buffer 3.
-                    IDLE_THERE_IS_NO_TR = 0x0,
-                    ///  Transmit. The CAN Controller is transmitting a message from Tx Buffer 3.
-                    TRANSMIT_THE_CAN_CO = 0x1,
-                },
-            },
-            ///  Error Status. This bit is identical to the ES bit in the CANxGSR.
-            ES_3: u1,
-            ///  Bus Status. This bit is identical to the BS bit in the CANxGSR.
-            BS_3: u1,
-            ///  Reserved, the value read from a reserved bit is not defined.
-            RESERVED: u8,
-        }),
-        ///  Receive frame status. Can only be written when RM in CANMOD is 1.
-        RFS: mmio.Mmio(packed struct(u32) {
-            ///  ID Index. If the BP bit (below) is 0, this value is the zero-based number of the Lookup Table RAM entry at which the Acceptance Filter matched the received Identifier. Disabled entries in the Standard tables are included in this numbering, but will not be matched. See Section 21.17 Examples of acceptance filter tables and ID index values on page 587 for examples of ID Index values.
-            IDINDEX: u10,
-            ///  If this bit is 1, the current message was received in AF Bypass mode, and the ID Index field (above) is meaningless.
-            BP: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u5,
-            ///  The field contains the Data Length Code (DLC) field of the current received message. When RTR = 0, this is related to the number of data bytes available in the CANRDA and CANRDB registers as follows: 0000-0111 = 0 to 7 bytes1000-1111 = 8 bytes With RTR = 1, this value indicates the number of data bytes requested to be sent back, with the same encoding.
-            DLC: u4,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u10,
-            ///  This bit contains the Remote Transmission Request bit of the current received message. 0 indicates a Data Frame, in which (if DLC is non-zero) data can be read from the CANRDA and possibly the CANRDB registers. 1 indicates a Remote frame, in which case the DLC value identifies the number of data bytes requested to be sent using the same Identifier.
-            RTR: u1,
-            ///  A 0 in this bit indicates that the current received message included an 11-bit Identifier, while a 1 indicates a 29-bit Identifier. This affects the contents of the CANid register described below.
-            FF: u1,
-        }),
-        ///  Received Identifier. Can only be written when RM in CANMOD is 1.
-        RID: mmio.Mmio(packed struct(u32) {
-            ///  The 11-bit Identifier field of the current received message. In CAN 2.0A, these bits are called ID10-0, while in CAN 2.0B they're called ID29-18.
-            ID: u11,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u21,
-        }),
-        ///  Received data bytes 1-4. Can only be written when RM in CANMOD is 1.
-        RDA: mmio.Mmio(packed struct(u32) {
-            ///  Data 1. If the DLC field in CANRFS >= 0001, this contains the first Data byte of the current received message.
-            DATA1: u8,
-            ///  Data 2. If the DLC field in CANRFS >= 0010, this contains the first Data byte of the current received message.
-            DATA2: u8,
-            ///  Data 3. If the DLC field in CANRFS >= 0011, this contains the first Data byte of the current received message.
-            DATA3: u8,
-            ///  Data 4. If the DLC field in CANRFS >= 0100, this contains the first Data byte of the current received message.
-            DATA4: u8,
-        }),
-        ///  Received data bytes 5-8. Can only be written when RM in CANMOD is 1.
-        RDB: mmio.Mmio(packed struct(u32) {
-            ///  Data 5. If the DLC field in CANRFS >= 0101, this contains the first Data byte of the current received message.
-            DATA5: u8,
-            ///  Data 6. If the DLC field in CANRFS >= 0110, this contains the first Data byte of the current received message.
-            DATA6: u8,
-            ///  Data 7. If the DLC field in CANRFS >= 0111, this contains the first Data byte of the current received message.
-            DATA7: u8,
-            ///  Data 8. If the DLC field in CANRFS >= 1000, this contains the first Data byte of the current received message.
-            DATA8: u8,
-        }),
-    };
-
-    ///  USB device/host/OTG controller
-    pub const USB = extern struct {
-        reserved220: [220]u8,
-        ///  USB Receive Packet Length
-        RXPLEN: mmio.Mmio(packed struct(u32) {
-            ///  The remaining number of bytes to be read from the currently selected endpoint's buffer. When this field decrements to 0, the RxENDPKT bit will be set in USBDevIntSt.
-            PKT_LNGTH: u10,
-            ///  Data valid. This bit is useful for isochronous endpoints. Non-isochronous endpoints do not raise an interrupt when an erroneous data packet is received. But invalid data packet can be produced with a bus reset. For isochronous endpoints, data transfer will happen even if an erroneous packet is received. In this case DV bit will not be set for the packet.
-            DV: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Data is invalid.
-                    DATA_IS_INVALID_ = 0x0,
-                    ///  Data is valid.
-                    DATA_IS_VALID_ = 0x1,
-                },
-            },
-            ///  The PKT_LNGTH field is valid and the packet is ready for reading.
-            PKT_RDY: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u20,
-        }),
-        reserved256: [32]u8,
-        ///  OTG Interrupt Status
-        INTST: mmio.Mmio(packed struct(u32) {
-            ///  Timer time-out.
-            TMR: u1,
-            ///  Remove pull-up. This bit is set by hardware to indicate that software needs to disable the D+ pull-up resistor.
-            REMOVE_PU: u1,
-            ///  HNP failed. This bit is set by hardware to indicate that the HNP switching has failed.
-            HNP_FAILURE: u1,
-            ///  HNP succeeded. This bit is set by hardware to indicate that the HNP switching has succeeded.
-            HNP_SUCCESS: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u28,
-        }),
-        ///  OTG Interrupt Enable
-        INTEN: mmio.Mmio(packed struct(u32) {
-            ///  1 = enable the corresponding bit in the IntSt register.
-            TMR_EN: u1,
-            ///  1 = enable the corresponding bit in the IntSt register.
-            REMOVE_PU_EN: u1,
-            ///  1 = enable the corresponding bit in the IntSt register.
-            HNP_FAILURE_EN: u1,
-            ///  1 = enable the corresponding bit in the IntSt register.
-            HNP_SUCCES_EN: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u28,
-        }),
-        ///  OTG Interrupt Set
-        INTSET: mmio.Mmio(packed struct(u32) {
-            ///  0 = no effect. 1 = set the corresponding bit in the IntSt register.
-            TMR_SET: u1,
-            ///  0 = no effect. 1 = set the corresponding bit in the IntSt register.
-            REMOVE_PU_SET: u1,
-            ///  0 = no effect. 1 = set the corresponding bit in the IntSt register.
-            HNP_FAILURE_SET: u1,
-            ///  0 = no effect. 1 = set the corresponding bit in the IntSt register.
-            HNP_SUCCES_SET: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u28,
-        }),
-        ///  OTG Interrupt Clear
-        INTCLR: mmio.Mmio(packed struct(u32) {
-            ///  0 = no effect. 1 = clear the corresponding bit in the IntSt register.
-            TMR_CLR: u1,
-            ///  0 = no effect. 1 = clear the corresponding bit in the IntSt register.
-            REMOVE_PU_CLR: u1,
-            ///  0 = no effect. 1 = clear the corresponding bit in the IntSt register.
-            HNP_FAILURE_CLR: u1,
-            ///  0 = no effect. 1 = clear the corresponding bit in the IntSt register.
-            HNP_SUCCES_CLR: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u28,
-        }),
-        ///  OTG Status and Control and USB port select
-        STCTRL: mmio.Mmio(packed struct(u32) {
-            ///  Controls connection of USB functions (see Figure 51). Bit 0 is set or cleared by hardware when B_HNP_TRACK or A_HNP_TRACK is set and HNP succeeds. See Section 14.9. 00: U1 = device (OTG), U2 = host 01: U1 = host (OTG), U2 = host 10: Reserved 11: U1 = host, U2 = device In a device-only configuration, the following values are allowed: 00: U1 = device. The USB device controller signals are mapped to the U1 port: USB_CONNECT1, USB_UP_LED1, USB_D+1, USB_D-1. 11: U2 = device. The USB device controller signals are mapped to the U2 port: USB_CONNECT2, USB_UP_LED2, USB_D+2, USB_D-2.
-            PORT_FUNC: u2,
-            ///  Timer scale selection. This field determines the duration of each timer count. 00: 10 ms (100 KHz) 01: 100 ms (10 KHz) 10: 1000 ms (1 KHz) 11: Reserved
-            TMR_SCALE: u2,
-            ///  Timer mode selection. 0: monoshot 1: free running
-            TMR_MODE: u1,
-            ///  Timer enable. When set, TMR_CNT increments. When cleared, TMR_CNT is reset to 0.
-            TMR_EN: u1,
-            ///  Timer reset. Writing one to this bit resets TMR_CNT to 0. This provides a single bit control for the software to restart the timer when the timer is enabled.
-            TMR_RST: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  Enable HNP tracking for B-device (peripheral), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.
-            B_HNP_TRACK: u1,
-            ///  Enable HNP tracking for A-device (host), see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.
-            A_HNP_TRACK: u1,
-            ///  When the B-device changes its role from peripheral to host, software sets this bit when it removes the D+ pull-up, see Section 14.9. Hardware clears this bit when HNP_SUCCESS or HNP_FAILURE is set.
-            PU_REMOVED: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u5,
-            ///  Current timer count value.
-            TMR_CNT: u16,
-        }),
-        ///  OTG Timer
-        TMR: mmio.Mmio(packed struct(u32) {
-            ///  The TMR interrupt is set when TMR_CNT reaches this value.
-            TIMEOUT_CNT: u16,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-        reserved512: [232]u8,
-        ///  USB Device Interrupt Status
-        DEVINTST: mmio.Mmio(packed struct(u32) {
-            ///  The frame interrupt occurs every 1 ms. This is used in isochronous packet transfers.
-            FRAME: u1,
-            ///  Fast endpoint interrupt. If an Endpoint Interrupt Priority register (USBEpIntPri) bit is set, the corresponding endpoint interrupt will be routed to this bit.
-            EP_FAST: u1,
-            ///  Slow endpoints interrupt. If an Endpoint Interrupt Priority Register (USBEpIntPri) bit is not set, the corresponding endpoint interrupt will be routed to this bit.
-            EP_SLOW: u1,
-            ///  Set when USB Bus reset, USB suspend change or Connect change event occurs. Refer to Section 13.12.6 Set Device Status (Command: 0xFE, Data: write 1 byte) on page 366.
-            DEV_STAT: u1,
-            ///  The command code register (USBCmdCode) is empty (New command can be written).
-            CCEMPTY: u1,
-            ///  Command data register (USBCmdData) is full (Data can be read now).
-            CDFULL: u1,
-            ///  The current packet in the endpoint buffer is transferred to the CPU.
-            RxENDPKT: u1,
-            ///  The number of data bytes transferred to the endpoint buffer equals the number of bytes programmed in the TxPacket length register (USBTxPLen).
-            TxENDPKT: u1,
-            ///  Endpoints realized. Set when Realize Endpoint register (USBReEp) or MaxPacketSize register (USBMaxPSize) is updated and the corresponding operation is completed.
-            EP_RLZED: u1,
-            ///  Error Interrupt. Any bus error interrupt from the USB device. Refer to Section 13.12.9 Read Error Status (Command: 0xFB, Data: read 1 byte) on page 368
-            ERR_INT: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u22,
-        }),
-        ///  USB Device Interrupt Enable
-        DEVINTEN: mmio.Mmio(packed struct(u32) {
-            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
-            FRAMEEN: u1,
-            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
-            EP_FASTEN: u1,
-            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
-            EP_SLOWEN: u1,
-            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
-            DEV_STATEN: u1,
-            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
-            CCEMPTYEN: u1,
-            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
-            CDFULLEN: u1,
-            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
-            RxENDPKTEN: u1,
-            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
-            TxENDPKTEN: u1,
-            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
-            EP_RLZEDEN: u1,
-            ///  0 = No interrupt is generated. 1 = An interrupt will be generated when the corresponding bit in the Device Interrupt Status (USBDevIntSt) register (Table 261) is set. By default, the interrupt is routed to the USB_INT_REQ_LP interrupt line. Optionally, either the EP_FAST or FRAME interrupt may be routed to the USB_INT_REQ_HP interrupt line by changing the value of USBDevIntPri.
-            ERR_INTEN: u1,
-            ///  Reserved
-            RESERVED: u22,
-        }),
-        ///  USB Device Interrupt Clear
-        DEVINTCLR: mmio.Mmio(packed struct(u32) {
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
-            FRAMECLR: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
-            EP_FASTCLR: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
-            EP_SLOWCLR: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
-            DEV_STATCLR: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
-            CCEMPTYCLR: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
-            CDFULLCLR: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
-            RxENDPKTCLR: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
-            TxENDPKTCLR: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
-            EP_RLZEDCLR: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is cleared.
-            ERR_INTCLR: u1,
-            ///  Reserved
-            RESERVED: u22,
-        }),
-        ///  USB Device Interrupt Set
-        DEVINTSET: mmio.Mmio(packed struct(u32) {
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
-            FRAMESET: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
-            EP_FASTSET: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
-            EP_SLOWSET: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
-            DEV_STATSET: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
-            CCEMPTYSET: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
-            CDFULLSET: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
-            RxENDPKTSET: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
-            TxENDPKTSET: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
-            EP_RLZEDSET: u1,
-            ///  0 = No effect. 1 = The corresponding bit in USBDevIntSt (Section 13.10.3.2) is set.
-            ERR_INTSET: u1,
-            ///  Reserved
-            RESERVED: u22,
-        }),
-        ///  USB Command Code
-        CMDCODE: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u8,
-            ///  The command phase:
-            CMD_PHASE: packed union {
-                raw: u8,
-                value: enum(u8) {
-                    ///  Read
-                    READ = 0x2,
-                    ///  Write
-                    WRITE = 0x1,
-                    ///  Command
-                    COMMAND = 0x5,
-                    _,
-                },
-            },
-            ///  This is a multi-purpose field. When CMD_PHASE is Command or Read, this field contains the code for the command (CMD_CODE). When CMD_PHASE is Write, this field contains the command write data (CMD_WDATA).
-            CMD_CODE_WDATA: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u8,
-        }),
-        ///  USB Command Data
-        CMDDATA: mmio.Mmio(packed struct(u32) {
-            ///  Command Read Data.
-            CMD_RDATA: u8,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  USB Receive Data
-        RXDATA: mmio.Mmio(packed struct(u32) {
-            ///  Data received.
-            RX_DATA: u32,
-        }),
-        ///  USB Transmit Data
-        TXDATA: mmio.Mmio(packed struct(u32) {
-            ///  Transmit Data.
-            TX_DATA: u32,
-        }),
-        reserved548: [4]u8,
-        ///  USB Transmit Packet Length
-        TXPLEN: mmio.Mmio(packed struct(u32) {
-            ///  The remaining number of bytes to be written to the selected endpoint buffer. This field is decremented by 4 by hardware after each write to USBTxData. When this field decrements to 0, the TxENDPKT bit will be set in USBDevIntSt.
-            PKT_LNGTH: u10,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u22,
-        }),
-        ///  USB Control
-        CTRL: mmio.Mmio(packed struct(u32) {
-            ///  Read mode control. Enables reading data from the OUT endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBRxData register. This bit is cleared by hardware when the last word of the current packet is read from USBRxData.
-            RD_EN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Enabled.
-                    ENABLED_ = 0x1,
-                },
-            },
-            ///  Write mode control. Enables writing data to the IN endpoint buffer for the endpoint specified in the LOG_ENDPOINT field using the USBTxData register. This bit is cleared by hardware when the number of bytes in USBTxLen have been sent.
-            WR_EN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Enabled.
-                    ENABLED_ = 0x1,
-                },
-            },
-            ///  Logical Endpoint number.
-            LOG_ENDPOINT: u4,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u26,
-        }),
-        ///  USB Device Interrupt Priority
-        DEVINTPRI: mmio.Mmio(packed struct(u32) {
-            ///  Frame interrupt routing
-            FRAME: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  FRAME interrupt is routed to USB_INT_REQ_LP.
-                    LP = 0x0,
-                    ///  FRAME interrupt is routed to USB_INT_REQ_HP.
-                    HP = 0x1,
-                },
-            },
-            ///  Fast endpoint interrupt routing
-            EP_FAST: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  EP_FAST interrupt is routed to USB_INT_REQ_LP.
-                    LP = 0x0,
-                    ///  EP_FAST interrupt is routed to USB_INT_REQ_HP.
-                    HP = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u30,
-        }),
-        ///  USB Endpoint Interrupt Status
-        EPINTST: mmio.Mmio(packed struct(u32) {
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST0: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST1: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST2: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST3: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST4: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST5: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST6: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST7: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST8: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST9: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST10: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST11: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST12: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST13: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST14: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST15: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST16: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST17: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST18: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST19: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST20: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST21: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST22: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST23: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST24: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST25: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST26: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST27: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST28: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST29: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST30: u1,
-            ///  1 = Endpoint Data Received (bits 0, 2, 4, ..., 30) or Transmitted (bits 1, 3, 5, ..., 31) Interrupt received.
-            EPST31: u1,
-        }),
-        ///  USB Endpoint Interrupt Enable
-        EPINTEN: mmio.Mmio(packed struct(u32) {
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN0: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN1: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN2: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN3: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN4: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN5: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN6: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN7: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN8: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN9: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN10: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN11: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN12: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN13: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN14: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN15: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN16: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN17: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN18: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN19: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN20: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN21: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN22: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN23: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN24: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN25: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN26: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN27: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN28: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN29: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN30: u1,
-            ///  0= The corresponding bit in USBDMARSt is set when an interrupt occurs for this endpoint. 1 = The corresponding bit in USBEpIntSt is set when an interrupt occurs for this endpoint. Implies Slave mode for this endpoint.
-            EPEN31: u1,
-        }),
-        ///  USB Endpoint Interrupt Clear
-        EPINTCLR: mmio.Mmio(packed struct(u32) {
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR0: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR1: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR2: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR3: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR4: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR5: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR6: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR7: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR8: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR9: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR10: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR11: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR12: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR13: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR14: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR15: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR16: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR17: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR18: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR19: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR20: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR21: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR22: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR23: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR24: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR25: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR26: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR27: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR28: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR29: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR30: u1,
-            ///  0 = No effect. 1 = Clears the corresponding bit in USBEpIntSt, by executing the SIE Select Endpoint/Clear Interrupt command for this endpoint.
-            EPCLR31: u1,
-        }),
-        ///  USB Endpoint Interrupt Set
-        EPINTSET: mmio.Mmio(packed struct(u32) {
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET0: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET1: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET2: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET3: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET4: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET5: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET6: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET7: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET8: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET9: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET10: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET11: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET12: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET13: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET14: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET15: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET16: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET17: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET18: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET19: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET20: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET21: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET22: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET23: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET24: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET25: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET26: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET27: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET28: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET29: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET30: u1,
-            ///  0 = No effect. 1 = Sets the corresponding bit in USBEpIntSt.
-            EPSET31: u1,
-        }),
-        ///  USB Endpoint Priority
-        EPINTPRI: mmio.Mmio(packed struct(u32) {
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI0: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI1: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI2: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI3: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI4: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI5: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI6: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI7: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI8: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI9: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI10: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI11: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI12: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI13: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI14: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI15: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI16: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI17: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI18: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI19: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI20: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI21: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI22: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI23: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI24: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI25: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI26: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI27: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI28: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI29: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI30: u1,
-            ///  0 = The corresponding interrupt is routed to the EP_SLOW bit of USBDevIntSt 1 = The corresponding interrupt is routed to the EP_FAST bit of USBDevIntSt
-            EPPRI31: u1,
-        }),
-        ///  USB Realize Endpoint
-        REEP: mmio.Mmio(packed struct(u32) {
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR0: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR1: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR2: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR3: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR4: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR5: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR6: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR7: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR8: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR9: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR10: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR11: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR12: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR13: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR14: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR15: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR16: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR17: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR18: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR19: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR20: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR21: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR22: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR23: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR24: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR25: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR26: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR27: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR28: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR29: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR30: u1,
-            ///  0 = Endpoint EPxx is not realized. 1 = Endpoint EPxx is realized.
-            EPR31: u1,
-        }),
-        ///  USB Endpoint Index
-        EPIND: mmio.Mmio(packed struct(u32) {
-            ///  Physical endpoint number (0-31)
-            PHY_EP: u5,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u27,
-        }),
-        ///  USB MaxPacketSize
-        MAXPSIZE: mmio.Mmio(packed struct(u32) {
-            ///  The maximum packet size value.
-            MPS: u10,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u22,
-        }),
-        ///  USB DMA Request Status
-        DMARST: mmio.Mmio(packed struct(u32) {
-            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and EP0 bit must be 0).
-            EPRST0: u1,
-            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and EP1 bit must be 0).
-            EPRST1: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST2: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST3: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST4: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST5: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST6: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST7: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST8: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST9: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST10: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST11: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST12: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST13: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST14: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST15: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST16: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST17: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST18: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST19: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST20: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST21: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST22: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST23: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST24: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST25: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST26: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST27: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST28: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST29: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST30: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA request. 0 = DMA not requested by endpoint xx. 1 = DMA requested by endpoint xx.
-            EPRST31: u1,
-        }),
-        ///  USB DMA Request Clear
-        DMARCLR: mmio.Mmio(packed struct(u32) {
-            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).
-            EPRCLR0: u1,
-            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).
-            EPRCLR1: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR2: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR3: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR4: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR5: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR6: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR7: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR8: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR9: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR10: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR11: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR12: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR13: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR14: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR15: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR16: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR17: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR18: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR19: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR20: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR21: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR22: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR23: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR24: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR25: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR26: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR27: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR28: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR29: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR30: u1,
-            ///  Clear the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Clear the corresponding bit in USBDMARSt.
-            EPRCLR31: u1,
-        }),
-        ///  USB DMA Request Set
-        DMARSET: mmio.Mmio(packed struct(u32) {
-            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0 bit must be 0).
-            EPRSET0: u1,
-            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1 bit must be 0).
-            EPRSET1: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET2: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET3: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET4: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET5: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET6: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET7: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET8: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET9: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET10: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET11: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET12: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET13: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET14: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET15: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET16: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET17: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET18: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET19: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET20: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET21: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET22: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET23: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET24: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET25: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET26: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET27: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET28: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET29: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET30: u1,
-            ///  Set the endpoint xx (2 <= xx <= 31) DMA request. 0 = No effect 1 = Set the corresponding bit in USBDMARSt.
-            EPRSET31: u1,
-        }),
-        reserved640: [36]u8,
-        ///  USB UDCA Head
-        UDCAH: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written. The UDCA is aligned to 128-byte boundaries.
-            RESERVED: u7,
-            ///  Start address of the UDCA.
-            UDCA_ADDR: u25,
-        }),
-        ///  USB Endpoint DMA Status
-        EPDMAST: mmio.Mmio(packed struct(u32) {
-            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit must be 0).
-            EP_DMA_ST0: u1,
-            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).
-            EP_DMA_ST1: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST2: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST3: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST4: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST5: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST6: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST7: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST8: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST9: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST10: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST11: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST12: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST13: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST14: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST15: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST16: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST17: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST18: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST19: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST20: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST21: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST22: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST23: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST24: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST25: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST26: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST27: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST28: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST29: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST30: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA enabled bit. 0 = The DMA for endpoint EPxx is disabled. 1 = The DMA for endpoint EPxx is enabled.
-            EP_DMA_ST31: u1,
-        }),
-        ///  USB Endpoint DMA Enable
-        EPDMAEN: mmio.Mmio(packed struct(u32) {
-            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_ENABLE bit value must be 0).
-            EP_DMA_EN0: u1,
-            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_ENABLE bit must be 0).
-            EP_DMA_EN1: u1,
-            ///  Endpoint xx(2 <= xx <= 31) DMA enable control bit. 0 = No effect. 1 = Enable the DMA operation for endpoint EPxx.
-            EP_DMA_EN: u30,
-        }),
-        ///  USB Endpoint DMA Disable
-        EPDMADIS: mmio.Mmio(packed struct(u32) {
-            ///  Control endpoint OUT (DMA cannot be enabled for this endpoint and the EP0_DMA_DISABLE bit value must be 0).
-            EP_DMA_DIS0: u1,
-            ///  Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1_DMA_DISABLE bit value must be 0).
-            EP_DMA_DIS1: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS2: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS3: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS4: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS5: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS6: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS7: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS8: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS9: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS10: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS11: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS12: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS13: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS14: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS15: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS16: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS17: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS18: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS19: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS20: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS21: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS22: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS23: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS24: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS25: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS26: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS27: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS28: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS29: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS30: u1,
-            ///  Endpoint xx (2 <= xx <= 31) DMA disable control bit. 0 = No effect. 1 = Disable the DMA operation for endpoint EPxx.
-            EP_DMA_DIS31: u1,
-        }),
-        ///  USB DMA Interrupt Status
-        DMAINTST: mmio.Mmio(packed struct(u32) {
-            ///  End of Transfer Interrupt bit.
-            EOT: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  All bits in the USBEoTIntSt register are 0.
-                    ALL_BITS_IN_THE_USBE = 0x0,
-                    ///  At least one bit in the USBEoTIntSt is set.
-                    AT_LEAST_ONE_BIT_IN_ = 0x1,
-                },
-            },
-            ///  New DD Request Interrupt bit.
-            NDDR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  All bits in the USBNDDRIntSt register are 0.
-                    ALL_BITS_IN_THE_USBN = 0x0,
-                    ///  At least one bit in the USBNDDRIntSt is set.
-                    AT_LEAST_ONE_BIT_IN_ = 0x1,
-                },
-            },
-            ///  System Error Interrupt bit.
-            ERR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  All bits in the USBSysErrIntSt register are 0.
-                    ALL_BITS_IN_THE_USBS = 0x0,
-                    ///  At least one bit in the USBSysErrIntSt is set.
-                    AT_LEAST_ONE_BIT_IN_ = 0x1,
-                },
-            },
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u29,
-        }),
-        ///  USB DMA Interrupt Enable
-        DMAINTEN: mmio.Mmio(packed struct(u32) {
-            ///  End of Transfer Interrupt enable bit.
-            EOT: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Enabled.
-                    ENABLED_ = 0x1,
-                },
-            },
-            ///  New DD Request Interrupt enable bit.
-            NDDR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Enabled.
-                    ENABLED_ = 0x1,
-                },
-            },
-            ///  System Error Interrupt enable bit.
-            ERR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled.
-                    DISABLED_ = 0x0,
-                    ///  Enabled.
-                    ENABLED_ = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u29,
-        }),
-        reserved672: [8]u8,
-        ///  USB End of Transfer Interrupt Status
-        EOTINTST: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST0: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST1: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST2: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST3: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST4: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST5: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST6: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST7: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST8: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST9: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST10: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST11: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST12: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST13: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST14: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST15: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST16: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST17: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST18: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST19: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST20: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST21: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST22: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST23: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST24: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST25: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST26: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST27: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST28: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST29: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST30: u1,
-            ///  Endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = There is no End of Transfer interrupt request for endpoint xx. 1 = There is an End of Transfer Interrupt request for endpoint xx.
-            EPTXINTST31: u1,
-        }),
-        ///  USB End of Transfer Interrupt Clear
-        EOTINTCLR: mmio.Mmio(packed struct(u32) {
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR0: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR1: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR2: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR3: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR4: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR5: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR6: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR7: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR8: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR9: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR10: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR11: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR12: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR13: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR14: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR15: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR16: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR17: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR18: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR19: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR20: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR21: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR22: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR23: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR24: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR25: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR26: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR27: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR28: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR29: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR30: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Clear the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTCLR31: u1,
-        }),
-        ///  USB End of Transfer Interrupt Set
-        EOTINTSET: mmio.Mmio(packed struct(u32) {
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET0: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET1: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET2: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET3: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET4: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET5: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET6: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET7: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET8: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET9: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET10: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET11: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET12: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET13: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET14: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET15: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET16: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET17: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET18: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET19: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET20: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET21: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET22: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET23: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET24: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET25: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET26: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET27: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET28: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET29: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET30: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) End of Transfer Interrupt request. 0 = No effect. 1 = Set the EPxx End of Transfer Interrupt request in the USBEoTIntSt register.
-            EPTXINTSET31: u1,
-        }),
-        ///  USB New DD Request Interrupt Status
-        NDDRINTST: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST0: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST1: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST2: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST3: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST4: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST5: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST6: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST7: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST8: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST9: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST10: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST11: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST12: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST13: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST14: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST15: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST16: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST17: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST18: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST19: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST20: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST21: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST22: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST23: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST24: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST25: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST26: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST27: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST28: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST29: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST30: u1,
-            ///  Endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = There is no new DD interrupt request for endpoint xx. 1 = There is a new DD interrupt request for endpoint xx.
-            EPNDDINTST31: u1,
-        }),
-        ///  USB New DD Request Interrupt Clear
-        NDDRINTCLR: mmio.Mmio(packed struct(u32) {
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR0: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR1: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR2: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR3: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR4: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR5: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR6: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR7: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR8: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR9: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR10: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR11: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR12: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR13: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR14: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR15: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR16: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR17: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR18: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR19: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR20: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR21: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR22: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR23: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR24: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR25: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR26: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR27: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR28: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR29: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR30: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Clear the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTCLR31: u1,
-        }),
-        ///  USB New DD Request Interrupt Set
-        NDDRINTSET: mmio.Mmio(packed struct(u32) {
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET0: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET1: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET2: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET3: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET4: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET5: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET6: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET7: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET8: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET9: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET10: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET11: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET12: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET13: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET14: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET15: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET16: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET17: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET18: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET19: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET20: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET21: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET22: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET23: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET24: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET25: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET26: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET27: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET28: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET29: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET30: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) new DD interrupt request. 0 = No effect. 1 = Set the EPxx new DD interrupt request in the USBNDDRIntSt register.
-            EPNDDINTSET31: u1,
-        }),
-        ///  USB System Error Interrupt Status
-        SYSERRINTST: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST0: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST1: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST2: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST3: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST4: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST5: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST6: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST7: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST8: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST9: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST10: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST11: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST12: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST13: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST14: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST15: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST16: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST17: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST18: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST19: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST20: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST21: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST22: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST23: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST24: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST25: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST26: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST27: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST28: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST29: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST30: u1,
-            ///  Endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = There is no System Error Interrupt request for endpoint xx. 1 = There is a System Error Interrupt request for endpoint xx.
-            EPERRINTST31: u1,
-        }),
-        ///  USB System Error Interrupt Clear
-        SYSERRINTCLR: mmio.Mmio(packed struct(u32) {
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR0: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR1: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR2: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR3: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR4: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR5: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR6: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR7: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR8: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR9: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR10: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR11: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR12: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR13: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR14: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR15: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR16: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR17: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR18: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR19: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR20: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR21: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR22: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR23: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR24: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR25: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR26: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR27: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR28: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR29: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR30: u1,
-            ///  Clear endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Clear the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTCLR31: u1,
-        }),
-        ///  USB System Error Interrupt Set
-        SYSERRINTSET: mmio.Mmio(packed struct(u32) {
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET0: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET1: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET2: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET3: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET4: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET5: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET6: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET7: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET8: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET9: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET10: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET11: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET12: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET13: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET14: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET15: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET16: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET17: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET18: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET19: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET20: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET21: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET22: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET23: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET24: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET25: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET26: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET27: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET28: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET29: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET30: u1,
-            ///  Set endpoint xx (2 <= xx <= 31) System Error Interrupt request. 0 = No effect. 1 = Set the EPxx System Error Interrupt request in the USBSysErrIntSt register.
-            EPERRINTSET31: u1,
-        }),
-        reserved768: [60]u8,
-        ///  I2C Receive
-        I2C_RX: mmio.Mmio(packed struct(u32) {
-            ///  Receive data.
-            RXDATA: u8,
-            padding: u24,
-        }),
-        ///  I2C Status
-        I2C_STS: mmio.Mmio(packed struct(u32) {
-            ///  Transaction Done Interrupt. This flag is set if a transaction completes successfully. It is cleared by writing a one to bit 0 of the status register. It is unaffected by slave transactions.
-            TDI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Transaction has not completed.
-                    NOT_COMPLETE = 0x0,
-                    ///  Transaction completed.
-                    COMPLETE = 0x1,
-                },
-            },
-            ///  Arbitration Failure Interrupt. When transmitting, if the SDA is low when SDAOUT is high, then this I2C has lost the arbitration to another device on the bus. The Arbitration Failure bit is set when this happens. It is cleared by writing a one to bit 1 of the status register.
-            AFI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No arbitration failure on last transmission.
-                    NO_ARBITRATION_FAILU = 0x0,
-                    ///  Arbitration failure occurred on last transmission.
-                    ARBITRATION_FAILURE_ = 0x1,
-                },
-            },
-            ///  No Acknowledge Interrupt. After every byte of data is sent, the transmitter expects an acknowledge from the receiver. This bit is set if the acknowledge is not received. It is cleared when a byte is written to the master TX FIFO.
-            NAI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Last transmission received an acknowledge.
-                    ACKNOWLEDGE_RCVD = 0x0,
-                    ///  Last transmission did not receive an acknowledge.
-                    NO_ACKNOWLEDGE_RCVD = 0x1,
-                },
-            },
-            ///  Master Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a stop condition or it will hold SCL low until more data is available. The Master Data Request bit is set when the master transmitter is data-starved. If the master TX FIFO is empty and the last byte did not have a STOP condition flag, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the master TX FIFO.
-            DRMI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Master transmitter does not need data.
-                    BUSY = 0x0,
-                    ///  Master transmitter needs data.
-                    NEED_DATA = 0x1,
-                },
-            },
-            ///  Slave Data Request Interrupt. Once a transmission is started, the transmitter must have data to transmit as long as it isn't followed by a STOP condition or it will hold SCL low until more data is available. The Slave Data Request bit is set when the slave transmitter is data-starved. If the slave TX FIFO is empty and the last byte transmitted was acknowledged, then SCL is held low until the CPU writes another byte to transmit. This bit is cleared when a byte is written to the slave Tx FIFO.
-            DRSI: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Slave transmitter does not need data.
-                    BUSY = 0x0,
-                    ///  Slave transmitter needs data.
-                    NEED_DATA = 0x1,
-                },
-            },
-            ///  Indicates whether the bus is busy. This bit is set when a START condition has been seen. It is cleared when a STOP condition is seen..
-            Active: u1,
-            ///  The current value of the SCL signal.
-            SCL: u1,
-            ///  The current value of the SDA signal.
-            SDA: u1,
-            ///  Receive FIFO Full (RFF). This bit is set when the RX FIFO is full and cannot accept any more data. It is cleared when the RX FIFO is not full. If a byte arrives when the Receive FIFO is full, the SCL is held low until the CPU reads the RX FIFO and makes room for it.
-            RFF: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  RX FIFO is not full
-                    RX_FIFO_IS_NOT_FULL = 0x0,
-                    ///  RX FIFO is full
-                    RX_FIFO_IS_FULL = 0x1,
-                },
-            },
-            ///  Receive FIFO Empty. RFE is set when the RX FIFO is empty and is cleared when the RX FIFO contains valid data.
-            RFE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  RX FIFO contains data.
-                    DATA = 0x0,
-                    ///  RX FIFO is empty
-                    EMPTY = 0x1,
-                },
-            },
-            ///  Transmit FIFO Full. TFF is set when the TX FIFO is full and is cleared when the TX FIFO is not full.
-            TFF: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  TX FIFO is not full.
-                    TX_FIFO_IS_NOT_FULL_ = 0x0,
-                    ///  TX FIFO is full
-                    TX_FIFO_IS_FULL = 0x1,
-                },
-            },
-            ///  Transmit FIFO Empty. TFE is set when the TX FIFO is empty and is cleared when the TX FIFO contains valid data.
-            TFE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  TX FIFO contains valid data.
-                    VALID_DATA = 0x0,
-                    ///  TX FIFO is empty
-                    EMPTY = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u20,
-        }),
-        ///  I2C Control
-        I2C_CTL: mmio.Mmio(packed struct(u32) {
-            ///  Transmit Done Interrupt Enable. This enables the TDI interrupt signalling that this I2C issued a STOP condition.
-            TDIE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable the TDI interrupt.
-                    DISABLE_THE_TDI_INTE = 0x0,
-                    ///  Enable the TDI interrupt.
-                    ENABLE_THE_TDI_INTER = 0x1,
-                },
-            },
-            ///  Transmitter Arbitration Failure Interrupt Enable. This enables the AFI interrupt which is asserted during transmission when trying to set SDA high, but the bus is driven low by another device.
-            AFIE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable the AFI.
-                    DISABLE_THE_AFI_ = 0x0,
-                    ///  Enable the AFI.
-                    ENABLE_THE_AFI_ = 0x1,
-                },
-            },
-            ///  Transmitter No Acknowledge Interrupt Enable. This enables the NAI interrupt signalling that transmitted byte was not acknowledged.
-            NAIE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable the NAI.
-                    DISABLE_THE_NAI_ = 0x0,
-                    ///  Enable the NAI.
-                    ENABLE_THE_NAI_ = 0x1,
-                },
-            },
-            ///  Master Transmitter Data Request Interrupt Enable. This enables the DRMI interrupt which signals that the master transmitter has run out of data, has not issued a STOP, and is holding the SCL line low.
-            DRMIE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable the DRMI interrupt.
-                    DISABLE_THE_DRMI_INT = 0x0,
-                    ///  Enable the DRMI interrupt.
-                    ENABLE_THE_DRMI_INTE = 0x1,
-                },
-            },
-            ///  Slave Transmitter Data Request Interrupt Enable. This enables the DRSI interrupt which signals that the slave transmitter has run out of data and the last byte was acknowledged, so the SCL line is being held low.
-            DRSIE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable the DRSI interrupt.
-                    DISABLE_THE_DRSI_INT = 0x0,
-                    ///  Enable the DRSI interrupt.
-                    ENABLE_THE_DRSI_INTE = 0x1,
-                },
-            },
-            ///  Receive FIFO Full Interrupt Enable. This enables the Receive FIFO Full interrupt to indicate that the receive FIFO cannot accept any more data.
-            REFIE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable the RFFI.
-                    DISABLE_THE_RFFI_ = 0x0,
-                    ///  Enable the RFFI.
-                    ENABLE_THE_RFFI_ = 0x1,
-                },
-            },
-            ///  Receive Data Available Interrupt Enable. This enables the DAI interrupt to indicate that data is available in the receive FIFO (i.e. not empty).
-            RFDAIE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable the DAI.
-                    DISABLE_THE_DAI_ = 0x0,
-                    ///  Enable the DAI.
-                    ENABLE_THE_DAI_ = 0x1,
-                },
-            },
-            ///  Transmit FIFO Not Full Interrupt Enable. This enables the Transmit FIFO Not Full interrupt to indicate that the more data can be written to the transmit FIFO. Note that this is not full. It is intended help the CPU to write to the I2C block only when there is room in the FIFO and do this without polling the status register.
-            TFFIE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable the TFFI.
-                    DISABLE_THE_TFFI_ = 0x0,
-                    ///  Enable the TFFI.
-                    ENABLE_THE_TFFI_ = 0x1,
-                },
-            },
-            ///  Soft reset. This is only needed in unusual circumstances. If a device issues a start condition without issuing a stop condition. A system timer may be used to reset the I2C if the bus remains busy longer than the time-out period. On a soft reset, the Tx and Rx FIFOs are flushed, I2C_STS register is cleared, and all internal state machines are reset to appear idle. The I2C_CLKHI, I2C_CLKLO and I2C_CTL (except Soft Reset Bit) are NOT modified by a soft reset.
-            SRST: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  No reset.
-                    NO_RESET = 0x0,
-                    ///  Reset the I2C to idle state. Self clearing.
-                    RESET = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u23,
-        }),
-        ///  I2C Clock High
-        I2C_CLKHI: mmio.Mmio(packed struct(u32) {
-            ///  Clock divisor high. This value is the number of 48 MHz clocks the serial clock (SCL) will be high.
-            CDHI: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  I2C Clock Low
-        I2C_CLKLO: mmio.Mmio(packed struct(u32) {
-            ///  Clock divisor low. This value is the number of 48 MHz clocks the serial clock (SCL) will be low.
-            CDLO: u8,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        reserved4084: [3296]u8,
-        ///  USB Clock Control
-        USBCLKCTRL: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  Device clock enable. Enables the usbclk input to the device controller
-            DEV_CLK_EN: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  Port select register clock enable.
-            PORTSEL_CLK_EN: u1,
-            ///  AHB clock enable
-            AHB_CLK_EN: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u27,
-        }),
-        ///  USB Clock Status
-        USBCLKST: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  Device clock on. The usbclk input to the device controller is active .
-            DEV_CLK_ON: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  Port select register clock on.
-            PORTSEL_CLK_ON: u1,
-            ///  AHB clock on.
-            AHB_CLK_ON: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u27,
-        }),
-    };
-
-    ///  General purpose DMA controller
-    pub const GPDMA = extern struct {
-        ///  DMA Interrupt Status Register
-        INTSTAT: mmio.Mmio(packed struct(u32) {
-            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
-            INTSTAT0: u1,
-            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
-            INTSTAT1: u1,
-            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
-            INTSTAT2: u1,
-            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
-            INTSTAT3: u1,
-            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
-            INTSTAT4: u1,
-            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
-            INTSTAT5: u1,
-            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
-            INTSTAT6: u1,
-            ///  Status of DMA channel interrupts after masking. Each bit represents one channel: 0 - the corresponding channel has no active interrupt request. 1 - the corresponding channel does have an active interrupt request.
-            INTSTAT7: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  DMA Interrupt Terminal Count Request Status Register
-        INTTCSTAT: mmio.Mmio(packed struct(u32) {
-            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            INTTCSTAT0: u1,
-            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            INTTCSTAT1: u1,
-            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            INTTCSTAT2: u1,
-            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            INTTCSTAT3: u1,
-            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            INTTCSTAT4: u1,
-            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            INTTCSTAT5: u1,
-            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            INTTCSTAT6: u1,
-            ///  Terminal count interrupt request status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            INTTCSTAT7: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  DMA Interrupt Terminal Count Request Clear Register
-        INTTCCLEAR: mmio.Mmio(packed struct(u32) {
-            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
-            INTTCCLEAR0: u1,
-            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
-            INTTCCLEAR1: u1,
-            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
-            INTTCCLEAR2: u1,
-            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
-            INTTCCLEAR3: u1,
-            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
-            INTTCCLEAR4: u1,
-            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
-            INTTCCLEAR5: u1,
-            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
-            INTTCCLEAR6: u1,
-            ///  Allows clearing the Terminal count interrupt request (IntTCStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel terminal count interrupt.
-            INTTCCLEAR7: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  DMA Interrupt Error Status Register
-        INTERRSTAT: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            INTERRSTAT0: u1,
-            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            INTERRSTAT1: u1,
-            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            INTERRSTAT2: u1,
-            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            INTERRSTAT3: u1,
-            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            INTERRSTAT4: u1,
-            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            INTERRSTAT5: u1,
-            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            INTERRSTAT6: u1,
-            ///  Interrupt error status for DMA channels. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            INTERRSTAT7: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  DMA Interrupt Error Clear Register
-        INTERRCLR: mmio.Mmio(packed struct(u32) {
-            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
-            INTERRCLR0: u1,
-            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
-            INTERRCLR1: u1,
-            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
-            INTERRCLR2: u1,
-            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
-            INTERRCLR3: u1,
-            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
-            INTERRCLR4: u1,
-            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
-            INTERRCLR5: u1,
-            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
-            INTERRCLR6: u1,
-            ///  Writing a 1 clears the error interrupt request (IntErrStat) for DMA channels. Each bit represents one channel: 0 - writing 0 has no effect. 1 - clears the corresponding channel error interrupt.
-            INTERRCLR7: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  DMA Raw Interrupt Terminal Count Status Register
-        RAWINTTCSTAT: mmio.Mmio(packed struct(u32) {
-            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            RAWINTTCSTAT0: u1,
-            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            RAWINTTCSTAT1: u1,
-            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            RAWINTTCSTAT2: u1,
-            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            RAWINTTCSTAT3: u1,
-            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            RAWINTTCSTAT4: u1,
-            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            RAWINTTCSTAT5: u1,
-            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            RAWINTTCSTAT6: u1,
-            ///  Status of the terminal count interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active terminal count interrupt request. 1 - the corresponding channel does have an active terminal count interrupt request.
-            RAWINTTCSTAT7: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  DMA Raw Error Interrupt Status Register
-        RAWINTERRSTAT: mmio.Mmio(packed struct(u32) {
-            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            RAWINTERRSTAT0: u1,
-            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            RAWINTERRSTAT1: u1,
-            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            RAWINTERRSTAT2: u1,
-            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            RAWINTERRSTAT3: u1,
-            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            RAWINTERRSTAT4: u1,
-            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            RAWINTERRSTAT5: u1,
-            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            RAWINTERRSTAT6: u1,
-            ///  Status of the error interrupt for DMA channels prior to masking. Each bit represents one channel: 0 - the corresponding channel has no active error interrupt request. 1 - the corresponding channel does have an active error interrupt request.
-            RAWINTERRSTAT7: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  DMA Enabled Channel Register
-        ENBLDCHNS: mmio.Mmio(packed struct(u32) {
-            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
-            ENABLEDCHANNELS0: u1,
-            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
-            ENABLEDCHANNELS1: u1,
-            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
-            ENABLEDCHANNELS2: u1,
-            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
-            ENABLEDCHANNELS3: u1,
-            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
-            ENABLEDCHANNELS4: u1,
-            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
-            ENABLEDCHANNELS5: u1,
-            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
-            ENABLEDCHANNELS6: u1,
-            ///  Enable status for DMA channels. Each bit represents one channel: 0 - DMA channel is disabled. 1 - DMA channel is enabled.
-            ENABLEDCHANNELS7: u1,
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  DMA Software Burst Request Register
-        SOFTBREQ: mmio.Mmio(packed struct(u32) {
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ0: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ1: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ2: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ3: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ4: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ5: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ6: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ7: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ8: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ9: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ10: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ11: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ12: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ13: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ14: u1,
-            ///  Software burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral Description (refer to Table 672 for peripheral hardware connections to the DMA controller): 0 - writing 0 has no effect. 1 - writing 1 generates a DMA burst request for the corresponding request line.
-            SOFTBREQ15: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-        ///  DMA Software Single Request Register
-        SOFTSREQ: mmio.Mmio(packed struct(u32) {
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ0: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ1: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ2: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ3: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ4: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ5: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ6: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ7: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ8: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ9: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ10: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ11: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ12: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ13: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ14: u1,
-            ///  Software single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA single transfer request for the corresponding request line.
-            SOFTSREQ15: u1,
-            ///  Reserved. Read undefined. Write reserved bits as zero.
-            RESERVED: u16,
-        }),
-        ///  DMA Software Last Burst Request Register
-        SOFTLBREQ: mmio.Mmio(packed struct(u32) {
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ0: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ1: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ2: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ3: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ4: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ5: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ6: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ7: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ8: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ9: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ10: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ11: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ12: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ13: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ14: u1,
-            ///  Software last burst request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last burst request for the corresponding request line.
-            SOFTLBREQ15: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-        ///  DMA Software Last Single Request Register
-        SOFTLSREQ: mmio.Mmio(packed struct(u32) {
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ0: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ1: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ2: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ3: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ4: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ5: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ6: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ7: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ8: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ9: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ10: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ11: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ12: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ13: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ14: u1,
-            ///  Software last single transfer request flags for each of 16 possible sources. Each bit represents one DMA request line or peripheral function: 0 - writing 0 has no effect. 1 - writing 1 generates a DMA last single transfer request for the corresponding request line.
-            SOFTLSREQ15: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-        ///  DMA Configuration Register
-        CONFIG: mmio.Mmio(packed struct(u32) {
-            ///  DMA Controller enable: 0 = disabled (default). Disabling the DMA Controller reduces power consumption. 1 = enabled.
-            E: u1,
-            ///  AHB Master endianness configuration: 0 = little-endian mode (default). 1 = big-endian mode.
-            M: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u30,
-        }),
-        ///  DMA Synchronization Register
-        SYNC: mmio.Mmio(packed struct(u32) {
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC0: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC1: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC2: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC3: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC4: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC5: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC6: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC7: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC8: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC9: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC10: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC11: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC12: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC13: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC14: u1,
-            ///  Controls the synchronization logic for DMA request signals. Each bit represents one set of DMA request lines as described in the preceding text: 0 - synchronization logic for the corresponding DMA request signals are enabled. 1 - synchronization logic for the corresponding DMA request signals are disabled.
-            DMACSYNC15: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-    };
-
-    ///  Ethernet
-    pub const EMAC = extern struct {
-        ///  MAC configuration register 1.
-        MAC1: mmio.Mmio(packed struct(u32) {
-            ///  RECEIVE ENABLE. Set this to allow receive frames to be received. Internally the MAC synchronizes this control bit to the incoming receive stream.
-            RXENABLE: u1,
-            ///  PASS ALL RECEIVE FRAMES. When enabled (set to 1), the MAC will pass all frames regardless of type (normal vs. Control). When disabled, the MAC does not pass valid Control frames.
-            PARF: u1,
-            ///  RX FLOW CONTROL. When enabled (set to 1), the MAC acts upon received PAUSE Flow Control frames. When disabled, received PAUSE Flow Control frames are ignored.
-            RXFLOWCTRL: u1,
-            ///  TX FLOW CONTROL. When enabled (set to 1), PAUSE Flow Control frames are allowed to be transmitted. When disabled, Flow Control frames are blocked.
-            TXFLOWCTRL: u1,
-            ///  Setting this bit will cause the MAC Transmit interface to be looped back to the MAC Receive interface. Clearing this bit results in normal operation.
-            LOOPBACK: u1,
-            ///  Unused
-            RESERVED: u3,
-            ///  Setting this bit will put the Transmit Function logic in reset.
-            RESETTX: u1,
-            ///  Setting this bit resets the MAC Control Sublayer / Transmit logic. The MCS logic implements flow control.
-            RESETMCSTX: u1,
-            ///  Setting this bit will put the Ethernet receive logic in reset.
-            RESETRX: u1,
-            ///  Setting this bit resets the MAC Control Sublayer / Receive logic. The MCS logic implements flow control.
-            RESETMCSRX: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  SIMULATION RESET. Setting this bit will cause a reset to the random number generator within the Transmit Function.
-            SIMRESET: u1,
-            ///  SOFT RESET. Setting this bit will put all modules within the MAC in reset except the Host Interface.
-            SOFTRESET: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-        ///  MAC configuration register 2.
-        MAC2: mmio.Mmio(packed struct(u32) {
-            ///  When enabled (set to 1), the MAC operates in Full-Duplex mode. When disabled, the MAC operates in Half-Duplex mode.
-            FULLDUPLEX: u1,
-            ///  FRAMELENGTH CHECKING. When enabled (set to 1), both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field represents a length then the check is performed. Mismatches are reported in the StatusInfo word for each received frame.
-            FLC: u1,
-            ///  HUGE FRAME ENABLEWhen enabled (set to 1), frames of any length are transmitted and received.
-            HFEN: u1,
-            ///  DELAYED CRC. This bit determines the number of bytes, if any, of proprietary header information that exist on the front of IEEE 802.3 frames. When 1, four bytes of header (ignored by the CRC function) are added. When 0, there is no proprietary header.
-            DELAYEDCRC: u1,
-            ///  CRC ENABLESet this bit to append a CRC to every frame whether padding was required or not. Must be set if PAD/CRC ENABLE is set. Clear this bit if frames presented to the MAC contain a CRC.
-            CRCEN: u1,
-            ///  PAD CRC ENABLE. Set this bit to have the MAC pad all short frames. Clear this bit if frames presented to the MAC have a valid length. This bit is used in conjunction with AUTO PAD ENABLE and VLAN PAD ENABLE. See Table 153 - Pad Operation for details on the pad function.
-            PADCRCEN: u1,
-            ///  VLAN PAD ENABLE. Set this bit to cause the MAC to pad all short frames to 64 bytes and append a valid CRC. Consult Table 153 - Pad Operation for more information on the various padding features. Note: This bit is ignored if PAD / CRC ENABLE is cleared.
-            VLANPADEN: u1,
-            ///  AUTODETECTPAD ENABLE. Set this bit to cause the MAC to automatically detect the type of frame, either tagged or un-tagged, by comparing the two octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly. Table 153 - Pad Operation provides a description of the pad function based on the configuration of this register. Note: This bit is ignored if PAD / CRC ENABLE is cleared.
-            AUTODETPADEN: u1,
-            ///  PURE PREAMBLE ENFORCEMEN. When enabled (set to 1), the MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with an incorrect preamble is discarded. When disabled, no preamble checking is performed.
-            PPENF: u1,
-            ///  LONG PREAMBLE ENFORCEMENT. When enabled (set to 1), the MAC only allows receive packets which contain preamble fields less than 12 bytes in length. When disabled, the MAC allows any length preamble as per the Standard.
-            LPENF: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u2,
-            ///  When enabled (set to 1), the MAC will immediately retransmit following a collision rather than using the Binary Exponential Backoff algorithm as specified in the Standard.
-            NOBACKOFF: u1,
-            ///  BACK PRESSURE / NO BACKOFF. When enabled (set to 1), after the MAC incidentally causes a collision during back pressure, it will immediately retransmit without backoff, reducing the chance of further collisions and ensuring transmit packets get sent.
-            BP_NOBACKOFF: u1,
-            ///  When enabled (set to 1) the MAC will defer to carrier indefinitely as per the Standard. When disabled, the MAC will abort when the excessive deferral limit is reached.
-            EXCESSDEFER: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u17,
-        }),
-        ///  Back-to-Back Inter-Packet-Gap register.
-        IPGT: mmio.Mmio(packed struct(u32) {
-            ///  BACK-TO-BACK INTER-PACKET-GAP.This is a programmable field representing the nibble time offset of the minimum possible period between the end of any transmitted packet to the beginning of the next. In Full-Duplex mode, the register value should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode). In Half-Duplex the recommended setting is 0x12 (18d), which also represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode).
-            BTOBINTEGAP: u7,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u25,
-        }),
-        ///  Non Back-to-Back Inter-Packet-Gap register.
-        IPGR: mmio.Mmio(packed struct(u32) {
-            ///  NON-BACK-TO-BACK INTER-PACKET-GAP PART2. This is a programmable field representing the Non-Back-to-Back Inter-Packet-Gap. The recommended value is 0x12 (18d), which represents the minimum IPG of 960 ns (in 100 Mbps mode) or 9.6 us (in 10 Mbps mode).
-            NBTOBINTEGAP2: u7,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  NON-BACK-TO-BACK INTER-PACKET-GAP PART1. This is a programmable field representing the optional carrierSense window referenced in IEEE 802.3/4.2.3.2.1 'Carrier Deference'. If carrier is detected during the timing of IPGR1, the MAC defers to carrier. If, however, carrier becomes active after IPGR1, the MAC continues timing IPGR2 and transmits, knowingly causing a collision, thus ensuring fair access to medium. Its range of values is 0x0 to IPGR2. The recommended value is 0xC (12d)
-            NBTOBINTEGAP1: u7,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u17,
-        }),
-        ///  Collision window / Retry register.
-        CLRT: mmio.Mmio(packed struct(u32) {
-            ///  RETRANSMISSION MAXIMUM.This is a programmable field specifying the number of retransmission attempts following a collision before aborting the packet due to excessive collisions. The Standard specifies the attemptLimit to be 0xF (15d). See IEEE 802.3/4.2.3.2.5.
-            RETRANSMAX: u4,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u4,
-            ///  COLLISION WINDOW. This is a programmable field representing the slot time or collision window during which collisions occur in properly configured networks. The default value of 0x37 (55d) represents a 56 byte window following the preamble and SFD.
-            COLLWIN: u6,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u18,
-        }),
-        ///  Maximum Frame register.
-        MAXF: mmio.Mmio(packed struct(u32) {
-            ///  MAXIMUM FRAME LENGTH. This field resets to the value 0x0600, which represents a maximum receive frame of 1536 octets. An untagged maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If a shorter maximum length restriction is desired, program this 16-bit field.
-            MAXFLEN: u16,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        ///  PHY Support register.
-        SUPP: mmio.Mmio(packed struct(u32) {
-            ///  Unused
-            RESERVED: u8,
-            ///  This bit configures the Reduced MII logic for the current operating speed. When set, 100 Mbps mode is selected. When cleared, 10 Mbps mode is selected.
-            SPEED: u1,
-            ///  Unused
-            RESERVED: u23,
-        }),
-        ///  Test register.
-        TEST: mmio.Mmio(packed struct(u32) {
-            ///  SHORTCUT PAUSE QUANTA. This bit reduces the effective PAUSE quanta from 64 byte-times to 1 byte-time.
-            SCPQ: u1,
-            ///  This bit causes the MAC Control sublayer to inhibit transmissions, just as if a PAUSE Receive Control frame with a nonzero pause time parameter was received.
-            TESTPAUSE: u1,
-            ///  TEST BACKPRESSURE. Setting this bit will cause the MAC to assert backpressure on the link. Backpressure causes preamble to be transmitted, raising carrier sense. A transmit packet from the system will be sent during backpressure.
-            TESTBP: u1,
-            ///  Unused
-            RESERVED: u29,
-        }),
-        ///  MII Mgmt Configuration register.
-        MCFG: mmio.Mmio(packed struct(u32) {
-            ///  SCAN INCREMENT. Set this bit to cause the MII Management hardware to perform read cycles across a range of PHYs. When set, the MII Management hardware will perform read cycles from address 1 through the value set in PHY ADDRESS[4:0]. Clear this bit to allow continuous reads of the same PHY.
-            SCANINC: u1,
-            ///  SUPPRESS PREAMBLE. Set this bit to cause the MII Management hardware to perform read/write cycles without the 32-bit preamble field. Clear this bit to cause normal cycles to be performed. Some PHYs support suppressed preamble.
-            SUPPPREAMBLE: u1,
-            ///  CLOCK SELECT. This field is used by the clock divide logic in creating the MII Management Clock (MDC) which IEEE 802.3u defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz, however. The AHB bus clock (HCLK) is divided by the specified amount. Refer to Table 160 below for the definition of values for this field.
-            CLOCKSEL: u4,
-            ///  Unused
-            RESERVED: u9,
-            ///  RESET MII MGMT. This bit resets the MII Management hardware.
-            RESETMIIMGMT: u1,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        ///  MII Mgmt Command register.
-        MCMD: mmio.Mmio(packed struct(u32) {
-            ///  This bit causes the MII Management hardware to perform a single Read cycle. The Read data is returned in Register MRDD (MII Mgmt Read Data).
-            READ: u1,
-            ///  This bit causes the MII Management hardware to perform Read cycles continuously. This is useful for monitoring Link Fail for example.
-            SCAN: u1,
-            ///  Unused
-            RESERVED: u30,
-        }),
-        ///  MII Mgmt Address register.
-        MADR: mmio.Mmio(packed struct(u32) {
-            ///  REGISTER ADDRESS. This field represents the 5-bit Register Address field of Mgmt cycles. Up to 32 registers can be accessed.
-            REGADDR: u5,
-            ///  Unused
-            RESERVED: u3,
-            ///  PHY ADDRESS. This field represents the 5-bit PHY Address field of Mgmt cycles. Up to 31 PHYs can be addressed (0 is reserved).
-            PHYADDR: u5,
-            ///  Unused
-            RESERVED: u19,
-        }),
-        ///  MII Mgmt Write Data register.
-        MWTD: mmio.Mmio(packed struct(u32) {
-            ///  WRITE DATA. When written, an MII Mgmt write cycle is performed using the 16-bit data and the pre-configured PHY and Register addresses from the MII Mgmt Address register (MADR).
-            WRITEDATA: u16,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        ///  MII Mgmt Read Data register.
-        MRDD: mmio.Mmio(packed struct(u32) {
-            ///  READ DATA. Following an MII Mgmt Read Cycle, the 16-bit data can be read from this location.
-            READDATA: u16,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        ///  MII Mgmt Indicators register.
-        MIND: mmio.Mmio(packed struct(u32) {
-            ///  When 1 is returned - indicates MII Mgmt is currently performing an MII Mgmt Read or Write cycle.
-            BUSY: u1,
-            ///  When 1 is returned - indicates a scan operation (continuous MII Mgmt Read cycles) is in progress.
-            SCANNING: u1,
-            ///  When 1 is returned - indicates MII Mgmt Read cycle has not completed and the Read Data is not yet valid.
-            NOTVALID: u1,
-            ///  When 1 is returned - indicates that an MII Mgmt link fail has occurred.
-            MIILINKFAIL: u1,
-            ///  Unused
-            RESERVED: u28,
-        }),
-        reserved64: [8]u8,
-        ///  Station Address 0 register.
-        SA0: mmio.Mmio(packed struct(u32) {
-            ///  STATION ADDRESS, 2nd octet. This field holds the second octet of the station address.
-            SADDR2: u8,
-            ///  STATION ADDRESS, 1st octet. This field holds the first octet of the station address.
-            SADDR1: u8,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        ///  Station Address 1 register.
-        SA1: mmio.Mmio(packed struct(u32) {
-            ///  STATION ADDRESS, 4th octet. This field holds the fourth octet of the station address.
-            SADDR4: u8,
-            ///  STATION ADDRESS, 3rd octet. This field holds the third octet of the station address.
-            SADDR3: u8,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        ///  Station Address 2 register.
-        SA2: mmio.Mmio(packed struct(u32) {
-            ///  STATION ADDRESS, 6th octet. This field holds the sixth octet of the station address.
-            SADDR6: u8,
-            ///  STATION ADDRESS, 5th octet. This field holds the fifth octet of the station address.
-            SADDR5: u8,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        reserved256: [180]u8,
-        ///  Command register.
-        COMMAND: mmio.Mmio(packed struct(u32) {
-            ///  Enable receive.
-            RXENABLE: u1,
-            ///  Enable transmit.
-            TXENABLE: u1,
-            ///  Unused
-            RESERVED: u1,
-            ///  When a 1 is written, all datapaths and the host registers are reset. The MAC needs to be reset separately.
-            REGRESET: u1,
-            ///  When a 1 is written, the transmit datapath is reset.
-            TXRESET: u1,
-            ///  When a 1 is written, the receive datapath is reset.
-            RXRESET: u1,
-            ///  When set to 1 , passes runt frames s1maller than 64 bytes to memory unless they have a CRC error. If 0 runt frames are filtered out.
-            PASSRUNTFRAME: u1,
-            ///  When set to 1 , disables receive filtering i.e. all frames received are written to memory.
-            PASSRXFILTER: u1,
-            ///  Enable IEEE 802.3 / clause 31 flow control sending pause frames in full duplex and continuous preamble in half duplex.
-            TXFLOWCONTROL: u1,
-            ///  When set to 1 , RMII mode is selected; if 0, MII mode is selected.
-            RMII: u1,
-            ///  When set to 1 , indicates full duplex operation.
-            FULLDUPLEX: u1,
-            ///  Unused
-            RESERVED: u21,
-        }),
-        ///  Status register.
-        STATUS: mmio.Mmio(packed struct(u32) {
-            ///  If 1, the receive channel is active. If 0, the receive channel is inactive.
-            RXSTATUS: u1,
-            ///  If 1, the transmit channel is active. If 0, the transmit channel is inactive.
-            TXSTATUS: u1,
-            ///  Unused
-            RESERVED: u30,
-        }),
-        ///  Receive descriptor base address register.
-        RXDESCRIPTOR: mmio.Mmio(packed struct(u32) {
-            ///  Fixed to 00
-            RESERVED: u2,
-            ///  MSBs of receive descriptor base address.
-            RXDESCRIPTOR: u30,
-        }),
-        ///  Receive status base address register.
-        RXSTATUS: mmio.Mmio(packed struct(u32) {
-            ///  Fixed to 000
-            RESERVED: u3,
-            ///  MSBs of receive status base address.
-            RXSTATUS: u29,
-        }),
-        ///  Receive number of descriptors register.
-        RXDESCRIPTORNUMBER: mmio.Mmio(packed struct(u32) {
-            ///  RxDescriptorNumber. Number of descriptors in the descriptor array for which RxDescriptor is the base address. The number of descriptors is minus one encoded.
-            RXDESCRIPTORN: u16,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        ///  Receive produce index register.
-        RXPRODUCEINDEX: mmio.Mmio(packed struct(u32) {
-            ///  Index of the descriptor that is going to be filled next by the receive datapath.
-            RXPRODUCEIX: u16,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        ///  Receive consume index register.
-        RXCONSUMEINDEX: mmio.Mmio(packed struct(u32) {
-            ///  Index of the descriptor that is going to be processed next by the receive
-            RXCONSUMEIX: u16,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        ///  Transmit descriptor base address register.
-        TXDESCRIPTOR: mmio.Mmio(packed struct(u32) {
-            ///  Fixed to 00
-            RESERVED: u2,
-            ///  TxDescriptor. MSBs of transmit descriptor base address.
-            TXD: u30,
-        }),
-        ///  Transmit status base address register.
-        TXSTATUS: mmio.Mmio(packed struct(u32) {
-            ///  Fixed to 00
-            RESERVED: u2,
-            ///  TxStatus. MSBs of transmit status base address.
-            TXSTAT: u30,
-        }),
-        ///  Transmit number of descriptors register.
-        TXDESCRIPTORNUMBER: mmio.Mmio(packed struct(u32) {
-            ///  TxDescriptorNumber. Number of descriptors in the descriptor array for which TxDescriptor is the base address. The register is minus one encoded.
-            TXDN: u16,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        ///  Transmit produce index register.
-        TXPRODUCEINDEX: mmio.Mmio(packed struct(u32) {
-            ///  TxProduceIndex. Index of the descriptor that is going to be filled next by the transmit software driver.
-            TXPI: u16,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        ///  Transmit consume index register.
-        TXCONSUMEINDEX: mmio.Mmio(packed struct(u32) {
-            ///  TxConsumeIndex. Index of the descriptor that is going to be transmitted next by the transmit datapath.
-            TXCI: u16,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        reserved344: [40]u8,
-        ///  Transmit status vector 0 register.
-        TSV0: mmio.Mmio(packed struct(u32) {
-            ///  CRC error. The attached CRC in the packet did not match the internally generated CRC.
-            CRCERR: u1,
-            ///  Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field.
-            LCE: u1,
-            ///  Length out of range. Indicates that frame type/length field was larger than 1500 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.
-            LOR: u1,
-            ///  Transmission of packet was completed.
-            DONE: u1,
-            ///  Packet's destination was a multicast address.
-            MULTICAST: u1,
-            ///  Packet's destination was a broadcast address.
-            BROADCAST: u1,
-            ///  Packet was deferred for at least one attempt, but less than an excessive defer.
-            PACKETDEFER: u1,
-            ///  Excessive Defer. Packet was deferred in excess of 6071 nibble times in 100 Mbps or 24287 bit times in 10 Mbps mode.
-            EXDF: u1,
-            ///  Excessive Collision. Packet was aborted due to exceeding of maximum allowed number of collisions.
-            EXCOL: u1,
-            ///  Late Collision. Collision occurred beyond collision window, 512 bit times.
-            LCOL: u1,
-            ///  Byte count in frame was greater than can be represented in the transmit byte count field in TSV1.
-            GIANT: u1,
-            ///  Host side caused buffer underrun.
-            UNDERRUN: u1,
-            ///  The total number of bytes transferred including collided attempts.
-            TOTALBYTES: u16,
-            ///  The frame was a control frame.
-            CONTROLFRAME: u1,
-            ///  The frame was a control frame with a valid PAUSE opcode.
-            PAUSE: u1,
-            ///  Carrier-sense method backpressure was previously applied.
-            BACKPRESSURE: u1,
-            ///  Frame's length/type field contained 0x8100 which is the VLAN protocol identifier.
-            VLAN: u1,
-        }),
-        ///  Transmit status vector 1 register.
-        TSV1: mmio.Mmio(packed struct(u32) {
-            ///  Transmit byte count. The total number of bytes in the frame, not counting the collided bytes.
-            TBC: u16,
-            ///  Transmit collision count. Number of collisions the current packet incurred during transmission attempts. The maximum number of collisions (16) cannot be represented.
-            TCC: u4,
-            ///  Unused
-            RESERVED: u12,
-        }),
-        ///  Receive status vector register.
-        RSV: mmio.Mmio(packed struct(u32) {
-            ///  Received byte count. Indicates length of received frame.
-            RBC: u16,
-            ///  Packet previously ignored. Indicates that a packet was dropped.
-            PPI: u1,
-            ///  RXDV event previously seen. Indicates that the last receive event seen was not long enough to be a valid packet.
-            RXDVSEEN: u1,
-            ///  Carrier event previously seen. Indicates that at some time since the last receive statistics, a carrier event was detected.
-            CESEEN: u1,
-            ///  Receive code violation. Indicates that received PHY data does not represent a valid receive code.
-            RCV: u1,
-            ///  CRC error. The attached CRC in the packet did not match the internally generated CRC.
-            CRCERR: u1,
-            ///  Length check error. Indicates the frame length field does not match the actual number of data items and is not a type field.
-            LCERR: u1,
-            ///  Length out of range. Indicates that frame type/length field was larger than 1518 bytes. The EMAC doesn't distinguish the frame type and frame length, so, e.g. when the IP(0x8000) or ARP(0x0806) packets are received, it compares the frame type with the max length and gives the "Length out of range" error. In fact, this bit is not an error indication, but simply a statement by the chip regarding the status of the received frame.
-            LOR: u1,
-            ///  Receive OK. The packet had valid CRC and no symbol errors.
-            ROK: u1,
-            ///  The packet destination was a multicast address.
-            MULTICAST: u1,
-            ///  The packet destination was a broadcast address.
-            BROADCAST: u1,
-            ///  Indicates that after the end of packet another 1-7 bits were received. A single nibble, called dribble nibble, is formed but not sent out.
-            DRIBBLENIBBLE: u1,
-            ///  The frame was a control frame.
-            CONTROLFRAME: u1,
-            ///  The frame was a control frame with a valid PAUSE opcode.
-            PAUSE: u1,
-            ///  Unsupported Opcode. The current frame was recognized as a Control Frame but contains an unknown opcode.
-            UO: u1,
-            ///  Frame's length/type field contained 0x8100 which is the VLAN protocol identifier.
-            VLAN: u1,
-            ///  Unused
-            RESERVED: u1,
-        }),
-        reserved368: [12]u8,
-        ///  Flow control counter register.
-        FLOWCONTROLCOUNTER: mmio.Mmio(packed struct(u32) {
-            ///  MirrorCounter. In full duplex mode the MirrorCounter specifies the number of cycles before re-issuing the Pause control frame.
-            MC: u16,
-            ///  PauseTimer. In full-duplex mode the PauseTimer specifies the value that is inserted into the pause timer field of a pause flow control frame. In half duplex mode the PauseTimer specifies the number of backpressure cycles.
-            PT: u16,
-        }),
-        ///  Flow control status register.
-        FLOWCONTROLSTATUS: mmio.Mmio(packed struct(u32) {
-            ///  MirrorCounterCurrent. In full duplex mode this register represents the current value of the datapath's mirror counter which counts up to the value specified by the MirrorCounter field in the FlowControlCounter register. In half duplex mode the register counts until it reaches the value of the PauseTimer bits in the FlowControlCounter register.
-            MCC: u16,
-            ///  Unused
-            RESERVED: u16,
-        }),
-        reserved512: [136]u8,
-        ///  Receive filter control register.
-        RXFILTERCTRL: mmio.Mmio(packed struct(u32) {
-            ///  AcceptUnicastEn. When set to 1, all unicast frames are accepted.
-            AUE: u1,
-            ///  AcceptBroadcastEn. When set to 1, all broadcast frames are accepted.
-            ABE: u1,
-            ///  AcceptMulticastEn. When set to 1, all multicast frames are accepted.
-            AME: u1,
-            ///  AcceptUnicastHashEn. When set to 1, unicast frames that pass the imperfect hash filter are accepted.
-            AUHE: u1,
-            ///  AcceptMulticastHashEn. When set to 1, multicast frames that pass the imperfect hash filter are accepted.
-            AMHE: u1,
-            ///  AcceptPerfectEn. When set to 1, the frames with a destination address identical to the station address are accepted.
-            APE: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u6,
-            ///  MagicPacketEnWoL. When set to 1, the result of the magic packet filter will generate a WoL interrupt when there is a match.
-            MPEW: u1,
-            ///  RxFilterEnWoL. When set to 1, the result of the perfect address matching filter and the imperfect hash filter will generate a WoL interrupt when there is a match.
-            RFEW: u1,
-            ///  Unused
-            RESERVED: u18,
-        }),
-        ///  Receive filter WoL status register.
-        RXFILTERWOLSTATUS: mmio.Mmio(packed struct(u32) {
-            ///  AcceptUnicastWoL. When the value is 1, a unicast frames caused WoL.
-            AUW: u1,
-            ///  AcceptBroadcastWoL. When the value is 1, a broadcast frame caused WoL.
-            ABW: u1,
-            ///  AcceptMulticastWoL. When the value is 1, a multicast frame caused WoL.
-            AMW: u1,
-            ///  AcceptUnicastHashWoL. When the value is 1, a unicast frame that passes the imperfect hash filter caused WoL.
-            AUHW: u1,
-            ///  AcceptMulticastHashWoL. When the value is 1, a multicast frame that passes the imperfect hash filter caused WoL.
-            AMHW: u1,
-            ///  AcceptPerfectWoL. When the value is 1, the perfect address matching filter caused WoL.
-            APW: u1,
-            ///  Unused
-            RESERVED: u1,
-            ///  RxFilterWoL. When the value is 1, the receive filter caused WoL.
-            RFW: u1,
-            ///  MagicPacketWoL. When the value is 1, the magic packet filter caused WoL.
-            MPW: u1,
-            ///  Unused
-            RESERVED: u23,
-        }),
-        ///  Receive filter WoL clear register.
-        RXFILTERWOLCLEAR: mmio.Mmio(packed struct(u32) {
-            ///  AcceptUnicastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
-            AUWCLR: u1,
-            ///  AcceptBroadcastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
-            ABWCLR: u1,
-            ///  AcceptMulticastWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
-            AMWCLR: u1,
-            ///  AcceptUnicastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
-            AUHWCLR: u1,
-            ///  AcceptMulticastHashWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
-            AMHWCLR: u1,
-            ///  AcceptPerfectWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
-            APWCLR: u1,
-            ///  Unused
-            RESERVED: u1,
-            ///  RxFilterWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
-            RFWCLR: u1,
-            ///  MagicPacketWoLClr. When a 1 is written, the corresponding status bit in the RxFilterWoLStatus register is cleared.
-            MPWCLR: u1,
-            ///  Unused
-            RESERVED: u23,
-        }),
-        reserved528: [4]u8,
-        ///  Hash filter table LSBs register.
-        HASHFILTERL: mmio.Mmio(packed struct(u32) {
-            ///  HashFilterL. Bits 31:0 of the imperfect filter hash table for receive filtering.
-            HFL: u32,
-        }),
-        ///  Hash filter table MSBs register.
-        HASHFILTERH: mmio.Mmio(packed struct(u32) {
-            ///  Bits 63:32 of the imperfect filter hash table for receive filtering.
-            HFH: u32,
-        }),
-        reserved4064: [3528]u8,
-        ///  Interrupt status register.
-        INTSTATUS: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt set on a fatal overrun error in the receive queue. The fatal interrupt should be resolved by a Rx soft-reset. The bit is not set when there is a nonfatal overrun error.
-            RXOVERRUNINT: u1,
-            ///  Interrupt trigger on receive errors: AlignmentError, RangeError, LengthError, SymbolError, CRCError or NoDescriptor or Overrun.
-            RXERRORINT: u1,
-            ///  Interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.
-            RXFINISHEDINT: u1,
-            ///  Interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set.
-            RXDONEINT: u1,
-            ///  Interrupt set on a fatal underrun error in the transmit queue. The fatal interrupt should be resolved by a Tx soft-reset. The bit is not set when there is a nonfatal underrun error.
-            TXUNDERRUNINT: u1,
-            ///  Interrupt trigger on transmit errors: LateCollision, ExcessiveCollision and ExcessiveDefer, NoDescriptor or Underrun.
-            TXERRORINT: u1,
-            ///  Interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.
-            TXFINISHEDINT: u1,
-            ///  Interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set.
-            TXDONEINT: u1,
-            ///  Unused
-            RESERVED: u4,
-            ///  Interrupt triggered by software writing a 1 to the SoftIntSet bit in the IntSet register.
-            SOFTINT: u1,
-            ///  Interrupt triggered by a Wake-up event detected by the receive filter.
-            WAKEUPINT: u1,
-            ///  Unused
-            RESERVED: u18,
-        }),
-        ///  Interrupt enable register.
-        INTENABLE: mmio.Mmio(packed struct(u32) {
-            ///  Enable for interrupt trigger on receive buffer overrun or descriptor underrun situations.
-            RXOVERRUNINTEN: u1,
-            ///  Enable for interrupt trigger on receive errors.
-            RXERRORINTEN: u1,
-            ///  Enable for interrupt triggered when all receive descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.
-            RXFINISHEDINTEN: u1,
-            ///  Enable for interrupt triggered when a receive descriptor has been processed while the Interrupt bit in the Control field of the descriptor was set.
-            RXDONEINTEN: u1,
-            ///  Enable for interrupt trigger on transmit buffer or descriptor underrun situations.
-            TXUNDERRUNINTEN: u1,
-            ///  Enable for interrupt trigger on transmit errors.
-            TXERRORINTEN: u1,
-            ///  Enable for interrupt triggered when all transmit descriptors have been processed i.e. on the transition to the situation where ProduceIndex == ConsumeIndex.
-            TXFINISHEDINTEN: u1,
-            ///  Enable for interrupt triggered when a descriptor has been transmitted while the Interrupt bit in the Control field of the descriptor was set.
-            TXDONEINTEN: u1,
-            ///  Unused
-            RESERVED: u4,
-            ///  Enable for interrupt triggered by the SoftInt bit in the IntStatus register, caused by software writing a 1 to the SoftIntSet bit in the IntSet register.
-            SOFTINTEN: u1,
-            ///  Enable for interrupt triggered by a Wake-up event detected by the receive filter.
-            WAKEUPINTEN: u1,
-            ///  Unused
-            RESERVED: u18,
-        }),
-        ///  Interrupt clear register.
-        INTCLEAR: mmio.Mmio(packed struct(u32) {
-            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
-            RXOVERRUNINTCLR: u1,
-            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
-            RXERRORINTCLR: u1,
-            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
-            RXFINISHEDINTCLR: u1,
-            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
-            RXDONEINTCLR: u1,
-            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
-            TXUNDERRUNINTCLR: u1,
-            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
-            TXERRORINTCLR: u1,
-            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
-            TXFINISHEDINTCLR: u1,
-            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
-            TXDONEINTCLR: u1,
-            ///  Unused
-            RESERVED: u4,
-            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
-            SOFTINTCLR: u1,
-            ///  Writing a 1 clears the corresponding status bit in interrupt status register IntStatus.
-            WAKEUPINTCLR: u1,
-            ///  Unused
-            RESERVED: u18,
-        }),
-        ///  Interrupt set register.
-        INTSET: mmio.Mmio(packed struct(u32) {
-            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
-            RXOVERRUNINTSET: u1,
-            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
-            RXERRORINTSET: u1,
-            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
-            RXFINISHEDINTSET: u1,
-            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
-            RXDONEINTSET: u1,
-            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
-            TXUNDERRUNINTSET: u1,
-            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
-            TXERRORINTSET: u1,
-            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
-            TXFINISHEDINTSET: u1,
-            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
-            TXDONEINTSET: u1,
-            ///  Unused
-            RESERVED: u4,
-            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
-            SOFTINTSET: u1,
-            ///  Writing a 1 to one sets the corresponding status bit in interrupt status register IntStatus.
-            WAKEUPINTSET: u1,
-            ///  Unused
-            RESERVED: u18,
-        }),
-        reserved4084: [4]u8,
-        ///  Power-down register.
-        POWERDOWN: mmio.Mmio(packed struct(u32) {
-            ///  Unused
-            RESERVED: u31,
-            ///  PowerDownMACAHB. If true, all AHB accesses will return a read/write error, except accesses to the Power-Down register.
-            PD: u1,
-        }),
-    };
-
-    ///  Digital-to-Analog Converter (DAC)
-    pub const DAC = extern struct {
-        ///  D/A Converter Register. This register contains the digital value to be converted to analog and a power control bit.
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u6,
-            ///  After the selected settling time after this field is written with a new VALUE, the voltage on the DAC_OUT pin (with respect to VSSA) is VALUE x ((VREFP - V REFN)/1024) + VREFN.
-            VALUE: u10,
-            ///  Settling time The settling times noted in the description of the BIAS bit are valid for a capacitance load on the DAC_OUT pin not exceeding 100 pF. A load impedance value greater than that value will cause settling time longer than the specified time. One or more graphs of load impedance vs. settling time will be included in the final data sheet.
-            BIAS: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The settling time of the DAC is 1 us max, and the maximum current is 700 uA. This allows a maximum update rate of 1 MHz.
-                    FAST = 0x0,
-                    ///  The settling time of the DAC is 2.5 us and the maximum current is 350 uA. This allows a maximum update rate of 400 kHz.
-                    SLOW = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u15,
-        }),
-        ///  DAC Control register. This register controls DMA and timer operation.
-        CTRL: mmio.Mmio(packed struct(u32) {
-            ///  DMA interrupt request
-            INT_DMA_REQ: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Clear on any write to the DACR register.
-                    CLEAR_ON_ANY_WRITE_T = 0x0,
-                    ///  Set by hardware when the timer times out.
-                    SET_BY_HARDWARE_WHEN = 0x1,
-                },
-            },
-            ///  Double buffering
-            DBLBUF_ENA: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable
-                    DISABLE = 0x0,
-                    ///  Enable. When this bit and the CNT_ENA bit are both set, the double-buffering feature in the DACR register will be enabled. Writes to the DACR register are written to a pre-buffer and then transferred to the DACR on the next time-out of the counter.
-                    ENABLE_WHEN_THIS_BI = 0x1,
-                },
-            },
-            ///  Time-out counter operation
-            CNT_ENA: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable
-                    DISABLE = 0x0,
-                    ///  Enable
-                    ENABLE = 0x1,
-                },
-            },
-            ///  DMA access
-            DMA_ENA: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disable
-                    DISABLE = 0x0,
-                    ///  Enable. DMA Burst Request Input 7 is enabled for the DAC (see Table 672).
-                    ENABLE_DMA_BURST_RE = 0x1,
-                },
-            },
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u28,
-        }),
-        ///  DAC Counter Value register. This register contains the reload value for the DAC DMA/Interrupt timer.
-        CNTVAL: mmio.Mmio(packed struct(u32) {
-            ///  16-bit reload value for the DAC interrupt/DMA timer.
-            VALUE: u16,
-            ///  Reserved
-            RESERVED: u16,
-        }),
-    };
-
-    ///  System and clock control
-    pub const SYSCON = extern struct {
-        ///  Flash Accelerator Configuration Register. Controls flash access timing.
-        FLASHCFG: mmio.Mmio(packed struct(u32) {
-            ///  Reserved, user software should not change these bits from the reset value.
-            RESERVED: u12,
-            ///  Flash access time. The value of this field plus 1 gives the number of CPU clocks used for a flash access. Warning: improper setting of this value may result in incorrect operation of the device. Other values are reserved.
-            FLASHTIM: packed union {
-                raw: u4,
-                value: enum(u4) {
-                    ///  Flash accesses use 1 CPU clock. Use for up to 20 MHz CPU clock.
-                    @"1CLK" = 0x0,
-                    ///  Flash accesses use 2 CPU clocks. Use for up to 40 MHz CPU clock.
-                    @"2CLK" = 0x1,
-                    ///  Flash accesses use 3 CPU clocks. Use for up to 60 MHz CPU clock.
-                    @"3CLK" = 0x2,
-                    ///  Flash accesses use 4 CPU clocks. Use for up to 80 MHz CPU clock.
-                    @"4CLK" = 0x3,
-                    ///  Flash accesses use 5 CPU clocks. Use for up to 100 MHz CPU clock. Use for up to 120 Mhz for LPC1759 and LPC1769 only.
-                    @"5CLK" = 0x4,
-                    ///  Flash accesses use 6 CPU clocks. This safe setting will work under any conditions.
-                    @"6CLK" = 0x5,
-                    _,
-                },
-            },
-            ///  Reserved. The value read from a reserved bit is not defined.
-            RESERVED: u16,
-        }),
-        reserved128: [124]u8,
-        ///  PLL0 Control Register
-        PLL0CON: mmio.Mmio(packed struct(u32) {
-            ///  PLL0 Enable. When one, and after a valid PLL0 feed, this bit will activate PLL0 and allow it to lock to the requested frequency. See PLL0STAT register.
-            PLLE0: u1,
-            ///  PLL0 Connect. Setting PLLC0 to one after PLL0 has been enabled and locked, then followed by a valid PLL0 feed sequence causes PLL0 to become the clock source for the CPU, AHB peripherals, and used to derive the clocks for APB peripherals. The PLL0 output may potentially be used to clock the USB subsystem if the frequency is 48 MHz. See PLL0STAT register.
-            PLLC0: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u30,
-        }),
-        ///  PLL0 Configuration Register
-        PLL0CFG: mmio.Mmio(packed struct(u32) {
-            ///  PLL0 Multiplier value. Supplies the value M in PLL0 frequency calculations. The value stored here is M - 1. Note: Not all values of M are needed, and therefore some are not supported by hardware.
-            MSEL0: u15,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u1,
-            ///  PLL0 Pre-Divider value. Supplies the value N in PLL0 frequency calculations. The value stored here is N - 1. Supported values for N are 1 through 32.
-            NSEL0: u8,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u8,
-        }),
-        ///  PLL0 Status Register
-        PLL0STAT: mmio.Mmio(packed struct(u32) {
-            ///  Read-back for the PLL0 Multiplier value. This is the value currently used by PLL0, and is one less than the actual multiplier.
-            MSEL0: u15,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u1,
-            ///  Read-back for the PLL0 Pre-Divider value. This is the value currently used by PLL0, and is one less than the actual divider.
-            NSEL0: u8,
-            ///  Read-back for the PLL0 Enable bit. This bit reflects the state of the PLEC0 bit in PLL0CON after a valid PLL0 feed. When one, PLL0 is currently enabled. When zero, PLL0 is turned off. This bit is automatically cleared when Power-down mode is entered.
-            PLLE0_STAT: u1,
-            ///  Read-back for the PLL0 Connect bit. This bit reflects the state of the PLLC0 bit in PLL0CON after a valid PLL0 feed. When PLLC0 and PLLE0 are both one, PLL0 is connected as the clock source for the CPU. When either PLLC0 or PLLE0 is zero, PLL0 is bypassed. This bit is automatically cleared when Power-down mode is entered.
-            PLLC0_STAT: u1,
-            ///  Reflects the PLL0 Lock status. When zero, PLL0 is not locked. When one, PLL0 is locked onto the requested frequency. See text for details.
-            PLOCK0: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u5,
-        }),
-        ///  PLL0 Feed Register
-        PLL0FEED: mmio.Mmio(packed struct(u32) {
-            ///  The PLL0 feed sequence must be written to this register in order for PLL0 configuration and control register changes to take effect.
-            PLL0FEED: u8,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        reserved160: [16]u8,
-        ///  PLL1 Control Register
-        PLL1CON: mmio.Mmio(packed struct(u32) {
-            ///  PLL1 Enable. When one, and after a valid PLL1 feed, this bit will activate PLL1 and allow it to lock to the requested frequency.
-            PLLE1: u1,
-            ///  PLL1 Connect. Setting PLLC to one after PLL1 has been enabled and locked, then followed by a valid PLL1 feed sequence causes PLL1 to become the clock source for the USB subsystem via the USB clock divider. See PLL1STAT register.
-            PLLC1: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u30,
-        }),
-        ///  PLL1 Configuration Register
-        PLL1CFG: mmio.Mmio(packed struct(u32) {
-            ///  PLL1 Multiplier value. Supplies the value M in the PLL1 frequency calculations.
-            MSEL1: u5,
-            ///  PLL1 Divider value. Supplies the value P in the PLL1 frequency calculations.
-            PSEL1: u2,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u25,
-        }),
-        ///  PLL1 Status Register
-        PLL1STAT: mmio.Mmio(packed struct(u32) {
-            ///  Read-back for the PLL1 Multiplier value. This is the value currently used by PLL1.
-            MSEL1: u5,
-            ///  Read-back for the PLL1 Divider value. This is the value currently used by PLL1.
-            PSEL1: u2,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u1,
-            ///  Read-back for the PLL1 Enable bit. When one, PLL1 is currently activated. When zero, PLL1 is turned off. This bit is automatically cleared when Power-down mode is activated.
-            PLLE1_STAT: u1,
-            ///  Read-back for the PLL1 Connect bit. When PLLC and PLLE are both one, PLL1 is connected as the clock source for the microcontroller. When either PLLC or PLLE is zero, PLL1 is bypassed and the oscillator clock is used directly by the microcontroller. This bit is automatically cleared when Power-down mode is activated.
-            PLLC1_STAT: u1,
-            ///  Reflects the PLL1 Lock status. When zero, PLL1 is not locked. When one, PLL1 is locked onto the requested frequency.
-            PLOCK1: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u21,
-        }),
-        ///  PLL1 Feed Register
-        PLL1FEED: mmio.Mmio(packed struct(u32) {
-            ///  The PLL1 feed sequence must be written to this register in order for PLL1 configuration and control register changes to take effect.
-            PLL1FEED: u8,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        reserved192: [16]u8,
-        ///  Power Control Register
-        PCON: mmio.Mmio(packed struct(u32) {
-            ///  Power mode control bit 0. This bit controls entry to the Power-down mode.
-            PM0: u1,
-            ///  Power mode control bit 1. This bit controls entry to the Deep Power-down mode.
-            PM1: u1,
-            ///  Brown-Out Reduced Power Mode. When BODRPM is 1, the Brown-Out Detect circuitry will be turned off when chip Power-down mode or Deep Sleep mode is entered, resulting in a further reduction in power usage. However, the possibility of using Brown-Out Detect as a wake-up source from the reduced power mode will be lost. When 0, the Brown-Out Detect function remains active during Power-down and Deep Sleep modes. See the System Control Block chapter for details of Brown-Out detection.
-            BODRPM: u1,
-            ///  Brown-Out Global Disable. When BOGD is 1, the Brown-Out Detect circuitry is fully disabled at all times, and does not consume power. When 0, the Brown-Out Detect circuitry is enabled. See the System Control Block chapter for details of Brown-Out detection. Note: the Brown-Out Reset Disable (BORD, in this register) and the Brown-Out Interrupt (xx) must be disabled when software changes the value of this bit.
-            BOGD: u1,
-            ///  Brown-Out Reset Disable. When BORD is 1, the BOD will not reset the device when the VDD(REG)(3V3) voltage dips goes below the BOD reset trip level. The Brown-Out interrupt is not affected. When BORD is 0, the BOD reset is enabled.
-            BORD: u1,
-            reserved8: u3,
-            ///  Sleep Mode entry flag. Set when the Sleep mode is successfully entered. Cleared by software writing a one to this bit.
-            SMFLAG: u1,
-            ///  Deep Sleep entry flag. Set when the Deep Sleep mode is successfully entered. Cleared by software writing a one to this bit.
-            DSFLAG: u1,
-            ///  Power-down entry flag. Set when the Power-down mode is successfully entered. Cleared by software writing a one to this bit.
-            PDFLAG: u1,
-            ///  Deep Power-down entry flag. Set when the Deep Power-down mode is successfully entered. Cleared by software writing a one to this bit.
-            DPDFLAG: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u20,
-        }),
-        ///  Power Control for Peripherals Register
-        PCONP: mmio.Mmio(packed struct(u32) {
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Timer/Counter 0 power/clock control bit.
-            PCTIM0: u1,
-            ///  Timer/Counter 1 power/clock control bit.
-            PCTIM1: u1,
-            ///  UART0 power/clock control bit.
-            PCUART0: u1,
-            ///  UART1 power/clock control bit.
-            PCUART1: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            ///  PWM1 power/clock control bit.
-            PCPWM1: u1,
-            ///  The I2C0 interface power/clock control bit.
-            PCI2C0: u1,
-            ///  The SPI interface power/clock control bit.
-            PCSPI: u1,
-            ///  The RTC power/clock control bit.
-            PCRTC: u1,
-            ///  The SSP 1 interface power/clock control bit.
-            PCSSP1: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            ///  A/D converter (ADC) power/clock control bit. Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit before setting PDN.
-            PCADC: u1,
-            ///  CAN Controller 1 power/clock control bit.
-            PCCAN1: u1,
-            ///  CAN Controller 2 power/clock control bit.
-            PCCAN2: u1,
-            ///  Power/clock control bit for IOCON, GPIO, and GPIO interrupts.
-            PCGPIO: u1,
-            ///  Repetitive Interrupt Timer power/clock control bit.
-            PCRIT: u1,
-            ///  Motor Control PWM
-            PCMCPWM: u1,
-            ///  Quadrature Encoder Interface power/clock control bit.
-            PCQEI: u1,
-            ///  The I2C1 interface power/clock control bit.
-            PCI2C1: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            ///  The SSP0 interface power/clock control bit.
-            PCSSP0: u1,
-            ///  Timer 2 power/clock control bit.
-            PCTIM2: u1,
-            ///  Timer 3 power/clock control bit.
-            PCTIM3: u1,
-            ///  UART 2 power/clock control bit.
-            PCUART2: u1,
-            ///  UART 3 power/clock control bit.
-            PCUART3: u1,
-            ///  I2C interface 2 power/clock control bit.
-            PCI2C2: u1,
-            ///  I2S interface power/clock control bit.
-            PCI2S: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            ///  GPDMA function power/clock control bit.
-            PCGPDMA: u1,
-            ///  Ethernet block power/clock control bit.
-            PCENET: u1,
-            ///  USB interface power/clock control bit.
-            PCUSB: u1,
-        }),
-        reserved260: [60]u8,
-        ///  CPU Clock Configuration Register
-        CCLKCFG: mmio.Mmio(packed struct(u32) {
-            ///  Selects the divide value for creating the CPU clock (CCLK) from the PLL0 output. 0 = pllclk is divided by 1 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 1 = pllclk is divided by 2 to produce the CPU clock. This setting is not allowed when the PLL0 is connected, because the rate would always be greater than the maximum allowed CPU clock. 2 = pllclk is divided by 3 to produce the CPU clock. 3 = pllclk is divided by 4 to produce the CPU clock. ... 255 = pllclk is divided by 256 to produce the CPU clock.
-            CCLKSEL: u8,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u24,
-        }),
-        ///  USB Clock Configuration Register
-        USBCLKCFG: mmio.Mmio(packed struct(u32) {
-            ///  Selects the divide value for creating the USB clock from the PLL0 output. Only the values shown below can produce even number multiples of 48 MHz from the PLL0 output. Warning: Improper setting of this value will result in incorrect operation of the USB interface. 5 = PLL0 output is divided by 6. PLL0 output must be 288 MHz. 7 = PLL0 output is divided by 8. PLL0 output must be 384 MHz. 9 = PLL0 output is divided by 10. PLL0 output must be 480 MHz.
-            USBSEL: u4,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        ///  Clock Source Select Register
-        CLKSRCSEL: mmio.Mmio(packed struct(u32) {
-            ///  Selects the clock source for PLL0 as follows. Warning: Improper setting of this value, or an incorrect sequence of changing this value may result in incorrect operation of the device.
-            CLKSRC: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Selects the Internal RC oscillator as the PLL0 clock source (default).
-                    SELECTS_THE_INTERNAL = 0x0,
-                    ///  Selects the main oscillator as the PLL0 clock source. Select the main oscillator as PLL0 clock source if the PLL0 clock output is used for USB or for CAN with baudrates > 100 kBit/s.
-                    SELECTS_THE_MAIN_OSC = 0x1,
-                    ///  Selects the RTC oscillator as the PLL0 clock source.
-                    SELECTS_THE_RTC_OSCI = 0x2,
-                    ///  Reserved, do not use this setting.
-                    RESERVED = 0x3,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u30,
-        }),
-        ///  Allows clearing the current CAN channel sleep state as well as reading that state.
-        CANSLEEPCLR: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  Sleep status and control for CAN channel 1. Read: when 1, indicates that CAN channel 1 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 1.
-            CAN1SLEEP: u1,
-            ///  Sleep status and control for CAN channel 2. Read: when 1, indicates that CAN channel 2 is in the sleep mode. Write: writing a 1 causes clocks to be restored to CAN channel 2.
-            CAN2SLEEP: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u29,
-        }),
-        ///  Allows reading the wake-up state of the CAN channels.
-        CANWAKEFLAGS: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  Wake-up status for CAN channel 1. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 1. Write: writing a 1 clears this bit.
-            CAN1WAKE: u1,
-            ///  Wake-up status for CAN channel 2. Read: when 1, indicates that a falling edge has occurred on the receive data line of CAN channel 2. Write: writing a 1 clears this bit.
-            CAN2WAKE: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u29,
-        }),
-        reserved320: [40]u8,
-        ///  External Interrupt Flag Register
-        EXTINT: mmio.Mmio(packed struct(u32) {
-            ///  In level-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT0 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.
-            EINT0: u1,
-            ///  In level-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT1 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.
-            EINT1: u1,
-            ///  In level-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT2 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.
-            EINT2: u1,
-            ///  In level-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the pin is in its active state. In edge-sensitive mode, this bit is set if the EINT3 function is selected for its pin, and the selected edge occurs on the pin. This bit is cleared by writing a one to it, except in level sensitive mode when the pin is in its active state.
-            EINT3: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        reserved328: [4]u8,
-        ///  External Interrupt Mode register
-        EXTMODE: mmio.Mmio(packed struct(u32) {
-            ///  External interrupt 0 EINT0 mode.
-            EXTMODE0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Level-sensitive. Level-sensitivity is selected for EINT0.
-                    LEVEL_SENSITIVE = 0x0,
-                    ///  Edge-sensitive. EINT0 is edge sensitive.
-                    EDGE_SENSITIVE = 0x1,
-                },
-            },
-            ///  External interrupt 1 EINT1 mode.
-            EXTMODE1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Level-sensitive. Level-sensitivity is selected for EINT1.
-                    LEVEL_SENSITIVE = 0x0,
-                    ///  Edge-sensitive. EINT1 is edge sensitive.
-                    EDGE_SENSITIVE = 0x1,
-                },
-            },
-            ///  External interrupt 2 EINT2 mode.
-            EXTMODE2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Level-sensitive. Level-sensitivity is selected for EINT2.
-                    LEVEL_SENSITIVE = 0x0,
-                    ///  Edge-sensitive. EINT2 is edge sensitive.
-                    EDGE_SENSITIVE = 0x1,
-                },
-            },
-            ///  External interrupt 3 EINT3 mode.
-            EXTMODE3: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Level-sensitive. Level-sensitivity is selected for EINT3.
-                    LEVEL_SENSITIVE = 0x0,
-                    ///  Edge-sensitive. EINT3 is edge sensitive.
-                    EDGE_SENSITIVE = 0x1,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        ///  External Interrupt Polarity Register
-        EXTPOLAR: mmio.Mmio(packed struct(u32) {
-            ///  External interrupt 0 EINT0 polarity.
-            EXTPOLAR0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Falling edge. EINT0 is low-active or falling-edge sensitive (depending on EXTMODE0).
-                    FALLING_EDGE = 0x0,
-                    ///  Rising edge. EINT0 is high-active or rising-edge sensitive (depending on EXTMODE0).
-                    RISING_EDGE = 0x1,
-                },
-            },
-            ///  External interrupt 1 EINT1 polarity.
-            EXTPOLAR1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Falling edge. EINT1 is low-active or falling-edge sensitive (depending on EXTMODE1).
-                    FALLING_EDGE = 0x0,
-                    ///  Rising edge. EINT1 is high-active or rising-edge sensitive (depending on EXTMODE1).
-                    RISING_EDGE = 0x1,
-                },
-            },
-            ///  External interrupt 2 EINT2 polarity.
-            EXTPOLAR2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Falling edge. EINT2 is low-active or falling-edge sensitive (depending on EXTMODE2).
-                    FALLING_EDGE = 0x0,
-                    ///  Rising edge. EINT2 is high-active or rising-edge sensitive (depending on EXTMODE2).
-                    RISING_EDGE = 0x1,
-                },
-            },
-            ///  External interrupt 3 EINT3 polarity.
-            EXTPOLAR3: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Falling edge. EINT3 is low-active or falling-edge sensitive (depending on EXTMODE3).
-                    FALLING_EDGE = 0x0,
-                    ///  Rising edge. EINT3 is high-active or rising-edge sensitive (depending on EXTMODE3).
-                    RISING_EDGE = 0x1,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        reserved384: [48]u8,
-        ///  Reset Source Identification Register
-        RSID: mmio.Mmio(packed struct(u32) {
-            ///  Assertion of the POR signal sets this bit, and clears all of the other bits in this register. But if another Reset signal (e.g., External Reset) remains asserted after the POR signal is negated, then its bit is set. This bit is not affected by any of the other sources of Reset.
-            POR: u1,
-            ///  Assertion of the RESET signal sets this bit. This bit is cleared only by software or POR.
-            EXTR: u1,
-            ///  This bit is set when the Watchdog Timer times out and the WDTRESET bit in the Watchdog Mode Register is 1. This bit is cleared only by software or POR.
-            WDTR: u1,
-            ///  This bit is set when the VDD(REG)(3V3) voltage reaches a level below the BOD reset trip level (typically 1.85 V under nominal room temperature conditions). If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and recovers, the BODR bit will be set to 1. If the VDD(REG)(3V3) voltage dips from the normal operating range to below the BOD reset trip level and continues to decline to the level at which POR is asserted (nominally 1 V), the BODR bit is cleared. If the VDD(REG)(3V3) voltage rises continuously from below 1 V to a level above the BOD reset trip level, the BODR will be set to 1. This bit is cleared only by software or POR. Note: Only in the case where a reset occurs and the POR = 0, the BODR bit indicates if the VDD(REG)(3V3) voltage was below the BOD reset trip level or not.
-            BODR: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        reserved416: [28]u8,
-        ///  System control and status
-        SCS: mmio.Mmio(packed struct(u32) {
-            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u4,
-            ///  Main oscillator range select.
-            OSCRANGE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Low. The frequency range of the main oscillator is 1 MHz to 20 MHz.
-                    LOW = 0x0,
-                    ///  High. The frequency range of the main oscillator is 15 MHz to 25 MHz.
-                    HIGH = 0x1,
-                },
-            },
-            ///  Main oscillator enable.
-            OSCEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Disabled. The main oscillator is disabled.
-                    DISABLED = 0x0,
-                    ///  Enabled.The main oscillator is enabled, and will start up if the correct external circuitry is connected to the XTAL1 and XTAL2 pins.
-                    ENABLED = 0x1,
-                },
-            },
-            ///  Main oscillator status.
-            OSCSTAT: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Not ready. The main oscillator is not ready to be used as a clock source.
-                    NOT_READY = 0x0,
-                    ///  Ready. The main oscillator is ready to be used as a clock source. The main oscillator must be enabled via the OSCEN bit.
-                    READY = 0x1,
-                },
-            },
-            ///  Reserved. User software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u25,
-        }),
-        reserved424: [4]u8,
-        ///  Peripheral Clock Selection register 0.
-        PCLKSEL0: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral clock selection for WDT.
-            PCLK_WDT: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for TIMER0.
-            PCLK_TIMER0: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for TIMER1.
-            PCLK_TIMER1: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for UART0.
-            PCLK_UART0: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for UART1.
-            PCLK_UART1: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u2,
-            ///  Peripheral clock selection for PWM1.
-            PCLK_PWM1: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for I2C0.
-            PCLK_I2C0: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for SPI.
-            PCLK_SPI: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u2,
-            ///  Peripheral clock selection for SSP1.
-            PCLK_SSP1: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for DAC.
-            PCLK_DAC: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for ADC.
-            PCLK_ADC: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for CAN1.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.
-            PCLK_CAN1: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 6. PCLK_peripheral = CCLK/6.
-                    CCLK_DIV_6 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for CAN2.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.
-            PCLK_CAN2: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 6. PCLK_peripheral = CCLK/6,
-                    CCLK_DIV_6 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for CAN acceptance filtering.PCLK_CAN1 and PCLK_CAN2 must have the same PCLK divide value when the CAN function is used.
-            PCLK_ACF: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 6. PCLK_peripheral = CCLK/6
-                    CCLK_DIV_6 = 0x3,
-                },
-            },
-        }),
-        ///  Peripheral Clock Selection register 1.
-        PCLKSEL1: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral clock selection for the Quadrature Encoder Interface.
-            PCLK_QEI: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for GPIO interrupts.
-            PCLK_GPIOINT: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for the Pin Connect block.
-            PCLK_PCB: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for I2C1.
-            PCLK_I2C1: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u2,
-            ///  Peripheral clock selection for SSP0.
-            PCLK_SSP0: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for TIMER2.
-            PCLK_TIMER2: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for TIMER3.
-            PCLK_TIMER3: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for UART2.
-            PCLK_UART2: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for UART3.
-            PCLK_UART3: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for I2C2.
-            PCLK_I2C2: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for I2S.
-            PCLK_I2S: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u2,
-            ///  Peripheral clock selection for Repetitive Interrupt Timer.
-            PCLK_RIT: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for the System Control block.
-            PCLK_SYSCON: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-            ///  Peripheral clock selection for the Motor Control PWM.
-            PCLK_MC: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  CCLK div 4. PCLK_peripheral = CCLK/4
-                    CCLK_DIV_4 = 0x0,
-                    ///  CCLK. PCLK_peripheral = CCLK
-                    CCLK = 0x1,
-                    ///  CCLK div 2. PCLK_peripheral = CCLK/2
-                    CCLK_DIV_2 = 0x2,
-                    ///  CCLK div 8. PCLK_peripheral = CCLK/8
-                    CCLK_DIV_8 = 0x3,
-                },
-            },
-        }),
-        reserved448: [16]u8,
-        ///  USB Interrupt Status
-        USBINTST: mmio.Mmio(packed struct(u32) {
-            ///  Low priority interrupt line status. This bit is read-only.
-            USB_INT_REQ_LP: u1,
-            ///  High priority interrupt line status. This bit is read-only.
-            USB_INT_REQ_HP: u1,
-            ///  DMA interrupt line status. This bit is read-only.
-            USB_INT_REQ_DMA: u1,
-            ///  USB host interrupt line status. This bit is read-only.
-            USB_HOST_INT: u1,
-            ///  External ATX interrupt line status. This bit is read-only.
-            USB_ATX_INT: u1,
-            ///  OTG interrupt line status. This bit is read-only.
-            USB_OTG_INT: u1,
-            ///  I2C module interrupt line status. This bit is read-only.
-            USB_I2C_INT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u1,
-            ///  USB need clock indicator. This bit is read-only. This bit is set to 1 when USB activity or a change of state on the USB data pins is detected, and it indicates that a PLL supplied clock of 48 MHz is needed. Once USB_NEED_CLK becomes one, it resets to zero 5 ms after the last packet has been received/sent, or 2 ms after the Suspend Change (SUS_CH) interrupt has occurred. A change of this bit from 0 to 1 can wake up the microcontroller if activity on the USB bus is selected to wake up the part from the Power-down mode (see Section 4.7.9 Wake-up from Reduced Power Modes for details). Also see Section 4.5.8 PLLs and Power-down mode and Section 4.7.10 Power Control for Peripherals register (PCONP - 0x400F C0C4) for considerations about the PLL and invoking the Power-down mode. This bit is read-only.
-            USB_NEED_CLK: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u22,
-            ///  Enable all USB interrupts. When this bit is cleared, the NVIC does not see the ORed output of the USB interrupt lines.
-            EN_USB_INTS: u1,
-        }),
-        ///  Selects between alternative requests on DMA channels 0 through 7 and 10 through 15
-        DMACREQSEL: mmio.Mmio(packed struct(u32) {
-            ///  Selects the DMA request for GPDMA input 8: 0 - uart0 tx 1 - Timer 0 match 0 is selected.
-            DMASEL08: u1,
-            ///  Selects the DMA request for GPDMA input 9: 0 - uart0 rx 1 - Timer 0 match 1 is selected.
-            DMASEL09: u1,
-            ///  Selects the DMA request for GPDMA input 10: 0 - uart1 tx is selected. 1 - Timer 1 match 0 is selected.
-            DMASEL10: u1,
-            ///  Selects the DMA request for GPDMA input 11: 0 - uart1 rx is selected. 1 - Timer 1 match 1 is selected.
-            DMASEL11: u1,
-            ///  Selects the DMA request for GPDMA input 12: 0 - uart2 tx is selected. 1 - Timer 2 match 0 is selected.
-            DMASEL12: u1,
-            ///  Selects the DMA request for GPDMA input 13: 0 - uart2 rx is selected. 1 - Timer 2 match 1 is selected.
-            DMASEL13: u1,
-            ///  Selects the DMA request for GPDMA input 14: 0 - uart3 tx is selected. 1 - I2S channel 0 is selected.
-            DMASEL14: u1,
-            ///  Selects the DMA request for GPDMA input 15: 0 - uart3 rx is selected. 1 - I2S channel 1 is selected.
-            DMASEL15: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u24,
-        }),
-        ///  Clock Output Configuration Register
-        CLKOUTCFG: mmio.Mmio(packed struct(u32) {
-            ///  Selects the clock source for the CLKOUT function. Other values are reserved. Do not use.
-            CLKOUTSEL: packed union {
-                raw: u4,
-                value: enum(u4) {
-                    ///  Selects the CPU clock as the CLKOUT source.
-                    SELECTS_THE_CPU_CLOC = 0x0,
-                    ///  Selects the main oscillator as the CLKOUT source.
-                    SELECTS_THE_MAIN_OSC = 0x1,
-                    ///  Selects the Internal RC oscillator as the CLKOUT source.
-                    SELECTS_THE_INTERNAL = 0x2,
-                    ///  Selects the USB clock as the CLKOUT source.
-                    SELECTS_THE_USB_CLOC = 0x3,
-                    ///  Selects the RTC oscillator as the CLKOUT source.
-                    SELECTS_THE_RTC_OSCI = 0x4,
-                    _,
-                },
-            },
-            ///  Integer value to divide the output clock by, minus one. 0 = Clock is divided by 1 1 = Clock is divided by 2. 2 = Clock is divided by 3. ... 15 = Clock is divided by 16.
-            CLKOUTDIV: u4,
-            ///  CLKOUT enable control, allows switching the CLKOUT source without glitches. Clear to stop CLKOUT on the next falling edge. Set to enable CLKOUT.
-            CLKOUT_EN: u1,
-            ///  CLKOUT activity indication. Reads as 1 when CLKOUT is enabled. Read as 0 when CLKOUT has been disabled via the CLKOUT_EN bit and the clock has completed being stopped.
-            CLKOUT_ACT: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u22,
-        }),
-    };
-
-    ///  Quadrature Encoder Interface (QEI)
-    pub const QEI = extern struct {
-        ///  Control register
-        CON: mmio.Mmio(packed struct(u32) {
-            ///  Reset position counter. When set = 1, resets the position counter to all zeros. Autoclears when the position counter is cleared.
-            RESP: u1,
-            ///  Reset position counter on index. When set = 1, resets the position counter to all zeros once only the first time an index pulse occurs. Autoclears when the position counter is cleared.
-            RESPI: u1,
-            ///  Reset velocity. When set = 1, resets the velocity counter to all zeros, reloads the velocity timer, and presets the velocity compare register. Autoclears when the velocity counter is cleared.
-            RESV: u1,
-            ///  Reset index counter. When set = 1, resets the index counter to all zeros. Autoclears when the index counter is cleared.
-            RESI: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u28,
-        }),
-        ///  Status register
-        STAT: mmio.Mmio(packed struct(u32) {
-            ///  Direction bit. In combination with DIRINV bit indicates forward or reverse direction. See Table 597.
-            DIR: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u31,
-        }),
-        ///  Configuration register
-        CONF: mmio.Mmio(packed struct(u32) {
-            ///  Direction invert. When 1, complements the DIR bit.
-            DIRINV: u1,
-            ///  Signal Mode. When 0, PhA and PhB function as quadrature encoder inputs. When 1, PhA functions as the direction signal and PhB functions as the clock signal.
-            SIGMODE: u1,
-            ///  Capture Mode. When 0, only PhA edges are counted (2X). When 1, BOTH PhA and PhB edges are counted (4X), increasing resolution but decreasing range.
-            CAPMODE: u1,
-            ///  Invert Index. When 1, inverts the sense of the index input.
-            INVINX: u1,
-            ///  Continuously reset the position counter on index. When 1, resets the position counter to all zeros whenever an index pulse occurs after the next position increase (recalibration).
-            CRESPI: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u11,
-            ///  Index gating configuration: When INXGATE[16] = 1, pass the index when PHA = 1 and PHB = 0, otherwise block index. When INXGATE[17] = 1, pass the index when PHA = 1 and PHB = 1, otherwise block index. When INXGATE[18] = 1, pass the index when PHA = 0 and PHB = 1, otherwise block index. When INXGATE[19] = 1, pass the index when PHA = 0 and PHB = 0, otherwise block index.
-            INXGATE: u4,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u12,
-        }),
-        ///  Position register
-        POS: mmio.Mmio(packed struct(u32) {
-            ///  Current position value.
-            POS: u32,
-        }),
-        ///  Maximum position register
-        MAXPOS: mmio.Mmio(packed struct(u32) {
-            ///  Current maximum position value.
-            MAXPOS: u32,
-        }),
-        ///  Position compare register 0
-        CMPOS0: mmio.Mmio(packed struct(u32) {
-            ///  Position compare value 0.
-            PCMP0: u32,
-        }),
-        ///  Position compare register 1
-        CMPOS1: mmio.Mmio(packed struct(u32) {
-            ///  Position compare value 1.
-            PCMP1: u32,
-        }),
-        ///  Position compare register 2
-        CMPOS2: mmio.Mmio(packed struct(u32) {
-            ///  Position compare value 2.
-            PCMP2: u32,
-        }),
-        ///  Index count register 0
-        INXCNT: mmio.Mmio(packed struct(u32) {
-            ///  Current index counter value.
-            ENCPOS: u32,
-        }),
-        ///  Index compare register 0
-        INXCMP0: mmio.Mmio(packed struct(u32) {
-            ///  Index compare value 0.
-            ICMP0: u32,
-        }),
-        ///  Velocity timer reload register
-        LOAD: mmio.Mmio(packed struct(u32) {
-            ///  Current velocity timer load value.
-            VELLOAD: u32,
-        }),
-        ///  Velocity timer register
-        TIME: mmio.Mmio(packed struct(u32) {
-            ///  Current velocity timer value.
-            VELVAL: u32,
-        }),
-        ///  Velocity counter register
-        VEL: mmio.Mmio(packed struct(u32) {
-            ///  Current velocity pulse count.
-            VELPC: u32,
-        }),
-        ///  Velocity capture register
-        CAP: mmio.Mmio(packed struct(u32) {
-            ///  Last velocity capture.
-            VELCAP: u32,
-        }),
-        ///  Velocity compare register
-        VELCOMP: mmio.Mmio(packed struct(u32) {
-            ///  Compare velocity pulse count.
-            VELPC: u32,
-        }),
-        ///  Digital filter register
-        FILTER: mmio.Mmio(packed struct(u32) {
-            ///  Digital filter sampling delay.
-            FILTA: u32,
-        }),
-        reserved4056: [3992]u8,
-        ///  Interrupt enable clear register
-        IEC: mmio.Mmio(packed struct(u32) {
-            ///  Writing a 1 disables the INX_Int interrupt in the QEIIE register.
-            INX_INT: u1,
-            ///  Writing a 1 disables the TIN_Int interrupt in the QEIIE register.
-            TIM_INT: u1,
-            ///  Writing a 1 disables the VELC_Int interrupt in the QEIIE register.
-            VELC_INT: u1,
-            ///  Writing a 1 disables the DIR_Int interrupt in the QEIIE register.
-            DIR_INT: u1,
-            ///  Writing a 1 disables the ERR_Int interrupt in the QEIIE register.
-            ERR_INT: u1,
-            ///  Writing a 1 disables the ENCLK_Int interrupt in the QEIIE register.
-            ENCLK_INT: u1,
-            ///  Writing a 1 disables the POS0_Int interrupt in the QEIIE register.
-            POS0_INT: u1,
-            ///  Writing a 1 disables the POS1_Int interrupt in the QEIIE register.
-            POS1_INT: u1,
-            ///  Writing a 1 disables the POS2_Int interrupt in the QEIIE register.
-            POS2_INT: u1,
-            ///  Writing a 1 disables the REV0_Int interrupt in the QEIIE register.
-            REV0_INT: u1,
-            ///  Writing a 1 disables the POS0REV_Int interrupt in the QEIIE register.
-            POS0REV_INT: u1,
-            ///  Writing a 1 disables the POS1REV_Int interrupt in the QEIIE register.
-            POS1REV_INT: u1,
-            ///  Writing a 1 disables the POS2REV_Int interrupt in the QEIIE register.
-            POS2REV_INT: u1,
-            ///  Writing a 1 disables the REV1_Int interrupt in the QEIIE register.
-            REV1_INT: u1,
-            ///  Writing a 1 disables the REV2_Int interrupt in the QEIIE register.
-            REV2_INT: u1,
-            ///  Writing a 1 disables the MAXPOS_Int interrupt in the QEIIE register.
-            MAXPOS_INT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-        ///  Interrupt enable set register
-        IES: mmio.Mmio(packed struct(u32) {
-            ///  Writing a 1 enables the INX_Int interrupt in the QEIIE register.
-            INX_INT: u1,
-            ///  Writing a 1 enables the TIN_Int interrupt in the QEIIE register.
-            TIM_INT: u1,
-            ///  Writing a 1 enables the VELC_Int interrupt in the QEIIE register.
-            VELC_INT: u1,
-            ///  Writing a 1 enables the DIR_Int interrupt in the QEIIE register.
-            DIR_INT: u1,
-            ///  Writing a 1 enables the ERR_Int interrupt in the QEIIE register.
-            ERR_INT: u1,
-            ///  Writing a 1 enables the ENCLK_Int interrupt in the QEIIE register.
-            ENCLK_INT: u1,
-            ///  Writing a 1 enables the POS0_Int interrupt in the QEIIE register.
-            POS0_INT: u1,
-            ///  Writing a 1 enables the POS1_Int interrupt in the QEIIE register.
-            POS1_INT: u1,
-            ///  Writing a 1 enables the POS2_Int interrupt in the QEIIE register.
-            POS2_INT: u1,
-            ///  Writing a 1 enables the REV0_Int interrupt in the QEIIE register.
-            REV0_INT: u1,
-            ///  Writing a 1 enables the POS0REV_Int interrupt in the QEIIE register.
-            POS0REV_INT: u1,
-            ///  Writing a 1 enables the POS1REV_Int interrupt in the QEIIE register.
-            POS1REV_INT: u1,
-            ///  Writing a 1 enables the POS2REV_Int interrupt in the QEIIE register.
-            POS2REV_INT: u1,
-            ///  Writing a 1 enables the REV1_Int interrupt in the QEIIE register.
-            REV1_INT: u1,
-            ///  Writing a 1 enables the REV2_Int interrupt in the QEIIE register.
-            REV2_INT: u1,
-            ///  Writing a 1 enables the MAXPOS_Int interrupt in the QEIIE register.
-            MAXPOS_INT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-        ///  Interrupt status register
-        INTSTAT: mmio.Mmio(packed struct(u32) {
-            ///  Indicates that an index pulse was detected.
-            INX_INT: u1,
-            ///  Indicates that a velocity timer overflow occurred
-            TIM_INT: u1,
-            ///  Indicates that captured velocity is less than compare velocity.
-            VELC_INT: u1,
-            ///  Indicates that a change of direction was detected.
-            DIR_INT: u1,
-            ///  Indicates that an encoder phase error was detected.
-            ERR_INT: u1,
-            ///  Indicates that and encoder clock pulse was detected.
-            ENCLK_INT: u1,
-            ///  Indicates that the position 0 compare value is equal to the current position.
-            POS0_INT: u1,
-            ///  Indicates that the position 1compare value is equal to the current position.
-            POS1_INT: u1,
-            ///  Indicates that the position 2 compare value is equal to the current position.
-            POS2_INT: u1,
-            ///  Indicates that the index compare 0 value is equal to the current index count.
-            REV0_INT: u1,
-            ///  Combined position 0 and revolution count interrupt. Set when both the POS0_Int bit is set and the REV0_Int is set.
-            POS0REV_INT: u1,
-            ///  Combined position 1 and revolution count interrupt. Set when both the POS1_Int bit is set and the REV1_Int is set.
-            POS1REV_INT: u1,
-            ///  Combined position 2 and revolution count interrupt. Set when both the POS2_Int bit is set and the REV2_Int is set.
-            POS2REV_INT: u1,
-            ///  Indicates that the index compare 1value is equal to the current index count.
-            REV1_INT: u1,
-            ///  Indicates that the index compare 2 value is equal to the current index count.
-            REV2_INT: u1,
-            ///  Indicates that the current position count goes through the MAXPOS value to zero in the forward direction, or through zero to MAXPOS in the reverse direction.
-            MAXPOS_INT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-        ///  Interrupt enable register
-        IE: mmio.Mmio(packed struct(u32) {
-            ///  When 1, the INX_Int interrupt is enabled.
-            INX_INT: u1,
-            ///  When 1, the TIN_Int interrupt is enabled.
-            TIM_INT: u1,
-            ///  When 1, the VELC_Int interrupt is enabled.
-            VELC_INT: u1,
-            ///  When 1, the DIR_Int interrupt is enabled.
-            DIR_INT: u1,
-            ///  When 1, the ERR_Int interrupt is enabled.
-            ERR_INT: u1,
-            ///  When 1, the ENCLK_Int interrupt is enabled.
-            ENCLK_INT: u1,
-            ///  When 1, the POS0_Int interrupt is enabled.
-            POS0_INT: u1,
-            ///  When 1, the POS1_Int interrupt is enabled.
-            POS1_INT: u1,
-            ///  When 1, the POS2_Int interrupt is enabled.
-            POS2_INT: u1,
-            ///  When 1, the REV0_Int interrupt is enabled.
-            REV0_INT: u1,
-            ///  When 1, the POS0REV_Int interrupt is enabled.
-            POS0REV_INT: u1,
-            ///  When 1, the POS1REV_Int interrupt is enabled.
-            POS1REV_INT: u1,
-            ///  When 1, the POS2REV_Int interrupt is enabled.
-            POS2REV_INT: u1,
-            ///  When 1, the REV1_Int interrupt is enabled.
-            REV1_INT: u1,
-            ///  When 1, the REV2_Int interrupt is enabled.
-            REV2_INT: u1,
-            ///  When 1, the MAXPOS_Int interrupt is enabled.
-            MAXPOS_INT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-        ///  Interrupt status clear register
-        CLR: mmio.Mmio(packed struct(u32) {
-            ///  Writing a 1 clears the INX_Int bit in QEIINTSTAT.
-            INX_INT: u1,
-            ///  Writing a 1 clears the TIN_Int bit in QEIINTSTAT.
-            TIM_INT: u1,
-            ///  Writing a 1 clears the VELC_Int bit in QEIINTSTAT.
-            VELC_INT: u1,
-            ///  Writing a 1 clears the DIR_Int bit in QEIINTSTAT.
-            DIR_INT: u1,
-            ///  Writing a 1 clears the ERR_Int bit in QEIINTSTAT.
-            ERR_INT: u1,
-            ///  Writing a 1 clears the ENCLK_Int bit in QEIINTSTAT.
-            ENCLK_INT: u1,
-            ///  Writing a 1 clears the POS0_Int bit in QEIINTSTAT.
-            POS0_INT: u1,
-            ///  Writing a 1 clears the POS1_Int bit in QEIINTSTAT.
-            POS1_INT: u1,
-            ///  Writing a 1 clears the POS2_Int bit in QEIINTSTAT.
-            POS2_INT: u1,
-            ///  Writing a 1 clears the REV0_Int bit in QEIINTSTAT.
-            REV0_INT: u1,
-            ///  Writing a 1 clears the POS0REV_Int bit in QEIINTSTAT.
-            POS0REV_INT: u1,
-            ///  Writing a 1 clears the POS1REV_Int bit in QEIINTSTAT.
-            POS1REV_INT: u1,
-            ///  Writing a 1 clears the POS2REV_Int bit in QEIINTSTAT.
-            POS2REV_INT: u1,
-            ///  Writing a 1 clears the REV1_Int bit in QEIINTSTAT.
-            REV1_INT: u1,
-            ///  Writing a 1 clears the REV2_Int bit in QEIINTSTAT.
-            REV2_INT: u1,
-            ///  Writing a 1 clears the MAXPOS_Int bit in QEIINTSTAT.
-            MAXPOS_INT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-        ///  Interrupt status set register
-        SET: mmio.Mmio(packed struct(u32) {
-            ///  Writing a 1 sets the INX_Int bit in QEIINTSTAT.
-            INX_INT: u1,
-            ///  Writing a 1 sets the TIN_Int bit in QEIINTSTAT.
-            TIM_INT: u1,
-            ///  Writing a 1 sets the VELC_Int bit in QEIINTSTAT.
-            VELC_INT: u1,
-            ///  Writing a 1 sets the DIR_Int bit in QEIINTSTAT.
-            DIR_INT: u1,
-            ///  Writing a 1 sets the ERR_Int bit in QEIINTSTAT.
-            ERR_INT: u1,
-            ///  Writing a 1 sets the ENCLK_Int bit in QEIINTSTAT.
-            ENCLK_INT: u1,
-            ///  Writing a 1 sets the POS0_Int bit in QEIINTSTAT.
-            POS0_INT: u1,
-            ///  Writing a 1 sets the POS1_Int bit in QEIINTSTAT.
-            POS1_INT: u1,
-            ///  Writing a 1 sets the POS2_Int bit in QEIINTSTAT.
-            POS2_INT: u1,
-            ///  Writing a 1 sets the REV0_Int bit in QEIINTSTAT.
-            REV0_INT: u1,
-            ///  Writing a 1 sets the POS0REV_Int bit in QEIINTSTAT.
-            POS0REV_INT: u1,
-            ///  Writing a 1 sets the POS1REV_Int bit in QEIINTSTAT.
-            POS1REV_INT: u1,
-            ///  Writing a 1 sets the POS2REV_Int bit in QEIINTSTAT.
-            POS2REV_INT: u1,
-            ///  Writing a 1 sets the REV1_Int bit in QEIINTSTAT.
-            REV1_INT: u1,
-            ///  Writing a 1 sets the REV2_Int bit in QEIINTSTAT.
-            REV2_INT: u1,
-            ///  Writing a 1 sets the MAXPOS_Int bit in QEIINTSTAT.
-            MAXPOS_INT: u1,
-            ///  Reserved. Read value is undefined, only zero should be written.
-            RESERVED: u16,
-        }),
-    };
-
-    ///  Motor Control PWM
-    pub const MCPWM = extern struct {
-        ///  PWM Control read address
-        CON: mmio.Mmio(packed struct(u32) {
-            ///  Stops/starts timer channel 0.
-            RUN0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Stop.
-                    STOP_ = 0x0,
-                    ///  Run.
-                    RUN_ = 0x1,
-                },
-            },
-            ///  Edge/center aligned operation for channel 0.
-            CENTER0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Edge-aligned.
-                    EDGE_ALIGNED_ = 0x0,
-                    ///  Center-aligned.
-                    CENTER_ALIGNED_ = 0x1,
-                },
-            },
-            ///  Selects polarity of the MCOA0 and MCOB0 pins.
-            POLA0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Passive state is LOW, active state is HIGH.
-                    PASSIVE_STATE_IS_LOW = 0x0,
-                    ///  Passive state is HIGH, active state is LOW.
-                    PASSIVE_STATE_IS_HIG = 0x1,
-                },
-            },
-            ///  Controls the dead-time feature for channel 0.
-            DTE0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Dead-time disabled.
-                    DEAD_TIME_DISABLED_ = 0x0,
-                    ///  Dead-time enabled.
-                    DEAD_TIME_ENABLED_ = 0x1,
-                },
-            },
-            ///  Enable/disable updates of functional registers for channel 0 (see Section 24.8.2).
-            DISUP0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Functional registers are updated from the write registers at the end of each PWM cycle.
-                    UPDATE = 0x0,
-                    ///  Functional registers remain the same as long as the timer is running.
-                    NOUPDATE = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u3,
-            ///  Stops/starts timer channel 1.
-            RUN1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Stop.
-                    STOP_ = 0x0,
-                    ///  Run.
-                    RUN_ = 0x1,
-                },
-            },
-            ///  Edge/center aligned operation for channel 1.
-            CENTER1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Edge-aligned.
-                    EDGE_ALIGNED_ = 0x0,
-                    ///  Center-aligned.
-                    CENTER_ALIGNED_ = 0x1,
-                },
-            },
-            ///  Selects polarity of the MCOA1 and MCOB1 pins.
-            POLA1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Passive state is LOW, active state is HIGH.
-                    PASSIVE_STATE_IS_LOW = 0x0,
-                    ///  Passive state is HIGH, active state is LOW.
-                    PASSIVE_STATE_IS_HIG = 0x1,
-                },
-            },
-            ///  Controls the dead-time feature for channel 1.
-            DTE1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Dead-time disabled.
-                    DEAD_TIME_DISABLED_ = 0x0,
-                    ///  Dead-time enabled.
-                    DEAD_TIME_ENABLED_ = 0x1,
-                },
-            },
-            ///  Enable/disable updates of functional registers for channel 1 (see Section 24.8.2).
-            DISUP1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Functional registers are updated from the write registers at the end of each PWM cycle.
-                    UPDATE = 0x0,
-                    ///  Functional registers remain the same as long as the timer is running.
-                    NOUPDATE = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u3,
-            ///  Stops/starts timer channel 2.
-            RUN2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Stop.
-                    STOP_ = 0x0,
-                    ///  Run.
-                    RUN_ = 0x1,
-                },
-            },
-            ///  Edge/center aligned operation for channel 2.
-            CENTER2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Edge-aligned.
-                    EDGE_ALIGNED_ = 0x0,
-                    ///  Center-aligned.
-                    CENTER_ALIGNED_ = 0x1,
-                },
-            },
-            ///  Selects polarity of the MCOA2 and MCOB2 pins.
-            POLA2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Passive state is LOW, active state is HIGH.
-                    PASSIVE_STATE_IS_LOW = 0x0,
-                    ///  Passive state is HIGH, active state is LOW.
-                    PASSIVE_STATE_IS_HIG = 0x1,
-                },
-            },
-            ///  Controls the dead-time feature for channel 1.
-            DTE2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Dead-time disabled.
-                    DEAD_TIME_DISABLED_ = 0x0,
-                    ///  Dead-time enabled.
-                    DEAD_TIME_ENABLED_ = 0x1,
-                },
-            },
-            ///  Enable/disable updates of functional registers for channel 2 (see Section 24.8.2).
-            DISUP2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Functional registers are updated from the write registers at the end of each PWM cycle.
-                    UPDATE = 0x0,
-                    ///  Functional registers remain the same as long as the timer is running.
-                    NOUPDATE = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u8,
-            ///  Controls the polarity of the MCOB outputs for all 3 channels. This bit is typically set to 1 only in 3-phase DC mode.
-            INVBDC: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The MCOB outputs have opposite polarity from the MCOA outputs (aside from dead time).
-                    OPPOSITE = 0x0,
-                    ///  The MCOB outputs have the same basic polarity as the MCOA outputs. (see Section 24.8.6)
-                    SAME = 0x1,
-                },
-            },
-            ///  3-phase AC mode select (see Section 24.8.7).
-            ACMODE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  3-phase AC-mode off: Each PWM channel uses its own timer-counter and period register.
-                    @"3_PHASE_AC_MODE_OFF" = 0x0,
-                    ///  3-phase AC-mode on: All PWM channels use the timer-counter and period register of channel 0.
-                    @"3_PHASE_AC_MODE_ON_" = 0x1,
-                },
-            },
-            ///  3-phase DC mode select (see Section 24.8.6).
-            DCMODE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  3-phase DC mode off: PWM channels are independent (unless bit ACMODE = 1)
-                    @"3_PHASE_DC_MODE_OFF" = 0x0,
-                    ///  3-phase DC mode on: The internal MCOA0 output is routed through the CP register (i.e. a mask) register to all six PWM outputs.
-                    @"3_PHASE_DC_MODE_ON_" = 0x1,
-                },
-            },
-        }),
-        ///  PWM Control set address
-        CON_SET: mmio.Mmio(packed struct(u32) {
-            ///  Writing a one sets the corresponding bit in the CON register.
-            RUN0_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            CENTER0_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            POLA0_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            DTE0_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            DISUP0_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            RESERVED: u3,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            RUN1_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            CENTER1_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            POLA1_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            DTE1_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            DISUP1_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            RESERVED: u3,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            RUN2_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            CENTER2_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            POLA2_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            DTE2_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            DISUP2_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            RESERVED: u8,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            INVBDC_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            ACMODE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CON register.
-            DCMODE_SET: u1,
-        }),
-        ///  PWM Control clear address
-        CON_CLR: mmio.Mmio(packed struct(u32) {
-            ///  Writing a one clears the corresponding bit in the CON register.
-            RUN0_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            CENTER0_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            POLA0_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            DTE0_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            DISUP0_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            RESERVED: u3,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            RUN1_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            CENTER1_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            POLA1_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            DTE1_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            DISUP1_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            RESERVED: u3,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            RUN2_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            CENTER2_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            POLA2_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            DTE2_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            DISUP2_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            RESERVED: u8,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            INVBDC_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            ACMOD_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CON register.
-            DCMODE_CLR: u1,
-        }),
-        ///  Capture Control read address
-        CAPCON: mmio.Mmio(packed struct(u32) {
-            ///  A 1 in this bit enables a channel 0 capture event on a rising edge on MCI0.
-            CAP0MCI0_RE: u1,
-            ///  A 1 in this bit enables a channel 0 capture event on a falling edge on MCI0.
-            CAP0MCI0_FE: u1,
-            ///  A 1 in this bit enables a channel 0 capture event on a rising edge on MCI1.
-            CAP0MCI1_RE: u1,
-            ///  A 1 in this bit enables a channel 0 capture event on a falling edge on MCI1.
-            CAP0MCI1_FE: u1,
-            ///  A 1 in this bit enables a channel 0 capture event on a rising edge on MCI2.
-            CAP0MCI2_RE: u1,
-            ///  A 1 in this bit enables a channel 0 capture event on a falling edge on MCI2.
-            CAP0MCI2_FE: u1,
-            ///  A 1 in this bit enables a channel 1 capture event on a rising edge on MCI0.
-            CAP1MCI0_RE: u1,
-            ///  A 1 in this bit enables a channel 1 capture event on a falling edge on MCI0.
-            CAP1MCI0_FE: u1,
-            ///  A 1 in this bit enables a channel 1 capture event on a rising edge on MCI1.
-            CAP1MCI1_RE: u1,
-            ///  A 1 in this bit enables a channel 1 capture event on a falling edge on MCI1.
-            CAP1MCI1_FE: u1,
-            ///  A 1 in this bit enables a channel 1 capture event on a rising edge on MCI2.
-            CAP1MCI2_RE: u1,
-            ///  A 1 in this bit enables a channel 1 capture event on a falling edge on MCI2.
-            CAP1MCI2_FE: u1,
-            ///  A 1 in this bit enables a channel 2 capture event on a rising edge on MCI0.
-            CAP2MCI0_RE: u1,
-            ///  A 1 in this bit enables a channel 2 capture event on a falling edge on MCI0.
-            CAP2MCI0_FE: u1,
-            ///  A 1 in this bit enables a channel 2 capture event on a rising edge on MCI1.
-            CAP2MCI1_RE: u1,
-            ///  A 1 in this bit enables a channel 2 capture event on a falling edge on MCI1.
-            CAP2MCI1_FE: u1,
-            ///  A 1 in this bit enables a channel 2 capture event on a rising edge on MCI2.
-            CAP2MCI2_RE: u1,
-            ///  A 1 in this bit enables a channel 2 capture event on a falling edge on MCI2.
-            CAP2MCI2_FE: u1,
-            ///  If this bit is 1, TC0 is reset by a channel 0 capture event.
-            RT0: u1,
-            ///  If this bit is 1, TC1 is reset by a channel 1 capture event.
-            RT1: u1,
-            ///  If this bit is 1, TC2 is reset by a channel 2 capture event.
-            RT2: u1,
-            ///  Reserved.
-            RESERVED: u11,
-        }),
-        ///  Capture Control set address
-        CAPCON_SET: mmio.Mmio(packed struct(u32) {
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP0MCI0_RE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP0MCI0_FE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP0MCI1_RE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP0MCI1_FE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP0MCI2_RE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP0MCI2_FE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP1MCI0_RE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP1MCI0_FE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP1MCI1_RE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP1MCI1_FE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP1MCI2_RE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP1MCI2_FE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP2MCI0_RE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP2MCI0_FE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP2MCI1_RE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP2MCI1_FE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP2MCI2_RE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            CAP2MCI2_FE_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            RT0_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            RT1_SET: u1,
-            ///  Writing a one sets the corresponding bits in the CAPCON register.
-            RT2_SET: u1,
-            ///  Reserved.
-            RESERVED: u11,
-        }),
-        ///  Event Control clear address
-        CAPCON_CLR: mmio.Mmio(packed struct(u32) {
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP0MCI0_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP0MCI0_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP0MCI1_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP0MCI1_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP0MCI2_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP0MCI2_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP1MCI0_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP1MCI0_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP1MCI1_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP1MCI1_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP1MCI2_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP1MCI2_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP2MCI0_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP2MCI0_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP2MCI1_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP2MCI1_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP2MCI2_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            CAP2MCI2_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            RT0_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            RT1_CLR: u1,
-            ///  Writing a one clears the corresponding bits in the CAPCON register.
-            RT2_CLR: u1,
-            ///  Reserved.
-            RESERVED: u11,
-        }),
-        reserved60: [36]u8,
-        ///  Dead time register
-        DT: mmio.Mmio(packed struct(u32) {
-            ///  Dead time for channel 0.[1]
-            DT0: u10,
-            ///  Dead time for channel 1.[2]
-            DT1: u10,
-            ///  Dead time for channel 2.[2]
-            DT2: u10,
-            ///  reserved
-            RESERVED: u2,
-        }),
-        ///  Communication Pattern register
-        CP: mmio.Mmio(packed struct(u32) {
-            ///  Communication pattern output A, channel 0.
-            CCPA0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  MCOA0 passive.
-                    MCOA0_PASSIVE_ = 0x0,
-                    ///  internal MCOA0.
-                    INTERNAL_MCOA0_ = 0x1,
-                },
-            },
-            ///  Communication pattern output B, channel 0.
-            CCPB0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  MCOB0 passive.
-                    MCOB0_PASSIVE_ = 0x0,
-                    ///  MCOB0 tracks internal MCOA0.
-                    MCOB0_TRACKS_INTERNA = 0x1,
-                },
-            },
-            ///  Communication pattern output A, channel 1.
-            CCPA1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  MCOA1 passive.
-                    MCOA1_PASSIVE_ = 0x0,
-                    ///  MCOA1 tracks internal MCOA0.
-                    MCOA1_TRACKS_INTERNA = 0x1,
-                },
-            },
-            ///  Communication pattern output B, channel 1.
-            CCPB1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  MCOB1 passive.
-                    MCOB1_PASSIVE_ = 0x0,
-                    ///  MCOB1 tracks internal MCOA0.
-                    MCOB1_TRACKS_INTERNA = 0x1,
-                },
-            },
-            ///  Communication pattern output A, channel 2.
-            CCPA2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  MCOA2 passive.
-                    MCOA2_PASSIVE_ = 0x0,
-                    ///  MCOA2 tracks internal MCOA0.
-                    MCOA2_TRACKS_INTERNA = 0x1,
-                },
-            },
-            ///  Communication pattern output B, channel 2.
-            CCPB2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  MCOB2 passive.
-                    MCOB2_PASSIVE_ = 0x0,
-                    ///  MCOB2 tracks internal MCOA0.
-                    MCOB2_TRACKS_INTERNA = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u26,
-        }),
-        reserved80: [12]u8,
-        ///  Interrupt Enable read address
-        INTEN: mmio.Mmio(packed struct(u32) {
-            ///  Limit interrupt for channel 0.
-            ILIM0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt disabled.
-                    INTERRUPT_DISABLED_ = 0x0,
-                    ///  Interrupt enabled.
-                    INTERRUPT_ENABLED_ = 0x1,
-                },
-            },
-            ///  Match interrupt for channel 0.
-            IMAT0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt disabled.
-                    INTERRUPT_DISABLED_ = 0x0,
-                    ///  Interrupt enabled.
-                    INTERRUPT_ENABLED_ = 0x1,
-                },
-            },
-            ///  Capture interrupt for channel 0.
-            ICAP0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt disabled.
-                    INTERRUPT_DISABLED_ = 0x0,
-                    ///  Interrupt enabled.
-                    INTERRUPT_ENABLED_ = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Limit interrupt for channel 1.
-            ILIM1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt disabled.
-                    INTERRUPT_DISABLED_ = 0x0,
-                    ///  Interrupt enabled.
-                    INTERRUPT_ENABLED_ = 0x1,
-                },
-            },
-            ///  Match interrupt for channel 1.
-            IMAT1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt disabled.
-                    INTERRUPT_DISABLED_ = 0x0,
-                    ///  Interrupt enabled.
-                    INTERRUPT_ENABLED_ = 0x1,
-                },
-            },
-            ///  Capture interrupt for channel 1.
-            ICAP1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt disabled.
-                    INTERRUPT_DISABLED_ = 0x0,
-                    ///  Interrupt enabled.
-                    INTERRUPT_ENABLED_ = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Limit interrupt for channel 2.
-            ILIM2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt disabled.
-                    INTERRUPT_DISABLED_ = 0x0,
-                    ///  Interrupt enabled.
-                    INTERRUPT_ENABLED_ = 0x1,
-                },
-            },
-            ///  Match interrupt for channel 2.
-            IMAT2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt disabled.
-                    INTERRUPT_DISABLED_ = 0x0,
-                    ///  Interrupt enabled.
-                    INTERRUPT_ENABLED_ = 0x1,
-                },
-            },
-            ///  Capture interrupt for channel 2.
-            ICAP2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt disabled.
-                    INTERRUPT_DISABLED_ = 0x0,
-                    ///  Interrupt enabled.
-                    INTERRUPT_ENABLED_ = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u4,
-            ///  Fast abort interrupt.
-            ABORT: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Interrupt disabled.
-                    INTERRUPT_DISABLED_ = 0x0,
-                    ///  Interrupt enabled.
-                    INTERRUPT_ENABLED_ = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u16,
-        }),
-        ///  Interrupt Enable set address
-        INTEN_SET: mmio.Mmio(packed struct(u32) {
-            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
-            ILIM0_SET: u1,
-            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
-            IMAT0_SET: u1,
-            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
-            ICAP0_SET: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
-            ILIM1_SET: u1,
-            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
-            IMAT1_SET: u1,
-            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
-            ICAP1_SET: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            reserved9: u1,
-            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
-            ILIM2_SET: u1,
-            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
-            IMAT2_SET: u1,
-            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
-            ICAP2_SET: u1,
-            ///  Reserved.
-            RESERVED: u3,
-            ///  Writing a one sets the corresponding bit in INTEN, thus enabling the interrupt.
-            ABORT_SET: u1,
-            ///  Reserved.
-            RESERVED: u16,
-        }),
-        ///  Interrupt Enable clear address
-        INTEN_CLR: mmio.Mmio(packed struct(u32) {
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ILIM0_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            IMAT0_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ICAP0_CLR: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ILIM1_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            IMAT1_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ICAP1_CLR: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ILIM2_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            IMAT2_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ICAP2_CLR: u1,
-            ///  Reserved.
-            RESERVED: u4,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ABORT_CLR: u1,
-            ///  Reserved.
-            RESERVED: u16,
-        }),
-        ///  Count Control read address
-        CNTCON: mmio.Mmio(packed struct(u32) {
-            ///  Counter 0 rising edge mode, channel 0.
-            TC0MCI0_RE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A rising edge on MCI0 does not affect counter 0.
-                    A_RISING_EDGE_ON_MCI = 0x0,
-                    ///  If MODE0 is 1, counter 0 advances on a rising edge on MCI0.
-                    RISING = 0x1,
-                },
-            },
-            ///  Counter 0 falling edge mode, channel 0.
-            TC0MCI0_FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A falling edge on MCI0 does not affect counter 0.
-                    A_FALLING_EDGE_ON_MC = 0x0,
-                    ///  If MODE0 is 1, counter 0 advances on a falling edge on MCI0.
-                    FALLING = 0x1,
-                },
-            },
-            ///  Counter 0 rising edge mode, channel 1.
-            TC0MCI1_RE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A rising edge on MCI1 does not affect counter 0.
-                    A_RISING_EDGE_ON_MCI = 0x0,
-                    ///  If MODE0 is 1, counter 0 advances on a rising edge on MCI1.
-                    RISING = 0x1,
-                },
-            },
-            ///  Counter 0 falling edge mode, channel 1.
-            TC0MCI1_FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A falling edge on MCI1 does not affect counter 0.
-                    A_FALLING_EDGE_ON_MC = 0x0,
-                    ///  If MODE0 is 1, counter 0 advances on a falling edge on MCI1.
-                    FALLING = 0x1,
-                },
-            },
-            ///  Counter 0 rising edge mode, channel 2.
-            TC0MCI2_RE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A rising edge on MCI0 does not affect counter 0.
-                    A_RISING_EDGE_ON_MCI = 0x0,
-                    ///  If MODE0 is 1, counter 0 advances on a rising edge on MCI2.
-                    RISING = 0x1,
-                },
-            },
-            ///  Counter 0 falling edge mode, channel 2.
-            TC0MCI2_FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A falling edge on MCI0 does not affect counter 0.
-                    A_FALLING_EDGE_ON_MC = 0x0,
-                    ///  If MODE0 is 1, counter 0 advances on a falling edge on MCI2.
-                    FALLLING = 0x1,
-                },
-            },
-            ///  Counter 1 rising edge mode, channel 0.
-            TC1MCI0_RE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A rising edge on MCI0 does not affect counter 1.
-                    A_RISING_EDGE_ON_MCI = 0x0,
-                    ///  If MODE1 is 1, counter 1 advances on a rising edge on MCI0.
-                    RISING = 0x1,
-                },
-            },
-            ///  Counter 1 falling edge mode, channel 0.
-            TC1MCI0_FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A falling edge on MCI0 does not affect counter 1.
-                    A_FALLING_EDGE_ON_MC = 0x0,
-                    ///  If MODE1 is 1, counter 1 advances on a falling edge on MCI0.
-                    FALLING = 0x1,
-                },
-            },
-            ///  Counter 1 rising edge mode, channel 1.
-            TC1MCI1_RE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A rising edge on MCI1 does not affect counter 1.
-                    A_RISING_EDGE_ON_MCI = 0x0,
-                    ///  If MODE1 is 1, counter 1 advances on a rising edge on MCI1.
-                    RISING = 0x1,
-                },
-            },
-            ///  Counter 1 falling edge mode, channel 1.
-            TC1MCI1_FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A falling edge on MCI0 does not affect counter 1.
-                    A_FALLING_EDGE_ON_MC = 0x0,
-                    ///  If MODE1 is 1, counter 1 advances on a falling edge on MCI1.
-                    FALLING = 0x1,
-                },
-            },
-            ///  Counter 1 rising edge mode, channel 2.
-            TC1MCI2_RE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A rising edge on MCI2 does not affect counter 1.
-                    A_RISING_EDGE_ON_MCI = 0x0,
-                    ///  If MODE1 is 1, counter 1 advances on a rising edge on MCI2.
-                    RISING = 0x1,
-                },
-            },
-            ///  Counter 1 falling edge mode, channel 2.
-            TC1MCI2_FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A falling edge on MCI2 does not affect counter 1.
-                    A_FALLING_EDGE_ON_MC = 0x0,
-                    ///  If MODE1 is 1, counter 1 advances on a falling edge on MCI2.
-                    FALLING = 0x1,
-                },
-            },
-            ///  Counter 2 rising edge mode, channel 0.
-            TC2MCI0_RE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A rising edge on MCI0 does not affect counter 2.
-                    A_RISING_EDGE_ON_MCI = 0x0,
-                    ///  If MODE2 is 1, counter 2 advances on a rising edge on MCI0.
-                    RISING = 0x1,
-                },
-            },
-            ///  Counter 2 falling edge mode, channel 0.
-            TC2MCI0_FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A falling edge on MCI0 does not affect counter 2.
-                    A_FALLING_EDGE_ON_MC = 0x0,
-                    ///  If MODE2 is 1, counter 2 advances on a falling edge on MCI0.
-                    FALLING = 0x1,
-                },
-            },
-            ///  Counter 2 rising edge mode, channel 1.
-            TC2MCI1_RE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A rising edge on MCI1 does not affect counter 2.
-                    A_RISING_EDGE_ON_MCI = 0x0,
-                    ///  If MODE2 is 1, counter 2 advances on a rising edge on MCI1.
-                    RISING = 0x1,
-                },
-            },
-            ///  Counter 2 falling edge mode, channel 1.
-            TC2MCI1_FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A falling edge on MCI1 does not affect counter 2.
-                    A_FALLING_EDGE_ON_MC = 0x0,
-                    ///  If MODE2 is 1, counter 2 advances on a falling edge on MCI1.
-                    FALLING = 0x1,
-                },
-            },
-            ///  Counter 2 rising edge mode, channel 2.
-            TC2MCI2_RE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A rising edge on MCI2 does not affect counter 2.
-                    A_RISING_EDGE_ON_MCI = 0x0,
-                    ///  If MODE2 is 1, counter 2 advances on a rising edge on MCI2.
-                    RISIING = 0x1,
-                },
-            },
-            ///  Counter 2 falling edge mode, channel 2.
-            TC2MCI2_FE: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  A falling edge on MCI2 does not affect counter 2.
-                    A_FALLING_EDGE_ON_MC = 0x0,
-                    ///  If MODE2 is 1, counter 2 advances on a falling edge on MCI2.
-                    FALLING = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u11,
-            ///  Channel 0 counter/timer mode.
-            CNTR0: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Channel 0 is in timer mode.
-                    CHANNEL_0_IS_IN_TIME = 0x0,
-                    ///  Channel 0 is in counter mode.
-                    CHANNEL_0_IS_IN_COUN = 0x1,
-                },
-            },
-            ///  Channel 1 counter/timer mode.
-            CNTR1: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Channel 1 is in timer mode.
-                    CHANNEL_1_IS_IN_TIME = 0x0,
-                    ///  Channel 1 is in counter mode.
-                    CHANNEL_1_IS_IN_COUN = 0x1,
-                },
-            },
-            ///  Channel 2 counter/timer mode.
-            CNTR2: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Channel 2 is in timer mode.
-                    CHANNEL_2_IS_IN_TIME = 0x0,
-                    ///  Channel 2 is in counter mode.
-                    CHANNEL_2_IS_IN_COUN = 0x1,
-                },
-            },
-        }),
-        ///  Count Control set address
-        CNTCON_SET: mmio.Mmio(packed struct(u32) {
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC0MCI0_RE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC0MCI0_FE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC0MCI1_RE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC0MCI1_FE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC0MCI2_RE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC0MCI2_FE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC1MCI0_RE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC1MCI0_FE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC1MCI1_RE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC1MCI1_FE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC1MCI2_RE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC1MCI2_FE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC2MCI0_RE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC2MCI0_FE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC2MCI1_RE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC2MCI1_FE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC2MCI2_RE_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            TC2MCI2_FE_SET: u1,
-            ///  Reserved.
-            RESERVED: u11,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            CNTR0_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            CNTR1_SET: u1,
-            ///  Writing a one sets the corresponding bit in the CNTCON register.
-            CNTR2_SET: u1,
-        }),
-        ///  Count Control clear address
-        CNTCON_CLR: mmio.Mmio(packed struct(u32) {
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC0MCI0_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC0MCI0_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC0MCI1_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC0MCI1_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC0MCI2_RE: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC0MCI2_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC1MCI0_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC1MCI0_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC1MCI1_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC1MCI1_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC1MCI2_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC1MCI2_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC2MCI0_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC2MCI0_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC2MCI1_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC2MCI1_FE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC2MCI2_RE_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            TC2MCI2_FE_CLR: u1,
-            ///  Reserved.
-            RESERVED: u11,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            CNTR0_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            CNTR1_CLR: u1,
-            ///  Writing a one clears the corresponding bit in the CNTCON register.
-            CNTR2_CLR: u1,
-        }),
-        ///  Interrupt flags read address
-        INTF: mmio.Mmio(packed struct(u32) {
-            ///  Limit interrupt flag for channel 0.
-            ILIM0_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
-                    THIS_INTERRUPT_SOURC = 0x0,
-                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
-                    IF_THE_CORRESPONDING = 0x1,
-                },
-            },
-            ///  Match interrupt flag for channel 0.
-            IMAT0_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
-                    THIS_INTERRUPT_SOURC = 0x0,
-                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
-                    IF_THE_CORRESPONDING = 0x1,
-                },
-            },
-            ///  Capture interrupt flag for channel 0.
-            ICAP0_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
-                    THIS_INTERRUPT_SOURC = 0x0,
-                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
-                    IF_THE_CORRESPONDING = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Limit interrupt flag for channel 1.
-            ILIM1_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
-                    THIS_INTERRUPT_SOURC = 0x0,
-                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
-                    IF_THE_CORRESPONDING = 0x1,
-                },
-            },
-            ///  Match interrupt flag for channel 1.
-            IMAT1_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
-                    THIS_INTERRUPT_SOURC = 0x0,
-                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
-                    IF_THE_CORRESPONDING = 0x1,
-                },
-            },
-            ///  Capture interrupt flag for channel 1.
-            ICAP1_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
-                    THIS_INTERRUPT_SOURC = 0x0,
-                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
-                    IF_THE_CORRESPONDING = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Limit interrupt flag for channel 2.
-            ILIM2_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
-                    THIS_INTERRUPT_SOURC = 0x0,
-                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
-                    IF_THE_CORRESPONDING = 0x1,
-                },
-            },
-            ///  Match interrupt flag for channel 2.
-            IMAT2_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
-                    THIS_INTERRUPT_SOURC = 0x0,
-                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
-                    IF_THE_CORRESPONDING = 0x1,
-                },
-            },
-            ///  Capture interrupt flag for channel 2.
-            ICAP2_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
-                    THIS_INTERRUPT_SOURC = 0x0,
-                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
-                    IF_THE_CORRESPONDING = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u4,
-            ///  Fast abort interrupt flag.
-            ABORT_F: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This interrupt source is not contributing to the MCPWM interrupt request.
-                    THIS_INTERRUPT_SOURC = 0x0,
-                    ///  If the corresponding bit in INTEN is 1, the MCPWM module is asserting its interrupt request to the Interrupt Controller.
-                    IF_THE_CORRESPONDING = 0x1,
-                },
-            },
-            ///  Reserved.
-            RESERVED: u16,
-        }),
-        ///  Interrupt flags set address
-        INTF_SET: mmio.Mmio(packed struct(u32) {
-            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
-            ILIM0_F_SET: u1,
-            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
-            IMAT0_F_SET: u1,
-            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
-            ICAP0_F_SET: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
-            ILIM1_F_SET: u1,
-            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
-            IMAT1_F_SET: u1,
-            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
-            ICAP1_F_SET: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
-            ILIM2_F_SET: u1,
-            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
-            IMAT2_F_SET: u1,
-            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
-            ICAP2_F_SET: u1,
-            ///  Reserved.
-            RESERVED: u4,
-            ///  Writing a one sets the corresponding bit in the INTF register, thus possibly simulating hardware interrupt.
-            ABORT_F_SET: u1,
-            ///  Reserved.
-            RESERVED: u16,
-        }),
-        ///  Interrupt flags clear address
-        INTF_CLR: mmio.Mmio(packed struct(u32) {
-            ///  Writing a one clears the corresponding bit in the INTF register, thus clearing the corresponding interrupt request.
-            ILIM0_F_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            IMAT0_F_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ICAP0_F_CLR: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ILIM1_F_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            IMAT1_F_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ICAP1_F_CLR: u1,
-            ///  Reserved.
-            RESERVED: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ILIM2_F_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            IMAT2_F_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ICAP2_F_CLR: u1,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            RESERVED: u4,
-            ///  Writing a one clears the corresponding bit in INTEN, thus disabling the interrupt.
-            ABORT_F_CLR: u1,
-            ///  Reserved.
-            RESERVED: u16,
-        }),
-        ///  Capture clear address
-        CAP_CLR: mmio.Mmio(packed struct(u32) {
-            ///  Writing a 1 to this bit clears the CAP0 register.
-            CAP_CLR0: u1,
-            ///  Writing a 1 to this bit clears the CAP1 register.
-            CAP_CLR1: u1,
-            ///  Writing a 1 to this bit clears the CAP2 register.
-            CAP_CLR2: u1,
-            ///  Reserved
-            RESERVED: u29,
-        }),
-    };
-
-    ///  Repetitive Interrupt Timer (RIT)
-    pub const RITIMER = extern struct {
-        ///  Compare register
-        COMPVAL: mmio.Mmio(packed struct(u32) {
-            ///  Compare register. Holds the compare value which is compared to the counter.
-            RICOMP: u32,
-        }),
-        ///  Mask register. This register holds the 32-bit mask value. A 1 written to any bit will force a compare on the corresponding bit of the counter and compare register.
-        MASK: mmio.Mmio(packed struct(u32) {
-            ///  Mask register. This register holds the 32-bit mask value. A one written to any bit overrides the result of the comparison for the corresponding bit of the counter and compare register (causes the comparison of the register bits to be always true).
-            RIMASK: u32,
-        }),
-        ///  Control register.
-        CTRL: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt flag
-            RITINT: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  This bit is set to 1 by hardware whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. Writing a 1 to this bit will clear it to 0. Writing a 0 has no effect.
-                    THIS_BIT_IS_SET_TO_1 = 0x1,
-                    ///  The counter value does not equal the masked compare value.
-                    THE_COUNTER_VALUE_DO = 0x0,
-                },
-            },
-            ///  Timer enable clear
-            RITENCLR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The timer will be cleared to 0 whenever the counter value equals the masked compare value specified by the contents of RICOMPVAL and RIMASK registers. This will occur on the same clock that sets the interrupt flag.
-                    THE_TIMER_WILL_BE_CL = 0x1,
-                    ///  The timer will not be cleared to 0.
-                    THE_TIMER_WILL_NOT_B = 0x0,
-                },
-            },
-            ///  Timer enable for debug
-            RITENBR: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  The timer is halted when the processor is halted for debugging.
-                    THE_TIMER_IS_HALTED_ = 0x1,
-                    ///  Debug has no effect on the timer operation.
-                    DEBUG_HAS_NO_EFFECT_ = 0x0,
-                },
-            },
-            ///  Timer enable.
-            RITEN: packed union {
-                raw: u1,
-                value: enum(u1) {
-                    ///  Timer enabled. This can be overruled by a debug halt if enabled in bit 2.
-                    TIMER_ENABLED_THIS_ = 0x1,
-                    ///  Timer disabled.
-                    TIMER_DISABLED_ = 0x0,
-                },
-            },
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        ///  32-bit counter
-        COUNTER: mmio.Mmio(packed struct(u32) {
-            ///  32-bit up counter. Counts continuously unless RITEN bit in RICTRL register is cleared or debug mode is entered (if enabled by the RITNEBR bit in RICTRL). Can be loaded to any value in software.
-            RICOUNTER: u32,
-        }),
-    };
-
-    ///  I2S interface
-    pub const I2S = extern struct {
-        ///  I2S Digital Audio Output Register. Contains control bits for the I2S transmit channel.
-        DAO: mmio.Mmio(packed struct(u32) {
-            ///  Selects the number of bytes in data as follows:
-            WORDWIDTH: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  8-bit data
-                    @"8_BIT_DATA" = 0x0,
-                    ///  16-bit data
-                    @"16_BIT_DATA" = 0x1,
-                    ///  32-bit data
-                    @"32_BIT_DATA" = 0x3,
-                    _,
-                },
-            },
-            ///  When 1, data is of monaural format. When 0, the data is in stereo format.
-            MONO: u1,
-            ///  When 1, disables accesses on FIFOs, places the transmit channel in mute mode.
-            STOP: u1,
-            ///  When 1, asynchronously resets the transmit channel and FIFO.
-            RESET: u1,
-            ///  When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with TXMODE.
-            WS_SEL: u1,
-            ///  Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.
-            WS_HALFPERIOD: u9,
-            ///  When 1, the transmit channel sends only zeroes.
-            MUTE: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u16,
-        }),
-        ///  I2S Digital Audio Input Register. Contains control bits for the I2S receive channel.
-        DAI: mmio.Mmio(packed struct(u32) {
-            ///  Selects the number of bytes in data as follows:
-            WORDWIDTH: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  8-bit data
-                    @"8_BIT_DATA" = 0x0,
-                    ///  16-bit data
-                    @"16_BIT_DATA" = 0x1,
-                    ///  32-bit data
-                    @"32_BIT_DATA" = 0x3,
-                    _,
-                },
-            },
-            ///  When 1, data is of monaural format. When 0, the data is in stereo format.
-            MONO: u1,
-            ///  When 1, disables accesses on FIFOs, places the transmit channel in mute mode.
-            STOP: u1,
-            ///  When 1, asynchronously reset the transmit channel and FIFO.
-            RESET: u1,
-            ///  When 0, the interface is in master mode. When 1, the interface is in slave mode. See Section 34.7.2 for a summary of useful combinations for this bit with RXMODE.
-            WS_SEL: u1,
-            ///  Word select half period minus 1, i.e. WS 64clk period -> ws_halfperiod = 31.
-            WS_HALFPERIOD: u9,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u17,
-        }),
-        ///  I2S Transmit FIFO. Access register for the 8 x 32-bit transmitter FIFO.
-        TXFIFO: mmio.Mmio(packed struct(u32) {
-            ///  8 x 32-bit transmit FIFO.
-            I2STXFIFO: u32,
-        }),
-        ///  I2S Receive FIFO. Access register for the 8 x 32-bit receiver FIFO.
-        RXFIFO: mmio.Mmio(packed struct(u32) {
-            ///  8 x 32-bit transmit FIFO.
-            I2SRXFIFO: u32,
-        }),
-        ///  I2S Status Feedback Register. Contains status information about the I2S interface.
-        STATE: mmio.Mmio(packed struct(u32) {
-            ///  This bit reflects the presence of Receive Interrupt or Transmit Interrupt. This is determined by comparing the current FIFO levels to the rx_depth_irq and tx_depth_irq fields in the IRQ register.
-            IRQ: u1,
-            ///  This bit reflects the presence of Receive or Transmit DMA Request 1. This is determined by comparing the current FIFO levels to the rx_depth_dma1 and tx_depth_dma1 fields in the DMA1 register.
-            DMAREQ1: u1,
-            ///  This bit reflects the presence of Receive or Transmit DMA Request 2. This is determined by comparing the current FIFO levels to the rx_depth_dma2 and tx_depth_dma2 fields in the DMA2 register.
-            DMAREQ2: u1,
-            ///  Reserved.
-            RESERVED: u5,
-            ///  Reflects the current level of the Receive FIFO.
-            RX_LEVEL: u4,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u4,
-            ///  Reflects the current level of the Transmit FIFO.
-            TX_LEVEL: u4,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u12,
-        }),
-        ///  I2S DMA Configuration Register 1. Contains control information for DMA request 1.
-        DMA1: mmio.Mmio(packed struct(u32) {
-            ///  When 1, enables DMA1 for I2S receive.
-            RX_DMA1_ENABLE: u1,
-            ///  When 1, enables DMA1 for I2S transmit.
-            TX_DMA1_ENABLE: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u6,
-            ///  Set the FIFO level that triggers a receive DMA request on DMA1.
-            RX_DEPTH_DMA1: u4,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u4,
-            ///  Set the FIFO level that triggers a transmit DMA request on DMA1.
-            TX_DEPTH_DMA1: u4,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u12,
-        }),
-        ///  I2S DMA Configuration Register 2. Contains control information for DMA request 2.
-        DMA2: mmio.Mmio(packed struct(u32) {
-            ///  When 1, enables DMA1 for I2S receive.
-            RX_DMA2_ENABLE: u1,
-            ///  When 1, enables DMA1 for I2S transmit.
-            TX_DMA2_ENABLE: u1,
-            ///  Reserved.
-            RESERVED: u6,
-            ///  Set the FIFO level that triggers a receive DMA request on DMA2.
-            RX_DEPTH_DMA2: u4,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u4,
-            ///  Set the FIFO level that triggers a transmit DMA request on DMA2.
-            TX_DEPTH_DMA2: u4,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u12,
-        }),
-        ///  I2S Interrupt Request Control Register. Contains bits that control how the I2S interrupt request is generated.
-        IRQ: mmio.Mmio(packed struct(u32) {
-            ///  When 1, enables I2S receive interrupt.
-            RX_IRQ_ENABLE: u1,
-            ///  When 1, enables I2S transmit interrupt.
-            TX_IRQ_ENABLE: u1,
-            ///  Reserved.
-            RESERVED: u6,
-            ///  Set the FIFO level on which to create an irq request.
-            RX_DEPTH_IRQ: u4,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u4,
-            ///  Set the FIFO level on which to create an irq request.
-            TX_DEPTH_IRQ: u4,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u12,
-        }),
-        ///  I2S Transmit MCLK divider. This register determines the I2S TX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.
-        TXRATE: mmio.Mmio(packed struct(u32) {
-            ///  I2S transmit MCLK rate denominator. This value is used to divide PCLK to produce the transmit MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.
-            Y_DIVIDER: u8,
-            ///  I2S transmit MCLK rate numerator. This value is used to multiply PCLK by to produce the transmit MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.
-            X_DIVIDER: u8,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u16,
-        }),
-        ///  I2S Receive MCLK divider. This register determines the I2S RX MCLK rate by specifying the value to divide PCLK by in order to produce MCLK.
-        RXRATE: mmio.Mmio(packed struct(u32) {
-            ///  I2S receive MCLK rate denominator. This value is used to divide PCLK to produce the receive MCLK. Eight bits of fractional divide supports a wide range of possibilities. A value of 0 stops the clock.
-            Y_DIVIDER: u8,
-            ///  I2S receive MCLK rate numerator. This value is used to multiply PCLK by to produce the receive MCLK. A value of 0 stops the clock. Eight bits of fractional divide supports a wide range of possibilities. Note: the resulting ratio X/Y is divided by 2.
-            X_DIVIDER: u8,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u16,
-        }),
-        ///  I2S Transmit bit rate divider. This register determines the I2S transmit bit rate by specifying the value to divide TX_MCLK by in order to produce the transmit bit clock.
-        TXBITRATE: mmio.Mmio(packed struct(u32) {
-            ///  I2S transmit bit rate. This value plus one is used to divide TX_MCLK to produce the transmit bit clock.
-            TX_BITRATE: u6,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u26,
-        }),
-        ///  I2S Receive bit rate divider. This register determines the I2S receive bit rate by specifying the value to divide RX_MCLK by in order to produce the receive bit clock.
-        RXBITRATE: mmio.Mmio(packed struct(u32) {
-            ///  I2S receive bit rate. This value plus one is used to divide RX_MCLK to produce the receive bit clock.
-            RX_BITRATE: u6,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u26,
-        }),
-        ///  I2S Transmit mode control.
-        TXMODE: mmio.Mmio(packed struct(u32) {
-            ///  Clock source selection for the transmit bit clock divider.
-            TXCLKSEL: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Select the TX fractional rate divider clock output as the source
-                    SELECT_THE_TX_FRACTI = 0x0,
-                    ///  Select the RX_MCLK signal as the TX_MCLK clock source
-                    SELECT_THE_RX_MCLK_S = 0x2,
-                    _,
-                },
-            },
-            ///  Transmit 4-pin mode selection. When 1, enables 4-pin mode.
-            TX4PIN: u1,
-            ///  Enable for the TX_MCLK output. When 0, output of TX_MCLK is not enabled. When 1, output of TX_MCLK is enabled.
-            TXMCENA: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-        ///  I2S Receive mode control.
-        RXMODE: mmio.Mmio(packed struct(u32) {
-            ///  Clock source selection for the receive bit clock divider.
-            RXCLKSEL: packed union {
-                raw: u2,
-                value: enum(u2) {
-                    ///  Select the RX fractional rate divider clock output as the source
-                    SELECT_THE_RX_FRACTI = 0x0,
-                    ///  Select the TX_MCLK signal as the RX_MCLK clock source
-                    SELECT_THE_TX_MCLK_S = 0x2,
-                    _,
-                },
-            },
-            ///  Receive 4-pin mode selection. When 1, enables 4-pin mode.
-            RX4PIN: u1,
-            ///  Enable for the RX_MCLK output. When 0, output of RX_MCLK is not enabled. When 1, output of RX_MCLK is enabled.
-            RXMCENA: u1,
-            ///  Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.
-            RESERVED: u28,
-        }),
-    };
-};
diff --git a/src/hals/LPC176x5x.zig b/src/hals/LPC176x5x.zig
index 8202d52ba..823545fdf 100644
--- a/src/hals/LPC176x5x.zig
+++ b/src/hals/LPC176x5x.zig
@@ -63,7 +63,7 @@ pub fn parse_pin(comptime spec: []const u8) type {
 
 pub fn route_pin(comptime pin: type, function: PinTarget) void {
     var val = pin.regs.pinsel_reg.read();
-    @field(val, pin.regs.pinsel_field) = @enumToInt(function);
+    @field(val, pin.regs.pinsel_field) = @intFromEnum(function);
     pin.regs.pinsel_reg.write(val);
 }
 
@@ -138,19 +138,19 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
             switch (index) {
                 0 => {
                     SYSCON.PCONP.modify(.{ .PCUART0 = 1 });
-                    SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = @enumToInt(uart.CClkDiv.four) });
+                    SYSCON.PCLKSEL0.modify(.{ .PCLK_UART0 = @intFromEnum(uart.CClkDiv.four) });
                 },
                 1 => {
                     SYSCON.PCONP.modify(.{ .PCUART1 = 1 });
-                    SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = @enumToInt(uart.CClkDiv.four) });
+                    SYSCON.PCLKSEL0.modify(.{ .PCLK_UART1 = @intFromEnum(uart.CClkDiv.four) });
                 },
                 2 => {
                     SYSCON.PCONP.modify(.{ .PCUART2 = 1 });
-                    SYSCON.PCLKSEL1.modify(.{ .PCLK_UART2 = @enumToInt(uart.CClkDiv.four) });
+                    SYSCON.PCLKSEL1.modify(.{ .PCLK_UART2 = @intFromEnum(uart.CClkDiv.four) });
                 },
                 3 => {
                     SYSCON.PCONP.modify(.{ .PCUART3 = 1 });
-                    SYSCON.PCLKSEL1.modify(.{ .PCLK_UART3 = @enumToInt(uart.CClkDiv.four) });
+                    SYSCON.PCLKSEL1.modify(.{ .PCLK_UART3 = @intFromEnum(uart.CClkDiv.four) });
                 },
                 else => unreachable,
             }
@@ -158,10 +158,10 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
 
             UARTn.LCR.modify(.{
                 // 8N1
-                .WLS = @enumToInt(config.data_bits),
-                .SBS = @enumToInt(config.stop_bits),
+                .WLS = @intFromEnum(config.data_bits),
+                .SBS = @intFromEnum(config.stop_bits),
                 .PE = if (config.parity != null) @as(u1, 1) else @as(u1, 0),
-                .PS = if (config.parity) |p| @enumToInt(p) else @enumToInt(uart.Parity.odd),
+                .PS = if (config.parity) |p| @intFromEnum(p) else @intFromEnum(uart.Parity.odd),
                 .BC = 0,
                 .DLAB = 1,
             });
@@ -180,8 +180,8 @@ pub fn Uart(comptime index: usize, comptime pins: micro.uart.Pins) type {
 
             const regval = std.math.cast(u16, divider) orelse return error.UnsupportedBaudRate;
 
-            UARTn.DLL.modify(.{ .DLLSB = @truncate(u8, regval >> 0x00) });
-            UARTn.DLM.modify(.{ .DLMSB = @truncate(u8, regval >> 0x08) });
+            UARTn.DLL.modify(.{ .DLLSB = @as(u8, @truncate(regval >> 0x00)) });
+            UARTn.DLM.modify(.{ .DLMSB = @as(u8, @truncate(regval >> 0x08)) });
 
             UARTn.LCR.modify(.{ .DLAB = 0 });
 
diff --git a/src/tools/patchelf.zig b/src/tools/patchelf.zig
new file mode 100644
index 000000000..8961bf8b6
--- /dev/null
+++ b/src/tools/patchelf.zig
@@ -0,0 +1,66 @@
+const std = @import("std");
+
+pub fn main() !u8 {
+    const argv = try std.process.argsAlloc(std.heap.page_allocator);
+    defer std.process.argsFree(std.heap.page_allocator, argv);
+
+    if (argv.len != 3) {
+        std.log.err("usage: lpc-patchelf  ", .{});
+        return 1;
+    }
+
+    const input_file_name = argv[1];
+    const output_file_name = argv[2];
+
+    try std.fs.Dir.copyFile(
+        std.fs.cwd(),
+        input_file_name,
+        std.fs.cwd(),
+        output_file_name,
+        .{},
+    );
+
+    var file = try std.fs.cwd().openFile(output_file_name, .{ .mode = .read_write });
+    defer file.close();
+
+    const header = try std.elf.Header.read(file);
+
+    var iter = header.program_header_iterator(file);
+    while (try iter.next()) |phdr| {
+        if (phdr.p_type != std.elf.PT_LOAD) {
+            continue;
+        }
+
+        if (phdr.p_paddr != 0) {
+            // std.log.warn("LOAD program header is not located at address 0x00000000!", .{});
+            break;
+        }
+
+        const boot_sector_items = 8;
+        const boot_sector_size = @sizeOf([boot_sector_items]u32);
+
+        if (phdr.p_filesz < boot_sector_size) {
+            std.log.warn("boot header is too small! Expected {} bytes, but sector only has {} bytes!", .{
+                boot_sector_size,
+                phdr.p_filesz,
+            });
+            continue;
+        }
+
+        try file.seekTo(phdr.p_offset);
+        var reader = file.reader();
+        var writer = file.writer();
+
+        var checksum: u32 = 0;
+
+        var i: usize = 0;
+        while (i < boot_sector_items - 1) : (i += 1) {
+            const item = try reader.readIntLittle(u32);
+            checksum -%= item;
+        }
+
+        try writer.writeIntLittle(u32, checksum);
+    }
+
+    return 0;
+}

From 7b528f927119682e50d2501e2178169f6bde64f3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Fri, 22 Sep 2023 09:03:54 +0200
Subject: [PATCH 209/286] Update to MicroZig Gen 2 build interface. (#21)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-authored-by: Felix "xq" Queißner 
---
 .gitmodules             |     3 -
 build.zig               |   120 +-
 deps/microzig           |     1 -
 src/boards.zig          |    13 -
 src/chips.zig           |    26 -
 src/chips/GD32VF103.zig | 12849 --------------------------------------
 6 files changed, 88 insertions(+), 12924 deletions(-)
 delete mode 160000 deps/microzig
 delete mode 100644 src/boards.zig
 delete mode 100644 src/chips.zig
 delete mode 100644 src/chips/GD32VF103.zig

diff --git a/.gitmodules b/.gitmodules
index 32e895ccb..e69de29bb 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -1,3 +0,0 @@
-[submodule "deps/microzig"]
-	path = deps/microzig
-	url = https://github.com/ZigEmbeddedGroup/microzig.git
diff --git a/build.zig b/build.zig
index 56ed4e58a..61f41a4ca 100644
--- a/build.zig
+++ b/build.zig
@@ -1,38 +1,94 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/build.zig");
 
-pub const boards = @import("src/boards.zig");
-pub const chips = @import("src/chips.zig");
+fn path(comptime suffix: []const u8) std.Build.LazyPath {
+    return .{
+        .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
+    };
+}
 
-pub fn build(b: *std.build.Builder) void {
-    const optimize = b.standardOptimizeOption(.{});
-    inline for (@typeInfo(boards).Struct.decls) |decl| {
-        if (!decl.is_pub)
-            continue;
-
-        const exe = microzig.addEmbeddedExecutable(b, .{
-            .name = @field(boards, decl.name).name ++ ".minimal",
-            .source_file = .{
-                .path = "test/programs/minimal.zig",
+const hal = .{
+    .source_file = path("/src/hals/GD32VF103.zig"),
+};
+
+pub const chips = struct {
+    pub const gd32vf103xb = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "GD32VF103",
+            .cpu = .riscv32_imac,
+            .memory_regions = &.{
+                .{ .offset = 0x08000000, .length = 128 * 1024, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 32 * 1024, .kind = .ram },
             },
-            .backing = .{ .board = @field(boards, decl.name) },
-            .optimize = optimize,
-        });
-        exe.installArtifact(b);
-    }
-
-    inline for (@typeInfo(chips).Struct.decls) |decl| {
-        if (!decl.is_pub)
-            continue;
-
-        const exe = microzig.addEmbeddedExecutable(b, .{
-            .name = @field(chips, decl.name).name ++ ".minimal",
-            .source_file = .{
-                .path = "test/programs/minimal.zig",
+            .register_definition = .{
+                .json = path("/src/chips/GD32VF103.json"),
             },
-            .backing = .{ .chip = @field(chips, decl.name) },
-            .optimize = optimize,
-        });
-        exe.installArtifact(b);
-    }
+        },
+        .hal = hal,
+    };
+
+    pub const gd32vf103x8 = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "GD32VF103",
+            .cpu = .riscv32_imac,
+            .memory_regions = &.{
+                .{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram },
+            },
+            .register_definition = .{
+                .json = path("/src/chips/GD32VF103.json"),
+            },
+        },
+        .hal = hal,
+    };
+};
+
+pub const boards = struct {
+    pub const sipeed = struct {
+        pub const longan_nano = .{
+            .preferred_format = .elf,
+            .chip = chips.gd32vf103xb.chip,
+            .hal = hal,
+            .board = .{
+                .name = "Longan Nano",
+                .url = "https://longan.sipeed.com/en/",
+                .source_file = path("/src/boards/longan_nano.zig"),
+            },
+        };
+    };
+};
+
+pub fn build(b: *std.build.Builder) void {
+    _ = b;
+    // const optimize = b.standardOptimizeOption(.{});
+    // inline for (@typeInfo(boards).Struct.decls) |decl| {
+    //     if (!decl.is_pub)
+    //         continue;
+
+    //     const exe = microzig.addEmbeddedExecutable(b, .{
+    //         .name = @field(boards, decl.name).name ++ ".minimal",
+    //         .source_file = .{
+    //             .path = "test/programs/minimal.zig",
+    //         },
+    //         .backing = .{ .board = @field(boards, decl.name) },
+    //         .optimize = optimize,
+    //     });
+    //     exe.installArtifact(b);
+    // }
+
+    // inline for (@typeInfo(chips).Struct.decls) |decl| {
+    //     if (!decl.is_pub)
+    //         continue;
+
+    //     const exe = microzig.addEmbeddedExecutable(b, .{
+    //         .name = @field(chips, decl.name).name ++ ".minimal",
+    //         .source_file = .{
+    //             .path = "test/programs/minimal.zig",
+    //         },
+    //         .backing = .{ .chip = @field(chips, decl.name) },
+    //         .optimize = optimize,
+    //     });
+    //     exe.installArtifact(b);
+    // }
 }
diff --git a/deps/microzig b/deps/microzig
deleted file mode 160000
index 9392fe0f7..000000000
--- a/deps/microzig
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791
diff --git a/src/boards.zig b/src/boards.zig
deleted file mode 100644
index 264bfeef9..000000000
--- a/src/boards.zig
+++ /dev/null
@@ -1,13 +0,0 @@
-const std = @import("std");
-const micro = @import("../deps/microzig/build.zig");
-const chips = @import("chips.zig");
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse ".";
-}
-
-pub const longan_nano = micro.Board{
-    .name = "Longan Nano",
-    .source = .{ .path = root_dir() ++ "/boards/longan_nano.zig" },
-    .chip = chips.gd32vf103xb,
-};
diff --git a/src/chips.zig b/src/chips.zig
deleted file mode 100644
index 2822bd7cd..000000000
--- a/src/chips.zig
+++ /dev/null
@@ -1,26 +0,0 @@
-const std = @import("std");
-const micro = @import("../deps/microzig/build.zig");
-const Chip = micro.Chip;
-const MemoryRegion = micro.MemoryRegion;
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
-
-pub const gd32vf103xb = Chip.from_standard_paths(root_dir(), .{
-    .name = "GD32VF103",
-    .cpu = micro.cpus.riscv32_imac,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x08000000, .length = 128 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 32 * 1024, .kind = .ram },
-    },
-});
-
-pub const gd32vf103x8 = Chip.from_standard_paths(root_dir(), .{
-    .name = "GD32VF103",
-    .cpu = micro.cpus.riscv32_imac,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram },
-    },
-});
diff --git a/src/chips/GD32VF103.zig b/src/chips/GD32VF103.zig
deleted file mode 100644
index 77618b43e..000000000
--- a/src/chips/GD32VF103.zig
+++ /dev/null
@@ -1,12849 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    ///  GD32VF103 RISC-V Microcontroller based device
-    pub const GD32VF103 = struct {
-        pub const properties = struct {
-            pub const @"cpu.nvic_prio_bits" = "4";
-            pub const @"cpu.mpu" = "0";
-            pub const @"cpu.fpu" = "0";
-            pub const @"cpu.revision" = "r2p1";
-            pub const @"cpu.vendor_systick_config" = "0";
-            pub const license =
-                \\
-                \\    Copyright 2019 Sipeed Co.,Ltd.
-                \\  
-                \\    Licensed under the Apache License, Version 2.0 (the "License");
-                \\    you may not use this file except in compliance with the License.
-                \\    You may obtain a copy of the License at
-                \\
-                \\        http://www.apache.org/licenses/LICENSE-2.0
-                \\
-                \\    Unless required by applicable law or agreed to in writing, software
-                \\    distributed under the License is distributed on an "AS IS" BASIS,
-                \\    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-                \\    See the License for the specific language governing permissions and
-                \\    limitations under the License.
-                \\
-            ;
-            pub const @"cpu.name" = "CM3";
-            pub const @"cpu.endian" = "little";
-        };
-
-        pub const VectorTable = extern struct {
-            const Handler = micro.interrupt.Handler;
-            const unhandled = micro.interrupt.unhandled;
-
-            initial_stack_pointer: u32,
-            Reset: Handler = unhandled,
-            NMI: Handler = unhandled,
-            HardFault: Handler = unhandled,
-            MemManageFault: Handler = unhandled,
-            BusFault: Handler = unhandled,
-            UsageFault: Handler = unhandled,
-            reserved5: [4]u32 = undefined,
-            SVCall: Handler = unhandled,
-            DebugMonitor: Handler = unhandled,
-            reserved11: [1]u32 = undefined,
-            PendSV: Handler = unhandled,
-            SysTick: Handler = unhandled,
-            WWDGT: Handler = unhandled,
-            reserved15: [20]u32 = undefined,
-            Tamper: Handler = unhandled,
-            RTC: Handler = unhandled,
-            FMC: Handler = unhandled,
-            RCU: Handler = unhandled,
-            EXTI_Line0: Handler = unhandled,
-            EXTI_Line1: Handler = unhandled,
-            EXTI_Line2: Handler = unhandled,
-            EXTI_Line3: Handler = unhandled,
-            EXTI_Line4: Handler = unhandled,
-            DMA0_Channel0: Handler = unhandled,
-            DMA0_Channel1: Handler = unhandled,
-            DMA0_Channel2: Handler = unhandled,
-            DMA0_Channel3: Handler = unhandled,
-            DMA0_Channel4: Handler = unhandled,
-            DMA0_Channel5: Handler = unhandled,
-            DMA0_Channel6: Handler = unhandled,
-            ADC0_1: Handler = unhandled,
-            CAN0_TX: Handler = unhandled,
-            CAN0_RX0: Handler = unhandled,
-            CAN0_RX1: Handler = unhandled,
-            CAN0_EWMC: Handler = unhandled,
-            EXTI_line9_5: Handler = unhandled,
-            TIMER0_BRK: Handler = unhandled,
-            TIMER0_UP: Handler = unhandled,
-            TIMER0_TRG_CMT: Handler = unhandled,
-            TIMER0_Channel: Handler = unhandled,
-            TIMER1: Handler = unhandled,
-            TIMER2: Handler = unhandled,
-            TIMER3: Handler = unhandled,
-            I2C0_EV: Handler = unhandled,
-            I2C0_ER: Handler = unhandled,
-            I2C1_EV: Handler = unhandled,
-            I2C1_ER: Handler = unhandled,
-            SPI0: Handler = unhandled,
-            SPI1: Handler = unhandled,
-            USART0: Handler = unhandled,
-            USART1: Handler = unhandled,
-            USART2: Handler = unhandled,
-            EXTI_line15_10: Handler = unhandled,
-            RTC_Alarm: Handler = unhandled,
-            USBFS_WKUP: Handler = unhandled,
-            reserved76: [7]u32 = undefined,
-            TIMER4: Handler = unhandled,
-            SPI2: Handler = unhandled,
-            UART3: Handler = unhandled,
-            UART4: Handler = unhandled,
-            TIMER5: Handler = unhandled,
-            TIMER6: Handler = unhandled,
-            DMA1_Channel0: Handler = unhandled,
-            DMA1_Channel1: Handler = unhandled,
-            DMA1_Channel2: Handler = unhandled,
-            DMA1_Channel3: Handler = unhandled,
-            DMA1_Channel4: Handler = unhandled,
-            reserved94: [2]u32 = undefined,
-            CAN1_TX: Handler = unhandled,
-            CAN1_RX0: Handler = unhandled,
-            CAN1_RX1: Handler = unhandled,
-            CAN1_EWMC: Handler = unhandled,
-            USBFS: Handler = unhandled,
-        };
-
-        pub const peripherals = struct {
-            ///  General-purpose-timers
-            pub const TIMER1 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000000);
-            ///  General-purpose-timers
-            pub const TIMER2 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000400);
-            ///  General-purpose-timers
-            pub const TIMER3 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000800);
-            ///  General-purpose-timers
-            pub const TIMER4 = @intToPtr(*volatile types.peripherals.TIMER1, 0x40000c00);
-            ///  Basic-timers
-            pub const TIMER5 = @intToPtr(*volatile types.peripherals.TIMER5, 0x40001000);
-            ///  Basic-timers
-            pub const TIMER6 = @intToPtr(*volatile types.peripherals.TIMER5, 0x40001400);
-            ///  Real-time clock
-            pub const RTC = @intToPtr(*volatile types.peripherals.RTC, 0x40002800);
-            ///  Window watchdog timer
-            pub const WWDGT = @intToPtr(*volatile types.peripherals.WWDGT, 0x40002c00);
-            ///  free watchdog timer
-            pub const FWDGT = @intToPtr(*volatile types.peripherals.FWDGT, 0x40003000);
-            ///  Serial peripheral interface
-            pub const SPI1 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003800);
-            ///  Serial peripheral interface
-            pub const SPI2 = @intToPtr(*volatile types.peripherals.SPI0, 0x40003c00);
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART1 = @intToPtr(*volatile types.peripherals.USART0, 0x40004400);
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART2 = @intToPtr(*volatile types.peripherals.USART0, 0x40004800);
-            ///  Universal asynchronous receiver transmitter
-            pub const UART3 = @intToPtr(*volatile types.peripherals.UART3, 0x40004c00);
-            ///  Universal asynchronous receiver transmitter
-            pub const UART4 = @intToPtr(*volatile types.peripherals.UART3, 0x40005000);
-            ///  Inter integrated circuit
-            pub const I2C0 = @intToPtr(*volatile types.peripherals.I2C0, 0x40005400);
-            ///  Inter integrated circuit
-            pub const I2C1 = @intToPtr(*volatile types.peripherals.I2C0, 0x40005800);
-            ///  Controller area network
-            pub const CAN0 = @intToPtr(*volatile types.peripherals.CAN0, 0x40006400);
-            ///  Controller area network
-            pub const CAN1 = @intToPtr(*volatile types.peripherals.CAN0, 0x40006800);
-            ///  Backup registers
-            pub const BKP = @intToPtr(*volatile types.peripherals.BKP, 0x40006c00);
-            ///  Power management unit
-            pub const PMU = @intToPtr(*volatile types.peripherals.PMU, 0x40007000);
-            ///  Digital-to-analog converter
-            pub const DAC = @intToPtr(*volatile types.peripherals.DAC, 0x40007400);
-            ///  Alternate-function I/Os
-            pub const AFIO = @intToPtr(*volatile types.peripherals.AFIO, 0x40010000);
-            ///  External interrupt/event controller
-            pub const EXTI = @intToPtr(*volatile types.peripherals.EXTI, 0x40010400);
-            ///  General-purpose I/Os
-            pub const GPIOA = @intToPtr(*volatile types.peripherals.GPIOA, 0x40010800);
-            ///  General-purpose I/Os
-            pub const GPIOB = @intToPtr(*volatile types.peripherals.GPIOA, 0x40010c00);
-            ///  General-purpose I/Os
-            pub const GPIOC = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011000);
-            ///  General-purpose I/Os
-            pub const GPIOD = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011400);
-            ///  General-purpose I/Os
-            pub const GPIOE = @intToPtr(*volatile types.peripherals.GPIOA, 0x40011800);
-            ///  Analog to digital converter
-            pub const ADC0 = @intToPtr(*volatile types.peripherals.ADC0, 0x40012400);
-            ///  Analog to digital converter
-            pub const ADC1 = @intToPtr(*volatile types.peripherals.ADC1, 0x40012800);
-            ///  Advanced-timers
-            pub const TIMER0 = @intToPtr(*volatile types.peripherals.TIMER0, 0x40012c00);
-            ///  Serial peripheral interface
-            pub const SPI0 = @intToPtr(*volatile types.peripherals.SPI0, 0x40013000);
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART0 = @intToPtr(*volatile types.peripherals.USART0, 0x40013800);
-            ///  DMA controller
-            pub const DMA0 = @intToPtr(*volatile types.peripherals.DMA0, 0x40020000);
-            ///  Direct memory access controller
-            pub const DMA1 = @intToPtr(*volatile types.peripherals.DMA1, 0x40020000);
-            ///  Reset and clock unit
-            pub const RCU = @intToPtr(*volatile types.peripherals.RCU, 0x40021000);
-            ///  FMC
-            pub const FMC = @intToPtr(*volatile types.peripherals.FMC, 0x40022000);
-            ///  cyclic redundancy check calculation unit
-            pub const CRC = @intToPtr(*volatile types.peripherals.CRC, 0x40023000);
-            ///  USB full speed global registers
-            pub const USBFS_GLOBAL = @intToPtr(*volatile types.peripherals.USBFS_GLOBAL, 0x50000000);
-            ///  USB on the go full speed host
-            pub const USBFS_HOST = @intToPtr(*volatile types.peripherals.USBFS_HOST, 0x50000400);
-            ///  USB on the go full speed device
-            pub const USBFS_DEVICE = @intToPtr(*volatile types.peripherals.USBFS_DEVICE, 0x50000800);
-            ///  USB on the go full speed
-            pub const USBFS_PWRCLK = @intToPtr(*volatile types.peripherals.USBFS_PWRCLK, 0x50000e00);
-            ///  External memory controller
-            pub const EXMC = @intToPtr(*volatile types.peripherals.EXMC, 0xa0000000);
-            ///  Enhanced Core Local Interrupt Controller
-            pub const ECLIC = @intToPtr(*volatile types.peripherals.ECLIC, 0xd2000000);
-            ///  System Tick Timer
-            pub const SysTick = @intToPtr(*volatile types.peripherals.SCS.SysTick, 0xe000e010);
-            ///  Debug support
-            pub const DBG = @intToPtr(*volatile types.peripherals.DBG, 0xe0042000);
-        };
-    };
-};
-
-pub const types = struct {
-    pub const peripherals = struct {
-        ///  System Control Space
-        pub const SCS = struct {
-            ///  System Tick Timer
-            pub const SysTick = extern struct {
-                ///  SysTick Control and Status Register
-                CTRL: mmio.Mmio(packed struct(u32) {
-                    ENABLE: u1,
-                    TICKINT: u1,
-                    CLKSOURCE: u1,
-                    reserved16: u13,
-                    COUNTFLAG: u1,
-                    padding: u15,
-                }),
-                ///  SysTick Reload Value Register
-                LOAD: mmio.Mmio(packed struct(u32) {
-                    RELOAD: u24,
-                    padding: u8,
-                }),
-                ///  SysTick Current Value Register
-                VAL: mmio.Mmio(packed struct(u32) {
-                    CURRENT: u24,
-                    padding: u8,
-                }),
-                ///  SysTick Calibration Register
-                CALIB: mmio.Mmio(packed struct(u32) {
-                    TENMS: u24,
-                    reserved30: u6,
-                    SKEW: u1,
-                    NOREF: u1,
-                }),
-            };
-        };
-
-        ///  Analog to digital converter
-        pub const ADC0 = extern struct {
-            ///  status register
-            STAT: mmio.Mmio(packed struct(u32) {
-                ///  Analog watchdog event flag
-                WDE: u1,
-                ///  End of group conversion flag
-                EOC: u1,
-                ///  End of inserted group conversion flag
-                EOIC: u1,
-                ///  Start flag of inserted channel group
-                STIC: u1,
-                ///  Start flag of regular channel group
-                STRC: u1,
-                padding: u27,
-            }),
-            ///  control register 0
-            CTL0: mmio.Mmio(packed struct(u32) {
-                ///  Analog watchdog channel select
-                WDCHSEL: u5,
-                ///  Interrupt enable for EOC
-                EOCIE: u1,
-                ///  Interrupt enable for WDE
-                WDEIE: u1,
-                ///  Interrupt enable for EOIC
-                EOICIE: u1,
-                ///  Scan mode
-                SM: u1,
-                ///  When in scan mode, analog watchdog is effective on a single channel
-                WDSC: u1,
-                ///  Inserted channel group convert automatically
-                ICA: u1,
-                ///  Discontinuous mode on regular channels
-                DISRC: u1,
-                ///  Discontinuous mode on inserted channels
-                DISIC: u1,
-                ///  Number of conversions in discontinuous mode
-                DISNUM: u3,
-                ///  sync mode selection
-                SYNCM: u4,
-                reserved22: u2,
-                ///  Inserted channel analog watchdog enable
-                IWDEN: u1,
-                ///  Regular channel analog watchdog enable
-                RWDEN: u1,
-                padding: u8,
-            }),
-            ///  control register 1
-            CTL1: mmio.Mmio(packed struct(u32) {
-                ///  ADC on
-                ADCON: u1,
-                ///  Continuous mode
-                CTN: u1,
-                ///  ADC calibration
-                CLB: u1,
-                ///  Reset calibration
-                RSTCLB: u1,
-                reserved8: u4,
-                ///  DMA request enable
-                DMA: u1,
-                reserved11: u2,
-                ///  Data alignment
-                DAL: u1,
-                ///  External trigger select for inserted channel
-                ETSIC: u3,
-                ///  External trigger select for inserted channel
-                ETEIC: u1,
-                reserved17: u1,
-                ///  External trigger select for regular channel
-                ETSRC: u3,
-                ///  External trigger enable for regular channel
-                ETERC: u1,
-                ///  Start on inserted channel
-                SWICST: u1,
-                ///  Start on regular channel
-                SWRCST: u1,
-                ///  Channel 16 and 17 enable of ADC0
-                TSVREN: u1,
-                padding: u8,
-            }),
-            ///  Sample time register 0
-            SAMPT0: mmio.Mmio(packed struct(u32) {
-                ///  Channel 10 sample time selection
-                SPT10: u3,
-                ///  Channel 11 sample time selection
-                SPT11: u3,
-                ///  Channel 12 sample time selection
-                SPT12: u3,
-                ///  Channel 13 sample time selection
-                SPT13: u3,
-                ///  Channel 14 sample time selection
-                SPT14: u3,
-                ///  Channel 15 sample time selection
-                SPT15: u3,
-                ///  Channel 16 sample time selection
-                SPT16: u3,
-                ///  Channel 17 sample time selection
-                SPT17: u3,
-                padding: u8,
-            }),
-            ///  Sample time register 1
-            SAMPT1: mmio.Mmio(packed struct(u32) {
-                ///  Channel 0 sample time selection
-                SPT0: u3,
-                ///  Channel 1 sample time selection
-                SPT1: u3,
-                ///  Channel 2 sample time selection
-                SPT2: u3,
-                ///  Channel 3 sample time selection
-                SPT3: u3,
-                ///  Channel 4 sample time selection
-                SPT4: u3,
-                ///  Channel 5 sample time selection
-                SPT5: u3,
-                ///  Channel 6 sample time selection
-                SPT6: u3,
-                ///  Channel 7 sample time selection
-                SPT7: u3,
-                ///  Channel 8 sample time selection
-                SPT8: u3,
-                ///  Channel 9 sample time selection
-                SPT9: u3,
-                padding: u2,
-            }),
-            ///  Inserted channel data offset register 0
-            IOFF0: mmio.Mmio(packed struct(u32) {
-                ///  Data offset for inserted channel 0
-                IOFF: u12,
-                padding: u20,
-            }),
-            ///  Inserted channel data offset register 1
-            IOFF1: mmio.Mmio(packed struct(u32) {
-                ///  Data offset for inserted channel 1
-                IOFF: u12,
-                padding: u20,
-            }),
-            ///  Inserted channel data offset register 2
-            IOFF2: mmio.Mmio(packed struct(u32) {
-                ///  Data offset for inserted channel 2
-                IOFF: u12,
-                padding: u20,
-            }),
-            ///  Inserted channel data offset register 3
-            IOFF3: mmio.Mmio(packed struct(u32) {
-                ///  Data offset for inserted channel 3
-                IOFF: u12,
-                padding: u20,
-            }),
-            ///  watchdog higher threshold register
-            WDHT: mmio.Mmio(packed struct(u32) {
-                ///  Analog watchdog higher threshold
-                WDHT: u12,
-                padding: u20,
-            }),
-            ///  watchdog lower threshold register
-            WDLT: mmio.Mmio(packed struct(u32) {
-                ///  Analog watchdog lower threshold
-                WDLT: u12,
-                padding: u20,
-            }),
-            ///  regular sequence register 0
-            RSQ0: mmio.Mmio(packed struct(u32) {
-                ///  13th conversion in regular sequence
-                RSQ12: u5,
-                ///  14th conversion in regular sequence
-                RSQ13: u5,
-                ///  15th conversion in regular sequence
-                RSQ14: u5,
-                ///  16th conversion in regular sequence
-                RSQ15: u5,
-                ///  Regular channel group length
-                RL: u4,
-                padding: u8,
-            }),
-            ///  regular sequence register 1
-            RSQ1: mmio.Mmio(packed struct(u32) {
-                ///  7th conversion in regular sequence
-                RSQ6: u5,
-                ///  8th conversion in regular sequence
-                RSQ7: u5,
-                ///  9th conversion in regular sequence
-                RSQ8: u5,
-                ///  10th conversion in regular sequence
-                RSQ9: u5,
-                ///  11th conversion in regular sequence
-                RSQ10: u5,
-                ///  12th conversion in regular sequence
-                RSQ11: u5,
-                padding: u2,
-            }),
-            ///  regular sequence register 2
-            RSQ2: mmio.Mmio(packed struct(u32) {
-                ///  1st conversion in regular sequence
-                RSQ0: u5,
-                ///  2nd conversion in regular sequence
-                RSQ1: u5,
-                ///  3rd conversion in regular sequence
-                RSQ2: u5,
-                ///  4th conversion in regular sequence
-                RSQ3: u5,
-                ///  5th conversion in regular sequence
-                RSQ4: u5,
-                ///  6th conversion in regular sequence
-                RSQ5: u5,
-                padding: u2,
-            }),
-            ///  Inserted sequence register
-            ISQ: mmio.Mmio(packed struct(u32) {
-                ///  1st conversion in inserted sequence
-                ISQ0: u5,
-                ///  2nd conversion in inserted sequence
-                ISQ1: u5,
-                ///  3rd conversion in inserted sequence
-                ISQ2: u5,
-                ///  4th conversion in inserted sequence
-                ISQ3: u5,
-                ///  Inserted channel group length
-                IL: u2,
-                padding: u10,
-            }),
-            ///  Inserted data register 0
-            IDATA0: mmio.Mmio(packed struct(u32) {
-                ///  Inserted number n conversion data
-                IDATAn: u16,
-                padding: u16,
-            }),
-            ///  Inserted data register 1
-            IDATA1: mmio.Mmio(packed struct(u32) {
-                ///  Inserted number n conversion data
-                IDATAn: u16,
-                padding: u16,
-            }),
-            ///  Inserted data register 2
-            IDATA2: mmio.Mmio(packed struct(u32) {
-                ///  Inserted number n conversion data
-                IDATAn: u16,
-                padding: u16,
-            }),
-            ///  Inserted data register 3
-            IDATA3: mmio.Mmio(packed struct(u32) {
-                ///  Inserted number n conversion data
-                IDATAn: u16,
-                padding: u16,
-            }),
-            ///  regular data register
-            RDATA: mmio.Mmio(packed struct(u32) {
-                ///  Regular channel data
-                RDATA: u16,
-                ///  ADC regular channel data
-                ADC1RDTR: u16,
-            }),
-            reserved128: [48]u8,
-            ///  Oversample control register
-            OVSAMPCTL: mmio.Mmio(packed struct(u32) {
-                ///  Oversampler Enable
-                OVSEN: u1,
-                reserved2: u1,
-                ///  Oversampling ratio
-                OVSR: u3,
-                ///  Oversampling shift
-                OVSS: u4,
-                ///  Triggered Oversampling
-                TOVS: u1,
-                reserved12: u2,
-                ///  ADC resolution
-                DRES: u2,
-                padding: u18,
-            }),
-        };
-
-        ///  Analog to digital converter
-        pub const ADC1 = extern struct {
-            ///  status register
-            STAT: mmio.Mmio(packed struct(u32) {
-                ///  Analog watchdog event flag
-                WDE: u1,
-                ///  End of group conversion flag
-                EOC: u1,
-                ///  End of inserted group conversion flag
-                EOIC: u1,
-                ///  Start flag of inserted channel group
-                STIC: u1,
-                ///  Start flag of regular channel group
-                STRC: u1,
-                padding: u27,
-            }),
-            ///  control register 0
-            CTL0: mmio.Mmio(packed struct(u32) {
-                ///  Analog watchdog channel select
-                WDCHSEL: u5,
-                ///  Interrupt enable for EOC
-                EOCIE: u1,
-                ///  Interrupt enable for WDE
-                WDEIE: u1,
-                ///  Interrupt enable for EOIC
-                EOICIE: u1,
-                ///  Scan mode
-                SM: u1,
-                ///  When in scan mode, analog watchdog is effective on a single channel
-                WDSC: u1,
-                ///  Inserted channel group convert automatically
-                ICA: u1,
-                ///  Discontinuous mode on regular channels
-                DISRC: u1,
-                ///  Discontinuous mode on inserted channels
-                DISIC: u1,
-                ///  Number of conversions in discontinuous mode
-                DISNUM: u3,
-                reserved22: u6,
-                ///  Inserted channel analog watchdog enable
-                IWDEN: u1,
-                ///  Regular channel analog watchdog enable
-                RWDEN: u1,
-                padding: u8,
-            }),
-            ///  control register 1
-            CTL1: mmio.Mmio(packed struct(u32) {
-                ///  ADC on
-                ADCON: u1,
-                ///  Continuous mode
-                CTN: u1,
-                ///  ADC calibration
-                CLB: u1,
-                ///  Reset calibration
-                RSTCLB: u1,
-                reserved8: u4,
-                ///  DMA request enable
-                DMA: u1,
-                reserved11: u2,
-                ///  Data alignment
-                DAL: u1,
-                ///  External trigger select for inserted channel
-                ETSIC: u3,
-                ///  External trigger enable for inserted channel
-                ETEIC: u1,
-                reserved17: u1,
-                ///  External trigger select for regular channel
-                ETSRC: u3,
-                ///  External trigger enable for regular channel
-                ETERC: u1,
-                ///  Start on inserted channel
-                SWICST: u1,
-                ///  Start on regular channel
-                SWRCST: u1,
-                padding: u9,
-            }),
-            ///  Sample time register 0
-            SAMPT0: mmio.Mmio(packed struct(u32) {
-                ///  Channel 10 sample time selection
-                SPT10: u3,
-                ///  Channel 11 sample time selection
-                SPT11: u3,
-                ///  Channel 12 sample time selection
-                SPT12: u3,
-                ///  Channel 13 sample time selection
-                SPT13: u3,
-                ///  Channel 14 sample time selection
-                SPT14: u3,
-                ///  Channel 15 sample time selection
-                SPT15: u3,
-                ///  Channel 16 sample time selection
-                SPT16: u3,
-                ///  Channel 17 sample time selection
-                SPT17: u3,
-                padding: u8,
-            }),
-            ///  Sample time register 1
-            SAMPT1: mmio.Mmio(packed struct(u32) {
-                ///  Channel 0 sample time selection
-                SPT0: u3,
-                ///  Channel 1 sample time selection
-                SPT1: u3,
-                ///  Channel 2 sample time selection
-                SPT2: u3,
-                ///  Channel 3 sample time selection
-                SPT3: u3,
-                ///  Channel 4 sample time selection
-                SPT4: u3,
-                ///  Channel 5 sample time selection
-                SPT5: u3,
-                ///  Channel 6 sample time selection
-                SPT6: u3,
-                ///  Channel 7 sample time selection
-                SPT7: u3,
-                ///  Channel 8 sample time selection
-                SPT8: u3,
-                ///  Channel 9 sample time selection
-                SPT9: u3,
-                padding: u2,
-            }),
-            ///  Inserted channel data offset register 0
-            IOFF0: mmio.Mmio(packed struct(u32) {
-                ///  Data offset for inserted channel 0
-                IOFF: u12,
-                padding: u20,
-            }),
-            ///  Inserted channel data offset register 1
-            IOFF1: mmio.Mmio(packed struct(u32) {
-                ///  Data offset for inserted channel 1
-                IOFF: u12,
-                padding: u20,
-            }),
-            ///  Inserted channel data offset register 2
-            IOFF2: mmio.Mmio(packed struct(u32) {
-                ///  Data offset for inserted channel 2
-                IOFF: u12,
-                padding: u20,
-            }),
-            ///  Inserted channel data offset register 3
-            IOFF3: mmio.Mmio(packed struct(u32) {
-                ///  Data offset for inserted channel 3
-                IOFF: u12,
-                padding: u20,
-            }),
-            ///  watchdog higher threshold register
-            WDHT: mmio.Mmio(packed struct(u32) {
-                ///  Analog watchdog higher threshold
-                WDHT: u12,
-                padding: u20,
-            }),
-            ///  watchdog lower threshold register
-            WDLT: mmio.Mmio(packed struct(u32) {
-                ///  Analog watchdog lower threshold
-                WDLT: u12,
-                padding: u20,
-            }),
-            ///  regular sequence register 0
-            RSQ0: mmio.Mmio(packed struct(u32) {
-                ///  13th conversion in regular sequence
-                RSQ12: u5,
-                ///  14th conversion in regular sequence
-                RSQ13: u5,
-                ///  15th conversion in regular sequence
-                RSQ14: u5,
-                ///  16th conversion in regular sequence
-                RSQ15: u5,
-                ///  Regular channel group length
-                RL: u4,
-                padding: u8,
-            }),
-            ///  regular sequence register 1
-            RSQ1: mmio.Mmio(packed struct(u32) {
-                ///  7th conversion in regular sequence
-                RSQ6: u5,
-                ///  8th conversion in regular sequence
-                RSQ7: u5,
-                ///  9th conversion in regular sequence
-                RSQ8: u5,
-                ///  10th conversion in regular sequence
-                RSQ9: u5,
-                ///  11th conversion in regular sequence
-                RSQ10: u5,
-                ///  12th conversion in regular sequence
-                RSQ11: u5,
-                padding: u2,
-            }),
-            ///  regular sequence register 2
-            RSQ2: mmio.Mmio(packed struct(u32) {
-                ///  1st conversion in regular sequence
-                RSQ0: u5,
-                ///  2nd conversion in regular sequence
-                RSQ1: u5,
-                ///  3rd conversion in regular sequence
-                RSQ2: u5,
-                ///  4th conversion in regular sequence
-                RSQ3: u5,
-                ///  5th conversion in regular sequence
-                RSQ4: u5,
-                ///  6th conversion in regular sequence
-                RSQ5: u5,
-                padding: u2,
-            }),
-            ///  Inserted sequence register
-            ISQ: mmio.Mmio(packed struct(u32) {
-                ///  1st conversion in inserted sequence
-                ISQ0: u5,
-                ///  2nd conversion in inserted sequence
-                ISQ1: u5,
-                ///  3rd conversion in inserted sequence
-                ISQ2: u5,
-                ///  4th conversion in inserted sequence
-                ISQ3: u5,
-                ///  Inserted channel group length
-                IL: u2,
-                padding: u10,
-            }),
-            ///  Inserted data register 0
-            IDATA0: mmio.Mmio(packed struct(u32) {
-                ///  Inserted number n conversion data
-                IDATAn: u16,
-                padding: u16,
-            }),
-            ///  Inserted data register 1
-            IDATA1: mmio.Mmio(packed struct(u32) {
-                ///  Inserted number n conversion data
-                IDATAn: u16,
-                padding: u16,
-            }),
-            ///  Inserted data register 2
-            IDATA2: mmio.Mmio(packed struct(u32) {
-                ///  Inserted number n conversion data
-                IDATAn: u16,
-                padding: u16,
-            }),
-            ///  Inserted data register 3
-            IDATA3: mmio.Mmio(packed struct(u32) {
-                ///  Inserted number n conversion data
-                IDATAn: u16,
-                padding: u16,
-            }),
-            ///  regular data register
-            RDATA: mmio.Mmio(packed struct(u32) {
-                ///  Regular channel data
-                RDATA: u16,
-                padding: u16,
-            }),
-        };
-
-        ///  Alternate-function I/Os
-        pub const AFIO = extern struct {
-            ///  Event control register
-            EC: mmio.Mmio(packed struct(u32) {
-                ///  Event output pin selection
-                PIN: u4,
-                ///  Event output port selection
-                PORT: u3,
-                ///  Event output enable
-                EOE: u1,
-                padding: u24,
-            }),
-            ///  AFIO port configuration register 0
-            PCF0: mmio.Mmio(packed struct(u32) {
-                ///  SPI0 remapping
-                SPI0_REMAP: u1,
-                ///  I2C0 remapping
-                I2C0_REMAP: u1,
-                ///  USART0 remapping
-                USART0_REMAP: u1,
-                ///  USART1 remapping
-                USART1_REMAP: u1,
-                ///  USART2 remapping
-                USART2_REMAP: u2,
-                ///  TIMER0 remapping
-                TIMER0_REMAP: u2,
-                ///  TIMER1 remapping
-                TIMER1_REMAP: u2,
-                ///  TIMER2 remapping
-                TIMER2_REMAP: u2,
-                ///  TIMER3 remapping
-                TIMER3_REMAP: u1,
-                ///  CAN0 alternate interface remapping
-                CAN0_REMAP: u2,
-                ///  Port D0/Port D1 mapping on OSC_IN/OSC_OUT
-                PD01_REMAP: u1,
-                ///  TIMER4 channel3 internal remapping
-                TIMER4CH3_IREMAP: u1,
-                reserved22: u5,
-                ///  CAN1 I/O remapping
-                CAN1_REMAP: u1,
-                reserved24: u1,
-                ///  Serial wire JTAG configuration
-                SWJ_CFG: u3,
-                reserved28: u1,
-                ///  SPI2/I2S2 remapping
-                SPI2_REMAP: u1,
-                ///  TIMER1 internal trigger 1 remapping
-                TIMER1ITI1_REMAP: u1,
-                padding: u2,
-            }),
-            ///  EXTI sources selection register 0
-            EXTISS0: mmio.Mmio(packed struct(u32) {
-                ///  EXTI 0 sources selection
-                EXTI0_SS: u4,
-                ///  EXTI 1 sources selection
-                EXTI1_SS: u4,
-                ///  EXTI 2 sources selection
-                EXTI2_SS: u4,
-                ///  EXTI 3 sources selection
-                EXTI3_SS: u4,
-                padding: u16,
-            }),
-            ///  EXTI sources selection register 1
-            EXTISS1: mmio.Mmio(packed struct(u32) {
-                ///  EXTI 4 sources selection
-                EXTI4_SS: u4,
-                ///  EXTI 5 sources selection
-                EXTI5_SS: u4,
-                ///  EXTI 6 sources selection
-                EXTI6_SS: u4,
-                ///  EXTI 7 sources selection
-                EXTI7_SS: u4,
-                padding: u16,
-            }),
-            ///  EXTI sources selection register 2
-            EXTISS2: mmio.Mmio(packed struct(u32) {
-                ///  EXTI 8 sources selection
-                EXTI8_SS: u4,
-                ///  EXTI 9 sources selection
-                EXTI9_SS: u4,
-                ///  EXTI 10 sources selection
-                EXTI10_SS: u4,
-                ///  EXTI 11 sources selection
-                EXTI11_SS: u4,
-                padding: u16,
-            }),
-            ///  EXTI sources selection register 3
-            EXTISS3: mmio.Mmio(packed struct(u32) {
-                ///  EXTI 12 sources selection
-                EXTI12_SS: u4,
-                ///  EXTI 13 sources selection
-                EXTI13_SS: u4,
-                ///  EXTI 14 sources selection
-                EXTI14_SS: u4,
-                ///  EXTI 15 sources selection
-                EXTI15_SS: u4,
-                padding: u16,
-            }),
-            reserved28: [4]u8,
-            ///  AFIO port configuration register 1
-            PCF1: mmio.Mmio(packed struct(u32) {
-                reserved10: u10,
-                ///  EXMC_NADV connect/disconnect
-                EXMC_NADV: u1,
-                padding: u21,
-            }),
-        };
-
-        ///  Backup registers
-        pub const BKP = extern struct {
-            reserved4: [4]u8,
-            ///  Backup data register 0
-            DATA0: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved8: [2]u8,
-            ///  Backup data register 1
-            DATA1: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved12: [2]u8,
-            ///  Backup data register 2
-            DATA2: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved16: [2]u8,
-            ///  Backup data register 3
-            DATA3: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved20: [2]u8,
-            ///  Backup data register 4
-            DATA4: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved24: [2]u8,
-            ///  Backup data register 5
-            DATA5: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved28: [2]u8,
-            ///  Backup data register 6
-            DATA6: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved32: [2]u8,
-            ///  Backup data register 7
-            DATA7: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved36: [2]u8,
-            ///  Backup data register 8
-            DATA8: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved40: [2]u8,
-            ///  Backup data register 9
-            DATA9: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved44: [2]u8,
-            ///  RTC signal output control register
-            OCTL: mmio.Mmio(packed struct(u16) {
-                ///  RTC clock calibration value
-                RCCV: u7,
-                ///  RTC clock calibration output enable
-                COEN: u1,
-                ///  RTC alarm or second signal output enable
-                ASOEN: u1,
-                ///  RTC output selection
-                ROSEL: u1,
-                padding: u6,
-            }),
-            reserved48: [2]u8,
-            ///  Tamper pin control register
-            TPCTL: mmio.Mmio(packed struct(u16) {
-                ///  TAMPER detection enable
-                TPEN: u1,
-                ///  TAMPER pin active level
-                TPAL: u1,
-                padding: u14,
-            }),
-            reserved52: [2]u8,
-            ///  Tamper control and status register
-            TPCS: mmio.Mmio(packed struct(u16) {
-                ///  Tamper event reset
-                TER: u1,
-                ///  Tamper interrupt reset
-                TIR: u1,
-                ///  Tamper interrupt enable
-                TPIE: u1,
-                reserved8: u5,
-                ///  Tamper event flag
-                TEF: u1,
-                ///  Tamper interrupt flag
-                TIF: u1,
-                padding: u6,
-            }),
-            reserved64: [10]u8,
-            ///  Backup data register 10
-            DATA10: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved68: [2]u8,
-            ///  Backup data register 11
-            DATA11: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved72: [2]u8,
-            ///  Backup data register 12
-            DATA12: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved76: [2]u8,
-            ///  Backup data register 13
-            DATA13: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved80: [2]u8,
-            ///  Backup data register 14
-            DATA14: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved84: [2]u8,
-            ///  Backup data register 15
-            DATA15: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved88: [2]u8,
-            ///  Backup data register 16
-            DATA16: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved92: [2]u8,
-            ///  Backup data register 17
-            DATA17: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved96: [2]u8,
-            ///  Backup data register 18
-            DATA18: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved100: [2]u8,
-            ///  Backup data register 19
-            DATA19: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved104: [2]u8,
-            ///  Backup data register 20
-            DATA20: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved108: [2]u8,
-            ///  Backup data register 21
-            DATA21: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved112: [2]u8,
-            ///  Backup data register 22
-            DATA22: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved116: [2]u8,
-            ///  Backup data register 23
-            DATA23: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved120: [2]u8,
-            ///  Backup data register 24
-            DATA24: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved124: [2]u8,
-            ///  Backup data register 25
-            DATA25: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved128: [2]u8,
-            ///  Backup data register 26
-            DATA26: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved132: [2]u8,
-            ///  Backup data register 27
-            DATA27: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved136: [2]u8,
-            ///  Backup data register 28
-            DATA28: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved140: [2]u8,
-            ///  Backup data register 29
-            DATA29: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved144: [2]u8,
-            ///  Backup data register 30
-            DATA30: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved148: [2]u8,
-            ///  Backup data register 31
-            DATA31: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved152: [2]u8,
-            ///  Backup data register 32
-            DATA32: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved156: [2]u8,
-            ///  Backup data register 33
-            DATA33: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved160: [2]u8,
-            ///  Backup data register 34
-            DATA34: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved164: [2]u8,
-            ///  Backup data register 35
-            DATA35: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved168: [2]u8,
-            ///  Backup data register 36
-            DATA36: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved172: [2]u8,
-            ///  Backup data register 37
-            DATA37: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved176: [2]u8,
-            ///  Backup data register 38
-            DATA38: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved180: [2]u8,
-            ///  Backup data register 39
-            DATA39: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved184: [2]u8,
-            ///  Backup data register 40
-            DATA40: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-            reserved188: [2]u8,
-            ///  Backup data register 41
-            DATA41: mmio.Mmio(packed struct(u16) {
-                ///  Backup data
-                DATA: u16,
-            }),
-        };
-
-        ///  Controller area network
-        pub const CAN0 = extern struct {
-            ///  Control register
-            CTL: mmio.Mmio(packed struct(u32) {
-                ///  Initial working mode
-                IWMOD: u1,
-                ///  Sleep working mode
-                SLPWMOD: u1,
-                ///  Transmit FIFO order
-                TFO: u1,
-                ///  Receive FIFO overwrite disable
-                RFOD: u1,
-                ///  Automatic retransmission disable
-                ARD: u1,
-                ///  Automatic wakeup
-                AWU: u1,
-                ///  Automatic bus-off recovery
-                ABOR: u1,
-                ///  Time-triggered communication
-                TTC: u1,
-                reserved15: u7,
-                ///  Software reset
-                SWRST: u1,
-                ///  Debug freeze
-                DFZ: u1,
-                padding: u15,
-            }),
-            ///  Status register
-            STAT: mmio.Mmio(packed struct(u32) {
-                ///  Initial working state
-                IWS: u1,
-                ///  Sleep working state
-                SLPWS: u1,
-                ///  Error interrupt flag
-                ERRIF: u1,
-                ///  Status change interrupt flag of wakeup from sleep working mode
-                WUIF: u1,
-                ///  Status change interrupt flag of sleep working mode entering
-                SLPIF: u1,
-                reserved8: u3,
-                ///  Transmitting state
-                TS: u1,
-                ///  Receiving state
-                RS: u1,
-                ///  Last sample value of RX pin
-                LASTRX: u1,
-                ///  RX level
-                RXL: u1,
-                padding: u20,
-            }),
-            ///  Transmit status register
-            TSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Mailbox 0 transmit finished
-                MTF0: u1,
-                ///  Mailbox 0 transmit finished and no error
-                MTFNERR0: u1,
-                ///  Mailbox 0 arbitration lost
-                MAL0: u1,
-                ///  Mailbox 0 transmit error
-                MTE0: u1,
-                reserved7: u3,
-                ///  Mailbox 0 stop transmitting
-                MST0: u1,
-                ///  Mailbox 1 transmit finished
-                MTF1: u1,
-                ///  Mailbox 1 transmit finished and no error
-                MTFNERR1: u1,
-                ///  Mailbox 1 arbitration lost
-                MAL1: u1,
-                ///  Mailbox 1 transmit error
-                MTE1: u1,
-                reserved15: u3,
-                ///  Mailbox 1 stop transmitting
-                MST1: u1,
-                ///  Mailbox 2 transmit finished
-                MTF2: u1,
-                ///  Mailbox 2 transmit finished and no error
-                MTFNERR2: u1,
-                ///  Mailbox 2 arbitration lost
-                MAL2: u1,
-                ///  Mailbox 2 transmit error
-                MTE2: u1,
-                reserved23: u3,
-                ///  Mailbox 2 stop transmitting
-                MST2: u1,
-                ///  number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty
-                NUM: u2,
-                ///  Transmit mailbox 0 empty
-                TME0: u1,
-                ///  Transmit mailbox 1 empty
-                TME1: u1,
-                ///  Transmit mailbox 2 empty
-                TME2: u1,
-                ///  Transmit mailbox 0 last sending in transmit FIFO
-                TMLS0: u1,
-                ///  Transmit mailbox 1 last sending in transmit FIFO
-                TMLS1: u1,
-                ///  Transmit mailbox 2 last sending in transmit FIFO
-                TMLS2: u1,
-            }),
-            ///  Receive message FIFO0 register
-            RFIFO0: mmio.Mmio(packed struct(u32) {
-                ///  Receive FIFO0 length
-                RFL0: u2,
-                reserved3: u1,
-                ///  Receive FIFO0 full
-                RFF0: u1,
-                ///  Receive FIFO0 overfull
-                RFO0: u1,
-                ///  Receive FIFO0 dequeue
-                RFD0: u1,
-                padding: u26,
-            }),
-            ///  Receive message FIFO1 register
-            RFIFO1: mmio.Mmio(packed struct(u32) {
-                ///  Receive FIFO1 length
-                RFL1: u2,
-                reserved3: u1,
-                ///  Receive FIFO1 full
-                RFF1: u1,
-                ///  Receive FIFO1 overfull
-                RFO1: u1,
-                ///  Receive FIFO1 dequeue
-                RFD1: u1,
-                padding: u26,
-            }),
-            ///  Interrupt enable register
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Transmit mailbox empty interrupt enable
-                TMEIE: u1,
-                ///  Receive FIFO0 not empty interrupt enable
-                RFNEIE0: u1,
-                ///  Receive FIFO0 full interrupt enable
-                RFFIE0: u1,
-                ///  Receive FIFO0 overfull interrupt enable
-                RFOIE0: u1,
-                ///  Receive FIFO1 not empty interrupt enable
-                RFNEIE1: u1,
-                ///  Receive FIFO1 full interrupt enable
-                RFFIE1: u1,
-                ///  Receive FIFO1 overfull interrupt enable
-                RFOIE1: u1,
-                reserved8: u1,
-                ///  Warning error interrupt enable
-                WERRIE: u1,
-                ///  Passive error interrupt enable
-                PERRIE: u1,
-                ///  Bus-off interrupt enable
-                BOIE: u1,
-                ///  Error number interrupt enable
-                ERRNIE: u1,
-                reserved15: u3,
-                ///  Error interrupt enable
-                ERRIE: u1,
-                ///  Wakeup interrupt enable
-                WIE: u1,
-                ///  Sleep working interrupt enable
-                SLPWIE: u1,
-                padding: u14,
-            }),
-            ///  Error register
-            ERR: mmio.Mmio(packed struct(u32) {
-                ///  Warning error
-                WERR: u1,
-                ///  Passive error
-                PERR: u1,
-                ///  Bus-off error
-                BOERR: u1,
-                reserved4: u1,
-                ///  Error number
-                ERRN: u3,
-                reserved16: u9,
-                ///  Transmit Error Count defined by the CAN standard
-                TECNT: u8,
-                ///  Receive Error Count defined by the CAN standard
-                RECNT: u8,
-            }),
-            ///  Bit timing register
-            BT: mmio.Mmio(packed struct(u32) {
-                ///  Baud rate prescaler
-                BAUDPSC: u10,
-                reserved16: u6,
-                ///  Bit segment 1
-                BS1: u4,
-                ///  Bit segment 2
-                BS2: u3,
-                reserved24: u1,
-                ///  Resynchronization jump width
-                SJW: u2,
-                reserved30: u4,
-                ///  Loopback communication mode
-                LCMOD: u1,
-                ///  Silent communication mode
-                SCMOD: u1,
-            }),
-            reserved384: [352]u8,
-            ///  Transmit mailbox identifier register 0
-            TMI0: mmio.Mmio(packed struct(u32) {
-                ///  Transmit enable
-                TEN: u1,
-                ///  Frame type
-                FT: u1,
-                ///  Frame format
-                FF: u1,
-                ///  The frame identifier
-                EFID: u18,
-                ///  The frame identifier
-                SFID_EFID: u11,
-            }),
-            ///  Transmit mailbox property register 0
-            TMP0: mmio.Mmio(packed struct(u32) {
-                ///  Data length code
-                DLENC: u4,
-                reserved8: u4,
-                ///  Time stamp enable
-                TSEN: u1,
-                reserved16: u7,
-                ///  Time stamp
-                TS: u16,
-            }),
-            ///  Transmit mailbox data0 register
-            TMDATA00: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 0
-                DB0: u8,
-                ///  Data byte 1
-                DB1: u8,
-                ///  Data byte 2
-                DB2: u8,
-                ///  Data byte 3
-                DB3: u8,
-            }),
-            ///  Transmit mailbox data1 register
-            TMDATA10: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 4
-                DB4: u8,
-                ///  Data byte 5
-                DB5: u8,
-                ///  Data byte 6
-                DB6: u8,
-                ///  Data byte 7
-                DB7: u8,
-            }),
-            ///  Transmit mailbox identifier register 1
-            TMI1: mmio.Mmio(packed struct(u32) {
-                ///  Transmit enable
-                TEN: u1,
-                ///  Frame type
-                FT: u1,
-                ///  Frame format
-                FF: u1,
-                ///  The frame identifier
-                EFID: u18,
-                ///  The frame identifier
-                SFID_EFID: u11,
-            }),
-            ///  Transmit mailbox property register 1
-            TMP1: mmio.Mmio(packed struct(u32) {
-                ///  Data length code
-                DLENC: u4,
-                reserved8: u4,
-                ///  Time stamp enable
-                TSEN: u1,
-                reserved16: u7,
-                ///  Time stamp
-                TS: u16,
-            }),
-            ///  Transmit mailbox data0 register
-            TMDATA01: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 0
-                DB0: u8,
-                ///  Data byte 1
-                DB1: u8,
-                ///  Data byte 2
-                DB2: u8,
-                ///  Data byte 3
-                DB3: u8,
-            }),
-            ///  Transmit mailbox data1 register
-            TMDATA11: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 4
-                DB4: u8,
-                ///  Data byte 5
-                DB5: u8,
-                ///  Data byte 6
-                DB6: u8,
-                ///  Data byte 7
-                DB7: u8,
-            }),
-            ///  Transmit mailbox identifier register 2
-            TMI2: mmio.Mmio(packed struct(u32) {
-                ///  Transmit enable
-                TEN: u1,
-                ///  Frame type
-                FT: u1,
-                ///  Frame format
-                FF: u1,
-                ///  The frame identifier
-                EFID: u18,
-                ///  The frame identifier
-                SFID_EFID: u11,
-            }),
-            ///  Transmit mailbox property register 2
-            TMP2: mmio.Mmio(packed struct(u32) {
-                ///  Data length code
-                DLENC: u4,
-                reserved8: u4,
-                ///  Time stamp enable
-                TSEN: u1,
-                reserved16: u7,
-                ///  Time stamp
-                TS: u16,
-            }),
-            ///  Transmit mailbox data0 register
-            TMDATA02: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 0
-                DB0: u8,
-                ///  Data byte 1
-                DB1: u8,
-                ///  Data byte 2
-                DB2: u8,
-                ///  Data byte 3
-                DB3: u8,
-            }),
-            ///  Transmit mailbox data1 register
-            TMDATA12: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 4
-                DB4: u8,
-                ///  Data byte 5
-                DB5: u8,
-                ///  Data byte 6
-                DB6: u8,
-                ///  Data byte 7
-                DB7: u8,
-            }),
-            ///  Receive FIFO mailbox identifier register
-            RFIFOMI0: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Frame type
-                FT: u1,
-                ///  Frame format
-                FF: u1,
-                ///  The frame identifier
-                EFID: u18,
-                ///  The frame identifier
-                SFID_EFID: u11,
-            }),
-            ///  Receive FIFO0 mailbox property register
-            RFIFOMP0: mmio.Mmio(packed struct(u32) {
-                ///  Data length code
-                DLENC: u4,
-                reserved8: u4,
-                ///  Filtering index
-                FI: u8,
-                ///  Time stamp
-                TS: u16,
-            }),
-            ///  Receive FIFO0 mailbox data0 register
-            RFIFOMDATA00: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 0
-                DB0: u8,
-                ///  Data byte 1
-                DB1: u8,
-                ///  Data byte 2
-                DB2: u8,
-                ///  Data byte 3
-                DB3: u8,
-            }),
-            ///  Receive FIFO0 mailbox data1 register
-            RFIFOMDATA10: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 4
-                DB4: u8,
-                ///  Data byte 5
-                DB5: u8,
-                ///  Data byte 6
-                DB6: u8,
-                ///  Data byte 7
-                DB7: u8,
-            }),
-            ///  Receive FIFO1 mailbox identifier register
-            RFIFOMI1: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Frame type
-                FT: u1,
-                ///  Frame format
-                FF: u1,
-                ///  The frame identifier
-                EFID: u18,
-                ///  The frame identifier
-                SFID_EFID: u11,
-            }),
-            ///  Receive FIFO1 mailbox property register
-            RFIFOMP1: mmio.Mmio(packed struct(u32) {
-                ///  Data length code
-                DLENC: u4,
-                reserved8: u4,
-                ///  Filtering index
-                FI: u8,
-                ///  Time stamp
-                TS: u16,
-            }),
-            ///  Receive FIFO1 mailbox data0 register
-            RFIFOMDATA01: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 0
-                DB0: u8,
-                ///  Data byte 1
-                DB1: u8,
-                ///  Data byte 2
-                DB2: u8,
-                ///  Data byte 3
-                DB3: u8,
-            }),
-            ///  Receive FIFO1 mailbox data1 register
-            RFIFOMDATA11: mmio.Mmio(packed struct(u32) {
-                ///  Data byte 4
-                DB4: u8,
-                ///  Data byte 5
-                DB5: u8,
-                ///  Data byte 6
-                DB6: u8,
-                ///  Data byte 7
-                DB7: u8,
-            }),
-            reserved512: [48]u8,
-            ///  Filter control register
-            FCTL: mmio.Mmio(packed struct(u32) {
-                ///  Filter lock disable
-                FLD: u1,
-                reserved8: u7,
-                ///  Header bank of CAN1 filter
-                HBC1F: u6,
-                padding: u18,
-            }),
-            ///  Filter mode configuration register
-            FMCFG: mmio.Mmio(packed struct(u32) {
-                ///  Filter mode
-                FMOD0: u1,
-                ///  Filter mode
-                FMOD1: u1,
-                ///  Filter mode
-                FMOD2: u1,
-                ///  Filter mode
-                FMOD3: u1,
-                ///  Filter mode
-                FMOD4: u1,
-                ///  Filter mode
-                FMOD5: u1,
-                ///  Filter mode
-                FMOD6: u1,
-                ///  Filter mode
-                FMOD7: u1,
-                ///  Filter mode
-                FMOD8: u1,
-                ///  Filter mode
-                FMOD9: u1,
-                ///  Filter mode
-                FMOD10: u1,
-                ///  Filter mode
-                FMOD11: u1,
-                ///  Filter mode
-                FMOD12: u1,
-                ///  Filter mode
-                FMOD13: u1,
-                ///  Filter mode
-                FMOD14: u1,
-                ///  Filter mode
-                FMOD15: u1,
-                ///  Filter mode
-                FMOD16: u1,
-                ///  Filter mode
-                FMOD17: u1,
-                ///  Filter mode
-                FMOD18: u1,
-                ///  Filter mode
-                FMOD19: u1,
-                ///  Filter mode
-                FMOD20: u1,
-                ///  Filter mode
-                FMOD21: u1,
-                ///  Filter mode
-                FMOD22: u1,
-                ///  Filter mode
-                FMOD23: u1,
-                ///  Filter mode
-                FMOD24: u1,
-                ///  Filter mode
-                FMOD25: u1,
-                ///  Filter mode
-                FMOD26: u1,
-                ///  Filter mode
-                FMOD27: u1,
-                padding: u4,
-            }),
-            reserved524: [4]u8,
-            ///  Filter scale configuration register
-            FSCFG: mmio.Mmio(packed struct(u32) {
-                ///  Filter scale configuration
-                FS0: u1,
-                ///  Filter scale configuration
-                FS1: u1,
-                ///  Filter scale configuration
-                FS2: u1,
-                ///  Filter scale configuration
-                FS3: u1,
-                ///  Filter scale configuration
-                FS4: u1,
-                ///  Filter scale configuration
-                FS5: u1,
-                ///  Filter scale configuration
-                FS6: u1,
-                ///  Filter scale configuration
-                FS7: u1,
-                ///  Filter scale configuration
-                FS8: u1,
-                ///  Filter scale configuration
-                FS9: u1,
-                ///  Filter scale configuration
-                FS10: u1,
-                ///  Filter scale configuration
-                FS11: u1,
-                ///  Filter scale configuration
-                FS12: u1,
-                ///  Filter scale configuration
-                FS13: u1,
-                ///  Filter scale configuration
-                FS14: u1,
-                ///  Filter scale configuration
-                FS15: u1,
-                ///  Filter scale configuration
-                FS16: u1,
-                ///  Filter scale configuration
-                FS17: u1,
-                ///  Filter scale configuration
-                FS18: u1,
-                ///  Filter scale configuration
-                FS19: u1,
-                ///  Filter scale configuration
-                FS20: u1,
-                ///  Filter scale configuration
-                FS21: u1,
-                ///  Filter scale configuration
-                FS22: u1,
-                ///  Filter scale configuration
-                FS23: u1,
-                ///  Filter scale configuration
-                FS24: u1,
-                ///  Filter scale configuration
-                FS25: u1,
-                ///  Filter scale configuration
-                FS26: u1,
-                ///  Filter scale configuration
-                FS27: u1,
-                padding: u4,
-            }),
-            reserved532: [4]u8,
-            ///  Filter associated FIFO register
-            FAFIFO: mmio.Mmio(packed struct(u32) {
-                ///  Filter 0 associated with FIFO
-                FAF0: u1,
-                ///  Filter 1 associated with FIFO
-                FAF1: u1,
-                ///  Filter 2 associated with FIFO
-                FAF2: u1,
-                ///  Filter 3 associated with FIFO
-                FAF3: u1,
-                ///  Filter 4 associated with FIFO
-                FAF4: u1,
-                ///  Filter 5 associated with FIFO
-                FAF5: u1,
-                ///  Filter 6 associated with FIFO
-                FAF6: u1,
-                ///  Filter 7 associated with FIFO
-                FAF7: u1,
-                ///  Filter 8 associated with FIFO
-                FAF8: u1,
-                ///  Filter 9 associated with FIFO
-                FAF9: u1,
-                ///  Filter 10 associated with FIFO
-                FAF10: u1,
-                ///  Filter 11 associated with FIFO
-                FAF11: u1,
-                ///  Filter 12 associated with FIFO
-                FAF12: u1,
-                ///  Filter 13 associated with FIFO
-                FAF13: u1,
-                ///  Filter 14 associated with FIFO
-                FAF14: u1,
-                ///  Filter 15 associated with FIFO
-                FAF15: u1,
-                ///  Filter 16 associated with FIFO
-                FAF16: u1,
-                ///  Filter 17 associated with FIFO
-                FAF17: u1,
-                ///  Filter 18 associated with FIFO
-                FAF18: u1,
-                ///  Filter 19 associated with FIFO
-                FAF19: u1,
-                ///  Filter 20 associated with FIFO
-                FAF20: u1,
-                ///  Filter 21 associated with FIFO
-                FAF21: u1,
-                ///  Filter 22 associated with FIFO
-                FAF22: u1,
-                ///  Filter 23 associated with FIFO
-                FAF23: u1,
-                ///  Filter 24 associated with FIFO
-                FAF24: u1,
-                ///  Filter 25 associated with FIFO
-                FAF25: u1,
-                ///  Filter 26 associated with FIFO
-                FAF26: u1,
-                ///  Filter 27 associated with FIFO
-                FAF27: u1,
-                padding: u4,
-            }),
-            reserved540: [4]u8,
-            ///  Filter working register
-            FW: mmio.Mmio(packed struct(u32) {
-                ///  Filter working
-                FW0: u1,
-                ///  Filter working
-                FW1: u1,
-                ///  Filter working
-                FW2: u1,
-                ///  Filter working
-                FW3: u1,
-                ///  Filter working
-                FW4: u1,
-                ///  Filter working
-                FW5: u1,
-                ///  Filter working
-                FW6: u1,
-                ///  Filter working
-                FW7: u1,
-                ///  Filter working
-                FW8: u1,
-                ///  Filter working
-                FW9: u1,
-                ///  Filter working
-                FW10: u1,
-                ///  Filter working
-                FW11: u1,
-                ///  Filter working
-                FW12: u1,
-                ///  Filter working
-                FW13: u1,
-                ///  Filter working
-                FW14: u1,
-                ///  Filter working
-                FW15: u1,
-                ///  Filter working
-                FW16: u1,
-                ///  Filter working
-                FW17: u1,
-                ///  Filter working
-                FW18: u1,
-                ///  Filter working
-                FW19: u1,
-                ///  Filter working
-                FW20: u1,
-                ///  Filter working
-                FW21: u1,
-                ///  Filter working
-                FW22: u1,
-                ///  Filter working
-                FW23: u1,
-                ///  Filter working
-                FW24: u1,
-                ///  Filter working
-                FW25: u1,
-                ///  Filter working
-                FW26: u1,
-                ///  Filter working
-                FW27: u1,
-                padding: u4,
-            }),
-            reserved576: [32]u8,
-            ///  Filter 0 data 0 register
-            F0DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 0 data 1 register
-            F0DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 1 data 0 register
-            F1DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 1 data 1 register
-            F1DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 2 data 0 register
-            F2DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 2 data 1 register
-            F2DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 3 data 0 register
-            F3DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 3 data 1 register
-            F3DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 4 data 0 register
-            F4DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 4 data 1 register
-            F4DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 5 data 0 register
-            F5DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 5 data 1 register
-            F5DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 6 data 0 register
-            F6DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 6 data 1 register
-            F6DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 7 data 0 register
-            F7DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 7 data 1 register
-            F7DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 8 data 0 register
-            F8DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 8 data 1 register
-            F8DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 9 data 0 register
-            F9DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 9 data 1 register
-            F9DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 10 data 0 register
-            F10DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 10 data 1 register
-            F10DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 11 data 0 register
-            F11DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 11 data 1 register
-            F11DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 12 data 0 register
-            F12DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 12 data 1 register
-            F12DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 13 data 0 register
-            F13DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 13 data 1 register
-            F13DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 14 data 0 register
-            F14DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 14 data 1 register
-            F14DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 15 data 0 register
-            F15DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 15 data 1 register
-            F15DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 16 data 0 register
-            F16DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 16 data 1 register
-            F16DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 17 data 0 register
-            F17DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 17 data 1 register
-            F17DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 18 data 0 register
-            F18DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 18 data 1 register
-            F18DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 19 data 0 register
-            F19DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 19 data 1 register
-            F19DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 20 data 0 register
-            F20DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 20 data 1 register
-            F20DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 21 data 0 register
-            F21DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 21 data 1 register
-            F21DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 22 data 0 register
-            F22DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 22 data 1 register
-            F22DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 23 data 0 register
-            F23DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 23 data 1 register
-            F23DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 24 data 0 register
-            F24DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 24 data 1 register
-            F24DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 25 data 0 register
-            F25DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 25 data 1 register
-            F25DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 26 data 0 register
-            F26DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 26 data 1 register
-            F26DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 27 data 0 register
-            F27DATA0: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-            ///  Filter 27 data 1 register
-            F27DATA1: mmio.Mmio(packed struct(u32) {
-                ///  Filter bits
-                FD0: u1,
-                ///  Filter bits
-                FD1: u1,
-                ///  Filter bits
-                FD2: u1,
-                ///  Filter bits
-                FD3: u1,
-                ///  Filter bits
-                FD4: u1,
-                ///  Filter bits
-                FD5: u1,
-                ///  Filter bits
-                FD6: u1,
-                ///  Filter bits
-                FD7: u1,
-                ///  Filter bits
-                FD8: u1,
-                ///  Filter bits
-                FD9: u1,
-                ///  Filter bits
-                FD10: u1,
-                ///  Filter bits
-                FD11: u1,
-                ///  Filter bits
-                FD12: u1,
-                ///  Filter bits
-                FD13: u1,
-                ///  Filter bits
-                FD14: u1,
-                ///  Filter bits
-                FD15: u1,
-                ///  Filter bits
-                FD16: u1,
-                ///  Filter bits
-                FD17: u1,
-                ///  Filter bits
-                FD18: u1,
-                ///  Filter bits
-                FD19: u1,
-                ///  Filter bits
-                FD20: u1,
-                ///  Filter bits
-                FD21: u1,
-                ///  Filter bits
-                FD22: u1,
-                ///  Filter bits
-                FD23: u1,
-                ///  Filter bits
-                FD24: u1,
-                ///  Filter bits
-                FD25: u1,
-                ///  Filter bits
-                FD26: u1,
-                ///  Filter bits
-                FD27: u1,
-                ///  Filter bits
-                FD28: u1,
-                ///  Filter bits
-                FD29: u1,
-                ///  Filter bits
-                FD30: u1,
-                ///  Filter bits
-                FD31: u1,
-            }),
-        };
-
-        ///  Window watchdog timer
-        pub const WWDGT = extern struct {
-            ///  Control register
-            CTL: mmio.Mmio(packed struct(u32) {
-                ///  7-bit counter
-                CNT: u7,
-                ///  Activation bit
-                WDGTEN: u1,
-                padding: u24,
-            }),
-            ///  Configuration register
-            CFG: mmio.Mmio(packed struct(u32) {
-                ///  7-bit window value
-                WIN: u7,
-                ///  Prescaler
-                PSC: u2,
-                ///  Early wakeup interrupt
-                EWIE: u1,
-                padding: u22,
-            }),
-            ///  Status register
-            STAT: mmio.Mmio(packed struct(u32) {
-                ///  Early wakeup interrupt flag
-                EWIF: u1,
-                padding: u31,
-            }),
-        };
-
-        ///  cyclic redundancy check calculation unit
-        pub const CRC = extern struct {
-            ///  Data register
-            DATA: mmio.Mmio(packed struct(u32) {
-                ///  CRC calculation result bits
-                DATA: u32,
-            }),
-            ///  Free data register
-            FDATA: mmio.Mmio(packed struct(u32) {
-                ///  Free Data Register bits
-                FDATA: u8,
-                padding: u24,
-            }),
-            ///  Control register
-            CTL: mmio.Mmio(packed struct(u32) {
-                ///  reset bit
-                RST: u1,
-                padding: u31,
-            }),
-        };
-
-        ///  Digital-to-analog converter
-        pub const DAC = extern struct {
-            ///  control register
-            CTL: mmio.Mmio(packed struct(u32) {
-                ///  DAC0 enable
-                DEN0: u1,
-                ///  DAC0 output buffer turn off
-                DBOFF0: u1,
-                ///  DAC0 trigger enable
-                DTEN0: u1,
-                ///  DAC0 trigger selection
-                DTSEL0: u3,
-                ///  DAC0 noise wave mode
-                DWM0: u2,
-                ///  DAC0 noise wave bit width
-                DWBW0: u4,
-                ///  DAC0 DMA enable
-                DDMAEN0: u1,
-                reserved16: u3,
-                ///  DAC1 enable
-                DEN1: u1,
-                ///  DAC1 output buffer turn off
-                DBOFF1: u1,
-                ///  DAC1 trigger enable
-                DTEN1: u1,
-                ///  DAC1 trigger selection
-                DTSEL1: u3,
-                ///  DAC1 noise wave mode
-                DWM1: u2,
-                ///  DAC1 noise wave bit width
-                DWBW1: u4,
-                ///  DAC1 DMA enable
-                DDMAEN1: u1,
-                padding: u3,
-            }),
-            ///  software trigger register
-            SWT: mmio.Mmio(packed struct(u32) {
-                ///  DAC0 software trigger
-                SWTR0: u1,
-                ///  DAC1 software trigger
-                SWTR1: u1,
-                padding: u30,
-            }),
-            ///  DAC0 12-bit right-aligned data holding register
-            DAC0_R12DH: mmio.Mmio(packed struct(u32) {
-                ///  DAC0 12-bit right-aligned data
-                DAC0_DH: u12,
-                padding: u20,
-            }),
-            ///  DAC0 12-bit left-aligned data holding register
-            DAC0_L12DH: mmio.Mmio(packed struct(u32) {
-                reserved4: u4,
-                ///  DAC0 12-bit left-aligned data
-                DAC0_DH: u12,
-                padding: u16,
-            }),
-            ///  DAC0 8-bit right aligned data holding register
-            DAC0_R8DH: mmio.Mmio(packed struct(u32) {
-                ///  DAC0 8-bit right-aligned data
-                DAC0_DH: u8,
-                padding: u24,
-            }),
-            ///  DAC1 12-bit right-aligned data holding register
-            DAC1_R12DH: mmio.Mmio(packed struct(u32) {
-                ///  DAC1 12-bit right-aligned data
-                DAC1_DH: u12,
-                padding: u20,
-            }),
-            ///  DAC1 12-bit left aligned data holding register
-            DAC1_L12DH: mmio.Mmio(packed struct(u32) {
-                reserved4: u4,
-                ///  DAC1 12-bit left-aligned data
-                DAC1_DH: u12,
-                padding: u16,
-            }),
-            ///  DAC1 8-bit right aligned data holding register
-            DAC1_R8DH: mmio.Mmio(packed struct(u32) {
-                ///  DAC1 8-bit right-aligned data
-                DAC1_DH: u8,
-                padding: u24,
-            }),
-            ///  DAC concurrent mode 12-bit right-aligned data holding register
-            DACC_R12DH: mmio.Mmio(packed struct(u32) {
-                ///  DAC0 12-bit right-aligned data
-                DAC0_DH: u12,
-                reserved16: u4,
-                ///  DAC1 12-bit right-aligned data
-                DAC1_DH: u12,
-                padding: u4,
-            }),
-            ///  DAC concurrent mode 12-bit left aligned data holding register
-            DACC_L12DH: mmio.Mmio(packed struct(u32) {
-                reserved4: u4,
-                ///  DAC0 12-bit left-aligned data
-                DAC0_DH: u12,
-                reserved20: u4,
-                ///  DAC1 12-bit left-aligned data
-                DAC1_DH: u12,
-            }),
-            ///  DAC concurrent mode 8-bit right aligned data holding register
-            DACC_R8DH: mmio.Mmio(packed struct(u32) {
-                ///  DAC0 8-bit right-aligned data
-                DAC0_DH: u8,
-                ///  DAC1 8-bit right-aligned data
-                DAC1_DH: u8,
-                padding: u16,
-            }),
-            ///  DAC0 data output register
-            DAC0_DO: mmio.Mmio(packed struct(u32) {
-                ///  DAC0 data output
-                DAC0_DO: u12,
-                padding: u20,
-            }),
-            ///  DAC1 data output register
-            DAC1_DO: mmio.Mmio(packed struct(u32) {
-                ///  DAC1 data output
-                DAC1_DO: u12,
-                padding: u20,
-            }),
-        };
-
-        ///  Debug support
-        pub const DBG = extern struct {
-            ///  ID code register
-            ID: mmio.Mmio(packed struct(u32) {
-                ///  DBG ID code register
-                ID_CODE: u32,
-            }),
-            ///  Control register 0
-            CTL: mmio.Mmio(packed struct(u32) {
-                ///  Sleep mode hold register
-                SLP_HOLD: u1,
-                ///  Deep-sleep mode hold register
-                DSLP_HOLD: u1,
-                ///  Standby mode hold register
-                STB_HOLD: u1,
-                reserved8: u5,
-                ///  FWDGT hold bit
-                FWDGT_HOLD: u1,
-                ///  WWDGT hold bit
-                WWDGT_HOLD: u1,
-                ///  TIMER 0 hold bit
-                TIMER0_HOLD: u1,
-                ///  TIMER 1 hold bit
-                TIMER1_HOLD: u1,
-                ///  TIMER 2 hold bit
-                TIMER2_HOLD: u1,
-                ///  TIMER 23 hold bit
-                TIMER3_HOLD: u1,
-                ///  CAN0 hold bit
-                CAN0_HOLD: u1,
-                ///  I2C0 hold bit
-                I2C0_HOLD: u1,
-                ///  I2C1 hold bit
-                I2C1_HOLD: u1,
-                reserved18: u1,
-                ///  TIMER4_HOLD
-                TIMER4_HOLD: u1,
-                ///  TIMER 5 hold bit
-                TIMER5_HOLD: u1,
-                ///  TIMER 6 hold bit
-                TIMER6_HOLD: u1,
-                ///  CAN1 hold bit
-                CAN1_HOLD: u1,
-                padding: u10,
-            }),
-        };
-
-        ///  DMA controller
-        pub const DMA0 = extern struct {
-            ///  Interrupt flag register
-            INTF: mmio.Mmio(packed struct(u32) {
-                ///  Global interrupt flag of channel 0
-                GIF0: u1,
-                ///  Full Transfer finish flag of channe 0
-                FTFIF0: u1,
-                ///  Half transfer finish flag of channel 0
-                HTFIF0: u1,
-                ///  Error flag of channel 0
-                ERRIF0: u1,
-                ///  Global interrupt flag of channel 1
-                GIF1: u1,
-                ///  Full Transfer finish flag of channe 1
-                FTFIF1: u1,
-                ///  Half transfer finish flag of channel 1
-                HTFIF1: u1,
-                ///  Error flag of channel 1
-                ERRIF1: u1,
-                ///  Global interrupt flag of channel 2
-                GIF2: u1,
-                ///  Full Transfer finish flag of channe 2
-                FTFIF2: u1,
-                ///  Half transfer finish flag of channel 2
-                HTFIF2: u1,
-                ///  Error flag of channel 2
-                ERRIF2: u1,
-                ///  Global interrupt flag of channel 3
-                GIF3: u1,
-                ///  Full Transfer finish flag of channe 3
-                FTFIF3: u1,
-                ///  Half transfer finish flag of channel 3
-                HTFIF3: u1,
-                ///  Error flag of channel 3
-                ERRIF3: u1,
-                ///  Global interrupt flag of channel 4
-                GIF4: u1,
-                ///  Full Transfer finish flag of channe 4
-                FTFIF4: u1,
-                ///  Half transfer finish flag of channel 4
-                HTFIF4: u1,
-                ///  Error flag of channel 4
-                ERRIF4: u1,
-                ///  Global interrupt flag of channel 5
-                GIF5: u1,
-                ///  Full Transfer finish flag of channe 5
-                FTFIF5: u1,
-                ///  Half transfer finish flag of channel 5
-                HTFIF5: u1,
-                ///  Error flag of channel 5
-                ERRIF5: u1,
-                ///  Global interrupt flag of channel 6
-                GIF6: u1,
-                ///  Full Transfer finish flag of channe 6
-                FTFIF6: u1,
-                ///  Half transfer finish flag of channel 6
-                HTFIF6: u1,
-                ///  Error flag of channel 6
-                ERRIF6: u1,
-                padding: u4,
-            }),
-            ///  Interrupt flag clear register
-            INTC: mmio.Mmio(packed struct(u32) {
-                ///  Clear global interrupt flag of channel 0
-                GIFC0: u1,
-                ///  Clear bit for full transfer finish flag of channel 0
-                FTFIFC0: u1,
-                ///  Clear bit for half transfer finish flag of channel 0
-                HTFIFC0: u1,
-                ///  Clear bit for error flag of channel 0
-                ERRIFC0: u1,
-                ///  Clear global interrupt flag of channel 1
-                GIFC1: u1,
-                ///  Clear bit for full transfer finish flag of channel 1
-                FTFIFC1: u1,
-                ///  Clear bit for half transfer finish flag of channel 1
-                HTFIFC1: u1,
-                ///  Clear bit for error flag of channel 1
-                ERRIFC1: u1,
-                ///  Clear global interrupt flag of channel 2
-                GIFC2: u1,
-                ///  Clear bit for full transfer finish flag of channel 2
-                FTFIFC2: u1,
-                ///  Clear bit for half transfer finish flag of channel 2
-                HTFIFC2: u1,
-                ///  Clear bit for error flag of channel 2
-                ERRIFC2: u1,
-                ///  Clear global interrupt flag of channel 3
-                GIFC3: u1,
-                ///  Clear bit for full transfer finish flag of channel 3
-                FTFIFC3: u1,
-                ///  Clear bit for half transfer finish flag of channel 3
-                HTFIFC3: u1,
-                ///  Clear bit for error flag of channel 3
-                ERRIFC3: u1,
-                ///  Clear global interrupt flag of channel 4
-                GIFC4: u1,
-                ///  Clear bit for full transfer finish flag of channel 4
-                FTFIFC4: u1,
-                ///  Clear bit for half transfer finish flag of channel 4
-                HTFIFC4: u1,
-                ///  Clear bit for error flag of channel 4
-                ERRIFC4: u1,
-                ///  Clear global interrupt flag of channel 5
-                GIFC5: u1,
-                ///  Clear bit for full transfer finish flag of channel 5
-                FTFIFC5: u1,
-                ///  Clear bit for half transfer finish flag of channel 5
-                HTFIFC5: u1,
-                ///  Clear bit for error flag of channel 5
-                ERRIFC5: u1,
-                ///  Clear global interrupt flag of channel 6
-                GIFC6: u1,
-                ///  Clear bit for full transfer finish flag of channel 6
-                FTFIFC6: u1,
-                ///  Clear bit for half transfer finish flag of channel 6
-                HTFIFC6: u1,
-                ///  Clear bit for error flag of channel 6
-                ERRIFC6: u1,
-                padding: u4,
-            }),
-            ///  Channel 0 control register
-            CH0CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 0 counter register
-            CH0CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 0 peripheral base address register
-            CH0PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 0 memory base address register
-            CH0MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-            reserved28: [4]u8,
-            ///  Channel 1 control register
-            CH1CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 1 counter register
-            CH1CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 1 peripheral base address register
-            CH1PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 1 memory base address register
-            CH1MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-            reserved48: [4]u8,
-            ///  Channel 2 control register
-            CH2CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 2 counter register
-            CH2CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 2 peripheral base address register
-            CH2PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 2 memory base address register
-            CH2MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-            reserved68: [4]u8,
-            ///  Channel 3 control register
-            CH3CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 3 counter register
-            CH3CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 3 peripheral base address register
-            CH3PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 3 memory base address register
-            CH3MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-            reserved88: [4]u8,
-            ///  Channel 4 control register
-            CH4CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 4 counter register
-            CH4CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 4 peripheral base address register
-            CH4PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 4 memory base address register
-            CH4MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-            reserved108: [4]u8,
-            ///  Channel 5 control register
-            CH5CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 5 counter register
-            CH5CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 5 peripheral base address register
-            CH5PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 5 memory base address register
-            CH5MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-            reserved128: [4]u8,
-            ///  Channel 6 control register
-            CH6CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 6 counter register
-            CH6CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 6 peripheral base address register
-            CH6PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 6 memory base address register
-            CH6MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-        };
-
-        ///  Direct memory access controller
-        pub const DMA1 = extern struct {
-            ///  Interrupt flag register
-            INTF: mmio.Mmio(packed struct(u32) {
-                ///  Global interrupt flag of channel 0
-                GIF0: u1,
-                ///  Full Transfer finish flag of channe 0
-                FTFIF0: u1,
-                ///  Half transfer finish flag of channel 0
-                HTFIF0: u1,
-                ///  Error flag of channel 0
-                ERRIF0: u1,
-                ///  Global interrupt flag of channel 1
-                GIF1: u1,
-                ///  Full Transfer finish flag of channe 1
-                FTFIF1: u1,
-                ///  Half transfer finish flag of channel 1
-                HTFIF1: u1,
-                ///  Error flag of channel 1
-                ERRIF1: u1,
-                ///  Global interrupt flag of channel 2
-                GIF2: u1,
-                ///  Full Transfer finish flag of channe 2
-                FTFIF2: u1,
-                ///  Half transfer finish flag of channel 2
-                HTFIF2: u1,
-                ///  Error flag of channel 2
-                ERRIF2: u1,
-                ///  Global interrupt flag of channel 3
-                GIF3: u1,
-                ///  Full Transfer finish flag of channe 3
-                FTFIF3: u1,
-                ///  Half transfer finish flag of channel 3
-                HTFIF3: u1,
-                ///  Error flag of channel 3
-                ERRIF3: u1,
-                ///  Global interrupt flag of channel 4
-                GIF4: u1,
-                ///  Full Transfer finish flag of channe 4
-                FTFIF4: u1,
-                ///  Half transfer finish flag of channel 4
-                HTFIF4: u1,
-                ///  Error flag of channel 4
-                ERRIF4: u1,
-                padding: u12,
-            }),
-            ///  Interrupt flag clear register
-            INTC: mmio.Mmio(packed struct(u32) {
-                ///  Clear global interrupt flag of channel 0
-                GIFC0: u1,
-                ///  Clear bit for full transfer finish flag of channel 0
-                FTFIFC0: u1,
-                ///  Clear bit for half transfer finish flag of channel 0
-                HTFIFC0: u1,
-                ///  Clear bit for error flag of channel 0
-                ERRIFC0: u1,
-                ///  Clear global interrupt flag of channel 1
-                GIFC1: u1,
-                ///  Clear bit for full transfer finish flag of channel 1
-                FTFIFC1: u1,
-                ///  Clear bit for half transfer finish flag of channel 1
-                HTFIFC1: u1,
-                ///  Clear bit for error flag of channel 1
-                ERRIFC1: u1,
-                ///  Clear global interrupt flag of channel 2
-                GIFC2: u1,
-                ///  Clear bit for full transfer finish flag of channel 2
-                FTFIFC2: u1,
-                ///  Clear bit for half transfer finish flag of channel 2
-                HTFIFC2: u1,
-                ///  Clear bit for error flag of channel 2
-                ERRIFC2: u1,
-                ///  Clear global interrupt flag of channel 3
-                GIFC3: u1,
-                ///  Clear bit for full transfer finish flag of channel 3
-                FTFIFC3: u1,
-                ///  Clear bit for half transfer finish flag of channel 3
-                HTFIFC3: u1,
-                ///  Clear bit for error flag of channel 3
-                ERRIFC3: u1,
-                ///  Clear global interrupt flag of channel 4
-                GIFC4: u1,
-                ///  Clear bit for full transfer finish flag of channel 4
-                FTFIFC4: u1,
-                ///  Clear bit for half transfer finish flag of channel 4
-                HTFIFC4: u1,
-                ///  Clear bit for error flag of channel 4
-                ERRIFC4: u1,
-                padding: u12,
-            }),
-            ///  Channel 0 control register
-            CH0CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 0 counter register
-            CH0CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 0 peripheral base address register
-            CH0PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 0 memory base address register
-            CH0MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-            reserved28: [4]u8,
-            ///  Channel 1 control register
-            CH1CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 1 counter register
-            CH1CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 1 peripheral base address register
-            CH1PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 1 memory base address register
-            CH1MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-            reserved48: [4]u8,
-            ///  Channel 2 control register
-            CH2CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 2 counter register
-            CH2CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 2 peripheral base address register
-            CH2PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 2 memory base address register
-            CH2MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-            reserved68: [4]u8,
-            ///  Channel 3 control register
-            CH3CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 3 counter register
-            CH3CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 3 peripheral base address register
-            CH3PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 3 memory base address register
-            CH3MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-            reserved88: [4]u8,
-            ///  Channel 4 control register
-            CH4CTL: mmio.Mmio(packed struct(u32) {
-                ///  Channel enable
-                CHEN: u1,
-                ///  Enable bit for channel full transfer finish interrupt
-                FTFIE: u1,
-                ///  Enable bit for channel half transfer finish interrupt
-                HTFIE: u1,
-                ///  Enable bit for channel error interrupt
-                ERRIE: u1,
-                ///  Transfer direction
-                DIR: u1,
-                ///  Circular mode enable
-                CMEN: u1,
-                ///  Next address generation algorithm of peripheral
-                PNAGA: u1,
-                ///  Next address generation algorithm of memory
-                MNAGA: u1,
-                ///  Transfer data size of peripheral
-                PWIDTH: u2,
-                ///  Transfer data size of memory
-                MWIDTH: u2,
-                ///  Priority level
-                PRIO: u2,
-                ///  Memory to Memory Mode
-                M2M: u1,
-                padding: u17,
-            }),
-            ///  Channel 4 counter register
-            CH4CNT: mmio.Mmio(packed struct(u32) {
-                ///  Transfer counter
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  Channel 4 peripheral base address register
-            CH4PADDR: mmio.Mmio(packed struct(u32) {
-                ///  Peripheral base address
-                PADDR: u32,
-            }),
-            ///  Channel 4 memory base address register
-            CH4MADDR: mmio.Mmio(packed struct(u32) {
-                ///  Memory base address
-                MADDR: u32,
-            }),
-        };
-
-        ///  External memory controller
-        pub const EXMC = extern struct {
-            ///  SRAM/NOR flash control register 0
-            SNCTL0: mmio.Mmio(packed struct(u32) {
-                ///  NOR bank enable
-                NRBKEN: u1,
-                ///  NOR bank memory address/data multiplexing
-                NRMUX: u1,
-                ///  NOR bank memory type
-                NRTP: u2,
-                ///  NOR bank memory data bus width
-                NRW: u2,
-                ///  NOR Flash access enable
-                NREN: u1,
-                reserved9: u2,
-                ///  NWAIT signal polarity
-                NRWTPOL: u1,
-                reserved12: u2,
-                ///  Write enable
-                WREN: u1,
-                ///  NWAIT signal enable
-                NRWTEN: u1,
-                reserved15: u1,
-                ///  Asynchronous wait
-                ASYNCWAIT: u1,
-                padding: u16,
-            }),
-            ///  SRAM/NOR flash timing configuration register 0
-            SNTCFG0: mmio.Mmio(packed struct(u32) {
-                ///  Address setup time
-                ASET: u4,
-                ///  Address hold time
-                AHLD: u4,
-                ///  Data setup time
-                DSET: u8,
-                ///  Bus latency
-                BUSLAT: u4,
-                padding: u12,
-            }),
-            ///  SRAM/NOR flash control register 1
-            SNCTL1: mmio.Mmio(packed struct(u32) {
-                ///  NOR bank enable
-                NRBKEN: u1,
-                ///  NOR bank memory address/data multiplexing
-                NRMUX: u1,
-                ///  NOR bank memory type
-                NRTP: u2,
-                ///  NOR bank memory data bus width
-                NRW: u2,
-                ///  NOR Flash access enable
-                NREN: u1,
-                reserved9: u2,
-                ///  NWAIT signal polarity
-                NRWTPOL: u1,
-                reserved12: u2,
-                ///  Write enable
-                WREN: u1,
-                ///  NWAIT signal enable
-                NRWTEN: u1,
-                reserved15: u1,
-                ///  Asynchronous wait
-                ASYNCWAIT: u1,
-                padding: u16,
-            }),
-        };
-
-        ///  External interrupt/event controller
-        pub const EXTI = extern struct {
-            ///  Interrupt enable register (EXTI_INTEN)
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable Interrupt on line 0
-                INTEN0: u1,
-                ///  Enable Interrupt on line 1
-                INTEN1: u1,
-                ///  Enable Interrupt on line 2
-                INTEN2: u1,
-                ///  Enable Interrupt on line 3
-                INTEN3: u1,
-                ///  Enable Interrupt on line 4
-                INTEN4: u1,
-                ///  Enable Interrupt on line 5
-                INTEN5: u1,
-                ///  Enable Interrupt on line 6
-                INTEN6: u1,
-                ///  Enable Interrupt on line 7
-                INTEN7: u1,
-                ///  Enable Interrupt on line 8
-                INTEN8: u1,
-                ///  Enable Interrupt on line 9
-                INTEN9: u1,
-                ///  Enable Interrupt on line 10
-                INTEN10: u1,
-                ///  Enable Interrupt on line 11
-                INTEN11: u1,
-                ///  Enable Interrupt on line 12
-                INTEN12: u1,
-                ///  Enable Interrupt on line 13
-                INTEN13: u1,
-                ///  Enable Interrupt on line 14
-                INTEN14: u1,
-                ///  Enable Interrupt on line 15
-                INTEN15: u1,
-                ///  Enable Interrupt on line 16
-                INTEN16: u1,
-                ///  Enable Interrupt on line 17
-                INTEN17: u1,
-                ///  Enable Interrupt on line 18
-                INTEN18: u1,
-                padding: u13,
-            }),
-            ///  Event enable register (EXTI_EVEN)
-            EVEN: mmio.Mmio(packed struct(u32) {
-                ///  Enable Event on line 0
-                EVEN0: u1,
-                ///  Enable Event on line 1
-                EVEN1: u1,
-                ///  Enable Event on line 2
-                EVEN2: u1,
-                ///  Enable Event on line 3
-                EVEN3: u1,
-                ///  Enable Event on line 4
-                EVEN4: u1,
-                ///  Enable Event on line 5
-                EVEN5: u1,
-                ///  Enable Event on line 6
-                EVEN6: u1,
-                ///  Enable Event on line 7
-                EVEN7: u1,
-                ///  Enable Event on line 8
-                EVEN8: u1,
-                ///  Enable Event on line 9
-                EVEN9: u1,
-                ///  Enable Event on line 10
-                EVEN10: u1,
-                ///  Enable Event on line 11
-                EVEN11: u1,
-                ///  Enable Event on line 12
-                EVEN12: u1,
-                ///  Enable Event on line 13
-                EVEN13: u1,
-                ///  Enable Event on line 14
-                EVEN14: u1,
-                ///  Enable Event on line 15
-                EVEN15: u1,
-                ///  Enable Event on line 16
-                EVEN16: u1,
-                ///  Enable Event on line 17
-                EVEN17: u1,
-                ///  Enable Event on line 18
-                EVEN18: u1,
-                padding: u13,
-            }),
-            ///  Rising Edge Trigger Enable register (EXTI_RTEN)
-            RTEN: mmio.Mmio(packed struct(u32) {
-                ///  Rising edge trigger enable of line 0
-                RTEN0: u1,
-                ///  Rising edge trigger enable of line 1
-                RTEN1: u1,
-                ///  Rising edge trigger enable of line 2
-                RTEN2: u1,
-                ///  Rising edge trigger enable of line 3
-                RTEN3: u1,
-                ///  Rising edge trigger enable of line 4
-                RTEN4: u1,
-                ///  Rising edge trigger enable of line 5
-                RTEN5: u1,
-                ///  Rising edge trigger enable of line 6
-                RTEN6: u1,
-                ///  Rising edge trigger enable of line 7
-                RTEN7: u1,
-                ///  Rising edge trigger enable of line 8
-                RTEN8: u1,
-                ///  Rising edge trigger enable of line 9
-                RTEN9: u1,
-                ///  Rising edge trigger enable of line 10
-                RTEN10: u1,
-                ///  Rising edge trigger enable of line 11
-                RTEN11: u1,
-                ///  Rising edge trigger enable of line 12
-                RTEN12: u1,
-                ///  Rising edge trigger enable of line 13
-                RTEN13: u1,
-                ///  Rising edge trigger enable of line 14
-                RTEN14: u1,
-                ///  Rising edge trigger enable of line 15
-                RTEN15: u1,
-                ///  Rising edge trigger enable of line 16
-                RTEN16: u1,
-                ///  Rising edge trigger enable of line 17
-                RTEN17: u1,
-                ///  Rising edge trigger enable of line 18
-                RTEN18: u1,
-                padding: u13,
-            }),
-            ///  Falling Egde Trigger Enable register (EXTI_FTEN)
-            FTEN: mmio.Mmio(packed struct(u32) {
-                ///  Falling edge trigger enable of line 0
-                FTEN0: u1,
-                ///  Falling edge trigger enable of line 1
-                FTEN1: u1,
-                ///  Falling edge trigger enable of line 2
-                FTEN2: u1,
-                ///  Falling edge trigger enable of line 3
-                FTEN3: u1,
-                ///  Falling edge trigger enable of line 4
-                FTEN4: u1,
-                ///  Falling edge trigger enable of line 5
-                FTEN5: u1,
-                ///  Falling edge trigger enable of line 6
-                FTEN6: u1,
-                ///  Falling edge trigger enable of line 7
-                FTEN7: u1,
-                ///  Falling edge trigger enable of line 8
-                FTEN8: u1,
-                ///  Falling edge trigger enable of line 9
-                FTEN9: u1,
-                ///  Falling edge trigger enable of line 10
-                FTEN10: u1,
-                ///  Falling edge trigger enable of line 11
-                FTEN11: u1,
-                ///  Falling edge trigger enable of line 12
-                FTEN12: u1,
-                ///  Falling edge trigger enable of line 13
-                FTEN13: u1,
-                ///  Falling edge trigger enable of line 14
-                FTEN14: u1,
-                ///  Falling edge trigger enable of line 15
-                FTEN15: u1,
-                ///  Falling edge trigger enable of line 16
-                FTEN16: u1,
-                ///  Falling edge trigger enable of line 17
-                FTEN17: u1,
-                ///  Falling edge trigger enable of line 18
-                FTEN18: u1,
-                padding: u13,
-            }),
-            ///  Software interrupt event register (EXTI_SWIEV)
-            SWIEV: mmio.Mmio(packed struct(u32) {
-                ///  Interrupt/Event software trigger on line 0
-                SWIEV0: u1,
-                ///  Interrupt/Event software trigger on line 1
-                SWIEV1: u1,
-                ///  Interrupt/Event software trigger on line 2
-                SWIEV2: u1,
-                ///  Interrupt/Event software trigger on line 3
-                SWIEV3: u1,
-                ///  Interrupt/Event software trigger on line 4
-                SWIEV4: u1,
-                ///  Interrupt/Event software trigger on line 5
-                SWIEV5: u1,
-                ///  Interrupt/Event software trigger on line 6
-                SWIEV6: u1,
-                ///  Interrupt/Event software trigger on line 7
-                SWIEV7: u1,
-                ///  Interrupt/Event software trigger on line 8
-                SWIEV8: u1,
-                ///  Interrupt/Event software trigger on line 9
-                SWIEV9: u1,
-                ///  Interrupt/Event software trigger on line 10
-                SWIEV10: u1,
-                ///  Interrupt/Event software trigger on line 11
-                SWIEV11: u1,
-                ///  Interrupt/Event software trigger on line 12
-                SWIEV12: u1,
-                ///  Interrupt/Event software trigger on line 13
-                SWIEV13: u1,
-                ///  Interrupt/Event software trigger on line 14
-                SWIEV14: u1,
-                ///  Interrupt/Event software trigger on line 15
-                SWIEV15: u1,
-                ///  Interrupt/Event software trigger on line 16
-                SWIEV16: u1,
-                ///  Interrupt/Event software trigger on line 17
-                SWIEV17: u1,
-                ///  Interrupt/Event software trigger on line 18
-                SWIEV18: u1,
-                padding: u13,
-            }),
-            ///  Pending register (EXTI_PD)
-            PD: mmio.Mmio(packed struct(u32) {
-                ///  Interrupt pending status of line 0
-                PD0: u1,
-                ///  Interrupt pending status of line 1
-                PD1: u1,
-                ///  Interrupt pending status of line 2
-                PD2: u1,
-                ///  Interrupt pending status of line 3
-                PD3: u1,
-                ///  Interrupt pending status of line 4
-                PD4: u1,
-                ///  Interrupt pending status of line 5
-                PD5: u1,
-                ///  Interrupt pending status of line 6
-                PD6: u1,
-                ///  Interrupt pending status of line 7
-                PD7: u1,
-                ///  Interrupt pending status of line 8
-                PD8: u1,
-                ///  Interrupt pending status of line 9
-                PD9: u1,
-                ///  Interrupt pending status of line 10
-                PD10: u1,
-                ///  Interrupt pending status of line 11
-                PD11: u1,
-                ///  Interrupt pending status of line 12
-                PD12: u1,
-                ///  Interrupt pending status of line 13
-                PD13: u1,
-                ///  Interrupt pending status of line 14
-                PD14: u1,
-                ///  Interrupt pending status of line 15
-                PD15: u1,
-                ///  Interrupt pending status of line 16
-                PD16: u1,
-                ///  Interrupt pending status of line 17
-                PD17: u1,
-                ///  Interrupt pending status of line 18
-                PD18: u1,
-                padding: u13,
-            }),
-        };
-
-        ///  FMC
-        pub const FMC = extern struct {
-            ///  wait state counter register
-            WS: mmio.Mmio(packed struct(u32) {
-                ///  wait state counter register
-                WSCNT: u3,
-                padding: u29,
-            }),
-            ///  Unlock key register 0
-            KEY0: mmio.Mmio(packed struct(u32) {
-                ///  FMC_CTL0 unlock key
-                KEY: u32,
-            }),
-            ///  Option byte unlock key register
-            OBKEY: mmio.Mmio(packed struct(u32) {
-                ///  FMC_ CTL0 option byte operation unlock register
-                OBKEY: u32,
-            }),
-            ///  Status register 0
-            STAT0: mmio.Mmio(packed struct(u32) {
-                ///  The flash is busy bit
-                BUSY: u1,
-                reserved2: u1,
-                ///  Program error flag bit
-                PGERR: u1,
-                reserved4: u1,
-                ///  Erase/Program protection error flag bit
-                WPERR: u1,
-                ///  End of operation flag bit
-                ENDF: u1,
-                padding: u26,
-            }),
-            ///  Control register 0
-            CTL0: mmio.Mmio(packed struct(u32) {
-                ///  Main flash program for bank0 command bit
-                PG: u1,
-                ///  Main flash page erase for bank0 command bit
-                PER: u1,
-                ///  Main flash mass erase for bank0 command bit
-                MER: u1,
-                reserved4: u1,
-                ///  Option bytes program command bit
-                OBPG: u1,
-                ///  Option bytes erase command bit
-                OBER: u1,
-                ///  Send erase command to FMC bit
-                START: u1,
-                ///  FMC_CTL0 lock bit
-                LK: u1,
-                reserved9: u1,
-                ///  Option byte erase/program enable bit
-                OBWEN: u1,
-                ///  Error interrupt enable bit
-                ERRIE: u1,
-                reserved12: u1,
-                ///  End of operation interrupt enable bit
-                ENDIE: u1,
-                padding: u19,
-            }),
-            ///  Address register 0
-            ADDR0: mmio.Mmio(packed struct(u32) {
-                ///  Flash erase/program command address bits
-                ADDR: u32,
-            }),
-            reserved28: [4]u8,
-            ///  Option byte status register
-            OBSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Option bytes read error bit
-                OBERR: u1,
-                ///  Option bytes security protection code
-                SPC: u1,
-                ///  Store USER of option bytes block after system reset
-                USER: u8,
-                ///  Store DATA[15:0] of option bytes block after system reset
-                DATA: u16,
-                padding: u6,
-            }),
-            ///  Erase/Program Protection register
-            WP: mmio.Mmio(packed struct(u32) {
-                ///  Store WP[31:0] of option bytes block after system reset
-                WP: u32,
-            }),
-            reserved256: [220]u8,
-            ///  Product ID register
-            PID: mmio.Mmio(packed struct(u32) {
-                ///  Product reserved ID code register
-                PID: u32,
-            }),
-        };
-
-        ///  free watchdog timer
-        pub const FWDGT = extern struct {
-            ///  Control register
-            CTL: mmio.Mmio(packed struct(u32) {
-                ///  Key value
-                CMD: u16,
-                padding: u16,
-            }),
-            ///  Prescaler register
-            PSC: mmio.Mmio(packed struct(u32) {
-                ///  Free watchdog timer prescaler selection
-                PSC: u3,
-                padding: u29,
-            }),
-            ///  Reload register
-            RLD: mmio.Mmio(packed struct(u32) {
-                ///  Free watchdog timer counter reload value
-                RLD: u12,
-                padding: u20,
-            }),
-            ///  Status register
-            STAT: mmio.Mmio(packed struct(u32) {
-                ///  Free watchdog timer prescaler value update
-                PUD: u1,
-                ///  Free watchdog timer counter reload value update
-                RUD: u1,
-                padding: u30,
-            }),
-        };
-
-        ///  General-purpose I/Os
-        pub const GPIOA = extern struct {
-            ///  port control register 0
-            CTL0: mmio.Mmio(packed struct(u32) {
-                ///  Port x mode bits (x = 0)
-                MD0: u2,
-                ///  Port x configuration bits (x = 0)
-                CTL0: u2,
-                ///  Port x mode bits (x = 1)
-                MD1: u2,
-                ///  Port x configuration bits (x = 1)
-                CTL1: u2,
-                ///  Port x mode bits (x = 2 )
-                MD2: u2,
-                ///  Port x configuration bits (x = 2)
-                CTL2: u2,
-                ///  Port x mode bits (x = 3 )
-                MD3: u2,
-                ///  Port x configuration bits (x = 3)
-                CTL3: u2,
-                ///  Port x mode bits (x = 4)
-                MD4: u2,
-                ///  Port x configuration bits (x = 4)
-                CTL4: u2,
-                ///  Port x mode bits (x = 5)
-                MD5: u2,
-                ///  Port x configuration bits (x = 5)
-                CTL5: u2,
-                ///  Port x mode bits (x = 6)
-                MD6: u2,
-                ///  Port x configuration bits (x = 6)
-                CTL6: u2,
-                ///  Port x mode bits (x = 7)
-                MD7: u2,
-                ///  Port x configuration bits (x = 7)
-                CTL7: u2,
-            }),
-            ///  port control register 1
-            CTL1: mmio.Mmio(packed struct(u32) {
-                ///  Port x mode bits (x = 8)
-                MD8: u2,
-                ///  Port x configuration bits (x = 8)
-                CTL8: u2,
-                ///  Port x mode bits (x = 9)
-                MD9: u2,
-                ///  Port x configuration bits (x = 9)
-                CTL9: u2,
-                ///  Port x mode bits (x = 10 )
-                MD10: u2,
-                ///  Port x configuration bits (x = 10)
-                CTL10: u2,
-                ///  Port x mode bits (x = 11 )
-                MD11: u2,
-                ///  Port x configuration bits (x = 11)
-                CTL11: u2,
-                ///  Port x mode bits (x = 12)
-                MD12: u2,
-                ///  Port x configuration bits (x = 12)
-                CTL12: u2,
-                ///  Port x mode bits (x = 13)
-                MD13: u2,
-                ///  Port x configuration bits (x = 13)
-                CTL13: u2,
-                ///  Port x mode bits (x = 14)
-                MD14: u2,
-                ///  Port x configuration bits (x = 14)
-                CTL14: u2,
-                ///  Port x mode bits (x = 15)
-                MD15: u2,
-                ///  Port x configuration bits (x = 15)
-                CTL15: u2,
-            }),
-            ///  Port input status register
-            ISTAT: mmio.Mmio(packed struct(u32) {
-                ///  Port input status
-                ISTAT0: u1,
-                ///  Port input status
-                ISTAT1: u1,
-                ///  Port input status
-                ISTAT2: u1,
-                ///  Port input status
-                ISTAT3: u1,
-                ///  Port input status
-                ISTAT4: u1,
-                ///  Port input status
-                ISTAT5: u1,
-                ///  Port input status
-                ISTAT6: u1,
-                ///  Port input status
-                ISTAT7: u1,
-                ///  Port input status
-                ISTAT8: u1,
-                ///  Port input status
-                ISTAT9: u1,
-                ///  Port input status
-                ISTAT10: u1,
-                ///  Port input status
-                ISTAT11: u1,
-                ///  Port input status
-                ISTAT12: u1,
-                ///  Port input status
-                ISTAT13: u1,
-                ///  Port input status
-                ISTAT14: u1,
-                ///  Port input status
-                ISTAT15: u1,
-                padding: u16,
-            }),
-            ///  Port output control register
-            OCTL: mmio.Mmio(packed struct(u32) {
-                ///  Port output control
-                OCTL0: u1,
-                ///  Port output control
-                OCTL1: u1,
-                ///  Port output control
-                OCTL2: u1,
-                ///  Port output control
-                OCTL3: u1,
-                ///  Port output control
-                OCTL4: u1,
-                ///  Port output control
-                OCTL5: u1,
-                ///  Port output control
-                OCTL6: u1,
-                ///  Port output control
-                OCTL7: u1,
-                ///  Port output control
-                OCTL8: u1,
-                ///  Port output control
-                OCTL9: u1,
-                ///  Port output control
-                OCTL10: u1,
-                ///  Port output control
-                OCTL11: u1,
-                ///  Port output control
-                OCTL12: u1,
-                ///  Port output control
-                OCTL13: u1,
-                ///  Port output control
-                OCTL14: u1,
-                ///  Port output control
-                OCTL15: u1,
-                padding: u16,
-            }),
-            ///  Port bit operate register
-            BOP: mmio.Mmio(packed struct(u32) {
-                ///  Port 0 Set bit
-                BOP0: u1,
-                ///  Port 1 Set bit
-                BOP1: u1,
-                ///  Port 2 Set bit
-                BOP2: u1,
-                ///  Port 3 Set bit
-                BOP3: u1,
-                ///  Port 4 Set bit
-                BOP4: u1,
-                ///  Port 5 Set bit
-                BOP5: u1,
-                ///  Port 6 Set bit
-                BOP6: u1,
-                ///  Port 7 Set bit
-                BOP7: u1,
-                ///  Port 8 Set bit
-                BOP8: u1,
-                ///  Port 9 Set bit
-                BOP9: u1,
-                ///  Port 10 Set bit
-                BOP10: u1,
-                ///  Port 11 Set bit
-                BOP11: u1,
-                ///  Port 12 Set bit
-                BOP12: u1,
-                ///  Port 13 Set bit
-                BOP13: u1,
-                ///  Port 14 Set bit
-                BOP14: u1,
-                ///  Port 15 Set bit
-                BOP15: u1,
-                ///  Port 0 Clear bit
-                CR0: u1,
-                ///  Port 1 Clear bit
-                CR1: u1,
-                ///  Port 2 Clear bit
-                CR2: u1,
-                ///  Port 3 Clear bit
-                CR3: u1,
-                ///  Port 4 Clear bit
-                CR4: u1,
-                ///  Port 5 Clear bit
-                CR5: u1,
-                ///  Port 6 Clear bit
-                CR6: u1,
-                ///  Port 7 Clear bit
-                CR7: u1,
-                ///  Port 8 Clear bit
-                CR8: u1,
-                ///  Port 9 Clear bit
-                CR9: u1,
-                ///  Port 10 Clear bit
-                CR10: u1,
-                ///  Port 11 Clear bit
-                CR11: u1,
-                ///  Port 12 Clear bit
-                CR12: u1,
-                ///  Port 13 Clear bit
-                CR13: u1,
-                ///  Port 14 Clear bit
-                CR14: u1,
-                ///  Port 15 Clear bit
-                CR15: u1,
-            }),
-            ///  Port bit clear register
-            BC: mmio.Mmio(packed struct(u32) {
-                ///  Port 0 Clear bit
-                CR0: u1,
-                ///  Port 1 Clear bit
-                CR1: u1,
-                ///  Port 2 Clear bit
-                CR2: u1,
-                ///  Port 3 Clear bit
-                CR3: u1,
-                ///  Port 4 Clear bit
-                CR4: u1,
-                ///  Port 5 Clear bit
-                CR5: u1,
-                ///  Port 6 Clear bit
-                CR6: u1,
-                ///  Port 7 Clear bit
-                CR7: u1,
-                ///  Port 8 Clear bit
-                CR8: u1,
-                ///  Port 9 Clear bit
-                CR9: u1,
-                ///  Port 10 Clear bit
-                CR10: u1,
-                ///  Port 11 Clear bit
-                CR11: u1,
-                ///  Port 12 Clear bit
-                CR12: u1,
-                ///  Port 13 Clear bit
-                CR13: u1,
-                ///  Port 14 Clear bit
-                CR14: u1,
-                ///  Port 15 Clear bit
-                CR15: u1,
-                padding: u16,
-            }),
-            ///  GPIO port configuration lock register
-            LOCK: mmio.Mmio(packed struct(u32) {
-                ///  Port Lock bit 0
-                LK0: u1,
-                ///  Port Lock bit 1
-                LK1: u1,
-                ///  Port Lock bit 2
-                LK2: u1,
-                ///  Port Lock bit 3
-                LK3: u1,
-                ///  Port Lock bit 4
-                LK4: u1,
-                ///  Port Lock bit 5
-                LK5: u1,
-                ///  Port Lock bit 6
-                LK6: u1,
-                ///  Port Lock bit 7
-                LK7: u1,
-                ///  Port Lock bit 8
-                LK8: u1,
-                ///  Port Lock bit 9
-                LK9: u1,
-                ///  Port Lock bit 10
-                LK10: u1,
-                ///  Port Lock bit 11
-                LK11: u1,
-                ///  Port Lock bit 12
-                LK12: u1,
-                ///  Port Lock bit 13
-                LK13: u1,
-                ///  Port Lock bit 14
-                LK14: u1,
-                ///  Port Lock bit 15
-                LK15: u1,
-                ///  Lock sequence key
-                LKK: u1,
-                padding: u15,
-            }),
-        };
-
-        ///  USB on the go full speed
-        pub const USBFS_PWRCLK = extern struct {
-            ///  power and clock gating control register (PWRCLKCTL)
-            PWRCLKCTL: mmio.Mmio(packed struct(u32) {
-                ///  Stop the USB clock
-                SUCLK: u1,
-                ///  Stop HCLK
-                SHCLK: u1,
-                padding: u30,
-            }),
-        };
-
-        ///  USB on the go full speed device
-        pub const USBFS_DEVICE = extern struct {
-            ///  device configuration register (DCFG)
-            DCFG: mmio.Mmio(packed struct(u32) {
-                ///  Device speed
-                DS: u2,
-                ///  Non-zero-length status OUT handshake
-                NZLSOH: u1,
-                reserved4: u1,
-                ///  Device address
-                DAR: u7,
-                ///  end of periodic frame time
-                EOPFT: u2,
-                padding: u19,
-            }),
-            ///  device control register (DCTL)
-            DCTL: mmio.Mmio(packed struct(u32) {
-                ///  Remote wakeup
-                RWKUP: u1,
-                ///  Soft disconnect
-                SD: u1,
-                ///  Global IN NAK status
-                GINS: u1,
-                ///  Global OUT NAK status
-                GONS: u1,
-                reserved7: u3,
-                ///  Set global IN NAK
-                SGINAK: u1,
-                ///  Clear global IN NAK
-                CGINAK: u1,
-                ///  Set global OUT NAK
-                SGONAK: u1,
-                ///  Clear global OUT NAK
-                CGONAK: u1,
-                ///  Power-on initialization flag
-                POIF: u1,
-                padding: u20,
-            }),
-            ///  device status register (DSTAT)
-            DSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Suspend status
-                SPST: u1,
-                ///  Enumerated speed
-                ES: u2,
-                reserved8: u5,
-                ///  Frame number of the received SOF
-                FNRSOF: u14,
-                padding: u10,
-            }),
-            reserved16: [4]u8,
-            ///  device IN endpoint common interrupt mask register (DIEPINTEN)
-            DIEPINTEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished interrupt enable
-                TFEN: u1,
-                ///  Endpoint disabled interrupt enable
-                EPDISEN: u1,
-                reserved3: u1,
-                ///  Control IN timeout condition interrupt enable (Non-isochronous endpoints)
-                CITOEN: u1,
-                ///  Endpoint Tx FIFO underrun interrupt enable bit
-                EPTXFUDEN: u1,
-                reserved6: u1,
-                ///  IN endpoint NAK effective interrupt enable
-                IEPNEEN: u1,
-                padding: u25,
-            }),
-            ///  device OUT endpoint common interrupt enable register (DOEPINTEN)
-            DOEPINTEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished interrupt enable
-                TFEN: u1,
-                ///  Endpoint disabled interrupt enable
-                EPDISEN: u1,
-                reserved3: u1,
-                ///  SETUP phase finished interrupt enable
-                STPFEN: u1,
-                ///  Endpoint Rx FIFO overrun interrupt enable
-                EPRXFOVREN: u1,
-                reserved6: u1,
-                ///  Back-to-back SETUP packets interrupt enable
-                BTBSTPEN: u1,
-                padding: u25,
-            }),
-            ///  device all endpoints interrupt register (DAEPINT)
-            DAEPINT: mmio.Mmio(packed struct(u32) {
-                ///  Device all IN endpoint interrupt bits
-                IEPITB: u4,
-                reserved16: u12,
-                ///  Device all OUT endpoint interrupt bits
-                OEPITB: u4,
-                padding: u12,
-            }),
-            ///  Device all endpoints interrupt enable register (DAEPINTEN)
-            DAEPINTEN: mmio.Mmio(packed struct(u32) {
-                ///  IN EP interrupt interrupt enable bits
-                IEPIE: u4,
-                reserved16: u12,
-                ///  OUT endpoint interrupt enable bits
-                OEPIE: u4,
-                padding: u12,
-            }),
-            reserved40: [8]u8,
-            ///  device VBUS discharge time register
-            DVBUSDT: mmio.Mmio(packed struct(u32) {
-                ///  Device VBUS discharge time
-                DVBUSDT: u16,
-                padding: u16,
-            }),
-            ///  device VBUS pulsing time register
-            DVBUSPT: mmio.Mmio(packed struct(u32) {
-                ///  Device VBUS pulsing time
-                DVBUSPT: u12,
-                padding: u20,
-            }),
-            reserved52: [4]u8,
-            ///  device IN endpoint FIFO empty interrupt enable register
-            DIEPFEINTEN: mmio.Mmio(packed struct(u32) {
-                ///  IN EP Tx FIFO empty interrupt enable bits
-                IEPTXFEIE: u4,
-                padding: u28,
-            }),
-            reserved256: [200]u8,
-            ///  device IN endpoint 0 control register (DIEP0CTL)
-            DIEP0CTL: mmio.Mmio(packed struct(u32) {
-                ///  Maximum packet length
-                MPL: u2,
-                reserved15: u13,
-                ///  endpoint active
-                EPACT: u1,
-                reserved17: u1,
-                ///  NAK status
-                NAKS: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved21: u1,
-                ///  STALL handshake
-                STALL: u1,
-                ///  TxFIFO number
-                TXFNUM: u4,
-                ///  Clear NAK
-                CNAK: u1,
-                ///  Set NAK
-                SNAK: u1,
-                reserved30: u2,
-                ///  Endpoint disable
-                EPD: u1,
-                ///  Endpoint enable
-                EPEN: u1,
-            }),
-            reserved264: [4]u8,
-            ///  device endpoint-0 interrupt register
-            DIEP0INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Endpoint finished
-                EPDIS: u1,
-                reserved3: u1,
-                ///  Control in timeout interrupt
-                CITO: u1,
-                ///  Endpoint Tx FIFO underrun
-                EPTXFUD: u1,
-                reserved6: u1,
-                ///  IN endpoint NAK effective
-                IEPNE: u1,
-                ///  Transmit FIFO empty
-                TXFE: u1,
-                padding: u24,
-            }),
-            reserved272: [4]u8,
-            ///  device IN endpoint-0 transfer length register
-            DIEP0LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u7,
-                reserved19: u12,
-                ///  Packet count
-                PCNT: u2,
-                padding: u11,
-            }),
-            reserved280: [4]u8,
-            ///  device IN endpoint 0 transmit FIFO status register
-            DIEP0TFSTAT: mmio.Mmio(packed struct(u32) {
-                ///  IN endpoint TxFIFO space remaining
-                IEPTFS: u16,
-                padding: u16,
-            }),
-            reserved288: [4]u8,
-            ///  device in endpoint-1 control register
-            DIEP1CTL: mmio.Mmio(packed struct(u32) {
-                ///  maximum packet length
-                MPL: u11,
-                reserved15: u4,
-                ///  Endpoint active
-                EPACT: u1,
-                ///  EOFRM/DPID
-                EOFRM_DPID: u1,
-                ///  NAK status
-                NAKS: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved21: u1,
-                ///  STALL handshake
-                STALL: u1,
-                ///  Tx FIFO number
-                TXFNUM: u4,
-                ///  Clear NAK
-                CNAK: u1,
-                ///  Set NAK
-                SNAK: u1,
-                ///  SD0PID/SEVNFRM
-                SD0PID_SEVENFRM: u1,
-                ///  Set DATA1 PID/Set odd frame
-                SD1PID_SODDFRM: u1,
-                ///  Endpoint disable
-                EPD: u1,
-                ///  Endpoint enable
-                EPEN: u1,
-            }),
-            reserved296: [4]u8,
-            ///  device endpoint-1 interrupt register
-            DIEP1INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Endpoint finished
-                EPDIS: u1,
-                reserved3: u1,
-                ///  Control in timeout interrupt
-                CITO: u1,
-                ///  Endpoint Tx FIFO underrun
-                EPTXFUD: u1,
-                reserved6: u1,
-                ///  IN endpoint NAK effective
-                IEPNE: u1,
-                ///  Transmit FIFO empty
-                TXFE: u1,
-                padding: u24,
-            }),
-            reserved304: [4]u8,
-            ///  device IN endpoint-1 transfer length register
-            DIEP1LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  Multi packet count per frame
-                MCPF: u2,
-                padding: u1,
-            }),
-            reserved312: [4]u8,
-            ///  device IN endpoint 1 transmit FIFO status register
-            DIEP1TFSTAT: mmio.Mmio(packed struct(u32) {
-                ///  IN endpoint TxFIFO space remaining
-                IEPTFS: u16,
-                padding: u16,
-            }),
-            reserved320: [4]u8,
-            ///  device endpoint-2 control register
-            DIEP2CTL: mmio.Mmio(packed struct(u32) {
-                ///  maximum packet length
-                MPL: u11,
-                reserved15: u4,
-                ///  Endpoint active
-                EPACT: u1,
-                ///  EOFRM/DPID
-                EOFRM_DPID: u1,
-                ///  NAK status
-                NAKS: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved21: u1,
-                ///  STALL handshake
-                STALL: u1,
-                ///  Tx FIFO number
-                TXFNUM: u4,
-                ///  Clear NAK
-                CNAK: u1,
-                ///  Set NAK
-                SNAK: u1,
-                ///  SD0PID/SEVNFRM
-                SD0PID_SEVENFRM: u1,
-                ///  Set DATA1 PID/Set odd frame
-                SD1PID_SODDFRM: u1,
-                ///  Endpoint disable
-                EPD: u1,
-                ///  Endpoint enable
-                EPEN: u1,
-            }),
-            reserved328: [4]u8,
-            ///  device endpoint-2 interrupt register
-            DIEP2INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Endpoint finished
-                EPDIS: u1,
-                reserved3: u1,
-                ///  Control in timeout interrupt
-                CITO: u1,
-                ///  Endpoint Tx FIFO underrun
-                EPTXFUD: u1,
-                reserved6: u1,
-                ///  IN endpoint NAK effective
-                IEPNE: u1,
-                ///  Transmit FIFO empty
-                TXFE: u1,
-                padding: u24,
-            }),
-            reserved336: [4]u8,
-            ///  device IN endpoint-2 transfer length register
-            DIEP2LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  Multi packet count per frame
-                MCPF: u2,
-                padding: u1,
-            }),
-            reserved344: [4]u8,
-            ///  device IN endpoint 2 transmit FIFO status register
-            DIEP2TFSTAT: mmio.Mmio(packed struct(u32) {
-                ///  IN endpoint TxFIFO space remaining
-                IEPTFS: u16,
-                padding: u16,
-            }),
-            reserved352: [4]u8,
-            ///  device endpoint-3 control register
-            DIEP3CTL: mmio.Mmio(packed struct(u32) {
-                ///  maximum packet length
-                MPL: u11,
-                reserved15: u4,
-                ///  Endpoint active
-                EPACT: u1,
-                ///  EOFRM/DPID
-                EOFRM_DPID: u1,
-                ///  NAK status
-                NAKS: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved21: u1,
-                ///  STALL handshake
-                STALL: u1,
-                ///  Tx FIFO number
-                TXFNUM: u4,
-                ///  Clear NAK
-                CNAK: u1,
-                ///  Set NAK
-                SNAK: u1,
-                ///  SD0PID/SEVNFRM
-                SD0PID_SEVENFRM: u1,
-                ///  Set DATA1 PID/Set odd frame
-                SD1PID_SODDFRM: u1,
-                ///  Endpoint disable
-                EPD: u1,
-                ///  Endpoint enable
-                EPEN: u1,
-            }),
-            reserved360: [4]u8,
-            ///  device endpoint-3 interrupt register
-            DIEP3INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Endpoint finished
-                EPDIS: u1,
-                reserved3: u1,
-                ///  Control in timeout interrupt
-                CITO: u1,
-                ///  Endpoint Tx FIFO underrun
-                EPTXFUD: u1,
-                reserved6: u1,
-                ///  IN endpoint NAK effective
-                IEPNE: u1,
-                ///  Transmit FIFO empty
-                TXFE: u1,
-                padding: u24,
-            }),
-            reserved368: [4]u8,
-            ///  device IN endpoint-3 transfer length register
-            DIEP3LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  Multi packet count per frame
-                MCPF: u2,
-                padding: u1,
-            }),
-            reserved376: [4]u8,
-            ///  device IN endpoint 3 transmit FIFO status register
-            DIEP3TFSTAT: mmio.Mmio(packed struct(u32) {
-                ///  IN endpoint TxFIFO space remaining
-                IEPTFS: u16,
-                padding: u16,
-            }),
-            reserved768: [388]u8,
-            ///  device endpoint-0 control register
-            DOEP0CTL: mmio.Mmio(packed struct(u32) {
-                ///  Maximum packet length
-                MPL: u2,
-                reserved15: u13,
-                ///  Endpoint active
-                EPACT: u1,
-                reserved17: u1,
-                ///  NAK status
-                NAKS: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                ///  Snoop mode
-                SNOOP: u1,
-                ///  STALL handshake
-                STALL: u1,
-                reserved26: u4,
-                ///  Clear NAK
-                CNAK: u1,
-                ///  Set NAK
-                SNAK: u1,
-                reserved30: u2,
-                ///  Endpoint disable
-                EPD: u1,
-                ///  Endpoint enable
-                EPEN: u1,
-            }),
-            reserved776: [4]u8,
-            ///  device out endpoint-0 interrupt flag register
-            DOEP0INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Endpoint disabled
-                EPDIS: u1,
-                reserved3: u1,
-                ///  Setup phase finished
-                STPF: u1,
-                ///  Endpoint Rx FIFO overrun
-                EPRXFOVR: u1,
-                reserved6: u1,
-                ///  Back-to-back SETUP packets
-                BTBSTP: u1,
-                padding: u25,
-            }),
-            reserved784: [4]u8,
-            ///  device OUT endpoint-0 transfer length register
-            DOEP0LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u7,
-                reserved19: u12,
-                ///  Packet count
-                PCNT: u1,
-                reserved29: u9,
-                ///  SETUP packet count
-                STPCNT: u2,
-                padding: u1,
-            }),
-            reserved800: [12]u8,
-            ///  device endpoint-1 control register
-            DOEP1CTL: mmio.Mmio(packed struct(u32) {
-                ///  maximum packet length
-                MPL: u11,
-                reserved15: u4,
-                ///  Endpoint active
-                EPACT: u1,
-                ///  EOFRM/DPID
-                EOFRM_DPID: u1,
-                ///  NAK status
-                NAKS: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                ///  Snoop mode
-                SNOOP: u1,
-                ///  STALL handshake
-                STALL: u1,
-                reserved26: u4,
-                ///  Clear NAK
-                CNAK: u1,
-                ///  Set NAK
-                SNAK: u1,
-                ///  SD0PID/SEVENFRM
-                SD0PID_SEVENFRM: u1,
-                ///  SD1PID/SODDFRM
-                SD1PID_SODDFRM: u1,
-                ///  Endpoint disable
-                EPD: u1,
-                ///  Endpoint enable
-                EPEN: u1,
-            }),
-            reserved808: [4]u8,
-            ///  device out endpoint-1 interrupt flag register
-            DOEP1INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Endpoint disabled
-                EPDIS: u1,
-                reserved3: u1,
-                ///  Setup phase finished
-                STPF: u1,
-                ///  Endpoint Rx FIFO overrun
-                EPRXFOVR: u1,
-                reserved6: u1,
-                ///  Back-to-back SETUP packets
-                BTBSTP: u1,
-                padding: u25,
-            }),
-            reserved816: [4]u8,
-            ///  device OUT endpoint-1 transfer length register
-            DOEP1LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  SETUP packet count/Received data PID
-                STPCNT_RXDPID: u2,
-                padding: u1,
-            }),
-            reserved832: [12]u8,
-            ///  device endpoint-2 control register
-            DOEP2CTL: mmio.Mmio(packed struct(u32) {
-                ///  maximum packet length
-                MPL: u11,
-                reserved15: u4,
-                ///  Endpoint active
-                EPACT: u1,
-                ///  EOFRM/DPID
-                EOFRM_DPID: u1,
-                ///  NAK status
-                NAKS: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                ///  Snoop mode
-                SNOOP: u1,
-                ///  STALL handshake
-                STALL: u1,
-                reserved26: u4,
-                ///  Clear NAK
-                CNAK: u1,
-                ///  Set NAK
-                SNAK: u1,
-                ///  SD0PID/SEVENFRM
-                SD0PID_SEVENFRM: u1,
-                ///  SD1PID/SODDFRM
-                SD1PID_SODDFRM: u1,
-                ///  Endpoint disable
-                EPD: u1,
-                ///  Endpoint enable
-                EPEN: u1,
-            }),
-            reserved840: [4]u8,
-            ///  device out endpoint-2 interrupt flag register
-            DOEP2INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Endpoint disabled
-                EPDIS: u1,
-                reserved3: u1,
-                ///  Setup phase finished
-                STPF: u1,
-                ///  Endpoint Rx FIFO overrun
-                EPRXFOVR: u1,
-                reserved6: u1,
-                ///  Back-to-back SETUP packets
-                BTBSTP: u1,
-                padding: u25,
-            }),
-            reserved848: [4]u8,
-            ///  device OUT endpoint-2 transfer length register
-            DOEP2LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  SETUP packet count/Received data PID
-                STPCNT_RXDPID: u2,
-                padding: u1,
-            }),
-            reserved864: [12]u8,
-            ///  device endpoint-3 control register
-            DOEP3CTL: mmio.Mmio(packed struct(u32) {
-                ///  maximum packet length
-                MPL: u11,
-                reserved15: u4,
-                ///  Endpoint active
-                EPACT: u1,
-                ///  EOFRM/DPID
-                EOFRM_DPID: u1,
-                ///  NAK status
-                NAKS: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                ///  Snoop mode
-                SNOOP: u1,
-                ///  STALL handshake
-                STALL: u1,
-                reserved26: u4,
-                ///  Clear NAK
-                CNAK: u1,
-                ///  Set NAK
-                SNAK: u1,
-                ///  SD0PID/SEVENFRM
-                SD0PID_SEVENFRM: u1,
-                ///  SD1PID/SODDFRM
-                SD1PID_SODDFRM: u1,
-                ///  Endpoint disable
-                EPD: u1,
-                ///  Endpoint enable
-                EPEN: u1,
-            }),
-            reserved872: [4]u8,
-            ///  device out endpoint-3 interrupt flag register
-            DOEP3INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Endpoint disabled
-                EPDIS: u1,
-                reserved3: u1,
-                ///  Setup phase finished
-                STPF: u1,
-                ///  Endpoint Rx FIFO overrun
-                EPRXFOVR: u1,
-                reserved6: u1,
-                ///  Back-to-back SETUP packets
-                BTBSTP: u1,
-                padding: u25,
-            }),
-            reserved880: [4]u8,
-            ///  device OUT endpoint-3 transfer length register
-            DOEP3LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  SETUP packet count/Received data PID
-                STPCNT_RXDPID: u2,
-                padding: u1,
-            }),
-        };
-
-        ///  USB on the go full speed host
-        pub const USBFS_HOST = extern struct {
-            ///  host configuration register (HCTL)
-            HCTL: mmio.Mmio(packed struct(u32) {
-                ///  clock select for USB clock
-                CLKSEL: u2,
-                padding: u30,
-            }),
-            ///  Host frame interval register
-            HFT: mmio.Mmio(packed struct(u32) {
-                ///  Frame interval
-                FRI: u16,
-                padding: u16,
-            }),
-            ///  FS host frame number/frame time remaining register (HFINFR)
-            HFINFR: mmio.Mmio(packed struct(u32) {
-                ///  Frame number
-                FRNUM: u16,
-                ///  Frame remaining time
-                FRT: u16,
-            }),
-            reserved16: [4]u8,
-            ///  Host periodic transmit FIFO/queue status register (HPTFQSTAT)
-            HPTFQSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Periodic transmit data FIFO space available
-                PTXFS: u16,
-                ///  Periodic transmit request queue space available
-                PTXREQS: u8,
-                ///  Top of the periodic transmit request queue
-                PTXREQT: u8,
-            }),
-            ///  Host all channels interrupt register
-            HACHINT: mmio.Mmio(packed struct(u32) {
-                ///  Host all channel interrupts
-                HACHINT: u8,
-                padding: u24,
-            }),
-            ///  host all channels interrupt mask register
-            HACHINTEN: mmio.Mmio(packed struct(u32) {
-                ///  Channel interrupt enable
-                CINTEN: u8,
-                padding: u24,
-            }),
-            reserved64: [36]u8,
-            ///  Host port control and status register (USBFS_HPCS)
-            HPCS: mmio.Mmio(packed struct(u32) {
-                ///  Port connect status
-                PCST: u1,
-                ///  Port connect detected
-                PCD: u1,
-                ///  Port enable
-                PE: u1,
-                ///  Port enable/disable change
-                PEDC: u1,
-                reserved6: u2,
-                ///  Port resume
-                PREM: u1,
-                ///  Port suspend
-                PSP: u1,
-                ///  Port reset
-                PRST: u1,
-                reserved10: u1,
-                ///  Port line status
-                PLST: u2,
-                ///  Port power
-                PP: u1,
-                reserved17: u4,
-                ///  Port speed
-                PS: u2,
-                padding: u13,
-            }),
-            reserved256: [188]u8,
-            ///  host channel-0 characteristics register (HCH0CTL)
-            HCH0CTL: mmio.Mmio(packed struct(u32) {
-                ///  Maximum packet size
-                MPL: u11,
-                ///  Endpoint number
-                EPNUM: u4,
-                ///  Endpoint direction
-                EPDIR: u1,
-                reserved17: u1,
-                ///  Low-speed device
-                LSD: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved22: u2,
-                ///  Device address
-                DAR: u7,
-                ///  Odd frame
-                ODDFRM: u1,
-                ///  Channel disable
-                CDIS: u1,
-                ///  Channel enable
-                CEN: u1,
-            }),
-            reserved264: [4]u8,
-            ///  host channel-0 interrupt register (USBFS_HCHxINTF)
-            HCH0INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Channel halted
-                CH: u1,
-                reserved3: u1,
-                ///  STALL response received interrupt
-                STALL: u1,
-                ///  NAK response received interrupt
-                NAK: u1,
-                ///  ACK response received/transmitted interrupt
-                ACK: u1,
-                reserved7: u1,
-                ///  USB bus error
-                USBER: u1,
-                ///  Babble error
-                BBER: u1,
-                ///  Request queue overrun
-                REQOVR: u1,
-                ///  Data toggle error
-                DTER: u1,
-                padding: u21,
-            }),
-            ///  host channel-0 interrupt enable register (HCH0INTEN)
-            HCH0INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer completed interrupt enable
-                TFIE: u1,
-                ///  Channel halted interrupt enable
-                CHIE: u1,
-                reserved3: u1,
-                ///  STALL interrupt enable
-                STALLIE: u1,
-                ///  NAK interrupt enable
-                NAKIE: u1,
-                ///  ACK interrupt enable
-                ACKIE: u1,
-                reserved7: u1,
-                ///  USB bus error interrupt enable
-                USBERIE: u1,
-                ///  Babble error interrupt enable
-                BBERIE: u1,
-                ///  request queue overrun interrupt enable
-                REQOVRIE: u1,
-                ///  Data toggle error interrupt enable
-                DTERIE: u1,
-                padding: u21,
-            }),
-            ///  host channel-0 transfer length register
-            HCH0LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  Data PID
-                DPID: u2,
-                padding: u1,
-            }),
-            reserved288: [12]u8,
-            ///  host channel-1 characteristics register (HCH1CTL)
-            HCH1CTL: mmio.Mmio(packed struct(u32) {
-                ///  Maximum packet size
-                MPL: u11,
-                ///  Endpoint number
-                EPNUM: u4,
-                ///  Endpoint direction
-                EPDIR: u1,
-                reserved17: u1,
-                ///  Low-speed device
-                LSD: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved22: u2,
-                ///  Device address
-                DAR: u7,
-                ///  Odd frame
-                ODDFRM: u1,
-                ///  Channel disable
-                CDIS: u1,
-                ///  Channel enable
-                CEN: u1,
-            }),
-            reserved296: [4]u8,
-            ///  host channel-1 interrupt register (HCH1INTF)
-            HCH1INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Channel halted
-                CH: u1,
-                reserved3: u1,
-                ///  STALL response received interrupt
-                STALL: u1,
-                ///  NAK response received interrupt
-                NAK: u1,
-                ///  ACK response received/transmitted interrupt
-                ACK: u1,
-                reserved7: u1,
-                ///  USB bus error
-                USBER: u1,
-                ///  Babble error
-                BBER: u1,
-                ///  Request queue overrun
-                REQOVR: u1,
-                ///  Data toggle error
-                DTER: u1,
-                padding: u21,
-            }),
-            ///  host channel-1 interrupt enable register (HCH1INTEN)
-            HCH1INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer completed interrupt enable
-                TFIE: u1,
-                ///  Channel halted interrupt enable
-                CHIE: u1,
-                reserved3: u1,
-                ///  STALL interrupt enable
-                STALLIE: u1,
-                ///  NAK interrupt enable
-                NAKIE: u1,
-                ///  ACK interrupt enable
-                ACKIE: u1,
-                reserved7: u1,
-                ///  USB bus error interrupt enable
-                USBERIE: u1,
-                ///  Babble error interrupt enable
-                BBERIE: u1,
-                ///  request queue overrun interrupt enable
-                REQOVRIE: u1,
-                ///  Data toggle error interrupt enable
-                DTERIE: u1,
-                padding: u21,
-            }),
-            ///  host channel-1 transfer length register
-            HCH1LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  Data PID
-                DPID: u2,
-                padding: u1,
-            }),
-            reserved320: [12]u8,
-            ///  host channel-2 characteristics register (HCH2CTL)
-            HCH2CTL: mmio.Mmio(packed struct(u32) {
-                ///  Maximum packet size
-                MPL: u11,
-                ///  Endpoint number
-                EPNUM: u4,
-                ///  Endpoint direction
-                EPDIR: u1,
-                reserved17: u1,
-                ///  Low-speed device
-                LSD: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved22: u2,
-                ///  Device address
-                DAR: u7,
-                ///  Odd frame
-                ODDFRM: u1,
-                ///  Channel disable
-                CDIS: u1,
-                ///  Channel enable
-                CEN: u1,
-            }),
-            reserved328: [4]u8,
-            ///  host channel-2 interrupt register (HCH2INTF)
-            HCH2INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Channel halted
-                CH: u1,
-                reserved3: u1,
-                ///  STALL response received interrupt
-                STALL: u1,
-                ///  NAK response received interrupt
-                NAK: u1,
-                ///  ACK response received/transmitted interrupt
-                ACK: u1,
-                reserved7: u1,
-                ///  USB bus error
-                USBER: u1,
-                ///  Babble error
-                BBER: u1,
-                ///  Request queue overrun
-                REQOVR: u1,
-                ///  Data toggle error
-                DTER: u1,
-                padding: u21,
-            }),
-            ///  host channel-2 interrupt enable register (HCH2INTEN)
-            HCH2INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer completed interrupt enable
-                TFIE: u1,
-                ///  Channel halted interrupt enable
-                CHIE: u1,
-                reserved3: u1,
-                ///  STALL interrupt enable
-                STALLIE: u1,
-                ///  NAK interrupt enable
-                NAKIE: u1,
-                ///  ACK interrupt enable
-                ACKIE: u1,
-                reserved7: u1,
-                ///  USB bus error interrupt enable
-                USBERIE: u1,
-                ///  Babble error interrupt enable
-                BBERIE: u1,
-                ///  request queue overrun interrupt enable
-                REQOVRIE: u1,
-                ///  Data toggle error interrupt enable
-                DTERIE: u1,
-                padding: u21,
-            }),
-            ///  host channel-2 transfer length register
-            HCH2LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  Data PID
-                DPID: u2,
-                padding: u1,
-            }),
-            reserved352: [12]u8,
-            ///  host channel-3 characteristics register (HCH3CTL)
-            HCH3CTL: mmio.Mmio(packed struct(u32) {
-                ///  Maximum packet size
-                MPL: u11,
-                ///  Endpoint number
-                EPNUM: u4,
-                ///  Endpoint direction
-                EPDIR: u1,
-                reserved17: u1,
-                ///  Low-speed device
-                LSD: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved22: u2,
-                ///  Device address
-                DAR: u7,
-                ///  Odd frame
-                ODDFRM: u1,
-                ///  Channel disable
-                CDIS: u1,
-                ///  Channel enable
-                CEN: u1,
-            }),
-            reserved360: [4]u8,
-            ///  host channel-3 interrupt register (HCH3INTF)
-            HCH3INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Channel halted
-                CH: u1,
-                reserved3: u1,
-                ///  STALL response received interrupt
-                STALL: u1,
-                ///  NAK response received interrupt
-                NAK: u1,
-                ///  ACK response received/transmitted interrupt
-                ACK: u1,
-                reserved7: u1,
-                ///  USB bus error
-                USBER: u1,
-                ///  Babble error
-                BBER: u1,
-                ///  Request queue overrun
-                REQOVR: u1,
-                ///  Data toggle error
-                DTER: u1,
-                padding: u21,
-            }),
-            ///  host channel-3 interrupt enable register (HCH3INTEN)
-            HCH3INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer completed interrupt enable
-                TFIE: u1,
-                ///  Channel halted interrupt enable
-                CHIE: u1,
-                reserved3: u1,
-                ///  STALL interrupt enable
-                STALLIE: u1,
-                ///  NAK interrupt enable
-                NAKIE: u1,
-                ///  ACK interrupt enable
-                ACKIE: u1,
-                reserved7: u1,
-                ///  USB bus error interrupt enable
-                USBERIE: u1,
-                ///  Babble error interrupt enable
-                BBERIE: u1,
-                ///  request queue overrun interrupt enable
-                REQOVRIE: u1,
-                ///  Data toggle error interrupt enable
-                DTERIE: u1,
-                padding: u21,
-            }),
-            ///  host channel-3 transfer length register
-            HCH3LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  Data PID
-                DPID: u2,
-                padding: u1,
-            }),
-            reserved384: [12]u8,
-            ///  host channel-4 characteristics register (HCH4CTL)
-            HCH4CTL: mmio.Mmio(packed struct(u32) {
-                ///  Maximum packet size
-                MPL: u11,
-                ///  Endpoint number
-                EPNUM: u4,
-                ///  Endpoint direction
-                EPDIR: u1,
-                reserved17: u1,
-                ///  Low-speed device
-                LSD: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved22: u2,
-                ///  Device address
-                DAR: u7,
-                ///  Odd frame
-                ODDFRM: u1,
-                ///  Channel disable
-                CDIS: u1,
-                ///  Channel enable
-                CEN: u1,
-            }),
-            reserved392: [4]u8,
-            ///  host channel-4 interrupt register (HCH4INTF)
-            HCH4INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Channel halted
-                CH: u1,
-                reserved3: u1,
-                ///  STALL response received interrupt
-                STALL: u1,
-                ///  NAK response received interrupt
-                NAK: u1,
-                ///  ACK response received/transmitted interrupt
-                ACK: u1,
-                reserved7: u1,
-                ///  USB bus error
-                USBER: u1,
-                ///  Babble error
-                BBER: u1,
-                ///  Request queue overrun
-                REQOVR: u1,
-                ///  Data toggle error
-                DTER: u1,
-                padding: u21,
-            }),
-            ///  host channel-4 interrupt enable register (HCH4INTEN)
-            HCH4INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer completed interrupt enable
-                TFIE: u1,
-                ///  Channel halted interrupt enable
-                CHIE: u1,
-                reserved3: u1,
-                ///  STALL interrupt enable
-                STALLIE: u1,
-                ///  NAK interrupt enable
-                NAKIE: u1,
-                ///  ACK interrupt enable
-                ACKIE: u1,
-                reserved7: u1,
-                ///  USB bus error interrupt enable
-                USBERIE: u1,
-                ///  Babble error interrupt enable
-                BBERIE: u1,
-                ///  request queue overrun interrupt enable
-                REQOVRIE: u1,
-                ///  Data toggle error interrupt enable
-                DTERIE: u1,
-                padding: u21,
-            }),
-            ///  host channel-4 transfer length register
-            HCH4LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  Data PID
-                DPID: u2,
-                padding: u1,
-            }),
-            reserved416: [12]u8,
-            ///  host channel-5 characteristics register (HCH5CTL)
-            HCH5CTL: mmio.Mmio(packed struct(u32) {
-                ///  Maximum packet size
-                MPL: u11,
-                ///  Endpoint number
-                EPNUM: u4,
-                ///  Endpoint direction
-                EPDIR: u1,
-                reserved17: u1,
-                ///  Low-speed device
-                LSD: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved22: u2,
-                ///  Device address
-                DAR: u7,
-                ///  Odd frame
-                ODDFRM: u1,
-                ///  Channel disable
-                CDIS: u1,
-                ///  Channel enable
-                CEN: u1,
-            }),
-            reserved424: [4]u8,
-            ///  host channel-5 interrupt register (HCH5INTF)
-            HCH5INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Channel halted
-                CH: u1,
-                reserved3: u1,
-                ///  STALL response received interrupt
-                STALL: u1,
-                ///  NAK response received interrupt
-                NAK: u1,
-                ///  ACK response received/transmitted interrupt
-                ACK: u1,
-                reserved7: u1,
-                ///  USB bus error
-                USBER: u1,
-                ///  Babble error
-                BBER: u1,
-                ///  Request queue overrun
-                REQOVR: u1,
-                ///  Data toggle error
-                DTER: u1,
-                padding: u21,
-            }),
-            ///  host channel-5 interrupt enable register (HCH5INTEN)
-            HCH5INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer completed interrupt enable
-                TFIE: u1,
-                ///  Channel halted interrupt enable
-                CHIE: u1,
-                reserved3: u1,
-                ///  STALL interrupt enable
-                STALLIE: u1,
-                ///  NAK interrupt enable
-                NAKIE: u1,
-                ///  ACK interrupt enable
-                ACKIE: u1,
-                reserved7: u1,
-                ///  USB bus error interrupt enable
-                USBERIE: u1,
-                ///  Babble error interrupt enable
-                BBERIE: u1,
-                ///  request queue overrun interrupt enable
-                REQOVRIE: u1,
-                ///  Data toggle error interrupt enable
-                DTERIE: u1,
-                padding: u21,
-            }),
-            ///  host channel-5 transfer length register
-            HCH5LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  Data PID
-                DPID: u2,
-                padding: u1,
-            }),
-            reserved448: [12]u8,
-            ///  host channel-6 characteristics register (HCH6CTL)
-            HCH6CTL: mmio.Mmio(packed struct(u32) {
-                ///  Maximum packet size
-                MPL: u11,
-                ///  Endpoint number
-                EPNUM: u4,
-                ///  Endpoint direction
-                EPDIR: u1,
-                reserved17: u1,
-                ///  Low-speed device
-                LSD: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved22: u2,
-                ///  Device address
-                DAR: u7,
-                ///  Odd frame
-                ODDFRM: u1,
-                ///  Channel disable
-                CDIS: u1,
-                ///  Channel enable
-                CEN: u1,
-            }),
-            reserved456: [4]u8,
-            ///  host channel-6 interrupt register (HCH6INTF)
-            HCH6INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Channel halted
-                CH: u1,
-                reserved3: u1,
-                ///  STALL response received interrupt
-                STALL: u1,
-                ///  NAK response received interrupt
-                NAK: u1,
-                ///  ACK response received/transmitted interrupt
-                ACK: u1,
-                reserved7: u1,
-                ///  USB bus error
-                USBER: u1,
-                ///  Babble error
-                BBER: u1,
-                ///  Request queue overrun
-                REQOVR: u1,
-                ///  Data toggle error
-                DTER: u1,
-                padding: u21,
-            }),
-            ///  host channel-6 interrupt enable register (HCH6INTEN)
-            HCH6INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer completed interrupt enable
-                TFIE: u1,
-                ///  Channel halted interrupt enable
-                CHIE: u1,
-                reserved3: u1,
-                ///  STALL interrupt enable
-                STALLIE: u1,
-                ///  NAK interrupt enable
-                NAKIE: u1,
-                ///  ACK interrupt enable
-                ACKIE: u1,
-                reserved7: u1,
-                ///  USB bus error interrupt enable
-                USBERIE: u1,
-                ///  Babble error interrupt enable
-                BBERIE: u1,
-                ///  request queue overrun interrupt enable
-                REQOVRIE: u1,
-                ///  Data toggle error interrupt enable
-                DTERIE: u1,
-                padding: u21,
-            }),
-            ///  host channel-6 transfer length register
-            HCH6LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  Data PID
-                DPID: u2,
-                padding: u1,
-            }),
-            reserved480: [12]u8,
-            ///  host channel-7 characteristics register (HCH7CTL)
-            HCH7CTL: mmio.Mmio(packed struct(u32) {
-                ///  Maximum packet size
-                MPL: u11,
-                ///  Endpoint number
-                EPNUM: u4,
-                ///  Endpoint direction
-                EPDIR: u1,
-                reserved17: u1,
-                ///  Low-speed device
-                LSD: u1,
-                ///  Endpoint type
-                EPTYPE: u2,
-                reserved22: u2,
-                ///  Device address
-                DAR: u7,
-                ///  Odd frame
-                ODDFRM: u1,
-                ///  Channel disable
-                CDIS: u1,
-                ///  Channel enable
-                CEN: u1,
-            }),
-            reserved488: [4]u8,
-            ///  host channel-7 interrupt register (HCH7INTF)
-            HCH7INTF: mmio.Mmio(packed struct(u32) {
-                ///  Transfer finished
-                TF: u1,
-                ///  Channel halted
-                CH: u1,
-                reserved3: u1,
-                ///  STALL response received interrupt
-                STALL: u1,
-                ///  NAK response received interrupt
-                NAK: u1,
-                ///  ACK response received/transmitted interrupt
-                ACK: u1,
-                reserved7: u1,
-                ///  USB bus error
-                USBER: u1,
-                ///  Babble error
-                BBER: u1,
-                ///  Request queue overrun
-                REQOVR: u1,
-                ///  Data toggle error
-                DTER: u1,
-                padding: u21,
-            }),
-            ///  host channel-7 interrupt enable register (HCH7INTEN)
-            HCH7INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer completed interrupt enable
-                TFIE: u1,
-                ///  Channel halted interrupt enable
-                CHIE: u1,
-                reserved3: u1,
-                ///  STALL interrupt enable
-                STALLIE: u1,
-                ///  NAK interrupt enable
-                NAKIE: u1,
-                ///  ACK interrupt enable
-                ACKIE: u1,
-                reserved7: u1,
-                ///  USB bus error interrupt enable
-                USBERIE: u1,
-                ///  Babble error interrupt enable
-                BBERIE: u1,
-                ///  request queue overrun interrupt enable
-                REQOVRIE: u1,
-                ///  Data toggle error interrupt enable
-                DTERIE: u1,
-                padding: u21,
-            }),
-            ///  host channel-7 transfer length register
-            HCH7LEN: mmio.Mmio(packed struct(u32) {
-                ///  Transfer length
-                TLEN: u19,
-                ///  Packet count
-                PCNT: u10,
-                ///  Data PID
-                DPID: u2,
-                padding: u1,
-            }),
-        };
-
-        ///  USB full speed global registers
-        pub const USBFS_GLOBAL = extern struct {
-            ///  Global OTG control and status register (USBFS_GOTGCS)
-            GOTGCS: mmio.Mmio(packed struct(u32) {
-                ///  SRP success
-                SRPS: u1,
-                ///  SRP request
-                SRPREQ: u1,
-                reserved8: u6,
-                ///  Host success
-                HNPS: u1,
-                ///  HNP request
-                HNPREQ: u1,
-                ///  Host HNP enable
-                HHNPEN: u1,
-                ///  Device HNP enabled
-                DHNPEN: u1,
-                reserved16: u4,
-                ///  ID pin status
-                IDPS: u1,
-                ///  Debounce interval
-                DI: u1,
-                ///  A-session valid
-                ASV: u1,
-                ///  B-session valid
-                BSV: u1,
-                padding: u12,
-            }),
-            ///  Global OTG interrupt flag register (USBFS_GOTGINTF)
-            GOTGINTF: mmio.Mmio(packed struct(u32) {
-                reserved2: u2,
-                ///  Session end
-                SESEND: u1,
-                reserved8: u5,
-                ///  Session request success status change
-                SRPEND: u1,
-                ///  HNP end
-                HNPEND: u1,
-                reserved17: u7,
-                ///  Host negotiation request detected
-                HNPDET: u1,
-                ///  A-device timeout
-                ADTO: u1,
-                ///  Debounce finish
-                DF: u1,
-                padding: u12,
-            }),
-            ///  Global AHB control and status register (USBFS_GAHBCS)
-            GAHBCS: mmio.Mmio(packed struct(u32) {
-                ///  Global interrupt enable
-                GINTEN: u1,
-                reserved7: u6,
-                ///  Tx FIFO threshold
-                TXFTH: u1,
-                ///  Periodic Tx FIFO threshold
-                PTXFTH: u1,
-                padding: u23,
-            }),
-            ///  Global USB control and status register (USBFS_GUSBCSR)
-            GUSBCS: mmio.Mmio(packed struct(u32) {
-                ///  Timeout calibration
-                TOC: u3,
-                reserved8: u5,
-                ///  SRP capability enable
-                SRPCEN: u1,
-                ///  HNP capability enable
-                HNPCEN: u1,
-                ///  USB turnaround time
-                UTT: u4,
-                reserved29: u15,
-                ///  Force host mode
-                FHM: u1,
-                ///  Force device mode
-                FDM: u1,
-                padding: u1,
-            }),
-            ///  Global reset control register (USBFS_GRSTCTL)
-            GRSTCTL: mmio.Mmio(packed struct(u32) {
-                ///  Core soft reset
-                CSRST: u1,
-                ///  HCLK soft reset
-                HCSRST: u1,
-                ///  Host frame counter reset
-                HFCRST: u1,
-                reserved4: u1,
-                ///  RxFIFO flush
-                RXFF: u1,
-                ///  TxFIFO flush
-                TXFF: u1,
-                ///  TxFIFO number
-                TXFNUM: u5,
-                padding: u21,
-            }),
-            ///  Global interrupt flag register (USBFS_GINTF)
-            GINTF: mmio.Mmio(packed struct(u32) {
-                ///  Current operation mode
-                COPM: u1,
-                ///  Mode fault interrupt flag
-                MFIF: u1,
-                ///  OTG interrupt flag
-                OTGIF: u1,
-                ///  Start of frame
-                SOF: u1,
-                ///  RxFIFO non-empty interrupt flag
-                RXFNEIF: u1,
-                ///  Non-periodic TxFIFO empty interrupt flag
-                NPTXFEIF: u1,
-                ///  Global Non-Periodic IN NAK effective
-                GNPINAK: u1,
-                ///  Global OUT NAK effective
-                GONAK: u1,
-                reserved10: u2,
-                ///  Early suspend
-                ESP: u1,
-                ///  USB suspend
-                SP: u1,
-                ///  USB reset
-                RST: u1,
-                ///  Enumeration finished
-                ENUMF: u1,
-                ///  Isochronous OUT packet dropped interrupt
-                ISOOPDIF: u1,
-                ///  End of periodic frame interrupt flag
-                EOPFIF: u1,
-                reserved18: u2,
-                ///  IN endpoint interrupt flag
-                IEPIF: u1,
-                ///  OUT endpoint interrupt flag
-                OEPIF: u1,
-                ///  Isochronous IN transfer Not Complete Interrupt Flag
-                ISOINCIF: u1,
-                ///  periodic transfer not complete interrupt flag(Host mode)/isochronous OUT transfer not complete interrupt flag(Device mode)
-                PXNCIF_ISOONCIF: u1,
-                reserved24: u2,
-                ///  Host port interrupt flag
-                HPIF: u1,
-                ///  Host channels interrupt flag
-                HCIF: u1,
-                ///  Periodic TxFIFO empty interrupt flag
-                PTXFEIF: u1,
-                reserved28: u1,
-                ///  ID pin status change
-                IDPSC: u1,
-                ///  Disconnect interrupt flag
-                DISCIF: u1,
-                ///  Session interrupt flag
-                SESIF: u1,
-                ///  Wakeup interrupt flag
-                WKUPIF: u1,
-            }),
-            ///  Global interrupt enable register (USBFS_GINTEN)
-            GINTEN: mmio.Mmio(packed struct(u32) {
-                reserved1: u1,
-                ///  Mode fault interrupt enable
-                MFIE: u1,
-                ///  OTG interrupt enable
-                OTGIE: u1,
-                ///  Start of frame interrupt enable
-                SOFIE: u1,
-                ///  Receive FIFO non-empty interrupt enable
-                RXFNEIE: u1,
-                ///  Non-periodic TxFIFO empty interrupt enable
-                NPTXFEIE: u1,
-                ///  Global non-periodic IN NAK effective interrupt enable
-                GNPINAKIE: u1,
-                ///  Global OUT NAK effective interrupt enable
-                GONAKIE: u1,
-                reserved10: u2,
-                ///  Early suspend interrupt enable
-                ESPIE: u1,
-                ///  USB suspend interrupt enable
-                SPIE: u1,
-                ///  USB reset interrupt enable
-                RSTIE: u1,
-                ///  Enumeration finish interrupt enable
-                ENUMFIE: u1,
-                ///  Isochronous OUT packet dropped interrupt enable
-                ISOOPDIE: u1,
-                ///  End of periodic frame interrupt enable
-                EOPFIE: u1,
-                reserved18: u2,
-                ///  IN endpoints interrupt enable
-                IEPIE: u1,
-                ///  OUT endpoints interrupt enable
-                OEPIE: u1,
-                ///  isochronous IN transfer not complete interrupt enable
-                ISOINCIE: u1,
-                ///  periodic transfer not compelete Interrupt enable(Host mode)/isochronous OUT transfer not complete interrupt enable(Device mode)
-                PXNCIE_ISOONCIE: u1,
-                reserved24: u2,
-                ///  Host port interrupt enable
-                HPIE: u1,
-                ///  Host channels interrupt enable
-                HCIE: u1,
-                ///  Periodic TxFIFO empty interrupt enable
-                PTXFEIE: u1,
-                reserved28: u1,
-                ///  ID pin status change interrupt enable
-                IDPSCIE: u1,
-                ///  Disconnect interrupt enable
-                DISCIE: u1,
-                ///  Session interrupt enable
-                SESIE: u1,
-                ///  Wakeup interrupt enable
-                WKUPIE: u1,
-            }),
-            ///  Global Receive status read(Device mode)
-            GRSTATR_Device: mmio.Mmio(packed struct(u32) {
-                ///  Endpoint number
-                EPNUM: u4,
-                ///  Byte count
-                BCOUNT: u11,
-                ///  Data PID
-                DPID: u2,
-                ///  Recieve packet status
-                RPCKST: u4,
-                padding: u11,
-            }),
-            ///  Global Receive status pop(Device mode)
-            GRSTATP_Device: mmio.Mmio(packed struct(u32) {
-                ///  Endpoint number
-                EPNUM: u4,
-                ///  Byte count
-                BCOUNT: u11,
-                ///  Data PID
-                DPID: u2,
-                ///  Recieve packet status
-                RPCKST: u4,
-                padding: u11,
-            }),
-            ///  Global Receive FIFO size register (USBFS_GRFLEN)
-            GRFLEN: mmio.Mmio(packed struct(u32) {
-                ///  Rx FIFO depth
-                RXFD: u16,
-                padding: u16,
-            }),
-            ///  Host non-periodic transmit FIFO length register (Host mode)
-            HNPTFLEN: mmio.Mmio(packed struct(u32) {
-                ///  host non-periodic transmit Tx RAM start address
-                HNPTXRSAR: u16,
-                ///  host non-periodic TxFIFO depth
-                HNPTXFD: u16,
-            }),
-            ///  Host non-periodic transmit FIFO/queue status register (HNPTFQSTAT)
-            HNPTFQSTAT: mmio.Mmio(packed struct(u32) {
-                ///  Non-periodic TxFIFO space
-                NPTXFS: u16,
-                ///  Non-periodic transmit request queue space
-                NPTXRQS: u8,
-                ///  Top of the non-periodic transmit request queue
-                NPTXRQTOP: u7,
-                padding: u1,
-            }),
-            reserved56: [8]u8,
-            ///  Global core configuration register (USBFS_GCCFG)
-            GCCFG: mmio.Mmio(packed struct(u32) {
-                reserved16: u16,
-                ///  Power on
-                PWRON: u1,
-                reserved18: u1,
-                ///  The VBUS A-device Comparer enable
-                VBUSACEN: u1,
-                ///  The VBUS B-device Comparer enable
-                VBUSBCEN: u1,
-                ///  SOF output enable
-                SOFOEN: u1,
-                ///  VBUS ignored
-                VBUSIG: u1,
-                padding: u10,
-            }),
-            ///  core ID register
-            CID: mmio.Mmio(packed struct(u32) {
-                ///  Core ID
-                CID: u32,
-            }),
-            reserved256: [192]u8,
-            ///  Host periodic transmit FIFO length register (HPTFLEN)
-            HPTFLEN: mmio.Mmio(packed struct(u32) {
-                ///  Host periodic TxFIFO start address
-                HPTXFSAR: u16,
-                ///  Host periodic TxFIFO depth
-                HPTXFD: u16,
-            }),
-            ///  device IN endpoint transmit FIFO size register (DIEP1TFLEN)
-            DIEP1TFLEN: mmio.Mmio(packed struct(u32) {
-                ///  IN endpoint FIFO transmit RAM start address
-                IEPTXRSAR: u16,
-                ///  IN endpoint TxFIFO depth
-                IEPTXFD: u16,
-            }),
-            ///  device IN endpoint transmit FIFO size register (DIEP2TFLEN)
-            DIEP2TFLEN: mmio.Mmio(packed struct(u32) {
-                ///  IN endpoint FIFO transmit RAM start address
-                IEPTXRSAR: u16,
-                ///  IN endpoint TxFIFO depth
-                IEPTXFD: u16,
-            }),
-            ///  device IN endpoint transmit FIFO size register (FS_DIEP3TXFLEN)
-            DIEP3TFLEN: mmio.Mmio(packed struct(u32) {
-                ///  IN endpoint FIFO4 transmit RAM start address
-                IEPTXRSAR: u16,
-                ///  IN endpoint TxFIFO depth
-                IEPTXFD: u16,
-            }),
-        };
-
-        ///  Inter integrated circuit
-        pub const I2C0 = extern struct {
-            ///  Control register 0
-            CTL0: mmio.Mmio(packed struct(u16) {
-                ///  I2C peripheral enable
-                I2CEN: u1,
-                ///  SMBus/I2C mode switch
-                SMBEN: u1,
-                reserved3: u1,
-                ///  SMBusType Selection
-                SMBSEL: u1,
-                ///  ARP protocol in SMBus switch
-                ARPEN: u1,
-                ///  PEC Calculation Switch
-                PECEN: u1,
-                ///  Whether or not to response to a General Call (0x00)
-                GCEN: u1,
-                ///  Whether to stretch SCL low when data is not ready in slave mode
-                SS: u1,
-                ///  Generate a START condition on I2C bus
-                START: u1,
-                ///  Generate a STOP condition on I2C bus
-                STOP: u1,
-                ///  Whether or not to send an ACK
-                ACKEN: u1,
-                ///  Position of ACK and PEC when receiving
-                POAP: u1,
-                ///  PEC Transfer
-                PECTRANS: u1,
-                ///  SMBus alert
-                SALT: u1,
-                reserved15: u1,
-                ///  Software reset
-                SRESET: u1,
-            }),
-            reserved4: [2]u8,
-            ///  Control register 1
-            CTL1: mmio.Mmio(packed struct(u16) {
-                ///  I2C Peripheral clock frequency
-                I2CCLK: u6,
-                reserved8: u2,
-                ///  Error interrupt enable
-                ERRIE: u1,
-                ///  Event interrupt enable
-                EVIE: u1,
-                ///  Buffer interrupt enable
-                BUFIE: u1,
-                ///  DMA mode switch
-                DMAON: u1,
-                ///  Flag indicating DMA last transfer
-                DMALST: u1,
-                padding: u3,
-            }),
-            reserved8: [2]u8,
-            ///  Slave address register 0
-            SADDR0: mmio.Mmio(packed struct(u16) {
-                ///  Bit 0 of a 10-bit address
-                ADDRESS0: u1,
-                ///  7-bit address or bits 7:1 of a 10-bit address
-                ADDRESS7_1: u7,
-                ///  Highest two bits of a 10-bit address
-                ADDRESS9_8: u2,
-                reserved15: u5,
-                ///  Address mode for the I2C slave
-                ADDFORMAT: u1,
-            }),
-            reserved12: [2]u8,
-            ///  Slave address register 1
-            SADDR1: mmio.Mmio(packed struct(u16) {
-                ///  Dual-Address mode switch
-                DUADEN: u1,
-                ///  Second I2C address for the slave in Dual-Address mode
-                ADDRESS2: u7,
-                padding: u8,
-            }),
-            reserved16: [2]u8,
-            ///  Transfer buffer register
-            DATA: mmio.Mmio(packed struct(u16) {
-                ///  Transmission or reception data buffer register
-                TRB: u8,
-                padding: u8,
-            }),
-            reserved20: [2]u8,
-            ///  Transfer status register 0
-            STAT0: mmio.Mmio(packed struct(u16) {
-                ///  START condition sent out in master mode
-                SBSEND: u1,
-                ///  Address is sent in master mode or received and matches in slave mode
-                ADDSEND: u1,
-                ///  Byte transmission completed
-                BTC: u1,
-                ///  Header of 10-bit address is sent in master mode
-                ADD10SEND: u1,
-                ///  STOP condition detected in slave mode
-                STPDET: u1,
-                reserved6: u1,
-                ///  I2C_DATA is not Empty during receiving
-                RBNE: u1,
-                ///  I2C_DATA is Empty during transmitting
-                TBE: u1,
-                ///  A bus error occurs indication a unexpected START or STOP condition on I2C bus
-                BERR: u1,
-                ///  Arbitration Lost in master mode
-                LOSTARB: u1,
-                ///  Acknowledge error
-                AERR: u1,
-                ///  Over-run or under-run situation occurs in slave mode
-                OUERR: u1,
-                ///  PEC error when receiving data
-                PECERR: u1,
-                reserved14: u1,
-                ///  Timeout signal in SMBus mode
-                SMBTO: u1,
-                ///  SMBus Alert status
-                SMBALT: u1,
-            }),
-            reserved24: [2]u8,
-            ///  Transfer status register 1
-            STAT1: mmio.Mmio(packed struct(u16) {
-                ///  A flag indicating whether I2C block is in master or slave mode
-                MASTER: u1,
-                ///  Busy flag
-                I2CBSY: u1,
-                ///  Whether the I2C is a transmitter or a receiver
-                TR: u1,
-                reserved4: u1,
-                ///  General call address (00h) received
-                RXGC: u1,
-                ///  Default address of SMBusDevice
-                DEFSMB: u1,
-                ///  SMBus Host Header detected in slave mode
-                HSTSMB: u1,
-                ///  Dual Flag in slave mode
-                DUMODF: u1,
-                ///  Packet Error Checking Value that calculated by hardware when PEC is enabled
-                PECV: u8,
-            }),
-            reserved28: [2]u8,
-            ///  Clock configure register
-            CKCFG: mmio.Mmio(packed struct(u16) {
-                ///  I2C Clock control in master mode
-                CLKC: u12,
-                reserved14: u2,
-                ///  Duty cycle in fast mode
-                DTCY: u1,
-                ///  I2C speed selection in master mode
-                FAST: u1,
-            }),
-            reserved32: [2]u8,
-            ///  Rise time register
-            RT: mmio.Mmio(packed struct(u16) {
-                ///  Maximum rise time in master mode
-                RISETIME: u6,
-                padding: u10,
-            }),
-        };
-
-        ///  Basic-timers
-        pub const TIMER5 = extern struct {
-            ///  control register 0
-            CTL0: mmio.Mmio(packed struct(u16) {
-                ///  Counter enable
-                CEN: u1,
-                ///  Update disable
-                UPDIS: u1,
-                ///  Update source
-                UPS: u1,
-                ///  Single pulse mode
-                SPM: u1,
-                reserved7: u3,
-                ///  Auto-reload shadow enable
-                ARSE: u1,
-                padding: u8,
-            }),
-            reserved4: [2]u8,
-            ///  control register 1
-            CTL1: mmio.Mmio(packed struct(u16) {
-                reserved4: u4,
-                ///  Master mode control
-                MMC: u3,
-                padding: u9,
-            }),
-            reserved12: [6]u8,
-            ///  DMA/Interrupt enable register
-            DMAINTEN: mmio.Mmio(packed struct(u16) {
-                ///  Update interrupt enable
-                UPIE: u1,
-                reserved8: u7,
-                ///  Update DMA request enable
-                UPDEN: u1,
-                padding: u7,
-            }),
-            reserved16: [2]u8,
-            ///  Interrupt flag register
-            INTF: mmio.Mmio(packed struct(u16) {
-                ///  Update interrupt flag
-                UPIF: u1,
-                padding: u15,
-            }),
-            reserved20: [2]u8,
-            ///  event generation register
-            SWEVG: mmio.Mmio(packed struct(u16) {
-                ///  Update generation
-                UPG: u1,
-                padding: u15,
-            }),
-            reserved36: [14]u8,
-            ///  Counter register
-            CNT: mmio.Mmio(packed struct(u16) {
-                ///  Low counter value
-                CNT: u16,
-            }),
-            reserved40: [2]u8,
-            ///  Prescaler register
-            PSC: mmio.Mmio(packed struct(u16) {
-                ///  Prescaler value of the counter clock
-                PSC: u16,
-            }),
-            reserved44: [2]u8,
-            ///  Counter auto reload register
-            CAR: mmio.Mmio(packed struct(u16) {
-                ///  Counter auto reload value
-                CARL: u16,
-            }),
-        };
-
-        ///  Enhanced Core Local Interrupt Controller
-        pub const ECLIC = extern struct {
-            ///  cliccfg Register
-            CLICCFG: mmio.Mmio(packed struct(u8) {
-                reserved1: u1,
-                ///  NLBITS
-                NLBITS: u4,
-                padding: u3,
-            }),
-            reserved4: [3]u8,
-            ///  clicinfo Register
-            CLICINFO: mmio.Mmio(packed struct(u32) {
-                ///  NUM_INTERRUPT
-                NUM_INTERRUPT: u13,
-                ///  VERSION
-                VERSION: u8,
-                ///  CLICINTCTLBITS
-                CLICINTCTLBITS: u4,
-                padding: u7,
-            }),
-            reserved11: [3]u8,
-            ///  MTH Register
-            MTH: mmio.Mmio(packed struct(u8) {
-                ///  MTH
-                MTH: u8,
-            }),
-            reserved4096: [4084]u8,
-            ///  clicintip Register
-            CLICINTIP_0: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_0: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_0: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_0: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_1: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_1: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_1: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_1: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_2: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_2: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_2: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_2: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_3: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_3: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_3: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_3: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_4: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_4: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_4: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_4: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_5: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_5: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_5: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_5: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_6: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_6: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_6: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_6: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_7: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_7: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_7: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_7: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_8: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_8: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_8: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_8: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_9: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_9: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_9: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_9: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_10: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_10: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_10: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_10: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_11: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_11: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_11: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_11: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_12: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_12: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_12: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_12: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_13: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_13: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_13: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_13: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_14: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_14: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_14: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_14: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_15: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_15: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_15: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_15: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_16: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_16: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_16: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_16: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_17: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_17: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_17: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_17: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_18: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_18: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_18: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_18: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_19: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_19: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_19: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_19: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_20: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_20: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_20: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_20: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_21: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_21: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_21: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_21: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_22: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_22: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_22: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_22: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_23: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_23: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_23: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_23: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_24: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_24: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_24: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_24: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_25: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_25: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_25: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_25: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_26: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_26: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_26: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_26: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_27: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_27: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_27: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_27: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_28: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_28: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_28: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_28: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_29: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_29: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_29: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_29: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_30: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_30: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_30: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_30: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_31: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_31: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_31: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_31: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_32: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_32: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_32: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_32: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_33: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_33: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_33: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_33: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_34: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_34: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_34: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_34: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_35: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_35: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_35: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_35: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_36: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_36: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_36: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_36: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_37: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_37: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_37: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_37: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_38: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_38: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_38: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_38: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_39: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_39: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_39: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_39: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_40: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_40: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_40: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_40: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_41: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_41: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_41: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_41: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_42: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_42: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_42: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_42: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_43: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_43: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_43: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_43: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_44: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_44: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_44: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_44: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_45: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_45: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_45: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_45: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_46: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_46: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_46: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_46: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_47: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_47: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_47: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_47: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_48: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_48: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_48: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_48: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_49: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_49: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_49: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_49: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_50: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_50: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_50: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_50: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_51: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_51: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_51: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_51: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_52: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_52: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_52: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_52: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_53: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_53: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_53: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_53: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_54: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_54: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_54: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_54: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_55: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_55: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_55: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_55: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_56: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_56: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_56: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_56: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_57: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_57: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_57: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_57: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_58: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_58: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_58: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_58: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_59: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_59: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_59: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_59: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_60: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_60: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_60: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_60: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_61: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_61: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_61: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_61: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_62: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_62: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_62: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_62: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_63: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_63: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_63: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_63: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_64: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_64: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_64: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_64: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_65: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_65: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_65: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_65: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_66: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_66: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_66: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_66: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_67: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_67: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_67: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_67: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_68: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_68: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_68: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_68: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_69: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_69: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_69: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_69: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_70: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_70: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_70: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_70: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_71: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_71: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_71: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_71: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_72: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_72: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_72: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_72: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_73: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_73: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_73: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_73: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_74: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_74: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_74: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_74: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_75: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_75: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_75: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_75: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_76: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_76: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_76: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_76: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_77: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_77: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_77: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_77: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_78: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_78: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_78: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_78: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_79: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_79: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_79: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_79: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_80: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_80: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_80: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_80: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_81: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_81: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_81: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_81: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_82: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_82: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_82: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_82: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_83: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_83: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_83: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_83: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_84: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_84: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_84: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_84: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            reserved4437: [1]u8,
-            ///  clicintie Register
-            CLICINTIE_85: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_85: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_85: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_85: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-            ///  clicintie Register
-            CLICINTIE_86: mmio.Mmio(packed struct(u8) {
-                ///  IE
-                IE: u1,
-                padding: u7,
-            }),
-            ///  clicintattr Register
-            CLICINTATTR_86: mmio.Mmio(packed struct(u8) {
-                ///  SHV
-                SHV: u1,
-                ///  TRIG
-                TRIG: u2,
-                padding: u5,
-            }),
-            ///  clicintctl Register
-            CLICINTCTL_86: mmio.Mmio(packed struct(u8) {
-                ///  LEVEL_PRIORITY
-                LEVEL_PRIORITY: u8,
-            }),
-            ///  clicintip Register
-            CLICINTIP_86: mmio.Mmio(packed struct(u8) {
-                ///  IP
-                IP: u1,
-                padding: u7,
-            }),
-        };
-
-        ///  Power management unit
-        pub const PMU = extern struct {
-            ///  power control register
-            CTL: mmio.Mmio(packed struct(u32) {
-                ///  LDO Low Power Mode
-                LDOLP: u1,
-                ///  Standby Mode
-                STBMOD: u1,
-                ///  Wakeup Flag Reset
-                WURST: u1,
-                ///  Standby Flag Reset
-                STBRST: u1,
-                ///  Low Voltage Detector Enable
-                LVDEN: u1,
-                ///  Low Voltage Detector Threshold
-                LVDT: u3,
-                ///  Backup Domain Write Enable
-                BKPWEN: u1,
-                padding: u23,
-            }),
-            ///  power control/status register
-            CS: mmio.Mmio(packed struct(u32) {
-                ///  Wakeup flag
-                WUF: u1,
-                ///  Standby flag
-                STBF: u1,
-                ///  Low Voltage Detector Status Flag
-                LVDF: u1,
-                reserved8: u5,
-                ///  Enable WKUP pin
-                WUPEN: u1,
-                padding: u23,
-            }),
-        };
-
-        ///  Reset and clock unit
-        pub const RCU = extern struct {
-            ///  Control register
-            CTL: mmio.Mmio(packed struct(u32) {
-                ///  Internal 8MHz RC oscillator Enable
-                IRC8MEN: u1,
-                ///  IRC8M Internal 8MHz RC Oscillator stabilization Flag
-                IRC8MSTB: u1,
-                reserved3: u1,
-                ///  Internal 8MHz RC Oscillator clock trim adjust value
-                IRC8MADJ: u5,
-                ///  Internal 8MHz RC Oscillator calibration value register
-                IRC8MCALIB: u8,
-                ///  External High Speed oscillator Enable
-                HXTALEN: u1,
-                ///  External crystal oscillator (HXTAL) clock stabilization flag
-                HXTALSTB: u1,
-                ///  External crystal oscillator (HXTAL) clock bypass mode enable
-                HXTALBPS: u1,
-                ///  HXTAL Clock Monitor Enable
-                CKMEN: u1,
-                reserved24: u4,
-                ///  PLL enable
-                PLLEN: u1,
-                ///  PLL Clock Stabilization Flag
-                PLLSTB: u1,
-                ///  PLL1 enable
-                PLL1EN: u1,
-                ///  PLL1 Clock Stabilization Flag
-                PLL1STB: u1,
-                ///  PLL2 enable
-                PLL2EN: u1,
-                ///  PLL2 Clock Stabilization Flag
-                PLL2STB: u1,
-                padding: u2,
-            }),
-            ///  Clock configuration register 0 (RCU_CFG0)
-            CFG0: mmio.Mmio(packed struct(u32) {
-                ///  System clock switch
-                SCS: u2,
-                ///  System clock switch status
-                SCSS: u2,
-                ///  AHB prescaler selection
-                AHBPSC: u4,
-                ///  APB1 prescaler selection
-                APB1PSC: u3,
-                ///  APB2 prescaler selection
-                APB2PSC: u3,
-                ///  ADC clock prescaler selection
-                ADCPSC_1_0: u2,
-                ///  PLL Clock Source Selection
-                PLLSEL: u1,
-                ///  The LSB of PREDV0 division factor
-                PREDV0_LSB: u1,
-                ///  The PLL clock multiplication factor
-                PLLMF_3_0: u4,
-                ///  USBFS clock prescaler selection
-                USBFSPSC: u2,
-                ///  CKOUT0 Clock Source Selection
-                CKOUT0SEL: u4,
-                ///  Bit 2 of ADCPSC
-                ADCPSC_2: u1,
-                ///  Bit 4 of PLLMF
-                PLLMF_4: u1,
-                padding: u2,
-            }),
-            ///  Clock interrupt register (RCU_INT)
-            INT: mmio.Mmio(packed struct(u32) {
-                ///  IRC40K stabilization interrupt flag
-                IRC40KSTBIF: u1,
-                ///  LXTAL stabilization interrupt flag
-                LXTALSTBIF: u1,
-                ///  IRC8M stabilization interrupt flag
-                IRC8MSTBIF: u1,
-                ///  HXTAL stabilization interrupt flag
-                HXTALSTBIF: u1,
-                ///  PLL stabilization interrupt flag
-                PLLSTBIF: u1,
-                ///  PLL1 stabilization interrupt flag
-                PLL1STBIF: u1,
-                ///  PLL2 stabilization interrupt flag
-                PLL2STBIF: u1,
-                ///  HXTAL Clock Stuck Interrupt Flag
-                CKMIF: u1,
-                ///  IRC40K Stabilization interrupt enable
-                IRC40KSTBIE: u1,
-                ///  LXTAL Stabilization Interrupt Enable
-                LXTALSTBIE: u1,
-                ///  IRC8M Stabilization Interrupt Enable
-                IRC8MSTBIE: u1,
-                ///  HXTAL Stabilization Interrupt Enable
-                HXTALSTBIE: u1,
-                ///  PLL Stabilization Interrupt Enable
-                PLLSTBIE: u1,
-                ///  PLL1 Stabilization Interrupt Enable
-                PLL1STBIE: u1,
-                ///  PLL2 Stabilization Interrupt Enable
-                PLL2STBIE: u1,
-                reserved16: u1,
-                ///  IRC40K Stabilization Interrupt Clear
-                IRC40KSTBIC: u1,
-                ///  LXTAL Stabilization Interrupt Clear
-                LXTALSTBIC: u1,
-                ///  IRC8M Stabilization Interrupt Clear
-                IRC8MSTBIC: u1,
-                ///  HXTAL Stabilization Interrupt Clear
-                HXTALSTBIC: u1,
-                ///  PLL stabilization Interrupt Clear
-                PLLSTBIC: u1,
-                ///  PLL1 stabilization Interrupt Clear
-                PLL1STBIC: u1,
-                ///  PLL2 stabilization Interrupt Clear
-                PLL2STBIC: u1,
-                ///  HXTAL Clock Stuck Interrupt Clear
-                CKMIC: u1,
-                padding: u8,
-            }),
-            ///  APB2 reset register (RCU_APB2RST)
-            APB2RST: mmio.Mmio(packed struct(u32) {
-                ///  Alternate function I/O reset
-                AFRST: u1,
-                reserved2: u1,
-                ///  GPIO port A reset
-                PARST: u1,
-                ///  GPIO port B reset
-                PBRST: u1,
-                ///  GPIO port C reset
-                PCRST: u1,
-                ///  GPIO port D reset
-                PDRST: u1,
-                ///  GPIO port E reset
-                PERST: u1,
-                reserved9: u2,
-                ///  ADC0 reset
-                ADC0RST: u1,
-                ///  ADC1 reset
-                ADC1RST: u1,
-                ///  Timer 0 reset
-                TIMER0RST: u1,
-                ///  SPI0 reset
-                SPI0RST: u1,
-                reserved14: u1,
-                ///  USART0 Reset
-                USART0RST: u1,
-                padding: u17,
-            }),
-            ///  APB1 reset register (RCU_APB1RST)
-            APB1RST: mmio.Mmio(packed struct(u32) {
-                ///  TIMER1 timer reset
-                TIMER1RST: u1,
-                ///  TIMER2 timer reset
-                TIMER2RST: u1,
-                ///  TIMER3 timer reset
-                TIMER3RST: u1,
-                ///  TIMER4 timer reset
-                TIMER4RST: u1,
-                ///  TIMER5 timer reset
-                TIMER5RST: u1,
-                ///  TIMER6 timer reset
-                TIMER6RST: u1,
-                reserved11: u5,
-                ///  Window watchdog timer reset
-                WWDGTRST: u1,
-                reserved14: u2,
-                ///  SPI1 reset
-                SPI1RST: u1,
-                ///  SPI2 reset
-                SPI2RST: u1,
-                reserved17: u1,
-                ///  USART1 reset
-                USART1RST: u1,
-                ///  USART2 reset
-                USART2RST: u1,
-                ///  UART3 reset
-                UART3RST: u1,
-                ///  UART4 reset
-                UART4RST: u1,
-                ///  I2C0 reset
-                I2C0RST: u1,
-                ///  I2C1 reset
-                I2C1RST: u1,
-                reserved25: u2,
-                ///  CAN0 reset
-                CAN0RST: u1,
-                ///  CAN1 reset
-                CAN1RST: u1,
-                ///  Backup interface reset
-                BKPIRST: u1,
-                ///  Power control reset
-                PMURST: u1,
-                ///  DAC reset
-                DACRST: u1,
-                padding: u2,
-            }),
-            ///  AHB enable register
-            AHBEN: mmio.Mmio(packed struct(u32) {
-                ///  DMA0 clock enable
-                DMA0EN: u1,
-                ///  DMA1 clock enable
-                DMA1EN: u1,
-                ///  SRAM interface clock enable when sleep mode
-                SRAMSPEN: u1,
-                reserved4: u1,
-                ///  FMC clock enable when sleep mode
-                FMCSPEN: u1,
-                reserved6: u1,
-                ///  CRC clock enable
-                CRCEN: u1,
-                reserved8: u1,
-                ///  EXMC clock enable
-                EXMCEN: u1,
-                reserved12: u3,
-                ///  USBFS clock enable
-                USBFSEN: u1,
-                padding: u19,
-            }),
-            ///  APB2 clock enable register (RCU_APB2EN)
-            APB2EN: mmio.Mmio(packed struct(u32) {
-                ///  Alternate function IO clock enable
-                AFEN: u1,
-                reserved2: u1,
-                ///  GPIO port A clock enable
-                PAEN: u1,
-                ///  GPIO port B clock enable
-                PBEN: u1,
-                ///  GPIO port C clock enable
-                PCEN: u1,
-                ///  GPIO port D clock enable
-                PDEN: u1,
-                ///  GPIO port E clock enable
-                PEEN: u1,
-                reserved9: u2,
-                ///  ADC0 clock enable
-                ADC0EN: u1,
-                ///  ADC1 clock enable
-                ADC1EN: u1,
-                ///  TIMER0 clock enable
-                TIMER0EN: u1,
-                ///  SPI0 clock enable
-                SPI0EN: u1,
-                reserved14: u1,
-                ///  USART0 clock enable
-                USART0EN: u1,
-                padding: u17,
-            }),
-            ///  APB1 clock enable register (RCU_APB1EN)
-            APB1EN: mmio.Mmio(packed struct(u32) {
-                ///  TIMER1 timer clock enable
-                TIMER1EN: u1,
-                ///  TIMER2 timer clock enable
-                TIMER2EN: u1,
-                ///  TIMER3 timer clock enable
-                TIMER3EN: u1,
-                ///  TIMER4 timer clock enable
-                TIMER4EN: u1,
-                ///  TIMER5 timer clock enable
-                TIMER5EN: u1,
-                ///  TIMER6 timer clock enable
-                TIMER6EN: u1,
-                reserved11: u5,
-                ///  Window watchdog timer clock enable
-                WWDGTEN: u1,
-                reserved14: u2,
-                ///  SPI1 clock enable
-                SPI1EN: u1,
-                ///  SPI2 clock enable
-                SPI2EN: u1,
-                reserved17: u1,
-                ///  USART1 clock enable
-                USART1EN: u1,
-                ///  USART2 clock enable
-                USART2EN: u1,
-                ///  UART3 clock enable
-                UART3EN: u1,
-                ///  UART4 clock enable
-                UART4EN: u1,
-                ///  I2C0 clock enable
-                I2C0EN: u1,
-                ///  I2C1 clock enable
-                I2C1EN: u1,
-                reserved25: u2,
-                ///  CAN0 clock enable
-                CAN0EN: u1,
-                ///  CAN1 clock enable
-                CAN1EN: u1,
-                ///  Backup interface clock enable
-                BKPIEN: u1,
-                ///  Power control clock enable
-                PMUEN: u1,
-                ///  DAC clock enable
-                DACEN: u1,
-                padding: u2,
-            }),
-            ///  Backup domain control register (RCU_BDCTL)
-            BDCTL: mmio.Mmio(packed struct(u32) {
-                ///  LXTAL enable
-                LXTALEN: u1,
-                ///  External low-speed oscillator stabilization
-                LXTALSTB: u1,
-                ///  LXTAL bypass mode enable
-                LXTALBPS: u1,
-                reserved8: u5,
-                ///  RTC clock entry selection
-                RTCSRC: u2,
-                reserved15: u5,
-                ///  RTC clock enable
-                RTCEN: u1,
-                ///  Backup domain reset
-                BKPRST: u1,
-                padding: u15,
-            }),
-            ///  Reset source /clock register (RCU_RSTSCK)
-            RSTSCK: mmio.Mmio(packed struct(u32) {
-                ///  IRC40K enable
-                IRC40KEN: u1,
-                ///  IRC40K stabilization
-                IRC40KSTB: u1,
-                reserved24: u22,
-                ///  Reset flag clear
-                RSTFC: u1,
-                reserved26: u1,
-                ///  External PIN reset flag
-                EPRSTF: u1,
-                ///  Power reset flag
-                PORRSTF: u1,
-                ///  Software reset flag
-                SWRSTF: u1,
-                ///  Free Watchdog timer reset flag
-                FWDGTRSTF: u1,
-                ///  Window watchdog timer reset flag
-                WWDGTRSTF: u1,
-                ///  Low-power reset flag
-                LPRSTF: u1,
-            }),
-            ///  AHB reset register
-            AHBRST: mmio.Mmio(packed struct(u32) {
-                reserved12: u12,
-                ///  USBFS reset
-                USBFSRST: u1,
-                padding: u19,
-            }),
-            ///  Clock Configuration register 1
-            CFG1: mmio.Mmio(packed struct(u32) {
-                ///  PREDV0 division factor
-                PREDV0: u4,
-                ///  PREDV1 division factor
-                PREDV1: u4,
-                ///  The PLL1 clock multiplication factor
-                PLL1MF: u4,
-                ///  The PLL2 clock multiplication factor
-                PLL2MF: u4,
-                ///  PREDV0 input Clock Source Selection
-                PREDV0SEL: u1,
-                ///  I2S1 Clock Source Selection
-                I2S1SEL: u1,
-                ///  I2S2 Clock Source Selection
-                I2S2SEL: u1,
-                padding: u13,
-            }),
-            reserved52: [4]u8,
-            ///  Deep sleep mode Voltage register
-            DSV: mmio.Mmio(packed struct(u32) {
-                ///  Deep-sleep mode voltage select
-                DSLPVS: u2,
-                padding: u30,
-            }),
-        };
-
-        ///  Real-time clock
-        pub const RTC = extern struct {
-            ///  RTC interrupt enable register
-            INTEN: mmio.Mmio(packed struct(u32) {
-                ///  Second interrupt
-                SCIE: u1,
-                ///  Alarm interrupt enable
-                ALRMIE: u1,
-                ///  Overflow interrupt enable
-                OVIE: u1,
-                padding: u29,
-            }),
-            ///  control register
-            CTL: mmio.Mmio(packed struct(u32) {
-                ///  Sencond interrupt flag
-                SCIF: u1,
-                ///  Alarm interrupt flag
-                ALRMIF: u1,
-                ///  Overflow interrupt flag
-                OVIF: u1,
-                ///  Registers synchronized flag
-                RSYNF: u1,
-                ///  Configuration mode flag
-                CMF: u1,
-                ///  Last write operation finished flag
-                LWOFF: u1,
-                padding: u26,
-            }),
-            ///  RTC prescaler high register
-            PSCH: mmio.Mmio(packed struct(u32) {
-                padding: u32,
-            }),
-            ///  RTC prescaler low register
-            PSCL: mmio.Mmio(packed struct(u32) {
-                padding: u32,
-            }),
-            ///  RTC divider high register
-            DIVH: mmio.Mmio(packed struct(u32) {
-                ///  RTC divider value high
-                DIV: u4,
-                padding: u28,
-            }),
-            ///  RTC divider low register
-            DIVL: mmio.Mmio(packed struct(u32) {
-                ///  RTC divider value low
-                DIV: u16,
-                padding: u16,
-            }),
-            ///  RTC counter high register
-            CNTH: mmio.Mmio(packed struct(u32) {
-                ///  RTC counter value high
-                CNT: u16,
-                padding: u16,
-            }),
-            ///  RTC counter low register
-            CNTL: mmio.Mmio(packed struct(u32) {
-                ///  RTC counter value low
-                CNT: u16,
-                padding: u16,
-            }),
-        };
-
-        ///  Serial peripheral interface
-        pub const SPI0 = extern struct {
-            ///  control register 0
-            CTL0: mmio.Mmio(packed struct(u16) {
-                ///  Clock Phase Selection
-                CKPH: u1,
-                ///  Clock polarity Selection
-                CKPL: u1,
-                ///  Master Mode Enable
-                MSTMOD: u1,
-                ///  Master Clock Prescaler Selection
-                PSC: u3,
-                ///  SPI enable
-                SPIEN: u1,
-                ///  LSB First Mode
-                LF: u1,
-                ///  NSS Pin Selection In NSS Software Mode
-                SWNSS: u1,
-                ///  NSS Software Mode Selection
-                SWNSSEN: u1,
-                ///  Receive only
-                RO: u1,
-                ///  Data frame format
-                FF16: u1,
-                ///  CRC Next Transfer
-                CRCNT: u1,
-                ///  CRC Calculation Enable
-                CRCEN: u1,
-                ///  Bidirectional Transmit output enable
-                BDOEN: u1,
-                ///  Bidirectional enable
-                BDEN: u1,
-            }),
-            reserved4: [2]u8,
-            ///  control register 1
-            CTL1: mmio.Mmio(packed struct(u16) {
-                ///  Rx buffer DMA enable
-                DMAREN: u1,
-                ///  Transmit Buffer DMA Enable
-                DMATEN: u1,
-                ///  Drive NSS Output
-                NSSDRV: u1,
-                ///  SPI NSS pulse mode enable
-                NSSP: u1,
-                ///  SPI TI mode enable
-                TMOD: u1,
-                ///  Error interrupt enable
-                ERRIE: u1,
-                ///  RX buffer not empty interrupt enable
-                RBNEIE: u1,
-                ///  Tx buffer empty interrupt enable
-                TBEIE: u1,
-                padding: u8,
-            }),
-            reserved8: [2]u8,
-            ///  status register
-            STAT: mmio.Mmio(packed struct(u16) {
-                ///  Receive Buffer Not Empty
-                RBNE: u1,
-                ///  Transmit Buffer Empty
-                TBE: u1,
-                ///  I2S channel side
-                I2SCH: u1,
-                ///  Transmission underrun error bit
-                TXURERR: u1,
-                ///  SPI CRC Error Bit
-                CRCERR: u1,
-                ///  SPI Configuration error
-                CONFERR: u1,
-                ///  Reception Overrun Error Bit
-                RXORERR: u1,
-                ///  Transmitting On-going Bit
-                TRANS: u1,
-                ///  Format error
-                FERR: u1,
-                padding: u7,
-            }),
-            reserved12: [2]u8,
-            ///  data register
-            DATA: mmio.Mmio(packed struct(u16) {
-                ///  Data transfer register
-                SPI_DATA: u16,
-            }),
-            reserved16: [2]u8,
-            ///  CRC polynomial register
-            CRCPOLY: mmio.Mmio(packed struct(u16) {
-                ///  CRC polynomial value
-                CRCPOLY: u16,
-            }),
-            reserved20: [2]u8,
-            ///  RX CRC register
-            RCRC: mmio.Mmio(packed struct(u16) {
-                ///  RX CRC value
-                RCRC: u16,
-            }),
-            reserved24: [2]u8,
-            ///  TX CRC register
-            TCRC: mmio.Mmio(packed struct(u16) {
-                ///  Tx CRC value
-                TCRC: u16,
-            }),
-            reserved28: [2]u8,
-            ///  I2S control register
-            I2SCTL: mmio.Mmio(packed struct(u16) {
-                ///  Channel length (number of bits per audio channel)
-                CHLEN: u1,
-                ///  Data length
-                DTLEN: u2,
-                ///  Idle state clock polarity
-                CKPL: u1,
-                ///  I2S standard selection
-                I2SSTD: u2,
-                reserved7: u1,
-                ///  PCM frame synchronization mode
-                PCMSMOD: u1,
-                ///  I2S operation mode
-                I2SOPMOD: u2,
-                ///  I2S Enable
-                I2SEN: u1,
-                ///  I2S mode selection
-                I2SSEL: u1,
-                padding: u4,
-            }),
-            reserved32: [2]u8,
-            ///  I2S prescaler register
-            I2SPSC: mmio.Mmio(packed struct(u16) {
-                ///  Dividing factor for the prescaler
-                DIV: u8,
-                ///  Odd factor for the prescaler
-                OF: u1,
-                ///  I2S_MCK output enable
-                MCKOEN: u1,
-                padding: u6,
-            }),
-        };
-
-        ///  Universal asynchronous receiver transmitter
-        pub const UART3 = extern struct {
-            ///  Status register
-            STAT: mmio.Mmio(packed struct(u32) {
-                ///  Parity error flag
-                PERR: u1,
-                ///  Frame error flag
-                FERR: u1,
-                ///  Noise error flag
-                NERR: u1,
-                ///  Overrun error
-                ORERR: u1,
-                ///  IDLE frame detected flag
-                IDLEF: u1,
-                ///  Read data buffer not empty
-                RBNE: u1,
-                ///  Transmission complete
-                TC: u1,
-                ///  Transmit data buffer empty
-                TBE: u1,
-                ///  LIN break detection flag
-                LBDF: u1,
-                padding: u23,
-            }),
-            ///  Data register
-            DATA: mmio.Mmio(packed struct(u32) {
-                ///  Transmit or read data value
-                DATA: u9,
-                padding: u23,
-            }),
-            ///  Baud rate register
-            BAUD: mmio.Mmio(packed struct(u32) {
-                ///  Fraction part of baud-rate divider
-                FRADIV: u4,
-                ///  Integer part of baud-rate divider
-                INTDIV: u12,
-                padding: u16,
-            }),
-            ///  Control register 0
-            CTL0: mmio.Mmio(packed struct(u32) {
-                ///  Send break command
-                SBKCMD: u1,
-                ///  Receiver wakeup from mute mode
-                RWU: u1,
-                ///  Receiver enable
-                REN: u1,
-                ///  Transmitter enable
-                TEN: u1,
-                ///  IDLE line detected interrupt enable
-                IDLEIE: u1,
-                ///  Read data buffer not empty interrupt and overrun error interrupt enable
-                RBNEIE: u1,
-                ///  Transmission complete interrupt enable
-                TCIE: u1,
-                ///  Transmitter buffer empty interrupt enable
-                TBEIE: u1,
-                ///  Parity error interrupt enable
-                PERRIE: u1,
-                ///  Parity mode
-                PM: u1,
-                ///  Parity check function enable
-                PCEN: u1,
-                ///  Wakeup method in mute mode
-                WM: u1,
-                ///  Word length
-                WL: u1,
-                ///  USART enable
-                UEN: u1,
-                padding: u18,
-            }),
-            ///  Control register 1
-            CTL1: mmio.Mmio(packed struct(u32) {
-                ///  Address of the USART
-                ADDR: u4,
-                reserved5: u1,
-                ///  LIN break frame length
-                LBLEN: u1,
-                ///  LIN break detection interrupt enable
-                LBDIE: u1,
-                reserved12: u5,
-                ///  STOP bits length
-                STB: u2,
-                ///  LIN mode enable
-                LMEN: u1,
-                padding: u17,
-            }),
-            ///  Control register 2
-            CTL2: mmio.Mmio(packed struct(u32) {
-                ///  Error interrupt enable
-                ERRIE: u1,
-                ///  IrDA mode enable
-                IREN: u1,
-                ///  IrDA low-power
-                IRLP: u1,
-                ///  Half-duplex selection
-                HDEN: u1,
-                reserved6: u2,
-                ///  DMA request enable for reception
-                DENR: u1,
-                ///  DMA request enable for transmission
-                DENT: u1,
-                padding: u24,
-            }),
-            ///  Guard time and prescaler register
-            GP: mmio.Mmio(packed struct(u32) {
-                ///  Prescaler value
-                PSC: u8,
-                padding: u24,
-            }),
-        };
-
-        ///  Universal synchronous asynchronous receiver transmitter
-        pub const USART0 = extern struct {
-            ///  Status register
-            STAT: mmio.Mmio(packed struct(u32) {
-                ///  Parity error flag
-                PERR: u1,
-                ///  Frame error flag
-                FERR: u1,
-                ///  Noise error flag
-                NERR: u1,
-                ///  Overrun error
-                ORERR: u1,
-                ///  IDLE frame detected flag
-                IDLEF: u1,
-                ///  Read data buffer not empty
-                RBNE: u1,
-                ///  Transmission complete
-                TC: u1,
-                ///  Transmit data buffer empty
-                TBE: u1,
-                ///  LIN break detection flag
-                LBDF: u1,
-                ///  CTS change flag
-                CTSF: u1,
-                padding: u22,
-            }),
-            ///  Data register
-            DATA: mmio.Mmio(packed struct(u32) {
-                ///  Transmit or read data value
-                DATA: u9,
-                padding: u23,
-            }),
-            ///  Baud rate register
-            BAUD: mmio.Mmio(packed struct(u32) {
-                ///  Fraction part of baud-rate divider
-                FRADIV: u4,
-                ///  Integer part of baud-rate divider
-                INTDIV: u12,
-                padding: u16,
-            }),
-            ///  Control register 0
-            CTL0: mmio.Mmio(packed struct(u32) {
-                ///  Send break command
-                SBKCMD: u1,
-                ///  Receiver wakeup from mute mode
-                RWU: u1,
-                ///  Receiver enable
-                REN: u1,
-                ///  Transmitter enable
-                TEN: u1,
-                ///  IDLE line detected interrupt enable
-                IDLEIE: u1,
-                ///  Read data buffer not empty interrupt and overrun error interrupt enable
-                RBNEIE: u1,
-                ///  Transmission complete interrupt enable
-                TCIE: u1,
-                ///  Transmitter buffer empty interrupt enable
-                TBEIE: u1,
-                ///  Parity error interrupt enable
-                PERRIE: u1,
-                ///  Parity mode
-                PM: u1,
-                ///  Parity check function enable
-                PCEN: u1,
-                ///  Wakeup method in mute mode
-                WM: u1,
-                ///  Word length
-                WL: u1,
-                ///  USART enable
-                UEN: u1,
-                padding: u18,
-            }),
-            ///  Control register 1
-            CTL1: mmio.Mmio(packed struct(u32) {
-                ///  Address of the USART
-                ADDR: u4,
-                reserved5: u1,
-                ///  LIN break frame length
-                LBLEN: u1,
-                ///  LIN break detection interrupt enable
-                LBDIE: u1,
-                reserved8: u1,
-                ///  CK Length
-                CLEN: u1,
-                ///  Clock phase
-                CPH: u1,
-                ///  Clock polarity
-                CPL: u1,
-                ///  CK pin enable
-                CKEN: u1,
-                ///  STOP bits length
-                STB: u2,
-                ///  LIN mode enable
-                LMEN: u1,
-                padding: u17,
-            }),
-            ///  Control register 2
-            CTL2: mmio.Mmio(packed struct(u32) {
-                ///  Error interrupt enable
-                ERRIE: u1,
-                ///  IrDA mode enable
-                IREN: u1,
-                ///  IrDA low-power
-                IRLP: u1,
-                ///  Half-duplex selection
-                HDEN: u1,
-                ///  Smartcard NACK enable
-                NKEN: u1,
-                ///  Smartcard mode enable
-                SCEN: u1,
-                ///  DMA request enable for reception
-                DENR: u1,
-                ///  DMA request enable for transmission
-                DENT: u1,
-                ///  RTS enable
-                RTSEN: u1,
-                ///  CTS enable
-                CTSEN: u1,
-                ///  CTS interrupt enable
-                CTSIE: u1,
-                padding: u21,
-            }),
-            ///  Guard time and prescaler register
-            GP: mmio.Mmio(packed struct(u32) {
-                ///  Prescaler value
-                PSC: u8,
-                ///  Guard time value in Smartcard mode
-                GUAT: u8,
-                padding: u16,
-            }),
-        };
-
-        ///  Advanced-timers
-        pub const TIMER0 = extern struct {
-            ///  control register 0
-            CTL0: mmio.Mmio(packed struct(u16) {
-                ///  Counter enable
-                CEN: u1,
-                ///  Update disable
-                UPDIS: u1,
-                ///  Update source
-                UPS: u1,
-                ///  Single pulse mode
-                SPM: u1,
-                ///  Direction
-                DIR: u1,
-                ///  Counter aligns mode selection
-                CAM: u2,
-                ///  Auto-reload shadow enable
-                ARSE: u1,
-                ///  Clock division
-                CKDIV: u2,
-                padding: u6,
-            }),
-            reserved4: [2]u8,
-            ///  control register 1
-            CTL1: mmio.Mmio(packed struct(u16) {
-                ///  Commutation control shadow enable
-                CCSE: u1,
-                reserved2: u1,
-                ///  Commutation control shadow register update control
-                CCUC: u1,
-                ///  DMA request source selection
-                DMAS: u1,
-                ///  Master mode control
-                MMC: u3,
-                ///  Channel 0 trigger input selection
-                TI0S: u1,
-                ///  Idle state of channel 0 output
-                ISO0: u1,
-                ///  Idle state of channel 0 complementary output
-                ISO0N: u1,
-                ///  Idle state of channel 1 output
-                ISO1: u1,
-                ///  Idle state of channel 1 complementary output
-                ISO1N: u1,
-                ///  Idle state of channel 2 output
-                ISO2: u1,
-                ///  Idle state of channel 2 complementary output
-                ISO2N: u1,
-                ///  Idle state of channel 3 output
-                ISO3: u1,
-                padding: u1,
-            }),
-            reserved8: [2]u8,
-            ///  slave mode configuration register
-            SMCFG: mmio.Mmio(packed struct(u16) {
-                ///  Slave mode selection
-                SMC: u3,
-                reserved4: u1,
-                ///  Trigger selection
-                TRGS: u3,
-                ///  Master/Slave mode
-                MSM: u1,
-                ///  External trigger filter control
-                ETFC: u4,
-                ///  External trigger prescaler
-                ETPSC: u2,
-                ///  Part of SMC for enable External clock mode1
-                SMC1: u1,
-                ///  External trigger polarity
-                ETP: u1,
-            }),
-            reserved12: [2]u8,
-            ///  DMA/Interrupt enable register
-            DMAINTEN: mmio.Mmio(packed struct(u16) {
-                ///  Update interrupt enable
-                UPIE: u1,
-                ///  Channel 0 capture/compare interrupt enable
-                CH0IE: u1,
-                ///  Channel 1 capture/compare interrupt enable
-                CH1IE: u1,
-                ///  Channel 2 capture/compare interrupt enable
-                CH2IE: u1,
-                ///  Channel 3 capture/compare interrupt enable
-                CH3IE: u1,
-                ///  commutation interrupt enable
-                CMTIE: u1,
-                ///  Trigger interrupt enable
-                TRGIE: u1,
-                ///  Break interrupt enable
-                BRKIE: u1,
-                ///  Update DMA request enable
-                UPDEN: u1,
-                ///  Channel 0 capture/compare DMA request enable
-                CH0DEN: u1,
-                ///  Channel 1 capture/compare DMA request enable
-                CH1DEN: u1,
-                ///  Channel 2 capture/compare DMA request enable
-                CH2DEN: u1,
-                ///  Channel 3 capture/compare DMA request enable
-                CH3DEN: u1,
-                ///  Commutation DMA request enable
-                CMTDEN: u1,
-                ///  Trigger DMA request enable
-                TRGDEN: u1,
-                padding: u1,
-            }),
-            reserved16: [2]u8,
-            ///  Interrupt flag register
-            INTF: mmio.Mmio(packed struct(u16) {
-                ///  Update interrupt flag
-                UPIF: u1,
-                ///  Channel 0 capture/compare interrupt flag
-                CH0IF: u1,
-                ///  Channel 1 capture/compare interrupt flag
-                CH1IF: u1,
-                ///  Channel 2 capture/compare interrupt flag
-                CH2IF: u1,
-                ///  Channel 3 capture/compare interrupt flag
-                CH3IF: u1,
-                ///  Channel commutation interrupt flag
-                CMTIF: u1,
-                ///  Trigger interrupt flag
-                TRGIF: u1,
-                ///  Break interrupt flag
-                BRKIF: u1,
-                reserved9: u1,
-                ///  Channel 0 over capture flag
-                CH0OF: u1,
-                ///  Channel 1 over capture flag
-                CH1OF: u1,
-                ///  Channel 2 over capture flag
-                CH2OF: u1,
-                ///  Channel 3 over capture flag
-                CH3OF: u1,
-                padding: u3,
-            }),
-            reserved20: [2]u8,
-            ///  Software event generation register
-            SWEVG: mmio.Mmio(packed struct(u16) {
-                ///  Update event generation
-                UPG: u1,
-                ///  Channel 0 capture or compare event generation
-                CH0G: u1,
-                ///  Channel 1 capture or compare event generation
-                CH1G: u1,
-                ///  Channel 2 capture or compare event generation
-                CH2G: u1,
-                ///  Channel 3 capture or compare event generation
-                CH3G: u1,
-                ///  Channel commutation event generation
-                CMTG: u1,
-                ///  Trigger event generation
-                TRGG: u1,
-                ///  Break event generation
-                BRKG: u1,
-                padding: u8,
-            }),
-            reserved24: [2]u8,
-            ///  Channel control register 0 (output mode)
-            CHCTL0_Output: mmio.Mmio(packed struct(u16) {
-                ///  Channel 0 I/O mode selection
-                CH0MS: u2,
-                ///  Channel 0 output compare fast enable
-                CH0COMFEN: u1,
-                ///  Channel 0 compare output shadow enable
-                CH0COMSEN: u1,
-                ///  Channel 0 compare output control
-                CH0COMCTL: u3,
-                ///  Channel 0 output compare clear enable
-                CH0COMCEN: u1,
-                ///  Channel 1 mode selection
-                CH1MS: u2,
-                ///  Channel 1 output compare fast enable
-                CH1COMFEN: u1,
-                ///  Channel 1 output compare shadow enable
-                CH1COMSEN: u1,
-                ///  Channel 1 compare output control
-                CH1COMCTL: u3,
-                ///  Channel 1 output compare clear enable
-                CH1COMCEN: u1,
-            }),
-            reserved28: [2]u8,
-            ///  Channel control register 1 (output mode)
-            CHCTL1_Output: mmio.Mmio(packed struct(u16) {
-                ///  Channel 2 I/O mode selection
-                CH2MS: u2,
-                ///  Channel 2 output compare fast enable
-                CH2COMFEN: u1,
-                ///  Channel 2 compare output shadow enable
-                CH2COMSEN: u1,
-                ///  Channel 2 compare output control
-                CH2COMCTL: u3,
-                ///  Channel 2 output compare clear enable
-                CH2COMCEN: u1,
-                ///  Channel 3 mode selection
-                CH3MS: u2,
-                ///  Channel 3 output compare fast enable
-                CH3COMFEN: u1,
-                ///  Channel 3 output compare shadow enable
-                CH3COMSEN: u1,
-                ///  Channel 3 compare output control
-                CH3COMCTL: u3,
-                ///  Channel 3 output compare clear enable
-                CH3COMCEN: u1,
-            }),
-            reserved32: [2]u8,
-            ///  Channel control register 2
-            CHCTL2: mmio.Mmio(packed struct(u16) {
-                ///  Channel 0 capture/compare function enable
-                CH0EN: u1,
-                ///  Channel 0 capture/compare function polarity
-                CH0P: u1,
-                ///  Channel 0 complementary output enable
-                CH0NEN: u1,
-                ///  Channel 0 complementary output polarity
-                CH0NP: u1,
-                ///  Channel 1 capture/compare function enable
-                CH1EN: u1,
-                ///  Channel 1 capture/compare function polarity
-                CH1P: u1,
-                ///  Channel 1 complementary output enable
-                CH1NEN: u1,
-                ///  Channel 1 complementary output polarity
-                CH1NP: u1,
-                ///  Channel 2 capture/compare function enable
-                CH2EN: u1,
-                ///  Channel 2 capture/compare function polarity
-                CH2P: u1,
-                ///  Channel 2 complementary output enable
-                CH2NEN: u1,
-                ///  Channel 2 complementary output polarity
-                CH2NP: u1,
-                ///  Channel 3 capture/compare function enable
-                CH3EN: u1,
-                ///  Channel 3 capture/compare function polarity
-                CH3P: u1,
-                padding: u2,
-            }),
-            reserved36: [2]u8,
-            ///  counter
-            CNT: mmio.Mmio(packed struct(u16) {
-                ///  current counter value
-                CNT: u16,
-            }),
-            reserved40: [2]u8,
-            ///  prescaler
-            PSC: mmio.Mmio(packed struct(u16) {
-                ///  Prescaler value of the counter clock
-                PSC: u16,
-            }),
-            reserved44: [2]u8,
-            ///  Counter auto reload register
-            CAR: mmio.Mmio(packed struct(u16) {
-                ///  Counter auto reload value
-                CARL: u16,
-            }),
-            reserved48: [2]u8,
-            ///  Counter repetition register
-            CREP: mmio.Mmio(packed struct(u16) {
-                ///  Counter repetition value
-                CREP: u8,
-                padding: u8,
-            }),
-            reserved52: [2]u8,
-            ///  Channel 0 capture/compare value register
-            CH0CV: mmio.Mmio(packed struct(u16) {
-                ///  Capture or compare value of channel0
-                CH0VAL: u16,
-            }),
-            reserved56: [2]u8,
-            ///  Channel 1 capture/compare value register
-            CH1CV: mmio.Mmio(packed struct(u16) {
-                ///  Capture or compare value of channel1
-                CH1VAL: u16,
-            }),
-            reserved60: [2]u8,
-            ///  Channel 2 capture/compare value register
-            CH2CV: mmio.Mmio(packed struct(u16) {
-                ///  Capture or compare value of channel 2
-                CH2VAL: u16,
-            }),
-            reserved64: [2]u8,
-            ///  Channel 3 capture/compare value register
-            CH3CV: mmio.Mmio(packed struct(u16) {
-                ///  Capture or compare value of channel 3
-                CH3VAL: u16,
-            }),
-            reserved68: [2]u8,
-            ///  channel complementary protection register
-            CCHP: mmio.Mmio(packed struct(u16) {
-                ///  Dead time configure
-                DTCFG: u8,
-                ///  Complementary register protect control
-                PROT: u2,
-                ///  Idle mode off-state configure
-                IOS: u1,
-                ///  Run mode off-state configure
-                ROS: u1,
-                ///  Break enable
-                BRKEN: u1,
-                ///  Break polarity
-                BRKP: u1,
-                ///  Output automatic enable
-                OAEN: u1,
-                ///  Primary output enable
-                POEN: u1,
-            }),
-            reserved72: [2]u8,
-            ///  DMA configuration register
-            DMACFG: mmio.Mmio(packed struct(u16) {
-                ///  DMA transfer access start address
-                DMATA: u5,
-                reserved8: u3,
-                ///  DMA transfer count
-                DMATC: u5,
-                padding: u3,
-            }),
-            reserved76: [2]u8,
-            ///  DMA transfer buffer register
-            DMATB: mmio.Mmio(packed struct(u16) {
-                ///  DMA transfer buffer
-                DMATB: u16,
-            }),
-        };
-
-        ///  General-purpose-timers
-        pub const TIMER1 = extern struct {
-            ///  control register 0
-            CTL0: mmio.Mmio(packed struct(u16) {
-                ///  Counter enable
-                CEN: u1,
-                ///  Update disable
-                UPDIS: u1,
-                ///  Update source
-                UPS: u1,
-                ///  Single pulse mode
-                SPM: u1,
-                ///  Direction
-                DIR: u1,
-                ///  Counter aligns mode selection
-                CAM: u2,
-                ///  Auto-reload shadow enable
-                ARSE: u1,
-                ///  Clock division
-                CKDIV: u2,
-                padding: u6,
-            }),
-            reserved4: [2]u8,
-            ///  control register 1
-            CTL1: mmio.Mmio(packed struct(u16) {
-                reserved3: u3,
-                ///  DMA request source selection
-                DMAS: u1,
-                ///  Master mode control
-                MMC: u3,
-                ///  Channel 0 trigger input selection
-                TI0S: u1,
-                padding: u8,
-            }),
-            reserved8: [2]u8,
-            ///  slave mode control register
-            SMCFG: mmio.Mmio(packed struct(u16) {
-                ///  Slave mode control
-                SMC: u3,
-                reserved4: u1,
-                ///  Trigger selection
-                TRGS: u3,
-                ///  Master-slave mode
-                MSM: u1,
-                ///  External trigger filter control
-                ETFC: u4,
-                ///  External trigger prescaler
-                ETPSC: u2,
-                ///  Part of SMC for enable External clock mode1
-                SMC1: u1,
-                ///  External trigger polarity
-                ETP: u1,
-            }),
-            reserved12: [2]u8,
-            ///  DMA/Interrupt enable register
-            DMAINTEN: mmio.Mmio(packed struct(u16) {
-                ///  Update interrupt enable
-                UPIE: u1,
-                ///  Channel 0 capture/compare interrupt enable
-                CH0IE: u1,
-                ///  Channel 1 capture/compare interrupt enable
-                CH1IE: u1,
-                ///  Channel 2 capture/compare interrupt enable
-                CH2IE: u1,
-                ///  Channel 3 capture/compare interrupt enable
-                CH3IE: u1,
-                reserved6: u1,
-                ///  Trigger interrupt enable
-                TRGIE: u1,
-                reserved8: u1,
-                ///  Update DMA request enable
-                UPDEN: u1,
-                ///  Channel 0 capture/compare DMA request enable
-                CH0DEN: u1,
-                ///  Channel 1 capture/compare DMA request enable
-                CH1DEN: u1,
-                ///  Channel 2 capture/compare DMA request enable
-                CH2DEN: u1,
-                ///  Channel 3 capture/compare DMA request enable
-                CH3DEN: u1,
-                reserved14: u1,
-                ///  Trigger DMA request enable
-                TRGDEN: u1,
-                padding: u1,
-            }),
-            reserved16: [2]u8,
-            ///  interrupt flag register
-            INTF: mmio.Mmio(packed struct(u16) {
-                ///  Update interrupt flag
-                UPIF: u1,
-                ///  Channel 0 capture/compare interrupt flag
-                CH0IF: u1,
-                ///  Channel 1 capture/compare interrupt flag
-                CH1IF: u1,
-                ///  Channel 2 capture/compare interrupt enable
-                CH2IF: u1,
-                ///  Channel 3 capture/compare interrupt enable
-                CH3IF: u1,
-                reserved6: u1,
-                ///  Trigger interrupt flag
-                TRGIF: u1,
-                reserved9: u2,
-                ///  Channel 0 over capture flag
-                CH0OF: u1,
-                ///  Channel 1 over capture flag
-                CH1OF: u1,
-                ///  Channel 2 over capture flag
-                CH2OF: u1,
-                ///  Channel 3 over capture flag
-                CH3OF: u1,
-                padding: u3,
-            }),
-            reserved20: [2]u8,
-            ///  event generation register
-            SWEVG: mmio.Mmio(packed struct(u16) {
-                ///  Update generation
-                UPG: u1,
-                ///  Channel 0 capture or compare event generation
-                CH0G: u1,
-                ///  Channel 1 capture or compare event generation
-                CH1G: u1,
-                ///  Channel 2 capture or compare event generation
-                CH2G: u1,
-                ///  Channel 3 capture or compare event generation
-                CH3G: u1,
-                reserved6: u1,
-                ///  Trigger event generation
-                TRGG: u1,
-                padding: u9,
-            }),
-            reserved24: [2]u8,
-            ///  Channel control register 0 (output mode)
-            CHCTL0_Output: mmio.Mmio(packed struct(u16) {
-                ///  Channel 0 I/O mode selection
-                CH0MS: u2,
-                ///  Channel 0 output compare fast enable
-                CH0COMFEN: u1,
-                ///  Channel 0 compare output shadow enable
-                CH0COMSEN: u1,
-                ///  Channel 0 compare output control
-                CH0COMCTL: u3,
-                ///  Channel 0 output compare clear enable
-                CH0COMCEN: u1,
-                ///  Channel 1 mode selection
-                CH1MS: u2,
-                ///  Channel 1 output compare fast enable
-                CH1COMFEN: u1,
-                ///  Channel 1 output compare shadow enable
-                CH1COMSEN: u1,
-                ///  Channel 1 compare output control
-                CH1COMCTL: u3,
-                ///  Channel 1 output compare clear enable
-                CH1COMCEN: u1,
-            }),
-            reserved28: [2]u8,
-            ///  Channel control register 1 (output mode)
-            CHCTL1_Output: mmio.Mmio(packed struct(u16) {
-                ///  Channel 2 I/O mode selection
-                CH2MS: u2,
-                ///  Channel 2 output compare fast enable
-                CH2COMFEN: u1,
-                ///  Channel 2 compare output shadow enable
-                CH2COMSEN: u1,
-                ///  Channel 2 compare output control
-                CH2COMCTL: u3,
-                ///  Channel 2 output compare clear enable
-                CH2COMCEN: u1,
-                ///  Channel 3 mode selection
-                CH3MS: u2,
-                ///  Channel 3 output compare fast enable
-                CH3COMFEN: u1,
-                ///  Channel 3 output compare shadow enable
-                CH3COMSEN: u1,
-                ///  Channel 3 compare output control
-                CH3COMCTL: u3,
-                ///  Channel 3 output compare clear enable
-                CH3COMCEN: u1,
-            }),
-            reserved32: [2]u8,
-            ///  Channel control register 2
-            CHCTL2: mmio.Mmio(packed struct(u16) {
-                ///  Channel 0 capture/compare function enable
-                CH0EN: u1,
-                ///  Channel 0 capture/compare function polarity
-                CH0P: u1,
-                reserved4: u2,
-                ///  Channel 1 capture/compare function enable
-                CH1EN: u1,
-                ///  Channel 1 capture/compare function polarity
-                CH1P: u1,
-                reserved8: u2,
-                ///  Channel 2 capture/compare function enable
-                CH2EN: u1,
-                ///  Channel 2 capture/compare function polarity
-                CH2P: u1,
-                reserved12: u2,
-                ///  Channel 3 capture/compare function enable
-                CH3EN: u1,
-                ///  Channel 3 capture/compare function polarity
-                CH3P: u1,
-                padding: u2,
-            }),
-            reserved36: [2]u8,
-            ///  Counter register
-            CNT: mmio.Mmio(packed struct(u16) {
-                ///  counter value
-                CNT: u16,
-            }),
-            reserved40: [2]u8,
-            ///  Prescaler register
-            PSC: mmio.Mmio(packed struct(u16) {
-                ///  Prescaler value of the counter clock
-                PSC: u16,
-            }),
-            reserved44: [2]u8,
-            ///  Counter auto reload register
-            CAR: mmio.Mmio(packed struct(u16) {
-                ///  Counter auto reload value
-                CARL: u16,
-            }),
-            reserved52: [6]u8,
-            ///  Channel 0 capture/compare value register
-            CH0CV: mmio.Mmio(packed struct(u32) {
-                ///  Capture or compare value of channel 0
-                CH0VAL: u16,
-                padding: u16,
-            }),
-            ///  Channel 1 capture/compare value register
-            CH1CV: mmio.Mmio(packed struct(u32) {
-                ///  Capture or compare value of channel1
-                CH1VAL: u16,
-                padding: u16,
-            }),
-            ///  Channel 2 capture/compare value register
-            CH2CV: mmio.Mmio(packed struct(u32) {
-                ///  Capture or compare value of channel 2
-                CH2VAL: u16,
-                padding: u16,
-            }),
-            ///  Channel 3 capture/compare value register
-            CH3CV: mmio.Mmio(packed struct(u32) {
-                ///  Capture or compare value of channel 3
-                CH3VAL: u16,
-                padding: u16,
-            }),
-            reserved72: [4]u8,
-            ///  DMA configuration register
-            DMACFG: mmio.Mmio(packed struct(u16) {
-                ///  DMA transfer access start address
-                DMATA: u5,
-                reserved8: u3,
-                ///  DMA transfer count
-                DMATC: u5,
-                padding: u3,
-            }),
-            reserved76: [2]u8,
-            ///  DMA transfer buffer register
-            DMATB: mmio.Mmio(packed struct(u32) {
-                ///  DMA transfer buffer
-                DMATB: u16,
-                padding: u16,
-            }),
-        };
-    };
-};

From 0eb570d9693d85e894f69a10e3bc915368cba004 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Fri, 22 Sep 2023 09:04:10 +0200
Subject: [PATCH 210/286] Rework for MicroZig Gen 2 (#26)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

Co-authored-by: Felix "xq" Queißner 
---
 build.zig               |   186 +-
 src/boards.zig          |    35 -
 src/chips.zig           |    48 -
 src/chips/STM32F103.zig | 10854 --------------------
 src/chips/STM32F303.zig | 13076 ------------------------
 src/chips/STM32F407.zig | 20004 -------------------------------------
 src/chips/STM32F429.zig | 20419 --------------------------------------
 7 files changed, 150 insertions(+), 64472 deletions(-)
 delete mode 100644 src/boards.zig
 delete mode 100644 src/chips.zig
 delete mode 100644 src/chips/STM32F103.zig
 delete mode 100644 src/chips/STM32F303.zig
 delete mode 100644 src/chips/STM32F407.zig
 delete mode 100644 src/chips/STM32F429.zig

diff --git a/build.zig b/build.zig
index 56ed4e58a..cea2a1682 100644
--- a/build.zig
+++ b/build.zig
@@ -1,38 +1,152 @@
 const std = @import("std");
-const microzig = @import("deps/microzig/build.zig");
-
-pub const boards = @import("src/boards.zig");
-pub const chips = @import("src/chips.zig");
-
-pub fn build(b: *std.build.Builder) void {
-    const optimize = b.standardOptimizeOption(.{});
-    inline for (@typeInfo(boards).Struct.decls) |decl| {
-        if (!decl.is_pub)
-            continue;
-
-        const exe = microzig.addEmbeddedExecutable(b, .{
-            .name = @field(boards, decl.name).name ++ ".minimal",
-            .source_file = .{
-                .path = "test/programs/minimal.zig",
-            },
-            .backing = .{ .board = @field(boards, decl.name) },
-            .optimize = optimize,
-        });
-        exe.installArtifact(b);
-    }
-
-    inline for (@typeInfo(chips).Struct.decls) |decl| {
-        if (!decl.is_pub)
-            continue;
-
-        const exe = microzig.addEmbeddedExecutable(b, .{
-            .name = @field(chips, decl.name).name ++ ".minimal",
-            .source_file = .{
-                .path = "test/programs/minimal.zig",
-            },
-            .backing = .{ .chip = @field(chips, decl.name) },
-            .optimize = optimize,
-        });
-        exe.installArtifact(b);
-    }
+const microzig = @import("root").dependencies.imports.microzig; // HACK: Please import MicroZig always under the name `microzig`. Otherwise the RP2040 module will fail to be properly imported.
+
+fn root() []const u8 {
+    return comptime (std.fs.path.dirname(@src().file) orelse ".");
+}
+const build_root = root();
+
+////////////////////////////////////////
+//      MicroZig Gen 2 Interface      //
+////////////////////////////////////////
+
+pub fn build(b: *std.Build) !void {
+    _ = b;
+    //  Dummy func to make package manager happy
 }
+
+pub const chips = struct {
+    pub const stm32f103x8 = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "STM32F103",
+            .cpu = .cortex_m3,
+            .memory_regions = &.{
+                .{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram },
+            },
+            .register_definition = .{
+                .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F103.json" },
+            },
+        },
+    };
+
+    pub const stm32f303vc = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "STM32F303",
+            .cpu = .cortex_m4,
+            .memory_regions = &.{
+                .{ .offset = 0x08000000, .length = 256 * 1024, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 40 * 1024, .kind = .ram },
+            },
+            .register_definition = .{
+                .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F303.json" },
+            },
+        },
+    };
+
+    pub const stm32f407vg = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "STM32F407",
+            .cpu = .cortex_m4,
+            .memory_regions = &.{
+                .{ .offset = 0x08000000, .length = 1024 * 1024, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 128 * 1024, .kind = .ram },
+                .{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, // CCM RAM
+            },
+            .register_definition = .{
+                .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F407.json" },
+            },
+        },
+    };
+
+    pub const stm32f429zit6u = .{
+        .preferred_format = .elf,
+        .chip = .{
+            .name = "STM32F429",
+            .cpu = .cortex_m4,
+            .memory_regions = &.{
+                .{ .offset = 0x08000000, .length = 2048 * 1024, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 192 * 1024, .kind = .ram },
+                .{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, // CCM RAM
+            },
+            .register_definition = .{
+                .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F429.json" },
+            },
+        },
+    };
+};
+
+pub const boards = struct {
+    pub const stm32f3discovery = .{
+        .preferred_format = .elf,
+        .chip = chips.stm32f303vc.chip,
+        .board = .{
+            .name = "STM32F3DISCOVERY",
+            .source_file = .{ .path = build_root ++ "/src/boards/STM32F3DISCOVERY.zig" },
+        },
+    };
+
+    pub const stm32f4discovery = .{
+        .preferred_format = .elf,
+        .chip = chips.stm32f407vg.chip,
+        .board = .{
+            .name = "STM32F4DISCOVERY",
+            .source_file = .{ .path = build_root ++ "/src/boards/STM32F4DISCOVERY.zig" },
+        },
+    };
+
+    pub const stm3240geval = .{
+        .preferred_format = .elf,
+        .chip = chips.stm32f407vg.chip,
+        .board = .{
+            .name = "STM3240G_EVAL",
+            .source_file = .{ .path = build_root ++ "/src/boards/STM3240G_EVAL.zig" },
+        },
+    };
+
+    pub const stm32f429idiscovery = .{
+        .preferred_format = .elf,
+        .chip = chips.stm32f429zit6u.chip,
+        .board = .{
+            .name = "STM32F429IDISCOVERY",
+            .source_file = .{ .path = build_root ++ "/src/boards/STM32F429IDISCOVERY.zig" },
+        },
+    };
+};
+
+// pub fn build(b: *std.build.Builder) void {
+//     _ = b;
+// const optimize = b.standardOptimizeOption(.{});
+// inline for (@typeInfo(boards).Struct.decls) |decl| {
+//     if (!decl.is_pub)
+//         continue;
+
+//     const exe = microzig.addEmbeddedExecutable(b, .{
+//         .name = @field(boards, decl.name).name ++ ".minimal",
+//         .source_file = .{
+//             .path = "test/programs/minimal.zig",
+//         },
+//         .backing = .{ .board = @field(boards, decl.name) },
+//         .optimize = optimize,
+//     });
+//     exe.installArtifact(b);
+// }
+
+// inline for (@typeInfo(chips).Struct.decls) |decl| {
+//     if (!decl.is_pub)
+//         continue;
+
+//     const exe = microzig.addEmbeddedExecutable(b, .{
+//         .name = @field(chips, decl.name).name ++ ".minimal",
+//         .source_file = .{
+//             .path = "test/programs/minimal.zig",
+//         },
+//         .backing = .{ .chip = @field(chips, decl.name) },
+//         .optimize = optimize,
+//     });
+//     exe.installArtifact(b);
+// }
+// }
diff --git a/src/boards.zig b/src/boards.zig
deleted file mode 100644
index 9f9c3fa5d..000000000
--- a/src/boards.zig
+++ /dev/null
@@ -1,35 +0,0 @@
-const std = @import("std");
-const microzig = @import("../deps/microzig/build.zig");
-const Board = microzig.Board;
-
-const chips = @import("chips.zig");
-
-fn root() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse unreachable;
-}
-
-const root_path = root() ++ "/";
-
-pub const stm32f3discovery = Board{
-    .name = "STM32F3DISCOVERY",
-    .source = .{ .path = root_path ++ "boards/STM32F3DISCOVERY.zig" },
-    .chip = chips.stm32f303vc,
-};
-
-pub const stm32f4discovery = Board{
-    .name = "STM32F4DISCOVERY",
-    .source = .{ .path = root_path ++ "boards/STM32F4DISCOVERY.zig" },
-    .chip = chips.stm32f407vg,
-};
-
-pub const stm3240geval = Board{
-    .name = "STM3240G_EVAL",
-    .source = .{ .path = root_path ++ "boards/STM3240G_EVAL.zig" },
-    .chip = chips.stm32f407vg,
-};
-
-pub const stm32f429idiscovery = Board{
-    .name = "STM32F429IDISCOVERY",
-    .source = .{ .path = root_path ++ "boards/STM32F429IDISCOVERY.zig" },
-    .chip = chips.stm32f429zit6u,
-};
diff --git a/src/chips.zig b/src/chips.zig
deleted file mode 100644
index c7a2eda64..000000000
--- a/src/chips.zig
+++ /dev/null
@@ -1,48 +0,0 @@
-const std = @import("std");
-const microzig = @import("../deps/microzig/build.zig");
-const Chip = microzig.Chip;
-const MemoryRegion = microzig.MemoryRegion;
-
-fn root_dir() []const u8 {
-    return std.fs.path.dirname(@src().file) orelse ".";
-}
-
-pub const stm32f103x8 = Chip.from_standard_paths(root_dir(), .{
-    .name = "STM32F103",
-    .cpu = microzig.cpus.cortex_m3,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram },
-    },
-});
-
-pub const stm32f303vc = Chip.from_standard_paths(root_dir(), .{
-    .name = "STM32F303",
-    .cpu = microzig.cpus.cortex_m4,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x08000000, .length = 256 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 40 * 1024, .kind = .ram },
-    },
-});
-
-pub const stm32f407vg = Chip.from_standard_paths(root_dir(), .{
-    .name = "STM32F407",
-    .cpu = microzig.cpus.cortex_m4,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x08000000, .length = 1024 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 128 * 1024, .kind = .ram },
-        // CCM RAM
-        MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram },
-    },
-});
-
-pub const stm32f429zit6u = Chip.from_standard_paths(root_dir(), .{
-    .name = "STM32F429",
-    .cpu = microzig.cpus.cortex_m4,
-    .memory_regions = &.{
-        MemoryRegion{ .offset = 0x08000000, .length = 2048 * 1024, .kind = .flash },
-        MemoryRegion{ .offset = 0x20000000, .length = 192 * 1024, .kind = .ram },
-        // CCM RAM
-        MemoryRegion{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram },
-    },
-});
diff --git a/src/chips/STM32F103.zig b/src/chips/STM32F103.zig
deleted file mode 100644
index 5a174116b..000000000
--- a/src/chips/STM32F103.zig
+++ /dev/null
@@ -1,10854 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    ///  STM32F103
-    pub const STM32F103 = struct {
-        pub const properties = struct {
-            pub const @"cpu.nvic_prio_bits" = "4";
-            pub const @"cpu.mpu" = "false";
-            pub const @"cpu.fpu" = "false";
-            pub const @"cpu.revision" = "r1p1";
-            pub const @"cpu.vendor_systick_config" = "false";
-            pub const @"cpu.endian" = "little";
-            pub const @"cpu.name" = "CM3";
-        };
-
-        pub const VectorTable = extern struct {
-            const Handler = micro.interrupt.Handler;
-            const unhandled = micro.interrupt.unhandled;
-
-            initial_stack_pointer: u32,
-            Reset: Handler = unhandled,
-            NMI: Handler = unhandled,
-            HardFault: Handler = unhandled,
-            MemManageFault: Handler = unhandled,
-            BusFault: Handler = unhandled,
-            UsageFault: Handler = unhandled,
-            reserved5: [4]u32 = undefined,
-            SVCall: Handler = unhandled,
-            DebugMonitor: Handler = unhandled,
-            reserved11: [1]u32 = undefined,
-            PendSV: Handler = unhandled,
-            SysTick: Handler = unhandled,
-            ///  Window Watchdog interrupt
-            WWDG: Handler = unhandled,
-            ///  PVD through EXTI line detection interrupt
-            PVD: Handler = unhandled,
-            ///  Tamper interrupt
-            TAMPER: Handler = unhandled,
-            ///  RTC global interrupt
-            RTC: Handler = unhandled,
-            ///  Flash global interrupt
-            FLASH: Handler = unhandled,
-            ///  RCC global interrupt
-            RCC: Handler = unhandled,
-            reserved20: [5]u32 = undefined,
-            ///  DMA1 Channel1 global interrupt
-            DMA1_Channel1: Handler = unhandled,
-            reserved26: [6]u32 = undefined,
-            ///  ADC1 and ADC2 global interrupt
-            ADC1_2: Handler = unhandled,
-            ///  USB High Priority or CAN TX interrupts
-            USB_HP_CAN_TX: Handler = unhandled,
-            reserved34: [1]u32 = undefined,
-            ///  CAN RX1 interrupt
-            CAN_RX1: Handler = unhandled,
-            reserved36: [2]u32 = undefined,
-            ///  TIM1 Break interrupt
-            TIM1_BRK: Handler = unhandled,
-            ///  TIM1 Update interrupt
-            TIM1_UP: Handler = unhandled,
-            ///  TIM1 Trigger and Commutation interrupts
-            TIM1_TRG_COM: Handler = unhandled,
-            reserved41: [1]u32 = undefined,
-            ///  TIM2 global interrupt
-            TIM2: Handler = unhandled,
-            ///  TIM3 global interrupt
-            TIM3: Handler = unhandled,
-            ///  TIM4 global interrupt
-            TIM4: Handler = unhandled,
-            ///  I2C1 event interrupt
-            I2C1_EV: Handler = unhandled,
-            reserved46: [1]u32 = undefined,
-            ///  I2C2 event interrupt
-            I2C2_EV: Handler = unhandled,
-            reserved48: [1]u32 = undefined,
-            ///  SPI1 global interrupt
-            SPI1: Handler = unhandled,
-            ///  SPI2 global interrupt
-            SPI2: Handler = unhandled,
-            ///  USART1 global interrupt
-            USART1: Handler = unhandled,
-            ///  USART2 global interrupt
-            USART2: Handler = unhandled,
-            ///  USART3 global interrupt
-            USART3: Handler = unhandled,
-            reserved54: [3]u32 = undefined,
-            ///  TIM8 Break interrupt
-            TIM8_BRK: Handler = unhandled,
-            reserved58: [3]u32 = undefined,
-            ///  ADC3 global interrupt
-            ADC3: Handler = unhandled,
-            ///  FSMC global interrupt
-            FSMC: Handler = unhandled,
-            ///  SDIO global interrupt
-            SDIO: Handler = unhandled,
-            ///  TIM5 global interrupt
-            TIM5: Handler = unhandled,
-            ///  SPI3 global interrupt
-            SPI3: Handler = unhandled,
-            ///  UART4 global interrupt
-            UART4: Handler = unhandled,
-            ///  UART5 global interrupt
-            UART5: Handler = unhandled,
-            ///  TIM6 global interrupt
-            TIM6: Handler = unhandled,
-            ///  TIM7 global interrupt
-            TIM7: Handler = unhandled,
-            ///  DMA2 Channel1 global interrupt
-            DMA2_Channel1: Handler = unhandled,
-        };
-
-        pub const peripherals = struct {
-            ///  General purpose timer
-            pub const TIM2 = @as(*volatile types.TIM2, @ptrFromInt(0x40000000));
-            ///  General purpose timer
-            pub const TIM3 = @as(*volatile types.TIM2, @ptrFromInt(0x40000400));
-            ///  General purpose timer
-            pub const TIM4 = @as(*volatile types.TIM2, @ptrFromInt(0x40000800));
-            ///  General purpose timer
-            pub const TIM5 = @as(*volatile types.TIM2, @ptrFromInt(0x40000c00));
-            ///  Basic timer
-            pub const TIM6 = @as(*volatile types.TIM6, @ptrFromInt(0x40001000));
-            ///  Basic timer
-            pub const TIM7 = @as(*volatile types.TIM6, @ptrFromInt(0x40001400));
-            ///  General purpose timer
-            pub const TIM12 = @as(*volatile types.TIM9, @ptrFromInt(0x40001800));
-            ///  General purpose timer
-            pub const TIM13 = @as(*volatile types.TIM10, @ptrFromInt(0x40001c00));
-            ///  General purpose timer
-            pub const TIM14 = @as(*volatile types.TIM10, @ptrFromInt(0x40002000));
-            ///  Real time clock
-            pub const RTC = @as(*volatile types.RTC, @ptrFromInt(0x40002800));
-            ///  Window watchdog
-            pub const WWDG = @as(*volatile types.WWDG, @ptrFromInt(0x40002c00));
-            ///  Independent watchdog
-            pub const IWDG = @as(*volatile types.IWDG, @ptrFromInt(0x40003000));
-            ///  Serial peripheral interface
-            pub const SPI2 = @as(*volatile types.SPI1, @ptrFromInt(0x40003800));
-            ///  Serial peripheral interface
-            pub const SPI3 = @as(*volatile types.SPI1, @ptrFromInt(0x40003c00));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART2 = @as(*volatile types.USART1, @ptrFromInt(0x40004400));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART3 = @as(*volatile types.USART1, @ptrFromInt(0x40004800));
-            ///  Universal asynchronous receiver transmitter
-            pub const UART4 = @as(*volatile types.UART4, @ptrFromInt(0x40004c00));
-            ///  Universal asynchronous receiver transmitter
-            pub const UART5 = @as(*volatile types.UART5, @ptrFromInt(0x40005000));
-            ///  Inter integrated circuit
-            pub const I2C1 = @as(*volatile types.I2C1, @ptrFromInt(0x40005400));
-            ///  Inter integrated circuit
-            pub const I2C2 = @as(*volatile types.I2C1, @ptrFromInt(0x40005800));
-            ///  Universal serial bus full-speed device interface
-            pub const USB = @as(*volatile types.USB, @ptrFromInt(0x40005c00));
-            ///  Controller area network
-            pub const CAN1 = @as(*volatile types.CAN1, @ptrFromInt(0x40006400));
-            ///  Controller area network
-            pub const CAN2 = @as(*volatile types.CAN1, @ptrFromInt(0x40006800));
-            ///  Backup registers
-            pub const BKP = @as(*volatile types.BKP, @ptrFromInt(0x40006c00));
-            ///  Power control
-            pub const PWR = @as(*volatile types.PWR, @ptrFromInt(0x40007000));
-            ///  Digital to analog converter
-            pub const DAC = @as(*volatile types.DAC, @ptrFromInt(0x40007400));
-            ///  Alternate function I/O
-            pub const AFIO = @as(*volatile types.AFIO, @ptrFromInt(0x40010000));
-            ///  EXTI
-            pub const EXTI = @as(*volatile types.EXTI, @ptrFromInt(0x40010400));
-            ///  General purpose I/O
-            pub const GPIOA = @as(*volatile types.GPIOA, @ptrFromInt(0x40010800));
-            ///  General purpose I/O
-            pub const GPIOB = @as(*volatile types.GPIOA, @ptrFromInt(0x40010c00));
-            ///  General purpose I/O
-            pub const GPIOC = @as(*volatile types.GPIOA, @ptrFromInt(0x40011000));
-            ///  General purpose I/O
-            pub const GPIOD = @as(*volatile types.GPIOA, @ptrFromInt(0x40011400));
-            ///  General purpose I/O
-            pub const GPIOE = @as(*volatile types.GPIOA, @ptrFromInt(0x40011800));
-            ///  General purpose I/O
-            pub const GPIOF = @as(*volatile types.GPIOA, @ptrFromInt(0x40011c00));
-            ///  General purpose I/O
-            pub const GPIOG = @as(*volatile types.GPIOA, @ptrFromInt(0x40012000));
-            ///  Analog to digital converter
-            pub const ADC1 = @as(*volatile types.ADC1, @ptrFromInt(0x40012400));
-            ///  Analog to digital converter
-            pub const ADC2 = @as(*volatile types.ADC2, @ptrFromInt(0x40012800));
-            ///  Advanced timer
-            pub const TIM1 = @as(*volatile types.TIM1, @ptrFromInt(0x40012c00));
-            ///  Serial peripheral interface
-            pub const SPI1 = @as(*volatile types.SPI1, @ptrFromInt(0x40013000));
-            ///  Advanced timer
-            pub const TIM8 = @as(*volatile types.TIM1, @ptrFromInt(0x40013400));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART1 = @as(*volatile types.USART1, @ptrFromInt(0x40013800));
-            ///  Analog to digital converter
-            pub const ADC3 = @as(*volatile types.ADC2, @ptrFromInt(0x40013c00));
-            ///  General purpose timer
-            pub const TIM9 = @as(*volatile types.TIM9, @ptrFromInt(0x40014c00));
-            ///  General purpose timer
-            pub const TIM10 = @as(*volatile types.TIM10, @ptrFromInt(0x40015000));
-            ///  General purpose timer
-            pub const TIM11 = @as(*volatile types.TIM10, @ptrFromInt(0x40015400));
-            ///  Secure digital input/output interface
-            pub const SDIO = @as(*volatile types.SDIO, @ptrFromInt(0x40018000));
-            ///  DMA controller
-            pub const DMA1 = @as(*volatile types.DMA1, @ptrFromInt(0x40020000));
-            ///  DMA controller
-            pub const DMA2 = @as(*volatile types.DMA1, @ptrFromInt(0x40020400));
-            ///  Reset and clock control
-            pub const RCC = @as(*volatile types.RCC, @ptrFromInt(0x40021000));
-            ///  FLASH
-            pub const FLASH = @as(*volatile types.FLASH, @ptrFromInt(0x40022000));
-            ///  CRC calculation unit
-            pub const CRC = @as(*volatile types.CRC, @ptrFromInt(0x40023000));
-            ///  Ethernet: media access control
-            pub const ETHERNET_MAC = @as(*volatile types.ETHERNET_MAC, @ptrFromInt(0x40028000));
-            ///  Ethernet: MAC management counters
-            pub const ETHERNET_MMC = @as(*volatile types.ETHERNET_MMC, @ptrFromInt(0x40028100));
-            ///  Ethernet: Precision time protocol
-            pub const ETHERNET_PTP = @as(*volatile types.ETHERNET_PTP, @ptrFromInt(0x40028700));
-            ///  Ethernet: DMA controller operation
-            pub const ETHERNET_DMA = @as(*volatile types.ETHERNET_DMA, @ptrFromInt(0x40029000));
-            ///  USB on the go full speed
-            pub const OTG_FS_GLOBAL = @as(*volatile types.OTG_FS_GLOBAL, @ptrFromInt(0x50000000));
-            ///  USB on the go full speed
-            pub const OTG_FS_HOST = @as(*volatile types.OTG_FS_HOST, @ptrFromInt(0x50000400));
-            ///  USB on the go full speed
-            pub const OTG_FS_DEVICE = @as(*volatile types.OTG_FS_DEVICE, @ptrFromInt(0x50000800));
-            ///  USB on the go full speed
-            pub const OTG_FS_PWRCLK = @as(*volatile types.OTG_FS_PWRCLK, @ptrFromInt(0x50000e00));
-            ///  Flexible static memory controller
-            pub const FSMC = @as(*volatile types.FSMC, @ptrFromInt(0xa0000000));
-            ///  System control block ACTLR
-            pub const SCB_ACTRL = @as(*volatile types.SCB_ACTRL, @ptrFromInt(0xe000e008));
-            ///  SysTick timer
-            pub const STK = @as(*volatile types.STK, @ptrFromInt(0xe000e010));
-            ///  Nested Vectored Interrupt Controller
-            pub const NVIC = @as(*volatile types.NVIC, @ptrFromInt(0xe000e100));
-            ///  System control block
-            pub const SCB = @as(*volatile types.SCB, @ptrFromInt(0xe000ed00));
-            ///  Memory protection unit
-            pub const MPU = @as(*volatile types.MPU, @ptrFromInt(0xe000ed90));
-            ///  Nested vectored interrupt controller
-            pub const NVIC_STIR = @as(*volatile types.NVIC_STIR, @ptrFromInt(0xe000ef00));
-            ///  Debug support
-            pub const DBG = @as(*volatile types.DBG, @ptrFromInt(0xe0042000));
-        };
-    };
-};
-
-pub const types = struct {
-    ///  Flexible static memory controller
-    pub const FSMC = extern struct {
-        ///  SRAM/NOR-Flash chip-select control register 1
-        BCR1: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            reserved11: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 1
-        BTR1: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 2
-        BCR2: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 2
-        BTR2: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 3
-        BCR3: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 3
-        BTR3: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 4
-        BCR4: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 4
-        BTR4: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved96: [64]u8,
-        ///  PC Card/NAND Flash control register 2
-        PCR2: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 2
-        SR2: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 2
-        PMEM2: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 2
-        PATT2: mmio.Mmio(packed struct(u32) {
-            ///  Attribute memory x setup time
-            ATTSETx: u8,
-            ///  Attribute memory x wait time
-            ATTWAITx: u8,
-            ///  Attribute memory x hold time
-            ATTHOLDx: u8,
-            ///  Attribute memory x databus HiZ time
-            ATTHIZx: u8,
-        }),
-        reserved116: [4]u8,
-        ///  ECC result register 2
-        ECCR2: mmio.Mmio(packed struct(u32) {
-            ///  ECC result
-            ECCx: u32,
-        }),
-        reserved128: [8]u8,
-        ///  PC Card/NAND Flash control register 3
-        PCR3: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 3
-        SR3: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 3
-        PMEM3: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 3
-        PATT3: mmio.Mmio(packed struct(u32) {
-            ///  ATTSETx
-            ATTSETx: u8,
-            ///  ATTWAITx
-            ATTWAITx: u8,
-            ///  ATTHOLDx
-            ATTHOLDx: u8,
-            ///  ATTHIZx
-            ATTHIZx: u8,
-        }),
-        reserved148: [4]u8,
-        ///  ECC result register 3
-        ECCR3: mmio.Mmio(packed struct(u32) {
-            ///  ECCx
-            ECCx: u32,
-        }),
-        reserved160: [8]u8,
-        ///  PC Card/NAND Flash control register 4
-        PCR4: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 4
-        SR4: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 4
-        PMEM4: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 4
-        PATT4: mmio.Mmio(packed struct(u32) {
-            ///  ATTSETx
-            ATTSETx: u8,
-            ///  ATTWAITx
-            ATTWAITx: u8,
-            ///  ATTHOLDx
-            ATTHOLDx: u8,
-            ///  ATTHIZx
-            ATTHIZx: u8,
-        }),
-        ///  I/O space timing register 4
-        PIO4: mmio.Mmio(packed struct(u32) {
-            ///  IOSETx
-            IOSETx: u8,
-            ///  IOWAITx
-            IOWAITx: u8,
-            ///  IOHOLDx
-            IOHOLDx: u8,
-            ///  IOHIZx
-            IOHIZx: u8,
-        }),
-        reserved260: [80]u8,
-        ///  SRAM/NOR-Flash write timing registers 1
-        BWTR1: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            reserved20: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved268: [4]u8,
-        ///  SRAM/NOR-Flash write timing registers 2
-        BWTR2: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            reserved20: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved276: [4]u8,
-        ///  SRAM/NOR-Flash write timing registers 3
-        BWTR3: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            reserved20: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved284: [4]u8,
-        ///  SRAM/NOR-Flash write timing registers 4
-        BWTR4: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            reserved20: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-    };
-
-    ///  Power control
-    pub const PWR = extern struct {
-        ///  Power control register (PWR_CR)
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Low Power Deep Sleep
-            LPDS: u1,
-            ///  Power Down Deep Sleep
-            PDDS: u1,
-            ///  Clear Wake-up Flag
-            CWUF: u1,
-            ///  Clear STANDBY Flag
-            CSBF: u1,
-            ///  Power Voltage Detector Enable
-            PVDE: u1,
-            ///  PVD Level Selection
-            PLS: u3,
-            ///  Disable Backup Domain write protection
-            DBP: u1,
-            padding: u23,
-        }),
-        ///  Power control register (PWR_CR)
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  Wake-Up Flag
-            WUF: u1,
-            ///  STANDBY Flag
-            SBF: u1,
-            ///  PVD Output
-            PVDO: u1,
-            reserved8: u5,
-            ///  Enable WKUP pin
-            EWUP: u1,
-            padding: u23,
-        }),
-    };
-
-    ///  Reset and clock control
-    pub const RCC = extern struct {
-        ///  Clock control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Internal High Speed clock enable
-            HSION: u1,
-            ///  Internal High Speed clock ready flag
-            HSIRDY: u1,
-            reserved3: u1,
-            ///  Internal High Speed clock trimming
-            HSITRIM: u5,
-            ///  Internal High Speed clock Calibration
-            HSICAL: u8,
-            ///  External High Speed clock enable
-            HSEON: u1,
-            ///  External High Speed clock ready flag
-            HSERDY: u1,
-            ///  External High Speed clock Bypass
-            HSEBYP: u1,
-            ///  Clock Security System enable
-            CSSON: u1,
-            reserved24: u4,
-            ///  PLL enable
-            PLLON: u1,
-            ///  PLL clock ready flag
-            PLLRDY: u1,
-            padding: u6,
-        }),
-        ///  Clock configuration register (RCC_CFGR)
-        CFGR: mmio.Mmio(packed struct(u32) {
-            ///  System clock Switch
-            SW: u2,
-            ///  System Clock Switch Status
-            SWS: u2,
-            ///  AHB prescaler
-            HPRE: u4,
-            ///  APB Low speed prescaler (APB1)
-            PPRE1: u3,
-            ///  APB High speed prescaler (APB2)
-            PPRE2: u3,
-            ///  ADC prescaler
-            ADCPRE: u2,
-            ///  PLL entry clock source
-            PLLSRC: u1,
-            ///  HSE divider for PLL entry
-            PLLXTPRE: u1,
-            ///  PLL Multiplication Factor
-            PLLMUL: u4,
-            ///  USB OTG FS prescaler
-            OTGFSPRE: u1,
-            reserved24: u1,
-            ///  Microcontroller clock output
-            MCO: u3,
-            padding: u5,
-        }),
-        ///  Clock interrupt register (RCC_CIR)
-        CIR: mmio.Mmio(packed struct(u32) {
-            ///  LSI Ready Interrupt flag
-            LSIRDYF: u1,
-            ///  LSE Ready Interrupt flag
-            LSERDYF: u1,
-            ///  HSI Ready Interrupt flag
-            HSIRDYF: u1,
-            ///  HSE Ready Interrupt flag
-            HSERDYF: u1,
-            ///  PLL Ready Interrupt flag
-            PLLRDYF: u1,
-            reserved7: u2,
-            ///  Clock Security System Interrupt flag
-            CSSF: u1,
-            ///  LSI Ready Interrupt Enable
-            LSIRDYIE: u1,
-            ///  LSE Ready Interrupt Enable
-            LSERDYIE: u1,
-            ///  HSI Ready Interrupt Enable
-            HSIRDYIE: u1,
-            ///  HSE Ready Interrupt Enable
-            HSERDYIE: u1,
-            ///  PLL Ready Interrupt Enable
-            PLLRDYIE: u1,
-            reserved16: u3,
-            ///  LSI Ready Interrupt Clear
-            LSIRDYC: u1,
-            ///  LSE Ready Interrupt Clear
-            LSERDYC: u1,
-            ///  HSI Ready Interrupt Clear
-            HSIRDYC: u1,
-            ///  HSE Ready Interrupt Clear
-            HSERDYC: u1,
-            ///  PLL Ready Interrupt Clear
-            PLLRDYC: u1,
-            reserved23: u2,
-            ///  Clock security system interrupt clear
-            CSSC: u1,
-            padding: u8,
-        }),
-        ///  APB2 peripheral reset register (RCC_APB2RSTR)
-        APB2RSTR: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function I/O reset
-            AFIORST: u1,
-            reserved2: u1,
-            ///  IO port A reset
-            IOPARST: u1,
-            ///  IO port B reset
-            IOPBRST: u1,
-            ///  IO port C reset
-            IOPCRST: u1,
-            ///  IO port D reset
-            IOPDRST: u1,
-            ///  IO port E reset
-            IOPERST: u1,
-            ///  IO port F reset
-            IOPFRST: u1,
-            ///  IO port G reset
-            IOPGRST: u1,
-            ///  ADC 1 interface reset
-            ADC1RST: u1,
-            ///  ADC 2 interface reset
-            ADC2RST: u1,
-            ///  TIM1 timer reset
-            TIM1RST: u1,
-            ///  SPI 1 reset
-            SPI1RST: u1,
-            ///  TIM8 timer reset
-            TIM8RST: u1,
-            ///  USART1 reset
-            USART1RST: u1,
-            ///  ADC 3 interface reset
-            ADC3RST: u1,
-            reserved19: u3,
-            ///  TIM9 timer reset
-            TIM9RST: u1,
-            ///  TIM10 timer reset
-            TIM10RST: u1,
-            ///  TIM11 timer reset
-            TIM11RST: u1,
-            padding: u10,
-        }),
-        ///  APB1 peripheral reset register (RCC_APB1RSTR)
-        APB1RSTR: mmio.Mmio(packed struct(u32) {
-            ///  Timer 2 reset
-            TIM2RST: u1,
-            ///  Timer 3 reset
-            TIM3RST: u1,
-            ///  Timer 4 reset
-            TIM4RST: u1,
-            ///  Timer 5 reset
-            TIM5RST: u1,
-            ///  Timer 6 reset
-            TIM6RST: u1,
-            ///  Timer 7 reset
-            TIM7RST: u1,
-            ///  Timer 12 reset
-            TIM12RST: u1,
-            ///  Timer 13 reset
-            TIM13RST: u1,
-            ///  Timer 14 reset
-            TIM14RST: u1,
-            reserved11: u2,
-            ///  Window watchdog reset
-            WWDGRST: u1,
-            reserved14: u2,
-            ///  SPI2 reset
-            SPI2RST: u1,
-            ///  SPI3 reset
-            SPI3RST: u1,
-            reserved17: u1,
-            ///  USART 2 reset
-            USART2RST: u1,
-            ///  USART 3 reset
-            USART3RST: u1,
-            ///  UART 4 reset
-            UART4RST: u1,
-            ///  UART 5 reset
-            UART5RST: u1,
-            ///  I2C1 reset
-            I2C1RST: u1,
-            ///  I2C2 reset
-            I2C2RST: u1,
-            ///  USB reset
-            USBRST: u1,
-            reserved25: u1,
-            ///  CAN reset
-            CANRST: u1,
-            reserved27: u1,
-            ///  Backup interface reset
-            BKPRST: u1,
-            ///  Power interface reset
-            PWRRST: u1,
-            ///  DAC interface reset
-            DACRST: u1,
-            padding: u2,
-        }),
-        ///  AHB Peripheral Clock enable register (RCC_AHBENR)
-        AHBENR: mmio.Mmio(packed struct(u32) {
-            ///  DMA1 clock enable
-            DMA1EN: u1,
-            ///  DMA2 clock enable
-            DMA2EN: u1,
-            ///  SRAM interface clock enable
-            SRAMEN: u1,
-            reserved4: u1,
-            ///  FLITF clock enable
-            FLITFEN: u1,
-            reserved6: u1,
-            ///  CRC clock enable
-            CRCEN: u1,
-            reserved8: u1,
-            ///  FSMC clock enable
-            FSMCEN: u1,
-            reserved10: u1,
-            ///  SDIO clock enable
-            SDIOEN: u1,
-            padding: u21,
-        }),
-        ///  APB2 peripheral clock enable register (RCC_APB2ENR)
-        APB2ENR: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function I/O clock enable
-            AFIOEN: u1,
-            reserved2: u1,
-            ///  I/O port A clock enable
-            IOPAEN: u1,
-            ///  I/O port B clock enable
-            IOPBEN: u1,
-            ///  I/O port C clock enable
-            IOPCEN: u1,
-            ///  I/O port D clock enable
-            IOPDEN: u1,
-            ///  I/O port E clock enable
-            IOPEEN: u1,
-            ///  I/O port F clock enable
-            IOPFEN: u1,
-            ///  I/O port G clock enable
-            IOPGEN: u1,
-            ///  ADC 1 interface clock enable
-            ADC1EN: u1,
-            ///  ADC 2 interface clock enable
-            ADC2EN: u1,
-            ///  TIM1 Timer clock enable
-            TIM1EN: u1,
-            ///  SPI 1 clock enable
-            SPI1EN: u1,
-            ///  TIM8 Timer clock enable
-            TIM8EN: u1,
-            ///  USART1 clock enable
-            USART1EN: u1,
-            ///  ADC3 interface clock enable
-            ADC3EN: u1,
-            reserved19: u3,
-            ///  TIM9 Timer clock enable
-            TIM9EN: u1,
-            ///  TIM10 Timer clock enable
-            TIM10EN: u1,
-            ///  TIM11 Timer clock enable
-            TIM11EN: u1,
-            padding: u10,
-        }),
-        ///  APB1 peripheral clock enable register (RCC_APB1ENR)
-        APB1ENR: mmio.Mmio(packed struct(u32) {
-            ///  Timer 2 clock enable
-            TIM2EN: u1,
-            ///  Timer 3 clock enable
-            TIM3EN: u1,
-            ///  Timer 4 clock enable
-            TIM4EN: u1,
-            ///  Timer 5 clock enable
-            TIM5EN: u1,
-            ///  Timer 6 clock enable
-            TIM6EN: u1,
-            ///  Timer 7 clock enable
-            TIM7EN: u1,
-            ///  Timer 12 clock enable
-            TIM12EN: u1,
-            ///  Timer 13 clock enable
-            TIM13EN: u1,
-            ///  Timer 14 clock enable
-            TIM14EN: u1,
-            reserved11: u2,
-            ///  Window watchdog clock enable
-            WWDGEN: u1,
-            reserved14: u2,
-            ///  SPI 2 clock enable
-            SPI2EN: u1,
-            ///  SPI 3 clock enable
-            SPI3EN: u1,
-            reserved17: u1,
-            ///  USART 2 clock enable
-            USART2EN: u1,
-            ///  USART 3 clock enable
-            USART3EN: u1,
-            ///  UART 4 clock enable
-            UART4EN: u1,
-            ///  UART 5 clock enable
-            UART5EN: u1,
-            ///  I2C 1 clock enable
-            I2C1EN: u1,
-            ///  I2C 2 clock enable
-            I2C2EN: u1,
-            ///  USB clock enable
-            USBEN: u1,
-            reserved25: u1,
-            ///  CAN clock enable
-            CANEN: u1,
-            reserved27: u1,
-            ///  Backup interface clock enable
-            BKPEN: u1,
-            ///  Power interface clock enable
-            PWREN: u1,
-            ///  DAC interface clock enable
-            DACEN: u1,
-            padding: u2,
-        }),
-        ///  Backup domain control register (RCC_BDCR)
-        BDCR: mmio.Mmio(packed struct(u32) {
-            ///  External Low Speed oscillator enable
-            LSEON: u1,
-            ///  External Low Speed oscillator ready
-            LSERDY: u1,
-            ///  External Low Speed oscillator bypass
-            LSEBYP: u1,
-            reserved8: u5,
-            ///  RTC clock source selection
-            RTCSEL: u2,
-            reserved15: u5,
-            ///  RTC clock enable
-            RTCEN: u1,
-            ///  Backup domain software reset
-            BDRST: u1,
-            padding: u15,
-        }),
-        ///  Control/status register (RCC_CSR)
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  Internal low speed oscillator enable
-            LSION: u1,
-            ///  Internal low speed oscillator ready
-            LSIRDY: u1,
-            reserved24: u22,
-            ///  Remove reset flag
-            RMVF: u1,
-            reserved26: u1,
-            ///  PIN reset flag
-            PINRSTF: u1,
-            ///  POR/PDR reset flag
-            PORRSTF: u1,
-            ///  Software reset flag
-            SFTRSTF: u1,
-            ///  Independent watchdog reset flag
-            IWDGRSTF: u1,
-            ///  Window watchdog reset flag
-            WWDGRSTF: u1,
-            ///  Low-power reset flag
-            LPWRRSTF: u1,
-        }),
-    };
-
-    ///  General purpose I/O
-    pub const GPIOA = extern struct {
-        ///  Port configuration register low (GPIOn_CRL)
-        CRL: mmio.Mmio(packed struct(u32) {
-            ///  Port n.0 mode bits
-            MODE0: u2,
-            ///  Port n.0 configuration bits
-            CNF0: u2,
-            ///  Port n.1 mode bits
-            MODE1: u2,
-            ///  Port n.1 configuration bits
-            CNF1: u2,
-            ///  Port n.2 mode bits
-            MODE2: u2,
-            ///  Port n.2 configuration bits
-            CNF2: u2,
-            ///  Port n.3 mode bits
-            MODE3: u2,
-            ///  Port n.3 configuration bits
-            CNF3: u2,
-            ///  Port n.4 mode bits
-            MODE4: u2,
-            ///  Port n.4 configuration bits
-            CNF4: u2,
-            ///  Port n.5 mode bits
-            MODE5: u2,
-            ///  Port n.5 configuration bits
-            CNF5: u2,
-            ///  Port n.6 mode bits
-            MODE6: u2,
-            ///  Port n.6 configuration bits
-            CNF6: u2,
-            ///  Port n.7 mode bits
-            MODE7: u2,
-            ///  Port n.7 configuration bits
-            CNF7: u2,
-        }),
-        ///  Port configuration register high (GPIOn_CRL)
-        CRH: mmio.Mmio(packed struct(u32) {
-            ///  Port n.8 mode bits
-            MODE8: u2,
-            ///  Port n.8 configuration bits
-            CNF8: u2,
-            ///  Port n.9 mode bits
-            MODE9: u2,
-            ///  Port n.9 configuration bits
-            CNF9: u2,
-            ///  Port n.10 mode bits
-            MODE10: u2,
-            ///  Port n.10 configuration bits
-            CNF10: u2,
-            ///  Port n.11 mode bits
-            MODE11: u2,
-            ///  Port n.11 configuration bits
-            CNF11: u2,
-            ///  Port n.12 mode bits
-            MODE12: u2,
-            ///  Port n.12 configuration bits
-            CNF12: u2,
-            ///  Port n.13 mode bits
-            MODE13: u2,
-            ///  Port n.13 configuration bits
-            CNF13: u2,
-            ///  Port n.14 mode bits
-            MODE14: u2,
-            ///  Port n.14 configuration bits
-            CNF14: u2,
-            ///  Port n.15 mode bits
-            MODE15: u2,
-            ///  Port n.15 configuration bits
-            CNF15: u2,
-        }),
-        ///  Port input data register (GPIOn_IDR)
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Port input data
-            IDR0: u1,
-            ///  Port input data
-            IDR1: u1,
-            ///  Port input data
-            IDR2: u1,
-            ///  Port input data
-            IDR3: u1,
-            ///  Port input data
-            IDR4: u1,
-            ///  Port input data
-            IDR5: u1,
-            ///  Port input data
-            IDR6: u1,
-            ///  Port input data
-            IDR7: u1,
-            ///  Port input data
-            IDR8: u1,
-            ///  Port input data
-            IDR9: u1,
-            ///  Port input data
-            IDR10: u1,
-            ///  Port input data
-            IDR11: u1,
-            ///  Port input data
-            IDR12: u1,
-            ///  Port input data
-            IDR13: u1,
-            ///  Port input data
-            IDR14: u1,
-            ///  Port input data
-            IDR15: u1,
-            padding: u16,
-        }),
-        ///  Port output data register (GPIOn_ODR)
-        ODR: mmio.Mmio(packed struct(u32) {
-            ///  Port output data
-            ODR0: u1,
-            ///  Port output data
-            ODR1: u1,
-            ///  Port output data
-            ODR2: u1,
-            ///  Port output data
-            ODR3: u1,
-            ///  Port output data
-            ODR4: u1,
-            ///  Port output data
-            ODR5: u1,
-            ///  Port output data
-            ODR6: u1,
-            ///  Port output data
-            ODR7: u1,
-            ///  Port output data
-            ODR8: u1,
-            ///  Port output data
-            ODR9: u1,
-            ///  Port output data
-            ODR10: u1,
-            ///  Port output data
-            ODR11: u1,
-            ///  Port output data
-            ODR12: u1,
-            ///  Port output data
-            ODR13: u1,
-            ///  Port output data
-            ODR14: u1,
-            ///  Port output data
-            ODR15: u1,
-            padding: u16,
-        }),
-        ///  Port bit set/reset register (GPIOn_BSRR)
-        BSRR: mmio.Mmio(packed struct(u32) {
-            ///  Set bit 0
-            BS0: u1,
-            ///  Set bit 1
-            BS1: u1,
-            ///  Set bit 1
-            BS2: u1,
-            ///  Set bit 3
-            BS3: u1,
-            ///  Set bit 4
-            BS4: u1,
-            ///  Set bit 5
-            BS5: u1,
-            ///  Set bit 6
-            BS6: u1,
-            ///  Set bit 7
-            BS7: u1,
-            ///  Set bit 8
-            BS8: u1,
-            ///  Set bit 9
-            BS9: u1,
-            ///  Set bit 10
-            BS10: u1,
-            ///  Set bit 11
-            BS11: u1,
-            ///  Set bit 12
-            BS12: u1,
-            ///  Set bit 13
-            BS13: u1,
-            ///  Set bit 14
-            BS14: u1,
-            ///  Set bit 15
-            BS15: u1,
-            ///  Reset bit 0
-            BR0: u1,
-            ///  Reset bit 1
-            BR1: u1,
-            ///  Reset bit 2
-            BR2: u1,
-            ///  Reset bit 3
-            BR3: u1,
-            ///  Reset bit 4
-            BR4: u1,
-            ///  Reset bit 5
-            BR5: u1,
-            ///  Reset bit 6
-            BR6: u1,
-            ///  Reset bit 7
-            BR7: u1,
-            ///  Reset bit 8
-            BR8: u1,
-            ///  Reset bit 9
-            BR9: u1,
-            ///  Reset bit 10
-            BR10: u1,
-            ///  Reset bit 11
-            BR11: u1,
-            ///  Reset bit 12
-            BR12: u1,
-            ///  Reset bit 13
-            BR13: u1,
-            ///  Reset bit 14
-            BR14: u1,
-            ///  Reset bit 15
-            BR15: u1,
-        }),
-        ///  Port bit reset register (GPIOn_BRR)
-        BRR: mmio.Mmio(packed struct(u32) {
-            ///  Reset bit 0
-            BR0: u1,
-            ///  Reset bit 1
-            BR1: u1,
-            ///  Reset bit 1
-            BR2: u1,
-            ///  Reset bit 3
-            BR3: u1,
-            ///  Reset bit 4
-            BR4: u1,
-            ///  Reset bit 5
-            BR5: u1,
-            ///  Reset bit 6
-            BR6: u1,
-            ///  Reset bit 7
-            BR7: u1,
-            ///  Reset bit 8
-            BR8: u1,
-            ///  Reset bit 9
-            BR9: u1,
-            ///  Reset bit 10
-            BR10: u1,
-            ///  Reset bit 11
-            BR11: u1,
-            ///  Reset bit 12
-            BR12: u1,
-            ///  Reset bit 13
-            BR13: u1,
-            ///  Reset bit 14
-            BR14: u1,
-            ///  Reset bit 15
-            BR15: u1,
-            padding: u16,
-        }),
-        ///  Port configuration lock register
-        LCKR: mmio.Mmio(packed struct(u32) {
-            ///  Port A Lock bit 0
-            LCK0: u1,
-            ///  Port A Lock bit 1
-            LCK1: u1,
-            ///  Port A Lock bit 2
-            LCK2: u1,
-            ///  Port A Lock bit 3
-            LCK3: u1,
-            ///  Port A Lock bit 4
-            LCK4: u1,
-            ///  Port A Lock bit 5
-            LCK5: u1,
-            ///  Port A Lock bit 6
-            LCK6: u1,
-            ///  Port A Lock bit 7
-            LCK7: u1,
-            ///  Port A Lock bit 8
-            LCK8: u1,
-            ///  Port A Lock bit 9
-            LCK9: u1,
-            ///  Port A Lock bit 10
-            LCK10: u1,
-            ///  Port A Lock bit 11
-            LCK11: u1,
-            ///  Port A Lock bit 12
-            LCK12: u1,
-            ///  Port A Lock bit 13
-            LCK13: u1,
-            ///  Port A Lock bit 14
-            LCK14: u1,
-            ///  Port A Lock bit 15
-            LCK15: u1,
-            ///  Lock key
-            LCKK: u1,
-            padding: u15,
-        }),
-    };
-
-    ///  SysTick timer
-    pub const STK = extern struct {
-        ///  SysTick control and status register
-        CTRL: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            ENABLE: u1,
-            ///  SysTick exception request enable
-            TICKINT: u1,
-            ///  Clock source selection
-            CLKSOURCE: u1,
-            reserved16: u13,
-            ///  COUNTFLAG
-            COUNTFLAG: u1,
-            padding: u15,
-        }),
-        ///  SysTick reload value register
-        LOAD_: mmio.Mmio(packed struct(u32) {
-            ///  RELOAD value
-            RELOAD: u24,
-            padding: u8,
-        }),
-        ///  SysTick current value register
-        VAL: mmio.Mmio(packed struct(u32) {
-            ///  Current counter value
-            CURRENT: u24,
-            padding: u8,
-        }),
-        ///  SysTick calibration value register
-        CALIB: mmio.Mmio(packed struct(u32) {
-            ///  Calibration value
-            TENMS: u24,
-            padding: u8,
-        }),
-    };
-
-    ///  System control block
-    pub const SCB = extern struct {
-        ///  CPUID base register
-        CPUID: mmio.Mmio(packed struct(u32) {
-            ///  Revision number
-            Revision: u4,
-            ///  Part number of the processor
-            PartNo: u12,
-            ///  Reads as 0xF
-            Constant: u4,
-            ///  Variant number
-            Variant: u4,
-            ///  Implementer code
-            Implementer: u8,
-        }),
-        ///  Interrupt control and state register
-        ICSR: mmio.Mmio(packed struct(u32) {
-            ///  Active vector
-            VECTACTIVE: u9,
-            reserved11: u2,
-            ///  Return to base level
-            RETTOBASE: u1,
-            ///  Pending vector
-            VECTPENDING: u7,
-            reserved22: u3,
-            ///  Interrupt pending flag
-            ISRPENDING: u1,
-            reserved25: u2,
-            ///  SysTick exception clear-pending bit
-            PENDSTCLR: u1,
-            ///  SysTick exception set-pending bit
-            PENDSTSET: u1,
-            ///  PendSV clear-pending bit
-            PENDSVCLR: u1,
-            ///  PendSV set-pending bit
-            PENDSVSET: u1,
-            reserved31: u2,
-            ///  NMI set-pending bit.
-            NMIPENDSET: u1,
-        }),
-        ///  Vector table offset register
-        VTOR: mmio.Mmio(packed struct(u32) {
-            reserved9: u9,
-            ///  Vector table base offset field
-            TBLOFF: u21,
-            padding: u2,
-        }),
-        ///  Application interrupt and reset control register
-        AIRCR: mmio.Mmio(packed struct(u32) {
-            ///  VECTRESET
-            VECTRESET: u1,
-            ///  VECTCLRACTIVE
-            VECTCLRACTIVE: u1,
-            ///  SYSRESETREQ
-            SYSRESETREQ: u1,
-            reserved8: u5,
-            ///  PRIGROUP
-            PRIGROUP: u3,
-            reserved15: u4,
-            ///  ENDIANESS
-            ENDIANESS: u1,
-            ///  Register key
-            VECTKEYSTAT: u16,
-        }),
-        ///  System control register
-        SCR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  SLEEPONEXIT
-            SLEEPONEXIT: u1,
-            ///  SLEEPDEEP
-            SLEEPDEEP: u1,
-            reserved4: u1,
-            ///  Send Event on Pending bit
-            SEVEONPEND: u1,
-            padding: u27,
-        }),
-        ///  Configuration and control register
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Configures how the processor enters Thread mode
-            NONBASETHRDENA: u1,
-            ///  USERSETMPEND
-            USERSETMPEND: u1,
-            reserved3: u1,
-            ///  UNALIGN_ TRP
-            UNALIGN__TRP: u1,
-            ///  DIV_0_TRP
-            DIV_0_TRP: u1,
-            reserved8: u3,
-            ///  BFHFNMIGN
-            BFHFNMIGN: u1,
-            ///  STKALIGN
-            STKALIGN: u1,
-            padding: u22,
-        }),
-        ///  System handler priority registers
-        SHPR1: mmio.Mmio(packed struct(u32) {
-            ///  Priority of system handler 4
-            PRI_4: u8,
-            ///  Priority of system handler 5
-            PRI_5: u8,
-            ///  Priority of system handler 6
-            PRI_6: u8,
-            padding: u8,
-        }),
-        ///  System handler priority registers
-        SHPR2: mmio.Mmio(packed struct(u32) {
-            reserved24: u24,
-            ///  Priority of system handler 11
-            PRI_11: u8,
-        }),
-        ///  System handler priority registers
-        SHPR3: mmio.Mmio(packed struct(u32) {
-            reserved16: u16,
-            ///  Priority of system handler 14
-            PRI_14: u8,
-            ///  Priority of system handler 15
-            PRI_15: u8,
-        }),
-        ///  System handler control and state register
-        SHCRS: mmio.Mmio(packed struct(u32) {
-            ///  Memory management fault exception active bit
-            MEMFAULTACT: u1,
-            ///  Bus fault exception active bit
-            BUSFAULTACT: u1,
-            reserved3: u1,
-            ///  Usage fault exception active bit
-            USGFAULTACT: u1,
-            reserved7: u3,
-            ///  SVC call active bit
-            SVCALLACT: u1,
-            ///  Debug monitor active bit
-            MONITORACT: u1,
-            reserved10: u1,
-            ///  PendSV exception active bit
-            PENDSVACT: u1,
-            ///  SysTick exception active bit
-            SYSTICKACT: u1,
-            ///  Usage fault exception pending bit
-            USGFAULTPENDED: u1,
-            ///  Memory management fault exception pending bit
-            MEMFAULTPENDED: u1,
-            ///  Bus fault exception pending bit
-            BUSFAULTPENDED: u1,
-            ///  SVC call pending bit
-            SVCALLPENDED: u1,
-            ///  Memory management fault enable bit
-            MEMFAULTENA: u1,
-            ///  Bus fault enable bit
-            BUSFAULTENA: u1,
-            ///  Usage fault enable bit
-            USGFAULTENA: u1,
-            padding: u13,
-        }),
-        ///  Configurable fault status register
-        CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) {
-            ///  IACCVIOL
-            IACCVIOL: u1,
-            ///  DACCVIOL
-            DACCVIOL: u1,
-            reserved3: u1,
-            ///  MUNSTKERR
-            MUNSTKERR: u1,
-            ///  MSTKERR
-            MSTKERR: u1,
-            ///  MLSPERR
-            MLSPERR: u1,
-            reserved7: u1,
-            ///  MMARVALID
-            MMARVALID: u1,
-            ///  Instruction bus error
-            IBUSERR: u1,
-            ///  Precise data bus error
-            PRECISERR: u1,
-            ///  Imprecise data bus error
-            IMPRECISERR: u1,
-            ///  Bus fault on unstacking for a return from exception
-            UNSTKERR: u1,
-            ///  Bus fault on stacking for exception entry
-            STKERR: u1,
-            ///  Bus fault on floating-point lazy state preservation
-            LSPERR: u1,
-            reserved15: u1,
-            ///  Bus Fault Address Register (BFAR) valid flag
-            BFARVALID: u1,
-            ///  Undefined instruction usage fault
-            UNDEFINSTR: u1,
-            ///  Invalid state usage fault
-            INVSTATE: u1,
-            ///  Invalid PC load usage fault
-            INVPC: u1,
-            ///  No coprocessor usage fault.
-            NOCP: u1,
-            reserved24: u4,
-            ///  Unaligned access usage fault
-            UNALIGNED: u1,
-            ///  Divide by zero usage fault
-            DIVBYZERO: u1,
-            padding: u6,
-        }),
-        ///  Hard fault status register
-        HFSR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Vector table hard fault
-            VECTTBL: u1,
-            reserved30: u28,
-            ///  Forced hard fault
-            FORCED: u1,
-            ///  Reserved for Debug use
-            DEBUG_VT: u1,
-        }),
-        reserved52: [4]u8,
-        ///  Memory management fault address register
-        MMFAR: mmio.Mmio(packed struct(u32) {
-            ///  Memory management fault address
-            MMFAR: u32,
-        }),
-        ///  Bus fault address register
-        BFAR: mmio.Mmio(packed struct(u32) {
-            ///  Bus fault address
-            BFAR: u32,
-        }),
-    };
-
-    ///  Nested vectored interrupt controller
-    pub const NVIC_STIR = extern struct {
-        ///  Software trigger interrupt register
-        STIR: mmio.Mmio(packed struct(u32) {
-            ///  Software generated interrupt ID
-            INTID: u9,
-            padding: u23,
-        }),
-    };
-
-    ///  System control block ACTLR
-    pub const SCB_ACTRL = extern struct {
-        ///  Auxiliary control register
-        ACTRL: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  DISFOLD
-            DISFOLD: u1,
-            reserved10: u7,
-            ///  FPEXCODIS
-            FPEXCODIS: u1,
-            ///  DISRAMODE
-            DISRAMODE: u1,
-            ///  DISITMATBFLUSH
-            DISITMATBFLUSH: u1,
-            padding: u19,
-        }),
-    };
-
-    ///  Memory protection unit
-    pub const MPU = extern struct {
-        ///  MPU type register
-        MPU_TYPER: mmio.Mmio(packed struct(u32) {
-            ///  Separate flag
-            SEPARATE: u1,
-            reserved8: u7,
-            ///  Number of MPU data regions
-            DREGION: u8,
-            ///  Number of MPU instruction regions
-            IREGION: u8,
-            padding: u8,
-        }),
-        ///  MPU control register
-        MPU_CTRL: mmio.Mmio(packed struct(u32) {
-            ///  Enables the MPU
-            ENABLE: u1,
-            ///  Enables the operation of MPU during hard fault
-            HFNMIENA: u1,
-            ///  Enable priviliged software access to default memory map
-            PRIVDEFENA: u1,
-            padding: u29,
-        }),
-        ///  MPU region number register
-        MPU_RNR: mmio.Mmio(packed struct(u32) {
-            ///  MPU region
-            REGION: u8,
-            padding: u24,
-        }),
-        ///  MPU region base address register
-        MPU_RBAR: mmio.Mmio(packed struct(u32) {
-            ///  MPU region field
-            REGION: u4,
-            ///  MPU region number valid
-            VALID: u1,
-            ///  Region base address field
-            ADDR: u27,
-        }),
-        ///  MPU region attribute and size register
-        MPU_RASR: mmio.Mmio(packed struct(u32) {
-            ///  Region enable bit.
-            ENABLE: u1,
-            ///  Size of the MPU protection region
-            SIZE: u5,
-            reserved8: u2,
-            ///  Subregion disable bits
-            SRD: u8,
-            ///  memory attribute
-            B: u1,
-            ///  memory attribute
-            C: u1,
-            ///  Shareable memory attribute
-            S: u1,
-            ///  memory attribute
-            TEX: u3,
-            reserved24: u2,
-            ///  Access permission
-            AP: u3,
-            reserved28: u1,
-            ///  Instruction access disable bit
-            XN: u1,
-            padding: u3,
-        }),
-    };
-
-    ///  Nested Vectored Interrupt Controller
-    pub const NVIC = extern struct {
-        ///  Interrupt Set-Enable Register
-        ISER0: mmio.Mmio(packed struct(u32) {
-            ///  SETENA
-            SETENA: u32,
-        }),
-        ///  Interrupt Set-Enable Register
-        ISER1: mmio.Mmio(packed struct(u32) {
-            ///  SETENA
-            SETENA: u32,
-        }),
-        reserved128: [120]u8,
-        ///  Interrupt Clear-Enable Register
-        ICER0: mmio.Mmio(packed struct(u32) {
-            ///  CLRENA
-            CLRENA: u32,
-        }),
-        ///  Interrupt Clear-Enable Register
-        ICER1: mmio.Mmio(packed struct(u32) {
-            ///  CLRENA
-            CLRENA: u32,
-        }),
-        reserved256: [120]u8,
-        ///  Interrupt Set-Pending Register
-        ISPR0: mmio.Mmio(packed struct(u32) {
-            ///  SETPEND
-            SETPEND: u32,
-        }),
-        ///  Interrupt Set-Pending Register
-        ISPR1: mmio.Mmio(packed struct(u32) {
-            ///  SETPEND
-            SETPEND: u32,
-        }),
-        reserved384: [120]u8,
-        ///  Interrupt Clear-Pending Register
-        ICPR0: mmio.Mmio(packed struct(u32) {
-            ///  CLRPEND
-            CLRPEND: u32,
-        }),
-        ///  Interrupt Clear-Pending Register
-        ICPR1: mmio.Mmio(packed struct(u32) {
-            ///  CLRPEND
-            CLRPEND: u32,
-        }),
-        reserved512: [120]u8,
-        ///  Interrupt Active Bit Register
-        IABR0: mmio.Mmio(packed struct(u32) {
-            ///  ACTIVE
-            ACTIVE: u32,
-        }),
-        ///  Interrupt Active Bit Register
-        IABR1: mmio.Mmio(packed struct(u32) {
-            ///  ACTIVE
-            ACTIVE: u32,
-        }),
-        reserved768: [248]u8,
-        ///  Interrupt Priority Register
-        IPR0: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR1: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR2: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR3: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR4: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR5: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR6: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR7: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR8: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR9: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR10: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR11: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR12: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR13: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR14: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-    };
-
-    ///  Alternate function I/O
-    pub const AFIO = extern struct {
-        ///  Event Control Register (AFIO_EVCR)
-        EVCR: mmio.Mmio(packed struct(u32) {
-            ///  Pin selection
-            PIN: u4,
-            ///  Port selection
-            PORT: u3,
-            ///  Event Output Enable
-            EVOE: u1,
-            padding: u24,
-        }),
-        ///  AF remap and debug I/O configuration register (AFIO_MAPR)
-        MAPR: mmio.Mmio(packed struct(u32) {
-            ///  SPI1 remapping
-            SPI1_REMAP: u1,
-            ///  I2C1 remapping
-            I2C1_REMAP: u1,
-            ///  USART1 remapping
-            USART1_REMAP: u1,
-            ///  USART2 remapping
-            USART2_REMAP: u1,
-            ///  USART3 remapping
-            USART3_REMAP: u2,
-            ///  TIM1 remapping
-            TIM1_REMAP: u2,
-            ///  TIM2 remapping
-            TIM2_REMAP: u2,
-            ///  TIM3 remapping
-            TIM3_REMAP: u2,
-            ///  TIM4 remapping
-            TIM4_REMAP: u1,
-            ///  CAN1 remapping
-            CAN_REMAP: u2,
-            ///  Port D0/Port D1 mapping on OSCIN/OSCOUT
-            PD01_REMAP: u1,
-            ///  Set and cleared by software
-            TIM5CH4_IREMAP: u1,
-            ///  ADC 1 External trigger injected conversion remapping
-            ADC1_ETRGINJ_REMAP: u1,
-            ///  ADC 1 external trigger regular conversion remapping
-            ADC1_ETRGREG_REMAP: u1,
-            ///  ADC 2 external trigger injected conversion remapping
-            ADC2_ETRGINJ_REMAP: u1,
-            ///  ADC 2 external trigger regular conversion remapping
-            ADC2_ETRGREG_REMAP: u1,
-            reserved24: u3,
-            ///  Serial wire JTAG configuration
-            SWJ_CFG: u3,
-            padding: u5,
-        }),
-        ///  External interrupt configuration register 1 (AFIO_EXTICR1)
-        EXTICR1: mmio.Mmio(packed struct(u32) {
-            ///  EXTI0 configuration
-            EXTI0: u4,
-            ///  EXTI1 configuration
-            EXTI1: u4,
-            ///  EXTI2 configuration
-            EXTI2: u4,
-            ///  EXTI3 configuration
-            EXTI3: u4,
-            padding: u16,
-        }),
-        ///  External interrupt configuration register 2 (AFIO_EXTICR2)
-        EXTICR2: mmio.Mmio(packed struct(u32) {
-            ///  EXTI4 configuration
-            EXTI4: u4,
-            ///  EXTI5 configuration
-            EXTI5: u4,
-            ///  EXTI6 configuration
-            EXTI6: u4,
-            ///  EXTI7 configuration
-            EXTI7: u4,
-            padding: u16,
-        }),
-        ///  External interrupt configuration register 3 (AFIO_EXTICR3)
-        EXTICR3: mmio.Mmio(packed struct(u32) {
-            ///  EXTI8 configuration
-            EXTI8: u4,
-            ///  EXTI9 configuration
-            EXTI9: u4,
-            ///  EXTI10 configuration
-            EXTI10: u4,
-            ///  EXTI11 configuration
-            EXTI11: u4,
-            padding: u16,
-        }),
-        ///  External interrupt configuration register 4 (AFIO_EXTICR4)
-        EXTICR4: mmio.Mmio(packed struct(u32) {
-            ///  EXTI12 configuration
-            EXTI12: u4,
-            ///  EXTI13 configuration
-            EXTI13: u4,
-            ///  EXTI14 configuration
-            EXTI14: u4,
-            ///  EXTI15 configuration
-            EXTI15: u4,
-            padding: u16,
-        }),
-        reserved28: [4]u8,
-        ///  AF remap and debug I/O configuration register
-        MAPR2: mmio.Mmio(packed struct(u32) {
-            reserved5: u5,
-            ///  TIM9 remapping
-            TIM9_REMAP: u1,
-            ///  TIM10 remapping
-            TIM10_REMAP: u1,
-            ///  TIM11 remapping
-            TIM11_REMAP: u1,
-            ///  TIM13 remapping
-            TIM13_REMAP: u1,
-            ///  TIM14 remapping
-            TIM14_REMAP: u1,
-            ///  NADV connect/disconnect
-            FSMC_NADV: u1,
-            padding: u21,
-        }),
-    };
-
-    ///  EXTI
-    pub const EXTI = extern struct {
-        ///  Interrupt mask register (EXTI_IMR)
-        IMR: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt Mask on line 0
-            MR0: u1,
-            ///  Interrupt Mask on line 1
-            MR1: u1,
-            ///  Interrupt Mask on line 2
-            MR2: u1,
-            ///  Interrupt Mask on line 3
-            MR3: u1,
-            ///  Interrupt Mask on line 4
-            MR4: u1,
-            ///  Interrupt Mask on line 5
-            MR5: u1,
-            ///  Interrupt Mask on line 6
-            MR6: u1,
-            ///  Interrupt Mask on line 7
-            MR7: u1,
-            ///  Interrupt Mask on line 8
-            MR8: u1,
-            ///  Interrupt Mask on line 9
-            MR9: u1,
-            ///  Interrupt Mask on line 10
-            MR10: u1,
-            ///  Interrupt Mask on line 11
-            MR11: u1,
-            ///  Interrupt Mask on line 12
-            MR12: u1,
-            ///  Interrupt Mask on line 13
-            MR13: u1,
-            ///  Interrupt Mask on line 14
-            MR14: u1,
-            ///  Interrupt Mask on line 15
-            MR15: u1,
-            ///  Interrupt Mask on line 16
-            MR16: u1,
-            ///  Interrupt Mask on line 17
-            MR17: u1,
-            ///  Interrupt Mask on line 18
-            MR18: u1,
-            padding: u13,
-        }),
-        ///  Event mask register (EXTI_EMR)
-        EMR: mmio.Mmio(packed struct(u32) {
-            ///  Event Mask on line 0
-            MR0: u1,
-            ///  Event Mask on line 1
-            MR1: u1,
-            ///  Event Mask on line 2
-            MR2: u1,
-            ///  Event Mask on line 3
-            MR3: u1,
-            ///  Event Mask on line 4
-            MR4: u1,
-            ///  Event Mask on line 5
-            MR5: u1,
-            ///  Event Mask on line 6
-            MR6: u1,
-            ///  Event Mask on line 7
-            MR7: u1,
-            ///  Event Mask on line 8
-            MR8: u1,
-            ///  Event Mask on line 9
-            MR9: u1,
-            ///  Event Mask on line 10
-            MR10: u1,
-            ///  Event Mask on line 11
-            MR11: u1,
-            ///  Event Mask on line 12
-            MR12: u1,
-            ///  Event Mask on line 13
-            MR13: u1,
-            ///  Event Mask on line 14
-            MR14: u1,
-            ///  Event Mask on line 15
-            MR15: u1,
-            ///  Event Mask on line 16
-            MR16: u1,
-            ///  Event Mask on line 17
-            MR17: u1,
-            ///  Event Mask on line 18
-            MR18: u1,
-            padding: u13,
-        }),
-        ///  Rising Trigger selection register (EXTI_RTSR)
-        RTSR: mmio.Mmio(packed struct(u32) {
-            ///  Rising trigger event configuration of line 0
-            TR0: u1,
-            ///  Rising trigger event configuration of line 1
-            TR1: u1,
-            ///  Rising trigger event configuration of line 2
-            TR2: u1,
-            ///  Rising trigger event configuration of line 3
-            TR3: u1,
-            ///  Rising trigger event configuration of line 4
-            TR4: u1,
-            ///  Rising trigger event configuration of line 5
-            TR5: u1,
-            ///  Rising trigger event configuration of line 6
-            TR6: u1,
-            ///  Rising trigger event configuration of line 7
-            TR7: u1,
-            ///  Rising trigger event configuration of line 8
-            TR8: u1,
-            ///  Rising trigger event configuration of line 9
-            TR9: u1,
-            ///  Rising trigger event configuration of line 10
-            TR10: u1,
-            ///  Rising trigger event configuration of line 11
-            TR11: u1,
-            ///  Rising trigger event configuration of line 12
-            TR12: u1,
-            ///  Rising trigger event configuration of line 13
-            TR13: u1,
-            ///  Rising trigger event configuration of line 14
-            TR14: u1,
-            ///  Rising trigger event configuration of line 15
-            TR15: u1,
-            ///  Rising trigger event configuration of line 16
-            TR16: u1,
-            ///  Rising trigger event configuration of line 17
-            TR17: u1,
-            ///  Rising trigger event configuration of line 18
-            TR18: u1,
-            padding: u13,
-        }),
-        ///  Falling Trigger selection register (EXTI_FTSR)
-        FTSR: mmio.Mmio(packed struct(u32) {
-            ///  Falling trigger event configuration of line 0
-            TR0: u1,
-            ///  Falling trigger event configuration of line 1
-            TR1: u1,
-            ///  Falling trigger event configuration of line 2
-            TR2: u1,
-            ///  Falling trigger event configuration of line 3
-            TR3: u1,
-            ///  Falling trigger event configuration of line 4
-            TR4: u1,
-            ///  Falling trigger event configuration of line 5
-            TR5: u1,
-            ///  Falling trigger event configuration of line 6
-            TR6: u1,
-            ///  Falling trigger event configuration of line 7
-            TR7: u1,
-            ///  Falling trigger event configuration of line 8
-            TR8: u1,
-            ///  Falling trigger event configuration of line 9
-            TR9: u1,
-            ///  Falling trigger event configuration of line 10
-            TR10: u1,
-            ///  Falling trigger event configuration of line 11
-            TR11: u1,
-            ///  Falling trigger event configuration of line 12
-            TR12: u1,
-            ///  Falling trigger event configuration of line 13
-            TR13: u1,
-            ///  Falling trigger event configuration of line 14
-            TR14: u1,
-            ///  Falling trigger event configuration of line 15
-            TR15: u1,
-            ///  Falling trigger event configuration of line 16
-            TR16: u1,
-            ///  Falling trigger event configuration of line 17
-            TR17: u1,
-            ///  Falling trigger event configuration of line 18
-            TR18: u1,
-            padding: u13,
-        }),
-        ///  Software interrupt event register (EXTI_SWIER)
-        SWIER: mmio.Mmio(packed struct(u32) {
-            ///  Software Interrupt on line 0
-            SWIER0: u1,
-            ///  Software Interrupt on line 1
-            SWIER1: u1,
-            ///  Software Interrupt on line 2
-            SWIER2: u1,
-            ///  Software Interrupt on line 3
-            SWIER3: u1,
-            ///  Software Interrupt on line 4
-            SWIER4: u1,
-            ///  Software Interrupt on line 5
-            SWIER5: u1,
-            ///  Software Interrupt on line 6
-            SWIER6: u1,
-            ///  Software Interrupt on line 7
-            SWIER7: u1,
-            ///  Software Interrupt on line 8
-            SWIER8: u1,
-            ///  Software Interrupt on line 9
-            SWIER9: u1,
-            ///  Software Interrupt on line 10
-            SWIER10: u1,
-            ///  Software Interrupt on line 11
-            SWIER11: u1,
-            ///  Software Interrupt on line 12
-            SWIER12: u1,
-            ///  Software Interrupt on line 13
-            SWIER13: u1,
-            ///  Software Interrupt on line 14
-            SWIER14: u1,
-            ///  Software Interrupt on line 15
-            SWIER15: u1,
-            ///  Software Interrupt on line 16
-            SWIER16: u1,
-            ///  Software Interrupt on line 17
-            SWIER17: u1,
-            ///  Software Interrupt on line 18
-            SWIER18: u1,
-            padding: u13,
-        }),
-        ///  Pending register (EXTI_PR)
-        PR: mmio.Mmio(packed struct(u32) {
-            ///  Pending bit 0
-            PR0: u1,
-            ///  Pending bit 1
-            PR1: u1,
-            ///  Pending bit 2
-            PR2: u1,
-            ///  Pending bit 3
-            PR3: u1,
-            ///  Pending bit 4
-            PR4: u1,
-            ///  Pending bit 5
-            PR5: u1,
-            ///  Pending bit 6
-            PR6: u1,
-            ///  Pending bit 7
-            PR7: u1,
-            ///  Pending bit 8
-            PR8: u1,
-            ///  Pending bit 9
-            PR9: u1,
-            ///  Pending bit 10
-            PR10: u1,
-            ///  Pending bit 11
-            PR11: u1,
-            ///  Pending bit 12
-            PR12: u1,
-            ///  Pending bit 13
-            PR13: u1,
-            ///  Pending bit 14
-            PR14: u1,
-            ///  Pending bit 15
-            PR15: u1,
-            ///  Pending bit 16
-            PR16: u1,
-            ///  Pending bit 17
-            PR17: u1,
-            ///  Pending bit 18
-            PR18: u1,
-            padding: u13,
-        }),
-    };
-
-    ///  DMA controller
-    pub const DMA1 = extern struct {
-        ///  DMA interrupt status register (DMA_ISR)
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  Channel 1 Global interrupt flag
-            GIF1: u1,
-            ///  Channel 1 Transfer Complete flag
-            TCIF1: u1,
-            ///  Channel 1 Half Transfer Complete flag
-            HTIF1: u1,
-            ///  Channel 1 Transfer Error flag
-            TEIF1: u1,
-            ///  Channel 2 Global interrupt flag
-            GIF2: u1,
-            ///  Channel 2 Transfer Complete flag
-            TCIF2: u1,
-            ///  Channel 2 Half Transfer Complete flag
-            HTIF2: u1,
-            ///  Channel 2 Transfer Error flag
-            TEIF2: u1,
-            ///  Channel 3 Global interrupt flag
-            GIF3: u1,
-            ///  Channel 3 Transfer Complete flag
-            TCIF3: u1,
-            ///  Channel 3 Half Transfer Complete flag
-            HTIF3: u1,
-            ///  Channel 3 Transfer Error flag
-            TEIF3: u1,
-            ///  Channel 4 Global interrupt flag
-            GIF4: u1,
-            ///  Channel 4 Transfer Complete flag
-            TCIF4: u1,
-            ///  Channel 4 Half Transfer Complete flag
-            HTIF4: u1,
-            ///  Channel 4 Transfer Error flag
-            TEIF4: u1,
-            ///  Channel 5 Global interrupt flag
-            GIF5: u1,
-            ///  Channel 5 Transfer Complete flag
-            TCIF5: u1,
-            ///  Channel 5 Half Transfer Complete flag
-            HTIF5: u1,
-            ///  Channel 5 Transfer Error flag
-            TEIF5: u1,
-            ///  Channel 6 Global interrupt flag
-            GIF6: u1,
-            ///  Channel 6 Transfer Complete flag
-            TCIF6: u1,
-            ///  Channel 6 Half Transfer Complete flag
-            HTIF6: u1,
-            ///  Channel 6 Transfer Error flag
-            TEIF6: u1,
-            ///  Channel 7 Global interrupt flag
-            GIF7: u1,
-            ///  Channel 7 Transfer Complete flag
-            TCIF7: u1,
-            ///  Channel 7 Half Transfer Complete flag
-            HTIF7: u1,
-            ///  Channel 7 Transfer Error flag
-            TEIF7: u1,
-            padding: u4,
-        }),
-        ///  DMA interrupt flag clear register (DMA_IFCR)
-        IFCR: mmio.Mmio(packed struct(u32) {
-            ///  Channel 1 Global interrupt clear
-            CGIF1: u1,
-            ///  Channel 1 Transfer Complete clear
-            CTCIF1: u1,
-            ///  Channel 1 Half Transfer clear
-            CHTIF1: u1,
-            ///  Channel 1 Transfer Error clear
-            CTEIF1: u1,
-            ///  Channel 2 Global interrupt clear
-            CGIF2: u1,
-            ///  Channel 2 Transfer Complete clear
-            CTCIF2: u1,
-            ///  Channel 2 Half Transfer clear
-            CHTIF2: u1,
-            ///  Channel 2 Transfer Error clear
-            CTEIF2: u1,
-            ///  Channel 3 Global interrupt clear
-            CGIF3: u1,
-            ///  Channel 3 Transfer Complete clear
-            CTCIF3: u1,
-            ///  Channel 3 Half Transfer clear
-            CHTIF3: u1,
-            ///  Channel 3 Transfer Error clear
-            CTEIF3: u1,
-            ///  Channel 4 Global interrupt clear
-            CGIF4: u1,
-            ///  Channel 4 Transfer Complete clear
-            CTCIF4: u1,
-            ///  Channel 4 Half Transfer clear
-            CHTIF4: u1,
-            ///  Channel 4 Transfer Error clear
-            CTEIF4: u1,
-            ///  Channel 5 Global interrupt clear
-            CGIF5: u1,
-            ///  Channel 5 Transfer Complete clear
-            CTCIF5: u1,
-            ///  Channel 5 Half Transfer clear
-            CHTIF5: u1,
-            ///  Channel 5 Transfer Error clear
-            CTEIF5: u1,
-            ///  Channel 6 Global interrupt clear
-            CGIF6: u1,
-            ///  Channel 6 Transfer Complete clear
-            CTCIF6: u1,
-            ///  Channel 6 Half Transfer clear
-            CHTIF6: u1,
-            ///  Channel 6 Transfer Error clear
-            CTEIF6: u1,
-            ///  Channel 7 Global interrupt clear
-            CGIF7: u1,
-            ///  Channel 7 Transfer Complete clear
-            CTCIF7: u1,
-            ///  Channel 7 Half Transfer clear
-            CHTIF7: u1,
-            ///  Channel 7 Transfer Error clear
-            CTEIF7: u1,
-            padding: u4,
-        }),
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 1 number of data register
-        CNDTR1: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 1 peripheral address register
-        CPAR1: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 1 memory address register
-        CMAR1: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved28: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 2 number of data register
-        CNDTR2: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 2 peripheral address register
-        CPAR2: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 2 memory address register
-        CMAR2: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved48: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 3 number of data register
-        CNDTR3: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 3 peripheral address register
-        CPAR3: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 3 memory address register
-        CMAR3: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved68: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 4 number of data register
-        CNDTR4: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 4 peripheral address register
-        CPAR4: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 4 memory address register
-        CMAR4: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved88: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR5: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 5 number of data register
-        CNDTR5: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 5 peripheral address register
-        CPAR5: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 5 memory address register
-        CMAR5: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved108: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR6: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 6 number of data register
-        CNDTR6: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 6 peripheral address register
-        CPAR6: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 6 memory address register
-        CMAR6: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved128: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR7: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 7 number of data register
-        CNDTR7: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 7 peripheral address register
-        CPAR7: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 7 memory address register
-        CMAR7: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-    };
-
-    ///  Ethernet: DMA controller operation
-    pub const ETHERNET_DMA = extern struct {
-        ///  Ethernet DMA bus mode register
-        DMABMR: mmio.Mmio(packed struct(u32) {
-            ///  Software reset
-            SR: u1,
-            ///  DMA Arbitration
-            DA: u1,
-            ///  Descriptor skip length
-            DSL: u5,
-            reserved8: u1,
-            ///  Programmable burst length
-            PBL: u6,
-            ///  Rx Tx priority ratio
-            RTPR: u2,
-            ///  Fixed burst
-            FB: u1,
-            ///  Rx DMA PBL
-            RDP: u6,
-            ///  Use separate PBL
-            USP: u1,
-            ///  4xPBL mode
-            FPM: u1,
-            ///  Address-aligned beats
-            AAB: u1,
-            padding: u6,
-        }),
-        ///  Ethernet DMA transmit poll demand register
-        DMATPDR: mmio.Mmio(packed struct(u32) {
-            ///  Transmit poll demand
-            TPD: u32,
-        }),
-        ///  EHERNET DMA receive poll demand register
-        DMARPDR: mmio.Mmio(packed struct(u32) {
-            ///  Receive poll demand
-            RPD: u32,
-        }),
-        ///  Ethernet DMA receive descriptor list address register
-        DMARDLAR: mmio.Mmio(packed struct(u32) {
-            ///  Start of receive list
-            SRL: u32,
-        }),
-        ///  Ethernet DMA transmit descriptor list address register
-        DMATDLAR: mmio.Mmio(packed struct(u32) {
-            ///  Start of transmit list
-            STL: u32,
-        }),
-        ///  Ethernet DMA status register
-        DMASR: mmio.Mmio(packed struct(u32) {
-            ///  Transmit status
-            TS: u1,
-            ///  Transmit process stopped status
-            TPSS: u1,
-            ///  Transmit buffer unavailable status
-            TBUS: u1,
-            ///  Transmit jabber timeout status
-            TJTS: u1,
-            ///  Receive overflow status
-            ROS: u1,
-            ///  Transmit underflow status
-            TUS: u1,
-            ///  Receive status
-            RS: u1,
-            ///  Receive buffer unavailable status
-            RBUS: u1,
-            ///  Receive process stopped status
-            RPSS: u1,
-            ///  Receive watchdog timeout status
-            PWTS: u1,
-            ///  Early transmit status
-            ETS: u1,
-            reserved13: u2,
-            ///  Fatal bus error status
-            FBES: u1,
-            ///  Early receive status
-            ERS: u1,
-            ///  Abnormal interrupt summary
-            AIS: u1,
-            ///  Normal interrupt summary
-            NIS: u1,
-            ///  Receive process state
-            RPS: u3,
-            ///  Transmit process state
-            TPS: u3,
-            ///  Error bits status
-            EBS: u3,
-            reserved27: u1,
-            ///  MMC status
-            MMCS: u1,
-            ///  PMT status
-            PMTS: u1,
-            ///  Time stamp trigger status
-            TSTS: u1,
-            padding: u2,
-        }),
-        ///  Ethernet DMA operation mode register
-        DMAOMR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  SR
-            SR: u1,
-            ///  OSF
-            OSF: u1,
-            ///  RTC
-            RTC: u2,
-            reserved6: u1,
-            ///  FUGF
-            FUGF: u1,
-            ///  FEF
-            FEF: u1,
-            reserved13: u5,
-            ///  ST
-            ST: u1,
-            ///  TTC
-            TTC: u3,
-            reserved20: u3,
-            ///  FTF
-            FTF: u1,
-            ///  TSF
-            TSF: u1,
-            reserved24: u2,
-            ///  DFRF
-            DFRF: u1,
-            ///  RSF
-            RSF: u1,
-            ///  DTCEFD
-            DTCEFD: u1,
-            padding: u5,
-        }),
-        ///  Ethernet DMA interrupt enable register
-        DMAIER: mmio.Mmio(packed struct(u32) {
-            ///  Transmit interrupt enable
-            TIE: u1,
-            ///  Transmit process stopped interrupt enable
-            TPSIE: u1,
-            ///  Transmit buffer unavailable interrupt enable
-            TBUIE: u1,
-            ///  Transmit jabber timeout interrupt enable
-            TJTIE: u1,
-            ///  Overflow interrupt enable
-            ROIE: u1,
-            ///  Underflow interrupt enable
-            TUIE: u1,
-            ///  Receive interrupt enable
-            RIE: u1,
-            ///  Receive buffer unavailable interrupt enable
-            RBUIE: u1,
-            ///  Receive process stopped interrupt enable
-            RPSIE: u1,
-            ///  receive watchdog timeout interrupt enable
-            RWTIE: u1,
-            ///  Early transmit interrupt enable
-            ETIE: u1,
-            reserved13: u2,
-            ///  Fatal bus error interrupt enable
-            FBEIE: u1,
-            ///  Early receive interrupt enable
-            ERIE: u1,
-            ///  Abnormal interrupt summary enable
-            AISE: u1,
-            ///  Normal interrupt summary enable
-            NISE: u1,
-            padding: u15,
-        }),
-        ///  Ethernet DMA missed frame and buffer overflow counter register
-        DMAMFBOCR: mmio.Mmio(packed struct(u32) {
-            ///  Missed frames by the controller
-            MFC: u16,
-            ///  Overflow bit for missed frame counter
-            OMFC: u1,
-            ///  Missed frames by the application
-            MFA: u11,
-            ///  Overflow bit for FIFO overflow counter
-            OFOC: u1,
-            padding: u3,
-        }),
-        reserved72: [36]u8,
-        ///  Ethernet DMA current host transmit descriptor register
-        DMACHTDR: mmio.Mmio(packed struct(u32) {
-            ///  Host transmit descriptor address pointer
-            HTDAP: u32,
-        }),
-        ///  Ethernet DMA current host receive descriptor register
-        DMACHRDR: mmio.Mmio(packed struct(u32) {
-            ///  Host receive descriptor address pointer
-            HRDAP: u32,
-        }),
-        ///  Ethernet DMA current host transmit buffer address register
-        DMACHTBAR: mmio.Mmio(packed struct(u32) {
-            ///  Host transmit buffer address pointer
-            HTBAP: u32,
-        }),
-        ///  Ethernet DMA current host receive buffer address register
-        DMACHRBAR: mmio.Mmio(packed struct(u32) {
-            ///  Host receive buffer address pointer
-            HRBAP: u32,
-        }),
-    };
-
-    ///  Secure digital input/output interface
-    pub const SDIO = extern struct {
-        ///  Bits 1:0 = PWRCTRL: Power supply control bits
-        POWER: mmio.Mmio(packed struct(u32) {
-            ///  PWRCTRL
-            PWRCTRL: u2,
-            padding: u30,
-        }),
-        ///  SDI clock control register (SDIO_CLKCR)
-        CLKCR: mmio.Mmio(packed struct(u32) {
-            ///  Clock divide factor
-            CLKDIV: u8,
-            ///  Clock enable bit
-            CLKEN: u1,
-            ///  Power saving configuration bit
-            PWRSAV: u1,
-            ///  Clock divider bypass enable bit
-            BYPASS: u1,
-            ///  Wide bus mode enable bit
-            WIDBUS: u2,
-            ///  SDIO_CK dephasing selection bit
-            NEGEDGE: u1,
-            ///  HW Flow Control enable
-            HWFC_EN: u1,
-            padding: u17,
-        }),
-        ///  Bits 31:0 = : Command argument
-        ARG: mmio.Mmio(packed struct(u32) {
-            ///  Command argument
-            CMDARG: u32,
-        }),
-        ///  SDIO command register (SDIO_CMD)
-        CMD: mmio.Mmio(packed struct(u32) {
-            ///  CMDINDEX
-            CMDINDEX: u6,
-            ///  WAITRESP
-            WAITRESP: u2,
-            ///  WAITINT
-            WAITINT: u1,
-            ///  WAITPEND
-            WAITPEND: u1,
-            ///  CPSMEN
-            CPSMEN: u1,
-            ///  SDIOSuspend
-            SDIOSuspend: u1,
-            ///  ENCMDcompl
-            ENCMDcompl: u1,
-            ///  nIEN
-            nIEN: u1,
-            ///  CE_ATACMD
-            CE_ATACMD: u1,
-            padding: u17,
-        }),
-        ///  SDIO command register
-        RESPCMD: mmio.Mmio(packed struct(u32) {
-            ///  RESPCMD
-            RESPCMD: u6,
-            padding: u26,
-        }),
-        ///  Bits 31:0 = CARDSTATUS1
-        RESPI1: mmio.Mmio(packed struct(u32) {
-            ///  CARDSTATUS1
-            CARDSTATUS1: u32,
-        }),
-        ///  Bits 31:0 = CARDSTATUS2
-        RESP2: mmio.Mmio(packed struct(u32) {
-            ///  CARDSTATUS2
-            CARDSTATUS2: u32,
-        }),
-        ///  Bits 31:0 = CARDSTATUS3
-        RESP3: mmio.Mmio(packed struct(u32) {
-            ///  CARDSTATUS3
-            CARDSTATUS3: u32,
-        }),
-        ///  Bits 31:0 = CARDSTATUS4
-        RESP4: mmio.Mmio(packed struct(u32) {
-            ///  CARDSTATUS4
-            CARDSTATUS4: u32,
-        }),
-        ///  Bits 31:0 = DATATIME: Data timeout period
-        DTIMER: mmio.Mmio(packed struct(u32) {
-            ///  Data timeout period
-            DATATIME: u32,
-        }),
-        ///  Bits 24:0 = DATALENGTH: Data length value
-        DLEN: mmio.Mmio(packed struct(u32) {
-            ///  Data length value
-            DATALENGTH: u25,
-            padding: u7,
-        }),
-        ///  SDIO data control register (SDIO_DCTRL)
-        DCTRL: mmio.Mmio(packed struct(u32) {
-            ///  DTEN
-            DTEN: u1,
-            ///  DTDIR
-            DTDIR: u1,
-            ///  DTMODE
-            DTMODE: u1,
-            ///  DMAEN
-            DMAEN: u1,
-            ///  DBLOCKSIZE
-            DBLOCKSIZE: u4,
-            ///  PWSTART
-            PWSTART: u1,
-            ///  PWSTOP
-            PWSTOP: u1,
-            ///  RWMOD
-            RWMOD: u1,
-            ///  SDIOEN
-            SDIOEN: u1,
-            padding: u20,
-        }),
-        ///  Bits 24:0 = DATACOUNT: Data count value
-        DCOUNT: mmio.Mmio(packed struct(u32) {
-            ///  Data count value
-            DATACOUNT: u25,
-            padding: u7,
-        }),
-        ///  SDIO status register (SDIO_STA)
-        STA: mmio.Mmio(packed struct(u32) {
-            ///  CCRCFAIL
-            CCRCFAIL: u1,
-            ///  DCRCFAIL
-            DCRCFAIL: u1,
-            ///  CTIMEOUT
-            CTIMEOUT: u1,
-            ///  DTIMEOUT
-            DTIMEOUT: u1,
-            ///  TXUNDERR
-            TXUNDERR: u1,
-            ///  RXOVERR
-            RXOVERR: u1,
-            ///  CMDREND
-            CMDREND: u1,
-            ///  CMDSENT
-            CMDSENT: u1,
-            ///  DATAEND
-            DATAEND: u1,
-            ///  STBITERR
-            STBITERR: u1,
-            ///  DBCKEND
-            DBCKEND: u1,
-            ///  CMDACT
-            CMDACT: u1,
-            ///  TXACT
-            TXACT: u1,
-            ///  RXACT
-            RXACT: u1,
-            ///  TXFIFOHE
-            TXFIFOHE: u1,
-            ///  RXFIFOHF
-            RXFIFOHF: u1,
-            ///  TXFIFOF
-            TXFIFOF: u1,
-            ///  RXFIFOF
-            RXFIFOF: u1,
-            ///  TXFIFOE
-            TXFIFOE: u1,
-            ///  RXFIFOE
-            RXFIFOE: u1,
-            ///  TXDAVL
-            TXDAVL: u1,
-            ///  RXDAVL
-            RXDAVL: u1,
-            ///  SDIOIT
-            SDIOIT: u1,
-            ///  CEATAEND
-            CEATAEND: u1,
-            padding: u8,
-        }),
-        ///  SDIO interrupt clear register (SDIO_ICR)
-        ICR: mmio.Mmio(packed struct(u32) {
-            ///  CCRCFAILC
-            CCRCFAILC: u1,
-            ///  DCRCFAILC
-            DCRCFAILC: u1,
-            ///  CTIMEOUTC
-            CTIMEOUTC: u1,
-            ///  DTIMEOUTC
-            DTIMEOUTC: u1,
-            ///  TXUNDERRC
-            TXUNDERRC: u1,
-            ///  RXOVERRC
-            RXOVERRC: u1,
-            ///  CMDRENDC
-            CMDRENDC: u1,
-            ///  CMDSENTC
-            CMDSENTC: u1,
-            ///  DATAENDC
-            DATAENDC: u1,
-            ///  STBITERRC
-            STBITERRC: u1,
-            ///  DBCKENDC
-            DBCKENDC: u1,
-            reserved22: u11,
-            ///  SDIOITC
-            SDIOITC: u1,
-            ///  CEATAENDC
-            CEATAENDC: u1,
-            padding: u8,
-        }),
-        ///  SDIO mask register (SDIO_MASK)
-        MASK: mmio.Mmio(packed struct(u32) {
-            ///  CCRCFAILIE
-            CCRCFAILIE: u1,
-            ///  DCRCFAILIE
-            DCRCFAILIE: u1,
-            ///  CTIMEOUTIE
-            CTIMEOUTIE: u1,
-            ///  DTIMEOUTIE
-            DTIMEOUTIE: u1,
-            ///  TXUNDERRIE
-            TXUNDERRIE: u1,
-            ///  RXOVERRIE
-            RXOVERRIE: u1,
-            ///  CMDRENDIE
-            CMDRENDIE: u1,
-            ///  CMDSENTIE
-            CMDSENTIE: u1,
-            ///  DATAENDIE
-            DATAENDIE: u1,
-            ///  STBITERRIE
-            STBITERRIE: u1,
-            ///  DBACKENDIE
-            DBACKENDIE: u1,
-            ///  CMDACTIE
-            CMDACTIE: u1,
-            ///  TXACTIE
-            TXACTIE: u1,
-            ///  RXACTIE
-            RXACTIE: u1,
-            ///  TXFIFOHEIE
-            TXFIFOHEIE: u1,
-            ///  RXFIFOHFIE
-            RXFIFOHFIE: u1,
-            ///  TXFIFOFIE
-            TXFIFOFIE: u1,
-            ///  RXFIFOFIE
-            RXFIFOFIE: u1,
-            ///  TXFIFOEIE
-            TXFIFOEIE: u1,
-            ///  RXFIFOEIE
-            RXFIFOEIE: u1,
-            ///  TXDAVLIE
-            TXDAVLIE: u1,
-            ///  RXDAVLIE
-            RXDAVLIE: u1,
-            ///  SDIOITIE
-            SDIOITIE: u1,
-            ///  CEATENDIE
-            CEATENDIE: u1,
-            padding: u8,
-        }),
-        reserved72: [8]u8,
-        ///  Bits 23:0 = FIFOCOUNT: Remaining number of words to be written to or read from the FIFO
-        FIFOCNT: mmio.Mmio(packed struct(u32) {
-            ///  FIF0COUNT
-            FIF0COUNT: u24,
-            padding: u8,
-        }),
-        reserved128: [52]u8,
-        ///  bits 31:0 = FIFOData: Receive and transmit FIFO data
-        FIFO: mmio.Mmio(packed struct(u32) {
-            ///  FIFOData
-            FIFOData: u32,
-        }),
-    };
-
-    ///  Real time clock
-    pub const RTC = extern struct {
-        ///  RTC Control Register High
-        CRH: mmio.Mmio(packed struct(u32) {
-            ///  Second interrupt Enable
-            SECIE: u1,
-            ///  Alarm interrupt Enable
-            ALRIE: u1,
-            ///  Overflow interrupt Enable
-            OWIE: u1,
-            padding: u29,
-        }),
-        ///  RTC Control Register Low
-        CRL: mmio.Mmio(packed struct(u32) {
-            ///  Second Flag
-            SECF: u1,
-            ///  Alarm Flag
-            ALRF: u1,
-            ///  Overflow Flag
-            OWF: u1,
-            ///  Registers Synchronized Flag
-            RSF: u1,
-            ///  Configuration Flag
-            CNF: u1,
-            ///  RTC operation OFF
-            RTOFF: u1,
-            padding: u26,
-        }),
-        ///  RTC Prescaler Load Register High
-        PRLH: mmio.Mmio(packed struct(u32) {
-            ///  RTC Prescaler Load Register High
-            PRLH: u4,
-            padding: u28,
-        }),
-        ///  RTC Prescaler Load Register Low
-        PRLL: mmio.Mmio(packed struct(u32) {
-            ///  RTC Prescaler Divider Register Low
-            PRLL: u16,
-            padding: u16,
-        }),
-        ///  RTC Prescaler Divider Register High
-        DIVH: mmio.Mmio(packed struct(u32) {
-            ///  RTC prescaler divider register high
-            DIVH: u4,
-            padding: u28,
-        }),
-        ///  RTC Prescaler Divider Register Low
-        DIVL: mmio.Mmio(packed struct(u32) {
-            ///  RTC prescaler divider register Low
-            DIVL: u16,
-            padding: u16,
-        }),
-        ///  RTC Counter Register High
-        CNTH: mmio.Mmio(packed struct(u32) {
-            ///  RTC counter register high
-            CNTH: u16,
-            padding: u16,
-        }),
-        ///  RTC Counter Register Low
-        CNTL: mmio.Mmio(packed struct(u32) {
-            ///  RTC counter register Low
-            CNTL: u16,
-            padding: u16,
-        }),
-        ///  RTC Alarm Register High
-        ALRH: mmio.Mmio(packed struct(u32) {
-            ///  RTC alarm register high
-            ALRH: u16,
-            padding: u16,
-        }),
-        ///  RTC Alarm Register Low
-        ALRL: mmio.Mmio(packed struct(u32) {
-            ///  RTC alarm register low
-            ALRL: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Backup registers
-    pub const BKP = extern struct {
-        ///  Backup data register (BKP_DR)
-        DR1: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D1: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR2: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D2: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR3: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D3: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR4: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D4: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR5: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D5: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR6: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D6: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR7: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D7: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR8: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D8: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR9: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D9: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR10: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D10: u16,
-            padding: u16,
-        }),
-        ///  RTC clock calibration register (BKP_RTCCR)
-        RTCCR: mmio.Mmio(packed struct(u32) {
-            ///  Calibration value
-            CAL: u7,
-            ///  Calibration Clock Output
-            CCO: u1,
-            ///  Alarm or second output enable
-            ASOE: u1,
-            ///  Alarm or second output selection
-            ASOS: u1,
-            padding: u22,
-        }),
-        ///  Backup control register (BKP_CR)
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Tamper pin enable
-            TPE: u1,
-            ///  Tamper pin active level
-            TPAL: u1,
-            padding: u30,
-        }),
-        ///  BKP_CSR control/status register (BKP_CSR)
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  Clear Tamper event
-            CTE: u1,
-            ///  Clear Tamper Interrupt
-            CTI: u1,
-            ///  Tamper Pin interrupt enable
-            TPIE: u1,
-            reserved8: u5,
-            ///  Tamper Event Flag
-            TEF: u1,
-            ///  Tamper Interrupt Flag
-            TIF: u1,
-            padding: u22,
-        }),
-        reserved60: [8]u8,
-        ///  Backup data register (BKP_DR)
-        DR11: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            DR11: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR12: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            DR12: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR13: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            DR13: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR14: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D14: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR15: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D15: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR16: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D16: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR17: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D17: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR18: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D18: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR19: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D19: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR20: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D20: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR21: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D21: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR22: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D22: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR23: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D23: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR24: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D24: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR25: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D25: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR26: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D26: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR27: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D27: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR28: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D28: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR29: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D29: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR30: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D30: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR31: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D31: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR32: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D32: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR33: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D33: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR34: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D34: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR35: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D35: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR36: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D36: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR37: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D37: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR38: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D38: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR39: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D39: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR40: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D40: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR41: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D41: u16,
-            padding: u16,
-        }),
-        ///  Backup data register (BKP_DR)
-        DR42: mmio.Mmio(packed struct(u32) {
-            ///  Backup data
-            D42: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Independent watchdog
-    pub const IWDG = extern struct {
-        ///  Key register (IWDG_KR)
-        KR: mmio.Mmio(packed struct(u32) {
-            ///  Key value
-            KEY: u16,
-            padding: u16,
-        }),
-        ///  Prescaler register (IWDG_PR)
-        PR: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler divider
-            PR: u3,
-            padding: u29,
-        }),
-        ///  Reload register (IWDG_RLR)
-        RLR: mmio.Mmio(packed struct(u32) {
-            ///  Watchdog counter reload value
-            RL: u12,
-            padding: u20,
-        }),
-        ///  Status register (IWDG_SR)
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Watchdog prescaler value update
-            PVU: u1,
-            ///  Watchdog counter reload value update
-            RVU: u1,
-            padding: u30,
-        }),
-    };
-
-    ///  Window watchdog
-    pub const WWDG = extern struct {
-        ///  Control register (WWDG_CR)
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  7-bit counter (MSB to LSB)
-            T: u7,
-            ///  Activation bit
-            WDGA: u1,
-            padding: u24,
-        }),
-        ///  Configuration register (WWDG_CFR)
-        CFR: mmio.Mmio(packed struct(u32) {
-            ///  7-bit window value
-            W: u7,
-            ///  Timer Base
-            WDGTB: u2,
-            ///  Early Wakeup Interrupt
-            EWI: u1,
-            padding: u22,
-        }),
-        ///  Status register (WWDG_SR)
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Early Wakeup Interrupt
-            EWI: u1,
-            padding: u31,
-        }),
-    };
-
-    ///  Advanced timer
-    pub const TIM1 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/compare preloaded control
-            CCPC: u1,
-            reserved2: u1,
-            ///  Capture/compare control update selection
-            CCUS: u1,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            ///  Output Idle state 1
-            OIS1: u1,
-            ///  Output Idle state 1
-            OIS1N: u1,
-            ///  Output Idle state 2
-            OIS2: u1,
-            ///  Output Idle state 2
-            OIS2N: u1,
-            ///  Output Idle state 3
-            OIS3: u1,
-            ///  Output Idle state 3
-            OIS3N: u1,
-            ///  Output Idle state 4
-            OIS4: u1,
-            padding: u17,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            padding: u16,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            ///  COM interrupt enable
-            COMIE: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            ///  Break interrupt enable
-            BIE: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            ///  COM DMA request enable
-            COMDE: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            ///  COM interrupt flag
-            COMIF: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            ///  Break interrupt flag
-            BIF: u1,
-            reserved9: u1,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            padding: u19,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            ///  Capture/Compare control update generation
-            COMG: u1,
-            ///  Trigger generation
-            TG: u1,
-            ///  Break generation
-            BG: u1,
-            padding: u24,
-        }),
-        ///  capture/compare mode register (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            ///  Output Compare 1 clear enable
-            OC1CE: u1,
-            ///  Capture/Compare 2 selection
-            CC2S: u2,
-            ///  Output Compare 2 fast enable
-            OC2FE: u1,
-            ///  Output Compare 2 preload enable
-            OC2PE: u1,
-            ///  Output Compare 2 mode
-            OC2M: u3,
-            ///  Output Compare 2 clear enable
-            OC2CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare mode register (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 3 selection
-            CC3S: u2,
-            ///  Output compare 3 fast enable
-            OC3FE: u1,
-            ///  Output compare 3 preload enable
-            OC3PE: u1,
-            ///  Output compare 3 mode
-            OC3M: u3,
-            ///  Output compare 3 clear enable
-            OC3CE: u1,
-            ///  Capture/Compare 4 selection
-            CC4S: u2,
-            ///  Output compare 4 fast enable
-            OC4FE: u1,
-            ///  Output compare 4 preload enable
-            OC4PE: u1,
-            ///  Output compare 4 mode
-            OC4M: u3,
-            ///  Output compare 4 clear enable
-            OC4CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            ///  Capture/Compare 1 complementary output enable
-            CC1NE: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            ///  Capture/Compare 2 complementary output enable
-            CC2NE: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            ///  Capture/Compare 3 complementary output enable
-            CC3NE: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            padding: u18,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        ///  repetition counter register
-        RCR: mmio.Mmio(packed struct(u32) {
-            ///  Repetition counter value
-            REP: u8,
-            padding: u24,
-        }),
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 2 value
-            CCR2: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare value
-            CCR3: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare value
-            CCR4: u16,
-            padding: u16,
-        }),
-        ///  break and dead-time register
-        BDTR: mmio.Mmio(packed struct(u32) {
-            ///  Dead-time generator setup
-            DTG: u8,
-            ///  Lock configuration
-            LOCK: u2,
-            ///  Off-state selection for Idle mode
-            OSSI: u1,
-            ///  Off-state selection for Run mode
-            OSSR: u1,
-            ///  Break enable
-            BKE: u1,
-            ///  Break polarity
-            BKP: u1,
-            ///  Automatic output enable
-            AOE: u1,
-            ///  Main output enable
-            MOE: u1,
-            padding: u16,
-        }),
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Ethernet: Precision time protocol
-    pub const ETHERNET_PTP = extern struct {
-        ///  Ethernet PTP time stamp control register (ETH_PTPTSCR)
-        PTPTSCR: mmio.Mmio(packed struct(u32) {
-            ///  Time stamp enable
-            TSE: u1,
-            ///  Time stamp fine or coarse update
-            TSFCU: u1,
-            ///  Time stamp system time initialize
-            TSSTI: u1,
-            ///  Time stamp system time update
-            TSSTU: u1,
-            ///  Time stamp interrupt trigger enable
-            TSITE: u1,
-            ///  Time stamp addend register update
-            TSARU: u1,
-            padding: u26,
-        }),
-        ///  Ethernet PTP subsecond increment register
-        PTPSSIR: mmio.Mmio(packed struct(u32) {
-            ///  System time subsecond increment
-            STSSI: u8,
-            padding: u24,
-        }),
-        ///  Ethernet PTP time stamp high register
-        PTPTSHR: mmio.Mmio(packed struct(u32) {
-            ///  System time second
-            STS: u32,
-        }),
-        ///  Ethernet PTP time stamp low register (ETH_PTPTSLR)
-        PTPTSLR: mmio.Mmio(packed struct(u32) {
-            ///  System time subseconds
-            STSS: u31,
-            ///  System time positive or negative sign
-            STPNS: u1,
-        }),
-        ///  Ethernet PTP time stamp high update register
-        PTPTSHUR: mmio.Mmio(packed struct(u32) {
-            ///  Time stamp update second
-            TSUS: u32,
-        }),
-        ///  Ethernet PTP time stamp low update register (ETH_PTPTSLUR)
-        PTPTSLUR: mmio.Mmio(packed struct(u32) {
-            ///  Time stamp update subseconds
-            TSUSS: u31,
-            ///  Time stamp update positive or negative sign
-            TSUPNS: u1,
-        }),
-        ///  Ethernet PTP time stamp addend register
-        PTPTSAR: mmio.Mmio(packed struct(u32) {
-            ///  Time stamp addend
-            TSA: u32,
-        }),
-        ///  Ethernet PTP target time high register
-        PTPTTHR: mmio.Mmio(packed struct(u32) {
-            ///  Target time stamp high
-            TTSH: u32,
-        }),
-        ///  Ethernet PTP target time low register
-        PTPTTLR: mmio.Mmio(packed struct(u32) {
-            ///  Target time stamp low
-            TTSL: u32,
-        }),
-    };
-
-    ///  General purpose timer
-    pub const TIM2 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            padding: u24,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            padding: u16,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            reserved6: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            reserved8: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            reserved14: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            reserved6: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            reserved9: u2,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            padding: u19,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            reserved6: u1,
-            ///  Trigger generation
-            TG: u1,
-            padding: u25,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output compare 1 fast enable
-            OC1FE: u1,
-            ///  Output compare 1 preload enable
-            OC1PE: u1,
-            ///  Output compare 1 mode
-            OC1M: u3,
-            ///  Output compare 1 clear enable
-            OC1CE: u1,
-            ///  Capture/Compare 2 selection
-            CC2S: u2,
-            ///  Output compare 2 fast enable
-            OC2FE: u1,
-            ///  Output compare 2 preload enable
-            OC2PE: u1,
-            ///  Output compare 2 mode
-            OC2M: u3,
-            ///  Output compare 2 clear enable
-            OC2CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare mode register 2 (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 3 selection
-            CC3S: u2,
-            ///  Output compare 3 fast enable
-            OC3FE: u1,
-            ///  Output compare 3 preload enable
-            OC3PE: u1,
-            ///  Output compare 3 mode
-            OC3M: u3,
-            ///  Output compare 3 clear enable
-            OC3CE: u1,
-            ///  Capture/Compare 4 selection
-            CC4S: u2,
-            ///  Output compare 4 fast enable
-            OC4FE: u1,
-            ///  Output compare 4 preload enable
-            OC4PE: u1,
-            ///  Output compare 4 mode
-            OC4M: u3,
-            ///  Output compare 4 clear enable
-            O24CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved4: u2,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved8: u2,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            reserved12: u2,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            padding: u18,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 2 value
-            CCR2: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare value
-            CCR3: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare value
-            CCR4: u16,
-            padding: u16,
-        }),
-        reserved72: [4]u8,
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Ethernet: media access control
-    pub const ETHERNET_MAC = extern struct {
-        ///  Ethernet MAC configuration register (ETH_MACCR)
-        MACCR: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Receiver enable
-            RE: u1,
-            ///  Transmitter enable
-            TE: u1,
-            ///  Deferral check
-            DC: u1,
-            ///  Back-off limit
-            BL: u2,
-            ///  Automatic pad/CRC stripping
-            APCS: u1,
-            reserved9: u1,
-            ///  Retry disable
-            RD: u1,
-            ///  IPv4 checksum offload
-            IPCO: u1,
-            ///  Duplex mode
-            DM: u1,
-            ///  Loopback mode
-            LM: u1,
-            ///  Receive own disable
-            ROD: u1,
-            ///  Fast Ethernet speed
-            FES: u1,
-            reserved16: u1,
-            ///  Carrier sense disable
-            CSD: u1,
-            ///  Interframe gap
-            IFG: u3,
-            reserved22: u2,
-            ///  Jabber disable
-            JD: u1,
-            ///  Watchdog disable
-            WD: u1,
-            padding: u8,
-        }),
-        ///  Ethernet MAC frame filter register (ETH_MACCFFR)
-        MACFFR: mmio.Mmio(packed struct(u32) {
-            ///  Promiscuous mode
-            PM: u1,
-            ///  Hash unicast
-            HU: u1,
-            ///  Hash multicast
-            HM: u1,
-            ///  Destination address inverse filtering
-            DAIF: u1,
-            ///  Pass all multicast
-            PAM: u1,
-            ///  Broadcast frames disable
-            BFD: u1,
-            ///  Pass control frames
-            PCF: u2,
-            ///  Source address inverse filtering
-            SAIF: u1,
-            ///  Source address filter
-            SAF: u1,
-            ///  Hash or perfect filter
-            HPF: u1,
-            reserved31: u20,
-            ///  Receive all
-            RA: u1,
-        }),
-        ///  Ethernet MAC hash table high register
-        MACHTHR: mmio.Mmio(packed struct(u32) {
-            ///  Hash table high
-            HTH: u32,
-        }),
-        ///  Ethernet MAC hash table low register
-        MACHTLR: mmio.Mmio(packed struct(u32) {
-            ///  Hash table low
-            HTL: u32,
-        }),
-        ///  Ethernet MAC MII address register (ETH_MACMIIAR)
-        MACMIIAR: mmio.Mmio(packed struct(u32) {
-            ///  MII busy
-            MB: u1,
-            ///  MII write
-            MW: u1,
-            ///  Clock range
-            CR: u3,
-            reserved6: u1,
-            ///  MII register
-            MR: u5,
-            ///  PHY address
-            PA: u5,
-            padding: u16,
-        }),
-        ///  Ethernet MAC MII data register (ETH_MACMIIDR)
-        MACMIIDR: mmio.Mmio(packed struct(u32) {
-            ///  MII data
-            MD: u16,
-            padding: u16,
-        }),
-        ///  Ethernet MAC flow control register (ETH_MACFCR)
-        MACFCR: mmio.Mmio(packed struct(u32) {
-            ///  Flow control busy/back pressure activate
-            FCB_BPA: u1,
-            ///  Transmit flow control enable
-            TFCE: u1,
-            ///  Receive flow control enable
-            RFCE: u1,
-            ///  Unicast pause frame detect
-            UPFD: u1,
-            ///  Pause low threshold
-            PLT: u2,
-            reserved7: u1,
-            ///  Zero-quanta pause disable
-            ZQPD: u1,
-            reserved16: u8,
-            ///  Pass control frames
-            PT: u16,
-        }),
-        ///  Ethernet MAC VLAN tag register (ETH_MACVLANTR)
-        MACVLANTR: mmio.Mmio(packed struct(u32) {
-            ///  VLAN tag identifier (for receive frames)
-            VLANTI: u16,
-            ///  12-bit VLAN tag comparison
-            VLANTC: u1,
-            padding: u15,
-        }),
-        reserved40: [8]u8,
-        ///  Ethernet MAC remote wakeup frame filter register (ETH_MACRWUFFR)
-        MACRWUFFR: u32,
-        ///  Ethernet MAC PMT control and status register (ETH_MACPMTCSR)
-        MACPMTCSR: mmio.Mmio(packed struct(u32) {
-            ///  Power down
-            PD: u1,
-            ///  Magic Packet enable
-            MPE: u1,
-            ///  Wakeup frame enable
-            WFE: u1,
-            reserved5: u2,
-            ///  Magic packet received
-            MPR: u1,
-            ///  Wakeup frame received
-            WFR: u1,
-            reserved9: u2,
-            ///  Global unicast
-            GU: u1,
-            reserved31: u21,
-            ///  Wakeup frame filter register pointer reset
-            WFFRPR: u1,
-        }),
-        reserved56: [8]u8,
-        ///  Ethernet MAC interrupt status register (ETH_MACSR)
-        MACSR: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  PMT status
-            PMTS: u1,
-            ///  MMC status
-            MMCS: u1,
-            ///  MMC receive status
-            MMCRS: u1,
-            ///  MMC transmit status
-            MMCTS: u1,
-            reserved9: u2,
-            ///  Time stamp trigger status
-            TSTS: u1,
-            padding: u22,
-        }),
-        ///  Ethernet MAC interrupt mask register (ETH_MACIMR)
-        MACIMR: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  PMT interrupt mask
-            PMTIM: u1,
-            reserved9: u5,
-            ///  Time stamp trigger interrupt mask
-            TSTIM: u1,
-            padding: u22,
-        }),
-        ///  Ethernet MAC address 0 high register (ETH_MACA0HR)
-        MACA0HR: mmio.Mmio(packed struct(u32) {
-            ///  MAC address0 high
-            MACA0H: u16,
-            reserved31: u15,
-            ///  Always 1
-            MO: u1,
-        }),
-        ///  Ethernet MAC address 0 low register
-        MACA0LR: mmio.Mmio(packed struct(u32) {
-            ///  MAC address0 low
-            MACA0L: u32,
-        }),
-        ///  Ethernet MAC address 1 high register (ETH_MACA1HR)
-        MACA1HR: mmio.Mmio(packed struct(u32) {
-            ///  MAC address1 high
-            MACA1H: u16,
-            reserved24: u8,
-            ///  Mask byte control
-            MBC: u6,
-            ///  Source address
-            SA: u1,
-            ///  Address enable
-            AE: u1,
-        }),
-        ///  Ethernet MAC address1 low register
-        MACA1LR: mmio.Mmio(packed struct(u32) {
-            ///  MAC address1 low
-            MACA1L: u32,
-        }),
-        ///  Ethernet MAC address 2 high register (ETH_MACA2HR)
-        MACA2HR: mmio.Mmio(packed struct(u32) {
-            ///  Ethernet MAC address 2 high register
-            ETH_MACA2HR: u16,
-            reserved24: u8,
-            ///  Mask byte control
-            MBC: u6,
-            ///  Source address
-            SA: u1,
-            ///  Address enable
-            AE: u1,
-        }),
-        ///  Ethernet MAC address 2 low register
-        MACA2LR: mmio.Mmio(packed struct(u32) {
-            ///  MAC address2 low
-            MACA2L: u31,
-            padding: u1,
-        }),
-        ///  Ethernet MAC address 3 high register (ETH_MACA3HR)
-        MACA3HR: mmio.Mmio(packed struct(u32) {
-            ///  MAC address3 high
-            MACA3H: u16,
-            reserved24: u8,
-            ///  Mask byte control
-            MBC: u6,
-            ///  Source address
-            SA: u1,
-            ///  Address enable
-            AE: u1,
-        }),
-        ///  Ethernet MAC address 3 low register
-        MACA3LR: mmio.Mmio(packed struct(u32) {
-            ///  MAC address3 low
-            MBCA3L: u32,
-        }),
-    };
-
-    ///  Ethernet: MAC management counters
-    pub const ETHERNET_MMC = extern struct {
-        ///  Ethernet MMC control register (ETH_MMCCR)
-        MMCCR: mmio.Mmio(packed struct(u32) {
-            ///  Counter reset
-            CR: u1,
-            ///  Counter stop rollover
-            CSR: u1,
-            ///  Reset on read
-            ROR: u1,
-            reserved31: u28,
-            ///  MMC counter freeze
-            MCF: u1,
-        }),
-        ///  Ethernet MMC receive interrupt register (ETH_MMCRIR)
-        MMCRIR: mmio.Mmio(packed struct(u32) {
-            reserved5: u5,
-            ///  Received frames CRC error status
-            RFCES: u1,
-            ///  Received frames alignment error status
-            RFAES: u1,
-            reserved17: u10,
-            ///  Received Good Unicast Frames Status
-            RGUFS: u1,
-            padding: u14,
-        }),
-        ///  Ethernet MMC transmit interrupt register (ETH_MMCTIR)
-        MMCTIR: mmio.Mmio(packed struct(u32) {
-            reserved14: u14,
-            ///  Transmitted good frames single collision status
-            TGFSCS: u1,
-            ///  Transmitted good frames more single collision status
-            TGFMSCS: u1,
-            reserved21: u5,
-            ///  Transmitted good frames status
-            TGFS: u1,
-            padding: u10,
-        }),
-        ///  Ethernet MMC receive interrupt mask register (ETH_MMCRIMR)
-        MMCRIMR: mmio.Mmio(packed struct(u32) {
-            reserved5: u5,
-            ///  Received frame CRC error mask
-            RFCEM: u1,
-            ///  Received frames alignment error mask
-            RFAEM: u1,
-            reserved17: u10,
-            ///  Received good unicast frames mask
-            RGUFM: u1,
-            padding: u14,
-        }),
-        ///  Ethernet MMC transmit interrupt mask register (ETH_MMCTIMR)
-        MMCTIMR: mmio.Mmio(packed struct(u32) {
-            reserved14: u14,
-            ///  Transmitted good frames single collision mask
-            TGFSCM: u1,
-            ///  Transmitted good frames more single collision mask
-            TGFMSCM: u1,
-            reserved21: u5,
-            ///  Transmitted good frames mask
-            TGFM: u1,
-            padding: u10,
-        }),
-        reserved76: [56]u8,
-        ///  Ethernet MMC transmitted good frames after a single collision counter
-        MMCTGFSCCR: mmio.Mmio(packed struct(u32) {
-            ///  Transmitted good frames after a single collision counter
-            TGFSCC: u32,
-        }),
-        ///  Ethernet MMC transmitted good frames after more than a single collision
-        MMCTGFMSCCR: mmio.Mmio(packed struct(u32) {
-            ///  Transmitted good frames after more than a single collision counter
-            TGFMSCC: u32,
-        }),
-        reserved104: [20]u8,
-        ///  Ethernet MMC transmitted good frames counter register
-        MMCTGFCR: mmio.Mmio(packed struct(u32) {
-            ///  Transmitted good frames counter
-            TGFC: u32,
-        }),
-        reserved148: [40]u8,
-        ///  Ethernet MMC received frames with CRC error counter register
-        MMCRFCECR: mmio.Mmio(packed struct(u32) {
-            ///  Received frames with CRC error counter
-            RFCFC: u32,
-        }),
-        ///  Ethernet MMC received frames with alignment error counter register
-        MMCRFAECR: mmio.Mmio(packed struct(u32) {
-            ///  Received frames with alignment error counter
-            RFAEC: u32,
-        }),
-        reserved196: [40]u8,
-        ///  MMC received good unicast frames counter register
-        MMCRGUFCR: mmio.Mmio(packed struct(u32) {
-            ///  Received good unicast frames counter
-            RGUFC: u32,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_PWRCLK = extern struct {
-        ///  OTG_FS power and clock gating control register
-        FS_PCGCCTL: mmio.Mmio(packed struct(u32) {
-            ///  Stop PHY clock
-            STPPCLK: u1,
-            ///  Gate HCLK
-            GATEHCLK: u1,
-            reserved4: u2,
-            ///  PHY Suspended
-            PHYSUSP: u1,
-            padding: u27,
-        }),
-    };
-
-    ///  General purpose timer
-    pub const TIM9 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            reserved7: u3,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  Master mode selection
-            MMS: u3,
-            padding: u25,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            padding: u24,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            reserved6: u3,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            padding: u25,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            reserved6: u3,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            reserved9: u2,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            padding: u21,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            reserved6: u3,
-            ///  Trigger generation
-            TG: u1,
-            padding: u25,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            reserved8: u1,
-            ///  Capture/Compare 2 selection
-            CC2S: u2,
-            ///  Output Compare 2 fast enable
-            OC2FE: u1,
-            ///  Output Compare 2 preload enable
-            OC2PE: u1,
-            ///  Output Compare 2 mode
-            OC2M: u3,
-            padding: u17,
-        }),
-        reserved32: [4]u8,
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved7: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            padding: u24,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 2 value
-            CCR2: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_HOST = extern struct {
-        ///  OTG_FS host configuration register (OTG_FS_HCFG)
-        FS_HCFG: mmio.Mmio(packed struct(u32) {
-            ///  FS/LS PHY clock select
-            FSLSPCS: u2,
-            ///  FS- and LS-only support
-            FSLSS: u1,
-            padding: u29,
-        }),
-        ///  OTG_FS Host frame interval register
-        HFIR: mmio.Mmio(packed struct(u32) {
-            ///  Frame interval
-            FRIVL: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
-        FS_HFNUM: mmio.Mmio(packed struct(u32) {
-            ///  Frame number
-            FRNUM: u16,
-            ///  Frame time remaining
-            FTREM: u16,
-        }),
-        reserved16: [4]u8,
-        ///  OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
-        FS_HPTXSTS: mmio.Mmio(packed struct(u32) {
-            ///  Periodic transmit data FIFO space available
-            PTXFSAVL: u16,
-            ///  Periodic transmit request queue space available
-            PTXQSAV: u8,
-            ///  Top of the periodic transmit request queue
-            PTXQTOP: u8,
-        }),
-        ///  OTG_FS Host all channels interrupt register
-        HAINT: mmio.Mmio(packed struct(u32) {
-            ///  Channel interrupts
-            HAINT: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS host all channels interrupt mask register
-        HAINTMSK: mmio.Mmio(packed struct(u32) {
-            ///  Channel interrupt mask
-            HAINTM: u16,
-            padding: u16,
-        }),
-        reserved64: [36]u8,
-        ///  OTG_FS host port control and status register (OTG_FS_HPRT)
-        FS_HPRT: mmio.Mmio(packed struct(u32) {
-            ///  Port connect status
-            PCSTS: u1,
-            ///  Port connect detected
-            PCDET: u1,
-            ///  Port enable
-            PENA: u1,
-            ///  Port enable/disable change
-            PENCHNG: u1,
-            ///  Port overcurrent active
-            POCA: u1,
-            ///  Port overcurrent change
-            POCCHNG: u1,
-            ///  Port resume
-            PRES: u1,
-            ///  Port suspend
-            PSUSP: u1,
-            ///  Port reset
-            PRST: u1,
-            reserved10: u1,
-            ///  Port line status
-            PLSTS: u2,
-            ///  Port power
-            PPWR: u1,
-            ///  Port test control
-            PTCTL: u4,
-            ///  Port speed
-            PSPD: u2,
-            padding: u13,
-        }),
-        reserved256: [188]u8,
-        ///  OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
-        FS_HCCHAR0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved264: [4]u8,
-        ///  OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
-        FS_HCINT0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
-        FS_HCINTMSK0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-0 transfer size register
-        FS_HCTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved288: [12]u8,
-        ///  OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)
-        FS_HCCHAR1: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved296: [4]u8,
-        ///  OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)
-        FS_HCINT1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)
-        FS_HCINTMSK1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-1 transfer size register
-        FS_HCTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved320: [12]u8,
-        ///  OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)
-        FS_HCCHAR2: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved328: [4]u8,
-        ///  OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)
-        FS_HCINT2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)
-        FS_HCINTMSK2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-2 transfer size register
-        FS_HCTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved352: [12]u8,
-        ///  OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)
-        FS_HCCHAR3: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved360: [4]u8,
-        ///  OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)
-        FS_HCINT3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)
-        FS_HCINTMSK3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-3 transfer size register
-        FS_HCTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved384: [12]u8,
-        ///  OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)
-        FS_HCCHAR4: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved392: [4]u8,
-        ///  OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)
-        FS_HCINT4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)
-        FS_HCINTMSK4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-x transfer size register
-        FS_HCTSIZ4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved416: [12]u8,
-        ///  OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)
-        FS_HCCHAR5: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved424: [4]u8,
-        ///  OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)
-        FS_HCINT5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)
-        FS_HCINTMSK5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-5 transfer size register
-        FS_HCTSIZ5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved448: [12]u8,
-        ///  OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)
-        FS_HCCHAR6: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved456: [4]u8,
-        ///  OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)
-        FS_HCINT6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)
-        FS_HCINTMSK6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-6 transfer size register
-        FS_HCTSIZ6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved480: [12]u8,
-        ///  OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)
-        FS_HCCHAR7: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved488: [4]u8,
-        ///  OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)
-        FS_HCINT7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)
-        FS_HCINTMSK7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-7 transfer size register
-        FS_HCTSIZ7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-    };
-
-    ///  General purpose timer
-    pub const TIM10 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            reserved7: u4,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  Master mode selection
-            MMS: u3,
-            padding: u25,
-        }),
-        reserved12: [4]u8,
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            padding: u30,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            reserved9: u7,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            padding: u22,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            padding: u30,
-        }),
-        ///  capture/compare mode register (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            reserved3: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            padding: u25,
-        }),
-        reserved32: [4]u8,
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            padding: u28,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_GLOBAL = extern struct {
-        ///  OTG_FS control and status register (OTG_FS_GOTGCTL)
-        FS_GOTGCTL: mmio.Mmio(packed struct(u32) {
-            ///  Session request success
-            SRQSCS: u1,
-            ///  Session request
-            SRQ: u1,
-            reserved8: u6,
-            ///  Host negotiation success
-            HNGSCS: u1,
-            ///  HNP request
-            HNPRQ: u1,
-            ///  Host set HNP enable
-            HSHNPEN: u1,
-            ///  Device HNP enabled
-            DHNPEN: u1,
-            reserved16: u4,
-            ///  Connector ID status
-            CIDSTS: u1,
-            ///  Long/short debounce time
-            DBCT: u1,
-            ///  A-session valid
-            ASVLD: u1,
-            ///  B-session valid
-            BSVLD: u1,
-            padding: u12,
-        }),
-        ///  OTG_FS interrupt register (OTG_FS_GOTGINT)
-        FS_GOTGINT: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Session end detected
-            SEDET: u1,
-            reserved8: u5,
-            ///  Session request success status change
-            SRSSCHG: u1,
-            ///  Host negotiation success status change
-            HNSSCHG: u1,
-            reserved17: u7,
-            ///  Host negotiation detected
-            HNGDET: u1,
-            ///  A-device timeout change
-            ADTOCHG: u1,
-            ///  Debounce done
-            DBCDNE: u1,
-            padding: u12,
-        }),
-        ///  OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
-        FS_GAHBCFG: mmio.Mmio(packed struct(u32) {
-            ///  Global interrupt mask
-            GINT: u1,
-            reserved7: u6,
-            ///  TxFIFO empty level
-            TXFELVL: u1,
-            ///  Periodic TxFIFO empty level
-            PTXFELVL: u1,
-            padding: u23,
-        }),
-        ///  OTG_FS USB configuration register (OTG_FS_GUSBCFG)
-        FS_GUSBCFG: mmio.Mmio(packed struct(u32) {
-            ///  FS timeout calibration
-            TOCAL: u3,
-            reserved6: u3,
-            ///  Full Speed serial transceiver select
-            PHYSEL: u1,
-            reserved8: u1,
-            ///  SRP-capable
-            SRPCAP: u1,
-            ///  HNP-capable
-            HNPCAP: u1,
-            ///  USB turnaround time
-            TRDT: u4,
-            reserved29: u15,
-            ///  Force host mode
-            FHMOD: u1,
-            ///  Force device mode
-            FDMOD: u1,
-            ///  Corrupt Tx packet
-            CTXPKT: u1,
-        }),
-        ///  OTG_FS reset register (OTG_FS_GRSTCTL)
-        FS_GRSTCTL: mmio.Mmio(packed struct(u32) {
-            ///  Core soft reset
-            CSRST: u1,
-            ///  HCLK soft reset
-            HSRST: u1,
-            ///  Host frame counter reset
-            FCRST: u1,
-            reserved4: u1,
-            ///  RxFIFO flush
-            RXFFLSH: u1,
-            ///  TxFIFO flush
-            TXFFLSH: u1,
-            ///  TxFIFO number
-            TXFNUM: u5,
-            reserved31: u20,
-            ///  AHB master idle
-            AHBIDL: u1,
-        }),
-        ///  OTG_FS core interrupt register (OTG_FS_GINTSTS)
-        FS_GINTSTS: mmio.Mmio(packed struct(u32) {
-            ///  Current mode of operation
-            CMOD: u1,
-            ///  Mode mismatch interrupt
-            MMIS: u1,
-            ///  OTG interrupt
-            OTGINT: u1,
-            ///  Start of frame
-            SOF: u1,
-            ///  RxFIFO non-empty
-            RXFLVL: u1,
-            ///  Non-periodic TxFIFO empty
-            NPTXFE: u1,
-            ///  Global IN non-periodic NAK effective
-            GINAKEFF: u1,
-            ///  Global OUT NAK effective
-            GOUTNAKEFF: u1,
-            reserved10: u2,
-            ///  Early suspend
-            ESUSP: u1,
-            ///  USB suspend
-            USBSUSP: u1,
-            ///  USB reset
-            USBRST: u1,
-            ///  Enumeration done
-            ENUMDNE: u1,
-            ///  Isochronous OUT packet dropped interrupt
-            ISOODRP: u1,
-            ///  End of periodic frame interrupt
-            EOPF: u1,
-            reserved18: u2,
-            ///  IN endpoint interrupt
-            IEPINT: u1,
-            ///  OUT endpoint interrupt
-            OEPINT: u1,
-            ///  Incomplete isochronous IN transfer
-            IISOIXFR: u1,
-            ///  Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)
-            IPXFR_INCOMPISOOUT: u1,
-            reserved24: u2,
-            ///  Host port interrupt
-            HPRTINT: u1,
-            ///  Host channels interrupt
-            HCINT: u1,
-            ///  Periodic TxFIFO empty
-            PTXFE: u1,
-            reserved28: u1,
-            ///  Connector ID status change
-            CIDSCHG: u1,
-            ///  Disconnect detected interrupt
-            DISCINT: u1,
-            ///  Session request/new session detected interrupt
-            SRQINT: u1,
-            ///  Resume/remote wakeup detected interrupt
-            WKUPINT: u1,
-        }),
-        ///  OTG_FS interrupt mask register (OTG_FS_GINTMSK)
-        FS_GINTMSK: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Mode mismatch interrupt mask
-            MMISM: u1,
-            ///  OTG interrupt mask
-            OTGINT: u1,
-            ///  Start of frame mask
-            SOFM: u1,
-            ///  Receive FIFO non-empty mask
-            RXFLVLM: u1,
-            ///  Non-periodic TxFIFO empty mask
-            NPTXFEM: u1,
-            ///  Global non-periodic IN NAK effective mask
-            GINAKEFFM: u1,
-            ///  Global OUT NAK effective mask
-            GONAKEFFM: u1,
-            reserved10: u2,
-            ///  Early suspend mask
-            ESUSPM: u1,
-            ///  USB suspend mask
-            USBSUSPM: u1,
-            ///  USB reset mask
-            USBRST: u1,
-            ///  Enumeration done mask
-            ENUMDNEM: u1,
-            ///  Isochronous OUT packet dropped interrupt mask
-            ISOODRPM: u1,
-            ///  End of periodic frame interrupt mask
-            EOPFM: u1,
-            reserved17: u1,
-            ///  Endpoint mismatch interrupt mask
-            EPMISM: u1,
-            ///  IN endpoints interrupt mask
-            IEPINT: u1,
-            ///  OUT endpoints interrupt mask
-            OEPINT: u1,
-            ///  Incomplete isochronous IN transfer mask
-            IISOIXFRM: u1,
-            ///  Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)
-            IPXFRM_IISOOXFRM: u1,
-            reserved24: u2,
-            ///  Host port interrupt mask
-            PRTIM: u1,
-            ///  Host channels interrupt mask
-            HCIM: u1,
-            ///  Periodic TxFIFO empty mask
-            PTXFEM: u1,
-            reserved28: u1,
-            ///  Connector ID status change mask
-            CIDSCHGM: u1,
-            ///  Disconnect detected interrupt mask
-            DISCINT: u1,
-            ///  Session request/new session detected interrupt mask
-            SRQIM: u1,
-            ///  Resume/remote wakeup detected interrupt mask
-            WUIM: u1,
-        }),
-        ///  OTG_FS Receive status debug read(Device mode)
-        FS_GRXSTSR_Device: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Byte count
-            BCNT: u11,
-            ///  Data PID
-            DPID: u2,
-            ///  Packet status
-            PKTSTS: u4,
-            ///  Frame number
-            FRMNUM: u4,
-            padding: u7,
-        }),
-        reserved36: [4]u8,
-        ///  OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
-        FS_GRXFSIZ: mmio.Mmio(packed struct(u32) {
-            ///  RxFIFO depth
-            RXFD: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS non-periodic transmit FIFO size register (Device mode)
-        FS_GNPTXFSIZ_Device: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint 0 transmit RAM start address
-            TX0FSA: u16,
-            ///  Endpoint 0 TxFIFO depth
-            TX0FD: u16,
-        }),
-        ///  OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)
-        FS_GNPTXSTS: mmio.Mmio(packed struct(u32) {
-            ///  Non-periodic TxFIFO space available
-            NPTXFSAV: u16,
-            ///  Non-periodic transmit request queue space available
-            NPTQXSAV: u8,
-            ///  Top of the non-periodic transmit request queue
-            NPTXQTOP: u7,
-            padding: u1,
-        }),
-        reserved56: [8]u8,
-        ///  OTG_FS general core configuration register (OTG_FS_GCCFG)
-        FS_GCCFG: mmio.Mmio(packed struct(u32) {
-            reserved16: u16,
-            ///  Power down
-            PWRDWN: u1,
-            reserved18: u1,
-            ///  Enable the VBUS sensing device
-            VBUSASEN: u1,
-            ///  Enable the VBUS sensing device
-            VBUSBSEN: u1,
-            ///  SOF output enable
-            SOFOUTEN: u1,
-            padding: u11,
-        }),
-        ///  core ID register
-        FS_CID: mmio.Mmio(packed struct(u32) {
-            ///  Product ID field
-            PRODUCT_ID: u32,
-        }),
-        reserved256: [192]u8,
-        ///  OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
-        FS_HPTXFSIZ: mmio.Mmio(packed struct(u32) {
-            ///  Host periodic TxFIFO start address
-            PTXSA: u16,
-            ///  Host periodic TxFIFO depth
-            PTXFSIZ: u16,
-        }),
-        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)
-        FS_DIEPTXF1: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFO2 transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)
-        FS_DIEPTXF2: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFO3 transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)
-        FS_DIEPTXF3: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFO4 transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_DEVICE = extern struct {
-        ///  OTG_FS device configuration register (OTG_FS_DCFG)
-        FS_DCFG: mmio.Mmio(packed struct(u32) {
-            ///  Device speed
-            DSPD: u2,
-            ///  Non-zero-length status OUT handshake
-            NZLSOHSK: u1,
-            reserved4: u1,
-            ///  Device address
-            DAD: u7,
-            ///  Periodic frame interval
-            PFIVL: u2,
-            padding: u19,
-        }),
-        ///  OTG_FS device control register (OTG_FS_DCTL)
-        FS_DCTL: mmio.Mmio(packed struct(u32) {
-            ///  Remote wakeup signaling
-            RWUSIG: u1,
-            ///  Soft disconnect
-            SDIS: u1,
-            ///  Global IN NAK status
-            GINSTS: u1,
-            ///  Global OUT NAK status
-            GONSTS: u1,
-            ///  Test control
-            TCTL: u3,
-            ///  Set global IN NAK
-            SGINAK: u1,
-            ///  Clear global IN NAK
-            CGINAK: u1,
-            ///  Set global OUT NAK
-            SGONAK: u1,
-            ///  Clear global OUT NAK
-            CGONAK: u1,
-            ///  Power-on programming done
-            POPRGDNE: u1,
-            padding: u20,
-        }),
-        ///  OTG_FS device status register (OTG_FS_DSTS)
-        FS_DSTS: mmio.Mmio(packed struct(u32) {
-            ///  Suspend status
-            SUSPSTS: u1,
-            ///  Enumerated speed
-            ENUMSPD: u2,
-            ///  Erratic error
-            EERR: u1,
-            reserved8: u4,
-            ///  Frame number of the received SOF
-            FNSOF: u14,
-            padding: u10,
-        }),
-        reserved16: [4]u8,
-        ///  OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
-        FS_DIEPMSK: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  Timeout condition mask (Non-isochronous endpoints)
-            TOM: u1,
-            ///  IN token received when TxFIFO empty mask
-            ITTXFEMSK: u1,
-            ///  IN token received with EP mismatch mask
-            INEPNMM: u1,
-            ///  IN endpoint NAK effective mask
-            INEPNEM: u1,
-            padding: u25,
-        }),
-        ///  OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
-        FS_DOEPMSK: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  SETUP phase done mask
-            STUPM: u1,
-            ///  OUT token received when endpoint disabled mask
-            OTEPDM: u1,
-            padding: u27,
-        }),
-        ///  OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
-        FS_DAINT: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint interrupt bits
-            IEPINT: u16,
-            ///  OUT endpoint interrupt bits
-            OEPINT: u16,
-        }),
-        ///  OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
-        FS_DAINTMSK: mmio.Mmio(packed struct(u32) {
-            ///  IN EP interrupt mask bits
-            IEPM: u16,
-            ///  OUT endpoint interrupt bits
-            OEPINT: u16,
-        }),
-        reserved40: [8]u8,
-        ///  OTG_FS device VBUS discharge time register
-        DVBUSDIS: mmio.Mmio(packed struct(u32) {
-            ///  Device VBUS discharge time
-            VBUSDT: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS device VBUS pulsing time register
-        DVBUSPULSE: mmio.Mmio(packed struct(u32) {
-            ///  Device VBUS pulsing time
-            DVBUSP: u12,
-            padding: u20,
-        }),
-        reserved52: [4]u8,
-        ///  OTG_FS device IN endpoint FIFO empty interrupt mask register
-        DIEPEMPMSK: mmio.Mmio(packed struct(u32) {
-            ///  IN EP Tx FIFO empty interrupt mask bits
-            INEPTXFEM: u16,
-            padding: u16,
-        }),
-        reserved256: [200]u8,
-        ///  OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
-        FS_DIEPCTL0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u2,
-            reserved15: u13,
-            ///  USB active endpoint
-            USBAEP: u1,
-            reserved17: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            STALL: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            reserved30: u2,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved264: [4]u8,
-        ///  device endpoint-x interrupt register
-        DIEPINT0: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved272: [4]u8,
-        ///  device endpoint-0 transfer size register
-        DIEPTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u7,
-            reserved19: u12,
-            ///  Packet count
-            PKTCNT: u2,
-            padding: u11,
-        }),
-        reserved280: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS0: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved288: [4]u8,
-        ///  OTG device endpoint-1 control register
-        DIEPCTL1: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            reserved21: u1,
-            ///  Stall
-            Stall: u1,
-            ///  TXFNUM
-            TXFNUM: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM/SD1PID
-            SODDFRM_SD1PID: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved296: [4]u8,
-        ///  device endpoint-1 interrupt register
-        DIEPINT1: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved304: [4]u8,
-        ///  device endpoint-1 transfer size register
-        DIEPTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        reserved312: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS1: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved320: [4]u8,
-        ///  OTG device endpoint-2 control register
-        DIEPCTL2: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            reserved21: u1,
-            ///  Stall
-            Stall: u1,
-            ///  TXFNUM
-            TXFNUM: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved328: [4]u8,
-        ///  device endpoint-2 interrupt register
-        DIEPINT2: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved336: [4]u8,
-        ///  device endpoint-2 transfer size register
-        DIEPTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        reserved344: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS2: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved352: [4]u8,
-        ///  OTG device endpoint-3 control register
-        DIEPCTL3: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            reserved21: u1,
-            ///  Stall
-            Stall: u1,
-            ///  TXFNUM
-            TXFNUM: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved360: [4]u8,
-        ///  device endpoint-3 interrupt register
-        DIEPINT3: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved368: [4]u8,
-        ///  device endpoint-3 transfer size register
-        DIEPTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        reserved376: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS3: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved768: [388]u8,
-        ///  device endpoint-0 control register
-        DOEPCTL0: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u2,
-            reserved15: u13,
-            ///  USBAEP
-            USBAEP: u1,
-            reserved17: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            reserved30: u2,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved776: [4]u8,
-        ///  device endpoint-0 interrupt register
-        DOEPINT0: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved784: [4]u8,
-        ///  device OUT endpoint-0 transfer size register
-        DOEPTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u7,
-            reserved19: u12,
-            ///  Packet count
-            PKTCNT: u1,
-            reserved29: u9,
-            ///  SETUP packet count
-            STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved800: [12]u8,
-        ///  device endpoint-1 control register
-        DOEPCTL1: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved808: [4]u8,
-        ///  device endpoint-1 interrupt register
-        DOEPINT1: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved816: [4]u8,
-        ///  device OUT endpoint-1 transfer size register
-        DOEPTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved832: [12]u8,
-        ///  device endpoint-2 control register
-        DOEPCTL2: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved840: [4]u8,
-        ///  device endpoint-2 interrupt register
-        DOEPINT2: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved848: [4]u8,
-        ///  device OUT endpoint-2 transfer size register
-        DOEPTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved864: [12]u8,
-        ///  device endpoint-3 control register
-        DOEPCTL3: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved872: [4]u8,
-        ///  device endpoint-3 interrupt register
-        DOEPINT3: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved880: [4]u8,
-        ///  device OUT endpoint-3 transfer size register
-        DOEPTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-    };
-
-    ///  Universal serial bus full-speed device interface
-    pub const USB = extern struct {
-        ///  endpoint 0 register
-        EP0R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 1 register
-        EP1R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 2 register
-        EP2R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 3 register
-        EP3R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 4 register
-        EP4R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 5 register
-        EP5R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 6 register
-        EP6R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 7 register
-        EP7R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        reserved64: [32]u8,
-        ///  control register
-        CNTR: mmio.Mmio(packed struct(u32) {
-            ///  Force USB Reset
-            FRES: u1,
-            ///  Power down
-            PDWN: u1,
-            ///  Low-power mode
-            LPMODE: u1,
-            ///  Force suspend
-            FSUSP: u1,
-            ///  Resume request
-            RESUME: u1,
-            reserved8: u3,
-            ///  Expected start of frame interrupt mask
-            ESOFM: u1,
-            ///  Start of frame interrupt mask
-            SOFM: u1,
-            ///  USB reset interrupt mask
-            RESETM: u1,
-            ///  Suspend mode interrupt mask
-            SUSPM: u1,
-            ///  Wakeup interrupt mask
-            WKUPM: u1,
-            ///  Error interrupt mask
-            ERRM: u1,
-            ///  Packet memory area over / underrun interrupt mask
-            PMAOVRM: u1,
-            ///  Correct transfer interrupt mask
-            CTRM: u1,
-            padding: u16,
-        }),
-        ///  interrupt status register
-        ISTR: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint Identifier
-            EP_ID: u4,
-            ///  Direction of transaction
-            DIR: u1,
-            reserved8: u3,
-            ///  Expected start frame
-            ESOF: u1,
-            ///  start of frame
-            SOF: u1,
-            ///  reset request
-            RESET: u1,
-            ///  Suspend mode request
-            SUSP: u1,
-            ///  Wakeup
-            WKUP: u1,
-            ///  Error
-            ERR: u1,
-            ///  Packet memory area over / underrun
-            PMAOVR: u1,
-            ///  Correct transfer
-            CTR: u1,
-            padding: u16,
-        }),
-        ///  frame number register
-        FNR: mmio.Mmio(packed struct(u32) {
-            ///  Frame number
-            FN: u11,
-            ///  Lost SOF
-            LSOF: u2,
-            ///  Locked
-            LCK: u1,
-            ///  Receive data - line status
-            RXDM: u1,
-            ///  Receive data + line status
-            RXDP: u1,
-            padding: u16,
-        }),
-        ///  device address
-        DADDR: mmio.Mmio(packed struct(u32) {
-            ///  Device address
-            ADD: u7,
-            ///  Enable function
-            EF: u1,
-            padding: u24,
-        }),
-        ///  Buffer table address
-        BTABLE: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Buffer table
-            BTABLE: u13,
-            padding: u16,
-        }),
-    };
-
-    ///  Basic timer
-    pub const TIM6 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            reserved7: u3,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            padding: u24,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  Master mode selection
-            MMS: u3,
-            padding: u25,
-        }),
-        reserved12: [4]u8,
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            reserved8: u7,
-            ///  Update DMA request enable
-            UDE: u1,
-            padding: u23,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            padding: u31,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            padding: u31,
-        }),
-        reserved36: [12]u8,
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  Low counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Low Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  FLASH
-    pub const FLASH = extern struct {
-        ///  Flash access control register
-        ACR: mmio.Mmio(packed struct(u32) {
-            ///  Latency
-            LATENCY: u3,
-            ///  Flash half cycle access enable
-            HLFCYA: u1,
-            ///  Prefetch buffer enable
-            PRFTBE: u1,
-            ///  Prefetch buffer status
-            PRFTBS: u1,
-            padding: u26,
-        }),
-        ///  Flash key register
-        KEYR: mmio.Mmio(packed struct(u32) {
-            ///  FPEC key
-            KEY: u32,
-        }),
-        ///  Flash option key register
-        OPTKEYR: mmio.Mmio(packed struct(u32) {
-            ///  Option byte key
-            OPTKEY: u32,
-        }),
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Busy
-            BSY: u1,
-            reserved2: u1,
-            ///  Programming error
-            PGERR: u1,
-            reserved4: u1,
-            ///  Write protection error
-            WRPRTERR: u1,
-            ///  End of operation
-            EOP: u1,
-            padding: u26,
-        }),
-        ///  Control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Programming
-            PG: u1,
-            ///  Page Erase
-            PER: u1,
-            ///  Mass Erase
-            MER: u1,
-            reserved4: u1,
-            ///  Option byte programming
-            OPTPG: u1,
-            ///  Option byte erase
-            OPTER: u1,
-            ///  Start
-            STRT: u1,
-            ///  Lock
-            LOCK: u1,
-            reserved9: u1,
-            ///  Option bytes write enable
-            OPTWRE: u1,
-            ///  Error interrupt enable
-            ERRIE: u1,
-            reserved12: u1,
-            ///  End of operation interrupt enable
-            EOPIE: u1,
-            padding: u19,
-        }),
-        ///  Flash address register
-        AR: mmio.Mmio(packed struct(u32) {
-            ///  Flash Address
-            FAR: u32,
-        }),
-        reserved28: [4]u8,
-        ///  Option byte register
-        OBR: mmio.Mmio(packed struct(u32) {
-            ///  Option byte error
-            OPTERR: u1,
-            ///  Read protection
-            RDPRT: u1,
-            ///  WDG_SW
-            WDG_SW: u1,
-            ///  nRST_STOP
-            nRST_STOP: u1,
-            ///  nRST_STDBY
-            nRST_STDBY: u1,
-            reserved10: u5,
-            ///  Data0
-            Data0: u8,
-            ///  Data1
-            Data1: u8,
-            padding: u6,
-        }),
-        ///  Write protection register
-        WRPR: mmio.Mmio(packed struct(u32) {
-            ///  Write protect
-            WRP: u32,
-        }),
-    };
-
-    ///  Inter integrated circuit
-    pub const I2C1 = extern struct {
-        ///  Control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral enable
-            PE: u1,
-            ///  SMBus mode
-            SMBUS: u1,
-            reserved3: u1,
-            ///  SMBus type
-            SMBTYPE: u1,
-            ///  ARP enable
-            ENARP: u1,
-            ///  PEC enable
-            ENPEC: u1,
-            ///  General call enable
-            ENGC: u1,
-            ///  Clock stretching disable (Slave mode)
-            NOSTRETCH: u1,
-            ///  Start generation
-            START: u1,
-            ///  Stop generation
-            STOP: u1,
-            ///  Acknowledge enable
-            ACK: u1,
-            ///  Acknowledge/PEC Position (for data reception)
-            POS: u1,
-            ///  Packet error checking
-            PEC: u1,
-            ///  SMBus alert
-            ALERT: u1,
-            reserved15: u1,
-            ///  Software reset
-            SWRST: u1,
-            padding: u16,
-        }),
-        ///  Control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral clock frequency
-            FREQ: u6,
-            reserved8: u2,
-            ///  Error interrupt enable
-            ITERREN: u1,
-            ///  Event interrupt enable
-            ITEVTEN: u1,
-            ///  Buffer interrupt enable
-            ITBUFEN: u1,
-            ///  DMA requests enable
-            DMAEN: u1,
-            ///  DMA last transfer
-            LAST: u1,
-            padding: u19,
-        }),
-        ///  Own address register 1
-        OAR1: mmio.Mmio(packed struct(u32) {
-            ///  Interface address
-            ADD0: u1,
-            ///  Interface address
-            ADD7: u7,
-            ///  Interface address
-            ADD10: u2,
-            reserved15: u5,
-            ///  Addressing mode (slave mode)
-            ADDMODE: u1,
-            padding: u16,
-        }),
-        ///  Own address register 2
-        OAR2: mmio.Mmio(packed struct(u32) {
-            ///  Dual addressing mode enable
-            ENDUAL: u1,
-            ///  Interface address
-            ADD2: u7,
-            padding: u24,
-        }),
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  8-bit data register
-            DR: u8,
-            padding: u24,
-        }),
-        ///  Status register 1
-        SR1: mmio.Mmio(packed struct(u32) {
-            ///  Start bit (Master mode)
-            SB: u1,
-            ///  Address sent (master mode)/matched (slave mode)
-            ADDR: u1,
-            ///  Byte transfer finished
-            BTF: u1,
-            ///  10-bit header sent (Master mode)
-            ADD10: u1,
-            ///  Stop detection (slave mode)
-            STOPF: u1,
-            reserved6: u1,
-            ///  Data register not empty (receivers)
-            RxNE: u1,
-            ///  Data register empty (transmitters)
-            TxE: u1,
-            ///  Bus error
-            BERR: u1,
-            ///  Arbitration lost (master mode)
-            ARLO: u1,
-            ///  Acknowledge failure
-            AF: u1,
-            ///  Overrun/Underrun
-            OVR: u1,
-            ///  PEC Error in reception
-            PECERR: u1,
-            reserved14: u1,
-            ///  Timeout or Tlow error
-            TIMEOUT: u1,
-            ///  SMBus alert
-            SMBALERT: u1,
-            padding: u16,
-        }),
-        ///  Status register 2
-        SR2: mmio.Mmio(packed struct(u32) {
-            ///  Master/slave
-            MSL: u1,
-            ///  Bus busy
-            BUSY: u1,
-            ///  Transmitter/receiver
-            TRA: u1,
-            reserved4: u1,
-            ///  General call address (Slave mode)
-            GENCALL: u1,
-            ///  SMBus device default address (Slave mode)
-            SMBDEFAULT: u1,
-            ///  SMBus host header (Slave mode)
-            SMBHOST: u1,
-            ///  Dual flag (Slave mode)
-            DUALF: u1,
-            ///  acket error checking register
-            PEC: u8,
-            padding: u16,
-        }),
-        ///  Clock control register
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Clock control register in Fast/Standard mode (Master mode)
-            CCR: u12,
-            reserved14: u2,
-            ///  Fast mode duty cycle
-            DUTY: u1,
-            ///  I2C master mode selection
-            F_S: u1,
-            padding: u16,
-        }),
-        ///  TRISE register
-        TRISE: mmio.Mmio(packed struct(u32) {
-            ///  Maximum rise time in Fast/Standard mode (Master mode)
-            TRISE: u6,
-            padding: u26,
-        }),
-    };
-
-    ///  CRC calculation unit
-    pub const CRC = extern struct {
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data Register
-            DR: u32,
-        }),
-        ///  Independent Data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Independent Data register
-            IDR: u8,
-            padding: u24,
-        }),
-        ///  Control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Reset bit
-            RESET: u1,
-            padding: u31,
-        }),
-    };
-
-    ///  Serial peripheral interface
-    pub const SPI1 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Clock phase
-            CPHA: u1,
-            ///  Clock polarity
-            CPOL: u1,
-            ///  Master selection
-            MSTR: u1,
-            ///  Baud rate control
-            BR: u3,
-            ///  SPI enable
-            SPE: u1,
-            ///  Frame format
-            LSBFIRST: u1,
-            ///  Internal slave select
-            SSI: u1,
-            ///  Software slave management
-            SSM: u1,
-            ///  Receive only
-            RXONLY: u1,
-            ///  Data frame format
-            DFF: u1,
-            ///  CRC transfer next
-            CRCNEXT: u1,
-            ///  Hardware CRC calculation enable
-            CRCEN: u1,
-            ///  Output enable in bidirectional mode
-            BIDIOE: u1,
-            ///  Bidirectional data mode enable
-            BIDIMODE: u1,
-            padding: u16,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Rx buffer DMA enable
-            RXDMAEN: u1,
-            ///  Tx buffer DMA enable
-            TXDMAEN: u1,
-            ///  SS output enable
-            SSOE: u1,
-            reserved5: u2,
-            ///  Error interrupt enable
-            ERRIE: u1,
-            ///  RX buffer not empty interrupt enable
-            RXNEIE: u1,
-            ///  Tx buffer empty interrupt enable
-            TXEIE: u1,
-            padding: u24,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Receive buffer not empty
-            RXNE: u1,
-            ///  Transmit buffer empty
-            TXE: u1,
-            ///  Channel side
-            CHSIDE: u1,
-            ///  Underrun flag
-            UDR: u1,
-            ///  CRC error flag
-            CRCERR: u1,
-            ///  Mode fault
-            MODF: u1,
-            ///  Overrun flag
-            OVR: u1,
-            ///  Busy flag
-            BSY: u1,
-            padding: u24,
-        }),
-        ///  data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data register
-            DR: u16,
-            padding: u16,
-        }),
-        ///  CRC polynomial register
-        CRCPR: mmio.Mmio(packed struct(u32) {
-            ///  CRC polynomial register
-            CRCPOLY: u16,
-            padding: u16,
-        }),
-        ///  RX CRC register
-        RXCRCR: mmio.Mmio(packed struct(u32) {
-            ///  Rx CRC register
-            RxCRC: u16,
-            padding: u16,
-        }),
-        ///  TX CRC register
-        TXCRCR: mmio.Mmio(packed struct(u32) {
-            ///  Tx CRC register
-            TxCRC: u16,
-            padding: u16,
-        }),
-        ///  I2S configuration register
-        I2SCFGR: mmio.Mmio(packed struct(u32) {
-            ///  Channel length (number of bits per audio channel)
-            CHLEN: u1,
-            ///  Data length to be transferred
-            DATLEN: u2,
-            ///  Steady state clock polarity
-            CKPOL: u1,
-            ///  I2S standard selection
-            I2SSTD: u2,
-            reserved7: u1,
-            ///  PCM frame synchronization
-            PCMSYNC: u1,
-            ///  I2S configuration mode
-            I2SCFG: u2,
-            ///  I2S Enable
-            I2SE: u1,
-            ///  I2S mode selection
-            I2SMOD: u1,
-            padding: u20,
-        }),
-        ///  I2S prescaler register
-        I2SPR: mmio.Mmio(packed struct(u32) {
-            ///  I2S Linear prescaler
-            I2SDIV: u8,
-            ///  Odd factor for the prescaler
-            ODD: u1,
-            ///  Master clock output enable
-            MCKOE: u1,
-            padding: u22,
-        }),
-    };
-
-    ///  Universal asynchronous receiver transmitter
-    pub const UART5 = extern struct {
-        ///  UART4_SR
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  PE
-            PE: u1,
-            ///  FE
-            FE: u1,
-            ///  NE
-            NE: u1,
-            ///  ORE
-            ORE: u1,
-            ///  IDLE
-            IDLE: u1,
-            ///  RXNE
-            RXNE: u1,
-            ///  TC
-            TC: u1,
-            ///  TXE
-            TXE: u1,
-            ///  LBD
-            LBD: u1,
-            padding: u23,
-        }),
-        ///  UART4_DR
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  DR
-            DR: u9,
-            padding: u23,
-        }),
-        ///  UART4_BRR
-        BRR: mmio.Mmio(packed struct(u32) {
-            ///  DIV_Fraction
-            DIV_Fraction: u4,
-            ///  DIV_Mantissa
-            DIV_Mantissa: u12,
-            padding: u16,
-        }),
-        ///  UART4_CR1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  SBK
-            SBK: u1,
-            ///  RWU
-            RWU: u1,
-            ///  RE
-            RE: u1,
-            ///  TE
-            TE: u1,
-            ///  IDLEIE
-            IDLEIE: u1,
-            ///  RXNEIE
-            RXNEIE: u1,
-            ///  TCIE
-            TCIE: u1,
-            ///  TXEIE
-            TXEIE: u1,
-            ///  PEIE
-            PEIE: u1,
-            ///  PS
-            PS: u1,
-            ///  PCE
-            PCE: u1,
-            ///  WAKE
-            WAKE: u1,
-            ///  M
-            M: u1,
-            ///  UE
-            UE: u1,
-            padding: u18,
-        }),
-        ///  UART4_CR2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  ADD
-            ADD: u4,
-            reserved5: u1,
-            ///  LBDL
-            LBDL: u1,
-            ///  LBDIE
-            LBDIE: u1,
-            reserved12: u5,
-            ///  STOP
-            STOP: u2,
-            ///  LINEN
-            LINEN: u1,
-            padding: u17,
-        }),
-        ///  UART4_CR3
-        CR3: mmio.Mmio(packed struct(u32) {
-            ///  Error interrupt enable
-            EIE: u1,
-            ///  IrDA mode enable
-            IREN: u1,
-            ///  IrDA low-power
-            IRLP: u1,
-            ///  Half-duplex selection
-            HDSEL: u1,
-            reserved7: u3,
-            ///  DMA enable transmitter
-            DMAT: u1,
-            padding: u24,
-        }),
-    };
-
-    ///  Universal asynchronous receiver transmitter
-    pub const UART4 = extern struct {
-        ///  UART4_SR
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Parity error
-            PE: u1,
-            ///  Framing error
-            FE: u1,
-            ///  Noise error flag
-            NE: u1,
-            ///  Overrun error
-            ORE: u1,
-            ///  IDLE line detected
-            IDLE: u1,
-            ///  Read data register not empty
-            RXNE: u1,
-            ///  Transmission complete
-            TC: u1,
-            ///  Transmit data register empty
-            TXE: u1,
-            ///  LIN break detection flag
-            LBD: u1,
-            padding: u23,
-        }),
-        ///  UART4_DR
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  DR
-            DR: u9,
-            padding: u23,
-        }),
-        ///  UART4_BRR
-        BRR: mmio.Mmio(packed struct(u32) {
-            ///  DIV_Fraction
-            DIV_Fraction: u4,
-            ///  DIV_Mantissa
-            DIV_Mantissa: u12,
-            padding: u16,
-        }),
-        ///  UART4_CR1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Send break
-            SBK: u1,
-            ///  Receiver wakeup
-            RWU: u1,
-            ///  Receiver enable
-            RE: u1,
-            ///  Transmitter enable
-            TE: u1,
-            ///  IDLE interrupt enable
-            IDLEIE: u1,
-            ///  RXNE interrupt enable
-            RXNEIE: u1,
-            ///  Transmission complete interrupt enable
-            TCIE: u1,
-            ///  TXE interrupt enable
-            TXEIE: u1,
-            ///  PE interrupt enable
-            PEIE: u1,
-            ///  Parity selection
-            PS: u1,
-            ///  Parity control enable
-            PCE: u1,
-            ///  Wakeup method
-            WAKE: u1,
-            ///  Word length
-            M: u1,
-            ///  USART enable
-            UE: u1,
-            padding: u18,
-        }),
-        ///  UART4_CR2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Address of the USART node
-            ADD: u4,
-            reserved5: u1,
-            ///  lin break detection length
-            LBDL: u1,
-            ///  LIN break detection interrupt enable
-            LBDIE: u1,
-            reserved12: u5,
-            ///  STOP bits
-            STOP: u2,
-            ///  LIN mode enable
-            LINEN: u1,
-            padding: u17,
-        }),
-        ///  UART4_CR3
-        CR3: mmio.Mmio(packed struct(u32) {
-            ///  Error interrupt enable
-            EIE: u1,
-            ///  IrDA mode enable
-            IREN: u1,
-            ///  IrDA low-power
-            IRLP: u1,
-            ///  Half-duplex selection
-            HDSEL: u1,
-            reserved6: u2,
-            ///  DMA enable receiver
-            DMAR: u1,
-            ///  DMA enable transmitter
-            DMAT: u1,
-            padding: u24,
-        }),
-    };
-
-    ///  Universal synchronous asynchronous receiver transmitter
-    pub const USART1 = extern struct {
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Parity error
-            PE: u1,
-            ///  Framing error
-            FE: u1,
-            ///  Noise error flag
-            NE: u1,
-            ///  Overrun error
-            ORE: u1,
-            ///  IDLE line detected
-            IDLE: u1,
-            ///  Read data register not empty
-            RXNE: u1,
-            ///  Transmission complete
-            TC: u1,
-            ///  Transmit data register empty
-            TXE: u1,
-            ///  LIN break detection flag
-            LBD: u1,
-            ///  CTS flag
-            CTS: u1,
-            padding: u22,
-        }),
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data value
-            DR: u9,
-            padding: u23,
-        }),
-        ///  Baud rate register
-        BRR: mmio.Mmio(packed struct(u32) {
-            ///  fraction of USARTDIV
-            DIV_Fraction: u4,
-            ///  mantissa of USARTDIV
-            DIV_Mantissa: u12,
-            padding: u16,
-        }),
-        ///  Control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Send break
-            SBK: u1,
-            ///  Receiver wakeup
-            RWU: u1,
-            ///  Receiver enable
-            RE: u1,
-            ///  Transmitter enable
-            TE: u1,
-            ///  IDLE interrupt enable
-            IDLEIE: u1,
-            ///  RXNE interrupt enable
-            RXNEIE: u1,
-            ///  Transmission complete interrupt enable
-            TCIE: u1,
-            ///  TXE interrupt enable
-            TXEIE: u1,
-            ///  PE interrupt enable
-            PEIE: u1,
-            ///  Parity selection
-            PS: u1,
-            ///  Parity control enable
-            PCE: u1,
-            ///  Wakeup method
-            WAKE: u1,
-            ///  Word length
-            M: u1,
-            ///  USART enable
-            UE: u1,
-            padding: u18,
-        }),
-        ///  Control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Address of the USART node
-            ADD: u4,
-            reserved5: u1,
-            ///  lin break detection length
-            LBDL: u1,
-            ///  LIN break detection interrupt enable
-            LBDIE: u1,
-            reserved8: u1,
-            ///  Last bit clock pulse
-            LBCL: u1,
-            ///  Clock phase
-            CPHA: u1,
-            ///  Clock polarity
-            CPOL: u1,
-            ///  Clock enable
-            CLKEN: u1,
-            ///  STOP bits
-            STOP: u2,
-            ///  LIN mode enable
-            LINEN: u1,
-            padding: u17,
-        }),
-        ///  Control register 3
-        CR3: mmio.Mmio(packed struct(u32) {
-            ///  Error interrupt enable
-            EIE: u1,
-            ///  IrDA mode enable
-            IREN: u1,
-            ///  IrDA low-power
-            IRLP: u1,
-            ///  Half-duplex selection
-            HDSEL: u1,
-            ///  Smartcard NACK enable
-            NACK: u1,
-            ///  Smartcard mode enable
-            SCEN: u1,
-            ///  DMA enable receiver
-            DMAR: u1,
-            ///  DMA enable transmitter
-            DMAT: u1,
-            ///  RTS enable
-            RTSE: u1,
-            ///  CTS enable
-            CTSE: u1,
-            ///  CTS interrupt enable
-            CTSIE: u1,
-            padding: u21,
-        }),
-        ///  Guard time and prescaler register
-        GTPR: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u8,
-            ///  Guard time value
-            GT: u8,
-            padding: u16,
-        }),
-    };
-
-    ///  Debug support
-    pub const DBG = extern struct {
-        ///  DBGMCU_IDCODE
-        IDCODE: mmio.Mmio(packed struct(u32) {
-            ///  DEV_ID
-            DEV_ID: u12,
-            reserved16: u4,
-            ///  REV_ID
-            REV_ID: u16,
-        }),
-        ///  DBGMCU_CR
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  DBG_SLEEP
-            DBG_SLEEP: u1,
-            ///  DBG_STOP
-            DBG_STOP: u1,
-            ///  DBG_STANDBY
-            DBG_STANDBY: u1,
-            reserved5: u2,
-            ///  TRACE_IOEN
-            TRACE_IOEN: u1,
-            ///  TRACE_MODE
-            TRACE_MODE: u2,
-            ///  DBG_IWDG_STOP
-            DBG_IWDG_STOP: u1,
-            ///  DBG_WWDG_STOP
-            DBG_WWDG_STOP: u1,
-            ///  DBG_TIM1_STOP
-            DBG_TIM1_STOP: u1,
-            ///  DBG_TIM2_STOP
-            DBG_TIM2_STOP: u1,
-            ///  DBG_TIM3_STOP
-            DBG_TIM3_STOP: u1,
-            ///  DBG_TIM4_STOP
-            DBG_TIM4_STOP: u1,
-            ///  DBG_CAN1_STOP
-            DBG_CAN1_STOP: u1,
-            ///  DBG_I2C1_SMBUS_TIMEOUT
-            DBG_I2C1_SMBUS_TIMEOUT: u1,
-            ///  DBG_I2C2_SMBUS_TIMEOUT
-            DBG_I2C2_SMBUS_TIMEOUT: u1,
-            ///  DBG_TIM8_STOP
-            DBG_TIM8_STOP: u1,
-            ///  DBG_TIM5_STOP
-            DBG_TIM5_STOP: u1,
-            ///  DBG_TIM6_STOP
-            DBG_TIM6_STOP: u1,
-            ///  DBG_TIM7_STOP
-            DBG_TIM7_STOP: u1,
-            ///  DBG_CAN2_STOP
-            DBG_CAN2_STOP: u1,
-            padding: u10,
-        }),
-    };
-
-    ///  Digital to analog converter
-    pub const DAC = extern struct {
-        ///  Control register (DAC_CR)
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 enable
-            EN1: u1,
-            ///  DAC channel1 output buffer disable
-            BOFF1: u1,
-            ///  DAC channel1 trigger enable
-            TEN1: u1,
-            ///  DAC channel1 trigger selection
-            TSEL1: u3,
-            ///  DAC channel1 noise/triangle wave generation enable
-            WAVE1: u2,
-            ///  DAC channel1 mask/amplitude selector
-            MAMP1: u4,
-            ///  DAC channel1 DMA enable
-            DMAEN1: u1,
-            reserved16: u3,
-            ///  DAC channel2 enable
-            EN2: u1,
-            ///  DAC channel2 output buffer disable
-            BOFF2: u1,
-            ///  DAC channel2 trigger enable
-            TEN2: u1,
-            ///  DAC channel2 trigger selection
-            TSEL2: u3,
-            ///  DAC channel2 noise/triangle wave generation enable
-            WAVE2: u2,
-            ///  DAC channel2 mask/amplitude selector
-            MAMP2: u4,
-            ///  DAC channel2 DMA enable
-            DMAEN2: u1,
-            padding: u3,
-        }),
-        ///  DAC software trigger register (DAC_SWTRIGR)
-        SWTRIGR: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 software trigger
-            SWTRIG1: u1,
-            ///  DAC channel2 software trigger
-            SWTRIG2: u1,
-            padding: u30,
-        }),
-        ///  DAC channel1 12-bit right-aligned data holding register(DAC_DHR12R1)
-        DHR12R1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 12-bit right-aligned data
-            DACC1DHR: u12,
-            padding: u20,
-        }),
-        ///  DAC channel1 12-bit left aligned data holding register (DAC_DHR12L1)
-        DHR12L1: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel1 12-bit left-aligned data
-            DACC1DHR: u12,
-            padding: u16,
-        }),
-        ///  DAC channel1 8-bit right aligned data holding register (DAC_DHR8R1)
-        DHR8R1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 8-bit right-aligned data
-            DACC1DHR: u8,
-            padding: u24,
-        }),
-        ///  DAC channel2 12-bit right aligned data holding register (DAC_DHR12R2)
-        DHR12R2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 12-bit right-aligned data
-            DACC2DHR: u12,
-            padding: u20,
-        }),
-        ///  DAC channel2 12-bit left aligned data holding register (DAC_DHR12L2)
-        DHR12L2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel2 12-bit left-aligned data
-            DACC2DHR: u12,
-            padding: u16,
-        }),
-        ///  DAC channel2 8-bit right-aligned data holding register (DAC_DHR8R2)
-        DHR8R2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 8-bit right-aligned data
-            DACC2DHR: u8,
-            padding: u24,
-        }),
-        ///  Dual DAC 12-bit right-aligned data holding register (DAC_DHR12RD), Bits 31:28 Reserved, Bits 15:12 Reserved
-        DHR12RD: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 12-bit right-aligned data
-            DACC1DHR: u12,
-            reserved16: u4,
-            ///  DAC channel2 12-bit right-aligned data
-            DACC2DHR: u12,
-            padding: u4,
-        }),
-        ///  DUAL DAC 12-bit left aligned data holding register (DAC_DHR12LD), Bits 19:16 Reserved, Bits 3:0 Reserved
-        DHR12LD: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel1 12-bit left-aligned data
-            DACC1DHR: u12,
-            reserved20: u4,
-            ///  DAC channel2 12-bit right-aligned data
-            DACC2DHR: u12,
-        }),
-        ///  DUAL DAC 8-bit right aligned data holding register (DAC_DHR8RD), Bits 31:16 Reserved
-        DHR8RD: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 8-bit right-aligned data
-            DACC1DHR: u8,
-            ///  DAC channel2 8-bit right-aligned data
-            DACC2DHR: u8,
-            padding: u16,
-        }),
-        ///  DAC channel1 data output register (DAC_DOR1)
-        DOR1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 data output
-            DACC1DOR: u12,
-            padding: u20,
-        }),
-        ///  DAC channel2 data output register (DAC_DOR2)
-        DOR2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 data output
-            DACC2DOR: u12,
-            padding: u20,
-        }),
-    };
-
-    ///  Analog to digital converter
-    pub const ADC1 = extern struct {
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog flag
-            AWD: u1,
-            ///  Regular channel end of conversion
-            EOC: u1,
-            ///  Injected channel end of conversion
-            JEOC: u1,
-            ///  Injected channel start flag
-            JSTRT: u1,
-            ///  Regular channel start flag
-            STRT: u1,
-            padding: u27,
-        }),
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog channel select bits
-            AWDCH: u5,
-            ///  Interrupt enable for EOC
-            EOCIE: u1,
-            ///  Analog watchdog interrupt enable
-            AWDIE: u1,
-            ///  Interrupt enable for injected channels
-            JEOCIE: u1,
-            ///  Scan mode
-            SCAN: u1,
-            ///  Enable the watchdog on a single channel in scan mode
-            AWDSGL: u1,
-            ///  Automatic injected group conversion
-            JAUTO: u1,
-            ///  Discontinuous mode on regular channels
-            DISCEN: u1,
-            ///  Discontinuous mode on injected channels
-            JDISCEN: u1,
-            ///  Discontinuous mode channel count
-            DISCNUM: u3,
-            ///  Dual mode selection
-            DUALMOD: u4,
-            reserved22: u2,
-            ///  Analog watchdog enable on injected channels
-            JAWDEN: u1,
-            ///  Analog watchdog enable on regular channels
-            AWDEN: u1,
-            padding: u8,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  A/D converter ON / OFF
-            ADON: u1,
-            ///  Continuous conversion
-            CONT: u1,
-            ///  A/D calibration
-            CAL: u1,
-            ///  Reset calibration
-            RSTCAL: u1,
-            reserved8: u4,
-            ///  Direct memory access mode
-            DMA: u1,
-            reserved11: u2,
-            ///  Data alignment
-            ALIGN: u1,
-            ///  External event select for injected group
-            JEXTSEL: u3,
-            ///  External trigger conversion mode for injected channels
-            JEXTTRIG: u1,
-            reserved17: u1,
-            ///  External event select for regular group
-            EXTSEL: u3,
-            ///  External trigger conversion mode for regular channels
-            EXTTRIG: u1,
-            ///  Start conversion of injected channels
-            JSWSTART: u1,
-            ///  Start conversion of regular channels
-            SWSTART: u1,
-            ///  Temperature sensor and VREFINT enable
-            TSVREFE: u1,
-            padding: u8,
-        }),
-        ///  sample time register 1
-        SMPR1: mmio.Mmio(packed struct(u32) {
-            ///  Channel 10 sample time selection
-            SMP10: u3,
-            ///  Channel 11 sample time selection
-            SMP11: u3,
-            ///  Channel 12 sample time selection
-            SMP12: u3,
-            ///  Channel 13 sample time selection
-            SMP13: u3,
-            ///  Channel 14 sample time selection
-            SMP14: u3,
-            ///  Channel 15 sample time selection
-            SMP15: u3,
-            ///  Channel 16 sample time selection
-            SMP16: u3,
-            ///  Channel 17 sample time selection
-            SMP17: u3,
-            padding: u8,
-        }),
-        ///  sample time register 2
-        SMPR2: mmio.Mmio(packed struct(u32) {
-            ///  Channel 0 sample time selection
-            SMP0: u3,
-            ///  Channel 1 sample time selection
-            SMP1: u3,
-            ///  Channel 2 sample time selection
-            SMP2: u3,
-            ///  Channel 3 sample time selection
-            SMP3: u3,
-            ///  Channel 4 sample time selection
-            SMP4: u3,
-            ///  Channel 5 sample time selection
-            SMP5: u3,
-            ///  Channel 6 sample time selection
-            SMP6: u3,
-            ///  Channel 7 sample time selection
-            SMP7: u3,
-            ///  Channel 8 sample time selection
-            SMP8: u3,
-            ///  Channel 9 sample time selection
-            SMP9: u3,
-            padding: u2,
-        }),
-        ///  injected channel data offset register x
-        JOFR1: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET1: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR2: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET2: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR3: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET3: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR4: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET4: u12,
-            padding: u20,
-        }),
-        ///  watchdog higher threshold register
-        HTR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog higher threshold
-            HT: u12,
-            padding: u20,
-        }),
-        ///  watchdog lower threshold register
-        LTR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog lower threshold
-            LT: u12,
-            padding: u20,
-        }),
-        ///  regular sequence register 1
-        SQR1: mmio.Mmio(packed struct(u32) {
-            ///  13th conversion in regular sequence
-            SQ13: u5,
-            ///  14th conversion in regular sequence
-            SQ14: u5,
-            ///  15th conversion in regular sequence
-            SQ15: u5,
-            ///  16th conversion in regular sequence
-            SQ16: u5,
-            ///  Regular channel sequence length
-            L: u4,
-            padding: u8,
-        }),
-        ///  regular sequence register 2
-        SQR2: mmio.Mmio(packed struct(u32) {
-            ///  7th conversion in regular sequence
-            SQ7: u5,
-            ///  8th conversion in regular sequence
-            SQ8: u5,
-            ///  9th conversion in regular sequence
-            SQ9: u5,
-            ///  10th conversion in regular sequence
-            SQ10: u5,
-            ///  11th conversion in regular sequence
-            SQ11: u5,
-            ///  12th conversion in regular sequence
-            SQ12: u5,
-            padding: u2,
-        }),
-        ///  regular sequence register 3
-        SQR3: mmio.Mmio(packed struct(u32) {
-            ///  1st conversion in regular sequence
-            SQ1: u5,
-            ///  2nd conversion in regular sequence
-            SQ2: u5,
-            ///  3rd conversion in regular sequence
-            SQ3: u5,
-            ///  4th conversion in regular sequence
-            SQ4: u5,
-            ///  5th conversion in regular sequence
-            SQ5: u5,
-            ///  6th conversion in regular sequence
-            SQ6: u5,
-            padding: u2,
-        }),
-        ///  injected sequence register
-        JSQR: mmio.Mmio(packed struct(u32) {
-            ///  1st conversion in injected sequence
-            JSQ1: u5,
-            ///  2nd conversion in injected sequence
-            JSQ2: u5,
-            ///  3rd conversion in injected sequence
-            JSQ3: u5,
-            ///  4th conversion in injected sequence
-            JSQ4: u5,
-            ///  Injected sequence length
-            JL: u2,
-            padding: u10,
-        }),
-        ///  injected data register x
-        JDR1: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR2: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR3: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR4: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  regular data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Regular data
-            DATA: u16,
-            ///  ADC2 data
-            ADC2DATA: u16,
-        }),
-    };
-
-    ///  Analog to digital converter
-    pub const ADC2 = extern struct {
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog flag
-            AWD: u1,
-            ///  Regular channel end of conversion
-            EOC: u1,
-            ///  Injected channel end of conversion
-            JEOC: u1,
-            ///  Injected channel start flag
-            JSTRT: u1,
-            ///  Regular channel start flag
-            STRT: u1,
-            padding: u27,
-        }),
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog channel select bits
-            AWDCH: u5,
-            ///  Interrupt enable for EOC
-            EOCIE: u1,
-            ///  Analog watchdog interrupt enable
-            AWDIE: u1,
-            ///  Interrupt enable for injected channels
-            JEOCIE: u1,
-            ///  Scan mode
-            SCAN: u1,
-            ///  Enable the watchdog on a single channel in scan mode
-            AWDSGL: u1,
-            ///  Automatic injected group conversion
-            JAUTO: u1,
-            ///  Discontinuous mode on regular channels
-            DISCEN: u1,
-            ///  Discontinuous mode on injected channels
-            JDISCEN: u1,
-            ///  Discontinuous mode channel count
-            DISCNUM: u3,
-            reserved22: u6,
-            ///  Analog watchdog enable on injected channels
-            JAWDEN: u1,
-            ///  Analog watchdog enable on regular channels
-            AWDEN: u1,
-            padding: u8,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  A/D converter ON / OFF
-            ADON: u1,
-            ///  Continuous conversion
-            CONT: u1,
-            ///  A/D calibration
-            CAL: u1,
-            ///  Reset calibration
-            RSTCAL: u1,
-            reserved8: u4,
-            ///  Direct memory access mode
-            DMA: u1,
-            reserved11: u2,
-            ///  Data alignment
-            ALIGN: u1,
-            ///  External event select for injected group
-            JEXTSEL: u3,
-            ///  External trigger conversion mode for injected channels
-            JEXTTRIG: u1,
-            reserved17: u1,
-            ///  External event select for regular group
-            EXTSEL: u3,
-            ///  External trigger conversion mode for regular channels
-            EXTTRIG: u1,
-            ///  Start conversion of injected channels
-            JSWSTART: u1,
-            ///  Start conversion of regular channels
-            SWSTART: u1,
-            ///  Temperature sensor and VREFINT enable
-            TSVREFE: u1,
-            padding: u8,
-        }),
-        ///  sample time register 1
-        SMPR1: mmio.Mmio(packed struct(u32) {
-            ///  Channel 10 sample time selection
-            SMP10: u3,
-            ///  Channel 11 sample time selection
-            SMP11: u3,
-            ///  Channel 12 sample time selection
-            SMP12: u3,
-            ///  Channel 13 sample time selection
-            SMP13: u3,
-            ///  Channel 14 sample time selection
-            SMP14: u3,
-            ///  Channel 15 sample time selection
-            SMP15: u3,
-            ///  Channel 16 sample time selection
-            SMP16: u3,
-            ///  Channel 17 sample time selection
-            SMP17: u3,
-            padding: u8,
-        }),
-        ///  sample time register 2
-        SMPR2: mmio.Mmio(packed struct(u32) {
-            ///  Channel 0 sample time selection
-            SMP0: u3,
-            ///  Channel 1 sample time selection
-            SMP1: u3,
-            ///  Channel 2 sample time selection
-            SMP2: u3,
-            ///  Channel 3 sample time selection
-            SMP3: u3,
-            ///  Channel 4 sample time selection
-            SMP4: u3,
-            ///  Channel 5 sample time selection
-            SMP5: u3,
-            ///  Channel 6 sample time selection
-            SMP6: u3,
-            ///  Channel 7 sample time selection
-            SMP7: u3,
-            ///  Channel 8 sample time selection
-            SMP8: u3,
-            ///  Channel 9 sample time selection
-            SMP9: u3,
-            padding: u2,
-        }),
-        ///  injected channel data offset register x
-        JOFR1: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET1: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR2: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET2: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR3: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET3: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR4: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET4: u12,
-            padding: u20,
-        }),
-        ///  watchdog higher threshold register
-        HTR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog higher threshold
-            HT: u12,
-            padding: u20,
-        }),
-        ///  watchdog lower threshold register
-        LTR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog lower threshold
-            LT: u12,
-            padding: u20,
-        }),
-        ///  regular sequence register 1
-        SQR1: mmio.Mmio(packed struct(u32) {
-            ///  13th conversion in regular sequence
-            SQ13: u5,
-            ///  14th conversion in regular sequence
-            SQ14: u5,
-            ///  15th conversion in regular sequence
-            SQ15: u5,
-            ///  16th conversion in regular sequence
-            SQ16: u5,
-            ///  Regular channel sequence length
-            L: u4,
-            padding: u8,
-        }),
-        ///  regular sequence register 2
-        SQR2: mmio.Mmio(packed struct(u32) {
-            ///  7th conversion in regular sequence
-            SQ7: u5,
-            ///  8th conversion in regular sequence
-            SQ8: u5,
-            ///  9th conversion in regular sequence
-            SQ9: u5,
-            ///  10th conversion in regular sequence
-            SQ10: u5,
-            ///  11th conversion in regular sequence
-            SQ11: u5,
-            ///  12th conversion in regular sequence
-            SQ12: u5,
-            padding: u2,
-        }),
-        ///  regular sequence register 3
-        SQR3: mmio.Mmio(packed struct(u32) {
-            ///  1st conversion in regular sequence
-            SQ1: u5,
-            ///  2nd conversion in regular sequence
-            SQ2: u5,
-            ///  3rd conversion in regular sequence
-            SQ3: u5,
-            ///  4th conversion in regular sequence
-            SQ4: u5,
-            ///  5th conversion in regular sequence
-            SQ5: u5,
-            ///  6th conversion in regular sequence
-            SQ6: u5,
-            padding: u2,
-        }),
-        ///  injected sequence register
-        JSQR: mmio.Mmio(packed struct(u32) {
-            ///  1st conversion in injected sequence
-            JSQ1: u5,
-            ///  2nd conversion in injected sequence
-            JSQ2: u5,
-            ///  3rd conversion in injected sequence
-            JSQ3: u5,
-            ///  4th conversion in injected sequence
-            JSQ4: u5,
-            ///  Injected sequence length
-            JL: u2,
-            padding: u10,
-        }),
-        ///  injected data register x
-        JDR1: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR2: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR3: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR4: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  regular data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Regular data
-            DATA: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Controller area network
-    pub const CAN1 = extern struct {
-        ///  CAN_MCR
-        CAN_MCR: mmio.Mmio(packed struct(u32) {
-            ///  INRQ
-            INRQ: u1,
-            ///  SLEEP
-            SLEEP: u1,
-            ///  TXFP
-            TXFP: u1,
-            ///  RFLM
-            RFLM: u1,
-            ///  NART
-            NART: u1,
-            ///  AWUM
-            AWUM: u1,
-            ///  ABOM
-            ABOM: u1,
-            ///  TTCM
-            TTCM: u1,
-            reserved15: u7,
-            ///  RESET
-            RESET: u1,
-            ///  DBF
-            DBF: u1,
-            padding: u15,
-        }),
-        ///  CAN_MSR
-        CAN_MSR: mmio.Mmio(packed struct(u32) {
-            ///  INAK
-            INAK: u1,
-            ///  SLAK
-            SLAK: u1,
-            ///  ERRI
-            ERRI: u1,
-            ///  WKUI
-            WKUI: u1,
-            ///  SLAKI
-            SLAKI: u1,
-            reserved8: u3,
-            ///  TXM
-            TXM: u1,
-            ///  RXM
-            RXM: u1,
-            ///  SAMP
-            SAMP: u1,
-            ///  RX
-            RX: u1,
-            padding: u20,
-        }),
-        ///  CAN_TSR
-        CAN_TSR: mmio.Mmio(packed struct(u32) {
-            ///  RQCP0
-            RQCP0: u1,
-            ///  TXOK0
-            TXOK0: u1,
-            ///  ALST0
-            ALST0: u1,
-            ///  TERR0
-            TERR0: u1,
-            reserved7: u3,
-            ///  ABRQ0
-            ABRQ0: u1,
-            ///  RQCP1
-            RQCP1: u1,
-            ///  TXOK1
-            TXOK1: u1,
-            ///  ALST1
-            ALST1: u1,
-            ///  TERR1
-            TERR1: u1,
-            reserved15: u3,
-            ///  ABRQ1
-            ABRQ1: u1,
-            ///  RQCP2
-            RQCP2: u1,
-            ///  TXOK2
-            TXOK2: u1,
-            ///  ALST2
-            ALST2: u1,
-            ///  TERR2
-            TERR2: u1,
-            reserved23: u3,
-            ///  ABRQ2
-            ABRQ2: u1,
-            ///  CODE
-            CODE: u2,
-            ///  Lowest priority flag for mailbox 0
-            TME0: u1,
-            ///  Lowest priority flag for mailbox 1
-            TME1: u1,
-            ///  Lowest priority flag for mailbox 2
-            TME2: u1,
-            ///  Lowest priority flag for mailbox 0
-            LOW0: u1,
-            ///  Lowest priority flag for mailbox 1
-            LOW1: u1,
-            ///  Lowest priority flag for mailbox 2
-            LOW2: u1,
-        }),
-        ///  CAN_RF0R
-        CAN_RF0R: mmio.Mmio(packed struct(u32) {
-            ///  FMP0
-            FMP0: u2,
-            reserved3: u1,
-            ///  FULL0
-            FULL0: u1,
-            ///  FOVR0
-            FOVR0: u1,
-            ///  RFOM0
-            RFOM0: u1,
-            padding: u26,
-        }),
-        ///  CAN_RF1R
-        CAN_RF1R: mmio.Mmio(packed struct(u32) {
-            ///  FMP1
-            FMP1: u2,
-            reserved3: u1,
-            ///  FULL1
-            FULL1: u1,
-            ///  FOVR1
-            FOVR1: u1,
-            ///  RFOM1
-            RFOM1: u1,
-            padding: u26,
-        }),
-        ///  CAN_IER
-        CAN_IER: mmio.Mmio(packed struct(u32) {
-            ///  TMEIE
-            TMEIE: u1,
-            ///  FMPIE0
-            FMPIE0: u1,
-            ///  FFIE0
-            FFIE0: u1,
-            ///  FOVIE0
-            FOVIE0: u1,
-            ///  FMPIE1
-            FMPIE1: u1,
-            ///  FFIE1
-            FFIE1: u1,
-            ///  FOVIE1
-            FOVIE1: u1,
-            reserved8: u1,
-            ///  EWGIE
-            EWGIE: u1,
-            ///  EPVIE
-            EPVIE: u1,
-            ///  BOFIE
-            BOFIE: u1,
-            ///  LECIE
-            LECIE: u1,
-            reserved15: u3,
-            ///  ERRIE
-            ERRIE: u1,
-            ///  WKUIE
-            WKUIE: u1,
-            ///  SLKIE
-            SLKIE: u1,
-            padding: u14,
-        }),
-        ///  CAN_ESR
-        CAN_ESR: mmio.Mmio(packed struct(u32) {
-            ///  EWGF
-            EWGF: u1,
-            ///  EPVF
-            EPVF: u1,
-            ///  BOFF
-            BOFF: u1,
-            reserved4: u1,
-            ///  LEC
-            LEC: u3,
-            reserved16: u9,
-            ///  TEC
-            TEC: u8,
-            ///  REC
-            REC: u8,
-        }),
-        ///  CAN_BTR
-        CAN_BTR: mmio.Mmio(packed struct(u32) {
-            ///  BRP
-            BRP: u10,
-            reserved16: u6,
-            ///  TS1
-            TS1: u4,
-            ///  TS2
-            TS2: u3,
-            reserved24: u1,
-            ///  SJW
-            SJW: u2,
-            reserved30: u4,
-            ///  LBKM
-            LBKM: u1,
-            ///  SILM
-            SILM: u1,
-        }),
-        reserved384: [352]u8,
-        ///  CAN_TI0R
-        CAN_TI0R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  CAN_TDT0R
-        CAN_TDT0R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  CAN_TDL0R
-        CAN_TDL0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  CAN_TDH0R
-        CAN_TDH0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  CAN_TI1R
-        CAN_TI1R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  CAN_TDT1R
-        CAN_TDT1R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  CAN_TDL1R
-        CAN_TDL1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  CAN_TDH1R
-        CAN_TDH1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  CAN_TI2R
-        CAN_TI2R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  CAN_TDT2R
-        CAN_TDT2R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  CAN_TDL2R
-        CAN_TDL2R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  CAN_TDH2R
-        CAN_TDH2R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  CAN_RI0R
-        CAN_RI0R: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  CAN_RDT0R
-        CAN_RDT0R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  FMI
-            FMI: u8,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  CAN_RDL0R
-        CAN_RDL0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  CAN_RDH0R
-        CAN_RDH0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  CAN_RI1R
-        CAN_RI1R: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  CAN_RDT1R
-        CAN_RDT1R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  FMI
-            FMI: u8,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  CAN_RDL1R
-        CAN_RDL1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  CAN_RDH1R
-        CAN_RDH1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        reserved512: [48]u8,
-        ///  CAN_FMR
-        CAN_FMR: mmio.Mmio(packed struct(u32) {
-            ///  FINIT
-            FINIT: u1,
-            padding: u31,
-        }),
-        ///  CAN_FM1R
-        CAN_FM1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter mode
-            FBM0: u1,
-            ///  Filter mode
-            FBM1: u1,
-            ///  Filter mode
-            FBM2: u1,
-            ///  Filter mode
-            FBM3: u1,
-            ///  Filter mode
-            FBM4: u1,
-            ///  Filter mode
-            FBM5: u1,
-            ///  Filter mode
-            FBM6: u1,
-            ///  Filter mode
-            FBM7: u1,
-            ///  Filter mode
-            FBM8: u1,
-            ///  Filter mode
-            FBM9: u1,
-            ///  Filter mode
-            FBM10: u1,
-            ///  Filter mode
-            FBM11: u1,
-            ///  Filter mode
-            FBM12: u1,
-            ///  Filter mode
-            FBM13: u1,
-            padding: u18,
-        }),
-        reserved524: [4]u8,
-        ///  CAN_FS1R
-        CAN_FS1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter scale configuration
-            FSC0: u1,
-            ///  Filter scale configuration
-            FSC1: u1,
-            ///  Filter scale configuration
-            FSC2: u1,
-            ///  Filter scale configuration
-            FSC3: u1,
-            ///  Filter scale configuration
-            FSC4: u1,
-            ///  Filter scale configuration
-            FSC5: u1,
-            ///  Filter scale configuration
-            FSC6: u1,
-            ///  Filter scale configuration
-            FSC7: u1,
-            ///  Filter scale configuration
-            FSC8: u1,
-            ///  Filter scale configuration
-            FSC9: u1,
-            ///  Filter scale configuration
-            FSC10: u1,
-            ///  Filter scale configuration
-            FSC11: u1,
-            ///  Filter scale configuration
-            FSC12: u1,
-            ///  Filter scale configuration
-            FSC13: u1,
-            padding: u18,
-        }),
-        reserved532: [4]u8,
-        ///  CAN_FFA1R
-        CAN_FFA1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter FIFO assignment for filter 0
-            FFA0: u1,
-            ///  Filter FIFO assignment for filter 1
-            FFA1: u1,
-            ///  Filter FIFO assignment for filter 2
-            FFA2: u1,
-            ///  Filter FIFO assignment for filter 3
-            FFA3: u1,
-            ///  Filter FIFO assignment for filter 4
-            FFA4: u1,
-            ///  Filter FIFO assignment for filter 5
-            FFA5: u1,
-            ///  Filter FIFO assignment for filter 6
-            FFA6: u1,
-            ///  Filter FIFO assignment for filter 7
-            FFA7: u1,
-            ///  Filter FIFO assignment for filter 8
-            FFA8: u1,
-            ///  Filter FIFO assignment for filter 9
-            FFA9: u1,
-            ///  Filter FIFO assignment for filter 10
-            FFA10: u1,
-            ///  Filter FIFO assignment for filter 11
-            FFA11: u1,
-            ///  Filter FIFO assignment for filter 12
-            FFA12: u1,
-            ///  Filter FIFO assignment for filter 13
-            FFA13: u1,
-            padding: u18,
-        }),
-        reserved540: [4]u8,
-        ///  CAN_FA1R
-        CAN_FA1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter active
-            FACT0: u1,
-            ///  Filter active
-            FACT1: u1,
-            ///  Filter active
-            FACT2: u1,
-            ///  Filter active
-            FACT3: u1,
-            ///  Filter active
-            FACT4: u1,
-            ///  Filter active
-            FACT5: u1,
-            ///  Filter active
-            FACT6: u1,
-            ///  Filter active
-            FACT7: u1,
-            ///  Filter active
-            FACT8: u1,
-            ///  Filter active
-            FACT9: u1,
-            ///  Filter active
-            FACT10: u1,
-            ///  Filter active
-            FACT11: u1,
-            ///  Filter active
-            FACT12: u1,
-            ///  Filter active
-            FACT13: u1,
-            padding: u18,
-        }),
-        reserved576: [32]u8,
-        ///  Filter bank 0 register 1
-        F0R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 0 register 2
-        F0R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 1 register 1
-        F1R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 1 register 2
-        F1R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 2 register 1
-        F2R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 2 register 2
-        F2R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 3 register 1
-        F3R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 3 register 2
-        F3R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 1
-        F4R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 2
-        F4R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 5 register 1
-        F5R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 5 register 2
-        F5R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 6 register 1
-        F6R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 6 register 2
-        F6R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 7 register 1
-        F7R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 7 register 2
-        F7R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 8 register 1
-        F8R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 8 register 2
-        F8R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 9 register 1
-        F9R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 9 register 2
-        F9R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 10 register 1
-        F10R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 10 register 2
-        F10R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 11 register 1
-        F11R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 11 register 2
-        F11R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 1
-        F12R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 12 register 2
-        F12R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 13 register 1
-        F13R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 13 register 2
-        F13R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-    };
-};
diff --git a/src/chips/STM32F303.zig b/src/chips/STM32F303.zig
deleted file mode 100644
index f897dc632..000000000
--- a/src/chips/STM32F303.zig
+++ /dev/null
@@ -1,13076 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    ///  STM32F303
-    pub const STM32F303 = struct {
-        pub const properties = struct {
-            pub const @"cpu.nvic_prio_bits" = "3";
-            pub const @"cpu.mpu" = "false";
-            pub const @"cpu.fpu" = "false";
-            pub const @"cpu.revision" = "r1p0";
-            pub const @"cpu.vendor_systick_config" = "false";
-            pub const @"cpu.endian" = "little";
-            pub const @"cpu.name" = "CM4";
-        };
-
-        pub const VectorTable = extern struct {
-            const Handler = micro.interrupt.Handler;
-            const unhandled = micro.interrupt.unhandled;
-
-            initial_stack_pointer: u32,
-            Reset: Handler = unhandled,
-            NMI: Handler = unhandled,
-            HardFault: Handler = unhandled,
-            MemManageFault: Handler = unhandled,
-            BusFault: Handler = unhandled,
-            UsageFault: Handler = unhandled,
-            reserved5: [4]u32 = undefined,
-            SVCall: Handler = unhandled,
-            DebugMonitor: Handler = unhandled,
-            reserved11: [1]u32 = undefined,
-            PendSV: Handler = unhandled,
-            SysTick: Handler = unhandled,
-            ///  Window Watchdog interrupt
-            WWDG: Handler = unhandled,
-            ///  PVD through EXTI line detection interrupt
-            PVD: Handler = unhandled,
-            ///  Tamper and TimeStamp interrupts
-            TAMP_STAMP: Handler = unhandled,
-            ///  RTC Wakeup interrupt through the EXTI line
-            RTC_WKUP: Handler = unhandled,
-            ///  Flash global interrupt
-            FLASH: Handler = unhandled,
-            ///  RCC global interrupt
-            RCC: Handler = unhandled,
-            reserved20: [2]u32 = undefined,
-            ///  EXTI Line2 and Touch sensing interrupts
-            EXTI2_TSC: Handler = unhandled,
-            reserved23: [2]u32 = undefined,
-            ///  DMA1 channel 1 interrupt
-            DMA1_CH1: Handler = unhandled,
-            reserved26: [6]u32 = undefined,
-            ///  ADC1 and ADC2 global interrupt
-            ADC1_2: Handler = unhandled,
-            ///  USB High Priority/CAN_TX interrupts
-            USB_HP_CAN_TX: Handler = unhandled,
-            reserved34: [4]u32 = undefined,
-            ///  TIM1 Break/TIM15 global interruts
-            TIM1_BRK_TIM15: Handler = unhandled,
-            ///  TIM1 Update/TIM16 global interrupts
-            TIM1_UP_TIM16: Handler = unhandled,
-            ///  TIM1 trigger and commutation/TIM17 interrupts
-            TIM1_TRG_COM_TIM17: Handler = unhandled,
-            ///  TIM1 capture compare interrupt
-            TIM1_CC: Handler = unhandled,
-            ///  TIM2 global interrupt
-            TIM2: Handler = unhandled,
-            ///  TIM3 global interrupt
-            TIM3: Handler = unhandled,
-            ///  TIM4 global interrupt
-            TIM4: Handler = unhandled,
-            ///  I2C1 event interrupt and EXTI Line23 interrupt
-            I2C1_EV_EXTI23: Handler = unhandled,
-            reserved46: [1]u32 = undefined,
-            ///  I2C2 event interrupt & EXTI Line24 interrupt
-            I2C2_EV_EXTI24: Handler = unhandled,
-            reserved48: [1]u32 = undefined,
-            ///  SPI1 global interrupt
-            SPI1: Handler = unhandled,
-            ///  SPI2 global interrupt
-            SPI2: Handler = unhandled,
-            ///  USART1 global interrupt and EXTI Line 25 interrupt
-            USART1_EXTI25: Handler = unhandled,
-            ///  USART2 global interrupt and EXTI Line 26 interrupt
-            USART2_EXTI26: Handler = unhandled,
-            ///  USART3 global interrupt and EXTI Line 28 interrupt
-            USART3_EXTI28: Handler = unhandled,
-            reserved54: [2]u32 = undefined,
-            ///  USB wakeup from Suspend
-            USB_WKUP: Handler = unhandled,
-            ///  TIM8 break interrupt
-            TIM8_BRK: Handler = unhandled,
-            reserved58: [3]u32 = undefined,
-            ///  ADC3 global interrupt
-            ADC3: Handler = unhandled,
-            ///  FSMC global interrupt
-            FMC: Handler = unhandled,
-            reserved63: [2]u32 = undefined,
-            ///  SPI3 global interrupt
-            SPI3: Handler = unhandled,
-            ///  UART4 global and EXTI Line 34 interrupts
-            UART4_EXTI34: Handler = unhandled,
-            ///  UART5 global and EXTI Line 35 interrupts
-            UART5_EXTI35: Handler = unhandled,
-            ///  TIM6 global and DAC12 underrun interrupts
-            TIM6_DACUNDER: Handler = unhandled,
-            ///  TIM7 global interrupt
-            TIM7: Handler = unhandled,
-            ///  DMA2 channel1 global interrupt
-            DMA2_CH1: Handler = unhandled,
-            reserved71: [4]u32 = undefined,
-            ///  ADC4 global interrupt
-            ADC4: Handler = unhandled,
-            reserved76: [2]u32 = undefined,
-            ///  COMP1 & COMP2 & COMP3 interrupts combined with EXTI Lines 21, 22 and 29 interrupts
-            COMP123: Handler = unhandled,
-            reserved79: [16]u32 = undefined,
-            ///  Floating point unit interrupt
-            FPU: Handler = unhandled,
-        };
-
-        pub const peripherals = struct {
-            ///  General purpose timer
-            pub const TIM2 = @as(*volatile types.TIM2, @ptrFromInt(0x40000000));
-            ///  General purpose timer
-            pub const TIM3 = @as(*volatile types.TIM2, @ptrFromInt(0x40000400));
-            ///  General purpose timer
-            pub const TIM4 = @as(*volatile types.TIM2, @ptrFromInt(0x40000800));
-            ///  Basic timers
-            pub const TIM6 = @as(*volatile types.TIM6, @ptrFromInt(0x40001000));
-            ///  Basic timers
-            pub const TIM7 = @as(*volatile types.TIM6, @ptrFromInt(0x40001400));
-            ///  Real-time clock
-            pub const RTC = @as(*volatile types.RTC, @ptrFromInt(0x40002800));
-            ///  Window watchdog
-            pub const WWDG = @as(*volatile types.WWDG, @ptrFromInt(0x40002c00));
-            ///  Independent watchdog
-            pub const IWDG = @as(*volatile types.IWDG, @ptrFromInt(0x40003000));
-            ///  Serial peripheral interface/Inter-IC sound
-            pub const I2S2ext = @as(*volatile types.SPI1, @ptrFromInt(0x40003400));
-            ///  Serial peripheral interface/Inter-IC sound
-            pub const SPI2 = @as(*volatile types.SPI1, @ptrFromInt(0x40003800));
-            ///  Serial peripheral interface/Inter-IC sound
-            pub const SPI3 = @as(*volatile types.SPI1, @ptrFromInt(0x40003c00));
-            ///  Serial peripheral interface/Inter-IC sound
-            pub const I2S3ext = @as(*volatile types.SPI1, @ptrFromInt(0x40004000));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART2 = @as(*volatile types.USART1, @ptrFromInt(0x40004400));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART3 = @as(*volatile types.USART1, @ptrFromInt(0x40004800));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART4 = @as(*volatile types.USART1, @ptrFromInt(0x40004c00));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART5 = @as(*volatile types.USART1, @ptrFromInt(0x40005000));
-            ///  Inter-integrated circuit
-            pub const I2C1 = @as(*volatile types.I2C1, @ptrFromInt(0x40005400));
-            ///  Inter-integrated circuit
-            pub const I2C2 = @as(*volatile types.I2C1, @ptrFromInt(0x40005800));
-            ///  Universal serial bus full-speed device interface
-            pub const USB_FS = @as(*volatile types.USB_FS, @ptrFromInt(0x40005c00));
-            ///  Controller area network
-            pub const CAN = @as(*volatile types.CAN, @ptrFromInt(0x40006400));
-            ///  Power control
-            pub const PWR = @as(*volatile types.PWR, @ptrFromInt(0x40007000));
-            ///  Digital-to-analog converter
-            pub const DAC = @as(*volatile types.DAC, @ptrFromInt(0x40007400));
-            ///  Inter-integrated circuit
-            pub const I2C3 = @as(*volatile types.I2C1, @ptrFromInt(0x40007800));
-            ///  System configuration controller _Comparator and Operational amplifier
-            pub const SYSCFG_COMP_OPAMP = @as(*volatile types.SYSCFG_COMP_OPAMP, @ptrFromInt(0x40010000));
-            ///  External interrupt/event controller
-            pub const EXTI = @as(*volatile types.EXTI, @ptrFromInt(0x40010400));
-            ///  Advanced timer
-            pub const TIM1 = @as(*volatile types.TIM1, @ptrFromInt(0x40012c00));
-            ///  Serial peripheral interface/Inter-IC sound
-            pub const SPI1 = @as(*volatile types.SPI1, @ptrFromInt(0x40013000));
-            ///  Advanced-timers
-            pub const TIM8 = @as(*volatile types.TIM8, @ptrFromInt(0x40013400));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART1 = @as(*volatile types.USART1, @ptrFromInt(0x40013800));
-            ///  Serial peripheral interface/Inter-IC sound
-            pub const SPI4 = @as(*volatile types.SPI1, @ptrFromInt(0x40013c00));
-            ///  General purpose timers
-            pub const TIM15 = @as(*volatile types.TIM15, @ptrFromInt(0x40014000));
-            ///  General-purpose-timers
-            pub const TIM16 = @as(*volatile types.TIM16, @ptrFromInt(0x40014400));
-            ///  General purpose timer
-            pub const TIM17 = @as(*volatile types.TIM17, @ptrFromInt(0x40014800));
-            ///  Advanced timer
-            pub const TIM20 = @as(*volatile types.TIM1, @ptrFromInt(0x40015000));
-            ///  DMA controller 1
-            pub const DMA1 = @as(*volatile types.DMA1, @ptrFromInt(0x40020000));
-            ///  DMA controller 1
-            pub const DMA2 = @as(*volatile types.DMA1, @ptrFromInt(0x40020400));
-            ///  Reset and clock control
-            pub const RCC = @as(*volatile types.RCC, @ptrFromInt(0x40021000));
-            ///  Flash
-            pub const Flash = @as(*volatile types.Flash, @ptrFromInt(0x40022000));
-            ///  cyclic redundancy check calculation unit
-            pub const CRC = @as(*volatile types.CRC, @ptrFromInt(0x40023000));
-            ///  Touch sensing controller
-            pub const TSC = @as(*volatile types.TSC, @ptrFromInt(0x40024000));
-            ///  General-purpose I/Os
-            pub const GPIOA = @as(*volatile types.GPIOA, @ptrFromInt(0x48000000));
-            ///  General-purpose I/Os
-            pub const GPIOB = @as(*volatile types.GPIOB, @ptrFromInt(0x48000400));
-            ///  General-purpose I/Os
-            pub const GPIOC = @as(*volatile types.GPIOB, @ptrFromInt(0x48000800));
-            ///  General-purpose I/Os
-            pub const GPIOD = @as(*volatile types.GPIOB, @ptrFromInt(0x48000c00));
-            ///  General-purpose I/Os
-            pub const GPIOE = @as(*volatile types.GPIOB, @ptrFromInt(0x48001000));
-            ///  General-purpose I/Os
-            pub const GPIOF = @as(*volatile types.GPIOB, @ptrFromInt(0x48001400));
-            ///  General-purpose I/Os
-            pub const GPIOG = @as(*volatile types.GPIOB, @ptrFromInt(0x48001800));
-            ///  General-purpose I/Os
-            pub const GPIOH = @as(*volatile types.GPIOB, @ptrFromInt(0x48001c00));
-            ///  Analog-to-Digital Converter
-            pub const ADC1 = @as(*volatile types.ADC1, @ptrFromInt(0x50000000));
-            ///  Analog-to-Digital Converter
-            pub const ADC2 = @as(*volatile types.ADC1, @ptrFromInt(0x50000100));
-            ///  Analog-to-Digital Converter
-            pub const ADC1_2 = @as(*volatile types.ADC1_2, @ptrFromInt(0x50000300));
-            ///  Analog-to-Digital Converter
-            pub const ADC3 = @as(*volatile types.ADC1, @ptrFromInt(0x50000400));
-            ///  Analog-to-Digital Converter
-            pub const ADC4 = @as(*volatile types.ADC1, @ptrFromInt(0x50000500));
-            ///  Analog-to-Digital Converter
-            pub const ADC3_4 = @as(*volatile types.ADC1_2, @ptrFromInt(0x50000700));
-            ///  Flexible memory controller
-            pub const FMC = @as(*volatile types.FMC, @ptrFromInt(0xa0000400));
-            ///  System control block ACTLR
-            pub const SCB_ACTRL = @as(*volatile types.SCB_ACTRL, @ptrFromInt(0xe000e008));
-            ///  SysTick timer
-            pub const STK = @as(*volatile types.STK, @ptrFromInt(0xe000e010));
-            ///  Nested Vectored Interrupt Controller
-            pub const NVIC = @as(*volatile types.NVIC, @ptrFromInt(0xe000e100));
-            ///  System control block
-            pub const SCB = @as(*volatile types.SCB, @ptrFromInt(0xe000ed00));
-            ///  Floating point unit CPACR
-            pub const FPU_CPACR = @as(*volatile types.FPU_CPACR, @ptrFromInt(0xe000ed88));
-            ///  Memory protection unit
-            pub const MPU = @as(*volatile types.MPU, @ptrFromInt(0xe000ed90));
-            ///  Nested vectored interrupt controller
-            pub const NVIC_STIR = @as(*volatile types.NVIC_STIR, @ptrFromInt(0xe000ef00));
-            ///  Floting point unit
-            pub const FPU = @as(*volatile types.FPU, @ptrFromInt(0xe000ef34));
-            ///  Debug support
-            pub const DBGMCU = @as(*volatile types.DBGMCU, @ptrFromInt(0xe0042000));
-        };
-    };
-};
-
-pub const types = struct {
-    ///  General-purpose I/Os
-    pub const GPIOA = extern struct {
-        ///  GPIO port mode register
-        MODER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            MODER0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER15: u2,
-        }),
-        ///  GPIO port output type register
-        OTYPER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OT0: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT1: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT2: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT3: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT4: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT5: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT6: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT7: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT8: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT9: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT10: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT11: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT12: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT13: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT14: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output speed register
-        OSPEEDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR15: u2,
-        }),
-        ///  GPIO port pull-up/pull-down register
-        PUPDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR15: u2,
-        }),
-        ///  GPIO port input data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Port input data (y = 0..15)
-            IDR0: u1,
-            ///  Port input data (y = 0..15)
-            IDR1: u1,
-            ///  Port input data (y = 0..15)
-            IDR2: u1,
-            ///  Port input data (y = 0..15)
-            IDR3: u1,
-            ///  Port input data (y = 0..15)
-            IDR4: u1,
-            ///  Port input data (y = 0..15)
-            IDR5: u1,
-            ///  Port input data (y = 0..15)
-            IDR6: u1,
-            ///  Port input data (y = 0..15)
-            IDR7: u1,
-            ///  Port input data (y = 0..15)
-            IDR8: u1,
-            ///  Port input data (y = 0..15)
-            IDR9: u1,
-            ///  Port input data (y = 0..15)
-            IDR10: u1,
-            ///  Port input data (y = 0..15)
-            IDR11: u1,
-            ///  Port input data (y = 0..15)
-            IDR12: u1,
-            ///  Port input data (y = 0..15)
-            IDR13: u1,
-            ///  Port input data (y = 0..15)
-            IDR14: u1,
-            ///  Port input data (y = 0..15)
-            IDR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output data register
-        ODR: mmio.Mmio(packed struct(u32) {
-            ///  Port output data (y = 0..15)
-            ODR0: u1,
-            ///  Port output data (y = 0..15)
-            ODR1: u1,
-            ///  Port output data (y = 0..15)
-            ODR2: u1,
-            ///  Port output data (y = 0..15)
-            ODR3: u1,
-            ///  Port output data (y = 0..15)
-            ODR4: u1,
-            ///  Port output data (y = 0..15)
-            ODR5: u1,
-            ///  Port output data (y = 0..15)
-            ODR6: u1,
-            ///  Port output data (y = 0..15)
-            ODR7: u1,
-            ///  Port output data (y = 0..15)
-            ODR8: u1,
-            ///  Port output data (y = 0..15)
-            ODR9: u1,
-            ///  Port output data (y = 0..15)
-            ODR10: u1,
-            ///  Port output data (y = 0..15)
-            ODR11: u1,
-            ///  Port output data (y = 0..15)
-            ODR12: u1,
-            ///  Port output data (y = 0..15)
-            ODR13: u1,
-            ///  Port output data (y = 0..15)
-            ODR14: u1,
-            ///  Port output data (y = 0..15)
-            ODR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port bit set/reset register
-        BSRR: mmio.Mmio(packed struct(u32) {
-            ///  Port x set bit y (y= 0..15)
-            BS0: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS1: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS2: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS3: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS4: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS5: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS6: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS7: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS8: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS9: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS10: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS11: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS12: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS13: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS14: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS15: u1,
-            ///  Port x set bit y (y= 0..15)
-            BR0: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR1: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR2: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR3: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR4: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR5: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR6: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR7: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR8: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR9: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR10: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR11: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR12: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR13: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR14: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR15: u1,
-        }),
-        ///  GPIO port configuration lock register
-        LCKR: mmio.Mmio(packed struct(u32) {
-            ///  Port x lock bit y (y= 0..15)
-            LCK0: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK1: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK2: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK3: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK4: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK5: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK6: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK7: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK8: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK9: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK10: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK11: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK12: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK13: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK14: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK15: u1,
-            ///  Lok Key
-            LCKK: u1,
-            padding: u15,
-        }),
-        ///  GPIO alternate function low register
-        AFRL: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL0: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL1: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL2: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL3: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL4: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL5: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL6: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL7: u4,
-        }),
-        ///  GPIO alternate function high register
-        AFRH: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH8: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH9: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH10: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH11: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH12: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH13: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH14: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH15: u4,
-        }),
-        ///  Port bit reset register
-        BRR: mmio.Mmio(packed struct(u32) {
-            ///  Port x Reset bit y
-            BR0: u1,
-            ///  Port x Reset bit y
-            BR1: u1,
-            ///  Port x Reset bit y
-            BR2: u1,
-            ///  Port x Reset bit y
-            BR3: u1,
-            ///  Port x Reset bit y
-            BR4: u1,
-            ///  Port x Reset bit y
-            BR5: u1,
-            ///  Port x Reset bit y
-            BR6: u1,
-            ///  Port x Reset bit y
-            BR7: u1,
-            ///  Port x Reset bit y
-            BR8: u1,
-            ///  Port x Reset bit y
-            BR9: u1,
-            ///  Port x Reset bit y
-            BR10: u1,
-            ///  Port x Reset bit y
-            BR11: u1,
-            ///  Port x Reset bit y
-            BR12: u1,
-            ///  Port x Reset bit y
-            BR13: u1,
-            ///  Port x Reset bit y
-            BR14: u1,
-            ///  Port x Reset bit y
-            BR15: u1,
-            padding: u16,
-        }),
-    };
-
-    ///  General-purpose I/Os
-    pub const GPIOB = extern struct {
-        ///  GPIO port mode register
-        MODER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            MODER0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER15: u2,
-        }),
-        ///  GPIO port output type register
-        OTYPER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bit 0
-            OT0: u1,
-            ///  Port x configuration bit 1
-            OT1: u1,
-            ///  Port x configuration bit 2
-            OT2: u1,
-            ///  Port x configuration bit 3
-            OT3: u1,
-            ///  Port x configuration bit 4
-            OT4: u1,
-            ///  Port x configuration bit 5
-            OT5: u1,
-            ///  Port x configuration bit 6
-            OT6: u1,
-            ///  Port x configuration bit 7
-            OT7: u1,
-            ///  Port x configuration bit 8
-            OT8: u1,
-            ///  Port x configuration bit 9
-            OT9: u1,
-            ///  Port x configuration bit 10
-            OT10: u1,
-            ///  Port x configuration bit 11
-            OT11: u1,
-            ///  Port x configuration bit 12
-            OT12: u1,
-            ///  Port x configuration bit 13
-            OT13: u1,
-            ///  Port x configuration bit 14
-            OT14: u1,
-            ///  Port x configuration bit 15
-            OT15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output speed register
-        OSPEEDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR15: u2,
-        }),
-        ///  GPIO port pull-up/pull-down register
-        PUPDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR15: u2,
-        }),
-        ///  GPIO port input data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Port input data (y = 0..15)
-            IDR0: u1,
-            ///  Port input data (y = 0..15)
-            IDR1: u1,
-            ///  Port input data (y = 0..15)
-            IDR2: u1,
-            ///  Port input data (y = 0..15)
-            IDR3: u1,
-            ///  Port input data (y = 0..15)
-            IDR4: u1,
-            ///  Port input data (y = 0..15)
-            IDR5: u1,
-            ///  Port input data (y = 0..15)
-            IDR6: u1,
-            ///  Port input data (y = 0..15)
-            IDR7: u1,
-            ///  Port input data (y = 0..15)
-            IDR8: u1,
-            ///  Port input data (y = 0..15)
-            IDR9: u1,
-            ///  Port input data (y = 0..15)
-            IDR10: u1,
-            ///  Port input data (y = 0..15)
-            IDR11: u1,
-            ///  Port input data (y = 0..15)
-            IDR12: u1,
-            ///  Port input data (y = 0..15)
-            IDR13: u1,
-            ///  Port input data (y = 0..15)
-            IDR14: u1,
-            ///  Port input data (y = 0..15)
-            IDR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output data register
-        ODR: mmio.Mmio(packed struct(u32) {
-            ///  Port output data (y = 0..15)
-            ODR0: u1,
-            ///  Port output data (y = 0..15)
-            ODR1: u1,
-            ///  Port output data (y = 0..15)
-            ODR2: u1,
-            ///  Port output data (y = 0..15)
-            ODR3: u1,
-            ///  Port output data (y = 0..15)
-            ODR4: u1,
-            ///  Port output data (y = 0..15)
-            ODR5: u1,
-            ///  Port output data (y = 0..15)
-            ODR6: u1,
-            ///  Port output data (y = 0..15)
-            ODR7: u1,
-            ///  Port output data (y = 0..15)
-            ODR8: u1,
-            ///  Port output data (y = 0..15)
-            ODR9: u1,
-            ///  Port output data (y = 0..15)
-            ODR10: u1,
-            ///  Port output data (y = 0..15)
-            ODR11: u1,
-            ///  Port output data (y = 0..15)
-            ODR12: u1,
-            ///  Port output data (y = 0..15)
-            ODR13: u1,
-            ///  Port output data (y = 0..15)
-            ODR14: u1,
-            ///  Port output data (y = 0..15)
-            ODR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port bit set/reset register
-        BSRR: mmio.Mmio(packed struct(u32) {
-            ///  Port x set bit y (y= 0..15)
-            BS0: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS1: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS2: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS3: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS4: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS5: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS6: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS7: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS8: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS9: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS10: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS11: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS12: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS13: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS14: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS15: u1,
-            ///  Port x set bit y (y= 0..15)
-            BR0: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR1: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR2: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR3: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR4: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR5: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR6: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR7: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR8: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR9: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR10: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR11: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR12: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR13: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR14: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR15: u1,
-        }),
-        ///  GPIO port configuration lock register
-        LCKR: mmio.Mmio(packed struct(u32) {
-            ///  Port x lock bit y (y= 0..15)
-            LCK0: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK1: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK2: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK3: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK4: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK5: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK6: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK7: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK8: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK9: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK10: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK11: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK12: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK13: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK14: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK15: u1,
-            ///  Lok Key
-            LCKK: u1,
-            padding: u15,
-        }),
-        ///  GPIO alternate function low register
-        AFRL: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL0: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL1: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL2: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL3: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL4: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL5: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL6: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL7: u4,
-        }),
-        ///  GPIO alternate function high register
-        AFRH: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH8: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH9: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH10: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH11: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH12: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH13: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH14: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH15: u4,
-        }),
-        ///  Port bit reset register
-        BRR: mmio.Mmio(packed struct(u32) {
-            ///  Port x Reset bit y
-            BR0: u1,
-            ///  Port x Reset bit y
-            BR1: u1,
-            ///  Port x Reset bit y
-            BR2: u1,
-            ///  Port x Reset bit y
-            BR3: u1,
-            ///  Port x Reset bit y
-            BR4: u1,
-            ///  Port x Reset bit y
-            BR5: u1,
-            ///  Port x Reset bit y
-            BR6: u1,
-            ///  Port x Reset bit y
-            BR7: u1,
-            ///  Port x Reset bit y
-            BR8: u1,
-            ///  Port x Reset bit y
-            BR9: u1,
-            ///  Port x Reset bit y
-            BR10: u1,
-            ///  Port x Reset bit y
-            BR11: u1,
-            ///  Port x Reset bit y
-            BR12: u1,
-            ///  Port x Reset bit y
-            BR13: u1,
-            ///  Port x Reset bit y
-            BR14: u1,
-            ///  Port x Reset bit y
-            BR15: u1,
-            padding: u16,
-        }),
-    };
-
-    ///  System control block ACTLR
-    pub const SCB_ACTRL = extern struct {
-        ///  Auxiliary control register
-        ACTRL: mmio.Mmio(packed struct(u32) {
-            ///  DISMCYCINT
-            DISMCYCINT: u1,
-            ///  DISDEFWBUF
-            DISDEFWBUF: u1,
-            ///  DISFOLD
-            DISFOLD: u1,
-            reserved8: u5,
-            ///  DISFPCA
-            DISFPCA: u1,
-            ///  DISOOFP
-            DISOOFP: u1,
-            padding: u22,
-        }),
-    };
-
-    ///  Floating point unit CPACR
-    pub const FPU_CPACR = extern struct {
-        ///  Coprocessor access control register
-        CPACR: mmio.Mmio(packed struct(u32) {
-            reserved20: u20,
-            ///  CP
-            CP: u4,
-            padding: u8,
-        }),
-    };
-
-    ///  Nested vectored interrupt controller
-    pub const NVIC_STIR = extern struct {
-        ///  Software trigger interrupt register
-        STIR: mmio.Mmio(packed struct(u32) {
-            ///  Software generated interrupt ID
-            INTID: u9,
-            padding: u23,
-        }),
-    };
-
-    ///  System control block
-    pub const SCB = extern struct {
-        ///  CPUID base register
-        CPUID: mmio.Mmio(packed struct(u32) {
-            ///  Revision number
-            Revision: u4,
-            ///  Part number of the processor
-            PartNo: u12,
-            ///  Reads as 0xF
-            Constant: u4,
-            ///  Variant number
-            Variant: u4,
-            ///  Implementer code
-            Implementer: u8,
-        }),
-        ///  Interrupt control and state register
-        ICSR: mmio.Mmio(packed struct(u32) {
-            ///  Active vector
-            VECTACTIVE: u9,
-            reserved11: u2,
-            ///  Return to base level
-            RETTOBASE: u1,
-            ///  Pending vector
-            VECTPENDING: u7,
-            reserved22: u3,
-            ///  Interrupt pending flag
-            ISRPENDING: u1,
-            reserved25: u2,
-            ///  SysTick exception clear-pending bit
-            PENDSTCLR: u1,
-            ///  SysTick exception set-pending bit
-            PENDSTSET: u1,
-            ///  PendSV clear-pending bit
-            PENDSVCLR: u1,
-            ///  PendSV set-pending bit
-            PENDSVSET: u1,
-            reserved31: u2,
-            ///  NMI set-pending bit.
-            NMIPENDSET: u1,
-        }),
-        ///  Vector table offset register
-        VTOR: mmio.Mmio(packed struct(u32) {
-            reserved9: u9,
-            ///  Vector table base offset field
-            TBLOFF: u21,
-            padding: u2,
-        }),
-        ///  Application interrupt and reset control register
-        AIRCR: mmio.Mmio(packed struct(u32) {
-            ///  VECTRESET
-            VECTRESET: u1,
-            ///  VECTCLRACTIVE
-            VECTCLRACTIVE: u1,
-            ///  SYSRESETREQ
-            SYSRESETREQ: u1,
-            reserved8: u5,
-            ///  PRIGROUP
-            PRIGROUP: u3,
-            reserved15: u4,
-            ///  ENDIANESS
-            ENDIANESS: u1,
-            ///  Register key
-            VECTKEYSTAT: u16,
-        }),
-        ///  System control register
-        SCR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  SLEEPONEXIT
-            SLEEPONEXIT: u1,
-            ///  SLEEPDEEP
-            SLEEPDEEP: u1,
-            reserved4: u1,
-            ///  Send Event on Pending bit
-            SEVEONPEND: u1,
-            padding: u27,
-        }),
-        ///  Configuration and control register
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Configures how the processor enters Thread mode
-            NONBASETHRDENA: u1,
-            ///  USERSETMPEND
-            USERSETMPEND: u1,
-            reserved3: u1,
-            ///  UNALIGN_ TRP
-            UNALIGN__TRP: u1,
-            ///  DIV_0_TRP
-            DIV_0_TRP: u1,
-            reserved8: u3,
-            ///  BFHFNMIGN
-            BFHFNMIGN: u1,
-            ///  STKALIGN
-            STKALIGN: u1,
-            padding: u22,
-        }),
-        ///  System handler priority registers
-        SHPR1: mmio.Mmio(packed struct(u32) {
-            ///  Priority of system handler 4
-            PRI_4: u8,
-            ///  Priority of system handler 5
-            PRI_5: u8,
-            ///  Priority of system handler 6
-            PRI_6: u8,
-            padding: u8,
-        }),
-        ///  System handler priority registers
-        SHPR2: mmio.Mmio(packed struct(u32) {
-            reserved24: u24,
-            ///  Priority of system handler 11
-            PRI_11: u8,
-        }),
-        ///  System handler priority registers
-        SHPR3: mmio.Mmio(packed struct(u32) {
-            reserved16: u16,
-            ///  Priority of system handler 14
-            PRI_14: u8,
-            ///  Priority of system handler 15
-            PRI_15: u8,
-        }),
-        ///  System handler control and state register
-        SHCRS: mmio.Mmio(packed struct(u32) {
-            ///  Memory management fault exception active bit
-            MEMFAULTACT: u1,
-            ///  Bus fault exception active bit
-            BUSFAULTACT: u1,
-            reserved3: u1,
-            ///  Usage fault exception active bit
-            USGFAULTACT: u1,
-            reserved7: u3,
-            ///  SVC call active bit
-            SVCALLACT: u1,
-            ///  Debug monitor active bit
-            MONITORACT: u1,
-            reserved10: u1,
-            ///  PendSV exception active bit
-            PENDSVACT: u1,
-            ///  SysTick exception active bit
-            SYSTICKACT: u1,
-            ///  Usage fault exception pending bit
-            USGFAULTPENDED: u1,
-            ///  Memory management fault exception pending bit
-            MEMFAULTPENDED: u1,
-            ///  Bus fault exception pending bit
-            BUSFAULTPENDED: u1,
-            ///  SVC call pending bit
-            SVCALLPENDED: u1,
-            ///  Memory management fault enable bit
-            MEMFAULTENA: u1,
-            ///  Bus fault enable bit
-            BUSFAULTENA: u1,
-            ///  Usage fault enable bit
-            USGFAULTENA: u1,
-            padding: u13,
-        }),
-        ///  Configurable fault status register
-        CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Instruction access violation flag
-            IACCVIOL: u1,
-            reserved3: u1,
-            ///  Memory manager fault on unstacking for a return from exception
-            MUNSTKERR: u1,
-            ///  Memory manager fault on stacking for exception entry.
-            MSTKERR: u1,
-            ///  MLSPERR
-            MLSPERR: u1,
-            reserved7: u1,
-            ///  Memory Management Fault Address Register (MMAR) valid flag
-            MMARVALID: u1,
-            ///  Instruction bus error
-            IBUSERR: u1,
-            ///  Precise data bus error
-            PRECISERR: u1,
-            ///  Imprecise data bus error
-            IMPRECISERR: u1,
-            ///  Bus fault on unstacking for a return from exception
-            UNSTKERR: u1,
-            ///  Bus fault on stacking for exception entry
-            STKERR: u1,
-            ///  Bus fault on floating-point lazy state preservation
-            LSPERR: u1,
-            reserved15: u1,
-            ///  Bus Fault Address Register (BFAR) valid flag
-            BFARVALID: u1,
-            ///  Undefined instruction usage fault
-            UNDEFINSTR: u1,
-            ///  Invalid state usage fault
-            INVSTATE: u1,
-            ///  Invalid PC load usage fault
-            INVPC: u1,
-            ///  No coprocessor usage fault.
-            NOCP: u1,
-            reserved24: u4,
-            ///  Unaligned access usage fault
-            UNALIGNED: u1,
-            ///  Divide by zero usage fault
-            DIVBYZERO: u1,
-            padding: u6,
-        }),
-        ///  Hard fault status register
-        HFSR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Vector table hard fault
-            VECTTBL: u1,
-            reserved30: u28,
-            ///  Forced hard fault
-            FORCED: u1,
-            ///  Reserved for Debug use
-            DEBUG_VT: u1,
-        }),
-        reserved52: [4]u8,
-        ///  Memory management fault address register
-        MMFAR: mmio.Mmio(packed struct(u32) {
-            ///  Memory management fault address
-            MMFAR: u32,
-        }),
-        ///  Bus fault address register
-        BFAR: mmio.Mmio(packed struct(u32) {
-            ///  Bus fault address
-            BFAR: u32,
-        }),
-        ///  Auxiliary fault status register
-        AFSR: mmio.Mmio(packed struct(u32) {
-            ///  Implementation defined
-            IMPDEF: u32,
-        }),
-    };
-
-    ///  SysTick timer
-    pub const STK = extern struct {
-        ///  SysTick control and status register
-        CTRL: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            ENABLE: u1,
-            ///  SysTick exception request enable
-            TICKINT: u1,
-            ///  Clock source selection
-            CLKSOURCE: u1,
-            reserved16: u13,
-            ///  COUNTFLAG
-            COUNTFLAG: u1,
-            padding: u15,
-        }),
-        ///  SysTick reload value register
-        LOAD: mmio.Mmio(packed struct(u32) {
-            ///  RELOAD value
-            RELOAD: u24,
-            padding: u8,
-        }),
-        ///  SysTick current value register
-        VAL: mmio.Mmio(packed struct(u32) {
-            ///  Current counter value
-            CURRENT: u24,
-            padding: u8,
-        }),
-        ///  SysTick calibration value register
-        CALIB: mmio.Mmio(packed struct(u32) {
-            ///  Calibration value
-            TENMS: u24,
-            reserved30: u6,
-            ///  SKEW flag: Indicates whether the TENMS value is exact
-            SKEW: u1,
-            ///  NOREF flag. Reads as zero
-            NOREF: u1,
-        }),
-    };
-
-    ///  Memory protection unit
-    pub const MPU = extern struct {
-        ///  MPU type register
-        MPU_TYPER: mmio.Mmio(packed struct(u32) {
-            ///  Separate flag
-            SEPARATE: u1,
-            reserved8: u7,
-            ///  Number of MPU data regions
-            DREGION: u8,
-            ///  Number of MPU instruction regions
-            IREGION: u8,
-            padding: u8,
-        }),
-        ///  MPU control register
-        MPU_CTRL: mmio.Mmio(packed struct(u32) {
-            ///  Enables the MPU
-            ENABLE: u1,
-            ///  Enables the operation of MPU during hard fault
-            HFNMIENA: u1,
-            ///  Enable priviliged software access to default memory map
-            PRIVDEFENA: u1,
-            padding: u29,
-        }),
-        ///  MPU region number register
-        MPU_RNR: mmio.Mmio(packed struct(u32) {
-            ///  MPU region
-            REGION: u8,
-            padding: u24,
-        }),
-        ///  MPU region base address register
-        MPU_RBAR: mmio.Mmio(packed struct(u32) {
-            ///  MPU region field
-            REGION: u4,
-            ///  MPU region number valid
-            VALID: u1,
-            ///  Region base address field
-            ADDR: u27,
-        }),
-        ///  MPU region attribute and size register
-        MPU_RASR: mmio.Mmio(packed struct(u32) {
-            ///  Region enable bit.
-            ENABLE: u1,
-            ///  Size of the MPU protection region
-            SIZE: u5,
-            reserved8: u2,
-            ///  Subregion disable bits
-            SRD: u8,
-            ///  memory attribute
-            B: u1,
-            ///  memory attribute
-            C: u1,
-            ///  Shareable memory attribute
-            S: u1,
-            ///  memory attribute
-            TEX: u3,
-            reserved24: u2,
-            ///  Access permission
-            AP: u3,
-            reserved28: u1,
-            ///  Instruction access disable bit
-            XN: u1,
-            padding: u3,
-        }),
-    };
-
-    ///  Touch sensing controller
-    pub const TSC = extern struct {
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Touch sensing controller enable
-            TSCE: u1,
-            ///  Start a new acquisition
-            START: u1,
-            ///  Acquisition mode
-            AM: u1,
-            ///  Synchronization pin polarity
-            SYNCPOL: u1,
-            ///  I/O Default mode
-            IODEF: u1,
-            ///  Max count value
-            MCV: u3,
-            reserved12: u4,
-            ///  pulse generator prescaler
-            PGPSC: u3,
-            ///  Spread spectrum prescaler
-            SSPSC: u1,
-            ///  Spread spectrum enable
-            SSE: u1,
-            ///  Spread spectrum deviation
-            SSD: u7,
-            ///  Charge transfer pulse low
-            CTPL: u4,
-            ///  Charge transfer pulse high
-            CTPH: u4,
-        }),
-        ///  interrupt enable register
-        IER: mmio.Mmio(packed struct(u32) {
-            ///  End of acquisition interrupt enable
-            EOAIE: u1,
-            ///  Max count error interrupt enable
-            MCEIE: u1,
-            padding: u30,
-        }),
-        ///  interrupt clear register
-        ICR: mmio.Mmio(packed struct(u32) {
-            ///  End of acquisition interrupt clear
-            EOAIC: u1,
-            ///  Max count error interrupt clear
-            MCEIC: u1,
-            padding: u30,
-        }),
-        ///  interrupt status register
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  End of acquisition flag
-            EOAF: u1,
-            ///  Max count error flag
-            MCEF: u1,
-            padding: u30,
-        }),
-        ///  I/O hysteresis control register
-        IOHCR: mmio.Mmio(packed struct(u32) {
-            ///  G1_IO1 Schmitt trigger hysteresis mode
-            G1_IO1: u1,
-            ///  G1_IO2 Schmitt trigger hysteresis mode
-            G1_IO2: u1,
-            ///  G1_IO3 Schmitt trigger hysteresis mode
-            G1_IO3: u1,
-            ///  G1_IO4 Schmitt trigger hysteresis mode
-            G1_IO4: u1,
-            ///  G2_IO1 Schmitt trigger hysteresis mode
-            G2_IO1: u1,
-            ///  G2_IO2 Schmitt trigger hysteresis mode
-            G2_IO2: u1,
-            ///  G2_IO3 Schmitt trigger hysteresis mode
-            G2_IO3: u1,
-            ///  G2_IO4 Schmitt trigger hysteresis mode
-            G2_IO4: u1,
-            ///  G3_IO1 Schmitt trigger hysteresis mode
-            G3_IO1: u1,
-            ///  G3_IO2 Schmitt trigger hysteresis mode
-            G3_IO2: u1,
-            ///  G3_IO3 Schmitt trigger hysteresis mode
-            G3_IO3: u1,
-            ///  G3_IO4 Schmitt trigger hysteresis mode
-            G3_IO4: u1,
-            ///  G4_IO1 Schmitt trigger hysteresis mode
-            G4_IO1: u1,
-            ///  G4_IO2 Schmitt trigger hysteresis mode
-            G4_IO2: u1,
-            ///  G4_IO3 Schmitt trigger hysteresis mode
-            G4_IO3: u1,
-            ///  G4_IO4 Schmitt trigger hysteresis mode
-            G4_IO4: u1,
-            ///  G5_IO1 Schmitt trigger hysteresis mode
-            G5_IO1: u1,
-            ///  G5_IO2 Schmitt trigger hysteresis mode
-            G5_IO2: u1,
-            ///  G5_IO3 Schmitt trigger hysteresis mode
-            G5_IO3: u1,
-            ///  G5_IO4 Schmitt trigger hysteresis mode
-            G5_IO4: u1,
-            ///  G6_IO1 Schmitt trigger hysteresis mode
-            G6_IO1: u1,
-            ///  G6_IO2 Schmitt trigger hysteresis mode
-            G6_IO2: u1,
-            ///  G6_IO3 Schmitt trigger hysteresis mode
-            G6_IO3: u1,
-            ///  G6_IO4 Schmitt trigger hysteresis mode
-            G6_IO4: u1,
-            ///  G7_IO1 Schmitt trigger hysteresis mode
-            G7_IO1: u1,
-            ///  G7_IO2 Schmitt trigger hysteresis mode
-            G7_IO2: u1,
-            ///  G7_IO3 Schmitt trigger hysteresis mode
-            G7_IO3: u1,
-            ///  G7_IO4 Schmitt trigger hysteresis mode
-            G7_IO4: u1,
-            ///  G8_IO1 Schmitt trigger hysteresis mode
-            G8_IO1: u1,
-            ///  G8_IO2 Schmitt trigger hysteresis mode
-            G8_IO2: u1,
-            ///  G8_IO3 Schmitt trigger hysteresis mode
-            G8_IO3: u1,
-            ///  G8_IO4 Schmitt trigger hysteresis mode
-            G8_IO4: u1,
-        }),
-        reserved24: [4]u8,
-        ///  I/O analog switch control register
-        IOASCR: mmio.Mmio(packed struct(u32) {
-            ///  G1_IO1 analog switch enable
-            G1_IO1: u1,
-            ///  G1_IO2 analog switch enable
-            G1_IO2: u1,
-            ///  G1_IO3 analog switch enable
-            G1_IO3: u1,
-            ///  G1_IO4 analog switch enable
-            G1_IO4: u1,
-            ///  G2_IO1 analog switch enable
-            G2_IO1: u1,
-            ///  G2_IO2 analog switch enable
-            G2_IO2: u1,
-            ///  G2_IO3 analog switch enable
-            G2_IO3: u1,
-            ///  G2_IO4 analog switch enable
-            G2_IO4: u1,
-            ///  G3_IO1 analog switch enable
-            G3_IO1: u1,
-            ///  G3_IO2 analog switch enable
-            G3_IO2: u1,
-            ///  G3_IO3 analog switch enable
-            G3_IO3: u1,
-            ///  G3_IO4 analog switch enable
-            G3_IO4: u1,
-            ///  G4_IO1 analog switch enable
-            G4_IO1: u1,
-            ///  G4_IO2 analog switch enable
-            G4_IO2: u1,
-            ///  G4_IO3 analog switch enable
-            G4_IO3: u1,
-            ///  G4_IO4 analog switch enable
-            G4_IO4: u1,
-            ///  G5_IO1 analog switch enable
-            G5_IO1: u1,
-            ///  G5_IO2 analog switch enable
-            G5_IO2: u1,
-            ///  G5_IO3 analog switch enable
-            G5_IO3: u1,
-            ///  G5_IO4 analog switch enable
-            G5_IO4: u1,
-            ///  G6_IO1 analog switch enable
-            G6_IO1: u1,
-            ///  G6_IO2 analog switch enable
-            G6_IO2: u1,
-            ///  G6_IO3 analog switch enable
-            G6_IO3: u1,
-            ///  G6_IO4 analog switch enable
-            G6_IO4: u1,
-            ///  G7_IO1 analog switch enable
-            G7_IO1: u1,
-            ///  G7_IO2 analog switch enable
-            G7_IO2: u1,
-            ///  G7_IO3 analog switch enable
-            G7_IO3: u1,
-            ///  G7_IO4 analog switch enable
-            G7_IO4: u1,
-            ///  G8_IO1 analog switch enable
-            G8_IO1: u1,
-            ///  G8_IO2 analog switch enable
-            G8_IO2: u1,
-            ///  G8_IO3 analog switch enable
-            G8_IO3: u1,
-            ///  G8_IO4 analog switch enable
-            G8_IO4: u1,
-        }),
-        reserved32: [4]u8,
-        ///  I/O sampling control register
-        IOSCR: mmio.Mmio(packed struct(u32) {
-            ///  G1_IO1 sampling mode
-            G1_IO1: u1,
-            ///  G1_IO2 sampling mode
-            G1_IO2: u1,
-            ///  G1_IO3 sampling mode
-            G1_IO3: u1,
-            ///  G1_IO4 sampling mode
-            G1_IO4: u1,
-            ///  G2_IO1 sampling mode
-            G2_IO1: u1,
-            ///  G2_IO2 sampling mode
-            G2_IO2: u1,
-            ///  G2_IO3 sampling mode
-            G2_IO3: u1,
-            ///  G2_IO4 sampling mode
-            G2_IO4: u1,
-            ///  G3_IO1 sampling mode
-            G3_IO1: u1,
-            ///  G3_IO2 sampling mode
-            G3_IO2: u1,
-            ///  G3_IO3 sampling mode
-            G3_IO3: u1,
-            ///  G3_IO4 sampling mode
-            G3_IO4: u1,
-            ///  G4_IO1 sampling mode
-            G4_IO1: u1,
-            ///  G4_IO2 sampling mode
-            G4_IO2: u1,
-            ///  G4_IO3 sampling mode
-            G4_IO3: u1,
-            ///  G4_IO4 sampling mode
-            G4_IO4: u1,
-            ///  G5_IO1 sampling mode
-            G5_IO1: u1,
-            ///  G5_IO2 sampling mode
-            G5_IO2: u1,
-            ///  G5_IO3 sampling mode
-            G5_IO3: u1,
-            ///  G5_IO4 sampling mode
-            G5_IO4: u1,
-            ///  G6_IO1 sampling mode
-            G6_IO1: u1,
-            ///  G6_IO2 sampling mode
-            G6_IO2: u1,
-            ///  G6_IO3 sampling mode
-            G6_IO3: u1,
-            ///  G6_IO4 sampling mode
-            G6_IO4: u1,
-            ///  G7_IO1 sampling mode
-            G7_IO1: u1,
-            ///  G7_IO2 sampling mode
-            G7_IO2: u1,
-            ///  G7_IO3 sampling mode
-            G7_IO3: u1,
-            ///  G7_IO4 sampling mode
-            G7_IO4: u1,
-            ///  G8_IO1 sampling mode
-            G8_IO1: u1,
-            ///  G8_IO2 sampling mode
-            G8_IO2: u1,
-            ///  G8_IO3 sampling mode
-            G8_IO3: u1,
-            ///  G8_IO4 sampling mode
-            G8_IO4: u1,
-        }),
-        reserved40: [4]u8,
-        ///  I/O channel control register
-        IOCCR: mmio.Mmio(packed struct(u32) {
-            ///  G1_IO1 channel mode
-            G1_IO1: u1,
-            ///  G1_IO2 channel mode
-            G1_IO2: u1,
-            ///  G1_IO3 channel mode
-            G1_IO3: u1,
-            ///  G1_IO4 channel mode
-            G1_IO4: u1,
-            ///  G2_IO1 channel mode
-            G2_IO1: u1,
-            ///  G2_IO2 channel mode
-            G2_IO2: u1,
-            ///  G2_IO3 channel mode
-            G2_IO3: u1,
-            ///  G2_IO4 channel mode
-            G2_IO4: u1,
-            ///  G3_IO1 channel mode
-            G3_IO1: u1,
-            ///  G3_IO2 channel mode
-            G3_IO2: u1,
-            ///  G3_IO3 channel mode
-            G3_IO3: u1,
-            ///  G3_IO4 channel mode
-            G3_IO4: u1,
-            ///  G4_IO1 channel mode
-            G4_IO1: u1,
-            ///  G4_IO2 channel mode
-            G4_IO2: u1,
-            ///  G4_IO3 channel mode
-            G4_IO3: u1,
-            ///  G4_IO4 channel mode
-            G4_IO4: u1,
-            ///  G5_IO1 channel mode
-            G5_IO1: u1,
-            ///  G5_IO2 channel mode
-            G5_IO2: u1,
-            ///  G5_IO3 channel mode
-            G5_IO3: u1,
-            ///  G5_IO4 channel mode
-            G5_IO4: u1,
-            ///  G6_IO1 channel mode
-            G6_IO1: u1,
-            ///  G6_IO2 channel mode
-            G6_IO2: u1,
-            ///  G6_IO3 channel mode
-            G6_IO3: u1,
-            ///  G6_IO4 channel mode
-            G6_IO4: u1,
-            ///  G7_IO1 channel mode
-            G7_IO1: u1,
-            ///  G7_IO2 channel mode
-            G7_IO2: u1,
-            ///  G7_IO3 channel mode
-            G7_IO3: u1,
-            ///  G7_IO4 channel mode
-            G7_IO4: u1,
-            ///  G8_IO1 channel mode
-            G8_IO1: u1,
-            ///  G8_IO2 channel mode
-            G8_IO2: u1,
-            ///  G8_IO3 channel mode
-            G8_IO3: u1,
-            ///  G8_IO4 channel mode
-            G8_IO4: u1,
-        }),
-        reserved48: [4]u8,
-        ///  I/O group control status register
-        IOGCSR: mmio.Mmio(packed struct(u32) {
-            ///  Analog I/O group x enable
-            G1E: u1,
-            ///  Analog I/O group x enable
-            G2E: u1,
-            ///  Analog I/O group x enable
-            G3E: u1,
-            ///  Analog I/O group x enable
-            G4E: u1,
-            ///  Analog I/O group x enable
-            G5E: u1,
-            ///  Analog I/O group x enable
-            G6E: u1,
-            ///  Analog I/O group x enable
-            G7E: u1,
-            ///  Analog I/O group x enable
-            G8E: u1,
-            reserved16: u8,
-            ///  Analog I/O group x status
-            G1S: u1,
-            ///  Analog I/O group x status
-            G2S: u1,
-            ///  Analog I/O group x status
-            G3S: u1,
-            ///  Analog I/O group x status
-            G4S: u1,
-            ///  Analog I/O group x status
-            G5S: u1,
-            ///  Analog I/O group x status
-            G6S: u1,
-            ///  Analog I/O group x status
-            G7S: u1,
-            ///  Analog I/O group x status
-            G8S: u1,
-            padding: u8,
-        }),
-        ///  I/O group x counter register
-        IOG1CR: mmio.Mmio(packed struct(u32) {
-            ///  Counter value
-            CNT: u14,
-            padding: u18,
-        }),
-        ///  I/O group x counter register
-        IOG2CR: mmio.Mmio(packed struct(u32) {
-            ///  Counter value
-            CNT: u14,
-            padding: u18,
-        }),
-        ///  I/O group x counter register
-        IOG3CR: mmio.Mmio(packed struct(u32) {
-            ///  Counter value
-            CNT: u14,
-            padding: u18,
-        }),
-        ///  I/O group x counter register
-        IOG4CR: mmio.Mmio(packed struct(u32) {
-            ///  Counter value
-            CNT: u14,
-            padding: u18,
-        }),
-        ///  I/O group x counter register
-        IOG5CR: mmio.Mmio(packed struct(u32) {
-            ///  Counter value
-            CNT: u14,
-            padding: u18,
-        }),
-        ///  I/O group x counter register
-        IOG6CR: mmio.Mmio(packed struct(u32) {
-            ///  Counter value
-            CNT: u14,
-            padding: u18,
-        }),
-        ///  I/O group x counter register
-        IOG7CR: mmio.Mmio(packed struct(u32) {
-            ///  Counter value
-            CNT: u14,
-            padding: u18,
-        }),
-        ///  I/O group x counter register
-        IOG8CR: mmio.Mmio(packed struct(u32) {
-            ///  Counter value
-            CNT: u14,
-            padding: u18,
-        }),
-    };
-
-    ///  cyclic redundancy check calculation unit
-    pub const CRC = extern struct {
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data register bits
-            DR: u32,
-        }),
-        ///  Independent data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  General-purpose 8-bit data register bits
-            IDR: u8,
-            padding: u24,
-        }),
-        ///  Control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  reset bit
-            RESET: u1,
-            reserved3: u2,
-            ///  Polynomial size
-            POLYSIZE: u2,
-            ///  Reverse input data
-            REV_IN: u2,
-            ///  Reverse output data
-            REV_OUT: u1,
-            padding: u24,
-        }),
-        reserved16: [4]u8,
-        ///  Initial CRC value
-        INIT: mmio.Mmio(packed struct(u32) {
-            ///  Programmable initial CRC value
-            INIT: u32,
-        }),
-        ///  CRC polynomial
-        POL: mmio.Mmio(packed struct(u32) {
-            ///  Programmable polynomial
-            POL: u32,
-        }),
-    };
-
-    ///  Flash
-    pub const Flash = extern struct {
-        ///  Flash access control register
-        ACR: mmio.Mmio(packed struct(u32) {
-            ///  LATENCY
-            LATENCY: u3,
-            reserved4: u1,
-            ///  PRFTBE
-            PRFTBE: u1,
-            ///  PRFTBS
-            PRFTBS: u1,
-            padding: u26,
-        }),
-        ///  Flash key register
-        KEYR: mmio.Mmio(packed struct(u32) {
-            ///  Flash Key
-            FKEYR: u32,
-        }),
-        ///  Flash option key register
-        OPTKEYR: mmio.Mmio(packed struct(u32) {
-            ///  Option byte key
-            OPTKEYR: u32,
-        }),
-        ///  Flash status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Busy
-            BSY: u1,
-            reserved2: u1,
-            ///  Programming error
-            PGERR: u1,
-            reserved4: u1,
-            ///  Write protection error
-            WRPRT: u1,
-            ///  End of operation
-            EOP: u1,
-            padding: u26,
-        }),
-        ///  Flash control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Programming
-            PG: u1,
-            ///  Page erase
-            PER: u1,
-            ///  Mass erase
-            MER: u1,
-            reserved4: u1,
-            ///  Option byte programming
-            OPTPG: u1,
-            ///  Option byte erase
-            OPTER: u1,
-            ///  Start
-            STRT: u1,
-            ///  Lock
-            LOCK: u1,
-            reserved9: u1,
-            ///  Option bytes write enable
-            OPTWRE: u1,
-            ///  Error interrupt enable
-            ERRIE: u1,
-            reserved12: u1,
-            ///  End of operation interrupt enable
-            EOPIE: u1,
-            ///  Force option byte loading
-            FORCE_OPTLOAD: u1,
-            padding: u18,
-        }),
-        ///  Flash address register
-        AR: mmio.Mmio(packed struct(u32) {
-            ///  Flash address
-            FAR: u32,
-        }),
-        reserved28: [4]u8,
-        ///  Option byte register
-        OBR: mmio.Mmio(packed struct(u32) {
-            ///  Option byte error
-            OPTERR: u1,
-            ///  Level 1 protection status
-            LEVEL1_PROT: u1,
-            ///  Level 2 protection status
-            LEVEL2_PROT: u1,
-            reserved8: u5,
-            ///  WDG_SW
-            WDG_SW: u1,
-            ///  nRST_STOP
-            nRST_STOP: u1,
-            ///  nRST_STDBY
-            nRST_STDBY: u1,
-            reserved12: u1,
-            ///  BOOT1
-            BOOT1: u1,
-            ///  VDDA_MONITOR
-            VDDA_MONITOR: u1,
-            ///  SRAM_PARITY_CHECK
-            SRAM_PARITY_CHECK: u1,
-            reserved16: u1,
-            ///  Data0
-            Data0: u8,
-            ///  Data1
-            Data1: u8,
-        }),
-        ///  Write protection register
-        WRPR: mmio.Mmio(packed struct(u32) {
-            ///  Write protect
-            WRP: u32,
-        }),
-    };
-
-    ///  Reset and clock control
-    pub const RCC = extern struct {
-        ///  Clock control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Internal High Speed clock enable
-            HSION: u1,
-            ///  Internal High Speed clock ready flag
-            HSIRDY: u1,
-            reserved3: u1,
-            ///  Internal High Speed clock trimming
-            HSITRIM: u5,
-            ///  Internal High Speed clock Calibration
-            HSICAL: u8,
-            ///  External High Speed clock enable
-            HSEON: u1,
-            ///  External High Speed clock ready flag
-            HSERDY: u1,
-            ///  External High Speed clock Bypass
-            HSEBYP: u1,
-            ///  Clock Security System enable
-            CSSON: u1,
-            reserved24: u4,
-            ///  PLL enable
-            PLLON: u1,
-            ///  PLL clock ready flag
-            PLLRDY: u1,
-            padding: u6,
-        }),
-        ///  Clock configuration register (RCC_CFGR)
-        CFGR: mmio.Mmio(packed struct(u32) {
-            ///  System clock Switch
-            SW: u2,
-            ///  System Clock Switch Status
-            SWS: u2,
-            ///  AHB prescaler
-            HPRE: u4,
-            ///  APB Low speed prescaler (APB1)
-            PPRE1: u3,
-            ///  APB high speed prescaler (APB2)
-            PPRE2: u3,
-            reserved15: u1,
-            ///  PLL entry clock source
-            PLLSRC: u2,
-            ///  HSE divider for PLL entry
-            PLLXTPRE: u1,
-            ///  PLL Multiplication Factor
-            PLLMUL: u4,
-            ///  USB prescaler
-            USBPRES: u1,
-            ///  I2S external clock source selection
-            I2SSRC: u1,
-            ///  Microcontroller clock output
-            MCO: u3,
-            reserved28: u1,
-            ///  Microcontroller Clock Output Flag
-            MCOF: u1,
-            padding: u3,
-        }),
-        ///  Clock interrupt register (RCC_CIR)
-        CIR: mmio.Mmio(packed struct(u32) {
-            ///  LSI Ready Interrupt flag
-            LSIRDYF: u1,
-            ///  LSE Ready Interrupt flag
-            LSERDYF: u1,
-            ///  HSI Ready Interrupt flag
-            HSIRDYF: u1,
-            ///  HSE Ready Interrupt flag
-            HSERDYF: u1,
-            ///  PLL Ready Interrupt flag
-            PLLRDYF: u1,
-            reserved7: u2,
-            ///  Clock Security System Interrupt flag
-            CSSF: u1,
-            ///  LSI Ready Interrupt Enable
-            LSIRDYIE: u1,
-            ///  LSE Ready Interrupt Enable
-            LSERDYIE: u1,
-            ///  HSI Ready Interrupt Enable
-            HSIRDYIE: u1,
-            ///  HSE Ready Interrupt Enable
-            HSERDYIE: u1,
-            ///  PLL Ready Interrupt Enable
-            PLLRDYIE: u1,
-            reserved16: u3,
-            ///  LSI Ready Interrupt Clear
-            LSIRDYC: u1,
-            ///  LSE Ready Interrupt Clear
-            LSERDYC: u1,
-            ///  HSI Ready Interrupt Clear
-            HSIRDYC: u1,
-            ///  HSE Ready Interrupt Clear
-            HSERDYC: u1,
-            ///  PLL Ready Interrupt Clear
-            PLLRDYC: u1,
-            reserved23: u2,
-            ///  Clock security system interrupt clear
-            CSSC: u1,
-            padding: u8,
-        }),
-        ///  APB2 peripheral reset register (RCC_APB2RSTR)
-        APB2RSTR: mmio.Mmio(packed struct(u32) {
-            ///  SYSCFG and COMP reset
-            SYSCFGRST: u1,
-            reserved11: u10,
-            ///  TIM1 timer reset
-            TIM1RST: u1,
-            ///  SPI 1 reset
-            SPI1RST: u1,
-            ///  TIM8 timer reset
-            TIM8RST: u1,
-            ///  USART1 reset
-            USART1RST: u1,
-            reserved16: u1,
-            ///  TIM15 timer reset
-            TIM15RST: u1,
-            ///  TIM16 timer reset
-            TIM16RST: u1,
-            ///  TIM17 timer reset
-            TIM17RST: u1,
-            padding: u13,
-        }),
-        ///  APB1 peripheral reset register (RCC_APB1RSTR)
-        APB1RSTR: mmio.Mmio(packed struct(u32) {
-            ///  Timer 2 reset
-            TIM2RST: u1,
-            ///  Timer 3 reset
-            TIM3RST: u1,
-            ///  Timer 14 reset
-            TIM4RST: u1,
-            reserved4: u1,
-            ///  Timer 6 reset
-            TIM6RST: u1,
-            ///  Timer 7 reset
-            TIM7RST: u1,
-            reserved11: u5,
-            ///  Window watchdog reset
-            WWDGRST: u1,
-            reserved14: u2,
-            ///  SPI2 reset
-            SPI2RST: u1,
-            ///  SPI3 reset
-            SPI3RST: u1,
-            reserved17: u1,
-            ///  USART 2 reset
-            USART2RST: u1,
-            ///  USART3 reset
-            USART3RST: u1,
-            ///  UART 4 reset
-            UART4RST: u1,
-            ///  UART 5 reset
-            UART5RST: u1,
-            ///  I2C1 reset
-            I2C1RST: u1,
-            ///  I2C2 reset
-            I2C2RST: u1,
-            ///  USB reset
-            USBRST: u1,
-            reserved25: u1,
-            ///  CAN reset
-            CANRST: u1,
-            reserved28: u2,
-            ///  Power interface reset
-            PWRRST: u1,
-            ///  DAC interface reset
-            DACRST: u1,
-            ///  I2C3 reset
-            I2C3RST: u1,
-            padding: u1,
-        }),
-        ///  AHB Peripheral Clock enable register (RCC_AHBENR)
-        AHBENR: mmio.Mmio(packed struct(u32) {
-            ///  DMA1 clock enable
-            DMAEN: u1,
-            ///  DMA2 clock enable
-            DMA2EN: u1,
-            ///  SRAM interface clock enable
-            SRAMEN: u1,
-            reserved4: u1,
-            ///  FLITF clock enable
-            FLITFEN: u1,
-            ///  FMC clock enable
-            FMCEN: u1,
-            ///  CRC clock enable
-            CRCEN: u1,
-            reserved16: u9,
-            ///  IO port H clock enable
-            IOPHEN: u1,
-            ///  I/O port A clock enable
-            IOPAEN: u1,
-            ///  I/O port B clock enable
-            IOPBEN: u1,
-            ///  I/O port C clock enable
-            IOPCEN: u1,
-            ///  I/O port D clock enable
-            IOPDEN: u1,
-            ///  I/O port E clock enable
-            IOPEEN: u1,
-            ///  I/O port F clock enable
-            IOPFEN: u1,
-            ///  I/O port G clock enable
-            IOPGEN: u1,
-            ///  Touch sensing controller clock enable
-            TSCEN: u1,
-            reserved28: u3,
-            ///  ADC1 and ADC2 clock enable
-            ADC12EN: u1,
-            ///  ADC3 and ADC4 clock enable
-            ADC34EN: u1,
-            padding: u2,
-        }),
-        ///  APB2 peripheral clock enable register (RCC_APB2ENR)
-        APB2ENR: mmio.Mmio(packed struct(u32) {
-            ///  SYSCFG clock enable
-            SYSCFGEN: u1,
-            reserved11: u10,
-            ///  TIM1 Timer clock enable
-            TIM1EN: u1,
-            ///  SPI 1 clock enable
-            SPI1EN: u1,
-            ///  TIM8 Timer clock enable
-            TIM8EN: u1,
-            ///  USART1 clock enable
-            USART1EN: u1,
-            reserved16: u1,
-            ///  TIM15 timer clock enable
-            TIM15EN: u1,
-            ///  TIM16 timer clock enable
-            TIM16EN: u1,
-            ///  TIM17 timer clock enable
-            TIM17EN: u1,
-            padding: u13,
-        }),
-        ///  APB1 peripheral clock enable register (RCC_APB1ENR)
-        APB1ENR: mmio.Mmio(packed struct(u32) {
-            ///  Timer 2 clock enable
-            TIM2EN: u1,
-            ///  Timer 3 clock enable
-            TIM3EN: u1,
-            ///  Timer 4 clock enable
-            TIM4EN: u1,
-            reserved4: u1,
-            ///  Timer 6 clock enable
-            TIM6EN: u1,
-            ///  Timer 7 clock enable
-            TIM7EN: u1,
-            reserved11: u5,
-            ///  Window watchdog clock enable
-            WWDGEN: u1,
-            reserved14: u2,
-            ///  SPI 2 clock enable
-            SPI2EN: u1,
-            ///  SPI 3 clock enable
-            SPI3EN: u1,
-            reserved17: u1,
-            ///  USART 2 clock enable
-            USART2EN: u1,
-            ///  USART 3 clock enable
-            USART3EN: u1,
-            ///  USART 4 clock enable
-            USART4EN: u1,
-            ///  USART 5 clock enable
-            USART5EN: u1,
-            ///  I2C 1 clock enable
-            I2C1EN: u1,
-            ///  I2C 2 clock enable
-            I2C2EN: u1,
-            ///  USB clock enable
-            USBEN: u1,
-            reserved25: u1,
-            ///  CAN clock enable
-            CANEN: u1,
-            ///  DAC2 interface clock enable
-            DAC2EN: u1,
-            reserved28: u1,
-            ///  Power interface clock enable
-            PWREN: u1,
-            ///  DAC interface clock enable
-            DACEN: u1,
-            ///  I2C3 clock enable
-            I2C3EN: u1,
-            padding: u1,
-        }),
-        ///  Backup domain control register (RCC_BDCR)
-        BDCR: mmio.Mmio(packed struct(u32) {
-            ///  External Low Speed oscillator enable
-            LSEON: u1,
-            ///  External Low Speed oscillator ready
-            LSERDY: u1,
-            ///  External Low Speed oscillator bypass
-            LSEBYP: u1,
-            ///  LSE oscillator drive capability
-            LSEDRV: u2,
-            reserved8: u3,
-            ///  RTC clock source selection
-            RTCSEL: u2,
-            reserved15: u5,
-            ///  RTC clock enable
-            RTCEN: u1,
-            ///  Backup domain software reset
-            BDRST: u1,
-            padding: u15,
-        }),
-        ///  Control/status register (RCC_CSR)
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  Internal low speed oscillator enable
-            LSION: u1,
-            ///  Internal low speed oscillator ready
-            LSIRDY: u1,
-            reserved24: u22,
-            ///  Remove reset flag
-            RMVF: u1,
-            ///  Option byte loader reset flag
-            OBLRSTF: u1,
-            ///  PIN reset flag
-            PINRSTF: u1,
-            ///  POR/PDR reset flag
-            PORRSTF: u1,
-            ///  Software reset flag
-            SFTRSTF: u1,
-            ///  Independent watchdog reset flag
-            IWDGRSTF: u1,
-            ///  Window watchdog reset flag
-            WWDGRSTF: u1,
-            ///  Low-power reset flag
-            LPWRRSTF: u1,
-        }),
-        ///  AHB peripheral reset register
-        AHBRSTR: mmio.Mmio(packed struct(u32) {
-            reserved5: u5,
-            ///  FMC reset
-            FMCRST: u1,
-            reserved16: u10,
-            ///  I/O port H reset
-            IOPHRST: u1,
-            ///  I/O port A reset
-            IOPARST: u1,
-            ///  I/O port B reset
-            IOPBRST: u1,
-            ///  I/O port C reset
-            IOPCRST: u1,
-            ///  I/O port D reset
-            IOPDRST: u1,
-            ///  I/O port E reset
-            IOPERST: u1,
-            ///  I/O port F reset
-            IOPFRST: u1,
-            ///  Touch sensing controller reset
-            IOPGRST: u1,
-            ///  Touch sensing controller reset
-            TSCRST: u1,
-            reserved28: u3,
-            ///  ADC1 and ADC2 reset
-            ADC12RST: u1,
-            ///  ADC3 and ADC4 reset
-            ADC34RST: u1,
-            padding: u2,
-        }),
-        ///  Clock configuration register 2
-        CFGR2: mmio.Mmio(packed struct(u32) {
-            ///  PREDIV division factor
-            PREDIV: u4,
-            ///  ADC1 and ADC2 prescaler
-            ADC12PRES: u5,
-            ///  ADC3 and ADC4 prescaler
-            ADC34PRES: u5,
-            padding: u18,
-        }),
-        ///  Clock configuration register 3
-        CFGR3: mmio.Mmio(packed struct(u32) {
-            ///  USART1 clock source selection
-            USART1SW: u2,
-            reserved4: u2,
-            ///  I2C1 clock source selection
-            I2C1SW: u1,
-            ///  I2C2 clock source selection
-            I2C2SW: u1,
-            ///  I2C3 clock source selection
-            I2C3SW: u1,
-            reserved8: u1,
-            ///  Timer1 clock source selection
-            TIM1SW: u1,
-            ///  Timer8 clock source selection
-            TIM8SW: u1,
-            reserved16: u6,
-            ///  USART2 clock source selection
-            USART2SW: u2,
-            ///  USART3 clock source selection
-            USART3SW: u2,
-            ///  UART4 clock source selection
-            UART4SW: u2,
-            ///  UART5 clock source selection
-            UART5SW: u2,
-            padding: u8,
-        }),
-    };
-
-    ///  DMA controller 1
-    pub const DMA1 = extern struct {
-        ///  DMA interrupt status register (DMA_ISR)
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  Channel 1 Global interrupt flag
-            GIF1: u1,
-            ///  Channel 1 Transfer Complete flag
-            TCIF1: u1,
-            ///  Channel 1 Half Transfer Complete flag
-            HTIF1: u1,
-            ///  Channel 1 Transfer Error flag
-            TEIF1: u1,
-            ///  Channel 2 Global interrupt flag
-            GIF2: u1,
-            ///  Channel 2 Transfer Complete flag
-            TCIF2: u1,
-            ///  Channel 2 Half Transfer Complete flag
-            HTIF2: u1,
-            ///  Channel 2 Transfer Error flag
-            TEIF2: u1,
-            ///  Channel 3 Global interrupt flag
-            GIF3: u1,
-            ///  Channel 3 Transfer Complete flag
-            TCIF3: u1,
-            ///  Channel 3 Half Transfer Complete flag
-            HTIF3: u1,
-            ///  Channel 3 Transfer Error flag
-            TEIF3: u1,
-            ///  Channel 4 Global interrupt flag
-            GIF4: u1,
-            ///  Channel 4 Transfer Complete flag
-            TCIF4: u1,
-            ///  Channel 4 Half Transfer Complete flag
-            HTIF4: u1,
-            ///  Channel 4 Transfer Error flag
-            TEIF4: u1,
-            ///  Channel 5 Global interrupt flag
-            GIF5: u1,
-            ///  Channel 5 Transfer Complete flag
-            TCIF5: u1,
-            ///  Channel 5 Half Transfer Complete flag
-            HTIF5: u1,
-            ///  Channel 5 Transfer Error flag
-            TEIF5: u1,
-            ///  Channel 6 Global interrupt flag
-            GIF6: u1,
-            ///  Channel 6 Transfer Complete flag
-            TCIF6: u1,
-            ///  Channel 6 Half Transfer Complete flag
-            HTIF6: u1,
-            ///  Channel 6 Transfer Error flag
-            TEIF6: u1,
-            ///  Channel 7 Global interrupt flag
-            GIF7: u1,
-            ///  Channel 7 Transfer Complete flag
-            TCIF7: u1,
-            ///  Channel 7 Half Transfer Complete flag
-            HTIF7: u1,
-            ///  Channel 7 Transfer Error flag
-            TEIF7: u1,
-            padding: u4,
-        }),
-        ///  DMA interrupt flag clear register (DMA_IFCR)
-        IFCR: mmio.Mmio(packed struct(u32) {
-            ///  Channel 1 Global interrupt clear
-            CGIF1: u1,
-            ///  Channel 1 Transfer Complete clear
-            CTCIF1: u1,
-            ///  Channel 1 Half Transfer clear
-            CHTIF1: u1,
-            ///  Channel 1 Transfer Error clear
-            CTEIF1: u1,
-            ///  Channel 2 Global interrupt clear
-            CGIF2: u1,
-            ///  Channel 2 Transfer Complete clear
-            CTCIF2: u1,
-            ///  Channel 2 Half Transfer clear
-            CHTIF2: u1,
-            ///  Channel 2 Transfer Error clear
-            CTEIF2: u1,
-            ///  Channel 3 Global interrupt clear
-            CGIF3: u1,
-            ///  Channel 3 Transfer Complete clear
-            CTCIF3: u1,
-            ///  Channel 3 Half Transfer clear
-            CHTIF3: u1,
-            ///  Channel 3 Transfer Error clear
-            CTEIF3: u1,
-            ///  Channel 4 Global interrupt clear
-            CGIF4: u1,
-            ///  Channel 4 Transfer Complete clear
-            CTCIF4: u1,
-            ///  Channel 4 Half Transfer clear
-            CHTIF4: u1,
-            ///  Channel 4 Transfer Error clear
-            CTEIF4: u1,
-            ///  Channel 5 Global interrupt clear
-            CGIF5: u1,
-            ///  Channel 5 Transfer Complete clear
-            CTCIF5: u1,
-            ///  Channel 5 Half Transfer clear
-            CHTIF5: u1,
-            ///  Channel 5 Transfer Error clear
-            CTEIF5: u1,
-            ///  Channel 6 Global interrupt clear
-            CGIF6: u1,
-            ///  Channel 6 Transfer Complete clear
-            CTCIF6: u1,
-            ///  Channel 6 Half Transfer clear
-            CHTIF6: u1,
-            ///  Channel 6 Transfer Error clear
-            CTEIF6: u1,
-            ///  Channel 7 Global interrupt clear
-            CGIF7: u1,
-            ///  Channel 7 Transfer Complete clear
-            CTCIF7: u1,
-            ///  Channel 7 Half Transfer clear
-            CHTIF7: u1,
-            ///  Channel 7 Transfer Error clear
-            CTEIF7: u1,
-            padding: u4,
-        }),
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 1 number of data register
-        CNDTR1: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 1 peripheral address register
-        CPAR1: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 1 memory address register
-        CMAR1: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved28: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 2 number of data register
-        CNDTR2: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 2 peripheral address register
-        CPAR2: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 2 memory address register
-        CMAR2: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved48: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 3 number of data register
-        CNDTR3: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 3 peripheral address register
-        CPAR3: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 3 memory address register
-        CMAR3: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved68: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 4 number of data register
-        CNDTR4: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 4 peripheral address register
-        CPAR4: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 4 memory address register
-        CMAR4: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved88: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR5: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 5 number of data register
-        CNDTR5: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 5 peripheral address register
-        CPAR5: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 5 memory address register
-        CMAR5: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved108: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR6: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 6 number of data register
-        CNDTR6: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 6 peripheral address register
-        CPAR6: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 6 memory address register
-        CMAR6: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        reserved128: [4]u8,
-        ///  DMA channel configuration register (DMA_CCR)
-        CCR7: mmio.Mmio(packed struct(u32) {
-            ///  Channel enable
-            EN: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Half Transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Data transfer direction
-            DIR: u1,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral size
-            PSIZE: u2,
-            ///  Memory size
-            MSIZE: u2,
-            ///  Channel Priority level
-            PL: u2,
-            ///  Memory to memory mode
-            MEM2MEM: u1,
-            padding: u17,
-        }),
-        ///  DMA channel 7 number of data register
-        CNDTR7: mmio.Mmio(packed struct(u32) {
-            ///  Number of data to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  DMA channel 7 peripheral address register
-        CPAR7: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  DMA channel 7 memory address register
-        CMAR7: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-    };
-
-    ///  Floting point unit
-    pub const FPU = extern struct {
-        ///  Floating-point context control register
-        FPCCR: mmio.Mmio(packed struct(u32) {
-            ///  LSPACT
-            LSPACT: u1,
-            ///  USER
-            USER: u1,
-            reserved3: u1,
-            ///  THREAD
-            THREAD: u1,
-            ///  HFRDY
-            HFRDY: u1,
-            ///  MMRDY
-            MMRDY: u1,
-            ///  BFRDY
-            BFRDY: u1,
-            reserved8: u1,
-            ///  MONRDY
-            MONRDY: u1,
-            reserved30: u21,
-            ///  LSPEN
-            LSPEN: u1,
-            ///  ASPEN
-            ASPEN: u1,
-        }),
-        ///  Floating-point context address register
-        FPCAR: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Location of unpopulated floating-point
-            ADDRESS: u29,
-        }),
-        ///  Floating-point status control register
-        FPSCR: mmio.Mmio(packed struct(u32) {
-            ///  Invalid operation cumulative exception bit
-            IOC: u1,
-            ///  Division by zero cumulative exception bit.
-            DZC: u1,
-            ///  Overflow cumulative exception bit
-            OFC: u1,
-            ///  Underflow cumulative exception bit
-            UFC: u1,
-            ///  Inexact cumulative exception bit
-            IXC: u1,
-            reserved7: u2,
-            ///  Input denormal cumulative exception bit.
-            IDC: u1,
-            reserved22: u14,
-            ///  Rounding Mode control field
-            RMode: u2,
-            ///  Flush-to-zero mode control bit:
-            FZ: u1,
-            ///  Default NaN mode control bit
-            DN: u1,
-            ///  Alternative half-precision control bit
-            AHP: u1,
-            reserved28: u1,
-            ///  Overflow condition code flag
-            V: u1,
-            ///  Carry condition code flag
-            C: u1,
-            ///  Zero condition code flag
-            Z: u1,
-            ///  Negative condition code flag
-            N: u1,
-        }),
-    };
-
-    ///  General purpose timer
-    pub const TIM2 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            reserved11: u1,
-            ///  UIF status bit remapping
-            UIFREMAP: u1,
-            padding: u20,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            padding: u24,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            ///  OCREF clear selection
-            OCCS: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            ///  Slave mode selection bit3
-            SMS_3: u1,
-            padding: u15,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            reserved6: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            reserved8: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            reserved14: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            reserved6: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            reserved9: u2,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            padding: u19,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            reserved6: u1,
-            ///  Trigger generation
-            TG: u1,
-            padding: u25,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output compare 1 fast enable
-            OC1FE: u1,
-            ///  Output compare 1 preload enable
-            OC1PE: u1,
-            ///  Output compare 1 mode
-            OC1M: u3,
-            ///  Output compare 1 clear enable
-            OC1CE: u1,
-            ///  Capture/Compare 2 selection
-            CC2S: u2,
-            ///  Output compare 2 fast enable
-            OC2FE: u1,
-            ///  Output compare 2 preload enable
-            OC2PE: u1,
-            ///  Output compare 2 mode
-            OC2M: u3,
-            ///  Output compare 2 clear enable
-            OC2CE: u1,
-            ///  Output compare 1 mode bit 3
-            OC1M_3: u1,
-            reserved24: u7,
-            ///  Output compare 2 mode bit 3
-            OC2M_3: u1,
-            padding: u7,
-        }),
-        ///  capture/compare mode register 2 (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 3 selection
-            CC3S: u2,
-            ///  Output compare 3 fast enable
-            OC3FE: u1,
-            ///  Output compare 3 preload enable
-            OC3PE: u1,
-            ///  Output compare 3 mode
-            OC3M: u3,
-            ///  Output compare 3 clear enable
-            OC3CE: u1,
-            ///  Capture/Compare 4 selection
-            CC4S: u2,
-            ///  Output compare 4 fast enable
-            OC4FE: u1,
-            ///  Output compare 4 preload enable
-            OC4PE: u1,
-            ///  Output compare 4 mode
-            OC4M: u3,
-            ///  Output compare 4 clear enable
-            O24CE: u1,
-            ///  Output compare 3 mode bit3
-            OC3M_3: u1,
-            reserved24: u7,
-            ///  Output compare 4 mode bit3
-            OC4M_3: u1,
-            padding: u7,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved7: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            reserved11: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            reserved15: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4NP: u1,
-            padding: u16,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  Low counter value
-            CNTL: u16,
-            ///  High counter value
-            CNTH: u15,
-            ///  if IUFREMAP=0 than CNT with read write access else UIFCPY with read only access
-            CNT_or_UIFCPY: u1,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Low Auto-reload value
-            ARRL: u16,
-            ///  High Auto-reload value
-            ARRH: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 1 value
-            CCR1L: u16,
-            ///  High Capture/Compare 1 value (on TIM2)
-            CCR1H: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 2 value
-            CCR2L: u16,
-            ///  High Capture/Compare 2 value (on TIM2)
-            CCR2H: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR3L: u16,
-            ///  High Capture/Compare value (on TIM2)
-            CCR3H: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR4L: u16,
-            ///  High Capture/Compare value (on TIM2)
-            CCR4H: u16,
-        }),
-        reserved72: [4]u8,
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Nested Vectored Interrupt Controller
-    pub const NVIC = extern struct {
-        ///  Interrupt Set-Enable Register
-        ISER0: mmio.Mmio(packed struct(u32) {
-            ///  SETENA
-            SETENA: u32,
-        }),
-        ///  Interrupt Set-Enable Register
-        ISER1: mmio.Mmio(packed struct(u32) {
-            ///  SETENA
-            SETENA: u32,
-        }),
-        ///  Interrupt Set-Enable Register
-        ISER2: mmio.Mmio(packed struct(u32) {
-            ///  SETENA
-            SETENA: u32,
-        }),
-        reserved128: [116]u8,
-        ///  Interrupt Clear-Enable Register
-        ICER0: mmio.Mmio(packed struct(u32) {
-            ///  CLRENA
-            CLRENA: u32,
-        }),
-        ///  Interrupt Clear-Enable Register
-        ICER1: mmio.Mmio(packed struct(u32) {
-            ///  CLRENA
-            CLRENA: u32,
-        }),
-        ///  Interrupt Clear-Enable Register
-        ICER2: mmio.Mmio(packed struct(u32) {
-            ///  CLRENA
-            CLRENA: u32,
-        }),
-        reserved256: [116]u8,
-        ///  Interrupt Set-Pending Register
-        ISPR0: mmio.Mmio(packed struct(u32) {
-            ///  SETPEND
-            SETPEND: u32,
-        }),
-        ///  Interrupt Set-Pending Register
-        ISPR1: mmio.Mmio(packed struct(u32) {
-            ///  SETPEND
-            SETPEND: u32,
-        }),
-        ///  Interrupt Set-Pending Register
-        ISPR2: mmio.Mmio(packed struct(u32) {
-            ///  SETPEND
-            SETPEND: u32,
-        }),
-        reserved384: [116]u8,
-        ///  Interrupt Clear-Pending Register
-        ICPR0: mmio.Mmio(packed struct(u32) {
-            ///  CLRPEND
-            CLRPEND: u32,
-        }),
-        ///  Interrupt Clear-Pending Register
-        ICPR1: mmio.Mmio(packed struct(u32) {
-            ///  CLRPEND
-            CLRPEND: u32,
-        }),
-        ///  Interrupt Clear-Pending Register
-        ICPR2: mmio.Mmio(packed struct(u32) {
-            ///  CLRPEND
-            CLRPEND: u32,
-        }),
-        reserved512: [116]u8,
-        ///  Interrupt Active Bit Register
-        IABR0: mmio.Mmio(packed struct(u32) {
-            ///  ACTIVE
-            ACTIVE: u32,
-        }),
-        ///  Interrupt Active Bit Register
-        IABR1: mmio.Mmio(packed struct(u32) {
-            ///  ACTIVE
-            ACTIVE: u32,
-        }),
-        ///  Interrupt Active Bit Register
-        IABR2: mmio.Mmio(packed struct(u32) {
-            ///  ACTIVE
-            ACTIVE: u32,
-        }),
-        reserved768: [244]u8,
-        ///  Interrupt Priority Register
-        IPR0: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR1: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR2: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR3: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR4: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR5: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR6: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR7: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR8: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR9: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR10: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR11: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR12: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR13: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR14: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR15: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR16: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR17: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR18: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR19: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR20: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-    };
-
-    ///  Flexible memory controller
-    pub const FMC = extern struct {
-        ///  SRAM/NOR-Flash chip-select control register 1
-        BCR1: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            reserved11: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            ///  CCLKEN
-            CCLKEN: u1,
-            padding: u11,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 1
-        BTR1: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 2
-        BCR2: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 2
-        BTR2: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 3
-        BCR3: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 3
-        BTR3: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 4
-        BCR4: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 4
-        BTR4: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved96: [64]u8,
-        ///  PC Card/NAND Flash control register 2
-        PCR2: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 2
-        SR2: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 2
-        PMEM2: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 2
-        PATT2: mmio.Mmio(packed struct(u32) {
-            ///  ATTSETx
-            ATTSETx: u8,
-            ///  ATTWAITx
-            ATTWAITx: u8,
-            ///  ATTHOLDx
-            ATTHOLDx: u8,
-            ///  ATTHIZx
-            ATTHIZx: u8,
-        }),
-        reserved116: [4]u8,
-        ///  ECC result register 2
-        ECCR2: mmio.Mmio(packed struct(u32) {
-            ///  ECCx
-            ECCx: u32,
-        }),
-        reserved128: [8]u8,
-        ///  PC Card/NAND Flash control register 3
-        PCR3: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 3
-        SR3: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 3
-        PMEM3: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 3
-        PATT3: mmio.Mmio(packed struct(u32) {
-            ///  ATTSETx
-            ATTSETx: u8,
-            ///  ATTWAITx
-            ATTWAITx: u8,
-            ///  ATTHOLDx
-            ATTHOLDx: u8,
-            ///  ATTHIZx
-            ATTHIZx: u8,
-        }),
-        reserved148: [4]u8,
-        ///  ECC result register 3
-        ECCR3: mmio.Mmio(packed struct(u32) {
-            ///  ECCx
-            ECCx: u32,
-        }),
-        reserved160: [8]u8,
-        ///  PC Card/NAND Flash control register 4
-        PCR4: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 4
-        SR4: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 4
-        PMEM4: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 4
-        PATT4: mmio.Mmio(packed struct(u32) {
-            ///  ATTSETx
-            ATTSETx: u8,
-            ///  ATTWAITx
-            ATTWAITx: u8,
-            ///  ATTHOLDx
-            ATTHOLDx: u8,
-            ///  ATTHIZx
-            ATTHIZx: u8,
-        }),
-        ///  I/O space timing register 4
-        PIO4: mmio.Mmio(packed struct(u32) {
-            ///  IOSETx
-            IOSETx: u8,
-            ///  IOWAITx
-            IOWAITx: u8,
-            ///  IOHOLDx
-            IOHOLDx: u8,
-            ///  IOHIZx
-            IOHIZx: u8,
-        }),
-        reserved260: [80]u8,
-        ///  SRAM/NOR-Flash write timing registers 1
-        BWTR1: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  Bus turnaround phase duration
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved268: [4]u8,
-        ///  SRAM/NOR-Flash write timing registers 2
-        BWTR2: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  Bus turnaround phase duration
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved276: [4]u8,
-        ///  SRAM/NOR-Flash write timing registers 3
-        BWTR3: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  Bus turnaround phase duration
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved284: [4]u8,
-        ///  SRAM/NOR-Flash write timing registers 4
-        BWTR4: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  Bus turnaround phase duration
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-    };
-
-    ///  General purpose timers
-    pub const TIM15 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            reserved7: u3,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            reserved11: u1,
-            ///  UIF status bit remapping
-            UIFREMAP: u1,
-            padding: u20,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/compare preloaded control
-            CCPC: u1,
-            reserved2: u1,
-            ///  Capture/compare control update selection
-            CCUS: u1,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            ///  Output Idle state 1
-            OIS1: u1,
-            ///  Output Idle state 1
-            OIS1N: u1,
-            ///  Output Idle state 2
-            OIS2: u1,
-            padding: u21,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            reserved16: u8,
-            ///  Slave mode selection bit 3
-            SMS_3: u1,
-            padding: u15,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            reserved5: u2,
-            ///  COM interrupt enable
-            COMIE: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            ///  Break interrupt enable
-            BIE: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            reserved13: u2,
-            ///  COM DMA request enable
-            COMDE: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            reserved5: u2,
-            ///  COM interrupt flag
-            COMIF: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            ///  Break interrupt flag
-            BIF: u1,
-            reserved9: u1,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            padding: u21,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            reserved5: u2,
-            ///  Capture/Compare control update generation
-            COMG: u1,
-            ///  Trigger generation
-            TG: u1,
-            ///  Break generation
-            BG: u1,
-            padding: u24,
-        }),
-        ///  capture/compare mode register (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            reserved8: u1,
-            ///  Capture/Compare 2 selection
-            CC2S: u2,
-            ///  Output Compare 2 fast enable
-            OC2FE: u1,
-            ///  Output Compare 2 preload enable
-            OC2PE: u1,
-            ///  Output Compare 2 mode
-            OC2M: u3,
-            reserved16: u1,
-            ///  Output Compare 1 mode bit 3
-            OC1M_3: u1,
-            reserved24: u7,
-            ///  Output Compare 2 mode bit 3
-            OC2M_3: u1,
-            padding: u7,
-        }),
-        reserved32: [4]u8,
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            ///  Capture/Compare 1 complementary output enable
-            CC1NE: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved7: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            padding: u24,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            reserved31: u15,
-            ///  UIF copy
-            UIFCPY: u1,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        ///  repetition counter register
-        RCR: mmio.Mmio(packed struct(u32) {
-            ///  Repetition counter value
-            REP: u8,
-            padding: u24,
-        }),
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 2 value
-            CCR2: u16,
-            padding: u16,
-        }),
-        reserved68: [8]u8,
-        ///  break and dead-time register
-        BDTR: mmio.Mmio(packed struct(u32) {
-            ///  Dead-time generator setup
-            DTG: u8,
-            ///  Lock configuration
-            LOCK: u2,
-            ///  Off-state selection for Idle mode
-            OSSI: u1,
-            ///  Off-state selection for Run mode
-            OSSR: u1,
-            ///  Break enable
-            BKE: u1,
-            ///  Break polarity
-            BKP: u1,
-            ///  Automatic output enable
-            AOE: u1,
-            ///  Main output enable
-            MOE: u1,
-            ///  Break filter
-            BKF: u4,
-            padding: u12,
-        }),
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  General-purpose-timers
-    pub const TIM16 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            reserved7: u3,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            reserved11: u1,
-            ///  UIF status bit remapping
-            UIFREMAP: u1,
-            padding: u20,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/compare preloaded control
-            CCPC: u1,
-            reserved2: u1,
-            ///  Capture/compare control update selection
-            CCUS: u1,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            reserved8: u4,
-            ///  Output Idle state 1
-            OIS1: u1,
-            ///  Output Idle state 1
-            OIS1N: u1,
-            padding: u22,
-        }),
-        reserved12: [4]u8,
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            reserved5: u3,
-            ///  COM interrupt enable
-            COMIE: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            ///  Break interrupt enable
-            BIE: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            reserved13: u3,
-            ///  COM DMA request enable
-            COMDE: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            reserved5: u3,
-            ///  COM interrupt flag
-            COMIF: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            ///  Break interrupt flag
-            BIF: u1,
-            reserved9: u1,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            padding: u22,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            reserved5: u3,
-            ///  Capture/Compare control update generation
-            COMG: u1,
-            ///  Trigger generation
-            TG: u1,
-            ///  Break generation
-            BG: u1,
-            padding: u24,
-        }),
-        ///  capture/compare mode register (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            reserved16: u9,
-            ///  Output Compare 1 mode
-            OC1M_3: u1,
-            padding: u15,
-        }),
-        reserved32: [4]u8,
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            ///  Capture/Compare 1 complementary output enable
-            CC1NE: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            padding: u28,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            reserved31: u15,
-            ///  UIF Copy
-            UIFCPY: u1,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        ///  repetition counter register
-        RCR: mmio.Mmio(packed struct(u32) {
-            ///  Repetition counter value
-            REP: u8,
-            padding: u24,
-        }),
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        reserved68: [12]u8,
-        ///  break and dead-time register
-        BDTR: mmio.Mmio(packed struct(u32) {
-            ///  Dead-time generator setup
-            DTG: u8,
-            ///  Lock configuration
-            LOCK: u2,
-            ///  Off-state selection for Idle mode
-            OSSI: u1,
-            ///  Off-state selection for Run mode
-            OSSR: u1,
-            ///  Break enable
-            BKE: u1,
-            ///  Break polarity
-            BKP: u1,
-            ///  Automatic output enable
-            AOE: u1,
-            ///  Main output enable
-            MOE: u1,
-            ///  Break filter
-            BKF: u4,
-            padding: u12,
-        }),
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-        ///  option register
-        OR: u32,
-    };
-
-    ///  General purpose timer
-    pub const TIM17 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            reserved7: u3,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            reserved11: u1,
-            ///  UIF status bit remapping
-            UIFREMAP: u1,
-            padding: u20,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/compare preloaded control
-            CCPC: u1,
-            reserved2: u1,
-            ///  Capture/compare control update selection
-            CCUS: u1,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            reserved8: u4,
-            ///  Output Idle state 1
-            OIS1: u1,
-            ///  Output Idle state 1
-            OIS1N: u1,
-            padding: u22,
-        }),
-        reserved12: [4]u8,
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            reserved5: u3,
-            ///  COM interrupt enable
-            COMIE: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            ///  Break interrupt enable
-            BIE: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            reserved13: u3,
-            ///  COM DMA request enable
-            COMDE: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            reserved5: u3,
-            ///  COM interrupt flag
-            COMIF: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            ///  Break interrupt flag
-            BIF: u1,
-            reserved9: u1,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            padding: u22,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            reserved5: u3,
-            ///  Capture/Compare control update generation
-            COMG: u1,
-            ///  Trigger generation
-            TG: u1,
-            ///  Break generation
-            BG: u1,
-            padding: u24,
-        }),
-        ///  capture/compare mode register (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            reserved16: u9,
-            ///  Output Compare 1 mode
-            OC1M_3: u1,
-            padding: u15,
-        }),
-        reserved32: [4]u8,
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            ///  Capture/Compare 1 complementary output enable
-            CC1NE: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            padding: u28,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            reserved31: u15,
-            ///  UIF Copy
-            UIFCPY: u1,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        ///  repetition counter register
-        RCR: mmio.Mmio(packed struct(u32) {
-            ///  Repetition counter value
-            REP: u8,
-            padding: u24,
-        }),
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        reserved68: [12]u8,
-        ///  break and dead-time register
-        BDTR: mmio.Mmio(packed struct(u32) {
-            ///  Dead-time generator setup
-            DTG: u8,
-            ///  Lock configuration
-            LOCK: u2,
-            ///  Off-state selection for Idle mode
-            OSSI: u1,
-            ///  Off-state selection for Run mode
-            OSSR: u1,
-            ///  Break enable
-            BKE: u1,
-            ///  Break polarity
-            BKP: u1,
-            ///  Automatic output enable
-            AOE: u1,
-            ///  Main output enable
-            MOE: u1,
-            ///  Break filter
-            BKF: u4,
-            padding: u12,
-        }),
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Universal synchronous asynchronous receiver transmitter
-    pub const USART1 = extern struct {
-        ///  Control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  USART enable
-            UE: u1,
-            ///  USART enable in Stop mode
-            UESM: u1,
-            ///  Receiver enable
-            RE: u1,
-            ///  Transmitter enable
-            TE: u1,
-            ///  IDLE interrupt enable
-            IDLEIE: u1,
-            ///  RXNE interrupt enable
-            RXNEIE: u1,
-            ///  Transmission complete interrupt enable
-            TCIE: u1,
-            ///  interrupt enable
-            TXEIE: u1,
-            ///  PE interrupt enable
-            PEIE: u1,
-            ///  Parity selection
-            PS: u1,
-            ///  Parity control enable
-            PCE: u1,
-            ///  Receiver wakeup method
-            WAKE: u1,
-            ///  Word length
-            M: u1,
-            ///  Mute mode enable
-            MME: u1,
-            ///  Character match interrupt enable
-            CMIE: u1,
-            ///  Oversampling mode
-            OVER8: u1,
-            ///  Driver Enable deassertion time
-            DEDT: u5,
-            ///  Driver Enable assertion time
-            DEAT: u5,
-            ///  Receiver timeout interrupt enable
-            RTOIE: u1,
-            ///  End of Block interrupt enable
-            EOBIE: u1,
-            padding: u4,
-        }),
-        ///  Control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  7-bit Address Detection/4-bit Address Detection
-            ADDM7: u1,
-            ///  LIN break detection length
-            LBDL: u1,
-            ///  LIN break detection interrupt enable
-            LBDIE: u1,
-            reserved8: u1,
-            ///  Last bit clock pulse
-            LBCL: u1,
-            ///  Clock phase
-            CPHA: u1,
-            ///  Clock polarity
-            CPOL: u1,
-            ///  Clock enable
-            CLKEN: u1,
-            ///  STOP bits
-            STOP: u2,
-            ///  LIN mode enable
-            LINEN: u1,
-            ///  Swap TX/RX pins
-            SWAP: u1,
-            ///  RX pin active level inversion
-            RXINV: u1,
-            ///  TX pin active level inversion
-            TXINV: u1,
-            ///  Binary data inversion
-            DATAINV: u1,
-            ///  Most significant bit first
-            MSBFIRST: u1,
-            ///  Auto baud rate enable
-            ABREN: u1,
-            ///  Auto baud rate mode
-            ABRMOD: u2,
-            ///  Receiver timeout enable
-            RTOEN: u1,
-            ///  Address of the USART node
-            ADD0: u4,
-            ///  Address of the USART node
-            ADD4: u4,
-        }),
-        ///  Control register 3
-        CR3: mmio.Mmio(packed struct(u32) {
-            ///  Error interrupt enable
-            EIE: u1,
-            ///  IrDA mode enable
-            IREN: u1,
-            ///  IrDA low-power
-            IRLP: u1,
-            ///  Half-duplex selection
-            HDSEL: u1,
-            ///  Smartcard NACK enable
-            NACK: u1,
-            ///  Smartcard mode enable
-            SCEN: u1,
-            ///  DMA enable receiver
-            DMAR: u1,
-            ///  DMA enable transmitter
-            DMAT: u1,
-            ///  RTS enable
-            RTSE: u1,
-            ///  CTS enable
-            CTSE: u1,
-            ///  CTS interrupt enable
-            CTSIE: u1,
-            ///  One sample bit method enable
-            ONEBIT: u1,
-            ///  Overrun Disable
-            OVRDIS: u1,
-            ///  DMA Disable on Reception Error
-            DDRE: u1,
-            ///  Driver enable mode
-            DEM: u1,
-            ///  Driver enable polarity selection
-            DEP: u1,
-            reserved17: u1,
-            ///  Smartcard auto-retry count
-            SCARCNT: u3,
-            ///  Wakeup from Stop mode interrupt flag selection
-            WUS: u2,
-            ///  Wakeup from Stop mode interrupt enable
-            WUFIE: u1,
-            padding: u9,
-        }),
-        ///  Baud rate register
-        BRR: mmio.Mmio(packed struct(u32) {
-            ///  fraction of USARTDIV
-            DIV_Fraction: u4,
-            ///  mantissa of USARTDIV
-            DIV_Mantissa: u12,
-            padding: u16,
-        }),
-        ///  Guard time and prescaler register
-        GTPR: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u8,
-            ///  Guard time value
-            GT: u8,
-            padding: u16,
-        }),
-        ///  Receiver timeout register
-        RTOR: mmio.Mmio(packed struct(u32) {
-            ///  Receiver timeout value
-            RTO: u24,
-            ///  Block Length
-            BLEN: u8,
-        }),
-        ///  Request register
-        RQR: mmio.Mmio(packed struct(u32) {
-            ///  Auto baud rate request
-            ABRRQ: u1,
-            ///  Send break request
-            SBKRQ: u1,
-            ///  Mute mode request
-            MMRQ: u1,
-            ///  Receive data flush request
-            RXFRQ: u1,
-            ///  Transmit data flush request
-            TXFRQ: u1,
-            padding: u27,
-        }),
-        ///  Interrupt & status register
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  Parity error
-            PE: u1,
-            ///  Framing error
-            FE: u1,
-            ///  Noise detected flag
-            NF: u1,
-            ///  Overrun error
-            ORE: u1,
-            ///  Idle line detected
-            IDLE: u1,
-            ///  Read data register not empty
-            RXNE: u1,
-            ///  Transmission complete
-            TC: u1,
-            ///  Transmit data register empty
-            TXE: u1,
-            ///  LIN break detection flag
-            LBDF: u1,
-            ///  CTS interrupt flag
-            CTSIF: u1,
-            ///  CTS flag
-            CTS: u1,
-            ///  Receiver timeout
-            RTOF: u1,
-            ///  End of block flag
-            EOBF: u1,
-            reserved14: u1,
-            ///  Auto baud rate error
-            ABRE: u1,
-            ///  Auto baud rate flag
-            ABRF: u1,
-            ///  Busy flag
-            BUSY: u1,
-            ///  character match flag
-            CMF: u1,
-            ///  Send break flag
-            SBKF: u1,
-            ///  Receiver wakeup from Mute mode
-            RWU: u1,
-            ///  Wakeup from Stop mode flag
-            WUF: u1,
-            ///  Transmit enable acknowledge flag
-            TEACK: u1,
-            ///  Receive enable acknowledge flag
-            REACK: u1,
-            padding: u9,
-        }),
-        ///  Interrupt flag clear register
-        ICR: mmio.Mmio(packed struct(u32) {
-            ///  Parity error clear flag
-            PECF: u1,
-            ///  Framing error clear flag
-            FECF: u1,
-            ///  Noise detected clear flag
-            NCF: u1,
-            ///  Overrun error clear flag
-            ORECF: u1,
-            ///  Idle line detected clear flag
-            IDLECF: u1,
-            reserved6: u1,
-            ///  Transmission complete clear flag
-            TCCF: u1,
-            reserved8: u1,
-            ///  LIN break detection clear flag
-            LBDCF: u1,
-            ///  CTS clear flag
-            CTSCF: u1,
-            reserved11: u1,
-            ///  Receiver timeout clear flag
-            RTOCF: u1,
-            ///  End of timeout clear flag
-            EOBCF: u1,
-            reserved17: u4,
-            ///  Character match clear flag
-            CMCF: u1,
-            reserved20: u2,
-            ///  Wakeup from Stop mode clear flag
-            WUCF: u1,
-            padding: u11,
-        }),
-        ///  Receive data register
-        RDR: mmio.Mmio(packed struct(u32) {
-            ///  Receive data value
-            RDR: u9,
-            padding: u23,
-        }),
-        ///  Transmit data register
-        TDR: mmio.Mmio(packed struct(u32) {
-            ///  Transmit data value
-            TDR: u9,
-            padding: u23,
-        }),
-    };
-
-    ///  System configuration controller _Comparator and Operational amplifier
-    pub const SYSCFG_COMP_OPAMP = extern struct {
-        ///  configuration register 1
-        SYSCFG_CFGR1: mmio.Mmio(packed struct(u32) {
-            ///  Memory mapping selection bits
-            MEM_MODE: u2,
-            reserved5: u3,
-            ///  USB interrupt remap
-            USB_IT_RMP: u1,
-            ///  Timer 1 ITR3 selection
-            TIM1_ITR_RMP: u1,
-            ///  DAC trigger remap (when TSEL = 001)
-            DAC_TRIG_RMP: u1,
-            ///  ADC24 DMA remapping bit
-            ADC24_DMA_RMP: u1,
-            reserved11: u2,
-            ///  TIM16 DMA request remapping bit
-            TIM16_DMA_RMP: u1,
-            ///  TIM17 DMA request remapping bit
-            TIM17_DMA_RMP: u1,
-            ///  TIM6 and DAC1 DMA request remapping bit
-            TIM6_DAC1_DMA_RMP: u1,
-            ///  TIM7 and DAC2 DMA request remapping bit
-            TIM7_DAC2_DMA_RMP: u1,
-            reserved16: u1,
-            ///  Fast Mode Plus (FM+) driving capability activation bits.
-            I2C_PB6_FM: u1,
-            ///  Fast Mode Plus (FM+) driving capability activation bits.
-            I2C_PB7_FM: u1,
-            ///  Fast Mode Plus (FM+) driving capability activation bits.
-            I2C_PB8_FM: u1,
-            ///  Fast Mode Plus (FM+) driving capability activation bits.
-            I2C_PB9_FM: u1,
-            ///  I2C1 Fast Mode Plus
-            I2C1_FM: u1,
-            ///  I2C2 Fast Mode Plus
-            I2C2_FM: u1,
-            ///  Encoder mode
-            ENCODER_MODE: u2,
-            reserved26: u2,
-            ///  Interrupt enable bits from FPU
-            FPU_IT: u6,
-        }),
-        ///  CCM SRAM protection register
-        SYSCFG_RCR: mmio.Mmio(packed struct(u32) {
-            ///  CCM SRAM page write protection bit
-            PAGE0_WP: u1,
-            ///  CCM SRAM page write protection bit
-            PAGE1_WP: u1,
-            ///  CCM SRAM page write protection bit
-            PAGE2_WP: u1,
-            ///  CCM SRAM page write protection bit
-            PAGE3_WP: u1,
-            ///  CCM SRAM page write protection bit
-            PAGE4_WP: u1,
-            ///  CCM SRAM page write protection bit
-            PAGE5_WP: u1,
-            ///  CCM SRAM page write protection bit
-            PAGE6_WP: u1,
-            ///  CCM SRAM page write protection bit
-            PAGE7_WP: u1,
-            padding: u24,
-        }),
-        ///  external interrupt configuration register 1
-        SYSCFG_EXTICR1: mmio.Mmio(packed struct(u32) {
-            ///  EXTI 0 configuration bits
-            EXTI0: u4,
-            ///  EXTI 1 configuration bits
-            EXTI1: u4,
-            ///  EXTI 2 configuration bits
-            EXTI2: u4,
-            ///  EXTI 3 configuration bits
-            EXTI3: u4,
-            padding: u16,
-        }),
-        ///  external interrupt configuration register 2
-        SYSCFG_EXTICR2: mmio.Mmio(packed struct(u32) {
-            ///  EXTI 4 configuration bits
-            EXTI4: u4,
-            ///  EXTI 5 configuration bits
-            EXTI5: u4,
-            ///  EXTI 6 configuration bits
-            EXTI6: u4,
-            ///  EXTI 7 configuration bits
-            EXTI7: u4,
-            padding: u16,
-        }),
-        ///  external interrupt configuration register 3
-        SYSCFG_EXTICR3: mmio.Mmio(packed struct(u32) {
-            ///  EXTI 8 configuration bits
-            EXTI8: u4,
-            ///  EXTI 9 configuration bits
-            EXTI9: u4,
-            ///  EXTI 10 configuration bits
-            EXTI10: u4,
-            ///  EXTI 11 configuration bits
-            EXTI11: u4,
-            padding: u16,
-        }),
-        ///  external interrupt configuration register 4
-        SYSCFG_EXTICR4: mmio.Mmio(packed struct(u32) {
-            ///  EXTI 12 configuration bits
-            EXTI12: u4,
-            ///  EXTI 13 configuration bits
-            EXTI13: u4,
-            ///  EXTI 14 configuration bits
-            EXTI14: u4,
-            ///  EXTI 15 configuration bits
-            EXTI15: u4,
-            padding: u16,
-        }),
-        ///  configuration register 2
-        SYSCFG_CFGR2: mmio.Mmio(packed struct(u32) {
-            ///  Cortex-M0 LOCKUP bit enable bit
-            LOCUP_LOCK: u1,
-            ///  SRAM parity lock bit
-            SRAM_PARITY_LOCK: u1,
-            ///  PVD lock enable bit
-            PVD_LOCK: u1,
-            reserved4: u1,
-            ///  Bypass address bit 29 in parity calculation
-            BYP_ADD_PAR: u1,
-            reserved8: u3,
-            ///  SRAM parity flag
-            SRAM_PEF: u1,
-            padding: u23,
-        }),
-        ///  control and status register
-        COMP1_CSR: mmio.Mmio(packed struct(u32) {
-            ///  Comparator 1 enable
-            COMP1EN: u1,
-            ///  COMP1_INP_DAC
-            COMP1_INP_DAC: u1,
-            ///  Comparator 1 mode
-            COMP1MODE: u2,
-            ///  Comparator 1 inverting input selection
-            COMP1INSEL: u3,
-            reserved10: u3,
-            ///  Comparator 1 output selection
-            COMP1_OUT_SEL: u4,
-            reserved15: u1,
-            ///  Comparator 1 output polarity
-            COMP1POL: u1,
-            ///  Comparator 1 hysteresis
-            COMP1HYST: u2,
-            ///  Comparator 1 blanking source
-            COMP1_BLANKING: u3,
-            reserved30: u9,
-            ///  Comparator 1 output
-            COMP1OUT: u1,
-            ///  Comparator 1 lock
-            COMP1LOCK: u1,
-        }),
-        ///  control and status register
-        COMP2_CSR: mmio.Mmio(packed struct(u32) {
-            ///  Comparator 2 enable
-            COMP2EN: u1,
-            reserved2: u1,
-            ///  Comparator 2 mode
-            COMP2MODE: u2,
-            ///  Comparator 2 inverting input selection
-            COMP2INSEL: u3,
-            ///  Comparator 2 non inverted input selection
-            COMP2INPSEL: u1,
-            reserved9: u1,
-            ///  Comparator 1inverting input selection
-            COMP2INMSEL: u1,
-            ///  Comparator 2 output selection
-            COMP2_OUT_SEL: u4,
-            reserved15: u1,
-            ///  Comparator 2 output polarity
-            COMP2POL: u1,
-            ///  Comparator 2 hysteresis
-            COMP2HYST: u2,
-            ///  Comparator 2 blanking source
-            COMP2_BLANKING: u3,
-            reserved31: u10,
-            ///  Comparator 2 lock
-            COMP2LOCK: u1,
-        }),
-        ///  control and status register
-        COMP3_CSR: mmio.Mmio(packed struct(u32) {
-            ///  Comparator 3 enable
-            COMP3EN: u1,
-            reserved2: u1,
-            ///  Comparator 3 mode
-            COMP3MODE: u2,
-            ///  Comparator 3 inverting input selection
-            COMP3INSEL: u3,
-            ///  Comparator 3 non inverted input selection
-            COMP3INPSEL: u1,
-            reserved10: u2,
-            ///  Comparator 3 output selection
-            COMP3_OUT_SEL: u4,
-            reserved15: u1,
-            ///  Comparator 3 output polarity
-            COMP3POL: u1,
-            ///  Comparator 3 hysteresis
-            COMP3HYST: u2,
-            ///  Comparator 3 blanking source
-            COMP3_BLANKING: u3,
-            reserved30: u9,
-            ///  Comparator 3 output
-            COMP3OUT: u1,
-            ///  Comparator 3 lock
-            COMP3LOCK: u1,
-        }),
-        ///  control and status register
-        COMP4_CSR: mmio.Mmio(packed struct(u32) {
-            ///  Comparator 4 enable
-            COMP4EN: u1,
-            reserved2: u1,
-            ///  Comparator 4 mode
-            COMP4MODE: u2,
-            ///  Comparator 4 inverting input selection
-            COMP4INSEL: u3,
-            ///  Comparator 4 non inverted input selection
-            COMP4INPSEL: u1,
-            reserved9: u1,
-            ///  Comparator 4 window mode
-            COM4WINMODE: u1,
-            ///  Comparator 4 output selection
-            COMP4_OUT_SEL: u4,
-            reserved15: u1,
-            ///  Comparator 4 output polarity
-            COMP4POL: u1,
-            ///  Comparator 4 hysteresis
-            COMP4HYST: u2,
-            ///  Comparator 4 blanking source
-            COMP4_BLANKING: u3,
-            reserved30: u9,
-            ///  Comparator 4 output
-            COMP4OUT: u1,
-            ///  Comparator 4 lock
-            COMP4LOCK: u1,
-        }),
-        ///  control and status register
-        COMP5_CSR: mmio.Mmio(packed struct(u32) {
-            ///  Comparator 5 enable
-            COMP5EN: u1,
-            reserved2: u1,
-            ///  Comparator 5 mode
-            COMP5MODE: u2,
-            ///  Comparator 5 inverting input selection
-            COMP5INSEL: u3,
-            ///  Comparator 5 non inverted input selection
-            COMP5INPSEL: u1,
-            reserved10: u2,
-            ///  Comparator 5 output selection
-            COMP5_OUT_SEL: u4,
-            reserved15: u1,
-            ///  Comparator 5 output polarity
-            COMP5POL: u1,
-            ///  Comparator 5 hysteresis
-            COMP5HYST: u2,
-            ///  Comparator 5 blanking source
-            COMP5_BLANKING: u3,
-            reserved30: u9,
-            ///  Comparator51 output
-            COMP5OUT: u1,
-            ///  Comparator 5 lock
-            COMP5LOCK: u1,
-        }),
-        ///  control and status register
-        COMP6_CSR: mmio.Mmio(packed struct(u32) {
-            ///  Comparator 6 enable
-            COMP6EN: u1,
-            reserved2: u1,
-            ///  Comparator 6 mode
-            COMP6MODE: u2,
-            ///  Comparator 6 inverting input selection
-            COMP6INSEL: u3,
-            ///  Comparator 6 non inverted input selection
-            COMP6INPSEL: u1,
-            reserved9: u1,
-            ///  Comparator 6 window mode
-            COM6WINMODE: u1,
-            ///  Comparator 6 output selection
-            COMP6_OUT_SEL: u4,
-            reserved15: u1,
-            ///  Comparator 6 output polarity
-            COMP6POL: u1,
-            ///  Comparator 6 hysteresis
-            COMP6HYST: u2,
-            ///  Comparator 6 blanking source
-            COMP6_BLANKING: u3,
-            reserved30: u9,
-            ///  Comparator 6 output
-            COMP6OUT: u1,
-            ///  Comparator 6 lock
-            COMP6LOCK: u1,
-        }),
-        ///  control and status register
-        COMP7_CSR: mmio.Mmio(packed struct(u32) {
-            ///  Comparator 7 enable
-            COMP7EN: u1,
-            reserved2: u1,
-            ///  Comparator 7 mode
-            COMP7MODE: u2,
-            ///  Comparator 7 inverting input selection
-            COMP7INSEL: u3,
-            ///  Comparator 7 non inverted input selection
-            COMP7INPSEL: u1,
-            reserved10: u2,
-            ///  Comparator 7 output selection
-            COMP7_OUT_SEL: u4,
-            reserved15: u1,
-            ///  Comparator 7 output polarity
-            COMP7POL: u1,
-            ///  Comparator 7 hysteresis
-            COMP7HYST: u2,
-            ///  Comparator 7 blanking source
-            COMP7_BLANKING: u3,
-            reserved30: u9,
-            ///  Comparator 7 output
-            COMP7OUT: u1,
-            ///  Comparator 7 lock
-            COMP7LOCK: u1,
-        }),
-        ///  control register
-        OPAMP1_CSR: mmio.Mmio(packed struct(u32) {
-            ///  OPAMP1 enable
-            OPAMP1_EN: u1,
-            ///  FORCE_VP
-            FORCE_VP: u1,
-            ///  OPAMP1 Non inverting input selection
-            VP_SEL: u2,
-            reserved5: u1,
-            ///  OPAMP1 inverting input selection
-            VM_SEL: u2,
-            ///  Timer controlled Mux mode enable
-            TCM_EN: u1,
-            ///  OPAMP1 inverting input secondary selection
-            VMS_SEL: u1,
-            ///  OPAMP1 Non inverting input secondary selection
-            VPS_SEL: u2,
-            ///  Calibration mode enable
-            CALON: u1,
-            ///  Calibration selection
-            CALSEL: u2,
-            ///  Gain in PGA mode
-            PGA_GAIN: u4,
-            ///  User trimming enable
-            USER_TRIM: u1,
-            ///  Offset trimming value (PMOS)
-            TRIMOFFSETP: u5,
-            ///  Offset trimming value (NMOS)
-            TRIMOFFSETN: u5,
-            ///  TSTREF
-            TSTREF: u1,
-            ///  OPAMP 1 ouput status flag
-            OUTCAL: u1,
-            ///  OPAMP 1 lock
-            LOCK: u1,
-        }),
-        ///  control register
-        OPAMP2_CSR: mmio.Mmio(packed struct(u32) {
-            ///  OPAMP2 enable
-            OPAMP2EN: u1,
-            ///  FORCE_VP
-            FORCE_VP: u1,
-            ///  OPAMP2 Non inverting input selection
-            VP_SEL: u2,
-            reserved5: u1,
-            ///  OPAMP2 inverting input selection
-            VM_SEL: u2,
-            ///  Timer controlled Mux mode enable
-            TCM_EN: u1,
-            ///  OPAMP2 inverting input secondary selection
-            VMS_SEL: u1,
-            ///  OPAMP2 Non inverting input secondary selection
-            VPS_SEL: u2,
-            ///  Calibration mode enable
-            CALON: u1,
-            ///  Calibration selection
-            CAL_SEL: u2,
-            ///  Gain in PGA mode
-            PGA_GAIN: u4,
-            ///  User trimming enable
-            USER_TRIM: u1,
-            ///  Offset trimming value (PMOS)
-            TRIMOFFSETP: u5,
-            ///  Offset trimming value (NMOS)
-            TRIMOFFSETN: u5,
-            ///  TSTREF
-            TSTREF: u1,
-            ///  OPAMP 2 ouput status flag
-            OUTCAL: u1,
-            ///  OPAMP 2 lock
-            LOCK: u1,
-        }),
-        ///  control register
-        OPAMP3_CSR: mmio.Mmio(packed struct(u32) {
-            ///  OPAMP3 enable
-            OPAMP3EN: u1,
-            ///  FORCE_VP
-            FORCE_VP: u1,
-            ///  OPAMP3 Non inverting input selection
-            VP_SEL: u2,
-            reserved5: u1,
-            ///  OPAMP3 inverting input selection
-            VM_SEL: u2,
-            ///  Timer controlled Mux mode enable
-            TCM_EN: u1,
-            ///  OPAMP3 inverting input secondary selection
-            VMS_SEL: u1,
-            ///  OPAMP3 Non inverting input secondary selection
-            VPS_SEL: u2,
-            ///  Calibration mode enable
-            CALON: u1,
-            ///  Calibration selection
-            CALSEL: u2,
-            ///  Gain in PGA mode
-            PGA_GAIN: u4,
-            ///  User trimming enable
-            USER_TRIM: u1,
-            ///  Offset trimming value (PMOS)
-            TRIMOFFSETP: u5,
-            ///  Offset trimming value (NMOS)
-            TRIMOFFSETN: u5,
-            ///  TSTREF
-            TSTREF: u1,
-            ///  OPAMP 3 ouput status flag
-            OUTCAL: u1,
-            ///  OPAMP 3 lock
-            LOCK: u1,
-        }),
-        ///  control register
-        OPAMP4_CSR: mmio.Mmio(packed struct(u32) {
-            ///  OPAMP4 enable
-            OPAMP4EN: u1,
-            ///  FORCE_VP
-            FORCE_VP: u1,
-            ///  OPAMP4 Non inverting input selection
-            VP_SEL: u2,
-            reserved5: u1,
-            ///  OPAMP4 inverting input selection
-            VM_SEL: u2,
-            ///  Timer controlled Mux mode enable
-            TCM_EN: u1,
-            ///  OPAMP4 inverting input secondary selection
-            VMS_SEL: u1,
-            ///  OPAMP4 Non inverting input secondary selection
-            VPS_SEL: u2,
-            ///  Calibration mode enable
-            CALON: u1,
-            ///  Calibration selection
-            CALSEL: u2,
-            ///  Gain in PGA mode
-            PGA_GAIN: u4,
-            ///  User trimming enable
-            USER_TRIM: u1,
-            ///  Offset trimming value (PMOS)
-            TRIMOFFSETP: u5,
-            ///  Offset trimming value (NMOS)
-            TRIMOFFSETN: u5,
-            ///  TSTREF
-            TSTREF: u1,
-            ///  OPAMP 4 ouput status flag
-            OUTCAL: u1,
-            ///  OPAMP 4 lock
-            LOCK: u1,
-        }),
-    };
-
-    ///  Independent watchdog
-    pub const IWDG = extern struct {
-        ///  Key register
-        KR: mmio.Mmio(packed struct(u32) {
-            ///  Key value
-            KEY: u16,
-            padding: u16,
-        }),
-        ///  Prescaler register
-        PR: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler divider
-            PR: u3,
-            padding: u29,
-        }),
-        ///  Reload register
-        RLR: mmio.Mmio(packed struct(u32) {
-            ///  Watchdog counter reload value
-            RL: u12,
-            padding: u20,
-        }),
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Watchdog prescaler value update
-            PVU: u1,
-            ///  Watchdog counter reload value update
-            RVU: u1,
-            ///  Watchdog counter window value update
-            WVU: u1,
-            padding: u29,
-        }),
-        ///  Window register
-        WINR: mmio.Mmio(packed struct(u32) {
-            ///  Watchdog counter window value
-            WIN: u12,
-            padding: u20,
-        }),
-    };
-
-    ///  Analog-to-Digital Converter
-    pub const ADC1_2 = extern struct {
-        ///  ADC Common status register
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  ADDRDY_MST
-            ADDRDY_MST: u1,
-            ///  EOSMP_MST
-            EOSMP_MST: u1,
-            ///  EOC_MST
-            EOC_MST: u1,
-            ///  EOS_MST
-            EOS_MST: u1,
-            ///  OVR_MST
-            OVR_MST: u1,
-            ///  JEOC_MST
-            JEOC_MST: u1,
-            ///  JEOS_MST
-            JEOS_MST: u1,
-            ///  AWD1_MST
-            AWD1_MST: u1,
-            ///  AWD2_MST
-            AWD2_MST: u1,
-            ///  AWD3_MST
-            AWD3_MST: u1,
-            ///  JQOVF_MST
-            JQOVF_MST: u1,
-            reserved16: u5,
-            ///  ADRDY_SLV
-            ADRDY_SLV: u1,
-            ///  EOSMP_SLV
-            EOSMP_SLV: u1,
-            ///  End of regular conversion of the slave ADC
-            EOC_SLV: u1,
-            ///  End of regular sequence flag of the slave ADC
-            EOS_SLV: u1,
-            ///  Overrun flag of the slave ADC
-            OVR_SLV: u1,
-            ///  End of injected conversion flag of the slave ADC
-            JEOC_SLV: u1,
-            ///  End of injected sequence flag of the slave ADC
-            JEOS_SLV: u1,
-            ///  Analog watchdog 1 flag of the slave ADC
-            AWD1_SLV: u1,
-            ///  Analog watchdog 2 flag of the slave ADC
-            AWD2_SLV: u1,
-            ///  Analog watchdog 3 flag of the slave ADC
-            AWD3_SLV: u1,
-            ///  Injected Context Queue Overflow flag of the slave ADC
-            JQOVF_SLV: u1,
-            padding: u5,
-        }),
-        reserved8: [4]u8,
-        ///  ADC common control register
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Multi ADC mode selection
-            MULT: u5,
-            reserved8: u3,
-            ///  Delay between 2 sampling phases
-            DELAY: u4,
-            reserved13: u1,
-            ///  DMA configuration (for multi-ADC mode)
-            DMACFG: u1,
-            ///  Direct memory access mode for multi ADC mode
-            MDMA: u2,
-            ///  ADC clock mode
-            CKMODE: u2,
-            reserved22: u4,
-            ///  VREFINT enable
-            VREFEN: u1,
-            ///  Temperature sensor enable
-            TSEN: u1,
-            ///  VBAT enable
-            VBATEN: u1,
-            padding: u7,
-        }),
-        ///  ADC common regular data register for dual and triple modes
-        CDR: mmio.Mmio(packed struct(u32) {
-            ///  Regular data of the master ADC
-            RDATA_MST: u16,
-            ///  Regular data of the slave ADC
-            RDATA_SLV: u16,
-        }),
-    };
-
-    ///  Window watchdog
-    pub const WWDG = extern struct {
-        ///  Control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  7-bit counter
-            T: u7,
-            ///  Activation bit
-            WDGA: u1,
-            padding: u24,
-        }),
-        ///  Configuration register
-        CFR: mmio.Mmio(packed struct(u32) {
-            ///  7-bit window value
-            W: u7,
-            ///  Timer base
-            WDGTB: u2,
-            ///  Early wakeup interrupt
-            EWI: u1,
-            padding: u22,
-        }),
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Early wakeup interrupt flag
-            EWIF: u1,
-            padding: u31,
-        }),
-    };
-
-    ///  Serial peripheral interface/Inter-IC sound
-    pub const SPI1 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Clock phase
-            CPHA: u1,
-            ///  Clock polarity
-            CPOL: u1,
-            ///  Master selection
-            MSTR: u1,
-            ///  Baud rate control
-            BR: u3,
-            ///  SPI enable
-            SPE: u1,
-            ///  Frame format
-            LSBFIRST: u1,
-            ///  Internal slave select
-            SSI: u1,
-            ///  Software slave management
-            SSM: u1,
-            ///  Receive only
-            RXONLY: u1,
-            ///  CRC length
-            CRCL: u1,
-            ///  CRC transfer next
-            CRCNEXT: u1,
-            ///  Hardware CRC calculation enable
-            CRCEN: u1,
-            ///  Output enable in bidirectional mode
-            BIDIOE: u1,
-            ///  Bidirectional data mode enable
-            BIDIMODE: u1,
-            padding: u16,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Rx buffer DMA enable
-            RXDMAEN: u1,
-            ///  Tx buffer DMA enable
-            TXDMAEN: u1,
-            ///  SS output enable
-            SSOE: u1,
-            ///  NSS pulse management
-            NSSP: u1,
-            ///  Frame format
-            FRF: u1,
-            ///  Error interrupt enable
-            ERRIE: u1,
-            ///  RX buffer not empty interrupt enable
-            RXNEIE: u1,
-            ///  Tx buffer empty interrupt enable
-            TXEIE: u1,
-            ///  Data size
-            DS: u4,
-            ///  FIFO reception threshold
-            FRXTH: u1,
-            ///  Last DMA transfer for reception
-            LDMA_RX: u1,
-            ///  Last DMA transfer for transmission
-            LDMA_TX: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Receive buffer not empty
-            RXNE: u1,
-            ///  Transmit buffer empty
-            TXE: u1,
-            ///  Channel side
-            CHSIDE: u1,
-            ///  Underrun flag
-            UDR: u1,
-            ///  CRC error flag
-            CRCERR: u1,
-            ///  Mode fault
-            MODF: u1,
-            ///  Overrun flag
-            OVR: u1,
-            ///  Busy flag
-            BSY: u1,
-            ///  TI frame format error
-            TIFRFE: u1,
-            ///  FIFO reception level
-            FRLVL: u2,
-            ///  FIFO transmission level
-            FTLVL: u2,
-            padding: u19,
-        }),
-        ///  data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data register
-            DR: u16,
-            padding: u16,
-        }),
-        ///  CRC polynomial register
-        CRCPR: mmio.Mmio(packed struct(u32) {
-            ///  CRC polynomial register
-            CRCPOLY: u16,
-            padding: u16,
-        }),
-        ///  RX CRC register
-        RXCRCR: mmio.Mmio(packed struct(u32) {
-            ///  Rx CRC register
-            RxCRC: u16,
-            padding: u16,
-        }),
-        ///  TX CRC register
-        TXCRCR: mmio.Mmio(packed struct(u32) {
-            ///  Tx CRC register
-            TxCRC: u16,
-            padding: u16,
-        }),
-        ///  I2S configuration register
-        I2SCFGR: mmio.Mmio(packed struct(u32) {
-            ///  Channel length (number of bits per audio channel)
-            CHLEN: u1,
-            ///  Data length to be transferred
-            DATLEN: u2,
-            ///  Steady state clock polarity
-            CKPOL: u1,
-            ///  I2S standard selection
-            I2SSTD: u2,
-            reserved7: u1,
-            ///  PCM frame synchronization
-            PCMSYNC: u1,
-            ///  I2S configuration mode
-            I2SCFG: u2,
-            ///  I2S Enable
-            I2SE: u1,
-            ///  I2S mode selection
-            I2SMOD: u1,
-            padding: u20,
-        }),
-        ///  I2S prescaler register
-        I2SPR: mmio.Mmio(packed struct(u32) {
-            ///  I2S Linear prescaler
-            I2SDIV: u8,
-            ///  Odd factor for the prescaler
-            ODD: u1,
-            ///  Master clock output enable
-            MCKOE: u1,
-            padding: u22,
-        }),
-    };
-
-    ///  Real-time clock
-    pub const RTC = extern struct {
-        ///  time register
-        TR: mmio.Mmio(packed struct(u32) {
-            ///  Second units in BCD format
-            SU: u4,
-            ///  Second tens in BCD format
-            ST: u3,
-            reserved8: u1,
-            ///  Minute units in BCD format
-            MNU: u4,
-            ///  Minute tens in BCD format
-            MNT: u3,
-            reserved16: u1,
-            ///  Hour units in BCD format
-            HU: u4,
-            ///  Hour tens in BCD format
-            HT: u2,
-            ///  AM/PM notation
-            PM: u1,
-            padding: u9,
-        }),
-        ///  date register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Date units in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            reserved8: u2,
-            ///  Month units in BCD format
-            MU: u4,
-            ///  Month tens in BCD format
-            MT: u1,
-            ///  Week day units
-            WDU: u3,
-            ///  Year units in BCD format
-            YU: u4,
-            ///  Year tens in BCD format
-            YT: u4,
-            padding: u8,
-        }),
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Wakeup clock selection
-            WCKSEL: u3,
-            ///  Time-stamp event active edge
-            TSEDGE: u1,
-            ///  Reference clock detection enable (50 or 60 Hz)
-            REFCKON: u1,
-            ///  Bypass the shadow registers
-            BYPSHAD: u1,
-            ///  Hour format
-            FMT: u1,
-            reserved8: u1,
-            ///  Alarm A enable
-            ALRAE: u1,
-            ///  Alarm B enable
-            ALRBE: u1,
-            ///  Wakeup timer enable
-            WUTE: u1,
-            ///  Time stamp enable
-            TSE: u1,
-            ///  Alarm A interrupt enable
-            ALRAIE: u1,
-            ///  Alarm B interrupt enable
-            ALRBIE: u1,
-            ///  Wakeup timer interrupt enable
-            WUTIE: u1,
-            ///  Time-stamp interrupt enable
-            TSIE: u1,
-            ///  Add 1 hour (summer time change)
-            ADD1H: u1,
-            ///  Subtract 1 hour (winter time change)
-            SUB1H: u1,
-            ///  Backup
-            BKP: u1,
-            ///  Calibration output selection
-            COSEL: u1,
-            ///  Output polarity
-            POL: u1,
-            ///  Output selection
-            OSEL: u2,
-            ///  Calibration output enable
-            COE: u1,
-            padding: u8,
-        }),
-        ///  initialization and status register
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  Alarm A write flag
-            ALRAWF: u1,
-            ///  Alarm B write flag
-            ALRBWF: u1,
-            ///  Wakeup timer write flag
-            WUTWF: u1,
-            ///  Shift operation pending
-            SHPF: u1,
-            ///  Initialization status flag
-            INITS: u1,
-            ///  Registers synchronization flag
-            RSF: u1,
-            ///  Initialization flag
-            INITF: u1,
-            ///  Initialization mode
-            INIT: u1,
-            ///  Alarm A flag
-            ALRAF: u1,
-            ///  Alarm B flag
-            ALRBF: u1,
-            ///  Wakeup timer flag
-            WUTF: u1,
-            ///  Time-stamp flag
-            TSF: u1,
-            ///  Time-stamp overflow flag
-            TSOVF: u1,
-            ///  Tamper detection flag
-            TAMP1F: u1,
-            ///  RTC_TAMP2 detection flag
-            TAMP2F: u1,
-            ///  RTC_TAMP3 detection flag
-            TAMP3F: u1,
-            ///  Recalibration pending Flag
-            RECALPF: u1,
-            padding: u15,
-        }),
-        ///  prescaler register
-        PRER: mmio.Mmio(packed struct(u32) {
-            ///  Synchronous prescaler factor
-            PREDIV_S: u15,
-            reserved16: u1,
-            ///  Asynchronous prescaler factor
-            PREDIV_A: u7,
-            padding: u9,
-        }),
-        ///  wakeup timer register
-        WUTR: mmio.Mmio(packed struct(u32) {
-            ///  Wakeup auto-reload value bits
-            WUT: u16,
-            padding: u16,
-        }),
-        reserved28: [4]u8,
-        ///  alarm A register
-        ALRMAR: mmio.Mmio(packed struct(u32) {
-            ///  Second units in BCD format
-            SU: u4,
-            ///  Second tens in BCD format
-            ST: u3,
-            ///  Alarm A seconds mask
-            MSK1: u1,
-            ///  Minute units in BCD format
-            MNU: u4,
-            ///  Minute tens in BCD format
-            MNT: u3,
-            ///  Alarm A minutes mask
-            MSK2: u1,
-            ///  Hour units in BCD format
-            HU: u4,
-            ///  Hour tens in BCD format
-            HT: u2,
-            ///  AM/PM notation
-            PM: u1,
-            ///  Alarm A hours mask
-            MSK3: u1,
-            ///  Date units or day in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            ///  Week day selection
-            WDSEL: u1,
-            ///  Alarm A date mask
-            MSK4: u1,
-        }),
-        ///  alarm B register
-        ALRMBR: mmio.Mmio(packed struct(u32) {
-            ///  Second units in BCD format
-            SU: u4,
-            ///  Second tens in BCD format
-            ST: u3,
-            ///  Alarm B seconds mask
-            MSK1: u1,
-            ///  Minute units in BCD format
-            MNU: u4,
-            ///  Minute tens in BCD format
-            MNT: u3,
-            ///  Alarm B minutes mask
-            MSK2: u1,
-            ///  Hour units in BCD format
-            HU: u4,
-            ///  Hour tens in BCD format
-            HT: u2,
-            ///  AM/PM notation
-            PM: u1,
-            ///  Alarm B hours mask
-            MSK3: u1,
-            ///  Date units or day in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            ///  Week day selection
-            WDSEL: u1,
-            ///  Alarm B date mask
-            MSK4: u1,
-        }),
-        ///  write protection register
-        WPR: mmio.Mmio(packed struct(u32) {
-            ///  Write protection key
-            KEY: u8,
-            padding: u24,
-        }),
-        ///  sub second register
-        SSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub second value
-            SS: u16,
-            padding: u16,
-        }),
-        ///  shift control register
-        SHIFTR: mmio.Mmio(packed struct(u32) {
-            ///  Subtract a fraction of a second
-            SUBFS: u15,
-            reserved31: u16,
-            ///  Add one second
-            ADD1S: u1,
-        }),
-        ///  time stamp time register
-        TSTR: mmio.Mmio(packed struct(u32) {
-            ///  Second units in BCD format
-            SU: u4,
-            ///  Second tens in BCD format
-            ST: u3,
-            reserved8: u1,
-            ///  Minute units in BCD format
-            MNU: u4,
-            ///  Minute tens in BCD format
-            MNT: u3,
-            reserved16: u1,
-            ///  Hour units in BCD format
-            HU: u4,
-            ///  Hour tens in BCD format
-            HT: u2,
-            ///  AM/PM notation
-            PM: u1,
-            padding: u9,
-        }),
-        ///  time stamp date register
-        TSDR: mmio.Mmio(packed struct(u32) {
-            ///  Date units in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            reserved8: u2,
-            ///  Month units in BCD format
-            MU: u4,
-            ///  Month tens in BCD format
-            MT: u1,
-            ///  Week day units
-            WDU: u3,
-            padding: u16,
-        }),
-        ///  timestamp sub second register
-        TSSSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub second value
-            SS: u16,
-            padding: u16,
-        }),
-        ///  calibration register
-        CALR: mmio.Mmio(packed struct(u32) {
-            ///  Calibration minus
-            CALM: u9,
-            reserved13: u4,
-            ///  Use a 16-second calibration cycle period
-            CALW16: u1,
-            ///  Use an 8-second calibration cycle period
-            CALW8: u1,
-            ///  Increase frequency of RTC by 488.5 ppm
-            CALP: u1,
-            padding: u16,
-        }),
-        ///  tamper and alternate function configuration register
-        TAFCR: mmio.Mmio(packed struct(u32) {
-            ///  Tamper 1 detection enable
-            TAMP1E: u1,
-            ///  Active level for tamper 1
-            TAMP1TRG: u1,
-            ///  Tamper interrupt enable
-            TAMPIE: u1,
-            ///  Tamper 2 detection enable
-            TAMP2E: u1,
-            ///  Active level for tamper 2
-            TAMP2TRG: u1,
-            ///  Tamper 3 detection enable
-            TAMP3E: u1,
-            ///  Active level for tamper 3
-            TAMP3TRG: u1,
-            ///  Activate timestamp on tamper detection event
-            TAMPTS: u1,
-            ///  Tamper sampling frequency
-            TAMPFREQ: u3,
-            ///  Tamper filter count
-            TAMPFLT: u2,
-            ///  Tamper precharge duration
-            TAMPPRCH: u2,
-            ///  TAMPER pull-up disable
-            TAMPPUDIS: u1,
-            reserved18: u2,
-            ///  PC13 value
-            PC13VALUE: u1,
-            ///  PC13 mode
-            PC13MODE: u1,
-            ///  PC14 value
-            PC14VALUE: u1,
-            ///  PC 14 mode
-            PC14MODE: u1,
-            ///  PC15 value
-            PC15VALUE: u1,
-            ///  PC15 mode
-            PC15MODE: u1,
-            padding: u8,
-        }),
-        ///  alarm A sub second register
-        ALRMASSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub seconds value
-            SS: u15,
-            reserved24: u9,
-            ///  Mask the most-significant bits starting at this bit
-            MASKSS: u4,
-            padding: u4,
-        }),
-        ///  alarm B sub second register
-        ALRMBSSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub seconds value
-            SS: u15,
-            reserved24: u9,
-            ///  Mask the most-significant bits starting at this bit
-            MASKSS: u4,
-            padding: u4,
-        }),
-        reserved80: [4]u8,
-        ///  backup register
-        BKP0R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP1R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP2R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP3R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP4R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP5R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP6R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP7R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP8R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP9R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP10R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP11R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP12R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP13R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP14R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP15R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP16R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP17R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP18R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP19R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP20R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP21R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP22R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP23R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP24R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP25R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP26R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP27R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP28R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP29R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP30R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP31R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-    };
-
-    ///  Basic timers
-    pub const TIM6 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            reserved7: u3,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            reserved11: u3,
-            ///  UIF status bit remapping
-            UIFREMAP: u1,
-            padding: u20,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  Master mode selection
-            MMS: u3,
-            padding: u25,
-        }),
-        reserved12: [4]u8,
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            reserved8: u7,
-            ///  Update DMA request enable
-            UDE: u1,
-            padding: u23,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            padding: u31,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            padding: u31,
-        }),
-        reserved36: [12]u8,
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  Low counter value
-            CNT: u16,
-            reserved31: u15,
-            ///  UIF Copy
-            UIFCPY: u1,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Low Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Analog-to-Digital Converter
-    pub const ADC1 = extern struct {
-        ///  interrupt and status register
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  ADRDY
-            ADRDY: u1,
-            ///  EOSMP
-            EOSMP: u1,
-            ///  EOC
-            EOC: u1,
-            ///  EOS
-            EOS: u1,
-            ///  OVR
-            OVR: u1,
-            ///  JEOC
-            JEOC: u1,
-            ///  JEOS
-            JEOS: u1,
-            ///  AWD1
-            AWD1: u1,
-            ///  AWD2
-            AWD2: u1,
-            ///  AWD3
-            AWD3: u1,
-            ///  JQOVF
-            JQOVF: u1,
-            padding: u21,
-        }),
-        ///  interrupt enable register
-        IER: mmio.Mmio(packed struct(u32) {
-            ///  ADRDYIE
-            ADRDYIE: u1,
-            ///  EOSMPIE
-            EOSMPIE: u1,
-            ///  EOCIE
-            EOCIE: u1,
-            ///  EOSIE
-            EOSIE: u1,
-            ///  OVRIE
-            OVRIE: u1,
-            ///  JEOCIE
-            JEOCIE: u1,
-            ///  JEOSIE
-            JEOSIE: u1,
-            ///  AWD1IE
-            AWD1IE: u1,
-            ///  AWD2IE
-            AWD2IE: u1,
-            ///  AWD3IE
-            AWD3IE: u1,
-            ///  JQOVFIE
-            JQOVFIE: u1,
-            padding: u21,
-        }),
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  ADEN
-            ADEN: u1,
-            ///  ADDIS
-            ADDIS: u1,
-            ///  ADSTART
-            ADSTART: u1,
-            ///  JADSTART
-            JADSTART: u1,
-            ///  ADSTP
-            ADSTP: u1,
-            ///  JADSTP
-            JADSTP: u1,
-            reserved28: u22,
-            ///  ADVREGEN
-            ADVREGEN: u1,
-            ///  DEEPPWD
-            DEEPPWD: u1,
-            ///  ADCALDIF
-            ADCALDIF: u1,
-            ///  ADCAL
-            ADCAL: u1,
-        }),
-        ///  configuration register
-        CFGR: mmio.Mmio(packed struct(u32) {
-            ///  DMAEN
-            DMAEN: u1,
-            ///  DMACFG
-            DMACFG: u1,
-            reserved3: u1,
-            ///  RES
-            RES: u2,
-            ///  ALIGN
-            ALIGN: u1,
-            ///  EXTSEL
-            EXTSEL: u4,
-            ///  EXTEN
-            EXTEN: u2,
-            ///  OVRMOD
-            OVRMOD: u1,
-            ///  CONT
-            CONT: u1,
-            ///  AUTDLY
-            AUTDLY: u1,
-            ///  AUTOFF
-            AUTOFF: u1,
-            ///  DISCEN
-            DISCEN: u1,
-            ///  DISCNUM
-            DISCNUM: u3,
-            ///  JDISCEN
-            JDISCEN: u1,
-            ///  JQM
-            JQM: u1,
-            ///  AWD1SGL
-            AWD1SGL: u1,
-            ///  AWD1EN
-            AWD1EN: u1,
-            ///  JAWD1EN
-            JAWD1EN: u1,
-            ///  JAUTO
-            JAUTO: u1,
-            ///  AWDCH1CH
-            AWDCH1CH: u5,
-            padding: u1,
-        }),
-        reserved20: [4]u8,
-        ///  sample time register 1
-        SMPR1: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  SMP1
-            SMP1: u3,
-            ///  SMP2
-            SMP2: u3,
-            ///  SMP3
-            SMP3: u3,
-            ///  SMP4
-            SMP4: u3,
-            ///  SMP5
-            SMP5: u3,
-            ///  SMP6
-            SMP6: u3,
-            ///  SMP7
-            SMP7: u3,
-            ///  SMP8
-            SMP8: u3,
-            ///  SMP9
-            SMP9: u3,
-            padding: u2,
-        }),
-        ///  sample time register 2
-        SMPR2: mmio.Mmio(packed struct(u32) {
-            ///  SMP10
-            SMP10: u3,
-            ///  SMP11
-            SMP11: u3,
-            ///  SMP12
-            SMP12: u3,
-            ///  SMP13
-            SMP13: u3,
-            ///  SMP14
-            SMP14: u3,
-            ///  SMP15
-            SMP15: u3,
-            ///  SMP16
-            SMP16: u3,
-            ///  SMP17
-            SMP17: u3,
-            ///  SMP18
-            SMP18: u3,
-            padding: u5,
-        }),
-        reserved32: [4]u8,
-        ///  watchdog threshold register 1
-        TR1: mmio.Mmio(packed struct(u32) {
-            ///  LT1
-            LT1: u12,
-            reserved16: u4,
-            ///  HT1
-            HT1: u12,
-            padding: u4,
-        }),
-        ///  watchdog threshold register
-        TR2: mmio.Mmio(packed struct(u32) {
-            ///  LT2
-            LT2: u8,
-            reserved16: u8,
-            ///  HT2
-            HT2: u8,
-            padding: u8,
-        }),
-        ///  watchdog threshold register 3
-        TR3: mmio.Mmio(packed struct(u32) {
-            ///  LT3
-            LT3: u8,
-            reserved16: u8,
-            ///  HT3
-            HT3: u8,
-            padding: u8,
-        }),
-        reserved48: [4]u8,
-        ///  regular sequence register 1
-        SQR1: mmio.Mmio(packed struct(u32) {
-            ///  L3
-            L3: u4,
-            reserved6: u2,
-            ///  SQ1
-            SQ1: u5,
-            reserved12: u1,
-            ///  SQ2
-            SQ2: u5,
-            reserved18: u1,
-            ///  SQ3
-            SQ3: u5,
-            reserved24: u1,
-            ///  SQ4
-            SQ4: u5,
-            padding: u3,
-        }),
-        ///  regular sequence register 2
-        SQR2: mmio.Mmio(packed struct(u32) {
-            ///  SQ5
-            SQ5: u5,
-            reserved6: u1,
-            ///  SQ6
-            SQ6: u5,
-            reserved12: u1,
-            ///  SQ7
-            SQ7: u5,
-            reserved18: u1,
-            ///  SQ8
-            SQ8: u5,
-            reserved24: u1,
-            ///  SQ9
-            SQ9: u5,
-            padding: u3,
-        }),
-        ///  regular sequence register 3
-        SQR3: mmio.Mmio(packed struct(u32) {
-            ///  SQ10
-            SQ10: u5,
-            reserved6: u1,
-            ///  SQ11
-            SQ11: u5,
-            reserved12: u1,
-            ///  SQ12
-            SQ12: u5,
-            reserved18: u1,
-            ///  SQ13
-            SQ13: u5,
-            reserved24: u1,
-            ///  SQ14
-            SQ14: u5,
-            padding: u3,
-        }),
-        ///  regular sequence register 4
-        SQR4: mmio.Mmio(packed struct(u32) {
-            ///  SQ15
-            SQ15: u5,
-            reserved6: u1,
-            ///  SQ16
-            SQ16: u5,
-            padding: u21,
-        }),
-        ///  regular Data Register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  regularDATA
-            regularDATA: u16,
-            padding: u16,
-        }),
-        reserved76: [8]u8,
-        ///  injected sequence register
-        JSQR: mmio.Mmio(packed struct(u32) {
-            ///  JL
-            JL: u2,
-            ///  JEXTSEL
-            JEXTSEL: u4,
-            ///  JEXTEN
-            JEXTEN: u2,
-            ///  JSQ1
-            JSQ1: u5,
-            reserved14: u1,
-            ///  JSQ2
-            JSQ2: u5,
-            reserved20: u1,
-            ///  JSQ3
-            JSQ3: u5,
-            reserved26: u1,
-            ///  JSQ4
-            JSQ4: u5,
-            padding: u1,
-        }),
-        reserved96: [16]u8,
-        ///  offset register 1
-        OFR1: mmio.Mmio(packed struct(u32) {
-            ///  OFFSET1
-            OFFSET1: u12,
-            reserved26: u14,
-            ///  OFFSET1_CH
-            OFFSET1_CH: u5,
-            ///  OFFSET1_EN
-            OFFSET1_EN: u1,
-        }),
-        ///  offset register 2
-        OFR2: mmio.Mmio(packed struct(u32) {
-            ///  OFFSET2
-            OFFSET2: u12,
-            reserved26: u14,
-            ///  OFFSET2_CH
-            OFFSET2_CH: u5,
-            ///  OFFSET2_EN
-            OFFSET2_EN: u1,
-        }),
-        ///  offset register 3
-        OFR3: mmio.Mmio(packed struct(u32) {
-            ///  OFFSET3
-            OFFSET3: u12,
-            reserved26: u14,
-            ///  OFFSET3_CH
-            OFFSET3_CH: u5,
-            ///  OFFSET3_EN
-            OFFSET3_EN: u1,
-        }),
-        ///  offset register 4
-        OFR4: mmio.Mmio(packed struct(u32) {
-            ///  OFFSET4
-            OFFSET4: u12,
-            reserved26: u14,
-            ///  OFFSET4_CH
-            OFFSET4_CH: u5,
-            ///  OFFSET4_EN
-            OFFSET4_EN: u1,
-        }),
-        reserved128: [16]u8,
-        ///  injected data register 1
-        JDR1: mmio.Mmio(packed struct(u32) {
-            ///  JDATA1
-            JDATA1: u16,
-            padding: u16,
-        }),
-        ///  injected data register 2
-        JDR2: mmio.Mmio(packed struct(u32) {
-            ///  JDATA2
-            JDATA2: u16,
-            padding: u16,
-        }),
-        ///  injected data register 3
-        JDR3: mmio.Mmio(packed struct(u32) {
-            ///  JDATA3
-            JDATA3: u16,
-            padding: u16,
-        }),
-        ///  injected data register 4
-        JDR4: mmio.Mmio(packed struct(u32) {
-            ///  JDATA4
-            JDATA4: u16,
-            padding: u16,
-        }),
-        reserved160: [16]u8,
-        ///  Analog Watchdog 2 Configuration Register
-        AWD2CR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  AWD2CH
-            AWD2CH: u18,
-            padding: u13,
-        }),
-        ///  Analog Watchdog 3 Configuration Register
-        AWD3CR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  AWD3CH
-            AWD3CH: u18,
-            padding: u13,
-        }),
-        reserved176: [8]u8,
-        ///  Differential Mode Selection Register 2
-        DIFSEL: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Differential mode for channels 15 to 1
-            DIFSEL_1_15: u15,
-            ///  Differential mode for channels 18 to 16
-            DIFSEL_16_18: u3,
-            padding: u13,
-        }),
-        ///  Calibration Factors
-        CALFACT: mmio.Mmio(packed struct(u32) {
-            ///  CALFACT_S
-            CALFACT_S: u7,
-            reserved16: u9,
-            ///  CALFACT_D
-            CALFACT_D: u7,
-            padding: u9,
-        }),
-    };
-
-    ///  Advanced-timers
-    pub const TIM8 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            reserved11: u1,
-            ///  UIF status bit remapping
-            UIFREMAP: u1,
-            padding: u20,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/compare preloaded control
-            CCPC: u1,
-            reserved2: u1,
-            ///  Capture/compare control update selection
-            CCUS: u1,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            ///  Output Idle state 1
-            OIS1: u1,
-            ///  Output Idle state 1
-            OIS1N: u1,
-            ///  Output Idle state 2
-            OIS2: u1,
-            ///  Output Idle state 2
-            OIS2N: u1,
-            ///  Output Idle state 3
-            OIS3: u1,
-            ///  Output Idle state 3
-            OIS3N: u1,
-            ///  Output Idle state 4
-            OIS4: u1,
-            reserved16: u1,
-            ///  Output Idle state 5
-            OIS5: u1,
-            reserved18: u1,
-            ///  Output Idle state 6
-            OIS6: u1,
-            reserved20: u1,
-            ///  Master mode selection 2
-            MMS2: u4,
-            padding: u8,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            ///  OCREF clear selection
-            OCCS: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            ///  Slave mode selection bit 3
-            SMS3: u1,
-            padding: u15,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            ///  COM interrupt enable
-            COMIE: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            ///  Break interrupt enable
-            BIE: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            ///  COM DMA request enable
-            COMDE: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            ///  COM interrupt flag
-            COMIF: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            ///  Break interrupt flag
-            BIF: u1,
-            ///  Break 2 interrupt flag
-            B2IF: u1,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            reserved16: u3,
-            ///  Capture/Compare 5 interrupt flag
-            C5IF: u1,
-            ///  Capture/Compare 6 interrupt flag
-            C6IF: u1,
-            padding: u14,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            ///  Capture/Compare control update generation
-            COMG: u1,
-            ///  Trigger generation
-            TG: u1,
-            ///  Break generation
-            BG: u1,
-            ///  Break 2 generation
-            B2G: u1,
-            padding: u23,
-        }),
-        ///  capture/compare mode register (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            ///  Output Compare 1 clear enable
-            OC1CE: u1,
-            ///  Capture/Compare 2 selection
-            CC2S: u2,
-            ///  Output Compare 2 fast enable
-            OC2FE: u1,
-            ///  Output Compare 2 preload enable
-            OC2PE: u1,
-            ///  Output Compare 2 mode
-            OC2M: u3,
-            ///  Output Compare 2 clear enable
-            OC2CE: u1,
-            ///  Output Compare 1 mode bit 3
-            OC1M_3: u1,
-            reserved24: u7,
-            ///  Output Compare 2 mode bit 3
-            OC2M_3: u1,
-            padding: u7,
-        }),
-        ///  capture/compare mode register (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 3 selection
-            CC3S: u2,
-            ///  Output compare 3 fast enable
-            OC3FE: u1,
-            ///  Output compare 3 preload enable
-            OC3PE: u1,
-            ///  Output compare 3 mode
-            OC3M: u3,
-            ///  Output compare 3 clear enable
-            OC3CE: u1,
-            ///  Capture/Compare 4 selection
-            CC4S: u2,
-            ///  Output compare 4 fast enable
-            OC4FE: u1,
-            ///  Output compare 4 preload enable
-            OC4PE: u1,
-            ///  Output compare 4 mode
-            OC4M: u3,
-            ///  Output compare 4 clear enable
-            OC4CE: u1,
-            ///  Output Compare 3 mode bit 3
-            OC3M_3: u1,
-            reserved24: u7,
-            ///  Output Compare 4 mode bit 3
-            OC4M_3: u1,
-            padding: u7,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            ///  Capture/Compare 1 complementary output enable
-            CC1NE: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            ///  Capture/Compare 2 complementary output enable
-            CC2NE: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            ///  Capture/Compare 3 complementary output enable
-            CC3NE: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            reserved15: u1,
-            ///  Capture/Compare 4 output Polarity
-            CC4NP: u1,
-            ///  Capture/Compare 5 output enable
-            CC5E: u1,
-            ///  Capture/Compare 5 output Polarity
-            CC5P: u1,
-            reserved20: u2,
-            ///  Capture/Compare 6 output enable
-            CC6E: u1,
-            ///  Capture/Compare 6 output Polarity
-            CC6P: u1,
-            padding: u10,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            reserved31: u15,
-            ///  UIF copy
-            UIFCPY: u1,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        ///  repetition counter register
-        RCR: mmio.Mmio(packed struct(u32) {
-            ///  Repetition counter value
-            REP: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 2 value
-            CCR2: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 3 value
-            CCR3: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 3 value
-            CCR4: u16,
-            padding: u16,
-        }),
-        ///  break and dead-time register
-        BDTR: mmio.Mmio(packed struct(u32) {
-            ///  Dead-time generator setup
-            DTG: u8,
-            ///  Lock configuration
-            LOCK: u2,
-            ///  Off-state selection for Idle mode
-            OSSI: u1,
-            ///  Off-state selection for Run mode
-            OSSR: u1,
-            ///  Break enable
-            BKE: u1,
-            ///  Break polarity
-            BKP: u1,
-            ///  Automatic output enable
-            AOE: u1,
-            ///  Main output enable
-            MOE: u1,
-            ///  Break filter
-            BKF: u4,
-            ///  Break 2 filter
-            BK2F: u4,
-            ///  Break 2 enable
-            BK2E: u1,
-            ///  Break 2 polarity
-            BK2P: u1,
-            padding: u6,
-        }),
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-        reserved84: [4]u8,
-        ///  capture/compare mode register 3 (output mode)
-        CCMR3_Output: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Output compare 5 fast enable
-            OC5FE: u1,
-            ///  Output compare 5 preload enable
-            OC5PE: u1,
-            ///  Output compare 5 mode
-            OC5M: u3,
-            ///  Output compare 5 clear enable
-            OC5CE: u1,
-            reserved10: u2,
-            ///  Output compare 6 fast enable
-            OC6FE: u1,
-            ///  Output compare 6 preload enable
-            OC6PE: u1,
-            ///  Output compare 6 mode
-            OC6M: u3,
-            ///  Output compare 6 clear enable
-            OC6CE: u1,
-            ///  Outout Compare 5 mode bit 3
-            OC5M_3: u1,
-            reserved24: u7,
-            ///  Outout Compare 6 mode bit 3
-            OC6M_3: u1,
-            padding: u7,
-        }),
-        ///  capture/compare register 5
-        CCR5: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 5 value
-            CCR5: u16,
-            reserved29: u13,
-            ///  Group Channel 5 and Channel 1
-            GC5C1: u1,
-            ///  Group Channel 5 and Channel 2
-            GC5C2: u1,
-            ///  Group Channel 5 and Channel 3
-            GC5C3: u1,
-        }),
-        ///  capture/compare register 6
-        CCR6: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 6 value
-            CCR6: u16,
-            padding: u16,
-        }),
-        ///  option registers
-        OR: mmio.Mmio(packed struct(u32) {
-            ///  TIM8_ETR_ADC2 remapping capability
-            TIM8_ETR_ADC2_RMP: u2,
-            ///  TIM8_ETR_ADC3 remapping capability
-            TIM8_ETR_ADC3_RMP: u2,
-            padding: u28,
-        }),
-    };
-
-    ///  Digital-to-analog converter
-    pub const DAC = extern struct {
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 enable
-            EN1: u1,
-            ///  DAC channel1 output buffer disable
-            BOFF1: u1,
-            ///  DAC channel1 trigger enable
-            TEN1: u1,
-            ///  DAC channel1 trigger selection
-            TSEL1: u3,
-            ///  DAC channel1 noise/triangle wave generation enable
-            WAVE1: u2,
-            ///  DAC channel1 mask/amplitude selector
-            MAMP1: u4,
-            ///  DAC channel1 DMA enable
-            DMAEN1: u1,
-            ///  DAC channel1 DMA Underrun Interrupt enable
-            DMAUDRIE1: u1,
-            reserved16: u2,
-            ///  DAC channel2 enable
-            EN2: u1,
-            ///  DAC channel2 output buffer disable
-            BOFF2: u1,
-            ///  DAC channel2 trigger enable
-            TEN2: u1,
-            ///  DAC channel2 trigger selection
-            TSEL2: u3,
-            ///  DAC channel2 noise/triangle wave generation enable
-            WAVE2: u2,
-            ///  DAC channel2 mask/amplitude selector
-            MAMP2: u4,
-            ///  DAC channel2 DMA enable
-            DMAEN2: u1,
-            ///  DAC channel2 DMA underrun interrupt enable
-            DMAUDRIE2: u1,
-            padding: u2,
-        }),
-        ///  software trigger register
-        SWTRIGR: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 software trigger
-            SWTRIG1: u1,
-            ///  DAC channel2 software trigger
-            SWTRIG2: u1,
-            padding: u30,
-        }),
-        ///  channel1 12-bit right-aligned data holding register
-        DHR12R1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 12-bit right-aligned data
-            DACC1DHR: u12,
-            padding: u20,
-        }),
-        ///  channel1 12-bit left aligned data holding register
-        DHR12L1: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel1 12-bit left-aligned data
-            DACC1DHR: u12,
-            padding: u16,
-        }),
-        ///  channel1 8-bit right aligned data holding register
-        DHR8R1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 8-bit right-aligned data
-            DACC1DHR: u8,
-            padding: u24,
-        }),
-        ///  channel2 12-bit right aligned data holding register
-        DHR12R2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 12-bit right-aligned data
-            DACC2DHR: u12,
-            padding: u20,
-        }),
-        ///  channel2 12-bit left aligned data holding register
-        DHR12L2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel2 12-bit left-aligned data
-            DACC2DHR: u12,
-            padding: u16,
-        }),
-        ///  channel2 8-bit right-aligned data holding register
-        DHR8R2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 8-bit right-aligned data
-            DACC2DHR: u8,
-            padding: u24,
-        }),
-        ///  Dual DAC 12-bit right-aligned data holding register
-        DHR12RD: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 12-bit right-aligned data
-            DACC1DHR: u12,
-            reserved16: u4,
-            ///  DAC channel2 12-bit right-aligned data
-            DACC2DHR: u12,
-            padding: u4,
-        }),
-        ///  DUAL DAC 12-bit left aligned data holding register
-        DHR12LD: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel1 12-bit left-aligned data
-            DACC1DHR: u12,
-            reserved20: u4,
-            ///  DAC channel2 12-bit left-aligned data
-            DACC2DHR: u12,
-        }),
-        ///  DUAL DAC 8-bit right aligned data holding register
-        DHR8RD: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 8-bit right-aligned data
-            DACC1DHR: u8,
-            ///  DAC channel2 8-bit right-aligned data
-            DACC2DHR: u8,
-            padding: u16,
-        }),
-        ///  channel1 data output register
-        DOR1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 data output
-            DACC1DOR: u12,
-            padding: u20,
-        }),
-        ///  channel2 data output register
-        DOR2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 data output
-            DACC2DOR: u12,
-            padding: u20,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            reserved13: u13,
-            ///  DAC channel1 DMA underrun flag
-            DMAUDR1: u1,
-            reserved29: u15,
-            ///  DAC channel2 DMA underrun flag
-            DMAUDR2: u1,
-            padding: u2,
-        }),
-    };
-
-    ///  External interrupt/event controller
-    pub const EXTI = extern struct {
-        ///  Interrupt mask register
-        IMR1: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt Mask on line 0
-            MR0: u1,
-            ///  Interrupt Mask on line 1
-            MR1: u1,
-            ///  Interrupt Mask on line 2
-            MR2: u1,
-            ///  Interrupt Mask on line 3
-            MR3: u1,
-            ///  Interrupt Mask on line 4
-            MR4: u1,
-            ///  Interrupt Mask on line 5
-            MR5: u1,
-            ///  Interrupt Mask on line 6
-            MR6: u1,
-            ///  Interrupt Mask on line 7
-            MR7: u1,
-            ///  Interrupt Mask on line 8
-            MR8: u1,
-            ///  Interrupt Mask on line 9
-            MR9: u1,
-            ///  Interrupt Mask on line 10
-            MR10: u1,
-            ///  Interrupt Mask on line 11
-            MR11: u1,
-            ///  Interrupt Mask on line 12
-            MR12: u1,
-            ///  Interrupt Mask on line 13
-            MR13: u1,
-            ///  Interrupt Mask on line 14
-            MR14: u1,
-            ///  Interrupt Mask on line 15
-            MR15: u1,
-            ///  Interrupt Mask on line 16
-            MR16: u1,
-            ///  Interrupt Mask on line 17
-            MR17: u1,
-            ///  Interrupt Mask on line 18
-            MR18: u1,
-            ///  Interrupt Mask on line 19
-            MR19: u1,
-            ///  Interrupt Mask on line 20
-            MR20: u1,
-            ///  Interrupt Mask on line 21
-            MR21: u1,
-            ///  Interrupt Mask on line 22
-            MR22: u1,
-            ///  Interrupt Mask on line 23
-            MR23: u1,
-            ///  Interrupt Mask on line 24
-            MR24: u1,
-            ///  Interrupt Mask on line 25
-            MR25: u1,
-            ///  Interrupt Mask on line 26
-            MR26: u1,
-            ///  Interrupt Mask on line 27
-            MR27: u1,
-            ///  Interrupt Mask on line 28
-            MR28: u1,
-            ///  Interrupt Mask on line 29
-            MR29: u1,
-            ///  Interrupt Mask on line 30
-            MR30: u1,
-            ///  Interrupt Mask on line 31
-            MR31: u1,
-        }),
-        ///  Event mask register
-        EMR1: mmio.Mmio(packed struct(u32) {
-            ///  Event Mask on line 0
-            MR0: u1,
-            ///  Event Mask on line 1
-            MR1: u1,
-            ///  Event Mask on line 2
-            MR2: u1,
-            ///  Event Mask on line 3
-            MR3: u1,
-            ///  Event Mask on line 4
-            MR4: u1,
-            ///  Event Mask on line 5
-            MR5: u1,
-            ///  Event Mask on line 6
-            MR6: u1,
-            ///  Event Mask on line 7
-            MR7: u1,
-            ///  Event Mask on line 8
-            MR8: u1,
-            ///  Event Mask on line 9
-            MR9: u1,
-            ///  Event Mask on line 10
-            MR10: u1,
-            ///  Event Mask on line 11
-            MR11: u1,
-            ///  Event Mask on line 12
-            MR12: u1,
-            ///  Event Mask on line 13
-            MR13: u1,
-            ///  Event Mask on line 14
-            MR14: u1,
-            ///  Event Mask on line 15
-            MR15: u1,
-            ///  Event Mask on line 16
-            MR16: u1,
-            ///  Event Mask on line 17
-            MR17: u1,
-            ///  Event Mask on line 18
-            MR18: u1,
-            ///  Event Mask on line 19
-            MR19: u1,
-            ///  Event Mask on line 20
-            MR20: u1,
-            ///  Event Mask on line 21
-            MR21: u1,
-            ///  Event Mask on line 22
-            MR22: u1,
-            ///  Event Mask on line 23
-            MR23: u1,
-            ///  Event Mask on line 24
-            MR24: u1,
-            ///  Event Mask on line 25
-            MR25: u1,
-            ///  Event Mask on line 26
-            MR26: u1,
-            ///  Event Mask on line 27
-            MR27: u1,
-            ///  Event Mask on line 28
-            MR28: u1,
-            ///  Event Mask on line 29
-            MR29: u1,
-            ///  Event Mask on line 30
-            MR30: u1,
-            ///  Event Mask on line 31
-            MR31: u1,
-        }),
-        ///  Rising Trigger selection register
-        RTSR1: mmio.Mmio(packed struct(u32) {
-            ///  Rising trigger event configuration of line 0
-            TR0: u1,
-            ///  Rising trigger event configuration of line 1
-            TR1: u1,
-            ///  Rising trigger event configuration of line 2
-            TR2: u1,
-            ///  Rising trigger event configuration of line 3
-            TR3: u1,
-            ///  Rising trigger event configuration of line 4
-            TR4: u1,
-            ///  Rising trigger event configuration of line 5
-            TR5: u1,
-            ///  Rising trigger event configuration of line 6
-            TR6: u1,
-            ///  Rising trigger event configuration of line 7
-            TR7: u1,
-            ///  Rising trigger event configuration of line 8
-            TR8: u1,
-            ///  Rising trigger event configuration of line 9
-            TR9: u1,
-            ///  Rising trigger event configuration of line 10
-            TR10: u1,
-            ///  Rising trigger event configuration of line 11
-            TR11: u1,
-            ///  Rising trigger event configuration of line 12
-            TR12: u1,
-            ///  Rising trigger event configuration of line 13
-            TR13: u1,
-            ///  Rising trigger event configuration of line 14
-            TR14: u1,
-            ///  Rising trigger event configuration of line 15
-            TR15: u1,
-            ///  Rising trigger event configuration of line 16
-            TR16: u1,
-            ///  Rising trigger event configuration of line 17
-            TR17: u1,
-            ///  Rising trigger event configuration of line 18
-            TR18: u1,
-            ///  Rising trigger event configuration of line 19
-            TR19: u1,
-            ///  Rising trigger event configuration of line 20
-            TR20: u1,
-            ///  Rising trigger event configuration of line 21
-            TR21: u1,
-            ///  Rising trigger event configuration of line 22
-            TR22: u1,
-            reserved29: u6,
-            ///  Rising trigger event configuration of line 29
-            TR29: u1,
-            ///  Rising trigger event configuration of line 30
-            TR30: u1,
-            ///  Rising trigger event configuration of line 31
-            TR31: u1,
-        }),
-        ///  Falling Trigger selection register
-        FTSR1: mmio.Mmio(packed struct(u32) {
-            ///  Falling trigger event configuration of line 0
-            TR0: u1,
-            ///  Falling trigger event configuration of line 1
-            TR1: u1,
-            ///  Falling trigger event configuration of line 2
-            TR2: u1,
-            ///  Falling trigger event configuration of line 3
-            TR3: u1,
-            ///  Falling trigger event configuration of line 4
-            TR4: u1,
-            ///  Falling trigger event configuration of line 5
-            TR5: u1,
-            ///  Falling trigger event configuration of line 6
-            TR6: u1,
-            ///  Falling trigger event configuration of line 7
-            TR7: u1,
-            ///  Falling trigger event configuration of line 8
-            TR8: u1,
-            ///  Falling trigger event configuration of line 9
-            TR9: u1,
-            ///  Falling trigger event configuration of line 10
-            TR10: u1,
-            ///  Falling trigger event configuration of line 11
-            TR11: u1,
-            ///  Falling trigger event configuration of line 12
-            TR12: u1,
-            ///  Falling trigger event configuration of line 13
-            TR13: u1,
-            ///  Falling trigger event configuration of line 14
-            TR14: u1,
-            ///  Falling trigger event configuration of line 15
-            TR15: u1,
-            ///  Falling trigger event configuration of line 16
-            TR16: u1,
-            ///  Falling trigger event configuration of line 17
-            TR17: u1,
-            ///  Falling trigger event configuration of line 18
-            TR18: u1,
-            ///  Falling trigger event configuration of line 19
-            TR19: u1,
-            ///  Falling trigger event configuration of line 20
-            TR20: u1,
-            ///  Falling trigger event configuration of line 21
-            TR21: u1,
-            ///  Falling trigger event configuration of line 22
-            TR22: u1,
-            reserved29: u6,
-            ///  Falling trigger event configuration of line 29
-            TR29: u1,
-            ///  Falling trigger event configuration of line 30.
-            TR30: u1,
-            ///  Falling trigger event configuration of line 31
-            TR31: u1,
-        }),
-        ///  Software interrupt event register
-        SWIER1: mmio.Mmio(packed struct(u32) {
-            ///  Software Interrupt on line 0
-            SWIER0: u1,
-            ///  Software Interrupt on line 1
-            SWIER1: u1,
-            ///  Software Interrupt on line 2
-            SWIER2: u1,
-            ///  Software Interrupt on line 3
-            SWIER3: u1,
-            ///  Software Interrupt on line 4
-            SWIER4: u1,
-            ///  Software Interrupt on line 5
-            SWIER5: u1,
-            ///  Software Interrupt on line 6
-            SWIER6: u1,
-            ///  Software Interrupt on line 7
-            SWIER7: u1,
-            ///  Software Interrupt on line 8
-            SWIER8: u1,
-            ///  Software Interrupt on line 9
-            SWIER9: u1,
-            ///  Software Interrupt on line 10
-            SWIER10: u1,
-            ///  Software Interrupt on line 11
-            SWIER11: u1,
-            ///  Software Interrupt on line 12
-            SWIER12: u1,
-            ///  Software Interrupt on line 13
-            SWIER13: u1,
-            ///  Software Interrupt on line 14
-            SWIER14: u1,
-            ///  Software Interrupt on line 15
-            SWIER15: u1,
-            ///  Software Interrupt on line 16
-            SWIER16: u1,
-            ///  Software Interrupt on line 17
-            SWIER17: u1,
-            ///  Software Interrupt on line 18
-            SWIER18: u1,
-            ///  Software Interrupt on line 19
-            SWIER19: u1,
-            ///  Software Interrupt on line 20
-            SWIER20: u1,
-            ///  Software Interrupt on line 21
-            SWIER21: u1,
-            ///  Software Interrupt on line 22
-            SWIER22: u1,
-            reserved29: u6,
-            ///  Software Interrupt on line 29
-            SWIER29: u1,
-            ///  Software Interrupt on line 309
-            SWIER30: u1,
-            ///  Software Interrupt on line 319
-            SWIER31: u1,
-        }),
-        ///  Pending register
-        PR1: mmio.Mmio(packed struct(u32) {
-            ///  Pending bit 0
-            PR0: u1,
-            ///  Pending bit 1
-            PR1: u1,
-            ///  Pending bit 2
-            PR2: u1,
-            ///  Pending bit 3
-            PR3: u1,
-            ///  Pending bit 4
-            PR4: u1,
-            ///  Pending bit 5
-            PR5: u1,
-            ///  Pending bit 6
-            PR6: u1,
-            ///  Pending bit 7
-            PR7: u1,
-            ///  Pending bit 8
-            PR8: u1,
-            ///  Pending bit 9
-            PR9: u1,
-            ///  Pending bit 10
-            PR10: u1,
-            ///  Pending bit 11
-            PR11: u1,
-            ///  Pending bit 12
-            PR12: u1,
-            ///  Pending bit 13
-            PR13: u1,
-            ///  Pending bit 14
-            PR14: u1,
-            ///  Pending bit 15
-            PR15: u1,
-            ///  Pending bit 16
-            PR16: u1,
-            ///  Pending bit 17
-            PR17: u1,
-            ///  Pending bit 18
-            PR18: u1,
-            ///  Pending bit 19
-            PR19: u1,
-            ///  Pending bit 20
-            PR20: u1,
-            ///  Pending bit 21
-            PR21: u1,
-            ///  Pending bit 22
-            PR22: u1,
-            reserved29: u6,
-            ///  Pending bit 29
-            PR29: u1,
-            ///  Pending bit 30
-            PR30: u1,
-            ///  Pending bit 31
-            PR31: u1,
-        }),
-        ///  Interrupt mask register
-        IMR2: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt Mask on external/internal line 32
-            MR32: u1,
-            ///  Interrupt Mask on external/internal line 33
-            MR33: u1,
-            ///  Interrupt Mask on external/internal line 34
-            MR34: u1,
-            ///  Interrupt Mask on external/internal line 35
-            MR35: u1,
-            padding: u28,
-        }),
-        ///  Event mask register
-        EMR2: mmio.Mmio(packed struct(u32) {
-            ///  Event mask on external/internal line 32
-            MR32: u1,
-            ///  Event mask on external/internal line 33
-            MR33: u1,
-            ///  Event mask on external/internal line 34
-            MR34: u1,
-            ///  Event mask on external/internal line 35
-            MR35: u1,
-            padding: u28,
-        }),
-        ///  Rising Trigger selection register
-        RTSR2: mmio.Mmio(packed struct(u32) {
-            ///  Rising trigger event configuration bit of line 32
-            TR32: u1,
-            ///  Rising trigger event configuration bit of line 33
-            TR33: u1,
-            padding: u30,
-        }),
-        ///  Falling Trigger selection register
-        FTSR2: mmio.Mmio(packed struct(u32) {
-            ///  Falling trigger event configuration bit of line 32
-            TR32: u1,
-            ///  Falling trigger event configuration bit of line 33
-            TR33: u1,
-            padding: u30,
-        }),
-        ///  Software interrupt event register
-        SWIER2: mmio.Mmio(packed struct(u32) {
-            ///  Software interrupt on line 32
-            SWIER32: u1,
-            ///  Software interrupt on line 33
-            SWIER33: u1,
-            padding: u30,
-        }),
-        ///  Pending register
-        PR2: mmio.Mmio(packed struct(u32) {
-            ///  Pending bit on line 32
-            PR32: u1,
-            ///  Pending bit on line 33
-            PR33: u1,
-            padding: u30,
-        }),
-    };
-
-    ///  Power control
-    pub const PWR = extern struct {
-        ///  power control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Low-power deep sleep
-            LPDS: u1,
-            ///  Power down deepsleep
-            PDDS: u1,
-            ///  Clear wakeup flag
-            CWUF: u1,
-            ///  Clear standby flag
-            CSBF: u1,
-            ///  Power voltage detector enable
-            PVDE: u1,
-            ///  PVD level selection
-            PLS: u3,
-            ///  Disable backup domain write protection
-            DBP: u1,
-            padding: u23,
-        }),
-        ///  power control/status register
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  Wakeup flag
-            WUF: u1,
-            ///  Standby flag
-            SBF: u1,
-            ///  PVD output
-            PVDO: u1,
-            reserved8: u5,
-            ///  Enable WKUP1 pin
-            EWUP1: u1,
-            ///  Enable WKUP2 pin
-            EWUP2: u1,
-            padding: u22,
-        }),
-    };
-
-    ///  Controller area network
-    pub const CAN = extern struct {
-        ///  master control register
-        MCR: mmio.Mmio(packed struct(u32) {
-            ///  INRQ
-            INRQ: u1,
-            ///  SLEEP
-            SLEEP: u1,
-            ///  TXFP
-            TXFP: u1,
-            ///  RFLM
-            RFLM: u1,
-            ///  NART
-            NART: u1,
-            ///  AWUM
-            AWUM: u1,
-            ///  ABOM
-            ABOM: u1,
-            ///  TTCM
-            TTCM: u1,
-            reserved15: u7,
-            ///  RESET
-            RESET: u1,
-            ///  DBF
-            DBF: u1,
-            padding: u15,
-        }),
-        ///  master status register
-        MSR: mmio.Mmio(packed struct(u32) {
-            ///  INAK
-            INAK: u1,
-            ///  SLAK
-            SLAK: u1,
-            ///  ERRI
-            ERRI: u1,
-            ///  WKUI
-            WKUI: u1,
-            ///  SLAKI
-            SLAKI: u1,
-            reserved8: u3,
-            ///  TXM
-            TXM: u1,
-            ///  RXM
-            RXM: u1,
-            ///  SAMP
-            SAMP: u1,
-            ///  RX
-            RX: u1,
-            padding: u20,
-        }),
-        ///  transmit status register
-        TSR: mmio.Mmio(packed struct(u32) {
-            ///  RQCP0
-            RQCP0: u1,
-            ///  TXOK0
-            TXOK0: u1,
-            ///  ALST0
-            ALST0: u1,
-            ///  TERR0
-            TERR0: u1,
-            reserved7: u3,
-            ///  ABRQ0
-            ABRQ0: u1,
-            ///  RQCP1
-            RQCP1: u1,
-            ///  TXOK1
-            TXOK1: u1,
-            ///  ALST1
-            ALST1: u1,
-            ///  TERR1
-            TERR1: u1,
-            reserved15: u3,
-            ///  ABRQ1
-            ABRQ1: u1,
-            ///  RQCP2
-            RQCP2: u1,
-            ///  TXOK2
-            TXOK2: u1,
-            ///  ALST2
-            ALST2: u1,
-            ///  TERR2
-            TERR2: u1,
-            reserved23: u3,
-            ///  ABRQ2
-            ABRQ2: u1,
-            ///  CODE
-            CODE: u2,
-            ///  Lowest priority flag for mailbox 0
-            TME0: u1,
-            ///  Lowest priority flag for mailbox 1
-            TME1: u1,
-            ///  Lowest priority flag for mailbox 2
-            TME2: u1,
-            ///  Lowest priority flag for mailbox 0
-            LOW0: u1,
-            ///  Lowest priority flag for mailbox 1
-            LOW1: u1,
-            ///  Lowest priority flag for mailbox 2
-            LOW2: u1,
-        }),
-        ///  receive FIFO 0 register
-        RF0R: mmio.Mmio(packed struct(u32) {
-            ///  FMP0
-            FMP0: u2,
-            reserved3: u1,
-            ///  FULL0
-            FULL0: u1,
-            ///  FOVR0
-            FOVR0: u1,
-            ///  RFOM0
-            RFOM0: u1,
-            padding: u26,
-        }),
-        ///  receive FIFO 1 register
-        RF1R: mmio.Mmio(packed struct(u32) {
-            ///  FMP1
-            FMP1: u2,
-            reserved3: u1,
-            ///  FULL1
-            FULL1: u1,
-            ///  FOVR1
-            FOVR1: u1,
-            ///  RFOM1
-            RFOM1: u1,
-            padding: u26,
-        }),
-        ///  interrupt enable register
-        IER: mmio.Mmio(packed struct(u32) {
-            ///  TMEIE
-            TMEIE: u1,
-            ///  FMPIE0
-            FMPIE0: u1,
-            ///  FFIE0
-            FFIE0: u1,
-            ///  FOVIE0
-            FOVIE0: u1,
-            ///  FMPIE1
-            FMPIE1: u1,
-            ///  FFIE1
-            FFIE1: u1,
-            ///  FOVIE1
-            FOVIE1: u1,
-            reserved8: u1,
-            ///  EWGIE
-            EWGIE: u1,
-            ///  EPVIE
-            EPVIE: u1,
-            ///  BOFIE
-            BOFIE: u1,
-            ///  LECIE
-            LECIE: u1,
-            reserved15: u3,
-            ///  ERRIE
-            ERRIE: u1,
-            ///  WKUIE
-            WKUIE: u1,
-            ///  SLKIE
-            SLKIE: u1,
-            padding: u14,
-        }),
-        ///  error status register
-        ESR: mmio.Mmio(packed struct(u32) {
-            ///  EWGF
-            EWGF: u1,
-            ///  EPVF
-            EPVF: u1,
-            ///  BOFF
-            BOFF: u1,
-            reserved4: u1,
-            ///  LEC
-            LEC: u3,
-            reserved16: u9,
-            ///  TEC
-            TEC: u8,
-            ///  REC
-            REC: u8,
-        }),
-        ///  bit timing register
-        BTR: mmio.Mmio(packed struct(u32) {
-            ///  BRP
-            BRP: u10,
-            reserved16: u6,
-            ///  TS1
-            TS1: u4,
-            ///  TS2
-            TS2: u3,
-            reserved24: u1,
-            ///  SJW
-            SJW: u2,
-            reserved30: u4,
-            ///  LBKM
-            LBKM: u1,
-            ///  SILM
-            SILM: u1,
-        }),
-        reserved384: [352]u8,
-        ///  TX mailbox identifier register
-        TI0R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data length control and time stamp register
-        TDT0R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data low register
-        TDL0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  mailbox data high register
-        TDH0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  TX mailbox identifier register
-        TI1R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data length control and time stamp register
-        TDT1R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data low register
-        TDL1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  mailbox data high register
-        TDH1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  TX mailbox identifier register
-        TI2R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data length control and time stamp register
-        TDT2R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data low register
-        TDL2R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  mailbox data high register
-        TDH2R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  receive FIFO mailbox identifier register
-        RI0R: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  receive FIFO mailbox data length control and time stamp register
-        RDT0R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  FMI
-            FMI: u8,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  receive FIFO mailbox data low register
-        RDL0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  receive FIFO mailbox data high register
-        RDH0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  receive FIFO mailbox identifier register
-        RI1R: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  receive FIFO mailbox data length control and time stamp register
-        RDT1R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  FMI
-            FMI: u8,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  receive FIFO mailbox data low register
-        RDL1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  receive FIFO mailbox data high register
-        RDH1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        reserved512: [48]u8,
-        ///  filter master register
-        FMR: mmio.Mmio(packed struct(u32) {
-            ///  Filter init mode
-            FINIT: u1,
-            reserved8: u7,
-            ///  CAN2 start bank
-            CAN2SB: u6,
-            padding: u18,
-        }),
-        ///  filter mode register
-        FM1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter mode
-            FBM0: u1,
-            ///  Filter mode
-            FBM1: u1,
-            ///  Filter mode
-            FBM2: u1,
-            ///  Filter mode
-            FBM3: u1,
-            ///  Filter mode
-            FBM4: u1,
-            ///  Filter mode
-            FBM5: u1,
-            ///  Filter mode
-            FBM6: u1,
-            ///  Filter mode
-            FBM7: u1,
-            ///  Filter mode
-            FBM8: u1,
-            ///  Filter mode
-            FBM9: u1,
-            ///  Filter mode
-            FBM10: u1,
-            ///  Filter mode
-            FBM11: u1,
-            ///  Filter mode
-            FBM12: u1,
-            ///  Filter mode
-            FBM13: u1,
-            ///  Filter mode
-            FBM14: u1,
-            ///  Filter mode
-            FBM15: u1,
-            ///  Filter mode
-            FBM16: u1,
-            ///  Filter mode
-            FBM17: u1,
-            ///  Filter mode
-            FBM18: u1,
-            ///  Filter mode
-            FBM19: u1,
-            ///  Filter mode
-            FBM20: u1,
-            ///  Filter mode
-            FBM21: u1,
-            ///  Filter mode
-            FBM22: u1,
-            ///  Filter mode
-            FBM23: u1,
-            ///  Filter mode
-            FBM24: u1,
-            ///  Filter mode
-            FBM25: u1,
-            ///  Filter mode
-            FBM26: u1,
-            ///  Filter mode
-            FBM27: u1,
-            padding: u4,
-        }),
-        reserved524: [4]u8,
-        ///  filter scale register
-        FS1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter scale configuration
-            FSC0: u1,
-            ///  Filter scale configuration
-            FSC1: u1,
-            ///  Filter scale configuration
-            FSC2: u1,
-            ///  Filter scale configuration
-            FSC3: u1,
-            ///  Filter scale configuration
-            FSC4: u1,
-            ///  Filter scale configuration
-            FSC5: u1,
-            ///  Filter scale configuration
-            FSC6: u1,
-            ///  Filter scale configuration
-            FSC7: u1,
-            ///  Filter scale configuration
-            FSC8: u1,
-            ///  Filter scale configuration
-            FSC9: u1,
-            ///  Filter scale configuration
-            FSC10: u1,
-            ///  Filter scale configuration
-            FSC11: u1,
-            ///  Filter scale configuration
-            FSC12: u1,
-            ///  Filter scale configuration
-            FSC13: u1,
-            ///  Filter scale configuration
-            FSC14: u1,
-            ///  Filter scale configuration
-            FSC15: u1,
-            ///  Filter scale configuration
-            FSC16: u1,
-            ///  Filter scale configuration
-            FSC17: u1,
-            ///  Filter scale configuration
-            FSC18: u1,
-            ///  Filter scale configuration
-            FSC19: u1,
-            ///  Filter scale configuration
-            FSC20: u1,
-            ///  Filter scale configuration
-            FSC21: u1,
-            ///  Filter scale configuration
-            FSC22: u1,
-            ///  Filter scale configuration
-            FSC23: u1,
-            ///  Filter scale configuration
-            FSC24: u1,
-            ///  Filter scale configuration
-            FSC25: u1,
-            ///  Filter scale configuration
-            FSC26: u1,
-            ///  Filter scale configuration
-            FSC27: u1,
-            padding: u4,
-        }),
-        reserved532: [4]u8,
-        ///  filter FIFO assignment register
-        FFA1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter FIFO assignment for filter 0
-            FFA0: u1,
-            ///  Filter FIFO assignment for filter 1
-            FFA1: u1,
-            ///  Filter FIFO assignment for filter 2
-            FFA2: u1,
-            ///  Filter FIFO assignment for filter 3
-            FFA3: u1,
-            ///  Filter FIFO assignment for filter 4
-            FFA4: u1,
-            ///  Filter FIFO assignment for filter 5
-            FFA5: u1,
-            ///  Filter FIFO assignment for filter 6
-            FFA6: u1,
-            ///  Filter FIFO assignment for filter 7
-            FFA7: u1,
-            ///  Filter FIFO assignment for filter 8
-            FFA8: u1,
-            ///  Filter FIFO assignment for filter 9
-            FFA9: u1,
-            ///  Filter FIFO assignment for filter 10
-            FFA10: u1,
-            ///  Filter FIFO assignment for filter 11
-            FFA11: u1,
-            ///  Filter FIFO assignment for filter 12
-            FFA12: u1,
-            ///  Filter FIFO assignment for filter 13
-            FFA13: u1,
-            ///  Filter FIFO assignment for filter 14
-            FFA14: u1,
-            ///  Filter FIFO assignment for filter 15
-            FFA15: u1,
-            ///  Filter FIFO assignment for filter 16
-            FFA16: u1,
-            ///  Filter FIFO assignment for filter 17
-            FFA17: u1,
-            ///  Filter FIFO assignment for filter 18
-            FFA18: u1,
-            ///  Filter FIFO assignment for filter 19
-            FFA19: u1,
-            ///  Filter FIFO assignment for filter 20
-            FFA20: u1,
-            ///  Filter FIFO assignment for filter 21
-            FFA21: u1,
-            ///  Filter FIFO assignment for filter 22
-            FFA22: u1,
-            ///  Filter FIFO assignment for filter 23
-            FFA23: u1,
-            ///  Filter FIFO assignment for filter 24
-            FFA24: u1,
-            ///  Filter FIFO assignment for filter 25
-            FFA25: u1,
-            ///  Filter FIFO assignment for filter 26
-            FFA26: u1,
-            ///  Filter FIFO assignment for filter 27
-            FFA27: u1,
-            padding: u4,
-        }),
-        reserved540: [4]u8,
-        ///  CAN filter activation register
-        FA1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter active
-            FACT0: u1,
-            ///  Filter active
-            FACT1: u1,
-            ///  Filter active
-            FACT2: u1,
-            ///  Filter active
-            FACT3: u1,
-            ///  Filter active
-            FACT4: u1,
-            ///  Filter active
-            FACT5: u1,
-            ///  Filter active
-            FACT6: u1,
-            ///  Filter active
-            FACT7: u1,
-            ///  Filter active
-            FACT8: u1,
-            ///  Filter active
-            FACT9: u1,
-            ///  Filter active
-            FACT10: u1,
-            ///  Filter active
-            FACT11: u1,
-            ///  Filter active
-            FACT12: u1,
-            ///  Filter active
-            FACT13: u1,
-            ///  Filter active
-            FACT14: u1,
-            ///  Filter active
-            FACT15: u1,
-            ///  Filter active
-            FACT16: u1,
-            ///  Filter active
-            FACT17: u1,
-            ///  Filter active
-            FACT18: u1,
-            ///  Filter active
-            FACT19: u1,
-            ///  Filter active
-            FACT20: u1,
-            ///  Filter active
-            FACT21: u1,
-            ///  Filter active
-            FACT22: u1,
-            ///  Filter active
-            FACT23: u1,
-            ///  Filter active
-            FACT24: u1,
-            ///  Filter active
-            FACT25: u1,
-            ///  Filter active
-            FACT26: u1,
-            ///  Filter active
-            FACT27: u1,
-            padding: u4,
-        }),
-        reserved576: [32]u8,
-        ///  Filter bank 0 register 1
-        F0R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 0 register 2
-        F0R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 1 register 1
-        F1R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 1 register 2
-        F1R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 2 register 1
-        F2R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 2 register 2
-        F2R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 3 register 1
-        F3R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 3 register 2
-        F3R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 1
-        F4R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 2
-        F4R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 5 register 1
-        F5R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 5 register 2
-        F5R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 6 register 1
-        F6R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 6 register 2
-        F6R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 7 register 1
-        F7R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 7 register 2
-        F7R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 8 register 1
-        F8R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 8 register 2
-        F8R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 9 register 1
-        F9R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 9 register 2
-        F9R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 10 register 1
-        F10R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 10 register 2
-        F10R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 11 register 1
-        F11R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 11 register 2
-        F11R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 1
-        F12R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 12 register 2
-        F12R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 13 register 1
-        F13R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 13 register 2
-        F13R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 14 register 1
-        F14R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 14 register 2
-        F14R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 15 register 1
-        F15R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 15 register 2
-        F15R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 16 register 1
-        F16R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 16 register 2
-        F16R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 17 register 1
-        F17R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 17 register 2
-        F17R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 18 register 1
-        F18R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 18 register 2
-        F18R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 19 register 1
-        F19R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 19 register 2
-        F19R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 20 register 1
-        F20R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 20 register 2
-        F20R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 21 register 1
-        F21R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 21 register 2
-        F21R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 22 register 1
-        F22R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 22 register 2
-        F22R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 23 register 1
-        F23R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 23 register 2
-        F23R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 24 register 1
-        F24R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 24 register 2
-        F24R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 25 register 1
-        F25R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 25 register 2
-        F25R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 26 register 1
-        F26R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 26 register 2
-        F26R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 27 register 1
-        F27R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 27 register 2
-        F27R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-    };
-
-    ///  Universal serial bus full-speed device interface
-    pub const USB_FS = extern struct {
-        ///  endpoint 0 register
-        USB_EP0R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 1 register
-        USB_EP1R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 2 register
-        USB_EP2R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 3 register
-        USB_EP3R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 4 register
-        USB_EP4R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 5 register
-        USB_EP5R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 6 register
-        USB_EP6R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        ///  endpoint 7 register
-        USB_EP7R: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint address
-            EA: u4,
-            ///  Status bits, for transmission transfers
-            STAT_TX: u2,
-            ///  Data Toggle, for transmission transfers
-            DTOG_TX: u1,
-            ///  Correct Transfer for transmission
-            CTR_TX: u1,
-            ///  Endpoint kind
-            EP_KIND: u1,
-            ///  Endpoint type
-            EP_TYPE: u2,
-            ///  Setup transaction completed
-            SETUP: u1,
-            ///  Status bits, for reception transfers
-            STAT_RX: u2,
-            ///  Data Toggle, for reception transfers
-            DTOG_RX: u1,
-            ///  Correct transfer for reception
-            CTR_RX: u1,
-            padding: u16,
-        }),
-        reserved64: [32]u8,
-        ///  control register
-        USB_CNTR: mmio.Mmio(packed struct(u32) {
-            ///  Force USB Reset
-            FRES: u1,
-            ///  Power down
-            PDWN: u1,
-            ///  Low-power mode
-            LPMODE: u1,
-            ///  Force suspend
-            FSUSP: u1,
-            ///  Resume request
-            RESUME: u1,
-            reserved8: u3,
-            ///  Expected start of frame interrupt mask
-            ESOFM: u1,
-            ///  Start of frame interrupt mask
-            SOFM: u1,
-            ///  USB reset interrupt mask
-            RESETM: u1,
-            ///  Suspend mode interrupt mask
-            SUSPM: u1,
-            ///  Wakeup interrupt mask
-            WKUPM: u1,
-            ///  Error interrupt mask
-            ERRM: u1,
-            ///  Packet memory area over / underrun interrupt mask
-            PMAOVRM: u1,
-            ///  Correct transfer interrupt mask
-            CTRM: u1,
-            padding: u16,
-        }),
-        ///  interrupt status register
-        ISTR: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint Identifier
-            EP_ID: u4,
-            ///  Direction of transaction
-            DIR: u1,
-            reserved8: u3,
-            ///  Expected start frame
-            ESOF: u1,
-            ///  start of frame
-            SOF: u1,
-            ///  reset request
-            RESET: u1,
-            ///  Suspend mode request
-            SUSP: u1,
-            ///  Wakeup
-            WKUP: u1,
-            ///  Error
-            ERR: u1,
-            ///  Packet memory area over / underrun
-            PMAOVR: u1,
-            ///  Correct transfer
-            CTR: u1,
-            padding: u16,
-        }),
-        ///  frame number register
-        FNR: mmio.Mmio(packed struct(u32) {
-            ///  Frame number
-            FN: u11,
-            ///  Lost SOF
-            LSOF: u2,
-            ///  Locked
-            LCK: u1,
-            ///  Receive data - line status
-            RXDM: u1,
-            ///  Receive data + line status
-            RXDP: u1,
-            padding: u16,
-        }),
-        ///  device address
-        DADDR: mmio.Mmio(packed struct(u32) {
-            ///  Device address
-            ADD: u1,
-            ///  Device address
-            ADD1: u1,
-            ///  Device address
-            ADD2: u1,
-            ///  Device address
-            ADD3: u1,
-            ///  Device address
-            ADD4: u1,
-            ///  Device address
-            ADD5: u1,
-            ///  Device address
-            ADD6: u1,
-            ///  Enable function
-            EF: u1,
-            padding: u24,
-        }),
-        ///  Buffer table address
-        BTABLE: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Buffer table
-            BTABLE: u13,
-            padding: u16,
-        }),
-    };
-
-    ///  Inter-integrated circuit
-    pub const I2C1 = extern struct {
-        ///  Control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral enable
-            PE: u1,
-            ///  TX Interrupt enable
-            TXIE: u1,
-            ///  RX Interrupt enable
-            RXIE: u1,
-            ///  Address match interrupt enable (slave only)
-            ADDRIE: u1,
-            ///  Not acknowledge received interrupt enable
-            NACKIE: u1,
-            ///  STOP detection Interrupt enable
-            STOPIE: u1,
-            ///  Transfer Complete interrupt enable
-            TCIE: u1,
-            ///  Error interrupts enable
-            ERRIE: u1,
-            ///  Digital noise filter
-            DNF: u4,
-            ///  Analog noise filter OFF
-            ANFOFF: u1,
-            ///  Software reset
-            SWRST: u1,
-            ///  DMA transmission requests enable
-            TXDMAEN: u1,
-            ///  DMA reception requests enable
-            RXDMAEN: u1,
-            ///  Slave byte control
-            SBC: u1,
-            ///  Clock stretching disable
-            NOSTRETCH: u1,
-            ///  Wakeup from STOP enable
-            WUPEN: u1,
-            ///  General call enable
-            GCEN: u1,
-            ///  SMBus Host address enable
-            SMBHEN: u1,
-            ///  SMBus Device Default address enable
-            SMBDEN: u1,
-            ///  SMBUS alert enable
-            ALERTEN: u1,
-            ///  PEC enable
-            PECEN: u1,
-            padding: u8,
-        }),
-        ///  Control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Slave address bit 0 (master mode)
-            SADD0: u1,
-            ///  Slave address bit 7:1 (master mode)
-            SADD1: u7,
-            ///  Slave address bit 9:8 (master mode)
-            SADD8: u2,
-            ///  Transfer direction (master mode)
-            RD_WRN: u1,
-            ///  10-bit addressing mode (master mode)
-            ADD10: u1,
-            ///  10-bit address header only read direction (master receiver mode)
-            HEAD10R: u1,
-            ///  Start generation
-            START: u1,
-            ///  Stop generation (master mode)
-            STOP: u1,
-            ///  NACK generation (slave mode)
-            NACK: u1,
-            ///  Number of bytes
-            NBYTES: u8,
-            ///  NBYTES reload mode
-            RELOAD: u1,
-            ///  Automatic end mode (master mode)
-            AUTOEND: u1,
-            ///  Packet error checking byte
-            PECBYTE: u1,
-            padding: u5,
-        }),
-        ///  Own address register 1
-        OAR1: mmio.Mmio(packed struct(u32) {
-            ///  Interface address
-            OA1_0: u1,
-            ///  Interface address
-            OA1_1: u7,
-            ///  Interface address
-            OA1_8: u2,
-            ///  Own Address 1 10-bit mode
-            OA1MODE: u1,
-            reserved15: u4,
-            ///  Own Address 1 enable
-            OA1EN: u1,
-            padding: u16,
-        }),
-        ///  Own address register 2
-        OAR2: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Interface address
-            OA2: u7,
-            ///  Own Address 2 masks
-            OA2MSK: u3,
-            reserved15: u4,
-            ///  Own Address 2 enable
-            OA2EN: u1,
-            padding: u16,
-        }),
-        ///  Timing register
-        TIMINGR: mmio.Mmio(packed struct(u32) {
-            ///  SCL low period (master mode)
-            SCLL: u8,
-            ///  SCL high period (master mode)
-            SCLH: u8,
-            ///  Data hold time
-            SDADEL: u4,
-            ///  Data setup time
-            SCLDEL: u4,
-            reserved28: u4,
-            ///  Timing prescaler
-            PRESC: u4,
-        }),
-        ///  Status register 1
-        TIMEOUTR: mmio.Mmio(packed struct(u32) {
-            ///  Bus timeout A
-            TIMEOUTA: u12,
-            ///  Idle clock timeout detection
-            TIDLE: u1,
-            reserved15: u2,
-            ///  Clock timeout enable
-            TIMOUTEN: u1,
-            ///  Bus timeout B
-            TIMEOUTB: u12,
-            reserved31: u3,
-            ///  Extended clock timeout enable
-            TEXTEN: u1,
-        }),
-        ///  Interrupt and Status register
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  Transmit data register empty (transmitters)
-            TXE: u1,
-            ///  Transmit interrupt status (transmitters)
-            TXIS: u1,
-            ///  Receive data register not empty (receivers)
-            RXNE: u1,
-            ///  Address matched (slave mode)
-            ADDR: u1,
-            ///  Not acknowledge received flag
-            NACKF: u1,
-            ///  Stop detection flag
-            STOPF: u1,
-            ///  Transfer Complete (master mode)
-            TC: u1,
-            ///  Transfer Complete Reload
-            TCR: u1,
-            ///  Bus error
-            BERR: u1,
-            ///  Arbitration lost
-            ARLO: u1,
-            ///  Overrun/Underrun (slave mode)
-            OVR: u1,
-            ///  PEC Error in reception
-            PECERR: u1,
-            ///  Timeout or t_low detection flag
-            TIMEOUT: u1,
-            ///  SMBus alert
-            ALERT: u1,
-            reserved15: u1,
-            ///  Bus busy
-            BUSY: u1,
-            ///  Transfer direction (Slave mode)
-            DIR: u1,
-            ///  Address match code (Slave mode)
-            ADDCODE: u7,
-            padding: u8,
-        }),
-        ///  Interrupt clear register
-        ICR: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Address Matched flag clear
-            ADDRCF: u1,
-            ///  Not Acknowledge flag clear
-            NACKCF: u1,
-            ///  Stop detection flag clear
-            STOPCF: u1,
-            reserved8: u2,
-            ///  Bus error flag clear
-            BERRCF: u1,
-            ///  Arbitration lost flag clear
-            ARLOCF: u1,
-            ///  Overrun/Underrun flag clear
-            OVRCF: u1,
-            ///  PEC Error flag clear
-            PECCF: u1,
-            ///  Timeout detection flag clear
-            TIMOUTCF: u1,
-            ///  Alert flag clear
-            ALERTCF: u1,
-            padding: u18,
-        }),
-        ///  PEC register
-        PECR: mmio.Mmio(packed struct(u32) {
-            ///  Packet error checking register
-            PEC: u8,
-            padding: u24,
-        }),
-        ///  Receive data register
-        RXDR: mmio.Mmio(packed struct(u32) {
-            ///  8-bit receive data
-            RXDATA: u8,
-            padding: u24,
-        }),
-        ///  Transmit data register
-        TXDR: mmio.Mmio(packed struct(u32) {
-            ///  8-bit transmit data
-            TXDATA: u8,
-            padding: u24,
-        }),
-    };
-
-    ///  Advanced timer
-    pub const TIM1 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            reserved11: u1,
-            ///  UIF status bit remapping
-            UIFREMAP: u1,
-            padding: u20,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/compare preloaded control
-            CCPC: u1,
-            reserved2: u1,
-            ///  Capture/compare control update selection
-            CCUS: u1,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            ///  Output Idle state 1
-            OIS1: u1,
-            ///  Output Idle state 1
-            OIS1N: u1,
-            ///  Output Idle state 2
-            OIS2: u1,
-            ///  Output Idle state 2
-            OIS2N: u1,
-            ///  Output Idle state 3
-            OIS3: u1,
-            ///  Output Idle state 3
-            OIS3N: u1,
-            ///  Output Idle state 4
-            OIS4: u1,
-            reserved16: u1,
-            ///  Output Idle state 5
-            OIS5: u1,
-            reserved18: u1,
-            ///  Output Idle state 6
-            OIS6: u1,
-            reserved20: u1,
-            ///  Master mode selection 2
-            MMS2: u4,
-            padding: u8,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            ///  OCREF clear selection
-            OCCS: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            ///  Slave mode selection bit 3
-            SMS3: u1,
-            padding: u15,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            ///  COM interrupt enable
-            COMIE: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            ///  Break interrupt enable
-            BIE: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            ///  COM DMA request enable
-            COMDE: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            ///  COM interrupt flag
-            COMIF: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            ///  Break interrupt flag
-            BIF: u1,
-            ///  Break 2 interrupt flag
-            B2IF: u1,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            reserved16: u3,
-            ///  Capture/Compare 5 interrupt flag
-            C5IF: u1,
-            ///  Capture/Compare 6 interrupt flag
-            C6IF: u1,
-            padding: u14,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            ///  Capture/Compare control update generation
-            COMG: u1,
-            ///  Trigger generation
-            TG: u1,
-            ///  Break generation
-            BG: u1,
-            ///  Break 2 generation
-            B2G: u1,
-            padding: u23,
-        }),
-        ///  capture/compare mode register (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            ///  Output Compare 1 clear enable
-            OC1CE: u1,
-            ///  Capture/Compare 2 selection
-            CC2S: u2,
-            ///  Output Compare 2 fast enable
-            OC2FE: u1,
-            ///  Output Compare 2 preload enable
-            OC2PE: u1,
-            ///  Output Compare 2 mode
-            OC2M: u3,
-            ///  Output Compare 2 clear enable
-            OC2CE: u1,
-            ///  Output Compare 1 mode bit 3
-            OC1M_3: u1,
-            reserved24: u7,
-            ///  Output Compare 2 mode bit 3
-            OC2M_3: u1,
-            padding: u7,
-        }),
-        ///  capture/compare mode register (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 3 selection
-            CC3S: u2,
-            ///  Output compare 3 fast enable
-            OC3FE: u1,
-            ///  Output compare 3 preload enable
-            OC3PE: u1,
-            ///  Output compare 3 mode
-            OC3M: u3,
-            ///  Output compare 3 clear enable
-            OC3CE: u1,
-            ///  Capture/Compare 4 selection
-            CC4S: u2,
-            ///  Output compare 4 fast enable
-            OC4FE: u1,
-            ///  Output compare 4 preload enable
-            OC4PE: u1,
-            ///  Output compare 4 mode
-            OC4M: u3,
-            ///  Output compare 4 clear enable
-            OC4CE: u1,
-            ///  Output Compare 3 mode bit 3
-            OC3M_3: u1,
-            reserved24: u7,
-            ///  Output Compare 4 mode bit 3
-            OC4M_3: u1,
-            padding: u7,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            ///  Capture/Compare 1 complementary output enable
-            CC1NE: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            ///  Capture/Compare 2 complementary output enable
-            CC2NE: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            ///  Capture/Compare 3 complementary output enable
-            CC3NE: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            reserved15: u1,
-            ///  Capture/Compare 4 output Polarity
-            CC4NP: u1,
-            ///  Capture/Compare 5 output enable
-            CC5E: u1,
-            ///  Capture/Compare 5 output Polarity
-            CC5P: u1,
-            reserved20: u2,
-            ///  Capture/Compare 6 output enable
-            CC6E: u1,
-            ///  Capture/Compare 6 output Polarity
-            CC6P: u1,
-            padding: u10,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            reserved31: u15,
-            ///  UIF copy
-            UIFCPY: u1,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        ///  repetition counter register
-        RCR: mmio.Mmio(packed struct(u32) {
-            ///  Repetition counter value
-            REP: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 2 value
-            CCR2: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 3 value
-            CCR3: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 3 value
-            CCR4: u16,
-            padding: u16,
-        }),
-        ///  break and dead-time register
-        BDTR: mmio.Mmio(packed struct(u32) {
-            ///  Dead-time generator setup
-            DTG: u8,
-            ///  Lock configuration
-            LOCK: u2,
-            ///  Off-state selection for Idle mode
-            OSSI: u1,
-            ///  Off-state selection for Run mode
-            OSSR: u1,
-            ///  Break enable
-            BKE: u1,
-            ///  Break polarity
-            BKP: u1,
-            ///  Automatic output enable
-            AOE: u1,
-            ///  Main output enable
-            MOE: u1,
-            ///  Break filter
-            BKF: u4,
-            ///  Break 2 filter
-            BK2F: u4,
-            ///  Break 2 enable
-            BK2E: u1,
-            ///  Break 2 polarity
-            BK2P: u1,
-            padding: u6,
-        }),
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-        reserved84: [4]u8,
-        ///  capture/compare mode register 3 (output mode)
-        CCMR3_Output: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Output compare 5 fast enable
-            OC5FE: u1,
-            ///  Output compare 5 preload enable
-            OC5PE: u1,
-            ///  Output compare 5 mode
-            OC5M: u3,
-            ///  Output compare 5 clear enable
-            OC5CE: u1,
-            reserved10: u2,
-            ///  Output compare 6 fast enable
-            OC6FE: u1,
-            ///  Output compare 6 preload enable
-            OC6PE: u1,
-            ///  Output compare 6 mode
-            OC6M: u3,
-            ///  Output compare 6 clear enable
-            OC6CE: u1,
-            ///  Outout Compare 5 mode bit 3
-            OC5M_3: u1,
-            reserved24: u7,
-            ///  Outout Compare 6 mode bit 3
-            OC6M_3: u1,
-            padding: u7,
-        }),
-        ///  capture/compare register 5
-        CCR5: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 5 value
-            CCR5: u16,
-            reserved29: u13,
-            ///  Group Channel 5 and Channel 1
-            GC5C1: u1,
-            ///  Group Channel 5 and Channel 2
-            GC5C2: u1,
-            ///  Group Channel 5 and Channel 3
-            GC5C3: u1,
-        }),
-        ///  capture/compare register 6
-        CCR6: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 6 value
-            CCR6: u16,
-            padding: u16,
-        }),
-        ///  option registers
-        OR: mmio.Mmio(packed struct(u32) {
-            ///  TIM1_ETR_ADC1 remapping capability
-            TIM1_ETR_ADC1_RMP: u2,
-            ///  TIM1_ETR_ADC4 remapping capability
-            TIM1_ETR_ADC4_RMP: u2,
-            padding: u28,
-        }),
-    };
-
-    ///  Debug support
-    pub const DBGMCU = extern struct {
-        ///  MCU Device ID Code Register
-        IDCODE: mmio.Mmio(packed struct(u32) {
-            ///  Device Identifier
-            DEV_ID: u12,
-            reserved16: u4,
-            ///  Revision Identifier
-            REV_ID: u16,
-        }),
-        ///  Debug MCU Configuration Register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Debug Sleep mode
-            DBG_SLEEP: u1,
-            ///  Debug Stop Mode
-            DBG_STOP: u1,
-            ///  Debug Standby Mode
-            DBG_STANDBY: u1,
-            reserved5: u2,
-            ///  Trace pin assignment control
-            TRACE_IOEN: u1,
-            ///  Trace pin assignment control
-            TRACE_MODE: u2,
-            padding: u24,
-        }),
-        ///  APB Low Freeze Register
-        APB1FZ: mmio.Mmio(packed struct(u32) {
-            ///  Debug Timer 2 stopped when Core is halted
-            DBG_TIM2_STOP: u1,
-            ///  Debug Timer 3 stopped when Core is halted
-            DBG_TIM3_STOP: u1,
-            ///  Debug Timer 4 stopped when Core is halted
-            DBG_TIM4_STOP: u1,
-            ///  Debug Timer 5 stopped when Core is halted
-            DBG_TIM5_STOP: u1,
-            ///  Debug Timer 6 stopped when Core is halted
-            DBG_TIM6_STOP: u1,
-            ///  Debug Timer 7 stopped when Core is halted
-            DBG_TIM7_STOP: u1,
-            ///  Debug Timer 12 stopped when Core is halted
-            DBG_TIM12_STOP: u1,
-            ///  Debug Timer 13 stopped when Core is halted
-            DBG_TIM13_STOP: u1,
-            ///  Debug Timer 14 stopped when Core is halted
-            DBG_TIMER14_STOP: u1,
-            ///  Debug Timer 18 stopped when Core is halted
-            DBG_TIM18_STOP: u1,
-            ///  Debug RTC stopped when Core is halted
-            DBG_RTC_STOP: u1,
-            ///  Debug Window Wachdog stopped when Core is halted
-            DBG_WWDG_STOP: u1,
-            ///  Debug Independent Wachdog stopped when Core is halted
-            DBG_IWDG_STOP: u1,
-            reserved21: u8,
-            ///  SMBUS timeout mode stopped when Core is halted
-            I2C1_SMBUS_TIMEOUT: u1,
-            ///  SMBUS timeout mode stopped when Core is halted
-            I2C2_SMBUS_TIMEOUT: u1,
-            reserved25: u2,
-            ///  Debug CAN stopped when core is halted
-            DBG_CAN_STOP: u1,
-            padding: u6,
-        }),
-        ///  APB High Freeze Register
-        APB2FZ: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Debug Timer 15 stopped when Core is halted
-            DBG_TIM15_STOP: u1,
-            ///  Debug Timer 16 stopped when Core is halted
-            DBG_TIM16_STOP: u1,
-            ///  Debug Timer 17 stopped when Core is halted
-            DBG_TIM17_STO: u1,
-            ///  Debug Timer 19 stopped when Core is halted
-            DBG_TIM19_STOP: u1,
-            padding: u26,
-        }),
-    };
-};
diff --git a/src/chips/STM32F407.zig b/src/chips/STM32F407.zig
deleted file mode 100644
index c0d311a27..000000000
--- a/src/chips/STM32F407.zig
+++ /dev/null
@@ -1,20004 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    ///  STM32F407
-    pub const STM32F407 = struct {
-        pub const properties = struct {
-            pub const @"cpu.nvic_prio_bits" = "3";
-            pub const @"cpu.mpu" = "false";
-            pub const @"cpu.fpu" = "false";
-            pub const @"cpu.revision" = "r1p0";
-            pub const @"cpu.vendor_systick_config" = "false";
-            pub const @"cpu.endian" = "little";
-            pub const @"cpu.name" = "CM4";
-        };
-
-        pub const VectorTable = extern struct {
-            const Handler = micro.interrupt.Handler;
-            const unhandled = micro.interrupt.unhandled;
-
-            initial_stack_pointer: u32,
-            Reset: Handler = unhandled,
-            NMI: Handler = unhandled,
-            HardFault: Handler = unhandled,
-            MemManageFault: Handler = unhandled,
-            BusFault: Handler = unhandled,
-            UsageFault: Handler = unhandled,
-            reserved5: [4]u32 = undefined,
-            SVCall: Handler = unhandled,
-            DebugMonitor: Handler = unhandled,
-            reserved11: [1]u32 = undefined,
-            PendSV: Handler = unhandled,
-            SysTick: Handler = unhandled,
-            ///  Window Watchdog interrupt
-            WWDG: Handler = unhandled,
-            ///  PVD through EXTI line detection interrupt
-            PVD: Handler = unhandled,
-            ///  Tamper and TimeStamp interrupts through the EXTI line
-            TAMP_STAMP: Handler = unhandled,
-            ///  RTC Wakeup interrupt through the EXTI line
-            RTC_WKUP: Handler = unhandled,
-            reserved18: [1]u32 = undefined,
-            ///  RCC global interrupt
-            RCC: Handler = unhandled,
-            reserved20: [5]u32 = undefined,
-            ///  DMA1 Stream0 global interrupt
-            DMA1_Stream0: Handler = unhandled,
-            reserved26: [6]u32 = undefined,
-            ///  ADC1 global interrupt
-            ADC: Handler = unhandled,
-            ///  CAN1 TX interrupts
-            CAN1_TX: Handler = unhandled,
-            reserved34: [4]u32 = undefined,
-            ///  TIM1 Break interrupt and TIM9 global interrupt
-            TIM1_BRK_TIM9: Handler = unhandled,
-            ///  TIM1 Update interrupt and TIM10 global interrupt
-            TIM1_UP_TIM10: Handler = unhandled,
-            ///  TIM1 Trigger and Commutation interrupts and TIM11 global interrupt
-            TIM1_TRG_COM_TIM11: Handler = unhandled,
-            reserved41: [1]u32 = undefined,
-            ///  TIM2 global interrupt
-            TIM2: Handler = unhandled,
-            ///  TIM3 global interrupt
-            TIM3: Handler = unhandled,
-            ///  TIM4 global interrupt
-            TIM4: Handler = unhandled,
-            ///  I2C1 event interrupt
-            I2C1_EV: Handler = unhandled,
-            reserved46: [1]u32 = undefined,
-            ///  I2C2 event interrupt
-            I2C2_EV: Handler = unhandled,
-            reserved48: [1]u32 = undefined,
-            ///  SPI1 global interrupt
-            SPI1: Handler = unhandled,
-            ///  SPI2 global interrupt
-            SPI2: Handler = unhandled,
-            ///  USART1 global interrupt
-            USART1: Handler = unhandled,
-            ///  USART2 global interrupt
-            USART2: Handler = unhandled,
-            ///  USART3 global interrupt
-            USART3: Handler = unhandled,
-            reserved54: [2]u32 = undefined,
-            ///  USB On-The-Go FS Wakeup through EXTI line interrupt
-            OTG_FS_WKUP: Handler = unhandled,
-            ///  TIM8 Break interrupt and TIM12 global interrupt
-            TIM8_BRK_TIM12: Handler = unhandled,
-            ///  TIM8 Update interrupt and TIM13 global interrupt
-            TIM8_UP_TIM13: Handler = unhandled,
-            ///  TIM8 Trigger and Commutation interrupts and TIM14 global interrupt
-            TIM8_TRG_COM_TIM14: Handler = unhandled,
-            reserved60: [2]u32 = undefined,
-            ///  FSMC global interrupt
-            FSMC: Handler = unhandled,
-            ///  SDIO global interrupt
-            SDIO: Handler = unhandled,
-            ///  TIM5 global interrupt
-            TIM5: Handler = unhandled,
-            ///  SPI3 global interrupt
-            SPI3: Handler = unhandled,
-            ///  UART4 global interrupt
-            UART4: Handler = unhandled,
-            ///  UART5 global interrupt
-            UART5: Handler = unhandled,
-            ///  TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt
-            TIM6_DAC: Handler = unhandled,
-            ///  TIM7 global interrupt
-            TIM7: Handler = unhandled,
-            ///  DMA2 Stream0 global interrupt
-            DMA2_Stream0: Handler = unhandled,
-            reserved71: [4]u32 = undefined,
-            ///  Ethernet global interrupt
-            ETH: Handler = unhandled,
-            reserved76: [1]u32 = undefined,
-            ///  CAN2 TX interrupts
-            CAN2_TX: Handler = unhandled,
-            reserved78: [7]u32 = undefined,
-            ///  USART6 global interrupt
-            USART6: Handler = unhandled,
-            ///  I2C3 event interrupt
-            I2C3_EV: Handler = unhandled,
-            reserved87: [1]u32 = undefined,
-            ///  USB On The Go HS End Point 1 Out global interrupt
-            OTG_HS_EP1_OUT: Handler = unhandled,
-            reserved89: [3]u32 = undefined,
-            ///  DCMI global interrupt
-            DCMI: Handler = unhandled,
-            ///  CRYP crypto global interrupt
-            CRYP: Handler = unhandled,
-            ///  Hash and Rng global interrupt
-            HASH_RNG: Handler = unhandled,
-            ///  FPU interrupt
-            FPU: Handler = unhandled,
-            reserved96: [6]u32 = undefined,
-            ///  LTDC global interrupt
-            LCD_TFT: Handler = unhandled,
-        };
-
-        pub const peripherals = struct {
-            ///  General purpose timers
-            pub const TIM2 = @as(*volatile types.TIM2, @ptrFromInt(0x40000000));
-            ///  General purpose timers
-            pub const TIM3 = @as(*volatile types.TIM3, @ptrFromInt(0x40000400));
-            ///  General purpose timers
-            pub const TIM4 = @as(*volatile types.TIM3, @ptrFromInt(0x40000800));
-            ///  General-purpose-timers
-            pub const TIM5 = @as(*volatile types.TIM5, @ptrFromInt(0x40000c00));
-            ///  Basic timers
-            pub const TIM6 = @as(*volatile types.TIM6, @ptrFromInt(0x40001000));
-            ///  Basic timers
-            pub const TIM7 = @as(*volatile types.TIM6, @ptrFromInt(0x40001400));
-            ///  General purpose timers
-            pub const TIM12 = @as(*volatile types.TIM9, @ptrFromInt(0x40001800));
-            ///  General-purpose-timers
-            pub const TIM13 = @as(*volatile types.TIM10, @ptrFromInt(0x40001c00));
-            ///  General-purpose-timers
-            pub const TIM14 = @as(*volatile types.TIM10, @ptrFromInt(0x40002000));
-            ///  Real-time clock
-            pub const RTC = @as(*volatile types.RTC, @ptrFromInt(0x40002800));
-            ///  Window watchdog
-            pub const WWDG = @as(*volatile types.WWDG, @ptrFromInt(0x40002c00));
-            ///  Independent watchdog
-            pub const IWDG = @as(*volatile types.IWDG, @ptrFromInt(0x40003000));
-            ///  Serial peripheral interface
-            pub const I2S2ext = @as(*volatile types.SPI1, @ptrFromInt(0x40003400));
-            ///  Serial peripheral interface
-            pub const SPI2 = @as(*volatile types.SPI1, @ptrFromInt(0x40003800));
-            ///  Serial peripheral interface
-            pub const SPI3 = @as(*volatile types.SPI1, @ptrFromInt(0x40003c00));
-            ///  Serial peripheral interface
-            pub const I2S3ext = @as(*volatile types.SPI1, @ptrFromInt(0x40004000));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART2 = @as(*volatile types.USART6, @ptrFromInt(0x40004400));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART3 = @as(*volatile types.USART6, @ptrFromInt(0x40004800));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART4 = @as(*volatile types.UART4, @ptrFromInt(0x40004c00));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART5 = @as(*volatile types.UART4, @ptrFromInt(0x40005000));
-            ///  Inter-integrated circuit
-            pub const I2C1 = @as(*volatile types.I2C3, @ptrFromInt(0x40005400));
-            ///  Inter-integrated circuit
-            pub const I2C2 = @as(*volatile types.I2C3, @ptrFromInt(0x40005800));
-            ///  Inter-integrated circuit
-            pub const I2C3 = @as(*volatile types.I2C3, @ptrFromInt(0x40005c00));
-            ///  Controller area network
-            pub const CAN1 = @as(*volatile types.CAN1, @ptrFromInt(0x40006400));
-            ///  Controller area network
-            pub const CAN2 = @as(*volatile types.CAN1, @ptrFromInt(0x40006800));
-            ///  Power control
-            pub const PWR = @as(*volatile types.PWR, @ptrFromInt(0x40007000));
-            ///  Digital-to-analog converter
-            pub const DAC = @as(*volatile types.DAC, @ptrFromInt(0x40007400));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART7 = @as(*volatile types.UART4, @ptrFromInt(0x40007800));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART8 = @as(*volatile types.UART4, @ptrFromInt(0x40007c00));
-            ///  Advanced-timers
-            pub const TIM1 = @as(*volatile types.TIM1, @ptrFromInt(0x40010000));
-            ///  Advanced-timers
-            pub const TIM8 = @as(*volatile types.TIM1, @ptrFromInt(0x40010400));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART1 = @as(*volatile types.USART6, @ptrFromInt(0x40011000));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART6 = @as(*volatile types.USART6, @ptrFromInt(0x40011400));
-            ///  Analog-to-digital converter
-            pub const ADC1 = @as(*volatile types.ADC1, @ptrFromInt(0x40012000));
-            ///  Analog-to-digital converter
-            pub const ADC2 = @as(*volatile types.ADC1, @ptrFromInt(0x40012100));
-            ///  Analog-to-digital converter
-            pub const ADC3 = @as(*volatile types.ADC1, @ptrFromInt(0x40012200));
-            ///  Common ADC registers
-            pub const C_ADC = @as(*volatile types.C_ADC, @ptrFromInt(0x40012300));
-            ///  Secure digital input/output interface
-            pub const SDIO = @as(*volatile types.SDIO, @ptrFromInt(0x40012c00));
-            ///  Serial peripheral interface
-            pub const SPI1 = @as(*volatile types.SPI1, @ptrFromInt(0x40013000));
-            ///  Serial peripheral interface
-            pub const SPI4 = @as(*volatile types.SPI1, @ptrFromInt(0x40013400));
-            ///  System configuration controller
-            pub const SYSCFG = @as(*volatile types.SYSCFG, @ptrFromInt(0x40013800));
-            ///  External interrupt/event controller
-            pub const EXTI = @as(*volatile types.EXTI, @ptrFromInt(0x40013c00));
-            ///  General purpose timers
-            pub const TIM9 = @as(*volatile types.TIM9, @ptrFromInt(0x40014000));
-            ///  General-purpose-timers
-            pub const TIM10 = @as(*volatile types.TIM10, @ptrFromInt(0x40014400));
-            ///  General-purpose-timers
-            pub const TIM11 = @as(*volatile types.TIM11, @ptrFromInt(0x40014800));
-            ///  Serial peripheral interface
-            pub const SPI5 = @as(*volatile types.SPI1, @ptrFromInt(0x40015000));
-            ///  Serial peripheral interface
-            pub const SPI6 = @as(*volatile types.SPI1, @ptrFromInt(0x40015400));
-            ///  Serial audio interface
-            pub const SAI1 = @as(*volatile types.SAI1, @ptrFromInt(0x40015800));
-            ///  LCD-TFT Controller
-            pub const LTDC = @as(*volatile types.LTDC, @ptrFromInt(0x40016800));
-            ///  General-purpose I/Os
-            pub const GPIOA = @as(*volatile types.GPIOA, @ptrFromInt(0x40020000));
-            ///  General-purpose I/Os
-            pub const GPIOB = @as(*volatile types.GPIOB, @ptrFromInt(0x40020400));
-            ///  General-purpose I/Os
-            pub const GPIOC = @as(*volatile types.GPIOI, @ptrFromInt(0x40020800));
-            ///  General-purpose I/Os
-            pub const GPIOD = @as(*volatile types.GPIOI, @ptrFromInt(0x40020c00));
-            ///  General-purpose I/Os
-            pub const GPIOE = @as(*volatile types.GPIOI, @ptrFromInt(0x40021000));
-            ///  General-purpose I/Os
-            pub const GPIOF = @as(*volatile types.GPIOI, @ptrFromInt(0x40021400));
-            ///  General-purpose I/Os
-            pub const GPIOG = @as(*volatile types.GPIOI, @ptrFromInt(0x40021800));
-            ///  General-purpose I/Os
-            pub const GPIOH = @as(*volatile types.GPIOI, @ptrFromInt(0x40021c00));
-            ///  General-purpose I/Os
-            pub const GPIOI = @as(*volatile types.GPIOI, @ptrFromInt(0x40022000));
-            ///  General-purpose I/Os
-            pub const GPIOJ = @as(*volatile types.GPIOI, @ptrFromInt(0x40022400));
-            ///  General-purpose I/Os
-            pub const GPIOK = @as(*volatile types.GPIOI, @ptrFromInt(0x40022800));
-            ///  Cryptographic processor
-            pub const CRC = @as(*volatile types.CRC, @ptrFromInt(0x40023000));
-            ///  Reset and clock control
-            pub const RCC = @as(*volatile types.RCC, @ptrFromInt(0x40023800));
-            ///  FLASH
-            pub const FLASH = @as(*volatile types.FLASH, @ptrFromInt(0x40023c00));
-            ///  DMA controller
-            pub const DMA1 = @as(*volatile types.DMA2, @ptrFromInt(0x40026000));
-            ///  DMA controller
-            pub const DMA2 = @as(*volatile types.DMA2, @ptrFromInt(0x40026400));
-            ///  Ethernet: media access control (MAC)
-            pub const Ethernet_MAC = @as(*volatile types.Ethernet_MAC, @ptrFromInt(0x40028000));
-            ///  Ethernet: MAC management counters
-            pub const Ethernet_MMC = @as(*volatile types.Ethernet_MMC, @ptrFromInt(0x40028100));
-            ///  Ethernet: Precision time protocol
-            pub const Ethernet_PTP = @as(*volatile types.Ethernet_PTP, @ptrFromInt(0x40028700));
-            ///  Ethernet: DMA controller operation
-            pub const Ethernet_DMA = @as(*volatile types.Ethernet_DMA, @ptrFromInt(0x40029000));
-            ///  USB on the go high speed
-            pub const OTG_HS_GLOBAL = @as(*volatile types.OTG_HS_GLOBAL, @ptrFromInt(0x40040000));
-            ///  USB on the go high speed
-            pub const OTG_HS_HOST = @as(*volatile types.OTG_HS_HOST, @ptrFromInt(0x40040400));
-            ///  USB on the go high speed
-            pub const OTG_HS_DEVICE = @as(*volatile types.OTG_HS_DEVICE, @ptrFromInt(0x40040800));
-            ///  USB on the go high speed
-            pub const OTG_HS_PWRCLK = @as(*volatile types.OTG_HS_PWRCLK, @ptrFromInt(0x40040e00));
-            ///  USB on the go full speed
-            pub const OTG_FS_GLOBAL = @as(*volatile types.OTG_FS_GLOBAL, @ptrFromInt(0x50000000));
-            ///  USB on the go full speed
-            pub const OTG_FS_HOST = @as(*volatile types.OTG_FS_HOST, @ptrFromInt(0x50000400));
-            ///  USB on the go full speed
-            pub const OTG_FS_DEVICE = @as(*volatile types.OTG_FS_DEVICE, @ptrFromInt(0x50000800));
-            ///  USB on the go full speed
-            pub const OTG_FS_PWRCLK = @as(*volatile types.OTG_FS_PWRCLK, @ptrFromInt(0x50000e00));
-            ///  Digital camera interface
-            pub const DCMI = @as(*volatile types.DCMI, @ptrFromInt(0x50050000));
-            ///  Cryptographic processor
-            pub const CRYP = @as(*volatile types.CRYP, @ptrFromInt(0x50060000));
-            ///  Hash processor
-            pub const HASH = @as(*volatile types.HASH, @ptrFromInt(0x50060400));
-            ///  Random number generator
-            pub const RNG = @as(*volatile types.RNG, @ptrFromInt(0x50060800));
-            ///  Flexible static memory controller
-            pub const FSMC = @as(*volatile types.FSMC, @ptrFromInt(0xa0000000));
-            ///  System control block ACTLR
-            pub const SCB_ACTRL = @as(*volatile types.SCB_ACTRL, @ptrFromInt(0xe000e008));
-            ///  SysTick timer
-            pub const STK = @as(*volatile types.STK, @ptrFromInt(0xe000e010));
-            ///  Nested Vectored Interrupt Controller
-            pub const NVIC = @as(*volatile types.NVIC, @ptrFromInt(0xe000e100));
-            ///  System control block
-            pub const SCB = @as(*volatile types.SCB, @ptrFromInt(0xe000ed00));
-            ///  Floating point unit CPACR
-            pub const FPU_CPACR = @as(*volatile types.FPU_CPACR, @ptrFromInt(0xe000ed88));
-            ///  Memory protection unit
-            pub const MPU = @as(*volatile types.MPU, @ptrFromInt(0xe000ed90));
-            ///  Nested vectored interrupt controller
-            pub const NVIC_STIR = @as(*volatile types.NVIC_STIR, @ptrFromInt(0xe000ef00));
-            ///  Floting point unit
-            pub const FPU = @as(*volatile types.FPU, @ptrFromInt(0xe000ef34));
-            ///  Debug support
-            pub const DBG = @as(*volatile types.DBG, @ptrFromInt(0xe0042000));
-        };
-    };
-};
-
-pub const types = struct {
-    ///  Random number generator
-    pub const RNG = extern struct {
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Random number generator enable
-            RNGEN: u1,
-            ///  Interrupt enable
-            IE: u1,
-            padding: u28,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Data ready
-            DRDY: u1,
-            ///  Clock error current status
-            CECS: u1,
-            ///  Seed error current status
-            SECS: u1,
-            reserved5: u2,
-            ///  Clock error interrupt status
-            CEIS: u1,
-            ///  Seed error interrupt status
-            SEIS: u1,
-            padding: u25,
-        }),
-        ///  data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Random data
-            RNDATA: u32,
-        }),
-    };
-
-    ///  Digital camera interface
-    pub const DCMI = extern struct {
-        ///  control register 1
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Capture enable
-            CAPTURE: u1,
-            ///  Capture mode
-            CM: u1,
-            ///  Crop feature
-            CROP: u1,
-            ///  JPEG format
-            JPEG: u1,
-            ///  Embedded synchronization select
-            ESS: u1,
-            ///  Pixel clock polarity
-            PCKPOL: u1,
-            ///  Horizontal synchronization polarity
-            HSPOL: u1,
-            ///  Vertical synchronization polarity
-            VSPOL: u1,
-            ///  Frame capture rate control
-            FCRC: u2,
-            ///  Extended data mode
-            EDM: u2,
-            reserved14: u2,
-            ///  DCMI enable
-            ENABLE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  HSYNC
-            HSYNC: u1,
-            ///  VSYNC
-            VSYNC: u1,
-            ///  FIFO not empty
-            FNE: u1,
-            padding: u29,
-        }),
-        ///  raw interrupt status register
-        RIS: mmio.Mmio(packed struct(u32) {
-            ///  Capture complete raw interrupt status
-            FRAME_RIS: u1,
-            ///  Overrun raw interrupt status
-            OVR_RIS: u1,
-            ///  Synchronization error raw interrupt status
-            ERR_RIS: u1,
-            ///  VSYNC raw interrupt status
-            VSYNC_RIS: u1,
-            ///  Line raw interrupt status
-            LINE_RIS: u1,
-            padding: u27,
-        }),
-        ///  interrupt enable register
-        IER: mmio.Mmio(packed struct(u32) {
-            ///  Capture complete interrupt enable
-            FRAME_IE: u1,
-            ///  Overrun interrupt enable
-            OVR_IE: u1,
-            ///  Synchronization error interrupt enable
-            ERR_IE: u1,
-            ///  VSYNC interrupt enable
-            VSYNC_IE: u1,
-            ///  Line interrupt enable
-            LINE_IE: u1,
-            padding: u27,
-        }),
-        ///  masked interrupt status register
-        MIS: mmio.Mmio(packed struct(u32) {
-            ///  Capture complete masked interrupt status
-            FRAME_MIS: u1,
-            ///  Overrun masked interrupt status
-            OVR_MIS: u1,
-            ///  Synchronization error masked interrupt status
-            ERR_MIS: u1,
-            ///  VSYNC masked interrupt status
-            VSYNC_MIS: u1,
-            ///  Line masked interrupt status
-            LINE_MIS: u1,
-            padding: u27,
-        }),
-        ///  interrupt clear register
-        ICR: mmio.Mmio(packed struct(u32) {
-            ///  Capture complete interrupt status clear
-            FRAME_ISC: u1,
-            ///  Overrun interrupt status clear
-            OVR_ISC: u1,
-            ///  Synchronization error interrupt status clear
-            ERR_ISC: u1,
-            ///  Vertical synch interrupt status clear
-            VSYNC_ISC: u1,
-            ///  line interrupt status clear
-            LINE_ISC: u1,
-            padding: u27,
-        }),
-        ///  embedded synchronization code register
-        ESCR: mmio.Mmio(packed struct(u32) {
-            ///  Frame start delimiter code
-            FSC: u8,
-            ///  Line start delimiter code
-            LSC: u8,
-            ///  Line end delimiter code
-            LEC: u8,
-            ///  Frame end delimiter code
-            FEC: u8,
-        }),
-        ///  embedded synchronization unmask register
-        ESUR: mmio.Mmio(packed struct(u32) {
-            ///  Frame start delimiter unmask
-            FSU: u8,
-            ///  Line start delimiter unmask
-            LSU: u8,
-            ///  Line end delimiter unmask
-            LEU: u8,
-            ///  Frame end delimiter unmask
-            FEU: u8,
-        }),
-        ///  crop window start
-        CWSTRT: mmio.Mmio(packed struct(u32) {
-            ///  Horizontal offset count
-            HOFFCNT: u14,
-            reserved16: u2,
-            ///  Vertical start line count
-            VST: u13,
-            padding: u3,
-        }),
-        ///  crop window size
-        CWSIZE: mmio.Mmio(packed struct(u32) {
-            ///  Capture count
-            CAPCNT: u14,
-            reserved16: u2,
-            ///  Vertical line count
-            VLINE: u14,
-            padding: u2,
-        }),
-        ///  data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data byte 0
-            Byte0: u8,
-            ///  Data byte 1
-            Byte1: u8,
-            ///  Data byte 2
-            Byte2: u8,
-            ///  Data byte 3
-            Byte3: u8,
-        }),
-    };
-
-    ///  Flexible static memory controller
-    pub const FSMC = extern struct {
-        ///  SRAM/NOR-Flash chip-select control register 1
-        BCR1: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            reserved11: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 1
-        BTR1: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 2
-        BCR2: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 2
-        BTR2: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 3
-        BCR3: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 3
-        BTR3: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 4
-        BCR4: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 4
-        BTR4: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved96: [64]u8,
-        ///  PC Card/NAND Flash control register 2
-        PCR2: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 2
-        SR2: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 2
-        PMEM2: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 2
-        PATT2: mmio.Mmio(packed struct(u32) {
-            ///  ATTSETx
-            ATTSETx: u8,
-            ///  ATTWAITx
-            ATTWAITx: u8,
-            ///  ATTHOLDx
-            ATTHOLDx: u8,
-            ///  ATTHIZx
-            ATTHIZx: u8,
-        }),
-        reserved116: [4]u8,
-        ///  ECC result register 2
-        ECCR2: mmio.Mmio(packed struct(u32) {
-            ///  ECCx
-            ECCx: u32,
-        }),
-        reserved128: [8]u8,
-        ///  PC Card/NAND Flash control register 3
-        PCR3: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 3
-        SR3: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 3
-        PMEM3: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 3
-        PATT3: mmio.Mmio(packed struct(u32) {
-            ///  ATTSETx
-            ATTSETx: u8,
-            ///  ATTWAITx
-            ATTWAITx: u8,
-            ///  ATTHOLDx
-            ATTHOLDx: u8,
-            ///  ATTHIZx
-            ATTHIZx: u8,
-        }),
-        reserved148: [4]u8,
-        ///  ECC result register 3
-        ECCR3: mmio.Mmio(packed struct(u32) {
-            ///  ECCx
-            ECCx: u32,
-        }),
-        reserved160: [8]u8,
-        ///  PC Card/NAND Flash control register 4
-        PCR4: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 4
-        SR4: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 4
-        PMEM4: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 4
-        PATT4: mmio.Mmio(packed struct(u32) {
-            ///  ATTSETx
-            ATTSETx: u8,
-            ///  ATTWAITx
-            ATTWAITx: u8,
-            ///  ATTHOLDx
-            ATTHOLDx: u8,
-            ///  ATTHIZx
-            ATTHIZx: u8,
-        }),
-        ///  I/O space timing register 4
-        PIO4: mmio.Mmio(packed struct(u32) {
-            ///  IOSETx
-            IOSETx: u8,
-            ///  IOWAITx
-            IOWAITx: u8,
-            ///  IOHOLDx
-            IOHOLDx: u8,
-            ///  IOHIZx
-            IOHIZx: u8,
-        }),
-        reserved260: [80]u8,
-        ///  SRAM/NOR-Flash write timing registers 1
-        BWTR1: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            reserved20: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved268: [4]u8,
-        ///  SRAM/NOR-Flash write timing registers 2
-        BWTR2: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            reserved20: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved276: [4]u8,
-        ///  SRAM/NOR-Flash write timing registers 3
-        BWTR3: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            reserved20: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved284: [4]u8,
-        ///  SRAM/NOR-Flash write timing registers 4
-        BWTR4: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            reserved20: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-    };
-
-    ///  Debug support
-    pub const DBG = extern struct {
-        ///  IDCODE
-        DBGMCU_IDCODE: mmio.Mmio(packed struct(u32) {
-            ///  DEV_ID
-            DEV_ID: u12,
-            reserved16: u4,
-            ///  REV_ID
-            REV_ID: u16,
-        }),
-        ///  Control Register
-        DBGMCU_CR: mmio.Mmio(packed struct(u32) {
-            ///  DBG_SLEEP
-            DBG_SLEEP: u1,
-            ///  DBG_STOP
-            DBG_STOP: u1,
-            ///  DBG_STANDBY
-            DBG_STANDBY: u1,
-            reserved5: u2,
-            ///  TRACE_IOEN
-            TRACE_IOEN: u1,
-            ///  TRACE_MODE
-            TRACE_MODE: u2,
-            reserved16: u8,
-            ///  DBG_I2C2_SMBUS_TIMEOUT
-            DBG_I2C2_SMBUS_TIMEOUT: u1,
-            ///  DBG_TIM8_STOP
-            DBG_TIM8_STOP: u1,
-            ///  DBG_TIM5_STOP
-            DBG_TIM5_STOP: u1,
-            ///  DBG_TIM6_STOP
-            DBG_TIM6_STOP: u1,
-            ///  DBG_TIM7_STOP
-            DBG_TIM7_STOP: u1,
-            padding: u11,
-        }),
-        ///  Debug MCU APB1 Freeze registe
-        DBGMCU_APB1_FZ: mmio.Mmio(packed struct(u32) {
-            ///  DBG_TIM2_STOP
-            DBG_TIM2_STOP: u1,
-            ///  DBG_TIM3 _STOP
-            DBG_TIM3_STOP: u1,
-            ///  DBG_TIM4_STOP
-            DBG_TIM4_STOP: u1,
-            ///  DBG_TIM5_STOP
-            DBG_TIM5_STOP: u1,
-            ///  DBG_TIM6_STOP
-            DBG_TIM6_STOP: u1,
-            ///  DBG_TIM7_STOP
-            DBG_TIM7_STOP: u1,
-            ///  DBG_TIM12_STOP
-            DBG_TIM12_STOP: u1,
-            ///  DBG_TIM13_STOP
-            DBG_TIM13_STOP: u1,
-            ///  DBG_TIM14_STOP
-            DBG_TIM14_STOP: u1,
-            reserved11: u2,
-            ///  DBG_WWDG_STOP
-            DBG_WWDG_STOP: u1,
-            ///  DBG_IWDEG_STOP
-            DBG_IWDEG_STOP: u1,
-            reserved21: u8,
-            ///  DBG_J2C1_SMBUS_TIMEOUT
-            DBG_J2C1_SMBUS_TIMEOUT: u1,
-            ///  DBG_J2C2_SMBUS_TIMEOUT
-            DBG_J2C2_SMBUS_TIMEOUT: u1,
-            ///  DBG_J2C3SMBUS_TIMEOUT
-            DBG_J2C3SMBUS_TIMEOUT: u1,
-            reserved25: u1,
-            ///  DBG_CAN1_STOP
-            DBG_CAN1_STOP: u1,
-            ///  DBG_CAN2_STOP
-            DBG_CAN2_STOP: u1,
-            padding: u5,
-        }),
-        ///  Debug MCU APB2 Freeze registe
-        DBGMCU_APB2_FZ: mmio.Mmio(packed struct(u32) {
-            ///  TIM1 counter stopped when core is halted
-            DBG_TIM1_STOP: u1,
-            ///  TIM8 counter stopped when core is halted
-            DBG_TIM8_STOP: u1,
-            reserved16: u14,
-            ///  TIM9 counter stopped when core is halted
-            DBG_TIM9_STOP: u1,
-            ///  TIM10 counter stopped when core is halted
-            DBG_TIM10_STOP: u1,
-            ///  TIM11 counter stopped when core is halted
-            DBG_TIM11_STOP: u1,
-            padding: u13,
-        }),
-    };
-
-    ///  DMA controller
-    pub const DMA2 = extern struct {
-        ///  low interrupt status register
-        LISR: mmio.Mmio(packed struct(u32) {
-            ///  Stream x FIFO error interrupt flag (x=3..0)
-            FEIF0: u1,
-            reserved2: u1,
-            ///  Stream x direct mode error interrupt flag (x=3..0)
-            DMEIF0: u1,
-            ///  Stream x transfer error interrupt flag (x=3..0)
-            TEIF0: u1,
-            ///  Stream x half transfer interrupt flag (x=3..0)
-            HTIF0: u1,
-            ///  Stream x transfer complete interrupt flag (x = 3..0)
-            TCIF0: u1,
-            ///  Stream x FIFO error interrupt flag (x=3..0)
-            FEIF1: u1,
-            reserved8: u1,
-            ///  Stream x direct mode error interrupt flag (x=3..0)
-            DMEIF1: u1,
-            ///  Stream x transfer error interrupt flag (x=3..0)
-            TEIF1: u1,
-            ///  Stream x half transfer interrupt flag (x=3..0)
-            HTIF1: u1,
-            ///  Stream x transfer complete interrupt flag (x = 3..0)
-            TCIF1: u1,
-            reserved16: u4,
-            ///  Stream x FIFO error interrupt flag (x=3..0)
-            FEIF2: u1,
-            reserved18: u1,
-            ///  Stream x direct mode error interrupt flag (x=3..0)
-            DMEIF2: u1,
-            ///  Stream x transfer error interrupt flag (x=3..0)
-            TEIF2: u1,
-            ///  Stream x half transfer interrupt flag (x=3..0)
-            HTIF2: u1,
-            ///  Stream x transfer complete interrupt flag (x = 3..0)
-            TCIF2: u1,
-            ///  Stream x FIFO error interrupt flag (x=3..0)
-            FEIF3: u1,
-            reserved24: u1,
-            ///  Stream x direct mode error interrupt flag (x=3..0)
-            DMEIF3: u1,
-            ///  Stream x transfer error interrupt flag (x=3..0)
-            TEIF3: u1,
-            ///  Stream x half transfer interrupt flag (x=3..0)
-            HTIF3: u1,
-            ///  Stream x transfer complete interrupt flag (x = 3..0)
-            TCIF3: u1,
-            padding: u4,
-        }),
-        ///  high interrupt status register
-        HISR: mmio.Mmio(packed struct(u32) {
-            ///  Stream x FIFO error interrupt flag (x=7..4)
-            FEIF4: u1,
-            reserved2: u1,
-            ///  Stream x direct mode error interrupt flag (x=7..4)
-            DMEIF4: u1,
-            ///  Stream x transfer error interrupt flag (x=7..4)
-            TEIF4: u1,
-            ///  Stream x half transfer interrupt flag (x=7..4)
-            HTIF4: u1,
-            ///  Stream x transfer complete interrupt flag (x=7..4)
-            TCIF4: u1,
-            ///  Stream x FIFO error interrupt flag (x=7..4)
-            FEIF5: u1,
-            reserved8: u1,
-            ///  Stream x direct mode error interrupt flag (x=7..4)
-            DMEIF5: u1,
-            ///  Stream x transfer error interrupt flag (x=7..4)
-            TEIF5: u1,
-            ///  Stream x half transfer interrupt flag (x=7..4)
-            HTIF5: u1,
-            ///  Stream x transfer complete interrupt flag (x=7..4)
-            TCIF5: u1,
-            reserved16: u4,
-            ///  Stream x FIFO error interrupt flag (x=7..4)
-            FEIF6: u1,
-            reserved18: u1,
-            ///  Stream x direct mode error interrupt flag (x=7..4)
-            DMEIF6: u1,
-            ///  Stream x transfer error interrupt flag (x=7..4)
-            TEIF6: u1,
-            ///  Stream x half transfer interrupt flag (x=7..4)
-            HTIF6: u1,
-            ///  Stream x transfer complete interrupt flag (x=7..4)
-            TCIF6: u1,
-            ///  Stream x FIFO error interrupt flag (x=7..4)
-            FEIF7: u1,
-            reserved24: u1,
-            ///  Stream x direct mode error interrupt flag (x=7..4)
-            DMEIF7: u1,
-            ///  Stream x transfer error interrupt flag (x=7..4)
-            TEIF7: u1,
-            ///  Stream x half transfer interrupt flag (x=7..4)
-            HTIF7: u1,
-            ///  Stream x transfer complete interrupt flag (x=7..4)
-            TCIF7: u1,
-            padding: u4,
-        }),
-        ///  low interrupt flag clear register
-        LIFCR: mmio.Mmio(packed struct(u32) {
-            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
-            CFEIF0: u1,
-            reserved2: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
-            CDMEIF0: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 3..0)
-            CTEIF0: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 3..0)
-            CHTIF0: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
-            CTCIF0: u1,
-            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
-            CFEIF1: u1,
-            reserved8: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
-            CDMEIF1: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 3..0)
-            CTEIF1: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 3..0)
-            CHTIF1: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
-            CTCIF1: u1,
-            reserved16: u4,
-            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
-            CFEIF2: u1,
-            reserved18: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
-            CDMEIF2: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 3..0)
-            CTEIF2: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 3..0)
-            CHTIF2: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
-            CTCIF2: u1,
-            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
-            CFEIF3: u1,
-            reserved24: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
-            CDMEIF3: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 3..0)
-            CTEIF3: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 3..0)
-            CHTIF3: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
-            CTCIF3: u1,
-            padding: u4,
-        }),
-        ///  high interrupt flag clear register
-        HIFCR: mmio.Mmio(packed struct(u32) {
-            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
-            CFEIF4: u1,
-            reserved2: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
-            CDMEIF4: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 7..4)
-            CTEIF4: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 7..4)
-            CHTIF4: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
-            CTCIF4: u1,
-            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
-            CFEIF5: u1,
-            reserved8: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
-            CDMEIF5: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 7..4)
-            CTEIF5: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 7..4)
-            CHTIF5: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
-            CTCIF5: u1,
-            reserved16: u4,
-            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
-            CFEIF6: u1,
-            reserved18: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
-            CDMEIF6: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 7..4)
-            CTEIF6: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 7..4)
-            CHTIF6: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
-            CTCIF6: u1,
-            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
-            CFEIF7: u1,
-            reserved24: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
-            CDMEIF7: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 7..4)
-            CTEIF7: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 7..4)
-            CHTIF7: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
-            CTCIF7: u1,
-            padding: u4,
-        }),
-        ///  stream x configuration register
-        S0CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            reserved21: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S0NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S0PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S0M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S0M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S0FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S1CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S1NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S1PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S1M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S1M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S1FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S2CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S2NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S2PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S2M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S2M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S2FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S3CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S3NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S3PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S3M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S3M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S3FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S4CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S4NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S4PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S4M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S4M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S4FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S5CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S5NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S5PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S5M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S5M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S5FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S6CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S6NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S6PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S6M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S6M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S6FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S7CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S7NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S7PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S7M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S7M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S7FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-    };
-
-    ///  System control block ACTLR
-    pub const SCB_ACTRL = extern struct {
-        ///  Auxiliary control register
-        ACTRL: mmio.Mmio(packed struct(u32) {
-            ///  DISMCYCINT
-            DISMCYCINT: u1,
-            ///  DISDEFWBUF
-            DISDEFWBUF: u1,
-            ///  DISFOLD
-            DISFOLD: u1,
-            reserved8: u5,
-            ///  DISFPCA
-            DISFPCA: u1,
-            ///  DISOOFP
-            DISOOFP: u1,
-            padding: u22,
-        }),
-    };
-
-    ///  Reset and clock control
-    pub const RCC = extern struct {
-        ///  clock control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Internal high-speed clock enable
-            HSION: u1,
-            ///  Internal high-speed clock ready flag
-            HSIRDY: u1,
-            reserved3: u1,
-            ///  Internal high-speed clock trimming
-            HSITRIM: u5,
-            ///  Internal high-speed clock calibration
-            HSICAL: u8,
-            ///  HSE clock enable
-            HSEON: u1,
-            ///  HSE clock ready flag
-            HSERDY: u1,
-            ///  HSE clock bypass
-            HSEBYP: u1,
-            ///  Clock security system enable
-            CSSON: u1,
-            reserved24: u4,
-            ///  Main PLL (PLL) enable
-            PLLON: u1,
-            ///  Main PLL (PLL) clock ready flag
-            PLLRDY: u1,
-            ///  PLLI2S enable
-            PLLI2SON: u1,
-            ///  PLLI2S clock ready flag
-            PLLI2SRDY: u1,
-            padding: u4,
-        }),
-        ///  PLL configuration register
-        PLLCFGR: mmio.Mmio(packed struct(u32) {
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM0: u1,
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM1: u1,
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM2: u1,
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM3: u1,
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM4: u1,
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM5: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN0: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN1: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN2: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN3: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN4: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN5: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN6: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN7: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN8: u1,
-            reserved16: u1,
-            ///  Main PLL (PLL) division factor for main system clock
-            PLLP0: u1,
-            ///  Main PLL (PLL) division factor for main system clock
-            PLLP1: u1,
-            reserved22: u4,
-            ///  Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
-            PLLSRC: u1,
-            reserved24: u1,
-            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
-            PLLQ0: u1,
-            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
-            PLLQ1: u1,
-            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
-            PLLQ2: u1,
-            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
-            PLLQ3: u1,
-            padding: u4,
-        }),
-        ///  clock configuration register
-        CFGR: mmio.Mmio(packed struct(u32) {
-            ///  System clock switch
-            SW0: u1,
-            ///  System clock switch
-            SW1: u1,
-            ///  System clock switch status
-            SWS0: u1,
-            ///  System clock switch status
-            SWS1: u1,
-            ///  AHB prescaler
-            HPRE: u4,
-            reserved10: u2,
-            ///  APB Low speed prescaler (APB1)
-            PPRE1: u3,
-            ///  APB high-speed prescaler (APB2)
-            PPRE2: u3,
-            ///  HSE division factor for RTC clock
-            RTCPRE: u5,
-            ///  Microcontroller clock output 1
-            MCO1: u2,
-            ///  I2S clock selection
-            I2SSRC: u1,
-            ///  MCO1 prescaler
-            MCO1PRE: u3,
-            ///  MCO2 prescaler
-            MCO2PRE: u3,
-            ///  Microcontroller clock output 2
-            MCO2: u2,
-        }),
-        ///  clock interrupt register
-        CIR: mmio.Mmio(packed struct(u32) {
-            ///  LSI ready interrupt flag
-            LSIRDYF: u1,
-            ///  LSE ready interrupt flag
-            LSERDYF: u1,
-            ///  HSI ready interrupt flag
-            HSIRDYF: u1,
-            ///  HSE ready interrupt flag
-            HSERDYF: u1,
-            ///  Main PLL (PLL) ready interrupt flag
-            PLLRDYF: u1,
-            ///  PLLI2S ready interrupt flag
-            PLLI2SRDYF: u1,
-            reserved7: u1,
-            ///  Clock security system interrupt flag
-            CSSF: u1,
-            ///  LSI ready interrupt enable
-            LSIRDYIE: u1,
-            ///  LSE ready interrupt enable
-            LSERDYIE: u1,
-            ///  HSI ready interrupt enable
-            HSIRDYIE: u1,
-            ///  HSE ready interrupt enable
-            HSERDYIE: u1,
-            ///  Main PLL (PLL) ready interrupt enable
-            PLLRDYIE: u1,
-            ///  PLLI2S ready interrupt enable
-            PLLI2SRDYIE: u1,
-            reserved16: u2,
-            ///  LSI ready interrupt clear
-            LSIRDYC: u1,
-            ///  LSE ready interrupt clear
-            LSERDYC: u1,
-            ///  HSI ready interrupt clear
-            HSIRDYC: u1,
-            ///  HSE ready interrupt clear
-            HSERDYC: u1,
-            ///  Main PLL(PLL) ready interrupt clear
-            PLLRDYC: u1,
-            ///  PLLI2S ready interrupt clear
-            PLLI2SRDYC: u1,
-            reserved23: u1,
-            ///  Clock security system interrupt clear
-            CSSC: u1,
-            padding: u8,
-        }),
-        ///  AHB1 peripheral reset register
-        AHB1RSTR: mmio.Mmio(packed struct(u32) {
-            ///  IO port A reset
-            GPIOARST: u1,
-            ///  IO port B reset
-            GPIOBRST: u1,
-            ///  IO port C reset
-            GPIOCRST: u1,
-            ///  IO port D reset
-            GPIODRST: u1,
-            ///  IO port E reset
-            GPIOERST: u1,
-            ///  IO port F reset
-            GPIOFRST: u1,
-            ///  IO port G reset
-            GPIOGRST: u1,
-            ///  IO port H reset
-            GPIOHRST: u1,
-            ///  IO port I reset
-            GPIOIRST: u1,
-            reserved12: u3,
-            ///  CRC reset
-            CRCRST: u1,
-            reserved21: u8,
-            ///  DMA2 reset
-            DMA1RST: u1,
-            ///  DMA2 reset
-            DMA2RST: u1,
-            reserved25: u2,
-            ///  Ethernet MAC reset
-            ETHMACRST: u1,
-            reserved29: u3,
-            ///  USB OTG HS module reset
-            OTGHSRST: u1,
-            padding: u2,
-        }),
-        ///  AHB2 peripheral reset register
-        AHB2RSTR: mmio.Mmio(packed struct(u32) {
-            ///  Camera interface reset
-            DCMIRST: u1,
-            reserved6: u5,
-            ///  Random number generator module reset
-            RNGRST: u1,
-            ///  USB OTG FS module reset
-            OTGFSRST: u1,
-            padding: u24,
-        }),
-        ///  AHB3 peripheral reset register
-        AHB3RSTR: mmio.Mmio(packed struct(u32) {
-            ///  Flexible static memory controller module reset
-            FSMCRST: u1,
-            padding: u31,
-        }),
-        reserved32: [4]u8,
-        ///  APB1 peripheral reset register
-        APB1RSTR: mmio.Mmio(packed struct(u32) {
-            ///  TIM2 reset
-            TIM2RST: u1,
-            ///  TIM3 reset
-            TIM3RST: u1,
-            ///  TIM4 reset
-            TIM4RST: u1,
-            ///  TIM5 reset
-            TIM5RST: u1,
-            ///  TIM6 reset
-            TIM6RST: u1,
-            ///  TIM7 reset
-            TIM7RST: u1,
-            ///  TIM12 reset
-            TIM12RST: u1,
-            ///  TIM13 reset
-            TIM13RST: u1,
-            ///  TIM14 reset
-            TIM14RST: u1,
-            reserved11: u2,
-            ///  Window watchdog reset
-            WWDGRST: u1,
-            reserved14: u2,
-            ///  SPI 2 reset
-            SPI2RST: u1,
-            ///  SPI 3 reset
-            SPI3RST: u1,
-            reserved17: u1,
-            ///  USART 2 reset
-            UART2RST: u1,
-            ///  USART 3 reset
-            UART3RST: u1,
-            ///  USART 4 reset
-            UART4RST: u1,
-            ///  USART 5 reset
-            UART5RST: u1,
-            ///  I2C 1 reset
-            I2C1RST: u1,
-            ///  I2C 2 reset
-            I2C2RST: u1,
-            ///  I2C3 reset
-            I2C3RST: u1,
-            reserved25: u1,
-            ///  CAN1 reset
-            CAN1RST: u1,
-            ///  CAN2 reset
-            CAN2RST: u1,
-            reserved28: u1,
-            ///  Power interface reset
-            PWRRST: u1,
-            ///  DAC reset
-            DACRST: u1,
-            padding: u2,
-        }),
-        ///  APB2 peripheral reset register
-        APB2RSTR: mmio.Mmio(packed struct(u32) {
-            ///  TIM1 reset
-            TIM1RST: u1,
-            ///  TIM8 reset
-            TIM8RST: u1,
-            reserved4: u2,
-            ///  USART1 reset
-            USART1RST: u1,
-            ///  USART6 reset
-            USART6RST: u1,
-            reserved8: u2,
-            ///  ADC interface reset (common to all ADCs)
-            ADCRST: u1,
-            reserved11: u2,
-            ///  SDIO reset
-            SDIORST: u1,
-            ///  SPI 1 reset
-            SPI1RST: u1,
-            reserved14: u1,
-            ///  System configuration controller reset
-            SYSCFGRST: u1,
-            reserved16: u1,
-            ///  TIM9 reset
-            TIM9RST: u1,
-            ///  TIM10 reset
-            TIM10RST: u1,
-            ///  TIM11 reset
-            TIM11RST: u1,
-            padding: u13,
-        }),
-        reserved48: [8]u8,
-        ///  AHB1 peripheral clock register
-        AHB1ENR: mmio.Mmio(packed struct(u32) {
-            ///  IO port A clock enable
-            GPIOAEN: u1,
-            ///  IO port B clock enable
-            GPIOBEN: u1,
-            ///  IO port C clock enable
-            GPIOCEN: u1,
-            ///  IO port D clock enable
-            GPIODEN: u1,
-            ///  IO port E clock enable
-            GPIOEEN: u1,
-            ///  IO port F clock enable
-            GPIOFEN: u1,
-            ///  IO port G clock enable
-            GPIOGEN: u1,
-            ///  IO port H clock enable
-            GPIOHEN: u1,
-            ///  IO port I clock enable
-            GPIOIEN: u1,
-            reserved12: u3,
-            ///  CRC clock enable
-            CRCEN: u1,
-            reserved18: u5,
-            ///  Backup SRAM interface clock enable
-            BKPSRAMEN: u1,
-            reserved21: u2,
-            ///  DMA1 clock enable
-            DMA1EN: u1,
-            ///  DMA2 clock enable
-            DMA2EN: u1,
-            reserved25: u2,
-            ///  Ethernet MAC clock enable
-            ETHMACEN: u1,
-            ///  Ethernet Transmission clock enable
-            ETHMACTXEN: u1,
-            ///  Ethernet Reception clock enable
-            ETHMACRXEN: u1,
-            ///  Ethernet PTP clock enable
-            ETHMACPTPEN: u1,
-            ///  USB OTG HS clock enable
-            OTGHSEN: u1,
-            ///  USB OTG HSULPI clock enable
-            OTGHSULPIEN: u1,
-            padding: u1,
-        }),
-        ///  AHB2 peripheral clock enable register
-        AHB2ENR: mmio.Mmio(packed struct(u32) {
-            ///  Camera interface enable
-            DCMIEN: u1,
-            reserved6: u5,
-            ///  Random number generator clock enable
-            RNGEN: u1,
-            ///  USB OTG FS clock enable
-            OTGFSEN: u1,
-            padding: u24,
-        }),
-        ///  AHB3 peripheral clock enable register
-        AHB3ENR: mmio.Mmio(packed struct(u32) {
-            ///  Flexible static memory controller module clock enable
-            FSMCEN: u1,
-            padding: u31,
-        }),
-        reserved64: [4]u8,
-        ///  APB1 peripheral clock enable register
-        APB1ENR: mmio.Mmio(packed struct(u32) {
-            ///  TIM2 clock enable
-            TIM2EN: u1,
-            ///  TIM3 clock enable
-            TIM3EN: u1,
-            ///  TIM4 clock enable
-            TIM4EN: u1,
-            ///  TIM5 clock enable
-            TIM5EN: u1,
-            ///  TIM6 clock enable
-            TIM6EN: u1,
-            ///  TIM7 clock enable
-            TIM7EN: u1,
-            ///  TIM12 clock enable
-            TIM12EN: u1,
-            ///  TIM13 clock enable
-            TIM13EN: u1,
-            ///  TIM14 clock enable
-            TIM14EN: u1,
-            reserved11: u2,
-            ///  Window watchdog clock enable
-            WWDGEN: u1,
-            reserved14: u2,
-            ///  SPI2 clock enable
-            SPI2EN: u1,
-            ///  SPI3 clock enable
-            SPI3EN: u1,
-            reserved17: u1,
-            ///  USART 2 clock enable
-            USART2EN: u1,
-            ///  USART3 clock enable
-            USART3EN: u1,
-            ///  UART4 clock enable
-            UART4EN: u1,
-            ///  UART5 clock enable
-            UART5EN: u1,
-            ///  I2C1 clock enable
-            I2C1EN: u1,
-            ///  I2C2 clock enable
-            I2C2EN: u1,
-            ///  I2C3 clock enable
-            I2C3EN: u1,
-            reserved25: u1,
-            ///  CAN 1 clock enable
-            CAN1EN: u1,
-            ///  CAN 2 clock enable
-            CAN2EN: u1,
-            reserved28: u1,
-            ///  Power interface clock enable
-            PWREN: u1,
-            ///  DAC interface clock enable
-            DACEN: u1,
-            padding: u2,
-        }),
-        ///  APB2 peripheral clock enable register
-        APB2ENR: mmio.Mmio(packed struct(u32) {
-            ///  TIM1 clock enable
-            TIM1EN: u1,
-            ///  TIM8 clock enable
-            TIM8EN: u1,
-            reserved4: u2,
-            ///  USART1 clock enable
-            USART1EN: u1,
-            ///  USART6 clock enable
-            USART6EN: u1,
-            reserved8: u2,
-            ///  ADC1 clock enable
-            ADC1EN: u1,
-            ///  ADC2 clock enable
-            ADC2EN: u1,
-            ///  ADC3 clock enable
-            ADC3EN: u1,
-            ///  SDIO clock enable
-            SDIOEN: u1,
-            ///  SPI1 clock enable
-            SPI1EN: u1,
-            reserved14: u1,
-            ///  System configuration controller clock enable
-            SYSCFGEN: u1,
-            reserved16: u1,
-            ///  TIM9 clock enable
-            TIM9EN: u1,
-            ///  TIM10 clock enable
-            TIM10EN: u1,
-            ///  TIM11 clock enable
-            TIM11EN: u1,
-            padding: u13,
-        }),
-        reserved80: [8]u8,
-        ///  AHB1 peripheral clock enable in low power mode register
-        AHB1LPENR: mmio.Mmio(packed struct(u32) {
-            ///  IO port A clock enable during sleep mode
-            GPIOALPEN: u1,
-            ///  IO port B clock enable during Sleep mode
-            GPIOBLPEN: u1,
-            ///  IO port C clock enable during Sleep mode
-            GPIOCLPEN: u1,
-            ///  IO port D clock enable during Sleep mode
-            GPIODLPEN: u1,
-            ///  IO port E clock enable during Sleep mode
-            GPIOELPEN: u1,
-            ///  IO port F clock enable during Sleep mode
-            GPIOFLPEN: u1,
-            ///  IO port G clock enable during Sleep mode
-            GPIOGLPEN: u1,
-            ///  IO port H clock enable during Sleep mode
-            GPIOHLPEN: u1,
-            ///  IO port I clock enable during Sleep mode
-            GPIOILPEN: u1,
-            reserved12: u3,
-            ///  CRC clock enable during Sleep mode
-            CRCLPEN: u1,
-            reserved15: u2,
-            ///  Flash interface clock enable during Sleep mode
-            FLITFLPEN: u1,
-            ///  SRAM 1interface clock enable during Sleep mode
-            SRAM1LPEN: u1,
-            ///  SRAM 2 interface clock enable during Sleep mode
-            SRAM2LPEN: u1,
-            ///  Backup SRAM interface clock enable during Sleep mode
-            BKPSRAMLPEN: u1,
-            reserved21: u2,
-            ///  DMA1 clock enable during Sleep mode
-            DMA1LPEN: u1,
-            ///  DMA2 clock enable during Sleep mode
-            DMA2LPEN: u1,
-            reserved25: u2,
-            ///  Ethernet MAC clock enable during Sleep mode
-            ETHMACLPEN: u1,
-            ///  Ethernet transmission clock enable during Sleep mode
-            ETHMACTXLPEN: u1,
-            ///  Ethernet reception clock enable during Sleep mode
-            ETHMACRXLPEN: u1,
-            ///  Ethernet PTP clock enable during Sleep mode
-            ETHMACPTPLPEN: u1,
-            ///  USB OTG HS clock enable during Sleep mode
-            OTGHSLPEN: u1,
-            ///  USB OTG HS ULPI clock enable during Sleep mode
-            OTGHSULPILPEN: u1,
-            padding: u1,
-        }),
-        ///  AHB2 peripheral clock enable in low power mode register
-        AHB2LPENR: mmio.Mmio(packed struct(u32) {
-            ///  Camera interface enable during Sleep mode
-            DCMILPEN: u1,
-            reserved6: u5,
-            ///  Random number generator clock enable during Sleep mode
-            RNGLPEN: u1,
-            ///  USB OTG FS clock enable during Sleep mode
-            OTGFSLPEN: u1,
-            padding: u24,
-        }),
-        ///  AHB3 peripheral clock enable in low power mode register
-        AHB3LPENR: mmio.Mmio(packed struct(u32) {
-            ///  Flexible static memory controller module clock enable during Sleep mode
-            FSMCLPEN: u1,
-            padding: u31,
-        }),
-        reserved96: [4]u8,
-        ///  APB1 peripheral clock enable in low power mode register
-        APB1LPENR: mmio.Mmio(packed struct(u32) {
-            ///  TIM2 clock enable during Sleep mode
-            TIM2LPEN: u1,
-            ///  TIM3 clock enable during Sleep mode
-            TIM3LPEN: u1,
-            ///  TIM4 clock enable during Sleep mode
-            TIM4LPEN: u1,
-            ///  TIM5 clock enable during Sleep mode
-            TIM5LPEN: u1,
-            ///  TIM6 clock enable during Sleep mode
-            TIM6LPEN: u1,
-            ///  TIM7 clock enable during Sleep mode
-            TIM7LPEN: u1,
-            ///  TIM12 clock enable during Sleep mode
-            TIM12LPEN: u1,
-            ///  TIM13 clock enable during Sleep mode
-            TIM13LPEN: u1,
-            ///  TIM14 clock enable during Sleep mode
-            TIM14LPEN: u1,
-            reserved11: u2,
-            ///  Window watchdog clock enable during Sleep mode
-            WWDGLPEN: u1,
-            reserved14: u2,
-            ///  SPI2 clock enable during Sleep mode
-            SPI2LPEN: u1,
-            ///  SPI3 clock enable during Sleep mode
-            SPI3LPEN: u1,
-            reserved17: u1,
-            ///  USART2 clock enable during Sleep mode
-            USART2LPEN: u1,
-            ///  USART3 clock enable during Sleep mode
-            USART3LPEN: u1,
-            ///  UART4 clock enable during Sleep mode
-            UART4LPEN: u1,
-            ///  UART5 clock enable during Sleep mode
-            UART5LPEN: u1,
-            ///  I2C1 clock enable during Sleep mode
-            I2C1LPEN: u1,
-            ///  I2C2 clock enable during Sleep mode
-            I2C2LPEN: u1,
-            ///  I2C3 clock enable during Sleep mode
-            I2C3LPEN: u1,
-            reserved25: u1,
-            ///  CAN 1 clock enable during Sleep mode
-            CAN1LPEN: u1,
-            ///  CAN 2 clock enable during Sleep mode
-            CAN2LPEN: u1,
-            reserved28: u1,
-            ///  Power interface clock enable during Sleep mode
-            PWRLPEN: u1,
-            ///  DAC interface clock enable during Sleep mode
-            DACLPEN: u1,
-            padding: u2,
-        }),
-        ///  APB2 peripheral clock enabled in low power mode register
-        APB2LPENR: mmio.Mmio(packed struct(u32) {
-            ///  TIM1 clock enable during Sleep mode
-            TIM1LPEN: u1,
-            ///  TIM8 clock enable during Sleep mode
-            TIM8LPEN: u1,
-            reserved4: u2,
-            ///  USART1 clock enable during Sleep mode
-            USART1LPEN: u1,
-            ///  USART6 clock enable during Sleep mode
-            USART6LPEN: u1,
-            reserved8: u2,
-            ///  ADC1 clock enable during Sleep mode
-            ADC1LPEN: u1,
-            ///  ADC2 clock enable during Sleep mode
-            ADC2LPEN: u1,
-            ///  ADC 3 clock enable during Sleep mode
-            ADC3LPEN: u1,
-            ///  SDIO clock enable during Sleep mode
-            SDIOLPEN: u1,
-            ///  SPI 1 clock enable during Sleep mode
-            SPI1LPEN: u1,
-            reserved14: u1,
-            ///  System configuration controller clock enable during Sleep mode
-            SYSCFGLPEN: u1,
-            reserved16: u1,
-            ///  TIM9 clock enable during sleep mode
-            TIM9LPEN: u1,
-            ///  TIM10 clock enable during Sleep mode
-            TIM10LPEN: u1,
-            ///  TIM11 clock enable during Sleep mode
-            TIM11LPEN: u1,
-            padding: u13,
-        }),
-        reserved112: [8]u8,
-        ///  Backup domain control register
-        BDCR: mmio.Mmio(packed struct(u32) {
-            ///  External low-speed oscillator enable
-            LSEON: u1,
-            ///  External low-speed oscillator ready
-            LSERDY: u1,
-            ///  External low-speed oscillator bypass
-            LSEBYP: u1,
-            reserved8: u5,
-            ///  RTC clock source selection
-            RTCSEL0: u1,
-            ///  RTC clock source selection
-            RTCSEL1: u1,
-            reserved15: u5,
-            ///  RTC clock enable
-            RTCEN: u1,
-            ///  Backup domain software reset
-            BDRST: u1,
-            padding: u15,
-        }),
-        ///  clock control & status register
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  Internal low-speed oscillator enable
-            LSION: u1,
-            ///  Internal low-speed oscillator ready
-            LSIRDY: u1,
-            reserved24: u22,
-            ///  Remove reset flag
-            RMVF: u1,
-            ///  BOR reset flag
-            BORRSTF: u1,
-            ///  PIN reset flag
-            PADRSTF: u1,
-            ///  POR/PDR reset flag
-            PORRSTF: u1,
-            ///  Software reset flag
-            SFTRSTF: u1,
-            ///  Independent watchdog reset flag
-            WDGRSTF: u1,
-            ///  Window watchdog reset flag
-            WWDGRSTF: u1,
-            ///  Low-power reset flag
-            LPWRRSTF: u1,
-        }),
-        reserved128: [8]u8,
-        ///  spread spectrum clock generation register
-        SSCGR: mmio.Mmio(packed struct(u32) {
-            ///  Modulation period
-            MODPER: u13,
-            ///  Incrementation step
-            INCSTEP: u15,
-            reserved30: u2,
-            ///  Spread Select
-            SPREADSEL: u1,
-            ///  Spread spectrum modulation enable
-            SSCGEN: u1,
-        }),
-        ///  PLLI2S configuration register
-        PLLI2SCFGR: mmio.Mmio(packed struct(u32) {
-            reserved6: u6,
-            ///  PLLI2S multiplication factor for VCO
-            PLLI2SNx: u9,
-            reserved28: u13,
-            ///  PLLI2S division factor for I2S clocks
-            PLLI2SRx: u3,
-            padding: u1,
-        }),
-    };
-
-    ///  General-purpose I/Os
-    pub const GPIOI = extern struct {
-        ///  GPIO port mode register
-        MODER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            MODER0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER15: u2,
-        }),
-        ///  GPIO port output type register
-        OTYPER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OT0: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT1: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT2: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT3: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT4: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT5: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT6: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT7: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT8: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT9: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT10: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT11: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT12: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT13: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT14: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output speed register
-        OSPEEDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR15: u2,
-        }),
-        ///  GPIO port pull-up/pull-down register
-        PUPDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR15: u2,
-        }),
-        ///  GPIO port input data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Port input data (y = 0..15)
-            IDR0: u1,
-            ///  Port input data (y = 0..15)
-            IDR1: u1,
-            ///  Port input data (y = 0..15)
-            IDR2: u1,
-            ///  Port input data (y = 0..15)
-            IDR3: u1,
-            ///  Port input data (y = 0..15)
-            IDR4: u1,
-            ///  Port input data (y = 0..15)
-            IDR5: u1,
-            ///  Port input data (y = 0..15)
-            IDR6: u1,
-            ///  Port input data (y = 0..15)
-            IDR7: u1,
-            ///  Port input data (y = 0..15)
-            IDR8: u1,
-            ///  Port input data (y = 0..15)
-            IDR9: u1,
-            ///  Port input data (y = 0..15)
-            IDR10: u1,
-            ///  Port input data (y = 0..15)
-            IDR11: u1,
-            ///  Port input data (y = 0..15)
-            IDR12: u1,
-            ///  Port input data (y = 0..15)
-            IDR13: u1,
-            ///  Port input data (y = 0..15)
-            IDR14: u1,
-            ///  Port input data (y = 0..15)
-            IDR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output data register
-        ODR: mmio.Mmio(packed struct(u32) {
-            ///  Port output data (y = 0..15)
-            ODR0: u1,
-            ///  Port output data (y = 0..15)
-            ODR1: u1,
-            ///  Port output data (y = 0..15)
-            ODR2: u1,
-            ///  Port output data (y = 0..15)
-            ODR3: u1,
-            ///  Port output data (y = 0..15)
-            ODR4: u1,
-            ///  Port output data (y = 0..15)
-            ODR5: u1,
-            ///  Port output data (y = 0..15)
-            ODR6: u1,
-            ///  Port output data (y = 0..15)
-            ODR7: u1,
-            ///  Port output data (y = 0..15)
-            ODR8: u1,
-            ///  Port output data (y = 0..15)
-            ODR9: u1,
-            ///  Port output data (y = 0..15)
-            ODR10: u1,
-            ///  Port output data (y = 0..15)
-            ODR11: u1,
-            ///  Port output data (y = 0..15)
-            ODR12: u1,
-            ///  Port output data (y = 0..15)
-            ODR13: u1,
-            ///  Port output data (y = 0..15)
-            ODR14: u1,
-            ///  Port output data (y = 0..15)
-            ODR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port bit set/reset register
-        BSRR: mmio.Mmio(packed struct(u32) {
-            ///  Port x set bit y (y= 0..15)
-            BS0: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS1: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS2: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS3: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS4: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS5: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS6: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS7: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS8: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS9: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS10: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS11: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS12: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS13: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS14: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS15: u1,
-            ///  Port x set bit y (y= 0..15)
-            BR0: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR1: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR2: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR3: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR4: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR5: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR6: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR7: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR8: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR9: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR10: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR11: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR12: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR13: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR14: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR15: u1,
-        }),
-        ///  GPIO port configuration lock register
-        LCKR: mmio.Mmio(packed struct(u32) {
-            ///  Port x lock bit y (y= 0..15)
-            LCK0: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK1: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK2: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK3: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK4: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK5: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK6: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK7: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK8: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK9: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK10: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK11: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK12: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK13: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK14: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK15: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCKK: u1,
-            padding: u15,
-        }),
-        ///  GPIO alternate function low register
-        AFRL: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL0: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL1: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL2: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL3: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL4: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL5: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL6: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL7: u4,
-        }),
-        ///  GPIO alternate function high register
-        AFRH: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH8: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH9: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH10: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH11: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH12: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH13: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH14: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH15: u4,
-        }),
-    };
-
-    ///  Floating point unit CPACR
-    pub const FPU_CPACR = extern struct {
-        ///  Coprocessor access control register
-        CPACR: mmio.Mmio(packed struct(u32) {
-            reserved20: u20,
-            ///  CP
-            CP: u4,
-            padding: u8,
-        }),
-    };
-
-    ///  Nested vectored interrupt controller
-    pub const NVIC_STIR = extern struct {
-        ///  Software trigger interrupt register
-        STIR: mmio.Mmio(packed struct(u32) {
-            ///  Software generated interrupt ID
-            INTID: u9,
-            padding: u23,
-        }),
-    };
-
-    ///  System control block
-    pub const SCB = extern struct {
-        ///  CPUID base register
-        CPUID: mmio.Mmio(packed struct(u32) {
-            ///  Revision number
-            Revision: u4,
-            ///  Part number of the processor
-            PartNo: u12,
-            ///  Reads as 0xF
-            Constant: u4,
-            ///  Variant number
-            Variant: u4,
-            ///  Implementer code
-            Implementer: u8,
-        }),
-        ///  Interrupt control and state register
-        ICSR: mmio.Mmio(packed struct(u32) {
-            ///  Active vector
-            VECTACTIVE: u9,
-            reserved11: u2,
-            ///  Return to base level
-            RETTOBASE: u1,
-            ///  Pending vector
-            VECTPENDING: u7,
-            reserved22: u3,
-            ///  Interrupt pending flag
-            ISRPENDING: u1,
-            reserved25: u2,
-            ///  SysTick exception clear-pending bit
-            PENDSTCLR: u1,
-            ///  SysTick exception set-pending bit
-            PENDSTSET: u1,
-            ///  PendSV clear-pending bit
-            PENDSVCLR: u1,
-            ///  PendSV set-pending bit
-            PENDSVSET: u1,
-            reserved31: u2,
-            ///  NMI set-pending bit.
-            NMIPENDSET: u1,
-        }),
-        ///  Vector table offset register
-        VTOR: mmio.Mmio(packed struct(u32) {
-            reserved9: u9,
-            ///  Vector table base offset field
-            TBLOFF: u21,
-            padding: u2,
-        }),
-        ///  Application interrupt and reset control register
-        AIRCR: mmio.Mmio(packed struct(u32) {
-            ///  VECTRESET
-            VECTRESET: u1,
-            ///  VECTCLRACTIVE
-            VECTCLRACTIVE: u1,
-            ///  SYSRESETREQ
-            SYSRESETREQ: u1,
-            reserved8: u5,
-            ///  PRIGROUP
-            PRIGROUP: u3,
-            reserved15: u4,
-            ///  ENDIANESS
-            ENDIANESS: u1,
-            ///  Register key
-            VECTKEYSTAT: u16,
-        }),
-        ///  System control register
-        SCR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  SLEEPONEXIT
-            SLEEPONEXIT: u1,
-            ///  SLEEPDEEP
-            SLEEPDEEP: u1,
-            reserved4: u1,
-            ///  Send Event on Pending bit
-            SEVEONPEND: u1,
-            padding: u27,
-        }),
-        ///  Configuration and control register
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Configures how the processor enters Thread mode
-            NONBASETHRDENA: u1,
-            ///  USERSETMPEND
-            USERSETMPEND: u1,
-            reserved3: u1,
-            ///  UNALIGN_ TRP
-            UNALIGN__TRP: u1,
-            ///  DIV_0_TRP
-            DIV_0_TRP: u1,
-            reserved8: u3,
-            ///  BFHFNMIGN
-            BFHFNMIGN: u1,
-            ///  STKALIGN
-            STKALIGN: u1,
-            padding: u22,
-        }),
-        ///  System handler priority registers
-        SHPR1: mmio.Mmio(packed struct(u32) {
-            ///  Priority of system handler 4
-            PRI_4: u8,
-            ///  Priority of system handler 5
-            PRI_5: u8,
-            ///  Priority of system handler 6
-            PRI_6: u8,
-            padding: u8,
-        }),
-        ///  System handler priority registers
-        SHPR2: mmio.Mmio(packed struct(u32) {
-            reserved24: u24,
-            ///  Priority of system handler 11
-            PRI_11: u8,
-        }),
-        ///  System handler priority registers
-        SHPR3: mmio.Mmio(packed struct(u32) {
-            reserved16: u16,
-            ///  Priority of system handler 14
-            PRI_14: u8,
-            ///  Priority of system handler 15
-            PRI_15: u8,
-        }),
-        ///  System handler control and state register
-        SHCRS: mmio.Mmio(packed struct(u32) {
-            ///  Memory management fault exception active bit
-            MEMFAULTACT: u1,
-            ///  Bus fault exception active bit
-            BUSFAULTACT: u1,
-            reserved3: u1,
-            ///  Usage fault exception active bit
-            USGFAULTACT: u1,
-            reserved7: u3,
-            ///  SVC call active bit
-            SVCALLACT: u1,
-            ///  Debug monitor active bit
-            MONITORACT: u1,
-            reserved10: u1,
-            ///  PendSV exception active bit
-            PENDSVACT: u1,
-            ///  SysTick exception active bit
-            SYSTICKACT: u1,
-            ///  Usage fault exception pending bit
-            USGFAULTPENDED: u1,
-            ///  Memory management fault exception pending bit
-            MEMFAULTPENDED: u1,
-            ///  Bus fault exception pending bit
-            BUSFAULTPENDED: u1,
-            ///  SVC call pending bit
-            SVCALLPENDED: u1,
-            ///  Memory management fault enable bit
-            MEMFAULTENA: u1,
-            ///  Bus fault enable bit
-            BUSFAULTENA: u1,
-            ///  Usage fault enable bit
-            USGFAULTENA: u1,
-            padding: u13,
-        }),
-        ///  Configurable fault status register
-        CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Instruction access violation flag
-            IACCVIOL: u1,
-            reserved3: u1,
-            ///  Memory manager fault on unstacking for a return from exception
-            MUNSTKERR: u1,
-            ///  Memory manager fault on stacking for exception entry.
-            MSTKERR: u1,
-            ///  MLSPERR
-            MLSPERR: u1,
-            reserved7: u1,
-            ///  Memory Management Fault Address Register (MMAR) valid flag
-            MMARVALID: u1,
-            ///  Instruction bus error
-            IBUSERR: u1,
-            ///  Precise data bus error
-            PRECISERR: u1,
-            ///  Imprecise data bus error
-            IMPRECISERR: u1,
-            ///  Bus fault on unstacking for a return from exception
-            UNSTKERR: u1,
-            ///  Bus fault on stacking for exception entry
-            STKERR: u1,
-            ///  Bus fault on floating-point lazy state preservation
-            LSPERR: u1,
-            reserved15: u1,
-            ///  Bus Fault Address Register (BFAR) valid flag
-            BFARVALID: u1,
-            ///  Undefined instruction usage fault
-            UNDEFINSTR: u1,
-            ///  Invalid state usage fault
-            INVSTATE: u1,
-            ///  Invalid PC load usage fault
-            INVPC: u1,
-            ///  No coprocessor usage fault.
-            NOCP: u1,
-            reserved24: u4,
-            ///  Unaligned access usage fault
-            UNALIGNED: u1,
-            ///  Divide by zero usage fault
-            DIVBYZERO: u1,
-            padding: u6,
-        }),
-        ///  Hard fault status register
-        HFSR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Vector table hard fault
-            VECTTBL: u1,
-            reserved30: u28,
-            ///  Forced hard fault
-            FORCED: u1,
-            ///  Reserved for Debug use
-            DEBUG_VT: u1,
-        }),
-        reserved52: [4]u8,
-        ///  Memory management fault address register
-        MMFAR: mmio.Mmio(packed struct(u32) {
-            ///  Memory management fault address
-            MMFAR: u32,
-        }),
-        ///  Bus fault address register
-        BFAR: mmio.Mmio(packed struct(u32) {
-            ///  Bus fault address
-            BFAR: u32,
-        }),
-        ///  Auxiliary fault status register
-        AFSR: mmio.Mmio(packed struct(u32) {
-            ///  Implementation defined
-            IMPDEF: u32,
-        }),
-    };
-
-    ///  SysTick timer
-    pub const STK = extern struct {
-        ///  SysTick control and status register
-        CTRL: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            ENABLE: u1,
-            ///  SysTick exception request enable
-            TICKINT: u1,
-            ///  Clock source selection
-            CLKSOURCE: u1,
-            reserved16: u13,
-            ///  COUNTFLAG
-            COUNTFLAG: u1,
-            padding: u15,
-        }),
-        ///  SysTick reload value register
-        LOAD: mmio.Mmio(packed struct(u32) {
-            ///  RELOAD value
-            RELOAD: u24,
-            padding: u8,
-        }),
-        ///  SysTick current value register
-        VAL: mmio.Mmio(packed struct(u32) {
-            ///  Current counter value
-            CURRENT: u24,
-            padding: u8,
-        }),
-        ///  SysTick calibration value register
-        CALIB: mmio.Mmio(packed struct(u32) {
-            ///  Calibration value
-            TENMS: u24,
-            reserved30: u6,
-            ///  SKEW flag: Indicates whether the TENMS value is exact
-            SKEW: u1,
-            ///  NOREF flag. Reads as zero
-            NOREF: u1,
-        }),
-    };
-
-    ///  Memory protection unit
-    pub const MPU = extern struct {
-        ///  MPU type register
-        MPU_TYPER: mmio.Mmio(packed struct(u32) {
-            ///  Separate flag
-            SEPARATE: u1,
-            reserved8: u7,
-            ///  Number of MPU data regions
-            DREGION: u8,
-            ///  Number of MPU instruction regions
-            IREGION: u8,
-            padding: u8,
-        }),
-        ///  MPU control register
-        MPU_CTRL: mmio.Mmio(packed struct(u32) {
-            ///  Enables the MPU
-            ENABLE: u1,
-            ///  Enables the operation of MPU during hard fault
-            HFNMIENA: u1,
-            ///  Enable priviliged software access to default memory map
-            PRIVDEFENA: u1,
-            padding: u29,
-        }),
-        ///  MPU region number register
-        MPU_RNR: mmio.Mmio(packed struct(u32) {
-            ///  MPU region
-            REGION: u8,
-            padding: u24,
-        }),
-        ///  MPU region base address register
-        MPU_RBAR: mmio.Mmio(packed struct(u32) {
-            ///  MPU region field
-            REGION: u4,
-            ///  MPU region number valid
-            VALID: u1,
-            ///  Region base address field
-            ADDR: u27,
-        }),
-        ///  MPU region attribute and size register
-        MPU_RASR: mmio.Mmio(packed struct(u32) {
-            ///  Region enable bit.
-            ENABLE: u1,
-            ///  Size of the MPU protection region
-            SIZE: u5,
-            reserved8: u2,
-            ///  Subregion disable bits
-            SRD: u8,
-            ///  memory attribute
-            B: u1,
-            ///  memory attribute
-            C: u1,
-            ///  Shareable memory attribute
-            S: u1,
-            ///  memory attribute
-            TEX: u3,
-            reserved24: u2,
-            ///  Access permission
-            AP: u3,
-            reserved28: u1,
-            ///  Instruction access disable bit
-            XN: u1,
-            padding: u3,
-        }),
-    };
-
-    ///  Floting point unit
-    pub const FPU = extern struct {
-        ///  Floating-point context control register
-        FPCCR: mmio.Mmio(packed struct(u32) {
-            ///  LSPACT
-            LSPACT: u1,
-            ///  USER
-            USER: u1,
-            reserved3: u1,
-            ///  THREAD
-            THREAD: u1,
-            ///  HFRDY
-            HFRDY: u1,
-            ///  MMRDY
-            MMRDY: u1,
-            ///  BFRDY
-            BFRDY: u1,
-            reserved8: u1,
-            ///  MONRDY
-            MONRDY: u1,
-            reserved30: u21,
-            ///  LSPEN
-            LSPEN: u1,
-            ///  ASPEN
-            ASPEN: u1,
-        }),
-        ///  Floating-point context address register
-        FPCAR: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Location of unpopulated floating-point
-            ADDRESS: u29,
-        }),
-        ///  Floating-point status control register
-        FPSCR: mmio.Mmio(packed struct(u32) {
-            ///  Invalid operation cumulative exception bit
-            IOC: u1,
-            ///  Division by zero cumulative exception bit.
-            DZC: u1,
-            ///  Overflow cumulative exception bit
-            OFC: u1,
-            ///  Underflow cumulative exception bit
-            UFC: u1,
-            ///  Inexact cumulative exception bit
-            IXC: u1,
-            reserved7: u2,
-            ///  Input denormal cumulative exception bit.
-            IDC: u1,
-            reserved22: u14,
-            ///  Rounding Mode control field
-            RMode: u2,
-            ///  Flush-to-zero mode control bit:
-            FZ: u1,
-            ///  Default NaN mode control bit
-            DN: u1,
-            ///  Alternative half-precision control bit
-            AHP: u1,
-            reserved28: u1,
-            ///  Overflow condition code flag
-            V: u1,
-            ///  Carry condition code flag
-            C: u1,
-            ///  Zero condition code flag
-            Z: u1,
-            ///  Negative condition code flag
-            N: u1,
-        }),
-    };
-
-    ///  Cryptographic processor
-    pub const CRYP = extern struct {
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Algorithm direction
-            ALGODIR: u1,
-            ///  Algorithm mode
-            ALGOMODE0: u3,
-            ///  Data type selection
-            DATATYPE: u2,
-            ///  Key size selection (AES mode only)
-            KEYSIZE: u2,
-            reserved14: u4,
-            ///  FIFO flush
-            FFLUSH: u1,
-            ///  Cryptographic processor enable
-            CRYPEN: u1,
-            ///  GCM_CCMPH
-            GCM_CCMPH: u2,
-            reserved19: u1,
-            ///  ALGOMODE
-            ALGOMODE3: u1,
-            padding: u12,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Input FIFO empty
-            IFEM: u1,
-            ///  Input FIFO not full
-            IFNF: u1,
-            ///  Output FIFO not empty
-            OFNE: u1,
-            ///  Output FIFO full
-            OFFU: u1,
-            ///  Busy bit
-            BUSY: u1,
-            padding: u27,
-        }),
-        ///  data input register
-        DIN: mmio.Mmio(packed struct(u32) {
-            ///  Data input
-            DATAIN: u32,
-        }),
-        ///  data output register
-        DOUT: mmio.Mmio(packed struct(u32) {
-            ///  Data output
-            DATAOUT: u32,
-        }),
-        ///  DMA control register
-        DMACR: mmio.Mmio(packed struct(u32) {
-            ///  DMA input enable
-            DIEN: u1,
-            ///  DMA output enable
-            DOEN: u1,
-            padding: u30,
-        }),
-        ///  interrupt mask set/clear register
-        IMSCR: mmio.Mmio(packed struct(u32) {
-            ///  Input FIFO service interrupt mask
-            INIM: u1,
-            ///  Output FIFO service interrupt mask
-            OUTIM: u1,
-            padding: u30,
-        }),
-        ///  raw interrupt status register
-        RISR: mmio.Mmio(packed struct(u32) {
-            ///  Input FIFO service raw interrupt status
-            INRIS: u1,
-            ///  Output FIFO service raw interrupt status
-            OUTRIS: u1,
-            padding: u30,
-        }),
-        ///  masked interrupt status register
-        MISR: mmio.Mmio(packed struct(u32) {
-            ///  Input FIFO service masked interrupt status
-            INMIS: u1,
-            ///  Output FIFO service masked interrupt status
-            OUTMIS: u1,
-            padding: u30,
-        }),
-        ///  key registers
-        K0LR: mmio.Mmio(packed struct(u32) {
-            ///  b224
-            b224: u1,
-            ///  b225
-            b225: u1,
-            ///  b226
-            b226: u1,
-            ///  b227
-            b227: u1,
-            ///  b228
-            b228: u1,
-            ///  b229
-            b229: u1,
-            ///  b230
-            b230: u1,
-            ///  b231
-            b231: u1,
-            ///  b232
-            b232: u1,
-            ///  b233
-            b233: u1,
-            ///  b234
-            b234: u1,
-            ///  b235
-            b235: u1,
-            ///  b236
-            b236: u1,
-            ///  b237
-            b237: u1,
-            ///  b238
-            b238: u1,
-            ///  b239
-            b239: u1,
-            ///  b240
-            b240: u1,
-            ///  b241
-            b241: u1,
-            ///  b242
-            b242: u1,
-            ///  b243
-            b243: u1,
-            ///  b244
-            b244: u1,
-            ///  b245
-            b245: u1,
-            ///  b246
-            b246: u1,
-            ///  b247
-            b247: u1,
-            ///  b248
-            b248: u1,
-            ///  b249
-            b249: u1,
-            ///  b250
-            b250: u1,
-            ///  b251
-            b251: u1,
-            ///  b252
-            b252: u1,
-            ///  b253
-            b253: u1,
-            ///  b254
-            b254: u1,
-            ///  b255
-            b255: u1,
-        }),
-        ///  key registers
-        K0RR: mmio.Mmio(packed struct(u32) {
-            ///  b192
-            b192: u1,
-            ///  b193
-            b193: u1,
-            ///  b194
-            b194: u1,
-            ///  b195
-            b195: u1,
-            ///  b196
-            b196: u1,
-            ///  b197
-            b197: u1,
-            ///  b198
-            b198: u1,
-            ///  b199
-            b199: u1,
-            ///  b200
-            b200: u1,
-            ///  b201
-            b201: u1,
-            ///  b202
-            b202: u1,
-            ///  b203
-            b203: u1,
-            ///  b204
-            b204: u1,
-            ///  b205
-            b205: u1,
-            ///  b206
-            b206: u1,
-            ///  b207
-            b207: u1,
-            ///  b208
-            b208: u1,
-            ///  b209
-            b209: u1,
-            ///  b210
-            b210: u1,
-            ///  b211
-            b211: u1,
-            ///  b212
-            b212: u1,
-            ///  b213
-            b213: u1,
-            ///  b214
-            b214: u1,
-            ///  b215
-            b215: u1,
-            ///  b216
-            b216: u1,
-            ///  b217
-            b217: u1,
-            ///  b218
-            b218: u1,
-            ///  b219
-            b219: u1,
-            ///  b220
-            b220: u1,
-            ///  b221
-            b221: u1,
-            ///  b222
-            b222: u1,
-            ///  b223
-            b223: u1,
-        }),
-        ///  key registers
-        K1LR: mmio.Mmio(packed struct(u32) {
-            ///  b160
-            b160: u1,
-            ///  b161
-            b161: u1,
-            ///  b162
-            b162: u1,
-            ///  b163
-            b163: u1,
-            ///  b164
-            b164: u1,
-            ///  b165
-            b165: u1,
-            ///  b166
-            b166: u1,
-            ///  b167
-            b167: u1,
-            ///  b168
-            b168: u1,
-            ///  b169
-            b169: u1,
-            ///  b170
-            b170: u1,
-            ///  b171
-            b171: u1,
-            ///  b172
-            b172: u1,
-            ///  b173
-            b173: u1,
-            ///  b174
-            b174: u1,
-            ///  b175
-            b175: u1,
-            ///  b176
-            b176: u1,
-            ///  b177
-            b177: u1,
-            ///  b178
-            b178: u1,
-            ///  b179
-            b179: u1,
-            ///  b180
-            b180: u1,
-            ///  b181
-            b181: u1,
-            ///  b182
-            b182: u1,
-            ///  b183
-            b183: u1,
-            ///  b184
-            b184: u1,
-            ///  b185
-            b185: u1,
-            ///  b186
-            b186: u1,
-            ///  b187
-            b187: u1,
-            ///  b188
-            b188: u1,
-            ///  b189
-            b189: u1,
-            ///  b190
-            b190: u1,
-            ///  b191
-            b191: u1,
-        }),
-        ///  key registers
-        K1RR: mmio.Mmio(packed struct(u32) {
-            ///  b128
-            b128: u1,
-            ///  b129
-            b129: u1,
-            ///  b130
-            b130: u1,
-            ///  b131
-            b131: u1,
-            ///  b132
-            b132: u1,
-            ///  b133
-            b133: u1,
-            ///  b134
-            b134: u1,
-            ///  b135
-            b135: u1,
-            ///  b136
-            b136: u1,
-            ///  b137
-            b137: u1,
-            ///  b138
-            b138: u1,
-            ///  b139
-            b139: u1,
-            ///  b140
-            b140: u1,
-            ///  b141
-            b141: u1,
-            ///  b142
-            b142: u1,
-            ///  b143
-            b143: u1,
-            ///  b144
-            b144: u1,
-            ///  b145
-            b145: u1,
-            ///  b146
-            b146: u1,
-            ///  b147
-            b147: u1,
-            ///  b148
-            b148: u1,
-            ///  b149
-            b149: u1,
-            ///  b150
-            b150: u1,
-            ///  b151
-            b151: u1,
-            ///  b152
-            b152: u1,
-            ///  b153
-            b153: u1,
-            ///  b154
-            b154: u1,
-            ///  b155
-            b155: u1,
-            ///  b156
-            b156: u1,
-            ///  b157
-            b157: u1,
-            ///  b158
-            b158: u1,
-            ///  b159
-            b159: u1,
-        }),
-        ///  key registers
-        K2LR: mmio.Mmio(packed struct(u32) {
-            ///  b96
-            b96: u1,
-            ///  b97
-            b97: u1,
-            ///  b98
-            b98: u1,
-            ///  b99
-            b99: u1,
-            ///  b100
-            b100: u1,
-            ///  b101
-            b101: u1,
-            ///  b102
-            b102: u1,
-            ///  b103
-            b103: u1,
-            ///  b104
-            b104: u1,
-            ///  b105
-            b105: u1,
-            ///  b106
-            b106: u1,
-            ///  b107
-            b107: u1,
-            ///  b108
-            b108: u1,
-            ///  b109
-            b109: u1,
-            ///  b110
-            b110: u1,
-            ///  b111
-            b111: u1,
-            ///  b112
-            b112: u1,
-            ///  b113
-            b113: u1,
-            ///  b114
-            b114: u1,
-            ///  b115
-            b115: u1,
-            ///  b116
-            b116: u1,
-            ///  b117
-            b117: u1,
-            ///  b118
-            b118: u1,
-            ///  b119
-            b119: u1,
-            ///  b120
-            b120: u1,
-            ///  b121
-            b121: u1,
-            ///  b122
-            b122: u1,
-            ///  b123
-            b123: u1,
-            ///  b124
-            b124: u1,
-            ///  b125
-            b125: u1,
-            ///  b126
-            b126: u1,
-            ///  b127
-            b127: u1,
-        }),
-        ///  key registers
-        K2RR: mmio.Mmio(packed struct(u32) {
-            ///  b64
-            b64: u1,
-            ///  b65
-            b65: u1,
-            ///  b66
-            b66: u1,
-            ///  b67
-            b67: u1,
-            ///  b68
-            b68: u1,
-            ///  b69
-            b69: u1,
-            ///  b70
-            b70: u1,
-            ///  b71
-            b71: u1,
-            ///  b72
-            b72: u1,
-            ///  b73
-            b73: u1,
-            ///  b74
-            b74: u1,
-            ///  b75
-            b75: u1,
-            ///  b76
-            b76: u1,
-            ///  b77
-            b77: u1,
-            ///  b78
-            b78: u1,
-            ///  b79
-            b79: u1,
-            ///  b80
-            b80: u1,
-            ///  b81
-            b81: u1,
-            ///  b82
-            b82: u1,
-            ///  b83
-            b83: u1,
-            ///  b84
-            b84: u1,
-            ///  b85
-            b85: u1,
-            ///  b86
-            b86: u1,
-            ///  b87
-            b87: u1,
-            ///  b88
-            b88: u1,
-            ///  b89
-            b89: u1,
-            ///  b90
-            b90: u1,
-            ///  b91
-            b91: u1,
-            ///  b92
-            b92: u1,
-            ///  b93
-            b93: u1,
-            ///  b94
-            b94: u1,
-            ///  b95
-            b95: u1,
-        }),
-        ///  key registers
-        K3LR: mmio.Mmio(packed struct(u32) {
-            ///  b32
-            b32: u1,
-            ///  b33
-            b33: u1,
-            ///  b34
-            b34: u1,
-            ///  b35
-            b35: u1,
-            ///  b36
-            b36: u1,
-            ///  b37
-            b37: u1,
-            ///  b38
-            b38: u1,
-            ///  b39
-            b39: u1,
-            ///  b40
-            b40: u1,
-            ///  b41
-            b41: u1,
-            ///  b42
-            b42: u1,
-            ///  b43
-            b43: u1,
-            ///  b44
-            b44: u1,
-            ///  b45
-            b45: u1,
-            ///  b46
-            b46: u1,
-            ///  b47
-            b47: u1,
-            ///  b48
-            b48: u1,
-            ///  b49
-            b49: u1,
-            ///  b50
-            b50: u1,
-            ///  b51
-            b51: u1,
-            ///  b52
-            b52: u1,
-            ///  b53
-            b53: u1,
-            ///  b54
-            b54: u1,
-            ///  b55
-            b55: u1,
-            ///  b56
-            b56: u1,
-            ///  b57
-            b57: u1,
-            ///  b58
-            b58: u1,
-            ///  b59
-            b59: u1,
-            ///  b60
-            b60: u1,
-            ///  b61
-            b61: u1,
-            ///  b62
-            b62: u1,
-            ///  b63
-            b63: u1,
-        }),
-        ///  key registers
-        K3RR: mmio.Mmio(packed struct(u32) {
-            ///  b0
-            b0: u1,
-            ///  b1
-            b1: u1,
-            ///  b2
-            b2: u1,
-            ///  b3
-            b3: u1,
-            ///  b4
-            b4: u1,
-            ///  b5
-            b5: u1,
-            ///  b6
-            b6: u1,
-            ///  b7
-            b7: u1,
-            ///  b8
-            b8: u1,
-            ///  b9
-            b9: u1,
-            ///  b10
-            b10: u1,
-            ///  b11
-            b11: u1,
-            ///  b12
-            b12: u1,
-            ///  b13
-            b13: u1,
-            ///  b14
-            b14: u1,
-            ///  b15
-            b15: u1,
-            ///  b16
-            b16: u1,
-            ///  b17
-            b17: u1,
-            ///  b18
-            b18: u1,
-            ///  b19
-            b19: u1,
-            ///  b20
-            b20: u1,
-            ///  b21
-            b21: u1,
-            ///  b22
-            b22: u1,
-            ///  b23
-            b23: u1,
-            ///  b24
-            b24: u1,
-            ///  b25
-            b25: u1,
-            ///  b26
-            b26: u1,
-            ///  b27
-            b27: u1,
-            ///  b28
-            b28: u1,
-            ///  b29
-            b29: u1,
-            ///  b30
-            b30: u1,
-            ///  b31
-            b31: u1,
-        }),
-        ///  initialization vector registers
-        IV0LR: mmio.Mmio(packed struct(u32) {
-            ///  IV31
-            IV31: u1,
-            ///  IV30
-            IV30: u1,
-            ///  IV29
-            IV29: u1,
-            ///  IV28
-            IV28: u1,
-            ///  IV27
-            IV27: u1,
-            ///  IV26
-            IV26: u1,
-            ///  IV25
-            IV25: u1,
-            ///  IV24
-            IV24: u1,
-            ///  IV23
-            IV23: u1,
-            ///  IV22
-            IV22: u1,
-            ///  IV21
-            IV21: u1,
-            ///  IV20
-            IV20: u1,
-            ///  IV19
-            IV19: u1,
-            ///  IV18
-            IV18: u1,
-            ///  IV17
-            IV17: u1,
-            ///  IV16
-            IV16: u1,
-            ///  IV15
-            IV15: u1,
-            ///  IV14
-            IV14: u1,
-            ///  IV13
-            IV13: u1,
-            ///  IV12
-            IV12: u1,
-            ///  IV11
-            IV11: u1,
-            ///  IV10
-            IV10: u1,
-            ///  IV9
-            IV9: u1,
-            ///  IV8
-            IV8: u1,
-            ///  IV7
-            IV7: u1,
-            ///  IV6
-            IV6: u1,
-            ///  IV5
-            IV5: u1,
-            ///  IV4
-            IV4: u1,
-            ///  IV3
-            IV3: u1,
-            ///  IV2
-            IV2: u1,
-            ///  IV1
-            IV1: u1,
-            ///  IV0
-            IV0: u1,
-        }),
-        ///  initialization vector registers
-        IV0RR: mmio.Mmio(packed struct(u32) {
-            ///  IV63
-            IV63: u1,
-            ///  IV62
-            IV62: u1,
-            ///  IV61
-            IV61: u1,
-            ///  IV60
-            IV60: u1,
-            ///  IV59
-            IV59: u1,
-            ///  IV58
-            IV58: u1,
-            ///  IV57
-            IV57: u1,
-            ///  IV56
-            IV56: u1,
-            ///  IV55
-            IV55: u1,
-            ///  IV54
-            IV54: u1,
-            ///  IV53
-            IV53: u1,
-            ///  IV52
-            IV52: u1,
-            ///  IV51
-            IV51: u1,
-            ///  IV50
-            IV50: u1,
-            ///  IV49
-            IV49: u1,
-            ///  IV48
-            IV48: u1,
-            ///  IV47
-            IV47: u1,
-            ///  IV46
-            IV46: u1,
-            ///  IV45
-            IV45: u1,
-            ///  IV44
-            IV44: u1,
-            ///  IV43
-            IV43: u1,
-            ///  IV42
-            IV42: u1,
-            ///  IV41
-            IV41: u1,
-            ///  IV40
-            IV40: u1,
-            ///  IV39
-            IV39: u1,
-            ///  IV38
-            IV38: u1,
-            ///  IV37
-            IV37: u1,
-            ///  IV36
-            IV36: u1,
-            ///  IV35
-            IV35: u1,
-            ///  IV34
-            IV34: u1,
-            ///  IV33
-            IV33: u1,
-            ///  IV32
-            IV32: u1,
-        }),
-        ///  initialization vector registers
-        IV1LR: mmio.Mmio(packed struct(u32) {
-            ///  IV95
-            IV95: u1,
-            ///  IV94
-            IV94: u1,
-            ///  IV93
-            IV93: u1,
-            ///  IV92
-            IV92: u1,
-            ///  IV91
-            IV91: u1,
-            ///  IV90
-            IV90: u1,
-            ///  IV89
-            IV89: u1,
-            ///  IV88
-            IV88: u1,
-            ///  IV87
-            IV87: u1,
-            ///  IV86
-            IV86: u1,
-            ///  IV85
-            IV85: u1,
-            ///  IV84
-            IV84: u1,
-            ///  IV83
-            IV83: u1,
-            ///  IV82
-            IV82: u1,
-            ///  IV81
-            IV81: u1,
-            ///  IV80
-            IV80: u1,
-            ///  IV79
-            IV79: u1,
-            ///  IV78
-            IV78: u1,
-            ///  IV77
-            IV77: u1,
-            ///  IV76
-            IV76: u1,
-            ///  IV75
-            IV75: u1,
-            ///  IV74
-            IV74: u1,
-            ///  IV73
-            IV73: u1,
-            ///  IV72
-            IV72: u1,
-            ///  IV71
-            IV71: u1,
-            ///  IV70
-            IV70: u1,
-            ///  IV69
-            IV69: u1,
-            ///  IV68
-            IV68: u1,
-            ///  IV67
-            IV67: u1,
-            ///  IV66
-            IV66: u1,
-            ///  IV65
-            IV65: u1,
-            ///  IV64
-            IV64: u1,
-        }),
-        ///  initialization vector registers
-        IV1RR: mmio.Mmio(packed struct(u32) {
-            ///  IV127
-            IV127: u1,
-            ///  IV126
-            IV126: u1,
-            ///  IV125
-            IV125: u1,
-            ///  IV124
-            IV124: u1,
-            ///  IV123
-            IV123: u1,
-            ///  IV122
-            IV122: u1,
-            ///  IV121
-            IV121: u1,
-            ///  IV120
-            IV120: u1,
-            ///  IV119
-            IV119: u1,
-            ///  IV118
-            IV118: u1,
-            ///  IV117
-            IV117: u1,
-            ///  IV116
-            IV116: u1,
-            ///  IV115
-            IV115: u1,
-            ///  IV114
-            IV114: u1,
-            ///  IV113
-            IV113: u1,
-            ///  IV112
-            IV112: u1,
-            ///  IV111
-            IV111: u1,
-            ///  IV110
-            IV110: u1,
-            ///  IV109
-            IV109: u1,
-            ///  IV108
-            IV108: u1,
-            ///  IV107
-            IV107: u1,
-            ///  IV106
-            IV106: u1,
-            ///  IV105
-            IV105: u1,
-            ///  IV104
-            IV104: u1,
-            ///  IV103
-            IV103: u1,
-            ///  IV102
-            IV102: u1,
-            ///  IV101
-            IV101: u1,
-            ///  IV100
-            IV100: u1,
-            ///  IV99
-            IV99: u1,
-            ///  IV98
-            IV98: u1,
-            ///  IV97
-            IV97: u1,
-            ///  IV96
-            IV96: u1,
-        }),
-        ///  context swap register
-        CSGCMCCM0R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM0R
-            CSGCMCCM0R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM1R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM1R
-            CSGCMCCM1R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM2R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM2R
-            CSGCMCCM2R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM3R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM3R
-            CSGCMCCM3R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM4R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM4R
-            CSGCMCCM4R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM5R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM5R
-            CSGCMCCM5R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM6R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM6R
-            CSGCMCCM6R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM7R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM7R
-            CSGCMCCM7R: u32,
-        }),
-        ///  context swap register
-        CSGCM0R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM0R
-            CSGCM0R: u32,
-        }),
-        ///  context swap register
-        CSGCM1R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM1R
-            CSGCM1R: u32,
-        }),
-        ///  context swap register
-        CSGCM2R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM2R
-            CSGCM2R: u32,
-        }),
-        ///  context swap register
-        CSGCM3R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM3R
-            CSGCM3R: u32,
-        }),
-        ///  context swap register
-        CSGCM4R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM4R
-            CSGCM4R: u32,
-        }),
-        ///  context swap register
-        CSGCM5R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM5R
-            CSGCM5R: u32,
-        }),
-        ///  context swap register
-        CSGCM6R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM6R
-            CSGCM6R: u32,
-        }),
-        ///  context swap register
-        CSGCM7R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM7R
-            CSGCM7R: u32,
-        }),
-    };
-
-    ///  Hash processor
-    pub const HASH = extern struct {
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Initialize message digest calculation
-            INIT: u1,
-            ///  DMA enable
-            DMAE: u1,
-            ///  Data type selection
-            DATATYPE: u2,
-            ///  Mode selection
-            MODE: u1,
-            ///  Algorithm selection
-            ALGO0: u1,
-            ///  Number of words already pushed
-            NBW: u4,
-            ///  DIN not empty
-            DINNE: u1,
-            ///  Multiple DMA Transfers
-            MDMAT: u1,
-            reserved16: u2,
-            ///  Long key selection
-            LKEY: u1,
-            reserved18: u1,
-            ///  ALGO
-            ALGO1: u1,
-            padding: u13,
-        }),
-        ///  data input register
-        DIN: mmio.Mmio(packed struct(u32) {
-            ///  Data input
-            DATAIN: u32,
-        }),
-        ///  start register
-        STR: mmio.Mmio(packed struct(u32) {
-            ///  Number of valid bits in the last word of the message
-            NBLW: u5,
-            reserved8: u3,
-            ///  Digest calculation
-            DCAL: u1,
-            padding: u23,
-        }),
-        ///  digest registers
-        HR0: mmio.Mmio(packed struct(u32) {
-            ///  H0
-            H0: u32,
-        }),
-        ///  digest registers
-        HR1: mmio.Mmio(packed struct(u32) {
-            ///  H1
-            H1: u32,
-        }),
-        ///  digest registers
-        HR2: mmio.Mmio(packed struct(u32) {
-            ///  H2
-            H2: u32,
-        }),
-        ///  digest registers
-        HR3: mmio.Mmio(packed struct(u32) {
-            ///  H3
-            H3: u32,
-        }),
-        ///  digest registers
-        HR4: mmio.Mmio(packed struct(u32) {
-            ///  H4
-            H4: u32,
-        }),
-        ///  interrupt enable register
-        IMR: mmio.Mmio(packed struct(u32) {
-            ///  Data input interrupt enable
-            DINIE: u1,
-            ///  Digest calculation completion interrupt enable
-            DCIE: u1,
-            padding: u30,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Data input interrupt status
-            DINIS: u1,
-            ///  Digest calculation completion interrupt status
-            DCIS: u1,
-            ///  DMA Status
-            DMAS: u1,
-            ///  Busy bit
-            BUSY: u1,
-            padding: u28,
-        }),
-        reserved248: [208]u8,
-        ///  context swap registers
-        CSR0: mmio.Mmio(packed struct(u32) {
-            ///  CSR0
-            CSR0: u32,
-        }),
-        ///  context swap registers
-        CSR1: mmio.Mmio(packed struct(u32) {
-            ///  CSR1
-            CSR1: u32,
-        }),
-        ///  context swap registers
-        CSR2: mmio.Mmio(packed struct(u32) {
-            ///  CSR2
-            CSR2: u32,
-        }),
-        ///  context swap registers
-        CSR3: mmio.Mmio(packed struct(u32) {
-            ///  CSR3
-            CSR3: u32,
-        }),
-        ///  context swap registers
-        CSR4: mmio.Mmio(packed struct(u32) {
-            ///  CSR4
-            CSR4: u32,
-        }),
-        ///  context swap registers
-        CSR5: mmio.Mmio(packed struct(u32) {
-            ///  CSR5
-            CSR5: u32,
-        }),
-        ///  context swap registers
-        CSR6: mmio.Mmio(packed struct(u32) {
-            ///  CSR6
-            CSR6: u32,
-        }),
-        ///  context swap registers
-        CSR7: mmio.Mmio(packed struct(u32) {
-            ///  CSR7
-            CSR7: u32,
-        }),
-        ///  context swap registers
-        CSR8: mmio.Mmio(packed struct(u32) {
-            ///  CSR8
-            CSR8: u32,
-        }),
-        ///  context swap registers
-        CSR9: mmio.Mmio(packed struct(u32) {
-            ///  CSR9
-            CSR9: u32,
-        }),
-        ///  context swap registers
-        CSR10: mmio.Mmio(packed struct(u32) {
-            ///  CSR10
-            CSR10: u32,
-        }),
-        ///  context swap registers
-        CSR11: mmio.Mmio(packed struct(u32) {
-            ///  CSR11
-            CSR11: u32,
-        }),
-        ///  context swap registers
-        CSR12: mmio.Mmio(packed struct(u32) {
-            ///  CSR12
-            CSR12: u32,
-        }),
-        ///  context swap registers
-        CSR13: mmio.Mmio(packed struct(u32) {
-            ///  CSR13
-            CSR13: u32,
-        }),
-        ///  context swap registers
-        CSR14: mmio.Mmio(packed struct(u32) {
-            ///  CSR14
-            CSR14: u32,
-        }),
-        ///  context swap registers
-        CSR15: mmio.Mmio(packed struct(u32) {
-            ///  CSR15
-            CSR15: u32,
-        }),
-        ///  context swap registers
-        CSR16: mmio.Mmio(packed struct(u32) {
-            ///  CSR16
-            CSR16: u32,
-        }),
-        ///  context swap registers
-        CSR17: mmio.Mmio(packed struct(u32) {
-            ///  CSR17
-            CSR17: u32,
-        }),
-        ///  context swap registers
-        CSR18: mmio.Mmio(packed struct(u32) {
-            ///  CSR18
-            CSR18: u32,
-        }),
-        ///  context swap registers
-        CSR19: mmio.Mmio(packed struct(u32) {
-            ///  CSR19
-            CSR19: u32,
-        }),
-        ///  context swap registers
-        CSR20: mmio.Mmio(packed struct(u32) {
-            ///  CSR20
-            CSR20: u32,
-        }),
-        ///  context swap registers
-        CSR21: mmio.Mmio(packed struct(u32) {
-            ///  CSR21
-            CSR21: u32,
-        }),
-        ///  context swap registers
-        CSR22: mmio.Mmio(packed struct(u32) {
-            ///  CSR22
-            CSR22: u32,
-        }),
-        ///  context swap registers
-        CSR23: mmio.Mmio(packed struct(u32) {
-            ///  CSR23
-            CSR23: u32,
-        }),
-        ///  context swap registers
-        CSR24: mmio.Mmio(packed struct(u32) {
-            ///  CSR24
-            CSR24: u32,
-        }),
-        ///  context swap registers
-        CSR25: mmio.Mmio(packed struct(u32) {
-            ///  CSR25
-            CSR25: u32,
-        }),
-        ///  context swap registers
-        CSR26: mmio.Mmio(packed struct(u32) {
-            ///  CSR26
-            CSR26: u32,
-        }),
-        ///  context swap registers
-        CSR27: mmio.Mmio(packed struct(u32) {
-            ///  CSR27
-            CSR27: u32,
-        }),
-        ///  context swap registers
-        CSR28: mmio.Mmio(packed struct(u32) {
-            ///  CSR28
-            CSR28: u32,
-        }),
-        ///  context swap registers
-        CSR29: mmio.Mmio(packed struct(u32) {
-            ///  CSR29
-            CSR29: u32,
-        }),
-        ///  context swap registers
-        CSR30: mmio.Mmio(packed struct(u32) {
-            ///  CSR30
-            CSR30: u32,
-        }),
-        ///  context swap registers
-        CSR31: mmio.Mmio(packed struct(u32) {
-            ///  CSR31
-            CSR31: u32,
-        }),
-        ///  context swap registers
-        CSR32: mmio.Mmio(packed struct(u32) {
-            ///  CSR32
-            CSR32: u32,
-        }),
-        ///  context swap registers
-        CSR33: mmio.Mmio(packed struct(u32) {
-            ///  CSR33
-            CSR33: u32,
-        }),
-        ///  context swap registers
-        CSR34: mmio.Mmio(packed struct(u32) {
-            ///  CSR34
-            CSR34: u32,
-        }),
-        ///  context swap registers
-        CSR35: mmio.Mmio(packed struct(u32) {
-            ///  CSR35
-            CSR35: u32,
-        }),
-        ///  context swap registers
-        CSR36: mmio.Mmio(packed struct(u32) {
-            ///  CSR36
-            CSR36: u32,
-        }),
-        ///  context swap registers
-        CSR37: mmio.Mmio(packed struct(u32) {
-            ///  CSR37
-            CSR37: u32,
-        }),
-        ///  context swap registers
-        CSR38: mmio.Mmio(packed struct(u32) {
-            ///  CSR38
-            CSR38: u32,
-        }),
-        ///  context swap registers
-        CSR39: mmio.Mmio(packed struct(u32) {
-            ///  CSR39
-            CSR39: u32,
-        }),
-        ///  context swap registers
-        CSR40: mmio.Mmio(packed struct(u32) {
-            ///  CSR40
-            CSR40: u32,
-        }),
-        ///  context swap registers
-        CSR41: mmio.Mmio(packed struct(u32) {
-            ///  CSR41
-            CSR41: u32,
-        }),
-        ///  context swap registers
-        CSR42: mmio.Mmio(packed struct(u32) {
-            ///  CSR42
-            CSR42: u32,
-        }),
-        ///  context swap registers
-        CSR43: mmio.Mmio(packed struct(u32) {
-            ///  CSR43
-            CSR43: u32,
-        }),
-        ///  context swap registers
-        CSR44: mmio.Mmio(packed struct(u32) {
-            ///  CSR44
-            CSR44: u32,
-        }),
-        ///  context swap registers
-        CSR45: mmio.Mmio(packed struct(u32) {
-            ///  CSR45
-            CSR45: u32,
-        }),
-        ///  context swap registers
-        CSR46: mmio.Mmio(packed struct(u32) {
-            ///  CSR46
-            CSR46: u32,
-        }),
-        ///  context swap registers
-        CSR47: mmio.Mmio(packed struct(u32) {
-            ///  CSR47
-            CSR47: u32,
-        }),
-        ///  context swap registers
-        CSR48: mmio.Mmio(packed struct(u32) {
-            ///  CSR48
-            CSR48: u32,
-        }),
-        ///  context swap registers
-        CSR49: mmio.Mmio(packed struct(u32) {
-            ///  CSR49
-            CSR49: u32,
-        }),
-        ///  context swap registers
-        CSR50: mmio.Mmio(packed struct(u32) {
-            ///  CSR50
-            CSR50: u32,
-        }),
-        ///  context swap registers
-        CSR51: mmio.Mmio(packed struct(u32) {
-            ///  CSR51
-            CSR51: u32,
-        }),
-        ///  context swap registers
-        CSR52: mmio.Mmio(packed struct(u32) {
-            ///  CSR52
-            CSR52: u32,
-        }),
-        ///  context swap registers
-        CSR53: mmio.Mmio(packed struct(u32) {
-            ///  CSR53
-            CSR53: u32,
-        }),
-        reserved784: [320]u8,
-        ///  HASH digest register
-        HASH_HR0: mmio.Mmio(packed struct(u32) {
-            ///  H0
-            H0: u32,
-        }),
-        ///  read-only
-        HASH_HR1: mmio.Mmio(packed struct(u32) {
-            ///  H1
-            H1: u32,
-        }),
-        ///  read-only
-        HASH_HR2: mmio.Mmio(packed struct(u32) {
-            ///  H2
-            H2: u32,
-        }),
-        ///  read-only
-        HASH_HR3: mmio.Mmio(packed struct(u32) {
-            ///  H3
-            H3: u32,
-        }),
-        ///  read-only
-        HASH_HR4: mmio.Mmio(packed struct(u32) {
-            ///  H4
-            H4: u32,
-        }),
-        ///  read-only
-        HASH_HR5: mmio.Mmio(packed struct(u32) {
-            ///  H5
-            H5: u32,
-        }),
-        ///  read-only
-        HASH_HR6: mmio.Mmio(packed struct(u32) {
-            ///  H6
-            H6: u32,
-        }),
-        ///  read-only
-        HASH_HR7: mmio.Mmio(packed struct(u32) {
-            ///  H7
-            H7: u32,
-        }),
-    };
-
-    ///  General-purpose I/Os
-    pub const GPIOB = extern struct {
-        ///  GPIO port mode register
-        MODER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            MODER0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER15: u2,
-        }),
-        ///  GPIO port output type register
-        OTYPER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OT0: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT1: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT2: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT3: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT4: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT5: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT6: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT7: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT8: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT9: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT10: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT11: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT12: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT13: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT14: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output speed register
-        OSPEEDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR15: u2,
-        }),
-        ///  GPIO port pull-up/pull-down register
-        PUPDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR15: u2,
-        }),
-        ///  GPIO port input data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Port input data (y = 0..15)
-            IDR0: u1,
-            ///  Port input data (y = 0..15)
-            IDR1: u1,
-            ///  Port input data (y = 0..15)
-            IDR2: u1,
-            ///  Port input data (y = 0..15)
-            IDR3: u1,
-            ///  Port input data (y = 0..15)
-            IDR4: u1,
-            ///  Port input data (y = 0..15)
-            IDR5: u1,
-            ///  Port input data (y = 0..15)
-            IDR6: u1,
-            ///  Port input data (y = 0..15)
-            IDR7: u1,
-            ///  Port input data (y = 0..15)
-            IDR8: u1,
-            ///  Port input data (y = 0..15)
-            IDR9: u1,
-            ///  Port input data (y = 0..15)
-            IDR10: u1,
-            ///  Port input data (y = 0..15)
-            IDR11: u1,
-            ///  Port input data (y = 0..15)
-            IDR12: u1,
-            ///  Port input data (y = 0..15)
-            IDR13: u1,
-            ///  Port input data (y = 0..15)
-            IDR14: u1,
-            ///  Port input data (y = 0..15)
-            IDR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output data register
-        ODR: mmio.Mmio(packed struct(u32) {
-            ///  Port output data (y = 0..15)
-            ODR0: u1,
-            ///  Port output data (y = 0..15)
-            ODR1: u1,
-            ///  Port output data (y = 0..15)
-            ODR2: u1,
-            ///  Port output data (y = 0..15)
-            ODR3: u1,
-            ///  Port output data (y = 0..15)
-            ODR4: u1,
-            ///  Port output data (y = 0..15)
-            ODR5: u1,
-            ///  Port output data (y = 0..15)
-            ODR6: u1,
-            ///  Port output data (y = 0..15)
-            ODR7: u1,
-            ///  Port output data (y = 0..15)
-            ODR8: u1,
-            ///  Port output data (y = 0..15)
-            ODR9: u1,
-            ///  Port output data (y = 0..15)
-            ODR10: u1,
-            ///  Port output data (y = 0..15)
-            ODR11: u1,
-            ///  Port output data (y = 0..15)
-            ODR12: u1,
-            ///  Port output data (y = 0..15)
-            ODR13: u1,
-            ///  Port output data (y = 0..15)
-            ODR14: u1,
-            ///  Port output data (y = 0..15)
-            ODR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port bit set/reset register
-        BSRR: mmio.Mmio(packed struct(u32) {
-            ///  Port x set bit y (y= 0..15)
-            BS0: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS1: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS2: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS3: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS4: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS5: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS6: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS7: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS8: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS9: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS10: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS11: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS12: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS13: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS14: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS15: u1,
-            ///  Port x set bit y (y= 0..15)
-            BR0: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR1: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR2: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR3: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR4: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR5: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR6: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR7: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR8: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR9: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR10: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR11: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR12: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR13: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR14: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR15: u1,
-        }),
-        ///  GPIO port configuration lock register
-        LCKR: mmio.Mmio(packed struct(u32) {
-            ///  Port x lock bit y (y= 0..15)
-            LCK0: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK1: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK2: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK3: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK4: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK5: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK6: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK7: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK8: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK9: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK10: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK11: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK12: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK13: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK14: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK15: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCKK: u1,
-            padding: u15,
-        }),
-        ///  GPIO alternate function low register
-        AFRL: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL0: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL1: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL2: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL3: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL4: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL5: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL6: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL7: u4,
-        }),
-        ///  GPIO alternate function high register
-        AFRH: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH8: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH9: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH10: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH11: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH12: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH13: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH14: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH15: u4,
-        }),
-    };
-
-    ///  General-purpose I/Os
-    pub const GPIOA = extern struct {
-        ///  GPIO port mode register
-        MODER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            MODER0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER15: u2,
-        }),
-        ///  GPIO port output type register
-        OTYPER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OT0: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT1: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT2: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT3: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT4: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT5: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT6: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT7: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT8: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT9: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT10: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT11: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT12: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT13: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT14: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output speed register
-        OSPEEDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR15: u2,
-        }),
-        ///  GPIO port pull-up/pull-down register
-        PUPDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR15: u2,
-        }),
-        ///  GPIO port input data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Port input data (y = 0..15)
-            IDR0: u1,
-            ///  Port input data (y = 0..15)
-            IDR1: u1,
-            ///  Port input data (y = 0..15)
-            IDR2: u1,
-            ///  Port input data (y = 0..15)
-            IDR3: u1,
-            ///  Port input data (y = 0..15)
-            IDR4: u1,
-            ///  Port input data (y = 0..15)
-            IDR5: u1,
-            ///  Port input data (y = 0..15)
-            IDR6: u1,
-            ///  Port input data (y = 0..15)
-            IDR7: u1,
-            ///  Port input data (y = 0..15)
-            IDR8: u1,
-            ///  Port input data (y = 0..15)
-            IDR9: u1,
-            ///  Port input data (y = 0..15)
-            IDR10: u1,
-            ///  Port input data (y = 0..15)
-            IDR11: u1,
-            ///  Port input data (y = 0..15)
-            IDR12: u1,
-            ///  Port input data (y = 0..15)
-            IDR13: u1,
-            ///  Port input data (y = 0..15)
-            IDR14: u1,
-            ///  Port input data (y = 0..15)
-            IDR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output data register
-        ODR: mmio.Mmio(packed struct(u32) {
-            ///  Port output data (y = 0..15)
-            ODR0: u1,
-            ///  Port output data (y = 0..15)
-            ODR1: u1,
-            ///  Port output data (y = 0..15)
-            ODR2: u1,
-            ///  Port output data (y = 0..15)
-            ODR3: u1,
-            ///  Port output data (y = 0..15)
-            ODR4: u1,
-            ///  Port output data (y = 0..15)
-            ODR5: u1,
-            ///  Port output data (y = 0..15)
-            ODR6: u1,
-            ///  Port output data (y = 0..15)
-            ODR7: u1,
-            ///  Port output data (y = 0..15)
-            ODR8: u1,
-            ///  Port output data (y = 0..15)
-            ODR9: u1,
-            ///  Port output data (y = 0..15)
-            ODR10: u1,
-            ///  Port output data (y = 0..15)
-            ODR11: u1,
-            ///  Port output data (y = 0..15)
-            ODR12: u1,
-            ///  Port output data (y = 0..15)
-            ODR13: u1,
-            ///  Port output data (y = 0..15)
-            ODR14: u1,
-            ///  Port output data (y = 0..15)
-            ODR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port bit set/reset register
-        BSRR: mmio.Mmio(packed struct(u32) {
-            ///  Port x set bit y (y= 0..15)
-            BS0: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS1: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS2: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS3: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS4: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS5: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS6: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS7: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS8: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS9: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS10: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS11: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS12: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS13: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS14: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS15: u1,
-            ///  Port x set bit y (y= 0..15)
-            BR0: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR1: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR2: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR3: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR4: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR5: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR6: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR7: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR8: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR9: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR10: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR11: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR12: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR13: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR14: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR15: u1,
-        }),
-        ///  GPIO port configuration lock register
-        LCKR: mmio.Mmio(packed struct(u32) {
-            ///  Port x lock bit y (y= 0..15)
-            LCK0: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK1: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK2: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK3: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK4: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK5: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK6: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK7: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK8: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK9: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK10: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK11: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK12: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK13: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK14: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK15: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCKK: u1,
-            padding: u15,
-        }),
-        ///  GPIO alternate function low register
-        AFRL: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL0: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL1: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL2: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL3: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL4: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL5: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL6: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL7: u4,
-        }),
-        ///  GPIO alternate function high register
-        AFRH: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH8: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH9: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH10: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH11: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH12: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH13: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH14: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH15: u4,
-        }),
-    };
-
-    ///  System configuration controller
-    pub const SYSCFG = extern struct {
-        ///  memory remap register
-        MEMRM: mmio.Mmio(packed struct(u32) {
-            ///  MEM_MODE
-            MEM_MODE: u2,
-            padding: u30,
-        }),
-        ///  peripheral mode configuration register
-        PMC: mmio.Mmio(packed struct(u32) {
-            reserved23: u23,
-            ///  Ethernet PHY interface selection
-            MII_RMII_SEL: u1,
-            padding: u8,
-        }),
-        ///  external interrupt configuration register 1
-        EXTICR1: mmio.Mmio(packed struct(u32) {
-            ///  EXTI x configuration (x = 0 to 3)
-            EXTI0: u4,
-            ///  EXTI x configuration (x = 0 to 3)
-            EXTI1: u4,
-            ///  EXTI x configuration (x = 0 to 3)
-            EXTI2: u4,
-            ///  EXTI x configuration (x = 0 to 3)
-            EXTI3: u4,
-            padding: u16,
-        }),
-        ///  external interrupt configuration register 2
-        EXTICR2: mmio.Mmio(packed struct(u32) {
-            ///  EXTI x configuration (x = 4 to 7)
-            EXTI4: u4,
-            ///  EXTI x configuration (x = 4 to 7)
-            EXTI5: u4,
-            ///  EXTI x configuration (x = 4 to 7)
-            EXTI6: u4,
-            ///  EXTI x configuration (x = 4 to 7)
-            EXTI7: u4,
-            padding: u16,
-        }),
-        ///  external interrupt configuration register 3
-        EXTICR3: mmio.Mmio(packed struct(u32) {
-            ///  EXTI x configuration (x = 8 to 11)
-            EXTI8: u4,
-            ///  EXTI x configuration (x = 8 to 11)
-            EXTI9: u4,
-            ///  EXTI10
-            EXTI10: u4,
-            ///  EXTI x configuration (x = 8 to 11)
-            EXTI11: u4,
-            padding: u16,
-        }),
-        ///  external interrupt configuration register 4
-        EXTICR4: mmio.Mmio(packed struct(u32) {
-            ///  EXTI x configuration (x = 12 to 15)
-            EXTI12: u4,
-            ///  EXTI x configuration (x = 12 to 15)
-            EXTI13: u4,
-            ///  EXTI x configuration (x = 12 to 15)
-            EXTI14: u4,
-            ///  EXTI x configuration (x = 12 to 15)
-            EXTI15: u4,
-            padding: u16,
-        }),
-        reserved32: [8]u8,
-        ///  Compensation cell control register
-        CMPCR: mmio.Mmio(packed struct(u32) {
-            ///  Compensation cell power-down
-            CMP_PD: u1,
-            reserved8: u7,
-            ///  READY
-            READY: u1,
-            padding: u23,
-        }),
-    };
-
-    ///  Serial peripheral interface
-    pub const SPI1 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Clock phase
-            CPHA: u1,
-            ///  Clock polarity
-            CPOL: u1,
-            ///  Master selection
-            MSTR: u1,
-            ///  Baud rate control
-            BR: u3,
-            ///  SPI enable
-            SPE: u1,
-            ///  Frame format
-            LSBFIRST: u1,
-            ///  Internal slave select
-            SSI: u1,
-            ///  Software slave management
-            SSM: u1,
-            ///  Receive only
-            RXONLY: u1,
-            ///  Data frame format
-            DFF: u1,
-            ///  CRC transfer next
-            CRCNEXT: u1,
-            ///  Hardware CRC calculation enable
-            CRCEN: u1,
-            ///  Output enable in bidirectional mode
-            BIDIOE: u1,
-            ///  Bidirectional data mode enable
-            BIDIMODE: u1,
-            padding: u16,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Rx buffer DMA enable
-            RXDMAEN: u1,
-            ///  Tx buffer DMA enable
-            TXDMAEN: u1,
-            ///  SS output enable
-            SSOE: u1,
-            reserved4: u1,
-            ///  Frame format
-            FRF: u1,
-            ///  Error interrupt enable
-            ERRIE: u1,
-            ///  RX buffer not empty interrupt enable
-            RXNEIE: u1,
-            ///  Tx buffer empty interrupt enable
-            TXEIE: u1,
-            padding: u24,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Receive buffer not empty
-            RXNE: u1,
-            ///  Transmit buffer empty
-            TXE: u1,
-            ///  Channel side
-            CHSIDE: u1,
-            ///  Underrun flag
-            UDR: u1,
-            ///  CRC error flag
-            CRCERR: u1,
-            ///  Mode fault
-            MODF: u1,
-            ///  Overrun flag
-            OVR: u1,
-            ///  Busy flag
-            BSY: u1,
-            ///  TI frame format error
-            TIFRFE: u1,
-            padding: u23,
-        }),
-        ///  data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data register
-            DR: u16,
-            padding: u16,
-        }),
-        ///  CRC polynomial register
-        CRCPR: mmio.Mmio(packed struct(u32) {
-            ///  CRC polynomial register
-            CRCPOLY: u16,
-            padding: u16,
-        }),
-        ///  RX CRC register
-        RXCRCR: mmio.Mmio(packed struct(u32) {
-            ///  Rx CRC register
-            RxCRC: u16,
-            padding: u16,
-        }),
-        ///  TX CRC register
-        TXCRCR: mmio.Mmio(packed struct(u32) {
-            ///  Tx CRC register
-            TxCRC: u16,
-            padding: u16,
-        }),
-        ///  I2S configuration register
-        I2SCFGR: mmio.Mmio(packed struct(u32) {
-            ///  Channel length (number of bits per audio channel)
-            CHLEN: u1,
-            ///  Data length to be transferred
-            DATLEN: u2,
-            ///  Steady state clock polarity
-            CKPOL: u1,
-            ///  I2S standard selection
-            I2SSTD: u2,
-            reserved7: u1,
-            ///  PCM frame synchronization
-            PCMSYNC: u1,
-            ///  I2S configuration mode
-            I2SCFG: u2,
-            ///  I2S Enable
-            I2SE: u1,
-            ///  I2S mode selection
-            I2SMOD: u1,
-            padding: u20,
-        }),
-        ///  I2S prescaler register
-        I2SPR: mmio.Mmio(packed struct(u32) {
-            ///  I2S Linear prescaler
-            I2SDIV: u8,
-            ///  Odd factor for the prescaler
-            ODD: u1,
-            ///  Master clock output enable
-            MCKOE: u1,
-            padding: u22,
-        }),
-    };
-
-    ///  LCD-TFT Controller
-    pub const LTDC = extern struct {
-        reserved8: [8]u8,
-        ///  Synchronization Size Configuration Register
-        SSCR: mmio.Mmio(packed struct(u32) {
-            ///  Vertical Synchronization Height (in units of horizontal scan line)
-            VSH: u11,
-            reserved16: u5,
-            ///  Horizontal Synchronization Width (in units of pixel clock period)
-            HSW: u10,
-            padding: u6,
-        }),
-        ///  Back Porch Configuration Register
-        BPCR: mmio.Mmio(packed struct(u32) {
-            ///  Accumulated Vertical back porch (in units of horizontal scan line)
-            AVBP: u11,
-            reserved16: u5,
-            ///  Accumulated Horizontal back porch (in units of pixel clock period)
-            AHBP: u10,
-            padding: u6,
-        }),
-        ///  Active Width Configuration Register
-        AWCR: mmio.Mmio(packed struct(u32) {
-            ///  Accumulated Active Height (in units of horizontal scan line)
-            AAH: u11,
-            reserved16: u5,
-            ///  AAV
-            AAV: u10,
-            padding: u6,
-        }),
-        ///  Total Width Configuration Register
-        TWCR: mmio.Mmio(packed struct(u32) {
-            ///  Total Height (in units of horizontal scan line)
-            TOTALH: u11,
-            reserved16: u5,
-            ///  Total Width (in units of pixel clock period)
-            TOTALW: u10,
-            padding: u6,
-        }),
-        ///  Global Control Register
-        GCR: mmio.Mmio(packed struct(u32) {
-            ///  LCD-TFT controller enable bit
-            LTDCEN: u1,
-            reserved4: u3,
-            ///  Dither Blue Width
-            DBW: u3,
-            reserved8: u1,
-            ///  Dither Green Width
-            DGW: u3,
-            reserved12: u1,
-            ///  Dither Red Width
-            DRW: u3,
-            reserved16: u1,
-            ///  Dither Enable
-            DEN: u1,
-            reserved28: u11,
-            ///  Pixel Clock Polarity
-            PCPOL: u1,
-            ///  Data Enable Polarity
-            DEPOL: u1,
-            ///  Vertical Synchronization Polarity
-            VSPOL: u1,
-            ///  Horizontal Synchronization Polarity
-            HSPOL: u1,
-        }),
-        reserved36: [8]u8,
-        ///  Shadow Reload Configuration Register
-        SRCR: mmio.Mmio(packed struct(u32) {
-            ///  Immediate Reload
-            IMR: u1,
-            ///  Vertical Blanking Reload
-            VBR: u1,
-            padding: u30,
-        }),
-        reserved44: [4]u8,
-        ///  Background Color Configuration Register
-        BCCR: mmio.Mmio(packed struct(u32) {
-            ///  Background Color Red value
-            BC: u24,
-            padding: u8,
-        }),
-        reserved52: [4]u8,
-        ///  Interrupt Enable Register
-        IER: mmio.Mmio(packed struct(u32) {
-            ///  Line Interrupt Enable
-            LIE: u1,
-            ///  FIFO Underrun Interrupt Enable
-            FUIE: u1,
-            ///  Transfer Error Interrupt Enable
-            TERRIE: u1,
-            ///  Register Reload interrupt enable
-            RRIE: u1,
-            padding: u28,
-        }),
-        ///  Interrupt Status Register
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  Line Interrupt flag
-            LIF: u1,
-            ///  FIFO Underrun Interrupt flag
-            FUIF: u1,
-            ///  Transfer Error interrupt flag
-            TERRIF: u1,
-            ///  Register Reload Interrupt Flag
-            RRIF: u1,
-            padding: u28,
-        }),
-        ///  Interrupt Clear Register
-        ICR: mmio.Mmio(packed struct(u32) {
-            ///  Clears the Line Interrupt Flag
-            CLIF: u1,
-            ///  Clears the FIFO Underrun Interrupt flag
-            CFUIF: u1,
-            ///  Clears the Transfer Error Interrupt Flag
-            CTERRIF: u1,
-            ///  Clears Register Reload Interrupt Flag
-            CRRIF: u1,
-            padding: u28,
-        }),
-        ///  Line Interrupt Position Configuration Register
-        LIPCR: mmio.Mmio(packed struct(u32) {
-            ///  Line Interrupt Position
-            LIPOS: u11,
-            padding: u21,
-        }),
-        ///  Current Position Status Register
-        CPSR: mmio.Mmio(packed struct(u32) {
-            ///  Current Y Position
-            CYPOS: u16,
-            ///  Current X Position
-            CXPOS: u16,
-        }),
-        ///  Current Display Status Register
-        CDSR: mmio.Mmio(packed struct(u32) {
-            ///  Vertical Data Enable display Status
-            VDES: u1,
-            ///  Horizontal Data Enable display Status
-            HDES: u1,
-            ///  Vertical Synchronization display Status
-            VSYNCS: u1,
-            ///  Horizontal Synchronization display Status
-            HSYNCS: u1,
-            padding: u28,
-        }),
-        reserved132: [56]u8,
-        ///  Layerx Control Register
-        L1CR: mmio.Mmio(packed struct(u32) {
-            ///  Layer Enable
-            LEN: u1,
-            ///  Color Keying Enable
-            COLKEN: u1,
-            reserved4: u2,
-            ///  Color Look-Up Table Enable
-            CLUTEN: u1,
-            padding: u27,
-        }),
-        ///  Layerx Window Horizontal Position Configuration Register
-        L1WHPCR: mmio.Mmio(packed struct(u32) {
-            ///  Window Horizontal Start Position
-            WHSTPOS: u12,
-            reserved16: u4,
-            ///  Window Horizontal Stop Position
-            WHSPPOS: u12,
-            padding: u4,
-        }),
-        ///  Layerx Window Vertical Position Configuration Register
-        L1WVPCR: mmio.Mmio(packed struct(u32) {
-            ///  Window Vertical Start Position
-            WVSTPOS: u11,
-            reserved16: u5,
-            ///  Window Vertical Stop Position
-            WVSPPOS: u11,
-            padding: u5,
-        }),
-        ///  Layerx Color Keying Configuration Register
-        L1CKCR: mmio.Mmio(packed struct(u32) {
-            ///  Color Key Blue value
-            CKBLUE: u8,
-            ///  Color Key Green value
-            CKGREEN: u8,
-            ///  Color Key Red value
-            CKRED: u8,
-            padding: u8,
-        }),
-        ///  Layerx Pixel Format Configuration Register
-        L1PFCR: mmio.Mmio(packed struct(u32) {
-            ///  Pixel Format
-            PF: u3,
-            padding: u29,
-        }),
-        ///  Layerx Constant Alpha Configuration Register
-        L1CACR: mmio.Mmio(packed struct(u32) {
-            ///  Constant Alpha
-            CONSTA: u8,
-            padding: u24,
-        }),
-        ///  Layerx Default Color Configuration Register
-        L1DCCR: mmio.Mmio(packed struct(u32) {
-            ///  Default Color Blue
-            DCBLUE: u8,
-            ///  Default Color Green
-            DCGREEN: u8,
-            ///  Default Color Red
-            DCRED: u8,
-            ///  Default Color Alpha
-            DCALPHA: u8,
-        }),
-        ///  Layerx Blending Factors Configuration Register
-        L1BFCR: mmio.Mmio(packed struct(u32) {
-            ///  Blending Factor 2
-            BF2: u3,
-            reserved8: u5,
-            ///  Blending Factor 1
-            BF1: u3,
-            padding: u21,
-        }),
-        reserved172: [8]u8,
-        ///  Layerx Color Frame Buffer Address Register
-        L1CFBAR: mmio.Mmio(packed struct(u32) {
-            ///  Color Frame Buffer Start Address
-            CFBADD: u32,
-        }),
-        ///  Layerx Color Frame Buffer Length Register
-        L1CFBLR: mmio.Mmio(packed struct(u32) {
-            ///  Color Frame Buffer Line Length
-            CFBLL: u13,
-            reserved16: u3,
-            ///  Color Frame Buffer Pitch in bytes
-            CFBP: u13,
-            padding: u3,
-        }),
-        ///  Layerx ColorFrame Buffer Line Number Register
-        L1CFBLNR: mmio.Mmio(packed struct(u32) {
-            ///  Frame Buffer Line Number
-            CFBLNBR: u11,
-            padding: u21,
-        }),
-        reserved196: [12]u8,
-        ///  Layerx CLUT Write Register
-        L1CLUTWR: mmio.Mmio(packed struct(u32) {
-            ///  Blue value
-            BLUE: u8,
-            ///  Green value
-            GREEN: u8,
-            ///  Red value
-            RED: u8,
-            ///  CLUT Address
-            CLUTADD: u8,
-        }),
-        reserved260: [60]u8,
-        ///  Layerx Control Register
-        L2CR: mmio.Mmio(packed struct(u32) {
-            ///  Layer Enable
-            LEN: u1,
-            ///  Color Keying Enable
-            COLKEN: u1,
-            reserved4: u2,
-            ///  Color Look-Up Table Enable
-            CLUTEN: u1,
-            padding: u27,
-        }),
-        ///  Layerx Window Horizontal Position Configuration Register
-        L2WHPCR: mmio.Mmio(packed struct(u32) {
-            ///  Window Horizontal Start Position
-            WHSTPOS: u12,
-            reserved16: u4,
-            ///  Window Horizontal Stop Position
-            WHSPPOS: u12,
-            padding: u4,
-        }),
-        ///  Layerx Window Vertical Position Configuration Register
-        L2WVPCR: mmio.Mmio(packed struct(u32) {
-            ///  Window Vertical Start Position
-            WVSTPOS: u11,
-            reserved16: u5,
-            ///  Window Vertical Stop Position
-            WVSPPOS: u11,
-            padding: u5,
-        }),
-        ///  Layerx Color Keying Configuration Register
-        L2CKCR: mmio.Mmio(packed struct(u32) {
-            ///  Color Key Blue value
-            CKBLUE: u8,
-            ///  Color Key Green value
-            CKGREEN: u7,
-            ///  Color Key Red value
-            CKRED: u9,
-            padding: u8,
-        }),
-        ///  Layerx Pixel Format Configuration Register
-        L2PFCR: mmio.Mmio(packed struct(u32) {
-            ///  Pixel Format
-            PF: u3,
-            padding: u29,
-        }),
-        ///  Layerx Constant Alpha Configuration Register
-        L2CACR: mmio.Mmio(packed struct(u32) {
-            ///  Constant Alpha
-            CONSTA: u8,
-            padding: u24,
-        }),
-        ///  Layerx Default Color Configuration Register
-        L2DCCR: mmio.Mmio(packed struct(u32) {
-            ///  Default Color Blue
-            DCBLUE: u8,
-            ///  Default Color Green
-            DCGREEN: u8,
-            ///  Default Color Red
-            DCRED: u8,
-            ///  Default Color Alpha
-            DCALPHA: u8,
-        }),
-        ///  Layerx Blending Factors Configuration Register
-        L2BFCR: mmio.Mmio(packed struct(u32) {
-            ///  Blending Factor 2
-            BF2: u3,
-            reserved8: u5,
-            ///  Blending Factor 1
-            BF1: u3,
-            padding: u21,
-        }),
-        reserved300: [8]u8,
-        ///  Layerx Color Frame Buffer Address Register
-        L2CFBAR: mmio.Mmio(packed struct(u32) {
-            ///  Color Frame Buffer Start Address
-            CFBADD: u32,
-        }),
-        ///  Layerx Color Frame Buffer Length Register
-        L2CFBLR: mmio.Mmio(packed struct(u32) {
-            ///  Color Frame Buffer Line Length
-            CFBLL: u13,
-            reserved16: u3,
-            ///  Color Frame Buffer Pitch in bytes
-            CFBP: u13,
-            padding: u3,
-        }),
-        ///  Layerx ColorFrame Buffer Line Number Register
-        L2CFBLNR: mmio.Mmio(packed struct(u32) {
-            ///  Frame Buffer Line Number
-            CFBLNBR: u11,
-            padding: u21,
-        }),
-        reserved324: [12]u8,
-        ///  Layerx CLUT Write Register
-        L2CLUTWR: mmio.Mmio(packed struct(u32) {
-            ///  Blue value
-            BLUE: u8,
-            ///  Green value
-            GREEN: u8,
-            ///  Red value
-            RED: u8,
-            ///  CLUT Address
-            CLUTADD: u8,
-        }),
-    };
-
-    ///  Serial audio interface
-    pub const SAI1 = extern struct {
-        reserved4: [4]u8,
-        ///  SAI AConfiguration register 1
-        SAI_ACR1: mmio.Mmio(packed struct(u32) {
-            ///  Audio block mode
-            MODE: u2,
-            ///  Protocol configuration
-            PRTCFG: u2,
-            reserved5: u1,
-            ///  Data size
-            DS: u3,
-            ///  Least significant bit first
-            LSBFIRST: u1,
-            ///  Clock strobing edge
-            CKSTR: u1,
-            ///  Synchronization enable
-            SYNCEN: u2,
-            ///  Mono mode
-            MONO: u1,
-            ///  Output drive
-            OUTDRIV: u1,
-            reserved16: u2,
-            ///  Audio block enable
-            SAIAEN: u1,
-            ///  DMA enable
-            DMAEN: u1,
-            reserved19: u1,
-            ///  No divider
-            NODIV: u1,
-            ///  Master clock divider
-            MCKDIV: u4,
-            padding: u8,
-        }),
-        ///  SAI AConfiguration register 2
-        SAI_ACR2: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold
-            FTH: u3,
-            ///  FIFO flush
-            FFLUSH: u1,
-            ///  Tristate management on data line
-            TRIS: u1,
-            ///  Mute
-            MUTE: u1,
-            ///  Mute value
-            MUTEVAL: u1,
-            ///  Mute counter
-            MUTECNT: u6,
-            ///  Complement bit
-            CPL: u1,
-            ///  Companding mode
-            COMP: u2,
-            padding: u16,
-        }),
-        ///  SAI AFrame configuration register
-        SAI_AFRCR: mmio.Mmio(packed struct(u32) {
-            ///  Frame length
-            FRL: u8,
-            ///  Frame synchronization active level length
-            FSALL: u7,
-            reserved16: u1,
-            ///  Frame synchronization definition
-            FSDEF: u1,
-            ///  Frame synchronization polarity
-            FSPOL: u1,
-            ///  Frame synchronization offset
-            FSOFF: u1,
-            padding: u13,
-        }),
-        ///  SAI ASlot register
-        SAI_ASLOTR: mmio.Mmio(packed struct(u32) {
-            ///  First bit offset
-            FBOFF: u5,
-            reserved6: u1,
-            ///  Slot size
-            SLOTSZ: u2,
-            ///  Number of slots in an audio frame
-            NBSLOT: u4,
-            reserved16: u4,
-            ///  Slot enable
-            SLOTEN: u16,
-        }),
-        ///  SAI AInterrupt mask register2
-        SAI_AIM: mmio.Mmio(packed struct(u32) {
-            ///  Overrun/underrun interrupt enable
-            OVRUDRIE: u1,
-            ///  Mute detection interrupt enable
-            MUTEDETIE: u1,
-            ///  Wrong clock configuration interrupt enable
-            WCKCFGIE: u1,
-            ///  FIFO request interrupt enable
-            FREQIE: u1,
-            ///  Codec not ready interrupt enable
-            CNRDYIE: u1,
-            ///  Anticipated frame synchronization detection interrupt enable
-            AFSDETIE: u1,
-            ///  Late frame synchronization detection interrupt enable
-            LFSDETIE: u1,
-            padding: u25,
-        }),
-        ///  SAI AStatus register
-        SAI_ASR: mmio.Mmio(packed struct(u32) {
-            ///  Overrun / underrun
-            OVRUDR: u1,
-            ///  Mute detection
-            MUTEDET: u1,
-            ///  Wrong clock configuration flag
-            WCKCFG: u1,
-            ///  FIFO request
-            FREQ: u1,
-            ///  Codec not ready
-            CNRDY: u1,
-            ///  Anticipated frame synchronization detection
-            AFSDET: u1,
-            ///  Late frame synchronization detection
-            LFSDET: u1,
-            reserved16: u9,
-            ///  FIFO level threshold
-            FLTH: u3,
-            padding: u13,
-        }),
-        ///  SAI AClear flag register
-        SAI_ACLRFR: mmio.Mmio(packed struct(u32) {
-            ///  Clear overrun / underrun
-            COVRUDR: u1,
-            ///  Mute detection flag
-            CMUTEDET: u1,
-            ///  Clear wrong clock configuration flag
-            CWCKCFG: u1,
-            reserved4: u1,
-            ///  Clear codec not ready flag
-            CCNRDY: u1,
-            ///  Clear anticipated frame synchronization detection flag
-            CAFSDET: u1,
-            ///  Clear late frame synchronization detection flag
-            CLFSDET: u1,
-            padding: u25,
-        }),
-        ///  SAI AData register
-        SAI_ADR: mmio.Mmio(packed struct(u32) {
-            ///  Data
-            DATA: u32,
-        }),
-        ///  SAI BConfiguration register 1
-        SAI_BCR1: mmio.Mmio(packed struct(u32) {
-            ///  Audio block mode
-            MODE: u2,
-            ///  Protocol configuration
-            PRTCFG: u2,
-            reserved5: u1,
-            ///  Data size
-            DS: u3,
-            ///  Least significant bit first
-            LSBFIRST: u1,
-            ///  Clock strobing edge
-            CKSTR: u1,
-            ///  Synchronization enable
-            SYNCEN: u2,
-            ///  Mono mode
-            MONO: u1,
-            ///  Output drive
-            OUTDRIV: u1,
-            reserved16: u2,
-            ///  Audio block enable
-            SAIBEN: u1,
-            ///  DMA enable
-            DMAEN: u1,
-            reserved19: u1,
-            ///  No divider
-            NODIV: u1,
-            ///  Master clock divider
-            MCKDIV: u4,
-            padding: u8,
-        }),
-        ///  SAI BConfiguration register 2
-        SAI_BCR2: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold
-            FTH: u3,
-            ///  FIFO flush
-            FFLUSH: u1,
-            ///  Tristate management on data line
-            TRIS: u1,
-            ///  Mute
-            MUTE: u1,
-            ///  Mute value
-            MUTEVAL: u1,
-            ///  Mute counter
-            MUTECNT: u6,
-            ///  Complement bit
-            CPL: u1,
-            ///  Companding mode
-            COMP: u2,
-            padding: u16,
-        }),
-        ///  SAI BFrame configuration register
-        SAI_BFRCR: mmio.Mmio(packed struct(u32) {
-            ///  Frame length
-            FRL: u8,
-            ///  Frame synchronization active level length
-            FSALL: u7,
-            reserved16: u1,
-            ///  Frame synchronization definition
-            FSDEF: u1,
-            ///  Frame synchronization polarity
-            FSPOL: u1,
-            ///  Frame synchronization offset
-            FSOFF: u1,
-            padding: u13,
-        }),
-        ///  SAI BSlot register
-        SAI_BSLOTR: mmio.Mmio(packed struct(u32) {
-            ///  First bit offset
-            FBOFF: u5,
-            reserved6: u1,
-            ///  Slot size
-            SLOTSZ: u2,
-            ///  Number of slots in an audio frame
-            NBSLOT: u4,
-            reserved16: u4,
-            ///  Slot enable
-            SLOTEN: u16,
-        }),
-        ///  SAI BInterrupt mask register2
-        SAI_BIM: mmio.Mmio(packed struct(u32) {
-            ///  Overrun/underrun interrupt enable
-            OVRUDRIE: u1,
-            ///  Mute detection interrupt enable
-            MUTEDETIE: u1,
-            ///  Wrong clock configuration interrupt enable
-            WCKCFGIE: u1,
-            ///  FIFO request interrupt enable
-            FREQIE: u1,
-            ///  Codec not ready interrupt enable
-            CNRDYIE: u1,
-            ///  Anticipated frame synchronization detection interrupt enable
-            AFSDETIE: u1,
-            ///  Late frame synchronization detection interrupt enable
-            LFSDETIE: u1,
-            padding: u25,
-        }),
-        ///  SAI BStatus register
-        SAI_BSR: mmio.Mmio(packed struct(u32) {
-            ///  Overrun / underrun
-            OVRUDR: u1,
-            ///  Mute detection
-            MUTEDET: u1,
-            ///  Wrong clock configuration flag
-            WCKCFG: u1,
-            ///  FIFO request
-            FREQ: u1,
-            ///  Codec not ready
-            CNRDY: u1,
-            ///  Anticipated frame synchronization detection
-            AFSDET: u1,
-            ///  Late frame synchronization detection
-            LFSDET: u1,
-            reserved16: u9,
-            ///  FIFO level threshold
-            FLTH: u3,
-            padding: u13,
-        }),
-        ///  SAI BClear flag register
-        SAI_BCLRFR: mmio.Mmio(packed struct(u32) {
-            ///  Clear overrun / underrun
-            COVRUDR: u1,
-            ///  Mute detection flag
-            CMUTEDET: u1,
-            ///  Clear wrong clock configuration flag
-            CWCKCFG: u1,
-            reserved4: u1,
-            ///  Clear codec not ready flag
-            CCNRDY: u1,
-            ///  Clear anticipated frame synchronization detection flag
-            CAFSDET: u1,
-            ///  Clear late frame synchronization detection flag
-            CLFSDET: u1,
-            padding: u25,
-        }),
-        ///  SAI BData register
-        SAI_BDR: mmio.Mmio(packed struct(u32) {
-            ///  Data
-            DATA: u32,
-        }),
-    };
-
-    ///  Nested Vectored Interrupt Controller
-    pub const NVIC = extern struct {
-        ///  Interrupt Set-Enable Register
-        ISER0: mmio.Mmio(packed struct(u32) {
-            ///  SETENA
-            SETENA: u32,
-        }),
-        ///  Interrupt Set-Enable Register
-        ISER1: mmio.Mmio(packed struct(u32) {
-            ///  SETENA
-            SETENA: u32,
-        }),
-        ///  Interrupt Set-Enable Register
-        ISER2: mmio.Mmio(packed struct(u32) {
-            ///  SETENA
-            SETENA: u32,
-        }),
-        reserved128: [116]u8,
-        ///  Interrupt Clear-Enable Register
-        ICER0: mmio.Mmio(packed struct(u32) {
-            ///  CLRENA
-            CLRENA: u32,
-        }),
-        ///  Interrupt Clear-Enable Register
-        ICER1: mmio.Mmio(packed struct(u32) {
-            ///  CLRENA
-            CLRENA: u32,
-        }),
-        ///  Interrupt Clear-Enable Register
-        ICER2: mmio.Mmio(packed struct(u32) {
-            ///  CLRENA
-            CLRENA: u32,
-        }),
-        reserved256: [116]u8,
-        ///  Interrupt Set-Pending Register
-        ISPR0: mmio.Mmio(packed struct(u32) {
-            ///  SETPEND
-            SETPEND: u32,
-        }),
-        ///  Interrupt Set-Pending Register
-        ISPR1: mmio.Mmio(packed struct(u32) {
-            ///  SETPEND
-            SETPEND: u32,
-        }),
-        ///  Interrupt Set-Pending Register
-        ISPR2: mmio.Mmio(packed struct(u32) {
-            ///  SETPEND
-            SETPEND: u32,
-        }),
-        reserved384: [116]u8,
-        ///  Interrupt Clear-Pending Register
-        ICPR0: mmio.Mmio(packed struct(u32) {
-            ///  CLRPEND
-            CLRPEND: u32,
-        }),
-        ///  Interrupt Clear-Pending Register
-        ICPR1: mmio.Mmio(packed struct(u32) {
-            ///  CLRPEND
-            CLRPEND: u32,
-        }),
-        ///  Interrupt Clear-Pending Register
-        ICPR2: mmio.Mmio(packed struct(u32) {
-            ///  CLRPEND
-            CLRPEND: u32,
-        }),
-        reserved512: [116]u8,
-        ///  Interrupt Active Bit Register
-        IABR0: mmio.Mmio(packed struct(u32) {
-            ///  ACTIVE
-            ACTIVE: u32,
-        }),
-        ///  Interrupt Active Bit Register
-        IABR1: mmio.Mmio(packed struct(u32) {
-            ///  ACTIVE
-            ACTIVE: u32,
-        }),
-        ///  Interrupt Active Bit Register
-        IABR2: mmio.Mmio(packed struct(u32) {
-            ///  ACTIVE
-            ACTIVE: u32,
-        }),
-        reserved768: [244]u8,
-        ///  Interrupt Priority Register
-        IPR0: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR1: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR2: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR3: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR4: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR5: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR6: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR7: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR8: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR9: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR10: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR11: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR12: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR13: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR14: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR15: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR16: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR17: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR18: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR19: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-    };
-
-    ///  USB on the go high speed
-    pub const OTG_HS_PWRCLK = extern struct {
-        ///  Power and clock gating control register
-        OTG_HS_PCGCR: mmio.Mmio(packed struct(u32) {
-            ///  Stop PHY clock
-            STPPCLK: u1,
-            ///  Gate HCLK
-            GATEHCLK: u1,
-            reserved4: u2,
-            ///  PHY suspended
-            PHYSUSP: u1,
-            padding: u27,
-        }),
-    };
-
-    ///  USB on the go high speed
-    pub const OTG_HS_DEVICE = extern struct {
-        ///  OTG_HS device configuration register
-        OTG_HS_DCFG: mmio.Mmio(packed struct(u32) {
-            ///  Device speed
-            DSPD: u2,
-            ///  Nonzero-length status OUT handshake
-            NZLSOHSK: u1,
-            reserved4: u1,
-            ///  Device address
-            DAD: u7,
-            ///  Periodic (micro)frame interval
-            PFIVL: u2,
-            reserved24: u11,
-            ///  Periodic scheduling interval
-            PERSCHIVL: u2,
-            padding: u6,
-        }),
-        ///  OTG_HS device control register
-        OTG_HS_DCTL: mmio.Mmio(packed struct(u32) {
-            ///  Remote wakeup signaling
-            RWUSIG: u1,
-            ///  Soft disconnect
-            SDIS: u1,
-            ///  Global IN NAK status
-            GINSTS: u1,
-            ///  Global OUT NAK status
-            GONSTS: u1,
-            ///  Test control
-            TCTL: u3,
-            ///  Set global IN NAK
-            SGINAK: u1,
-            ///  Clear global IN NAK
-            CGINAK: u1,
-            ///  Set global OUT NAK
-            SGONAK: u1,
-            ///  Clear global OUT NAK
-            CGONAK: u1,
-            ///  Power-on programming done
-            POPRGDNE: u1,
-            padding: u20,
-        }),
-        ///  OTG_HS device status register
-        OTG_HS_DSTS: mmio.Mmio(packed struct(u32) {
-            ///  Suspend status
-            SUSPSTS: u1,
-            ///  Enumerated speed
-            ENUMSPD: u2,
-            ///  Erratic error
-            EERR: u1,
-            reserved8: u4,
-            ///  Frame number of the received SOF
-            FNSOF: u14,
-            padding: u10,
-        }),
-        reserved16: [4]u8,
-        ///  OTG_HS device IN endpoint common interrupt mask register
-        OTG_HS_DIEPMSK: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  Timeout condition mask (nonisochronous endpoints)
-            TOM: u1,
-            ///  IN token received when TxFIFO empty mask
-            ITTXFEMSK: u1,
-            ///  IN token received with EP mismatch mask
-            INEPNMM: u1,
-            ///  IN endpoint NAK effective mask
-            INEPNEM: u1,
-            reserved8: u1,
-            ///  FIFO underrun mask
-            TXFURM: u1,
-            ///  BNA interrupt mask
-            BIM: u1,
-            padding: u22,
-        }),
-        ///  OTG_HS device OUT endpoint common interrupt mask register
-        OTG_HS_DOEPMSK: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  SETUP phase done mask
-            STUPM: u1,
-            ///  OUT token received when endpoint disabled mask
-            OTEPDM: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received mask
-            B2BSTUP: u1,
-            reserved8: u1,
-            ///  OUT packet error mask
-            OPEM: u1,
-            ///  BNA interrupt mask
-            BOIM: u1,
-            padding: u22,
-        }),
-        ///  OTG_HS device all endpoints interrupt register
-        OTG_HS_DAINT: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint interrupt bits
-            IEPINT: u16,
-            ///  OUT endpoint interrupt bits
-            OEPINT: u16,
-        }),
-        ///  OTG_HS all endpoints interrupt mask register
-        OTG_HS_DAINTMSK: mmio.Mmio(packed struct(u32) {
-            ///  IN EP interrupt mask bits
-            IEPM: u16,
-            ///  OUT EP interrupt mask bits
-            OEPM: u16,
-        }),
-        reserved40: [8]u8,
-        ///  OTG_HS device VBUS discharge time register
-        OTG_HS_DVBUSDIS: mmio.Mmio(packed struct(u32) {
-            ///  Device VBUS discharge time
-            VBUSDT: u16,
-            padding: u16,
-        }),
-        ///  OTG_HS device VBUS pulsing time register
-        OTG_HS_DVBUSPULSE: mmio.Mmio(packed struct(u32) {
-            ///  Device VBUS pulsing time
-            DVBUSP: u12,
-            padding: u20,
-        }),
-        ///  OTG_HS Device threshold control register
-        OTG_HS_DTHRCTL: mmio.Mmio(packed struct(u32) {
-            ///  Nonisochronous IN endpoints threshold enable
-            NONISOTHREN: u1,
-            ///  ISO IN endpoint threshold enable
-            ISOTHREN: u1,
-            ///  Transmit threshold length
-            TXTHRLEN: u9,
-            reserved16: u5,
-            ///  Receive threshold enable
-            RXTHREN: u1,
-            ///  Receive threshold length
-            RXTHRLEN: u9,
-            reserved27: u1,
-            ///  Arbiter parking enable
-            ARPEN: u1,
-            padding: u4,
-        }),
-        ///  OTG_HS device IN endpoint FIFO empty interrupt mask register
-        OTG_HS_DIEPEMPMSK: mmio.Mmio(packed struct(u32) {
-            ///  IN EP Tx FIFO empty interrupt mask bits
-            INEPTXFEM: u16,
-            padding: u16,
-        }),
-        ///  OTG_HS device each endpoint interrupt register
-        OTG_HS_DEACHINT: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  IN endpoint 1interrupt bit
-            IEP1INT: u1,
-            reserved17: u15,
-            ///  OUT endpoint 1 interrupt bit
-            OEP1INT: u1,
-            padding: u14,
-        }),
-        ///  OTG_HS device each endpoint interrupt register mask
-        OTG_HS_DEACHINTMSK: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  IN Endpoint 1 interrupt mask bit
-            IEP1INTM: u1,
-            reserved17: u15,
-            ///  OUT Endpoint 1 interrupt mask bit
-            OEP1INTM: u1,
-            padding: u14,
-        }),
-        ///  OTG_HS device each in endpoint-1 interrupt register
-        OTG_HS_DIEPEACHMSK1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  Timeout condition mask (nonisochronous endpoints)
-            TOM: u1,
-            ///  IN token received when TxFIFO empty mask
-            ITTXFEMSK: u1,
-            ///  IN token received with EP mismatch mask
-            INEPNMM: u1,
-            ///  IN endpoint NAK effective mask
-            INEPNEM: u1,
-            reserved8: u1,
-            ///  FIFO underrun mask
-            TXFURM: u1,
-            ///  BNA interrupt mask
-            BIM: u1,
-            reserved13: u3,
-            ///  NAK interrupt mask
-            NAKM: u1,
-            padding: u18,
-        }),
-        reserved128: [60]u8,
-        ///  OTG_HS device each OUT endpoint-1 interrupt register
-        OTG_HS_DOEPEACHMSK1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  Timeout condition mask
-            TOM: u1,
-            ///  IN token received when TxFIFO empty mask
-            ITTXFEMSK: u1,
-            ///  IN token received with EP mismatch mask
-            INEPNMM: u1,
-            ///  IN endpoint NAK effective mask
-            INEPNEM: u1,
-            reserved8: u1,
-            ///  OUT packet error mask
-            TXFURM: u1,
-            ///  BNA interrupt mask
-            BIM: u1,
-            reserved12: u2,
-            ///  Bubble error interrupt mask
-            BERRM: u1,
-            ///  NAK interrupt mask
-            NAKM: u1,
-            ///  NYET interrupt mask
-            NYETM: u1,
-            padding: u17,
-        }),
-        reserved256: [124]u8,
-        ///  OTG device endpoint-0 control register
-        OTG_HS_DIEPCTL0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved264: [4]u8,
-        ///  OTG device endpoint-0 interrupt register
-        OTG_HS_DIEPINT0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved272: [4]u8,
-        ///  OTG_HS device IN endpoint 0 transfer size register
-        OTG_HS_DIEPTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u7,
-            reserved19: u12,
-            ///  Packet count
-            PKTCNT: u2,
-            padding: u11,
-        }),
-        ///  OTG_HS device endpoint-1 DMA address register
-        OTG_HS_DIEPDMA1: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS0: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved288: [4]u8,
-        ///  OTG device endpoint-1 control register
-        OTG_HS_DIEPCTL1: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved296: [4]u8,
-        ///  OTG device endpoint-1 interrupt register
-        OTG_HS_DIEPINT1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved304: [4]u8,
-        ///  OTG_HS device endpoint transfer size register
-        OTG_HS_DIEPTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS device endpoint-2 DMA address register
-        OTG_HS_DIEPDMA2: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS1: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved320: [4]u8,
-        ///  OTG device endpoint-2 control register
-        OTG_HS_DIEPCTL2: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved328: [4]u8,
-        ///  OTG device endpoint-2 interrupt register
-        OTG_HS_DIEPINT2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved336: [4]u8,
-        ///  OTG_HS device endpoint transfer size register
-        OTG_HS_DIEPTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS device endpoint-3 DMA address register
-        OTG_HS_DIEPDMA3: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS2: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved352: [4]u8,
-        ///  OTG device endpoint-3 control register
-        OTG_HS_DIEPCTL3: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved360: [4]u8,
-        ///  OTG device endpoint-3 interrupt register
-        OTG_HS_DIEPINT3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved368: [4]u8,
-        ///  OTG_HS device endpoint transfer size register
-        OTG_HS_DIEPTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS device endpoint-4 DMA address register
-        OTG_HS_DIEPDMA4: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS3: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved384: [4]u8,
-        ///  OTG device endpoint-4 control register
-        OTG_HS_DIEPCTL4: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved392: [4]u8,
-        ///  OTG device endpoint-4 interrupt register
-        OTG_HS_DIEPINT4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved400: [4]u8,
-        ///  OTG_HS device endpoint transfer size register
-        OTG_HS_DIEPTSIZ4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS device endpoint-5 DMA address register
-        OTG_HS_DIEPDMA5: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS4: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved416: [4]u8,
-        ///  OTG device endpoint-5 control register
-        OTG_HS_DIEPCTL5: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved424: [4]u8,
-        ///  OTG device endpoint-5 interrupt register
-        OTG_HS_DIEPINT5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved432: [4]u8,
-        ///  OTG_HS device endpoint transfer size register
-        OTG_HS_DIEPTSIZ5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        reserved440: [4]u8,
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS5: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved448: [4]u8,
-        ///  OTG device endpoint-6 control register
-        OTG_HS_DIEPCTL6: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved456: [4]u8,
-        ///  OTG device endpoint-6 interrupt register
-        OTG_HS_DIEPINT6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved480: [20]u8,
-        ///  OTG device endpoint-7 control register
-        OTG_HS_DIEPCTL7: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved488: [4]u8,
-        ///  OTG device endpoint-7 interrupt register
-        OTG_HS_DIEPINT7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved768: [276]u8,
-        ///  OTG_HS device control OUT endpoint 0 control register
-        OTG_HS_DOEPCTL0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u2,
-            reserved15: u13,
-            ///  USB active endpoint
-            USBAEP: u1,
-            reserved17: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Snoop mode
-            SNPM: u1,
-            ///  STALL handshake
-            Stall: u1,
-            reserved26: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            reserved30: u2,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved776: [4]u8,
-        ///  OTG_HS device endpoint-0 interrupt register
-        OTG_HS_DOEPINT0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved784: [4]u8,
-        ///  OTG_HS device endpoint-1 transfer size register
-        OTG_HS_DOEPTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u7,
-            reserved19: u12,
-            ///  Packet count
-            PKTCNT: u1,
-            reserved29: u9,
-            ///  SETUP packet count
-            STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved800: [12]u8,
-        ///  OTG device endpoint-1 control register
-        OTG_HS_DOEPCTL1: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even odd frame/Endpoint data PID
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Snoop mode
-            SNPM: u1,
-            ///  STALL handshake
-            Stall: u1,
-            reserved26: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID/Set even frame
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved808: [4]u8,
-        ///  OTG_HS device endpoint-1 interrupt register
-        OTG_HS_DOEPINT1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved816: [4]u8,
-        ///  OTG_HS device endpoint-2 transfer size register
-        OTG_HS_DOEPTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved832: [12]u8,
-        ///  OTG device endpoint-2 control register
-        OTG_HS_DOEPCTL2: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even odd frame/Endpoint data PID
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Snoop mode
-            SNPM: u1,
-            ///  STALL handshake
-            Stall: u1,
-            reserved26: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID/Set even frame
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved840: [4]u8,
-        ///  OTG_HS device endpoint-2 interrupt register
-        OTG_HS_DOEPINT2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved848: [4]u8,
-        ///  OTG_HS device endpoint-3 transfer size register
-        OTG_HS_DOEPTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved864: [12]u8,
-        ///  OTG device endpoint-3 control register
-        OTG_HS_DOEPCTL3: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even odd frame/Endpoint data PID
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Snoop mode
-            SNPM: u1,
-            ///  STALL handshake
-            Stall: u1,
-            reserved26: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID/Set even frame
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved872: [4]u8,
-        ///  OTG_HS device endpoint-3 interrupt register
-        OTG_HS_DOEPINT3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved880: [4]u8,
-        ///  OTG_HS device endpoint-4 transfer size register
-        OTG_HS_DOEPTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved904: [20]u8,
-        ///  OTG_HS device endpoint-4 interrupt register
-        OTG_HS_DOEPINT4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved912: [4]u8,
-        ///  OTG_HS device endpoint-5 transfer size register
-        OTG_HS_DOEPTSIZ4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved936: [20]u8,
-        ///  OTG_HS device endpoint-5 interrupt register
-        OTG_HS_DOEPINT5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved968: [28]u8,
-        ///  OTG_HS device endpoint-6 interrupt register
-        OTG_HS_DOEPINT6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved1000: [28]u8,
-        ///  OTG_HS device endpoint-7 interrupt register
-        OTG_HS_DOEPINT7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-    };
-
-    ///  USB on the go high speed
-    pub const OTG_HS_HOST = extern struct {
-        ///  OTG_HS host configuration register
-        OTG_HS_HCFG: mmio.Mmio(packed struct(u32) {
-            ///  FS/LS PHY clock select
-            FSLSPCS: u2,
-            ///  FS- and LS-only support
-            FSLSS: u1,
-            padding: u29,
-        }),
-        ///  OTG_HS Host frame interval register
-        OTG_HS_HFIR: mmio.Mmio(packed struct(u32) {
-            ///  Frame interval
-            FRIVL: u16,
-            padding: u16,
-        }),
-        ///  OTG_HS host frame number/frame time remaining register
-        OTG_HS_HFNUM: mmio.Mmio(packed struct(u32) {
-            ///  Frame number
-            FRNUM: u16,
-            ///  Frame time remaining
-            FTREM: u16,
-        }),
-        reserved16: [4]u8,
-        ///  OTG_HS_Host periodic transmit FIFO/queue status register
-        OTG_HS_HPTXSTS: mmio.Mmio(packed struct(u32) {
-            ///  Periodic transmit data FIFO space available
-            PTXFSAVL: u16,
-            ///  Periodic transmit request queue space available
-            PTXQSAV: u8,
-            ///  Top of the periodic transmit request queue
-            PTXQTOP: u8,
-        }),
-        ///  OTG_HS Host all channels interrupt register
-        OTG_HS_HAINT: mmio.Mmio(packed struct(u32) {
-            ///  Channel interrupts
-            HAINT: u16,
-            padding: u16,
-        }),
-        ///  OTG_HS host all channels interrupt mask register
-        OTG_HS_HAINTMSK: mmio.Mmio(packed struct(u32) {
-            ///  Channel interrupt mask
-            HAINTM: u16,
-            padding: u16,
-        }),
-        reserved64: [36]u8,
-        ///  OTG_HS host port control and status register
-        OTG_HS_HPRT: mmio.Mmio(packed struct(u32) {
-            ///  Port connect status
-            PCSTS: u1,
-            ///  Port connect detected
-            PCDET: u1,
-            ///  Port enable
-            PENA: u1,
-            ///  Port enable/disable change
-            PENCHNG: u1,
-            ///  Port overcurrent active
-            POCA: u1,
-            ///  Port overcurrent change
-            POCCHNG: u1,
-            ///  Port resume
-            PRES: u1,
-            ///  Port suspend
-            PSUSP: u1,
-            ///  Port reset
-            PRST: u1,
-            reserved10: u1,
-            ///  Port line status
-            PLSTS: u2,
-            ///  Port power
-            PPWR: u1,
-            ///  Port test control
-            PTCTL: u4,
-            ///  Port speed
-            PSPD: u2,
-            padding: u13,
-        }),
-        reserved256: [188]u8,
-        ///  OTG_HS host channel-0 characteristics register
-        OTG_HS_HCCHAR0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-0 split control register
-        OTG_HS_HCSPLT0: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-11 interrupt register
-        OTG_HS_HCINT0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-11 interrupt mask register
-        OTG_HS_HCINTMSK0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-11 transfer size register
-        OTG_HS_HCTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-0 DMA address register
-        OTG_HS_HCDMA0: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved288: [8]u8,
-        ///  OTG_HS host channel-1 characteristics register
-        OTG_HS_HCCHAR1: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-1 split control register
-        OTG_HS_HCSPLT1: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-1 interrupt register
-        OTG_HS_HCINT1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-1 interrupt mask register
-        OTG_HS_HCINTMSK1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-1 transfer size register
-        OTG_HS_HCTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-1 DMA address register
-        OTG_HS_HCDMA1: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved320: [8]u8,
-        ///  OTG_HS host channel-2 characteristics register
-        OTG_HS_HCCHAR2: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-2 split control register
-        OTG_HS_HCSPLT2: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-2 interrupt register
-        OTG_HS_HCINT2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-2 interrupt mask register
-        OTG_HS_HCINTMSK2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-2 transfer size register
-        OTG_HS_HCTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-2 DMA address register
-        OTG_HS_HCDMA2: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved352: [8]u8,
-        ///  OTG_HS host channel-3 characteristics register
-        OTG_HS_HCCHAR3: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-3 split control register
-        OTG_HS_HCSPLT3: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-3 interrupt register
-        OTG_HS_HCINT3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-3 interrupt mask register
-        OTG_HS_HCINTMSK3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-3 transfer size register
-        OTG_HS_HCTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-3 DMA address register
-        OTG_HS_HCDMA3: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved384: [8]u8,
-        ///  OTG_HS host channel-4 characteristics register
-        OTG_HS_HCCHAR4: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-4 split control register
-        OTG_HS_HCSPLT4: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-4 interrupt register
-        OTG_HS_HCINT4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-4 interrupt mask register
-        OTG_HS_HCINTMSK4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-4 transfer size register
-        OTG_HS_HCTSIZ4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-4 DMA address register
-        OTG_HS_HCDMA4: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved416: [8]u8,
-        ///  OTG_HS host channel-5 characteristics register
-        OTG_HS_HCCHAR5: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-5 split control register
-        OTG_HS_HCSPLT5: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-5 interrupt register
-        OTG_HS_HCINT5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-5 interrupt mask register
-        OTG_HS_HCINTMSK5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-5 transfer size register
-        OTG_HS_HCTSIZ5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-5 DMA address register
-        OTG_HS_HCDMA5: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved448: [8]u8,
-        ///  OTG_HS host channel-6 characteristics register
-        OTG_HS_HCCHAR6: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-6 split control register
-        OTG_HS_HCSPLT6: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-6 interrupt register
-        OTG_HS_HCINT6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-6 interrupt mask register
-        OTG_HS_HCINTMSK6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-6 transfer size register
-        OTG_HS_HCTSIZ6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-6 DMA address register
-        OTG_HS_HCDMA6: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved480: [8]u8,
-        ///  OTG_HS host channel-7 characteristics register
-        OTG_HS_HCCHAR7: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-7 split control register
-        OTG_HS_HCSPLT7: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-7 interrupt register
-        OTG_HS_HCINT7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-7 interrupt mask register
-        OTG_HS_HCINTMSK7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-7 transfer size register
-        OTG_HS_HCTSIZ7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-7 DMA address register
-        OTG_HS_HCDMA7: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved512: [8]u8,
-        ///  OTG_HS host channel-8 characteristics register
-        OTG_HS_HCCHAR8: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-8 split control register
-        OTG_HS_HCSPLT8: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-8 interrupt register
-        OTG_HS_HCINT8: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-8 interrupt mask register
-        OTG_HS_HCINTMSK8: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-8 transfer size register
-        OTG_HS_HCTSIZ8: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-8 DMA address register
-        OTG_HS_HCDMA8: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved544: [8]u8,
-        ///  OTG_HS host channel-9 characteristics register
-        OTG_HS_HCCHAR9: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-9 split control register
-        OTG_HS_HCSPLT9: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-9 interrupt register
-        OTG_HS_HCINT9: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-9 interrupt mask register
-        OTG_HS_HCINTMSK9: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-9 transfer size register
-        OTG_HS_HCTSIZ9: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-9 DMA address register
-        OTG_HS_HCDMA9: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved576: [8]u8,
-        ///  OTG_HS host channel-10 characteristics register
-        OTG_HS_HCCHAR10: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-10 split control register
-        OTG_HS_HCSPLT10: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-10 interrupt register
-        OTG_HS_HCINT10: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-10 interrupt mask register
-        OTG_HS_HCINTMSK10: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-10 transfer size register
-        OTG_HS_HCTSIZ10: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-10 DMA address register
-        OTG_HS_HCDMA10: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved608: [8]u8,
-        ///  OTG_HS host channel-11 characteristics register
-        OTG_HS_HCCHAR11: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-11 split control register
-        OTG_HS_HCSPLT11: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-11 interrupt register
-        OTG_HS_HCINT11: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-11 interrupt mask register
-        OTG_HS_HCINTMSK11: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-11 transfer size register
-        OTG_HS_HCTSIZ11: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-11 DMA address register
-        OTG_HS_HCDMA11: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-    };
-
-    ///  USB on the go high speed
-    pub const OTG_HS_GLOBAL = extern struct {
-        ///  OTG_HS control and status register
-        OTG_HS_GOTGCTL: mmio.Mmio(packed struct(u32) {
-            ///  Session request success
-            SRQSCS: u1,
-            ///  Session request
-            SRQ: u1,
-            reserved8: u6,
-            ///  Host negotiation success
-            HNGSCS: u1,
-            ///  HNP request
-            HNPRQ: u1,
-            ///  Host set HNP enable
-            HSHNPEN: u1,
-            ///  Device HNP enabled
-            DHNPEN: u1,
-            reserved16: u4,
-            ///  Connector ID status
-            CIDSTS: u1,
-            ///  Long/short debounce time
-            DBCT: u1,
-            ///  A-session valid
-            ASVLD: u1,
-            ///  B-session valid
-            BSVLD: u1,
-            padding: u12,
-        }),
-        ///  OTG_HS interrupt register
-        OTG_HS_GOTGINT: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Session end detected
-            SEDET: u1,
-            reserved8: u5,
-            ///  Session request success status change
-            SRSSCHG: u1,
-            ///  Host negotiation success status change
-            HNSSCHG: u1,
-            reserved17: u7,
-            ///  Host negotiation detected
-            HNGDET: u1,
-            ///  A-device timeout change
-            ADTOCHG: u1,
-            ///  Debounce done
-            DBCDNE: u1,
-            padding: u12,
-        }),
-        ///  OTG_HS AHB configuration register
-        OTG_HS_GAHBCFG: mmio.Mmio(packed struct(u32) {
-            ///  Global interrupt mask
-            GINT: u1,
-            ///  Burst length/type
-            HBSTLEN: u4,
-            ///  DMA enable
-            DMAEN: u1,
-            reserved7: u1,
-            ///  TxFIFO empty level
-            TXFELVL: u1,
-            ///  Periodic TxFIFO empty level
-            PTXFELVL: u1,
-            padding: u23,
-        }),
-        ///  OTG_HS USB configuration register
-        OTG_HS_GUSBCFG: mmio.Mmio(packed struct(u32) {
-            ///  FS timeout calibration
-            TOCAL: u3,
-            reserved6: u3,
-            ///  USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
-            PHYSEL: u1,
-            reserved8: u1,
-            ///  SRP-capable
-            SRPCAP: u1,
-            ///  HNP-capable
-            HNPCAP: u1,
-            ///  USB turnaround time
-            TRDT: u4,
-            reserved15: u1,
-            ///  PHY Low-power clock select
-            PHYLPCS: u1,
-            reserved17: u1,
-            ///  ULPI FS/LS select
-            ULPIFSLS: u1,
-            ///  ULPI Auto-resume
-            ULPIAR: u1,
-            ///  ULPI Clock SuspendM
-            ULPICSM: u1,
-            ///  ULPI External VBUS Drive
-            ULPIEVBUSD: u1,
-            ///  ULPI external VBUS indicator
-            ULPIEVBUSI: u1,
-            ///  TermSel DLine pulsing selection
-            TSDPS: u1,
-            ///  Indicator complement
-            PCCI: u1,
-            ///  Indicator pass through
-            PTCI: u1,
-            ///  ULPI interface protect disable
-            ULPIIPD: u1,
-            reserved29: u3,
-            ///  Forced host mode
-            FHMOD: u1,
-            ///  Forced peripheral mode
-            FDMOD: u1,
-            ///  Corrupt Tx packet
-            CTXPKT: u1,
-        }),
-        ///  OTG_HS reset register
-        OTG_HS_GRSTCTL: mmio.Mmio(packed struct(u32) {
-            ///  Core soft reset
-            CSRST: u1,
-            ///  HCLK soft reset
-            HSRST: u1,
-            ///  Host frame counter reset
-            FCRST: u1,
-            reserved4: u1,
-            ///  RxFIFO flush
-            RXFFLSH: u1,
-            ///  TxFIFO flush
-            TXFFLSH: u1,
-            ///  TxFIFO number
-            TXFNUM: u5,
-            reserved30: u19,
-            ///  DMA request signal
-            DMAREQ: u1,
-            ///  AHB master idle
-            AHBIDL: u1,
-        }),
-        ///  OTG_HS core interrupt register
-        OTG_HS_GINTSTS: mmio.Mmio(packed struct(u32) {
-            ///  Current mode of operation
-            CMOD: u1,
-            ///  Mode mismatch interrupt
-            MMIS: u1,
-            ///  OTG interrupt
-            OTGINT: u1,
-            ///  Start of frame
-            SOF: u1,
-            ///  RxFIFO nonempty
-            RXFLVL: u1,
-            ///  Nonperiodic TxFIFO empty
-            NPTXFE: u1,
-            ///  Global IN nonperiodic NAK effective
-            GINAKEFF: u1,
-            ///  Global OUT NAK effective
-            BOUTNAKEFF: u1,
-            reserved10: u2,
-            ///  Early suspend
-            ESUSP: u1,
-            ///  USB suspend
-            USBSUSP: u1,
-            ///  USB reset
-            USBRST: u1,
-            ///  Enumeration done
-            ENUMDNE: u1,
-            ///  Isochronous OUT packet dropped interrupt
-            ISOODRP: u1,
-            ///  End of periodic frame interrupt
-            EOPF: u1,
-            reserved18: u2,
-            ///  IN endpoint interrupt
-            IEPINT: u1,
-            ///  OUT endpoint interrupt
-            OEPINT: u1,
-            ///  Incomplete isochronous IN transfer
-            IISOIXFR: u1,
-            ///  Incomplete periodic transfer
-            PXFR_INCOMPISOOUT: u1,
-            ///  Data fetch suspended
-            DATAFSUSP: u1,
-            reserved24: u1,
-            ///  Host port interrupt
-            HPRTINT: u1,
-            ///  Host channels interrupt
-            HCINT: u1,
-            ///  Periodic TxFIFO empty
-            PTXFE: u1,
-            reserved28: u1,
-            ///  Connector ID status change
-            CIDSCHG: u1,
-            ///  Disconnect detected interrupt
-            DISCINT: u1,
-            ///  Session request/new session detected interrupt
-            SRQINT: u1,
-            ///  Resume/remote wakeup detected interrupt
-            WKUINT: u1,
-        }),
-        ///  OTG_HS interrupt mask register
-        OTG_HS_GINTMSK: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Mode mismatch interrupt mask
-            MMISM: u1,
-            ///  OTG interrupt mask
-            OTGINT: u1,
-            ///  Start of frame mask
-            SOFM: u1,
-            ///  Receive FIFO nonempty mask
-            RXFLVLM: u1,
-            ///  Nonperiodic TxFIFO empty mask
-            NPTXFEM: u1,
-            ///  Global nonperiodic IN NAK effective mask
-            GINAKEFFM: u1,
-            ///  Global OUT NAK effective mask
-            GONAKEFFM: u1,
-            reserved10: u2,
-            ///  Early suspend mask
-            ESUSPM: u1,
-            ///  USB suspend mask
-            USBSUSPM: u1,
-            ///  USB reset mask
-            USBRST: u1,
-            ///  Enumeration done mask
-            ENUMDNEM: u1,
-            ///  Isochronous OUT packet dropped interrupt mask
-            ISOODRPM: u1,
-            ///  End of periodic frame interrupt mask
-            EOPFM: u1,
-            reserved17: u1,
-            ///  Endpoint mismatch interrupt mask
-            EPMISM: u1,
-            ///  IN endpoints interrupt mask
-            IEPINT: u1,
-            ///  OUT endpoints interrupt mask
-            OEPINT: u1,
-            ///  Incomplete isochronous IN transfer mask
-            IISOIXFRM: u1,
-            ///  Incomplete periodic transfer mask
-            PXFRM_IISOOXFRM: u1,
-            ///  Data fetch suspended mask
-            FSUSPM: u1,
-            reserved24: u1,
-            ///  Host port interrupt mask
-            PRTIM: u1,
-            ///  Host channels interrupt mask
-            HCIM: u1,
-            ///  Periodic TxFIFO empty mask
-            PTXFEM: u1,
-            reserved28: u1,
-            ///  Connector ID status change mask
-            CIDSCHGM: u1,
-            ///  Disconnect detected interrupt mask
-            DISCINT: u1,
-            ///  Session request/new session detected interrupt mask
-            SRQIM: u1,
-            ///  Resume/remote wakeup detected interrupt mask
-            WUIM: u1,
-        }),
-        ///  OTG_HS Receive status debug read register (host mode)
-        OTG_HS_GRXSTSR_Host: mmio.Mmio(packed struct(u32) {
-            ///  Channel number
-            CHNUM: u4,
-            ///  Byte count
-            BCNT: u11,
-            ///  Data PID
-            DPID: u2,
-            ///  Packet status
-            PKTSTS: u4,
-            padding: u11,
-        }),
-        ///  OTG_HS status read and pop register (host mode)
-        OTG_HS_GRXSTSP_Host: mmio.Mmio(packed struct(u32) {
-            ///  Channel number
-            CHNUM: u4,
-            ///  Byte count
-            BCNT: u11,
-            ///  Data PID
-            DPID: u2,
-            ///  Packet status
-            PKTSTS: u4,
-            padding: u11,
-        }),
-        ///  OTG_HS Receive FIFO size register
-        OTG_HS_GRXFSIZ: mmio.Mmio(packed struct(u32) {
-            ///  RxFIFO depth
-            RXFD: u16,
-            padding: u16,
-        }),
-        ///  OTG_HS nonperiodic transmit FIFO size register (host mode)
-        OTG_HS_GNPTXFSIZ_Host: mmio.Mmio(packed struct(u32) {
-            ///  Nonperiodic transmit RAM start address
-            NPTXFSA: u16,
-            ///  Nonperiodic TxFIFO depth
-            NPTXFD: u16,
-        }),
-        ///  OTG_HS nonperiodic transmit FIFO/queue status register
-        OTG_HS_GNPTXSTS: mmio.Mmio(packed struct(u32) {
-            ///  Nonperiodic TxFIFO space available
-            NPTXFSAV: u16,
-            ///  Nonperiodic transmit request queue space available
-            NPTQXSAV: u8,
-            ///  Top of the nonperiodic transmit request queue
-            NPTXQTOP: u7,
-            padding: u1,
-        }),
-        reserved56: [8]u8,
-        ///  OTG_HS general core configuration register
-        OTG_HS_GCCFG: mmio.Mmio(packed struct(u32) {
-            reserved16: u16,
-            ///  Power down
-            PWRDWN: u1,
-            ///  Enable I2C bus connection for the external I2C PHY interface
-            I2CPADEN: u1,
-            ///  Enable the VBUS sensing device
-            VBUSASEN: u1,
-            ///  Enable the VBUS sensing device
-            VBUSBSEN: u1,
-            ///  SOF output enable
-            SOFOUTEN: u1,
-            ///  VBUS sensing disable option
-            NOVBUSSENS: u1,
-            padding: u10,
-        }),
-        ///  OTG_HS core ID register
-        OTG_HS_CID: mmio.Mmio(packed struct(u32) {
-            ///  Product ID field
-            PRODUCT_ID: u32,
-        }),
-        reserved256: [192]u8,
-        ///  OTG_HS Host periodic transmit FIFO size register
-        OTG_HS_HPTXFSIZ: mmio.Mmio(packed struct(u32) {
-            ///  Host periodic TxFIFO start address
-            PTXSA: u16,
-            ///  Host periodic TxFIFO depth
-            PTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF1: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF2: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        reserved284: [16]u8,
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF3: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF4: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF5: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF6: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF7: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-    };
-
-    ///  Secure digital input/output interface
-    pub const SDIO = extern struct {
-        ///  power control register
-        POWER: mmio.Mmio(packed struct(u32) {
-            ///  PWRCTRL
-            PWRCTRL: u2,
-            padding: u30,
-        }),
-        ///  SDI clock control register
-        CLKCR: mmio.Mmio(packed struct(u32) {
-            ///  Clock divide factor
-            CLKDIV: u8,
-            ///  Clock enable bit
-            CLKEN: u1,
-            ///  Power saving configuration bit
-            PWRSAV: u1,
-            ///  Clock divider bypass enable bit
-            BYPASS: u1,
-            ///  Wide bus mode enable bit
-            WIDBUS: u2,
-            ///  SDIO_CK dephasing selection bit
-            NEGEDGE: u1,
-            ///  HW Flow Control enable
-            HWFC_EN: u1,
-            padding: u17,
-        }),
-        ///  argument register
-        ARG: mmio.Mmio(packed struct(u32) {
-            ///  Command argument
-            CMDARG: u32,
-        }),
-        ///  command register
-        CMD: mmio.Mmio(packed struct(u32) {
-            ///  Command index
-            CMDINDEX: u6,
-            ///  Wait for response bits
-            WAITRESP: u2,
-            ///  CPSM waits for interrupt request
-            WAITINT: u1,
-            ///  CPSM Waits for ends of data transfer (CmdPend internal signal).
-            WAITPEND: u1,
-            ///  Command path state machine (CPSM) Enable bit
-            CPSMEN: u1,
-            ///  SD I/O suspend command
-            SDIOSuspend: u1,
-            ///  Enable CMD completion
-            ENCMDcompl: u1,
-            ///  not Interrupt Enable
-            nIEN: u1,
-            ///  CE-ATA command
-            CE_ATACMD: u1,
-            padding: u17,
-        }),
-        ///  command response register
-        RESPCMD: mmio.Mmio(packed struct(u32) {
-            ///  Response command index
-            RESPCMD: u6,
-            padding: u26,
-        }),
-        ///  response 1..4 register
-        RESP1: mmio.Mmio(packed struct(u32) {
-            ///  see Table 132.
-            CARDSTATUS1: u32,
-        }),
-        ///  response 1..4 register
-        RESP2: mmio.Mmio(packed struct(u32) {
-            ///  see Table 132.
-            CARDSTATUS2: u32,
-        }),
-        ///  response 1..4 register
-        RESP3: mmio.Mmio(packed struct(u32) {
-            ///  see Table 132.
-            CARDSTATUS3: u32,
-        }),
-        ///  response 1..4 register
-        RESP4: mmio.Mmio(packed struct(u32) {
-            ///  see Table 132.
-            CARDSTATUS4: u32,
-        }),
-        ///  data timer register
-        DTIMER: mmio.Mmio(packed struct(u32) {
-            ///  Data timeout period
-            DATATIME: u32,
-        }),
-        ///  data length register
-        DLEN: mmio.Mmio(packed struct(u32) {
-            ///  Data length value
-            DATALENGTH: u25,
-            padding: u7,
-        }),
-        ///  data control register
-        DCTRL: mmio.Mmio(packed struct(u32) {
-            ///  DTEN
-            DTEN: u1,
-            ///  Data transfer direction selection
-            DTDIR: u1,
-            ///  Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
-            DTMODE: u1,
-            ///  DMA enable bit
-            DMAEN: u1,
-            ///  Data block size
-            DBLOCKSIZE: u4,
-            ///  Read wait start
-            RWSTART: u1,
-            ///  Read wait stop
-            RWSTOP: u1,
-            ///  Read wait mode
-            RWMOD: u1,
-            ///  SD I/O enable functions
-            SDIOEN: u1,
-            padding: u20,
-        }),
-        ///  data counter register
-        DCOUNT: mmio.Mmio(packed struct(u32) {
-            ///  Data count value
-            DATACOUNT: u25,
-            padding: u7,
-        }),
-        ///  status register
-        STA: mmio.Mmio(packed struct(u32) {
-            ///  Command response received (CRC check failed)
-            CCRCFAIL: u1,
-            ///  Data block sent/received (CRC check failed)
-            DCRCFAIL: u1,
-            ///  Command response timeout
-            CTIMEOUT: u1,
-            ///  Data timeout
-            DTIMEOUT: u1,
-            ///  Transmit FIFO underrun error
-            TXUNDERR: u1,
-            ///  Received FIFO overrun error
-            RXOVERR: u1,
-            ///  Command response received (CRC check passed)
-            CMDREND: u1,
-            ///  Command sent (no response required)
-            CMDSENT: u1,
-            ///  Data end (data counter, SDIDCOUNT, is zero)
-            DATAEND: u1,
-            ///  Start bit not detected on all data signals in wide bus mode
-            STBITERR: u1,
-            ///  Data block sent/received (CRC check passed)
-            DBCKEND: u1,
-            ///  Command transfer in progress
-            CMDACT: u1,
-            ///  Data transmit in progress
-            TXACT: u1,
-            ///  Data receive in progress
-            RXACT: u1,
-            ///  Transmit FIFO half empty: at least 8 words can be written into the FIFO
-            TXFIFOHE: u1,
-            ///  Receive FIFO half full: there are at least 8 words in the FIFO
-            RXFIFOHF: u1,
-            ///  Transmit FIFO full
-            TXFIFOF: u1,
-            ///  Receive FIFO full
-            RXFIFOF: u1,
-            ///  Transmit FIFO empty
-            TXFIFOE: u1,
-            ///  Receive FIFO empty
-            RXFIFOE: u1,
-            ///  Data available in transmit FIFO
-            TXDAVL: u1,
-            ///  Data available in receive FIFO
-            RXDAVL: u1,
-            ///  SDIO interrupt received
-            SDIOIT: u1,
-            ///  CE-ATA command completion signal received for CMD61
-            CEATAEND: u1,
-            padding: u8,
-        }),
-        ///  interrupt clear register
-        ICR: mmio.Mmio(packed struct(u32) {
-            ///  CCRCFAIL flag clear bit
-            CCRCFAILC: u1,
-            ///  DCRCFAIL flag clear bit
-            DCRCFAILC: u1,
-            ///  CTIMEOUT flag clear bit
-            CTIMEOUTC: u1,
-            ///  DTIMEOUT flag clear bit
-            DTIMEOUTC: u1,
-            ///  TXUNDERR flag clear bit
-            TXUNDERRC: u1,
-            ///  RXOVERR flag clear bit
-            RXOVERRC: u1,
-            ///  CMDREND flag clear bit
-            CMDRENDC: u1,
-            ///  CMDSENT flag clear bit
-            CMDSENTC: u1,
-            ///  DATAEND flag clear bit
-            DATAENDC: u1,
-            ///  STBITERR flag clear bit
-            STBITERRC: u1,
-            ///  DBCKEND flag clear bit
-            DBCKENDC: u1,
-            reserved22: u11,
-            ///  SDIOIT flag clear bit
-            SDIOITC: u1,
-            ///  CEATAEND flag clear bit
-            CEATAENDC: u1,
-            padding: u8,
-        }),
-        ///  mask register
-        MASK: mmio.Mmio(packed struct(u32) {
-            ///  Command CRC fail interrupt enable
-            CCRCFAILIE: u1,
-            ///  Data CRC fail interrupt enable
-            DCRCFAILIE: u1,
-            ///  Command timeout interrupt enable
-            CTIMEOUTIE: u1,
-            ///  Data timeout interrupt enable
-            DTIMEOUTIE: u1,
-            ///  Tx FIFO underrun error interrupt enable
-            TXUNDERRIE: u1,
-            ///  Rx FIFO overrun error interrupt enable
-            RXOVERRIE: u1,
-            ///  Command response received interrupt enable
-            CMDRENDIE: u1,
-            ///  Command sent interrupt enable
-            CMDSENTIE: u1,
-            ///  Data end interrupt enable
-            DATAENDIE: u1,
-            ///  Start bit error interrupt enable
-            STBITERRIE: u1,
-            ///  Data block end interrupt enable
-            DBCKENDIE: u1,
-            ///  Command acting interrupt enable
-            CMDACTIE: u1,
-            ///  Data transmit acting interrupt enable
-            TXACTIE: u1,
-            ///  Data receive acting interrupt enable
-            RXACTIE: u1,
-            ///  Tx FIFO half empty interrupt enable
-            TXFIFOHEIE: u1,
-            ///  Rx FIFO half full interrupt enable
-            RXFIFOHFIE: u1,
-            ///  Tx FIFO full interrupt enable
-            TXFIFOFIE: u1,
-            ///  Rx FIFO full interrupt enable
-            RXFIFOFIE: u1,
-            ///  Tx FIFO empty interrupt enable
-            TXFIFOEIE: u1,
-            ///  Rx FIFO empty interrupt enable
-            RXFIFOEIE: u1,
-            ///  Data available in Tx FIFO interrupt enable
-            TXDAVLIE: u1,
-            ///  Data available in Rx FIFO interrupt enable
-            RXDAVLIE: u1,
-            ///  SDIO mode interrupt received interrupt enable
-            SDIOITIE: u1,
-            ///  CE-ATA command completion signal received interrupt enable
-            CEATAENDIE: u1,
-            padding: u8,
-        }),
-        reserved72: [8]u8,
-        ///  FIFO counter register
-        FIFOCNT: mmio.Mmio(packed struct(u32) {
-            ///  Remaining number of words to be written to or read from the FIFO.
-            FIFOCOUNT: u24,
-            padding: u8,
-        }),
-        reserved128: [52]u8,
-        ///  data FIFO register
-        FIFO: mmio.Mmio(packed struct(u32) {
-            ///  Receive and transmit FIFO data
-            FIFOData: u32,
-        }),
-    };
-
-    ///  Analog-to-digital converter
-    pub const ADC1 = extern struct {
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog flag
-            AWD: u1,
-            ///  Regular channel end of conversion
-            EOC: u1,
-            ///  Injected channel end of conversion
-            JEOC: u1,
-            ///  Injected channel start flag
-            JSTRT: u1,
-            ///  Regular channel start flag
-            STRT: u1,
-            ///  Overrun
-            OVR: u1,
-            padding: u26,
-        }),
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog channel select bits
-            AWDCH: u5,
-            ///  Interrupt enable for EOC
-            EOCIE: u1,
-            ///  Analog watchdog interrupt enable
-            AWDIE: u1,
-            ///  Interrupt enable for injected channels
-            JEOCIE: u1,
-            ///  Scan mode
-            SCAN: u1,
-            ///  Enable the watchdog on a single channel in scan mode
-            AWDSGL: u1,
-            ///  Automatic injected group conversion
-            JAUTO: u1,
-            ///  Discontinuous mode on regular channels
-            DISCEN: u1,
-            ///  Discontinuous mode on injected channels
-            JDISCEN: u1,
-            ///  Discontinuous mode channel count
-            DISCNUM: u3,
-            reserved22: u6,
-            ///  Analog watchdog enable on injected channels
-            JAWDEN: u1,
-            ///  Analog watchdog enable on regular channels
-            AWDEN: u1,
-            ///  Resolution
-            RES: u2,
-            ///  Overrun interrupt enable
-            OVRIE: u1,
-            padding: u5,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  A/D Converter ON / OFF
-            ADON: u1,
-            ///  Continuous conversion
-            CONT: u1,
-            reserved8: u6,
-            ///  Direct memory access mode (for single ADC mode)
-            DMA: u1,
-            ///  DMA disable selection (for single ADC mode)
-            DDS: u1,
-            ///  End of conversion selection
-            EOCS: u1,
-            ///  Data alignment
-            ALIGN: u1,
-            reserved16: u4,
-            ///  External event select for injected group
-            JEXTSEL: u4,
-            ///  External trigger enable for injected channels
-            JEXTEN: u2,
-            ///  Start conversion of injected channels
-            JSWSTART: u1,
-            reserved24: u1,
-            ///  External event select for regular group
-            EXTSEL: u4,
-            ///  External trigger enable for regular channels
-            EXTEN: u2,
-            ///  Start conversion of regular channels
-            SWSTART: u1,
-            padding: u1,
-        }),
-        ///  sample time register 1
-        SMPR1: mmio.Mmio(packed struct(u32) {
-            ///  Sample time bits
-            SMPx_x: u32,
-        }),
-        ///  sample time register 2
-        SMPR2: mmio.Mmio(packed struct(u32) {
-            ///  Sample time bits
-            SMPx_x: u32,
-        }),
-        ///  injected channel data offset register x
-        JOFR1: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET1: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR2: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET2: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR3: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET3: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR4: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET4: u12,
-            padding: u20,
-        }),
-        ///  watchdog higher threshold register
-        HTR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog higher threshold
-            HT: u12,
-            padding: u20,
-        }),
-        ///  watchdog lower threshold register
-        LTR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog lower threshold
-            LT: u12,
-            padding: u20,
-        }),
-        ///  regular sequence register 1
-        SQR1: mmio.Mmio(packed struct(u32) {
-            ///  13th conversion in regular sequence
-            SQ13: u5,
-            ///  14th conversion in regular sequence
-            SQ14: u5,
-            ///  15th conversion in regular sequence
-            SQ15: u5,
-            ///  16th conversion in regular sequence
-            SQ16: u5,
-            ///  Regular channel sequence length
-            L: u4,
-            padding: u8,
-        }),
-        ///  regular sequence register 2
-        SQR2: mmio.Mmio(packed struct(u32) {
-            ///  7th conversion in regular sequence
-            SQ7: u5,
-            ///  8th conversion in regular sequence
-            SQ8: u5,
-            ///  9th conversion in regular sequence
-            SQ9: u5,
-            ///  10th conversion in regular sequence
-            SQ10: u5,
-            ///  11th conversion in regular sequence
-            SQ11: u5,
-            ///  12th conversion in regular sequence
-            SQ12: u5,
-            padding: u2,
-        }),
-        ///  regular sequence register 3
-        SQR3: mmio.Mmio(packed struct(u32) {
-            ///  1st conversion in regular sequence
-            SQ1: u5,
-            ///  2nd conversion in regular sequence
-            SQ2: u5,
-            ///  3rd conversion in regular sequence
-            SQ3: u5,
-            ///  4th conversion in regular sequence
-            SQ4: u5,
-            ///  5th conversion in regular sequence
-            SQ5: u5,
-            ///  6th conversion in regular sequence
-            SQ6: u5,
-            padding: u2,
-        }),
-        ///  injected sequence register
-        JSQR: mmio.Mmio(packed struct(u32) {
-            ///  1st conversion in injected sequence
-            JSQ1: u5,
-            ///  2nd conversion in injected sequence
-            JSQ2: u5,
-            ///  3rd conversion in injected sequence
-            JSQ3: u5,
-            ///  4th conversion in injected sequence
-            JSQ4: u5,
-            ///  Injected sequence length
-            JL: u2,
-            padding: u10,
-        }),
-        ///  injected data register x
-        JDR1: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR2: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR3: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR4: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  regular data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Regular data
-            DATA: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  External interrupt/event controller
-    pub const EXTI = extern struct {
-        ///  Interrupt mask register (EXTI_IMR)
-        IMR: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt Mask on line 0
-            MR0: u1,
-            ///  Interrupt Mask on line 1
-            MR1: u1,
-            ///  Interrupt Mask on line 2
-            MR2: u1,
-            ///  Interrupt Mask on line 3
-            MR3: u1,
-            ///  Interrupt Mask on line 4
-            MR4: u1,
-            ///  Interrupt Mask on line 5
-            MR5: u1,
-            ///  Interrupt Mask on line 6
-            MR6: u1,
-            ///  Interrupt Mask on line 7
-            MR7: u1,
-            ///  Interrupt Mask on line 8
-            MR8: u1,
-            ///  Interrupt Mask on line 9
-            MR9: u1,
-            ///  Interrupt Mask on line 10
-            MR10: u1,
-            ///  Interrupt Mask on line 11
-            MR11: u1,
-            ///  Interrupt Mask on line 12
-            MR12: u1,
-            ///  Interrupt Mask on line 13
-            MR13: u1,
-            ///  Interrupt Mask on line 14
-            MR14: u1,
-            ///  Interrupt Mask on line 15
-            MR15: u1,
-            ///  Interrupt Mask on line 16
-            MR16: u1,
-            ///  Interrupt Mask on line 17
-            MR17: u1,
-            ///  Interrupt Mask on line 18
-            MR18: u1,
-            ///  Interrupt Mask on line 19
-            MR19: u1,
-            ///  Interrupt Mask on line 20
-            MR20: u1,
-            ///  Interrupt Mask on line 21
-            MR21: u1,
-            ///  Interrupt Mask on line 22
-            MR22: u1,
-            padding: u9,
-        }),
-        ///  Event mask register (EXTI_EMR)
-        EMR: mmio.Mmio(packed struct(u32) {
-            ///  Event Mask on line 0
-            MR0: u1,
-            ///  Event Mask on line 1
-            MR1: u1,
-            ///  Event Mask on line 2
-            MR2: u1,
-            ///  Event Mask on line 3
-            MR3: u1,
-            ///  Event Mask on line 4
-            MR4: u1,
-            ///  Event Mask on line 5
-            MR5: u1,
-            ///  Event Mask on line 6
-            MR6: u1,
-            ///  Event Mask on line 7
-            MR7: u1,
-            ///  Event Mask on line 8
-            MR8: u1,
-            ///  Event Mask on line 9
-            MR9: u1,
-            ///  Event Mask on line 10
-            MR10: u1,
-            ///  Event Mask on line 11
-            MR11: u1,
-            ///  Event Mask on line 12
-            MR12: u1,
-            ///  Event Mask on line 13
-            MR13: u1,
-            ///  Event Mask on line 14
-            MR14: u1,
-            ///  Event Mask on line 15
-            MR15: u1,
-            ///  Event Mask on line 16
-            MR16: u1,
-            ///  Event Mask on line 17
-            MR17: u1,
-            ///  Event Mask on line 18
-            MR18: u1,
-            ///  Event Mask on line 19
-            MR19: u1,
-            ///  Event Mask on line 20
-            MR20: u1,
-            ///  Event Mask on line 21
-            MR21: u1,
-            ///  Event Mask on line 22
-            MR22: u1,
-            padding: u9,
-        }),
-        ///  Rising Trigger selection register (EXTI_RTSR)
-        RTSR: mmio.Mmio(packed struct(u32) {
-            ///  Rising trigger event configuration of line 0
-            TR0: u1,
-            ///  Rising trigger event configuration of line 1
-            TR1: u1,
-            ///  Rising trigger event configuration of line 2
-            TR2: u1,
-            ///  Rising trigger event configuration of line 3
-            TR3: u1,
-            ///  Rising trigger event configuration of line 4
-            TR4: u1,
-            ///  Rising trigger event configuration of line 5
-            TR5: u1,
-            ///  Rising trigger event configuration of line 6
-            TR6: u1,
-            ///  Rising trigger event configuration of line 7
-            TR7: u1,
-            ///  Rising trigger event configuration of line 8
-            TR8: u1,
-            ///  Rising trigger event configuration of line 9
-            TR9: u1,
-            ///  Rising trigger event configuration of line 10
-            TR10: u1,
-            ///  Rising trigger event configuration of line 11
-            TR11: u1,
-            ///  Rising trigger event configuration of line 12
-            TR12: u1,
-            ///  Rising trigger event configuration of line 13
-            TR13: u1,
-            ///  Rising trigger event configuration of line 14
-            TR14: u1,
-            ///  Rising trigger event configuration of line 15
-            TR15: u1,
-            ///  Rising trigger event configuration of line 16
-            TR16: u1,
-            ///  Rising trigger event configuration of line 17
-            TR17: u1,
-            ///  Rising trigger event configuration of line 18
-            TR18: u1,
-            ///  Rising trigger event configuration of line 19
-            TR19: u1,
-            ///  Rising trigger event configuration of line 20
-            TR20: u1,
-            ///  Rising trigger event configuration of line 21
-            TR21: u1,
-            ///  Rising trigger event configuration of line 22
-            TR22: u1,
-            padding: u9,
-        }),
-        ///  Falling Trigger selection register (EXTI_FTSR)
-        FTSR: mmio.Mmio(packed struct(u32) {
-            ///  Falling trigger event configuration of line 0
-            TR0: u1,
-            ///  Falling trigger event configuration of line 1
-            TR1: u1,
-            ///  Falling trigger event configuration of line 2
-            TR2: u1,
-            ///  Falling trigger event configuration of line 3
-            TR3: u1,
-            ///  Falling trigger event configuration of line 4
-            TR4: u1,
-            ///  Falling trigger event configuration of line 5
-            TR5: u1,
-            ///  Falling trigger event configuration of line 6
-            TR6: u1,
-            ///  Falling trigger event configuration of line 7
-            TR7: u1,
-            ///  Falling trigger event configuration of line 8
-            TR8: u1,
-            ///  Falling trigger event configuration of line 9
-            TR9: u1,
-            ///  Falling trigger event configuration of line 10
-            TR10: u1,
-            ///  Falling trigger event configuration of line 11
-            TR11: u1,
-            ///  Falling trigger event configuration of line 12
-            TR12: u1,
-            ///  Falling trigger event configuration of line 13
-            TR13: u1,
-            ///  Falling trigger event configuration of line 14
-            TR14: u1,
-            ///  Falling trigger event configuration of line 15
-            TR15: u1,
-            ///  Falling trigger event configuration of line 16
-            TR16: u1,
-            ///  Falling trigger event configuration of line 17
-            TR17: u1,
-            ///  Falling trigger event configuration of line 18
-            TR18: u1,
-            ///  Falling trigger event configuration of line 19
-            TR19: u1,
-            ///  Falling trigger event configuration of line 20
-            TR20: u1,
-            ///  Falling trigger event configuration of line 21
-            TR21: u1,
-            ///  Falling trigger event configuration of line 22
-            TR22: u1,
-            padding: u9,
-        }),
-        ///  Software interrupt event register (EXTI_SWIER)
-        SWIER: mmio.Mmio(packed struct(u32) {
-            ///  Software Interrupt on line 0
-            SWIER0: u1,
-            ///  Software Interrupt on line 1
-            SWIER1: u1,
-            ///  Software Interrupt on line 2
-            SWIER2: u1,
-            ///  Software Interrupt on line 3
-            SWIER3: u1,
-            ///  Software Interrupt on line 4
-            SWIER4: u1,
-            ///  Software Interrupt on line 5
-            SWIER5: u1,
-            ///  Software Interrupt on line 6
-            SWIER6: u1,
-            ///  Software Interrupt on line 7
-            SWIER7: u1,
-            ///  Software Interrupt on line 8
-            SWIER8: u1,
-            ///  Software Interrupt on line 9
-            SWIER9: u1,
-            ///  Software Interrupt on line 10
-            SWIER10: u1,
-            ///  Software Interrupt on line 11
-            SWIER11: u1,
-            ///  Software Interrupt on line 12
-            SWIER12: u1,
-            ///  Software Interrupt on line 13
-            SWIER13: u1,
-            ///  Software Interrupt on line 14
-            SWIER14: u1,
-            ///  Software Interrupt on line 15
-            SWIER15: u1,
-            ///  Software Interrupt on line 16
-            SWIER16: u1,
-            ///  Software Interrupt on line 17
-            SWIER17: u1,
-            ///  Software Interrupt on line 18
-            SWIER18: u1,
-            ///  Software Interrupt on line 19
-            SWIER19: u1,
-            ///  Software Interrupt on line 20
-            SWIER20: u1,
-            ///  Software Interrupt on line 21
-            SWIER21: u1,
-            ///  Software Interrupt on line 22
-            SWIER22: u1,
-            padding: u9,
-        }),
-        ///  Pending register (EXTI_PR)
-        PR: mmio.Mmio(packed struct(u32) {
-            ///  Pending bit 0
-            PR0: u1,
-            ///  Pending bit 1
-            PR1: u1,
-            ///  Pending bit 2
-            PR2: u1,
-            ///  Pending bit 3
-            PR3: u1,
-            ///  Pending bit 4
-            PR4: u1,
-            ///  Pending bit 5
-            PR5: u1,
-            ///  Pending bit 6
-            PR6: u1,
-            ///  Pending bit 7
-            PR7: u1,
-            ///  Pending bit 8
-            PR8: u1,
-            ///  Pending bit 9
-            PR9: u1,
-            ///  Pending bit 10
-            PR10: u1,
-            ///  Pending bit 11
-            PR11: u1,
-            ///  Pending bit 12
-            PR12: u1,
-            ///  Pending bit 13
-            PR13: u1,
-            ///  Pending bit 14
-            PR14: u1,
-            ///  Pending bit 15
-            PR15: u1,
-            ///  Pending bit 16
-            PR16: u1,
-            ///  Pending bit 17
-            PR17: u1,
-            ///  Pending bit 18
-            PR18: u1,
-            ///  Pending bit 19
-            PR19: u1,
-            ///  Pending bit 20
-            PR20: u1,
-            ///  Pending bit 21
-            PR21: u1,
-            ///  Pending bit 22
-            PR22: u1,
-            padding: u9,
-        }),
-    };
-
-    ///  FLASH
-    pub const FLASH = extern struct {
-        ///  Flash access control register
-        ACR: mmio.Mmio(packed struct(u32) {
-            ///  Latency
-            LATENCY: u3,
-            reserved8: u5,
-            ///  Prefetch enable
-            PRFTEN: u1,
-            ///  Instruction cache enable
-            ICEN: u1,
-            ///  Data cache enable
-            DCEN: u1,
-            ///  Instruction cache reset
-            ICRST: u1,
-            ///  Data cache reset
-            DCRST: u1,
-            padding: u19,
-        }),
-        ///  Flash key register
-        KEYR: mmio.Mmio(packed struct(u32) {
-            ///  FPEC key
-            KEY: u32,
-        }),
-        ///  Flash option key register
-        OPTKEYR: mmio.Mmio(packed struct(u32) {
-            ///  Option byte key
-            OPTKEY: u32,
-        }),
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  End of operation
-            EOP: u1,
-            ///  Operation error
-            OPERR: u1,
-            reserved4: u2,
-            ///  Write protection error
-            WRPERR: u1,
-            ///  Programming alignment error
-            PGAERR: u1,
-            ///  Programming parallelism error
-            PGPERR: u1,
-            ///  Programming sequence error
-            PGSERR: u1,
-            reserved16: u8,
-            ///  Busy
-            BSY: u1,
-            padding: u15,
-        }),
-        ///  Control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Programming
-            PG: u1,
-            ///  Sector Erase
-            SER: u1,
-            ///  Mass Erase
-            MER: u1,
-            ///  Sector number
-            SNB: u4,
-            reserved8: u1,
-            ///  Program size
-            PSIZE: u2,
-            reserved16: u6,
-            ///  Start
-            STRT: u1,
-            reserved24: u7,
-            ///  End of operation interrupt enable
-            EOPIE: u1,
-            ///  Error interrupt enable
-            ERRIE: u1,
-            reserved31: u5,
-            ///  Lock
-            LOCK: u1,
-        }),
-        ///  Flash option control register
-        OPTCR: mmio.Mmio(packed struct(u32) {
-            ///  Option lock
-            OPTLOCK: u1,
-            ///  Option start
-            OPTSTRT: u1,
-            ///  BOR reset Level
-            BOR_LEV: u2,
-            reserved5: u1,
-            ///  WDG_SW User option bytes
-            WDG_SW: u1,
-            ///  nRST_STOP User option bytes
-            nRST_STOP: u1,
-            ///  nRST_STDBY User option bytes
-            nRST_STDBY: u1,
-            ///  Read protect
-            RDP: u8,
-            ///  Not write protect
-            nWRP: u12,
-            padding: u4,
-        }),
-    };
-
-    ///  Universal synchronous asynchronous receiver transmitter
-    pub const USART6 = extern struct {
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Parity error
-            PE: u1,
-            ///  Framing error
-            FE: u1,
-            ///  Noise detected flag
-            NF: u1,
-            ///  Overrun error
-            ORE: u1,
-            ///  IDLE line detected
-            IDLE: u1,
-            ///  Read data register not empty
-            RXNE: u1,
-            ///  Transmission complete
-            TC: u1,
-            ///  Transmit data register empty
-            TXE: u1,
-            ///  LIN break detection flag
-            LBD: u1,
-            ///  CTS flag
-            CTS: u1,
-            padding: u22,
-        }),
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data value
-            DR: u9,
-            padding: u23,
-        }),
-        ///  Baud rate register
-        BRR: mmio.Mmio(packed struct(u32) {
-            ///  fraction of USARTDIV
-            DIV_Fraction: u4,
-            ///  mantissa of USARTDIV
-            DIV_Mantissa: u12,
-            padding: u16,
-        }),
-        ///  Control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Send break
-            SBK: u1,
-            ///  Receiver wakeup
-            RWU: u1,
-            ///  Receiver enable
-            RE: u1,
-            ///  Transmitter enable
-            TE: u1,
-            ///  IDLE interrupt enable
-            IDLEIE: u1,
-            ///  RXNE interrupt enable
-            RXNEIE: u1,
-            ///  Transmission complete interrupt enable
-            TCIE: u1,
-            ///  TXE interrupt enable
-            TXEIE: u1,
-            ///  PE interrupt enable
-            PEIE: u1,
-            ///  Parity selection
-            PS: u1,
-            ///  Parity control enable
-            PCE: u1,
-            ///  Wakeup method
-            WAKE: u1,
-            ///  Word length
-            M: u1,
-            ///  USART enable
-            UE: u1,
-            reserved15: u1,
-            ///  Oversampling mode
-            OVER8: u1,
-            padding: u16,
-        }),
-        ///  Control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Address of the USART node
-            ADD: u4,
-            reserved5: u1,
-            ///  lin break detection length
-            LBDL: u1,
-            ///  LIN break detection interrupt enable
-            LBDIE: u1,
-            reserved8: u1,
-            ///  Last bit clock pulse
-            LBCL: u1,
-            ///  Clock phase
-            CPHA: u1,
-            ///  Clock polarity
-            CPOL: u1,
-            ///  Clock enable
-            CLKEN: u1,
-            ///  STOP bits
-            STOP: u2,
-            ///  LIN mode enable
-            LINEN: u1,
-            padding: u17,
-        }),
-        ///  Control register 3
-        CR3: mmio.Mmio(packed struct(u32) {
-            ///  Error interrupt enable
-            EIE: u1,
-            ///  IrDA mode enable
-            IREN: u1,
-            ///  IrDA low-power
-            IRLP: u1,
-            ///  Half-duplex selection
-            HDSEL: u1,
-            ///  Smartcard NACK enable
-            NACK: u1,
-            ///  Smartcard mode enable
-            SCEN: u1,
-            ///  DMA enable receiver
-            DMAR: u1,
-            ///  DMA enable transmitter
-            DMAT: u1,
-            ///  RTS enable
-            RTSE: u1,
-            ///  CTS enable
-            CTSE: u1,
-            ///  CTS interrupt enable
-            CTSIE: u1,
-            ///  One sample bit method enable
-            ONEBIT: u1,
-            padding: u20,
-        }),
-        ///  Guard time and prescaler register
-        GTPR: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u8,
-            ///  Guard time value
-            GT: u8,
-            padding: u16,
-        }),
-    };
-
-    ///  Basic timers
-    pub const TIM6 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            reserved7: u3,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            padding: u24,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  Master mode selection
-            MMS: u3,
-            padding: u25,
-        }),
-        reserved12: [4]u8,
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            reserved8: u7,
-            ///  Update DMA request enable
-            UDE: u1,
-            padding: u23,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            padding: u31,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            padding: u31,
-        }),
-        reserved36: [12]u8,
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  Low counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Low Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Controller area network
-    pub const CAN1 = extern struct {
-        ///  master control register
-        MCR: mmio.Mmio(packed struct(u32) {
-            ///  INRQ
-            INRQ: u1,
-            ///  SLEEP
-            SLEEP: u1,
-            ///  TXFP
-            TXFP: u1,
-            ///  RFLM
-            RFLM: u1,
-            ///  NART
-            NART: u1,
-            ///  AWUM
-            AWUM: u1,
-            ///  ABOM
-            ABOM: u1,
-            ///  TTCM
-            TTCM: u1,
-            reserved15: u7,
-            ///  RESET
-            RESET: u1,
-            ///  DBF
-            DBF: u1,
-            padding: u15,
-        }),
-        ///  master status register
-        MSR: mmio.Mmio(packed struct(u32) {
-            ///  INAK
-            INAK: u1,
-            ///  SLAK
-            SLAK: u1,
-            ///  ERRI
-            ERRI: u1,
-            ///  WKUI
-            WKUI: u1,
-            ///  SLAKI
-            SLAKI: u1,
-            reserved8: u3,
-            ///  TXM
-            TXM: u1,
-            ///  RXM
-            RXM: u1,
-            ///  SAMP
-            SAMP: u1,
-            ///  RX
-            RX: u1,
-            padding: u20,
-        }),
-        ///  transmit status register
-        TSR: mmio.Mmio(packed struct(u32) {
-            ///  RQCP0
-            RQCP0: u1,
-            ///  TXOK0
-            TXOK0: u1,
-            ///  ALST0
-            ALST0: u1,
-            ///  TERR0
-            TERR0: u1,
-            reserved7: u3,
-            ///  ABRQ0
-            ABRQ0: u1,
-            ///  RQCP1
-            RQCP1: u1,
-            ///  TXOK1
-            TXOK1: u1,
-            ///  ALST1
-            ALST1: u1,
-            ///  TERR1
-            TERR1: u1,
-            reserved15: u3,
-            ///  ABRQ1
-            ABRQ1: u1,
-            ///  RQCP2
-            RQCP2: u1,
-            ///  TXOK2
-            TXOK2: u1,
-            ///  ALST2
-            ALST2: u1,
-            ///  TERR2
-            TERR2: u1,
-            reserved23: u3,
-            ///  ABRQ2
-            ABRQ2: u1,
-            ///  CODE
-            CODE: u2,
-            ///  Lowest priority flag for mailbox 0
-            TME0: u1,
-            ///  Lowest priority flag for mailbox 1
-            TME1: u1,
-            ///  Lowest priority flag for mailbox 2
-            TME2: u1,
-            ///  Lowest priority flag for mailbox 0
-            LOW0: u1,
-            ///  Lowest priority flag for mailbox 1
-            LOW1: u1,
-            ///  Lowest priority flag for mailbox 2
-            LOW2: u1,
-        }),
-        ///  receive FIFO 0 register
-        RF0R: mmio.Mmio(packed struct(u32) {
-            ///  FMP0
-            FMP0: u2,
-            reserved3: u1,
-            ///  FULL0
-            FULL0: u1,
-            ///  FOVR0
-            FOVR0: u1,
-            ///  RFOM0
-            RFOM0: u1,
-            padding: u26,
-        }),
-        ///  receive FIFO 1 register
-        RF1R: mmio.Mmio(packed struct(u32) {
-            ///  FMP1
-            FMP1: u2,
-            reserved3: u1,
-            ///  FULL1
-            FULL1: u1,
-            ///  FOVR1
-            FOVR1: u1,
-            ///  RFOM1
-            RFOM1: u1,
-            padding: u26,
-        }),
-        ///  interrupt enable register
-        IER: mmio.Mmio(packed struct(u32) {
-            ///  TMEIE
-            TMEIE: u1,
-            ///  FMPIE0
-            FMPIE0: u1,
-            ///  FFIE0
-            FFIE0: u1,
-            ///  FOVIE0
-            FOVIE0: u1,
-            ///  FMPIE1
-            FMPIE1: u1,
-            ///  FFIE1
-            FFIE1: u1,
-            ///  FOVIE1
-            FOVIE1: u1,
-            reserved8: u1,
-            ///  EWGIE
-            EWGIE: u1,
-            ///  EPVIE
-            EPVIE: u1,
-            ///  BOFIE
-            BOFIE: u1,
-            ///  LECIE
-            LECIE: u1,
-            reserved15: u3,
-            ///  ERRIE
-            ERRIE: u1,
-            ///  WKUIE
-            WKUIE: u1,
-            ///  SLKIE
-            SLKIE: u1,
-            padding: u14,
-        }),
-        ///  interrupt enable register
-        ESR: mmio.Mmio(packed struct(u32) {
-            ///  EWGF
-            EWGF: u1,
-            ///  EPVF
-            EPVF: u1,
-            ///  BOFF
-            BOFF: u1,
-            reserved4: u1,
-            ///  LEC
-            LEC: u3,
-            reserved16: u9,
-            ///  TEC
-            TEC: u8,
-            ///  REC
-            REC: u8,
-        }),
-        ///  bit timing register
-        BTR: mmio.Mmio(packed struct(u32) {
-            ///  BRP
-            BRP: u10,
-            reserved16: u6,
-            ///  TS1
-            TS1: u4,
-            ///  TS2
-            TS2: u3,
-            reserved24: u1,
-            ///  SJW
-            SJW: u2,
-            reserved30: u4,
-            ///  LBKM
-            LBKM: u1,
-            ///  SILM
-            SILM: u1,
-        }),
-        reserved384: [352]u8,
-        ///  TX mailbox identifier register
-        TI0R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data length control and time stamp register
-        TDT0R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data low register
-        TDL0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  mailbox data high register
-        TDH0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  mailbox identifier register
-        TI1R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data length control and time stamp register
-        TDT1R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data low register
-        TDL1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  mailbox data high register
-        TDH1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  mailbox identifier register
-        TI2R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data length control and time stamp register
-        TDT2R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data low register
-        TDL2R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  mailbox data high register
-        TDH2R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  receive FIFO mailbox identifier register
-        RI0R: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data high register
-        RDT0R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  FMI
-            FMI: u8,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data high register
-        RDL0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  receive FIFO mailbox data high register
-        RDH0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  mailbox data high register
-        RI1R: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data high register
-        RDT1R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  FMI
-            FMI: u8,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data high register
-        RDL1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  mailbox data high register
-        RDH1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        reserved512: [48]u8,
-        ///  filter master register
-        FMR: mmio.Mmio(packed struct(u32) {
-            ///  FINIT
-            FINIT: u1,
-            reserved8: u7,
-            ///  CAN2SB
-            CAN2SB: u6,
-            padding: u18,
-        }),
-        ///  filter mode register
-        FM1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter mode
-            FBM0: u1,
-            ///  Filter mode
-            FBM1: u1,
-            ///  Filter mode
-            FBM2: u1,
-            ///  Filter mode
-            FBM3: u1,
-            ///  Filter mode
-            FBM4: u1,
-            ///  Filter mode
-            FBM5: u1,
-            ///  Filter mode
-            FBM6: u1,
-            ///  Filter mode
-            FBM7: u1,
-            ///  Filter mode
-            FBM8: u1,
-            ///  Filter mode
-            FBM9: u1,
-            ///  Filter mode
-            FBM10: u1,
-            ///  Filter mode
-            FBM11: u1,
-            ///  Filter mode
-            FBM12: u1,
-            ///  Filter mode
-            FBM13: u1,
-            ///  Filter mode
-            FBM14: u1,
-            ///  Filter mode
-            FBM15: u1,
-            ///  Filter mode
-            FBM16: u1,
-            ///  Filter mode
-            FBM17: u1,
-            ///  Filter mode
-            FBM18: u1,
-            ///  Filter mode
-            FBM19: u1,
-            ///  Filter mode
-            FBM20: u1,
-            ///  Filter mode
-            FBM21: u1,
-            ///  Filter mode
-            FBM22: u1,
-            ///  Filter mode
-            FBM23: u1,
-            ///  Filter mode
-            FBM24: u1,
-            ///  Filter mode
-            FBM25: u1,
-            ///  Filter mode
-            FBM26: u1,
-            ///  Filter mode
-            FBM27: u1,
-            padding: u4,
-        }),
-        reserved524: [4]u8,
-        ///  filter scale register
-        FS1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter scale configuration
-            FSC0: u1,
-            ///  Filter scale configuration
-            FSC1: u1,
-            ///  Filter scale configuration
-            FSC2: u1,
-            ///  Filter scale configuration
-            FSC3: u1,
-            ///  Filter scale configuration
-            FSC4: u1,
-            ///  Filter scale configuration
-            FSC5: u1,
-            ///  Filter scale configuration
-            FSC6: u1,
-            ///  Filter scale configuration
-            FSC7: u1,
-            ///  Filter scale configuration
-            FSC8: u1,
-            ///  Filter scale configuration
-            FSC9: u1,
-            ///  Filter scale configuration
-            FSC10: u1,
-            ///  Filter scale configuration
-            FSC11: u1,
-            ///  Filter scale configuration
-            FSC12: u1,
-            ///  Filter scale configuration
-            FSC13: u1,
-            ///  Filter scale configuration
-            FSC14: u1,
-            ///  Filter scale configuration
-            FSC15: u1,
-            ///  Filter scale configuration
-            FSC16: u1,
-            ///  Filter scale configuration
-            FSC17: u1,
-            ///  Filter scale configuration
-            FSC18: u1,
-            ///  Filter scale configuration
-            FSC19: u1,
-            ///  Filter scale configuration
-            FSC20: u1,
-            ///  Filter scale configuration
-            FSC21: u1,
-            ///  Filter scale configuration
-            FSC22: u1,
-            ///  Filter scale configuration
-            FSC23: u1,
-            ///  Filter scale configuration
-            FSC24: u1,
-            ///  Filter scale configuration
-            FSC25: u1,
-            ///  Filter scale configuration
-            FSC26: u1,
-            ///  Filter scale configuration
-            FSC27: u1,
-            padding: u4,
-        }),
-        reserved532: [4]u8,
-        ///  filter FIFO assignment register
-        FFA1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter FIFO assignment for filter 0
-            FFA0: u1,
-            ///  Filter FIFO assignment for filter 1
-            FFA1: u1,
-            ///  Filter FIFO assignment for filter 2
-            FFA2: u1,
-            ///  Filter FIFO assignment for filter 3
-            FFA3: u1,
-            ///  Filter FIFO assignment for filter 4
-            FFA4: u1,
-            ///  Filter FIFO assignment for filter 5
-            FFA5: u1,
-            ///  Filter FIFO assignment for filter 6
-            FFA6: u1,
-            ///  Filter FIFO assignment for filter 7
-            FFA7: u1,
-            ///  Filter FIFO assignment for filter 8
-            FFA8: u1,
-            ///  Filter FIFO assignment for filter 9
-            FFA9: u1,
-            ///  Filter FIFO assignment for filter 10
-            FFA10: u1,
-            ///  Filter FIFO assignment for filter 11
-            FFA11: u1,
-            ///  Filter FIFO assignment for filter 12
-            FFA12: u1,
-            ///  Filter FIFO assignment for filter 13
-            FFA13: u1,
-            ///  Filter FIFO assignment for filter 14
-            FFA14: u1,
-            ///  Filter FIFO assignment for filter 15
-            FFA15: u1,
-            ///  Filter FIFO assignment for filter 16
-            FFA16: u1,
-            ///  Filter FIFO assignment for filter 17
-            FFA17: u1,
-            ///  Filter FIFO assignment for filter 18
-            FFA18: u1,
-            ///  Filter FIFO assignment for filter 19
-            FFA19: u1,
-            ///  Filter FIFO assignment for filter 20
-            FFA20: u1,
-            ///  Filter FIFO assignment for filter 21
-            FFA21: u1,
-            ///  Filter FIFO assignment for filter 22
-            FFA22: u1,
-            ///  Filter FIFO assignment for filter 23
-            FFA23: u1,
-            ///  Filter FIFO assignment for filter 24
-            FFA24: u1,
-            ///  Filter FIFO assignment for filter 25
-            FFA25: u1,
-            ///  Filter FIFO assignment for filter 26
-            FFA26: u1,
-            ///  Filter FIFO assignment for filter 27
-            FFA27: u1,
-            padding: u4,
-        }),
-        reserved540: [4]u8,
-        ///  filter activation register
-        FA1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter active
-            FACT0: u1,
-            ///  Filter active
-            FACT1: u1,
-            ///  Filter active
-            FACT2: u1,
-            ///  Filter active
-            FACT3: u1,
-            ///  Filter active
-            FACT4: u1,
-            ///  Filter active
-            FACT5: u1,
-            ///  Filter active
-            FACT6: u1,
-            ///  Filter active
-            FACT7: u1,
-            ///  Filter active
-            FACT8: u1,
-            ///  Filter active
-            FACT9: u1,
-            ///  Filter active
-            FACT10: u1,
-            ///  Filter active
-            FACT11: u1,
-            ///  Filter active
-            FACT12: u1,
-            ///  Filter active
-            FACT13: u1,
-            ///  Filter active
-            FACT14: u1,
-            ///  Filter active
-            FACT15: u1,
-            ///  Filter active
-            FACT16: u1,
-            ///  Filter active
-            FACT17: u1,
-            ///  Filter active
-            FACT18: u1,
-            ///  Filter active
-            FACT19: u1,
-            ///  Filter active
-            FACT20: u1,
-            ///  Filter active
-            FACT21: u1,
-            ///  Filter active
-            FACT22: u1,
-            ///  Filter active
-            FACT23: u1,
-            ///  Filter active
-            FACT24: u1,
-            ///  Filter active
-            FACT25: u1,
-            ///  Filter active
-            FACT26: u1,
-            ///  Filter active
-            FACT27: u1,
-            padding: u4,
-        }),
-        reserved576: [32]u8,
-        ///  Filter bank 0 register 1
-        F0R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 0 register 2
-        F0R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 1 register 1
-        F1R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 1 register 2
-        F1R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 2 register 1
-        F2R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 2 register 2
-        F2R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 3 register 1
-        F3R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 3 register 2
-        F3R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 1
-        F4R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 2
-        F4R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 5 register 1
-        F5R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 5 register 2
-        F5R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 6 register 1
-        F6R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 6 register 2
-        F6R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 7 register 1
-        F7R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 7 register 2
-        F7R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 8 register 1
-        F8R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 8 register 2
-        F8R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 9 register 1
-        F9R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 9 register 2
-        F9R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 10 register 1
-        F10R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 10 register 2
-        F10R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 11 register 1
-        F11R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 11 register 2
-        F11R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 1
-        F12R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 12 register 2
-        F12R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 13 register 1
-        F13R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 13 register 2
-        F13R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 14 register 1
-        F14R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 14 register 2
-        F14R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 15 register 1
-        F15R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 15 register 2
-        F15R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 16 register 1
-        F16R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 16 register 2
-        F16R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 17 register 1
-        F17R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 17 register 2
-        F17R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 18 register 1
-        F18R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 18 register 2
-        F18R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 19 register 1
-        F19R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 19 register 2
-        F19R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 20 register 1
-        F20R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 20 register 2
-        F20R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 21 register 1
-        F21R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 21 register 2
-        F21R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 22 register 1
-        F22R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 22 register 2
-        F22R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 23 register 1
-        F23R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 23 register 2
-        F23R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 24 register 1
-        F24R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 24 register 2
-        F24R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 25 register 1
-        F25R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 25 register 2
-        F25R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 26 register 1
-        F26R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 26 register 2
-        F26R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 27 register 1
-        F27R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 27 register 2
-        F27R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_PWRCLK = extern struct {
-        ///  OTG_FS power and clock gating control register
-        FS_PCGCCTL: mmio.Mmio(packed struct(u32) {
-            ///  Stop PHY clock
-            STPPCLK: u1,
-            ///  Gate HCLK
-            GATEHCLK: u1,
-            reserved4: u2,
-            ///  PHY Suspended
-            PHYSUSP: u1,
-            padding: u27,
-        }),
-    };
-
-    ///  Digital-to-analog converter
-    pub const DAC = extern struct {
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 enable
-            EN1: u1,
-            ///  DAC channel1 output buffer disable
-            BOFF1: u1,
-            ///  DAC channel1 trigger enable
-            TEN1: u1,
-            ///  DAC channel1 trigger selection
-            TSEL1: u3,
-            ///  DAC channel1 noise/triangle wave generation enable
-            WAVE1: u2,
-            ///  DAC channel1 mask/amplitude selector
-            MAMP1: u4,
-            ///  DAC channel1 DMA enable
-            DMAEN1: u1,
-            ///  DAC channel1 DMA Underrun Interrupt enable
-            DMAUDRIE1: u1,
-            reserved16: u2,
-            ///  DAC channel2 enable
-            EN2: u1,
-            ///  DAC channel2 output buffer disable
-            BOFF2: u1,
-            ///  DAC channel2 trigger enable
-            TEN2: u1,
-            ///  DAC channel2 trigger selection
-            TSEL2: u3,
-            ///  DAC channel2 noise/triangle wave generation enable
-            WAVE2: u2,
-            ///  DAC channel2 mask/amplitude selector
-            MAMP2: u4,
-            ///  DAC channel2 DMA enable
-            DMAEN2: u1,
-            ///  DAC channel2 DMA underrun interrupt enable
-            DMAUDRIE2: u1,
-            padding: u2,
-        }),
-        ///  software trigger register
-        SWTRIGR: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 software trigger
-            SWTRIG1: u1,
-            ///  DAC channel2 software trigger
-            SWTRIG2: u1,
-            padding: u30,
-        }),
-        ///  channel1 12-bit right-aligned data holding register
-        DHR12R1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 12-bit right-aligned data
-            DACC1DHR: u12,
-            padding: u20,
-        }),
-        ///  channel1 12-bit left aligned data holding register
-        DHR12L1: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel1 12-bit left-aligned data
-            DACC1DHR: u12,
-            padding: u16,
-        }),
-        ///  channel1 8-bit right aligned data holding register
-        DHR8R1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 8-bit right-aligned data
-            DACC1DHR: u8,
-            padding: u24,
-        }),
-        ///  channel2 12-bit right aligned data holding register
-        DHR12R2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 12-bit right-aligned data
-            DACC2DHR: u12,
-            padding: u20,
-        }),
-        ///  channel2 12-bit left aligned data holding register
-        DHR12L2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel2 12-bit left-aligned data
-            DACC2DHR: u12,
-            padding: u16,
-        }),
-        ///  channel2 8-bit right-aligned data holding register
-        DHR8R2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 8-bit right-aligned data
-            DACC2DHR: u8,
-            padding: u24,
-        }),
-        ///  Dual DAC 12-bit right-aligned data holding register
-        DHR12RD: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 12-bit right-aligned data
-            DACC1DHR: u12,
-            reserved16: u4,
-            ///  DAC channel2 12-bit right-aligned data
-            DACC2DHR: u12,
-            padding: u4,
-        }),
-        ///  DUAL DAC 12-bit left aligned data holding register
-        DHR12LD: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel1 12-bit left-aligned data
-            DACC1DHR: u12,
-            reserved20: u4,
-            ///  DAC channel2 12-bit left-aligned data
-            DACC2DHR: u12,
-        }),
-        ///  DUAL DAC 8-bit right aligned data holding register
-        DHR8RD: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 8-bit right-aligned data
-            DACC1DHR: u8,
-            ///  DAC channel2 8-bit right-aligned data
-            DACC2DHR: u8,
-            padding: u16,
-        }),
-        ///  channel1 data output register
-        DOR1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 data output
-            DACC1DOR: u12,
-            padding: u20,
-        }),
-        ///  channel2 data output register
-        DOR2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 data output
-            DACC2DOR: u12,
-            padding: u20,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            reserved13: u13,
-            ///  DAC channel1 DMA underrun flag
-            DMAUDR1: u1,
-            reserved29: u15,
-            ///  DAC channel2 DMA underrun flag
-            DMAUDR2: u1,
-            padding: u2,
-        }),
-    };
-
-    ///  Power control
-    pub const PWR = extern struct {
-        ///  power control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Low-power deep sleep
-            LPDS: u1,
-            ///  Power down deepsleep
-            PDDS: u1,
-            ///  Clear wakeup flag
-            CWUF: u1,
-            ///  Clear standby flag
-            CSBF: u1,
-            ///  Power voltage detector enable
-            PVDE: u1,
-            ///  PVD level selection
-            PLS: u3,
-            ///  Disable backup domain write protection
-            DBP: u1,
-            ///  Flash power down in Stop mode
-            FPDS: u1,
-            padding: u22,
-        }),
-        ///  power control/status register
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  Wakeup flag
-            WUF: u1,
-            ///  Standby flag
-            SBF: u1,
-            ///  PVD output
-            PVDO: u1,
-            ///  Backup regulator ready
-            BRR: u1,
-            reserved8: u4,
-            ///  Enable WKUP pin
-            EWUP: u1,
-            ///  Backup regulator enable
-            BRE: u1,
-            reserved14: u4,
-            ///  Regulator voltage scaling output selection ready bit
-            VOSRDY: u1,
-            padding: u17,
-        }),
-    };
-
-    ///  Inter-integrated circuit
-    pub const I2C3 = extern struct {
-        ///  Control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral enable
-            PE: u1,
-            ///  SMBus mode
-            SMBUS: u1,
-            reserved3: u1,
-            ///  SMBus type
-            SMBTYPE: u1,
-            ///  ARP enable
-            ENARP: u1,
-            ///  PEC enable
-            ENPEC: u1,
-            ///  General call enable
-            ENGC: u1,
-            ///  Clock stretching disable (Slave mode)
-            NOSTRETCH: u1,
-            ///  Start generation
-            START: u1,
-            ///  Stop generation
-            STOP: u1,
-            ///  Acknowledge enable
-            ACK: u1,
-            ///  Acknowledge/PEC Position (for data reception)
-            POS: u1,
-            ///  Packet error checking
-            PEC: u1,
-            ///  SMBus alert
-            ALERT: u1,
-            reserved15: u1,
-            ///  Software reset
-            SWRST: u1,
-            padding: u16,
-        }),
-        ///  Control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral clock frequency
-            FREQ: u6,
-            reserved8: u2,
-            ///  Error interrupt enable
-            ITERREN: u1,
-            ///  Event interrupt enable
-            ITEVTEN: u1,
-            ///  Buffer interrupt enable
-            ITBUFEN: u1,
-            ///  DMA requests enable
-            DMAEN: u1,
-            ///  DMA last transfer
-            LAST: u1,
-            padding: u19,
-        }),
-        ///  Own address register 1
-        OAR1: mmio.Mmio(packed struct(u32) {
-            ///  Interface address
-            ADD0: u1,
-            ///  Interface address
-            ADD7: u7,
-            ///  Interface address
-            ADD10: u2,
-            reserved15: u5,
-            ///  Addressing mode (slave mode)
-            ADDMODE: u1,
-            padding: u16,
-        }),
-        ///  Own address register 2
-        OAR2: mmio.Mmio(packed struct(u32) {
-            ///  Dual addressing mode enable
-            ENDUAL: u1,
-            ///  Interface address
-            ADD2: u7,
-            padding: u24,
-        }),
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  8-bit data register
-            DR: u8,
-            padding: u24,
-        }),
-        ///  Status register 1
-        SR1: mmio.Mmio(packed struct(u32) {
-            ///  Start bit (Master mode)
-            SB: u1,
-            ///  Address sent (master mode)/matched (slave mode)
-            ADDR: u1,
-            ///  Byte transfer finished
-            BTF: u1,
-            ///  10-bit header sent (Master mode)
-            ADD10: u1,
-            ///  Stop detection (slave mode)
-            STOPF: u1,
-            reserved6: u1,
-            ///  Data register not empty (receivers)
-            RxNE: u1,
-            ///  Data register empty (transmitters)
-            TxE: u1,
-            ///  Bus error
-            BERR: u1,
-            ///  Arbitration lost (master mode)
-            ARLO: u1,
-            ///  Acknowledge failure
-            AF: u1,
-            ///  Overrun/Underrun
-            OVR: u1,
-            ///  PEC Error in reception
-            PECERR: u1,
-            reserved14: u1,
-            ///  Timeout or Tlow error
-            TIMEOUT: u1,
-            ///  SMBus alert
-            SMBALERT: u1,
-            padding: u16,
-        }),
-        ///  Status register 2
-        SR2: mmio.Mmio(packed struct(u32) {
-            ///  Master/slave
-            MSL: u1,
-            ///  Bus busy
-            BUSY: u1,
-            ///  Transmitter/receiver
-            TRA: u1,
-            reserved4: u1,
-            ///  General call address (Slave mode)
-            GENCALL: u1,
-            ///  SMBus device default address (Slave mode)
-            SMBDEFAULT: u1,
-            ///  SMBus host header (Slave mode)
-            SMBHOST: u1,
-            ///  Dual flag (Slave mode)
-            DUALF: u1,
-            ///  acket error checking register
-            PEC: u8,
-            padding: u16,
-        }),
-        ///  Clock control register
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Clock control register in Fast/Standard mode (Master mode)
-            CCR: u12,
-            reserved14: u2,
-            ///  Fast mode duty cycle
-            DUTY: u1,
-            ///  I2C master mode selection
-            F_S: u1,
-            padding: u16,
-        }),
-        ///  TRISE register
-        TRISE: mmio.Mmio(packed struct(u32) {
-            ///  Maximum rise time in Fast/Standard mode (Master mode)
-            TRISE: u6,
-            padding: u26,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_DEVICE = extern struct {
-        ///  OTG_FS device configuration register (OTG_FS_DCFG)
-        FS_DCFG: mmio.Mmio(packed struct(u32) {
-            ///  Device speed
-            DSPD: u2,
-            ///  Non-zero-length status OUT handshake
-            NZLSOHSK: u1,
-            reserved4: u1,
-            ///  Device address
-            DAD: u7,
-            ///  Periodic frame interval
-            PFIVL: u2,
-            padding: u19,
-        }),
-        ///  OTG_FS device control register (OTG_FS_DCTL)
-        FS_DCTL: mmio.Mmio(packed struct(u32) {
-            ///  Remote wakeup signaling
-            RWUSIG: u1,
-            ///  Soft disconnect
-            SDIS: u1,
-            ///  Global IN NAK status
-            GINSTS: u1,
-            ///  Global OUT NAK status
-            GONSTS: u1,
-            ///  Test control
-            TCTL: u3,
-            ///  Set global IN NAK
-            SGINAK: u1,
-            ///  Clear global IN NAK
-            CGINAK: u1,
-            ///  Set global OUT NAK
-            SGONAK: u1,
-            ///  Clear global OUT NAK
-            CGONAK: u1,
-            ///  Power-on programming done
-            POPRGDNE: u1,
-            padding: u20,
-        }),
-        ///  OTG_FS device status register (OTG_FS_DSTS)
-        FS_DSTS: mmio.Mmio(packed struct(u32) {
-            ///  Suspend status
-            SUSPSTS: u1,
-            ///  Enumerated speed
-            ENUMSPD: u2,
-            ///  Erratic error
-            EERR: u1,
-            reserved8: u4,
-            ///  Frame number of the received SOF
-            FNSOF: u14,
-            padding: u10,
-        }),
-        reserved16: [4]u8,
-        ///  OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
-        FS_DIEPMSK: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  Timeout condition mask (Non-isochronous endpoints)
-            TOM: u1,
-            ///  IN token received when TxFIFO empty mask
-            ITTXFEMSK: u1,
-            ///  IN token received with EP mismatch mask
-            INEPNMM: u1,
-            ///  IN endpoint NAK effective mask
-            INEPNEM: u1,
-            padding: u25,
-        }),
-        ///  OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
-        FS_DOEPMSK: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  SETUP phase done mask
-            STUPM: u1,
-            ///  OUT token received when endpoint disabled mask
-            OTEPDM: u1,
-            padding: u27,
-        }),
-        ///  OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
-        FS_DAINT: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint interrupt bits
-            IEPINT: u16,
-            ///  OUT endpoint interrupt bits
-            OEPINT: u16,
-        }),
-        ///  OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
-        FS_DAINTMSK: mmio.Mmio(packed struct(u32) {
-            ///  IN EP interrupt mask bits
-            IEPM: u16,
-            ///  OUT endpoint interrupt bits
-            OEPINT: u16,
-        }),
-        reserved40: [8]u8,
-        ///  OTG_FS device VBUS discharge time register
-        DVBUSDIS: mmio.Mmio(packed struct(u32) {
-            ///  Device VBUS discharge time
-            VBUSDT: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS device VBUS pulsing time register
-        DVBUSPULSE: mmio.Mmio(packed struct(u32) {
-            ///  Device VBUS pulsing time
-            DVBUSP: u12,
-            padding: u20,
-        }),
-        reserved52: [4]u8,
-        ///  OTG_FS device IN endpoint FIFO empty interrupt mask register
-        DIEPEMPMSK: mmio.Mmio(packed struct(u32) {
-            ///  IN EP Tx FIFO empty interrupt mask bits
-            INEPTXFEM: u16,
-            padding: u16,
-        }),
-        reserved256: [200]u8,
-        ///  OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
-        FS_DIEPCTL0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u2,
-            reserved15: u13,
-            ///  USB active endpoint
-            USBAEP: u1,
-            reserved17: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            STALL: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            reserved30: u2,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved264: [4]u8,
-        ///  device endpoint-x interrupt register
-        DIEPINT0: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved272: [4]u8,
-        ///  device endpoint-0 transfer size register
-        DIEPTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u7,
-            reserved19: u12,
-            ///  Packet count
-            PKTCNT: u2,
-            padding: u11,
-        }),
-        reserved280: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS0: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved288: [4]u8,
-        ///  OTG device endpoint-1 control register
-        DIEPCTL1: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            reserved21: u1,
-            ///  Stall
-            Stall: u1,
-            ///  TXFNUM
-            TXFNUM: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM/SD1PID
-            SODDFRM_SD1PID: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved296: [4]u8,
-        ///  device endpoint-1 interrupt register
-        DIEPINT1: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved304: [4]u8,
-        ///  device endpoint-1 transfer size register
-        DIEPTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        reserved312: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS1: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved320: [4]u8,
-        ///  OTG device endpoint-2 control register
-        DIEPCTL2: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            reserved21: u1,
-            ///  Stall
-            Stall: u1,
-            ///  TXFNUM
-            TXFNUM: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved328: [4]u8,
-        ///  device endpoint-2 interrupt register
-        DIEPINT2: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved336: [4]u8,
-        ///  device endpoint-2 transfer size register
-        DIEPTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        reserved344: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS2: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved352: [4]u8,
-        ///  OTG device endpoint-3 control register
-        DIEPCTL3: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            reserved21: u1,
-            ///  Stall
-            Stall: u1,
-            ///  TXFNUM
-            TXFNUM: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved360: [4]u8,
-        ///  device endpoint-3 interrupt register
-        DIEPINT3: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved368: [4]u8,
-        ///  device endpoint-3 transfer size register
-        DIEPTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        reserved376: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS3: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved768: [388]u8,
-        ///  device endpoint-0 control register
-        DOEPCTL0: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u2,
-            reserved15: u13,
-            ///  USBAEP
-            USBAEP: u1,
-            reserved17: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            reserved30: u2,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved776: [4]u8,
-        ///  device endpoint-0 interrupt register
-        DOEPINT0: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved784: [4]u8,
-        ///  device OUT endpoint-0 transfer size register
-        DOEPTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u7,
-            reserved19: u12,
-            ///  Packet count
-            PKTCNT: u1,
-            reserved29: u9,
-            ///  SETUP packet count
-            STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved800: [12]u8,
-        ///  device endpoint-1 control register
-        DOEPCTL1: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved808: [4]u8,
-        ///  device endpoint-1 interrupt register
-        DOEPINT1: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved816: [4]u8,
-        ///  device OUT endpoint-1 transfer size register
-        DOEPTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved832: [12]u8,
-        ///  device endpoint-2 control register
-        DOEPCTL2: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved840: [4]u8,
-        ///  device endpoint-2 interrupt register
-        DOEPINT2: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved848: [4]u8,
-        ///  device OUT endpoint-2 transfer size register
-        DOEPTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved864: [12]u8,
-        ///  device endpoint-3 control register
-        DOEPCTL3: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved872: [4]u8,
-        ///  device endpoint-3 interrupt register
-        DOEPINT3: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved880: [4]u8,
-        ///  device OUT endpoint-3 transfer size register
-        DOEPTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_HOST = extern struct {
-        ///  OTG_FS host configuration register (OTG_FS_HCFG)
-        FS_HCFG: mmio.Mmio(packed struct(u32) {
-            ///  FS/LS PHY clock select
-            FSLSPCS: u2,
-            ///  FS- and LS-only support
-            FSLSS: u1,
-            padding: u29,
-        }),
-        ///  OTG_FS Host frame interval register
-        HFIR: mmio.Mmio(packed struct(u32) {
-            ///  Frame interval
-            FRIVL: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
-        FS_HFNUM: mmio.Mmio(packed struct(u32) {
-            ///  Frame number
-            FRNUM: u16,
-            ///  Frame time remaining
-            FTREM: u16,
-        }),
-        reserved16: [4]u8,
-        ///  OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
-        FS_HPTXSTS: mmio.Mmio(packed struct(u32) {
-            ///  Periodic transmit data FIFO space available
-            PTXFSAVL: u16,
-            ///  Periodic transmit request queue space available
-            PTXQSAV: u8,
-            ///  Top of the periodic transmit request queue
-            PTXQTOP: u8,
-        }),
-        ///  OTG_FS Host all channels interrupt register
-        HAINT: mmio.Mmio(packed struct(u32) {
-            ///  Channel interrupts
-            HAINT: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS host all channels interrupt mask register
-        HAINTMSK: mmio.Mmio(packed struct(u32) {
-            ///  Channel interrupt mask
-            HAINTM: u16,
-            padding: u16,
-        }),
-        reserved64: [36]u8,
-        ///  OTG_FS host port control and status register (OTG_FS_HPRT)
-        FS_HPRT: mmio.Mmio(packed struct(u32) {
-            ///  Port connect status
-            PCSTS: u1,
-            ///  Port connect detected
-            PCDET: u1,
-            ///  Port enable
-            PENA: u1,
-            ///  Port enable/disable change
-            PENCHNG: u1,
-            ///  Port overcurrent active
-            POCA: u1,
-            ///  Port overcurrent change
-            POCCHNG: u1,
-            ///  Port resume
-            PRES: u1,
-            ///  Port suspend
-            PSUSP: u1,
-            ///  Port reset
-            PRST: u1,
-            reserved10: u1,
-            ///  Port line status
-            PLSTS: u2,
-            ///  Port power
-            PPWR: u1,
-            ///  Port test control
-            PTCTL: u4,
-            ///  Port speed
-            PSPD: u2,
-            padding: u13,
-        }),
-        reserved256: [188]u8,
-        ///  OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
-        FS_HCCHAR0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved264: [4]u8,
-        ///  OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
-        FS_HCINT0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
-        FS_HCINTMSK0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-0 transfer size register
-        FS_HCTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved288: [12]u8,
-        ///  OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)
-        FS_HCCHAR1: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved296: [4]u8,
-        ///  OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)
-        FS_HCINT1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)
-        FS_HCINTMSK1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-1 transfer size register
-        FS_HCTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved320: [12]u8,
-        ///  OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)
-        FS_HCCHAR2: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved328: [4]u8,
-        ///  OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)
-        FS_HCINT2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)
-        FS_HCINTMSK2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-2 transfer size register
-        FS_HCTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved352: [12]u8,
-        ///  OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)
-        FS_HCCHAR3: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved360: [4]u8,
-        ///  OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)
-        FS_HCINT3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)
-        FS_HCINTMSK3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-3 transfer size register
-        FS_HCTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved384: [12]u8,
-        ///  OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)
-        FS_HCCHAR4: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved392: [4]u8,
-        ///  OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)
-        FS_HCINT4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)
-        FS_HCINTMSK4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-x transfer size register
-        FS_HCTSIZ4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved416: [12]u8,
-        ///  OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)
-        FS_HCCHAR5: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved424: [4]u8,
-        ///  OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)
-        FS_HCINT5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)
-        FS_HCINTMSK5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-5 transfer size register
-        FS_HCTSIZ5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved448: [12]u8,
-        ///  OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)
-        FS_HCCHAR6: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved456: [4]u8,
-        ///  OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)
-        FS_HCINT6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)
-        FS_HCINTMSK6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-6 transfer size register
-        FS_HCTSIZ6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved480: [12]u8,
-        ///  OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)
-        FS_HCCHAR7: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved488: [4]u8,
-        ///  OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)
-        FS_HCINT7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)
-        FS_HCINTMSK7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-7 transfer size register
-        FS_HCTSIZ7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-    };
-
-    ///  Independent watchdog
-    pub const IWDG = extern struct {
-        ///  Key register
-        KR: mmio.Mmio(packed struct(u32) {
-            ///  Key value (write only, read 0000h)
-            KEY: u16,
-            padding: u16,
-        }),
-        ///  Prescaler register
-        PR: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler divider
-            PR: u3,
-            padding: u29,
-        }),
-        ///  Reload register
-        RLR: mmio.Mmio(packed struct(u32) {
-            ///  Watchdog counter reload value
-            RL: u12,
-            padding: u20,
-        }),
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Watchdog prescaler value update
-            PVU: u1,
-            ///  Watchdog counter reload value update
-            RVU: u1,
-            padding: u30,
-        }),
-    };
-
-    ///  Window watchdog
-    pub const WWDG = extern struct {
-        ///  Control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  7-bit counter (MSB to LSB)
-            T: u7,
-            ///  Activation bit
-            WDGA: u1,
-            padding: u24,
-        }),
-        ///  Configuration register
-        CFR: mmio.Mmio(packed struct(u32) {
-            ///  7-bit window value
-            W: u7,
-            ///  Timer base
-            WDGTB0: u1,
-            ///  Timer base
-            WDGTB1: u1,
-            ///  Early wakeup interrupt
-            EWI: u1,
-            padding: u22,
-        }),
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Early wakeup interrupt flag
-            EWIF: u1,
-            padding: u31,
-        }),
-    };
-
-    ///  Real-time clock
-    pub const RTC = extern struct {
-        ///  time register
-        TR: mmio.Mmio(packed struct(u32) {
-            ///  Second units in BCD format
-            SU: u4,
-            ///  Second tens in BCD format
-            ST: u3,
-            reserved8: u1,
-            ///  Minute units in BCD format
-            MNU: u4,
-            ///  Minute tens in BCD format
-            MNT: u3,
-            reserved16: u1,
-            ///  Hour units in BCD format
-            HU: u4,
-            ///  Hour tens in BCD format
-            HT: u2,
-            ///  AM/PM notation
-            PM: u1,
-            padding: u9,
-        }),
-        ///  date register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Date units in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            reserved8: u2,
-            ///  Month units in BCD format
-            MU: u4,
-            ///  Month tens in BCD format
-            MT: u1,
-            ///  Week day units
-            WDU: u3,
-            ///  Year units in BCD format
-            YU: u4,
-            ///  Year tens in BCD format
-            YT: u4,
-            padding: u8,
-        }),
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Wakeup clock selection
-            WCKSEL: u3,
-            ///  Time-stamp event active edge
-            TSEDGE: u1,
-            ///  Reference clock detection enable (50 or 60 Hz)
-            REFCKON: u1,
-            reserved6: u1,
-            ///  Hour format
-            FMT: u1,
-            ///  Coarse digital calibration enable
-            DCE: u1,
-            ///  Alarm A enable
-            ALRAE: u1,
-            ///  Alarm B enable
-            ALRBE: u1,
-            ///  Wakeup timer enable
-            WUTE: u1,
-            ///  Time stamp enable
-            TSE: u1,
-            ///  Alarm A interrupt enable
-            ALRAIE: u1,
-            ///  Alarm B interrupt enable
-            ALRBIE: u1,
-            ///  Wakeup timer interrupt enable
-            WUTIE: u1,
-            ///  Time-stamp interrupt enable
-            TSIE: u1,
-            ///  Add 1 hour (summer time change)
-            ADD1H: u1,
-            ///  Subtract 1 hour (winter time change)
-            SUB1H: u1,
-            ///  Backup
-            BKP: u1,
-            reserved20: u1,
-            ///  Output polarity
-            POL: u1,
-            ///  Output selection
-            OSEL: u2,
-            ///  Calibration output enable
-            COE: u1,
-            padding: u8,
-        }),
-        ///  initialization and status register
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  Alarm A write flag
-            ALRAWF: u1,
-            ///  Alarm B write flag
-            ALRBWF: u1,
-            ///  Wakeup timer write flag
-            WUTWF: u1,
-            ///  Shift operation pending
-            SHPF: u1,
-            ///  Initialization status flag
-            INITS: u1,
-            ///  Registers synchronization flag
-            RSF: u1,
-            ///  Initialization flag
-            INITF: u1,
-            ///  Initialization mode
-            INIT: u1,
-            ///  Alarm A flag
-            ALRAF: u1,
-            ///  Alarm B flag
-            ALRBF: u1,
-            ///  Wakeup timer flag
-            WUTF: u1,
-            ///  Time-stamp flag
-            TSF: u1,
-            ///  Time-stamp overflow flag
-            TSOVF: u1,
-            ///  Tamper detection flag
-            TAMP1F: u1,
-            ///  TAMPER2 detection flag
-            TAMP2F: u1,
-            reserved16: u1,
-            ///  Recalibration pending Flag
-            RECALPF: u1,
-            padding: u15,
-        }),
-        ///  prescaler register
-        PRER: mmio.Mmio(packed struct(u32) {
-            ///  Synchronous prescaler factor
-            PREDIV_S: u15,
-            reserved16: u1,
-            ///  Asynchronous prescaler factor
-            PREDIV_A: u7,
-            padding: u9,
-        }),
-        ///  wakeup timer register
-        WUTR: mmio.Mmio(packed struct(u32) {
-            ///  Wakeup auto-reload value bits
-            WUT: u16,
-            padding: u16,
-        }),
-        ///  calibration register
-        CALIBR: mmio.Mmio(packed struct(u32) {
-            ///  Digital calibration
-            DC: u5,
-            reserved7: u2,
-            ///  Digital calibration sign
-            DCS: u1,
-            padding: u24,
-        }),
-        ///  alarm A register
-        ALRMAR: mmio.Mmio(packed struct(u32) {
-            ///  Second units in BCD format
-            SU: u4,
-            ///  Second tens in BCD format
-            ST: u3,
-            ///  Alarm A seconds mask
-            MSK1: u1,
-            ///  Minute units in BCD format
-            MNU: u4,
-            ///  Minute tens in BCD format
-            MNT: u3,
-            ///  Alarm A minutes mask
-            MSK2: u1,
-            ///  Hour units in BCD format
-            HU: u4,
-            ///  Hour tens in BCD format
-            HT: u2,
-            ///  AM/PM notation
-            PM: u1,
-            ///  Alarm A hours mask
-            MSK3: u1,
-            ///  Date units or day in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            ///  Week day selection
-            WDSEL: u1,
-            ///  Alarm A date mask
-            MSK4: u1,
-        }),
-        ///  alarm B register
-        ALRMBR: mmio.Mmio(packed struct(u32) {
-            ///  Second units in BCD format
-            SU: u4,
-            ///  Second tens in BCD format
-            ST: u3,
-            ///  Alarm B seconds mask
-            MSK1: u1,
-            ///  Minute units in BCD format
-            MNU: u4,
-            ///  Minute tens in BCD format
-            MNT: u3,
-            ///  Alarm B minutes mask
-            MSK2: u1,
-            ///  Hour units in BCD format
-            HU: u4,
-            ///  Hour tens in BCD format
-            HT: u2,
-            ///  AM/PM notation
-            PM: u1,
-            ///  Alarm B hours mask
-            MSK3: u1,
-            ///  Date units or day in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            ///  Week day selection
-            WDSEL: u1,
-            ///  Alarm B date mask
-            MSK4: u1,
-        }),
-        ///  write protection register
-        WPR: mmio.Mmio(packed struct(u32) {
-            ///  Write protection key
-            KEY: u8,
-            padding: u24,
-        }),
-        ///  sub second register
-        SSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub second value
-            SS: u16,
-            padding: u16,
-        }),
-        ///  shift control register
-        SHIFTR: mmio.Mmio(packed struct(u32) {
-            ///  Subtract a fraction of a second
-            SUBFS: u15,
-            reserved31: u16,
-            ///  Add one second
-            ADD1S: u1,
-        }),
-        ///  time stamp time register
-        TSTR: mmio.Mmio(packed struct(u32) {
-            ///  Tamper 1 detection enable
-            TAMP1E: u1,
-            ///  Active level for tamper 1
-            TAMP1TRG: u1,
-            ///  Tamper interrupt enable
-            TAMPIE: u1,
-            reserved16: u13,
-            ///  TAMPER1 mapping
-            TAMP1INSEL: u1,
-            ///  TIMESTAMP mapping
-            TSINSEL: u1,
-            ///  AFO_ALARM output type
-            ALARMOUTTYPE: u1,
-            padding: u13,
-        }),
-        ///  time stamp date register
-        TSDR: mmio.Mmio(packed struct(u32) {
-            ///  Date units in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            reserved8: u2,
-            ///  Month units in BCD format
-            MU: u4,
-            ///  Month tens in BCD format
-            MT: u1,
-            ///  Week day units
-            WDU: u3,
-            padding: u16,
-        }),
-        ///  timestamp sub second register
-        TSSSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub second value
-            SS: u16,
-            padding: u16,
-        }),
-        ///  calibration register
-        CALR: mmio.Mmio(packed struct(u32) {
-            ///  Calibration minus
-            CALM: u9,
-            reserved13: u4,
-            ///  Use a 16-second calibration cycle period
-            CALW16: u1,
-            ///  Use an 8-second calibration cycle period
-            CALW8: u1,
-            ///  Increase frequency of RTC by 488.5 ppm
-            CALP: u1,
-            padding: u16,
-        }),
-        ///  tamper and alternate function configuration register
-        TAFCR: mmio.Mmio(packed struct(u32) {
-            ///  Tamper 1 detection enable
-            TAMP1E: u1,
-            ///  Active level for tamper 1
-            TAMP1TRG: u1,
-            ///  Tamper interrupt enable
-            TAMPIE: u1,
-            ///  Tamper 2 detection enable
-            TAMP2E: u1,
-            ///  Active level for tamper 2
-            TAMP2TRG: u1,
-            reserved7: u2,
-            ///  Activate timestamp on tamper detection event
-            TAMPTS: u1,
-            ///  Tamper sampling frequency
-            TAMPFREQ: u3,
-            ///  Tamper filter count
-            TAMPFLT: u2,
-            ///  Tamper precharge duration
-            TAMPPRCH: u2,
-            ///  TAMPER pull-up disable
-            TAMPPUDIS: u1,
-            ///  TAMPER1 mapping
-            TAMP1INSEL: u1,
-            ///  TIMESTAMP mapping
-            TSINSEL: u1,
-            ///  AFO_ALARM output type
-            ALARMOUTTYPE: u1,
-            padding: u13,
-        }),
-        ///  alarm A sub second register
-        ALRMASSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub seconds value
-            SS: u15,
-            reserved24: u9,
-            ///  Mask the most-significant bits starting at this bit
-            MASKSS: u4,
-            padding: u4,
-        }),
-        ///  alarm B sub second register
-        ALRMBSSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub seconds value
-            SS: u15,
-            reserved24: u9,
-            ///  Mask the most-significant bits starting at this bit
-            MASKSS: u4,
-            padding: u4,
-        }),
-        reserved80: [4]u8,
-        ///  backup register
-        BKP0R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP1R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP2R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP3R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP4R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP5R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP6R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP7R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP8R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP9R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP10R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP11R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP12R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP13R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP14R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP15R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP16R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP17R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP18R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP19R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-    };
-
-    ///  Universal synchronous asynchronous receiver transmitter
-    pub const UART4 = extern struct {
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Parity error
-            PE: u1,
-            ///  Framing error
-            FE: u1,
-            ///  Noise detected flag
-            NF: u1,
-            ///  Overrun error
-            ORE: u1,
-            ///  IDLE line detected
-            IDLE: u1,
-            ///  Read data register not empty
-            RXNE: u1,
-            ///  Transmission complete
-            TC: u1,
-            ///  Transmit data register empty
-            TXE: u1,
-            ///  LIN break detection flag
-            LBD: u1,
-            padding: u23,
-        }),
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data value
-            DR: u9,
-            padding: u23,
-        }),
-        ///  Baud rate register
-        BRR: mmio.Mmio(packed struct(u32) {
-            ///  fraction of USARTDIV
-            DIV_Fraction: u4,
-            ///  mantissa of USARTDIV
-            DIV_Mantissa: u12,
-            padding: u16,
-        }),
-        ///  Control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Send break
-            SBK: u1,
-            ///  Receiver wakeup
-            RWU: u1,
-            ///  Receiver enable
-            RE: u1,
-            ///  Transmitter enable
-            TE: u1,
-            ///  IDLE interrupt enable
-            IDLEIE: u1,
-            ///  RXNE interrupt enable
-            RXNEIE: u1,
-            ///  Transmission complete interrupt enable
-            TCIE: u1,
-            ///  TXE interrupt enable
-            TXEIE: u1,
-            ///  PE interrupt enable
-            PEIE: u1,
-            ///  Parity selection
-            PS: u1,
-            ///  Parity control enable
-            PCE: u1,
-            ///  Wakeup method
-            WAKE: u1,
-            ///  Word length
-            M: u1,
-            ///  USART enable
-            UE: u1,
-            reserved15: u1,
-            ///  Oversampling mode
-            OVER8: u1,
-            padding: u16,
-        }),
-        ///  Control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Address of the USART node
-            ADD: u4,
-            reserved5: u1,
-            ///  lin break detection length
-            LBDL: u1,
-            ///  LIN break detection interrupt enable
-            LBDIE: u1,
-            reserved12: u5,
-            ///  STOP bits
-            STOP: u2,
-            ///  LIN mode enable
-            LINEN: u1,
-            padding: u17,
-        }),
-        ///  Control register 3
-        CR3: mmio.Mmio(packed struct(u32) {
-            ///  Error interrupt enable
-            EIE: u1,
-            ///  IrDA mode enable
-            IREN: u1,
-            ///  IrDA low-power
-            IRLP: u1,
-            ///  Half-duplex selection
-            HDSEL: u1,
-            reserved6: u2,
-            ///  DMA enable receiver
-            DMAR: u1,
-            ///  DMA enable transmitter
-            DMAT: u1,
-            reserved11: u3,
-            ///  One sample bit method enable
-            ONEBIT: u1,
-            padding: u20,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_GLOBAL = extern struct {
-        ///  OTG_FS control and status register (OTG_FS_GOTGCTL)
-        FS_GOTGCTL: mmio.Mmio(packed struct(u32) {
-            ///  Session request success
-            SRQSCS: u1,
-            ///  Session request
-            SRQ: u1,
-            reserved8: u6,
-            ///  Host negotiation success
-            HNGSCS: u1,
-            ///  HNP request
-            HNPRQ: u1,
-            ///  Host set HNP enable
-            HSHNPEN: u1,
-            ///  Device HNP enabled
-            DHNPEN: u1,
-            reserved16: u4,
-            ///  Connector ID status
-            CIDSTS: u1,
-            ///  Long/short debounce time
-            DBCT: u1,
-            ///  A-session valid
-            ASVLD: u1,
-            ///  B-session valid
-            BSVLD: u1,
-            padding: u12,
-        }),
-        ///  OTG_FS interrupt register (OTG_FS_GOTGINT)
-        FS_GOTGINT: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Session end detected
-            SEDET: u1,
-            reserved8: u5,
-            ///  Session request success status change
-            SRSSCHG: u1,
-            ///  Host negotiation success status change
-            HNSSCHG: u1,
-            reserved17: u7,
-            ///  Host negotiation detected
-            HNGDET: u1,
-            ///  A-device timeout change
-            ADTOCHG: u1,
-            ///  Debounce done
-            DBCDNE: u1,
-            padding: u12,
-        }),
-        ///  OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
-        FS_GAHBCFG: mmio.Mmio(packed struct(u32) {
-            ///  Global interrupt mask
-            GINT: u1,
-            reserved7: u6,
-            ///  TxFIFO empty level
-            TXFELVL: u1,
-            ///  Periodic TxFIFO empty level
-            PTXFELVL: u1,
-            padding: u23,
-        }),
-        ///  OTG_FS USB configuration register (OTG_FS_GUSBCFG)
-        FS_GUSBCFG: mmio.Mmio(packed struct(u32) {
-            ///  FS timeout calibration
-            TOCAL: u3,
-            reserved6: u3,
-            ///  Full Speed serial transceiver select
-            PHYSEL: u1,
-            reserved8: u1,
-            ///  SRP-capable
-            SRPCAP: u1,
-            ///  HNP-capable
-            HNPCAP: u1,
-            ///  USB turnaround time
-            TRDT: u4,
-            reserved29: u15,
-            ///  Force host mode
-            FHMOD: u1,
-            ///  Force device mode
-            FDMOD: u1,
-            ///  Corrupt Tx packet
-            CTXPKT: u1,
-        }),
-        ///  OTG_FS reset register (OTG_FS_GRSTCTL)
-        FS_GRSTCTL: mmio.Mmio(packed struct(u32) {
-            ///  Core soft reset
-            CSRST: u1,
-            ///  HCLK soft reset
-            HSRST: u1,
-            ///  Host frame counter reset
-            FCRST: u1,
-            reserved4: u1,
-            ///  RxFIFO flush
-            RXFFLSH: u1,
-            ///  TxFIFO flush
-            TXFFLSH: u1,
-            ///  TxFIFO number
-            TXFNUM: u5,
-            reserved31: u20,
-            ///  AHB master idle
-            AHBIDL: u1,
-        }),
-        ///  OTG_FS core interrupt register (OTG_FS_GINTSTS)
-        FS_GINTSTS: mmio.Mmio(packed struct(u32) {
-            ///  Current mode of operation
-            CMOD: u1,
-            ///  Mode mismatch interrupt
-            MMIS: u1,
-            ///  OTG interrupt
-            OTGINT: u1,
-            ///  Start of frame
-            SOF: u1,
-            ///  RxFIFO non-empty
-            RXFLVL: u1,
-            ///  Non-periodic TxFIFO empty
-            NPTXFE: u1,
-            ///  Global IN non-periodic NAK effective
-            GINAKEFF: u1,
-            ///  Global OUT NAK effective
-            GOUTNAKEFF: u1,
-            reserved10: u2,
-            ///  Early suspend
-            ESUSP: u1,
-            ///  USB suspend
-            USBSUSP: u1,
-            ///  USB reset
-            USBRST: u1,
-            ///  Enumeration done
-            ENUMDNE: u1,
-            ///  Isochronous OUT packet dropped interrupt
-            ISOODRP: u1,
-            ///  End of periodic frame interrupt
-            EOPF: u1,
-            reserved18: u2,
-            ///  IN endpoint interrupt
-            IEPINT: u1,
-            ///  OUT endpoint interrupt
-            OEPINT: u1,
-            ///  Incomplete isochronous IN transfer
-            IISOIXFR: u1,
-            ///  Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)
-            IPXFR_INCOMPISOOUT: u1,
-            reserved24: u2,
-            ///  Host port interrupt
-            HPRTINT: u1,
-            ///  Host channels interrupt
-            HCINT: u1,
-            ///  Periodic TxFIFO empty
-            PTXFE: u1,
-            reserved28: u1,
-            ///  Connector ID status change
-            CIDSCHG: u1,
-            ///  Disconnect detected interrupt
-            DISCINT: u1,
-            ///  Session request/new session detected interrupt
-            SRQINT: u1,
-            ///  Resume/remote wakeup detected interrupt
-            WKUPINT: u1,
-        }),
-        ///  OTG_FS interrupt mask register (OTG_FS_GINTMSK)
-        FS_GINTMSK: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Mode mismatch interrupt mask
-            MMISM: u1,
-            ///  OTG interrupt mask
-            OTGINT: u1,
-            ///  Start of frame mask
-            SOFM: u1,
-            ///  Receive FIFO non-empty mask
-            RXFLVLM: u1,
-            ///  Non-periodic TxFIFO empty mask
-            NPTXFEM: u1,
-            ///  Global non-periodic IN NAK effective mask
-            GINAKEFFM: u1,
-            ///  Global OUT NAK effective mask
-            GONAKEFFM: u1,
-            reserved10: u2,
-            ///  Early suspend mask
-            ESUSPM: u1,
-            ///  USB suspend mask
-            USBSUSPM: u1,
-            ///  USB reset mask
-            USBRST: u1,
-            ///  Enumeration done mask
-            ENUMDNEM: u1,
-            ///  Isochronous OUT packet dropped interrupt mask
-            ISOODRPM: u1,
-            ///  End of periodic frame interrupt mask
-            EOPFM: u1,
-            reserved17: u1,
-            ///  Endpoint mismatch interrupt mask
-            EPMISM: u1,
-            ///  IN endpoints interrupt mask
-            IEPINT: u1,
-            ///  OUT endpoints interrupt mask
-            OEPINT: u1,
-            ///  Incomplete isochronous IN transfer mask
-            IISOIXFRM: u1,
-            ///  Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)
-            IPXFRM_IISOOXFRM: u1,
-            reserved24: u2,
-            ///  Host port interrupt mask
-            PRTIM: u1,
-            ///  Host channels interrupt mask
-            HCIM: u1,
-            ///  Periodic TxFIFO empty mask
-            PTXFEM: u1,
-            reserved28: u1,
-            ///  Connector ID status change mask
-            CIDSCHGM: u1,
-            ///  Disconnect detected interrupt mask
-            DISCINT: u1,
-            ///  Session request/new session detected interrupt mask
-            SRQIM: u1,
-            ///  Resume/remote wakeup detected interrupt mask
-            WUIM: u1,
-        }),
-        ///  OTG_FS Receive status debug read(Device mode)
-        FS_GRXSTSR_Device: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Byte count
-            BCNT: u11,
-            ///  Data PID
-            DPID: u2,
-            ///  Packet status
-            PKTSTS: u4,
-            ///  Frame number
-            FRMNUM: u4,
-            padding: u7,
-        }),
-        reserved36: [4]u8,
-        ///  OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
-        FS_GRXFSIZ: mmio.Mmio(packed struct(u32) {
-            ///  RxFIFO depth
-            RXFD: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS non-periodic transmit FIFO size register (Device mode)
-        FS_GNPTXFSIZ_Device: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint 0 transmit RAM start address
-            TX0FSA: u16,
-            ///  Endpoint 0 TxFIFO depth
-            TX0FD: u16,
-        }),
-        ///  OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)
-        FS_GNPTXSTS: mmio.Mmio(packed struct(u32) {
-            ///  Non-periodic TxFIFO space available
-            NPTXFSAV: u16,
-            ///  Non-periodic transmit request queue space available
-            NPTQXSAV: u8,
-            ///  Top of the non-periodic transmit request queue
-            NPTXQTOP: u7,
-            padding: u1,
-        }),
-        reserved56: [8]u8,
-        ///  OTG_FS general core configuration register (OTG_FS_GCCFG)
-        FS_GCCFG: mmio.Mmio(packed struct(u32) {
-            reserved16: u16,
-            ///  Power down
-            PWRDWN: u1,
-            reserved18: u1,
-            ///  Enable the VBUS sensing device
-            VBUSASEN: u1,
-            ///  Enable the VBUS sensing device
-            VBUSBSEN: u1,
-            ///  SOF output enable
-            SOFOUTEN: u1,
-            padding: u11,
-        }),
-        ///  core ID register
-        FS_CID: mmio.Mmio(packed struct(u32) {
-            ///  Product ID field
-            PRODUCT_ID: u32,
-        }),
-        reserved256: [192]u8,
-        ///  OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
-        FS_HPTXFSIZ: mmio.Mmio(packed struct(u32) {
-            ///  Host periodic TxFIFO start address
-            PTXSA: u16,
-            ///  Host periodic TxFIFO depth
-            PTXFSIZ: u16,
-        }),
-        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)
-        FS_DIEPTXF1: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFO2 transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)
-        FS_DIEPTXF2: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFO3 transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)
-        FS_DIEPTXF3: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFO4 transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-    };
-
-    ///  Cryptographic processor
-    pub const CRC = extern struct {
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data Register
-            DR: u32,
-        }),
-        ///  Independent Data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Independent Data register
-            IDR: u8,
-            padding: u24,
-        }),
-        ///  Control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Control regidter
-            CR: u1,
-            padding: u31,
-        }),
-    };
-
-    ///  Ethernet: DMA controller operation
-    pub const Ethernet_DMA = extern struct {
-        ///  Ethernet DMA bus mode register
-        DMABMR: mmio.Mmio(packed struct(u32) {
-            ///  SR
-            SR: u1,
-            ///  DA
-            DA: u1,
-            ///  DSL
-            DSL: u5,
-            ///  EDFE
-            EDFE: u1,
-            ///  PBL
-            PBL: u6,
-            ///  RTPR
-            RTPR: u2,
-            ///  FB
-            FB: u1,
-            ///  RDP
-            RDP: u6,
-            ///  USP
-            USP: u1,
-            ///  FPM
-            FPM: u1,
-            ///  AAB
-            AAB: u1,
-            ///  MB
-            MB: u1,
-            padding: u5,
-        }),
-        ///  Ethernet DMA transmit poll demand register
-        DMATPDR: mmio.Mmio(packed struct(u32) {
-            ///  TPD
-            TPD: u32,
-        }),
-        ///  EHERNET DMA receive poll demand register
-        DMARPDR: mmio.Mmio(packed struct(u32) {
-            ///  RPD
-            RPD: u32,
-        }),
-        ///  Ethernet DMA receive descriptor list address register
-        DMARDLAR: mmio.Mmio(packed struct(u32) {
-            ///  SRL
-            SRL: u32,
-        }),
-        ///  Ethernet DMA transmit descriptor list address register
-        DMATDLAR: mmio.Mmio(packed struct(u32) {
-            ///  STL
-            STL: u32,
-        }),
-        ///  Ethernet DMA status register
-        DMASR: mmio.Mmio(packed struct(u32) {
-            ///  TS
-            TS: u1,
-            ///  TPSS
-            TPSS: u1,
-            ///  TBUS
-            TBUS: u1,
-            ///  TJTS
-            TJTS: u1,
-            ///  ROS
-            ROS: u1,
-            ///  TUS
-            TUS: u1,
-            ///  RS
-            RS: u1,
-            ///  RBUS
-            RBUS: u1,
-            ///  RPSS
-            RPSS: u1,
-            ///  PWTS
-            PWTS: u1,
-            ///  ETS
-            ETS: u1,
-            reserved13: u2,
-            ///  FBES
-            FBES: u1,
-            ///  ERS
-            ERS: u1,
-            ///  AIS
-            AIS: u1,
-            ///  NIS
-            NIS: u1,
-            ///  RPS
-            RPS: u3,
-            ///  TPS
-            TPS: u3,
-            ///  EBS
-            EBS: u3,
-            reserved27: u1,
-            ///  MMCS
-            MMCS: u1,
-            ///  PMTS
-            PMTS: u1,
-            ///  TSTS
-            TSTS: u1,
-            padding: u2,
-        }),
-        ///  Ethernet DMA operation mode register
-        DMAOMR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  SR
-            SR: u1,
-            ///  OSF
-            OSF: u1,
-            ///  RTC
-            RTC: u2,
-            reserved6: u1,
-            ///  FUGF
-            FUGF: u1,
-            ///  FEF
-            FEF: u1,
-            reserved13: u5,
-            ///  ST
-            ST: u1,
-            ///  TTC
-            TTC: u3,
-            reserved20: u3,
-            ///  FTF
-            FTF: u1,
-            ///  TSF
-            TSF: u1,
-            reserved24: u2,
-            ///  DFRF
-            DFRF: u1,
-            ///  RSF
-            RSF: u1,
-            ///  DTCEFD
-            DTCEFD: u1,
-            padding: u5,
-        }),
-        ///  Ethernet DMA interrupt enable register
-        DMAIER: mmio.Mmio(packed struct(u32) {
-            ///  TIE
-            TIE: u1,
-            ///  TPSIE
-            TPSIE: u1,
-            ///  TBUIE
-            TBUIE: u1,
-            ///  TJTIE
-            TJTIE: u1,
-            ///  ROIE
-            ROIE: u1,
-            ///  TUIE
-            TUIE: u1,
-            ///  RIE
-            RIE: u1,
-            ///  RBUIE
-            RBUIE: u1,
-            ///  RPSIE
-            RPSIE: u1,
-            ///  RWTIE
-            RWTIE: u1,
-            ///  ETIE
-            ETIE: u1,
-            reserved13: u2,
-            ///  FBEIE
-            FBEIE: u1,
-            ///  ERIE
-            ERIE: u1,
-            ///  AISE
-            AISE: u1,
-            ///  NISE
-            NISE: u1,
-            padding: u15,
-        }),
-        ///  Ethernet DMA missed frame and buffer overflow counter register
-        DMAMFBOCR: mmio.Mmio(packed struct(u32) {
-            ///  MFC
-            MFC: u16,
-            ///  OMFC
-            OMFC: u1,
-            ///  MFA
-            MFA: u11,
-            ///  OFOC
-            OFOC: u1,
-            padding: u3,
-        }),
-        ///  Ethernet DMA receive status watchdog timer register
-        DMARSWTR: mmio.Mmio(packed struct(u32) {
-            ///  RSWTC
-            RSWTC: u8,
-            padding: u24,
-        }),
-        reserved72: [32]u8,
-        ///  Ethernet DMA current host transmit descriptor register
-        DMACHTDR: mmio.Mmio(packed struct(u32) {
-            ///  HTDAP
-            HTDAP: u32,
-        }),
-        ///  Ethernet DMA current host receive descriptor register
-        DMACHRDR: mmio.Mmio(packed struct(u32) {
-            ///  HRDAP
-            HRDAP: u32,
-        }),
-        ///  Ethernet DMA current host transmit buffer address register
-        DMACHTBAR: mmio.Mmio(packed struct(u32) {
-            ///  HTBAP
-            HTBAP: u32,
-        }),
-        ///  Ethernet DMA current host receive buffer address register
-        DMACHRBAR: mmio.Mmio(packed struct(u32) {
-            ///  HRBAP
-            HRBAP: u32,
-        }),
-    };
-
-    ///  Common ADC registers
-    pub const C_ADC = extern struct {
-        ///  ADC Common status register
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog flag of ADC 1
-            AWD1: u1,
-            ///  End of conversion of ADC 1
-            EOC1: u1,
-            ///  Injected channel end of conversion of ADC 1
-            JEOC1: u1,
-            ///  Injected channel Start flag of ADC 1
-            JSTRT1: u1,
-            ///  Regular channel Start flag of ADC 1
-            STRT1: u1,
-            ///  Overrun flag of ADC 1
-            OVR1: u1,
-            reserved8: u2,
-            ///  Analog watchdog flag of ADC 2
-            AWD2: u1,
-            ///  End of conversion of ADC 2
-            EOC2: u1,
-            ///  Injected channel end of conversion of ADC 2
-            JEOC2: u1,
-            ///  Injected channel Start flag of ADC 2
-            JSTRT2: u1,
-            ///  Regular channel Start flag of ADC 2
-            STRT2: u1,
-            ///  Overrun flag of ADC 2
-            OVR2: u1,
-            reserved16: u2,
-            ///  Analog watchdog flag of ADC 3
-            AWD3: u1,
-            ///  End of conversion of ADC 3
-            EOC3: u1,
-            ///  Injected channel end of conversion of ADC 3
-            JEOC3: u1,
-            ///  Injected channel Start flag of ADC 3
-            JSTRT3: u1,
-            ///  Regular channel Start flag of ADC 3
-            STRT3: u1,
-            ///  Overrun flag of ADC3
-            OVR3: u1,
-            padding: u10,
-        }),
-        ///  ADC common control register
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Multi ADC mode selection
-            MULT: u5,
-            reserved8: u3,
-            ///  Delay between 2 sampling phases
-            DELAY: u4,
-            reserved13: u1,
-            ///  DMA disable selection for multi-ADC mode
-            DDS: u1,
-            ///  Direct memory access mode for multi ADC mode
-            DMA: u2,
-            ///  ADC prescaler
-            ADCPRE: u2,
-            reserved22: u4,
-            ///  VBAT enable
-            VBATE: u1,
-            ///  Temperature sensor and VREFINT enable
-            TSVREFE: u1,
-            padding: u8,
-        }),
-        ///  ADC common regular data register for dual and triple modes
-        CDR: mmio.Mmio(packed struct(u32) {
-            ///  1st data item of a pair of regular conversions
-            DATA1: u16,
-            ///  2nd data item of a pair of regular conversions
-            DATA2: u16,
-        }),
-    };
-
-    ///  Advanced-timers
-    pub const TIM1 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/compare preloaded control
-            CCPC: u1,
-            reserved2: u1,
-            ///  Capture/compare control update selection
-            CCUS: u1,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            ///  Output Idle state 1
-            OIS1: u1,
-            ///  Output Idle state 1
-            OIS1N: u1,
-            ///  Output Idle state 2
-            OIS2: u1,
-            ///  Output Idle state 2
-            OIS2N: u1,
-            ///  Output Idle state 3
-            OIS3: u1,
-            ///  Output Idle state 3
-            OIS3N: u1,
-            ///  Output Idle state 4
-            OIS4: u1,
-            padding: u17,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            padding: u16,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            ///  COM interrupt enable
-            COMIE: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            ///  Break interrupt enable
-            BIE: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            ///  COM DMA request enable
-            COMDE: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            ///  COM interrupt flag
-            COMIF: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            ///  Break interrupt flag
-            BIF: u1,
-            reserved9: u1,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            padding: u19,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            ///  Capture/Compare control update generation
-            COMG: u1,
-            ///  Trigger generation
-            TG: u1,
-            ///  Break generation
-            BG: u1,
-            padding: u24,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            ///  Output Compare 1 clear enable
-            OC1CE: u1,
-            ///  Capture/Compare 2 selection
-            CC2S: u2,
-            ///  Output Compare 2 fast enable
-            OC2FE: u1,
-            ///  Output Compare 2 preload enable
-            OC2PE: u1,
-            ///  Output Compare 2 mode
-            OC2M: u3,
-            ///  Output Compare 2 clear enable
-            OC2CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare mode register 2 (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 3 selection
-            CC3S: u2,
-            ///  Output compare 3 fast enable
-            OC3FE: u1,
-            ///  Output compare 3 preload enable
-            OC3PE: u1,
-            ///  Output compare 3 mode
-            OC3M: u3,
-            ///  Output compare 3 clear enable
-            OC3CE: u1,
-            ///  Capture/Compare 4 selection
-            CC4S: u2,
-            ///  Output compare 4 fast enable
-            OC4FE: u1,
-            ///  Output compare 4 preload enable
-            OC4PE: u1,
-            ///  Output compare 4 mode
-            OC4M: u3,
-            ///  Output compare 4 clear enable
-            OC4CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            ///  Capture/Compare 1 complementary output enable
-            CC1NE: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            ///  Capture/Compare 2 complementary output enable
-            CC2NE: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            ///  Capture/Compare 3 complementary output enable
-            CC3NE: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            padding: u18,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        ///  repetition counter register
-        RCR: mmio.Mmio(packed struct(u32) {
-            ///  Repetition counter value
-            REP: u8,
-            padding: u24,
-        }),
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 2 value
-            CCR2: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare value
-            CCR3: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare value
-            CCR4: u16,
-            padding: u16,
-        }),
-        ///  break and dead-time register
-        BDTR: mmio.Mmio(packed struct(u32) {
-            ///  Dead-time generator setup
-            DTG: u8,
-            ///  Lock configuration
-            LOCK: u2,
-            ///  Off-state selection for Idle mode
-            OSSI: u1,
-            ///  Off-state selection for Run mode
-            OSSR: u1,
-            ///  Break enable
-            BKE: u1,
-            ///  Break polarity
-            BKP: u1,
-            ///  Automatic output enable
-            AOE: u1,
-            ///  Main output enable
-            MOE: u1,
-            padding: u16,
-        }),
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Ethernet: Precision time protocol
-    pub const Ethernet_PTP = extern struct {
-        ///  Ethernet PTP time stamp control register
-        PTPTSCR: mmio.Mmio(packed struct(u32) {
-            ///  TSE
-            TSE: u1,
-            ///  TSFCU
-            TSFCU: u1,
-            ///  TSSTI
-            TSSTI: u1,
-            ///  TSSTU
-            TSSTU: u1,
-            ///  TSITE
-            TSITE: u1,
-            ///  TTSARU
-            TTSARU: u1,
-            reserved8: u2,
-            ///  TSSARFE
-            TSSARFE: u1,
-            ///  TSSSR
-            TSSSR: u1,
-            ///  TSPTPPSV2E
-            TSPTPPSV2E: u1,
-            ///  TSSPTPOEFE
-            TSSPTPOEFE: u1,
-            ///  TSSIPV6FE
-            TSSIPV6FE: u1,
-            ///  TSSIPV4FE
-            TSSIPV4FE: u1,
-            ///  TSSEME
-            TSSEME: u1,
-            ///  TSSMRME
-            TSSMRME: u1,
-            ///  TSCNT
-            TSCNT: u2,
-            ///  TSPFFMAE
-            TSPFFMAE: u1,
-            padding: u13,
-        }),
-        ///  Ethernet PTP subsecond increment register
-        PTPSSIR: mmio.Mmio(packed struct(u32) {
-            ///  STSSI
-            STSSI: u8,
-            padding: u24,
-        }),
-        ///  Ethernet PTP time stamp high register
-        PTPTSHR: mmio.Mmio(packed struct(u32) {
-            ///  STS
-            STS: u32,
-        }),
-        ///  Ethernet PTP time stamp low register
-        PTPTSLR: mmio.Mmio(packed struct(u32) {
-            ///  STSS
-            STSS: u31,
-            ///  STPNS
-            STPNS: u1,
-        }),
-        ///  Ethernet PTP time stamp high update register
-        PTPTSHUR: mmio.Mmio(packed struct(u32) {
-            ///  TSUS
-            TSUS: u32,
-        }),
-        ///  Ethernet PTP time stamp low update register
-        PTPTSLUR: mmio.Mmio(packed struct(u32) {
-            ///  TSUSS
-            TSUSS: u31,
-            ///  TSUPNS
-            TSUPNS: u1,
-        }),
-        ///  Ethernet PTP time stamp addend register
-        PTPTSAR: mmio.Mmio(packed struct(u32) {
-            ///  TSA
-            TSA: u32,
-        }),
-        ///  Ethernet PTP target time high register
-        PTPTTHR: mmio.Mmio(packed struct(u32) {
-            ///  0
-            TTSH: u32,
-        }),
-        ///  Ethernet PTP target time low register
-        PTPTTLR: mmio.Mmio(packed struct(u32) {
-            ///  TTSL
-            TTSL: u32,
-        }),
-        reserved40: [4]u8,
-        ///  Ethernet PTP time stamp status register
-        PTPTSSR: mmio.Mmio(packed struct(u32) {
-            ///  TSSO
-            TSSO: u1,
-            ///  TSTTR
-            TSTTR: u1,
-            padding: u30,
-        }),
-        ///  Ethernet PTP PPS control register
-        PTPPPSCR: mmio.Mmio(packed struct(u32) {
-            ///  TSSO
-            TSSO: u1,
-            ///  TSTTR
-            TSTTR: u1,
-            padding: u30,
-        }),
-    };
-
-    ///  General purpose timers
-    pub const TIM2 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            padding: u24,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            padding: u16,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            reserved6: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            reserved8: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            reserved14: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            reserved6: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            reserved9: u2,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            padding: u19,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            reserved6: u1,
-            ///  Trigger generation
-            TG: u1,
-            padding: u25,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC1S
-            CC1S: u2,
-            ///  OC1FE
-            OC1FE: u1,
-            ///  OC1PE
-            OC1PE: u1,
-            ///  OC1M
-            OC1M: u3,
-            ///  OC1CE
-            OC1CE: u1,
-            ///  CC2S
-            CC2S: u2,
-            ///  OC2FE
-            OC2FE: u1,
-            ///  OC2PE
-            OC2PE: u1,
-            ///  OC2M
-            OC2M: u3,
-            ///  OC2CE
-            OC2CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare mode register 2 (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC3S
-            CC3S: u2,
-            ///  OC3FE
-            OC3FE: u1,
-            ///  OC3PE
-            OC3PE: u1,
-            ///  OC3M
-            OC3M: u3,
-            ///  OC3CE
-            OC3CE: u1,
-            ///  CC4S
-            CC4S: u2,
-            ///  OC4FE
-            OC4FE: u1,
-            ///  OC4PE
-            OC4PE: u1,
-            ///  OC4M
-            OC4M: u3,
-            ///  O24CE
-            O24CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved7: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            reserved11: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            reserved15: u1,
-            ///  Capture/Compare 4 output Polarity
-            CC4NP: u1,
-            padding: u16,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  Low counter value
-            CNT_L: u16,
-            ///  High counter value
-            CNT_H: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Low Auto-reload value
-            ARR_L: u16,
-            ///  High Auto-reload value
-            ARR_H: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 1 value
-            CCR1_L: u16,
-            ///  High Capture/Compare 1 value
-            CCR1_H: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 2 value
-            CCR2_L: u16,
-            ///  High Capture/Compare 2 value
-            CCR2_H: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR3_L: u16,
-            ///  High Capture/Compare value
-            CCR3_H: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR4_L: u16,
-            ///  High Capture/Compare value
-            CCR4_H: u16,
-        }),
-        reserved72: [4]u8,
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-        ///  TIM5 option register
-        OR: mmio.Mmio(packed struct(u32) {
-            reserved10: u10,
-            ///  Timer Input 4 remap
-            ITR1_RMP: u2,
-            padding: u20,
-        }),
-    };
-
-    ///  General purpose timers
-    pub const TIM3 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            padding: u24,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            padding: u16,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            reserved6: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            reserved8: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            reserved14: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            reserved6: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            reserved9: u2,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            padding: u19,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            reserved6: u1,
-            ///  Trigger generation
-            TG: u1,
-            padding: u25,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC1S
-            CC1S: u2,
-            ///  OC1FE
-            OC1FE: u1,
-            ///  OC1PE
-            OC1PE: u1,
-            ///  OC1M
-            OC1M: u3,
-            ///  OC1CE
-            OC1CE: u1,
-            ///  CC2S
-            CC2S: u2,
-            ///  OC2FE
-            OC2FE: u1,
-            ///  OC2PE
-            OC2PE: u1,
-            ///  OC2M
-            OC2M: u3,
-            ///  OC2CE
-            OC2CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare mode register 2 (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC3S
-            CC3S: u2,
-            ///  OC3FE
-            OC3FE: u1,
-            ///  OC3PE
-            OC3PE: u1,
-            ///  OC3M
-            OC3M: u3,
-            ///  OC3CE
-            OC3CE: u1,
-            ///  CC4S
-            CC4S: u2,
-            ///  OC4FE
-            OC4FE: u1,
-            ///  OC4PE
-            OC4PE: u1,
-            ///  OC4M
-            OC4M: u3,
-            ///  O24CE
-            O24CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved7: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            reserved11: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            reserved15: u1,
-            ///  Capture/Compare 4 output Polarity
-            CC4NP: u1,
-            padding: u16,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  Low counter value
-            CNT_L: u16,
-            ///  High counter value
-            CNT_H: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Low Auto-reload value
-            ARR_L: u16,
-            ///  High Auto-reload value
-            ARR_H: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 1 value
-            CCR1_L: u16,
-            ///  High Capture/Compare 1 value
-            CCR1_H: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 2 value
-            CCR2_L: u16,
-            ///  High Capture/Compare 2 value
-            CCR2_H: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR3_L: u16,
-            ///  High Capture/Compare value
-            CCR3_H: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR4_L: u16,
-            ///  High Capture/Compare value
-            CCR4_H: u16,
-        }),
-        reserved72: [4]u8,
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Ethernet: MAC management counters
-    pub const Ethernet_MMC = extern struct {
-        ///  Ethernet MMC control register
-        MMCCR: mmio.Mmio(packed struct(u32) {
-            ///  CR
-            CR: u1,
-            ///  CSR
-            CSR: u1,
-            ///  ROR
-            ROR: u1,
-            ///  MCF
-            MCF: u1,
-            ///  MCP
-            MCP: u1,
-            ///  MCFHP
-            MCFHP: u1,
-            padding: u26,
-        }),
-        ///  Ethernet MMC receive interrupt register
-        MMCRIR: mmio.Mmio(packed struct(u32) {
-            reserved5: u5,
-            ///  RFCES
-            RFCES: u1,
-            ///  RFAES
-            RFAES: u1,
-            reserved17: u10,
-            ///  RGUFS
-            RGUFS: u1,
-            padding: u14,
-        }),
-        ///  Ethernet MMC transmit interrupt register
-        MMCTIR: mmio.Mmio(packed struct(u32) {
-            reserved14: u14,
-            ///  TGFSCS
-            TGFSCS: u1,
-            ///  TGFMSCS
-            TGFMSCS: u1,
-            reserved21: u5,
-            ///  TGFS
-            TGFS: u1,
-            padding: u10,
-        }),
-        ///  Ethernet MMC receive interrupt mask register
-        MMCRIMR: mmio.Mmio(packed struct(u32) {
-            reserved5: u5,
-            ///  RFCEM
-            RFCEM: u1,
-            ///  RFAEM
-            RFAEM: u1,
-            reserved17: u10,
-            ///  RGUFM
-            RGUFM: u1,
-            padding: u14,
-        }),
-        ///  Ethernet MMC transmit interrupt mask register
-        MMCTIMR: mmio.Mmio(packed struct(u32) {
-            reserved14: u14,
-            ///  TGFSCM
-            TGFSCM: u1,
-            ///  TGFMSCM
-            TGFMSCM: u1,
-            ///  TGFM
-            TGFM: u1,
-            padding: u15,
-        }),
-        reserved76: [56]u8,
-        ///  Ethernet MMC transmitted good frames after a single collision counter
-        MMCTGFSCCR: mmio.Mmio(packed struct(u32) {
-            ///  TGFSCC
-            TGFSCC: u32,
-        }),
-        ///  Ethernet MMC transmitted good frames after more than a single collision
-        MMCTGFMSCCR: mmio.Mmio(packed struct(u32) {
-            ///  TGFMSCC
-            TGFMSCC: u32,
-        }),
-        reserved104: [20]u8,
-        ///  Ethernet MMC transmitted good frames counter register
-        MMCTGFCR: mmio.Mmio(packed struct(u32) {
-            ///  HTL
-            TGFC: u32,
-        }),
-        reserved148: [40]u8,
-        ///  Ethernet MMC received frames with CRC error counter register
-        MMCRFCECR: mmio.Mmio(packed struct(u32) {
-            ///  RFCFC
-            RFCFC: u32,
-        }),
-        ///  Ethernet MMC received frames with alignment error counter register
-        MMCRFAECR: mmio.Mmio(packed struct(u32) {
-            ///  RFAEC
-            RFAEC: u32,
-        }),
-        reserved196: [40]u8,
-        ///  MMC received good unicast frames counter register
-        MMCRGUFCR: mmio.Mmio(packed struct(u32) {
-            ///  RGUFC
-            RGUFC: u32,
-        }),
-    };
-
-    ///  General-purpose-timers
-    pub const TIM5 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            padding: u24,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            padding: u16,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            reserved6: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            reserved8: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            reserved14: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            reserved6: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            reserved9: u2,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            padding: u19,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            reserved6: u1,
-            ///  Trigger generation
-            TG: u1,
-            padding: u25,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC1S
-            CC1S: u2,
-            ///  OC1FE
-            OC1FE: u1,
-            ///  OC1PE
-            OC1PE: u1,
-            ///  OC1M
-            OC1M: u3,
-            ///  OC1CE
-            OC1CE: u1,
-            ///  CC2S
-            CC2S: u2,
-            ///  OC2FE
-            OC2FE: u1,
-            ///  OC2PE
-            OC2PE: u1,
-            ///  OC2M
-            OC2M: u3,
-            ///  OC2CE
-            OC2CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare mode register 2 (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC3S
-            CC3S: u2,
-            ///  OC3FE
-            OC3FE: u1,
-            ///  OC3PE
-            OC3PE: u1,
-            ///  OC3M
-            OC3M: u3,
-            ///  OC3CE
-            OC3CE: u1,
-            ///  CC4S
-            CC4S: u2,
-            ///  OC4FE
-            OC4FE: u1,
-            ///  OC4PE
-            OC4PE: u1,
-            ///  OC4M
-            OC4M: u3,
-            ///  O24CE
-            O24CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved7: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            reserved11: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            reserved15: u1,
-            ///  Capture/Compare 4 output Polarity
-            CC4NP: u1,
-            padding: u16,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  Low counter value
-            CNT_L: u16,
-            ///  High counter value
-            CNT_H: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Low Auto-reload value
-            ARR_L: u16,
-            ///  High Auto-reload value
-            ARR_H: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 1 value
-            CCR1_L: u16,
-            ///  High Capture/Compare 1 value
-            CCR1_H: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 2 value
-            CCR2_L: u16,
-            ///  High Capture/Compare 2 value
-            CCR2_H: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR3_L: u16,
-            ///  High Capture/Compare value
-            CCR3_H: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR4_L: u16,
-            ///  High Capture/Compare value
-            CCR4_H: u16,
-        }),
-        reserved72: [4]u8,
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-        ///  TIM5 option register
-        OR: mmio.Mmio(packed struct(u32) {
-            reserved6: u6,
-            ///  Timer Input 4 remap
-            IT4_RMP: u2,
-            padding: u24,
-        }),
-    };
-
-    ///  General purpose timers
-    pub const TIM9 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            reserved7: u3,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  Master mode selection
-            MMS: u3,
-            padding: u25,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            padding: u24,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            reserved6: u3,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            padding: u25,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            reserved6: u3,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            reserved9: u2,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            padding: u21,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            reserved6: u3,
-            ///  Trigger generation
-            TG: u1,
-            padding: u25,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            reserved8: u1,
-            ///  Capture/Compare 2 selection
-            CC2S: u2,
-            ///  Output Compare 2 fast enable
-            OC2FE: u1,
-            ///  Output Compare 2 preload enable
-            OC2PE: u1,
-            ///  Output Compare 2 mode
-            OC2M: u3,
-            padding: u17,
-        }),
-        reserved32: [4]u8,
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved7: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            padding: u24,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 2 value
-            CCR2: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Ethernet: media access control (MAC)
-    pub const Ethernet_MAC = extern struct {
-        ///  Ethernet MAC configuration register
-        MACCR: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  RE
-            RE: u1,
-            ///  TE
-            TE: u1,
-            ///  DC
-            DC: u1,
-            ///  BL
-            BL: u2,
-            ///  APCS
-            APCS: u1,
-            reserved9: u1,
-            ///  RD
-            RD: u1,
-            ///  IPCO
-            IPCO: u1,
-            ///  DM
-            DM: u1,
-            ///  LM
-            LM: u1,
-            ///  ROD
-            ROD: u1,
-            ///  FES
-            FES: u1,
-            reserved16: u1,
-            ///  CSD
-            CSD: u1,
-            ///  IFG
-            IFG: u3,
-            reserved22: u2,
-            ///  JD
-            JD: u1,
-            ///  WD
-            WD: u1,
-            reserved25: u1,
-            ///  CSTF
-            CSTF: u1,
-            padding: u6,
-        }),
-        ///  Ethernet MAC frame filter register
-        MACFFR: mmio.Mmio(packed struct(u32) {
-            ///  PM
-            PM: u1,
-            ///  HU
-            HU: u1,
-            ///  HM
-            HM: u1,
-            ///  DAIF
-            DAIF: u1,
-            ///  RAM
-            RAM: u1,
-            ///  BFD
-            BFD: u1,
-            ///  PCF
-            PCF: u1,
-            ///  SAIF
-            SAIF: u1,
-            ///  SAF
-            SAF: u1,
-            ///  HPF
-            HPF: u1,
-            reserved31: u21,
-            ///  RA
-            RA: u1,
-        }),
-        ///  Ethernet MAC hash table high register
-        MACHTHR: mmio.Mmio(packed struct(u32) {
-            ///  HTH
-            HTH: u32,
-        }),
-        ///  Ethernet MAC hash table low register
-        MACHTLR: mmio.Mmio(packed struct(u32) {
-            ///  HTL
-            HTL: u32,
-        }),
-        ///  Ethernet MAC MII address register
-        MACMIIAR: mmio.Mmio(packed struct(u32) {
-            ///  MB
-            MB: u1,
-            ///  MW
-            MW: u1,
-            ///  CR
-            CR: u3,
-            reserved6: u1,
-            ///  MR
-            MR: u5,
-            ///  PA
-            PA: u5,
-            padding: u16,
-        }),
-        ///  Ethernet MAC MII data register
-        MACMIIDR: mmio.Mmio(packed struct(u32) {
-            ///  TD
-            TD: u16,
-            padding: u16,
-        }),
-        ///  Ethernet MAC flow control register
-        MACFCR: mmio.Mmio(packed struct(u32) {
-            ///  FCB
-            FCB: u1,
-            ///  TFCE
-            TFCE: u1,
-            ///  RFCE
-            RFCE: u1,
-            ///  UPFD
-            UPFD: u1,
-            ///  PLT
-            PLT: u2,
-            reserved7: u1,
-            ///  ZQPD
-            ZQPD: u1,
-            reserved16: u8,
-            ///  PT
-            PT: u16,
-        }),
-        ///  Ethernet MAC VLAN tag register
-        MACVLANTR: mmio.Mmio(packed struct(u32) {
-            ///  VLANTI
-            VLANTI: u16,
-            ///  VLANTC
-            VLANTC: u1,
-            padding: u15,
-        }),
-        reserved44: [12]u8,
-        ///  Ethernet MAC PMT control and status register
-        MACPMTCSR: mmio.Mmio(packed struct(u32) {
-            ///  PD
-            PD: u1,
-            ///  MPE
-            MPE: u1,
-            ///  WFE
-            WFE: u1,
-            reserved5: u2,
-            ///  MPR
-            MPR: u1,
-            ///  WFR
-            WFR: u1,
-            reserved9: u2,
-            ///  GU
-            GU: u1,
-            reserved31: u21,
-            ///  WFFRPR
-            WFFRPR: u1,
-        }),
-        reserved52: [4]u8,
-        ///  Ethernet MAC debug register
-        MACDBGR: mmio.Mmio(packed struct(u32) {
-            ///  CR
-            CR: u1,
-            ///  CSR
-            CSR: u1,
-            ///  ROR
-            ROR: u1,
-            ///  MCF
-            MCF: u1,
-            ///  MCP
-            MCP: u1,
-            ///  MCFHP
-            MCFHP: u1,
-            padding: u26,
-        }),
-        ///  Ethernet MAC interrupt status register
-        MACSR: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  PMTS
-            PMTS: u1,
-            ///  MMCS
-            MMCS: u1,
-            ///  MMCRS
-            MMCRS: u1,
-            ///  MMCTS
-            MMCTS: u1,
-            reserved9: u2,
-            ///  TSTS
-            TSTS: u1,
-            padding: u22,
-        }),
-        ///  Ethernet MAC interrupt mask register
-        MACIMR: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  PMTIM
-            PMTIM: u1,
-            reserved9: u5,
-            ///  TSTIM
-            TSTIM: u1,
-            padding: u22,
-        }),
-        ///  Ethernet MAC address 0 high register
-        MACA0HR: mmio.Mmio(packed struct(u32) {
-            ///  MAC address0 high
-            MACA0H: u16,
-            reserved31: u15,
-            ///  Always 1
-            MO: u1,
-        }),
-        ///  Ethernet MAC address 0 low register
-        MACA0LR: mmio.Mmio(packed struct(u32) {
-            ///  0
-            MACA0L: u32,
-        }),
-        ///  Ethernet MAC address 1 high register
-        MACA1HR: mmio.Mmio(packed struct(u32) {
-            ///  MACA1H
-            MACA1H: u16,
-            reserved24: u8,
-            ///  MBC
-            MBC: u6,
-            ///  SA
-            SA: u1,
-            ///  AE
-            AE: u1,
-        }),
-        ///  Ethernet MAC address1 low register
-        MACA1LR: mmio.Mmio(packed struct(u32) {
-            ///  MACA1LR
-            MACA1LR: u32,
-        }),
-        ///  Ethernet MAC address 2 high register
-        MACA2HR: mmio.Mmio(packed struct(u32) {
-            ///  MAC2AH
-            MAC2AH: u16,
-            reserved24: u8,
-            ///  MBC
-            MBC: u6,
-            ///  SA
-            SA: u1,
-            ///  AE
-            AE: u1,
-        }),
-        ///  Ethernet MAC address 2 low register
-        MACA2LR: mmio.Mmio(packed struct(u32) {
-            ///  MACA2L
-            MACA2L: u31,
-            padding: u1,
-        }),
-        ///  Ethernet MAC address 3 high register
-        MACA3HR: mmio.Mmio(packed struct(u32) {
-            ///  MACA3H
-            MACA3H: u16,
-            reserved24: u8,
-            ///  MBC
-            MBC: u6,
-            ///  SA
-            SA: u1,
-            ///  AE
-            AE: u1,
-        }),
-        ///  Ethernet MAC address 3 low register
-        MACA3LR: mmio.Mmio(packed struct(u32) {
-            ///  MBCA3L
-            MBCA3L: u32,
-        }),
-    };
-
-    ///  General-purpose-timers
-    pub const TIM10 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            reserved7: u4,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        reserved12: [8]u8,
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            padding: u30,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            reserved9: u7,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            padding: u22,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            padding: u30,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            padding: u25,
-        }),
-        reserved32: [4]u8,
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            padding: u28,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  General-purpose-timers
-    pub const TIM11 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            reserved7: u4,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        reserved12: [8]u8,
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            padding: u30,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            reserved9: u7,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            padding: u22,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            padding: u30,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            padding: u25,
-        }),
-        reserved32: [4]u8,
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            padding: u28,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        reserved80: [24]u8,
-        ///  option register
-        OR: mmio.Mmio(packed struct(u32) {
-            ///  Input 1 remapping capability
-            RMP: u2,
-            padding: u30,
-        }),
-    };
-};
diff --git a/src/chips/STM32F429.zig b/src/chips/STM32F429.zig
deleted file mode 100644
index 8638044a2..000000000
--- a/src/chips/STM32F429.zig
+++ /dev/null
@@ -1,20419 +0,0 @@
-const micro = @import("microzig");
-const mmio = micro.mmio;
-
-pub const devices = struct {
-    ///  STM32F429
-    pub const STM32F429 = struct {
-        pub const properties = struct {
-            pub const @"cpu.nvic_prio_bits" = "3";
-            pub const @"cpu.mpu" = "false";
-            pub const @"cpu.fpu" = "false";
-            pub const @"cpu.revision" = "r1p0";
-            pub const @"cpu.vendor_systick_config" = "false";
-            pub const @"cpu.endian" = "little";
-            pub const @"cpu.name" = "CM4";
-        };
-
-        pub const VectorTable = extern struct {
-            const Handler = micro.interrupt.Handler;
-            const unhandled = micro.interrupt.unhandled;
-
-            initial_stack_pointer: u32,
-            Reset: Handler = unhandled,
-            NMI: Handler = unhandled,
-            HardFault: Handler = unhandled,
-            MemManageFault: Handler = unhandled,
-            BusFault: Handler = unhandled,
-            UsageFault: Handler = unhandled,
-            reserved5: [4]u32 = undefined,
-            SVCall: Handler = unhandled,
-            DebugMonitor: Handler = unhandled,
-            reserved11: [1]u32 = undefined,
-            PendSV: Handler = unhandled,
-            SysTick: Handler = unhandled,
-            ///  Window Watchdog interrupt
-            WWDG: Handler = unhandled,
-            ///  PVD through EXTI line detection interrupt
-            PVD: Handler = unhandled,
-            ///  Tamper and TimeStamp interrupts through the EXTI line
-            TAMP_STAMP: Handler = unhandled,
-            ///  RTC Wakeup interrupt through the EXTI line
-            RTC_WKUP: Handler = unhandled,
-            ///  Flash global interrupt
-            FLASH: Handler = unhandled,
-            ///  RCC global interrupt
-            RCC: Handler = unhandled,
-            reserved20: [5]u32 = undefined,
-            ///  DMA1 Stream0 global interrupt
-            DMA1_Stream0: Handler = unhandled,
-            reserved26: [6]u32 = undefined,
-            ///  ADC2 global interrupts
-            ADC: Handler = unhandled,
-            ///  CAN1 TX interrupts
-            CAN1_TX: Handler = unhandled,
-            reserved34: [4]u32 = undefined,
-            ///  TIM1 Break interrupt and TIM9 global interrupt
-            TIM1_BRK_TIM9: Handler = unhandled,
-            reserved39: [3]u32 = undefined,
-            ///  TIM2 global interrupt
-            TIM2: Handler = unhandled,
-            ///  TIM3 global interrupt
-            TIM3: Handler = unhandled,
-            ///  TIM4 global interrupt
-            TIM4: Handler = unhandled,
-            ///  I2C1 event interrupt
-            I2C1_EV: Handler = unhandled,
-            reserved46: [1]u32 = undefined,
-            ///  I2C2 event interrupt
-            I2C2_EV: Handler = unhandled,
-            reserved48: [1]u32 = undefined,
-            ///  SPI1 global interrupt
-            SPI1: Handler = unhandled,
-            ///  SPI2 global interrupt
-            SPI2: Handler = unhandled,
-            ///  USART1 global interrupt
-            USART1: Handler = unhandled,
-            ///  USART2 global interrupt
-            USART2: Handler = unhandled,
-            ///  USART3 global interrupt
-            USART3: Handler = unhandled,
-            reserved54: [2]u32 = undefined,
-            ///  USB On-The-Go FS Wakeup through EXTI line interrupt
-            OTG_FS_WKUP: Handler = unhandled,
-            ///  TIM8 Break interrupt and TIM12 global interrupt
-            TIM8_BRK_TIM12: Handler = unhandled,
-            ///  TIM8 Update interrupt and TIM13 global interrupt
-            TIM8_UP_TIM13: Handler = unhandled,
-            ///  TIM8 Trigger and Commutation interrupts and TIM14 global interrupt
-            TIM8_TRG_COM_TIM14: Handler = unhandled,
-            reserved60: [2]u32 = undefined,
-            ///  FMC global interrupt
-            FMC: Handler = unhandled,
-            ///  SDIO global interrupt
-            SDIO: Handler = unhandled,
-            ///  TIM5 global interrupt
-            TIM5: Handler = unhandled,
-            ///  SPI3 global interrupt
-            SPI3: Handler = unhandled,
-            ///  UART4 global interrupt
-            UART4: Handler = unhandled,
-            ///  UART5 global interrupt
-            UART5: Handler = unhandled,
-            ///  TIM6 global interrupt, DAC1 and DAC2 underrun error interrupt
-            TIM6_DAC: Handler = unhandled,
-            ///  TIM7 global interrupt
-            TIM7: Handler = unhandled,
-            ///  DMA2 Stream0 global interrupt
-            DMA2_Stream0: Handler = unhandled,
-            reserved71: [4]u32 = undefined,
-            ///  Ethernet global interrupt
-            ETH: Handler = unhandled,
-            reserved76: [1]u32 = undefined,
-            ///  CAN2 TX interrupts
-            CAN2_TX: Handler = unhandled,
-            reserved78: [7]u32 = undefined,
-            ///  USART6 global interrupt
-            USART6: Handler = unhandled,
-            ///  I2C3 event interrupt
-            I2C3_EV: Handler = unhandled,
-            reserved87: [1]u32 = undefined,
-            ///  USB On The Go HS End Point 1 Out global interrupt
-            OTG_HS_EP1_OUT: Handler = unhandled,
-            reserved89: [3]u32 = undefined,
-            ///  DCMI global interrupt
-            DCMI: Handler = unhandled,
-            ///  CRYP crypto global interrupt
-            CRYP: Handler = unhandled,
-            ///  Hash and Rng global interrupt
-            HASH_RNG: Handler = unhandled,
-            ///  FPU interrupt
-            FPU: Handler = unhandled,
-            ///  UART 7 global interrupt
-            UART7: Handler = unhandled,
-            ///  UART 8 global interrupt
-            UART8: Handler = unhandled,
-            ///  SPI 4 global interrupt
-            SPI4: Handler = unhandled,
-            ///  SPI 5 global interrupt
-            SPI5: Handler = unhandled,
-            ///  SPI 6 global interrupt
-            SPI6: Handler = unhandled,
-            ///  SAI1 global interrupt
-            SAI1: Handler = unhandled,
-            ///  LTDC global interrupt
-            LCD_TFT: Handler = unhandled,
-            reserved103: [1]u32 = undefined,
-            ///  DMA2D global interrupt
-            DMA2D: Handler = unhandled,
-        };
-
-        pub const peripherals = struct {
-            ///  General purpose timers
-            pub const TIM2 = @as(*volatile types.TIM2, @ptrFromInt(0x40000000));
-            ///  General purpose timers
-            pub const TIM3 = @as(*volatile types.TIM3, @ptrFromInt(0x40000400));
-            ///  General purpose timers
-            pub const TIM4 = @as(*volatile types.TIM3, @ptrFromInt(0x40000800));
-            ///  General-purpose-timers
-            pub const TIM5 = @as(*volatile types.TIM5, @ptrFromInt(0x40000c00));
-            ///  Basic timers
-            pub const TIM6 = @as(*volatile types.TIM6, @ptrFromInt(0x40001000));
-            ///  Basic timers
-            pub const TIM7 = @as(*volatile types.TIM6, @ptrFromInt(0x40001400));
-            ///  General purpose timers
-            pub const TIM12 = @as(*volatile types.TIM9, @ptrFromInt(0x40001800));
-            ///  General-purpose-timers
-            pub const TIM13 = @as(*volatile types.TIM10, @ptrFromInt(0x40001c00));
-            ///  General-purpose-timers
-            pub const TIM14 = @as(*volatile types.TIM10, @ptrFromInt(0x40002000));
-            ///  Real-time clock
-            pub const RTC = @as(*volatile types.RTC, @ptrFromInt(0x40002800));
-            ///  Window watchdog
-            pub const WWDG = @as(*volatile types.WWDG, @ptrFromInt(0x40002c00));
-            ///  Independent watchdog
-            pub const IWDG = @as(*volatile types.IWDG, @ptrFromInt(0x40003000));
-            ///  Serial peripheral interface
-            pub const I2S2ext = @as(*volatile types.SPI1, @ptrFromInt(0x40003400));
-            ///  Serial peripheral interface
-            pub const SPI2 = @as(*volatile types.SPI1, @ptrFromInt(0x40003800));
-            ///  Serial peripheral interface
-            pub const SPI3 = @as(*volatile types.SPI1, @ptrFromInt(0x40003c00));
-            ///  Serial peripheral interface
-            pub const I2S3ext = @as(*volatile types.SPI1, @ptrFromInt(0x40004000));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART2 = @as(*volatile types.USART6, @ptrFromInt(0x40004400));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART3 = @as(*volatile types.USART6, @ptrFromInt(0x40004800));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART4 = @as(*volatile types.UART4, @ptrFromInt(0x40004c00));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART5 = @as(*volatile types.UART4, @ptrFromInt(0x40005000));
-            ///  Inter-integrated circuit
-            pub const I2C1 = @as(*volatile types.I2C3, @ptrFromInt(0x40005400));
-            ///  Inter-integrated circuit
-            pub const I2C2 = @as(*volatile types.I2C3, @ptrFromInt(0x40005800));
-            ///  Inter-integrated circuit
-            pub const I2C3 = @as(*volatile types.I2C3, @ptrFromInt(0x40005c00));
-            ///  Controller area network
-            pub const CAN1 = @as(*volatile types.CAN1, @ptrFromInt(0x40006400));
-            ///  Controller area network
-            pub const CAN2 = @as(*volatile types.CAN1, @ptrFromInt(0x40006800));
-            ///  Power control
-            pub const PWR = @as(*volatile types.PWR, @ptrFromInt(0x40007000));
-            ///  Digital-to-analog converter
-            pub const DAC = @as(*volatile types.DAC, @ptrFromInt(0x40007400));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART7 = @as(*volatile types.USART6, @ptrFromInt(0x40007800));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const UART8 = @as(*volatile types.USART6, @ptrFromInt(0x40007c00));
-            ///  Advanced-timers
-            pub const TIM1 = @as(*volatile types.TIM1, @ptrFromInt(0x40010000));
-            ///  Advanced-timers
-            pub const TIM8 = @as(*volatile types.TIM1, @ptrFromInt(0x40010400));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART1 = @as(*volatile types.USART6, @ptrFromInt(0x40011000));
-            ///  Universal synchronous asynchronous receiver transmitter
-            pub const USART6 = @as(*volatile types.USART6, @ptrFromInt(0x40011400));
-            ///  Analog-to-digital converter
-            pub const ADC1 = @as(*volatile types.ADC1, @ptrFromInt(0x40012000));
-            ///  Analog-to-digital converter
-            pub const ADC2 = @as(*volatile types.ADC1, @ptrFromInt(0x40012100));
-            ///  Analog-to-digital converter
-            pub const ADC3 = @as(*volatile types.ADC1, @ptrFromInt(0x40012200));
-            ///  Common ADC registers
-            pub const C_ADC = @as(*volatile types.C_ADC, @ptrFromInt(0x40012300));
-            ///  Secure digital input/output interface
-            pub const SDIO = @as(*volatile types.SDIO, @ptrFromInt(0x40012c00));
-            ///  Serial peripheral interface
-            pub const SPI1 = @as(*volatile types.SPI1, @ptrFromInt(0x40013000));
-            ///  Serial peripheral interface
-            pub const SPI4 = @as(*volatile types.SPI1, @ptrFromInt(0x40013400));
-            ///  System configuration controller
-            pub const SYSCFG = @as(*volatile types.SYSCFG, @ptrFromInt(0x40013800));
-            ///  External interrupt/event controller
-            pub const EXTI = @as(*volatile types.EXTI, @ptrFromInt(0x40013c00));
-            ///  General purpose timers
-            pub const TIM9 = @as(*volatile types.TIM9, @ptrFromInt(0x40014000));
-            ///  General-purpose-timers
-            pub const TIM10 = @as(*volatile types.TIM10, @ptrFromInt(0x40014400));
-            ///  General-purpose-timers
-            pub const TIM11 = @as(*volatile types.TIM11, @ptrFromInt(0x40014800));
-            ///  Serial peripheral interface
-            pub const SPI5 = @as(*volatile types.SPI1, @ptrFromInt(0x40015000));
-            ///  Serial peripheral interface
-            pub const SPI6 = @as(*volatile types.SPI1, @ptrFromInt(0x40015400));
-            ///  Serial audio interface
-            pub const SAI = @as(*volatile types.SAI, @ptrFromInt(0x40015800));
-            ///  LCD-TFT Controller
-            pub const LTDC = @as(*volatile types.LTDC, @ptrFromInt(0x40016800));
-            ///  General-purpose I/Os
-            pub const GPIOA = @as(*volatile types.GPIOA, @ptrFromInt(0x40020000));
-            ///  General-purpose I/Os
-            pub const GPIOB = @as(*volatile types.GPIOB, @ptrFromInt(0x40020400));
-            ///  General-purpose I/Os
-            pub const GPIOC = @as(*volatile types.GPIOK, @ptrFromInt(0x40020800));
-            ///  General-purpose I/Os
-            pub const GPIOD = @as(*volatile types.GPIOK, @ptrFromInt(0x40020c00));
-            ///  General-purpose I/Os
-            pub const GPIOE = @as(*volatile types.GPIOK, @ptrFromInt(0x40021000));
-            ///  General-purpose I/Os
-            pub const GPIOF = @as(*volatile types.GPIOK, @ptrFromInt(0x40021400));
-            ///  General-purpose I/Os
-            pub const GPIOG = @as(*volatile types.GPIOK, @ptrFromInt(0x40021800));
-            ///  General-purpose I/Os
-            pub const GPIOH = @as(*volatile types.GPIOK, @ptrFromInt(0x40021c00));
-            ///  General-purpose I/Os
-            pub const GPIOI = @as(*volatile types.GPIOK, @ptrFromInt(0x40022000));
-            ///  General-purpose I/Os
-            pub const GPIOJ = @as(*volatile types.GPIOK, @ptrFromInt(0x40022400));
-            ///  General-purpose I/Os
-            pub const GPIOK = @as(*volatile types.GPIOK, @ptrFromInt(0x40022800));
-            ///  Cryptographic processor
-            pub const CRC = @as(*volatile types.CRC, @ptrFromInt(0x40023000));
-            ///  Reset and clock control
-            pub const RCC = @as(*volatile types.RCC, @ptrFromInt(0x40023800));
-            ///  FLASH
-            pub const FLASH = @as(*volatile types.FLASH, @ptrFromInt(0x40023c00));
-            ///  DMA controller
-            pub const DMA1 = @as(*volatile types.DMA2, @ptrFromInt(0x40026000));
-            ///  DMA controller
-            pub const DMA2 = @as(*volatile types.DMA2, @ptrFromInt(0x40026400));
-            ///  Ethernet: media access control (MAC)
-            pub const Ethernet_MAC = @as(*volatile types.Ethernet_MAC, @ptrFromInt(0x40028000));
-            ///  Ethernet: MAC management counters
-            pub const Ethernet_MMC = @as(*volatile types.Ethernet_MMC, @ptrFromInt(0x40028100));
-            ///  Ethernet: Precision time protocol
-            pub const Ethernet_PTP = @as(*volatile types.Ethernet_PTP, @ptrFromInt(0x40028700));
-            ///  Ethernet: DMA controller operation
-            pub const Ethernet_DMA = @as(*volatile types.Ethernet_DMA, @ptrFromInt(0x40029000));
-            ///  DMA2D controller
-            pub const DMA2D = @as(*volatile types.DMA2D, @ptrFromInt(0x4002b000));
-            ///  USB on the go high speed
-            pub const OTG_HS_GLOBAL = @as(*volatile types.OTG_HS_GLOBAL, @ptrFromInt(0x40040000));
-            ///  USB on the go high speed
-            pub const OTG_HS_HOST = @as(*volatile types.OTG_HS_HOST, @ptrFromInt(0x40040400));
-            ///  USB on the go high speed
-            pub const OTG_HS_DEVICE = @as(*volatile types.OTG_HS_DEVICE, @ptrFromInt(0x40040800));
-            ///  USB on the go high speed
-            pub const OTG_HS_PWRCLK = @as(*volatile types.OTG_HS_PWRCLK, @ptrFromInt(0x40040e00));
-            ///  USB on the go full speed
-            pub const OTG_FS_GLOBAL = @as(*volatile types.OTG_FS_GLOBAL, @ptrFromInt(0x50000000));
-            ///  USB on the go full speed
-            pub const OTG_FS_HOST = @as(*volatile types.OTG_FS_HOST, @ptrFromInt(0x50000400));
-            ///  USB on the go full speed
-            pub const OTG_FS_DEVICE = @as(*volatile types.OTG_FS_DEVICE, @ptrFromInt(0x50000800));
-            ///  USB on the go full speed
-            pub const OTG_FS_PWRCLK = @as(*volatile types.OTG_FS_PWRCLK, @ptrFromInt(0x50000e00));
-            ///  Digital camera interface
-            pub const DCMI = @as(*volatile types.DCMI, @ptrFromInt(0x50050000));
-            ///  Cryptographic processor
-            pub const CRYP = @as(*volatile types.CRYP, @ptrFromInt(0x50060000));
-            ///  Hash processor
-            pub const HASH = @as(*volatile types.HASH, @ptrFromInt(0x50060400));
-            ///  Random number generator
-            pub const RNG = @as(*volatile types.RNG, @ptrFromInt(0x50060800));
-            ///  Flexible memory controller
-            pub const FMC = @as(*volatile types.FMC, @ptrFromInt(0xa0000000));
-            ///  System control block ACTLR
-            pub const SCB_ACTRL = @as(*volatile types.SCB_ACTRL, @ptrFromInt(0xe000e008));
-            ///  SysTick timer
-            pub const STK = @as(*volatile types.STK, @ptrFromInt(0xe000e010));
-            ///  Nested Vectored Interrupt Controller
-            pub const NVIC = @as(*volatile types.NVIC, @ptrFromInt(0xe000e100));
-            ///  System control block
-            pub const SCB = @as(*volatile types.SCB, @ptrFromInt(0xe000ed00));
-            ///  Floating point unit CPACR
-            pub const FPU_CPACR = @as(*volatile types.FPU_CPACR, @ptrFromInt(0xe000ed88));
-            ///  Memory protection unit
-            pub const MPU = @as(*volatile types.MPU, @ptrFromInt(0xe000ed90));
-            ///  Nested vectored interrupt controller
-            pub const NVIC_STIR = @as(*volatile types.NVIC_STIR, @ptrFromInt(0xe000ef00));
-            ///  Floting point unit
-            pub const FPU = @as(*volatile types.FPU, @ptrFromInt(0xe000ef34));
-            ///  Debug support
-            pub const DBG = @as(*volatile types.DBG, @ptrFromInt(0xe0042000));
-        };
-    };
-};
-
-pub const types = struct {
-    ///  Random number generator
-    pub const RNG = extern struct {
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Random number generator enable
-            RNGEN: u1,
-            ///  Interrupt enable
-            IE: u1,
-            padding: u28,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Data ready
-            DRDY: u1,
-            ///  Clock error current status
-            CECS: u1,
-            ///  Seed error current status
-            SECS: u1,
-            reserved5: u2,
-            ///  Clock error interrupt status
-            CEIS: u1,
-            ///  Seed error interrupt status
-            SEIS: u1,
-            padding: u25,
-        }),
-        ///  data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Random data
-            RNDATA: u32,
-        }),
-    };
-
-    ///  Hash processor
-    pub const HASH = extern struct {
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Initialize message digest calculation
-            INIT: u1,
-            ///  DMA enable
-            DMAE: u1,
-            ///  Data type selection
-            DATATYPE: u2,
-            ///  Mode selection
-            MODE: u1,
-            ///  Algorithm selection
-            ALGO0: u1,
-            ///  Number of words already pushed
-            NBW: u4,
-            ///  DIN not empty
-            DINNE: u1,
-            ///  Multiple DMA Transfers
-            MDMAT: u1,
-            reserved16: u2,
-            ///  Long key selection
-            LKEY: u1,
-            reserved18: u1,
-            ///  ALGO
-            ALGO1: u1,
-            padding: u13,
-        }),
-        ///  data input register
-        DIN: mmio.Mmio(packed struct(u32) {
-            ///  Data input
-            DATAIN: u32,
-        }),
-        ///  start register
-        STR: mmio.Mmio(packed struct(u32) {
-            ///  Number of valid bits in the last word of the message
-            NBLW: u5,
-            reserved8: u3,
-            ///  Digest calculation
-            DCAL: u1,
-            padding: u23,
-        }),
-        ///  digest registers
-        HR0: mmio.Mmio(packed struct(u32) {
-            ///  H0
-            H0: u32,
-        }),
-        ///  digest registers
-        HR1: mmio.Mmio(packed struct(u32) {
-            ///  H1
-            H1: u32,
-        }),
-        ///  digest registers
-        HR2: mmio.Mmio(packed struct(u32) {
-            ///  H2
-            H2: u32,
-        }),
-        ///  digest registers
-        HR3: mmio.Mmio(packed struct(u32) {
-            ///  H3
-            H3: u32,
-        }),
-        ///  digest registers
-        HR4: mmio.Mmio(packed struct(u32) {
-            ///  H4
-            H4: u32,
-        }),
-        ///  interrupt enable register
-        IMR: mmio.Mmio(packed struct(u32) {
-            ///  Data input interrupt enable
-            DINIE: u1,
-            ///  Digest calculation completion interrupt enable
-            DCIE: u1,
-            padding: u30,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Data input interrupt status
-            DINIS: u1,
-            ///  Digest calculation completion interrupt status
-            DCIS: u1,
-            ///  DMA Status
-            DMAS: u1,
-            ///  Busy bit
-            BUSY: u1,
-            padding: u28,
-        }),
-        reserved248: [208]u8,
-        ///  context swap registers
-        CSR0: mmio.Mmio(packed struct(u32) {
-            ///  CSR0
-            CSR0: u32,
-        }),
-        ///  context swap registers
-        CSR1: mmio.Mmio(packed struct(u32) {
-            ///  CSR1
-            CSR1: u32,
-        }),
-        ///  context swap registers
-        CSR2: mmio.Mmio(packed struct(u32) {
-            ///  CSR2
-            CSR2: u32,
-        }),
-        ///  context swap registers
-        CSR3: mmio.Mmio(packed struct(u32) {
-            ///  CSR3
-            CSR3: u32,
-        }),
-        ///  context swap registers
-        CSR4: mmio.Mmio(packed struct(u32) {
-            ///  CSR4
-            CSR4: u32,
-        }),
-        ///  context swap registers
-        CSR5: mmio.Mmio(packed struct(u32) {
-            ///  CSR5
-            CSR5: u32,
-        }),
-        ///  context swap registers
-        CSR6: mmio.Mmio(packed struct(u32) {
-            ///  CSR6
-            CSR6: u32,
-        }),
-        ///  context swap registers
-        CSR7: mmio.Mmio(packed struct(u32) {
-            ///  CSR7
-            CSR7: u32,
-        }),
-        ///  context swap registers
-        CSR8: mmio.Mmio(packed struct(u32) {
-            ///  CSR8
-            CSR8: u32,
-        }),
-        ///  context swap registers
-        CSR9: mmio.Mmio(packed struct(u32) {
-            ///  CSR9
-            CSR9: u32,
-        }),
-        ///  context swap registers
-        CSR10: mmio.Mmio(packed struct(u32) {
-            ///  CSR10
-            CSR10: u32,
-        }),
-        ///  context swap registers
-        CSR11: mmio.Mmio(packed struct(u32) {
-            ///  CSR11
-            CSR11: u32,
-        }),
-        ///  context swap registers
-        CSR12: mmio.Mmio(packed struct(u32) {
-            ///  CSR12
-            CSR12: u32,
-        }),
-        ///  context swap registers
-        CSR13: mmio.Mmio(packed struct(u32) {
-            ///  CSR13
-            CSR13: u32,
-        }),
-        ///  context swap registers
-        CSR14: mmio.Mmio(packed struct(u32) {
-            ///  CSR14
-            CSR14: u32,
-        }),
-        ///  context swap registers
-        CSR15: mmio.Mmio(packed struct(u32) {
-            ///  CSR15
-            CSR15: u32,
-        }),
-        ///  context swap registers
-        CSR16: mmio.Mmio(packed struct(u32) {
-            ///  CSR16
-            CSR16: u32,
-        }),
-        ///  context swap registers
-        CSR17: mmio.Mmio(packed struct(u32) {
-            ///  CSR17
-            CSR17: u32,
-        }),
-        ///  context swap registers
-        CSR18: mmio.Mmio(packed struct(u32) {
-            ///  CSR18
-            CSR18: u32,
-        }),
-        ///  context swap registers
-        CSR19: mmio.Mmio(packed struct(u32) {
-            ///  CSR19
-            CSR19: u32,
-        }),
-        ///  context swap registers
-        CSR20: mmio.Mmio(packed struct(u32) {
-            ///  CSR20
-            CSR20: u32,
-        }),
-        ///  context swap registers
-        CSR21: mmio.Mmio(packed struct(u32) {
-            ///  CSR21
-            CSR21: u32,
-        }),
-        ///  context swap registers
-        CSR22: mmio.Mmio(packed struct(u32) {
-            ///  CSR22
-            CSR22: u32,
-        }),
-        ///  context swap registers
-        CSR23: mmio.Mmio(packed struct(u32) {
-            ///  CSR23
-            CSR23: u32,
-        }),
-        ///  context swap registers
-        CSR24: mmio.Mmio(packed struct(u32) {
-            ///  CSR24
-            CSR24: u32,
-        }),
-        ///  context swap registers
-        CSR25: mmio.Mmio(packed struct(u32) {
-            ///  CSR25
-            CSR25: u32,
-        }),
-        ///  context swap registers
-        CSR26: mmio.Mmio(packed struct(u32) {
-            ///  CSR26
-            CSR26: u32,
-        }),
-        ///  context swap registers
-        CSR27: mmio.Mmio(packed struct(u32) {
-            ///  CSR27
-            CSR27: u32,
-        }),
-        ///  context swap registers
-        CSR28: mmio.Mmio(packed struct(u32) {
-            ///  CSR28
-            CSR28: u32,
-        }),
-        ///  context swap registers
-        CSR29: mmio.Mmio(packed struct(u32) {
-            ///  CSR29
-            CSR29: u32,
-        }),
-        ///  context swap registers
-        CSR30: mmio.Mmio(packed struct(u32) {
-            ///  CSR30
-            CSR30: u32,
-        }),
-        ///  context swap registers
-        CSR31: mmio.Mmio(packed struct(u32) {
-            ///  CSR31
-            CSR31: u32,
-        }),
-        ///  context swap registers
-        CSR32: mmio.Mmio(packed struct(u32) {
-            ///  CSR32
-            CSR32: u32,
-        }),
-        ///  context swap registers
-        CSR33: mmio.Mmio(packed struct(u32) {
-            ///  CSR33
-            CSR33: u32,
-        }),
-        ///  context swap registers
-        CSR34: mmio.Mmio(packed struct(u32) {
-            ///  CSR34
-            CSR34: u32,
-        }),
-        ///  context swap registers
-        CSR35: mmio.Mmio(packed struct(u32) {
-            ///  CSR35
-            CSR35: u32,
-        }),
-        ///  context swap registers
-        CSR36: mmio.Mmio(packed struct(u32) {
-            ///  CSR36
-            CSR36: u32,
-        }),
-        ///  context swap registers
-        CSR37: mmio.Mmio(packed struct(u32) {
-            ///  CSR37
-            CSR37: u32,
-        }),
-        ///  context swap registers
-        CSR38: mmio.Mmio(packed struct(u32) {
-            ///  CSR38
-            CSR38: u32,
-        }),
-        ///  context swap registers
-        CSR39: mmio.Mmio(packed struct(u32) {
-            ///  CSR39
-            CSR39: u32,
-        }),
-        ///  context swap registers
-        CSR40: mmio.Mmio(packed struct(u32) {
-            ///  CSR40
-            CSR40: u32,
-        }),
-        ///  context swap registers
-        CSR41: mmio.Mmio(packed struct(u32) {
-            ///  CSR41
-            CSR41: u32,
-        }),
-        ///  context swap registers
-        CSR42: mmio.Mmio(packed struct(u32) {
-            ///  CSR42
-            CSR42: u32,
-        }),
-        ///  context swap registers
-        CSR43: mmio.Mmio(packed struct(u32) {
-            ///  CSR43
-            CSR43: u32,
-        }),
-        ///  context swap registers
-        CSR44: mmio.Mmio(packed struct(u32) {
-            ///  CSR44
-            CSR44: u32,
-        }),
-        ///  context swap registers
-        CSR45: mmio.Mmio(packed struct(u32) {
-            ///  CSR45
-            CSR45: u32,
-        }),
-        ///  context swap registers
-        CSR46: mmio.Mmio(packed struct(u32) {
-            ///  CSR46
-            CSR46: u32,
-        }),
-        ///  context swap registers
-        CSR47: mmio.Mmio(packed struct(u32) {
-            ///  CSR47
-            CSR47: u32,
-        }),
-        ///  context swap registers
-        CSR48: mmio.Mmio(packed struct(u32) {
-            ///  CSR48
-            CSR48: u32,
-        }),
-        ///  context swap registers
-        CSR49: mmio.Mmio(packed struct(u32) {
-            ///  CSR49
-            CSR49: u32,
-        }),
-        ///  context swap registers
-        CSR50: mmio.Mmio(packed struct(u32) {
-            ///  CSR50
-            CSR50: u32,
-        }),
-        ///  context swap registers
-        CSR51: mmio.Mmio(packed struct(u32) {
-            ///  CSR51
-            CSR51: u32,
-        }),
-        ///  context swap registers
-        CSR52: mmio.Mmio(packed struct(u32) {
-            ///  CSR52
-            CSR52: u32,
-        }),
-        ///  context swap registers
-        CSR53: mmio.Mmio(packed struct(u32) {
-            ///  CSR53
-            CSR53: u32,
-        }),
-        reserved784: [320]u8,
-        ///  HASH digest register
-        HASH_HR0: mmio.Mmio(packed struct(u32) {
-            ///  H0
-            H0: u32,
-        }),
-        ///  read-only
-        HASH_HR1: mmio.Mmio(packed struct(u32) {
-            ///  H1
-            H1: u32,
-        }),
-        ///  read-only
-        HASH_HR2: mmio.Mmio(packed struct(u32) {
-            ///  H2
-            H2: u32,
-        }),
-        ///  read-only
-        HASH_HR3: mmio.Mmio(packed struct(u32) {
-            ///  H3
-            H3: u32,
-        }),
-        ///  read-only
-        HASH_HR4: mmio.Mmio(packed struct(u32) {
-            ///  H4
-            H4: u32,
-        }),
-        ///  read-only
-        HASH_HR5: mmio.Mmio(packed struct(u32) {
-            ///  H5
-            H5: u32,
-        }),
-        ///  read-only
-        HASH_HR6: mmio.Mmio(packed struct(u32) {
-            ///  H6
-            H6: u32,
-        }),
-        ///  read-only
-        HASH_HR7: mmio.Mmio(packed struct(u32) {
-            ///  H7
-            H7: u32,
-        }),
-    };
-
-    ///  Cryptographic processor
-    pub const CRYP = extern struct {
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Algorithm direction
-            ALGODIR: u1,
-            ///  Algorithm mode
-            ALGOMODE0: u3,
-            ///  Data type selection
-            DATATYPE: u2,
-            ///  Key size selection (AES mode only)
-            KEYSIZE: u2,
-            reserved14: u4,
-            ///  FIFO flush
-            FFLUSH: u1,
-            ///  Cryptographic processor enable
-            CRYPEN: u1,
-            ///  GCM_CCMPH
-            GCM_CCMPH: u2,
-            reserved19: u1,
-            ///  ALGOMODE
-            ALGOMODE3: u1,
-            padding: u12,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Input FIFO empty
-            IFEM: u1,
-            ///  Input FIFO not full
-            IFNF: u1,
-            ///  Output FIFO not empty
-            OFNE: u1,
-            ///  Output FIFO full
-            OFFU: u1,
-            ///  Busy bit
-            BUSY: u1,
-            padding: u27,
-        }),
-        ///  data input register
-        DIN: mmio.Mmio(packed struct(u32) {
-            ///  Data input
-            DATAIN: u32,
-        }),
-        ///  data output register
-        DOUT: mmio.Mmio(packed struct(u32) {
-            ///  Data output
-            DATAOUT: u32,
-        }),
-        ///  DMA control register
-        DMACR: mmio.Mmio(packed struct(u32) {
-            ///  DMA input enable
-            DIEN: u1,
-            ///  DMA output enable
-            DOEN: u1,
-            padding: u30,
-        }),
-        ///  interrupt mask set/clear register
-        IMSCR: mmio.Mmio(packed struct(u32) {
-            ///  Input FIFO service interrupt mask
-            INIM: u1,
-            ///  Output FIFO service interrupt mask
-            OUTIM: u1,
-            padding: u30,
-        }),
-        ///  raw interrupt status register
-        RISR: mmio.Mmio(packed struct(u32) {
-            ///  Input FIFO service raw interrupt status
-            INRIS: u1,
-            ///  Output FIFO service raw interrupt status
-            OUTRIS: u1,
-            padding: u30,
-        }),
-        ///  masked interrupt status register
-        MISR: mmio.Mmio(packed struct(u32) {
-            ///  Input FIFO service masked interrupt status
-            INMIS: u1,
-            ///  Output FIFO service masked interrupt status
-            OUTMIS: u1,
-            padding: u30,
-        }),
-        ///  key registers
-        K0LR: mmio.Mmio(packed struct(u32) {
-            ///  b224
-            b224: u1,
-            ///  b225
-            b225: u1,
-            ///  b226
-            b226: u1,
-            ///  b227
-            b227: u1,
-            ///  b228
-            b228: u1,
-            ///  b229
-            b229: u1,
-            ///  b230
-            b230: u1,
-            ///  b231
-            b231: u1,
-            ///  b232
-            b232: u1,
-            ///  b233
-            b233: u1,
-            ///  b234
-            b234: u1,
-            ///  b235
-            b235: u1,
-            ///  b236
-            b236: u1,
-            ///  b237
-            b237: u1,
-            ///  b238
-            b238: u1,
-            ///  b239
-            b239: u1,
-            ///  b240
-            b240: u1,
-            ///  b241
-            b241: u1,
-            ///  b242
-            b242: u1,
-            ///  b243
-            b243: u1,
-            ///  b244
-            b244: u1,
-            ///  b245
-            b245: u1,
-            ///  b246
-            b246: u1,
-            ///  b247
-            b247: u1,
-            ///  b248
-            b248: u1,
-            ///  b249
-            b249: u1,
-            ///  b250
-            b250: u1,
-            ///  b251
-            b251: u1,
-            ///  b252
-            b252: u1,
-            ///  b253
-            b253: u1,
-            ///  b254
-            b254: u1,
-            ///  b255
-            b255: u1,
-        }),
-        ///  key registers
-        K0RR: mmio.Mmio(packed struct(u32) {
-            ///  b192
-            b192: u1,
-            ///  b193
-            b193: u1,
-            ///  b194
-            b194: u1,
-            ///  b195
-            b195: u1,
-            ///  b196
-            b196: u1,
-            ///  b197
-            b197: u1,
-            ///  b198
-            b198: u1,
-            ///  b199
-            b199: u1,
-            ///  b200
-            b200: u1,
-            ///  b201
-            b201: u1,
-            ///  b202
-            b202: u1,
-            ///  b203
-            b203: u1,
-            ///  b204
-            b204: u1,
-            ///  b205
-            b205: u1,
-            ///  b206
-            b206: u1,
-            ///  b207
-            b207: u1,
-            ///  b208
-            b208: u1,
-            ///  b209
-            b209: u1,
-            ///  b210
-            b210: u1,
-            ///  b211
-            b211: u1,
-            ///  b212
-            b212: u1,
-            ///  b213
-            b213: u1,
-            ///  b214
-            b214: u1,
-            ///  b215
-            b215: u1,
-            ///  b216
-            b216: u1,
-            ///  b217
-            b217: u1,
-            ///  b218
-            b218: u1,
-            ///  b219
-            b219: u1,
-            ///  b220
-            b220: u1,
-            ///  b221
-            b221: u1,
-            ///  b222
-            b222: u1,
-            ///  b223
-            b223: u1,
-        }),
-        ///  key registers
-        K1LR: mmio.Mmio(packed struct(u32) {
-            ///  b160
-            b160: u1,
-            ///  b161
-            b161: u1,
-            ///  b162
-            b162: u1,
-            ///  b163
-            b163: u1,
-            ///  b164
-            b164: u1,
-            ///  b165
-            b165: u1,
-            ///  b166
-            b166: u1,
-            ///  b167
-            b167: u1,
-            ///  b168
-            b168: u1,
-            ///  b169
-            b169: u1,
-            ///  b170
-            b170: u1,
-            ///  b171
-            b171: u1,
-            ///  b172
-            b172: u1,
-            ///  b173
-            b173: u1,
-            ///  b174
-            b174: u1,
-            ///  b175
-            b175: u1,
-            ///  b176
-            b176: u1,
-            ///  b177
-            b177: u1,
-            ///  b178
-            b178: u1,
-            ///  b179
-            b179: u1,
-            ///  b180
-            b180: u1,
-            ///  b181
-            b181: u1,
-            ///  b182
-            b182: u1,
-            ///  b183
-            b183: u1,
-            ///  b184
-            b184: u1,
-            ///  b185
-            b185: u1,
-            ///  b186
-            b186: u1,
-            ///  b187
-            b187: u1,
-            ///  b188
-            b188: u1,
-            ///  b189
-            b189: u1,
-            ///  b190
-            b190: u1,
-            ///  b191
-            b191: u1,
-        }),
-        ///  key registers
-        K1RR: mmio.Mmio(packed struct(u32) {
-            ///  b128
-            b128: u1,
-            ///  b129
-            b129: u1,
-            ///  b130
-            b130: u1,
-            ///  b131
-            b131: u1,
-            ///  b132
-            b132: u1,
-            ///  b133
-            b133: u1,
-            ///  b134
-            b134: u1,
-            ///  b135
-            b135: u1,
-            ///  b136
-            b136: u1,
-            ///  b137
-            b137: u1,
-            ///  b138
-            b138: u1,
-            ///  b139
-            b139: u1,
-            ///  b140
-            b140: u1,
-            ///  b141
-            b141: u1,
-            ///  b142
-            b142: u1,
-            ///  b143
-            b143: u1,
-            ///  b144
-            b144: u1,
-            ///  b145
-            b145: u1,
-            ///  b146
-            b146: u1,
-            ///  b147
-            b147: u1,
-            ///  b148
-            b148: u1,
-            ///  b149
-            b149: u1,
-            ///  b150
-            b150: u1,
-            ///  b151
-            b151: u1,
-            ///  b152
-            b152: u1,
-            ///  b153
-            b153: u1,
-            ///  b154
-            b154: u1,
-            ///  b155
-            b155: u1,
-            ///  b156
-            b156: u1,
-            ///  b157
-            b157: u1,
-            ///  b158
-            b158: u1,
-            ///  b159
-            b159: u1,
-        }),
-        ///  key registers
-        K2LR: mmio.Mmio(packed struct(u32) {
-            ///  b96
-            b96: u1,
-            ///  b97
-            b97: u1,
-            ///  b98
-            b98: u1,
-            ///  b99
-            b99: u1,
-            ///  b100
-            b100: u1,
-            ///  b101
-            b101: u1,
-            ///  b102
-            b102: u1,
-            ///  b103
-            b103: u1,
-            ///  b104
-            b104: u1,
-            ///  b105
-            b105: u1,
-            ///  b106
-            b106: u1,
-            ///  b107
-            b107: u1,
-            ///  b108
-            b108: u1,
-            ///  b109
-            b109: u1,
-            ///  b110
-            b110: u1,
-            ///  b111
-            b111: u1,
-            ///  b112
-            b112: u1,
-            ///  b113
-            b113: u1,
-            ///  b114
-            b114: u1,
-            ///  b115
-            b115: u1,
-            ///  b116
-            b116: u1,
-            ///  b117
-            b117: u1,
-            ///  b118
-            b118: u1,
-            ///  b119
-            b119: u1,
-            ///  b120
-            b120: u1,
-            ///  b121
-            b121: u1,
-            ///  b122
-            b122: u1,
-            ///  b123
-            b123: u1,
-            ///  b124
-            b124: u1,
-            ///  b125
-            b125: u1,
-            ///  b126
-            b126: u1,
-            ///  b127
-            b127: u1,
-        }),
-        ///  key registers
-        K2RR: mmio.Mmio(packed struct(u32) {
-            ///  b64
-            b64: u1,
-            ///  b65
-            b65: u1,
-            ///  b66
-            b66: u1,
-            ///  b67
-            b67: u1,
-            ///  b68
-            b68: u1,
-            ///  b69
-            b69: u1,
-            ///  b70
-            b70: u1,
-            ///  b71
-            b71: u1,
-            ///  b72
-            b72: u1,
-            ///  b73
-            b73: u1,
-            ///  b74
-            b74: u1,
-            ///  b75
-            b75: u1,
-            ///  b76
-            b76: u1,
-            ///  b77
-            b77: u1,
-            ///  b78
-            b78: u1,
-            ///  b79
-            b79: u1,
-            ///  b80
-            b80: u1,
-            ///  b81
-            b81: u1,
-            ///  b82
-            b82: u1,
-            ///  b83
-            b83: u1,
-            ///  b84
-            b84: u1,
-            ///  b85
-            b85: u1,
-            ///  b86
-            b86: u1,
-            ///  b87
-            b87: u1,
-            ///  b88
-            b88: u1,
-            ///  b89
-            b89: u1,
-            ///  b90
-            b90: u1,
-            ///  b91
-            b91: u1,
-            ///  b92
-            b92: u1,
-            ///  b93
-            b93: u1,
-            ///  b94
-            b94: u1,
-            ///  b95
-            b95: u1,
-        }),
-        ///  key registers
-        K3LR: mmio.Mmio(packed struct(u32) {
-            ///  b32
-            b32: u1,
-            ///  b33
-            b33: u1,
-            ///  b34
-            b34: u1,
-            ///  b35
-            b35: u1,
-            ///  b36
-            b36: u1,
-            ///  b37
-            b37: u1,
-            ///  b38
-            b38: u1,
-            ///  b39
-            b39: u1,
-            ///  b40
-            b40: u1,
-            ///  b41
-            b41: u1,
-            ///  b42
-            b42: u1,
-            ///  b43
-            b43: u1,
-            ///  b44
-            b44: u1,
-            ///  b45
-            b45: u1,
-            ///  b46
-            b46: u1,
-            ///  b47
-            b47: u1,
-            ///  b48
-            b48: u1,
-            ///  b49
-            b49: u1,
-            ///  b50
-            b50: u1,
-            ///  b51
-            b51: u1,
-            ///  b52
-            b52: u1,
-            ///  b53
-            b53: u1,
-            ///  b54
-            b54: u1,
-            ///  b55
-            b55: u1,
-            ///  b56
-            b56: u1,
-            ///  b57
-            b57: u1,
-            ///  b58
-            b58: u1,
-            ///  b59
-            b59: u1,
-            ///  b60
-            b60: u1,
-            ///  b61
-            b61: u1,
-            ///  b62
-            b62: u1,
-            ///  b63
-            b63: u1,
-        }),
-        ///  key registers
-        K3RR: mmio.Mmio(packed struct(u32) {
-            ///  b0
-            b0: u1,
-            ///  b1
-            b1: u1,
-            ///  b2
-            b2: u1,
-            ///  b3
-            b3: u1,
-            ///  b4
-            b4: u1,
-            ///  b5
-            b5: u1,
-            ///  b6
-            b6: u1,
-            ///  b7
-            b7: u1,
-            ///  b8
-            b8: u1,
-            ///  b9
-            b9: u1,
-            ///  b10
-            b10: u1,
-            ///  b11
-            b11: u1,
-            ///  b12
-            b12: u1,
-            ///  b13
-            b13: u1,
-            ///  b14
-            b14: u1,
-            ///  b15
-            b15: u1,
-            ///  b16
-            b16: u1,
-            ///  b17
-            b17: u1,
-            ///  b18
-            b18: u1,
-            ///  b19
-            b19: u1,
-            ///  b20
-            b20: u1,
-            ///  b21
-            b21: u1,
-            ///  b22
-            b22: u1,
-            ///  b23
-            b23: u1,
-            ///  b24
-            b24: u1,
-            ///  b25
-            b25: u1,
-            ///  b26
-            b26: u1,
-            ///  b27
-            b27: u1,
-            ///  b28
-            b28: u1,
-            ///  b29
-            b29: u1,
-            ///  b30
-            b30: u1,
-            ///  b31
-            b31: u1,
-        }),
-        ///  initialization vector registers
-        IV0LR: mmio.Mmio(packed struct(u32) {
-            ///  IV31
-            IV31: u1,
-            ///  IV30
-            IV30: u1,
-            ///  IV29
-            IV29: u1,
-            ///  IV28
-            IV28: u1,
-            ///  IV27
-            IV27: u1,
-            ///  IV26
-            IV26: u1,
-            ///  IV25
-            IV25: u1,
-            ///  IV24
-            IV24: u1,
-            ///  IV23
-            IV23: u1,
-            ///  IV22
-            IV22: u1,
-            ///  IV21
-            IV21: u1,
-            ///  IV20
-            IV20: u1,
-            ///  IV19
-            IV19: u1,
-            ///  IV18
-            IV18: u1,
-            ///  IV17
-            IV17: u1,
-            ///  IV16
-            IV16: u1,
-            ///  IV15
-            IV15: u1,
-            ///  IV14
-            IV14: u1,
-            ///  IV13
-            IV13: u1,
-            ///  IV12
-            IV12: u1,
-            ///  IV11
-            IV11: u1,
-            ///  IV10
-            IV10: u1,
-            ///  IV9
-            IV9: u1,
-            ///  IV8
-            IV8: u1,
-            ///  IV7
-            IV7: u1,
-            ///  IV6
-            IV6: u1,
-            ///  IV5
-            IV5: u1,
-            ///  IV4
-            IV4: u1,
-            ///  IV3
-            IV3: u1,
-            ///  IV2
-            IV2: u1,
-            ///  IV1
-            IV1: u1,
-            ///  IV0
-            IV0: u1,
-        }),
-        ///  initialization vector registers
-        IV0RR: mmio.Mmio(packed struct(u32) {
-            ///  IV63
-            IV63: u1,
-            ///  IV62
-            IV62: u1,
-            ///  IV61
-            IV61: u1,
-            ///  IV60
-            IV60: u1,
-            ///  IV59
-            IV59: u1,
-            ///  IV58
-            IV58: u1,
-            ///  IV57
-            IV57: u1,
-            ///  IV56
-            IV56: u1,
-            ///  IV55
-            IV55: u1,
-            ///  IV54
-            IV54: u1,
-            ///  IV53
-            IV53: u1,
-            ///  IV52
-            IV52: u1,
-            ///  IV51
-            IV51: u1,
-            ///  IV50
-            IV50: u1,
-            ///  IV49
-            IV49: u1,
-            ///  IV48
-            IV48: u1,
-            ///  IV47
-            IV47: u1,
-            ///  IV46
-            IV46: u1,
-            ///  IV45
-            IV45: u1,
-            ///  IV44
-            IV44: u1,
-            ///  IV43
-            IV43: u1,
-            ///  IV42
-            IV42: u1,
-            ///  IV41
-            IV41: u1,
-            ///  IV40
-            IV40: u1,
-            ///  IV39
-            IV39: u1,
-            ///  IV38
-            IV38: u1,
-            ///  IV37
-            IV37: u1,
-            ///  IV36
-            IV36: u1,
-            ///  IV35
-            IV35: u1,
-            ///  IV34
-            IV34: u1,
-            ///  IV33
-            IV33: u1,
-            ///  IV32
-            IV32: u1,
-        }),
-        ///  initialization vector registers
-        IV1LR: mmio.Mmio(packed struct(u32) {
-            ///  IV95
-            IV95: u1,
-            ///  IV94
-            IV94: u1,
-            ///  IV93
-            IV93: u1,
-            ///  IV92
-            IV92: u1,
-            ///  IV91
-            IV91: u1,
-            ///  IV90
-            IV90: u1,
-            ///  IV89
-            IV89: u1,
-            ///  IV88
-            IV88: u1,
-            ///  IV87
-            IV87: u1,
-            ///  IV86
-            IV86: u1,
-            ///  IV85
-            IV85: u1,
-            ///  IV84
-            IV84: u1,
-            ///  IV83
-            IV83: u1,
-            ///  IV82
-            IV82: u1,
-            ///  IV81
-            IV81: u1,
-            ///  IV80
-            IV80: u1,
-            ///  IV79
-            IV79: u1,
-            ///  IV78
-            IV78: u1,
-            ///  IV77
-            IV77: u1,
-            ///  IV76
-            IV76: u1,
-            ///  IV75
-            IV75: u1,
-            ///  IV74
-            IV74: u1,
-            ///  IV73
-            IV73: u1,
-            ///  IV72
-            IV72: u1,
-            ///  IV71
-            IV71: u1,
-            ///  IV70
-            IV70: u1,
-            ///  IV69
-            IV69: u1,
-            ///  IV68
-            IV68: u1,
-            ///  IV67
-            IV67: u1,
-            ///  IV66
-            IV66: u1,
-            ///  IV65
-            IV65: u1,
-            ///  IV64
-            IV64: u1,
-        }),
-        ///  initialization vector registers
-        IV1RR: mmio.Mmio(packed struct(u32) {
-            ///  IV127
-            IV127: u1,
-            ///  IV126
-            IV126: u1,
-            ///  IV125
-            IV125: u1,
-            ///  IV124
-            IV124: u1,
-            ///  IV123
-            IV123: u1,
-            ///  IV122
-            IV122: u1,
-            ///  IV121
-            IV121: u1,
-            ///  IV120
-            IV120: u1,
-            ///  IV119
-            IV119: u1,
-            ///  IV118
-            IV118: u1,
-            ///  IV117
-            IV117: u1,
-            ///  IV116
-            IV116: u1,
-            ///  IV115
-            IV115: u1,
-            ///  IV114
-            IV114: u1,
-            ///  IV113
-            IV113: u1,
-            ///  IV112
-            IV112: u1,
-            ///  IV111
-            IV111: u1,
-            ///  IV110
-            IV110: u1,
-            ///  IV109
-            IV109: u1,
-            ///  IV108
-            IV108: u1,
-            ///  IV107
-            IV107: u1,
-            ///  IV106
-            IV106: u1,
-            ///  IV105
-            IV105: u1,
-            ///  IV104
-            IV104: u1,
-            ///  IV103
-            IV103: u1,
-            ///  IV102
-            IV102: u1,
-            ///  IV101
-            IV101: u1,
-            ///  IV100
-            IV100: u1,
-            ///  IV99
-            IV99: u1,
-            ///  IV98
-            IV98: u1,
-            ///  IV97
-            IV97: u1,
-            ///  IV96
-            IV96: u1,
-        }),
-        ///  context swap register
-        CSGCMCCM0R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM0R
-            CSGCMCCM0R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM1R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM1R
-            CSGCMCCM1R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM2R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM2R
-            CSGCMCCM2R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM3R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM3R
-            CSGCMCCM3R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM4R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM4R
-            CSGCMCCM4R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM5R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM5R
-            CSGCMCCM5R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM6R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM6R
-            CSGCMCCM6R: u32,
-        }),
-        ///  context swap register
-        CSGCMCCM7R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCMCCM7R
-            CSGCMCCM7R: u32,
-        }),
-        ///  context swap register
-        CSGCM0R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM0R
-            CSGCM0R: u32,
-        }),
-        ///  context swap register
-        CSGCM1R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM1R
-            CSGCM1R: u32,
-        }),
-        ///  context swap register
-        CSGCM2R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM2R
-            CSGCM2R: u32,
-        }),
-        ///  context swap register
-        CSGCM3R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM3R
-            CSGCM3R: u32,
-        }),
-        ///  context swap register
-        CSGCM4R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM4R
-            CSGCM4R: u32,
-        }),
-        ///  context swap register
-        CSGCM5R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM5R
-            CSGCM5R: u32,
-        }),
-        ///  context swap register
-        CSGCM6R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM6R
-            CSGCM6R: u32,
-        }),
-        ///  context swap register
-        CSGCM7R: mmio.Mmio(packed struct(u32) {
-            ///  CSGCM7R
-            CSGCM7R: u32,
-        }),
-    };
-
-    ///  Digital camera interface
-    pub const DCMI = extern struct {
-        ///  control register 1
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Capture enable
-            CAPTURE: u1,
-            ///  Capture mode
-            CM: u1,
-            ///  Crop feature
-            CROP: u1,
-            ///  JPEG format
-            JPEG: u1,
-            ///  Embedded synchronization select
-            ESS: u1,
-            ///  Pixel clock polarity
-            PCKPOL: u1,
-            ///  Horizontal synchronization polarity
-            HSPOL: u1,
-            ///  Vertical synchronization polarity
-            VSPOL: u1,
-            ///  Frame capture rate control
-            FCRC: u2,
-            ///  Extended data mode
-            EDM: u2,
-            reserved14: u2,
-            ///  DCMI enable
-            ENABLE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  HSYNC
-            HSYNC: u1,
-            ///  VSYNC
-            VSYNC: u1,
-            ///  FIFO not empty
-            FNE: u1,
-            padding: u29,
-        }),
-        ///  raw interrupt status register
-        RIS: mmio.Mmio(packed struct(u32) {
-            ///  Capture complete raw interrupt status
-            FRAME_RIS: u1,
-            ///  Overrun raw interrupt status
-            OVR_RIS: u1,
-            ///  Synchronization error raw interrupt status
-            ERR_RIS: u1,
-            ///  VSYNC raw interrupt status
-            VSYNC_RIS: u1,
-            ///  Line raw interrupt status
-            LINE_RIS: u1,
-            padding: u27,
-        }),
-        ///  interrupt enable register
-        IER: mmio.Mmio(packed struct(u32) {
-            ///  Capture complete interrupt enable
-            FRAME_IE: u1,
-            ///  Overrun interrupt enable
-            OVR_IE: u1,
-            ///  Synchronization error interrupt enable
-            ERR_IE: u1,
-            ///  VSYNC interrupt enable
-            VSYNC_IE: u1,
-            ///  Line interrupt enable
-            LINE_IE: u1,
-            padding: u27,
-        }),
-        ///  masked interrupt status register
-        MIS: mmio.Mmio(packed struct(u32) {
-            ///  Capture complete masked interrupt status
-            FRAME_MIS: u1,
-            ///  Overrun masked interrupt status
-            OVR_MIS: u1,
-            ///  Synchronization error masked interrupt status
-            ERR_MIS: u1,
-            ///  VSYNC masked interrupt status
-            VSYNC_MIS: u1,
-            ///  Line masked interrupt status
-            LINE_MIS: u1,
-            padding: u27,
-        }),
-        ///  interrupt clear register
-        ICR: mmio.Mmio(packed struct(u32) {
-            ///  Capture complete interrupt status clear
-            FRAME_ISC: u1,
-            ///  Overrun interrupt status clear
-            OVR_ISC: u1,
-            ///  Synchronization error interrupt status clear
-            ERR_ISC: u1,
-            ///  Vertical synch interrupt status clear
-            VSYNC_ISC: u1,
-            ///  line interrupt status clear
-            LINE_ISC: u1,
-            padding: u27,
-        }),
-        ///  embedded synchronization code register
-        ESCR: mmio.Mmio(packed struct(u32) {
-            ///  Frame start delimiter code
-            FSC: u8,
-            ///  Line start delimiter code
-            LSC: u8,
-            ///  Line end delimiter code
-            LEC: u8,
-            ///  Frame end delimiter code
-            FEC: u8,
-        }),
-        ///  embedded synchronization unmask register
-        ESUR: mmio.Mmio(packed struct(u32) {
-            ///  Frame start delimiter unmask
-            FSU: u8,
-            ///  Line start delimiter unmask
-            LSU: u8,
-            ///  Line end delimiter unmask
-            LEU: u8,
-            ///  Frame end delimiter unmask
-            FEU: u8,
-        }),
-        ///  crop window start
-        CWSTRT: mmio.Mmio(packed struct(u32) {
-            ///  Horizontal offset count
-            HOFFCNT: u14,
-            reserved16: u2,
-            ///  Vertical start line count
-            VST: u13,
-            padding: u3,
-        }),
-        ///  crop window size
-        CWSIZE: mmio.Mmio(packed struct(u32) {
-            ///  Capture count
-            CAPCNT: u14,
-            reserved16: u2,
-            ///  Vertical line count
-            VLINE: u14,
-            padding: u2,
-        }),
-        ///  data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data byte 0
-            Byte0: u8,
-            ///  Data byte 1
-            Byte1: u8,
-            ///  Data byte 2
-            Byte2: u8,
-            ///  Data byte 3
-            Byte3: u8,
-        }),
-    };
-
-    ///  Flexible memory controller
-    pub const FMC = extern struct {
-        ///  SRAM/NOR-Flash chip-select control register 1
-        BCR1: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            reserved11: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            ///  CCLKEN
-            CCLKEN: u1,
-            padding: u11,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 1
-        BTR1: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 2
-        BCR2: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 2
-        BTR2: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 3
-        BCR3: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 3
-        BTR3: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        ///  SRAM/NOR-Flash chip-select control register 4
-        BCR4: mmio.Mmio(packed struct(u32) {
-            ///  MBKEN
-            MBKEN: u1,
-            ///  MUXEN
-            MUXEN: u1,
-            ///  MTYP
-            MTYP: u2,
-            ///  MWID
-            MWID: u2,
-            ///  FACCEN
-            FACCEN: u1,
-            reserved8: u1,
-            ///  BURSTEN
-            BURSTEN: u1,
-            ///  WAITPOL
-            WAITPOL: u1,
-            ///  WRAPMOD
-            WRAPMOD: u1,
-            ///  WAITCFG
-            WAITCFG: u1,
-            ///  WREN
-            WREN: u1,
-            ///  WAITEN
-            WAITEN: u1,
-            ///  EXTMOD
-            EXTMOD: u1,
-            ///  ASYNCWAIT
-            ASYNCWAIT: u1,
-            reserved19: u3,
-            ///  CBURSTRW
-            CBURSTRW: u1,
-            padding: u12,
-        }),
-        ///  SRAM/NOR-Flash chip-select timing register 4
-        BTR4: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            ///  BUSTURN
-            BUSTURN: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved96: [64]u8,
-        ///  PC Card/NAND Flash control register 2
-        PCR2: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 2
-        SR2: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 2
-        PMEM2: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 2
-        PATT2: mmio.Mmio(packed struct(u32) {
-            ///  ATTSETx
-            ATTSETx: u8,
-            ///  ATTWAITx
-            ATTWAITx: u8,
-            ///  ATTHOLDx
-            ATTHOLDx: u8,
-            ///  ATTHIZx
-            ATTHIZx: u8,
-        }),
-        reserved116: [4]u8,
-        ///  ECC result register 2
-        ECCR2: mmio.Mmio(packed struct(u32) {
-            ///  ECCx
-            ECCx: u32,
-        }),
-        reserved128: [8]u8,
-        ///  PC Card/NAND Flash control register 3
-        PCR3: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 3
-        SR3: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 3
-        PMEM3: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 3
-        PATT3: mmio.Mmio(packed struct(u32) {
-            ///  ATTSETx
-            ATTSETx: u8,
-            ///  ATTWAITx
-            ATTWAITx: u8,
-            ///  ATTHOLDx
-            ATTHOLDx: u8,
-            ///  ATTHIZx
-            ATTHIZx: u8,
-        }),
-        reserved148: [4]u8,
-        ///  ECC result register 3
-        ECCR3: mmio.Mmio(packed struct(u32) {
-            ///  ECCx
-            ECCx: u32,
-        }),
-        reserved160: [8]u8,
-        ///  PC Card/NAND Flash control register 4
-        PCR4: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  PWAITEN
-            PWAITEN: u1,
-            ///  PBKEN
-            PBKEN: u1,
-            ///  PTYP
-            PTYP: u1,
-            ///  PWID
-            PWID: u2,
-            ///  ECCEN
-            ECCEN: u1,
-            reserved9: u2,
-            ///  TCLR
-            TCLR: u4,
-            ///  TAR
-            TAR: u4,
-            ///  ECCPS
-            ECCPS: u3,
-            padding: u12,
-        }),
-        ///  FIFO status and interrupt register 4
-        SR4: mmio.Mmio(packed struct(u32) {
-            ///  IRS
-            IRS: u1,
-            ///  ILS
-            ILS: u1,
-            ///  IFS
-            IFS: u1,
-            ///  IREN
-            IREN: u1,
-            ///  ILEN
-            ILEN: u1,
-            ///  IFEN
-            IFEN: u1,
-            ///  FEMPT
-            FEMPT: u1,
-            padding: u25,
-        }),
-        ///  Common memory space timing register 4
-        PMEM4: mmio.Mmio(packed struct(u32) {
-            ///  MEMSETx
-            MEMSETx: u8,
-            ///  MEMWAITx
-            MEMWAITx: u8,
-            ///  MEMHOLDx
-            MEMHOLDx: u8,
-            ///  MEMHIZx
-            MEMHIZx: u8,
-        }),
-        ///  Attribute memory space timing register 4
-        PATT4: mmio.Mmio(packed struct(u32) {
-            ///  ATTSETx
-            ATTSETx: u8,
-            ///  ATTWAITx
-            ATTWAITx: u8,
-            ///  ATTHOLDx
-            ATTHOLDx: u8,
-            ///  ATTHIZx
-            ATTHIZx: u8,
-        }),
-        ///  I/O space timing register 4
-        PIO4: mmio.Mmio(packed struct(u32) {
-            ///  IOSETx
-            IOSETx: u8,
-            ///  IOWAITx
-            IOWAITx: u8,
-            ///  IOHOLDx
-            IOHOLDx: u8,
-            ///  IOHIZx
-            IOHIZx: u8,
-        }),
-        reserved260: [80]u8,
-        ///  SRAM/NOR-Flash write timing registers 1
-        BWTR1: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            reserved20: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved268: [4]u8,
-        ///  SRAM/NOR-Flash write timing registers 2
-        BWTR2: mmio.Mmio(packed struct(u32) {
-            ///  ADDSET
-            ADDSET: u4,
-            ///  ADDHLD
-            ADDHLD: u4,
-            ///  DATAST
-            DATAST: u8,
-            reserved20: u4,
-            ///  CLKDIV
-            CLKDIV: u4,
-            ///  DATLAT
-            DATLAT: u4,
-            ///  ACCMOD
-            ACCMOD: u2,
-            padding: u2,
-        }),
-        reserved320: [48]u8,
-        ///  SDRAM Control Register 1
-        SDCR1: mmio.Mmio(packed struct(u32) {
-            ///  Number of column address bits
-            NC: u2,
-            ///  Number of row address bits
-            NR: u2,
-            ///  Memory data bus width
-            MWID: u2,
-            ///  Number of internal banks
-            NB: u1,
-            ///  CAS latency
-            CAS: u2,
-            ///  Write protection
-            WP: u1,
-            ///  SDRAM clock configuration
-            SDCLK: u2,
-            ///  Burst read
-            RBURST: u1,
-            ///  Read pipe
-            RPIPE: u2,
-            padding: u17,
-        }),
-        ///  SDRAM Control Register 2
-        SDCR2: mmio.Mmio(packed struct(u32) {
-            ///  Number of column address bits
-            NC: u2,
-            ///  Number of row address bits
-            NR: u2,
-            ///  Memory data bus width
-            MWID: u2,
-            ///  Number of internal banks
-            NB: u1,
-            ///  CAS latency
-            CAS: u2,
-            ///  Write protection
-            WP: u1,
-            ///  SDRAM clock configuration
-            SDCLK: u2,
-            ///  Burst read
-            RBURST: u1,
-            ///  Read pipe
-            RPIPE: u2,
-            padding: u17,
-        }),
-        ///  SDRAM Timing register 1
-        SDTR1: mmio.Mmio(packed struct(u32) {
-            ///  Load Mode Register to Active
-            TMRD: u4,
-            ///  Exit self-refresh delay
-            TXSR: u4,
-            ///  Self refresh time
-            TRAS: u4,
-            ///  Row cycle delay
-            TRC: u4,
-            ///  Recovery delay
-            TWR: u4,
-            ///  Row precharge delay
-            TRP: u4,
-            ///  Row to column delay
-            TRCD: u4,
-            padding: u4,
-        }),
-        ///  SDRAM Timing register 2
-        SDTR2: mmio.Mmio(packed struct(u32) {
-            ///  Load Mode Register to Active
-            TMRD: u4,
-            ///  Exit self-refresh delay
-            TXSR: u4,
-            ///  Self refresh time
-            TRAS: u4,
-            ///  Row cycle delay
-            TRC: u4,
-            ///  Recovery delay
-            TWR: u4,
-            ///  Row precharge delay
-            TRP: u4,
-            ///  Row to column delay
-            TRCD: u4,
-            padding: u4,
-        }),
-        ///  SDRAM Command Mode register
-        SDCMR: mmio.Mmio(packed struct(u32) {
-            ///  Command mode
-            MODE: u3,
-            ///  Command target bank 2
-            CTB2: u1,
-            ///  Command target bank 1
-            CTB1: u1,
-            ///  Number of Auto-refresh
-            NRFS: u4,
-            ///  Mode Register definition
-            MRD: u13,
-            padding: u10,
-        }),
-        ///  SDRAM Refresh Timer register
-        SDRTR: mmio.Mmio(packed struct(u32) {
-            ///  Clear Refresh error flag
-            CRE: u1,
-            ///  Refresh Timer Count
-            COUNT: u13,
-            ///  RES Interrupt Enable
-            REIE: u1,
-            padding: u17,
-        }),
-        ///  SDRAM Status register
-        SDSR: mmio.Mmio(packed struct(u32) {
-            ///  Refresh error flag
-            RE: u1,
-            ///  Status Mode for Bank 1
-            MODES1: u2,
-            ///  Status Mode for Bank 2
-            MODES2: u2,
-            ///  Busy status
-            BUSY: u1,
-            padding: u26,
-        }),
-    };
-
-    ///  Debug support
-    pub const DBG = extern struct {
-        ///  IDCODE
-        DBGMCU_IDCODE: mmio.Mmio(packed struct(u32) {
-            ///  DEV_ID
-            DEV_ID: u12,
-            reserved16: u4,
-            ///  REV_ID
-            REV_ID: u16,
-        }),
-        ///  Control Register
-        DBGMCU_CR: mmio.Mmio(packed struct(u32) {
-            ///  DBG_SLEEP
-            DBG_SLEEP: u1,
-            ///  DBG_STOP
-            DBG_STOP: u1,
-            ///  DBG_STANDBY
-            DBG_STANDBY: u1,
-            reserved5: u2,
-            ///  TRACE_IOEN
-            TRACE_IOEN: u1,
-            ///  TRACE_MODE
-            TRACE_MODE: u2,
-            padding: u24,
-        }),
-        ///  Debug MCU APB1 Freeze registe
-        DBGMCU_APB1_FZ: mmio.Mmio(packed struct(u32) {
-            ///  DBG_TIM2_STOP
-            DBG_TIM2_STOP: u1,
-            ///  DBG_TIM3 _STOP
-            DBG_TIM3_STOP: u1,
-            ///  DBG_TIM4_STOP
-            DBG_TIM4_STOP: u1,
-            ///  DBG_TIM5_STOP
-            DBG_TIM5_STOP: u1,
-            ///  DBG_TIM6_STOP
-            DBG_TIM6_STOP: u1,
-            ///  DBG_TIM7_STOP
-            DBG_TIM7_STOP: u1,
-            ///  DBG_TIM12_STOP
-            DBG_TIM12_STOP: u1,
-            ///  DBG_TIM13_STOP
-            DBG_TIM13_STOP: u1,
-            ///  DBG_TIM14_STOP
-            DBG_TIM14_STOP: u1,
-            reserved11: u2,
-            ///  DBG_WWDG_STOP
-            DBG_WWDG_STOP: u1,
-            ///  DBG_IWDEG_STOP
-            DBG_IWDEG_STOP: u1,
-            reserved21: u8,
-            ///  DBG_J2C1_SMBUS_TIMEOUT
-            DBG_J2C1_SMBUS_TIMEOUT: u1,
-            ///  DBG_J2C2_SMBUS_TIMEOUT
-            DBG_J2C2_SMBUS_TIMEOUT: u1,
-            ///  DBG_J2C3SMBUS_TIMEOUT
-            DBG_J2C3SMBUS_TIMEOUT: u1,
-            reserved25: u1,
-            ///  DBG_CAN1_STOP
-            DBG_CAN1_STOP: u1,
-            ///  DBG_CAN2_STOP
-            DBG_CAN2_STOP: u1,
-            padding: u5,
-        }),
-        ///  Debug MCU APB2 Freeze registe
-        DBGMCU_APB2_FZ: mmio.Mmio(packed struct(u32) {
-            ///  TIM1 counter stopped when core is halted
-            DBG_TIM1_STOP: u1,
-            ///  TIM8 counter stopped when core is halted
-            DBG_TIM8_STOP: u1,
-            reserved16: u14,
-            ///  TIM9 counter stopped when core is halted
-            DBG_TIM9_STOP: u1,
-            ///  TIM10 counter stopped when core is halted
-            DBG_TIM10_STOP: u1,
-            ///  TIM11 counter stopped when core is halted
-            DBG_TIM11_STOP: u1,
-            padding: u13,
-        }),
-    };
-
-    ///  DMA controller
-    pub const DMA2 = extern struct {
-        ///  low interrupt status register
-        LISR: mmio.Mmio(packed struct(u32) {
-            ///  Stream x FIFO error interrupt flag (x=3..0)
-            FEIF0: u1,
-            reserved2: u1,
-            ///  Stream x direct mode error interrupt flag (x=3..0)
-            DMEIF0: u1,
-            ///  Stream x transfer error interrupt flag (x=3..0)
-            TEIF0: u1,
-            ///  Stream x half transfer interrupt flag (x=3..0)
-            HTIF0: u1,
-            ///  Stream x transfer complete interrupt flag (x = 3..0)
-            TCIF0: u1,
-            ///  Stream x FIFO error interrupt flag (x=3..0)
-            FEIF1: u1,
-            reserved8: u1,
-            ///  Stream x direct mode error interrupt flag (x=3..0)
-            DMEIF1: u1,
-            ///  Stream x transfer error interrupt flag (x=3..0)
-            TEIF1: u1,
-            ///  Stream x half transfer interrupt flag (x=3..0)
-            HTIF1: u1,
-            ///  Stream x transfer complete interrupt flag (x = 3..0)
-            TCIF1: u1,
-            reserved16: u4,
-            ///  Stream x FIFO error interrupt flag (x=3..0)
-            FEIF2: u1,
-            reserved18: u1,
-            ///  Stream x direct mode error interrupt flag (x=3..0)
-            DMEIF2: u1,
-            ///  Stream x transfer error interrupt flag (x=3..0)
-            TEIF2: u1,
-            ///  Stream x half transfer interrupt flag (x=3..0)
-            HTIF2: u1,
-            ///  Stream x transfer complete interrupt flag (x = 3..0)
-            TCIF2: u1,
-            ///  Stream x FIFO error interrupt flag (x=3..0)
-            FEIF3: u1,
-            reserved24: u1,
-            ///  Stream x direct mode error interrupt flag (x=3..0)
-            DMEIF3: u1,
-            ///  Stream x transfer error interrupt flag (x=3..0)
-            TEIF3: u1,
-            ///  Stream x half transfer interrupt flag (x=3..0)
-            HTIF3: u1,
-            ///  Stream x transfer complete interrupt flag (x = 3..0)
-            TCIF3: u1,
-            padding: u4,
-        }),
-        ///  high interrupt status register
-        HISR: mmio.Mmio(packed struct(u32) {
-            ///  Stream x FIFO error interrupt flag (x=7..4)
-            FEIF4: u1,
-            reserved2: u1,
-            ///  Stream x direct mode error interrupt flag (x=7..4)
-            DMEIF4: u1,
-            ///  Stream x transfer error interrupt flag (x=7..4)
-            TEIF4: u1,
-            ///  Stream x half transfer interrupt flag (x=7..4)
-            HTIF4: u1,
-            ///  Stream x transfer complete interrupt flag (x=7..4)
-            TCIF4: u1,
-            ///  Stream x FIFO error interrupt flag (x=7..4)
-            FEIF5: u1,
-            reserved8: u1,
-            ///  Stream x direct mode error interrupt flag (x=7..4)
-            DMEIF5: u1,
-            ///  Stream x transfer error interrupt flag (x=7..4)
-            TEIF5: u1,
-            ///  Stream x half transfer interrupt flag (x=7..4)
-            HTIF5: u1,
-            ///  Stream x transfer complete interrupt flag (x=7..4)
-            TCIF5: u1,
-            reserved16: u4,
-            ///  Stream x FIFO error interrupt flag (x=7..4)
-            FEIF6: u1,
-            reserved18: u1,
-            ///  Stream x direct mode error interrupt flag (x=7..4)
-            DMEIF6: u1,
-            ///  Stream x transfer error interrupt flag (x=7..4)
-            TEIF6: u1,
-            ///  Stream x half transfer interrupt flag (x=7..4)
-            HTIF6: u1,
-            ///  Stream x transfer complete interrupt flag (x=7..4)
-            TCIF6: u1,
-            ///  Stream x FIFO error interrupt flag (x=7..4)
-            FEIF7: u1,
-            reserved24: u1,
-            ///  Stream x direct mode error interrupt flag (x=7..4)
-            DMEIF7: u1,
-            ///  Stream x transfer error interrupt flag (x=7..4)
-            TEIF7: u1,
-            ///  Stream x half transfer interrupt flag (x=7..4)
-            HTIF7: u1,
-            ///  Stream x transfer complete interrupt flag (x=7..4)
-            TCIF7: u1,
-            padding: u4,
-        }),
-        ///  low interrupt flag clear register
-        LIFCR: mmio.Mmio(packed struct(u32) {
-            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
-            CFEIF0: u1,
-            reserved2: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
-            CDMEIF0: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 3..0)
-            CTEIF0: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 3..0)
-            CHTIF0: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
-            CTCIF0: u1,
-            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
-            CFEIF1: u1,
-            reserved8: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
-            CDMEIF1: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 3..0)
-            CTEIF1: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 3..0)
-            CHTIF1: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
-            CTCIF1: u1,
-            reserved16: u4,
-            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
-            CFEIF2: u1,
-            reserved18: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
-            CDMEIF2: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 3..0)
-            CTEIF2: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 3..0)
-            CHTIF2: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
-            CTCIF2: u1,
-            ///  Stream x clear FIFO error interrupt flag (x = 3..0)
-            CFEIF3: u1,
-            reserved24: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 3..0)
-            CDMEIF3: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 3..0)
-            CTEIF3: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 3..0)
-            CHTIF3: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 3..0)
-            CTCIF3: u1,
-            padding: u4,
-        }),
-        ///  high interrupt flag clear register
-        HIFCR: mmio.Mmio(packed struct(u32) {
-            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
-            CFEIF4: u1,
-            reserved2: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
-            CDMEIF4: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 7..4)
-            CTEIF4: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 7..4)
-            CHTIF4: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
-            CTCIF4: u1,
-            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
-            CFEIF5: u1,
-            reserved8: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
-            CDMEIF5: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 7..4)
-            CTEIF5: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 7..4)
-            CHTIF5: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
-            CTCIF5: u1,
-            reserved16: u4,
-            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
-            CFEIF6: u1,
-            reserved18: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
-            CDMEIF6: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 7..4)
-            CTEIF6: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 7..4)
-            CHTIF6: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
-            CTCIF6: u1,
-            ///  Stream x clear FIFO error interrupt flag (x = 7..4)
-            CFEIF7: u1,
-            reserved24: u1,
-            ///  Stream x clear direct mode error interrupt flag (x = 7..4)
-            CDMEIF7: u1,
-            ///  Stream x clear transfer error interrupt flag (x = 7..4)
-            CTEIF7: u1,
-            ///  Stream x clear half transfer interrupt flag (x = 7..4)
-            CHTIF7: u1,
-            ///  Stream x clear transfer complete interrupt flag (x = 7..4)
-            CTCIF7: u1,
-            padding: u4,
-        }),
-        ///  stream x configuration register
-        S0CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            reserved21: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S0NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S0PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S0M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S0M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S0FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S1CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S1NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S1PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S1M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S1M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S1FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S2CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S2NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S2PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S2M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S2M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S2FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S3CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S3NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S3PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S3M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S3M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S3FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S4CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S4NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S4PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S4M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S4M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S4FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S5CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S5NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S5PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S5M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S5M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S5FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S6CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S6NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S6PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S6M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S6M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S6FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-        ///  stream x configuration register
-        S7CR: mmio.Mmio(packed struct(u32) {
-            ///  Stream enable / flag stream ready when read low
-            EN: u1,
-            ///  Direct mode error interrupt enable
-            DMEIE: u1,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Half transfer interrupt enable
-            HTIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Peripheral flow controller
-            PFCTRL: u1,
-            ///  Data transfer direction
-            DIR: u2,
-            ///  Circular mode
-            CIRC: u1,
-            ///  Peripheral increment mode
-            PINC: u1,
-            ///  Memory increment mode
-            MINC: u1,
-            ///  Peripheral data size
-            PSIZE: u2,
-            ///  Memory data size
-            MSIZE: u2,
-            ///  Peripheral increment offset size
-            PINCOS: u1,
-            ///  Priority level
-            PL: u2,
-            ///  Double buffer mode
-            DBM: u1,
-            ///  Current target (only in double buffer mode)
-            CT: u1,
-            ///  ACK
-            ACK: u1,
-            ///  Peripheral burst transfer configuration
-            PBURST: u2,
-            ///  Memory burst transfer configuration
-            MBURST: u2,
-            ///  Channel selection
-            CHSEL: u3,
-            padding: u4,
-        }),
-        ///  stream x number of data register
-        S7NDTR: mmio.Mmio(packed struct(u32) {
-            ///  Number of data items to transfer
-            NDT: u16,
-            padding: u16,
-        }),
-        ///  stream x peripheral address register
-        S7PAR: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral address
-            PA: u32,
-        }),
-        ///  stream x memory 0 address register
-        S7M0AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 0 address
-            M0A: u32,
-        }),
-        ///  stream x memory 1 address register
-        S7M1AR: mmio.Mmio(packed struct(u32) {
-            ///  Memory 1 address (used in case of Double buffer mode)
-            M1A: u32,
-        }),
-        ///  stream x FIFO control register
-        S7FCR: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold selection
-            FTH: u2,
-            ///  Direct mode disable
-            DMDIS: u1,
-            ///  FIFO status
-            FS: u3,
-            reserved7: u1,
-            ///  FIFO error interrupt enable
-            FEIE: u1,
-            padding: u24,
-        }),
-    };
-
-    ///  System control block ACTLR
-    pub const SCB_ACTRL = extern struct {
-        ///  Auxiliary control register
-        ACTRL: mmio.Mmio(packed struct(u32) {
-            ///  DISMCYCINT
-            DISMCYCINT: u1,
-            ///  DISDEFWBUF
-            DISDEFWBUF: u1,
-            ///  DISFOLD
-            DISFOLD: u1,
-            reserved8: u5,
-            ///  DISFPCA
-            DISFPCA: u1,
-            ///  DISOOFP
-            DISOOFP: u1,
-            padding: u22,
-        }),
-    };
-
-    ///  Reset and clock control
-    pub const RCC = extern struct {
-        ///  clock control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Internal high-speed clock enable
-            HSION: u1,
-            ///  Internal high-speed clock ready flag
-            HSIRDY: u1,
-            reserved3: u1,
-            ///  Internal high-speed clock trimming
-            HSITRIM: u5,
-            ///  Internal high-speed clock calibration
-            HSICAL: u8,
-            ///  HSE clock enable
-            HSEON: u1,
-            ///  HSE clock ready flag
-            HSERDY: u1,
-            ///  HSE clock bypass
-            HSEBYP: u1,
-            ///  Clock security system enable
-            CSSON: u1,
-            reserved24: u4,
-            ///  Main PLL (PLL) enable
-            PLLON: u1,
-            ///  Main PLL (PLL) clock ready flag
-            PLLRDY: u1,
-            ///  PLLI2S enable
-            PLLI2SON: u1,
-            ///  PLLI2S clock ready flag
-            PLLI2SRDY: u1,
-            padding: u4,
-        }),
-        ///  PLL configuration register
-        PLLCFGR: mmio.Mmio(packed struct(u32) {
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM0: u1,
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM1: u1,
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM2: u1,
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM3: u1,
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM4: u1,
-            ///  Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock
-            PLLM5: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN0: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN1: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN2: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN3: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN4: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN5: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN6: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN7: u1,
-            ///  Main PLL (PLL) multiplication factor for VCO
-            PLLN8: u1,
-            reserved16: u1,
-            ///  Main PLL (PLL) division factor for main system clock
-            PLLP0: u1,
-            ///  Main PLL (PLL) division factor for main system clock
-            PLLP1: u1,
-            reserved22: u4,
-            ///  Main PLL(PLL) and audio PLL (PLLI2S) entry clock source
-            PLLSRC: u1,
-            reserved24: u1,
-            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
-            PLLQ0: u1,
-            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
-            PLLQ1: u1,
-            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
-            PLLQ2: u1,
-            ///  Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks
-            PLLQ3: u1,
-            padding: u4,
-        }),
-        ///  clock configuration register
-        CFGR: mmio.Mmio(packed struct(u32) {
-            ///  System clock switch
-            SW0: u1,
-            ///  System clock switch
-            SW1: u1,
-            ///  System clock switch status
-            SWS0: u1,
-            ///  System clock switch status
-            SWS1: u1,
-            ///  AHB prescaler
-            HPRE: u4,
-            reserved10: u2,
-            ///  APB Low speed prescaler (APB1)
-            PPRE1: u3,
-            ///  APB high-speed prescaler (APB2)
-            PPRE2: u3,
-            ///  HSE division factor for RTC clock
-            RTCPRE: u5,
-            ///  Microcontroller clock output 1
-            MCO1: u2,
-            ///  I2S clock selection
-            I2SSRC: u1,
-            ///  MCO1 prescaler
-            MCO1PRE: u3,
-            ///  MCO2 prescaler
-            MCO2PRE: u3,
-            ///  Microcontroller clock output 2
-            MCO2: u2,
-        }),
-        ///  clock interrupt register
-        CIR: mmio.Mmio(packed struct(u32) {
-            ///  LSI ready interrupt flag
-            LSIRDYF: u1,
-            ///  LSE ready interrupt flag
-            LSERDYF: u1,
-            ///  HSI ready interrupt flag
-            HSIRDYF: u1,
-            ///  HSE ready interrupt flag
-            HSERDYF: u1,
-            ///  Main PLL (PLL) ready interrupt flag
-            PLLRDYF: u1,
-            ///  PLLI2S ready interrupt flag
-            PLLI2SRDYF: u1,
-            reserved7: u1,
-            ///  Clock security system interrupt flag
-            CSSF: u1,
-            ///  LSI ready interrupt enable
-            LSIRDYIE: u1,
-            ///  LSE ready interrupt enable
-            LSERDYIE: u1,
-            ///  HSI ready interrupt enable
-            HSIRDYIE: u1,
-            ///  HSE ready interrupt enable
-            HSERDYIE: u1,
-            ///  Main PLL (PLL) ready interrupt enable
-            PLLRDYIE: u1,
-            ///  PLLI2S ready interrupt enable
-            PLLI2SRDYIE: u1,
-            reserved16: u2,
-            ///  LSI ready interrupt clear
-            LSIRDYC: u1,
-            ///  LSE ready interrupt clear
-            LSERDYC: u1,
-            ///  HSI ready interrupt clear
-            HSIRDYC: u1,
-            ///  HSE ready interrupt clear
-            HSERDYC: u1,
-            ///  Main PLL(PLL) ready interrupt clear
-            PLLRDYC: u1,
-            ///  PLLI2S ready interrupt clear
-            PLLI2SRDYC: u1,
-            reserved23: u1,
-            ///  Clock security system interrupt clear
-            CSSC: u1,
-            padding: u8,
-        }),
-        ///  AHB1 peripheral reset register
-        AHB1RSTR: mmio.Mmio(packed struct(u32) {
-            ///  IO port A reset
-            GPIOARST: u1,
-            ///  IO port B reset
-            GPIOBRST: u1,
-            ///  IO port C reset
-            GPIOCRST: u1,
-            ///  IO port D reset
-            GPIODRST: u1,
-            ///  IO port E reset
-            GPIOERST: u1,
-            ///  IO port F reset
-            GPIOFRST: u1,
-            ///  IO port G reset
-            GPIOGRST: u1,
-            ///  IO port H reset
-            GPIOHRST: u1,
-            ///  IO port I reset
-            GPIOIRST: u1,
-            reserved12: u3,
-            ///  CRC reset
-            CRCRST: u1,
-            reserved21: u8,
-            ///  DMA2 reset
-            DMA1RST: u1,
-            ///  DMA2 reset
-            DMA2RST: u1,
-            reserved25: u2,
-            ///  Ethernet MAC reset
-            ETHMACRST: u1,
-            reserved29: u3,
-            ///  USB OTG HS module reset
-            OTGHSRST: u1,
-            padding: u2,
-        }),
-        ///  AHB2 peripheral reset register
-        AHB2RSTR: mmio.Mmio(packed struct(u32) {
-            ///  Camera interface reset
-            DCMIRST: u1,
-            reserved4: u3,
-            ///  Cryptographic module reset
-            CRYPRST: u1,
-            ///  Hash module reset
-            HSAHRST: u1,
-            ///  Random number generator module reset
-            RNGRST: u1,
-            ///  USB OTG FS module reset
-            OTGFSRST: u1,
-            padding: u24,
-        }),
-        ///  AHB3 peripheral reset register
-        AHB3RSTR: mmio.Mmio(packed struct(u32) {
-            ///  Flexible memory controller module reset
-            FMCRST: u1,
-            padding: u31,
-        }),
-        reserved32: [4]u8,
-        ///  APB1 peripheral reset register
-        APB1RSTR: mmio.Mmio(packed struct(u32) {
-            ///  TIM2 reset
-            TIM2RST: u1,
-            ///  TIM3 reset
-            TIM3RST: u1,
-            ///  TIM4 reset
-            TIM4RST: u1,
-            ///  TIM5 reset
-            TIM5RST: u1,
-            ///  TIM6 reset
-            TIM6RST: u1,
-            ///  TIM7 reset
-            TIM7RST: u1,
-            ///  TIM12 reset
-            TIM12RST: u1,
-            ///  TIM13 reset
-            TIM13RST: u1,
-            ///  TIM14 reset
-            TIM14RST: u1,
-            reserved11: u2,
-            ///  Window watchdog reset
-            WWDGRST: u1,
-            reserved14: u2,
-            ///  SPI 2 reset
-            SPI2RST: u1,
-            ///  SPI 3 reset
-            SPI3RST: u1,
-            reserved17: u1,
-            ///  USART 2 reset
-            UART2RST: u1,
-            ///  USART 3 reset
-            UART3RST: u1,
-            ///  USART 4 reset
-            UART4RST: u1,
-            ///  USART 5 reset
-            UART5RST: u1,
-            ///  I2C 1 reset
-            I2C1RST: u1,
-            ///  I2C 2 reset
-            I2C2RST: u1,
-            ///  I2C3 reset
-            I2C3RST: u1,
-            reserved25: u1,
-            ///  CAN1 reset
-            CAN1RST: u1,
-            ///  CAN2 reset
-            CAN2RST: u1,
-            reserved28: u1,
-            ///  Power interface reset
-            PWRRST: u1,
-            ///  DAC reset
-            DACRST: u1,
-            padding: u2,
-        }),
-        ///  APB2 peripheral reset register
-        APB2RSTR: mmio.Mmio(packed struct(u32) {
-            ///  TIM1 reset
-            TIM1RST: u1,
-            ///  TIM8 reset
-            TIM8RST: u1,
-            reserved4: u2,
-            ///  USART1 reset
-            USART1RST: u1,
-            ///  USART6 reset
-            USART6RST: u1,
-            reserved8: u2,
-            ///  ADC interface reset (common to all ADCs)
-            ADCRST: u1,
-            reserved11: u2,
-            ///  SDIO reset
-            SDIORST: u1,
-            ///  SPI 1 reset
-            SPI1RST: u1,
-            reserved14: u1,
-            ///  System configuration controller reset
-            SYSCFGRST: u1,
-            reserved16: u1,
-            ///  TIM9 reset
-            TIM9RST: u1,
-            ///  TIM10 reset
-            TIM10RST: u1,
-            ///  TIM11 reset
-            TIM11RST: u1,
-            padding: u13,
-        }),
-        reserved48: [8]u8,
-        ///  AHB1 peripheral clock register
-        AHB1ENR: mmio.Mmio(packed struct(u32) {
-            ///  IO port A clock enable
-            GPIOAEN: u1,
-            ///  IO port B clock enable
-            GPIOBEN: u1,
-            ///  IO port C clock enable
-            GPIOCEN: u1,
-            ///  IO port D clock enable
-            GPIODEN: u1,
-            ///  IO port E clock enable
-            GPIOEEN: u1,
-            ///  IO port F clock enable
-            GPIOFEN: u1,
-            ///  IO port G clock enable
-            GPIOGEN: u1,
-            ///  IO port H clock enable
-            GPIOHEN: u1,
-            ///  IO port I clock enable
-            GPIOIEN: u1,
-            reserved12: u3,
-            ///  CRC clock enable
-            CRCEN: u1,
-            reserved18: u5,
-            ///  Backup SRAM interface clock enable
-            BKPSRAMEN: u1,
-            reserved20: u1,
-            ///  CCM data RAM clock enable
-            CCMDATARAMEN: u1,
-            ///  DMA1 clock enable
-            DMA1EN: u1,
-            ///  DMA2 clock enable
-            DMA2EN: u1,
-            reserved25: u2,
-            ///  Ethernet MAC clock enable
-            ETHMACEN: u1,
-            ///  Ethernet Transmission clock enable
-            ETHMACTXEN: u1,
-            ///  Ethernet Reception clock enable
-            ETHMACRXEN: u1,
-            ///  Ethernet PTP clock enable
-            ETHMACPTPEN: u1,
-            ///  USB OTG HS clock enable
-            OTGHSEN: u1,
-            ///  USB OTG HSULPI clock enable
-            OTGHSULPIEN: u1,
-            padding: u1,
-        }),
-        ///  AHB2 peripheral clock enable register
-        AHB2ENR: mmio.Mmio(packed struct(u32) {
-            ///  Camera interface enable
-            DCMIEN: u1,
-            reserved4: u3,
-            ///  Cryptographic modules clock enable
-            CRYPEN: u1,
-            ///  Hash modules clock enable
-            HASHEN: u1,
-            ///  Random number generator clock enable
-            RNGEN: u1,
-            ///  USB OTG FS clock enable
-            OTGFSEN: u1,
-            padding: u24,
-        }),
-        ///  AHB3 peripheral clock enable register
-        AHB3ENR: mmio.Mmio(packed struct(u32) {
-            ///  Flexible memory controller module clock enable
-            FMCEN: u1,
-            padding: u31,
-        }),
-        reserved64: [4]u8,
-        ///  APB1 peripheral clock enable register
-        APB1ENR: mmio.Mmio(packed struct(u32) {
-            ///  TIM2 clock enable
-            TIM2EN: u1,
-            ///  TIM3 clock enable
-            TIM3EN: u1,
-            ///  TIM4 clock enable
-            TIM4EN: u1,
-            ///  TIM5 clock enable
-            TIM5EN: u1,
-            ///  TIM6 clock enable
-            TIM6EN: u1,
-            ///  TIM7 clock enable
-            TIM7EN: u1,
-            ///  TIM12 clock enable
-            TIM12EN: u1,
-            ///  TIM13 clock enable
-            TIM13EN: u1,
-            ///  TIM14 clock enable
-            TIM14EN: u1,
-            reserved11: u2,
-            ///  Window watchdog clock enable
-            WWDGEN: u1,
-            reserved14: u2,
-            ///  SPI2 clock enable
-            SPI2EN: u1,
-            ///  SPI3 clock enable
-            SPI3EN: u1,
-            reserved17: u1,
-            ///  USART 2 clock enable
-            USART2EN: u1,
-            ///  USART3 clock enable
-            USART3EN: u1,
-            ///  UART4 clock enable
-            UART4EN: u1,
-            ///  UART5 clock enable
-            UART5EN: u1,
-            ///  I2C1 clock enable
-            I2C1EN: u1,
-            ///  I2C2 clock enable
-            I2C2EN: u1,
-            ///  I2C3 clock enable
-            I2C3EN: u1,
-            reserved25: u1,
-            ///  CAN 1 clock enable
-            CAN1EN: u1,
-            ///  CAN 2 clock enable
-            CAN2EN: u1,
-            reserved28: u1,
-            ///  Power interface clock enable
-            PWREN: u1,
-            ///  DAC interface clock enable
-            DACEN: u1,
-            padding: u2,
-        }),
-        ///  APB2 peripheral clock enable register
-        APB2ENR: mmio.Mmio(packed struct(u32) {
-            ///  TIM1 clock enable
-            TIM1EN: u1,
-            ///  TIM8 clock enable
-            TIM8EN: u1,
-            reserved4: u2,
-            ///  USART1 clock enable
-            USART1EN: u1,
-            ///  USART6 clock enable
-            USART6EN: u1,
-            reserved8: u2,
-            ///  ADC1 clock enable
-            ADC1EN: u1,
-            ///  ADC2 clock enable
-            ADC2EN: u1,
-            ///  ADC3 clock enable
-            ADC3EN: u1,
-            ///  SDIO clock enable
-            SDIOEN: u1,
-            ///  SPI1 clock enable
-            SPI1EN: u1,
-            reserved14: u1,
-            ///  System configuration controller clock enable
-            SYSCFGEN: u1,
-            reserved16: u1,
-            ///  TIM9 clock enable
-            TIM9EN: u1,
-            ///  TIM10 clock enable
-            TIM10EN: u1,
-            ///  TIM11 clock enable
-            TIM11EN: u1,
-            padding: u13,
-        }),
-        reserved80: [8]u8,
-        ///  AHB1 peripheral clock enable in low power mode register
-        AHB1LPENR: mmio.Mmio(packed struct(u32) {
-            ///  IO port A clock enable during sleep mode
-            GPIOALPEN: u1,
-            ///  IO port B clock enable during Sleep mode
-            GPIOBLPEN: u1,
-            ///  IO port C clock enable during Sleep mode
-            GPIOCLPEN: u1,
-            ///  IO port D clock enable during Sleep mode
-            GPIODLPEN: u1,
-            ///  IO port E clock enable during Sleep mode
-            GPIOELPEN: u1,
-            ///  IO port F clock enable during Sleep mode
-            GPIOFLPEN: u1,
-            ///  IO port G clock enable during Sleep mode
-            GPIOGLPEN: u1,
-            ///  IO port H clock enable during Sleep mode
-            GPIOHLPEN: u1,
-            ///  IO port I clock enable during Sleep mode
-            GPIOILPEN: u1,
-            reserved12: u3,
-            ///  CRC clock enable during Sleep mode
-            CRCLPEN: u1,
-            reserved15: u2,
-            ///  Flash interface clock enable during Sleep mode
-            FLITFLPEN: u1,
-            ///  SRAM 1interface clock enable during Sleep mode
-            SRAM1LPEN: u1,
-            ///  SRAM 2 interface clock enable during Sleep mode
-            SRAM2LPEN: u1,
-            ///  Backup SRAM interface clock enable during Sleep mode
-            BKPSRAMLPEN: u1,
-            reserved21: u2,
-            ///  DMA1 clock enable during Sleep mode
-            DMA1LPEN: u1,
-            ///  DMA2 clock enable during Sleep mode
-            DMA2LPEN: u1,
-            reserved25: u2,
-            ///  Ethernet MAC clock enable during Sleep mode
-            ETHMACLPEN: u1,
-            ///  Ethernet transmission clock enable during Sleep mode
-            ETHMACTXLPEN: u1,
-            ///  Ethernet reception clock enable during Sleep mode
-            ETHMACRXLPEN: u1,
-            ///  Ethernet PTP clock enable during Sleep mode
-            ETHMACPTPLPEN: u1,
-            ///  USB OTG HS clock enable during Sleep mode
-            OTGHSLPEN: u1,
-            ///  USB OTG HS ULPI clock enable during Sleep mode
-            OTGHSULPILPEN: u1,
-            padding: u1,
-        }),
-        ///  AHB2 peripheral clock enable in low power mode register
-        AHB2LPENR: mmio.Mmio(packed struct(u32) {
-            ///  Camera interface enable during Sleep mode
-            DCMILPEN: u1,
-            reserved4: u3,
-            ///  Cryptography modules clock enable during Sleep mode
-            CRYPLPEN: u1,
-            ///  Hash modules clock enable during Sleep mode
-            HASHLPEN: u1,
-            ///  Random number generator clock enable during Sleep mode
-            RNGLPEN: u1,
-            ///  USB OTG FS clock enable during Sleep mode
-            OTGFSLPEN: u1,
-            padding: u24,
-        }),
-        ///  AHB3 peripheral clock enable in low power mode register
-        AHB3LPENR: mmio.Mmio(packed struct(u32) {
-            ///  Flexible memory controller module clock enable during Sleep mode
-            FMCLPEN: u1,
-            padding: u31,
-        }),
-        reserved96: [4]u8,
-        ///  APB1 peripheral clock enable in low power mode register
-        APB1LPENR: mmio.Mmio(packed struct(u32) {
-            ///  TIM2 clock enable during Sleep mode
-            TIM2LPEN: u1,
-            ///  TIM3 clock enable during Sleep mode
-            TIM3LPEN: u1,
-            ///  TIM4 clock enable during Sleep mode
-            TIM4LPEN: u1,
-            ///  TIM5 clock enable during Sleep mode
-            TIM5LPEN: u1,
-            ///  TIM6 clock enable during Sleep mode
-            TIM6LPEN: u1,
-            ///  TIM7 clock enable during Sleep mode
-            TIM7LPEN: u1,
-            ///  TIM12 clock enable during Sleep mode
-            TIM12LPEN: u1,
-            ///  TIM13 clock enable during Sleep mode
-            TIM13LPEN: u1,
-            ///  TIM14 clock enable during Sleep mode
-            TIM14LPEN: u1,
-            reserved11: u2,
-            ///  Window watchdog clock enable during Sleep mode
-            WWDGLPEN: u1,
-            reserved14: u2,
-            ///  SPI2 clock enable during Sleep mode
-            SPI2LPEN: u1,
-            ///  SPI3 clock enable during Sleep mode
-            SPI3LPEN: u1,
-            reserved17: u1,
-            ///  USART2 clock enable during Sleep mode
-            USART2LPEN: u1,
-            ///  USART3 clock enable during Sleep mode
-            USART3LPEN: u1,
-            ///  UART4 clock enable during Sleep mode
-            UART4LPEN: u1,
-            ///  UART5 clock enable during Sleep mode
-            UART5LPEN: u1,
-            ///  I2C1 clock enable during Sleep mode
-            I2C1LPEN: u1,
-            ///  I2C2 clock enable during Sleep mode
-            I2C2LPEN: u1,
-            ///  I2C3 clock enable during Sleep mode
-            I2C3LPEN: u1,
-            reserved25: u1,
-            ///  CAN 1 clock enable during Sleep mode
-            CAN1LPEN: u1,
-            ///  CAN 2 clock enable during Sleep mode
-            CAN2LPEN: u1,
-            reserved28: u1,
-            ///  Power interface clock enable during Sleep mode
-            PWRLPEN: u1,
-            ///  DAC interface clock enable during Sleep mode
-            DACLPEN: u1,
-            padding: u2,
-        }),
-        ///  APB2 peripheral clock enabled in low power mode register
-        APB2LPENR: mmio.Mmio(packed struct(u32) {
-            ///  TIM1 clock enable during Sleep mode
-            TIM1LPEN: u1,
-            ///  TIM8 clock enable during Sleep mode
-            TIM8LPEN: u1,
-            reserved4: u2,
-            ///  USART1 clock enable during Sleep mode
-            USART1LPEN: u1,
-            ///  USART6 clock enable during Sleep mode
-            USART6LPEN: u1,
-            reserved8: u2,
-            ///  ADC1 clock enable during Sleep mode
-            ADC1LPEN: u1,
-            ///  ADC2 clock enable during Sleep mode
-            ADC2LPEN: u1,
-            ///  ADC 3 clock enable during Sleep mode
-            ADC3LPEN: u1,
-            ///  SDIO clock enable during Sleep mode
-            SDIOLPEN: u1,
-            ///  SPI 1 clock enable during Sleep mode
-            SPI1LPEN: u1,
-            reserved14: u1,
-            ///  System configuration controller clock enable during Sleep mode
-            SYSCFGLPEN: u1,
-            reserved16: u1,
-            ///  TIM9 clock enable during sleep mode
-            TIM9LPEN: u1,
-            ///  TIM10 clock enable during Sleep mode
-            TIM10LPEN: u1,
-            ///  TIM11 clock enable during Sleep mode
-            TIM11LPEN: u1,
-            padding: u13,
-        }),
-        reserved112: [8]u8,
-        ///  Backup domain control register
-        BDCR: mmio.Mmio(packed struct(u32) {
-            ///  External low-speed oscillator enable
-            LSEON: u1,
-            ///  External low-speed oscillator ready
-            LSERDY: u1,
-            ///  External low-speed oscillator bypass
-            LSEBYP: u1,
-            reserved8: u5,
-            ///  RTC clock source selection
-            RTCSEL0: u1,
-            ///  RTC clock source selection
-            RTCSEL1: u1,
-            reserved15: u5,
-            ///  RTC clock enable
-            RTCEN: u1,
-            ///  Backup domain software reset
-            BDRST: u1,
-            padding: u15,
-        }),
-        ///  clock control & status register
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  Internal low-speed oscillator enable
-            LSION: u1,
-            ///  Internal low-speed oscillator ready
-            LSIRDY: u1,
-            reserved24: u22,
-            ///  Remove reset flag
-            RMVF: u1,
-            ///  BOR reset flag
-            BORRSTF: u1,
-            ///  PIN reset flag
-            PADRSTF: u1,
-            ///  POR/PDR reset flag
-            PORRSTF: u1,
-            ///  Software reset flag
-            SFTRSTF: u1,
-            ///  Independent watchdog reset flag
-            WDGRSTF: u1,
-            ///  Window watchdog reset flag
-            WWDGRSTF: u1,
-            ///  Low-power reset flag
-            LPWRRSTF: u1,
-        }),
-        reserved128: [8]u8,
-        ///  spread spectrum clock generation register
-        SSCGR: mmio.Mmio(packed struct(u32) {
-            ///  Modulation period
-            MODPER: u13,
-            ///  Incrementation step
-            INCSTEP: u15,
-            reserved30: u2,
-            ///  Spread Select
-            SPREADSEL: u1,
-            ///  Spread spectrum modulation enable
-            SSCGEN: u1,
-        }),
-        ///  PLLI2S configuration register
-        PLLI2SCFGR: mmio.Mmio(packed struct(u32) {
-            reserved6: u6,
-            ///  PLLI2S multiplication factor for VCO
-            PLLI2SN: u9,
-            reserved24: u9,
-            ///  PLLI2S division factor for SAI1 clock
-            PLLI2SQ: u4,
-            ///  PLLI2S division factor for I2S clocks
-            PLLI2SR: u3,
-            padding: u1,
-        }),
-        ///  RCC PLL configuration register
-        PLLSAICFGR: mmio.Mmio(packed struct(u32) {
-            reserved6: u6,
-            ///  PLLSAI division factor for VCO
-            PLLSAIN: u9,
-            reserved24: u9,
-            ///  PLLSAI division factor for SAI1 clock
-            PLLSAIQ: u4,
-            ///  PLLSAI division factor for LCD clock
-            PLLSAIR: u3,
-            padding: u1,
-        }),
-        ///  RCC Dedicated Clock Configuration Register
-        DCKCFGR: mmio.Mmio(packed struct(u32) {
-            ///  PLLI2S division factor for SAI1 clock
-            PLLI2SDIVQ: u5,
-            reserved8: u3,
-            ///  PLLSAI division factor for SAI1 clock
-            PLLSAIDIVQ: u5,
-            reserved16: u3,
-            ///  division factor for LCD_CLK
-            PLLSAIDIVR: u2,
-            reserved20: u2,
-            ///  SAI1-A clock source selection
-            SAI1ASRC: u2,
-            ///  SAI1-B clock source selection
-            SAI1BSRC: u2,
-            ///  Timers clocks prescalers selection
-            TIMPRE: u1,
-            padding: u7,
-        }),
-    };
-
-    ///  General-purpose I/Os
-    pub const GPIOK = extern struct {
-        ///  GPIO port mode register
-        MODER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            MODER0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER15: u2,
-        }),
-        ///  GPIO port output type register
-        OTYPER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OT0: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT1: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT2: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT3: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT4: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT5: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT6: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT7: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT8: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT9: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT10: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT11: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT12: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT13: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT14: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output speed register
-        OSPEEDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR15: u2,
-        }),
-        ///  GPIO port pull-up/pull-down register
-        PUPDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR15: u2,
-        }),
-        ///  GPIO port input data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Port input data (y = 0..15)
-            IDR0: u1,
-            ///  Port input data (y = 0..15)
-            IDR1: u1,
-            ///  Port input data (y = 0..15)
-            IDR2: u1,
-            ///  Port input data (y = 0..15)
-            IDR3: u1,
-            ///  Port input data (y = 0..15)
-            IDR4: u1,
-            ///  Port input data (y = 0..15)
-            IDR5: u1,
-            ///  Port input data (y = 0..15)
-            IDR6: u1,
-            ///  Port input data (y = 0..15)
-            IDR7: u1,
-            ///  Port input data (y = 0..15)
-            IDR8: u1,
-            ///  Port input data (y = 0..15)
-            IDR9: u1,
-            ///  Port input data (y = 0..15)
-            IDR10: u1,
-            ///  Port input data (y = 0..15)
-            IDR11: u1,
-            ///  Port input data (y = 0..15)
-            IDR12: u1,
-            ///  Port input data (y = 0..15)
-            IDR13: u1,
-            ///  Port input data (y = 0..15)
-            IDR14: u1,
-            ///  Port input data (y = 0..15)
-            IDR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output data register
-        ODR: mmio.Mmio(packed struct(u32) {
-            ///  Port output data (y = 0..15)
-            ODR0: u1,
-            ///  Port output data (y = 0..15)
-            ODR1: u1,
-            ///  Port output data (y = 0..15)
-            ODR2: u1,
-            ///  Port output data (y = 0..15)
-            ODR3: u1,
-            ///  Port output data (y = 0..15)
-            ODR4: u1,
-            ///  Port output data (y = 0..15)
-            ODR5: u1,
-            ///  Port output data (y = 0..15)
-            ODR6: u1,
-            ///  Port output data (y = 0..15)
-            ODR7: u1,
-            ///  Port output data (y = 0..15)
-            ODR8: u1,
-            ///  Port output data (y = 0..15)
-            ODR9: u1,
-            ///  Port output data (y = 0..15)
-            ODR10: u1,
-            ///  Port output data (y = 0..15)
-            ODR11: u1,
-            ///  Port output data (y = 0..15)
-            ODR12: u1,
-            ///  Port output data (y = 0..15)
-            ODR13: u1,
-            ///  Port output data (y = 0..15)
-            ODR14: u1,
-            ///  Port output data (y = 0..15)
-            ODR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port bit set/reset register
-        BSRR: mmio.Mmio(packed struct(u32) {
-            ///  Port x set bit y (y= 0..15)
-            BS0: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS1: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS2: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS3: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS4: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS5: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS6: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS7: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS8: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS9: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS10: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS11: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS12: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS13: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS14: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS15: u1,
-            ///  Port x set bit y (y= 0..15)
-            BR0: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR1: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR2: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR3: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR4: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR5: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR6: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR7: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR8: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR9: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR10: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR11: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR12: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR13: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR14: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR15: u1,
-        }),
-        ///  GPIO port configuration lock register
-        LCKR: mmio.Mmio(packed struct(u32) {
-            ///  Port x lock bit y (y= 0..15)
-            LCK0: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK1: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK2: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK3: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK4: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK5: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK6: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK7: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK8: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK9: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK10: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK11: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK12: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK13: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK14: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK15: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCKK: u1,
-            padding: u15,
-        }),
-        ///  GPIO alternate function low register
-        AFRL: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL0: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL1: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL2: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL3: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL4: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL5: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL6: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL7: u4,
-        }),
-        ///  GPIO alternate function high register
-        AFRH: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH8: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH9: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH10: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH11: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH12: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH13: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH14: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH15: u4,
-        }),
-    };
-
-    ///  Floating point unit CPACR
-    pub const FPU_CPACR = extern struct {
-        ///  Coprocessor access control register
-        CPACR: mmio.Mmio(packed struct(u32) {
-            reserved20: u20,
-            ///  CP
-            CP: u4,
-            padding: u8,
-        }),
-    };
-
-    ///  Nested vectored interrupt controller
-    pub const NVIC_STIR = extern struct {
-        ///  Software trigger interrupt register
-        STIR: mmio.Mmio(packed struct(u32) {
-            ///  Software generated interrupt ID
-            INTID: u9,
-            padding: u23,
-        }),
-    };
-
-    ///  System control block
-    pub const SCB = extern struct {
-        ///  CPUID base register
-        CPUID: mmio.Mmio(packed struct(u32) {
-            ///  Revision number
-            Revision: u4,
-            ///  Part number of the processor
-            PartNo: u12,
-            ///  Reads as 0xF
-            Constant: u4,
-            ///  Variant number
-            Variant: u4,
-            ///  Implementer code
-            Implementer: u8,
-        }),
-        ///  Interrupt control and state register
-        ICSR: mmio.Mmio(packed struct(u32) {
-            ///  Active vector
-            VECTACTIVE: u9,
-            reserved11: u2,
-            ///  Return to base level
-            RETTOBASE: u1,
-            ///  Pending vector
-            VECTPENDING: u7,
-            reserved22: u3,
-            ///  Interrupt pending flag
-            ISRPENDING: u1,
-            reserved25: u2,
-            ///  SysTick exception clear-pending bit
-            PENDSTCLR: u1,
-            ///  SysTick exception set-pending bit
-            PENDSTSET: u1,
-            ///  PendSV clear-pending bit
-            PENDSVCLR: u1,
-            ///  PendSV set-pending bit
-            PENDSVSET: u1,
-            reserved31: u2,
-            ///  NMI set-pending bit.
-            NMIPENDSET: u1,
-        }),
-        ///  Vector table offset register
-        VTOR: mmio.Mmio(packed struct(u32) {
-            reserved9: u9,
-            ///  Vector table base offset field
-            TBLOFF: u21,
-            padding: u2,
-        }),
-        ///  Application interrupt and reset control register
-        AIRCR: mmio.Mmio(packed struct(u32) {
-            ///  VECTRESET
-            VECTRESET: u1,
-            ///  VECTCLRACTIVE
-            VECTCLRACTIVE: u1,
-            ///  SYSRESETREQ
-            SYSRESETREQ: u1,
-            reserved8: u5,
-            ///  PRIGROUP
-            PRIGROUP: u3,
-            reserved15: u4,
-            ///  ENDIANESS
-            ENDIANESS: u1,
-            ///  Register key
-            VECTKEYSTAT: u16,
-        }),
-        ///  System control register
-        SCR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  SLEEPONEXIT
-            SLEEPONEXIT: u1,
-            ///  SLEEPDEEP
-            SLEEPDEEP: u1,
-            reserved4: u1,
-            ///  Send Event on Pending bit
-            SEVEONPEND: u1,
-            padding: u27,
-        }),
-        ///  Configuration and control register
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Configures how the processor enters Thread mode
-            NONBASETHRDENA: u1,
-            ///  USERSETMPEND
-            USERSETMPEND: u1,
-            reserved3: u1,
-            ///  UNALIGN_ TRP
-            UNALIGN__TRP: u1,
-            ///  DIV_0_TRP
-            DIV_0_TRP: u1,
-            reserved8: u3,
-            ///  BFHFNMIGN
-            BFHFNMIGN: u1,
-            ///  STKALIGN
-            STKALIGN: u1,
-            padding: u22,
-        }),
-        ///  System handler priority registers
-        SHPR1: mmio.Mmio(packed struct(u32) {
-            ///  Priority of system handler 4
-            PRI_4: u8,
-            ///  Priority of system handler 5
-            PRI_5: u8,
-            ///  Priority of system handler 6
-            PRI_6: u8,
-            padding: u8,
-        }),
-        ///  System handler priority registers
-        SHPR2: mmio.Mmio(packed struct(u32) {
-            reserved24: u24,
-            ///  Priority of system handler 11
-            PRI_11: u8,
-        }),
-        ///  System handler priority registers
-        SHPR3: mmio.Mmio(packed struct(u32) {
-            reserved16: u16,
-            ///  Priority of system handler 14
-            PRI_14: u8,
-            ///  Priority of system handler 15
-            PRI_15: u8,
-        }),
-        ///  System handler control and state register
-        SHCRS: mmio.Mmio(packed struct(u32) {
-            ///  Memory management fault exception active bit
-            MEMFAULTACT: u1,
-            ///  Bus fault exception active bit
-            BUSFAULTACT: u1,
-            reserved3: u1,
-            ///  Usage fault exception active bit
-            USGFAULTACT: u1,
-            reserved7: u3,
-            ///  SVC call active bit
-            SVCALLACT: u1,
-            ///  Debug monitor active bit
-            MONITORACT: u1,
-            reserved10: u1,
-            ///  PendSV exception active bit
-            PENDSVACT: u1,
-            ///  SysTick exception active bit
-            SYSTICKACT: u1,
-            ///  Usage fault exception pending bit
-            USGFAULTPENDED: u1,
-            ///  Memory management fault exception pending bit
-            MEMFAULTPENDED: u1,
-            ///  Bus fault exception pending bit
-            BUSFAULTPENDED: u1,
-            ///  SVC call pending bit
-            SVCALLPENDED: u1,
-            ///  Memory management fault enable bit
-            MEMFAULTENA: u1,
-            ///  Bus fault enable bit
-            BUSFAULTENA: u1,
-            ///  Usage fault enable bit
-            USGFAULTENA: u1,
-            padding: u13,
-        }),
-        ///  Configurable fault status register
-        CFSR_UFSR_BFSR_MMFSR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Instruction access violation flag
-            IACCVIOL: u1,
-            reserved3: u1,
-            ///  Memory manager fault on unstacking for a return from exception
-            MUNSTKERR: u1,
-            ///  Memory manager fault on stacking for exception entry.
-            MSTKERR: u1,
-            ///  MLSPERR
-            MLSPERR: u1,
-            reserved7: u1,
-            ///  Memory Management Fault Address Register (MMAR) valid flag
-            MMARVALID: u1,
-            ///  Instruction bus error
-            IBUSERR: u1,
-            ///  Precise data bus error
-            PRECISERR: u1,
-            ///  Imprecise data bus error
-            IMPRECISERR: u1,
-            ///  Bus fault on unstacking for a return from exception
-            UNSTKERR: u1,
-            ///  Bus fault on stacking for exception entry
-            STKERR: u1,
-            ///  Bus fault on floating-point lazy state preservation
-            LSPERR: u1,
-            reserved15: u1,
-            ///  Bus Fault Address Register (BFAR) valid flag
-            BFARVALID: u1,
-            ///  Undefined instruction usage fault
-            UNDEFINSTR: u1,
-            ///  Invalid state usage fault
-            INVSTATE: u1,
-            ///  Invalid PC load usage fault
-            INVPC: u1,
-            ///  No coprocessor usage fault.
-            NOCP: u1,
-            reserved24: u4,
-            ///  Unaligned access usage fault
-            UNALIGNED: u1,
-            ///  Divide by zero usage fault
-            DIVBYZERO: u1,
-            padding: u6,
-        }),
-        ///  Hard fault status register
-        HFSR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Vector table hard fault
-            VECTTBL: u1,
-            reserved30: u28,
-            ///  Forced hard fault
-            FORCED: u1,
-            ///  Reserved for Debug use
-            DEBUG_VT: u1,
-        }),
-        reserved52: [4]u8,
-        ///  Memory management fault address register
-        MMFAR: mmio.Mmio(packed struct(u32) {
-            ///  Memory management fault address
-            MMFAR: u32,
-        }),
-        ///  Bus fault address register
-        BFAR: mmio.Mmio(packed struct(u32) {
-            ///  Bus fault address
-            BFAR: u32,
-        }),
-        ///  Auxiliary fault status register
-        AFSR: mmio.Mmio(packed struct(u32) {
-            ///  Implementation defined
-            IMPDEF: u32,
-        }),
-    };
-
-    ///  SysTick timer
-    pub const STK = extern struct {
-        ///  SysTick control and status register
-        CTRL: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            ENABLE: u1,
-            ///  SysTick exception request enable
-            TICKINT: u1,
-            ///  Clock source selection
-            CLKSOURCE: u1,
-            reserved16: u13,
-            ///  COUNTFLAG
-            COUNTFLAG: u1,
-            padding: u15,
-        }),
-        ///  SysTick reload value register
-        LOAD: mmio.Mmio(packed struct(u32) {
-            ///  RELOAD value
-            RELOAD: u24,
-            padding: u8,
-        }),
-        ///  SysTick current value register
-        VAL: mmio.Mmio(packed struct(u32) {
-            ///  Current counter value
-            CURRENT: u24,
-            padding: u8,
-        }),
-        ///  SysTick calibration value register
-        CALIB: mmio.Mmio(packed struct(u32) {
-            ///  Calibration value
-            TENMS: u24,
-            reserved30: u6,
-            ///  SKEW flag: Indicates whether the TENMS value is exact
-            SKEW: u1,
-            ///  NOREF flag. Reads as zero
-            NOREF: u1,
-        }),
-    };
-
-    ///  Memory protection unit
-    pub const MPU = extern struct {
-        ///  MPU type register
-        MPU_TYPER: mmio.Mmio(packed struct(u32) {
-            ///  Separate flag
-            SEPARATE: u1,
-            reserved8: u7,
-            ///  Number of MPU data regions
-            DREGION: u8,
-            ///  Number of MPU instruction regions
-            IREGION: u8,
-            padding: u8,
-        }),
-        ///  MPU control register
-        MPU_CTRL: mmio.Mmio(packed struct(u32) {
-            ///  Enables the MPU
-            ENABLE: u1,
-            ///  Enables the operation of MPU during hard fault
-            HFNMIENA: u1,
-            ///  Enable priviliged software access to default memory map
-            PRIVDEFENA: u1,
-            padding: u29,
-        }),
-        ///  MPU region number register
-        MPU_RNR: mmio.Mmio(packed struct(u32) {
-            ///  MPU region
-            REGION: u8,
-            padding: u24,
-        }),
-        ///  MPU region base address register
-        MPU_RBAR: mmio.Mmio(packed struct(u32) {
-            ///  MPU region field
-            REGION: u4,
-            ///  MPU region number valid
-            VALID: u1,
-            ///  Region base address field
-            ADDR: u27,
-        }),
-        ///  MPU region attribute and size register
-        MPU_RASR: mmio.Mmio(packed struct(u32) {
-            ///  Region enable bit.
-            ENABLE: u1,
-            ///  Size of the MPU protection region
-            SIZE: u5,
-            reserved8: u2,
-            ///  Subregion disable bits
-            SRD: u8,
-            ///  memory attribute
-            B: u1,
-            ///  memory attribute
-            C: u1,
-            ///  Shareable memory attribute
-            S: u1,
-            ///  memory attribute
-            TEX: u3,
-            reserved24: u2,
-            ///  Access permission
-            AP: u3,
-            reserved28: u1,
-            ///  Instruction access disable bit
-            XN: u1,
-            padding: u3,
-        }),
-    };
-
-    ///  Floting point unit
-    pub const FPU = extern struct {
-        ///  Floating-point context control register
-        FPCCR: mmio.Mmio(packed struct(u32) {
-            ///  LSPACT
-            LSPACT: u1,
-            ///  USER
-            USER: u1,
-            reserved3: u1,
-            ///  THREAD
-            THREAD: u1,
-            ///  HFRDY
-            HFRDY: u1,
-            ///  MMRDY
-            MMRDY: u1,
-            ///  BFRDY
-            BFRDY: u1,
-            reserved8: u1,
-            ///  MONRDY
-            MONRDY: u1,
-            reserved30: u21,
-            ///  LSPEN
-            LSPEN: u1,
-            ///  ASPEN
-            ASPEN: u1,
-        }),
-        ///  Floating-point context address register
-        FPCAR: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Location of unpopulated floating-point
-            ADDRESS: u29,
-        }),
-        ///  Floating-point status control register
-        FPSCR: mmio.Mmio(packed struct(u32) {
-            ///  Invalid operation cumulative exception bit
-            IOC: u1,
-            ///  Division by zero cumulative exception bit.
-            DZC: u1,
-            ///  Overflow cumulative exception bit
-            OFC: u1,
-            ///  Underflow cumulative exception bit
-            UFC: u1,
-            ///  Inexact cumulative exception bit
-            IXC: u1,
-            reserved7: u2,
-            ///  Input denormal cumulative exception bit.
-            IDC: u1,
-            reserved22: u14,
-            ///  Rounding Mode control field
-            RMode: u2,
-            ///  Flush-to-zero mode control bit:
-            FZ: u1,
-            ///  Default NaN mode control bit
-            DN: u1,
-            ///  Alternative half-precision control bit
-            AHP: u1,
-            reserved28: u1,
-            ///  Overflow condition code flag
-            V: u1,
-            ///  Carry condition code flag
-            C: u1,
-            ///  Zero condition code flag
-            Z: u1,
-            ///  Negative condition code flag
-            N: u1,
-        }),
-    };
-
-    ///  Basic timers
-    pub const TIM6 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            reserved7: u3,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            padding: u24,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  Master mode selection
-            MMS: u3,
-            padding: u25,
-        }),
-        reserved12: [4]u8,
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            reserved8: u7,
-            ///  Update DMA request enable
-            UDE: u1,
-            padding: u23,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            padding: u31,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            padding: u31,
-        }),
-        reserved36: [12]u8,
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  Low counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Low Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Ethernet: MAC management counters
-    pub const Ethernet_MMC = extern struct {
-        ///  Ethernet MMC control register
-        MMCCR: mmio.Mmio(packed struct(u32) {
-            ///  CR
-            CR: u1,
-            ///  CSR
-            CSR: u1,
-            ///  ROR
-            ROR: u1,
-            ///  MCF
-            MCF: u1,
-            ///  MCP
-            MCP: u1,
-            ///  MCFHP
-            MCFHP: u1,
-            padding: u26,
-        }),
-        ///  Ethernet MMC receive interrupt register
-        MMCRIR: mmio.Mmio(packed struct(u32) {
-            reserved5: u5,
-            ///  RFCES
-            RFCES: u1,
-            ///  RFAES
-            RFAES: u1,
-            reserved17: u10,
-            ///  RGUFS
-            RGUFS: u1,
-            padding: u14,
-        }),
-        ///  Ethernet MMC transmit interrupt register
-        MMCTIR: mmio.Mmio(packed struct(u32) {
-            reserved14: u14,
-            ///  TGFSCS
-            TGFSCS: u1,
-            ///  TGFMSCS
-            TGFMSCS: u1,
-            reserved21: u5,
-            ///  TGFS
-            TGFS: u1,
-            padding: u10,
-        }),
-        ///  Ethernet MMC receive interrupt mask register
-        MMCRIMR: mmio.Mmio(packed struct(u32) {
-            reserved5: u5,
-            ///  RFCEM
-            RFCEM: u1,
-            ///  RFAEM
-            RFAEM: u1,
-            reserved17: u10,
-            ///  RGUFM
-            RGUFM: u1,
-            padding: u14,
-        }),
-        ///  Ethernet MMC transmit interrupt mask register
-        MMCTIMR: mmio.Mmio(packed struct(u32) {
-            reserved14: u14,
-            ///  TGFSCM
-            TGFSCM: u1,
-            ///  TGFMSCM
-            TGFMSCM: u1,
-            ///  TGFM
-            TGFM: u1,
-            padding: u15,
-        }),
-        reserved76: [56]u8,
-        ///  Ethernet MMC transmitted good frames after a single collision counter
-        MMCTGFSCCR: mmio.Mmio(packed struct(u32) {
-            ///  TGFSCC
-            TGFSCC: u32,
-        }),
-        ///  Ethernet MMC transmitted good frames after more than a single collision
-        MMCTGFMSCCR: mmio.Mmio(packed struct(u32) {
-            ///  TGFMSCC
-            TGFMSCC: u32,
-        }),
-        reserved104: [20]u8,
-        ///  Ethernet MMC transmitted good frames counter register
-        MMCTGFCR: mmio.Mmio(packed struct(u32) {
-            ///  HTL
-            TGFC: u32,
-        }),
-        reserved148: [40]u8,
-        ///  Ethernet MMC received frames with CRC error counter register
-        MMCRFCECR: mmio.Mmio(packed struct(u32) {
-            ///  RFCFC
-            RFCFC: u32,
-        }),
-        ///  Ethernet MMC received frames with alignment error counter register
-        MMCRFAECR: mmio.Mmio(packed struct(u32) {
-            ///  RFAEC
-            RFAEC: u32,
-        }),
-        reserved196: [40]u8,
-        ///  MMC received good unicast frames counter register
-        MMCRGUFCR: mmio.Mmio(packed struct(u32) {
-            ///  RGUFC
-            RGUFC: u32,
-        }),
-    };
-
-    ///  General-purpose I/Os
-    pub const GPIOB = extern struct {
-        ///  GPIO port mode register
-        MODER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            MODER0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER15: u2,
-        }),
-        ///  GPIO port output type register
-        OTYPER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OT0: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT1: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT2: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT3: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT4: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT5: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT6: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT7: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT8: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT9: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT10: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT11: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT12: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT13: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT14: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output speed register
-        OSPEEDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR15: u2,
-        }),
-        ///  GPIO port pull-up/pull-down register
-        PUPDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR15: u2,
-        }),
-        ///  GPIO port input data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Port input data (y = 0..15)
-            IDR0: u1,
-            ///  Port input data (y = 0..15)
-            IDR1: u1,
-            ///  Port input data (y = 0..15)
-            IDR2: u1,
-            ///  Port input data (y = 0..15)
-            IDR3: u1,
-            ///  Port input data (y = 0..15)
-            IDR4: u1,
-            ///  Port input data (y = 0..15)
-            IDR5: u1,
-            ///  Port input data (y = 0..15)
-            IDR6: u1,
-            ///  Port input data (y = 0..15)
-            IDR7: u1,
-            ///  Port input data (y = 0..15)
-            IDR8: u1,
-            ///  Port input data (y = 0..15)
-            IDR9: u1,
-            ///  Port input data (y = 0..15)
-            IDR10: u1,
-            ///  Port input data (y = 0..15)
-            IDR11: u1,
-            ///  Port input data (y = 0..15)
-            IDR12: u1,
-            ///  Port input data (y = 0..15)
-            IDR13: u1,
-            ///  Port input data (y = 0..15)
-            IDR14: u1,
-            ///  Port input data (y = 0..15)
-            IDR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output data register
-        ODR: mmio.Mmio(packed struct(u32) {
-            ///  Port output data (y = 0..15)
-            ODR0: u1,
-            ///  Port output data (y = 0..15)
-            ODR1: u1,
-            ///  Port output data (y = 0..15)
-            ODR2: u1,
-            ///  Port output data (y = 0..15)
-            ODR3: u1,
-            ///  Port output data (y = 0..15)
-            ODR4: u1,
-            ///  Port output data (y = 0..15)
-            ODR5: u1,
-            ///  Port output data (y = 0..15)
-            ODR6: u1,
-            ///  Port output data (y = 0..15)
-            ODR7: u1,
-            ///  Port output data (y = 0..15)
-            ODR8: u1,
-            ///  Port output data (y = 0..15)
-            ODR9: u1,
-            ///  Port output data (y = 0..15)
-            ODR10: u1,
-            ///  Port output data (y = 0..15)
-            ODR11: u1,
-            ///  Port output data (y = 0..15)
-            ODR12: u1,
-            ///  Port output data (y = 0..15)
-            ODR13: u1,
-            ///  Port output data (y = 0..15)
-            ODR14: u1,
-            ///  Port output data (y = 0..15)
-            ODR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port bit set/reset register
-        BSRR: mmio.Mmio(packed struct(u32) {
-            ///  Port x set bit y (y= 0..15)
-            BS0: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS1: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS2: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS3: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS4: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS5: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS6: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS7: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS8: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS9: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS10: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS11: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS12: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS13: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS14: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS15: u1,
-            ///  Port x set bit y (y= 0..15)
-            BR0: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR1: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR2: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR3: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR4: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR5: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR6: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR7: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR8: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR9: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR10: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR11: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR12: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR13: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR14: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR15: u1,
-        }),
-        ///  GPIO port configuration lock register
-        LCKR: mmio.Mmio(packed struct(u32) {
-            ///  Port x lock bit y (y= 0..15)
-            LCK0: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK1: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK2: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK3: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK4: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK5: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK6: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK7: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK8: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK9: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK10: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK11: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK12: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK13: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK14: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK15: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCKK: u1,
-            padding: u15,
-        }),
-        ///  GPIO alternate function low register
-        AFRL: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL0: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL1: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL2: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL3: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL4: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL5: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL6: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL7: u4,
-        }),
-        ///  GPIO alternate function high register
-        AFRH: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH8: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH9: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH10: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH11: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH12: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH13: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH14: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH15: u4,
-        }),
-    };
-
-    ///  General-purpose I/Os
-    pub const GPIOA = extern struct {
-        ///  GPIO port mode register
-        MODER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            MODER0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            MODER15: u2,
-        }),
-        ///  GPIO port output type register
-        OTYPER: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OT0: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT1: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT2: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT3: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT4: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT5: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT6: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT7: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT8: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT9: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT10: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT11: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT12: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT13: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT14: u1,
-            ///  Port x configuration bits (y = 0..15)
-            OT15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output speed register
-        OSPEEDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            OSPEEDR15: u2,
-        }),
-        ///  GPIO port pull-up/pull-down register
-        PUPDR: mmio.Mmio(packed struct(u32) {
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR0: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR1: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR2: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR3: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR4: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR5: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR6: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR7: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR8: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR9: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR10: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR11: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR12: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR13: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR14: u2,
-            ///  Port x configuration bits (y = 0..15)
-            PUPDR15: u2,
-        }),
-        ///  GPIO port input data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Port input data (y = 0..15)
-            IDR0: u1,
-            ///  Port input data (y = 0..15)
-            IDR1: u1,
-            ///  Port input data (y = 0..15)
-            IDR2: u1,
-            ///  Port input data (y = 0..15)
-            IDR3: u1,
-            ///  Port input data (y = 0..15)
-            IDR4: u1,
-            ///  Port input data (y = 0..15)
-            IDR5: u1,
-            ///  Port input data (y = 0..15)
-            IDR6: u1,
-            ///  Port input data (y = 0..15)
-            IDR7: u1,
-            ///  Port input data (y = 0..15)
-            IDR8: u1,
-            ///  Port input data (y = 0..15)
-            IDR9: u1,
-            ///  Port input data (y = 0..15)
-            IDR10: u1,
-            ///  Port input data (y = 0..15)
-            IDR11: u1,
-            ///  Port input data (y = 0..15)
-            IDR12: u1,
-            ///  Port input data (y = 0..15)
-            IDR13: u1,
-            ///  Port input data (y = 0..15)
-            IDR14: u1,
-            ///  Port input data (y = 0..15)
-            IDR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port output data register
-        ODR: mmio.Mmio(packed struct(u32) {
-            ///  Port output data (y = 0..15)
-            ODR0: u1,
-            ///  Port output data (y = 0..15)
-            ODR1: u1,
-            ///  Port output data (y = 0..15)
-            ODR2: u1,
-            ///  Port output data (y = 0..15)
-            ODR3: u1,
-            ///  Port output data (y = 0..15)
-            ODR4: u1,
-            ///  Port output data (y = 0..15)
-            ODR5: u1,
-            ///  Port output data (y = 0..15)
-            ODR6: u1,
-            ///  Port output data (y = 0..15)
-            ODR7: u1,
-            ///  Port output data (y = 0..15)
-            ODR8: u1,
-            ///  Port output data (y = 0..15)
-            ODR9: u1,
-            ///  Port output data (y = 0..15)
-            ODR10: u1,
-            ///  Port output data (y = 0..15)
-            ODR11: u1,
-            ///  Port output data (y = 0..15)
-            ODR12: u1,
-            ///  Port output data (y = 0..15)
-            ODR13: u1,
-            ///  Port output data (y = 0..15)
-            ODR14: u1,
-            ///  Port output data (y = 0..15)
-            ODR15: u1,
-            padding: u16,
-        }),
-        ///  GPIO port bit set/reset register
-        BSRR: mmio.Mmio(packed struct(u32) {
-            ///  Port x set bit y (y= 0..15)
-            BS0: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS1: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS2: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS3: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS4: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS5: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS6: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS7: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS8: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS9: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS10: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS11: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS12: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS13: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS14: u1,
-            ///  Port x set bit y (y= 0..15)
-            BS15: u1,
-            ///  Port x set bit y (y= 0..15)
-            BR0: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR1: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR2: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR3: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR4: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR5: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR6: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR7: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR8: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR9: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR10: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR11: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR12: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR13: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR14: u1,
-            ///  Port x reset bit y (y = 0..15)
-            BR15: u1,
-        }),
-        ///  GPIO port configuration lock register
-        LCKR: mmio.Mmio(packed struct(u32) {
-            ///  Port x lock bit y (y= 0..15)
-            LCK0: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK1: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK2: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK3: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK4: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK5: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK6: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK7: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK8: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK9: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK10: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK11: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK12: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK13: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK14: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCK15: u1,
-            ///  Port x lock bit y (y= 0..15)
-            LCKK: u1,
-            padding: u15,
-        }),
-        ///  GPIO alternate function low register
-        AFRL: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL0: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL1: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL2: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL3: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL4: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL5: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL6: u4,
-            ///  Alternate function selection for port x bit y (y = 0..7)
-            AFRL7: u4,
-        }),
-        ///  GPIO alternate function high register
-        AFRH: mmio.Mmio(packed struct(u32) {
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH8: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH9: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH10: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH11: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH12: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH13: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH14: u4,
-            ///  Alternate function selection for port x bit y (y = 8..15)
-            AFRH15: u4,
-        }),
-    };
-
-    ///  System configuration controller
-    pub const SYSCFG = extern struct {
-        ///  memory remap register
-        MEMRM: mmio.Mmio(packed struct(u32) {
-            ///  Memory mapping selection
-            MEM_MODE: u3,
-            reserved8: u5,
-            ///  Flash bank mode selection
-            FB_MODE: u1,
-            reserved10: u1,
-            ///  FMC memory mapping swap
-            SWP_FMC: u2,
-            padding: u20,
-        }),
-        ///  peripheral mode configuration register
-        PMC: mmio.Mmio(packed struct(u32) {
-            reserved16: u16,
-            ///  ADC1DC2
-            ADC1DC2: u1,
-            ///  ADC2DC2
-            ADC2DC2: u1,
-            ///  ADC3DC2
-            ADC3DC2: u1,
-            reserved23: u4,
-            ///  Ethernet PHY interface selection
-            MII_RMII_SEL: u1,
-            padding: u8,
-        }),
-        ///  external interrupt configuration register 1
-        EXTICR1: mmio.Mmio(packed struct(u32) {
-            ///  EXTI x configuration (x = 0 to 3)
-            EXTI0: u4,
-            ///  EXTI x configuration (x = 0 to 3)
-            EXTI1: u4,
-            ///  EXTI x configuration (x = 0 to 3)
-            EXTI2: u4,
-            ///  EXTI x configuration (x = 0 to 3)
-            EXTI3: u4,
-            padding: u16,
-        }),
-        ///  external interrupt configuration register 2
-        EXTICR2: mmio.Mmio(packed struct(u32) {
-            ///  EXTI x configuration (x = 4 to 7)
-            EXTI4: u4,
-            ///  EXTI x configuration (x = 4 to 7)
-            EXTI5: u4,
-            ///  EXTI x configuration (x = 4 to 7)
-            EXTI6: u4,
-            ///  EXTI x configuration (x = 4 to 7)
-            EXTI7: u4,
-            padding: u16,
-        }),
-        ///  external interrupt configuration register 3
-        EXTICR3: mmio.Mmio(packed struct(u32) {
-            ///  EXTI x configuration (x = 8 to 11)
-            EXTI8: u4,
-            ///  EXTI x configuration (x = 8 to 11)
-            EXTI9: u4,
-            ///  EXTI10
-            EXTI10: u4,
-            ///  EXTI x configuration (x = 8 to 11)
-            EXTI11: u4,
-            padding: u16,
-        }),
-        ///  external interrupt configuration register 4
-        EXTICR4: mmio.Mmio(packed struct(u32) {
-            ///  EXTI x configuration (x = 12 to 15)
-            EXTI12: u4,
-            ///  EXTI x configuration (x = 12 to 15)
-            EXTI13: u4,
-            ///  EXTI x configuration (x = 12 to 15)
-            EXTI14: u4,
-            ///  EXTI x configuration (x = 12 to 15)
-            EXTI15: u4,
-            padding: u16,
-        }),
-        reserved32: [8]u8,
-        ///  Compensation cell control register
-        CMPCR: mmio.Mmio(packed struct(u32) {
-            ///  Compensation cell power-down
-            CMP_PD: u1,
-            reserved8: u7,
-            ///  READY
-            READY: u1,
-            padding: u23,
-        }),
-    };
-
-    ///  Serial peripheral interface
-    pub const SPI1 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Clock phase
-            CPHA: u1,
-            ///  Clock polarity
-            CPOL: u1,
-            ///  Master selection
-            MSTR: u1,
-            ///  Baud rate control
-            BR: u3,
-            ///  SPI enable
-            SPE: u1,
-            ///  Frame format
-            LSBFIRST: u1,
-            ///  Internal slave select
-            SSI: u1,
-            ///  Software slave management
-            SSM: u1,
-            ///  Receive only
-            RXONLY: u1,
-            ///  Data frame format
-            DFF: u1,
-            ///  CRC transfer next
-            CRCNEXT: u1,
-            ///  Hardware CRC calculation enable
-            CRCEN: u1,
-            ///  Output enable in bidirectional mode
-            BIDIOE: u1,
-            ///  Bidirectional data mode enable
-            BIDIMODE: u1,
-            padding: u16,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Rx buffer DMA enable
-            RXDMAEN: u1,
-            ///  Tx buffer DMA enable
-            TXDMAEN: u1,
-            ///  SS output enable
-            SSOE: u1,
-            reserved4: u1,
-            ///  Frame format
-            FRF: u1,
-            ///  Error interrupt enable
-            ERRIE: u1,
-            ///  RX buffer not empty interrupt enable
-            RXNEIE: u1,
-            ///  Tx buffer empty interrupt enable
-            TXEIE: u1,
-            padding: u24,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Receive buffer not empty
-            RXNE: u1,
-            ///  Transmit buffer empty
-            TXE: u1,
-            ///  Channel side
-            CHSIDE: u1,
-            ///  Underrun flag
-            UDR: u1,
-            ///  CRC error flag
-            CRCERR: u1,
-            ///  Mode fault
-            MODF: u1,
-            ///  Overrun flag
-            OVR: u1,
-            ///  Busy flag
-            BSY: u1,
-            ///  TI frame format error
-            TIFRFE: u1,
-            padding: u23,
-        }),
-        ///  data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data register
-            DR: u16,
-            padding: u16,
-        }),
-        ///  CRC polynomial register
-        CRCPR: mmio.Mmio(packed struct(u32) {
-            ///  CRC polynomial register
-            CRCPOLY: u16,
-            padding: u16,
-        }),
-        ///  RX CRC register
-        RXCRCR: mmio.Mmio(packed struct(u32) {
-            ///  Rx CRC register
-            RxCRC: u16,
-            padding: u16,
-        }),
-        ///  TX CRC register
-        TXCRCR: mmio.Mmio(packed struct(u32) {
-            ///  Tx CRC register
-            TxCRC: u16,
-            padding: u16,
-        }),
-        ///  I2S configuration register
-        I2SCFGR: mmio.Mmio(packed struct(u32) {
-            ///  Channel length (number of bits per audio channel)
-            CHLEN: u1,
-            ///  Data length to be transferred
-            DATLEN: u2,
-            ///  Steady state clock polarity
-            CKPOL: u1,
-            ///  I2S standard selection
-            I2SSTD: u2,
-            reserved7: u1,
-            ///  PCM frame synchronization
-            PCMSYNC: u1,
-            ///  I2S configuration mode
-            I2SCFG: u2,
-            ///  I2S Enable
-            I2SE: u1,
-            ///  I2S mode selection
-            I2SMOD: u1,
-            padding: u20,
-        }),
-        ///  I2S prescaler register
-        I2SPR: mmio.Mmio(packed struct(u32) {
-            ///  I2S Linear prescaler
-            I2SDIV: u8,
-            ///  Odd factor for the prescaler
-            ODD: u1,
-            ///  Master clock output enable
-            MCKOE: u1,
-            padding: u22,
-        }),
-    };
-
-    ///  Inter-integrated circuit
-    pub const I2C3 = extern struct {
-        ///  Control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral enable
-            PE: u1,
-            ///  SMBus mode
-            SMBUS: u1,
-            reserved3: u1,
-            ///  SMBus type
-            SMBTYPE: u1,
-            ///  ARP enable
-            ENARP: u1,
-            ///  PEC enable
-            ENPEC: u1,
-            ///  General call enable
-            ENGC: u1,
-            ///  Clock stretching disable (Slave mode)
-            NOSTRETCH: u1,
-            ///  Start generation
-            START: u1,
-            ///  Stop generation
-            STOP: u1,
-            ///  Acknowledge enable
-            ACK: u1,
-            ///  Acknowledge/PEC Position (for data reception)
-            POS: u1,
-            ///  Packet error checking
-            PEC: u1,
-            ///  SMBus alert
-            ALERT: u1,
-            reserved15: u1,
-            ///  Software reset
-            SWRST: u1,
-            padding: u16,
-        }),
-        ///  Control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Peripheral clock frequency
-            FREQ: u6,
-            reserved8: u2,
-            ///  Error interrupt enable
-            ITERREN: u1,
-            ///  Event interrupt enable
-            ITEVTEN: u1,
-            ///  Buffer interrupt enable
-            ITBUFEN: u1,
-            ///  DMA requests enable
-            DMAEN: u1,
-            ///  DMA last transfer
-            LAST: u1,
-            padding: u19,
-        }),
-        ///  Own address register 1
-        OAR1: mmio.Mmio(packed struct(u32) {
-            ///  Interface address
-            ADD0: u1,
-            ///  Interface address
-            ADD7: u7,
-            ///  Interface address
-            ADD10: u2,
-            reserved15: u5,
-            ///  Addressing mode (slave mode)
-            ADDMODE: u1,
-            padding: u16,
-        }),
-        ///  Own address register 2
-        OAR2: mmio.Mmio(packed struct(u32) {
-            ///  Dual addressing mode enable
-            ENDUAL: u1,
-            ///  Interface address
-            ADD2: u7,
-            padding: u24,
-        }),
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  8-bit data register
-            DR: u8,
-            padding: u24,
-        }),
-        ///  Status register 1
-        SR1: mmio.Mmio(packed struct(u32) {
-            ///  Start bit (Master mode)
-            SB: u1,
-            ///  Address sent (master mode)/matched (slave mode)
-            ADDR: u1,
-            ///  Byte transfer finished
-            BTF: u1,
-            ///  10-bit header sent (Master mode)
-            ADD10: u1,
-            ///  Stop detection (slave mode)
-            STOPF: u1,
-            reserved6: u1,
-            ///  Data register not empty (receivers)
-            RxNE: u1,
-            ///  Data register empty (transmitters)
-            TxE: u1,
-            ///  Bus error
-            BERR: u1,
-            ///  Arbitration lost (master mode)
-            ARLO: u1,
-            ///  Acknowledge failure
-            AF: u1,
-            ///  Overrun/Underrun
-            OVR: u1,
-            ///  PEC Error in reception
-            PECERR: u1,
-            reserved14: u1,
-            ///  Timeout or Tlow error
-            TIMEOUT: u1,
-            ///  SMBus alert
-            SMBALERT: u1,
-            padding: u16,
-        }),
-        ///  Status register 2
-        SR2: mmio.Mmio(packed struct(u32) {
-            ///  Master/slave
-            MSL: u1,
-            ///  Bus busy
-            BUSY: u1,
-            ///  Transmitter/receiver
-            TRA: u1,
-            reserved4: u1,
-            ///  General call address (Slave mode)
-            GENCALL: u1,
-            ///  SMBus device default address (Slave mode)
-            SMBDEFAULT: u1,
-            ///  SMBus host header (Slave mode)
-            SMBHOST: u1,
-            ///  Dual flag (Slave mode)
-            DUALF: u1,
-            ///  acket error checking register
-            PEC: u8,
-            padding: u16,
-        }),
-        ///  Clock control register
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Clock control register in Fast/Standard mode (Master mode)
-            CCR: u12,
-            reserved14: u2,
-            ///  Fast mode duty cycle
-            DUTY: u1,
-            ///  I2C master mode selection
-            F_S: u1,
-            padding: u16,
-        }),
-        ///  TRISE register
-        TRISE: mmio.Mmio(packed struct(u32) {
-            ///  Maximum rise time in Fast/Standard mode (Master mode)
-            TRISE: u6,
-            padding: u26,
-        }),
-        ///  I2C FLTR register
-        FLTR: mmio.Mmio(packed struct(u32) {
-            ///  Digital noise filter
-            DNF: u4,
-            ///  Analog noise filter OFF
-            ANOFF: u1,
-            padding: u27,
-        }),
-    };
-
-    ///  DMA2D controller
-    pub const DMA2D = extern struct {
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Start
-            START: u1,
-            ///  Suspend
-            SUSP: u1,
-            ///  Abort
-            ABORT: u1,
-            reserved8: u5,
-            ///  Transfer error interrupt enable
-            TEIE: u1,
-            ///  Transfer complete interrupt enable
-            TCIE: u1,
-            ///  Transfer watermark interrupt enable
-            TWIE: u1,
-            ///  CLUT access error interrupt enable
-            CAEIE: u1,
-            ///  CLUT transfer complete interrupt enable
-            CTCIE: u1,
-            ///  Configuration Error Interrupt Enable
-            CEIE: u1,
-            reserved16: u2,
-            ///  DMA2D mode
-            MODE: u2,
-            padding: u14,
-        }),
-        ///  Interrupt Status Register
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  Transfer error interrupt flag
-            TEIF: u1,
-            ///  Transfer complete interrupt flag
-            TCIF: u1,
-            ///  Transfer watermark interrupt flag
-            TWIF: u1,
-            ///  CLUT access error interrupt flag
-            CAEIF: u1,
-            ///  CLUT transfer complete interrupt flag
-            CTCIF: u1,
-            ///  Configuration error interrupt flag
-            CEIF: u1,
-            padding: u26,
-        }),
-        ///  interrupt flag clear register
-        IFCR: mmio.Mmio(packed struct(u32) {
-            ///  Clear Transfer error interrupt flag
-            CTEIF: u1,
-            ///  Clear transfer complete interrupt flag
-            CTCIF: u1,
-            ///  Clear transfer watermark interrupt flag
-            CTWIF: u1,
-            ///  Clear CLUT access error interrupt flag
-            CAECIF: u1,
-            ///  Clear CLUT transfer complete interrupt flag
-            CCTCIF: u1,
-            ///  Clear configuration error interrupt flag
-            CCEIF: u1,
-            padding: u26,
-        }),
-        ///  foreground memory address register
-        FGMAR: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        ///  foreground offset register
-        FGOR: mmio.Mmio(packed struct(u32) {
-            ///  Line offset
-            LO: u14,
-            padding: u18,
-        }),
-        ///  background memory address register
-        BGMAR: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        ///  background offset register
-        BGOR: mmio.Mmio(packed struct(u32) {
-            ///  Line offset
-            LO: u14,
-            padding: u18,
-        }),
-        ///  foreground PFC control register
-        FGPFCCR: mmio.Mmio(packed struct(u32) {
-            ///  Color mode
-            CM: u4,
-            ///  CLUT color mode
-            CCM: u1,
-            ///  Start
-            START: u1,
-            reserved8: u2,
-            ///  CLUT size
-            CS: u8,
-            ///  Alpha mode
-            AM: u2,
-            reserved24: u6,
-            ///  Alpha value
-            ALPHA: u8,
-        }),
-        ///  foreground color register
-        FGCOLR: mmio.Mmio(packed struct(u32) {
-            ///  Blue Value
-            BLUE: u8,
-            ///  Green Value
-            GREEN: u8,
-            ///  Red Value
-            RED: u8,
-            padding: u8,
-        }),
-        ///  background PFC control register
-        BGPFCCR: mmio.Mmio(packed struct(u32) {
-            ///  Color mode
-            CM: u4,
-            ///  CLUT Color mode
-            CCM: u1,
-            ///  Start
-            START: u1,
-            reserved8: u2,
-            ///  CLUT size
-            CS: u8,
-            ///  Alpha mode
-            AM: u2,
-            reserved24: u6,
-            ///  Alpha value
-            ALPHA: u8,
-        }),
-        ///  background color register
-        BGCOLR: mmio.Mmio(packed struct(u32) {
-            ///  Blue Value
-            BLUE: u8,
-            ///  Green Value
-            GREEN: u8,
-            ///  Red Value
-            RED: u8,
-            padding: u8,
-        }),
-        ///  foreground CLUT memory address register
-        FGCMAR: mmio.Mmio(packed struct(u32) {
-            ///  Memory Address
-            MA: u32,
-        }),
-        ///  background CLUT memory address register
-        BGCMAR: mmio.Mmio(packed struct(u32) {
-            ///  Memory address
-            MA: u32,
-        }),
-        ///  output PFC control register
-        OPFCCR: mmio.Mmio(packed struct(u32) {
-            ///  Color mode
-            CM: u3,
-            padding: u29,
-        }),
-        ///  output color register
-        OCOLR: mmio.Mmio(packed struct(u32) {
-            ///  Blue Value
-            BLUE: u8,
-            ///  Green Value
-            GREEN: u8,
-            ///  Red Value
-            RED: u8,
-            ///  Alpha Channel Value
-            APLHA: u8,
-        }),
-        ///  output memory address register
-        OMAR: mmio.Mmio(packed struct(u32) {
-            ///  Memory Address
-            MA: u32,
-        }),
-        ///  output offset register
-        OOR: mmio.Mmio(packed struct(u32) {
-            ///  Line Offset
-            LO: u14,
-            padding: u18,
-        }),
-        ///  number of line register
-        NLR: mmio.Mmio(packed struct(u32) {
-            ///  Number of lines
-            NL: u16,
-            ///  Pixel per lines
-            PL: u14,
-            padding: u2,
-        }),
-        ///  line watermark register
-        LWR: mmio.Mmio(packed struct(u32) {
-            ///  Line watermark
-            LW: u16,
-            padding: u16,
-        }),
-        ///  AHB master timer configuration register
-        AMTCR: mmio.Mmio(packed struct(u32) {
-            ///  Enable
-            EN: u1,
-            reserved8: u7,
-            ///  Dead Time
-            DT: u8,
-            padding: u16,
-        }),
-        reserved1024: [944]u8,
-        ///  FGCLUT
-        FGCLUT: mmio.Mmio(packed struct(u32) {
-            ///  BLUE
-            BLUE: u8,
-            ///  GREEN
-            GREEN: u8,
-            ///  RED
-            RED: u8,
-            ///  APLHA
-            APLHA: u8,
-        }),
-        reserved2048: [1020]u8,
-        ///  BGCLUT
-        BGCLUT: mmio.Mmio(packed struct(u32) {
-            ///  BLUE
-            BLUE: u8,
-            ///  GREEN
-            GREEN: u8,
-            ///  RED
-            RED: u8,
-            ///  APLHA
-            APLHA: u8,
-        }),
-    };
-
-    ///  Serial audio interface
-    pub const SAI = extern struct {
-        reserved4: [4]u8,
-        ///  AConfiguration register 1
-        ACR1: mmio.Mmio(packed struct(u32) {
-            ///  Audio block mode
-            MODE: u2,
-            ///  Protocol configuration
-            PRTCFG: u2,
-            reserved5: u1,
-            ///  Data size
-            DS: u3,
-            ///  Least significant bit first
-            LSBFIRST: u1,
-            ///  Clock strobing edge
-            CKSTR: u1,
-            ///  Synchronization enable
-            SYNCEN: u2,
-            ///  Mono mode
-            MONO: u1,
-            ///  Output drive
-            OutDri: u1,
-            reserved16: u2,
-            ///  Audio block A enable
-            SAIAEN: u1,
-            ///  DMA enable
-            DMAEN: u1,
-            reserved19: u1,
-            ///  No divider
-            NODIV: u1,
-            ///  Master clock divider
-            MCJDIV: u4,
-            padding: u8,
-        }),
-        ///  AConfiguration register 2
-        ACR2: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold
-            FTH: u3,
-            ///  FIFO flush
-            FFLUS: u1,
-            ///  Tristate management on data line
-            TRIS: u1,
-            ///  Mute
-            MUTE: u1,
-            ///  Mute value
-            MUTEVAL: u1,
-            ///  Mute counter
-            MUTECN: u6,
-            ///  Complement bit
-            CPL: u1,
-            ///  Companding mode
-            COMP: u2,
-            padding: u16,
-        }),
-        ///  AFRCR
-        AFRCR: mmio.Mmio(packed struct(u32) {
-            ///  Frame length
-            FRL: u8,
-            ///  Frame synchronization active level length
-            FSALL: u7,
-            reserved16: u1,
-            ///  Frame synchronization definition
-            FSDEF: u1,
-            ///  Frame synchronization polarity
-            FSPOL: u1,
-            ///  Frame synchronization offset
-            FSOFF: u1,
-            padding: u13,
-        }),
-        ///  ASlot register
-        ASLOTR: mmio.Mmio(packed struct(u32) {
-            ///  First bit offset
-            FBOFF: u5,
-            reserved6: u1,
-            ///  Slot size
-            SLOTSZ: u2,
-            ///  Number of slots in an audio frame
-            NBSLOT: u4,
-            reserved16: u4,
-            ///  Slot enable
-            SLOTEN: u16,
-        }),
-        ///  AInterrupt mask register2
-        AIM: mmio.Mmio(packed struct(u32) {
-            ///  Overrun/underrun interrupt enable
-            OVRUDRIE: u1,
-            ///  Mute detection interrupt enable
-            MUTEDET: u1,
-            ///  Wrong clock configuration interrupt enable
-            WCKCFG: u1,
-            ///  FIFO request interrupt enable
-            FREQIE: u1,
-            ///  Codec not ready interrupt enable
-            CNRDYIE: u1,
-            ///  Anticipated frame synchronization detection interrupt enable
-            AFSDETIE: u1,
-            ///  Late frame synchronization detection interrupt enable
-            LFSDET: u1,
-            padding: u25,
-        }),
-        ///  AStatus register
-        ASR: mmio.Mmio(packed struct(u32) {
-            ///  Overrun / underrun
-            OVRUDR: u1,
-            ///  Mute detection
-            MUTEDET: u1,
-            ///  Wrong clock configuration flag. This bit is read only.
-            WCKCFG: u1,
-            ///  FIFO request
-            FREQ: u1,
-            ///  Codec not ready
-            CNRDY: u1,
-            ///  Anticipated frame synchronization detection
-            AFSDET: u1,
-            ///  Late frame synchronization detection
-            LFSDET: u1,
-            reserved16: u9,
-            ///  FIFO level threshold
-            FLVL: u3,
-            padding: u13,
-        }),
-        ///  AClear flag register
-        ACLRFR: mmio.Mmio(packed struct(u32) {
-            ///  Clear overrun / underrun
-            OVRUDR: u1,
-            ///  Mute detection flag
-            MUTEDET: u1,
-            ///  Clear wrong clock configuration flag
-            WCKCFG: u1,
-            reserved4: u1,
-            ///  Clear codec not ready flag
-            CNRDY: u1,
-            ///  Clear anticipated frame synchronization detection flag.
-            CAFSDET: u1,
-            ///  Clear late frame synchronization detection flag
-            LFSDET: u1,
-            padding: u25,
-        }),
-        ///  AData register
-        ADR: mmio.Mmio(packed struct(u32) {
-            ///  Data
-            DATA: u32,
-        }),
-        ///  BConfiguration register 1
-        BCR1: mmio.Mmio(packed struct(u32) {
-            ///  Audio block mode
-            MODE: u2,
-            ///  Protocol configuration
-            PRTCFG: u2,
-            reserved5: u1,
-            ///  Data size
-            DS: u3,
-            ///  Least significant bit first
-            LSBFIRST: u1,
-            ///  Clock strobing edge
-            CKSTR: u1,
-            ///  Synchronization enable
-            SYNCEN: u2,
-            ///  Mono mode
-            MONO: u1,
-            ///  Output drive
-            OutDri: u1,
-            reserved16: u2,
-            ///  Audio block B enable
-            SAIBEN: u1,
-            ///  DMA enable
-            DMAEN: u1,
-            reserved19: u1,
-            ///  No divider
-            NODIV: u1,
-            ///  Master clock divider
-            MCJDIV: u4,
-            padding: u8,
-        }),
-        ///  BConfiguration register 2
-        BCR2: mmio.Mmio(packed struct(u32) {
-            ///  FIFO threshold
-            FTH: u3,
-            ///  FIFO flush
-            FFLUS: u1,
-            ///  Tristate management on data line
-            TRIS: u1,
-            ///  Mute
-            MUTE: u1,
-            ///  Mute value
-            MUTEVAL: u1,
-            ///  Mute counter
-            MUTECN: u6,
-            ///  Complement bit
-            CPL: u1,
-            ///  Companding mode
-            COMP: u2,
-            padding: u16,
-        }),
-        ///  BFRCR
-        BFRCR: mmio.Mmio(packed struct(u32) {
-            ///  Frame length
-            FRL: u8,
-            ///  Frame synchronization active level length
-            FSALL: u7,
-            reserved16: u1,
-            ///  Frame synchronization definition
-            FSDEF: u1,
-            ///  Frame synchronization polarity
-            FSPOL: u1,
-            ///  Frame synchronization offset
-            FSOFF: u1,
-            padding: u13,
-        }),
-        ///  BSlot register
-        BSLOTR: mmio.Mmio(packed struct(u32) {
-            ///  First bit offset
-            FBOFF: u5,
-            reserved6: u1,
-            ///  Slot size
-            SLOTSZ: u2,
-            ///  Number of slots in an audio frame
-            NBSLOT: u4,
-            reserved16: u4,
-            ///  Slot enable
-            SLOTEN: u16,
-        }),
-        ///  BInterrupt mask register2
-        BIM: mmio.Mmio(packed struct(u32) {
-            ///  Overrun/underrun interrupt enable
-            OVRUDRIE: u1,
-            ///  Mute detection interrupt enable
-            MUTEDET: u1,
-            ///  Wrong clock configuration interrupt enable
-            WCKCFG: u1,
-            ///  FIFO request interrupt enable
-            FREQIE: u1,
-            ///  Codec not ready interrupt enable
-            CNRDYIE: u1,
-            ///  Anticipated frame synchronization detection interrupt enable
-            AFSDETIE: u1,
-            ///  Late frame synchronization detection interrupt enable
-            LFSDETIE: u1,
-            padding: u25,
-        }),
-        ///  BStatus register
-        BSR: mmio.Mmio(packed struct(u32) {
-            ///  Overrun / underrun
-            OVRUDR: u1,
-            ///  Mute detection
-            MUTEDET: u1,
-            ///  Wrong clock configuration flag
-            WCKCFG: u1,
-            ///  FIFO request
-            FREQ: u1,
-            ///  Codec not ready
-            CNRDY: u1,
-            ///  Anticipated frame synchronization detection
-            AFSDET: u1,
-            ///  Late frame synchronization detection
-            LFSDET: u1,
-            reserved16: u9,
-            ///  FIFO level threshold
-            FLVL: u3,
-            padding: u13,
-        }),
-        ///  BClear flag register
-        BCLRFR: mmio.Mmio(packed struct(u32) {
-            ///  Clear overrun / underrun
-            OVRUDR: u1,
-            ///  Mute detection flag
-            MUTEDET: u1,
-            ///  Clear wrong clock configuration flag
-            WCKCFG: u1,
-            reserved4: u1,
-            ///  Clear codec not ready flag
-            CNRDY: u1,
-            ///  Clear anticipated frame synchronization detection flag
-            CAFSDET: u1,
-            ///  Clear late frame synchronization detection flag
-            LFSDET: u1,
-            padding: u25,
-        }),
-        ///  BData register
-        BDR: mmio.Mmio(packed struct(u32) {
-            ///  Data
-            DATA: u32,
-        }),
-    };
-
-    ///  LCD-TFT Controller
-    pub const LTDC = extern struct {
-        reserved8: [8]u8,
-        ///  Synchronization Size Configuration Register
-        SSCR: mmio.Mmio(packed struct(u32) {
-            ///  Vertical Synchronization Height (in units of horizontal scan line)
-            VSH: u11,
-            reserved16: u5,
-            ///  Horizontal Synchronization Width (in units of pixel clock period)
-            HSW: u10,
-            padding: u6,
-        }),
-        ///  Back Porch Configuration Register
-        BPCR: mmio.Mmio(packed struct(u32) {
-            ///  Accumulated Vertical back porch (in units of horizontal scan line)
-            AVBP: u11,
-            reserved16: u5,
-            ///  Accumulated Horizontal back porch (in units of pixel clock period)
-            AHBP: u10,
-            padding: u6,
-        }),
-        ///  Active Width Configuration Register
-        AWCR: mmio.Mmio(packed struct(u32) {
-            ///  Accumulated Active Height (in units of horizontal scan line)
-            AAH: u11,
-            reserved16: u5,
-            ///  AAV
-            AAV: u10,
-            padding: u6,
-        }),
-        ///  Total Width Configuration Register
-        TWCR: mmio.Mmio(packed struct(u32) {
-            ///  Total Height (in units of horizontal scan line)
-            TOTALH: u11,
-            reserved16: u5,
-            ///  Total Width (in units of pixel clock period)
-            TOTALW: u10,
-            padding: u6,
-        }),
-        ///  Global Control Register
-        GCR: mmio.Mmio(packed struct(u32) {
-            ///  LCD-TFT controller enable bit
-            LTDCEN: u1,
-            reserved4: u3,
-            ///  Dither Blue Width
-            DBW: u3,
-            reserved8: u1,
-            ///  Dither Green Width
-            DGW: u3,
-            reserved12: u1,
-            ///  Dither Red Width
-            DRW: u3,
-            reserved16: u1,
-            ///  Dither Enable
-            DEN: u1,
-            reserved28: u11,
-            ///  Pixel Clock Polarity
-            PCPOL: u1,
-            ///  Data Enable Polarity
-            DEPOL: u1,
-            ///  Vertical Synchronization Polarity
-            VSPOL: u1,
-            ///  Horizontal Synchronization Polarity
-            HSPOL: u1,
-        }),
-        reserved36: [8]u8,
-        ///  Shadow Reload Configuration Register
-        SRCR: mmio.Mmio(packed struct(u32) {
-            ///  Immediate Reload
-            IMR: u1,
-            ///  Vertical Blanking Reload
-            VBR: u1,
-            padding: u30,
-        }),
-        reserved44: [4]u8,
-        ///  Background Color Configuration Register
-        BCCR: mmio.Mmio(packed struct(u32) {
-            ///  Background Color Red value
-            BC: u24,
-            padding: u8,
-        }),
-        reserved52: [4]u8,
-        ///  Interrupt Enable Register
-        IER: mmio.Mmio(packed struct(u32) {
-            ///  Line Interrupt Enable
-            LIE: u1,
-            ///  FIFO Underrun Interrupt Enable
-            FUIE: u1,
-            ///  Transfer Error Interrupt Enable
-            TERRIE: u1,
-            ///  Register Reload interrupt enable
-            RRIE: u1,
-            padding: u28,
-        }),
-        ///  Interrupt Status Register
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  Line Interrupt flag
-            LIF: u1,
-            ///  FIFO Underrun Interrupt flag
-            FUIF: u1,
-            ///  Transfer Error interrupt flag
-            TERRIF: u1,
-            ///  Register Reload Interrupt Flag
-            RRIF: u1,
-            padding: u28,
-        }),
-        ///  Interrupt Clear Register
-        ICR: mmio.Mmio(packed struct(u32) {
-            ///  Clears the Line Interrupt Flag
-            CLIF: u1,
-            ///  Clears the FIFO Underrun Interrupt flag
-            CFUIF: u1,
-            ///  Clears the Transfer Error Interrupt Flag
-            CTERRIF: u1,
-            ///  Clears Register Reload Interrupt Flag
-            CRRIF: u1,
-            padding: u28,
-        }),
-        ///  Line Interrupt Position Configuration Register
-        LIPCR: mmio.Mmio(packed struct(u32) {
-            ///  Line Interrupt Position
-            LIPOS: u11,
-            padding: u21,
-        }),
-        ///  Current Position Status Register
-        CPSR: mmio.Mmio(packed struct(u32) {
-            ///  Current Y Position
-            CYPOS: u16,
-            ///  Current X Position
-            CXPOS: u16,
-        }),
-        ///  Current Display Status Register
-        CDSR: mmio.Mmio(packed struct(u32) {
-            ///  Vertical Data Enable display Status
-            VDES: u1,
-            ///  Horizontal Data Enable display Status
-            HDES: u1,
-            ///  Vertical Synchronization display Status
-            VSYNCS: u1,
-            ///  Horizontal Synchronization display Status
-            HSYNCS: u1,
-            padding: u28,
-        }),
-        reserved132: [56]u8,
-        ///  Layerx Control Register
-        L1CR: mmio.Mmio(packed struct(u32) {
-            ///  Layer Enable
-            LEN: u1,
-            ///  Color Keying Enable
-            COLKEN: u1,
-            reserved4: u2,
-            ///  Color Look-Up Table Enable
-            CLUTEN: u1,
-            padding: u27,
-        }),
-        ///  Layerx Window Horizontal Position Configuration Register
-        L1WHPCR: mmio.Mmio(packed struct(u32) {
-            ///  Window Horizontal Start Position
-            WHSTPOS: u12,
-            reserved16: u4,
-            ///  Window Horizontal Stop Position
-            WHSPPOS: u12,
-            padding: u4,
-        }),
-        ///  Layerx Window Vertical Position Configuration Register
-        L1WVPCR: mmio.Mmio(packed struct(u32) {
-            ///  Window Vertical Start Position
-            WVSTPOS: u11,
-            reserved16: u5,
-            ///  Window Vertical Stop Position
-            WVSPPOS: u11,
-            padding: u5,
-        }),
-        ///  Layerx Color Keying Configuration Register
-        L1CKCR: mmio.Mmio(packed struct(u32) {
-            ///  Color Key Blue value
-            CKBLUE: u8,
-            ///  Color Key Green value
-            CKGREEN: u8,
-            ///  Color Key Red value
-            CKRED: u8,
-            padding: u8,
-        }),
-        ///  Layerx Pixel Format Configuration Register
-        L1PFCR: mmio.Mmio(packed struct(u32) {
-            ///  Pixel Format
-            PF: u3,
-            padding: u29,
-        }),
-        ///  Layerx Constant Alpha Configuration Register
-        L1CACR: mmio.Mmio(packed struct(u32) {
-            ///  Constant Alpha
-            CONSTA: u8,
-            padding: u24,
-        }),
-        ///  Layerx Default Color Configuration Register
-        L1DCCR: mmio.Mmio(packed struct(u32) {
-            ///  Default Color Blue
-            DCBLUE: u8,
-            ///  Default Color Green
-            DCGREEN: u8,
-            ///  Default Color Red
-            DCRED: u8,
-            ///  Default Color Alpha
-            DCALPHA: u8,
-        }),
-        ///  Layerx Blending Factors Configuration Register
-        L1BFCR: mmio.Mmio(packed struct(u32) {
-            ///  Blending Factor 2
-            BF2: u3,
-            reserved8: u5,
-            ///  Blending Factor 1
-            BF1: u3,
-            padding: u21,
-        }),
-        reserved172: [8]u8,
-        ///  Layerx Color Frame Buffer Address Register
-        L1CFBAR: mmio.Mmio(packed struct(u32) {
-            ///  Color Frame Buffer Start Address
-            CFBADD: u32,
-        }),
-        ///  Layerx Color Frame Buffer Length Register
-        L1CFBLR: mmio.Mmio(packed struct(u32) {
-            ///  Color Frame Buffer Line Length
-            CFBLL: u13,
-            reserved16: u3,
-            ///  Color Frame Buffer Pitch in bytes
-            CFBP: u13,
-            padding: u3,
-        }),
-        ///  Layerx ColorFrame Buffer Line Number Register
-        L1CFBLNR: mmio.Mmio(packed struct(u32) {
-            ///  Frame Buffer Line Number
-            CFBLNBR: u11,
-            padding: u21,
-        }),
-        reserved196: [12]u8,
-        ///  Layerx CLUT Write Register
-        L1CLUTWR: mmio.Mmio(packed struct(u32) {
-            ///  Blue value
-            BLUE: u8,
-            ///  Green value
-            GREEN: u8,
-            ///  Red value
-            RED: u8,
-            ///  CLUT Address
-            CLUTADD: u8,
-        }),
-        reserved260: [60]u8,
-        ///  Layerx Control Register
-        L2CR: mmio.Mmio(packed struct(u32) {
-            ///  Layer Enable
-            LEN: u1,
-            ///  Color Keying Enable
-            COLKEN: u1,
-            reserved4: u2,
-            ///  Color Look-Up Table Enable
-            CLUTEN: u1,
-            padding: u27,
-        }),
-        ///  Layerx Window Horizontal Position Configuration Register
-        L2WHPCR: mmio.Mmio(packed struct(u32) {
-            ///  Window Horizontal Start Position
-            WHSTPOS: u12,
-            reserved16: u4,
-            ///  Window Horizontal Stop Position
-            WHSPPOS: u12,
-            padding: u4,
-        }),
-        ///  Layerx Window Vertical Position Configuration Register
-        L2WVPCR: mmio.Mmio(packed struct(u32) {
-            ///  Window Vertical Start Position
-            WVSTPOS: u11,
-            reserved16: u5,
-            ///  Window Vertical Stop Position
-            WVSPPOS: u11,
-            padding: u5,
-        }),
-        ///  Layerx Color Keying Configuration Register
-        L2CKCR: mmio.Mmio(packed struct(u32) {
-            ///  Color Key Blue value
-            CKBLUE: u8,
-            ///  Color Key Green value
-            CKGREEN: u7,
-            ///  Color Key Red value
-            CKRED: u9,
-            padding: u8,
-        }),
-        ///  Layerx Pixel Format Configuration Register
-        L2PFCR: mmio.Mmio(packed struct(u32) {
-            ///  Pixel Format
-            PF: u3,
-            padding: u29,
-        }),
-        ///  Layerx Constant Alpha Configuration Register
-        L2CACR: mmio.Mmio(packed struct(u32) {
-            ///  Constant Alpha
-            CONSTA: u8,
-            padding: u24,
-        }),
-        ///  Layerx Default Color Configuration Register
-        L2DCCR: mmio.Mmio(packed struct(u32) {
-            ///  Default Color Blue
-            DCBLUE: u8,
-            ///  Default Color Green
-            DCGREEN: u8,
-            ///  Default Color Red
-            DCRED: u8,
-            ///  Default Color Alpha
-            DCALPHA: u8,
-        }),
-        ///  Layerx Blending Factors Configuration Register
-        L2BFCR: mmio.Mmio(packed struct(u32) {
-            ///  Blending Factor 2
-            BF2: u3,
-            reserved8: u5,
-            ///  Blending Factor 1
-            BF1: u3,
-            padding: u21,
-        }),
-        reserved300: [8]u8,
-        ///  Layerx Color Frame Buffer Address Register
-        L2CFBAR: mmio.Mmio(packed struct(u32) {
-            ///  Color Frame Buffer Start Address
-            CFBADD: u32,
-        }),
-        ///  Layerx Color Frame Buffer Length Register
-        L2CFBLR: mmio.Mmio(packed struct(u32) {
-            ///  Color Frame Buffer Line Length
-            CFBLL: u13,
-            reserved16: u3,
-            ///  Color Frame Buffer Pitch in bytes
-            CFBP: u13,
-            padding: u3,
-        }),
-        ///  Layerx ColorFrame Buffer Line Number Register
-        L2CFBLNR: mmio.Mmio(packed struct(u32) {
-            ///  Frame Buffer Line Number
-            CFBLNBR: u11,
-            padding: u21,
-        }),
-        reserved324: [12]u8,
-        ///  Layerx CLUT Write Register
-        L2CLUTWR: mmio.Mmio(packed struct(u32) {
-            ///  Blue value
-            BLUE: u8,
-            ///  Green value
-            GREEN: u8,
-            ///  Red value
-            RED: u8,
-            ///  CLUT Address
-            CLUTADD: u8,
-        }),
-    };
-
-    ///  USB on the go high speed
-    pub const OTG_HS_PWRCLK = extern struct {
-        ///  Power and clock gating control register
-        OTG_HS_PCGCR: mmio.Mmio(packed struct(u32) {
-            ///  Stop PHY clock
-            STPPCLK: u1,
-            ///  Gate HCLK
-            GATEHCLK: u1,
-            reserved4: u2,
-            ///  PHY suspended
-            PHYSUSP: u1,
-            padding: u27,
-        }),
-    };
-
-    ///  USB on the go high speed
-    pub const OTG_HS_DEVICE = extern struct {
-        ///  OTG_HS device configuration register
-        OTG_HS_DCFG: mmio.Mmio(packed struct(u32) {
-            ///  Device speed
-            DSPD: u2,
-            ///  Nonzero-length status OUT handshake
-            NZLSOHSK: u1,
-            reserved4: u1,
-            ///  Device address
-            DAD: u7,
-            ///  Periodic (micro)frame interval
-            PFIVL: u2,
-            reserved24: u11,
-            ///  Periodic scheduling interval
-            PERSCHIVL: u2,
-            padding: u6,
-        }),
-        ///  OTG_HS device control register
-        OTG_HS_DCTL: mmio.Mmio(packed struct(u32) {
-            ///  Remote wakeup signaling
-            RWUSIG: u1,
-            ///  Soft disconnect
-            SDIS: u1,
-            ///  Global IN NAK status
-            GINSTS: u1,
-            ///  Global OUT NAK status
-            GONSTS: u1,
-            ///  Test control
-            TCTL: u3,
-            ///  Set global IN NAK
-            SGINAK: u1,
-            ///  Clear global IN NAK
-            CGINAK: u1,
-            ///  Set global OUT NAK
-            SGONAK: u1,
-            ///  Clear global OUT NAK
-            CGONAK: u1,
-            ///  Power-on programming done
-            POPRGDNE: u1,
-            padding: u20,
-        }),
-        ///  OTG_HS device status register
-        OTG_HS_DSTS: mmio.Mmio(packed struct(u32) {
-            ///  Suspend status
-            SUSPSTS: u1,
-            ///  Enumerated speed
-            ENUMSPD: u2,
-            ///  Erratic error
-            EERR: u1,
-            reserved8: u4,
-            ///  Frame number of the received SOF
-            FNSOF: u14,
-            padding: u10,
-        }),
-        reserved16: [4]u8,
-        ///  OTG_HS device IN endpoint common interrupt mask register
-        OTG_HS_DIEPMSK: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  Timeout condition mask (nonisochronous endpoints)
-            TOM: u1,
-            ///  IN token received when TxFIFO empty mask
-            ITTXFEMSK: u1,
-            ///  IN token received with EP mismatch mask
-            INEPNMM: u1,
-            ///  IN endpoint NAK effective mask
-            INEPNEM: u1,
-            reserved8: u1,
-            ///  FIFO underrun mask
-            TXFURM: u1,
-            ///  BNA interrupt mask
-            BIM: u1,
-            padding: u22,
-        }),
-        ///  OTG_HS device OUT endpoint common interrupt mask register
-        OTG_HS_DOEPMSK: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  SETUP phase done mask
-            STUPM: u1,
-            ///  OUT token received when endpoint disabled mask
-            OTEPDM: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received mask
-            B2BSTUP: u1,
-            reserved8: u1,
-            ///  OUT packet error mask
-            OPEM: u1,
-            ///  BNA interrupt mask
-            BOIM: u1,
-            padding: u22,
-        }),
-        ///  OTG_HS device all endpoints interrupt register
-        OTG_HS_DAINT: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint interrupt bits
-            IEPINT: u16,
-            ///  OUT endpoint interrupt bits
-            OEPINT: u16,
-        }),
-        ///  OTG_HS all endpoints interrupt mask register
-        OTG_HS_DAINTMSK: mmio.Mmio(packed struct(u32) {
-            ///  IN EP interrupt mask bits
-            IEPM: u16,
-            ///  OUT EP interrupt mask bits
-            OEPM: u16,
-        }),
-        reserved40: [8]u8,
-        ///  OTG_HS device VBUS discharge time register
-        OTG_HS_DVBUSDIS: mmio.Mmio(packed struct(u32) {
-            ///  Device VBUS discharge time
-            VBUSDT: u16,
-            padding: u16,
-        }),
-        ///  OTG_HS device VBUS pulsing time register
-        OTG_HS_DVBUSPULSE: mmio.Mmio(packed struct(u32) {
-            ///  Device VBUS pulsing time
-            DVBUSP: u12,
-            padding: u20,
-        }),
-        ///  OTG_HS Device threshold control register
-        OTG_HS_DTHRCTL: mmio.Mmio(packed struct(u32) {
-            ///  Nonisochronous IN endpoints threshold enable
-            NONISOTHREN: u1,
-            ///  ISO IN endpoint threshold enable
-            ISOTHREN: u1,
-            ///  Transmit threshold length
-            TXTHRLEN: u9,
-            reserved16: u5,
-            ///  Receive threshold enable
-            RXTHREN: u1,
-            ///  Receive threshold length
-            RXTHRLEN: u9,
-            reserved27: u1,
-            ///  Arbiter parking enable
-            ARPEN: u1,
-            padding: u4,
-        }),
-        ///  OTG_HS device IN endpoint FIFO empty interrupt mask register
-        OTG_HS_DIEPEMPMSK: mmio.Mmio(packed struct(u32) {
-            ///  IN EP Tx FIFO empty interrupt mask bits
-            INEPTXFEM: u16,
-            padding: u16,
-        }),
-        ///  OTG_HS device each endpoint interrupt register
-        OTG_HS_DEACHINT: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  IN endpoint 1interrupt bit
-            IEP1INT: u1,
-            reserved17: u15,
-            ///  OUT endpoint 1 interrupt bit
-            OEP1INT: u1,
-            padding: u14,
-        }),
-        ///  OTG_HS device each endpoint interrupt register mask
-        OTG_HS_DEACHINTMSK: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  IN Endpoint 1 interrupt mask bit
-            IEP1INTM: u1,
-            reserved17: u15,
-            ///  OUT Endpoint 1 interrupt mask bit
-            OEP1INTM: u1,
-            padding: u14,
-        }),
-        ///  OTG_HS device each in endpoint-1 interrupt register
-        OTG_HS_DIEPEACHMSK1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  Timeout condition mask (nonisochronous endpoints)
-            TOM: u1,
-            ///  IN token received when TxFIFO empty mask
-            ITTXFEMSK: u1,
-            ///  IN token received with EP mismatch mask
-            INEPNMM: u1,
-            ///  IN endpoint NAK effective mask
-            INEPNEM: u1,
-            reserved8: u1,
-            ///  FIFO underrun mask
-            TXFURM: u1,
-            ///  BNA interrupt mask
-            BIM: u1,
-            reserved13: u3,
-            ///  NAK interrupt mask
-            NAKM: u1,
-            padding: u18,
-        }),
-        reserved128: [60]u8,
-        ///  OTG_HS device each OUT endpoint-1 interrupt register
-        OTG_HS_DOEPEACHMSK1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  Timeout condition mask
-            TOM: u1,
-            ///  IN token received when TxFIFO empty mask
-            ITTXFEMSK: u1,
-            ///  IN token received with EP mismatch mask
-            INEPNMM: u1,
-            ///  IN endpoint NAK effective mask
-            INEPNEM: u1,
-            reserved8: u1,
-            ///  OUT packet error mask
-            TXFURM: u1,
-            ///  BNA interrupt mask
-            BIM: u1,
-            reserved12: u2,
-            ///  Bubble error interrupt mask
-            BERRM: u1,
-            ///  NAK interrupt mask
-            NAKM: u1,
-            ///  NYET interrupt mask
-            NYETM: u1,
-            padding: u17,
-        }),
-        reserved256: [124]u8,
-        ///  OTG device endpoint-0 control register
-        OTG_HS_DIEPCTL0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved264: [4]u8,
-        ///  OTG device endpoint-0 interrupt register
-        OTG_HS_DIEPINT0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved272: [4]u8,
-        ///  OTG_HS device IN endpoint 0 transfer size register
-        OTG_HS_DIEPTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u7,
-            reserved19: u12,
-            ///  Packet count
-            PKTCNT: u2,
-            padding: u11,
-        }),
-        ///  OTG_HS device endpoint-1 DMA address register
-        OTG_HS_DIEPDMA1: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS0: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved288: [4]u8,
-        ///  OTG device endpoint-1 control register
-        OTG_HS_DIEPCTL1: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved296: [4]u8,
-        ///  OTG device endpoint-1 interrupt register
-        OTG_HS_DIEPINT1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved304: [4]u8,
-        ///  OTG_HS device endpoint transfer size register
-        OTG_HS_DIEPTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS device endpoint-2 DMA address register
-        OTG_HS_DIEPDMA2: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS1: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved320: [4]u8,
-        ///  OTG device endpoint-2 control register
-        OTG_HS_DIEPCTL2: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved328: [4]u8,
-        ///  OTG device endpoint-2 interrupt register
-        OTG_HS_DIEPINT2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved336: [4]u8,
-        ///  OTG_HS device endpoint transfer size register
-        OTG_HS_DIEPTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS device endpoint-3 DMA address register
-        OTG_HS_DIEPDMA3: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS2: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved352: [4]u8,
-        ///  OTG device endpoint-3 control register
-        OTG_HS_DIEPCTL3: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved360: [4]u8,
-        ///  OTG device endpoint-3 interrupt register
-        OTG_HS_DIEPINT3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved368: [4]u8,
-        ///  OTG_HS device endpoint transfer size register
-        OTG_HS_DIEPTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS device endpoint-4 DMA address register
-        OTG_HS_DIEPDMA4: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS3: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved384: [4]u8,
-        ///  OTG device endpoint-4 control register
-        OTG_HS_DIEPCTL4: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved392: [4]u8,
-        ///  OTG device endpoint-4 interrupt register
-        OTG_HS_DIEPINT4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved400: [4]u8,
-        ///  OTG_HS device endpoint transfer size register
-        OTG_HS_DIEPTSIZ4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS device endpoint-5 DMA address register
-        OTG_HS_DIEPDMA5: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS4: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved416: [4]u8,
-        ///  OTG device endpoint-5 control register
-        OTG_HS_DIEPCTL5: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved424: [4]u8,
-        ///  OTG device endpoint-5 interrupt register
-        OTG_HS_DIEPINT5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved432: [4]u8,
-        ///  OTG_HS device endpoint transfer size register
-        OTG_HS_DIEPTSIZ5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        reserved440: [4]u8,
-        ///  OTG_HS device IN endpoint transmit FIFO status register
-        OTG_HS_DTXFSTS5: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space avail
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved448: [4]u8,
-        ///  OTG device endpoint-6 control register
-        OTG_HS_DIEPCTL6: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved456: [4]u8,
-        ///  OTG device endpoint-6 interrupt register
-        OTG_HS_DIEPINT6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved480: [20]u8,
-        ///  OTG device endpoint-7 control register
-        OTG_HS_DIEPCTL7: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even/odd frame
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            Stall: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved488: [4]u8,
-        ///  OTG device endpoint-7 interrupt register
-        OTG_HS_DIEPINT7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  Timeout condition
-            TOC: u1,
-            ///  IN token received when TxFIFO is empty
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  IN endpoint NAK effective
-            INEPNE: u1,
-            ///  Transmit FIFO empty
-            TXFE: u1,
-            ///  Transmit Fifo Underrun
-            TXFIFOUDRN: u1,
-            ///  Buffer not available interrupt
-            BNA: u1,
-            reserved11: u1,
-            ///  Packet dropped status
-            PKTDRPSTS: u1,
-            ///  Babble error interrupt
-            BERR: u1,
-            ///  NAK interrupt
-            NAK: u1,
-            padding: u18,
-        }),
-        reserved768: [276]u8,
-        ///  OTG_HS device control OUT endpoint 0 control register
-        OTG_HS_DOEPCTL0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u2,
-            reserved15: u13,
-            ///  USB active endpoint
-            USBAEP: u1,
-            reserved17: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Snoop mode
-            SNPM: u1,
-            ///  STALL handshake
-            Stall: u1,
-            reserved26: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            reserved30: u2,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved776: [4]u8,
-        ///  OTG_HS device endpoint-0 interrupt register
-        OTG_HS_DOEPINT0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved784: [4]u8,
-        ///  OTG_HS device endpoint-1 transfer size register
-        OTG_HS_DOEPTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u7,
-            reserved19: u12,
-            ///  Packet count
-            PKTCNT: u1,
-            reserved29: u9,
-            ///  SETUP packet count
-            STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved800: [12]u8,
-        ///  OTG device endpoint-1 control register
-        OTG_HS_DOEPCTL1: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even odd frame/Endpoint data PID
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Snoop mode
-            SNPM: u1,
-            ///  STALL handshake
-            Stall: u1,
-            reserved26: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID/Set even frame
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved808: [4]u8,
-        ///  OTG_HS device endpoint-1 interrupt register
-        OTG_HS_DOEPINT1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved816: [4]u8,
-        ///  OTG_HS device endpoint-2 transfer size register
-        OTG_HS_DOEPTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved832: [12]u8,
-        ///  OTG device endpoint-2 control register
-        OTG_HS_DOEPCTL2: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even odd frame/Endpoint data PID
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Snoop mode
-            SNPM: u1,
-            ///  STALL handshake
-            Stall: u1,
-            reserved26: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID/Set even frame
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved840: [4]u8,
-        ///  OTG_HS device endpoint-2 interrupt register
-        OTG_HS_DOEPINT2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved848: [4]u8,
-        ///  OTG_HS device endpoint-3 transfer size register
-        OTG_HS_DOEPTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved864: [12]u8,
-        ///  OTG device endpoint-3 control register
-        OTG_HS_DOEPCTL3: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USB active endpoint
-            USBAEP: u1,
-            ///  Even odd frame/Endpoint data PID
-            EONUM_DPID: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Snoop mode
-            SNPM: u1,
-            ///  STALL handshake
-            Stall: u1,
-            reserved26: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            ///  Set DATA0 PID/Set even frame
-            SD0PID_SEVNFRM: u1,
-            ///  Set odd frame
-            SODDFRM: u1,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved872: [4]u8,
-        ///  OTG_HS device endpoint-3 interrupt register
-        OTG_HS_DOEPINT3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved880: [4]u8,
-        ///  OTG_HS device endpoint-4 transfer size register
-        OTG_HS_DOEPTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved904: [20]u8,
-        ///  OTG_HS device endpoint-4 interrupt register
-        OTG_HS_DOEPINT4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved912: [4]u8,
-        ///  OTG_HS device endpoint-5 transfer size register
-        OTG_HS_DOEPTSIZ4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved936: [20]u8,
-        ///  OTG_HS device endpoint-5 interrupt register
-        OTG_HS_DOEPINT5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved968: [28]u8,
-        ///  OTG_HS device endpoint-6 interrupt register
-        OTG_HS_DOEPINT6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-        reserved1000: [28]u8,
-        ///  OTG_HS device endpoint-7 interrupt register
-        OTG_HS_DOEPINT7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt
-            XFRC: u1,
-            ///  Endpoint disabled interrupt
-            EPDISD: u1,
-            reserved3: u1,
-            ///  SETUP phase done
-            STUP: u1,
-            ///  OUT token received when endpoint disabled
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  Back-to-back SETUP packets received
-            B2BSTUP: u1,
-            reserved14: u7,
-            ///  NYET interrupt
-            NYET: u1,
-            padding: u17,
-        }),
-    };
-
-    ///  USB on the go high speed
-    pub const OTG_HS_HOST = extern struct {
-        ///  OTG_HS host configuration register
-        OTG_HS_HCFG: mmio.Mmio(packed struct(u32) {
-            ///  FS/LS PHY clock select
-            FSLSPCS: u2,
-            ///  FS- and LS-only support
-            FSLSS: u1,
-            padding: u29,
-        }),
-        ///  OTG_HS Host frame interval register
-        OTG_HS_HFIR: mmio.Mmio(packed struct(u32) {
-            ///  Frame interval
-            FRIVL: u16,
-            padding: u16,
-        }),
-        ///  OTG_HS host frame number/frame time remaining register
-        OTG_HS_HFNUM: mmio.Mmio(packed struct(u32) {
-            ///  Frame number
-            FRNUM: u16,
-            ///  Frame time remaining
-            FTREM: u16,
-        }),
-        reserved16: [4]u8,
-        ///  OTG_HS_Host periodic transmit FIFO/queue status register
-        OTG_HS_HPTXSTS: mmio.Mmio(packed struct(u32) {
-            ///  Periodic transmit data FIFO space available
-            PTXFSAVL: u16,
-            ///  Periodic transmit request queue space available
-            PTXQSAV: u8,
-            ///  Top of the periodic transmit request queue
-            PTXQTOP: u8,
-        }),
-        ///  OTG_HS Host all channels interrupt register
-        OTG_HS_HAINT: mmio.Mmio(packed struct(u32) {
-            ///  Channel interrupts
-            HAINT: u16,
-            padding: u16,
-        }),
-        ///  OTG_HS host all channels interrupt mask register
-        OTG_HS_HAINTMSK: mmio.Mmio(packed struct(u32) {
-            ///  Channel interrupt mask
-            HAINTM: u16,
-            padding: u16,
-        }),
-        reserved64: [36]u8,
-        ///  OTG_HS host port control and status register
-        OTG_HS_HPRT: mmio.Mmio(packed struct(u32) {
-            ///  Port connect status
-            PCSTS: u1,
-            ///  Port connect detected
-            PCDET: u1,
-            ///  Port enable
-            PENA: u1,
-            ///  Port enable/disable change
-            PENCHNG: u1,
-            ///  Port overcurrent active
-            POCA: u1,
-            ///  Port overcurrent change
-            POCCHNG: u1,
-            ///  Port resume
-            PRES: u1,
-            ///  Port suspend
-            PSUSP: u1,
-            ///  Port reset
-            PRST: u1,
-            reserved10: u1,
-            ///  Port line status
-            PLSTS: u2,
-            ///  Port power
-            PPWR: u1,
-            ///  Port test control
-            PTCTL: u4,
-            ///  Port speed
-            PSPD: u2,
-            padding: u13,
-        }),
-        reserved256: [188]u8,
-        ///  OTG_HS host channel-0 characteristics register
-        OTG_HS_HCCHAR0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-0 split control register
-        OTG_HS_HCSPLT0: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-11 interrupt register
-        OTG_HS_HCINT0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-11 interrupt mask register
-        OTG_HS_HCINTMSK0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-11 transfer size register
-        OTG_HS_HCTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-0 DMA address register
-        OTG_HS_HCDMA0: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved288: [8]u8,
-        ///  OTG_HS host channel-1 characteristics register
-        OTG_HS_HCCHAR1: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-1 split control register
-        OTG_HS_HCSPLT1: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-1 interrupt register
-        OTG_HS_HCINT1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-1 interrupt mask register
-        OTG_HS_HCINTMSK1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-1 transfer size register
-        OTG_HS_HCTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-1 DMA address register
-        OTG_HS_HCDMA1: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved320: [8]u8,
-        ///  OTG_HS host channel-2 characteristics register
-        OTG_HS_HCCHAR2: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-2 split control register
-        OTG_HS_HCSPLT2: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-2 interrupt register
-        OTG_HS_HCINT2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-2 interrupt mask register
-        OTG_HS_HCINTMSK2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-2 transfer size register
-        OTG_HS_HCTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-2 DMA address register
-        OTG_HS_HCDMA2: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved352: [8]u8,
-        ///  OTG_HS host channel-3 characteristics register
-        OTG_HS_HCCHAR3: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-3 split control register
-        OTG_HS_HCSPLT3: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-3 interrupt register
-        OTG_HS_HCINT3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-3 interrupt mask register
-        OTG_HS_HCINTMSK3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-3 transfer size register
-        OTG_HS_HCTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-3 DMA address register
-        OTG_HS_HCDMA3: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved384: [8]u8,
-        ///  OTG_HS host channel-4 characteristics register
-        OTG_HS_HCCHAR4: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-4 split control register
-        OTG_HS_HCSPLT4: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-4 interrupt register
-        OTG_HS_HCINT4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-4 interrupt mask register
-        OTG_HS_HCINTMSK4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-4 transfer size register
-        OTG_HS_HCTSIZ4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-4 DMA address register
-        OTG_HS_HCDMA4: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved416: [8]u8,
-        ///  OTG_HS host channel-5 characteristics register
-        OTG_HS_HCCHAR5: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-5 split control register
-        OTG_HS_HCSPLT5: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-5 interrupt register
-        OTG_HS_HCINT5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-5 interrupt mask register
-        OTG_HS_HCINTMSK5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-5 transfer size register
-        OTG_HS_HCTSIZ5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-5 DMA address register
-        OTG_HS_HCDMA5: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved448: [8]u8,
-        ///  OTG_HS host channel-6 characteristics register
-        OTG_HS_HCCHAR6: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-6 split control register
-        OTG_HS_HCSPLT6: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-6 interrupt register
-        OTG_HS_HCINT6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-6 interrupt mask register
-        OTG_HS_HCINTMSK6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-6 transfer size register
-        OTG_HS_HCTSIZ6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-6 DMA address register
-        OTG_HS_HCDMA6: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved480: [8]u8,
-        ///  OTG_HS host channel-7 characteristics register
-        OTG_HS_HCCHAR7: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-7 split control register
-        OTG_HS_HCSPLT7: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-7 interrupt register
-        OTG_HS_HCINT7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-7 interrupt mask register
-        OTG_HS_HCINTMSK7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-7 transfer size register
-        OTG_HS_HCTSIZ7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-7 DMA address register
-        OTG_HS_HCDMA7: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved512: [8]u8,
-        ///  OTG_HS host channel-8 characteristics register
-        OTG_HS_HCCHAR8: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-8 split control register
-        OTG_HS_HCSPLT8: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-8 interrupt register
-        OTG_HS_HCINT8: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-8 interrupt mask register
-        OTG_HS_HCINTMSK8: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-8 transfer size register
-        OTG_HS_HCTSIZ8: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-8 DMA address register
-        OTG_HS_HCDMA8: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved544: [8]u8,
-        ///  OTG_HS host channel-9 characteristics register
-        OTG_HS_HCCHAR9: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-9 split control register
-        OTG_HS_HCSPLT9: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-9 interrupt register
-        OTG_HS_HCINT9: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-9 interrupt mask register
-        OTG_HS_HCINTMSK9: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-9 transfer size register
-        OTG_HS_HCTSIZ9: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-9 DMA address register
-        OTG_HS_HCDMA9: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved576: [8]u8,
-        ///  OTG_HS host channel-10 characteristics register
-        OTG_HS_HCCHAR10: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-10 split control register
-        OTG_HS_HCSPLT10: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-10 interrupt register
-        OTG_HS_HCINT10: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-10 interrupt mask register
-        OTG_HS_HCINTMSK10: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-10 transfer size register
-        OTG_HS_HCTSIZ10: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-10 DMA address register
-        OTG_HS_HCDMA10: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-        reserved608: [8]u8,
-        ///  OTG_HS host channel-11 characteristics register
-        OTG_HS_HCCHAR11: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multi Count (MC) / Error Count (EC)
-            MC: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        ///  OTG_HS host channel-11 split control register
-        OTG_HS_HCSPLT11: mmio.Mmio(packed struct(u32) {
-            ///  Port address
-            PRTADDR: u7,
-            ///  Hub address
-            HUBADDR: u7,
-            ///  XACTPOS
-            XACTPOS: u2,
-            ///  Do complete split
-            COMPLSPLT: u1,
-            reserved31: u14,
-            ///  Split enable
-            SPLITEN: u1,
-        }),
-        ///  OTG_HS host channel-11 interrupt register
-        OTG_HS_HCINT11: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            ///  Response received interrupt
-            NYET: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-11 interrupt mask register
-        OTG_HS_HCINTMSK11: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            ///  AHB error
-            AHBERR: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_HS host channel-11 transfer size register
-        OTG_HS_HCTSIZ11: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        ///  OTG_HS host channel-11 DMA address register
-        OTG_HS_HCDMA11: mmio.Mmio(packed struct(u32) {
-            ///  DMA address
-            DMAADDR: u32,
-        }),
-    };
-
-    ///  Secure digital input/output interface
-    pub const SDIO = extern struct {
-        ///  power control register
-        POWER: mmio.Mmio(packed struct(u32) {
-            ///  PWRCTRL
-            PWRCTRL: u2,
-            padding: u30,
-        }),
-        ///  SDI clock control register
-        CLKCR: mmio.Mmio(packed struct(u32) {
-            ///  Clock divide factor
-            CLKDIV: u8,
-            ///  Clock enable bit
-            CLKEN: u1,
-            ///  Power saving configuration bit
-            PWRSAV: u1,
-            ///  Clock divider bypass enable bit
-            BYPASS: u1,
-            ///  Wide bus mode enable bit
-            WIDBUS: u2,
-            ///  SDIO_CK dephasing selection bit
-            NEGEDGE: u1,
-            ///  HW Flow Control enable
-            HWFC_EN: u1,
-            padding: u17,
-        }),
-        ///  argument register
-        ARG: mmio.Mmio(packed struct(u32) {
-            ///  Command argument
-            CMDARG: u32,
-        }),
-        ///  command register
-        CMD: mmio.Mmio(packed struct(u32) {
-            ///  Command index
-            CMDINDEX: u6,
-            ///  Wait for response bits
-            WAITRESP: u2,
-            ///  CPSM waits for interrupt request
-            WAITINT: u1,
-            ///  CPSM Waits for ends of data transfer (CmdPend internal signal).
-            WAITPEND: u1,
-            ///  Command path state machine (CPSM) Enable bit
-            CPSMEN: u1,
-            ///  SD I/O suspend command
-            SDIOSuspend: u1,
-            ///  Enable CMD completion
-            ENCMDcompl: u1,
-            ///  not Interrupt Enable
-            nIEN: u1,
-            ///  CE-ATA command
-            CE_ATACMD: u1,
-            padding: u17,
-        }),
-        ///  command response register
-        RESPCMD: mmio.Mmio(packed struct(u32) {
-            ///  Response command index
-            RESPCMD: u6,
-            padding: u26,
-        }),
-        ///  response 1..4 register
-        RESP1: mmio.Mmio(packed struct(u32) {
-            ///  see Table 132.
-            CARDSTATUS1: u32,
-        }),
-        ///  response 1..4 register
-        RESP2: mmio.Mmio(packed struct(u32) {
-            ///  see Table 132.
-            CARDSTATUS2: u32,
-        }),
-        ///  response 1..4 register
-        RESP3: mmio.Mmio(packed struct(u32) {
-            ///  see Table 132.
-            CARDSTATUS3: u32,
-        }),
-        ///  response 1..4 register
-        RESP4: mmio.Mmio(packed struct(u32) {
-            ///  see Table 132.
-            CARDSTATUS4: u32,
-        }),
-        ///  data timer register
-        DTIMER: mmio.Mmio(packed struct(u32) {
-            ///  Data timeout period
-            DATATIME: u32,
-        }),
-        ///  data length register
-        DLEN: mmio.Mmio(packed struct(u32) {
-            ///  Data length value
-            DATALENGTH: u25,
-            padding: u7,
-        }),
-        ///  data control register
-        DCTRL: mmio.Mmio(packed struct(u32) {
-            ///  DTEN
-            DTEN: u1,
-            ///  Data transfer direction selection
-            DTDIR: u1,
-            ///  Data transfer mode selection 1: Stream or SDIO multibyte data transfer.
-            DTMODE: u1,
-            ///  DMA enable bit
-            DMAEN: u1,
-            ///  Data block size
-            DBLOCKSIZE: u4,
-            ///  Read wait start
-            RWSTART: u1,
-            ///  Read wait stop
-            RWSTOP: u1,
-            ///  Read wait mode
-            RWMOD: u1,
-            ///  SD I/O enable functions
-            SDIOEN: u1,
-            padding: u20,
-        }),
-        ///  data counter register
-        DCOUNT: mmio.Mmio(packed struct(u32) {
-            ///  Data count value
-            DATACOUNT: u25,
-            padding: u7,
-        }),
-        ///  status register
-        STA: mmio.Mmio(packed struct(u32) {
-            ///  Command response received (CRC check failed)
-            CCRCFAIL: u1,
-            ///  Data block sent/received (CRC check failed)
-            DCRCFAIL: u1,
-            ///  Command response timeout
-            CTIMEOUT: u1,
-            ///  Data timeout
-            DTIMEOUT: u1,
-            ///  Transmit FIFO underrun error
-            TXUNDERR: u1,
-            ///  Received FIFO overrun error
-            RXOVERR: u1,
-            ///  Command response received (CRC check passed)
-            CMDREND: u1,
-            ///  Command sent (no response required)
-            CMDSENT: u1,
-            ///  Data end (data counter, SDIDCOUNT, is zero)
-            DATAEND: u1,
-            ///  Start bit not detected on all data signals in wide bus mode
-            STBITERR: u1,
-            ///  Data block sent/received (CRC check passed)
-            DBCKEND: u1,
-            ///  Command transfer in progress
-            CMDACT: u1,
-            ///  Data transmit in progress
-            TXACT: u1,
-            ///  Data receive in progress
-            RXACT: u1,
-            ///  Transmit FIFO half empty: at least 8 words can be written into the FIFO
-            TXFIFOHE: u1,
-            ///  Receive FIFO half full: there are at least 8 words in the FIFO
-            RXFIFOHF: u1,
-            ///  Transmit FIFO full
-            TXFIFOF: u1,
-            ///  Receive FIFO full
-            RXFIFOF: u1,
-            ///  Transmit FIFO empty
-            TXFIFOE: u1,
-            ///  Receive FIFO empty
-            RXFIFOE: u1,
-            ///  Data available in transmit FIFO
-            TXDAVL: u1,
-            ///  Data available in receive FIFO
-            RXDAVL: u1,
-            ///  SDIO interrupt received
-            SDIOIT: u1,
-            ///  CE-ATA command completion signal received for CMD61
-            CEATAEND: u1,
-            padding: u8,
-        }),
-        ///  interrupt clear register
-        ICR: mmio.Mmio(packed struct(u32) {
-            ///  CCRCFAIL flag clear bit
-            CCRCFAILC: u1,
-            ///  DCRCFAIL flag clear bit
-            DCRCFAILC: u1,
-            ///  CTIMEOUT flag clear bit
-            CTIMEOUTC: u1,
-            ///  DTIMEOUT flag clear bit
-            DTIMEOUTC: u1,
-            ///  TXUNDERR flag clear bit
-            TXUNDERRC: u1,
-            ///  RXOVERR flag clear bit
-            RXOVERRC: u1,
-            ///  CMDREND flag clear bit
-            CMDRENDC: u1,
-            ///  CMDSENT flag clear bit
-            CMDSENTC: u1,
-            ///  DATAEND flag clear bit
-            DATAENDC: u1,
-            ///  STBITERR flag clear bit
-            STBITERRC: u1,
-            ///  DBCKEND flag clear bit
-            DBCKENDC: u1,
-            reserved22: u11,
-            ///  SDIOIT flag clear bit
-            SDIOITC: u1,
-            ///  CEATAEND flag clear bit
-            CEATAENDC: u1,
-            padding: u8,
-        }),
-        ///  mask register
-        MASK: mmio.Mmio(packed struct(u32) {
-            ///  Command CRC fail interrupt enable
-            CCRCFAILIE: u1,
-            ///  Data CRC fail interrupt enable
-            DCRCFAILIE: u1,
-            ///  Command timeout interrupt enable
-            CTIMEOUTIE: u1,
-            ///  Data timeout interrupt enable
-            DTIMEOUTIE: u1,
-            ///  Tx FIFO underrun error interrupt enable
-            TXUNDERRIE: u1,
-            ///  Rx FIFO overrun error interrupt enable
-            RXOVERRIE: u1,
-            ///  Command response received interrupt enable
-            CMDRENDIE: u1,
-            ///  Command sent interrupt enable
-            CMDSENTIE: u1,
-            ///  Data end interrupt enable
-            DATAENDIE: u1,
-            ///  Start bit error interrupt enable
-            STBITERRIE: u1,
-            ///  Data block end interrupt enable
-            DBCKENDIE: u1,
-            ///  Command acting interrupt enable
-            CMDACTIE: u1,
-            ///  Data transmit acting interrupt enable
-            TXACTIE: u1,
-            ///  Data receive acting interrupt enable
-            RXACTIE: u1,
-            ///  Tx FIFO half empty interrupt enable
-            TXFIFOHEIE: u1,
-            ///  Rx FIFO half full interrupt enable
-            RXFIFOHFIE: u1,
-            ///  Tx FIFO full interrupt enable
-            TXFIFOFIE: u1,
-            ///  Rx FIFO full interrupt enable
-            RXFIFOFIE: u1,
-            ///  Tx FIFO empty interrupt enable
-            TXFIFOEIE: u1,
-            ///  Rx FIFO empty interrupt enable
-            RXFIFOEIE: u1,
-            ///  Data available in Tx FIFO interrupt enable
-            TXDAVLIE: u1,
-            ///  Data available in Rx FIFO interrupt enable
-            RXDAVLIE: u1,
-            ///  SDIO mode interrupt received interrupt enable
-            SDIOITIE: u1,
-            ///  CE-ATA command completion signal received interrupt enable
-            CEATAENDIE: u1,
-            padding: u8,
-        }),
-        reserved72: [8]u8,
-        ///  FIFO counter register
-        FIFOCNT: mmio.Mmio(packed struct(u32) {
-            ///  Remaining number of words to be written to or read from the FIFO.
-            FIFOCOUNT: u24,
-            padding: u8,
-        }),
-        reserved128: [52]u8,
-        ///  data FIFO register
-        FIFO: mmio.Mmio(packed struct(u32) {
-            ///  Receive and transmit FIFO data
-            FIFOData: u32,
-        }),
-    };
-
-    ///  Analog-to-digital converter
-    pub const ADC1 = extern struct {
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog flag
-            AWD: u1,
-            ///  Regular channel end of conversion
-            EOC: u1,
-            ///  Injected channel end of conversion
-            JEOC: u1,
-            ///  Injected channel start flag
-            JSTRT: u1,
-            ///  Regular channel start flag
-            STRT: u1,
-            ///  Overrun
-            OVR: u1,
-            padding: u26,
-        }),
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog channel select bits
-            AWDCH: u5,
-            ///  Interrupt enable for EOC
-            EOCIE: u1,
-            ///  Analog watchdog interrupt enable
-            AWDIE: u1,
-            ///  Interrupt enable for injected channels
-            JEOCIE: u1,
-            ///  Scan mode
-            SCAN: u1,
-            ///  Enable the watchdog on a single channel in scan mode
-            AWDSGL: u1,
-            ///  Automatic injected group conversion
-            JAUTO: u1,
-            ///  Discontinuous mode on regular channels
-            DISCEN: u1,
-            ///  Discontinuous mode on injected channels
-            JDISCEN: u1,
-            ///  Discontinuous mode channel count
-            DISCNUM: u3,
-            reserved22: u6,
-            ///  Analog watchdog enable on injected channels
-            JAWDEN: u1,
-            ///  Analog watchdog enable on regular channels
-            AWDEN: u1,
-            ///  Resolution
-            RES: u2,
-            ///  Overrun interrupt enable
-            OVRIE: u1,
-            padding: u5,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  A/D Converter ON / OFF
-            ADON: u1,
-            ///  Continuous conversion
-            CONT: u1,
-            reserved8: u6,
-            ///  Direct memory access mode (for single ADC mode)
-            DMA: u1,
-            ///  DMA disable selection (for single ADC mode)
-            DDS: u1,
-            ///  End of conversion selection
-            EOCS: u1,
-            ///  Data alignment
-            ALIGN: u1,
-            reserved16: u4,
-            ///  External event select for injected group
-            JEXTSEL: u4,
-            ///  External trigger enable for injected channels
-            JEXTEN: u2,
-            ///  Start conversion of injected channels
-            JSWSTART: u1,
-            reserved24: u1,
-            ///  External event select for regular group
-            EXTSEL: u4,
-            ///  External trigger enable for regular channels
-            EXTEN: u2,
-            ///  Start conversion of regular channels
-            SWSTART: u1,
-            padding: u1,
-        }),
-        ///  sample time register 1
-        SMPR1: mmio.Mmio(packed struct(u32) {
-            ///  Sample time bits
-            SMPx_x: u32,
-        }),
-        ///  sample time register 2
-        SMPR2: mmio.Mmio(packed struct(u32) {
-            ///  Sample time bits
-            SMPx_x: u32,
-        }),
-        ///  injected channel data offset register x
-        JOFR1: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET1: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR2: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET2: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR3: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET3: u12,
-            padding: u20,
-        }),
-        ///  injected channel data offset register x
-        JOFR4: mmio.Mmio(packed struct(u32) {
-            ///  Data offset for injected channel x
-            JOFFSET4: u12,
-            padding: u20,
-        }),
-        ///  watchdog higher threshold register
-        HTR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog higher threshold
-            HT: u12,
-            padding: u20,
-        }),
-        ///  watchdog lower threshold register
-        LTR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog lower threshold
-            LT: u12,
-            padding: u20,
-        }),
-        ///  regular sequence register 1
-        SQR1: mmio.Mmio(packed struct(u32) {
-            ///  13th conversion in regular sequence
-            SQ13: u5,
-            ///  14th conversion in regular sequence
-            SQ14: u5,
-            ///  15th conversion in regular sequence
-            SQ15: u5,
-            ///  16th conversion in regular sequence
-            SQ16: u5,
-            ///  Regular channel sequence length
-            L: u4,
-            padding: u8,
-        }),
-        ///  regular sequence register 2
-        SQR2: mmio.Mmio(packed struct(u32) {
-            ///  7th conversion in regular sequence
-            SQ7: u5,
-            ///  8th conversion in regular sequence
-            SQ8: u5,
-            ///  9th conversion in regular sequence
-            SQ9: u5,
-            ///  10th conversion in regular sequence
-            SQ10: u5,
-            ///  11th conversion in regular sequence
-            SQ11: u5,
-            ///  12th conversion in regular sequence
-            SQ12: u5,
-            padding: u2,
-        }),
-        ///  regular sequence register 3
-        SQR3: mmio.Mmio(packed struct(u32) {
-            ///  1st conversion in regular sequence
-            SQ1: u5,
-            ///  2nd conversion in regular sequence
-            SQ2: u5,
-            ///  3rd conversion in regular sequence
-            SQ3: u5,
-            ///  4th conversion in regular sequence
-            SQ4: u5,
-            ///  5th conversion in regular sequence
-            SQ5: u5,
-            ///  6th conversion in regular sequence
-            SQ6: u5,
-            padding: u2,
-        }),
-        ///  injected sequence register
-        JSQR: mmio.Mmio(packed struct(u32) {
-            ///  1st conversion in injected sequence
-            JSQ1: u5,
-            ///  2nd conversion in injected sequence
-            JSQ2: u5,
-            ///  3rd conversion in injected sequence
-            JSQ3: u5,
-            ///  4th conversion in injected sequence
-            JSQ4: u5,
-            ///  Injected sequence length
-            JL: u2,
-            padding: u10,
-        }),
-        ///  injected data register x
-        JDR1: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR2: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR3: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  injected data register x
-        JDR4: mmio.Mmio(packed struct(u32) {
-            ///  Injected data
-            JDATA: u16,
-            padding: u16,
-        }),
-        ///  regular data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Regular data
-            DATA: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  USB on the go high speed
-    pub const OTG_HS_GLOBAL = extern struct {
-        ///  OTG_HS control and status register
-        OTG_HS_GOTGCTL: mmio.Mmio(packed struct(u32) {
-            ///  Session request success
-            SRQSCS: u1,
-            ///  Session request
-            SRQ: u1,
-            reserved8: u6,
-            ///  Host negotiation success
-            HNGSCS: u1,
-            ///  HNP request
-            HNPRQ: u1,
-            ///  Host set HNP enable
-            HSHNPEN: u1,
-            ///  Device HNP enabled
-            DHNPEN: u1,
-            reserved16: u4,
-            ///  Connector ID status
-            CIDSTS: u1,
-            ///  Long/short debounce time
-            DBCT: u1,
-            ///  A-session valid
-            ASVLD: u1,
-            ///  B-session valid
-            BSVLD: u1,
-            padding: u12,
-        }),
-        ///  OTG_HS interrupt register
-        OTG_HS_GOTGINT: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Session end detected
-            SEDET: u1,
-            reserved8: u5,
-            ///  Session request success status change
-            SRSSCHG: u1,
-            ///  Host negotiation success status change
-            HNSSCHG: u1,
-            reserved17: u7,
-            ///  Host negotiation detected
-            HNGDET: u1,
-            ///  A-device timeout change
-            ADTOCHG: u1,
-            ///  Debounce done
-            DBCDNE: u1,
-            padding: u12,
-        }),
-        ///  OTG_HS AHB configuration register
-        OTG_HS_GAHBCFG: mmio.Mmio(packed struct(u32) {
-            ///  Global interrupt mask
-            GINT: u1,
-            ///  Burst length/type
-            HBSTLEN: u4,
-            ///  DMA enable
-            DMAEN: u1,
-            reserved7: u1,
-            ///  TxFIFO empty level
-            TXFELVL: u1,
-            ///  Periodic TxFIFO empty level
-            PTXFELVL: u1,
-            padding: u23,
-        }),
-        ///  OTG_HS USB configuration register
-        OTG_HS_GUSBCFG: mmio.Mmio(packed struct(u32) {
-            ///  FS timeout calibration
-            TOCAL: u3,
-            reserved6: u3,
-            ///  USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select
-            PHYSEL: u1,
-            reserved8: u1,
-            ///  SRP-capable
-            SRPCAP: u1,
-            ///  HNP-capable
-            HNPCAP: u1,
-            ///  USB turnaround time
-            TRDT: u4,
-            reserved15: u1,
-            ///  PHY Low-power clock select
-            PHYLPCS: u1,
-            reserved17: u1,
-            ///  ULPI FS/LS select
-            ULPIFSLS: u1,
-            ///  ULPI Auto-resume
-            ULPIAR: u1,
-            ///  ULPI Clock SuspendM
-            ULPICSM: u1,
-            ///  ULPI External VBUS Drive
-            ULPIEVBUSD: u1,
-            ///  ULPI external VBUS indicator
-            ULPIEVBUSI: u1,
-            ///  TermSel DLine pulsing selection
-            TSDPS: u1,
-            ///  Indicator complement
-            PCCI: u1,
-            ///  Indicator pass through
-            PTCI: u1,
-            ///  ULPI interface protect disable
-            ULPIIPD: u1,
-            reserved29: u3,
-            ///  Forced host mode
-            FHMOD: u1,
-            ///  Forced peripheral mode
-            FDMOD: u1,
-            ///  Corrupt Tx packet
-            CTXPKT: u1,
-        }),
-        ///  OTG_HS reset register
-        OTG_HS_GRSTCTL: mmio.Mmio(packed struct(u32) {
-            ///  Core soft reset
-            CSRST: u1,
-            ///  HCLK soft reset
-            HSRST: u1,
-            ///  Host frame counter reset
-            FCRST: u1,
-            reserved4: u1,
-            ///  RxFIFO flush
-            RXFFLSH: u1,
-            ///  TxFIFO flush
-            TXFFLSH: u1,
-            ///  TxFIFO number
-            TXFNUM: u5,
-            reserved30: u19,
-            ///  DMA request signal
-            DMAREQ: u1,
-            ///  AHB master idle
-            AHBIDL: u1,
-        }),
-        ///  OTG_HS core interrupt register
-        OTG_HS_GINTSTS: mmio.Mmio(packed struct(u32) {
-            ///  Current mode of operation
-            CMOD: u1,
-            ///  Mode mismatch interrupt
-            MMIS: u1,
-            ///  OTG interrupt
-            OTGINT: u1,
-            ///  Start of frame
-            SOF: u1,
-            ///  RxFIFO nonempty
-            RXFLVL: u1,
-            ///  Nonperiodic TxFIFO empty
-            NPTXFE: u1,
-            ///  Global IN nonperiodic NAK effective
-            GINAKEFF: u1,
-            ///  Global OUT NAK effective
-            BOUTNAKEFF: u1,
-            reserved10: u2,
-            ///  Early suspend
-            ESUSP: u1,
-            ///  USB suspend
-            USBSUSP: u1,
-            ///  USB reset
-            USBRST: u1,
-            ///  Enumeration done
-            ENUMDNE: u1,
-            ///  Isochronous OUT packet dropped interrupt
-            ISOODRP: u1,
-            ///  End of periodic frame interrupt
-            EOPF: u1,
-            reserved18: u2,
-            ///  IN endpoint interrupt
-            IEPINT: u1,
-            ///  OUT endpoint interrupt
-            OEPINT: u1,
-            ///  Incomplete isochronous IN transfer
-            IISOIXFR: u1,
-            ///  Incomplete periodic transfer
-            PXFR_INCOMPISOOUT: u1,
-            ///  Data fetch suspended
-            DATAFSUSP: u1,
-            reserved24: u1,
-            ///  Host port interrupt
-            HPRTINT: u1,
-            ///  Host channels interrupt
-            HCINT: u1,
-            ///  Periodic TxFIFO empty
-            PTXFE: u1,
-            reserved28: u1,
-            ///  Connector ID status change
-            CIDSCHG: u1,
-            ///  Disconnect detected interrupt
-            DISCINT: u1,
-            ///  Session request/new session detected interrupt
-            SRQINT: u1,
-            ///  Resume/remote wakeup detected interrupt
-            WKUINT: u1,
-        }),
-        ///  OTG_HS interrupt mask register
-        OTG_HS_GINTMSK: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Mode mismatch interrupt mask
-            MMISM: u1,
-            ///  OTG interrupt mask
-            OTGINT: u1,
-            ///  Start of frame mask
-            SOFM: u1,
-            ///  Receive FIFO nonempty mask
-            RXFLVLM: u1,
-            ///  Nonperiodic TxFIFO empty mask
-            NPTXFEM: u1,
-            ///  Global nonperiodic IN NAK effective mask
-            GINAKEFFM: u1,
-            ///  Global OUT NAK effective mask
-            GONAKEFFM: u1,
-            reserved10: u2,
-            ///  Early suspend mask
-            ESUSPM: u1,
-            ///  USB suspend mask
-            USBSUSPM: u1,
-            ///  USB reset mask
-            USBRST: u1,
-            ///  Enumeration done mask
-            ENUMDNEM: u1,
-            ///  Isochronous OUT packet dropped interrupt mask
-            ISOODRPM: u1,
-            ///  End of periodic frame interrupt mask
-            EOPFM: u1,
-            reserved17: u1,
-            ///  Endpoint mismatch interrupt mask
-            EPMISM: u1,
-            ///  IN endpoints interrupt mask
-            IEPINT: u1,
-            ///  OUT endpoints interrupt mask
-            OEPINT: u1,
-            ///  Incomplete isochronous IN transfer mask
-            IISOIXFRM: u1,
-            ///  Incomplete periodic transfer mask
-            PXFRM_IISOOXFRM: u1,
-            ///  Data fetch suspended mask
-            FSUSPM: u1,
-            reserved24: u1,
-            ///  Host port interrupt mask
-            PRTIM: u1,
-            ///  Host channels interrupt mask
-            HCIM: u1,
-            ///  Periodic TxFIFO empty mask
-            PTXFEM: u1,
-            reserved28: u1,
-            ///  Connector ID status change mask
-            CIDSCHGM: u1,
-            ///  Disconnect detected interrupt mask
-            DISCINT: u1,
-            ///  Session request/new session detected interrupt mask
-            SRQIM: u1,
-            ///  Resume/remote wakeup detected interrupt mask
-            WUIM: u1,
-        }),
-        ///  OTG_HS Receive status debug read register (host mode)
-        OTG_HS_GRXSTSR_Host: mmio.Mmio(packed struct(u32) {
-            ///  Channel number
-            CHNUM: u4,
-            ///  Byte count
-            BCNT: u11,
-            ///  Data PID
-            DPID: u2,
-            ///  Packet status
-            PKTSTS: u4,
-            padding: u11,
-        }),
-        ///  OTG_HS status read and pop register (host mode)
-        OTG_HS_GRXSTSP_Host: mmio.Mmio(packed struct(u32) {
-            ///  Channel number
-            CHNUM: u4,
-            ///  Byte count
-            BCNT: u11,
-            ///  Data PID
-            DPID: u2,
-            ///  Packet status
-            PKTSTS: u4,
-            padding: u11,
-        }),
-        ///  OTG_HS Receive FIFO size register
-        OTG_HS_GRXFSIZ: mmio.Mmio(packed struct(u32) {
-            ///  RxFIFO depth
-            RXFD: u16,
-            padding: u16,
-        }),
-        ///  OTG_HS nonperiodic transmit FIFO size register (host mode)
-        OTG_HS_GNPTXFSIZ_Host: mmio.Mmio(packed struct(u32) {
-            ///  Nonperiodic transmit RAM start address
-            NPTXFSA: u16,
-            ///  Nonperiodic TxFIFO depth
-            NPTXFD: u16,
-        }),
-        ///  OTG_HS nonperiodic transmit FIFO/queue status register
-        OTG_HS_GNPTXSTS: mmio.Mmio(packed struct(u32) {
-            ///  Nonperiodic TxFIFO space available
-            NPTXFSAV: u16,
-            ///  Nonperiodic transmit request queue space available
-            NPTQXSAV: u8,
-            ///  Top of the nonperiodic transmit request queue
-            NPTXQTOP: u7,
-            padding: u1,
-        }),
-        reserved56: [8]u8,
-        ///  OTG_HS general core configuration register
-        OTG_HS_GCCFG: mmio.Mmio(packed struct(u32) {
-            reserved16: u16,
-            ///  Power down
-            PWRDWN: u1,
-            ///  Enable I2C bus connection for the external I2C PHY interface
-            I2CPADEN: u1,
-            ///  Enable the VBUS sensing device
-            VBUSASEN: u1,
-            ///  Enable the VBUS sensing device
-            VBUSBSEN: u1,
-            ///  SOF output enable
-            SOFOUTEN: u1,
-            ///  VBUS sensing disable option
-            NOVBUSSENS: u1,
-            padding: u10,
-        }),
-        ///  OTG_HS core ID register
-        OTG_HS_CID: mmio.Mmio(packed struct(u32) {
-            ///  Product ID field
-            PRODUCT_ID: u32,
-        }),
-        reserved256: [192]u8,
-        ///  OTG_HS Host periodic transmit FIFO size register
-        OTG_HS_HPTXFSIZ: mmio.Mmio(packed struct(u32) {
-            ///  Host periodic TxFIFO start address
-            PTXSA: u16,
-            ///  Host periodic TxFIFO depth
-            PTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF1: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF2: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        reserved284: [16]u8,
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF3: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF4: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF5: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF6: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_HS device IN endpoint transmit FIFO size register
-        OTG_HS_DIEPTXF7: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFOx transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-    };
-
-    ///  External interrupt/event controller
-    pub const EXTI = extern struct {
-        ///  Interrupt mask register (EXTI_IMR)
-        IMR: mmio.Mmio(packed struct(u32) {
-            ///  Interrupt Mask on line 0
-            MR0: u1,
-            ///  Interrupt Mask on line 1
-            MR1: u1,
-            ///  Interrupt Mask on line 2
-            MR2: u1,
-            ///  Interrupt Mask on line 3
-            MR3: u1,
-            ///  Interrupt Mask on line 4
-            MR4: u1,
-            ///  Interrupt Mask on line 5
-            MR5: u1,
-            ///  Interrupt Mask on line 6
-            MR6: u1,
-            ///  Interrupt Mask on line 7
-            MR7: u1,
-            ///  Interrupt Mask on line 8
-            MR8: u1,
-            ///  Interrupt Mask on line 9
-            MR9: u1,
-            ///  Interrupt Mask on line 10
-            MR10: u1,
-            ///  Interrupt Mask on line 11
-            MR11: u1,
-            ///  Interrupt Mask on line 12
-            MR12: u1,
-            ///  Interrupt Mask on line 13
-            MR13: u1,
-            ///  Interrupt Mask on line 14
-            MR14: u1,
-            ///  Interrupt Mask on line 15
-            MR15: u1,
-            ///  Interrupt Mask on line 16
-            MR16: u1,
-            ///  Interrupt Mask on line 17
-            MR17: u1,
-            ///  Interrupt Mask on line 18
-            MR18: u1,
-            ///  Interrupt Mask on line 19
-            MR19: u1,
-            ///  Interrupt Mask on line 20
-            MR20: u1,
-            ///  Interrupt Mask on line 21
-            MR21: u1,
-            ///  Interrupt Mask on line 22
-            MR22: u1,
-            padding: u9,
-        }),
-        ///  Event mask register (EXTI_EMR)
-        EMR: mmio.Mmio(packed struct(u32) {
-            ///  Event Mask on line 0
-            MR0: u1,
-            ///  Event Mask on line 1
-            MR1: u1,
-            ///  Event Mask on line 2
-            MR2: u1,
-            ///  Event Mask on line 3
-            MR3: u1,
-            ///  Event Mask on line 4
-            MR4: u1,
-            ///  Event Mask on line 5
-            MR5: u1,
-            ///  Event Mask on line 6
-            MR6: u1,
-            ///  Event Mask on line 7
-            MR7: u1,
-            ///  Event Mask on line 8
-            MR8: u1,
-            ///  Event Mask on line 9
-            MR9: u1,
-            ///  Event Mask on line 10
-            MR10: u1,
-            ///  Event Mask on line 11
-            MR11: u1,
-            ///  Event Mask on line 12
-            MR12: u1,
-            ///  Event Mask on line 13
-            MR13: u1,
-            ///  Event Mask on line 14
-            MR14: u1,
-            ///  Event Mask on line 15
-            MR15: u1,
-            ///  Event Mask on line 16
-            MR16: u1,
-            ///  Event Mask on line 17
-            MR17: u1,
-            ///  Event Mask on line 18
-            MR18: u1,
-            ///  Event Mask on line 19
-            MR19: u1,
-            ///  Event Mask on line 20
-            MR20: u1,
-            ///  Event Mask on line 21
-            MR21: u1,
-            ///  Event Mask on line 22
-            MR22: u1,
-            padding: u9,
-        }),
-        ///  Rising Trigger selection register (EXTI_RTSR)
-        RTSR: mmio.Mmio(packed struct(u32) {
-            ///  Rising trigger event configuration of line 0
-            TR0: u1,
-            ///  Rising trigger event configuration of line 1
-            TR1: u1,
-            ///  Rising trigger event configuration of line 2
-            TR2: u1,
-            ///  Rising trigger event configuration of line 3
-            TR3: u1,
-            ///  Rising trigger event configuration of line 4
-            TR4: u1,
-            ///  Rising trigger event configuration of line 5
-            TR5: u1,
-            ///  Rising trigger event configuration of line 6
-            TR6: u1,
-            ///  Rising trigger event configuration of line 7
-            TR7: u1,
-            ///  Rising trigger event configuration of line 8
-            TR8: u1,
-            ///  Rising trigger event configuration of line 9
-            TR9: u1,
-            ///  Rising trigger event configuration of line 10
-            TR10: u1,
-            ///  Rising trigger event configuration of line 11
-            TR11: u1,
-            ///  Rising trigger event configuration of line 12
-            TR12: u1,
-            ///  Rising trigger event configuration of line 13
-            TR13: u1,
-            ///  Rising trigger event configuration of line 14
-            TR14: u1,
-            ///  Rising trigger event configuration of line 15
-            TR15: u1,
-            ///  Rising trigger event configuration of line 16
-            TR16: u1,
-            ///  Rising trigger event configuration of line 17
-            TR17: u1,
-            ///  Rising trigger event configuration of line 18
-            TR18: u1,
-            ///  Rising trigger event configuration of line 19
-            TR19: u1,
-            ///  Rising trigger event configuration of line 20
-            TR20: u1,
-            ///  Rising trigger event configuration of line 21
-            TR21: u1,
-            ///  Rising trigger event configuration of line 22
-            TR22: u1,
-            padding: u9,
-        }),
-        ///  Falling Trigger selection register (EXTI_FTSR)
-        FTSR: mmio.Mmio(packed struct(u32) {
-            ///  Falling trigger event configuration of line 0
-            TR0: u1,
-            ///  Falling trigger event configuration of line 1
-            TR1: u1,
-            ///  Falling trigger event configuration of line 2
-            TR2: u1,
-            ///  Falling trigger event configuration of line 3
-            TR3: u1,
-            ///  Falling trigger event configuration of line 4
-            TR4: u1,
-            ///  Falling trigger event configuration of line 5
-            TR5: u1,
-            ///  Falling trigger event configuration of line 6
-            TR6: u1,
-            ///  Falling trigger event configuration of line 7
-            TR7: u1,
-            ///  Falling trigger event configuration of line 8
-            TR8: u1,
-            ///  Falling trigger event configuration of line 9
-            TR9: u1,
-            ///  Falling trigger event configuration of line 10
-            TR10: u1,
-            ///  Falling trigger event configuration of line 11
-            TR11: u1,
-            ///  Falling trigger event configuration of line 12
-            TR12: u1,
-            ///  Falling trigger event configuration of line 13
-            TR13: u1,
-            ///  Falling trigger event configuration of line 14
-            TR14: u1,
-            ///  Falling trigger event configuration of line 15
-            TR15: u1,
-            ///  Falling trigger event configuration of line 16
-            TR16: u1,
-            ///  Falling trigger event configuration of line 17
-            TR17: u1,
-            ///  Falling trigger event configuration of line 18
-            TR18: u1,
-            ///  Falling trigger event configuration of line 19
-            TR19: u1,
-            ///  Falling trigger event configuration of line 20
-            TR20: u1,
-            ///  Falling trigger event configuration of line 21
-            TR21: u1,
-            ///  Falling trigger event configuration of line 22
-            TR22: u1,
-            padding: u9,
-        }),
-        ///  Software interrupt event register (EXTI_SWIER)
-        SWIER: mmio.Mmio(packed struct(u32) {
-            ///  Software Interrupt on line 0
-            SWIER0: u1,
-            ///  Software Interrupt on line 1
-            SWIER1: u1,
-            ///  Software Interrupt on line 2
-            SWIER2: u1,
-            ///  Software Interrupt on line 3
-            SWIER3: u1,
-            ///  Software Interrupt on line 4
-            SWIER4: u1,
-            ///  Software Interrupt on line 5
-            SWIER5: u1,
-            ///  Software Interrupt on line 6
-            SWIER6: u1,
-            ///  Software Interrupt on line 7
-            SWIER7: u1,
-            ///  Software Interrupt on line 8
-            SWIER8: u1,
-            ///  Software Interrupt on line 9
-            SWIER9: u1,
-            ///  Software Interrupt on line 10
-            SWIER10: u1,
-            ///  Software Interrupt on line 11
-            SWIER11: u1,
-            ///  Software Interrupt on line 12
-            SWIER12: u1,
-            ///  Software Interrupt on line 13
-            SWIER13: u1,
-            ///  Software Interrupt on line 14
-            SWIER14: u1,
-            ///  Software Interrupt on line 15
-            SWIER15: u1,
-            ///  Software Interrupt on line 16
-            SWIER16: u1,
-            ///  Software Interrupt on line 17
-            SWIER17: u1,
-            ///  Software Interrupt on line 18
-            SWIER18: u1,
-            ///  Software Interrupt on line 19
-            SWIER19: u1,
-            ///  Software Interrupt on line 20
-            SWIER20: u1,
-            ///  Software Interrupt on line 21
-            SWIER21: u1,
-            ///  Software Interrupt on line 22
-            SWIER22: u1,
-            padding: u9,
-        }),
-        ///  Pending register (EXTI_PR)
-        PR: mmio.Mmio(packed struct(u32) {
-            ///  Pending bit 0
-            PR0: u1,
-            ///  Pending bit 1
-            PR1: u1,
-            ///  Pending bit 2
-            PR2: u1,
-            ///  Pending bit 3
-            PR3: u1,
-            ///  Pending bit 4
-            PR4: u1,
-            ///  Pending bit 5
-            PR5: u1,
-            ///  Pending bit 6
-            PR6: u1,
-            ///  Pending bit 7
-            PR7: u1,
-            ///  Pending bit 8
-            PR8: u1,
-            ///  Pending bit 9
-            PR9: u1,
-            ///  Pending bit 10
-            PR10: u1,
-            ///  Pending bit 11
-            PR11: u1,
-            ///  Pending bit 12
-            PR12: u1,
-            ///  Pending bit 13
-            PR13: u1,
-            ///  Pending bit 14
-            PR14: u1,
-            ///  Pending bit 15
-            PR15: u1,
-            ///  Pending bit 16
-            PR16: u1,
-            ///  Pending bit 17
-            PR17: u1,
-            ///  Pending bit 18
-            PR18: u1,
-            ///  Pending bit 19
-            PR19: u1,
-            ///  Pending bit 20
-            PR20: u1,
-            ///  Pending bit 21
-            PR21: u1,
-            ///  Pending bit 22
-            PR22: u1,
-            padding: u9,
-        }),
-    };
-
-    ///  Universal synchronous asynchronous receiver transmitter
-    pub const USART6 = extern struct {
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Parity error
-            PE: u1,
-            ///  Framing error
-            FE: u1,
-            ///  Noise detected flag
-            NF: u1,
-            ///  Overrun error
-            ORE: u1,
-            ///  IDLE line detected
-            IDLE: u1,
-            ///  Read data register not empty
-            RXNE: u1,
-            ///  Transmission complete
-            TC: u1,
-            ///  Transmit data register empty
-            TXE: u1,
-            ///  LIN break detection flag
-            LBD: u1,
-            ///  CTS flag
-            CTS: u1,
-            padding: u22,
-        }),
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data value
-            DR: u9,
-            padding: u23,
-        }),
-        ///  Baud rate register
-        BRR: mmio.Mmio(packed struct(u32) {
-            ///  fraction of USARTDIV
-            DIV_Fraction: u4,
-            ///  mantissa of USARTDIV
-            DIV_Mantissa: u12,
-            padding: u16,
-        }),
-        ///  Control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Send break
-            SBK: u1,
-            ///  Receiver wakeup
-            RWU: u1,
-            ///  Receiver enable
-            RE: u1,
-            ///  Transmitter enable
-            TE: u1,
-            ///  IDLE interrupt enable
-            IDLEIE: u1,
-            ///  RXNE interrupt enable
-            RXNEIE: u1,
-            ///  Transmission complete interrupt enable
-            TCIE: u1,
-            ///  TXE interrupt enable
-            TXEIE: u1,
-            ///  PE interrupt enable
-            PEIE: u1,
-            ///  Parity selection
-            PS: u1,
-            ///  Parity control enable
-            PCE: u1,
-            ///  Wakeup method
-            WAKE: u1,
-            ///  Word length
-            M: u1,
-            ///  USART enable
-            UE: u1,
-            reserved15: u1,
-            ///  Oversampling mode
-            OVER8: u1,
-            padding: u16,
-        }),
-        ///  Control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Address of the USART node
-            ADD: u4,
-            reserved5: u1,
-            ///  lin break detection length
-            LBDL: u1,
-            ///  LIN break detection interrupt enable
-            LBDIE: u1,
-            reserved8: u1,
-            ///  Last bit clock pulse
-            LBCL: u1,
-            ///  Clock phase
-            CPHA: u1,
-            ///  Clock polarity
-            CPOL: u1,
-            ///  Clock enable
-            CLKEN: u1,
-            ///  STOP bits
-            STOP: u2,
-            ///  LIN mode enable
-            LINEN: u1,
-            padding: u17,
-        }),
-        ///  Control register 3
-        CR3: mmio.Mmio(packed struct(u32) {
-            ///  Error interrupt enable
-            EIE: u1,
-            ///  IrDA mode enable
-            IREN: u1,
-            ///  IrDA low-power
-            IRLP: u1,
-            ///  Half-duplex selection
-            HDSEL: u1,
-            ///  Smartcard NACK enable
-            NACK: u1,
-            ///  Smartcard mode enable
-            SCEN: u1,
-            ///  DMA enable receiver
-            DMAR: u1,
-            ///  DMA enable transmitter
-            DMAT: u1,
-            ///  RTS enable
-            RTSE: u1,
-            ///  CTS enable
-            CTSE: u1,
-            ///  CTS interrupt enable
-            CTSIE: u1,
-            ///  One sample bit method enable
-            ONEBIT: u1,
-            padding: u20,
-        }),
-        ///  Guard time and prescaler register
-        GTPR: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u8,
-            ///  Guard time value
-            GT: u8,
-            padding: u16,
-        }),
-    };
-
-    ///  FLASH
-    pub const FLASH = extern struct {
-        ///  Flash access control register
-        ACR: mmio.Mmio(packed struct(u32) {
-            ///  Latency
-            LATENCY: u3,
-            reserved8: u5,
-            ///  Prefetch enable
-            PRFTEN: u1,
-            ///  Instruction cache enable
-            ICEN: u1,
-            ///  Data cache enable
-            DCEN: u1,
-            ///  Instruction cache reset
-            ICRST: u1,
-            ///  Data cache reset
-            DCRST: u1,
-            padding: u19,
-        }),
-        ///  Flash key register
-        KEYR: mmio.Mmio(packed struct(u32) {
-            ///  FPEC key
-            KEY: u32,
-        }),
-        ///  Flash option key register
-        OPTKEYR: mmio.Mmio(packed struct(u32) {
-            ///  Option byte key
-            OPTKEY: u32,
-        }),
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  End of operation
-            EOP: u1,
-            ///  Operation error
-            OPERR: u1,
-            reserved4: u2,
-            ///  Write protection error
-            WRPERR: u1,
-            ///  Programming alignment error
-            PGAERR: u1,
-            ///  Programming parallelism error
-            PGPERR: u1,
-            ///  Programming sequence error
-            PGSERR: u1,
-            reserved16: u8,
-            ///  Busy
-            BSY: u1,
-            padding: u15,
-        }),
-        ///  Control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Programming
-            PG: u1,
-            ///  Sector Erase
-            SER: u1,
-            ///  Mass Erase of sectors 0 to 11
-            MER: u1,
-            ///  Sector number
-            SNB: u5,
-            ///  Program size
-            PSIZE: u2,
-            reserved15: u5,
-            ///  Mass Erase of sectors 12 to 23
-            MER1: u1,
-            ///  Start
-            STRT: u1,
-            reserved24: u7,
-            ///  End of operation interrupt enable
-            EOPIE: u1,
-            ///  Error interrupt enable
-            ERRIE: u1,
-            reserved31: u5,
-            ///  Lock
-            LOCK: u1,
-        }),
-        ///  Flash option control register
-        OPTCR: mmio.Mmio(packed struct(u32) {
-            ///  Option lock
-            OPTLOCK: u1,
-            ///  Option start
-            OPTSTRT: u1,
-            ///  BOR reset Level
-            BOR_LEV: u2,
-            reserved5: u1,
-            ///  WDG_SW User option bytes
-            WDG_SW: u1,
-            ///  nRST_STOP User option bytes
-            nRST_STOP: u1,
-            ///  nRST_STDBY User option bytes
-            nRST_STDBY: u1,
-            ///  Read protect
-            RDP: u8,
-            ///  Not write protect
-            nWRP: u12,
-            padding: u4,
-        }),
-        ///  Flash option control register 1
-        OPTCR1: mmio.Mmio(packed struct(u32) {
-            reserved16: u16,
-            ///  Not write protect
-            nWRP: u12,
-            padding: u4,
-        }),
-    };
-
-    ///  Nested Vectored Interrupt Controller
-    pub const NVIC = extern struct {
-        ///  Interrupt Set-Enable Register
-        ISER0: mmio.Mmio(packed struct(u32) {
-            ///  SETENA
-            SETENA: u32,
-        }),
-        ///  Interrupt Set-Enable Register
-        ISER1: mmio.Mmio(packed struct(u32) {
-            ///  SETENA
-            SETENA: u32,
-        }),
-        ///  Interrupt Set-Enable Register
-        ISER2: mmio.Mmio(packed struct(u32) {
-            ///  SETENA
-            SETENA: u32,
-        }),
-        reserved128: [116]u8,
-        ///  Interrupt Clear-Enable Register
-        ICER0: mmio.Mmio(packed struct(u32) {
-            ///  CLRENA
-            CLRENA: u32,
-        }),
-        ///  Interrupt Clear-Enable Register
-        ICER1: mmio.Mmio(packed struct(u32) {
-            ///  CLRENA
-            CLRENA: u32,
-        }),
-        ///  Interrupt Clear-Enable Register
-        ICER2: mmio.Mmio(packed struct(u32) {
-            ///  CLRENA
-            CLRENA: u32,
-        }),
-        reserved256: [116]u8,
-        ///  Interrupt Set-Pending Register
-        ISPR0: mmio.Mmio(packed struct(u32) {
-            ///  SETPEND
-            SETPEND: u32,
-        }),
-        ///  Interrupt Set-Pending Register
-        ISPR1: mmio.Mmio(packed struct(u32) {
-            ///  SETPEND
-            SETPEND: u32,
-        }),
-        ///  Interrupt Set-Pending Register
-        ISPR2: mmio.Mmio(packed struct(u32) {
-            ///  SETPEND
-            SETPEND: u32,
-        }),
-        reserved384: [116]u8,
-        ///  Interrupt Clear-Pending Register
-        ICPR0: mmio.Mmio(packed struct(u32) {
-            ///  CLRPEND
-            CLRPEND: u32,
-        }),
-        ///  Interrupt Clear-Pending Register
-        ICPR1: mmio.Mmio(packed struct(u32) {
-            ///  CLRPEND
-            CLRPEND: u32,
-        }),
-        ///  Interrupt Clear-Pending Register
-        ICPR2: mmio.Mmio(packed struct(u32) {
-            ///  CLRPEND
-            CLRPEND: u32,
-        }),
-        reserved512: [116]u8,
-        ///  Interrupt Active Bit Register
-        IABR0: mmio.Mmio(packed struct(u32) {
-            ///  ACTIVE
-            ACTIVE: u32,
-        }),
-        ///  Interrupt Active Bit Register
-        IABR1: mmio.Mmio(packed struct(u32) {
-            ///  ACTIVE
-            ACTIVE: u32,
-        }),
-        ///  Interrupt Active Bit Register
-        IABR2: mmio.Mmio(packed struct(u32) {
-            ///  ACTIVE
-            ACTIVE: u32,
-        }),
-        reserved768: [244]u8,
-        ///  Interrupt Priority Register
-        IPR0: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR1: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR2: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR3: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR4: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR5: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR6: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR7: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR8: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR9: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR10: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR11: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR12: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR13: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR14: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR15: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR16: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR17: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR18: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR19: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-        ///  Interrupt Priority Register
-        IPR20: mmio.Mmio(packed struct(u32) {
-            ///  IPR_N0
-            IPR_N0: u8,
-            ///  IPR_N1
-            IPR_N1: u8,
-            ///  IPR_N2
-            IPR_N2: u8,
-            ///  IPR_N3
-            IPR_N3: u8,
-        }),
-    };
-
-    ///  Ethernet: media access control (MAC)
-    pub const Ethernet_MAC = extern struct {
-        ///  Ethernet MAC configuration register
-        MACCR: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  RE
-            RE: u1,
-            ///  TE
-            TE: u1,
-            ///  DC
-            DC: u1,
-            ///  BL
-            BL: u2,
-            ///  APCS
-            APCS: u1,
-            reserved9: u1,
-            ///  RD
-            RD: u1,
-            ///  IPCO
-            IPCO: u1,
-            ///  DM
-            DM: u1,
-            ///  LM
-            LM: u1,
-            ///  ROD
-            ROD: u1,
-            ///  FES
-            FES: u1,
-            reserved16: u1,
-            ///  CSD
-            CSD: u1,
-            ///  IFG
-            IFG: u3,
-            reserved22: u2,
-            ///  JD
-            JD: u1,
-            ///  WD
-            WD: u1,
-            reserved25: u1,
-            ///  CSTF
-            CSTF: u1,
-            padding: u6,
-        }),
-        ///  Ethernet MAC frame filter register
-        MACFFR: mmio.Mmio(packed struct(u32) {
-            ///  PM
-            PM: u1,
-            ///  HU
-            HU: u1,
-            ///  HM
-            HM: u1,
-            ///  DAIF
-            DAIF: u1,
-            ///  RAM
-            RAM: u1,
-            ///  BFD
-            BFD: u1,
-            ///  PCF
-            PCF: u1,
-            ///  SAIF
-            SAIF: u1,
-            ///  SAF
-            SAF: u1,
-            ///  HPF
-            HPF: u1,
-            reserved31: u21,
-            ///  RA
-            RA: u1,
-        }),
-        ///  Ethernet MAC hash table high register
-        MACHTHR: mmio.Mmio(packed struct(u32) {
-            ///  HTH
-            HTH: u32,
-        }),
-        ///  Ethernet MAC hash table low register
-        MACHTLR: mmio.Mmio(packed struct(u32) {
-            ///  HTL
-            HTL: u32,
-        }),
-        ///  Ethernet MAC MII address register
-        MACMIIAR: mmio.Mmio(packed struct(u32) {
-            ///  MB
-            MB: u1,
-            ///  MW
-            MW: u1,
-            ///  CR
-            CR: u3,
-            reserved6: u1,
-            ///  MR
-            MR: u5,
-            ///  PA
-            PA: u5,
-            padding: u16,
-        }),
-        ///  Ethernet MAC MII data register
-        MACMIIDR: mmio.Mmio(packed struct(u32) {
-            ///  TD
-            TD: u16,
-            padding: u16,
-        }),
-        ///  Ethernet MAC flow control register
-        MACFCR: mmio.Mmio(packed struct(u32) {
-            ///  FCB
-            FCB: u1,
-            ///  TFCE
-            TFCE: u1,
-            ///  RFCE
-            RFCE: u1,
-            ///  UPFD
-            UPFD: u1,
-            ///  PLT
-            PLT: u2,
-            reserved7: u1,
-            ///  ZQPD
-            ZQPD: u1,
-            reserved16: u8,
-            ///  PT
-            PT: u16,
-        }),
-        ///  Ethernet MAC VLAN tag register
-        MACVLANTR: mmio.Mmio(packed struct(u32) {
-            ///  VLANTI
-            VLANTI: u16,
-            ///  VLANTC
-            VLANTC: u1,
-            padding: u15,
-        }),
-        reserved44: [12]u8,
-        ///  Ethernet MAC PMT control and status register
-        MACPMTCSR: mmio.Mmio(packed struct(u32) {
-            ///  PD
-            PD: u1,
-            ///  MPE
-            MPE: u1,
-            ///  WFE
-            WFE: u1,
-            reserved5: u2,
-            ///  MPR
-            MPR: u1,
-            ///  WFR
-            WFR: u1,
-            reserved9: u2,
-            ///  GU
-            GU: u1,
-            reserved31: u21,
-            ///  WFFRPR
-            WFFRPR: u1,
-        }),
-        reserved52: [4]u8,
-        ///  Ethernet MAC debug register
-        MACDBGR: mmio.Mmio(packed struct(u32) {
-            ///  CR
-            CR: u1,
-            ///  CSR
-            CSR: u1,
-            ///  ROR
-            ROR: u1,
-            ///  MCF
-            MCF: u1,
-            ///  MCP
-            MCP: u1,
-            ///  MCFHP
-            MCFHP: u1,
-            padding: u26,
-        }),
-        ///  Ethernet MAC interrupt status register
-        MACSR: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  PMTS
-            PMTS: u1,
-            ///  MMCS
-            MMCS: u1,
-            ///  MMCRS
-            MMCRS: u1,
-            ///  MMCTS
-            MMCTS: u1,
-            reserved9: u2,
-            ///  TSTS
-            TSTS: u1,
-            padding: u22,
-        }),
-        ///  Ethernet MAC interrupt mask register
-        MACIMR: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  PMTIM
-            PMTIM: u1,
-            reserved9: u5,
-            ///  TSTIM
-            TSTIM: u1,
-            padding: u22,
-        }),
-        ///  Ethernet MAC address 0 high register
-        MACA0HR: mmio.Mmio(packed struct(u32) {
-            ///  MAC address0 high
-            MACA0H: u16,
-            reserved31: u15,
-            ///  Always 1
-            MO: u1,
-        }),
-        ///  Ethernet MAC address 0 low register
-        MACA0LR: mmio.Mmio(packed struct(u32) {
-            ///  0
-            MACA0L: u32,
-        }),
-        ///  Ethernet MAC address 1 high register
-        MACA1HR: mmio.Mmio(packed struct(u32) {
-            ///  MACA1H
-            MACA1H: u16,
-            reserved24: u8,
-            ///  MBC
-            MBC: u6,
-            ///  SA
-            SA: u1,
-            ///  AE
-            AE: u1,
-        }),
-        ///  Ethernet MAC address1 low register
-        MACA1LR: mmio.Mmio(packed struct(u32) {
-            ///  MACA1LR
-            MACA1LR: u32,
-        }),
-        ///  Ethernet MAC address 2 high register
-        MACA2HR: mmio.Mmio(packed struct(u32) {
-            ///  MAC2AH
-            MAC2AH: u16,
-            reserved24: u8,
-            ///  MBC
-            MBC: u6,
-            ///  SA
-            SA: u1,
-            ///  AE
-            AE: u1,
-        }),
-        ///  Ethernet MAC address 2 low register
-        MACA2LR: mmio.Mmio(packed struct(u32) {
-            ///  MACA2L
-            MACA2L: u31,
-            padding: u1,
-        }),
-        ///  Ethernet MAC address 3 high register
-        MACA3HR: mmio.Mmio(packed struct(u32) {
-            ///  MACA3H
-            MACA3H: u16,
-            reserved24: u8,
-            ///  MBC
-            MBC: u6,
-            ///  SA
-            SA: u1,
-            ///  AE
-            AE: u1,
-        }),
-        ///  Ethernet MAC address 3 low register
-        MACA3LR: mmio.Mmio(packed struct(u32) {
-            ///  MBCA3L
-            MBCA3L: u32,
-        }),
-    };
-
-    ///  Controller area network
-    pub const CAN1 = extern struct {
-        ///  master control register
-        MCR: mmio.Mmio(packed struct(u32) {
-            ///  INRQ
-            INRQ: u1,
-            ///  SLEEP
-            SLEEP: u1,
-            ///  TXFP
-            TXFP: u1,
-            ///  RFLM
-            RFLM: u1,
-            ///  NART
-            NART: u1,
-            ///  AWUM
-            AWUM: u1,
-            ///  ABOM
-            ABOM: u1,
-            ///  TTCM
-            TTCM: u1,
-            reserved15: u7,
-            ///  RESET
-            RESET: u1,
-            ///  DBF
-            DBF: u1,
-            padding: u15,
-        }),
-        ///  master status register
-        MSR: mmio.Mmio(packed struct(u32) {
-            ///  INAK
-            INAK: u1,
-            ///  SLAK
-            SLAK: u1,
-            ///  ERRI
-            ERRI: u1,
-            ///  WKUI
-            WKUI: u1,
-            ///  SLAKI
-            SLAKI: u1,
-            reserved8: u3,
-            ///  TXM
-            TXM: u1,
-            ///  RXM
-            RXM: u1,
-            ///  SAMP
-            SAMP: u1,
-            ///  RX
-            RX: u1,
-            padding: u20,
-        }),
-        ///  transmit status register
-        TSR: mmio.Mmio(packed struct(u32) {
-            ///  RQCP0
-            RQCP0: u1,
-            ///  TXOK0
-            TXOK0: u1,
-            ///  ALST0
-            ALST0: u1,
-            ///  TERR0
-            TERR0: u1,
-            reserved7: u3,
-            ///  ABRQ0
-            ABRQ0: u1,
-            ///  RQCP1
-            RQCP1: u1,
-            ///  TXOK1
-            TXOK1: u1,
-            ///  ALST1
-            ALST1: u1,
-            ///  TERR1
-            TERR1: u1,
-            reserved15: u3,
-            ///  ABRQ1
-            ABRQ1: u1,
-            ///  RQCP2
-            RQCP2: u1,
-            ///  TXOK2
-            TXOK2: u1,
-            ///  ALST2
-            ALST2: u1,
-            ///  TERR2
-            TERR2: u1,
-            reserved23: u3,
-            ///  ABRQ2
-            ABRQ2: u1,
-            ///  CODE
-            CODE: u2,
-            ///  Lowest priority flag for mailbox 0
-            TME0: u1,
-            ///  Lowest priority flag for mailbox 1
-            TME1: u1,
-            ///  Lowest priority flag for mailbox 2
-            TME2: u1,
-            ///  Lowest priority flag for mailbox 0
-            LOW0: u1,
-            ///  Lowest priority flag for mailbox 1
-            LOW1: u1,
-            ///  Lowest priority flag for mailbox 2
-            LOW2: u1,
-        }),
-        ///  receive FIFO 0 register
-        RF0R: mmio.Mmio(packed struct(u32) {
-            ///  FMP0
-            FMP0: u2,
-            reserved3: u1,
-            ///  FULL0
-            FULL0: u1,
-            ///  FOVR0
-            FOVR0: u1,
-            ///  RFOM0
-            RFOM0: u1,
-            padding: u26,
-        }),
-        ///  receive FIFO 1 register
-        RF1R: mmio.Mmio(packed struct(u32) {
-            ///  FMP1
-            FMP1: u2,
-            reserved3: u1,
-            ///  FULL1
-            FULL1: u1,
-            ///  FOVR1
-            FOVR1: u1,
-            ///  RFOM1
-            RFOM1: u1,
-            padding: u26,
-        }),
-        ///  interrupt enable register
-        IER: mmio.Mmio(packed struct(u32) {
-            ///  TMEIE
-            TMEIE: u1,
-            ///  FMPIE0
-            FMPIE0: u1,
-            ///  FFIE0
-            FFIE0: u1,
-            ///  FOVIE0
-            FOVIE0: u1,
-            ///  FMPIE1
-            FMPIE1: u1,
-            ///  FFIE1
-            FFIE1: u1,
-            ///  FOVIE1
-            FOVIE1: u1,
-            reserved8: u1,
-            ///  EWGIE
-            EWGIE: u1,
-            ///  EPVIE
-            EPVIE: u1,
-            ///  BOFIE
-            BOFIE: u1,
-            ///  LECIE
-            LECIE: u1,
-            reserved15: u3,
-            ///  ERRIE
-            ERRIE: u1,
-            ///  WKUIE
-            WKUIE: u1,
-            ///  SLKIE
-            SLKIE: u1,
-            padding: u14,
-        }),
-        ///  interrupt enable register
-        ESR: mmio.Mmio(packed struct(u32) {
-            ///  EWGF
-            EWGF: u1,
-            ///  EPVF
-            EPVF: u1,
-            ///  BOFF
-            BOFF: u1,
-            reserved4: u1,
-            ///  LEC
-            LEC: u3,
-            reserved16: u9,
-            ///  TEC
-            TEC: u8,
-            ///  REC
-            REC: u8,
-        }),
-        ///  bit timing register
-        BTR: mmio.Mmio(packed struct(u32) {
-            ///  BRP
-            BRP: u10,
-            reserved16: u6,
-            ///  TS1
-            TS1: u4,
-            ///  TS2
-            TS2: u3,
-            reserved24: u1,
-            ///  SJW
-            SJW: u2,
-            reserved30: u4,
-            ///  LBKM
-            LBKM: u1,
-            ///  SILM
-            SILM: u1,
-        }),
-        reserved384: [352]u8,
-        ///  TX mailbox identifier register
-        TI0R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data length control and time stamp register
-        TDT0R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data low register
-        TDL0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  mailbox data high register
-        TDH0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  mailbox identifier register
-        TI1R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data length control and time stamp register
-        TDT1R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data low register
-        TDL1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  mailbox data high register
-        TDH1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  mailbox identifier register
-        TI2R: mmio.Mmio(packed struct(u32) {
-            ///  TXRQ
-            TXRQ: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data length control and time stamp register
-        TDT2R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  TGT
-            TGT: u1,
-            reserved16: u7,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data low register
-        TDL2R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  mailbox data high register
-        TDH2R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  receive FIFO mailbox identifier register
-        RI0R: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data high register
-        RDT0R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  FMI
-            FMI: u8,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data high register
-        RDL0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  receive FIFO mailbox data high register
-        RDH0R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        ///  mailbox data high register
-        RI1R: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  RTR
-            RTR: u1,
-            ///  IDE
-            IDE: u1,
-            ///  EXID
-            EXID: u18,
-            ///  STID
-            STID: u11,
-        }),
-        ///  mailbox data high register
-        RDT1R: mmio.Mmio(packed struct(u32) {
-            ///  DLC
-            DLC: u4,
-            reserved8: u4,
-            ///  FMI
-            FMI: u8,
-            ///  TIME
-            TIME: u16,
-        }),
-        ///  mailbox data high register
-        RDL1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA0
-            DATA0: u8,
-            ///  DATA1
-            DATA1: u8,
-            ///  DATA2
-            DATA2: u8,
-            ///  DATA3
-            DATA3: u8,
-        }),
-        ///  mailbox data high register
-        RDH1R: mmio.Mmio(packed struct(u32) {
-            ///  DATA4
-            DATA4: u8,
-            ///  DATA5
-            DATA5: u8,
-            ///  DATA6
-            DATA6: u8,
-            ///  DATA7
-            DATA7: u8,
-        }),
-        reserved512: [48]u8,
-        ///  filter master register
-        FMR: mmio.Mmio(packed struct(u32) {
-            ///  FINIT
-            FINIT: u1,
-            reserved8: u7,
-            ///  CAN2SB
-            CAN2SB: u6,
-            padding: u18,
-        }),
-        ///  filter mode register
-        FM1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter mode
-            FBM0: u1,
-            ///  Filter mode
-            FBM1: u1,
-            ///  Filter mode
-            FBM2: u1,
-            ///  Filter mode
-            FBM3: u1,
-            ///  Filter mode
-            FBM4: u1,
-            ///  Filter mode
-            FBM5: u1,
-            ///  Filter mode
-            FBM6: u1,
-            ///  Filter mode
-            FBM7: u1,
-            ///  Filter mode
-            FBM8: u1,
-            ///  Filter mode
-            FBM9: u1,
-            ///  Filter mode
-            FBM10: u1,
-            ///  Filter mode
-            FBM11: u1,
-            ///  Filter mode
-            FBM12: u1,
-            ///  Filter mode
-            FBM13: u1,
-            ///  Filter mode
-            FBM14: u1,
-            ///  Filter mode
-            FBM15: u1,
-            ///  Filter mode
-            FBM16: u1,
-            ///  Filter mode
-            FBM17: u1,
-            ///  Filter mode
-            FBM18: u1,
-            ///  Filter mode
-            FBM19: u1,
-            ///  Filter mode
-            FBM20: u1,
-            ///  Filter mode
-            FBM21: u1,
-            ///  Filter mode
-            FBM22: u1,
-            ///  Filter mode
-            FBM23: u1,
-            ///  Filter mode
-            FBM24: u1,
-            ///  Filter mode
-            FBM25: u1,
-            ///  Filter mode
-            FBM26: u1,
-            ///  Filter mode
-            FBM27: u1,
-            padding: u4,
-        }),
-        reserved524: [4]u8,
-        ///  filter scale register
-        FS1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter scale configuration
-            FSC0: u1,
-            ///  Filter scale configuration
-            FSC1: u1,
-            ///  Filter scale configuration
-            FSC2: u1,
-            ///  Filter scale configuration
-            FSC3: u1,
-            ///  Filter scale configuration
-            FSC4: u1,
-            ///  Filter scale configuration
-            FSC5: u1,
-            ///  Filter scale configuration
-            FSC6: u1,
-            ///  Filter scale configuration
-            FSC7: u1,
-            ///  Filter scale configuration
-            FSC8: u1,
-            ///  Filter scale configuration
-            FSC9: u1,
-            ///  Filter scale configuration
-            FSC10: u1,
-            ///  Filter scale configuration
-            FSC11: u1,
-            ///  Filter scale configuration
-            FSC12: u1,
-            ///  Filter scale configuration
-            FSC13: u1,
-            ///  Filter scale configuration
-            FSC14: u1,
-            ///  Filter scale configuration
-            FSC15: u1,
-            ///  Filter scale configuration
-            FSC16: u1,
-            ///  Filter scale configuration
-            FSC17: u1,
-            ///  Filter scale configuration
-            FSC18: u1,
-            ///  Filter scale configuration
-            FSC19: u1,
-            ///  Filter scale configuration
-            FSC20: u1,
-            ///  Filter scale configuration
-            FSC21: u1,
-            ///  Filter scale configuration
-            FSC22: u1,
-            ///  Filter scale configuration
-            FSC23: u1,
-            ///  Filter scale configuration
-            FSC24: u1,
-            ///  Filter scale configuration
-            FSC25: u1,
-            ///  Filter scale configuration
-            FSC26: u1,
-            ///  Filter scale configuration
-            FSC27: u1,
-            padding: u4,
-        }),
-        reserved532: [4]u8,
-        ///  filter FIFO assignment register
-        FFA1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter FIFO assignment for filter 0
-            FFA0: u1,
-            ///  Filter FIFO assignment for filter 1
-            FFA1: u1,
-            ///  Filter FIFO assignment for filter 2
-            FFA2: u1,
-            ///  Filter FIFO assignment for filter 3
-            FFA3: u1,
-            ///  Filter FIFO assignment for filter 4
-            FFA4: u1,
-            ///  Filter FIFO assignment for filter 5
-            FFA5: u1,
-            ///  Filter FIFO assignment for filter 6
-            FFA6: u1,
-            ///  Filter FIFO assignment for filter 7
-            FFA7: u1,
-            ///  Filter FIFO assignment for filter 8
-            FFA8: u1,
-            ///  Filter FIFO assignment for filter 9
-            FFA9: u1,
-            ///  Filter FIFO assignment for filter 10
-            FFA10: u1,
-            ///  Filter FIFO assignment for filter 11
-            FFA11: u1,
-            ///  Filter FIFO assignment for filter 12
-            FFA12: u1,
-            ///  Filter FIFO assignment for filter 13
-            FFA13: u1,
-            ///  Filter FIFO assignment for filter 14
-            FFA14: u1,
-            ///  Filter FIFO assignment for filter 15
-            FFA15: u1,
-            ///  Filter FIFO assignment for filter 16
-            FFA16: u1,
-            ///  Filter FIFO assignment for filter 17
-            FFA17: u1,
-            ///  Filter FIFO assignment for filter 18
-            FFA18: u1,
-            ///  Filter FIFO assignment for filter 19
-            FFA19: u1,
-            ///  Filter FIFO assignment for filter 20
-            FFA20: u1,
-            ///  Filter FIFO assignment for filter 21
-            FFA21: u1,
-            ///  Filter FIFO assignment for filter 22
-            FFA22: u1,
-            ///  Filter FIFO assignment for filter 23
-            FFA23: u1,
-            ///  Filter FIFO assignment for filter 24
-            FFA24: u1,
-            ///  Filter FIFO assignment for filter 25
-            FFA25: u1,
-            ///  Filter FIFO assignment for filter 26
-            FFA26: u1,
-            ///  Filter FIFO assignment for filter 27
-            FFA27: u1,
-            padding: u4,
-        }),
-        reserved540: [4]u8,
-        ///  filter activation register
-        FA1R: mmio.Mmio(packed struct(u32) {
-            ///  Filter active
-            FACT0: u1,
-            ///  Filter active
-            FACT1: u1,
-            ///  Filter active
-            FACT2: u1,
-            ///  Filter active
-            FACT3: u1,
-            ///  Filter active
-            FACT4: u1,
-            ///  Filter active
-            FACT5: u1,
-            ///  Filter active
-            FACT6: u1,
-            ///  Filter active
-            FACT7: u1,
-            ///  Filter active
-            FACT8: u1,
-            ///  Filter active
-            FACT9: u1,
-            ///  Filter active
-            FACT10: u1,
-            ///  Filter active
-            FACT11: u1,
-            ///  Filter active
-            FACT12: u1,
-            ///  Filter active
-            FACT13: u1,
-            ///  Filter active
-            FACT14: u1,
-            ///  Filter active
-            FACT15: u1,
-            ///  Filter active
-            FACT16: u1,
-            ///  Filter active
-            FACT17: u1,
-            ///  Filter active
-            FACT18: u1,
-            ///  Filter active
-            FACT19: u1,
-            ///  Filter active
-            FACT20: u1,
-            ///  Filter active
-            FACT21: u1,
-            ///  Filter active
-            FACT22: u1,
-            ///  Filter active
-            FACT23: u1,
-            ///  Filter active
-            FACT24: u1,
-            ///  Filter active
-            FACT25: u1,
-            ///  Filter active
-            FACT26: u1,
-            ///  Filter active
-            FACT27: u1,
-            padding: u4,
-        }),
-        reserved576: [32]u8,
-        ///  Filter bank 0 register 1
-        F0R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 0 register 2
-        F0R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 1 register 1
-        F1R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 1 register 2
-        F1R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 2 register 1
-        F2R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 2 register 2
-        F2R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 3 register 1
-        F3R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 3 register 2
-        F3R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 1
-        F4R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 2
-        F4R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 5 register 1
-        F5R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 5 register 2
-        F5R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 6 register 1
-        F6R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 6 register 2
-        F6R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 7 register 1
-        F7R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 7 register 2
-        F7R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 8 register 1
-        F8R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 8 register 2
-        F8R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 9 register 1
-        F9R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 9 register 2
-        F9R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 10 register 1
-        F10R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 10 register 2
-        F10R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 11 register 1
-        F11R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 11 register 2
-        F11R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 4 register 1
-        F12R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 12 register 2
-        F12R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 13 register 1
-        F13R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 13 register 2
-        F13R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 14 register 1
-        F14R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 14 register 2
-        F14R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 15 register 1
-        F15R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 15 register 2
-        F15R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 16 register 1
-        F16R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 16 register 2
-        F16R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 17 register 1
-        F17R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 17 register 2
-        F17R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 18 register 1
-        F18R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 18 register 2
-        F18R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 19 register 1
-        F19R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 19 register 2
-        F19R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 20 register 1
-        F20R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 20 register 2
-        F20R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 21 register 1
-        F21R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 21 register 2
-        F21R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 22 register 1
-        F22R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 22 register 2
-        F22R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 23 register 1
-        F23R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 23 register 2
-        F23R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 24 register 1
-        F24R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 24 register 2
-        F24R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 25 register 1
-        F25R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 25 register 2
-        F25R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 26 register 1
-        F26R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 26 register 2
-        F26R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 27 register 1
-        F27R1: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-        ///  Filter bank 27 register 2
-        F27R2: mmio.Mmio(packed struct(u32) {
-            ///  Filter bits
-            FB0: u1,
-            ///  Filter bits
-            FB1: u1,
-            ///  Filter bits
-            FB2: u1,
-            ///  Filter bits
-            FB3: u1,
-            ///  Filter bits
-            FB4: u1,
-            ///  Filter bits
-            FB5: u1,
-            ///  Filter bits
-            FB6: u1,
-            ///  Filter bits
-            FB7: u1,
-            ///  Filter bits
-            FB8: u1,
-            ///  Filter bits
-            FB9: u1,
-            ///  Filter bits
-            FB10: u1,
-            ///  Filter bits
-            FB11: u1,
-            ///  Filter bits
-            FB12: u1,
-            ///  Filter bits
-            FB13: u1,
-            ///  Filter bits
-            FB14: u1,
-            ///  Filter bits
-            FB15: u1,
-            ///  Filter bits
-            FB16: u1,
-            ///  Filter bits
-            FB17: u1,
-            ///  Filter bits
-            FB18: u1,
-            ///  Filter bits
-            FB19: u1,
-            ///  Filter bits
-            FB20: u1,
-            ///  Filter bits
-            FB21: u1,
-            ///  Filter bits
-            FB22: u1,
-            ///  Filter bits
-            FB23: u1,
-            ///  Filter bits
-            FB24: u1,
-            ///  Filter bits
-            FB25: u1,
-            ///  Filter bits
-            FB26: u1,
-            ///  Filter bits
-            FB27: u1,
-            ///  Filter bits
-            FB28: u1,
-            ///  Filter bits
-            FB29: u1,
-            ///  Filter bits
-            FB30: u1,
-            ///  Filter bits
-            FB31: u1,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_PWRCLK = extern struct {
-        ///  OTG_FS power and clock gating control register (OTG_FS_PCGCCTL)
-        FS_PCGCCTL: mmio.Mmio(packed struct(u32) {
-            ///  Stop PHY clock
-            STPPCLK: u1,
-            ///  Gate HCLK
-            GATEHCLK: u1,
-            reserved4: u2,
-            ///  PHY Suspended
-            PHYSUSP: u1,
-            padding: u27,
-        }),
-    };
-
-    ///  Digital-to-analog converter
-    pub const DAC = extern struct {
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 enable
-            EN1: u1,
-            ///  DAC channel1 output buffer disable
-            BOFF1: u1,
-            ///  DAC channel1 trigger enable
-            TEN1: u1,
-            ///  DAC channel1 trigger selection
-            TSEL1: u3,
-            ///  DAC channel1 noise/triangle wave generation enable
-            WAVE1: u2,
-            ///  DAC channel1 mask/amplitude selector
-            MAMP1: u4,
-            ///  DAC channel1 DMA enable
-            DMAEN1: u1,
-            ///  DAC channel1 DMA Underrun Interrupt enable
-            DMAUDRIE1: u1,
-            reserved16: u2,
-            ///  DAC channel2 enable
-            EN2: u1,
-            ///  DAC channel2 output buffer disable
-            BOFF2: u1,
-            ///  DAC channel2 trigger enable
-            TEN2: u1,
-            ///  DAC channel2 trigger selection
-            TSEL2: u3,
-            ///  DAC channel2 noise/triangle wave generation enable
-            WAVE2: u2,
-            ///  DAC channel2 mask/amplitude selector
-            MAMP2: u4,
-            ///  DAC channel2 DMA enable
-            DMAEN2: u1,
-            ///  DAC channel2 DMA underrun interrupt enable
-            DMAUDRIE2: u1,
-            padding: u2,
-        }),
-        ///  software trigger register
-        SWTRIGR: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 software trigger
-            SWTRIG1: u1,
-            ///  DAC channel2 software trigger
-            SWTRIG2: u1,
-            padding: u30,
-        }),
-        ///  channel1 12-bit right-aligned data holding register
-        DHR12R1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 12-bit right-aligned data
-            DACC1DHR: u12,
-            padding: u20,
-        }),
-        ///  channel1 12-bit left aligned data holding register
-        DHR12L1: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel1 12-bit left-aligned data
-            DACC1DHR: u12,
-            padding: u16,
-        }),
-        ///  channel1 8-bit right aligned data holding register
-        DHR8R1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 8-bit right-aligned data
-            DACC1DHR: u8,
-            padding: u24,
-        }),
-        ///  channel2 12-bit right aligned data holding register
-        DHR12R2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 12-bit right-aligned data
-            DACC2DHR: u12,
-            padding: u20,
-        }),
-        ///  channel2 12-bit left aligned data holding register
-        DHR12L2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel2 12-bit left-aligned data
-            DACC2DHR: u12,
-            padding: u16,
-        }),
-        ///  channel2 8-bit right-aligned data holding register
-        DHR8R2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 8-bit right-aligned data
-            DACC2DHR: u8,
-            padding: u24,
-        }),
-        ///  Dual DAC 12-bit right-aligned data holding register
-        DHR12RD: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 12-bit right-aligned data
-            DACC1DHR: u12,
-            reserved16: u4,
-            ///  DAC channel2 12-bit right-aligned data
-            DACC2DHR: u12,
-            padding: u4,
-        }),
-        ///  DUAL DAC 12-bit left aligned data holding register
-        DHR12LD: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  DAC channel1 12-bit left-aligned data
-            DACC1DHR: u12,
-            reserved20: u4,
-            ///  DAC channel2 12-bit left-aligned data
-            DACC2DHR: u12,
-        }),
-        ///  DUAL DAC 8-bit right aligned data holding register
-        DHR8RD: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 8-bit right-aligned data
-            DACC1DHR: u8,
-            ///  DAC channel2 8-bit right-aligned data
-            DACC2DHR: u8,
-            padding: u16,
-        }),
-        ///  channel1 data output register
-        DOR1: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel1 data output
-            DACC1DOR: u12,
-            padding: u20,
-        }),
-        ///  channel2 data output register
-        DOR2: mmio.Mmio(packed struct(u32) {
-            ///  DAC channel2 data output
-            DACC2DOR: u12,
-            padding: u20,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            reserved13: u13,
-            ///  DAC channel1 DMA underrun flag
-            DMAUDR1: u1,
-            reserved29: u15,
-            ///  DAC channel2 DMA underrun flag
-            DMAUDR2: u1,
-            padding: u2,
-        }),
-    };
-
-    ///  Power control
-    pub const PWR = extern struct {
-        ///  power control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Low-power deep sleep
-            LPDS: u1,
-            ///  Power down deepsleep
-            PDDS: u1,
-            ///  Clear wakeup flag
-            CWUF: u1,
-            ///  Clear standby flag
-            CSBF: u1,
-            ///  Power voltage detector enable
-            PVDE: u1,
-            ///  PVD level selection
-            PLS: u3,
-            ///  Disable backup domain write protection
-            DBP: u1,
-            ///  Flash power down in Stop mode
-            FPDS: u1,
-            ///  Low-Power Regulator Low Voltage in deepsleep
-            LPLVDS: u1,
-            ///  Main regulator low voltage in deepsleep mode
-            MRLVDS: u1,
-            reserved14: u2,
-            ///  Regulator voltage scaling output selection
-            VOS: u2,
-            ///  Over-drive enable
-            ODEN: u1,
-            ///  Over-drive switching enabled
-            ODSWEN: u1,
-            ///  Under-drive enable in stop mode
-            UDEN: u2,
-            padding: u12,
-        }),
-        ///  power control/status register
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  Wakeup flag
-            WUF: u1,
-            ///  Standby flag
-            SBF: u1,
-            ///  PVD output
-            PVDO: u1,
-            ///  Backup regulator ready
-            BRR: u1,
-            reserved8: u4,
-            ///  Enable WKUP pin
-            EWUP: u1,
-            ///  Backup regulator enable
-            BRE: u1,
-            reserved14: u4,
-            ///  Regulator voltage scaling output selection ready bit
-            VOSRDY: u1,
-            reserved16: u1,
-            ///  Over-drive mode ready
-            ODRDY: u1,
-            ///  Over-drive mode switching ready
-            ODSWRDY: u1,
-            ///  Under-drive ready flag
-            UDRDY: u2,
-            padding: u12,
-        }),
-    };
-
-    ///  Independent watchdog
-    pub const IWDG = extern struct {
-        ///  Key register
-        KR: mmio.Mmio(packed struct(u32) {
-            ///  Key value (write only, read 0000h)
-            KEY: u16,
-            padding: u16,
-        }),
-        ///  Prescaler register
-        PR: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler divider
-            PR: u3,
-            padding: u29,
-        }),
-        ///  Reload register
-        RLR: mmio.Mmio(packed struct(u32) {
-            ///  Watchdog counter reload value
-            RL: u12,
-            padding: u20,
-        }),
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Watchdog prescaler value update
-            PVU: u1,
-            ///  Watchdog counter reload value update
-            RVU: u1,
-            padding: u30,
-        }),
-    };
-
-    ///  Window watchdog
-    pub const WWDG = extern struct {
-        ///  Control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  7-bit counter (MSB to LSB)
-            T: u7,
-            ///  Activation bit
-            WDGA: u1,
-            padding: u24,
-        }),
-        ///  Configuration register
-        CFR: mmio.Mmio(packed struct(u32) {
-            ///  7-bit window value
-            W: u7,
-            ///  Timer base
-            WDGTB0: u1,
-            ///  Timer base
-            WDGTB1: u1,
-            ///  Early wakeup interrupt
-            EWI: u1,
-            padding: u22,
-        }),
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Early wakeup interrupt flag
-            EWIF: u1,
-            padding: u31,
-        }),
-    };
-
-    ///  Real-time clock
-    pub const RTC = extern struct {
-        ///  time register
-        TR: mmio.Mmio(packed struct(u32) {
-            ///  Second units in BCD format
-            SU: u4,
-            ///  Second tens in BCD format
-            ST: u3,
-            reserved8: u1,
-            ///  Minute units in BCD format
-            MNU: u4,
-            ///  Minute tens in BCD format
-            MNT: u3,
-            reserved16: u1,
-            ///  Hour units in BCD format
-            HU: u4,
-            ///  Hour tens in BCD format
-            HT: u2,
-            ///  AM/PM notation
-            PM: u1,
-            padding: u9,
-        }),
-        ///  date register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Date units in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            reserved8: u2,
-            ///  Month units in BCD format
-            MU: u4,
-            ///  Month tens in BCD format
-            MT: u1,
-            ///  Week day units
-            WDU: u3,
-            ///  Year units in BCD format
-            YU: u4,
-            ///  Year tens in BCD format
-            YT: u4,
-            padding: u8,
-        }),
-        ///  control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Wakeup clock selection
-            WCKSEL: u3,
-            ///  Time-stamp event active edge
-            TSEDGE: u1,
-            ///  Reference clock detection enable (50 or 60 Hz)
-            REFCKON: u1,
-            reserved6: u1,
-            ///  Hour format
-            FMT: u1,
-            ///  Coarse digital calibration enable
-            DCE: u1,
-            ///  Alarm A enable
-            ALRAE: u1,
-            ///  Alarm B enable
-            ALRBE: u1,
-            ///  Wakeup timer enable
-            WUTE: u1,
-            ///  Time stamp enable
-            TSE: u1,
-            ///  Alarm A interrupt enable
-            ALRAIE: u1,
-            ///  Alarm B interrupt enable
-            ALRBIE: u1,
-            ///  Wakeup timer interrupt enable
-            WUTIE: u1,
-            ///  Time-stamp interrupt enable
-            TSIE: u1,
-            ///  Add 1 hour (summer time change)
-            ADD1H: u1,
-            ///  Subtract 1 hour (winter time change)
-            SUB1H: u1,
-            ///  Backup
-            BKP: u1,
-            reserved20: u1,
-            ///  Output polarity
-            POL: u1,
-            ///  Output selection
-            OSEL: u2,
-            ///  Calibration output enable
-            COE: u1,
-            padding: u8,
-        }),
-        ///  initialization and status register
-        ISR: mmio.Mmio(packed struct(u32) {
-            ///  Alarm A write flag
-            ALRAWF: u1,
-            ///  Alarm B write flag
-            ALRBWF: u1,
-            ///  Wakeup timer write flag
-            WUTWF: u1,
-            ///  Shift operation pending
-            SHPF: u1,
-            ///  Initialization status flag
-            INITS: u1,
-            ///  Registers synchronization flag
-            RSF: u1,
-            ///  Initialization flag
-            INITF: u1,
-            ///  Initialization mode
-            INIT: u1,
-            ///  Alarm A flag
-            ALRAF: u1,
-            ///  Alarm B flag
-            ALRBF: u1,
-            ///  Wakeup timer flag
-            WUTF: u1,
-            ///  Time-stamp flag
-            TSF: u1,
-            ///  Time-stamp overflow flag
-            TSOVF: u1,
-            ///  Tamper detection flag
-            TAMP1F: u1,
-            ///  TAMPER2 detection flag
-            TAMP2F: u1,
-            reserved16: u1,
-            ///  Recalibration pending Flag
-            RECALPF: u1,
-            padding: u15,
-        }),
-        ///  prescaler register
-        PRER: mmio.Mmio(packed struct(u32) {
-            ///  Synchronous prescaler factor
-            PREDIV_S: u15,
-            reserved16: u1,
-            ///  Asynchronous prescaler factor
-            PREDIV_A: u7,
-            padding: u9,
-        }),
-        ///  wakeup timer register
-        WUTR: mmio.Mmio(packed struct(u32) {
-            ///  Wakeup auto-reload value bits
-            WUT: u16,
-            padding: u16,
-        }),
-        ///  calibration register
-        CALIBR: mmio.Mmio(packed struct(u32) {
-            ///  Digital calibration
-            DC: u5,
-            reserved7: u2,
-            ///  Digital calibration sign
-            DCS: u1,
-            padding: u24,
-        }),
-        ///  alarm A register
-        ALRMAR: mmio.Mmio(packed struct(u32) {
-            ///  Second units in BCD format
-            SU: u4,
-            ///  Second tens in BCD format
-            ST: u3,
-            ///  Alarm A seconds mask
-            MSK1: u1,
-            ///  Minute units in BCD format
-            MNU: u4,
-            ///  Minute tens in BCD format
-            MNT: u3,
-            ///  Alarm A minutes mask
-            MSK2: u1,
-            ///  Hour units in BCD format
-            HU: u4,
-            ///  Hour tens in BCD format
-            HT: u2,
-            ///  AM/PM notation
-            PM: u1,
-            ///  Alarm A hours mask
-            MSK3: u1,
-            ///  Date units or day in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            ///  Week day selection
-            WDSEL: u1,
-            ///  Alarm A date mask
-            MSK4: u1,
-        }),
-        ///  alarm B register
-        ALRMBR: mmio.Mmio(packed struct(u32) {
-            ///  Second units in BCD format
-            SU: u4,
-            ///  Second tens in BCD format
-            ST: u3,
-            ///  Alarm B seconds mask
-            MSK1: u1,
-            ///  Minute units in BCD format
-            MNU: u4,
-            ///  Minute tens in BCD format
-            MNT: u3,
-            ///  Alarm B minutes mask
-            MSK2: u1,
-            ///  Hour units in BCD format
-            HU: u4,
-            ///  Hour tens in BCD format
-            HT: u2,
-            ///  AM/PM notation
-            PM: u1,
-            ///  Alarm B hours mask
-            MSK3: u1,
-            ///  Date units or day in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            ///  Week day selection
-            WDSEL: u1,
-            ///  Alarm B date mask
-            MSK4: u1,
-        }),
-        ///  write protection register
-        WPR: mmio.Mmio(packed struct(u32) {
-            ///  Write protection key
-            KEY: u8,
-            padding: u24,
-        }),
-        ///  sub second register
-        SSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub second value
-            SS: u16,
-            padding: u16,
-        }),
-        ///  shift control register
-        SHIFTR: mmio.Mmio(packed struct(u32) {
-            ///  Subtract a fraction of a second
-            SUBFS: u15,
-            reserved31: u16,
-            ///  Add one second
-            ADD1S: u1,
-        }),
-        ///  time stamp time register
-        TSTR: mmio.Mmio(packed struct(u32) {
-            ///  Tamper 1 detection enable
-            TAMP1E: u1,
-            ///  Active level for tamper 1
-            TAMP1TRG: u1,
-            ///  Tamper interrupt enable
-            TAMPIE: u1,
-            reserved16: u13,
-            ///  TAMPER1 mapping
-            TAMP1INSEL: u1,
-            ///  TIMESTAMP mapping
-            TSINSEL: u1,
-            ///  AFO_ALARM output type
-            ALARMOUTTYPE: u1,
-            padding: u13,
-        }),
-        ///  time stamp date register
-        TSDR: mmio.Mmio(packed struct(u32) {
-            ///  Date units in BCD format
-            DU: u4,
-            ///  Date tens in BCD format
-            DT: u2,
-            reserved8: u2,
-            ///  Month units in BCD format
-            MU: u4,
-            ///  Month tens in BCD format
-            MT: u1,
-            ///  Week day units
-            WDU: u3,
-            padding: u16,
-        }),
-        ///  timestamp sub second register
-        TSSSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub second value
-            SS: u16,
-            padding: u16,
-        }),
-        ///  calibration register
-        CALR: mmio.Mmio(packed struct(u32) {
-            ///  Calibration minus
-            CALM: u9,
-            reserved13: u4,
-            ///  Use a 16-second calibration cycle period
-            CALW16: u1,
-            ///  Use an 8-second calibration cycle period
-            CALW8: u1,
-            ///  Increase frequency of RTC by 488.5 ppm
-            CALP: u1,
-            padding: u16,
-        }),
-        ///  tamper and alternate function configuration register
-        TAFCR: mmio.Mmio(packed struct(u32) {
-            ///  Tamper 1 detection enable
-            TAMP1E: u1,
-            ///  Active level for tamper 1
-            TAMP1TRG: u1,
-            ///  Tamper interrupt enable
-            TAMPIE: u1,
-            ///  Tamper 2 detection enable
-            TAMP2E: u1,
-            ///  Active level for tamper 2
-            TAMP2TRG: u1,
-            reserved7: u2,
-            ///  Activate timestamp on tamper detection event
-            TAMPTS: u1,
-            ///  Tamper sampling frequency
-            TAMPFREQ: u3,
-            ///  Tamper filter count
-            TAMPFLT: u2,
-            ///  Tamper precharge duration
-            TAMPPRCH: u2,
-            ///  TAMPER pull-up disable
-            TAMPPUDIS: u1,
-            ///  TAMPER1 mapping
-            TAMP1INSEL: u1,
-            ///  TIMESTAMP mapping
-            TSINSEL: u1,
-            ///  AFO_ALARM output type
-            ALARMOUTTYPE: u1,
-            padding: u13,
-        }),
-        ///  alarm A sub second register
-        ALRMASSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub seconds value
-            SS: u15,
-            reserved24: u9,
-            ///  Mask the most-significant bits starting at this bit
-            MASKSS: u4,
-            padding: u4,
-        }),
-        ///  alarm B sub second register
-        ALRMBSSR: mmio.Mmio(packed struct(u32) {
-            ///  Sub seconds value
-            SS: u15,
-            reserved24: u9,
-            ///  Mask the most-significant bits starting at this bit
-            MASKSS: u4,
-            padding: u4,
-        }),
-        reserved80: [4]u8,
-        ///  backup register
-        BKP0R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP1R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP2R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP3R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP4R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP5R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP6R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP7R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP8R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP9R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP10R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP11R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP12R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP13R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP14R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP15R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP16R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP17R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP18R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-        ///  backup register
-        BKP19R: mmio.Mmio(packed struct(u32) {
-            ///  BKP
-            BKP: u32,
-        }),
-    };
-
-    ///  Universal synchronous asynchronous receiver transmitter
-    pub const UART4 = extern struct {
-        ///  Status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Parity error
-            PE: u1,
-            ///  Framing error
-            FE: u1,
-            ///  Noise detected flag
-            NF: u1,
-            ///  Overrun error
-            ORE: u1,
-            ///  IDLE line detected
-            IDLE: u1,
-            ///  Read data register not empty
-            RXNE: u1,
-            ///  Transmission complete
-            TC: u1,
-            ///  Transmit data register empty
-            TXE: u1,
-            ///  LIN break detection flag
-            LBD: u1,
-            padding: u23,
-        }),
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data value
-            DR: u9,
-            padding: u23,
-        }),
-        ///  Baud rate register
-        BRR: mmio.Mmio(packed struct(u32) {
-            ///  fraction of USARTDIV
-            DIV_Fraction: u4,
-            ///  mantissa of USARTDIV
-            DIV_Mantissa: u12,
-            padding: u16,
-        }),
-        ///  Control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Send break
-            SBK: u1,
-            ///  Receiver wakeup
-            RWU: u1,
-            ///  Receiver enable
-            RE: u1,
-            ///  Transmitter enable
-            TE: u1,
-            ///  IDLE interrupt enable
-            IDLEIE: u1,
-            ///  RXNE interrupt enable
-            RXNEIE: u1,
-            ///  Transmission complete interrupt enable
-            TCIE: u1,
-            ///  TXE interrupt enable
-            TXEIE: u1,
-            ///  PE interrupt enable
-            PEIE: u1,
-            ///  Parity selection
-            PS: u1,
-            ///  Parity control enable
-            PCE: u1,
-            ///  Wakeup method
-            WAKE: u1,
-            ///  Word length
-            M: u1,
-            ///  USART enable
-            UE: u1,
-            reserved15: u1,
-            ///  Oversampling mode
-            OVER8: u1,
-            padding: u16,
-        }),
-        ///  Control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Address of the USART node
-            ADD: u4,
-            reserved5: u1,
-            ///  lin break detection length
-            LBDL: u1,
-            ///  LIN break detection interrupt enable
-            LBDIE: u1,
-            reserved12: u5,
-            ///  STOP bits
-            STOP: u2,
-            ///  LIN mode enable
-            LINEN: u1,
-            padding: u17,
-        }),
-        ///  Control register 3
-        CR3: mmio.Mmio(packed struct(u32) {
-            ///  Error interrupt enable
-            EIE: u1,
-            ///  IrDA mode enable
-            IREN: u1,
-            ///  IrDA low-power
-            IRLP: u1,
-            ///  Half-duplex selection
-            HDSEL: u1,
-            reserved6: u2,
-            ///  DMA enable receiver
-            DMAR: u1,
-            ///  DMA enable transmitter
-            DMAT: u1,
-            reserved11: u3,
-            ///  One sample bit method enable
-            ONEBIT: u1,
-            padding: u20,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_DEVICE = extern struct {
-        ///  OTG_FS device configuration register (OTG_FS_DCFG)
-        FS_DCFG: mmio.Mmio(packed struct(u32) {
-            ///  Device speed
-            DSPD: u2,
-            ///  Non-zero-length status OUT handshake
-            NZLSOHSK: u1,
-            reserved4: u1,
-            ///  Device address
-            DAD: u7,
-            ///  Periodic frame interval
-            PFIVL: u2,
-            padding: u19,
-        }),
-        ///  OTG_FS device control register (OTG_FS_DCTL)
-        FS_DCTL: mmio.Mmio(packed struct(u32) {
-            ///  Remote wakeup signaling
-            RWUSIG: u1,
-            ///  Soft disconnect
-            SDIS: u1,
-            ///  Global IN NAK status
-            GINSTS: u1,
-            ///  Global OUT NAK status
-            GONSTS: u1,
-            ///  Test control
-            TCTL: u3,
-            ///  Set global IN NAK
-            SGINAK: u1,
-            ///  Clear global IN NAK
-            CGINAK: u1,
-            ///  Set global OUT NAK
-            SGONAK: u1,
-            ///  Clear global OUT NAK
-            CGONAK: u1,
-            ///  Power-on programming done
-            POPRGDNE: u1,
-            padding: u20,
-        }),
-        ///  OTG_FS device status register (OTG_FS_DSTS)
-        FS_DSTS: mmio.Mmio(packed struct(u32) {
-            ///  Suspend status
-            SUSPSTS: u1,
-            ///  Enumerated speed
-            ENUMSPD: u2,
-            ///  Erratic error
-            EERR: u1,
-            reserved8: u4,
-            ///  Frame number of the received SOF
-            FNSOF: u14,
-            padding: u10,
-        }),
-        reserved16: [4]u8,
-        ///  OTG_FS device IN endpoint common interrupt mask register (OTG_FS_DIEPMSK)
-        FS_DIEPMSK: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  Timeout condition mask (Non-isochronous endpoints)
-            TOM: u1,
-            ///  IN token received when TxFIFO empty mask
-            ITTXFEMSK: u1,
-            ///  IN token received with EP mismatch mask
-            INEPNMM: u1,
-            ///  IN endpoint NAK effective mask
-            INEPNEM: u1,
-            padding: u25,
-        }),
-        ///  OTG_FS device OUT endpoint common interrupt mask register (OTG_FS_DOEPMSK)
-        FS_DOEPMSK: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed interrupt mask
-            XFRCM: u1,
-            ///  Endpoint disabled interrupt mask
-            EPDM: u1,
-            reserved3: u1,
-            ///  SETUP phase done mask
-            STUPM: u1,
-            ///  OUT token received when endpoint disabled mask
-            OTEPDM: u1,
-            padding: u27,
-        }),
-        ///  OTG_FS device all endpoints interrupt register (OTG_FS_DAINT)
-        FS_DAINT: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint interrupt bits
-            IEPINT: u16,
-            ///  OUT endpoint interrupt bits
-            OEPINT: u16,
-        }),
-        ///  OTG_FS all endpoints interrupt mask register (OTG_FS_DAINTMSK)
-        FS_DAINTMSK: mmio.Mmio(packed struct(u32) {
-            ///  IN EP interrupt mask bits
-            IEPM: u16,
-            ///  OUT endpoint interrupt bits
-            OEPINT: u16,
-        }),
-        reserved40: [8]u8,
-        ///  OTG_FS device VBUS discharge time register
-        DVBUSDIS: mmio.Mmio(packed struct(u32) {
-            ///  Device VBUS discharge time
-            VBUSDT: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS device VBUS pulsing time register
-        DVBUSPULSE: mmio.Mmio(packed struct(u32) {
-            ///  Device VBUS pulsing time
-            DVBUSP: u12,
-            padding: u20,
-        }),
-        reserved52: [4]u8,
-        ///  OTG_FS device IN endpoint FIFO empty interrupt mask register
-        DIEPEMPMSK: mmio.Mmio(packed struct(u32) {
-            ///  IN EP Tx FIFO empty interrupt mask bits
-            INEPTXFEM: u16,
-            padding: u16,
-        }),
-        reserved256: [200]u8,
-        ///  OTG_FS device control IN endpoint 0 control register (OTG_FS_DIEPCTL0)
-        FS_DIEPCTL0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u2,
-            reserved15: u13,
-            ///  USB active endpoint
-            USBAEP: u1,
-            reserved17: u1,
-            ///  NAK status
-            NAKSTS: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            reserved21: u1,
-            ///  STALL handshake
-            STALL: u1,
-            ///  TxFIFO number
-            TXFNUM: u4,
-            ///  Clear NAK
-            CNAK: u1,
-            ///  Set NAK
-            SNAK: u1,
-            reserved30: u2,
-            ///  Endpoint disable
-            EPDIS: u1,
-            ///  Endpoint enable
-            EPENA: u1,
-        }),
-        reserved264: [4]u8,
-        ///  device endpoint-x interrupt register
-        DIEPINT0: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved272: [4]u8,
-        ///  device endpoint-0 transfer size register
-        DIEPTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u7,
-            reserved19: u12,
-            ///  Packet count
-            PKTCNT: u2,
-            padding: u11,
-        }),
-        reserved280: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS0: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved288: [4]u8,
-        ///  OTG device endpoint-1 control register
-        DIEPCTL1: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            reserved21: u1,
-            ///  Stall
-            Stall: u1,
-            ///  TXFNUM
-            TXFNUM: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM/SD1PID
-            SODDFRM_SD1PID: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved296: [4]u8,
-        ///  device endpoint-1 interrupt register
-        DIEPINT1: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved304: [4]u8,
-        ///  device endpoint-1 transfer size register
-        DIEPTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        reserved312: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS1: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved320: [4]u8,
-        ///  OTG device endpoint-2 control register
-        DIEPCTL2: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            reserved21: u1,
-            ///  Stall
-            Stall: u1,
-            ///  TXFNUM
-            TXFNUM: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved328: [4]u8,
-        ///  device endpoint-2 interrupt register
-        DIEPINT2: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved336: [4]u8,
-        ///  device endpoint-2 transfer size register
-        DIEPTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        reserved344: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS2: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved352: [4]u8,
-        ///  OTG device endpoint-3 control register
-        DIEPCTL3: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            reserved21: u1,
-            ///  Stall
-            Stall: u1,
-            ///  TXFNUM
-            TXFNUM: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved360: [4]u8,
-        ///  device endpoint-3 interrupt register
-        DIEPINT3: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  TOC
-            TOC: u1,
-            ///  ITTXFE
-            ITTXFE: u1,
-            reserved6: u1,
-            ///  INEPNE
-            INEPNE: u1,
-            ///  TXFE
-            TXFE: u1,
-            padding: u24,
-        }),
-        reserved368: [4]u8,
-        ///  device endpoint-3 transfer size register
-        DIEPTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Multi count
-            MCNT: u2,
-            padding: u1,
-        }),
-        reserved376: [4]u8,
-        ///  OTG_FS device IN endpoint transmit FIFO status register
-        DTXFSTS3: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint TxFIFO space available
-            INEPTFSAV: u16,
-            padding: u16,
-        }),
-        reserved768: [388]u8,
-        ///  device endpoint-0 control register
-        DOEPCTL0: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u2,
-            reserved15: u13,
-            ///  USBAEP
-            USBAEP: u1,
-            reserved17: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            reserved30: u2,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved776: [4]u8,
-        ///  device endpoint-0 interrupt register
-        DOEPINT0: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved784: [4]u8,
-        ///  device OUT endpoint-0 transfer size register
-        DOEPTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u7,
-            reserved19: u12,
-            ///  Packet count
-            PKTCNT: u1,
-            reserved29: u9,
-            ///  SETUP packet count
-            STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved800: [12]u8,
-        ///  device endpoint-1 control register
-        DOEPCTL1: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved808: [4]u8,
-        ///  device endpoint-1 interrupt register
-        DOEPINT1: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved816: [4]u8,
-        ///  device OUT endpoint-1 transfer size register
-        DOEPTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved832: [12]u8,
-        ///  device endpoint-2 control register
-        DOEPCTL2: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved840: [4]u8,
-        ///  device endpoint-2 interrupt register
-        DOEPINT2: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved848: [4]u8,
-        ///  device OUT endpoint-2 transfer size register
-        DOEPTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-        reserved864: [12]u8,
-        ///  device endpoint-3 control register
-        DOEPCTL3: mmio.Mmio(packed struct(u32) {
-            ///  MPSIZ
-            MPSIZ: u11,
-            reserved15: u4,
-            ///  USBAEP
-            USBAEP: u1,
-            ///  EONUM/DPID
-            EONUM_DPID: u1,
-            ///  NAKSTS
-            NAKSTS: u1,
-            ///  EPTYP
-            EPTYP: u2,
-            ///  SNPM
-            SNPM: u1,
-            ///  Stall
-            Stall: u1,
-            reserved26: u4,
-            ///  CNAK
-            CNAK: u1,
-            ///  SNAK
-            SNAK: u1,
-            ///  SD0PID/SEVNFRM
-            SD0PID_SEVNFRM: u1,
-            ///  SODDFRM
-            SODDFRM: u1,
-            ///  EPDIS
-            EPDIS: u1,
-            ///  EPENA
-            EPENA: u1,
-        }),
-        reserved872: [4]u8,
-        ///  device endpoint-3 interrupt register
-        DOEPINT3: mmio.Mmio(packed struct(u32) {
-            ///  XFRC
-            XFRC: u1,
-            ///  EPDISD
-            EPDISD: u1,
-            reserved3: u1,
-            ///  STUP
-            STUP: u1,
-            ///  OTEPDIS
-            OTEPDIS: u1,
-            reserved6: u1,
-            ///  B2BSTUP
-            B2BSTUP: u1,
-            padding: u25,
-        }),
-        reserved880: [4]u8,
-        ///  device OUT endpoint-3 transfer size register
-        DOEPTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Received data PID/SETUP packet count
-            RXDPID_STUPCNT: u2,
-            padding: u1,
-        }),
-    };
-
-    ///  Common ADC registers
-    pub const C_ADC = extern struct {
-        ///  ADC Common status register
-        CSR: mmio.Mmio(packed struct(u32) {
-            ///  Analog watchdog flag of ADC 1
-            AWD1: u1,
-            ///  End of conversion of ADC 1
-            EOC1: u1,
-            ///  Injected channel end of conversion of ADC 1
-            JEOC1: u1,
-            ///  Injected channel Start flag of ADC 1
-            JSTRT1: u1,
-            ///  Regular channel Start flag of ADC 1
-            STRT1: u1,
-            ///  Overrun flag of ADC 1
-            OVR1: u1,
-            reserved8: u2,
-            ///  Analog watchdog flag of ADC 2
-            AWD2: u1,
-            ///  End of conversion of ADC 2
-            EOC2: u1,
-            ///  Injected channel end of conversion of ADC 2
-            JEOC2: u1,
-            ///  Injected channel Start flag of ADC 2
-            JSTRT2: u1,
-            ///  Regular channel Start flag of ADC 2
-            STRT2: u1,
-            ///  Overrun flag of ADC 2
-            OVR2: u1,
-            reserved16: u2,
-            ///  Analog watchdog flag of ADC 3
-            AWD3: u1,
-            ///  End of conversion of ADC 3
-            EOC3: u1,
-            ///  Injected channel end of conversion of ADC 3
-            JEOC3: u1,
-            ///  Injected channel Start flag of ADC 3
-            JSTRT3: u1,
-            ///  Regular channel Start flag of ADC 3
-            STRT3: u1,
-            ///  Overrun flag of ADC3
-            OVR3: u1,
-            padding: u10,
-        }),
-        ///  ADC common control register
-        CCR: mmio.Mmio(packed struct(u32) {
-            ///  Multi ADC mode selection
-            MULT: u5,
-            reserved8: u3,
-            ///  Delay between 2 sampling phases
-            DELAY: u4,
-            reserved13: u1,
-            ///  DMA disable selection for multi-ADC mode
-            DDS: u1,
-            ///  Direct memory access mode for multi ADC mode
-            DMA: u2,
-            ///  ADC prescaler
-            ADCPRE: u2,
-            reserved22: u4,
-            ///  VBAT enable
-            VBATE: u1,
-            ///  Temperature sensor and VREFINT enable
-            TSVREFE: u1,
-            padding: u8,
-        }),
-        ///  ADC common regular data register for dual and triple modes
-        CDR: mmio.Mmio(packed struct(u32) {
-            ///  1st data item of a pair of regular conversions
-            DATA1: u16,
-            ///  2nd data item of a pair of regular conversions
-            DATA2: u16,
-        }),
-    };
-
-    ///  Advanced-timers
-    pub const TIM1 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/compare preloaded control
-            CCPC: u1,
-            reserved2: u1,
-            ///  Capture/compare control update selection
-            CCUS: u1,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            ///  Output Idle state 1
-            OIS1: u1,
-            ///  Output Idle state 1
-            OIS1N: u1,
-            ///  Output Idle state 2
-            OIS2: u1,
-            ///  Output Idle state 2
-            OIS2N: u1,
-            ///  Output Idle state 3
-            OIS3: u1,
-            ///  Output Idle state 3
-            OIS3N: u1,
-            ///  Output Idle state 4
-            OIS4: u1,
-            padding: u17,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            padding: u16,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            ///  COM interrupt enable
-            COMIE: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            ///  Break interrupt enable
-            BIE: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            ///  COM DMA request enable
-            COMDE: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            ///  COM interrupt flag
-            COMIF: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            ///  Break interrupt flag
-            BIF: u1,
-            reserved9: u1,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            padding: u19,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            ///  Capture/Compare control update generation
-            COMG: u1,
-            ///  Trigger generation
-            TG: u1,
-            ///  Break generation
-            BG: u1,
-            padding: u24,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            ///  Output Compare 1 clear enable
-            OC1CE: u1,
-            ///  Capture/Compare 2 selection
-            CC2S: u2,
-            ///  Output Compare 2 fast enable
-            OC2FE: u1,
-            ///  Output Compare 2 preload enable
-            OC2PE: u1,
-            ///  Output Compare 2 mode
-            OC2M: u3,
-            ///  Output Compare 2 clear enable
-            OC2CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare mode register 2 (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 3 selection
-            CC3S: u2,
-            ///  Output compare 3 fast enable
-            OC3FE: u1,
-            ///  Output compare 3 preload enable
-            OC3PE: u1,
-            ///  Output compare 3 mode
-            OC3M: u3,
-            ///  Output compare 3 clear enable
-            OC3CE: u1,
-            ///  Capture/Compare 4 selection
-            CC4S: u2,
-            ///  Output compare 4 fast enable
-            OC4FE: u1,
-            ///  Output compare 4 preload enable
-            OC4PE: u1,
-            ///  Output compare 4 mode
-            OC4M: u3,
-            ///  Output compare 4 clear enable
-            OC4CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            ///  Capture/Compare 1 complementary output enable
-            CC1NE: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            ///  Capture/Compare 2 complementary output enable
-            CC2NE: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            ///  Capture/Compare 3 complementary output enable
-            CC3NE: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            padding: u18,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        ///  repetition counter register
-        RCR: mmio.Mmio(packed struct(u32) {
-            ///  Repetition counter value
-            REP: u8,
-            padding: u24,
-        }),
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 2 value
-            CCR2: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare value
-            CCR3: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare value
-            CCR4: u16,
-            padding: u16,
-        }),
-        ///  break and dead-time register
-        BDTR: mmio.Mmio(packed struct(u32) {
-            ///  Dead-time generator setup
-            DTG: u8,
-            ///  Lock configuration
-            LOCK: u2,
-            ///  Off-state selection for Idle mode
-            OSSI: u1,
-            ///  Off-state selection for Run mode
-            OSSR: u1,
-            ///  Break enable
-            BKE: u1,
-            ///  Break polarity
-            BKP: u1,
-            ///  Automatic output enable
-            AOE: u1,
-            ///  Main output enable
-            MOE: u1,
-            padding: u16,
-        }),
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_HOST = extern struct {
-        ///  OTG_FS host configuration register (OTG_FS_HCFG)
-        FS_HCFG: mmio.Mmio(packed struct(u32) {
-            ///  FS/LS PHY clock select
-            FSLSPCS: u2,
-            ///  FS- and LS-only support
-            FSLSS: u1,
-            padding: u29,
-        }),
-        ///  OTG_FS Host frame interval register
-        HFIR: mmio.Mmio(packed struct(u32) {
-            ///  Frame interval
-            FRIVL: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS host frame number/frame time remaining register (OTG_FS_HFNUM)
-        FS_HFNUM: mmio.Mmio(packed struct(u32) {
-            ///  Frame number
-            FRNUM: u16,
-            ///  Frame time remaining
-            FTREM: u16,
-        }),
-        reserved16: [4]u8,
-        ///  OTG_FS_Host periodic transmit FIFO/queue status register (OTG_FS_HPTXSTS)
-        FS_HPTXSTS: mmio.Mmio(packed struct(u32) {
-            ///  Periodic transmit data FIFO space available
-            PTXFSAVL: u16,
-            ///  Periodic transmit request queue space available
-            PTXQSAV: u8,
-            ///  Top of the periodic transmit request queue
-            PTXQTOP: u8,
-        }),
-        ///  OTG_FS Host all channels interrupt register
-        HAINT: mmio.Mmio(packed struct(u32) {
-            ///  Channel interrupts
-            HAINT: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS host all channels interrupt mask register
-        HAINTMSK: mmio.Mmio(packed struct(u32) {
-            ///  Channel interrupt mask
-            HAINTM: u16,
-            padding: u16,
-        }),
-        reserved64: [36]u8,
-        ///  OTG_FS host port control and status register (OTG_FS_HPRT)
-        FS_HPRT: mmio.Mmio(packed struct(u32) {
-            ///  Port connect status
-            PCSTS: u1,
-            ///  Port connect detected
-            PCDET: u1,
-            ///  Port enable
-            PENA: u1,
-            ///  Port enable/disable change
-            PENCHNG: u1,
-            ///  Port overcurrent active
-            POCA: u1,
-            ///  Port overcurrent change
-            POCCHNG: u1,
-            ///  Port resume
-            PRES: u1,
-            ///  Port suspend
-            PSUSP: u1,
-            ///  Port reset
-            PRST: u1,
-            reserved10: u1,
-            ///  Port line status
-            PLSTS: u2,
-            ///  Port power
-            PPWR: u1,
-            ///  Port test control
-            PTCTL: u4,
-            ///  Port speed
-            PSPD: u2,
-            padding: u13,
-        }),
-        reserved256: [188]u8,
-        ///  OTG_FS host channel-0 characteristics register (OTG_FS_HCCHAR0)
-        FS_HCCHAR0: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved264: [4]u8,
-        ///  OTG_FS host channel-0 interrupt register (OTG_FS_HCINT0)
-        FS_HCINT0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-0 mask register (OTG_FS_HCINTMSK0)
-        FS_HCINTMSK0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-0 transfer size register
-        FS_HCTSIZ0: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved288: [12]u8,
-        ///  OTG_FS host channel-1 characteristics register (OTG_FS_HCCHAR1)
-        FS_HCCHAR1: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved296: [4]u8,
-        ///  OTG_FS host channel-1 interrupt register (OTG_FS_HCINT1)
-        FS_HCINT1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-1 mask register (OTG_FS_HCINTMSK1)
-        FS_HCINTMSK1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-1 transfer size register
-        FS_HCTSIZ1: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved320: [12]u8,
-        ///  OTG_FS host channel-2 characteristics register (OTG_FS_HCCHAR2)
-        FS_HCCHAR2: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved328: [4]u8,
-        ///  OTG_FS host channel-2 interrupt register (OTG_FS_HCINT2)
-        FS_HCINT2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-2 mask register (OTG_FS_HCINTMSK2)
-        FS_HCINTMSK2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-2 transfer size register
-        FS_HCTSIZ2: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved352: [12]u8,
-        ///  OTG_FS host channel-3 characteristics register (OTG_FS_HCCHAR3)
-        FS_HCCHAR3: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved360: [4]u8,
-        ///  OTG_FS host channel-3 interrupt register (OTG_FS_HCINT3)
-        FS_HCINT3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-3 mask register (OTG_FS_HCINTMSK3)
-        FS_HCINTMSK3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-3 transfer size register
-        FS_HCTSIZ3: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved384: [12]u8,
-        ///  OTG_FS host channel-4 characteristics register (OTG_FS_HCCHAR4)
-        FS_HCCHAR4: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved392: [4]u8,
-        ///  OTG_FS host channel-4 interrupt register (OTG_FS_HCINT4)
-        FS_HCINT4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-4 mask register (OTG_FS_HCINTMSK4)
-        FS_HCINTMSK4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-x transfer size register
-        FS_HCTSIZ4: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved416: [12]u8,
-        ///  OTG_FS host channel-5 characteristics register (OTG_FS_HCCHAR5)
-        FS_HCCHAR5: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved424: [4]u8,
-        ///  OTG_FS host channel-5 interrupt register (OTG_FS_HCINT5)
-        FS_HCINT5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-5 mask register (OTG_FS_HCINTMSK5)
-        FS_HCINTMSK5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-5 transfer size register
-        FS_HCTSIZ5: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved448: [12]u8,
-        ///  OTG_FS host channel-6 characteristics register (OTG_FS_HCCHAR6)
-        FS_HCCHAR6: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved456: [4]u8,
-        ///  OTG_FS host channel-6 interrupt register (OTG_FS_HCINT6)
-        FS_HCINT6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-6 mask register (OTG_FS_HCINTMSK6)
-        FS_HCINTMSK6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-6 transfer size register
-        FS_HCTSIZ6: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-        reserved480: [12]u8,
-        ///  OTG_FS host channel-7 characteristics register (OTG_FS_HCCHAR7)
-        FS_HCCHAR7: mmio.Mmio(packed struct(u32) {
-            ///  Maximum packet size
-            MPSIZ: u11,
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Endpoint direction
-            EPDIR: u1,
-            reserved17: u1,
-            ///  Low-speed device
-            LSDEV: u1,
-            ///  Endpoint type
-            EPTYP: u2,
-            ///  Multicount
-            MCNT: u2,
-            ///  Device address
-            DAD: u7,
-            ///  Odd frame
-            ODDFRM: u1,
-            ///  Channel disable
-            CHDIS: u1,
-            ///  Channel enable
-            CHENA: u1,
-        }),
-        reserved488: [4]u8,
-        ///  OTG_FS host channel-7 interrupt register (OTG_FS_HCINT7)
-        FS_HCINT7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed
-            XFRC: u1,
-            ///  Channel halted
-            CHH: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt
-            STALL: u1,
-            ///  NAK response received interrupt
-            NAK: u1,
-            ///  ACK response received/transmitted interrupt
-            ACK: u1,
-            reserved7: u1,
-            ///  Transaction error
-            TXERR: u1,
-            ///  Babble error
-            BBERR: u1,
-            ///  Frame overrun
-            FRMOR: u1,
-            ///  Data toggle error
-            DTERR: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-7 mask register (OTG_FS_HCINTMSK7)
-        FS_HCINTMSK7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer completed mask
-            XFRCM: u1,
-            ///  Channel halted mask
-            CHHM: u1,
-            reserved3: u1,
-            ///  STALL response received interrupt mask
-            STALLM: u1,
-            ///  NAK response received interrupt mask
-            NAKM: u1,
-            ///  ACK response received/transmitted interrupt mask
-            ACKM: u1,
-            ///  response received interrupt mask
-            NYET: u1,
-            ///  Transaction error mask
-            TXERRM: u1,
-            ///  Babble error mask
-            BBERRM: u1,
-            ///  Frame overrun mask
-            FRMORM: u1,
-            ///  Data toggle error mask
-            DTERRM: u1,
-            padding: u21,
-        }),
-        ///  OTG_FS host channel-7 transfer size register
-        FS_HCTSIZ7: mmio.Mmio(packed struct(u32) {
-            ///  Transfer size
-            XFRSIZ: u19,
-            ///  Packet count
-            PKTCNT: u10,
-            ///  Data PID
-            DPID: u2,
-            padding: u1,
-        }),
-    };
-
-    ///  General purpose timers
-    pub const TIM2 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            padding: u24,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            padding: u16,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            reserved6: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            reserved8: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            reserved14: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            reserved6: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            reserved9: u2,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            padding: u19,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            reserved6: u1,
-            ///  Trigger generation
-            TG: u1,
-            padding: u25,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC1S
-            CC1S: u2,
-            ///  OC1FE
-            OC1FE: u1,
-            ///  OC1PE
-            OC1PE: u1,
-            ///  OC1M
-            OC1M: u3,
-            ///  OC1CE
-            OC1CE: u1,
-            ///  CC2S
-            CC2S: u2,
-            ///  OC2FE
-            OC2FE: u1,
-            ///  OC2PE
-            OC2PE: u1,
-            ///  OC2M
-            OC2M: u3,
-            ///  OC2CE
-            OC2CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare mode register 2 (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC3S
-            CC3S: u2,
-            ///  OC3FE
-            OC3FE: u1,
-            ///  OC3PE
-            OC3PE: u1,
-            ///  OC3M
-            OC3M: u3,
-            ///  OC3CE
-            OC3CE: u1,
-            ///  CC4S
-            CC4S: u2,
-            ///  OC4FE
-            OC4FE: u1,
-            ///  OC4PE
-            OC4PE: u1,
-            ///  OC4M
-            OC4M: u3,
-            ///  O24CE
-            O24CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved7: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            reserved11: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            reserved15: u1,
-            ///  Capture/Compare 4 output Polarity
-            CC4NP: u1,
-            padding: u16,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  Low counter value
-            CNT_L: u16,
-            ///  High counter value
-            CNT_H: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Low Auto-reload value
-            ARR_L: u16,
-            ///  High Auto-reload value
-            ARR_H: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 1 value
-            CCR1_L: u16,
-            ///  High Capture/Compare 1 value
-            CCR1_H: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 2 value
-            CCR2_L: u16,
-            ///  High Capture/Compare 2 value
-            CCR2_H: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR3_L: u16,
-            ///  High Capture/Compare value
-            CCR3_H: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR4_L: u16,
-            ///  High Capture/Compare value
-            CCR4_H: u16,
-        }),
-        reserved72: [4]u8,
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-        ///  TIM5 option register
-        OR: mmio.Mmio(packed struct(u32) {
-            reserved10: u10,
-            ///  Timer Input 4 remap
-            ITR1_RMP: u2,
-            padding: u20,
-        }),
-    };
-
-    ///  General purpose timers
-    pub const TIM3 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            padding: u24,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            padding: u16,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            reserved6: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            reserved8: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            reserved14: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            reserved6: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            reserved9: u2,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            padding: u19,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            reserved6: u1,
-            ///  Trigger generation
-            TG: u1,
-            padding: u25,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC1S
-            CC1S: u2,
-            ///  OC1FE
-            OC1FE: u1,
-            ///  OC1PE
-            OC1PE: u1,
-            ///  OC1M
-            OC1M: u3,
-            ///  OC1CE
-            OC1CE: u1,
-            ///  CC2S
-            CC2S: u2,
-            ///  OC2FE
-            OC2FE: u1,
-            ///  OC2PE
-            OC2PE: u1,
-            ///  OC2M
-            OC2M: u3,
-            ///  OC2CE
-            OC2CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare mode register 2 (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC3S
-            CC3S: u2,
-            ///  OC3FE
-            OC3FE: u1,
-            ///  OC3PE
-            OC3PE: u1,
-            ///  OC3M
-            OC3M: u3,
-            ///  OC3CE
-            OC3CE: u1,
-            ///  CC4S
-            CC4S: u2,
-            ///  OC4FE
-            OC4FE: u1,
-            ///  OC4PE
-            OC4PE: u1,
-            ///  OC4M
-            OC4M: u3,
-            ///  O24CE
-            O24CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved7: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            reserved11: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            reserved15: u1,
-            ///  Capture/Compare 4 output Polarity
-            CC4NP: u1,
-            padding: u16,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  Low counter value
-            CNT_L: u16,
-            ///  High counter value
-            CNT_H: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Low Auto-reload value
-            ARR_L: u16,
-            ///  High Auto-reload value
-            ARR_H: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 1 value
-            CCR1_L: u16,
-            ///  High Capture/Compare 1 value
-            CCR1_H: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 2 value
-            CCR2_L: u16,
-            ///  High Capture/Compare 2 value
-            CCR2_H: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR3_L: u16,
-            ///  High Capture/Compare value
-            CCR3_H: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR4_L: u16,
-            ///  High Capture/Compare value
-            CCR4_H: u16,
-        }),
-        reserved72: [4]u8,
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  USB on the go full speed
-    pub const OTG_FS_GLOBAL = extern struct {
-        ///  OTG_FS control and status register (OTG_FS_GOTGCTL)
-        FS_GOTGCTL: mmio.Mmio(packed struct(u32) {
-            ///  Session request success
-            SRQSCS: u1,
-            ///  Session request
-            SRQ: u1,
-            reserved8: u6,
-            ///  Host negotiation success
-            HNGSCS: u1,
-            ///  HNP request
-            HNPRQ: u1,
-            ///  Host set HNP enable
-            HSHNPEN: u1,
-            ///  Device HNP enabled
-            DHNPEN: u1,
-            reserved16: u4,
-            ///  Connector ID status
-            CIDSTS: u1,
-            ///  Long/short debounce time
-            DBCT: u1,
-            ///  A-session valid
-            ASVLD: u1,
-            ///  B-session valid
-            BSVLD: u1,
-            padding: u12,
-        }),
-        ///  OTG_FS interrupt register (OTG_FS_GOTGINT)
-        FS_GOTGINT: mmio.Mmio(packed struct(u32) {
-            reserved2: u2,
-            ///  Session end detected
-            SEDET: u1,
-            reserved8: u5,
-            ///  Session request success status change
-            SRSSCHG: u1,
-            ///  Host negotiation success status change
-            HNSSCHG: u1,
-            reserved17: u7,
-            ///  Host negotiation detected
-            HNGDET: u1,
-            ///  A-device timeout change
-            ADTOCHG: u1,
-            ///  Debounce done
-            DBCDNE: u1,
-            padding: u12,
-        }),
-        ///  OTG_FS AHB configuration register (OTG_FS_GAHBCFG)
-        FS_GAHBCFG: mmio.Mmio(packed struct(u32) {
-            ///  Global interrupt mask
-            GINT: u1,
-            reserved7: u6,
-            ///  TxFIFO empty level
-            TXFELVL: u1,
-            ///  Periodic TxFIFO empty level
-            PTXFELVL: u1,
-            padding: u23,
-        }),
-        ///  OTG_FS USB configuration register (OTG_FS_GUSBCFG)
-        FS_GUSBCFG: mmio.Mmio(packed struct(u32) {
-            ///  FS timeout calibration
-            TOCAL: u3,
-            reserved6: u3,
-            ///  Full Speed serial transceiver select
-            PHYSEL: u1,
-            reserved8: u1,
-            ///  SRP-capable
-            SRPCAP: u1,
-            ///  HNP-capable
-            HNPCAP: u1,
-            ///  USB turnaround time
-            TRDT: u4,
-            reserved29: u15,
-            ///  Force host mode
-            FHMOD: u1,
-            ///  Force device mode
-            FDMOD: u1,
-            ///  Corrupt Tx packet
-            CTXPKT: u1,
-        }),
-        ///  OTG_FS reset register (OTG_FS_GRSTCTL)
-        FS_GRSTCTL: mmio.Mmio(packed struct(u32) {
-            ///  Core soft reset
-            CSRST: u1,
-            ///  HCLK soft reset
-            HSRST: u1,
-            ///  Host frame counter reset
-            FCRST: u1,
-            reserved4: u1,
-            ///  RxFIFO flush
-            RXFFLSH: u1,
-            ///  TxFIFO flush
-            TXFFLSH: u1,
-            ///  TxFIFO number
-            TXFNUM: u5,
-            reserved31: u20,
-            ///  AHB master idle
-            AHBIDL: u1,
-        }),
-        ///  OTG_FS core interrupt register (OTG_FS_GINTSTS)
-        FS_GINTSTS: mmio.Mmio(packed struct(u32) {
-            ///  Current mode of operation
-            CMOD: u1,
-            ///  Mode mismatch interrupt
-            MMIS: u1,
-            ///  OTG interrupt
-            OTGINT: u1,
-            ///  Start of frame
-            SOF: u1,
-            ///  RxFIFO non-empty
-            RXFLVL: u1,
-            ///  Non-periodic TxFIFO empty
-            NPTXFE: u1,
-            ///  Global IN non-periodic NAK effective
-            GINAKEFF: u1,
-            ///  Global OUT NAK effective
-            GOUTNAKEFF: u1,
-            reserved10: u2,
-            ///  Early suspend
-            ESUSP: u1,
-            ///  USB suspend
-            USBSUSP: u1,
-            ///  USB reset
-            USBRST: u1,
-            ///  Enumeration done
-            ENUMDNE: u1,
-            ///  Isochronous OUT packet dropped interrupt
-            ISOODRP: u1,
-            ///  End of periodic frame interrupt
-            EOPF: u1,
-            reserved18: u2,
-            ///  IN endpoint interrupt
-            IEPINT: u1,
-            ///  OUT endpoint interrupt
-            OEPINT: u1,
-            ///  Incomplete isochronous IN transfer
-            IISOIXFR: u1,
-            ///  Incomplete periodic transfer(Host mode)/Incomplete isochronous OUT transfer(Device mode)
-            IPXFR_INCOMPISOOUT: u1,
-            reserved24: u2,
-            ///  Host port interrupt
-            HPRTINT: u1,
-            ///  Host channels interrupt
-            HCINT: u1,
-            ///  Periodic TxFIFO empty
-            PTXFE: u1,
-            reserved28: u1,
-            ///  Connector ID status change
-            CIDSCHG: u1,
-            ///  Disconnect detected interrupt
-            DISCINT: u1,
-            ///  Session request/new session detected interrupt
-            SRQINT: u1,
-            ///  Resume/remote wakeup detected interrupt
-            WKUPINT: u1,
-        }),
-        ///  OTG_FS interrupt mask register (OTG_FS_GINTMSK)
-        FS_GINTMSK: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  Mode mismatch interrupt mask
-            MMISM: u1,
-            ///  OTG interrupt mask
-            OTGINT: u1,
-            ///  Start of frame mask
-            SOFM: u1,
-            ///  Receive FIFO non-empty mask
-            RXFLVLM: u1,
-            ///  Non-periodic TxFIFO empty mask
-            NPTXFEM: u1,
-            ///  Global non-periodic IN NAK effective mask
-            GINAKEFFM: u1,
-            ///  Global OUT NAK effective mask
-            GONAKEFFM: u1,
-            reserved10: u2,
-            ///  Early suspend mask
-            ESUSPM: u1,
-            ///  USB suspend mask
-            USBSUSPM: u1,
-            ///  USB reset mask
-            USBRST: u1,
-            ///  Enumeration done mask
-            ENUMDNEM: u1,
-            ///  Isochronous OUT packet dropped interrupt mask
-            ISOODRPM: u1,
-            ///  End of periodic frame interrupt mask
-            EOPFM: u1,
-            reserved17: u1,
-            ///  Endpoint mismatch interrupt mask
-            EPMISM: u1,
-            ///  IN endpoints interrupt mask
-            IEPINT: u1,
-            ///  OUT endpoints interrupt mask
-            OEPINT: u1,
-            ///  Incomplete isochronous IN transfer mask
-            IISOIXFRM: u1,
-            ///  Incomplete periodic transfer mask(Host mode)/Incomplete isochronous OUT transfer mask(Device mode)
-            IPXFRM_IISOOXFRM: u1,
-            reserved24: u2,
-            ///  Host port interrupt mask
-            PRTIM: u1,
-            ///  Host channels interrupt mask
-            HCIM: u1,
-            ///  Periodic TxFIFO empty mask
-            PTXFEM: u1,
-            reserved28: u1,
-            ///  Connector ID status change mask
-            CIDSCHGM: u1,
-            ///  Disconnect detected interrupt mask
-            DISCINT: u1,
-            ///  Session request/new session detected interrupt mask
-            SRQIM: u1,
-            ///  Resume/remote wakeup detected interrupt mask
-            WUIM: u1,
-        }),
-        ///  OTG_FS Receive status debug read(Device mode)
-        FS_GRXSTSR_Device: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint number
-            EPNUM: u4,
-            ///  Byte count
-            BCNT: u11,
-            ///  Data PID
-            DPID: u2,
-            ///  Packet status
-            PKTSTS: u4,
-            ///  Frame number
-            FRMNUM: u4,
-            padding: u7,
-        }),
-        reserved36: [4]u8,
-        ///  OTG_FS Receive FIFO size register (OTG_FS_GRXFSIZ)
-        FS_GRXFSIZ: mmio.Mmio(packed struct(u32) {
-            ///  RxFIFO depth
-            RXFD: u16,
-            padding: u16,
-        }),
-        ///  OTG_FS non-periodic transmit FIFO size register (Device mode)
-        FS_GNPTXFSIZ_Device: mmio.Mmio(packed struct(u32) {
-            ///  Endpoint 0 transmit RAM start address
-            TX0FSA: u16,
-            ///  Endpoint 0 TxFIFO depth
-            TX0FD: u16,
-        }),
-        ///  OTG_FS non-periodic transmit FIFO/queue status register (OTG_FS_GNPTXSTS)
-        FS_GNPTXSTS: mmio.Mmio(packed struct(u32) {
-            ///  Non-periodic TxFIFO space available
-            NPTXFSAV: u16,
-            ///  Non-periodic transmit request queue space available
-            NPTQXSAV: u8,
-            ///  Top of the non-periodic transmit request queue
-            NPTXQTOP: u7,
-            padding: u1,
-        }),
-        reserved56: [8]u8,
-        ///  OTG_FS general core configuration register (OTG_FS_GCCFG)
-        FS_GCCFG: mmio.Mmio(packed struct(u32) {
-            reserved16: u16,
-            ///  Power down
-            PWRDWN: u1,
-            reserved18: u1,
-            ///  Enable the VBUS sensing device
-            VBUSASEN: u1,
-            ///  Enable the VBUS sensing device
-            VBUSBSEN: u1,
-            ///  SOF output enable
-            SOFOUTEN: u1,
-            padding: u11,
-        }),
-        ///  core ID register
-        FS_CID: mmio.Mmio(packed struct(u32) {
-            ///  Product ID field
-            PRODUCT_ID: u32,
-        }),
-        reserved256: [192]u8,
-        ///  OTG_FS Host periodic transmit FIFO size register (OTG_FS_HPTXFSIZ)
-        FS_HPTXFSIZ: mmio.Mmio(packed struct(u32) {
-            ///  Host periodic TxFIFO start address
-            PTXSA: u16,
-            ///  Host periodic TxFIFO depth
-            PTXFSIZ: u16,
-        }),
-        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF2)
-        FS_DIEPTXF1: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFO2 transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF3)
-        FS_DIEPTXF2: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFO3 transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-        ///  OTG_FS device IN endpoint transmit FIFO size register (OTG_FS_DIEPTXF4)
-        FS_DIEPTXF3: mmio.Mmio(packed struct(u32) {
-            ///  IN endpoint FIFO4 transmit RAM start address
-            INEPTXSA: u16,
-            ///  IN endpoint TxFIFO depth
-            INEPTXFD: u16,
-        }),
-    };
-
-    ///  General-purpose-timers
-    pub const TIM5 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            ///  Direction
-            DIR: u1,
-            ///  Center-aligned mode selection
-            CMS: u2,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved3: u3,
-            ///  Capture/compare DMA selection
-            CCDS: u1,
-            ///  Master mode selection
-            MMS: u3,
-            ///  TI1 selection
-            TI1S: u1,
-            padding: u24,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            ///  External trigger filter
-            ETF: u4,
-            ///  External trigger prescaler
-            ETPS: u2,
-            ///  External clock enable
-            ECE: u1,
-            ///  External trigger polarity
-            ETP: u1,
-            padding: u16,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            ///  Capture/Compare 3 interrupt enable
-            CC3IE: u1,
-            ///  Capture/Compare 4 interrupt enable
-            CC4IE: u1,
-            reserved6: u1,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            reserved8: u1,
-            ///  Update DMA request enable
-            UDE: u1,
-            ///  Capture/Compare 1 DMA request enable
-            CC1DE: u1,
-            ///  Capture/Compare 2 DMA request enable
-            CC2DE: u1,
-            ///  Capture/Compare 3 DMA request enable
-            CC3DE: u1,
-            ///  Capture/Compare 4 DMA request enable
-            CC4DE: u1,
-            reserved14: u1,
-            ///  Trigger DMA request enable
-            TDE: u1,
-            padding: u17,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            ///  Capture/Compare 3 interrupt flag
-            CC3IF: u1,
-            ///  Capture/Compare 4 interrupt flag
-            CC4IF: u1,
-            reserved6: u1,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            reserved9: u2,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            ///  Capture/Compare 3 overcapture flag
-            CC3OF: u1,
-            ///  Capture/Compare 4 overcapture flag
-            CC4OF: u1,
-            padding: u19,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            ///  Capture/compare 3 generation
-            CC3G: u1,
-            ///  Capture/compare 4 generation
-            CC4G: u1,
-            reserved6: u1,
-            ///  Trigger generation
-            TG: u1,
-            padding: u25,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC1S
-            CC1S: u2,
-            ///  OC1FE
-            OC1FE: u1,
-            ///  OC1PE
-            OC1PE: u1,
-            ///  OC1M
-            OC1M: u3,
-            ///  OC1CE
-            OC1CE: u1,
-            ///  CC2S
-            CC2S: u2,
-            ///  OC2FE
-            OC2FE: u1,
-            ///  OC2PE
-            OC2PE: u1,
-            ///  OC2M
-            OC2M: u3,
-            ///  OC2CE
-            OC2CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare mode register 2 (output mode)
-        CCMR2_Output: mmio.Mmio(packed struct(u32) {
-            ///  CC3S
-            CC3S: u2,
-            ///  OC3FE
-            OC3FE: u1,
-            ///  OC3PE
-            OC3PE: u1,
-            ///  OC3M
-            OC3M: u3,
-            ///  OC3CE
-            OC3CE: u1,
-            ///  CC4S
-            CC4S: u2,
-            ///  OC4FE
-            OC4FE: u1,
-            ///  OC4PE
-            OC4PE: u1,
-            ///  OC4M
-            OC4M: u3,
-            ///  O24CE
-            O24CE: u1,
-            padding: u16,
-        }),
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved7: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            ///  Capture/Compare 3 output enable
-            CC3E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3P: u1,
-            reserved11: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC3NP: u1,
-            ///  Capture/Compare 4 output enable
-            CC4E: u1,
-            ///  Capture/Compare 3 output Polarity
-            CC4P: u1,
-            reserved15: u1,
-            ///  Capture/Compare 4 output Polarity
-            CC4NP: u1,
-            padding: u16,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  Low counter value
-            CNT_L: u16,
-            ///  High counter value
-            CNT_H: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Low Auto-reload value
-            ARR_L: u16,
-            ///  High Auto-reload value
-            ARR_H: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 1 value
-            CCR1_L: u16,
-            ///  High Capture/Compare 1 value
-            CCR1_H: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare 2 value
-            CCR2_L: u16,
-            ///  High Capture/Compare 2 value
-            CCR2_H: u16,
-        }),
-        ///  capture/compare register 3
-        CCR3: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR3_L: u16,
-            ///  High Capture/Compare value
-            CCR3_H: u16,
-        }),
-        ///  capture/compare register 4
-        CCR4: mmio.Mmio(packed struct(u32) {
-            ///  Low Capture/Compare value
-            CCR4_L: u16,
-            ///  High Capture/Compare value
-            CCR4_H: u16,
-        }),
-        reserved72: [4]u8,
-        ///  DMA control register
-        DCR: mmio.Mmio(packed struct(u32) {
-            ///  DMA base address
-            DBA: u5,
-            reserved8: u3,
-            ///  DMA burst length
-            DBL: u5,
-            padding: u19,
-        }),
-        ///  DMA address for full transfer
-        DMAR: mmio.Mmio(packed struct(u32) {
-            ///  DMA register for burst accesses
-            DMAB: u16,
-            padding: u16,
-        }),
-        ///  TIM5 option register
-        OR: mmio.Mmio(packed struct(u32) {
-            reserved6: u6,
-            ///  Timer Input 4 remap
-            IT4_RMP: u2,
-            padding: u24,
-        }),
-    };
-
-    ///  General purpose timers
-    pub const TIM9 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            ///  One-pulse mode
-            OPM: u1,
-            reserved7: u3,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        ///  control register 2
-        CR2: mmio.Mmio(packed struct(u32) {
-            reserved4: u4,
-            ///  Master mode selection
-            MMS: u3,
-            padding: u25,
-        }),
-        ///  slave mode control register
-        SMCR: mmio.Mmio(packed struct(u32) {
-            ///  Slave mode selection
-            SMS: u3,
-            reserved4: u1,
-            ///  Trigger selection
-            TS: u3,
-            ///  Master/Slave mode
-            MSM: u1,
-            padding: u24,
-        }),
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            ///  Capture/Compare 2 interrupt enable
-            CC2IE: u1,
-            reserved6: u3,
-            ///  Trigger interrupt enable
-            TIE: u1,
-            padding: u25,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            ///  Capture/Compare 2 interrupt flag
-            CC2IF: u1,
-            reserved6: u3,
-            ///  Trigger interrupt flag
-            TIF: u1,
-            reserved9: u2,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            ///  Capture/compare 2 overcapture flag
-            CC2OF: u1,
-            padding: u21,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            ///  Capture/compare 2 generation
-            CC2G: u1,
-            reserved6: u3,
-            ///  Trigger generation
-            TG: u1,
-            padding: u25,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            reserved8: u1,
-            ///  Capture/Compare 2 selection
-            CC2S: u2,
-            ///  Output Compare 2 fast enable
-            OC2FE: u1,
-            ///  Output Compare 2 preload enable
-            OC2PE: u1,
-            ///  Output Compare 2 mode
-            OC2M: u3,
-            padding: u17,
-        }),
-        reserved32: [4]u8,
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            ///  Capture/Compare 2 output enable
-            CC2E: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2P: u1,
-            reserved7: u1,
-            ///  Capture/Compare 2 output Polarity
-            CC2NP: u1,
-            padding: u24,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        ///  capture/compare register 2
-        CCR2: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 2 value
-            CCR2: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Cryptographic processor
-    pub const CRC = extern struct {
-        ///  Data register
-        DR: mmio.Mmio(packed struct(u32) {
-            ///  Data Register
-            DR: u32,
-        }),
-        ///  Independent Data register
-        IDR: mmio.Mmio(packed struct(u32) {
-            ///  Independent Data register
-            IDR: u8,
-            padding: u24,
-        }),
-        ///  Control register
-        CR: mmio.Mmio(packed struct(u32) {
-            ///  Control regidter
-            CR: u1,
-            padding: u31,
-        }),
-    };
-
-    ///  General-purpose-timers
-    pub const TIM10 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            reserved7: u4,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        reserved12: [8]u8,
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            padding: u30,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            reserved9: u7,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            padding: u22,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            padding: u30,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            padding: u25,
-        }),
-        reserved32: [4]u8,
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            padding: u28,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-    };
-
-    ///  Ethernet: DMA controller operation
-    pub const Ethernet_DMA = extern struct {
-        ///  Ethernet DMA bus mode register
-        DMABMR: mmio.Mmio(packed struct(u32) {
-            ///  SR
-            SR: u1,
-            ///  DA
-            DA: u1,
-            ///  DSL
-            DSL: u5,
-            ///  EDFE
-            EDFE: u1,
-            ///  PBL
-            PBL: u6,
-            ///  RTPR
-            RTPR: u2,
-            ///  FB
-            FB: u1,
-            ///  RDP
-            RDP: u6,
-            ///  USP
-            USP: u1,
-            ///  FPM
-            FPM: u1,
-            ///  AAB
-            AAB: u1,
-            ///  MB
-            MB: u1,
-            padding: u5,
-        }),
-        ///  Ethernet DMA transmit poll demand register
-        DMATPDR: mmio.Mmio(packed struct(u32) {
-            ///  TPD
-            TPD: u32,
-        }),
-        ///  EHERNET DMA receive poll demand register
-        DMARPDR: mmio.Mmio(packed struct(u32) {
-            ///  RPD
-            RPD: u32,
-        }),
-        ///  Ethernet DMA receive descriptor list address register
-        DMARDLAR: mmio.Mmio(packed struct(u32) {
-            ///  SRL
-            SRL: u32,
-        }),
-        ///  Ethernet DMA transmit descriptor list address register
-        DMATDLAR: mmio.Mmio(packed struct(u32) {
-            ///  STL
-            STL: u32,
-        }),
-        ///  Ethernet DMA status register
-        DMASR: mmio.Mmio(packed struct(u32) {
-            ///  TS
-            TS: u1,
-            ///  TPSS
-            TPSS: u1,
-            ///  TBUS
-            TBUS: u1,
-            ///  TJTS
-            TJTS: u1,
-            ///  ROS
-            ROS: u1,
-            ///  TUS
-            TUS: u1,
-            ///  RS
-            RS: u1,
-            ///  RBUS
-            RBUS: u1,
-            ///  RPSS
-            RPSS: u1,
-            ///  PWTS
-            PWTS: u1,
-            ///  ETS
-            ETS: u1,
-            reserved13: u2,
-            ///  FBES
-            FBES: u1,
-            ///  ERS
-            ERS: u1,
-            ///  AIS
-            AIS: u1,
-            ///  NIS
-            NIS: u1,
-            ///  RPS
-            RPS: u3,
-            ///  TPS
-            TPS: u3,
-            ///  EBS
-            EBS: u3,
-            reserved27: u1,
-            ///  MMCS
-            MMCS: u1,
-            ///  PMTS
-            PMTS: u1,
-            ///  TSTS
-            TSTS: u1,
-            padding: u2,
-        }),
-        ///  Ethernet DMA operation mode register
-        DMAOMR: mmio.Mmio(packed struct(u32) {
-            reserved1: u1,
-            ///  SR
-            SR: u1,
-            ///  OSF
-            OSF: u1,
-            ///  RTC
-            RTC: u2,
-            reserved6: u1,
-            ///  FUGF
-            FUGF: u1,
-            ///  FEF
-            FEF: u1,
-            reserved13: u5,
-            ///  ST
-            ST: u1,
-            ///  TTC
-            TTC: u3,
-            reserved20: u3,
-            ///  FTF
-            FTF: u1,
-            ///  TSF
-            TSF: u1,
-            reserved24: u2,
-            ///  DFRF
-            DFRF: u1,
-            ///  RSF
-            RSF: u1,
-            ///  DTCEFD
-            DTCEFD: u1,
-            padding: u5,
-        }),
-        ///  Ethernet DMA interrupt enable register
-        DMAIER: mmio.Mmio(packed struct(u32) {
-            ///  TIE
-            TIE: u1,
-            ///  TPSIE
-            TPSIE: u1,
-            ///  TBUIE
-            TBUIE: u1,
-            ///  TJTIE
-            TJTIE: u1,
-            ///  ROIE
-            ROIE: u1,
-            ///  TUIE
-            TUIE: u1,
-            ///  RIE
-            RIE: u1,
-            ///  RBUIE
-            RBUIE: u1,
-            ///  RPSIE
-            RPSIE: u1,
-            ///  RWTIE
-            RWTIE: u1,
-            ///  ETIE
-            ETIE: u1,
-            reserved13: u2,
-            ///  FBEIE
-            FBEIE: u1,
-            ///  ERIE
-            ERIE: u1,
-            ///  AISE
-            AISE: u1,
-            ///  NISE
-            NISE: u1,
-            padding: u15,
-        }),
-        ///  Ethernet DMA missed frame and buffer overflow counter register
-        DMAMFBOCR: mmio.Mmio(packed struct(u32) {
-            ///  MFC
-            MFC: u16,
-            ///  OMFC
-            OMFC: u1,
-            ///  MFA
-            MFA: u11,
-            ///  OFOC
-            OFOC: u1,
-            padding: u3,
-        }),
-        ///  Ethernet DMA receive status watchdog timer register
-        DMARSWTR: mmio.Mmio(packed struct(u32) {
-            ///  RSWTC
-            RSWTC: u8,
-            padding: u24,
-        }),
-        reserved72: [32]u8,
-        ///  Ethernet DMA current host transmit descriptor register
-        DMACHTDR: mmio.Mmio(packed struct(u32) {
-            ///  HTDAP
-            HTDAP: u32,
-        }),
-        ///  Ethernet DMA current host receive descriptor register
-        DMACHRDR: mmio.Mmio(packed struct(u32) {
-            ///  HRDAP
-            HRDAP: u32,
-        }),
-        ///  Ethernet DMA current host transmit buffer address register
-        DMACHTBAR: mmio.Mmio(packed struct(u32) {
-            ///  HTBAP
-            HTBAP: u32,
-        }),
-        ///  Ethernet DMA current host receive buffer address register
-        DMACHRBAR: mmio.Mmio(packed struct(u32) {
-            ///  HRBAP
-            HRBAP: u32,
-        }),
-    };
-
-    ///  Ethernet: Precision time protocol
-    pub const Ethernet_PTP = extern struct {
-        ///  Ethernet PTP time stamp control register
-        PTPTSCR: mmio.Mmio(packed struct(u32) {
-            ///  TSE
-            TSE: u1,
-            ///  TSFCU
-            TSFCU: u1,
-            ///  TSSTI
-            TSSTI: u1,
-            ///  TSSTU
-            TSSTU: u1,
-            ///  TSITE
-            TSITE: u1,
-            ///  TTSARU
-            TTSARU: u1,
-            reserved8: u2,
-            ///  TSSARFE
-            TSSARFE: u1,
-            ///  TSSSR
-            TSSSR: u1,
-            ///  TSPTPPSV2E
-            TSPTPPSV2E: u1,
-            ///  TSSPTPOEFE
-            TSSPTPOEFE: u1,
-            ///  TSSIPV6FE
-            TSSIPV6FE: u1,
-            ///  TSSIPV4FE
-            TSSIPV4FE: u1,
-            ///  TSSEME
-            TSSEME: u1,
-            ///  TSSMRME
-            TSSMRME: u1,
-            ///  TSCNT
-            TSCNT: u2,
-            ///  TSPFFMAE
-            TSPFFMAE: u1,
-            padding: u13,
-        }),
-        ///  Ethernet PTP subsecond increment register
-        PTPSSIR: mmio.Mmio(packed struct(u32) {
-            ///  STSSI
-            STSSI: u8,
-            padding: u24,
-        }),
-        ///  Ethernet PTP time stamp high register
-        PTPTSHR: mmio.Mmio(packed struct(u32) {
-            ///  STS
-            STS: u32,
-        }),
-        ///  Ethernet PTP time stamp low register
-        PTPTSLR: mmio.Mmio(packed struct(u32) {
-            ///  STSS
-            STSS: u31,
-            ///  STPNS
-            STPNS: u1,
-        }),
-        ///  Ethernet PTP time stamp high update register
-        PTPTSHUR: mmio.Mmio(packed struct(u32) {
-            ///  TSUS
-            TSUS: u32,
-        }),
-        ///  Ethernet PTP time stamp low update register
-        PTPTSLUR: mmio.Mmio(packed struct(u32) {
-            ///  TSUSS
-            TSUSS: u31,
-            ///  TSUSS
-            TSUPNS: u1,
-        }),
-        ///  Ethernet PTP time stamp addend register
-        PTPTSAR: mmio.Mmio(packed struct(u32) {
-            ///  TSA
-            TSA: u32,
-        }),
-        ///  Ethernet PTP target time high register
-        PTPTTHR: mmio.Mmio(packed struct(u32) {
-            ///  0
-            TTSH: u32,
-        }),
-        ///  Ethernet PTP target time low register
-        PTPTTLR: mmio.Mmio(packed struct(u32) {
-            ///  TTSL
-            TTSL: u32,
-        }),
-        reserved40: [4]u8,
-        ///  Ethernet PTP time stamp status register
-        PTPTSSR: mmio.Mmio(packed struct(u32) {
-            ///  TSSO
-            TSSO: u1,
-            ///  TSTTR
-            TSTTR: u1,
-            padding: u30,
-        }),
-        ///  Ethernet PTP PPS control register
-        PTPPPSCR: mmio.Mmio(packed struct(u32) {
-            ///  TSSO
-            TSSO: u1,
-            ///  TSTTR
-            TSTTR: u1,
-            padding: u30,
-        }),
-    };
-
-    ///  General-purpose-timers
-    pub const TIM11 = extern struct {
-        ///  control register 1
-        CR1: mmio.Mmio(packed struct(u32) {
-            ///  Counter enable
-            CEN: u1,
-            ///  Update disable
-            UDIS: u1,
-            ///  Update request source
-            URS: u1,
-            reserved7: u4,
-            ///  Auto-reload preload enable
-            ARPE: u1,
-            ///  Clock division
-            CKD: u2,
-            padding: u22,
-        }),
-        reserved12: [8]u8,
-        ///  DMA/Interrupt enable register
-        DIER: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt enable
-            UIE: u1,
-            ///  Capture/Compare 1 interrupt enable
-            CC1IE: u1,
-            padding: u30,
-        }),
-        ///  status register
-        SR: mmio.Mmio(packed struct(u32) {
-            ///  Update interrupt flag
-            UIF: u1,
-            ///  Capture/compare 1 interrupt flag
-            CC1IF: u1,
-            reserved9: u7,
-            ///  Capture/Compare 1 overcapture flag
-            CC1OF: u1,
-            padding: u22,
-        }),
-        ///  event generation register
-        EGR: mmio.Mmio(packed struct(u32) {
-            ///  Update generation
-            UG: u1,
-            ///  Capture/compare 1 generation
-            CC1G: u1,
-            padding: u30,
-        }),
-        ///  capture/compare mode register 1 (output mode)
-        CCMR1_Output: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 selection
-            CC1S: u2,
-            ///  Output Compare 1 fast enable
-            OC1FE: u1,
-            ///  Output Compare 1 preload enable
-            OC1PE: u1,
-            ///  Output Compare 1 mode
-            OC1M: u3,
-            padding: u25,
-        }),
-        reserved32: [4]u8,
-        ///  capture/compare enable register
-        CCER: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 output enable
-            CC1E: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1P: u1,
-            reserved3: u1,
-            ///  Capture/Compare 1 output Polarity
-            CC1NP: u1,
-            padding: u28,
-        }),
-        ///  counter
-        CNT: mmio.Mmio(packed struct(u32) {
-            ///  counter value
-            CNT: u16,
-            padding: u16,
-        }),
-        ///  prescaler
-        PSC: mmio.Mmio(packed struct(u32) {
-            ///  Prescaler value
-            PSC: u16,
-            padding: u16,
-        }),
-        ///  auto-reload register
-        ARR: mmio.Mmio(packed struct(u32) {
-            ///  Auto-reload value
-            ARR: u16,
-            padding: u16,
-        }),
-        reserved52: [4]u8,
-        ///  capture/compare register 1
-        CCR1: mmio.Mmio(packed struct(u32) {
-            ///  Capture/Compare 1 value
-            CCR1: u16,
-            padding: u16,
-        }),
-        reserved80: [24]u8,
-        ///  option register
-        OR: mmio.Mmio(packed struct(u32) {
-            ///  Input 1 remapping capability
-            RMP: u2,
-            padding: u30,
-        }),
-    };
-};

From 2fb0b5eeca59b381bfea1c536a1564b1a3d7fa0b Mon Sep 17 00:00:00 2001
From: Yerlan 
Date: Sat, 23 Sep 2023 13:55:50 +0200
Subject: [PATCH 211/286] Update README.adoc for Zig 0.11 release (#29)

Zig 0.11 was released.
I guess it makes sense to update the readme.
Looking at microzig, it looks like 0.11 is the supported version.
---
 README.adoc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.adoc b/README.adoc
index 4123f3c9a..d1a8bf801 100644
--- a/README.adoc
+++ b/README.adoc
@@ -6,4 +6,4 @@ SVD is copied from https://github.com/esp-rs/esp-pacs
 
 == What version of Zig to use
 
-Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+0.11.0

From 366e58f65c15736ddd7789ef7eed653922b39f1c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ardelean=20C=C4=83lin?=
 <9417983+Ardelean-Calin@users.noreply.github.com>
Date: Sat, 23 Sep 2023 18:01:42 +0300
Subject: [PATCH 212/286] Added support for STM32L0 series (#27)

* Added support for STM32L0 series

* Switched from JSON to SVD.
---
 build.zig               |   123 +-
 src/chips/STM32L0x1.svd | 16671 ++++++++++++++++++++++++++++
 src/chips/STM32L0x2.svd | 20698 +++++++++++++++++++++++++++++++++++
 src/chips/STM32L0x3.svd | 22518 ++++++++++++++++++++++++++++++++++++++
 4 files changed, 60000 insertions(+), 10 deletions(-)
 create mode 100644 src/chips/STM32L0x1.svd
 create mode 100644 src/chips/STM32L0x2.svd
 create mode 100644 src/chips/STM32L0x3.svd

diff --git a/build.zig b/build.zig
index cea2a1682..7a0aac02c 100644
--- a/build.zig
+++ b/build.zig
@@ -5,6 +5,7 @@ fn root() []const u8 {
     return comptime (std.fs.path.dirname(@src().file) orelse ".");
 }
 const build_root = root();
+const KiB = 1024;
 
 ////////////////////////////////////////
 //      MicroZig Gen 2 Interface      //
@@ -22,8 +23,8 @@ pub const chips = struct {
             .name = "STM32F103",
             .cpu = .cortex_m3,
             .memory_regions = &.{
-                .{ .offset = 0x08000000, .length = 64 * 1024, .kind = .flash },
-                .{ .offset = 0x20000000, .length = 20 * 1024, .kind = .ram },
+                .{ .offset = 0x08000000, .length = 64 * KiB, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 20 * KiB, .kind = .ram },
             },
             .register_definition = .{
                 .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F103.json" },
@@ -37,8 +38,8 @@ pub const chips = struct {
             .name = "STM32F303",
             .cpu = .cortex_m4,
             .memory_regions = &.{
-                .{ .offset = 0x08000000, .length = 256 * 1024, .kind = .flash },
-                .{ .offset = 0x20000000, .length = 40 * 1024, .kind = .ram },
+                .{ .offset = 0x08000000, .length = 256 * KiB, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 40 * KiB, .kind = .ram },
             },
             .register_definition = .{
                 .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F303.json" },
@@ -52,9 +53,9 @@ pub const chips = struct {
             .name = "STM32F407",
             .cpu = .cortex_m4,
             .memory_regions = &.{
-                .{ .offset = 0x08000000, .length = 1024 * 1024, .kind = .flash },
-                .{ .offset = 0x20000000, .length = 128 * 1024, .kind = .ram },
-                .{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, // CCM RAM
+                .{ .offset = 0x08000000, .length = 1024 * KiB, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 128 * KiB, .kind = .ram },
+                .{ .offset = 0x10000000, .length = 64 * KiB, .kind = .ram }, // CCM RAM
             },
             .register_definition = .{
                 .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F407.json" },
@@ -68,15 +69,117 @@ pub const chips = struct {
             .name = "STM32F429",
             .cpu = .cortex_m4,
             .memory_regions = &.{
-                .{ .offset = 0x08000000, .length = 2048 * 1024, .kind = .flash },
-                .{ .offset = 0x20000000, .length = 192 * 1024, .kind = .ram },
-                .{ .offset = 0x10000000, .length = 64 * 1024, .kind = .ram }, // CCM RAM
+                .{ .offset = 0x08000000, .length = 2048 * KiB, .kind = .flash },
+                .{ .offset = 0x20000000, .length = 192 * KiB, .kind = .ram },
+                .{ .offset = 0x10000000, .length = 64 * KiB, .kind = .ram }, // CCM RAM
             },
             .register_definition = .{
                 .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F429.json" },
             },
         },
     };
+
+    // All STM32L0x1 series MCUs differ only in memory size. So we create a comptime function
+    // to generate all MCU variants as per https://www.st.com/en/microcontrollers-microprocessors/stm32l0x1.html
+    fn stm32l0x1(comptime rom_size: u64, comptime ram_size: u64) microzig.Target {
+        return microzig.Target{
+            .preferred_format = .elf,
+            .chip = .{
+                .name = "STM32L0x1",
+                .cpu = .cortex_m0plus,
+                .memory_regions = &.{
+                    .{ .offset = 0x08000000, .length = rom_size, .kind = .flash },
+                    .{ .offset = 0x20000000, .length = ram_size, .kind = .ram },
+                },
+                .register_definition = .{
+                    .svd = .{ .cwd_relative = build_root ++ "/src/chips/STM32L0x1.svd" },
+                },
+            },
+        };
+    }
+
+    pub const stm32l011x3 = stm32l0x1(8 * KiB, 2 * KiB);
+
+    pub const stm32l011x4 = stm32l0x1(16 * KiB, 2 * KiB);
+    pub const stm32l021x4 = stm32l0x1(16 * KiB, 2 * KiB);
+    pub const stm32l031x4 = stm32l0x1(16 * KiB, 8 * KiB);
+
+    pub const stm32l031x6 = stm32l0x1(32 * KiB, 8 * KiB);
+    pub const stm32l041x6 = stm32l0x1(32 * KiB, 8 * KiB);
+    pub const stm32l051x6 = stm32l0x1(32 * KiB, 8 * KiB);
+
+    pub const stm32l051x8 = stm32l0x1(64 * KiB, 8 * KiB);
+    pub const stm32l071x8 = stm32l0x1(64 * KiB, 20 * KiB);
+
+    pub const stm32l071xb = stm32l0x1(128 * KiB, 20 * KiB);
+    pub const stm32l081cb = stm32l0x1(128 * KiB, 20 * KiB);
+
+    pub const stm32l071xz = stm32l0x1(192 * KiB, 20 * KiB);
+    pub const stm32l081xz = stm32l0x1(192 * KiB, 20 * KiB);
+
+    // All STM32L0x2 series MCUs differ only in memory size. So we create a comptime function
+    // to generate all MCU variants as per https://www.st.com/en/microcontrollers-microprocessors/stm32l0x2.html
+    fn stm32l0x2(comptime rom_size: u64, comptime ram_size: u64) microzig.Target {
+        return microzig.Target{
+            .preferred_format = .elf,
+            .chip = .{
+                .name = "STM32L0x2",
+                .cpu = .cortex_m0plus,
+                .memory_regions = &.{
+                    .{ .offset = 0x08000000, .length = rom_size, .kind = .flash },
+                    .{ .offset = 0x20000000, .length = ram_size, .kind = .ram },
+                },
+                .register_definition = .{
+                    .svd = .{ .cwd_relative = build_root ++ "/src/chips/STM32L0x2.svd" },
+                },
+            },
+        };
+    }
+
+    pub const stm32l052x6 = stm32l0x2(32 * KiB, 8 * KiB);
+
+    pub const stm32l052x8 = stm32l0x2(64 * KiB, 8 * KiB);
+    pub const stm32l062x8 = stm32l0x2(64 * KiB, 8 * KiB);
+    pub const stm32l072v8 = stm32l0x2(64 * KiB, 20 * KiB);
+
+    pub const stm32l072xb = stm32l0x2(128 * KiB, 20 * KiB);
+    pub const stm32l082xb = stm32l0x2(128 * KiB, 20 * KiB);
+
+    pub const stm32l072xz = stm32l0x2(192 * KiB, 20 * KiB);
+    pub const stm32l082xz = stm32l0x2(192 * KiB, 20 * KiB);
+
+    // All STM32L0x2 series MCUs differ only in memory size. So we create a comptime function
+    // to generate all MCU variants as per https://www.st.com/en/microcontrollers-microprocessors/stm32l0x3.html
+    fn stm32l0x3(comptime rom_size: u64, comptime ram_size: u64) microzig.Target {
+        return microzig.Target{
+            .preferred_format = .elf,
+            .chip = .{
+                .name = "STM32L0x3",
+                .cpu = .cortex_m0plus,
+                .memory_regions = &.{
+                    .{ .offset = 0x08000000, .length = rom_size, .kind = .flash },
+                    .{ .offset = 0x20000000, .length = ram_size, .kind = .ram },
+                },
+                .register_definition = .{
+                    .svd = .{ .cwd_relative = build_root ++ "/src/chips/STM32L0x3.svd" },
+                },
+            },
+        };
+    }
+
+    pub const stm32l053x6 = stm32l0x2(32 * KiB, 8 * KiB);
+
+    pub const stm32l053x8 = stm32l0x2(64 * KiB, 8 * KiB);
+    pub const stm32l063x8 = stm32l0x2(64 * KiB, 8 * KiB);
+
+    pub const stm32l073v8 = stm32l0x2(64 * KiB, 20 * KiB);
+    pub const stm32l083v8 = stm32l0x2(64 * KiB, 20 * KiB);
+
+    pub const stm32l073xb = stm32l0x2(128 * KiB, 20 * KiB);
+    pub const stm32l083xb = stm32l0x2(128 * KiB, 20 * KiB);
+
+    pub const stm32l073xz = stm32l0x2(192 * KiB, 20 * KiB);
+    pub const stm32l083xz = stm32l0x2(192 * KiB, 20 * KiB);
 };
 
 pub const boards = struct {
diff --git a/src/chips/STM32L0x1.svd b/src/chips/STM32L0x1.svd
new file mode 100644
index 000000000..360fdb22c
--- /dev/null
+++ b/src/chips/STM32L0x1.svd
@@ -0,0 +1,16671 @@
+
+
+  STM32L0x1
+  1.3
+  STM32L0x1
+  
+  
+    CM0+
+    r0p0
+    little
+    false
+    false
+    3
+    false
+  
+  
+  
+  8
+  
+  32
+  
+  0x20
+  0x0
+  0xFFFFFFFF
+  
+    
+      AES
+      Advanced encryption standard hardware
+      accelerator
+      AES
+      0x40026000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        AES_RNG_LPUART1
+        AES global interrupt RNG global interrupt and
+        LPUART1 global interrupt through
+        29
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DMAOUTEN
+              Enable DMA management of data output
+              phase
+              12
+              1
+            
+            
+              DMAINEN
+              Enable DMA management of data input
+              phase
+              11
+              1
+            
+            
+              ERRIE
+              Error interrupt enable
+              10
+              1
+            
+            
+              CCFIE
+              CCF flag interrupt enable
+              9
+              1
+            
+            
+              ERRC
+              Error clear
+              8
+              1
+            
+            
+              CCFC
+              Computation Complete Flag
+              Clear
+              7
+              1
+            
+            
+              CHMOD
+              AES chaining mode
+              5
+              2
+            
+            
+              MODE
+              AES operating mode
+              3
+              2
+            
+            
+              DATATYPE
+              Data type selection (for data in and
+              data out to/from the cryptographic
+              block)
+              1
+              2
+            
+            
+              EN
+              AES enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x4
+          0x20
+          read-only
+          0x00000000
+          
+            
+              WRERR
+              Write error flag
+              2
+              1
+            
+            
+              RDERR
+              Read error flag
+              1
+              1
+            
+            
+              CCF
+              Computation complete flag
+              0
+              1
+            
+          
+        
+        
+          DINR
+          DINR
+          data input register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_DINR
+              Data Input Register.
+              0
+              32
+            
+          
+        
+        
+          DOUTR
+          DOUTR
+          data output register
+          0xC
+          0x20
+          read-only
+          0x00000000
+          
+            
+              AES_DOUTR
+              Data output register
+              0
+              32
+            
+          
+        
+        
+          KEYR0
+          KEYR0
+          key register 0
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR0
+              Data Output Register (LSB key
+              [31:0])
+              0
+              32
+            
+          
+        
+        
+          KEYR1
+          KEYR1
+          key register 1
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR1
+              AES key register (key
+              [63:32])
+              0
+              32
+            
+          
+        
+        
+          KEYR2
+          KEYR2
+          key register 2
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR2
+              AES key register (key
+              [95:64])
+              0
+              32
+            
+          
+        
+        
+          KEYR3
+          KEYR3
+          key register 3
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR3
+              AES key register (MSB key
+              [127:96])
+              0
+              32
+            
+          
+        
+        
+          IVR0
+          IVR0
+          initialization vector register
+          0
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR0
+              initialization vector register (LSB IVR
+              [31:0])
+              0
+              32
+            
+          
+        
+        
+          IVR1
+          IVR1
+          initialization vector register
+          1
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR1
+              Initialization Vector Register (IVR
+              [63:32])
+              0
+              32
+            
+          
+        
+        
+          IVR2
+          IVR2
+          initialization vector register
+          2
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR2
+              Initialization Vector Register (IVR
+              [95:64])
+              0
+              32
+            
+          
+        
+        
+          IVR3
+          IVR3
+          initialization vector register
+          3
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR3
+              Initialization Vector Register (MSB IVR
+              [127:96])
+              0
+              32
+            
+          
+        
+      
+    
+    
+      DMA1
+      Direct memory access controller
+      DMA
+      0x40020000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        DMA1_Channel1
+        DMA1 Channel1 global interrupt
+        9
+      
+      
+        DMA1_Channel2_3
+        DMA1 Channel2 and 3 interrupts
+        10
+      
+      
+        DMA1_Channel4_7
+        DMA1 Channel4 to 7 interrupts
+        11
+      
+      
+        
+          ISR
+          ISR
+          interrupt status register
+          0x0
+          0x20
+          read-only
+          0x00000000
+          
+            
+              TEIF7
+              Channel x transfer error flag (x = 1
+              ..7)
+              27
+              1
+            
+            
+              HTIF7
+              Channel x half transfer flag (x = 1
+              ..7)
+              26
+              1
+            
+            
+              TCIF7
+              Channel x transfer complete flag (x = 1
+              ..7)
+              25
+              1
+            
+            
+              GIF7
+              Channel x global interrupt flag (x = 1
+              ..7)
+              24
+              1
+            
+            
+              TEIF6
+              Channel x transfer error flag (x = 1
+              ..7)
+              23
+              1
+            
+            
+              HTIF6
+              Channel x half transfer flag (x = 1
+              ..7)
+              22
+              1
+            
+            
+              TCIF6
+              Channel x transfer complete flag (x = 1
+              ..7)
+              21
+              1
+            
+            
+              GIF6
+              Channel x global interrupt flag (x = 1
+              ..7)
+              20
+              1
+            
+            
+              TEIF5
+              Channel x transfer error flag (x = 1
+              ..7)
+              19
+              1
+            
+            
+              HTIF5
+              Channel x half transfer flag (x = 1
+              ..7)
+              18
+              1
+            
+            
+              TCIF5
+              Channel x transfer complete flag (x = 1
+              ..7)
+              17
+              1
+            
+            
+              GIF5
+              Channel x global interrupt flag (x = 1
+              ..7)
+              16
+              1
+            
+            
+              TEIF4
+              Channel x transfer error flag (x = 1
+              ..7)
+              15
+              1
+            
+            
+              HTIF4
+              Channel x half transfer flag (x = 1
+              ..7)
+              14
+              1
+            
+            
+              TCIF4
+              Channel x transfer complete flag (x = 1
+              ..7)
+              13
+              1
+            
+            
+              GIF4
+              Channel x global interrupt flag (x = 1
+              ..7)
+              12
+              1
+            
+            
+              TEIF3
+              Channel x transfer error flag (x = 1
+              ..7)
+              11
+              1
+            
+            
+              HTIF3
+              Channel x half transfer flag (x = 1
+              ..7)
+              10
+              1
+            
+            
+              TCIF3
+              Channel x transfer complete flag (x = 1
+              ..7)
+              9
+              1
+            
+            
+              GIF3
+              Channel x global interrupt flag (x = 1
+              ..7)
+              8
+              1
+            
+            
+              TEIF2
+              Channel x transfer error flag (x = 1
+              ..7)
+              7
+              1
+            
+            
+              HTIF2
+              Channel x half transfer flag (x = 1
+              ..7)
+              6
+              1
+            
+            
+              TCIF2
+              Channel x transfer complete flag (x = 1
+              ..7)
+              5
+              1
+            
+            
+              GIF2
+              Channel x global interrupt flag (x = 1
+              ..7)
+              4
+              1
+            
+            
+              TEIF1
+              Channel x transfer error flag (x = 1
+              ..7)
+              3
+              1
+            
+            
+              HTIF1
+              Channel x half transfer flag (x = 1
+              ..7)
+              2
+              1
+            
+            
+              TCIF1
+              Channel x transfer complete flag (x = 1
+              ..7)
+              1
+              1
+            
+            
+              GIF1
+              Channel x global interrupt flag (x = 1
+              ..7)
+              0
+              1
+            
+          
+        
+        
+          IFCR
+          IFCR
+          interrupt flag clear register
+          0x4
+          0x20
+          write-only
+          0x00000000
+          
+            
+              CTEIF7
+              Channel x transfer error clear (x = 1
+              ..7)
+              27
+              1
+            
+            
+              CHTIF7
+              Channel x half transfer clear (x = 1
+              ..7)
+              26
+              1
+            
+            
+              CTCIF7
+              Channel x transfer complete clear (x = 1
+              ..7)
+              25
+              1
+            
+            
+              CGIF7
+              Channel x global interrupt clear (x = 1
+              ..7)
+              24
+              1
+            
+            
+              CTEIF6
+              Channel x transfer error clear (x = 1
+              ..7)
+              23
+              1
+            
+            
+              CHTIF6
+              Channel x half transfer clear (x = 1
+              ..7)
+              22
+              1
+            
+            
+              CTCIF6
+              Channel x transfer complete clear (x = 1
+              ..7)
+              21
+              1
+            
+            
+              CGIF6
+              Channel x global interrupt clear (x = 1
+              ..7)
+              20
+              1
+            
+            
+              CTEIF5
+              Channel x transfer error clear (x = 1
+              ..7)
+              19
+              1
+            
+            
+              CHTIF5
+              Channel x half transfer clear (x = 1
+              ..7)
+              18
+              1
+            
+            
+              CTCIF5
+              Channel x transfer complete clear (x = 1
+              ..7)
+              17
+              1
+            
+            
+              CGIF5
+              Channel x global interrupt clear (x = 1
+              ..7)
+              16
+              1
+            
+            
+              CTEIF4
+              Channel x transfer error clear (x = 1
+              ..7)
+              15
+              1
+            
+            
+              CHTIF4
+              Channel x half transfer clear (x = 1
+              ..7)
+              14
+              1
+            
+            
+              CTCIF4
+              Channel x transfer complete clear (x = 1
+              ..7)
+              13
+              1
+            
+            
+              CGIF4
+              Channel x global interrupt clear (x = 1
+              ..7)
+              12
+              1
+            
+            
+              CTEIF3
+              Channel x transfer error clear (x = 1
+              ..7)
+              11
+              1
+            
+            
+              CHTIF3
+              Channel x half transfer clear (x = 1
+              ..7)
+              10
+              1
+            
+            
+              CTCIF3
+              Channel x transfer complete clear (x = 1
+              ..7)
+              9
+              1
+            
+            
+              CGIF3
+              Channel x global interrupt clear (x = 1
+              ..7)
+              8
+              1
+            
+            
+              CTEIF2
+              Channel x transfer error clear (x = 1
+              ..7)
+              7
+              1
+            
+            
+              CHTIF2
+              Channel x half transfer clear (x = 1
+              ..7)
+              6
+              1
+            
+            
+              CTCIF2
+              Channel x transfer complete clear (x = 1
+              ..7)
+              5
+              1
+            
+            
+              CGIF2
+              Channel x global interrupt clear (x = 1
+              ..7)
+              4
+              1
+            
+            
+              CTEIF1
+              Channel x transfer error clear (x = 1
+              ..7)
+              3
+              1
+            
+            
+              CHTIF1
+              Channel x half transfer clear (x = 1
+              ..7)
+              2
+              1
+            
+            
+              CTCIF1
+              Channel x transfer complete clear (x = 1
+              ..7)
+              1
+              1
+            
+            
+              CGIF1
+              Channel x global interrupt clear (x = 1
+              ..7)
+              0
+              1
+            
+          
+        
+        
+          CCR1
+          CCR1
+          channel x configuration
+          register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR1
+          CNDTR1
+          channel x number of data
+          register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR1
+          CPAR1
+          channel x peripheral address
+          register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR1
+          CMAR1
+          channel x memory address
+          register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR2
+          CCR2
+          channel x configuration
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR2
+          CNDTR2
+          channel x number of data
+          register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR2
+          CPAR2
+          channel x peripheral address
+          register
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR2
+          CMAR2
+          channel x memory address
+          register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR3
+          CCR3
+          channel x configuration
+          register
+          0x30
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR3
+          CNDTR3
+          channel x number of data
+          register
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR3
+          CPAR3
+          channel x peripheral address
+          register
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR3
+          CMAR3
+          channel x memory address
+          register
+          0x3C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR4
+          CCR4
+          channel x configuration
+          register
+          0x44
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR4
+          CNDTR4
+          channel x number of data
+          register
+          0x48
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR4
+          CPAR4
+          channel x peripheral address
+          register
+          0x4C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR4
+          CMAR4
+          channel x memory address
+          register
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR5
+          CCR5
+          channel x configuration
+          register
+          0x58
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR5
+          CNDTR5
+          channel x number of data
+          register
+          0x5C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR5
+          CPAR5
+          channel x peripheral address
+          register
+          0x60
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR5
+          CMAR5
+          channel x memory address
+          register
+          0x64
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR6
+          CCR6
+          channel x configuration
+          register
+          0x6C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR6
+          CNDTR6
+          channel x number of data
+          register
+          0x70
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR6
+          CPAR6
+          channel x peripheral address
+          register
+          0x74
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR6
+          CMAR6
+          channel x memory address
+          register
+          0x78
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR7
+          CCR7
+          channel x configuration
+          register
+          0x80
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR7
+          CNDTR7
+          channel x number of data
+          register
+          0x84
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR7
+          CPAR7
+          channel x peripheral address
+          register
+          0x88
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR7
+          CMAR7
+          channel x memory address
+          register
+          0x8C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CSELR
+          CSELR
+          channel selection register
+          0xA8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              C7S
+              DMA channel 7 selection
+              24
+              4
+            
+            
+              C6S
+              DMA channel 6 selection
+              20
+              4
+            
+            
+              C5S
+              DMA channel 5 selection
+              16
+              4
+            
+            
+              C4S
+              DMA channel 4 selection
+              12
+              4
+            
+            
+              C3S
+              DMA channel 3 selection
+              8
+              4
+            
+            
+              C2S
+              DMA channel 2 selection
+              4
+              4
+            
+            
+              C1S
+              DMA channel 1 selection
+              0
+              4
+            
+          
+        
+      
+    
+    
+      CRC
+      Cyclic redundancy check calculation
+      unit
+      CRC
+      0x40023000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          DR
+          DR
+          Data register
+          0x0
+          0x20
+          read-write
+          0xFFFFFFFF
+          
+            
+              DR
+              Data register bits
+              0
+              32
+            
+          
+        
+        
+          IDR
+          IDR
+          Independent data register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IDR
+              General-purpose 8-bit data register
+              bits
+              0
+              8
+            
+          
+        
+        
+          CR
+          CR
+          Control register
+          0x8
+          0x20
+          0x00000000
+          
+            
+              REV_OUT
+              Reverse output data
+              7
+              1
+              read-write
+            
+            
+              REV_IN
+              Reverse input data
+              5
+              2
+              read-write
+            
+            
+              POLYSIZE
+              Polynomial size
+              3
+              2
+              read-write
+            
+            
+              RESET
+              RESET bit
+              0
+              1
+              write-only
+            
+          
+        
+        
+          INIT
+          INIT
+          Initial CRC value
+          0x10
+          0x20
+          read-write
+          0xFFFFFFFF
+          
+            
+              CRC_INIT
+              Programmable initial CRC
+              value
+              0
+              32
+            
+          
+        
+        
+          POL
+          POL
+          polynomial
+          0x14
+          0x20
+          read-write
+          0x04C11DB7
+          
+            
+              Polynomialcoefficients
+              Programmable polynomial
+              0
+              32
+            
+          
+        
+      
+    
+    
+      GPIOA
+      General-purpose I/Os
+      GPIO
+      0x50000000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          MODER
+          MODER
+          GPIO port mode register
+          0x0
+          0x20
+          read-write
+          0xEBFFFCFF
+          
+            
+              MODE0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+            
+              MODE1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              MODE2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              MODE3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              MODE4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              MODE5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              MODE6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              MODE7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              MODE8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              MODE9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              MODE10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              MODE11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              MODE12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              MODE13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              MODE14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              MODE15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+          
+        
+        
+          OTYPER
+          OTYPER
+          GPIO port output type register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OT15
+              Port x configuration bits (y =
+              0..15)
+              15
+              1
+            
+            
+              OT14
+              Port x configuration bits (y =
+              0..15)
+              14
+              1
+            
+            
+              OT13
+              Port x configuration bits (y =
+              0..15)
+              13
+              1
+            
+            
+              OT12
+              Port x configuration bits (y =
+              0..15)
+              12
+              1
+            
+            
+              OT11
+              Port x configuration bits (y =
+              0..15)
+              11
+              1
+            
+            
+              OT10
+              Port x configuration bits (y =
+              0..15)
+              10
+              1
+            
+            
+              OT9
+              Port x configuration bits (y =
+              0..15)
+              9
+              1
+            
+            
+              OT8
+              Port x configuration bits (y =
+              0..15)
+              8
+              1
+            
+            
+              OT7
+              Port x configuration bits (y =
+              0..15)
+              7
+              1
+            
+            
+              OT6
+              Port x configuration bits (y =
+              0..15)
+              6
+              1
+            
+            
+              OT5
+              Port x configuration bits (y =
+              0..15)
+              5
+              1
+            
+            
+              OT4
+              Port x configuration bits (y =
+              0..15)
+              4
+              1
+            
+            
+              OT3
+              Port x configuration bits (y =
+              0..15)
+              3
+              1
+            
+            
+              OT2
+              Port x configuration bits (y =
+              0..15)
+              2
+              1
+            
+            
+              OT1
+              Port x configuration bits (y =
+              0..15)
+              1
+              1
+            
+            
+              OT0
+              Port x configuration bits (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          OSPEEDR
+          OSPEEDR
+          GPIO port output speed
+          register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OSPEED15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              OSPEED14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              OSPEED13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              OSPEED12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              OSPEED11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              OSPEED10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              OSPEED9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              OSPEED8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              OSPEED7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              OSPEED6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              OSPEED5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              OSPEED4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              OSPEED3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              OSPEED2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              OSPEED1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              OSPEED0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          PUPDR
+          PUPDR
+          GPIO port pull-up/pull-down
+          register
+          0xC
+          0x20
+          read-write
+          0x24000000
+          
+            
+              PUPD15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              PUPD14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              PUPD13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              PUPD12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              PUPD11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              PUPD10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              PUPD9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              PUPD8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              PUPD7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              PUPD6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              PUPD5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              PUPD4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              PUPD3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              PUPD2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              PUPD1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              PUPD0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          IDR
+          IDR
+          GPIO port input data register
+          0x10
+          0x20
+          read-only
+          0x00000000
+          
+            
+              ID15
+              Port input data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              ID14
+              Port input data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              ID13
+              Port input data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              ID12
+              Port input data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              ID11
+              Port input data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              ID10
+              Port input data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              ID9
+              Port input data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              ID8
+              Port input data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              ID7
+              Port input data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              ID6
+              Port input data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              ID5
+              Port input data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              ID4
+              Port input data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              ID3
+              Port input data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              ID2
+              Port input data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              ID1
+              Port input data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              ID0
+              Port input data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          ODR
+          ODR
+          GPIO port output data register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OD15
+              Port output data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              OD14
+              Port output data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              OD13
+              Port output data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              OD12
+              Port output data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              OD11
+              Port output data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              OD10
+              Port output data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              OD9
+              Port output data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              OD8
+              Port output data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              OD7
+              Port output data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              OD6
+              Port output data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              OD5
+              Port output data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              OD4
+              Port output data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              OD3
+              Port output data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              OD2
+              Port output data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              OD1
+              Port output data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              OD0
+              Port output data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          BSRR
+          BSRR
+          GPIO port bit set/reset
+          register
+          0x18
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x reset bit y (y =
+              0..15)
+              31
+              1
+            
+            
+              BR14
+              Port x reset bit y (y =
+              0..15)
+              30
+              1
+            
+            
+              BR13
+              Port x reset bit y (y =
+              0..15)
+              29
+              1
+            
+            
+              BR12
+              Port x reset bit y (y =
+              0..15)
+              28
+              1
+            
+            
+              BR11
+              Port x reset bit y (y =
+              0..15)
+              27
+              1
+            
+            
+              BR10
+              Port x reset bit y (y =
+              0..15)
+              26
+              1
+            
+            
+              BR9
+              Port x reset bit y (y =
+              0..15)
+              25
+              1
+            
+            
+              BR8
+              Port x reset bit y (y =
+              0..15)
+              24
+              1
+            
+            
+              BR7
+              Port x reset bit y (y =
+              0..15)
+              23
+              1
+            
+            
+              BR6
+              Port x reset bit y (y =
+              0..15)
+              22
+              1
+            
+            
+              BR5
+              Port x reset bit y (y =
+              0..15)
+              21
+              1
+            
+            
+              BR4
+              Port x reset bit y (y =
+              0..15)
+              20
+              1
+            
+            
+              BR3
+              Port x reset bit y (y =
+              0..15)
+              19
+              1
+            
+            
+              BR2
+              Port x reset bit y (y =
+              0..15)
+              18
+              1
+            
+            
+              BR1
+              Port x reset bit y (y =
+              0..15)
+              17
+              1
+            
+            
+              BR0
+              Port x reset bit y (y =
+              0..15)
+              16
+              1
+            
+            
+              BS15
+              Port x set bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              BS14
+              Port x set bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              BS13
+              Port x set bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              BS12
+              Port x set bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              BS11
+              Port x set bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              BS10
+              Port x set bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              BS9
+              Port x set bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              BS8
+              Port x set bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              BS7
+              Port x set bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              BS6
+              Port x set bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              BS5
+              Port x set bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              BS4
+              Port x set bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              BS3
+              Port x set bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              BS2
+              Port x set bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              BS1
+              Port x set bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              BS0
+              Port x set bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          LCKR
+          LCKR
+          GPIO port configuration lock
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LCKK
+              Port x lock bit y (y=
+              0..15)
+              16
+              1
+            
+            
+              LCK15
+              Port x lock bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              LCK14
+              Port x lock bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              LCK13
+              Port x lock bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              LCK12
+              Port x lock bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              LCK11
+              Port x lock bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              LCK10
+              Port x lock bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              LCK9
+              Port x lock bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              LCK8
+              Port x lock bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              LCK7
+              Port x lock bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              LCK6
+              Port x lock bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              LCK5
+              Port x lock bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              LCK4
+              Port x lock bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              LCK3
+              Port x lock bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              LCK2
+              Port x lock bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              LCK1
+              Port x lock bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              LCK0
+              Port x lock bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          AFRL
+          AFRL
+          GPIO alternate function low
+          register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL7
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              28
+              4
+            
+            
+              AFSEL6
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              24
+              4
+            
+            
+              AFSEL5
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              20
+              4
+            
+            
+              AFSEL4
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              16
+              4
+            
+            
+              AFSEL3
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              12
+              4
+            
+            
+              AFSEL2
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              8
+              4
+            
+            
+              AFSEL1
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              4
+              4
+            
+            
+              AFSEL0
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              0
+              4
+            
+          
+        
+        
+          AFRH
+          AFRH
+          GPIO alternate function high
+          register
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL15
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              28
+              4
+            
+            
+              AFSEL14
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              24
+              4
+            
+            
+              AFSEL13
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              20
+              4
+            
+            
+              AFSEL12
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              16
+              4
+            
+            
+              AFSEL11
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              12
+              4
+            
+            
+              AFSEL10
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              8
+              4
+            
+            
+              AFSEL9
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              4
+              4
+            
+            
+              AFSEL8
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              0
+              4
+            
+          
+        
+        
+          BRR
+          BRR
+          GPIO port bit reset register
+          0x28
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x Reset bit y (y= 0 ..
+              15)
+              15
+              1
+            
+            
+              BR14
+              Port x Reset bit y (y= 0 ..
+              15)
+              14
+              1
+            
+            
+              BR13
+              Port x Reset bit y (y= 0 ..
+              15)
+              13
+              1
+            
+            
+              BR12
+              Port x Reset bit y (y= 0 ..
+              15)
+              12
+              1
+            
+            
+              BR11
+              Port x Reset bit y (y= 0 ..
+              15)
+              11
+              1
+            
+            
+              BR10
+              Port x Reset bit y (y= 0 ..
+              15)
+              10
+              1
+            
+            
+              BR9
+              Port x Reset bit y (y= 0 ..
+              15)
+              9
+              1
+            
+            
+              BR8
+              Port x Reset bit y (y= 0 ..
+              15)
+              8
+              1
+            
+            
+              BR7
+              Port x Reset bit y (y= 0 ..
+              15)
+              7
+              1
+            
+            
+              BR6
+              Port x Reset bit y (y= 0 ..
+              15)
+              6
+              1
+            
+            
+              BR5
+              Port x Reset bit y (y= 0 ..
+              15)
+              5
+              1
+            
+            
+              BR4
+              Port x Reset bit y (y= 0 ..
+              15)
+              4
+              1
+            
+            
+              BR3
+              Port x Reset bit y (y= 0 ..
+              15)
+              3
+              1
+            
+            
+              BR2
+              Port x Reset bit y (y= 0 ..
+              15)
+              2
+              1
+            
+            
+              BR1
+              Port x Reset bit y (y= 0 ..
+              15)
+              1
+              1
+            
+            
+              BR0
+              Port x Reset bit y (y= 0 ..
+              15)
+              0
+              1
+            
+          
+        
+      
+    
+    
+      GPIOB
+      General-purpose I/Os
+      GPIO
+      0x50000400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          MODER
+          MODER
+          GPIO port mode register
+          0x0
+          0x20
+          read-write
+          0xFFFFFFFF
+          
+            
+              MODE15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              MODE14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              MODE13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              MODE12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              MODE11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              MODE10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              MODE9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              MODE8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              MODE7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              MODE6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              MODE5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              MODE4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              MODE3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              MODE2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              MODE1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              MODE0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          OTYPER
+          OTYPER
+          GPIO port output type register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OT15
+              Port x configuration bits (y =
+              0..15)
+              15
+              1
+            
+            
+              OT14
+              Port x configuration bits (y =
+              0..15)
+              14
+              1
+            
+            
+              OT13
+              Port x configuration bits (y =
+              0..15)
+              13
+              1
+            
+            
+              OT12
+              Port x configuration bits (y =
+              0..15)
+              12
+              1
+            
+            
+              OT11
+              Port x configuration bits (y =
+              0..15)
+              11
+              1
+            
+            
+              OT10
+              Port x configuration bits (y =
+              0..15)
+              10
+              1
+            
+            
+              OT9
+              Port x configuration bits (y =
+              0..15)
+              9
+              1
+            
+            
+              OT8
+              Port x configuration bits (y =
+              0..15)
+              8
+              1
+            
+            
+              OT7
+              Port x configuration bits (y =
+              0..15)
+              7
+              1
+            
+            
+              OT6
+              Port x configuration bits (y =
+              0..15)
+              6
+              1
+            
+            
+              OT5
+              Port x configuration bits (y =
+              0..15)
+              5
+              1
+            
+            
+              OT4
+              Port x configuration bits (y =
+              0..15)
+              4
+              1
+            
+            
+              OT3
+              Port x configuration bits (y =
+              0..15)
+              3
+              1
+            
+            
+              OT2
+              Port x configuration bits (y =
+              0..15)
+              2
+              1
+            
+            
+              OT1
+              Port x configuration bits (y =
+              0..15)
+              1
+              1
+            
+            
+              OT0
+              Port x configuration bits (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          OSPEEDR
+          OSPEEDR
+          GPIO port output speed
+          register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OSPEED15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              OSPEED14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              OSPEED13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              OSPEED12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              OSPEED11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              OSPEED10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              OSPEED9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              OSPEED8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              OSPEED7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              OSPEED6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              OSPEED5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              OSPEED4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              OSPEED3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              OSPEED2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              OSPEED1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              OSPEED0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          PUPDR
+          PUPDR
+          GPIO port pull-up/pull-down
+          register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PUPD15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              PUPD14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              PUPD13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              PUPD12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              PUPD11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              PUPD10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              PUPD9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              PUPD8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              PUPD7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              PUPD6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              PUPD5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              PUPD4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              PUPD3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              PUPD2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              PUPD1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              PUPD0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          IDR
+          IDR
+          GPIO port input data register
+          0x10
+          0x20
+          read-only
+          0x00000000
+          
+            
+              ID15
+              Port input data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              ID14
+              Port input data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              ID13
+              Port input data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              ID12
+              Port input data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              ID11
+              Port input data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              ID10
+              Port input data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              ID9
+              Port input data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              ID8
+              Port input data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              ID7
+              Port input data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              ID6
+              Port input data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              ID5
+              Port input data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              ID4
+              Port input data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              ID3
+              Port input data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              ID2
+              Port input data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              ID1
+              Port input data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              ID0
+              Port input data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          ODR
+          ODR
+          GPIO port output data register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OD15
+              Port output data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              OD14
+              Port output data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              OD13
+              Port output data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              OD12
+              Port output data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              OD11
+              Port output data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              OD10
+              Port output data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              OD9
+              Port output data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              OD8
+              Port output data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              OD7
+              Port output data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              OD6
+              Port output data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              OD5
+              Port output data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              OD4
+              Port output data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              OD3
+              Port output data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              OD2
+              Port output data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              OD1
+              Port output data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              OD0
+              Port output data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          BSRR
+          BSRR
+          GPIO port bit set/reset
+          register
+          0x18
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x reset bit y (y =
+              0..15)
+              31
+              1
+            
+            
+              BR14
+              Port x reset bit y (y =
+              0..15)
+              30
+              1
+            
+            
+              BR13
+              Port x reset bit y (y =
+              0..15)
+              29
+              1
+            
+            
+              BR12
+              Port x reset bit y (y =
+              0..15)
+              28
+              1
+            
+            
+              BR11
+              Port x reset bit y (y =
+              0..15)
+              27
+              1
+            
+            
+              BR10
+              Port x reset bit y (y =
+              0..15)
+              26
+              1
+            
+            
+              BR9
+              Port x reset bit y (y =
+              0..15)
+              25
+              1
+            
+            
+              BR8
+              Port x reset bit y (y =
+              0..15)
+              24
+              1
+            
+            
+              BR7
+              Port x reset bit y (y =
+              0..15)
+              23
+              1
+            
+            
+              BR6
+              Port x reset bit y (y =
+              0..15)
+              22
+              1
+            
+            
+              BR5
+              Port x reset bit y (y =
+              0..15)
+              21
+              1
+            
+            
+              BR4
+              Port x reset bit y (y =
+              0..15)
+              20
+              1
+            
+            
+              BR3
+              Port x reset bit y (y =
+              0..15)
+              19
+              1
+            
+            
+              BR2
+              Port x reset bit y (y =
+              0..15)
+              18
+              1
+            
+            
+              BR1
+              Port x reset bit y (y =
+              0..15)
+              17
+              1
+            
+            
+              BR0
+              Port x reset bit y (y =
+              0..15)
+              16
+              1
+            
+            
+              BS15
+              Port x set bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              BS14
+              Port x set bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              BS13
+              Port x set bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              BS12
+              Port x set bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              BS11
+              Port x set bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              BS10
+              Port x set bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              BS9
+              Port x set bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              BS8
+              Port x set bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              BS7
+              Port x set bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              BS6
+              Port x set bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              BS5
+              Port x set bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              BS4
+              Port x set bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              BS3
+              Port x set bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              BS2
+              Port x set bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              BS1
+              Port x set bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              BS0
+              Port x set bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          LCKR
+          LCKR
+          GPIO port configuration lock
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LCKK
+              Port x lock bit y (y=
+              0..15)
+              16
+              1
+            
+            
+              LCK15
+              Port x lock bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              LCK14
+              Port x lock bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              LCK13
+              Port x lock bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              LCK12
+              Port x lock bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              LCK11
+              Port x lock bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              LCK10
+              Port x lock bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              LCK9
+              Port x lock bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              LCK8
+              Port x lock bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              LCK7
+              Port x lock bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              LCK6
+              Port x lock bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              LCK5
+              Port x lock bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              LCK4
+              Port x lock bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              LCK3
+              Port x lock bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              LCK2
+              Port x lock bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              LCK1
+              Port x lock bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              LCK0
+              Port x lock bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          AFRL
+          AFRL
+          GPIO alternate function low
+          register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL7
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              28
+              4
+            
+            
+              AFSEL6
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              24
+              4
+            
+            
+              AFSEL5
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              20
+              4
+            
+            
+              AFSEL4
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              16
+              4
+            
+            
+              AFSEL3
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              12
+              4
+            
+            
+              AFSEL2
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              8
+              4
+            
+            
+              AFSEL1
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              4
+              4
+            
+            
+              AFSEL0
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              0
+              4
+            
+          
+        
+        
+          AFRH
+          AFRH
+          GPIO alternate function high
+          register
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL15
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              28
+              4
+            
+            
+              AFSEL14
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              24
+              4
+            
+            
+              AFSEL13
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              20
+              4
+            
+            
+              AFSEL12
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              16
+              4
+            
+            
+              AFSEL11
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              12
+              4
+            
+            
+              AFSEL10
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              8
+              4
+            
+            
+              AFSEL9
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              4
+              4
+            
+            
+              AFSEL8
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              0
+              4
+            
+          
+        
+        
+          BRR
+          BRR
+          GPIO port bit reset register
+          0x28
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x Reset bit y (y= 0 ..
+              15)
+              15
+              1
+            
+            
+              BR14
+              Port x Reset bit y (y= 0 ..
+              15)
+              14
+              1
+            
+            
+              BR13
+              Port x Reset bit y (y= 0 ..
+              15)
+              13
+              1
+            
+            
+              BR12
+              Port x Reset bit y (y= 0 ..
+              15)
+              12
+              1
+            
+            
+              BR11
+              Port x Reset bit y (y= 0 ..
+              15)
+              11
+              1
+            
+            
+              BR10
+              Port x Reset bit y (y= 0 ..
+              15)
+              10
+              1
+            
+            
+              BR9
+              Port x Reset bit y (y= 0 ..
+              15)
+              9
+              1
+            
+            
+              BR8
+              Port x Reset bit y (y= 0 ..
+              15)
+              8
+              1
+            
+            
+              BR7
+              Port x Reset bit y (y= 0 ..
+              15)
+              7
+              1
+            
+            
+              BR6
+              Port x Reset bit y (y= 0 ..
+              15)
+              6
+              1
+            
+            
+              BR5
+              Port x Reset bit y (y= 0 ..
+              15)
+              5
+              1
+            
+            
+              BR4
+              Port x Reset bit y (y= 0 ..
+              15)
+              4
+              1
+            
+            
+              BR3
+              Port x Reset bit y (y= 0 ..
+              15)
+              3
+              1
+            
+            
+              BR2
+              Port x Reset bit y (y= 0 ..
+              15)
+              2
+              1
+            
+            
+              BR1
+              Port x Reset bit y (y= 0 ..
+              15)
+              1
+              1
+            
+            
+              BR0
+              Port x Reset bit y (y= 0 ..
+              15)
+              0
+              1
+            
+          
+        
+      
+    
+    
+      GPIOC
+      0x50000800
+    
+    
+      GPIOD
+      0x50000C00
+    
+    
+      GPIOH
+      0x50001C00
+    
+    
+      GPIOE
+      0x50001000
+    
+    
+      LPTIM
+      Low power timer
+      LPTIM
+      0x40007C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        LPTIM1
+        LPTIMER1 interrupt through
+        EXTI29
+        13
+      
+      
+        
+          ISR
+          ISR
+          Interrupt and Status Register
+          0x0
+          0x20
+          read-only
+          0x00000000
+          
+            
+              DOWN
+              Counter direction change up to
+              down
+              6
+              1
+            
+            
+              UP
+              Counter direction change down to
+              up
+              5
+              1
+            
+            
+              ARROK
+              Autoreload register update
+              OK
+              4
+              1
+            
+            
+              CMPOK
+              Compare register update OK
+              3
+              1
+            
+            
+              EXTTRIG
+              External trigger edge
+              event
+              2
+              1
+            
+            
+              ARRM
+              Autoreload match
+              1
+              1
+            
+            
+              CMPM
+              Compare match
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt Clear Register
+          0x4
+          0x20
+          write-only
+          0x00000000
+          
+            
+              DOWNCF
+              Direction change to down Clear
+              Flag
+              6
+              1
+            
+            
+              UPCF
+              Direction change to UP Clear
+              Flag
+              5
+              1
+            
+            
+              ARROKCF
+              Autoreload register update OK Clear
+              Flag
+              4
+              1
+            
+            
+              CMPOKCF
+              Compare register update OK Clear
+              Flag
+              3
+              1
+            
+            
+              EXTTRIGCF
+              External trigger valid edge Clear
+              Flag
+              2
+              1
+            
+            
+              ARRMCF
+              Autoreload match Clear
+              Flag
+              1
+              1
+            
+            
+              CMPMCF
+              compare match Clear Flag
+              0
+              1
+            
+          
+        
+        
+          IER
+          IER
+          Interrupt Enable Register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DOWNIE
+              Direction change to down Interrupt
+              Enable
+              6
+              1
+            
+            
+              UPIE
+              Direction change to UP Interrupt
+              Enable
+              5
+              1
+            
+            
+              ARROKIE
+              Autoreload register update OK Interrupt
+              Enable
+              4
+              1
+            
+            
+              CMPOKIE
+              Compare register update OK Interrupt
+              Enable
+              3
+              1
+            
+            
+              EXTTRIGIE
+              External trigger valid edge Interrupt
+              Enable
+              2
+              1
+            
+            
+              ARRMIE
+              Autoreload match Interrupt
+              Enable
+              1
+              1
+            
+            
+              CMPMIE
+              Compare match Interrupt
+              Enable
+              0
+              1
+            
+          
+        
+        
+          CFGR
+          CFGR
+          Configuration Register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ENC
+              Encoder mode enable
+              24
+              1
+            
+            
+              COUNTMODE
+              counter mode enabled
+              23
+              1
+            
+            
+              PRELOAD
+              Registers update mode
+              22
+              1
+            
+            
+              WAVPOL
+              Waveform shape polarity
+              21
+              1
+            
+            
+              WAVE
+              Waveform shape
+              20
+              1
+            
+            
+              TIMOUT
+              Timeout enable
+              19
+              1
+            
+            
+              TRIGEN
+              Trigger enable and
+              polarity
+              17
+              2
+            
+            
+              TRIGSEL
+              Trigger selector
+              13
+              3
+            
+            
+              PRESC
+              Clock prescaler
+              9
+              3
+            
+            
+              TRGFLT
+              Configurable digital filter for
+              trigger
+              6
+              2
+            
+            
+              CKFLT
+              Configurable digital filter for external
+              clock
+              3
+              2
+            
+            
+              CKPOL
+              Clock Polarity
+              1
+              2
+            
+            
+              CKSEL
+              Clock selector
+              0
+              1
+            
+          
+        
+        
+          CR
+          CR
+          Control Register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNTSTRT
+              Timer start in continuous
+              mode
+              2
+              1
+            
+            
+              SNGSTRT
+              LPTIM start in single mode
+              1
+              1
+            
+            
+              ENABLE
+              LPTIM Enable
+              0
+              1
+            
+          
+        
+        
+          CMP
+          CMP
+          Compare Register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CMP
+              Compare value.
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          Autoreload Register
+          0x18
+          0x20
+          read-write
+          0x00000001
+          
+            
+              ARR
+              Auto reload value.
+              0
+              16
+            
+          
+        
+        
+          CNT
+          CNT
+          Counter Register
+          0x1C
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value.
+              0
+              16
+            
+          
+        
+      
+    
+    
+      RTC
+      Real-time clock
+      RTC
+      0x40002800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        RTC
+        RTC global interrupt
+        2
+      
+      
+        
+          TR
+          TR
+          RTC time register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format
+              16
+              4
+            
+            
+              MNT
+              Minute tens in BCD format
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD format
+              8
+              4
+            
+            
+              ST
+              Second tens in BCD format
+              4
+              3
+            
+            
+              SU
+              Second units in BCD format
+              0
+              4
+            
+          
+        
+        
+          DR
+          DR
+          RTC date register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              YT
+              Year tens in BCD format
+              20
+              4
+            
+            
+              YU
+              Year units in BCD format
+              16
+              4
+            
+            
+              WDU
+              Week day units
+              13
+              3
+            
+            
+              MT
+              Month tens in BCD format
+              12
+              1
+            
+            
+              MU
+              Month units in BCD format
+              8
+              4
+            
+            
+              DT
+              Date tens in BCD format
+              4
+              2
+            
+            
+              DU
+              Date units in BCD format
+              0
+              4
+            
+          
+        
+        
+          CR
+          CR
+          RTC control register
+          0x8
+          0x20
+          0x00000000
+          
+            
+              COE
+              Calibration output enable
+              23
+              1
+              read-write
+            
+            
+              OSEL
+              Output selection
+              21
+              2
+              read-write
+            
+            
+              POL
+              Output polarity
+              20
+              1
+              read-write
+            
+            
+              COSEL
+              Calibration output
+              selection
+              19
+              1
+              read-write
+            
+            
+              BKP
+              Backup
+              18
+              1
+              read-write
+            
+            
+              SUB1H
+              Subtract 1 hour (winter time
+              change)
+              17
+              1
+              write-only
+            
+            
+              ADD1H
+              Add 1 hour (summer time
+              change)
+              16
+              1
+              write-only
+            
+            
+              TSIE
+              Time-stamp interrupt
+              enable
+              15
+              1
+              read-write
+            
+            
+              WUTIE
+              Wakeup timer interrupt
+              enable
+              14
+              1
+              read-write
+            
+            
+              ALRBIE
+              Alarm B interrupt enable
+              13
+              1
+              read-write
+            
+            
+              ALRAIE
+              Alarm A interrupt enable
+              12
+              1
+              read-write
+            
+            
+              TSE
+              timestamp enable
+              11
+              1
+              read-write
+            
+            
+              WUTE
+              Wakeup timer enable
+              10
+              1
+              read-write
+            
+            
+              ALRBE
+              Alarm B enable
+              9
+              1
+              read-write
+            
+            
+              ALRAE
+              Alarm A enable
+              8
+              1
+              read-write
+            
+            
+              FMT
+              Hour format
+              6
+              1
+              read-write
+            
+            
+              BYPSHAD
+              Bypass the shadow
+              registers
+              5
+              1
+              read-write
+            
+            
+              REFCKON
+              RTC_REFIN reference clock detection
+              enable (50 or 60 Hz)
+              4
+              1
+              read-write
+            
+            
+              TSEDGE
+              Time-stamp event active
+              edge
+              3
+              1
+              read-write
+            
+            
+              WUCKSEL
+              Wakeup clock selection
+              0
+              3
+              read-write
+            
+          
+        
+        
+          ISR
+          ISR
+          RTC initialization and status
+          register
+          0xC
+          0x20
+          0x00000000
+          
+            
+              TAMP2F
+              RTC_TAMP2 detection flag
+              14
+              1
+              read-write
+            
+            
+              TAMP1F
+              RTC_TAMP1 detection flag
+              13
+              1
+              read-write
+            
+            
+              TSOVF
+              Time-stamp overflow flag
+              12
+              1
+              read-write
+            
+            
+              TSF
+              Time-stamp flag
+              11
+              1
+              read-write
+            
+            
+              WUTF
+              Wakeup timer flag
+              10
+              1
+              read-write
+            
+            
+              ALRBF
+              Alarm B flag
+              9
+              1
+              read-write
+            
+            
+              ALRAF
+              Alarm A flag
+              8
+              1
+              read-write
+            
+            
+              INIT
+              Initialization mode
+              7
+              1
+              read-write
+            
+            
+              INITF
+              Initialization flag
+              6
+              1
+              read-only
+            
+            
+              RSF
+              Registers synchronization
+              flag
+              5
+              1
+              read-write
+            
+            
+              INITS
+              Initialization status flag
+              4
+              1
+              read-only
+            
+            
+              SHPF
+              Shift operation pending
+              3
+              1
+              read-only
+            
+            
+              WUTWF
+              Wakeup timer write flag
+              2
+              1
+              read-only
+            
+            
+              ALRBWF
+              Alarm B write flag
+              1
+              1
+              read-only
+            
+            
+              ALRAWF
+              Alarm A write flag
+              0
+              1
+              read-only
+            
+          
+        
+        
+          PRER
+          PRER
+          RTC prescaler register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PREDIV_A
+              Asynchronous prescaler
+              factor
+              16
+              7
+            
+            
+              PREDIV_S
+              Synchronous prescaler
+              factor
+              0
+              16
+            
+          
+        
+        
+          WUTR
+          WUTR
+          RTC wakeup timer register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              WUT
+              Wakeup auto-reload value
+              bits
+              0
+              16
+            
+          
+        
+        
+          ALRMAR
+          ALRMAR
+          RTC alarm A register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MSK4
+              Alarm A date mask
+              31
+              1
+            
+            
+              WDSEL
+              Week day selection
+              30
+              1
+            
+            
+              DT
+              Date tens in BCD format.
+              28
+              2
+            
+            
+              DU
+              Date units or day in BCD
+              format.
+              24
+              4
+            
+            
+              MSK3
+              Alarm A hours mask
+              23
+              1
+            
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format.
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format.
+              16
+              4
+            
+            
+              MSK2
+              Alarm A minutes mask
+              15
+              1
+            
+            
+              MNT
+              Minute tens in BCD format.
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD
+              format.
+              8
+              4
+            
+            
+              MSK1
+              Alarm A seconds mask
+              7
+              1
+            
+            
+              ST
+              Second tens in BCD format.
+              4
+              3
+            
+            
+              SU
+              Second units in BCD
+              format.
+              0
+              4
+            
+          
+        
+        
+          ALRMBR
+          ALRMBR
+          RTC alarm B register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MSK4
+              Alarm B date mask
+              31
+              1
+            
+            
+              WDSEL
+              Week day selection
+              30
+              1
+            
+            
+              DT
+              Date tens in BCD format
+              28
+              2
+            
+            
+              DU
+              Date units or day in BCD
+              format
+              24
+              4
+            
+            
+              MSK3
+              Alarm B hours mask
+              23
+              1
+            
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format
+              16
+              4
+            
+            
+              MSK2
+              Alarm B minutes mask
+              15
+              1
+            
+            
+              MNT
+              Minute tens in BCD format
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD format
+              8
+              4
+            
+            
+              MSK1
+              Alarm B seconds mask
+              7
+              1
+            
+            
+              ST
+              Second tens in BCD format
+              4
+              3
+            
+            
+              SU
+              Second units in BCD format
+              0
+              4
+            
+          
+        
+        
+          WPR
+          WPR
+          write protection register
+          0x24
+          0x20
+          write-only
+          0x00000000
+          
+            
+              KEY
+              Write protection key
+              0
+              8
+            
+          
+        
+        
+          SSR
+          SSR
+          RTC sub second register
+          0x28
+          0x20
+          read-only
+          0x00000000
+          
+            
+              SS
+              Sub second value
+              0
+              16
+            
+          
+        
+        
+          SHIFTR
+          SHIFTR
+          RTC shift control register
+          0x2C
+          0x20
+          write-only
+          0x00000000
+          
+            
+              ADD1S
+              Add one second
+              31
+              1
+            
+            
+              SUBFS
+              Subtract a fraction of a
+              second
+              0
+              15
+            
+          
+        
+        
+          TSTR
+          TSTR
+          RTC timestamp time register
+          0x30
+          0x20
+          read-only
+          0x00000000
+          
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format.
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format.
+              16
+              4
+            
+            
+              MNT
+              Minute tens in BCD format.
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD
+              format.
+              8
+              4
+            
+            
+              ST
+              Second tens in BCD format.
+              4
+              3
+            
+            
+              SU
+              Second units in BCD
+              format.
+              0
+              4
+            
+          
+        
+        
+          TSDR
+          TSDR
+          RTC timestamp date register
+          0x34
+          0x20
+          read-only
+          0x00000000
+          
+            
+              WDU
+              Week day units
+              13
+              3
+            
+            
+              MT
+              Month tens in BCD format
+              12
+              1
+            
+            
+              MU
+              Month units in BCD format
+              8
+              4
+            
+            
+              DT
+              Date tens in BCD format
+              4
+              2
+            
+            
+              DU
+              Date units in BCD format
+              0
+              4
+            
+          
+        
+        
+          TSSSR
+          TSSSR
+          RTC time-stamp sub second
+          register
+          0x38
+          0x20
+          read-only
+          0x00000000
+          
+            
+              SS
+              Sub second value
+              0
+              16
+            
+          
+        
+        
+          CALR
+          CALR
+          RTC calibration register
+          0x3C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CALP
+              Increase frequency of RTC by 488.5
+              ppm
+              15
+              1
+            
+            
+              CALW8
+              Use an 8-second calibration cycle
+              period
+              14
+              1
+            
+            
+              CALW16
+              Use a 16-second calibration cycle
+              period
+              13
+              1
+            
+            
+              CALM
+              Calibration minus
+              0
+              9
+            
+          
+        
+        
+          TAMPCR
+          TAMPCR
+          RTC tamper configuration
+          register
+          0x40
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TAMP2MF
+              Tamper 2 mask flag
+              21
+              1
+            
+            
+              TAMP2NOERASE
+              Tamper 2 no erase
+              20
+              1
+            
+            
+              TAMP2IE
+              Tamper 2 interrupt enable
+              19
+              1
+            
+            
+              TAMP1MF
+              Tamper 1 mask flag
+              18
+              1
+            
+            
+              TAMP1NOERASE
+              Tamper 1 no erase
+              17
+              1
+            
+            
+              TAMP1IE
+              Tamper 1 interrupt enable
+              16
+              1
+            
+            
+              TAMPPUDIS
+              RTC_TAMPx pull-up disable
+              15
+              1
+            
+            
+              TAMPPRCH
+              RTC_TAMPx precharge
+              duration
+              13
+              2
+            
+            
+              TAMPFLT
+              RTC_TAMPx filter count
+              11
+              2
+            
+            
+              TAMPFREQ
+              Tamper sampling frequency
+              8
+              3
+            
+            
+              TAMPTS
+              Activate timestamp on tamper detection
+              event
+              7
+              1
+            
+            
+              TAMP2_TRG
+              Active level for RTC_TAMP2
+              input
+              4
+              1
+            
+            
+              TAMP2E
+              RTC_TAMP2 input detection
+              enable
+              3
+              1
+            
+            
+              TAMPIE
+              Tamper interrupt enable
+              2
+              1
+            
+            
+              TAMP1TRG
+              Active level for RTC_TAMP1
+              input
+              1
+              1
+            
+            
+              TAMP1E
+              RTC_TAMP1 input detection
+              enable
+              0
+              1
+            
+          
+        
+        
+          ALRMASSR
+          ALRMASSR
+          RTC alarm A sub second
+          register
+          0x44
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MASKSS
+              Mask the most-significant bits starting
+              at this bit
+              24
+              4
+            
+            
+              SS
+              Sub seconds value
+              0
+              15
+            
+          
+        
+        
+          ALRMBSSR
+          ALRMBSSR
+          RTC alarm B sub second
+          register
+          0x48
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MASKSS
+              Mask the most-significant bits starting
+              at this bit
+              24
+              4
+            
+            
+              SS
+              Sub seconds value
+              0
+              15
+            
+          
+        
+        
+          OR
+          OR
+          option register
+          0x4C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              RTC_OUT_RMP
+              RTC_ALARM on PC13 output
+              type
+              1
+              1
+            
+            
+              RTC_ALARM_TYPE
+              RTC_ALARM on PC13 output
+              type
+              0
+              1
+            
+          
+        
+        
+          BKP0R
+          BKP0R
+          RTC backup registers
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP1R
+          BKP1R
+          RTC backup registers
+          0x54
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP2R
+          BKP2R
+          RTC backup registers
+          0x58
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP3R
+          BKP3R
+          RTC backup registers
+          0x5C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP4R
+          BKP4R
+          RTC backup registers
+          0x60
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+      
+    
+    
+      USART1
+      Universal synchronous asynchronous receiver
+      transmitter
+      USART
+      0x40013800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        USART1
+        USART1 global interrupt
+        27
+      
+      
+        
+          CR1
+          CR1
+          Control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              M1
+              Word length
+              28
+              1
+            
+            
+              EOBIE
+              End of Block interrupt
+              enable
+              27
+              1
+            
+            
+              RTOIE
+              Receiver timeout interrupt
+              enable
+              26
+              1
+            
+            
+              DEAT4
+              Driver Enable assertion
+              time
+              25
+              1
+            
+            
+              DEAT3
+              DEAT3
+              24
+              1
+            
+            
+              DEAT2
+              DEAT2
+              23
+              1
+            
+            
+              DEAT1
+              DEAT1
+              22
+              1
+            
+            
+              DEAT0
+              DEAT0
+              21
+              1
+            
+            
+              DEDT4
+              Driver Enable de-assertion
+              time
+              20
+              1
+            
+            
+              DEDT3
+              DEDT3
+              19
+              1
+            
+            
+              DEDT2
+              DEDT2
+              18
+              1
+            
+            
+              DEDT1
+              DEDT1
+              17
+              1
+            
+            
+              DEDT0
+              DEDT0
+              16
+              1
+            
+            
+              OVER8
+              Oversampling mode
+              15
+              1
+            
+            
+              CMIE
+              Character match interrupt
+              enable
+              14
+              1
+            
+            
+              MME
+              Mute mode enable
+              13
+              1
+            
+            
+              M0
+              Word length
+              12
+              1
+            
+            
+              WAKE
+              Receiver wakeup method
+              11
+              1
+            
+            
+              PCE
+              Parity control enable
+              10
+              1
+            
+            
+              PS
+              Parity selection
+              9
+              1
+            
+            
+              PEIE
+              PE interrupt enable
+              8
+              1
+            
+            
+              TXEIE
+              interrupt enable
+              7
+              1
+            
+            
+              TCIE
+              Transmission complete interrupt
+              enable
+              6
+              1
+            
+            
+              RXNEIE
+              RXNE interrupt enable
+              5
+              1
+            
+            
+              IDLEIE
+              IDLE interrupt enable
+              4
+              1
+            
+            
+              TE
+              Transmitter enable
+              3
+              1
+            
+            
+              RE
+              Receiver enable
+              2
+              1
+            
+            
+              UESM
+              USART enable in Stop mode
+              1
+              1
+            
+            
+              UE
+              USART enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          Control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              ADD4_7
+              Address of the USART node
+              28
+              4
+            
+            
+              ADD0_3
+              Address of the USART node
+              24
+              4
+            
+            
+              RTOEN
+              Receiver timeout enable
+              23
+              1
+            
+            
+              ABRMOD1
+              Auto baud rate mode
+              22
+              1
+            
+            
+              ABRMOD0
+              ABRMOD0
+              21
+              1
+            
+            
+              ABREN
+              Auto baud rate enable
+              20
+              1
+            
+            
+              MSBFIRST
+              Most significant bit first
+              19
+              1
+            
+            
+              TAINV
+              Binary data inversion
+              18
+              1
+            
+            
+              TXINV
+              TX pin active level
+              inversion
+              17
+              1
+            
+            
+              RXINV
+              RX pin active level
+              inversion
+              16
+              1
+            
+            
+              SWAP
+              Swap TX/RX pins
+              15
+              1
+            
+            
+              LINEN
+              LIN mode enable
+              14
+              1
+            
+            
+              STOP
+              STOP bits
+              12
+              2
+            
+            
+              CLKEN
+              Clock enable
+              11
+              1
+            
+            
+              CPOL
+              Clock polarity
+              10
+              1
+            
+            
+              CPHA
+              Clock phase
+              9
+              1
+            
+            
+              LBCL
+              Last bit clock pulse
+              8
+              1
+            
+            
+              LBDIE
+              LIN break detection interrupt
+              enable
+              6
+              1
+            
+            
+              LBDL
+              LIN break detection length
+              5
+              1
+            
+            
+              ADDM7
+              7-bit Address Detection/4-bit Address
+              Detection
+              4
+              1
+            
+          
+        
+        
+          CR3
+          CR3
+          Control register 3
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              WUFIE
+              Wakeup from Stop mode interrupt
+              enable
+              22
+              1
+            
+            
+              WUS
+              Wakeup from Stop mode interrupt flag
+              selection
+              20
+              2
+            
+            
+              SCARCNT
+              Smartcard auto-retry count
+              17
+              3
+            
+            
+              DEP
+              Driver enable polarity
+              selection
+              15
+              1
+            
+            
+              DEM
+              Driver enable mode
+              14
+              1
+            
+            
+              DDRE
+              DMA Disable on Reception
+              Error
+              13
+              1
+            
+            
+              OVRDIS
+              Overrun Disable
+              12
+              1
+            
+            
+              ONEBIT
+              One sample bit method
+              enable
+              11
+              1
+            
+            
+              CTSIE
+              CTS interrupt enable
+              10
+              1
+            
+            
+              CTSE
+              CTS enable
+              9
+              1
+            
+            
+              RTSE
+              RTS enable
+              8
+              1
+            
+            
+              DMAT
+              DMA enable transmitter
+              7
+              1
+            
+            
+              DMAR
+              DMA enable receiver
+              6
+              1
+            
+            
+              SCEN
+              Smartcard mode enable
+              5
+              1
+            
+            
+              NACK
+              Smartcard NACK enable
+              4
+              1
+            
+            
+              HDSEL
+              Half-duplex selection
+              3
+              1
+            
+            
+              IRLP
+              Ir low-power
+              2
+              1
+            
+            
+              IREN
+              Ir mode enable
+              1
+              1
+            
+            
+              EIE
+              Error interrupt enable
+              0
+              1
+            
+          
+        
+        
+          BRR
+          BRR
+          Baud rate register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              DIV_Mantissa
+              DIV_Mantissa
+              4
+              12
+            
+            
+              DIV_Fraction
+              DIV_Fraction
+              0
+              4
+            
+          
+        
+        
+          GTPR
+          GTPR
+          Guard time and prescaler
+          register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              GT
+              Guard time value
+              8
+              8
+            
+            
+              PSC
+              Prescaler value
+              0
+              8
+            
+          
+        
+        
+          RTOR
+          RTOR
+          Receiver timeout register
+          0x14
+          0x20
+          read-write
+          0x0000
+          
+            
+              BLEN
+              Block Length
+              24
+              8
+            
+            
+              RTO
+              Receiver timeout value
+              0
+              24
+            
+          
+        
+        
+          RQR
+          RQR
+          Request register
+          0x18
+          0x20
+          write-only
+          0x0000
+          
+            
+              TXFRQ
+              Transmit data flush
+              request
+              4
+              1
+            
+            
+              RXFRQ
+              Receive data flush request
+              3
+              1
+            
+            
+              MMRQ
+              Mute mode request
+              2
+              1
+            
+            
+              SBKRQ
+              Send break request
+              1
+              1
+            
+            
+              ABRRQ
+              Auto baud rate request
+              0
+              1
+            
+          
+        
+        
+          ISR
+          ISR
+          Interrupt & status
+          register
+          0x1C
+          0x20
+          read-only
+          0x00C0
+          
+            
+              REACK
+              REACK
+              22
+              1
+            
+            
+              TEACK
+              TEACK
+              21
+              1
+            
+            
+              WUF
+              WUF
+              20
+              1
+            
+            
+              RWU
+              RWU
+              19
+              1
+            
+            
+              SBKF
+              SBKF
+              18
+              1
+            
+            
+              CMF
+              CMF
+              17
+              1
+            
+            
+              BUSY
+              BUSY
+              16
+              1
+            
+            
+              ABRF
+              ABRF
+              15
+              1
+            
+            
+              ABRE
+              ABRE
+              14
+              1
+            
+            
+              EOBF
+              EOBF
+              12
+              1
+            
+            
+              RTOF
+              RTOF
+              11
+              1
+            
+            
+              CTS
+              CTS
+              10
+              1
+            
+            
+              CTSIF
+              CTSIF
+              9
+              1
+            
+            
+              LBDF
+              LBDF
+              8
+              1
+            
+            
+              TXE
+              TXE
+              7
+              1
+            
+            
+              TC
+              TC
+              6
+              1
+            
+            
+              RXNE
+              RXNE
+              5
+              1
+            
+            
+              IDLE
+              IDLE
+              4
+              1
+            
+            
+              ORE
+              ORE
+              3
+              1
+            
+            
+              NF
+              NF
+              2
+              1
+            
+            
+              FE
+              FE
+              1
+              1
+            
+            
+              PE
+              PE
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt flag clear register
+          0x20
+          0x20
+          write-only
+          0x0000
+          
+            
+              WUCF
+              Wakeup from Stop mode clear
+              flag
+              20
+              1
+            
+            
+              CMCF
+              Character match clear flag
+              17
+              1
+            
+            
+              EOBCF
+              End of block clear flag
+              12
+              1
+            
+            
+              RTOCF
+              Receiver timeout clear
+              flag
+              11
+              1
+            
+            
+              CTSCF
+              CTS clear flag
+              9
+              1
+            
+            
+              LBDCF
+              LIN break detection clear
+              flag
+              8
+              1
+            
+            
+              TCCF
+              Transmission complete clear
+              flag
+              6
+              1
+            
+            
+              IDLECF
+              Idle line detected clear
+              flag
+              4
+              1
+            
+            
+              ORECF
+              Overrun error clear flag
+              3
+              1
+            
+            
+              NCF
+              Noise detected clear flag
+              2
+              1
+            
+            
+              FECF
+              Framing error clear flag
+              1
+              1
+            
+            
+              PECF
+              Parity error clear flag
+              0
+              1
+            
+          
+        
+        
+          RDR
+          RDR
+          Receive data register
+          0x24
+          0x20
+          read-only
+          0x0000
+          
+            
+              RDR
+              Receive data value
+              0
+              9
+            
+          
+        
+        
+          TDR
+          TDR
+          Transmit data register
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              TDR
+              Transmit data value
+              0
+              9
+            
+          
+        
+      
+    
+    
+      USART2
+      0x40004400
+    
+    
+      USART4
+      0x40004C00
+      
+        USART4_USART5
+        USART4/USART5 global interrupt
+        14
+      
+    
+    
+      USART5
+      0x40005000
+      
+        USART2
+        USART2 global interrupt
+        28
+      
+    
+    
+      IWDG
+      Independent watchdog
+      IWDG
+      0x40003000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          KR
+          KR
+          Key register
+          0x0
+          0x20
+          write-only
+          0x00000000
+          
+            
+              KEY
+              Key value (write only, read
+              0x0000)
+              0
+              16
+            
+          
+        
+        
+          PR
+          PR
+          Prescaler register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PR
+              Prescaler divider
+              0
+              3
+            
+          
+        
+        
+          RLR
+          RLR
+          Reload register
+          0x8
+          0x20
+          read-write
+          0x00000FFF
+          
+            
+              RL
+              Watchdog counter reload
+              value
+              0
+              12
+            
+          
+        
+        
+          SR
+          SR
+          Status register
+          0xC
+          0x20
+          read-only
+          0x00000000
+          
+            
+              WVU
+              Watchdog counter window value
+              update
+              2
+              1
+            
+            
+              RVU
+              Watchdog counter reload value
+              update
+              1
+              1
+            
+            
+              PVU
+              Watchdog prescaler value
+              update
+              0
+              1
+            
+          
+        
+        
+          WINR
+          WINR
+          Window register
+          0x10
+          0x20
+          read-write
+          0x00000FFF
+          
+            
+              WIN
+              Watchdog counter window
+              value
+              0
+              12
+            
+          
+        
+      
+    
+    
+      WWDG
+      System window watchdog
+      WWDG
+      0x40002C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        WWDG
+        Window Watchdog interrupt
+        0
+      
+      
+        
+          CR
+          CR
+          Control register
+          0x0
+          0x20
+          read-write
+          0x0000007F
+          
+            
+              WDGA
+              Activation bit
+              7
+              1
+            
+            
+              T
+              7-bit counter (MSB to LSB)
+              0
+              7
+            
+          
+        
+        
+          CFR
+          CFR
+          Configuration register
+          0x4
+          0x20
+          read-write
+          0x0000007F
+          
+            
+              EWI
+              Early wakeup interrupt
+              9
+              1
+            
+            
+              WDGTB1
+              Timer base
+              8
+              1
+            
+            
+              WDGTB0
+              WDGTB0
+              7
+              1
+            
+            
+              W
+              7-bit window value
+              0
+              7
+            
+          
+        
+        
+          SR
+          SR
+          Status register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EWIF
+              Early wakeup interrupt
+              flag
+              0
+              1
+            
+          
+        
+      
+    
+    
+      Firewall
+      Firewall
+      Firewall
+      0x40011C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          FIREWALL_CSSA
+          FIREWALL_CSSA
+          Code segment start address
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADD
+              code segment start address
+              8
+              16
+            
+          
+        
+        
+          FIREWALL_CSL
+          FIREWALL_CSL
+          Code segment length
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LENG
+              code segment length
+              8
+              14
+            
+          
+        
+        
+          FIREWALL_NVDSSA
+          FIREWALL_NVDSSA
+          Non-volatile data segment start
+          address
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADD
+              Non-volatile data segment start
+              address
+              8
+              16
+            
+          
+        
+        
+          FIREWALL_NVDSL
+          FIREWALL_NVDSL
+          Non-volatile data segment
+          length
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LENG
+              Non-volatile data segment
+              length
+              8
+              14
+            
+          
+        
+        
+          FIREWALL_VDSSA
+          FIREWALL_VDSSA
+          Volatile data segment start
+          address
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADD
+              Volatile data segment start
+              address
+              6
+              10
+            
+          
+        
+        
+          FIREWALL_VDSL
+          FIREWALL_VDSL
+          Volatile data segment length
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LENG
+              Non-volatile data segment
+              length
+              6
+              10
+            
+          
+        
+        
+          FIREWALL_CR
+          FIREWALL_CR
+          Configuration register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              VDE
+              Volatile data execution
+              2
+              1
+            
+            
+              VDS
+              Volatile data shared
+              1
+              1
+            
+            
+              FPA
+              Firewall pre alarm
+              0
+              1
+            
+          
+        
+      
+    
+    
+      RCC
+      Reset and clock control
+      RCC
+      0x40021000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        RCC
+        RCC global interrupt
+        4
+      
+      
+        
+          CR
+          CR
+          Clock control register
+          0x0
+          0x20
+          0x00000300
+          
+            
+              PLLRDY
+              PLL clock ready flag
+              25
+              1
+              read-only
+            
+            
+              PLLON
+              PLL enable bit
+              24
+              1
+              read-write
+            
+            
+              RTCPRE
+              TC/LCD prescaler
+              20
+              2
+              read-write
+            
+            
+              CSSLSEON
+              Clock security system on HSE enable
+              bit
+              19
+              1
+              read-write
+            
+            
+              HSEBYP
+              HSE clock bypass bit
+              18
+              1
+              read-write
+            
+            
+              HSERDY
+              HSE clock ready flag
+              17
+              1
+              read-only
+            
+            
+              HSEON
+              HSE clock enable bit
+              16
+              1
+              read-write
+            
+            
+              MSIRDY
+              MSI clock ready flag
+              9
+              1
+              read-only
+            
+            
+              MSION
+              MSI clock enable bit
+              8
+              1
+              read-write
+            
+            
+              HSI16DIVF
+              HSI16DIVF
+              4
+              1
+              read-only
+            
+            
+              HSI16DIVEN
+              HSI16DIVEN
+              3
+              1
+              read-write
+            
+            
+              HSI16RDYF
+              Internal high-speed clock ready
+              flag
+              2
+              1
+              read-write
+            
+            
+              HSI16KERON
+              High-speed internal clock enable bit for
+              some IP kernels
+              1
+              1
+              read-only
+            
+            
+              HSI16ON
+              16 MHz high-speed internal clock
+              enable
+              0
+              1
+              read-write
+            
+            
+              HSI16OUTEN
+              16 MHz high-speed internal clock output
+              enable
+              5
+              1
+              read-write
+            
+          
+        
+        
+          ICSCR
+          ICSCR
+          Internal clock sources calibration
+          register
+          0x4
+          0x20
+          0x0000B000
+          
+            
+              MSITRIM
+              MSI clock trimming
+              24
+              8
+              read-write
+            
+            
+              MSICAL
+              MSI clock calibration
+              16
+              8
+              read-only
+            
+            
+              MSIRANGE
+              MSI clock ranges
+              13
+              3
+              read-write
+            
+            
+              HSI16TRIM
+              High speed internal clock
+              trimming
+              8
+              5
+              read-write
+            
+            
+              HSI16CAL
+              nternal high speed clock
+              calibration
+              0
+              8
+              read-only
+            
+          
+        
+        
+          CFGR
+          CFGR
+          Clock configuration register
+          0xC
+          0x20
+          0x00000000
+          
+            
+              MCOPRE
+              Microcontroller clock output
+              prescaler
+              28
+              3
+              read-write
+            
+            
+              MCOSEL
+              Microcontroller clock output
+              selection
+              24
+              3
+              read-write
+            
+            
+              PLLDIV
+              PLL output division
+              22
+              2
+              read-write
+            
+            
+              PLLMUL
+              PLL multiplication factor
+              18
+              4
+              read-write
+            
+            
+              PLLSRC
+              PLL entry clock source
+              16
+              1
+              read-write
+            
+            
+              STOPWUCK
+              Wake-up from stop clock
+              selection
+              15
+              1
+              read-write
+            
+            
+              PPRE2
+              APB high-speed prescaler
+              (APB2)
+              11
+              3
+              read-write
+            
+            
+              PPRE1
+              APB low-speed prescaler
+              (APB1)
+              8
+              3
+              read-write
+            
+            
+              HPRE
+              AHB prescaler
+              4
+              4
+              read-write
+            
+            
+              SWS
+              System clock switch status
+              2
+              2
+              read-only
+            
+            
+              SW
+              System clock switch
+              0
+              2
+              read-write
+            
+          
+        
+        
+          CIER
+          CIER
+          Clock interrupt enable
+          register
+          0x10
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CSSLSE
+              LSE CSS interrupt flag
+              7
+              1
+            
+            
+              MSIRDYIE
+              MSI ready interrupt flag
+              5
+              1
+            
+            
+              PLLRDYIE
+              PLL ready interrupt flag
+              4
+              1
+            
+            
+              HSERDYIE
+              HSE ready interrupt flag
+              3
+              1
+            
+            
+              HSI16RDYIE
+              HSI16 ready interrupt flag
+              2
+              1
+            
+            
+              LSERDYIE
+              LSE ready interrupt flag
+              1
+              1
+            
+            
+              LSIRDYIE
+              LSI ready interrupt flag
+              0
+              1
+            
+          
+        
+        
+          CIFR
+          CIFR
+          Clock interrupt flag register
+          0x14
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CSSHSEF
+              Clock Security System Interrupt
+              flag
+              8
+              1
+            
+            
+              CSSLSEF
+              LSE Clock Security System Interrupt
+              flag
+              7
+              1
+            
+            
+              MSIRDYF
+              MSI ready interrupt flag
+              5
+              1
+            
+            
+              PLLRDYF
+              PLL ready interrupt flag
+              4
+              1
+            
+            
+              HSERDYF
+              HSE ready interrupt flag
+              3
+              1
+            
+            
+              HSI16RDYF
+              HSI16 ready interrupt flag
+              2
+              1
+            
+            
+              LSERDYF
+              LSE ready interrupt flag
+              1
+              1
+            
+            
+              LSIRDYF
+              LSI ready interrupt flag
+              0
+              1
+            
+          
+        
+        
+          CICR
+          CICR
+          Clock interrupt clear register
+          0x18
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CSSHSEC
+              Clock Security System Interrupt
+              clear
+              8
+              1
+            
+            
+              CSSLSEC
+              LSE Clock Security System Interrupt
+              clear
+              7
+              1
+            
+            
+              MSIRDYC
+              MSI ready Interrupt clear
+              5
+              1
+            
+            
+              PLLRDYC
+              PLL ready Interrupt clear
+              4
+              1
+            
+            
+              HSERDYC
+              HSE ready Interrupt clear
+              3
+              1
+            
+            
+              HSI16RDYC
+              HSI16 ready Interrupt
+              clear
+              2
+              1
+            
+            
+              LSERDYC
+              LSE ready Interrupt clear
+              1
+              1
+            
+            
+              LSIRDYC
+              LSI ready Interrupt clear
+              0
+              1
+            
+          
+        
+        
+          IOPRSTR
+          IOPRSTR
+          GPIO reset register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IOPHRST
+              I/O port H reset
+              7
+              1
+            
+            
+              IOPDRST
+              I/O port D reset
+              3
+              1
+            
+            
+              IOPCRST
+              I/O port A reset
+              2
+              1
+            
+            
+              IOPBRST
+              I/O port B reset
+              1
+              1
+            
+            
+              IOPARST
+              I/O port A reset
+              0
+              1
+            
+            
+              IOPERST
+              I/O port E reset
+              4
+              1
+            
+          
+        
+        
+          AHBRSTR
+          AHBRSTR
+          AHB peripheral reset register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CRYPRST
+              Crypto module reset
+              24
+              1
+            
+            
+              CRCRST
+              Test integration module
+              reset
+              12
+              1
+            
+            
+              MIFRST
+              Memory interface reset
+              8
+              1
+            
+            
+              DMARST
+              DMA reset
+              0
+              1
+            
+          
+        
+        
+          APB2RSTR
+          APB2RSTR
+          APB2 peripheral reset register
+          0x24
+          0x20
+          read-write
+          0x000000000
+          
+            
+              DBGRST
+              DBG reset
+              22
+              1
+            
+            
+              USART1RST
+              USART1 reset
+              14
+              1
+            
+            
+              SPI1RST
+              SPI 1 reset
+              12
+              1
+            
+            
+              ADCRST
+              ADC interface reset
+              9
+              1
+            
+            
+              TIM22RST
+              TIM22 timer reset
+              5
+              1
+            
+            
+              TIM21RST
+              TIM21 timer reset
+              2
+              1
+            
+            
+              SYSCFGRST
+              System configuration controller
+              reset
+              0
+              1
+            
+          
+        
+        
+          APB1RSTR
+          APB1RSTR
+          APB1 peripheral reset register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LPTIM1RST
+              Low power timer reset
+              31
+              1
+            
+            
+              PWRRST
+              Power interface reset
+              28
+              1
+            
+            
+              I2C2RST
+              I2C2 reset
+              22
+              1
+            
+            
+              I2C1RST
+              I2C1 reset
+              21
+              1
+            
+            
+              LPUART1RST
+              LPUART1 reset
+              18
+              1
+            
+            
+              USART2RST
+              USART2 reset
+              17
+              1
+            
+            
+              SPI2RST
+              SPI2 reset
+              14
+              1
+            
+            
+              WWDGRST
+              Window watchdog reset
+              11
+              1
+            
+            
+              TIM6RST
+              Timer 6 reset
+              4
+              1
+            
+            
+              TIM2RST
+              Timer 2 reset
+              0
+              1
+            
+            
+              TIM3RST
+              Timer 3 reset
+              1
+              1
+            
+            
+              TIM7RST
+              Timer 7 reset
+              5
+              1
+            
+            
+              USART4RST
+              USART4 reset
+              19
+              1
+            
+            
+              USART5RST
+              USART5 reset
+              20
+              1
+            
+            
+              CRCRST
+              CRC reset
+              27
+              1
+            
+            
+              I2C3
+              I2C3 reset
+              30
+              1
+            
+          
+        
+        
+          IOPENR
+          IOPENR
+          GPIO clock enable register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IOPHEN
+              I/O port H clock enable
+              bit
+              7
+              1
+            
+            
+              IOPDEN
+              I/O port D clock enable
+              bit
+              3
+              1
+            
+            
+              IOPCEN
+              IO port A clock enable bit
+              2
+              1
+            
+            
+              IOPBEN
+              IO port B clock enable bit
+              1
+              1
+            
+            
+              IOPAEN
+              IO port A clock enable bit
+              0
+              1
+            
+            
+              IOPEEN
+              IO port E clock enable bit
+              4
+              1
+            
+          
+        
+        
+          AHBENR
+          AHBENR
+          AHB peripheral clock enable
+          register
+          0x30
+          0x20
+          read-write
+          0x00000100
+          
+            
+              CRYPEN
+              Crypto clock enable bit
+              24
+              1
+            
+            
+              CRCEN
+              CRC clock enable bit
+              12
+              1
+            
+            
+              MIFEN
+              NVM interface clock enable
+              bit
+              8
+              1
+            
+            
+              DMAEN
+              DMA clock enable bit
+              0
+              1
+            
+          
+        
+        
+          APB2ENR
+          APB2ENR
+          APB2 peripheral clock enable
+          register
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DBGEN
+              DBG clock enable bit
+              22
+              1
+            
+            
+              USART1EN
+              USART1 clock enable bit
+              14
+              1
+            
+            
+              SPI1EN
+              SPI1 clock enable bit
+              12
+              1
+            
+            
+              ADCEN
+              ADC clock enable bit
+              9
+              1
+            
+            
+              FWEN
+              Firewall clock enable bit
+              7
+              1
+            
+            
+              TIM22EN
+              TIM22 timer clock enable
+              bit
+              5
+              1
+            
+            
+              TIM21EN
+              TIM21 timer clock enable
+              bit
+              2
+              1
+            
+            
+              SYSCFGEN
+              System configuration controller clock
+              enable bit
+              0
+              1
+            
+          
+        
+        
+          APB1ENR
+          APB1ENR
+          APB1 peripheral clock enable
+          register
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LPTIM1EN
+              Low power timer clock enable
+              bit
+              31
+              1
+            
+            
+              PWREN
+              Power interface clock enable
+              bit
+              28
+              1
+            
+            
+              I2C2EN
+              I2C2 clock enable bit
+              22
+              1
+            
+            
+              I2C1EN
+              I2C1 clock enable bit
+              21
+              1
+            
+            
+              LPUART1EN
+              LPUART1 clock enable bit
+              18
+              1
+            
+            
+              USART2EN
+              UART2 clock enable bit
+              17
+              1
+            
+            
+              SPI2EN
+              SPI2 clock enable bit
+              14
+              1
+            
+            
+              WWDGEN
+              Window watchdog clock enable
+              bit
+              11
+              1
+            
+            
+              TIM6EN
+              Timer 6 clock enable bit
+              4
+              1
+            
+            
+              TIM2EN
+              Timer2 clock enable bit
+              0
+              1
+            
+            
+              TIM3EN
+              Timer 3 clock enbale bit
+              2
+              1
+            
+            
+              TIM7EN
+              Timer 7 clock enable bit
+              5
+              1
+            
+            
+              USART4EN
+              USART4 clock enable bit
+              19
+              1
+            
+            
+              USART5EN
+              USART5 clock enable bit
+              20
+              1
+            
+            
+              I2C3EN
+              I2C3 clock enable bit
+              30
+              1
+            
+          
+        
+        
+          IOPSMEN
+          IOPSMEN
+          GPIO clock enable in sleep mode
+          register
+          0x3C
+          0x20
+          read-write
+          0x0000008F
+          
+            
+              IOPHSMEN
+              Port H clock enable during Sleep mode
+              bit
+              7
+              1
+            
+            
+              IOPDSMEN
+              Port D clock enable during Sleep mode
+              bit
+              3
+              1
+            
+            
+              IOPCSMEN
+              Port C clock enable during Sleep mode
+              bit
+              2
+              1
+            
+            
+              IOPBSMEN
+              Port B clock enable during Sleep mode
+              bit
+              1
+              1
+            
+            
+              IOPASMEN
+              Port A clock enable during Sleep mode
+              bit
+              0
+              1
+            
+            
+              IOPESMEN
+              Port E clock enable during Sleep mode
+              bit
+              4
+              1
+            
+          
+        
+        
+          AHBSMENR
+          AHBSMENR
+          AHB peripheral clock enable in sleep mode
+          register
+          0x40
+          0x20
+          read-write
+          0x01111301
+          
+            
+              CRYPTSMEN
+              Crypto clock enable during sleep mode
+              bit
+              24
+              1
+            
+            
+              CRCSMEN
+              CRC clock enable during sleep mode
+              bit
+              12
+              1
+            
+            
+              SRAMSMEN
+              SRAM interface clock enable during sleep
+              mode bit
+              9
+              1
+            
+            
+              MIFSMEN
+              NVM interface clock enable during sleep
+              mode bit
+              8
+              1
+            
+            
+              DMASMEN
+              DMA clock enable during sleep mode
+              bit
+              0
+              1
+            
+          
+        
+        
+          APB2SMENR
+          APB2SMENR
+          APB2 peripheral clock enable in sleep mode
+          register
+          0x44
+          0x20
+          read-write
+          0x00405225
+          
+            
+              DBGSMEN
+              DBG clock enable during sleep mode
+              bit
+              22
+              1
+            
+            
+              USART1SMEN
+              USART1 clock enable during sleep mode
+              bit
+              14
+              1
+            
+            
+              SPI1SMEN
+              SPI1 clock enable during sleep mode
+              bit
+              12
+              1
+            
+            
+              ADCSMEN
+              ADC clock enable during sleep mode
+              bit
+              9
+              1
+            
+            
+              TIM22SMEN
+              TIM22 timer clock enable during sleep
+              mode bit
+              5
+              1
+            
+            
+              TIM21SMEN
+              TIM21 timer clock enable during sleep
+              mode bit
+              2
+              1
+            
+            
+              SYSCFGSMEN
+              System configuration controller clock
+              enable during sleep mode bit
+              0
+              1
+            
+          
+        
+        
+          APB1SMENR
+          APB1SMENR
+          APB1 peripheral clock enable in sleep mode
+          register
+          0x48
+          0x20
+          read-write
+          0xB8E64A11
+          
+            
+              LPTIM1SMEN
+              Low power timer clock enable during
+              sleep mode bit
+              31
+              1
+            
+            
+              PWRSMEN
+              Power interface clock enable during
+              sleep mode bit
+              28
+              1
+            
+            
+              CRSSMEN
+              Clock recovery system clock enable
+              during sleep mode bit
+              27
+              1
+            
+            
+              I2C2SMEN
+              I2C2 clock enable during sleep mode
+              bit
+              22
+              1
+            
+            
+              I2C1SMEN
+              I2C1 clock enable during sleep mode
+              bit
+              21
+              1
+            
+            
+              LPUART1SMEN
+              LPUART1 clock enable during sleep mode
+              bit
+              18
+              1
+            
+            
+              USART2SMEN
+              UART2 clock enable during sleep mode
+              bit
+              17
+              1
+            
+            
+              SPI2SMEN
+              SPI2 clock enable during sleep mode
+              bit
+              14
+              1
+            
+            
+              WWDGSMEN
+              Window watchdog clock enable during
+              sleep mode bit
+              11
+              1
+            
+            
+              TIM6SMEN
+              Timer 6 clock enable during sleep mode
+              bit
+              4
+              1
+            
+            
+              TIM2SMEN
+              Timer2 clock enable during sleep mode
+              bit
+              0
+              1
+            
+            
+              TIM3SMEN
+              Timer 3 clock enable during sleep mode
+              bit
+              1
+              1
+            
+            
+              TIM7SMEN
+              Timer 7 clock enable during sleep mode
+              bit
+              5
+              1
+            
+            
+              USART4SMEN
+              USART4 clock enabe during sleep mode
+              bit
+              19
+              1
+            
+            
+              USART5SMEN
+              USART5 clock enable during sleep mode
+              bit
+              20
+              1
+            
+            
+              I2C3SMEN
+              I2C3 clock enable during sleep mode
+              bit
+              30
+              1
+            
+          
+        
+        
+          CCIPR
+          CCIPR
+          Clock configuration register
+          0x4C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LPTIM1SEL1
+              Low Power Timer clock source selection
+              bits
+              19
+              1
+            
+            
+              LPTIM1SEL0
+              LPTIM1SEL0
+              18
+              1
+            
+            
+              I2C1SEL1
+              I2C1 clock source selection
+              bits
+              13
+              1
+            
+            
+              I2C1SEL0
+              I2C1SEL0
+              12
+              1
+            
+            
+              LPUART1SEL1
+              LPUART1 clock source selection
+              bits
+              11
+              1
+            
+            
+              LPUART1SEL0
+              LPUART1SEL0
+              10
+              1
+            
+            
+              USART2SEL1
+              USART2 clock source selection
+              bits
+              3
+              1
+            
+            
+              USART2SEL0
+              USART2SEL0
+              2
+              1
+            
+            
+              USART1SEL1
+              USART1 clock source selection
+              bits
+              1
+              1
+            
+            
+              USART1SEL0
+              USART1SEL0
+              0
+              1
+            
+            
+              I2C3SEL0
+              I2C3 clock source selection
+              bits
+              16
+              1
+            
+            
+              I2C3SEL1
+              I2C3 clock source selection
+              bits
+              17
+              1
+            
+          
+        
+        
+          CSR
+          CSR
+          Control and status register
+          0x50
+          0x20
+          0x0C000000
+          
+            
+              LPWRSTF
+              Low-power reset flag
+              31
+              1
+              read-write
+            
+            
+              WWDGRSTF
+              Window watchdog reset flag
+              30
+              1
+              read-write
+            
+            
+              IWDGRSTF
+              Independent watchdog reset
+              flag
+              29
+              1
+              read-write
+            
+            
+              SFTRSTF
+              Software reset flag
+              28
+              1
+              read-write
+            
+            
+              PORRSTF
+              POR/PDR reset flag
+              27
+              1
+              read-write
+            
+            
+              PINRSTF
+              PIN reset flag
+              26
+              1
+              read-write
+            
+            
+              OBLRSTF
+              OBLRSTF
+              25
+              1
+              read-write
+            
+            
+              FWRSTF
+              Firewall reset flag
+              24
+              1
+              read-write
+            
+            
+              RTCRST
+              RTC software reset bit
+              19
+              1
+              read-write
+            
+            
+              RTCEN
+              RTC clock enable bit
+              18
+              1
+              read-write
+            
+            
+              RTCSEL
+              RTC and LCD clock source selection
+              bits
+              16
+              2
+              read-write
+            
+            
+              CSSLSED
+              CSS on LSE failure detection
+              flag
+              14
+              1
+              read-write
+            
+            
+              CSSLSEON
+              CSSLSEON
+              13
+              1
+              read-write
+            
+            
+              LSEDRV
+              LSEDRV
+              11
+              2
+              read-write
+            
+            
+              LSEBYP
+              External low-speed oscillator bypass
+              bit
+              10
+              1
+              read-write
+            
+            
+              LSERDY
+              External low-speed oscillator ready
+              bit
+              9
+              1
+              read-only
+            
+            
+              LSEON
+              External low-speed oscillator enable
+              bit
+              8
+              1
+              read-write
+            
+            
+              LSIRDY
+              Internal low-speed oscillator ready
+              bit
+              1
+              1
+              read-only
+            
+            
+              LSION
+              Internal low-speed oscillator
+              enable
+              0
+              1
+              read-write
+            
+            
+              LSIIWDGLP
+              LSI clock input to IWDG in
+              Ultra-low-power mode (Stop and Standby) enable
+              bit
+              2
+              1
+              read-write
+            
+            
+              RMVF
+              Remove reset flag
+              23
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      SYSCFG_COMP
+      System configuration controller and COMP
+      register
+      SYSCFG
+      0x40010000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CFGR1
+          CFGR1
+          SYSCFG configuration register
+          1
+          0x0
+          0x20
+          0x00000000
+          
+            
+              BOOT_MODE
+              Boot mode selected by the boot pins
+              status bits
+              8
+              2
+              read-only
+            
+            
+              MEM_MODE
+              Memory mapping selection
+              bits
+              0
+              2
+              read-write
+            
+          
+        
+        
+          CFGR2
+          CFGR2
+          SYSCFG configuration register
+          2
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              I2C2_FMP
+              I2C2 Fm+ drive capability enable
+              bit
+              13
+              1
+            
+            
+              I2C1_FMP
+              I2C1 Fm+ drive capability enable
+              bit
+              12
+              1
+            
+            
+              I2C_PB9_FMP
+              Fm+ drive capability on PB9 enable
+              bit
+              11
+              1
+            
+            
+              I2C_PB8_FMP
+              Fm+ drive capability on PB8 enable
+              bit
+              10
+              1
+            
+            
+              I2C_PB7_FMP
+              Fm+ drive capability on PB7 enable
+              bit
+              9
+              1
+            
+            
+              I2C_PB6_FMP
+              Fm+ drive capability on PB6 enable
+              bit
+              8
+              1
+            
+            
+              CAPA
+              Configuration of internal VLCD rail
+              connection to optional external
+              capacitor
+              1
+              3
+            
+            
+              FWDISEN
+              Firewall disable bit
+              0
+              1
+            
+          
+        
+        
+          EXTICR1
+          EXTICR1
+          external interrupt configuration register
+          1
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI3
+              EXTI x configuration (x = 0 to
+              3)
+              12
+              4
+            
+            
+              EXTI2
+              EXTI x configuration (x = 0 to
+              3)
+              8
+              4
+            
+            
+              EXTI1
+              EXTI x configuration (x = 0 to
+              3)
+              4
+              4
+            
+            
+              EXTI0
+              EXTI x configuration (x = 0 to
+              3)
+              0
+              4
+            
+          
+        
+        
+          EXTICR2
+          EXTICR2
+          external interrupt configuration register
+          2
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI7
+              EXTI x configuration (x = 4 to
+              7)
+              12
+              4
+            
+            
+              EXTI6
+              EXTI x configuration (x = 4 to
+              7)
+              8
+              4
+            
+            
+              EXTI5
+              EXTI x configuration (x = 4 to
+              7)
+              4
+              4
+            
+            
+              EXTI4
+              EXTI x configuration (x = 4 to
+              7)
+              0
+              4
+            
+          
+        
+        
+          EXTICR3
+          EXTICR3
+          external interrupt configuration register
+          3
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI11
+              EXTI x configuration (x = 8 to
+              11)
+              12
+              4
+            
+            
+              EXTI10
+              EXTI10
+              8
+              4
+            
+            
+              EXTI9
+              EXTI x configuration (x = 8 to
+              11)
+              4
+              4
+            
+            
+              EXTI8
+              EXTI x configuration (x = 8 to
+              11)
+              0
+              4
+            
+          
+        
+        
+          EXTICR4
+          EXTICR4
+          external interrupt configuration register
+          4
+          0x14
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI15
+              EXTI x configuration (x = 12 to
+              15)
+              12
+              4
+            
+            
+              EXTI14
+              EXTI14
+              8
+              4
+            
+            
+              EXTI13
+              EXTI13
+              4
+              4
+            
+            
+              EXTI12
+              EXTI12
+              0
+              4
+            
+          
+        
+        
+          CFGR3
+          CFGR3
+          SYSCFG configuration register
+          3
+          0x20
+          0x20
+          0x00000000
+          
+            
+              REF_LOCK
+              REF_CTRL lock bit
+              31
+              1
+              write-only
+            
+            
+              VREFINT_RDYF
+              VREFINT ready flag
+              30
+              1
+              read-only
+            
+            
+              VREFINT_COMP_RDYF
+              VREFINT for comparator ready
+              flag
+              29
+              1
+              read-only
+            
+            
+              VREFINT_ADC_RDYF
+              VREFINT for ADC ready flag
+              28
+              1
+              read-only
+            
+            
+              SENSOR_ADC_RDYF
+              Sensor for ADC ready flag
+              27
+              1
+              read-only
+            
+            
+              REF_RC48MHz_RDYF
+              VREFINT for 48 MHz RC oscillator ready
+              flag
+              26
+              1
+              read-only
+            
+            
+              ENREF_RC48MHz
+              VREFINT reference for 48 MHz RC
+              oscillator enable bit
+              13
+              1
+              read-write
+            
+            
+              ENBUF_VREFINT_COMP
+              VREFINT reference for comparator 2
+              enable bit
+              12
+              1
+              read-write
+            
+            
+              ENBUF_SENSOR_ADC
+              Sensor reference for ADC enable
+              bit
+              9
+              1
+              read-write
+            
+            
+              ENBUF_BGAP_ADC
+              VREFINT reference for ADC enable
+              bit
+              8
+              1
+              read-write
+            
+            
+              SEL_VREF_OUT
+              BGAP_ADC connection bit
+              4
+              2
+              read-write
+            
+            
+              EN_BGAP
+              Vref Enable bit
+              0
+              1
+              read-write
+            
+          
+        
+        
+          COMP1_CTRL
+          COMP1_CTRL
+          Comparator 1 control and status
+          register
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              COMP1EN
+              Comparator 1 enable bit
+              0
+              1
+            
+            
+              COMP1INNSEL
+              Comparator 1 Input Minus connection
+              configuration bit
+              4
+              2
+            
+            
+              COMP1WM
+              Comparator 1 window mode selection
+              bit
+              8
+              1
+            
+            
+              COMP1LPTIMIN1
+              Comparator 1 LPTIM input propagation
+              bit
+              12
+              1
+            
+            
+              COMP1POLARITY
+              Comparator 1 polarity selection
+              bit
+              15
+              1
+            
+            
+              COMP1VALUE
+              Comparator 1 output status
+              bit
+              30
+              1
+            
+            
+              COMP1LOCK
+              COMP1_CSR register lock
+              bit
+              31
+              1
+            
+          
+        
+        
+          COMP2_CTRL
+          COMP2_CTRL
+          Comparator 2 control and status
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              COMP2EN
+              Comparator 2 enable bit
+              0
+              1
+            
+            
+              COMP2SPEED
+              Comparator 2 power mode selection
+              bit
+              3
+              1
+            
+            
+              COMP2INNSEL
+              Comparator 2 Input Minus connection
+              configuration bit
+              4
+              3
+            
+            
+              COMP2INPSEL
+              Comparator 2 Input Plus connection
+              configuration bit
+              8
+              3
+            
+            
+              COMP2LPTIMIN2
+              Comparator 2 LPTIM input 2 propagation
+              bit
+              12
+              1
+            
+            
+              COMP2LPTIMIN1
+              Comparator 2 LPTIM input 1 propagation
+              bit
+              13
+              1
+            
+            
+              COMP2POLARITY
+              Comparator 2 polarity selection
+              bit
+              15
+              1
+            
+            
+              COMP2VALUE
+              Comparator 2 output status
+              bit
+              30
+              1
+            
+            
+              COMP2LOCK
+              COMP2_CSR register lock
+              bit
+              31
+              1
+            
+          
+        
+      
+    
+    
+      SPI1
+      Serial peripheral interface
+      SPI
+      0x40013000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        SPI1
+        SPI1_global_interrupt
+        25
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              BIDIMODE
+              Bidirectional data mode
+              enable
+              15
+              1
+            
+            
+              BIDIOE
+              Output enable in bidirectional
+              mode
+              14
+              1
+            
+            
+              CRCEN
+              Hardware CRC calculation
+              enable
+              13
+              1
+            
+            
+              CRCNEXT
+              CRC transfer next
+              12
+              1
+            
+            
+              DFF
+              Data frame format
+              11
+              1
+            
+            
+              RXONLY
+              Receive only
+              10
+              1
+            
+            
+              SSM
+              Software slave management
+              9
+              1
+            
+            
+              SSI
+              Internal slave select
+              8
+              1
+            
+            
+              LSBFIRST
+              Frame format
+              7
+              1
+            
+            
+              SPE
+              SPI enable
+              6
+              1
+            
+            
+              BR
+              Baud rate control
+              3
+              3
+            
+            
+              MSTR
+              Master selection
+              2
+              1
+            
+            
+              CPOL
+              Clock polarity
+              1
+              1
+            
+            
+              CPHA
+              Clock phase
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              RXDMAEN
+              Rx buffer DMA enable
+              0
+              1
+            
+            
+              TXDMAEN
+              Tx buffer DMA enable
+              1
+              1
+            
+            
+              SSOE
+              SS output enable
+              2
+              1
+            
+            
+              FRF
+              Frame format
+              4
+              1
+            
+            
+              ERRIE
+              Error interrupt enable
+              5
+              1
+            
+            
+              RXNEIE
+              RX buffer not empty interrupt
+              enable
+              6
+              1
+            
+            
+              TXEIE
+              Tx buffer empty interrupt
+              enable
+              7
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x8
+          0x20
+          0x0002
+          
+            
+              RXNE
+              Receive buffer not empty
+              0
+              1
+              read-only
+            
+            
+              TXE
+              Transmit buffer empty
+              1
+              1
+              read-only
+            
+            
+              CHSIDE
+              Channel side
+              2
+              1
+              read-only
+            
+            
+              UDR
+              Underrun flag
+              3
+              1
+              read-only
+            
+            
+              CRCERR
+              CRC error flag
+              4
+              1
+              read-write
+            
+            
+              MODF
+              Mode fault
+              5
+              1
+              read-only
+            
+            
+              OVR
+              Overrun flag
+              6
+              1
+              read-only
+            
+            
+              BSY
+              Busy flag
+              7
+              1
+              read-only
+            
+            
+              TIFRFE
+              TI frame format error
+              8
+              1
+              read-only
+            
+          
+        
+        
+          DR
+          DR
+          data register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              DR
+              Data register
+              0
+              16
+            
+          
+        
+        
+          CRCPR
+          CRCPR
+          CRC polynomial register
+          0x10
+          0x20
+          read-write
+          0x0007
+          
+            
+              CRCPOLY
+              CRC polynomial register
+              0
+              16
+            
+          
+        
+        
+          RXCRCR
+          RXCRCR
+          RX CRC register
+          0x14
+          0x20
+          read-only
+          0x0000
+          
+            
+              RxCRC
+              Rx CRC register
+              0
+              16
+            
+          
+        
+        
+          TXCRCR
+          TXCRCR
+          TX CRC register
+          0x18
+          0x20
+          read-only
+          0x0000
+          
+            
+              TxCRC
+              Tx CRC register
+              0
+              16
+            
+          
+        
+        
+          I2SCFGR
+          I2SCFGR
+          I2S configuration register
+          0x1C
+          0x20
+          read-write
+          0x0000
+          
+            
+              I2SMOD
+              I2S mode selection
+              11
+              1
+            
+            
+              I2SE
+              I2S Enable
+              10
+              1
+            
+            
+              I2SCFG
+              I2S configuration mode
+              8
+              2
+            
+            
+              PCMSYNC
+              PCM frame synchronization
+              7
+              1
+            
+            
+              I2SSTD
+              I2S standard selection
+              4
+              2
+            
+            
+              CKPOL
+              Steady state clock
+              polarity
+              3
+              1
+            
+            
+              DATLEN
+              Data length to be
+              transferred
+              1
+              2
+            
+            
+              CHLEN
+              Channel length (number of bits per audio
+              channel)
+              0
+              1
+            
+          
+        
+        
+          I2SPR
+          I2SPR
+          I2S prescaler register
+          0x20
+          0x20
+          read-write
+          0x00000010
+          
+            
+              MCKOE
+              Master clock output enable
+              9
+              1
+            
+            
+              ODD
+              Odd factor for the
+              prescaler
+              8
+              1
+            
+            
+              I2SDIV
+              I2S Linear prescaler
+              0
+              8
+            
+          
+        
+      
+    
+    
+      SPI2
+      0x40003800
+      
+        SPI2
+        SPI2 global interrupt
+        26
+      
+    
+    
+      I2C1
+      Inter-integrated circuit
+      I2C
+      0x40005400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        I2C1
+        I2C1 global interrupt
+        23
+      
+      
+        
+          CR1
+          CR1
+          Control register 1
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PE
+              Peripheral enable
+              0
+              1
+            
+            
+              TXIE
+              TX Interrupt enable
+              1
+              1
+            
+            
+              RXIE
+              RX Interrupt enable
+              2
+              1
+            
+            
+              ADDRIE
+              Address match interrupt enable (slave
+              only)
+              3
+              1
+            
+            
+              NACKIE
+              Not acknowledge received interrupt
+              enable
+              4
+              1
+            
+            
+              STOPIE
+              STOP detection Interrupt
+              enable
+              5
+              1
+            
+            
+              TCIE
+              Transfer Complete interrupt
+              enable
+              6
+              1
+            
+            
+              ERRIE
+              Error interrupts enable
+              7
+              1
+            
+            
+              DNF
+              Digital noise filter
+              8
+              4
+            
+            
+              ANFOFF
+              Analog noise filter OFF
+              12
+              1
+            
+            
+              TXDMAEN
+              DMA transmission requests
+              enable
+              14
+              1
+            
+            
+              RXDMAEN
+              DMA reception requests
+              enable
+              15
+              1
+            
+            
+              SBC
+              Slave byte control
+              16
+              1
+            
+            
+              NOSTRETCH
+              Clock stretching disable
+              17
+              1
+            
+            
+              WUPEN
+              Wakeup from STOP enable
+              18
+              1
+            
+            
+              GCEN
+              General call enable
+              19
+              1
+            
+            
+              SMBHEN
+              SMBus Host address enable
+              20
+              1
+            
+            
+              SMBDEN
+              SMBus Device Default address
+              enable
+              21
+              1
+            
+            
+              ALERTEN
+              SMBUS alert enable
+              22
+              1
+            
+            
+              PECEN
+              PEC enable
+              23
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          Control register 2
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PECBYTE
+              Packet error checking byte
+              26
+              1
+            
+            
+              AUTOEND
+              Automatic end mode (master
+              mode)
+              25
+              1
+            
+            
+              RELOAD
+              NBYTES reload mode
+              24
+              1
+            
+            
+              NBYTES
+              Number of bytes
+              16
+              8
+            
+            
+              NACK
+              NACK generation (slave
+              mode)
+              15
+              1
+            
+            
+              STOP
+              Stop generation (master
+              mode)
+              14
+              1
+            
+            
+              START
+              Start generation
+              13
+              1
+            
+            
+              HEAD10R
+              10-bit address header only read
+              direction (master receiver mode)
+              12
+              1
+            
+            
+              ADD10
+              10-bit addressing mode (master
+              mode)
+              11
+              1
+            
+            
+              RD_WRN
+              Transfer direction (master
+              mode)
+              10
+              1
+            
+            
+              SADD
+              Slave address bit (master
+              mode)
+              0
+              10
+            
+          
+        
+        
+          OAR1
+          OAR1
+          Own address register 1
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OA1
+              Interface address
+              0
+              10
+            
+            
+              OA1MODE
+              Own Address 1 10-bit mode
+              10
+              1
+            
+            
+              OA1EN
+              Own Address 1 enable
+              15
+              1
+            
+          
+        
+        
+          OAR2
+          OAR2
+          Own address register 2
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OA2
+              Interface address
+              1
+              7
+            
+            
+              OA2MSK
+              Own Address 2 masks
+              8
+              3
+            
+            
+              OA2EN
+              Own Address 2 enable
+              15
+              1
+            
+          
+        
+        
+          TIMINGR
+          TIMINGR
+          Timing register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SCLL
+              SCL low period (master
+              mode)
+              0
+              8
+            
+            
+              SCLH
+              SCL high period (master
+              mode)
+              8
+              8
+            
+            
+              SDADEL
+              Data hold time
+              16
+              4
+            
+            
+              SCLDEL
+              Data setup time
+              20
+              4
+            
+            
+              PRESC
+              Timing prescaler
+              28
+              4
+            
+          
+        
+        
+          TIMEOUTR
+          TIMEOUTR
+          Status register 1
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TIMEOUTA
+              Bus timeout A
+              0
+              12
+            
+            
+              TIDLE
+              Idle clock timeout
+              detection
+              12
+              1
+            
+            
+              TIMOUTEN
+              Clock timeout enable
+              15
+              1
+            
+            
+              TIMEOUTB
+              Bus timeout B
+              16
+              12
+            
+            
+              TEXTEN
+              Extended clock timeout
+              enable
+              31
+              1
+            
+          
+        
+        
+          ISR
+          ISR
+          Interrupt and Status register
+          0x18
+          0x20
+          0x00000001
+          
+            
+              ADDCODE
+              Address match code (Slave
+              mode)
+              17
+              7
+              read-only
+            
+            
+              DIR
+              Transfer direction (Slave
+              mode)
+              16
+              1
+              read-only
+            
+            
+              BUSY
+              Bus busy
+              15
+              1
+              read-only
+            
+            
+              ALERT
+              SMBus alert
+              13
+              1
+              read-only
+            
+            
+              TIMEOUT
+              Timeout or t_low detection
+              flag
+              12
+              1
+              read-only
+            
+            
+              PECERR
+              PEC Error in reception
+              11
+              1
+              read-only
+            
+            
+              OVR
+              Overrun/Underrun (slave
+              mode)
+              10
+              1
+              read-only
+            
+            
+              ARLO
+              Arbitration lost
+              9
+              1
+              read-only
+            
+            
+              BERR
+              Bus error
+              8
+              1
+              read-only
+            
+            
+              TCR
+              Transfer Complete Reload
+              7
+              1
+              read-only
+            
+            
+              TC
+              Transfer Complete (master
+              mode)
+              6
+              1
+              read-only
+            
+            
+              STOPF
+              Stop detection flag
+              5
+              1
+              read-only
+            
+            
+              NACKF
+              Not acknowledge received
+              flag
+              4
+              1
+              read-only
+            
+            
+              ADDR
+              Address matched (slave
+              mode)
+              3
+              1
+              read-only
+            
+            
+              RXNE
+              Receive data register not empty
+              (receivers)
+              2
+              1
+              read-only
+            
+            
+              TXIS
+              Transmit interrupt status
+              (transmitters)
+              1
+              1
+              read-write
+            
+            
+              TXE
+              Transmit data register empty
+              (transmitters)
+              0
+              1
+              read-write
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt clear register
+          0x1C
+          0x20
+          write-only
+          0x00000000
+          
+            
+              ALERTCF
+              Alert flag clear
+              13
+              1
+            
+            
+              TIMOUTCF
+              Timeout detection flag
+              clear
+              12
+              1
+            
+            
+              PECCF
+              PEC Error flag clear
+              11
+              1
+            
+            
+              OVRCF
+              Overrun/Underrun flag
+              clear
+              10
+              1
+            
+            
+              ARLOCF
+              Arbitration lost flag
+              clear
+              9
+              1
+            
+            
+              BERRCF
+              Bus error flag clear
+              8
+              1
+            
+            
+              STOPCF
+              Stop detection flag clear
+              5
+              1
+            
+            
+              NACKCF
+              Not Acknowledge flag clear
+              4
+              1
+            
+            
+              ADDRCF
+              Address Matched flag clear
+              3
+              1
+            
+          
+        
+        
+          PECR
+          PECR
+          PEC register
+          0x20
+          0x20
+          read-only
+          0x00000000
+          
+            
+              PEC
+              Packet error checking
+              register
+              0
+              8
+            
+          
+        
+        
+          RXDR
+          RXDR
+          Receive data register
+          0x24
+          0x20
+          read-only
+          0x00000000
+          
+            
+              RXDATA
+              8-bit receive data
+              0
+              8
+            
+          
+        
+        
+          TXDR
+          TXDR
+          Transmit data register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TXDATA
+              8-bit transmit data
+              0
+              8
+            
+          
+        
+      
+    
+    
+      I2C2
+      0x40005800
+      
+        I2C2
+        I2C2 global interrupt
+        24
+      
+    
+    
+      I2C3
+      0x40007800
+      
+        I2C3
+        I2C3 global interrupt
+        21
+      
+    
+    
+      PWR
+      Power control
+      PWR
+      0x40007000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR
+          CR
+          power control register
+          0x0
+          0x20
+          read-write
+          0x00001000
+          
+            
+              LPDS
+              Low-power deep sleep
+              0
+              1
+            
+            
+              PDDS
+              Power down deepsleep
+              1
+              1
+            
+            
+              CWUF
+              Clear wakeup flag
+              2
+              1
+            
+            
+              CSBF
+              Clear standby flag
+              3
+              1
+            
+            
+              PVDE
+              Power voltage detector
+              enable
+              4
+              1
+            
+            
+              PLS
+              PVD level selection
+              5
+              3
+            
+            
+              DBP
+              Disable backup domain write
+              protection
+              8
+              1
+            
+            
+              ULP
+              Ultra-low-power mode
+              9
+              1
+            
+            
+              FWU
+              Fast wakeup
+              10
+              1
+            
+            
+              VOS
+              Voltage scaling range
+              selection
+              11
+              2
+            
+            
+              DS_EE_KOFF
+              Deep sleep mode with Flash memory kept
+              off
+              13
+              1
+            
+            
+              LPRUN
+              Low power run mode
+              14
+              1
+            
+          
+        
+        
+          CSR
+          CSR
+          power control/status register
+          0x4
+          0x20
+          0x00000000
+          
+            
+              BRE
+              Backup regulator enable
+              9
+              1
+              read-write
+            
+            
+              EWUP
+              Enable WKUP pin
+              8
+              1
+              read-write
+            
+            
+              BRR
+              Backup regulator ready
+              3
+              1
+              read-only
+            
+            
+              PVDO
+              PVD output
+              2
+              1
+              read-only
+            
+            
+              SBF
+              Standby flag
+              1
+              1
+              read-only
+            
+            
+              WUF
+              Wakeup flag
+              0
+              1
+              read-only
+            
+            
+              VOSF
+              Voltage Scaling select
+              flag
+              4
+              1
+              read-only
+            
+            
+              REGLPF
+              Regulator LP flag
+              5
+              1
+              read-only
+            
+          
+        
+      
+    
+    
+      Flash
+      Flash
+      Flash
+      0x40022000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        FLASH
+        Flash global interrupt
+        3
+      
+      
+        
+          ACR
+          ACR
+          Access control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LATENCY
+              Latency
+              0
+              1
+            
+            
+              PRFTEN
+              Prefetch enable
+              1
+              1
+            
+            
+              SLEEP_PD
+              Flash mode during Sleep
+              3
+              1
+            
+            
+              RUN_PD
+              Flash mode during Run
+              4
+              1
+            
+            
+              DESAB_BUF
+              Disable Buffer
+              5
+              1
+            
+            
+              PRE_READ
+              Pre-read data address
+              6
+              1
+            
+          
+        
+        
+          PECR
+          PECR
+          Program/erase control register
+          0x4
+          0x20
+          read-write
+          0x00000007
+          
+            
+              PELOCK
+              FLASH_PECR and data EEPROM
+              lock
+              0
+              1
+            
+            
+              PRGLOCK
+              Program memory lock
+              1
+              1
+            
+            
+              OPTLOCK
+              Option bytes block lock
+              2
+              1
+            
+            
+              PROG
+              Program memory selection
+              3
+              1
+            
+            
+              DATA
+              Data EEPROM selection
+              4
+              1
+            
+            
+              FTDW
+              Fixed time data write for Byte, Half
+              Word and Word programming
+              8
+              1
+            
+            
+              ERASE
+              Page or Double Word erase
+              mode
+              9
+              1
+            
+            
+              FPRG
+              Half Page/Double Word programming
+              mode
+              10
+              1
+            
+            
+              PARALLELBANK
+              Parallel bank mode
+              15
+              1
+            
+            
+              EOPIE
+              End of programming interrupt
+              enable
+              16
+              1
+            
+            
+              ERRIE
+              Error interrupt enable
+              17
+              1
+            
+            
+              OBL_LAUNCH
+              Launch the option byte
+              loading
+              18
+              1
+            
+          
+        
+        
+          PDKEYR
+          PDKEYR
+          Power down key register
+          0x8
+          0x20
+          write-only
+          0x00000000
+          
+            
+              PDKEYR
+              RUN_PD in FLASH_ACR key
+              0
+              32
+            
+          
+        
+        
+          PEKEYR
+          PEKEYR
+          Program/erase key register
+          0xC
+          0x20
+          write-only
+          0x00000000
+          
+            
+              PEKEYR
+              FLASH_PEC and data EEPROM
+              key
+              0
+              32
+            
+          
+        
+        
+          PRGKEYR
+          PRGKEYR
+          Program memory key register
+          0x10
+          0x20
+          write-only
+          0x00000000
+          
+            
+              PRGKEYR
+              Program memory key
+              0
+              32
+            
+          
+        
+        
+          OPTKEYR
+          OPTKEYR
+          Option byte key register
+          0x14
+          0x20
+          write-only
+          0x00000000
+          
+            
+              OPTKEYR
+              Option byte key
+              0
+              32
+            
+          
+        
+        
+          SR
+          SR
+          Status register
+          0x18
+          0x20
+          0x00000004
+          
+            
+              BSY
+              Write/erase operations in
+              progress
+              0
+              1
+              read-only
+            
+            
+              EOP
+              End of operation
+              1
+              1
+              read-only
+            
+            
+              ENDHV
+              End of high voltage
+              2
+              1
+              read-only
+            
+            
+              READY
+              Flash memory module ready after low
+              power mode
+              3
+              1
+              read-only
+            
+            
+              WRPERR
+              Write protected error
+              8
+              1
+              read-write
+            
+            
+              PGAERR
+              Programming alignment
+              error
+              9
+              1
+              read-write
+            
+            
+              SIZERR
+              Size error
+              10
+              1
+              read-write
+            
+            
+              OPTVERR
+              Option validity error
+              11
+              1
+              read-write
+            
+            
+              RDERR
+              RDERR
+              14
+              1
+              read-write
+            
+            
+              NOTZEROERR
+              NOTZEROERR
+              16
+              1
+              read-write
+            
+            
+              FWWERR
+              FWWERR
+              17
+              1
+              read-write
+            
+          
+        
+        
+          OBR
+          OBR
+          Option byte register
+          0x1C
+          0x20
+          read-only
+          0x00F80000
+          
+            
+              RDPRT
+              Read protection
+              0
+              8
+            
+            
+              BOR_LEV
+              BOR_LEV
+              16
+              4
+            
+            
+              SPRMOD
+              Selection of protection mode of WPR
+              bits
+              8
+              1
+            
+          
+        
+        
+          WRPR
+          WRPR
+          Write protection register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              WRP
+              Write protection
+              0
+              16
+            
+          
+        
+      
+    
+    
+      EXTI
+      External interrupt/event
+      controller
+      EXTI
+      0x40010400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        PVD
+        PVD through EXTI line detection
+        1
+      
+      
+        EXTI0_1
+        EXTI Line[1:0] interrupts
+        5
+      
+      
+        EXTI2_3
+        EXTI Line[3:2] interrupts
+        6
+      
+      
+        EXTI4_15
+        EXTI Line15 and EXTI4 interrupts
+        7
+      
+      
+        
+          IMR
+          IMR
+          Interrupt mask register
+          (EXTI_IMR)
+          0x0
+          0x20
+          read-write
+          0xFF840000
+          
+            
+              IM0
+              Interrupt Mask on line 0
+              0
+              1
+            
+            
+              IM1
+              Interrupt Mask on line 1
+              1
+              1
+            
+            
+              IM2
+              Interrupt Mask on line 2
+              2
+              1
+            
+            
+              IM3
+              Interrupt Mask on line 3
+              3
+              1
+            
+            
+              IM4
+              Interrupt Mask on line 4
+              4
+              1
+            
+            
+              IM5
+              Interrupt Mask on line 5
+              5
+              1
+            
+            
+              IM6
+              Interrupt Mask on line 6
+              6
+              1
+            
+            
+              IM7
+              Interrupt Mask on line 7
+              7
+              1
+            
+            
+              IM8
+              Interrupt Mask on line 8
+              8
+              1
+            
+            
+              IM9
+              Interrupt Mask on line 9
+              9
+              1
+            
+            
+              IM10
+              Interrupt Mask on line 10
+              10
+              1
+            
+            
+              IM11
+              Interrupt Mask on line 11
+              11
+              1
+            
+            
+              IM12
+              Interrupt Mask on line 12
+              12
+              1
+            
+            
+              IM13
+              Interrupt Mask on line 13
+              13
+              1
+            
+            
+              IM14
+              Interrupt Mask on line 14
+              14
+              1
+            
+            
+              IM15
+              Interrupt Mask on line 15
+              15
+              1
+            
+            
+              IM16
+              Interrupt Mask on line 16
+              16
+              1
+            
+            
+              IM17
+              Interrupt Mask on line 17
+              17
+              1
+            
+            
+              IM18
+              Interrupt Mask on line 18
+              18
+              1
+            
+            
+              IM19
+              Interrupt Mask on line 19
+              19
+              1
+            
+            
+              IM20
+              Interrupt Mask on line 20
+              20
+              1
+            
+            
+              IM21
+              Interrupt Mask on line 21
+              21
+              1
+            
+            
+              IM22
+              Interrupt Mask on line 22
+              22
+              1
+            
+            
+              IM23
+              Interrupt Mask on line 23
+              23
+              1
+            
+            
+              IM24
+              Interrupt Mask on line 24
+              24
+              1
+            
+            
+              IM25
+              Interrupt Mask on line 25
+              25
+              1
+            
+            
+              IM26
+              Interrupt Mask on line 27
+              26
+              1
+            
+            
+              IM28
+              Interrupt Mask on line 27
+              28
+              1
+            
+            
+              IM29
+              Interrupt Mask on line 27
+              29
+              1
+            
+          
+        
+        
+          EMR
+          EMR
+          Event mask register (EXTI_EMR)
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EM0
+              Event Mask on line 0
+              0
+              1
+            
+            
+              EM1
+              Event Mask on line 1
+              1
+              1
+            
+            
+              EM2
+              Event Mask on line 2
+              2
+              1
+            
+            
+              EM3
+              Event Mask on line 3
+              3
+              1
+            
+            
+              EM4
+              Event Mask on line 4
+              4
+              1
+            
+            
+              EM5
+              Event Mask on line 5
+              5
+              1
+            
+            
+              EM6
+              Event Mask on line 6
+              6
+              1
+            
+            
+              EM7
+              Event Mask on line 7
+              7
+              1
+            
+            
+              EM8
+              Event Mask on line 8
+              8
+              1
+            
+            
+              EM9
+              Event Mask on line 9
+              9
+              1
+            
+            
+              EM10
+              Event Mask on line 10
+              10
+              1
+            
+            
+              EM11
+              Event Mask on line 11
+              11
+              1
+            
+            
+              EM12
+              Event Mask on line 12
+              12
+              1
+            
+            
+              EM13
+              Event Mask on line 13
+              13
+              1
+            
+            
+              EM14
+              Event Mask on line 14
+              14
+              1
+            
+            
+              EM15
+              Event Mask on line 15
+              15
+              1
+            
+            
+              EM16
+              Event Mask on line 16
+              16
+              1
+            
+            
+              EM17
+              Event Mask on line 17
+              17
+              1
+            
+            
+              EM18
+              Event Mask on line 18
+              18
+              1
+            
+            
+              EM19
+              Event Mask on line 19
+              19
+              1
+            
+            
+              EM20
+              Event Mask on line 20
+              20
+              1
+            
+            
+              EM21
+              Event Mask on line 21
+              21
+              1
+            
+            
+              EM22
+              Event Mask on line 22
+              22
+              1
+            
+            
+              EM23
+              Event Mask on line 23
+              23
+              1
+            
+            
+              EM24
+              Event Mask on line 24
+              24
+              1
+            
+            
+              EM25
+              Event Mask on line 25
+              25
+              1
+            
+            
+              EM26
+              Event Mask on line 26
+              26
+              1
+            
+            
+              EM28
+              Event Mask on line 28
+              28
+              1
+            
+            
+              EM29
+              Event Mask on line 29
+              29
+              1
+            
+          
+        
+        
+          RTSR
+          RTSR
+          Rising Trigger selection register
+          (EXTI_RTSR)
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              RT0
+              Rising trigger event configuration of
+              line 0
+              0
+              1
+            
+            
+              RT1
+              Rising trigger event configuration of
+              line 1
+              1
+              1
+            
+            
+              RT2
+              Rising trigger event configuration of
+              line 2
+              2
+              1
+            
+            
+              RT3
+              Rising trigger event configuration of
+              line 3
+              3
+              1
+            
+            
+              RT4
+              Rising trigger event configuration of
+              line 4
+              4
+              1
+            
+            
+              RT5
+              Rising trigger event configuration of
+              line 5
+              5
+              1
+            
+            
+              RT6
+              Rising trigger event configuration of
+              line 6
+              6
+              1
+            
+            
+              RT7
+              Rising trigger event configuration of
+              line 7
+              7
+              1
+            
+            
+              RT8
+              Rising trigger event configuration of
+              line 8
+              8
+              1
+            
+            
+              RT9
+              Rising trigger event configuration of
+              line 9
+              9
+              1
+            
+            
+              RT10
+              Rising trigger event configuration of
+              line 10
+              10
+              1
+            
+            
+              RT11
+              Rising trigger event configuration of
+              line 11
+              11
+              1
+            
+            
+              RT12
+              Rising trigger event configuration of
+              line 12
+              12
+              1
+            
+            
+              RT13
+              Rising trigger event configuration of
+              line 13
+              13
+              1
+            
+            
+              RT14
+              Rising trigger event configuration of
+              line 14
+              14
+              1
+            
+            
+              RT15
+              Rising trigger event configuration of
+              line 15
+              15
+              1
+            
+            
+              RT16
+              Rising trigger event configuration of
+              line 16
+              16
+              1
+            
+            
+              RT17
+              Rising trigger event configuration of
+              line 17
+              17
+              1
+            
+            
+              RT19
+              Rising trigger event configuration of
+              line 19
+              19
+              1
+            
+            
+              RT20
+              Rising trigger event configuration of
+              line 20
+              20
+              1
+            
+            
+              RT21
+              Rising trigger event configuration of
+              line 21
+              21
+              1
+            
+            
+              RT22
+              Rising trigger event configuration of
+              line 22
+              22
+              1
+            
+          
+        
+        
+          FTSR
+          FTSR
+          Falling Trigger selection register
+          (EXTI_FTSR)
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              FT0
+              Falling trigger event configuration of
+              line 0
+              0
+              1
+            
+            
+              FT1
+              Falling trigger event configuration of
+              line 1
+              1
+              1
+            
+            
+              FT2
+              Falling trigger event configuration of
+              line 2
+              2
+              1
+            
+            
+              FT3
+              Falling trigger event configuration of
+              line 3
+              3
+              1
+            
+            
+              FT4
+              Falling trigger event configuration of
+              line 4
+              4
+              1
+            
+            
+              FT5
+              Falling trigger event configuration of
+              line 5
+              5
+              1
+            
+            
+              FT6
+              Falling trigger event configuration of
+              line 6
+              6
+              1
+            
+            
+              FT7
+              Falling trigger event configuration of
+              line 7
+              7
+              1
+            
+            
+              FT8
+              Falling trigger event configuration of
+              line 8
+              8
+              1
+            
+            
+              FT9
+              Falling trigger event configuration of
+              line 9
+              9
+              1
+            
+            
+              FT10
+              Falling trigger event configuration of
+              line 10
+              10
+              1
+            
+            
+              FT11
+              Falling trigger event configuration of
+              line 11
+              11
+              1
+            
+            
+              FT12
+              Falling trigger event configuration of
+              line 12
+              12
+              1
+            
+            
+              FT13
+              Falling trigger event configuration of
+              line 13
+              13
+              1
+            
+            
+              FT14
+              Falling trigger event configuration of
+              line 14
+              14
+              1
+            
+            
+              FT15
+              Falling trigger event configuration of
+              line 15
+              15
+              1
+            
+            
+              FT16
+              Falling trigger event configuration of
+              line 16
+              16
+              1
+            
+            
+              FT17
+              Falling trigger event configuration of
+              line 17
+              17
+              1
+            
+            
+              FT19
+              Falling trigger event configuration of
+              line 19
+              19
+              1
+            
+            
+              FT20
+              Falling trigger event configuration of
+              line 20
+              20
+              1
+            
+            
+              FT21
+              Falling trigger event configuration of
+              line 21
+              21
+              1
+            
+            
+              FT22
+              Falling trigger event configuration of
+              line 22
+              22
+              1
+            
+          
+        
+        
+          SWIER
+          SWIER
+          Software interrupt event register
+          (EXTI_SWIER)
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SWI0
+              Software Interrupt on line
+              0
+              0
+              1
+            
+            
+              SWI1
+              Software Interrupt on line
+              1
+              1
+              1
+            
+            
+              SWI2
+              Software Interrupt on line
+              2
+              2
+              1
+            
+            
+              SWI3
+              Software Interrupt on line
+              3
+              3
+              1
+            
+            
+              SWI4
+              Software Interrupt on line
+              4
+              4
+              1
+            
+            
+              SWI5
+              Software Interrupt on line
+              5
+              5
+              1
+            
+            
+              SWI6
+              Software Interrupt on line
+              6
+              6
+              1
+            
+            
+              SWI7
+              Software Interrupt on line
+              7
+              7
+              1
+            
+            
+              SWI8
+              Software Interrupt on line
+              8
+              8
+              1
+            
+            
+              SWI9
+              Software Interrupt on line
+              9
+              9
+              1
+            
+            
+              SWI10
+              Software Interrupt on line
+              10
+              10
+              1
+            
+            
+              SWI11
+              Software Interrupt on line
+              11
+              11
+              1
+            
+            
+              SWI12
+              Software Interrupt on line
+              12
+              12
+              1
+            
+            
+              SWI13
+              Software Interrupt on line
+              13
+              13
+              1
+            
+            
+              SWI14
+              Software Interrupt on line
+              14
+              14
+              1
+            
+            
+              SWI15
+              Software Interrupt on line
+              15
+              15
+              1
+            
+            
+              SWI16
+              Software Interrupt on line
+              16
+              16
+              1
+            
+            
+              SWI17
+              Software Interrupt on line
+              17
+              17
+              1
+            
+            
+              SWI19
+              Software Interrupt on line
+              19
+              19
+              1
+            
+            
+              SWI20
+              Software Interrupt on line
+              20
+              20
+              1
+            
+            
+              SWI21
+              Software Interrupt on line
+              21
+              21
+              1
+            
+            
+              SWI22
+              Software Interrupt on line
+              22
+              22
+              1
+            
+          
+        
+        
+          PR
+          PR
+          Pending register (EXTI_PR)
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PIF0
+              Pending bit 0
+              0
+              1
+            
+            
+              PIF1
+              Pending bit 1
+              1
+              1
+            
+            
+              PIF2
+              Pending bit 2
+              2
+              1
+            
+            
+              PIF3
+              Pending bit 3
+              3
+              1
+            
+            
+              PIF4
+              Pending bit 4
+              4
+              1
+            
+            
+              PIF5
+              Pending bit 5
+              5
+              1
+            
+            
+              PIF6
+              Pending bit 6
+              6
+              1
+            
+            
+              PIF7
+              Pending bit 7
+              7
+              1
+            
+            
+              PIF8
+              Pending bit 8
+              8
+              1
+            
+            
+              PIF9
+              Pending bit 9
+              9
+              1
+            
+            
+              PIF10
+              Pending bit 10
+              10
+              1
+            
+            
+              PIF11
+              Pending bit 11
+              11
+              1
+            
+            
+              PIF12
+              Pending bit 12
+              12
+              1
+            
+            
+              PIF13
+              Pending bit 13
+              13
+              1
+            
+            
+              PIF14
+              Pending bit 14
+              14
+              1
+            
+            
+              PIF15
+              Pending bit 15
+              15
+              1
+            
+            
+              PIF16
+              Pending bit 16
+              16
+              1
+            
+            
+              PIF17
+              Pending bit 17
+              17
+              1
+            
+            
+              PIF19
+              Pending bit 19
+              19
+              1
+            
+            
+              PIF20
+              Pending bit 20
+              20
+              1
+            
+            
+              PIF21
+              Pending bit 21
+              21
+              1
+            
+            
+              PIF22
+              Pending bit 22
+              22
+              1
+            
+          
+        
+      
+    
+    
+      ADC
+      Analog-to-digital converter
+      ADC
+      0x40012400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        ADC_COMP
+        ADC and comparator 1 and 2
+        12
+      
+      
+        
+          ISR
+          ISR
+          interrupt and status register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADRDY
+              ADC ready
+              0
+              1
+            
+            
+              EOSMP
+              End of sampling flag
+              1
+              1
+            
+            
+              EOC
+              End of conversion flag
+              2
+              1
+            
+            
+              EOS
+              End of sequence flag
+              3
+              1
+            
+            
+              OVR
+              ADC overrun
+              4
+              1
+            
+            
+              AWD
+              Analog watchdog flag
+              7
+              1
+            
+            
+              EOCAL
+              End Of Calibration flag
+              11
+              1
+            
+          
+        
+        
+          IER
+          IER
+          interrupt enable register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADRDYIE
+              ADC ready interrupt enable
+              0
+              1
+            
+            
+              EOSMPIE
+              End of sampling flag interrupt
+              enable
+              1
+              1
+            
+            
+              EOCIE
+              End of conversion interrupt
+              enable
+              2
+              1
+            
+            
+              EOSIE
+              End of conversion sequence interrupt
+              enable
+              3
+              1
+            
+            
+              OVRIE
+              Overrun interrupt enable
+              4
+              1
+            
+            
+              AWDIE
+              Analog watchdog interrupt
+              enable
+              7
+              1
+            
+            
+              EOCALIE
+              End of calibration interrupt
+              enable
+              11
+              1
+            
+          
+        
+        
+          CR
+          CR
+          control register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADEN
+              ADC enable command
+              0
+              1
+            
+            
+              ADDIS
+              ADC disable command
+              1
+              1
+            
+            
+              ADSTART
+              ADC start conversion
+              command
+              2
+              1
+            
+            
+              ADSTP
+              ADC stop conversion
+              command
+              4
+              1
+            
+            
+              ADVREGEN
+              ADC Voltage Regulator
+              Enable
+              28
+              1
+            
+            
+              ADCAL
+              ADC calibration
+              31
+              1
+            
+          
+        
+        
+          CFGR1
+          CFGR1
+          configuration register 1
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AWDCH
+              Analog watchdog channel
+              selection
+              26
+              5
+            
+            
+              AWDEN
+              Analog watchdog enable
+              23
+              1
+            
+            
+              AWDSGL
+              Enable the watchdog on a single channel
+              or on all channels
+              22
+              1
+            
+            
+              DISCEN
+              Discontinuous mode
+              16
+              1
+            
+            
+              AUTOFF
+              Auto-off mode
+              15
+              1
+            
+            
+              AUTDLY
+              Auto-delayed conversion
+              mode
+              14
+              1
+            
+            
+              CONT
+              Single / continuous conversion
+              mode
+              13
+              1
+            
+            
+              OVRMOD
+              Overrun management mode
+              12
+              1
+            
+            
+              EXTEN
+              External trigger enable and polarity
+              selection
+              10
+              2
+            
+            
+              EXTSEL
+              External trigger selection
+              6
+              3
+            
+            
+              ALIGN
+              Data alignment
+              5
+              1
+            
+            
+              RES
+              Data resolution
+              3
+              2
+            
+            
+              SCANDIR
+              Scan sequence direction
+              2
+              1
+            
+            
+              DMACFG
+              Direct memery access
+              configuration
+              1
+              1
+            
+            
+              DMAEN
+              Direct memory access
+              enable
+              0
+              1
+            
+          
+        
+        
+          CFGR2
+          CFGR2
+          configuration register 2
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OVSE
+              Oversampler Enable
+              0
+              1
+            
+            
+              OVSR
+              Oversampling ratio
+              2
+              3
+            
+            
+              OVSS
+              Oversampling shift
+              5
+              4
+            
+            
+              TOVS
+              Triggered Oversampling
+              9
+              1
+            
+            
+              CKMODE
+              ADC clock mode
+              30
+              2
+            
+          
+        
+        
+          SMPR
+          SMPR
+          sampling time register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SMPR
+              Sampling time selection
+              0
+              3
+            
+          
+        
+        
+          TR
+          TR
+          watchdog threshold register
+          0x20
+          0x20
+          read-write
+          0x0FFF0000
+          
+            
+              HT
+              Analog watchdog higher
+              threshold
+              16
+              12
+            
+            
+              LT
+              Analog watchdog lower
+              threshold
+              0
+              12
+            
+          
+        
+        
+          CHSELR
+          CHSELR
+          channel selection register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CHSEL18
+              Channel-x selection
+              18
+              1
+            
+            
+              CHSEL17
+              Channel-x selection
+              17
+              1
+            
+            
+              CHSEL16
+              Channel-x selection
+              16
+              1
+            
+            
+              CHSEL15
+              Channel-x selection
+              15
+              1
+            
+            
+              CHSEL14
+              Channel-x selection
+              14
+              1
+            
+            
+              CHSEL13
+              Channel-x selection
+              13
+              1
+            
+            
+              CHSEL12
+              Channel-x selection
+              12
+              1
+            
+            
+              CHSEL11
+              Channel-x selection
+              11
+              1
+            
+            
+              CHSEL10
+              Channel-x selection
+              10
+              1
+            
+            
+              CHSEL9
+              Channel-x selection
+              9
+              1
+            
+            
+              CHSEL8
+              Channel-x selection
+              8
+              1
+            
+            
+              CHSEL7
+              Channel-x selection
+              7
+              1
+            
+            
+              CHSEL6
+              Channel-x selection
+              6
+              1
+            
+            
+              CHSEL5
+              Channel-x selection
+              5
+              1
+            
+            
+              CHSEL4
+              Channel-x selection
+              4
+              1
+            
+            
+              CHSEL3
+              Channel-x selection
+              3
+              1
+            
+            
+              CHSEL2
+              Channel-x selection
+              2
+              1
+            
+            
+              CHSEL1
+              Channel-x selection
+              1
+              1
+            
+            
+              CHSEL0
+              Channel-x selection
+              0
+              1
+            
+          
+        
+        
+          DR
+          DR
+          data register
+          0x40
+          0x20
+          read-only
+          0x00000000
+          
+            
+              DATA
+              Converted data
+              0
+              16
+            
+          
+        
+        
+          CALFACT
+          CALFACT
+          ADC Calibration factor
+          0xB4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CALFACT
+              Calibration factor
+              0
+              7
+            
+          
+        
+        
+          CCR
+          CCR
+          ADC common configuration
+          register
+          0x308
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRESC
+              ADC prescaler
+              18
+              4
+            
+            
+              VREFEN
+              VREFINT enable
+              22
+              1
+            
+            
+              TSEN
+              Temperature sensor enable
+              23
+              1
+            
+            
+              VLCDEN
+              VLCD enable
+              24
+              1
+            
+            
+              LFMEN
+              Low Frequency Mode enable
+              25
+              1
+            
+          
+        
+      
+    
+    
+      DBG
+      Debug support
+      DBGMCU
+      0x40015800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          IDCODE
+          IDCODE
+          MCU Device ID Code Register
+          0x0
+          0x20
+          read-only
+          0x0
+          
+            
+              DEV_ID
+              Device Identifier
+              0
+              12
+            
+            
+              REV_ID
+              Revision Identifier
+              16
+              16
+            
+          
+        
+        
+          CR
+          CR
+          Debug MCU Configuration
+          Register
+          0x4
+          0x20
+          read-write
+          0x0
+          
+            
+              DBG_STOP
+              Debug Stop Mode
+              1
+              1
+            
+            
+              DBG_STANDBY
+              Debug Standby Mode
+              2
+              1
+            
+            
+              DBG_SLEEP
+              Debug Sleep Mode
+              0
+              1
+            
+          
+        
+        
+          APB1_FZ
+          APB1_FZ
+          APB Low Freeze Register
+          0x8
+          0x20
+          read-write
+          0x0
+          
+            
+              DBG_TIMER2_STOP
+              Debug Timer 2 stopped when Core is
+              halted
+              0
+              1
+            
+            
+              DBG_TIMER6_STOP
+              Debug Timer 6 stopped when Core is
+              halted
+              4
+              1
+            
+            
+              DBG_RTC_STOP
+              Debug RTC stopped when Core is
+              halted
+              10
+              1
+            
+            
+              DBG_WWDG_STOP
+              Debug Window Wachdog stopped when Core
+              is halted
+              11
+              1
+            
+            
+              DBG_IWDG_STOP
+              Debug Independent Wachdog stopped when
+              Core is halted
+              12
+              1
+            
+            
+              DBG_I2C1_STOP
+              I2C1 SMBUS timeout mode stopped when
+              core is halted
+              21
+              1
+            
+            
+              DBG_I2C2_STOP
+              I2C2 SMBUS timeout mode stopped when
+              core is halted
+              22
+              1
+            
+            
+              DBG_LPTIMER_STOP
+              LPTIM1 counter stopped when core is
+              halted
+              31
+              1
+            
+          
+        
+        
+          APB2_FZ
+          APB2_FZ
+          APB High Freeze Register
+          0xC
+          0x20
+          read-write
+          0x0
+          
+            
+              DBG_TIMER21_STOP
+              Debug Timer 21 stopped when Core is
+              halted
+              2
+              1
+            
+            
+              DBG_TIMER22_STO
+              Debug Timer 22 stopped when Core is
+              halted
+              6
+              1
+            
+          
+        
+      
+    
+    
+      TIM2
+      General-purpose-timers
+      TIM
+      0x40000000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM2
+        TIM2 global interrupt
+        15
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              CKD
+              Clock division
+              8
+              2
+            
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              CMS
+              Center-aligned mode
+              selection
+              5
+              2
+            
+            
+              DIR
+              Direction
+              4
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              TI1S
+              TI1 selection
+              7
+              1
+            
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+            
+              CCDS
+              Capture/compare DMA
+              selection
+              3
+              1
+            
+          
+        
+        
+          SMCR
+          SMCR
+          slave mode control register
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              ETP
+              External trigger polarity
+              15
+              1
+            
+            
+              ECE
+              External clock enable
+              14
+              1
+            
+            
+              ETPS
+              External trigger prescaler
+              12
+              2
+            
+            
+              ETF
+              External trigger filter
+              8
+              4
+            
+            
+              MSM
+              Master/Slave mode
+              7
+              1
+            
+            
+              TS
+              Trigger selection
+              4
+              3
+            
+            
+              SMS
+              Slave mode selection
+              0
+              3
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              TDE
+              Trigger DMA request enable
+              14
+              1
+            
+            
+              CC4DE
+              Capture/Compare 4 DMA request
+              enable
+              12
+              1
+            
+            
+              CC3DE
+              Capture/Compare 3 DMA request
+              enable
+              11
+              1
+            
+            
+              CC2DE
+              Capture/Compare 2 DMA request
+              enable
+              10
+              1
+            
+            
+              CC1DE
+              Capture/Compare 1 DMA request
+              enable
+              9
+              1
+            
+            
+              UDE
+              Update DMA request enable
+              8
+              1
+            
+            
+              TIE
+              Trigger interrupt enable
+              6
+              1
+            
+            
+              CC4IE
+              Capture/Compare 4 interrupt
+              enable
+              4
+              1
+            
+            
+              CC3IE
+              Capture/Compare 3 interrupt
+              enable
+              3
+              1
+            
+            
+              CC2IE
+              Capture/Compare 2 interrupt
+              enable
+              2
+              1
+            
+            
+              CC1IE
+              Capture/Compare 1 interrupt
+              enable
+              1
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC4OF
+              Capture/Compare 4 overcapture
+              flag
+              12
+              1
+            
+            
+              CC3OF
+              Capture/Compare 3 overcapture
+              flag
+              11
+              1
+            
+            
+              CC2OF
+              Capture/compare 2 overcapture
+              flag
+              10
+              1
+            
+            
+              CC1OF
+              Capture/Compare 1 overcapture
+              flag
+              9
+              1
+            
+            
+              TIF
+              Trigger interrupt flag
+              6
+              1
+            
+            
+              CC4IF
+              Capture/Compare 4 interrupt
+              flag
+              4
+              1
+            
+            
+              CC3IF
+              Capture/Compare 3 interrupt
+              flag
+              3
+              1
+            
+            
+              CC2IF
+              Capture/Compare 2 interrupt
+              flag
+              2
+              1
+            
+            
+              CC1IF
+              Capture/compare 1 interrupt
+              flag
+              1
+              1
+            
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              TG
+              Trigger generation
+              6
+              1
+            
+            
+              CC4G
+              Capture/compare 4
+              generation
+              4
+              1
+            
+            
+              CC3G
+              Capture/compare 3
+              generation
+              3
+              1
+            
+            
+              CC2G
+              Capture/compare 2
+              generation
+              2
+              1
+            
+            
+              CC1G
+              Capture/compare 1
+              generation
+              1
+              1
+            
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CCMR1_Output
+          CCMR1_Output
+          capture/compare mode register 1 (output
+          mode)
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC2CE
+              Output compare 2 clear
+              enable
+              15
+              1
+            
+            
+              OC2M
+              Output compare 2 mode
+              12
+              3
+            
+            
+              OC2PE
+              Output compare 2 preload
+              enable
+              11
+              1
+            
+            
+              OC2FE
+              Output compare 2 fast
+              enable
+              10
+              1
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              OC1CE
+              Output compare 1 clear
+              enable
+              7
+              1
+            
+            
+              OC1M
+              Output compare 1 mode
+              4
+              3
+            
+            
+              OC1PE
+              Output compare 1 preload
+              enable
+              3
+              1
+            
+            
+              OC1FE
+              Output compare 1 fast
+              enable
+              2
+              1
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR1_Input
+          CCMR1_Input
+          capture/compare mode register 1 (input
+          mode)
+          CCMR1_Output
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC2F
+              Input capture 2 filter
+              12
+              4
+            
+            
+              IC2PSC
+              Input capture 2 prescaler
+              10
+              2
+            
+            
+              CC2S
+              Capture/compare 2
+              selection
+              8
+              2
+            
+            
+              IC1F
+              Input capture 1 filter
+              4
+              4
+            
+            
+              IC1PSC
+              Input capture 1 prescaler
+              2
+              2
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR2_Output
+          CCMR2_Output
+          capture/compare mode register 2 (output
+          mode)
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC4CE
+              Output compare 4 clear
+              enable
+              15
+              1
+            
+            
+              OC4M
+              Output compare 4 mode
+              12
+              3
+            
+            
+              OC4PE
+              Output compare 4 preload
+              enable
+              11
+              1
+            
+            
+              OC4FE
+              Output compare 4 fast
+              enable
+              10
+              1
+            
+            
+              CC4S
+              Capture/Compare 4
+              selection
+              8
+              2
+            
+            
+              OC3CE
+              Output compare 3 clear
+              enable
+              7
+              1
+            
+            
+              OC3M
+              Output compare 3 mode
+              4
+              3
+            
+            
+              OC3PE
+              Output compare 3 preload
+              enable
+              3
+              1
+            
+            
+              OC3FE
+              Output compare 3 fast
+              enable
+              2
+              1
+            
+            
+              CC3S
+              Capture/Compare 3
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR2_Input
+          CCMR2_Input
+          capture/compare mode register 2 (input
+          mode)
+          CCMR2_Output
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC4F
+              Input capture 4 filter
+              12
+              4
+            
+            
+              IC4PSC
+              Input capture 4 prescaler
+              10
+              2
+            
+            
+              CC4S
+              Capture/Compare 4
+              selection
+              8
+              2
+            
+            
+              IC3F
+              Input capture 3 filter
+              4
+              4
+            
+            
+              IC3PSC
+              Input capture 3 prescaler
+              2
+              2
+            
+            
+              CC3S
+              Capture/Compare 3
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCER
+          CCER
+          capture/compare enable
+          register
+          0x20
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC4NP
+              Capture/Compare 4 output
+              Polarity
+              15
+              1
+            
+            
+              CC4P
+              Capture/Compare 3 output
+              Polarity
+              13
+              1
+            
+            
+              CC4E
+              Capture/Compare 4 output
+              enable
+              12
+              1
+            
+            
+              CC3NP
+              Capture/Compare 3 output
+              Polarity
+              11
+              1
+            
+            
+              CC3P
+              Capture/Compare 3 output
+              Polarity
+              9
+              1
+            
+            
+              CC3E
+              Capture/Compare 3 output
+              enable
+              8
+              1
+            
+            
+              CC2NP
+              Capture/Compare 2 output
+              Polarity
+              7
+              1
+            
+            
+              CC2P
+              Capture/Compare 2 output
+              Polarity
+              5
+              1
+            
+            
+              CC2E
+              Capture/Compare 2 output
+              enable
+              4
+              1
+            
+            
+              CC1NP
+              Capture/Compare 1 output
+              Polarity
+              3
+              1
+            
+            
+              CC1P
+              Capture/Compare 1 output
+              Polarity
+              1
+              1
+            
+            
+              CC1E
+              Capture/Compare 1 output
+              enable
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT_H
+              High counter value (TIM2
+              only)
+              16
+              16
+            
+            
+              CNT_L
+              Low counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR_H
+              High Auto-reload value (TIM2
+              only)
+              16
+              16
+            
+            
+              ARR_L
+              Low Auto-reload value
+              0
+              16
+            
+          
+        
+        
+          CCR1
+          CCR1
+          capture/compare register 1
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR1_H
+              High Capture/Compare 1 value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR1_L
+              Low Capture/Compare 1
+              value
+              0
+              16
+            
+          
+        
+        
+          CCR2
+          CCR2
+          capture/compare register 2
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR2_H
+              High Capture/Compare 2 value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR2_L
+              Low Capture/Compare 2
+              value
+              0
+              16
+            
+          
+        
+        
+          CCR3
+          CCR3
+          capture/compare register 3
+          0x3C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR3_H
+              High Capture/Compare value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR3_L
+              Low Capture/Compare value
+              0
+              16
+            
+          
+        
+        
+          CCR4
+          CCR4
+          capture/compare register 4
+          0x40
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR4_H
+              High Capture/Compare value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR4_L
+              Low Capture/Compare value
+              0
+              16
+            
+          
+        
+        
+          DCR
+          DCR
+          DMA control register
+          0x48
+          0x20
+          read-write
+          0x0000
+          
+            
+              DBL
+              DMA burst length
+              8
+              5
+            
+            
+              DBA
+              DMA base address
+              0
+              5
+            
+          
+        
+        
+          DMAR
+          DMAR
+          DMA address for full transfer
+          0x4C
+          0x20
+          read-write
+          0x0000
+          
+            
+              DMAB
+              DMA register for burst
+              accesses
+              0
+              16
+            
+          
+        
+        
+          OR
+          OR
+          TIM2 option register
+          0x50
+          0x20
+          read-write
+          0x0000
+          
+            
+              ETR_RMP
+              Timer2 ETR remap
+              0
+              3
+            
+            
+              TI4_RMP
+              Internal trigger
+              3
+              2
+            
+          
+        
+      
+    
+    
+      TIM3
+      0x40000400
+      
+        TIM3
+        TIM3 global interrupt
+        16
+      
+    
+    
+      TIM6
+      Basic-timers
+      TIM
+      0x40001000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM6
+        TIM6 global interrupt and DAC
+        17
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              UDE
+              Update DMA request enable
+              8
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT
+              Low counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR
+              Low Auto-reload value
+              0
+              16
+            
+          
+        
+      
+    
+    
+      TIM7
+      0x40001400
+      
+        TIM7
+        TIM7 global interrupt and DAC
+        18
+      
+    
+    
+      TIM21
+      General-purpose-timers
+      TIM
+      0x40010800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM21
+        TIMER21 global interrupt
+        20
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              DIR
+              Direction
+              4
+              1
+            
+            
+              CMS
+              Center-aligned mode
+              selection
+              5
+              2
+            
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              CKD
+              Clock division
+              8
+              2
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+          
+        
+        
+          SMCR
+          SMCR
+          slave mode control register
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              SMS
+              Slave mode selection
+              0
+              3
+            
+            
+              TS
+              Trigger selection
+              4
+              3
+            
+            
+              MSM
+              Master/Slave mode
+              7
+              1
+            
+            
+              ETF
+              External trigger filter
+              8
+              4
+            
+            
+              ETPS
+              External trigger prescaler
+              12
+              2
+            
+            
+              ECE
+              External clock enable
+              14
+              1
+            
+            
+              ETP
+              External trigger polarity
+              15
+              1
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              TIE
+              Trigger interrupt enable
+              6
+              1
+            
+            
+              CC2IE
+              Capture/Compare 2 interrupt
+              enable
+              2
+              1
+            
+            
+              CC1IE
+              Capture/Compare 1 interrupt
+              enable
+              1
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2OF
+              Capture/compare 2 overcapture
+              flag
+              10
+              1
+            
+            
+              CC1OF
+              Capture/Compare 1 overcapture
+              flag
+              9
+              1
+            
+            
+              TIF
+              Trigger interrupt flag
+              6
+              1
+            
+            
+              CC2IF
+              Capture/Compare 2 interrupt
+              flag
+              2
+              1
+            
+            
+              CC1IF
+              Capture/compare 1 interrupt
+              flag
+              1
+              1
+            
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              TG
+              Trigger generation
+              6
+              1
+            
+            
+              CC2G
+              Capture/compare 2
+              generation
+              2
+              1
+            
+            
+              CC1G
+              Capture/compare 1
+              generation
+              1
+              1
+            
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CCMR1_Output
+          CCMR1_Output
+          capture/compare mode register (output
+          mode)
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC2M
+              Output Compare 2 mode
+              12
+              3
+            
+            
+              OC2PE
+              Output Compare 2 preload
+              enable
+              11
+              1
+            
+            
+              OC2FE
+              Output Compare 2 fast
+              enable
+              10
+              1
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              OC1M
+              Output Compare 1 mode
+              4
+              3
+            
+            
+              OC1PE
+              Output Compare 1 preload
+              enable
+              3
+              1
+            
+            
+              OC1FE
+              Output Compare 1 fast
+              enable
+              2
+              1
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR1_Input
+          CCMR1_Input
+          capture/compare mode register 1 (input
+          mode)
+          CCMR1_Output
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC2F
+              Input capture 2 filter
+              12
+              4
+            
+            
+              IC2PSC
+              Input capture 2 prescaler
+              10
+              2
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              IC1F
+              Input capture 1 filter
+              4
+              4
+            
+            
+              IC1PSC
+              Input capture 1 prescaler
+              2
+              2
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCER
+          CCER
+          capture/compare enable
+          register
+          0x20
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2NP
+              Capture/Compare 2 output
+              Polarity
+              7
+              1
+            
+            
+              CC2P
+              Capture/Compare 2 output
+              Polarity
+              5
+              1
+            
+            
+              CC2E
+              Capture/Compare 2 output
+              enable
+              4
+              1
+            
+            
+              CC1NP
+              Capture/Compare 1 output
+              Polarity
+              3
+              1
+            
+            
+              CC1P
+              Capture/Compare 1 output
+              Polarity
+              1
+              1
+            
+            
+              CC1E
+              Capture/Compare 1 output
+              enable
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT
+              counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR
+              Auto-reload value
+              0
+              16
+            
+          
+        
+        
+          CCR1
+          CCR1
+          capture/compare register 1
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR1
+              Capture/Compare 1 value
+              0
+              16
+            
+          
+        
+        
+          CCR2
+          CCR2
+          capture/compare register 2
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR2
+              Capture/Compare 2 value
+              0
+              16
+            
+          
+        
+        
+          OR
+          OR
+          TIM21 option register
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ETR_RMP
+              Timer21 ETR remap
+              0
+              2
+            
+            
+              TI1_RMP
+              Timer21 TI1
+              2
+              3
+            
+            
+              TI2_RMP
+              Timer21 TI2
+              5
+              1
+            
+          
+        
+      
+    
+    
+      TIM22
+      General-purpose-timers
+      TIM
+      0x40011400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM22
+        TIMER22 global interrupt
+        22
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              DIR
+              Direction
+              4
+              1
+            
+            
+              CMS
+              Center-aligned mode
+              selection
+              5
+              2
+            
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              CKD
+              Clock division
+              8
+              2
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+          
+        
+        
+          SMCR
+          SMCR
+          slave mode control register
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              SMS
+              Slave mode selection
+              0
+              3
+            
+            
+              TS
+              Trigger selection
+              4
+              3
+            
+            
+              MSM
+              Master/Slave mode
+              7
+              1
+            
+            
+              ETF
+              External trigger filter
+              8
+              4
+            
+            
+              ETPS
+              External trigger prescaler
+              12
+              2
+            
+            
+              ECE
+              External clock enable
+              14
+              1
+            
+            
+              ETP
+              External trigger polarity
+              15
+              1
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              TIE
+              Trigger interrupt enable
+              6
+              1
+            
+            
+              CC2IE
+              Capture/Compare 2 interrupt
+              enable
+              2
+              1
+            
+            
+              CC1IE
+              Capture/Compare 1 interrupt
+              enable
+              1
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2OF
+              Capture/compare 2 overcapture
+              flag
+              10
+              1
+            
+            
+              CC1OF
+              Capture/Compare 1 overcapture
+              flag
+              9
+              1
+            
+            
+              TIF
+              Trigger interrupt flag
+              6
+              1
+            
+            
+              CC2IF
+              Capture/Compare 2 interrupt
+              flag
+              2
+              1
+            
+            
+              CC1IF
+              Capture/compare 1 interrupt
+              flag
+              1
+              1
+            
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              TG
+              Trigger generation
+              6
+              1
+            
+            
+              CC2G
+              Capture/compare 2
+              generation
+              2
+              1
+            
+            
+              CC1G
+              Capture/compare 1
+              generation
+              1
+              1
+            
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CCMR1_Output
+          CCMR1_Output
+          capture/compare mode register (output
+          mode)
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC2M
+              Output Compare 2 mode
+              12
+              3
+            
+            
+              OC2PE
+              Output Compare 2 preload
+              enable
+              11
+              1
+            
+            
+              OC2FE
+              Output Compare 2 fast
+              enable
+              10
+              1
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              OC1M
+              Output Compare 1 mode
+              4
+              3
+            
+            
+              OC1PE
+              Output Compare 1 preload
+              enable
+              3
+              1
+            
+            
+              OC1FE
+              Output Compare 1 fast
+              enable
+              2
+              1
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR1_Input
+          CCMR1_Input
+          capture/compare mode register 1 (input
+          mode)
+          CCMR1_Output
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC2F
+              Input capture 2 filter
+              12
+              4
+            
+            
+              IC2PSC
+              Input capture 2 prescaler
+              10
+              2
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              IC1F
+              Input capture 1 filter
+              4
+              4
+            
+            
+              IC1PSC
+              Input capture 1 prescaler
+              2
+              2
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCER
+          CCER
+          capture/compare enable
+          register
+          0x20
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2NP
+              Capture/Compare 2 output
+              Polarity
+              7
+              1
+            
+            
+              CC2P
+              Capture/Compare 2 output
+              Polarity
+              5
+              1
+            
+            
+              CC2E
+              Capture/Compare 2 output
+              enable
+              4
+              1
+            
+            
+              CC1NP
+              Capture/Compare 1 output
+              Polarity
+              3
+              1
+            
+            
+              CC1P
+              Capture/Compare 1 output
+              Polarity
+              1
+              1
+            
+            
+              CC1E
+              Capture/Compare 1 output
+              enable
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT
+              counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR
+              Auto-reload value
+              0
+              16
+            
+          
+        
+        
+          CCR1
+          CCR1
+          capture/compare register 1
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR1
+              Capture/Compare 1 value
+              0
+              16
+            
+          
+        
+        
+          CCR2
+          CCR2
+          capture/compare register 2
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR2
+              Capture/Compare 2 value
+              0
+              16
+            
+          
+        
+        
+          OR
+          OR
+          TIM22 option register
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ETR_RMP
+              Timer22 ETR remap
+              0
+              2
+            
+            
+              TI1_RMP
+              Timer22 TI1
+              2
+              2
+            
+          
+        
+      
+    
+    
+      LPUART1
+      Lower power Universal asynchronous receiver
+      transmitter
+      USART
+      0x40004800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR1
+          CR1
+          Control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              M1
+              Word length
+              28
+              1
+            
+            
+              DEAT4
+              Driver Enable assertion
+              time
+              25
+              1
+            
+            
+              DEAT3
+              DEAT3
+              24
+              1
+            
+            
+              DEAT2
+              DEAT2
+              23
+              1
+            
+            
+              DEAT1
+              DEAT1
+              22
+              1
+            
+            
+              DEAT0
+              DEAT0
+              21
+              1
+            
+            
+              DEDT4
+              Driver Enable de-assertion
+              time
+              20
+              1
+            
+            
+              DEDT3
+              DEDT3
+              19
+              1
+            
+            
+              DEDT2
+              DEDT2
+              18
+              1
+            
+            
+              DEDT1
+              DEDT1
+              17
+              1
+            
+            
+              DEDT0
+              DEDT0
+              16
+              1
+            
+            
+              CMIE
+              Character match interrupt
+              enable
+              14
+              1
+            
+            
+              MME
+              Mute mode enable
+              13
+              1
+            
+            
+              M0
+              Word length
+              12
+              1
+            
+            
+              WAKE
+              Receiver wakeup method
+              11
+              1
+            
+            
+              PCE
+              Parity control enable
+              10
+              1
+            
+            
+              PS
+              Parity selection
+              9
+              1
+            
+            
+              PEIE
+              PE interrupt enable
+              8
+              1
+            
+            
+              TXEIE
+              interrupt enable
+              7
+              1
+            
+            
+              TCIE
+              Transmission complete interrupt
+              enable
+              6
+              1
+            
+            
+              RXNEIE
+              RXNE interrupt enable
+              5
+              1
+            
+            
+              IDLEIE
+              IDLE interrupt enable
+              4
+              1
+            
+            
+              TE
+              Transmitter enable
+              3
+              1
+            
+            
+              RE
+              Receiver enable
+              2
+              1
+            
+            
+              UESM
+              USART enable in Stop mode
+              1
+              1
+            
+            
+              UE
+              USART enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          Control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              ADD4_7
+              Address of the USART node
+              28
+              4
+            
+            
+              ADD0_3
+              Address of the USART node
+              24
+              4
+            
+            
+              MSBFIRST
+              Most significant bit first
+              19
+              1
+            
+            
+              TAINV
+              Binary data inversion
+              18
+              1
+            
+            
+              TXINV
+              TX pin active level
+              inversion
+              17
+              1
+            
+            
+              RXINV
+              RX pin active level
+              inversion
+              16
+              1
+            
+            
+              SWAP
+              Swap TX/RX pins
+              15
+              1
+            
+            
+              STOP
+              STOP bits
+              12
+              2
+            
+            
+              CLKEN
+              Clock enable
+              11
+              1
+            
+            
+              ADDM7
+              7-bit Address Detection/4-bit Address
+              Detection
+              4
+              1
+            
+          
+        
+        
+          CR3
+          CR3
+          Control register 3
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              WUFIE
+              Wakeup from Stop mode interrupt
+              enable
+              22
+              1
+            
+            
+              WUS
+              Wakeup from Stop mode interrupt flag
+              selection
+              20
+              2
+            
+            
+              DEP
+              Driver enable polarity
+              selection
+              15
+              1
+            
+            
+              DEM
+              Driver enable mode
+              14
+              1
+            
+            
+              DDRE
+              DMA Disable on Reception
+              Error
+              13
+              1
+            
+            
+              OVRDIS
+              Overrun Disable
+              12
+              1
+            
+            
+              CTSIE
+              CTS interrupt enable
+              10
+              1
+            
+            
+              CTSE
+              CTS enable
+              9
+              1
+            
+            
+              RTSE
+              RTS enable
+              8
+              1
+            
+            
+              DMAT
+              DMA enable transmitter
+              7
+              1
+            
+            
+              DMAR
+              DMA enable receiver
+              6
+              1
+            
+            
+              HDSEL
+              Half-duplex selection
+              3
+              1
+            
+            
+              EIE
+              Error interrupt enable
+              0
+              1
+            
+          
+        
+        
+          BRR
+          BRR
+          Baud rate register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              BRR
+              BRR
+              0
+              20
+            
+          
+        
+        
+          RQR
+          RQR
+          Request register
+          0x18
+          0x20
+          write-only
+          0x0000
+          
+            
+              RXFRQ
+              Receive data flush request
+              3
+              1
+            
+            
+              MMRQ
+              Mute mode request
+              2
+              1
+            
+            
+              SBKRQ
+              Send break request
+              1
+              1
+            
+          
+        
+        
+          ISR
+          ISR
+          Interrupt & status
+          register
+          0x1C
+          0x20
+          read-only
+          0x00C0
+          
+            
+              REACK
+              REACK
+              22
+              1
+            
+            
+              TEACK
+              TEACK
+              21
+              1
+            
+            
+              WUF
+              WUF
+              20
+              1
+            
+            
+              RWU
+              RWU
+              19
+              1
+            
+            
+              SBKF
+              SBKF
+              18
+              1
+            
+            
+              CMF
+              CMF
+              17
+              1
+            
+            
+              BUSY
+              BUSY
+              16
+              1
+            
+            
+              CTS
+              CTS
+              10
+              1
+            
+            
+              CTSIF
+              CTSIF
+              9
+              1
+            
+            
+              TXE
+              TXE
+              7
+              1
+            
+            
+              TC
+              TC
+              6
+              1
+            
+            
+              RXNE
+              RXNE
+              5
+              1
+            
+            
+              IDLE
+              IDLE
+              4
+              1
+            
+            
+              ORE
+              ORE
+              3
+              1
+            
+            
+              NF
+              NF
+              2
+              1
+            
+            
+              FE
+              FE
+              1
+              1
+            
+            
+              PE
+              PE
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt flag clear register
+          0x20
+          0x20
+          write-only
+          0x0000
+          
+            
+              WUCF
+              Wakeup from Stop mode clear
+              flag
+              20
+              1
+            
+            
+              CMCF
+              Character match clear flag
+              17
+              1
+            
+            
+              CTSCF
+              CTS clear flag
+              9
+              1
+            
+            
+              TCCF
+              Transmission complete clear
+              flag
+              6
+              1
+            
+            
+              IDLECF
+              Idle line detected clear
+              flag
+              4
+              1
+            
+            
+              ORECF
+              Overrun error clear flag
+              3
+              1
+            
+            
+              NCF
+              Noise detected clear flag
+              2
+              1
+            
+            
+              FECF
+              Framing error clear flag
+              1
+              1
+            
+            
+              PECF
+              Parity error clear flag
+              0
+              1
+            
+          
+        
+        
+          RDR
+          RDR
+          Receive data register
+          0x24
+          0x20
+          read-only
+          0x0000
+          
+            
+              RDR
+              Receive data value
+              0
+              9
+            
+          
+        
+        
+          TDR
+          TDR
+          Transmit data register
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              TDR
+              Transmit data value
+              0
+              9
+            
+          
+        
+      
+    
+    
+      NVIC
+      Nested Vectored Interrupt
+      Controller
+      NVIC
+      0xE000E100
+      
+        0x0
+        0x33D
+        registers
+      
+      
+        
+          ISER
+          ISER
+          Interrupt Set Enable Register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SETENA
+              SETENA
+              0
+              32
+            
+          
+        
+        
+          ICER
+          ICER
+          Interrupt Clear Enable
+          Register
+          0x80
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CLRENA
+              CLRENA
+              0
+              32
+            
+          
+        
+        
+          ISPR
+          ISPR
+          Interrupt Set-Pending Register
+          0x100
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SETPEND
+              SETPEND
+              0
+              32
+            
+          
+        
+        
+          ICPR
+          ICPR
+          Interrupt Clear-Pending
+          Register
+          0x180
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CLRPEND
+              CLRPEND
+              0
+              32
+            
+          
+        
+        
+          IPR0
+          IPR0
+          Interrupt Priority Register 0
+          0x300
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_0
+              priority for interrupt 0
+              0
+              8
+            
+            
+              PRI_1
+              priority for interrupt 1
+              8
+              8
+            
+            
+              PRI_2
+              priority for interrupt 2
+              16
+              8
+            
+            
+              PRI_3
+              priority for interrupt 3
+              24
+              8
+            
+          
+        
+        
+          IPR1
+          IPR1
+          Interrupt Priority Register 1
+          0x304
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_4
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_5
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_6
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_7
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR2
+          IPR2
+          Interrupt Priority Register 2
+          0x308
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_8
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_9
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_10
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_11
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR3
+          IPR3
+          Interrupt Priority Register 3
+          0x30C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_12
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_13
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_14
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_15
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR4
+          IPR4
+          Interrupt Priority Register 4
+          0x310
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_16
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_17
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_18
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_19
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR5
+          IPR5
+          Interrupt Priority Register 5
+          0x314
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_20
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_21
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_22
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_23
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR6
+          IPR6
+          Interrupt Priority Register 6
+          0x318
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_24
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_25
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_26
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_27
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR7
+          IPR7
+          Interrupt Priority Register 7
+          0x31C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_28
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_29
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_30
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_31
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+      
+    
+    
+      MPU
+      Memory protection unit
+      MPU
+      0xE000ED90
+      
+        0x0
+        0x15
+        registers
+      
+      
+        
+          MPU_TYPER
+          MPU_TYPER
+          MPU type register
+          0x0
+          0x20
+          read-only
+          0X00000800
+          
+            
+              SEPARATE
+              Separate flag
+              0
+              1
+            
+            
+              DREGION
+              Number of MPU data regions
+              8
+              8
+            
+            
+              IREGION
+              Number of MPU instruction
+              regions
+              16
+              8
+            
+          
+        
+        
+          MPU_CTRL
+          MPU_CTRL
+          MPU control register
+          0x4
+          0x20
+          read-only
+          0X00000000
+          
+            
+              ENABLE
+              Enables the MPU
+              0
+              1
+            
+            
+              HFNMIENA
+              Enables the operation of MPU during hard
+              fault
+              1
+              1
+            
+            
+              PRIVDEFENA
+              Enable priviliged software access to
+              default memory map
+              2
+              1
+            
+          
+        
+        
+          MPU_RNR
+          MPU_RNR
+          MPU region number register
+          0x8
+          0x20
+          read-write
+          0X00000000
+          
+            
+              REGION
+              MPU region
+              0
+              8
+            
+          
+        
+        
+          MPU_RBAR
+          MPU_RBAR
+          MPU region base address
+          register
+          0xC
+          0x20
+          read-write
+          0X00000000
+          
+            
+              REGION
+              MPU region field
+              0
+              4
+            
+            
+              VALID
+              MPU region number valid
+              4
+              1
+            
+            
+              ADDR
+              Region base address field
+              5
+              27
+            
+          
+        
+        
+          MPU_RASR
+          MPU_RASR
+          MPU region attribute and size
+          register
+          0x10
+          0x20
+          read-write
+          0X00000000
+          
+            
+              ENABLE
+              Region enable bit.
+              0
+              1
+            
+            
+              SIZE
+              Size of the MPU protection
+              region
+              1
+              5
+            
+            
+              SRD
+              Subregion disable bits
+              8
+              8
+            
+            
+              B
+              memory attribute
+              16
+              1
+            
+            
+              C
+              memory attribute
+              17
+              1
+            
+            
+              S
+              Shareable memory attribute
+              18
+              1
+            
+            
+              TEX
+              memory attribute
+              19
+              3
+            
+            
+              AP
+              Access permission
+              24
+              3
+            
+            
+              XN
+              Instruction access disable
+              bit
+              28
+              1
+            
+          
+        
+      
+    
+    
+      STK
+      SysTick timer
+      STK
+      0xE000E010
+      
+        0x0
+        0x11
+        registers
+      
+      
+        
+          CSR
+          CSR
+          SysTick control and status
+          register
+          0x0
+          0x20
+          read-write
+          0X00000000
+          
+            
+              ENABLE
+              Counter enable
+              0
+              1
+            
+            
+              TICKINT
+              SysTick exception request
+              enable
+              1
+              1
+            
+            
+              CLKSOURCE
+              Clock source selection
+              2
+              1
+            
+            
+              COUNTFLAG
+              COUNTFLAG
+              16
+              1
+            
+          
+        
+        
+          RVR
+          RVR
+          SysTick reload value register
+          0x4
+          0x20
+          read-write
+          0X00000000
+          
+            
+              RELOAD
+              RELOAD value
+              0
+              24
+            
+          
+        
+        
+          CVR
+          CVR
+          SysTick current value register
+          0x8
+          0x20
+          read-write
+          0X00000000
+          
+            
+              CURRENT
+              Current counter value
+              0
+              24
+            
+          
+        
+        
+          CALIB
+          CALIB
+          SysTick calibration value
+          register
+          0xC
+          0x20
+          read-write
+          0X00000000
+          
+            
+              TENMS
+              Calibration value
+              0
+              24
+            
+            
+              SKEW
+              SKEW flag: Indicates whether the TENMS
+              value is exact
+              30
+              1
+            
+            
+              NOREF
+              NOREF flag. Reads as zero
+              31
+              1
+            
+          
+        
+      
+    
+    
+      SCB
+      System control block
+      SCB
+      0xE000ED00
+      
+        0x0
+        0x41
+        registers
+      
+      
+        
+          CPUID
+          CPUID
+          CPUID base register
+          0x0
+          0x20
+          read-only
+          0x410FC241
+          
+            
+              Revision
+              Revision number
+              0
+              4
+            
+            
+              PartNo
+              Part number of the
+              processor
+              4
+              12
+            
+            
+              Architecture
+              Reads as 0xF
+              16
+              4
+            
+            
+              Variant
+              Variant number
+              20
+              4
+            
+            
+              Implementer
+              Implementer code
+              24
+              8
+            
+          
+        
+        
+          ICSR
+          ICSR
+          Interrupt control and state
+          register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              VECTACTIVE
+              Active vector
+              0
+              9
+            
+            
+              RETTOBASE
+              Return to base level
+              11
+              1
+            
+            
+              VECTPENDING
+              Pending vector
+              12
+              7
+            
+            
+              ISRPENDING
+              Interrupt pending flag
+              22
+              1
+            
+            
+              PENDSTCLR
+              SysTick exception clear-pending
+              bit
+              25
+              1
+            
+            
+              PENDSTSET
+              SysTick exception set-pending
+              bit
+              26
+              1
+            
+            
+              PENDSVCLR
+              PendSV clear-pending bit
+              27
+              1
+            
+            
+              PENDSVSET
+              PendSV set-pending bit
+              28
+              1
+            
+            
+              NMIPENDSET
+              NMI set-pending bit.
+              31
+              1
+            
+          
+        
+        
+          VTOR
+          VTOR
+          Vector table offset register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TBLOFF
+              Vector table base offset
+              field
+              7
+              25
+            
+          
+        
+        
+          AIRCR
+          AIRCR
+          Application interrupt and reset control
+          register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              VECTCLRACTIVE
+              VECTCLRACTIVE
+              1
+              1
+            
+            
+              SYSRESETREQ
+              SYSRESETREQ
+              2
+              1
+            
+            
+              ENDIANESS
+              ENDIANESS
+              15
+              1
+            
+            
+              VECTKEYSTAT
+              Register key
+              16
+              16
+            
+          
+        
+        
+          SCR
+          SCR
+          System control register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SLEEPONEXIT
+              SLEEPONEXIT
+              1
+              1
+            
+            
+              SLEEPDEEP
+              SLEEPDEEP
+              2
+              1
+            
+            
+              SEVEONPEND
+              Send Event on Pending bit
+              4
+              1
+            
+          
+        
+        
+          CCR
+          CCR
+          Configuration and control
+          register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NONBASETHRDENA
+              Configures how the processor enters
+              Thread mode
+              0
+              1
+            
+            
+              USERSETMPEND
+              USERSETMPEND
+              1
+              1
+            
+            
+              UNALIGN__TRP
+              UNALIGN_ TRP
+              3
+              1
+            
+            
+              DIV_0_TRP
+              DIV_0_TRP
+              4
+              1
+            
+            
+              BFHFNMIGN
+              BFHFNMIGN
+              8
+              1
+            
+            
+              STKALIGN
+              STKALIGN
+              9
+              1
+            
+          
+        
+        
+          SHPR2
+          SHPR2
+          System handler priority
+          registers
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_11
+              Priority of system handler
+              11
+              24
+              8
+            
+          
+        
+        
+          SHPR3
+          SHPR3
+          System handler priority
+          registers
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_14
+              Priority of system handler
+              14
+              16
+              8
+            
+            
+              PRI_15
+              Priority of system handler
+              15
+              24
+              8
+            
+          
+        
+      
+    
+  
+
diff --git a/src/chips/STM32L0x2.svd b/src/chips/STM32L0x2.svd
new file mode 100644
index 000000000..bc19e6f77
--- /dev/null
+++ b/src/chips/STM32L0x2.svd
@@ -0,0 +1,20698 @@
+
+
+  STM32L0x2
+  1.3
+  STM32L0x2
+  
+  
+    CM0+
+    r0p0
+    little
+    false
+    false
+    3
+    false
+  
+  
+  
+  8
+  
+  32
+  
+  0x20
+  0x0
+  0xFFFFFFFF
+  
+    
+      AES
+      Advanced encryption standard hardware
+      accelerator
+      AES
+      0x40026000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        AES_RNG_LPUART1
+        AES global interrupt RNG global interrupt and
+        LPUART1 global interrupt through
+        29
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DMAOUTEN
+              Enable DMA management of data output
+              phase
+              12
+              1
+            
+            
+              DMAINEN
+              Enable DMA management of data input
+              phase
+              11
+              1
+            
+            
+              ERRIE
+              Error interrupt enable
+              10
+              1
+            
+            
+              CCFIE
+              CCF flag interrupt enable
+              9
+              1
+            
+            
+              ERRC
+              Error clear
+              8
+              1
+            
+            
+              CCFC
+              Computation Complete Flag
+              Clear
+              7
+              1
+            
+            
+              CHMOD
+              AES chaining mode
+              5
+              2
+            
+            
+              MODE
+              AES operating mode
+              3
+              2
+            
+            
+              DATATYPE
+              Data type selection (for data in and
+              data out to/from the cryptographic
+              block)
+              1
+              2
+            
+            
+              EN
+              AES enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x4
+          0x20
+          read-only
+          0x00000000
+          
+            
+              WRERR
+              Write error flag
+              2
+              1
+            
+            
+              RDERR
+              Read error flag
+              1
+              1
+            
+            
+              CCF
+              Computation complete flag
+              0
+              1
+            
+          
+        
+        
+          DINR
+          DINR
+          data input register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_DINR
+              Data Input Register.
+              0
+              32
+            
+          
+        
+        
+          DOUTR
+          DOUTR
+          data output register
+          0xC
+          0x20
+          read-only
+          0x00000000
+          
+            
+              AES_DOUTR
+              Data output register
+              0
+              32
+            
+          
+        
+        
+          KEYR0
+          KEYR0
+          key register 0
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR0
+              Data Output Register (LSB key
+              [31:0])
+              0
+              32
+            
+          
+        
+        
+          KEYR1
+          KEYR1
+          key register 1
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR1
+              AES key register (key
+              [63:32])
+              0
+              32
+            
+          
+        
+        
+          KEYR2
+          KEYR2
+          key register 2
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR2
+              AES key register (key
+              [95:64])
+              0
+              32
+            
+          
+        
+        
+          KEYR3
+          KEYR3
+          key register 3
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR3
+              AES key register (MSB key
+              [127:96])
+              0
+              32
+            
+          
+        
+        
+          IVR0
+          IVR0
+          initialization vector register
+          0
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR0
+              initialization vector register (LSB IVR
+              [31:0])
+              0
+              32
+            
+          
+        
+        
+          IVR1
+          IVR1
+          initialization vector register
+          1
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR1
+              Initialization Vector Register (IVR
+              [63:32])
+              0
+              32
+            
+          
+        
+        
+          IVR2
+          IVR2
+          initialization vector register
+          2
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR2
+              Initialization Vector Register (IVR
+              [95:64])
+              0
+              32
+            
+          
+        
+        
+          IVR3
+          IVR3
+          initialization vector register
+          3
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR3
+              Initialization Vector Register (MSB IVR
+              [127:96])
+              0
+              32
+            
+          
+        
+      
+    
+    
+      DAC
+      Digital-to-analog converter
+      DAC
+      0x40007400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DMAUDRIE1
+              DAC channel1 DMA Underrun Interrupt
+              enable
+              13
+              1
+            
+            
+              DMAEN1
+              DAC channel1 DMA enable
+              12
+              1
+            
+            
+              MAMP1
+              DAC channel1 mask/amplitude
+              selector
+              8
+              4
+            
+            
+              WAVE1
+              DAC channel1 noise/triangle wave
+              generation enable
+              6
+              2
+            
+            
+              TSEL1
+              DAC channel1 trigger
+              selection
+              3
+              3
+            
+            
+              TEN1
+              DAC channel1 trigger
+              enable
+              2
+              1
+            
+            
+              BOFF1
+              DAC channel1 output buffer
+              disable
+              1
+              1
+            
+            
+              EN1
+              DAC channel1 enable
+              0
+              1
+            
+          
+        
+        
+          SWTRIGR
+          SWTRIGR
+          software trigger register
+          0x4
+          0x20
+          write-only
+          0x00000000
+          
+            
+              SWTRIG1
+              DAC channel1 software
+              trigger
+              0
+              1
+            
+          
+        
+        
+          DHR12R1
+          DHR12R1
+          channel1 12-bit right-aligned data holding
+          register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 12-bit right-aligned
+              data
+              0
+              12
+            
+          
+        
+        
+          DHR12L1
+          DHR12L1
+          channel1 12-bit left-aligned data holding
+          register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 12-bit left-aligned
+              data
+              4
+              12
+            
+          
+        
+        
+          DHR8R1
+          DHR8R1
+          channel1 8-bit right-aligned data holding
+          register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 8-bit right-aligned
+              data
+              0
+              8
+            
+          
+        
+        
+          DOR1
+          DOR1
+          channel1 data output register
+          0x2C
+          0x20
+          read-only
+          0x00000000
+          
+            
+              DACC1DOR
+              DAC channel1 data output
+              0
+              12
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DMAUDR1
+              DAC channel1 DMA underrun
+              flag
+              13
+              1
+            
+          
+        
+        
+          DHR12R2
+          DHR12R2
+          channel2 12-bit right-aligned data holding
+          register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC2DHR
+              DAC channel2 12-bit right-aligned
+              data
+              0
+              12
+            
+          
+        
+        
+          DHR12L2
+          DHR12L2
+          channel2 12-bit left-aligned data holding
+          register
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC2DHR
+              DAC channel2 12-bit left-aligned
+              data
+              4
+              12
+            
+          
+        
+        
+          DHR8R2
+          DHR8R2
+          channel2 8-bit right-aligned data holding
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC2DHR
+              DAC channel2 8-bit right-aligned
+              data
+              0
+              8
+            
+          
+        
+        
+          DHR12RD
+          DHR12RD
+          Dual DAC 12-bit right-aligned data holding
+          register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 12-bit right-aligned
+              data
+              0
+              12
+            
+            
+              DACC2DHR
+              DAC channel2 12-bit right-aligned
+              data
+              16
+              12
+            
+          
+        
+        
+          DHR12LD
+          DHR12LD
+          Dual DAC 12-bit left-aligned data holding
+          register
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 12-bit left-aligned
+              data
+              4
+              12
+            
+            
+              DACC2DHR
+              DAC channel2 12-bit left-aligned
+              data
+              20
+              12
+            
+          
+        
+        
+          DHR8RD
+          DHR8RD
+          Dual DAC 8-bit right-aligned data holding
+          register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 8-bit right-aligned
+              data
+              0
+              8
+            
+            
+              DACC2DHR
+              DAC channel2 8-bit right-aligned
+              data
+              8
+              8
+            
+          
+        
+        
+          DOR2
+          DOR2
+          channel2 data output register
+          0x30
+          0x20
+          read-only
+          0x00000000
+          
+            
+              DACC2DOR
+              DAC channel2 data output
+              0
+              12
+            
+          
+        
+      
+    
+    
+      DMA1
+      Direct memory access controller
+      DMA
+      0x40020000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        DMA1_Channel1
+        DMA1 Channel1 global interrupt
+        9
+      
+      
+        DMA1_Channel2_3
+        DMA1 Channel2 and 3 interrupts
+        10
+      
+      
+        DMA1_Channel4_7
+        DMA1 Channel4 to 7 interrupts
+        11
+      
+      
+        
+          ISR
+          ISR
+          interrupt status register
+          0x0
+          0x20
+          read-only
+          0x00000000
+          
+            
+              TEIF7
+              Channel x transfer error flag (x = 1
+              ..7)
+              27
+              1
+            
+            
+              HTIF7
+              Channel x half transfer flag (x = 1
+              ..7)
+              26
+              1
+            
+            
+              TCIF7
+              Channel x transfer complete flag (x = 1
+              ..7)
+              25
+              1
+            
+            
+              GIF7
+              Channel x global interrupt flag (x = 1
+              ..7)
+              24
+              1
+            
+            
+              TEIF6
+              Channel x transfer error flag (x = 1
+              ..7)
+              23
+              1
+            
+            
+              HTIF6
+              Channel x half transfer flag (x = 1
+              ..7)
+              22
+              1
+            
+            
+              TCIF6
+              Channel x transfer complete flag (x = 1
+              ..7)
+              21
+              1
+            
+            
+              GIF6
+              Channel x global interrupt flag (x = 1
+              ..7)
+              20
+              1
+            
+            
+              TEIF5
+              Channel x transfer error flag (x = 1
+              ..7)
+              19
+              1
+            
+            
+              HTIF5
+              Channel x half transfer flag (x = 1
+              ..7)
+              18
+              1
+            
+            
+              TCIF5
+              Channel x transfer complete flag (x = 1
+              ..7)
+              17
+              1
+            
+            
+              GIF5
+              Channel x global interrupt flag (x = 1
+              ..7)
+              16
+              1
+            
+            
+              TEIF4
+              Channel x transfer error flag (x = 1
+              ..7)
+              15
+              1
+            
+            
+              HTIF4
+              Channel x half transfer flag (x = 1
+              ..7)
+              14
+              1
+            
+            
+              TCIF4
+              Channel x transfer complete flag (x = 1
+              ..7)
+              13
+              1
+            
+            
+              GIF4
+              Channel x global interrupt flag (x = 1
+              ..7)
+              12
+              1
+            
+            
+              TEIF3
+              Channel x transfer error flag (x = 1
+              ..7)
+              11
+              1
+            
+            
+              HTIF3
+              Channel x half transfer flag (x = 1
+              ..7)
+              10
+              1
+            
+            
+              TCIF3
+              Channel x transfer complete flag (x = 1
+              ..7)
+              9
+              1
+            
+            
+              GIF3
+              Channel x global interrupt flag (x = 1
+              ..7)
+              8
+              1
+            
+            
+              TEIF2
+              Channel x transfer error flag (x = 1
+              ..7)
+              7
+              1
+            
+            
+              HTIF2
+              Channel x half transfer flag (x = 1
+              ..7)
+              6
+              1
+            
+            
+              TCIF2
+              Channel x transfer complete flag (x = 1
+              ..7)
+              5
+              1
+            
+            
+              GIF2
+              Channel x global interrupt flag (x = 1
+              ..7)
+              4
+              1
+            
+            
+              TEIF1
+              Channel x transfer error flag (x = 1
+              ..7)
+              3
+              1
+            
+            
+              HTIF1
+              Channel x half transfer flag (x = 1
+              ..7)
+              2
+              1
+            
+            
+              TCIF1
+              Channel x transfer complete flag (x = 1
+              ..7)
+              1
+              1
+            
+            
+              GIF1
+              Channel x global interrupt flag (x = 1
+              ..7)
+              0
+              1
+            
+          
+        
+        
+          IFCR
+          IFCR
+          interrupt flag clear register
+          0x4
+          0x20
+          write-only
+          0x00000000
+          
+            
+              CTEIF7
+              Channel x transfer error clear (x = 1
+              ..7)
+              27
+              1
+            
+            
+              CHTIF7
+              Channel x half transfer clear (x = 1
+              ..7)
+              26
+              1
+            
+            
+              CTCIF7
+              Channel x transfer complete clear (x = 1
+              ..7)
+              25
+              1
+            
+            
+              CGIF7
+              Channel x global interrupt clear (x = 1
+              ..7)
+              24
+              1
+            
+            
+              CTEIF6
+              Channel x transfer error clear (x = 1
+              ..7)
+              23
+              1
+            
+            
+              CHTIF6
+              Channel x half transfer clear (x = 1
+              ..7)
+              22
+              1
+            
+            
+              CTCIF6
+              Channel x transfer complete clear (x = 1
+              ..7)
+              21
+              1
+            
+            
+              CGIF6
+              Channel x global interrupt clear (x = 1
+              ..7)
+              20
+              1
+            
+            
+              CTEIF5
+              Channel x transfer error clear (x = 1
+              ..7)
+              19
+              1
+            
+            
+              CHTIF5
+              Channel x half transfer clear (x = 1
+              ..7)
+              18
+              1
+            
+            
+              CTCIF5
+              Channel x transfer complete clear (x = 1
+              ..7)
+              17
+              1
+            
+            
+              CGIF5
+              Channel x global interrupt clear (x = 1
+              ..7)
+              16
+              1
+            
+            
+              CTEIF4
+              Channel x transfer error clear (x = 1
+              ..7)
+              15
+              1
+            
+            
+              CHTIF4
+              Channel x half transfer clear (x = 1
+              ..7)
+              14
+              1
+            
+            
+              CTCIF4
+              Channel x transfer complete clear (x = 1
+              ..7)
+              13
+              1
+            
+            
+              CGIF4
+              Channel x global interrupt clear (x = 1
+              ..7)
+              12
+              1
+            
+            
+              CTEIF3
+              Channel x transfer error clear (x = 1
+              ..7)
+              11
+              1
+            
+            
+              CHTIF3
+              Channel x half transfer clear (x = 1
+              ..7)
+              10
+              1
+            
+            
+              CTCIF3
+              Channel x transfer complete clear (x = 1
+              ..7)
+              9
+              1
+            
+            
+              CGIF3
+              Channel x global interrupt clear (x = 1
+              ..7)
+              8
+              1
+            
+            
+              CTEIF2
+              Channel x transfer error clear (x = 1
+              ..7)
+              7
+              1
+            
+            
+              CHTIF2
+              Channel x half transfer clear (x = 1
+              ..7)
+              6
+              1
+            
+            
+              CTCIF2
+              Channel x transfer complete clear (x = 1
+              ..7)
+              5
+              1
+            
+            
+              CGIF2
+              Channel x global interrupt clear (x = 1
+              ..7)
+              4
+              1
+            
+            
+              CTEIF1
+              Channel x transfer error clear (x = 1
+              ..7)
+              3
+              1
+            
+            
+              CHTIF1
+              Channel x half transfer clear (x = 1
+              ..7)
+              2
+              1
+            
+            
+              CTCIF1
+              Channel x transfer complete clear (x = 1
+              ..7)
+              1
+              1
+            
+            
+              CGIF1
+              Channel x global interrupt clear (x = 1
+              ..7)
+              0
+              1
+            
+          
+        
+        
+          CCR1
+          CCR1
+          channel x configuration
+          register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR1
+          CNDTR1
+          channel x number of data
+          register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR1
+          CPAR1
+          channel x peripheral address
+          register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR1
+          CMAR1
+          channel x memory address
+          register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR2
+          CCR2
+          channel x configuration
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR2
+          CNDTR2
+          channel x number of data
+          register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR2
+          CPAR2
+          channel x peripheral address
+          register
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR2
+          CMAR2
+          channel x memory address
+          register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR3
+          CCR3
+          channel x configuration
+          register
+          0x30
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR3
+          CNDTR3
+          channel x number of data
+          register
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR3
+          CPAR3
+          channel x peripheral address
+          register
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR3
+          CMAR3
+          channel x memory address
+          register
+          0x3C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR4
+          CCR4
+          channel x configuration
+          register
+          0x44
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR4
+          CNDTR4
+          channel x number of data
+          register
+          0x48
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR4
+          CPAR4
+          channel x peripheral address
+          register
+          0x4C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR4
+          CMAR4
+          channel x memory address
+          register
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR5
+          CCR5
+          channel x configuration
+          register
+          0x58
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR5
+          CNDTR5
+          channel x number of data
+          register
+          0x5C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR5
+          CPAR5
+          channel x peripheral address
+          register
+          0x60
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR5
+          CMAR5
+          channel x memory address
+          register
+          0x64
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR6
+          CCR6
+          channel x configuration
+          register
+          0x6C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR6
+          CNDTR6
+          channel x number of data
+          register
+          0x70
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR6
+          CPAR6
+          channel x peripheral address
+          register
+          0x74
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR6
+          CMAR6
+          channel x memory address
+          register
+          0x78
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR7
+          CCR7
+          channel x configuration
+          register
+          0x80
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR7
+          CNDTR7
+          channel x number of data
+          register
+          0x84
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR7
+          CPAR7
+          channel x peripheral address
+          register
+          0x88
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR7
+          CMAR7
+          channel x memory address
+          register
+          0x8C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CSELR
+          CSELR
+          channel selection register
+          0xA8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              C7S
+              DMA channel 7 selection
+              24
+              4
+            
+            
+              C6S
+              DMA channel 6 selection
+              20
+              4
+            
+            
+              C5S
+              DMA channel 5 selection
+              16
+              4
+            
+            
+              C4S
+              DMA channel 4 selection
+              12
+              4
+            
+            
+              C3S
+              DMA channel 3 selection
+              8
+              4
+            
+            
+              C2S
+              DMA channel 2 selection
+              4
+              4
+            
+            
+              C1S
+              DMA channel 1 selection
+              0
+              4
+            
+          
+        
+      
+    
+    
+      CRC
+      Cyclic redundancy check calculation
+      unit
+      CRC
+      0x40023000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          DR
+          DR
+          Data register
+          0x0
+          0x20
+          read-write
+          0xFFFFFFFF
+          
+            
+              DR
+              Data register bits
+              0
+              32
+            
+          
+        
+        
+          IDR
+          IDR
+          Independent data register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IDR
+              General-purpose 8-bit data register
+              bits
+              0
+              8
+            
+          
+        
+        
+          CR
+          CR
+          Control register
+          0x8
+          0x20
+          0x00000000
+          
+            
+              REV_OUT
+              Reverse output data
+              7
+              1
+              read-write
+            
+            
+              REV_IN
+              Reverse input data
+              5
+              2
+              read-write
+            
+            
+              POLYSIZE
+              Polynomial size
+              3
+              2
+              read-write
+            
+            
+              RESET
+              RESET bit
+              0
+              1
+              write-only
+            
+          
+        
+        
+          INIT
+          INIT
+          Initial CRC value
+          0x10
+          0x20
+          read-write
+          0xFFFFFFFF
+          
+            
+              CRC_INIT
+              Programmable initial CRC
+              value
+              0
+              32
+            
+          
+        
+        
+          POL
+          POL
+          polynomial
+          0x14
+          0x20
+          read-write
+          0x04C11DB7
+          
+            
+              Polynomialcoefficients
+              Programmable polynomial
+              0
+              32
+            
+          
+        
+      
+    
+    
+      GPIOA
+      General-purpose I/Os
+      GPIO
+      0x50000000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          MODER
+          MODER
+          GPIO port mode register
+          0x0
+          0x20
+          read-write
+          0xEBFFFCFF
+          
+            
+              MODE0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+            
+              MODE1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              MODE2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              MODE3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              MODE4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              MODE5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              MODE6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              MODE7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              MODE8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              MODE9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              MODE10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              MODE11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              MODE12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              MODE13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              MODE14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              MODE15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+          
+        
+        
+          OTYPER
+          OTYPER
+          GPIO port output type register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OT15
+              Port x configuration bits (y =
+              0..15)
+              15
+              1
+            
+            
+              OT14
+              Port x configuration bits (y =
+              0..15)
+              14
+              1
+            
+            
+              OT13
+              Port x configuration bits (y =
+              0..15)
+              13
+              1
+            
+            
+              OT12
+              Port x configuration bits (y =
+              0..15)
+              12
+              1
+            
+            
+              OT11
+              Port x configuration bits (y =
+              0..15)
+              11
+              1
+            
+            
+              OT10
+              Port x configuration bits (y =
+              0..15)
+              10
+              1
+            
+            
+              OT9
+              Port x configuration bits (y =
+              0..15)
+              9
+              1
+            
+            
+              OT8
+              Port x configuration bits (y =
+              0..15)
+              8
+              1
+            
+            
+              OT7
+              Port x configuration bits (y =
+              0..15)
+              7
+              1
+            
+            
+              OT6
+              Port x configuration bits (y =
+              0..15)
+              6
+              1
+            
+            
+              OT5
+              Port x configuration bits (y =
+              0..15)
+              5
+              1
+            
+            
+              OT4
+              Port x configuration bits (y =
+              0..15)
+              4
+              1
+            
+            
+              OT3
+              Port x configuration bits (y =
+              0..15)
+              3
+              1
+            
+            
+              OT2
+              Port x configuration bits (y =
+              0..15)
+              2
+              1
+            
+            
+              OT1
+              Port x configuration bits (y =
+              0..15)
+              1
+              1
+            
+            
+              OT0
+              Port x configuration bits (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          OSPEEDR
+          OSPEEDR
+          GPIO port output speed
+          register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OSPEED15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              OSPEED14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              OSPEED13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              OSPEED12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              OSPEED11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              OSPEED10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              OSPEED9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              OSPEED8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              OSPEED7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              OSPEED6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              OSPEED5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              OSPEED4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              OSPEED3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              OSPEED2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              OSPEED1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              OSPEED0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          PUPDR
+          PUPDR
+          GPIO port pull-up/pull-down
+          register
+          0xC
+          0x20
+          read-write
+          0x24000000
+          
+            
+              PUPD15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              PUPD14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              PUPD13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              PUPD12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              PUPD11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              PUPD10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              PUPD9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              PUPD8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              PUPD7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              PUPD6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              PUPD5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              PUPD4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              PUPD3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              PUPD2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              PUPD1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              PUPD0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          IDR
+          IDR
+          GPIO port input data register
+          0x10
+          0x20
+          read-only
+          0x00000000
+          
+            
+              ID15
+              Port input data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              ID14
+              Port input data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              ID13
+              Port input data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              ID12
+              Port input data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              ID11
+              Port input data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              ID10
+              Port input data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              ID9
+              Port input data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              ID8
+              Port input data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              ID7
+              Port input data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              ID6
+              Port input data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              ID5
+              Port input data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              ID4
+              Port input data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              ID3
+              Port input data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              ID2
+              Port input data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              ID1
+              Port input data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              ID0
+              Port input data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          ODR
+          ODR
+          GPIO port output data register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OD15
+              Port output data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              OD14
+              Port output data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              OD13
+              Port output data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              OD12
+              Port output data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              OD11
+              Port output data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              OD10
+              Port output data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              OD9
+              Port output data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              OD8
+              Port output data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              OD7
+              Port output data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              OD6
+              Port output data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              OD5
+              Port output data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              OD4
+              Port output data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              OD3
+              Port output data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              OD2
+              Port output data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              OD1
+              Port output data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              OD0
+              Port output data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          BSRR
+          BSRR
+          GPIO port bit set/reset
+          register
+          0x18
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x reset bit y (y =
+              0..15)
+              31
+              1
+            
+            
+              BR14
+              Port x reset bit y (y =
+              0..15)
+              30
+              1
+            
+            
+              BR13
+              Port x reset bit y (y =
+              0..15)
+              29
+              1
+            
+            
+              BR12
+              Port x reset bit y (y =
+              0..15)
+              28
+              1
+            
+            
+              BR11
+              Port x reset bit y (y =
+              0..15)
+              27
+              1
+            
+            
+              BR10
+              Port x reset bit y (y =
+              0..15)
+              26
+              1
+            
+            
+              BR9
+              Port x reset bit y (y =
+              0..15)
+              25
+              1
+            
+            
+              BR8
+              Port x reset bit y (y =
+              0..15)
+              24
+              1
+            
+            
+              BR7
+              Port x reset bit y (y =
+              0..15)
+              23
+              1
+            
+            
+              BR6
+              Port x reset bit y (y =
+              0..15)
+              22
+              1
+            
+            
+              BR5
+              Port x reset bit y (y =
+              0..15)
+              21
+              1
+            
+            
+              BR4
+              Port x reset bit y (y =
+              0..15)
+              20
+              1
+            
+            
+              BR3
+              Port x reset bit y (y =
+              0..15)
+              19
+              1
+            
+            
+              BR2
+              Port x reset bit y (y =
+              0..15)
+              18
+              1
+            
+            
+              BR1
+              Port x reset bit y (y =
+              0..15)
+              17
+              1
+            
+            
+              BR0
+              Port x reset bit y (y =
+              0..15)
+              16
+              1
+            
+            
+              BS15
+              Port x set bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              BS14
+              Port x set bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              BS13
+              Port x set bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              BS12
+              Port x set bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              BS11
+              Port x set bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              BS10
+              Port x set bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              BS9
+              Port x set bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              BS8
+              Port x set bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              BS7
+              Port x set bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              BS6
+              Port x set bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              BS5
+              Port x set bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              BS4
+              Port x set bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              BS3
+              Port x set bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              BS2
+              Port x set bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              BS1
+              Port x set bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              BS0
+              Port x set bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          LCKR
+          LCKR
+          GPIO port configuration lock
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LCKK
+              Port x lock bit y (y=
+              0..15)
+              16
+              1
+            
+            
+              LCK15
+              Port x lock bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              LCK14
+              Port x lock bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              LCK13
+              Port x lock bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              LCK12
+              Port x lock bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              LCK11
+              Port x lock bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              LCK10
+              Port x lock bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              LCK9
+              Port x lock bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              LCK8
+              Port x lock bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              LCK7
+              Port x lock bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              LCK6
+              Port x lock bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              LCK5
+              Port x lock bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              LCK4
+              Port x lock bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              LCK3
+              Port x lock bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              LCK2
+              Port x lock bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              LCK1
+              Port x lock bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              LCK0
+              Port x lock bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          AFRL
+          AFRL
+          GPIO alternate function low
+          register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL7
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              28
+              4
+            
+            
+              AFSEL6
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              24
+              4
+            
+            
+              AFSEL5
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              20
+              4
+            
+            
+              AFSEL4
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              16
+              4
+            
+            
+              AFSEL3
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              12
+              4
+            
+            
+              AFSEL2
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              8
+              4
+            
+            
+              AFSEL1
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              4
+              4
+            
+            
+              AFSEL0
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              0
+              4
+            
+          
+        
+        
+          AFRH
+          AFRH
+          GPIO alternate function high
+          register
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL15
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              28
+              4
+            
+            
+              AFSEL14
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              24
+              4
+            
+            
+              AFSEL13
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              20
+              4
+            
+            
+              AFSEL12
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              16
+              4
+            
+            
+              AFSEL11
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              12
+              4
+            
+            
+              AFSEL10
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              8
+              4
+            
+            
+              AFSEL9
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              4
+              4
+            
+            
+              AFSEL8
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              0
+              4
+            
+          
+        
+        
+          BRR
+          BRR
+          GPIO port bit reset register
+          0x28
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x Reset bit y (y= 0 ..
+              15)
+              15
+              1
+            
+            
+              BR14
+              Port x Reset bit y (y= 0 ..
+              15)
+              14
+              1
+            
+            
+              BR13
+              Port x Reset bit y (y= 0 ..
+              15)
+              13
+              1
+            
+            
+              BR12
+              Port x Reset bit y (y= 0 ..
+              15)
+              12
+              1
+            
+            
+              BR11
+              Port x Reset bit y (y= 0 ..
+              15)
+              11
+              1
+            
+            
+              BR10
+              Port x Reset bit y (y= 0 ..
+              15)
+              10
+              1
+            
+            
+              BR9
+              Port x Reset bit y (y= 0 ..
+              15)
+              9
+              1
+            
+            
+              BR8
+              Port x Reset bit y (y= 0 ..
+              15)
+              8
+              1
+            
+            
+              BR7
+              Port x Reset bit y (y= 0 ..
+              15)
+              7
+              1
+            
+            
+              BR6
+              Port x Reset bit y (y= 0 ..
+              15)
+              6
+              1
+            
+            
+              BR5
+              Port x Reset bit y (y= 0 ..
+              15)
+              5
+              1
+            
+            
+              BR4
+              Port x Reset bit y (y= 0 ..
+              15)
+              4
+              1
+            
+            
+              BR3
+              Port x Reset bit y (y= 0 ..
+              15)
+              3
+              1
+            
+            
+              BR2
+              Port x Reset bit y (y= 0 ..
+              15)
+              2
+              1
+            
+            
+              BR1
+              Port x Reset bit y (y= 0 ..
+              15)
+              1
+              1
+            
+            
+              BR0
+              Port x Reset bit y (y= 0 ..
+              15)
+              0
+              1
+            
+          
+        
+      
+    
+    
+      GPIOB
+      General-purpose I/Os
+      GPIO
+      0x50000400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          MODER
+          MODER
+          GPIO port mode register
+          0x0
+          0x20
+          read-write
+          0xFFFFFFFF
+          
+            
+              MODE15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              MODE14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              MODE13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              MODE12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              MODE11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              MODE10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              MODE9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              MODE8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              MODE7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              MODE6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              MODE5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              MODE4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              MODE3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              MODE2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              MODE1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              MODE0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          OTYPER
+          OTYPER
+          GPIO port output type register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OT15
+              Port x configuration bits (y =
+              0..15)
+              15
+              1
+            
+            
+              OT14
+              Port x configuration bits (y =
+              0..15)
+              14
+              1
+            
+            
+              OT13
+              Port x configuration bits (y =
+              0..15)
+              13
+              1
+            
+            
+              OT12
+              Port x configuration bits (y =
+              0..15)
+              12
+              1
+            
+            
+              OT11
+              Port x configuration bits (y =
+              0..15)
+              11
+              1
+            
+            
+              OT10
+              Port x configuration bits (y =
+              0..15)
+              10
+              1
+            
+            
+              OT9
+              Port x configuration bits (y =
+              0..15)
+              9
+              1
+            
+            
+              OT8
+              Port x configuration bits (y =
+              0..15)
+              8
+              1
+            
+            
+              OT7
+              Port x configuration bits (y =
+              0..15)
+              7
+              1
+            
+            
+              OT6
+              Port x configuration bits (y =
+              0..15)
+              6
+              1
+            
+            
+              OT5
+              Port x configuration bits (y =
+              0..15)
+              5
+              1
+            
+            
+              OT4
+              Port x configuration bits (y =
+              0..15)
+              4
+              1
+            
+            
+              OT3
+              Port x configuration bits (y =
+              0..15)
+              3
+              1
+            
+            
+              OT2
+              Port x configuration bits (y =
+              0..15)
+              2
+              1
+            
+            
+              OT1
+              Port x configuration bits (y =
+              0..15)
+              1
+              1
+            
+            
+              OT0
+              Port x configuration bits (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          OSPEEDR
+          OSPEEDR
+          GPIO port output speed
+          register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OSPEED15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              OSPEED14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              OSPEED13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              OSPEED12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              OSPEED11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              OSPEED10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              OSPEED9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              OSPEED8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              OSPEED7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              OSPEED6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              OSPEED5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              OSPEED4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              OSPEED3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              OSPEED2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              OSPEED1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              OSPEED0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          PUPDR
+          PUPDR
+          GPIO port pull-up/pull-down
+          register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PUPD15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              PUPD14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              PUPD13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              PUPD12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              PUPD11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              PUPD10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              PUPD9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              PUPD8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              PUPD7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              PUPD6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              PUPD5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              PUPD4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              PUPD3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              PUPD2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              PUPD1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              PUPD0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          IDR
+          IDR
+          GPIO port input data register
+          0x10
+          0x20
+          read-only
+          0x00000000
+          
+            
+              ID15
+              Port input data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              ID14
+              Port input data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              ID13
+              Port input data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              ID12
+              Port input data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              ID11
+              Port input data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              ID10
+              Port input data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              ID9
+              Port input data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              ID8
+              Port input data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              ID7
+              Port input data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              ID6
+              Port input data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              ID5
+              Port input data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              ID4
+              Port input data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              ID3
+              Port input data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              ID2
+              Port input data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              ID1
+              Port input data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              ID0
+              Port input data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          ODR
+          ODR
+          GPIO port output data register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OD15
+              Port output data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              OD14
+              Port output data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              OD13
+              Port output data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              OD12
+              Port output data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              OD11
+              Port output data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              OD10
+              Port output data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              OD9
+              Port output data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              OD8
+              Port output data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              OD7
+              Port output data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              OD6
+              Port output data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              OD5
+              Port output data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              OD4
+              Port output data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              OD3
+              Port output data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              OD2
+              Port output data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              OD1
+              Port output data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              OD0
+              Port output data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          BSRR
+          BSRR
+          GPIO port bit set/reset
+          register
+          0x18
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x reset bit y (y =
+              0..15)
+              31
+              1
+            
+            
+              BR14
+              Port x reset bit y (y =
+              0..15)
+              30
+              1
+            
+            
+              BR13
+              Port x reset bit y (y =
+              0..15)
+              29
+              1
+            
+            
+              BR12
+              Port x reset bit y (y =
+              0..15)
+              28
+              1
+            
+            
+              BR11
+              Port x reset bit y (y =
+              0..15)
+              27
+              1
+            
+            
+              BR10
+              Port x reset bit y (y =
+              0..15)
+              26
+              1
+            
+            
+              BR9
+              Port x reset bit y (y =
+              0..15)
+              25
+              1
+            
+            
+              BR8
+              Port x reset bit y (y =
+              0..15)
+              24
+              1
+            
+            
+              BR7
+              Port x reset bit y (y =
+              0..15)
+              23
+              1
+            
+            
+              BR6
+              Port x reset bit y (y =
+              0..15)
+              22
+              1
+            
+            
+              BR5
+              Port x reset bit y (y =
+              0..15)
+              21
+              1
+            
+            
+              BR4
+              Port x reset bit y (y =
+              0..15)
+              20
+              1
+            
+            
+              BR3
+              Port x reset bit y (y =
+              0..15)
+              19
+              1
+            
+            
+              BR2
+              Port x reset bit y (y =
+              0..15)
+              18
+              1
+            
+            
+              BR1
+              Port x reset bit y (y =
+              0..15)
+              17
+              1
+            
+            
+              BR0
+              Port x reset bit y (y =
+              0..15)
+              16
+              1
+            
+            
+              BS15
+              Port x set bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              BS14
+              Port x set bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              BS13
+              Port x set bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              BS12
+              Port x set bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              BS11
+              Port x set bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              BS10
+              Port x set bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              BS9
+              Port x set bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              BS8
+              Port x set bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              BS7
+              Port x set bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              BS6
+              Port x set bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              BS5
+              Port x set bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              BS4
+              Port x set bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              BS3
+              Port x set bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              BS2
+              Port x set bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              BS1
+              Port x set bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              BS0
+              Port x set bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          LCKR
+          LCKR
+          GPIO port configuration lock
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LCKK
+              Port x lock bit y (y=
+              0..15)
+              16
+              1
+            
+            
+              LCK15
+              Port x lock bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              LCK14
+              Port x lock bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              LCK13
+              Port x lock bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              LCK12
+              Port x lock bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              LCK11
+              Port x lock bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              LCK10
+              Port x lock bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              LCK9
+              Port x lock bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              LCK8
+              Port x lock bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              LCK7
+              Port x lock bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              LCK6
+              Port x lock bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              LCK5
+              Port x lock bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              LCK4
+              Port x lock bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              LCK3
+              Port x lock bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              LCK2
+              Port x lock bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              LCK1
+              Port x lock bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              LCK0
+              Port x lock bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          AFRL
+          AFRL
+          GPIO alternate function low
+          register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL7
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              28
+              4
+            
+            
+              AFSEL6
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              24
+              4
+            
+            
+              AFSEL5
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              20
+              4
+            
+            
+              AFSEL4
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              16
+              4
+            
+            
+              AFSEL3
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              12
+              4
+            
+            
+              AFSEL2
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              8
+              4
+            
+            
+              AFSEL1
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              4
+              4
+            
+            
+              AFSEL0
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              0
+              4
+            
+          
+        
+        
+          AFRH
+          AFRH
+          GPIO alternate function high
+          register
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL15
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              28
+              4
+            
+            
+              AFSEL14
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              24
+              4
+            
+            
+              AFSEL13
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              20
+              4
+            
+            
+              AFSEL12
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              16
+              4
+            
+            
+              AFSEL11
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              12
+              4
+            
+            
+              AFSEL10
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              8
+              4
+            
+            
+              AFSEL9
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              4
+              4
+            
+            
+              AFSEL8
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              0
+              4
+            
+          
+        
+        
+          BRR
+          BRR
+          GPIO port bit reset register
+          0x28
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x Reset bit y (y= 0 ..
+              15)
+              15
+              1
+            
+            
+              BR14
+              Port x Reset bit y (y= 0 ..
+              15)
+              14
+              1
+            
+            
+              BR13
+              Port x Reset bit y (y= 0 ..
+              15)
+              13
+              1
+            
+            
+              BR12
+              Port x Reset bit y (y= 0 ..
+              15)
+              12
+              1
+            
+            
+              BR11
+              Port x Reset bit y (y= 0 ..
+              15)
+              11
+              1
+            
+            
+              BR10
+              Port x Reset bit y (y= 0 ..
+              15)
+              10
+              1
+            
+            
+              BR9
+              Port x Reset bit y (y= 0 ..
+              15)
+              9
+              1
+            
+            
+              BR8
+              Port x Reset bit y (y= 0 ..
+              15)
+              8
+              1
+            
+            
+              BR7
+              Port x Reset bit y (y= 0 ..
+              15)
+              7
+              1
+            
+            
+              BR6
+              Port x Reset bit y (y= 0 ..
+              15)
+              6
+              1
+            
+            
+              BR5
+              Port x Reset bit y (y= 0 ..
+              15)
+              5
+              1
+            
+            
+              BR4
+              Port x Reset bit y (y= 0 ..
+              15)
+              4
+              1
+            
+            
+              BR3
+              Port x Reset bit y (y= 0 ..
+              15)
+              3
+              1
+            
+            
+              BR2
+              Port x Reset bit y (y= 0 ..
+              15)
+              2
+              1
+            
+            
+              BR1
+              Port x Reset bit y (y= 0 ..
+              15)
+              1
+              1
+            
+            
+              BR0
+              Port x Reset bit y (y= 0 ..
+              15)
+              0
+              1
+            
+          
+        
+      
+    
+    
+      GPIOC
+      0x50000800
+    
+    
+      GPIOD
+      0x50000C00
+    
+    
+      GPIOH
+      0x50001C00
+    
+    
+      GPIOE
+      0x50001000
+    
+    
+      LPTIM
+      Low power timer
+      LPTIM
+      0x40007C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        LPTIM1
+        LPTIMER1 interrupt through
+        EXTI29
+        13
+      
+      
+        
+          ISR
+          ISR
+          Interrupt and Status Register
+          0x0
+          0x20
+          read-only
+          0x00000000
+          
+            
+              DOWN
+              Counter direction change up to
+              down
+              6
+              1
+            
+            
+              UP
+              Counter direction change down to
+              up
+              5
+              1
+            
+            
+              ARROK
+              Autoreload register update
+              OK
+              4
+              1
+            
+            
+              CMPOK
+              Compare register update OK
+              3
+              1
+            
+            
+              EXTTRIG
+              External trigger edge
+              event
+              2
+              1
+            
+            
+              ARRM
+              Autoreload match
+              1
+              1
+            
+            
+              CMPM
+              Compare match
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt Clear Register
+          0x4
+          0x20
+          write-only
+          0x00000000
+          
+            
+              DOWNCF
+              Direction change to down Clear
+              Flag
+              6
+              1
+            
+            
+              UPCF
+              Direction change to UP Clear
+              Flag
+              5
+              1
+            
+            
+              ARROKCF
+              Autoreload register update OK Clear
+              Flag
+              4
+              1
+            
+            
+              CMPOKCF
+              Compare register update OK Clear
+              Flag
+              3
+              1
+            
+            
+              EXTTRIGCF
+              External trigger valid edge Clear
+              Flag
+              2
+              1
+            
+            
+              ARRMCF
+              Autoreload match Clear
+              Flag
+              1
+              1
+            
+            
+              CMPMCF
+              compare match Clear Flag
+              0
+              1
+            
+          
+        
+        
+          IER
+          IER
+          Interrupt Enable Register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DOWNIE
+              Direction change to down Interrupt
+              Enable
+              6
+              1
+            
+            
+              UPIE
+              Direction change to UP Interrupt
+              Enable
+              5
+              1
+            
+            
+              ARROKIE
+              Autoreload register update OK Interrupt
+              Enable
+              4
+              1
+            
+            
+              CMPOKIE
+              Compare register update OK Interrupt
+              Enable
+              3
+              1
+            
+            
+              EXTTRIGIE
+              External trigger valid edge Interrupt
+              Enable
+              2
+              1
+            
+            
+              ARRMIE
+              Autoreload match Interrupt
+              Enable
+              1
+              1
+            
+            
+              CMPMIE
+              Compare match Interrupt
+              Enable
+              0
+              1
+            
+          
+        
+        
+          CFGR
+          CFGR
+          Configuration Register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ENC
+              Encoder mode enable
+              24
+              1
+            
+            
+              COUNTMODE
+              counter mode enabled
+              23
+              1
+            
+            
+              PRELOAD
+              Registers update mode
+              22
+              1
+            
+            
+              WAVPOL
+              Waveform shape polarity
+              21
+              1
+            
+            
+              WAVE
+              Waveform shape
+              20
+              1
+            
+            
+              TIMOUT
+              Timeout enable
+              19
+              1
+            
+            
+              TRIGEN
+              Trigger enable and
+              polarity
+              17
+              2
+            
+            
+              TRIGSEL
+              Trigger selector
+              13
+              3
+            
+            
+              PRESC
+              Clock prescaler
+              9
+              3
+            
+            
+              TRGFLT
+              Configurable digital filter for
+              trigger
+              6
+              2
+            
+            
+              CKFLT
+              Configurable digital filter for external
+              clock
+              3
+              2
+            
+            
+              CKPOL
+              Clock Polarity
+              1
+              2
+            
+            
+              CKSEL
+              Clock selector
+              0
+              1
+            
+          
+        
+        
+          CR
+          CR
+          Control Register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNTSTRT
+              Timer start in continuous
+              mode
+              2
+              1
+            
+            
+              SNGSTRT
+              LPTIM start in single mode
+              1
+              1
+            
+            
+              ENABLE
+              LPTIM Enable
+              0
+              1
+            
+          
+        
+        
+          CMP
+          CMP
+          Compare Register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CMP
+              Compare value.
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          Autoreload Register
+          0x18
+          0x20
+          read-write
+          0x00000001
+          
+            
+              ARR
+              Auto reload value.
+              0
+              16
+            
+          
+        
+        
+          CNT
+          CNT
+          Counter Register
+          0x1C
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value.
+              0
+              16
+            
+          
+        
+      
+    
+    
+      RNG
+      Random number generator
+      RNG
+      0x40025000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IE
+              Interrupt enable
+              3
+              1
+            
+            
+              RNGEN
+              Random number generator
+              enable
+              2
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x4
+          0x20
+          0x00000000
+          
+            
+              SEIS
+              Seed error interrupt
+              status
+              6
+              1
+              read-write
+            
+            
+              CEIS
+              Clock error interrupt
+              status
+              5
+              1
+              read-write
+            
+            
+              SECS
+              Seed error current status
+              2
+              1
+              read-only
+            
+            
+              CECS
+              Clock error current status
+              1
+              1
+              read-only
+            
+            
+              DRDY
+              Data ready
+              0
+              1
+              read-only
+            
+          
+        
+        
+          DR
+          DR
+          data register
+          0x8
+          0x20
+          read-only
+          0x00000000
+          
+            
+              RNDATA
+              Random data
+              0
+              32
+            
+          
+        
+      
+    
+    
+      RTC
+      Real-time clock
+      RTC
+      0x40002800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        RTC
+        RTC global interrupt
+        2
+      
+      
+        
+          TR
+          TR
+          RTC time register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format
+              16
+              4
+            
+            
+              MNT
+              Minute tens in BCD format
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD format
+              8
+              4
+            
+            
+              ST
+              Second tens in BCD format
+              4
+              3
+            
+            
+              SU
+              Second units in BCD format
+              0
+              4
+            
+          
+        
+        
+          DR
+          DR
+          RTC date register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              YT
+              Year tens in BCD format
+              20
+              4
+            
+            
+              YU
+              Year units in BCD format
+              16
+              4
+            
+            
+              WDU
+              Week day units
+              13
+              3
+            
+            
+              MT
+              Month tens in BCD format
+              12
+              1
+            
+            
+              MU
+              Month units in BCD format
+              8
+              4
+            
+            
+              DT
+              Date tens in BCD format
+              4
+              2
+            
+            
+              DU
+              Date units in BCD format
+              0
+              4
+            
+          
+        
+        
+          CR
+          CR
+          RTC control register
+          0x8
+          0x20
+          0x00000000
+          
+            
+              COE
+              Calibration output enable
+              23
+              1
+              read-write
+            
+            
+              OSEL
+              Output selection
+              21
+              2
+              read-write
+            
+            
+              POL
+              Output polarity
+              20
+              1
+              read-write
+            
+            
+              COSEL
+              Calibration output
+              selection
+              19
+              1
+              read-write
+            
+            
+              BKP
+              Backup
+              18
+              1
+              read-write
+            
+            
+              SUB1H
+              Subtract 1 hour (winter time
+              change)
+              17
+              1
+              write-only
+            
+            
+              ADD1H
+              Add 1 hour (summer time
+              change)
+              16
+              1
+              write-only
+            
+            
+              TSIE
+              Time-stamp interrupt
+              enable
+              15
+              1
+              read-write
+            
+            
+              WUTIE
+              Wakeup timer interrupt
+              enable
+              14
+              1
+              read-write
+            
+            
+              ALRBIE
+              Alarm B interrupt enable
+              13
+              1
+              read-write
+            
+            
+              ALRAIE
+              Alarm A interrupt enable
+              12
+              1
+              read-write
+            
+            
+              TSE
+              timestamp enable
+              11
+              1
+              read-write
+            
+            
+              WUTE
+              Wakeup timer enable
+              10
+              1
+              read-write
+            
+            
+              ALRBE
+              Alarm B enable
+              9
+              1
+              read-write
+            
+            
+              ALRAE
+              Alarm A enable
+              8
+              1
+              read-write
+            
+            
+              FMT
+              Hour format
+              6
+              1
+              read-write
+            
+            
+              BYPSHAD
+              Bypass the shadow
+              registers
+              5
+              1
+              read-write
+            
+            
+              REFCKON
+              RTC_REFIN reference clock detection
+              enable (50 or 60 Hz)
+              4
+              1
+              read-write
+            
+            
+              TSEDGE
+              Time-stamp event active
+              edge
+              3
+              1
+              read-write
+            
+            
+              WUCKSEL
+              Wakeup clock selection
+              0
+              3
+              read-write
+            
+          
+        
+        
+          ISR
+          ISR
+          RTC initialization and status
+          register
+          0xC
+          0x20
+          0x00000000
+          
+            
+              TAMP2F
+              RTC_TAMP2 detection flag
+              14
+              1
+              read-write
+            
+            
+              TAMP1F
+              RTC_TAMP1 detection flag
+              13
+              1
+              read-write
+            
+            
+              TSOVF
+              Time-stamp overflow flag
+              12
+              1
+              read-write
+            
+            
+              TSF
+              Time-stamp flag
+              11
+              1
+              read-write
+            
+            
+              WUTF
+              Wakeup timer flag
+              10
+              1
+              read-write
+            
+            
+              ALRBF
+              Alarm B flag
+              9
+              1
+              read-write
+            
+            
+              ALRAF
+              Alarm A flag
+              8
+              1
+              read-write
+            
+            
+              INIT
+              Initialization mode
+              7
+              1
+              read-write
+            
+            
+              INITF
+              Initialization flag
+              6
+              1
+              read-only
+            
+            
+              RSF
+              Registers synchronization
+              flag
+              5
+              1
+              read-write
+            
+            
+              INITS
+              Initialization status flag
+              4
+              1
+              read-only
+            
+            
+              SHPF
+              Shift operation pending
+              3
+              1
+              read-only
+            
+            
+              WUTWF
+              Wakeup timer write flag
+              2
+              1
+              read-only
+            
+            
+              ALRBWF
+              Alarm B write flag
+              1
+              1
+              read-only
+            
+            
+              ALRAWF
+              Alarm A write flag
+              0
+              1
+              read-only
+            
+          
+        
+        
+          PRER
+          PRER
+          RTC prescaler register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PREDIV_A
+              Asynchronous prescaler
+              factor
+              16
+              7
+            
+            
+              PREDIV_S
+              Synchronous prescaler
+              factor
+              0
+              16
+            
+          
+        
+        
+          WUTR
+          WUTR
+          RTC wakeup timer register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              WUT
+              Wakeup auto-reload value
+              bits
+              0
+              16
+            
+          
+        
+        
+          ALRMAR
+          ALRMAR
+          RTC alarm A register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MSK4
+              Alarm A date mask
+              31
+              1
+            
+            
+              WDSEL
+              Week day selection
+              30
+              1
+            
+            
+              DT
+              Date tens in BCD format.
+              28
+              2
+            
+            
+              DU
+              Date units or day in BCD
+              format.
+              24
+              4
+            
+            
+              MSK3
+              Alarm A hours mask
+              23
+              1
+            
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format.
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format.
+              16
+              4
+            
+            
+              MSK2
+              Alarm A minutes mask
+              15
+              1
+            
+            
+              MNT
+              Minute tens in BCD format.
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD
+              format.
+              8
+              4
+            
+            
+              MSK1
+              Alarm A seconds mask
+              7
+              1
+            
+            
+              ST
+              Second tens in BCD format.
+              4
+              3
+            
+            
+              SU
+              Second units in BCD
+              format.
+              0
+              4
+            
+          
+        
+        
+          ALRMBR
+          ALRMBR
+          RTC alarm B register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MSK4
+              Alarm B date mask
+              31
+              1
+            
+            
+              WDSEL
+              Week day selection
+              30
+              1
+            
+            
+              DT
+              Date tens in BCD format
+              28
+              2
+            
+            
+              DU
+              Date units or day in BCD
+              format
+              24
+              4
+            
+            
+              MSK3
+              Alarm B hours mask
+              23
+              1
+            
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format
+              16
+              4
+            
+            
+              MSK2
+              Alarm B minutes mask
+              15
+              1
+            
+            
+              MNT
+              Minute tens in BCD format
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD format
+              8
+              4
+            
+            
+              MSK1
+              Alarm B seconds mask
+              7
+              1
+            
+            
+              ST
+              Second tens in BCD format
+              4
+              3
+            
+            
+              SU
+              Second units in BCD format
+              0
+              4
+            
+          
+        
+        
+          WPR
+          WPR
+          write protection register
+          0x24
+          0x20
+          write-only
+          0x00000000
+          
+            
+              KEY
+              Write protection key
+              0
+              8
+            
+          
+        
+        
+          SSR
+          SSR
+          RTC sub second register
+          0x28
+          0x20
+          read-only
+          0x00000000
+          
+            
+              SS
+              Sub second value
+              0
+              16
+            
+          
+        
+        
+          SHIFTR
+          SHIFTR
+          RTC shift control register
+          0x2C
+          0x20
+          write-only
+          0x00000000
+          
+            
+              ADD1S
+              Add one second
+              31
+              1
+            
+            
+              SUBFS
+              Subtract a fraction of a
+              second
+              0
+              15
+            
+          
+        
+        
+          TSTR
+          TSTR
+          RTC timestamp time register
+          0x30
+          0x20
+          read-only
+          0x00000000
+          
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format.
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format.
+              16
+              4
+            
+            
+              MNT
+              Minute tens in BCD format.
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD
+              format.
+              8
+              4
+            
+            
+              ST
+              Second tens in BCD format.
+              4
+              3
+            
+            
+              SU
+              Second units in BCD
+              format.
+              0
+              4
+            
+          
+        
+        
+          TSDR
+          TSDR
+          RTC timestamp date register
+          0x34
+          0x20
+          read-only
+          0x00000000
+          
+            
+              WDU
+              Week day units
+              13
+              3
+            
+            
+              MT
+              Month tens in BCD format
+              12
+              1
+            
+            
+              MU
+              Month units in BCD format
+              8
+              4
+            
+            
+              DT
+              Date tens in BCD format
+              4
+              2
+            
+            
+              DU
+              Date units in BCD format
+              0
+              4
+            
+          
+        
+        
+          TSSSR
+          TSSSR
+          RTC time-stamp sub second
+          register
+          0x38
+          0x20
+          read-only
+          0x00000000
+          
+            
+              SS
+              Sub second value
+              0
+              16
+            
+          
+        
+        
+          CALR
+          CALR
+          RTC calibration register
+          0x3C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CALP
+              Increase frequency of RTC by 488.5
+              ppm
+              15
+              1
+            
+            
+              CALW8
+              Use a 8-second calibration cycle
+              period
+              14
+              1
+            
+            
+              CALW16
+              Use a 16-second calibration cycle
+              period
+              13
+              1
+            
+            
+              CALM
+              Calibration minus
+              0
+              9
+            
+          
+        
+        
+          TAMPCR
+          TAMPCR
+          RTC tamper configuration
+          register
+          0x40
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TAMP2MF
+              Tamper 2 mask flag
+              21
+              1
+            
+            
+              TAMP2NOERASE
+              Tamper 2 no erase
+              20
+              1
+            
+            
+              TAMP2IE
+              Tamper 2 interrupt enable
+              19
+              1
+            
+            
+              TAMP1MF
+              Tamper 1 mask flag
+              18
+              1
+            
+            
+              TAMP1NOERASE
+              Tamper 1 no erase
+              17
+              1
+            
+            
+              TAMP1IE
+              Tamper 1 interrupt enable
+              16
+              1
+            
+            
+              TAMPPUDIS
+              RTC_TAMPx pull-up disable
+              15
+              1
+            
+            
+              TAMPPRCH
+              RTC_TAMPx precharge
+              duration
+              13
+              2
+            
+            
+              TAMPFLT
+              RTC_TAMPx filter count
+              11
+              2
+            
+            
+              TAMPFREQ
+              Tamper sampling frequency
+              8
+              3
+            
+            
+              TAMPTS
+              Activate timestamp on tamper detection
+              event
+              7
+              1
+            
+            
+              TAMP2_TRG
+              Active level for RTC_TAMP2
+              input
+              4
+              1
+            
+            
+              TAMP2E
+              RTC_TAMP2 input detection
+              enable
+              3
+              1
+            
+            
+              TAMPIE
+              Tamper interrupt enable
+              2
+              1
+            
+            
+              TAMP1TRG
+              Active level for RTC_TAMP1
+              input
+              1
+              1
+            
+            
+              TAMP1E
+              RTC_TAMP1 input detection
+              enable
+              0
+              1
+            
+          
+        
+        
+          ALRMASSR
+          ALRMASSR
+          RTC alarm A sub second
+          register
+          0x44
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MASKSS
+              Mask the most-significant bits starting
+              at this bit
+              24
+              4
+            
+            
+              SS
+              Sub seconds value
+              0
+              15
+            
+          
+        
+        
+          ALRMBSSR
+          ALRMBSSR
+          RTC alarm B sub second
+          register
+          0x48
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MASKSS
+              Mask the most-significant bits starting
+              at this bit
+              24
+              4
+            
+            
+              SS
+              Sub seconds value
+              0
+              15
+            
+          
+        
+        
+          OR
+          OR
+          option register
+          0x4C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              RTC_OUT_RMP
+              RTC_ALARM on PC13 output
+              type
+              1
+              1
+            
+            
+              RTC_ALARM_TYPE
+              RTC_ALARM on PC13 output
+              type
+              0
+              1
+            
+          
+        
+        
+          BKP0R
+          BKP0R
+          RTC backup registers
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP1R
+          BKP1R
+          RTC backup registers
+          0x54
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP2R
+          BKP2R
+          RTC backup registers
+          0x58
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP3R
+          BKP3R
+          RTC backup registers
+          0x5C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP4R
+          BKP4R
+          RTC backup registers
+          0x60
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+      
+    
+    
+      USART1
+      Universal synchronous asynchronous receiver
+      transmitter
+      USART
+      0x40013800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR1
+          CR1
+          Control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              M1
+              Word length
+              28
+              1
+            
+            
+              EOBIE
+              End of Block interrupt
+              enable
+              27
+              1
+            
+            
+              RTOIE
+              Receiver timeout interrupt
+              enable
+              26
+              1
+            
+            
+              DEAT4
+              Driver Enable assertion
+              time
+              25
+              1
+            
+            
+              DEAT3
+              DEAT3
+              24
+              1
+            
+            
+              DEAT2
+              DEAT2
+              23
+              1
+            
+            
+              DEAT1
+              DEAT1
+              22
+              1
+            
+            
+              DEAT0
+              DEAT0
+              21
+              1
+            
+            
+              DEDT4
+              Driver Enable de-assertion
+              time
+              20
+              1
+            
+            
+              DEDT3
+              DEDT3
+              19
+              1
+            
+            
+              DEDT2
+              DEDT2
+              18
+              1
+            
+            
+              DEDT1
+              DEDT1
+              17
+              1
+            
+            
+              DEDT0
+              DEDT0
+              16
+              1
+            
+            
+              OVER8
+              Oversampling mode
+              15
+              1
+            
+            
+              CMIE
+              Character match interrupt
+              enable
+              14
+              1
+            
+            
+              MME
+              Mute mode enable
+              13
+              1
+            
+            
+              M0
+              Word length
+              12
+              1
+            
+            
+              WAKE
+              Receiver wakeup method
+              11
+              1
+            
+            
+              PCE
+              Parity control enable
+              10
+              1
+            
+            
+              PS
+              Parity selection
+              9
+              1
+            
+            
+              PEIE
+              PE interrupt enable
+              8
+              1
+            
+            
+              TXEIE
+              interrupt enable
+              7
+              1
+            
+            
+              TCIE
+              Transmission complete interrupt
+              enable
+              6
+              1
+            
+            
+              RXNEIE
+              RXNE interrupt enable
+              5
+              1
+            
+            
+              IDLEIE
+              IDLE interrupt enable
+              4
+              1
+            
+            
+              TE
+              Transmitter enable
+              3
+              1
+            
+            
+              RE
+              Receiver enable
+              2
+              1
+            
+            
+              UESM
+              USART enable in Stop mode
+              1
+              1
+            
+            
+              UE
+              USART enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          Control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              ADD4_7
+              Address of the USART node
+              28
+              4
+            
+            
+              ADD0_3
+              Address of the USART node
+              24
+              4
+            
+            
+              RTOEN
+              Receiver timeout enable
+              23
+              1
+            
+            
+              ABRMOD1
+              Auto baud rate mode
+              22
+              1
+            
+            
+              ABRMOD0
+              ABRMOD0
+              21
+              1
+            
+            
+              ABREN
+              Auto baud rate enable
+              20
+              1
+            
+            
+              MSBFIRST
+              Most significant bit first
+              19
+              1
+            
+            
+              TAINV
+              Binary data inversion
+              18
+              1
+            
+            
+              TXINV
+              TX pin active level
+              inversion
+              17
+              1
+            
+            
+              RXINV
+              RX pin active level
+              inversion
+              16
+              1
+            
+            
+              SWAP
+              Swap TX/RX pins
+              15
+              1
+            
+            
+              LINEN
+              LIN mode enable
+              14
+              1
+            
+            
+              STOP
+              STOP bits
+              12
+              2
+            
+            
+              CLKEN
+              Clock enable
+              11
+              1
+            
+            
+              CPOL
+              Clock polarity
+              10
+              1
+            
+            
+              CPHA
+              Clock phase
+              9
+              1
+            
+            
+              LBCL
+              Last bit clock pulse
+              8
+              1
+            
+            
+              LBDIE
+              LIN break detection interrupt
+              enable
+              6
+              1
+            
+            
+              LBDL
+              LIN break detection length
+              5
+              1
+            
+            
+              ADDM7
+              7-bit Address Detection/4-bit Address
+              Detection
+              4
+              1
+            
+          
+        
+        
+          CR3
+          CR3
+          Control register 3
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              WUFIE
+              Wakeup from Stop mode interrupt
+              enable
+              22
+              1
+            
+            
+              WUS
+              Wakeup from Stop mode interrupt flag
+              selection
+              20
+              2
+            
+            
+              SCARCNT
+              Smartcard auto-retry count
+              17
+              3
+            
+            
+              DEP
+              Driver enable polarity
+              selection
+              15
+              1
+            
+            
+              DEM
+              Driver enable mode
+              14
+              1
+            
+            
+              DDRE
+              DMA Disable on Reception
+              Error
+              13
+              1
+            
+            
+              OVRDIS
+              Overrun Disable
+              12
+              1
+            
+            
+              ONEBIT
+              One sample bit method
+              enable
+              11
+              1
+            
+            
+              CTSIE
+              CTS interrupt enable
+              10
+              1
+            
+            
+              CTSE
+              CTS enable
+              9
+              1
+            
+            
+              RTSE
+              RTS enable
+              8
+              1
+            
+            
+              DMAT
+              DMA enable transmitter
+              7
+              1
+            
+            
+              DMAR
+              DMA enable receiver
+              6
+              1
+            
+            
+              SCEN
+              Smartcard mode enable
+              5
+              1
+            
+            
+              NACK
+              Smartcard NACK enable
+              4
+              1
+            
+            
+              HDSEL
+              Half-duplex selection
+              3
+              1
+            
+            
+              IRLP
+              Ir low-power
+              2
+              1
+            
+            
+              IREN
+              Ir mode enable
+              1
+              1
+            
+            
+              EIE
+              Error interrupt enable
+              0
+              1
+            
+          
+        
+        
+          BRR
+          BRR
+          Baud rate register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              DIV_Mantissa
+              DIV_Mantissa
+              4
+              12
+            
+            
+              DIV_Fraction
+              DIV_Fraction
+              0
+              4
+            
+          
+        
+        
+          GTPR
+          GTPR
+          Guard time and prescaler
+          register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              GT
+              Guard time value
+              8
+              8
+            
+            
+              PSC
+              Prescaler value
+              0
+              8
+            
+          
+        
+        
+          RTOR
+          RTOR
+          Receiver timeout register
+          0x14
+          0x20
+          read-write
+          0x0000
+          
+            
+              BLEN
+              Block Length
+              24
+              8
+            
+            
+              RTO
+              Receiver timeout value
+              0
+              24
+            
+          
+        
+        
+          RQR
+          RQR
+          Request register
+          0x18
+          0x20
+          write-only
+          0x0000
+          
+            
+              TXFRQ
+              Transmit data flush
+              request
+              4
+              1
+            
+            
+              RXFRQ
+              Receive data flush request
+              3
+              1
+            
+            
+              MMRQ
+              Mute mode request
+              2
+              1
+            
+            
+              SBKRQ
+              Send break request
+              1
+              1
+            
+            
+              ABRRQ
+              Auto baud rate request
+              0
+              1
+            
+          
+        
+        
+          ISR
+          ISR
+          Interrupt & status
+          register
+          0x1C
+          0x20
+          read-only
+          0x00C0
+          
+            
+              REACK
+              REACK
+              22
+              1
+            
+            
+              TEACK
+              TEACK
+              21
+              1
+            
+            
+              WUF
+              WUF
+              20
+              1
+            
+            
+              RWU
+              RWU
+              19
+              1
+            
+            
+              SBKF
+              SBKF
+              18
+              1
+            
+            
+              CMF
+              CMF
+              17
+              1
+            
+            
+              BUSY
+              BUSY
+              16
+              1
+            
+            
+              ABRF
+              ABRF
+              15
+              1
+            
+            
+              ABRE
+              ABRE
+              14
+              1
+            
+            
+              EOBF
+              EOBF
+              12
+              1
+            
+            
+              RTOF
+              RTOF
+              11
+              1
+            
+            
+              CTS
+              CTS
+              10
+              1
+            
+            
+              CTSIF
+              CTSIF
+              9
+              1
+            
+            
+              LBDF
+              LBDF
+              8
+              1
+            
+            
+              TXE
+              TXE
+              7
+              1
+            
+            
+              TC
+              TC
+              6
+              1
+            
+            
+              RXNE
+              RXNE
+              5
+              1
+            
+            
+              IDLE
+              IDLE
+              4
+              1
+            
+            
+              ORE
+              ORE
+              3
+              1
+            
+            
+              NF
+              NF
+              2
+              1
+            
+            
+              FE
+              FE
+              1
+              1
+            
+            
+              PE
+              PE
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt flag clear register
+          0x20
+          0x20
+          write-only
+          0x0000
+          
+            
+              WUCF
+              Wakeup from Stop mode clear
+              flag
+              20
+              1
+            
+            
+              CMCF
+              Character match clear flag
+              17
+              1
+            
+            
+              EOBCF
+              End of block clear flag
+              12
+              1
+            
+            
+              RTOCF
+              Receiver timeout clear
+              flag
+              11
+              1
+            
+            
+              CTSCF
+              CTS clear flag
+              9
+              1
+            
+            
+              LBDCF
+              LIN break detection clear
+              flag
+              8
+              1
+            
+            
+              TCCF
+              Transmission complete clear
+              flag
+              6
+              1
+            
+            
+              IDLECF
+              Idle line detected clear
+              flag
+              4
+              1
+            
+            
+              ORECF
+              Overrun error clear flag
+              3
+              1
+            
+            
+              NCF
+              Noise detected clear flag
+              2
+              1
+            
+            
+              FECF
+              Framing error clear flag
+              1
+              1
+            
+            
+              PECF
+              Parity error clear flag
+              0
+              1
+            
+          
+        
+        
+          RDR
+          RDR
+          Receive data register
+          0x24
+          0x20
+          read-only
+          0x0000
+          
+            
+              RDR
+              Receive data value
+              0
+              9
+            
+          
+        
+        
+          TDR
+          TDR
+          Transmit data register
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              TDR
+              Transmit data value
+              0
+              9
+            
+          
+        
+      
+    
+    
+      USART2
+      0x40004400
+    
+    
+      USART4
+      0x40004C00
+      
+        USART4_USART5
+        USART4/USART5 global interrupt
+        14
+      
+      
+        USART1
+        USART1 global interrupt
+        27
+      
+    
+    
+      USART5
+      0x40005000
+      
+        USART2
+        USART2 global interrupt
+        28
+      
+    
+    
+      TSC
+      Touch sensing controller
+      TSC
+      0x40024000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TSC
+        Touch sensing interrupt
+        8
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CTPH
+              Charge transfer pulse high
+              28
+              4
+            
+            
+              CTPL
+              Charge transfer pulse low
+              24
+              4
+            
+            
+              SSD
+              Spread spectrum deviation
+              17
+              7
+            
+            
+              SSE
+              Spread spectrum enable
+              16
+              1
+            
+            
+              SSPSC
+              Spread spectrum prescaler
+              15
+              1
+            
+            
+              PGPSC
+              pulse generator prescaler
+              12
+              3
+            
+            
+              MCV
+              Max count value
+              5
+              3
+            
+            
+              IODEF
+              I/O Default mode
+              4
+              1
+            
+            
+              SYNCPOL
+              Synchronization pin
+              polarity
+              3
+              1
+            
+            
+              AM
+              Acquisition mode
+              2
+              1
+            
+            
+              START
+              Start a new acquisition
+              1
+              1
+            
+            
+              TSCE
+              Touch sensing controller
+              enable
+              0
+              1
+            
+          
+        
+        
+          IER
+          IER
+          interrupt enable register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MCEIE
+              Max count error interrupt
+              enable
+              1
+              1
+            
+            
+              EOAIE
+              End of acquisition interrupt
+              enable
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          interrupt clear register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MCEIC
+              Max count error interrupt
+              clear
+              1
+              1
+            
+            
+              EOAIC
+              End of acquisition interrupt
+              clear
+              0
+              1
+            
+          
+        
+        
+          ISR
+          ISR
+          interrupt status register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MCEF
+              Max count error flag
+              1
+              1
+            
+            
+              EOAF
+              End of acquisition flag
+              0
+              1
+            
+          
+        
+        
+          IOHCR
+          IOHCR
+          I/O hysteresis control
+          register
+          0x10
+          0x20
+          read-write
+          0xFFFFFFFF
+          
+            
+              G8_IO4
+              G8_IO4
+              31
+              1
+            
+            
+              G8_IO3
+              G8_IO3
+              30
+              1
+            
+            
+              G8_IO2
+              G8_IO2
+              29
+              1
+            
+            
+              G8_IO1
+              G8_IO1
+              28
+              1
+            
+            
+              G7_IO4
+              G7_IO4
+              27
+              1
+            
+            
+              G7_IO3
+              G7_IO3
+              26
+              1
+            
+            
+              G7_IO2
+              G7_IO2
+              25
+              1
+            
+            
+              G7_IO1
+              G7_IO1
+              24
+              1
+            
+            
+              G6_IO4
+              G6_IO4
+              23
+              1
+            
+            
+              G6_IO3
+              G6_IO3
+              22
+              1
+            
+            
+              G6_IO2
+              G6_IO2
+              21
+              1
+            
+            
+              G6_IO1
+              G6_IO1
+              20
+              1
+            
+            
+              G5_IO4
+              G5_IO4
+              19
+              1
+            
+            
+              G5_IO3
+              G5_IO3
+              18
+              1
+            
+            
+              G5_IO2
+              G5_IO2
+              17
+              1
+            
+            
+              G5_IO1
+              G5_IO1
+              16
+              1
+            
+            
+              G4_IO4
+              G4_IO4
+              15
+              1
+            
+            
+              G4_IO3
+              G4_IO3
+              14
+              1
+            
+            
+              G4_IO2
+              G4_IO2
+              13
+              1
+            
+            
+              G4_IO1
+              G4_IO1
+              12
+              1
+            
+            
+              G3_IO4
+              G3_IO4
+              11
+              1
+            
+            
+              G3_IO3
+              G3_IO3
+              10
+              1
+            
+            
+              G3_IO2
+              G3_IO2
+              9
+              1
+            
+            
+              G3_IO1
+              G3_IO1
+              8
+              1
+            
+            
+              G2_IO4
+              G2_IO4
+              7
+              1
+            
+            
+              G2_IO3
+              G2_IO3
+              6
+              1
+            
+            
+              G2_IO2
+              G2_IO2
+              5
+              1
+            
+            
+              G2_IO1
+              G2_IO1
+              4
+              1
+            
+            
+              G1_IO4
+              G1_IO4
+              3
+              1
+            
+            
+              G1_IO3
+              G1_IO3
+              2
+              1
+            
+            
+              G1_IO2
+              G1_IO2
+              1
+              1
+            
+            
+              G1_IO1
+              G1_IO1
+              0
+              1
+            
+          
+        
+        
+          IOASCR
+          IOASCR
+          I/O analog switch control
+          register
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              G8_IO4
+              G8_IO4
+              31
+              1
+            
+            
+              G8_IO3
+              G8_IO3
+              30
+              1
+            
+            
+              G8_IO2
+              G8_IO2
+              29
+              1
+            
+            
+              G8_IO1
+              G8_IO1
+              28
+              1
+            
+            
+              G7_IO4
+              G7_IO4
+              27
+              1
+            
+            
+              G7_IO3
+              G7_IO3
+              26
+              1
+            
+            
+              G7_IO2
+              G7_IO2
+              25
+              1
+            
+            
+              G7_IO1
+              G7_IO1
+              24
+              1
+            
+            
+              G6_IO4
+              G6_IO4
+              23
+              1
+            
+            
+              G6_IO3
+              G6_IO3
+              22
+              1
+            
+            
+              G6_IO2
+              G6_IO2
+              21
+              1
+            
+            
+              G6_IO1
+              G6_IO1
+              20
+              1
+            
+            
+              G5_IO4
+              G5_IO4
+              19
+              1
+            
+            
+              G5_IO3
+              G5_IO3
+              18
+              1
+            
+            
+              G5_IO2
+              G5_IO2
+              17
+              1
+            
+            
+              G5_IO1
+              G5_IO1
+              16
+              1
+            
+            
+              G4_IO4
+              G4_IO4
+              15
+              1
+            
+            
+              G4_IO3
+              G4_IO3
+              14
+              1
+            
+            
+              G4_IO2
+              G4_IO2
+              13
+              1
+            
+            
+              G4_IO1
+              G4_IO1
+              12
+              1
+            
+            
+              G3_IO4
+              G3_IO4
+              11
+              1
+            
+            
+              G3_IO3
+              G3_IO3
+              10
+              1
+            
+            
+              G3_IO2
+              G3_IO2
+              9
+              1
+            
+            
+              G3_IO1
+              G3_IO1
+              8
+              1
+            
+            
+              G2_IO4
+              G2_IO4
+              7
+              1
+            
+            
+              G2_IO3
+              G2_IO3
+              6
+              1
+            
+            
+              G2_IO2
+              G2_IO2
+              5
+              1
+            
+            
+              G2_IO1
+              G2_IO1
+              4
+              1
+            
+            
+              G1_IO4
+              G1_IO4
+              3
+              1
+            
+            
+              G1_IO3
+              G1_IO3
+              2
+              1
+            
+            
+              G1_IO2
+              G1_IO2
+              1
+              1
+            
+            
+              G1_IO1
+              G1_IO1
+              0
+              1
+            
+          
+        
+        
+          IOSCR
+          IOSCR
+          I/O sampling control register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              G8_IO4
+              G8_IO4
+              31
+              1
+            
+            
+              G8_IO3
+              G8_IO3
+              30
+              1
+            
+            
+              G8_IO2
+              G8_IO2
+              29
+              1
+            
+            
+              G8_IO1
+              G8_IO1
+              28
+              1
+            
+            
+              G7_IO4
+              G7_IO4
+              27
+              1
+            
+            
+              G7_IO3
+              G7_IO3
+              26
+              1
+            
+            
+              G7_IO2
+              G7_IO2
+              25
+              1
+            
+            
+              G7_IO1
+              G7_IO1
+              24
+              1
+            
+            
+              G6_IO4
+              G6_IO4
+              23
+              1
+            
+            
+              G6_IO3
+              G6_IO3
+              22
+              1
+            
+            
+              G6_IO2
+              G6_IO2
+              21
+              1
+            
+            
+              G6_IO1
+              G6_IO1
+              20
+              1
+            
+            
+              G5_IO4
+              G5_IO4
+              19
+              1
+            
+            
+              G5_IO3
+              G5_IO3
+              18
+              1
+            
+            
+              G5_IO2
+              G5_IO2
+              17
+              1
+            
+            
+              G5_IO1
+              G5_IO1
+              16
+              1
+            
+            
+              G4_IO4
+              G4_IO4
+              15
+              1
+            
+            
+              G4_IO3
+              G4_IO3
+              14
+              1
+            
+            
+              G4_IO2
+              G4_IO2
+              13
+              1
+            
+            
+              G4_IO1
+              G4_IO1
+              12
+              1
+            
+            
+              G3_IO4
+              G3_IO4
+              11
+              1
+            
+            
+              G3_IO3
+              G3_IO3
+              10
+              1
+            
+            
+              G3_IO2
+              G3_IO2
+              9
+              1
+            
+            
+              G3_IO1
+              G3_IO1
+              8
+              1
+            
+            
+              G2_IO4
+              G2_IO4
+              7
+              1
+            
+            
+              G2_IO3
+              G2_IO3
+              6
+              1
+            
+            
+              G2_IO2
+              G2_IO2
+              5
+              1
+            
+            
+              G2_IO1
+              G2_IO1
+              4
+              1
+            
+            
+              G1_IO4
+              G1_IO4
+              3
+              1
+            
+            
+              G1_IO3
+              G1_IO3
+              2
+              1
+            
+            
+              G1_IO2
+              G1_IO2
+              1
+              1
+            
+            
+              G1_IO1
+              G1_IO1
+              0
+              1
+            
+          
+        
+        
+          IOCCR
+          IOCCR
+          I/O channel control register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              G8_IO4
+              G8_IO4
+              31
+              1
+            
+            
+              G8_IO3
+              G8_IO3
+              30
+              1
+            
+            
+              G8_IO2
+              G8_IO2
+              29
+              1
+            
+            
+              G8_IO1
+              G8_IO1
+              28
+              1
+            
+            
+              G7_IO4
+              G7_IO4
+              27
+              1
+            
+            
+              G7_IO3
+              G7_IO3
+              26
+              1
+            
+            
+              G7_IO2
+              G7_IO2
+              25
+              1
+            
+            
+              G7_IO1
+              G7_IO1
+              24
+              1
+            
+            
+              G6_IO4
+              G6_IO4
+              23
+              1
+            
+            
+              G6_IO3
+              G6_IO3
+              22
+              1
+            
+            
+              G6_IO2
+              G6_IO2
+              21
+              1
+            
+            
+              G6_IO1
+              G6_IO1
+              20
+              1
+            
+            
+              G5_IO4
+              G5_IO4
+              19
+              1
+            
+            
+              G5_IO3
+              G5_IO3
+              18
+              1
+            
+            
+              G5_IO2
+              G5_IO2
+              17
+              1
+            
+            
+              G5_IO1
+              G5_IO1
+              16
+              1
+            
+            
+              G4_IO4
+              G4_IO4
+              15
+              1
+            
+            
+              G4_IO3
+              G4_IO3
+              14
+              1
+            
+            
+              G4_IO2
+              G4_IO2
+              13
+              1
+            
+            
+              G4_IO1
+              G4_IO1
+              12
+              1
+            
+            
+              G3_IO4
+              G3_IO4
+              11
+              1
+            
+            
+              G3_IO3
+              G3_IO3
+              10
+              1
+            
+            
+              G3_IO2
+              G3_IO2
+              9
+              1
+            
+            
+              G3_IO1
+              G3_IO1
+              8
+              1
+            
+            
+              G2_IO4
+              G2_IO4
+              7
+              1
+            
+            
+              G2_IO3
+              G2_IO3
+              6
+              1
+            
+            
+              G2_IO2
+              G2_IO2
+              5
+              1
+            
+            
+              G2_IO1
+              G2_IO1
+              4
+              1
+            
+            
+              G1_IO4
+              G1_IO4
+              3
+              1
+            
+            
+              G1_IO3
+              G1_IO3
+              2
+              1
+            
+            
+              G1_IO2
+              G1_IO2
+              1
+              1
+            
+            
+              G1_IO1
+              G1_IO1
+              0
+              1
+            
+          
+        
+        
+          IOGCSR
+          IOGCSR
+          I/O group control status
+          register
+          0x30
+          0x20
+          0x00000000
+          
+            
+              G8S
+              Analog I/O group x status
+              23
+              1
+              read-only
+            
+            
+              G7S
+              Analog I/O group x status
+              22
+              1
+              read-only
+            
+            
+              G6S
+              Analog I/O group x status
+              21
+              1
+              read-only
+            
+            
+              G5S
+              Analog I/O group x status
+              20
+              1
+              read-only
+            
+            
+              G4S
+              Analog I/O group x status
+              19
+              1
+              read-only
+            
+            
+              G3S
+              Analog I/O group x status
+              18
+              1
+              read-only
+            
+            
+              G2S
+              Analog I/O group x status
+              17
+              1
+              read-only
+            
+            
+              G1S
+              Analog I/O group x status
+              16
+              1
+              read-only
+            
+            
+              G8E
+              Analog I/O group x enable
+              7
+              1
+              read-write
+            
+            
+              G7E
+              Analog I/O group x enable
+              6
+              1
+              read-write
+            
+            
+              G6E
+              Analog I/O group x enable
+              5
+              1
+              read-write
+            
+            
+              G5E
+              Analog I/O group x enable
+              4
+              1
+              read-write
+            
+            
+              G4E
+              Analog I/O group x enable
+              3
+              1
+              read-write
+            
+            
+              G3E
+              Analog I/O group x enable
+              2
+              1
+              read-write
+            
+            
+              G2E
+              Analog I/O group x enable
+              1
+              1
+              read-write
+            
+            
+              G1E
+              Analog I/O group x enable
+              0
+              1
+              read-write
+            
+          
+        
+        
+          IOG1CR
+          IOG1CR
+          I/O group x counter register
+          0x34
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG2CR
+          IOG2CR
+          I/O group x counter register
+          0x38
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG3CR
+          IOG3CR
+          I/O group x counter register
+          0x3C
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG4CR
+          IOG4CR
+          I/O group x counter register
+          0x40
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG5CR
+          IOG5CR
+          I/O group x counter register
+          0x44
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG6CR
+          IOG6CR
+          I/O group x counter register
+          0x48
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG7CR
+          IOG7CR
+          I/O group x counter register
+          0x4C
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG8CR
+          IOG8CR
+          I/O group x counter register
+          0x50
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+      
+    
+    
+      IWDG
+      Independent watchdog
+      IWDG
+      0x40003000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          KR
+          KR
+          Key register
+          0x0
+          0x20
+          write-only
+          0x00000000
+          
+            
+              KEY
+              Key value (write only, read
+              0x0000)
+              0
+              16
+            
+          
+        
+        
+          PR
+          PR
+          Prescaler register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PR
+              Prescaler divider
+              0
+              3
+            
+          
+        
+        
+          RLR
+          RLR
+          Reload register
+          0x8
+          0x20
+          read-write
+          0x00000FFF
+          
+            
+              RL
+              Watchdog counter reload
+              value
+              0
+              12
+            
+          
+        
+        
+          SR
+          SR
+          Status register
+          0xC
+          0x20
+          read-only
+          0x00000000
+          
+            
+              WVU
+              Watchdog counter window value
+              update
+              2
+              1
+            
+            
+              RVU
+              Watchdog counter reload value
+              update
+              1
+              1
+            
+            
+              PVU
+              Watchdog prescaler value
+              update
+              0
+              1
+            
+          
+        
+        
+          WINR
+          WINR
+          Window register
+          0x10
+          0x20
+          read-write
+          0x00000FFF
+          
+            
+              WIN
+              Watchdog counter window
+              value
+              0
+              12
+            
+          
+        
+      
+    
+    
+      WWDG
+      System window watchdog
+      WWDG
+      0x40002C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        WWDG
+        Window Watchdog interrupt
+        0
+      
+      
+        
+          CR
+          CR
+          Control register
+          0x0
+          0x20
+          read-write
+          0x0000007F
+          
+            
+              WDGA
+              Activation bit
+              7
+              1
+            
+            
+              T
+              7-bit counter (MSB to LSB)
+              0
+              7
+            
+          
+        
+        
+          CFR
+          CFR
+          Configuration register
+          0x4
+          0x20
+          read-write
+          0x0000007F
+          
+            
+              EWI
+              Early wakeup interrupt
+              9
+              1
+            
+            
+              WDGTB1
+              Timer base
+              8
+              1
+            
+            
+              WDGTB0
+              WDGTB0
+              7
+              1
+            
+            
+              W
+              7-bit window value
+              0
+              7
+            
+          
+        
+        
+          SR
+          SR
+          Status register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EWIF
+              Early wakeup interrupt
+              flag
+              0
+              1
+            
+          
+        
+      
+    
+    
+      USB_FS
+      Universal serial bus full-speed device
+      interface
+      USB
+      0x40005C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        USB
+        USB event interrupt through
+        EXTI18
+        31
+      
+      
+        
+          EP0R
+          EP0R
+          endpoint register
+          0x0
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP1R
+          EP1R
+          endpoint register
+          0x4
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP2R
+          EP2R
+          endpoint register
+          0x8
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP3R
+          EP3R
+          endpoint register
+          0xC
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP4R
+          EP4R
+          endpoint register
+          0x10
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP5R
+          EP5R
+          endpoint register
+          0x14
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP6R
+          EP6R
+          endpoint register
+          0x18
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP7R
+          EP7R
+          endpoint register
+          0x1C
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          CNTR
+          CNTR
+          control register
+          0x40
+          0x20
+          read-write
+          0x0
+          
+            
+              CTRM
+              CTRM
+              15
+              1
+            
+            
+              PMAOVRM
+              PMAOVRM
+              14
+              1
+            
+            
+              ERRM
+              ERRM
+              13
+              1
+            
+            
+              WKUPM
+              WKUPM
+              12
+              1
+            
+            
+              SUSPM
+              SUSPM
+              11
+              1
+            
+            
+              RESETM
+              RESETM
+              10
+              1
+            
+            
+              SOFM
+              SOFM
+              9
+              1
+            
+            
+              ESOFM
+              ESOFM
+              8
+              1
+            
+            
+              L1REQM
+              L1REQM
+              7
+              1
+            
+            
+              L1RESUME
+              L1RESUME
+              5
+              1
+            
+            
+              RESUME
+              RESUME
+              4
+              1
+            
+            
+              FSUSP
+              FSUSP
+              3
+              1
+            
+            
+              LPMODE
+              LPMODE
+              2
+              1
+            
+            
+              PDWN
+              PDWN
+              1
+              1
+            
+            
+              FRES
+              FRES
+              0
+              1
+            
+          
+        
+        
+          ISTR
+          ISTR
+          interrupt status register
+          0x44
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR
+              CTR
+              15
+              1
+            
+            
+              PMAOVR
+              PMAOVR
+              14
+              1
+            
+            
+              ERR
+              ERR
+              13
+              1
+            
+            
+              WKUP
+              WKUP
+              12
+              1
+            
+            
+              SUSP
+              SUSP
+              11
+              1
+            
+            
+              RESET
+              RESET
+              10
+              1
+            
+            
+              SOF
+              SOF
+              9
+              1
+            
+            
+              ESOF
+              ESOF
+              8
+              1
+            
+            
+              L1REQ
+              L1REQ
+              7
+              1
+            
+            
+              DIR
+              DIR
+              4
+              1
+            
+            
+              EP_ID
+              EP_ID
+              0
+              4
+            
+          
+        
+        
+          FNR
+          FNR
+          frame number register
+          0x48
+          0x20
+          read-only
+          0x0
+          
+            
+              RXDP
+              RXDP
+              15
+              1
+            
+            
+              RXDM
+              RXDM
+              14
+              1
+            
+            
+              LCK
+              LCK
+              13
+              1
+            
+            
+              LSOF
+              LSOF
+              11
+              2
+            
+            
+              FN
+              FN
+              0
+              11
+            
+          
+        
+        
+          DADDR
+          DADDR
+          device address
+          0x4C
+          0x20
+          read-write
+          0x0
+          
+            
+              EF
+              EF
+              7
+              1
+            
+            
+              ADD
+              ADD
+              0
+              7
+            
+          
+        
+        
+          BTABLE
+          BTABLE
+          Buffer table address
+          0x50
+          0x20
+          read-write
+          0x0
+          
+            
+              BTABLE
+              BTABLE
+              3
+              13
+            
+          
+        
+        
+          LPMCSR
+          LPMCSR
+          LPM control and status
+          register
+          0x54
+          0x20
+          0x0
+          
+            
+              BESL
+              BESL
+              4
+              4
+              read-only
+            
+            
+              REMWAKE
+              REMWAKE
+              3
+              1
+              read-only
+            
+            
+              LPMACK
+              LPMACK
+              1
+              1
+              read-write
+            
+            
+              LPMEN
+              LPMEN
+              0
+              1
+              read-write
+            
+          
+        
+        
+          BCDR
+          BCDR
+          Battery charging detector
+          0x58
+          0x20
+          0x0
+          
+            
+              DPPU
+              DPPU
+              15
+              1
+              read-write
+            
+            
+              PS2DET
+              PS2DET
+              7
+              1
+              read-only
+            
+            
+              SDET
+              SDET
+              6
+              1
+              read-only
+            
+            
+              PDET
+              PDET
+              5
+              1
+              read-only
+            
+            
+              DCDET
+              DCDET
+              4
+              1
+              read-only
+            
+            
+              SDEN
+              SDEN
+              3
+              1
+              read-write
+            
+            
+              PDEN
+              PDEN
+              2
+              1
+              read-write
+            
+            
+              DCDEN
+              DCDEN
+              1
+              1
+              read-write
+            
+            
+              BCDEN
+              BCDEN
+              0
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      CRS
+      Clock recovery system
+      CRS
+      0x40006C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00002000
+          
+            
+              TRIM
+              HSI48 oscillator smooth
+              trimming
+              8
+              6
+            
+            
+              SWSYNC
+              Generate software SYNC
+              event
+              7
+              1
+            
+            
+              AUTOTRIMEN
+              Automatic trimming enable
+              6
+              1
+            
+            
+              CEN
+              Frequency error counter
+              enable
+              5
+              1
+            
+            
+              ESYNCIE
+              Expected SYNC interrupt
+              enable
+              3
+              1
+            
+            
+              ERRIE
+              Synchronization or trimming error
+              interrupt enable
+              2
+              1
+            
+            
+              SYNCWARNIE
+              SYNC warning interrupt
+              enable
+              1
+              1
+            
+            
+              SYNCOKIE
+              SYNC event OK interrupt
+              enable
+              0
+              1
+            
+          
+        
+        
+          CFGR
+          CFGR
+          configuration register
+          0x4
+          0x20
+          read-write
+          0x2022BB7F
+          
+            
+              SYNCPOL
+              SYNC polarity selection
+              31
+              1
+            
+            
+              SYNCSRC
+              SYNC signal source
+              selection
+              28
+              2
+            
+            
+              SYNCDIV
+              SYNC divider
+              24
+              3
+            
+            
+              FELIM
+              Frequency error limit
+              16
+              8
+            
+            
+              RELOAD
+              Counter reload value
+              0
+              16
+            
+          
+        
+        
+          ISR
+          ISR
+          interrupt and status register
+          0x8
+          0x20
+          read-only
+          0x00000000
+          
+            
+              FECAP
+              Frequency error capture
+              16
+              16
+            
+            
+              FEDIR
+              Frequency error direction
+              15
+              1
+            
+            
+              TRIMOVF
+              Trimming overflow or
+              underflow
+              10
+              1
+            
+            
+              SYNCMISS
+              SYNC missed
+              9
+              1
+            
+            
+              SYNCERR
+              SYNC error
+              8
+              1
+            
+            
+              ESYNCF
+              Expected SYNC flag
+              3
+              1
+            
+            
+              ERRF
+              Error flag
+              2
+              1
+            
+            
+              SYNCWARNF
+              SYNC warning flag
+              1
+              1
+            
+            
+              SYNCOKF
+              SYNC event OK flag
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          interrupt flag clear register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ESYNCC
+              Expected SYNC clear flag
+              3
+              1
+            
+            
+              ERRC
+              Error clear flag
+              2
+              1
+            
+            
+              SYNCWARNC
+              SYNC warning clear flag
+              1
+              1
+            
+            
+              SYNCOKC
+              SYNC event OK clear flag
+              0
+              1
+            
+          
+        
+      
+    
+    
+      Firewall
+      Firewall
+      Firewall
+      0x40011C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          FIREWALL_CSSA
+          FIREWALL_CSSA
+          Code segment start address
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADD
+              code segment start address
+              8
+              16
+            
+          
+        
+        
+          FIREWALL_CSL
+          FIREWALL_CSL
+          Code segment length
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LENG
+              code segment length
+              8
+              14
+            
+          
+        
+        
+          FIREWALL_NVDSSA
+          FIREWALL_NVDSSA
+          Non-volatile data segment start
+          address
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADD
+              Non-volatile data segment start
+              address
+              8
+              16
+            
+          
+        
+        
+          FIREWALL_NVDSL
+          FIREWALL_NVDSL
+          Non-volatile data segment
+          length
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LENG
+              Non-volatile data segment
+              length
+              8
+              14
+            
+          
+        
+        
+          FIREWALL_VDSSA
+          FIREWALL_VDSSA
+          Volatile data segment start
+          address
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADD
+              Volatile data segment start
+              address
+              6
+              10
+            
+          
+        
+        
+          FIREWALL_VDSL
+          FIREWALL_VDSL
+          Volatile data segment length
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LENG
+              Non-volatile data segment
+              length
+              6
+              10
+            
+          
+        
+        
+          FIREWALL_CR
+          FIREWALL_CR
+          Configuration register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              VDE
+              Volatile data execution
+              2
+              1
+            
+            
+              VDS
+              Volatile data shared
+              1
+              1
+            
+            
+              FPA
+              Firewall pre alarm
+              0
+              1
+            
+          
+        
+      
+    
+    
+      RCC
+      Reset and clock control
+      RCC
+      0x40021000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        RCC
+        RCC global interrupt
+        4
+      
+      
+        
+          CR
+          CR
+          Clock control register
+          0x0
+          0x20
+          0x00000300
+          
+            
+              PLLRDY
+              PLL clock ready flag
+              25
+              1
+              read-only
+            
+            
+              PLLON
+              PLL enable bit
+              24
+              1
+              read-write
+            
+            
+              RTCPRE
+              TC/LCD prescaler
+              20
+              2
+              read-write
+            
+            
+              CSSLSEON
+              Clock security system on HSE enable
+              bit
+              19
+              1
+              read-write
+            
+            
+              HSEBYP
+              HSE clock bypass bit
+              18
+              1
+              read-write
+            
+            
+              HSERDY
+              HSE clock ready flag
+              17
+              1
+              read-only
+            
+            
+              HSEON
+              HSE clock enable bit
+              16
+              1
+              read-write
+            
+            
+              MSIRDY
+              MSI clock ready flag
+              9
+              1
+              read-only
+            
+            
+              MSION
+              MSI clock enable bit
+              8
+              1
+              read-write
+            
+            
+              HSI16DIVF
+              HSI16DIVF
+              4
+              1
+              read-only
+            
+            
+              HSI16DIVEN
+              HSI16DIVEN
+              3
+              1
+              read-write
+            
+            
+              HSI16RDYF
+              Internal high-speed clock ready
+              flag
+              2
+              1
+              read-write
+            
+            
+              HSI16KERON
+              High-speed internal clock enable bit for
+              some IP kernels
+              1
+              1
+              read-only
+            
+            
+              HSI16ON
+              16 MHz high-speed internal clock
+              enable
+              0
+              1
+              read-write
+            
+            
+              HSI16OUTEN
+              16 MHz high-speed internal clock output
+              enable
+              5
+              1
+              read-write
+            
+          
+        
+        
+          ICSCR
+          ICSCR
+          Internal clock sources calibration
+          register
+          0x4
+          0x20
+          0x0000B000
+          
+            
+              MSITRIM
+              MSI clock trimming
+              24
+              8
+              read-write
+            
+            
+              MSICAL
+              MSI clock calibration
+              16
+              8
+              read-only
+            
+            
+              MSIRANGE
+              MSI clock ranges
+              13
+              3
+              read-write
+            
+            
+              HSI16TRIM
+              High speed internal clock
+              trimming
+              8
+              5
+              read-write
+            
+            
+              HSI16CAL
+              nternal high speed clock
+              calibration
+              0
+              8
+              read-only
+            
+          
+        
+        
+          CRRCR
+          CRRCR
+          Clock recovery RC register
+          0x8
+          0x20
+          0x00000000
+          
+            
+              HSI48CAL
+              48 MHz HSI clock
+              calibration
+              8
+              8
+              read-only
+            
+            
+              HSI48RDY
+              48MHz HSI clock ready flag
+              1
+              1
+              read-only
+            
+            
+              HSI48ON
+              48MHz HSI clock enable bit
+              0
+              1
+              read-write
+            
+            
+              HSI48DIV6EN
+              48 MHz HSI clock divided by 6 output
+              enable
+              2
+              1
+              read-write
+            
+          
+        
+        
+          CFGR
+          CFGR
+          Clock configuration register
+          0xC
+          0x20
+          0x00000000
+          
+            
+              MCOPRE
+              Microcontroller clock output
+              prescaler
+              28
+              3
+              read-write
+            
+            
+              MCOSEL
+              Microcontroller clock output
+              selection
+              24
+              4
+              read-write
+            
+            
+              PLLDIV
+              PLL output division
+              22
+              2
+              read-write
+            
+            
+              PLLMUL
+              PLL multiplication factor
+              18
+              4
+              read-write
+            
+            
+              PLLSRC
+              PLL entry clock source
+              16
+              1
+              read-write
+            
+            
+              STOPWUCK
+              Wake-up from stop clock
+              selection
+              15
+              1
+              read-write
+            
+            
+              PPRE2
+              APB high-speed prescaler
+              (APB2)
+              11
+              3
+              read-write
+            
+            
+              PPRE1
+              APB low-speed prescaler
+              (APB1)
+              8
+              3
+              read-write
+            
+            
+              HPRE
+              AHB prescaler
+              4
+              4
+              read-write
+            
+            
+              SWS
+              System clock switch status
+              2
+              2
+              read-only
+            
+            
+              SW
+              System clock switch
+              0
+              2
+              read-write
+            
+          
+        
+        
+          CIER
+          CIER
+          Clock interrupt enable
+          register
+          0x10
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CSSLSE
+              LSE CSS interrupt flag
+              7
+              1
+            
+            
+              HSI48RDYIE
+              HSI48 ready interrupt flag
+              6
+              1
+            
+            
+              MSIRDYIE
+              MSI ready interrupt flag
+              5
+              1
+            
+            
+              PLLRDYIE
+              PLL ready interrupt flag
+              4
+              1
+            
+            
+              HSERDYIE
+              HSE ready interrupt flag
+              3
+              1
+            
+            
+              HSI16RDYIE
+              HSI16 ready interrupt flag
+              2
+              1
+            
+            
+              LSERDYIE
+              LSE ready interrupt flag
+              1
+              1
+            
+            
+              LSIRDYIE
+              LSI ready interrupt flag
+              0
+              1
+            
+          
+        
+        
+          CIFR
+          CIFR
+          Clock interrupt flag register
+          0x14
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CSSHSEF
+              Clock Security System Interrupt
+              flag
+              8
+              1
+            
+            
+              CSSLSEF
+              LSE Clock Security System Interrupt
+              flag
+              7
+              1
+            
+            
+              HSI48RDYF
+              HSI48 ready interrupt flag
+              6
+              1
+            
+            
+              MSIRDYF
+              MSI ready interrupt flag
+              5
+              1
+            
+            
+              PLLRDYF
+              PLL ready interrupt flag
+              4
+              1
+            
+            
+              HSERDYF
+              HSE ready interrupt flag
+              3
+              1
+            
+            
+              HSI16RDYF
+              HSI16 ready interrupt flag
+              2
+              1
+            
+            
+              LSERDYF
+              LSE ready interrupt flag
+              1
+              1
+            
+            
+              LSIRDYF
+              LSI ready interrupt flag
+              0
+              1
+            
+          
+        
+        
+          CICR
+          CICR
+          Clock interrupt clear register
+          0x18
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CSSHSEC
+              Clock Security System Interrupt
+              clear
+              8
+              1
+            
+            
+              CSSLSEC
+              LSE Clock Security System Interrupt
+              clear
+              7
+              1
+            
+            
+              HSI48RDYC
+              HSI48 ready Interrupt
+              clear
+              6
+              1
+            
+            
+              MSIRDYC
+              MSI ready Interrupt clear
+              5
+              1
+            
+            
+              PLLRDYC
+              PLL ready Interrupt clear
+              4
+              1
+            
+            
+              HSERDYC
+              HSE ready Interrupt clear
+              3
+              1
+            
+            
+              HSI16RDYC
+              HSI16 ready Interrupt
+              clear
+              2
+              1
+            
+            
+              LSERDYC
+              LSE ready Interrupt clear
+              1
+              1
+            
+            
+              LSIRDYC
+              LSI ready Interrupt clear
+              0
+              1
+            
+          
+        
+        
+          IOPRSTR
+          IOPRSTR
+          GPIO reset register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IOPHRST
+              I/O port H reset
+              7
+              1
+            
+            
+              IOPDRST
+              I/O port D reset
+              3
+              1
+            
+            
+              IOPCRST
+              I/O port A reset
+              2
+              1
+            
+            
+              IOPBRST
+              I/O port B reset
+              1
+              1
+            
+            
+              IOPARST
+              I/O port A reset
+              0
+              1
+            
+            
+              IOPERST
+              I/O port E reset
+              4
+              1
+            
+          
+        
+        
+          AHBRSTR
+          AHBRSTR
+          AHB peripheral reset register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CRYPRST
+              Crypto module reset
+              24
+              1
+            
+            
+              RNGRST
+              Random Number Generator module
+              reset
+              20
+              1
+            
+            
+              TOUCHRST
+              Touch Sensing reset
+              16
+              1
+            
+            
+              CRCRST
+              Test integration module
+              reset
+              12
+              1
+            
+            
+              MIFRST
+              Memory interface reset
+              8
+              1
+            
+            
+              DMARST
+              DMA reset
+              0
+              1
+            
+          
+        
+        
+          APB2RSTR
+          APB2RSTR
+          APB2 peripheral reset register
+          0x24
+          0x20
+          read-write
+          0x000000000
+          
+            
+              DBGRST
+              DBG reset
+              22
+              1
+            
+            
+              USART1RST
+              USART1 reset
+              14
+              1
+            
+            
+              SPI1RST
+              SPI 1 reset
+              12
+              1
+            
+            
+              ADCRST
+              ADC interface reset
+              9
+              1
+            
+            
+              TM12RST
+              TIM22 timer reset
+              5
+              1
+            
+            
+              TIM21RST
+              TIM21 timer reset
+              2
+              1
+            
+            
+              SYSCFGRST
+              System configuration controller
+              reset
+              0
+              1
+            
+          
+        
+        
+          APB1RSTR
+          APB1RSTR
+          APB1 peripheral reset register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LPTIM1RST
+              Low power timer reset
+              31
+              1
+            
+            
+              DACRST
+              DAC interface reset
+              29
+              1
+            
+            
+              PWRRST
+              Power interface reset
+              28
+              1
+            
+            
+              CRSRST
+              Clock recovery system
+              reset
+              27
+              1
+            
+            
+              USBRST
+              USB reset
+              23
+              1
+            
+            
+              I2C2RST
+              I2C2 reset
+              22
+              1
+            
+            
+              I2C1RST
+              I2C1 reset
+              21
+              1
+            
+            
+              LPUART1RST
+              LPUART1 reset
+              18
+              1
+            
+            
+              LPUART12RST
+              UART2 reset
+              17
+              1
+            
+            
+              SPI2RST
+              SPI2 reset
+              14
+              1
+            
+            
+              WWDRST
+              Window watchdog reset
+              11
+              1
+            
+            
+              TIM6RST
+              Timer 6 reset
+              4
+              1
+            
+            
+              TIM2RST
+              Timer2 reset
+              0
+              1
+            
+            
+              TIM3RST
+              Timer3 reset
+              1
+              1
+            
+            
+              TIM7RST
+              Timer 7 reset
+              5
+              1
+            
+            
+              USART4RST
+              USART4 reset
+              19
+              1
+            
+            
+              USART5RST
+              USART5 reset
+              20
+              1
+            
+            
+              I2C3RST
+              I2C3 reset
+              30
+              1
+            
+          
+        
+        
+          IOPENR
+          IOPENR
+          GPIO clock enable register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IOPHEN
+              I/O port H clock enable
+              bit
+              7
+              1
+            
+            
+              IOPDEN
+              I/O port D clock enable
+              bit
+              3
+              1
+            
+            
+              IOPCEN
+              IO port A clock enable bit
+              2
+              1
+            
+            
+              IOPBEN
+              IO port B clock enable bit
+              1
+              1
+            
+            
+              IOPAEN
+              IO port A clock enable bit
+              0
+              1
+            
+            
+              IOPEEN
+              I/O port E clock enable
+              bit
+              4
+              1
+            
+          
+        
+        
+          AHBENR
+          AHBENR
+          AHB peripheral clock enable
+          register
+          0x30
+          0x20
+          read-write
+          0x00000100
+          
+            
+              CRYPEN
+              Crypto clock enable bit
+              24
+              1
+            
+            
+              RNGEN
+              Random Number Generator clock enable
+              bit
+              20
+              1
+            
+            
+              TOUCHEN
+              Touch Sensing clock enable
+              bit
+              16
+              1
+            
+            
+              CRCEN
+              CRC clock enable bit
+              12
+              1
+            
+            
+              MIFEN
+              NVM interface clock enable
+              bit
+              8
+              1
+            
+            
+              DMAEN
+              DMA clock enable bit
+              0
+              1
+            
+          
+        
+        
+          APB2ENR
+          APB2ENR
+          APB2 peripheral clock enable
+          register
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DBGEN
+              DBG clock enable bit
+              22
+              1
+            
+            
+              USART1EN
+              USART1 clock enable bit
+              14
+              1
+            
+            
+              SPI1EN
+              SPI1 clock enable bit
+              12
+              1
+            
+            
+              ADCEN
+              ADC clock enable bit
+              9
+              1
+            
+            
+              MIFIEN
+              MiFaRe Firewall clock enable
+              bit
+              7
+              1
+            
+            
+              TIM22EN
+              TIM22 timer clock enable
+              bit
+              5
+              1
+            
+            
+              TIM21EN
+              TIM21 timer clock enable
+              bit
+              2
+              1
+            
+            
+              SYSCFGEN
+              System configuration controller clock
+              enable bit
+              0
+              1
+            
+          
+        
+        
+          APB1ENR
+          APB1ENR
+          APB1 peripheral clock enable
+          register
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LPTIM1EN
+              Low power timer clock enable
+              bit
+              31
+              1
+            
+            
+              DACEN
+              DAC interface clock enable
+              bit
+              29
+              1
+            
+            
+              PWREN
+              Power interface clock enable
+              bit
+              28
+              1
+            
+            
+              CRSEN
+              Clock recovery system clock enable
+              bit
+              27
+              1
+            
+            
+              USBEN
+              USB clock enable bit
+              23
+              1
+            
+            
+              I2C2EN
+              I2C2 clock enable bit
+              22
+              1
+            
+            
+              I2C1EN
+              I2C1 clock enable bit
+              21
+              1
+            
+            
+              LPUART1EN
+              LPUART1 clock enable bit
+              18
+              1
+            
+            
+              USART2EN
+              UART2 clock enable bit
+              17
+              1
+            
+            
+              SPI2EN
+              SPI2 clock enable bit
+              14
+              1
+            
+            
+              WWDGEN
+              Window watchdog clock enable
+              bit
+              11
+              1
+            
+            
+              TIM6EN
+              Timer 6 clock enable bit
+              4
+              1
+            
+            
+              TIM2EN
+              Timer2 clock enable bit
+              0
+              1
+            
+            
+              TIM3EN
+              Timer3 clock enable bit
+              1
+              1
+            
+            
+              TIM7EN
+              Timer 7 clock enable bit
+              5
+              1
+            
+            
+              USART4EN
+              USART4 clock enable bit
+              19
+              1
+            
+            
+              USART5EN
+              USART5 clock enable bit
+              20
+              1
+            
+            
+              I2C3EN
+              I2C3 clock enable bit
+              30
+              1
+            
+          
+        
+        
+          IOPSMEN
+          IOPSMEN
+          GPIO clock enable in sleep mode
+          register
+          0x3C
+          0x20
+          read-write
+          0x0000008F
+          
+            
+              IOPHSMEN
+              IOPHSMEN
+              7
+              1
+            
+            
+              IOPDSMEN
+              IOPDSMEN
+              3
+              1
+            
+            
+              IOPCSMEN
+              IOPCSMEN
+              2
+              1
+            
+            
+              IOPBSMEN
+              IOPBSMEN
+              1
+              1
+            
+            
+              IOPASMEN
+              IOPASMEN
+              0
+              1
+            
+            
+              IOPESMEN
+              Port E clock enable during Sleep mode
+              bit
+              4
+              1
+            
+          
+        
+        
+          AHBSMENR
+          AHBSMENR
+          AHB peripheral clock enable in sleep mode
+          register
+          0x40
+          0x20
+          read-write
+          0x01111301
+          
+            
+              CRYPSMEN
+              Crypto clock enable during sleep mode
+              bit
+              24
+              1
+            
+            
+              RNGSMEN
+              Random Number Generator clock enable
+              during sleep mode bit
+              20
+              1
+            
+            
+              TOUCHSMEN
+              Touch Sensing clock enable during sleep
+              mode bit
+              16
+              1
+            
+            
+              CRCSMEN
+              CRC clock enable during sleep mode
+              bit
+              12
+              1
+            
+            
+              SRAMSMEN
+              SRAM interface clock enable during sleep
+              mode bit
+              9
+              1
+            
+            
+              MIFSMEN
+              NVM interface clock enable during sleep
+              mode bit
+              8
+              1
+            
+            
+              DMASMEN
+              DMA clock enable during sleep mode
+              bit
+              0
+              1
+            
+          
+        
+        
+          APB2SMENR
+          APB2SMENR
+          APB2 peripheral clock enable in sleep mode
+          register
+          0x44
+          0x20
+          read-write
+          0x00405225
+          
+            
+              DBGSMEN
+              DBG clock enable during sleep mode
+              bit
+              22
+              1
+            
+            
+              USART1SMEN
+              USART1 clock enable during sleep mode
+              bit
+              14
+              1
+            
+            
+              SPI1SMEN
+              SPI1 clock enable during sleep mode
+              bit
+              12
+              1
+            
+            
+              ADCSMEN
+              ADC clock enable during sleep mode
+              bit
+              9
+              1
+            
+            
+              TIM22SMEN
+              TIM22 timer clock enable during sleep
+              mode bit
+              5
+              1
+            
+            
+              TIM21SMEN
+              TIM21 timer clock enable during sleep
+              mode bit
+              2
+              1
+            
+            
+              SYSCFGSMEN
+              System configuration controller clock
+              enable during sleep mode bit
+              0
+              1
+            
+          
+        
+        
+          APB1SMENR
+          APB1SMENR
+          APB1 peripheral clock enable in sleep mode
+          register
+          0x48
+          0x20
+          read-write
+          0xB8E64A11
+          
+            
+              LPTIM1SMEN
+              Low power timer clock enable during
+              sleep mode bit
+              31
+              1
+            
+            
+              DACSMEN
+              DAC interface clock enable during sleep
+              mode bit
+              29
+              1
+            
+            
+              PWRSMEN
+              Power interface clock enable during
+              sleep mode bit
+              28
+              1
+            
+            
+              CRSSMEN
+              Clock recovery system clock enable
+              during sleep mode bit
+              27
+              1
+            
+            
+              USBSMEN
+              USB clock enable during sleep mode
+              bit
+              23
+              1
+            
+            
+              I2C2SMEN
+              I2C2 clock enable during sleep mode
+              bit
+              22
+              1
+            
+            
+              I2C1SMEN
+              I2C1 clock enable during sleep mode
+              bit
+              21
+              1
+            
+            
+              LPUART1SMEN
+              LPUART1 clock enable during sleep mode
+              bit
+              18
+              1
+            
+            
+              USART2SMEN
+              UART2 clock enable during sleep mode
+              bit
+              17
+              1
+            
+            
+              SPI2SMEN
+              SPI2 clock enable during sleep mode
+              bit
+              14
+              1
+            
+            
+              WWDGSMEN
+              Window watchdog clock enable during
+              sleep mode bit
+              11
+              1
+            
+            
+              TIM6SMEN
+              Timer 6 clock enable during sleep mode
+              bit
+              4
+              1
+            
+            
+              TIM2SMEN
+              Timer2 clock enable during sleep mode
+              bit
+              0
+              1
+            
+            
+              TIM3SMEN
+              Timer3 clock enable during Sleep mode
+              bit
+              1
+              1
+            
+            
+              TIM7SMEN
+              Timer 7 clock enable during Sleep mode
+              bit
+              5
+              1
+            
+            
+              USART4SMEN
+              USART4 clock enable during Sleep mode
+              bit
+              19
+              1
+            
+            
+              USART5SMEN
+              USART5 clock enable during Sleep mode
+              bit
+              20
+              1
+            
+            
+              I2C3SMEN
+              2C3 clock enable during Sleep mode
+              bit
+              30
+              1
+            
+          
+        
+        
+          CCIPR
+          CCIPR
+          Clock configuration register
+          0x4C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              HSI48MSEL
+              48 MHz HSI48 clock source selection
+              bit
+              26
+              1
+            
+            
+              LPTIM1SEL1
+              Low Power Timer clock source selection
+              bits
+              19
+              1
+            
+            
+              LPTIM1SEL0
+              LPTIM1SEL0
+              18
+              1
+            
+            
+              I2C1SEL1
+              I2C1 clock source selection
+              bits
+              13
+              1
+            
+            
+              I2C1SEL0
+              I2C1SEL0
+              12
+              1
+            
+            
+              LPUART1SEL1
+              LPUART1 clock source selection
+              bits
+              11
+              1
+            
+            
+              LPUART1SEL0
+              LPUART1SEL0
+              10
+              1
+            
+            
+              USART2SEL1
+              USART2 clock source selection
+              bits
+              3
+              1
+            
+            
+              USART2SEL0
+              USART2SEL0
+              2
+              1
+            
+            
+              USART1SEL1
+              USART1 clock source selection
+              bits
+              1
+              1
+            
+            
+              USART1SEL0
+              USART1SEL0
+              0
+              1
+            
+            
+              I2C3SEL
+              I2C3 clock source selection
+              bits
+              16
+              2
+            
+          
+        
+        
+          CSR
+          CSR
+          Control and status register
+          0x50
+          0x20
+          0x0C000000
+          
+            
+              LPWRSTF
+              Low-power reset flag
+              31
+              1
+              read-write
+            
+            
+              WWDGRSTF
+              Window watchdog reset flag
+              30
+              1
+              read-write
+            
+            
+              IWDGRSTF
+              Independent watchdog reset
+              flag
+              29
+              1
+              read-write
+            
+            
+              SFTRSTF
+              Software reset flag
+              28
+              1
+              read-write
+            
+            
+              PORRSTF
+              POR/PDR reset flag
+              27
+              1
+              read-write
+            
+            
+              PINRSTF
+              PIN reset flag
+              26
+              1
+              read-write
+            
+            
+              OBLRSTF
+              OBLRSTF
+              25
+              1
+              read-write
+            
+            
+              RMVF
+              Remove reset flag
+              24
+              1
+              read-write
+            
+            
+              RTCRST
+              RTC software reset bit
+              19
+              1
+              read-write
+            
+            
+              RTCEN
+              RTC clock enable bit
+              18
+              1
+              read-write
+            
+            
+              RTCSEL
+              RTC and LCD clock source selection
+              bits
+              16
+              2
+              read-write
+            
+            
+              CSSLSED
+              CSS on LSE failure detection
+              flag
+              14
+              1
+              read-write
+            
+            
+              CSSLSEON
+              CSSLSEON
+              13
+              1
+              read-write
+            
+            
+              LSEDRV
+              LSEDRV
+              11
+              2
+              read-write
+            
+            
+              LSEBYP
+              External low-speed oscillator bypass
+              bit
+              10
+              1
+              read-write
+            
+            
+              LSERDY
+              External low-speed oscillator ready
+              bit
+              9
+              1
+              read-only
+            
+            
+              LSEON
+              External low-speed oscillator enable
+              bit
+              8
+              1
+              read-write
+            
+            
+              LSIRDY
+              Internal low-speed oscillator ready
+              bit
+              1
+              1
+              read-write
+            
+            
+              LSION
+              Internal low-speed oscillator
+              enable
+              0
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      SYSCFG_COMP
+      System configuration controller and
+      Comparator
+      SYSCFG
+      0x40010000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CFGR1
+          CFGR1
+          SYSCFG configuration register
+          1
+          0x0
+          0x20
+          0x00000000
+          
+            
+              BOOT_MODE
+              Boot mode selected by the boot pins
+              status bits
+              8
+              2
+              read-only
+            
+            
+              MEM_MODE
+              Memory mapping selection
+              bits
+              0
+              2
+              read-write
+            
+          
+        
+        
+          CFGR2
+          CFGR2
+          SYSCFG configuration register
+          2
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              I2C2_FMP
+              I2C2 Fm+ drive capability enable
+              bit
+              13
+              1
+            
+            
+              I2C1_FMP
+              I2C1 Fm+ drive capability enable
+              bit
+              12
+              1
+            
+            
+              I2C_PB9_FMP
+              Fm+ drive capability on PB9 enable
+              bit
+              11
+              1
+            
+            
+              I2C_PB8_FMP
+              Fm+ drive capability on PB8 enable
+              bit
+              10
+              1
+            
+            
+              I2C_PB7_FMP
+              Fm+ drive capability on PB7 enable
+              bit
+              9
+              1
+            
+            
+              I2C_PB6_FMP
+              Fm+ drive capability on PB6 enable
+              bit
+              8
+              1
+            
+            
+              FWDISEN
+              Firewall disable bit
+              0
+              1
+            
+          
+        
+        
+          EXTICR1
+          EXTICR1
+          external interrupt configuration register
+          1
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI3
+              EXTI x configuration (x = 0 to
+              3)
+              12
+              4
+            
+            
+              EXTI2
+              EXTI x configuration (x = 0 to
+              3)
+              8
+              4
+            
+            
+              EXTI1
+              EXTI x configuration (x = 0 to
+              3)
+              4
+              4
+            
+            
+              EXTI0
+              EXTI x configuration (x = 0 to
+              3)
+              0
+              4
+            
+          
+        
+        
+          EXTICR2
+          EXTICR2
+          external interrupt configuration register
+          2
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI7
+              EXTI x configuration (x = 4 to
+              7)
+              12
+              4
+            
+            
+              EXTI6
+              EXTI x configuration (x = 4 to
+              7)
+              8
+              4
+            
+            
+              EXTI5
+              EXTI x configuration (x = 4 to
+              7)
+              4
+              4
+            
+            
+              EXTI4
+              EXTI x configuration (x = 4 to
+              7)
+              0
+              4
+            
+          
+        
+        
+          EXTICR3
+          EXTICR3
+          external interrupt configuration register
+          3
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI11
+              EXTI x configuration (x = 8 to
+              11)
+              12
+              4
+            
+            
+              EXTI10
+              EXTI10
+              8
+              4
+            
+            
+              EXTI9
+              EXTI x configuration (x = 8 to
+              11)
+              4
+              4
+            
+            
+              EXTI8
+              EXTI x configuration (x = 8 to
+              11)
+              0
+              4
+            
+          
+        
+        
+          EXTICR4
+          EXTICR4
+          external interrupt configuration register
+          4
+          0x14
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI15
+              EXTI x configuration (x = 12 to
+              15)
+              12
+              4
+            
+            
+              EXTI14
+              EXTI14
+              8
+              4
+            
+            
+              EXTI13
+              EXTI13
+              4
+              4
+            
+            
+              EXTI12
+              EXTI12
+              0
+              4
+            
+          
+        
+        
+          CFGR3
+          CFGR3
+          SYSCFG configuration register
+          3
+          0x20
+          0x20
+          0x00000000
+          
+            
+              REF_LOCK
+              REF_CTRL lock bit
+              31
+              1
+              write-only
+            
+            
+              VREFINT_RDYF
+              VREFINT ready flag
+              30
+              1
+              read-only
+            
+            
+              VREFINT_COMP_RDYF
+              VREFINT for comparator ready
+              flag
+              29
+              1
+              read-only
+            
+            
+              VREFINT_ADC_RDYF
+              VREFINT for ADC ready flag
+              28
+              1
+              read-only
+            
+            
+              SENSOR_ADC_RDYF
+              Sensor for ADC ready flag
+              27
+              1
+              read-only
+            
+            
+              REF_RC48MHz_RDYF
+              VREFINT for 48 MHz RC oscillator ready
+              flag
+              26
+              1
+              read-only
+            
+            
+              ENREF_RC48MHz
+              VREFINT reference for 48 MHz RC
+              oscillator enable bit
+              13
+              1
+              read-write
+            
+            
+              ENBUF_VREFINT_COMP
+              VREFINT reference for comparator 2
+              enable bit
+              12
+              1
+              read-write
+            
+            
+              ENBUF_SENSOR_ADC
+              Sensor reference for ADC enable
+              bit
+              9
+              1
+              read-write
+            
+            
+              ENBUF_BGAP_ADC
+              VREFINT reference for ADC enable
+              bit
+              8
+              1
+              read-write
+            
+            
+              SEL_VREF_OUT
+              BGAP_ADC connection bit
+              4
+              2
+              read-write
+            
+            
+              EN_BGAP
+              Vref Enable bit
+              0
+              1
+              read-write
+            
+          
+        
+        
+          COMP1_CSR
+          COMP1_CSR
+          Comparator 1 control and status
+          register
+          0x18
+          0x20
+          0x00000000
+          
+            
+              COMP1LOCK
+              COMP1_CSR register lock
+              bit
+              31
+              1
+              read-only
+            
+            
+              COMP1VALUE
+              Comparator 1 output status
+              bit
+              30
+              1
+              read-only
+            
+            
+              COMP1POLARITY
+              Comparator 1 polarity selection
+              bit
+              15
+              1
+              read-write
+            
+            
+              COMP1LPTIMIN1
+              Comparator 1 LPTIM input propagation
+              bit
+              12
+              1
+              read-write
+            
+            
+              COMP1WM
+              Comparator 1 window mode selection
+              bit
+              8
+              1
+              read-write
+            
+            
+              COMP1INNSEL
+              Comparator 1 Input Minus connection
+              configuration bit
+              4
+              2
+              read-write
+            
+            
+              COMP1EN
+              Comparator 1 enable bit
+              0
+              1
+              read-write
+            
+          
+        
+        
+          COMP2_CSR
+          COMP2_CSR
+          Comparator 2 control and status
+          register
+          0x1C
+          0x20
+          0x00000000
+          
+            
+              COMP2LOCK
+              COMP2_CSR register lock
+              bit
+              31
+              1
+              read-only
+            
+            
+              COMP2VALUE
+              Comparator 2 output status
+              bit
+              20
+              1
+              read-only
+            
+            
+              COMP2POLARITY
+              Comparator 2 polarity selection
+              bit
+              15
+              1
+              read-write
+            
+            
+              COMP2LPTIMIN1
+              Comparator 2 LPTIM input 1 propagation
+              bit
+              13
+              1
+              read-write
+            
+            
+              COMP2LPTIMIN2
+              Comparator 2 LPTIM input 2 propagation
+              bit
+              12
+              1
+              read-write
+            
+            
+              COMP2INPSEL
+              Comparator 2 Input Plus connection
+              configuration bit
+              8
+              3
+              read-write
+            
+            
+              COMP2INNSEL
+              Comparator 2 Input Minus connection
+              configuration bit
+              4
+              3
+              read-write
+            
+            
+              COMP2SPEED
+              Comparator 2 power mode selection
+              bit
+              3
+              1
+              read-write
+            
+            
+              COMP2EN
+              Comparator 2 enable bit
+              0
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      SPI1
+      Serial peripheral interface
+      SPI
+      0x40013000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              BIDIMODE
+              Bidirectional data mode
+              enable
+              15
+              1
+            
+            
+              BIDIOE
+              Output enable in bidirectional
+              mode
+              14
+              1
+            
+            
+              CRCEN
+              Hardware CRC calculation
+              enable
+              13
+              1
+            
+            
+              CRCNEXT
+              CRC transfer next
+              12
+              1
+            
+            
+              DFF
+              Data frame format
+              11
+              1
+            
+            
+              RXONLY
+              Receive only
+              10
+              1
+            
+            
+              SSM
+              Software slave management
+              9
+              1
+            
+            
+              SSI
+              Internal slave select
+              8
+              1
+            
+            
+              LSBFIRST
+              Frame format
+              7
+              1
+            
+            
+              SPE
+              SPI enable
+              6
+              1
+            
+            
+              BR
+              Baud rate control
+              3
+              3
+            
+            
+              MSTR
+              Master selection
+              2
+              1
+            
+            
+              CPOL
+              Clock polarity
+              1
+              1
+            
+            
+              CPHA
+              Clock phase
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              RXDMAEN
+              Rx buffer DMA enable
+              0
+              1
+            
+            
+              TXDMAEN
+              Tx buffer DMA enable
+              1
+              1
+            
+            
+              SSOE
+              SS output enable
+              2
+              1
+            
+            
+              FRF
+              Frame format
+              4
+              1
+            
+            
+              ERRIE
+              Error interrupt enable
+              5
+              1
+            
+            
+              RXNEIE
+              RX buffer not empty interrupt
+              enable
+              6
+              1
+            
+            
+              TXEIE
+              Tx buffer empty interrupt
+              enable
+              7
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x8
+          0x20
+          0x0002
+          
+            
+              RXNE
+              Receive buffer not empty
+              0
+              1
+              read-only
+            
+            
+              TXE
+              Transmit buffer empty
+              1
+              1
+              read-only
+            
+            
+              CHSIDE
+              Channel side
+              2
+              1
+              read-only
+            
+            
+              UDR
+              Underrun flag
+              3
+              1
+              read-only
+            
+            
+              CRCERR
+              CRC error flag
+              4
+              1
+              read-write
+            
+            
+              MODF
+              Mode fault
+              5
+              1
+              read-only
+            
+            
+              OVR
+              Overrun flag
+              6
+              1
+              read-only
+            
+            
+              BSY
+              Busy flag
+              7
+              1
+              read-only
+            
+            
+              TIFRFE
+              TI frame format error
+              8
+              1
+              read-only
+            
+          
+        
+        
+          DR
+          DR
+          data register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              DR
+              Data register
+              0
+              16
+            
+          
+        
+        
+          CRCPR
+          CRCPR
+          CRC polynomial register
+          0x10
+          0x20
+          read-write
+          0x0007
+          
+            
+              CRCPOLY
+              CRC polynomial register
+              0
+              16
+            
+          
+        
+        
+          RXCRCR
+          RXCRCR
+          RX CRC register
+          0x14
+          0x20
+          read-only
+          0x0000
+          
+            
+              RxCRC
+              Rx CRC register
+              0
+              16
+            
+          
+        
+        
+          TXCRCR
+          TXCRCR
+          TX CRC register
+          0x18
+          0x20
+          read-only
+          0x0000
+          
+            
+              TxCRC
+              Tx CRC register
+              0
+              16
+            
+          
+        
+        
+          I2SCFGR
+          I2SCFGR
+          I2S configuration register
+          0x1C
+          0x20
+          read-write
+          0x0000
+          
+            
+              I2SMOD
+              I2S mode selection
+              11
+              1
+            
+            
+              I2SE
+              I2S Enable
+              10
+              1
+            
+            
+              I2SCFG
+              I2S configuration mode
+              8
+              2
+            
+            
+              PCMSYNC
+              PCM frame synchronization
+              7
+              1
+            
+            
+              I2SSTD
+              I2S standard selection
+              4
+              2
+            
+            
+              CKPOL
+              Steady state clock
+              polarity
+              3
+              1
+            
+            
+              DATLEN
+              Data length to be
+              transferred
+              1
+              2
+            
+            
+              CHLEN
+              Channel length (number of bits per audio
+              channel)
+              0
+              1
+            
+          
+        
+        
+          I2SPR
+          I2SPR
+          I2S prescaler register
+          0x20
+          0x20
+          read-write
+          0x00000010
+          
+            
+              MCKOE
+              Master clock output enable
+              9
+              1
+            
+            
+              ODD
+              Odd factor for the
+              prescaler
+              8
+              1
+            
+            
+              I2SDIV
+              I2S Linear prescaler
+              0
+              8
+            
+          
+        
+      
+    
+    
+      SPI2
+      0x40003800
+      
+        SPI1
+        SPI1_global_interrupt
+        25
+      
+    
+    
+      I2C1
+      Inter-integrated circuit
+      I2C
+      0x40005400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        SPI2
+        SPI2 global interrupt
+        26
+      
+      
+        
+          CR1
+          CR1
+          Control register 1
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PE
+              Peripheral enable
+              0
+              1
+            
+            
+              TXIE
+              TX Interrupt enable
+              1
+              1
+            
+            
+              RXIE
+              RX Interrupt enable
+              2
+              1
+            
+            
+              ADDRIE
+              Address match interrupt enable (slave
+              only)
+              3
+              1
+            
+            
+              NACKIE
+              Not acknowledge received interrupt
+              enable
+              4
+              1
+            
+            
+              STOPIE
+              STOP detection Interrupt
+              enable
+              5
+              1
+            
+            
+              TCIE
+              Transfer Complete interrupt
+              enable
+              6
+              1
+            
+            
+              ERRIE
+              Error interrupts enable
+              7
+              1
+            
+            
+              DNF
+              Digital noise filter
+              8
+              4
+            
+            
+              ANFOFF
+              Analog noise filter OFF
+              12
+              1
+            
+            
+              TXDMAEN
+              DMA transmission requests
+              enable
+              14
+              1
+            
+            
+              RXDMAEN
+              DMA reception requests
+              enable
+              15
+              1
+            
+            
+              SBC
+              Slave byte control
+              16
+              1
+            
+            
+              NOSTRETCH
+              Clock stretching disable
+              17
+              1
+            
+            
+              WUPEN
+              Wakeup from STOP enable
+              18
+              1
+            
+            
+              GCEN
+              General call enable
+              19
+              1
+            
+            
+              SMBHEN
+              SMBus Host address enable
+              20
+              1
+            
+            
+              SMBDEN
+              SMBus Device Default address
+              enable
+              21
+              1
+            
+            
+              ALERTEN
+              SMBUS alert enable
+              22
+              1
+            
+            
+              PECEN
+              PEC enable
+              23
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          Control register 2
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PECBYTE
+              Packet error checking byte
+              26
+              1
+            
+            
+              AUTOEND
+              Automatic end mode (master
+              mode)
+              25
+              1
+            
+            
+              RELOAD
+              NBYTES reload mode
+              24
+              1
+            
+            
+              NBYTES
+              Number of bytes
+              16
+              8
+            
+            
+              NACK
+              NACK generation (slave
+              mode)
+              15
+              1
+            
+            
+              STOP
+              Stop generation (master
+              mode)
+              14
+              1
+            
+            
+              START
+              Start generation
+              13
+              1
+            
+            
+              HEAD10R
+              10-bit address header only read
+              direction (master receiver mode)
+              12
+              1
+            
+            
+              ADD10
+              10-bit addressing mode (master
+              mode)
+              11
+              1
+            
+            
+              RD_WRN
+              Transfer direction (master
+              mode)
+              10
+              1
+            
+            
+              SADD
+              Slave address bit (master
+              mode)
+              0
+              10
+            
+          
+        
+        
+          OAR1
+          OAR1
+          Own address register 1
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OA1
+              Interface address
+              0
+              10
+            
+            
+              OA1MODE
+              Own Address 1 10-bit mode
+              10
+              1
+            
+            
+              OA1EN
+              Own Address 1 enable
+              15
+              1
+            
+          
+        
+        
+          OAR2
+          OAR2
+          Own address register 2
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OA2
+              Interface address
+              1
+              7
+            
+            
+              OA2MSK
+              Own Address 2 masks
+              8
+              3
+            
+            
+              OA2EN
+              Own Address 2 enable
+              15
+              1
+            
+          
+        
+        
+          TIMINGR
+          TIMINGR
+          Timing register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SCLL
+              SCL low period (master
+              mode)
+              0
+              8
+            
+            
+              SCLH
+              SCL high period (master
+              mode)
+              8
+              8
+            
+            
+              SDADEL
+              Data hold time
+              16
+              4
+            
+            
+              SCLDEL
+              Data setup time
+              20
+              4
+            
+            
+              PRESC
+              Timing prescaler
+              28
+              4
+            
+          
+        
+        
+          TIMEOUTR
+          TIMEOUTR
+          Status register 1
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TIMEOUTA
+              Bus timeout A
+              0
+              12
+            
+            
+              TIDLE
+              Idle clock timeout
+              detection
+              12
+              1
+            
+            
+              TIMOUTEN
+              Clock timeout enable
+              15
+              1
+            
+            
+              TIMEOUTB
+              Bus timeout B
+              16
+              12
+            
+            
+              TEXTEN
+              Extended clock timeout
+              enable
+              31
+              1
+            
+          
+        
+        
+          ISR
+          ISR
+          Interrupt and Status register
+          0x18
+          0x20
+          0x00000001
+          
+            
+              ADDCODE
+              Address match code (Slave
+              mode)
+              17
+              7
+              read-only
+            
+            
+              DIR
+              Transfer direction (Slave
+              mode)
+              16
+              1
+              read-only
+            
+            
+              BUSY
+              Bus busy
+              15
+              1
+              read-only
+            
+            
+              ALERT
+              SMBus alert
+              13
+              1
+              read-only
+            
+            
+              TIMEOUT
+              Timeout or t_low detection
+              flag
+              12
+              1
+              read-only
+            
+            
+              PECERR
+              PEC Error in reception
+              11
+              1
+              read-only
+            
+            
+              OVR
+              Overrun/Underrun (slave
+              mode)
+              10
+              1
+              read-only
+            
+            
+              ARLO
+              Arbitration lost
+              9
+              1
+              read-only
+            
+            
+              BERR
+              Bus error
+              8
+              1
+              read-only
+            
+            
+              TCR
+              Transfer Complete Reload
+              7
+              1
+              read-only
+            
+            
+              TC
+              Transfer Complete (master
+              mode)
+              6
+              1
+              read-only
+            
+            
+              STOPF
+              Stop detection flag
+              5
+              1
+              read-only
+            
+            
+              NACKF
+              Not acknowledge received
+              flag
+              4
+              1
+              read-only
+            
+            
+              ADDR
+              Address matched (slave
+              mode)
+              3
+              1
+              read-only
+            
+            
+              RXNE
+              Receive data register not empty
+              (receivers)
+              2
+              1
+              read-only
+            
+            
+              TXIS
+              Transmit interrupt status
+              (transmitters)
+              1
+              1
+              read-write
+            
+            
+              TXE
+              Transmit data register empty
+              (transmitters)
+              0
+              1
+              read-write
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt clear register
+          0x1C
+          0x20
+          write-only
+          0x00000000
+          
+            
+              ALERTCF
+              Alert flag clear
+              13
+              1
+            
+            
+              TIMOUTCF
+              Timeout detection flag
+              clear
+              12
+              1
+            
+            
+              PECCF
+              PEC Error flag clear
+              11
+              1
+            
+            
+              OVRCF
+              Overrun/Underrun flag
+              clear
+              10
+              1
+            
+            
+              ARLOCF
+              Arbitration lost flag
+              clear
+              9
+              1
+            
+            
+              BERRCF
+              Bus error flag clear
+              8
+              1
+            
+            
+              STOPCF
+              Stop detection flag clear
+              5
+              1
+            
+            
+              NACKCF
+              Not Acknowledge flag clear
+              4
+              1
+            
+            
+              ADDRCF
+              Address Matched flag clear
+              3
+              1
+            
+          
+        
+        
+          PECR
+          PECR
+          PEC register
+          0x20
+          0x20
+          read-only
+          0x00000000
+          
+            
+              PEC
+              Packet error checking
+              register
+              0
+              8
+            
+          
+        
+        
+          RXDR
+          RXDR
+          Receive data register
+          0x24
+          0x20
+          read-only
+          0x00000000
+          
+            
+              RXDATA
+              8-bit receive data
+              0
+              8
+            
+          
+        
+        
+          TXDR
+          TXDR
+          Transmit data register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TXDATA
+              8-bit transmit data
+              0
+              8
+            
+          
+        
+      
+    
+    
+      I2C2
+      0x40005800
+      
+        I2C1
+        I2C1 global interrupt
+        23
+      
+      
+        I2C2
+        I2C2 global interrupt
+        24
+      
+    
+    
+      I2C3
+      0x40007800
+    
+    
+      PWR
+      Power control
+      PWR
+      0x40007000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        I2C3
+        I2C3 global interrupt
+        21
+      
+      
+        
+          CR
+          CR
+          power control register
+          0x0
+          0x20
+          read-write
+          0x00001000
+          
+            
+              LPDS
+              Low-power deep sleep
+              0
+              1
+            
+            
+              PDDS
+              Power down deepsleep
+              1
+              1
+            
+            
+              CWUF
+              Clear wakeup flag
+              2
+              1
+            
+            
+              CSBF
+              Clear standby flag
+              3
+              1
+            
+            
+              PVDE
+              Power voltage detector
+              enable
+              4
+              1
+            
+            
+              PLS
+              PVD level selection
+              5
+              3
+            
+            
+              DBP
+              Disable backup domain write
+              protection
+              8
+              1
+            
+            
+              ULP
+              Ultra-low-power mode
+              9
+              1
+            
+            
+              FWU
+              Fast wakeup
+              10
+              1
+            
+            
+              VOS
+              Voltage scaling range
+              selection
+              11
+              2
+            
+            
+              DS_EE_KOFF
+              Deep sleep mode with Flash memory kept
+              off
+              13
+              1
+            
+            
+              LPRUN
+              Low power run mode
+              14
+              1
+            
+          
+        
+        
+          CSR
+          CSR
+          power control/status register
+          0x4
+          0x20
+          0x00000000
+          
+            
+              BRE
+              Backup regulator enable
+              9
+              1
+              read-write
+            
+            
+              EWUP
+              Enable WKUP pin
+              8
+              1
+              read-write
+            
+            
+              BRR
+              Backup regulator ready
+              3
+              1
+              read-only
+            
+            
+              PVDO
+              PVD output
+              2
+              1
+              read-only
+            
+            
+              SBF
+              Standby flag
+              1
+              1
+              read-only
+            
+            
+              WUF
+              Wakeup flag
+              0
+              1
+              read-only
+            
+            
+              VOSF
+              Voltage Scaling select
+              flag
+              4
+              1
+              read-only
+            
+            
+              REGLPF
+              Regulator LP flag
+              5
+              1
+              read-only
+            
+          
+        
+      
+    
+    
+      Flash
+      Flash
+      Flash
+      0x40022000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          ACR
+          ACR
+          Access control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LATENCY
+              Latency
+              0
+              1
+            
+            
+              PRFTEN
+              Prefetch enable
+              1
+              1
+            
+            
+              SLEEP_PD
+              Flash mode during Sleep
+              3
+              1
+            
+            
+              RUN_PD
+              Flash mode during Run
+              4
+              1
+            
+            
+              DESAB_BUF
+              Disable Buffer
+              5
+              1
+            
+            
+              PRE_READ
+              Pre-read data address
+              6
+              1
+            
+          
+        
+        
+          PECR
+          PECR
+          Program/erase control register
+          0x4
+          0x20
+          read-write
+          0x00000007
+          
+            
+              PELOCK
+              FLASH_PECR and data EEPROM
+              lock
+              0
+              1
+            
+            
+              PRGLOCK
+              Program memory lock
+              1
+              1
+            
+            
+              OPTLOCK
+              Option bytes block lock
+              2
+              1
+            
+            
+              PROG
+              Program memory selection
+              3
+              1
+            
+            
+              DATA
+              Data EEPROM selection
+              4
+              1
+            
+            
+              FTDW
+              Fixed time data write for Byte, Half
+              Word and Word programming
+              8
+              1
+            
+            
+              ERASE
+              Page or Double Word erase
+              mode
+              9
+              1
+            
+            
+              FPRG
+              Half Page/Double Word programming
+              mode
+              10
+              1
+            
+            
+              PARALLELBANK
+              Parallel bank mode
+              15
+              1
+            
+            
+              EOPIE
+              End of programming interrupt
+              enable
+              16
+              1
+            
+            
+              ERRIE
+              Error interrupt enable
+              17
+              1
+            
+            
+              OBL_LAUNCH
+              Launch the option byte
+              loading
+              18
+              1
+            
+          
+        
+        
+          PDKEYR
+          PDKEYR
+          Power down key register
+          0x8
+          0x20
+          write-only
+          0x00000000
+          
+            
+              PDKEYR
+              RUN_PD in FLASH_ACR key
+              0
+              32
+            
+          
+        
+        
+          PEKEYR
+          PEKEYR
+          Program/erase key register
+          0xC
+          0x20
+          write-only
+          0x00000000
+          
+            
+              PEKEYR
+              FLASH_PEC and data EEPROM
+              key
+              0
+              32
+            
+          
+        
+        
+          PRGKEYR
+          PRGKEYR
+          Program memory key register
+          0x10
+          0x20
+          write-only
+          0x00000000
+          
+            
+              PRGKEYR
+              Program memory key
+              0
+              32
+            
+          
+        
+        
+          OPTKEYR
+          OPTKEYR
+          Option byte key register
+          0x14
+          0x20
+          write-only
+          0x00000000
+          
+            
+              OPTKEYR
+              Option byte key
+              0
+              32
+            
+          
+        
+        
+          SR
+          SR
+          Status register
+          0x18
+          0x20
+          0x00000004
+          
+            
+              BSY
+              Write/erase operations in
+              progress
+              0
+              1
+              read-only
+            
+            
+              EOP
+              End of operation
+              1
+              1
+              read-only
+            
+            
+              ENDHV
+              End of high voltage
+              2
+              1
+              read-only
+            
+            
+              READY
+              Flash memory module ready after low
+              power mode
+              3
+              1
+              read-only
+            
+            
+              WRPERR
+              Write protected error
+              8
+              1
+              read-write
+            
+            
+              PGAERR
+              Programming alignment
+              error
+              9
+              1
+              read-write
+            
+            
+              SIZERR
+              Size error
+              10
+              1
+              read-write
+            
+            
+              OPTVERR
+              Option validity error
+              11
+              1
+              read-write
+            
+            
+              RDERR
+              RDERR
+              14
+              1
+              read-write
+            
+            
+              NOTZEROERR
+              NOTZEROERR
+              16
+              1
+              read-write
+            
+            
+              FWWERR
+              FWWERR
+              17
+              1
+              read-write
+            
+          
+        
+        
+          OBR
+          OBR
+          Option byte register
+          0x1C
+          0x20
+          read-only
+          0x00F80000
+          
+            
+              RDPRT
+              Read protection
+              0
+              8
+            
+            
+              BOR_LEV
+              BOR_LEV
+              16
+              4
+            
+            
+              SPRMOD
+              Selection of protection mode of WPR
+              bits
+              8
+              1
+            
+          
+        
+        
+          WRPR
+          WRPR
+          Write protection register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              WRP
+              Write protection
+              0
+              16
+            
+          
+        
+      
+    
+    
+      EXTI
+      External interrupt/event
+      controller
+      EXTI
+      0x40010400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        PVD
+        PVD through EXTI line detection
+        1
+      
+      
+        EXTI0_1
+        EXTI Line[1:0] interrupts
+        5
+      
+      
+        EXTI2_3
+        EXTI Line[3:2] interrupts
+        6
+      
+      
+        EXTI4_15
+        EXTI Line15 and EXTI4 interrupts
+        7
+      
+      
+        
+          IMR
+          IMR
+          Interrupt mask register
+          (EXTI_IMR)
+          0x0
+          0x20
+          read-write
+          0xFF840000
+          
+            
+              IM0
+              Interrupt Mask on line 0
+              0
+              1
+            
+            
+              IM1
+              Interrupt Mask on line 1
+              1
+              1
+            
+            
+              IM2
+              Interrupt Mask on line 2
+              2
+              1
+            
+            
+              IM3
+              Interrupt Mask on line 3
+              3
+              1
+            
+            
+              IM4
+              Interrupt Mask on line 4
+              4
+              1
+            
+            
+              IM5
+              Interrupt Mask on line 5
+              5
+              1
+            
+            
+              IM6
+              Interrupt Mask on line 6
+              6
+              1
+            
+            
+              IM7
+              Interrupt Mask on line 7
+              7
+              1
+            
+            
+              IM8
+              Interrupt Mask on line 8
+              8
+              1
+            
+            
+              IM9
+              Interrupt Mask on line 9
+              9
+              1
+            
+            
+              IM10
+              Interrupt Mask on line 10
+              10
+              1
+            
+            
+              IM11
+              Interrupt Mask on line 11
+              11
+              1
+            
+            
+              IM12
+              Interrupt Mask on line 12
+              12
+              1
+            
+            
+              IM13
+              Interrupt Mask on line 13
+              13
+              1
+            
+            
+              IM14
+              Interrupt Mask on line 14
+              14
+              1
+            
+            
+              IM15
+              Interrupt Mask on line 15
+              15
+              1
+            
+            
+              IM16
+              Interrupt Mask on line 16
+              16
+              1
+            
+            
+              IM17
+              Interrupt Mask on line 17
+              17
+              1
+            
+            
+              IM18
+              Interrupt Mask on line 18
+              18
+              1
+            
+            
+              IM19
+              Interrupt Mask on line 19
+              19
+              1
+            
+            
+              IM20
+              Interrupt Mask on line 20
+              20
+              1
+            
+            
+              IM21
+              Interrupt Mask on line 21
+              21
+              1
+            
+            
+              IM22
+              Interrupt Mask on line 22
+              22
+              1
+            
+            
+              IM23
+              Interrupt Mask on line 23
+              23
+              1
+            
+            
+              IM24
+              Interrupt Mask on line 24
+              24
+              1
+            
+            
+              IM25
+              Interrupt Mask on line 25
+              25
+              1
+            
+            
+              IM26
+              Interrupt Mask on line 27
+              26
+              1
+            
+            
+              IM28
+              Interrupt Mask on line 27
+              28
+              1
+            
+            
+              IM29
+              Interrupt Mask on line 27
+              29
+              1
+            
+          
+        
+        
+          EMR
+          EMR
+          Event mask register (EXTI_EMR)
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EM0
+              Event Mask on line 0
+              0
+              1
+            
+            
+              EM1
+              Event Mask on line 1
+              1
+              1
+            
+            
+              EM2
+              Event Mask on line 2
+              2
+              1
+            
+            
+              EM3
+              Event Mask on line 3
+              3
+              1
+            
+            
+              EM4
+              Event Mask on line 4
+              4
+              1
+            
+            
+              EM5
+              Event Mask on line 5
+              5
+              1
+            
+            
+              EM6
+              Event Mask on line 6
+              6
+              1
+            
+            
+              EM7
+              Event Mask on line 7
+              7
+              1
+            
+            
+              EM8
+              Event Mask on line 8
+              8
+              1
+            
+            
+              EM9
+              Event Mask on line 9
+              9
+              1
+            
+            
+              EM10
+              Event Mask on line 10
+              10
+              1
+            
+            
+              EM11
+              Event Mask on line 11
+              11
+              1
+            
+            
+              EM12
+              Event Mask on line 12
+              12
+              1
+            
+            
+              EM13
+              Event Mask on line 13
+              13
+              1
+            
+            
+              EM14
+              Event Mask on line 14
+              14
+              1
+            
+            
+              EM15
+              Event Mask on line 15
+              15
+              1
+            
+            
+              EM16
+              Event Mask on line 16
+              16
+              1
+            
+            
+              EM17
+              Event Mask on line 17
+              17
+              1
+            
+            
+              EM18
+              Event Mask on line 18
+              18
+              1
+            
+            
+              EM19
+              Event Mask on line 19
+              19
+              1
+            
+            
+              EM20
+              Event Mask on line 20
+              20
+              1
+            
+            
+              EM21
+              Event Mask on line 21
+              21
+              1
+            
+            
+              EM22
+              Event Mask on line 22
+              22
+              1
+            
+            
+              EM23
+              Event Mask on line 23
+              23
+              1
+            
+            
+              EM24
+              Event Mask on line 24
+              24
+              1
+            
+            
+              EM25
+              Event Mask on line 25
+              25
+              1
+            
+            
+              EM26
+              Event Mask on line 26
+              26
+              1
+            
+            
+              EM28
+              Event Mask on line 28
+              28
+              1
+            
+            
+              EM29
+              Event Mask on line 29
+              29
+              1
+            
+          
+        
+        
+          RTSR
+          RTSR
+          Rising Trigger selection register
+          (EXTI_RTSR)
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              RT0
+              Rising trigger event configuration of
+              line 0
+              0
+              1
+            
+            
+              RT1
+              Rising trigger event configuration of
+              line 1
+              1
+              1
+            
+            
+              RT2
+              Rising trigger event configuration of
+              line 2
+              2
+              1
+            
+            
+              RT3
+              Rising trigger event configuration of
+              line 3
+              3
+              1
+            
+            
+              RT4
+              Rising trigger event configuration of
+              line 4
+              4
+              1
+            
+            
+              RT5
+              Rising trigger event configuration of
+              line 5
+              5
+              1
+            
+            
+              RT6
+              Rising trigger event configuration of
+              line 6
+              6
+              1
+            
+            
+              RT7
+              Rising trigger event configuration of
+              line 7
+              7
+              1
+            
+            
+              RT8
+              Rising trigger event configuration of
+              line 8
+              8
+              1
+            
+            
+              RT9
+              Rising trigger event configuration of
+              line 9
+              9
+              1
+            
+            
+              RT10
+              Rising trigger event configuration of
+              line 10
+              10
+              1
+            
+            
+              RT11
+              Rising trigger event configuration of
+              line 11
+              11
+              1
+            
+            
+              RT12
+              Rising trigger event configuration of
+              line 12
+              12
+              1
+            
+            
+              RT13
+              Rising trigger event configuration of
+              line 13
+              13
+              1
+            
+            
+              RT14
+              Rising trigger event configuration of
+              line 14
+              14
+              1
+            
+            
+              RT15
+              Rising trigger event configuration of
+              line 15
+              15
+              1
+            
+            
+              RT16
+              Rising trigger event configuration of
+              line 16
+              16
+              1
+            
+            
+              RT17
+              Rising trigger event configuration of
+              line 17
+              17
+              1
+            
+            
+              RT19
+              Rising trigger event configuration of
+              line 19
+              19
+              1
+            
+            
+              RT20
+              Rising trigger event configuration of
+              line 20
+              20
+              1
+            
+            
+              RT21
+              Rising trigger event configuration of
+              line 21
+              21
+              1
+            
+            
+              RT22
+              Rising trigger event configuration of
+              line 22
+              22
+              1
+            
+          
+        
+        
+          FTSR
+          FTSR
+          Falling Trigger selection register
+          (EXTI_FTSR)
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              FT0
+              Falling trigger event configuration of
+              line 0
+              0
+              1
+            
+            
+              FT1
+              Falling trigger event configuration of
+              line 1
+              1
+              1
+            
+            
+              FT2
+              Falling trigger event configuration of
+              line 2
+              2
+              1
+            
+            
+              FT3
+              Falling trigger event configuration of
+              line 3
+              3
+              1
+            
+            
+              FT4
+              Falling trigger event configuration of
+              line 4
+              4
+              1
+            
+            
+              FT5
+              Falling trigger event configuration of
+              line 5
+              5
+              1
+            
+            
+              FT6
+              Falling trigger event configuration of
+              line 6
+              6
+              1
+            
+            
+              FT7
+              Falling trigger event configuration of
+              line 7
+              7
+              1
+            
+            
+              FT8
+              Falling trigger event configuration of
+              line 8
+              8
+              1
+            
+            
+              FT9
+              Falling trigger event configuration of
+              line 9
+              9
+              1
+            
+            
+              FT10
+              Falling trigger event configuration of
+              line 10
+              10
+              1
+            
+            
+              FT11
+              Falling trigger event configuration of
+              line 11
+              11
+              1
+            
+            
+              FT12
+              Falling trigger event configuration of
+              line 12
+              12
+              1
+            
+            
+              FT13
+              Falling trigger event configuration of
+              line 13
+              13
+              1
+            
+            
+              FT14
+              Falling trigger event configuration of
+              line 14
+              14
+              1
+            
+            
+              FT15
+              Falling trigger event configuration of
+              line 15
+              15
+              1
+            
+            
+              FT16
+              Falling trigger event configuration of
+              line 16
+              16
+              1
+            
+            
+              FT17
+              Falling trigger event configuration of
+              line 17
+              17
+              1
+            
+            
+              FT19
+              Falling trigger event configuration of
+              line 19
+              19
+              1
+            
+            
+              FT20
+              Falling trigger event configuration of
+              line 20
+              20
+              1
+            
+            
+              FT21
+              Falling trigger event configuration of
+              line 21
+              21
+              1
+            
+            
+              FT22
+              Falling trigger event configuration of
+              line 22
+              22
+              1
+            
+          
+        
+        
+          SWIER
+          SWIER
+          Software interrupt event register
+          (EXTI_SWIER)
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SWI0
+              Software Interrupt on line
+              0
+              0
+              1
+            
+            
+              SWI1
+              Software Interrupt on line
+              1
+              1
+              1
+            
+            
+              SWI2
+              Software Interrupt on line
+              2
+              2
+              1
+            
+            
+              SWI3
+              Software Interrupt on line
+              3
+              3
+              1
+            
+            
+              SWI4
+              Software Interrupt on line
+              4
+              4
+              1
+            
+            
+              SWI5
+              Software Interrupt on line
+              5
+              5
+              1
+            
+            
+              SWI6
+              Software Interrupt on line
+              6
+              6
+              1
+            
+            
+              SWI7
+              Software Interrupt on line
+              7
+              7
+              1
+            
+            
+              SWI8
+              Software Interrupt on line
+              8
+              8
+              1
+            
+            
+              SWI9
+              Software Interrupt on line
+              9
+              9
+              1
+            
+            
+              SWI10
+              Software Interrupt on line
+              10
+              10
+              1
+            
+            
+              SWI11
+              Software Interrupt on line
+              11
+              11
+              1
+            
+            
+              SWI12
+              Software Interrupt on line
+              12
+              12
+              1
+            
+            
+              SWI13
+              Software Interrupt on line
+              13
+              13
+              1
+            
+            
+              SWI14
+              Software Interrupt on line
+              14
+              14
+              1
+            
+            
+              SWI15
+              Software Interrupt on line
+              15
+              15
+              1
+            
+            
+              SWI16
+              Software Interrupt on line
+              16
+              16
+              1
+            
+            
+              SWI17
+              Software Interrupt on line
+              17
+              17
+              1
+            
+            
+              SWI19
+              Software Interrupt on line
+              19
+              19
+              1
+            
+            
+              SWI20
+              Software Interrupt on line
+              20
+              20
+              1
+            
+            
+              SWI21
+              Software Interrupt on line
+              21
+              21
+              1
+            
+            
+              SWI22
+              Software Interrupt on line
+              22
+              22
+              1
+            
+          
+        
+        
+          PR
+          PR
+          Pending register (EXTI_PR)
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PIF0
+              Pending bit 0
+              0
+              1
+            
+            
+              PIF1
+              Pending bit 1
+              1
+              1
+            
+            
+              PIF2
+              Pending bit 2
+              2
+              1
+            
+            
+              PIF3
+              Pending bit 3
+              3
+              1
+            
+            
+              PIF4
+              Pending bit 4
+              4
+              1
+            
+            
+              PIF5
+              Pending bit 5
+              5
+              1
+            
+            
+              PIF6
+              Pending bit 6
+              6
+              1
+            
+            
+              PIF7
+              Pending bit 7
+              7
+              1
+            
+            
+              PIF8
+              Pending bit 8
+              8
+              1
+            
+            
+              PIF9
+              Pending bit 9
+              9
+              1
+            
+            
+              PIF10
+              Pending bit 10
+              10
+              1
+            
+            
+              PIF11
+              Pending bit 11
+              11
+              1
+            
+            
+              PIF12
+              Pending bit 12
+              12
+              1
+            
+            
+              PIF13
+              Pending bit 13
+              13
+              1
+            
+            
+              PIF14
+              Pending bit 14
+              14
+              1
+            
+            
+              PIF15
+              Pending bit 15
+              15
+              1
+            
+            
+              PIF16
+              Pending bit 16
+              16
+              1
+            
+            
+              PIF17
+              Pending bit 17
+              17
+              1
+            
+            
+              PIF19
+              Pending bit 19
+              19
+              1
+            
+            
+              PIF20
+              Pending bit 20
+              20
+              1
+            
+            
+              PIF21
+              Pending bit 21
+              21
+              1
+            
+            
+              PIF22
+              Pending bit 22
+              22
+              1
+            
+          
+        
+      
+    
+    
+      ADC
+      Analog-to-digital converter
+      ADC
+      0x40012400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        EXTI2_3
+        EXTI Line[3:2] interrupts
+        6
+      
+      
+        
+          ISR
+          ISR
+          interrupt and status register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADRDY
+              ADC ready
+              0
+              1
+            
+            
+              EOSMP
+              End of sampling flag
+              1
+              1
+            
+            
+              EOC
+              End of conversion flag
+              2
+              1
+            
+            
+              EOS
+              End of sequence flag
+              3
+              1
+            
+            
+              OVR
+              ADC overrun
+              4
+              1
+            
+            
+              AWD
+              Analog watchdog flag
+              7
+              1
+            
+            
+              EOCAL
+              End Of Calibration flag
+              11
+              1
+            
+          
+        
+        
+          IER
+          IER
+          interrupt enable register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADRDYIE
+              ADC ready interrupt enable
+              0
+              1
+            
+            
+              EOSMPIE
+              End of sampling flag interrupt
+              enable
+              1
+              1
+            
+            
+              EOCIE
+              End of conversion interrupt
+              enable
+              2
+              1
+            
+            
+              EOSIE
+              End of conversion sequence interrupt
+              enable
+              3
+              1
+            
+            
+              OVRIE
+              Overrun interrupt enable
+              4
+              1
+            
+            
+              AWDIE
+              Analog watchdog interrupt
+              enable
+              7
+              1
+            
+            
+              EOCALIE
+              End of calibration interrupt
+              enable
+              11
+              1
+            
+          
+        
+        
+          CR
+          CR
+          control register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADEN
+              ADC enable command
+              0
+              1
+            
+            
+              ADDIS
+              ADC disable command
+              1
+              1
+            
+            
+              ADSTART
+              ADC start conversion
+              command
+              2
+              1
+            
+            
+              ADSTP
+              ADC stop conversion
+              command
+              4
+              1
+            
+            
+              ADVREGEN
+              ADC Voltage Regulator
+              Enable
+              28
+              1
+            
+            
+              ADCAL
+              ADC calibration
+              31
+              1
+            
+          
+        
+        
+          CFGR1
+          CFGR1
+          configuration register 1
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AWDCH
+              Analog watchdog channel
+              selection
+              26
+              5
+            
+            
+              AWDEN
+              Analog watchdog enable
+              23
+              1
+            
+            
+              AWDSGL
+              Enable the watchdog on a single channel
+              or on all channels
+              22
+              1
+            
+            
+              DISCEN
+              Discontinuous mode
+              16
+              1
+            
+            
+              AUTOFF
+              Auto-off mode
+              15
+              1
+            
+            
+              AUTDLY
+              Auto-delayed conversion
+              mode
+              14
+              1
+            
+            
+              CONT
+              Single / continuous conversion
+              mode
+              13
+              1
+            
+            
+              OVRMOD
+              Overrun management mode
+              12
+              1
+            
+            
+              EXTEN
+              External trigger enable and polarity
+              selection
+              10
+              2
+            
+            
+              EXTSEL
+              External trigger selection
+              6
+              3
+            
+            
+              ALIGN
+              Data alignment
+              5
+              1
+            
+            
+              RES
+              Data resolution
+              3
+              2
+            
+            
+              SCANDIR
+              Scan sequence direction
+              2
+              1
+            
+            
+              DMACFG
+              Direct memery access
+              configuration
+              1
+              1
+            
+            
+              DMAEN
+              Direct memory access
+              enable
+              0
+              1
+            
+          
+        
+        
+          CFGR2
+          CFGR2
+          configuration register 2
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OVSE
+              Oversampler Enable
+              0
+              1
+            
+            
+              OVSR
+              Oversampling ratio
+              2
+              3
+            
+            
+              OVSS
+              Oversampling shift
+              5
+              4
+            
+            
+              TOVS
+              Triggered Oversampling
+              9
+              1
+            
+            
+              CKMODE
+              ADC clock mode
+              30
+              2
+            
+          
+        
+        
+          SMPR
+          SMPR
+          sampling time register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SMPR
+              Sampling time selection
+              0
+              3
+            
+          
+        
+        
+          TR
+          TR
+          watchdog threshold register
+          0x20
+          0x20
+          read-write
+          0x0FFF0000
+          
+            
+              HT
+              Analog watchdog higher
+              threshold
+              16
+              12
+            
+            
+              LT
+              Analog watchdog lower
+              threshold
+              0
+              12
+            
+          
+        
+        
+          CHSELR
+          CHSELR
+          channel selection register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CHSEL18
+              Channel-x selection
+              18
+              1
+            
+            
+              CHSEL17
+              Channel-x selection
+              17
+              1
+            
+            
+              CHSEL16
+              Channel-x selection
+              16
+              1
+            
+            
+              CHSEL15
+              Channel-x selection
+              15
+              1
+            
+            
+              CHSEL14
+              Channel-x selection
+              14
+              1
+            
+            
+              CHSEL13
+              Channel-x selection
+              13
+              1
+            
+            
+              CHSEL12
+              Channel-x selection
+              12
+              1
+            
+            
+              CHSEL11
+              Channel-x selection
+              11
+              1
+            
+            
+              CHSEL10
+              Channel-x selection
+              10
+              1
+            
+            
+              CHSEL9
+              Channel-x selection
+              9
+              1
+            
+            
+              CHSEL8
+              Channel-x selection
+              8
+              1
+            
+            
+              CHSEL7
+              Channel-x selection
+              7
+              1
+            
+            
+              CHSEL6
+              Channel-x selection
+              6
+              1
+            
+            
+              CHSEL5
+              Channel-x selection
+              5
+              1
+            
+            
+              CHSEL4
+              Channel-x selection
+              4
+              1
+            
+            
+              CHSEL3
+              Channel-x selection
+              3
+              1
+            
+            
+              CHSEL2
+              Channel-x selection
+              2
+              1
+            
+            
+              CHSEL1
+              Channel-x selection
+              1
+              1
+            
+            
+              CHSEL0
+              Channel-x selection
+              0
+              1
+            
+          
+        
+        
+          DR
+          DR
+          data register
+          0x40
+          0x20
+          read-only
+          0x00000000
+          
+            
+              DATA
+              Converted data
+              0
+              16
+            
+          
+        
+        
+          CALFACT
+          CALFACT
+          ADC Calibration factor
+          0xB4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CALFACT
+              Calibration factor
+              0
+              7
+            
+          
+        
+        
+          CCR
+          CCR
+          ADC common configuration
+          register
+          0x308
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRESC
+              ADC prescaler
+              18
+              4
+            
+            
+              VREFEN
+              VREFINT enable
+              22
+              1
+            
+            
+              TSEN
+              Temperature sensor enable
+              23
+              1
+            
+            
+              LFMEN
+              Low Frequency Mode enable
+              25
+              1
+            
+          
+        
+      
+    
+    
+      DBGMCU
+      Debug support
+      DBGMCU
+      0x40015800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        ADC_COMP
+        ADC and comparator 1 and 2
+        12
+      
+      
+        
+          IDCODE
+          IDCODE
+          MCU Device ID Code Register
+          0x0
+          0x20
+          read-only
+          0x0
+          
+            
+              DEV_ID
+              Device Identifier
+              0
+              12
+            
+            
+              REV_ID
+              Revision Identifier
+              16
+              16
+            
+          
+        
+        
+          CR
+          CR
+          Debug MCU Configuration
+          Register
+          0x4
+          0x20
+          read-write
+          0x0
+          
+            
+              DBG_STOP
+              Debug Stop Mode
+              1
+              1
+            
+            
+              DBG_STANDBY
+              Debug Standby Mode
+              2
+              1
+            
+            
+              DBG_SLEEP
+              Debug Sleep Mode
+              0
+              1
+            
+          
+        
+        
+          APB1_FZ
+          APB1_FZ
+          APB Low Freeze Register
+          0x8
+          0x20
+          read-write
+          0x0
+          
+            
+              DBG_TIMER2_STOP
+              Debug Timer 2 stopped when Core is
+              halted
+              0
+              1
+            
+            
+              DBG_TIMER6_STOP
+              Debug Timer 6 stopped when Core is
+              halted
+              4
+              1
+            
+            
+              DBG_RTC_STOP
+              Debug RTC stopped when Core is
+              halted
+              10
+              1
+            
+            
+              DBG_WWDG_STOP
+              Debug Window Wachdog stopped when Core
+              is halted
+              11
+              1
+            
+            
+              DBG_IWDG_STOP
+              Debug Independent Wachdog stopped when
+              Core is halted
+              12
+              1
+            
+            
+              DBG_I2C1_STOP
+              I2C1 SMBUS timeout mode stopped when
+              core is halted
+              21
+              1
+            
+            
+              DBG_I2C2_STOP
+              I2C2 SMBUS timeout mode stopped when
+              core is halted
+              22
+              1
+            
+            
+              DBG_LPTIMER_STOP
+              LPTIM1 counter stopped when core is
+              halted
+              31
+              1
+            
+          
+        
+        
+          APB2_FZ
+          APB2_FZ
+          APB High Freeze Register
+          0xC
+          0x20
+          read-write
+          0x0
+          
+            
+              DBG_TIMER21_STOP
+              Debug Timer 21 stopped when Core is
+              halted
+              2
+              1
+            
+            
+              DBG_TIMER22_STO
+              Debug Timer 22 stopped when Core is
+              halted
+              6
+              1
+            
+          
+        
+      
+    
+    
+      TIM2
+      General-purpose-timers
+      TIM
+      0x40000000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              CKD
+              Clock division
+              8
+              2
+            
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              CMS
+              Center-aligned mode
+              selection
+              5
+              2
+            
+            
+              DIR
+              Direction
+              4
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              TI1S
+              TI1 selection
+              7
+              1
+            
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+            
+              CCDS
+              Capture/compare DMA
+              selection
+              3
+              1
+            
+          
+        
+        
+          SMCR
+          SMCR
+          slave mode control register
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              ETP
+              External trigger polarity
+              15
+              1
+            
+            
+              ECE
+              External clock enable
+              14
+              1
+            
+            
+              ETPS
+              External trigger prescaler
+              12
+              2
+            
+            
+              ETF
+              External trigger filter
+              8
+              4
+            
+            
+              MSM
+              Master/Slave mode
+              7
+              1
+            
+            
+              TS
+              Trigger selection
+              4
+              3
+            
+            
+              SMS
+              Slave mode selection
+              0
+              3
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              TDE
+              Trigger DMA request enable
+              14
+              1
+            
+            
+              CC4DE
+              Capture/Compare 4 DMA request
+              enable
+              12
+              1
+            
+            
+              CC3DE
+              Capture/Compare 3 DMA request
+              enable
+              11
+              1
+            
+            
+              CC2DE
+              Capture/Compare 2 DMA request
+              enable
+              10
+              1
+            
+            
+              CC1DE
+              Capture/Compare 1 DMA request
+              enable
+              9
+              1
+            
+            
+              UDE
+              Update DMA request enable
+              8
+              1
+            
+            
+              TIE
+              Trigger interrupt enable
+              6
+              1
+            
+            
+              CC4IE
+              Capture/Compare 4 interrupt
+              enable
+              4
+              1
+            
+            
+              CC3IE
+              Capture/Compare 3 interrupt
+              enable
+              3
+              1
+            
+            
+              CC2IE
+              Capture/Compare 2 interrupt
+              enable
+              2
+              1
+            
+            
+              CC1IE
+              Capture/Compare 1 interrupt
+              enable
+              1
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC4OF
+              Capture/Compare 4 overcapture
+              flag
+              12
+              1
+            
+            
+              CC3OF
+              Capture/Compare 3 overcapture
+              flag
+              11
+              1
+            
+            
+              CC2OF
+              Capture/compare 2 overcapture
+              flag
+              10
+              1
+            
+            
+              CC1OF
+              Capture/Compare 1 overcapture
+              flag
+              9
+              1
+            
+            
+              TIF
+              Trigger interrupt flag
+              6
+              1
+            
+            
+              CC4IF
+              Capture/Compare 4 interrupt
+              flag
+              4
+              1
+            
+            
+              CC3IF
+              Capture/Compare 3 interrupt
+              flag
+              3
+              1
+            
+            
+              CC2IF
+              Capture/Compare 2 interrupt
+              flag
+              2
+              1
+            
+            
+              CC1IF
+              Capture/compare 1 interrupt
+              flag
+              1
+              1
+            
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              TG
+              Trigger generation
+              6
+              1
+            
+            
+              CC4G
+              Capture/compare 4
+              generation
+              4
+              1
+            
+            
+              CC3G
+              Capture/compare 3
+              generation
+              3
+              1
+            
+            
+              CC2G
+              Capture/compare 2
+              generation
+              2
+              1
+            
+            
+              CC1G
+              Capture/compare 1
+              generation
+              1
+              1
+            
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CCMR1_Output
+          CCMR1_Output
+          capture/compare mode register 1 (output
+          mode)
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC2CE
+              Output compare 2 clear
+              enable
+              15
+              1
+            
+            
+              OC2M
+              Output compare 2 mode
+              12
+              3
+            
+            
+              OC2PE
+              Output compare 2 preload
+              enable
+              11
+              1
+            
+            
+              OC2FE
+              Output compare 2 fast
+              enable
+              10
+              1
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              OC1CE
+              Output compare 1 clear
+              enable
+              7
+              1
+            
+            
+              OC1M
+              Output compare 1 mode
+              4
+              3
+            
+            
+              OC1PE
+              Output compare 1 preload
+              enable
+              3
+              1
+            
+            
+              OC1FE
+              Output compare 1 fast
+              enable
+              2
+              1
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR1_Input
+          CCMR1_Input
+          capture/compare mode register 1 (input
+          mode)
+          CCMR1_Output
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC2F
+              Input capture 2 filter
+              12
+              4
+            
+            
+              IC2PSC
+              Input capture 2 prescaler
+              10
+              2
+            
+            
+              CC2S
+              Capture/compare 2
+              selection
+              8
+              2
+            
+            
+              IC1F
+              Input capture 1 filter
+              4
+              4
+            
+            
+              IC1PSC
+              Input capture 1 prescaler
+              2
+              2
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR2_Output
+          CCMR2_Output
+          capture/compare mode register 2 (output
+          mode)
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC4CE
+              Output compare 4 clear
+              enable
+              15
+              1
+            
+            
+              OC4M
+              Output compare 4 mode
+              12
+              3
+            
+            
+              OC4PE
+              Output compare 4 preload
+              enable
+              11
+              1
+            
+            
+              OC4FE
+              Output compare 4 fast
+              enable
+              10
+              1
+            
+            
+              CC4S
+              Capture/Compare 4
+              selection
+              8
+              2
+            
+            
+              OC3CE
+              Output compare 3 clear
+              enable
+              7
+              1
+            
+            
+              OC3M
+              Output compare 3 mode
+              4
+              3
+            
+            
+              OC3PE
+              Output compare 3 preload
+              enable
+              3
+              1
+            
+            
+              OC3FE
+              Output compare 3 fast
+              enable
+              2
+              1
+            
+            
+              CC3S
+              Capture/Compare 3
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR2_Input
+          CCMR2_Input
+          capture/compare mode register 2 (input
+          mode)
+          CCMR2_Output
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC4F
+              Input capture 4 filter
+              12
+              4
+            
+            
+              IC4PSC
+              Input capture 4 prescaler
+              10
+              2
+            
+            
+              CC4S
+              Capture/Compare 4
+              selection
+              8
+              2
+            
+            
+              IC3F
+              Input capture 3 filter
+              4
+              4
+            
+            
+              IC3PSC
+              Input capture 3 prescaler
+              2
+              2
+            
+            
+              CC3S
+              Capture/Compare 3
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCER
+          CCER
+          capture/compare enable
+          register
+          0x20
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC4NP
+              Capture/Compare 4 output
+              Polarity
+              15
+              1
+            
+            
+              CC4P
+              Capture/Compare 3 output
+              Polarity
+              13
+              1
+            
+            
+              CC4E
+              Capture/Compare 4 output
+              enable
+              12
+              1
+            
+            
+              CC3NP
+              Capture/Compare 3 output
+              Polarity
+              11
+              1
+            
+            
+              CC3P
+              Capture/Compare 3 output
+              Polarity
+              9
+              1
+            
+            
+              CC3E
+              Capture/Compare 3 output
+              enable
+              8
+              1
+            
+            
+              CC2NP
+              Capture/Compare 2 output
+              Polarity
+              7
+              1
+            
+            
+              CC2P
+              Capture/Compare 2 output
+              Polarity
+              5
+              1
+            
+            
+              CC2E
+              Capture/Compare 2 output
+              enable
+              4
+              1
+            
+            
+              CC1NP
+              Capture/Compare 1 output
+              Polarity
+              3
+              1
+            
+            
+              CC1P
+              Capture/Compare 1 output
+              Polarity
+              1
+              1
+            
+            
+              CC1E
+              Capture/Compare 1 output
+              enable
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT_H
+              High counter value (TIM2
+              only)
+              16
+              16
+            
+            
+              CNT_L
+              Low counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR_H
+              High Auto-reload value (TIM2
+              only)
+              16
+              16
+            
+            
+              ARR_L
+              Low Auto-reload value
+              0
+              16
+            
+          
+        
+        
+          CCR1
+          CCR1
+          capture/compare register 1
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR1_H
+              High Capture/Compare 1 value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR1_L
+              Low Capture/Compare 1
+              value
+              0
+              16
+            
+          
+        
+        
+          CCR2
+          CCR2
+          capture/compare register 2
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR2_H
+              High Capture/Compare 2 value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR2_L
+              Low Capture/Compare 2
+              value
+              0
+              16
+            
+          
+        
+        
+          CCR3
+          CCR3
+          capture/compare register 3
+          0x3C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR3_H
+              High Capture/Compare value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR3_L
+              Low Capture/Compare value
+              0
+              16
+            
+          
+        
+        
+          CCR4
+          CCR4
+          capture/compare register 4
+          0x40
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR4_H
+              High Capture/Compare value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR4_L
+              Low Capture/Compare value
+              0
+              16
+            
+          
+        
+        
+          DCR
+          DCR
+          DMA control register
+          0x48
+          0x20
+          read-write
+          0x0000
+          
+            
+              DBL
+              DMA burst length
+              8
+              5
+            
+            
+              DBA
+              DMA base address
+              0
+              5
+            
+          
+        
+        
+          DMAR
+          DMAR
+          DMA address for full transfer
+          0x4C
+          0x20
+          read-write
+          0x0000
+          
+            
+              DMAB
+              DMA register for burst
+              accesses
+              0
+              16
+            
+          
+        
+        
+          OR
+          OR
+          TIM2 option register
+          0x50
+          0x20
+          read-write
+          0x0000
+          
+            
+              ETR_RMP
+              Timer2 ETR remap
+              0
+              3
+            
+            
+              TI4_RMP
+              Internal trigger
+              3
+              2
+            
+          
+        
+      
+    
+    
+      TIM3
+      0x40000400
+      
+        TIM2
+        TIM2 global interrupt
+        15
+      
+    
+    
+      TIM6
+      Basic-timers
+      TIM
+      0x40001000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM3
+        TIM3 global interrupt
+        16
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              UDE
+              Update DMA request enable
+              8
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT
+              Low counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR
+              Low Auto-reload value
+              0
+              16
+            
+          
+        
+      
+    
+    
+      TIM7
+      0x40001400
+      
+        TIM6_DAC
+        TIM6 global interrupt and DAC
+        17
+      
+    
+    
+      TIM21
+      General-purpose-timers
+      TIM
+      0x40010800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM7
+        TIM7 global interrupt and DAC
+        18
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              DIR
+              Direction
+              4
+              1
+            
+            
+              CMS
+              Center-aligned mode
+              selection
+              5
+              2
+            
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              CKD
+              Clock division
+              8
+              2
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+          
+        
+        
+          SMCR
+          SMCR
+          slave mode control register
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              SMS
+              Slave mode selection
+              0
+              3
+            
+            
+              TS
+              Trigger selection
+              4
+              3
+            
+            
+              MSM
+              Master/Slave mode
+              7
+              1
+            
+            
+              ETF
+              External trigger filter
+              8
+              4
+            
+            
+              ETPS
+              External trigger prescaler
+              12
+              2
+            
+            
+              ECE
+              External clock enable
+              14
+              1
+            
+            
+              ETP
+              External trigger polarity
+              15
+              1
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              TIE
+              Trigger interrupt enable
+              6
+              1
+            
+            
+              CC2IE
+              Capture/Compare 2 interrupt
+              enable
+              2
+              1
+            
+            
+              CC1IE
+              Capture/Compare 1 interrupt
+              enable
+              1
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2OF
+              Capture/compare 2 overcapture
+              flag
+              10
+              1
+            
+            
+              CC1OF
+              Capture/Compare 1 overcapture
+              flag
+              9
+              1
+            
+            
+              TIF
+              Trigger interrupt flag
+              6
+              1
+            
+            
+              CC2IF
+              Capture/Compare 2 interrupt
+              flag
+              2
+              1
+            
+            
+              CC1IF
+              Capture/compare 1 interrupt
+              flag
+              1
+              1
+            
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              TG
+              Trigger generation
+              6
+              1
+            
+            
+              CC2G
+              Capture/compare 2
+              generation
+              2
+              1
+            
+            
+              CC1G
+              Capture/compare 1
+              generation
+              1
+              1
+            
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CCMR1_Output
+          CCMR1_Output
+          capture/compare mode register (output
+          mode)
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC2M
+              Output Compare 2 mode
+              12
+              3
+            
+            
+              OC2PE
+              Output Compare 2 preload
+              enable
+              11
+              1
+            
+            
+              OC2FE
+              Output Compare 2 fast
+              enable
+              10
+              1
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              OC1M
+              Output Compare 1 mode
+              4
+              3
+            
+            
+              OC1PE
+              Output Compare 1 preload
+              enable
+              3
+              1
+            
+            
+              OC1FE
+              Output Compare 1 fast
+              enable
+              2
+              1
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR1_Input
+          CCMR1_Input
+          capture/compare mode register 1 (input
+          mode)
+          CCMR1_Output
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC2F
+              Input capture 2 filter
+              12
+              4
+            
+            
+              IC2PSC
+              Input capture 2 prescaler
+              10
+              2
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              IC1F
+              Input capture 1 filter
+              4
+              4
+            
+            
+              IC1PSC
+              Input capture 1 prescaler
+              2
+              2
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCER
+          CCER
+          capture/compare enable
+          register
+          0x20
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2NP
+              Capture/Compare 2 output
+              Polarity
+              7
+              1
+            
+            
+              CC2P
+              Capture/Compare 2 output
+              Polarity
+              5
+              1
+            
+            
+              CC2E
+              Capture/Compare 2 output
+              enable
+              4
+              1
+            
+            
+              CC1NP
+              Capture/Compare 1 output
+              Polarity
+              3
+              1
+            
+            
+              CC1P
+              Capture/Compare 1 output
+              Polarity
+              1
+              1
+            
+            
+              CC1E
+              Capture/Compare 1 output
+              enable
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT
+              counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR
+              Auto-reload value
+              0
+              16
+            
+          
+        
+        
+          CCR1
+          CCR1
+          capture/compare register 1
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR1
+              Capture/Compare 1 value
+              0
+              16
+            
+          
+        
+        
+          CCR2
+          CCR2
+          capture/compare register 2
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR2
+              Capture/Compare 2 value
+              0
+              16
+            
+          
+        
+        
+          OR
+          OR
+          TIM21 option register
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ETR_RMP
+              Timer21 ETR remap
+              0
+              2
+            
+            
+              TI1_RMP
+              Timer21 TI1
+              2
+              3
+            
+            
+              TI2_RMP
+              Timer21 TI2
+              5
+              1
+            
+          
+        
+      
+    
+    
+      TIM22
+      General-purpose-timers
+      TIM
+      0x40011400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM21
+        TIMER21 global interrupt
+        20
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              DIR
+              Direction
+              4
+              1
+            
+            
+              CMS
+              Center-aligned mode
+              selection
+              5
+              2
+            
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              CKD
+              Clock division
+              8
+              2
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+          
+        
+        
+          SMCR
+          SMCR
+          slave mode control register
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              SMS
+              Slave mode selection
+              0
+              3
+            
+            
+              TS
+              Trigger selection
+              4
+              3
+            
+            
+              MSM
+              Master/Slave mode
+              7
+              1
+            
+            
+              ETF
+              External trigger filter
+              8
+              4
+            
+            
+              ETPS
+              External trigger prescaler
+              12
+              2
+            
+            
+              ECE
+              External clock enable
+              14
+              1
+            
+            
+              ETP
+              External trigger polarity
+              15
+              1
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              TIE
+              Trigger interrupt enable
+              6
+              1
+            
+            
+              CC2IE
+              Capture/Compare 2 interrupt
+              enable
+              2
+              1
+            
+            
+              CC1IE
+              Capture/Compare 1 interrupt
+              enable
+              1
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2OF
+              Capture/compare 2 overcapture
+              flag
+              10
+              1
+            
+            
+              CC1OF
+              Capture/Compare 1 overcapture
+              flag
+              9
+              1
+            
+            
+              TIF
+              Trigger interrupt flag
+              6
+              1
+            
+            
+              CC2IF
+              Capture/Compare 2 interrupt
+              flag
+              2
+              1
+            
+            
+              CC1IF
+              Capture/compare 1 interrupt
+              flag
+              1
+              1
+            
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              TG
+              Trigger generation
+              6
+              1
+            
+            
+              CC2G
+              Capture/compare 2
+              generation
+              2
+              1
+            
+            
+              CC1G
+              Capture/compare 1
+              generation
+              1
+              1
+            
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CCMR1_Output
+          CCMR1_Output
+          capture/compare mode register (output
+          mode)
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC2M
+              Output Compare 2 mode
+              12
+              3
+            
+            
+              OC2PE
+              Output Compare 2 preload
+              enable
+              11
+              1
+            
+            
+              OC2FE
+              Output Compare 2 fast
+              enable
+              10
+              1
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              OC1M
+              Output Compare 1 mode
+              4
+              3
+            
+            
+              OC1PE
+              Output Compare 1 preload
+              enable
+              3
+              1
+            
+            
+              OC1FE
+              Output Compare 1 fast
+              enable
+              2
+              1
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR1_Input
+          CCMR1_Input
+          capture/compare mode register 1 (input
+          mode)
+          CCMR1_Output
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC2F
+              Input capture 2 filter
+              12
+              4
+            
+            
+              IC2PSC
+              Input capture 2 prescaler
+              10
+              2
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              IC1F
+              Input capture 1 filter
+              4
+              4
+            
+            
+              IC1PSC
+              Input capture 1 prescaler
+              2
+              2
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCER
+          CCER
+          capture/compare enable
+          register
+          0x20
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2NP
+              Capture/Compare 2 output
+              Polarity
+              7
+              1
+            
+            
+              CC2P
+              Capture/Compare 2 output
+              Polarity
+              5
+              1
+            
+            
+              CC2E
+              Capture/Compare 2 output
+              enable
+              4
+              1
+            
+            
+              CC1NP
+              Capture/Compare 1 output
+              Polarity
+              3
+              1
+            
+            
+              CC1P
+              Capture/Compare 1 output
+              Polarity
+              1
+              1
+            
+            
+              CC1E
+              Capture/Compare 1 output
+              enable
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT
+              counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR
+              Auto-reload value
+              0
+              16
+            
+          
+        
+        
+          CCR1
+          CCR1
+          capture/compare register 1
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR1
+              Capture/Compare 1 value
+              0
+              16
+            
+          
+        
+        
+          CCR2
+          CCR2
+          capture/compare register 2
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR2
+              Capture/Compare 2 value
+              0
+              16
+            
+          
+        
+        
+          OR
+          OR
+          TIM22 option register
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ETR_RMP
+              Timer22 ETR remap
+              0
+              2
+            
+            
+              TI1_RMP
+              Timer22 TI1
+              2
+              2
+            
+          
+        
+      
+    
+    
+      LPUSART1
+      Universal synchronous asynchronous receiver
+      transmitter
+      USART
+      0x40004800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM22
+        TIMER22 global interrupt
+        22
+      
+      
+        
+          CR1
+          CR1
+          Control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              M1
+              Word length
+              28
+              1
+            
+            
+              DEAT4
+              Driver Enable assertion
+              time
+              25
+              1
+            
+            
+              DEAT3
+              DEAT3
+              24
+              1
+            
+            
+              DEAT2
+              DEAT2
+              23
+              1
+            
+            
+              DEAT1
+              DEAT1
+              22
+              1
+            
+            
+              DEAT0
+              DEAT0
+              21
+              1
+            
+            
+              DEDT4
+              Driver Enable de-assertion
+              time
+              20
+              1
+            
+            
+              DEDT3
+              DEDT3
+              19
+              1
+            
+            
+              DEDT2
+              DEDT2
+              18
+              1
+            
+            
+              DEDT1
+              DEDT1
+              17
+              1
+            
+            
+              DEDT0
+              DEDT0
+              16
+              1
+            
+            
+              CMIE
+              Character match interrupt
+              enable
+              14
+              1
+            
+            
+              MME
+              Mute mode enable
+              13
+              1
+            
+            
+              M0
+              Word length
+              12
+              1
+            
+            
+              WAKE
+              Receiver wakeup method
+              11
+              1
+            
+            
+              PCE
+              Parity control enable
+              10
+              1
+            
+            
+              PS
+              Parity selection
+              9
+              1
+            
+            
+              PEIE
+              PE interrupt enable
+              8
+              1
+            
+            
+              TXEIE
+              interrupt enable
+              7
+              1
+            
+            
+              TCIE
+              Transmission complete interrupt
+              enable
+              6
+              1
+            
+            
+              RXNEIE
+              RXNE interrupt enable
+              5
+              1
+            
+            
+              IDLEIE
+              IDLE interrupt enable
+              4
+              1
+            
+            
+              TE
+              Transmitter enable
+              3
+              1
+            
+            
+              RE
+              Receiver enable
+              2
+              1
+            
+            
+              UESM
+              USART enable in Stop mode
+              1
+              1
+            
+            
+              UE
+              USART enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          Control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              ADD4_7
+              Address of the USART node
+              28
+              4
+            
+            
+              ADD0_3
+              Address of the USART node
+              24
+              4
+            
+            
+              MSBFIRST
+              Most significant bit first
+              19
+              1
+            
+            
+              TAINV
+              Binary data inversion
+              18
+              1
+            
+            
+              TXINV
+              TX pin active level
+              inversion
+              17
+              1
+            
+            
+              RXINV
+              RX pin active level
+              inversion
+              16
+              1
+            
+            
+              SWAP
+              Swap TX/RX pins
+              15
+              1
+            
+            
+              STOP
+              STOP bits
+              12
+              2
+            
+            
+              CLKEN
+              Clock enable
+              11
+              1
+            
+            
+              ADDM7
+              7-bit Address Detection/4-bit Address
+              Detection
+              4
+              1
+            
+          
+        
+        
+          CR3
+          CR3
+          Control register 3
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              WUFIE
+              Wakeup from Stop mode interrupt
+              enable
+              22
+              1
+            
+            
+              WUS
+              Wakeup from Stop mode interrupt flag
+              selection
+              20
+              2
+            
+            
+              DEP
+              Driver enable polarity
+              selection
+              15
+              1
+            
+            
+              DEM
+              Driver enable mode
+              14
+              1
+            
+            
+              DDRE
+              DMA Disable on Reception
+              Error
+              13
+              1
+            
+            
+              OVRDIS
+              Overrun Disable
+              12
+              1
+            
+            
+              CTSIE
+              CTS interrupt enable
+              10
+              1
+            
+            
+              CTSE
+              CTS enable
+              9
+              1
+            
+            
+              RTSE
+              RTS enable
+              8
+              1
+            
+            
+              DMAT
+              DMA enable transmitter
+              7
+              1
+            
+            
+              DMAR
+              DMA enable receiver
+              6
+              1
+            
+            
+              HDSEL
+              Half-duplex selection
+              3
+              1
+            
+            
+              EIE
+              Error interrupt enable
+              0
+              1
+            
+          
+        
+        
+          BRR
+          BRR
+          Baud rate register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              BRR
+              BRR
+              0
+              20
+            
+          
+        
+        
+          RQR
+          RQR
+          Request register
+          0x18
+          0x20
+          write-only
+          0x0000
+          
+            
+              RXFRQ
+              Receive data flush request
+              3
+              1
+            
+            
+              MMRQ
+              Mute mode request
+              2
+              1
+            
+            
+              SBKRQ
+              Send break request
+              1
+              1
+            
+          
+        
+        
+          ISR
+          ISR
+          Interrupt & status
+          register
+          0x1C
+          0x20
+          read-only
+          0x00C0
+          
+            
+              REACK
+              REACK
+              22
+              1
+            
+            
+              TEACK
+              TEACK
+              21
+              1
+            
+            
+              WUF
+              WUF
+              20
+              1
+            
+            
+              RWU
+              RWU
+              19
+              1
+            
+            
+              SBKF
+              SBKF
+              18
+              1
+            
+            
+              CMF
+              CMF
+              17
+              1
+            
+            
+              BUSY
+              BUSY
+              16
+              1
+            
+            
+              CTS
+              CTS
+              10
+              1
+            
+            
+              CTSIF
+              CTSIF
+              9
+              1
+            
+            
+              TXE
+              TXE
+              7
+              1
+            
+            
+              TC
+              TC
+              6
+              1
+            
+            
+              RXNE
+              RXNE
+              5
+              1
+            
+            
+              IDLE
+              IDLE
+              4
+              1
+            
+            
+              ORE
+              ORE
+              3
+              1
+            
+            
+              NF
+              NF
+              2
+              1
+            
+            
+              FE
+              FE
+              1
+              1
+            
+            
+              PE
+              PE
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt flag clear register
+          0x20
+          0x20
+          write-only
+          0x0000
+          
+            
+              WUCF
+              Wakeup from Stop mode clear
+              flag
+              20
+              1
+            
+            
+              CMCF
+              Character match clear flag
+              17
+              1
+            
+            
+              CTSCF
+              CTS clear flag
+              9
+              1
+            
+            
+              TCCF
+              Transmission complete clear
+              flag
+              6
+              1
+            
+            
+              IDLECF
+              Idle line detected clear
+              flag
+              4
+              1
+            
+            
+              ORECF
+              Overrun error clear flag
+              3
+              1
+            
+            
+              NCF
+              Noise detected clear flag
+              2
+              1
+            
+            
+              FECF
+              Framing error clear flag
+              1
+              1
+            
+            
+              PECF
+              Parity error clear flag
+              0
+              1
+            
+          
+        
+        
+          RDR
+          RDR
+          Receive data register
+          0x24
+          0x20
+          read-only
+          0x0000
+          
+            
+              RDR
+              Receive data value
+              0
+              9
+            
+          
+        
+        
+          TDR
+          TDR
+          Transmit data register
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              TDR
+              Transmit data value
+              0
+              9
+            
+          
+        
+      
+    
+    
+      NVIC
+      Nested Vectored Interrupt
+      Controller
+      NVIC
+      0xE000E100
+      
+        0x0
+        0x33D
+        registers
+      
+      
+        
+          ISER
+          ISER
+          Interrupt Set Enable Register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SETENA
+              SETENA
+              0
+              32
+            
+          
+        
+        
+          ICER
+          ICER
+          Interrupt Clear Enable
+          Register
+          0x80
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CLRENA
+              CLRENA
+              0
+              32
+            
+          
+        
+        
+          ISPR
+          ISPR
+          Interrupt Set-Pending Register
+          0x100
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SETPEND
+              SETPEND
+              0
+              32
+            
+          
+        
+        
+          ICPR
+          ICPR
+          Interrupt Clear-Pending
+          Register
+          0x180
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CLRPEND
+              CLRPEND
+              0
+              32
+            
+          
+        
+        
+          IPR0
+          IPR0
+          Interrupt Priority Register 0
+          0x300
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_0
+              priority for interrupt 0
+              0
+              8
+            
+            
+              PRI_1
+              priority for interrupt 1
+              8
+              8
+            
+            
+              PRI_2
+              priority for interrupt 2
+              16
+              8
+            
+            
+              PRI_3
+              priority for interrupt 3
+              24
+              8
+            
+          
+        
+        
+          IPR1
+          IPR1
+          Interrupt Priority Register 1
+          0x304
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_4
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_5
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_6
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_7
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR2
+          IPR2
+          Interrupt Priority Register 2
+          0x308
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_8
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_9
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_10
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_11
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR3
+          IPR3
+          Interrupt Priority Register 3
+          0x30C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_12
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_13
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_14
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_15
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR4
+          IPR4
+          Interrupt Priority Register 4
+          0x310
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_16
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_17
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_18
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_19
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR5
+          IPR5
+          Interrupt Priority Register 5
+          0x314
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_20
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_21
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_22
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_23
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR6
+          IPR6
+          Interrupt Priority Register 6
+          0x318
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_24
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_25
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_26
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_27
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR7
+          IPR7
+          Interrupt Priority Register 7
+          0x31C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_28
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_29
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_30
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_31
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+      
+    
+    
+      USB_SRAM
+      Universal serial bus full-speed device
+      interface
+      USB
+      0x40006000
+      
+        0x0
+        0x800
+        registers
+      
+      
+        
+          EP0R
+          EP0R
+          endpoint 0 register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP1R
+          EP1R
+          endpoint 1 register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP2R
+          EP2R
+          endpoint 2 register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP3R
+          EP3R
+          endpoint 3 register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP4R
+          EP4R
+          endpoint 4 register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP5R
+          EP5R
+          endpoint 5 register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP6R
+          EP6R
+          endpoint 6 register
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP7R
+          EP7R
+          endpoint 7 register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          CNTR
+          CNTR
+          control register
+          0x40
+          0x20
+          read-write
+          0x00000003
+          
+            
+              FRES
+              Force USB Reset
+              0
+              1
+            
+            
+              PDWN
+              Power down
+              1
+              1
+            
+            
+              LPMODE
+              Low-power mode
+              2
+              1
+            
+            
+              FSUSP
+              Force suspend
+              3
+              1
+            
+            
+              RESUME
+              Resume request
+              4
+              1
+            
+            
+              L1RESUME
+              LPM L1 Resume request
+              5
+              1
+            
+            
+              L1REQM
+              LPM L1 state request interrupt
+              mask
+              7
+              1
+            
+            
+              ESOFM
+              Expected start of frame interrupt
+              mask
+              8
+              1
+            
+            
+              SOFM
+              Start of frame interrupt
+              mask
+              9
+              1
+            
+            
+              RESETM
+              USB reset interrupt mask
+              10
+              1
+            
+            
+              SUSPM
+              Suspend mode interrupt
+              mask
+              11
+              1
+            
+            
+              WKUPM
+              Wakeup interrupt mask
+              12
+              1
+            
+            
+              ERRM
+              Error interrupt mask
+              13
+              1
+            
+            
+              PMAOVRM
+              Packet memory area over / underrun
+              interrupt mask
+              14
+              1
+            
+            
+              CTRM
+              Correct transfer interrupt
+              mask
+              15
+              1
+            
+          
+        
+        
+          ISTR
+          ISTR
+          interrupt status register
+          0x44
+          0x20
+          0x00000000
+          
+            
+              EP_ID
+              Endpoint Identifier
+              0
+              4
+              read-only
+            
+            
+              DIR
+              Direction of transaction
+              4
+              1
+              read-only
+            
+            
+              L1REQ
+              LPM L1 state request
+              7
+              1
+              read-write
+            
+            
+              ESOF
+              Expected start frame
+              8
+              1
+              read-write
+            
+            
+              SOF
+              start of frame
+              9
+              1
+              read-write
+            
+            
+              RESET
+              reset request
+              10
+              1
+              read-write
+            
+            
+              SUSP
+              Suspend mode request
+              11
+              1
+              read-write
+            
+            
+              WKUP
+              Wakeup
+              12
+              1
+              read-write
+            
+            
+              ERR
+              Error
+              13
+              1
+              read-write
+            
+            
+              PMAOVR
+              Packet memory area over /
+              underrun
+              14
+              1
+              read-write
+            
+            
+              CTR
+              Correct transfer
+              15
+              1
+              read-only
+            
+          
+        
+        
+          FNR
+          FNR
+          frame number register
+          0x48
+          0x20
+          read-only
+          0x0000
+          
+            
+              FN
+              Frame number
+              0
+              11
+            
+            
+              LSOF
+              Lost SOF
+              11
+              2
+            
+            
+              LCK
+              Locked
+              13
+              1
+            
+            
+              RXDM
+              Receive data - line status
+              14
+              1
+            
+            
+              RXDP
+              Receive data + line status
+              15
+              1
+            
+          
+        
+        
+          DADDR
+          DADDR
+          device address
+          0x4C
+          0x20
+          read-write
+          0x0000
+          
+            
+              ADD
+              Device address
+              0
+              7
+            
+            
+              EF
+              Enable function
+              7
+              1
+            
+          
+        
+        
+          BTABLE
+          BTABLE
+          Buffer table address
+          0x50
+          0x20
+          read-write
+          0x0000
+          
+            
+              BTABLE
+              Buffer table
+              3
+              13
+            
+          
+        
+        
+          LPMCSR
+          LPMCSR
+          LPM control and status
+          register
+          0x54
+          0x20
+          0x0000
+          
+            
+              LPMEN
+              LPM support enable
+              0
+              1
+              read-write
+            
+            
+              LPMACK
+              LPM Token acknowledge
+              enable
+              1
+              1
+              read-write
+            
+            
+              REMWAKE
+              bRemoteWake value
+              3
+              1
+              read-only
+            
+            
+              BESL
+              BESL value
+              4
+              4
+              read-only
+            
+          
+        
+        
+          BCDR
+          BCDR
+          Battery charging detector
+          0x58
+          0x20
+          0x0000
+          
+            
+              BCDEN
+              Battery charging detector
+              0
+              1
+              read-write
+            
+            
+              DCDEN
+              Data contact detection
+              1
+              1
+              read-write
+            
+            
+              PDEN
+              Primary detection
+              2
+              1
+              read-write
+            
+            
+              SDEN
+              Secondary detection
+              3
+              1
+              read-write
+            
+            
+              DCDET
+              Data contact detection
+              4
+              1
+              read-only
+            
+            
+              PDET
+              Primary detection
+              5
+              1
+              read-only
+            
+            
+              SDET
+              Secondary detection
+              6
+              1
+              read-only
+            
+            
+              PS2DET
+              DM pull-up detection
+              status
+              7
+              1
+              read-only
+            
+            
+              DPPU
+              DP pull-up control
+              15
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      MPU
+      Memory protection unit
+      MPU
+      0xE000ED90
+      
+        0x0
+        0x15
+        registers
+      
+      
+        
+          MPU_TYPER
+          MPU_TYPER
+          MPU type register
+          0x0
+          0x20
+          read-only
+          0X00000800
+          
+            
+              SEPARATE
+              Separate flag
+              0
+              1
+            
+            
+              DREGION
+              Number of MPU data regions
+              8
+              8
+            
+            
+              IREGION
+              Number of MPU instruction
+              regions
+              16
+              8
+            
+          
+        
+        
+          MPU_CTRL
+          MPU_CTRL
+          MPU control register
+          0x4
+          0x20
+          read-only
+          0X00000000
+          
+            
+              ENABLE
+              Enables the MPU
+              0
+              1
+            
+            
+              HFNMIENA
+              Enables the operation of MPU during hard
+              fault
+              1
+              1
+            
+            
+              PRIVDEFENA
+              Enable priviliged software access to
+              default memory map
+              2
+              1
+            
+          
+        
+        
+          MPU_RNR
+          MPU_RNR
+          MPU region number register
+          0x8
+          0x20
+          read-write
+          0X00000000
+          
+            
+              REGION
+              MPU region
+              0
+              8
+            
+          
+        
+        
+          MPU_RBAR
+          MPU_RBAR
+          MPU region base address
+          register
+          0xC
+          0x20
+          read-write
+          0X00000000
+          
+            
+              REGION
+              MPU region field
+              0
+              4
+            
+            
+              VALID
+              MPU region number valid
+              4
+              1
+            
+            
+              ADDR
+              Region base address field
+              5
+              27
+            
+          
+        
+        
+          MPU_RASR
+          MPU_RASR
+          MPU region attribute and size
+          register
+          0x10
+          0x20
+          read-write
+          0X00000000
+          
+            
+              ENABLE
+              Region enable bit.
+              0
+              1
+            
+            
+              SIZE
+              Size of the MPU protection
+              region
+              1
+              5
+            
+            
+              SRD
+              Subregion disable bits
+              8
+              8
+            
+            
+              B
+              memory attribute
+              16
+              1
+            
+            
+              C
+              memory attribute
+              17
+              1
+            
+            
+              S
+              Shareable memory attribute
+              18
+              1
+            
+            
+              TEX
+              memory attribute
+              19
+              3
+            
+            
+              AP
+              Access permission
+              24
+              3
+            
+            
+              XN
+              Instruction access disable
+              bit
+              28
+              1
+            
+          
+        
+      
+    
+    
+      STK
+      SysTick timer
+      STK
+      0xE000E010
+      
+        0x0
+        0x11
+        registers
+      
+      
+        
+          CSR
+          CSR
+          SysTick control and status
+          register
+          0x0
+          0x20
+          read-write
+          0X00000000
+          
+            
+              ENABLE
+              Counter enable
+              0
+              1
+            
+            
+              TICKINT
+              SysTick exception request
+              enable
+              1
+              1
+            
+            
+              CLKSOURCE
+              Clock source selection
+              2
+              1
+            
+            
+              COUNTFLAG
+              COUNTFLAG
+              16
+              1
+            
+          
+        
+        
+          RVR
+          RVR
+          SysTick reload value register
+          0x4
+          0x20
+          read-write
+          0X00000000
+          
+            
+              RELOAD
+              RELOAD value
+              0
+              24
+            
+          
+        
+        
+          CVR
+          CVR
+          SysTick current value register
+          0x8
+          0x20
+          read-write
+          0X00000000
+          
+            
+              CURRENT
+              Current counter value
+              0
+              24
+            
+          
+        
+        
+          CALIB
+          CALIB
+          SysTick calibration value
+          register
+          0xC
+          0x20
+          read-write
+          0X00000000
+          
+            
+              TENMS
+              Calibration value
+              0
+              24
+            
+            
+              SKEW
+              SKEW flag: Indicates whether the TENMS
+              value is exact
+              30
+              1
+            
+            
+              NOREF
+              NOREF flag. Reads as zero
+              31
+              1
+            
+          
+        
+      
+    
+    
+      SCB
+      System control block
+      SCB
+      0xE000ED00
+      
+        0x0
+        0x41
+        registers
+      
+      
+        
+          CPUID
+          CPUID
+          CPUID base register
+          0x0
+          0x20
+          read-only
+          0x410FC241
+          
+            
+              Revision
+              Revision number
+              0
+              4
+            
+            
+              PartNo
+              Part number of the
+              processor
+              4
+              12
+            
+            
+              Architecture
+              Reads as 0xF
+              16
+              4
+            
+            
+              Variant
+              Variant number
+              20
+              4
+            
+            
+              Implementer
+              Implementer code
+              24
+              8
+            
+          
+        
+        
+          ICSR
+          ICSR
+          Interrupt control and state
+          register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              VECTACTIVE
+              Active vector
+              0
+              9
+            
+            
+              RETTOBASE
+              Return to base level
+              11
+              1
+            
+            
+              VECTPENDING
+              Pending vector
+              12
+              7
+            
+            
+              ISRPENDING
+              Interrupt pending flag
+              22
+              1
+            
+            
+              PENDSTCLR
+              SysTick exception clear-pending
+              bit
+              25
+              1
+            
+            
+              PENDSTSET
+              SysTick exception set-pending
+              bit
+              26
+              1
+            
+            
+              PENDSVCLR
+              PendSV clear-pending bit
+              27
+              1
+            
+            
+              PENDSVSET
+              PendSV set-pending bit
+              28
+              1
+            
+            
+              NMIPENDSET
+              NMI set-pending bit.
+              31
+              1
+            
+          
+        
+        
+          VTOR
+          VTOR
+          Vector table offset register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TBLOFF
+              Vector table base offset
+              field
+              7
+              25
+            
+          
+        
+        
+          AIRCR
+          AIRCR
+          Application interrupt and reset control
+          register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              VECTCLRACTIVE
+              VECTCLRACTIVE
+              1
+              1
+            
+            
+              SYSRESETREQ
+              SYSRESETREQ
+              2
+              1
+            
+            
+              ENDIANESS
+              ENDIANESS
+              15
+              1
+            
+            
+              VECTKEYSTAT
+              Register key
+              16
+              16
+            
+          
+        
+        
+          SCR
+          SCR
+          System control register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SLEEPONEXIT
+              SLEEPONEXIT
+              1
+              1
+            
+            
+              SLEEPDEEP
+              SLEEPDEEP
+              2
+              1
+            
+            
+              SEVEONPEND
+              Send Event on Pending bit
+              4
+              1
+            
+          
+        
+        
+          CCR
+          CCR
+          Configuration and control
+          register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NONBASETHRDENA
+              Configures how the processor enters
+              Thread mode
+              0
+              1
+            
+            
+              USERSETMPEND
+              USERSETMPEND
+              1
+              1
+            
+            
+              UNALIGN__TRP
+              UNALIGN_ TRP
+              3
+              1
+            
+            
+              DIV_0_TRP
+              DIV_0_TRP
+              4
+              1
+            
+            
+              BFHFNMIGN
+              BFHFNMIGN
+              8
+              1
+            
+            
+              STKALIGN
+              STKALIGN
+              9
+              1
+            
+          
+        
+        
+          SHPR2
+          SHPR2
+          System handler priority
+          registers
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_11
+              Priority of system handler
+              11
+              24
+              8
+            
+          
+        
+        
+          SHPR3
+          SHPR3
+          System handler priority
+          registers
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_14
+              Priority of system handler
+              14
+              16
+              8
+            
+            
+              PRI_15
+              Priority of system handler
+              15
+              24
+              8
+            
+          
+        
+      
+    
+  
+
diff --git a/src/chips/STM32L0x3.svd b/src/chips/STM32L0x3.svd
new file mode 100644
index 000000000..f1282791c
--- /dev/null
+++ b/src/chips/STM32L0x3.svd
@@ -0,0 +1,22518 @@
+
+
+  STM32L0x3
+  1.3
+  STM32L0x3
+  
+  
+    CM0+
+    r0p0
+    little
+    false
+    false
+    3
+    false
+  
+  
+  
+  8
+  
+  32
+  
+  0x20
+  0x0
+  0xFFFFFFFF
+  
+    
+      AES
+      Advanced encryption standard hardware
+      accelerator
+      AES
+      0x40026000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        AES_RNG_LPUART1
+        AES global interrupt RNG global interrupt and
+        LPUART1 global interrupt through
+        29
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DMAOUTEN
+              Enable DMA management of data output
+              phase
+              12
+              1
+            
+            
+              DMAINEN
+              Enable DMA management of data input
+              phase
+              11
+              1
+            
+            
+              ERRIE
+              Error interrupt enable
+              10
+              1
+            
+            
+              CCFIE
+              CCF flag interrupt enable
+              9
+              1
+            
+            
+              ERRC
+              Error clear
+              8
+              1
+            
+            
+              CCFC
+              Computation Complete Flag
+              Clear
+              7
+              1
+            
+            
+              CHMOD
+              AES chaining mode
+              5
+              2
+            
+            
+              MODE
+              AES operating mode
+              3
+              2
+            
+            
+              DATATYPE
+              Data type selection (for data in and
+              data out to/from the cryptographic
+              block)
+              1
+              2
+            
+            
+              EN
+              AES enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x4
+          0x20
+          read-only
+          0x00000000
+          
+            
+              WRERR
+              Write error flag
+              2
+              1
+            
+            
+              RDERR
+              Read error flag
+              1
+              1
+            
+            
+              CCF
+              Computation complete flag
+              0
+              1
+            
+          
+        
+        
+          DINR
+          DINR
+          data input register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_DINR
+              Data Input Register.
+              0
+              32
+            
+          
+        
+        
+          DOUTR
+          DOUTR
+          data output register
+          0xC
+          0x20
+          read-only
+          0x00000000
+          
+            
+              AES_DOUTR
+              Data output register
+              0
+              32
+            
+          
+        
+        
+          KEYR0
+          KEYR0
+          key register 0
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR0
+              Data Output Register (LSB key
+              [31:0])
+              0
+              32
+            
+          
+        
+        
+          KEYR1
+          KEYR1
+          key register 1
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR1
+              AES key register (key
+              [63:32])
+              0
+              32
+            
+          
+        
+        
+          KEYR2
+          KEYR2
+          key register 2
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR2
+              AES key register (key
+              [95:64])
+              0
+              32
+            
+          
+        
+        
+          KEYR3
+          KEYR3
+          key register 3
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_KEYR3
+              AES key register (MSB key
+              [127:96])
+              0
+              32
+            
+          
+        
+        
+          IVR0
+          IVR0
+          initialization vector register
+          0
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR0
+              initialization vector register (LSB IVR
+              [31:0])
+              0
+              32
+            
+          
+        
+        
+          IVR1
+          IVR1
+          initialization vector register
+          1
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR1
+              Initialization Vector Register (IVR
+              [63:32])
+              0
+              32
+            
+          
+        
+        
+          IVR2
+          IVR2
+          initialization vector register
+          2
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR2
+              Initialization Vector Register (IVR
+              [95:64])
+              0
+              32
+            
+          
+        
+        
+          IVR3
+          IVR3
+          initialization vector register
+          3
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AES_IVR3
+              Initialization Vector Register (MSB IVR
+              [127:96])
+              0
+              32
+            
+          
+        
+      
+    
+    
+      DAC
+      Digital-to-analog converter
+      DAC
+      0x40007400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DMAUDRIE1
+              DAC channel1 DMA Underrun Interrupt
+              enable
+              13
+              1
+            
+            
+              DMAEN1
+              DAC channel1 DMA enable
+              12
+              1
+            
+            
+              MAMP1
+              DAC channel1 mask/amplitude
+              selector
+              8
+              4
+            
+            
+              WAVE1
+              DAC channel1 noise/triangle wave
+              generation enable
+              6
+              2
+            
+            
+              TSEL1
+              DAC channel1 trigger
+              selection
+              3
+              3
+            
+            
+              TEN1
+              DAC channel1 trigger
+              enable
+              2
+              1
+            
+            
+              BOFF1
+              DAC channel1 output buffer
+              disable
+              1
+              1
+            
+            
+              EN1
+              DAC channel1 enable
+              0
+              1
+            
+          
+        
+        
+          SWTRIGR
+          SWTRIGR
+          software trigger register
+          0x4
+          0x20
+          write-only
+          0x00000000
+          
+            
+              SWTRIG1
+              DAC channel1 software
+              trigger
+              0
+              1
+            
+          
+        
+        
+          DHR12R1
+          DHR12R1
+          channel1 12-bit right-aligned data holding
+          register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 12-bit right-aligned
+              data
+              0
+              12
+            
+          
+        
+        
+          DHR12L1
+          DHR12L1
+          channel1 12-bit left-aligned data holding
+          register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 12-bit left-aligned
+              data
+              4
+              12
+            
+          
+        
+        
+          DHR8R1
+          DHR8R1
+          channel1 8-bit right-aligned data holding
+          register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 8-bit right-aligned
+              data
+              0
+              8
+            
+          
+        
+        
+          DOR1
+          DOR1
+          channel1 data output register
+          0x2C
+          0x20
+          read-only
+          0x00000000
+          
+            
+              DACC1DOR
+              DAC channel1 data output
+              0
+              12
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DMAUDR1
+              DAC channel1 DMA underrun
+              flag
+              13
+              1
+            
+          
+        
+        
+          DHR12R2
+          DHR12R2
+          channel2 12-bit right-aligned data holding
+          register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC2DHR
+              DAC channel2 12-bit right-aligned
+              data
+              0
+              12
+            
+          
+        
+        
+          DHR12L2
+          DHR12L2
+          channel2 12-bit left-aligned data holding
+          register
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC2DHR
+              DAC channel2 12-bit left-aligned
+              data
+              4
+              12
+            
+          
+        
+        
+          DHR8R2
+          DHR8R2
+          channel2 8-bit right-aligned data holding
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC2DHR
+              DAC channel2 8-bit right-aligned
+              data
+              0
+              8
+            
+          
+        
+        
+          DHR12RD
+          DHR12RD
+          Dual DAC 12-bit right-aligned data holding
+          register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 12-bit right-aligned
+              data
+              0
+              12
+            
+            
+              DACC2DHR
+              DAC channel2 12-bit right-aligned
+              data
+              16
+              12
+            
+          
+        
+        
+          DHR12LD
+          DHR12LD
+          Dual DAC 12-bit left-aligned data holding
+          register
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 12-bit left-aligned
+              data
+              4
+              12
+            
+            
+              DACC2DHR
+              DAC channel2 12-bit left-aligned
+              data
+              20
+              12
+            
+          
+        
+        
+          DHR8RD
+          DHR8RD
+          Dual DAC 8-bit right-aligned data holding
+          register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DACC1DHR
+              DAC channel1 8-bit right-aligned
+              data
+              0
+              8
+            
+            
+              DACC2DHR
+              DAC channel2 8-bit right-aligned
+              data
+              8
+              8
+            
+          
+        
+        
+          DOR2
+          DOR2
+          channel2 data output register
+          0x30
+          0x20
+          read-only
+          0x00000000
+          
+            
+              DACC2DOR
+              DAC channel2 data output
+              0
+              12
+            
+          
+        
+      
+    
+    
+      DMA1
+      Direct memory access controller
+      DMA
+      0x40020000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        DMA1_Channel1
+        DMA1 Channel1 global interrupt
+        9
+      
+      
+        DMA1_Channel2_3
+        DMA1 Channel2 and 3 interrupts
+        10
+      
+      
+        DMA1_Channel4_7
+        DMA1 Channel4 to 7 interrupts
+        11
+      
+      
+        
+          ISR
+          ISR
+          interrupt status register
+          0x0
+          0x20
+          read-only
+          0x00000000
+          
+            
+              TEIF7
+              Channel x transfer error flag (x = 1
+              ..7)
+              27
+              1
+            
+            
+              HTIF7
+              Channel x half transfer flag (x = 1
+              ..7)
+              26
+              1
+            
+            
+              TCIF7
+              Channel x transfer complete flag (x = 1
+              ..7)
+              25
+              1
+            
+            
+              GIF7
+              Channel x global interrupt flag (x = 1
+              ..7)
+              24
+              1
+            
+            
+              TEIF6
+              Channel x transfer error flag (x = 1
+              ..7)
+              23
+              1
+            
+            
+              HTIF6
+              Channel x half transfer flag (x = 1
+              ..7)
+              22
+              1
+            
+            
+              TCIF6
+              Channel x transfer complete flag (x = 1
+              ..7)
+              21
+              1
+            
+            
+              GIF6
+              Channel x global interrupt flag (x = 1
+              ..7)
+              20
+              1
+            
+            
+              TEIF5
+              Channel x transfer error flag (x = 1
+              ..7)
+              19
+              1
+            
+            
+              HTIF5
+              Channel x half transfer flag (x = 1
+              ..7)
+              18
+              1
+            
+            
+              TCIF5
+              Channel x transfer complete flag (x = 1
+              ..7)
+              17
+              1
+            
+            
+              GIF5
+              Channel x global interrupt flag (x = 1
+              ..7)
+              16
+              1
+            
+            
+              TEIF4
+              Channel x transfer error flag (x = 1
+              ..7)
+              15
+              1
+            
+            
+              HTIF4
+              Channel x half transfer flag (x = 1
+              ..7)
+              14
+              1
+            
+            
+              TCIF4
+              Channel x transfer complete flag (x = 1
+              ..7)
+              13
+              1
+            
+            
+              GIF4
+              Channel x global interrupt flag (x = 1
+              ..7)
+              12
+              1
+            
+            
+              TEIF3
+              Channel x transfer error flag (x = 1
+              ..7)
+              11
+              1
+            
+            
+              HTIF3
+              Channel x half transfer flag (x = 1
+              ..7)
+              10
+              1
+            
+            
+              TCIF3
+              Channel x transfer complete flag (x = 1
+              ..7)
+              9
+              1
+            
+            
+              GIF3
+              Channel x global interrupt flag (x = 1
+              ..7)
+              8
+              1
+            
+            
+              TEIF2
+              Channel x transfer error flag (x = 1
+              ..7)
+              7
+              1
+            
+            
+              HTIF2
+              Channel x half transfer flag (x = 1
+              ..7)
+              6
+              1
+            
+            
+              TCIF2
+              Channel x transfer complete flag (x = 1
+              ..7)
+              5
+              1
+            
+            
+              GIF2
+              Channel x global interrupt flag (x = 1
+              ..7)
+              4
+              1
+            
+            
+              TEIF1
+              Channel x transfer error flag (x = 1
+              ..7)
+              3
+              1
+            
+            
+              HTIF1
+              Channel x half transfer flag (x = 1
+              ..7)
+              2
+              1
+            
+            
+              TCIF1
+              Channel x transfer complete flag (x = 1
+              ..7)
+              1
+              1
+            
+            
+              GIF1
+              Channel x global interrupt flag (x = 1
+              ..7)
+              0
+              1
+            
+          
+        
+        
+          IFCR
+          IFCR
+          interrupt flag clear register
+          0x4
+          0x20
+          write-only
+          0x00000000
+          
+            
+              CTEIF7
+              Channel x transfer error clear (x = 1
+              ..7)
+              27
+              1
+            
+            
+              CHTIF7
+              Channel x half transfer clear (x = 1
+              ..7)
+              26
+              1
+            
+            
+              CTCIF7
+              Channel x transfer complete clear (x = 1
+              ..7)
+              25
+              1
+            
+            
+              CGIF7
+              Channel x global interrupt clear (x = 1
+              ..7)
+              24
+              1
+            
+            
+              CTEIF6
+              Channel x transfer error clear (x = 1
+              ..7)
+              23
+              1
+            
+            
+              CHTIF6
+              Channel x half transfer clear (x = 1
+              ..7)
+              22
+              1
+            
+            
+              CTCIF6
+              Channel x transfer complete clear (x = 1
+              ..7)
+              21
+              1
+            
+            
+              CGIF6
+              Channel x global interrupt clear (x = 1
+              ..7)
+              20
+              1
+            
+            
+              CTEIF5
+              Channel x transfer error clear (x = 1
+              ..7)
+              19
+              1
+            
+            
+              CHTIF5
+              Channel x half transfer clear (x = 1
+              ..7)
+              18
+              1
+            
+            
+              CTCIF5
+              Channel x transfer complete clear (x = 1
+              ..7)
+              17
+              1
+            
+            
+              CGIF5
+              Channel x global interrupt clear (x = 1
+              ..7)
+              16
+              1
+            
+            
+              CTEIF4
+              Channel x transfer error clear (x = 1
+              ..7)
+              15
+              1
+            
+            
+              CHTIF4
+              Channel x half transfer clear (x = 1
+              ..7)
+              14
+              1
+            
+            
+              CTCIF4
+              Channel x transfer complete clear (x = 1
+              ..7)
+              13
+              1
+            
+            
+              CGIF4
+              Channel x global interrupt clear (x = 1
+              ..7)
+              12
+              1
+            
+            
+              CTEIF3
+              Channel x transfer error clear (x = 1
+              ..7)
+              11
+              1
+            
+            
+              CHTIF3
+              Channel x half transfer clear (x = 1
+              ..7)
+              10
+              1
+            
+            
+              CTCIF3
+              Channel x transfer complete clear (x = 1
+              ..7)
+              9
+              1
+            
+            
+              CGIF3
+              Channel x global interrupt clear (x = 1
+              ..7)
+              8
+              1
+            
+            
+              CTEIF2
+              Channel x transfer error clear (x = 1
+              ..7)
+              7
+              1
+            
+            
+              CHTIF2
+              Channel x half transfer clear (x = 1
+              ..7)
+              6
+              1
+            
+            
+              CTCIF2
+              Channel x transfer complete clear (x = 1
+              ..7)
+              5
+              1
+            
+            
+              CGIF2
+              Channel x global interrupt clear (x = 1
+              ..7)
+              4
+              1
+            
+            
+              CTEIF1
+              Channel x transfer error clear (x = 1
+              ..7)
+              3
+              1
+            
+            
+              CHTIF1
+              Channel x half transfer clear (x = 1
+              ..7)
+              2
+              1
+            
+            
+              CTCIF1
+              Channel x transfer complete clear (x = 1
+              ..7)
+              1
+              1
+            
+            
+              CGIF1
+              Channel x global interrupt clear (x = 1
+              ..7)
+              0
+              1
+            
+          
+        
+        
+          CCR1
+          CCR1
+          channel x configuration
+          register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR1
+          CNDTR1
+          channel x number of data
+          register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR1
+          CPAR1
+          channel x peripheral address
+          register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR1
+          CMAR1
+          channel x memory address
+          register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR2
+          CCR2
+          channel x configuration
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR2
+          CNDTR2
+          channel x number of data
+          register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR2
+          CPAR2
+          channel x peripheral address
+          register
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR2
+          CMAR2
+          channel x memory address
+          register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR3
+          CCR3
+          channel x configuration
+          register
+          0x30
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR3
+          CNDTR3
+          channel x number of data
+          register
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR3
+          CPAR3
+          channel x peripheral address
+          register
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR3
+          CMAR3
+          channel x memory address
+          register
+          0x3C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR4
+          CCR4
+          channel x configuration
+          register
+          0x44
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR4
+          CNDTR4
+          channel x number of data
+          register
+          0x48
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR4
+          CPAR4
+          channel x peripheral address
+          register
+          0x4C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR4
+          CMAR4
+          channel x memory address
+          register
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR5
+          CCR5
+          channel x configuration
+          register
+          0x58
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR5
+          CNDTR5
+          channel x number of data
+          register
+          0x5C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR5
+          CPAR5
+          channel x peripheral address
+          register
+          0x60
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR5
+          CMAR5
+          channel x memory address
+          register
+          0x64
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR6
+          CCR6
+          channel x configuration
+          register
+          0x6C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR6
+          CNDTR6
+          channel x number of data
+          register
+          0x70
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR6
+          CPAR6
+          channel x peripheral address
+          register
+          0x74
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR6
+          CMAR6
+          channel x memory address
+          register
+          0x78
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CCR7
+          CCR7
+          channel x configuration
+          register
+          0x80
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MEM2MEM
+              Memory to memory mode
+              14
+              1
+            
+            
+              PL
+              Channel priority level
+              12
+              2
+            
+            
+              MSIZE
+              Memory size
+              10
+              2
+            
+            
+              PSIZE
+              Peripheral size
+              8
+              2
+            
+            
+              MINC
+              Memory increment mode
+              7
+              1
+            
+            
+              PINC
+              Peripheral increment mode
+              6
+              1
+            
+            
+              CIRC
+              Circular mode
+              5
+              1
+            
+            
+              DIR
+              Data transfer direction
+              4
+              1
+            
+            
+              TEIE
+              Transfer error interrupt
+              enable
+              3
+              1
+            
+            
+              HTIE
+              Half transfer interrupt
+              enable
+              2
+              1
+            
+            
+              TCIE
+              Transfer complete interrupt
+              enable
+              1
+              1
+            
+            
+              EN
+              Channel enable
+              0
+              1
+            
+          
+        
+        
+          CNDTR7
+          CNDTR7
+          channel x number of data
+          register
+          0x84
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NDT
+              Number of data to transfer
+              0
+              16
+            
+          
+        
+        
+          CPAR7
+          CPAR7
+          channel x peripheral address
+          register
+          0x88
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PA
+              Peripheral address
+              0
+              32
+            
+          
+        
+        
+          CMAR7
+          CMAR7
+          channel x memory address
+          register
+          0x8C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MA
+              Memory address
+              0
+              32
+            
+          
+        
+        
+          CSELR
+          CSELR
+          channel selection register
+          0xA8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              C7S
+              DMA channel 7 selection
+              24
+              4
+            
+            
+              C6S
+              DMA channel 6 selection
+              20
+              4
+            
+            
+              C5S
+              DMA channel 5 selection
+              16
+              4
+            
+            
+              C4S
+              DMA channel 4 selection
+              12
+              4
+            
+            
+              C3S
+              DMA channel 3 selection
+              8
+              4
+            
+            
+              C2S
+              DMA channel 2 selection
+              4
+              4
+            
+            
+              C1S
+              DMA channel 1 selection
+              0
+              4
+            
+          
+        
+      
+    
+    
+      CRC
+      Cyclic redundancy check calculation
+      unit
+      CRC
+      0x40023000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          DR
+          DR
+          Data register
+          0x0
+          0x20
+          read-write
+          0xFFFFFFFF
+          
+            
+              DR
+              Data register bits
+              0
+              32
+            
+          
+        
+        
+          IDR
+          IDR
+          Independent data register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IDR
+              General-purpose 8-bit data register
+              bits
+              0
+              8
+            
+          
+        
+        
+          CR
+          CR
+          Control register
+          0x8
+          0x20
+          0x00000000
+          
+            
+              REV_OUT
+              Reverse output data
+              7
+              1
+              read-write
+            
+            
+              REV_IN
+              Reverse input data
+              5
+              2
+              read-write
+            
+            
+              POLYSIZE
+              Polynomial size
+              3
+              2
+              read-write
+            
+            
+              RESET
+              RESET bit
+              0
+              1
+              write-only
+            
+          
+        
+        
+          INIT
+          INIT
+          Initial CRC value
+          0x10
+          0x20
+          read-write
+          0xFFFFFFFF
+          
+            
+              CRC_INIT
+              Programmable initial CRC
+              value
+              0
+              32
+            
+          
+        
+        
+          POL
+          POL
+          polynomial
+          0x14
+          0x20
+          read-write
+          0x04C11DB7
+          
+            
+              Polynomialcoefficients
+              Programmable polynomial
+              0
+              32
+            
+          
+        
+      
+    
+    
+      GPIOA
+      General-purpose I/Os
+      GPIO
+      0x50000000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          MODER
+          MODER
+          GPIO port mode register
+          0x0
+          0x20
+          read-write
+          0xEBFFFCFF
+          
+            
+              MODE0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+            
+              MODE1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              MODE2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              MODE3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              MODE4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              MODE5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              MODE6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              MODE7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              MODE8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              MODE9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              MODE10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              MODE11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              MODE12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              MODE13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              MODE14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              MODE15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+          
+        
+        
+          OTYPER
+          OTYPER
+          GPIO port output type register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OT15
+              Port x configuration bits (y =
+              0..15)
+              15
+              1
+            
+            
+              OT14
+              Port x configuration bits (y =
+              0..15)
+              14
+              1
+            
+            
+              OT13
+              Port x configuration bits (y =
+              0..15)
+              13
+              1
+            
+            
+              OT12
+              Port x configuration bits (y =
+              0..15)
+              12
+              1
+            
+            
+              OT11
+              Port x configuration bits (y =
+              0..15)
+              11
+              1
+            
+            
+              OT10
+              Port x configuration bits (y =
+              0..15)
+              10
+              1
+            
+            
+              OT9
+              Port x configuration bits (y =
+              0..15)
+              9
+              1
+            
+            
+              OT8
+              Port x configuration bits (y =
+              0..15)
+              8
+              1
+            
+            
+              OT7
+              Port x configuration bits (y =
+              0..15)
+              7
+              1
+            
+            
+              OT6
+              Port x configuration bits (y =
+              0..15)
+              6
+              1
+            
+            
+              OT5
+              Port x configuration bits (y =
+              0..15)
+              5
+              1
+            
+            
+              OT4
+              Port x configuration bits (y =
+              0..15)
+              4
+              1
+            
+            
+              OT3
+              Port x configuration bits (y =
+              0..15)
+              3
+              1
+            
+            
+              OT2
+              Port x configuration bits (y =
+              0..15)
+              2
+              1
+            
+            
+              OT1
+              Port x configuration bits (y =
+              0..15)
+              1
+              1
+            
+            
+              OT0
+              Port x configuration bits (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          OSPEEDR
+          OSPEEDR
+          GPIO port output speed
+          register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OSPEED15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              OSPEED14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              OSPEED13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              OSPEED12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              OSPEED11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              OSPEED10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              OSPEED9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              OSPEED8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              OSPEED7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              OSPEED6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              OSPEED5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              OSPEED4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              OSPEED3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              OSPEED2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              OSPEED1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              OSPEED0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          PUPDR
+          PUPDR
+          GPIO port pull-up/pull-down
+          register
+          0xC
+          0x20
+          read-write
+          0x24000000
+          
+            
+              PUPD15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              PUPD14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              PUPD13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              PUPD12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              PUPD11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              PUPD10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              PUPD9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              PUPD8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              PUPD7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              PUPD6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              PUPD5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              PUPD4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              PUPD3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              PUPD2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              PUPD1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              PUPD0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          IDR
+          IDR
+          GPIO port input data register
+          0x10
+          0x20
+          read-only
+          0x00000000
+          
+            
+              ID15
+              Port input data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              ID14
+              Port input data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              ID13
+              Port input data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              ID12
+              Port input data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              ID11
+              Port input data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              ID10
+              Port input data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              ID9
+              Port input data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              ID8
+              Port input data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              ID7
+              Port input data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              ID6
+              Port input data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              ID5
+              Port input data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              ID4
+              Port input data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              ID3
+              Port input data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              ID2
+              Port input data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              ID1
+              Port input data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              ID0
+              Port input data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          ODR
+          ODR
+          GPIO port output data register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OD15
+              Port output data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              OD14
+              Port output data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              OD13
+              Port output data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              OD12
+              Port output data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              OD11
+              Port output data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              OD10
+              Port output data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              OD9
+              Port output data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              OD8
+              Port output data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              OD7
+              Port output data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              OD6
+              Port output data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              OD5
+              Port output data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              OD4
+              Port output data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              OD3
+              Port output data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              OD2
+              Port output data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              OD1
+              Port output data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              OD0
+              Port output data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          BSRR
+          BSRR
+          GPIO port bit set/reset
+          register
+          0x18
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x reset bit y (y =
+              0..15)
+              31
+              1
+            
+            
+              BR14
+              Port x reset bit y (y =
+              0..15)
+              30
+              1
+            
+            
+              BR13
+              Port x reset bit y (y =
+              0..15)
+              29
+              1
+            
+            
+              BR12
+              Port x reset bit y (y =
+              0..15)
+              28
+              1
+            
+            
+              BR11
+              Port x reset bit y (y =
+              0..15)
+              27
+              1
+            
+            
+              BR10
+              Port x reset bit y (y =
+              0..15)
+              26
+              1
+            
+            
+              BR9
+              Port x reset bit y (y =
+              0..15)
+              25
+              1
+            
+            
+              BR8
+              Port x reset bit y (y =
+              0..15)
+              24
+              1
+            
+            
+              BR7
+              Port x reset bit y (y =
+              0..15)
+              23
+              1
+            
+            
+              BR6
+              Port x reset bit y (y =
+              0..15)
+              22
+              1
+            
+            
+              BR5
+              Port x reset bit y (y =
+              0..15)
+              21
+              1
+            
+            
+              BR4
+              Port x reset bit y (y =
+              0..15)
+              20
+              1
+            
+            
+              BR3
+              Port x reset bit y (y =
+              0..15)
+              19
+              1
+            
+            
+              BR2
+              Port x reset bit y (y =
+              0..15)
+              18
+              1
+            
+            
+              BR1
+              Port x reset bit y (y =
+              0..15)
+              17
+              1
+            
+            
+              BR0
+              Port x reset bit y (y =
+              0..15)
+              16
+              1
+            
+            
+              BS15
+              Port x set bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              BS14
+              Port x set bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              BS13
+              Port x set bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              BS12
+              Port x set bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              BS11
+              Port x set bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              BS10
+              Port x set bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              BS9
+              Port x set bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              BS8
+              Port x set bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              BS7
+              Port x set bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              BS6
+              Port x set bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              BS5
+              Port x set bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              BS4
+              Port x set bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              BS3
+              Port x set bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              BS2
+              Port x set bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              BS1
+              Port x set bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              BS0
+              Port x set bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          LCKR
+          LCKR
+          GPIO port configuration lock
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LCKK
+              Port x lock bit y (y=
+              0..15)
+              16
+              1
+            
+            
+              LCK15
+              Port x lock bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              LCK14
+              Port x lock bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              LCK13
+              Port x lock bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              LCK12
+              Port x lock bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              LCK11
+              Port x lock bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              LCK10
+              Port x lock bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              LCK9
+              Port x lock bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              LCK8
+              Port x lock bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              LCK7
+              Port x lock bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              LCK6
+              Port x lock bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              LCK5
+              Port x lock bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              LCK4
+              Port x lock bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              LCK3
+              Port x lock bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              LCK2
+              Port x lock bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              LCK1
+              Port x lock bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              LCK0
+              Port x lock bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          AFRL
+          AFRL
+          GPIO alternate function low
+          register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL7
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              28
+              4
+            
+            
+              AFSEL6
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              24
+              4
+            
+            
+              AFSEL5
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              20
+              4
+            
+            
+              AFSEL4
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              16
+              4
+            
+            
+              AFSEL3
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              12
+              4
+            
+            
+              AFSEL2
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              8
+              4
+            
+            
+              AFSEL1
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              4
+              4
+            
+            
+              AFSEL0
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              0
+              4
+            
+          
+        
+        
+          AFRH
+          AFRH
+          GPIO alternate function high
+          register
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL15
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              28
+              4
+            
+            
+              AFSEL14
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              24
+              4
+            
+            
+              AFSEL13
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              20
+              4
+            
+            
+              AFSEL12
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              16
+              4
+            
+            
+              AFSEL11
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              12
+              4
+            
+            
+              AFSEL10
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              8
+              4
+            
+            
+              AFSEL9
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              4
+              4
+            
+            
+              AFSEL8
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              0
+              4
+            
+          
+        
+        
+          BRR
+          BRR
+          GPIO port bit reset register
+          0x28
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x Reset bit y (y= 0 ..
+              15)
+              15
+              1
+            
+            
+              BR14
+              Port x Reset bit y (y= 0 ..
+              15)
+              14
+              1
+            
+            
+              BR13
+              Port x Reset bit y (y= 0 ..
+              15)
+              13
+              1
+            
+            
+              BR12
+              Port x Reset bit y (y= 0 ..
+              15)
+              12
+              1
+            
+            
+              BR11
+              Port x Reset bit y (y= 0 ..
+              15)
+              11
+              1
+            
+            
+              BR10
+              Port x Reset bit y (y= 0 ..
+              15)
+              10
+              1
+            
+            
+              BR9
+              Port x Reset bit y (y= 0 ..
+              15)
+              9
+              1
+            
+            
+              BR8
+              Port x Reset bit y (y= 0 ..
+              15)
+              8
+              1
+            
+            
+              BR7
+              Port x Reset bit y (y= 0 ..
+              15)
+              7
+              1
+            
+            
+              BR6
+              Port x Reset bit y (y= 0 ..
+              15)
+              6
+              1
+            
+            
+              BR5
+              Port x Reset bit y (y= 0 ..
+              15)
+              5
+              1
+            
+            
+              BR4
+              Port x Reset bit y (y= 0 ..
+              15)
+              4
+              1
+            
+            
+              BR3
+              Port x Reset bit y (y= 0 ..
+              15)
+              3
+              1
+            
+            
+              BR2
+              Port x Reset bit y (y= 0 ..
+              15)
+              2
+              1
+            
+            
+              BR1
+              Port x Reset bit y (y= 0 ..
+              15)
+              1
+              1
+            
+            
+              BR0
+              Port x Reset bit y (y= 0 ..
+              15)
+              0
+              1
+            
+          
+        
+      
+    
+    
+      GPIOB
+      General-purpose I/Os
+      GPIO
+      0x50000400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          MODER
+          MODER
+          GPIO port mode register
+          0x0
+          0x20
+          read-write
+          0xFFFFFFFF
+          
+            
+              MODE15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              MODE14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              MODE13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              MODE12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              MODE11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              MODE10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              MODE9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              MODE8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              MODE7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              MODE6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              MODE5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              MODE4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              MODE3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              MODE2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              MODE1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              MODE0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          OTYPER
+          OTYPER
+          GPIO port output type register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OT15
+              Port x configuration bits (y =
+              0..15)
+              15
+              1
+            
+            
+              OT14
+              Port x configuration bits (y =
+              0..15)
+              14
+              1
+            
+            
+              OT13
+              Port x configuration bits (y =
+              0..15)
+              13
+              1
+            
+            
+              OT12
+              Port x configuration bits (y =
+              0..15)
+              12
+              1
+            
+            
+              OT11
+              Port x configuration bits (y =
+              0..15)
+              11
+              1
+            
+            
+              OT10
+              Port x configuration bits (y =
+              0..15)
+              10
+              1
+            
+            
+              OT9
+              Port x configuration bits (y =
+              0..15)
+              9
+              1
+            
+            
+              OT8
+              Port x configuration bits (y =
+              0..15)
+              8
+              1
+            
+            
+              OT7
+              Port x configuration bits (y =
+              0..15)
+              7
+              1
+            
+            
+              OT6
+              Port x configuration bits (y =
+              0..15)
+              6
+              1
+            
+            
+              OT5
+              Port x configuration bits (y =
+              0..15)
+              5
+              1
+            
+            
+              OT4
+              Port x configuration bits (y =
+              0..15)
+              4
+              1
+            
+            
+              OT3
+              Port x configuration bits (y =
+              0..15)
+              3
+              1
+            
+            
+              OT2
+              Port x configuration bits (y =
+              0..15)
+              2
+              1
+            
+            
+              OT1
+              Port x configuration bits (y =
+              0..15)
+              1
+              1
+            
+            
+              OT0
+              Port x configuration bits (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          OSPEEDR
+          OSPEEDR
+          GPIO port output speed
+          register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OSPEED15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              OSPEED14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              OSPEED13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              OSPEED12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              OSPEED11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              OSPEED10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              OSPEED9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              OSPEED8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              OSPEED7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              OSPEED6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              OSPEED5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              OSPEED4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              OSPEED3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              OSPEED2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              OSPEED1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              OSPEED0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          PUPDR
+          PUPDR
+          GPIO port pull-up/pull-down
+          register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PUPD15
+              Port x configuration bits (y =
+              0..15)
+              30
+              2
+            
+            
+              PUPD14
+              Port x configuration bits (y =
+              0..15)
+              28
+              2
+            
+            
+              PUPD13
+              Port x configuration bits (y =
+              0..15)
+              26
+              2
+            
+            
+              PUPD12
+              Port x configuration bits (y =
+              0..15)
+              24
+              2
+            
+            
+              PUPD11
+              Port x configuration bits (y =
+              0..15)
+              22
+              2
+            
+            
+              PUPD10
+              Port x configuration bits (y =
+              0..15)
+              20
+              2
+            
+            
+              PUPD9
+              Port x configuration bits (y =
+              0..15)
+              18
+              2
+            
+            
+              PUPD8
+              Port x configuration bits (y =
+              0..15)
+              16
+              2
+            
+            
+              PUPD7
+              Port x configuration bits (y =
+              0..15)
+              14
+              2
+            
+            
+              PUPD6
+              Port x configuration bits (y =
+              0..15)
+              12
+              2
+            
+            
+              PUPD5
+              Port x configuration bits (y =
+              0..15)
+              10
+              2
+            
+            
+              PUPD4
+              Port x configuration bits (y =
+              0..15)
+              8
+              2
+            
+            
+              PUPD3
+              Port x configuration bits (y =
+              0..15)
+              6
+              2
+            
+            
+              PUPD2
+              Port x configuration bits (y =
+              0..15)
+              4
+              2
+            
+            
+              PUPD1
+              Port x configuration bits (y =
+              0..15)
+              2
+              2
+            
+            
+              PUPD0
+              Port x configuration bits (y =
+              0..15)
+              0
+              2
+            
+          
+        
+        
+          IDR
+          IDR
+          GPIO port input data register
+          0x10
+          0x20
+          read-only
+          0x00000000
+          
+            
+              ID15
+              Port input data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              ID14
+              Port input data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              ID13
+              Port input data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              ID12
+              Port input data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              ID11
+              Port input data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              ID10
+              Port input data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              ID9
+              Port input data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              ID8
+              Port input data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              ID7
+              Port input data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              ID6
+              Port input data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              ID5
+              Port input data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              ID4
+              Port input data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              ID3
+              Port input data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              ID2
+              Port input data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              ID1
+              Port input data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              ID0
+              Port input data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          ODR
+          ODR
+          GPIO port output data register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OD15
+              Port output data bit (y =
+              0..15)
+              15
+              1
+            
+            
+              OD14
+              Port output data bit (y =
+              0..15)
+              14
+              1
+            
+            
+              OD13
+              Port output data bit (y =
+              0..15)
+              13
+              1
+            
+            
+              OD12
+              Port output data bit (y =
+              0..15)
+              12
+              1
+            
+            
+              OD11
+              Port output data bit (y =
+              0..15)
+              11
+              1
+            
+            
+              OD10
+              Port output data bit (y =
+              0..15)
+              10
+              1
+            
+            
+              OD9
+              Port output data bit (y =
+              0..15)
+              9
+              1
+            
+            
+              OD8
+              Port output data bit (y =
+              0..15)
+              8
+              1
+            
+            
+              OD7
+              Port output data bit (y =
+              0..15)
+              7
+              1
+            
+            
+              OD6
+              Port output data bit (y =
+              0..15)
+              6
+              1
+            
+            
+              OD5
+              Port output data bit (y =
+              0..15)
+              5
+              1
+            
+            
+              OD4
+              Port output data bit (y =
+              0..15)
+              4
+              1
+            
+            
+              OD3
+              Port output data bit (y =
+              0..15)
+              3
+              1
+            
+            
+              OD2
+              Port output data bit (y =
+              0..15)
+              2
+              1
+            
+            
+              OD1
+              Port output data bit (y =
+              0..15)
+              1
+              1
+            
+            
+              OD0
+              Port output data bit (y =
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          BSRR
+          BSRR
+          GPIO port bit set/reset
+          register
+          0x18
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x reset bit y (y =
+              0..15)
+              31
+              1
+            
+            
+              BR14
+              Port x reset bit y (y =
+              0..15)
+              30
+              1
+            
+            
+              BR13
+              Port x reset bit y (y =
+              0..15)
+              29
+              1
+            
+            
+              BR12
+              Port x reset bit y (y =
+              0..15)
+              28
+              1
+            
+            
+              BR11
+              Port x reset bit y (y =
+              0..15)
+              27
+              1
+            
+            
+              BR10
+              Port x reset bit y (y =
+              0..15)
+              26
+              1
+            
+            
+              BR9
+              Port x reset bit y (y =
+              0..15)
+              25
+              1
+            
+            
+              BR8
+              Port x reset bit y (y =
+              0..15)
+              24
+              1
+            
+            
+              BR7
+              Port x reset bit y (y =
+              0..15)
+              23
+              1
+            
+            
+              BR6
+              Port x reset bit y (y =
+              0..15)
+              22
+              1
+            
+            
+              BR5
+              Port x reset bit y (y =
+              0..15)
+              21
+              1
+            
+            
+              BR4
+              Port x reset bit y (y =
+              0..15)
+              20
+              1
+            
+            
+              BR3
+              Port x reset bit y (y =
+              0..15)
+              19
+              1
+            
+            
+              BR2
+              Port x reset bit y (y =
+              0..15)
+              18
+              1
+            
+            
+              BR1
+              Port x reset bit y (y =
+              0..15)
+              17
+              1
+            
+            
+              BR0
+              Port x reset bit y (y =
+              0..15)
+              16
+              1
+            
+            
+              BS15
+              Port x set bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              BS14
+              Port x set bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              BS13
+              Port x set bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              BS12
+              Port x set bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              BS11
+              Port x set bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              BS10
+              Port x set bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              BS9
+              Port x set bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              BS8
+              Port x set bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              BS7
+              Port x set bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              BS6
+              Port x set bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              BS5
+              Port x set bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              BS4
+              Port x set bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              BS3
+              Port x set bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              BS2
+              Port x set bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              BS1
+              Port x set bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              BS0
+              Port x set bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          LCKR
+          LCKR
+          GPIO port configuration lock
+          register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LCKK
+              Port x lock bit y (y=
+              0..15)
+              16
+              1
+            
+            
+              LCK15
+              Port x lock bit y (y=
+              0..15)
+              15
+              1
+            
+            
+              LCK14
+              Port x lock bit y (y=
+              0..15)
+              14
+              1
+            
+            
+              LCK13
+              Port x lock bit y (y=
+              0..15)
+              13
+              1
+            
+            
+              LCK12
+              Port x lock bit y (y=
+              0..15)
+              12
+              1
+            
+            
+              LCK11
+              Port x lock bit y (y=
+              0..15)
+              11
+              1
+            
+            
+              LCK10
+              Port x lock bit y (y=
+              0..15)
+              10
+              1
+            
+            
+              LCK9
+              Port x lock bit y (y=
+              0..15)
+              9
+              1
+            
+            
+              LCK8
+              Port x lock bit y (y=
+              0..15)
+              8
+              1
+            
+            
+              LCK7
+              Port x lock bit y (y=
+              0..15)
+              7
+              1
+            
+            
+              LCK6
+              Port x lock bit y (y=
+              0..15)
+              6
+              1
+            
+            
+              LCK5
+              Port x lock bit y (y=
+              0..15)
+              5
+              1
+            
+            
+              LCK4
+              Port x lock bit y (y=
+              0..15)
+              4
+              1
+            
+            
+              LCK3
+              Port x lock bit y (y=
+              0..15)
+              3
+              1
+            
+            
+              LCK2
+              Port x lock bit y (y=
+              0..15)
+              2
+              1
+            
+            
+              LCK1
+              Port x lock bit y (y=
+              0..15)
+              1
+              1
+            
+            
+              LCK0
+              Port x lock bit y (y=
+              0..15)
+              0
+              1
+            
+          
+        
+        
+          AFRL
+          AFRL
+          GPIO alternate function low
+          register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL7
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              28
+              4
+            
+            
+              AFSEL6
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              24
+              4
+            
+            
+              AFSEL5
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              20
+              4
+            
+            
+              AFSEL4
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              16
+              4
+            
+            
+              AFSEL3
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              12
+              4
+            
+            
+              AFSEL2
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              8
+              4
+            
+            
+              AFSEL1
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              4
+              4
+            
+            
+              AFSEL0
+              Alternate function selection for port x
+              pin y (y = 0..7)
+              0
+              4
+            
+          
+        
+        
+          AFRH
+          AFRH
+          GPIO alternate function high
+          register
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AFSEL15
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              28
+              4
+            
+            
+              AFSEL14
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              24
+              4
+            
+            
+              AFSEL13
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              20
+              4
+            
+            
+              AFSEL12
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              16
+              4
+            
+            
+              AFSEL11
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              12
+              4
+            
+            
+              AFSEL10
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              8
+              4
+            
+            
+              AFSEL9
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              4
+              4
+            
+            
+              AFSEL8
+              Alternate function selection for port x
+              pin y (y = 8..15)
+              0
+              4
+            
+          
+        
+        
+          BRR
+          BRR
+          GPIO port bit reset register
+          0x28
+          0x20
+          write-only
+          0x00000000
+          
+            
+              BR15
+              Port x Reset bit y (y= 0 ..
+              15)
+              15
+              1
+            
+            
+              BR14
+              Port x Reset bit y (y= 0 ..
+              15)
+              14
+              1
+            
+            
+              BR13
+              Port x Reset bit y (y= 0 ..
+              15)
+              13
+              1
+            
+            
+              BR12
+              Port x Reset bit y (y= 0 ..
+              15)
+              12
+              1
+            
+            
+              BR11
+              Port x Reset bit y (y= 0 ..
+              15)
+              11
+              1
+            
+            
+              BR10
+              Port x Reset bit y (y= 0 ..
+              15)
+              10
+              1
+            
+            
+              BR9
+              Port x Reset bit y (y= 0 ..
+              15)
+              9
+              1
+            
+            
+              BR8
+              Port x Reset bit y (y= 0 ..
+              15)
+              8
+              1
+            
+            
+              BR7
+              Port x Reset bit y (y= 0 ..
+              15)
+              7
+              1
+            
+            
+              BR6
+              Port x Reset bit y (y= 0 ..
+              15)
+              6
+              1
+            
+            
+              BR5
+              Port x Reset bit y (y= 0 ..
+              15)
+              5
+              1
+            
+            
+              BR4
+              Port x Reset bit y (y= 0 ..
+              15)
+              4
+              1
+            
+            
+              BR3
+              Port x Reset bit y (y= 0 ..
+              15)
+              3
+              1
+            
+            
+              BR2
+              Port x Reset bit y (y= 0 ..
+              15)
+              2
+              1
+            
+            
+              BR1
+              Port x Reset bit y (y= 0 ..
+              15)
+              1
+              1
+            
+            
+              BR0
+              Port x Reset bit y (y= 0 ..
+              15)
+              0
+              1
+            
+          
+        
+      
+    
+    
+      GPIOC
+      0x50000800
+    
+    
+      GPIOD
+      0x50000C00
+    
+    
+      GPIOH
+      0x50001C00
+    
+    
+      GPIOE
+      0x50001000
+    
+    
+      LPTIM
+      Low power timer
+      LPTIM
+      0x40007C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        LPTIM1
+        LPTIMER1 interrupt through
+        EXTI29
+        13
+      
+      
+        
+          ISR
+          ISR
+          Interrupt and Status Register
+          0x0
+          0x20
+          read-only
+          0x00000000
+          
+            
+              DOWN
+              Counter direction change up to
+              down
+              6
+              1
+            
+            
+              UP
+              Counter direction change down to
+              up
+              5
+              1
+            
+            
+              ARROK
+              Autoreload register update
+              OK
+              4
+              1
+            
+            
+              CMPOK
+              Compare register update OK
+              3
+              1
+            
+            
+              EXTTRIG
+              External trigger edge
+              event
+              2
+              1
+            
+            
+              ARRM
+              Autoreload match
+              1
+              1
+            
+            
+              CMPM
+              Compare match
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt Clear Register
+          0x4
+          0x20
+          write-only
+          0x00000000
+          
+            
+              DOWNCF
+              Direction change to down Clear
+              Flag
+              6
+              1
+            
+            
+              UPCF
+              Direction change to UP Clear
+              Flag
+              5
+              1
+            
+            
+              ARROKCF
+              Autoreload register update OK Clear
+              Flag
+              4
+              1
+            
+            
+              CMPOKCF
+              Compare register update OK Clear
+              Flag
+              3
+              1
+            
+            
+              EXTTRIGCF
+              External trigger valid edge Clear
+              Flag
+              2
+              1
+            
+            
+              ARRMCF
+              Autoreload match Clear
+              Flag
+              1
+              1
+            
+            
+              CMPMCF
+              compare match Clear Flag
+              0
+              1
+            
+          
+        
+        
+          IER
+          IER
+          Interrupt Enable Register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DOWNIE
+              Direction change to down Interrupt
+              Enable
+              6
+              1
+            
+            
+              UPIE
+              Direction change to UP Interrupt
+              Enable
+              5
+              1
+            
+            
+              ARROKIE
+              Autoreload register update OK Interrupt
+              Enable
+              4
+              1
+            
+            
+              CMPOKIE
+              Compare register update OK Interrupt
+              Enable
+              3
+              1
+            
+            
+              EXTTRIGIE
+              External trigger valid edge Interrupt
+              Enable
+              2
+              1
+            
+            
+              ARRMIE
+              Autoreload match Interrupt
+              Enable
+              1
+              1
+            
+            
+              CMPMIE
+              Compare match Interrupt
+              Enable
+              0
+              1
+            
+          
+        
+        
+          CFGR
+          CFGR
+          Configuration Register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ENC
+              Encoder mode enable
+              24
+              1
+            
+            
+              COUNTMODE
+              counter mode enabled
+              23
+              1
+            
+            
+              PRELOAD
+              Registers update mode
+              22
+              1
+            
+            
+              WAVPOL
+              Waveform shape polarity
+              21
+              1
+            
+            
+              WAVE
+              Waveform shape
+              20
+              1
+            
+            
+              TIMOUT
+              Timeout enable
+              19
+              1
+            
+            
+              TRIGEN
+              Trigger enable and
+              polarity
+              17
+              2
+            
+            
+              TRIGSEL
+              Trigger selector
+              13
+              3
+            
+            
+              PRESC
+              Clock prescaler
+              9
+              3
+            
+            
+              TRGFLT
+              Configurable digital filter for
+              trigger
+              6
+              2
+            
+            
+              CKFLT
+              Configurable digital filter for external
+              clock
+              3
+              2
+            
+            
+              CKPOL
+              Clock Polarity
+              1
+              2
+            
+            
+              CKSEL
+              Clock selector
+              0
+              1
+            
+          
+        
+        
+          CR
+          CR
+          Control Register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNTSTRT
+              Timer start in continuous
+              mode
+              2
+              1
+            
+            
+              SNGSTRT
+              LPTIM start in single mode
+              1
+              1
+            
+            
+              ENABLE
+              LPTIM Enable
+              0
+              1
+            
+          
+        
+        
+          CMP
+          CMP
+          Compare Register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CMP
+              Compare value.
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          Autoreload Register
+          0x18
+          0x20
+          read-write
+          0x00000001
+          
+            
+              ARR
+              Auto reload value.
+              0
+              16
+            
+          
+        
+        
+          CNT
+          CNT
+          Counter Register
+          0x1C
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value.
+              0
+              16
+            
+          
+        
+      
+    
+    
+      RNG
+      Random number generator
+      RNG
+      0x40025000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IE
+              Interrupt enable
+              3
+              1
+            
+            
+              RNGEN
+              Random number generator
+              enable
+              2
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x4
+          0x20
+          0x00000000
+          
+            
+              SEIS
+              Seed error interrupt
+              status
+              6
+              1
+              read-write
+            
+            
+              CEIS
+              Clock error interrupt
+              status
+              5
+              1
+              read-write
+            
+            
+              SECS
+              Seed error current status
+              2
+              1
+              read-only
+            
+            
+              CECS
+              Clock error current status
+              1
+              1
+              read-only
+            
+            
+              DRDY
+              Data ready
+              0
+              1
+              read-only
+            
+          
+        
+        
+          DR
+          DR
+          data register
+          0x8
+          0x20
+          read-only
+          0x00000000
+          
+            
+              RNDATA
+              Random data
+              0
+              32
+            
+          
+        
+      
+    
+    
+      RTC
+      Real-time clock
+      RTC
+      0x40002800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        RTC
+        RTC global interrupt
+        2
+      
+      
+        
+          TR
+          TR
+          RTC time register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format
+              16
+              4
+            
+            
+              MNT
+              Minute tens in BCD format
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD format
+              8
+              4
+            
+            
+              ST
+              Second tens in BCD format
+              4
+              3
+            
+            
+              SU
+              Second units in BCD format
+              0
+              4
+            
+          
+        
+        
+          DR
+          DR
+          RTC date register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              YT
+              Year tens in BCD format
+              20
+              4
+            
+            
+              YU
+              Year units in BCD format
+              16
+              4
+            
+            
+              WDU
+              Week day units
+              13
+              3
+            
+            
+              MT
+              Month tens in BCD format
+              12
+              1
+            
+            
+              MU
+              Month units in BCD format
+              8
+              4
+            
+            
+              DT
+              Date tens in BCD format
+              4
+              2
+            
+            
+              DU
+              Date units in BCD format
+              0
+              4
+            
+          
+        
+        
+          CR
+          CR
+          RTC control register
+          0x8
+          0x20
+          0x00000000
+          
+            
+              COE
+              Calibration output enable
+              23
+              1
+              read-write
+            
+            
+              OSEL
+              Output selection
+              21
+              2
+              read-write
+            
+            
+              POL
+              Output polarity
+              20
+              1
+              read-write
+            
+            
+              COSEL
+              Calibration output
+              selection
+              19
+              1
+              read-write
+            
+            
+              BKP
+              Backup
+              18
+              1
+              read-write
+            
+            
+              SUB1H
+              Subtract 1 hour (winter time
+              change)
+              17
+              1
+              write-only
+            
+            
+              ADD1H
+              Add 1 hour (summer time
+              change)
+              16
+              1
+              write-only
+            
+            
+              TSIE
+              Time-stamp interrupt
+              enable
+              15
+              1
+              read-write
+            
+            
+              WUTIE
+              Wakeup timer interrupt
+              enable
+              14
+              1
+              read-write
+            
+            
+              ALRBIE
+              Alarm B interrupt enable
+              13
+              1
+              read-write
+            
+            
+              ALRAIE
+              Alarm A interrupt enable
+              12
+              1
+              read-write
+            
+            
+              TSE
+              timestamp enable
+              11
+              1
+              read-write
+            
+            
+              WUTE
+              Wakeup timer enable
+              10
+              1
+              read-write
+            
+            
+              ALRBE
+              Alarm B enable
+              9
+              1
+              read-write
+            
+            
+              ALRAE
+              Alarm A enable
+              8
+              1
+              read-write
+            
+            
+              FMT
+              Hour format
+              6
+              1
+              read-write
+            
+            
+              BYPSHAD
+              Bypass the shadow
+              registers
+              5
+              1
+              read-write
+            
+            
+              REFCKON
+              RTC_REFIN reference clock detection
+              enable (50 or 60 Hz)
+              4
+              1
+              read-write
+            
+            
+              TSEDGE
+              Time-stamp event active
+              edge
+              3
+              1
+              read-write
+            
+            
+              WUCKSEL
+              Wakeup clock selection
+              0
+              3
+              read-write
+            
+          
+        
+        
+          ISR
+          ISR
+          RTC initialization and status
+          register
+          0xC
+          0x20
+          0x00000000
+          
+            
+              TAMP2F
+              RTC_TAMP2 detection flag
+              14
+              1
+              read-write
+            
+            
+              TAMP1F
+              RTC_TAMP1 detection flag
+              13
+              1
+              read-write
+            
+            
+              TSOVF
+              Time-stamp overflow flag
+              12
+              1
+              read-write
+            
+            
+              TSF
+              Time-stamp flag
+              11
+              1
+              read-write
+            
+            
+              WUTF
+              Wakeup timer flag
+              10
+              1
+              read-write
+            
+            
+              ALRBF
+              Alarm B flag
+              9
+              1
+              read-write
+            
+            
+              ALRAF
+              Alarm A flag
+              8
+              1
+              read-write
+            
+            
+              INIT
+              Initialization mode
+              7
+              1
+              read-write
+            
+            
+              INITF
+              Initialization flag
+              6
+              1
+              read-only
+            
+            
+              RSF
+              Registers synchronization
+              flag
+              5
+              1
+              read-write
+            
+            
+              INITS
+              Initialization status flag
+              4
+              1
+              read-only
+            
+            
+              SHPF
+              Shift operation pending
+              3
+              1
+              read-only
+            
+            
+              WUTWF
+              Wakeup timer write flag
+              2
+              1
+              read-only
+            
+            
+              ALRBWF
+              Alarm B write flag
+              1
+              1
+              read-only
+            
+            
+              ALRAWF
+              Alarm A write flag
+              0
+              1
+              read-only
+            
+          
+        
+        
+          PRER
+          PRER
+          RTC prescaler register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PREDIV_A
+              Asynchronous prescaler
+              factor
+              16
+              7
+            
+            
+              PREDIV_S
+              Synchronous prescaler
+              factor
+              0
+              16
+            
+          
+        
+        
+          WUTR
+          WUTR
+          RTC wakeup timer register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              WUT
+              Wakeup auto-reload value
+              bits
+              0
+              16
+            
+          
+        
+        
+          ALRMAR
+          ALRMAR
+          RTC alarm A register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MSK4
+              Alarm A date mask
+              31
+              1
+            
+            
+              WDSEL
+              Week day selection
+              30
+              1
+            
+            
+              DT
+              Date tens in BCD format.
+              28
+              2
+            
+            
+              DU
+              Date units or day in BCD
+              format.
+              24
+              4
+            
+            
+              MSK3
+              Alarm A hours mask
+              23
+              1
+            
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format.
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format.
+              16
+              4
+            
+            
+              MSK2
+              Alarm A minutes mask
+              15
+              1
+            
+            
+              MNT
+              Minute tens in BCD format.
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD
+              format.
+              8
+              4
+            
+            
+              MSK1
+              Alarm A seconds mask
+              7
+              1
+            
+            
+              ST
+              Second tens in BCD format.
+              4
+              3
+            
+            
+              SU
+              Second units in BCD
+              format.
+              0
+              4
+            
+          
+        
+        
+          ALRMBR
+          ALRMBR
+          RTC alarm B register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MSK4
+              Alarm B date mask
+              31
+              1
+            
+            
+              WDSEL
+              Week day selection
+              30
+              1
+            
+            
+              DT
+              Date tens in BCD format
+              28
+              2
+            
+            
+              DU
+              Date units or day in BCD
+              format
+              24
+              4
+            
+            
+              MSK3
+              Alarm B hours mask
+              23
+              1
+            
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format
+              16
+              4
+            
+            
+              MSK2
+              Alarm B minutes mask
+              15
+              1
+            
+            
+              MNT
+              Minute tens in BCD format
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD format
+              8
+              4
+            
+            
+              MSK1
+              Alarm B seconds mask
+              7
+              1
+            
+            
+              ST
+              Second tens in BCD format
+              4
+              3
+            
+            
+              SU
+              Second units in BCD format
+              0
+              4
+            
+          
+        
+        
+          WPR
+          WPR
+          write protection register
+          0x24
+          0x20
+          write-only
+          0x00000000
+          
+            
+              KEY
+              Write protection key
+              0
+              8
+            
+          
+        
+        
+          SSR
+          SSR
+          RTC sub second register
+          0x28
+          0x20
+          read-only
+          0x00000000
+          
+            
+              SS
+              Sub second value
+              0
+              16
+            
+          
+        
+        
+          SHIFTR
+          SHIFTR
+          RTC shift control register
+          0x2C
+          0x20
+          write-only
+          0x00000000
+          
+            
+              ADD1S
+              Add one second
+              31
+              1
+            
+            
+              SUBFS
+              Subtract a fraction of a
+              second
+              0
+              15
+            
+          
+        
+        
+          TSTR
+          TSTR
+          RTC timestamp time register
+          0x30
+          0x20
+          read-only
+          0x00000000
+          
+            
+              PM
+              AM/PM notation
+              22
+              1
+            
+            
+              HT
+              Hour tens in BCD format.
+              20
+              2
+            
+            
+              HU
+              Hour units in BCD format.
+              16
+              4
+            
+            
+              MNT
+              Minute tens in BCD format.
+              12
+              3
+            
+            
+              MNU
+              Minute units in BCD
+              format.
+              8
+              4
+            
+            
+              ST
+              Second tens in BCD format.
+              4
+              3
+            
+            
+              SU
+              Second units in BCD
+              format.
+              0
+              4
+            
+          
+        
+        
+          TSDR
+          TSDR
+          RTC timestamp date register
+          0x34
+          0x20
+          read-only
+          0x00000000
+          
+            
+              WDU
+              Week day units
+              13
+              3
+            
+            
+              MT
+              Month tens in BCD format
+              12
+              1
+            
+            
+              MU
+              Month units in BCD format
+              8
+              4
+            
+            
+              DT
+              Date tens in BCD format
+              4
+              2
+            
+            
+              DU
+              Date units in BCD format
+              0
+              4
+            
+          
+        
+        
+          TSSSR
+          TSSSR
+          RTC time-stamp sub second
+          register
+          0x38
+          0x20
+          read-only
+          0x00000000
+          
+            
+              SS
+              Sub second value
+              0
+              16
+            
+          
+        
+        
+          CALR
+          CALR
+          RTC calibration register
+          0x3C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CALP
+              Increase frequency of RTC by 488.5
+              ppm
+              15
+              1
+            
+            
+              CALW8
+              Use a 8-second calibration cycle
+              period
+              14
+              1
+            
+            
+              CALW16
+              Use a 16-second calibration cycle
+              period
+              13
+              1
+            
+            
+              CALM
+              Calibration minus
+              0
+              9
+            
+          
+        
+        
+          TAMPCR
+          TAMPCR
+          RTC tamper configuration
+          register
+          0x40
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TAMP2MF
+              Tamper 2 mask flag
+              21
+              1
+            
+            
+              TAMP2NOERASE
+              Tamper 2 no erase
+              20
+              1
+            
+            
+              TAMP2IE
+              Tamper 2 interrupt enable
+              19
+              1
+            
+            
+              TAMP1MF
+              Tamper 1 mask flag
+              18
+              1
+            
+            
+              TAMP1NOERASE
+              Tamper 1 no erase
+              17
+              1
+            
+            
+              TAMP1IE
+              Tamper 1 interrupt enable
+              16
+              1
+            
+            
+              TAMPPUDIS
+              RTC_TAMPx pull-up disable
+              15
+              1
+            
+            
+              TAMPPRCH
+              RTC_TAMPx precharge
+              duration
+              13
+              2
+            
+            
+              TAMPFLT
+              RTC_TAMPx filter count
+              11
+              2
+            
+            
+              TAMPFREQ
+              Tamper sampling frequency
+              8
+              3
+            
+            
+              TAMPTS
+              Activate timestamp on tamper detection
+              event
+              7
+              1
+            
+            
+              TAMP2_TRG
+              Active level for RTC_TAMP2
+              input
+              4
+              1
+            
+            
+              TAMP2E
+              RTC_TAMP2 input detection
+              enable
+              3
+              1
+            
+            
+              TAMPIE
+              Tamper interrupt enable
+              2
+              1
+            
+            
+              TAMP1TRG
+              Active level for RTC_TAMP1
+              input
+              1
+              1
+            
+            
+              TAMP1E
+              RTC_TAMP1 input detection
+              enable
+              0
+              1
+            
+          
+        
+        
+          ALRMASSR
+          ALRMASSR
+          RTC alarm A sub second
+          register
+          0x44
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MASKSS
+              Mask the most-significant bits starting
+              at this bit
+              24
+              4
+            
+            
+              SS
+              Sub seconds value
+              0
+              15
+            
+          
+        
+        
+          ALRMBSSR
+          ALRMBSSR
+          RTC alarm B sub second
+          register
+          0x48
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MASKSS
+              Mask the most-significant bits starting
+              at this bit
+              24
+              4
+            
+            
+              SS
+              Sub seconds value
+              0
+              15
+            
+          
+        
+        
+          OR
+          OR
+          option register
+          0x4C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              RTC_OUT_RMP
+              RTC_ALARM on PC13 output
+              type
+              1
+              1
+            
+            
+              RTC_ALARM_TYPE
+              RTC_ALARM on PC13 output
+              type
+              0
+              1
+            
+          
+        
+        
+          BKP0R
+          BKP0R
+          RTC backup registers
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP1R
+          BKP1R
+          RTC backup registers
+          0x54
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP2R
+          BKP2R
+          RTC backup registers
+          0x58
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP3R
+          BKP3R
+          RTC backup registers
+          0x5C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+        
+          BKP4R
+          BKP4R
+          RTC backup registers
+          0x60
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BKP
+              BKP
+              0
+              32
+            
+          
+        
+      
+    
+    
+      USART1
+      Universal synchronous asynchronous receiver
+      transmitter
+      USART
+      0x40013800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR1
+          CR1
+          Control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              M1
+              Word length
+              28
+              1
+            
+            
+              EOBIE
+              End of Block interrupt
+              enable
+              27
+              1
+            
+            
+              RTOIE
+              Receiver timeout interrupt
+              enable
+              26
+              1
+            
+            
+              DEAT4
+              Driver Enable assertion
+              time
+              25
+              1
+            
+            
+              DEAT3
+              DEAT3
+              24
+              1
+            
+            
+              DEAT2
+              DEAT2
+              23
+              1
+            
+            
+              DEAT1
+              DEAT1
+              22
+              1
+            
+            
+              DEAT0
+              DEAT0
+              21
+              1
+            
+            
+              DEDT4
+              Driver Enable de-assertion
+              time
+              20
+              1
+            
+            
+              DEDT3
+              DEDT3
+              19
+              1
+            
+            
+              DEDT2
+              DEDT2
+              18
+              1
+            
+            
+              DEDT1
+              DEDT1
+              17
+              1
+            
+            
+              DEDT0
+              DEDT0
+              16
+              1
+            
+            
+              OVER8
+              Oversampling mode
+              15
+              1
+            
+            
+              CMIE
+              Character match interrupt
+              enable
+              14
+              1
+            
+            
+              MME
+              Mute mode enable
+              13
+              1
+            
+            
+              M0
+              Word length
+              12
+              1
+            
+            
+              WAKE
+              Receiver wakeup method
+              11
+              1
+            
+            
+              PCE
+              Parity control enable
+              10
+              1
+            
+            
+              PS
+              Parity selection
+              9
+              1
+            
+            
+              PEIE
+              PE interrupt enable
+              8
+              1
+            
+            
+              TXEIE
+              interrupt enable
+              7
+              1
+            
+            
+              TCIE
+              Transmission complete interrupt
+              enable
+              6
+              1
+            
+            
+              RXNEIE
+              RXNE interrupt enable
+              5
+              1
+            
+            
+              IDLEIE
+              IDLE interrupt enable
+              4
+              1
+            
+            
+              TE
+              Transmitter enable
+              3
+              1
+            
+            
+              RE
+              Receiver enable
+              2
+              1
+            
+            
+              UESM
+              USART enable in Stop mode
+              1
+              1
+            
+            
+              UE
+              USART enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          Control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              ADD4_7
+              Address of the USART node
+              28
+              4
+            
+            
+              ADD0_3
+              Address of the USART node
+              24
+              4
+            
+            
+              RTOEN
+              Receiver timeout enable
+              23
+              1
+            
+            
+              ABRMOD1
+              Auto baud rate mode
+              22
+              1
+            
+            
+              ABRMOD0
+              ABRMOD0
+              21
+              1
+            
+            
+              ABREN
+              Auto baud rate enable
+              20
+              1
+            
+            
+              MSBFIRST
+              Most significant bit first
+              19
+              1
+            
+            
+              TAINV
+              Binary data inversion
+              18
+              1
+            
+            
+              TXINV
+              TX pin active level
+              inversion
+              17
+              1
+            
+            
+              RXINV
+              RX pin active level
+              inversion
+              16
+              1
+            
+            
+              SWAP
+              Swap TX/RX pins
+              15
+              1
+            
+            
+              LINEN
+              LIN mode enable
+              14
+              1
+            
+            
+              STOP
+              STOP bits
+              12
+              2
+            
+            
+              CLKEN
+              Clock enable
+              11
+              1
+            
+            
+              CPOL
+              Clock polarity
+              10
+              1
+            
+            
+              CPHA
+              Clock phase
+              9
+              1
+            
+            
+              LBCL
+              Last bit clock pulse
+              8
+              1
+            
+            
+              LBDIE
+              LIN break detection interrupt
+              enable
+              6
+              1
+            
+            
+              LBDL
+              LIN break detection length
+              5
+              1
+            
+            
+              ADDM7
+              7-bit Address Detection/4-bit Address
+              Detection
+              4
+              1
+            
+          
+        
+        
+          CR3
+          CR3
+          Control register 3
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              WUFIE
+              Wakeup from Stop mode interrupt
+              enable
+              22
+              1
+            
+            
+              WUS
+              Wakeup from Stop mode interrupt flag
+              selection
+              20
+              2
+            
+            
+              SCARCNT
+              Smartcard auto-retry count
+              17
+              3
+            
+            
+              DEP
+              Driver enable polarity
+              selection
+              15
+              1
+            
+            
+              DEM
+              Driver enable mode
+              14
+              1
+            
+            
+              DDRE
+              DMA Disable on Reception
+              Error
+              13
+              1
+            
+            
+              OVRDIS
+              Overrun Disable
+              12
+              1
+            
+            
+              ONEBIT
+              One sample bit method
+              enable
+              11
+              1
+            
+            
+              CTSIE
+              CTS interrupt enable
+              10
+              1
+            
+            
+              CTSE
+              CTS enable
+              9
+              1
+            
+            
+              RTSE
+              RTS enable
+              8
+              1
+            
+            
+              DMAT
+              DMA enable transmitter
+              7
+              1
+            
+            
+              DMAR
+              DMA enable receiver
+              6
+              1
+            
+            
+              SCEN
+              Smartcard mode enable
+              5
+              1
+            
+            
+              NACK
+              Smartcard NACK enable
+              4
+              1
+            
+            
+              HDSEL
+              Half-duplex selection
+              3
+              1
+            
+            
+              IRLP
+              Ir low-power
+              2
+              1
+            
+            
+              IREN
+              Ir mode enable
+              1
+              1
+            
+            
+              EIE
+              Error interrupt enable
+              0
+              1
+            
+          
+        
+        
+          BRR
+          BRR
+          Baud rate register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              DIV_Mantissa
+              DIV_Mantissa
+              4
+              12
+            
+            
+              DIV_Fraction
+              DIV_Fraction
+              0
+              4
+            
+          
+        
+        
+          GTPR
+          GTPR
+          Guard time and prescaler
+          register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              GT
+              Guard time value
+              8
+              8
+            
+            
+              PSC
+              Prescaler value
+              0
+              8
+            
+          
+        
+        
+          RTOR
+          RTOR
+          Receiver timeout register
+          0x14
+          0x20
+          read-write
+          0x0000
+          
+            
+              BLEN
+              Block Length
+              24
+              8
+            
+            
+              RTO
+              Receiver timeout value
+              0
+              24
+            
+          
+        
+        
+          RQR
+          RQR
+          Request register
+          0x18
+          0x20
+          write-only
+          0x0000
+          
+            
+              TXFRQ
+              Transmit data flush
+              request
+              4
+              1
+            
+            
+              RXFRQ
+              Receive data flush request
+              3
+              1
+            
+            
+              MMRQ
+              Mute mode request
+              2
+              1
+            
+            
+              SBKRQ
+              Send break request
+              1
+              1
+            
+            
+              ABRRQ
+              Auto baud rate request
+              0
+              1
+            
+          
+        
+        
+          ISR
+          ISR
+          Interrupt & status
+          register
+          0x1C
+          0x20
+          read-only
+          0x00C0
+          
+            
+              REACK
+              REACK
+              22
+              1
+            
+            
+              TEACK
+              TEACK
+              21
+              1
+            
+            
+              WUF
+              WUF
+              20
+              1
+            
+            
+              RWU
+              RWU
+              19
+              1
+            
+            
+              SBKF
+              SBKF
+              18
+              1
+            
+            
+              CMF
+              CMF
+              17
+              1
+            
+            
+              BUSY
+              BUSY
+              16
+              1
+            
+            
+              ABRF
+              ABRF
+              15
+              1
+            
+            
+              ABRE
+              ABRE
+              14
+              1
+            
+            
+              EOBF
+              EOBF
+              12
+              1
+            
+            
+              RTOF
+              RTOF
+              11
+              1
+            
+            
+              CTS
+              CTS
+              10
+              1
+            
+            
+              CTSIF
+              CTSIF
+              9
+              1
+            
+            
+              LBDF
+              LBDF
+              8
+              1
+            
+            
+              TXE
+              TXE
+              7
+              1
+            
+            
+              TC
+              TC
+              6
+              1
+            
+            
+              RXNE
+              RXNE
+              5
+              1
+            
+            
+              IDLE
+              IDLE
+              4
+              1
+            
+            
+              ORE
+              ORE
+              3
+              1
+            
+            
+              NF
+              NF
+              2
+              1
+            
+            
+              FE
+              FE
+              1
+              1
+            
+            
+              PE
+              PE
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt flag clear register
+          0x20
+          0x20
+          write-only
+          0x0000
+          
+            
+              WUCF
+              Wakeup from Stop mode clear
+              flag
+              20
+              1
+            
+            
+              CMCF
+              Character match clear flag
+              17
+              1
+            
+            
+              EOBCF
+              End of block clear flag
+              12
+              1
+            
+            
+              RTOCF
+              Receiver timeout clear
+              flag
+              11
+              1
+            
+            
+              CTSCF
+              CTS clear flag
+              9
+              1
+            
+            
+              LBDCF
+              LIN break detection clear
+              flag
+              8
+              1
+            
+            
+              TCCF
+              Transmission complete clear
+              flag
+              6
+              1
+            
+            
+              IDLECF
+              Idle line detected clear
+              flag
+              4
+              1
+            
+            
+              ORECF
+              Overrun error clear flag
+              3
+              1
+            
+            
+              NCF
+              Noise detected clear flag
+              2
+              1
+            
+            
+              FECF
+              Framing error clear flag
+              1
+              1
+            
+            
+              PECF
+              Parity error clear flag
+              0
+              1
+            
+          
+        
+        
+          RDR
+          RDR
+          Receive data register
+          0x24
+          0x20
+          read-only
+          0x0000
+          
+            
+              RDR
+              Receive data value
+              0
+              9
+            
+          
+        
+        
+          TDR
+          TDR
+          Transmit data register
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              TDR
+              Transmit data value
+              0
+              9
+            
+          
+        
+      
+    
+    
+      USART2
+      0x40004400
+    
+    
+      USART4
+      0x40004C00
+      
+        USART4_USART5
+        USART4/USART5 global interrupt
+        14
+      
+      
+        USART1
+        USART1 global interrupt
+        27
+      
+    
+    
+      USART5
+      0x40005000
+      
+        USART2
+        USART2 global interrupt
+        28
+      
+    
+    
+      TSC
+      Touch sensing controller
+      TSC
+      0x40024000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TSC
+        Touch sensing interrupt
+        8
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CTPH
+              Charge transfer pulse high
+              28
+              4
+            
+            
+              CTPL
+              Charge transfer pulse low
+              24
+              4
+            
+            
+              SSD
+              Spread spectrum deviation
+              17
+              7
+            
+            
+              SSE
+              Spread spectrum enable
+              16
+              1
+            
+            
+              SSPSC
+              Spread spectrum prescaler
+              15
+              1
+            
+            
+              PGPSC
+              pulse generator prescaler
+              12
+              3
+            
+            
+              MCV
+              Max count value
+              5
+              3
+            
+            
+              IODEF
+              I/O Default mode
+              4
+              1
+            
+            
+              SYNCPOL
+              Synchronization pin
+              polarity
+              3
+              1
+            
+            
+              AM
+              Acquisition mode
+              2
+              1
+            
+            
+              START
+              Start a new acquisition
+              1
+              1
+            
+            
+              TSCE
+              Touch sensing controller
+              enable
+              0
+              1
+            
+          
+        
+        
+          IER
+          IER
+          interrupt enable register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MCEIE
+              Max count error interrupt
+              enable
+              1
+              1
+            
+            
+              EOAIE
+              End of acquisition interrupt
+              enable
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          interrupt clear register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MCEIC
+              Max count error interrupt
+              clear
+              1
+              1
+            
+            
+              EOAIC
+              End of acquisition interrupt
+              clear
+              0
+              1
+            
+          
+        
+        
+          ISR
+          ISR
+          interrupt status register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              MCEF
+              Max count error flag
+              1
+              1
+            
+            
+              EOAF
+              End of acquisition flag
+              0
+              1
+            
+          
+        
+        
+          IOHCR
+          IOHCR
+          I/O hysteresis control
+          register
+          0x10
+          0x20
+          read-write
+          0xFFFFFFFF
+          
+            
+              G8_IO4
+              G8_IO4
+              31
+              1
+            
+            
+              G8_IO3
+              G8_IO3
+              30
+              1
+            
+            
+              G8_IO2
+              G8_IO2
+              29
+              1
+            
+            
+              G8_IO1
+              G8_IO1
+              28
+              1
+            
+            
+              G7_IO4
+              G7_IO4
+              27
+              1
+            
+            
+              G7_IO3
+              G7_IO3
+              26
+              1
+            
+            
+              G7_IO2
+              G7_IO2
+              25
+              1
+            
+            
+              G7_IO1
+              G7_IO1
+              24
+              1
+            
+            
+              G6_IO4
+              G6_IO4
+              23
+              1
+            
+            
+              G6_IO3
+              G6_IO3
+              22
+              1
+            
+            
+              G6_IO2
+              G6_IO2
+              21
+              1
+            
+            
+              G6_IO1
+              G6_IO1
+              20
+              1
+            
+            
+              G5_IO4
+              G5_IO4
+              19
+              1
+            
+            
+              G5_IO3
+              G5_IO3
+              18
+              1
+            
+            
+              G5_IO2
+              G5_IO2
+              17
+              1
+            
+            
+              G5_IO1
+              G5_IO1
+              16
+              1
+            
+            
+              G4_IO4
+              G4_IO4
+              15
+              1
+            
+            
+              G4_IO3
+              G4_IO3
+              14
+              1
+            
+            
+              G4_IO2
+              G4_IO2
+              13
+              1
+            
+            
+              G4_IO1
+              G4_IO1
+              12
+              1
+            
+            
+              G3_IO4
+              G3_IO4
+              11
+              1
+            
+            
+              G3_IO3
+              G3_IO3
+              10
+              1
+            
+            
+              G3_IO2
+              G3_IO2
+              9
+              1
+            
+            
+              G3_IO1
+              G3_IO1
+              8
+              1
+            
+            
+              G2_IO4
+              G2_IO4
+              7
+              1
+            
+            
+              G2_IO3
+              G2_IO3
+              6
+              1
+            
+            
+              G2_IO2
+              G2_IO2
+              5
+              1
+            
+            
+              G2_IO1
+              G2_IO1
+              4
+              1
+            
+            
+              G1_IO4
+              G1_IO4
+              3
+              1
+            
+            
+              G1_IO3
+              G1_IO3
+              2
+              1
+            
+            
+              G1_IO2
+              G1_IO2
+              1
+              1
+            
+            
+              G1_IO1
+              G1_IO1
+              0
+              1
+            
+          
+        
+        
+          IOASCR
+          IOASCR
+          I/O analog switch control
+          register
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              G8_IO4
+              G8_IO4
+              31
+              1
+            
+            
+              G8_IO3
+              G8_IO3
+              30
+              1
+            
+            
+              G8_IO2
+              G8_IO2
+              29
+              1
+            
+            
+              G8_IO1
+              G8_IO1
+              28
+              1
+            
+            
+              G7_IO4
+              G7_IO4
+              27
+              1
+            
+            
+              G7_IO3
+              G7_IO3
+              26
+              1
+            
+            
+              G7_IO2
+              G7_IO2
+              25
+              1
+            
+            
+              G7_IO1
+              G7_IO1
+              24
+              1
+            
+            
+              G6_IO4
+              G6_IO4
+              23
+              1
+            
+            
+              G6_IO3
+              G6_IO3
+              22
+              1
+            
+            
+              G6_IO2
+              G6_IO2
+              21
+              1
+            
+            
+              G6_IO1
+              G6_IO1
+              20
+              1
+            
+            
+              G5_IO4
+              G5_IO4
+              19
+              1
+            
+            
+              G5_IO3
+              G5_IO3
+              18
+              1
+            
+            
+              G5_IO2
+              G5_IO2
+              17
+              1
+            
+            
+              G5_IO1
+              G5_IO1
+              16
+              1
+            
+            
+              G4_IO4
+              G4_IO4
+              15
+              1
+            
+            
+              G4_IO3
+              G4_IO3
+              14
+              1
+            
+            
+              G4_IO2
+              G4_IO2
+              13
+              1
+            
+            
+              G4_IO1
+              G4_IO1
+              12
+              1
+            
+            
+              G3_IO4
+              G3_IO4
+              11
+              1
+            
+            
+              G3_IO3
+              G3_IO3
+              10
+              1
+            
+            
+              G3_IO2
+              G3_IO2
+              9
+              1
+            
+            
+              G3_IO1
+              G3_IO1
+              8
+              1
+            
+            
+              G2_IO4
+              G2_IO4
+              7
+              1
+            
+            
+              G2_IO3
+              G2_IO3
+              6
+              1
+            
+            
+              G2_IO2
+              G2_IO2
+              5
+              1
+            
+            
+              G2_IO1
+              G2_IO1
+              4
+              1
+            
+            
+              G1_IO4
+              G1_IO4
+              3
+              1
+            
+            
+              G1_IO3
+              G1_IO3
+              2
+              1
+            
+            
+              G1_IO2
+              G1_IO2
+              1
+              1
+            
+            
+              G1_IO1
+              G1_IO1
+              0
+              1
+            
+          
+        
+        
+          IOSCR
+          IOSCR
+          I/O sampling control register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              G8_IO4
+              G8_IO4
+              31
+              1
+            
+            
+              G8_IO3
+              G8_IO3
+              30
+              1
+            
+            
+              G8_IO2
+              G8_IO2
+              29
+              1
+            
+            
+              G8_IO1
+              G8_IO1
+              28
+              1
+            
+            
+              G7_IO4
+              G7_IO4
+              27
+              1
+            
+            
+              G7_IO3
+              G7_IO3
+              26
+              1
+            
+            
+              G7_IO2
+              G7_IO2
+              25
+              1
+            
+            
+              G7_IO1
+              G7_IO1
+              24
+              1
+            
+            
+              G6_IO4
+              G6_IO4
+              23
+              1
+            
+            
+              G6_IO3
+              G6_IO3
+              22
+              1
+            
+            
+              G6_IO2
+              G6_IO2
+              21
+              1
+            
+            
+              G6_IO1
+              G6_IO1
+              20
+              1
+            
+            
+              G5_IO4
+              G5_IO4
+              19
+              1
+            
+            
+              G5_IO3
+              G5_IO3
+              18
+              1
+            
+            
+              G5_IO2
+              G5_IO2
+              17
+              1
+            
+            
+              G5_IO1
+              G5_IO1
+              16
+              1
+            
+            
+              G4_IO4
+              G4_IO4
+              15
+              1
+            
+            
+              G4_IO3
+              G4_IO3
+              14
+              1
+            
+            
+              G4_IO2
+              G4_IO2
+              13
+              1
+            
+            
+              G4_IO1
+              G4_IO1
+              12
+              1
+            
+            
+              G3_IO4
+              G3_IO4
+              11
+              1
+            
+            
+              G3_IO3
+              G3_IO3
+              10
+              1
+            
+            
+              G3_IO2
+              G3_IO2
+              9
+              1
+            
+            
+              G3_IO1
+              G3_IO1
+              8
+              1
+            
+            
+              G2_IO4
+              G2_IO4
+              7
+              1
+            
+            
+              G2_IO3
+              G2_IO3
+              6
+              1
+            
+            
+              G2_IO2
+              G2_IO2
+              5
+              1
+            
+            
+              G2_IO1
+              G2_IO1
+              4
+              1
+            
+            
+              G1_IO4
+              G1_IO4
+              3
+              1
+            
+            
+              G1_IO3
+              G1_IO3
+              2
+              1
+            
+            
+              G1_IO2
+              G1_IO2
+              1
+              1
+            
+            
+              G1_IO1
+              G1_IO1
+              0
+              1
+            
+          
+        
+        
+          IOCCR
+          IOCCR
+          I/O channel control register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              G8_IO4
+              G8_IO4
+              31
+              1
+            
+            
+              G8_IO3
+              G8_IO3
+              30
+              1
+            
+            
+              G8_IO2
+              G8_IO2
+              29
+              1
+            
+            
+              G8_IO1
+              G8_IO1
+              28
+              1
+            
+            
+              G7_IO4
+              G7_IO4
+              27
+              1
+            
+            
+              G7_IO3
+              G7_IO3
+              26
+              1
+            
+            
+              G7_IO2
+              G7_IO2
+              25
+              1
+            
+            
+              G7_IO1
+              G7_IO1
+              24
+              1
+            
+            
+              G6_IO4
+              G6_IO4
+              23
+              1
+            
+            
+              G6_IO3
+              G6_IO3
+              22
+              1
+            
+            
+              G6_IO2
+              G6_IO2
+              21
+              1
+            
+            
+              G6_IO1
+              G6_IO1
+              20
+              1
+            
+            
+              G5_IO4
+              G5_IO4
+              19
+              1
+            
+            
+              G5_IO3
+              G5_IO3
+              18
+              1
+            
+            
+              G5_IO2
+              G5_IO2
+              17
+              1
+            
+            
+              G5_IO1
+              G5_IO1
+              16
+              1
+            
+            
+              G4_IO4
+              G4_IO4
+              15
+              1
+            
+            
+              G4_IO3
+              G4_IO3
+              14
+              1
+            
+            
+              G4_IO2
+              G4_IO2
+              13
+              1
+            
+            
+              G4_IO1
+              G4_IO1
+              12
+              1
+            
+            
+              G3_IO4
+              G3_IO4
+              11
+              1
+            
+            
+              G3_IO3
+              G3_IO3
+              10
+              1
+            
+            
+              G3_IO2
+              G3_IO2
+              9
+              1
+            
+            
+              G3_IO1
+              G3_IO1
+              8
+              1
+            
+            
+              G2_IO4
+              G2_IO4
+              7
+              1
+            
+            
+              G2_IO3
+              G2_IO3
+              6
+              1
+            
+            
+              G2_IO2
+              G2_IO2
+              5
+              1
+            
+            
+              G2_IO1
+              G2_IO1
+              4
+              1
+            
+            
+              G1_IO4
+              G1_IO4
+              3
+              1
+            
+            
+              G1_IO3
+              G1_IO3
+              2
+              1
+            
+            
+              G1_IO2
+              G1_IO2
+              1
+              1
+            
+            
+              G1_IO1
+              G1_IO1
+              0
+              1
+            
+          
+        
+        
+          IOGCSR
+          IOGCSR
+          I/O group control status
+          register
+          0x30
+          0x20
+          0x00000000
+          
+            
+              G8S
+              Analog I/O group x status
+              23
+              1
+              read-only
+            
+            
+              G7S
+              Analog I/O group x status
+              22
+              1
+              read-only
+            
+            
+              G6S
+              Analog I/O group x status
+              21
+              1
+              read-only
+            
+            
+              G5S
+              Analog I/O group x status
+              20
+              1
+              read-only
+            
+            
+              G4S
+              Analog I/O group x status
+              19
+              1
+              read-only
+            
+            
+              G3S
+              Analog I/O group x status
+              18
+              1
+              read-only
+            
+            
+              G2S
+              Analog I/O group x status
+              17
+              1
+              read-only
+            
+            
+              G1S
+              Analog I/O group x status
+              16
+              1
+              read-only
+            
+            
+              G8E
+              Analog I/O group x enable
+              7
+              1
+              read-write
+            
+            
+              G7E
+              Analog I/O group x enable
+              6
+              1
+              read-write
+            
+            
+              G6E
+              Analog I/O group x enable
+              5
+              1
+              read-write
+            
+            
+              G5E
+              Analog I/O group x enable
+              4
+              1
+              read-write
+            
+            
+              G4E
+              Analog I/O group x enable
+              3
+              1
+              read-write
+            
+            
+              G3E
+              Analog I/O group x enable
+              2
+              1
+              read-write
+            
+            
+              G2E
+              Analog I/O group x enable
+              1
+              1
+              read-write
+            
+            
+              G1E
+              Analog I/O group x enable
+              0
+              1
+              read-write
+            
+          
+        
+        
+          IOG1CR
+          IOG1CR
+          I/O group x counter register
+          0x34
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG2CR
+          IOG2CR
+          I/O group x counter register
+          0x38
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG3CR
+          IOG3CR
+          I/O group x counter register
+          0x3C
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG4CR
+          IOG4CR
+          I/O group x counter register
+          0x40
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG5CR
+          IOG5CR
+          I/O group x counter register
+          0x44
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG6CR
+          IOG6CR
+          I/O group x counter register
+          0x48
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG7CR
+          IOG7CR
+          I/O group x counter register
+          0x4C
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+        
+          IOG8CR
+          IOG8CR
+          I/O group x counter register
+          0x50
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CNT
+              Counter value
+              0
+              14
+            
+          
+        
+      
+    
+    
+      IWDG
+      Independent watchdog
+      IWDG
+      0x40003000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          KR
+          KR
+          Key register
+          0x0
+          0x20
+          write-only
+          0x00000000
+          
+            
+              KEY
+              Key value (write only, read
+              0x0000)
+              0
+              16
+            
+          
+        
+        
+          PR
+          PR
+          Prescaler register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PR
+              Prescaler divider
+              0
+              3
+            
+          
+        
+        
+          RLR
+          RLR
+          Reload register
+          0x8
+          0x20
+          read-write
+          0x00000FFF
+          
+            
+              RL
+              Watchdog counter reload
+              value
+              0
+              12
+            
+          
+        
+        
+          SR
+          SR
+          Status register
+          0xC
+          0x20
+          read-only
+          0x00000000
+          
+            
+              WVU
+              Watchdog counter window value
+              update
+              2
+              1
+            
+            
+              RVU
+              Watchdog counter reload value
+              update
+              1
+              1
+            
+            
+              PVU
+              Watchdog prescaler value
+              update
+              0
+              1
+            
+          
+        
+        
+          WINR
+          WINR
+          Window register
+          0x10
+          0x20
+          read-write
+          0x00000FFF
+          
+            
+              WIN
+              Watchdog counter window
+              value
+              0
+              12
+            
+          
+        
+      
+    
+    
+      WWDG
+      System window watchdog
+      WWDG
+      0x40002C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        WWDG
+        Window Watchdog interrupt
+        0
+      
+      
+        
+          CR
+          CR
+          Control register
+          0x0
+          0x20
+          read-write
+          0x0000007F
+          
+            
+              WDGA
+              Activation bit
+              7
+              1
+            
+            
+              T
+              7-bit counter (MSB to LSB)
+              0
+              7
+            
+          
+        
+        
+          CFR
+          CFR
+          Configuration register
+          0x4
+          0x20
+          read-write
+          0x0000007F
+          
+            
+              EWI
+              Early wakeup interrupt
+              9
+              1
+            
+            
+              WDGTB1
+              Timer base
+              8
+              1
+            
+            
+              WDGTB0
+              WDGTB0
+              7
+              1
+            
+            
+              W
+              7-bit window value
+              0
+              7
+            
+          
+        
+        
+          SR
+          SR
+          Status register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EWIF
+              Early wakeup interrupt
+              flag
+              0
+              1
+            
+          
+        
+      
+    
+    
+      USB_FS
+      Universal serial bus full-speed device
+      interface
+      USB
+      0x40005C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        USB
+        USB event interrupt through
+        EXTI18
+        31
+      
+      
+        
+          EP0R
+          EP0R
+          endpoint register
+          0x0
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP1R
+          EP1R
+          endpoint register
+          0x4
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP2R
+          EP2R
+          endpoint register
+          0x8
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP3R
+          EP3R
+          endpoint register
+          0xC
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP4R
+          EP4R
+          endpoint register
+          0x10
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP5R
+          EP5R
+          endpoint register
+          0x14
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP6R
+          EP6R
+          endpoint register
+          0x18
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          EP7R
+          EP7R
+          endpoint register
+          0x1C
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR_RX
+              CTR_RX
+              15
+              1
+            
+            
+              DTOG_RX
+              DTOG_RX
+              14
+              1
+            
+            
+              STAT_RX
+              STAT_RX
+              12
+              2
+            
+            
+              SETUP
+              SETUP
+              11
+              1
+            
+            
+              EPTYPE
+              EPTYPE
+              9
+              2
+            
+            
+              EP_KIND
+              EP_KIND
+              8
+              1
+            
+            
+              CTR_TX
+              CTR_TX
+              7
+              1
+            
+            
+              DTOG_TX
+              DTOG_TX
+              6
+              1
+            
+            
+              STAT_TX
+              STAT_TX
+              4
+              2
+            
+            
+              EA
+              EA
+              0
+              4
+            
+          
+        
+        
+          CNTR
+          CNTR
+          control register
+          0x40
+          0x20
+          read-write
+          0x0
+          
+            
+              CTRM
+              CTRM
+              15
+              1
+            
+            
+              PMAOVRM
+              PMAOVRM
+              14
+              1
+            
+            
+              ERRM
+              ERRM
+              13
+              1
+            
+            
+              WKUPM
+              WKUPM
+              12
+              1
+            
+            
+              SUSPM
+              SUSPM
+              11
+              1
+            
+            
+              RESETM
+              RESETM
+              10
+              1
+            
+            
+              SOFM
+              SOFM
+              9
+              1
+            
+            
+              ESOFM
+              ESOFM
+              8
+              1
+            
+            
+              L1REQM
+              L1REQM
+              7
+              1
+            
+            
+              L1RESUME
+              L1RESUME
+              5
+              1
+            
+            
+              RESUME
+              RESUME
+              4
+              1
+            
+            
+              FSUSP
+              FSUSP
+              3
+              1
+            
+            
+              LPMODE
+              LPMODE
+              2
+              1
+            
+            
+              PDWN
+              PDWN
+              1
+              1
+            
+            
+              FRES
+              FRES
+              0
+              1
+            
+          
+        
+        
+          ISTR
+          ISTR
+          interrupt status register
+          0x44
+          0x20
+          read-write
+          0x0
+          
+            
+              CTR
+              CTR
+              15
+              1
+            
+            
+              PMAOVR
+              PMAOVR
+              14
+              1
+            
+            
+              ERR
+              ERR
+              13
+              1
+            
+            
+              WKUP
+              WKUP
+              12
+              1
+            
+            
+              SUSP
+              SUSP
+              11
+              1
+            
+            
+              RESET
+              RESET
+              10
+              1
+            
+            
+              SOF
+              SOF
+              9
+              1
+            
+            
+              ESOF
+              ESOF
+              8
+              1
+            
+            
+              L1REQ
+              L1REQ
+              7
+              1
+            
+            
+              DIR
+              DIR
+              4
+              1
+            
+            
+              EP_ID
+              EP_ID
+              0
+              4
+            
+          
+        
+        
+          FNR
+          FNR
+          frame number register
+          0x48
+          0x20
+          read-only
+          0x0
+          
+            
+              RXDP
+              RXDP
+              15
+              1
+            
+            
+              RXDM
+              RXDM
+              14
+              1
+            
+            
+              LCK
+              LCK
+              13
+              1
+            
+            
+              LSOF
+              LSOF
+              11
+              2
+            
+            
+              FN
+              FN
+              0
+              11
+            
+          
+        
+        
+          DADDR
+          DADDR
+          device address
+          0x4C
+          0x20
+          read-write
+          0x0
+          
+            
+              EF
+              EF
+              7
+              1
+            
+            
+              ADD
+              ADD
+              0
+              7
+            
+          
+        
+        
+          BTABLE
+          BTABLE
+          Buffer table address
+          0x50
+          0x20
+          read-write
+          0x0
+          
+            
+              BTABLE
+              BTABLE
+              3
+              13
+            
+          
+        
+        
+          LPMCSR
+          LPMCSR
+          LPM control and status
+          register
+          0x54
+          0x20
+          0x0
+          
+            
+              BESL
+              BESL
+              4
+              4
+              read-only
+            
+            
+              REMWAKE
+              REMWAKE
+              3
+              1
+              read-only
+            
+            
+              LPMACK
+              LPMACK
+              1
+              1
+              read-write
+            
+            
+              LPMEN
+              LPMEN
+              0
+              1
+              read-write
+            
+          
+        
+        
+          BCDR
+          BCDR
+          Battery charging detector
+          0x58
+          0x20
+          0x0
+          
+            
+              DPPU
+              DPPU
+              15
+              1
+              read-write
+            
+            
+              PS2DET
+              PS2DET
+              7
+              1
+              read-only
+            
+            
+              SDET
+              SDET
+              6
+              1
+              read-only
+            
+            
+              PDET
+              PDET
+              5
+              1
+              read-only
+            
+            
+              DCDET
+              DCDET
+              4
+              1
+              read-only
+            
+            
+              SDEN
+              SDEN
+              3
+              1
+              read-write
+            
+            
+              PDEN
+              PDEN
+              2
+              1
+              read-write
+            
+            
+              DCDEN
+              DCDEN
+              1
+              1
+              read-write
+            
+            
+              BCDEN
+              BCDEN
+              0
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      CRS
+      Clock recovery system
+      CRS
+      0x40006C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00002000
+          
+            
+              TRIM
+              HSI48 oscillator smooth
+              trimming
+              8
+              6
+            
+            
+              SWSYNC
+              Generate software SYNC
+              event
+              7
+              1
+            
+            
+              AUTOTRIMEN
+              Automatic trimming enable
+              6
+              1
+            
+            
+              CEN
+              Frequency error counter
+              enable
+              5
+              1
+            
+            
+              ESYNCIE
+              Expected SYNC interrupt
+              enable
+              3
+              1
+            
+            
+              ERRIE
+              Synchronization or trimming error
+              interrupt enable
+              2
+              1
+            
+            
+              SYNCWARNIE
+              SYNC warning interrupt
+              enable
+              1
+              1
+            
+            
+              SYNCOKIE
+              SYNC event OK interrupt
+              enable
+              0
+              1
+            
+          
+        
+        
+          CFGR
+          CFGR
+          configuration register
+          0x4
+          0x20
+          read-write
+          0x2022BB7F
+          
+            
+              SYNCPOL
+              SYNC polarity selection
+              31
+              1
+            
+            
+              SYNCSRC
+              SYNC signal source
+              selection
+              28
+              2
+            
+            
+              SYNCDIV
+              SYNC divider
+              24
+              3
+            
+            
+              FELIM
+              Frequency error limit
+              16
+              8
+            
+            
+              RELOAD
+              Counter reload value
+              0
+              16
+            
+          
+        
+        
+          ISR
+          ISR
+          interrupt and status register
+          0x8
+          0x20
+          read-only
+          0x00000000
+          
+            
+              FECAP
+              Frequency error capture
+              16
+              16
+            
+            
+              FEDIR
+              Frequency error direction
+              15
+              1
+            
+            
+              TRIMOVF
+              Trimming overflow or
+              underflow
+              10
+              1
+            
+            
+              SYNCMISS
+              SYNC missed
+              9
+              1
+            
+            
+              SYNCERR
+              SYNC error
+              8
+              1
+            
+            
+              ESYNCF
+              Expected SYNC flag
+              3
+              1
+            
+            
+              ERRF
+              Error flag
+              2
+              1
+            
+            
+              SYNCWARNF
+              SYNC warning flag
+              1
+              1
+            
+            
+              SYNCOKF
+              SYNC event OK flag
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          interrupt flag clear register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ESYNCC
+              Expected SYNC clear flag
+              3
+              1
+            
+            
+              ERRC
+              Error clear flag
+              2
+              1
+            
+            
+              SYNCWARNC
+              SYNC warning clear flag
+              1
+              1
+            
+            
+              SYNCOKC
+              SYNC event OK clear flag
+              0
+              1
+            
+          
+        
+      
+    
+    
+      Firewall
+      Firewall
+      Firewall
+      0x40011C00
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          FIREWALL_CSSA
+          FIREWALL_CSSA
+          Code segment start address
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADD
+              code segment start address
+              8
+              16
+            
+          
+        
+        
+          FIREWALL_CSL
+          FIREWALL_CSL
+          Code segment length
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LENG
+              code segment length
+              8
+              14
+            
+          
+        
+        
+          FIREWALL_NVDSSA
+          FIREWALL_NVDSSA
+          Non-volatile data segment start
+          address
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADD
+              Non-volatile data segment start
+              address
+              8
+              16
+            
+          
+        
+        
+          FIREWALL_NVDSL
+          FIREWALL_NVDSL
+          Non-volatile data segment
+          length
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LENG
+              Non-volatile data segment
+              length
+              8
+              14
+            
+          
+        
+        
+          FIREWALL_VDSSA
+          FIREWALL_VDSSA
+          Volatile data segment start
+          address
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADD
+              Volatile data segment start
+              address
+              6
+              10
+            
+          
+        
+        
+          FIREWALL_VDSL
+          FIREWALL_VDSL
+          Volatile data segment length
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LENG
+              Non-volatile data segment
+              length
+              6
+              10
+            
+          
+        
+        
+          FIREWALL_CR
+          FIREWALL_CR
+          Configuration register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              VDE
+              Volatile data execution
+              2
+              1
+            
+            
+              VDS
+              Volatile data shared
+              1
+              1
+            
+            
+              FPA
+              Firewall pre alarm
+              0
+              1
+            
+          
+        
+      
+    
+    
+      RCC
+      Reset and clock control
+      RCC
+      0x40021000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        RCC
+        RCC global interrupt
+        4
+      
+      
+        
+          CR
+          CR
+          Clock control register
+          0x0
+          0x20
+          0x00000300
+          
+            
+              PLLRDY
+              PLL clock ready flag
+              25
+              1
+              read-only
+            
+            
+              PLLON
+              PLL enable bit
+              24
+              1
+              read-write
+            
+            
+              RTCPRE
+              TC/LCD prescaler
+              20
+              2
+              read-write
+            
+            
+              CSSLSEON
+              Clock security system on HSE enable
+              bit
+              19
+              1
+              read-write
+            
+            
+              HSEBYP
+              HSE clock bypass bit
+              18
+              1
+              read-write
+            
+            
+              HSERDY
+              HSE clock ready flag
+              17
+              1
+              read-only
+            
+            
+              HSEON
+              HSE clock enable bit
+              16
+              1
+              read-write
+            
+            
+              MSIRDY
+              MSI clock ready flag
+              9
+              1
+              read-only
+            
+            
+              MSION
+              MSI clock enable bit
+              8
+              1
+              read-write
+            
+            
+              HSI16DIVF
+              HSI16DIVF
+              4
+              1
+              read-only
+            
+            
+              HSI16DIVEN
+              HSI16DIVEN
+              3
+              1
+              read-write
+            
+            
+              HSI16RDYF
+              Internal high-speed clock ready
+              flag
+              2
+              1
+              read-write
+            
+            
+              HSI16KERON
+              High-speed internal clock enable bit for
+              some IP kernels
+              1
+              1
+              read-only
+            
+            
+              HSI16ON
+              16 MHz high-speed internal clock
+              enable
+              0
+              1
+              read-write
+            
+            
+              HSI16OUTEN
+              16 MHz high-speed internal clock output
+              enable
+              5
+              1
+              read-write
+            
+          
+        
+        
+          ICSCR
+          ICSCR
+          Internal clock sources calibration
+          register
+          0x4
+          0x20
+          0x0000B000
+          
+            
+              MSITRIM
+              MSI clock trimming
+              24
+              8
+              read-write
+            
+            
+              MSICAL
+              MSI clock calibration
+              16
+              8
+              read-only
+            
+            
+              MSIRANGE
+              MSI clock ranges
+              13
+              3
+              read-write
+            
+            
+              HSI16TRIM
+              High speed internal clock
+              trimming
+              8
+              5
+              read-write
+            
+            
+              HSI16CAL
+              nternal high speed clock
+              calibration
+              0
+              8
+              read-only
+            
+          
+        
+        
+          CRRCR
+          CRRCR
+          Clock recovery RC register
+          0x8
+          0x20
+          0x00000000
+          
+            
+              HSI48CAL
+              48 MHz HSI clock
+              calibration
+              8
+              8
+              read-only
+            
+            
+              HSI48RDY
+              48MHz HSI clock ready flag
+              1
+              1
+              read-only
+            
+            
+              HSI48ON
+              48MHz HSI clock enable bit
+              0
+              1
+              read-write
+            
+            
+              HSI48DIV6EN
+              48 MHz HSI clock divided by 6 output
+              enable
+              2
+              1
+              read-write
+            
+          
+        
+        
+          CFGR
+          CFGR
+          Clock configuration register
+          0xC
+          0x20
+          0x00000000
+          
+            
+              MCOPRE
+              Microcontroller clock output
+              prescaler
+              28
+              3
+              read-write
+            
+            
+              MCOSEL
+              Microcontroller clock output
+              selection
+              24
+              4
+              read-write
+            
+            
+              PLLDIV
+              PLL output division
+              22
+              2
+              read-write
+            
+            
+              PLLMUL
+              PLL multiplication factor
+              18
+              4
+              read-write
+            
+            
+              PLLSRC
+              PLL entry clock source
+              16
+              1
+              read-write
+            
+            
+              STOPWUCK
+              Wake-up from stop clock
+              selection
+              15
+              1
+              read-write
+            
+            
+              PPRE2
+              APB high-speed prescaler
+              (APB2)
+              11
+              3
+              read-write
+            
+            
+              PPRE1
+              APB low-speed prescaler
+              (APB1)
+              8
+              3
+              read-write
+            
+            
+              HPRE
+              AHB prescaler
+              4
+              4
+              read-write
+            
+            
+              SWS
+              System clock switch status
+              2
+              2
+              read-only
+            
+            
+              SW
+              System clock switch
+              0
+              2
+              read-write
+            
+          
+        
+        
+          CIER
+          CIER
+          Clock interrupt enable
+          register
+          0x10
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CSSLSE
+              LSE CSS interrupt flag
+              7
+              1
+            
+            
+              HSI48RDYIE
+              HSI48 ready interrupt flag
+              6
+              1
+            
+            
+              MSIRDYIE
+              MSI ready interrupt flag
+              5
+              1
+            
+            
+              PLLRDYIE
+              PLL ready interrupt flag
+              4
+              1
+            
+            
+              HSERDYIE
+              HSE ready interrupt flag
+              3
+              1
+            
+            
+              HSI16RDYIE
+              HSI16 ready interrupt flag
+              2
+              1
+            
+            
+              LSERDYIE
+              LSE ready interrupt flag
+              1
+              1
+            
+            
+              LSIRDYIE
+              LSI ready interrupt flag
+              0
+              1
+            
+          
+        
+        
+          CIFR
+          CIFR
+          Clock interrupt flag register
+          0x14
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CSSHSEF
+              Clock Security System Interrupt
+              flag
+              8
+              1
+            
+            
+              CSSLSEF
+              LSE Clock Security System Interrupt
+              flag
+              7
+              1
+            
+            
+              HSI48RDYF
+              HSI48 ready interrupt flag
+              6
+              1
+            
+            
+              MSIRDYF
+              MSI ready interrupt flag
+              5
+              1
+            
+            
+              PLLRDYF
+              PLL ready interrupt flag
+              4
+              1
+            
+            
+              HSERDYF
+              HSE ready interrupt flag
+              3
+              1
+            
+            
+              HSI16RDYF
+              HSI16 ready interrupt flag
+              2
+              1
+            
+            
+              LSERDYF
+              LSE ready interrupt flag
+              1
+              1
+            
+            
+              LSIRDYF
+              LSI ready interrupt flag
+              0
+              1
+            
+          
+        
+        
+          CICR
+          CICR
+          Clock interrupt clear register
+          0x18
+          0x20
+          read-only
+          0x00000000
+          
+            
+              CSSHSEC
+              Clock Security System Interrupt
+              clear
+              8
+              1
+            
+            
+              CSSLSEC
+              LSE Clock Security System Interrupt
+              clear
+              7
+              1
+            
+            
+              HSI48RDYC
+              HSI48 ready Interrupt
+              clear
+              6
+              1
+            
+            
+              MSIRDYC
+              MSI ready Interrupt clear
+              5
+              1
+            
+            
+              PLLRDYC
+              PLL ready Interrupt clear
+              4
+              1
+            
+            
+              HSERDYC
+              HSE ready Interrupt clear
+              3
+              1
+            
+            
+              HSI16RDYC
+              HSI16 ready Interrupt
+              clear
+              2
+              1
+            
+            
+              LSERDYC
+              LSE ready Interrupt clear
+              1
+              1
+            
+            
+              LSIRDYC
+              LSI ready Interrupt clear
+              0
+              1
+            
+          
+        
+        
+          IOPRSTR
+          IOPRSTR
+          GPIO reset register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IOPHRST
+              I/O port H reset
+              7
+              1
+            
+            
+              IOPDRST
+              I/O port D reset
+              3
+              1
+            
+            
+              IOPCRST
+              I/O port A reset
+              2
+              1
+            
+            
+              IOPBRST
+              I/O port B reset
+              1
+              1
+            
+            
+              IOPARST
+              I/O port A reset
+              0
+              1
+            
+            
+              IOPERST
+              I/O port E reset
+              4
+              1
+            
+          
+        
+        
+          AHBRSTR
+          AHBRSTR
+          AHB peripheral reset register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CRYPRST
+              Crypto module reset
+              24
+              1
+            
+            
+              RNGRST
+              Random Number Generator module
+              reset
+              20
+              1
+            
+            
+              TOUCHRST
+              Touch Sensing reset
+              16
+              1
+            
+            
+              CRCRST
+              Test integration module
+              reset
+              12
+              1
+            
+            
+              MIFRST
+              Memory interface reset
+              8
+              1
+            
+            
+              DMARST
+              DMA reset
+              0
+              1
+            
+          
+        
+        
+          APB2RSTR
+          APB2RSTR
+          APB2 peripheral reset register
+          0x24
+          0x20
+          read-write
+          0x000000000
+          
+            
+              DBGRST
+              DBG reset
+              22
+              1
+            
+            
+              USART1RST
+              USART1 reset
+              14
+              1
+            
+            
+              SPI1RST
+              SPI 1 reset
+              12
+              1
+            
+            
+              ADCRST
+              ADC interface reset
+              9
+              1
+            
+            
+              TM12RST
+              TIM22 timer reset
+              5
+              1
+            
+            
+              TIM21RST
+              TIM21 timer reset
+              2
+              1
+            
+            
+              SYSCFGRST
+              System configuration controller
+              reset
+              0
+              1
+            
+          
+        
+        
+          APB1RSTR
+          APB1RSTR
+          APB1 peripheral reset register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LPTIM1RST
+              Low power timer reset
+              31
+              1
+            
+            
+              DACRST
+              DAC interface reset
+              29
+              1
+            
+            
+              PWRRST
+              Power interface reset
+              28
+              1
+            
+            
+              CRSRST
+              Clock recovery system
+              reset
+              27
+              1
+            
+            
+              USBRST
+              USB reset
+              23
+              1
+            
+            
+              I2C2RST
+              I2C2 reset
+              22
+              1
+            
+            
+              I2C1RST
+              I2C1 reset
+              21
+              1
+            
+            
+              LPUART1RST
+              LPUART1 reset
+              18
+              1
+            
+            
+              LPUART12RST
+              UART2 reset
+              17
+              1
+            
+            
+              SPI2RST
+              SPI2 reset
+              14
+              1
+            
+            
+              WWDRST
+              Window watchdog reset
+              11
+              1
+            
+            
+              TIM6RST
+              Timer 6 reset
+              4
+              1
+            
+            
+              TIM2RST
+              Timer2 reset
+              0
+              1
+            
+            
+              TIM3RST
+              Timer3 reset
+              1
+              1
+            
+            
+              TIM7RST
+              Timer 7 reset
+              5
+              1
+            
+            
+              USART4RST
+              USART4 reset
+              19
+              1
+            
+            
+              USART5RST
+              USART5 reset
+              20
+              1
+            
+            
+              I2C3RST
+              I2C3 reset
+              30
+              1
+            
+          
+        
+        
+          IOPENR
+          IOPENR
+          GPIO clock enable register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IOPHEN
+              I/O port H clock enable
+              bit
+              7
+              1
+            
+            
+              IOPDEN
+              I/O port D clock enable
+              bit
+              3
+              1
+            
+            
+              IOPCEN
+              IO port A clock enable bit
+              2
+              1
+            
+            
+              IOPBEN
+              IO port B clock enable bit
+              1
+              1
+            
+            
+              IOPAEN
+              IO port A clock enable bit
+              0
+              1
+            
+            
+              IOPEEN
+              I/O port E clock enable
+              bit
+              4
+              1
+            
+          
+        
+        
+          AHBENR
+          AHBENR
+          AHB peripheral clock enable
+          register
+          0x30
+          0x20
+          read-write
+          0x00000100
+          
+            
+              CRYPEN
+              Crypto clock enable bit
+              24
+              1
+            
+            
+              RNGEN
+              Random Number Generator clock enable
+              bit
+              20
+              1
+            
+            
+              TOUCHEN
+              Touch Sensing clock enable
+              bit
+              16
+              1
+            
+            
+              CRCEN
+              CRC clock enable bit
+              12
+              1
+            
+            
+              MIFEN
+              NVM interface clock enable
+              bit
+              8
+              1
+            
+            
+              DMAEN
+              DMA clock enable bit
+              0
+              1
+            
+          
+        
+        
+          APB2ENR
+          APB2ENR
+          APB2 peripheral clock enable
+          register
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              DBGEN
+              DBG clock enable bit
+              22
+              1
+            
+            
+              USART1EN
+              USART1 clock enable bit
+              14
+              1
+            
+            
+              SPI1EN
+              SPI1 clock enable bit
+              12
+              1
+            
+            
+              ADCEN
+              ADC clock enable bit
+              9
+              1
+            
+            
+              MIFIEN
+              MiFaRe Firewall clock enable
+              bit
+              7
+              1
+            
+            
+              TIM22EN
+              TIM22 timer clock enable
+              bit
+              5
+              1
+            
+            
+              TIM21EN
+              TIM21 timer clock enable
+              bit
+              2
+              1
+            
+            
+              SYSCFGEN
+              System configuration controller clock
+              enable bit
+              0
+              1
+            
+          
+        
+        
+          APB1ENR
+          APB1ENR
+          APB1 peripheral clock enable
+          register
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LPTIM1EN
+              Low power timer clock enable
+              bit
+              31
+              1
+            
+            
+              DACEN
+              DAC interface clock enable
+              bit
+              29
+              1
+            
+            
+              PWREN
+              Power interface clock enable
+              bit
+              28
+              1
+            
+            
+              CRSEN
+              Clock recovery system clock enable
+              bit
+              27
+              1
+            
+            
+              USBEN
+              USB clock enable bit
+              23
+              1
+            
+            
+              I2C2EN
+              I2C2 clock enable bit
+              22
+              1
+            
+            
+              I2C1EN
+              I2C1 clock enable bit
+              21
+              1
+            
+            
+              LPUART1EN
+              LPUART1 clock enable bit
+              18
+              1
+            
+            
+              USART2EN
+              UART2 clock enable bit
+              17
+              1
+            
+            
+              SPI2EN
+              SPI2 clock enable bit
+              14
+              1
+            
+            
+              WWDGEN
+              Window watchdog clock enable
+              bit
+              11
+              1
+            
+            
+              TIM6EN
+              Timer 6 clock enable bit
+              4
+              1
+            
+            
+              TIM2EN
+              Timer2 clock enable bit
+              0
+              1
+            
+            
+              TIM3EN
+              Timer3 clock enable bit
+              1
+              1
+            
+            
+              TIM7EN
+              Timer 7 clock enable bit
+              5
+              1
+            
+            
+              USART4EN
+              USART4 clock enable bit
+              19
+              1
+            
+            
+              USART5EN
+              USART5 clock enable bit
+              20
+              1
+            
+            
+              I2C3EN
+              I2C3 clock enable bit
+              30
+              1
+            
+          
+        
+        
+          IOPSMEN
+          IOPSMEN
+          GPIO clock enable in sleep mode
+          register
+          0x3C
+          0x20
+          read-write
+          0x0000008F
+          
+            
+              IOPHSMEN
+              IOPHSMEN
+              7
+              1
+            
+            
+              IOPDSMEN
+              IOPDSMEN
+              3
+              1
+            
+            
+              IOPCSMEN
+              IOPCSMEN
+              2
+              1
+            
+            
+              IOPBSMEN
+              IOPBSMEN
+              1
+              1
+            
+            
+              IOPASMEN
+              IOPASMEN
+              0
+              1
+            
+            
+              IOPESMEN
+              Port E clock enable during Sleep mode
+              bit
+              4
+              1
+            
+          
+        
+        
+          AHBSMENR
+          AHBSMENR
+          AHB peripheral clock enable in sleep mode
+          register
+          0x40
+          0x20
+          read-write
+          0x01111301
+          
+            
+              CRYPSMEN
+              Crypto clock enable during sleep mode
+              bit
+              24
+              1
+            
+            
+              RNGSMEN
+              Random Number Generator clock enable
+              during sleep mode bit
+              20
+              1
+            
+            
+              TOUCHSMEN
+              Touch Sensing clock enable during sleep
+              mode bit
+              16
+              1
+            
+            
+              CRCSMEN
+              CRC clock enable during sleep mode
+              bit
+              12
+              1
+            
+            
+              SRAMSMEN
+              SRAM interface clock enable during sleep
+              mode bit
+              9
+              1
+            
+            
+              MIFSMEN
+              NVM interface clock enable during sleep
+              mode bit
+              8
+              1
+            
+            
+              DMASMEN
+              DMA clock enable during sleep mode
+              bit
+              0
+              1
+            
+          
+        
+        
+          APB2SMENR
+          APB2SMENR
+          APB2 peripheral clock enable in sleep mode
+          register
+          0x44
+          0x20
+          read-write
+          0x00405225
+          
+            
+              DBGSMEN
+              DBG clock enable during sleep mode
+              bit
+              22
+              1
+            
+            
+              USART1SMEN
+              USART1 clock enable during sleep mode
+              bit
+              14
+              1
+            
+            
+              SPI1SMEN
+              SPI1 clock enable during sleep mode
+              bit
+              12
+              1
+            
+            
+              ADCSMEN
+              ADC clock enable during sleep mode
+              bit
+              9
+              1
+            
+            
+              TIM22SMEN
+              TIM22 timer clock enable during sleep
+              mode bit
+              5
+              1
+            
+            
+              TIM21SMEN
+              TIM21 timer clock enable during sleep
+              mode bit
+              2
+              1
+            
+            
+              SYSCFGSMEN
+              System configuration controller clock
+              enable during sleep mode bit
+              0
+              1
+            
+          
+        
+        
+          APB1SMENR
+          APB1SMENR
+          APB1 peripheral clock enable in sleep mode
+          register
+          0x48
+          0x20
+          read-write
+          0xB8E64A11
+          
+            
+              LPTIM1SMEN
+              Low power timer clock enable during
+              sleep mode bit
+              31
+              1
+            
+            
+              DACSMEN
+              DAC interface clock enable during sleep
+              mode bit
+              29
+              1
+            
+            
+              PWRSMEN
+              Power interface clock enable during
+              sleep mode bit
+              28
+              1
+            
+            
+              CRSSMEN
+              Clock recovery system clock enable
+              during sleep mode bit
+              27
+              1
+            
+            
+              USBSMEN
+              USB clock enable during sleep mode
+              bit
+              23
+              1
+            
+            
+              I2C2SMEN
+              I2C2 clock enable during sleep mode
+              bit
+              22
+              1
+            
+            
+              I2C1SMEN
+              I2C1 clock enable during sleep mode
+              bit
+              21
+              1
+            
+            
+              LPUART1SMEN
+              LPUART1 clock enable during sleep mode
+              bit
+              18
+              1
+            
+            
+              USART2SMEN
+              UART2 clock enable during sleep mode
+              bit
+              17
+              1
+            
+            
+              SPI2SMEN
+              SPI2 clock enable during sleep mode
+              bit
+              14
+              1
+            
+            
+              WWDGSMEN
+              Window watchdog clock enable during
+              sleep mode bit
+              11
+              1
+            
+            
+              TIM6SMEN
+              Timer 6 clock enable during sleep mode
+              bit
+              4
+              1
+            
+            
+              TIM2SMEN
+              Timer2 clock enable during sleep mode
+              bit
+              0
+              1
+            
+            
+              TIM3SMEN
+              Timer3 clock enable during Sleep mode
+              bit
+              1
+              1
+            
+            
+              TIM7SMEN
+              Timer 7 clock enable during Sleep mode
+              bit
+              5
+              1
+            
+            
+              USART4SMEN
+              USART4 clock enable during Sleep mode
+              bit
+              19
+              1
+            
+            
+              USART5SMEN
+              USART5 clock enable during Sleep mode
+              bit
+              20
+              1
+            
+            
+              I2C3SMEN
+              2C3 clock enable during Sleep mode
+              bit
+              30
+              1
+            
+          
+        
+        
+          CCIPR
+          CCIPR
+          Clock configuration register
+          0x4C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              HSI48MSEL
+              48 MHz HSI48 clock source selection
+              bit
+              26
+              1
+            
+            
+              LPTIM1SEL1
+              Low Power Timer clock source selection
+              bits
+              19
+              1
+            
+            
+              LPTIM1SEL0
+              LPTIM1SEL0
+              18
+              1
+            
+            
+              I2C1SEL1
+              I2C1 clock source selection
+              bits
+              13
+              1
+            
+            
+              I2C1SEL0
+              I2C1SEL0
+              12
+              1
+            
+            
+              LPUART1SEL1
+              LPUART1 clock source selection
+              bits
+              11
+              1
+            
+            
+              LPUART1SEL0
+              LPUART1SEL0
+              10
+              1
+            
+            
+              USART2SEL1
+              USART2 clock source selection
+              bits
+              3
+              1
+            
+            
+              USART2SEL0
+              USART2SEL0
+              2
+              1
+            
+            
+              USART1SEL1
+              USART1 clock source selection
+              bits
+              1
+              1
+            
+            
+              USART1SEL0
+              USART1SEL0
+              0
+              1
+            
+            
+              I2C3SEL
+              I2C3 clock source selection
+              bits
+              16
+              2
+            
+          
+        
+        
+          CSR
+          CSR
+          Control and status register
+          0x50
+          0x20
+          0x0C000000
+          
+            
+              LPWRSTF
+              Low-power reset flag
+              31
+              1
+              read-write
+            
+            
+              WWDGRSTF
+              Window watchdog reset flag
+              30
+              1
+              read-write
+            
+            
+              IWDGRSTF
+              Independent watchdog reset
+              flag
+              29
+              1
+              read-write
+            
+            
+              SFTRSTF
+              Software reset flag
+              28
+              1
+              read-write
+            
+            
+              PORRSTF
+              POR/PDR reset flag
+              27
+              1
+              read-write
+            
+            
+              PINRSTF
+              PIN reset flag
+              26
+              1
+              read-write
+            
+            
+              OBLRSTF
+              OBLRSTF
+              25
+              1
+              read-write
+            
+            
+              RMVF
+              Remove reset flag
+              24
+              1
+              read-write
+            
+            
+              RTCRST
+              RTC software reset bit
+              19
+              1
+              read-write
+            
+            
+              RTCEN
+              RTC clock enable bit
+              18
+              1
+              read-write
+            
+            
+              RTCSEL
+              RTC and LCD clock source selection
+              bits
+              16
+              2
+              read-write
+            
+            
+              CSSLSED
+              CSS on LSE failure detection
+              flag
+              14
+              1
+              read-write
+            
+            
+              CSSLSEON
+              CSSLSEON
+              13
+              1
+              read-write
+            
+            
+              LSEDRV
+              LSEDRV
+              11
+              2
+              read-write
+            
+            
+              LSEBYP
+              External low-speed oscillator bypass
+              bit
+              10
+              1
+              read-write
+            
+            
+              LSERDY
+              External low-speed oscillator ready
+              bit
+              9
+              1
+              read-only
+            
+            
+              LSEON
+              External low-speed oscillator enable
+              bit
+              8
+              1
+              read-write
+            
+            
+              LSIRDY
+              Internal low-speed oscillator ready
+              bit
+              1
+              1
+              read-write
+            
+            
+              LSION
+              Internal low-speed oscillator
+              enable
+              0
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      SYSCFG_COMP
+      System configuration controller and
+      Comparator
+      SYSCFG
+      0x40010000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CFGR1
+          CFGR1
+          SYSCFG configuration register
+          1
+          0x0
+          0x20
+          0x00000000
+          
+            
+              BOOT_MODE
+              Boot mode selected by the boot pins
+              status bits
+              8
+              2
+              read-only
+            
+            
+              MEM_MODE
+              Memory mapping selection
+              bits
+              0
+              2
+              read-write
+            
+          
+        
+        
+          CFGR2
+          CFGR2
+          SYSCFG configuration register
+          2
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              I2C2_FMP
+              I2C2 Fm+ drive capability enable
+              bit
+              13
+              1
+            
+            
+              I2C1_FMP
+              I2C1 Fm+ drive capability enable
+              bit
+              12
+              1
+            
+            
+              I2C_PB9_FMP
+              Fm+ drive capability on PB9 enable
+              bit
+              11
+              1
+            
+            
+              I2C_PB8_FMP
+              Fm+ drive capability on PB8 enable
+              bit
+              10
+              1
+            
+            
+              I2C_PB7_FMP
+              Fm+ drive capability on PB7 enable
+              bit
+              9
+              1
+            
+            
+              I2C_PB6_FMP
+              Fm+ drive capability on PB6 enable
+              bit
+              8
+              1
+            
+            
+              FWDISEN
+              Firewall disable bit
+              0
+              1
+            
+          
+        
+        
+          EXTICR1
+          EXTICR1
+          external interrupt configuration register
+          1
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI3
+              EXTI x configuration (x = 0 to
+              3)
+              12
+              4
+            
+            
+              EXTI2
+              EXTI x configuration (x = 0 to
+              3)
+              8
+              4
+            
+            
+              EXTI1
+              EXTI x configuration (x = 0 to
+              3)
+              4
+              4
+            
+            
+              EXTI0
+              EXTI x configuration (x = 0 to
+              3)
+              0
+              4
+            
+          
+        
+        
+          EXTICR2
+          EXTICR2
+          external interrupt configuration register
+          2
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI7
+              EXTI x configuration (x = 4 to
+              7)
+              12
+              4
+            
+            
+              EXTI6
+              EXTI x configuration (x = 4 to
+              7)
+              8
+              4
+            
+            
+              EXTI5
+              EXTI x configuration (x = 4 to
+              7)
+              4
+              4
+            
+            
+              EXTI4
+              EXTI x configuration (x = 4 to
+              7)
+              0
+              4
+            
+          
+        
+        
+          EXTICR3
+          EXTICR3
+          external interrupt configuration register
+          3
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI11
+              EXTI x configuration (x = 8 to
+              11)
+              12
+              4
+            
+            
+              EXTI10
+              EXTI10
+              8
+              4
+            
+            
+              EXTI9
+              EXTI x configuration (x = 8 to
+              11)
+              4
+              4
+            
+            
+              EXTI8
+              EXTI x configuration (x = 8 to
+              11)
+              0
+              4
+            
+          
+        
+        
+          EXTICR4
+          EXTICR4
+          external interrupt configuration register
+          4
+          0x14
+          0x20
+          read-write
+          0x0000
+          
+            
+              EXTI15
+              EXTI x configuration (x = 12 to
+              15)
+              12
+              4
+            
+            
+              EXTI14
+              EXTI14
+              8
+              4
+            
+            
+              EXTI13
+              EXTI13
+              4
+              4
+            
+            
+              EXTI12
+              EXTI12
+              0
+              4
+            
+          
+        
+        
+          CFGR3
+          CFGR3
+          SYSCFG configuration register
+          3
+          0x20
+          0x20
+          0x00000000
+          
+            
+              REF_LOCK
+              REF_CTRL lock bit
+              31
+              1
+              write-only
+            
+            
+              VREFINT_RDYF
+              VREFINT ready flag
+              30
+              1
+              read-only
+            
+            
+              VREFINT_COMP_RDYF
+              VREFINT for comparator ready
+              flag
+              29
+              1
+              read-only
+            
+            
+              VREFINT_ADC_RDYF
+              VREFINT for ADC ready flag
+              28
+              1
+              read-only
+            
+            
+              SENSOR_ADC_RDYF
+              Sensor for ADC ready flag
+              27
+              1
+              read-only
+            
+            
+              REF_RC48MHz_RDYF
+              VREFINT for 48 MHz RC oscillator ready
+              flag
+              26
+              1
+              read-only
+            
+            
+              ENREF_RC48MHz
+              VREFINT reference for 48 MHz RC
+              oscillator enable bit
+              13
+              1
+              read-write
+            
+            
+              ENBUF_VREFINT_COMP
+              VREFINT reference for comparator 2
+              enable bit
+              12
+              1
+              read-write
+            
+            
+              ENBUF_SENSOR_ADC
+              Sensor reference for ADC enable
+              bit
+              9
+              1
+              read-write
+            
+            
+              ENBUF_BGAP_ADC
+              VREFINT reference for ADC enable
+              bit
+              8
+              1
+              read-write
+            
+            
+              SEL_VREF_OUT
+              BGAP_ADC connection bit
+              4
+              2
+              read-write
+            
+            
+              EN_BGAP
+              Vref Enable bit
+              0
+              1
+              read-write
+            
+          
+        
+        
+          COMP1_CSR
+          COMP1_CSR
+          Comparator 1 control and status
+          register
+          0x18
+          0x20
+          0x00000000
+          
+            
+              COMP1LOCK
+              COMP1_CSR register lock
+              bit
+              31
+              1
+              read-only
+            
+            
+              COMP1VALUE
+              Comparator 1 output status
+              bit
+              30
+              1
+              read-only
+            
+            
+              COMP1POLARITY
+              Comparator 1 polarity selection
+              bit
+              15
+              1
+              read-write
+            
+            
+              COMP1LPTIMIN1
+              Comparator 1 LPTIM input propagation
+              bit
+              12
+              1
+              read-write
+            
+            
+              COMP1WM
+              Comparator 1 window mode selection
+              bit
+              8
+              1
+              read-write
+            
+            
+              COMP1INNSEL
+              Comparator 1 Input Minus connection
+              configuration bit
+              4
+              2
+              read-write
+            
+            
+              COMP1EN
+              Comparator 1 enable bit
+              0
+              1
+              read-write
+            
+          
+        
+        
+          COMP2_CSR
+          COMP2_CSR
+          Comparator 2 control and status
+          register
+          0x1C
+          0x20
+          0x00000000
+          
+            
+              COMP2LOCK
+              COMP2_CSR register lock
+              bit
+              31
+              1
+              read-only
+            
+            
+              COMP2VALUE
+              Comparator 2 output status
+              bit
+              20
+              1
+              read-only
+            
+            
+              COMP2POLARITY
+              Comparator 2 polarity selection
+              bit
+              15
+              1
+              read-write
+            
+            
+              COMP2LPTIMIN1
+              Comparator 2 LPTIM input 1 propagation
+              bit
+              13
+              1
+              read-write
+            
+            
+              COMP2LPTIMIN2
+              Comparator 2 LPTIM input 2 propagation
+              bit
+              12
+              1
+              read-write
+            
+            
+              COMP2INPSEL
+              Comparator 2 Input Plus connection
+              configuration bit
+              8
+              3
+              read-write
+            
+            
+              COMP2INNSEL
+              Comparator 2 Input Minus connection
+              configuration bit
+              4
+              3
+              read-write
+            
+            
+              COMP2SPEED
+              Comparator 2 power mode selection
+              bit
+              3
+              1
+              read-write
+            
+            
+              COMP2EN
+              Comparator 2 enable bit
+              0
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      SPI1
+      Serial peripheral interface
+      SPI
+      0x40013000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              BIDIMODE
+              Bidirectional data mode
+              enable
+              15
+              1
+            
+            
+              BIDIOE
+              Output enable in bidirectional
+              mode
+              14
+              1
+            
+            
+              CRCEN
+              Hardware CRC calculation
+              enable
+              13
+              1
+            
+            
+              CRCNEXT
+              CRC transfer next
+              12
+              1
+            
+            
+              DFF
+              Data frame format
+              11
+              1
+            
+            
+              RXONLY
+              Receive only
+              10
+              1
+            
+            
+              SSM
+              Software slave management
+              9
+              1
+            
+            
+              SSI
+              Internal slave select
+              8
+              1
+            
+            
+              LSBFIRST
+              Frame format
+              7
+              1
+            
+            
+              SPE
+              SPI enable
+              6
+              1
+            
+            
+              BR
+              Baud rate control
+              3
+              3
+            
+            
+              MSTR
+              Master selection
+              2
+              1
+            
+            
+              CPOL
+              Clock polarity
+              1
+              1
+            
+            
+              CPHA
+              Clock phase
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              RXDMAEN
+              Rx buffer DMA enable
+              0
+              1
+            
+            
+              TXDMAEN
+              Tx buffer DMA enable
+              1
+              1
+            
+            
+              SSOE
+              SS output enable
+              2
+              1
+            
+            
+              FRF
+              Frame format
+              4
+              1
+            
+            
+              ERRIE
+              Error interrupt enable
+              5
+              1
+            
+            
+              RXNEIE
+              RX buffer not empty interrupt
+              enable
+              6
+              1
+            
+            
+              TXEIE
+              Tx buffer empty interrupt
+              enable
+              7
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x8
+          0x20
+          0x0002
+          
+            
+              RXNE
+              Receive buffer not empty
+              0
+              1
+              read-only
+            
+            
+              TXE
+              Transmit buffer empty
+              1
+              1
+              read-only
+            
+            
+              CHSIDE
+              Channel side
+              2
+              1
+              read-only
+            
+            
+              UDR
+              Underrun flag
+              3
+              1
+              read-only
+            
+            
+              CRCERR
+              CRC error flag
+              4
+              1
+              read-write
+            
+            
+              MODF
+              Mode fault
+              5
+              1
+              read-only
+            
+            
+              OVR
+              Overrun flag
+              6
+              1
+              read-only
+            
+            
+              BSY
+              Busy flag
+              7
+              1
+              read-only
+            
+            
+              TIFRFE
+              TI frame format error
+              8
+              1
+              read-only
+            
+          
+        
+        
+          DR
+          DR
+          data register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              DR
+              Data register
+              0
+              16
+            
+          
+        
+        
+          CRCPR
+          CRCPR
+          CRC polynomial register
+          0x10
+          0x20
+          read-write
+          0x0007
+          
+            
+              CRCPOLY
+              CRC polynomial register
+              0
+              16
+            
+          
+        
+        
+          RXCRCR
+          RXCRCR
+          RX CRC register
+          0x14
+          0x20
+          read-only
+          0x0000
+          
+            
+              RxCRC
+              Rx CRC register
+              0
+              16
+            
+          
+        
+        
+          TXCRCR
+          TXCRCR
+          TX CRC register
+          0x18
+          0x20
+          read-only
+          0x0000
+          
+            
+              TxCRC
+              Tx CRC register
+              0
+              16
+            
+          
+        
+        
+          I2SCFGR
+          I2SCFGR
+          I2S configuration register
+          0x1C
+          0x20
+          read-write
+          0x0000
+          
+            
+              I2SMOD
+              I2S mode selection
+              11
+              1
+            
+            
+              I2SE
+              I2S Enable
+              10
+              1
+            
+            
+              I2SCFG
+              I2S configuration mode
+              8
+              2
+            
+            
+              PCMSYNC
+              PCM frame synchronization
+              7
+              1
+            
+            
+              I2SSTD
+              I2S standard selection
+              4
+              2
+            
+            
+              CKPOL
+              Steady state clock
+              polarity
+              3
+              1
+            
+            
+              DATLEN
+              Data length to be
+              transferred
+              1
+              2
+            
+            
+              CHLEN
+              Channel length (number of bits per audio
+              channel)
+              0
+              1
+            
+          
+        
+        
+          I2SPR
+          I2SPR
+          I2S prescaler register
+          0x20
+          0x20
+          read-write
+          0x00000010
+          
+            
+              MCKOE
+              Master clock output enable
+              9
+              1
+            
+            
+              ODD
+              Odd factor for the
+              prescaler
+              8
+              1
+            
+            
+              I2SDIV
+              I2S Linear prescaler
+              0
+              8
+            
+          
+        
+      
+    
+    
+      SPI2
+      0x40003800
+      
+        SPI1
+        SPI1_global_interrupt
+        25
+      
+    
+    
+      I2C1
+      Inter-integrated circuit
+      I2C
+      0x40005400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        SPI2
+        SPI2 global interrupt
+        26
+      
+      
+        
+          CR1
+          CR1
+          Control register 1
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PE
+              Peripheral enable
+              0
+              1
+            
+            
+              TXIE
+              TX Interrupt enable
+              1
+              1
+            
+            
+              RXIE
+              RX Interrupt enable
+              2
+              1
+            
+            
+              ADDRIE
+              Address match interrupt enable (slave
+              only)
+              3
+              1
+            
+            
+              NACKIE
+              Not acknowledge received interrupt
+              enable
+              4
+              1
+            
+            
+              STOPIE
+              STOP detection Interrupt
+              enable
+              5
+              1
+            
+            
+              TCIE
+              Transfer Complete interrupt
+              enable
+              6
+              1
+            
+            
+              ERRIE
+              Error interrupts enable
+              7
+              1
+            
+            
+              DNF
+              Digital noise filter
+              8
+              4
+            
+            
+              ANFOFF
+              Analog noise filter OFF
+              12
+              1
+            
+            
+              TXDMAEN
+              DMA transmission requests
+              enable
+              14
+              1
+            
+            
+              RXDMAEN
+              DMA reception requests
+              enable
+              15
+              1
+            
+            
+              SBC
+              Slave byte control
+              16
+              1
+            
+            
+              NOSTRETCH
+              Clock stretching disable
+              17
+              1
+            
+            
+              WUPEN
+              Wakeup from STOP enable
+              18
+              1
+            
+            
+              GCEN
+              General call enable
+              19
+              1
+            
+            
+              SMBHEN
+              SMBus Host address enable
+              20
+              1
+            
+            
+              SMBDEN
+              SMBus Device Default address
+              enable
+              21
+              1
+            
+            
+              ALERTEN
+              SMBUS alert enable
+              22
+              1
+            
+            
+              PECEN
+              PEC enable
+              23
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          Control register 2
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PECBYTE
+              Packet error checking byte
+              26
+              1
+            
+            
+              AUTOEND
+              Automatic end mode (master
+              mode)
+              25
+              1
+            
+            
+              RELOAD
+              NBYTES reload mode
+              24
+              1
+            
+            
+              NBYTES
+              Number of bytes
+              16
+              8
+            
+            
+              NACK
+              NACK generation (slave
+              mode)
+              15
+              1
+            
+            
+              STOP
+              Stop generation (master
+              mode)
+              14
+              1
+            
+            
+              START
+              Start generation
+              13
+              1
+            
+            
+              HEAD10R
+              10-bit address header only read
+              direction (master receiver mode)
+              12
+              1
+            
+            
+              ADD10
+              10-bit addressing mode (master
+              mode)
+              11
+              1
+            
+            
+              RD_WRN
+              Transfer direction (master
+              mode)
+              10
+              1
+            
+            
+              SADD
+              Slave address bit (master
+              mode)
+              0
+              10
+            
+          
+        
+        
+          OAR1
+          OAR1
+          Own address register 1
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OA1
+              Interface address
+              0
+              10
+            
+            
+              OA1MODE
+              Own Address 1 10-bit mode
+              10
+              1
+            
+            
+              OA1EN
+              Own Address 1 enable
+              15
+              1
+            
+          
+        
+        
+          OAR2
+          OAR2
+          Own address register 2
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OA2
+              Interface address
+              1
+              7
+            
+            
+              OA2MSK
+              Own Address 2 masks
+              8
+              3
+            
+            
+              OA2EN
+              Own Address 2 enable
+              15
+              1
+            
+          
+        
+        
+          TIMINGR
+          TIMINGR
+          Timing register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SCLL
+              SCL low period (master
+              mode)
+              0
+              8
+            
+            
+              SCLH
+              SCL high period (master
+              mode)
+              8
+              8
+            
+            
+              SDADEL
+              Data hold time
+              16
+              4
+            
+            
+              SCLDEL
+              Data setup time
+              20
+              4
+            
+            
+              PRESC
+              Timing prescaler
+              28
+              4
+            
+          
+        
+        
+          TIMEOUTR
+          TIMEOUTR
+          Status register 1
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TIMEOUTA
+              Bus timeout A
+              0
+              12
+            
+            
+              TIDLE
+              Idle clock timeout
+              detection
+              12
+              1
+            
+            
+              TIMOUTEN
+              Clock timeout enable
+              15
+              1
+            
+            
+              TIMEOUTB
+              Bus timeout B
+              16
+              12
+            
+            
+              TEXTEN
+              Extended clock timeout
+              enable
+              31
+              1
+            
+          
+        
+        
+          ISR
+          ISR
+          Interrupt and Status register
+          0x18
+          0x20
+          0x00000001
+          
+            
+              ADDCODE
+              Address match code (Slave
+              mode)
+              17
+              7
+              read-only
+            
+            
+              DIR
+              Transfer direction (Slave
+              mode)
+              16
+              1
+              read-only
+            
+            
+              BUSY
+              Bus busy
+              15
+              1
+              read-only
+            
+            
+              ALERT
+              SMBus alert
+              13
+              1
+              read-only
+            
+            
+              TIMEOUT
+              Timeout or t_low detection
+              flag
+              12
+              1
+              read-only
+            
+            
+              PECERR
+              PEC Error in reception
+              11
+              1
+              read-only
+            
+            
+              OVR
+              Overrun/Underrun (slave
+              mode)
+              10
+              1
+              read-only
+            
+            
+              ARLO
+              Arbitration lost
+              9
+              1
+              read-only
+            
+            
+              BERR
+              Bus error
+              8
+              1
+              read-only
+            
+            
+              TCR
+              Transfer Complete Reload
+              7
+              1
+              read-only
+            
+            
+              TC
+              Transfer Complete (master
+              mode)
+              6
+              1
+              read-only
+            
+            
+              STOPF
+              Stop detection flag
+              5
+              1
+              read-only
+            
+            
+              NACKF
+              Not acknowledge received
+              flag
+              4
+              1
+              read-only
+            
+            
+              ADDR
+              Address matched (slave
+              mode)
+              3
+              1
+              read-only
+            
+            
+              RXNE
+              Receive data register not empty
+              (receivers)
+              2
+              1
+              read-only
+            
+            
+              TXIS
+              Transmit interrupt status
+              (transmitters)
+              1
+              1
+              read-write
+            
+            
+              TXE
+              Transmit data register empty
+              (transmitters)
+              0
+              1
+              read-write
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt clear register
+          0x1C
+          0x20
+          write-only
+          0x00000000
+          
+            
+              ALERTCF
+              Alert flag clear
+              13
+              1
+            
+            
+              TIMOUTCF
+              Timeout detection flag
+              clear
+              12
+              1
+            
+            
+              PECCF
+              PEC Error flag clear
+              11
+              1
+            
+            
+              OVRCF
+              Overrun/Underrun flag
+              clear
+              10
+              1
+            
+            
+              ARLOCF
+              Arbitration lost flag
+              clear
+              9
+              1
+            
+            
+              BERRCF
+              Bus error flag clear
+              8
+              1
+            
+            
+              STOPCF
+              Stop detection flag clear
+              5
+              1
+            
+            
+              NACKCF
+              Not Acknowledge flag clear
+              4
+              1
+            
+            
+              ADDRCF
+              Address Matched flag clear
+              3
+              1
+            
+          
+        
+        
+          PECR
+          PECR
+          PEC register
+          0x20
+          0x20
+          read-only
+          0x00000000
+          
+            
+              PEC
+              Packet error checking
+              register
+              0
+              8
+            
+          
+        
+        
+          RXDR
+          RXDR
+          Receive data register
+          0x24
+          0x20
+          read-only
+          0x00000000
+          
+            
+              RXDATA
+              8-bit receive data
+              0
+              8
+            
+          
+        
+        
+          TXDR
+          TXDR
+          Transmit data register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TXDATA
+              8-bit transmit data
+              0
+              8
+            
+          
+        
+      
+    
+    
+      I2C2
+      0x40005800
+      
+        I2C1
+        I2C1 global interrupt
+        23
+      
+      
+        I2C2
+        I2C2 global interrupt
+        24
+      
+    
+    
+      I2C3
+      0x40007800
+    
+    
+      PWR
+      Power control
+      PWR
+      0x40007000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        I2C3
+        I2C3 global interrupt
+        21
+      
+      
+        
+          CR
+          CR
+          power control register
+          0x0
+          0x20
+          read-write
+          0x00001000
+          
+            
+              LPDS
+              Low-power deep sleep
+              0
+              1
+            
+            
+              PDDS
+              Power down deepsleep
+              1
+              1
+            
+            
+              CWUF
+              Clear wakeup flag
+              2
+              1
+            
+            
+              CSBF
+              Clear standby flag
+              3
+              1
+            
+            
+              PVDE
+              Power voltage detector
+              enable
+              4
+              1
+            
+            
+              PLS
+              PVD level selection
+              5
+              3
+            
+            
+              DBP
+              Disable backup domain write
+              protection
+              8
+              1
+            
+            
+              ULP
+              Ultra-low-power mode
+              9
+              1
+            
+            
+              FWU
+              Fast wakeup
+              10
+              1
+            
+            
+              VOS
+              Voltage scaling range
+              selection
+              11
+              2
+            
+            
+              DS_EE_KOFF
+              Deep sleep mode with Flash memory kept
+              off
+              13
+              1
+            
+            
+              LPRUN
+              Low power run mode
+              14
+              1
+            
+          
+        
+        
+          CSR
+          CSR
+          power control/status register
+          0x4
+          0x20
+          0x00000000
+          
+            
+              BRE
+              Backup regulator enable
+              9
+              1
+              read-write
+            
+            
+              EWUP
+              Enable WKUP pin
+              8
+              1
+              read-write
+            
+            
+              BRR
+              Backup regulator ready
+              3
+              1
+              read-only
+            
+            
+              PVDO
+              PVD output
+              2
+              1
+              read-only
+            
+            
+              SBF
+              Standby flag
+              1
+              1
+              read-only
+            
+            
+              WUF
+              Wakeup flag
+              0
+              1
+              read-only
+            
+            
+              VOSF
+              Voltage Scaling select
+              flag
+              4
+              1
+              read-only
+            
+            
+              REGLPF
+              Regulator LP flag
+              5
+              1
+              read-only
+            
+          
+        
+      
+    
+    
+      Flash
+      Flash
+      Flash
+      0x40022000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          ACR
+          ACR
+          Access control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              LATENCY
+              Latency
+              0
+              1
+            
+            
+              PRFTEN
+              Prefetch enable
+              1
+              1
+            
+            
+              SLEEP_PD
+              Flash mode during Sleep
+              3
+              1
+            
+            
+              RUN_PD
+              Flash mode during Run
+              4
+              1
+            
+            
+              DESAB_BUF
+              Disable Buffer
+              5
+              1
+            
+            
+              PRE_READ
+              Pre-read data address
+              6
+              1
+            
+          
+        
+        
+          PECR
+          PECR
+          Program/erase control register
+          0x4
+          0x20
+          read-write
+          0x00000007
+          
+            
+              PELOCK
+              FLASH_PECR and data EEPROM
+              lock
+              0
+              1
+            
+            
+              PRGLOCK
+              Program memory lock
+              1
+              1
+            
+            
+              OPTLOCK
+              Option bytes block lock
+              2
+              1
+            
+            
+              PROG
+              Program memory selection
+              3
+              1
+            
+            
+              DATA
+              Data EEPROM selection
+              4
+              1
+            
+            
+              FTDW
+              Fixed time data write for Byte, Half
+              Word and Word programming
+              8
+              1
+            
+            
+              ERASE
+              Page or Double Word erase
+              mode
+              9
+              1
+            
+            
+              FPRG
+              Half Page/Double Word programming
+              mode
+              10
+              1
+            
+            
+              PARALLELBANK
+              Parallel bank mode
+              15
+              1
+            
+            
+              EOPIE
+              End of programming interrupt
+              enable
+              16
+              1
+            
+            
+              ERRIE
+              Error interrupt enable
+              17
+              1
+            
+            
+              OBL_LAUNCH
+              Launch the option byte
+              loading
+              18
+              1
+            
+          
+        
+        
+          PDKEYR
+          PDKEYR
+          Power down key register
+          0x8
+          0x20
+          write-only
+          0x00000000
+          
+            
+              PDKEYR
+              RUN_PD in FLASH_ACR key
+              0
+              32
+            
+          
+        
+        
+          PEKEYR
+          PEKEYR
+          Program/erase key register
+          0xC
+          0x20
+          write-only
+          0x00000000
+          
+            
+              PEKEYR
+              FLASH_PEC and data EEPROM
+              key
+              0
+              32
+            
+          
+        
+        
+          PRGKEYR
+          PRGKEYR
+          Program memory key register
+          0x10
+          0x20
+          write-only
+          0x00000000
+          
+            
+              PRGKEYR
+              Program memory key
+              0
+              32
+            
+          
+        
+        
+          OPTKEYR
+          OPTKEYR
+          Option byte key register
+          0x14
+          0x20
+          write-only
+          0x00000000
+          
+            
+              OPTKEYR
+              Option byte key
+              0
+              32
+            
+          
+        
+        
+          SR
+          SR
+          Status register
+          0x18
+          0x20
+          0x00000004
+          
+            
+              BSY
+              Write/erase operations in
+              progress
+              0
+              1
+              read-only
+            
+            
+              EOP
+              End of operation
+              1
+              1
+              read-only
+            
+            
+              ENDHV
+              End of high voltage
+              2
+              1
+              read-only
+            
+            
+              READY
+              Flash memory module ready after low
+              power mode
+              3
+              1
+              read-only
+            
+            
+              WRPERR
+              Write protected error
+              8
+              1
+              read-write
+            
+            
+              PGAERR
+              Programming alignment
+              error
+              9
+              1
+              read-write
+            
+            
+              SIZERR
+              Size error
+              10
+              1
+              read-write
+            
+            
+              OPTVERR
+              Option validity error
+              11
+              1
+              read-write
+            
+            
+              RDERR
+              RDERR
+              14
+              1
+              read-write
+            
+            
+              NOTZEROERR
+              NOTZEROERR
+              16
+              1
+              read-write
+            
+            
+              FWWERR
+              FWWERR
+              17
+              1
+              read-write
+            
+          
+        
+        
+          OBR
+          OBR
+          Option byte register
+          0x1C
+          0x20
+          read-only
+          0x00F80000
+          
+            
+              RDPRT
+              Read protection
+              0
+              8
+            
+            
+              BOR_LEV
+              BOR_LEV
+              16
+              4
+            
+            
+              SPRMOD
+              Selection of protection mode of WPR
+              bits
+              8
+              1
+            
+          
+        
+        
+          WRPR
+          WRPR
+          Write protection register
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              WRP
+              Write protection
+              0
+              16
+            
+          
+        
+      
+    
+    
+      EXTI
+      External interrupt/event
+      controller
+      EXTI
+      0x40010400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        PVD
+        PVD through EXTI line detection
+        1
+      
+      
+        EXTI0_1
+        EXTI Line[1:0] interrupts
+        5
+      
+      
+        EXTI2_3
+        EXTI Line[3:2] interrupts
+        6
+      
+      
+        EXTI4_15
+        EXTI Line15 and EXTI4 interrupts
+        7
+      
+      
+        
+          IMR
+          IMR
+          Interrupt mask register
+          (EXTI_IMR)
+          0x0
+          0x20
+          read-write
+          0xFF840000
+          
+            
+              IM0
+              Interrupt Mask on line 0
+              0
+              1
+            
+            
+              IM1
+              Interrupt Mask on line 1
+              1
+              1
+            
+            
+              IM2
+              Interrupt Mask on line 2
+              2
+              1
+            
+            
+              IM3
+              Interrupt Mask on line 3
+              3
+              1
+            
+            
+              IM4
+              Interrupt Mask on line 4
+              4
+              1
+            
+            
+              IM5
+              Interrupt Mask on line 5
+              5
+              1
+            
+            
+              IM6
+              Interrupt Mask on line 6
+              6
+              1
+            
+            
+              IM7
+              Interrupt Mask on line 7
+              7
+              1
+            
+            
+              IM8
+              Interrupt Mask on line 8
+              8
+              1
+            
+            
+              IM9
+              Interrupt Mask on line 9
+              9
+              1
+            
+            
+              IM10
+              Interrupt Mask on line 10
+              10
+              1
+            
+            
+              IM11
+              Interrupt Mask on line 11
+              11
+              1
+            
+            
+              IM12
+              Interrupt Mask on line 12
+              12
+              1
+            
+            
+              IM13
+              Interrupt Mask on line 13
+              13
+              1
+            
+            
+              IM14
+              Interrupt Mask on line 14
+              14
+              1
+            
+            
+              IM15
+              Interrupt Mask on line 15
+              15
+              1
+            
+            
+              IM16
+              Interrupt Mask on line 16
+              16
+              1
+            
+            
+              IM17
+              Interrupt Mask on line 17
+              17
+              1
+            
+            
+              IM18
+              Interrupt Mask on line 18
+              18
+              1
+            
+            
+              IM19
+              Interrupt Mask on line 19
+              19
+              1
+            
+            
+              IM20
+              Interrupt Mask on line 20
+              20
+              1
+            
+            
+              IM21
+              Interrupt Mask on line 21
+              21
+              1
+            
+            
+              IM22
+              Interrupt Mask on line 22
+              22
+              1
+            
+            
+              IM23
+              Interrupt Mask on line 23
+              23
+              1
+            
+            
+              IM24
+              Interrupt Mask on line 24
+              24
+              1
+            
+            
+              IM25
+              Interrupt Mask on line 25
+              25
+              1
+            
+            
+              IM26
+              Interrupt Mask on line 27
+              26
+              1
+            
+            
+              IM28
+              Interrupt Mask on line 27
+              28
+              1
+            
+            
+              IM29
+              Interrupt Mask on line 27
+              29
+              1
+            
+          
+        
+        
+          EMR
+          EMR
+          Event mask register (EXTI_EMR)
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EM0
+              Event Mask on line 0
+              0
+              1
+            
+            
+              EM1
+              Event Mask on line 1
+              1
+              1
+            
+            
+              EM2
+              Event Mask on line 2
+              2
+              1
+            
+            
+              EM3
+              Event Mask on line 3
+              3
+              1
+            
+            
+              EM4
+              Event Mask on line 4
+              4
+              1
+            
+            
+              EM5
+              Event Mask on line 5
+              5
+              1
+            
+            
+              EM6
+              Event Mask on line 6
+              6
+              1
+            
+            
+              EM7
+              Event Mask on line 7
+              7
+              1
+            
+            
+              EM8
+              Event Mask on line 8
+              8
+              1
+            
+            
+              EM9
+              Event Mask on line 9
+              9
+              1
+            
+            
+              EM10
+              Event Mask on line 10
+              10
+              1
+            
+            
+              EM11
+              Event Mask on line 11
+              11
+              1
+            
+            
+              EM12
+              Event Mask on line 12
+              12
+              1
+            
+            
+              EM13
+              Event Mask on line 13
+              13
+              1
+            
+            
+              EM14
+              Event Mask on line 14
+              14
+              1
+            
+            
+              EM15
+              Event Mask on line 15
+              15
+              1
+            
+            
+              EM16
+              Event Mask on line 16
+              16
+              1
+            
+            
+              EM17
+              Event Mask on line 17
+              17
+              1
+            
+            
+              EM18
+              Event Mask on line 18
+              18
+              1
+            
+            
+              EM19
+              Event Mask on line 19
+              19
+              1
+            
+            
+              EM20
+              Event Mask on line 20
+              20
+              1
+            
+            
+              EM21
+              Event Mask on line 21
+              21
+              1
+            
+            
+              EM22
+              Event Mask on line 22
+              22
+              1
+            
+            
+              EM23
+              Event Mask on line 23
+              23
+              1
+            
+            
+              EM24
+              Event Mask on line 24
+              24
+              1
+            
+            
+              EM25
+              Event Mask on line 25
+              25
+              1
+            
+            
+              EM26
+              Event Mask on line 26
+              26
+              1
+            
+            
+              EM28
+              Event Mask on line 28
+              28
+              1
+            
+            
+              EM29
+              Event Mask on line 29
+              29
+              1
+            
+          
+        
+        
+          RTSR
+          RTSR
+          Rising Trigger selection register
+          (EXTI_RTSR)
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              RT0
+              Rising trigger event configuration of
+              line 0
+              0
+              1
+            
+            
+              RT1
+              Rising trigger event configuration of
+              line 1
+              1
+              1
+            
+            
+              RT2
+              Rising trigger event configuration of
+              line 2
+              2
+              1
+            
+            
+              RT3
+              Rising trigger event configuration of
+              line 3
+              3
+              1
+            
+            
+              RT4
+              Rising trigger event configuration of
+              line 4
+              4
+              1
+            
+            
+              RT5
+              Rising trigger event configuration of
+              line 5
+              5
+              1
+            
+            
+              RT6
+              Rising trigger event configuration of
+              line 6
+              6
+              1
+            
+            
+              RT7
+              Rising trigger event configuration of
+              line 7
+              7
+              1
+            
+            
+              RT8
+              Rising trigger event configuration of
+              line 8
+              8
+              1
+            
+            
+              RT9
+              Rising trigger event configuration of
+              line 9
+              9
+              1
+            
+            
+              RT10
+              Rising trigger event configuration of
+              line 10
+              10
+              1
+            
+            
+              RT11
+              Rising trigger event configuration of
+              line 11
+              11
+              1
+            
+            
+              RT12
+              Rising trigger event configuration of
+              line 12
+              12
+              1
+            
+            
+              RT13
+              Rising trigger event configuration of
+              line 13
+              13
+              1
+            
+            
+              RT14
+              Rising trigger event configuration of
+              line 14
+              14
+              1
+            
+            
+              RT15
+              Rising trigger event configuration of
+              line 15
+              15
+              1
+            
+            
+              RT16
+              Rising trigger event configuration of
+              line 16
+              16
+              1
+            
+            
+              RT17
+              Rising trigger event configuration of
+              line 17
+              17
+              1
+            
+            
+              RT19
+              Rising trigger event configuration of
+              line 19
+              19
+              1
+            
+            
+              RT20
+              Rising trigger event configuration of
+              line 20
+              20
+              1
+            
+            
+              RT21
+              Rising trigger event configuration of
+              line 21
+              21
+              1
+            
+            
+              RT22
+              Rising trigger event configuration of
+              line 22
+              22
+              1
+            
+          
+        
+        
+          FTSR
+          FTSR
+          Falling Trigger selection register
+          (EXTI_FTSR)
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              FT0
+              Falling trigger event configuration of
+              line 0
+              0
+              1
+            
+            
+              FT1
+              Falling trigger event configuration of
+              line 1
+              1
+              1
+            
+            
+              FT2
+              Falling trigger event configuration of
+              line 2
+              2
+              1
+            
+            
+              FT3
+              Falling trigger event configuration of
+              line 3
+              3
+              1
+            
+            
+              FT4
+              Falling trigger event configuration of
+              line 4
+              4
+              1
+            
+            
+              FT5
+              Falling trigger event configuration of
+              line 5
+              5
+              1
+            
+            
+              FT6
+              Falling trigger event configuration of
+              line 6
+              6
+              1
+            
+            
+              FT7
+              Falling trigger event configuration of
+              line 7
+              7
+              1
+            
+            
+              FT8
+              Falling trigger event configuration of
+              line 8
+              8
+              1
+            
+            
+              FT9
+              Falling trigger event configuration of
+              line 9
+              9
+              1
+            
+            
+              FT10
+              Falling trigger event configuration of
+              line 10
+              10
+              1
+            
+            
+              FT11
+              Falling trigger event configuration of
+              line 11
+              11
+              1
+            
+            
+              FT12
+              Falling trigger event configuration of
+              line 12
+              12
+              1
+            
+            
+              FT13
+              Falling trigger event configuration of
+              line 13
+              13
+              1
+            
+            
+              FT14
+              Falling trigger event configuration of
+              line 14
+              14
+              1
+            
+            
+              FT15
+              Falling trigger event configuration of
+              line 15
+              15
+              1
+            
+            
+              FT16
+              Falling trigger event configuration of
+              line 16
+              16
+              1
+            
+            
+              FT17
+              Falling trigger event configuration of
+              line 17
+              17
+              1
+            
+            
+              FT19
+              Falling trigger event configuration of
+              line 19
+              19
+              1
+            
+            
+              FT20
+              Falling trigger event configuration of
+              line 20
+              20
+              1
+            
+            
+              FT21
+              Falling trigger event configuration of
+              line 21
+              21
+              1
+            
+            
+              FT22
+              Falling trigger event configuration of
+              line 22
+              22
+              1
+            
+          
+        
+        
+          SWIER
+          SWIER
+          Software interrupt event register
+          (EXTI_SWIER)
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SWI0
+              Software Interrupt on line
+              0
+              0
+              1
+            
+            
+              SWI1
+              Software Interrupt on line
+              1
+              1
+              1
+            
+            
+              SWI2
+              Software Interrupt on line
+              2
+              2
+              1
+            
+            
+              SWI3
+              Software Interrupt on line
+              3
+              3
+              1
+            
+            
+              SWI4
+              Software Interrupt on line
+              4
+              4
+              1
+            
+            
+              SWI5
+              Software Interrupt on line
+              5
+              5
+              1
+            
+            
+              SWI6
+              Software Interrupt on line
+              6
+              6
+              1
+            
+            
+              SWI7
+              Software Interrupt on line
+              7
+              7
+              1
+            
+            
+              SWI8
+              Software Interrupt on line
+              8
+              8
+              1
+            
+            
+              SWI9
+              Software Interrupt on line
+              9
+              9
+              1
+            
+            
+              SWI10
+              Software Interrupt on line
+              10
+              10
+              1
+            
+            
+              SWI11
+              Software Interrupt on line
+              11
+              11
+              1
+            
+            
+              SWI12
+              Software Interrupt on line
+              12
+              12
+              1
+            
+            
+              SWI13
+              Software Interrupt on line
+              13
+              13
+              1
+            
+            
+              SWI14
+              Software Interrupt on line
+              14
+              14
+              1
+            
+            
+              SWI15
+              Software Interrupt on line
+              15
+              15
+              1
+            
+            
+              SWI16
+              Software Interrupt on line
+              16
+              16
+              1
+            
+            
+              SWI17
+              Software Interrupt on line
+              17
+              17
+              1
+            
+            
+              SWI19
+              Software Interrupt on line
+              19
+              19
+              1
+            
+            
+              SWI20
+              Software Interrupt on line
+              20
+              20
+              1
+            
+            
+              SWI21
+              Software Interrupt on line
+              21
+              21
+              1
+            
+            
+              SWI22
+              Software Interrupt on line
+              22
+              22
+              1
+            
+          
+        
+        
+          PR
+          PR
+          Pending register (EXTI_PR)
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PIF0
+              Pending bit 0
+              0
+              1
+            
+            
+              PIF1
+              Pending bit 1
+              1
+              1
+            
+            
+              PIF2
+              Pending bit 2
+              2
+              1
+            
+            
+              PIF3
+              Pending bit 3
+              3
+              1
+            
+            
+              PIF4
+              Pending bit 4
+              4
+              1
+            
+            
+              PIF5
+              Pending bit 5
+              5
+              1
+            
+            
+              PIF6
+              Pending bit 6
+              6
+              1
+            
+            
+              PIF7
+              Pending bit 7
+              7
+              1
+            
+            
+              PIF8
+              Pending bit 8
+              8
+              1
+            
+            
+              PIF9
+              Pending bit 9
+              9
+              1
+            
+            
+              PIF10
+              Pending bit 10
+              10
+              1
+            
+            
+              PIF11
+              Pending bit 11
+              11
+              1
+            
+            
+              PIF12
+              Pending bit 12
+              12
+              1
+            
+            
+              PIF13
+              Pending bit 13
+              13
+              1
+            
+            
+              PIF14
+              Pending bit 14
+              14
+              1
+            
+            
+              PIF15
+              Pending bit 15
+              15
+              1
+            
+            
+              PIF16
+              Pending bit 16
+              16
+              1
+            
+            
+              PIF17
+              Pending bit 17
+              17
+              1
+            
+            
+              PIF19
+              Pending bit 19
+              19
+              1
+            
+            
+              PIF20
+              Pending bit 20
+              20
+              1
+            
+            
+              PIF21
+              Pending bit 21
+              21
+              1
+            
+            
+              PIF22
+              Pending bit 22
+              22
+              1
+            
+          
+        
+      
+    
+    
+      ADC
+      Analog-to-digital converter
+      ADC
+      0x40012400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        EXTI2_3
+        EXTI Line[3:2] interrupts
+        6
+      
+      
+        
+          ISR
+          ISR
+          interrupt and status register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADRDY
+              ADC ready
+              0
+              1
+            
+            
+              EOSMP
+              End of sampling flag
+              1
+              1
+            
+            
+              EOC
+              End of conversion flag
+              2
+              1
+            
+            
+              EOS
+              End of sequence flag
+              3
+              1
+            
+            
+              OVR
+              ADC overrun
+              4
+              1
+            
+            
+              AWD
+              Analog watchdog flag
+              7
+              1
+            
+            
+              EOCAL
+              End Of Calibration flag
+              11
+              1
+            
+          
+        
+        
+          IER
+          IER
+          interrupt enable register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADRDYIE
+              ADC ready interrupt enable
+              0
+              1
+            
+            
+              EOSMPIE
+              End of sampling flag interrupt
+              enable
+              1
+              1
+            
+            
+              EOCIE
+              End of conversion interrupt
+              enable
+              2
+              1
+            
+            
+              EOSIE
+              End of conversion sequence interrupt
+              enable
+              3
+              1
+            
+            
+              OVRIE
+              Overrun interrupt enable
+              4
+              1
+            
+            
+              AWDIE
+              Analog watchdog interrupt
+              enable
+              7
+              1
+            
+            
+              EOCALIE
+              End of calibration interrupt
+              enable
+              11
+              1
+            
+          
+        
+        
+          CR
+          CR
+          control register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ADEN
+              ADC enable command
+              0
+              1
+            
+            
+              ADDIS
+              ADC disable command
+              1
+              1
+            
+            
+              ADSTART
+              ADC start conversion
+              command
+              2
+              1
+            
+            
+              ADSTP
+              ADC stop conversion
+              command
+              4
+              1
+            
+            
+              ADVREGEN
+              ADC Voltage Regulator
+              Enable
+              28
+              1
+            
+            
+              ADCAL
+              ADC calibration
+              31
+              1
+            
+          
+        
+        
+          CFGR1
+          CFGR1
+          configuration register 1
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              AWDCH
+              Analog watchdog channel
+              selection
+              26
+              5
+            
+            
+              AWDEN
+              Analog watchdog enable
+              23
+              1
+            
+            
+              AWDSGL
+              Enable the watchdog on a single channel
+              or on all channels
+              22
+              1
+            
+            
+              DISCEN
+              Discontinuous mode
+              16
+              1
+            
+            
+              AUTOFF
+              Auto-off mode
+              15
+              1
+            
+            
+              AUTDLY
+              Auto-delayed conversion
+              mode
+              14
+              1
+            
+            
+              CONT
+              Single / continuous conversion
+              mode
+              13
+              1
+            
+            
+              OVRMOD
+              Overrun management mode
+              12
+              1
+            
+            
+              EXTEN
+              External trigger enable and polarity
+              selection
+              10
+              2
+            
+            
+              EXTSEL
+              External trigger selection
+              6
+              3
+            
+            
+              ALIGN
+              Data alignment
+              5
+              1
+            
+            
+              RES
+              Data resolution
+              3
+              2
+            
+            
+              SCANDIR
+              Scan sequence direction
+              2
+              1
+            
+            
+              DMACFG
+              Direct memery access
+              configuration
+              1
+              1
+            
+            
+              DMAEN
+              Direct memory access
+              enable
+              0
+              1
+            
+          
+        
+        
+          CFGR2
+          CFGR2
+          configuration register 2
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OVSE
+              Oversampler Enable
+              0
+              1
+            
+            
+              OVSR
+              Oversampling ratio
+              2
+              3
+            
+            
+              OVSS
+              Oversampling shift
+              5
+              4
+            
+            
+              TOVS
+              Triggered Oversampling
+              9
+              1
+            
+            
+              CKMODE
+              ADC clock mode
+              30
+              2
+            
+          
+        
+        
+          SMPR
+          SMPR
+          sampling time register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SMPR
+              Sampling time selection
+              0
+              3
+            
+          
+        
+        
+          TR
+          TR
+          watchdog threshold register
+          0x20
+          0x20
+          read-write
+          0x0FFF0000
+          
+            
+              HT
+              Analog watchdog higher
+              threshold
+              16
+              12
+            
+            
+              LT
+              Analog watchdog lower
+              threshold
+              0
+              12
+            
+          
+        
+        
+          CHSELR
+          CHSELR
+          channel selection register
+          0x28
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CHSEL18
+              Channel-x selection
+              18
+              1
+            
+            
+              CHSEL17
+              Channel-x selection
+              17
+              1
+            
+            
+              CHSEL16
+              Channel-x selection
+              16
+              1
+            
+            
+              CHSEL15
+              Channel-x selection
+              15
+              1
+            
+            
+              CHSEL14
+              Channel-x selection
+              14
+              1
+            
+            
+              CHSEL13
+              Channel-x selection
+              13
+              1
+            
+            
+              CHSEL12
+              Channel-x selection
+              12
+              1
+            
+            
+              CHSEL11
+              Channel-x selection
+              11
+              1
+            
+            
+              CHSEL10
+              Channel-x selection
+              10
+              1
+            
+            
+              CHSEL9
+              Channel-x selection
+              9
+              1
+            
+            
+              CHSEL8
+              Channel-x selection
+              8
+              1
+            
+            
+              CHSEL7
+              Channel-x selection
+              7
+              1
+            
+            
+              CHSEL6
+              Channel-x selection
+              6
+              1
+            
+            
+              CHSEL5
+              Channel-x selection
+              5
+              1
+            
+            
+              CHSEL4
+              Channel-x selection
+              4
+              1
+            
+            
+              CHSEL3
+              Channel-x selection
+              3
+              1
+            
+            
+              CHSEL2
+              Channel-x selection
+              2
+              1
+            
+            
+              CHSEL1
+              Channel-x selection
+              1
+              1
+            
+            
+              CHSEL0
+              Channel-x selection
+              0
+              1
+            
+          
+        
+        
+          DR
+          DR
+          data register
+          0x40
+          0x20
+          read-only
+          0x00000000
+          
+            
+              DATA
+              Converted data
+              0
+              16
+            
+          
+        
+        
+          CALFACT
+          CALFACT
+          ADC Calibration factor
+          0xB4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CALFACT
+              Calibration factor
+              0
+              7
+            
+          
+        
+        
+          CCR
+          CCR
+          ADC common configuration
+          register
+          0x308
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRESC
+              ADC prescaler
+              18
+              4
+            
+            
+              VREFEN
+              VREFINT enable
+              22
+              1
+            
+            
+              TSEN
+              Temperature sensor enable
+              23
+              1
+            
+            
+              LFMEN
+              Low Frequency Mode enable
+              25
+              1
+            
+          
+        
+      
+    
+    
+      DBGMCU
+      Debug support
+      DBGMCU
+      0x40015800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        ADC_COMP
+        ADC and comparator 1 and 2
+        12
+      
+      
+        
+          IDCODE
+          IDCODE
+          MCU Device ID Code Register
+          0x0
+          0x20
+          read-only
+          0x0
+          
+            
+              DEV_ID
+              Device Identifier
+              0
+              12
+            
+            
+              REV_ID
+              Revision Identifier
+              16
+              16
+            
+          
+        
+        
+          CR
+          CR
+          Debug MCU Configuration
+          Register
+          0x4
+          0x20
+          read-write
+          0x0
+          
+            
+              DBG_STOP
+              Debug Stop Mode
+              1
+              1
+            
+            
+              DBG_STANDBY
+              Debug Standby Mode
+              2
+              1
+            
+            
+              DBG_SLEEP
+              Debug Sleep Mode
+              0
+              1
+            
+          
+        
+        
+          APB1_FZ
+          APB1_FZ
+          APB Low Freeze Register
+          0x8
+          0x20
+          read-write
+          0x0
+          
+            
+              DBG_TIMER2_STOP
+              Debug Timer 2 stopped when Core is
+              halted
+              0
+              1
+            
+            
+              DBG_TIMER6_STOP
+              Debug Timer 6 stopped when Core is
+              halted
+              4
+              1
+            
+            
+              DBG_RTC_STOP
+              Debug RTC stopped when Core is
+              halted
+              10
+              1
+            
+            
+              DBG_WWDG_STOP
+              Debug Window Wachdog stopped when Core
+              is halted
+              11
+              1
+            
+            
+              DBG_IWDG_STOP
+              Debug Independent Wachdog stopped when
+              Core is halted
+              12
+              1
+            
+            
+              DBG_I2C1_STOP
+              I2C1 SMBUS timeout mode stopped when
+              core is halted
+              21
+              1
+            
+            
+              DBG_I2C2_STOP
+              I2C2 SMBUS timeout mode stopped when
+              core is halted
+              22
+              1
+            
+            
+              DBG_LPTIMER_STOP
+              LPTIM1 counter stopped when core is
+              halted
+              31
+              1
+            
+          
+        
+        
+          APB2_FZ
+          APB2_FZ
+          APB High Freeze Register
+          0xC
+          0x20
+          read-write
+          0x0
+          
+            
+              DBG_TIMER21_STOP
+              Debug Timer 21 stopped when Core is
+              halted
+              2
+              1
+            
+            
+              DBG_TIMER22_STO
+              Debug Timer 22 stopped when Core is
+              halted
+              6
+              1
+            
+          
+        
+      
+    
+    
+      TIM2
+      General-purpose-timers
+      TIM
+      0x40000000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              CKD
+              Clock division
+              8
+              2
+            
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              CMS
+              Center-aligned mode
+              selection
+              5
+              2
+            
+            
+              DIR
+              Direction
+              4
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              TI1S
+              TI1 selection
+              7
+              1
+            
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+            
+              CCDS
+              Capture/compare DMA
+              selection
+              3
+              1
+            
+          
+        
+        
+          SMCR
+          SMCR
+          slave mode control register
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              ETP
+              External trigger polarity
+              15
+              1
+            
+            
+              ECE
+              External clock enable
+              14
+              1
+            
+            
+              ETPS
+              External trigger prescaler
+              12
+              2
+            
+            
+              ETF
+              External trigger filter
+              8
+              4
+            
+            
+              MSM
+              Master/Slave mode
+              7
+              1
+            
+            
+              TS
+              Trigger selection
+              4
+              3
+            
+            
+              SMS
+              Slave mode selection
+              0
+              3
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              TDE
+              Trigger DMA request enable
+              14
+              1
+            
+            
+              CC4DE
+              Capture/Compare 4 DMA request
+              enable
+              12
+              1
+            
+            
+              CC3DE
+              Capture/Compare 3 DMA request
+              enable
+              11
+              1
+            
+            
+              CC2DE
+              Capture/Compare 2 DMA request
+              enable
+              10
+              1
+            
+            
+              CC1DE
+              Capture/Compare 1 DMA request
+              enable
+              9
+              1
+            
+            
+              UDE
+              Update DMA request enable
+              8
+              1
+            
+            
+              TIE
+              Trigger interrupt enable
+              6
+              1
+            
+            
+              CC4IE
+              Capture/Compare 4 interrupt
+              enable
+              4
+              1
+            
+            
+              CC3IE
+              Capture/Compare 3 interrupt
+              enable
+              3
+              1
+            
+            
+              CC2IE
+              Capture/Compare 2 interrupt
+              enable
+              2
+              1
+            
+            
+              CC1IE
+              Capture/Compare 1 interrupt
+              enable
+              1
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC4OF
+              Capture/Compare 4 overcapture
+              flag
+              12
+              1
+            
+            
+              CC3OF
+              Capture/Compare 3 overcapture
+              flag
+              11
+              1
+            
+            
+              CC2OF
+              Capture/compare 2 overcapture
+              flag
+              10
+              1
+            
+            
+              CC1OF
+              Capture/Compare 1 overcapture
+              flag
+              9
+              1
+            
+            
+              TIF
+              Trigger interrupt flag
+              6
+              1
+            
+            
+              CC4IF
+              Capture/Compare 4 interrupt
+              flag
+              4
+              1
+            
+            
+              CC3IF
+              Capture/Compare 3 interrupt
+              flag
+              3
+              1
+            
+            
+              CC2IF
+              Capture/Compare 2 interrupt
+              flag
+              2
+              1
+            
+            
+              CC1IF
+              Capture/compare 1 interrupt
+              flag
+              1
+              1
+            
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              TG
+              Trigger generation
+              6
+              1
+            
+            
+              CC4G
+              Capture/compare 4
+              generation
+              4
+              1
+            
+            
+              CC3G
+              Capture/compare 3
+              generation
+              3
+              1
+            
+            
+              CC2G
+              Capture/compare 2
+              generation
+              2
+              1
+            
+            
+              CC1G
+              Capture/compare 1
+              generation
+              1
+              1
+            
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CCMR1_Output
+          CCMR1_Output
+          capture/compare mode register 1 (output
+          mode)
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC2CE
+              Output compare 2 clear
+              enable
+              15
+              1
+            
+            
+              OC2M
+              Output compare 2 mode
+              12
+              3
+            
+            
+              OC2PE
+              Output compare 2 preload
+              enable
+              11
+              1
+            
+            
+              OC2FE
+              Output compare 2 fast
+              enable
+              10
+              1
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              OC1CE
+              Output compare 1 clear
+              enable
+              7
+              1
+            
+            
+              OC1M
+              Output compare 1 mode
+              4
+              3
+            
+            
+              OC1PE
+              Output compare 1 preload
+              enable
+              3
+              1
+            
+            
+              OC1FE
+              Output compare 1 fast
+              enable
+              2
+              1
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR1_Input
+          CCMR1_Input
+          capture/compare mode register 1 (input
+          mode)
+          CCMR1_Output
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC2F
+              Input capture 2 filter
+              12
+              4
+            
+            
+              IC2PSC
+              Input capture 2 prescaler
+              10
+              2
+            
+            
+              CC2S
+              Capture/compare 2
+              selection
+              8
+              2
+            
+            
+              IC1F
+              Input capture 1 filter
+              4
+              4
+            
+            
+              IC1PSC
+              Input capture 1 prescaler
+              2
+              2
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR2_Output
+          CCMR2_Output
+          capture/compare mode register 2 (output
+          mode)
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC4CE
+              Output compare 4 clear
+              enable
+              15
+              1
+            
+            
+              OC4M
+              Output compare 4 mode
+              12
+              3
+            
+            
+              OC4PE
+              Output compare 4 preload
+              enable
+              11
+              1
+            
+            
+              OC4FE
+              Output compare 4 fast
+              enable
+              10
+              1
+            
+            
+              CC4S
+              Capture/Compare 4
+              selection
+              8
+              2
+            
+            
+              OC3CE
+              Output compare 3 clear
+              enable
+              7
+              1
+            
+            
+              OC3M
+              Output compare 3 mode
+              4
+              3
+            
+            
+              OC3PE
+              Output compare 3 preload
+              enable
+              3
+              1
+            
+            
+              OC3FE
+              Output compare 3 fast
+              enable
+              2
+              1
+            
+            
+              CC3S
+              Capture/Compare 3
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR2_Input
+          CCMR2_Input
+          capture/compare mode register 2 (input
+          mode)
+          CCMR2_Output
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC4F
+              Input capture 4 filter
+              12
+              4
+            
+            
+              IC4PSC
+              Input capture 4 prescaler
+              10
+              2
+            
+            
+              CC4S
+              Capture/Compare 4
+              selection
+              8
+              2
+            
+            
+              IC3F
+              Input capture 3 filter
+              4
+              4
+            
+            
+              IC3PSC
+              Input capture 3 prescaler
+              2
+              2
+            
+            
+              CC3S
+              Capture/Compare 3
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCER
+          CCER
+          capture/compare enable
+          register
+          0x20
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC4NP
+              Capture/Compare 4 output
+              Polarity
+              15
+              1
+            
+            
+              CC4P
+              Capture/Compare 3 output
+              Polarity
+              13
+              1
+            
+            
+              CC4E
+              Capture/Compare 4 output
+              enable
+              12
+              1
+            
+            
+              CC3NP
+              Capture/Compare 3 output
+              Polarity
+              11
+              1
+            
+            
+              CC3P
+              Capture/Compare 3 output
+              Polarity
+              9
+              1
+            
+            
+              CC3E
+              Capture/Compare 3 output
+              enable
+              8
+              1
+            
+            
+              CC2NP
+              Capture/Compare 2 output
+              Polarity
+              7
+              1
+            
+            
+              CC2P
+              Capture/Compare 2 output
+              Polarity
+              5
+              1
+            
+            
+              CC2E
+              Capture/Compare 2 output
+              enable
+              4
+              1
+            
+            
+              CC1NP
+              Capture/Compare 1 output
+              Polarity
+              3
+              1
+            
+            
+              CC1P
+              Capture/Compare 1 output
+              Polarity
+              1
+              1
+            
+            
+              CC1E
+              Capture/Compare 1 output
+              enable
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT_H
+              High counter value (TIM2
+              only)
+              16
+              16
+            
+            
+              CNT_L
+              Low counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR_H
+              High Auto-reload value (TIM2
+              only)
+              16
+              16
+            
+            
+              ARR_L
+              Low Auto-reload value
+              0
+              16
+            
+          
+        
+        
+          CCR1
+          CCR1
+          capture/compare register 1
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR1_H
+              High Capture/Compare 1 value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR1_L
+              Low Capture/Compare 1
+              value
+              0
+              16
+            
+          
+        
+        
+          CCR2
+          CCR2
+          capture/compare register 2
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR2_H
+              High Capture/Compare 2 value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR2_L
+              Low Capture/Compare 2
+              value
+              0
+              16
+            
+          
+        
+        
+          CCR3
+          CCR3
+          capture/compare register 3
+          0x3C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR3_H
+              High Capture/Compare value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR3_L
+              Low Capture/Compare value
+              0
+              16
+            
+          
+        
+        
+          CCR4
+          CCR4
+          capture/compare register 4
+          0x40
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR4_H
+              High Capture/Compare value (TIM2
+              only)
+              16
+              16
+            
+            
+              CCR4_L
+              Low Capture/Compare value
+              0
+              16
+            
+          
+        
+        
+          DCR
+          DCR
+          DMA control register
+          0x48
+          0x20
+          read-write
+          0x0000
+          
+            
+              DBL
+              DMA burst length
+              8
+              5
+            
+            
+              DBA
+              DMA base address
+              0
+              5
+            
+          
+        
+        
+          DMAR
+          DMAR
+          DMA address for full transfer
+          0x4C
+          0x20
+          read-write
+          0x0000
+          
+            
+              DMAB
+              DMA register for burst
+              accesses
+              0
+              16
+            
+          
+        
+        
+          OR
+          OR
+          TIM2 option register
+          0x50
+          0x20
+          read-write
+          0x0000
+          
+            
+              ETR_RMP
+              Timer2 ETR remap
+              0
+              3
+            
+            
+              TI4_RMP
+              Internal trigger
+              3
+              2
+            
+          
+        
+      
+    
+    
+      TIM3
+      0x40000400
+      
+        TIM2
+        TIM2 global interrupt
+        15
+      
+    
+    
+      TIM6
+      Basic-timers
+      TIM
+      0x40001000
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM3
+        TIM3 global interrupt
+        16
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              UDE
+              Update DMA request enable
+              8
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT
+              Low counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR
+              Low Auto-reload value
+              0
+              16
+            
+          
+        
+      
+    
+    
+      TIM7
+      0x40001400
+      
+        TIM6_DAC
+        TIM6 global interrupt and DAC
+        17
+      
+    
+    
+      TIM21
+      General-purpose-timers
+      TIM
+      0x40010800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM7
+        TIM7 global interrupt and DAC
+        18
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              DIR
+              Direction
+              4
+              1
+            
+            
+              CMS
+              Center-aligned mode
+              selection
+              5
+              2
+            
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              CKD
+              Clock division
+              8
+              2
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+          
+        
+        
+          SMCR
+          SMCR
+          slave mode control register
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              SMS
+              Slave mode selection
+              0
+              3
+            
+            
+              TS
+              Trigger selection
+              4
+              3
+            
+            
+              MSM
+              Master/Slave mode
+              7
+              1
+            
+            
+              ETF
+              External trigger filter
+              8
+              4
+            
+            
+              ETPS
+              External trigger prescaler
+              12
+              2
+            
+            
+              ECE
+              External clock enable
+              14
+              1
+            
+            
+              ETP
+              External trigger polarity
+              15
+              1
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              TIE
+              Trigger interrupt enable
+              6
+              1
+            
+            
+              CC2IE
+              Capture/Compare 2 interrupt
+              enable
+              2
+              1
+            
+            
+              CC1IE
+              Capture/Compare 1 interrupt
+              enable
+              1
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2OF
+              Capture/compare 2 overcapture
+              flag
+              10
+              1
+            
+            
+              CC1OF
+              Capture/Compare 1 overcapture
+              flag
+              9
+              1
+            
+            
+              TIF
+              Trigger interrupt flag
+              6
+              1
+            
+            
+              CC2IF
+              Capture/Compare 2 interrupt
+              flag
+              2
+              1
+            
+            
+              CC1IF
+              Capture/compare 1 interrupt
+              flag
+              1
+              1
+            
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              TG
+              Trigger generation
+              6
+              1
+            
+            
+              CC2G
+              Capture/compare 2
+              generation
+              2
+              1
+            
+            
+              CC1G
+              Capture/compare 1
+              generation
+              1
+              1
+            
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CCMR1_Output
+          CCMR1_Output
+          capture/compare mode register (output
+          mode)
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC2M
+              Output Compare 2 mode
+              12
+              3
+            
+            
+              OC2PE
+              Output Compare 2 preload
+              enable
+              11
+              1
+            
+            
+              OC2FE
+              Output Compare 2 fast
+              enable
+              10
+              1
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              OC1M
+              Output Compare 1 mode
+              4
+              3
+            
+            
+              OC1PE
+              Output Compare 1 preload
+              enable
+              3
+              1
+            
+            
+              OC1FE
+              Output Compare 1 fast
+              enable
+              2
+              1
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR1_Input
+          CCMR1_Input
+          capture/compare mode register 1 (input
+          mode)
+          CCMR1_Output
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC2F
+              Input capture 2 filter
+              12
+              4
+            
+            
+              IC2PSC
+              Input capture 2 prescaler
+              10
+              2
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              IC1F
+              Input capture 1 filter
+              4
+              4
+            
+            
+              IC1PSC
+              Input capture 1 prescaler
+              2
+              2
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCER
+          CCER
+          capture/compare enable
+          register
+          0x20
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2NP
+              Capture/Compare 2 output
+              Polarity
+              7
+              1
+            
+            
+              CC2P
+              Capture/Compare 2 output
+              Polarity
+              5
+              1
+            
+            
+              CC2E
+              Capture/Compare 2 output
+              enable
+              4
+              1
+            
+            
+              CC1NP
+              Capture/Compare 1 output
+              Polarity
+              3
+              1
+            
+            
+              CC1P
+              Capture/Compare 1 output
+              Polarity
+              1
+              1
+            
+            
+              CC1E
+              Capture/Compare 1 output
+              enable
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT
+              counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR
+              Auto-reload value
+              0
+              16
+            
+          
+        
+        
+          CCR1
+          CCR1
+          capture/compare register 1
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR1
+              Capture/Compare 1 value
+              0
+              16
+            
+          
+        
+        
+          CCR2
+          CCR2
+          capture/compare register 2
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR2
+              Capture/Compare 2 value
+              0
+              16
+            
+          
+        
+        
+          OR
+          OR
+          TIM21 option register
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ETR_RMP
+              Timer21 ETR remap
+              0
+              2
+            
+            
+              TI1_RMP
+              Timer21 TI1
+              2
+              3
+            
+            
+              TI2_RMP
+              Timer21 TI2
+              5
+              1
+            
+          
+        
+      
+    
+    
+      TIM22
+      General-purpose-timers
+      TIM
+      0x40011400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM21
+        TIMER21 global interrupt
+        20
+      
+      
+        
+          CR1
+          CR1
+          control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              CEN
+              Counter enable
+              0
+              1
+            
+            
+              UDIS
+              Update disable
+              1
+              1
+            
+            
+              URS
+              Update request source
+              2
+              1
+            
+            
+              OPM
+              One-pulse mode
+              3
+              1
+            
+            
+              DIR
+              Direction
+              4
+              1
+            
+            
+              CMS
+              Center-aligned mode
+              selection
+              5
+              2
+            
+            
+              ARPE
+              Auto-reload preload enable
+              7
+              1
+            
+            
+              CKD
+              Clock division
+              8
+              2
+            
+          
+        
+        
+          CR2
+          CR2
+          control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              MMS
+              Master mode selection
+              4
+              3
+            
+          
+        
+        
+          SMCR
+          SMCR
+          slave mode control register
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              SMS
+              Slave mode selection
+              0
+              3
+            
+            
+              TS
+              Trigger selection
+              4
+              3
+            
+            
+              MSM
+              Master/Slave mode
+              7
+              1
+            
+            
+              ETF
+              External trigger filter
+              8
+              4
+            
+            
+              ETPS
+              External trigger prescaler
+              12
+              2
+            
+            
+              ECE
+              External clock enable
+              14
+              1
+            
+            
+              ETP
+              External trigger polarity
+              15
+              1
+            
+          
+        
+        
+          DIER
+          DIER
+          DMA/Interrupt enable register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              TIE
+              Trigger interrupt enable
+              6
+              1
+            
+            
+              CC2IE
+              Capture/Compare 2 interrupt
+              enable
+              2
+              1
+            
+            
+              CC1IE
+              Capture/Compare 1 interrupt
+              enable
+              1
+              1
+            
+            
+              UIE
+              Update interrupt enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x10
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2OF
+              Capture/compare 2 overcapture
+              flag
+              10
+              1
+            
+            
+              CC1OF
+              Capture/Compare 1 overcapture
+              flag
+              9
+              1
+            
+            
+              TIF
+              Trigger interrupt flag
+              6
+              1
+            
+            
+              CC2IF
+              Capture/Compare 2 interrupt
+              flag
+              2
+              1
+            
+            
+              CC1IF
+              Capture/compare 1 interrupt
+              flag
+              1
+              1
+            
+            
+              UIF
+              Update interrupt flag
+              0
+              1
+            
+          
+        
+        
+          EGR
+          EGR
+          event generation register
+          0x14
+          0x20
+          write-only
+          0x0000
+          
+            
+              TG
+              Trigger generation
+              6
+              1
+            
+            
+              CC2G
+              Capture/compare 2
+              generation
+              2
+              1
+            
+            
+              CC1G
+              Capture/compare 1
+              generation
+              1
+              1
+            
+            
+              UG
+              Update generation
+              0
+              1
+            
+          
+        
+        
+          CCMR1_Output
+          CCMR1_Output
+          capture/compare mode register (output
+          mode)
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              OC2M
+              Output Compare 2 mode
+              12
+              3
+            
+            
+              OC2PE
+              Output Compare 2 preload
+              enable
+              11
+              1
+            
+            
+              OC2FE
+              Output Compare 2 fast
+              enable
+              10
+              1
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              OC1M
+              Output Compare 1 mode
+              4
+              3
+            
+            
+              OC1PE
+              Output Compare 1 preload
+              enable
+              3
+              1
+            
+            
+              OC1FE
+              Output Compare 1 fast
+              enable
+              2
+              1
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCMR1_Input
+          CCMR1_Input
+          capture/compare mode register 1 (input
+          mode)
+          CCMR1_Output
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              IC2F
+              Input capture 2 filter
+              12
+              4
+            
+            
+              IC2PSC
+              Input capture 2 prescaler
+              10
+              2
+            
+            
+              CC2S
+              Capture/Compare 2
+              selection
+              8
+              2
+            
+            
+              IC1F
+              Input capture 1 filter
+              4
+              4
+            
+            
+              IC1PSC
+              Input capture 1 prescaler
+              2
+              2
+            
+            
+              CC1S
+              Capture/Compare 1
+              selection
+              0
+              2
+            
+          
+        
+        
+          CCER
+          CCER
+          capture/compare enable
+          register
+          0x20
+          0x20
+          read-write
+          0x0000
+          
+            
+              CC2NP
+              Capture/Compare 2 output
+              Polarity
+              7
+              1
+            
+            
+              CC2P
+              Capture/Compare 2 output
+              Polarity
+              5
+              1
+            
+            
+              CC2E
+              Capture/Compare 2 output
+              enable
+              4
+              1
+            
+            
+              CC1NP
+              Capture/Compare 1 output
+              Polarity
+              3
+              1
+            
+            
+              CC1P
+              Capture/Compare 1 output
+              Polarity
+              1
+              1
+            
+            
+              CC1E
+              Capture/Compare 1 output
+              enable
+              0
+              1
+            
+          
+        
+        
+          CNT
+          CNT
+          counter
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CNT
+              counter value
+              0
+              16
+            
+          
+        
+        
+          PSC
+          PSC
+          prescaler
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              PSC
+              Prescaler value
+              0
+              16
+            
+          
+        
+        
+          ARR
+          ARR
+          auto-reload register
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ARR
+              Auto-reload value
+              0
+              16
+            
+          
+        
+        
+          CCR1
+          CCR1
+          capture/compare register 1
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR1
+              Capture/Compare 1 value
+              0
+              16
+            
+          
+        
+        
+          CCR2
+          CCR2
+          capture/compare register 2
+          0x38
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CCR2
+              Capture/Compare 2 value
+              0
+              16
+            
+          
+        
+        
+          OR
+          OR
+          TIM22 option register
+          0x50
+          0x20
+          read-write
+          0x00000000
+          
+            
+              ETR_RMP
+              Timer22 ETR remap
+              0
+              2
+            
+            
+              TI1_RMP
+              Timer22 TI1
+              2
+              2
+            
+          
+        
+      
+    
+    
+      LPUSART1
+      Universal synchronous asynchronous receiver
+      transmitter
+      USART
+      0x40004800
+      
+        0x0
+        0x400
+        registers
+      
+      
+        TIM22
+        TIMER22 global interrupt
+        22
+      
+      
+        
+          CR1
+          CR1
+          Control register 1
+          0x0
+          0x20
+          read-write
+          0x0000
+          
+            
+              M1
+              Word length
+              28
+              1
+            
+            
+              DEAT4
+              Driver Enable assertion
+              time
+              25
+              1
+            
+            
+              DEAT3
+              DEAT3
+              24
+              1
+            
+            
+              DEAT2
+              DEAT2
+              23
+              1
+            
+            
+              DEAT1
+              DEAT1
+              22
+              1
+            
+            
+              DEAT0
+              DEAT0
+              21
+              1
+            
+            
+              DEDT4
+              Driver Enable de-assertion
+              time
+              20
+              1
+            
+            
+              DEDT3
+              DEDT3
+              19
+              1
+            
+            
+              DEDT2
+              DEDT2
+              18
+              1
+            
+            
+              DEDT1
+              DEDT1
+              17
+              1
+            
+            
+              DEDT0
+              DEDT0
+              16
+              1
+            
+            
+              CMIE
+              Character match interrupt
+              enable
+              14
+              1
+            
+            
+              MME
+              Mute mode enable
+              13
+              1
+            
+            
+              M0
+              Word length
+              12
+              1
+            
+            
+              WAKE
+              Receiver wakeup method
+              11
+              1
+            
+            
+              PCE
+              Parity control enable
+              10
+              1
+            
+            
+              PS
+              Parity selection
+              9
+              1
+            
+            
+              PEIE
+              PE interrupt enable
+              8
+              1
+            
+            
+              TXEIE
+              interrupt enable
+              7
+              1
+            
+            
+              TCIE
+              Transmission complete interrupt
+              enable
+              6
+              1
+            
+            
+              RXNEIE
+              RXNE interrupt enable
+              5
+              1
+            
+            
+              IDLEIE
+              IDLE interrupt enable
+              4
+              1
+            
+            
+              TE
+              Transmitter enable
+              3
+              1
+            
+            
+              RE
+              Receiver enable
+              2
+              1
+            
+            
+              UESM
+              USART enable in Stop mode
+              1
+              1
+            
+            
+              UE
+              USART enable
+              0
+              1
+            
+          
+        
+        
+          CR2
+          CR2
+          Control register 2
+          0x4
+          0x20
+          read-write
+          0x0000
+          
+            
+              ADD4_7
+              Address of the USART node
+              28
+              4
+            
+            
+              ADD0_3
+              Address of the USART node
+              24
+              4
+            
+            
+              MSBFIRST
+              Most significant bit first
+              19
+              1
+            
+            
+              TAINV
+              Binary data inversion
+              18
+              1
+            
+            
+              TXINV
+              TX pin active level
+              inversion
+              17
+              1
+            
+            
+              RXINV
+              RX pin active level
+              inversion
+              16
+              1
+            
+            
+              SWAP
+              Swap TX/RX pins
+              15
+              1
+            
+            
+              STOP
+              STOP bits
+              12
+              2
+            
+            
+              CLKEN
+              Clock enable
+              11
+              1
+            
+            
+              ADDM7
+              7-bit Address Detection/4-bit Address
+              Detection
+              4
+              1
+            
+          
+        
+        
+          CR3
+          CR3
+          Control register 3
+          0x8
+          0x20
+          read-write
+          0x0000
+          
+            
+              WUFIE
+              Wakeup from Stop mode interrupt
+              enable
+              22
+              1
+            
+            
+              WUS
+              Wakeup from Stop mode interrupt flag
+              selection
+              20
+              2
+            
+            
+              DEP
+              Driver enable polarity
+              selection
+              15
+              1
+            
+            
+              DEM
+              Driver enable mode
+              14
+              1
+            
+            
+              DDRE
+              DMA Disable on Reception
+              Error
+              13
+              1
+            
+            
+              OVRDIS
+              Overrun Disable
+              12
+              1
+            
+            
+              CTSIE
+              CTS interrupt enable
+              10
+              1
+            
+            
+              CTSE
+              CTS enable
+              9
+              1
+            
+            
+              RTSE
+              RTS enable
+              8
+              1
+            
+            
+              DMAT
+              DMA enable transmitter
+              7
+              1
+            
+            
+              DMAR
+              DMA enable receiver
+              6
+              1
+            
+            
+              HDSEL
+              Half-duplex selection
+              3
+              1
+            
+            
+              EIE
+              Error interrupt enable
+              0
+              1
+            
+          
+        
+        
+          BRR
+          BRR
+          Baud rate register
+          0xC
+          0x20
+          read-write
+          0x0000
+          
+            
+              BRR
+              BRR
+              0
+              20
+            
+          
+        
+        
+          RQR
+          RQR
+          Request register
+          0x18
+          0x20
+          write-only
+          0x0000
+          
+            
+              RXFRQ
+              Receive data flush request
+              3
+              1
+            
+            
+              MMRQ
+              Mute mode request
+              2
+              1
+            
+            
+              SBKRQ
+              Send break request
+              1
+              1
+            
+          
+        
+        
+          ISR
+          ISR
+          Interrupt & status
+          register
+          0x1C
+          0x20
+          read-only
+          0x00C0
+          
+            
+              REACK
+              REACK
+              22
+              1
+            
+            
+              TEACK
+              TEACK
+              21
+              1
+            
+            
+              WUF
+              WUF
+              20
+              1
+            
+            
+              RWU
+              RWU
+              19
+              1
+            
+            
+              SBKF
+              SBKF
+              18
+              1
+            
+            
+              CMF
+              CMF
+              17
+              1
+            
+            
+              BUSY
+              BUSY
+              16
+              1
+            
+            
+              CTS
+              CTS
+              10
+              1
+            
+            
+              CTSIF
+              CTSIF
+              9
+              1
+            
+            
+              TXE
+              TXE
+              7
+              1
+            
+            
+              TC
+              TC
+              6
+              1
+            
+            
+              RXNE
+              RXNE
+              5
+              1
+            
+            
+              IDLE
+              IDLE
+              4
+              1
+            
+            
+              ORE
+              ORE
+              3
+              1
+            
+            
+              NF
+              NF
+              2
+              1
+            
+            
+              FE
+              FE
+              1
+              1
+            
+            
+              PE
+              PE
+              0
+              1
+            
+          
+        
+        
+          ICR
+          ICR
+          Interrupt flag clear register
+          0x20
+          0x20
+          write-only
+          0x0000
+          
+            
+              WUCF
+              Wakeup from Stop mode clear
+              flag
+              20
+              1
+            
+            
+              CMCF
+              Character match clear flag
+              17
+              1
+            
+            
+              CTSCF
+              CTS clear flag
+              9
+              1
+            
+            
+              TCCF
+              Transmission complete clear
+              flag
+              6
+              1
+            
+            
+              IDLECF
+              Idle line detected clear
+              flag
+              4
+              1
+            
+            
+              ORECF
+              Overrun error clear flag
+              3
+              1
+            
+            
+              NCF
+              Noise detected clear flag
+              2
+              1
+            
+            
+              FECF
+              Framing error clear flag
+              1
+              1
+            
+            
+              PECF
+              Parity error clear flag
+              0
+              1
+            
+          
+        
+        
+          RDR
+          RDR
+          Receive data register
+          0x24
+          0x20
+          read-only
+          0x0000
+          
+            
+              RDR
+              Receive data value
+              0
+              9
+            
+          
+        
+        
+          TDR
+          TDR
+          Transmit data register
+          0x28
+          0x20
+          read-write
+          0x0000
+          
+            
+              TDR
+              Transmit data value
+              0
+              9
+            
+          
+        
+      
+    
+    
+      NVIC
+      Nested Vectored Interrupt
+      Controller
+      NVIC
+      0xE000E100
+      
+        0x0
+        0x33D
+        registers
+      
+      
+        
+          ISER
+          ISER
+          Interrupt Set Enable Register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SETENA
+              SETENA
+              0
+              32
+            
+          
+        
+        
+          ICER
+          ICER
+          Interrupt Clear Enable
+          Register
+          0x80
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CLRENA
+              CLRENA
+              0
+              32
+            
+          
+        
+        
+          ISPR
+          ISPR
+          Interrupt Set-Pending Register
+          0x100
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SETPEND
+              SETPEND
+              0
+              32
+            
+          
+        
+        
+          ICPR
+          ICPR
+          Interrupt Clear-Pending
+          Register
+          0x180
+          0x20
+          read-write
+          0x00000000
+          
+            
+              CLRPEND
+              CLRPEND
+              0
+              32
+            
+          
+        
+        
+          IPR0
+          IPR0
+          Interrupt Priority Register 0
+          0x300
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_0
+              priority for interrupt 0
+              0
+              8
+            
+            
+              PRI_1
+              priority for interrupt 1
+              8
+              8
+            
+            
+              PRI_2
+              priority for interrupt 2
+              16
+              8
+            
+            
+              PRI_3
+              priority for interrupt 3
+              24
+              8
+            
+          
+        
+        
+          IPR1
+          IPR1
+          Interrupt Priority Register 1
+          0x304
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_4
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_5
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_6
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_7
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR2
+          IPR2
+          Interrupt Priority Register 2
+          0x308
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_8
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_9
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_10
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_11
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR3
+          IPR3
+          Interrupt Priority Register 3
+          0x30C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_12
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_13
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_14
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_15
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR4
+          IPR4
+          Interrupt Priority Register 4
+          0x310
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_16
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_17
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_18
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_19
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR5
+          IPR5
+          Interrupt Priority Register 5
+          0x314
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_20
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_21
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_22
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_23
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR6
+          IPR6
+          Interrupt Priority Register 6
+          0x318
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_24
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_25
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_26
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_27
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+        
+          IPR7
+          IPR7
+          Interrupt Priority Register 7
+          0x31C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_28
+              priority for interrupt n
+              0
+              8
+            
+            
+              PRI_29
+              priority for interrupt n
+              8
+              8
+            
+            
+              PRI_30
+              priority for interrupt n
+              16
+              8
+            
+            
+              PRI_31
+              priority for interrupt n
+              24
+              8
+            
+          
+        
+      
+    
+    
+      USB_SRAM
+      Universal serial bus full-speed device
+      interface
+      USB
+      0x40006000
+      
+        0x0
+        0x800
+        registers
+      
+      
+        
+          EP0R
+          EP0R
+          endpoint 0 register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP1R
+          EP1R
+          endpoint 1 register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP2R
+          EP2R
+          endpoint 2 register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP3R
+          EP3R
+          endpoint 3 register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP4R
+          EP4R
+          endpoint 4 register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP5R
+          EP5R
+          endpoint 5 register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP6R
+          EP6R
+          endpoint 6 register
+          0x18
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          EP7R
+          EP7R
+          endpoint 7 register
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              EA
+              Endpoint address
+              0
+              4
+            
+            
+              STAT_TX
+              Status bits, for transmission
+              transfers
+              4
+              2
+            
+            
+              DTOG_TX
+              Data Toggle, for transmission
+              transfers
+              6
+              1
+            
+            
+              CTR_TX
+              Correct Transfer for
+              transmission
+              7
+              1
+            
+            
+              EP_KIND
+              Endpoint kind
+              8
+              1
+            
+            
+              EP_TYPE
+              Endpoint type
+              9
+              2
+            
+            
+              SETUP
+              Setup transaction
+              completed
+              11
+              1
+            
+            
+              STAT_RX
+              Status bits, for reception
+              transfers
+              12
+              2
+            
+            
+              DTOG_RX
+              Data Toggle, for reception
+              transfers
+              14
+              1
+            
+            
+              CTR_RX
+              Correct transfer for
+              reception
+              15
+              1
+            
+          
+        
+        
+          CNTR
+          CNTR
+          control register
+          0x40
+          0x20
+          read-write
+          0x00000003
+          
+            
+              FRES
+              Force USB Reset
+              0
+              1
+            
+            
+              PDWN
+              Power down
+              1
+              1
+            
+            
+              LPMODE
+              Low-power mode
+              2
+              1
+            
+            
+              FSUSP
+              Force suspend
+              3
+              1
+            
+            
+              RESUME
+              Resume request
+              4
+              1
+            
+            
+              L1RESUME
+              LPM L1 Resume request
+              5
+              1
+            
+            
+              L1REQM
+              LPM L1 state request interrupt
+              mask
+              7
+              1
+            
+            
+              ESOFM
+              Expected start of frame interrupt
+              mask
+              8
+              1
+            
+            
+              SOFM
+              Start of frame interrupt
+              mask
+              9
+              1
+            
+            
+              RESETM
+              USB reset interrupt mask
+              10
+              1
+            
+            
+              SUSPM
+              Suspend mode interrupt
+              mask
+              11
+              1
+            
+            
+              WKUPM
+              Wakeup interrupt mask
+              12
+              1
+            
+            
+              ERRM
+              Error interrupt mask
+              13
+              1
+            
+            
+              PMAOVRM
+              Packet memory area over / underrun
+              interrupt mask
+              14
+              1
+            
+            
+              CTRM
+              Correct transfer interrupt
+              mask
+              15
+              1
+            
+          
+        
+        
+          ISTR
+          ISTR
+          interrupt status register
+          0x44
+          0x20
+          0x00000000
+          
+            
+              EP_ID
+              Endpoint Identifier
+              0
+              4
+              read-only
+            
+            
+              DIR
+              Direction of transaction
+              4
+              1
+              read-only
+            
+            
+              L1REQ
+              LPM L1 state request
+              7
+              1
+              read-write
+            
+            
+              ESOF
+              Expected start frame
+              8
+              1
+              read-write
+            
+            
+              SOF
+              start of frame
+              9
+              1
+              read-write
+            
+            
+              RESET
+              reset request
+              10
+              1
+              read-write
+            
+            
+              SUSP
+              Suspend mode request
+              11
+              1
+              read-write
+            
+            
+              WKUP
+              Wakeup
+              12
+              1
+              read-write
+            
+            
+              ERR
+              Error
+              13
+              1
+              read-write
+            
+            
+              PMAOVR
+              Packet memory area over /
+              underrun
+              14
+              1
+              read-write
+            
+            
+              CTR
+              Correct transfer
+              15
+              1
+              read-only
+            
+          
+        
+        
+          FNR
+          FNR
+          frame number register
+          0x48
+          0x20
+          read-only
+          0x0000
+          
+            
+              FN
+              Frame number
+              0
+              11
+            
+            
+              LSOF
+              Lost SOF
+              11
+              2
+            
+            
+              LCK
+              Locked
+              13
+              1
+            
+            
+              RXDM
+              Receive data - line status
+              14
+              1
+            
+            
+              RXDP
+              Receive data + line status
+              15
+              1
+            
+          
+        
+        
+          DADDR
+          DADDR
+          device address
+          0x4C
+          0x20
+          read-write
+          0x0000
+          
+            
+              ADD
+              Device address
+              0
+              7
+            
+            
+              EF
+              Enable function
+              7
+              1
+            
+          
+        
+        
+          BTABLE
+          BTABLE
+          Buffer table address
+          0x50
+          0x20
+          read-write
+          0x0000
+          
+            
+              BTABLE
+              Buffer table
+              3
+              13
+            
+          
+        
+        
+          LPMCSR
+          LPMCSR
+          LPM control and status
+          register
+          0x54
+          0x20
+          0x0000
+          
+            
+              LPMEN
+              LPM support enable
+              0
+              1
+              read-write
+            
+            
+              LPMACK
+              LPM Token acknowledge
+              enable
+              1
+              1
+              read-write
+            
+            
+              REMWAKE
+              bRemoteWake value
+              3
+              1
+              read-only
+            
+            
+              BESL
+              BESL value
+              4
+              4
+              read-only
+            
+          
+        
+        
+          BCDR
+          BCDR
+          Battery charging detector
+          0x58
+          0x20
+          0x0000
+          
+            
+              BCDEN
+              Battery charging detector
+              0
+              1
+              read-write
+            
+            
+              DCDEN
+              Data contact detection
+              1
+              1
+              read-write
+            
+            
+              PDEN
+              Primary detection
+              2
+              1
+              read-write
+            
+            
+              SDEN
+              Secondary detection
+              3
+              1
+              read-write
+            
+            
+              DCDET
+              Data contact detection
+              4
+              1
+              read-only
+            
+            
+              PDET
+              Primary detection
+              5
+              1
+              read-only
+            
+            
+              SDET
+              Secondary detection
+              6
+              1
+              read-only
+            
+            
+              PS2DET
+              DM pull-up detection
+              status
+              7
+              1
+              read-only
+            
+            
+              DPPU
+              DP pull-up control
+              15
+              1
+              read-write
+            
+          
+        
+      
+    
+    
+      LCD
+      Liquid crystal display controller
+      LCD
+      0x40002400
+      
+        0x0
+        0x400
+        registers
+      
+      
+        LCD
+        LCD global interrupt
+        30
+      
+      
+        
+          CR
+          CR
+          control register
+          0x0
+          0x20
+          read-write
+          0x00000000
+          
+            
+              BIAS
+              Bias selector
+              5
+              2
+            
+            
+              DUTY
+              Duty selection
+              2
+              3
+            
+            
+              VSEL
+              Voltage source selection
+              1
+              1
+            
+            
+              LCDEN
+              LCD controller enable
+              0
+              1
+            
+          
+        
+        
+          FCR
+          FCR
+          frame control register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PS
+              PS 16-bit prescaler
+              22
+              4
+            
+            
+              DIV
+              DIV clock divider
+              18
+              4
+            
+            
+              BLINK
+              Blink mode selection
+              16
+              2
+            
+            
+              BLINKF
+              Blink frequency selection
+              13
+              3
+            
+            
+              CC
+              Contrast control
+              10
+              3
+            
+            
+              DEAD
+              Dead time duration
+              7
+              3
+            
+            
+              PON
+              Pulse ON duration
+              4
+              3
+            
+            
+              UDDIE
+              Update display done interrupt
+              enable
+              3
+              1
+            
+            
+              SOFIE
+              Start of frame interrupt
+              enable
+              1
+              1
+            
+            
+              HD
+              High drive enable
+              0
+              1
+            
+          
+        
+        
+          SR
+          SR
+          status register
+          0x8
+          0x20
+          0x00000020
+          
+            
+              FCRSF
+              LCD Frame Control Register
+              Synchronization flag
+              5
+              1
+              read-only
+            
+            
+              RDY
+              Ready flag
+              4
+              1
+              read-only
+            
+            
+              UDD
+              Update Display Done
+              3
+              1
+              read-only
+            
+            
+              UDR
+              Update display request
+              2
+              1
+              write-only
+            
+            
+              SOF
+              Start of frame flag
+              1
+              1
+              read-only
+            
+            
+              ENS
+              ENS
+              0
+              1
+              read-only
+            
+          
+        
+        
+          CLR
+          CLR
+          clear register
+          0xC
+          0x20
+          write-only
+          0x00000000
+          
+            
+              UDDC
+              Update display done clear
+              3
+              1
+            
+            
+              SOFC
+              Start of frame flag clear
+              1
+              1
+            
+          
+        
+        
+          RAM_COM0
+          RAM_COM0
+          display memory
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              S30
+              S30
+              30
+              1
+            
+            
+              S29
+              S29
+              29
+              1
+            
+            
+              S28
+              S28
+              28
+              1
+            
+            
+              S27
+              S27
+              27
+              1
+            
+            
+              S26
+              S26
+              26
+              1
+            
+            
+              S25
+              S25
+              25
+              1
+            
+            
+              S24
+              S24
+              24
+              1
+            
+            
+              S23
+              S23
+              23
+              1
+            
+            
+              S22
+              S22
+              22
+              1
+            
+            
+              S21
+              S21
+              21
+              1
+            
+            
+              S20
+              S20
+              20
+              1
+            
+            
+              S19
+              S19
+              19
+              1
+            
+            
+              S18
+              S18
+              18
+              1
+            
+            
+              S17
+              S17
+              17
+              1
+            
+            
+              S16
+              S16
+              16
+              1
+            
+            
+              S15
+              S15
+              15
+              1
+            
+            
+              S14
+              S14
+              14
+              1
+            
+            
+              S13
+              S13
+              13
+              1
+            
+            
+              S12
+              S12
+              12
+              1
+            
+            
+              S11
+              S11
+              11
+              1
+            
+            
+              S10
+              S10
+              10
+              1
+            
+            
+              S09
+              S09
+              9
+              1
+            
+            
+              S08
+              S08
+              8
+              1
+            
+            
+              S07
+              S07
+              7
+              1
+            
+            
+              S06
+              S06
+              6
+              1
+            
+            
+              S05
+              S05
+              5
+              1
+            
+            
+              S04
+              S04
+              4
+              1
+            
+            
+              S03
+              S03
+              3
+              1
+            
+            
+              S02
+              S02
+              2
+              1
+            
+            
+              S01
+              S01
+              1
+              1
+            
+            
+              S00
+              S00
+              0
+              1
+            
+          
+        
+        
+          RAM_COM1
+          RAM_COM1
+          display memory
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              S31
+              S31
+              31
+              1
+            
+            
+              S30
+              S30
+              30
+              1
+            
+            
+              S29
+              S29
+              29
+              1
+            
+            
+              S28
+              S28
+              28
+              1
+            
+            
+              S27
+              S27
+              27
+              1
+            
+            
+              S26
+              S26
+              26
+              1
+            
+            
+              S25
+              S25
+              25
+              1
+            
+            
+              S24
+              S24
+              24
+              1
+            
+            
+              S23
+              S23
+              23
+              1
+            
+            
+              S22
+              S22
+              22
+              1
+            
+            
+              S21
+              S21
+              21
+              1
+            
+            
+              S20
+              S20
+              20
+              1
+            
+            
+              S19
+              S19
+              19
+              1
+            
+            
+              S18
+              S18
+              18
+              1
+            
+            
+              S17
+              S17
+              17
+              1
+            
+            
+              S16
+              S16
+              16
+              1
+            
+            
+              S15
+              S15
+              15
+              1
+            
+            
+              S14
+              S14
+              14
+              1
+            
+            
+              S13
+              S13
+              13
+              1
+            
+            
+              S12
+              S12
+              12
+              1
+            
+            
+              S11
+              S11
+              11
+              1
+            
+            
+              S10
+              S10
+              10
+              1
+            
+            
+              S09
+              S09
+              9
+              1
+            
+            
+              S08
+              S08
+              8
+              1
+            
+            
+              S07
+              S07
+              7
+              1
+            
+            
+              S06
+              S06
+              6
+              1
+            
+            
+              S05
+              S05
+              5
+              1
+            
+            
+              S04
+              S04
+              4
+              1
+            
+            
+              S03
+              S03
+              3
+              1
+            
+            
+              S02
+              S02
+              2
+              1
+            
+            
+              S01
+              S01
+              1
+              1
+            
+            
+              S00
+              S00
+              0
+              1
+            
+          
+        
+        
+          RAM_COM2
+          RAM_COM2
+          display memory
+          0x24
+          0x20
+          read-write
+          0x00000000
+          
+            
+              S31
+              S31
+              31
+              1
+            
+            
+              S30
+              S30
+              30
+              1
+            
+            
+              S29
+              S29
+              29
+              1
+            
+            
+              S28
+              S28
+              28
+              1
+            
+            
+              S27
+              S27
+              27
+              1
+            
+            
+              S26
+              S26
+              26
+              1
+            
+            
+              S25
+              S25
+              25
+              1
+            
+            
+              S24
+              S24
+              24
+              1
+            
+            
+              S23
+              S23
+              23
+              1
+            
+            
+              S22
+              S22
+              22
+              1
+            
+            
+              S21
+              S21
+              21
+              1
+            
+            
+              S20
+              S20
+              20
+              1
+            
+            
+              S19
+              S19
+              19
+              1
+            
+            
+              S18
+              S18
+              18
+              1
+            
+            
+              S17
+              S17
+              17
+              1
+            
+            
+              S16
+              S16
+              16
+              1
+            
+            
+              S15
+              S15
+              15
+              1
+            
+            
+              S14
+              S14
+              14
+              1
+            
+            
+              S13
+              S13
+              13
+              1
+            
+            
+              S12
+              S12
+              12
+              1
+            
+            
+              S11
+              S11
+              11
+              1
+            
+            
+              S10
+              S10
+              10
+              1
+            
+            
+              S09
+              S09
+              9
+              1
+            
+            
+              S08
+              S08
+              8
+              1
+            
+            
+              S07
+              S07
+              7
+              1
+            
+            
+              S06
+              S06
+              6
+              1
+            
+            
+              S05
+              S05
+              5
+              1
+            
+            
+              S04
+              S04
+              4
+              1
+            
+            
+              S03
+              S03
+              3
+              1
+            
+            
+              S02
+              S02
+              2
+              1
+            
+            
+              S01
+              S01
+              1
+              1
+            
+            
+              S00
+              S00
+              0
+              1
+            
+          
+        
+        
+          RAM_COM3
+          RAM_COM3
+          display memory
+          0x2C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              S31
+              S31
+              31
+              1
+            
+            
+              S30
+              S30
+              30
+              1
+            
+            
+              S29
+              S29
+              29
+              1
+            
+            
+              S28
+              S28
+              28
+              1
+            
+            
+              S27
+              S27
+              27
+              1
+            
+            
+              S26
+              S26
+              26
+              1
+            
+            
+              S25
+              S25
+              25
+              1
+            
+            
+              S24
+              S24
+              24
+              1
+            
+            
+              S23
+              S23
+              23
+              1
+            
+            
+              S22
+              S22
+              22
+              1
+            
+            
+              S21
+              S21
+              21
+              1
+            
+            
+              S20
+              S20
+              20
+              1
+            
+            
+              S19
+              S19
+              19
+              1
+            
+            
+              S18
+              S18
+              18
+              1
+            
+            
+              S17
+              S17
+              17
+              1
+            
+            
+              S16
+              S16
+              16
+              1
+            
+            
+              S15
+              S15
+              15
+              1
+            
+            
+              S14
+              S14
+              14
+              1
+            
+            
+              S13
+              S13
+              13
+              1
+            
+            
+              S12
+              S12
+              12
+              1
+            
+            
+              S11
+              S11
+              11
+              1
+            
+            
+              S10
+              S10
+              10
+              1
+            
+            
+              S09
+              S09
+              9
+              1
+            
+            
+              S08
+              S08
+              8
+              1
+            
+            
+              S07
+              S07
+              7
+              1
+            
+            
+              S06
+              S06
+              6
+              1
+            
+            
+              S05
+              S05
+              5
+              1
+            
+            
+              S04
+              S04
+              4
+              1
+            
+            
+              S03
+              S03
+              3
+              1
+            
+            
+              S02
+              S02
+              2
+              1
+            
+            
+              S01
+              S01
+              1
+              1
+            
+            
+              S00
+              S00
+              0
+              1
+            
+          
+        
+        
+          RAM_COM4
+          RAM_COM4
+          display memory
+          0x34
+          0x20
+          read-write
+          0x00000000
+          
+            
+              S31
+              S31
+              31
+              1
+            
+            
+              S30
+              S30
+              30
+              1
+            
+            
+              S29
+              S29
+              29
+              1
+            
+            
+              S28
+              S28
+              28
+              1
+            
+            
+              S27
+              S27
+              27
+              1
+            
+            
+              S26
+              S26
+              26
+              1
+            
+            
+              S25
+              S25
+              25
+              1
+            
+            
+              S24
+              S24
+              24
+              1
+            
+            
+              S23
+              S23
+              23
+              1
+            
+            
+              S22
+              S22
+              22
+              1
+            
+            
+              S21
+              S21
+              21
+              1
+            
+            
+              S20
+              S20
+              20
+              1
+            
+            
+              S19
+              S19
+              19
+              1
+            
+            
+              S18
+              S18
+              18
+              1
+            
+            
+              S17
+              S17
+              17
+              1
+            
+            
+              S16
+              S16
+              16
+              1
+            
+            
+              S15
+              S15
+              15
+              1
+            
+            
+              S14
+              S14
+              14
+              1
+            
+            
+              S13
+              S13
+              13
+              1
+            
+            
+              S12
+              S12
+              12
+              1
+            
+            
+              S11
+              S11
+              11
+              1
+            
+            
+              S10
+              S10
+              10
+              1
+            
+            
+              S09
+              S09
+              9
+              1
+            
+            
+              S08
+              S08
+              8
+              1
+            
+            
+              S07
+              S07
+              7
+              1
+            
+            
+              S06
+              S06
+              6
+              1
+            
+            
+              S05
+              S05
+              5
+              1
+            
+            
+              S04
+              S04
+              4
+              1
+            
+            
+              S03
+              S03
+              3
+              1
+            
+            
+              S02
+              S02
+              2
+              1
+            
+            
+              S01
+              S01
+              1
+              1
+            
+            
+              S00
+              S00
+              0
+              1
+            
+          
+        
+        
+          RAM_COM5
+          RAM_COM5
+          display memory
+          0x3C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              S31
+              S31
+              31
+              1
+            
+            
+              S30
+              S30
+              30
+              1
+            
+            
+              S29
+              S29
+              29
+              1
+            
+            
+              S28
+              S28
+              28
+              1
+            
+            
+              S27
+              S27
+              27
+              1
+            
+            
+              S26
+              S26
+              26
+              1
+            
+            
+              S25
+              S25
+              25
+              1
+            
+            
+              S24
+              S24
+              24
+              1
+            
+            
+              S23
+              S23
+              23
+              1
+            
+            
+              S22
+              S22
+              22
+              1
+            
+            
+              S21
+              S21
+              21
+              1
+            
+            
+              S20
+              S20
+              20
+              1
+            
+            
+              S19
+              S19
+              19
+              1
+            
+            
+              S18
+              S18
+              18
+              1
+            
+            
+              S17
+              S17
+              17
+              1
+            
+            
+              S16
+              S16
+              16
+              1
+            
+            
+              S15
+              S15
+              15
+              1
+            
+            
+              S14
+              S14
+              14
+              1
+            
+            
+              S13
+              S13
+              13
+              1
+            
+            
+              S12
+              S12
+              12
+              1
+            
+            
+              S11
+              S11
+              11
+              1
+            
+            
+              S10
+              S10
+              10
+              1
+            
+            
+              S09
+              S09
+              9
+              1
+            
+            
+              S08
+              S08
+              8
+              1
+            
+            
+              S07
+              S07
+              7
+              1
+            
+            
+              S06
+              S06
+              6
+              1
+            
+            
+              S05
+              S05
+              5
+              1
+            
+            
+              S04
+              S04
+              4
+              1
+            
+            
+              S03
+              S03
+              3
+              1
+            
+            
+              S02
+              S02
+              2
+              1
+            
+            
+              S01
+              S01
+              1
+              1
+            
+            
+              S00
+              S00
+              0
+              1
+            
+          
+        
+        
+          RAM_COM6
+          RAM_COM6
+          display memory
+          0x44
+          0x20
+          read-write
+          0x00000000
+          
+            
+              S31
+              S31
+              31
+              1
+            
+            
+              S30
+              S30
+              30
+              1
+            
+            
+              S29
+              S29
+              29
+              1
+            
+            
+              S28
+              S28
+              28
+              1
+            
+            
+              S27
+              S27
+              27
+              1
+            
+            
+              S26
+              S26
+              26
+              1
+            
+            
+              S25
+              S25
+              25
+              1
+            
+            
+              S24
+              S24
+              24
+              1
+            
+            
+              S23
+              S23
+              23
+              1
+            
+            
+              S22
+              S22
+              22
+              1
+            
+            
+              S21
+              S21
+              21
+              1
+            
+            
+              S20
+              S20
+              20
+              1
+            
+            
+              S19
+              S19
+              19
+              1
+            
+            
+              S18
+              S18
+              18
+              1
+            
+            
+              S17
+              S17
+              17
+              1
+            
+            
+              S16
+              S16
+              16
+              1
+            
+            
+              S15
+              S15
+              15
+              1
+            
+            
+              S14
+              S14
+              14
+              1
+            
+            
+              S13
+              S13
+              13
+              1
+            
+            
+              S12
+              S12
+              12
+              1
+            
+            
+              S11
+              S11
+              11
+              1
+            
+            
+              S10
+              S10
+              10
+              1
+            
+            
+              S09
+              S09
+              9
+              1
+            
+            
+              S08
+              S08
+              8
+              1
+            
+            
+              S07
+              S07
+              7
+              1
+            
+            
+              S06
+              S06
+              6
+              1
+            
+            
+              S05
+              S05
+              5
+              1
+            
+            
+              S04
+              S04
+              4
+              1
+            
+            
+              S03
+              S03
+              3
+              1
+            
+            
+              S02
+              S02
+              2
+              1
+            
+            
+              S01
+              S01
+              1
+              1
+            
+            
+              S00
+              S00
+              0
+              1
+            
+          
+        
+        
+          RAM_COM7
+          RAM_COM7
+          display memory
+          0x4C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              S31
+              S31
+              31
+              1
+            
+            
+              S30
+              S30
+              30
+              1
+            
+            
+              S29
+              S29
+              29
+              1
+            
+            
+              S28
+              S28
+              28
+              1
+            
+            
+              S27
+              S27
+              27
+              1
+            
+            
+              S26
+              S26
+              26
+              1
+            
+            
+              S25
+              S25
+              25
+              1
+            
+            
+              S24
+              S24
+              24
+              1
+            
+            
+              S23
+              S23
+              23
+              1
+            
+            
+              S22
+              S22
+              22
+              1
+            
+            
+              S21
+              S21
+              21
+              1
+            
+            
+              S20
+              S20
+              20
+              1
+            
+            
+              S19
+              S19
+              19
+              1
+            
+            
+              S18
+              S18
+              18
+              1
+            
+            
+              S17
+              S17
+              17
+              1
+            
+            
+              S16
+              S16
+              16
+              1
+            
+            
+              S15
+              S15
+              15
+              1
+            
+            
+              S14
+              S14
+              14
+              1
+            
+            
+              S13
+              S13
+              13
+              1
+            
+            
+              S12
+              S12
+              12
+              1
+            
+            
+              S11
+              S11
+              11
+              1
+            
+            
+              S10
+              S10
+              10
+              1
+            
+            
+              S09
+              S09
+              9
+              1
+            
+            
+              S08
+              S08
+              8
+              1
+            
+            
+              S07
+              S07
+              7
+              1
+            
+            
+              S06
+              S06
+              6
+              1
+            
+            
+              S05
+              S05
+              5
+              1
+            
+            
+              S04
+              S04
+              4
+              1
+            
+            
+              S03
+              S03
+              3
+              1
+            
+            
+              S02
+              S02
+              2
+              1
+            
+            
+              S01
+              S01
+              1
+              1
+            
+            
+              S00
+              S00
+              0
+              1
+            
+          
+        
+      
+    
+    
+      MPU
+      Memory protection unit
+      MPU
+      0xE000ED90
+      
+        0x0
+        0x15
+        registers
+      
+      
+        
+          MPU_TYPER
+          MPU_TYPER
+          MPU type register
+          0x0
+          0x20
+          read-only
+          0X00000800
+          
+            
+              SEPARATE
+              Separate flag
+              0
+              1
+            
+            
+              DREGION
+              Number of MPU data regions
+              8
+              8
+            
+            
+              IREGION
+              Number of MPU instruction
+              regions
+              16
+              8
+            
+          
+        
+        
+          MPU_CTRL
+          MPU_CTRL
+          MPU control register
+          0x4
+          0x20
+          read-only
+          0X00000000
+          
+            
+              ENABLE
+              Enables the MPU
+              0
+              1
+            
+            
+              HFNMIENA
+              Enables the operation of MPU during hard
+              fault
+              1
+              1
+            
+            
+              PRIVDEFENA
+              Enable priviliged software access to
+              default memory map
+              2
+              1
+            
+          
+        
+        
+          MPU_RNR
+          MPU_RNR
+          MPU region number register
+          0x8
+          0x20
+          read-write
+          0X00000000
+          
+            
+              REGION
+              MPU region
+              0
+              8
+            
+          
+        
+        
+          MPU_RBAR
+          MPU_RBAR
+          MPU region base address
+          register
+          0xC
+          0x20
+          read-write
+          0X00000000
+          
+            
+              REGION
+              MPU region field
+              0
+              4
+            
+            
+              VALID
+              MPU region number valid
+              4
+              1
+            
+            
+              ADDR
+              Region base address field
+              5
+              27
+            
+          
+        
+        
+          MPU_RASR
+          MPU_RASR
+          MPU region attribute and size
+          register
+          0x10
+          0x20
+          read-write
+          0X00000000
+          
+            
+              ENABLE
+              Region enable bit.
+              0
+              1
+            
+            
+              SIZE
+              Size of the MPU protection
+              region
+              1
+              5
+            
+            
+              SRD
+              Subregion disable bits
+              8
+              8
+            
+            
+              B
+              memory attribute
+              16
+              1
+            
+            
+              C
+              memory attribute
+              17
+              1
+            
+            
+              S
+              Shareable memory attribute
+              18
+              1
+            
+            
+              TEX
+              memory attribute
+              19
+              3
+            
+            
+              AP
+              Access permission
+              24
+              3
+            
+            
+              XN
+              Instruction access disable
+              bit
+              28
+              1
+            
+          
+        
+      
+    
+    
+      STK
+      SysTick timer
+      STK
+      0xE000E010
+      
+        0x0
+        0x11
+        registers
+      
+      
+        
+          CSR
+          CSR
+          SysTick control and status
+          register
+          0x0
+          0x20
+          read-write
+          0X00000000
+          
+            
+              ENABLE
+              Counter enable
+              0
+              1
+            
+            
+              TICKINT
+              SysTick exception request
+              enable
+              1
+              1
+            
+            
+              CLKSOURCE
+              Clock source selection
+              2
+              1
+            
+            
+              COUNTFLAG
+              COUNTFLAG
+              16
+              1
+            
+          
+        
+        
+          RVR
+          RVR
+          SysTick reload value register
+          0x4
+          0x20
+          read-write
+          0X00000000
+          
+            
+              RELOAD
+              RELOAD value
+              0
+              24
+            
+          
+        
+        
+          CVR
+          CVR
+          SysTick current value register
+          0x8
+          0x20
+          read-write
+          0X00000000
+          
+            
+              CURRENT
+              Current counter value
+              0
+              24
+            
+          
+        
+        
+          CALIB
+          CALIB
+          SysTick calibration value
+          register
+          0xC
+          0x20
+          read-write
+          0X00000000
+          
+            
+              TENMS
+              Calibration value
+              0
+              24
+            
+            
+              SKEW
+              SKEW flag: Indicates whether the TENMS
+              value is exact
+              30
+              1
+            
+            
+              NOREF
+              NOREF flag. Reads as zero
+              31
+              1
+            
+          
+        
+      
+    
+    
+      SCB
+      System control block
+      SCB
+      0xE000ED00
+      
+        0x0
+        0x41
+        registers
+      
+      
+        
+          CPUID
+          CPUID
+          CPUID base register
+          0x0
+          0x20
+          read-only
+          0x410FC241
+          
+            
+              Revision
+              Revision number
+              0
+              4
+            
+            
+              PartNo
+              Part number of the
+              processor
+              4
+              12
+            
+            
+              Architecture
+              Reads as 0xF
+              16
+              4
+            
+            
+              Variant
+              Variant number
+              20
+              4
+            
+            
+              Implementer
+              Implementer code
+              24
+              8
+            
+          
+        
+        
+          ICSR
+          ICSR
+          Interrupt control and state
+          register
+          0x4
+          0x20
+          read-write
+          0x00000000
+          
+            
+              VECTACTIVE
+              Active vector
+              0
+              9
+            
+            
+              RETTOBASE
+              Return to base level
+              11
+              1
+            
+            
+              VECTPENDING
+              Pending vector
+              12
+              7
+            
+            
+              ISRPENDING
+              Interrupt pending flag
+              22
+              1
+            
+            
+              PENDSTCLR
+              SysTick exception clear-pending
+              bit
+              25
+              1
+            
+            
+              PENDSTSET
+              SysTick exception set-pending
+              bit
+              26
+              1
+            
+            
+              PENDSVCLR
+              PendSV clear-pending bit
+              27
+              1
+            
+            
+              PENDSVSET
+              PendSV set-pending bit
+              28
+              1
+            
+            
+              NMIPENDSET
+              NMI set-pending bit.
+              31
+              1
+            
+          
+        
+        
+          VTOR
+          VTOR
+          Vector table offset register
+          0x8
+          0x20
+          read-write
+          0x00000000
+          
+            
+              TBLOFF
+              Vector table base offset
+              field
+              7
+              25
+            
+          
+        
+        
+          AIRCR
+          AIRCR
+          Application interrupt and reset control
+          register
+          0xC
+          0x20
+          read-write
+          0x00000000
+          
+            
+              VECTCLRACTIVE
+              VECTCLRACTIVE
+              1
+              1
+            
+            
+              SYSRESETREQ
+              SYSRESETREQ
+              2
+              1
+            
+            
+              ENDIANESS
+              ENDIANESS
+              15
+              1
+            
+            
+              VECTKEYSTAT
+              Register key
+              16
+              16
+            
+          
+        
+        
+          SCR
+          SCR
+          System control register
+          0x10
+          0x20
+          read-write
+          0x00000000
+          
+            
+              SLEEPONEXIT
+              SLEEPONEXIT
+              1
+              1
+            
+            
+              SLEEPDEEP
+              SLEEPDEEP
+              2
+              1
+            
+            
+              SEVEONPEND
+              Send Event on Pending bit
+              4
+              1
+            
+          
+        
+        
+          CCR
+          CCR
+          Configuration and control
+          register
+          0x14
+          0x20
+          read-write
+          0x00000000
+          
+            
+              NONBASETHRDENA
+              Configures how the processor enters
+              Thread mode
+              0
+              1
+            
+            
+              USERSETMPEND
+              USERSETMPEND
+              1
+              1
+            
+            
+              UNALIGN__TRP
+              UNALIGN_ TRP
+              3
+              1
+            
+            
+              DIV_0_TRP
+              DIV_0_TRP
+              4
+              1
+            
+            
+              BFHFNMIGN
+              BFHFNMIGN
+              8
+              1
+            
+            
+              STKALIGN
+              STKALIGN
+              9
+              1
+            
+          
+        
+        
+          SHPR2
+          SHPR2
+          System handler priority
+          registers
+          0x1C
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_11
+              Priority of system handler
+              11
+              24
+              8
+            
+          
+        
+        
+          SHPR3
+          SHPR3
+          System handler priority
+          registers
+          0x20
+          0x20
+          read-write
+          0x00000000
+          
+            
+              PRI_14
+              Priority of system handler
+              14
+              16
+              8
+            
+            
+              PRI_15
+              Priority of system handler
+              15
+              24
+              8
+            
+          
+        
+      
+    
+  
+

From 01287dd68db70950b901c056f76453e767b0cfa0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 18:16:10 +0200
Subject: [PATCH 213/286] Rough file architecture

---
 .github/workflows/build.yml            |   2 +
 .gitignore                             |   9 +-
 espressif-esp/blinky/blinky.zig        |  57 ++++++++
 build.zig => espressif-esp/build.zig   |   0
 espressif-esp/build.zig.zon            |  14 ++
 ezpkg.sh                               |  13 --
 generic/build.zig                      |  84 +++++++++++
 build.zig.zon => generic/build.zig.zon |   2 +-
 {src => generic/src}/blinky.zig        |   0
 {src => generic/src}/empty.zig         |   0
 gigadevice-gd32/build.zig              |  84 +++++++++++
 gigadevice-gd32/build.zig.zon          |  14 ++
 microchip-atmega/build.zig             |  84 +++++++++++
 microchip-atmega/build.zig.zon         |  14 ++
 nordic-nrf5x/README.adoc               |  11 ++
 nordic-nrf5x/build.zig                 |  84 +++++++++++
 nordic-nrf5x/build.zig.zon             |  14 ++
 nxp-lpc/build.zig                      |  84 +++++++++++
 nxp-lpc/build.zig.zon                  |  14 ++
 nxp-lpc/src/blinky.zig                 |   0
 rp2040/build.zig                       |  84 +++++++++++
 rp2040/build.zig.zon                   |  14 ++
 rp2040/scripts/hid_test.py             |  29 ++++
 rp2040/scripts/usb_device_loopback.py  |  48 +++++++
 rp2040/src/adc.zig                     |  40 ++++++
 rp2040/src/blinky.zig                  |  20 +++
 rp2040/src/blinky_core1.zig            |  28 ++++
 rp2040/src/flash_program.zig           |  81 +++++++++++
 rp2040/src/gpio_clk.zig                |  16 +++
 rp2040/src/i2c_bus_scan.zig            |  44 ++++++
 rp2040/src/pwm.zig                     |  23 +++
 rp2040/src/random.zig                  |  68 +++++++++
 rp2040/src/spi_master.zig              |  26 ++++
 rp2040/src/squarewave.zig              |  84 +++++++++++
 rp2040/src/uart.zig                    |  49 +++++++
 rp2040/src/usb_device.zig              | 172 +++++++++++++++++++++++
 rp2040/src/usb_hid.zig                 | 187 +++++++++++++++++++++++++
 rp2040/src/ws2812.zig                  |  94 +++++++++++++
 shell.nix                              |   9 --
 stmicro-stm32/build.zig                |  84 +++++++++++
 stmicro-stm32/build.zig.zon            |  14 ++
 41 files changed, 1773 insertions(+), 25 deletions(-)
 create mode 100644 espressif-esp/blinky/blinky.zig
 rename build.zig => espressif-esp/build.zig (100%)
 create mode 100644 espressif-esp/build.zig.zon
 delete mode 100755 ezpkg.sh
 create mode 100644 generic/build.zig
 rename build.zig.zon => generic/build.zig.zon (98%)
 rename {src => generic/src}/blinky.zig (100%)
 rename {src => generic/src}/empty.zig (100%)
 create mode 100644 gigadevice-gd32/build.zig
 create mode 100644 gigadevice-gd32/build.zig.zon
 create mode 100644 microchip-atmega/build.zig
 create mode 100644 microchip-atmega/build.zig.zon
 create mode 100644 nordic-nrf5x/README.adoc
 create mode 100644 nordic-nrf5x/build.zig
 create mode 100644 nordic-nrf5x/build.zig.zon
 create mode 100644 nxp-lpc/build.zig
 create mode 100644 nxp-lpc/build.zig.zon
 create mode 100644 nxp-lpc/src/blinky.zig
 create mode 100644 rp2040/build.zig
 create mode 100644 rp2040/build.zig.zon
 create mode 100755 rp2040/scripts/hid_test.py
 create mode 100755 rp2040/scripts/usb_device_loopback.py
 create mode 100644 rp2040/src/adc.zig
 create mode 100644 rp2040/src/blinky.zig
 create mode 100644 rp2040/src/blinky_core1.zig
 create mode 100644 rp2040/src/flash_program.zig
 create mode 100644 rp2040/src/gpio_clk.zig
 create mode 100644 rp2040/src/i2c_bus_scan.zig
 create mode 100644 rp2040/src/pwm.zig
 create mode 100644 rp2040/src/random.zig
 create mode 100644 rp2040/src/spi_master.zig
 create mode 100644 rp2040/src/squarewave.zig
 create mode 100644 rp2040/src/uart.zig
 create mode 100644 rp2040/src/usb_device.zig
 create mode 100644 rp2040/src/usb_hid.zig
 create mode 100644 rp2040/src/ws2812.zig
 delete mode 100644 shell.nix
 create mode 100644 stmicro-stm32/build.zig
 create mode 100644 stmicro-stm32/build.zig.zon

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index af725e66c..ee9f1bb00 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -11,6 +11,7 @@ jobs:
     strategy:
       matrix:
         os: [windows-latest, macos-latest, ubuntu-latest]
+        dir: espressif-esp  generic  gigadevice-gd32  microchip-atmega  nordic-nrf5x  nxp-lpc  rp2040  stmicro-stm32
     steps:
       - name: Checkout
         uses: actions/checkout@v2
@@ -21,4 +22,5 @@ jobs:
           version: 0.11.0
 
       - name: Build examples
+        working-directory: ${{ matrix.dir }}
         run: zig build
diff --git a/.gitignore b/.gitignore
index f975728be..585506141 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,4 +1,9 @@
 zig-cache/
-dev-scripts/
-zig-out
+zig-out/
+
+ezpkg.sh
+
+.vscode
+
 .envrc
+shell.nix
diff --git a/espressif-esp/blinky/blinky.zig b/espressif-esp/blinky/blinky.zig
new file mode 100644
index 000000000..811b04894
--- /dev/null
+++ b/espressif-esp/blinky/blinky.zig
@@ -0,0 +1,57 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const peripherals = microzig.chip.peripherals;
+const TIMG0 = peripherals.TIMG0;
+const RTC_CNTL = peripherals.RTC_CNTL;
+const INTERRUPT_CORE0 = peripherals.INTERRUPT_CORE0;
+const GPIO = peripherals.GPIO;
+
+const dogfood: u32 = 0x50D83AA1;
+const super_dogfood: u32 = 0x8F1D312A;
+
+pub fn main() !void {
+    TIMG0.WDTWPROTECT.raw = dogfood;
+    TIMG0.WDTCONFIG0.raw = 0;
+    TIMG0.WDTWPROTECT.raw = 0;
+
+    RTC_CNTL.WDTWPROTECT.raw = dogfood;
+    RTC_CNTL.WDTCONFIG0.raw = 0;
+    RTC_CNTL.WDTWPROTECT.raw = 0;
+
+    RTC_CNTL.SWD_WPROTECT.raw = super_dogfood;
+    RTC_CNTL.SWD_CONF.modify(.{ .SWD_DISABLE = 1 });
+    RTC_CNTL.SWD_WPROTECT.raw = 0;
+
+    INTERRUPT_CORE0.CPU_INT_ENABLE.raw = 0;
+
+    microzig.hal.gpio.init(LED_R_PIN, .{
+        .direction = .output,
+        .direct_io = true,
+    });
+    microzig.hal.gpio.init(LED_G_PIN, .{
+        .direction = .output,
+        .direct_io = true,
+    });
+    microzig.hal.gpio.init(LED_B_PIN, .{
+        .direction = .output,
+        .direct_io = true,
+    });
+
+    microzig.hal.uart.write(0, "Hello from Zig!\r\n");
+
+    while (true) {
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
+        microzig.hal.uart.write(0, "R");
+        microzig.core.experimental.debug.busy_sleep(100_000);
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
+        microzig.hal.uart.write(0, "G");
+        microzig.core.experimental.debug.busy_sleep(100_000);
+        GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
+        microzig.hal.uart.write(0, "B");
+        microzig.core.experimental.debug.busy_sleep(100_000);
+    }
+}
+
+const LED_R_PIN = 3; // GPIO
+const LED_G_PIN = 16; // GPIO
+const LED_B_PIN = 17; // GPIO
diff --git a/build.zig b/espressif-esp/build.zig
similarity index 100%
rename from build.zig
rename to espressif-esp/build.zig
diff --git a/espressif-esp/build.zig.zon b/espressif-esp/build.zig.zon
new file mode 100644
index 000000000..a729ce616
--- /dev/null
+++ b/espressif-esp/build.zig.zon
@@ -0,0 +1,14 @@
+.{
+    .name = "microzig-espressif-esp-examples",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
+            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
+        },
+        .esp = .{
+            .url = "https://github.com/ZigEmbeddedGroup/espressif-esp/archive/59b8ca028915c0d6224ec88dbf4db19afbb559c0.tar.gz",
+            .hash = "1220f6e5f22416fdc63442cd8869fcaa35f9abf30d878ea3d80073176677dc6f8a65",
+        },
+    },
+}
diff --git a/ezpkg.sh b/ezpkg.sh
deleted file mode 100755
index caafa0365..000000000
--- a/ezpkg.sh
+++ /dev/null
@@ -1,13 +0,0 @@
-#!/bin/sh
-
-exec ezpkg \
-    microzig=/home/felix/projects/zeg/microzig \
-    microzig.uf2=/home/felix/projects/zeg/uf2 \
-    microzig.regz=/home/felix/projects/zeg/regz \
-    rp2040=/home/felix/projects/zeg/device-support-package/rp2040 \
-    stm32=/home/felix/projects/zeg/device-support-package/stmicro-stm32 \
-    lpc=/home/felix/projects/zeg/device-support-package/nxp-lpc \
-    gd32=/home/felix/projects/zeg/device-support-package/gigadevice-gd32 \
-    esp=/home/felix/projects/zeg/device-support-package/espressif-esp \
-    nrf5x=/home/felix/projects/zeg/device-support-package/nordic-nrf5x \
-    atmega=/home/felix/projects/zeg/device-support-package/microchip-atmega 
\ No newline at end of file
diff --git a/generic/build.zig b/generic/build.zig
new file mode 100644
index 000000000..406477261
--- /dev/null
+++ b/generic/build.zig
@@ -0,0 +1,84 @@
+const std = @import("std");
+const rp2040 = @import("rp2040");
+const stm32 = @import("stm32");
+const lpc = @import("lpc");
+const gd32 = @import("gd32");
+const nrf5x = @import("nrf5x");
+const esp = @import("esp");
+const atmega = @import("atmega");
+
+pub fn build(b: *std.Build) void {
+    const microzig = @import("microzig").init(b, "microzig");
+    const optimize = b.standardOptimizeOption(.{});
+
+    const TargetDesc = struct {
+        target: @import("microzig").Target,
+        name: []const u8,
+    };
+
+    const available_targets = [_]TargetDesc{
+        // RP2040
+        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
+        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
+        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
+        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
+
+        // STM32
+        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
+        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
+        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
+        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
+        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
+        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
+        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
+        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
+
+        // NXP LPC
+        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
+        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+
+        // GigaDevice GD32
+        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
+        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
+        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
+
+        // Nordic Nrf5x
+        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
+        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
+        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
+
+        // RISC-V Espressif ESP
+        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
+
+        // Microchip ATmega
+        // TODO: Fix compiler bugs
+        // - https://github.com/ziglang/zig/issues/17219
+        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
+        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
+        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
+    };
+
+    for (available_targets) |dest| {
+        // `addFirmware` basically works like addExecutable, but takes a
+        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+        //
+        // The target will convey all necessary information on the chip,
+        // cpu and potentially the board as well.
+        const firmware = microzig.addFirmware(b, .{
+            .name = b.fmt("empty-{s}", .{dest.name}),
+            .target = dest.target,
+            .optimize = optimize,
+            .source_file = .{ .path = "src/empty.zig" },
+        });
+
+        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+        // and allows installing the firmware as a typical firmware file.
+        //
+        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+        microzig.installFirmware(b, firmware, .{});
+
+        // For debugging, we also always install the firmware as an ELF file
+        microzig.installFirmware(b, firmware, .{ .format = .elf });
+    }
+}
diff --git a/build.zig.zon b/generic/build.zig.zon
similarity index 98%
rename from build.zig.zon
rename to generic/build.zig.zon
index 716625979..fba280d24 100644
--- a/build.zig.zon
+++ b/generic/build.zig.zon
@@ -1,5 +1,5 @@
 .{
-    .name = "microzig-examples",
+    .name = "microzig-generic-examples",
     .version = "0.1.0",
     .dependencies = .{
         .microzig = .{
diff --git a/src/blinky.zig b/generic/src/blinky.zig
similarity index 100%
rename from src/blinky.zig
rename to generic/src/blinky.zig
diff --git a/src/empty.zig b/generic/src/empty.zig
similarity index 100%
rename from src/empty.zig
rename to generic/src/empty.zig
diff --git a/gigadevice-gd32/build.zig b/gigadevice-gd32/build.zig
new file mode 100644
index 000000000..406477261
--- /dev/null
+++ b/gigadevice-gd32/build.zig
@@ -0,0 +1,84 @@
+const std = @import("std");
+const rp2040 = @import("rp2040");
+const stm32 = @import("stm32");
+const lpc = @import("lpc");
+const gd32 = @import("gd32");
+const nrf5x = @import("nrf5x");
+const esp = @import("esp");
+const atmega = @import("atmega");
+
+pub fn build(b: *std.Build) void {
+    const microzig = @import("microzig").init(b, "microzig");
+    const optimize = b.standardOptimizeOption(.{});
+
+    const TargetDesc = struct {
+        target: @import("microzig").Target,
+        name: []const u8,
+    };
+
+    const available_targets = [_]TargetDesc{
+        // RP2040
+        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
+        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
+        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
+        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
+
+        // STM32
+        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
+        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
+        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
+        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
+        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
+        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
+        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
+        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
+
+        // NXP LPC
+        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
+        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+
+        // GigaDevice GD32
+        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
+        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
+        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
+
+        // Nordic Nrf5x
+        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
+        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
+        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
+
+        // RISC-V Espressif ESP
+        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
+
+        // Microchip ATmega
+        // TODO: Fix compiler bugs
+        // - https://github.com/ziglang/zig/issues/17219
+        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
+        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
+        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
+    };
+
+    for (available_targets) |dest| {
+        // `addFirmware` basically works like addExecutable, but takes a
+        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+        //
+        // The target will convey all necessary information on the chip,
+        // cpu and potentially the board as well.
+        const firmware = microzig.addFirmware(b, .{
+            .name = b.fmt("empty-{s}", .{dest.name}),
+            .target = dest.target,
+            .optimize = optimize,
+            .source_file = .{ .path = "src/empty.zig" },
+        });
+
+        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+        // and allows installing the firmware as a typical firmware file.
+        //
+        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+        microzig.installFirmware(b, firmware, .{});
+
+        // For debugging, we also always install the firmware as an ELF file
+        microzig.installFirmware(b, firmware, .{ .format = .elf });
+    }
+}
diff --git a/gigadevice-gd32/build.zig.zon b/gigadevice-gd32/build.zig.zon
new file mode 100644
index 000000000..2cfeaae93
--- /dev/null
+++ b/gigadevice-gd32/build.zig.zon
@@ -0,0 +1,14 @@
+.{
+    .name = "microzig-gigadevice-gd32-examples",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
+            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
+        },
+        .gd32 = .{
+            .url = "https://github.com/ZigEmbeddedGroup/gigadevice-gd32/archive/9324753cc3b8e7afe83fcda085bcfe76681a3be3.tar.gz",
+            .hash = "122043ff4dcbc342f25dbb936b0d9eaa701ac3509e2cbe6764be37b90d31c7a385d0",
+        },
+    },
+}
diff --git a/microchip-atmega/build.zig b/microchip-atmega/build.zig
new file mode 100644
index 000000000..406477261
--- /dev/null
+++ b/microchip-atmega/build.zig
@@ -0,0 +1,84 @@
+const std = @import("std");
+const rp2040 = @import("rp2040");
+const stm32 = @import("stm32");
+const lpc = @import("lpc");
+const gd32 = @import("gd32");
+const nrf5x = @import("nrf5x");
+const esp = @import("esp");
+const atmega = @import("atmega");
+
+pub fn build(b: *std.Build) void {
+    const microzig = @import("microzig").init(b, "microzig");
+    const optimize = b.standardOptimizeOption(.{});
+
+    const TargetDesc = struct {
+        target: @import("microzig").Target,
+        name: []const u8,
+    };
+
+    const available_targets = [_]TargetDesc{
+        // RP2040
+        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
+        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
+        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
+        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
+
+        // STM32
+        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
+        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
+        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
+        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
+        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
+        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
+        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
+        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
+
+        // NXP LPC
+        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
+        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+
+        // GigaDevice GD32
+        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
+        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
+        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
+
+        // Nordic Nrf5x
+        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
+        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
+        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
+
+        // RISC-V Espressif ESP
+        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
+
+        // Microchip ATmega
+        // TODO: Fix compiler bugs
+        // - https://github.com/ziglang/zig/issues/17219
+        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
+        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
+        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
+    };
+
+    for (available_targets) |dest| {
+        // `addFirmware` basically works like addExecutable, but takes a
+        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+        //
+        // The target will convey all necessary information on the chip,
+        // cpu and potentially the board as well.
+        const firmware = microzig.addFirmware(b, .{
+            .name = b.fmt("empty-{s}", .{dest.name}),
+            .target = dest.target,
+            .optimize = optimize,
+            .source_file = .{ .path = "src/empty.zig" },
+        });
+
+        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+        // and allows installing the firmware as a typical firmware file.
+        //
+        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+        microzig.installFirmware(b, firmware, .{});
+
+        // For debugging, we also always install the firmware as an ELF file
+        microzig.installFirmware(b, firmware, .{ .format = .elf });
+    }
+}
diff --git a/microchip-atmega/build.zig.zon b/microchip-atmega/build.zig.zon
new file mode 100644
index 000000000..f3c3bdfc1
--- /dev/null
+++ b/microchip-atmega/build.zig.zon
@@ -0,0 +1,14 @@
+.{
+    .name = "microzig-microchip-atmega-examples",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
+            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
+        },
+        .atmega = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microchip-atmega/archive/feefcb87a63c0aae31afb783d4e388e90c4d922f.tar.gz",
+            .hash = "1220048dc5d22729ee119a496f8b8ca3556838af1f3bd32ce6acd5f76480ec942965",
+        },
+    },
+}
diff --git a/nordic-nrf5x/README.adoc b/nordic-nrf5x/README.adoc
new file mode 100644
index 000000000..7c2fa2fb5
--- /dev/null
+++ b/nordic-nrf5x/README.adoc
@@ -0,0 +1,11 @@
+= Nordic nrf5x
+
+HALs and register definitions for nrf5x devices
+
+== What version of Zig to use
+
+Right now we are following https://ziglang.org/download/[master], but once 0.11.0 is released, we will be switching to the latest stable version of Zig.
+
+== Renode supports:
+
+- nrf52840 development kit
diff --git a/nordic-nrf5x/build.zig b/nordic-nrf5x/build.zig
new file mode 100644
index 000000000..406477261
--- /dev/null
+++ b/nordic-nrf5x/build.zig
@@ -0,0 +1,84 @@
+const std = @import("std");
+const rp2040 = @import("rp2040");
+const stm32 = @import("stm32");
+const lpc = @import("lpc");
+const gd32 = @import("gd32");
+const nrf5x = @import("nrf5x");
+const esp = @import("esp");
+const atmega = @import("atmega");
+
+pub fn build(b: *std.Build) void {
+    const microzig = @import("microzig").init(b, "microzig");
+    const optimize = b.standardOptimizeOption(.{});
+
+    const TargetDesc = struct {
+        target: @import("microzig").Target,
+        name: []const u8,
+    };
+
+    const available_targets = [_]TargetDesc{
+        // RP2040
+        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
+        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
+        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
+        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
+
+        // STM32
+        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
+        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
+        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
+        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
+        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
+        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
+        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
+        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
+
+        // NXP LPC
+        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
+        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+
+        // GigaDevice GD32
+        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
+        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
+        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
+
+        // Nordic Nrf5x
+        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
+        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
+        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
+
+        // RISC-V Espressif ESP
+        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
+
+        // Microchip ATmega
+        // TODO: Fix compiler bugs
+        // - https://github.com/ziglang/zig/issues/17219
+        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
+        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
+        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
+    };
+
+    for (available_targets) |dest| {
+        // `addFirmware` basically works like addExecutable, but takes a
+        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+        //
+        // The target will convey all necessary information on the chip,
+        // cpu and potentially the board as well.
+        const firmware = microzig.addFirmware(b, .{
+            .name = b.fmt("empty-{s}", .{dest.name}),
+            .target = dest.target,
+            .optimize = optimize,
+            .source_file = .{ .path = "src/empty.zig" },
+        });
+
+        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+        // and allows installing the firmware as a typical firmware file.
+        //
+        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+        microzig.installFirmware(b, firmware, .{});
+
+        // For debugging, we also always install the firmware as an ELF file
+        microzig.installFirmware(b, firmware, .{ .format = .elf });
+    }
+}
diff --git a/nordic-nrf5x/build.zig.zon b/nordic-nrf5x/build.zig.zon
new file mode 100644
index 000000000..2034409a0
--- /dev/null
+++ b/nordic-nrf5x/build.zig.zon
@@ -0,0 +1,14 @@
+.{
+    .name = "microzig-nordic-nrf5x-examples",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
+            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
+        },
+        .nrf5x = .{
+            .url = "https://github.com/ZigEmbeddedGroup/nordic-nrf5x/archive/0ab136860ccf7eb1d07969c3ef523f3cd898e2ff.tar.gz",
+            .hash = "1220980da06f9634dcff06afefa7aa111bd030018fea49f79e86657dab69621e1d08",
+        },
+    },
+}
diff --git a/nxp-lpc/build.zig b/nxp-lpc/build.zig
new file mode 100644
index 000000000..406477261
--- /dev/null
+++ b/nxp-lpc/build.zig
@@ -0,0 +1,84 @@
+const std = @import("std");
+const rp2040 = @import("rp2040");
+const stm32 = @import("stm32");
+const lpc = @import("lpc");
+const gd32 = @import("gd32");
+const nrf5x = @import("nrf5x");
+const esp = @import("esp");
+const atmega = @import("atmega");
+
+pub fn build(b: *std.Build) void {
+    const microzig = @import("microzig").init(b, "microzig");
+    const optimize = b.standardOptimizeOption(.{});
+
+    const TargetDesc = struct {
+        target: @import("microzig").Target,
+        name: []const u8,
+    };
+
+    const available_targets = [_]TargetDesc{
+        // RP2040
+        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
+        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
+        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
+        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
+
+        // STM32
+        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
+        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
+        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
+        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
+        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
+        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
+        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
+        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
+
+        // NXP LPC
+        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
+        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+
+        // GigaDevice GD32
+        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
+        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
+        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
+
+        // Nordic Nrf5x
+        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
+        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
+        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
+
+        // RISC-V Espressif ESP
+        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
+
+        // Microchip ATmega
+        // TODO: Fix compiler bugs
+        // - https://github.com/ziglang/zig/issues/17219
+        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
+        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
+        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
+    };
+
+    for (available_targets) |dest| {
+        // `addFirmware` basically works like addExecutable, but takes a
+        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+        //
+        // The target will convey all necessary information on the chip,
+        // cpu and potentially the board as well.
+        const firmware = microzig.addFirmware(b, .{
+            .name = b.fmt("empty-{s}", .{dest.name}),
+            .target = dest.target,
+            .optimize = optimize,
+            .source_file = .{ .path = "src/empty.zig" },
+        });
+
+        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+        // and allows installing the firmware as a typical firmware file.
+        //
+        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+        microzig.installFirmware(b, firmware, .{});
+
+        // For debugging, we also always install the firmware as an ELF file
+        microzig.installFirmware(b, firmware, .{ .format = .elf });
+    }
+}
diff --git a/nxp-lpc/build.zig.zon b/nxp-lpc/build.zig.zon
new file mode 100644
index 000000000..aa5a11a05
--- /dev/null
+++ b/nxp-lpc/build.zig.zon
@@ -0,0 +1,14 @@
+.{
+    .name = "microzig-nxp-lpc-examples",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
+            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
+        },
+        .lpc = .{
+            .url = "https://github.com/ZigEmbeddedGroup/nxp-lpc/archive/130a1316c0892415e7da958a5e9548ed87bba54d.tar.gz",
+            .hash = "1220165879f85a1d51656d35b3963a95f3585dc665fc7414f76aa6aad4e6635536cf",
+        },
+    },
+}
diff --git a/nxp-lpc/src/blinky.zig b/nxp-lpc/src/blinky.zig
new file mode 100644
index 000000000..e69de29bb
diff --git a/rp2040/build.zig b/rp2040/build.zig
new file mode 100644
index 000000000..406477261
--- /dev/null
+++ b/rp2040/build.zig
@@ -0,0 +1,84 @@
+const std = @import("std");
+const rp2040 = @import("rp2040");
+const stm32 = @import("stm32");
+const lpc = @import("lpc");
+const gd32 = @import("gd32");
+const nrf5x = @import("nrf5x");
+const esp = @import("esp");
+const atmega = @import("atmega");
+
+pub fn build(b: *std.Build) void {
+    const microzig = @import("microzig").init(b, "microzig");
+    const optimize = b.standardOptimizeOption(.{});
+
+    const TargetDesc = struct {
+        target: @import("microzig").Target,
+        name: []const u8,
+    };
+
+    const available_targets = [_]TargetDesc{
+        // RP2040
+        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
+        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
+        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
+        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
+
+        // STM32
+        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
+        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
+        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
+        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
+        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
+        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
+        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
+        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
+
+        // NXP LPC
+        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
+        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+
+        // GigaDevice GD32
+        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
+        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
+        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
+
+        // Nordic Nrf5x
+        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
+        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
+        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
+
+        // RISC-V Espressif ESP
+        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
+
+        // Microchip ATmega
+        // TODO: Fix compiler bugs
+        // - https://github.com/ziglang/zig/issues/17219
+        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
+        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
+        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
+    };
+
+    for (available_targets) |dest| {
+        // `addFirmware` basically works like addExecutable, but takes a
+        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+        //
+        // The target will convey all necessary information on the chip,
+        // cpu and potentially the board as well.
+        const firmware = microzig.addFirmware(b, .{
+            .name = b.fmt("empty-{s}", .{dest.name}),
+            .target = dest.target,
+            .optimize = optimize,
+            .source_file = .{ .path = "src/empty.zig" },
+        });
+
+        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+        // and allows installing the firmware as a typical firmware file.
+        //
+        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+        microzig.installFirmware(b, firmware, .{});
+
+        // For debugging, we also always install the firmware as an ELF file
+        microzig.installFirmware(b, firmware, .{ .format = .elf });
+    }
+}
diff --git a/rp2040/build.zig.zon b/rp2040/build.zig.zon
new file mode 100644
index 000000000..255be3f0f
--- /dev/null
+++ b/rp2040/build.zig.zon
@@ -0,0 +1,14 @@
+.{
+    .name = "microzig-raspberrypi-rp2040-examples",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
+            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
+        },
+        .rp2040 = .{
+            .url = "https://github.com/ZigEmbeddedGroup/raspberrypi-rp2040/archive/67d36eebb0fbd89633db1a51d6d2bcb049f2066a.tar.gz",
+            .hash = "122094bf268f45b188f3916f9e5964f4257414afaafba98a455ac47d25389a456832",
+        },
+    },
+}
diff --git a/rp2040/scripts/hid_test.py b/rp2040/scripts/hid_test.py
new file mode 100755
index 000000000..ccc2dd093
--- /dev/null
+++ b/rp2040/scripts/hid_test.py
@@ -0,0 +1,29 @@
+#!/usr/bin/env python3
+
+# Install python3 HID package https://pypi.org/project/hid/
+import hid
+
+# default is TinyUSB (0xcafe), Adafruit (0x239a), RaspberryPi (0x2e8a), Espressif (0x303a) VID
+USB_VID = (0xcafe, 0x239a, 0x2e8a, 0x303a)
+
+print("VID list: " + ", ".join('%02x' % v for v in USB_VID))
+
+for vid in  USB_VID:
+    for dict in hid.enumerate(vid):
+        print(dict)
+        dev = hid.Device(dict['vendor_id'], dict['product_id'])
+        if dev:
+            while True:
+                inp = input("Send text to HID Device : ").encode('utf-8')
+                dev.write(inp)
+
+                x = 0
+                l = len(inp)
+                r = b""
+                while (x < l):
+                    str_in = dev.read(64)
+                    r += str_in
+                    x += 64
+
+                print("Received from HID Device:\n", r)
+                print("hex:\n", r.hex())
diff --git a/rp2040/scripts/usb_device_loopback.py b/rp2040/scripts/usb_device_loopback.py
new file mode 100755
index 000000000..82bf47899
--- /dev/null
+++ b/rp2040/scripts/usb_device_loopback.py
@@ -0,0 +1,48 @@
+#!/usr/bin/env python3
+
+#
+# Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+#
+# SPDX-License-Identifier: BSD-3-Clause
+#
+
+# sudo pip3 install pyusb
+
+import usb.core
+import usb.util
+
+# find our device
+dev = usb.core.find(idVendor=0x0000, idProduct=0x0001)
+
+# was it found?
+if dev is None:
+    raise ValueError('Device not found')
+
+# get an endpoint instance
+cfg = dev.get_active_configuration()
+intf = cfg[(0, 0)]
+
+outep = usb.util.find_descriptor(
+    intf,
+    # match the first OUT endpoint
+    custom_match= \
+        lambda e: \
+            usb.util.endpoint_direction(e.bEndpointAddress) == \
+            usb.util.ENDPOINT_OUT)
+
+inep = usb.util.find_descriptor(
+    intf,
+    # match the first IN endpoint
+    custom_match= \
+        lambda e: \
+            usb.util.endpoint_direction(e.bEndpointAddress) == \
+            usb.util.ENDPOINT_IN)
+
+assert inep is not None
+assert outep is not None
+
+test_string = "Hello World!"
+outep.write(test_string)
+from_device = inep.read(len(test_string))
+
+print("Device Says: {}".format(''.join([chr(x) for x in from_device])))
diff --git a/rp2040/src/adc.zig b/rp2040/src/adc.zig
new file mode 100644
index 000000000..ff180dd53
--- /dev/null
+++ b/rp2040/src/adc.zig
@@ -0,0 +1,40 @@
+//! This example takes periodic samples of the temperature sensor and
+//! prints it to the UART using the stdlib logging facility.
+const std = @import("std");
+const microzig = @import("microzig");
+const rp2040 = microzig.hal;
+const gpio = rp2040.gpio;
+const adc = rp2040.adc;
+const time = rp2040.time;
+
+const uart = rp2040.uart.num(0);
+const baud_rate = 115200;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
+
+pub const std_options = struct {
+    pub const logFn = rp2040.uart.log;
+};
+
+pub fn main() void {
+    adc.apply(.{
+        .temp_sensor_enabled = true,
+    });
+
+    uart.apply(.{
+        .baud_rate = baud_rate,
+        .tx_pin = uart_tx_pin,
+        .rx_pin = uart_rx_pin,
+        .clock_config = rp2040.clock_config,
+    });
+
+    rp2040.uart.init_logger(uart);
+    while (true) : (time.sleep_ms(1000)) {
+        const sample = adc.convert_one_shot_blocking(.temp_sensor) catch {
+            std.log.err("conversion failed!", .{});
+            continue;
+        };
+
+        std.log.info("temp value: {}", .{sample});
+    }
+}
diff --git a/rp2040/src/blinky.zig b/rp2040/src/blinky.zig
new file mode 100644
index 000000000..5632fe349
--- /dev/null
+++ b/rp2040/src/blinky.zig
@@ -0,0 +1,20 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const rp2040 = microzig.hal;
+const time = rp2040.time;
+
+const pin_config = rp2040.pins.GlobalConfiguration{
+    .GPIO25 = .{
+        .name = "led",
+        .direction = .out,
+    },
+};
+
+pub fn main() !void {
+    const pins = pin_config.apply();
+
+    while (true) {
+        pins.led.toggle();
+        time.sleep_ms(250);
+    }
+}
diff --git a/rp2040/src/blinky_core1.zig b/rp2040/src/blinky_core1.zig
new file mode 100644
index 000000000..06157295b
--- /dev/null
+++ b/rp2040/src/blinky_core1.zig
@@ -0,0 +1,28 @@
+const std = @import("std");
+
+const microzig = @import("microzig");
+const rp2040 = microzig.hal;
+const gpio = rp2040.gpio;
+const time = rp2040.time;
+const multicore = rp2040.multicore;
+
+const led = gpio.num(25);
+
+fn core1() void {
+    while (true) {
+        led.put(1);
+        time.sleep_ms(250);
+        led.put(0);
+        time.sleep_ms(250);
+    }
+}
+
+pub fn main() !void {
+    led.set_function(.sio);
+    led.set_direction(.out);
+    multicore.launch_core1(core1);
+
+    while (true) {
+        microzig.cpu.wfi();
+    }
+}
diff --git a/rp2040/src/flash_program.zig b/rp2040/src/flash_program.zig
new file mode 100644
index 000000000..9fd13be06
--- /dev/null
+++ b/rp2040/src/flash_program.zig
@@ -0,0 +1,81 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const flash = rp2040.flash;
+const time = rp2040.time;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+
+const led = gpio.num(25);
+const uart = rp2040.uart.num(0);
+const baud_rate = 115200;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
+
+const flash_target_offset: u32 = 256 * 1024;
+const flash_target_contents = @as([*]const u8, @ptrFromInt(rp2040.flash.XIP_BASE + flash_target_offset));
+
+pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
+    std.log.err("panic: {s}", .{message});
+    @breakpoint();
+    while (true) {}
+}
+
+pub const std_options = struct {
+    pub const log_level = .debug;
+    pub const logFn = rp2040.uart.log;
+};
+
+pub fn main() !void {
+    led.set_function(.sio);
+    led.set_direction(.out);
+    led.put(1);
+
+    uart.apply(.{
+        .baud_rate = baud_rate,
+        .tx_pin = uart_tx_pin,
+        .rx_pin = uart_rx_pin,
+        .clock_config = rp2040.clock_config,
+    });
+
+    rp2040.uart.init_logger(uart);
+
+    var data: [flash.PAGE_SIZE]u8 = undefined;
+    var i: usize = 0;
+    var j: u8 = 0;
+    while (i < flash.PAGE_SIZE) : (i += 1) {
+        data[i] = j;
+
+        if (j == 255) j = 0;
+        j += 1;
+    }
+
+    std.log.info("Generate data", .{});
+    std.log.info("data: {s}", .{&data});
+
+    // Note that a whole number of sectors (4096 bytes) must be erased at a time
+    std.log.info("Erasing target region...", .{});
+    flash.range_erase(flash_target_offset, flash.SECTOR_SIZE);
+    std.log.info("Done. Read back target region:", .{});
+    std.log.info("data: {s}", .{flash_target_contents[0..flash.PAGE_SIZE]});
+
+    // Note that a whole number of pages (256 bytes) must be written at a time
+    std.log.info("Programming target region...", .{});
+    flash.range_program(flash_target_offset, data[0..]);
+    std.log.info("Done. Read back target region:", .{});
+    std.log.info("data: {s}", .{flash_target_contents[0..flash.PAGE_SIZE]});
+
+    var mismatch: bool = false;
+    i = 0;
+    while (i < flash.PAGE_SIZE) : (i += 1) {
+        if (data[i] != flash_target_contents[i])
+            mismatch = true;
+    }
+
+    if (mismatch) {
+        std.log.info("Programming failed!", .{});
+    } else {
+        std.log.info("Programming successful!", .{});
+    }
+}
diff --git a/rp2040/src/gpio_clk.zig b/rp2040/src/gpio_clk.zig
new file mode 100644
index 000000000..dd2810242
--- /dev/null
+++ b/rp2040/src/gpio_clk.zig
@@ -0,0 +1,16 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const rp2040 = microzig.hal;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+
+const gpout0_pin = gpio.num(21);
+const clock_config = clocks.GlobalConfiguration.init(.{
+    .sys = .{ .source = .src_xosc },
+    .gpout0 = .{ .source = .clk_sys },
+});
+
+pub fn main() !void {
+    gpout0_pin.set_function(.gpck);
+    while (true) {}
+}
diff --git a/rp2040/src/i2c_bus_scan.zig b/rp2040/src/i2c_bus_scan.zig
new file mode 100644
index 000000000..702bcefc3
--- /dev/null
+++ b/rp2040/src/i2c_bus_scan.zig
@@ -0,0 +1,44 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const i2c = rp2040.i2c;
+const gpio = rp2040.gpio;
+const peripherals = microzig.chip.peripherals;
+
+pub const std_options = struct {
+    pub const log_level = .info;
+    pub const logFn = rp2040.uart.log;
+};
+
+const uart = rp2040.uart.num(0);
+const i2c0 = i2c.num(0);
+
+pub fn main() !void {
+    uart.apply(.{
+        .baud_rate = 115200,
+        .tx_pin = gpio.num(0),
+        .rx_pin = gpio.num(1),
+        .clock_config = rp2040.clock_config,
+    });
+    rp2040.uart.init_logger(uart);
+
+    _ = i2c0.apply(.{
+        .clock_config = rp2040.clock_config,
+        .scl_pin = gpio.num(4),
+        .sda_pin = gpio.num(5),
+    });
+
+    for (0..std.math.maxInt(u7)) |addr| {
+        const a: i2c.Address = @enumFromInt(addr);
+
+        // Skip over any reserved addresses.
+        if (a.is_reserved()) continue;
+
+        var rx_data: [1]u8 = undefined;
+        _ = i2c0.read_blocking(a, &rx_data) catch continue;
+
+        std.log.info("I2C device found at address {X}.", .{addr});
+    }
+}
+
diff --git a/rp2040/src/pwm.zig b/rp2040/src/pwm.zig
new file mode 100644
index 000000000..d372ef4c2
--- /dev/null
+++ b/rp2040/src/pwm.zig
@@ -0,0 +1,23 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const rp2040 = microzig.hal;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+const time = rp2040.time;
+const regs = microzig.chip.registers;
+const multicore = rp2040.multicore;
+
+const pin_config = rp2040.pins.GlobalConfiguration{
+    .GPIO25 = .{ .name = "led", .function = .PWM4_B },
+};
+
+pub fn main() !void {
+    const pins = pin_config.apply();
+    pins.led.slice().set_wrap(100);
+    pins.led.set_level(10);
+    pins.led.slice().enable();
+
+    while (true) {
+        time.sleep_ms(250);
+    }
+}
diff --git a/rp2040/src/random.zig b/rp2040/src/random.zig
new file mode 100644
index 000000000..34d03d1c7
--- /dev/null
+++ b/rp2040/src/random.zig
@@ -0,0 +1,68 @@
+//! Example that generates a 4 byte random number every second and outputs the result over UART
+
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const flash = rp2040.flash;
+const time = rp2040.time;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+const rand = rp2040.rand;
+
+const led = gpio.num(25);
+const uart = rp2040.uart.num(0);
+const baud_rate = 115200;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
+
+pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
+    std.log.err("panic: {s}", .{message});
+    @breakpoint();
+    while (true) {}
+}
+
+pub const std_options = struct {
+    pub const log_level = .debug;
+    pub const logFn = rp2040.uart.log;
+};
+
+pub fn main() !void {
+    led.set_function(.sio);
+    led.set_direction(.out);
+    led.put(1);
+
+    uart.apply(.{
+        .baud_rate = baud_rate,
+        .tx_pin = uart_tx_pin,
+        .rx_pin = uart_rx_pin,
+        .clock_config = rp2040.clock_config,
+    });
+
+    var ascon = rand.Ascon.init();
+    var rng = ascon.random();
+
+    rp2040.uart.init_logger(uart);
+
+    var buffer: [8]u8 = undefined;
+    var dist: [256]usize = .{0} ** 256;
+    var counter: usize = 0;
+
+    while (true) {
+        rng.bytes(buffer[0..]);
+        counter += 8;
+        for (buffer) |byte| {
+            dist[@as(usize, @intCast(byte))] += 1;
+        }
+        std.log.info("Generate random number: {any}", .{buffer});
+
+        if (counter % 256 == 0) {
+            var i: usize = 0;
+            std.log.info("Distribution:", .{});
+            while (i < 256) : (i += 1) {
+                std.log.info("{} -> {}, {d:2}%", .{ i, dist[i], @as(f32, @floatFromInt(dist[i])) / @as(f32, @floatFromInt(counter)) });
+            }
+        }
+        time.sleep_ms(1000);
+    }
+}
diff --git a/rp2040/src/spi_master.zig b/rp2040/src/spi_master.zig
new file mode 100644
index 000000000..c160fee96
--- /dev/null
+++ b/rp2040/src/spi_master.zig
@@ -0,0 +1,26 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const time = rp2040.time;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+const peripherals = microzig.chip.peripherals;
+
+const BUF_LEN = 0x100;
+const spi = rp2040.spi.num(0);
+
+// Communicate with another RP2040 over spi
+// Slave implementation: https://github.com/raspberrypi/pico-examples/blob/master/spi/spi_master_slave/spi_slave/spi_slave.c
+pub fn main() !void {
+    spi.apply(.{
+        .clock_config = rp2040.clock_config,
+    });
+    var out_buf: [BUF_LEN]u8 = .{ 0xAA, 0xBB, 0xCC, 0xDD } ** (BUF_LEN / 4);
+    var in_buf: [BUF_LEN]u8 = undefined;
+
+    while (true) {
+        _ = spi.transceive(&out_buf, &in_buf);
+        time.sleep_ms(1 * 1000);
+    }
+}
diff --git a/rp2040/src/squarewave.zig b/rp2040/src/squarewave.zig
new file mode 100644
index 000000000..0894d9a0c
--- /dev/null
+++ b/rp2040/src/squarewave.zig
@@ -0,0 +1,84 @@
+//! Hello world for the PIO module: generating a square wave
+const std = @import("std");
+const microzig = @import("microzig");
+const rp2040 = microzig.hal;
+const gpio = rp2040.gpio;
+const Pio = rp2040.pio.Pio;
+const StateMachine = rp2040.pio.StateMachine;
+
+const squarewave_program = blk: {
+    @setEvalBranchQuota(2000);
+    break :blk rp2040.pio.assemble(
+        \\;
+        \\; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+        \\;
+        \\; SPDX-License-Identifier: BSD-3-Clause
+        \\;
+        \\.program squarewave
+        \\    set pindirs, 1   ; Set pin to output
+        \\again:
+        \\    set pins, 1 [1]  ; Drive pin high and then delay for one cycle
+        \\    set pins, 0      ; Drive pin low
+        \\    jmp again        ; Set PC to label `again`
+    , .{}).get_program_by_name("squarewave");
+};
+
+// Pick one PIO instance arbitrarily. We're also arbitrarily picking state
+// machine 0 on this PIO instance (the state machines are numbered 0 to 3
+// inclusive).
+const pio: Pio = .pio0;
+const sm: StateMachine = .sm0;
+
+pub fn main() void {
+    pio.gpio_init(gpio.num(2));
+    pio.sm_load_and_start_program(sm, squarewave_program, .{
+        .clkdiv = rp2040.pio.ClkDivOptions.from_float(125),
+        .pin_mappings = .{
+            .set = .{
+                .base = 2,
+                .count = 1,
+            },
+        },
+    }) catch unreachable;
+
+    pio.sm_set_enabled(sm, true);
+
+    while (true) {}
+
+    //// Load the assembled program directly into the PIO's instruction memory.
+    //// Each PIO instance has a 32-slot instruction memory, which all 4 state
+    //// machines can see. The system has write-only access.
+    //for (squarewave_program.instructions, 0..) |insn, i|
+    //    pio.get_instruction_memory()[i] = insn;
+
+    //// Configure state machine 0 to run at sysclk/2.5. The state machines can
+    //// run as fast as one instruction per clock cycle, but we can scale their
+    //// speed down uniformly to meet some precise frequency target, e.g. for a
+    //// UART baud rate. This register has 16 integer divisor bits and 8
+    //// fractional divisor bits.
+    //pio.sm_set_clkdiv(sm, .{
+    //    .int = 2,
+    //    .frac = 0x80,
+    //});
+
+    //// There are five pin mapping groups (out, in, set, side-set, jmp pin)
+    //// which are used by different instructions or in different circumstances.
+    //// Here we're just using SET instructions. Configure state machine 0 SETs
+    //// to affect GPIO 0 only; then configure GPIO0 to be controlled by PIO0,
+    //// as opposed to e.g. the processors.
+    //pio.gpio_init(2);
+    //pio.sm_set_pin_mappings(sm, .{
+    //    .out = .{
+    //        .base = 2,
+    //        .count = 1,
+    //    },
+    //});
+
+    //// Set the state machine running. The PIO CTRL register is global within a
+    //// PIO instance, so you can start/stop multiple state machines
+    //// simultaneously. We're using the register's hardware atomic set alias to
+    //// make one bit high without doing a read-modify-write on the register.
+    //pio.sm_set_enabled(sm, true);
+
+    //while (true) {}
+}
diff --git a/rp2040/src/uart.zig b/rp2040/src/uart.zig
new file mode 100644
index 000000000..914b9ae98
--- /dev/null
+++ b/rp2040/src/uart.zig
@@ -0,0 +1,49 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const time = rp2040.time;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+
+const led = gpio.num(25);
+const uart = rp2040.uart.num(0);
+const baud_rate = 115200;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
+
+pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
+    std.log.err("panic: {s}", .{message});
+    @breakpoint();
+    while (true) {}
+}
+
+pub const std_options = struct {
+    pub const log_level = .debug;
+    pub const logFn = rp2040.uart.log;
+};
+
+pub fn main() !void {
+    led.set_function(.sio);
+    led.set_direction(.out);
+    led.put(1);
+
+    uart.apply(.{
+        .baud_rate = baud_rate,
+        .tx_pin = uart_tx_pin,
+        .rx_pin = uart_rx_pin,
+        .clock_config = rp2040.clock_config,
+    });
+
+    rp2040.uart.init_logger(uart);
+
+    var i: u32 = 0;
+    while (true) : (i += 1) {
+        led.put(1);
+        std.log.info("what {}", .{i});
+        time.sleep_ms(500);
+
+        led.put(0);
+        time.sleep_ms(500);
+    }
+}
diff --git a/rp2040/src/usb_device.zig b/rp2040/src/usb_device.zig
new file mode 100644
index 000000000..8f2d74e4f
--- /dev/null
+++ b/rp2040/src/usb_device.zig
@@ -0,0 +1,172 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const flash = rp2040.flash;
+const time = rp2040.time;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+const usb = rp2040.usb;
+
+const led = gpio.num(25);
+const uart = rp2040.uart.num(0);
+const baud_rate = 115200;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
+
+// First we define two callbacks that will be used by the endpoints we define next...
+fn ep1_in_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
+    _ = data;
+    // The host has collected the data we repeated onto
+    // EP1! Set up to receive more data on EP1.
+    usb.Usb.callbacks.usb_start_rx(
+        dc.endpoints[2], // EP1_OUT_CFG,
+        64,
+    );
+}
+
+fn ep1_out_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
+    // We've gotten data from the host on our custom
+    // EP1! Set up EP1 to repeat it.
+    usb.Usb.callbacks.usb_start_tx(
+        dc.endpoints[3], // EP1_IN_CFG,
+        data,
+    );
+}
+
+// The endpoints EP0_IN and EP0_OUT are already defined but you can
+// add your own endpoints to...
+pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
+    .descriptor = &usb.EndpointDescriptor{
+        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
+        .descriptor_type = usb.DescType.Endpoint,
+        .endpoint_address = usb.Dir.Out.endpoint(1),
+        .attributes = @intFromEnum(usb.TransferType.Bulk),
+        .max_packet_size = 64,
+        .interval = 0,
+    },
+    .endpoint_control_index = 2,
+    .buffer_control_index = 3,
+    .data_buffer_index = 2,
+    .next_pid_1 = false,
+    // The callback will be executed if we got an interrupt on EP1_OUT
+    .callback = ep1_out_callback,
+};
+
+pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
+    .descriptor = &usb.EndpointDescriptor{
+        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
+        .descriptor_type = usb.DescType.Endpoint,
+        .endpoint_address = usb.Dir.In.endpoint(1),
+        .attributes = @intFromEnum(usb.TransferType.Bulk),
+        .max_packet_size = 64,
+        .interval = 0,
+    },
+    .endpoint_control_index = 1,
+    .buffer_control_index = 2,
+    .data_buffer_index = 3,
+    .next_pid_1 = false,
+    // The callback will be executed if we got an interrupt on EP1_IN
+    .callback = ep1_in_callback,
+};
+
+// This is our device configuration
+pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
+    .device_descriptor = &.{
+        .length = @as(u8, @intCast(@sizeOf(usb.DeviceDescriptor))),
+        .descriptor_type = usb.DescType.Device,
+        .bcd_usb = 0x0110,
+        .device_class = 0,
+        .device_subclass = 0,
+        .device_protocol = 0,
+        .max_packet_size0 = 64,
+        .vendor = 0,
+        .product = 1,
+        .bcd_device = 0,
+        .manufacturer_s = 1,
+        .product_s = 2,
+        .serial_s = 0,
+        .num_configurations = 1,
+    },
+    .interface_descriptor = &.{
+        .length = @as(u8, @intCast(@sizeOf(usb.InterfaceDescriptor))),
+        .descriptor_type = usb.DescType.Interface,
+        .interface_number = 0,
+        .alternate_setting = 0,
+        // We have two endpoints (EP0 IN/OUT don't count)
+        .num_endpoints = 2,
+        .interface_class = 0xff,
+        .interface_subclass = 0,
+        .interface_protocol = 0,
+        .interface_s = 0,
+    },
+    .config_descriptor = &.{
+        .length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor))),
+        .descriptor_type = usb.DescType.Config,
+        .total_length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor) + @sizeOf(usb.InterfaceDescriptor) + @sizeOf(usb.EndpointDescriptor) + @sizeOf(usb.EndpointDescriptor))),
+        .num_interfaces = 1,
+        .configuration_value = 1,
+        .configuration_s = 0,
+        .attributes = 0xc0,
+        .max_power = 0x32,
+    },
+    .lang_descriptor = "\x04\x03\x09\x04", // length || string descriptor (0x03) || Engl (0x0409)
+    .descriptor_strings = &.{
+        // ugly unicode :|
+        "R\x00a\x00s\x00p\x00b\x00e\x00r\x00r\x00y\x00 \x00P\x00i\x00",
+        "P\x00i\x00c\x00o\x00 \x00T\x00e\x00s\x00t\x00 \x00D\x00e\x00v\x00i\x00c\x00e\x00",
+    },
+    // Here we pass all endpoints to the config
+    // Dont forget to pass EP0_[IN|OUT] in the order seen below!
+    .endpoints = .{
+        &usb.EP0_OUT_CFG,
+        &usb.EP0_IN_CFG,
+        &EP1_OUT_CFG,
+        &EP1_IN_CFG,
+    },
+};
+
+pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
+    std.log.err("panic: {s}", .{message});
+    @breakpoint();
+    while (true) {}
+}
+
+pub const std_options = struct {
+    pub const log_level = .debug;
+    pub const logFn = rp2040.uart.log;
+};
+
+pub fn main() !void {
+    led.set_function(.sio);
+    led.set_direction(.out);
+    led.put(1);
+
+    uart.apply(.{
+        .baud_rate = baud_rate,
+        .tx_pin = uart_tx_pin,
+        .rx_pin = uart_rx_pin,
+        .clock_config = rp2040.clock_config,
+    });
+
+    rp2040.uart.init_logger(uart);
+
+    // First we initialize the USB clock
+    rp2040.usb.Usb.init_clk();
+    // Then initialize the USB device using the configuration defined above
+    rp2040.usb.Usb.init_device(&DEVICE_CONFIGURATION) catch unreachable;
+    var old: u64 = time.get_time_since_boot().to_us();
+    var new: u64 = 0;
+    while (true) {
+        // You can now poll for USB events
+        rp2040.usb.Usb.task(
+            false, // debug output over UART [Y/n]
+        ) catch unreachable;
+
+        new = time.get_time_since_boot().to_us();
+        if (new - old > 500000) {
+            old = new;
+            led.toggle();
+        }
+    }
+}
diff --git a/rp2040/src/usb_hid.zig b/rp2040/src/usb_hid.zig
new file mode 100644
index 000000000..752111ad0
--- /dev/null
+++ b/rp2040/src/usb_hid.zig
@@ -0,0 +1,187 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const rp2040 = microzig.hal;
+const flash = rp2040.flash;
+const time = rp2040.time;
+const gpio = rp2040.gpio;
+const clocks = rp2040.clocks;
+const usb = rp2040.usb;
+
+const led = gpio.num(25);
+const uart = rp2040.uart.num(0);
+const baud_rate = 115200;
+const uart_tx_pin = gpio.num(0);
+const uart_rx_pin = gpio.num(1);
+
+// First we define two callbacks that will be used by the endpoints we define next...
+fn ep1_in_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
+    _ = data;
+    // The host has collected the data we repeated onto
+    // EP1! Set up to receive more data on EP1.
+    usb.Usb.callbacks.usb_start_rx(
+        dc.endpoints[2], // EP1_OUT_CFG,
+        64,
+    );
+}
+
+fn ep1_out_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
+    // We've gotten data from the host on our custom
+    // EP1! Set up EP1 to repeat it.
+    usb.Usb.callbacks.usb_start_tx(
+        dc.endpoints[3], // EP1_IN_CFG,
+        data,
+    );
+}
+
+// The endpoints EP0_IN and EP0_OUT are already defined but you can
+// add your own endpoints to...
+pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
+    .descriptor = &usb.EndpointDescriptor{
+        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
+        .descriptor_type = usb.DescType.Endpoint,
+        .endpoint_address = usb.Dir.Out.endpoint(1),
+        .attributes = @intFromEnum(usb.TransferType.Interrupt),
+        .max_packet_size = 64,
+        .interval = 0,
+    },
+    .endpoint_control_index = 2,
+    .buffer_control_index = 3,
+    .data_buffer_index = 2,
+    .next_pid_1 = false,
+    // The callback will be executed if we got an interrupt on EP1_OUT
+    .callback = ep1_out_callback,
+};
+
+pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
+    .descriptor = &usb.EndpointDescriptor{
+        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
+        .descriptor_type = usb.DescType.Endpoint,
+        .endpoint_address = usb.Dir.In.endpoint(1),
+        .attributes = @intFromEnum(usb.TransferType.Interrupt),
+        .max_packet_size = 64,
+        .interval = 0,
+    },
+    .endpoint_control_index = 1,
+    .buffer_control_index = 2,
+    .data_buffer_index = 3,
+    .next_pid_1 = false,
+    // The callback will be executed if we got an interrupt on EP1_IN
+    .callback = ep1_in_callback,
+};
+
+// This is our device configuration
+pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
+    .device_descriptor = &.{
+        .length = @as(u8, @intCast(@sizeOf(usb.DeviceDescriptor))),
+        .descriptor_type = usb.DescType.Device,
+        .bcd_usb = 0x0200,
+        .device_class = 0,
+        .device_subclass = 0,
+        .device_protocol = 0,
+        .max_packet_size0 = 64,
+        .vendor = 0xCafe,
+        .product = 1,
+        .bcd_device = 0x0100,
+        // Those are indices to the descriptor strings
+        // Make sure to provide enough string descriptors!
+        .manufacturer_s = 1,
+        .product_s = 2,
+        .serial_s = 3,
+        .num_configurations = 1,
+    },
+    .interface_descriptor = &.{
+        .length = @as(u8, @intCast(@sizeOf(usb.InterfaceDescriptor))),
+        .descriptor_type = usb.DescType.Interface,
+        .interface_number = 0,
+        .alternate_setting = 0,
+        // We have two endpoints (EP0 IN/OUT don't count)
+        .num_endpoints = 2,
+        .interface_class = 3,
+        .interface_subclass = 0,
+        .interface_protocol = 0,
+        .interface_s = 0,
+    },
+    .config_descriptor = &.{
+        .length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor))),
+        .descriptor_type = usb.DescType.Config,
+        .total_length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor) + @sizeOf(usb.InterfaceDescriptor) + @sizeOf(usb.EndpointDescriptor) + @sizeOf(usb.EndpointDescriptor))),
+        .num_interfaces = 1,
+        .configuration_value = 1,
+        .configuration_s = 0,
+        .attributes = 0xc0,
+        .max_power = 0x32,
+    },
+    .lang_descriptor = "\x04\x03\x09\x04", // length || string descriptor (0x03) || Engl (0x0409)
+    .descriptor_strings = &.{
+        // ugly unicode :|
+        //"R\x00a\x00s\x00p\x00b\x00e\x00r\x00r\x00y\x00 \x00P\x00i\x00",
+        &usb.utf8ToUtf16Le("Raspberry Pi"),
+        //"P\x00i\x00c\x00o\x00 \x00T\x00e\x00s\x00t\x00 \x00D\x00e\x00v\x00i\x00c\x00e\x00",
+        &usb.utf8ToUtf16Le("Pico Test Device"),
+        //"c\x00a\x00f\x00e\x00b\x00a\x00b\x00e\x00",
+        &usb.utf8ToUtf16Le("cafebabe"),
+    },
+    .hid = .{
+        .hid_descriptor = &.{
+            .bcd_hid = 0x0111,
+            .country_code = 0,
+            .num_descriptors = 1,
+            .report_length = 34,
+        },
+        .report_descriptor = &usb.hid.ReportDescriptorFidoU2f,
+    },
+    // Here we pass all endpoints to the config
+    // Dont forget to pass EP0_[IN|OUT] in the order seen below!
+    .endpoints = .{
+        &usb.EP0_OUT_CFG,
+        &usb.EP0_IN_CFG,
+        &EP1_OUT_CFG,
+        &EP1_IN_CFG,
+    },
+};
+
+pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
+    std.log.err("panic: {s}", .{message});
+    @breakpoint();
+    while (true) {}
+}
+
+pub const std_options = struct {
+    pub const log_level = .debug;
+    pub const logFn = rp2040.uart.log;
+};
+
+pub fn main() !void {
+    led.set_function(.sio);
+    led.set_direction(.out);
+    led.put(1);
+
+    uart.apply(.{
+        .baud_rate = baud_rate,
+        .tx_pin = uart_tx_pin,
+        .rx_pin = uart_rx_pin,
+        .clock_config = rp2040.clock_config,
+    });
+
+    rp2040.uart.init_logger(uart);
+
+    // First we initialize the USB clock
+    rp2040.usb.Usb.init_clk();
+    // Then initialize the USB device using the configuration defined above
+    rp2040.usb.Usb.init_device(&DEVICE_CONFIGURATION) catch unreachable;
+    var old: u64 = time.get_time_since_boot().to_us();
+    var new: u64 = 0;
+    while (true) {
+        // You can now poll for USB events
+        rp2040.usb.Usb.task(
+            true, // debug output over UART [Y/n]
+        ) catch unreachable;
+
+        new = time.get_time_since_boot().to_us();
+        if (new - old > 500000) {
+            old = new;
+            led.toggle();
+        }
+    }
+}
diff --git a/rp2040/src/ws2812.zig b/rp2040/src/ws2812.zig
new file mode 100644
index 000000000..64fbac225
--- /dev/null
+++ b/rp2040/src/ws2812.zig
@@ -0,0 +1,94 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const rp2040 = microzig.hal;
+const gpio = rp2040.gpio;
+const Pio = rp2040.pio.Pio;
+const StateMachine = rp2040.pio.StateMachine;
+
+const ws2812_program = blk: {
+    @setEvalBranchQuota(5000);
+    break :blk rp2040.pio.assemble(
+        \\;
+        \\; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+        \\;
+        \\; SPDX-License-Identifier: BSD-3-Clause
+        \\;
+        \\.program ws2812
+        \\.side_set 1
+        \\
+        \\.define public T1 2
+        \\.define public T2 5
+        \\.define public T3 3
+        \\
+        \\.wrap_target
+        \\bitloop:
+        \\    out x, 1       side 0 [T3 - 1] ; Side-set still takes place when instruction stalls
+        \\    jmp !x do_zero side 1 [T1 - 1] ; Branch on the bit we shifted out. Positive pulse
+        \\do_one:
+        \\    jmp  bitloop   side 1 [T2 - 1] ; Continue driving high, for a long pulse
+        \\do_zero:
+        \\    nop            side 0 [T2 - 1] ; Or drive low, for a short pulse
+        \\.wrap
+    , .{}).get_program_by_name("ws2812");
+};
+
+const pio: Pio = .pio0;
+const sm: StateMachine = .sm0;
+const led_pin = gpio.num(23);
+
+pub fn main() void {
+    pio.gpio_init(led_pin);
+    sm_set_consecutive_pindirs(pio, sm, @intFromEnum(led_pin), 1, true);
+
+    const cycles_per_bit: comptime_int = ws2812_program.defines[0].value + //T1
+        ws2812_program.defines[1].value + //T2
+        ws2812_program.defines[2].value; //T3
+    const div = @as(f32, @floatFromInt(rp2040.clock_config.sys.?.output_freq)) /
+        (800_000 * cycles_per_bit);
+
+    pio.sm_load_and_start_program(sm, ws2812_program, .{
+        .clkdiv = rp2040.pio.ClkDivOptions.from_float(div),
+        .pin_mappings = .{
+            .side_set = .{
+                .base = @intFromEnum(led_pin),
+                .count = 1,
+            },
+        },
+        .shift = .{
+            .out_shiftdir = .left,
+            .autopull = true,
+            .pull_threshold = 24,
+            .join_tx = true,
+        },
+    }) catch unreachable;
+    pio.sm_set_enabled(sm, true);
+
+    while (true) {
+        pio.sm_blocking_write(sm, 0x00ff00 << 8); //red
+        rp2040.time.sleep_ms(1000);
+        pio.sm_blocking_write(sm, 0xff0000 << 8); //green
+        rp2040.time.sleep_ms(1000);
+        pio.sm_blocking_write(sm, 0x0000ff << 8); //blue
+        rp2040.time.sleep_ms(1000);
+    }
+}
+
+fn sm_set_consecutive_pindirs(_pio: Pio, _sm: StateMachine, pin: u5, count: u3, is_out: bool) void {
+    const sm_regs = _pio.get_sm_regs(_sm);
+    const pinctrl_saved = sm_regs.pinctrl.raw;
+    sm_regs.pinctrl.modify(.{
+        .SET_BASE = pin,
+        .SET_COUNT = count,
+    });
+    _pio.sm_exec(_sm, rp2040.pio.Instruction{
+        .tag = .set,
+        .delay_side_set = 0,
+        .payload = .{
+            .set = .{
+                .data = @intFromBool(is_out),
+                .destination = .pindirs,
+            },
+        },
+    });
+    sm_regs.pinctrl.raw = pinctrl_saved;
+}
diff --git a/shell.nix b/shell.nix
deleted file mode 100644
index b1724c483..000000000
--- a/shell.nix
+++ /dev/null
@@ -1,9 +0,0 @@
-{pkgs ? import  {}}:
-pkgs.mkShell {
-  nativeBuildInputs = [
-    pkgs.zig_0_11_0
-    pkgs.picotool
-    pkgs.llvmPackages_16.bintools
-  ];
-  buildInputs = [];
-}
diff --git a/stmicro-stm32/build.zig b/stmicro-stm32/build.zig
new file mode 100644
index 000000000..406477261
--- /dev/null
+++ b/stmicro-stm32/build.zig
@@ -0,0 +1,84 @@
+const std = @import("std");
+const rp2040 = @import("rp2040");
+const stm32 = @import("stm32");
+const lpc = @import("lpc");
+const gd32 = @import("gd32");
+const nrf5x = @import("nrf5x");
+const esp = @import("esp");
+const atmega = @import("atmega");
+
+pub fn build(b: *std.Build) void {
+    const microzig = @import("microzig").init(b, "microzig");
+    const optimize = b.standardOptimizeOption(.{});
+
+    const TargetDesc = struct {
+        target: @import("microzig").Target,
+        name: []const u8,
+    };
+
+    const available_targets = [_]TargetDesc{
+        // RP2040
+        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
+        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
+        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
+        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
+
+        // STM32
+        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
+        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
+        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
+        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
+        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
+        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
+        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
+        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
+
+        // NXP LPC
+        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
+        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+
+        // GigaDevice GD32
+        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
+        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
+        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
+
+        // Nordic Nrf5x
+        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
+        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
+        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
+
+        // RISC-V Espressif ESP
+        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
+
+        // Microchip ATmega
+        // TODO: Fix compiler bugs
+        // - https://github.com/ziglang/zig/issues/17219
+        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
+        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
+        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
+    };
+
+    for (available_targets) |dest| {
+        // `addFirmware` basically works like addExecutable, but takes a
+        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+        //
+        // The target will convey all necessary information on the chip,
+        // cpu and potentially the board as well.
+        const firmware = microzig.addFirmware(b, .{
+            .name = b.fmt("empty-{s}", .{dest.name}),
+            .target = dest.target,
+            .optimize = optimize,
+            .source_file = .{ .path = "src/empty.zig" },
+        });
+
+        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+        // and allows installing the firmware as a typical firmware file.
+        //
+        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+        microzig.installFirmware(b, firmware, .{});
+
+        // For debugging, we also always install the firmware as an ELF file
+        microzig.installFirmware(b, firmware, .{ .format = .elf });
+    }
+}
diff --git a/stmicro-stm32/build.zig.zon b/stmicro-stm32/build.zig.zon
new file mode 100644
index 000000000..e54d44fbf
--- /dev/null
+++ b/stmicro-stm32/build.zig.zon
@@ -0,0 +1,14 @@
+.{
+    .name = "microzig-stmicro-stm32-examples",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
+            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
+        },
+        .stm32 = .{
+            .url = "https://github.com/ZigEmbeddedGroup/stmicro-stm32/archive/cb2893707efa6aa289fa72f02959ad5f2d9db2a1.tar.gz",
+            .hash = "12208cab5f60ef97cac4165ad694f3ba0c7b28f279538c1539b74f7c152f34fe306d",
+        },
+    },
+}

From c1f553d20335ea1eca135a091a44678249b60210 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 18:20:00 +0200
Subject: [PATCH 214/286] Fixes CI

---
 .github/workflows/build.yml               | 16 ++++++++++++++--
 {generic => all-platforms}/build.zig      |  0
 {generic => all-platforms}/build.zig.zon  |  0
 {generic => all-platforms}/src/blinky.zig |  0
 {generic => all-platforms}/src/empty.zig  |  0
 espressif-esp/{blinky => src}/blinky.zig  |  0
 6 files changed, 14 insertions(+), 2 deletions(-)
 rename {generic => all-platforms}/build.zig (100%)
 rename {generic => all-platforms}/build.zig.zon (100%)
 rename {generic => all-platforms}/src/blinky.zig (100%)
 rename {generic => all-platforms}/src/empty.zig (100%)
 rename espressif-esp/{blinky => src}/blinky.zig (100%)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index ee9f1bb00..ac3fd430b 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -9,9 +9,21 @@ jobs:
   build:
     runs-on: ${{ matrix.os }}
     strategy:
+      fail-fast: false
       matrix:
-        os: [windows-latest, macos-latest, ubuntu-latest]
-        dir: espressif-esp  generic  gigadevice-gd32  microchip-atmega  nordic-nrf5x  nxp-lpc  rp2040  stmicro-stm32
+        os:
+          - windows-latest
+          - macos-latest
+          - ubuntu-latest
+        dir:
+          - all-platforms
+          - espressif-esp
+          - gigadevice-gd32
+          - microchip-atmega
+          - nordic-nrf5x
+          - nxp-lpc
+          - rp2040
+          - stmicro-stm32
     steps:
       - name: Checkout
         uses: actions/checkout@v2
diff --git a/generic/build.zig b/all-platforms/build.zig
similarity index 100%
rename from generic/build.zig
rename to all-platforms/build.zig
diff --git a/generic/build.zig.zon b/all-platforms/build.zig.zon
similarity index 100%
rename from generic/build.zig.zon
rename to all-platforms/build.zig.zon
diff --git a/generic/src/blinky.zig b/all-platforms/src/blinky.zig
similarity index 100%
rename from generic/src/blinky.zig
rename to all-platforms/src/blinky.zig
diff --git a/generic/src/empty.zig b/all-platforms/src/empty.zig
similarity index 100%
rename from generic/src/empty.zig
rename to all-platforms/src/empty.zig
diff --git a/espressif-esp/blinky/blinky.zig b/espressif-esp/src/blinky.zig
similarity index 100%
rename from espressif-esp/blinky/blinky.zig
rename to espressif-esp/src/blinky.zig

From 80a16e10eb2d081beed28dfd3a83c0378100ecab Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 18:28:32 +0200
Subject: [PATCH 215/286] Fixes all-platforms

---
 all-platforms/build.zig.zon | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/all-platforms/build.zig.zon b/all-platforms/build.zig.zon
index fba280d24..5513788d9 100644
--- a/all-platforms/build.zig.zon
+++ b/all-platforms/build.zig.zon
@@ -1,5 +1,5 @@
 .{
-    .name = "microzig-generic-examples",
+    .name = "microzig-all-platforms-examples",
     .version = "0.1.0",
     .dependencies = .{
         .microzig = .{

From def3a61e2839ee04dcc2c411b4eeb0da87903d55 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 18:35:38 +0200
Subject: [PATCH 216/286] Starts to work on raspberrypi-rp2040 examples

---
 .github/workflows/build.yml                   | 18 ++--
 all-platforms/build.zig                       | 88 +++++++++----------
 raspberrypi-rp2040/build.zig                  | 62 +++++++++++++
 {rp2040 => raspberrypi-rp2040}/build.zig.zon  |  0
 .../scripts/hid_test.py                       |  0
 .../scripts/usb_device_loopback.py            |  0
 {rp2040 => raspberrypi-rp2040}/src/adc.zig    |  0
 {rp2040 => raspberrypi-rp2040}/src/blinky.zig |  0
 .../src/blinky_core1.zig                      |  0
 .../src/flash_program.zig                     |  0
 .../src/gpio_clk.zig                          |  0
 .../src/i2c_bus_scan.zig                      |  0
 {rp2040 => raspberrypi-rp2040}/src/pwm.zig    |  0
 {rp2040 => raspberrypi-rp2040}/src/random.zig |  0
 .../src/spi_master.zig                        |  0
 .../src/squarewave.zig                        |  0
 {rp2040 => raspberrypi-rp2040}/src/uart.zig   |  0
 .../src/usb_device.zig                        |  0
 .../src/usb_hid.zig                           |  0
 {rp2040 => raspberrypi-rp2040}/src/ws2812.zig |  0
 rp2040/build.zig                              | 84 ------------------
 21 files changed, 115 insertions(+), 137 deletions(-)
 create mode 100644 raspberrypi-rp2040/build.zig
 rename {rp2040 => raspberrypi-rp2040}/build.zig.zon (100%)
 rename {rp2040 => raspberrypi-rp2040}/scripts/hid_test.py (100%)
 rename {rp2040 => raspberrypi-rp2040}/scripts/usb_device_loopback.py (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/adc.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/blinky.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/blinky_core1.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/flash_program.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/gpio_clk.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/i2c_bus_scan.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/pwm.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/random.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/spi_master.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/squarewave.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/uart.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/usb_device.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/usb_hid.zig (100%)
 rename {rp2040 => raspberrypi-rp2040}/src/ws2812.zig (100%)
 delete mode 100644 rp2040/build.zig

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index ac3fd430b..668835968 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -11,19 +11,19 @@ jobs:
     strategy:
       fail-fast: false
       matrix:
+        dir:
+          - all-platforms
+          - raspberrypi-rp2040
+          # TODO: - espressif-esp
+          # TODO: - gigadevice-gd32
+          # TODO: - microchip-atmega
+          # TODO: - nordic-nrf5x
+          # TODO: - nxp-lpc
+          # TODO: - stmicro-stm32
         os:
           - windows-latest
           - macos-latest
           - ubuntu-latest
-        dir:
-          - all-platforms
-          - espressif-esp
-          - gigadevice-gd32
-          - microchip-atmega
-          - nordic-nrf5x
-          - nxp-lpc
-          - rp2040
-          - stmicro-stm32
     steps:
       - name: Checkout
         uses: actions/checkout@v2
diff --git a/all-platforms/build.zig b/all-platforms/build.zig
index 406477261..6cf3b48ad 100644
--- a/all-platforms/build.zig
+++ b/all-platforms/build.zig
@@ -7,57 +7,52 @@ const nrf5x = @import("nrf5x");
 const esp = @import("esp");
 const atmega = @import("atmega");
 
-pub fn build(b: *std.Build) void {
-    const microzig = @import("microzig").init(b, "microzig");
-    const optimize = b.standardOptimizeOption(.{});
-
-    const TargetDesc = struct {
-        target: @import("microzig").Target,
-        name: []const u8,
-    };
+const available_targets = [_]TargetDesc{
+    // RP2040
+    .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
+    .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
+    .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
+    .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+    .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
 
-    const available_targets = [_]TargetDesc{
-        // RP2040
-        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
-        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
-        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
-        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
-        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
+    // STM32
+    .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
+    .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
+    .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
+    .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
+    .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
+    .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
+    .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
+    .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
 
-        // STM32
-        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
-        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
-        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
-        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
-        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
-        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
-        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
-        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
+    // NXP LPC
+    .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
+    .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
 
-        // NXP LPC
-        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
-        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+    // GigaDevice GD32
+    .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
+    .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
+    .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
 
-        // GigaDevice GD32
-        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
-        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
-        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
+    // Nordic Nrf5x
+    .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
+    .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
+    .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
 
-        // Nordic Nrf5x
-        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
-        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
-        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
+    // RISC-V Espressif ESP
+    .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
 
-        // RISC-V Espressif ESP
-        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
+    // Microchip ATmega
+    // TODO: Fix compiler bugs
+    // - https://github.com/ziglang/zig/issues/17219
+    // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
+    // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
+    // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
+};
 
-        // Microchip ATmega
-        // TODO: Fix compiler bugs
-        // - https://github.com/ziglang/zig/issues/17219
-        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
-        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
-        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
-    };
+pub fn build(b: *std.Build) void {
+    const microzig = @import("microzig").init(b, "microzig");
+    const optimize = b.standardOptimizeOption(.{});
 
     for (available_targets) |dest| {
         // `addFirmware` basically works like addExecutable, but takes a
@@ -82,3 +77,8 @@ pub fn build(b: *std.Build) void {
         microzig.installFirmware(b, firmware, .{ .format = .elf });
     }
 }
+
+const TargetDesc = struct {
+    target: @import("microzig").Target,
+    name: []const u8,
+};
diff --git a/raspberrypi-rp2040/build.zig b/raspberrypi-rp2040/build.zig
new file mode 100644
index 000000000..c5845720c
--- /dev/null
+++ b/raspberrypi-rp2040/build.zig
@@ -0,0 +1,62 @@
+const std = @import("std");
+const rp2040 = @import("rp2040");
+
+const available_targets = [_]TargetDesc{
+    .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
+    .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
+    .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
+    .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+    .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
+};
+
+const available_examples = [_][]const u8{
+    "src/adc.zig",
+    "src/blinky.zig",
+    "src/blinky_core1.zig",
+    "src/flash_program.zig",
+    "src/gpio_clk.zig",
+    "src/i2c_bus_scan.zig",
+    "src/pwm.zig",
+    "src/random.zig",
+    "src/spi_master.zig",
+    "src/squarewave.zig",
+    "src/uart.zig",
+    "src/usb_device.zig",
+    "src/usb_hid.zig",
+    "src/ws2812.zig",
+};
+
+pub fn build(b: *std.Build) void {
+    const microzig = @import("microzig").init(b, "microzig");
+    const optimize = b.standardOptimizeOption(.{});
+
+    for (available_targets) |target| {
+        for (available_examples) |example| {
+            // `addFirmware` basically works like addExecutable, but takes a
+            // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+            //
+            // The target will convey all necessary information on the chip,
+            // cpu and potentially the board as well.
+            const firmware = microzig.addFirmware(b, .{
+                .name = b.fmt("{s}-{s}", .{ std.fs.path.stem(example), target.name }),
+                .target = target.target,
+                .optimize = optimize,
+                .source_file = .{ .path = example },
+            });
+
+            // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+            // and allows installing the firmware as a typical firmware file.
+            //
+            // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+            microzig.installFirmware(b, firmware, .{});
+
+            // For debugging, we also always install the firmware as an ELF file
+            microzig.installFirmware(b, firmware, .{ .format = .elf });
+        }
+    }
+}
+
+const TargetDesc = struct {
+    target: @import("microzig").Target,
+    name: []const u8,
+};
diff --git a/rp2040/build.zig.zon b/raspberrypi-rp2040/build.zig.zon
similarity index 100%
rename from rp2040/build.zig.zon
rename to raspberrypi-rp2040/build.zig.zon
diff --git a/rp2040/scripts/hid_test.py b/raspberrypi-rp2040/scripts/hid_test.py
similarity index 100%
rename from rp2040/scripts/hid_test.py
rename to raspberrypi-rp2040/scripts/hid_test.py
diff --git a/rp2040/scripts/usb_device_loopback.py b/raspberrypi-rp2040/scripts/usb_device_loopback.py
similarity index 100%
rename from rp2040/scripts/usb_device_loopback.py
rename to raspberrypi-rp2040/scripts/usb_device_loopback.py
diff --git a/rp2040/src/adc.zig b/raspberrypi-rp2040/src/adc.zig
similarity index 100%
rename from rp2040/src/adc.zig
rename to raspberrypi-rp2040/src/adc.zig
diff --git a/rp2040/src/blinky.zig b/raspberrypi-rp2040/src/blinky.zig
similarity index 100%
rename from rp2040/src/blinky.zig
rename to raspberrypi-rp2040/src/blinky.zig
diff --git a/rp2040/src/blinky_core1.zig b/raspberrypi-rp2040/src/blinky_core1.zig
similarity index 100%
rename from rp2040/src/blinky_core1.zig
rename to raspberrypi-rp2040/src/blinky_core1.zig
diff --git a/rp2040/src/flash_program.zig b/raspberrypi-rp2040/src/flash_program.zig
similarity index 100%
rename from rp2040/src/flash_program.zig
rename to raspberrypi-rp2040/src/flash_program.zig
diff --git a/rp2040/src/gpio_clk.zig b/raspberrypi-rp2040/src/gpio_clk.zig
similarity index 100%
rename from rp2040/src/gpio_clk.zig
rename to raspberrypi-rp2040/src/gpio_clk.zig
diff --git a/rp2040/src/i2c_bus_scan.zig b/raspberrypi-rp2040/src/i2c_bus_scan.zig
similarity index 100%
rename from rp2040/src/i2c_bus_scan.zig
rename to raspberrypi-rp2040/src/i2c_bus_scan.zig
diff --git a/rp2040/src/pwm.zig b/raspberrypi-rp2040/src/pwm.zig
similarity index 100%
rename from rp2040/src/pwm.zig
rename to raspberrypi-rp2040/src/pwm.zig
diff --git a/rp2040/src/random.zig b/raspberrypi-rp2040/src/random.zig
similarity index 100%
rename from rp2040/src/random.zig
rename to raspberrypi-rp2040/src/random.zig
diff --git a/rp2040/src/spi_master.zig b/raspberrypi-rp2040/src/spi_master.zig
similarity index 100%
rename from rp2040/src/spi_master.zig
rename to raspberrypi-rp2040/src/spi_master.zig
diff --git a/rp2040/src/squarewave.zig b/raspberrypi-rp2040/src/squarewave.zig
similarity index 100%
rename from rp2040/src/squarewave.zig
rename to raspberrypi-rp2040/src/squarewave.zig
diff --git a/rp2040/src/uart.zig b/raspberrypi-rp2040/src/uart.zig
similarity index 100%
rename from rp2040/src/uart.zig
rename to raspberrypi-rp2040/src/uart.zig
diff --git a/rp2040/src/usb_device.zig b/raspberrypi-rp2040/src/usb_device.zig
similarity index 100%
rename from rp2040/src/usb_device.zig
rename to raspberrypi-rp2040/src/usb_device.zig
diff --git a/rp2040/src/usb_hid.zig b/raspberrypi-rp2040/src/usb_hid.zig
similarity index 100%
rename from rp2040/src/usb_hid.zig
rename to raspberrypi-rp2040/src/usb_hid.zig
diff --git a/rp2040/src/ws2812.zig b/raspberrypi-rp2040/src/ws2812.zig
similarity index 100%
rename from rp2040/src/ws2812.zig
rename to raspberrypi-rp2040/src/ws2812.zig
diff --git a/rp2040/build.zig b/rp2040/build.zig
deleted file mode 100644
index 406477261..000000000
--- a/rp2040/build.zig
+++ /dev/null
@@ -1,84 +0,0 @@
-const std = @import("std");
-const rp2040 = @import("rp2040");
-const stm32 = @import("stm32");
-const lpc = @import("lpc");
-const gd32 = @import("gd32");
-const nrf5x = @import("nrf5x");
-const esp = @import("esp");
-const atmega = @import("atmega");
-
-pub fn build(b: *std.Build) void {
-    const microzig = @import("microzig").init(b, "microzig");
-    const optimize = b.standardOptimizeOption(.{});
-
-    const TargetDesc = struct {
-        target: @import("microzig").Target,
-        name: []const u8,
-    };
-
-    const available_targets = [_]TargetDesc{
-        // RP2040
-        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
-        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
-        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
-        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
-        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
-
-        // STM32
-        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
-        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
-        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
-        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
-        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
-        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
-        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
-        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
-
-        // NXP LPC
-        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
-        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
-
-        // GigaDevice GD32
-        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
-        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
-        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
-
-        // Nordic Nrf5x
-        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
-        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
-        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
-
-        // RISC-V Espressif ESP
-        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
-
-        // Microchip ATmega
-        // TODO: Fix compiler bugs
-        // - https://github.com/ziglang/zig/issues/17219
-        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
-        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
-        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
-    };
-
-    for (available_targets) |dest| {
-        // `addFirmware` basically works like addExecutable, but takes a
-        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
-        //
-        // The target will convey all necessary information on the chip,
-        // cpu and potentially the board as well.
-        const firmware = microzig.addFirmware(b, .{
-            .name = b.fmt("empty-{s}", .{dest.name}),
-            .target = dest.target,
-            .optimize = optimize,
-            .source_file = .{ .path = "src/empty.zig" },
-        });
-
-        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
-        // and allows installing the firmware as a typical firmware file.
-        //
-        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
-        microzig.installFirmware(b, firmware, .{});
-
-        // For debugging, we also always install the firmware as an ELF file
-        microzig.installFirmware(b, firmware, .{ .format = .elf });
-    }
-}

From cc2b97de4603e754686bf21c52c666bdf8916682 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 18:36:30 +0200
Subject: [PATCH 217/286] Disables flaky example

---
 raspberrypi-rp2040/build.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/raspberrypi-rp2040/build.zig b/raspberrypi-rp2040/build.zig
index c5845720c..dea02c5e4 100644
--- a/raspberrypi-rp2040/build.zig
+++ b/raspberrypi-rp2040/build.zig
@@ -12,7 +12,7 @@ const available_targets = [_]TargetDesc{
 const available_examples = [_][]const u8{
     "src/adc.zig",
     "src/blinky.zig",
-    "src/blinky_core1.zig",
+    // TODO: Fix multicore hal! "src/blinky_core1.zig",
     "src/flash_program.zig",
     "src/gpio_clk.zig",
     "src/i2c_bus_scan.zig",

From 11b5bef01a31eff31205f7fe0e8d7e01870a55ef Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 18:43:06 +0200
Subject: [PATCH 218/286] enables espressif-esp examples

---
 .github/workflows/build.yml |   2 +-
 espressif-esp/build.zig     | 111 ++++++++++++------------------------
 2 files changed, 37 insertions(+), 76 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 668835968..9f6738efc 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -14,7 +14,7 @@ jobs:
         dir:
           - all-platforms
           - raspberrypi-rp2040
-          # TODO: - espressif-esp
+          - espressif-esp
           # TODO: - gigadevice-gd32
           # TODO: - microchip-atmega
           # TODO: - nordic-nrf5x
diff --git a/espressif-esp/build.zig b/espressif-esp/build.zig
index 406477261..08dcceeb0 100644
--- a/espressif-esp/build.zig
+++ b/espressif-esp/build.zig
@@ -1,84 +1,45 @@
 const std = @import("std");
-const rp2040 = @import("rp2040");
-const stm32 = @import("stm32");
-const lpc = @import("lpc");
-const gd32 = @import("gd32");
-const nrf5x = @import("nrf5x");
 const esp = @import("esp");
-const atmega = @import("atmega");
+
+const available_targets = [_]TargetDesc{
+    .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 },
+};
+
+const available_examples = [_][]const u8{
+    "src/blinky.zig",
+};
 
 pub fn build(b: *std.Build) void {
     const microzig = @import("microzig").init(b, "microzig");
     const optimize = b.standardOptimizeOption(.{});
 
-    const TargetDesc = struct {
-        target: @import("microzig").Target,
-        name: []const u8,
-    };
-
-    const available_targets = [_]TargetDesc{
-        // RP2040
-        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
-        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
-        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
-        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
-        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
-
-        // STM32
-        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
-        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
-        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
-        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
-        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
-        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
-        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
-        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
-
-        // NXP LPC
-        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
-        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
-
-        // GigaDevice GD32
-        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
-        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
-        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
-
-        // Nordic Nrf5x
-        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
-        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
-        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
-
-        // RISC-V Espressif ESP
-        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
-
-        // Microchip ATmega
-        // TODO: Fix compiler bugs
-        // - https://github.com/ziglang/zig/issues/17219
-        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
-        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
-        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
-    };
-
-    for (available_targets) |dest| {
-        // `addFirmware` basically works like addExecutable, but takes a
-        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
-        //
-        // The target will convey all necessary information on the chip,
-        // cpu and potentially the board as well.
-        const firmware = microzig.addFirmware(b, .{
-            .name = b.fmt("empty-{s}", .{dest.name}),
-            .target = dest.target,
-            .optimize = optimize,
-            .source_file = .{ .path = "src/empty.zig" },
-        });
-
-        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
-        // and allows installing the firmware as a typical firmware file.
-        //
-        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
-        microzig.installFirmware(b, firmware, .{});
-
-        // For debugging, we also always install the firmware as an ELF file
-        microzig.installFirmware(b, firmware, .{ .format = .elf });
+    for (available_targets) |target| {
+        for (available_examples) |example| {
+            // `addFirmware` basically works like addExecutable, but takes a
+            // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+            //
+            // The target will convey all necessary information on the chip,
+            // cpu and potentially the board as well.
+            const firmware = microzig.addFirmware(b, .{
+                .name = b.fmt("{s}-{s}", .{ std.fs.path.stem(example), target.name }),
+                .target = target.target,
+                .optimize = optimize,
+                .source_file = .{ .path = example },
+            });
+
+            // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+            // and allows installing the firmware as a typical firmware file.
+            //
+            // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+            microzig.installFirmware(b, firmware, .{});
+
+            // For debugging, we also always install the firmware as an ELF file
+            microzig.installFirmware(b, firmware, .{ .format = .elf });
+        }
     }
 }
+
+const TargetDesc = struct {
+    target: @import("microzig").Target,
+    name: []const u8,
+};

From 38793077e87e97716c1807728eec190d2f1ab768 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 20:13:15 +0200
Subject: [PATCH 219/286] Implements blinky for mbed LPC1768

---
 .github/workflows/build.yml |  2 +-
 nxp-lpc/README.md           |  4 +++
 nxp-lpc/build.zig           | 72 ++++++++-----------------------------
 nxp-lpc/src/blinky.zig      | 56 +++++++++++++++++++++++++++++
 4 files changed, 75 insertions(+), 59 deletions(-)
 create mode 100644 nxp-lpc/README.md

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 9f6738efc..2805e5313 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -15,10 +15,10 @@ jobs:
           - all-platforms
           - raspberrypi-rp2040
           - espressif-esp
+          - nxp-lpc
           # TODO: - gigadevice-gd32
           # TODO: - microchip-atmega
           # TODO: - nordic-nrf5x
-          # TODO: - nxp-lpc
           # TODO: - stmicro-stm32
         os:
           - windows-latest
diff --git a/nxp-lpc/README.md b/nxp-lpc/README.md
new file mode 100644
index 000000000..7bc74a7b4
--- /dev/null
+++ b/nxp-lpc/README.md
@@ -0,0 +1,4 @@
+# Examples for the BSP `nxp-lpc`
+
+- [Blinky](src/blinky.zig) on [mbed LPC1768](https://os.mbed.com/platforms/mbed-LPC1768/)  
+  Performs a really basic round robin blinky on the four LEDs on the development board. Flash by copying `zig-out/firmware/mbed-lpc1768_blinky.hex` to the mass storage of the board, then press the big button in the center.
diff --git a/nxp-lpc/build.zig b/nxp-lpc/build.zig
index 406477261..a6f0b305f 100644
--- a/nxp-lpc/build.zig
+++ b/nxp-lpc/build.zig
@@ -1,75 +1,25 @@
 const std = @import("std");
-const rp2040 = @import("rp2040");
-const stm32 = @import("stm32");
 const lpc = @import("lpc");
-const gd32 = @import("gd32");
-const nrf5x = @import("nrf5x");
-const esp = @import("esp");
-const atmega = @import("atmega");
+
+const available_examples = [_]ExampleDesc{
+    .{ .name = "mbed-lpc1768_blinky", .target = lpc.boards.mbed.lpc1768, .file = "src/blinky.zig" },
+};
 
 pub fn build(b: *std.Build) void {
     const microzig = @import("microzig").init(b, "microzig");
     const optimize = b.standardOptimizeOption(.{});
 
-    const TargetDesc = struct {
-        target: @import("microzig").Target,
-        name: []const u8,
-    };
-
-    const available_targets = [_]TargetDesc{
-        // RP2040
-        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
-        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
-        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
-        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
-        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
-
-        // STM32
-        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
-        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
-        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
-        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
-        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
-        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
-        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
-        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
-
-        // NXP LPC
-        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
-        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
-
-        // GigaDevice GD32
-        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
-        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
-        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
-
-        // Nordic Nrf5x
-        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
-        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
-        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
-
-        // RISC-V Espressif ESP
-        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
-
-        // Microchip ATmega
-        // TODO: Fix compiler bugs
-        // - https://github.com/ziglang/zig/issues/17219
-        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
-        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
-        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
-    };
-
-    for (available_targets) |dest| {
+    for (available_examples) |example| {
         // `addFirmware` basically works like addExecutable, but takes a
         // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
         //
         // The target will convey all necessary information on the chip,
         // cpu and potentially the board as well.
         const firmware = microzig.addFirmware(b, .{
-            .name = b.fmt("empty-{s}", .{dest.name}),
-            .target = dest.target,
+            .name = example.name,
+            .target = example.target,
             .optimize = optimize,
-            .source_file = .{ .path = "src/empty.zig" },
+            .source_file = .{ .path = example.file },
         });
 
         // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
@@ -82,3 +32,9 @@ pub fn build(b: *std.Build) void {
         microzig.installFirmware(b, firmware, .{ .format = .elf });
     }
 }
+
+const ExampleDesc = struct {
+    target: @import("microzig").Target,
+    name: []const u8,
+    file: []const u8,
+};
diff --git a/nxp-lpc/src/blinky.zig b/nxp-lpc/src/blinky.zig
index e69de29bb..328d63705 100644
--- a/nxp-lpc/src/blinky.zig
+++ b/nxp-lpc/src/blinky.zig
@@ -0,0 +1,56 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const chip = microzig.chip;
+
+// LED-1: P1.18
+// LED-2: P1.20
+// LED-3: P1.21
+// LED-4: P1.23
+
+const conn = chip.peripherals.PINCONNECT;
+const gpio: *volatile [5]PatchedGpio = @ptrCast(@alignCast(chip.peripherals.GPIO));
+
+const led_mask = [4]u32{
+    (1 << 18),
+    (1 << 20),
+    (1 << 21),
+    (1 << 23),
+};
+const all_mask = led_mask[0] | led_mask[1] | led_mask[2] | led_mask[3];
+
+pub fn main() !void {
+    conn.PINSEL3.modify(.{
+        .P1_18 = .{ .value = .GPIO_P1 },
+        .P1_20 = .{ .value = .GPIO_P1 },
+        .P1_21 = .{ .value = .GPIO_P1 },
+        .P1_23 = .{ .value = .GPIO_P1 },
+    });
+
+    const p1 = &gpio[1];
+
+    p1.dir = all_mask;
+
+    while (true) {
+        for (led_mask) |mask| {
+            p1.pin_clr = (all_mask & ~mask);
+            p1.pin_set = mask;
+            microzig.core.experimental.debug.busy_sleep(100_000);
+        }
+    }
+}
+
+const PatchedGpio = extern struct {
+    dir: u32, // 0x2009 C000
+    __padding0: u32, // 0x2009 C004
+    __padding1: u32, // 0x2009 C008
+    __padding2: u32, // 0x2009 C00C
+    mask: u32, // 0x2009 C010
+    pin: u32, // 0x2009 C014
+    pin_set: u32, // 0x2009 C018
+    pin_clr: u32, // 0x2009 C01C
+
+    comptime {
+        std.debug.assert(@sizeOf(PatchedGpio) == 0x20);
+    }
+};

From fac4648f5c2bb3684c701737cc4830f02bc72a48 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 20:35:14 +0200
Subject: [PATCH 220/286] Updates raspberrypi-pico example readme.

---
 raspberrypi-rp2040/README.md   | 31 +++++++++++++
 raspberrypi-rp2040/build.zig   | 84 ++++++++++++++++------------------
 raspberrypi-rp2040/src/pwm.zig | 10 +++-
 3 files changed, 79 insertions(+), 46 deletions(-)
 create mode 100644 raspberrypi-rp2040/README.md

diff --git a/raspberrypi-rp2040/README.md b/raspberrypi-rp2040/README.md
new file mode 100644
index 000000000..dbb4e7294
--- /dev/null
+++ b/raspberrypi-rp2040/README.md
@@ -0,0 +1,31 @@
+# Examples for the BSP `raspberrypi-rp2040`
+
+- [adc](src/adc.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  This example takes periodic samples of the temperature sensor and prints it to the UART using the stdlib logging facility.
+- [blinky](src/blinky.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  Blinks the LED on the board.
+- [blinky core1](src/blinky_core1.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  Blinks the LED on the board using the second CPU.
+- [flash program](src/flash_program.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  Writes and reads data into the flash.
+- [gpio clk](src/gpio_clk.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  Enables a `CLKOUT` mode on GPIO0.
+- [i2c bus scan](src/i2c_bus_scan.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  Prints all I²C devices on UART0 (Pin 0,1) attached to I²C on SCL=GPIO4, SDA=GPIO5.
+- [pwm](src/pwm.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  Slowly blinks the LED on the Pico with a smooth blinking using PWM.
+- [random](src/random.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  Showcases how to use the internal random generator.
+- [spi master](src/spi_master.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  Showcases how to use the SPI host controller.
+- [squarewave](src/squarewave.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  Showcases how to use the PIO to emit a basic square wave.
+- [uart](src/uart.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  Showcases how to use the UART together with `std.log`.
+- [usb device](src/usb_device.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  A really basic example for a raw USB device. You can use the Python 3 script [`scripts/usb_device_loopback.py`](scripts/usb_device_loopback.py) to test the USB device.
+- [usb hid](src/usb_hid.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  A really basic example how to implement a USB HID device. You can use the Python 3 script [`scripts/hid_test.py`](scripts/hid_test.py) to test the HID device.
+- [ws2812](src/ws2812.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
+  Showcases how to control one WS2812 LED attached to GPIO23.
+
diff --git a/raspberrypi-rp2040/build.zig b/raspberrypi-rp2040/build.zig
index dea02c5e4..1128c6990 100644
--- a/raspberrypi-rp2040/build.zig
+++ b/raspberrypi-rp2040/build.zig
@@ -1,62 +1,58 @@
 const std = @import("std");
 const rp2040 = @import("rp2040");
 
-const available_targets = [_]TargetDesc{
-    .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
-    .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
-    .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
-    .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
-    .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
-};
+const available_examples = [_]Example{
+    .{ .name = "pico_adc", .target = rp2040.boards.raspberry_pi.pico, .file = "src/adc.zig" },
+    .{ .name = "pico_blinky", .target = rp2040.boards.raspberry_pi.pico, .file = "src/blinky.zig" },
+    // TODO: Fix multicore hal! .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico , .file = "src/blinky_core1.zig" },
+    .{ .name = "pico_flash-program", .target = rp2040.boards.raspberry_pi.pico, .file = "src/flash_program.zig" },
+    .{ .name = "pico_gpio-clk", .target = rp2040.boards.raspberry_pi.pico, .file = "src/gpio_clk.zig" },
+    .{ .name = "pico_i2c-bus-scan", .target = rp2040.boards.raspberry_pi.pico, .file = "src/i2c_bus_scan.zig" },
+    .{ .name = "pico_pwm", .target = rp2040.boards.raspberry_pi.pico, .file = "src/pwm.zig" },
+    .{ .name = "pico_random", .target = rp2040.boards.raspberry_pi.pico, .file = "src/random.zig" },
+    .{ .name = "pico_spi-master", .target = rp2040.boards.raspberry_pi.pico, .file = "src/spi_master.zig" },
+    .{ .name = "pico_squarewave", .target = rp2040.boards.raspberry_pi.pico, .file = "src/squarewave.zig" },
+    .{ .name = "pico_uart", .target = rp2040.boards.raspberry_pi.pico, .file = "src/uart.zig" },
+    .{ .name = "pico_usb-device", .target = rp2040.boards.raspberry_pi.pico, .file = "src/usb_device.zig" },
+    .{ .name = "pico_usb-hid", .target = rp2040.boards.raspberry_pi.pico, .file = "src/usb_hid.zig" },
+    .{ .name = "pico_ws2812", .target = rp2040.boards.raspberry_pi.pico, .file = "src/ws2812.zig" },
 
-const available_examples = [_][]const u8{
-    "src/adc.zig",
-    "src/blinky.zig",
-    // TODO: Fix multicore hal! "src/blinky_core1.zig",
-    "src/flash_program.zig",
-    "src/gpio_clk.zig",
-    "src/i2c_bus_scan.zig",
-    "src/pwm.zig",
-    "src/random.zig",
-    "src/spi_master.zig",
-    "src/squarewave.zig",
-    "src/uart.zig",
-    "src/usb_device.zig",
-    "src/usb_hid.zig",
-    "src/ws2812.zig",
+    //     .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
+    //     .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
+    //     .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+    //     .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
 };
 
 pub fn build(b: *std.Build) void {
     const microzig = @import("microzig").init(b, "microzig");
     const optimize = b.standardOptimizeOption(.{});
 
-    for (available_targets) |target| {
-        for (available_examples) |example| {
-            // `addFirmware` basically works like addExecutable, but takes a
-            // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
-            //
-            // The target will convey all necessary information on the chip,
-            // cpu and potentially the board as well.
-            const firmware = microzig.addFirmware(b, .{
-                .name = b.fmt("{s}-{s}", .{ std.fs.path.stem(example), target.name }),
-                .target = target.target,
-                .optimize = optimize,
-                .source_file = .{ .path = example },
-            });
+    for (available_examples) |example| {
+        // `addFirmware` basically works like addExecutable, but takes a
+        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+        //
+        // The target will convey all necessary information on the chip,
+        // cpu and potentially the board as well.
+        const firmware = microzig.addFirmware(b, .{
+            .name = example.name,
+            .target = example.target,
+            .optimize = optimize,
+            .source_file = .{ .path = example.file },
+        });
 
-            // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
-            // and allows installing the firmware as a typical firmware file.
-            //
-            // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
-            microzig.installFirmware(b, firmware, .{});
+        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+        // and allows installing the firmware as a typical firmware file.
+        //
+        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+        microzig.installFirmware(b, firmware, .{});
 
-            // For debugging, we also always install the firmware as an ELF file
-            microzig.installFirmware(b, firmware, .{ .format = .elf });
-        }
+        // For debugging, we also always install the firmware as an ELF file
+        microzig.installFirmware(b, firmware, .{ .format = .elf });
     }
 }
 
-const TargetDesc = struct {
+const Example = struct {
     target: @import("microzig").Target,
     name: []const u8,
+    file: []const u8,
 };
diff --git a/raspberrypi-rp2040/src/pwm.zig b/raspberrypi-rp2040/src/pwm.zig
index d372ef4c2..523c91f9a 100644
--- a/raspberrypi-rp2040/src/pwm.zig
+++ b/raspberrypi-rp2040/src/pwm.zig
@@ -14,10 +14,16 @@ const pin_config = rp2040.pins.GlobalConfiguration{
 pub fn main() !void {
     const pins = pin_config.apply();
     pins.led.slice().set_wrap(100);
-    pins.led.set_level(10);
     pins.led.slice().enable();
 
     while (true) {
-        time.sleep_ms(250);
+        for (0..101) |level| {
+            pins.led.set_level(@truncate(level));
+            time.sleep_ms(10);
+        }
+        for (1..100) |level| {
+            pins.led.set_level(@truncate(100 - level));
+            time.sleep_ms(10);
+        }
     }
 }

From 71e59a4f7d9eabb5cd7085483120aa599e77effa Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 20:47:49 +0200
Subject: [PATCH 221/286] Adds tiles example.

---
 raspberrypi-rp2040/README.md     |  19 ++++
 raspberrypi-rp2040/build.zig     |   3 +-
 raspberrypi-rp2040/src/tiles.zig | 147 +++++++++++++++++++++++++++++++
 3 files changed, 168 insertions(+), 1 deletion(-)
 create mode 100644 raspberrypi-rp2040/src/tiles.zig

diff --git a/raspberrypi-rp2040/README.md b/raspberrypi-rp2040/README.md
index dbb4e7294..e5c829372 100644
--- a/raspberrypi-rp2040/README.md
+++ b/raspberrypi-rp2040/README.md
@@ -1,5 +1,9 @@
 # Examples for the BSP `raspberrypi-rp2040`
 
+## Demos
+
+All demos that run on the [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/) can also be run on the [RP2040-Plus](https://www.waveshare.com/rp2040-plus.htm) without modification.
+
 - [adc](src/adc.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
   This example takes periodic samples of the temperature sensor and prints it to the UART using the stdlib logging facility.
 - [blinky](src/blinky.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
@@ -28,4 +32,19 @@
   A really basic example how to implement a USB HID device. You can use the Python 3 script [`scripts/hid_test.py`](scripts/hid_test.py) to test the HID device.
 - [ws2812](src/ws2812.zig) on [RaspberryPi Pico](https://www.raspberrypi.com/products/raspberry-pi-pico/)  
   Showcases how to control one WS2812 LED attached to GPIO23.
+- [tiles](src/tiles.zig) on [RP2040-Matrix](https://www.waveshare.com/rp2040-matrix.htm)  
+  Showcases how to control the LED matrix on the development board to do a simple color flipper effect.
+
+## Flashing
+
+You can flash all examples using either your file browser by dragging the example `.uf2` file from `zig-out/firmware/` to the directory.
+
+Or you can use [`picotool`](https://github.com/raspberrypi/picotool) to flash a uf2 file:
+```sh-session
+[user@host] raspberrypi-rp2040/ $ picotool load -x zig-out/firmware/${file}.uf2
+Loading into Flash: [==============================]  100%
+
+The device was rebooted to start the application.
+[user@host] raspberrypi-rp2040/ $ 
+```
 
diff --git a/raspberrypi-rp2040/build.zig b/raspberrypi-rp2040/build.zig
index 1128c6990..6e91de005 100644
--- a/raspberrypi-rp2040/build.zig
+++ b/raspberrypi-rp2040/build.zig
@@ -17,10 +17,11 @@ const available_examples = [_]Example{
     .{ .name = "pico_usb-hid", .target = rp2040.boards.raspberry_pi.pico, .file = "src/usb_hid.zig" },
     .{ .name = "pico_ws2812", .target = rp2040.boards.raspberry_pi.pico, .file = "src/ws2812.zig" },
 
+    .{ .name = "rp2040-matrix_tiles", .target = rp2040.boards.waveshare.rp2040_matrix, .file = "src/tiles.zig" },
+
     //     .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
     //     .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
     //     .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
-    //     .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
 };
 
 pub fn build(b: *std.Build) void {
diff --git a/raspberrypi-rp2040/src/tiles.zig b/raspberrypi-rp2040/src/tiles.zig
new file mode 100644
index 000000000..b55f791bf
--- /dev/null
+++ b/raspberrypi-rp2040/src/tiles.zig
@@ -0,0 +1,147 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const rp2040 = microzig.hal;
+const gpio = rp2040.gpio;
+const Pio = rp2040.pio.Pio;
+const StateMachine = rp2040.pio.StateMachine;
+
+const ws2812_program = blk: {
+    @setEvalBranchQuota(5000);
+    break :blk rp2040.pio.assemble(
+        \\;
+        \\; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
+        \\;
+        \\; SPDX-License-Identifier: BSD-3-Clause
+        \\;
+        \\.program ws2812
+        \\.side_set 1
+        \\
+        \\.define public T1 2
+        \\.define public T2 5
+        \\.define public T3 3
+        \\
+        \\.wrap_target
+        \\bitloop:
+        \\    out x, 1       side 0 [T3 - 1] ; Side-set still takes place when instruction stalls
+        \\    jmp !x do_zero side 1 [T1 - 1] ; Branch on the bit we shifted out. Positive pulse
+        \\do_one:
+        \\    jmp  bitloop   side 1 [T2 - 1] ; Continue driving high, for a long pulse
+        \\do_zero:
+        \\    nop            side 0 [T2 - 1] ; Or drive low, for a short pulse
+        \\.wrap
+    , .{}).get_program_by_name("ws2812");
+};
+
+const pio: Pio = .pio0;
+const sm: StateMachine = .sm0;
+const led_pin = gpio.num(16);
+
+const brightness: [256]u8 = blk: {
+    @setEvalBranchQuota(10_000);
+
+    const gamma = 2.2;
+
+    const max_brightness = 0x10;
+
+    var data: [256]u8 = undefined;
+    for (&data, 0..) |*bit, i| {
+        const raw_index: f32 = @floatFromInt(i);
+
+        const gamma_brightness = std.math.pow(f32, raw_index / 255.0, gamma);
+
+        bit.* = @intFromFloat(max_brightness * gamma_brightness);
+    }
+    // @compileLog(data);
+    break :blk data;
+};
+
+const RGB = extern struct {
+    x: u8 = 0x00,
+    b: u8,
+    g: u8,
+    r: u8,
+};
+
+inline fn floatToBright(f: f32) u8 {
+    return brightness[
+        @intFromFloat(
+            std.math.clamp(255.0 * f, 0.0, 255.0),
+        )
+    ];
+}
+
+pub fn main() void {
+    pio.gpio_init(led_pin);
+    sm_set_consecutive_pindirs(pio, sm, @intFromEnum(led_pin), 1, true);
+
+    const cycles_per_bit: comptime_int = ws2812_program.defines[0].value + //T1
+        ws2812_program.defines[1].value + //T2
+        ws2812_program.defines[2].value; //T3
+    const div = @as(f32, @floatFromInt(rp2040.clock_config.sys.?.output_freq)) /
+        (800_000 * cycles_per_bit);
+
+    pio.sm_load_and_start_program(sm, ws2812_program, .{
+        .clkdiv = rp2040.pio.ClkDivOptions.from_float(div),
+        .pin_mappings = .{
+            .side_set = .{
+                .base = @intFromEnum(led_pin),
+                .count = 1,
+            },
+        },
+        .shift = .{
+            .out_shiftdir = .left,
+            .autopull = true,
+            .pull_threshold = 24,
+            .join_tx = true,
+        },
+    }) catch unreachable;
+    pio.sm_set_enabled(sm, true);
+
+    var rng_src = std.rand.DefaultPrng.init(0x1234);
+
+    const rng = rng_src.random();
+
+    var screen: [5][5]RGB = undefined;
+    for (&screen) |*row| {
+        for (row) |*pix| {
+            pix.* = RGB{
+                .r = brightness[rng.int(u8)],
+                .g = brightness[rng.int(u8)],
+                .b = brightness[rng.int(u8)],
+            };
+        }
+    }
+
+    while (true) {
+        screen[rng.intRangeLessThan(u8, 0, 5)][rng.intRangeLessThan(u8, 0, 5)] = RGB{
+            .r = brightness[rng.int(u8)],
+            .g = brightness[rng.int(u8)],
+            .b = brightness[rng.int(u8)],
+        };
+
+        for (@as([25]RGB, @bitCast(screen))) |color| {
+            pio.sm_blocking_write(sm, @bitCast(color));
+        }
+        rp2040.time.sleep_ms(50);
+    }
+}
+
+fn sm_set_consecutive_pindirs(_pio: Pio, _sm: StateMachine, pin: u5, count: u3, is_out: bool) void {
+    const sm_regs = _pio.get_sm_regs(_sm);
+    const pinctrl_saved = sm_regs.pinctrl.raw;
+    sm_regs.pinctrl.modify(.{
+        .SET_BASE = pin,
+        .SET_COUNT = count,
+    });
+    _pio.sm_exec(_sm, rp2040.pio.Instruction{
+        .tag = .set,
+        .delay_side_set = 0,
+        .payload = .{
+            .set = .{
+                .data = @intFromBool(is_out),
+                .destination = .pindirs,
+            },
+        },
+    });
+    sm_regs.pinctrl.raw = pinctrl_saved;
+}

From b8437914f0d40dcc0b43b1acad2ca9efcf2b203c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 21:26:15 +0200
Subject: [PATCH 222/286] Fixes blinky for ESP32-C3-32S-Kit

---
 espressif-esp/README.md      |  4 +++
 espressif-esp/src/blinky.zig | 63 +++++++++++++++++++++++++++---------
 2 files changed, 52 insertions(+), 15 deletions(-)
 create mode 100644 espressif-esp/README.md

diff --git a/espressif-esp/README.md b/espressif-esp/README.md
new file mode 100644
index 000000000..bfa4e43bb
--- /dev/null
+++ b/espressif-esp/README.md
@@ -0,0 +1,4 @@
+# Examples for the BSP `espressif-esp`
+
+- [Blinky](src/blinky.zig) on [ESP32-C3-32S-Kit](https://www.waveshare.com/wiki/ESP-C3-32S-Kit)  
+  Showcases how to do a simple RGB cycling.
diff --git a/espressif-esp/src/blinky.zig b/espressif-esp/src/blinky.zig
index 811b04894..a44ac5f61 100644
--- a/espressif-esp/src/blinky.zig
+++ b/espressif-esp/src/blinky.zig
@@ -5,53 +5,86 @@ const TIMG0 = peripherals.TIMG0;
 const RTC_CNTL = peripherals.RTC_CNTL;
 const INTERRUPT_CORE0 = peripherals.INTERRUPT_CORE0;
 const GPIO = peripherals.GPIO;
+const IO_MUX = peripherals.IO_MUX;
 
 const dogfood: u32 = 0x50D83AA1;
 const super_dogfood: u32 = 0x8F1D312A;
 
+const LED_R_PIN = 3; // GPIO
+const LED_G_PIN = 4; // GPIO
+const LED_B_PIN = 5; // GPIO
+
+const led_pins = [_]u32{
+    LED_R_PIN,
+    LED_G_PIN,
+    LED_B_PIN,
+};
+
 pub fn main() !void {
+    // Feed and disable watchdog 0
     TIMG0.WDTWPROTECT.raw = dogfood;
     TIMG0.WDTCONFIG0.raw = 0;
     TIMG0.WDTWPROTECT.raw = 0;
 
+    // Feed and disable rtc watchdog
     RTC_CNTL.WDTWPROTECT.raw = dogfood;
     RTC_CNTL.WDTCONFIG0.raw = 0;
     RTC_CNTL.WDTWPROTECT.raw = 0;
 
+    // Feed and disable rtc super watchdog
     RTC_CNTL.SWD_WPROTECT.raw = super_dogfood;
     RTC_CNTL.SWD_CONF.modify(.{ .SWD_DISABLE = 1 });
     RTC_CNTL.SWD_WPROTECT.raw = 0;
 
+    // Disable all interrupts
     INTERRUPT_CORE0.CPU_INT_ENABLE.raw = 0;
 
-    microzig.hal.gpio.init(LED_R_PIN, .{
-        .direction = .output,
-        .direct_io = true,
-    });
-    microzig.hal.gpio.init(LED_G_PIN, .{
-        .direction = .output,
-        .direct_io = true,
-    });
-    microzig.hal.gpio.init(LED_B_PIN, .{
-        .direction = .output,
-        .direct_io = true,
+    GPIO.ENABLE.modify(.{
+        .DATA = (1 << LED_R_PIN) |
+            (1 << LED_G_PIN) |
+            (1 << LED_B_PIN),
     });
 
+    for (led_pins) |pin| {
+        IO_MUX.GPIO[pin].modify(.{
+            .MCU_OE = 1, // 1: output enabled
+            .SLP_SEL = 0, // Set to 1 to put the pin in sleep mode. (R/W)
+            .MCU_WPD = 0, // 0: internal pull-down disabled. (R/W)
+            .MCU_WPU = 0, // 0: internal pull-up disabled. (R/W)
+            .MCU_IE = 0, // 0: input disabled. (R/W)
+            .FUN_WPD = 0, // 0: internal pull-down disabled. (R/W)
+            .FUN_WPU = 0, // 0: internal pull-up disabled. (R/W)
+            .FUN_IE = 0, // 0: input disabled. (R/W)
+            .FUN_DRV = 3, // Select the drive strength of the pin. 0: ~5 mA; 1: ~ 10 mA; 2: ~ 20 mA; 3: ~40mA. (R/W)
+            .MCU_SEL = 1, // 1: GPIO
+            .FILTER_EN = 0, // 0: Filter disabled. (R/W)
+        });
+
+        GPIO.FUNC_OUT_SEL_CFG[pin].write(.{
+            // If a value 128 is written to this field, bit n of GPIO_OUT_REG and GPIO_ENABLE_REG will be selected as the output value and output enable. (R/W)
+            .OUT_SEL = 0x80,
+
+            .INV_SEL = 0x00, // 0: Do not invert the output value
+            .OEN_SEL = 0x01, // 1: Force the output enable signal to be sourced from bit n of GPIO_ENABLE_REG. (R/W)
+            .OEN_INV_SEL = 0x00, // 0: Do not invert the output enable signal
+
+            .padding = 0,
+        });
+    }
+
     microzig.hal.uart.write(0, "Hello from Zig!\r\n");
 
     while (true) {
         GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_R_PIN) });
         microzig.hal.uart.write(0, "R");
         microzig.core.experimental.debug.busy_sleep(100_000);
+
         GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_G_PIN) });
         microzig.hal.uart.write(0, "G");
         microzig.core.experimental.debug.busy_sleep(100_000);
+
         GPIO.OUT.modify(.{ .DATA_ORIG = (1 << LED_B_PIN) });
         microzig.hal.uart.write(0, "B");
         microzig.core.experimental.debug.busy_sleep(100_000);
     }
 }
-
-const LED_R_PIN = 3; // GPIO
-const LED_G_PIN = 16; // GPIO
-const LED_B_PIN = 17; // GPIO

From 2b4034fe7947db0cbb2a92a8f9ac4364bdc627ff Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 22:03:17 +0200
Subject: [PATCH 223/286] Makes nrf52 stuff work barely, but no blinky yet.

---
 nordic-nrf5x/build.zig      | 72 ++++++++-----------------------------
 nordic-nrf5x/src/blinky.zig |  6 ++++
 2 files changed, 20 insertions(+), 58 deletions(-)
 create mode 100644 nordic-nrf5x/src/blinky.zig

diff --git a/nordic-nrf5x/build.zig b/nordic-nrf5x/build.zig
index 406477261..85a2b6f17 100644
--- a/nordic-nrf5x/build.zig
+++ b/nordic-nrf5x/build.zig
@@ -1,75 +1,25 @@
 const std = @import("std");
-const rp2040 = @import("rp2040");
-const stm32 = @import("stm32");
-const lpc = @import("lpc");
-const gd32 = @import("gd32");
 const nrf5x = @import("nrf5x");
-const esp = @import("esp");
-const atmega = @import("atmega");
+
+const available_examples = [_]Example{
+    .{ .name = "nrf52480-dongle_blinky", .target = nrf5x.boards.nordic.nRF52840_Dongle, .file = "src/blinky.zig" },
+};
 
 pub fn build(b: *std.Build) void {
     const microzig = @import("microzig").init(b, "microzig");
     const optimize = b.standardOptimizeOption(.{});
 
-    const TargetDesc = struct {
-        target: @import("microzig").Target,
-        name: []const u8,
-    };
-
-    const available_targets = [_]TargetDesc{
-        // RP2040
-        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
-        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
-        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
-        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
-        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
-
-        // STM32
-        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
-        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
-        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
-        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
-        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
-        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
-        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
-        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
-
-        // NXP LPC
-        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
-        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
-
-        // GigaDevice GD32
-        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
-        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
-        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
-
-        // Nordic Nrf5x
-        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
-        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
-        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
-
-        // RISC-V Espressif ESP
-        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
-
-        // Microchip ATmega
-        // TODO: Fix compiler bugs
-        // - https://github.com/ziglang/zig/issues/17219
-        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
-        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
-        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
-    };
-
-    for (available_targets) |dest| {
+    for (available_examples) |example| {
         // `addFirmware` basically works like addExecutable, but takes a
         // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
         //
         // The target will convey all necessary information on the chip,
         // cpu and potentially the board as well.
         const firmware = microzig.addFirmware(b, .{
-            .name = b.fmt("empty-{s}", .{dest.name}),
-            .target = dest.target,
+            .name = example.name,
+            .target = example.target,
             .optimize = optimize,
-            .source_file = .{ .path = "src/empty.zig" },
+            .source_file = .{ .path = example.file },
         });
 
         // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
@@ -82,3 +32,9 @@ pub fn build(b: *std.Build) void {
         microzig.installFirmware(b, firmware, .{ .format = .elf });
     }
 }
+
+const Example = struct {
+    target: @import("microzig").Target,
+    name: []const u8,
+    file: []const u8,
+};
diff --git a/nordic-nrf5x/src/blinky.zig b/nordic-nrf5x/src/blinky.zig
new file mode 100644
index 000000000..db1529a0a
--- /dev/null
+++ b/nordic-nrf5x/src/blinky.zig
@@ -0,0 +1,6 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+pub fn main() !void {
+    // TODO: Implement the blinky
+}

From 15ea39573194a5e3fba4d876aefd72f2a45f8606 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 23 Sep 2023 23:58:59 +0200
Subject: [PATCH 224/286] Enables AVr

---
 .github/workflows/build.yml     |  2 +-
 microchip-atmega/build.zig      | 74 +++++++--------------------------
 microchip-atmega/src/blinky.zig | 15 +++++++
 nxp-lpc/README.md               |  5 ++-
 4 files changed, 34 insertions(+), 62 deletions(-)
 create mode 100644 microchip-atmega/src/blinky.zig

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 2805e5313..08208de71 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -16,8 +16,8 @@ jobs:
           - raspberrypi-rp2040
           - espressif-esp
           - nxp-lpc
+          - microchip-atmega
           # TODO: - gigadevice-gd32
-          # TODO: - microchip-atmega
           # TODO: - nordic-nrf5x
           # TODO: - stmicro-stm32
         os:
diff --git a/microchip-atmega/build.zig b/microchip-atmega/build.zig
index 406477261..4eba0c2fa 100644
--- a/microchip-atmega/build.zig
+++ b/microchip-atmega/build.zig
@@ -1,75 +1,25 @@
 const std = @import("std");
-const rp2040 = @import("rp2040");
-const stm32 = @import("stm32");
-const lpc = @import("lpc");
-const gd32 = @import("gd32");
-const nrf5x = @import("nrf5x");
-const esp = @import("esp");
 const atmega = @import("atmega");
 
+const available_examples = [_]Example{
+    .{ .name = "arduino-nano_blinky", .target = atmega.boards.arduino.nano, .file = "src/blinky.zig" },
+};
+
 pub fn build(b: *std.Build) void {
     const microzig = @import("microzig").init(b, "microzig");
-    const optimize = b.standardOptimizeOption(.{});
-
-    const TargetDesc = struct {
-        target: @import("microzig").Target,
-        name: []const u8,
-    };
-
-    const available_targets = [_]TargetDesc{
-        // RP2040
-        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
-        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
-        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
-        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
-        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
-
-        // STM32
-        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
-        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
-        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
-        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
-        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
-        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
-        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
-        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
-
-        // NXP LPC
-        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
-        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+    const optimize = .ReleaseSmall; // The others are not really an option on AVR
 
-        // GigaDevice GD32
-        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
-        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
-        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
-
-        // Nordic Nrf5x
-        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
-        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
-        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
-
-        // RISC-V Espressif ESP
-        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
-
-        // Microchip ATmega
-        // TODO: Fix compiler bugs
-        // - https://github.com/ziglang/zig/issues/17219
-        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
-        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
-        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
-    };
-
-    for (available_targets) |dest| {
+    for (available_examples) |example| {
         // `addFirmware` basically works like addExecutable, but takes a
         // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
         //
         // The target will convey all necessary information on the chip,
         // cpu and potentially the board as well.
         const firmware = microzig.addFirmware(b, .{
-            .name = b.fmt("empty-{s}", .{dest.name}),
-            .target = dest.target,
+            .name = example.name,
+            .target = example.target,
             .optimize = optimize,
-            .source_file = .{ .path = "src/empty.zig" },
+            .source_file = .{ .path = example.file },
         });
 
         // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
@@ -82,3 +32,9 @@ pub fn build(b: *std.Build) void {
         microzig.installFirmware(b, firmware, .{ .format = .elf });
     }
 }
+
+const Example = struct {
+    target: @import("microzig").Target,
+    name: []const u8,
+    file: []const u8,
+};
diff --git a/microchip-atmega/src/blinky.zig b/microchip-atmega/src/blinky.zig
new file mode 100644
index 000000000..2d2f2a157
--- /dev/null
+++ b/microchip-atmega/src/blinky.zig
@@ -0,0 +1,15 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+// LED is PB5
+const port = microzig.chip.peripherals.PORTB;
+
+pub fn main() void {
+    port.DDRB |= (1 << 5);
+    port.PORTB |= 0x00;
+
+    while (true) {
+        microzig.core.experimental.debug.busy_sleep(1_000);
+        port.PINB |= (1 << 5);
+    }
+}
diff --git a/nxp-lpc/README.md b/nxp-lpc/README.md
index 7bc74a7b4..7909f7c4c 100644
--- a/nxp-lpc/README.md
+++ b/nxp-lpc/README.md
@@ -1,4 +1,5 @@
 # Examples for the BSP `nxp-lpc`
 
-- [Blinky](src/blinky.zig) on [mbed LPC1768](https://os.mbed.com/platforms/mbed-LPC1768/)  
-  Performs a really basic round robin blinky on the four LEDs on the development board. Flash by copying `zig-out/firmware/mbed-lpc1768_blinky.hex` to the mass storage of the board, then press the big button in the center.
+- [Blinky](src/blinky.zig) on [nRF52840 Dongle](https://www.nordicsemi.com/Products/Development-hardware/nrf52840-dongle)  
+  TODO: Implement this!
+

From 237890d49ee795110a63df2c45bdd6f6a0029a72 Mon Sep 17 00:00:00 2001
From: fmaggi <61335294+fmaggi@users.noreply.github.com>
Date: Mon, 25 Sep 2023 12:14:35 -0300
Subject: [PATCH 225/286] Blue pill hal (#28)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* Rework for MicroZig Gen 2

* gpio hal for blue pill

* added a comment

* better interface

* Started implementing pins interface

* commented unused stuff for now

* forgot setting pin mode

* fixed somethings I forgot

* made global config have fields instead of decls

* fixed a bug

* Lots of bugs

* bugs bugs and more bugs

* bugs bunny

* forgot ?

* i

* sizes

* so weird

* weird size

* const issues

* const issues

* always const issues

* what is happeningn

* weird issues

* finally got a led to turn on!

* Rework for MicroZig Gen 2

* Rebased onto master

---------

Co-authored-by: Felix "xq" Queißner 
---
 build.zig                   |   4 +
 src/hals/STM32F103/gpio.zig | 160 ++++++++++++++++++++++++
 src/hals/STM32F103/hal.zig  |   3 +
 src/hals/STM32F103/pins.zig | 237 ++++++++++++++++++++++++++++++++++++
 4 files changed, 404 insertions(+)
 create mode 100644 src/hals/STM32F103/gpio.zig
 create mode 100644 src/hals/STM32F103/hal.zig
 create mode 100644 src/hals/STM32F103/pins.zig

diff --git a/build.zig b/build.zig
index 7a0aac02c..410578209 100644
--- a/build.zig
+++ b/build.zig
@@ -5,6 +5,7 @@ fn root() []const u8 {
     return comptime (std.fs.path.dirname(@src().file) orelse ".");
 }
 const build_root = root();
+
 const KiB = 1024;
 
 ////////////////////////////////////////
@@ -30,6 +31,9 @@ pub const chips = struct {
                 .json = .{ .cwd_relative = build_root ++ "/src/chips/STM32F103.json" },
             },
         },
+        .hal = .{
+            .source_file = .{ .cwd_relative = build_root ++ "/src/hals/STM32F103/hal.zig" },
+        },
     };
 
     pub const stm32f303vc = .{
diff --git a/src/hals/STM32F103/gpio.zig b/src/hals/STM32F103/gpio.zig
new file mode 100644
index 000000000..811a80c04
--- /dev/null
+++ b/src/hals/STM32F103/gpio.zig
@@ -0,0 +1,160 @@
+const std = @import("std");
+const assert = std.debug.assert;
+
+const microzig = @import("microzig");
+pub const peripherals = microzig.chip.peripherals;
+
+const GPIOA = peripherals.GPIOA;
+const GPIOB = peripherals.GPIOB;
+const GPIOC = peripherals.GPIOC;
+const GPIOD = peripherals.GPIOD;
+const GPIOE = peripherals.GPIOE;
+const GPIOF = peripherals.GPIOF;
+const GPIOG = peripherals.GPIOG;
+
+const GPIO = @TypeOf(GPIOA);
+
+const log = std.log.scoped(.gpio);
+
+pub const Function = enum {};
+
+pub const Mode = union(enum) {
+    input: InputMode,
+    output: OutputMode,
+};
+
+pub const InputMode = enum(u2) {
+    analog,
+    floating,
+    pull,
+    reserved,
+};
+
+pub const OutputMode = enum(u2) {
+    general_purpose_push_pull,
+    general_purpose_open_drain,
+    alternate_function_push_pull,
+    alternate_function_open_drain,
+};
+
+pub const Speed = enum(u2) {
+    reserved,
+    max_10MHz,
+    max_2MHz,
+    max_50MHz,
+};
+
+pub const IrqLevel = enum(u2) {
+    low,
+    high,
+    fall,
+    rise,
+};
+
+pub const IrqCallback = fn (gpio: u32, events: u32) callconv(.C) void;
+
+pub const Enabled = enum {
+    disabled,
+    enabled,
+};
+
+pub const Pull = enum {
+    up,
+    down,
+};
+
+// NOTE: With this current setup, every time we want to do anythting we go through a switch
+//       Do we want this?
+pub const Pin = packed struct(u8) {
+    number: u4,
+    port: u3,
+    padding: u1,
+
+    pub fn init(port: u3, number: u4) Pin {
+        return Pin{
+            .number = number,
+            .port = port,
+            .padding = 0,
+        };
+    }
+    inline fn write_pin_config(gpio: Pin, config: u32) void {
+        const port = gpio.get_port();
+        if (gpio.number <= 7) {
+            const offset = @as(u5, gpio.number) << 2;
+            port.CRL.raw &= ~(@as(u32, 0b1111) << offset);
+            port.CRL.raw |= config << offset;
+        } else {
+            const offset = (@as(u5, gpio.number) - 8) << 2;
+            port.CRH.raw &= ~(@as(u32, 0b1111) << offset);
+            port.CRH.raw |= config << offset;
+        }
+    }
+
+    fn mask(gpio: Pin) u16 {
+        return @as(u16, 1) << gpio.number;
+    }
+
+    // NOTE: Im not sure I like this
+    //       We could probably calculate an offset from GPIOA?
+    pub fn get_port(gpio: Pin) GPIO {
+        return switch (gpio.port) {
+            0 => GPIOA,
+            1 => GPIOB,
+            2 => GPIOC,
+            3 => GPIOD,
+            4 => GPIOE,
+            5 => GPIOF,
+            6 => GPIOG,
+            7 => @panic("The STM32 only has ports 0..6 (A..G)"),
+        };
+    }
+
+    pub inline fn set_mode(gpio: Pin, mode: Mode) void {
+        switch (mode) {
+            .input => |in| gpio.set_input_mode(in),
+            .output => |out| gpio.set_output_mode(out, .max_2MHz),
+        }
+    }
+
+    pub inline fn set_input_mode(gpio: Pin, mode: InputMode) void {
+        const m_mode = @as(u32, @intFromEnum(mode));
+        const config: u32 = m_mode << 2;
+        gpio.write_pin_config(config);
+    }
+
+    pub inline fn set_output_mode(gpio: Pin, mode: OutputMode, speed: Speed) void {
+        const s_speed = @as(u32, @intFromEnum(speed));
+        const m_mode = @as(u32, @intFromEnum(mode));
+        const config: u32 = s_speed + (m_mode << 2);
+        gpio.write_pin_config(config);
+    }
+
+    pub inline fn set_pull(gpio: Pin, pull: Pull) void {
+        var port = gpio.get_port();
+        switch (pull) {
+            .up => port.BSRR.raw = gpio.mask(),
+            .down => port.BRR.raw = gpio.mask(),
+        }
+    }
+
+    pub inline fn read(gpio: Pin) u1 {
+        const port = gpio.get_port();
+        return if (port.IDR.raw & gpio.mask() != 0)
+            1
+        else
+            0;
+    }
+
+    pub inline fn put(gpio: Pin, value: u1) void {
+        var port = gpio.get_port();
+        switch (value) {
+            0 => port.BSRR.raw = gpio.mask() << 16,
+            1 => port.BSRR.raw = gpio.mask(),
+        }
+    }
+
+    pub inline fn toggle(gpio: Pin) void {
+        var port = gpio.get_port();
+        port.ODR.raw ^= gpio.mask();
+    }
+};
diff --git a/src/hals/STM32F103/hal.zig b/src/hals/STM32F103/hal.zig
new file mode 100644
index 000000000..fafa677a6
--- /dev/null
+++ b/src/hals/STM32F103/hal.zig
@@ -0,0 +1,3 @@
+pub const pins = @import("pins.zig");
+
+pub fn init() void {}
diff --git a/src/hals/STM32F103/pins.zig b/src/hals/STM32F103/pins.zig
new file mode 100644
index 000000000..021dd6c11
--- /dev/null
+++ b/src/hals/STM32F103/pins.zig
@@ -0,0 +1,237 @@
+const std = @import("std");
+const assert = std.debug.assert;
+const comptimePrint = std.fmt.comptimePrint;
+const StructField = std.builtin.Type.StructField;
+
+const microzig = @import("microzig");
+
+const RCC = microzig.chip.peripherals.RCC;
+
+const gpio = @import("gpio.zig");
+// const pwm = @import("pwm.zig");
+// const adc = @import("adc.zig");
+// const resets = @import("resets.zig");
+
+pub const Pin = enum {
+    PIN0,
+    PIN1,
+    PIN2,
+    PIN3,
+    PIN4,
+    PIN5,
+    PIN6,
+    PIN7,
+    PIN8,
+    PIN9,
+    PIN10,
+    PIN11,
+    PIN12,
+    PIN13,
+    PIN14,
+    PIN15,
+    pub const Configuration = struct {
+        name: ?[]const u8 = null,
+        // function: Function = .SIO,
+        mode: ?gpio.Mode = null,
+        speed: ?gpio.Speed = null,
+        pull: ?gpio.Pull = null,
+        // input/output enable
+        // schmitt trigger
+        // hysteresis
+
+        pub fn get_mode(comptime config: Configuration) gpio.Mode {
+            return if (config.mode) |mode|
+                mode
+                // else if (comptime config.function.is_pwm())
+                //     .out
+                // else if (comptime config.function.is_uart_tx())
+                //     .out
+                // else if (comptime config.function.is_uart_rx())
+                //     .in
+                // else if (comptime config.function.is_adc())
+                //     .in
+            else
+                @panic("TODO");
+        }
+    };
+};
+
+pub fn GPIO(comptime port: u3, comptime num: u4, comptime mode: gpio.Mode) type {
+    return switch (mode) {
+        .input => struct {
+            const pin = gpio.Pin.init(port, num);
+
+            pub inline fn read(self: @This()) u1 {
+                _ = self;
+                return pin.read();
+            }
+        },
+        .output => struct {
+            const pin = gpio.Pin.init(port, num);
+
+            pub inline fn put(self: @This(), value: u1) void {
+                _ = self;
+                pin.put(value);
+            }
+
+            pub inline fn toggle(self: @This()) void {
+                _ = self;
+                pin.toggle();
+            }
+        },
+    };
+}
+
+pub fn Pins(comptime config: GlobalConfiguration) type {
+    comptime {
+        var fields: []const StructField = &.{};
+        for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| {
+            if (@field(config, port_field.name)) |port_config| {
+                for (@typeInfo(Port.Configuration).Struct.fields) |field| {
+                    if (@field(port_config, field.name)) |pin_config| {
+                        var pin_field = StructField{
+                            .is_comptime = false,
+                            .default_value = null,
+
+                            // initialized below:
+                            .name = undefined,
+                            .type = undefined,
+                            .alignment = undefined,
+                        };
+
+                        pin_field.name = pin_config.name orelse field.name;
+                        pin_field.type = GPIO(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name)), pin_config.mode orelse .{ .input = .{.floating} });
+                        pin_field.alignment = @alignOf(field.type);
+
+                        fields = fields ++ &[_]StructField{pin_field};
+                    }
+                }
+            }
+        }
+
+        return @Type(.{
+            .Struct = .{
+                .layout = .Auto,
+                .is_tuple = false,
+                .fields = fields,
+                .decls = &.{},
+            },
+        });
+    }
+}
+
+pub const Port = enum {
+    GPIOA,
+    GPIOB,
+    GPIOC,
+    GPIOD,
+    GPIOE,
+    GPIOF,
+    GPIOG,
+    pub const Configuration = struct {
+        PIN0: ?Pin.Configuration = null,
+        PIN1: ?Pin.Configuration = null,
+        PIN2: ?Pin.Configuration = null,
+        PIN3: ?Pin.Configuration = null,
+        PIN4: ?Pin.Configuration = null,
+        PIN5: ?Pin.Configuration = null,
+        PIN6: ?Pin.Configuration = null,
+        PIN7: ?Pin.Configuration = null,
+        PIN8: ?Pin.Configuration = null,
+        PIN9: ?Pin.Configuration = null,
+        PIN10: ?Pin.Configuration = null,
+        PIN11: ?Pin.Configuration = null,
+        PIN12: ?Pin.Configuration = null,
+        PIN13: ?Pin.Configuration = null,
+        PIN14: ?Pin.Configuration = null,
+        PIN15: ?Pin.Configuration = null,
+
+        comptime {
+            const pin_field_count = @typeInfo(Pin).Enum.fields.len;
+            const config_field_count = @typeInfo(Configuration).Struct.fields.len;
+            if (pin_field_count != config_field_count)
+                @compileError(comptimePrint("{} {}", .{ pin_field_count, config_field_count }));
+        }
+    };
+};
+
+pub const GlobalConfiguration = struct {
+    GPIOA: ?Port.Configuration = null,
+    GPIOB: ?Port.Configuration = null,
+    GPIOC: ?Port.Configuration = null,
+    GPIOD: ?Port.Configuration = null,
+    GPIOE: ?Port.Configuration = null,
+    GPIOF: ?Port.Configuration = null,
+    GPIOG: ?Port.Configuration = null,
+
+    comptime {
+        const port_field_count = @typeInfo(Port).Enum.fields.len;
+        const config_field_count = @typeInfo(GlobalConfiguration).Struct.fields.len;
+        if (port_field_count != config_field_count)
+            @compileError(comptimePrint("{} {}", .{ port_field_count, config_field_count }));
+    }
+
+    pub fn apply(comptime config: GlobalConfiguration) Pins(config) {
+        inline for (@typeInfo(GlobalConfiguration).Struct.fields) |port_field| {
+            if (@field(config, port_field.name)) |port_config| {
+                comptime var input_gpios: u16 = 0;
+                comptime var output_gpios: u16 = 0;
+                comptime {
+                    inline for (@typeInfo(Port.Configuration).Struct.fields) |field|
+                        if (@field(port_config, field.name)) |pin_config| {
+                            const gpio_num = @intFromEnum(@field(Pin, field.name));
+
+                            switch (pin_config.get_mode()) {
+                                .input => input_gpios |= 1 << gpio_num,
+                                .output => output_gpios |= 1 << gpio_num,
+                            }
+                        };
+                }
+
+                // TODO: ensure only one instance of an input function exists
+                const used_gpios = comptime input_gpios | output_gpios;
+
+                if (used_gpios != 0) {
+                    const offset = @intFromEnum(@field(Port, port_field.name)) + 2;
+                    const bit = @as(u32, 1 << offset);
+                    RCC.APB2ENR.raw |= bit;
+                    // Delay after setting
+                    _ = RCC.APB2ENR.raw & bit;
+                }
+
+                inline for (@typeInfo(Port.Configuration).Struct.fields) |field| {
+                    if (@field(port_config, field.name)) |pin_config| {
+                        var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name)));
+                        pin.set_mode(pin_config.mode.?);
+                    }
+                }
+
+                if (input_gpios != 0) {
+                    inline for (@typeInfo(Port.Configuration).Struct.fields) |field|
+                        if (@field(port_config, field.name)) |pin_config| {
+                            var pin = gpio.Pin.init(@intFromEnum(@field(Port, port_field.name)), @intFromEnum(@field(Pin, field.name)));
+                            const pull = pin_config.pull orelse continue;
+                            if (comptime pin_config.get_mode() != .input)
+                                @compileError("Only input pins can have pull up/down enabled");
+
+                            pin.set_pull(pull);
+                        };
+                }
+            }
+        }
+
+        // fields in the Pins(config) type should be zero sized, so we just
+        // default build them all (wasn't sure how to do that cleanly in
+        // `Pins()`
+        var ret: Pins(config) = undefined;
+        inline for (@typeInfo(Pins(config)).Struct.fields) |field| {
+            if (field.default_value) |default_value| {
+                @field(ret, field.name) = @as(*const field.field_type, @ptrCast(default_value)).*;
+            } else {
+                @field(ret, field.name) = .{};
+            }
+        }
+        return ret;
+        // validate selected function
+    }
+};

From a9c3ae56907ad8949325dfb7e532a038e5d6ec77 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Mon, 25 Sep 2023 18:41:49 +0200
Subject: [PATCH 226/286] Enables all packages, with no examples if defunct.

---
 .github/workflows/build.yml |  6 +--
 gigadevice-gd32/build.zig   | 76 ++++++++--------------------------
 microchip-atmega/build.zig  |  2 +-
 stmicro-stm32/build.zig     | 81 ++++++++++---------------------------
 4 files changed, 43 insertions(+), 122 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 08208de71..720973f40 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -17,9 +17,9 @@ jobs:
           - espressif-esp
           - nxp-lpc
           - microchip-atmega
-          # TODO: - gigadevice-gd32
-          # TODO: - nordic-nrf5x
-          # TODO: - stmicro-stm32
+          - gigadevice-gd32
+          - nordic-nrf5x
+          - stmicro-stm32
         os:
           - windows-latest
           - macos-latest
diff --git a/gigadevice-gd32/build.zig b/gigadevice-gd32/build.zig
index 406477261..b7a2e4cf7 100644
--- a/gigadevice-gd32/build.zig
+++ b/gigadevice-gd32/build.zig
@@ -1,75 +1,27 @@
 const std = @import("std");
-const rp2040 = @import("rp2040");
-const stm32 = @import("stm32");
-const lpc = @import("lpc");
 const gd32 = @import("gd32");
-const nrf5x = @import("nrf5x");
-const esp = @import("esp");
-const atmega = @import("atmega");
+
+const available_examples = [_]Example{
+    // .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb, .file = "src/blinky.zig" },
+    // .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8, .file = "src/blinky.zig" },
+    // .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano, .file = "src/blinky.zig" },
+};
 
 pub fn build(b: *std.Build) void {
     const microzig = @import("microzig").init(b, "microzig");
-    const optimize = b.standardOptimizeOption(.{});
-
-    const TargetDesc = struct {
-        target: @import("microzig").Target,
-        name: []const u8,
-    };
-
-    const available_targets = [_]TargetDesc{
-        // RP2040
-        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
-        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
-        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
-        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
-        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
-
-        // STM32
-        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
-        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
-        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
-        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
-        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
-        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
-        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
-        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
-
-        // NXP LPC
-        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
-        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+    const optimize = .ReleaseSmall; // The others are not really an option on AVR
 
-        // GigaDevice GD32
-        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
-        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
-        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
-
-        // Nordic Nrf5x
-        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
-        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
-        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
-
-        // RISC-V Espressif ESP
-        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
-
-        // Microchip ATmega
-        // TODO: Fix compiler bugs
-        // - https://github.com/ziglang/zig/issues/17219
-        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
-        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
-        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
-    };
-
-    for (available_targets) |dest| {
+    for (available_examples) |example| {
         // `addFirmware` basically works like addExecutable, but takes a
         // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
         //
         // The target will convey all necessary information on the chip,
         // cpu and potentially the board as well.
         const firmware = microzig.addFirmware(b, .{
-            .name = b.fmt("empty-{s}", .{dest.name}),
-            .target = dest.target,
+            .name = example.name,
+            .target = example.target,
             .optimize = optimize,
-            .source_file = .{ .path = "src/empty.zig" },
+            .source_file = .{ .path = example.file },
         });
 
         // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
@@ -82,3 +34,9 @@ pub fn build(b: *std.Build) void {
         microzig.installFirmware(b, firmware, .{ .format = .elf });
     }
 }
+
+const Example = struct {
+    target: @import("microzig").Target,
+    name: []const u8,
+    file: []const u8,
+};
diff --git a/microchip-atmega/build.zig b/microchip-atmega/build.zig
index 4eba0c2fa..6459450dd 100644
--- a/microchip-atmega/build.zig
+++ b/microchip-atmega/build.zig
@@ -2,7 +2,7 @@ const std = @import("std");
 const atmega = @import("atmega");
 
 const available_examples = [_]Example{
-    .{ .name = "arduino-nano_blinky", .target = atmega.boards.arduino.nano, .file = "src/blinky.zig" },
+    // TODO:    .{ .name = "arduino-nano_blinky", .target = atmega.boards.arduino.nano, .file = "src/blinky.zig" },
 };
 
 pub fn build(b: *std.Build) void {
diff --git a/stmicro-stm32/build.zig b/stmicro-stm32/build.zig
index 406477261..26bbda7eb 100644
--- a/stmicro-stm32/build.zig
+++ b/stmicro-stm32/build.zig
@@ -1,75 +1,32 @@
 const std = @import("std");
-const rp2040 = @import("rp2040");
 const stm32 = @import("stm32");
-const lpc = @import("lpc");
-const gd32 = @import("gd32");
-const nrf5x = @import("nrf5x");
-const esp = @import("esp");
-const atmega = @import("atmega");
+
+const available_examples = [_]Example{
+    // TODO: .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8, .file = "src/blinky.zig" },
+    // TODO: .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc, .file = "src/blinky.zig" },
+    // TODO: .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg, .file = "src/blinky.zig" },
+    // TODO: .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u, .file = "src/blinky.zig" },
+    // TODO: .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery, .file = "src/blinky.zig" },
+    // TODO: .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery, .file = "src/blinky.zig" },
+    // TODO: .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval, .file = "src/blinky.zig" },
+    // TODO: .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery, .file = "src/blinky.zig" },
+};
 
 pub fn build(b: *std.Build) void {
     const microzig = @import("microzig").init(b, "microzig");
-    const optimize = b.standardOptimizeOption(.{});
-
-    const TargetDesc = struct {
-        target: @import("microzig").Target,
-        name: []const u8,
-    };
-
-    const available_targets = [_]TargetDesc{
-        // RP2040
-        .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
-        .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
-        .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
-        .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
-        .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
-
-        // STM32
-        .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
-        .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
-        .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
-        .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
-        .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
-        .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
-        .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
-        .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
-
-        // NXP LPC
-        .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
-        .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
+    const optimize = .ReleaseSmall; // The others are not really an option on AVR
 
-        // GigaDevice GD32
-        .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
-        .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
-        .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
-
-        // Nordic Nrf5x
-        .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
-        .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
-        .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
-
-        // RISC-V Espressif ESP
-        .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
-
-        // Microchip ATmega
-        // TODO: Fix compiler bugs
-        // - https://github.com/ziglang/zig/issues/17219
-        // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
-        // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
-        // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
-    };
-
-    for (available_targets) |dest| {
+    for (available_examples) |example| {
         // `addFirmware` basically works like addExecutable, but takes a
         // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
         //
         // The target will convey all necessary information on the chip,
         // cpu and potentially the board as well.
         const firmware = microzig.addFirmware(b, .{
-            .name = b.fmt("empty-{s}", .{dest.name}),
-            .target = dest.target,
+            .name = example.name,
+            .target = example.target,
             .optimize = optimize,
-            .source_file = .{ .path = "src/empty.zig" },
+            .source_file = .{ .path = example.file },
         });
 
         // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
@@ -82,3 +39,9 @@ pub fn build(b: *std.Build) void {
         microzig.installFirmware(b, firmware, .{ .format = .elf });
     }
 }
+
+const Example = struct {
+    target: @import("microzig").Target,
+    name: []const u8,
+    file: []const u8,
+};

From b63d10598fa15bbadc7e2fe3f482ddfa097e9415 Mon Sep 17 00:00:00 2001
From: Francisco 
Date: Tue, 26 Sep 2023 09:37:41 -0300
Subject: [PATCH 227/286] blinky for the stm32f103

---
 stmicro-stm32/build.zig      |  2 +-
 stmicro-stm32/build.zig.zon  |  4 ++--
 stmicro-stm32/src/blinky.zig | 22 ++++++++++++++++++++++
 3 files changed, 25 insertions(+), 3 deletions(-)
 create mode 100644 stmicro-stm32/src/blinky.zig

diff --git a/stmicro-stm32/build.zig b/stmicro-stm32/build.zig
index 26bbda7eb..471a7276d 100644
--- a/stmicro-stm32/build.zig
+++ b/stmicro-stm32/build.zig
@@ -2,7 +2,7 @@ const std = @import("std");
 const stm32 = @import("stm32");
 
 const available_examples = [_]Example{
-    // TODO: .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8, .file = "src/blinky.zig" },
+    .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8, .file = "src/blinky.zig" },
     // TODO: .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc, .file = "src/blinky.zig" },
     // TODO: .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg, .file = "src/blinky.zig" },
     // TODO: .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u, .file = "src/blinky.zig" },
diff --git a/stmicro-stm32/build.zig.zon b/stmicro-stm32/build.zig.zon
index e54d44fbf..b6063eabc 100644
--- a/stmicro-stm32/build.zig.zon
+++ b/stmicro-stm32/build.zig.zon
@@ -7,8 +7,8 @@
             .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
         },
         .stm32 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/stmicro-stm32/archive/cb2893707efa6aa289fa72f02959ad5f2d9db2a1.tar.gz",
-            .hash = "12208cab5f60ef97cac4165ad694f3ba0c7b28f279538c1539b74f7c152f34fe306d",
+            .url = "https://github.com/ZigEmbeddedGroup/stmicro-stm32/archive/237890d49ee795110a63df2c45bdd6f6a0029a72.tar.gz",
+            .hash = "1220960897777f9713fa1055ffdf1fbad1518b2f62bd2f2ae39b887821dbf0781df0",
         },
     },
 }
diff --git a/stmicro-stm32/src/blinky.zig b/stmicro-stm32/src/blinky.zig
new file mode 100644
index 000000000..1fad430e1
--- /dev/null
+++ b/stmicro-stm32/src/blinky.zig
@@ -0,0 +1,22 @@
+const std = @import("std");
+const microzig = @import("microzig");
+const stm32 = microzig.hal;
+
+const pin_config = stm32.pins.GlobalConfiguration{
+    .GPIOC = .{
+        .PIN13 = .{ .name = "led", .mode = .{ .output = .general_purpose_push_pull } },
+    },
+};
+
+pub fn main() !void {
+    const pins = pin_config.apply();
+
+    while (true) {
+        var i: u32 = 0;
+        while (i < 800_000) {
+            asm volatile ("nop");
+            i += 1;
+        }
+        pins.led.toggle();
+    }
+}

From d361a622baeaf827831507163f5fba090e049b65 Mon Sep 17 00:00:00 2001
From: Vesim 
Date: Tue, 26 Sep 2023 17:57:22 +0200
Subject: [PATCH 228/286] add umm allocator (#148)

---
 build.zig         | 3 +++
 build.zig.zon     | 4 ++++
 src/core.zig      | 2 ++
 src/core/heap.zig | 5 +++++
 4 files changed, 14 insertions(+)
 create mode 100644 src/core/heap.zig

diff --git a/build.zig b/build.zig
index 9b92d6b89..f801a558a 100644
--- a/build.zig
+++ b/build.zig
@@ -538,6 +538,9 @@ pub fn addFirmware(
         },
     });
 
+    const umm = mz.dependency("umm-zig", .{}).module("umm");
+    fw.modules.microzig.dependencies.put("umm", umm) catch @panic("out of memory");
+
     fw.artifact.addModule("app", fw.modules.app);
     fw.artifact.addModule("microzig", fw.modules.microzig);
 
diff --git a/build.zig.zon b/build.zig.zon
index 5f0ac76f9..e790e7db7 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -10,5 +10,9 @@
             .url = "https://github.com/ZigEmbeddedGroup/regz/archive/b0ded63fc284da0ed9f4776eb7d1c4ad7175622d.tar.gz",
             .hash = "1220e9299f949d3566a1dc4dd62caf82a06bb6c8ad5a693e62117b0941da9dc55ea2",
         },
+        .@"umm-zig" = .{
+            .url = "https://github.com/ZigEmbeddedGroup/umm-zig/archive/99d815adfbc5cc4ad385dd765a6192f85e54179f.tar.gz",
+            .hash = "12207ef7375ea45e97f4fba9c5dfa74d022902893c4dbf1a0076726b7ec39a02ea3f",
+        },
     },
 }
diff --git a/src/core.zig b/src/core.zig
index 10b26c25c..232f0f70f 100644
--- a/src/core.zig
+++ b/src/core.zig
@@ -1,7 +1,9 @@
 pub const experimental = @import("core/experimental.zig");
+pub const heap = @import("core/heap.zig");
 /// USB data types and helper functions
 pub const usb = @import("core/usb.zig");
 
 test "core tests" {
     _ = usb;
+    _ = heap;
 }
diff --git a/src/core/heap.zig b/src/core/heap.zig
new file mode 100644
index 000000000..ae6501a7b
--- /dev/null
+++ b/src/core/heap.zig
@@ -0,0 +1,5 @@
+pub const UmmAllocator = @import("umm").UmmAllocator;
+
+test "heap tests" {
+    _ = UmmAllocator;
+}

From f286bc8e25837131a4bc0eb0adb0ccb5175c3cd3 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ardelean=20C=C4=83lin?=
 <9417983+Ardelean-Calin@users.noreply.github.com>
Date: Tue, 26 Sep 2023 21:39:06 +0300
Subject: [PATCH 229/286] Corrected Cortex-M ABI (#149)

---
 build.zig | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/build.zig b/build.zig
index f801a558a..748833fd4 100644
--- a/build.zig
+++ b/build.zig
@@ -793,7 +793,7 @@ pub const cpus = struct {
             .cpu_arch = .thumb,
             .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 },
             .os_tag = .freestanding,
-            .abi = .none,
+            .abi = .eabi,
         },
     };
 
@@ -804,7 +804,7 @@ pub const cpus = struct {
             .cpu_arch = .thumb,
             .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus },
             .os_tag = .freestanding,
-            .abi = .none,
+            .abi = .eabi,
         },
     };
 
@@ -815,7 +815,7 @@ pub const cpus = struct {
             .cpu_arch = .thumb,
             .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 },
             .os_tag = .freestanding,
-            .abi = .none,
+            .abi = .eabi,
         },
     };
 
@@ -826,7 +826,7 @@ pub const cpus = struct {
             .cpu_arch = .thumb,
             .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 },
             .os_tag = .freestanding,
-            .abi = .none,
+            .abi = .eabi,
         },
     };
 

From 2873e9e0b109ce55aab083e56225c783f2b7ff2a Mon Sep 17 00:00:00 2001
From: Marnix Klooster 
Date: Thu, 26 Oct 2023 21:29:28 +0200
Subject: [PATCH 230/286] Change the HAL API to snake_case() from camelCase()
 (#151)

---
 src/core/experimental/debug.zig |  2 +-
 src/core/experimental/i2c.zig   | 22 ++++++++++----------
 src/core/experimental/spi.zig   | 36 ++++++++++++++++-----------------
 src/core/experimental/uart.zig  |  8 ++++----
 4 files changed, 34 insertions(+), 34 deletions(-)

diff --git a/src/core/experimental/debug.zig b/src/core/experimental/debug.zig
index c74bdba31..767f8c316 100644
--- a/src/core/experimental/debug.zig
+++ b/src/core/experimental/debug.zig
@@ -30,7 +30,7 @@ const DebugWriter = std.io.Writer(void, DebugErr, writer_write);
 pub fn write(string: []const u8) void {
     if (!config.has_board)
         return;
-    if (!@hasDecl(board, "debugWrite"))
+    if (!@hasDecl(board, "debug_write"))
         return;
 
     board.debug_write(string);
diff --git a/src/core/experimental/i2c.zig b/src/core/experimental/i2c.zig
index 7eefcbde4..52fbaa373 100644
--- a/src/core/experimental/i2c.zig
+++ b/src/core/experimental/i2c.zig
@@ -28,7 +28,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type {
                     }
 
                     fn read_some(self: *Self, buffer: []u8) ReadError!usize {
-                        try self.state.readNoEof(buffer);
+                        try self.state.read_no_eof(buffer);
                         return buffer.len;
                     }
 
@@ -41,7 +41,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type {
                     /// Note that some platforms set the repeated START condition
                     /// on the first read or write call.
                     pub fn restart_transfer(self: *Self, comptime new_direction: Direction) !Transfer(new_direction) {
-                        return Transfer(direction){ .state = try self.state.restartTransfer(new_direction) };
+                        return Transfer(direction){ .state = try self.state.restart_transfer(new_direction) };
                     }
                 },
                 .write => struct {
@@ -59,7 +59,7 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type {
                     }
 
                     fn write_some(self: *Self, buffer: []const u8) WriteError!usize {
-                        try self.state.writeAll(buffer);
+                        try self.state.write_all(buffer);
                         return buffer.len;
                     }
 
@@ -73,8 +73,8 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type {
                     /// on the first read or write call.
                     pub fn restart_transfer(self: *Self, comptime new_direction: Direction) !Transfer(new_direction) {
                         return switch (new_direction) {
-                            .read => Transfer(new_direction){ .state = try self.state.restartRead() },
-                            .write => Transfer(new_direction){ .state = try self.state.restartWrite() },
+                            .read => Transfer(new_direction){ .state = try self.state.restart_read() },
+                            .write => Transfer(new_direction){ .state = try self.state.restart_write() },
                         };
                     }
                 },
@@ -93,12 +93,12 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type {
 
         /// Shorthand for 'register-based' devices
         pub fn write_register(self: Device, register_address: u8, byte: u8) ReadError!void {
-            try self.writeRegisters(register_address, &.{byte});
+            try self.write_registers(register_address, &.{byte});
         }
 
         /// Shorthand for 'register-based' devices
-        pub fn write_registers(self: Device, register_address: u8, buffer: []u8) ReadError!void {
-            var wt = try self.startTransfer(.write);
+        pub fn write_registers(self: Device, register_address: u8, buffer: []const u8) ReadError!void {
+            var wt = try self.start_transfer(.write);
             defer wt.stop() catch {};
             try wt.writer().writeByte(register_address);
             try wt.writer().writeAll(buffer);
@@ -107,17 +107,17 @@ pub fn I2CController(comptime index: usize, comptime pins: Pins) type {
         /// Shorthand for 'register-based' devices
         pub fn read_register(self: Device, register_address: u8) ReadError!u8 {
             var buffer: [1]u8 = undefined;
-            try self.readRegisters(register_address, &buffer);
+            try self.read_registers(register_address, &buffer);
             return buffer[0];
         }
 
         /// Shorthand for 'register-based' devices
         pub fn read_registers(self: Device, register_address: u8, buffer: []u8) ReadError!void {
             var rt = write_and_restart: {
-                var wt = try self.startTransfer(.write);
+                var wt = try self.start_transfer(.write);
                 errdefer wt.stop() catch {};
                 try wt.writer().writeByte(1 << 7 | register_address); // MSB == 'keep sending until I STOP'
-                break :write_and_restart try wt.restartTransfer(.read);
+                break :write_and_restart try wt.restart_transfer(.read);
             };
             defer rt.stop() catch {};
             try rt.reader().readNoEof(buffer);
diff --git a/src/core/experimental/spi.zig b/src/core/experimental/spi.zig
index 250e74768..7db6ab5a7 100644
--- a/src/core/experimental/spi.zig
+++ b/src/core/experimental/spi.zig
@@ -1,16 +1,16 @@
 const std = @import("std");
-const micro = @import("microzig");
-const chip = @import("chip");
+const hal = @import("hal");
+const clock = @import("clock.zig"); // Is there a different/better way?
 
 /// The SPI bus with the given environment-specific number.
 /// Only 'master' mode is supported currently.
 pub fn SpiBus(comptime index: usize) type {
-    const SystemSpi = chip.SpiBus(index);
+    const SystemSpi = hal.SpiBus(index);
 
     return struct {
         /// A SPI 'slave' device, selected via the given CS pin.
         /// (Default is CS=low to select.)
-        pub fn SpiDevice(comptime cs_pin: type, config: DeviceConfig) type {
+        pub fn SpiDevice(comptime cs_pin: type, comptime config: DeviceConfig) type {
             return struct {
                 const SelfSpiDevice = @This();
 
@@ -24,7 +24,7 @@ pub fn SpiBus(comptime index: usize) type {
                     device: SelfSpiDevice,
 
                     fn transceive_byte(self: *SelfTransfer, write_byte: u8, read_pointer: *u8) !void {
-                        try self.device.internal.transceiveByte(write_byte, read_pointer);
+                        try self.device.internal.transceive_byte(write_byte, read_pointer);
                     }
 
                     pub const Writer = std.io.Writer(*SelfTransfer, WriteError, write_some);
@@ -35,7 +35,7 @@ pub fn SpiBus(comptime index: usize) type {
                     }
 
                     fn write_some(self: *SelfTransfer, buffer: []const u8) WriteError!usize {
-                        try self.device.internal.writeAll(buffer);
+                        try self.device.internal.write_all(buffer);
                         return buffer.len;
                     }
 
@@ -47,40 +47,40 @@ pub fn SpiBus(comptime index: usize) type {
                     }
 
                     fn read_some(self: *SelfTransfer, buffer: []u8) ReadError!usize {
-                        try self.device.internal.readInto(buffer);
+                        try self.device.internal.read_into(buffer);
                         return buffer.len;
                     }
 
                     /// end the current transfer, releasing via the CS pin
                     pub fn end(self: *SelfTransfer) void {
-                        self.device.internal.endTransfer(cs_pin, config);
+                        self.device.internal.end_transfer(cs_pin, config);
                     }
                 };
 
                 /// start a new transfer, selecting using the CS pin
                 pub fn begin_transfer(self: SelfSpiDevice) !Transfer {
-                    self.internal.switchToDevice(cs_pin, config);
-                    self.internal.beginTransfer(cs_pin, config);
+                    self.internal.switch_to_device(cs_pin, config);
+                    self.internal.begin_transfer(cs_pin, config);
                     return Transfer{ .device = self };
                 }
 
                 pub fn transceive(self: SelfSpiDevice, write_buffer: []const u8, read_buffer: []u8) !void {
                     std.debug.assert(write_buffer.len == read_buffer.len);
-                    var transfer = try self.beginTransfer();
+                    var transfer = try self.begin_transfer();
                     defer transfer.end();
                     for (write_buffer, 0..) |_, i| {
-                        try transfer.transceiveByte(write_buffer[i], &read_buffer[i]);
+                        try transfer.transceive_byte(write_buffer[i], &read_buffer[i]);
                     }
                 }
 
                 /// Shorthand for 'register-based' devices
                 pub fn write_register(self: SelfSpiDevice, register_address: u8, byte: u8) ReadError!void {
-                    try self.writeRegisters(register_address, &.{byte});
+                    try self.write_registers(register_address, &.{byte});
                 }
 
                 /// Shorthand for 'register-based' devices
-                pub fn write_registers(self: SelfSpiDevice, register_address: u8, buffer: []u8) ReadError!void {
-                    var transfer = try self.beginTransfer();
+                pub fn write_registers(self: SelfSpiDevice, register_address: u8, buffer: []const u8) ReadError!void {
+                    var transfer = try self.begin_transfer();
                     defer transfer.end();
                     // write auto-increment, starting at given register
                     try transfer.writer().writeByte(0b01_000000 | register_address);
@@ -90,13 +90,13 @@ pub fn SpiBus(comptime index: usize) type {
                 /// Shorthand for 'register-based' devices
                 pub fn read_register(self: SelfSpiDevice, register_address: u8) ReadError!u8 {
                     var buffer: [1]u8 = undefined;
-                    try self.readRegisters(register_address, &buffer);
+                    try self.read_registers(register_address, &buffer);
                     return buffer[0];
                 }
 
                 /// Shorthand for 'register-based' devices
                 pub fn read_registers(self: SelfSpiDevice, register_address: u8, buffer: []u8) ReadError!void {
-                    var transfer = try self.beginTransfer();
+                    var transfer = try self.begin_transfer();
                     defer transfer.end();
                     // read auto-increment, starting at given register
                     try transfer.writer().writeByte(0b11_000000 | register_address);
@@ -111,7 +111,7 @@ pub fn SpiBus(comptime index: usize) type {
 
         /// Initialize this SPI bus and return a handle to it.
         pub fn init(config: BusConfig) InitError!SelfSpiBus {
-            micro.clock.ensure(); // TODO: Wat?
+            clock.ensure(); // TODO: Wat?
             return SelfSpiBus{
                 .internal = try SystemSpi.init(config),
             };
diff --git a/src/core/experimental/uart.zig b/src/core/experimental/uart.zig
index bba29dad8..e64dd5e9d 100644
--- a/src/core/experimental/uart.zig
+++ b/src/core/experimental/uart.zig
@@ -20,21 +20,21 @@ pub fn Uart(comptime index: usize, comptime pins: Pins) type {
         /// If the UART is already initialized, try to return a handle to it,
         /// else initialize with the given config.
         pub fn get_or_init(config: Config) InitError!Self {
-            if (!@hasDecl(SystemUart, "getOrInit")) {
+            if (!@hasDecl(SystemUart, "get_or_init")) {
                 // fallback to reinitializing the UART
                 return init(config);
             }
             return Self{
-                .internal = try SystemUart.getOrInit(config),
+                .internal = try SystemUart.get_or_init(config),
             };
         }
 
         pub fn can_read(self: Self) bool {
-            return self.internal.canRead();
+            return self.internal.can_read();
         }
 
         pub fn can_write(self: Self) bool {
-            return self.internal.canWrite();
+            return self.internal.can_write();
         }
 
         pub fn reader(self: Self) Reader {

From f8a506ccc28447ff6f20bba13ad04e7ce8d26318 Mon Sep 17 00:00:00 2001
From: Prince Bett <75972193+kodesafi@users.noreply.github.com>
Date: Mon, 6 Nov 2023 22:13:50 +0300
Subject: [PATCH 231/286] doc: add getting started tip (#156)

direct new users to microzig-examples for ease
the onboarding experience.
---
 README.adoc | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/README.adoc b/README.adoc
index 903b390b3..d21a7d264 100644
--- a/README.adoc
+++ b/README.adoc
@@ -29,6 +29,10 @@ This repo contains the infrastructure for getting started in an embedded Zig pro
 * device drivers for interacting with external hardware
 * an uncomplicated method to define xref:interrupts[interrupts]
 
+== Getting Started 
+
+Visit https://github.com/ZigEmbeddedGroup/microzig-examples to find examples for your specific board. 
+
 == Design
 
 For MicroZig internals please see the xref:docs/design.adoc[Design Document].

From c3baa4a2777634a2b5cd366b87b453e9b72b4b26 Mon Sep 17 00:00:00 2001
From: Jacob Young 
Date: Mon, 20 Nov 2023 12:48:34 -0800
Subject: [PATCH 232/286] Update dependencies and add paths (#158)

---
 build.zig.zon | 19 +++++++++++++++----
 1 file changed, 15 insertions(+), 4 deletions(-)

diff --git a/build.zig.zon b/build.zig.zon
index e790e7db7..a23790191 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -1,14 +1,25 @@
 .{
     .name = "microzig",
     .version = "0.1.0",
+    .paths = .{
+        "build.zig",
+        "build.zig.zon",
+        "design",
+        "docs",
+        "LICENSE",
+        "README.adoc",
+        "src",
+        "test",
+        "thoughts.md",
+    },
     .dependencies = .{
         .uf2 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/c523a4d23469282f95658a879f5ba925757dc9d9.tar.gz",
-            .hash = "12208530bdc194e8c1f3405ad681a409c7fabfe82735cd3972ec07c221a7786db03a",
+            .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/0550d4b1519264669b4ac5d944c370b41ebd6579.tar.gz",
+            .hash = "122058e26facbba3f6e06881ec0d356c7f9046e88edc46b9f244b50d366062528471",
         },
         .regz = .{
-            .url = "https://github.com/ZigEmbeddedGroup/regz/archive/b0ded63fc284da0ed9f4776eb7d1c4ad7175622d.tar.gz",
-            .hash = "1220e9299f949d3566a1dc4dd62caf82a06bb6c8ad5a693e62117b0941da9dc55ea2",
+            .url = "https://github.com/ZigEmbeddedGroup/regz/archive/d66ffd56f51fc46c071412141b5d0c74dc83c310.tar.gz",
+            .hash = "122002c5f2e31c11373ede6e8a8dd9a61aabd60d38df667ec33b5f994d1f0b503823",
         },
         .@"umm-zig" = .{
             .url = "https://github.com/ZigEmbeddedGroup/umm-zig/archive/99d815adfbc5cc4ad385dd765a6192f85e54179f.tar.gz",

From 8ac1db65743a79a6794a77c4d14a777388a1780f Mon Sep 17 00:00:00 2001
From: Sreehari Sreedev 
Date: Tue, 21 Nov 2023 16:19:54 -0700
Subject: [PATCH 233/286] packed struct => extern struct for USB (#159)

---
 src/core/usb.zig     | 12 ++++++------
 src/core/usb/hid.zig |  2 +-
 2 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/src/core/usb.zig b/src/core/usb.zig
index 3d76c3bad..a7b4e5643 100644
--- a/src/core/usb.zig
+++ b/src/core/usb.zig
@@ -511,7 +511,7 @@ pub const Dir = enum(u8) {
 };
 
 /// Describes an endpoint within an interface
-pub const EndpointDescriptor = packed struct {
+pub const EndpointDescriptor = extern struct {
     /// Length of this struct, must be 7.
     length: u8,
     /// Type of this descriptor, must be `Endpoint`.
@@ -542,7 +542,7 @@ pub const EndpointDescriptor = packed struct {
 };
 
 /// Description of an interface within a configuration.
-pub const InterfaceDescriptor = packed struct {
+pub const InterfaceDescriptor = extern struct {
     /// Length of this structure, must be 9.
     length: u8,
     /// Type of this descriptor, must be `Interface`.
@@ -580,7 +580,7 @@ pub const InterfaceDescriptor = packed struct {
 };
 
 /// Description of a single available device configuration.
-pub const ConfigurationDescriptor = packed struct {
+pub const ConfigurationDescriptor = extern struct {
     /// Length of this structure, must be 9.
     length: u8,
     /// Type of this descriptor, must be `Config`.
@@ -625,7 +625,7 @@ pub const ConfigurationDescriptor = packed struct {
 
 /// Describes a device. This is the most broad description in USB and is
 /// typically the first thing the host asks for.
-pub const DeviceDescriptor = packed struct {
+pub const DeviceDescriptor = extern struct {
     /// Length of this structure, must be 18.
     length: u8,
     /// Type of this descriptor, must be `Device`.
@@ -682,7 +682,7 @@ pub const DeviceDescriptor = packed struct {
 
 /// USB Device Qualifier Descriptor
 /// This descriptor is mostly the same as the DeviceDescriptor
-pub const DeviceQualifierDescriptor = packed struct {
+pub const DeviceQualifierDescriptor = extern struct {
     /// Length of this structure, must be 18.
     length: u8 = 10,
     /// Type of this descriptor, must be `Device`.
@@ -720,7 +720,7 @@ pub const DeviceQualifierDescriptor = packed struct {
 };
 
 /// Layout of an 8-byte USB SETUP packet.
-pub const SetupPacket = packed struct {
+pub const SetupPacket = extern struct {
     /// Request type; in practice, this is always either OUT (host-to-device) or
     /// IN (device-to-host), whose values are given in the `Dir` enum.
     request_type: u8,
diff --git a/src/core/usb/hid.zig b/src/core/usb/hid.zig
index e2c6d7f4b..c63e28aec 100644
--- a/src/core/usb/hid.zig
+++ b/src/core/usb/hid.zig
@@ -87,7 +87,7 @@ pub const DescType = enum(u8) {
 };
 
 /// USB HID descriptor
-pub const HidDescriptor = packed struct {
+pub const HidDescriptor = extern struct {
     length: u8 = 9,
     descriptor_type: DescType = DescType.Hid,
     /// Numeric expression identifying the HID Class Specification release

From 5e2fe60e2d1b04b6cd1a64f1d4e87f1341c5c6a9 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 21 Nov 2023 20:03:57 -0800
Subject: [PATCH 234/286] Initial commit

---
 README.md | 1 +
 1 file changed, 1 insertion(+)
 create mode 100644 README.md

diff --git a/README.md b/README.md
new file mode 100644
index 000000000..028ffa737
--- /dev/null
+++ b/README.md
@@ -0,0 +1 @@
+# microchip-atsam
\ No newline at end of file

From 6dcf11cd3096c6020d8880d90303824ddae57f2b Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 21 Nov 2023 20:18:13 -0800
Subject: [PATCH 235/286] initial commit

---
 .gitignore                  |     2 +
 LICENSE                     |    19 +
 README.md                   |     8 +-
 build.zig                   |    29 +
 src/chips/ATSAMD51J19A.atdf | 19800 ++++++++++++++++++++++++++++++++++
 5 files changed, 19857 insertions(+), 1 deletion(-)
 create mode 100644 .gitignore
 create mode 100644 LICENSE
 create mode 100644 build.zig
 create mode 100644 src/chips/ATSAMD51J19A.atdf

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 000000000..c26d4af28
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1,2 @@
+zig-out
+zig-cache
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 000000000..bcb425d88
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,19 @@
+Copyright (c) 2022 Zig Embedded Group Contributors
+
+This software is provided 'as-is', without any express or implied warranty. In
+no event will the authors be held liable for any damages arising from the use
+of this software.
+
+Permission is granted to anyone to use this software for any purpose, including
+commercial applications, and to alter it and redistribute it freely, subject to
+the following restrictions:
+
+1. The origin of this software must not be misrepresented; you must not claim
+that you wrote the original software. If you use this software in a product, an
+acknowledgment in the product documentation would be appreciated but is not
+required.
+
+2. Altered source versions must be plainly marked as such, and must not be
+misrepresented as being the original software.
+
+3. This notice may not be removed or altered from any source distribution.
diff --git a/README.md b/README.md
index 028ffa737..207183ee1 100644
--- a/README.md
+++ b/README.md
@@ -1 +1,7 @@
-# microchip-atsam
\ No newline at end of file
+# microchip-atsam
+
+HALs and register definitions for Microchip ATSAM devices
+
+## What version of Zig to use
+
+0.11.0
diff --git a/build.zig b/build.zig
new file mode 100644
index 000000000..75d493d1e
--- /dev/null
+++ b/build.zig
@@ -0,0 +1,29 @@
+const std = @import("std");
+
+pub fn build(b: *std.Build) void {
+    _ = b;
+    //  Dummy func to make package manager happy
+}
+
+fn root() []const u8 {
+    return comptime (std.fs.path.dirname(@src().file) orelse ".");
+}
+
+const build_root = root();
+
+pub const chips = struct {
+    pub const atsamd51j19 = .{
+        .name = "ATSAMD51J19A",
+        .url = "https://www.microchip.com/en-us/product/ATSAMD51J19A",
+        .cpu = .cortex_m4,
+        .register_definition = .{
+            .atdf = .{ .path = build_root ++ "src/chips/ATSAMD51J19A.atdf" },
+        },
+        .memory_regions = &.{
+            .{ .kind = .flash, .offset = 0x00004000, .length = 512 * 1024 }, // Embedded Flash
+            .{ .kind = .ram, .offset = 0x20000000, .length = 192 * 1024 }, // Embedded SRAM
+            .{ .kind = .ram, .offset = 0x47000000, .length = 8 * 1024 }, // Backup SRAM
+            .{ .kind = .flash, .offset = 0x00804000, .length = 512 }, // NVM User Row
+        },
+    };
+};
diff --git a/src/chips/ATSAMD51J19A.atdf b/src/chips/ATSAMD51J19A.atdf
new file mode 100644
index 000000000..b744b0edc
--- /dev/null
+++ b/src/chips/ATSAMD51J19A.atdf
@@ -0,0 +1,19800 @@
+
+
+
+   
+   
+      
+      
+      
+      
+      
+      
+      
+      
+   
+   
+      
+         
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+            
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+         
+         
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+            
+         
+         
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From 93ddffbcbe7a0b849cca610ee933210280d731b4 Mon Sep 17 00:00:00 2001
From: Matt Knight 
Date: Tue, 21 Nov 2023 20:20:21 -0800
Subject: [PATCH 236/286] fix path

---
 build.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/build.zig b/build.zig
index 75d493d1e..3cbb87b94 100644
--- a/build.zig
+++ b/build.zig
@@ -17,7 +17,7 @@ pub const chips = struct {
         .url = "https://www.microchip.com/en-us/product/ATSAMD51J19A",
         .cpu = .cortex_m4,
         .register_definition = .{
-            .atdf = .{ .path = build_root ++ "src/chips/ATSAMD51J19A.atdf" },
+            .atdf = .{ .path = build_root ++ "/src/chips/ATSAMD51J19A.atdf" },
         },
         .memory_regions = &.{
             .{ .kind = .flash, .offset = 0x00004000, .length = 512 * 1024 }, // Embedded Flash

From 57e4379062e396b354d70d5b924d5da2e8905bd4 Mon Sep 17 00:00:00 2001
From: Jacob Young 
Date: Tue, 28 Nov 2023 10:58:44 -0500
Subject: [PATCH 237/286] Update uf2 dependency (#160)

---
 build.zig.zon | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/build.zig.zon b/build.zig.zon
index a23790191..437acb5f9 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -14,8 +14,8 @@
     },
     .dependencies = .{
         .uf2 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/0550d4b1519264669b4ac5d944c370b41ebd6579.tar.gz",
-            .hash = "122058e26facbba3f6e06881ec0d356c7f9046e88edc46b9f244b50d366062528471",
+            .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/8037b439ccbac862471392b25e94a8995d784e2c.tar.gz",
+            .hash = "1220cc66563fc1ecefca7990968441dc9d4db717884ffa9a2de657f60ed4bb74a70a",
         },
         .regz = .{
             .url = "https://github.com/ZigEmbeddedGroup/regz/archive/d66ffd56f51fc46c071412141b5d0c74dc83c310.tar.gz",

From 6ddf91c60c42db3110695e02df3d530c4586892d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 08:40:20 +0100
Subject: [PATCH 238/286] initial empty commit


From a92518c99f0b6589b15ffce8654f5c4b8ef86a8c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 08:46:08 +0100
Subject: [PATCH 239/286] Moves microzig to core/

---
 LICENSE => core/LICENSE                             |   0
 README.adoc => core/README.adoc                     |   0
 build.zig => core/build.zig                         |   0
 build.zig.zon => core/build.zig.zon                 |   0
 {design => core/design}/logo-text-auto.svg          |   0
 {design => core/design}/logo-text-brightmode.svg    |   0
 {design => core/design}/logo-text-darkmode.svg      |   0
 {design => core/design}/logo-text-inkscape.svg      |   0
 {design => core/design}/logo.svg                    |   0
 {design => core/design}/social-media-preview.png    | Bin
 {design => core/design}/social-media-preview.xcf    | Bin
 {docs => core/docs}/design.adoc                     |   0
 {docs => core/docs}/hardware_support_packages.adoc  |   0
 {docs => core/docs}/images/deps.dot                 |   0
 {docs => core/docs}/images/deps.svg                 |   0
 {docs => core/docs}/tricks.adoc                     |   0
 {src => core/src}/core.zig                          |   0
 {src => core/src}/core/experimental.zig             |   0
 {src => core/src}/core/experimental/clock.zig       |   0
 {src => core/src}/core/experimental/debug.zig       |   0
 {src => core/src}/core/experimental/gpio.zig        |   0
 {src => core/src}/core/experimental/i2c.zig         |   0
 {src => core/src}/core/experimental/pin.zig         |   0
 {src => core/src}/core/experimental/spi.zig         |   0
 {src => core/src}/core/experimental/uart.zig        |   0
 {src => core/src}/core/heap.zig                     |   0
 {src => core/src}/core/usb.zig                      |   0
 {src => core/src}/core/usb/hid.zig                  |   0
 {src => core/src}/cpus/avr5.zig                     |   0
 {src => core/src}/cpus/cortex-m.zig                 |   0
 {src => core/src}/cpus/riscv32.zig                  |   0
 {src => core/src}/drivers.zig                       |   0
 {src => core/src}/drivers/experimental.zig          |   0
 {src => core/src}/drivers/experimental/button.zig   |   0
 .../src}/drivers/experimental/quadrature.zig        |   0
 {src => core/src}/interrupt.zig                     |   0
 {src => core/src}/microzig.zig                      |   0
 {src => core/src}/mmio.zig                          |   0
 {src => core/src}/start.zig                         |   0
 {test => core/test}/README.adoc                     |   0
 {test => core/test}/backings.zig                    |   0
 {test => core/test}/board.zig                       |   0
 {test => core/test}/chip.zig                        |   0
 {test => core/test}/cpu.zig                         |   0
 {test => core/test}/hal.zig                         |   0
 {test => core/test}/programs/blinky.zig             |   0
 {test => core/test}/programs/has_board.zig          |   0
 {test => core/test}/programs/has_dependencies.zig   |   0
 {test => core/test}/programs/has_hal.zig            |   0
 {test => core/test}/programs/interrupt.zig          |   0
 {test => core/test}/programs/minimal.zig            |   0
 {test => core/test}/programs/uart-sync.zig          |   0
 thoughts.md => core/thoughts.md                     |   0
 53 files changed, 0 insertions(+), 0 deletions(-)
 rename LICENSE => core/LICENSE (100%)
 rename README.adoc => core/README.adoc (100%)
 rename build.zig => core/build.zig (100%)
 rename build.zig.zon => core/build.zig.zon (100%)
 rename {design => core/design}/logo-text-auto.svg (100%)
 rename {design => core/design}/logo-text-brightmode.svg (100%)
 rename {design => core/design}/logo-text-darkmode.svg (100%)
 rename {design => core/design}/logo-text-inkscape.svg (100%)
 rename {design => core/design}/logo.svg (100%)
 rename {design => core/design}/social-media-preview.png (100%)
 rename {design => core/design}/social-media-preview.xcf (100%)
 rename {docs => core/docs}/design.adoc (100%)
 rename {docs => core/docs}/hardware_support_packages.adoc (100%)
 rename {docs => core/docs}/images/deps.dot (100%)
 rename {docs => core/docs}/images/deps.svg (100%)
 rename {docs => core/docs}/tricks.adoc (100%)
 rename {src => core/src}/core.zig (100%)
 rename {src => core/src}/core/experimental.zig (100%)
 rename {src => core/src}/core/experimental/clock.zig (100%)
 rename {src => core/src}/core/experimental/debug.zig (100%)
 rename {src => core/src}/core/experimental/gpio.zig (100%)
 rename {src => core/src}/core/experimental/i2c.zig (100%)
 rename {src => core/src}/core/experimental/pin.zig (100%)
 rename {src => core/src}/core/experimental/spi.zig (100%)
 rename {src => core/src}/core/experimental/uart.zig (100%)
 rename {src => core/src}/core/heap.zig (100%)
 rename {src => core/src}/core/usb.zig (100%)
 rename {src => core/src}/core/usb/hid.zig (100%)
 rename {src => core/src}/cpus/avr5.zig (100%)
 rename {src => core/src}/cpus/cortex-m.zig (100%)
 rename {src => core/src}/cpus/riscv32.zig (100%)
 rename {src => core/src}/drivers.zig (100%)
 rename {src => core/src}/drivers/experimental.zig (100%)
 rename {src => core/src}/drivers/experimental/button.zig (100%)
 rename {src => core/src}/drivers/experimental/quadrature.zig (100%)
 rename {src => core/src}/interrupt.zig (100%)
 rename {src => core/src}/microzig.zig (100%)
 rename {src => core/src}/mmio.zig (100%)
 rename {src => core/src}/start.zig (100%)
 rename {test => core/test}/README.adoc (100%)
 rename {test => core/test}/backings.zig (100%)
 rename {test => core/test}/board.zig (100%)
 rename {test => core/test}/chip.zig (100%)
 rename {test => core/test}/cpu.zig (100%)
 rename {test => core/test}/hal.zig (100%)
 rename {test => core/test}/programs/blinky.zig (100%)
 rename {test => core/test}/programs/has_board.zig (100%)
 rename {test => core/test}/programs/has_dependencies.zig (100%)
 rename {test => core/test}/programs/has_hal.zig (100%)
 rename {test => core/test}/programs/interrupt.zig (100%)
 rename {test => core/test}/programs/minimal.zig (100%)
 rename {test => core/test}/programs/uart-sync.zig (100%)
 rename thoughts.md => core/thoughts.md (100%)

diff --git a/LICENSE b/core/LICENSE
similarity index 100%
rename from LICENSE
rename to core/LICENSE
diff --git a/README.adoc b/core/README.adoc
similarity index 100%
rename from README.adoc
rename to core/README.adoc
diff --git a/build.zig b/core/build.zig
similarity index 100%
rename from build.zig
rename to core/build.zig
diff --git a/build.zig.zon b/core/build.zig.zon
similarity index 100%
rename from build.zig.zon
rename to core/build.zig.zon
diff --git a/design/logo-text-auto.svg b/core/design/logo-text-auto.svg
similarity index 100%
rename from design/logo-text-auto.svg
rename to core/design/logo-text-auto.svg
diff --git a/design/logo-text-brightmode.svg b/core/design/logo-text-brightmode.svg
similarity index 100%
rename from design/logo-text-brightmode.svg
rename to core/design/logo-text-brightmode.svg
diff --git a/design/logo-text-darkmode.svg b/core/design/logo-text-darkmode.svg
similarity index 100%
rename from design/logo-text-darkmode.svg
rename to core/design/logo-text-darkmode.svg
diff --git a/design/logo-text-inkscape.svg b/core/design/logo-text-inkscape.svg
similarity index 100%
rename from design/logo-text-inkscape.svg
rename to core/design/logo-text-inkscape.svg
diff --git a/design/logo.svg b/core/design/logo.svg
similarity index 100%
rename from design/logo.svg
rename to core/design/logo.svg
diff --git a/design/social-media-preview.png b/core/design/social-media-preview.png
similarity index 100%
rename from design/social-media-preview.png
rename to core/design/social-media-preview.png
diff --git a/design/social-media-preview.xcf b/core/design/social-media-preview.xcf
similarity index 100%
rename from design/social-media-preview.xcf
rename to core/design/social-media-preview.xcf
diff --git a/docs/design.adoc b/core/docs/design.adoc
similarity index 100%
rename from docs/design.adoc
rename to core/docs/design.adoc
diff --git a/docs/hardware_support_packages.adoc b/core/docs/hardware_support_packages.adoc
similarity index 100%
rename from docs/hardware_support_packages.adoc
rename to core/docs/hardware_support_packages.adoc
diff --git a/docs/images/deps.dot b/core/docs/images/deps.dot
similarity index 100%
rename from docs/images/deps.dot
rename to core/docs/images/deps.dot
diff --git a/docs/images/deps.svg b/core/docs/images/deps.svg
similarity index 100%
rename from docs/images/deps.svg
rename to core/docs/images/deps.svg
diff --git a/docs/tricks.adoc b/core/docs/tricks.adoc
similarity index 100%
rename from docs/tricks.adoc
rename to core/docs/tricks.adoc
diff --git a/src/core.zig b/core/src/core.zig
similarity index 100%
rename from src/core.zig
rename to core/src/core.zig
diff --git a/src/core/experimental.zig b/core/src/core/experimental.zig
similarity index 100%
rename from src/core/experimental.zig
rename to core/src/core/experimental.zig
diff --git a/src/core/experimental/clock.zig b/core/src/core/experimental/clock.zig
similarity index 100%
rename from src/core/experimental/clock.zig
rename to core/src/core/experimental/clock.zig
diff --git a/src/core/experimental/debug.zig b/core/src/core/experimental/debug.zig
similarity index 100%
rename from src/core/experimental/debug.zig
rename to core/src/core/experimental/debug.zig
diff --git a/src/core/experimental/gpio.zig b/core/src/core/experimental/gpio.zig
similarity index 100%
rename from src/core/experimental/gpio.zig
rename to core/src/core/experimental/gpio.zig
diff --git a/src/core/experimental/i2c.zig b/core/src/core/experimental/i2c.zig
similarity index 100%
rename from src/core/experimental/i2c.zig
rename to core/src/core/experimental/i2c.zig
diff --git a/src/core/experimental/pin.zig b/core/src/core/experimental/pin.zig
similarity index 100%
rename from src/core/experimental/pin.zig
rename to core/src/core/experimental/pin.zig
diff --git a/src/core/experimental/spi.zig b/core/src/core/experimental/spi.zig
similarity index 100%
rename from src/core/experimental/spi.zig
rename to core/src/core/experimental/spi.zig
diff --git a/src/core/experimental/uart.zig b/core/src/core/experimental/uart.zig
similarity index 100%
rename from src/core/experimental/uart.zig
rename to core/src/core/experimental/uart.zig
diff --git a/src/core/heap.zig b/core/src/core/heap.zig
similarity index 100%
rename from src/core/heap.zig
rename to core/src/core/heap.zig
diff --git a/src/core/usb.zig b/core/src/core/usb.zig
similarity index 100%
rename from src/core/usb.zig
rename to core/src/core/usb.zig
diff --git a/src/core/usb/hid.zig b/core/src/core/usb/hid.zig
similarity index 100%
rename from src/core/usb/hid.zig
rename to core/src/core/usb/hid.zig
diff --git a/src/cpus/avr5.zig b/core/src/cpus/avr5.zig
similarity index 100%
rename from src/cpus/avr5.zig
rename to core/src/cpus/avr5.zig
diff --git a/src/cpus/cortex-m.zig b/core/src/cpus/cortex-m.zig
similarity index 100%
rename from src/cpus/cortex-m.zig
rename to core/src/cpus/cortex-m.zig
diff --git a/src/cpus/riscv32.zig b/core/src/cpus/riscv32.zig
similarity index 100%
rename from src/cpus/riscv32.zig
rename to core/src/cpus/riscv32.zig
diff --git a/src/drivers.zig b/core/src/drivers.zig
similarity index 100%
rename from src/drivers.zig
rename to core/src/drivers.zig
diff --git a/src/drivers/experimental.zig b/core/src/drivers/experimental.zig
similarity index 100%
rename from src/drivers/experimental.zig
rename to core/src/drivers/experimental.zig
diff --git a/src/drivers/experimental/button.zig b/core/src/drivers/experimental/button.zig
similarity index 100%
rename from src/drivers/experimental/button.zig
rename to core/src/drivers/experimental/button.zig
diff --git a/src/drivers/experimental/quadrature.zig b/core/src/drivers/experimental/quadrature.zig
similarity index 100%
rename from src/drivers/experimental/quadrature.zig
rename to core/src/drivers/experimental/quadrature.zig
diff --git a/src/interrupt.zig b/core/src/interrupt.zig
similarity index 100%
rename from src/interrupt.zig
rename to core/src/interrupt.zig
diff --git a/src/microzig.zig b/core/src/microzig.zig
similarity index 100%
rename from src/microzig.zig
rename to core/src/microzig.zig
diff --git a/src/mmio.zig b/core/src/mmio.zig
similarity index 100%
rename from src/mmio.zig
rename to core/src/mmio.zig
diff --git a/src/start.zig b/core/src/start.zig
similarity index 100%
rename from src/start.zig
rename to core/src/start.zig
diff --git a/test/README.adoc b/core/test/README.adoc
similarity index 100%
rename from test/README.adoc
rename to core/test/README.adoc
diff --git a/test/backings.zig b/core/test/backings.zig
similarity index 100%
rename from test/backings.zig
rename to core/test/backings.zig
diff --git a/test/board.zig b/core/test/board.zig
similarity index 100%
rename from test/board.zig
rename to core/test/board.zig
diff --git a/test/chip.zig b/core/test/chip.zig
similarity index 100%
rename from test/chip.zig
rename to core/test/chip.zig
diff --git a/test/cpu.zig b/core/test/cpu.zig
similarity index 100%
rename from test/cpu.zig
rename to core/test/cpu.zig
diff --git a/test/hal.zig b/core/test/hal.zig
similarity index 100%
rename from test/hal.zig
rename to core/test/hal.zig
diff --git a/test/programs/blinky.zig b/core/test/programs/blinky.zig
similarity index 100%
rename from test/programs/blinky.zig
rename to core/test/programs/blinky.zig
diff --git a/test/programs/has_board.zig b/core/test/programs/has_board.zig
similarity index 100%
rename from test/programs/has_board.zig
rename to core/test/programs/has_board.zig
diff --git a/test/programs/has_dependencies.zig b/core/test/programs/has_dependencies.zig
similarity index 100%
rename from test/programs/has_dependencies.zig
rename to core/test/programs/has_dependencies.zig
diff --git a/test/programs/has_hal.zig b/core/test/programs/has_hal.zig
similarity index 100%
rename from test/programs/has_hal.zig
rename to core/test/programs/has_hal.zig
diff --git a/test/programs/interrupt.zig b/core/test/programs/interrupt.zig
similarity index 100%
rename from test/programs/interrupt.zig
rename to core/test/programs/interrupt.zig
diff --git a/test/programs/minimal.zig b/core/test/programs/minimal.zig
similarity index 100%
rename from test/programs/minimal.zig
rename to core/test/programs/minimal.zig
diff --git a/test/programs/uart-sync.zig b/core/test/programs/uart-sync.zig
similarity index 100%
rename from test/programs/uart-sync.zig
rename to core/test/programs/uart-sync.zig
diff --git a/thoughts.md b/core/thoughts.md
similarity index 100%
rename from thoughts.md
rename to core/thoughts.md

From 6fcd0baa24328fdf0a7e445db413a57cdfdbfab0 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 08:49:17 +0100
Subject: [PATCH 240/286] Moves raspberrypi-rp2040 to
 board-support/raspberrypi-rp2040

---
 LICENSE => board-support/raspberrypi-rp2040/LICENSE               | 0
 README.adoc => board-support/raspberrypi-rp2040/README.adoc       | 0
 build.zig => board-support/raspberrypi-rp2040/build.zig           | 0
 build.zig.zon => board-support/raspberrypi-rp2040/build.zig.zon   | 0
 {examples => board-support/raspberrypi-rp2040/examples}/adc.zig   | 0
 .../raspberrypi-rp2040/examples}/blinky.zig                       | 0
 .../raspberrypi-rp2040/examples}/blinky_core1.zig                 | 0
 .../raspberrypi-rp2040/examples}/flash_program.zig                | 0
 .../raspberrypi-rp2040/examples}/gpio_clk.zig                     | 0
 .../raspberrypi-rp2040/examples}/i2c_bus_scan.zig                 | 0
 {examples => board-support/raspberrypi-rp2040/examples}/pwm.zig   | 0
 .../raspberrypi-rp2040/examples}/random.zig                       | 0
 .../raspberrypi-rp2040/examples}/scripts/hid_test.py              | 0
 .../raspberrypi-rp2040/examples}/scripts/usb_device_loopback.py   | 0
 .../raspberrypi-rp2040/examples}/spi_master.zig                   | 0
 .../raspberrypi-rp2040/examples}/squarewave.zig                   | 0
 {examples => board-support/raspberrypi-rp2040/examples}/uart.zig  | 0
 .../raspberrypi-rp2040/examples}/usb_device.zig                   | 0
 .../raspberrypi-rp2040/examples}/usb_hid.zig                      | 0
 .../raspberrypi-rp2040/examples}/ws2812.zig                       | 0
 rp2040.ld => board-support/raspberrypi-rp2040/rp2040.ld           | 0
 .../raspberrypi-rp2040/src}/boards/raspberry_pi_pico.zig          | 0
 .../raspberrypi-rp2040/src}/boards/shared/bootrom.zig             | 0
 .../raspberrypi-rp2040/src}/boards/waveshare_rp2040_eth.zig       | 0
 .../raspberrypi-rp2040/src}/boards/waveshare_rp2040_matrix.zig    | 0
 .../raspberrypi-rp2040/src}/boards/waveshare_rp2040_plus_16m.zig  | 0
 .../raspberrypi-rp2040/src}/boards/waveshare_rp2040_plus_4m.zig   | 0
 .../raspberrypi-rp2040/src}/bootroms/at25sf128a.S                 | 0
 .../raspberrypi-rp2040/src}/bootroms/generic_03h.S                | 0
 .../raspberrypi-rp2040/src}/bootroms/is25lp080.S                  | 0
 {src => board-support/raspberrypi-rp2040/src}/bootroms/legacy.S   | 0
 .../raspberrypi-rp2040/src}/bootroms/shared/addressmap.h          | 0
 .../raspberrypi-rp2040/src}/bootroms/shared/asm_helper.S          | 0
 .../raspberrypi-rp2040/src}/bootroms/shared/exit_from_boot2.S     | 0
 .../raspberrypi-rp2040/src}/bootroms/shared/m0plus.h              | 0
 .../raspberrypi-rp2040/src}/bootroms/shared/pads_qspi.h           | 0
 .../raspberrypi-rp2040/src}/bootroms/shared/read_flash_sreg.S     | 0
 .../raspberrypi-rp2040/src}/bootroms/shared/regs.h                | 0
 .../raspberrypi-rp2040/src}/bootroms/shared/ssi.h                 | 0
 .../raspberrypi-rp2040/src}/bootroms/shared/stage2.ld             | 0
 .../raspberrypi-rp2040/src}/bootroms/shared/wait_ssi_ready.S      | 0
 {src => board-support/raspberrypi-rp2040/src}/bootroms/w25q080.S  | 0
 .../raspberrypi-rp2040/src}/bootroms/w25q32jvssiq.S               | 0
 {src => board-support/raspberrypi-rp2040/src}/bootroms/w25x10cl.S | 0
 {src => board-support/raspberrypi-rp2040/src}/chips/RP2040.json   | 0
 {src => board-support/raspberrypi-rp2040/src}/hal.zig             | 0
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diff --git a/src/hal/pio/assembler/comparison_tests/resistor_dac.pio b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/resistor_dac.pio
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/resistor_dac.pio
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/resistor_dac.pio
diff --git a/src/hal/pio/assembler/comparison_tests/resistor_dac.pio.h b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/resistor_dac.pio.h
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/resistor_dac.pio.h
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/resistor_dac.pio.h
diff --git a/src/hal/pio/assembler/comparison_tests/spi.pio b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/spi.pio
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/spi.pio
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/spi.pio
diff --git a/src/hal/pio/assembler/comparison_tests/spi.pio.h b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/spi.pio.h
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/spi.pio.h
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/spi.pio.h
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave.pio b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave.pio
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/squarewave.pio
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave.pio
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave.pio.h b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave.pio.h
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/squarewave.pio.h
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave.pio.h
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/squarewave_fast.pio
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio.h b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio.h
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/squarewave_fast.pio.h
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave_fast.pio.h
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave_test.pio b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave_test.pio
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/squarewave_test.pio
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave_test.pio
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio
diff --git a/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio.h b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio.h
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio.h
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/squarewave_wrap.pio.h
diff --git a/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/st7789_lcd.pio
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio
diff --git a/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio.h b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio.h
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/st7789_lcd.pio.h
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/st7789_lcd.pio.h
diff --git a/src/hal/pio/assembler/comparison_tests/uart_rx.pio b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/uart_rx.pio
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/uart_rx.pio
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/uart_rx.pio
diff --git a/src/hal/pio/assembler/comparison_tests/uart_rx.pio.h b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/uart_rx.pio.h
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/uart_rx.pio.h
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/uart_rx.pio.h
diff --git a/src/hal/pio/assembler/comparison_tests/uart_tx.pio b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/uart_tx.pio
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/uart_tx.pio
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/uart_tx.pio
diff --git a/src/hal/pio/assembler/comparison_tests/uart_tx.pio.h b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/uart_tx.pio.h
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/uart_tx.pio.h
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/uart_tx.pio.h
diff --git a/src/hal/pio/assembler/comparison_tests/ws2812.pio b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/ws2812.pio
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/ws2812.pio
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/ws2812.pio
diff --git a/src/hal/pio/assembler/comparison_tests/ws2812.pio.h b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/ws2812.pio.h
similarity index 100%
rename from src/hal/pio/assembler/comparison_tests/ws2812.pio.h
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/comparison_tests/ws2812.pio.h
diff --git a/src/hal/pio/assembler/encoder.zig b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/encoder.zig
similarity index 100%
rename from src/hal/pio/assembler/encoder.zig
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/encoder.zig
diff --git a/src/hal/pio/assembler/tokenizer.zig b/board-support/raspberrypi-rp2040/src/hal/pio/assembler/tokenizer.zig
similarity index 100%
rename from src/hal/pio/assembler/tokenizer.zig
rename to board-support/raspberrypi-rp2040/src/hal/pio/assembler/tokenizer.zig
diff --git a/src/hal/pll.zig b/board-support/raspberrypi-rp2040/src/hal/pll.zig
similarity index 100%
rename from src/hal/pll.zig
rename to board-support/raspberrypi-rp2040/src/hal/pll.zig
diff --git a/src/hal/pwm.zig b/board-support/raspberrypi-rp2040/src/hal/pwm.zig
similarity index 100%
rename from src/hal/pwm.zig
rename to board-support/raspberrypi-rp2040/src/hal/pwm.zig
diff --git a/src/hal/random.zig b/board-support/raspberrypi-rp2040/src/hal/random.zig
similarity index 100%
rename from src/hal/random.zig
rename to board-support/raspberrypi-rp2040/src/hal/random.zig
diff --git a/src/hal/resets.zig b/board-support/raspberrypi-rp2040/src/hal/resets.zig
similarity index 100%
rename from src/hal/resets.zig
rename to board-support/raspberrypi-rp2040/src/hal/resets.zig
diff --git a/src/hal/rom.zig b/board-support/raspberrypi-rp2040/src/hal/rom.zig
similarity index 100%
rename from src/hal/rom.zig
rename to board-support/raspberrypi-rp2040/src/hal/rom.zig
diff --git a/src/hal/spi.zig b/board-support/raspberrypi-rp2040/src/hal/spi.zig
similarity index 100%
rename from src/hal/spi.zig
rename to board-support/raspberrypi-rp2040/src/hal/spi.zig
diff --git a/src/hal/time.zig b/board-support/raspberrypi-rp2040/src/hal/time.zig
similarity index 100%
rename from src/hal/time.zig
rename to board-support/raspberrypi-rp2040/src/hal/time.zig
diff --git a/src/hal/uart.zig b/board-support/raspberrypi-rp2040/src/hal/uart.zig
similarity index 100%
rename from src/hal/uart.zig
rename to board-support/raspberrypi-rp2040/src/hal/uart.zig
diff --git a/src/hal/usb.zig b/board-support/raspberrypi-rp2040/src/hal/usb.zig
similarity index 100%
rename from src/hal/usb.zig
rename to board-support/raspberrypi-rp2040/src/hal/usb.zig
diff --git a/tools/rp2040-flash.zig b/board-support/raspberrypi-rp2040/tools/rp2040-flash.zig
similarity index 100%
rename from tools/rp2040-flash.zig
rename to board-support/raspberrypi-rp2040/tools/rp2040-flash.zig

From 4ba6016ea0cf4f28779fe3dd57b1441ab09a4a70 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 08:51:05 +0100
Subject: [PATCH 241/286] moves stmicro-stm32 to board-support

---
 .buildkite/pipeline.yml                                     | 6 ------
 LICENSE => board-support/stmicro-stm32/LICENSE              | 0
 README.adoc => board-support/stmicro-stm32/README.adoc      | 0
 build.zig => board-support/stmicro-stm32/build.zig          | 0
 .../stmicro-stm32/src}/boards/STM3240G_EVAL.zig             | 0
 .../stmicro-stm32/src}/boards/STM32F3DISCOVERY.zig          | 0
 .../stmicro-stm32/src}/boards/STM32F429IDISCOVERY.zig       | 0
 .../stmicro-stm32/src}/boards/STM32F4DISCOVERY.zig          | 0
 .../stmicro-stm32/src}/chips/STM32F103.json                 | 0
 .../stmicro-stm32/src}/chips/STM32F303.json                 | 0
 .../stmicro-stm32/src}/chips/STM32F407.json                 | 0
 .../stmicro-stm32/src}/chips/STM32F429.json                 | 0
 .../stmicro-stm32/src}/chips/STM32L0x1.svd                  | 0
 .../stmicro-stm32/src}/chips/STM32L0x2.svd                  | 0
 .../stmicro-stm32/src}/chips/STM32L0x3.svd                  | 0
 {src => board-support/stmicro-stm32/src}/hals/STM32F103.zig | 0
 .../stmicro-stm32/src}/hals/STM32F103/gpio.zig              | 0
 .../stmicro-stm32/src}/hals/STM32F103/hal.zig               | 0
 .../stmicro-stm32/src}/hals/STM32F103/pins.zig              | 0
 {src => board-support/stmicro-stm32/src}/hals/STM32F303.zig | 0
 {src => board-support/stmicro-stm32/src}/hals/STM32F407.zig | 0
 {src => board-support/stmicro-stm32/src}/hals/STM32F429.zig | 0
 .../stmicro-stm32/test}/programs/minimal.zig                | 0
 {test => board-support/stmicro-stm32/test}/stm32f103.robot  | 0
 deps/microzig                                               | 1 -
 25 files changed, 7 deletions(-)
 delete mode 100644 .buildkite/pipeline.yml
 rename LICENSE => board-support/stmicro-stm32/LICENSE (100%)
 rename README.adoc => board-support/stmicro-stm32/README.adoc (100%)
 rename build.zig => board-support/stmicro-stm32/build.zig (100%)
 rename {src => board-support/stmicro-stm32/src}/boards/STM3240G_EVAL.zig (100%)
 rename {src => board-support/stmicro-stm32/src}/boards/STM32F3DISCOVERY.zig (100%)
 rename {src => board-support/stmicro-stm32/src}/boards/STM32F429IDISCOVERY.zig (100%)
 rename {src => board-support/stmicro-stm32/src}/boards/STM32F4DISCOVERY.zig (100%)
 rename {src => board-support/stmicro-stm32/src}/chips/STM32F103.json (100%)
 rename {src => board-support/stmicro-stm32/src}/chips/STM32F303.json (100%)
 rename {src => board-support/stmicro-stm32/src}/chips/STM32F407.json (100%)
 rename {src => board-support/stmicro-stm32/src}/chips/STM32F429.json (100%)
 rename {src => board-support/stmicro-stm32/src}/chips/STM32L0x1.svd (100%)
 rename {src => board-support/stmicro-stm32/src}/chips/STM32L0x2.svd (100%)
 rename {src => board-support/stmicro-stm32/src}/chips/STM32L0x3.svd (100%)
 rename {src => board-support/stmicro-stm32/src}/hals/STM32F103.zig (100%)
 rename {src => board-support/stmicro-stm32/src}/hals/STM32F103/gpio.zig (100%)
 rename {src => board-support/stmicro-stm32/src}/hals/STM32F103/hal.zig (100%)
 rename {src => board-support/stmicro-stm32/src}/hals/STM32F103/pins.zig (100%)
 rename {src => board-support/stmicro-stm32/src}/hals/STM32F303.zig (100%)
 rename {src => board-support/stmicro-stm32/src}/hals/STM32F407.zig (100%)
 rename {src => board-support/stmicro-stm32/src}/hals/STM32F429.zig (100%)
 rename {test => board-support/stmicro-stm32/test}/programs/minimal.zig (100%)
 rename {test => board-support/stmicro-stm32/test}/stm32f103.robot (100%)
 delete mode 160000 deps/microzig

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
deleted file mode 100644
index ad6d38054..000000000
--- a/.buildkite/pipeline.yml
+++ /dev/null
@@ -1,6 +0,0 @@
-steps:
-  - group: Build and Test
-    steps:
-    - command: zig build
-    - label: 🔨 Test
-      command: renode-test test/stm32f103.robot
diff --git a/LICENSE b/board-support/stmicro-stm32/LICENSE
similarity index 100%
rename from LICENSE
rename to board-support/stmicro-stm32/LICENSE
diff --git a/README.adoc b/board-support/stmicro-stm32/README.adoc
similarity index 100%
rename from README.adoc
rename to board-support/stmicro-stm32/README.adoc
diff --git a/build.zig b/board-support/stmicro-stm32/build.zig
similarity index 100%
rename from build.zig
rename to board-support/stmicro-stm32/build.zig
diff --git a/src/boards/STM3240G_EVAL.zig b/board-support/stmicro-stm32/src/boards/STM3240G_EVAL.zig
similarity index 100%
rename from src/boards/STM3240G_EVAL.zig
rename to board-support/stmicro-stm32/src/boards/STM3240G_EVAL.zig
diff --git a/src/boards/STM32F3DISCOVERY.zig b/board-support/stmicro-stm32/src/boards/STM32F3DISCOVERY.zig
similarity index 100%
rename from src/boards/STM32F3DISCOVERY.zig
rename to board-support/stmicro-stm32/src/boards/STM32F3DISCOVERY.zig
diff --git a/src/boards/STM32F429IDISCOVERY.zig b/board-support/stmicro-stm32/src/boards/STM32F429IDISCOVERY.zig
similarity index 100%
rename from src/boards/STM32F429IDISCOVERY.zig
rename to board-support/stmicro-stm32/src/boards/STM32F429IDISCOVERY.zig
diff --git a/src/boards/STM32F4DISCOVERY.zig b/board-support/stmicro-stm32/src/boards/STM32F4DISCOVERY.zig
similarity index 100%
rename from src/boards/STM32F4DISCOVERY.zig
rename to board-support/stmicro-stm32/src/boards/STM32F4DISCOVERY.zig
diff --git a/src/chips/STM32F103.json b/board-support/stmicro-stm32/src/chips/STM32F103.json
similarity index 100%
rename from src/chips/STM32F103.json
rename to board-support/stmicro-stm32/src/chips/STM32F103.json
diff --git a/src/chips/STM32F303.json b/board-support/stmicro-stm32/src/chips/STM32F303.json
similarity index 100%
rename from src/chips/STM32F303.json
rename to board-support/stmicro-stm32/src/chips/STM32F303.json
diff --git a/src/chips/STM32F407.json b/board-support/stmicro-stm32/src/chips/STM32F407.json
similarity index 100%
rename from src/chips/STM32F407.json
rename to board-support/stmicro-stm32/src/chips/STM32F407.json
diff --git a/src/chips/STM32F429.json b/board-support/stmicro-stm32/src/chips/STM32F429.json
similarity index 100%
rename from src/chips/STM32F429.json
rename to board-support/stmicro-stm32/src/chips/STM32F429.json
diff --git a/src/chips/STM32L0x1.svd b/board-support/stmicro-stm32/src/chips/STM32L0x1.svd
similarity index 100%
rename from src/chips/STM32L0x1.svd
rename to board-support/stmicro-stm32/src/chips/STM32L0x1.svd
diff --git a/src/chips/STM32L0x2.svd b/board-support/stmicro-stm32/src/chips/STM32L0x2.svd
similarity index 100%
rename from src/chips/STM32L0x2.svd
rename to board-support/stmicro-stm32/src/chips/STM32L0x2.svd
diff --git a/src/chips/STM32L0x3.svd b/board-support/stmicro-stm32/src/chips/STM32L0x3.svd
similarity index 100%
rename from src/chips/STM32L0x3.svd
rename to board-support/stmicro-stm32/src/chips/STM32L0x3.svd
diff --git a/src/hals/STM32F103.zig b/board-support/stmicro-stm32/src/hals/STM32F103.zig
similarity index 100%
rename from src/hals/STM32F103.zig
rename to board-support/stmicro-stm32/src/hals/STM32F103.zig
diff --git a/src/hals/STM32F103/gpio.zig b/board-support/stmicro-stm32/src/hals/STM32F103/gpio.zig
similarity index 100%
rename from src/hals/STM32F103/gpio.zig
rename to board-support/stmicro-stm32/src/hals/STM32F103/gpio.zig
diff --git a/src/hals/STM32F103/hal.zig b/board-support/stmicro-stm32/src/hals/STM32F103/hal.zig
similarity index 100%
rename from src/hals/STM32F103/hal.zig
rename to board-support/stmicro-stm32/src/hals/STM32F103/hal.zig
diff --git a/src/hals/STM32F103/pins.zig b/board-support/stmicro-stm32/src/hals/STM32F103/pins.zig
similarity index 100%
rename from src/hals/STM32F103/pins.zig
rename to board-support/stmicro-stm32/src/hals/STM32F103/pins.zig
diff --git a/src/hals/STM32F303.zig b/board-support/stmicro-stm32/src/hals/STM32F303.zig
similarity index 100%
rename from src/hals/STM32F303.zig
rename to board-support/stmicro-stm32/src/hals/STM32F303.zig
diff --git a/src/hals/STM32F407.zig b/board-support/stmicro-stm32/src/hals/STM32F407.zig
similarity index 100%
rename from src/hals/STM32F407.zig
rename to board-support/stmicro-stm32/src/hals/STM32F407.zig
diff --git a/src/hals/STM32F429.zig b/board-support/stmicro-stm32/src/hals/STM32F429.zig
similarity index 100%
rename from src/hals/STM32F429.zig
rename to board-support/stmicro-stm32/src/hals/STM32F429.zig
diff --git a/test/programs/minimal.zig b/board-support/stmicro-stm32/test/programs/minimal.zig
similarity index 100%
rename from test/programs/minimal.zig
rename to board-support/stmicro-stm32/test/programs/minimal.zig
diff --git a/test/stm32f103.robot b/board-support/stmicro-stm32/test/stm32f103.robot
similarity index 100%
rename from test/stm32f103.robot
rename to board-support/stmicro-stm32/test/stm32f103.robot
diff --git a/deps/microzig b/deps/microzig
deleted file mode 160000
index 9392fe0f7..000000000
--- a/deps/microzig
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 9392fe0f7bddde26155c181ab80b70097b49c791

From c99eb4e1e48bc0f50a9530fee50c1df3c8f2b369 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 08:52:14 +0100
Subject: [PATCH 242/286] Moves nxp to board-support/nxp-lpc

---
 .buildkite/pipeline.yml                                    | 4 ----
 LICENSE => board-support/nxp-lpc/LICENSE                   | 0
 README.adoc => board-support/nxp-lpc/README.adoc           | 0
 build.zig => board-support/nxp-lpc/build.zig               | 0
 {src => board-support/nxp-lpc/src}/boards/mbed_LPC1768.zig | 0
 {src => board-support/nxp-lpc/src}/chips/LPC176x5x.json    | 0
 {src => board-support/nxp-lpc/src}/hals/LPC176x5x.zig      | 0
 {src => board-support/nxp-lpc/src}/tools/patchelf.zig      | 0
 {test => board-support/nxp-lpc/test}/programs/minimal.zig  | 0
 9 files changed, 4 deletions(-)
 delete mode 100644 .buildkite/pipeline.yml
 rename LICENSE => board-support/nxp-lpc/LICENSE (100%)
 rename README.adoc => board-support/nxp-lpc/README.adoc (100%)
 rename build.zig => board-support/nxp-lpc/build.zig (100%)
 rename {src => board-support/nxp-lpc/src}/boards/mbed_LPC1768.zig (100%)
 rename {src => board-support/nxp-lpc/src}/chips/LPC176x5x.json (100%)
 rename {src => board-support/nxp-lpc/src}/hals/LPC176x5x.zig (100%)
 rename {src => board-support/nxp-lpc/src}/tools/patchelf.zig (100%)
 rename {test => board-support/nxp-lpc/test}/programs/minimal.zig (100%)

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
deleted file mode 100644
index 7767bbb66..000000000
--- a/.buildkite/pipeline.yml
+++ /dev/null
@@ -1,4 +0,0 @@
-steps:
-  - group: Build
-    steps:
-    - command: zig build
diff --git a/LICENSE b/board-support/nxp-lpc/LICENSE
similarity index 100%
rename from LICENSE
rename to board-support/nxp-lpc/LICENSE
diff --git a/README.adoc b/board-support/nxp-lpc/README.adoc
similarity index 100%
rename from README.adoc
rename to board-support/nxp-lpc/README.adoc
diff --git a/build.zig b/board-support/nxp-lpc/build.zig
similarity index 100%
rename from build.zig
rename to board-support/nxp-lpc/build.zig
diff --git a/src/boards/mbed_LPC1768.zig b/board-support/nxp-lpc/src/boards/mbed_LPC1768.zig
similarity index 100%
rename from src/boards/mbed_LPC1768.zig
rename to board-support/nxp-lpc/src/boards/mbed_LPC1768.zig
diff --git a/src/chips/LPC176x5x.json b/board-support/nxp-lpc/src/chips/LPC176x5x.json
similarity index 100%
rename from src/chips/LPC176x5x.json
rename to board-support/nxp-lpc/src/chips/LPC176x5x.json
diff --git a/src/hals/LPC176x5x.zig b/board-support/nxp-lpc/src/hals/LPC176x5x.zig
similarity index 100%
rename from src/hals/LPC176x5x.zig
rename to board-support/nxp-lpc/src/hals/LPC176x5x.zig
diff --git a/src/tools/patchelf.zig b/board-support/nxp-lpc/src/tools/patchelf.zig
similarity index 100%
rename from src/tools/patchelf.zig
rename to board-support/nxp-lpc/src/tools/patchelf.zig
diff --git a/test/programs/minimal.zig b/board-support/nxp-lpc/test/programs/minimal.zig
similarity index 100%
rename from test/programs/minimal.zig
rename to board-support/nxp-lpc/test/programs/minimal.zig

From 1e490a3d67c1f22e953fe2f36f4a4147584c7420 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 08:53:39 +0100
Subject: [PATCH 243/286] Moves nrf5x to board-support/nordic-nrf5x

---
 README.adoc => board-support/nordic-nrf5x/README.adoc             | 0
 build.zig => board-support/nordic-nrf5x/build.zig                 | 0
 build.zig.zon => board-support/nordic-nrf5x/build.zig.zon         | 0
 .../nordic-nrf5x/src}/boards/nrf52840-dongle.zig                  | 0
 {src => board-support/nordic-nrf5x/src}/chips/nrf52.json          | 0
 {src => board-support/nordic-nrf5x/src}/chips/nrf52840.json       | 0
 {test => board-support/nordic-nrf5x/test}/nrf52840.robot          | 0
 {test => board-support/nordic-nrf5x/test}/programs/minimal.zig    | 0
 8 files changed, 0 insertions(+), 0 deletions(-)
 rename README.adoc => board-support/nordic-nrf5x/README.adoc (100%)
 rename build.zig => board-support/nordic-nrf5x/build.zig (100%)
 rename build.zig.zon => board-support/nordic-nrf5x/build.zig.zon (100%)
 rename {src => board-support/nordic-nrf5x/src}/boards/nrf52840-dongle.zig (100%)
 rename {src => board-support/nordic-nrf5x/src}/chips/nrf52.json (100%)
 rename {src => board-support/nordic-nrf5x/src}/chips/nrf52840.json (100%)
 rename {test => board-support/nordic-nrf5x/test}/nrf52840.robot (100%)
 rename {test => board-support/nordic-nrf5x/test}/programs/minimal.zig (100%)

diff --git a/README.adoc b/board-support/nordic-nrf5x/README.adoc
similarity index 100%
rename from README.adoc
rename to board-support/nordic-nrf5x/README.adoc
diff --git a/build.zig b/board-support/nordic-nrf5x/build.zig
similarity index 100%
rename from build.zig
rename to board-support/nordic-nrf5x/build.zig
diff --git a/build.zig.zon b/board-support/nordic-nrf5x/build.zig.zon
similarity index 100%
rename from build.zig.zon
rename to board-support/nordic-nrf5x/build.zig.zon
diff --git a/src/boards/nrf52840-dongle.zig b/board-support/nordic-nrf5x/src/boards/nrf52840-dongle.zig
similarity index 100%
rename from src/boards/nrf52840-dongle.zig
rename to board-support/nordic-nrf5x/src/boards/nrf52840-dongle.zig
diff --git a/src/chips/nrf52.json b/board-support/nordic-nrf5x/src/chips/nrf52.json
similarity index 100%
rename from src/chips/nrf52.json
rename to board-support/nordic-nrf5x/src/chips/nrf52.json
diff --git a/src/chips/nrf52840.json b/board-support/nordic-nrf5x/src/chips/nrf52840.json
similarity index 100%
rename from src/chips/nrf52840.json
rename to board-support/nordic-nrf5x/src/chips/nrf52840.json
diff --git a/test/nrf52840.robot b/board-support/nordic-nrf5x/test/nrf52840.robot
similarity index 100%
rename from test/nrf52840.robot
rename to board-support/nordic-nrf5x/test/nrf52840.robot
diff --git a/test/programs/minimal.zig b/board-support/nordic-nrf5x/test/programs/minimal.zig
similarity index 100%
rename from test/programs/minimal.zig
rename to board-support/nordic-nrf5x/test/programs/minimal.zig

From 34a4df5cb982209d85675cb551c20c1b39cfcde6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 08:57:48 +0100
Subject: [PATCH 244/286] Moves AVR to board-support/microchip-avr

---
 LICENSE => board-support/microchip-avr/LICENSE                   | 0
 README.adoc => board-support/microchip-avr/README.adoc           | 0
 build.zig => board-support/microchip-avr/build.zig               | 0
 build.zig.zon => board-support/microchip-avr/build.zig.zon       | 0
 {src => board-support/microchip-avr/src}/boards.zig              | 0
 {src => board-support/microchip-avr/src}/boards/arduino_nano.zig | 0
 {src => board-support/microchip-avr/src}/boards/arduino_uno.zig  | 0
 {src => board-support/microchip-avr/src}/chips.zig               | 0
 {src => board-support/microchip-avr/src}/chips/ATmega328P.json   | 0
 {src => board-support/microchip-avr/src}/hals/ATmega328P.zig     | 0
 {test => board-support/microchip-avr/test}/programs/minimal.zig  | 0
 11 files changed, 0 insertions(+), 0 deletions(-)
 rename LICENSE => board-support/microchip-avr/LICENSE (100%)
 rename README.adoc => board-support/microchip-avr/README.adoc (100%)
 rename build.zig => board-support/microchip-avr/build.zig (100%)
 rename build.zig.zon => board-support/microchip-avr/build.zig.zon (100%)
 rename {src => board-support/microchip-avr/src}/boards.zig (100%)
 rename {src => board-support/microchip-avr/src}/boards/arduino_nano.zig (100%)
 rename {src => board-support/microchip-avr/src}/boards/arduino_uno.zig (100%)
 rename {src => board-support/microchip-avr/src}/chips.zig (100%)
 rename {src => board-support/microchip-avr/src}/chips/ATmega328P.json (100%)
 rename {src => board-support/microchip-avr/src}/hals/ATmega328P.zig (100%)
 rename {test => board-support/microchip-avr/test}/programs/minimal.zig (100%)

diff --git a/LICENSE b/board-support/microchip-avr/LICENSE
similarity index 100%
rename from LICENSE
rename to board-support/microchip-avr/LICENSE
diff --git a/README.adoc b/board-support/microchip-avr/README.adoc
similarity index 100%
rename from README.adoc
rename to board-support/microchip-avr/README.adoc
diff --git a/build.zig b/board-support/microchip-avr/build.zig
similarity index 100%
rename from build.zig
rename to board-support/microchip-avr/build.zig
diff --git a/build.zig.zon b/board-support/microchip-avr/build.zig.zon
similarity index 100%
rename from build.zig.zon
rename to board-support/microchip-avr/build.zig.zon
diff --git a/src/boards.zig b/board-support/microchip-avr/src/boards.zig
similarity index 100%
rename from src/boards.zig
rename to board-support/microchip-avr/src/boards.zig
diff --git a/src/boards/arduino_nano.zig b/board-support/microchip-avr/src/boards/arduino_nano.zig
similarity index 100%
rename from src/boards/arduino_nano.zig
rename to board-support/microchip-avr/src/boards/arduino_nano.zig
diff --git a/src/boards/arduino_uno.zig b/board-support/microchip-avr/src/boards/arduino_uno.zig
similarity index 100%
rename from src/boards/arduino_uno.zig
rename to board-support/microchip-avr/src/boards/arduino_uno.zig
diff --git a/src/chips.zig b/board-support/microchip-avr/src/chips.zig
similarity index 100%
rename from src/chips.zig
rename to board-support/microchip-avr/src/chips.zig
diff --git a/src/chips/ATmega328P.json b/board-support/microchip-avr/src/chips/ATmega328P.json
similarity index 100%
rename from src/chips/ATmega328P.json
rename to board-support/microchip-avr/src/chips/ATmega328P.json
diff --git a/src/hals/ATmega328P.zig b/board-support/microchip-avr/src/hals/ATmega328P.zig
similarity index 100%
rename from src/hals/ATmega328P.zig
rename to board-support/microchip-avr/src/hals/ATmega328P.zig
diff --git a/test/programs/minimal.zig b/board-support/microchip-avr/test/programs/minimal.zig
similarity index 100%
rename from test/programs/minimal.zig
rename to board-support/microchip-avr/test/programs/minimal.zig

From 273414c4f5845972eb0a1c8ff4556f1843cb1dc1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 08:58:55 +0100
Subject: [PATCH 245/286] Moves atsam to board-support/microchip-atsam

---
 LICENSE => board-support/microchip-atsam/LICENSE               | 0
 README.md => board-support/microchip-atsam/README.md           | 0
 build.zig => board-support/microchip-atsam/build.zig           | 0
 {src => board-support/microchip-atsam}/chips/ATSAMD51J19A.atdf | 0
 4 files changed, 0 insertions(+), 0 deletions(-)
 rename LICENSE => board-support/microchip-atsam/LICENSE (100%)
 rename README.md => board-support/microchip-atsam/README.md (100%)
 rename build.zig => board-support/microchip-atsam/build.zig (100%)
 rename {src => board-support/microchip-atsam}/chips/ATSAMD51J19A.atdf (100%)

diff --git a/LICENSE b/board-support/microchip-atsam/LICENSE
similarity index 100%
rename from LICENSE
rename to board-support/microchip-atsam/LICENSE
diff --git a/README.md b/board-support/microchip-atsam/README.md
similarity index 100%
rename from README.md
rename to board-support/microchip-atsam/README.md
diff --git a/build.zig b/board-support/microchip-atsam/build.zig
similarity index 100%
rename from build.zig
rename to board-support/microchip-atsam/build.zig
diff --git a/src/chips/ATSAMD51J19A.atdf b/board-support/microchip-atsam/chips/ATSAMD51J19A.atdf
similarity index 100%
rename from src/chips/ATSAMD51J19A.atdf
rename to board-support/microchip-atsam/chips/ATSAMD51J19A.atdf

From 4eeb5d95f8d23ef36cc26de814d7812d4a89fee1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 08:59:51 +0100
Subject: [PATCH 246/286] moves gd32 to board-support/gigadevice-gd32

---
 LICENSE => board-support/gigadevice-gd32/LICENSE                  | 0
 README.adoc => board-support/gigadevice-gd32/README.adoc          | 0
 build.zig => board-support/gigadevice-gd32/build.zig              | 0
 {src => board-support/gigadevice-gd32/src}/boards/longan_nano.zig | 0
 {src => board-support/gigadevice-gd32/src}/chips/GD32VF103.json   | 0
 {src => board-support/gigadevice-gd32/src}/hals/GD32VF103.zig     | 0
 {test => board-support/gigadevice-gd32/test}/programs/minimal.zig | 0
 7 files changed, 0 insertions(+), 0 deletions(-)
 rename LICENSE => board-support/gigadevice-gd32/LICENSE (100%)
 rename README.adoc => board-support/gigadevice-gd32/README.adoc (100%)
 rename build.zig => board-support/gigadevice-gd32/build.zig (100%)
 rename {src => board-support/gigadevice-gd32/src}/boards/longan_nano.zig (100%)
 rename {src => board-support/gigadevice-gd32/src}/chips/GD32VF103.json (100%)
 rename {src => board-support/gigadevice-gd32/src}/hals/GD32VF103.zig (100%)
 rename {test => board-support/gigadevice-gd32/test}/programs/minimal.zig (100%)

diff --git a/LICENSE b/board-support/gigadevice-gd32/LICENSE
similarity index 100%
rename from LICENSE
rename to board-support/gigadevice-gd32/LICENSE
diff --git a/README.adoc b/board-support/gigadevice-gd32/README.adoc
similarity index 100%
rename from README.adoc
rename to board-support/gigadevice-gd32/README.adoc
diff --git a/build.zig b/board-support/gigadevice-gd32/build.zig
similarity index 100%
rename from build.zig
rename to board-support/gigadevice-gd32/build.zig
diff --git a/src/boards/longan_nano.zig b/board-support/gigadevice-gd32/src/boards/longan_nano.zig
similarity index 100%
rename from src/boards/longan_nano.zig
rename to board-support/gigadevice-gd32/src/boards/longan_nano.zig
diff --git a/src/chips/GD32VF103.json b/board-support/gigadevice-gd32/src/chips/GD32VF103.json
similarity index 100%
rename from src/chips/GD32VF103.json
rename to board-support/gigadevice-gd32/src/chips/GD32VF103.json
diff --git a/src/hals/GD32VF103.zig b/board-support/gigadevice-gd32/src/hals/GD32VF103.zig
similarity index 100%
rename from src/hals/GD32VF103.zig
rename to board-support/gigadevice-gd32/src/hals/GD32VF103.zig
diff --git a/test/programs/minimal.zig b/board-support/gigadevice-gd32/test/programs/minimal.zig
similarity index 100%
rename from test/programs/minimal.zig
rename to board-support/gigadevice-gd32/test/programs/minimal.zig

From 3373a5e7991b4bb8fb54fc025a84ef8348183581 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 09:00:58 +0100
Subject: [PATCH 247/286] Moves ESP to board-support/espressif-esp

---
 .gitmodules                                         |   0
 LICENSE => board-support/espressif-esp/LICENSE      |   0
 .../espressif-esp/README.adoc                       |   0
 build.zig => board-support/espressif-esp/build.zig  |   0
 .../espressif-esp/build.zig.zon                     |   0
 .../espressif-esp/docs}/esp32-c3-32s-pinout.png     | Bin
 .../espressif-esp/docs}/esp32-c3-32s-pinout.xcf     | Bin
 .../espressif-esp/perform-flash.sh                  |   0
 .../espressif-esp/src}/chips/ESP32-C3.svd           |   0
 .../espressif-esp/src}/cpus/espressif-riscv.zig     |   0
 .../espressif-esp/src}/example/blinky.zig           |   0
 .../espressif-esp/src}/hals/ESP32_C3.zig            |   0
 12 files changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 .gitmodules
 rename LICENSE => board-support/espressif-esp/LICENSE (100%)
 rename README.adoc => board-support/espressif-esp/README.adoc (100%)
 rename build.zig => board-support/espressif-esp/build.zig (100%)
 rename build.zig.zon => board-support/espressif-esp/build.zig.zon (100%)
 rename {docs => board-support/espressif-esp/docs}/esp32-c3-32s-pinout.png (100%)
 rename {docs => board-support/espressif-esp/docs}/esp32-c3-32s-pinout.xcf (100%)
 rename perform-flash.sh => board-support/espressif-esp/perform-flash.sh (100%)
 rename {src => board-support/espressif-esp/src}/chips/ESP32-C3.svd (100%)
 rename {src => board-support/espressif-esp/src}/cpus/espressif-riscv.zig (100%)
 rename {src => board-support/espressif-esp/src}/example/blinky.zig (100%)
 rename {src => board-support/espressif-esp/src}/hals/ESP32_C3.zig (100%)

diff --git a/.gitmodules b/.gitmodules
deleted file mode 100644
index e69de29bb..000000000
diff --git a/LICENSE b/board-support/espressif-esp/LICENSE
similarity index 100%
rename from LICENSE
rename to board-support/espressif-esp/LICENSE
diff --git a/README.adoc b/board-support/espressif-esp/README.adoc
similarity index 100%
rename from README.adoc
rename to board-support/espressif-esp/README.adoc
diff --git a/build.zig b/board-support/espressif-esp/build.zig
similarity index 100%
rename from build.zig
rename to board-support/espressif-esp/build.zig
diff --git a/build.zig.zon b/board-support/espressif-esp/build.zig.zon
similarity index 100%
rename from build.zig.zon
rename to board-support/espressif-esp/build.zig.zon
diff --git a/docs/esp32-c3-32s-pinout.png b/board-support/espressif-esp/docs/esp32-c3-32s-pinout.png
similarity index 100%
rename from docs/esp32-c3-32s-pinout.png
rename to board-support/espressif-esp/docs/esp32-c3-32s-pinout.png
diff --git a/docs/esp32-c3-32s-pinout.xcf b/board-support/espressif-esp/docs/esp32-c3-32s-pinout.xcf
similarity index 100%
rename from docs/esp32-c3-32s-pinout.xcf
rename to board-support/espressif-esp/docs/esp32-c3-32s-pinout.xcf
diff --git a/perform-flash.sh b/board-support/espressif-esp/perform-flash.sh
similarity index 100%
rename from perform-flash.sh
rename to board-support/espressif-esp/perform-flash.sh
diff --git a/src/chips/ESP32-C3.svd b/board-support/espressif-esp/src/chips/ESP32-C3.svd
similarity index 100%
rename from src/chips/ESP32-C3.svd
rename to board-support/espressif-esp/src/chips/ESP32-C3.svd
diff --git a/src/cpus/espressif-riscv.zig b/board-support/espressif-esp/src/cpus/espressif-riscv.zig
similarity index 100%
rename from src/cpus/espressif-riscv.zig
rename to board-support/espressif-esp/src/cpus/espressif-riscv.zig
diff --git a/src/example/blinky.zig b/board-support/espressif-esp/src/example/blinky.zig
similarity index 100%
rename from src/example/blinky.zig
rename to board-support/espressif-esp/src/example/blinky.zig
diff --git a/src/hals/ESP32_C3.zig b/board-support/espressif-esp/src/hals/ESP32_C3.zig
similarity index 100%
rename from src/hals/ESP32_C3.zig
rename to board-support/espressif-esp/src/hals/ESP32_C3.zig

From d5e05d7f42e988981edc6f817edb064e398c8012 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 09:05:26 +0100
Subject: [PATCH 248/286] Removes superfluous .buildkit ci.

---
 .buildkite/pipeline.yml | 4 ----
 1 file changed, 4 deletions(-)
 delete mode 100644 .buildkite/pipeline.yml

diff --git a/.buildkite/pipeline.yml b/.buildkite/pipeline.yml
deleted file mode 100644
index 7767bbb66..000000000
--- a/.buildkite/pipeline.yml
+++ /dev/null
@@ -1,4 +0,0 @@
-steps:
-  - group: Build
-    steps:
-    - command: zig build

From 597034bb9797a35fc43beaae8f6c6730f2577ef2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 09:51:40 +0100
Subject: [PATCH 249/286] Adds some basic package metadata.

---
 board-support/espressif-esp/microzig-package.json      | 4 ++++
 board-support/gigadevice-gd32/microzig-package.json    | 4 ++++
 board-support/microchip-atsam/microzig-package.json    | 4 ++++
 board-support/microchip-avr/microzig-package.json      | 4 ++++
 board-support/nordic-nrf5x/microzig-package.json       | 4 ++++
 board-support/nxp-lpc/microzig-package.json            | 4 ++++
 board-support/raspberrypi-rp2040/microzig-package.json | 4 ++++
 board-support/stmicro-stm32/microzig-package.json      | 4 ++++
 core/microzig-package.json                             | 4 ++++
 9 files changed, 36 insertions(+)
 create mode 100644 board-support/espressif-esp/microzig-package.json
 create mode 100644 board-support/gigadevice-gd32/microzig-package.json
 create mode 100644 board-support/microchip-atsam/microzig-package.json
 create mode 100644 board-support/microchip-avr/microzig-package.json
 create mode 100644 board-support/nordic-nrf5x/microzig-package.json
 create mode 100644 board-support/nxp-lpc/microzig-package.json
 create mode 100644 board-support/raspberrypi-rp2040/microzig-package.json
 create mode 100644 board-support/stmicro-stm32/microzig-package.json
 create mode 100644 core/microzig-package.json

diff --git a/board-support/espressif-esp/microzig-package.json b/board-support/espressif-esp/microzig-package.json
new file mode 100644
index 000000000..e38c47137
--- /dev/null
+++ b/board-support/espressif-esp/microzig-package.json
@@ -0,0 +1,4 @@
+{
+  "package_name": "espressif/esp",
+  "package_type": "board-support"
+}
diff --git a/board-support/gigadevice-gd32/microzig-package.json b/board-support/gigadevice-gd32/microzig-package.json
new file mode 100644
index 000000000..7e748a67f
--- /dev/null
+++ b/board-support/gigadevice-gd32/microzig-package.json
@@ -0,0 +1,4 @@
+{
+  "package_name": "gigadevice/gd32",
+  "package_type": "board-support"
+}
diff --git a/board-support/microchip-atsam/microzig-package.json b/board-support/microchip-atsam/microzig-package.json
new file mode 100644
index 000000000..e0eaab181
--- /dev/null
+++ b/board-support/microchip-atsam/microzig-package.json
@@ -0,0 +1,4 @@
+{
+  "package_name": "microchip/atsam",
+  "package_type": "board-support"
+}
diff --git a/board-support/microchip-avr/microzig-package.json b/board-support/microchip-avr/microzig-package.json
new file mode 100644
index 000000000..3a9d0e43d
--- /dev/null
+++ b/board-support/microchip-avr/microzig-package.json
@@ -0,0 +1,4 @@
+{
+  "package_name": "microchip/avr",
+  "package_type": "board-support"
+}
diff --git a/board-support/nordic-nrf5x/microzig-package.json b/board-support/nordic-nrf5x/microzig-package.json
new file mode 100644
index 000000000..7be87c111
--- /dev/null
+++ b/board-support/nordic-nrf5x/microzig-package.json
@@ -0,0 +1,4 @@
+{
+  "package_name": "nordic/nrf52",
+  "package_type": "board-support"
+}
diff --git a/board-support/nxp-lpc/microzig-package.json b/board-support/nxp-lpc/microzig-package.json
new file mode 100644
index 000000000..6f34eff51
--- /dev/null
+++ b/board-support/nxp-lpc/microzig-package.json
@@ -0,0 +1,4 @@
+{
+  "package_name": "nxp/lpc",
+  "package_type": "board-support"
+}
diff --git a/board-support/raspberrypi-rp2040/microzig-package.json b/board-support/raspberrypi-rp2040/microzig-package.json
new file mode 100644
index 000000000..4a0a2753c
--- /dev/null
+++ b/board-support/raspberrypi-rp2040/microzig-package.json
@@ -0,0 +1,4 @@
+{
+  "package_name": "raspberrypi/rp2040",
+  "package_type": "board-support"
+}
diff --git a/board-support/stmicro-stm32/microzig-package.json b/board-support/stmicro-stm32/microzig-package.json
new file mode 100644
index 000000000..08eb7153e
--- /dev/null
+++ b/board-support/stmicro-stm32/microzig-package.json
@@ -0,0 +1,4 @@
+{
+  "package_name": "stmicro/stm32",
+  "package_type": "board-support"
+}
diff --git a/core/microzig-package.json b/core/microzig-package.json
new file mode 100644
index 000000000..ed42e68ac
--- /dev/null
+++ b/core/microzig-package.json
@@ -0,0 +1,4 @@
+{
+  "package_name": "microzig",
+  "package_type": "core"
+}

From 0c4e82e69739885f864025b8038f3c50faff12f7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 11:55:03 +0100
Subject: [PATCH 250/286] Adds nix flake, adds tooling for creating a
 deployment of microzig, vendors some code from ezpkg

---
 .gitignore              |   1 +
 README.md               |  19 ++
 build.zig               |  20 ++
 flake.lock              | 146 ++++++++++++
 flake.nix               |  62 ++++++
 tools/archive-info.zig  | 265 ++++++++++++++++++++++
 tools/bundle.sh         | 157 +++++++++++++
 tools/create-package.sh |  45 ++++
 tools/demo-server.py    |  85 +++++++
 tools/lib/tar.zig       | 483 ++++++++++++++++++++++++++++++++++++++++
 10 files changed, 1283 insertions(+)
 create mode 100644 README.md
 create mode 100644 build.zig
 create mode 100644 flake.lock
 create mode 100644 flake.nix
 create mode 100644 tools/archive-info.zig
 create mode 100755 tools/bundle.sh
 create mode 100755 tools/create-package.sh
 create mode 100755 tools/demo-server.py
 create mode 100644 tools/lib/tar.zig

diff --git a/.gitignore b/.gitignore
index 919a2318d..aa8f1d641 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1,5 +1,6 @@
 zig-out/
 zig-cache/
+microzig-deploy/
 .DS_Store
 .gdbinit
 .lldbinit
diff --git a/README.md b/README.md
new file mode 100644
index 000000000..289bc4454
--- /dev/null
+++ b/README.md
@@ -0,0 +1,19 @@
+# MicroZig
+
+## Overview
+
+- `core/` contains the shared components of MicroZig.
+- `board-support/` contains all official board support package.
+- `examples/` contains examples that can be used with the board support packages.
+- `tools/` contains tooling to work *on* MicroZig.
+
+## Versioning Scheme
+
+MicroZig versions are tightly locked with Zig versions.
+
+The general scheme is `${zig_version}-${commit}-${count}`, so the MicroZig versions will look really similar to
+Zigs versions, but with our own commit abbreviations and counters.
+
+As MicroZig sticks to tagged Zig releases, `${zig_version}` will show to which Zig version the MicroZig build is compatible.
+
+Consider the version `0.11.0-abcdef-123` means that this MicroZig version has a commit starting with `abcdef`, which was the 123rd commit of the version that is compatible with Zig 0.11.0.
diff --git a/build.zig b/build.zig
new file mode 100644
index 000000000..21246fe29
--- /dev/null
+++ b/build.zig
@@ -0,0 +1,20 @@
+const std = @import("std");
+
+pub fn build(b: *std.Build) void {
+    buildTools(b);
+}
+
+fn buildTools(b: *std.Build) void {
+    const tools_step = b.step("tools", "Only build the development tools");
+    b.getInstallStep().dependOn(tools_step);
+
+    const archive_info = b.addExecutable(.{
+        .name = "archive-info",
+        .optimize = .ReleaseSafe,
+        .root_source_file = .{ .path = "tools/archive-info.zig" },
+    });
+
+    tools_step.dependOn(&b.addInstallArtifact(archive_info, .{
+        .dest_dir = .{ .override = .{ .custom = "tools" } },
+    }).step);
+}
diff --git a/flake.lock b/flake.lock
new file mode 100644
index 000000000..d614e0c7e
--- /dev/null
+++ b/flake.lock
@@ -0,0 +1,146 @@
+{
+  "nodes": {
+    "flake-compat": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1696426674,
+        "narHash": "sha256-kvjfFW7WAETZlt09AgDn1MrtKzP7t90Vf7vypd3OL1U=",
+        "owner": "edolstra",
+        "repo": "flake-compat",
+        "rev": "0f9255e01c2351cc7d116c072cb317785dd33b33",
+        "type": "github"
+      },
+      "original": {
+        "owner": "edolstra",
+        "repo": "flake-compat",
+        "type": "github"
+      }
+    },
+    "flake-compat_2": {
+      "flake": false,
+      "locked": {
+        "lastModified": 1673956053,
+        "narHash": "sha256-4gtG9iQuiKITOjNQQeQIpoIB6b16fm+504Ch3sNKLd8=",
+        "owner": "edolstra",
+        "repo": "flake-compat",
+        "rev": "35bb57c0c8d8b62bbfd284272c928ceb64ddbde9",
+        "type": "github"
+      },
+      "original": {
+        "owner": "edolstra",
+        "repo": "flake-compat",
+        "type": "github"
+      }
+    },
+    "flake-utils": {
+      "inputs": {
+        "systems": "systems"
+      },
+      "locked": {
+        "lastModified": 1701680307,
+        "narHash": "sha256-kAuep2h5ajznlPMD9rnQyffWG8EM/C73lejGofXvdM8=",
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "rev": "4022d587cbbfd70fe950c1e2083a02621806a725",
+        "type": "github"
+      },
+      "original": {
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "type": "github"
+      }
+    },
+    "flake-utils_2": {
+      "locked": {
+        "lastModified": 1659877975,
+        "narHash": "sha256-zllb8aq3YO3h8B/U0/J1WBgAL8EX5yWf5pMj3G0NAmc=",
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "rev": "c0e246b9b83f637f4681389ecabcb2681b4f3af0",
+        "type": "github"
+      },
+      "original": {
+        "owner": "numtide",
+        "repo": "flake-utils",
+        "type": "github"
+      }
+    },
+    "nixpkgs": {
+      "locked": {
+        "lastModified": 1704290814,
+        "narHash": "sha256-LWvKHp7kGxk/GEtlrGYV68qIvPHkU9iToomNFGagixU=",
+        "owner": "nixos",
+        "repo": "nixpkgs",
+        "rev": "70bdadeb94ffc8806c0570eb5c2695ad29f0e421",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nixos",
+        "ref": "release-23.05",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
+    "nixpkgs_2": {
+      "locked": {
+        "lastModified": 1702350026,
+        "narHash": "sha256-A+GNZFZdfl4JdDphYKBJ5Ef1HOiFsP18vQe9mqjmUis=",
+        "owner": "NixOS",
+        "repo": "nixpkgs",
+        "rev": "9463103069725474698139ab10f17a9d125da859",
+        "type": "github"
+      },
+      "original": {
+        "owner": "NixOS",
+        "ref": "nixos-23.05",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
+    "root": {
+      "inputs": {
+        "flake-compat": "flake-compat",
+        "flake-utils": "flake-utils",
+        "nixpkgs": "nixpkgs",
+        "zig": "zig"
+      }
+    },
+    "systems": {
+      "locked": {
+        "lastModified": 1681028828,
+        "narHash": "sha256-Vy1rq5AaRuLzOxct8nz4T6wlgyUR7zLU309k9mBC768=",
+        "owner": "nix-systems",
+        "repo": "default",
+        "rev": "da67096a3b9bf56a91d16901293e51ba5b49a27e",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nix-systems",
+        "repo": "default",
+        "type": "github"
+      }
+    },
+    "zig": {
+      "inputs": {
+        "flake-compat": "flake-compat_2",
+        "flake-utils": "flake-utils_2",
+        "nixpkgs": "nixpkgs_2"
+      },
+      "locked": {
+        "lastModified": 1704283725,
+        "narHash": "sha256-sRWv8au/59BZpWpqqC8PaGDC9bUNhRIMzanF1zPnXNQ=",
+        "owner": "mitchellh",
+        "repo": "zig-overlay",
+        "rev": "f06e268e24a71922ff8b20c94cff1d2afcbd4ab5",
+        "type": "github"
+      },
+      "original": {
+        "owner": "mitchellh",
+        "repo": "zig-overlay",
+        "type": "github"
+      }
+    }
+  },
+  "root": "root",
+  "version": 7
+}
diff --git a/flake.nix b/flake.nix
new file mode 100644
index 000000000..c778a9697
--- /dev/null
+++ b/flake.nix
@@ -0,0 +1,62 @@
+{
+  description = "microzig development environment";
+
+  inputs = {
+    nixpkgs.url = "github:nixos/nixpkgs/release-23.05";
+    flake-utils.url = "github:numtide/flake-utils";
+
+    # required for latest zig
+    zig.url = "github:mitchellh/zig-overlay";
+
+    # Used for shell.nix
+    flake-compat = {
+      url = github:edolstra/flake-compat;
+      flake = false;
+    };
+  };
+
+  outputs = {
+    self,
+    nixpkgs,
+    flake-utils,
+    ...
+  } @ inputs: let
+    overlays = [
+      # Other overlays
+      (final: prev: {
+        zigpkgs = inputs.zig.packages.${prev.system};
+      })
+    ];
+
+    # Our supported systems are the same supported systems as the Zig binaries
+    systems = builtins.attrNames inputs.zig.packages;
+  in
+    flake-utils.lib.eachSystem systems (
+      system: let
+        pkgs = import nixpkgs {inherit overlays system;};
+      in rec {
+        devShells.default = pkgs.mkShell {
+          nativeBuildInputs = [
+            pkgs.zigpkgs."0.11.0"
+          ];
+
+          buildInputs = [
+            # we need a version of bash capable of being interactive
+            # as opposed to a bash just used for building this flake
+            # in non-interactive mode
+            pkgs.bashInteractive
+            pkgs.zlib
+          ];
+
+          shellHook = ''
+            # once we set SHELL to point to the interactive bash, neovim will
+            # launch the correct $SHELL in its :terminal
+            export SHELL=${pkgs.bashInteractive}/bin/bash
+          '';
+        };
+
+        # For compatibility with older versions of the `nix` binary
+        devShell = self.devShells.${system}.default;
+      }
+    );
+}
diff --git a/tools/archive-info.zig b/tools/archive-info.zig
new file mode 100644
index 000000000..d563c0c05
--- /dev/null
+++ b/tools/archive-info.zig
@@ -0,0 +1,265 @@
+//!
+//! Computes some meta information for packages and prints them as JSON.
+//! Usage: archive-info 
+//!
+//! Is used in `/tools/bundle.sh` to extend the `microzig-package.json` file.
+//!
+
+const std = @import("std");
+const Allocator = std.mem.Allocator;
+const assert = std.debug.assert;
+const Hash = std.crypto.hash.sha2.Sha256;
+
+const builtin = @import("builtin");
+const tar = @import("lib/tar.zig");
+
+const JsonInfo = struct {
+    hash: []const u8,
+    files: []const []const u8,
+};
+
+pub fn main() !void {
+    var gpa = std.heap.GeneralPurposeAllocator(.{}){};
+    defer _ = gpa.deinit();
+    const allocator = gpa.allocator();
+
+    const argv = try std.process.argsAlloc(allocator);
+    defer std.process.argsFree(allocator, argv);
+
+    if (argv.len != 2) {
+        @panic("archive-info ");
+    }
+
+    var file = try std.fs.cwd().openFile(argv[1], .{});
+    defer file.close();
+
+    var buffered = std.io.bufferedReaderSize(4096, file.reader());
+
+    var decompress = try std.compress.gzip.decompress(allocator, buffered.reader());
+    defer decompress.deinit();
+
+    var arc = try Archive.read_from_tar(allocator, decompress.reader(), .{
+        .strip_components = 0,
+    });
+    defer arc.deinit(allocator);
+
+    {
+        var paths = std.ArrayList([]const u8).init(allocator);
+        defer paths.deinit();
+
+        try paths.appendSlice(arc.files.keys());
+        std.mem.sort([]const u8, paths.items, {}, Archive.path_less_than);
+
+        const calculated_hash = try arc.hash(allocator, .ignore_executable_bit);
+        var hash_buf: [4 + 2 * calculated_hash.len]u8 = undefined;
+        const hash_str = try std.fmt.bufPrint(&hash_buf, "1220{}", .{std.fmt.fmtSliceHexLower(&calculated_hash)});
+
+        var json_info = JsonInfo{
+            .hash = hash_str,
+            .files = paths.items,
+        };
+
+        try std.json.stringify(json_info, .{}, std.io.getStdOut().writer());
+    }
+}
+
+const Archive = struct {
+    files: std.StringArrayHashMapUnmanaged(File) = .{},
+
+    pub const File = struct {
+        mode: std.fs.File.Mode,
+        text: []const u8,
+    };
+
+    pub fn deinit(archive: *Archive, allocator: Allocator) void {
+        for (archive.files.keys(), archive.files.values()) |path, file| {
+            allocator.free(path);
+            allocator.free(file.text);
+        }
+
+        archive.files.deinit(allocator);
+    }
+
+    fn padding_from_size(size: usize) usize {
+        const mod = (512 + size) % 512;
+        return if (mod > 0) 512 - mod else 0;
+    }
+
+    pub fn entry_should_be_skipped(path: []const u8) !bool {
+        var it = try std.fs.path.componentIterator(path);
+        const first = it.next().?;
+        return std.mem.eql(u8, first.name, ".git") or
+            std.mem.eql(u8, first.name, "zig-out") or
+            std.mem.eql(u8, first.name, "zig-cache");
+    }
+
+    fn stripComponents(path: []const u8, count: u32) ![]const u8 {
+        var i: usize = 0;
+        var c = count;
+        while (c > 0) : (c -= 1) {
+            if (std.mem.indexOfScalarPos(u8, path, i, '/')) |pos| {
+                i = pos + 1;
+            } else {
+                return error.TarComponentsOutsideStrippedPrefix;
+            }
+        }
+        return path[i..];
+    }
+
+    const ReadFromTarOptions = struct {
+        strip_components: u32,
+    };
+
+    pub fn read_from_tar(
+        allocator: Allocator,
+        reader: anytype,
+        options: ReadFromTarOptions,
+    ) !Archive {
+        var archive = Archive{};
+        errdefer archive.deinit(allocator);
+
+        var file_name_buffer: [255]u8 = undefined;
+        var buffer: [512 * 8]u8 = undefined;
+        var start: usize = 0;
+        var end: usize = 0;
+        header: while (true) {
+            if (buffer.len - start < 1024) {
+                const dest_end = end - start;
+                @memcpy(buffer[0..dest_end], buffer[start..end]);
+                end = dest_end;
+                start = 0;
+            }
+            const ask_header = @min(buffer.len - end, 1024 -| (end - start));
+            end += try reader.readAtLeast(buffer[end..], ask_header);
+            switch (end - start) {
+                0 => return archive,
+                1...511 => return error.UnexpectedEndOfStream,
+                else => {},
+            }
+            const header: std.tar.Header = .{ .bytes = buffer[start..][0..512] };
+            start += 512;
+            const file_size = try header.fileSize();
+            const rounded_file_size = std.mem.alignForward(u64, file_size, 512);
+            const pad_len = @as(usize, @intCast(rounded_file_size - file_size));
+            const unstripped_file_name = try header.fullFileName(&file_name_buffer);
+            switch (header.fileType()) {
+                .directory => {},
+                .normal => {
+                    if (file_size == 0 and unstripped_file_name.len == 0) return archive;
+                    const file_name = try stripComponents(unstripped_file_name, options.strip_components);
+
+                    const file_name_copy = try allocator.dupe(u8, file_name);
+                    errdefer allocator.free(file_name_copy);
+
+                    var file = std.ArrayList(u8).init(allocator);
+                    defer file.deinit();
+
+                    var file_off: usize = 0;
+                    while (true) {
+                        if (buffer.len - start < 1024) {
+                            const dest_end = end - start;
+                            @memcpy(buffer[0..dest_end], buffer[start..end]);
+                            end = dest_end;
+                            start = 0;
+                        }
+                        // Ask for the rounded up file size + 512 for the next header.
+                        // TODO: https://github.com/ziglang/zig/issues/14039
+                        const ask = @as(usize, @intCast(@min(
+                            buffer.len - end,
+                            rounded_file_size + 512 - file_off -| (end - start),
+                        )));
+                        end += try reader.readAtLeast(buffer[end..], ask);
+                        if (end - start < ask) return error.UnexpectedEndOfStream;
+                        // TODO: https://github.com/ziglang/zig/issues/14039
+                        const slice = buffer[start..@as(usize, @intCast(@min(file_size - file_off + start, end)))];
+                        try file.writer().writeAll(slice);
+                        file_off += slice.len;
+                        start += slice.len;
+                        if (file_off >= file_size) {
+                            start += pad_len;
+                            // Guaranteed since we use a buffer divisible by 512.
+                            assert(start <= end);
+                            const text = try file.toOwnedSlice();
+                            errdefer allocator.free(text);
+
+                            const local_header: *const tar.Header = @ptrCast(header.bytes);
+                            _ = local_header;
+                            try archive.files.put(allocator, file_name_copy, .{
+                                .text = text,
+                                .mode = 0o644,
+                                //.mode = try local_header.get_mode(),
+                            });
+                            continue :header;
+                        }
+                    }
+                },
+                .global_extended_header, .extended_header => {
+                    if (start + rounded_file_size > end) return error.TarHeadersTooBig;
+                    start = @as(usize, @intCast(start + rounded_file_size));
+                },
+                .hard_link => return error.TarUnsupportedFileType,
+                .symbolic_link => return error.TarUnsupportedFileType,
+                else => return error.TarUnsupportedFileType,
+            }
+        }
+
+        return archive;
+    }
+
+    fn path_less_than(_: void, lhs: []const u8, rhs: []const u8) bool {
+        return std.mem.lessThan(u8, lhs, rhs);
+    }
+
+    pub const WhatToDoWithExecutableBit = enum {
+        ignore_executable_bit,
+        include_executable_bit,
+    };
+
+    fn is_executable(mode: std.fs.File.Mode, executable_bit: WhatToDoWithExecutableBit) bool {
+        switch (executable_bit) {
+            .ignore_executable_bit => return false,
+            .include_executable_bit => {},
+        }
+
+        if (builtin.os.tag == .windows) {
+            // TODO check the ACL on Windows.
+            // Until this is implemented, this could be a false negative on
+            // Windows, which is why we do not yet set executable_bit_only above
+            // when unpacking the tarball.
+            return false;
+        } else {
+            return (mode & std.os.S.IXUSR) != 0;
+        }
+    }
+
+    pub fn hash(
+        archive: Archive,
+        allocator: Allocator,
+        executable_bit: WhatToDoWithExecutableBit,
+    ) ![Hash.digest_length]u8 {
+        var paths = std.ArrayList([]const u8).init(allocator);
+        defer paths.deinit();
+
+        var hashes = std.ArrayList([Hash.digest_length]u8).init(allocator);
+        defer hashes.deinit();
+
+        try paths.appendSlice(archive.files.keys());
+        try hashes.appendNTimes(undefined, paths.items.len);
+        std.mem.sort([]const u8, paths.items, {}, path_less_than);
+
+        for (paths.items, hashes.items) |path, *result| {
+            const file = archive.files.get(path).?;
+            var hasher = Hash.init(.{});
+            hasher.update(path);
+            hasher.update(&.{ 0, @intFromBool(is_executable(file.mode, executable_bit)) });
+            hasher.update(file.text);
+            hasher.final(result);
+        }
+
+        var hasher = Hash.init(.{});
+        for (hashes.items) |file_hash|
+            hasher.update(&file_hash);
+
+        return hasher.finalResult();
+    }
+};
diff --git a/tools/bundle.sh b/tools/bundle.sh
new file mode 100755
index 000000000..22b94eef9
--- /dev/null
+++ b/tools/bundle.sh
@@ -0,0 +1,157 @@
+#!/bin/sh
+
+#
+# Prepares a full deployment of MicroZig.
+# Creates all packages into /microzig-deploy with the final folder structure.
+#
+
+set -euo pipefail
+
+all_files_dir=".data"
+
+# test for all required tools:
+which zig date find jq mkdir dirname realpath > /dev/null
+
+[ "$(zig version)" == "0.11.0" ]
+
+repo_root="$(dirname "$(dirname "$(realpath "$0")")")"
+[ -d "${repo_root}" ]
+
+echo "preparing environment..."
+
+alias create_package="${repo_root}/tools/create-package.sh"
+
+# Some generic meta information:
+
+unix_timestamp="$(date '+%s')"
+iso_timestamp="$(date --iso-8601=seconds)"
+
+# Determine correct version:
+
+git_description="$(git describe --match "*.*.*" --tags --abbrev=9)"
+version=""
+
+# render-version     
+function render_version()
+{
+    [ "$#" -eq 5 ] 
+    echo "$1.$2.$3-$4-$5"
+}
+
+case "${git_description}" in 
+    *.*.*-*-*)
+        version="$(render_version $(echo "${git_description}" | sed -E 's/^([0-9]+)\.([0-9]+)\.([0-9]+)\-([0-9]+)\-([a-z0-9]+)$/\1 \2 \3 \4 \5/'))"
+        ;;
+
+    *.*.*)
+        # a "on point" tagged version still has a hash as well as the counter 0!
+        version="$(render_version $(echo "${git_description}" | sed -E 's/^([0-9]+)\.([0-9]+)\.([0-9]+)$/\1 \2 \3/') 0 $(git rev-parse --short=9 HEAD))"
+        ;;
+    
+    *)
+        echo "Bad result '${git_description}' from git describe." >&2
+        exit 1
+        ;;
+esac
+
+if [ -z "${version}" ]; then
+    echo "Could not determine a version. Please verify repository state!" >&2
+    exit 1
+fi
+
+deploy_target="${repo_root}/microzig-deploy"
+
+[ -d "${deploy_target}" ] && rm -r "${deploy_target}"
+mkdir -p "${deploy_target}"
+
+cd "${repo_root}"
+
+# ensure we have our tools available:
+zig build tools
+
+[ -x "${repo_root}/zig-out/tools/archive-info" ]
+alias archive_info="${repo_root}/zig-out/tools/archive-info"
+
+for dir in $(find -type f -name microzig-package.json -exec dirname '{}' ';'); do
+    dir="$(realpath "${dir}")"
+    meta_path="$(realpath "${dir}/microzig-package.json")"
+
+    pkg_name="$(jq -r .package_name < "${meta_path}")"
+    pkg_type="$(jq -r .package_type < "${meta_path}")"
+
+    (
+        cd "${dir}"
+
+        echo "bundling ${dir}..."
+
+        out_dir=""
+        out_basename=""
+
+        case "${pkg_type}" in
+            core)
+                out_dir="${deploy_target}"
+                out_basename="${pkg_name}"
+                ;;
+            
+            board-support)
+                out_dir="${deploy_target}/board-support/$(dirname "${pkg_name}")"
+                out_basename="$(basename "${pkg_name}")"
+                ;;
+
+            *)
+                echo "Unsupported package type: '${pkg_type}'!" >&2
+                exit 1
+                ;;
+        esac
+
+        [ ! -z "${out_dir}" ] && [ ! -z "${out_basename}" ]
+
+        out_fullname="${out_basename}-${version}.tar.gz"
+        out_fullmeta="${out_basename}-${version}.json"
+
+        out_name="${out_basename}.tar.gz"
+        out_meta="${out_basename}.json"
+        
+        out_path="${out_dir}/${all_files_dir}/${out_fullname}"
+
+        mkdir -p "${out_dir}/${all_files_dir}"
+
+        # first, compile package
+        create_package "${dir}" "${out_path}"
+
+        # get some required metadata
+        file_hash=($(sha256sum "${out_path}" | cut -f 1))
+        file_size="$(stat --format="%s" "${out_path}")"
+
+        pkg_info="$(archive_info ${out_path})"
+
+        jq \
+            --arg vers "${version}" \
+            --arg ts_unix "${unix_timestamp}" \
+            --arg ts_iso "${iso_timestamp}" \
+            --arg fhash "${file_hash}" \
+            --arg fsize "${file_size}" \
+            --argjson pkg "${pkg_info}" \
+                '. + {
+                    version: $vers,
+                    created: {
+                        unix: $ts_unix,
+                        iso: $ts_iso,
+                    },
+                    archive: {
+                        size: $fsize,
+                        sha256sum: $fhash,
+                    },
+                    package: $pkg
+                }' \
+            "${meta_path}" \
+            > "${out_dir}/${all_files_dir}/${out_fullmeta}" \
+
+        (
+            cd "${out_dir}"
+            ln -s "${all_files_dir}/${out_fullname}" "${out_name}"
+            ln -s "${all_files_dir}/${out_fullmeta}" "${out_meta}"
+        )
+
+    )
+done
diff --git a/tools/create-package.sh b/tools/create-package.sh
new file mode 100755
index 000000000..e22a67c8f
--- /dev/null
+++ b/tools/create-package.sh
@@ -0,0 +1,45 @@
+#!/bin/sh
+
+set -euo pipefail
+
+# test for all required tools:
+which tar gzip jq basename dirname realpath > /dev/null
+
+if [ "$#" -ne 2 ]; then 
+    echo "usage: $(basename "$0")  " >&2
+    exit 1
+fi
+
+input_folder="$(realpath "$1")"
+output_file="$(realpath "$2")"
+
+if [ ! -d "${input_folder}" ]; then 
+    echo "${input_folder} does not exist or is not a directory!" >&2
+    exit 1
+fi
+
+
+if [ ! -f "${input_folder}/microzig-package.json" ]; then 
+    echo "The input folder does not contain a microzig-package.json!" >&2
+    exit 1
+fi 
+
+if [ -e "${output_file}" ]; then 
+    echo "${output_file} already exists, please delete first!" >&2
+    exit 1
+fi 
+
+if [ ! -d "$(dirname "${output_file}")" ]; then 
+    echo "${output_file} does not point to a path where a file can be created!" >&2
+    exit 1
+fi 
+
+(
+    cd "${input_folder}"
+    # explanation on ls-files: 
+    # https://stackoverflow.com/a/53083343
+    tar -caf "${output_file}" $(git ls-files -- . ':!:microzig-package.json')
+)
+
+# echo "included files:"
+# tar -tf "${output_file}"
diff --git a/tools/demo-server.py b/tools/demo-server.py
new file mode 100755
index 000000000..302edf51a
--- /dev/null
+++ b/tools/demo-server.py
@@ -0,0 +1,85 @@
+#!/usr/bin/env python3
+
+
+from pathlib import Path
+from http.server import HTTPServer,SimpleHTTPRequestHandler
+from http import HTTPStatus
+import sys, os, io, urllib.parse, html
+
+SELF_DIR = Path(__file__).parent
+assert SELF_DIR.is_dir()
+
+ROOT_DIR = SELF_DIR.parent
+assert SELF_DIR.is_dir()
+
+DEPLOYMENT_DIR = ROOT_DIR / "microzig-deploy"
+if not DEPLOYMENT_DIR.is_dir():
+    print(f"{DEPLOYMENT_DIR} isn't a directory. Please create a directory first with ./tools/bundle.sh!")
+    exit(1)
+
+class Handler(SimpleHTTPRequestHandler):
+    def __init__(self, *args, **kwargs):
+        super().__init__(*args, directory=str(DEPLOYMENT_DIR), **kwargs)
+
+    def list_directory(self, path):
+        """Helper to produce a directory listing (absent index.html).
+
+        Return value is either a file object, or None (indicating an
+        error).  In either case, the headers are sent, making the
+        interface the same as for send_head().
+
+        """
+        try:
+            list = os.listdir(path)
+        except OSError:
+            self.send_error(
+                HTTPStatus.NOT_FOUND,
+                "No permission to list directory")
+            return None
+        list.sort(key=lambda a: a.lower())
+        r = []
+        try:
+            displaypath = urllib.parse.unquote(self.path,
+                                               errors='surrogatepass')
+        except UnicodeDecodeError:
+            displaypath = urllib.parse.unquote(self.path)
+        displaypath = html.escape(displaypath, quote=False)
+        enc = sys.getfilesystemencoding()
+        title = 'Directory listing for %s' % displaypath
+        r.append('')
+        r.append('\n')
+        r.append('' % enc)
+        r.append('%s\n' % title)
+        r.append('\n
    %s
    ' % title)
+        r.append('
    \n    \n
    \n\n\n')
+        encoded = '\n'.join(r).encode(enc, 'surrogateescape')
+        f = io.BytesIO()
+        f.write(encoded)
+        f.seek(0)
+        self.send_response(HTTPStatus.OK)
+        self.send_header("Content-type", "text/html; charset=%s" % enc)
+        self.send_header("Content-Length", str(len(encoded)))
+        self.end_headers()
+        return f
+
+if __name__ == "__main__":
+    httpd = HTTPServer(('', 8080), Handler)
+    httpd.serve_forever()
+
diff --git a/tools/lib/tar.zig b/tools/lib/tar.zig
new file mode 100644
index 000000000..43c1b8d08
--- /dev/null
+++ b/tools/lib/tar.zig
@@ -0,0 +1,483 @@
+const std = @import("std");
+const builtin = @import("builtin");
+
+const testing = std.testing;
+const Allocator = std.mem.Allocator;
+
+// ustar tar implementation
+pub const Header = extern struct {
+    name: [100]u8,
+    mode: [7:0]u8,
+    uid: [7:0]u8,
+    gid: [7:0]u8,
+    size: [11:0]u8,
+    mtime: [11:0]u8,
+    checksum: [7:0]u8,
+    typeflag: FileType,
+    linkname: [100]u8,
+    magic: [5:0]u8,
+    version: [2]u8,
+    uname: [31:0]u8,
+    gname: [31:0]u8,
+    devmajor: [7:0]u8,
+    devminor: [7:0]u8,
+    prefix: [155]u8,
+    pad: [12]u8,
+
+    comptime {
+        std.debug.assert(@sizeOf(Header) == 512);
+    }
+
+    const Self = @This();
+
+    const FileType = enum(u8) {
+        regular = '0',
+        hard_link = '1',
+        symbolic_link = '2',
+        character = '3',
+        block = '4',
+        directory = '5',
+        fifo = '6',
+        reserved = '7',
+        pax_global = 'g',
+        extended = 'x',
+        _,
+    };
+
+    const Options = struct {
+        typeflag: FileType,
+        path: []const u8,
+        size: u64,
+        mode: std.fs.File.Mode,
+    };
+
+    pub fn to_bytes(header: *const Header) *const [512]u8 {
+        return @ptrCast(header);
+    }
+
+    pub fn init(opts: Options) !Self {
+        var ret = std.mem.zeroes(Self);
+        ret.magic = [_:0]u8{ 'u', 's', 't', 'a', 'r' };
+        ret.version = [_:0]u8{ '0', '0' };
+        ret.typeflag = opts.typeflag;
+
+        try ret.setPath(opts.path);
+        try ret.setSize(opts.size);
+        try ret.setMtime(0);
+        try ret.setMode(opts.typeflag, opts.mode);
+        try ret.setUid(0);
+        try ret.setGid(0);
+
+        std.mem.copy(u8, &ret.uname, "root");
+        std.mem.copy(u8, &ret.gname, "root");
+
+        try ret.updateChecksum();
+        return ret;
+    }
+
+    pub fn setPath(self: *Self, path: []const u8) !void {
+        if (path.len > 100) {
+            var i: usize = 100;
+            while (i > 0) : (i -= 1) {
+                if (path[i] == '/' and i < 100)
+                    break;
+            }
+
+            _ = try std.fmt.bufPrint(&self.prefix, "{s}", .{path[0..i]});
+            _ = try std.fmt.bufPrint(&self.name, "{s}", .{path[i + 1 ..]});
+        } else {
+            _ = try std.fmt.bufPrint(&self.name, "{s}", .{path});
+        }
+    }
+
+    pub fn setSize(self: *Self, size: u64) !void {
+        _ = try std.fmt.bufPrint(&self.size, "{o:0>11}", .{size});
+    }
+
+    pub fn get_size(header: Header) !u64 {
+        return std.fmt.parseUnsigned(u64, &header.size, 8);
+    }
+
+    pub fn setMtime(self: *Self, mtime: u32) !void {
+        _ = try std.fmt.bufPrint(&self.mtime, "{o:0>11}", .{mtime});
+    }
+
+    pub fn setMode(self: *Self, filetype: FileType, perm: std.fs.File.Mode) !void {
+        switch (filetype) {
+            .regular => _ = try std.fmt.bufPrint(&self.mode, "0{o:0>6}", .{perm}),
+            .directory => _ = try std.fmt.bufPrint(&self.mode, "0{o:0>6}", .{perm}),
+            else => return error.Unsupported,
+        }
+    }
+
+    pub fn get_mode(header: Header) !std.fs.File.Mode {
+        std.log.info("mode str: {s}", .{&header.mode});
+        return std.fmt.parseUnsigned(std.fs.File.Mode, &header.mode, 8);
+    }
+
+    fn setUid(self: *Self, uid: u32) !void {
+        _ = try std.fmt.bufPrint(&self.uid, "{o:0>7}", .{uid});
+    }
+
+    fn setGid(self: *Self, gid: u32) !void {
+        _ = try std.fmt.bufPrint(&self.gid, "{o:0>7}", .{gid});
+    }
+
+    pub fn updateChecksum(self: *Self) !void {
+        const offset = @offsetOf(Self, "checksum");
+        var checksum: usize = 0;
+        for (std.mem.asBytes(self), 0..) |val, i| {
+            checksum += if (i >= offset and i < offset + @sizeOf(@TypeOf(self.checksum)))
+                ' '
+            else
+                val;
+        }
+
+        _ = try std.fmt.bufPrint(&self.checksum, "{o:0>7}", .{checksum});
+    }
+
+    pub fn fromStat(stat: std.fs.File.Stat, path: []const u8) !Header {
+        if (std.mem.indexOf(u8, path, "\\") != null) return error.NeedPosixPath;
+        if (std.fs.path.isAbsolute(path)) return error.NeedRelPath;
+
+        var ret = Self.init();
+        ret.typeflag = switch (stat.kind) {
+            .File => .regular,
+            .Directory => .directory,
+            else => return error.UnsupportedType,
+        };
+
+        try ret.setPath(path);
+        try ret.setSize(stat.size);
+        try ret.setMtime(@as(u32, @truncate(@as(u128, @bitCast(@divTrunc(stat.mtime, std.time.ns_per_s))))));
+        try ret.setMode(ret.typeflag, @as(u9, @truncate(stat.mode)));
+
+        try ret.setUid(0);
+        try ret.setGid(0);
+
+        std.mem.copy(u8, &ret.uname, "root");
+        std.mem.copy(u8, &ret.gname, "root");
+
+        try ret.updateChecksum();
+        return ret;
+    }
+
+    pub fn isBlank(self: *const Header) bool {
+        const block = std.mem.asBytes(self);
+        return for (block) |elem| {
+            if (elem != 0) break false;
+        } else true;
+    }
+};
+
+test "Header size" {
+    try testing.expectEqual(512, @sizeOf(Header));
+}
+
+pub fn instantiate(
+    allocator: Allocator,
+    dir: std.fs.Dir,
+    reader: anytype,
+    skip_depth: usize,
+) !void {
+    var count: usize = 0;
+    while (true) {
+        const header = reader.readStruct(Header) catch |err| {
+            return if (err == error.EndOfStream)
+                if (count < 2) error.AbrubtEnd else break
+            else
+                err;
+        };
+
+        if (header.isBlank()) {
+            count += 1;
+            continue;
+        } else if (count > 0) {
+            return error.Format;
+        }
+
+        var size = try std.fmt.parseUnsigned(usize, &header.size, 8);
+        const block_size = ((size + 511) / 512) * 512;
+        var components = std.ArrayList([]const u8).init(allocator);
+        defer components.deinit();
+
+        var path_it = std.mem.tokenize(u8, &header.prefix, "/\x00");
+        if (header.prefix[0] != 0) {
+            while (path_it.next()) |component| {
+                try components.append(component);
+            }
+        }
+
+        path_it = std.mem.tokenize(u8, &header.name, "/\x00");
+        while (path_it.next()) |component| {
+            try components.append(component);
+        }
+
+        const tmp_path = try std.fs.path.join(allocator, components.items);
+        defer allocator.free(tmp_path);
+
+        if (skip_depth >= components.items.len) {
+            try reader.skipBytes(block_size, .{});
+            continue;
+        }
+
+        var i: usize = 0;
+        while (i < skip_depth) : (i += 1) {
+            _ = components.orderedRemove(0);
+        }
+
+        const file_path = try std.fs.path.join(allocator, components.items);
+        defer allocator.free(file_path);
+
+        switch (header.typeflag) {
+            .directory => try dir.makePath(file_path),
+            .pax_global => try reader.skipBytes(512, .{}),
+            .regular => {
+                const file = try dir.createFile(file_path, .{ .read = true, .truncate = true });
+                defer file.close();
+                const skip_size = block_size - size;
+
+                var buf: [std.mem.page_size]u8 = undefined;
+                while (size > 0) {
+                    const buffered = try reader.read(buf[0..std.math.min(size, 512)]);
+                    try file.writeAll(buf[0..buffered]);
+                    size -= buffered;
+                }
+
+                try reader.skipBytes(skip_size, .{});
+            },
+            else => {},
+        }
+    }
+}
+
+pub fn builder(allocator: Allocator, writer: anytype) Builder(@TypeOf(writer)) {
+    return Builder(@TypeOf(writer)).init(allocator, writer);
+}
+
+pub fn Builder(comptime Writer: type) type {
+    return struct {
+        writer: Writer,
+        arena: std.heap.ArenaAllocator,
+        directories: std.StringHashMap(void),
+
+        const Self = @This();
+
+        pub fn init(allocator: Allocator, writer: Writer) Self {
+            return Self{
+                .arena = std.heap.ArenaAllocator.init(allocator),
+                .writer = writer,
+                .directories = std.StringHashMap(void).init(allocator),
+            };
+        }
+
+        pub fn deinit(self: *Self) void {
+            self.directories.deinit();
+            self.arena.deinit();
+        }
+
+        pub fn finish(self: *Self) !void {
+            try self.writer.writeByteNTimes(0, 1024);
+        }
+
+        fn maybeAddDirectories(
+            self: *Self,
+            path: []const u8,
+        ) !void {
+            var i: usize = 0;
+            while (i < path.len) : (i += 1) {
+                while (path[i] != '/' and i < path.len) i += 1;
+                if (i >= path.len) break;
+                const dirpath = try self.arena.allocator().dupe(u8, path[0..i]);
+                if (self.directories.contains(dirpath)) continue else try self.directories.put(dirpath, {});
+
+                const stat = std.fs.File.Stat{
+                    .inode = undefined,
+                    .size = 0,
+                    .mode = switch (builtin.os.tag) {
+                        .windows => 0,
+                        else => 0o755,
+                    },
+                    .kind = .Directory,
+                    .atime = undefined,
+                    .mtime = std.time.nanoTimestamp(),
+                    .ctime = undefined,
+                };
+                const allocator = self.arena.child_allocator;
+                const posix_dirpath = try std.mem.replaceOwned(u8, allocator, dirpath, std.fs.path.sep_str_windows, std.fs.path.sep_str_posix);
+                defer allocator.free(posix_dirpath);
+
+                const header = try Header.fromStat(stat, posix_dirpath);
+                try self.writer.writeAll(std.mem.asBytes(&header));
+            }
+        }
+
+        /// prefix is a path to prepend subpath with
+        pub fn addFile(
+            self: *Self,
+            root: std.fs.Dir,
+            prefix: ?[]const u8,
+            subpath: []const u8,
+        ) !void {
+            const allocator = self.arena.child_allocator;
+            const path = if (prefix) |prefix_path|
+                try std.fs.path.join(allocator, &[_][]const u8{ prefix_path, subpath })
+            else
+                subpath;
+            defer if (prefix != null) allocator.free(path);
+
+            const posix_path = try std.mem.replaceOwned(u8, allocator, path, std.fs.path.sep_str_windows, std.fs.path.sep_str_posix);
+            defer allocator.free(posix_path);
+
+            if (std.fs.path.dirname(posix_path)) |dirname|
+                try self.maybeAddDirectories(posix_path[0 .. dirname.len + 1]);
+            const subfile = try root.openFile(subpath, .{ .mode = .read_write });
+            defer subfile.close();
+
+            const stat = try subfile.stat();
+            const header = try Header.fromStat(stat, posix_path);
+            var buf: [std.mem.page_size]u8 = undefined;
+
+            try self.writer.writeAll(std.mem.asBytes(&header));
+            var counter = std.io.countingWriter(self.writer);
+
+            while (true) {
+                const n = try subfile.reader().read(&buf);
+                if (n == 0) break;
+
+                try counter.writer().writeAll(buf[0..n]);
+            }
+
+            const padding = blk: {
+                const mod = counter.bytes_written % 512;
+                break :blk if (mod > 0) 512 - mod else 0;
+            };
+            try self.writer.writeByteNTimes(0, @as(usize, @intCast(padding)));
+        }
+
+        /// add slice of bytes as file `path`
+        pub fn addSlice(self: *Self, slice: []const u8, path: []const u8) !void {
+            const allocator = self.arena.child_allocator;
+            const posix_path = try std.mem.replaceOwned(u8, allocator, path, std.fs.path.sep_str_windows, std.fs.path.sep_str_posix);
+            defer allocator.free(posix_path);
+
+            const stat = std.fs.File.Stat{
+                .inode = undefined,
+                .size = slice.len,
+                .mode = switch (builtin.os.tag) {
+                    .windows => 0,
+                    else => 0o644,
+                },
+                .kind = .File,
+                .atime = undefined,
+                .mtime = std.time.nanoTimestamp(),
+                .ctime = undefined,
+            };
+
+            var header = try Header.fromStat(stat, posix_path);
+            const padding = blk: {
+                const mod = slice.len % 512;
+                break :blk if (mod > 0) 512 - mod else 0;
+            };
+            try self.writer.writeAll(std.mem.asBytes(&header));
+            try self.writer.writeAll(slice);
+            try self.writer.writeByteNTimes(0, padding);
+        }
+    };
+}
+
+pub const PaxHeaderMap = struct {
+    text: []const u8,
+    map: std.StringHashMap([]const u8),
+
+    const Self = @This();
+
+    pub fn init(allocator: Allocator, reader: anytype) !Self {
+        // TODO: header verification
+        const header = try reader.readStruct(Header);
+        if (header.typeflag != .pax_global) return error.NotPaxGlobalHeader;
+
+        const size = try std.fmt.parseInt(usize, &header.size, 8);
+        const text = try allocator.alloc(u8, size);
+        errdefer allocator.free(text);
+
+        var i: usize = 0;
+        while (i < size) : (i = try reader.read(text[i..])) {}
+
+        var map = std.StringHashMap([]const u8).init(allocator);
+        errdefer map.deinit();
+
+        var it = std.mem.tokenize(u8, text, "\n");
+        while (it.next()) |line| {
+            const begin = (std.mem.indexOf(u8, line, " ") orelse return error.BadMapEntry) + 1;
+            const eql = std.mem.indexOf(u8, line[begin..], "=") orelse return error.BadMapEntry;
+            try map.put(line[begin .. begin + eql], line[begin + eql + 1 ..]);
+        }
+
+        return Self{
+            .text = text,
+            .map = map,
+        };
+    }
+
+    pub fn get(self: Self, key: []const u8) ?[]const u8 {
+        return self.map.get(key);
+    }
+
+    pub fn deinit(self: *Self) void {
+        self.map.allocator.free(self.text);
+        self.map.deinit();
+    }
+};
+
+pub fn fileExtractor(path: []const u8, reader: anytype) FileExtractor(@TypeOf(reader)) {
+    return FileExtractor(@TypeOf(reader)).init(path, reader);
+}
+
+pub fn FileExtractor(comptime ReaderType: type) type {
+    return struct {
+        path: []const u8,
+        internal: ReaderType,
+        len: ?usize,
+
+        const Self = @This();
+
+        pub fn init(path: []const u8, internal: ReaderType) Self {
+            return Self{
+                .path = path,
+                .internal = internal,
+                .len = null,
+            };
+        }
+
+        pub const Error = ReaderType.Error || error{ FileNotFound, EndOfStream } || std.fmt.ParseIntError;
+        pub const Reader = std.io.Reader(*Self, Error, read);
+
+        pub fn read(self: *Self, buf: []u8) Error!usize {
+            if (self.len == null) {
+                while (true) {
+                    const header = try self.internal.readStruct(Header);
+                    for (std.mem.asBytes(&header)) |c| {
+                        if (c != 0) break;
+                    } else return error.FileNotFound;
+                    const size = try std.fmt.parseInt(usize, &header.size, 8);
+                    const name = header.name[0 .. std.mem.indexOf(u8, &header.name, "\x00") orelse header.name.len];
+                    if (std.mem.eql(u8, name, self.path)) {
+                        self.len = size;
+                        break;
+                    } else if (size > 0) {
+                        try self.internal.skipBytes(size + (512 - (size % 512)), .{});
+                    }
+                }
+            }
+
+            const n = try self.internal.read(buf[0..std.math.min(self.len.?, buf.len)]);
+            self.len.? -= n;
+            return n;
+        }
+
+        pub fn reader(self: *Self) Reader {
+            return .{ .context = self };
+        }
+    };
+}

From 6eccd8fd956b984327988faeff9f3f3fce914134 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 12:54:33 +0100
Subject: [PATCH 251/286] Implements board-support info extraction that
 inspects (and validates) the build.zig file for BSPs

---
 board-support/espressif-esp/build.zig         |   4 +
 board-support/espressif-esp/extract-bsp-info  | Bin 0 -> 2062248 bytes
 .../espressif-esp/extract-bsp-info.o          | Bin 0 -> 1969032 bytes
 board-support/microchip-atsam/build.zig       |  33 +++---
 board-support/raspberrypi-rp2040/build.zig    |   2 +-
 board-support/stmicro-stm32/build.zig         |   2 +-
 tools/bundle.sh                               |  16 ++-
 tools/create-package.sh                       |   3 -
 tools/extract-bsp-info.zig                    | 102 ++++++++++++++++++
 tools/lib/dummy_uf2.zig                       |   5 +
 10 files changed, 148 insertions(+), 19 deletions(-)
 create mode 100755 board-support/espressif-esp/extract-bsp-info
 create mode 100644 board-support/espressif-esp/extract-bsp-info.o
 create mode 100644 tools/extract-bsp-info.zig
 create mode 100644 tools/lib/dummy_uf2.zig

diff --git a/board-support/espressif-esp/build.zig b/board-support/espressif-esp/build.zig
index 089066cbd..d1b62ccf5 100644
--- a/board-support/espressif-esp/build.zig
+++ b/board-support/espressif-esp/build.zig
@@ -47,6 +47,10 @@ pub const chips = struct {
     };
 };
 
+pub const boards = struct {
+    // empty right now
+};
+
 pub fn build(b: *std.Build) void {
     _ = b;
     // const optimize = b.standardOptimizeOption(.{});
diff --git a/board-support/espressif-esp/extract-bsp-info b/board-support/espressif-esp/extract-bsp-info
new file mode 100755
index 0000000000000000000000000000000000000000..e805c7e173d96d164d07c2876b7c1472a904866c
GIT binary patch
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zN80Rj(Z@PN&mVc8Mcf2^NAxlCt#pEb$KI0kk4{U#Fzn?+_piWdx~64}OcpKBhI+Ad
zZujLlfB25@SJJS6<{xK%)c<+$zjRU_Aj4klqp1C#DaZBy{ocjdL^C%WWGAiP&-|GF
z+Vl~}seKiyVJPvT_0J}v-^IcQHxpzrGdMpD5`!M-;XG
z&;!S>hFvB~J-@OFr-IN&bddQm|4ZI~{kmit2HR2a(bvU$asNMmi2tc;p)>9O3G-w6
mmAA5g?Ve!uk45y${QV3SIElwtkNiI``TetHiu{w-{{I6^1{l}?

literal 0
HcmV?d00001

diff --git a/board-support/microchip-atsam/build.zig b/board-support/microchip-atsam/build.zig
index 3cbb87b94..d9dbf958e 100644
--- a/board-support/microchip-atsam/build.zig
+++ b/board-support/microchip-atsam/build.zig
@@ -11,19 +11,28 @@ fn root() []const u8 {
 
 const build_root = root();
 
+pub const chip_atsamd51j19 = .{
+    .name = "ATSAMD51J19A",
+    .url = "https://www.microchip.com/en-us/product/ATSAMD51J19A",
+    .cpu = .cortex_m4,
+    .register_definition = .{
+        .atdf = .{ .path = build_root ++ "/src/chips/ATSAMD51J19A.atdf" },
+    },
+    .memory_regions = &.{
+        .{ .kind = .flash, .offset = 0x00004000, .length = 512 * 1024 }, // Embedded Flash
+        .{ .kind = .ram, .offset = 0x20000000, .length = 192 * 1024 }, // Embedded SRAM
+        .{ .kind = .ram, .offset = 0x47000000, .length = 8 * 1024 }, // Backup SRAM
+        .{ .kind = .flash, .offset = 0x00804000, .length = 512 }, // NVM User Row
+    },
+};
+
 pub const chips = struct {
     pub const atsamd51j19 = .{
-        .name = "ATSAMD51J19A",
-        .url = "https://www.microchip.com/en-us/product/ATSAMD51J19A",
-        .cpu = .cortex_m4,
-        .register_definition = .{
-            .atdf = .{ .path = build_root ++ "/src/chips/ATSAMD51J19A.atdf" },
-        },
-        .memory_regions = &.{
-            .{ .kind = .flash, .offset = 0x00004000, .length = 512 * 1024 }, // Embedded Flash
-            .{ .kind = .ram, .offset = 0x20000000, .length = 192 * 1024 }, // Embedded SRAM
-            .{ .kind = .ram, .offset = 0x47000000, .length = 8 * 1024 }, // Backup SRAM
-            .{ .kind = .flash, .offset = 0x00804000, .length = 512 }, // NVM User Row
-        },
+        .preferred_format = .elf,
+        .chip = chip_atsamd51j19,
     };
 };
+
+pub const boards = struct {
+    // empty right now
+};
diff --git a/board-support/raspberrypi-rp2040/build.zig b/board-support/raspberrypi-rp2040/build.zig
index cb3c13fcf..05fdad2e6 100644
--- a/board-support/raspberrypi-rp2040/build.zig
+++ b/board-support/raspberrypi-rp2040/build.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("root").dependencies.imports.microzig; // HACK: Please import MicroZig always under the name `microzig`. Otherwise the RP2040 module will fail to be properly imported.
+const microzig = @import("microzig");
 
 fn root() []const u8 {
     return comptime (std.fs.path.dirname(@src().file) orelse ".");
diff --git a/board-support/stmicro-stm32/build.zig b/board-support/stmicro-stm32/build.zig
index 410578209..dcbf169ab 100644
--- a/board-support/stmicro-stm32/build.zig
+++ b/board-support/stmicro-stm32/build.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("root").dependencies.imports.microzig; // HACK: Please import MicroZig always under the name `microzig`. Otherwise the RP2040 module will fail to be properly imported.
+const microzig = @import("microzig");
 
 fn root() []const u8 {
     return comptime (std.fs.path.dirname(@src().file) orelse ".");
diff --git a/tools/bundle.sh b/tools/bundle.sh
index 22b94eef9..fbb61f60e 100755
--- a/tools/bundle.sh
+++ b/tools/bundle.sh
@@ -86,6 +86,7 @@ for dir in $(find -type f -name microzig-package.json -exec dirname '{}' ';'); d
 
         out_dir=""
         out_basename=""
+        extra_json="{}"
 
         case "${pkg_type}" in
             core)
@@ -96,6 +97,17 @@ for dir in $(find -type f -name microzig-package.json -exec dirname '{}' ';'); d
             board-support)
                 out_dir="${deploy_target}/board-support/$(dirname "${pkg_name}")"
                 out_basename="$(basename "${pkg_name}")"
+
+                extra_json="$(
+                    zig run \
+                        "${repo_root}/tools/extract-bsp-info.zig" \
+                        --cache-dir "${repo_root}/zig-cache" \
+                        --deps bsp,microzig \
+                        --mod "bsp:microzig:${dir}/build.zig" \
+                        --mod "microzig:uf2:${repo_root}/core/build.zig" \
+                        --mod "uf2::${repo_root}/tools/lib/dummy_uf2.zig" \
+                )"
+
                 ;;
 
             *)
@@ -132,7 +144,8 @@ for dir in $(find -type f -name microzig-package.json -exec dirname '{}' ';'); d
             --arg fhash "${file_hash}" \
             --arg fsize "${file_size}" \
             --argjson pkg "${pkg_info}" \
-                '. + {
+            --argjson extra "${extra_json}" \
+                '. + $extra + {
                     version: $vers,
                     created: {
                         unix: $ts_unix,
@@ -152,6 +165,5 @@ for dir in $(find -type f -name microzig-package.json -exec dirname '{}' ';'); d
             ln -s "${all_files_dir}/${out_fullname}" "${out_name}"
             ln -s "${all_files_dir}/${out_fullmeta}" "${out_meta}"
         )
-
     )
 done
diff --git a/tools/create-package.sh b/tools/create-package.sh
index e22a67c8f..0dd9e821f 100755
--- a/tools/create-package.sh
+++ b/tools/create-package.sh
@@ -40,6 +40,3 @@ fi
     # https://stackoverflow.com/a/53083343
     tar -caf "${output_file}" $(git ls-files -- . ':!:microzig-package.json')
 )
-
-# echo "included files:"
-# tar -tf "${output_file}"
diff --git a/tools/extract-bsp-info.zig b/tools/extract-bsp-info.zig
new file mode 100644
index 000000000..565c3d0cb
--- /dev/null
+++ b/tools/extract-bsp-info.zig
@@ -0,0 +1,102 @@
+//!
+//! A tool that extracs which chips and boards are avaiilable from a board support package
+//! and validates that the declarations conform
+//!
+
+const std = @import("std");
+const bsp = @import("bsp");
+const microzig = @import("microzig");
+
+const JsonTarget = struct {
+    id: []const u8,
+
+    output_format: ?[]const u8,
+
+    features: struct {
+        hal: bool,
+    },
+
+    memory: struct {
+        flash: u64,
+        ram: u64,
+    },
+
+    cpu: []const u8,
+
+    chip: []const u8,
+    chip_url: ?[]const u8,
+
+    board: ?[]const u8,
+    board_url: ?[]const u8,
+};
+
+fn renderMicroZigTarget(stream: anytype, key: []const u8, target: microzig.Target) !void {
+    var jtarget = JsonTarget{
+        .id = key,
+
+        .output_format = if (target.preferred_format) |fmt| @tagName(fmt) else null,
+
+        .features = .{
+            .hal = (target.hal != null),
+        },
+
+        .cpu = @tagName(target.chip.cpu),
+
+        .chip = target.chip.name,
+        .chip_url = target.chip.url,
+
+        .board = null,
+        .board_url = null,
+
+        .memory = .{
+            .flash = 0,
+            .ram = 0,
+        },
+    };
+
+    if (target.board) |brd| {
+        jtarget.board = brd.name;
+        jtarget.board_url = brd.url;
+    }
+
+    for (target.chip.memory_regions) |reg| {
+        switch (reg.kind) {
+            .flash => jtarget.memory.flash += reg.length,
+            .ram => jtarget.memory.flash += reg.length,
+            else => {},
+        }
+    }
+
+    try std.json.stringify(jtarget, .{}, stream);
+}
+
+fn renderTargetArray(stream: anytype, comptime array: type) !void {
+    inline for (comptime std.meta.declarations(array), 0..) |fld, i| {
+        if (i > 0) try stream.writeAll(",");
+        const target = comptime @field(array, fld.name);
+
+        if (@TypeOf(target) == type) {
+            // recurse
+            try renderTargetArray(stream, target);
+        } else {
+            try renderMicroZigTarget(
+                stream,
+                fld.name,
+                target,
+            );
+        }
+    }
+}
+
+pub fn main() !void {
+    var stdout = std.io.getStdOut().writer();
+
+    try stdout.writeAll("{ \"board-support\": {");
+
+    try stdout.writeAll("\"chips\":[");
+    try renderTargetArray(stdout, bsp.chips);
+    try stdout.writeAll("],\"boards\":[");
+    try renderTargetArray(stdout, bsp.boards);
+
+    try stdout.writeAll("]}}");
+}
diff --git a/tools/lib/dummy_uf2.zig b/tools/lib/dummy_uf2.zig
new file mode 100644
index 000000000..3e50f6105
--- /dev/null
+++ b/tools/lib/dummy_uf2.zig
@@ -0,0 +1,5 @@
+//!
+//! Only required for the BSP info tooling, fakes everything we need to make the build work
+//!
+
+pub const FamilyId = enum { RP2040 };

From 2f6a61e6ae2f72957cd846c6512e819231dfdcc2 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 12:58:26 +0100
Subject: [PATCH 252/286] Fixes GitHub CI

---
 .github/workflows/build.yml | 46 ++++++++++++++++++-------------------
 tools/bundle.sh             |  8 +++----
 tools/create-package.sh     |  2 +-
 3 files changed, 28 insertions(+), 28 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 720973f40..e697a7464 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -1,4 +1,5 @@
-name: Build
+name: Continuous Integration
+
 on:
   push:
     branches: [main]
@@ -6,33 +7,32 @@ on:
     branches: [main]
 
 jobs:
-  build:
-    runs-on: ${{ matrix.os }}
-    strategy:
-      fail-fast: false
-      matrix:
-        dir:
-          - all-platforms
-          - raspberrypi-rp2040
-          - espressif-esp
-          - nxp-lpc
-          - microchip-atmega
-          - gigadevice-gd32
-          - nordic-nrf5x
-          - stmicro-stm32
-        os:
-          - windows-latest
-          - macos-latest
-          - ubuntu-latest
+  generate-packages:
+    runs-on: ubuntu-latest
     steps:
       - name: Checkout
-        uses: actions/checkout@v2
+        uses: actions/checkout@v4
+        with:
+          fetch-tags: true # required for "git describe"
+
+      - name: Fetch more data from git
+        run: |
+          # fetch everything back till the 0.11.0 tag.
+          # https://stackoverflow.com/a/58082274
+          git fetch --shallow-exclude 0.11.0
+          git fetch --deepen=2
 
       - name: Setup Zig
         uses: goto-bus-stop/setup-zig@v2
         with:
           version: 0.11.0
 
-      - name: Build examples
-        working-directory: ${{ matrix.dir }}
-        run: zig build
+      - name: Generate and validate packages
+        run: |
+          ./tools/bundle.sh
+
+      - name: Upload artifacts
+        uses: actions/upload-artifact@v4
+        with:
+          name: packages
+          path: microzig-deploy/
diff --git a/tools/bundle.sh b/tools/bundle.sh
index fbb61f60e..3f19239f1 100755
--- a/tools/bundle.sh
+++ b/tools/bundle.sh
@@ -5,14 +5,14 @@
 # Creates all packages into /microzig-deploy with the final folder structure.
 #
 
-set -euo pipefail
+set -eu
 
 all_files_dir=".data"
 
 # test for all required tools:
 which zig date find jq mkdir dirname realpath > /dev/null
 
-[ "$(zig version)" == "0.11.0" ]
+[ "$(zig version)" = "0.11.0" ]
 
 repo_root="$(dirname "$(dirname "$(realpath "$0")")")"
 [ -d "${repo_root}" ]
@@ -32,7 +32,7 @@ git_description="$(git describe --match "*.*.*" --tags --abbrev=9)"
 version=""
 
 # render-version     
-function render_version()
+render_version()
 {
     [ "$#" -eq 5 ] 
     echo "$1.$2.$3-$4-$5"
@@ -132,7 +132,7 @@ for dir in $(find -type f -name microzig-package.json -exec dirname '{}' ';'); d
         create_package "${dir}" "${out_path}"
 
         # get some required metadata
-        file_hash=($(sha256sum "${out_path}" | cut -f 1))
+        file_hash="$(sha256sum "${out_path}" | cut -d " " -f 1)"
         file_size="$(stat --format="%s" "${out_path}")"
 
         pkg_info="$(archive_info ${out_path})"
diff --git a/tools/create-package.sh b/tools/create-package.sh
index 0dd9e821f..1eaf96b80 100755
--- a/tools/create-package.sh
+++ b/tools/create-package.sh
@@ -1,6 +1,6 @@
 #!/bin/sh
 
-set -euo pipefail
+set -eu
 
 # test for all required tools:
 which tar gzip jq basename dirname realpath > /dev/null

From 3fdc016ef368fc6e75f665c0e6c388530480f4df Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 4 Jan 2024 13:50:35 +0100
Subject: [PATCH 253/286] Adds CI to readme.

---
 README.md | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/README.md b/README.md
index 289bc4454..db1040d1d 100644
--- a/README.md
+++ b/README.md
@@ -1,5 +1,7 @@
 # MicroZig
 
+[![Continuous Integration](https://github.com/ZigEmbeddedGroup/microzig-monorepo/actions/workflows/build.yml/badge.svg)](https://github.com/ZigEmbeddedGroup/microzig-monorepo/actions/workflows/build.yml)
+
 ## Overview
 
 - `core/` contains the shared components of MicroZig.
@@ -17,3 +19,12 @@ Zigs versions, but with our own commit abbreviations and counters.
 As MicroZig sticks to tagged Zig releases, `${zig_version}` will show to which Zig version the MicroZig build is compatible.
 
 Consider the version `0.11.0-abcdef-123` means that this MicroZig version has a commit starting with `abcdef`, which was the 123rd commit of the version that is compatible with Zig 0.11.0.
+
+## TODO (before exchanging upstream)
+
+- Integrate https://github.com/ZigEmbeddedGroup/microzig-driver-framework as package
+- Create support for nice GitHub badges
+- validate that the table on https://github.com/ZigEmbeddedGroup is correct (in CI)
+- make system build again properly
+- start porting everything to 0.12/unstable
+

From bb2b13227b1d2d4a0735dfce4ac32584b59623b5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sun, 7 Jan 2024 20:56:48 +0100
Subject: [PATCH 254/286] Snapshot for transfer

---
 build/README.md                 |   4 +
 build/build.zig                 | 979 ++++++++++++++++++++++++++++++++
 build/build.zig.zon             |  29 +
 build/microzig-package.json     |   4 +
 examples/modular/README.md      |   5 +
 examples/modular/build.zig      |  33 ++
 examples/modular/build.zig.zon  |  14 +
 examples/modular/src/blinky.zig |  56 ++
 8 files changed, 1124 insertions(+)
 create mode 100644 build/README.md
 create mode 100644 build/build.zig
 create mode 100644 build/build.zig.zon
 create mode 100644 build/microzig-package.json
 create mode 100644 examples/modular/README.md
 create mode 100644 examples/modular/build.zig
 create mode 100644 examples/modular/build.zig.zon
 create mode 100644 examples/modular/src/blinky.zig

diff --git a/build/README.md b/build/README.md
new file mode 100644
index 000000000..0f1955c0d
--- /dev/null
+++ b/build/README.md
@@ -0,0 +1,4 @@
+# MicroZig Build Support
+
+This package is meant to provide build utilities to create embedded firmware easily.
+
diff --git a/build/build.zig b/build/build.zig
new file mode 100644
index 000000000..748833fd4
--- /dev/null
+++ b/build/build.zig
@@ -0,0 +1,979 @@
+//! Some words on the build script here:
+//! We cannot use a test runner here as we're building for freestanding.
+//! This means we need to use addExecutable() instead of using
+
+const std = @import("std");
+const uf2 = @import("uf2");
+
+////////////////////////////////////////
+//      MicroZig Gen 2 Interface      //
+////////////////////////////////////////
+
+fn root() []const u8 {
+    return comptime (std.fs.path.dirname(@src().file) orelse ".");
+}
+const build_root = root();
+
+const MicroZig = @This();
+
+b: *std.Build,
+self: *std.Build.Dependency,
+
+/// Creates a new instance of the MicroZig build support.
+///
+/// This is necessary as we need to keep track of some internal state to prevent
+/// duplicated work per firmware built.
+pub fn init(b: *std.Build, dependency_name: []const u8) *MicroZig {
+    const mz = b.allocator.create(MicroZig) catch @panic("out of memory");
+    mz.* = MicroZig{
+        .b = b,
+        .self = b.dependency(dependency_name, .{}),
+    };
+    return mz;
+}
+
+/// This build script validates usage patterns we expect from MicroZig
+pub fn build(b: *std.Build) !void {
+    const uf2_dep = b.dependency("uf2", .{});
+
+    const build_test = b.addTest(.{
+        .root_source_file = .{ .path = "build.zig" },
+    });
+
+    build_test.addAnonymousModule("uf2", .{
+        .source_file = .{ .cwd_relative = uf2_dep.builder.pathFromRoot("build.zig") },
+    });
+
+    const install_docs = b.addInstallDirectory(.{
+        .source_dir = build_test.getEmittedDocs(),
+        .install_dir = .prefix,
+        .install_subdir = "docs",
+    });
+
+    b.getInstallStep().dependOn(&install_docs.step);
+
+    // const backings = @import("test/backings.zig");
+    // const optimize = b.standardOptimizeOption(.{});
+
+    // const minimal = addEmbeddedExecutable(b, .{
+    //     .name = "minimal",
+    //     .source_file = .{
+    //         .path = comptime root_dir() ++ "/test/programs/minimal.zig",
+    //     },
+    //     .backing = backings.minimal,
+    //     .optimize = optimize,
+    // });
+
+    // const has_hal = addEmbeddedExecutable(b, .{
+    //     .name = "has_hal",
+    //     .source_file = .{
+    //         .path = comptime root_dir() ++ "/test/programs/has_hal.zig",
+    //     },
+    //     .backing = backings.has_hal,
+    //     .optimize = optimize,
+    // });
+
+    // const has_board = addEmbeddedExecutable(b, .{
+    //     .name = "has_board",
+    //     .source_file = .{
+    //         .path = comptime root_dir() ++ "/test/programs/has_board.zig",
+    //     },
+    //     .backing = backings.has_board,
+    //     .optimize = optimize,
+    // });
+
+    // const core_tests = b.addTest(.{
+    //     .root_source_file = .{
+    //         .path = comptime root_dir() ++ "/src/core.zig",
+    //     },
+    //     .optimize = optimize,
+    // });
+
+    // const test_step = b.step("test", "build test programs");
+    // test_step.dependOn(&minimal.inner.step);
+    // test_step.dependOn(&has_hal.inner.step);
+    // test_step.dependOn(&has_board.inner.step);
+    // test_step.dependOn(&b.addRunArtifact(core_tests).step);
+}
+
+/// The resulting binary format for the firmware file.
+/// A lot of embedded systems don't use plain ELF files, thus we provide means
+/// to convert the resulting ELF into other common formats.
+pub const BinaryFormat = union(enum) {
+    /// [Executable and Linkable Format](https://en.wikipedia.org/wiki/Executable_and_Linkable_Format), the standard output from the compiler.
+    elf,
+
+    /// A flat binary, contains only the loaded portions of the firmware with an unspecified base offset.
+    bin,
+
+    /// The [Intel HEX](https://en.wikipedia.org/wiki/Intel_HEX) format, contains
+    /// an ASCII description of what memory to load where.
+    hex,
+
+    /// A [Device Firmware Upgrade](https://www.usb.org/sites/default/files/DFU_1.1.pdf) file.
+    dfu,
+
+    /// The [USB Flashing Format (UF2)](https://github.com/microsoft/uf2) designed by Microsoft.
+    uf2: uf2.FamilyId,
+
+    /// The [firmware format](https://docs.espressif.com/projects/esptool/en/latest/esp32/advanced-topics/firmware-image-format.html) used by the [esptool](https://github.com/espressif/esptool) bootloader.
+    esp,
+
+    /// Custom option for non-standard formats.
+    custom: *Custom,
+
+    /// Returns the standard extension for the resulting binary file.
+    pub fn getExtension(format: BinaryFormat) []const u8 {
+        return switch (format) {
+            .elf => ".elf",
+            .bin => ".bin",
+            .hex => ".hex",
+            .dfu => ".dfu",
+            .uf2 => ".uf2",
+            .esp => ".bin",
+
+            .custom => |c| c.extension,
+        };
+    }
+
+    pub const Custom = struct {
+        /// The standard extension of the format.
+        extension: []const u8,
+
+        /// A function that will convert a given `elf` file into the custom output format.
+        ///
+        /// The `*Custom` format is passed so contextual information can be obtained by using
+        /// `@fieldParentPtr` to provide access to tooling.
+        convert: *const fn (*Custom, elf: std.Build.LazyPath) std.Build.LazyPath,
+    };
+
+    const Enum = std.meta.Tag(BinaryFormat);
+
+    const Context = struct {
+        pub fn hash(self: @This(), fmt: BinaryFormat) u32 {
+            _ = self;
+
+            var hasher = std.hash.XxHash32.init(0x1337_42_21);
+
+            hasher.update(@tagName(fmt));
+
+            switch (fmt) {
+                .elf, .bin, .hex, .dfu, .esp => |val| {
+                    if (@TypeOf(val) != void) @compileError("Missing update: Context.hash now requires special care!");
+                },
+
+                .uf2 => |family_id| hasher.update(@tagName(family_id)),
+                .custom => |custom| hasher.update(std.mem.asBytes(custom)),
+            }
+
+            return hasher.final();
+        }
+
+        pub fn eql(self: @This(), fmt_a: BinaryFormat, fmt_b: BinaryFormat, index: usize) bool {
+            _ = self;
+            _ = index;
+            if (@as(BinaryFormat.Enum, fmt_a) != @as(BinaryFormat.Enum, fmt_b))
+                return false;
+
+            return switch (fmt_a) {
+                .elf, .bin, .hex, .dfu, .esp => |val| {
+                    if (@TypeOf(val) != void) @compileError("Missing update: Context.eql now requires special care!");
+                    return true;
+                },
+
+                .uf2 => |a| (a == fmt_b.uf2),
+                .custom => |a| (a == fmt_b.custom),
+            };
+        }
+    };
+};
+
+/// The CPU model a target uses.
+///
+/// The CPUs usually require special care on how to do interrupts, and getting an entry point.
+///
+/// MicroZig officially only supports the CPUs listed here, but other CPUs might be provided
+/// via the `custom` field.
+pub const CpuModel = union(enum) {
+    avr5,
+    cortex_m0,
+    cortex_m0plus,
+    cortex_m3,
+    cortex_m4,
+    riscv32_imac,
+
+    custom: *const Cpu,
+
+    pub fn getDescriptor(model: CpuModel) *const Cpu {
+        return switch (@as(std.meta.Tag(CpuModel), model)) {
+            inline else => |tag| &@field(cpus, @tagName(tag)),
+            .custom => model.custom,
+        };
+    }
+};
+
+/// A cpu descriptor.
+pub const Cpu = struct {
+    /// Display name of the CPU.
+    name: []const u8,
+
+    /// Source file providing startup code and memory initialization routines.
+    source_file: std.build.LazyPath,
+
+    /// The compiler target we use to compile all the code.
+    target: std.zig.CrossTarget,
+};
+
+/// A descriptor for memory regions in a microcontroller.
+pub const MemoryRegion = struct {
+    /// The type of the memory region for generating a proper linker script.
+    kind: Kind,
+    offset: u64,
+    length: u64,
+
+    pub const Kind = union(enum) {
+        /// This is a (normally) immutable memory region where the code is stored.
+        flash,
+
+        /// This is a mutable memory region for data storage.
+        ram,
+
+        /// This is a memory region that maps MMIO devices.
+        io,
+
+        /// This is a memory region that exists, but is reserved and must not be used.
+        reserved,
+
+        /// This is a memory region used for internal linking tasks required by the board support package.
+        private: PrivateRegion,
+    };
+
+    pub const PrivateRegion = struct {
+        /// The name of the memory region. Will not have an automatic numeric counter and must be unique.
+        name: []const u8,
+
+        /// Is the memory region executable?
+        executable: bool,
+
+        /// Is the memory region readable?
+        readable: bool,
+
+        /// Is the memory region writable?
+        writeable: bool,
+    };
+};
+
+/// Defines a custom microcontroller.
+pub const Chip = struct {
+    /// The display name of the controller.
+    name: []const u8,
+
+    /// (optional) link to the documentation/vendor page of the controller.
+    url: ?[]const u8 = null,
+
+    /// The cpu model this controller uses.
+    cpu: CpuModel,
+
+    /// The provider for register definitions.
+    register_definition: union(enum) {
+        /// Use `regz` to create a zig file from a JSON schema.
+        json: std.Build.LazyPath,
+
+        /// Use `regz` to create a json file from a SVD schema.
+        svd: std.Build.LazyPath,
+
+        /// Use `regz` to create a zig file from an ATDF schema.
+        atdf: std.Build.LazyPath,
+
+        /// Use the provided file directly as the chip file.
+        zig: std.Build.LazyPath,
+    },
+
+    /// The memory regions that are present in this chip.
+    memory_regions: []const MemoryRegion,
+};
+
+/// Defines a hardware abstraction layer.
+pub const HardwareAbstractionLayer = struct {
+    /// Root source file for this HAL.
+    source_file: std.Build.LazyPath,
+};
+
+/// Provides a description of a board.
+///
+/// Boards provide additional information to a chip and HAL package.
+/// For example, they can list attached peripherials, external crystal frequencies,
+/// flash sizes, ...
+pub const BoardDefinition = struct {
+    /// Display name of the board
+    name: []const u8,
+
+    /// (optional) link to the documentation/vendor page of the board.
+    url: ?[]const u8 = null,
+
+    /// Provides the root file for the board definition.
+    source_file: std.Build.LazyPath,
+};
+
+/// The linker script used to link the firmware.
+pub const LinkerScript = union(enum) {
+    /// Auto-generated linker script derived from the memory regions of the chip.
+    generated,
+
+    /// Externally defined linker script.
+    source_file: std.build.LazyPath,
+};
+
+/// A compilation target for MicroZig. Provides information about the chip,
+/// hal, board and so on.
+///
+/// This is used instead of `std.zig.CrossTarget` to define a MicroZig Firmware.
+pub const Target = struct {
+    /// The preferred binary format of this MicroZig target. If `null`, the user must
+    /// explicitly give the `.format` field during a call to `getEmittedBin()` or installation steps.
+    preferred_format: ?BinaryFormat,
+
+    /// The chip this target uses,
+    chip: Chip,
+
+    /// Usually, embedded projects are single-threaded and single-core applications. Platforms that
+    /// support multiple CPUs should set this to `false`.
+    single_threaded: bool = true,
+
+    /// Determines whether the compiler_rt package is bundled with the application or not.
+    /// This should always be true except for platforms where compiler_rt cannot be built right now.
+    bundle_compiler_rt: bool = true,
+
+    /// (optional) Provides a default hardware abstraction layer that is used.
+    /// If `null`, no `microzig.hal` will be available.
+    hal: ?HardwareAbstractionLayer = null,
+
+    /// (optional) Provides description of external hardware and connected devices
+    /// like oscillators and such.
+    ///
+    /// This structure isn't used by MicroZig itself, but can be utilized from the HAL
+    /// if present.
+    board: ?BoardDefinition = null,
+
+    /// (optional) Provide a custom linker script for the hardware or define a custom generation.
+    linker_script: LinkerScript = .generated,
+
+    /// (optional) Further configures the created firmware depending on the chip and/or board settings.
+    /// This can be used to set/change additional properties on the created `*Firmware` object.
+    configure: ?*const fn (host_build: *std.Build, *Firmware) void = null,
+
+    /// (optional) Post processing step that will patch up and modify the elf file if necessary.
+    binary_post_process: ?*const fn (host_build: *std.Build, std.Build.LazyPath) std.Build.LazyPath = null,
+};
+
+/// Options to the `addFirmware` function.
+pub const FirmwareOptions = struct {
+    /// The name of the firmware file.
+    name: []const u8,
+
+    /// The MicroZig target that the firmware is built for. Either a board or a chip.
+    target: Target,
+
+    /// The optimization level that should be used. Usually `ReleaseSmall` or `Debug` is a good choice.
+    /// Also using `std.Build.standardOptimizeOption` is a good idea.
+    optimize: std.builtin.OptimizeMode,
+
+    /// The root source file for the application. This is your `src/main.zig` file.
+    source_file: std.Build.LazyPath,
+
+    // Overrides:
+
+    /// If set, overrides the `single_threaded` property of the target.
+    single_threaded: ?bool = null,
+
+    /// If set, overrides the `bundle_compiler_rt` property of the target.
+    bundle_compiler_rt: ?bool = null,
+
+    /// If set, overrides the `hal` property of the target.
+    hal: ?HardwareAbstractionLayer = null,
+
+    /// If set, overrides the `board` property of the target.
+    board: ?BoardDefinition = null,
+
+    /// If set, overrides the `linker_script` property of the target.
+    linker_script: ?LinkerScript = null,
+};
+
+/// Declares a new MicroZig firmware file.
+pub fn addFirmware(
+    /// The MicroZig instance that should be used to create the firmware.
+    mz: *MicroZig,
+    /// The instance of the `build.zig` that is calling this function.
+    host_build: *std.Build,
+    /// Options that define how the firmware is built.
+    options: FirmwareOptions,
+) *Firmware {
+    const micro_build = mz.self.builder;
+
+    const chip = &options.target.chip;
+    const cpu = chip.cpu.getDescriptor();
+    const maybe_hal = options.hal orelse options.target.hal;
+    const maybe_board = options.board orelse options.target.board;
+
+    const linker_script = options.linker_script orelse options.target.linker_script;
+
+    // TODO: let the user override which ram section to use the stack on,
+    // for now just using the first ram section in the memory region list
+    const first_ram = blk: {
+        for (chip.memory_regions) |region| {
+            if (region.kind == .ram)
+                break :blk region;
+        } else @panic("no ram memory region found for setting the end-of-stack address");
+    };
+
+    // On demand, generate chip definitions via regz:
+    const chip_source = switch (chip.register_definition) {
+        .json, .atdf, .svd => |file| blk: {
+            const regz_exe = mz.dependency("regz", .{ .optimize = .ReleaseSafe }).artifact("regz");
+
+            const regz_gen = host_build.addRunArtifact(regz_exe);
+
+            regz_gen.addArg("--schema"); // Explicitly set schema type, one of: svd, atdf, json
+            regz_gen.addArg(@tagName(chip.register_definition));
+
+            regz_gen.addArg("--output_path"); // Write to a file
+            const zig_file = regz_gen.addOutputFileArg("chip.zig");
+
+            regz_gen.addFileArg(file);
+
+            break :blk zig_file;
+        },
+
+        .zig => |src| src,
+    };
+
+    const config = host_build.addOptions();
+    config.addOption(bool, "has_hal", (maybe_hal != null));
+    config.addOption(bool, "has_board", (maybe_board != null));
+
+    config.addOption(?[]const u8, "board_name", if (maybe_board) |brd| brd.name else null);
+
+    config.addOption([]const u8, "chip_name", chip.name);
+    config.addOption([]const u8, "cpu_name", chip.name);
+    config.addOption(usize, "end_of_stack", first_ram.offset + first_ram.length);
+
+    const fw: *Firmware = host_build.allocator.create(Firmware) catch @panic("out of memory");
+    fw.* = Firmware{
+        .mz = mz,
+        .host_build = host_build,
+        .artifact = host_build.addExecutable(.{
+            .name = options.name,
+            .optimize = options.optimize,
+            .target = cpu.target,
+            .linkage = .static,
+            .root_source_file = .{ .cwd_relative = mz.self.builder.pathFromRoot("src/start.zig") },
+        }),
+        .target = options.target,
+        .output_files = Firmware.OutputFileMap.init(host_build.allocator),
+
+        .config = config,
+
+        .modules = .{
+            .microzig = micro_build.createModule(.{
+                .source_file = .{ .cwd_relative = micro_build.pathFromRoot("src/microzig.zig") },
+                .dependencies = &.{
+                    .{
+                        .name = "config",
+                        .module = micro_build.createModule(.{ .source_file = config.getSource() }),
+                    },
+                },
+            }),
+
+            .cpu = undefined,
+            .chip = undefined,
+
+            .board = null,
+            .hal = null,
+
+            .app = undefined,
+        },
+    };
+    errdefer fw.output_files.deinit();
+
+    fw.modules.chip = micro_build.createModule(.{
+        .source_file = chip_source,
+        .dependencies = &.{
+            .{ .name = "microzig", .module = fw.modules.microzig },
+        },
+    });
+    fw.modules.microzig.dependencies.put("chip", fw.modules.chip) catch @panic("out of memory");
+
+    fw.modules.cpu = micro_build.createModule(.{
+        .source_file = cpu.source_file,
+        .dependencies = &.{
+            .{ .name = "microzig", .module = fw.modules.microzig },
+        },
+    });
+    fw.modules.microzig.dependencies.put("cpu", fw.modules.cpu) catch @panic("out of memory");
+
+    if (maybe_hal) |hal| {
+        fw.modules.hal = micro_build.createModule(.{
+            .source_file = hal.source_file,
+            .dependencies = &.{
+                .{ .name = "microzig", .module = fw.modules.microzig },
+            },
+        });
+        fw.modules.microzig.dependencies.put("hal", fw.modules.hal.?) catch @panic("out of memory");
+    }
+
+    if (maybe_board) |brd| {
+        fw.modules.board = micro_build.createModule(.{
+            .source_file = brd.source_file,
+            .dependencies = &.{
+                .{ .name = "microzig", .module = fw.modules.microzig },
+            },
+        });
+        fw.modules.microzig.dependencies.put("board", fw.modules.board.?) catch @panic("out of memory");
+    }
+
+    fw.modules.app = host_build.createModule(.{
+        .source_file = options.source_file,
+        .dependencies = &.{
+            .{ .name = "microzig", .module = fw.modules.microzig },
+        },
+    });
+
+    const umm = mz.dependency("umm-zig", .{}).module("umm");
+    fw.modules.microzig.dependencies.put("umm", umm) catch @panic("out of memory");
+
+    fw.artifact.addModule("app", fw.modules.app);
+    fw.artifact.addModule("microzig", fw.modules.microzig);
+
+    fw.artifact.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded
+    fw.artifact.single_threaded = options.single_threaded orelse fw.target.single_threaded;
+    fw.artifact.bundle_compiler_rt = options.bundle_compiler_rt orelse fw.target.bundle_compiler_rt;
+
+    switch (linker_script) {
+        .generated => {
+            fw.artifact.setLinkerScript(
+                generateLinkerScript(host_build, chip.*) catch @panic("out of memory"),
+            );
+        },
+
+        .source_file => |source| {
+            fw.artifact.setLinkerScriptPath(source);
+        },
+    }
+
+    if (options.target.configure) |configure| {
+        configure(host_build, fw);
+    }
+
+    return fw;
+}
+
+/// Configuration options for firmware installation.
+pub const InstallFirmwareOptions = struct {
+    /// Overrides the output format for the binary. If not set, the standard preferred file format for the firmware target is used.
+    format: ?BinaryFormat = null,
+};
+
+/// Adds a new dependency to the `install` step that will install the `firmware` into the folder `$prefix/firmware`.
+pub fn installFirmware(
+    /// The MicroZig instance that was used to create the firmware.
+    mz: *MicroZig,
+    /// The instance of the `build.zig` that should perform installation.
+    b: *std.Build,
+    /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
+    firmware: *Firmware,
+    /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
+    options: InstallFirmwareOptions,
+) void {
+    std.debug.assert(mz == firmware.mz);
+    const install_step = addInstallFirmware(mz, b, firmware, options);
+    b.getInstallStep().dependOn(&install_step.step);
+}
+
+/// Creates a new `std.Build.Step.InstallFile` instance that will install the given firmware to `$prefix/firmware`.
+///
+/// **NOTE:** This does not actually install the firmware yet. You have to add the returned step as a dependency to another step.
+///           If you want to just install the firmware, use `installFirmware` instead!
+pub fn addInstallFirmware(
+    /// The MicroZig instance that was used to create the firmware.
+    mz: *MicroZig,
+    /// The instance of the `build.zig` that should perform installation.
+    b: *std.Build,
+    /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
+    firmware: *Firmware,
+    /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
+    options: InstallFirmwareOptions,
+) *std.Build.Step.InstallFile {
+    const format = firmware.resolveFormat(options.format);
+
+    const basename = b.fmt("{s}{s}", .{
+        firmware.artifact.name,
+        format.getExtension(),
+    });
+
+    _ = mz;
+
+    return b.addInstallFileWithDir(firmware.getEmittedBin(format), .{ .custom = "firmware" }, basename);
+}
+
+/// Declaration of a firmware build.
+pub const Firmware = struct {
+    const OutputFileMap = std.ArrayHashMap(BinaryFormat, std.Build.LazyPath, BinaryFormat.Context, false);
+
+    const Modules = struct {
+        app: *std.Build.Module,
+        cpu: *std.Build.Module,
+        chip: *std.Build.Module,
+        board: ?*std.Build.Module,
+        hal: ?*std.Build.Module,
+        microzig: *std.Build.Module,
+    };
+
+    // privates:
+    mz: *MicroZig,
+    host_build: *std.Build,
+    target: Target,
+    output_files: OutputFileMap,
+
+    // publics:
+
+    /// The artifact that is built by Zig.
+    artifact: *std.Build.Step.Compile,
+
+    /// The options step that provides `microzig.config`. If you need custom configuration, you can add this here.
+    config: *std.Build.Step.Options,
+
+    /// Declaration of the MicroZig modules used by this firmware.
+    modules: Modules,
+
+    /// Path to the emitted elf file, if any.
+    emitted_elf: ?std.Build.LazyPath = null,
+
+    /// Returns the emitted ELF file for this firmware. This is useful if you need debug information
+    /// or want to use a debugger like Segger, ST-Link or similar.
+    ///
+    /// **NOTE:** This is similar, but not equivalent to `std.Build.Step.Compile.getEmittedBin`. The call on the compile step does
+    ///           not include post processing of the ELF files necessary by certain targets.
+    pub fn getEmittedElf(firmware: *Firmware) std.Build.LazyPath {
+        if (firmware.emitted_elf == null) {
+            const raw_elf = firmware.artifact.getEmittedBin();
+            firmware.emitted_elf = if (firmware.target.binary_post_process) |binary_post_process|
+                binary_post_process(firmware.host_build, raw_elf)
+            else
+                raw_elf;
+        }
+        return firmware.emitted_elf.?;
+    }
+
+    /// Returns the emitted binary for this firmware. The file is either in the preferred file format for
+    /// the target or in `format` if not null.
+    ///
+    /// **NOTE:** The file returned here is the same file that will be installed.
+    pub fn getEmittedBin(firmware: *Firmware, format: ?BinaryFormat) std.Build.LazyPath {
+        const actual_format = firmware.resolveFormat(format);
+
+        const gop = firmware.output_files.getOrPut(actual_format) catch @panic("out of memory");
+        if (!gop.found_existing) {
+            const elf_file = firmware.getEmittedElf();
+
+            const basename = firmware.host_build.fmt("{s}{s}", .{
+                firmware.artifact.name,
+                actual_format.getExtension(),
+            });
+
+            gop.value_ptr.* = switch (actual_format) {
+                .elf => elf_file,
+
+                .bin => blk: {
+                    const objcopy = firmware.host_build.addObjCopy(elf_file, .{
+                        .basename = basename,
+                        .format = .bin,
+                    });
+
+                    break :blk objcopy.getOutput();
+                },
+
+                .hex => blk: {
+                    const objcopy = firmware.host_build.addObjCopy(elf_file, .{
+                        .basename = basename,
+                        .format = .hex,
+                    });
+
+                    break :blk objcopy.getOutput();
+                },
+
+                .uf2 => |family_id| blk: {
+                    const uf2_exe = firmware.mz.dependency("uf2", .{ .optimize = .ReleaseSafe }).artifact("elf2uf2");
+
+                    const convert = firmware.host_build.addRunArtifact(uf2_exe);
+
+                    convert.addArg("--family-id");
+                    convert.addArg(firmware.host_build.fmt("0x{X:0>4}", .{@intFromEnum(family_id)}));
+
+                    convert.addArg("--elf-path");
+                    convert.addFileArg(elf_file);
+
+                    convert.addArg("--output-path");
+                    break :blk convert.addOutputFileArg(basename);
+                },
+
+                .dfu => buildConfigError(firmware.host_build, "DFU is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/145 for more details!", .{}),
+                .esp => buildConfigError(firmware.host_build, "ESP firmware image is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/146 for more details!", .{}),
+
+                .custom => |generator| generator.convert(generator, elf_file),
+            };
+        }
+        return gop.value_ptr.*;
+    }
+
+    pub const AppDependencyOptions = struct {
+        depend_on_microzig: bool = false,
+    };
+
+    /// Adds a regular dependency to your application.
+    pub fn addAppDependency(fw: *Firmware, name: []const u8, module: *std.Build.Module, options: AppDependencyOptions) void {
+        if (options.depend_on_microzig) {
+            module.dependencies.put("microzig", fw.modules.microzig) catch @panic("OOM");
+        }
+        fw.modules.app.dependencies.put(name, module) catch @panic("OOM");
+    }
+
+    pub fn addIncludePath(fw: *Firmware, path: std.Build.LazyPath) void {
+        fw.artifact.addIncludePath(path);
+    }
+
+    pub fn addSystemIncludePath(fw: *Firmware, path: std.Build.LazyPath) void {
+        fw.artifact.addSystemIncludePath(path);
+    }
+
+    pub fn addCSourceFile(fw: *Firmware, source: std.Build.Step.Compile.CSourceFile) void {
+        fw.artifact.addCSourceFile(source);
+    }
+
+    pub fn addOptions(fw: *Firmware, module_name: []const u8, options: *std.Build.OptionsStep) void {
+        fw.artifact.addOptions(module_name, options);
+        fw.modules.app.dependencies.put(
+            module_name,
+            fw.host_build.createModule(.{
+                .source_file = options.getOutput(),
+            }),
+        ) catch @panic("OOM");
+    }
+
+    pub fn addObjectFile(fw: *Firmware, source: std.Build.LazyPath) void {
+        fw.artifact.addObjectFile(source);
+    }
+
+    fn resolveFormat(firmware: *Firmware, format: ?BinaryFormat) BinaryFormat {
+        if (format) |fmt| return fmt;
+
+        if (firmware.target.preferred_format) |fmt| return fmt;
+
+        buildConfigError(firmware.host_build, "{s} has no preferred output format, please provide one in the `format` option.", .{
+            firmware.target.chip.name,
+        });
+    }
+};
+
+pub const cpus = struct {
+    pub const avr5 = Cpu{
+        .name = "AVR5",
+        .source_file = .{ .path = build_root ++ "/src/cpus/avr5.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .avr,
+            .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 },
+            .os_tag = .freestanding,
+            .abi = .eabi,
+        },
+    };
+
+    pub const cortex_m0 = Cpu{
+        .name = "ARM Cortex-M0",
+        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 },
+            .os_tag = .freestanding,
+            .abi = .eabi,
+        },
+    };
+
+    pub const cortex_m0plus = Cpu{
+        .name = "ARM Cortex-M0+",
+        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus },
+            .os_tag = .freestanding,
+            .abi = .eabi,
+        },
+    };
+
+    pub const cortex_m3 = Cpu{
+        .name = "ARM Cortex-M3",
+        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 },
+            .os_tag = .freestanding,
+            .abi = .eabi,
+        },
+    };
+
+    pub const cortex_m4 = Cpu{
+        .name = "ARM Cortex-M4",
+        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .thumb,
+            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 },
+            .os_tag = .freestanding,
+            .abi = .eabi,
+        },
+    };
+
+    pub const riscv32_imac = Cpu{
+        .name = "RISC-V 32-bit",
+        .source_file = .{ .path = build_root ++ "/src/cpus/riscv32.zig" },
+        .target = std.zig.CrossTarget{
+            .cpu_arch = .riscv32,
+            .cpu_model = .{ .explicit = &std.Target.riscv.cpu.sifive_e21 },
+            .os_tag = .freestanding,
+            .abi = .none,
+        },
+    };
+};
+
+fn buildConfigError(b: *std.Build, comptime fmt: []const u8, args: anytype) noreturn {
+    const msg = b.fmt(fmt, args);
+    @panic(msg);
+}
+
+fn dependency(mz: *MicroZig, name: []const u8, args: anytype) *std.Build.Dependency {
+    return mz.self.builder.dependency(name, args);
+}
+
+fn generateLinkerScript(b: *std.Build, chip: Chip) !std.Build.LazyPath {
+    const cpu = chip.cpu.getDescriptor();
+
+    var contents = std.ArrayList(u8).init(b.allocator);
+    const writer = contents.writer();
+    try writer.print(
+        \\/*
+        \\ * This file was auto-generated by microzig
+        \\ *
+        \\ * Target CPU:  {[cpu]s}
+        \\ * Target Chip: {[chip]s}
+        \\ */
+        \\
+        // This is not the "true" entry point, but there's no such thing on embedded platforms
+        // anyways. This is the logical entrypoint that should be invoked when
+        // stack, .data and .bss are set up and the CPU is ready to be used.
+        \\ENTRY(microzig_main);
+        \\
+        \\
+    , .{
+        .cpu = cpu.name,
+        .chip = chip.name,
+    });
+
+    try writer.writeAll("MEMORY\n{\n");
+    {
+        var counters = [4]usize{ 0, 0, 0, 0 };
+        for (chip.memory_regions) |region| {
+            // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k
+
+            switch (region.kind) {
+                .flash => {
+                    try writer.print("  flash{d}    (rx!w)", .{counters[0]});
+                    counters[0] += 1;
+                },
+
+                .ram => {
+                    try writer.print("  ram{d}      (rw!x)", .{counters[1]});
+                    counters[1] += 1;
+                },
+
+                .io => {
+                    try writer.print("  io{d}       (rw!x)", .{counters[2]});
+                    counters[2] += 1;
+                },
+
+                .reserved => {
+                    try writer.print("  reserved{d} (rw!x)", .{counters[3]});
+                    counters[3] += 1;
+                },
+
+                .private => |custom| {
+                    try writer.print("  {s} (", .{custom.name});
+                    if (custom.readable) try writer.writeAll("r");
+                    if (custom.writeable) try writer.writeAll("w");
+                    if (custom.executable) try writer.writeAll("x");
+
+                    if (!custom.readable or !custom.writeable or !custom.executable) {
+                        try writer.writeAll("!");
+                        if (!custom.readable) try writer.writeAll("r");
+                        if (!custom.writeable) try writer.writeAll("w");
+                        if (!custom.executable) try writer.writeAll("x");
+                    }
+                    try writer.writeAll(")");
+                },
+            }
+            try writer.print(" : ORIGIN = 0x{X:0>8}, LENGTH = 0x{X:0>8}\n", .{ region.offset, region.length });
+        }
+    }
+
+    try writer.writeAll("}\n\nSECTIONS\n{\n");
+    {
+        try writer.writeAll(
+            \\  .text :
+            \\  {
+            \\     KEEP(*(microzig_flash_start))
+            \\     *(.text*)
+            \\  } > flash0
+            \\
+            \\
+        );
+
+        switch (cpu.target.getCpuArch()) {
+            .arm, .thumb => try writer.writeAll(
+                \\  .ARM.exidx : {
+                \\      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+                \\  } >flash0
+                \\
+                \\
+            ),
+            else => {},
+        }
+
+        try writer.writeAll(
+            \\  .data :
+            \\  {
+            \\     microzig_data_start = .;
+            \\     *(.rodata*)
+            \\     *(.data*)
+            \\     microzig_data_end = .;
+            \\  } > ram0 AT> flash0
+            \\
+            \\  .bss (NOLOAD) :
+            \\  {
+            \\      microzig_bss_start = .;
+            \\      *(.bss*)
+            \\      microzig_bss_end = .;
+            \\  } > ram0
+            \\
+            \\  microzig_data_load_start = LOADADDR(.data);
+            \\
+        );
+    }
+    try writer.writeAll("}\n");
+
+    // TODO: Assert that the flash can actually hold all data!
+    // try writer.writeAll(
+    //     \\
+    //     \\  ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" );
+    //     \\
+    // );
+
+    const write = b.addWriteFiles();
+
+    return write.add("linker.ld", contents.items);
+}
diff --git a/build/build.zig.zon b/build/build.zig.zon
new file mode 100644
index 000000000..437acb5f9
--- /dev/null
+++ b/build/build.zig.zon
@@ -0,0 +1,29 @@
+.{
+    .name = "microzig",
+    .version = "0.1.0",
+    .paths = .{
+        "build.zig",
+        "build.zig.zon",
+        "design",
+        "docs",
+        "LICENSE",
+        "README.adoc",
+        "src",
+        "test",
+        "thoughts.md",
+    },
+    .dependencies = .{
+        .uf2 = .{
+            .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/8037b439ccbac862471392b25e94a8995d784e2c.tar.gz",
+            .hash = "1220cc66563fc1ecefca7990968441dc9d4db717884ffa9a2de657f60ed4bb74a70a",
+        },
+        .regz = .{
+            .url = "https://github.com/ZigEmbeddedGroup/regz/archive/d66ffd56f51fc46c071412141b5d0c74dc83c310.tar.gz",
+            .hash = "122002c5f2e31c11373ede6e8a8dd9a61aabd60d38df667ec33b5f994d1f0b503823",
+        },
+        .@"umm-zig" = .{
+            .url = "https://github.com/ZigEmbeddedGroup/umm-zig/archive/99d815adfbc5cc4ad385dd765a6192f85e54179f.tar.gz",
+            .hash = "12207ef7375ea45e97f4fba9c5dfa74d022902893c4dbf1a0076726b7ec39a02ea3f",
+        },
+    },
+}
diff --git a/build/microzig-package.json b/build/microzig-package.json
new file mode 100644
index 000000000..92812f004
--- /dev/null
+++ b/build/microzig-package.json
@@ -0,0 +1,4 @@
+{
+  "package_name": "microzig-build",
+  "package_type": "core"
+}
diff --git a/examples/modular/README.md b/examples/modular/README.md
new file mode 100644
index 000000000..7909f7c4c
--- /dev/null
+++ b/examples/modular/README.md
@@ -0,0 +1,5 @@
+# Examples for the BSP `nxp-lpc`
+
+- [Blinky](src/blinky.zig) on [nRF52840 Dongle](https://www.nordicsemi.com/Products/Development-hardware/nrf52840-dongle)  
+  TODO: Implement this!
+
diff --git a/examples/modular/build.zig b/examples/modular/build.zig
new file mode 100644
index 000000000..f58e4a8eb
--- /dev/null
+++ b/examples/modular/build.zig
@@ -0,0 +1,33 @@
+const std = @import("std");
+const microzig_build = @import("microzig-build");
+const lpc = @import("lpc");
+
+pub fn build(b: *std.Build) void {
+    const microbuild = microzig_build.init(
+        b,
+        b.dependency("microzig", .{}),
+    );
+
+    const optimize = b.standardOptimizeOption(.{});
+
+    // `addFirmware` basically works like addExecutable, but takes a
+    // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+    //
+    // The target will convey all necessary information on the chip,
+    // cpu and potentially the board as well.
+    const firmware = microbuild.addFirmware(b, .{
+        .name = "blinky",
+        .target = lpc.boards.mbed.lpc1768,
+        .optimize = optimize,
+        .source_file = .{ .path = "src/blinky.zig" },
+    });
+
+    // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+    // and allows installing the firmware as a typical firmware file.
+    //
+    // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+    microbuild.installFirmware(b, firmware, .{});
+
+    // For debugging, we also always install the firmware as an ELF file
+    microbuild.installFirmware(b, firmware, .{ .format = .elf });
+}
diff --git a/examples/modular/build.zig.zon b/examples/modular/build.zig.zon
new file mode 100644
index 000000000..aa5a11a05
--- /dev/null
+++ b/examples/modular/build.zig.zon
@@ -0,0 +1,14 @@
+.{
+    .name = "microzig-nxp-lpc-examples",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
+            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
+        },
+        .lpc = .{
+            .url = "https://github.com/ZigEmbeddedGroup/nxp-lpc/archive/130a1316c0892415e7da958a5e9548ed87bba54d.tar.gz",
+            .hash = "1220165879f85a1d51656d35b3963a95f3585dc665fc7414f76aa6aad4e6635536cf",
+        },
+    },
+}
diff --git a/examples/modular/src/blinky.zig b/examples/modular/src/blinky.zig
new file mode 100644
index 000000000..328d63705
--- /dev/null
+++ b/examples/modular/src/blinky.zig
@@ -0,0 +1,56 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+const chip = microzig.chip;
+
+// LED-1: P1.18
+// LED-2: P1.20
+// LED-3: P1.21
+// LED-4: P1.23
+
+const conn = chip.peripherals.PINCONNECT;
+const gpio: *volatile [5]PatchedGpio = @ptrCast(@alignCast(chip.peripherals.GPIO));
+
+const led_mask = [4]u32{
+    (1 << 18),
+    (1 << 20),
+    (1 << 21),
+    (1 << 23),
+};
+const all_mask = led_mask[0] | led_mask[1] | led_mask[2] | led_mask[3];
+
+pub fn main() !void {
+    conn.PINSEL3.modify(.{
+        .P1_18 = .{ .value = .GPIO_P1 },
+        .P1_20 = .{ .value = .GPIO_P1 },
+        .P1_21 = .{ .value = .GPIO_P1 },
+        .P1_23 = .{ .value = .GPIO_P1 },
+    });
+
+    const p1 = &gpio[1];
+
+    p1.dir = all_mask;
+
+    while (true) {
+        for (led_mask) |mask| {
+            p1.pin_clr = (all_mask & ~mask);
+            p1.pin_set = mask;
+            microzig.core.experimental.debug.busy_sleep(100_000);
+        }
+    }
+}
+
+const PatchedGpio = extern struct {
+    dir: u32, // 0x2009 C000
+    __padding0: u32, // 0x2009 C004
+    __padding1: u32, // 0x2009 C008
+    __padding2: u32, // 0x2009 C00C
+    mask: u32, // 0x2009 C010
+    pin: u32, // 0x2009 C014
+    pin_set: u32, // 0x2009 C018
+    pin_clr: u32, // 0x2009 C01C
+
+    comptime {
+        std.debug.assert(@sizeOf(PatchedGpio) == 0x20);
+    }
+};

From 31f26f57d99a8194a9371593da0b6575e63c35b1 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Tue, 9 Jan 2024 15:57:23 +0100
Subject: [PATCH 255/286] Refactors packaging process from bash to python

---
 .envrc                                        |   2 +
 .gitignore                                    |   1 +
 board-support/espressif-esp/build.zig.zon     |   5 -
 board-support/espressif-esp/extract-bsp-info  | Bin 2062248 -> 0 bytes
 board-support/microchip-avr/build.zig.zon     |   5 -
 board-support/nordic-nrf5x/build.zig.zon      |   5 -
 board-support/raspberrypi-rp2040/build.zig    |  41 --
 .../raspberrypi-rp2040/examples/adc.zig       |  40 --
 .../raspberrypi-rp2040/examples/blinky.zig    |  20 -
 .../examples/blinky_core1.zig                 |  28 --
 .../examples/flash_program.zig                |  81 ---
 .../raspberrypi-rp2040/examples/gpio_clk.zig  |  16 -
 .../examples/i2c_bus_scan.zig                 |  44 --
 .../raspberrypi-rp2040/examples/pwm.zig       |  23 -
 .../raspberrypi-rp2040/examples/random.zig    |  68 ---
 .../examples/scripts/hid_test.py              |  29 --
 .../examples/scripts/usb_device_loopback.py   |  48 --
 .../examples/spi_master.zig                   |  26 -
 .../examples/squarewave.zig                   |  84 ----
 .../raspberrypi-rp2040/examples/uart.zig      |  49 --
 .../examples/usb_device.zig                   | 172 -------
 .../raspberrypi-rp2040/examples/usb_hid.zig   | 187 -------
 .../raspberrypi-rp2040/examples/ws2812.zig    |  94 ----
 build.zig                                     |  16 +-
 build.zig.zon                                 |  10 +
 build/build.zig.zon                           |  29 --
 build/microzig-package.json                   |  16 +-
 core/build.zig.zon                            |  29 --
 core/microzig-package.json                    |  12 +-
 flake.lock                                    |   8 +-
 flake.nix                                     |  94 +++-
 for-extraction/uf2-flasher/build.zig          |  19 +
 .../uf2-flasher}/build.zig.zon                |   0
 for-extraction/uf2-flasher/src/main.zig       | 333 ++++++++++++
 tools/archive-info.zig                        |  22 +-
 tools/bundle.py                               | 473 ++++++++++++++++++
 tools/bundle.sh                               | 169 -------
 tools/create-pkg-descriptor.zig               | 122 +++++
 38 files changed, 1090 insertions(+), 1330 deletions(-)
 create mode 100644 .envrc
 delete mode 100644 board-support/espressif-esp/build.zig.zon
 delete mode 100755 board-support/espressif-esp/extract-bsp-info
 delete mode 100644 board-support/microchip-avr/build.zig.zon
 delete mode 100644 board-support/nordic-nrf5x/build.zig.zon
 delete mode 100644 board-support/raspberrypi-rp2040/examples/adc.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/blinky.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/blinky_core1.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/flash_program.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/gpio_clk.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/i2c_bus_scan.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/pwm.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/random.zig
 delete mode 100755 board-support/raspberrypi-rp2040/examples/scripts/hid_test.py
 delete mode 100755 board-support/raspberrypi-rp2040/examples/scripts/usb_device_loopback.py
 delete mode 100644 board-support/raspberrypi-rp2040/examples/spi_master.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/squarewave.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/uart.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/usb_device.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/usb_hid.zig
 delete mode 100644 board-support/raspberrypi-rp2040/examples/ws2812.zig
 create mode 100644 build.zig.zon
 delete mode 100644 build/build.zig.zon
 delete mode 100644 core/build.zig.zon
 create mode 100644 for-extraction/uf2-flasher/build.zig
 rename {board-support/raspberrypi-rp2040 => for-extraction/uf2-flasher}/build.zig.zon (100%)
 create mode 100644 for-extraction/uf2-flasher/src/main.zig
 create mode 100755 tools/bundle.py
 delete mode 100755 tools/bundle.sh
 create mode 100644 tools/create-pkg-descriptor.zig

diff --git a/.envrc b/.envrc
new file mode 100644
index 000000000..4cc700ca7
--- /dev/null
+++ b/.envrc
@@ -0,0 +1,2 @@
+# use_nix
+use_flake
diff --git a/.gitignore b/.gitignore
index aa8f1d641..1efc3f0f9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -4,3 +4,4 @@ microzig-deploy/
 .DS_Store
 .gdbinit
 .lldbinit
+.direnv/
diff --git a/board-support/espressif-esp/build.zig.zon b/board-support/espressif-esp/build.zig.zon
deleted file mode 100644
index fd45779e6..000000000
--- a/board-support/espressif-esp/build.zig.zon
+++ /dev/null
@@ -1,5 +0,0 @@
-.{
-    .name = "microzig-espressif-esp",
-    .version = "0.1.0",
-    .dependencies = .{},
-}
diff --git a/board-support/espressif-esp/extract-bsp-info b/board-support/espressif-esp/extract-bsp-info
deleted file mode 100755
index e805c7e173d96d164d07c2876b7c1472a904866c..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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z7wAS3!6x;F2x!_$;;)OH3t|fSa*54I51klGrhJFQHu~_BKnAN86a=Psg8)u&tt7sJ
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zAC+Ex{yko~JtS!F%Jkp=6Y-ly<28m-&0o {}, {d:2}%", .{ i, dist[i], @as(f32, @floatFromInt(dist[i])) / @as(f32, @floatFromInt(counter)) });
-            }
-        }
-        time.sleep_ms(1000);
-    }
-}
diff --git a/board-support/raspberrypi-rp2040/examples/scripts/hid_test.py b/board-support/raspberrypi-rp2040/examples/scripts/hid_test.py
deleted file mode 100755
index ccc2dd093..000000000
--- a/board-support/raspberrypi-rp2040/examples/scripts/hid_test.py
+++ /dev/null
@@ -1,29 +0,0 @@
-#!/usr/bin/env python3
-
-# Install python3 HID package https://pypi.org/project/hid/
-import hid
-
-# default is TinyUSB (0xcafe), Adafruit (0x239a), RaspberryPi (0x2e8a), Espressif (0x303a) VID
-USB_VID = (0xcafe, 0x239a, 0x2e8a, 0x303a)
-
-print("VID list: " + ", ".join('%02x' % v for v in USB_VID))
-
-for vid in  USB_VID:
-    for dict in hid.enumerate(vid):
-        print(dict)
-        dev = hid.Device(dict['vendor_id'], dict['product_id'])
-        if dev:
-            while True:
-                inp = input("Send text to HID Device : ").encode('utf-8')
-                dev.write(inp)
-
-                x = 0
-                l = len(inp)
-                r = b""
-                while (x < l):
-                    str_in = dev.read(64)
-                    r += str_in
-                    x += 64
-
-                print("Received from HID Device:\n", r)
-                print("hex:\n", r.hex())
diff --git a/board-support/raspberrypi-rp2040/examples/scripts/usb_device_loopback.py b/board-support/raspberrypi-rp2040/examples/scripts/usb_device_loopback.py
deleted file mode 100755
index 82bf47899..000000000
--- a/board-support/raspberrypi-rp2040/examples/scripts/usb_device_loopback.py
+++ /dev/null
@@ -1,48 +0,0 @@
-#!/usr/bin/env python3
-
-#
-# Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
-#
-# SPDX-License-Identifier: BSD-3-Clause
-#
-
-# sudo pip3 install pyusb
-
-import usb.core
-import usb.util
-
-# find our device
-dev = usb.core.find(idVendor=0x0000, idProduct=0x0001)
-
-# was it found?
-if dev is None:
-    raise ValueError('Device not found')
-
-# get an endpoint instance
-cfg = dev.get_active_configuration()
-intf = cfg[(0, 0)]
-
-outep = usb.util.find_descriptor(
-    intf,
-    # match the first OUT endpoint
-    custom_match= \
-        lambda e: \
-            usb.util.endpoint_direction(e.bEndpointAddress) == \
-            usb.util.ENDPOINT_OUT)
-
-inep = usb.util.find_descriptor(
-    intf,
-    # match the first IN endpoint
-    custom_match= \
-        lambda e: \
-            usb.util.endpoint_direction(e.bEndpointAddress) == \
-            usb.util.ENDPOINT_IN)
-
-assert inep is not None
-assert outep is not None
-
-test_string = "Hello World!"
-outep.write(test_string)
-from_device = inep.read(len(test_string))
-
-print("Device Says: {}".format(''.join([chr(x) for x in from_device])))
diff --git a/board-support/raspberrypi-rp2040/examples/spi_master.zig b/board-support/raspberrypi-rp2040/examples/spi_master.zig
deleted file mode 100644
index c160fee96..000000000
--- a/board-support/raspberrypi-rp2040/examples/spi_master.zig
+++ /dev/null
@@ -1,26 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-const rp2040 = microzig.hal;
-const time = rp2040.time;
-const gpio = rp2040.gpio;
-const clocks = rp2040.clocks;
-const peripherals = microzig.chip.peripherals;
-
-const BUF_LEN = 0x100;
-const spi = rp2040.spi.num(0);
-
-// Communicate with another RP2040 over spi
-// Slave implementation: https://github.com/raspberrypi/pico-examples/blob/master/spi/spi_master_slave/spi_slave/spi_slave.c
-pub fn main() !void {
-    spi.apply(.{
-        .clock_config = rp2040.clock_config,
-    });
-    var out_buf: [BUF_LEN]u8 = .{ 0xAA, 0xBB, 0xCC, 0xDD } ** (BUF_LEN / 4);
-    var in_buf: [BUF_LEN]u8 = undefined;
-
-    while (true) {
-        _ = spi.transceive(&out_buf, &in_buf);
-        time.sleep_ms(1 * 1000);
-    }
-}
diff --git a/board-support/raspberrypi-rp2040/examples/squarewave.zig b/board-support/raspberrypi-rp2040/examples/squarewave.zig
deleted file mode 100644
index 0894d9a0c..000000000
--- a/board-support/raspberrypi-rp2040/examples/squarewave.zig
+++ /dev/null
@@ -1,84 +0,0 @@
-//! Hello world for the PIO module: generating a square wave
-const std = @import("std");
-const microzig = @import("microzig");
-const rp2040 = microzig.hal;
-const gpio = rp2040.gpio;
-const Pio = rp2040.pio.Pio;
-const StateMachine = rp2040.pio.StateMachine;
-
-const squarewave_program = blk: {
-    @setEvalBranchQuota(2000);
-    break :blk rp2040.pio.assemble(
-        \\;
-        \\; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
-        \\;
-        \\; SPDX-License-Identifier: BSD-3-Clause
-        \\;
-        \\.program squarewave
-        \\    set pindirs, 1   ; Set pin to output
-        \\again:
-        \\    set pins, 1 [1]  ; Drive pin high and then delay for one cycle
-        \\    set pins, 0      ; Drive pin low
-        \\    jmp again        ; Set PC to label `again`
-    , .{}).get_program_by_name("squarewave");
-};
-
-// Pick one PIO instance arbitrarily. We're also arbitrarily picking state
-// machine 0 on this PIO instance (the state machines are numbered 0 to 3
-// inclusive).
-const pio: Pio = .pio0;
-const sm: StateMachine = .sm0;
-
-pub fn main() void {
-    pio.gpio_init(gpio.num(2));
-    pio.sm_load_and_start_program(sm, squarewave_program, .{
-        .clkdiv = rp2040.pio.ClkDivOptions.from_float(125),
-        .pin_mappings = .{
-            .set = .{
-                .base = 2,
-                .count = 1,
-            },
-        },
-    }) catch unreachable;
-
-    pio.sm_set_enabled(sm, true);
-
-    while (true) {}
-
-    //// Load the assembled program directly into the PIO's instruction memory.
-    //// Each PIO instance has a 32-slot instruction memory, which all 4 state
-    //// machines can see. The system has write-only access.
-    //for (squarewave_program.instructions, 0..) |insn, i|
-    //    pio.get_instruction_memory()[i] = insn;
-
-    //// Configure state machine 0 to run at sysclk/2.5. The state machines can
-    //// run as fast as one instruction per clock cycle, but we can scale their
-    //// speed down uniformly to meet some precise frequency target, e.g. for a
-    //// UART baud rate. This register has 16 integer divisor bits and 8
-    //// fractional divisor bits.
-    //pio.sm_set_clkdiv(sm, .{
-    //    .int = 2,
-    //    .frac = 0x80,
-    //});
-
-    //// There are five pin mapping groups (out, in, set, side-set, jmp pin)
-    //// which are used by different instructions or in different circumstances.
-    //// Here we're just using SET instructions. Configure state machine 0 SETs
-    //// to affect GPIO 0 only; then configure GPIO0 to be controlled by PIO0,
-    //// as opposed to e.g. the processors.
-    //pio.gpio_init(2);
-    //pio.sm_set_pin_mappings(sm, .{
-    //    .out = .{
-    //        .base = 2,
-    //        .count = 1,
-    //    },
-    //});
-
-    //// Set the state machine running. The PIO CTRL register is global within a
-    //// PIO instance, so you can start/stop multiple state machines
-    //// simultaneously. We're using the register's hardware atomic set alias to
-    //// make one bit high without doing a read-modify-write on the register.
-    //pio.sm_set_enabled(sm, true);
-
-    //while (true) {}
-}
diff --git a/board-support/raspberrypi-rp2040/examples/uart.zig b/board-support/raspberrypi-rp2040/examples/uart.zig
deleted file mode 100644
index 914b9ae98..000000000
--- a/board-support/raspberrypi-rp2040/examples/uart.zig
+++ /dev/null
@@ -1,49 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-const rp2040 = microzig.hal;
-const time = rp2040.time;
-const gpio = rp2040.gpio;
-const clocks = rp2040.clocks;
-
-const led = gpio.num(25);
-const uart = rp2040.uart.num(0);
-const baud_rate = 115200;
-const uart_tx_pin = gpio.num(0);
-const uart_rx_pin = gpio.num(1);
-
-pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
-    std.log.err("panic: {s}", .{message});
-    @breakpoint();
-    while (true) {}
-}
-
-pub const std_options = struct {
-    pub const log_level = .debug;
-    pub const logFn = rp2040.uart.log;
-};
-
-pub fn main() !void {
-    led.set_function(.sio);
-    led.set_direction(.out);
-    led.put(1);
-
-    uart.apply(.{
-        .baud_rate = baud_rate,
-        .tx_pin = uart_tx_pin,
-        .rx_pin = uart_rx_pin,
-        .clock_config = rp2040.clock_config,
-    });
-
-    rp2040.uart.init_logger(uart);
-
-    var i: u32 = 0;
-    while (true) : (i += 1) {
-        led.put(1);
-        std.log.info("what {}", .{i});
-        time.sleep_ms(500);
-
-        led.put(0);
-        time.sleep_ms(500);
-    }
-}
diff --git a/board-support/raspberrypi-rp2040/examples/usb_device.zig b/board-support/raspberrypi-rp2040/examples/usb_device.zig
deleted file mode 100644
index 8f2d74e4f..000000000
--- a/board-support/raspberrypi-rp2040/examples/usb_device.zig
+++ /dev/null
@@ -1,172 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-const rp2040 = microzig.hal;
-const flash = rp2040.flash;
-const time = rp2040.time;
-const gpio = rp2040.gpio;
-const clocks = rp2040.clocks;
-const usb = rp2040.usb;
-
-const led = gpio.num(25);
-const uart = rp2040.uart.num(0);
-const baud_rate = 115200;
-const uart_tx_pin = gpio.num(0);
-const uart_rx_pin = gpio.num(1);
-
-// First we define two callbacks that will be used by the endpoints we define next...
-fn ep1_in_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
-    _ = data;
-    // The host has collected the data we repeated onto
-    // EP1! Set up to receive more data on EP1.
-    usb.Usb.callbacks.usb_start_rx(
-        dc.endpoints[2], // EP1_OUT_CFG,
-        64,
-    );
-}
-
-fn ep1_out_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
-    // We've gotten data from the host on our custom
-    // EP1! Set up EP1 to repeat it.
-    usb.Usb.callbacks.usb_start_tx(
-        dc.endpoints[3], // EP1_IN_CFG,
-        data,
-    );
-}
-
-// The endpoints EP0_IN and EP0_OUT are already defined but you can
-// add your own endpoints to...
-pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
-    .descriptor = &usb.EndpointDescriptor{
-        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
-        .descriptor_type = usb.DescType.Endpoint,
-        .endpoint_address = usb.Dir.Out.endpoint(1),
-        .attributes = @intFromEnum(usb.TransferType.Bulk),
-        .max_packet_size = 64,
-        .interval = 0,
-    },
-    .endpoint_control_index = 2,
-    .buffer_control_index = 3,
-    .data_buffer_index = 2,
-    .next_pid_1 = false,
-    // The callback will be executed if we got an interrupt on EP1_OUT
-    .callback = ep1_out_callback,
-};
-
-pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
-    .descriptor = &usb.EndpointDescriptor{
-        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
-        .descriptor_type = usb.DescType.Endpoint,
-        .endpoint_address = usb.Dir.In.endpoint(1),
-        .attributes = @intFromEnum(usb.TransferType.Bulk),
-        .max_packet_size = 64,
-        .interval = 0,
-    },
-    .endpoint_control_index = 1,
-    .buffer_control_index = 2,
-    .data_buffer_index = 3,
-    .next_pid_1 = false,
-    // The callback will be executed if we got an interrupt on EP1_IN
-    .callback = ep1_in_callback,
-};
-
-// This is our device configuration
-pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
-    .device_descriptor = &.{
-        .length = @as(u8, @intCast(@sizeOf(usb.DeviceDescriptor))),
-        .descriptor_type = usb.DescType.Device,
-        .bcd_usb = 0x0110,
-        .device_class = 0,
-        .device_subclass = 0,
-        .device_protocol = 0,
-        .max_packet_size0 = 64,
-        .vendor = 0,
-        .product = 1,
-        .bcd_device = 0,
-        .manufacturer_s = 1,
-        .product_s = 2,
-        .serial_s = 0,
-        .num_configurations = 1,
-    },
-    .interface_descriptor = &.{
-        .length = @as(u8, @intCast(@sizeOf(usb.InterfaceDescriptor))),
-        .descriptor_type = usb.DescType.Interface,
-        .interface_number = 0,
-        .alternate_setting = 0,
-        // We have two endpoints (EP0 IN/OUT don't count)
-        .num_endpoints = 2,
-        .interface_class = 0xff,
-        .interface_subclass = 0,
-        .interface_protocol = 0,
-        .interface_s = 0,
-    },
-    .config_descriptor = &.{
-        .length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor))),
-        .descriptor_type = usb.DescType.Config,
-        .total_length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor) + @sizeOf(usb.InterfaceDescriptor) + @sizeOf(usb.EndpointDescriptor) + @sizeOf(usb.EndpointDescriptor))),
-        .num_interfaces = 1,
-        .configuration_value = 1,
-        .configuration_s = 0,
-        .attributes = 0xc0,
-        .max_power = 0x32,
-    },
-    .lang_descriptor = "\x04\x03\x09\x04", // length || string descriptor (0x03) || Engl (0x0409)
-    .descriptor_strings = &.{
-        // ugly unicode :|
-        "R\x00a\x00s\x00p\x00b\x00e\x00r\x00r\x00y\x00 \x00P\x00i\x00",
-        "P\x00i\x00c\x00o\x00 \x00T\x00e\x00s\x00t\x00 \x00D\x00e\x00v\x00i\x00c\x00e\x00",
-    },
-    // Here we pass all endpoints to the config
-    // Dont forget to pass EP0_[IN|OUT] in the order seen below!
-    .endpoints = .{
-        &usb.EP0_OUT_CFG,
-        &usb.EP0_IN_CFG,
-        &EP1_OUT_CFG,
-        &EP1_IN_CFG,
-    },
-};
-
-pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
-    std.log.err("panic: {s}", .{message});
-    @breakpoint();
-    while (true) {}
-}
-
-pub const std_options = struct {
-    pub const log_level = .debug;
-    pub const logFn = rp2040.uart.log;
-};
-
-pub fn main() !void {
-    led.set_function(.sio);
-    led.set_direction(.out);
-    led.put(1);
-
-    uart.apply(.{
-        .baud_rate = baud_rate,
-        .tx_pin = uart_tx_pin,
-        .rx_pin = uart_rx_pin,
-        .clock_config = rp2040.clock_config,
-    });
-
-    rp2040.uart.init_logger(uart);
-
-    // First we initialize the USB clock
-    rp2040.usb.Usb.init_clk();
-    // Then initialize the USB device using the configuration defined above
-    rp2040.usb.Usb.init_device(&DEVICE_CONFIGURATION) catch unreachable;
-    var old: u64 = time.get_time_since_boot().to_us();
-    var new: u64 = 0;
-    while (true) {
-        // You can now poll for USB events
-        rp2040.usb.Usb.task(
-            false, // debug output over UART [Y/n]
-        ) catch unreachable;
-
-        new = time.get_time_since_boot().to_us();
-        if (new - old > 500000) {
-            old = new;
-            led.toggle();
-        }
-    }
-}
diff --git a/board-support/raspberrypi-rp2040/examples/usb_hid.zig b/board-support/raspberrypi-rp2040/examples/usb_hid.zig
deleted file mode 100644
index 752111ad0..000000000
--- a/board-support/raspberrypi-rp2040/examples/usb_hid.zig
+++ /dev/null
@@ -1,187 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-const rp2040 = microzig.hal;
-const flash = rp2040.flash;
-const time = rp2040.time;
-const gpio = rp2040.gpio;
-const clocks = rp2040.clocks;
-const usb = rp2040.usb;
-
-const led = gpio.num(25);
-const uart = rp2040.uart.num(0);
-const baud_rate = 115200;
-const uart_tx_pin = gpio.num(0);
-const uart_rx_pin = gpio.num(1);
-
-// First we define two callbacks that will be used by the endpoints we define next...
-fn ep1_in_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
-    _ = data;
-    // The host has collected the data we repeated onto
-    // EP1! Set up to receive more data on EP1.
-    usb.Usb.callbacks.usb_start_rx(
-        dc.endpoints[2], // EP1_OUT_CFG,
-        64,
-    );
-}
-
-fn ep1_out_callback(dc: *usb.DeviceConfiguration, data: []const u8) void {
-    // We've gotten data from the host on our custom
-    // EP1! Set up EP1 to repeat it.
-    usb.Usb.callbacks.usb_start_tx(
-        dc.endpoints[3], // EP1_IN_CFG,
-        data,
-    );
-}
-
-// The endpoints EP0_IN and EP0_OUT are already defined but you can
-// add your own endpoints to...
-pub var EP1_OUT_CFG: usb.EndpointConfiguration = .{
-    .descriptor = &usb.EndpointDescriptor{
-        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
-        .descriptor_type = usb.DescType.Endpoint,
-        .endpoint_address = usb.Dir.Out.endpoint(1),
-        .attributes = @intFromEnum(usb.TransferType.Interrupt),
-        .max_packet_size = 64,
-        .interval = 0,
-    },
-    .endpoint_control_index = 2,
-    .buffer_control_index = 3,
-    .data_buffer_index = 2,
-    .next_pid_1 = false,
-    // The callback will be executed if we got an interrupt on EP1_OUT
-    .callback = ep1_out_callback,
-};
-
-pub var EP1_IN_CFG: usb.EndpointConfiguration = .{
-    .descriptor = &usb.EndpointDescriptor{
-        .length = @as(u8, @intCast(@sizeOf(usb.EndpointDescriptor))),
-        .descriptor_type = usb.DescType.Endpoint,
-        .endpoint_address = usb.Dir.In.endpoint(1),
-        .attributes = @intFromEnum(usb.TransferType.Interrupt),
-        .max_packet_size = 64,
-        .interval = 0,
-    },
-    .endpoint_control_index = 1,
-    .buffer_control_index = 2,
-    .data_buffer_index = 3,
-    .next_pid_1 = false,
-    // The callback will be executed if we got an interrupt on EP1_IN
-    .callback = ep1_in_callback,
-};
-
-// This is our device configuration
-pub var DEVICE_CONFIGURATION: usb.DeviceConfiguration = .{
-    .device_descriptor = &.{
-        .length = @as(u8, @intCast(@sizeOf(usb.DeviceDescriptor))),
-        .descriptor_type = usb.DescType.Device,
-        .bcd_usb = 0x0200,
-        .device_class = 0,
-        .device_subclass = 0,
-        .device_protocol = 0,
-        .max_packet_size0 = 64,
-        .vendor = 0xCafe,
-        .product = 1,
-        .bcd_device = 0x0100,
-        // Those are indices to the descriptor strings
-        // Make sure to provide enough string descriptors!
-        .manufacturer_s = 1,
-        .product_s = 2,
-        .serial_s = 3,
-        .num_configurations = 1,
-    },
-    .interface_descriptor = &.{
-        .length = @as(u8, @intCast(@sizeOf(usb.InterfaceDescriptor))),
-        .descriptor_type = usb.DescType.Interface,
-        .interface_number = 0,
-        .alternate_setting = 0,
-        // We have two endpoints (EP0 IN/OUT don't count)
-        .num_endpoints = 2,
-        .interface_class = 3,
-        .interface_subclass = 0,
-        .interface_protocol = 0,
-        .interface_s = 0,
-    },
-    .config_descriptor = &.{
-        .length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor))),
-        .descriptor_type = usb.DescType.Config,
-        .total_length = @as(u8, @intCast(@sizeOf(usb.ConfigurationDescriptor) + @sizeOf(usb.InterfaceDescriptor) + @sizeOf(usb.EndpointDescriptor) + @sizeOf(usb.EndpointDescriptor))),
-        .num_interfaces = 1,
-        .configuration_value = 1,
-        .configuration_s = 0,
-        .attributes = 0xc0,
-        .max_power = 0x32,
-    },
-    .lang_descriptor = "\x04\x03\x09\x04", // length || string descriptor (0x03) || Engl (0x0409)
-    .descriptor_strings = &.{
-        // ugly unicode :|
-        //"R\x00a\x00s\x00p\x00b\x00e\x00r\x00r\x00y\x00 \x00P\x00i\x00",
-        &usb.utf8ToUtf16Le("Raspberry Pi"),
-        //"P\x00i\x00c\x00o\x00 \x00T\x00e\x00s\x00t\x00 \x00D\x00e\x00v\x00i\x00c\x00e\x00",
-        &usb.utf8ToUtf16Le("Pico Test Device"),
-        //"c\x00a\x00f\x00e\x00b\x00a\x00b\x00e\x00",
-        &usb.utf8ToUtf16Le("cafebabe"),
-    },
-    .hid = .{
-        .hid_descriptor = &.{
-            .bcd_hid = 0x0111,
-            .country_code = 0,
-            .num_descriptors = 1,
-            .report_length = 34,
-        },
-        .report_descriptor = &usb.hid.ReportDescriptorFidoU2f,
-    },
-    // Here we pass all endpoints to the config
-    // Dont forget to pass EP0_[IN|OUT] in the order seen below!
-    .endpoints = .{
-        &usb.EP0_OUT_CFG,
-        &usb.EP0_IN_CFG,
-        &EP1_OUT_CFG,
-        &EP1_IN_CFG,
-    },
-};
-
-pub fn panic(message: []const u8, _: ?*std.builtin.StackTrace, _: ?usize) noreturn {
-    std.log.err("panic: {s}", .{message});
-    @breakpoint();
-    while (true) {}
-}
-
-pub const std_options = struct {
-    pub const log_level = .debug;
-    pub const logFn = rp2040.uart.log;
-};
-
-pub fn main() !void {
-    led.set_function(.sio);
-    led.set_direction(.out);
-    led.put(1);
-
-    uart.apply(.{
-        .baud_rate = baud_rate,
-        .tx_pin = uart_tx_pin,
-        .rx_pin = uart_rx_pin,
-        .clock_config = rp2040.clock_config,
-    });
-
-    rp2040.uart.init_logger(uart);
-
-    // First we initialize the USB clock
-    rp2040.usb.Usb.init_clk();
-    // Then initialize the USB device using the configuration defined above
-    rp2040.usb.Usb.init_device(&DEVICE_CONFIGURATION) catch unreachable;
-    var old: u64 = time.get_time_since_boot().to_us();
-    var new: u64 = 0;
-    while (true) {
-        // You can now poll for USB events
-        rp2040.usb.Usb.task(
-            true, // debug output over UART [Y/n]
-        ) catch unreachable;
-
-        new = time.get_time_since_boot().to_us();
-        if (new - old > 500000) {
-            old = new;
-            led.toggle();
-        }
-    }
-}
diff --git a/board-support/raspberrypi-rp2040/examples/ws2812.zig b/board-support/raspberrypi-rp2040/examples/ws2812.zig
deleted file mode 100644
index 64fbac225..000000000
--- a/board-support/raspberrypi-rp2040/examples/ws2812.zig
+++ /dev/null
@@ -1,94 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-const rp2040 = microzig.hal;
-const gpio = rp2040.gpio;
-const Pio = rp2040.pio.Pio;
-const StateMachine = rp2040.pio.StateMachine;
-
-const ws2812_program = blk: {
-    @setEvalBranchQuota(5000);
-    break :blk rp2040.pio.assemble(
-        \\;
-        \\; Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
-        \\;
-        \\; SPDX-License-Identifier: BSD-3-Clause
-        \\;
-        \\.program ws2812
-        \\.side_set 1
-        \\
-        \\.define public T1 2
-        \\.define public T2 5
-        \\.define public T3 3
-        \\
-        \\.wrap_target
-        \\bitloop:
-        \\    out x, 1       side 0 [T3 - 1] ; Side-set still takes place when instruction stalls
-        \\    jmp !x do_zero side 1 [T1 - 1] ; Branch on the bit we shifted out. Positive pulse
-        \\do_one:
-        \\    jmp  bitloop   side 1 [T2 - 1] ; Continue driving high, for a long pulse
-        \\do_zero:
-        \\    nop            side 0 [T2 - 1] ; Or drive low, for a short pulse
-        \\.wrap
-    , .{}).get_program_by_name("ws2812");
-};
-
-const pio: Pio = .pio0;
-const sm: StateMachine = .sm0;
-const led_pin = gpio.num(23);
-
-pub fn main() void {
-    pio.gpio_init(led_pin);
-    sm_set_consecutive_pindirs(pio, sm, @intFromEnum(led_pin), 1, true);
-
-    const cycles_per_bit: comptime_int = ws2812_program.defines[0].value + //T1
-        ws2812_program.defines[1].value + //T2
-        ws2812_program.defines[2].value; //T3
-    const div = @as(f32, @floatFromInt(rp2040.clock_config.sys.?.output_freq)) /
-        (800_000 * cycles_per_bit);
-
-    pio.sm_load_and_start_program(sm, ws2812_program, .{
-        .clkdiv = rp2040.pio.ClkDivOptions.from_float(div),
-        .pin_mappings = .{
-            .side_set = .{
-                .base = @intFromEnum(led_pin),
-                .count = 1,
-            },
-        },
-        .shift = .{
-            .out_shiftdir = .left,
-            .autopull = true,
-            .pull_threshold = 24,
-            .join_tx = true,
-        },
-    }) catch unreachable;
-    pio.sm_set_enabled(sm, true);
-
-    while (true) {
-        pio.sm_blocking_write(sm, 0x00ff00 << 8); //red
-        rp2040.time.sleep_ms(1000);
-        pio.sm_blocking_write(sm, 0xff0000 << 8); //green
-        rp2040.time.sleep_ms(1000);
-        pio.sm_blocking_write(sm, 0x0000ff << 8); //blue
-        rp2040.time.sleep_ms(1000);
-    }
-}
-
-fn sm_set_consecutive_pindirs(_pio: Pio, _sm: StateMachine, pin: u5, count: u3, is_out: bool) void {
-    const sm_regs = _pio.get_sm_regs(_sm);
-    const pinctrl_saved = sm_regs.pinctrl.raw;
-    sm_regs.pinctrl.modify(.{
-        .SET_BASE = pin,
-        .SET_COUNT = count,
-    });
-    _pio.sm_exec(_sm, rp2040.pio.Instruction{
-        .tag = .set,
-        .delay_side_set = 0,
-        .payload = .{
-            .set = .{
-                .data = @intFromBool(is_out),
-                .destination = .pindirs,
-            },
-        },
-    });
-    sm_regs.pinctrl.raw = pinctrl_saved;
-}
diff --git a/build.zig b/build.zig
index 21246fe29..d582de9a7 100644
--- a/build.zig
+++ b/build.zig
@@ -8,13 +8,27 @@ fn buildTools(b: *std.Build) void {
     const tools_step = b.step("tools", "Only build the development tools");
     b.getInstallStep().dependOn(tools_step);
 
+    const eggzon_dep = b.dependency("eggzon", .{});
+    const eggzon_mod = eggzon_dep.module("eggzon");
+
+    const create_build_meta = b.addExecutable(.{
+        .name = "create-pkg-descriptor",
+        .root_source_file = .{ .path = "tools/create-pkg-descriptor.zig" },
+        .optimize = .ReleaseSafe,
+    });
+    create_build_meta.addModule("eggzon", eggzon_mod);
+    installTool(tools_step, create_build_meta);
+
     const archive_info = b.addExecutable(.{
         .name = "archive-info",
         .optimize = .ReleaseSafe,
         .root_source_file = .{ .path = "tools/archive-info.zig" },
     });
+    installTool(tools_step, archive_info);
+}
 
-    tools_step.dependOn(&b.addInstallArtifact(archive_info, .{
+fn installTool(tools_step: *std.Build.Step, exe: *std.Build.Step.Compile) void {
+    tools_step.dependOn(&tools_step.owner.addInstallArtifact(exe, .{
         .dest_dir = .{ .override = .{ .custom = "tools" } },
     }).step);
 }
diff --git a/build.zig.zon b/build.zig.zon
new file mode 100644
index 000000000..a4e965265
--- /dev/null
+++ b/build.zig.zon
@@ -0,0 +1,10 @@
+.{
+    .name = "microzig/monorepo",
+    .version = "0.0.0",
+    .dependencies = .{
+        .eggzon = .{
+            .url = "https://github.com/ziglibs/eggzon/archive/refs/heads/master.tar.gz",
+            .hash = "1220cd5cec7e9d4911074a9b2dec2dabef76e1adf94d041bca068163ce7666c4be47",
+        },
+    },
+}
diff --git a/build/build.zig.zon b/build/build.zig.zon
deleted file mode 100644
index 437acb5f9..000000000
--- a/build/build.zig.zon
+++ /dev/null
@@ -1,29 +0,0 @@
-.{
-    .name = "microzig",
-    .version = "0.1.0",
-    .paths = .{
-        "build.zig",
-        "build.zig.zon",
-        "design",
-        "docs",
-        "LICENSE",
-        "README.adoc",
-        "src",
-        "test",
-        "thoughts.md",
-    },
-    .dependencies = .{
-        .uf2 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/8037b439ccbac862471392b25e94a8995d784e2c.tar.gz",
-            .hash = "1220cc66563fc1ecefca7990968441dc9d4db717884ffa9a2de657f60ed4bb74a70a",
-        },
-        .regz = .{
-            .url = "https://github.com/ZigEmbeddedGroup/regz/archive/d66ffd56f51fc46c071412141b5d0c74dc83c310.tar.gz",
-            .hash = "122002c5f2e31c11373ede6e8a8dd9a61aabd60d38df667ec33b5f994d1f0b503823",
-        },
-        .@"umm-zig" = .{
-            .url = "https://github.com/ZigEmbeddedGroup/umm-zig/archive/99d815adfbc5cc4ad385dd765a6192f85e54179f.tar.gz",
-            .hash = "12207ef7375ea45e97f4fba9c5dfa74d022902893c4dbf1a0076726b7ec39a02ea3f",
-        },
-    },
-}
diff --git a/build/microzig-package.json b/build/microzig-package.json
index 92812f004..bdabd11c0 100644
--- a/build/microzig-package.json
+++ b/build/microzig-package.json
@@ -1,4 +1,14 @@
 {
-  "package_name": "microzig-build",
-  "package_type": "core"
-}
+    "package_name": "build",
+    "package_type": "build",
+    "external_dependencies": {
+        "uf2": {
+            "url": "https://github.com/ZigEmbeddedGroup/uf2/archive/8037b439ccbac862471392b25e94a8995d784e2c.tar.gz",
+            "hash": "1220cc66563fc1ecefca7990968441dc9d4db717884ffa9a2de657f60ed4bb74a70a"
+        },
+        "regz": {
+            "url": "https://github.com/ZigEmbeddedGroup/regz/archive/d66ffd56f51fc46c071412141b5d0c74dc83c310.tar.gz",
+            "hash": "122002c5f2e31c11373ede6e8a8dd9a61aabd60d38df667ec33b5f994d1f0b503823"
+        }
+    }
+}
\ No newline at end of file
diff --git a/core/build.zig.zon b/core/build.zig.zon
deleted file mode 100644
index 437acb5f9..000000000
--- a/core/build.zig.zon
+++ /dev/null
@@ -1,29 +0,0 @@
-.{
-    .name = "microzig",
-    .version = "0.1.0",
-    .paths = .{
-        "build.zig",
-        "build.zig.zon",
-        "design",
-        "docs",
-        "LICENSE",
-        "README.adoc",
-        "src",
-        "test",
-        "thoughts.md",
-    },
-    .dependencies = .{
-        .uf2 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/8037b439ccbac862471392b25e94a8995d784e2c.tar.gz",
-            .hash = "1220cc66563fc1ecefca7990968441dc9d4db717884ffa9a2de657f60ed4bb74a70a",
-        },
-        .regz = .{
-            .url = "https://github.com/ZigEmbeddedGroup/regz/archive/d66ffd56f51fc46c071412141b5d0c74dc83c310.tar.gz",
-            .hash = "122002c5f2e31c11373ede6e8a8dd9a61aabd60d38df667ec33b5f994d1f0b503823",
-        },
-        .@"umm-zig" = .{
-            .url = "https://github.com/ZigEmbeddedGroup/umm-zig/archive/99d815adfbc5cc4ad385dd765a6192f85e54179f.tar.gz",
-            .hash = "12207ef7375ea45e97f4fba9c5dfa74d022902893c4dbf1a0076726b7ec39a02ea3f",
-        },
-    },
-}
diff --git a/core/microzig-package.json b/core/microzig-package.json
index ed42e68ac..6d49cb335 100644
--- a/core/microzig-package.json
+++ b/core/microzig-package.json
@@ -1,4 +1,10 @@
 {
-  "package_name": "microzig",
-  "package_type": "core"
-}
+    "package_name": "core",
+    "package_type": "core",
+    "external_dependencies": {
+        "umm-zig": {
+            "url": "https://github.com/ZigEmbeddedGroup/umm-zig/archive/99d815adfbc5cc4ad385dd765a6192f85e54179f.tar.gz",
+            "hash": "12207ef7375ea45e97f4fba9c5dfa74d022902893c4dbf1a0076726b7ec39a02ea3f"
+        }
+    }
+}
\ No newline at end of file
diff --git a/flake.lock b/flake.lock
index d614e0c7e..0776794e5 100644
--- a/flake.lock
+++ b/flake.lock
@@ -67,16 +67,16 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1704290814,
-        "narHash": "sha256-LWvKHp7kGxk/GEtlrGYV68qIvPHkU9iToomNFGagixU=",
+        "lastModified": 1704766047,
+        "narHash": "sha256-q9tH9yvUWVBh5XpWafpCYAYf72ZyNhfmpgfR4fwM6uw=",
         "owner": "nixos",
         "repo": "nixpkgs",
-        "rev": "70bdadeb94ffc8806c0570eb5c2695ad29f0e421",
+        "rev": "cc2f101c016d42b728a9cb8244215a5d2d98f6df",
         "type": "github"
       },
       "original": {
         "owner": "nixos",
-        "ref": "release-23.05",
+        "ref": "release-23.11",
         "repo": "nixpkgs",
         "type": "github"
       }
diff --git a/flake.nix b/flake.nix
index c778a9697..599201eec 100644
--- a/flake.nix
+++ b/flake.nix
@@ -2,7 +2,7 @@
   description = "microzig development environment";
 
   inputs = {
-    nixpkgs.url = "github:nixos/nixpkgs/release-23.05";
+    nixpkgs.url = "github:nixos/nixpkgs/release-23.11";
     flake-utils.url = "github:numtide/flake-utils";
 
     # required for latest zig
@@ -15,29 +15,83 @@
     };
   };
 
-  outputs = {
-    self,
-    nixpkgs,
-    flake-utils,
-    ...
-  } @ inputs: let
-    overlays = [
-      # Other overlays
-      (final: prev: {
-        zigpkgs = inputs.zig.packages.${prev.system};
-      })
-    ];
-
-    # Our supported systems are the same supported systems as the Zig binaries
-    systems = builtins.attrNames inputs.zig.packages;
-  in
+  outputs =
+    { self
+    , nixpkgs
+    , flake-utils
+    , ...
+    } @ inputs:
+    let
+      overlays = [
+        # Other overlays
+        (final: prev: {
+          zigpkgs = inputs.zig.packages.${prev.system};
+        })
+      ];
+
+      # Our supported systems are the same supported systems as the Zig binaries
+      systems = builtins.attrNames inputs.zig.packages;
+
+
+      # buildenv-python-pkgs = ps: with ps; [
+      #   # ...
+      #   (
+      #     # https://files.pythonhosted.org/packages/26/b4/bd652fbd5cbfa4f149e1630c0da70dc3c37ac27187eb8425eb403bd28a88/dataclasses_json-0.6.3.tar.gz
+      #     buildPythonPackage rec {
+      #       pname = "dataclasses_json";
+      #       version = "0.6.3";
+      #       pyproject = true;
+      #       src = fetchPypi {
+      #         inherit pname version;
+      #         sha256 = "sha256-NctAqugkc2/flZgBNWZBg2NlIZz+FMrrEVw5E293XSo=";
+      #       };
+      #       doCheck = false;
+      #       propagatedBuildInputs = [
+      #         # Specify dependencies
+      #         ps.poetry-dynamic-versioning
+      #         pkgs.poetry
+      #         ps.poetry-core
+      #       ];
+      #     }
+      #   )
+      # ];
+
+    in
     flake-utils.lib.eachSystem systems (
-      system: let
-        pkgs = import nixpkgs {inherit overlays system;};
-      in rec {
+      system:
+      let
+        pkgs = import nixpkgs { inherit overlays system; };
+      in
+      let
+
+        python3 = pkgs.python3.override {
+          self = python3;
+          packageOverrides = self: super: {
+            dataclasses_json = self.buildPythonPackage rec {
+              pname = "dataclasses_json";
+              format = "pyproject";
+              version = "0.6.3";
+              src = self.fetchPypi {
+                inherit pname version;
+                sha256 = "sha256-NctAqugkc2/flZgBNWZBg2NlIZz+FMrrEVw5E293XSo=";
+              };
+              doCheck = false;
+              nativeBuildInputs = [ self.poetry-dynamic-versioning self.poetry-core ];
+            };
+          };
+        };
+      in
+      rec {
         devShells.default = pkgs.mkShell {
           nativeBuildInputs = [
             pkgs.zigpkgs."0.11.0"
+            (python3.withPackages (ps: [
+              ps.dataclasses_json
+              ps.marshmallow
+              ps.typing-inspect
+              ps.semver
+              ps.pathspec
+            ]))
           ];
 
           buildInputs = [
diff --git a/for-extraction/uf2-flasher/build.zig b/for-extraction/uf2-flasher/build.zig
new file mode 100644
index 000000000..c14804666
--- /dev/null
+++ b/for-extraction/uf2-flasher/build.zig
@@ -0,0 +1,19 @@
+const std = @import("std");
+
+pub fn build(b: *std.Build) !void {
+    const target = b.standardTargetOptions(.{});
+    const optimize = b.standardOptimizeOption(.{});
+
+    const args_dep = b.dependency("args", .{});
+    const args_mod = args_dep.module("args");
+
+    const flash_tool = b.addExecutable(.{
+        .name = "uf2-flash",
+        .root_source_file = .{ .path = "src/main.zig" },
+        .optimize = optimize,
+        .target = target,
+    });
+    flash_tool.addModule("args", args_mod);
+
+    b.installArtifact(flash_tool);
+}
diff --git a/board-support/raspberrypi-rp2040/build.zig.zon b/for-extraction/uf2-flasher/build.zig.zon
similarity index 100%
rename from board-support/raspberrypi-rp2040/build.zig.zon
rename to for-extraction/uf2-flasher/build.zig.zon
diff --git a/for-extraction/uf2-flasher/src/main.zig b/for-extraction/uf2-flasher/src/main.zig
new file mode 100644
index 000000000..3a8af68ed
--- /dev/null
+++ b/for-extraction/uf2-flasher/src/main.zig
@@ -0,0 +1,333 @@
+const std = @import("std");
+const args_parser = @import("args");
+const builtin = @import("builtin");
+
+const CliOptions = struct {
+    help: bool = false,
+    device: ?[]const u8 = null,
+    wait: bool = false,
+
+    pub const shorthands = .{
+        .h = "help",
+        .d = "device",
+        .w = "wait",
+    };
+};
+
+const wait_device_ready_timeout = 60 * std.time.ns_per_s; // timeout until a device is found
+const wait_device_avail_timeout = 60 * std.time.ns_per_s; // timeout until a device is found
+const access_denied_limit = 20; // try that many times with AccessDenied before the user is informed
+
+fn print_usage(file: std.fs.File, exe: ?[]const u8) !void {
+    try file.writer().writeAll(exe orelse "uf2-flash");
+    try file.writer().writeAll(
+        \\ [-h] [-d ] 
+        \\Flash devices easily via the UF2 interface.
+        \\
+        \\Options:
+        \\  -h, --help          Shows this help text.
+        \\  -d, --device  Uses  as the UF2 device. Otherwise tries to auto-guess the correct device.
+        \\  -w, --wait          Waits 60 seconds until a device appears.
+        \\
+    );
+}
+
+pub fn main() !u8 {
+    const stderr = std.io.getStdErr();
+    const stdout = std.io.getStdOut();
+    const stdin = std.io.getStdIn();
+
+    var arena = std.heap.ArenaAllocator.init(std.heap.page_allocator);
+    defer _ = arena.deinit();
+
+    const allocator = arena.allocator();
+
+    var cli = args_parser.parseForCurrentProcess(CliOptions, allocator, .print) catch return 1;
+    defer cli.deinit();
+
+    if (cli.options.help) {
+        try print_usage(stdout, cli.executable_name);
+        return 0;
+    }
+
+    if (cli.positionals.len != 1) {
+        try print_usage(stderr, cli.executable_name);
+        return 1;
+    }
+
+    const uf2_file_path = cli.positionals[0];
+
+    var uf2_file = try std.fs.cwd().openFile(uf2_file_path, .{});
+    defer uf2_file.close();
+
+    const uf2_stat = try uf2_file.stat();
+    if ((uf2_stat.size % 512) != 0) {
+        std.log.warn("{s} does not have a size multiple of 512. might be corrupt!", .{uf2_file_path});
+    }
+
+    const file_valid = blk: {
+        try uf2_file.seekTo(0);
+
+        var file_valid = true;
+
+        while (file_valid) {
+            var block: [512]u8 = undefined;
+            const len = try uf2_file.read(&block);
+            if (len == 0)
+                break;
+
+            // 0    4   First magic number, 0x0A324655 ("UF2\n")
+            // 4    4   Second magic number, 0x9E5D5157
+            // 8    4   Flags
+            // 12   4   Address in flash where the data should be written
+            // 16   4   Number of bytes used in data (often 256)
+            // 20   4   Sequential block number; starts at 0
+            // 24   4   Total number of blocks in file
+            // 28   4   File size or board family ID or zero
+            //                          32   476 Data, padded with zeros
+            // 508  4   Final magic number, 0x0AB16F30
+
+            const first_magic_number = std.mem.readIntLittle(u32, block[0..][0..4]);
+            const second_magic_number = std.mem.readIntLittle(u32, block[4..][0..4]);
+            const final_magic_number = std.mem.readIntLittle(u32, block[508..][0..4]);
+
+            file_valid = file_valid and (first_magic_number == 0x0A324655);
+            file_valid = file_valid and (second_magic_number == 0x9E5D5157);
+            file_valid = file_valid and (final_magic_number == 0x0AB16F30);
+
+            // TODO: Use [File size or board family ID or zero] field to determine the way to find the UF2 device.
+        }
+        break :blk file_valid;
+    };
+
+    if (file_valid == false) {
+        std.log.warn("{s} does not seem to be a valid UF2 file. Do you really want to flash it?", .{uf2_file_path});
+        while (true) {
+            try stderr.writer().writeAll("Flash? [jN]: ");
+
+            var buffer: [64]u8 = undefined;
+            const selection_or_null = try stdin.reader().readUntilDelimiterOrEof(&buffer, '\n');
+
+            const selection_str = std.mem.trim(u8, selection_or_null orelse "", "\r\n\t ");
+            if (selection_str.len == 0)
+                return 1;
+
+            if (std.ascii.eqlIgnoreCase(selection_str, "j"))
+                break;
+
+            if (std.ascii.eqlIgnoreCase(selection_str, "n"))
+                return 1;
+        }
+    }
+
+    try uf2_file.seekTo(0);
+
+    const detect_timeout = std.time.nanoTimestamp() + wait_device_avail_timeout;
+    var first_run = true;
+    const device_path = if (cli.options.device) |devname|
+        try allocator.dupe(u8, devname)
+    else while (true) {
+        if (std.time.nanoTimestamp() >= detect_timeout) {
+            try stderr.writeAll("failed to detect any RP2040 devices :(\n");
+
+            return 1;
+        }
+
+        const maybe_device = try autoDetectPico(allocator);
+
+        if (maybe_device) |device|
+            break device;
+
+        if (!cli.options.wait) {
+            try stderr.writeAll("failed to detect any RP2040 devices :(\n");
+            return 1;
+        }
+
+        if (first_run) {
+            try stderr.writeAll("failed to detect any RP2040 devices, waiting...\n");
+            first_run = false;
+        }
+
+        std.time.sleep(250 * std.time.ns_per_ms);
+    };
+
+    const connect_timeout = std.time.nanoTimestamp() + wait_device_ready_timeout;
+
+    var first_attempt = true;
+    var access_denied_counter: u32 = 0;
+    var last_err: anyerror = error.Unknown;
+    var device_file: std.fs.File = blk: while (std.time.nanoTimestamp() < connect_timeout) {
+        var device = std.fs.cwd().openFile(device_path, .{ .mode = .write_only }) catch |err| {
+            last_err = err;
+
+            switch (err) {
+                error.FileNotFound => {}, // just waiting for the device
+                error.AccessDenied => {
+                    access_denied_counter += 1;
+                    if (access_denied_counter >= access_denied_limit) {
+                        try stderr.writer().print("Could not open {s}: Access denied. Do you have write-access to the device?\n", .{device_path});
+                        return 1;
+                    }
+                },
+                else => |e| return e,
+            }
+
+            if (first_attempt) {
+                try stderr.writer().print("Waiting for {s}.", .{device_path});
+                first_attempt = false;
+            } else {
+                try stderr.writeAll(".");
+            }
+            std.time.sleep(250 * std.time.ns_per_ms);
+            continue;
+        };
+        try stderr.writeAll("\n");
+        break :blk device;
+    } else {
+        try stderr.writer().print("\nfailed to connect to {s}: {s}\n", .{ device_path, @errorName(last_err) });
+        return 1;
+    };
+    defer device_file.close();
+
+    try stderr.writeAll("Flashing");
+
+    {
+        try uf2_file.seekTo(0);
+
+        var block_num: u64 = 0;
+        while (true) {
+            try stderr.writeAll(".");
+
+            var block: [512]u8 = undefined;
+            const rd_len = try uf2_file.read(&block);
+            if (rd_len == 0)
+                break;
+            if (rd_len != block.len) {
+                try stderr.writer().print("\nFailed to read block {}: Only {} bytes read!\n", .{ block_num, rd_len });
+                return 1;
+            }
+
+            const wr_len = try device_file.write(&block);
+            if (wr_len != block.len) {
+                try stderr.writer().print("\nFailed to write block {}: Only {} bytes written!\n", .{ block_num, wr_len });
+                return 1;
+            }
+
+            block_num += 1;
+        }
+    }
+    try stderr.writeAll("\nDone.\n");
+
+    return 0;
+}
+
+fn autoDetectPico(allocator: std.mem.Allocator) !?[]const u8 {
+    switch (builtin.os.tag) {
+        .linux => {
+            const stdin = std.io.getStdIn();
+            const stderr = std.io.getStdErr();
+
+            const Device = struct {
+                name: []const u8,
+                path: []const u8,
+            };
+
+            var picos = std.ArrayList(Device).init(allocator);
+            defer picos.deinit();
+
+            var base_dir = try std.fs.openIterableDirAbsolute("/sys/block/", .{});
+            defer base_dir.close();
+
+            var iter = base_dir.iterate();
+
+            while (try iter.next()) |entry| {
+                var device_dir = try base_dir.dir.openDir(entry.name, .{});
+                defer device_dir.close();
+
+                const H = struct {
+                    fn isPicoDevice(dir: std.fs.Dir, allo: std.mem.Allocator) !?[]const u8 {
+                        // "/sys/block/*/removable" => "1"
+                        // "/sys/block/*/device/model" => "RP2"
+                        // "/sys/block/*/device/vendor" => "RPI"
+
+                        var buffer: [64]u8 = undefined;
+
+                        const removable = std.mem.trim(u8, try dir.readFile("removable", &buffer), "\r\n\t ");
+                        if (!std.mem.eql(u8, removable, "1"))
+                            return null;
+
+                        const device_model = std.mem.trim(u8, try dir.readFile("device/model", &buffer), "\r\n\t ");
+                        if (!std.mem.eql(u8, device_model, "RP2"))
+                            return null;
+
+                        const device_vendor = std.mem.trim(u8, try dir.readFile("device/vendor", &buffer), "\r\n\t ");
+                        if (!std.mem.eql(u8, device_vendor, "RPI"))
+                            return null;
+
+                        const device_id = std.mem.trim(u8, try dir.readFile("dev", &buffer), "\r\n\t ");
+
+                        return try std.fs.path.join(allo, &.{
+                            "/dev/block", device_id,
+                        });
+                    }
+                };
+
+                const maybe_device = H.isPicoDevice(device_dir, allocator) catch |err| {
+                    if (err != error.FileNotFound and err != error.AccessDenied) {
+                        std.log.err("failed to scan /sys/block/{s}: {s}", .{ entry.name, @errorName(err) });
+                    }
+                    continue;
+                };
+
+                if (maybe_device) |device_path| {
+                    try picos.append(Device{
+                        .name = try allocator.dupe(u8, entry.name),
+                        .path = device_path,
+                    });
+                }
+            }
+
+            if (picos.items.len == 0) {
+                return null;
+            }
+
+            var default_selection: usize = 0;
+
+            try stderr.writer().writeAll("Select your device:\n");
+            for (picos.items, 1..) |pico_dev, index| {
+                try stderr.writer().print("#{d: <2} {s}\n", .{ index, pico_dev.name });
+
+                if (default_selection == 0) {
+                    default_selection = index;
+                }
+            }
+
+            const selection = while (true) {
+                try stderr.writer().print("Select port [{}]: ", .{default_selection});
+
+                var buffer: [64]u8 = undefined;
+                const selection_or_null = try stdin.reader().readUntilDelimiterOrEof(&buffer, '\n');
+
+                const selection_str = std.mem.trim(u8, selection_or_null orelse break default_selection, "\r\n\t ");
+
+                if (selection_str.len == 0)
+                    break default_selection;
+
+                const selection = std.fmt.parseInt(usize, selection_str, 10) catch continue;
+
+                if (selection < 1 or selection > picos.items.len) {
+                    continue;
+                }
+
+                break selection;
+            };
+
+            return picos.items[selection - 1].path;
+        },
+
+        else => {
+            std.log.warn("Device auto-detection not implemented for {s}", .{@tagName(builtin.os.tag)});
+            return null;
+        },
+    }
+}
diff --git a/tools/archive-info.zig b/tools/archive-info.zig
index d563c0c05..049d98150 100644
--- a/tools/archive-info.zig
+++ b/tools/archive-info.zig
@@ -21,8 +21,14 @@ const JsonInfo = struct {
 pub fn main() !void {
     var gpa = std.heap.GeneralPurposeAllocator(.{}){};
     defer _ = gpa.deinit();
+
     const allocator = gpa.allocator();
 
+    var arena_impl = std.heap.ArenaAllocator.init(allocator);
+    defer arena_impl.deinit();
+
+    const arena = arena_impl.allocator();
+
     const argv = try std.process.argsAlloc(allocator);
     defer std.process.argsFree(allocator, argv);
 
@@ -35,13 +41,13 @@ pub fn main() !void {
 
     var buffered = std.io.bufferedReaderSize(4096, file.reader());
 
-    var decompress = try std.compress.gzip.decompress(allocator, buffered.reader());
-    defer decompress.deinit();
+    // var decompress = try std.compress.gzip.decompress(allocator, buffered.reader());
+    // defer decompress.deinit();
 
-    var arc = try Archive.read_from_tar(allocator, decompress.reader(), .{
+    var arc = try Archive.read_from_tar(arena, buffered.reader(), .{
         .strip_components = 0,
     });
-    defer arc.deinit(allocator);
+    defer arc.deinit(arena);
 
     {
         var paths = std.ArrayList([]const u8).init(allocator);
@@ -197,9 +203,11 @@ const Archive = struct {
                     if (start + rounded_file_size > end) return error.TarHeadersTooBig;
                     start = @as(usize, @intCast(start + rounded_file_size));
                 },
-                .hard_link => return error.TarUnsupportedFileType,
-                .symbolic_link => return error.TarUnsupportedFileType,
-                else => return error.TarUnsupportedFileType,
+                // includes .symlink, .hardlink
+                else => {
+                    std.log.err("unsupported tar type ({}) for '{s}'", .{ header.fileType(), unstripped_file_name });
+                    return error.TarUnsupportedFileType;
+                },
             }
         }
 
diff --git a/tools/bundle.py b/tools/bundle.py
new file mode 100755
index 000000000..1d6ab9ea2
--- /dev/null
+++ b/tools/bundle.py
@@ -0,0 +1,473 @@
+#!/usr/bin/env python3
+#
+# Prepares a full deployment of MicroZig.
+# Creates all packages into /microzig-deploy with the final folder structure.
+#
+
+import sys, os, subprocess,datetime, re, shutil, json, hashlib
+from pathlib import Path, PurePosixPath
+from dataclasses import dataclass, field 
+from dataclasses_json import dataclass_json, config as  dcj_config, Exclude as JsonExclude
+from semver import Version
+from marshmallow import fields
+from enum import Enum as StrEnum
+import pathspec
+import stat 
+from marshmallow import fields as mm_fields
+from typing import Optional
+
+
+VERBOSE = False 
+ALL_FILES_DIR=".data"
+REQUIRED_TOOLS = [
+    "zig",
+    "git",
+    # "date",
+    # "find",
+    # "jq",
+    # "mkdir",
+    # "dirname",
+    # "realpath",
+]
+
+REPO_ROOT = Path(__file__).parent.parent
+assert REPO_ROOT.is_dir()
+
+
+
+
+class PackageType(StrEnum):
+    build = "build"
+    core = "core"
+    board_support = "board-support"
+
+@dataclass_json
+@dataclass
+class Archive:
+    size: int
+    sha256sum: str
+
+@dataclass_json
+@dataclass
+class Package:
+    hash: str
+    files: list[str] = field(default_factory=lambda:[])
+
+@dataclass_json
+@dataclass
+class ExternalDependency:
+    url: str
+    hash: str 
+    
+@dataclass_json
+@dataclass
+class Timestamp:
+    unix: str
+    iso: str 
+
+@dataclass_json
+@dataclass
+class PackageConfiguration:
+    package_name: str 
+    package_type: PackageType
+
+    version: Optional[Version] = field(default=None, metadata=dcj_config(decoder=Version.parse, encoder=Version.__str__, mm_field=fields.String()))
+    
+    external_dependencies: dict[str,ExternalDependency] = field(default_factory=lambda:dict())
+    inner_dependencies: set[str] = field(default_factory=lambda:set())
+    
+    archive: Optional[Archive] = field(default = None)
+    created: Optional[Timestamp] = field(default = None)
+    package: Optional[Package]  = field(default= None)
+
+    # inner fields:
+    # package_dir: Path = field(default=None, metadata = dcj_config(exclude=JsonExclude.ALWAYS))
+
+PackageSchema = Package.schema()
+PackageConfigurationSchema = PackageConfiguration.schema()
+
+def file_digest(path: Path, hashfunc) -> bytes:
+    BUF_SIZE = 65536
+
+    digest = hashfunc()
+
+    with path.open('rb') as f:
+        while True:
+            data = f.read(BUF_SIZE)
+            if not data:
+                break
+            digest.update(data)
+
+    return digest.digest()
+
+
+FILE_STAT_MAP = {
+    stat.S_IFDIR: "directory",
+    stat.S_IFCHR: "character device",
+    stat.S_IFBLK: "block device",
+    stat.S_IFREG: "regular",
+    stat.S_IFIFO: "fifo",
+    stat.S_IFLNK: "link",
+    stat.S_IFSOCK: "socket",
+    }
+
+def file_type(path: Path) -> str:
+    return FILE_STAT_MAP[stat.S_IFMT( path.stat().st_mode)]
+
+def execute_raw(*args,hide_stderr = False,**kwargs):
+    args = [ str(f) for f in args]
+    if VERBOSE:
+        print(*args)
+    res = subprocess.run(args, **kwargs, check=False)
+    if res.stderr is not None and (not hide_stderr or res.returncode != 0):
+        sys.stderr.buffer.write(res.stderr)
+    if res.returncode != 0:
+        sys.stderr.write(f"command {' '.join(args)} failed with exit code {res.returncode}")
+    res.check_returncode()
+    return res 
+
+def execute(*args,**kwargs):
+    execute_raw(*args, **kwargs, capture_output=False)
+
+def slurp(*args, **kwargs):
+    res = execute_raw(*args, **kwargs, capture_output=True)
+    return res.stdout
+
+def check_required_tools():
+    for tool in REQUIRED_TOOLS:
+        slurp("which", tool)
+
+
+def check_zig_version(expected):
+    actual = slurp("zig", "version")
+    if actual.strip() != expected.encode():
+        raise RuntimeError(f"Unexpected zig version! Expected {expected}, but found {actual.strip()}!")
+
+def build_zig_tools():    
+    # ensure we have our tools available:
+    execute("zig", "build", "tools", cwd=REPO_ROOT)
+
+    archive_info = REPO_ROOT / "zig-out/tools/archive-info"
+    create_pkg_descriptor = REPO_ROOT / "zig-out/tools/create-pkg-descriptor"
+    
+    assert archive_info.is_file()
+    assert create_pkg_descriptor.is_file()
+
+    return {
+        "archive_info": archive_info,
+        "create_pkg_descriptor": create_pkg_descriptor,
+    }
+
+
+# Determines the correct version:
+def get_version_from_git() -> str:
+
+    raw_git_out = slurp("git", "describe", "--match", "*.*.*", "--tags", "--abbrev=9", cwd=REPO_ROOT).strip().decode()
+
+    def render_version(major,minor,patch,counter,hash):
+        return f"{major}.{minor}.{patch}-{counter}-{hash}"
+    
+    full_version = re.match('^([0-9]+)\.([0-9]+)\.([0-9]+)\-([0-9]+)\-([a-z0-9]+)$', raw_git_out)
+    if full_version:
+        return render_version(*full_version.groups())
+
+    
+    base_version = re.match('^([0-9]+)\.([0-9]+)\.([0-9]+)$', raw_git_out)
+    if base_version:
+        commit_hash = slurp("git", "rev-parse", "--short=9", "HEAD")
+        return render_version(*base_version.groups(), 0, commit_hash) 
+
+    raise RuntimeError(f"Bad result '{raw_git_out}' from git describe.")
+    
+
+def create_output_directory(repo_root: Path) -> Path:
+
+    deploy_target=repo_root / "microzig-deploy"
+    if deploy_target.is_dir():
+        shutil.rmtree(deploy_target)
+    assert not deploy_target.exists()
+
+    deploy_target.mkdir()
+
+    return deploy_target
+
+def resolve_dependency_order(packages: dict[PackageConfiguration]) -> list[PackageConfiguration]:
+
+    open_list = list(packages.values())
+
+    closed_set = set()
+    closed_list = []
+    while len(open_list) > 0:
+
+        head = open_list.pop(0)
+
+        all_resolved = True
+        for dep_name in head.inner_dependencies:
+            
+            dep = packages[dep_name]
+
+            if dep.package_name not in closed_set:
+                all_resolved = False
+                break 
+        
+        if all_resolved:
+            closed_set.add(head.package_name)
+            closed_list.append(head)
+        else:
+            open_list.append(head)
+
+    return closed_list
+
+def get_batch_timestamp():
+    render_time = datetime.datetime.now()
+    return Timestamp(
+        unix=str(int(render_time.timestamp())),
+        iso=render_time.isoformat(),
+    )
+
+def main():
+
+    check_required_tools()
+
+    check_zig_version("0.11.0")
+
+    print("preparing environment...")
+
+    deploy_target = create_output_directory(REPO_ROOT)    
+
+    # Some generic meta information:
+    batch_timestamp = get_batch_timestamp()
+
+    version = get_version_from_git()
+
+    tools = build_zig_tools()
+
+    # After building the tools, zig-cache should exist, so we can tap into it for our own caching purposes:
+
+    cache_root = REPO_ROOT / "zig-cache"
+    assert cache_root.is_dir()
+
+    cache_dir = cache_root / "microzig"
+    cache_root.mkdir(exist_ok=True)
+
+    # Prepare `.gitignore` pattern matcher:
+    global_ignore_spec = pathspec.PathSpec.from_lines(
+        pathspec.patterns.GitWildMatchPattern, 
+        (REPO_ROOT / ".gitignore").read_text().splitlines(),
+    )
+
+    # also insert a pattern to exclude 
+    global_ignore_spec.patterns.append(
+        pathspec.patterns.GitWildMatchPattern("microzig-package.json")
+    )
+
+    print(global_ignore_spec)      
+
+    # Fetch and find all packages:
+
+    print("validating packages...")
+
+    packages = {}
+    validation_ok = True
+
+    for meta_path in REPO_ROOT.rglob("microzig-package.json"):
+        assert meta_path.is_file()
+
+        pkg_dir = meta_path.parent
+
+        pkg_dict = json.loads(meta_path.read_bytes())
+        pkg = PackageConfigurationSchema.load(pkg_dict)
+
+        pkg.version = version
+        pkg.created = batch_timestamp
+        pkg.package_dir = pkg_dir
+
+        if pkg.package_type == PackageType.core:
+            pass
+        elif pkg.package_type == PackageType.build:
+            pass        
+        elif pkg.package_type == PackageType.board_support:
+            pkg.inner_dependencies.add("core") # BSPs implicitly depend on the core "microzig" package
+        else:
+            assert False 
+
+        buildzig_path = pkg_dir / "build.zig"
+        buildzon_path = pkg_dir / "build.zig.zon"
+        
+        if not buildzig_path.is_file():
+            print("")
+            print(f"The package at {meta_path} is missing its build.zig file: {buildzig_path}")
+            print("Please create a build.zig for that package!")
+            validation_ok = False
+            
+        if buildzon_path.is_file():
+            print("")
+            print(f"The package at {meta_path} has a build.zig.zon: {buildzon_path}")
+            print("Please remove that file and merge it into microzig-package.json!")
+            validation_ok = False
+        
+        if pkg.package_name not in packages:
+            packages[pkg.package_name] = pkg
+        else:
+            print("")
+            print(f"The package at {meta_path} has a duplicate package name {pkg.package_name}")
+            print("Please remove that file and merge it into microzig-package.json!")
+            validation_ok = False
+
+        # print("%d\t%s\n", "${pkg_prio}" "${reldir}" >> "${cache_dir}/packages.raw")
+
+    # cat "${cache_dir}/packages.raw" | sort | cut -f 2 > "${cache_dir}/packages.list"
+
+    if not validation_ok:
+        print("Not all packages are valid. Fix the packages and try again!" )
+        exit(1)
+
+    print("loaded packages:")
+    for key in packages:
+        print(f"  * {key}")
+
+    print("resolving inner dependencies...")
+    
+    evaluation_ordered_packages = resolve_dependency_order(packages)
+
+    # bundle everything:
+
+    
+
+
+    print("creating packages...")
+    for pkg in evaluation_ordered_packages:
+        print(f"bundling {pkg.package_name}...")
+        
+        pkg_dir = pkg.package_dir        
+
+        pkg_cache_dir = cache_dir / hashlib.md5(pkg.package_name.encode()).hexdigest()
+        pkg_cache_dir.mkdir(exist_ok=True)
+        
+        meta_path = pkg_dir / "microzig-package.json"
+        pkg_zon_file = pkg_cache_dir / "build.zig.zon" 
+
+        out_rel_dir: PurePosixPath 
+        out_basename: str 
+        extra_json: dict = {}
+        
+        if pkg.package_type == PackageType.build:
+            out_rel_dir = PurePosixPath(".")
+            out_basename = pkg.package_name
+
+        elif pkg.package_type == PackageType.core:
+            out_rel_dir = PurePosixPath(".")
+            out_basename = pkg.package_name
+
+        elif pkg.package_type == PackageType.board_support:
+            parsed_pkg_name = PurePosixPath(pkg.package_name)
+
+            out_rel_dir = "board-support" / parsed_pkg_name.parent
+            out_basename = parsed_pkg_name.name
+
+            bsp_info = slurp(
+                "zig", "build-exe",
+                    f"{REPO_ROOT}/tools/extract-bsp-info.zig" ,
+                    "--cache-dir", f"{REPO_ROOT}/zig-cache",
+                    "--deps", "bsp,microzig",
+                    "--mod", f"bsp:microzig:{pkg_dir}/build.zig",
+                    "--mod", f"microzig:uf2:{REPO_ROOT}/core/build.zig",
+                    "--mod", f"uf2::{REPO_ROOT}/tools/lib/dummy_uf2.zig",
+                    "--name", "extract-bsp-info",
+                cwd=pkg_cache_dir,
+            )
+
+            extra_json_str=slurp(pkg_cache_dir/"extract-bsp-info")
+
+            extra_json = json.loads(extra_json_str)
+
+        else:
+            assert False 
+
+        assert out_rel_dir is not None
+        assert out_basename is not None
+        assert isinstance(extra_json, dict)
+
+        # File names:
+
+        out_file_name_tar = f"{out_basename}-{version}.tar"
+        out_file_name_compr = f"{out_file_name_tar}.gz"
+        out_file_name_meta = f"{out_basename}-{version}.json"
+
+        out_symlink_pkg_name = f"{out_basename}.tar.gz"
+        out_symlink_meta_name = f"{out_basename}.json"
+
+        
+        # Directories_:        
+        out_base_dir = deploy_target / out_rel_dir
+        out_data_dir = out_base_dir / ALL_FILES_DIR
+
+        # paths:
+        out_file_tar = out_data_dir / out_file_name_tar
+        out_file_targz = out_data_dir / out_file_name_compr
+        out_file_meta = out_data_dir / out_file_name_meta
+
+        out_symlink_pkg = out_base_dir / out_symlink_pkg_name
+        out_symlink_meta = out_base_dir / out_symlink_meta_name
+   
+        # ensure the directories exist:
+        out_base_dir.mkdir(parents = True, exist_ok=True)
+        out_data_dir.mkdir(parents = True, exist_ok=True)
+
+        # find files that should be packaged:
+
+        package_files = [*global_ignore_spec.match_tree(pkg_dir,negate = True )]
+        # package_files = [ 
+        #     file.relative_to(pkg_dir)
+        #     for file in pkg_dir.rglob("*") 
+        #         if not global_ignore_spec.match_file(str(file))
+        #         if file.name != 
+        # ]
+
+        if VERBOSE:
+            print("\n".join(f"  * {str(f)} ({file_type(pkg_dir / f)})" for f in package_files))
+            print()
+
+        # tar -cf "${out_tar}" $(git ls-files -- . ':!:microzig-package.json')
+        execute("tar", "-cf", out_file_tar, "--hard-dereference", *package_files, cwd=pkg_dir)
+
+        zon_data = slurp(
+            tools["create_pkg_descriptor"], version, out_rel_dir, 
+            input=PackageConfigurationSchema.dumps(pkg).encode(),
+        )
+
+        with pkg_zon_file.open("wb") as f:
+            f.write(zon_data)
+
+        slurp("zig", "fmt", pkg_zon_file) # slurp the message away
+
+        execute("tar", "-rf", out_file_tar, "--hard-dereference", pkg_zon_file.name, cwd=pkg_zon_file.parent)
+
+        # tar --list --file "${out_tar}" > "${pkg_cache_dir}/contents.list"
+        
+        zig_pkg_info_str = slurp(tools["archive_info"], out_file_tar)
+        pkg.package = PackageSchema.loads(zig_pkg_info_str)
+
+        # explicitly use maximum compression level here as we're shipping to potentially many people
+        execute("gzip", "-f9", out_file_tar)
+        assert not out_file_tar.exists()
+        assert out_file_targz.is_file()
+        del out_file_tar
+
+        pkg.archive = Archive(
+            sha256sum = file_digest(out_file_targz, hashlib.sha256).hex(),
+            size = str(out_file_targz.stat().st_size),
+        )
+        
+        with out_file_meta.open("w") as f:
+            f.write(PackageConfigurationSchema.dumps(pkg))
+
+        out_symlink_pkg.symlink_to(out_file_targz.relative_to(out_symlink_pkg.parent))
+        out_symlink_meta.symlink_to(out_file_meta.relative_to(out_symlink_meta.parent))
+
+    # TODO: Verify that each package can be unpacked and built
+
+
+
+if __name__ == "__main__":
+    main()
\ No newline at end of file
diff --git a/tools/bundle.sh b/tools/bundle.sh
deleted file mode 100755
index 3f19239f1..000000000
--- a/tools/bundle.sh
+++ /dev/null
@@ -1,169 +0,0 @@
-#!/bin/sh
-
-#
-# Prepares a full deployment of MicroZig.
-# Creates all packages into /microzig-deploy with the final folder structure.
-#
-
-set -eu
-
-all_files_dir=".data"
-
-# test for all required tools:
-which zig date find jq mkdir dirname realpath > /dev/null
-
-[ "$(zig version)" = "0.11.0" ]
-
-repo_root="$(dirname "$(dirname "$(realpath "$0")")")"
-[ -d "${repo_root}" ]
-
-echo "preparing environment..."
-
-alias create_package="${repo_root}/tools/create-package.sh"
-
-# Some generic meta information:
-
-unix_timestamp="$(date '+%s')"
-iso_timestamp="$(date --iso-8601=seconds)"
-
-# Determine correct version:
-
-git_description="$(git describe --match "*.*.*" --tags --abbrev=9)"
-version=""
-
-# render-version     
-render_version()
-{
-    [ "$#" -eq 5 ] 
-    echo "$1.$2.$3-$4-$5"
-}
-
-case "${git_description}" in 
-    *.*.*-*-*)
-        version="$(render_version $(echo "${git_description}" | sed -E 's/^([0-9]+)\.([0-9]+)\.([0-9]+)\-([0-9]+)\-([a-z0-9]+)$/\1 \2 \3 \4 \5/'))"
-        ;;
-
-    *.*.*)
-        # a "on point" tagged version still has a hash as well as the counter 0!
-        version="$(render_version $(echo "${git_description}" | sed -E 's/^([0-9]+)\.([0-9]+)\.([0-9]+)$/\1 \2 \3/') 0 $(git rev-parse --short=9 HEAD))"
-        ;;
-    
-    *)
-        echo "Bad result '${git_description}' from git describe." >&2
-        exit 1
-        ;;
-esac
-
-if [ -z "${version}" ]; then
-    echo "Could not determine a version. Please verify repository state!" >&2
-    exit 1
-fi
-
-deploy_target="${repo_root}/microzig-deploy"
-
-[ -d "${deploy_target}" ] && rm -r "${deploy_target}"
-mkdir -p "${deploy_target}"
-
-cd "${repo_root}"
-
-# ensure we have our tools available:
-zig build tools
-
-[ -x "${repo_root}/zig-out/tools/archive-info" ]
-alias archive_info="${repo_root}/zig-out/tools/archive-info"
-
-for dir in $(find -type f -name microzig-package.json -exec dirname '{}' ';'); do
-    dir="$(realpath "${dir}")"
-    meta_path="$(realpath "${dir}/microzig-package.json")"
-
-    pkg_name="$(jq -r .package_name < "${meta_path}")"
-    pkg_type="$(jq -r .package_type < "${meta_path}")"
-
-    (
-        cd "${dir}"
-
-        echo "bundling ${dir}..."
-
-        out_dir=""
-        out_basename=""
-        extra_json="{}"
-
-        case "${pkg_type}" in
-            core)
-                out_dir="${deploy_target}"
-                out_basename="${pkg_name}"
-                ;;
-            
-            board-support)
-                out_dir="${deploy_target}/board-support/$(dirname "${pkg_name}")"
-                out_basename="$(basename "${pkg_name}")"
-
-                extra_json="$(
-                    zig run \
-                        "${repo_root}/tools/extract-bsp-info.zig" \
-                        --cache-dir "${repo_root}/zig-cache" \
-                        --deps bsp,microzig \
-                        --mod "bsp:microzig:${dir}/build.zig" \
-                        --mod "microzig:uf2:${repo_root}/core/build.zig" \
-                        --mod "uf2::${repo_root}/tools/lib/dummy_uf2.zig" \
-                )"
-
-                ;;
-
-            *)
-                echo "Unsupported package type: '${pkg_type}'!" >&2
-                exit 1
-                ;;
-        esac
-
-        [ ! -z "${out_dir}" ] && [ ! -z "${out_basename}" ]
-
-        out_fullname="${out_basename}-${version}.tar.gz"
-        out_fullmeta="${out_basename}-${version}.json"
-
-        out_name="${out_basename}.tar.gz"
-        out_meta="${out_basename}.json"
-        
-        out_path="${out_dir}/${all_files_dir}/${out_fullname}"
-
-        mkdir -p "${out_dir}/${all_files_dir}"
-
-        # first, compile package
-        create_package "${dir}" "${out_path}"
-
-        # get some required metadata
-        file_hash="$(sha256sum "${out_path}" | cut -d " " -f 1)"
-        file_size="$(stat --format="%s" "${out_path}")"
-
-        pkg_info="$(archive_info ${out_path})"
-
-        jq \
-            --arg vers "${version}" \
-            --arg ts_unix "${unix_timestamp}" \
-            --arg ts_iso "${iso_timestamp}" \
-            --arg fhash "${file_hash}" \
-            --arg fsize "${file_size}" \
-            --argjson pkg "${pkg_info}" \
-            --argjson extra "${extra_json}" \
-                '. + $extra + {
-                    version: $vers,
-                    created: {
-                        unix: $ts_unix,
-                        iso: $ts_iso,
-                    },
-                    archive: {
-                        size: $fsize,
-                        sha256sum: $fhash,
-                    },
-                    package: $pkg
-                }' \
-            "${meta_path}" \
-            > "${out_dir}/${all_files_dir}/${out_fullmeta}" \
-
-        (
-            cd "${out_dir}"
-            ln -s "${all_files_dir}/${out_fullname}" "${out_name}"
-            ln -s "${all_files_dir}/${out_fullmeta}" "${out_meta}"
-        )
-    )
-done
diff --git a/tools/create-pkg-descriptor.zig b/tools/create-pkg-descriptor.zig
new file mode 100644
index 000000000..e6226f6b8
--- /dev/null
+++ b/tools/create-pkg-descriptor.zig
@@ -0,0 +1,122 @@
+const std = @import("std");
+const eggzon = @import("eggzon");
+
+const fmtEscapes = std.zig.fmtEscapes;
+const fmtId = std.zig.fmtId;
+
+const Archive = struct {
+    sha256sum: []const u8,
+    size: []const u8,
+};
+
+const Package = struct {
+    hash: []const u8,
+    files: []const []const u8,
+};
+
+const Timestamp = struct {
+    iso: []const u8,
+    unix: []const u8,
+};
+
+const MetaData = struct {
+    const Type = enum {
+        @"board-support",
+        core,
+        build,
+    };
+
+    package_name: []const u8,
+    package_type: Type,
+    version: []const u8,
+
+    inner_dependencies: []const []const u8 = &.{},
+    external_dependencies: std.json.Value = .null,
+
+    archive: ?Archive = null,
+    package: ?Package = null,
+    created: ?Timestamp = null,
+};
+
+// create-pkg-descriptor 
+pub fn main() !void {
+    var gpa = std.heap.GeneralPurposeAllocator(.{}){};
+    defer _ = gpa.deinit();
+
+    const allocator = gpa.allocator();
+
+    var arena_impl = std.heap.ArenaAllocator.init(allocator);
+    defer arena_impl.deinit();
+
+    const arena = arena_impl.allocator();
+
+    const argv = try std.process.argsAlloc(arena);
+
+    if (argv.len != 3) {
+        @panic("version and/or relpath missing!");
+    }
+
+    // System configuration:
+    const deployment_base_url = "https://download.microzig.tech/packages"; // TODO: Make those configurable
+
+    // build inputs:
+    const version_string = argv[1];
+    const rel_pkg_path = argv[2];
+
+    const version = try std.SemanticVersion.parse(version_string);
+
+    const json_input = try std.io.getStdIn().readToEndAlloc(arena, 1 << 20);
+
+    errdefer std.log.err("failed to parse json from {s}", .{json_input});
+
+    const metadata = try std.json.parseFromSliceLeaky(MetaData, arena, json_input, .{});
+
+    var buffered_stdout = std.io.bufferedWriter(std.io.getStdOut().writer());
+
+    const stdout = buffered_stdout.writer();
+    {
+        try stdout.writeAll(".{\n");
+        try stdout.print("    .name = \"{}\",\n", .{fmtEscapes(metadata.package_name)});
+        try stdout.print("    .version = \"{}\",\n", .{version});
+        try stdout.writeAll("    .dependencies = .{\n");
+        if (metadata.external_dependencies != .null) {
+            const deps = &metadata.external_dependencies.object;
+            for (deps.keys(), deps.values()) |key, value| {
+                const dep: *const std.json.ObjectMap = &value.object;
+
+                //
+
+                try stdout.print("            .{} = .{{\n", .{fmtId(key)});
+
+                try stdout.print("                .url = \"{}\",\n", .{fmtEscapes(dep.get("url").?.string)});
+                try stdout.print("                .hash = \"{}\",\n", .{fmtEscapes(dep.get("hash").?.string)});
+                try stdout.writeAll("        },\n");
+            }
+        }
+
+        switch (metadata.package_type) {
+            .core => {
+                // core packages are always "standalone" in the microzig environment and provide the root
+                // of the build
+            },
+
+            .build => {
+                //
+            },
+
+            .@"board-support" => {
+                // bsp packages implicitly depend on the "microzig" package:
+
+                try stdout.writeAll("            .microzig = .{\n");
+                try stdout.print("                .url = \"{}/{}\",\n", .{ fmtEscapes(deployment_base_url), fmtEscapes(rel_pkg_path) });
+                try stdout.print("                .hash = \"{}\",\n", .{fmtEscapes("???")});
+                try stdout.writeAll("        },\n");
+            },
+        }
+
+        try stdout.writeAll("    },\n");
+        try stdout.writeAll("}\n");
+    }
+
+    try buffered_stdout.flush();
+}

From 8d9c165a1d863f0c3e40a83cd7d472ab59320176 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Tue, 9 Jan 2024 16:01:21 +0100
Subject: [PATCH 256/286] Fixes CI

---
 .github/workflows/build.yml | 6 +++++-
 tools/bundle.py             | 2 +-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index e697a7464..350c2ae08 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -27,9 +27,13 @@ jobs:
         with:
           version: 0.11.0
 
+      - name: Install PIP packages
+        run: |
+          pip install dataclasses_json==0.6.3 marshmallow typing-inspect semver pathspec
+
       - name: Generate and validate packages
         run: |
-          ./tools/bundle.sh
+          ./tools/bundle.py
 
       - name: Upload artifacts
         uses: actions/upload-artifact@v4
diff --git a/tools/bundle.py b/tools/bundle.py
index 1d6ab9ea2..cd3298853 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -248,7 +248,7 @@ def main():
     assert cache_root.is_dir()
 
     cache_dir = cache_root / "microzig"
-    cache_root.mkdir(exist_ok=True)
+    cache_dir.mkdir(exist_ok=True)
 
     # Prepare `.gitignore` pattern matcher:
     global_ignore_spec = pathspec.PathSpec.from_lines(

From c65088cca6966ec5688185e9d040075e456433f5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Tue, 9 Jan 2024 17:28:08 +0100
Subject: [PATCH 257/286] Further improves deployment information, makes
 package info really useful

---
 build/microzig-package.json     |   2 +-
 core/microzig-package.json      |   2 +-
 tools/bundle.py                 | 102 ++++++++++++++++++++------------
 tools/create-pkg-descriptor.zig |  82 +++++++++++++------------
 4 files changed, 110 insertions(+), 78 deletions(-)

diff --git a/build/microzig-package.json b/build/microzig-package.json
index bdabd11c0..6ddeab066 100644
--- a/build/microzig-package.json
+++ b/build/microzig-package.json
@@ -1,5 +1,5 @@
 {
-    "package_name": "build",
+    "package_name": "microzig-build",
     "package_type": "build",
     "external_dependencies": {
         "uf2": {
diff --git a/core/microzig-package.json b/core/microzig-package.json
index 6d49cb335..b8cc13610 100644
--- a/core/microzig-package.json
+++ b/core/microzig-package.json
@@ -1,5 +1,5 @@
 {
-    "package_name": "core",
+    "package_name": "microzig-core",
     "package_type": "core",
     "external_dependencies": {
         "umm-zig": {
diff --git a/tools/bundle.py b/tools/bundle.py
index cd3298853..76c85c1ee 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -14,7 +14,7 @@
 import pathspec
 import stat 
 from marshmallow import fields as mm_fields
-from typing import Optional
+from typing import Optional, Any
 
 
 VERBOSE = False 
@@ -29,6 +29,7 @@
     # "dirname",
     # "realpath",
 ]
+DEPLOYMENT_BASE="https://download.microzig.tech/packages"
 
 REPO_ROOT = Path(__file__).parent.parent
 assert REPO_ROOT.is_dir()
@@ -44,7 +45,7 @@ class PackageType(StrEnum):
 @dataclass_json
 @dataclass
 class Archive:
-    size: int
+    size: str
     sha256sum: str
 
 @dataclass_json
@@ -64,7 +65,7 @@ class ExternalDependency:
 class Timestamp:
     unix: str
     iso: str 
-
+    
 @dataclass_json
 @dataclass
 class PackageConfiguration:
@@ -80,9 +81,30 @@ class PackageConfiguration:
     created: Optional[Timestamp] = field(default = None)
     package: Optional[Package]  = field(default= None)
 
+    download_url: Optional[str] = field(default=None)
+
+    microzig: Optional[Any] = field(default=None)
+
     # inner fields:
     # package_dir: Path = field(default=None, metadata = dcj_config(exclude=JsonExclude.ALWAYS))
 
+@dataclass_json
+@dataclass
+class PackageDesc:
+    name: str
+    type: PackageType
+    version: str # semver
+    metadata: str # url to json
+    download: str # url to tar.gz
+
+@dataclass_json
+@dataclass
+class PackageIndex:
+    
+    last_update: Timestamp
+    packages: list[PackageDesc]
+
+PackageIndexSchema = PackageIndex.schema()
 PackageSchema = Package.schema()
 PackageConfigurationSchema = PackageConfiguration.schema()
 
@@ -261,8 +283,6 @@ def main():
         pathspec.patterns.GitWildMatchPattern("microzig-package.json")
     )
 
-    print(global_ignore_spec)      
-
     # Fetch and find all packages:
 
     print("validating packages...")
@@ -282,15 +302,28 @@ def main():
         pkg.created = batch_timestamp
         pkg.package_dir = pkg_dir
 
+
         if pkg.package_type == PackageType.core:
-            pass
+            pkg.out_rel_dir = PurePosixPath(".")
+            pkg.out_basename = pkg.package_name
+
         elif pkg.package_type == PackageType.build:
-            pass        
+            pkg.out_rel_dir = PurePosixPath(".")
+            pkg.out_basename = pkg.package_name
+
         elif pkg.package_type == PackageType.board_support:
-            pkg.inner_dependencies.add("core") # BSPs implicitly depend on the core "microzig" package
+            parsed_pkg_name = PurePosixPath(pkg.package_name)
+
+            pkg.out_rel_dir = "board-support" / parsed_pkg_name.parent
+            pkg.out_basename = parsed_pkg_name.name
+
+            pkg.inner_dependencies.add("microzig-core") # BSPs implicitly depend on the core "microzig" package
         else:
             assert False 
 
+        download_path = pkg.out_rel_dir / ALL_FILES_DIR / f"{pkg.out_basename}-{version}.tar.gz"
+        pkg.download_url = f"{DEPLOYMENT_BASE}/{download_path}"
+
         buildzig_path = pkg_dir / "build.zig"
         buildzon_path = pkg_dir / "build.zig.zon"
         
@@ -313,11 +346,7 @@ def main():
             print(f"The package at {meta_path} has a duplicate package name {pkg.package_name}")
             print("Please remove that file and merge it into microzig-package.json!")
             validation_ok = False
-
-        # print("%d\t%s\n", "${pkg_prio}" "${reldir}" >> "${cache_dir}/packages.raw")
-
-    # cat "${cache_dir}/packages.raw" | sort | cut -f 2 > "${cache_dir}/packages.list"
-
+        
     if not validation_ok:
         print("Not all packages are valid. Fix the packages and try again!" )
         exit(1)
@@ -332,8 +361,10 @@ def main():
 
     # bundle everything:
 
-    
-
+    index = PackageIndex(
+        last_update = batch_timestamp,
+        packages = [],
+    )
 
     print("creating packages...")
     for pkg in evaluation_ordered_packages:
@@ -347,24 +378,10 @@ def main():
         meta_path = pkg_dir / "microzig-package.json"
         pkg_zon_file = pkg_cache_dir / "build.zig.zon" 
 
-        out_rel_dir: PurePosixPath 
-        out_basename: str 
-        extra_json: dict = {}
+        out_rel_dir: PurePosixPath = pkg.out_rel_dir
+        out_basename: str = pkg.out_basename
         
-        if pkg.package_type == PackageType.build:
-            out_rel_dir = PurePosixPath(".")
-            out_basename = pkg.package_name
-
-        elif pkg.package_type == PackageType.core:
-            out_rel_dir = PurePosixPath(".")
-            out_basename = pkg.package_name
-
-        elif pkg.package_type == PackageType.board_support:
-            parsed_pkg_name = PurePosixPath(pkg.package_name)
-
-            out_rel_dir = "board-support" / parsed_pkg_name.parent
-            out_basename = parsed_pkg_name.name
-
+        if pkg.package_type == PackageType.board_support:
             bsp_info = slurp(
                 "zig", "build-exe",
                     f"{REPO_ROOT}/tools/extract-bsp-info.zig" ,
@@ -379,14 +396,11 @@ def main():
 
             extra_json_str=slurp(pkg_cache_dir/"extract-bsp-info")
 
-            extra_json = json.loads(extra_json_str)
+            pkg.microzig = json.loads(extra_json_str)
 
-        else:
-            assert False 
 
         assert out_rel_dir is not None
         assert out_basename is not None
-        assert isinstance(extra_json, dict)
 
         # File names:
 
@@ -432,8 +446,9 @@ def main():
         execute("tar", "-cf", out_file_tar, "--hard-dereference", *package_files, cwd=pkg_dir)
 
         zon_data = slurp(
-            tools["create_pkg_descriptor"], version, out_rel_dir, 
-            input=PackageConfigurationSchema.dumps(pkg).encode(),
+            tools["create_pkg_descriptor"],
+            pkg.package_name, 
+            input=PackageConfigurationSchema.dumps(evaluation_ordered_packages, many=True ).encode(),
         )
 
         with pkg_zon_file.open("wb") as f:
@@ -465,6 +480,17 @@ def main():
         out_symlink_pkg.symlink_to(out_file_targz.relative_to(out_symlink_pkg.parent))
         out_symlink_meta.symlink_to(out_file_meta.relative_to(out_symlink_meta.parent))
 
+        index.packages.append(PackageDesc(
+            name = pkg.package_name,
+            type = pkg.package_type,
+            version = version,
+            metadata = pkg.download_url.removesuffix(".tar.gz") + ".json",
+            download = pkg.download_url,
+        ))
+
+    with (deploy_target / "index.json").open("w") as f:
+        f.write(PackageIndexSchema.dumps(index))
+
     # TODO: Verify that each package can be unpacked and built
 
 
diff --git a/tools/create-pkg-descriptor.zig b/tools/create-pkg-descriptor.zig
index e6226f6b8..26862f3ad 100644
--- a/tools/create-pkg-descriptor.zig
+++ b/tools/create-pkg-descriptor.zig
@@ -36,9 +36,27 @@ const MetaData = struct {
     archive: ?Archive = null,
     package: ?Package = null,
     created: ?Timestamp = null,
+
+    download_url: ?[]const u8 = null,
+
+    microzig: std.json.Value = .null,
 };
 
-// create-pkg-descriptor 
+fn findPackage(packages: []const MetaData, name: []const u8) ?*const MetaData {
+    return for (packages) |*pkg| {
+        if (std.mem.eql(u8, pkg.package_name, name))
+            return pkg;
+    } else null;
+}
+
+fn renderDep(writer: anytype, name: []const u8, url: []const u8, hash: []const u8) !void {
+    try writer.print("            .{} = .{{\n", .{fmtId(name)});
+    try writer.print("                .url = \"{}\",\n", .{fmtEscapes(url)});
+    try writer.print("                .hash = \"{}\",\n", .{fmtEscapes(hash)});
+    try writer.writeAll("        },\n");
+}
+
+// create-pkg-descriptor 
 pub fn main() !void {
     var gpa = std.heap.GeneralPurposeAllocator(.{}){};
     defer _ = gpa.deinit();
@@ -52,66 +70,54 @@ pub fn main() !void {
 
     const argv = try std.process.argsAlloc(arena);
 
-    if (argv.len != 3) {
+    if (argv.len != 2) {
         @panic("version and/or relpath missing!");
     }
 
-    // System configuration:
-    const deployment_base_url = "https://download.microzig.tech/packages"; // TODO: Make those configurable
-
     // build inputs:
-    const version_string = argv[1];
-    const rel_pkg_path = argv[2];
-
-    const version = try std.SemanticVersion.parse(version_string);
+    const pkg_name = argv[1];
 
     const json_input = try std.io.getStdIn().readToEndAlloc(arena, 1 << 20);
 
     errdefer std.log.err("failed to parse json from {s}", .{json_input});
 
-    const metadata = try std.json.parseFromSliceLeaky(MetaData, arena, json_input, .{});
+    const all_packages = try std.json.parseFromSliceLeaky([]MetaData, arena, json_input, .{});
+
+    const package = findPackage(all_packages, pkg_name).?;
+
+    const version = try std.SemanticVersion.parse(package.version);
 
     var buffered_stdout = std.io.bufferedWriter(std.io.getStdOut().writer());
 
     const stdout = buffered_stdout.writer();
     {
         try stdout.writeAll(".{\n");
-        try stdout.print("    .name = \"{}\",\n", .{fmtEscapes(metadata.package_name)});
+        try stdout.print("    .name = \"{}\",\n", .{fmtEscapes(package.package_name)});
         try stdout.print("    .version = \"{}\",\n", .{version});
         try stdout.writeAll("    .dependencies = .{\n");
-        if (metadata.external_dependencies != .null) {
-            const deps = &metadata.external_dependencies.object;
+        if (package.external_dependencies != .null) {
+            const deps = &package.external_dependencies.object;
             for (deps.keys(), deps.values()) |key, value| {
                 const dep: *const std.json.ObjectMap = &value.object;
-
-                //
-
-                try stdout.print("            .{} = .{{\n", .{fmtId(key)});
-
-                try stdout.print("                .url = \"{}\",\n", .{fmtEscapes(dep.get("url").?.string)});
-                try stdout.print("                .hash = \"{}\",\n", .{fmtEscapes(dep.get("hash").?.string)});
-                try stdout.writeAll("        },\n");
+                try renderDep(
+                    stdout,
+                    key,
+                    dep.get("url").?.string,
+                    dep.get("hash").?.string,
+                );
             }
         }
 
-        switch (metadata.package_type) {
-            .core => {
-                // core packages are always "standalone" in the microzig environment and provide the root
-                // of the build
-            },
-
-            .build => {
-                //
-            },
-
-            .@"board-support" => {
-                // bsp packages implicitly depend on the "microzig" package:
+        // Add all other dependencies:
+        for (package.inner_dependencies) |dep_name| {
+            const dep = findPackage(all_packages, dep_name).?;
 
-                try stdout.writeAll("            .microzig = .{\n");
-                try stdout.print("                .url = \"{}/{}\",\n", .{ fmtEscapes(deployment_base_url), fmtEscapes(rel_pkg_path) });
-                try stdout.print("                .hash = \"{}\",\n", .{fmtEscapes("???")});
-                try stdout.writeAll("        },\n");
-            },
+            try renderDep(
+                stdout,
+                "microzig",
+                dep.download_url.?,
+                dep.package.?.hash,
+            );
         }
 
         try stdout.writeAll("    },\n");

From e5b00e1d938672f0e53c160a193dcecdec35cbad Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Fri, 12 Jan 2024 10:10:19 +0100
Subject: [PATCH 258/286] More docs on the tooling, fixes bug in memory
 computation.

---
 .../espressif-esp/extract-bsp-info.o          | Bin 1969032 -> 0 bytes
 tools/archive-info.zig                        |   5 ++-
 tools/bundle.py                               |  11 ++---
 tools/create-package.sh                       |  42 ------------------
 tools/create-pkg-descriptor.zig               |  15 ++++++-
 tools/demo-server.py                          |   7 ++-
 tools/extract-bsp-info.zig                    |   4 +-
 tools/lib/tar.zig                             |   4 ++
 8 files changed, 33 insertions(+), 55 deletions(-)
 delete mode 100644 board-support/espressif-esp/extract-bsp-info.o
 delete mode 100755 tools/create-package.sh

diff --git a/board-support/espressif-esp/extract-bsp-info.o b/board-support/espressif-esp/extract-bsp-info.o
deleted file mode 100644
index 85f74f4ac9358c4323ab0ae7bd9e83351e07c5ed..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/tools/archive-info.zig b/tools/archive-info.zig
index 049d98150..33f8496d5 100644
--- a/tools/archive-info.zig
+++ b/tools/archive-info.zig
@@ -1,8 +1,9 @@
 //!
-//! Computes some meta information for packages and prints them as JSON.
+//! Computes the hash and some meta information for package tar balls and prints them as JSON.
+//!
 //! Usage: archive-info 
 //!
-//! Is used in `/tools/bundle.sh` to extend the `microzig-package.json` file.
+//! Is used in `/tools/bundle.py` to extend the `microzig-package.json` file.
 //!
 
 const std = @import("std");
diff --git a/tools/bundle.py b/tools/bundle.py
index 76c85c1ee..47761c10c 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -1,8 +1,11 @@
 #!/usr/bin/env python3
 #
 # Prepares a full deployment of MicroZig.
-# Creates all packages into /microzig-deploy with the final folder structure.
+# Creates all packages into ${repo}/microzig-deploy with the final folder structure.
 #
+# Just invoke this script to create a deployment structure for MicroZig.
+#
+
 
 import sys, os, subprocess,datetime, re, shutil, json, hashlib
 from pathlib import Path, PurePosixPath
@@ -22,12 +25,6 @@
 REQUIRED_TOOLS = [
     "zig",
     "git",
-    # "date",
-    # "find",
-    # "jq",
-    # "mkdir",
-    # "dirname",
-    # "realpath",
 ]
 DEPLOYMENT_BASE="https://download.microzig.tech/packages"
 
diff --git a/tools/create-package.sh b/tools/create-package.sh
deleted file mode 100755
index 1eaf96b80..000000000
--- a/tools/create-package.sh
+++ /dev/null
@@ -1,42 +0,0 @@
-#!/bin/sh
-
-set -eu
-
-# test for all required tools:
-which tar gzip jq basename dirname realpath > /dev/null
-
-if [ "$#" -ne 2 ]; then 
-    echo "usage: $(basename "$0")  " >&2
-    exit 1
-fi
-
-input_folder="$(realpath "$1")"
-output_file="$(realpath "$2")"
-
-if [ ! -d "${input_folder}" ]; then 
-    echo "${input_folder} does not exist or is not a directory!" >&2
-    exit 1
-fi
-
-
-if [ ! -f "${input_folder}/microzig-package.json" ]; then 
-    echo "The input folder does not contain a microzig-package.json!" >&2
-    exit 1
-fi 
-
-if [ -e "${output_file}" ]; then 
-    echo "${output_file} already exists, please delete first!" >&2
-    exit 1
-fi 
-
-if [ ! -d "$(dirname "${output_file}")" ]; then 
-    echo "${output_file} does not point to a path where a file can be created!" >&2
-    exit 1
-fi 
-
-(
-    cd "${input_folder}"
-    # explanation on ls-files: 
-    # https://stackoverflow.com/a/53083343
-    tar -caf "${output_file}" $(git ls-files -- . ':!:microzig-package.json')
-)
diff --git a/tools/create-pkg-descriptor.zig b/tools/create-pkg-descriptor.zig
index 26862f3ad..d41abeb61 100644
--- a/tools/create-pkg-descriptor.zig
+++ b/tools/create-pkg-descriptor.zig
@@ -1,3 +1,17 @@
+//!
+//! Creates a `build.zig.zon` based on a JSON array of `microzig-package.json` files.
+//!
+//! Usage: create-pkg-descriptor  < all-packages.json > build.zig.zon
+//!
+//! Searches for a package called `` in the `microzig-package.json` descriptors
+//! passed in on stdin.
+//!
+//! Those package descriptors must have `version`, `package_name`, `external_dependencies` and `inner_dependencies` set,
+//! The inner dependencies must also have `download_url` and `package.hash` available.
+//!
+//! This program is intended for the use from the `tools/bundly.py` bundler. See this script for more usage information.
+//!
+
 const std = @import("std");
 const eggzon = @import("eggzon");
 
@@ -56,7 +70,6 @@ fn renderDep(writer: anytype, name: []const u8, url: []const u8, hash: []const u
     try writer.writeAll("        },\n");
 }
 
-// create-pkg-descriptor 
 pub fn main() !void {
     var gpa = std.heap.GeneralPurposeAllocator(.{}){};
     defer _ = gpa.deinit();
diff --git a/tools/demo-server.py b/tools/demo-server.py
index 302edf51a..68545df8d 100755
--- a/tools/demo-server.py
+++ b/tools/demo-server.py
@@ -1,5 +1,10 @@
 #!/usr/bin/env python3
-
+#
+# A small web server that can serve the `${root}/microzig-deploy` folder for testing the package infrastructure.
+#
+# Basically `python -m http.server 8080`, but also hides folders starting with `.data` so the "internals" aren't shown
+# to the user in the file listing.
+#
 
 from pathlib import Path
 from http.server import HTTPServer,SimpleHTTPRequestHandler
diff --git a/tools/extract-bsp-info.zig b/tools/extract-bsp-info.zig
index 565c3d0cb..9d83f7db5 100644
--- a/tools/extract-bsp-info.zig
+++ b/tools/extract-bsp-info.zig
@@ -1,5 +1,5 @@
 //!
-//! A tool that extracs which chips and boards are avaiilable from a board support package
+//! A tool that extracs which chips and boards are available from a board support package
 //! and validates that the declarations conform
 //!
 
@@ -62,7 +62,7 @@ fn renderMicroZigTarget(stream: anytype, key: []const u8, target: microzig.Targe
     for (target.chip.memory_regions) |reg| {
         switch (reg.kind) {
             .flash => jtarget.memory.flash += reg.length,
-            .ram => jtarget.memory.flash += reg.length,
+            .ram => jtarget.memory.ram += reg.length,
             else => {},
         }
     }
diff --git a/tools/lib/tar.zig b/tools/lib/tar.zig
index 43c1b8d08..c93684d12 100644
--- a/tools/lib/tar.zig
+++ b/tools/lib/tar.zig
@@ -1,3 +1,7 @@
+//!
+//! Extracted from https://github.com/mattnite/ezpkg.
+//!
+
 const std = @import("std");
 const builtin = @import("builtin");
 

From 91fcc6b4701c7eb6dd0256f517706b2b036049cc Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Fri, 12 Jan 2024 11:02:48 +0100
Subject: [PATCH 259/286] Deduplicates info in github ci script.

---
 .github/workflows/build.yml | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 350c2ae08..5395153b1 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -1,5 +1,9 @@
 name: Continuous Integration
 
+env:
+  # Specify the current Zig version MicroZig uses:
+  ZIG_VERSION: 0.11.0
+
 on:
   push:
     branches: [main]
@@ -17,15 +21,15 @@ jobs:
 
       - name: Fetch more data from git
         run: |
-          # fetch everything back till the 0.11.0 tag.
+          # fetch everything back till the $(ZIG_VERSION) tag.
           # https://stackoverflow.com/a/58082274
-          git fetch --shallow-exclude 0.11.0
+          git fetch --shallow-exclude ${{ env.ZIG_VERSION }}
           git fetch --deepen=2
 
       - name: Setup Zig
         uses: goto-bus-stop/setup-zig@v2
         with:
-          version: 0.11.0
+          version: ${{ env.ZIG_VERSION }}
 
       - name: Install PIP packages
         run: |

From cadd5d1b0f112357a504b6620ad799a05d3b3323 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Thu, 18 Jan 2024 12:13:09 +0100
Subject: [PATCH 260/286] Makes examples/next-gen kinda build with experimental
 setup. Packages are now correct and microzig-build can determine all
 available targets and BSPs.

---
 README.md                                  |    2 +-
 board-support/nordic-nrf5x/build.zig       |    7 +-
 board-support/nxp-lpc/build.zig            |    5 +-
 board-support/raspberrypi-rp2040/build.zig |   14 +-
 board-support/stmicro-stm32/build.zig      |    2 +-
 build.zig                                  |    3 +
 build.zig.zon                              |    8 +
 build/build.zig                            |  558 ++++---
 core/build.zig                             | 1696 ++++++++++----------
 examples/build.zig                         |   28 +
 examples/modular/README.md                 |    5 -
 examples/modular/build.zig                 |   33 -
 examples/modular/build.zig.zon             |   14 -
 examples/modular/src/blinky.zig            |   56 -
 examples/next-gen/build.zig                |   32 +
 examples/next-gen/build.zig.zon            |   22 +
 examples/next-gen/src/empty.zig            |    8 +
 tools/archive-info.zig                     |   65 +-
 tools/bundle.py                            |   34 +-
 tools/create-pkg-descriptor.zig            |    2 +-
 tools/extract-bsp-info.zig                 |    2 +-
 tools/patch-build-zon.py                   |   74 +
 22 files changed, 1430 insertions(+), 1240 deletions(-)
 create mode 100644 examples/build.zig
 delete mode 100644 examples/modular/README.md
 delete mode 100644 examples/modular/build.zig
 delete mode 100644 examples/modular/build.zig.zon
 delete mode 100644 examples/modular/src/blinky.zig
 create mode 100644 examples/next-gen/build.zig
 create mode 100644 examples/next-gen/build.zig.zon
 create mode 100644 examples/next-gen/src/empty.zig
 create mode 100755 tools/patch-build-zon.py

diff --git a/README.md b/README.md
index db1040d1d..ac6321216 100644
--- a/README.md
+++ b/README.md
@@ -27,4 +27,4 @@ Consider the version `0.11.0-abcdef-123` means that this MicroZig version has a
 - validate that the table on https://github.com/ZigEmbeddedGroup is correct (in CI)
 - make system build again properly
 - start porting everything to 0.12/unstable
-
+- Try to get some autodocs to build.
diff --git a/board-support/nordic-nrf5x/build.zig b/board-support/nordic-nrf5x/build.zig
index 1690e0c7d..9bc2b7882 100644
--- a/board-support/nordic-nrf5x/build.zig
+++ b/board-support/nordic-nrf5x/build.zig
@@ -1,4 +1,5 @@
 const std = @import("std");
+const MicroZig = @import("microzig-build");
 
 fn path(comptime suffix: []const u8) std.Build.LazyPath {
     return .{
@@ -7,7 +8,7 @@ fn path(comptime suffix: []const u8) std.Build.LazyPath {
 }
 
 pub const chips = struct {
-    pub const nrf52840 = .{
+    pub const nrf52840 = MicroZig.Target{
         .preferred_format = .elf,
         .chip = .{
             .name = "nrf52840",
@@ -29,7 +30,7 @@ pub const chips = struct {
         },
     };
 
-    pub const nrf52832 = .{
+    pub const nrf52832 = MicroZig.Target{
         .preferred_format = .elf,
         .chip = .{
             .name = "nrf52",
@@ -48,7 +49,7 @@ pub const chips = struct {
 
 pub const boards = struct {
     pub const nordic = struct {
-        pub const nRF52840_Dongle = .{
+        pub const nRF52840_Dongle = MicroZig.Target{
             .preferred_format = .elf,
             .chip = chips.nrf52840.chip,
             .board = .{
diff --git a/board-support/nxp-lpc/build.zig b/board-support/nxp-lpc/build.zig
index 639a034ce..5f75d436a 100644
--- a/board-support/nxp-lpc/build.zig
+++ b/board-support/nxp-lpc/build.zig
@@ -1,4 +1,5 @@
 const std = @import("std");
+const MicroZig = @import("microzig-build");
 
 fn path(comptime suffix: []const u8) std.Build.LazyPath {
     return .{
@@ -11,7 +12,7 @@ const hal = .{
 };
 
 pub const chips = struct {
-    pub const lpc176x5x = .{
+    pub const lpc176x5x = MicroZig.Target{
         .preferred_format = .elf,
         .chip = .{
             // TODO: Separate over those chips, this is not generic!
@@ -33,7 +34,7 @@ pub const chips = struct {
 
 pub const boards = struct {
     pub const mbed = struct {
-        pub const lpc1768 = .{
+        pub const lpc1768 = MicroZig.Target{
             .preferred_format = .hex,
             .chip = chips.lpc176x5x.chip,
             .hal = hal,
diff --git a/board-support/raspberrypi-rp2040/build.zig b/board-support/raspberrypi-rp2040/build.zig
index eae5bc9f1..73453f343 100644
--- a/board-support/raspberrypi-rp2040/build.zig
+++ b/board-support/raspberrypi-rp2040/build.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("microzig");
+const microzig = @import("microzig-build");
 
 fn root() []const u8 {
     return comptime (std.fs.path.dirname(@src().file) orelse ".");
@@ -17,7 +17,7 @@ pub fn build(b: *std.Build) !void {
 
 pub const chips = struct {
     // Note: This chip has no flash support defined and requires additional configuration!
-    pub const rp2040 = .{
+    pub const rp2040 = microzig.Target{
         .preferred_format = .{ .uf2 = .RP2040 },
         .chip = chip,
         .hal = hal,
@@ -28,7 +28,7 @@ pub const chips = struct {
 
 pub const boards = struct {
     pub const raspberry_pi = struct {
-        pub const pico = .{
+        pub const pico = microzig.Target{
             .preferred_format = .{ .uf2 = .RP2040 },
             .chip = chip,
             .hal = hal,
@@ -43,7 +43,7 @@ pub const boards = struct {
     };
 
     pub const waveshare = struct {
-        pub const rp2040_plus_4m = .{
+        pub const rp2040_plus_4m = microzig.Target{
             .preferred_format = .{ .uf2 = .RP2040 },
             .chip = chip,
             .hal = hal,
@@ -56,7 +56,7 @@ pub const boards = struct {
             .configure = rp2040_configure(.w25q080),
         };
 
-        pub const rp2040_plus_16m = .{
+        pub const rp2040_plus_16m = microzig.Target{
             .preferred_format = .{ .uf2 = .RP2040 },
             .chip = chip,
             .hal = hal,
@@ -69,7 +69,7 @@ pub const boards = struct {
             .configure = rp2040_configure(.w25q080),
         };
 
-        pub const rp2040_eth = .{
+        pub const rp2040_eth = microzig.Target{
             .preferred_format = .{ .uf2 = .RP2040 },
             .chip = chip,
             .hal = hal,
@@ -82,7 +82,7 @@ pub const boards = struct {
             .configure = rp2040_configure(.w25q080),
         };
 
-        pub const rp2040_matrix = .{
+        pub const rp2040_matrix = microzig.Target{
             .preferred_format = .{ .uf2 = .RP2040 },
             .chip = chip,
             .hal = hal,
diff --git a/board-support/stmicro-stm32/build.zig b/board-support/stmicro-stm32/build.zig
index dcbf169ab..4e0e0d541 100644
--- a/board-support/stmicro-stm32/build.zig
+++ b/board-support/stmicro-stm32/build.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const microzig = @import("microzig");
+const microzig = @import("microzig-build");
 
 fn root() []const u8 {
     return comptime (std.fs.path.dirname(@src().file) orelse ".");
diff --git a/build.zig b/build.zig
index d582de9a7..2f711927c 100644
--- a/build.zig
+++ b/build.zig
@@ -1,7 +1,10 @@
 const std = @import("std");
+// const examples = @import("examples/build.zig");
 
 pub fn build(b: *std.Build) void {
     buildTools(b);
+
+    // examples.build(b);
 }
 
 fn buildTools(b: *std.Build) void {
diff --git a/build.zig.zon b/build.zig.zon
index a4e965265..e0c48b3da 100644
--- a/build.zig.zon
+++ b/build.zig.zon
@@ -6,5 +6,13 @@
             .url = "https://github.com/ziglibs/eggzon/archive/refs/heads/master.tar.gz",
             .hash = "1220cd5cec7e9d4911074a9b2dec2dabef76e1adf94d041bca068163ce7666c4be47",
         },
+        .uf2 = .{
+            .url = "https://github.com/ZigEmbeddedGroup/uf2/archive/8037b439ccbac862471392b25e94a8995d784e2c.tar.gz",
+            .hash = "1220cc66563fc1ecefca7990968441dc9d4db717884ffa9a2de657f60ed4bb74a70a",
+        },
+        .regz = .{
+            .url = "https://github.com/ZigEmbeddedGroup/regz/archive/d66ffd56f51fc46c071412141b5d0c74dc83c310.tar.gz",
+            .hash = "122002c5f2e31c11373ede6e8a8dd9a61aabd60d38df667ec33b5f994d1f0b503823",
+        },
     },
 }
diff --git a/build/build.zig b/build/build.zig
index 748833fd4..2c6df508b 100644
--- a/build/build.zig
+++ b/build/build.zig
@@ -5,6 +5,342 @@
 const std = @import("std");
 const uf2 = @import("uf2");
 
+////////////////////////////////////////
+//      MicroZig Gen 3 Interface      //
+////////////////////////////////////////
+
+pub const EnvironmentInfo = struct {
+    /// include package names of your board support packages here:
+    board_support: []const []const u8,
+
+    /// package name of the build package (optional)
+    self: []const u8 = "microzig",
+
+    /// package name of the core package (optional)
+    core: []const u8 = "microzig-core",
+};
+
+pub fn createBuildEnvironment(b: *std.Build, comptime info: EnvironmentInfo) *BuildEnvironment {
+    const be = b.allocator.create(BuildEnvironment) catch @panic("out of memory");
+    be.* = BuildEnvironment{
+        .host_build = b,
+        .self = undefined,
+        .microzig_core = undefined,
+        .board_support_packages = b.allocator.alloc(BoardSupportPackage, info.board_support.len) catch @panic("out of memory"),
+        .targets = .{},
+    };
+
+    be.self = b.dependency(info.self, .{});
+    be.microzig_core = b.dependency(info.core, .{});
+
+    for (be.board_support_packages, info.board_support) |*out, in| {
+        out.* = BoardSupportPackage{
+            .name = in,
+            .dep = b.dependency(in, .{}),
+        };
+    }
+
+    // Fetch and collect all supported targets:
+    inline for (info.board_support) |bsp_name| {
+        // Keep in sync with the logic from Build.zig:dependency
+        const build_runner = @import("root");
+        const deps = build_runner.dependencies;
+
+        const bsp_root = @field(deps.imports, bsp_name);
+
+        if (@hasDecl(bsp_root, "chips")) {
+            fetch_microzig_targets("chip:", bsp_root.chips, bsp_name, be);
+        }
+
+        if (@hasDecl(bsp_root, "boards")) {
+            fetch_microzig_targets("board:", bsp_root.boards, bsp_name, be);
+        }
+    }
+
+    return be;
+}
+
+fn fetch_microzig_targets(comptime prefix: []const u8, comptime namespace: type, comptime bsp_name: []const u8, be: *BuildEnvironment) void {
+    inline for (@typeInfo(namespace).Struct.decls) |decl_info| {
+        const decl = @field(namespace, decl_info.name);
+        const T = @TypeOf(decl);
+
+        const name = comptime prefix ++ decl_info.name; // board:vendor/name
+        const full_name = comptime name ++ "#" ++ bsp_name; // board:vendor/name#bsp-package-name
+
+        if (T == Target) {
+            const target: Target = decl;
+
+            be.targets.put(be.host_build.allocator, name, target) catch @panic("out of memory");
+            be.targets.put(be.host_build.allocator, full_name, target) catch @panic("out of memory");
+        } else {
+            const ok = blk: {
+                if (comptime T != type) {
+                    // @compileLog(full_name, "check 1:", T, decl);
+                    break :blk false;
+                }
+
+                const ti = @typeInfo(decl);
+                if (comptime ti != .Struct) {
+                    // @compileLog(full_name, "check 2:", ti);
+                    break :blk false;
+                }
+
+                if (comptime ti.Struct.fields.len > 0) {
+                    // @compileLog(full_name, "check 3:", ti.Struct);
+                    // @compileLog(full_name, "check 3:", ti.Struct.fields);
+                    break :blk false;
+                }
+
+                fetch_microzig_targets(
+                    comptime name ++ "/",
+                    decl,
+                    bsp_name,
+                    be,
+                );
+
+                break :blk true;
+            };
+            if (!ok) {
+                std.debug.print("Bad BSP: {s} is neither namespace nor a microzig.Target\n", .{ prefix, full_name });
+            }
+        }
+    }
+}
+
+pub const BoardSupportPackage = struct {
+    dep: *std.Build.Dependency,
+    name: []const u8,
+};
+
+pub const BuildEnvironment = struct {
+    host_build: *std.Build,
+    self: *std.Build.Dependency,
+
+    microzig_core: *std.Build.Dependency,
+
+    board_support_packages: []BoardSupportPackage,
+
+    targets: std.StringArrayHashMapUnmanaged(Target),
+
+    pub fn findTarget(env: *const BuildEnvironment, name: []const u8) ?*const Target {
+        return env.targets.getPtr(name);
+    }
+
+    /// Declares a new MicroZig firmware file.
+    pub fn addFirmware(
+        /// The MicroZig instance that should be used to create the firmware.
+        env: *BuildEnvironment,
+        /// The instance of the `build.zig` that is calling this function.
+        host_build: *std.Build,
+        /// Options that define how the firmware is built.
+        options: FirmwareOptions,
+    ) *Firmware {
+        const micro_build = env.self.builder;
+
+        const chip = &options.target.chip;
+        const cpu = chip.cpu.getDescriptor();
+        const maybe_hal = options.hal orelse options.target.hal;
+        const maybe_board = options.board orelse options.target.board;
+
+        const linker_script = options.linker_script orelse options.target.linker_script;
+
+        // TODO: let the user override which ram section to use the stack on,
+        // for now just using the first ram section in the memory region list
+        const first_ram = blk: {
+            for (chip.memory_regions) |region| {
+                if (region.kind == .ram)
+                    break :blk region;
+            } else @panic("no ram memory region found for setting the end-of-stack address");
+        };
+
+        // On demand, generate chip definitions via regz:
+        const chip_source = switch (chip.register_definition) {
+            .json, .atdf, .svd => |file| blk: {
+                const regz_exe = env.dependency("regz", .{ .optimize = .ReleaseSafe }).artifact("regz");
+
+                const regz_gen = host_build.addRunArtifact(regz_exe);
+
+                regz_gen.addArg("--schema"); // Explicitly set schema type, one of: svd, atdf, json
+                regz_gen.addArg(@tagName(chip.register_definition));
+
+                regz_gen.addArg("--output_path"); // Write to a file
+                const zig_file = regz_gen.addOutputFileArg("chip.zig");
+
+                regz_gen.addFileArg(file);
+
+                break :blk zig_file;
+            },
+
+            .zig => |src| src,
+        };
+
+        const config = host_build.addOptions();
+        config.addOption(bool, "has_hal", (maybe_hal != null));
+        config.addOption(bool, "has_board", (maybe_board != null));
+
+        config.addOption(?[]const u8, "board_name", if (maybe_board) |brd| brd.name else null);
+
+        config.addOption([]const u8, "chip_name", chip.name);
+        config.addOption([]const u8, "cpu_name", chip.name);
+        config.addOption(usize, "end_of_stack", first_ram.offset + first_ram.length);
+
+        const fw: *Firmware = host_build.allocator.create(Firmware) catch @panic("out of memory");
+        fw.* = Firmware{
+            .env = env,
+            .host_build = host_build,
+            .artifact = host_build.addExecutable(.{
+                .name = options.name,
+                .optimize = options.optimize,
+                .target = cpu.target,
+                .linkage = .static,
+                .root_source_file = .{ .cwd_relative = env.self.builder.pathFromRoot("src/start.zig") },
+            }),
+            .target = options.target,
+            .output_files = Firmware.OutputFileMap.init(host_build.allocator),
+
+            .config = config,
+
+            .modules = .{
+                .microzig = micro_build.createModule(.{
+                    .source_file = .{ .cwd_relative = micro_build.pathFromRoot("src/microzig.zig") },
+                    .dependencies = &.{
+                        .{
+                            .name = "config",
+                            .module = micro_build.createModule(.{ .source_file = config.getSource() }),
+                        },
+                    },
+                }),
+
+                .cpu = undefined,
+                .chip = undefined,
+
+                .board = null,
+                .hal = null,
+
+                .app = undefined,
+            },
+        };
+        errdefer fw.output_files.deinit();
+
+        fw.modules.chip = micro_build.createModule(.{
+            .source_file = chip_source,
+            .dependencies = &.{
+                .{ .name = "microzig", .module = fw.modules.microzig },
+            },
+        });
+        fw.modules.microzig.dependencies.put("chip", fw.modules.chip) catch @panic("out of memory");
+
+        fw.modules.cpu = micro_build.createModule(.{
+            .source_file = cpu.source_file,
+            .dependencies = &.{
+                .{ .name = "microzig", .module = fw.modules.microzig },
+            },
+        });
+        fw.modules.microzig.dependencies.put("cpu", fw.modules.cpu) catch @panic("out of memory");
+
+        if (maybe_hal) |hal| {
+            fw.modules.hal = micro_build.createModule(.{
+                .source_file = hal.source_file,
+                .dependencies = &.{
+                    .{ .name = "microzig", .module = fw.modules.microzig },
+                },
+            });
+            fw.modules.microzig.dependencies.put("hal", fw.modules.hal.?) catch @panic("out of memory");
+        }
+
+        if (maybe_board) |brd| {
+            fw.modules.board = micro_build.createModule(.{
+                .source_file = brd.source_file,
+                .dependencies = &.{
+                    .{ .name = "microzig", .module = fw.modules.microzig },
+                },
+            });
+            fw.modules.microzig.dependencies.put("board", fw.modules.board.?) catch @panic("out of memory");
+        }
+
+        fw.modules.app = host_build.createModule(.{
+            .source_file = options.source_file,
+            .dependencies = &.{
+                .{ .name = "microzig", .module = fw.modules.microzig },
+            },
+        });
+
+        const umm = env.dependency("umm-zig", .{}).module("umm");
+        fw.modules.microzig.dependencies.put("umm", umm) catch @panic("out of memory");
+
+        fw.artifact.addModule("app", fw.modules.app);
+        fw.artifact.addModule("microzig", fw.modules.microzig);
+
+        fw.artifact.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded
+        fw.artifact.single_threaded = options.single_threaded orelse fw.target.single_threaded;
+        fw.artifact.bundle_compiler_rt = options.bundle_compiler_rt orelse fw.target.bundle_compiler_rt;
+
+        switch (linker_script) {
+            .generated => {
+                fw.artifact.setLinkerScript(
+                    generateLinkerScript(host_build, chip.*) catch @panic("out of memory"),
+                );
+            },
+
+            .source_file => |source| {
+                fw.artifact.setLinkerScriptPath(source);
+            },
+        }
+
+        if (options.target.configure) |configure| {
+            configure(host_build, fw);
+        }
+
+        return fw;
+    }
+
+    /// Adds a new dependency to the `install` step that will install the `firmware` into the folder `$prefix/firmware`.
+    pub fn installFirmware(
+        /// The MicroZig instance that was used to create the firmware.
+        env: *BuildEnvironment,
+        /// The instance of the `build.zig` that should perform installation.
+        b: *std.Build,
+        /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
+        firmware: *Firmware,
+        /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
+        options: InstallFirmwareOptions,
+    ) void {
+        std.debug.assert(env == firmware.env);
+        const install_step = addInstallFirmware(env, b, firmware, options);
+        b.getInstallStep().dependOn(&install_step.step);
+    }
+
+    /// Creates a new `std.Build.Step.InstallFile` instance that will install the given firmware to `$prefix/firmware`.
+    ///
+    /// **NOTE:** This does not actually install the firmware yet. You have to add the returned step as a dependency to another step.
+    ///           If you want to just install the firmware, use `installFirmware` instead!
+    pub fn addInstallFirmware(
+        /// The MicroZig instance that was used to create the firmware.
+        env: *BuildEnvironment,
+        /// The instance of the `build.zig` that should perform installation.
+        b: *std.Build,
+        /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
+        firmware: *Firmware,
+        /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
+        options: InstallFirmwareOptions,
+    ) *std.Build.Step.InstallFile {
+        _ = env;
+        const format = firmware.resolveFormat(options.format);
+
+        const basename = b.fmt("{s}{s}", .{
+            firmware.artifact.name,
+            format.getExtension(),
+        });
+
+        return b.addInstallFileWithDir(firmware.getEmittedBin(format), .{ .custom = "firmware" }, basename);
+    }
+
+    fn dependency(env: *BuildEnvironment, name: []const u8, args: anytype) *std.Build.Dependency {
+        return env.self.builder.dependency(name, args);
+    }
+};
+
 ////////////////////////////////////////
 //      MicroZig Gen 2 Interface      //
 ////////////////////////////////////////
@@ -372,7 +708,7 @@ pub const FirmwareOptions = struct {
     name: []const u8,
 
     /// The MicroZig target that the firmware is built for. Either a board or a chip.
-    target: Target,
+    target: *const Target,
 
     /// The optimization level that should be used. Usually `ReleaseSmall` or `Debug` is a good choice.
     /// Also using `std.Build.standardOptimizeOption` is a good idea.
@@ -399,222 +735,12 @@ pub const FirmwareOptions = struct {
     linker_script: ?LinkerScript = null,
 };
 
-/// Declares a new MicroZig firmware file.
-pub fn addFirmware(
-    /// The MicroZig instance that should be used to create the firmware.
-    mz: *MicroZig,
-    /// The instance of the `build.zig` that is calling this function.
-    host_build: *std.Build,
-    /// Options that define how the firmware is built.
-    options: FirmwareOptions,
-) *Firmware {
-    const micro_build = mz.self.builder;
-
-    const chip = &options.target.chip;
-    const cpu = chip.cpu.getDescriptor();
-    const maybe_hal = options.hal orelse options.target.hal;
-    const maybe_board = options.board orelse options.target.board;
-
-    const linker_script = options.linker_script orelse options.target.linker_script;
-
-    // TODO: let the user override which ram section to use the stack on,
-    // for now just using the first ram section in the memory region list
-    const first_ram = blk: {
-        for (chip.memory_regions) |region| {
-            if (region.kind == .ram)
-                break :blk region;
-        } else @panic("no ram memory region found for setting the end-of-stack address");
-    };
-
-    // On demand, generate chip definitions via regz:
-    const chip_source = switch (chip.register_definition) {
-        .json, .atdf, .svd => |file| blk: {
-            const regz_exe = mz.dependency("regz", .{ .optimize = .ReleaseSafe }).artifact("regz");
-
-            const regz_gen = host_build.addRunArtifact(regz_exe);
-
-            regz_gen.addArg("--schema"); // Explicitly set schema type, one of: svd, atdf, json
-            regz_gen.addArg(@tagName(chip.register_definition));
-
-            regz_gen.addArg("--output_path"); // Write to a file
-            const zig_file = regz_gen.addOutputFileArg("chip.zig");
-
-            regz_gen.addFileArg(file);
-
-            break :blk zig_file;
-        },
-
-        .zig => |src| src,
-    };
-
-    const config = host_build.addOptions();
-    config.addOption(bool, "has_hal", (maybe_hal != null));
-    config.addOption(bool, "has_board", (maybe_board != null));
-
-    config.addOption(?[]const u8, "board_name", if (maybe_board) |brd| brd.name else null);
-
-    config.addOption([]const u8, "chip_name", chip.name);
-    config.addOption([]const u8, "cpu_name", chip.name);
-    config.addOption(usize, "end_of_stack", first_ram.offset + first_ram.length);
-
-    const fw: *Firmware = host_build.allocator.create(Firmware) catch @panic("out of memory");
-    fw.* = Firmware{
-        .mz = mz,
-        .host_build = host_build,
-        .artifact = host_build.addExecutable(.{
-            .name = options.name,
-            .optimize = options.optimize,
-            .target = cpu.target,
-            .linkage = .static,
-            .root_source_file = .{ .cwd_relative = mz.self.builder.pathFromRoot("src/start.zig") },
-        }),
-        .target = options.target,
-        .output_files = Firmware.OutputFileMap.init(host_build.allocator),
-
-        .config = config,
-
-        .modules = .{
-            .microzig = micro_build.createModule(.{
-                .source_file = .{ .cwd_relative = micro_build.pathFromRoot("src/microzig.zig") },
-                .dependencies = &.{
-                    .{
-                        .name = "config",
-                        .module = micro_build.createModule(.{ .source_file = config.getSource() }),
-                    },
-                },
-            }),
-
-            .cpu = undefined,
-            .chip = undefined,
-
-            .board = null,
-            .hal = null,
-
-            .app = undefined,
-        },
-    };
-    errdefer fw.output_files.deinit();
-
-    fw.modules.chip = micro_build.createModule(.{
-        .source_file = chip_source,
-        .dependencies = &.{
-            .{ .name = "microzig", .module = fw.modules.microzig },
-        },
-    });
-    fw.modules.microzig.dependencies.put("chip", fw.modules.chip) catch @panic("out of memory");
-
-    fw.modules.cpu = micro_build.createModule(.{
-        .source_file = cpu.source_file,
-        .dependencies = &.{
-            .{ .name = "microzig", .module = fw.modules.microzig },
-        },
-    });
-    fw.modules.microzig.dependencies.put("cpu", fw.modules.cpu) catch @panic("out of memory");
-
-    if (maybe_hal) |hal| {
-        fw.modules.hal = micro_build.createModule(.{
-            .source_file = hal.source_file,
-            .dependencies = &.{
-                .{ .name = "microzig", .module = fw.modules.microzig },
-            },
-        });
-        fw.modules.microzig.dependencies.put("hal", fw.modules.hal.?) catch @panic("out of memory");
-    }
-
-    if (maybe_board) |brd| {
-        fw.modules.board = micro_build.createModule(.{
-            .source_file = brd.source_file,
-            .dependencies = &.{
-                .{ .name = "microzig", .module = fw.modules.microzig },
-            },
-        });
-        fw.modules.microzig.dependencies.put("board", fw.modules.board.?) catch @panic("out of memory");
-    }
-
-    fw.modules.app = host_build.createModule(.{
-        .source_file = options.source_file,
-        .dependencies = &.{
-            .{ .name = "microzig", .module = fw.modules.microzig },
-        },
-    });
-
-    const umm = mz.dependency("umm-zig", .{}).module("umm");
-    fw.modules.microzig.dependencies.put("umm", umm) catch @panic("out of memory");
-
-    fw.artifact.addModule("app", fw.modules.app);
-    fw.artifact.addModule("microzig", fw.modules.microzig);
-
-    fw.artifact.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded
-    fw.artifact.single_threaded = options.single_threaded orelse fw.target.single_threaded;
-    fw.artifact.bundle_compiler_rt = options.bundle_compiler_rt orelse fw.target.bundle_compiler_rt;
-
-    switch (linker_script) {
-        .generated => {
-            fw.artifact.setLinkerScript(
-                generateLinkerScript(host_build, chip.*) catch @panic("out of memory"),
-            );
-        },
-
-        .source_file => |source| {
-            fw.artifact.setLinkerScriptPath(source);
-        },
-    }
-
-    if (options.target.configure) |configure| {
-        configure(host_build, fw);
-    }
-
-    return fw;
-}
-
 /// Configuration options for firmware installation.
 pub const InstallFirmwareOptions = struct {
     /// Overrides the output format for the binary. If not set, the standard preferred file format for the firmware target is used.
     format: ?BinaryFormat = null,
 };
 
-/// Adds a new dependency to the `install` step that will install the `firmware` into the folder `$prefix/firmware`.
-pub fn installFirmware(
-    /// The MicroZig instance that was used to create the firmware.
-    mz: *MicroZig,
-    /// The instance of the `build.zig` that should perform installation.
-    b: *std.Build,
-    /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
-    firmware: *Firmware,
-    /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
-    options: InstallFirmwareOptions,
-) void {
-    std.debug.assert(mz == firmware.mz);
-    const install_step = addInstallFirmware(mz, b, firmware, options);
-    b.getInstallStep().dependOn(&install_step.step);
-}
-
-/// Creates a new `std.Build.Step.InstallFile` instance that will install the given firmware to `$prefix/firmware`.
-///
-/// **NOTE:** This does not actually install the firmware yet. You have to add the returned step as a dependency to another step.
-///           If you want to just install the firmware, use `installFirmware` instead!
-pub fn addInstallFirmware(
-    /// The MicroZig instance that was used to create the firmware.
-    mz: *MicroZig,
-    /// The instance of the `build.zig` that should perform installation.
-    b: *std.Build,
-    /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
-    firmware: *Firmware,
-    /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
-    options: InstallFirmwareOptions,
-) *std.Build.Step.InstallFile {
-    const format = firmware.resolveFormat(options.format);
-
-    const basename = b.fmt("{s}{s}", .{
-        firmware.artifact.name,
-        format.getExtension(),
-    });
-
-    _ = mz;
-
-    return b.addInstallFileWithDir(firmware.getEmittedBin(format), .{ .custom = "firmware" }, basename);
-}
-
 /// Declaration of a firmware build.
 pub const Firmware = struct {
     const OutputFileMap = std.ArrayHashMap(BinaryFormat, std.Build.LazyPath, BinaryFormat.Context, false);
@@ -629,9 +755,9 @@ pub const Firmware = struct {
     };
 
     // privates:
-    mz: *MicroZig,
+    env: *BuildEnvironment,
     host_build: *std.Build,
-    target: Target,
+    target: *const Target,
     output_files: OutputFileMap,
 
     // publics:
@@ -702,7 +828,7 @@ pub const Firmware = struct {
                 },
 
                 .uf2 => |family_id| blk: {
-                    const uf2_exe = firmware.mz.dependency("uf2", .{ .optimize = .ReleaseSafe }).artifact("elf2uf2");
+                    const uf2_exe = firmware.env.dependency("uf2", .{ .optimize = .ReleaseSafe }).artifact("elf2uf2");
 
                     const convert = firmware.host_build.addRunArtifact(uf2_exe);
 
@@ -847,10 +973,6 @@ fn buildConfigError(b: *std.Build, comptime fmt: []const u8, args: anytype) nore
     @panic(msg);
 }
 
-fn dependency(mz: *MicroZig, name: []const u8, args: anytype) *std.Build.Dependency {
-    return mz.self.builder.dependency(name, args);
-}
-
 fn generateLinkerScript(b: *std.Build, chip: Chip) !std.Build.LazyPath {
     const cpu = chip.cpu.getDescriptor();
 
diff --git a/core/build.zig b/core/build.zig
index 748833fd4..1768f5133 100644
--- a/core/build.zig
+++ b/core/build.zig
@@ -3,7 +3,8 @@
 //! This means we need to use addExecutable() instead of using
 
 const std = @import("std");
-const uf2 = @import("uf2");
+const microbuild = @import("microzig-build");
+// const uf2 = @import("uf2");
 
 ////////////////////////////////////////
 //      MicroZig Gen 2 Interface      //
@@ -14,43 +15,44 @@ fn root() []const u8 {
 }
 const build_root = root();
 
-const MicroZig = @This();
+// const MicroZig = @This();
 
-b: *std.Build,
-self: *std.Build.Dependency,
+// b: *std.Build,
+// self: *std.Build.Dependency,
 
-/// Creates a new instance of the MicroZig build support.
-///
-/// This is necessary as we need to keep track of some internal state to prevent
-/// duplicated work per firmware built.
-pub fn init(b: *std.Build, dependency_name: []const u8) *MicroZig {
-    const mz = b.allocator.create(MicroZig) catch @panic("out of memory");
-    mz.* = MicroZig{
-        .b = b,
-        .self = b.dependency(dependency_name, .{}),
-    };
-    return mz;
-}
+// /// Creates a new instance of the MicroZig build support.
+// ///
+// /// This is necessary as we need to keep track of some internal state to prevent
+// /// duplicated work per firmware built.
+// pub fn init(b: *std.Build, dependency_name: []const u8) *MicroZig {
+//     const mz = b.allocator.create(MicroZig) catch @panic("out of memory");
+//     mz.* = MicroZig{
+//         .b = b,
+//         .self = b.dependency(dependency_name, .{}),
+//     };
+//     return mz;
+// }
 
 /// This build script validates usage patterns we expect from MicroZig
 pub fn build(b: *std.Build) !void {
-    const uf2_dep = b.dependency("uf2", .{});
+    _ = b;
+    // const uf2_dep = b.dependency("uf2", .{});
 
-    const build_test = b.addTest(.{
-        .root_source_file = .{ .path = "build.zig" },
-    });
+    // const build_test = b.addTest(.{
+    //     .root_source_file = .{ .path = "build.zig" },
+    // });
 
-    build_test.addAnonymousModule("uf2", .{
-        .source_file = .{ .cwd_relative = uf2_dep.builder.pathFromRoot("build.zig") },
-    });
+    // build_test.addAnonymousModule("uf2", .{
+    //     .source_file = .{ .cwd_relative = uf2_dep.builder.pathFromRoot("build.zig") },
+    // });
 
-    const install_docs = b.addInstallDirectory(.{
-        .source_dir = build_test.getEmittedDocs(),
-        .install_dir = .prefix,
-        .install_subdir = "docs",
-    });
+    // const install_docs = b.addInstallDirectory(.{
+    //     .source_dir = build_test.getEmittedDocs(),
+    //     .install_dir = .prefix,
+    //     .install_subdir = "docs",
+    // });
 
-    b.getInstallStep().dependOn(&install_docs.step);
+    // b.getInstallStep().dependOn(&install_docs.step);
 
     // const backings = @import("test/backings.zig");
     // const optimize = b.standardOptimizeOption(.{});
@@ -96,686 +98,686 @@ pub fn build(b: *std.Build) !void {
     // test_step.dependOn(&b.addRunArtifact(core_tests).step);
 }
 
-/// The resulting binary format for the firmware file.
-/// A lot of embedded systems don't use plain ELF files, thus we provide means
-/// to convert the resulting ELF into other common formats.
-pub const BinaryFormat = union(enum) {
-    /// [Executable and Linkable Format](https://en.wikipedia.org/wiki/Executable_and_Linkable_Format), the standard output from the compiler.
-    elf,
-
-    /// A flat binary, contains only the loaded portions of the firmware with an unspecified base offset.
-    bin,
-
-    /// The [Intel HEX](https://en.wikipedia.org/wiki/Intel_HEX) format, contains
-    /// an ASCII description of what memory to load where.
-    hex,
-
-    /// A [Device Firmware Upgrade](https://www.usb.org/sites/default/files/DFU_1.1.pdf) file.
-    dfu,
-
-    /// The [USB Flashing Format (UF2)](https://github.com/microsoft/uf2) designed by Microsoft.
-    uf2: uf2.FamilyId,
-
-    /// The [firmware format](https://docs.espressif.com/projects/esptool/en/latest/esp32/advanced-topics/firmware-image-format.html) used by the [esptool](https://github.com/espressif/esptool) bootloader.
-    esp,
-
-    /// Custom option for non-standard formats.
-    custom: *Custom,
-
-    /// Returns the standard extension for the resulting binary file.
-    pub fn getExtension(format: BinaryFormat) []const u8 {
-        return switch (format) {
-            .elf => ".elf",
-            .bin => ".bin",
-            .hex => ".hex",
-            .dfu => ".dfu",
-            .uf2 => ".uf2",
-            .esp => ".bin",
-
-            .custom => |c| c.extension,
-        };
-    }
-
-    pub const Custom = struct {
-        /// The standard extension of the format.
-        extension: []const u8,
-
-        /// A function that will convert a given `elf` file into the custom output format.
-        ///
-        /// The `*Custom` format is passed so contextual information can be obtained by using
-        /// `@fieldParentPtr` to provide access to tooling.
-        convert: *const fn (*Custom, elf: std.Build.LazyPath) std.Build.LazyPath,
-    };
-
-    const Enum = std.meta.Tag(BinaryFormat);
-
-    const Context = struct {
-        pub fn hash(self: @This(), fmt: BinaryFormat) u32 {
-            _ = self;
-
-            var hasher = std.hash.XxHash32.init(0x1337_42_21);
-
-            hasher.update(@tagName(fmt));
-
-            switch (fmt) {
-                .elf, .bin, .hex, .dfu, .esp => |val| {
-                    if (@TypeOf(val) != void) @compileError("Missing update: Context.hash now requires special care!");
-                },
-
-                .uf2 => |family_id| hasher.update(@tagName(family_id)),
-                .custom => |custom| hasher.update(std.mem.asBytes(custom)),
-            }
-
-            return hasher.final();
-        }
-
-        pub fn eql(self: @This(), fmt_a: BinaryFormat, fmt_b: BinaryFormat, index: usize) bool {
-            _ = self;
-            _ = index;
-            if (@as(BinaryFormat.Enum, fmt_a) != @as(BinaryFormat.Enum, fmt_b))
-                return false;
-
-            return switch (fmt_a) {
-                .elf, .bin, .hex, .dfu, .esp => |val| {
-                    if (@TypeOf(val) != void) @compileError("Missing update: Context.eql now requires special care!");
-                    return true;
-                },
-
-                .uf2 => |a| (a == fmt_b.uf2),
-                .custom => |a| (a == fmt_b.custom),
-            };
-        }
-    };
-};
-
-/// The CPU model a target uses.
-///
-/// The CPUs usually require special care on how to do interrupts, and getting an entry point.
-///
-/// MicroZig officially only supports the CPUs listed here, but other CPUs might be provided
-/// via the `custom` field.
-pub const CpuModel = union(enum) {
-    avr5,
-    cortex_m0,
-    cortex_m0plus,
-    cortex_m3,
-    cortex_m4,
-    riscv32_imac,
-
-    custom: *const Cpu,
-
-    pub fn getDescriptor(model: CpuModel) *const Cpu {
-        return switch (@as(std.meta.Tag(CpuModel), model)) {
-            inline else => |tag| &@field(cpus, @tagName(tag)),
-            .custom => model.custom,
-        };
-    }
-};
-
-/// A cpu descriptor.
-pub const Cpu = struct {
-    /// Display name of the CPU.
-    name: []const u8,
-
-    /// Source file providing startup code and memory initialization routines.
-    source_file: std.build.LazyPath,
-
-    /// The compiler target we use to compile all the code.
-    target: std.zig.CrossTarget,
-};
-
-/// A descriptor for memory regions in a microcontroller.
-pub const MemoryRegion = struct {
-    /// The type of the memory region for generating a proper linker script.
-    kind: Kind,
-    offset: u64,
-    length: u64,
-
-    pub const Kind = union(enum) {
-        /// This is a (normally) immutable memory region where the code is stored.
-        flash,
-
-        /// This is a mutable memory region for data storage.
-        ram,
-
-        /// This is a memory region that maps MMIO devices.
-        io,
-
-        /// This is a memory region that exists, but is reserved and must not be used.
-        reserved,
-
-        /// This is a memory region used for internal linking tasks required by the board support package.
-        private: PrivateRegion,
-    };
-
-    pub const PrivateRegion = struct {
-        /// The name of the memory region. Will not have an automatic numeric counter and must be unique.
-        name: []const u8,
-
-        /// Is the memory region executable?
-        executable: bool,
-
-        /// Is the memory region readable?
-        readable: bool,
-
-        /// Is the memory region writable?
-        writeable: bool,
-    };
-};
-
-/// Defines a custom microcontroller.
-pub const Chip = struct {
-    /// The display name of the controller.
-    name: []const u8,
-
-    /// (optional) link to the documentation/vendor page of the controller.
-    url: ?[]const u8 = null,
-
-    /// The cpu model this controller uses.
-    cpu: CpuModel,
-
-    /// The provider for register definitions.
-    register_definition: union(enum) {
-        /// Use `regz` to create a zig file from a JSON schema.
-        json: std.Build.LazyPath,
-
-        /// Use `regz` to create a json file from a SVD schema.
-        svd: std.Build.LazyPath,
-
-        /// Use `regz` to create a zig file from an ATDF schema.
-        atdf: std.Build.LazyPath,
-
-        /// Use the provided file directly as the chip file.
-        zig: std.Build.LazyPath,
-    },
-
-    /// The memory regions that are present in this chip.
-    memory_regions: []const MemoryRegion,
-};
-
-/// Defines a hardware abstraction layer.
-pub const HardwareAbstractionLayer = struct {
-    /// Root source file for this HAL.
-    source_file: std.Build.LazyPath,
-};
-
-/// Provides a description of a board.
-///
-/// Boards provide additional information to a chip and HAL package.
-/// For example, they can list attached peripherials, external crystal frequencies,
-/// flash sizes, ...
-pub const BoardDefinition = struct {
-    /// Display name of the board
-    name: []const u8,
-
-    /// (optional) link to the documentation/vendor page of the board.
-    url: ?[]const u8 = null,
-
-    /// Provides the root file for the board definition.
-    source_file: std.Build.LazyPath,
-};
-
-/// The linker script used to link the firmware.
-pub const LinkerScript = union(enum) {
-    /// Auto-generated linker script derived from the memory regions of the chip.
-    generated,
-
-    /// Externally defined linker script.
-    source_file: std.build.LazyPath,
-};
-
-/// A compilation target for MicroZig. Provides information about the chip,
-/// hal, board and so on.
-///
-/// This is used instead of `std.zig.CrossTarget` to define a MicroZig Firmware.
-pub const Target = struct {
-    /// The preferred binary format of this MicroZig target. If `null`, the user must
-    /// explicitly give the `.format` field during a call to `getEmittedBin()` or installation steps.
-    preferred_format: ?BinaryFormat,
-
-    /// The chip this target uses,
-    chip: Chip,
-
-    /// Usually, embedded projects are single-threaded and single-core applications. Platforms that
-    /// support multiple CPUs should set this to `false`.
-    single_threaded: bool = true,
-
-    /// Determines whether the compiler_rt package is bundled with the application or not.
-    /// This should always be true except for platforms where compiler_rt cannot be built right now.
-    bundle_compiler_rt: bool = true,
-
-    /// (optional) Provides a default hardware abstraction layer that is used.
-    /// If `null`, no `microzig.hal` will be available.
-    hal: ?HardwareAbstractionLayer = null,
-
-    /// (optional) Provides description of external hardware and connected devices
-    /// like oscillators and such.
-    ///
-    /// This structure isn't used by MicroZig itself, but can be utilized from the HAL
-    /// if present.
-    board: ?BoardDefinition = null,
-
-    /// (optional) Provide a custom linker script for the hardware or define a custom generation.
-    linker_script: LinkerScript = .generated,
-
-    /// (optional) Further configures the created firmware depending on the chip and/or board settings.
-    /// This can be used to set/change additional properties on the created `*Firmware` object.
-    configure: ?*const fn (host_build: *std.Build, *Firmware) void = null,
-
-    /// (optional) Post processing step that will patch up and modify the elf file if necessary.
-    binary_post_process: ?*const fn (host_build: *std.Build, std.Build.LazyPath) std.Build.LazyPath = null,
-};
-
-/// Options to the `addFirmware` function.
-pub const FirmwareOptions = struct {
-    /// The name of the firmware file.
-    name: []const u8,
-
-    /// The MicroZig target that the firmware is built for. Either a board or a chip.
-    target: Target,
-
-    /// The optimization level that should be used. Usually `ReleaseSmall` or `Debug` is a good choice.
-    /// Also using `std.Build.standardOptimizeOption` is a good idea.
-    optimize: std.builtin.OptimizeMode,
-
-    /// The root source file for the application. This is your `src/main.zig` file.
-    source_file: std.Build.LazyPath,
-
-    // Overrides:
-
-    /// If set, overrides the `single_threaded` property of the target.
-    single_threaded: ?bool = null,
-
-    /// If set, overrides the `bundle_compiler_rt` property of the target.
-    bundle_compiler_rt: ?bool = null,
-
-    /// If set, overrides the `hal` property of the target.
-    hal: ?HardwareAbstractionLayer = null,
-
-    /// If set, overrides the `board` property of the target.
-    board: ?BoardDefinition = null,
-
-    /// If set, overrides the `linker_script` property of the target.
-    linker_script: ?LinkerScript = null,
-};
-
-/// Declares a new MicroZig firmware file.
-pub fn addFirmware(
-    /// The MicroZig instance that should be used to create the firmware.
-    mz: *MicroZig,
-    /// The instance of the `build.zig` that is calling this function.
-    host_build: *std.Build,
-    /// Options that define how the firmware is built.
-    options: FirmwareOptions,
-) *Firmware {
-    const micro_build = mz.self.builder;
-
-    const chip = &options.target.chip;
-    const cpu = chip.cpu.getDescriptor();
-    const maybe_hal = options.hal orelse options.target.hal;
-    const maybe_board = options.board orelse options.target.board;
-
-    const linker_script = options.linker_script orelse options.target.linker_script;
-
-    // TODO: let the user override which ram section to use the stack on,
-    // for now just using the first ram section in the memory region list
-    const first_ram = blk: {
-        for (chip.memory_regions) |region| {
-            if (region.kind == .ram)
-                break :blk region;
-        } else @panic("no ram memory region found for setting the end-of-stack address");
-    };
-
-    // On demand, generate chip definitions via regz:
-    const chip_source = switch (chip.register_definition) {
-        .json, .atdf, .svd => |file| blk: {
-            const regz_exe = mz.dependency("regz", .{ .optimize = .ReleaseSafe }).artifact("regz");
-
-            const regz_gen = host_build.addRunArtifact(regz_exe);
-
-            regz_gen.addArg("--schema"); // Explicitly set schema type, one of: svd, atdf, json
-            regz_gen.addArg(@tagName(chip.register_definition));
-
-            regz_gen.addArg("--output_path"); // Write to a file
-            const zig_file = regz_gen.addOutputFileArg("chip.zig");
-
-            regz_gen.addFileArg(file);
-
-            break :blk zig_file;
-        },
-
-        .zig => |src| src,
-    };
-
-    const config = host_build.addOptions();
-    config.addOption(bool, "has_hal", (maybe_hal != null));
-    config.addOption(bool, "has_board", (maybe_board != null));
-
-    config.addOption(?[]const u8, "board_name", if (maybe_board) |brd| brd.name else null);
-
-    config.addOption([]const u8, "chip_name", chip.name);
-    config.addOption([]const u8, "cpu_name", chip.name);
-    config.addOption(usize, "end_of_stack", first_ram.offset + first_ram.length);
-
-    const fw: *Firmware = host_build.allocator.create(Firmware) catch @panic("out of memory");
-    fw.* = Firmware{
-        .mz = mz,
-        .host_build = host_build,
-        .artifact = host_build.addExecutable(.{
-            .name = options.name,
-            .optimize = options.optimize,
-            .target = cpu.target,
-            .linkage = .static,
-            .root_source_file = .{ .cwd_relative = mz.self.builder.pathFromRoot("src/start.zig") },
-        }),
-        .target = options.target,
-        .output_files = Firmware.OutputFileMap.init(host_build.allocator),
-
-        .config = config,
-
-        .modules = .{
-            .microzig = micro_build.createModule(.{
-                .source_file = .{ .cwd_relative = micro_build.pathFromRoot("src/microzig.zig") },
-                .dependencies = &.{
-                    .{
-                        .name = "config",
-                        .module = micro_build.createModule(.{ .source_file = config.getSource() }),
-                    },
-                },
-            }),
-
-            .cpu = undefined,
-            .chip = undefined,
-
-            .board = null,
-            .hal = null,
-
-            .app = undefined,
-        },
-    };
-    errdefer fw.output_files.deinit();
-
-    fw.modules.chip = micro_build.createModule(.{
-        .source_file = chip_source,
-        .dependencies = &.{
-            .{ .name = "microzig", .module = fw.modules.microzig },
-        },
-    });
-    fw.modules.microzig.dependencies.put("chip", fw.modules.chip) catch @panic("out of memory");
-
-    fw.modules.cpu = micro_build.createModule(.{
-        .source_file = cpu.source_file,
-        .dependencies = &.{
-            .{ .name = "microzig", .module = fw.modules.microzig },
-        },
-    });
-    fw.modules.microzig.dependencies.put("cpu", fw.modules.cpu) catch @panic("out of memory");
-
-    if (maybe_hal) |hal| {
-        fw.modules.hal = micro_build.createModule(.{
-            .source_file = hal.source_file,
-            .dependencies = &.{
-                .{ .name = "microzig", .module = fw.modules.microzig },
-            },
-        });
-        fw.modules.microzig.dependencies.put("hal", fw.modules.hal.?) catch @panic("out of memory");
-    }
-
-    if (maybe_board) |brd| {
-        fw.modules.board = micro_build.createModule(.{
-            .source_file = brd.source_file,
-            .dependencies = &.{
-                .{ .name = "microzig", .module = fw.modules.microzig },
-            },
-        });
-        fw.modules.microzig.dependencies.put("board", fw.modules.board.?) catch @panic("out of memory");
-    }
-
-    fw.modules.app = host_build.createModule(.{
-        .source_file = options.source_file,
-        .dependencies = &.{
-            .{ .name = "microzig", .module = fw.modules.microzig },
-        },
-    });
-
-    const umm = mz.dependency("umm-zig", .{}).module("umm");
-    fw.modules.microzig.dependencies.put("umm", umm) catch @panic("out of memory");
-
-    fw.artifact.addModule("app", fw.modules.app);
-    fw.artifact.addModule("microzig", fw.modules.microzig);
-
-    fw.artifact.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded
-    fw.artifact.single_threaded = options.single_threaded orelse fw.target.single_threaded;
-    fw.artifact.bundle_compiler_rt = options.bundle_compiler_rt orelse fw.target.bundle_compiler_rt;
-
-    switch (linker_script) {
-        .generated => {
-            fw.artifact.setLinkerScript(
-                generateLinkerScript(host_build, chip.*) catch @panic("out of memory"),
-            );
-        },
-
-        .source_file => |source| {
-            fw.artifact.setLinkerScriptPath(source);
-        },
-    }
-
-    if (options.target.configure) |configure| {
-        configure(host_build, fw);
-    }
-
-    return fw;
-}
-
-/// Configuration options for firmware installation.
-pub const InstallFirmwareOptions = struct {
-    /// Overrides the output format for the binary. If not set, the standard preferred file format for the firmware target is used.
-    format: ?BinaryFormat = null,
-};
-
-/// Adds a new dependency to the `install` step that will install the `firmware` into the folder `$prefix/firmware`.
-pub fn installFirmware(
-    /// The MicroZig instance that was used to create the firmware.
-    mz: *MicroZig,
-    /// The instance of the `build.zig` that should perform installation.
-    b: *std.Build,
-    /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
-    firmware: *Firmware,
-    /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
-    options: InstallFirmwareOptions,
-) void {
-    std.debug.assert(mz == firmware.mz);
-    const install_step = addInstallFirmware(mz, b, firmware, options);
-    b.getInstallStep().dependOn(&install_step.step);
-}
-
-/// Creates a new `std.Build.Step.InstallFile` instance that will install the given firmware to `$prefix/firmware`.
-///
-/// **NOTE:** This does not actually install the firmware yet. You have to add the returned step as a dependency to another step.
-///           If you want to just install the firmware, use `installFirmware` instead!
-pub fn addInstallFirmware(
-    /// The MicroZig instance that was used to create the firmware.
-    mz: *MicroZig,
-    /// The instance of the `build.zig` that should perform installation.
-    b: *std.Build,
-    /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
-    firmware: *Firmware,
-    /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
-    options: InstallFirmwareOptions,
-) *std.Build.Step.InstallFile {
-    const format = firmware.resolveFormat(options.format);
-
-    const basename = b.fmt("{s}{s}", .{
-        firmware.artifact.name,
-        format.getExtension(),
-    });
-
-    _ = mz;
-
-    return b.addInstallFileWithDir(firmware.getEmittedBin(format), .{ .custom = "firmware" }, basename);
-}
-
-/// Declaration of a firmware build.
-pub const Firmware = struct {
-    const OutputFileMap = std.ArrayHashMap(BinaryFormat, std.Build.LazyPath, BinaryFormat.Context, false);
-
-    const Modules = struct {
-        app: *std.Build.Module,
-        cpu: *std.Build.Module,
-        chip: *std.Build.Module,
-        board: ?*std.Build.Module,
-        hal: ?*std.Build.Module,
-        microzig: *std.Build.Module,
-    };
-
-    // privates:
-    mz: *MicroZig,
-    host_build: *std.Build,
-    target: Target,
-    output_files: OutputFileMap,
-
-    // publics:
-
-    /// The artifact that is built by Zig.
-    artifact: *std.Build.Step.Compile,
-
-    /// The options step that provides `microzig.config`. If you need custom configuration, you can add this here.
-    config: *std.Build.Step.Options,
-
-    /// Declaration of the MicroZig modules used by this firmware.
-    modules: Modules,
-
-    /// Path to the emitted elf file, if any.
-    emitted_elf: ?std.Build.LazyPath = null,
-
-    /// Returns the emitted ELF file for this firmware. This is useful if you need debug information
-    /// or want to use a debugger like Segger, ST-Link or similar.
-    ///
-    /// **NOTE:** This is similar, but not equivalent to `std.Build.Step.Compile.getEmittedBin`. The call on the compile step does
-    ///           not include post processing of the ELF files necessary by certain targets.
-    pub fn getEmittedElf(firmware: *Firmware) std.Build.LazyPath {
-        if (firmware.emitted_elf == null) {
-            const raw_elf = firmware.artifact.getEmittedBin();
-            firmware.emitted_elf = if (firmware.target.binary_post_process) |binary_post_process|
-                binary_post_process(firmware.host_build, raw_elf)
-            else
-                raw_elf;
-        }
-        return firmware.emitted_elf.?;
-    }
-
-    /// Returns the emitted binary for this firmware. The file is either in the preferred file format for
-    /// the target or in `format` if not null.
-    ///
-    /// **NOTE:** The file returned here is the same file that will be installed.
-    pub fn getEmittedBin(firmware: *Firmware, format: ?BinaryFormat) std.Build.LazyPath {
-        const actual_format = firmware.resolveFormat(format);
-
-        const gop = firmware.output_files.getOrPut(actual_format) catch @panic("out of memory");
-        if (!gop.found_existing) {
-            const elf_file = firmware.getEmittedElf();
-
-            const basename = firmware.host_build.fmt("{s}{s}", .{
-                firmware.artifact.name,
-                actual_format.getExtension(),
-            });
-
-            gop.value_ptr.* = switch (actual_format) {
-                .elf => elf_file,
-
-                .bin => blk: {
-                    const objcopy = firmware.host_build.addObjCopy(elf_file, .{
-                        .basename = basename,
-                        .format = .bin,
-                    });
-
-                    break :blk objcopy.getOutput();
-                },
-
-                .hex => blk: {
-                    const objcopy = firmware.host_build.addObjCopy(elf_file, .{
-                        .basename = basename,
-                        .format = .hex,
-                    });
-
-                    break :blk objcopy.getOutput();
-                },
-
-                .uf2 => |family_id| blk: {
-                    const uf2_exe = firmware.mz.dependency("uf2", .{ .optimize = .ReleaseSafe }).artifact("elf2uf2");
-
-                    const convert = firmware.host_build.addRunArtifact(uf2_exe);
-
-                    convert.addArg("--family-id");
-                    convert.addArg(firmware.host_build.fmt("0x{X:0>4}", .{@intFromEnum(family_id)}));
-
-                    convert.addArg("--elf-path");
-                    convert.addFileArg(elf_file);
-
-                    convert.addArg("--output-path");
-                    break :blk convert.addOutputFileArg(basename);
-                },
-
-                .dfu => buildConfigError(firmware.host_build, "DFU is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/145 for more details!", .{}),
-                .esp => buildConfigError(firmware.host_build, "ESP firmware image is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/146 for more details!", .{}),
-
-                .custom => |generator| generator.convert(generator, elf_file),
-            };
-        }
-        return gop.value_ptr.*;
-    }
-
-    pub const AppDependencyOptions = struct {
-        depend_on_microzig: bool = false,
-    };
-
-    /// Adds a regular dependency to your application.
-    pub fn addAppDependency(fw: *Firmware, name: []const u8, module: *std.Build.Module, options: AppDependencyOptions) void {
-        if (options.depend_on_microzig) {
-            module.dependencies.put("microzig", fw.modules.microzig) catch @panic("OOM");
-        }
-        fw.modules.app.dependencies.put(name, module) catch @panic("OOM");
-    }
-
-    pub fn addIncludePath(fw: *Firmware, path: std.Build.LazyPath) void {
-        fw.artifact.addIncludePath(path);
-    }
-
-    pub fn addSystemIncludePath(fw: *Firmware, path: std.Build.LazyPath) void {
-        fw.artifact.addSystemIncludePath(path);
-    }
-
-    pub fn addCSourceFile(fw: *Firmware, source: std.Build.Step.Compile.CSourceFile) void {
-        fw.artifact.addCSourceFile(source);
-    }
-
-    pub fn addOptions(fw: *Firmware, module_name: []const u8, options: *std.Build.OptionsStep) void {
-        fw.artifact.addOptions(module_name, options);
-        fw.modules.app.dependencies.put(
-            module_name,
-            fw.host_build.createModule(.{
-                .source_file = options.getOutput(),
-            }),
-        ) catch @panic("OOM");
-    }
-
-    pub fn addObjectFile(fw: *Firmware, source: std.Build.LazyPath) void {
-        fw.artifact.addObjectFile(source);
-    }
-
-    fn resolveFormat(firmware: *Firmware, format: ?BinaryFormat) BinaryFormat {
-        if (format) |fmt| return fmt;
-
-        if (firmware.target.preferred_format) |fmt| return fmt;
-
-        buildConfigError(firmware.host_build, "{s} has no preferred output format, please provide one in the `format` option.", .{
-            firmware.target.chip.name,
-        });
-    }
-};
+// /// The resulting binary format for the firmware file.
+// /// A lot of embedded systems don't use plain ELF files, thus we provide means
+// /// to convert the resulting ELF into other common formats.
+// pub const BinaryFormat = union(enum) {
+//     /// [Executable and Linkable Format](https://en.wikipedia.org/wiki/Executable_and_Linkable_Format), the standard output from the compiler.
+//     elf,
+
+//     /// A flat binary, contains only the loaded portions of the firmware with an unspecified base offset.
+//     bin,
+
+//     /// The [Intel HEX](https://en.wikipedia.org/wiki/Intel_HEX) format, contains
+//     /// an ASCII description of what memory to load where.
+//     hex,
+
+//     /// A [Device Firmware Upgrade](https://www.usb.org/sites/default/files/DFU_1.1.pdf) file.
+//     dfu,
+
+//     /// The [USB Flashing Format (UF2)](https://github.com/microsoft/uf2) designed by Microsoft.
+//     uf2: uf2.FamilyId,
+
+//     /// The [firmware format](https://docs.espressif.com/projects/esptool/en/latest/esp32/advanced-topics/firmware-image-format.html) used by the [esptool](https://github.com/espressif/esptool) bootloader.
+//     esp,
+
+//     /// Custom option for non-standard formats.
+//     custom: *Custom,
+
+//     /// Returns the standard extension for the resulting binary file.
+//     pub fn getExtension(format: BinaryFormat) []const u8 {
+//         return switch (format) {
+//             .elf => ".elf",
+//             .bin => ".bin",
+//             .hex => ".hex",
+//             .dfu => ".dfu",
+//             .uf2 => ".uf2",
+//             .esp => ".bin",
+
+//             .custom => |c| c.extension,
+//         };
+//     }
+
+//     pub const Custom = struct {
+//         /// The standard extension of the format.
+//         extension: []const u8,
+
+//         /// A function that will convert a given `elf` file into the custom output format.
+//         ///
+//         /// The `*Custom` format is passed so contextual information can be obtained by using
+//         /// `@fieldParentPtr` to provide access to tooling.
+//         convert: *const fn (*Custom, elf: std.Build.LazyPath) std.Build.LazyPath,
+//     };
+
+//     const Enum = std.meta.Tag(BinaryFormat);
+
+//     const Context = struct {
+//         pub fn hash(self: @This(), fmt: BinaryFormat) u32 {
+//             _ = self;
+
+//             var hasher = std.hash.XxHash32.init(0x1337_42_21);
+
+//             hasher.update(@tagName(fmt));
+
+//             switch (fmt) {
+//                 .elf, .bin, .hex, .dfu, .esp => |val| {
+//                     if (@TypeOf(val) != void) @compileError("Missing update: Context.hash now requires special care!");
+//                 },
+
+//                 .uf2 => |family_id| hasher.update(@tagName(family_id)),
+//                 .custom => |custom| hasher.update(std.mem.asBytes(custom)),
+//             }
+
+//             return hasher.final();
+//         }
+
+//         pub fn eql(self: @This(), fmt_a: BinaryFormat, fmt_b: BinaryFormat, index: usize) bool {
+//             _ = self;
+//             _ = index;
+//             if (@as(BinaryFormat.Enum, fmt_a) != @as(BinaryFormat.Enum, fmt_b))
+//                 return false;
+
+//             return switch (fmt_a) {
+//                 .elf, .bin, .hex, .dfu, .esp => |val| {
+//                     if (@TypeOf(val) != void) @compileError("Missing update: Context.eql now requires special care!");
+//                     return true;
+//                 },
+
+//                 .uf2 => |a| (a == fmt_b.uf2),
+//                 .custom => |a| (a == fmt_b.custom),
+//             };
+//         }
+//     };
+// };
+
+// /// The CPU model a target uses.
+// ///
+// /// The CPUs usually require special care on how to do interrupts, and getting an entry point.
+// ///
+// /// MicroZig officially only supports the CPUs listed here, but other CPUs might be provided
+// /// via the `custom` field.
+// pub const CpuModel = union(enum) {
+//     avr5,
+//     cortex_m0,
+//     cortex_m0plus,
+//     cortex_m3,
+//     cortex_m4,
+//     riscv32_imac,
+
+//     custom: *const Cpu,
+
+//     pub fn getDescriptor(model: CpuModel) *const Cpu {
+//         return switch (@as(std.meta.Tag(CpuModel), model)) {
+//             inline else => |tag| &@field(cpus, @tagName(tag)),
+//             .custom => model.custom,
+//         };
+//     }
+// };
+
+// /// A cpu descriptor.
+// pub const Cpu = struct {
+//     /// Display name of the CPU.
+//     name: []const u8,
+
+//     /// Source file providing startup code and memory initialization routines.
+//     source_file: std.build.LazyPath,
+
+//     /// The compiler target we use to compile all the code.
+//     target: std.zig.CrossTarget,
+// };
+
+// /// A descriptor for memory regions in a microcontroller.
+// pub const MemoryRegion = struct {
+//     /// The type of the memory region for generating a proper linker script.
+//     kind: Kind,
+//     offset: u64,
+//     length: u64,
+
+//     pub const Kind = union(enum) {
+//         /// This is a (normally) immutable memory region where the code is stored.
+//         flash,
+
+//         /// This is a mutable memory region for data storage.
+//         ram,
+
+//         /// This is a memory region that maps MMIO devices.
+//         io,
+
+//         /// This is a memory region that exists, but is reserved and must not be used.
+//         reserved,
+
+//         /// This is a memory region used for internal linking tasks required by the board support package.
+//         private: PrivateRegion,
+//     };
+
+//     pub const PrivateRegion = struct {
+//         /// The name of the memory region. Will not have an automatic numeric counter and must be unique.
+//         name: []const u8,
+
+//         /// Is the memory region executable?
+//         executable: bool,
+
+//         /// Is the memory region readable?
+//         readable: bool,
+
+//         /// Is the memory region writable?
+//         writeable: bool,
+//     };
+// };
+
+// /// Defines a custom microcontroller.
+// pub const Chip = struct {
+//     /// The display name of the controller.
+//     name: []const u8,
+
+//     /// (optional) link to the documentation/vendor page of the controller.
+//     url: ?[]const u8 = null,
+
+//     /// The cpu model this controller uses.
+//     cpu: CpuModel,
+
+//     /// The provider for register definitions.
+//     register_definition: union(enum) {
+//         /// Use `regz` to create a zig file from a JSON schema.
+//         json: std.Build.LazyPath,
+
+//         /// Use `regz` to create a json file from a SVD schema.
+//         svd: std.Build.LazyPath,
+
+//         /// Use `regz` to create a zig file from an ATDF schema.
+//         atdf: std.Build.LazyPath,
+
+//         /// Use the provided file directly as the chip file.
+//         zig: std.Build.LazyPath,
+//     },
+
+//     /// The memory regions that are present in this chip.
+//     memory_regions: []const MemoryRegion,
+// };
+
+// /// Defines a hardware abstraction layer.
+// pub const HardwareAbstractionLayer = struct {
+//     /// Root source file for this HAL.
+//     source_file: std.Build.LazyPath,
+// };
+
+// /// Provides a description of a board.
+// ///
+// /// Boards provide additional information to a chip and HAL package.
+// /// For example, they can list attached peripherials, external crystal frequencies,
+// /// flash sizes, ...
+// pub const BoardDefinition = struct {
+//     /// Display name of the board
+//     name: []const u8,
+
+//     /// (optional) link to the documentation/vendor page of the board.
+//     url: ?[]const u8 = null,
+
+//     /// Provides the root file for the board definition.
+//     source_file: std.Build.LazyPath,
+// };
+
+// /// The linker script used to link the firmware.
+// pub const LinkerScript = union(enum) {
+//     /// Auto-generated linker script derived from the memory regions of the chip.
+//     generated,
+
+//     /// Externally defined linker script.
+//     source_file: std.build.LazyPath,
+// };
+
+// /// A compilation target for MicroZig. Provides information about the chip,
+// /// hal, board and so on.
+// ///
+// /// This is used instead of `std.zig.CrossTarget` to define a MicroZig Firmware.
+// pub const Target = struct {
+//     /// The preferred binary format of this MicroZig target. If `null`, the user must
+//     /// explicitly give the `.format` field during a call to `getEmittedBin()` or installation steps.
+//     preferred_format: ?BinaryFormat,
+
+//     /// The chip this target uses,
+//     chip: Chip,
+
+//     /// Usually, embedded projects are single-threaded and single-core applications. Platforms that
+//     /// support multiple CPUs should set this to `false`.
+//     single_threaded: bool = true,
+
+//     /// Determines whether the compiler_rt package is bundled with the application or not.
+//     /// This should always be true except for platforms where compiler_rt cannot be built right now.
+//     bundle_compiler_rt: bool = true,
+
+//     /// (optional) Provides a default hardware abstraction layer that is used.
+//     /// If `null`, no `microzig.hal` will be available.
+//     hal: ?HardwareAbstractionLayer = null,
+
+//     /// (optional) Provides description of external hardware and connected devices
+//     /// like oscillators and such.
+//     ///
+//     /// This structure isn't used by MicroZig itself, but can be utilized from the HAL
+//     /// if present.
+//     board: ?BoardDefinition = null,
+
+//     /// (optional) Provide a custom linker script for the hardware or define a custom generation.
+//     linker_script: LinkerScript = .generated,
+
+//     /// (optional) Further configures the created firmware depending on the chip and/or board settings.
+//     /// This can be used to set/change additional properties on the created `*Firmware` object.
+//     configure: ?*const fn (host_build: *std.Build, *Firmware) void = null,
+
+//     /// (optional) Post processing step that will patch up and modify the elf file if necessary.
+//     binary_post_process: ?*const fn (host_build: *std.Build, std.Build.LazyPath) std.Build.LazyPath = null,
+// };
+
+// /// Options to the `addFirmware` function.
+// pub const FirmwareOptions = struct {
+//     /// The name of the firmware file.
+//     name: []const u8,
+
+//     /// The MicroZig target that the firmware is built for. Either a board or a chip.
+//     target: Target,
+
+//     /// The optimization level that should be used. Usually `ReleaseSmall` or `Debug` is a good choice.
+//     /// Also using `std.Build.standardOptimizeOption` is a good idea.
+//     optimize: std.builtin.OptimizeMode,
+
+//     /// The root source file for the application. This is your `src/main.zig` file.
+//     source_file: std.Build.LazyPath,
+
+//     // Overrides:
+
+//     /// If set, overrides the `single_threaded` property of the target.
+//     single_threaded: ?bool = null,
+
+//     /// If set, overrides the `bundle_compiler_rt` property of the target.
+//     bundle_compiler_rt: ?bool = null,
+
+//     /// If set, overrides the `hal` property of the target.
+//     hal: ?HardwareAbstractionLayer = null,
+
+//     /// If set, overrides the `board` property of the target.
+//     board: ?BoardDefinition = null,
+
+//     /// If set, overrides the `linker_script` property of the target.
+//     linker_script: ?LinkerScript = null,
+// };
+
+// /// Declares a new MicroZig firmware file.
+// pub fn addFirmware(
+//     /// The MicroZig instance that should be used to create the firmware.
+//     mz: *MicroZig,
+//     /// The instance of the `build.zig` that is calling this function.
+//     host_build: *std.Build,
+//     /// Options that define how the firmware is built.
+//     options: FirmwareOptions,
+// ) *Firmware {
+//     const micro_build = mz.self.builder;
+
+//     const chip = &options.target.chip;
+//     const cpu = chip.cpu.getDescriptor();
+//     const maybe_hal = options.hal orelse options.target.hal;
+//     const maybe_board = options.board orelse options.target.board;
+
+//     const linker_script = options.linker_script orelse options.target.linker_script;
+
+//     // TODO: let the user override which ram section to use the stack on,
+//     // for now just using the first ram section in the memory region list
+//     const first_ram = blk: {
+//         for (chip.memory_regions) |region| {
+//             if (region.kind == .ram)
+//                 break :blk region;
+//         } else @panic("no ram memory region found for setting the end-of-stack address");
+//     };
+
+//     // On demand, generate chip definitions via regz:
+//     const chip_source = switch (chip.register_definition) {
+//         .json, .atdf, .svd => |file| blk: {
+//             const regz_exe = mz.dependency("regz", .{ .optimize = .ReleaseSafe }).artifact("regz");
+
+//             const regz_gen = host_build.addRunArtifact(regz_exe);
+
+//             regz_gen.addArg("--schema"); // Explicitly set schema type, one of: svd, atdf, json
+//             regz_gen.addArg(@tagName(chip.register_definition));
+
+//             regz_gen.addArg("--output_path"); // Write to a file
+//             const zig_file = regz_gen.addOutputFileArg("chip.zig");
+
+//             regz_gen.addFileArg(file);
+
+//             break :blk zig_file;
+//         },
+
+//         .zig => |src| src,
+//     };
+
+//     const config = host_build.addOptions();
+//     config.addOption(bool, "has_hal", (maybe_hal != null));
+//     config.addOption(bool, "has_board", (maybe_board != null));
+
+//     config.addOption(?[]const u8, "board_name", if (maybe_board) |brd| brd.name else null);
+
+//     config.addOption([]const u8, "chip_name", chip.name);
+//     config.addOption([]const u8, "cpu_name", chip.name);
+//     config.addOption(usize, "end_of_stack", first_ram.offset + first_ram.length);
+
+//     const fw: *Firmware = host_build.allocator.create(Firmware) catch @panic("out of memory");
+//     fw.* = Firmware{
+//         .mz = mz,
+//         .host_build = host_build,
+//         .artifact = host_build.addExecutable(.{
+//             .name = options.name,
+//             .optimize = options.optimize,
+//             .target = cpu.target,
+//             .linkage = .static,
+//             .root_source_file = .{ .cwd_relative = mz.self.builder.pathFromRoot("src/start.zig") },
+//         }),
+//         .target = options.target,
+//         .output_files = Firmware.OutputFileMap.init(host_build.allocator),
+
+//         .config = config,
+
+//         .modules = .{
+//             .microzig = micro_build.createModule(.{
+//                 .source_file = .{ .cwd_relative = micro_build.pathFromRoot("src/microzig.zig") },
+//                 .dependencies = &.{
+//                     .{
+//                         .name = "config",
+//                         .module = micro_build.createModule(.{ .source_file = config.getSource() }),
+//                     },
+//                 },
+//             }),
+
+//             .cpu = undefined,
+//             .chip = undefined,
+
+//             .board = null,
+//             .hal = null,
+
+//             .app = undefined,
+//         },
+//     };
+//     errdefer fw.output_files.deinit();
+
+//     fw.modules.chip = micro_build.createModule(.{
+//         .source_file = chip_source,
+//         .dependencies = &.{
+//             .{ .name = "microzig", .module = fw.modules.microzig },
+//         },
+//     });
+//     fw.modules.microzig.dependencies.put("chip", fw.modules.chip) catch @panic("out of memory");
+
+//     fw.modules.cpu = micro_build.createModule(.{
+//         .source_file = cpu.source_file,
+//         .dependencies = &.{
+//             .{ .name = "microzig", .module = fw.modules.microzig },
+//         },
+//     });
+//     fw.modules.microzig.dependencies.put("cpu", fw.modules.cpu) catch @panic("out of memory");
+
+//     if (maybe_hal) |hal| {
+//         fw.modules.hal = micro_build.createModule(.{
+//             .source_file = hal.source_file,
+//             .dependencies = &.{
+//                 .{ .name = "microzig", .module = fw.modules.microzig },
+//             },
+//         });
+//         fw.modules.microzig.dependencies.put("hal", fw.modules.hal.?) catch @panic("out of memory");
+//     }
+
+//     if (maybe_board) |brd| {
+//         fw.modules.board = micro_build.createModule(.{
+//             .source_file = brd.source_file,
+//             .dependencies = &.{
+//                 .{ .name = "microzig", .module = fw.modules.microzig },
+//             },
+//         });
+//         fw.modules.microzig.dependencies.put("board", fw.modules.board.?) catch @panic("out of memory");
+//     }
+
+//     fw.modules.app = host_build.createModule(.{
+//         .source_file = options.source_file,
+//         .dependencies = &.{
+//             .{ .name = "microzig", .module = fw.modules.microzig },
+//         },
+//     });
+
+//     const umm = mz.dependency("umm-zig", .{}).module("umm");
+//     fw.modules.microzig.dependencies.put("umm", umm) catch @panic("out of memory");
+
+//     fw.artifact.addModule("app", fw.modules.app);
+//     fw.artifact.addModule("microzig", fw.modules.microzig);
+
+//     fw.artifact.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded
+//     fw.artifact.single_threaded = options.single_threaded orelse fw.target.single_threaded;
+//     fw.artifact.bundle_compiler_rt = options.bundle_compiler_rt orelse fw.target.bundle_compiler_rt;
+
+//     switch (linker_script) {
+//         .generated => {
+//             fw.artifact.setLinkerScript(
+//                 generateLinkerScript(host_build, chip.*) catch @panic("out of memory"),
+//             );
+//         },
+
+//         .source_file => |source| {
+//             fw.artifact.setLinkerScriptPath(source);
+//         },
+//     }
+
+//     if (options.target.configure) |configure| {
+//         configure(host_build, fw);
+//     }
+
+//     return fw;
+// }
+
+// /// Configuration options for firmware installation.
+// pub const InstallFirmwareOptions = struct {
+//     /// Overrides the output format for the binary. If not set, the standard preferred file format for the firmware target is used.
+//     format: ?BinaryFormat = null,
+// };
+
+// /// Adds a new dependency to the `install` step that will install the `firmware` into the folder `$prefix/firmware`.
+// pub fn installFirmware(
+//     /// The MicroZig instance that was used to create the firmware.
+//     mz: *MicroZig,
+//     /// The instance of the `build.zig` that should perform installation.
+//     b: *std.Build,
+//     /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
+//     firmware: *Firmware,
+//     /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
+//     options: InstallFirmwareOptions,
+// ) void {
+//     std.debug.assert(mz == firmware.mz);
+//     const install_step = addInstallFirmware(mz, b, firmware, options);
+//     b.getInstallStep().dependOn(&install_step.step);
+// }
+
+// /// Creates a new `std.Build.Step.InstallFile` instance that will install the given firmware to `$prefix/firmware`.
+// ///
+// /// **NOTE:** This does not actually install the firmware yet. You have to add the returned step as a dependency to another step.
+// ///           If you want to just install the firmware, use `installFirmware` instead!
+// pub fn addInstallFirmware(
+//     /// The MicroZig instance that was used to create the firmware.
+//     mz: *MicroZig,
+//     /// The instance of the `build.zig` that should perform installation.
+//     b: *std.Build,
+//     /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
+//     firmware: *Firmware,
+//     /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
+//     options: InstallFirmwareOptions,
+// ) *std.Build.Step.InstallFile {
+//     const format = firmware.resolveFormat(options.format);
+
+//     const basename = b.fmt("{s}{s}", .{
+//         firmware.artifact.name,
+//         format.getExtension(),
+//     });
+
+//     _ = mz;
+
+//     return b.addInstallFileWithDir(firmware.getEmittedBin(format), .{ .custom = "firmware" }, basename);
+// }
+
+// /// Declaration of a firmware build.
+// pub const Firmware = struct {
+//     const OutputFileMap = std.ArrayHashMap(BinaryFormat, std.Build.LazyPath, BinaryFormat.Context, false);
+
+//     const Modules = struct {
+//         app: *std.Build.Module,
+//         cpu: *std.Build.Module,
+//         chip: *std.Build.Module,
+//         board: ?*std.Build.Module,
+//         hal: ?*std.Build.Module,
+//         microzig: *std.Build.Module,
+//     };
+
+//     // privates:
+//     mz: *MicroZig,
+//     host_build: *std.Build,
+//     target: Target,
+//     output_files: OutputFileMap,
+
+//     // publics:
+
+//     /// The artifact that is built by Zig.
+//     artifact: *std.Build.Step.Compile,
+
+//     /// The options step that provides `microzig.config`. If you need custom configuration, you can add this here.
+//     config: *std.Build.Step.Options,
+
+//     /// Declaration of the MicroZig modules used by this firmware.
+//     modules: Modules,
+
+//     /// Path to the emitted elf file, if any.
+//     emitted_elf: ?std.Build.LazyPath = null,
+
+//     /// Returns the emitted ELF file for this firmware. This is useful if you need debug information
+//     /// or want to use a debugger like Segger, ST-Link or similar.
+//     ///
+//     /// **NOTE:** This is similar, but not equivalent to `std.Build.Step.Compile.getEmittedBin`. The call on the compile step does
+//     ///           not include post processing of the ELF files necessary by certain targets.
+//     pub fn getEmittedElf(firmware: *Firmware) std.Build.LazyPath {
+//         if (firmware.emitted_elf == null) {
+//             const raw_elf = firmware.artifact.getEmittedBin();
+//             firmware.emitted_elf = if (firmware.target.binary_post_process) |binary_post_process|
+//                 binary_post_process(firmware.host_build, raw_elf)
+//             else
+//                 raw_elf;
+//         }
+//         return firmware.emitted_elf.?;
+//     }
+
+//     /// Returns the emitted binary for this firmware. The file is either in the preferred file format for
+//     /// the target or in `format` if not null.
+//     ///
+//     /// **NOTE:** The file returned here is the same file that will be installed.
+//     pub fn getEmittedBin(firmware: *Firmware, format: ?BinaryFormat) std.Build.LazyPath {
+//         const actual_format = firmware.resolveFormat(format);
+
+//         const gop = firmware.output_files.getOrPut(actual_format) catch @panic("out of memory");
+//         if (!gop.found_existing) {
+//             const elf_file = firmware.getEmittedElf();
+
+//             const basename = firmware.host_build.fmt("{s}{s}", .{
+//                 firmware.artifact.name,
+//                 actual_format.getExtension(),
+//             });
+
+//             gop.value_ptr.* = switch (actual_format) {
+//                 .elf => elf_file,
+
+//                 .bin => blk: {
+//                     const objcopy = firmware.host_build.addObjCopy(elf_file, .{
+//                         .basename = basename,
+//                         .format = .bin,
+//                     });
+
+//                     break :blk objcopy.getOutput();
+//                 },
+
+//                 .hex => blk: {
+//                     const objcopy = firmware.host_build.addObjCopy(elf_file, .{
+//                         .basename = basename,
+//                         .format = .hex,
+//                     });
+
+//                     break :blk objcopy.getOutput();
+//                 },
+
+//                 .uf2 => |family_id| blk: {
+//                     const uf2_exe = firmware.mz.dependency("uf2", .{ .optimize = .ReleaseSafe }).artifact("elf2uf2");
+
+//                     const convert = firmware.host_build.addRunArtifact(uf2_exe);
+
+//                     convert.addArg("--family-id");
+//                     convert.addArg(firmware.host_build.fmt("0x{X:0>4}", .{@intFromEnum(family_id)}));
+
+//                     convert.addArg("--elf-path");
+//                     convert.addFileArg(elf_file);
+
+//                     convert.addArg("--output-path");
+//                     break :blk convert.addOutputFileArg(basename);
+//                 },
+
+//                 .dfu => buildConfigError(firmware.host_build, "DFU is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/145 for more details!", .{}),
+//                 .esp => buildConfigError(firmware.host_build, "ESP firmware image is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/146 for more details!", .{}),
+
+//                 .custom => |generator| generator.convert(generator, elf_file),
+//             };
+//         }
+//         return gop.value_ptr.*;
+//     }
+
+//     pub const AppDependencyOptions = struct {
+//         depend_on_microzig: bool = false,
+//     };
+
+//     /// Adds a regular dependency to your application.
+//     pub fn addAppDependency(fw: *Firmware, name: []const u8, module: *std.Build.Module, options: AppDependencyOptions) void {
+//         if (options.depend_on_microzig) {
+//             module.dependencies.put("microzig", fw.modules.microzig) catch @panic("OOM");
+//         }
+//         fw.modules.app.dependencies.put(name, module) catch @panic("OOM");
+//     }
+
+//     pub fn addIncludePath(fw: *Firmware, path: std.Build.LazyPath) void {
+//         fw.artifact.addIncludePath(path);
+//     }
+
+//     pub fn addSystemIncludePath(fw: *Firmware, path: std.Build.LazyPath) void {
+//         fw.artifact.addSystemIncludePath(path);
+//     }
+
+//     pub fn addCSourceFile(fw: *Firmware, source: std.Build.Step.Compile.CSourceFile) void {
+//         fw.artifact.addCSourceFile(source);
+//     }
+
+//     pub fn addOptions(fw: *Firmware, module_name: []const u8, options: *std.Build.OptionsStep) void {
+//         fw.artifact.addOptions(module_name, options);
+//         fw.modules.app.dependencies.put(
+//             module_name,
+//             fw.host_build.createModule(.{
+//                 .source_file = options.getOutput(),
+//             }),
+//         ) catch @panic("OOM");
+//     }
+
+//     pub fn addObjectFile(fw: *Firmware, source: std.Build.LazyPath) void {
+//         fw.artifact.addObjectFile(source);
+//     }
+
+//     fn resolveFormat(firmware: *Firmware, format: ?BinaryFormat) BinaryFormat {
+//         if (format) |fmt| return fmt;
+
+//         if (firmware.target.preferred_format) |fmt| return fmt;
+
+//         buildConfigError(firmware.host_build, "{s} has no preferred output format, please provide one in the `format` option.", .{
+//             firmware.target.chip.name,
+//         });
+//     }
+// };
 
 pub const cpus = struct {
-    pub const avr5 = Cpu{
+    pub const avr5 = microbuild.Cpu{
         .name = "AVR5",
         .source_file = .{ .path = build_root ++ "/src/cpus/avr5.zig" },
         .target = std.zig.CrossTarget{
@@ -786,7 +788,7 @@ pub const cpus = struct {
         },
     };
 
-    pub const cortex_m0 = Cpu{
+    pub const cortex_m0 = microbuild.Cpu{
         .name = "ARM Cortex-M0",
         .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
         .target = std.zig.CrossTarget{
@@ -797,7 +799,7 @@ pub const cpus = struct {
         },
     };
 
-    pub const cortex_m0plus = Cpu{
+    pub const cortex_m0plus = microbuild.Cpu{
         .name = "ARM Cortex-M0+",
         .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
         .target = std.zig.CrossTarget{
@@ -808,7 +810,7 @@ pub const cpus = struct {
         },
     };
 
-    pub const cortex_m3 = Cpu{
+    pub const cortex_m3 = microbuild.Cpu{
         .name = "ARM Cortex-M3",
         .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
         .target = std.zig.CrossTarget{
@@ -819,7 +821,7 @@ pub const cpus = struct {
         },
     };
 
-    pub const cortex_m4 = Cpu{
+    pub const cortex_m4 = microbuild.Cpu{
         .name = "ARM Cortex-M4",
         .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
         .target = std.zig.CrossTarget{
@@ -830,7 +832,7 @@ pub const cpus = struct {
         },
     };
 
-    pub const riscv32_imac = Cpu{
+    pub const riscv32_imac = microbuild.Cpu{
         .name = "RISC-V 32-bit",
         .source_file = .{ .path = build_root ++ "/src/cpus/riscv32.zig" },
         .target = std.zig.CrossTarget{
@@ -842,138 +844,138 @@ pub const cpus = struct {
     };
 };
 
-fn buildConfigError(b: *std.Build, comptime fmt: []const u8, args: anytype) noreturn {
-    const msg = b.fmt(fmt, args);
-    @panic(msg);
-}
-
-fn dependency(mz: *MicroZig, name: []const u8, args: anytype) *std.Build.Dependency {
-    return mz.self.builder.dependency(name, args);
-}
-
-fn generateLinkerScript(b: *std.Build, chip: Chip) !std.Build.LazyPath {
-    const cpu = chip.cpu.getDescriptor();
-
-    var contents = std.ArrayList(u8).init(b.allocator);
-    const writer = contents.writer();
-    try writer.print(
-        \\/*
-        \\ * This file was auto-generated by microzig
-        \\ *
-        \\ * Target CPU:  {[cpu]s}
-        \\ * Target Chip: {[chip]s}
-        \\ */
-        \\
-        // This is not the "true" entry point, but there's no such thing on embedded platforms
-        // anyways. This is the logical entrypoint that should be invoked when
-        // stack, .data and .bss are set up and the CPU is ready to be used.
-        \\ENTRY(microzig_main);
-        \\
-        \\
-    , .{
-        .cpu = cpu.name,
-        .chip = chip.name,
-    });
-
-    try writer.writeAll("MEMORY\n{\n");
-    {
-        var counters = [4]usize{ 0, 0, 0, 0 };
-        for (chip.memory_regions) |region| {
-            // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k
-
-            switch (region.kind) {
-                .flash => {
-                    try writer.print("  flash{d}    (rx!w)", .{counters[0]});
-                    counters[0] += 1;
-                },
-
-                .ram => {
-                    try writer.print("  ram{d}      (rw!x)", .{counters[1]});
-                    counters[1] += 1;
-                },
-
-                .io => {
-                    try writer.print("  io{d}       (rw!x)", .{counters[2]});
-                    counters[2] += 1;
-                },
-
-                .reserved => {
-                    try writer.print("  reserved{d} (rw!x)", .{counters[3]});
-                    counters[3] += 1;
-                },
-
-                .private => |custom| {
-                    try writer.print("  {s} (", .{custom.name});
-                    if (custom.readable) try writer.writeAll("r");
-                    if (custom.writeable) try writer.writeAll("w");
-                    if (custom.executable) try writer.writeAll("x");
-
-                    if (!custom.readable or !custom.writeable or !custom.executable) {
-                        try writer.writeAll("!");
-                        if (!custom.readable) try writer.writeAll("r");
-                        if (!custom.writeable) try writer.writeAll("w");
-                        if (!custom.executable) try writer.writeAll("x");
-                    }
-                    try writer.writeAll(")");
-                },
-            }
-            try writer.print(" : ORIGIN = 0x{X:0>8}, LENGTH = 0x{X:0>8}\n", .{ region.offset, region.length });
-        }
-    }
-
-    try writer.writeAll("}\n\nSECTIONS\n{\n");
-    {
-        try writer.writeAll(
-            \\  .text :
-            \\  {
-            \\     KEEP(*(microzig_flash_start))
-            \\     *(.text*)
-            \\  } > flash0
-            \\
-            \\
-        );
-
-        switch (cpu.target.getCpuArch()) {
-            .arm, .thumb => try writer.writeAll(
-                \\  .ARM.exidx : {
-                \\      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-                \\  } >flash0
-                \\
-                \\
-            ),
-            else => {},
-        }
-
-        try writer.writeAll(
-            \\  .data :
-            \\  {
-            \\     microzig_data_start = .;
-            \\     *(.rodata*)
-            \\     *(.data*)
-            \\     microzig_data_end = .;
-            \\  } > ram0 AT> flash0
-            \\
-            \\  .bss (NOLOAD) :
-            \\  {
-            \\      microzig_bss_start = .;
-            \\      *(.bss*)
-            \\      microzig_bss_end = .;
-            \\  } > ram0
-            \\
-            \\  microzig_data_load_start = LOADADDR(.data);
-            \\
-        );
-    }
-    try writer.writeAll("}\n");
-
-    // TODO: Assert that the flash can actually hold all data!
-    // try writer.writeAll(
-    //     \\
-    //     \\  ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" );
-    //     \\
-    // );
-
-    const write = b.addWriteFiles();
-
-    return write.add("linker.ld", contents.items);
-}
+// fn buildConfigError(b: *std.Build, comptime fmt: []const u8, args: anytype) noreturn {
+//     const msg = b.fmt(fmt, args);
+//     @panic(msg);
+// }
+
+// fn dependency(mz: *MicroZig, name: []const u8, args: anytype) *std.Build.Dependency {
+//     return mz.self.builder.dependency(name, args);
+// }
+
+// fn generateLinkerScript(b: *std.Build, chip: Chip) !std.Build.LazyPath {
+//     const cpu = chip.cpu.getDescriptor();
+
+//     var contents = std.ArrayList(u8).init(b.allocator);
+//     const writer = contents.writer();
+//     try writer.print(
+//         \\/*
+//         \\ * This file was auto-generated by microzig
+//         \\ *
+//         \\ * Target CPU:  {[cpu]s}
+//         \\ * Target Chip: {[chip]s}
+//         \\ */
+//         \\
+//         // This is not the "true" entry point, but there's no such thing on embedded platforms
+//         // anyways. This is the logical entrypoint that should be invoked when
+//         // stack, .data and .bss are set up and the CPU is ready to be used.
+//         \\ENTRY(microzig_main);
+//         \\
+//         \\
+//     , .{
+//         .cpu = cpu.name,
+//         .chip = chip.name,
+//     });
+
+//     try writer.writeAll("MEMORY\n{\n");
+//     {
+//         var counters = [4]usize{ 0, 0, 0, 0 };
+//         for (chip.memory_regions) |region| {
+//             // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k
+
+//             switch (region.kind) {
+//                 .flash => {
+//                     try writer.print("  flash{d}    (rx!w)", .{counters[0]});
+//                     counters[0] += 1;
+//                 },
+
+//                 .ram => {
+//                     try writer.print("  ram{d}      (rw!x)", .{counters[1]});
+//                     counters[1] += 1;
+//                 },
+
+//                 .io => {
+//                     try writer.print("  io{d}       (rw!x)", .{counters[2]});
+//                     counters[2] += 1;
+//                 },
+
+//                 .reserved => {
+//                     try writer.print("  reserved{d} (rw!x)", .{counters[3]});
+//                     counters[3] += 1;
+//                 },
+
+//                 .private => |custom| {
+//                     try writer.print("  {s} (", .{custom.name});
+//                     if (custom.readable) try writer.writeAll("r");
+//                     if (custom.writeable) try writer.writeAll("w");
+//                     if (custom.executable) try writer.writeAll("x");
+
+//                     if (!custom.readable or !custom.writeable or !custom.executable) {
+//                         try writer.writeAll("!");
+//                         if (!custom.readable) try writer.writeAll("r");
+//                         if (!custom.writeable) try writer.writeAll("w");
+//                         if (!custom.executable) try writer.writeAll("x");
+//                     }
+//                     try writer.writeAll(")");
+//                 },
+//             }
+//             try writer.print(" : ORIGIN = 0x{X:0>8}, LENGTH = 0x{X:0>8}\n", .{ region.offset, region.length });
+//         }
+//     }
+
+//     try writer.writeAll("}\n\nSECTIONS\n{\n");
+//     {
+//         try writer.writeAll(
+//             \\  .text :
+//             \\  {
+//             \\     KEEP(*(microzig_flash_start))
+//             \\     *(.text*)
+//             \\  } > flash0
+//             \\
+//             \\
+//         );
+
+//         switch (cpu.target.getCpuArch()) {
+//             .arm, .thumb => try writer.writeAll(
+//                 \\  .ARM.exidx : {
+//                 \\      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+//                 \\  } >flash0
+//                 \\
+//                 \\
+//             ),
+//             else => {},
+//         }
+
+//         try writer.writeAll(
+//             \\  .data :
+//             \\  {
+//             \\     microzig_data_start = .;
+//             \\     *(.rodata*)
+//             \\     *(.data*)
+//             \\     microzig_data_end = .;
+//             \\  } > ram0 AT> flash0
+//             \\
+//             \\  .bss (NOLOAD) :
+//             \\  {
+//             \\      microzig_bss_start = .;
+//             \\      *(.bss*)
+//             \\      microzig_bss_end = .;
+//             \\  } > ram0
+//             \\
+//             \\  microzig_data_load_start = LOADADDR(.data);
+//             \\
+//         );
+//     }
+//     try writer.writeAll("}\n");
+
+//     // TODO: Assert that the flash can actually hold all data!
+//     // try writer.writeAll(
+//     //     \\
+//     //     \\  ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" );
+//     //     \\
+//     // );
+
+//     const write = b.addWriteFiles();
+
+//     return write.add("linker.ld", contents.items);
+// }
diff --git a/examples/build.zig b/examples/build.zig
new file mode 100644
index 000000000..bd3f69f7b
--- /dev/null
+++ b/examples/build.zig
@@ -0,0 +1,28 @@
+const std = @import("std");
+const MicroZig = @import("../build/build.zig"); // "microzig-build"
+
+pub fn build(b: *std.Build) void {
+    const microzig = MicroZig.createBuildEnvironment(b, .{
+        .self = "microzig", // package name of the build package (optional)
+        .core = "microzig-core", // package name of the core package (optional)
+        .board_support = &.{
+            // package names for BSP packages:
+            "microzig-bsp-nxp",
+            "microzig-bsp-rp2040",
+        },
+    });
+
+    const optimize = b.standardOptimizeOption(.{});
+    const target_name = b.option([]const u8, "target", "Select the target to build for.") orelse "board:mbed/lpc1768";
+
+    const target = microzig.findTarget(target_name).?;
+
+    const firmware = microzig.addFirmware(b, .{
+        .name = "blinky",
+        .target = target,
+        .optimize = optimize,
+        .source_file = .{ .path = "src/empty.zig" },
+    });
+
+    microzig.installFirmware(b, firmware, .{});
+}
diff --git a/examples/modular/README.md b/examples/modular/README.md
deleted file mode 100644
index 7909f7c4c..000000000
--- a/examples/modular/README.md
+++ /dev/null
@@ -1,5 +0,0 @@
-# Examples for the BSP `nxp-lpc`
-
-- [Blinky](src/blinky.zig) on [nRF52840 Dongle](https://www.nordicsemi.com/Products/Development-hardware/nrf52840-dongle)  
-  TODO: Implement this!
-
diff --git a/examples/modular/build.zig b/examples/modular/build.zig
deleted file mode 100644
index f58e4a8eb..000000000
--- a/examples/modular/build.zig
+++ /dev/null
@@ -1,33 +0,0 @@
-const std = @import("std");
-const microzig_build = @import("microzig-build");
-const lpc = @import("lpc");
-
-pub fn build(b: *std.Build) void {
-    const microbuild = microzig_build.init(
-        b,
-        b.dependency("microzig", .{}),
-    );
-
-    const optimize = b.standardOptimizeOption(.{});
-
-    // `addFirmware` basically works like addExecutable, but takes a
-    // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
-    //
-    // The target will convey all necessary information on the chip,
-    // cpu and potentially the board as well.
-    const firmware = microbuild.addFirmware(b, .{
-        .name = "blinky",
-        .target = lpc.boards.mbed.lpc1768,
-        .optimize = optimize,
-        .source_file = .{ .path = "src/blinky.zig" },
-    });
-
-    // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
-    // and allows installing the firmware as a typical firmware file.
-    //
-    // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
-    microbuild.installFirmware(b, firmware, .{});
-
-    // For debugging, we also always install the firmware as an ELF file
-    microbuild.installFirmware(b, firmware, .{ .format = .elf });
-}
diff --git a/examples/modular/build.zig.zon b/examples/modular/build.zig.zon
deleted file mode 100644
index aa5a11a05..000000000
--- a/examples/modular/build.zig.zon
+++ /dev/null
@@ -1,14 +0,0 @@
-.{
-    .name = "microzig-nxp-lpc-examples",
-    .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
-            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
-        },
-        .lpc = .{
-            .url = "https://github.com/ZigEmbeddedGroup/nxp-lpc/archive/130a1316c0892415e7da958a5e9548ed87bba54d.tar.gz",
-            .hash = "1220165879f85a1d51656d35b3963a95f3585dc665fc7414f76aa6aad4e6635536cf",
-        },
-    },
-}
diff --git a/examples/modular/src/blinky.zig b/examples/modular/src/blinky.zig
deleted file mode 100644
index 328d63705..000000000
--- a/examples/modular/src/blinky.zig
+++ /dev/null
@@ -1,56 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-const chip = microzig.chip;
-
-// LED-1: P1.18
-// LED-2: P1.20
-// LED-3: P1.21
-// LED-4: P1.23
-
-const conn = chip.peripherals.PINCONNECT;
-const gpio: *volatile [5]PatchedGpio = @ptrCast(@alignCast(chip.peripherals.GPIO));
-
-const led_mask = [4]u32{
-    (1 << 18),
-    (1 << 20),
-    (1 << 21),
-    (1 << 23),
-};
-const all_mask = led_mask[0] | led_mask[1] | led_mask[2] | led_mask[3];
-
-pub fn main() !void {
-    conn.PINSEL3.modify(.{
-        .P1_18 = .{ .value = .GPIO_P1 },
-        .P1_20 = .{ .value = .GPIO_P1 },
-        .P1_21 = .{ .value = .GPIO_P1 },
-        .P1_23 = .{ .value = .GPIO_P1 },
-    });
-
-    const p1 = &gpio[1];
-
-    p1.dir = all_mask;
-
-    while (true) {
-        for (led_mask) |mask| {
-            p1.pin_clr = (all_mask & ~mask);
-            p1.pin_set = mask;
-            microzig.core.experimental.debug.busy_sleep(100_000);
-        }
-    }
-}
-
-const PatchedGpio = extern struct {
-    dir: u32, // 0x2009 C000
-    __padding0: u32, // 0x2009 C004
-    __padding1: u32, // 0x2009 C008
-    __padding2: u32, // 0x2009 C00C
-    mask: u32, // 0x2009 C010
-    pin: u32, // 0x2009 C014
-    pin_set: u32, // 0x2009 C018
-    pin_clr: u32, // 0x2009 C01C
-
-    comptime {
-        std.debug.assert(@sizeOf(PatchedGpio) == 0x20);
-    }
-};
diff --git a/examples/next-gen/build.zig b/examples/next-gen/build.zig
new file mode 100644
index 000000000..37628be1a
--- /dev/null
+++ b/examples/next-gen/build.zig
@@ -0,0 +1,32 @@
+const std = @import("std");
+const MicroZig = @import("microzig");
+
+pub fn build(b: *std.Build) void {
+    const microzig = MicroZig.createBuildEnvironment(b, .{
+        .self = "microzig", // package name of the build package (optional)
+        .core = "microzig-core", // package name of the core package (optional)
+        .board_support = &.{
+            // package names for BSP packages:
+            "microzig-bsp-nxp",
+            "microzig-bsp-rp2040",
+        },
+    });
+
+    const optimize = b.standardOptimizeOption(.{});
+    const target_name = b.option([]const u8, "target", "Select the target to build for.") orelse "board:mbed/lpc1768";
+
+    for (microzig.targets.keys()) |listed_target_name| {
+        std.debug.print("- '{s}'\n", .{listed_target_name});
+    }
+
+    const target = microzig.findTarget(target_name).?;
+
+    const firmware = microzig.addFirmware(b, .{
+        .name = "blinky",
+        .target = target,
+        .optimize = optimize,
+        .source_file = .{ .path = "src/empty.zig" },
+    });
+
+    microzig.installFirmware(b, firmware, .{});
+}
diff --git a/examples/next-gen/build.zig.zon b/examples/next-gen/build.zig.zon
new file mode 100644
index 000000000..f9d6f771a
--- /dev/null
+++ b/examples/next-gen/build.zig.zon
@@ -0,0 +1,22 @@
+.{
+    .name = "microzig-nxp-lpc-examples",
+    .version = "0.1.0",
+    .dependencies = .{
+        .microzig = .{
+            .url = "https://public.devspace.random-projects.net/microzig-build.tar.gz",
+            .hash = "122068db50e2a071cac3fc5b42d5cd2213ccb563986af60b941cb7af29b83df65b02",
+        },
+        .@"microzig-core" = .{
+            .url = "https://public.devspace.random-projects.net/microzig-core.tar.gz",
+            .hash = "12202df033d2b967108b25b8e66d8c8abcf690348a24baa35474a28086170ff31e54",
+        },
+        .@"microzig-bsp-nxp" = .{
+            .url = "https://public.devspace.random-projects.net/board-support/nxp/lpc.tar.gz",
+            .hash = "12201efd8d8b992caef770c87d78e6bd00bd73051bd1559bc342703f2e83650ef2f9",
+        },
+        .@"microzig-bsp-rp2040" = .{
+            .url = "https://public.devspace.random-projects.net/board-support/raspberrypi/rp2040.tar.gz",
+            .hash = "1220154cd3634d0f3286cd2fb727cce9af3f3ab166772065e3efe4f9577128f4c559",
+        },
+    },
+}
\ No newline at end of file
diff --git a/examples/next-gen/src/empty.zig b/examples/next-gen/src/empty.zig
new file mode 100644
index 000000000..b2925389e
--- /dev/null
+++ b/examples/next-gen/src/empty.zig
@@ -0,0 +1,8 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+pub fn main() !void {
+    while (true) {
+        asm volatile ("" ::: "memory");
+    }
+}
diff --git a/tools/archive-info.zig b/tools/archive-info.zig
index 33f8496d5..034be0d6c 100644
--- a/tools/archive-info.zig
+++ b/tools/archive-info.zig
@@ -46,7 +46,7 @@ pub fn main() !void {
     // defer decompress.deinit();
 
     var arc = try Archive.read_from_tar(arena, buffered.reader(), .{
-        .strip_components = 0,
+        .strip_components = 1,
     });
     defer arc.deinit(arena);
 
@@ -57,7 +57,23 @@ pub fn main() !void {
         try paths.appendSlice(arc.files.keys());
         std.mem.sort([]const u8, paths.items, {}, Archive.path_less_than);
 
-        const calculated_hash = try arc.hash(allocator, .ignore_executable_bit);
+        const calculated_hash = blk: {
+            var arc_hasher = Hash.init(.{});
+
+            for (paths.items) |path| {
+                const archived_file = arc.files.getPtr(path).?;
+
+                var file_hasher = Hash.init(.{});
+                file_hasher.update(path);
+                file_hasher.update(&.{ 0, 0 }); // second part is "executable bit"
+                file_hasher.update(archived_file.text);
+
+                arc_hasher.update(&file_hasher.finalResult());
+            }
+
+            break :blk arc_hasher.finalResult();
+        };
+
         var hash_buf: [4 + 2 * calculated_hash.len]u8 = undefined;
         const hash_str = try std.fmt.bufPrint(&hash_buf, "1220{}", .{std.fmt.fmtSliceHexLower(&calculated_hash)});
 
@@ -92,13 +108,13 @@ const Archive = struct {
         return if (mod > 0) 512 - mod else 0;
     }
 
-    pub fn entry_should_be_skipped(path: []const u8) !bool {
-        var it = try std.fs.path.componentIterator(path);
-        const first = it.next().?;
-        return std.mem.eql(u8, first.name, ".git") or
-            std.mem.eql(u8, first.name, "zig-out") or
-            std.mem.eql(u8, first.name, "zig-cache");
-    }
+    // pub fn entry_should_be_skipped(path: []const u8) !bool {
+    //     var it = try std.fs.path.componentIterator(path);
+    //     const first = it.next().?;
+    //     return std.mem.eql(u8, first.name, ".git") or
+    //         std.mem.eql(u8, first.name, "zig-out") or
+    //         std.mem.eql(u8, first.name, "zig-cache");
+    // }
 
     fn stripComponents(path: []const u8, count: u32) ![]const u8 {
         var i: usize = 0;
@@ -240,35 +256,4 @@ const Archive = struct {
             return (mode & std.os.S.IXUSR) != 0;
         }
     }
-
-    pub fn hash(
-        archive: Archive,
-        allocator: Allocator,
-        executable_bit: WhatToDoWithExecutableBit,
-    ) ![Hash.digest_length]u8 {
-        var paths = std.ArrayList([]const u8).init(allocator);
-        defer paths.deinit();
-
-        var hashes = std.ArrayList([Hash.digest_length]u8).init(allocator);
-        defer hashes.deinit();
-
-        try paths.appendSlice(archive.files.keys());
-        try hashes.appendNTimes(undefined, paths.items.len);
-        std.mem.sort([]const u8, paths.items, {}, path_less_than);
-
-        for (paths.items, hashes.items) |path, *result| {
-            const file = archive.files.get(path).?;
-            var hasher = Hash.init(.{});
-            hasher.update(path);
-            hasher.update(&.{ 0, @intFromBool(is_executable(file.mode, executable_bit)) });
-            hasher.update(file.text);
-            hasher.final(result);
-        }
-
-        var hasher = Hash.init(.{});
-        for (hashes.items) |file_hash|
-            hasher.update(&file_hash);
-
-        return hasher.finalResult();
-    }
 };
diff --git a/tools/bundle.py b/tools/bundle.py
index 47761c10c..e00cda07f 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -16,6 +16,8 @@
 from enum import Enum as StrEnum
 import pathspec
 import stat 
+import tarfile
+
 from marshmallow import fields as mm_fields
 from typing import Optional, Any
 
@@ -26,7 +28,8 @@
     "zig",
     "git",
 ]
-DEPLOYMENT_BASE="https://download.microzig.tech/packages"
+# DEPLOYMENT_BASE="https://download.microzig.tech/packages"
+DEPLOYMENT_BASE="https://public.devspace.random-projects.net"
 
 REPO_ROOT = Path(__file__).parent.parent
 assert REPO_ROOT.is_dir()
@@ -300,13 +303,17 @@ def main():
         pkg.package_dir = pkg_dir
 
 
-        if pkg.package_type == PackageType.core:
+
+        if pkg.package_type == PackageType.build:
             pkg.out_rel_dir = PurePosixPath(".")
             pkg.out_basename = pkg.package_name
-
-        elif pkg.package_type == PackageType.build:
+            
+        elif pkg.package_type == PackageType.core:
             pkg.out_rel_dir = PurePosixPath(".")
             pkg.out_basename = pkg.package_name
+            
+            # Implicit dependencies:
+            pkg.inner_dependencies.add("microzig-build") # core requires the build types
 
         elif pkg.package_type == PackageType.board_support:
             parsed_pkg_name = PurePosixPath(pkg.package_name)
@@ -314,7 +321,9 @@ def main():
             pkg.out_rel_dir = "board-support" / parsed_pkg_name.parent
             pkg.out_basename = parsed_pkg_name.name
 
-            pkg.inner_dependencies.add("microzig-core") # BSPs implicitly depend on the core "microzig" package
+            # Implicit dependencies:
+            pkg.inner_dependencies.add("microzig-build") # BSPs also require build types
+            pkg.inner_dependencies.add("microzig-core") # but also the core types (?)
         else:
             assert False 
 
@@ -373,7 +382,7 @@ def main():
         pkg_cache_dir.mkdir(exist_ok=True)
         
         meta_path = pkg_dir / "microzig-package.json"
-        pkg_zon_file = pkg_cache_dir / "build.zig.zon" 
+        pkg_zon_file = pkg_cache_dir / pkg_dir.name / "build.zig.zon" 
 
         out_rel_dir: PurePosixPath = pkg.out_rel_dir
         out_basename: str = pkg.out_basename
@@ -383,9 +392,9 @@ def main():
                 "zig", "build-exe",
                     f"{REPO_ROOT}/tools/extract-bsp-info.zig" ,
                     "--cache-dir", f"{REPO_ROOT}/zig-cache",
-                    "--deps", "bsp,microzig",
-                    "--mod", f"bsp:microzig:{pkg_dir}/build.zig",
-                    "--mod", f"microzig:uf2:{REPO_ROOT}/core/build.zig",
+                    "--deps", "bsp,microzig-build",
+                    "--mod", f"bsp:microzig-build:{pkg_dir}/build.zig",
+                    "--mod", f"microzig-build:uf2:{REPO_ROOT}/build/build.zig",
                     "--mod", f"uf2::{REPO_ROOT}/tools/lib/dummy_uf2.zig",
                     "--name", "extract-bsp-info",
                 cwd=pkg_cache_dir,
@@ -440,7 +449,8 @@ def main():
             print()
 
         # tar -cf "${out_tar}" $(git ls-files -- . ':!:microzig-package.json')
-        execute("tar", "-cf", out_file_tar, "--hard-dereference", *package_files, cwd=pkg_dir)
+
+        execute("tar", "-cf", out_file_tar, "--hard-dereference", *( f"{pkg_dir.name}/{file}" for file in package_files), cwd=pkg_dir.parent)
 
         zon_data = slurp(
             tools["create_pkg_descriptor"],
@@ -448,12 +458,14 @@ def main():
             input=PackageConfigurationSchema.dumps(evaluation_ordered_packages, many=True ).encode(),
         )
 
+        pkg_zon_file.parent.mkdir(exist_ok=True)
+
         with pkg_zon_file.open("wb") as f:
             f.write(zon_data)
 
         slurp("zig", "fmt", pkg_zon_file) # slurp the message away
 
-        execute("tar", "-rf", out_file_tar, "--hard-dereference", pkg_zon_file.name, cwd=pkg_zon_file.parent)
+        execute("tar", "-rf", out_file_tar, "--hard-dereference", f"{pkg_zon_file.parent.name}/{pkg_zon_file.name}", cwd=pkg_zon_file.parent.parent)
 
         # tar --list --file "${out_tar}" > "${pkg_cache_dir}/contents.list"
         
diff --git a/tools/create-pkg-descriptor.zig b/tools/create-pkg-descriptor.zig
index d41abeb61..70985d8bc 100644
--- a/tools/create-pkg-descriptor.zig
+++ b/tools/create-pkg-descriptor.zig
@@ -127,7 +127,7 @@ pub fn main() !void {
 
             try renderDep(
                 stdout,
-                "microzig",
+                dep_name,
                 dep.download_url.?,
                 dep.package.?.hash,
             );
diff --git a/tools/extract-bsp-info.zig b/tools/extract-bsp-info.zig
index 9d83f7db5..b0f562732 100644
--- a/tools/extract-bsp-info.zig
+++ b/tools/extract-bsp-info.zig
@@ -5,7 +5,7 @@
 
 const std = @import("std");
 const bsp = @import("bsp");
-const microzig = @import("microzig");
+const microzig = @import("microzig-build");
 
 const JsonTarget = struct {
     id: []const u8,
diff --git a/tools/patch-build-zon.py b/tools/patch-build-zon.py
new file mode 100755
index 000000000..85cc96264
--- /dev/null
+++ b/tools/patch-build-zon.py
@@ -0,0 +1,74 @@
+#!/usr/bin/env python3
+#
+# Hacky auto-patcher to update dependencies in examples.
+#
+# Receives a **formatted(!)** build.zig.zon that requires ".url" and ".hash" to be written in that order on different lines.
+#
+
+import sys
+import json
+from urllib.parse import urlparse, urlunparse
+from urllib.request import urlopen
+from pathlib import Path, PurePosixPath
+import re 
+
+
+def main():
+
+    build_zig_zon = Path(sys.argv[1])
+    assert build_zig_zon.is_file()
+
+    input_lines = build_zig_zon.read_text().splitlines()
+
+    output_lines = []
+
+    last_pkg_url: urllib.parse.ParseResult = None
+    for line in input_lines:
+
+        stripped = line.strip()
+        if stripped.startswith(".url = \""):
+            
+            match = re.match('\s*\.url\s*=\s*"([^"]+)",', line)
+            
+            urlstr = match.group(1)
+
+            last_pkg_url = urlparse(urlstr)
+
+            output_lines.append(line)
+
+        elif stripped.startswith(".hash = \""):
+            try:
+                pkg_path = PurePosixPath(last_pkg_url.path)
+                assert pkg_path.suffixes ==  ['.tar', '.gz']
+                pkg_json_url = urlunparse(
+                    # scheme, netloc, url, params, query, fragment
+                    (
+                        last_pkg_url.scheme,  # scheme
+                        last_pkg_url.netloc, # netloc
+                        pkg_path.with_suffix("").with_suffix(".json").as_posix(), # url
+                        last_pkg_url.params, # params
+                        last_pkg_url.query, # query
+                        last_pkg_url.fragment, # fragment
+                    )
+                )
+                
+                metadata = json.loads(urlopen(pkg_json_url).read())
+
+                pkg_hash = metadata["package"]["hash"]
+
+                line_prefix = re.match("^(\s*)", line).group(1)
+
+                output_lines.append(f'{line_prefix}.hash = "{pkg_hash}",')
+                last_pkg_url = None 
+                
+
+            except BaseException as ex:
+                print(ex)
+                output_lines.append(line)
+        else:
+            output_lines.append(line)
+    
+    build_zig_zon.write_text("\n".join(output_lines))
+
+if __name__ == "__main__":
+    main()
\ No newline at end of file

From 99e8d09cf0a7e17ff04ba2958f0f3fd5aefb597e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 20 Jan 2024 12:23:41 +0100
Subject: [PATCH 261/286] Adds auto-discovery of BSPs.

---
 board-support/espressif-esp/build.zig      |   5 +-
 board-support/gigadevice-gd32/build.zig    |   9 +-
 board-support/microchip-atsam/build.zig    |   5 +-
 board-support/microchip-avr/build.zig      |   9 +-
 board-support/nordic-nrf5x/build.zig       |   2 +
 board-support/nxp-lpc/build.zig            |   2 +
 board-support/raspberrypi-rp2040/build.zig |   2 +
 board-support/stmicro-stm32/build.zig      |  32 +-
 build/build.zig                            | 205 +++--
 core/build.zig                             | 837 ---------------------
 examples/next-gen/build.zig                |   5 -
 examples/next-gen/build.zig.zon            |   8 +-
 tools/extract-bsp-info.zig                 |  29 +-
 13 files changed, 193 insertions(+), 957 deletions(-)

diff --git a/board-support/espressif-esp/build.zig b/board-support/espressif-esp/build.zig
index d1b62ccf5..ebc95c749 100644
--- a/board-support/espressif-esp/build.zig
+++ b/board-support/espressif-esp/build.zig
@@ -1,4 +1,7 @@
 const std = @import("std");
+const MicroZig = @import("microzig-build");
+
+pub const microzig_board_support = MicroZig.registerBoardSupport(@This());
 
 fn path(comptime suffix: []const u8) std.Build.LazyPath {
     return .{
@@ -26,7 +29,7 @@ const hal = .{
 };
 
 pub const chips = struct {
-    pub const esp32_c3 = .{
+    pub const esp32_c3 = MicroZig.Target{
         .preferred_format = .bin, // TODO: Exchange FLAT format with .esp format
         .chip = .{
             .name = "ESP32-C3",
diff --git a/board-support/gigadevice-gd32/build.zig b/board-support/gigadevice-gd32/build.zig
index 61f41a4ca..7b13e1a0e 100644
--- a/board-support/gigadevice-gd32/build.zig
+++ b/board-support/gigadevice-gd32/build.zig
@@ -1,4 +1,7 @@
 const std = @import("std");
+const MicroZig = @import("microzig-build");
+
+pub const microzig_board_support = MicroZig.registerBoardSupport(@This());
 
 fn path(comptime suffix: []const u8) std.Build.LazyPath {
     return .{
@@ -11,7 +14,7 @@ const hal = .{
 };
 
 pub const chips = struct {
-    pub const gd32vf103xb = .{
+    pub const gd32vf103xb = MicroZig.Target{
         .preferred_format = .elf,
         .chip = .{
             .name = "GD32VF103",
@@ -27,7 +30,7 @@ pub const chips = struct {
         .hal = hal,
     };
 
-    pub const gd32vf103x8 = .{
+    pub const gd32vf103x8 = MicroZig.Target{
         .preferred_format = .elf,
         .chip = .{
             .name = "GD32VF103",
@@ -46,7 +49,7 @@ pub const chips = struct {
 
 pub const boards = struct {
     pub const sipeed = struct {
-        pub const longan_nano = .{
+        pub const longan_nano = MicroZig.Target{
             .preferred_format = .elf,
             .chip = chips.gd32vf103xb.chip,
             .hal = hal,
diff --git a/board-support/microchip-atsam/build.zig b/board-support/microchip-atsam/build.zig
index d9dbf958e..77010ee55 100644
--- a/board-support/microchip-atsam/build.zig
+++ b/board-support/microchip-atsam/build.zig
@@ -1,4 +1,7 @@
 const std = @import("std");
+const MicroZig = @import("microzig-build");
+
+pub const microzig_board_support = MicroZig.registerBoardSupport(@This());
 
 pub fn build(b: *std.Build) void {
     _ = b;
@@ -27,7 +30,7 @@ pub const chip_atsamd51j19 = .{
 };
 
 pub const chips = struct {
-    pub const atsamd51j19 = .{
+    pub const atsamd51j19 = MicroZig.Target{
         .preferred_format = .elf,
         .chip = chip_atsamd51j19,
     };
diff --git a/board-support/microchip-avr/build.zig b/board-support/microchip-avr/build.zig
index 19ba0769f..650d54b35 100644
--- a/board-support/microchip-avr/build.zig
+++ b/board-support/microchip-avr/build.zig
@@ -1,4 +1,7 @@
 const std = @import("std");
+const MicroZig = @import("microzig-build");
+
+pub const microzig_board_support = MicroZig.registerBoardSupport(@This());
 
 fn path(comptime suffix: []const u8) std.Build.LazyPath {
     return .{
@@ -11,7 +14,7 @@ const hal = .{
 };
 
 pub const chips = struct {
-    pub const atmega328p = .{
+    pub const atmega328p = MicroZig.Target{
         .preferred_format = .hex,
         .chip = .{
             .name = "ATmega328P",
@@ -31,7 +34,7 @@ pub const chips = struct {
 
 pub const boards = struct {
     pub const arduino = struct {
-        pub const nano = .{
+        pub const nano = MicroZig.Target{
             .preferred_format = .hex,
             .chip = chips.atmega328p.chip,
             .hal = hal,
@@ -42,7 +45,7 @@ pub const boards = struct {
             },
         };
 
-        pub const uno_rev3 = .{
+        pub const uno_rev3 = MicroZig.Target{
             .preferred_format = .hex,
             .chip = chips.atmega328p.chip,
             .hal = hal,
diff --git a/board-support/nordic-nrf5x/build.zig b/board-support/nordic-nrf5x/build.zig
index 9bc2b7882..445bae7b3 100644
--- a/board-support/nordic-nrf5x/build.zig
+++ b/board-support/nordic-nrf5x/build.zig
@@ -1,6 +1,8 @@
 const std = @import("std");
 const MicroZig = @import("microzig-build");
 
+pub const microzig_board_support = MicroZig.registerBoardSupport(@This());
+
 fn path(comptime suffix: []const u8) std.Build.LazyPath {
     return .{
         .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
diff --git a/board-support/nxp-lpc/build.zig b/board-support/nxp-lpc/build.zig
index 5f75d436a..b17678ec8 100644
--- a/board-support/nxp-lpc/build.zig
+++ b/board-support/nxp-lpc/build.zig
@@ -1,6 +1,8 @@
 const std = @import("std");
 const MicroZig = @import("microzig-build");
 
+pub const microzig_board_support = MicroZig.registerBoardSupport(@This());
+
 fn path(comptime suffix: []const u8) std.Build.LazyPath {
     return .{
         .cwd_relative = comptime ((std.fs.path.dirname(@src().file) orelse ".") ++ suffix),
diff --git a/board-support/raspberrypi-rp2040/build.zig b/board-support/raspberrypi-rp2040/build.zig
index 73453f343..3e0d5344d 100644
--- a/board-support/raspberrypi-rp2040/build.zig
+++ b/board-support/raspberrypi-rp2040/build.zig
@@ -1,6 +1,8 @@
 const std = @import("std");
 const microzig = @import("microzig-build");
 
+pub const microzig_board_support = microzig.registerBoardSupport(@This());
+
 fn root() []const u8 {
     return comptime (std.fs.path.dirname(@src().file) orelse ".");
 }
diff --git a/board-support/stmicro-stm32/build.zig b/board-support/stmicro-stm32/build.zig
index 4e0e0d541..b843537c4 100644
--- a/board-support/stmicro-stm32/build.zig
+++ b/board-support/stmicro-stm32/build.zig
@@ -1,5 +1,7 @@
 const std = @import("std");
-const microzig = @import("microzig-build");
+const MicroZig = @import("microzig-build");
+
+pub const microzig_board_support = MicroZig.registerBoardSupport(@This());
 
 fn root() []const u8 {
     return comptime (std.fs.path.dirname(@src().file) orelse ".");
@@ -18,7 +20,7 @@ pub fn build(b: *std.Build) !void {
 }
 
 pub const chips = struct {
-    pub const stm32f103x8 = .{
+    pub const stm32f103x8 = MicroZig.Target{
         .preferred_format = .elf,
         .chip = .{
             .name = "STM32F103",
@@ -36,7 +38,7 @@ pub const chips = struct {
         },
     };
 
-    pub const stm32f303vc = .{
+    pub const stm32f303vc = MicroZig.Target{
         .preferred_format = .elf,
         .chip = .{
             .name = "STM32F303",
@@ -51,7 +53,7 @@ pub const chips = struct {
         },
     };
 
-    pub const stm32f407vg = .{
+    pub const stm32f407vg = MicroZig.Target{
         .preferred_format = .elf,
         .chip = .{
             .name = "STM32F407",
@@ -67,7 +69,7 @@ pub const chips = struct {
         },
     };
 
-    pub const stm32f429zit6u = .{
+    pub const stm32f429zit6u = MicroZig.Target{
         .preferred_format = .elf,
         .chip = .{
             .name = "STM32F429",
@@ -85,8 +87,8 @@ pub const chips = struct {
 
     // All STM32L0x1 series MCUs differ only in memory size. So we create a comptime function
     // to generate all MCU variants as per https://www.st.com/en/microcontrollers-microprocessors/stm32l0x1.html
-    fn stm32l0x1(comptime rom_size: u64, comptime ram_size: u64) microzig.Target {
-        return microzig.Target{
+    fn stm32l0x1(comptime rom_size: u64, comptime ram_size: u64) MicroZig.Target {
+        return MicroZig.Target{
             .preferred_format = .elf,
             .chip = .{
                 .name = "STM32L0x1",
@@ -123,8 +125,8 @@ pub const chips = struct {
 
     // All STM32L0x2 series MCUs differ only in memory size. So we create a comptime function
     // to generate all MCU variants as per https://www.st.com/en/microcontrollers-microprocessors/stm32l0x2.html
-    fn stm32l0x2(comptime rom_size: u64, comptime ram_size: u64) microzig.Target {
-        return microzig.Target{
+    fn stm32l0x2(comptime rom_size: u64, comptime ram_size: u64) MicroZig.Target {
+        return MicroZig.Target{
             .preferred_format = .elf,
             .chip = .{
                 .name = "STM32L0x2",
@@ -154,8 +156,8 @@ pub const chips = struct {
 
     // All STM32L0x2 series MCUs differ only in memory size. So we create a comptime function
     // to generate all MCU variants as per https://www.st.com/en/microcontrollers-microprocessors/stm32l0x3.html
-    fn stm32l0x3(comptime rom_size: u64, comptime ram_size: u64) microzig.Target {
-        return microzig.Target{
+    fn stm32l0x3(comptime rom_size: u64, comptime ram_size: u64) MicroZig.Target {
+        return MicroZig.Target{
             .preferred_format = .elf,
             .chip = .{
                 .name = "STM32L0x3",
@@ -187,7 +189,7 @@ pub const chips = struct {
 };
 
 pub const boards = struct {
-    pub const stm32f3discovery = .{
+    pub const stm32f3discovery = MicroZig.Target{
         .preferred_format = .elf,
         .chip = chips.stm32f303vc.chip,
         .board = .{
@@ -196,7 +198,7 @@ pub const boards = struct {
         },
     };
 
-    pub const stm32f4discovery = .{
+    pub const stm32f4discovery = MicroZig.Target{
         .preferred_format = .elf,
         .chip = chips.stm32f407vg.chip,
         .board = .{
@@ -205,7 +207,7 @@ pub const boards = struct {
         },
     };
 
-    pub const stm3240geval = .{
+    pub const stm3240geval = MicroZig.Target{
         .preferred_format = .elf,
         .chip = chips.stm32f407vg.chip,
         .board = .{
@@ -214,7 +216,7 @@ pub const boards = struct {
         },
     };
 
-    pub const stm32f429idiscovery = .{
+    pub const stm32f429idiscovery = MicroZig.Target{
         .preferred_format = .elf,
         .chip = chips.stm32f429zit6u.chip,
         .board = .{
diff --git a/build/build.zig b/build/build.zig
index 2c6df508b..67c16e24b 100644
--- a/build/build.zig
+++ b/build/build.zig
@@ -9,10 +9,131 @@ const uf2 = @import("uf2");
 //      MicroZig Gen 3 Interface      //
 ////////////////////////////////////////
 
-pub const EnvironmentInfo = struct {
-    /// include package names of your board support packages here:
-    board_support: []const []const u8,
+pub const BoardSupportPackageDefinition = struct {
+    pub const TargetDefinition = struct {
+        id: []const u8, // full "uri"
+        target: Target,
+    };
+
+    bsp_root: type,
+    targets: []const TargetDefinition,
+
+    fn init(comptime bsp_root: type) BoardSupportPackageDefinition {
+        var targets: []const TargetDefinition = &.{};
+
+        if (@hasDecl(bsp_root, "chips")) {
+            targets = targets ++ construct_target_database("chip:", bsp_root.chips);
+        }
+
+        if (@hasDecl(bsp_root, "boards")) {
+            targets = targets ++ construct_target_database("board:", bsp_root.boards);
+        }
+
+        if (targets.len == 0) {
+            @compileError("Board support package contains not a single target. Please add at least one target!");
+        }
+
+        return BoardSupportPackageDefinition{
+            .bsp_root = bsp_root,
+            .targets = targets,
+        };
+    }
+
+    fn construct_target_database(comptime prefix: []const u8, comptime namespace: type) []const TargetDefinition {
+        var list: []const TargetDefinition = &.{};
+
+        inline for (@typeInfo(namespace).Struct.decls) |decl_info| {
+            const decl = @field(namespace, decl_info.name);
+            const T = @TypeOf(decl);
+
+            const name = comptime prefix ++ decl_info.name; // board:vendor/name
+
+            if (T == Target) {
+                const target: Target = decl;
+
+                list = list ++ &[_]TargetDefinition{.{
+                    .id = name,
+                    .target = target,
+                }};
+                // be.targets.put(be.host_build.allocator, name, target) catch @panic("out of memory");
+            } else {
+                if (T != type) {
+                    @compileError(std.fmt.comptimePrint("Declaration {s} is neither a MicroZig.Target nor a namespace. Expected declaration to be a 'type', found {s}.", .{
+                        name,
+                        @typeName(T),
+                    }));
+                }
+
+                const ti = @typeInfo(decl);
+                if (ti != .Struct) {
+                    @compileError(std.fmt.comptimePrint("Declaration {s} is neither a MicroZig.Target nor a namespace. Expected declaration to be a 'struct', found {s}.", .{
+                        name,
+                        @tagName(ti),
+                    }));
+                }
+
+                if (ti.Struct.fields.len > 0) {
+                    @compileError(std.fmt.comptimePrint("Declaration {s} is neither a MicroZig.Target nor a namespace. Expected declaration to have no fields, but found {} fields.", .{
+                        name,
+                        ti.Struct.fields.len,
+                    }));
+                }
+
+                const sublist = construct_target_database(
+                    comptime name ++ "/",
+                    decl,
+                );
+
+                list = list ++ sublist;
+            }
+        }
+
+        return list;
+    }
+};
+
+/// Validates a board support package and returns a registration type that can be used
+/// with MicroZig automatic BSP discovery.
+///
+/// Store the return value into a public constant named "" at the root of your build script:
+///
+///     pub const microzig_board_support = microzig.registerBoardSupport(@This());
+///
+pub fn registerBoardSupport(comptime bsp_root: type) BoardSupportPackageDefinition {
+    return BoardSupportPackageDefinition.init(bsp_root);
+}
+
+const ImportedBSP = struct {
+    import_name: []const u8,
+    bsp: BoardSupportPackageDefinition,
+};
+
+fn get_declared_bsps() []const ImportedBSP {
+
+    // Keep in sync with the logic from Build.zig:dependency
+    const build_runner = @import("root");
+    const deps = build_runner.dependencies;
+
+    var bsps: []const ImportedBSP = &.{};
+    inline for (@typeInfo(deps.imports).Struct.decls) |decl| {
+        if (comptime std.mem.indexOfScalar(u8, decl.name, '.') == null) {
+            const maybe_bsp = @field(deps.imports, decl.name);
+
+            if (@hasDecl(maybe_bsp, "microzig_board_support")) {
+                const bsp = @field(maybe_bsp, "microzig_board_support");
+                if (@TypeOf(bsp) == BoardSupportPackageDefinition) {
+                    bsps = bsps ++ [_]ImportedBSP{.{
+                        .import_name = decl.name,
+                        .bsp = bsp,
+                    }};
+                }
+            }
+        }
+    }
+    return bsps;
+}
 
+pub const EnvironmentInfo = struct {
     /// package name of the build package (optional)
     self: []const u8 = "microzig",
 
@@ -21,93 +142,37 @@ pub const EnvironmentInfo = struct {
 };
 
 pub fn createBuildEnvironment(b: *std.Build, comptime info: EnvironmentInfo) *BuildEnvironment {
+    const available_bsps = comptime get_declared_bsps();
+
     const be = b.allocator.create(BuildEnvironment) catch @panic("out of memory");
     be.* = BuildEnvironment{
         .host_build = b,
         .self = undefined,
         .microzig_core = undefined,
-        .board_support_packages = b.allocator.alloc(BoardSupportPackage, info.board_support.len) catch @panic("out of memory"),
+        .board_support_packages = b.allocator.alloc(BoardSupportPackage, available_bsps.len) catch @panic("out of memory"),
         .targets = .{},
     };
 
     be.self = b.dependency(info.self, .{});
     be.microzig_core = b.dependency(info.core, .{});
 
-    for (be.board_support_packages, info.board_support) |*out, in| {
-        out.* = BoardSupportPackage{
-            .name = in,
-            .dep = b.dependency(in, .{}),
+    inline for (be.board_support_packages, available_bsps) |*bsp, def| {
+        bsp.* = BoardSupportPackage{
+            .name = def.import_name,
+            .dep = b.dependency(def.import_name, .{}),
         };
-    }
 
-    // Fetch and collect all supported targets:
-    inline for (info.board_support) |bsp_name| {
-        // Keep in sync with the logic from Build.zig:dependency
-        const build_runner = @import("root");
-        const deps = build_runner.dependencies;
+        for (def.bsp.targets) |tgt| {
+            const full_name = b.fmt("{s}#{s}", .{ tgt.id, def.import_name });
 
-        const bsp_root = @field(deps.imports, bsp_name);
-
-        if (@hasDecl(bsp_root, "chips")) {
-            fetch_microzig_targets("chip:", bsp_root.chips, bsp_name, be);
-        }
-
-        if (@hasDecl(bsp_root, "boards")) {
-            fetch_microzig_targets("board:", bsp_root.boards, bsp_name, be);
+            be.targets.put(be.host_build.allocator, tgt.id, tgt.target) catch @panic("out of memory");
+            be.targets.put(be.host_build.allocator, full_name, tgt.target) catch @panic("out of memory");
         }
     }
 
     return be;
 }
 
-fn fetch_microzig_targets(comptime prefix: []const u8, comptime namespace: type, comptime bsp_name: []const u8, be: *BuildEnvironment) void {
-    inline for (@typeInfo(namespace).Struct.decls) |decl_info| {
-        const decl = @field(namespace, decl_info.name);
-        const T = @TypeOf(decl);
-
-        const name = comptime prefix ++ decl_info.name; // board:vendor/name
-        const full_name = comptime name ++ "#" ++ bsp_name; // board:vendor/name#bsp-package-name
-
-        if (T == Target) {
-            const target: Target = decl;
-
-            be.targets.put(be.host_build.allocator, name, target) catch @panic("out of memory");
-            be.targets.put(be.host_build.allocator, full_name, target) catch @panic("out of memory");
-        } else {
-            const ok = blk: {
-                if (comptime T != type) {
-                    // @compileLog(full_name, "check 1:", T, decl);
-                    break :blk false;
-                }
-
-                const ti = @typeInfo(decl);
-                if (comptime ti != .Struct) {
-                    // @compileLog(full_name, "check 2:", ti);
-                    break :blk false;
-                }
-
-                if (comptime ti.Struct.fields.len > 0) {
-                    // @compileLog(full_name, "check 3:", ti.Struct);
-                    // @compileLog(full_name, "check 3:", ti.Struct.fields);
-                    break :blk false;
-                }
-
-                fetch_microzig_targets(
-                    comptime name ++ "/",
-                    decl,
-                    bsp_name,
-                    be,
-                );
-
-                break :blk true;
-            };
-            if (!ok) {
-                std.debug.print("Bad BSP: {s} is neither namespace nor a microzig.Target\n", .{ prefix, full_name });
-            }
-        }
-    }
-}
-
 pub const BoardSupportPackage = struct {
     dep: *std.Build.Dependency,
     name: []const u8,
diff --git a/core/build.zig b/core/build.zig
index 1768f5133..033709021 100644
--- a/core/build.zig
+++ b/core/build.zig
@@ -4,35 +4,12 @@
 
 const std = @import("std");
 const microbuild = @import("microzig-build");
-// const uf2 = @import("uf2");
-
-////////////////////////////////////////
-//      MicroZig Gen 2 Interface      //
-////////////////////////////////////////
 
 fn root() []const u8 {
     return comptime (std.fs.path.dirname(@src().file) orelse ".");
 }
 const build_root = root();
 
-// const MicroZig = @This();
-
-// b: *std.Build,
-// self: *std.Build.Dependency,
-
-// /// Creates a new instance of the MicroZig build support.
-// ///
-// /// This is necessary as we need to keep track of some internal state to prevent
-// /// duplicated work per firmware built.
-// pub fn init(b: *std.Build, dependency_name: []const u8) *MicroZig {
-//     const mz = b.allocator.create(MicroZig) catch @panic("out of memory");
-//     mz.* = MicroZig{
-//         .b = b,
-//         .self = b.dependency(dependency_name, .{}),
-//     };
-//     return mz;
-// }
-
 /// This build script validates usage patterns we expect from MicroZig
 pub fn build(b: *std.Build) !void {
     _ = b;
@@ -98,684 +75,6 @@ pub fn build(b: *std.Build) !void {
     // test_step.dependOn(&b.addRunArtifact(core_tests).step);
 }
 
-// /// The resulting binary format for the firmware file.
-// /// A lot of embedded systems don't use plain ELF files, thus we provide means
-// /// to convert the resulting ELF into other common formats.
-// pub const BinaryFormat = union(enum) {
-//     /// [Executable and Linkable Format](https://en.wikipedia.org/wiki/Executable_and_Linkable_Format), the standard output from the compiler.
-//     elf,
-
-//     /// A flat binary, contains only the loaded portions of the firmware with an unspecified base offset.
-//     bin,
-
-//     /// The [Intel HEX](https://en.wikipedia.org/wiki/Intel_HEX) format, contains
-//     /// an ASCII description of what memory to load where.
-//     hex,
-
-//     /// A [Device Firmware Upgrade](https://www.usb.org/sites/default/files/DFU_1.1.pdf) file.
-//     dfu,
-
-//     /// The [USB Flashing Format (UF2)](https://github.com/microsoft/uf2) designed by Microsoft.
-//     uf2: uf2.FamilyId,
-
-//     /// The [firmware format](https://docs.espressif.com/projects/esptool/en/latest/esp32/advanced-topics/firmware-image-format.html) used by the [esptool](https://github.com/espressif/esptool) bootloader.
-//     esp,
-
-//     /// Custom option for non-standard formats.
-//     custom: *Custom,
-
-//     /// Returns the standard extension for the resulting binary file.
-//     pub fn getExtension(format: BinaryFormat) []const u8 {
-//         return switch (format) {
-//             .elf => ".elf",
-//             .bin => ".bin",
-//             .hex => ".hex",
-//             .dfu => ".dfu",
-//             .uf2 => ".uf2",
-//             .esp => ".bin",
-
-//             .custom => |c| c.extension,
-//         };
-//     }
-
-//     pub const Custom = struct {
-//         /// The standard extension of the format.
-//         extension: []const u8,
-
-//         /// A function that will convert a given `elf` file into the custom output format.
-//         ///
-//         /// The `*Custom` format is passed so contextual information can be obtained by using
-//         /// `@fieldParentPtr` to provide access to tooling.
-//         convert: *const fn (*Custom, elf: std.Build.LazyPath) std.Build.LazyPath,
-//     };
-
-//     const Enum = std.meta.Tag(BinaryFormat);
-
-//     const Context = struct {
-//         pub fn hash(self: @This(), fmt: BinaryFormat) u32 {
-//             _ = self;
-
-//             var hasher = std.hash.XxHash32.init(0x1337_42_21);
-
-//             hasher.update(@tagName(fmt));
-
-//             switch (fmt) {
-//                 .elf, .bin, .hex, .dfu, .esp => |val| {
-//                     if (@TypeOf(val) != void) @compileError("Missing update: Context.hash now requires special care!");
-//                 },
-
-//                 .uf2 => |family_id| hasher.update(@tagName(family_id)),
-//                 .custom => |custom| hasher.update(std.mem.asBytes(custom)),
-//             }
-
-//             return hasher.final();
-//         }
-
-//         pub fn eql(self: @This(), fmt_a: BinaryFormat, fmt_b: BinaryFormat, index: usize) bool {
-//             _ = self;
-//             _ = index;
-//             if (@as(BinaryFormat.Enum, fmt_a) != @as(BinaryFormat.Enum, fmt_b))
-//                 return false;
-
-//             return switch (fmt_a) {
-//                 .elf, .bin, .hex, .dfu, .esp => |val| {
-//                     if (@TypeOf(val) != void) @compileError("Missing update: Context.eql now requires special care!");
-//                     return true;
-//                 },
-
-//                 .uf2 => |a| (a == fmt_b.uf2),
-//                 .custom => |a| (a == fmt_b.custom),
-//             };
-//         }
-//     };
-// };
-
-// /// The CPU model a target uses.
-// ///
-// /// The CPUs usually require special care on how to do interrupts, and getting an entry point.
-// ///
-// /// MicroZig officially only supports the CPUs listed here, but other CPUs might be provided
-// /// via the `custom` field.
-// pub const CpuModel = union(enum) {
-//     avr5,
-//     cortex_m0,
-//     cortex_m0plus,
-//     cortex_m3,
-//     cortex_m4,
-//     riscv32_imac,
-
-//     custom: *const Cpu,
-
-//     pub fn getDescriptor(model: CpuModel) *const Cpu {
-//         return switch (@as(std.meta.Tag(CpuModel), model)) {
-//             inline else => |tag| &@field(cpus, @tagName(tag)),
-//             .custom => model.custom,
-//         };
-//     }
-// };
-
-// /// A cpu descriptor.
-// pub const Cpu = struct {
-//     /// Display name of the CPU.
-//     name: []const u8,
-
-//     /// Source file providing startup code and memory initialization routines.
-//     source_file: std.build.LazyPath,
-
-//     /// The compiler target we use to compile all the code.
-//     target: std.zig.CrossTarget,
-// };
-
-// /// A descriptor for memory regions in a microcontroller.
-// pub const MemoryRegion = struct {
-//     /// The type of the memory region for generating a proper linker script.
-//     kind: Kind,
-//     offset: u64,
-//     length: u64,
-
-//     pub const Kind = union(enum) {
-//         /// This is a (normally) immutable memory region where the code is stored.
-//         flash,
-
-//         /// This is a mutable memory region for data storage.
-//         ram,
-
-//         /// This is a memory region that maps MMIO devices.
-//         io,
-
-//         /// This is a memory region that exists, but is reserved and must not be used.
-//         reserved,
-
-//         /// This is a memory region used for internal linking tasks required by the board support package.
-//         private: PrivateRegion,
-//     };
-
-//     pub const PrivateRegion = struct {
-//         /// The name of the memory region. Will not have an automatic numeric counter and must be unique.
-//         name: []const u8,
-
-//         /// Is the memory region executable?
-//         executable: bool,
-
-//         /// Is the memory region readable?
-//         readable: bool,
-
-//         /// Is the memory region writable?
-//         writeable: bool,
-//     };
-// };
-
-// /// Defines a custom microcontroller.
-// pub const Chip = struct {
-//     /// The display name of the controller.
-//     name: []const u8,
-
-//     /// (optional) link to the documentation/vendor page of the controller.
-//     url: ?[]const u8 = null,
-
-//     /// The cpu model this controller uses.
-//     cpu: CpuModel,
-
-//     /// The provider for register definitions.
-//     register_definition: union(enum) {
-//         /// Use `regz` to create a zig file from a JSON schema.
-//         json: std.Build.LazyPath,
-
-//         /// Use `regz` to create a json file from a SVD schema.
-//         svd: std.Build.LazyPath,
-
-//         /// Use `regz` to create a zig file from an ATDF schema.
-//         atdf: std.Build.LazyPath,
-
-//         /// Use the provided file directly as the chip file.
-//         zig: std.Build.LazyPath,
-//     },
-
-//     /// The memory regions that are present in this chip.
-//     memory_regions: []const MemoryRegion,
-// };
-
-// /// Defines a hardware abstraction layer.
-// pub const HardwareAbstractionLayer = struct {
-//     /// Root source file for this HAL.
-//     source_file: std.Build.LazyPath,
-// };
-
-// /// Provides a description of a board.
-// ///
-// /// Boards provide additional information to a chip and HAL package.
-// /// For example, they can list attached peripherials, external crystal frequencies,
-// /// flash sizes, ...
-// pub const BoardDefinition = struct {
-//     /// Display name of the board
-//     name: []const u8,
-
-//     /// (optional) link to the documentation/vendor page of the board.
-//     url: ?[]const u8 = null,
-
-//     /// Provides the root file for the board definition.
-//     source_file: std.Build.LazyPath,
-// };
-
-// /// The linker script used to link the firmware.
-// pub const LinkerScript = union(enum) {
-//     /// Auto-generated linker script derived from the memory regions of the chip.
-//     generated,
-
-//     /// Externally defined linker script.
-//     source_file: std.build.LazyPath,
-// };
-
-// /// A compilation target for MicroZig. Provides information about the chip,
-// /// hal, board and so on.
-// ///
-// /// This is used instead of `std.zig.CrossTarget` to define a MicroZig Firmware.
-// pub const Target = struct {
-//     /// The preferred binary format of this MicroZig target. If `null`, the user must
-//     /// explicitly give the `.format` field during a call to `getEmittedBin()` or installation steps.
-//     preferred_format: ?BinaryFormat,
-
-//     /// The chip this target uses,
-//     chip: Chip,
-
-//     /// Usually, embedded projects are single-threaded and single-core applications. Platforms that
-//     /// support multiple CPUs should set this to `false`.
-//     single_threaded: bool = true,
-
-//     /// Determines whether the compiler_rt package is bundled with the application or not.
-//     /// This should always be true except for platforms where compiler_rt cannot be built right now.
-//     bundle_compiler_rt: bool = true,
-
-//     /// (optional) Provides a default hardware abstraction layer that is used.
-//     /// If `null`, no `microzig.hal` will be available.
-//     hal: ?HardwareAbstractionLayer = null,
-
-//     /// (optional) Provides description of external hardware and connected devices
-//     /// like oscillators and such.
-//     ///
-//     /// This structure isn't used by MicroZig itself, but can be utilized from the HAL
-//     /// if present.
-//     board: ?BoardDefinition = null,
-
-//     /// (optional) Provide a custom linker script for the hardware or define a custom generation.
-//     linker_script: LinkerScript = .generated,
-
-//     /// (optional) Further configures the created firmware depending on the chip and/or board settings.
-//     /// This can be used to set/change additional properties on the created `*Firmware` object.
-//     configure: ?*const fn (host_build: *std.Build, *Firmware) void = null,
-
-//     /// (optional) Post processing step that will patch up and modify the elf file if necessary.
-//     binary_post_process: ?*const fn (host_build: *std.Build, std.Build.LazyPath) std.Build.LazyPath = null,
-// };
-
-// /// Options to the `addFirmware` function.
-// pub const FirmwareOptions = struct {
-//     /// The name of the firmware file.
-//     name: []const u8,
-
-//     /// The MicroZig target that the firmware is built for. Either a board or a chip.
-//     target: Target,
-
-//     /// The optimization level that should be used. Usually `ReleaseSmall` or `Debug` is a good choice.
-//     /// Also using `std.Build.standardOptimizeOption` is a good idea.
-//     optimize: std.builtin.OptimizeMode,
-
-//     /// The root source file for the application. This is your `src/main.zig` file.
-//     source_file: std.Build.LazyPath,
-
-//     // Overrides:
-
-//     /// If set, overrides the `single_threaded` property of the target.
-//     single_threaded: ?bool = null,
-
-//     /// If set, overrides the `bundle_compiler_rt` property of the target.
-//     bundle_compiler_rt: ?bool = null,
-
-//     /// If set, overrides the `hal` property of the target.
-//     hal: ?HardwareAbstractionLayer = null,
-
-//     /// If set, overrides the `board` property of the target.
-//     board: ?BoardDefinition = null,
-
-//     /// If set, overrides the `linker_script` property of the target.
-//     linker_script: ?LinkerScript = null,
-// };
-
-// /// Declares a new MicroZig firmware file.
-// pub fn addFirmware(
-//     /// The MicroZig instance that should be used to create the firmware.
-//     mz: *MicroZig,
-//     /// The instance of the `build.zig` that is calling this function.
-//     host_build: *std.Build,
-//     /// Options that define how the firmware is built.
-//     options: FirmwareOptions,
-// ) *Firmware {
-//     const micro_build = mz.self.builder;
-
-//     const chip = &options.target.chip;
-//     const cpu = chip.cpu.getDescriptor();
-//     const maybe_hal = options.hal orelse options.target.hal;
-//     const maybe_board = options.board orelse options.target.board;
-
-//     const linker_script = options.linker_script orelse options.target.linker_script;
-
-//     // TODO: let the user override which ram section to use the stack on,
-//     // for now just using the first ram section in the memory region list
-//     const first_ram = blk: {
-//         for (chip.memory_regions) |region| {
-//             if (region.kind == .ram)
-//                 break :blk region;
-//         } else @panic("no ram memory region found for setting the end-of-stack address");
-//     };
-
-//     // On demand, generate chip definitions via regz:
-//     const chip_source = switch (chip.register_definition) {
-//         .json, .atdf, .svd => |file| blk: {
-//             const regz_exe = mz.dependency("regz", .{ .optimize = .ReleaseSafe }).artifact("regz");
-
-//             const regz_gen = host_build.addRunArtifact(regz_exe);
-
-//             regz_gen.addArg("--schema"); // Explicitly set schema type, one of: svd, atdf, json
-//             regz_gen.addArg(@tagName(chip.register_definition));
-
-//             regz_gen.addArg("--output_path"); // Write to a file
-//             const zig_file = regz_gen.addOutputFileArg("chip.zig");
-
-//             regz_gen.addFileArg(file);
-
-//             break :blk zig_file;
-//         },
-
-//         .zig => |src| src,
-//     };
-
-//     const config = host_build.addOptions();
-//     config.addOption(bool, "has_hal", (maybe_hal != null));
-//     config.addOption(bool, "has_board", (maybe_board != null));
-
-//     config.addOption(?[]const u8, "board_name", if (maybe_board) |brd| brd.name else null);
-
-//     config.addOption([]const u8, "chip_name", chip.name);
-//     config.addOption([]const u8, "cpu_name", chip.name);
-//     config.addOption(usize, "end_of_stack", first_ram.offset + first_ram.length);
-
-//     const fw: *Firmware = host_build.allocator.create(Firmware) catch @panic("out of memory");
-//     fw.* = Firmware{
-//         .mz = mz,
-//         .host_build = host_build,
-//         .artifact = host_build.addExecutable(.{
-//             .name = options.name,
-//             .optimize = options.optimize,
-//             .target = cpu.target,
-//             .linkage = .static,
-//             .root_source_file = .{ .cwd_relative = mz.self.builder.pathFromRoot("src/start.zig") },
-//         }),
-//         .target = options.target,
-//         .output_files = Firmware.OutputFileMap.init(host_build.allocator),
-
-//         .config = config,
-
-//         .modules = .{
-//             .microzig = micro_build.createModule(.{
-//                 .source_file = .{ .cwd_relative = micro_build.pathFromRoot("src/microzig.zig") },
-//                 .dependencies = &.{
-//                     .{
-//                         .name = "config",
-//                         .module = micro_build.createModule(.{ .source_file = config.getSource() }),
-//                     },
-//                 },
-//             }),
-
-//             .cpu = undefined,
-//             .chip = undefined,
-
-//             .board = null,
-//             .hal = null,
-
-//             .app = undefined,
-//         },
-//     };
-//     errdefer fw.output_files.deinit();
-
-//     fw.modules.chip = micro_build.createModule(.{
-//         .source_file = chip_source,
-//         .dependencies = &.{
-//             .{ .name = "microzig", .module = fw.modules.microzig },
-//         },
-//     });
-//     fw.modules.microzig.dependencies.put("chip", fw.modules.chip) catch @panic("out of memory");
-
-//     fw.modules.cpu = micro_build.createModule(.{
-//         .source_file = cpu.source_file,
-//         .dependencies = &.{
-//             .{ .name = "microzig", .module = fw.modules.microzig },
-//         },
-//     });
-//     fw.modules.microzig.dependencies.put("cpu", fw.modules.cpu) catch @panic("out of memory");
-
-//     if (maybe_hal) |hal| {
-//         fw.modules.hal = micro_build.createModule(.{
-//             .source_file = hal.source_file,
-//             .dependencies = &.{
-//                 .{ .name = "microzig", .module = fw.modules.microzig },
-//             },
-//         });
-//         fw.modules.microzig.dependencies.put("hal", fw.modules.hal.?) catch @panic("out of memory");
-//     }
-
-//     if (maybe_board) |brd| {
-//         fw.modules.board = micro_build.createModule(.{
-//             .source_file = brd.source_file,
-//             .dependencies = &.{
-//                 .{ .name = "microzig", .module = fw.modules.microzig },
-//             },
-//         });
-//         fw.modules.microzig.dependencies.put("board", fw.modules.board.?) catch @panic("out of memory");
-//     }
-
-//     fw.modules.app = host_build.createModule(.{
-//         .source_file = options.source_file,
-//         .dependencies = &.{
-//             .{ .name = "microzig", .module = fw.modules.microzig },
-//         },
-//     });
-
-//     const umm = mz.dependency("umm-zig", .{}).module("umm");
-//     fw.modules.microzig.dependencies.put("umm", umm) catch @panic("out of memory");
-
-//     fw.artifact.addModule("app", fw.modules.app);
-//     fw.artifact.addModule("microzig", fw.modules.microzig);
-
-//     fw.artifact.strip = false; // we always want debug symbols, stripping brings us no benefit on embedded
-//     fw.artifact.single_threaded = options.single_threaded orelse fw.target.single_threaded;
-//     fw.artifact.bundle_compiler_rt = options.bundle_compiler_rt orelse fw.target.bundle_compiler_rt;
-
-//     switch (linker_script) {
-//         .generated => {
-//             fw.artifact.setLinkerScript(
-//                 generateLinkerScript(host_build, chip.*) catch @panic("out of memory"),
-//             );
-//         },
-
-//         .source_file => |source| {
-//             fw.artifact.setLinkerScriptPath(source);
-//         },
-//     }
-
-//     if (options.target.configure) |configure| {
-//         configure(host_build, fw);
-//     }
-
-//     return fw;
-// }
-
-// /// Configuration options for firmware installation.
-// pub const InstallFirmwareOptions = struct {
-//     /// Overrides the output format for the binary. If not set, the standard preferred file format for the firmware target is used.
-//     format: ?BinaryFormat = null,
-// };
-
-// /// Adds a new dependency to the `install` step that will install the `firmware` into the folder `$prefix/firmware`.
-// pub fn installFirmware(
-//     /// The MicroZig instance that was used to create the firmware.
-//     mz: *MicroZig,
-//     /// The instance of the `build.zig` that should perform installation.
-//     b: *std.Build,
-//     /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
-//     firmware: *Firmware,
-//     /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
-//     options: InstallFirmwareOptions,
-// ) void {
-//     std.debug.assert(mz == firmware.mz);
-//     const install_step = addInstallFirmware(mz, b, firmware, options);
-//     b.getInstallStep().dependOn(&install_step.step);
-// }
-
-// /// Creates a new `std.Build.Step.InstallFile` instance that will install the given firmware to `$prefix/firmware`.
-// ///
-// /// **NOTE:** This does not actually install the firmware yet. You have to add the returned step as a dependency to another step.
-// ///           If you want to just install the firmware, use `installFirmware` instead!
-// pub fn addInstallFirmware(
-//     /// The MicroZig instance that was used to create the firmware.
-//     mz: *MicroZig,
-//     /// The instance of the `build.zig` that should perform installation.
-//     b: *std.Build,
-//     /// The firmware that should be installed. Please make sure that this was created with the same `MicroZig` instance as `mz`.
-//     firmware: *Firmware,
-//     /// Optional configuration of the installation process. Pass `.{}` if you're not sure what to do here.
-//     options: InstallFirmwareOptions,
-// ) *std.Build.Step.InstallFile {
-//     const format = firmware.resolveFormat(options.format);
-
-//     const basename = b.fmt("{s}{s}", .{
-//         firmware.artifact.name,
-//         format.getExtension(),
-//     });
-
-//     _ = mz;
-
-//     return b.addInstallFileWithDir(firmware.getEmittedBin(format), .{ .custom = "firmware" }, basename);
-// }
-
-// /// Declaration of a firmware build.
-// pub const Firmware = struct {
-//     const OutputFileMap = std.ArrayHashMap(BinaryFormat, std.Build.LazyPath, BinaryFormat.Context, false);
-
-//     const Modules = struct {
-//         app: *std.Build.Module,
-//         cpu: *std.Build.Module,
-//         chip: *std.Build.Module,
-//         board: ?*std.Build.Module,
-//         hal: ?*std.Build.Module,
-//         microzig: *std.Build.Module,
-//     };
-
-//     // privates:
-//     mz: *MicroZig,
-//     host_build: *std.Build,
-//     target: Target,
-//     output_files: OutputFileMap,
-
-//     // publics:
-
-//     /// The artifact that is built by Zig.
-//     artifact: *std.Build.Step.Compile,
-
-//     /// The options step that provides `microzig.config`. If you need custom configuration, you can add this here.
-//     config: *std.Build.Step.Options,
-
-//     /// Declaration of the MicroZig modules used by this firmware.
-//     modules: Modules,
-
-//     /// Path to the emitted elf file, if any.
-//     emitted_elf: ?std.Build.LazyPath = null,
-
-//     /// Returns the emitted ELF file for this firmware. This is useful if you need debug information
-//     /// or want to use a debugger like Segger, ST-Link or similar.
-//     ///
-//     /// **NOTE:** This is similar, but not equivalent to `std.Build.Step.Compile.getEmittedBin`. The call on the compile step does
-//     ///           not include post processing of the ELF files necessary by certain targets.
-//     pub fn getEmittedElf(firmware: *Firmware) std.Build.LazyPath {
-//         if (firmware.emitted_elf == null) {
-//             const raw_elf = firmware.artifact.getEmittedBin();
-//             firmware.emitted_elf = if (firmware.target.binary_post_process) |binary_post_process|
-//                 binary_post_process(firmware.host_build, raw_elf)
-//             else
-//                 raw_elf;
-//         }
-//         return firmware.emitted_elf.?;
-//     }
-
-//     /// Returns the emitted binary for this firmware. The file is either in the preferred file format for
-//     /// the target or in `format` if not null.
-//     ///
-//     /// **NOTE:** The file returned here is the same file that will be installed.
-//     pub fn getEmittedBin(firmware: *Firmware, format: ?BinaryFormat) std.Build.LazyPath {
-//         const actual_format = firmware.resolveFormat(format);
-
-//         const gop = firmware.output_files.getOrPut(actual_format) catch @panic("out of memory");
-//         if (!gop.found_existing) {
-//             const elf_file = firmware.getEmittedElf();
-
-//             const basename = firmware.host_build.fmt("{s}{s}", .{
-//                 firmware.artifact.name,
-//                 actual_format.getExtension(),
-//             });
-
-//             gop.value_ptr.* = switch (actual_format) {
-//                 .elf => elf_file,
-
-//                 .bin => blk: {
-//                     const objcopy = firmware.host_build.addObjCopy(elf_file, .{
-//                         .basename = basename,
-//                         .format = .bin,
-//                     });
-
-//                     break :blk objcopy.getOutput();
-//                 },
-
-//                 .hex => blk: {
-//                     const objcopy = firmware.host_build.addObjCopy(elf_file, .{
-//                         .basename = basename,
-//                         .format = .hex,
-//                     });
-
-//                     break :blk objcopy.getOutput();
-//                 },
-
-//                 .uf2 => |family_id| blk: {
-//                     const uf2_exe = firmware.mz.dependency("uf2", .{ .optimize = .ReleaseSafe }).artifact("elf2uf2");
-
-//                     const convert = firmware.host_build.addRunArtifact(uf2_exe);
-
-//                     convert.addArg("--family-id");
-//                     convert.addArg(firmware.host_build.fmt("0x{X:0>4}", .{@intFromEnum(family_id)}));
-
-//                     convert.addArg("--elf-path");
-//                     convert.addFileArg(elf_file);
-
-//                     convert.addArg("--output-path");
-//                     break :blk convert.addOutputFileArg(basename);
-//                 },
-
-//                 .dfu => buildConfigError(firmware.host_build, "DFU is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/145 for more details!", .{}),
-//                 .esp => buildConfigError(firmware.host_build, "ESP firmware image is not implemented yet. See https://github.com/ZigEmbeddedGroup/microzig/issues/146 for more details!", .{}),
-
-//                 .custom => |generator| generator.convert(generator, elf_file),
-//             };
-//         }
-//         return gop.value_ptr.*;
-//     }
-
-//     pub const AppDependencyOptions = struct {
-//         depend_on_microzig: bool = false,
-//     };
-
-//     /// Adds a regular dependency to your application.
-//     pub fn addAppDependency(fw: *Firmware, name: []const u8, module: *std.Build.Module, options: AppDependencyOptions) void {
-//         if (options.depend_on_microzig) {
-//             module.dependencies.put("microzig", fw.modules.microzig) catch @panic("OOM");
-//         }
-//         fw.modules.app.dependencies.put(name, module) catch @panic("OOM");
-//     }
-
-//     pub fn addIncludePath(fw: *Firmware, path: std.Build.LazyPath) void {
-//         fw.artifact.addIncludePath(path);
-//     }
-
-//     pub fn addSystemIncludePath(fw: *Firmware, path: std.Build.LazyPath) void {
-//         fw.artifact.addSystemIncludePath(path);
-//     }
-
-//     pub fn addCSourceFile(fw: *Firmware, source: std.Build.Step.Compile.CSourceFile) void {
-//         fw.artifact.addCSourceFile(source);
-//     }
-
-//     pub fn addOptions(fw: *Firmware, module_name: []const u8, options: *std.Build.OptionsStep) void {
-//         fw.artifact.addOptions(module_name, options);
-//         fw.modules.app.dependencies.put(
-//             module_name,
-//             fw.host_build.createModule(.{
-//                 .source_file = options.getOutput(),
-//             }),
-//         ) catch @panic("OOM");
-//     }
-
-//     pub fn addObjectFile(fw: *Firmware, source: std.Build.LazyPath) void {
-//         fw.artifact.addObjectFile(source);
-//     }
-
-//     fn resolveFormat(firmware: *Firmware, format: ?BinaryFormat) BinaryFormat {
-//         if (format) |fmt| return fmt;
-
-//         if (firmware.target.preferred_format) |fmt| return fmt;
-
-//         buildConfigError(firmware.host_build, "{s} has no preferred output format, please provide one in the `format` option.", .{
-//             firmware.target.chip.name,
-//         });
-//     }
-// };
-
 pub const cpus = struct {
     pub const avr5 = microbuild.Cpu{
         .name = "AVR5",
@@ -843,139 +142,3 @@ pub const cpus = struct {
         },
     };
 };
-
-// fn buildConfigError(b: *std.Build, comptime fmt: []const u8, args: anytype) noreturn {
-//     const msg = b.fmt(fmt, args);
-//     @panic(msg);
-// }
-
-// fn dependency(mz: *MicroZig, name: []const u8, args: anytype) *std.Build.Dependency {
-//     return mz.self.builder.dependency(name, args);
-// }
-
-// fn generateLinkerScript(b: *std.Build, chip: Chip) !std.Build.LazyPath {
-//     const cpu = chip.cpu.getDescriptor();
-
-//     var contents = std.ArrayList(u8).init(b.allocator);
-//     const writer = contents.writer();
-//     try writer.print(
-//         \\/*
-//         \\ * This file was auto-generated by microzig
-//         \\ *
-//         \\ * Target CPU:  {[cpu]s}
-//         \\ * Target Chip: {[chip]s}
-//         \\ */
-//         \\
-//         // This is not the "true" entry point, but there's no such thing on embedded platforms
-//         // anyways. This is the logical entrypoint that should be invoked when
-//         // stack, .data and .bss are set up and the CPU is ready to be used.
-//         \\ENTRY(microzig_main);
-//         \\
-//         \\
-//     , .{
-//         .cpu = cpu.name,
-//         .chip = chip.name,
-//     });
-
-//     try writer.writeAll("MEMORY\n{\n");
-//     {
-//         var counters = [4]usize{ 0, 0, 0, 0 };
-//         for (chip.memory_regions) |region| {
-//             // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k
-
-//             switch (region.kind) {
-//                 .flash => {
-//                     try writer.print("  flash{d}    (rx!w)", .{counters[0]});
-//                     counters[0] += 1;
-//                 },
-
-//                 .ram => {
-//                     try writer.print("  ram{d}      (rw!x)", .{counters[1]});
-//                     counters[1] += 1;
-//                 },
-
-//                 .io => {
-//                     try writer.print("  io{d}       (rw!x)", .{counters[2]});
-//                     counters[2] += 1;
-//                 },
-
-//                 .reserved => {
-//                     try writer.print("  reserved{d} (rw!x)", .{counters[3]});
-//                     counters[3] += 1;
-//                 },
-
-//                 .private => |custom| {
-//                     try writer.print("  {s} (", .{custom.name});
-//                     if (custom.readable) try writer.writeAll("r");
-//                     if (custom.writeable) try writer.writeAll("w");
-//                     if (custom.executable) try writer.writeAll("x");
-
-//                     if (!custom.readable or !custom.writeable or !custom.executable) {
-//                         try writer.writeAll("!");
-//                         if (!custom.readable) try writer.writeAll("r");
-//                         if (!custom.writeable) try writer.writeAll("w");
-//                         if (!custom.executable) try writer.writeAll("x");
-//                     }
-//                     try writer.writeAll(")");
-//                 },
-//             }
-//             try writer.print(" : ORIGIN = 0x{X:0>8}, LENGTH = 0x{X:0>8}\n", .{ region.offset, region.length });
-//         }
-//     }
-
-//     try writer.writeAll("}\n\nSECTIONS\n{\n");
-//     {
-//         try writer.writeAll(
-//             \\  .text :
-//             \\  {
-//             \\     KEEP(*(microzig_flash_start))
-//             \\     *(.text*)
-//             \\  } > flash0
-//             \\
-//             \\
-//         );
-
-//         switch (cpu.target.getCpuArch()) {
-//             .arm, .thumb => try writer.writeAll(
-//                 \\  .ARM.exidx : {
-//                 \\      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-//                 \\  } >flash0
-//                 \\
-//                 \\
-//             ),
-//             else => {},
-//         }
-
-//         try writer.writeAll(
-//             \\  .data :
-//             \\  {
-//             \\     microzig_data_start = .;
-//             \\     *(.rodata*)
-//             \\     *(.data*)
-//             \\     microzig_data_end = .;
-//             \\  } > ram0 AT> flash0
-//             \\
-//             \\  .bss (NOLOAD) :
-//             \\  {
-//             \\      microzig_bss_start = .;
-//             \\      *(.bss*)
-//             \\      microzig_bss_end = .;
-//             \\  } > ram0
-//             \\
-//             \\  microzig_data_load_start = LOADADDR(.data);
-//             \\
-//         );
-//     }
-//     try writer.writeAll("}\n");
-
-//     // TODO: Assert that the flash can actually hold all data!
-//     // try writer.writeAll(
-//     //     \\
-//     //     \\  ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" );
-//     //     \\
-//     // );
-
-//     const write = b.addWriteFiles();
-
-//     return write.add("linker.ld", contents.items);
-// }
diff --git a/examples/next-gen/build.zig b/examples/next-gen/build.zig
index 37628be1a..0c3579e3f 100644
--- a/examples/next-gen/build.zig
+++ b/examples/next-gen/build.zig
@@ -5,11 +5,6 @@ pub fn build(b: *std.Build) void {
     const microzig = MicroZig.createBuildEnvironment(b, .{
         .self = "microzig", // package name of the build package (optional)
         .core = "microzig-core", // package name of the core package (optional)
-        .board_support = &.{
-            // package names for BSP packages:
-            "microzig-bsp-nxp",
-            "microzig-bsp-rp2040",
-        },
     });
 
     const optimize = b.standardOptimizeOption(.{});
diff --git a/examples/next-gen/build.zig.zon b/examples/next-gen/build.zig.zon
index f9d6f771a..90539673b 100644
--- a/examples/next-gen/build.zig.zon
+++ b/examples/next-gen/build.zig.zon
@@ -4,19 +4,19 @@
     .dependencies = .{
         .microzig = .{
             .url = "https://public.devspace.random-projects.net/microzig-build.tar.gz",
-            .hash = "122068db50e2a071cac3fc5b42d5cd2213ccb563986af60b941cb7af29b83df65b02",
+            .hash = "1220c87cc608598bdb4ae5ed6436c6fa3e126c57d3d1bbfaf01625c3af0c15da44e4",
         },
         .@"microzig-core" = .{
             .url = "https://public.devspace.random-projects.net/microzig-core.tar.gz",
-            .hash = "12202df033d2b967108b25b8e66d8c8abcf690348a24baa35474a28086170ff31e54",
+            .hash = "1220a37d914f0585bbaeba2bc4d4d15586bef310a6af340af87f0e13fde0b4ddfb1a",
         },
         .@"microzig-bsp-nxp" = .{
             .url = "https://public.devspace.random-projects.net/board-support/nxp/lpc.tar.gz",
-            .hash = "12201efd8d8b992caef770c87d78e6bd00bd73051bd1559bc342703f2e83650ef2f9",
+            .hash = "122040dc9467f6dac90a1376fff25350b2a5abd291904db7bea48a78db4f6e6dff13",
         },
         .@"microzig-bsp-rp2040" = .{
             .url = "https://public.devspace.random-projects.net/board-support/raspberrypi/rp2040.tar.gz",
-            .hash = "1220154cd3634d0f3286cd2fb727cce9af3f3ab166772065e3efe4f9577128f4c559",
+            .hash = "1220142a13e590252deb7667569bdd3f6147c5b461f6b0343a825079a7dd3a24dea9",
         },
     },
 }
\ No newline at end of file
diff --git a/tools/extract-bsp-info.zig b/tools/extract-bsp-info.zig
index b0f562732..4c2b26091 100644
--- a/tools/extract-bsp-info.zig
+++ b/tools/extract-bsp-info.zig
@@ -70,33 +70,26 @@ fn renderMicroZigTarget(stream: anytype, key: []const u8, target: microzig.Targe
     try std.json.stringify(jtarget, .{}, stream);
 }
 
-fn renderTargetArray(stream: anytype, comptime array: type) !void {
-    inline for (comptime std.meta.declarations(array), 0..) |fld, i| {
+fn renderTargetArray(stream: anytype, targets: []const microzig.BoardSupportPackageDefinition.TargetDefinition) !void {
+    for (targets, 0..) |target_def, i| {
         if (i > 0) try stream.writeAll(",");
-        const target = comptime @field(array, fld.name);
-
-        if (@TypeOf(target) == type) {
-            // recurse
-            try renderTargetArray(stream, target);
-        } else {
-            try renderMicroZigTarget(
-                stream,
-                fld.name,
-                target,
-            );
-        }
+        try renderMicroZigTarget(
+            stream,
+            target_def.id,
+            target_def.target,
+        );
     }
 }
 
 pub fn main() !void {
+    const info = bsp.microzig_board_support;
+
     var stdout = std.io.getStdOut().writer();
 
     try stdout.writeAll("{ \"board-support\": {");
 
-    try stdout.writeAll("\"chips\":[");
-    try renderTargetArray(stdout, bsp.chips);
-    try stdout.writeAll("],\"boards\":[");
-    try renderTargetArray(stdout, bsp.boards);
+    try stdout.writeAll("\"targets\":[");
+    try renderTargetArray(stdout, info.targets);
 
     try stdout.writeAll("]}}");
 }

From 4480b7c17a8dc9bc4f7e3c107d7f7bcb29e95ead Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Tue, 23 Jan 2024 09:59:50 +0100
Subject: [PATCH 262/286] Fixes build script enough to make next-gen example
 build.

---
 board-support/raspberrypi-rp2040/build.zig |  22 +-
 build/build.zig                            | 560 ++++++++++-----------
 core/build.zig                             |  90 +---
 examples/next-gen/build.zig.zon            |   8 +-
 tools/bundle.py                            |   2 +-
 tools/extract-bsp-info.zig                 |   5 +
 6 files changed, 295 insertions(+), 392 deletions(-)

diff --git a/board-support/raspberrypi-rp2040/build.zig b/board-support/raspberrypi-rp2040/build.zig
index 3e0d5344d..1baf71e65 100644
--- a/board-support/raspberrypi-rp2040/build.zig
+++ b/board-support/raspberrypi-rp2040/build.zig
@@ -137,15 +137,15 @@ const chip = .{
 };
 
 /// Returns a configuration function that will add the provided `BootROM` to the firmware.
-pub fn rp2040_configure(comptime bootrom: BootROM) *const fn (host_build: *std.Build, *microzig.Firmware) void {
+pub fn rp2040_configure(comptime bootrom: BootROM) *const fn (env: *microzig.BuildEnvironment, *microzig.Firmware) void {
     const T = struct {
-        fn configure(host_build: *std.Build, fw: *microzig.Firmware) void {
-            const bootrom_file = getBootrom(host_build, bootrom);
+        fn configure(env: *microzig.BuildEnvironment, fw: *microzig.Firmware) void {
+            const bootrom_file = getBootrom(env, bootrom);
 
             // HACK: Inject the file as a dependency to MicroZig.board
             fw.modules.board.?.dependencies.put(
                 "bootloader",
-                host_build.createModule(.{
+                env.host_build.createModule(.{
                     .source_file = bootrom_file.bin,
                 }),
             ) catch @panic("oom");
@@ -161,7 +161,7 @@ pub const Stage2Bootloader = struct {
     elf: ?std.Build.LazyPath,
 };
 
-pub fn getBootrom(b: *std.Build, rom: BootROM) Stage2Bootloader {
+pub fn getBootrom(env: *microzig.BuildEnvironment, rom: BootROM) Stage2Bootloader {
     const rom_exe = switch (rom) {
         .artifact => |artifact| artifact,
         .blob => |blob| return Stage2Bootloader{
@@ -170,13 +170,13 @@ pub fn getBootrom(b: *std.Build, rom: BootROM) Stage2Bootloader {
         },
 
         else => blk: {
-            var target = @as(microzig.CpuModel, chip.cpu).getDescriptor().target;
+            var target = env.getCpuDescriptor(chip.cpu).target;
             target.abi = .eabi;
 
-            const rom_path = b.pathFromRoot(b.fmt("{s}/src/bootroms/{s}.S", .{ build_root, @tagName(rom) }));
+            const rom_path = env.host_build.pathFromRoot(env.host_build.fmt("{s}/src/bootroms/{s}.S", .{ build_root, @tagName(rom) }));
 
-            const rom_exe = b.addExecutable(.{
-                .name = b.fmt("stage2-{s}", .{@tagName(rom)}),
+            const rom_exe = env.host_build.addExecutable(.{
+                .name = env.host_build.fmt("stage2-{s}", .{@tagName(rom)}),
                 .optimize = .ReleaseSmall,
                 .target = target,
                 .root_source_file = null,
@@ -191,8 +191,8 @@ pub fn getBootrom(b: *std.Build, rom: BootROM) Stage2Bootloader {
         },
     };
 
-    const rom_objcopy = b.addObjCopy(rom_exe.getEmittedBin(), .{
-        .basename = b.fmt("{s}.bin", .{@tagName(rom)}),
+    const rom_objcopy = env.host_build.addObjCopy(rom_exe.getEmittedBin(), .{
+        .basename = env.host_build.fmt("{s}.bin", .{@tagName(rom)}),
         .format = .bin,
     });
 
diff --git a/build/build.zig b/build/build.zig
index 67c16e24b..815055157 100644
--- a/build/build.zig
+++ b/build/build.zig
@@ -5,10 +5,64 @@
 const std = @import("std");
 const uf2 = @import("uf2");
 
+/// This build script validates usage patterns we expect from MicroZig
+pub fn build(b: *std.Build) !void {
+    const uf2_dep = b.dependency("uf2", .{});
+
+    const build_test = b.addTest(.{
+        .root_source_file = .{ .path = "build.zig" },
+    });
+
+    build_test.addAnonymousModule("uf2", .{
+        .source_file = .{ .cwd_relative = uf2_dep.builder.pathFromRoot("build.zig") },
+    });
+
+    const install_docs = b.addInstallDirectory(.{
+        .source_dir = build_test.getEmittedDocs(),
+        .install_dir = .prefix,
+        .install_subdir = "docs",
+    });
+
+    b.getInstallStep().dependOn(&install_docs.step);
+}
+
 ////////////////////////////////////////
 //      MicroZig Gen 3 Interface      //
 ////////////////////////////////////////
 
+const zig_deps = struct {
+    // Keep in sync with the logic from Build.zig:dependency:
+
+    const build_runner = @import("root");
+    const deps = build_runner.dependencies;
+
+    const names = blk: {
+        var list: []const []const u8 = &.{};
+        for (@typeInfo(deps.imports).Struct.decls) |decl| {
+            list = list ++ [_][]const u8{decl.name};
+        }
+        break :blk list;
+    };
+
+    const modules = blk: {
+        var list: []const type = &.{};
+        for (@typeInfo(deps.imports).Struct.decls) |decl| {
+            list = list ++ [_]type{@field(deps.imports, decl.name)};
+        }
+        break :blk list;
+    };
+
+    fn get(comptime name: []const u8) ?type {
+        for (names, modules) |item, mod| {
+            if (std.mem.eql(u8, item, name))
+                return mod;
+        }
+        return null;
+    }
+};
+
+pub const CpuArray = std.enums.EnumArray(CpuType, Cpu);
+
 pub const BoardSupportPackageDefinition = struct {
     pub const TargetDefinition = struct {
         id: []const u8, // full "uri"
@@ -109,21 +163,14 @@ const ImportedBSP = struct {
 };
 
 fn get_declared_bsps() []const ImportedBSP {
-
-    // Keep in sync with the logic from Build.zig:dependency
-    const build_runner = @import("root");
-    const deps = build_runner.dependencies;
-
     var bsps: []const ImportedBSP = &.{};
-    inline for (@typeInfo(deps.imports).Struct.decls) |decl| {
-        if (comptime std.mem.indexOfScalar(u8, decl.name, '.') == null) {
-            const maybe_bsp = @field(deps.imports, decl.name);
-
+    inline for (zig_deps.names, zig_deps.modules) |name, maybe_bsp| {
+        if (comptime std.mem.indexOfScalar(u8, name, '.') == null) {
             if (@hasDecl(maybe_bsp, "microzig_board_support")) {
                 const bsp = @field(maybe_bsp, "microzig_board_support");
                 if (@TypeOf(bsp) == BoardSupportPackageDefinition) {
                     bsps = bsps ++ [_]ImportedBSP{.{
-                        .import_name = decl.name,
+                        .import_name = name,
                         .bsp = bsp,
                     }};
                 }
@@ -139,24 +186,72 @@ pub const EnvironmentInfo = struct {
 
     /// package name of the core package (optional)
     core: []const u8 = "microzig-core",
+
+    board_support_packages: BspSource = .from_dependencies,
+
+    pub const BspSource = union(enum) {
+        from_dependencies,
+        explicit: []const []const u8,
+    };
 };
 
+/// Creates a new MicroZig build environment that can be used to create new firmware.
 pub fn createBuildEnvironment(b: *std.Build, comptime info: EnvironmentInfo) *BuildEnvironment {
     const available_bsps = comptime get_declared_bsps();
 
+    const requested_bsps = switch (info.board_support_packages) {
+        .from_dependencies => available_bsps,
+        .explicit => |list| comptime blk: {
+            var used = std.StaticBitSet(list.len).initEmpty();
+
+            var requested_bsps: []const ImportedBSP = &.{};
+            for (list, 0..) |name, index| {
+                for (available_bsps) |bsp| {
+                    if (std.mem.eql(u8, bsp.name, name)) {
+                        requested_bsps = requested_bsps ++ [_]ImportedBSP{bsp};
+                    } else {
+                        used.set(index);
+                    }
+                }
+            }
+
+            if (used.count > 0) {
+                var msg: []const u8 = "Not all requested board support packages were declared in build.zig.zon. The following packages are missing:";
+                var iter = used.iterator();
+                while (iter.next()) |index| {
+                    msg = msg ++ std.fmt.comptimePrint("\n* {s}", .{
+                        list[index].name,
+                    });
+                }
+                @compileError(msg);
+            }
+
+            break :blk requested_bsps;
+        },
+    };
+
+    const core_module = zig_deps.get(info.core) orelse @compileError("A module named " ++ info.core ++ " is not declared in build.zig.zon!");
+    const build_module = zig_deps.get(info.self) orelse @compileError("A module named " ++ info.self ++ " is not declared in build.zig.zon!");
+    if (build_module != @This()) {
+        @compileError("The module " ++ info.self ++ " is not the same of which this function is called. Please pass the exact same module name to this function as you pass to import!");
+    }
+
     const be = b.allocator.create(BuildEnvironment) catch @panic("out of memory");
     be.* = BuildEnvironment{
         .host_build = b,
         .self = undefined,
         .microzig_core = undefined,
-        .board_support_packages = b.allocator.alloc(BoardSupportPackage, available_bsps.len) catch @panic("out of memory"),
+        .board_support_packages = b.allocator.alloc(BoardSupportPackage, requested_bsps.len) catch @panic("out of memory"),
         .targets = .{},
+        .self_pkg_name = comptime info.self,
+        .core_pkg_name = comptime info.core,
+        .cpus = &core_module.cpus,
     };
 
     be.self = b.dependency(info.self, .{});
     be.microzig_core = b.dependency(info.core, .{});
 
-    inline for (be.board_support_packages, available_bsps) |*bsp, def| {
+    inline for (be.board_support_packages, requested_bsps) |*bsp, def| {
         bsp.* = BoardSupportPackage{
             .name = def.import_name,
             .dep = b.dependency(def.import_name, .{}),
@@ -184,14 +279,28 @@ pub const BuildEnvironment = struct {
 
     microzig_core: *std.Build.Dependency,
 
+    self_pkg_name: []const u8,
+    core_pkg_name: []const u8,
+
     board_support_packages: []BoardSupportPackage,
 
     targets: std.StringArrayHashMapUnmanaged(Target),
 
+    cpus: *const CpuArray,
+
+    /// Searches for a target called `name` and returns a pointer to the MicroZig Target if it exists.
     pub fn findTarget(env: *const BuildEnvironment, name: []const u8) ?*const Target {
         return env.targets.getPtr(name);
     }
 
+    /// Returns the instance to the CPU descriptor for the given CPU model.
+    pub fn getCpuDescriptor(env: *BuildEnvironment, model: CpuModel) *const Cpu {
+        return if (model == .custom)
+            model.custom
+        else
+            env.cpus.getPtrConst(model);
+    }
+
     /// Declares a new MicroZig firmware file.
     pub fn addFirmware(
         /// The MicroZig instance that should be used to create the firmware.
@@ -204,7 +313,7 @@ pub const BuildEnvironment = struct {
         const micro_build = env.self.builder;
 
         const chip = &options.target.chip;
-        const cpu = chip.cpu.getDescriptor();
+        const cpu = env.getCpuDescriptor(chip.cpu);
         const maybe_hal = options.hal orelse options.target.hal;
         const maybe_board = options.board orelse options.target.board;
 
@@ -259,7 +368,7 @@ pub const BuildEnvironment = struct {
                 .optimize = options.optimize,
                 .target = cpu.target,
                 .linkage = .static,
-                .root_source_file = .{ .cwd_relative = env.self.builder.pathFromRoot("src/start.zig") },
+                .root_source_file = .{ .cwd_relative = env.microzig_core.builder.pathFromRoot("src/start.zig") },
             }),
             .target = options.target,
             .output_files = Firmware.OutputFileMap.init(host_build.allocator),
@@ -268,7 +377,7 @@ pub const BuildEnvironment = struct {
 
             .modules = .{
                 .microzig = micro_build.createModule(.{
-                    .source_file = .{ .cwd_relative = micro_build.pathFromRoot("src/microzig.zig") },
+                    .source_file = .{ .cwd_relative = env.microzig_core.builder.pathFromRoot("src/microzig.zig") },
                     .dependencies = &.{
                         .{
                             .name = "config",
@@ -331,7 +440,7 @@ pub const BuildEnvironment = struct {
             },
         });
 
-        const umm = env.dependency("umm-zig", .{}).module("umm");
+        const umm = env.microzig_core.builder.dependency("umm-zig", .{}).module("umm");
         fw.modules.microzig.dependencies.put("umm", umm) catch @panic("out of memory");
 
         fw.artifact.addModule("app", fw.modules.app);
@@ -344,7 +453,7 @@ pub const BuildEnvironment = struct {
         switch (linker_script) {
             .generated => {
                 fw.artifact.setLinkerScript(
-                    generateLinkerScript(host_build, chip.*) catch @panic("out of memory"),
+                    env.generateLinkerScript(chip.*) catch @panic("out of memory"),
                 );
             },
 
@@ -354,7 +463,7 @@ pub const BuildEnvironment = struct {
         }
 
         if (options.target.configure) |configure| {
-            configure(host_build, fw);
+            configure(fw.env, fw);
         }
 
         return fw;
@@ -404,98 +513,145 @@ pub const BuildEnvironment = struct {
     fn dependency(env: *BuildEnvironment, name: []const u8, args: anytype) *std.Build.Dependency {
         return env.self.builder.dependency(name, args);
     }
-};
 
-////////////////////////////////////////
-//      MicroZig Gen 2 Interface      //
-////////////////////////////////////////
+    fn generateLinkerScript(env: *BuildEnvironment, chip: Chip) !std.Build.LazyPath {
+        const cpu = env.getCpuDescriptor(chip.cpu);
+
+        var contents = std.ArrayList(u8).init(env.host_build.allocator);
+        const writer = contents.writer();
+        try writer.print(
+            \\/*
+            \\ * This file was auto-generated by microzig
+            \\ *
+            \\ * Target CPU:  {[cpu]s}
+            \\ * Target Chip: {[chip]s}
+            \\ */
+            \\
+            // This is not the "true" entry point, but there's no such thing on embedded platforms
+            // anyways. This is the logical entrypoint that should be invoked when
+            // stack, .data and .bss are set up and the CPU is ready to be used.
+            \\ENTRY(microzig_main);
+            \\
+            \\
+        , .{
+            .cpu = cpu.name,
+            .chip = chip.name,
+        });
 
-fn root() []const u8 {
-    return comptime (std.fs.path.dirname(@src().file) orelse ".");
-}
-const build_root = root();
+        try writer.writeAll("MEMORY\n{\n");
+        {
+            var counters = [4]usize{ 0, 0, 0, 0 };
+            for (chip.memory_regions) |region| {
+                // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k
 
-const MicroZig = @This();
+                switch (region.kind) {
+                    .flash => {
+                        try writer.print("  flash{d}    (rx!w)", .{counters[0]});
+                        counters[0] += 1;
+                    },
 
-b: *std.Build,
-self: *std.Build.Dependency,
+                    .ram => {
+                        try writer.print("  ram{d}      (rw!x)", .{counters[1]});
+                        counters[1] += 1;
+                    },
 
-/// Creates a new instance of the MicroZig build support.
-///
-/// This is necessary as we need to keep track of some internal state to prevent
-/// duplicated work per firmware built.
-pub fn init(b: *std.Build, dependency_name: []const u8) *MicroZig {
-    const mz = b.allocator.create(MicroZig) catch @panic("out of memory");
-    mz.* = MicroZig{
-        .b = b,
-        .self = b.dependency(dependency_name, .{}),
-    };
-    return mz;
-}
+                    .io => {
+                        try writer.print("  io{d}       (rw!x)", .{counters[2]});
+                        counters[2] += 1;
+                    },
 
-/// This build script validates usage patterns we expect from MicroZig
-pub fn build(b: *std.Build) !void {
-    const uf2_dep = b.dependency("uf2", .{});
+                    .reserved => {
+                        try writer.print("  reserved{d} (rw!x)", .{counters[3]});
+                        counters[3] += 1;
+                    },
 
-    const build_test = b.addTest(.{
-        .root_source_file = .{ .path = "build.zig" },
-    });
+                    .private => |custom| {
+                        try writer.print("  {s} (", .{custom.name});
+                        if (custom.readable) try writer.writeAll("r");
+                        if (custom.writeable) try writer.writeAll("w");
+                        if (custom.executable) try writer.writeAll("x");
+
+                        if (!custom.readable or !custom.writeable or !custom.executable) {
+                            try writer.writeAll("!");
+                            if (!custom.readable) try writer.writeAll("r");
+                            if (!custom.writeable) try writer.writeAll("w");
+                            if (!custom.executable) try writer.writeAll("x");
+                        }
+                        try writer.writeAll(")");
+                    },
+                }
+                try writer.print(" : ORIGIN = 0x{X:0>8}, LENGTH = 0x{X:0>8}\n", .{ region.offset, region.length });
+            }
+        }
 
-    build_test.addAnonymousModule("uf2", .{
-        .source_file = .{ .cwd_relative = uf2_dep.builder.pathFromRoot("build.zig") },
-    });
+        try writer.writeAll("}\n\nSECTIONS\n{\n");
+        {
+            try writer.writeAll(
+                \\  .text :
+                \\  {
+                \\     KEEP(*(microzig_flash_start))
+                \\     *(.text*)
+                \\  } > flash0
+                \\
+                \\
+            );
+
+            switch (cpu.target.getCpuArch()) {
+                .arm, .thumb => try writer.writeAll(
+                    \\  .ARM.exidx : {
+                    \\      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+                    \\  } >flash0
+                    \\
+                    \\
+                ),
+                else => {},
+            }
 
-    const install_docs = b.addInstallDirectory(.{
-        .source_dir = build_test.getEmittedDocs(),
-        .install_dir = .prefix,
-        .install_subdir = "docs",
-    });
+            try writer.writeAll(
+                \\  .data :
+                \\  {
+                \\     microzig_data_start = .;
+                \\     *(.rodata*)
+                \\     *(.data*)
+                \\     microzig_data_end = .;
+                \\  } > ram0 AT> flash0
+                \\
+                \\  .bss (NOLOAD) :
+                \\  {
+                \\      microzig_bss_start = .;
+                \\      *(.bss*)
+                \\      microzig_bss_end = .;
+                \\  } > ram0
+                \\
+                \\  microzig_data_load_start = LOADADDR(.data);
+                \\
+            );
+        }
+        try writer.writeAll("}\n");
 
-    b.getInstallStep().dependOn(&install_docs.step);
+        // TODO: Assert that the flash can actually hold all data!
+        // try writer.writeAll(
+        //     \\
+        //     \\  ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" );
+        //     \\
+        // );
+
+        const write = env.host_build.addWriteFiles();
+
+        return write.add("linker.ld", contents.items);
+    }
+};
 
-    // const backings = @import("test/backings.zig");
-    // const optimize = b.standardOptimizeOption(.{});
-
-    // const minimal = addEmbeddedExecutable(b, .{
-    //     .name = "minimal",
-    //     .source_file = .{
-    //         .path = comptime root_dir() ++ "/test/programs/minimal.zig",
-    //     },
-    //     .backing = backings.minimal,
-    //     .optimize = optimize,
-    // });
-
-    // const has_hal = addEmbeddedExecutable(b, .{
-    //     .name = "has_hal",
-    //     .source_file = .{
-    //         .path = comptime root_dir() ++ "/test/programs/has_hal.zig",
-    //     },
-    //     .backing = backings.has_hal,
-    //     .optimize = optimize,
-    // });
-
-    // const has_board = addEmbeddedExecutable(b, .{
-    //     .name = "has_board",
-    //     .source_file = .{
-    //         .path = comptime root_dir() ++ "/test/programs/has_board.zig",
-    //     },
-    //     .backing = backings.has_board,
-    //     .optimize = optimize,
-    // });
-
-    // const core_tests = b.addTest(.{
-    //     .root_source_file = .{
-    //         .path = comptime root_dir() ++ "/src/core.zig",
-    //     },
-    //     .optimize = optimize,
-    // });
-
-    // const test_step = b.step("test", "build test programs");
-    // test_step.dependOn(&minimal.inner.step);
-    // test_step.dependOn(&has_hal.inner.step);
-    // test_step.dependOn(&has_board.inner.step);
-    // test_step.dependOn(&b.addRunArtifact(core_tests).step);
+////////////////////////////////////////
+//      MicroZig Gen 2 Interface      //
+////////////////////////////////////////
+
+fn root() []const u8 {
+    return comptime (std.fs.path.dirname(@src().file) orelse ".");
 }
+const build_root = root();
+
+const MicroZig = @This();
 
 /// The resulting binary format for the firmware file.
 /// A lot of embedded systems don't use plain ELF files, thus we provide means
@@ -602,17 +758,12 @@ pub const CpuModel = union(enum) {
     cortex_m3,
     cortex_m4,
     riscv32_imac,
-
     custom: *const Cpu,
-
-    pub fn getDescriptor(model: CpuModel) *const Cpu {
-        return switch (@as(std.meta.Tag(CpuModel), model)) {
-            inline else => |tag| &@field(cpus, @tagName(tag)),
-            .custom => model.custom,
-        };
-    }
 };
 
+/// Tag of CpuModel
+pub const CpuType = std.meta.Tag(CpuModel);
+
 /// A cpu descriptor.
 pub const Cpu = struct {
     /// Display name of the CPU.
@@ -761,7 +912,7 @@ pub const Target = struct {
 
     /// (optional) Further configures the created firmware depending on the chip and/or board settings.
     /// This can be used to set/change additional properties on the created `*Firmware` object.
-    configure: ?*const fn (host_build: *std.Build, *Firmware) void = null,
+    configure: ?*const fn (env: *BuildEnvironment, *Firmware) void = null,
 
     /// (optional) Post processing step that will patch up and modify the elf file if necessary.
     binary_post_process: ?*const fn (host_build: *std.Build, std.Build.LazyPath) std.Build.LazyPath = null,
@@ -965,202 +1116,7 @@ pub const Firmware = struct {
     }
 };
 
-pub const cpus = struct {
-    pub const avr5 = Cpu{
-        .name = "AVR5",
-        .source_file = .{ .path = build_root ++ "/src/cpus/avr5.zig" },
-        .target = std.zig.CrossTarget{
-            .cpu_arch = .avr,
-            .cpu_model = .{ .explicit = &std.Target.avr.cpu.avr5 },
-            .os_tag = .freestanding,
-            .abi = .eabi,
-        },
-    };
-
-    pub const cortex_m0 = Cpu{
-        .name = "ARM Cortex-M0",
-        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
-        .target = std.zig.CrossTarget{
-            .cpu_arch = .thumb,
-            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0 },
-            .os_tag = .freestanding,
-            .abi = .eabi,
-        },
-    };
-
-    pub const cortex_m0plus = Cpu{
-        .name = "ARM Cortex-M0+",
-        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
-        .target = std.zig.CrossTarget{
-            .cpu_arch = .thumb,
-            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m0plus },
-            .os_tag = .freestanding,
-            .abi = .eabi,
-        },
-    };
-
-    pub const cortex_m3 = Cpu{
-        .name = "ARM Cortex-M3",
-        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
-        .target = std.zig.CrossTarget{
-            .cpu_arch = .thumb,
-            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m3 },
-            .os_tag = .freestanding,
-            .abi = .eabi,
-        },
-    };
-
-    pub const cortex_m4 = Cpu{
-        .name = "ARM Cortex-M4",
-        .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
-        .target = std.zig.CrossTarget{
-            .cpu_arch = .thumb,
-            .cpu_model = .{ .explicit = &std.Target.arm.cpu.cortex_m4 },
-            .os_tag = .freestanding,
-            .abi = .eabi,
-        },
-    };
-
-    pub const riscv32_imac = Cpu{
-        .name = "RISC-V 32-bit",
-        .source_file = .{ .path = build_root ++ "/src/cpus/riscv32.zig" },
-        .target = std.zig.CrossTarget{
-            .cpu_arch = .riscv32,
-            .cpu_model = .{ .explicit = &std.Target.riscv.cpu.sifive_e21 },
-            .os_tag = .freestanding,
-            .abi = .none,
-        },
-    };
-};
-
 fn buildConfigError(b: *std.Build, comptime fmt: []const u8, args: anytype) noreturn {
     const msg = b.fmt(fmt, args);
     @panic(msg);
 }
-
-fn generateLinkerScript(b: *std.Build, chip: Chip) !std.Build.LazyPath {
-    const cpu = chip.cpu.getDescriptor();
-
-    var contents = std.ArrayList(u8).init(b.allocator);
-    const writer = contents.writer();
-    try writer.print(
-        \\/*
-        \\ * This file was auto-generated by microzig
-        \\ *
-        \\ * Target CPU:  {[cpu]s}
-        \\ * Target Chip: {[chip]s}
-        \\ */
-        \\
-        // This is not the "true" entry point, but there's no such thing on embedded platforms
-        // anyways. This is the logical entrypoint that should be invoked when
-        // stack, .data and .bss are set up and the CPU is ready to be used.
-        \\ENTRY(microzig_main);
-        \\
-        \\
-    , .{
-        .cpu = cpu.name,
-        .chip = chip.name,
-    });
-
-    try writer.writeAll("MEMORY\n{\n");
-    {
-        var counters = [4]usize{ 0, 0, 0, 0 };
-        for (chip.memory_regions) |region| {
-            // flash (rx!w) : ORIGIN = 0x00000000, LENGTH = 512k
-
-            switch (region.kind) {
-                .flash => {
-                    try writer.print("  flash{d}    (rx!w)", .{counters[0]});
-                    counters[0] += 1;
-                },
-
-                .ram => {
-                    try writer.print("  ram{d}      (rw!x)", .{counters[1]});
-                    counters[1] += 1;
-                },
-
-                .io => {
-                    try writer.print("  io{d}       (rw!x)", .{counters[2]});
-                    counters[2] += 1;
-                },
-
-                .reserved => {
-                    try writer.print("  reserved{d} (rw!x)", .{counters[3]});
-                    counters[3] += 1;
-                },
-
-                .private => |custom| {
-                    try writer.print("  {s} (", .{custom.name});
-                    if (custom.readable) try writer.writeAll("r");
-                    if (custom.writeable) try writer.writeAll("w");
-                    if (custom.executable) try writer.writeAll("x");
-
-                    if (!custom.readable or !custom.writeable or !custom.executable) {
-                        try writer.writeAll("!");
-                        if (!custom.readable) try writer.writeAll("r");
-                        if (!custom.writeable) try writer.writeAll("w");
-                        if (!custom.executable) try writer.writeAll("x");
-                    }
-                    try writer.writeAll(")");
-                },
-            }
-            try writer.print(" : ORIGIN = 0x{X:0>8}, LENGTH = 0x{X:0>8}\n", .{ region.offset, region.length });
-        }
-    }
-
-    try writer.writeAll("}\n\nSECTIONS\n{\n");
-    {
-        try writer.writeAll(
-            \\  .text :
-            \\  {
-            \\     KEEP(*(microzig_flash_start))
-            \\     *(.text*)
-            \\  } > flash0
-            \\
-            \\
-        );
-
-        switch (cpu.target.getCpuArch()) {
-            .arm, .thumb => try writer.writeAll(
-                \\  .ARM.exidx : {
-                \\      *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-                \\  } >flash0
-                \\
-                \\
-            ),
-            else => {},
-        }
-
-        try writer.writeAll(
-            \\  .data :
-            \\  {
-            \\     microzig_data_start = .;
-            \\     *(.rodata*)
-            \\     *(.data*)
-            \\     microzig_data_end = .;
-            \\  } > ram0 AT> flash0
-            \\
-            \\  .bss (NOLOAD) :
-            \\  {
-            \\      microzig_bss_start = .;
-            \\      *(.bss*)
-            \\      microzig_bss_end = .;
-            \\  } > ram0
-            \\
-            \\  microzig_data_load_start = LOADADDR(.data);
-            \\
-        );
-    }
-    try writer.writeAll("}\n");
-
-    // TODO: Assert that the flash can actually hold all data!
-    // try writer.writeAll(
-    //     \\
-    //     \\  ASSERT( (SIZEOF(.text) + SIZEOF(.data) > LENGTH(flash0)), "Error: .text + .data is too large for flash!" );
-    //     \\
-    // );
-
-    const write = b.addWriteFiles();
-
-    return write.add("linker.ld", contents.items);
-}
diff --git a/core/build.zig b/core/build.zig
index 033709021..2d6008f64 100644
--- a/core/build.zig
+++ b/core/build.zig
@@ -13,70 +13,10 @@ const build_root = root();
 /// This build script validates usage patterns we expect from MicroZig
 pub fn build(b: *std.Build) !void {
     _ = b;
-    // const uf2_dep = b.dependency("uf2", .{});
-
-    // const build_test = b.addTest(.{
-    //     .root_source_file = .{ .path = "build.zig" },
-    // });
-
-    // build_test.addAnonymousModule("uf2", .{
-    //     .source_file = .{ .cwd_relative = uf2_dep.builder.pathFromRoot("build.zig") },
-    // });
-
-    // const install_docs = b.addInstallDirectory(.{
-    //     .source_dir = build_test.getEmittedDocs(),
-    //     .install_dir = .prefix,
-    //     .install_subdir = "docs",
-    // });
-
-    // b.getInstallStep().dependOn(&install_docs.step);
-
-    // const backings = @import("test/backings.zig");
-    // const optimize = b.standardOptimizeOption(.{});
-
-    // const minimal = addEmbeddedExecutable(b, .{
-    //     .name = "minimal",
-    //     .source_file = .{
-    //         .path = comptime root_dir() ++ "/test/programs/minimal.zig",
-    //     },
-    //     .backing = backings.minimal,
-    //     .optimize = optimize,
-    // });
-
-    // const has_hal = addEmbeddedExecutable(b, .{
-    //     .name = "has_hal",
-    //     .source_file = .{
-    //         .path = comptime root_dir() ++ "/test/programs/has_hal.zig",
-    //     },
-    //     .backing = backings.has_hal,
-    //     .optimize = optimize,
-    // });
-
-    // const has_board = addEmbeddedExecutable(b, .{
-    //     .name = "has_board",
-    //     .source_file = .{
-    //         .path = comptime root_dir() ++ "/test/programs/has_board.zig",
-    //     },
-    //     .backing = backings.has_board,
-    //     .optimize = optimize,
-    // });
-
-    // const core_tests = b.addTest(.{
-    //     .root_source_file = .{
-    //         .path = comptime root_dir() ++ "/src/core.zig",
-    //     },
-    //     .optimize = optimize,
-    // });
-
-    // const test_step = b.step("test", "build test programs");
-    // test_step.dependOn(&minimal.inner.step);
-    // test_step.dependOn(&has_hal.inner.step);
-    // test_step.dependOn(&has_board.inner.step);
-    // test_step.dependOn(&b.addRunArtifact(core_tests).step);
 }
 
-pub const cpus = struct {
-    pub const avr5 = microbuild.Cpu{
+pub const cpus = microbuild.CpuArray.init(.{
+    .avr5 = microbuild.Cpu{
         .name = "AVR5",
         .source_file = .{ .path = build_root ++ "/src/cpus/avr5.zig" },
         .target = std.zig.CrossTarget{
@@ -85,9 +25,9 @@ pub const cpus = struct {
             .os_tag = .freestanding,
             .abi = .eabi,
         },
-    };
+    },
 
-    pub const cortex_m0 = microbuild.Cpu{
+    .cortex_m0 = microbuild.Cpu{
         .name = "ARM Cortex-M0",
         .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
         .target = std.zig.CrossTarget{
@@ -96,9 +36,9 @@ pub const cpus = struct {
             .os_tag = .freestanding,
             .abi = .eabi,
         },
-    };
+    },
 
-    pub const cortex_m0plus = microbuild.Cpu{
+    .cortex_m0plus = microbuild.Cpu{
         .name = "ARM Cortex-M0+",
         .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
         .target = std.zig.CrossTarget{
@@ -107,9 +47,9 @@ pub const cpus = struct {
             .os_tag = .freestanding,
             .abi = .eabi,
         },
-    };
+    },
 
-    pub const cortex_m3 = microbuild.Cpu{
+    .cortex_m3 = microbuild.Cpu{
         .name = "ARM Cortex-M3",
         .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
         .target = std.zig.CrossTarget{
@@ -118,9 +58,9 @@ pub const cpus = struct {
             .os_tag = .freestanding,
             .abi = .eabi,
         },
-    };
+    },
 
-    pub const cortex_m4 = microbuild.Cpu{
+    .cortex_m4 = microbuild.Cpu{
         .name = "ARM Cortex-M4",
         .source_file = .{ .path = build_root ++ "/src/cpus/cortex-m.zig" },
         .target = std.zig.CrossTarget{
@@ -129,9 +69,9 @@ pub const cpus = struct {
             .os_tag = .freestanding,
             .abi = .eabi,
         },
-    };
+    },
 
-    pub const riscv32_imac = microbuild.Cpu{
+    .riscv32_imac = microbuild.Cpu{
         .name = "RISC-V 32-bit",
         .source_file = .{ .path = build_root ++ "/src/cpus/riscv32.zig" },
         .target = std.zig.CrossTarget{
@@ -140,5 +80,7 @@ pub const cpus = struct {
             .os_tag = .freestanding,
             .abi = .none,
         },
-    };
-};
+    },
+
+    .custom = undefined,
+});
diff --git a/examples/next-gen/build.zig.zon b/examples/next-gen/build.zig.zon
index 90539673b..ce5dbe80d 100644
--- a/examples/next-gen/build.zig.zon
+++ b/examples/next-gen/build.zig.zon
@@ -4,19 +4,19 @@
     .dependencies = .{
         .microzig = .{
             .url = "https://public.devspace.random-projects.net/microzig-build.tar.gz",
-            .hash = "1220c87cc608598bdb4ae5ed6436c6fa3e126c57d3d1bbfaf01625c3af0c15da44e4",
+            .hash = "12208fcae95a6d3bc80301bfbabe9f937cf299188f44bed100f61e39437d8fc4a49a",
         },
         .@"microzig-core" = .{
             .url = "https://public.devspace.random-projects.net/microzig-core.tar.gz",
-            .hash = "1220a37d914f0585bbaeba2bc4d4d15586bef310a6af340af87f0e13fde0b4ddfb1a",
+            .hash = "122085d8c30906f461a3aecb54eb0dadb644c25724b0eb2d3fc89f1f4c3a8d411be2",
         },
         .@"microzig-bsp-nxp" = .{
             .url = "https://public.devspace.random-projects.net/board-support/nxp/lpc.tar.gz",
-            .hash = "122040dc9467f6dac90a1376fff25350b2a5abd291904db7bea48a78db4f6e6dff13",
+            .hash = "12201530a2d4d2751a5bc93720d3a3d6eab0349cc271004102bcc470beffb02c7e84",
         },
         .@"microzig-bsp-rp2040" = .{
             .url = "https://public.devspace.random-projects.net/board-support/raspberrypi/rp2040.tar.gz",
-            .hash = "1220142a13e590252deb7667569bdd3f6147c5b461f6b0343a825079a7dd3a24dea9",
+            .hash = "1220817e39ac34923bae65047afc344706c11e7dd054efee3ca31ff78adc78a4e0f6",
         },
     },
 }
\ No newline at end of file
diff --git a/tools/bundle.py b/tools/bundle.py
index e00cda07f..eebb21578 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -145,7 +145,7 @@ def execute_raw(*args,hide_stderr = False,**kwargs):
         sys.stderr.buffer.write(res.stderr)
     if res.returncode != 0:
         sys.stderr.write(f"command {' '.join(args)} failed with exit code {res.returncode}")
-    res.check_returncode()
+        sys.exit(res.returncode)
     return res 
 
 def execute(*args,**kwargs):
diff --git a/tools/extract-bsp-info.zig b/tools/extract-bsp-info.zig
index 4c2b26091..a157be7ab 100644
--- a/tools/extract-bsp-info.zig
+++ b/tools/extract-bsp-info.zig
@@ -7,6 +7,11 @@ const std = @import("std");
 const bsp = @import("bsp");
 const microzig = @import("microzig-build");
 
+// Fake build_runner.zig api:
+pub const dependencies = struct {
+    pub const imports = struct {};
+};
+
 const JsonTarget = struct {
     id: []const u8,
 

From b1e189b4f463a21d98d84f3ddbd19ed47201e6c5 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Wed, 24 Jan 2024 12:52:47 +0100
Subject: [PATCH 263/286] Adds step/option for printing the available targets,
 shortens target list.

---
 build/build.zig                 | 87 +++++++++++++++++++++++++++++----
 examples/next-gen/build.zig     | 12 ++---
 examples/next-gen/build.zig.zon |  8 +--
 3 files changed, 86 insertions(+), 21 deletions(-)

diff --git a/build/build.zig b/build/build.zig
index 815055157..272bd6952 100644
--- a/build/build.zig
+++ b/build/build.zig
@@ -246,22 +246,66 @@ pub fn createBuildEnvironment(b: *std.Build, comptime info: EnvironmentInfo) *Bu
         .self_pkg_name = comptime info.self,
         .core_pkg_name = comptime info.core,
         .cpus = &core_module.cpus,
+
+        .show_targets_step = std.Build.Step.init(.{
+            .id = .custom,
+            .name = "Show MicroZig targets",
+            .owner = b,
+            .makeFn = BuildEnvironment.print_target_steps,
+            .first_ret_addr = null,
+        }),
     };
 
     be.self = b.dependency(info.self, .{});
     be.microzig_core = b.dependency(info.core, .{});
 
-    inline for (be.board_support_packages, requested_bsps) |*bsp, def| {
-        bsp.* = BoardSupportPackage{
-            .name = def.import_name,
-            .dep = b.dependency(def.import_name, .{}),
-        };
+    // Fetch all available board support packages and targets:
+    {
+        var duplicate_package_names = std.StringArrayHashMap(void).init(be.host_build.allocator);
+        defer duplicate_package_names.deinit();
+
+        inline for (be.board_support_packages, requested_bsps) |*bsp, def| {
+            bsp.* = BoardSupportPackage{
+                .name = def.import_name,
+                .dep = b.dependency(def.import_name, .{}),
+            };
+
+            for (def.bsp.targets) |tgt| {
+                const full_name = b.fmt("{s}#{s}", .{ tgt.id, def.import_name });
+
+                const old_value = be.targets.fetchPut(be.host_build.allocator, tgt.id, tgt.target) catch @panic("out of memory");
+                be.targets.put(be.host_build.allocator, full_name, tgt.target) catch @panic("out of memory");
+
+                if (old_value != null) {
+                    duplicate_package_names.put(tgt.id, {}) catch @panic("out of memory");
+                }
+            }
+        }
+
+        // Remove all non-unique packages from the list as they are ambigious:
+        for (duplicate_package_names.keys()) |key| {
+            _ = be.targets.orderedRemove(key);
+        }
+
+        // reuse set to store names of unique long names
+        duplicate_package_names.clearRetainingCapacity();
+
+        // Find all elements where only a single non-hashed variant exists:
+        for (be.targets.keys()) |long_value| {
+            const index = std.mem.indexOfScalar(u8, long_value, '#') orelse continue;
 
-        for (def.bsp.targets) |tgt| {
-            const full_name = b.fmt("{s}#{s}", .{ tgt.id, def.import_name });
+            const short_value = long_value[0..index];
 
-            be.targets.put(be.host_build.allocator, tgt.id, tgt.target) catch @panic("out of memory");
-            be.targets.put(be.host_build.allocator, full_name, tgt.target) catch @panic("out of memory");
+            if (be.targets.get(short_value) != null) {
+                // If we have the short variant, we don't have a duplicate anymore, so
+                // let's drop the long variant:
+                duplicate_package_names.put(long_value, {}) catch @panic("out of memory");
+            }
+        }
+
+        // Drop all unnecessary long variants:
+        for (duplicate_package_names.keys()) |key| {
+            _ = be.targets.orderedRemove(key);
         }
     }
 
@@ -288,11 +332,18 @@ pub const BuildEnvironment = struct {
 
     cpus: *const CpuArray,
 
+    show_targets_step: std.Build.Step,
+
     /// Searches for a target called `name` and returns a pointer to the MicroZig Target if it exists.
     pub fn findTarget(env: *const BuildEnvironment, name: []const u8) ?*const Target {
         return env.targets.getPtr(name);
     }
 
+    /// Returns a slice to all available target names.
+    pub fn getTargetNames(env: *const BuildEnvironment) []const []const u8 {
+        return env.targets.keys();
+    }
+
     /// Returns the instance to the CPU descriptor for the given CPU model.
     pub fn getCpuDescriptor(env: *BuildEnvironment, model: CpuModel) *const Cpu {
         return if (model == .custom)
@@ -301,6 +352,13 @@ pub const BuildEnvironment = struct {
             env.cpus.getPtrConst(model);
     }
 
+    /// Returns a build step that will print all available targets to this instance.
+    ///
+    /// Can be used to provide a list to the user or developer.
+    pub fn getShowTargetsStep(env: *BuildEnvironment) *std.Build.Step {
+        return &env.show_targets_step;
+    }
+
     /// Declares a new MicroZig firmware file.
     pub fn addFirmware(
         /// The MicroZig instance that should be used to create the firmware.
@@ -640,6 +698,17 @@ pub const BuildEnvironment = struct {
 
         return write.add("linker.ld", contents.items);
     }
+
+    fn print_target_steps(step: *std.Build.Step, prog_node: *std.Progress.Node) !void {
+        _ = prog_node;
+
+        const env = @fieldParentPtr(BuildEnvironment, "show_targets_step", step);
+
+        std.debug.print("Available MicroZig targets:\n", .{});
+        for (env.targets.keys()) |listed_target_name| {
+            std.debug.print("* {s}\n", .{listed_target_name});
+        }
+    }
 };
 
 ////////////////////////////////////////
diff --git a/examples/next-gen/build.zig b/examples/next-gen/build.zig
index 0c3579e3f..2c500c32e 100644
--- a/examples/next-gen/build.zig
+++ b/examples/next-gen/build.zig
@@ -2,18 +2,14 @@ const std = @import("std");
 const MicroZig = @import("microzig");
 
 pub fn build(b: *std.Build) void {
-    const microzig = MicroZig.createBuildEnvironment(b, .{
-        .self = "microzig", // package name of the build package (optional)
-        .core = "microzig-core", // package name of the core package (optional)
-    });
+    const microzig = MicroZig.createBuildEnvironment(b, .{});
+
+    const show_targets_step = b.step("show-targets", "Shows all available MicroZig targets");
+    show_targets_step.dependOn(microzig.getShowTargetsStep());
 
     const optimize = b.standardOptimizeOption(.{});
     const target_name = b.option([]const u8, "target", "Select the target to build for.") orelse "board:mbed/lpc1768";
 
-    for (microzig.targets.keys()) |listed_target_name| {
-        std.debug.print("- '{s}'\n", .{listed_target_name});
-    }
-
     const target = microzig.findTarget(target_name).?;
 
     const firmware = microzig.addFirmware(b, .{
diff --git a/examples/next-gen/build.zig.zon b/examples/next-gen/build.zig.zon
index ce5dbe80d..d587aec33 100644
--- a/examples/next-gen/build.zig.zon
+++ b/examples/next-gen/build.zig.zon
@@ -4,19 +4,19 @@
     .dependencies = .{
         .microzig = .{
             .url = "https://public.devspace.random-projects.net/microzig-build.tar.gz",
-            .hash = "12208fcae95a6d3bc80301bfbabe9f937cf299188f44bed100f61e39437d8fc4a49a",
+            .hash = "122001f3340f37dd4d80e0942407a503e6a429d7c92a05221a3e301b947782933bdb",
         },
         .@"microzig-core" = .{
             .url = "https://public.devspace.random-projects.net/microzig-core.tar.gz",
-            .hash = "122085d8c30906f461a3aecb54eb0dadb644c25724b0eb2d3fc89f1f4c3a8d411be2",
+            .hash = "1220460c2625fb17a075b17f720f275d814544e1f20a8f89e7e542ff3e0d697111bc",
         },
         .@"microzig-bsp-nxp" = .{
             .url = "https://public.devspace.random-projects.net/board-support/nxp/lpc.tar.gz",
-            .hash = "12201530a2d4d2751a5bc93720d3a3d6eab0349cc271004102bcc470beffb02c7e84",
+            .hash = "122005a181f1d51aaffd02748ab5d910597f328a12b37e68dc5a1993716d9888ccc5",
         },
         .@"microzig-bsp-rp2040" = .{
             .url = "https://public.devspace.random-projects.net/board-support/raspberrypi/rp2040.tar.gz",
-            .hash = "1220817e39ac34923bae65047afc344706c11e7dd054efee3ca31ff78adc78a4e0f6",
+            .hash = "122094dceb25e3664b96a6b482529fdc254582048d82fcec7126678e5e021b26af2c",
         },
     },
 }
\ No newline at end of file

From d2c46f3d66a15dc7941bf0c3a25b28fd6bfe96bc Mon Sep 17 00:00:00 2001
From: Tobias Kohlbau 
Date: Sat, 3 Feb 2024 10:09:32 +0100
Subject: [PATCH 264/286] rework raspberry pico examples

Rework raspberry pico examples to support new
microzig architecture. This involves using newly
added target selection by bsp projects.

Signed-off-by: Tobias Kohlbau 
---
 examples/raspberrypi-rp2040/build.zig     | 48 +++++++++++------------
 examples/raspberrypi-rp2040/build.zig.zon | 14 ++++---
 2 files changed, 33 insertions(+), 29 deletions(-)

diff --git a/examples/raspberrypi-rp2040/build.zig b/examples/raspberrypi-rp2040/build.zig
index 6e91de005..ba67302a5 100644
--- a/examples/raspberrypi-rp2040/build.zig
+++ b/examples/raspberrypi-rp2040/build.zig
@@ -1,34 +1,34 @@
 const std = @import("std");
-const rp2040 = @import("rp2040");
+const rp2040 = @import("microzig-bsp-rp2040");
+const MicroZig = @import("microzig");
 
 const available_examples = [_]Example{
-    .{ .name = "pico_adc", .target = rp2040.boards.raspberry_pi.pico, .file = "src/adc.zig" },
-    .{ .name = "pico_blinky", .target = rp2040.boards.raspberry_pi.pico, .file = "src/blinky.zig" },
-    // TODO: Fix multicore hal! .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico , .file = "src/blinky_core1.zig" },
-    .{ .name = "pico_flash-program", .target = rp2040.boards.raspberry_pi.pico, .file = "src/flash_program.zig" },
-    .{ .name = "pico_gpio-clk", .target = rp2040.boards.raspberry_pi.pico, .file = "src/gpio_clk.zig" },
-    .{ .name = "pico_i2c-bus-scan", .target = rp2040.boards.raspberry_pi.pico, .file = "src/i2c_bus_scan.zig" },
-    .{ .name = "pico_pwm", .target = rp2040.boards.raspberry_pi.pico, .file = "src/pwm.zig" },
-    .{ .name = "pico_random", .target = rp2040.boards.raspberry_pi.pico, .file = "src/random.zig" },
-    .{ .name = "pico_spi-master", .target = rp2040.boards.raspberry_pi.pico, .file = "src/spi_master.zig" },
-    .{ .name = "pico_squarewave", .target = rp2040.boards.raspberry_pi.pico, .file = "src/squarewave.zig" },
-    .{ .name = "pico_uart", .target = rp2040.boards.raspberry_pi.pico, .file = "src/uart.zig" },
-    .{ .name = "pico_usb-device", .target = rp2040.boards.raspberry_pi.pico, .file = "src/usb_device.zig" },
-    .{ .name = "pico_usb-hid", .target = rp2040.boards.raspberry_pi.pico, .file = "src/usb_hid.zig" },
-    .{ .name = "pico_ws2812", .target = rp2040.boards.raspberry_pi.pico, .file = "src/ws2812.zig" },
-
-    .{ .name = "rp2040-matrix_tiles", .target = rp2040.boards.waveshare.rp2040_matrix, .file = "src/tiles.zig" },
-
-    //     .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
-    //     .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
-    //     .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
+    .{ .name = "pico_adc", .target = "board:raspberry_pi/pico", .file = "src/adc.zig" },
+    .{ .name = "pico_blinky", .target = "board:raspberry_pi/pico", .file = "src/blinky.zig" },
+    // TODO: Fix multicore hal! .{ .name = "pico", .target = "board:raspberry_pi/pico", .file = "src/blinky_core1.zig" },
+    .{ .name = "pico_flash-program", .target = "board:raspberry_pi/pico", .file = "src/flash_program.zig" },
+    .{ .name = "pico_gpio-clk", .target = "board:raspberry_pi/pico", .file = "src/gpio_clk.zig" },
+    .{ .name = "pico_i2c-bus-scan", .target = "board:raspberry_pi/pico", .file = "src/i2c_bus_scan.zig" },
+    .{ .name = "pico_pwm", .target = "board:raspberry_pi/pico", .file = "src/pwm.zig" },
+    .{ .name = "pico_random", .target = "board:raspberry_pi/pico", .file = "src/random.zig" },
+    .{ .name = "pico_spi-master", .target = "board:raspberry_pi/pico", .file = "src/spi_master.zig" },
+    .{ .name = "pico_squarewave", .target = "board:raspberry_pi/pico", .file = "src/squarewave.zig" },
+    .{ .name = "pico_uart", .target = "board:raspberry_pi/pico", .file = "src/uart.zig" },
+    .{ .name = "pico_usb-device", .target = "board:raspberry_pi/pico", .file = "src/usb_device.zig" },
+    .{ .name = "pico_usb-hid", .target = "board:raspberry_pi/pico", .file = "src/usb_hid.zig" },
+    .{ .name = "pico_ws2812", .target = "board:raspberry_pi/pico", .file = "src/ws2812.zig" },
+
+    .{ .name = "rp2040-matrix_tiles", .target = "board:waveshare/rp2040_matrix", .file = "src/tiles.zig" },
 };
 
 pub fn build(b: *std.Build) void {
-    const microzig = @import("microzig").init(b, "microzig");
+    const microzig = MicroZig.createBuildEnvironment(b, .{});
+
     const optimize = b.standardOptimizeOption(.{});
 
     for (available_examples) |example| {
+        const target = microzig.findTarget(example.target).?;
+
         // `addFirmware` basically works like addExecutable, but takes a
         // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
         //
@@ -36,7 +36,7 @@ pub fn build(b: *std.Build) void {
         // cpu and potentially the board as well.
         const firmware = microzig.addFirmware(b, .{
             .name = example.name,
-            .target = example.target,
+            .target = target,
             .optimize = optimize,
             .source_file = .{ .path = example.file },
         });
@@ -53,7 +53,7 @@ pub fn build(b: *std.Build) void {
 }
 
 const Example = struct {
-    target: @import("microzig").Target,
+    target: []const u8,
     name: []const u8,
     file: []const u8,
 };
diff --git a/examples/raspberrypi-rp2040/build.zig.zon b/examples/raspberrypi-rp2040/build.zig.zon
index 255be3f0f..36711f611 100644
--- a/examples/raspberrypi-rp2040/build.zig.zon
+++ b/examples/raspberrypi-rp2040/build.zig.zon
@@ -3,12 +3,16 @@
     .version = "0.1.0",
     .dependencies = .{
         .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
-            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
+            .url = "http://localhost:8080/microzig-build.tar.gz",
+            .hash = "1220db1de385b765aa45a04719c199d7ab8306fcca6ac1a12b487ed589a69d05a665",
         },
-        .rp2040 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/raspberrypi-rp2040/archive/67d36eebb0fbd89633db1a51d6d2bcb049f2066a.tar.gz",
-            .hash = "122094bf268f45b188f3916f9e5964f4257414afaafba98a455ac47d25389a456832",
+        .@"microzig-core" = .{
+            .url = "http://localhost:8080/microzig-core.tar.gz",
+            .hash = "122006d6343021c1502ceba7948fd61ac813f2bb498a74df27a50e34398ccdfb92e3",
+        },
+        .@"microzig-bsp-rp2040" = .{
+            .url = "http://localhost:8080/board-support/raspberrypi/rp2040.tar.gz",
+            .hash = "12200319b02d9d0237984fd7acb15a4945e5547b750e0a3309d13d62440983b5b67f",
         },
     },
 }

From b26ccf66458144a51af058feb423a399722d1e99 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 3 Feb 2024 10:16:26 +0100
Subject: [PATCH 265/286] Adds new structure for output: split into /examples/
 and /packages/

---
 build/build.zig                      |  2 +-
 examples/espressif-esp/build.zig.zon | 16 ++++++++++------
 examples/next-gen/build.zig          |  2 +-
 examples/next-gen/build.zig.zon      | 18 +++++++++---------
 tools/bundle.py                      | 27 +++++++++++++++++++++++----
 tools/create-pkg-descriptor.zig      |  1 +
 6 files changed, 45 insertions(+), 21 deletions(-)

diff --git a/build/build.zig b/build/build.zig
index 272bd6952..7402a7262 100644
--- a/build/build.zig
+++ b/build/build.zig
@@ -182,7 +182,7 @@ fn get_declared_bsps() []const ImportedBSP {
 
 pub const EnvironmentInfo = struct {
     /// package name of the build package (optional)
-    self: []const u8 = "microzig",
+    self: []const u8 = "microzig-build",
 
     /// package name of the core package (optional)
     core: []const u8 = "microzig-core",
diff --git a/examples/espressif-esp/build.zig.zon b/examples/espressif-esp/build.zig.zon
index a729ce616..5fc8d3025 100644
--- a/examples/espressif-esp/build.zig.zon
+++ b/examples/espressif-esp/build.zig.zon
@@ -1,14 +1,18 @@
 .{
-    .name = "microzig-espressif-esp-examples",
+    .name = "microzig-nxp-lpc-examples",
     .version = "0.1.0",
     .dependencies = .{
         .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
-            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
+            .url = "https://public.devspace.random-projects.net/packages/microzig-build.tar.gz",
+            .hash = "1220db1de385b765aa45a04719c199d7ab8306fcca6ac1a12b487ed589a69d05a665",
         },
-        .esp = .{
-            .url = "https://github.com/ZigEmbeddedGroup/espressif-esp/archive/59b8ca028915c0d6224ec88dbf4db19afbb559c0.tar.gz",
-            .hash = "1220f6e5f22416fdc63442cd8869fcaa35f9abf30d878ea3d80073176677dc6f8a65",
+        .@"microzig-core" = .{
+            .url = "https://public.devspace.random-projects.net/packages/microzig-core.tar.gz",
+            .hash = "1220f72de650278d4184dd4a43992189246b520a5c137b54fca05d7a44df8b828267",
+        },
+        .@"microzig-bsp-rp2040" = .{
+            .url = "https://public.devspace.random-projects.net/packages/board-support/raspberrypi/rp2040.tar.gz",
+            .hash = "1220b170e56d2bd85b96bd8b7f40f2890cf9926da2fcb86967e466a3c87486f31c43",
         },
     },
 }
diff --git a/examples/next-gen/build.zig b/examples/next-gen/build.zig
index 2c500c32e..fe531f970 100644
--- a/examples/next-gen/build.zig
+++ b/examples/next-gen/build.zig
@@ -1,5 +1,5 @@
 const std = @import("std");
-const MicroZig = @import("microzig");
+const MicroZig = @import("microzig-build");
 
 pub fn build(b: *std.Build) void {
     const microzig = MicroZig.createBuildEnvironment(b, .{});
diff --git a/examples/next-gen/build.zig.zon b/examples/next-gen/build.zig.zon
index d587aec33..70de7cc6f 100644
--- a/examples/next-gen/build.zig.zon
+++ b/examples/next-gen/build.zig.zon
@@ -2,21 +2,21 @@
     .name = "microzig-nxp-lpc-examples",
     .version = "0.1.0",
     .dependencies = .{
-        .microzig = .{
-            .url = "https://public.devspace.random-projects.net/microzig-build.tar.gz",
-            .hash = "122001f3340f37dd4d80e0942407a503e6a429d7c92a05221a3e301b947782933bdb",
+        .@"microzig-build" = .{
+            .url = "https://public.devspace.random-projects.net/packages/microzig-build.tar.gz",
+            .hash = "1220e1f1446176832d84fa9b132022a45ea8c21fbaba8a51d787c6b4e0f1d455f4ed",
         },
         .@"microzig-core" = .{
-            .url = "https://public.devspace.random-projects.net/microzig-core.tar.gz",
-            .hash = "1220460c2625fb17a075b17f720f275d814544e1f20a8f89e7e542ff3e0d697111bc",
+            .url = "https://public.devspace.random-projects.net/packages/microzig-core.tar.gz",
+            .hash = "12207d2604083d414ff3ca7c31c5dc76ee8ac3f1292a22e40ffe8b87fcadbd2e3c7d",
         },
         .@"microzig-bsp-nxp" = .{
-            .url = "https://public.devspace.random-projects.net/board-support/nxp/lpc.tar.gz",
-            .hash = "122005a181f1d51aaffd02748ab5d910597f328a12b37e68dc5a1993716d9888ccc5",
+            .url = "https://public.devspace.random-projects.net/packages/board-support/nxp/lpc.tar.gz",
+            .hash = "1220ac0aa694eaa23cda453bb5a2711b22d8f58f10a9e0389502439cbb881987fa95",
         },
         .@"microzig-bsp-rp2040" = .{
-            .url = "https://public.devspace.random-projects.net/board-support/raspberrypi/rp2040.tar.gz",
-            .hash = "122094dceb25e3664b96a6b482529fdc254582048d82fcec7126678e5e021b26af2c",
+            .url = "https://public.devspace.random-projects.net/packages/board-support/raspberrypi/rp2040.tar.gz",
+            .hash = "12204d3998590f27f19aa31a8a250576b4314b29bbeb97628e264b42cb488ee6fad7",
         },
     },
 }
\ No newline at end of file
diff --git a/tools/bundle.py b/tools/bundle.py
index eebb21578..4878ccbb7 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -21,6 +21,7 @@
 from marshmallow import fields as mm_fields
 from typing import Optional, Any
 
+LEGAL_PACKAGE_NAME = re.compile("^[A-Za-z]$")
 
 VERBOSE = False 
 ALL_FILES_DIR=".data"
@@ -41,6 +42,7 @@ class PackageType(StrEnum):
     build = "build"
     core = "core"
     board_support = "board-support"
+    example = "example"
 
 @dataclass_json
 @dataclass
@@ -290,6 +292,9 @@ def main():
     packages = {}
     validation_ok = True
 
+    PACKAGES_ROOT = PurePosixPath("packages")
+    EXAMPLES_ROOT = PurePosixPath("examples")
+
     for meta_path in REPO_ROOT.rglob("microzig-package.json"):
         assert meta_path.is_file()
 
@@ -305,25 +310,39 @@ def main():
 
 
         if pkg.package_type == PackageType.build:
-            pkg.out_rel_dir = PurePosixPath(".")
+            pkg.out_rel_dir = PACKAGES_ROOT
             pkg.out_basename = pkg.package_name
             
         elif pkg.package_type == PackageType.core:
-            pkg.out_rel_dir = PurePosixPath(".")
+            pkg.out_rel_dir = PACKAGES_ROOT
             pkg.out_basename = pkg.package_name
             
             # Implicit dependencies:
             pkg.inner_dependencies.add("microzig-build") # core requires the build types
 
         elif pkg.package_type == PackageType.board_support:
-            parsed_pkg_name = PurePosixPath(pkg.package_name)
+            parsed_pkg_name = PurePosixPath( pkg.package_name)
 
-            pkg.out_rel_dir = "board-support" / parsed_pkg_name.parent
+            pkg.out_rel_dir = PACKAGES_ROOT / "board-support" / parsed_pkg_name.parent
             pkg.out_basename = parsed_pkg_name.name
 
             # Implicit dependencies:
             pkg.inner_dependencies.add("microzig-build") # BSPs also require build types
             pkg.inner_dependencies.add("microzig-core") # but also the core types (?)
+            
+            
+        elif pkg.package_type == PackageType.example:
+            parsed_pkg_name = PurePosixPath( pkg.package_name)
+
+            pkg.package_name = "examples:" + pkg.package_name # patch the name so we can use the same name for BSP and Example 
+
+            pkg.out_rel_dir = EXAMPLES_ROOT / parsed_pkg_name.parent
+            pkg.out_basename = parsed_pkg_name.name
+
+            # Implicit dependencies:
+            pkg.inner_dependencies.add("microzig-build") # BSPs also require build types
+            pkg.inner_dependencies.add("microzig-core") # but also the core types (?)
+
         else:
             assert False 
 
diff --git a/tools/create-pkg-descriptor.zig b/tools/create-pkg-descriptor.zig
index 70985d8bc..13dd89957 100644
--- a/tools/create-pkg-descriptor.zig
+++ b/tools/create-pkg-descriptor.zig
@@ -38,6 +38,7 @@ const MetaData = struct {
         @"board-support",
         core,
         build,
+        example,
     };
 
     package_name: []const u8,

From 243c263150e6e0edb8b6dc0617e253ae459f422b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 3 Feb 2024 10:23:44 +0100
Subject: [PATCH 266/286] Ports raspberrypi-rp2040 to microzig-package.json
 style, reorders fields to have nicer file.

---
 examples/raspberrypi-rp2040/build.zig         | 43 +++++++++++--------
 examples/raspberrypi-rp2040/build.zig.zon     | 18 --------
 .../raspberrypi-rp2040/microzig-package.json  |  7 +++
 3 files changed, 32 insertions(+), 36 deletions(-)
 delete mode 100644 examples/raspberrypi-rp2040/build.zig.zon
 create mode 100644 examples/raspberrypi-rp2040/microzig-package.json

diff --git a/examples/raspberrypi-rp2040/build.zig b/examples/raspberrypi-rp2040/build.zig
index ba67302a5..57c701313 100644
--- a/examples/raspberrypi-rp2040/build.zig
+++ b/examples/raspberrypi-rp2040/build.zig
@@ -1,24 +1,28 @@
 const std = @import("std");
-const rp2040 = @import("microzig-bsp-rp2040");
-const MicroZig = @import("microzig");
+const MicroZig = @import("microzig-build");
 
 const available_examples = [_]Example{
-    .{ .name = "pico_adc", .target = "board:raspberry_pi/pico", .file = "src/adc.zig" },
-    .{ .name = "pico_blinky", .target = "board:raspberry_pi/pico", .file = "src/blinky.zig" },
-    // TODO: Fix multicore hal! .{ .name = "pico", .target = "board:raspberry_pi/pico", .file = "src/blinky_core1.zig" },
-    .{ .name = "pico_flash-program", .target = "board:raspberry_pi/pico", .file = "src/flash_program.zig" },
-    .{ .name = "pico_gpio-clk", .target = "board:raspberry_pi/pico", .file = "src/gpio_clk.zig" },
-    .{ .name = "pico_i2c-bus-scan", .target = "board:raspberry_pi/pico", .file = "src/i2c_bus_scan.zig" },
-    .{ .name = "pico_pwm", .target = "board:raspberry_pi/pico", .file = "src/pwm.zig" },
-    .{ .name = "pico_random", .target = "board:raspberry_pi/pico", .file = "src/random.zig" },
-    .{ .name = "pico_spi-master", .target = "board:raspberry_pi/pico", .file = "src/spi_master.zig" },
-    .{ .name = "pico_squarewave", .target = "board:raspberry_pi/pico", .file = "src/squarewave.zig" },
-    .{ .name = "pico_uart", .target = "board:raspberry_pi/pico", .file = "src/uart.zig" },
-    .{ .name = "pico_usb-device", .target = "board:raspberry_pi/pico", .file = "src/usb_device.zig" },
-    .{ .name = "pico_usb-hid", .target = "board:raspberry_pi/pico", .file = "src/usb_hid.zig" },
-    .{ .name = "pico_ws2812", .target = "board:raspberry_pi/pico", .file = "src/ws2812.zig" },
-
-    .{ .name = "rp2040-matrix_tiles", .target = "board:waveshare/rp2040_matrix", .file = "src/tiles.zig" },
+    // RaspberryPi Boards:
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_adc", .file = "src/adc.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_blinky", .file = "src/blinky.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_flash-program", .file = "src/flash_program.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_gpio-clk", .file = "src/gpio_clk.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_i2c-bus-scan", .file = "src/i2c_bus_scan.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_pwm", .file = "src/pwm.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_random", .file = "src/random.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_spi-master", .file = "src/spi_master.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_squarewave", .file = "src/squarewave.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_uart", .file = "src/uart.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_usb-device", .file = "src/usb_device.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_usb-hid", .file = "src/usb_hid.zig" },
+    .{ .target = "board:raspberry_pi/pico", .name = "pico_ws2812", .file = "src/ws2812.zig" },
+    // TODO: Fix multicore hal! .{ .name = "pico", .target = "board:raspberry_pi/pico" , .file = "src/blinky_core1.zig" },
+
+    // WaveShare Boards:
+    .{ .target = "board:waveshare/rp2040_matrix", .name = "rp2040-matrix_tiles", .file = "src/tiles.zig" },
+    // .{ .target = "board:waveshare/rp2040_eth", .name = "rp2040-eth" },
+    // .{ .target = "board:waveshare/rp2040_plus_4m", .name = "rp2040-plus-4m" },
+    // .{ .target = "board:waveshare/rp2040_plus_16m", .name = "rp2040-plus-16m" },
 };
 
 pub fn build(b: *std.Build) void {
@@ -26,6 +30,9 @@ pub fn build(b: *std.Build) void {
 
     const optimize = b.standardOptimizeOption(.{});
 
+    const show_targets_step = b.step("show-targets", "Shows all available MicroZig targets");
+    show_targets_step.dependOn(microzig.getShowTargetsStep());
+
     for (available_examples) |example| {
         const target = microzig.findTarget(example.target).?;
 
diff --git a/examples/raspberrypi-rp2040/build.zig.zon b/examples/raspberrypi-rp2040/build.zig.zon
deleted file mode 100644
index 36711f611..000000000
--- a/examples/raspberrypi-rp2040/build.zig.zon
+++ /dev/null
@@ -1,18 +0,0 @@
-.{
-    .name = "microzig-raspberrypi-rp2040-examples",
-    .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "http://localhost:8080/microzig-build.tar.gz",
-            .hash = "1220db1de385b765aa45a04719c199d7ab8306fcca6ac1a12b487ed589a69d05a665",
-        },
-        .@"microzig-core" = .{
-            .url = "http://localhost:8080/microzig-core.tar.gz",
-            .hash = "122006d6343021c1502ceba7948fd61ac813f2bb498a74df27a50e34398ccdfb92e3",
-        },
-        .@"microzig-bsp-rp2040" = .{
-            .url = "http://localhost:8080/board-support/raspberrypi/rp2040.tar.gz",
-            .hash = "12200319b02d9d0237984fd7acb15a4945e5547b750e0a3309d13d62440983b5b67f",
-        },
-    },
-}
diff --git a/examples/raspberrypi-rp2040/microzig-package.json b/examples/raspberrypi-rp2040/microzig-package.json
new file mode 100644
index 000000000..e0df92f41
--- /dev/null
+++ b/examples/raspberrypi-rp2040/microzig-package.json
@@ -0,0 +1,7 @@
+{
+    "package_name": "raspberrypi/rp2040",
+    "package_type": "example",
+    "inner_dependencies": [
+        "raspberrypi/rp2040"
+    ]
+}
\ No newline at end of file

From 2e9df6032d58924d4cd8ddf1768fbe6abe7c40a7 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Mon, 5 Feb 2024 10:29:22 +0100
Subject: [PATCH 267/286] Tiny change in the rp2040 build

---
 examples/raspberrypi-rp2040/build.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/examples/raspberrypi-rp2040/build.zig b/examples/raspberrypi-rp2040/build.zig
index 57c701313..a09340503 100644
--- a/examples/raspberrypi-rp2040/build.zig
+++ b/examples/raspberrypi-rp2040/build.zig
@@ -16,7 +16,7 @@ const available_examples = [_]Example{
     .{ .target = "board:raspberry_pi/pico", .name = "pico_usb-device", .file = "src/usb_device.zig" },
     .{ .target = "board:raspberry_pi/pico", .name = "pico_usb-hid", .file = "src/usb_hid.zig" },
     .{ .target = "board:raspberry_pi/pico", .name = "pico_ws2812", .file = "src/ws2812.zig" },
-    // TODO: Fix multicore hal! .{ .name = "pico", .target = "board:raspberry_pi/pico" , .file = "src/blinky_core1.zig" },
+    // TODO: Fix multicore hal! .{ .target = "board:raspberry_pi/pico", .name = "pico_multicore" , .file = "src/blinky_core1.zig" },
 
     // WaveShare Boards:
     .{ .target = "board:waveshare/rp2040_matrix", .name = "rp2040-matrix_tiles", .file = "src/tiles.zig" },

From 7a33e6fd55a711f9fdce30fe83b39e7a9a8e3110 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Mon, 5 Feb 2024 13:15:56 +0100
Subject: [PATCH 268/286] Makes stm32 module build again.

---
 .gitignore                                   |  1 +
 examples/raspberrypi-rp2040/build.zig        |  1 -
 examples/stmicro-stm32/build.zig             | 33 ++++----
 examples/stmicro-stm32/build.zig.zon         | 14 ----
 examples/stmicro-stm32/microzig-package.json |  7 ++
 tools/bundle.py                              | 37 ++-------
 tools/lib/common.py                          | 32 ++++++++
 tools/validate-all-examples.sh               | 11 +++
 tools/validate-example.py                    | 85 ++++++++++++++++++++
 9 files changed, 163 insertions(+), 58 deletions(-)
 delete mode 100644 examples/stmicro-stm32/build.zig.zon
 create mode 100644 examples/stmicro-stm32/microzig-package.json
 create mode 100644 tools/lib/common.py
 create mode 100755 tools/validate-all-examples.sh
 create mode 100755 tools/validate-example.py

diff --git a/.gitignore b/.gitignore
index 1efc3f0f9..066031673 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,3 +5,4 @@ microzig-deploy/
 .gdbinit
 .lldbinit
 .direnv/
+__pycache__/
\ No newline at end of file
diff --git a/examples/raspberrypi-rp2040/build.zig b/examples/raspberrypi-rp2040/build.zig
index a09340503..73fe7a290 100644
--- a/examples/raspberrypi-rp2040/build.zig
+++ b/examples/raspberrypi-rp2040/build.zig
@@ -27,7 +27,6 @@ const available_examples = [_]Example{
 
 pub fn build(b: *std.Build) void {
     const microzig = MicroZig.createBuildEnvironment(b, .{});
-
     const optimize = b.standardOptimizeOption(.{});
 
     const show_targets_step = b.step("show-targets", "Shows all available MicroZig targets");
diff --git a/examples/stmicro-stm32/build.zig b/examples/stmicro-stm32/build.zig
index 471a7276d..653f83407 100644
--- a/examples/stmicro-stm32/build.zig
+++ b/examples/stmicro-stm32/build.zig
@@ -1,22 +1,27 @@
 const std = @import("std");
-const stm32 = @import("stm32");
+const MicroZig = @import("microzig-build");
 
 const available_examples = [_]Example{
-    .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8, .file = "src/blinky.zig" },
-    // TODO: .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc, .file = "src/blinky.zig" },
-    // TODO: .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg, .file = "src/blinky.zig" },
-    // TODO: .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u, .file = "src/blinky.zig" },
-    // TODO: .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery, .file = "src/blinky.zig" },
-    // TODO: .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery, .file = "src/blinky.zig" },
-    // TODO: .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval, .file = "src/blinky.zig" },
-    // TODO: .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery, .file = "src/blinky.zig" },
+    .{ .target = "chip:stm32f103x8",.name = "stm32f103x8",  .file = "src/blinky.zig" },
+    // TODO: .{ .target = "chip:stm32f303vc", .name = "stm32f303vc",  .file = "src/blinky.zig" },
+    // TODO: .{ .target = "chip:stm32f407vg", .name = "stm32f407vg",  .file = "src/blinky.zig" },
+    // TODO: .{ .target = "chip:stm32f429zit6u", .name = "stm32f429zit6u",  .file = "src/blinky.zig" },
+    // TODO: .{ .target = "board:stm32f3discovery", .name = "stm32f3discovery",  .file = "src/blinky.zig" },
+    // TODO: .{ .target = "board:stm32f4discovery", .name = "stm32f4discovery",  .file = "src/blinky.zig" },
+    // TODO: .{ .target = "board:stm3240geval", .name = "stm3240geval",  .file = "src/blinky.zig" },
+    // TODO: .{ .target = "board:stm32f429idiscovery", .name = "stm32f429idiscovery",  .file = "src/blinky.zig" },
 };
 
 pub fn build(b: *std.Build) void {
-    const microzig = @import("microzig").init(b, "microzig");
-    const optimize = .ReleaseSmall; // The others are not really an option on AVR
+    const microzig = MicroZig.createBuildEnvironment(b, .{});
+    const optimize = b.standardOptimizeOption(.{});
+
+    const show_targets_step = b.step("show-targets", "Shows all available MicroZig targets");
+    show_targets_step.dependOn(microzig.getShowTargetsStep());
 
     for (available_examples) |example| {
+        const target = microzig.findTarget(example.target).?;
+
         // `addFirmware` basically works like addExecutable, but takes a
         // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
         //
@@ -24,7 +29,7 @@ pub fn build(b: *std.Build) void {
         // cpu and potentially the board as well.
         const firmware = microzig.addFirmware(b, .{
             .name = example.name,
-            .target = example.target,
+            .target = target,
             .optimize = optimize,
             .source_file = .{ .path = example.file },
         });
@@ -41,7 +46,7 @@ pub fn build(b: *std.Build) void {
 }
 
 const Example = struct {
-    target: @import("microzig").Target,
+    target: []const u8,
     name: []const u8,
     file: []const u8,
-};
+};
\ No newline at end of file
diff --git a/examples/stmicro-stm32/build.zig.zon b/examples/stmicro-stm32/build.zig.zon
deleted file mode 100644
index b6063eabc..000000000
--- a/examples/stmicro-stm32/build.zig.zon
+++ /dev/null
@@ -1,14 +0,0 @@
-.{
-    .name = "microzig-stmicro-stm32-examples",
-    .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
-            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
-        },
-        .stm32 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/stmicro-stm32/archive/237890d49ee795110a63df2c45bdd6f6a0029a72.tar.gz",
-            .hash = "1220960897777f9713fa1055ffdf1fbad1518b2f62bd2f2ae39b887821dbf0781df0",
-        },
-    },
-}
diff --git a/examples/stmicro-stm32/microzig-package.json b/examples/stmicro-stm32/microzig-package.json
new file mode 100644
index 000000000..674b76e6d
--- /dev/null
+++ b/examples/stmicro-stm32/microzig-package.json
@@ -0,0 +1,7 @@
+{
+    "package_name": "stmicro/stm32",
+    "package_type": "example",
+    "inner_dependencies": [
+        "stmicro/stm32"
+    ]
+}
\ No newline at end of file
diff --git a/tools/bundle.py b/tools/bundle.py
index 4878ccbb7..4e0e2155e 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -7,7 +7,7 @@
 #
 
 
-import sys, os, subprocess,datetime, re, shutil, json, hashlib
+import sys, os, datetime, re, shutil, json, hashlib
 from pathlib import Path, PurePosixPath
 from dataclasses import dataclass, field 
 from dataclasses_json import dataclass_json, config as  dcj_config, Exclude as JsonExclude
@@ -18,9 +18,14 @@
 import stat 
 import tarfile
 
+
+
 from marshmallow import fields as mm_fields
 from typing import Optional, Any
 
+from lib.common import  execute_raw, execute, slurp, check_zig_version, check_required_tools
+import lib.common as common
+
 LEGAL_PACKAGE_NAME = re.compile("^[A-Za-z]$")
 
 VERBOSE = False 
@@ -36,7 +41,7 @@
 assert REPO_ROOT.is_dir()
 
 
-
+common.VERBOSE = VERBOSE
 
 class PackageType(StrEnum):
     build = "build"
@@ -138,34 +143,8 @@ def file_digest(path: Path, hashfunc) -> bytes:
 def file_type(path: Path) -> str:
     return FILE_STAT_MAP[stat.S_IFMT( path.stat().st_mode)]
 
-def execute_raw(*args,hide_stderr = False,**kwargs):
-    args = [ str(f) for f in args]
-    if VERBOSE:
-        print(*args)
-    res = subprocess.run(args, **kwargs, check=False)
-    if res.stderr is not None and (not hide_stderr or res.returncode != 0):
-        sys.stderr.buffer.write(res.stderr)
-    if res.returncode != 0:
-        sys.stderr.write(f"command {' '.join(args)} failed with exit code {res.returncode}")
-        sys.exit(res.returncode)
-    return res 
-
-def execute(*args,**kwargs):
-    execute_raw(*args, **kwargs, capture_output=False)
-
-def slurp(*args, **kwargs):
-    res = execute_raw(*args, **kwargs, capture_output=True)
-    return res.stdout
-
-def check_required_tools():
-    for tool in REQUIRED_TOOLS:
-        slurp("which", tool)
 
 
-def check_zig_version(expected):
-    actual = slurp("zig", "version")
-    if actual.strip() != expected.encode():
-        raise RuntimeError(f"Unexpected zig version! Expected {expected}, but found {actual.strip()}!")
 
 def build_zig_tools():    
     # ensure we have our tools available:
@@ -251,7 +230,7 @@ def get_batch_timestamp():
 
 def main():
 
-    check_required_tools()
+    check_required_tools(REQUIRED_TOOLS)
 
     check_zig_version("0.11.0")
 
diff --git a/tools/lib/common.py b/tools/lib/common.py
new file mode 100644
index 000000000..4d72ca906
--- /dev/null
+++ b/tools/lib/common.py
@@ -0,0 +1,32 @@
+
+import subprocess, sys
+
+VERBOSE = False
+
+def execute_raw(*args,hide_stderr = False,**kwargs):
+    args = [ str(f) for f in args]
+    if VERBOSE:
+        print(*args)
+    res = subprocess.run(args, **kwargs, check=False)
+    if res.stderr is not None and (not hide_stderr or res.returncode != 0):
+        sys.stderr.buffer.write(res.stderr)
+    if res.returncode != 0:
+        sys.stderr.write(f"command {' '.join(args)} failed with exit code {res.returncode}")
+        sys.exit(res.returncode)
+    return res 
+
+def execute(*args,**kwargs):
+    execute_raw(*args, **kwargs, capture_output=False)
+
+def slurp(*args, **kwargs):
+    res = execute_raw(*args, **kwargs, capture_output=True)
+    return res.stdout
+
+def check_zig_version(expected):
+    actual = slurp("zig", "version")
+    if actual.strip() != expected.encode():
+        raise RuntimeError(f"Unexpected zig version! Expected {expected}, but found {actual.strip()}!")
+
+def check_required_tools(tools):
+    for tool in tools:
+        slurp("which", tool)
\ No newline at end of file
diff --git a/tools/validate-all-examples.sh b/tools/validate-all-examples.sh
new file mode 100755
index 000000000..494efb87c
--- /dev/null
+++ b/tools/validate-all-examples.sh
@@ -0,0 +1,11 @@
+#!/bin/sh
+
+set -e 
+
+root="$(dirname "$(realpath "$0")")"
+tmpdir="/tmp/microzig-test"
+
+mkdir -p "${tmpdir}"
+
+"${root}/validate-example.py" --build-root "${tmpdir}" --example raspberrypi/rp2040
+"${root}/validate-example.py" --build-root "${tmpdir}" --example stmicro/stm32
diff --git a/tools/validate-example.py b/tools/validate-example.py
new file mode 100755
index 000000000..12dac7bd8
--- /dev/null
+++ b/tools/validate-example.py
@@ -0,0 +1,85 @@
+#!/usr/bin/env python3
+
+
+from lib.common import execute_raw, execute, slurp, check_zig_version, check_required_tools
+from pathlib import Path, PurePosixPath
+import argparse
+import sys 
+import shutil
+
+REQUIRED_TOOLS = ["zig", "curl", "tar", "gunzip"]
+
+
+def main():
+
+    check_required_tools(REQUIRED_TOOLS)
+
+    check_zig_version("0.11.0")
+
+    parser = argparse.ArgumentParser()
+
+    parser.add_argument("--example", type=PurePosixPath, required=True)
+    parser.add_argument("--build-root", type=Path, required=True)
+    args = parser.parse_args()
+
+    example_id: PurePosixPath = args.example 
+    build_root: Path = args.build_root
+
+    if len(example_id.parents) != 2 or str(example_id.parents[1]) != ".":
+        print(f"example must be /", file=sys.stderr)
+        exit(1)
+
+
+    example_group: str = example_id.parent.name
+    example_name: str = example_id.name
+
+    if not build_root.is_dir():
+        print(f"{build_root} is not a directory", file=sys.stderr)
+        exit(1)
+
+    execute(
+        "curl",
+        "-o",
+        f"{example_name}.tar.gz",
+        f"https://public.devspace.random-projects.net/examples/{example_group}/{example_name}.tar.gz",
+        cwd=build_root,
+    )
+
+    any_path = slurp(
+        "tar",
+        "-tf",
+        f"{example_name}.tar.gz",
+        cwd=build_root,
+    ).splitlines()[0].decode()
+
+    root_folder_name = any_path.split(sep='/')[0]
+
+    example_build_root = build_root / root_folder_name
+
+    if example_build_root.exists():
+        shutil.rmtree(example_build_root)
+
+    execute(
+        "tar",
+        "-xf",
+        f"{example_name}.tar.gz",
+        cwd=build_root,
+    )
+
+    # print(list(example_build_root.glob("*")))
+
+    execute(
+        "zig",
+        "build",
+        cwd = example_build_root,
+    )
+
+    out_dir = example_build_root / "zig-out"
+
+    print("all files:")
+    for path in out_dir.rglob("*"):
+        if path.is_file():
+            print(f"- {path}")
+
+if __name__ == "__main__":
+    main()

From 71e60e3c4435220fcfdb3248d7c5e86b9b098b71 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Mon, 5 Feb 2024 18:02:22 +0100
Subject: [PATCH 269/286] Makes nxp/lpc and nordic/nrf5x examples, fixes bug in
 build.zig.zon generation

---
 .../nordic-nrf5x/microzig-package.json        |  6 ++--
 examples/nordic-nrf5x/build.zig               | 15 ++++++---
 examples/nordic-nrf5x/build.zig.zon           | 14 --------
 examples/nordic-nrf5x/microzig-package.json   |  7 ++++
 examples/nxp-lpc/build.zig                    | 15 ++++++---
 examples/nxp-lpc/build.zig.zon                | 14 --------
 examples/nxp-lpc/microzig-package.json        |  7 ++++
 tools/create-pkg-descriptor.zig               | 32 +++++++++++++++----
 tools/validate-all-examples.sh                |  1 +
 tools/validate-example.py                     |  2 --
 10 files changed, 64 insertions(+), 49 deletions(-)
 delete mode 100644 examples/nordic-nrf5x/build.zig.zon
 create mode 100644 examples/nordic-nrf5x/microzig-package.json
 delete mode 100644 examples/nxp-lpc/build.zig.zon
 create mode 100644 examples/nxp-lpc/microzig-package.json

diff --git a/board-support/nordic-nrf5x/microzig-package.json b/board-support/nordic-nrf5x/microzig-package.json
index 7be87c111..5697daad1 100644
--- a/board-support/nordic-nrf5x/microzig-package.json
+++ b/board-support/nordic-nrf5x/microzig-package.json
@@ -1,4 +1,4 @@
 {
-  "package_name": "nordic/nrf52",
-  "package_type": "board-support"
-}
+    "package_name": "nordic/nrf5x",
+    "package_type": "board-support"
+}
\ No newline at end of file
diff --git a/examples/nordic-nrf5x/build.zig b/examples/nordic-nrf5x/build.zig
index 85a2b6f17..8b200d194 100644
--- a/examples/nordic-nrf5x/build.zig
+++ b/examples/nordic-nrf5x/build.zig
@@ -1,15 +1,20 @@
 const std = @import("std");
-const nrf5x = @import("nrf5x");
+const MicroZig = @import("microzig-build");
 
 const available_examples = [_]Example{
-    .{ .name = "nrf52480-dongle_blinky", .target = nrf5x.boards.nordic.nRF52840_Dongle, .file = "src/blinky.zig" },
+    .{ .target = "board:nordic/nRF52840_Dongle", .name = "nrf52480-dongle_blinky", .file = "src/blinky.zig" },
 };
 
 pub fn build(b: *std.Build) void {
-    const microzig = @import("microzig").init(b, "microzig");
+    const microzig = MicroZig.createBuildEnvironment(b, .{});
     const optimize = b.standardOptimizeOption(.{});
 
+    const show_targets_step = b.step("show-targets", "Shows all available MicroZig targets");
+    show_targets_step.dependOn(microzig.getShowTargetsStep());
+
     for (available_examples) |example| {
+        const target = microzig.findTarget(example.target).?;
+
         // `addFirmware` basically works like addExecutable, but takes a
         // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
         //
@@ -17,7 +22,7 @@ pub fn build(b: *std.Build) void {
         // cpu and potentially the board as well.
         const firmware = microzig.addFirmware(b, .{
             .name = example.name,
-            .target = example.target,
+            .target = target,
             .optimize = optimize,
             .source_file = .{ .path = example.file },
         });
@@ -34,7 +39,7 @@ pub fn build(b: *std.Build) void {
 }
 
 const Example = struct {
-    target: @import("microzig").Target,
+    target: []const u8,
     name: []const u8,
     file: []const u8,
 };
diff --git a/examples/nordic-nrf5x/build.zig.zon b/examples/nordic-nrf5x/build.zig.zon
deleted file mode 100644
index 2034409a0..000000000
--- a/examples/nordic-nrf5x/build.zig.zon
+++ /dev/null
@@ -1,14 +0,0 @@
-.{
-    .name = "microzig-nordic-nrf5x-examples",
-    .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
-            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
-        },
-        .nrf5x = .{
-            .url = "https://github.com/ZigEmbeddedGroup/nordic-nrf5x/archive/0ab136860ccf7eb1d07969c3ef523f3cd898e2ff.tar.gz",
-            .hash = "1220980da06f9634dcff06afefa7aa111bd030018fea49f79e86657dab69621e1d08",
-        },
-    },
-}
diff --git a/examples/nordic-nrf5x/microzig-package.json b/examples/nordic-nrf5x/microzig-package.json
new file mode 100644
index 000000000..a3c636ec7
--- /dev/null
+++ b/examples/nordic-nrf5x/microzig-package.json
@@ -0,0 +1,7 @@
+{
+    "package_name": "nordic/nrf5x",
+    "package_type": "example",
+    "inner_dependencies": [
+        "nordic/nrf5x"
+    ]
+}
\ No newline at end of file
diff --git a/examples/nxp-lpc/build.zig b/examples/nxp-lpc/build.zig
index a6f0b305f..b43360d96 100644
--- a/examples/nxp-lpc/build.zig
+++ b/examples/nxp-lpc/build.zig
@@ -1,15 +1,20 @@
 const std = @import("std");
-const lpc = @import("lpc");
+const MicroZig = @import("microzig-build");
 
 const available_examples = [_]ExampleDesc{
-    .{ .name = "mbed-lpc1768_blinky", .target = lpc.boards.mbed.lpc1768, .file = "src/blinky.zig" },
+    .{ .target = "board:mbed/lpc1768", .name = "mbed-lpc1768_blinky", .file = "src/blinky.zig" },
 };
 
 pub fn build(b: *std.Build) void {
-    const microzig = @import("microzig").init(b, "microzig");
+    const microzig = MicroZig.createBuildEnvironment(b, .{});
     const optimize = b.standardOptimizeOption(.{});
 
+    const show_targets_step = b.step("show-targets", "Shows all available MicroZig targets");
+    show_targets_step.dependOn(microzig.getShowTargetsStep());
+
     for (available_examples) |example| {
+        const target = microzig.findTarget(example.target).?;
+
         // `addFirmware` basically works like addExecutable, but takes a
         // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
         //
@@ -17,7 +22,7 @@ pub fn build(b: *std.Build) void {
         // cpu and potentially the board as well.
         const firmware = microzig.addFirmware(b, .{
             .name = example.name,
-            .target = example.target,
+            .target = target,
             .optimize = optimize,
             .source_file = .{ .path = example.file },
         });
@@ -34,7 +39,7 @@ pub fn build(b: *std.Build) void {
 }
 
 const ExampleDesc = struct {
-    target: @import("microzig").Target,
+    target: []const u8,
     name: []const u8,
     file: []const u8,
 };
diff --git a/examples/nxp-lpc/build.zig.zon b/examples/nxp-lpc/build.zig.zon
deleted file mode 100644
index aa5a11a05..000000000
--- a/examples/nxp-lpc/build.zig.zon
+++ /dev/null
@@ -1,14 +0,0 @@
-.{
-    .name = "microzig-nxp-lpc-examples",
-    .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
-            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
-        },
-        .lpc = .{
-            .url = "https://github.com/ZigEmbeddedGroup/nxp-lpc/archive/130a1316c0892415e7da958a5e9548ed87bba54d.tar.gz",
-            .hash = "1220165879f85a1d51656d35b3963a95f3585dc665fc7414f76aa6aad4e6635536cf",
-        },
-    },
-}
diff --git a/examples/nxp-lpc/microzig-package.json b/examples/nxp-lpc/microzig-package.json
new file mode 100644
index 000000000..32638dd0f
--- /dev/null
+++ b/examples/nxp-lpc/microzig-package.json
@@ -0,0 +1,7 @@
+{
+    "package_name": "nxp/lpc",
+    "package_type": "example",
+    "inner_dependencies": [
+        "nxp/lpc"
+    ]
+}
\ No newline at end of file
diff --git a/tools/create-pkg-descriptor.zig b/tools/create-pkg-descriptor.zig
index 13dd89957..8b0625312 100644
--- a/tools/create-pkg-descriptor.zig
+++ b/tools/create-pkg-descriptor.zig
@@ -34,18 +34,21 @@ const Timestamp = struct {
 };
 
 const MetaData = struct {
-    const Type = enum {
-        @"board-support",
-        core,
-        build,
-        example,
+    const Type = enum(u32) {
+        // we "abuse" the enum value here to map our keys to a priority mapping:
+        // Zig 0.11 must have dependencies with inner dependencies in the right order,
+        // otherwise the build system won't find the dependencies:
+        build = 0, // must always be first
+        core = 300,
+        @"board-support" = 500,
+        example = 900,
     };
 
     package_name: []const u8,
     package_type: Type,
     version: []const u8,
 
-    inner_dependencies: []const []const u8 = &.{},
+    inner_dependencies: [][]const u8 = &.{},
     external_dependencies: std.json.Value = .null,
 
     archive: ?Archive = null,
@@ -122,6 +125,8 @@ pub fn main() !void {
             }
         }
 
+        std.sort.block([]const u8, package.inner_dependencies, all_packages, orderPackagesByPriority);
+
         // Add all other dependencies:
         for (package.inner_dependencies) |dep_name| {
             const dep = findPackage(all_packages, dep_name).?;
@@ -140,3 +145,18 @@ pub fn main() !void {
 
     try buffered_stdout.flush();
 }
+
+fn orderPackagesByPriority(mt: []MetaData, lhs_name: []const u8, rhs_name: []const u8) bool {
+    const rhs = findPackage(mt, rhs_name).?;
+    const lhs = findPackage(mt, lhs_name).?;
+
+    const rhs_prio = @intFromEnum(rhs.package_type);
+    const lhs_prio = @intFromEnum(lhs.package_type);
+
+    if (lhs_prio < rhs_prio)
+        return true;
+    if (lhs_prio > rhs_prio)
+        return false;
+
+    return std.ascii.lessThanIgnoreCase(lhs_name, rhs_name);
+}
diff --git a/tools/validate-all-examples.sh b/tools/validate-all-examples.sh
index 494efb87c..bf50cde70 100755
--- a/tools/validate-all-examples.sh
+++ b/tools/validate-all-examples.sh
@@ -9,3 +9,4 @@ mkdir -p "${tmpdir}"
 
 "${root}/validate-example.py" --build-root "${tmpdir}" --example raspberrypi/rp2040
 "${root}/validate-example.py" --build-root "${tmpdir}" --example stmicro/stm32
+"${root}/validate-example.py" --build-root "${tmpdir}" --example nxp/lpc
diff --git a/tools/validate-example.py b/tools/validate-example.py
index 12dac7bd8..d04c8afd0 100755
--- a/tools/validate-example.py
+++ b/tools/validate-example.py
@@ -66,8 +66,6 @@ def main():
         cwd=build_root,
     )
 
-    # print(list(example_build_root.glob("*")))
-
     execute(
         "zig",
         "build",

From 2ef68047de25e308ccd43264a81113ed6839e3a8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Tue, 6 Feb 2024 09:20:43 +0100
Subject: [PATCH 270/286] Adds up navigation in dev server

---
 tools/demo-server.py | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/tools/demo-server.py b/tools/demo-server.py
index 68545df8d..6ef5a8755 100755
--- a/tools/demo-server.py
+++ b/tools/demo-server.py
@@ -59,12 +59,18 @@ def list_directory(self, path):
         r.append('%s\n' % title)
         r.append('\n
    %s
    ' % title)
         r.append('
    \n
      ')
+
+        suffix = path.removeprefix(self.directory)
+        
+        if suffix != "/":
+            r.append('
    • ..
      • ')
+
         for name in list:
             fullname = os.path.join(path, name)
             displayname = linkname = name
             if name.startswith("."):
                 # ignore "hidden" directories
-                continue 
+                continue
             # Append / for directories or @ for symbolic links
             if os.path.isdir(fullname):
                 displayname = name + "/"

From 7dd20383fb389d2daa9d1c7b49cdc3f68f0cd38a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Tue, 6 Feb 2024 11:16:37 +0100
Subject: [PATCH 271/286] Adds examples for espressif/esp, gigadevice/gd32

---
 .gitignore                                    |  2 +-
 examples/espressif-esp/build.zig              | 66 +++++++++----------
 examples/espressif-esp/build.zig.zon          | 18 -----
 examples/espressif-esp/microzig-package.json  |  7 ++
 examples/gigadevice-gd32/build.zig            | 21 +++---
 examples/gigadevice-gd32/build.zig.zon        | 14 ----
 .../gigadevice-gd32/microzig-package.json     |  7 ++
 examples/gigadevice-gd32/src/empty.zig        |  6 ++
 8 files changed, 67 insertions(+), 74 deletions(-)
 delete mode 100644 examples/espressif-esp/build.zig.zon
 create mode 100644 examples/espressif-esp/microzig-package.json
 delete mode 100644 examples/gigadevice-gd32/build.zig.zon
 create mode 100644 examples/gigadevice-gd32/microzig-package.json
 create mode 100644 examples/gigadevice-gd32/src/empty.zig

diff --git a/.gitignore b/.gitignore
index 066031673..3f1d472a5 100644
--- a/.gitignore
+++ b/.gitignore
@@ -5,4 +5,4 @@ microzig-deploy/
 .gdbinit
 .lldbinit
 .direnv/
-__pycache__/
\ No newline at end of file
+__pycache__/
diff --git a/examples/espressif-esp/build.zig b/examples/espressif-esp/build.zig
index 08dcceeb0..8e2b58401 100644
--- a/examples/espressif-esp/build.zig
+++ b/examples/espressif-esp/build.zig
@@ -1,45 +1,45 @@
 const std = @import("std");
-const esp = @import("esp");
+const MicroZig = @import("microzig-build");
 
-const available_targets = [_]TargetDesc{
-    .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 },
-};
-
-const available_examples = [_][]const u8{
-    "src/blinky.zig",
+const available_examples = [_]Example{
+    .{ .target = "chip:esp32_c3", .name = "esp32-c3_blinky", .file = "src/blinky.zig" },
 };
 
 pub fn build(b: *std.Build) void {
-    const microzig = @import("microzig").init(b, "microzig");
+    const microzig = MicroZig.createBuildEnvironment(b, .{});
     const optimize = b.standardOptimizeOption(.{});
 
-    for (available_targets) |target| {
-        for (available_examples) |example| {
-            // `addFirmware` basically works like addExecutable, but takes a
-            // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
-            //
-            // The target will convey all necessary information on the chip,
-            // cpu and potentially the board as well.
-            const firmware = microzig.addFirmware(b, .{
-                .name = b.fmt("{s}-{s}", .{ std.fs.path.stem(example), target.name }),
-                .target = target.target,
-                .optimize = optimize,
-                .source_file = .{ .path = example },
-            });
-
-            // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
-            // and allows installing the firmware as a typical firmware file.
-            //
-            // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
-            microzig.installFirmware(b, firmware, .{});
-
-            // For debugging, we also always install the firmware as an ELF file
-            microzig.installFirmware(b, firmware, .{ .format = .elf });
-        }
+    const show_targets_step = b.step("show-targets", "Shows all available MicroZig targets");
+    show_targets_step.dependOn(microzig.getShowTargetsStep());
+
+    for (available_examples) |example| {
+        const target = microzig.findTarget(example.target).?;
+
+        // `addFirmware` basically works like addExecutable, but takes a
+        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+        //
+        // The target will convey all necessary information on the chip,
+        // cpu and potentially the board as well.
+        const firmware = microzig.addFirmware(b, .{
+            .name = example.name,
+            .target = target,
+            .optimize = optimize,
+            .source_file = .{ .path = example.file },
+        });
+
+        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+        // and allows installing the firmware as a typical firmware file.
+        //
+        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+        microzig.installFirmware(b, firmware, .{});
+
+        // For debugging, we also always install the firmware as an ELF file
+        microzig.installFirmware(b, firmware, .{ .format = .elf });
     }
 }
 
-const TargetDesc = struct {
-    target: @import("microzig").Target,
+const Example = struct {
+    target: []const u8,
     name: []const u8,
+    file: []const u8,
 };
diff --git a/examples/espressif-esp/build.zig.zon b/examples/espressif-esp/build.zig.zon
deleted file mode 100644
index 5fc8d3025..000000000
--- a/examples/espressif-esp/build.zig.zon
+++ /dev/null
@@ -1,18 +0,0 @@
-.{
-    .name = "microzig-nxp-lpc-examples",
-    .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://public.devspace.random-projects.net/packages/microzig-build.tar.gz",
-            .hash = "1220db1de385b765aa45a04719c199d7ab8306fcca6ac1a12b487ed589a69d05a665",
-        },
-        .@"microzig-core" = .{
-            .url = "https://public.devspace.random-projects.net/packages/microzig-core.tar.gz",
-            .hash = "1220f72de650278d4184dd4a43992189246b520a5c137b54fca05d7a44df8b828267",
-        },
-        .@"microzig-bsp-rp2040" = .{
-            .url = "https://public.devspace.random-projects.net/packages/board-support/raspberrypi/rp2040.tar.gz",
-            .hash = "1220b170e56d2bd85b96bd8b7f40f2890cf9926da2fcb86967e466a3c87486f31c43",
-        },
-    },
-}
diff --git a/examples/espressif-esp/microzig-package.json b/examples/espressif-esp/microzig-package.json
new file mode 100644
index 000000000..162a6c7fb
--- /dev/null
+++ b/examples/espressif-esp/microzig-package.json
@@ -0,0 +1,7 @@
+{
+    "package_name": "espressif/esp",
+    "package_type": "example",
+    "inner_dependencies": [
+        "espressif/esp"
+    ]
+}
\ No newline at end of file
diff --git a/examples/gigadevice-gd32/build.zig b/examples/gigadevice-gd32/build.zig
index b7a2e4cf7..7783f3f0e 100644
--- a/examples/gigadevice-gd32/build.zig
+++ b/examples/gigadevice-gd32/build.zig
@@ -1,17 +1,22 @@
 const std = @import("std");
-const gd32 = @import("gd32");
+const MicroZig = @import("microzig-build");
 
 const available_examples = [_]Example{
-    // .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb, .file = "src/blinky.zig" },
-    // .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8, .file = "src/blinky.zig" },
-    // .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano, .file = "src/blinky.zig" },
+    .{ .target = "chip:gd32vf103xb", .name = "gd32vf103xb", .file = "src/empty.zig" },
+    .{ .target = "chip:gd32vf103x8", .name = "gd32vf103x8", .file = "src/empty.zig" },
+    .{ .target = "board:sipeed/longan_nano", .name = "sipeed-longan_nano", .file = "src/empty.zig" },
 };
 
 pub fn build(b: *std.Build) void {
-    const microzig = @import("microzig").init(b, "microzig");
-    const optimize = .ReleaseSmall; // The others are not really an option on AVR
+    const microzig = MicroZig.createBuildEnvironment(b, .{});
+    const optimize = b.standardOptimizeOption(.{});
+
+    const show_targets_step = b.step("show-targets", "Shows all available MicroZig targets");
+    show_targets_step.dependOn(microzig.getShowTargetsStep());
 
     for (available_examples) |example| {
+        const target = microzig.findTarget(example.target).?;
+
         // `addFirmware` basically works like addExecutable, but takes a
         // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
         //
@@ -19,7 +24,7 @@ pub fn build(b: *std.Build) void {
         // cpu and potentially the board as well.
         const firmware = microzig.addFirmware(b, .{
             .name = example.name,
-            .target = example.target,
+            .target = target,
             .optimize = optimize,
             .source_file = .{ .path = example.file },
         });
@@ -36,7 +41,7 @@ pub fn build(b: *std.Build) void {
 }
 
 const Example = struct {
-    target: @import("microzig").Target,
+    target: []const u8,
     name: []const u8,
     file: []const u8,
 };
diff --git a/examples/gigadevice-gd32/build.zig.zon b/examples/gigadevice-gd32/build.zig.zon
deleted file mode 100644
index 2cfeaae93..000000000
--- a/examples/gigadevice-gd32/build.zig.zon
+++ /dev/null
@@ -1,14 +0,0 @@
-.{
-    .name = "microzig-gigadevice-gd32-examples",
-    .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
-            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
-        },
-        .gd32 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/gigadevice-gd32/archive/9324753cc3b8e7afe83fcda085bcfe76681a3be3.tar.gz",
-            .hash = "122043ff4dcbc342f25dbb936b0d9eaa701ac3509e2cbe6764be37b90d31c7a385d0",
-        },
-    },
-}
diff --git a/examples/gigadevice-gd32/microzig-package.json b/examples/gigadevice-gd32/microzig-package.json
new file mode 100644
index 000000000..a4815bb59
--- /dev/null
+++ b/examples/gigadevice-gd32/microzig-package.json
@@ -0,0 +1,7 @@
+{
+    "package_name": "gigadevice/gd32",
+    "package_type": "example",
+    "inner_dependencies": [
+        "gigadevice/gd32"
+    ]
+}
\ No newline at end of file
diff --git a/examples/gigadevice-gd32/src/empty.zig b/examples/gigadevice-gd32/src/empty.zig
new file mode 100644
index 000000000..7c6dbbe42
--- /dev/null
+++ b/examples/gigadevice-gd32/src/empty.zig
@@ -0,0 +1,6 @@
+const std = @import("std");
+const microzig = @import("microzig");
+
+pub fn main() void {
+    //
+}

From 2878ae6e194a591465c42b6d457b884b6ce9d551 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Wed, 7 Feb 2024 10:23:04 +0100
Subject: [PATCH 272/286] Makes microchip/atsam example and bsp work

---
 .../{ => src}/chips/ATSAMD51J19A.atdf         |  0
 examples/all-platforms/build.zig              | 84 -------------------
 examples/all-platforms/build.zig.zon          | 38 ---------
 examples/all-platforms/src/blinky.zig         | 20 -----
 examples/all-platforms/src/empty.zig          |  6 --
 examples/build.zig                            | 28 -------
 examples/microchip-atsam/build.zig            | 45 ++++++++++
 .../microchip-atsam/microzig-package.json     |  7 ++
 .../src/blinky.zig}                           |  4 +-
 examples/next-gen/build.zig                   | 23 -----
 examples/next-gen/build.zig.zon               | 22 -----
 tools/validate-all-examples.sh                |  8 +-
 12 files changed, 58 insertions(+), 227 deletions(-)
 rename board-support/microchip-atsam/{ => src}/chips/ATSAMD51J19A.atdf (100%)
 delete mode 100644 examples/all-platforms/build.zig
 delete mode 100644 examples/all-platforms/build.zig.zon
 delete mode 100644 examples/all-platforms/src/blinky.zig
 delete mode 100644 examples/all-platforms/src/empty.zig
 delete mode 100644 examples/build.zig
 create mode 100644 examples/microchip-atsam/build.zig
 create mode 100644 examples/microchip-atsam/microzig-package.json
 rename examples/{next-gen/src/empty.zig => microchip-atsam/src/blinky.zig} (58%)
 delete mode 100644 examples/next-gen/build.zig
 delete mode 100644 examples/next-gen/build.zig.zon

diff --git a/board-support/microchip-atsam/chips/ATSAMD51J19A.atdf b/board-support/microchip-atsam/src/chips/ATSAMD51J19A.atdf
similarity index 100%
rename from board-support/microchip-atsam/chips/ATSAMD51J19A.atdf
rename to board-support/microchip-atsam/src/chips/ATSAMD51J19A.atdf
diff --git a/examples/all-platforms/build.zig b/examples/all-platforms/build.zig
deleted file mode 100644
index 6cf3b48ad..000000000
--- a/examples/all-platforms/build.zig
+++ /dev/null
@@ -1,84 +0,0 @@
-const std = @import("std");
-const rp2040 = @import("rp2040");
-const stm32 = @import("stm32");
-const lpc = @import("lpc");
-const gd32 = @import("gd32");
-const nrf5x = @import("nrf5x");
-const esp = @import("esp");
-const atmega = @import("atmega");
-
-const available_targets = [_]TargetDesc{
-    // RP2040
-    .{ .name = "pico", .target = rp2040.boards.raspberry_pi.pico },
-    .{ .name = "rp2040-eth", .target = rp2040.boards.waveshare.rp2040_eth },
-    .{ .name = "rp2040-plus-4m", .target = rp2040.boards.waveshare.rp2040_plus_4m },
-    .{ .name = "rp2040-plus-16m", .target = rp2040.boards.waveshare.rp2040_plus_16m },
-    .{ .name = "rp2040-matrix", .target = rp2040.boards.waveshare.rp2040_matrix },
-
-    // STM32
-    .{ .name = "stm32f103x8", .target = stm32.chips.stm32f103x8 },
-    .{ .name = "stm32f303vc", .target = stm32.chips.stm32f303vc },
-    .{ .name = "stm32f407vg", .target = stm32.chips.stm32f407vg },
-    .{ .name = "stm32f429zit6u", .target = stm32.chips.stm32f429zit6u },
-    .{ .name = "stm32f3discovery", .target = stm32.boards.stm32f3discovery },
-    .{ .name = "stm32f4discovery", .target = stm32.boards.stm32f4discovery },
-    .{ .name = "stm3240geval", .target = stm32.boards.stm3240geval },
-    .{ .name = "stm32f429idiscovery", .target = stm32.boards.stm32f429idiscovery },
-
-    // NXP LPC
-    .{ .name = "lpc176x5x", .target = lpc.chips.lpc176x5x },
-    .{ .name = "mbed-lpc1768", .target = lpc.boards.mbed.lpc1768 },
-
-    // GigaDevice GD32
-    .{ .name = "gd32vf103xb", .target = gd32.chips.gd32vf103xb },
-    .{ .name = "gd32vf103x8", .target = gd32.chips.gd32vf103x8 },
-    .{ .name = "sipeed-longan_nano", .target = gd32.boards.sipeed.longan_nano },
-
-    // Nordic Nrf5x
-    .{ .name = "nrf52832", .target = nrf5x.chips.nrf52832 },
-    .{ .name = "nrf52840", .target = nrf5x.chips.nrf52840 },
-    .{ .name = "nrf52840-dongle", .target = nrf5x.boards.nordic.nRF52840_Dongle }, // TODO: Add support for DFU files!
-
-    // RISC-V Espressif ESP
-    .{ .name = "esp32-c3", .target = esp.chips.esp32_c3 }, // TODO: Add support for Espressif Update Binaries
-
-    // Microchip ATmega
-    // TODO: Fix compiler bugs
-    // - https://github.com/ziglang/zig/issues/17219
-    // .{ .name = "atmega328p", .target = atmega.chips.atmega328p },
-    // .{ .name = "arduino-nano", .target = atmega.boards.arduino.nano },
-    // .{ .name = "arduino-uno-rev3", .target = atmega.boards.arduino.uno_rev3 },
-};
-
-pub fn build(b: *std.Build) void {
-    const microzig = @import("microzig").init(b, "microzig");
-    const optimize = b.standardOptimizeOption(.{});
-
-    for (available_targets) |dest| {
-        // `addFirmware` basically works like addExecutable, but takes a
-        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
-        //
-        // The target will convey all necessary information on the chip,
-        // cpu and potentially the board as well.
-        const firmware = microzig.addFirmware(b, .{
-            .name = b.fmt("empty-{s}", .{dest.name}),
-            .target = dest.target,
-            .optimize = optimize,
-            .source_file = .{ .path = "src/empty.zig" },
-        });
-
-        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
-        // and allows installing the firmware as a typical firmware file.
-        //
-        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
-        microzig.installFirmware(b, firmware, .{});
-
-        // For debugging, we also always install the firmware as an ELF file
-        microzig.installFirmware(b, firmware, .{ .format = .elf });
-    }
-}
-
-const TargetDesc = struct {
-    target: @import("microzig").Target,
-    name: []const u8,
-};
diff --git a/examples/all-platforms/build.zig.zon b/examples/all-platforms/build.zig.zon
deleted file mode 100644
index 5513788d9..000000000
--- a/examples/all-platforms/build.zig.zon
+++ /dev/null
@@ -1,38 +0,0 @@
-.{
-    .name = "microzig-all-platforms-examples",
-    .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
-            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
-        },
-        .rp2040 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/raspberrypi-rp2040/archive/67d36eebb0fbd89633db1a51d6d2bcb049f2066a.tar.gz",
-            .hash = "122094bf268f45b188f3916f9e5964f4257414afaafba98a455ac47d25389a456832",
-        },
-        .stm32 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/stmicro-stm32/archive/cb2893707efa6aa289fa72f02959ad5f2d9db2a1.tar.gz",
-            .hash = "12208cab5f60ef97cac4165ad694f3ba0c7b28f279538c1539b74f7c152f34fe306d",
-        },
-        .lpc = .{
-            .url = "https://github.com/ZigEmbeddedGroup/nxp-lpc/archive/130a1316c0892415e7da958a5e9548ed87bba54d.tar.gz",
-            .hash = "1220165879f85a1d51656d35b3963a95f3585dc665fc7414f76aa6aad4e6635536cf",
-        },
-        .gd32 = .{
-            .url = "https://github.com/ZigEmbeddedGroup/gigadevice-gd32/archive/9324753cc3b8e7afe83fcda085bcfe76681a3be3.tar.gz",
-            .hash = "122043ff4dcbc342f25dbb936b0d9eaa701ac3509e2cbe6764be37b90d31c7a385d0",
-        },
-        .nrf5x = .{
-            .url = "https://github.com/ZigEmbeddedGroup/nordic-nrf5x/archive/0ab136860ccf7eb1d07969c3ef523f3cd898e2ff.tar.gz",
-            .hash = "1220980da06f9634dcff06afefa7aa111bd030018fea49f79e86657dab69621e1d08",
-        },
-        .esp = .{
-            .url = "https://github.com/ZigEmbeddedGroup/espressif-esp/archive/59b8ca028915c0d6224ec88dbf4db19afbb559c0.tar.gz",
-            .hash = "1220f6e5f22416fdc63442cd8869fcaa35f9abf30d878ea3d80073176677dc6f8a65",
-        },
-        .atmega = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microchip-atmega/archive/feefcb87a63c0aae31afb783d4e388e90c4d922f.tar.gz",
-            .hash = "1220048dc5d22729ee119a496f8b8ca3556838af1f3bd32ce6acd5f76480ec942965",
-        },
-    },
-}
diff --git a/examples/all-platforms/src/blinky.zig b/examples/all-platforms/src/blinky.zig
deleted file mode 100644
index 5632fe349..000000000
--- a/examples/all-platforms/src/blinky.zig
+++ /dev/null
@@ -1,20 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-const rp2040 = microzig.hal;
-const time = rp2040.time;
-
-const pin_config = rp2040.pins.GlobalConfiguration{
-    .GPIO25 = .{
-        .name = "led",
-        .direction = .out,
-    },
-};
-
-pub fn main() !void {
-    const pins = pin_config.apply();
-
-    while (true) {
-        pins.led.toggle();
-        time.sleep_ms(250);
-    }
-}
diff --git a/examples/all-platforms/src/empty.zig b/examples/all-platforms/src/empty.zig
deleted file mode 100644
index 7c6dbbe42..000000000
--- a/examples/all-platforms/src/empty.zig
+++ /dev/null
@@ -1,6 +0,0 @@
-const std = @import("std");
-const microzig = @import("microzig");
-
-pub fn main() void {
-    //
-}
diff --git a/examples/build.zig b/examples/build.zig
deleted file mode 100644
index bd3f69f7b..000000000
--- a/examples/build.zig
+++ /dev/null
@@ -1,28 +0,0 @@
-const std = @import("std");
-const MicroZig = @import("../build/build.zig"); // "microzig-build"
-
-pub fn build(b: *std.Build) void {
-    const microzig = MicroZig.createBuildEnvironment(b, .{
-        .self = "microzig", // package name of the build package (optional)
-        .core = "microzig-core", // package name of the core package (optional)
-        .board_support = &.{
-            // package names for BSP packages:
-            "microzig-bsp-nxp",
-            "microzig-bsp-rp2040",
-        },
-    });
-
-    const optimize = b.standardOptimizeOption(.{});
-    const target_name = b.option([]const u8, "target", "Select the target to build for.") orelse "board:mbed/lpc1768";
-
-    const target = microzig.findTarget(target_name).?;
-
-    const firmware = microzig.addFirmware(b, .{
-        .name = "blinky",
-        .target = target,
-        .optimize = optimize,
-        .source_file = .{ .path = "src/empty.zig" },
-    });
-
-    microzig.installFirmware(b, firmware, .{});
-}
diff --git a/examples/microchip-atsam/build.zig b/examples/microchip-atsam/build.zig
new file mode 100644
index 000000000..681cf3731
--- /dev/null
+++ b/examples/microchip-atsam/build.zig
@@ -0,0 +1,45 @@
+const std = @import("std");
+const MicroZig = @import("microzig-build");
+
+const available_examples = [_]Example{
+    .{ .target = "chip:atsamd51j19", .name = "atsamd51j19-blinky", .file = "src/blinky.zig" },
+};
+
+pub fn build(b: *std.Build) void {
+    const microzig = MicroZig.createBuildEnvironment(b, .{});
+    const optimize = b.standardOptimizeOption(.{});
+
+    const show_targets_step = b.step("show-targets", "Shows all available MicroZig targets");
+    show_targets_step.dependOn(microzig.getShowTargetsStep());
+
+    for (available_examples) |example| {
+        const target = microzig.findTarget(example.target).?;
+
+        // `addFirmware` basically works like addExecutable, but takes a
+        // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
+        //
+        // The target will convey all necessary information on the chip,
+        // cpu and potentially the board as well.
+        const firmware = microzig.addFirmware(b, .{
+            .name = example.name,
+            .target = target,
+            .optimize = optimize,
+            .source_file = .{ .path = example.file },
+        });
+
+        // `installFirmware()` is the MicroZig pendant to `Build.installArtifact()`
+        // and allows installing the firmware as a typical firmware file.
+        //
+        // This will also install into `$prefix/firmware` instead of `$prefix/bin`.
+        microzig.installFirmware(b, firmware, .{});
+
+        // For debugging, we also always install the firmware as an ELF file
+        microzig.installFirmware(b, firmware, .{ .format = .elf });
+    }
+}
+
+const Example = struct {
+    target: []const u8,
+    name: []const u8,
+    file: []const u8,
+};
diff --git a/examples/microchip-atsam/microzig-package.json b/examples/microchip-atsam/microzig-package.json
new file mode 100644
index 000000000..b0f787b58
--- /dev/null
+++ b/examples/microchip-atsam/microzig-package.json
@@ -0,0 +1,7 @@
+{
+    "package_name": "microchip/atsam",
+    "package_type": "example",
+    "inner_dependencies": [
+        "microchip/atsam"
+    ]
+}
\ No newline at end of file
diff --git a/examples/next-gen/src/empty.zig b/examples/microchip-atsam/src/blinky.zig
similarity index 58%
rename from examples/next-gen/src/empty.zig
rename to examples/microchip-atsam/src/blinky.zig
index b2925389e..db1529a0a 100644
--- a/examples/next-gen/src/empty.zig
+++ b/examples/microchip-atsam/src/blinky.zig
@@ -2,7 +2,5 @@ const std = @import("std");
 const microzig = @import("microzig");
 
 pub fn main() !void {
-    while (true) {
-        asm volatile ("" ::: "memory");
-    }
+    // TODO: Implement the blinky
 }
diff --git a/examples/next-gen/build.zig b/examples/next-gen/build.zig
deleted file mode 100644
index fe531f970..000000000
--- a/examples/next-gen/build.zig
+++ /dev/null
@@ -1,23 +0,0 @@
-const std = @import("std");
-const MicroZig = @import("microzig-build");
-
-pub fn build(b: *std.Build) void {
-    const microzig = MicroZig.createBuildEnvironment(b, .{});
-
-    const show_targets_step = b.step("show-targets", "Shows all available MicroZig targets");
-    show_targets_step.dependOn(microzig.getShowTargetsStep());
-
-    const optimize = b.standardOptimizeOption(.{});
-    const target_name = b.option([]const u8, "target", "Select the target to build for.") orelse "board:mbed/lpc1768";
-
-    const target = microzig.findTarget(target_name).?;
-
-    const firmware = microzig.addFirmware(b, .{
-        .name = "blinky",
-        .target = target,
-        .optimize = optimize,
-        .source_file = .{ .path = "src/empty.zig" },
-    });
-
-    microzig.installFirmware(b, firmware, .{});
-}
diff --git a/examples/next-gen/build.zig.zon b/examples/next-gen/build.zig.zon
deleted file mode 100644
index 70de7cc6f..000000000
--- a/examples/next-gen/build.zig.zon
+++ /dev/null
@@ -1,22 +0,0 @@
-.{
-    .name = "microzig-nxp-lpc-examples",
-    .version = "0.1.0",
-    .dependencies = .{
-        .@"microzig-build" = .{
-            .url = "https://public.devspace.random-projects.net/packages/microzig-build.tar.gz",
-            .hash = "1220e1f1446176832d84fa9b132022a45ea8c21fbaba8a51d787c6b4e0f1d455f4ed",
-        },
-        .@"microzig-core" = .{
-            .url = "https://public.devspace.random-projects.net/packages/microzig-core.tar.gz",
-            .hash = "12207d2604083d414ff3ca7c31c5dc76ee8ac3f1292a22e40ffe8b87fcadbd2e3c7d",
-        },
-        .@"microzig-bsp-nxp" = .{
-            .url = "https://public.devspace.random-projects.net/packages/board-support/nxp/lpc.tar.gz",
-            .hash = "1220ac0aa694eaa23cda453bb5a2711b22d8f58f10a9e0389502439cbb881987fa95",
-        },
-        .@"microzig-bsp-rp2040" = .{
-            .url = "https://public.devspace.random-projects.net/packages/board-support/raspberrypi/rp2040.tar.gz",
-            .hash = "12204d3998590f27f19aa31a8a250576b4314b29bbeb97628e264b42cb488ee6fad7",
-        },
-    },
-}
\ No newline at end of file
diff --git a/tools/validate-all-examples.sh b/tools/validate-all-examples.sh
index bf50cde70..817ad58d0 100755
--- a/tools/validate-all-examples.sh
+++ b/tools/validate-all-examples.sh
@@ -7,6 +7,8 @@ tmpdir="/tmp/microzig-test"
 
 mkdir -p "${tmpdir}"
 
-"${root}/validate-example.py" --build-root "${tmpdir}" --example raspberrypi/rp2040
-"${root}/validate-example.py" --build-root "${tmpdir}" --example stmicro/stm32
-"${root}/validate-example.py" --build-root "${tmpdir}" --example nxp/lpc
+examples="espressif/esp stmicro/stm32 nordic/nrf5x gigadevice/gd32 raspberrypi/rp2040 nxp/lpc microchip/atsam"
+
+for key in ${examples}; do
+    "${root}/validate-example.py" --build-root "${tmpdir}" --example "$key"
+done

From 1643c30d7deb41e219dc2d4e6acfd933ee8e2f8b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Wed, 7 Feb 2024 10:45:39 +0100
Subject: [PATCH 273/286] Makes AVR example fit, but still crashes compiler

---
 .github/workflows/build.yml                   | 34 +++++++++++++++++++
 build/build.zig                               |  1 +
 core/src/cpus/avr5.zig                        |  4 +--
 examples/microchip-atmega/build.zig.zon       | 14 --------
 .../build.zig                                 | 18 ++++++----
 examples/microchip-avr/microzig-package.json  |  7 ++++
 .../src/blinky.zig                            |  0
 tools/validate-all-examples.sh                |  2 +-
 8 files changed, 57 insertions(+), 23 deletions(-)
 delete mode 100644 examples/microchip-atmega/build.zig.zon
 rename examples/{microchip-atmega => microchip-avr}/build.zig (64%)
 create mode 100644 examples/microchip-avr/microzig-package.json
 rename examples/{microchip-atmega => microchip-avr}/src/blinky.zig (100%)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 5395153b1..b324e859a 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -44,3 +44,37 @@ jobs:
         with:
           name: packages
           path: microzig-deploy/
+  
+  validate-packages:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+        with:
+          fetch-tags: true # required for "git describe"
+
+      - name: Fetch more data from git
+        run: |
+          # fetch everything back till the $(ZIG_VERSION) tag.
+          # https://stackoverflow.com/a/58082274
+          git fetch --shallow-exclude ${{ env.ZIG_VERSION }}
+          git fetch --deepen=2
+
+      - name: Setup Zig
+        uses: goto-bus-stop/setup-zig@v2
+        with:
+          version: ${{ env.ZIG_VERSION }}
+
+      - name: Install PIP packages
+        run: |
+          pip install dataclasses_json==0.6.3 marshmallow typing-inspect semver pathspec
+
+      - name: Generate and validate packages
+        run: |
+          ./tools/bundle.py
+
+      - name: Upload artifacts
+        uses: actions/upload-artifact@v4
+        with:
+          name: packages
+          path: microzig-deploy/
diff --git a/build/build.zig b/build/build.zig
index 7402a7262..38a804955 100644
--- a/build/build.zig
+++ b/build/build.zig
@@ -523,6 +523,7 @@ pub const BuildEnvironment = struct {
         if (options.target.configure) |configure| {
             configure(fw.env, fw);
         }
+        
 
         return fw;
     }
diff --git a/core/src/cpus/avr5.zig b/core/src/cpus/avr5.zig
index 117a70f6f..478a7d3d0 100644
--- a/core/src/cpus/avr5.zig
+++ b/core/src/cpus/avr5.zig
@@ -102,13 +102,13 @@ fn make_isr_handler(comptime name: []const u8, comptime func: anytype) type {
 }
 
 pub const startup_logic = struct {
-    export fn microzig_unhandled_vector() callconv(.Naked) noreturn {
+    export fn microzig_unhandled_vector() callconv(.C) noreturn {
         @panic("Unhandled interrupt");
     }
 
     extern fn microzig_main() noreturn;
 
-    export fn microzig_start() callconv(.Naked) noreturn {
+    export fn microzig_start() callconv(.C) noreturn {
         // At startup the stack pointer is at the end of RAM
         // so, no need to set it manually!
 
diff --git a/examples/microchip-atmega/build.zig.zon b/examples/microchip-atmega/build.zig.zon
deleted file mode 100644
index f3c3bdfc1..000000000
--- a/examples/microchip-atmega/build.zig.zon
+++ /dev/null
@@ -1,14 +0,0 @@
-.{
-    .name = "microzig-microchip-atmega-examples",
-    .version = "0.1.0",
-    .dependencies = .{
-        .microzig = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microzig/archive/c6c9ec4516f57638e751141085c9d76120990312.tar.gz",
-            .hash = "1220af58bdaa721b8189f3a7adfda660517dd354463463388e96d69fe4ceccf80b92",
-        },
-        .atmega = .{
-            .url = "https://github.com/ZigEmbeddedGroup/microchip-atmega/archive/feefcb87a63c0aae31afb783d4e388e90c4d922f.tar.gz",
-            .hash = "1220048dc5d22729ee119a496f8b8ca3556838af1f3bd32ce6acd5f76480ec942965",
-        },
-    },
-}
diff --git a/examples/microchip-atmega/build.zig b/examples/microchip-avr/build.zig
similarity index 64%
rename from examples/microchip-atmega/build.zig
rename to examples/microchip-avr/build.zig
index 6459450dd..b8b5faa15 100644
--- a/examples/microchip-atmega/build.zig
+++ b/examples/microchip-avr/build.zig
@@ -1,15 +1,21 @@
 const std = @import("std");
-const atmega = @import("atmega");
+const MicroZig = @import("microzig-build");
 
 const available_examples = [_]Example{
-    // TODO:    .{ .name = "arduino-nano_blinky", .target = atmega.boards.arduino.nano, .file = "src/blinky.zig" },
+    .{ .target = "board:arduino/nano", .name = "arduino-nano_blinky", .file = "src/blinky.zig" },
+    .{ .target = "board:arduino/uno_rev3", .name = "arduino-nano_blinky", .file = "src/blinky.zig" },
 };
 
 pub fn build(b: *std.Build) void {
-    const microzig = @import("microzig").init(b, "microzig");
-    const optimize = .ReleaseSmall; // The others are not really an option on AVR
+    const microzig = MicroZig.createBuildEnvironment(b, .{});
+    const optimize = b.standardOptimizeOption(.{});
+
+    const show_targets_step = b.step("show-targets", "Shows all available MicroZig targets");
+    show_targets_step.dependOn(microzig.getShowTargetsStep());
 
     for (available_examples) |example| {
+        const target = microzig.findTarget(example.target).?;
+
         // `addFirmware` basically works like addExecutable, but takes a
         // `microzig.Target` for target instead of a `std.zig.CrossTarget`.
         //
@@ -17,7 +23,7 @@ pub fn build(b: *std.Build) void {
         // cpu and potentially the board as well.
         const firmware = microzig.addFirmware(b, .{
             .name = example.name,
-            .target = example.target,
+            .target = target,
             .optimize = optimize,
             .source_file = .{ .path = example.file },
         });
@@ -34,7 +40,7 @@ pub fn build(b: *std.Build) void {
 }
 
 const Example = struct {
-    target: @import("microzig").Target,
+    target: []const u8,
     name: []const u8,
     file: []const u8,
 };
diff --git a/examples/microchip-avr/microzig-package.json b/examples/microchip-avr/microzig-package.json
new file mode 100644
index 000000000..e6eca91a2
--- /dev/null
+++ b/examples/microchip-avr/microzig-package.json
@@ -0,0 +1,7 @@
+{
+    "package_name": "microchip/avr",
+    "package_type": "example",
+    "inner_dependencies": [
+        "microchip/avr"
+    ]
+}
\ No newline at end of file
diff --git a/examples/microchip-atmega/src/blinky.zig b/examples/microchip-avr/src/blinky.zig
similarity index 100%
rename from examples/microchip-atmega/src/blinky.zig
rename to examples/microchip-avr/src/blinky.zig
diff --git a/tools/validate-all-examples.sh b/tools/validate-all-examples.sh
index 817ad58d0..8af432bd4 100755
--- a/tools/validate-all-examples.sh
+++ b/tools/validate-all-examples.sh
@@ -7,7 +7,7 @@ tmpdir="/tmp/microzig-test"
 
 mkdir -p "${tmpdir}"
 
-examples="espressif/esp stmicro/stm32 nordic/nrf5x gigadevice/gd32 raspberrypi/rp2040 nxp/lpc microchip/atsam"
+examples="espressif/esp stmicro/stm32 nordic/nrf5x gigadevice/gd32 raspberrypi/rp2040 nxp/lpc microchip/atsam" # microchip/avr (does not build with 0.11)
 
 for key in ${examples}; do
     "${root}/validate-example.py" --build-root "${tmpdir}" --example "$key"

From a4ac2d1858530e12307a17c409d979df0d76c269 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Wed, 7 Feb 2024 11:03:19 +0100
Subject: [PATCH 274/286] Adds deployment+example test to CI

---
 .github/workflows/build.yml    | 23 +++++++++++++++++------
 tools/bundle.py                | 20 +++++++++++++++++---
 tools/validate-all-examples.sh |  5 +----
 tools/validate-example.py      |  6 +++++-
 4 files changed, 40 insertions(+), 14 deletions(-)

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index b324e859a..929e54d36 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -3,6 +3,7 @@ name: Continuous Integration
 env:
   # Specify the current Zig version MicroZig uses:
   ZIG_VERSION: 0.11.0
+  DEPLOYMENT_URL: "https://download.microzig.tech"
 
 on:
   push:
@@ -69,12 +70,22 @@ jobs:
         run: |
           pip install dataclasses_json==0.6.3 marshmallow typing-inspect semver pathspec
 
-      - name: Generate and validate packages
+      - name: Generate packages
         run: |
-          ./tools/bundle.py
+          ./tools/bundle.py --debug
 
-      - name: Upload artifacts
-        uses: actions/upload-artifact@v4
+      - name: Spawn local web server
+        uses: Eun/http-server-action@v1
         with:
-          name: packages
-          path: microzig-deploy/
+          directory: "${{ github.workspace }}/microzig-deploy"
+          port: 8080
+          content-types: |
+            {
+              "gz": "application/gzip",
+              "json": "application/json"
+            }
+
+      - name: Validate examples
+        run: |
+          mkdir -p "${{ github.workspace }}/microzig-test"
+          ./tools/validate-all-examples.sh --build-root "${{ github.workspace }}/microzig-test"
diff --git a/tools/bundle.py b/tools/bundle.py
index 4e0e2155e..2a4bd50b9 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -14,6 +14,7 @@
 from semver import Version
 from marshmallow import fields
 from enum import Enum as StrEnum
+from argparse import ArgumentParser
 import pathspec
 import stat 
 import tarfile
@@ -26,6 +27,9 @@
 from lib.common import  execute_raw, execute, slurp, check_zig_version, check_required_tools
 import lib.common as common
 
+DEFAULT_DEPLOYMENT_BASE="https://download.microzig.tech/packages"
+DEBUG_DEPLOYMENT_BASE="http://localhost:8080"
+
 LEGAL_PACKAGE_NAME = re.compile("^[A-Za-z]$")
 
 VERBOSE = False 
@@ -34,8 +38,7 @@
     "zig",
     "git",
 ]
-# DEPLOYMENT_BASE="https://download.microzig.tech/packages"
-DEPLOYMENT_BASE="https://public.devspace.random-projects.net"
+
 
 REPO_ROOT = Path(__file__).parent.parent
 assert REPO_ROOT.is_dir()
@@ -230,6 +233,17 @@ def get_batch_timestamp():
 
 def main():
 
+    
+    arg_parser = ArgumentParser()
+
+    arg_parser.add_argument("--base-url", type=str, required=False, default=DEFAULT_DEPLOYMENT_BASE, help="Sets the download URL for the packages.")
+    arg_parser.add_argument("--debug", action="store_true", required=False, default=False, help="Creates a deployment for local development, hosted by localhost:8080")
+
+    cli_args = arg_parser.parse_args()
+
+    base_url = cli_args.base_url if not cli_args.debug else DEBUG_DEPLOYMENT_BASE
+
+
     check_required_tools(REQUIRED_TOOLS)
 
     check_zig_version("0.11.0")
@@ -326,7 +340,7 @@ def main():
             assert False 
 
         download_path = pkg.out_rel_dir / ALL_FILES_DIR / f"{pkg.out_basename}-{version}.tar.gz"
-        pkg.download_url = f"{DEPLOYMENT_BASE}/{download_path}"
+        pkg.download_url = f"{base_url}/{download_path}"
 
         buildzig_path = pkg_dir / "build.zig"
         buildzon_path = pkg_dir / "build.zig.zon"
diff --git a/tools/validate-all-examples.sh b/tools/validate-all-examples.sh
index 8af432bd4..7d0982eb9 100755
--- a/tools/validate-all-examples.sh
+++ b/tools/validate-all-examples.sh
@@ -3,12 +3,9 @@
 set -e 
 
 root="$(dirname "$(realpath "$0")")"
-tmpdir="/tmp/microzig-test"
-
-mkdir -p "${tmpdir}"
 
 examples="espressif/esp stmicro/stm32 nordic/nrf5x gigadevice/gd32 raspberrypi/rp2040 nxp/lpc microchip/atsam" # microchip/avr (does not build with 0.11)
 
 for key in ${examples}; do
-    "${root}/validate-example.py" --build-root "${tmpdir}" --example "$key"
+    "${root}/validate-example.py" --example "$key" "$@"
 done
diff --git a/tools/validate-example.py b/tools/validate-example.py
index d04c8afd0..4b9ab30aa 100755
--- a/tools/validate-example.py
+++ b/tools/validate-example.py
@@ -8,6 +8,7 @@
 import shutil
 
 REQUIRED_TOOLS = ["zig", "curl", "tar", "gunzip"]
+DEBUG_DEPLOYMENT_BASE="http://localhost:8080"
 
 
 def main():
@@ -20,10 +21,13 @@ def main():
 
     parser.add_argument("--example", type=PurePosixPath, required=True)
     parser.add_argument("--build-root", type=Path, required=True)
+    parser.add_argument("--base-url", type=str, required=False, default=DEBUG_DEPLOYMENT_BASE, help="Sets the download URL for the packages.")
+
     args = parser.parse_args()
 
     example_id: PurePosixPath = args.example 
     build_root: Path = args.build_root
+    base_url: str = args.base_url
 
     if len(example_id.parents) != 2 or str(example_id.parents[1]) != ".":
         print(f"example must be /", file=sys.stderr)
@@ -41,7 +45,7 @@ def main():
         "curl",
         "-o",
         f"{example_name}.tar.gz",
-        f"https://public.devspace.random-projects.net/examples/{example_group}/{example_name}.tar.gz",
+        f"{base_url}/examples/{example_group}/{example_name}.tar.gz",
         cwd=build_root,
     )
 

From 7817cdd27ed4b9647d842068b4eff947983c657f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 10 Feb 2024 12:54:06 +0100
Subject: [PATCH 275/286] Implements continous deployment

---
 .github/workflows/deploy.yml | 50 ++++++++++++++++++++++++++++++++++++
 README.md                    |  4 +--
 tools/bundle.py              |  2 +-
 3 files changed, 53 insertions(+), 3 deletions(-)
 create mode 100644 .github/workflows/deploy.yml

diff --git a/.github/workflows/deploy.yml b/.github/workflows/deploy.yml
new file mode 100644
index 000000000..fc174c0f0
--- /dev/null
+++ b/.github/workflows/deploy.yml
@@ -0,0 +1,50 @@
+name: Continuous Deployment
+
+env:
+  # Specify the current Zig version MicroZig uses:
+  ZIG_VERSION: 0.11.0
+
+on:
+  push:
+    branches: [main]
+
+jobs:
+  deploy-packages:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Checkout
+        uses: actions/checkout@v4
+        with:
+          fetch-tags: true # required for "git describe"
+
+      - name: Fetch more data from git
+        run: |
+          # fetch everything back till the $(ZIG_VERSION) tag.
+          # https://stackoverflow.com/a/58082274
+          git fetch --shallow-exclude ${{ env.ZIG_VERSION }}
+          git fetch --deepen=2
+
+      - name: Setup Zig
+        uses: goto-bus-stop/setup-zig@v2
+        with:
+          version: ${{ env.ZIG_VERSION }}
+
+      - name: Install PIP packages
+        run: |
+          pip install dataclasses_json==0.6.3 marshmallow typing-inspect semver pathspec
+
+      - name: Generate and validate packages
+        run: |
+          ./tools/bundle.py --base-url "${{ secrets.DOWNLOADS_URL }}"
+
+      - name: Deploy
+        uses: easingthemes/ssh-deploy@main
+        with:
+          SSH_PRIVATE_KEY: ${{ secrets.DEPLOY_PRIVATE_KEY }}
+          ARGS: "-vzrli"
+          SOURCE: "microzig-deploy/"
+          REMOTE_HOST: ${{ secrets.DEPLOY_HOST }}
+          REMOTE_USER: ${{ secrets.DEPLOY_USER }}
+          REMOTE_PORT: ${{ secrets.DEPLOY_PORT }}
+          TARGET: "."
+    
\ No newline at end of file
diff --git a/README.md b/README.md
index ac6321216..cd6d629d2 100644
--- a/README.md
+++ b/README.md
@@ -4,10 +4,11 @@
 
 ## Overview
 
+- `build/` contains the build components of MicroZig.
 - `core/` contains the shared components of MicroZig.
 - `board-support/` contains all official board support package.
 - `examples/` contains examples that can be used with the board support packages.
-- `tools/` contains tooling to work *on* MicroZig.
+- `tools/` contains tooling to work *on* MicroZig itself, so deployment, testing, ...
 
 ## Versioning Scheme
 
@@ -25,6 +26,5 @@ Consider the version `0.11.0-abcdef-123` means that this MicroZig version has a
 - Integrate https://github.com/ZigEmbeddedGroup/microzig-driver-framework as package
 - Create support for nice GitHub badges
 - validate that the table on https://github.com/ZigEmbeddedGroup is correct (in CI)
-- make system build again properly
 - start porting everything to 0.12/unstable
 - Try to get some autodocs to build.
diff --git a/tools/bundle.py b/tools/bundle.py
index 2a4bd50b9..30805cbaf 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -141,7 +141,7 @@ def file_digest(path: Path, hashfunc) -> bytes:
     stat.S_IFIFO: "fifo",
     stat.S_IFLNK: "link",
     stat.S_IFSOCK: "socket",
-    }
+}
 
 def file_type(path: Path) -> str:
     return FILE_STAT_MAP[stat.S_IFMT( path.stat().st_mode)]

From 37319a93cad3a2cabba5704e4cffe7a229f437d6 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Sat, 10 Feb 2024 13:13:14 +0100
Subject: [PATCH 276/286] Moves some files out of core

---
 README.md                                          |   2 +-
 {core/design => design}/logo-text-auto.svg         |   0
 {core/design => design}/logo-text-brightmode.svg   |   0
 {core/design => design}/logo-text-darkmode.svg     |   0
 {core/design => design}/logo-text-inkscape.svg     |   0
 {core/design => design}/logo.svg                   |   0
 {core/design => design}/social-media-preview.png   | Bin
 {core/design => design}/social-media-preview.xcf   | Bin
 {core/docs => docs}/design.adoc                    |   0
 {core/docs => docs}/hardware_support_packages.adoc |   0
 {core/docs => docs}/images/deps.dot                |   0
 {core/docs => docs}/images/deps.svg                |   0
 {core/docs => docs}/tricks.adoc                    |   0
 13 files changed, 1 insertion(+), 1 deletion(-)
 rename {core/design => design}/logo-text-auto.svg (100%)
 rename {core/design => design}/logo-text-brightmode.svg (100%)
 rename {core/design => design}/logo-text-darkmode.svg (100%)
 rename {core/design => design}/logo-text-inkscape.svg (100%)
 rename {core/design => design}/logo.svg (100%)
 rename {core/design => design}/social-media-preview.png (100%)
 rename {core/design => design}/social-media-preview.xcf (100%)
 rename {core/docs => docs}/design.adoc (100%)
 rename {core/docs => docs}/hardware_support_packages.adoc (100%)
 rename {core/docs => docs}/images/deps.dot (100%)
 rename {core/docs => docs}/images/deps.svg (100%)
 rename {core/docs => docs}/tricks.adoc (100%)

diff --git a/README.md b/README.md
index cd6d629d2..be972eb75 100644
--- a/README.md
+++ b/README.md
@@ -1,4 +1,4 @@
-# MicroZig
+![MicroZig Logo](design/logo-text-auto.svg)
 
 [![Continuous Integration](https://github.com/ZigEmbeddedGroup/microzig-monorepo/actions/workflows/build.yml/badge.svg)](https://github.com/ZigEmbeddedGroup/microzig-monorepo/actions/workflows/build.yml)
 
diff --git a/core/design/logo-text-auto.svg b/design/logo-text-auto.svg
similarity index 100%
rename from core/design/logo-text-auto.svg
rename to design/logo-text-auto.svg
diff --git a/core/design/logo-text-brightmode.svg b/design/logo-text-brightmode.svg
similarity index 100%
rename from core/design/logo-text-brightmode.svg
rename to design/logo-text-brightmode.svg
diff --git a/core/design/logo-text-darkmode.svg b/design/logo-text-darkmode.svg
similarity index 100%
rename from core/design/logo-text-darkmode.svg
rename to design/logo-text-darkmode.svg
diff --git a/core/design/logo-text-inkscape.svg b/design/logo-text-inkscape.svg
similarity index 100%
rename from core/design/logo-text-inkscape.svg
rename to design/logo-text-inkscape.svg
diff --git a/core/design/logo.svg b/design/logo.svg
similarity index 100%
rename from core/design/logo.svg
rename to design/logo.svg
diff --git a/core/design/social-media-preview.png b/design/social-media-preview.png
similarity index 100%
rename from core/design/social-media-preview.png
rename to design/social-media-preview.png
diff --git a/core/design/social-media-preview.xcf b/design/social-media-preview.xcf
similarity index 100%
rename from core/design/social-media-preview.xcf
rename to design/social-media-preview.xcf
diff --git a/core/docs/design.adoc b/docs/design.adoc
similarity index 100%
rename from core/docs/design.adoc
rename to docs/design.adoc
diff --git a/core/docs/hardware_support_packages.adoc b/docs/hardware_support_packages.adoc
similarity index 100%
rename from core/docs/hardware_support_packages.adoc
rename to docs/hardware_support_packages.adoc
diff --git a/core/docs/images/deps.dot b/docs/images/deps.dot
similarity index 100%
rename from core/docs/images/deps.dot
rename to docs/images/deps.dot
diff --git a/core/docs/images/deps.svg b/docs/images/deps.svg
similarity index 100%
rename from core/docs/images/deps.svg
rename to docs/images/deps.svg
diff --git a/core/docs/tricks.adoc b/docs/tricks.adoc
similarity index 100%
rename from core/docs/tricks.adoc
rename to docs/tricks.adoc

From cb45e3309c51ccb0e9dbe9162b1681a382058b3a Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sat, 10 Feb 2024 13:29:43 +0100
Subject: [PATCH 277/286] Update README.md

---
 README.md | 45 ++++++++++++++++++++++++++++++++++++---------
 1 file changed, 36 insertions(+), 9 deletions(-)

diff --git a/README.md b/README.md
index be972eb75..9f594a38b 100644
--- a/README.md
+++ b/README.md
@@ -1,14 +1,48 @@
-![MicroZig Logo](design/logo-text-auto.svg)
+# ![MicroZig Logo](design/logo-text-auto.svg)
 
+[![Chat](https://img.shields.io/discord/824493524413710336.svg?logo=discord)](link=https://discord.gg/ShUWykk38X)
+[![Downloads](https://img.shields.io/badge/Zig_Package-Download-blue)](https://downloads.microzig.tech/)
 [![Continuous Integration](https://github.com/ZigEmbeddedGroup/microzig-monorepo/actions/workflows/build.yml/badge.svg)](https://github.com/ZigEmbeddedGroup/microzig-monorepo/actions/workflows/build.yml)
 
-## Overview
+> **NOTE:** This is in development; breaks in the API are bound to happen.
+
+## What version of Zig to use
+
+0.11.0
+
+## Contributing
+
+Please see the [project page](https://github.com/orgs/ZigEmbeddedGroup/projects/1/views/1), it’s used as a place to brainstorm and organize work in ZEG. There will be issues marked as good first issue or drafts for larger ideas that need scoping/breaking ground on.
+
+## Introduction
+
+This repo contains the infrastructure for getting started in an embedded Zig project; it "gets you to main()". Specifically, it offers:
+
+* a single easy-to-use builder function that:
+  * generates your linker script
+  * sets up packages and startup code
+* generalized interfaces for common devices, such as UART.
+* device drivers for interacting with external hardware
+* an uncomplicated method to define xref:interrupts[interrupts]
+
+## Getting Started
+
+Search for your chip family in [the examples](https://downloads.microzig.tech/examples/) and get the archive.
+
+You can easily get started based on that.
+
+## Design
+
+For MicroZig internals please see the [Design Document](docs/design.adoc).
+
+## Repository structure
 
 - `build/` contains the build components of MicroZig.
 - `core/` contains the shared components of MicroZig.
 - `board-support/` contains all official board support package.
 - `examples/` contains examples that can be used with the board support packages.
 - `tools/` contains tooling to work *on* MicroZig itself, so deployment, testing, ...
+- `design/` contains images and logos
 
 ## Versioning Scheme
 
@@ -21,10 +55,3 @@ As MicroZig sticks to tagged Zig releases, `${zig_version}` will show to which Z
 
 Consider the version `0.11.0-abcdef-123` means that this MicroZig version has a commit starting with `abcdef`, which was the 123rd commit of the version that is compatible with Zig 0.11.0.
 
-## TODO (before exchanging upstream)
-
-- Integrate https://github.com/ZigEmbeddedGroup/microzig-driver-framework as package
-- Create support for nice GitHub badges
-- validate that the table on https://github.com/ZigEmbeddedGroup is correct (in CI)
-- start porting everything to 0.12/unstable
-- Try to get some autodocs to build.

From be113c7adcb80f8a64a3b33b200a8c62b5d9d919 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20=22xq=22=20Quei=C3=9Fner?= 
Date: Fri, 16 Feb 2024 08:57:30 +0100
Subject: [PATCH 278/286] Updates README.md

---
 README.md                | 64 ++++++++++++++++++++++++++++++++++++----
 tools/patch-build-zon.py | 10 ++++---
 2 files changed, 64 insertions(+), 10 deletions(-)

diff --git a/README.md b/README.md
index 9f594a38b..8f2c9bd2d 100644
--- a/README.md
+++ b/README.md
@@ -35,14 +35,66 @@ You can easily get started based on that.
 
 For MicroZig internals please see the [Design Document](docs/design.adoc).
 
+## Developing
+
+Right now, the developer experience is not optimal due to 0.11 not really supporting what we're doing at all.
+
+If you want to test your changes, you gotta to the following:
+
+**Step 1:** Create a deployment for local usage:
+
+```sh-session
+[user@host] microzig-monorepo/ $ python3 ./tools/bundle.py --debug
+preparing environment...
+validating packages...
+loaded packages:
+  * microzig-build
+  * examples:microchip/avr
+  * examples:...
+  * microzig-core
+  * microchip/avr
+  * ...
+resolving inner dependencies...
+creating packages...
+bundling microzig-build...
+bundling microzig-core...
+bundling microchip/avr...
+...
+[user@host] microzig-monorepo/ $ 
+```
+
+This command yields output in `./microzig-deploy` that is meant to be fetched via `http://localhost:8080/`.
+
+**Step 2:** To serve the files on this port, you can start a pre-bundled web server:
+
+```sh-session
+[user@host] microzig-monorepo/ $ python3 ./tools/demo-server.py
+...
+```
+
+This way, you spawn a local HTTP server that will serve `./microzig-deploy` on port 8080 on your machine, and you can then
+start fetching packages from this.
+
+Now you can use curl to fetch the packages, or you can just create a local development project.
+
+**Step 3:** You can use the tool `tools/patch-build-zon.py` to patch/upgrade your development project inplace:
+
+```sh-session
+[user@host] microzig-monorepo/ $ python3 ./tools/patch-build-zon.py /tmp/dev-project
+Updating hash of http://localhost:8080/packages/microzig-build.tar.gz to 12200040a36bbbb2fe09809861f565fcda9a10ec3064d70357aa40ad0a61596c16fb
+Updating hash of http://localhost:8080/packages/microzig-core.tar.gz to 122013a37ce9ac295303f26057c203e722b9ceaefa5b4403fe5a18ab065f03079e7d
+Updating hash of http://localhost:8080/packages/board-support/stmicro/stm32.tar.gz to 12207c278b78c5aeb08cd7889647d7d0d9a359cb28fe68105d2e43f85dabb3865981
+[user@host] microzig-monorepo/ $
+```
+
 ## Repository structure
 
-- `build/` contains the build components of MicroZig.
-- `core/` contains the shared components of MicroZig.
-- `board-support/` contains all official board support package.
-- `examples/` contains examples that can be used with the board support packages.
-- `tools/` contains tooling to work *on* MicroZig itself, so deployment, testing, ...
-- `design/` contains images and logos
+* `build/` contains the build components of MicroZig.
+* `core/` contains the shared components of MicroZig.
+* `board-support/` contains all official board support package.
+* `examples/` contains examples that can be used with the board support packages.
+* `tools/` contains tooling to work *on* MicroZig itself, so deployment, testing, ...
+* `design/` contains images and logos
 
 ## Versioning Scheme
 
diff --git a/tools/patch-build-zon.py b/tools/patch-build-zon.py
index 85cc96264..6cb0ae75d 100755
--- a/tools/patch-build-zon.py
+++ b/tools/patch-build-zon.py
@@ -39,7 +39,7 @@ def main():
         elif stripped.startswith(".hash = \""):
             try:
                 pkg_path = PurePosixPath(last_pkg_url.path)
-                assert pkg_path.suffixes ==  ['.tar', '.gz']
+                assert pkg_path.suffixes[-2:] ==  ['.tar', '.gz']
                 pkg_json_url = urlunparse(
                     # scheme, netloc, url, params, query, fragment
                     (
@@ -58,12 +58,14 @@ def main():
 
                 line_prefix = re.match("^(\s*)", line).group(1)
 
+                print(f"Updating hash of {urlunparse(last_pkg_url)} to {pkg_hash}")
+
                 output_lines.append(f'{line_prefix}.hash = "{pkg_hash}",')
                 last_pkg_url = None 
-                
-
+            except AssertionError:
+                raise 
             except BaseException as ex:
-                print(ex)
+                print(f"error: {type(ex)} {ex}")
                 output_lines.append(line)
         else:
             output_lines.append(line)

From e9859fbab26bf08127ec2bd79d9b36d01050d701 Mon Sep 17 00:00:00 2001
From: Tobias Kohlbau 
Date: Sat, 17 Feb 2024 10:58:29 +0100
Subject: [PATCH 279/286] support bundling only specific boards (#166)

Support bundling only specified boards and skipping
the examples. This speedsup the process in case
the developer is only working on specific boards
at a time. By default every example and every board
are bundled.

Signed-off-by: Tobias Kohlbau 
---
 tools/bundle.py | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

diff --git a/tools/bundle.py b/tools/bundle.py
index 30805cbaf..a70081c03 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -14,7 +14,7 @@
 from semver import Version
 from marshmallow import fields
 from enum import Enum as StrEnum
-from argparse import ArgumentParser
+from argparse import ArgumentParser, BooleanOptionalAction
 import pathspec
 import stat 
 import tarfile
@@ -231,6 +231,9 @@ def get_batch_timestamp():
         iso=render_time.isoformat(),
     )
 
+def list_of_str(arg):
+    return arg.split(',')
+
 def main():
 
     
@@ -238,6 +241,8 @@ def main():
 
     arg_parser.add_argument("--base-url", type=str, required=False, default=DEFAULT_DEPLOYMENT_BASE, help="Sets the download URL for the packages.")
     arg_parser.add_argument("--debug", action="store_true", required=False, default=False, help="Creates a deployment for local development, hosted by localhost:8080")
+    arg_parser.add_argument("--examples", action=BooleanOptionalAction, required=False, default=True, help="Build the examples")
+    arg_parser.add_argument("--boards", type=list_of_str, help='list of boards to build', default=[])
 
     cli_args = arg_parser.parse_args()
 
@@ -296,6 +301,13 @@ def main():
         pkg_dict = json.loads(meta_path.read_bytes())
         pkg = PackageConfigurationSchema.load(pkg_dict)
 
+        # Skip examples or non enabled boards
+        if any([
+            pkg.package_type == PackageType.example and not cli_args.examples,
+            pkg.package_type == PackageType.board_support and cli_args.boards and pkg.package_name not in cli_args.boards
+           ]):
+            continue
+
         pkg.version = version
         pkg.created = batch_timestamp
         pkg.package_dir = pkg_dir
@@ -517,4 +529,4 @@ def main():
 
 
 if __name__ == "__main__":
-    main()
\ No newline at end of file
+    main()

From 829f860b8c1039cd8a8e498f8733d9a83b10fe31 Mon Sep 17 00:00:00 2001
From: Tobias Kohlbau 
Date: Sat, 17 Feb 2024 10:59:34 +0100
Subject: [PATCH 280/286] fix documentation for patch tool (#165)

The patch tool expects the build.zig.zon file as
it's argument not the project folder.

Signed-off-by: Tobias Kohlbau 
---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 8f2c9bd2d..f0c7c1e59 100644
--- a/README.md
+++ b/README.md
@@ -80,7 +80,7 @@ Now you can use curl to fetch the packages, or you can just create a local devel
 **Step 3:** You can use the tool `tools/patch-build-zon.py` to patch/upgrade your development project inplace:
 
 ```sh-session
-[user@host] microzig-monorepo/ $ python3 ./tools/patch-build-zon.py /tmp/dev-project
+[user@host] microzig-monorepo/ $ python3 ./tools/patch-build-zon.py /tmp/dev-project/build.zig.zon
 Updating hash of http://localhost:8080/packages/microzig-build.tar.gz to 12200040a36bbbb2fe09809861f565fcda9a10ec3064d70357aa40ad0a61596c16fb
 Updating hash of http://localhost:8080/packages/microzig-core.tar.gz to 122013a37ce9ac295303f26057c203e722b9ceaefa5b4403fe5a18ab065f03079e7d
 Updating hash of http://localhost:8080/packages/board-support/stmicro/stm32.tar.gz to 12207c278b78c5aeb08cd7889647d7d0d9a359cb28fe68105d2e43f85dabb3865981

From 196bbd8094d0628bf182a583d972ae50b3c4a260 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sat, 17 Feb 2024 12:57:20 +0100
Subject: [PATCH 281/286] Fixes CI Badge in README.md (#164)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

* Fixes CI Badge in README.md

* Removes additional fetching from git

* More work on the CI script

* Adds requirements.txt for tools, fixes CI script even more

---------

Co-authored-by: Felix "xq" Queißner 
---
 .github/workflows/build.yml  | 20 ++++----------------
 .github/workflows/deploy.yml | 10 ++--------
 README.md                    |  2 +-
 tools/bundle.py              |  8 ++++++--
 tools/lib/common.py          |  4 ++--
 tools/requirements.txt       |  5 +++++
 6 files changed, 20 insertions(+), 29 deletions(-)
 create mode 100644 tools/requirements.txt

diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml
index 929e54d36..e00945d40 100644
--- a/.github/workflows/build.yml
+++ b/.github/workflows/build.yml
@@ -19,13 +19,7 @@ jobs:
         uses: actions/checkout@v4
         with:
           fetch-tags: true # required for "git describe"
-
-      - name: Fetch more data from git
-        run: |
-          # fetch everything back till the $(ZIG_VERSION) tag.
-          # https://stackoverflow.com/a/58082274
-          git fetch --shallow-exclude ${{ env.ZIG_VERSION }}
-          git fetch --deepen=2
+          fetch-depth: 0
 
       - name: Setup Zig
         uses: goto-bus-stop/setup-zig@v2
@@ -34,7 +28,7 @@ jobs:
 
       - name: Install PIP packages
         run: |
-          pip install dataclasses_json==0.6.3 marshmallow typing-inspect semver pathspec
+          pip install -r tools/requirements.txt
 
       - name: Generate and validate packages
         run: |
@@ -53,13 +47,7 @@ jobs:
         uses: actions/checkout@v4
         with:
           fetch-tags: true # required for "git describe"
-
-      - name: Fetch more data from git
-        run: |
-          # fetch everything back till the $(ZIG_VERSION) tag.
-          # https://stackoverflow.com/a/58082274
-          git fetch --shallow-exclude ${{ env.ZIG_VERSION }}
-          git fetch --deepen=2
+          fetch-depth: 0
 
       - name: Setup Zig
         uses: goto-bus-stop/setup-zig@v2
@@ -68,7 +56,7 @@ jobs:
 
       - name: Install PIP packages
         run: |
-          pip install dataclasses_json==0.6.3 marshmallow typing-inspect semver pathspec
+          pip install -r tools/requirements.txt
 
       - name: Generate packages
         run: |
diff --git a/.github/workflows/deploy.yml b/.github/workflows/deploy.yml
index fc174c0f0..e2a30df98 100644
--- a/.github/workflows/deploy.yml
+++ b/.github/workflows/deploy.yml
@@ -16,13 +16,7 @@ jobs:
         uses: actions/checkout@v4
         with:
           fetch-tags: true # required for "git describe"
-
-      - name: Fetch more data from git
-        run: |
-          # fetch everything back till the $(ZIG_VERSION) tag.
-          # https://stackoverflow.com/a/58082274
-          git fetch --shallow-exclude ${{ env.ZIG_VERSION }}
-          git fetch --deepen=2
+          fetch-depth: 0
 
       - name: Setup Zig
         uses: goto-bus-stop/setup-zig@v2
@@ -31,7 +25,7 @@ jobs:
 
       - name: Install PIP packages
         run: |
-          pip install dataclasses_json==0.6.3 marshmallow typing-inspect semver pathspec
+          pip install -r tools/requirements.txt
 
       - name: Generate and validate packages
         run: |
diff --git a/README.md b/README.md
index f0c7c1e59..446f20587 100644
--- a/README.md
+++ b/README.md
@@ -2,7 +2,7 @@
 
 [![Chat](https://img.shields.io/discord/824493524413710336.svg?logo=discord)](link=https://discord.gg/ShUWykk38X)
 [![Downloads](https://img.shields.io/badge/Zig_Package-Download-blue)](https://downloads.microzig.tech/)
-[![Continuous Integration](https://github.com/ZigEmbeddedGroup/microzig-monorepo/actions/workflows/build.yml/badge.svg)](https://github.com/ZigEmbeddedGroup/microzig-monorepo/actions/workflows/build.yml)
+[![Continuous Integration](https://github.com/ZigEmbeddedGroup/microzig/actions/workflows/build.yml/badge.svg)](https://github.com/ZigEmbeddedGroup/microzig/actions/workflows/build.yml)
 
 > **NOTE:** This is in development; breaks in the API are bound to happen.
 
diff --git a/tools/bundle.py b/tools/bundle.py
index a70081c03..b4c0d7824 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -38,6 +38,7 @@
     "zig",
     "git",
 ]
+REQUIRED_ZIG_VERSION="0.11.0"
 
 
 REPO_ROOT = Path(__file__).parent.parent
@@ -168,7 +169,10 @@ def build_zig_tools():
 # Determines the correct version:
 def get_version_from_git() -> str:
 
-    raw_git_out = slurp("git", "describe", "--match", "*.*.*", "--tags", "--abbrev=9", cwd=REPO_ROOT).strip().decode()
+    raw_git_out = slurp("git", "describe", "--match", "*.*.*", "--tags", "--abbrev=9", cwd=REPO_ROOT, allow_failure=True).strip().decode()
+    if len(raw_git_out) == 0:
+        print("failed to get version from git, using 'development'", file=sys.stderr)
+        return f"{REQUIRED_ZIG_VERSION}-development"
 
     def render_version(major,minor,patch,counter,hash):
         return f"{major}.{minor}.{patch}-{counter}-{hash}"
@@ -251,7 +255,7 @@ def main():
 
     check_required_tools(REQUIRED_TOOLS)
 
-    check_zig_version("0.11.0")
+    check_zig_version(REQUIRED_ZIG_VERSION)
 
     print("preparing environment...")
 
diff --git a/tools/lib/common.py b/tools/lib/common.py
index 4d72ca906..b0bb984dc 100644
--- a/tools/lib/common.py
+++ b/tools/lib/common.py
@@ -3,14 +3,14 @@
 
 VERBOSE = False
 
-def execute_raw(*args,hide_stderr = False,**kwargs):
+def execute_raw(*args,hide_stderr: bool = False, allow_failure: bool = False, **kwargs):
     args = [ str(f) for f in args]
     if VERBOSE:
         print(*args)
     res = subprocess.run(args, **kwargs, check=False)
     if res.stderr is not None and (not hide_stderr or res.returncode != 0):
         sys.stderr.buffer.write(res.stderr)
-    if res.returncode != 0:
+    if not allow_failure and res.returncode != 0:
         sys.stderr.write(f"command {' '.join(args)} failed with exit code {res.returncode}")
         sys.exit(res.returncode)
     return res 
diff --git a/tools/requirements.txt b/tools/requirements.txt
new file mode 100644
index 000000000..b43b94fad
--- /dev/null
+++ b/tools/requirements.txt
@@ -0,0 +1,5 @@
+dataclasses_json==0.6.3
+marshmallow
+typing-inspect
+semver
+pathspec

From b1cbd1bf34734e640f1cadcdbb9fe9d75833a69a Mon Sep 17 00:00:00 2001
From: Grazfather 
Date: Sun, 18 Feb 2024 03:37:04 -0500
Subject: [PATCH 282/286] hal: dma: Cast channel index in claim_unused_channel
 (#170)

`i` is `usize` but `channel()` expects a `u4`.
---
 board-support/raspberrypi-rp2040/src/hal/dma.zig | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/board-support/raspberrypi-rp2040/src/hal/dma.zig b/board-support/raspberrypi-rp2040/src/hal/dma.zig
index 469966f2a..fcbc3d86e 100644
--- a/board-support/raspberrypi-rp2040/src/hal/dma.zig
+++ b/board-support/raspberrypi-rp2040/src/hal/dma.zig
@@ -26,7 +26,7 @@ pub fn claim_unused_channel() ?Channel {
     for (0..num_channels) |i| {
         if (claimed_channels.get(i)) {
             claimed_channels.set(i, true);
-            return channel(i);
+            return channel(@intCast(i));
         }
     }
 

From 4c44611f2053a25968a227ad1dff8f03baa1d1e3 Mon Sep 17 00:00:00 2001
From: Grazfather 
Date: Sun, 18 Feb 2024 03:38:29 -0500
Subject: [PATCH 283/286] Fix requirements.txt and update README (#172)

---
 README.md              | 12 +++++++++---
 tools/requirements.txt |  2 +-
 2 files changed, 10 insertions(+), 4 deletions(-)

diff --git a/README.md b/README.md
index 446f20587..fab78f107 100644
--- a/README.md
+++ b/README.md
@@ -41,7 +41,13 @@ Right now, the developer experience is not optimal due to 0.11 not really suppor
 
 If you want to test your changes, you gotta to the following:
 
-**Step 1:** Create a deployment for local usage:
+**Step 1:** Install required python pacakges:
+
+```sh-session
+[user@host] microzig-monorepo/ $ pip3 install -r tools/requirements.txt
+```
+
+**Step 2:** Create a deployment for local usage:
 
 ```sh-session
 [user@host] microzig-monorepo/ $ python3 ./tools/bundle.py --debug
@@ -65,7 +71,7 @@ bundling microchip/avr...
 
 This command yields output in `./microzig-deploy` that is meant to be fetched via `http://localhost:8080/`.
 
-**Step 2:** To serve the files on this port, you can start a pre-bundled web server:
+**Step 3:** To serve the files on this port, you can start a pre-bundled web server:
 
 ```sh-session
 [user@host] microzig-monorepo/ $ python3 ./tools/demo-server.py
@@ -77,7 +83,7 @@ start fetching packages from this.
 
 Now you can use curl to fetch the packages, or you can just create a local development project.
 
-**Step 3:** You can use the tool `tools/patch-build-zon.py` to patch/upgrade your development project inplace:
+**Step 4:** You can use the tool `tools/patch-build-zon.py` to patch/upgrade your development project inplace:
 
 ```sh-session
 [user@host] microzig-monorepo/ $ python3 ./tools/patch-build-zon.py /tmp/dev-project/build.zig.zon
diff --git a/tools/requirements.txt b/tools/requirements.txt
index b43b94fad..d0f9080f7 100644
--- a/tools/requirements.txt
+++ b/tools/requirements.txt
@@ -2,4 +2,4 @@ dataclasses_json==0.6.3
 marshmallow
 typing-inspect
 semver
-pathspec
+pathspec>=0.12.0

From 5742d0e4b32beb0ba03719d9a625521f5da512ef Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Felix=20Quei=C3=9Fner?= 
Date: Sun, 18 Feb 2024 13:26:31 +0100
Subject: [PATCH 284/286] Better readme (#173)

* Adds better docs to README.md
* Adds tar, gzip to bundle.py checked dependencies.
* Adds fancy rendering of .data/chip-families.svg in output for embedding.
---
 .gitignore                                    |   1 +
 README.md                                     |  47 +++-
 .../espressif-esp/microzig-package.json       |   6 +-
 tools/bundle.py                               | 219 +++++++++++++++++-
 tools/requirements.txt                        |   6 +-
 5 files changed, 259 insertions(+), 20 deletions(-)

diff --git a/.gitignore b/.gitignore
index 3f1d472a5..ce13a0488 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,3 +6,4 @@ microzig-deploy/
 .lldbinit
 .direnv/
 __pycache__/
+.venv
diff --git a/README.md b/README.md
index fab78f107..1f55fa039 100644
--- a/README.md
+++ b/README.md
@@ -1,6 +1,6 @@
 # ![MicroZig Logo](design/logo-text-auto.svg)
 
-[![Chat](https://img.shields.io/discord/824493524413710336.svg?logo=discord)](link=https://discord.gg/ShUWykk38X)
+[![Chat](https://img.shields.io/discord/824493524413710336.svg?logo=discord)](https://discord.gg/ShUWykk38X)
 [![Downloads](https://img.shields.io/badge/Zig_Package-Download-blue)](https://downloads.microzig.tech/)
 [![Continuous Integration](https://github.com/ZigEmbeddedGroup/microzig/actions/workflows/build.yml/badge.svg)](https://github.com/ZigEmbeddedGroup/microzig/actions/workflows/build.yml)
 
@@ -10,10 +10,28 @@
 
 0.11.0
 
-## Contributing
+## Getting Started With MicroZig
+
+### I Want To Use MicroZig
+
+**IMPORTANT:** You don't have to clone this repository to get started!
+
+MicroZig uses a monorepo architecture, but provides a lot of different packages. If you just want to get started, head over to [downloads.microzig.tech](https://downloads.microzig.tech/) and download an example for the chip family you desire.
+
+We support several chip families like the [RP2 family by RaspberryPi Foundation](https://www.raspberrypi.com/products/rp2040/), [STM32 by STMicroelectronics](https://www.st.com/content/st_com/en.html), and many others.
+
+Unpack the example, and run `zig build` in the resulting example folder gives you `zig-out/firmware` which contains the resulting files.
+
+Right now, you gotta figure out how to flash the MCU yourself, but as people say: Google is your friend. But you can also ask for help [on our Discord server](https://discord.gg/ShUWykk38X).
+
+### I Want To Contribute To MicroZig
+
+**IMPORTANT:** Developer experience is degraded right now, and not really good. Windows isn't really a supported dev target and you got to expect some friction. [There's a project for improving DX, feel free to grab tasks from there!](https://github.com/orgs/ZigEmbeddedGroup/projects/4)
 
 Please see the [project page](https://github.com/orgs/ZigEmbeddedGroup/projects/1/views/1), it’s used as a place to brainstorm and organize work in ZEG. There will be issues marked as good first issue or drafts for larger ideas that need scoping/breaking ground on.
 
+More words on contribution and development on MicroZig are [further down below](#developing).
+
 ## Introduction
 
 This repo contains the infrastructure for getting started in an embedded Zig project; it "gets you to main()". Specifically, it offers:
@@ -25,12 +43,6 @@ This repo contains the infrastructure for getting started in an embedded Zig pro
 * device drivers for interacting with external hardware
 * an uncomplicated method to define xref:interrupts[interrupts]
 
-## Getting Started
-
-Search for your chip family in [the examples](https://downloads.microzig.tech/examples/) and get the archive.
-
-You can easily get started based on that.
-
 ## Design
 
 For MicroZig internals please see the [Design Document](docs/design.adoc).
@@ -41,10 +53,19 @@ Right now, the developer experience is not optimal due to 0.11 not really suppor
 
 If you want to test your changes, you gotta to the following:
 
-**Step 1:** Install required python pacakges:
+**Step 1:** Install required python packages, either systemwide or via a [virtual environment](https://docs.python.org/3/library/venv.html):
 
 ```sh-session
+# systemwide:
+[user@host] microzig-monorepo/ $ pip install -r tools/requirements.txt
+[user@host] microzig-monorepo/ $ 
+
+# using virtual environments:
+[user@host] microzig-monorepo/ $ python3 -m venv .venv
+[user@host] microzig-monorepo/ $ . .venv/bin/activate # on linux, macos
+[user@host] microzig-monorepo/ $ . .venv/Scripts/activate # on windows
 [user@host] microzig-monorepo/ $ pip3 install -r tools/requirements.txt
+[user@host] microzig-monorepo/ $ 
 ```
 
 **Step 2:** Create a deployment for local usage:
@@ -83,7 +104,11 @@ start fetching packages from this.
 
 Now you can use curl to fetch the packages, or you can just create a local development project.
 
-**Step 4:** You can use the tool `tools/patch-build-zon.py` to patch/upgrade your development project inplace:
+**Step 4:** Create a local test environment
+
+This is basically done by unpacking an example from the `./microzig-deploy/examples` folder, and starting to test changes.
+As the `build.zig.zon` has to be updated after running `./tools/bundle.py` again, there's a script that helps here:
+`tools/patch-build-zon.py` can be used to patch/upgrade your development project inplace based on what it finds in `./microzig-deploy`:
 
 ```sh-session
 [user@host] microzig-monorepo/ $ python3 ./tools/patch-build-zon.py /tmp/dev-project/build.zig.zon
@@ -93,6 +118,8 @@ Updating hash of http://localhost:8080/packages/board-support/stmicro/stm32.tar.
 [user@host] microzig-monorepo/ $
 ```
 
+Both compiling the local example and updating the `build.zig.zon` requires running the local development server.
+
 ## Repository structure
 
 * `build/` contains the build components of MicroZig.
diff --git a/board-support/espressif-esp/microzig-package.json b/board-support/espressif-esp/microzig-package.json
index e38c47137..2d868c2f3 100644
--- a/board-support/espressif-esp/microzig-package.json
+++ b/board-support/espressif-esp/microzig-package.json
@@ -1,4 +1,4 @@
 {
-  "package_name": "espressif/esp",
-  "package_type": "board-support"
-}
+    "package_name": "espressif/esp",
+    "package_type": "board-support"
+}
\ No newline at end of file
diff --git a/tools/bundle.py b/tools/bundle.py
index b4c0d7824..e7e7ead46 100755
--- a/tools/bundle.py
+++ b/tools/bundle.py
@@ -7,7 +7,7 @@
 #
 
 
-import sys, os, datetime, re, shutil, json, hashlib
+import io, sys, os, datetime, re, shutil, json, hashlib, html 
 from pathlib import Path, PurePosixPath
 from dataclasses import dataclass, field 
 from dataclasses_json import dataclass_json, config as  dcj_config, Exclude as JsonExclude
@@ -37,6 +37,8 @@
 REQUIRED_TOOLS = [
     "zig",
     "git",
+    "tar",
+    "gzip",
 ]
 REQUIRED_ZIG_VERSION="0.11.0"
 
@@ -94,7 +96,7 @@ class PackageConfiguration:
 
     download_url: Optional[str] = field(default=None)
 
-    microzig: Optional[Any] = field(default=None)
+    microzig: Optional[Any] = field(default=None) # optional configuration field with microzig-specific options
 
     # inner fields:
     # package_dir: Path = field(default=None, metadata = dcj_config(exclude=JsonExclude.ALWAYS))
@@ -259,7 +261,7 @@ def main():
 
     print("preparing environment...")
 
-    deploy_target = create_output_directory(REPO_ROOT)    
+    deploy_target = create_output_directory(REPO_ROOT)
 
     # Some generic meta information:
     batch_timestamp = get_batch_timestamp()
@@ -276,6 +278,9 @@ def main():
     cache_dir = cache_root / "microzig"
     cache_dir.mkdir(exist_ok=True)
 
+    detail_files_dir = deploy_target / ALL_FILES_DIR
+    detail_files_dir.mkdir(exist_ok=True)
+
     # Prepare `.gitignore` pattern matcher:
     global_ignore_spec = pathspec.PathSpec.from_lines(
         pathspec.patterns.GitWildMatchPattern, 
@@ -528,9 +533,215 @@ def main():
     with (deploy_target / "index.json").open("w") as f:
         f.write(PackageIndexSchema.dumps(index))
 
-    # TODO: Verify that each package can be unpacked and built
 
+    with (detail_files_dir / "chip-families.svg").open("w") as f:
+        ICON_YES = TableIcon(
+            glyph="✅",
+            path="M10,17L5,12L6.41,10.58L10,14.17L17.59,6.58L19,8M19,3H5C3.89,3 3,3.89 3,5V19A2,2 0 0,0 5,21H19A2,2 0 0,0 21,19V5C21,3.89 20.1,3 19,3Z",
+            color="#0f0",
+        )
+        ICON_NO = TableIcon(
+            glyph="❌",
+            path="M19,6.41L17.59,5L12,10.59L6.41,5L5,6.41L10.59,12L5,17.59L6.41,19L12,13.41L17.59,19L19,17.59L13.41,12L19,6.41Z",
+            color="#f44336",
+        )
+        ICON_WIP = TableIcon(
+            glyph="🛠",
+            path="M13.78 15.3L19.78 21.3L21.89 19.14L15.89 13.14L13.78 15.3M17.5 10.1C17.11 10.1 16.69 10.05 16.36 9.91L4.97 21.25L2.86 19.14L10.27 11.74L8.5 9.96L7.78 10.66L6.33 9.25V12.11L5.63 12.81L2.11 9.25L2.81 8.55H5.62L4.22 7.14L7.78 3.58C8.95 2.41 10.83 2.41 12 3.58L9.89 5.74L11.3 7.14L10.59 7.85L12.38 9.63L14.2 7.75C14.06 7.42 14 7 14 6.63C14 4.66 15.56 3.11 17.5 3.11C18.09 3.11 18.61 3.25 19.08 3.53L16.41 6.2L17.91 7.7L20.58 5.03C20.86 5.5 21 6 21 6.63C21 8.55 19.45 10.1 17.5 10.1Z",
+            color="#82aec0",
+        )
+        ICON_EXPERIMENTAL = TableIcon(
+            glyph="🧪",
+            path="M7,2V4H8V18A4,4 0 0,0 12,22A4,4 0 0,0 16,18V4H17V2H7M11,16C10.4,16 10,15.6 10,15C10,14.4 10.4,14 11,14C11.6,14 12,14.4 12,15C12,15.6 11.6,16 11,16M13,12C12.4,12 12,11.6 12,11C12,10.4 12.4,10 13,10C13.6,10 14,10.4 14,11C14,11.6 13.6,12 13,12M14,7H10V4H14V7Z",
+            color="#2ac9b4"
+        )
+        ICON_UNKNOWN = TableIcon(
+            glyph="❓",
+            path="M10,19H13V22H10V19M12,2C17.35,2.22 19.68,7.62 16.5,11.67C15.67,12.67 14.33,13.33 13.67,14.17C13,15 13,16 13,17H10C10,15.33 10,13.92 10.67,12.92C11.33,11.92 12.67,11.33 13.5,10.67C15.92,8.43 15.32,5.26 12,5A3,3 0 0,0 9,8H6A6,6 0 0,1 12,2Z",
+            color="#ed4034"
+        )
+        
+        def bsp_info(bsp: PackageConfiguration):
+
+            targets = bsp.microzig["board-support"]["targets"]
+
+            num_chips = len([
+                1
+                for tgt
+                in targets
+                if tgt["board"] is None
+            ])
+            num_boards = len(targets) - num_chips
+
+            any_hal = any(
+                tgt["features"]["hal"]
+                for tgt
+                in targets
+            )
+
+            all_hal = all(
+                tgt["features"]["hal"]
+                for tgt
+                in targets
+            )
 
+            hal_support = ICON_NO
+            if all_hal:
+                hal_support = ICON_YES
+            elif any_hal:
+                hal_support = ICON_WIP
+
+            examples = packages.get(f"examples:{bsp.package_name}", None)
+
+
+            return [
+                bsp.package_name, # Chip Family
+                num_chips,  # Chips
+                num_boards,  # Boards
+                hal_support,  # HAL
+                TableLink(href=f"https://downloads.microzig.tech/examples/{bsp.package_name}.tar.gz", content="Download") if examples is not None else "", # Examples
+            ]
+
+        render_table(
+            target=f,
+            columns=[
+                TableColumn(title="Chip Family", width=200),
+                TableColumn(title="Chips", width=70),
+                TableColumn(title="Boards", width=70),
+                TableColumn(title="HAL", width=50),
+                TableColumn(title="Examples", width=100),
+                # TableColumn(title="Abstractions", width=120),
+            ],
+            rows = [
+                bsp_info(bsp)
+                for key, bsp
+                in sorted(packages.items())
+                if bsp.package_type == PackageType.board_support
+            ],
+        ) 
+
+@dataclass
+class TableLink:
+    href: str
+    content: any
+
+@dataclass
+class TableIcon:
+    glyph: str
+    path: str
+    color: str = field(default="#fff")
+
+@dataclass
+class TableColumn:
+    title: str
+    width: int
+
+def render_table(target: io.IOBase, columns: list[TableColumn], rows: list[list[str]]):
+
+    cell_height = 25
+
+    total_width = sum(col.width for col in columns)
+    total_height = cell_height * (1 + len(rows))
+
+    target.write('')
+    target.write('')
+    target.write("""""")
+    target.write('')
+
+    x = 0
+    y = 0
+
+    def valueout(content: any):
+
+        if isinstance(content, TableLink):
+            target.write(f'')
+            valueout(content.content)
+            target.write('')
+        elif isinstance(content, TableIcon):
+            target.write(content.glyph)
+        else:
+            target.write(html.escape(str(content)))
+
+    def cellout(col: TableColumn, content: any, is_heading: bool = False):
+        nonlocal x, y 
+        
+        target.write('')
+
+        target.write('')
+        valueout(content)
+        target.write("")
+
+        x += col.width
+
+    def endrow():
+        nonlocal x, y
+        x = 0
+        y += cell_height
+
+    for col in columns:
+        cellout(col, col.title, is_heading=True)
+    endrow()
+
+    for row in rows:
+
+        for col, cell in zip(columns, row):
+            cellout(col, cell)
+        endrow()
+
+    target.write("""  
+
+""")
 
 if __name__ == "__main__":
     main()
diff --git a/tools/requirements.txt b/tools/requirements.txt
index d0f9080f7..a284c5b36 100644
--- a/tools/requirements.txt
+++ b/tools/requirements.txt
@@ -1,5 +1,5 @@
 dataclasses_json==0.6.3
-marshmallow
-typing-inspect
-semver
+marshmallow>=3.20.0
+typing-inspect>=0.9.0
+semver>=3.0.0
 pathspec>=0.12.0

From a7ff8ed32ba8b80dc131ad2a7fe602704b04b3f1 Mon Sep 17 00:00:00 2001
From: Grazfather 
Date: Fri, 23 Feb 2024 13:06:28 -0500
Subject: [PATCH 285/286] rp2040: Fix DMA not respecting transfer_size_bytes
 (#176)

---
 board-support/raspberrypi-rp2040/src/hal/dma.zig | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/board-support/raspberrypi-rp2040/src/hal/dma.zig b/board-support/raspberrypi-rp2040/src/hal/dma.zig
index fcbc3d86e..b7f962940 100644
--- a/board-support/raspberrypi-rp2040/src/hal/dma.zig
+++ b/board-support/raspberrypi-rp2040/src/hal/dma.zig
@@ -107,7 +107,12 @@ pub const Channel = enum(u4) {
         regs.ctrl_trig.modify(.{
             .EN = @intFromBool(config.enable),
             .DATA_SIZE = .{
-                .value = .SIZE_BYTE,
+                .value = switch (config.transfer_size_bytes) {
+                    1 => @TypeOf(regs.ctrl_trig.read().DATA_SIZE.value).SIZE_BYTE,
+                    2 => .SIZE_HALFWORD,
+                    4 => .SIZE_WORD,
+                    else => unreachable,
+                },
             },
             .INCR_READ = @intFromBool(config.read_increment),
             .INCR_WRITE = @intFromBool(config.write_increment),

From 245401a0cad216f116a47af3d83316a444aecb92 Mon Sep 17 00:00:00 2001
From: Grazfather 
Date: Fri, 23 Feb 2024 17:33:43 -0500
Subject: [PATCH 286/286] wip: rp2040: Add support for PIO's jmp_pin (#174)

This field is a bit tricky: It belongs to the EXECCTRL register, while
most of the other fields can determined based on the directives used in
the assembled program, this one has to be set explicitly. This makes it
so that we have to plumb some way to explicitly set the field. I did
this by making `LoadAndStartProgramOptions` take `ExecOptions`, but this
isn't perfect, because if a user sets other fields, they will be ignored
in favour of the values set in the program.
---
 board-support/raspberrypi-rp2040/src/hal/pio.zig | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/board-support/raspberrypi-rp2040/src/hal/pio.zig b/board-support/raspberrypi-rp2040/src/hal/pio.zig
index 9472728d2..473f5f2ec 100644
--- a/board-support/raspberrypi-rp2040/src/hal/pio.zig
+++ b/board-support/raspberrypi-rp2040/src/hal/pio.zig
@@ -83,6 +83,7 @@ pub const ClkDivOptions = struct {
 };
 
 pub const ExecOptions = struct {
+    jmp_pin: u5 = 0,
     wrap: u5 = 31,
     wrap_target: u5 = 0,
     side_pindir: bool = false,
@@ -132,6 +133,7 @@ pub const LoadAndStartProgramOptions = struct {
     clkdiv: ClkDivOptions,
     shift: ShiftOptions = .{},
     pin_mappings: PinMappingOptions = .{},
+    exec: ExecOptions = .{},
 };
 
 pub const Pio = enum(u1) {
@@ -254,10 +256,12 @@ pub const Pio = enum(u1) {
     pub fn sm_set_exec_options(self: Pio, sm: StateMachine, options: ExecOptions) void {
         const sm_regs = self.get_sm_regs(sm);
         sm_regs.execctrl.modify(.{
+            // NOTE: EXEC_STALLED is RO
             .WRAP_BOTTOM = options.wrap_target,
             .WRAP_TOP = options.wrap,
             .SIDE_PINDIR = @intFromBool(options.side_pindir),
             .SIDE_EN = @intFromBool(options.side_set_optional),
+            .JMP_PIN = options.jmp_pin,
 
             // TODO: plug in rest of the options
             // STATUS_N
@@ -265,7 +269,6 @@ pub const Pio = enum(u1) {
             // OUT_STICKY
             // INLINE_OUT_EN
             // OUT_EN_SEL
-            // JMP_PIN
             // EXEC_STALLED
         });
     }
@@ -514,6 +517,8 @@ pub const Pio = enum(u1) {
                     side_set.optional
                 else
                     false,
+
+                .jmp_pin = options.exec.jmp_pin,
             },
         });
     }

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